commit 7cdb441af6a21dcb62db5df5df25888952ab0175
Author: Martin Vladic <martin.vladic@gmail.com>
Date:   Wed Jul 6 17:22:50 2022 +0200

    init

diff --git a/.cproject b/.cproject
new file mode 100644
index 0000000..8c9d092
--- /dev/null
+++ b/.cproject
@@ -0,0 +1,272 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
+	<storageModule moduleId="org.eclipse.cdt.core.settings">
+		<cconfiguration id="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.debug.460065682">
+			<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.debug.460065682" moduleId="org.eclipse.cdt.core.settings" name="Debug">
+				<externalSettings/>
+				<extensions>
+					<extension id="org.eclipse.cdt.core.ELF" point="org.eclipse.cdt.core.BinaryParser"/>
+					<extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+				</extensions>
+			</storageModule>
+			<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+				<configuration artifactExtension="elf" artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe,org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.debug" cleanCommand="rm -rf" description="" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.debug.460065682" name="Debug" parent="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.debug">
+					<folderInfo id="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.debug.460065682." name="/" resourcePath="">
+						<toolChain id="com.st.stm32cube.ide.mcu.gnu.managedbuild.toolchain.exe.debug.1828784752" name="MCU ARM GCC" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.toolchain.exe.debug">
+							<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_mcu.1527339935" name="MCU" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_mcu" useByScannerDiscovery="true" value="STM32F469NIHx" valueType="string"/>
+							<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_cpuid.48540806" name="CPU" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_cpuid" useByScannerDiscovery="false" value="0" valueType="string"/>
+							<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_coreid.25256515" name="Core" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_coreid" useByScannerDiscovery="false" value="0" valueType="string"/>
+							<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.fpu.540523005" name="Floating-point unit" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.fpu" useByScannerDiscovery="true" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.fpu.value.fpv4-sp-d16" valueType="enumerated"/>
+							<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.floatabi.1004578780" name="Floating-point ABI" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.floatabi" useByScannerDiscovery="true" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.floatabi.value.hard" valueType="enumerated"/>
+							<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_board.1428482885" name="Board" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_board" useByScannerDiscovery="false" value="STM32F469I-DISCO" valueType="string"/>
+							<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.defaults.992922296" name="Defaults" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.defaults" useByScannerDiscovery="false" value="com.st.stm32cube.ide.common.services.build.inputs.revA.1.0.5 || Debug || true || Executable || com.st.stm32cube.ide.mcu.gnu.managedbuild.option.toolchain.value.workspace || STM32F469I-DISCO || 0 || 0 || arm-none-eabi- || ${gnu_tools_for_stm32_compiler_path} || ../FATFS/App | ../USB_HOST/App | ../Middlewares/Third_Party/FreeRTOS/Source/include | ../Drivers/STM32F4xx_HAL_Driver/Inc | ../Drivers/CMSIS/Device/ST/STM32F4xx/Include | ../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2 | ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy | ../Middlewares/ST/STM32_USB_Host_Library/Core/Inc | ../Middlewares/ST/STM32_USB_Host_Library/Class/CDC/Inc | ../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F | ../Drivers/CMSIS/Include | ../Core/Inc | ../FATFS/Target | ../USB_HOST/Target | ../Middlewares/Third_Party/FatFs/src ||  ||  || USE_HAL_DRIVER | STM32F469xx ||  || Drivers | USB_HOST | Core/Startup | Middlewares | Core | FATFS ||  ||  || ${workspace_loc:/${ProjName}/STM32F469NIHX_FLASH.ld} || true || NonSecure ||  || secure_nsclib.o ||  || None || " valueType="string"/>
+							<targetPlatform archList="all" binaryParser="org.eclipse.cdt.core.ELF" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.targetplatform.940103679" isAbstract="false" osList="all" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.targetplatform"/>
+							<builder buildPath="${workspace_loc:/eez-flow-template-stm32f469i-disco}/Debug" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.builder.1381519550" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="Gnu Make Builder" parallelBuildOn="true" parallelizationNumber="optimal" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.builder"/>
+							<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.1508774904" name="MCU GCC Assembler" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler">
+								<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.option.debuglevel.420577669" name="Debug level" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.option.debuglevel" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.option.debuglevel.value.g3" valueType="enumerated"/>
+								<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.option.definedsymbols.2090615990" name="Define symbols (-D)" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.option.definedsymbols" valueType="definedSymbols">
+									<listOptionValue builtIn="false" value="DEBUG"/>
+								</option>
+								<inputType id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.input.1062565987" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.input"/>
+							</tool>
+							<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.312266454" name="MCU GCC Compiler" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler">
+								<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.debuglevel.1695697071" name="Debug level" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.debuglevel" useByScannerDiscovery="false" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.debuglevel.value.g3" valueType="enumerated"/>
+								<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.optimization.level.693135146" name="Optimization level" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.optimization.level" useByScannerDiscovery="false"/>
+								<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.definedsymbols.2052235859" name="Define symbols (-D)" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.definedsymbols" useByScannerDiscovery="false" valueType="definedSymbols">
+									<listOptionValue builtIn="false" value="DEBUG"/>
+									<listOptionValue builtIn="false" value="USE_HAL_DRIVER"/>
+									<listOptionValue builtIn="false" value="STM32F469xx"/>
+									<listOptionValue builtIn="false" value="USE_STM32469I_DISCO_REVB"/>
+									<listOptionValue builtIn="false" value="EEZ_PLATFORM_STM32"/>
+									<listOptionValue builtIn="false" value="LZ4_FORCE_MEMORY_ACCESS=0"/>
+								</option>
+								<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.includepaths.123567366" name="Include paths (-I)" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.includepaths" useByScannerDiscovery="false" valueType="includePath">
+									<listOptionValue builtIn="false" value="../Core/Inc"/>
+									<listOptionValue builtIn="false" value="../FATFS/Target"/>
+									<listOptionValue builtIn="false" value="../FATFS/App"/>
+									<listOptionValue builtIn="false" value="../USB_HOST/App"/>
+									<listOptionValue builtIn="false" value="../USB_HOST/Target"/>
+									<listOptionValue builtIn="false" value="../Drivers/STM32F4xx_HAL_Driver/Inc"/>
+									<listOptionValue builtIn="false" value="../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy"/>
+									<listOptionValue builtIn="false" value="../Middlewares/Third_Party/FreeRTOS/Source/include"/>
+									<listOptionValue builtIn="false" value="../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F"/>
+									<listOptionValue builtIn="false" value="../Middlewares/Third_Party/FatFs/src"/>
+									<listOptionValue builtIn="false" value="../Middlewares/ST/STM32_USB_Host_Library/Core/Inc"/>
+									<listOptionValue builtIn="false" value="../Middlewares/ST/STM32_USB_Host_Library/Class/CDC/Inc"/>
+									<listOptionValue builtIn="false" value="../Drivers/CMSIS/Device/ST/STM32F4xx/Include"/>
+									<listOptionValue builtIn="false" value="../Drivers/CMSIS/Include"/>
+									<listOptionValue builtIn="false" value="../Drivers/BSP/STM32469I-Discovery"/>
+									<listOptionValue builtIn="false" value="../Drivers/BSP/Components/Common"/>
+									<listOptionValue builtIn="false" value="../Utilities/CPU"/>
+									<listOptionValue builtIn="false" value="../Utilities/Log"/>
+									<listOptionValue builtIn="false" value="../Src/conf"/>
+									<listOptionValue builtIn="false" value="../Middlewares"/>
+									<listOptionValue builtIn="false" value="../Middlewares/eez/libs/agg"/>
+									<listOptionValue builtIn="false" value="../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2"/>
+								</option>
+								<inputType id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.input.c.801324572" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.input.c"/>
+							</tool>
+							<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.1825023861" name="MCU G++ Compiler" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler">
+								<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.option.debuglevel.340047260" name="Debug level" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.option.debuglevel" useByScannerDiscovery="false" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.option.debuglevel.value.g3" valueType="enumerated"/>
+								<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.option.optimization.level.1337055648" name="Optimization level" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.option.optimization.level" useByScannerDiscovery="false"/>
+								<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.option.definedsymbols.1035648377" name="Define symbols (-D)" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.option.definedsymbols" useByScannerDiscovery="false" valueType="definedSymbols">
+									<listOptionValue builtIn="false" value="DEBUG"/>
+									<listOptionValue builtIn="false" value="USE_HAL_DRIVER"/>
+									<listOptionValue builtIn="false" value="STM32F469xx"/>
+									<listOptionValue builtIn="false" value="USE_STM32469I_DISCO_REVB"/>
+									<listOptionValue builtIn="false" value="EEZ_PLATFORM_STM32"/>
+									<listOptionValue builtIn="false" value="LZ4_FORCE_MEMORY_ACCESS=0"/>
+								</option>
+								<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.option.includepaths.1521980530" name="Include paths (-I)" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.option.includepaths" useByScannerDiscovery="false" valueType="includePath">
+									<listOptionValue builtIn="false" value="../Core/Inc"/>
+									<listOptionValue builtIn="false" value="../FATFS/Target"/>
+									<listOptionValue builtIn="false" value="../FATFS/App"/>
+									<listOptionValue builtIn="false" value="../USB_HOST/App"/>
+									<listOptionValue builtIn="false" value="../USB_HOST/Target"/>
+									<listOptionValue builtIn="false" value="../Drivers/STM32F4xx_HAL_Driver/Inc"/>
+									<listOptionValue builtIn="false" value="../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy"/>
+									<listOptionValue builtIn="false" value="../Middlewares/Third_Party/FreeRTOS/Source/include"/>
+									<listOptionValue builtIn="false" value="../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F"/>
+									<listOptionValue builtIn="false" value="../Middlewares/Third_Party/FatFs/src"/>
+									<listOptionValue builtIn="false" value="../Middlewares/ST/STM32_USB_Host_Library/Core/Inc"/>
+									<listOptionValue builtIn="false" value="../Middlewares/ST/STM32_USB_Host_Library/Class/CDC/Inc"/>
+									<listOptionValue builtIn="false" value="../Drivers/CMSIS/Device/ST/STM32F4xx/Include"/>
+									<listOptionValue builtIn="false" value="../Drivers/CMSIS/Include"/>
+									<listOptionValue builtIn="false" value="../Drivers/BSP/STM32469I-Discovery"/>
+									<listOptionValue builtIn="false" value="../Drivers/BSP/Components/Common"/>
+									<listOptionValue builtIn="false" value="../Utilities/CPU"/>
+									<listOptionValue builtIn="false" value="../Utilities/Log"/>
+									<listOptionValue builtIn="false" value="../Src/conf"/>
+									<listOptionValue builtIn="false" value="../Middlewares"/>
+									<listOptionValue builtIn="false" value="../Middlewares/eez/libs/agg"/>
+									<listOptionValue builtIn="false" value="../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2"/>
+								</option>
+								<inputType id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.input.cpp.1771274810" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.input.cpp"/>
+							</tool>
+							<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.linker.1885412948" name="MCU GCC Linker" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.linker"/>
+							<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.linker.1261659320" name="MCU G++ Linker" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.linker">
+								<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.linker.option.script.54722534" name="Linker Script (-T)" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.linker.option.script" value="${workspace_loc:/${ProjName}/STM32F469NIHX_FLASH.ld}" valueType="string"/>
+								<inputType id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.linker.input.67527135" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.linker.input">
+									<additionalInput kind="additionalinputdependency" paths="$(USER_OBJS)"/>
+									<additionalInput kind="additionalinput" paths="$(LIBS)"/>
+								</inputType>
+							</tool>
+							<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.archiver.435637738" name="MCU GCC Archiver" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.archiver"/>
+							<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.size.307560726" name="MCU Size" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.size"/>
+							<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objdump.listfile.552578781" name="MCU Output Converter list file" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objdump.listfile"/>
+							<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.hex.723982269" name="MCU Output Converter Hex" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.hex"/>
+							<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.binary.1744086731" name="MCU Output Converter Binary" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.binary"/>
+							<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.verilog.199907884" name="MCU Output Converter Verilog" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.verilog"/>
+							<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.srec.1615684565" name="MCU Output Converter Motorola S-rec" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.srec"/>
+							<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.symbolsrec.913675658" name="MCU Output Converter Motorola S-rec with symbols" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.symbolsrec"/>
+						</toolChain>
+					</folderInfo>
+					<sourceEntries>
+						<entry excluding="eez/libs/libscpi|eez/fs/simulator|eez/platform/simulator" flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="Middlewares"/>
+						<entry excluding="Fonts|Log|CPU" flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="Utilities"/>
+						<entry excluding="Src/my_system_stm32f4xx.c|Src/my_stm32f4xx_it.c|Src/my_stm32f4xx_hal_msp.c" flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="Core"/>
+						<entry excluding="BSP/STM32469I-Discovery/stm32469i_discovery_sd.c|BSP/STM32469I-Discovery/stm32469i_discovery_audio.c" flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="Drivers"/>
+						<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="USB_HOST"/>
+						<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="FATFS"/>
+					</sourceEntries>
+				</configuration>
+			</storageModule>
+			<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
+		</cconfiguration>
+		<cconfiguration id="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.release.22838031">
+			<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.release.22838031" moduleId="org.eclipse.cdt.core.settings" name="Release">
+				<externalSettings/>
+				<extensions>
+					<extension id="org.eclipse.cdt.core.ELF" point="org.eclipse.cdt.core.BinaryParser"/>
+					<extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+				</extensions>
+			</storageModule>
+			<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+				<configuration artifactExtension="elf" artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe,org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.release" cleanCommand="rm -rf" description="" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.release.22838031" name="Release" parent="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.release">
+					<folderInfo id="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.release.22838031." name="/" resourcePath="">
+						<toolChain id="com.st.stm32cube.ide.mcu.gnu.managedbuild.toolchain.exe.release.1823191174" name="MCU ARM GCC" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.toolchain.exe.release">
+							<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_mcu.699869768" name="MCU" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_mcu" useByScannerDiscovery="true" value="STM32F469NIHx" valueType="string"/>
+							<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_cpuid.1461406888" name="CPU" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_cpuid" useByScannerDiscovery="false" value="0" valueType="string"/>
+							<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_coreid.2077453065" name="Core" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_coreid" useByScannerDiscovery="false" value="0" valueType="string"/>
+							<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.fpu.1667934266" name="Floating-point unit" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.fpu" useByScannerDiscovery="true" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.fpu.value.fpv4-sp-d16" valueType="enumerated"/>
+							<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.floatabi.660557340" name="Floating-point ABI" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.floatabi" useByScannerDiscovery="true" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.floatabi.value.hard" valueType="enumerated"/>
+							<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_board.1017528934" name="Board" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_board" useByScannerDiscovery="false" value="STM32F469I-DISCO" valueType="string"/>
+							<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.defaults.632082707" name="Defaults" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.defaults" useByScannerDiscovery="false" value="com.st.stm32cube.ide.common.services.build.inputs.revA.1.0.5 || Release || false || Executable || com.st.stm32cube.ide.mcu.gnu.managedbuild.option.toolchain.value.workspace || STM32F469I-DISCO || 0 || 0 || arm-none-eabi- || ${gnu_tools_for_stm32_compiler_path} || ../FATFS/App | ../USB_HOST/App | ../Middlewares/Third_Party/FreeRTOS/Source/include | ../Drivers/STM32F4xx_HAL_Driver/Inc | ../Drivers/CMSIS/Device/ST/STM32F4xx/Include | ../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2 | ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy | ../Middlewares/ST/STM32_USB_Host_Library/Core/Inc | ../Middlewares/ST/STM32_USB_Host_Library/Class/CDC/Inc | ../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F | ../Drivers/CMSIS/Include | ../Core/Inc | ../FATFS/Target | ../USB_HOST/Target | ../Middlewares/Third_Party/FatFs/src ||  ||  || USE_HAL_DRIVER | STM32F469xx ||  || Drivers | USB_HOST | Core/Startup | Middlewares | Core | FATFS ||  ||  || ${workspace_loc:/${ProjName}/STM32F469NIHX_FLASH.ld} || true || NonSecure ||  || secure_nsclib.o ||  || None || " valueType="string"/>
+							<targetPlatform archList="all" binaryParser="org.eclipse.cdt.core.ELF" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.targetplatform.1663973541" isAbstract="false" osList="all" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.targetplatform"/>
+							<builder buildPath="${workspace_loc:/eez-flow-template-stm32f469i-disco}/Release" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.builder.1906799016" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="Gnu Make Builder" parallelBuildOn="true" parallelizationNumber="optimal" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.builder"/>
+							<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.1798704718" name="MCU GCC Assembler" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler">
+								<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.option.debuglevel.1965537707" name="Debug level" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.option.debuglevel" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.option.debuglevel.value.g0" valueType="enumerated"/>
+								<inputType id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.input.1929343366" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.input"/>
+							</tool>
+							<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.1986339965" name="MCU GCC Compiler" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler">
+								<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.debuglevel.1136736331" name="Debug level" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.debuglevel" useByScannerDiscovery="false" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.debuglevel.value.g0" valueType="enumerated"/>
+								<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.optimization.level.1725200503" name="Optimization level" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.optimization.level" useByScannerDiscovery="false" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.optimization.level.value.os" valueType="enumerated"/>
+								<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.definedsymbols.27956814" name="Define symbols (-D)" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.definedsymbols" useByScannerDiscovery="false" valueType="definedSymbols">
+									<listOptionValue builtIn="false" value="USE_HAL_DRIVER"/>
+									<listOptionValue builtIn="false" value="STM32F469xx"/>
+								</option>
+								<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.includepaths.249851950" name="Include paths (-I)" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.includepaths" useByScannerDiscovery="false" valueType="includePath">
+									<listOptionValue builtIn="false" value="../Core/Inc"/>
+									<listOptionValue builtIn="false" value="../FATFS/Target"/>
+									<listOptionValue builtIn="false" value="../FATFS/App"/>
+									<listOptionValue builtIn="false" value="../USB_HOST/App"/>
+									<listOptionValue builtIn="false" value="../USB_HOST/Target"/>
+									<listOptionValue builtIn="false" value="../Drivers/STM32F4xx_HAL_Driver/Inc"/>
+									<listOptionValue builtIn="false" value="../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy"/>
+									<listOptionValue builtIn="false" value="../Middlewares/Third_Party/FreeRTOS/Source/include"/>
+									<listOptionValue builtIn="false" value="../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F"/>
+									<listOptionValue builtIn="false" value="../Middlewares/Third_Party/FatFs/src"/>
+									<listOptionValue builtIn="false" value="../Middlewares/ST/STM32_USB_Host_Library/Core/Inc"/>
+									<listOptionValue builtIn="false" value="../Middlewares/ST/STM32_USB_Host_Library/Class/CDC/Inc"/>
+									<listOptionValue builtIn="false" value="../Drivers/CMSIS/Device/ST/STM32F4xx/Include"/>
+									<listOptionValue builtIn="false" value="../Drivers/CMSIS/Include"/>
+									<listOptionValue builtIn="false" value="../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2"/>
+								</option>
+								<inputType id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.input.c.634427817" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.input.c"/>
+							</tool>
+							<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.454175356" name="MCU G++ Compiler" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler">
+								<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.option.debuglevel.1060330445" name="Debug level" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.option.debuglevel" useByScannerDiscovery="false" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.option.debuglevel.value.g0" valueType="enumerated"/>
+								<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.option.optimization.level.1201803955" name="Optimization level" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.option.optimization.level" useByScannerDiscovery="false" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.option.optimization.level.value.os" valueType="enumerated"/>
+								<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.option.definedsymbols.360428959" name="Define symbols (-D)" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.option.definedsymbols" useByScannerDiscovery="false" valueType="definedSymbols">
+									<listOptionValue builtIn="false" value="USE_HAL_DRIVER"/>
+									<listOptionValue builtIn="false" value="STM32F469xx"/>
+								</option>
+								<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.option.includepaths.1005896393" name="Include paths (-I)" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.option.includepaths" useByScannerDiscovery="false" valueType="includePath">
+									<listOptionValue builtIn="false" value="../Core/Inc"/>
+									<listOptionValue builtIn="false" value="../FATFS/Target"/>
+									<listOptionValue builtIn="false" value="../FATFS/App"/>
+									<listOptionValue builtIn="false" value="../USB_HOST/App"/>
+									<listOptionValue builtIn="false" value="../USB_HOST/Target"/>
+									<listOptionValue builtIn="false" value="../Drivers/STM32F4xx_HAL_Driver/Inc"/>
+									<listOptionValue builtIn="false" value="../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy"/>
+									<listOptionValue builtIn="false" value="../Middlewares/Third_Party/FreeRTOS/Source/include"/>
+									<listOptionValue builtIn="false" value="../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F"/>
+									<listOptionValue builtIn="false" value="../Middlewares/Third_Party/FatFs/src"/>
+									<listOptionValue builtIn="false" value="../Middlewares/ST/STM32_USB_Host_Library/Core/Inc"/>
+									<listOptionValue builtIn="false" value="../Middlewares/ST/STM32_USB_Host_Library/Class/CDC/Inc"/>
+									<listOptionValue builtIn="false" value="../Drivers/CMSIS/Device/ST/STM32F4xx/Include"/>
+									<listOptionValue builtIn="false" value="../Drivers/CMSIS/Include"/>
+									<listOptionValue builtIn="false" value="../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2"/>
+								</option>
+								<inputType id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.input.cpp.135319302" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.input.cpp"/>
+							</tool>
+							<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.linker.728531574" name="MCU GCC Linker" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.linker"/>
+							<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.linker.1378427683" name="MCU G++ Linker" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.linker">
+								<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.linker.option.script.811658304" name="Linker Script (-T)" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.linker.option.script" value="${workspace_loc:/${ProjName}/STM32F469NIHX_FLASH.ld}" valueType="string"/>
+								<inputType id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.linker.input.1312553728" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.linker.input">
+									<additionalInput kind="additionalinputdependency" paths="$(USER_OBJS)"/>
+									<additionalInput kind="additionalinput" paths="$(LIBS)"/>
+								</inputType>
+							</tool>
+							<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.archiver.221472056" name="MCU GCC Archiver" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.archiver"/>
+							<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.size.430461177" name="MCU Size" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.size"/>
+							<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objdump.listfile.1061010777" name="MCU Output Converter list file" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objdump.listfile"/>
+							<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.hex.306385884" name="MCU Output Converter Hex" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.hex"/>
+							<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.binary.1715292840" name="MCU Output Converter Binary" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.binary"/>
+							<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.verilog.1577549252" name="MCU Output Converter Verilog" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.verilog"/>
+							<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.srec.1364354635" name="MCU Output Converter Motorola S-rec" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.srec"/>
+							<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.symbolsrec.817959020" name="MCU Output Converter Motorola S-rec with symbols" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.symbolsrec"/>
+						</toolChain>
+					</folderInfo>
+					<sourceEntries>
+						<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="USB_HOST"/>
+						<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="Core"/>
+						<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="FATFS"/>
+						<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="Middlewares"/>
+						<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="Drivers"/>
+					</sourceEntries>
+				</configuration>
+			</storageModule>
+			<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
+		</cconfiguration>
+	</storageModule>
+	<storageModule moduleId="org.eclipse.cdt.make.core.buildtargets"/>
+	<storageModule moduleId="org.eclipse.cdt.core.pathentry"/>
+	<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+		<project id="eez-flow-template-stm32f469i-disco.null.560981908" name="eez-flow-template-stm32f469i-disco"/>
+	</storageModule>
+	<storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/>
+	<storageModule moduleId="scannerConfiguration">
+		<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+		<scannerConfigBuildInfo instanceId="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.debug.460065682;com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.debug.460065682.;com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.1825023861;com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.input.cpp.1771274810">
+			<autodiscovery enabled="false" problemReportingEnabled="true" selectedProfileId=""/>
+		</scannerConfigBuildInfo>
+		<scannerConfigBuildInfo instanceId="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.release.22838031;com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.release.22838031.;com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.1986339965;com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.input.c.634427817">
+			<autodiscovery enabled="false" problemReportingEnabled="true" selectedProfileId=""/>
+		</scannerConfigBuildInfo>
+		<scannerConfigBuildInfo instanceId="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.release.22838031;com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.release.22838031.;com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.454175356;com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.input.cpp.135319302">
+			<autodiscovery enabled="false" problemReportingEnabled="true" selectedProfileId=""/>
+		</scannerConfigBuildInfo>
+		<scannerConfigBuildInfo instanceId="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.debug.460065682;com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.debug.460065682.;com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.312266454;com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.input.c.801324572">
+			<autodiscovery enabled="false" problemReportingEnabled="true" selectedProfileId=""/>
+		</scannerConfigBuildInfo>
+	</storageModule>
+</cproject>
\ No newline at end of file
diff --git a/.gitignore b/.gitignore
new file mode 100644
index 0000000..0d38868
--- /dev/null
+++ b/.gitignore
@@ -0,0 +1,16 @@
+build
+.vscode/launch.json
+.vscode/.vscode/c_cpp_properties.json
+.vscode/launch.json
+
+.vscode/*.log
+nul.d
+
+Debug
+Release
+
+*.eez-project-ui-state
+
+org.eclipse.cdt.core.prefs
+
+sync.ffs_db
\ No newline at end of file
diff --git a/.gitmodules b/.gitmodules
new file mode 100644
index 0000000..bf91785
--- /dev/null
+++ b/.gitmodules
@@ -0,0 +1,3 @@
+[submodule "Middlewares/eez"]
+	path = Middlewares/eez
+	url = https://github.com/eez-open/eez-framework
diff --git a/.mxproject b/.mxproject
new file mode 100644
index 0000000..3cc6dc9
--- /dev/null
+++ b/.mxproject
@@ -0,0 +1,75 @@
+[PreviousLibFiles]
+LibFiles=Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_hcd.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_usb.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc_ex.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_bus.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_rcc.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_system.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_utils.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ex.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ramfunc.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio_ex.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_gpio.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma_ex.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_dma.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_dmamux.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr_ex.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_pwr.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_cortex.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_cortex.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal.h;Drivers\STM32F4xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_def.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_exti.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_exti.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_crc.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_crc.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma2d.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_dma2d.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dsi.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_fmc.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_sdram.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_i2c.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c_ex.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_ltdc.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_ltdc_ex.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_qspi.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_sai.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_sai_ex.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_sdmmc.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_sd.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim_ex.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_tim.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_uart.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_usart.h;Middlewares\Third_Party\FatFs\src\diskio.h;Middlewares\Third_Party\FatFs\src\ff.h;Middlewares\Third_Party\FatFs\src\ff_gen_drv.h;Middlewares\Third_Party\FatFs\src\integer.h;Middlewares\Third_Party\FreeRTOS\Source\include\croutine.h;Middlewares\Third_Party\FreeRTOS\Source\include\deprecated_definitions.h;Middlewares\Third_Party\FreeRTOS\Source\include\event_groups.h;Middlewares\Third_Party\FreeRTOS\Source\include\FreeRTOS.h;Middlewares\Third_Party\FreeRTOS\Source\include\list.h;Middlewares\Third_Party\FreeRTOS\Source\include\message_buffer.h;Middlewares\Third_Party\FreeRTOS\Source\include\mpu_prototypes.h;Middlewares\Third_Party\FreeRTOS\Source\include\mpu_wrappers.h;Middlewares\Third_Party\FreeRTOS\Source\include\portable.h;Middlewares\Third_Party\FreeRTOS\Source\include\projdefs.h;Middlewares\Third_Party\FreeRTOS\Source\include\queue.h;Middlewares\Third_Party\FreeRTOS\Source\include\semphr.h;Middlewares\Third_Party\FreeRTOS\Source\include\stack_macros.h;Middlewares\Third_Party\FreeRTOS\Source\include\StackMacros.h;Middlewares\Third_Party\FreeRTOS\Source\include\stream_buffer.h;Middlewares\Third_Party\FreeRTOS\Source\include\task.h;Middlewares\Third_Party\FreeRTOS\Source\include\timers.h;Middlewares\Third_Party\FreeRTOS\Source\include\atomic.h;Middlewares\Third_Party\FreeRTOS\Source\CMSIS_RTOS_V2\cmsis_os2.h;Middlewares\Third_Party\FreeRTOS\Source\CMSIS_RTOS_V2\cmsis_os.h;Middlewares\Third_Party\FreeRTOS\Source\CMSIS_RTOS_V2\freertos_mpool.h;Middlewares\Third_Party\FreeRTOS\Source\CMSIS_RTOS_V2\freertos_os2.h;Middlewares\Third_Party\FreeRTOS\Source\portable\GCC\ARM_CM4F\portmacro.h;Middlewares\ST\STM32_USB_Host_Library\Core\Inc\usbh_core.h;Middlewares\ST\STM32_USB_Host_Library\Core\Inc\usbh_ctlreq.h;Middlewares\ST\STM32_USB_Host_Library\Core\Inc\usbh_def.h;Middlewares\ST\STM32_USB_Host_Library\Core\Inc\usbh_ioreq.h;Middlewares\ST\STM32_USB_Host_Library\Core\Inc\usbh_pipes.h;Middlewares\ST\STM32_USB_Host_Library\Class\CDC\Inc\usbh_cdc.h;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_hcd.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_ll_usb.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_rcc.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_rcc_ex.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_flash.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_flash_ex.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_flash_ramfunc.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_gpio.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_dma_ex.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_dma.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_pwr.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_pwr_ex.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_cortex.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_exti.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_crc.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_dma2d.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_dsi.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_ll_fmc.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_sdram.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_i2c.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_i2c_ex.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_ltdc.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_ltdc_ex.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_qspi.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_sai.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_sai_ex.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_ll_sdmmc.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_sd.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_tim.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_tim_ex.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_uart.c;Middlewares\Third_Party\FatFs\src\diskio.c;Middlewares\Third_Party\FatFs\src\ff.c;Middlewares\Third_Party\FatFs\src\ff_gen_drv.c;Middlewares\Third_Party\FatFs\src\option\syscall.c;Middlewares\Third_Party\FreeRTOS\Source\croutine.c;Middlewares\Third_Party\FreeRTOS\Source\event_groups.c;Middlewares\Third_Party\FreeRTOS\Source\list.c;Middlewares\Third_Party\FreeRTOS\Source\queue.c;Middlewares\Third_Party\FreeRTOS\Source\stream_buffer.c;Middlewares\Third_Party\FreeRTOS\Source\tasks.c;Middlewares\Third_Party\FreeRTOS\Source\timers.c;Middlewares\Third_Party\FreeRTOS\Source\CMSIS_RTOS_V2\cmsis_os2.c;Middlewares\Third_Party\FreeRTOS\Source\portable\MemMang\heap_4.c;Middlewares\Third_Party\FreeRTOS\Source\portable\GCC\ARM_CM4F\port.c;Middlewares\ST\STM32_USB_Host_Library\Core\Src\usbh_core.c;Middlewares\ST\STM32_USB_Host_Library\Core\Src\usbh_ctlreq.c;Middlewares\ST\STM32_USB_Host_Library\Core\Src\usbh_ioreq.c;Middlewares\ST\STM32_USB_Host_Library\Core\Src\usbh_pipes.c;Middlewares\ST\STM32_USB_Host_Library\Class\CDC\Src\usbh_cdc.c;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_hcd.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_usb.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc_ex.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_bus.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_rcc.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_system.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_utils.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ex.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ramfunc.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio_ex.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_gpio.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma_ex.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_dma.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_dmamux.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr_ex.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_pwr.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_cortex.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_cortex.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal.h;Drivers\STM32F4xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_def.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_exti.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_exti.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_crc.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_crc.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma2d.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_dma2d.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dsi.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_fmc.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_sdram.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_i2c.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c_ex.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_ltdc.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_ltdc_ex.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_qspi.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_sai.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_sai_ex.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_sdmmc.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_sd.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim_ex.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_tim.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_uart.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_usart.h;Middlewares\Third_Party\FatFs\src\diskio.h;Middlewares\Third_Party\FatFs\src\ff.h;Middlewares\Third_Party\FatFs\src\ff_gen_drv.h;Middlewares\Third_Party\FatFs\src\integer.h;Middlewares\Third_Party\FreeRTOS\Source\include\croutine.h;Middlewares\Third_Party\FreeRTOS\Source\include\deprecated_definitions.h;Middlewares\Third_Party\FreeRTOS\Source\include\event_groups.h;Middlewares\Third_Party\FreeRTOS\Source\include\FreeRTOS.h;Middlewares\Third_Party\FreeRTOS\Source\include\list.h;Middlewares\Third_Party\FreeRTOS\Source\include\message_buffer.h;Middlewares\Third_Party\FreeRTOS\Source\include\mpu_prototypes.h;Middlewares\Third_Party\FreeRTOS\Source\include\mpu_wrappers.h;Middlewares\Third_Party\FreeRTOS\Source\include\portable.h;Middlewares\Third_Party\FreeRTOS\Source\include\projdefs.h;Middlewares\Third_Party\FreeRTOS\Source\include\queue.h;Middlewares\Third_Party\FreeRTOS\Source\include\semphr.h;Middlewares\Third_Party\FreeRTOS\Source\include\stack_macros.h;Middlewares\Third_Party\FreeRTOS\Source\include\StackMacros.h;Middlewares\Third_Party\FreeRTOS\Source\include\stream_buffer.h;Middlewares\Third_Party\FreeRTOS\Source\include\task.h;Middlewares\Third_Party\FreeRTOS\Source\include\timers.h;Middlewares\Third_Party\FreeRTOS\Source\include\atomic.h;Middlewares\Third_Party\FreeRTOS\Source\CMSIS_RTOS_V2\cmsis_os2.h;Middlewares\Third_Party\FreeRTOS\Source\CMSIS_RTOS_V2\cmsis_os.h;Middlewares\Third_Party\FreeRTOS\Source\CMSIS_RTOS_V2\freertos_mpool.h;Middlewares\Third_Party\FreeRTOS\Source\CMSIS_RTOS_V2\freertos_os2.h;Middlewares\Third_Party\FreeRTOS\Source\portable\GCC\ARM_CM4F\portmacro.h;Middlewares\ST\STM32_USB_Host_Library\Core\Inc\usbh_core.h;Middlewares\ST\STM32_USB_Host_Library\Core\Inc\usbh_ctlreq.h;Middlewares\ST\STM32_USB_Host_Library\Core\Inc\usbh_def.h;Middlewares\ST\STM32_USB_Host_Library\Core\Inc\usbh_ioreq.h;Middlewares\ST\STM32_USB_Host_Library\Core\Inc\usbh_pipes.h;Middlewares\ST\STM32_USB_Host_Library\Class\CDC\Inc\usbh_cdc.h;Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f469xx.h;Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f4xx.h;Drivers\CMSIS\Device\ST\STM32F4xx\Include\system_stm32f4xx.h;Drivers\CMSIS\Device\ST\STM32F4xx\Source\Templates\system_stm32f4xx.c;Drivers\CMSIS\Include\cmsis_armcc.h;Drivers\CMSIS\Include\cmsis_armclang.h;Drivers\CMSIS\Include\cmsis_compiler.h;Drivers\CMSIS\Include\cmsis_gcc.h;Drivers\CMSIS\Include\cmsis_iccarm.h;Drivers\CMSIS\Include\cmsis_version.h;Drivers\CMSIS\Include\core_armv8mbl.h;Drivers\CMSIS\Include\core_armv8mml.h;Drivers\CMSIS\Include\core_cm0.h;Drivers\CMSIS\Include\core_cm0plus.h;Drivers\CMSIS\Include\core_cm1.h;Drivers\CMSIS\Include\core_cm23.h;Drivers\CMSIS\Include\core_cm3.h;Drivers\CMSIS\Include\core_cm33.h;Drivers\CMSIS\Include\core_cm4.h;Drivers\CMSIS\Include\core_cm7.h;Drivers\CMSIS\Include\core_sc000.h;Drivers\CMSIS\Include\core_sc300.h;Drivers\CMSIS\Include\mpu_armv7.h;Drivers\CMSIS\Include\mpu_armv8.h;Drivers\CMSIS\Include\tz_context.h;
+
+[PreviousUsedCubeIDEFiles]
+SourceFiles=Core\Src\main.c;Core\Src\gpio.c;Core\Src\crc.c;Core\Src\dma2d.c;Core\Src\dsihost.c;FATFS\Target\bsp_driver_sd.c;FATFS\Target\sd_diskio.c;FATFS\App\fatfs.c;FATFS\Target\fatfs_platform.c;Core\Src\fmc.c;Core\Src\freertos.c;Core\Src\i2c.c;Core\Src\ltdc.c;Core\Src\quadspi.c;Core\Src\sai.c;Core\Src\sdio.c;Core\Src\tim.c;Core\Src\usart.c;USB_HOST\App\usb_host.c;USB_HOST\Target\usbh_conf.c;USB_HOST\Target\usbh_platform.c;Core\Src\stm32f4xx_it.c;Core\Src\stm32f4xx_hal_msp.c;Core\Src\stm32f4xx_hal_timebase_tim.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_hcd.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_ll_usb.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_rcc.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_rcc_ex.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_flash.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_flash_ex.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_flash_ramfunc.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_gpio.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_dma_ex.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_dma.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_pwr.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_pwr_ex.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_cortex.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_exti.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_crc.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_dma2d.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_dsi.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_ll_fmc.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_sdram.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_i2c.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_i2c_ex.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_ltdc.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_ltdc_ex.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_qspi.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_sai.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_sai_ex.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_ll_sdmmc.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_sd.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_tim.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_tim_ex.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_uart.c;Middlewares\Third_Party\FatFs\src\diskio.c;Middlewares\Third_Party\FatFs\src\ff.c;Middlewares\Third_Party\FatFs\src\ff_gen_drv.c;Middlewares\Third_Party\FatFs\src\option\syscall.c;Middlewares\Third_Party\FreeRTOS\Source\croutine.c;Middlewares\Third_Party\FreeRTOS\Source\event_groups.c;Middlewares\Third_Party\FreeRTOS\Source\list.c;Middlewares\Third_Party\FreeRTOS\Source\queue.c;Middlewares\Third_Party\FreeRTOS\Source\stream_buffer.c;Middlewares\Third_Party\FreeRTOS\Source\tasks.c;Middlewares\Third_Party\FreeRTOS\Source\timers.c;Middlewares\Third_Party\FreeRTOS\Source\CMSIS_RTOS_V2\cmsis_os2.c;Middlewares\Third_Party\FreeRTOS\Source\portable\MemMang\heap_4.c;Middlewares\Third_Party\FreeRTOS\Source\portable\GCC\ARM_CM4F\port.c;Middlewares\ST\STM32_USB_Host_Library\Core\Src\usbh_core.c;Middlewares\ST\STM32_USB_Host_Library\Core\Src\usbh_ctlreq.c;Middlewares\ST\STM32_USB_Host_Library\Core\Src\usbh_ioreq.c;Middlewares\ST\STM32_USB_Host_Library\Core\Src\usbh_pipes.c;Middlewares\ST\STM32_USB_Host_Library\Class\CDC\Src\usbh_cdc.c;Drivers\CMSIS\Device\ST\STM32F4xx\Source\Templates\system_stm32f4xx.c;Core\Src\system_stm32f4xx.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_hcd.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_ll_usb.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_rcc.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_rcc_ex.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_flash.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_flash_ex.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_flash_ramfunc.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_gpio.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_dma_ex.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_dma.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_pwr.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_pwr_ex.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_cortex.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_exti.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_crc.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_dma2d.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_dsi.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_ll_fmc.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_sdram.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_i2c.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_i2c_ex.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_ltdc.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_ltdc_ex.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_qspi.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_sai.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_sai_ex.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_ll_sdmmc.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_sd.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_tim.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_tim_ex.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_uart.c;Middlewares\Third_Party\FatFs\src\diskio.c;Middlewares\Third_Party\FatFs\src\ff.c;Middlewares\Third_Party\FatFs\src\ff_gen_drv.c;Middlewares\Third_Party\FatFs\src\option\syscall.c;Middlewares\Third_Party\FreeRTOS\Source\croutine.c;Middlewares\Third_Party\FreeRTOS\Source\event_groups.c;Middlewares\Third_Party\FreeRTOS\Source\list.c;Middlewares\Third_Party\FreeRTOS\Source\queue.c;Middlewares\Third_Party\FreeRTOS\Source\stream_buffer.c;Middlewares\Third_Party\FreeRTOS\Source\tasks.c;Middlewares\Third_Party\FreeRTOS\Source\timers.c;Middlewares\Third_Party\FreeRTOS\Source\CMSIS_RTOS_V2\cmsis_os2.c;Middlewares\Third_Party\FreeRTOS\Source\portable\MemMang\heap_4.c;Middlewares\Third_Party\FreeRTOS\Source\portable\GCC\ARM_CM4F\port.c;Middlewares\ST\STM32_USB_Host_Library\Core\Src\usbh_core.c;Middlewares\ST\STM32_USB_Host_Library\Core\Src\usbh_ctlreq.c;Middlewares\ST\STM32_USB_Host_Library\Core\Src\usbh_ioreq.c;Middlewares\ST\STM32_USB_Host_Library\Core\Src\usbh_pipes.c;Middlewares\ST\STM32_USB_Host_Library\Class\CDC\Src\usbh_cdc.c;Drivers\CMSIS\Device\ST\STM32F4xx\Source\Templates\system_stm32f4xx.c;Core\Src\system_stm32f4xx.c;;;Middlewares\Third_Party\FatFs\src\diskio.c;Middlewares\Third_Party\FatFs\src\ff.c;Middlewares\Third_Party\FatFs\src\ff_gen_drv.c;Middlewares\Third_Party\FatFs\src\option\syscall.c;Middlewares\Third_Party\FreeRTOS\Source\croutine.c;Middlewares\Third_Party\FreeRTOS\Source\event_groups.c;Middlewares\Third_Party\FreeRTOS\Source\list.c;Middlewares\Third_Party\FreeRTOS\Source\queue.c;Middlewares\Third_Party\FreeRTOS\Source\stream_buffer.c;Middlewares\Third_Party\FreeRTOS\Source\tasks.c;Middlewares\Third_Party\FreeRTOS\Source\timers.c;Middlewares\Third_Party\FreeRTOS\Source\CMSIS_RTOS_V2\cmsis_os2.c;Middlewares\Third_Party\FreeRTOS\Source\portable\MemMang\heap_4.c;Middlewares\Third_Party\FreeRTOS\Source\portable\GCC\ARM_CM4F\port.c;Middlewares\ST\STM32_USB_Host_Library\Core\Src\usbh_core.c;Middlewares\ST\STM32_USB_Host_Library\Core\Src\usbh_ctlreq.c;Middlewares\ST\STM32_USB_Host_Library\Core\Src\usbh_ioreq.c;Middlewares\ST\STM32_USB_Host_Library\Core\Src\usbh_pipes.c;Middlewares\ST\STM32_USB_Host_Library\Class\CDC\Src\usbh_cdc.c;
+HeaderPath=Drivers\STM32F4xx_HAL_Driver\Inc;Drivers\STM32F4xx_HAL_Driver\Inc\Legacy;Middlewares\Third_Party\FatFs\src;Middlewares\Third_Party\FreeRTOS\Source\include;Middlewares\Third_Party\FreeRTOS\Source\CMSIS_RTOS_V2;Middlewares\Third_Party\FreeRTOS\Source\portable\GCC\ARM_CM4F;Middlewares\ST\STM32_USB_Host_Library\Core\Inc;Middlewares\ST\STM32_USB_Host_Library\Class\CDC\Inc;Drivers\CMSIS\Device\ST\STM32F4xx\Include;Drivers\CMSIS\Include;Core\Inc;FATFS\Target;FATFS\App;USB_HOST\App;USB_HOST\Target;
+CDefines=USE_HAL_DRIVER;STM32F469xx;USE_HAL_DRIVER;USE_HAL_DRIVER;
+
+[PreviousGenFiles]
+AdvancedFolderStructure=true
+HeaderFileListSize=24
+HeaderFiles#0=..\Core\Inc\gpio.h
+HeaderFiles#1=..\Core\Inc\crc.h
+HeaderFiles#2=..\Core\Inc\dma2d.h
+HeaderFiles#3=..\Core\Inc\dsihost.h
+HeaderFiles#4=..\FATFS\Target\ffconf.h
+HeaderFiles#5=..\FATFS\Target\bsp_driver_sd.h
+HeaderFiles#6=..\FATFS\Target\sd_diskio.h
+HeaderFiles#7=..\FATFS\App\fatfs.h
+HeaderFiles#8=..\FATFS\Target\fatfs_platform.h
+HeaderFiles#9=..\Core\Inc\fmc.h
+HeaderFiles#10=..\Core\Inc\FreeRTOSConfig.h
+HeaderFiles#11=..\Core\Inc\i2c.h
+HeaderFiles#12=..\Core\Inc\ltdc.h
+HeaderFiles#13=..\Core\Inc\quadspi.h
+HeaderFiles#14=..\Core\Inc\sai.h
+HeaderFiles#15=..\Core\Inc\sdio.h
+HeaderFiles#16=..\Core\Inc\tim.h
+HeaderFiles#17=..\Core\Inc\usart.h
+HeaderFiles#18=..\USB_HOST\App\usb_host.h
+HeaderFiles#19=..\USB_HOST\Target\usbh_conf.h
+HeaderFiles#20=..\USB_HOST\Target\usbh_platform.h
+HeaderFiles#21=..\Core\Inc\stm32f4xx_it.h
+HeaderFiles#22=..\Core\Inc\stm32f4xx_hal_conf.h
+HeaderFiles#23=..\Core\Inc\main.h
+HeaderFolderListSize=5
+HeaderPath#0=..\Core\Inc
+HeaderPath#1=..\FATFS\Target
+HeaderPath#2=..\FATFS\App
+HeaderPath#3=..\USB_HOST\App
+HeaderPath#4=..\USB_HOST\Target
+HeaderFiles=;
+SourceFileListSize=24
+SourceFiles#0=..\Core\Src\gpio.c
+SourceFiles#1=..\Core\Src\crc.c
+SourceFiles#2=..\Core\Src\dma2d.c
+SourceFiles#3=..\Core\Src\dsihost.c
+SourceFiles#4=..\FATFS\Target\bsp_driver_sd.c
+SourceFiles#5=..\FATFS\Target\sd_diskio.c
+SourceFiles#6=..\FATFS\App\fatfs.c
+SourceFiles#7=..\FATFS\Target\fatfs_platform.c
+SourceFiles#8=..\Core\Src\fmc.c
+SourceFiles#9=..\Core\Src\freertos.c
+SourceFiles#10=..\Core\Src\i2c.c
+SourceFiles#11=..\Core\Src\ltdc.c
+SourceFiles#12=..\Core\Src\quadspi.c
+SourceFiles#13=..\Core\Src\sai.c
+SourceFiles#14=..\Core\Src\sdio.c
+SourceFiles#15=..\Core\Src\tim.c
+SourceFiles#16=..\Core\Src\usart.c
+SourceFiles#17=..\USB_HOST\App\usb_host.c
+SourceFiles#18=..\USB_HOST\Target\usbh_conf.c
+SourceFiles#19=..\USB_HOST\Target\usbh_platform.c
+SourceFiles#20=..\Core\Src\stm32f4xx_it.c
+SourceFiles#21=..\Core\Src\stm32f4xx_hal_msp.c
+SourceFiles#22=..\Core\Src\stm32f4xx_hal_timebase_tim.c
+SourceFiles#23=..\Core\Src\main.c
+SourceFolderListSize=5
+SourcePath#0=..\Core\Src
+SourcePath#1=..\FATFS\Target
+SourcePath#2=..\FATFS\App
+SourcePath#3=..\USB_HOST\App
+SourcePath#4=..\USB_HOST\Target
+SourceFiles=;
+
diff --git a/.project b/.project
new file mode 100644
index 0000000..67b4508
--- /dev/null
+++ b/.project
@@ -0,0 +1,33 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+	<name>eez-flow-template-stm32f469i-disco</name>
+	<comment></comment>
+	<projects>
+	</projects>
+	<buildSpec>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
+			<triggers>clean,full,incremental,</triggers>
+			<arguments>
+			</arguments>
+		</buildCommand>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
+			<triggers>full,incremental,</triggers>
+			<arguments>
+			</arguments>
+		</buildCommand>
+	</buildSpec>
+	<natures>
+		<nature>com.st.stm32cube.ide.mcu.MCUProjectNature</nature>
+		<nature>com.st.stm32cube.ide.mcu.MCUCubeProjectNature</nature>
+		<nature>org.eclipse.cdt.core.cnature</nature>
+		<nature>org.eclipse.cdt.core.ccnature</nature>
+		<nature>com.st.stm32cube.ide.mcu.MCUCubeIdeServicesRevAev2ProjectNature</nature>
+		<nature>com.st.stm32cube.ide.mcu.MCUAdvancedStructureProjectNature</nature>
+		<nature>com.st.stm32cube.ide.mcu.MCUSingleCpuProjectNature</nature>
+		<nature>com.st.stm32cube.ide.mcu.MCURootProjectNature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+	</natures>
+</projectDescription>
diff --git a/.settings/language.settings.xml b/.settings/language.settings.xml
new file mode 100644
index 0000000..25202d9
--- /dev/null
+++ b/.settings/language.settings.xml
@@ -0,0 +1,25 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<project>
+	<configuration id="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.debug.460065682" name="Debug">
+		<extension point="org.eclipse.cdt.core.LanguageSettingsProvider">
+			<provider copy-of="extension" id="org.eclipse.cdt.ui.UserLanguageSettingsProvider"/>
+			<provider-reference id="org.eclipse.cdt.core.ReferencedProjectsLanguageSettingsProvider" ref="shared-provider"/>
+			<provider-reference id="org.eclipse.cdt.managedbuilder.core.MBSLanguageSettingsProvider" ref="shared-provider"/>
+			<provider class="com.st.stm32cube.ide.mcu.toolchain.armnone.setup.CrossBuiltinSpecsDetector" console="false" env-hash="-404192909888548527" id="com.st.stm32cube.ide.mcu.toolchain.armnone.setup.CrossBuiltinSpecsDetector" keep-relative-paths="false" name="MCU ARM GCC Built-in Compiler Settings" parameter="${COMMAND} ${FLAGS} -E -P -v -dD &quot;${INPUTS}&quot;" prefer-non-shared="true">
+				<language-scope id="org.eclipse.cdt.core.gcc"/>
+				<language-scope id="org.eclipse.cdt.core.g++"/>
+			</provider>
+		</extension>
+	</configuration>
+	<configuration id="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.release.22838031" name="Release">
+		<extension point="org.eclipse.cdt.core.LanguageSettingsProvider">
+			<provider copy-of="extension" id="org.eclipse.cdt.ui.UserLanguageSettingsProvider"/>
+			<provider-reference id="org.eclipse.cdt.core.ReferencedProjectsLanguageSettingsProvider" ref="shared-provider"/>
+			<provider-reference id="org.eclipse.cdt.managedbuilder.core.MBSLanguageSettingsProvider" ref="shared-provider"/>
+			<provider class="com.st.stm32cube.ide.mcu.toolchain.armnone.setup.CrossBuiltinSpecsDetector" console="false" env-hash="-404192909888548527" id="com.st.stm32cube.ide.mcu.toolchain.armnone.setup.CrossBuiltinSpecsDetector" keep-relative-paths="false" name="MCU ARM GCC Built-in Compiler Settings" parameter="${COMMAND} ${FLAGS} -E -P -v -dD &quot;${INPUTS}&quot;" prefer-non-shared="true">
+				<language-scope id="org.eclipse.cdt.core.gcc"/>
+				<language-scope id="org.eclipse.cdt.core.g++"/>
+			</provider>
+		</extension>
+	</configuration>
+</project>
\ No newline at end of file
diff --git a/.settings/stm32cubeide.project.prefs b/.settings/stm32cubeide.project.prefs
new file mode 100644
index 0000000..56817ff
--- /dev/null
+++ b/.settings/stm32cubeide.project.prefs
@@ -0,0 +1,5 @@
+635E684B79701B039C64EA45C3F84D30=BF3467EB2F6A6B48939123F7923F5F8B
+66BE74F758C12D739921AEA421D593D3=1
+8DF89ED150041C4CBC7CB9A9CAA90856=A1FFDF8FD2CA4383961428405A05528F
+DC22A860405A8BF2F2C095E5B6529F12=A1FFDF8FD2CA4383961428405A05528F
+eclipse.preferences.version=1
diff --git a/.vscode/settings.json b/.vscode/settings.json
new file mode 100644
index 0000000..65e1ec0
--- /dev/null
+++ b/.vscode/settings.json
@@ -0,0 +1,3 @@
+{
+    "makefile.extensionOutputFolder": "./.vscode"
+}
\ No newline at end of file
diff --git a/Core/Inc/FreeRTOSConfig.h b/Core/Inc/FreeRTOSConfig.h
new file mode 100644
index 0000000..617b3b0
--- /dev/null
+++ b/Core/Inc/FreeRTOSConfig.h
@@ -0,0 +1,176 @@
+/* USER CODE BEGIN Header */
+/*
+ * FreeRTOS Kernel V10.3.1
+ * Portion Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Portion Copyright (C) 2019 StMicroelectronics, Inc.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+/* USER CODE END Header */
+
+#ifndef FREERTOS_CONFIG_H
+#define FREERTOS_CONFIG_H
+
+/*-----------------------------------------------------------
+ * Application specific definitions.
+ *
+ * These definitions should be adjusted for your particular hardware and
+ * application requirements.
+ *
+ * These parameters and more are described within the 'configuration' section of the
+ * FreeRTOS API documentation available on the FreeRTOS.org web site.
+ *
+ * See http://www.freertos.org/a00110.html
+ *----------------------------------------------------------*/
+
+/* USER CODE BEGIN Includes */
+/* Section where include file can be added */
+/* USER CODE END Includes */
+
+/* Ensure definitions are only used by the compiler, and not by the assembler. */
+#if defined(__ICCARM__) || defined(__CC_ARM) || defined(__GNUC__)
+  #include <stdint.h>
+  extern uint32_t SystemCoreClock;
+#endif
+#ifndef CMSIS_device_header
+#define CMSIS_device_header "stm32f4xx.h"
+#endif /* CMSIS_device_header */
+
+#define configENABLE_FPU                         0
+#define configENABLE_MPU                         0
+
+#define configUSE_PREEMPTION                     1
+#define configSUPPORT_STATIC_ALLOCATION          1
+#define configSUPPORT_DYNAMIC_ALLOCATION         1
+#define configUSE_IDLE_HOOK                      1
+#define configUSE_TICK_HOOK                      0
+#define configCPU_CLOCK_HZ                       ( SystemCoreClock )
+#define configTICK_RATE_HZ                       ((TickType_t)1000)
+#define configMAX_PRIORITIES                     ( 56 )
+#define configMINIMAL_STACK_SIZE                 ((uint16_t)128)
+#define configTOTAL_HEAP_SIZE                    ((size_t)32768)
+#define configMAX_TASK_NAME_LEN                  ( 16 )
+#define configUSE_TRACE_FACILITY                 1
+#define configUSE_16_BIT_TICKS                   0
+#define configUSE_MUTEXES                        1
+#define configQUEUE_REGISTRY_SIZE                8
+#define configCHECK_FOR_STACK_OVERFLOW           2
+#define configUSE_RECURSIVE_MUTEXES              1
+#define configUSE_MALLOC_FAILED_HOOK             1
+#define configUSE_APPLICATION_TASK_TAG           1
+#define configUSE_COUNTING_SEMAPHORES            1
+#define configUSE_PORT_OPTIMISED_TASK_SELECTION  0
+/* USER CODE BEGIN MESSAGE_BUFFER_LENGTH_TYPE */
+/* Defaults to size_t for backward compatibility, but can be changed
+   if lengths will always be less than the number of bytes in a size_t. */
+#define configMESSAGE_BUFFER_LENGTH_TYPE         size_t
+/* USER CODE END MESSAGE_BUFFER_LENGTH_TYPE */
+
+/* Co-routine definitions. */
+#define configUSE_CO_ROUTINES                    0
+#define configMAX_CO_ROUTINE_PRIORITIES          ( 2 )
+
+/* Software timer definitions. */
+#define configUSE_TIMERS                         1
+#define configTIMER_TASK_PRIORITY                ( 2 )
+#define configTIMER_QUEUE_LENGTH                 10
+#define configTIMER_TASK_STACK_DEPTH             256
+
+/* The following flag must be enabled only when using newlib */
+#define configUSE_NEWLIB_REENTRANT          1
+
+/* CMSIS-RTOS V2 flags */
+#define configUSE_OS2_THREAD_SUSPEND_RESUME  1
+#define configUSE_OS2_THREAD_ENUMERATE       1
+#define configUSE_OS2_EVENTFLAGS_FROM_ISR    1
+#define configUSE_OS2_THREAD_FLAGS           1
+#define configUSE_OS2_TIMER                  1
+#define configUSE_OS2_MUTEX                  1
+
+/* Set the following definitions to 1 to include the API function, or zero
+to exclude the API function. */
+#define INCLUDE_vTaskPrioritySet             1
+#define INCLUDE_uxTaskPriorityGet            1
+#define INCLUDE_vTaskDelete                  1
+#define INCLUDE_vTaskCleanUpResources        0
+#define INCLUDE_vTaskSuspend                 1
+#define INCLUDE_vTaskDelayUntil              1
+#define INCLUDE_vTaskDelay                   1
+#define INCLUDE_xTaskGetSchedulerState       1
+#define INCLUDE_xTimerPendFunctionCall       1
+#define INCLUDE_xQueueGetMutexHolder         1
+#define INCLUDE_uxTaskGetStackHighWaterMark  1
+#define INCLUDE_xTaskGetCurrentTaskHandle    1
+#define INCLUDE_eTaskGetState                1
+
+/*
+ * The CMSIS-RTOS V2 FreeRTOS wrapper is dependent on the heap implementation used
+ * by the application thus the correct define need to be enabled below
+ */
+#define USE_FreeRTOS_HEAP_4
+
+/* Cortex-M specific definitions. */
+#ifdef __NVIC_PRIO_BITS
+ /* __BVIC_PRIO_BITS will be specified when CMSIS is being used. */
+ #define configPRIO_BITS         __NVIC_PRIO_BITS
+#else
+ #define configPRIO_BITS         4
+#endif
+
+/* The lowest interrupt priority that can be used in a call to a "set priority"
+function. */
+#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY   15
+
+/* The highest interrupt priority that can be used by any interrupt service
+routine that makes calls to interrupt safe FreeRTOS API functions.  DO NOT CALL
+INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER
+PRIORITY THAN THIS! (higher priorities are lower numeric values. */
+#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY 5
+
+/* Interrupt priorities used by the kernel port layer itself.  These are generic
+to all Cortex-M ports, and do not rely on any particular library functions. */
+#define configKERNEL_INTERRUPT_PRIORITY 		( configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
+/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!!
+See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */
+#define configMAX_SYSCALL_INTERRUPT_PRIORITY 	( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
+
+/* Normal assert() semantics without relying on the provision of an assert.h
+header file. */
+/* USER CODE BEGIN 1 */
+#define configASSERT( x ) if ((x) == 0) {taskDISABLE_INTERRUPTS(); for( ;; );}
+/* USER CODE END 1 */
+
+/* Definitions that map the FreeRTOS port interrupt handlers to their CMSIS
+standard names. */
+#define vPortSVCHandler    SVC_Handler
+#define xPortPendSVHandler PendSV_Handler
+
+/* IMPORTANT: After 10.3.1 update, Systick_Handler comes from NVIC (if SYS timebase = systick), otherwise from cmsis_os2.c */
+
+#define USE_CUSTOM_SYSTICK_HANDLER_IMPLEMENTATION 0
+
+/* USER CODE BEGIN Defines */
+/* Section where parameter definitions can be added (for instance, to override default ones in FreeRTOS.h) */
+/* USER CODE END Defines */
+
+#endif /* FREERTOS_CONFIG_H */
diff --git a/Core/Inc/crc.h b/Core/Inc/crc.h
new file mode 100644
index 0000000..1880cf8
--- /dev/null
+++ b/Core/Inc/crc.h
@@ -0,0 +1,52 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    crc.h
+  * @brief   This file contains all the function prototypes for
+  *          the crc.c file
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2022 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __CRC_H__
+#define __CRC_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+extern CRC_HandleTypeDef hcrc;
+
+/* USER CODE BEGIN Private defines */
+
+/* USER CODE END Private defines */
+
+void MX_CRC_Init(void);
+
+/* USER CODE BEGIN Prototypes */
+
+/* USER CODE END Prototypes */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CRC_H__ */
+
diff --git a/Core/Inc/dma2d.h b/Core/Inc/dma2d.h
new file mode 100644
index 0000000..5e25146
--- /dev/null
+++ b/Core/Inc/dma2d.h
@@ -0,0 +1,52 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    dma2d.h
+  * @brief   This file contains all the function prototypes for
+  *          the dma2d.c file
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2022 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __DMA2D_H__
+#define __DMA2D_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+extern DMA2D_HandleTypeDef hdma2d;
+
+/* USER CODE BEGIN Private defines */
+
+/* USER CODE END Private defines */
+
+void MX_DMA2D_Init(void);
+
+/* USER CODE BEGIN Prototypes */
+
+/* USER CODE END Prototypes */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __DMA2D_H__ */
+
diff --git a/Core/Inc/dsihost.h b/Core/Inc/dsihost.h
new file mode 100644
index 0000000..67726ac
--- /dev/null
+++ b/Core/Inc/dsihost.h
@@ -0,0 +1,52 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    dsihost.h
+  * @brief   This file contains all the function prototypes for
+  *          the dsihost.c file
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2022 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __DSIHOST_H__
+#define __DSIHOST_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+extern DSI_HandleTypeDef hdsi;
+
+/* USER CODE BEGIN Private defines */
+
+/* USER CODE END Private defines */
+
+void MX_DSIHOST_DSI_Init(void);
+
+/* USER CODE BEGIN Prototypes */
+
+/* USER CODE END Prototypes */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __DSIHOST_H__ */
+
diff --git a/Core/Inc/fmc.h b/Core/Inc/fmc.h
new file mode 100644
index 0000000..6300d21
--- /dev/null
+++ b/Core/Inc/fmc.h
@@ -0,0 +1,59 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * File Name          : FMC.h
+  * Description        : This file provides code for the configuration
+  *                      of the FMC peripheral.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2022 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __FMC_H
+#define __FMC_H
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+extern SDRAM_HandleTypeDef hsdram1;
+
+/* USER CODE BEGIN Private defines */
+
+/* USER CODE END Private defines */
+
+void MX_FMC_Init(void);
+void HAL_SDRAM_MspInit(SDRAM_HandleTypeDef* hsdram);
+void HAL_SDRAM_MspDeInit(SDRAM_HandleTypeDef* hsdram);
+
+/* USER CODE BEGIN Prototypes */
+
+/* USER CODE END Prototypes */
+
+#ifdef __cplusplus
+}
+#endif
+#endif /*__FMC_H */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
diff --git a/Core/Inc/gpio.h b/Core/Inc/gpio.h
new file mode 100644
index 0000000..757cbd0
--- /dev/null
+++ b/Core/Inc/gpio.h
@@ -0,0 +1,49 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    gpio.h
+  * @brief   This file contains all the function prototypes for
+  *          the gpio.c file
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2022 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __GPIO_H__
+#define __GPIO_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* USER CODE BEGIN Private defines */
+
+/* USER CODE END Private defines */
+
+void MX_GPIO_Init(void);
+
+/* USER CODE BEGIN Prototypes */
+
+/* USER CODE END Prototypes */
+
+#ifdef __cplusplus
+}
+#endif
+#endif /*__ GPIO_H__ */
+
diff --git a/Core/Inc/i2c.h b/Core/Inc/i2c.h
new file mode 100644
index 0000000..f5ae58a
--- /dev/null
+++ b/Core/Inc/i2c.h
@@ -0,0 +1,55 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    i2c.h
+  * @brief   This file contains all the function prototypes for
+  *          the i2c.c file
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2022 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __I2C_H__
+#define __I2C_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+extern I2C_HandleTypeDef hi2c1;
+
+extern I2C_HandleTypeDef hi2c2;
+
+/* USER CODE BEGIN Private defines */
+
+/* USER CODE END Private defines */
+
+void MX_I2C1_Init(void);
+void MX_I2C2_Init(void);
+
+/* USER CODE BEGIN Prototypes */
+
+/* USER CODE END Prototypes */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __I2C_H__ */
+
diff --git a/Core/Inc/image_320x240_argb8888.h b/Core/Inc/image_320x240_argb8888.h
new file mode 100644
index 0000000..b56e131
--- /dev/null
+++ b/Core/Inc/image_320x240_argb8888.h
@@ -0,0 +1,76840 @@
+/**
+  ******************************************************************************
+  * @file    LCD_DSI/LCD_DSI_VideoMode_SingleBuffer/Inc/image_320x240_argb8888.h
+  * @author  MCD Application Team
+  * @brief   This file contains ARGB8888 image 320x240.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __IMAGE_320x240_ARGB8888_H
+#define __IMAGE_320x240_ARGB8888_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+
+const uint32_t image_320x240_argb8888[76800] =
+{
+0xFF254888,
+0xFF254888,
+0xFF254888,
+0xFF264989,
+0xFF264989,
+0xFF274A8A,
+0xFF274A8A,
+0xFF274A8A,
+0xFF254B8A,
+0xFF254B8A,
+0xFF254B8C,
+0xFF254B8C,
+0xFF254B8C,
+0xFF264C8D,
+0xFF264C8D,
+0xFF254C8D,
+0xFF264D90,
+0xFF254E90,
+0xFF254E90,
+0xFF264F91,
+0xFF264F91,
+0xFF264F91,
+0xFF264E93,
+0xFF274F94,
+0xFF285095,
+0xFF285095,
+0xFF285095,
+0xFF285095,
+0xFF285095,
+0xFF285095,
+0xFF285095,
+0xFF295196,
+0xFF2A5097,
+0xFF2A5097,
+0xFF2A5097,
+0xFF2A5097,
+0xFF2A5097,
+0xFF2B5198,
+0xFF2A5298,
+0xFF2A5298,
+0xFF2B539B,
+0xFF2B539B,
+0xFF2A549C,
+0xFF2A549C,
+0xFF2A549C,
+0xFF2A549C,
+0xFF2B559D,
+0xFF2B559D,
+0xFF28549B,
+0xFF29559C,
+0xFF2A569F,
+0xFF2A569F,
+0xFF28579F,
+0xFF28579F,
+0xFF28579F,
+0xFF2958A0,
+0xFF2958A0,
+0xFF2958A0,
+0xFF2958A0,
+0xFF2958A0,
+0xFF2958A0,
+0xFF2A59A1,
+0xFF2A59A1,
+0xFF2A59A1,
+0xFF2959A3,
+0xFF2959A3,
+0xFF2A5AA4,
+0xFF2A5AA4,
+0xFF2A5AA4,
+0xFF2A5AA4,
+0xFF2A5AA4,
+0xFF2A5AA4,
+0xFF2A5AA4,
+0xFF2B5BA5,
+0xFF2B5BA5,
+0xFF2B5BA5,
+0xFF2B5BA7,
+0xFF2B5BA7,
+0xFF2C5CA8,
+0xFF2C5CA8,
+0xFF2C5CA6,
+0xFF2C5CA6,
+0xFF2C5CA6,
+0xFF2C5CA6,
+0xFF2C5CA6,
+0xFF2C5CA6,
+0xFF2C5CA6,
+0xFF2C5CA6,
+0xFF2C5CA6,
+0xFF2D5DA7,
+0xFF2D5DA7,
+0xFF2D5DA7,
+0xFF2D5FA8,
+0xFF2D5FA8,
+0xFF2D5FA8,
+0xFF2D5FA8,
+0xFF2E5EA8,
+0xFF2E5EA8,
+0xFF2E5EA8,
+0xFF2E5EA8,
+0xFF2E5EA8,
+0xFF2F5FA9,
+0xFF2F5FAB,
+0xFF2F5FAB,
+0xFF2E5EAA,
+0xFF2E5EAA,
+0xFF2E5EAA,
+0xFF2E5EAA,
+0xFF2D5EAA,
+0xFF2D5EAA,
+0xFF2E5FAB,
+0xFF2E5FAB,
+0xFF2C60AB,
+0xFF2C60AB,
+0xFF2C60AB,
+0xFF2C60AB,
+0xFF2C60AB,
+0xFF2C60AB,
+0xFF2C60AB,
+0xFF2C60AB,
+0xFF2C60AB,
+0xFF2C60AB,
+0xFF2C60AB,
+0xFF2C60AB,
+0xFF2D61AC,
+0xFF2D61AC,
+0xFF2D61AC,
+0xFF2D61AC,
+0xFF2C60AB,
+0xFF2C60AB,
+0xFF2C60AB,
+0xFF2C60AB,
+0xFF2C60AB,
+0xFF2C60AB,
+0xFF2C60AB,
+0xFF2C60AB,
+0xFF2D61AC,
+0xFF2D61AC,
+0xFF2D61AC,
+0xFF2D61AC,
+0xFF2D61AC,
+0xFF2D61AC,
+0xFF2D61AC,
+0xFF2E62AD,
+0xFF2D61AC,
+0xFF2D61AC,
+0xFF2D61AC,
+0xFF2E62AD,
+0xFF2E62AD,
+0xFF2E62AD,
+0xFF2E62AD,
+0xFF2D61AC,
+0xFF2D61AC,
+0xFF2D61AC,
+0xFF2E62AD,
+0xFF2E62AD,
+0xFF2E62AD,
+0xFF2E62AD,
+0xFF2E62AD,
+0xFF2E62AD,
+0xFF2D63AD,
+0xFF2D63AD,
+0xFF2D63AD,
+0xFF2D63AD,
+0xFF2D63AD,
+0xFF2D63AD,
+0xFF2D63AD,
+0xFF2D63AD,
+0xFF2D63AD,
+0xFF2D63AD,
+0xFF2C62AC,
+0xFF2D63AD,
+0xFF2D63AD,
+0xFF2E64AE,
+0xFF2D63AD,
+0xFF2D63AD,
+0xFF2D62AE,
+0xFF2D62AE,
+0xFF2D62AE,
+0xFF2D62AE,
+0xFF2D62AE,
+0xFF2D62AE,
+0xFF2D62AE,
+0xFF2D62AE,
+0xFF2D62AE,
+0xFF2D62AE,
+0xFF2D62AE,
+0xFF2D62AE,
+0xFF2D62AE,
+0xFF2D62AE,
+0xFF2D62AE,
+0xFF2D62AE,
+0xFF2E63AF,
+0xFF2E63AF,
+0xFF2E63AF,
+0xFF2E63AF,
+0xFF2E63AF,
+0xFF2E63AF,
+0xFF2E63AF,
+0xFF2E63AF,
+0xFF2D62AE,
+0xFF2D62AE,
+0xFF2D62AE,
+0xFF2D62AE,
+0xFF2D62AE,
+0xFF2D62AE,
+0xFF2D62AE,
+0xFF2D62AE,
+0xFF2E63AF,
+0xFF2E63AF,
+0xFF2E63AF,
+0xFF2E63AF,
+0xFF2D62AE,
+0xFF2D62AE,
+0xFF2D62AE,
+0xFF2D62AE,
+0xFF2E63AF,
+0xFF2E63AF,
+0xFF2D62AE,
+0xFF2D62AE,
+0xFF2D62AE,
+0xFF2D62AE,
+0xFF2D62AE,
+0xFF2D62AE,
+0xFF2D62AE,
+0xFF2D62AE,
+0xFF2E62AE,
+0xFF2E62AE,
+0xFF2E62AE,
+0xFF2E62AE,
+0xFF2E62AE,
+0xFF2E62AE,
+0xFF2E62AE,
+0xFF2D61AD,
+0xFF2D61AD,
+0xFF2D61AD,
+0xFF2E62AE,
+0xFF2E62AE,
+0xFF2D61AD,
+0xFF2D61AD,
+0xFF2F60AD,
+0xFF2F60AD,
+0xFF2F60AD,
+0xFF2F60AD,
+0xFF2F60AD,
+0xFF2F60AD,
+0xFF2F60AD,
+0xFF2F60AD,
+0xFF2D61AD,
+0xFF2C60AC,
+0xFF2C60AC,
+0xFF2C60AC,
+0xFF2C60AB,
+0xFF2C60AB,
+0xFF2C60AB,
+0xFF2B5FAA,
+0xFF2E5FAB,
+0xFF2D5EAA,
+0xFF2D5EAA,
+0xFF2D5EAA,
+0xFF2D5EAA,
+0xFF2D5EAA,
+0xFF2D5EAA,
+0xFF2C5DA9,
+0xFF2C5DA9,
+0xFF2B5CA8,
+0xFF2B5CA8,
+0xFF2B5CA8,
+0xFF2B5CA8,
+0xFF2B5CA8,
+0xFF2B5CA8,
+0xFF2B5CA8,
+0xFF2C5CA8,
+0xFF2B5BA7,
+0xFF2B5BA7,
+0xFF2A5AA6,
+0xFF2A5AA6,
+0xFF2A5AA6,
+0xFF2A5AA6,
+0xFF2A5AA6,
+0xFF2A5AA6,
+0xFF2959A5,
+0xFF2959A5,
+0xFF2959A5,
+0xFF2858A4,
+0xFF2858A4,
+0xFF2957A4,
+0xFF2957A2,
+0xFF2957A2,
+0xFF2958A0,
+0xFF2958A0,
+0xFF2958A0,
+0xFF28579F,
+0xFF28579F,
+0xFF28579F,
+0xFF28579F,
+0xFF29559E,
+0xFF29559E,
+0xFF28549D,
+0xFF28549D,
+0xFF27539C,
+0xFF27539C,
+0xFF27539C,
+0xFF27539C,
+0xFF2A529A,
+0xFF295199,
+0xFF295199,
+0xFF295199,
+0xFF295199,
+0xFF285098,
+0xFF285098,
+0xFF285098,
+0xFF285096,
+0xFF285096,
+0xFF285096,
+0xFF285096,
+0xFF274F95,
+0xFF274F95,
+0xFF274F95,
+0xFF274F95,
+0xFF254888,
+0xFF264989,
+0xFF264989,
+0xFF264989,
+0xFF274A8A,
+0xFF274A8A,
+0xFF274A8A,
+0xFF284B8B,
+0xFF264C8B,
+0xFF264C8B,
+0xFF264C8D,
+0xFF264C8D,
+0xFF264C8D,
+0xFF264C8D,
+0xFF274D8E,
+0xFF264D8E,
+0xFF264D90,
+0xFF254E90,
+0xFF264F91,
+0xFF264F91,
+0xFF264F91,
+0xFF275092,
+0xFF274F94,
+0xFF274F94,
+0xFF285095,
+0xFF285095,
+0xFF285095,
+0xFF285095,
+0xFF285095,
+0xFF285095,
+0xFF295196,
+0xFF295196,
+0xFF2A5097,
+0xFF2A5097,
+0xFF2A5097,
+0xFF2B5198,
+0xFF2B5198,
+0xFF2B5198,
+0xFF2B5399,
+0xFF2B5399,
+0xFF2B539B,
+0xFF2B539B,
+0xFF29539B,
+0xFF2A549C,
+0xFF2A549C,
+0xFF2A549C,
+0xFF2A549C,
+0xFF2A549C,
+0xFF28549B,
+0xFF29559C,
+0xFF2A569F,
+0xFF2A569F,
+0xFF28579F,
+0xFF28579F,
+0xFF28579F,
+0xFF2958A0,
+0xFF2958A0,
+0xFF2958A0,
+0xFF2958A0,
+0xFF2A59A1,
+0xFF2A59A1,
+0xFF2A59A1,
+0xFF2A59A1,
+0xFF2A59A1,
+0xFF2959A3,
+0xFF2A5AA4,
+0xFF2A5AA4,
+0xFF2A5AA4,
+0xFF2A5AA4,
+0xFF2A5AA4,
+0xFF2A5AA4,
+0xFF2A5AA4,
+0xFF2B5BA5,
+0xFF2B5BA5,
+0xFF2B5BA5,
+0xFF2C5CA6,
+0xFF2C5CA8,
+0xFF2C5CA8,
+0xFF2C5CA8,
+0xFF2C5CA8,
+0xFF2D5DA7,
+0xFF2D5DA7,
+0xFF2D5DA7,
+0xFF2D5DA7,
+0xFF2D5DA7,
+0xFF2D5DA7,
+0xFF2D5DA7,
+0xFF2D5DA7,
+0xFF2D5DA7,
+0xFF2D5DA7,
+0xFF2E5EA8,
+0xFF2E5EA8,
+0xFF2D5FA8,
+0xFF2D5FA8,
+0xFF2D5FA8,
+0xFF2D5FA8,
+0xFF2E5EA8,
+0xFF2E5EA8,
+0xFF2E5EA8,
+0xFF2F5FA9,
+0xFF2F5FA9,
+0xFF2F5FA9,
+0xFF2F5FAB,
+0xFF2F5FAB,
+0xFF2F5FAB,
+0xFF2F5FAB,
+0xFF2F5FAB,
+0xFF2F5FAB,
+0xFF2E5FAB,
+0xFF2E5FAB,
+0xFF2E5FAB,
+0xFF2E5FAB,
+0xFF2C60AB,
+0xFF2C60AB,
+0xFF2C60AB,
+0xFF2C60AB,
+0xFF2C60AB,
+0xFF2C60AB,
+0xFF2C60AB,
+0xFF2C60AB,
+0xFF2D61AC,
+0xFF2D61AC,
+0xFF2D61AC,
+0xFF2D61AC,
+0xFF2D61AC,
+0xFF2D61AC,
+0xFF2D61AC,
+0xFF2D61AC,
+0xFF2D61AC,
+0xFF2D61AC,
+0xFF2D61AC,
+0xFF2D61AC,
+0xFF2D61AC,
+0xFF2D61AC,
+0xFF2D61AC,
+0xFF2D61AC,
+0xFF2D61AC,
+0xFF2D61AC,
+0xFF2D61AC,
+0xFF2D61AC,
+0xFF2D61AC,
+0xFF2E62AD,
+0xFF2E62AD,
+0xFF2E62AD,
+0xFF2E62AD,
+0xFF2E62AD,
+0xFF2E62AD,
+0xFF2E62AD,
+0xFF2E62AD,
+0xFF2E62AD,
+0xFF2E62AD,
+0xFF2E62AD,
+0xFF2E62AD,
+0xFF2E62AD,
+0xFF2E62AD,
+0xFF2E62AD,
+0xFF2E62AD,
+0xFF2E62AD,
+0xFF2E62AD,
+0xFF2E62AD,
+0xFF2D63AD,
+0xFF2D63AD,
+0xFF2D63AD,
+0xFF2D63AD,
+0xFF2D63AD,
+0xFF2D63AD,
+0xFF2D63AD,
+0xFF2D63AD,
+0xFF2E64AE,
+0xFF2E64AE,
+0xFF2E64AE,
+0xFF2E64AE,
+0xFF2F65AF,
+0xFF2F65AF,
+0xFF2E64AE,
+0xFF2E64AE,
+0xFF2E63AF,
+0xFF2E63AF,
+0xFF2E63AF,
+0xFF2E63AF,
+0xFF2E63AF,
+0xFF2E63AF,
+0xFF2E63AF,
+0xFF2E63AF,
+0xFF2E63AF,
+0xFF2E63AF,
+0xFF2E63AF,
+0xFF2E63AF,
+0xFF2E63AF,
+0xFF2E63AF,
+0xFF2E63AF,
+0xFF2E63AF,
+0xFF2E63AF,
+0xFF2E63AF,
+0xFF2E63AF,
+0xFF2E63AF,
+0xFF2E63AF,
+0xFF2E63AF,
+0xFF2E63AF,
+0xFF2E63AF,
+0xFF2E63AF,
+0xFF2E63AF,
+0xFF2E63AF,
+0xFF2E63AF,
+0xFF2E63AF,
+0xFF2E63AF,
+0xFF2E63AF,
+0xFF2E63AF,
+0xFF2E63AF,
+0xFF2E63AF,
+0xFF2E63AF,
+0xFF2E63AF,
+0xFF2E63AF,
+0xFF2E63AF,
+0xFF2E63AF,
+0xFF2E63AF,
+0xFF2E63AF,
+0xFF2E63AF,
+0xFF2E63AF,
+0xFF2E63AF,
+0xFF2E63AF,
+0xFF2D62AE,
+0xFF2D62AE,
+0xFF2D62AE,
+0xFF2D62AE,
+0xFF2D62AE,
+0xFF2E62AE,
+0xFF2E62AE,
+0xFF2E62AE,
+0xFF2E62AE,
+0xFF2E62AE,
+0xFF2E62AE,
+0xFF2E62AE,
+0xFF2E62AE,
+0xFF2D61AD,
+0xFF2D61AD,
+0xFF2E62AE,
+0xFF2E62AE,
+0xFF2E62AE,
+0xFF2D61AD,
+0xFF2F60AD,
+0xFF2F60AD,
+0xFF2F60AD,
+0xFF2F60AD,
+0xFF2F60AD,
+0xFF2F60AD,
+0xFF2F60AD,
+0xFF2F60AD,
+0xFF2D61AD,
+0xFF2C60AC,
+0xFF2C60AC,
+0xFF2C60AC,
+0xFF2C60AB,
+0xFF2C60AB,
+0xFF2C60AB,
+0xFF2B5FAA,
+0xFF2E5FAB,
+0xFF2E5FAB,
+0xFF2D5EAA,
+0xFF2D5EAA,
+0xFF2E5FAB,
+0xFF2E5FAB,
+0xFF2D5EAA,
+0xFF2D5EAA,
+0xFF2D5EAA,
+0xFF2C5DA9,
+0xFF2C5DA9,
+0xFF2C5DA9,
+0xFF2C5DA9,
+0xFF2C5DA9,
+0xFF2C5DA9,
+0xFF2C5DA9,
+0xFF2C5CA8,
+0xFF2C5CA8,
+0xFF2B5BA7,
+0xFF2B5BA7,
+0xFF2B5BA7,
+0xFF2B5BA7,
+0xFF2B5BA7,
+0xFF2A5AA6,
+0xFF2B5BA7,
+0xFF2A5AA6,
+0xFF2A5AA6,
+0xFF2A5AA6,
+0xFF2959A5,
+0xFF2959A5,
+0xFF2A58A5,
+0xFF2A58A5,
+0xFF2957A2,
+0xFF2958A0,
+0xFF2958A0,
+0xFF2958A0,
+0xFF28579F,
+0xFF28579F,
+0xFF28579F,
+0xFF28579F,
+0xFF2A569F,
+0xFF2A569F,
+0xFF29559E,
+0xFF29559E,
+0xFF28549D,
+0xFF28549D,
+0xFF28549D,
+0xFF28549D,
+0xFF2B539B,
+0xFF2A529A,
+0xFF2A529A,
+0xFF2A529A,
+0xFF2A529A,
+0xFF295199,
+0xFF295199,
+0xFF295199,
+0xFF285096,
+0xFF285096,
+0xFF285096,
+0xFF285096,
+0xFF285096,
+0xFF274F95,
+0xFF274F95,
+0xFF274F95,
+0xFF264989,
+0xFF264989,
+0xFF274A8A,
+0xFF274A8A,
+0xFF274A8A,
+0xFF284B8B,
+0xFF284B8B,
+0xFF284B8B,
+0xFF264C8D,
+0xFF264C8D,
+0xFF264C8D,
+0xFF264C8D,
+0xFF274D8E,
+0xFF274D8E,
+0xFF264D8E,
+0xFF274E8F,
+0xFF264D90,
+0xFF274E91,
+0xFF274E91,
+0xFF274E91,
+0xFF284F92,
+0xFF284F92,
+0xFF295095,
+0xFF295095,
+0xFF295095,
+0xFF295095,
+0xFF295095,
+0xFF295095,
+0xFF2A5196,
+0xFF2A5196,
+0xFF2A5097,
+0xFF2A5097,
+0xFF2B5198,
+0xFF2B5198,
+0xFF2B5198,
+0xFF2B5198,
+0xFF2B5399,
+0xFF2B5399,
+0xFF2C549C,
+0xFF2C549C,
+0xFF2C549C,
+0xFF2C549C,
+0xFF2A549C,
+0xFF2A549C,
+0xFF2A549C,
+0xFF2A549C,
+0xFF2A549C,
+0xFF2A549C,
+0xFF29559E,
+0xFF28579F,
+0xFF2958A0,
+0xFF2958A0,
+0xFF2958A0,
+0xFF2958A0,
+0xFF2958A0,
+0xFF2958A0,
+0xFF2A59A1,
+0xFF2A59A1,
+0xFF2A59A1,
+0xFF2A59A1,
+0xFF2A59A1,
+0xFF2B5AA2,
+0xFF2B5AA2,
+0xFF2B5AA2,
+0xFF2A5AA4,
+0xFF2A5AA4,
+0xFF2A5AA4,
+0xFF2A5AA4,
+0xFF2A5AA4,
+0xFF2B5BA5,
+0xFF2B5BA5,
+0xFF2B5BA5,
+0xFF2C5CA6,
+0xFF2C5CA6,
+0xFF2C5CA6,
+0xFF2C5CA6,
+0xFF2D5DA9,
+0xFF2D5DA9,
+0xFF2D5DA9,
+0xFF2D5DA9,
+0xFF2D5DA7,
+0xFF2D5DA7,
+0xFF2D5DA7,
+0xFF2D5DA7,
+0xFF2E5EA8,
+0xFF2E5EA8,
+0xFF2E5EA8,
+0xFF2E5EA8,
+0xFF2E5EA8,
+0xFF2E5EA8,
+0xFF2E60A9,
+0xFF2E60A9,
+0xFF2D5FA8,
+0xFF2D5FA8,
+0xFF2D5FA8,
+0xFF2D5FA8,
+0xFF2F5FA9,
+0xFF2F5FA9,
+0xFF2F5FA9,
+0xFF2F5FA9,
+0xFF2E5FAB,
+0xFF2E5FAB,
+0xFF2E5FAB,
+0xFF2E5FAB,
+0xFF2F60AC,
+0xFF2E5FAB,
+0xFF2E5FAB,
+0xFF2E5FAB,
+0xFF2E5FAB,
+0xFF2F60AC,
+0xFF2F60AC,
+0xFF2F60AC,
+0xFF2C60AB,
+0xFF2C60AB,
+0xFF2C60AB,
+0xFF2C60AB,
+0xFF2D61AC,
+0xFF2D61AC,
+0xFF2D61AC,
+0xFF2D61AC,
+0xFF2D61AC,
+0xFF2D61AC,
+0xFF2D61AC,
+0xFF2D61AC,
+0xFF2D61AC,
+0xFF2D61AC,
+0xFF2D61AC,
+0xFF2E62AD,
+0xFF2E62AD,
+0xFF2E62AD,
+0xFF2E62AD,
+0xFF2E62AD,
+0xFF2E62AD,
+0xFF2E62AD,
+0xFF2E62AD,
+0xFF2E62AD,
+0xFF2D61AC,
+0xFF2D61AC,
+0xFF2E62AD,
+0xFF2E62AD,
+0xFF2E62AD,
+0xFF2E62AD,
+0xFF2E62AD,
+0xFF2E62AD,
+0xFF2E62AD,
+0xFF2E62AD,
+0xFF2E62AD,
+0xFF2F63AE,
+0xFF2F63AE,
+0xFF2F63AE,
+0xFF2F63AE,
+0xFF2F63AE,
+0xFF2E62AD,
+0xFF2E62AD,
+0xFF2E62AD,
+0xFF2E62AD,
+0xFF2E62AD,
+0xFF2E62AD,
+0xFF2E62AD,
+0xFF2E62AD,
+0xFF2E63AF,
+0xFF2E63AF,
+0xFF2D62AE,
+0xFF2D62AE,
+0xFF2D62AE,
+0xFF2D62AE,
+0xFF2E63AF,
+0xFF2E63AF,
+0xFF2E63AF,
+0xFF2E63AF,
+0xFF2E63AF,
+0xFF2E63AF,
+0xFF2F64B0,
+0xFF2F64B0,
+0xFF2E63AF,
+0xFF2E63AF,
+0xFF2F64B0,
+0xFF2F64B0,
+0xFF2F64B0,
+0xFF2F64B0,
+0xFF2F64B0,
+0xFF2F64B0,
+0xFF2F64B0,
+0xFF2F64B0,
+0xFF2E63AF,
+0xFF2E63AF,
+0xFF2E63AF,
+0xFF2E63AF,
+0xFF2E63AF,
+0xFF2E63AF,
+0xFF2E63AF,
+0xFF2E63AF,
+0xFF2F64B0,
+0xFF2F64B0,
+0xFF2F64B0,
+0xFF2F64B0,
+0xFF2F64B0,
+0xFF2F64B0,
+0xFF2F64B0,
+0xFF2F64B0,
+0xFF2F64B0,
+0xFF2F64B0,
+0xFF2F64B0,
+0xFF2F64B0,
+0xFF2F64B0,
+0xFF2E63AF,
+0xFF2E63AF,
+0xFF2E63AF,
+0xFF2F64B0,
+0xFF2F64B0,
+0xFF2F64B0,
+0xFF2E63AF,
+0xFF2E63AF,
+0xFF2E63AF,
+0xFF2E63AF,
+0xFF2E63AF,
+0xFF2E63AF,
+0xFF2E63AF,
+0xFF2E63AF,
+0xFF2E63AF,
+0xFF2E63AF,
+0xFF2E63AF,
+0xFF2E63AF,
+0xFF2E63AF,
+0xFF2D62AE,
+0xFF2D62AE,
+0xFF2E63AF,
+0xFF2E63AF,
+0xFF2E63AF,
+0xFF2E63AF,
+0xFF2E62AE,
+0xFF2E62AE,
+0xFF2E62AE,
+0xFF2E62AE,
+0xFF2E62AE,
+0xFF2E62AE,
+0xFF2E62AE,
+0xFF2E62AE,
+0xFF2E62AE,
+0xFF2D61AD,
+0xFF3061AE,
+0xFF3061AE,
+0xFF2F60AD,
+0xFF2F60AD,
+0xFF2F60AD,
+0xFF2F60AD,
+0xFF2D61AD,
+0xFF2D61AD,
+0xFF2D61AD,
+0xFF2D61AD,
+0xFF2C60AC,
+0xFF2C60AC,
+0xFF2D61AC,
+0xFF2D61AC,
+0xFF2C60AB,
+0xFF2C60AB,
+0xFF2F60AC,
+0xFF2E5FAB,
+0xFF2E5FAB,
+0xFF2E5FAB,
+0xFF2E5FAB,
+0xFF2E5FAB,
+0xFF2D5EAA,
+0xFF2D5EAA,
+0xFF2D5EAA,
+0xFF2D5EAA,
+0xFF2D5EAA,
+0xFF2D5EAA,
+0xFF2C5DA9,
+0xFF2C5DA9,
+0xFF2C5DA9,
+0xFF2C5DA9,
+0xFF2C5DA9,
+0xFF2B5CA8,
+0xFF2B5CA8,
+0xFF2B5CA8,
+0xFF2C5CA8,
+0xFF2C5CA8,
+0xFF2B5BA7,
+0xFF2B5BA7,
+0xFF2A5AA6,
+0xFF2A5AA6,
+0xFF2A5AA6,
+0xFF2959A5,
+0xFF2959A5,
+0xFF2959A5,
+0xFF2959A5,
+0xFF2959A5,
+0xFF2A58A3,
+0xFF2A58A3,
+0xFF2957A2,
+0xFF2957A2,
+0xFF2957A2,
+0xFF2856A1,
+0xFF28579F,
+0xFF28579F,
+0xFF2B57A0,
+0xFF2A569F,
+0xFF2A569F,
+0xFF2A569F,
+0xFF29559E,
+0xFF29559E,
+0xFF29559E,
+0xFF29559E,
+0xFF2B539B,
+0xFF2B539B,
+0xFF2B539B,
+0xFF2B539B,
+0xFF2A529A,
+0xFF2A529A,
+0xFF2A529A,
+0xFF2A529A,
+0xFF285098,
+0xFF285098,
+0xFF285096,
+0xFF285096,
+0xFF285096,
+0xFF285096,
+0xFF274F95,
+0xFF274F95,
+0xFF274A8A,
+0xFF274A8A,
+0xFF274A8A,
+0xFF274A8A,
+0xFF284B8B,
+0xFF284B8B,
+0xFF284B8B,
+0xFF284B8B,
+0xFF264C8D,
+0xFF264C8D,
+0xFF274D8E,
+0xFF274D8E,
+0xFF274D8E,
+0xFF284E8F,
+0xFF274E8F,
+0xFF274E8F,
+0xFF274E91,
+0xFF274E91,
+0xFF284F92,
+0xFF284F92,
+0xFF295093,
+0xFF295093,
+0xFF2A5196,
+0xFF2A5196,
+0xFF2A5196,
+0xFF2A5196,
+0xFF2A5196,
+0xFF2A5196,
+0xFF2A5196,
+0xFF2B5297,
+0xFF2B5198,
+0xFF2B5198,
+0xFF2C5299,
+0xFF2C5299,
+0xFF2C5299,
+0xFF2C5299,
+0xFF2B5399,
+0xFF2C549A,
+0xFF2C549C,
+0xFF2C549C,
+0xFF2D559D,
+0xFF2D559D,
+0xFF2B559D,
+0xFF2B559D,
+0xFF2B559D,
+0xFF2B559D,
+0xFF2B559D,
+0xFF2A569D,
+0xFF28579F,
+0xFF2958A0,
+0xFF2A59A1,
+0xFF2A59A1,
+0xFF2A59A1,
+0xFF2A59A1,
+0xFF2A59A1,
+0xFF2A59A1,
+0xFF2A59A1,
+0xFF2A59A1,
+0xFF2A59A1,
+0xFF2B5AA2,
+0xFF2B5AA2,
+0xFF2B5AA2,
+0xFF2B5AA2,
+0xFF2B5AA2,
+0xFF2A5AA4,
+0xFF2A5AA4,
+0xFF2B5BA5,
+0xFF2B5BA5,
+0xFF2B5BA5,
+0xFF2B5BA5,
+0xFF2B5BA5,
+0xFF2C5CA6,
+0xFF2D5DA7,
+0xFF2D5DA7,
+0xFF2D5DA7,
+0xFF2D5DA7,
+0xFF2D5DA9,
+0xFF2D5DA9,
+0xFF2D5DA9,
+0xFF2D5DA9,
+0xFF2E5EA8,
+0xFF2E5EA8,
+0xFF2E5EA8,
+0xFF2E5EA8,
+0xFF2E5EA8,
+0xFF2E5EA8,
+0xFF2E5EA8,
+0xFF2E5EA8,
+0xFF2F5FA9,
+0xFF2F5FA9,
+0xFF2E60A9,
+0xFF2E60A9,
+0xFF2E60A9,
+0xFF2E60A9,
+0xFF2E60A9,
+0xFF2E60A9,
+0xFF2F5FA9,
+0xFF2F5FA9,
+0xFF2F5FA9,
+0xFF2F5FA9,
+0xFF2E5FAB,
+0xFF2E5FAB,
+0xFF2E5FAB,
+0xFF2E5FAB,
+0xFF2F60AC,
+0xFF2F60AC,
+0xFF2F60AC,
+0xFF2F60AC,
+0xFF2F60AC,
+0xFF2F60AC,
+0xFF2F60AC,
+0xFF2F60AC,
+0xFF2D61AC,
+0xFF2D61AC,
+0xFF2D61AC,
+0xFF2D61AC,
+0xFF2D61AC,
+0xFF2D61AC,
+0xFF2D61AC,
+0xFF2D61AC,
+0xFF2D61AC,
+0xFF2D61AC,
+0xFF2D61AC,
+0xFF2E62AD,
+0xFF2E62AD,
+0xFF2E62AD,
+0xFF2E62AD,
+0xFF2E62AD,
+0xFF2E62AD,
+0xFF2E62AD,
+0xFF2E62AD,
+0xFF2E62AD,
+0xFF2E62AD,
+0xFF2E62AD,
+0xFF2E62AD,
+0xFF2E62AD,
+0xFF2E62AD,
+0xFF2E62AD,
+0xFF2E62AD,
+0xFF2E62AD,
+0xFF2E62AD,
+0xFF2E62AD,
+0xFF2E62AD,
+0xFF2E62AD,
+0xFF2E62AD,
+0xFF2F63AE,
+0xFF2F63AE,
+0xFF2F63AE,
+0xFF2F63AE,
+0xFF2F63AE,
+0xFF2F63AE,
+0xFF2F63AE,
+0xFF2F63AE,
+0xFF2F63AE,
+0xFF2F63AE,
+0xFF2F63AE,
+0xFF2F63AE,
+0xFF2F63AE,
+0xFF2F63AE,
+0xFF2F63AE,
+0xFF2E63AF,
+0xFF2E63AF,
+0xFF2E63AF,
+0xFF2E63AF,
+0xFF2E63AF,
+0xFF2E63AF,
+0xFF2E63AF,
+0xFF2E63AF,
+0xFF2E63AF,
+0xFF2E63AF,
+0xFF2E63AF,
+0xFF2E63AF,
+0xFF2E63AF,
+0xFF2E63AF,
+0xFF2E63AF,
+0xFF2E63AF,
+0xFF2E63AF,
+0xFF2E63AF,
+0xFF2E63AF,
+0xFF2E63AF,
+0xFF2E63AF,
+0xFF2E63AF,
+0xFF2E63AF,
+0xFF2E63AF,
+0xFF2F64B0,
+0xFF2F64B0,
+0xFF2F64B0,
+0xFF2F64B0,
+0xFF2F64B0,
+0xFF2F64B0,
+0xFF2F64B0,
+0xFF2F64B0,
+0xFF2F64B0,
+0xFF2F64B0,
+0xFF2F64B0,
+0xFF2F64B0,
+0xFF2F64B0,
+0xFF2F64B0,
+0xFF2F64B0,
+0xFF2F64B0,
+0xFF3065B1,
+0xFF2F64B0,
+0xFF2F64B0,
+0xFF2F64B0,
+0xFF2F64B0,
+0xFF2F64B0,
+0xFF2F64B0,
+0xFF2F64B0,
+0xFF2F64B0,
+0xFF2F64B0,
+0xFF2F64B0,
+0xFF2F64B0,
+0xFF2F64B0,
+0xFF2F64B0,
+0xFF2F64B0,
+0xFF2F64B0,
+0xFF2F64B0,
+0xFF2F64B0,
+0xFF2F64B0,
+0xFF2E63AF,
+0xFF2E63AF,
+0xFF2E63AF,
+0xFF2E63AF,
+0xFF2E63AF,
+0xFF2E63AF,
+0xFF2E63AF,
+0xFF2E63AF,
+0xFF2E63AF,
+0xFF2E63AF,
+0xFF2E63AF,
+0xFF2F63AF,
+0xFF2F63AF,
+0xFF2F63AF,
+0xFF2F63AF,
+0xFF2E62AE,
+0xFF2E62AE,
+0xFF2F63AF,
+0xFF2F63AF,
+0xFF2E62AE,
+0xFF2E62AE,
+0xFF3061AE,
+0xFF3061AE,
+0xFF3061AE,
+0xFF3061AE,
+0xFF3061AE,
+0xFF3061AE,
+0xFF2E62AE,
+0xFF2E62AE,
+0xFF2E62AE,
+0xFF2D61AD,
+0xFF2D61AD,
+0xFF2D61AD,
+0xFF2D61AC,
+0xFF2D61AC,
+0xFF2D61AC,
+0xFF2C60AB,
+0xFF2E5FAB,
+0xFF2E5FAB,
+0xFF2E5FAB,
+0xFF2E5FAB,
+0xFF2E5FAB,
+0xFF2E5FAB,
+0xFF2D5EAA,
+0xFF2D5EAA,
+0xFF2D5EAA,
+0xFF2D5EAA,
+0xFF2D5EAA,
+0xFF2D5EAA,
+0xFF2C5DA9,
+0xFF2C5DA9,
+0xFF2C5DA9,
+0xFF2C5DA9,
+0xFF2C5DA9,
+0xFF2C5DA9,
+0xFF2C5DA9,
+0xFF2C5DA9,
+0xFF2D5DA9,
+0xFF2D5DA9,
+0xFF2C5CA8,
+0xFF2B5BA7,
+0xFF2B5BA7,
+0xFF2A5AA6,
+0xFF2A5AA6,
+0xFF2A5AA6,
+0xFF2959A5,
+0xFF2959A5,
+0xFF2959A5,
+0xFF2959A5,
+0xFF2A58A3,
+0xFF2A58A3,
+0xFF2A58A3,
+0xFF2A58A3,
+0xFF2957A2,
+0xFF2957A2,
+0xFF2958A0,
+0xFF2958A0,
+0xFF2A569F,
+0xFF2A569F,
+0xFF2A569F,
+0xFF29559E,
+0xFF29559E,
+0xFF29559E,
+0xFF29559E,
+0xFF29559E,
+0xFF29539B,
+0xFF2B539B,
+0xFF2B539B,
+0xFF2B539B,
+0xFF2A529A,
+0xFF2A529A,
+0xFF2A529A,
+0xFF2A529A,
+0xFF295199,
+0xFF295199,
+0xFF295197,
+0xFF295197,
+0xFF285096,
+0xFF285096,
+0xFF285096,
+0xFF285096,
+0xFF274A8A,
+0xFF274A8A,
+0xFF274A8A,
+0xFF274A8A,
+0xFF284B8B,
+0xFF284B8B,
+0xFF264C8D,
+0xFF264C8D,
+0xFF264C8D,
+0xFF264C8D,
+0xFF264D90,
+0xFF264D90,
+0xFF264D90,
+0xFF274E91,
+0xFF274E91,
+0xFF284F92,
+0xFF284F92,
+0xFF284F92,
+0xFF284F94,
+0xFF295095,
+0xFF295095,
+0xFF2A5196,
+0xFF2A5196,
+0xFF2A5196,
+0xFF2B5297,
+0xFF2B5297,
+0xFF2B5198,
+0xFF2B5198,
+0xFF2B5198,
+0xFF2B5198,
+0xFF2C5299,
+0xFF2C5299,
+0xFF2B539B,
+0xFF2B539B,
+0xFF2B539B,
+0xFF2B539B,
+0xFF2C549C,
+0xFF2C549C,
+0xFF2A549C,
+0xFF2A549C,
+0xFF2C569E,
+0xFF2C569E,
+0xFF2C569E,
+0xFF2C569E,
+0xFF2B579E,
+0xFF2B579E,
+0xFF2B579E,
+0xFF2B579E,
+0xFF2958A0,
+0xFF2958A0,
+0xFF2A59A1,
+0xFF2A59A1,
+0xFF2A59A1,
+0xFF2A59A1,
+0xFF2A59A1,
+0xFF2A59A1,
+0xFF2A59A1,
+0xFF2B5AA2,
+0xFF2B5AA2,
+0xFF2B5AA2,
+0xFF2B5AA2,
+0xFF2C5BA3,
+0xFF2C5BA3,
+0xFF2C5BA3,
+0xFF2C5AA5,
+0xFF2C5AA5,
+0xFF2C5AA5,
+0xFF2D5BA6,
+0xFF2D5BA6,
+0xFF2D5BA6,
+0xFF2C5CA6,
+0xFF2D5DA7,
+0xFF2D5DA7,
+0xFF2D5DA7,
+0xFF2D5DA7,
+0xFF2D5DA7,
+0xFF2D5DA9,
+0xFF2E5EAA,
+0xFF2E5EAA,
+0xFF2E5EAA,
+0xFF2E5EA8,
+0xFF2E5EA8,
+0xFF2E5EA8,
+0xFF2E5EA8,
+0xFF2E5EA8,
+0xFF2E5EA8,
+0xFF2D5FA8,
+0xFF2D5FA8,
+0xFF2E60A9,
+0xFF2E60A9,
+0xFF2E60A9,
+0xFF2F61AA,
+0xFF2F61AA,
+0xFF2F61AA,
+0xFF2F61AA,
+0xFF2F61AA,
+0xFF2E60A9,
+0xFF2E60A9,
+0xFF2E5FAB,
+0xFF2E5FAB,
+0xFF2E5FAB,
+0xFF2E5FAB,
+0xFF2E5FAB,
+0xFF2F60AC,
+0xFF2F60AC,
+0xFF2F60AC,
+0xFF2F60AC,
+0xFF2F60AC,
+0xFF2D61AC,
+0xFF2D61AC,
+0xFF2D61AC,
+0xFF2D61AC,
+0xFF2D61AC,
+0xFF2D61AC,
+0xFF2D61AC,
+0xFF2D61AC,
+0xFF2E62AD,
+0xFF2E62AD,
+0xFF2E62AD,
+0xFF2E62AD,
+0xFF2E62AD,
+0xFF2E62AD,
+0xFF2E62AD,
+0xFF2E62AD,
+0xFF2E62AD,
+0xFF2E62AD,
+0xFF2E62AD,
+0xFF2E62AD,
+0xFF2E62AD,
+0xFF2E62AD,
+0xFF2E62AD,
+0xFF2E62AD,
+0xFF2E62AD,
+0xFF2E62AD,
+0xFF2E62AD,
+0xFF2E62AD,
+0xFF2F63AE,
+0xFF2F63AE,
+0xFF2F63AE,
+0xFF2F63AE,
+0xFF2F63AE,
+0xFF2F63AE,
+0xFF2F63AE,
+0xFF2F63AE,
+0xFF2E62AD,
+0xFF2F63AE,
+0xFF2F63AE,
+0xFF2F63AE,
+0xFF2F63AE,
+0xFF2F63AE,
+0xFF2F63AE,
+0xFF2F63AE,
+0xFF2F63AE,
+0xFF2F63AE,
+0xFF2F63AE,
+0xFF2F63AE,
+0xFF2F63AE,
+0xFF2F63AE,
+0xFF2F63AE,
+0xFF2F63AE,
+0xFF2F64B0,
+0xFF2F64B0,
+0xFF2E63AF,
+0xFF2E63AF,
+0xFF2E63AF,
+0xFF2E63AF,
+0xFF2F64B0,
+0xFF2F64B0,
+0xFF2F64B0,
+0xFF2F64B0,
+0xFF2F64B0,
+0xFF2F64B0,
+0xFF2F64B0,
+0xFF2F64B0,
+0xFF2F64B0,
+0xFF2F64B0,
+0xFF2F64B0,
+0xFF2F64B0,
+0xFF2F64B0,
+0xFF2F64B0,
+0xFF2F64B0,
+0xFF2F64B0,
+0xFF2F64B0,
+0xFF2F64B0,
+0xFF2F64B0,
+0xFF2F64B0,
+0xFF2F64B0,
+0xFF2F64B0,
+0xFF2F64B0,
+0xFF2F64B0,
+0xFF2F64B0,
+0xFF2F64B0,
+0xFF2F64B0,
+0xFF2F64B0,
+0xFF2F64B0,
+0xFF2F64B0,
+0xFF2F64B0,
+0xFF2F64B0,
+0xFF2F64B0,
+0xFF2F64B0,
+0xFF2F64B0,
+0xFF2F64B0,
+0xFF2F64B0,
+0xFF2F64B0,
+0xFF2F64B0,
+0xFF3065B1,
+0xFF3065B1,
+0xFF3065B1,
+0xFF3065B1,
+0xFF3065B1,
+0xFF3065B1,
+0xFF3065B1,
+0xFF3065B1,
+0xFF2F64B0,
+0xFF2F64B0,
+0xFF2F64B0,
+0xFF2F64B0,
+0xFF2F64B0,
+0xFF2F64B0,
+0xFF2F64B0,
+0xFF2F64B0,
+0xFF2F64B0,
+0xFF2F64B0,
+0xFF2F64B0,
+0xFF2F64B0,
+0xFF2F64B0,
+0xFF2F64B0,
+0xFF2F64B0,
+0xFF2F64B0,
+0xFF2E63AF,
+0xFF2E63AF,
+0xFF2E63AF,
+0xFF2F64B0,
+0xFF2E63AF,
+0xFF2F63AF,
+0xFF2F63AF,
+0xFF2F63AF,
+0xFF2F63AF,
+0xFF2F63AF,
+0xFF2E62AE,
+0xFF2F63AF,
+0xFF2F63AF,
+0xFF2E62AE,
+0xFF2E62AE,
+0xFF2E62AE,
+0xFF2E62AE,
+0xFF2E62AE,
+0xFF2E62AE,
+0xFF2E62AE,
+0xFF2E62AE,
+0xFF2D61AD,
+0xFF2D61AD,
+0xFF2E62AD,
+0xFF2E62AD,
+0xFF2D61AC,
+0xFF2D61AC,
+0xFF2C60AB,
+0xFF2C60AB,
+0xFF2C60AB,
+0xFF2C60AB,
+0xFF2C60AB,
+0xFF2C60AB,
+0xFF2B5FAA,
+0xFF2C60AB,
+0xFF2C60AB,
+0xFF2B5FAA,
+0xFF2B5FAA,
+0xFF2B5FAA,
+0xFF2B5FAA,
+0xFF2A5EA9,
+0xFF2A5EA9,
+0xFF2A5EA9,
+0xFF2C5DA9,
+0xFF2C5DA9,
+0xFF2C5DA9,
+0xFF2C5DA9,
+0xFF2C5DA9,
+0xFF2C5DA9,
+0xFF2B5CA8,
+0xFF2A5BA7,
+0xFF2B5CA8,
+0xFF2B5CA8,
+0xFF2B5CA8,
+0xFF2A5BA7,
+0xFF2A5BA7,
+0xFF2A5BA7,
+0xFF2B5BA7,
+0xFF2B5BA7,
+0xFF2A5AA6,
+0xFF2A5AA6,
+0xFF2B59A4,
+0xFF2A58A3,
+0xFF2A58A3,
+0xFF2A58A3,
+0xFF2957A2,
+0xFF2957A2,
+0xFF2958A0,
+0xFF28579F,
+0xFF28579F,
+0xFF28579F,
+0xFF29559E,
+0xFF29559E,
+0xFF29559E,
+0xFF29559E,
+0xFF29539D,
+0xFF29539D,
+0xFF29539B,
+0xFF29539B,
+0xFF28529A,
+0xFF28529A,
+0xFF28529A,
+0xFF28529A,
+0xFF2A529A,
+0xFF2A529A,
+0xFF295197,
+0xFF295197,
+0xFF295197,
+0xFF295197,
+0xFF294F96,
+0xFF294F96,
+0xFF274A8A,
+0xFF274A8A,
+0xFF274A8A,
+0xFF284B8B,
+0xFF284B8B,
+0xFF284B8B,
+0xFF264C8D,
+0xFF274D8E,
+0xFF274D8E,
+0xFF274D8E,
+0xFF264D90,
+0xFF264D90,
+0xFF274E91,
+0xFF274E91,
+0xFF284F92,
+0xFF284F92,
+0xFF295093,
+0xFF295093,
+0xFF295095,
+0xFF2A5196,
+0xFF2A5196,
+0xFF2A5196,
+0xFF2B5297,
+0xFF2B5297,
+0xFF2B5297,
+0xFF2B5297,
+0xFF2B5198,
+0xFF2B5198,
+0xFF2C5299,
+0xFF2C5299,
+0xFF2C5299,
+0xFF2D539A,
+0xFF2C549C,
+0xFF2C549C,
+0xFF2C549C,
+0xFF2C549C,
+0xFF2C549C,
+0xFF2C549C,
+0xFF2B559D,
+0xFF2B559D,
+0xFF2C569E,
+0xFF2C569E,
+0xFF2C569E,
+0xFF2C569E,
+0xFF2B579E,
+0xFF2B579E,
+0xFF2B579E,
+0xFF2B579E,
+0xFF2958A0,
+0xFF2958A0,
+0xFF2A59A1,
+0xFF2A59A1,
+0xFF2A59A1,
+0xFF2A59A1,
+0xFF2A59A1,
+0xFF2A59A1,
+0xFF2B5AA2,
+0xFF2B5AA2,
+0xFF2C5BA3,
+0xFF2C5BA3,
+0xFF2C5BA3,
+0xFF2C5BA3,
+0xFF2D5CA4,
+0xFF2D5CA4,
+0xFF2D5BA6,
+0xFF2D5BA6,
+0xFF2D5BA6,
+0xFF2E5CA7,
+0xFF2E5CA7,
+0xFF2E5CA7,
+0xFF2E5EA8,
+0xFF2E5EA8,
+0xFF2E5EA8,
+0xFF2E5EA8,
+0xFF2E5EA8,
+0xFF2E5EA8,
+0xFF2E5EAA,
+0xFF2E5EAA,
+0xFF2E5EAA,
+0xFF2E5EAA,
+0xFF2E5EA8,
+0xFF2E5EA8,
+0xFF2E5EA8,
+0xFF2E5EA8,
+0xFF2F5FA9,
+0xFF2F5FA9,
+0xFF2E60A9,
+0xFF2E60A9,
+0xFF2E60A9,
+0xFF2E60A9,
+0xFF2F61AA,
+0xFF2F61AA,
+0xFF2F61AA,
+0xFF2F61AA,
+0xFF2F61AA,
+0xFF2F61AA,
+0xFF2E60A9,
+0xFF2E60A9,
+0xFF2F60AC,
+0xFF2F60AC,
+0xFF2F60AC,
+0xFF2F60AC,
+0xFF2F60AC,
+0xFF2F60AC,
+0xFF2F60AC,
+0xFF2F60AC,
+0xFF2F60AC,
+0xFF2F60AC,
+0xFF2D61AC,
+0xFF2D61AC,
+0xFF2E62AD,
+0xFF2E62AD,
+0xFF2E62AD,
+0xFF2E62AD,
+0xFF2E62AD,
+0xFF2E62AD,
+0xFF2E62AD,
+0xFF2E62AD,
+0xFF2E62AD,
+0xFF2E62AD,
+0xFF2E62AD,
+0xFF2E62AD,
+0xFF2E62AD,
+0xFF2E62AD,
+0xFF2E62AD,
+0xFF2E62AD,
+0xFF2F63AE,
+0xFF2F63AE,
+0xFF2F63AE,
+0xFF2F63AE,
+0xFF2F63AE,
+0xFF2F63AE,
+0xFF2F63AE,
+0xFF2F63AE,
+0xFF2F63AE,
+0xFF2F63AE,
+0xFF2F63AE,
+0xFF2F63AE,
+0xFF2F63AE,
+0xFF2F63AE,
+0xFF2F63AE,
+0xFF2F63AE,
+0xFF2F63AE,
+0xFF2F63AE,
+0xFF2F63AE,
+0xFF2F63AE,
+0xFF2F63AE,
+0xFF2F63AE,
+0xFF2F63AE,
+0xFF2F63AE,
+0xFF2F63AE,
+0xFF2F63AE,
+0xFF3064AF,
+0xFF3064AF,
+0xFF3064AF,
+0xFF3064AF,
+0xFF3064AF,
+0xFF3064AF,
+0xFF3064AF,
+0xFF3064AF,
+0xFF2F64B0,
+0xFF2F64B0,
+0xFF2F64B0,
+0xFF2F64B0,
+0xFF2F64B0,
+0xFF2F64B0,
+0xFF2F64B0,
+0xFF2F64B0,
+0xFF2E63AF,
+0xFF2F64B0,
+0xFF2F64B0,
+0xFF2F64B0,
+0xFF2F64B0,
+0xFF2F64B0,
+0xFF2F64B0,
+0xFF2F64B0,
+0xFF2F64B0,
+0xFF2F64B0,
+0xFF2F64B0,
+0xFF2F64B0,
+0xFF2F64B0,
+0xFF2F64B0,
+0xFF2F64B0,
+0xFF2F64B0,
+0xFF2F64B0,
+0xFF2F64B0,
+0xFF2F64B0,
+0xFF2F64B0,
+0xFF2F64B0,
+0xFF2F64B0,
+0xFF2F64B0,
+0xFF2F64B0,
+0xFF2F64B0,
+0xFF2F64B0,
+0xFF2F64B0,
+0xFF2F64B0,
+0xFF2F64B0,
+0xFF2F64B0,
+0xFF2F64B0,
+0xFF2F64B0,
+0xFF2F64B0,
+0xFF2F64B0,
+0xFF2F64B0,
+0xFF2F64B0,
+0xFF3065B1,
+0xFF3065B1,
+0xFF3065B1,
+0xFF3065B1,
+0xFF3065B1,
+0xFF3065B1,
+0xFF3065B1,
+0xFF3065B1,
+0xFF3065B1,
+0xFF3065B1,
+0xFF3065B1,
+0xFF3065B1,
+0xFF3065B1,
+0xFF3065B1,
+0xFF3065B1,
+0xFF3065B1,
+0xFF2F64B0,
+0xFF2F64B0,
+0xFF2F64B0,
+0xFF2F64B0,
+0xFF2F64B0,
+0xFF2F64B0,
+0xFF2F64B0,
+0xFF2F64B0,
+0xFF2F64B0,
+0xFF2F64B0,
+0xFF2F64B0,
+0xFF2F64B0,
+0xFF2F64B0,
+0xFF2F64B0,
+0xFF2F63AF,
+0xFF2F63AF,
+0xFF3064B0,
+0xFF3064B0,
+0xFF2F63AF,
+0xFF2F63AF,
+0xFF2F63AF,
+0xFF2F63AF,
+0xFF2F63AF,
+0xFF2F63AF,
+0xFF2E62AE,
+0xFF2E62AE,
+0xFF2E62AE,
+0xFF2E62AE,
+0xFF2F63AF,
+0xFF2E62AE,
+0xFF2E62AE,
+0xFF2E62AE,
+0xFF2E62AD,
+0xFF2E62AD,
+0xFF2E62AD,
+0xFF2D61AC,
+0xFF2D61AC,
+0xFF2D61AC,
+0xFF2D61AC,
+0xFF2D61AC,
+0xFF2C60AB,
+0xFF2C60AB,
+0xFF2C60AB,
+0xFF2C60AB,
+0xFF2C60AB,
+0xFF2C60AB,
+0xFF2C60AB,
+0xFF2C60AB,
+0xFF2C60AB,
+0xFF2B5FAA,
+0xFF2B5FAA,
+0xFF2B5FAA,
+0xFF2D5EAA,
+0xFF2C5DA9,
+0xFF2C5DA9,
+0xFF2C5DA9,
+0xFF2C5DA9,
+0xFF2C5DA9,
+0xFF2B5CA8,
+0xFF2B5CA8,
+0xFF2B5CA8,
+0xFF2B5CA8,
+0xFF2B5CA8,
+0xFF2A5BA7,
+0xFF2A5BA7,
+0xFF2A5BA7,
+0xFF2B5BA7,
+0xFF2B5BA7,
+0xFF2A5AA6,
+0xFF2A5AA6,
+0xFF2B59A4,
+0xFF2B59A4,
+0xFF2A58A3,
+0xFF2A58A3,
+0xFF2A58A3,
+0xFF2A58A3,
+0xFF2958A0,
+0xFF2958A0,
+0xFF2958A0,
+0xFF2958A0,
+0xFF2A569F,
+0xFF2A569F,
+0xFF2A569F,
+0xFF2A569F,
+0xFF2A549E,
+0xFF2A549E,
+0xFF2A549C,
+0xFF2A549C,
+0xFF29539B,
+0xFF29539B,
+0xFF29539B,
+0xFF29539B,
+0xFF2A529A,
+0xFF2A529A,
+0xFF2A5298,
+0xFF2A5298,
+0xFF2A5298,
+0xFF295197,
+0xFF2A5097,
+0xFF2A5097,
+0xFF284B8B,
+0xFF284B8B,
+0xFF284B8B,
+0xFF284B8B,
+0xFF294C8C,
+0xFF294C8C,
+0xFF274D8E,
+0xFF274D8E,
+0xFF264D90,
+0xFF264D90,
+0xFF274E91,
+0xFF274E91,
+0xFF274F94,
+0xFF274F94,
+0xFF285095,
+0xFF285095,
+0xFF2A5196,
+0xFF2A5196,
+0xFF2A5196,
+0xFF2A5196,
+0xFF2A5196,
+0xFF2B5297,
+0xFF2B5297,
+0xFF2B5297,
+0xFF2B5198,
+0xFF2C5299,
+0xFF2C5299,
+0xFF2C5299,
+0xFF2B5399,
+0xFF2C549A,
+0xFF2C549A,
+0xFF2C549A,
+0xFF2D559D,
+0xFF2D559D,
+0xFF2B559D,
+0xFF2B559D,
+0xFF2B559D,
+0xFF2B559D,
+0xFF2C569E,
+0xFF2C569E,
+0xFF2B579E,
+0xFF2B579E,
+0xFF2B579E,
+0xFF2B579E,
+0xFF2C58A1,
+0xFF2C58A1,
+0xFF2C58A1,
+0xFF2C58A1,
+0xFF2A59A1,
+0xFF2A59A1,
+0xFF2B5AA2,
+0xFF2B5AA2,
+0xFF2B5AA2,
+0xFF2B5AA2,
+0xFF2B5AA2,
+0xFF2B5AA2,
+0xFF2C5BA3,
+0xFF2D5CA4,
+0xFF2C5CA6,
+0xFF2C5CA6,
+0xFF2C5CA6,
+0xFF2C5CA6,
+0xFF2D5DA7,
+0xFF2D5DA7,
+0xFF2E5CA7,
+0xFF2E5CA7,
+0xFF2E5CA7,
+0xFF2F5DA8,
+0xFF2F5DA8,
+0xFF2F5DA8,
+0xFF2F5FA9,
+0xFF2F5FA9,
+0xFF2F5FA9,
+0xFF2F5FA9,
+0xFF2F5FA9,
+0xFF2F5FA9,
+0xFF2F5FAB,
+0xFF2F5FAB,
+0xFF2F5FAB,
+0xFF2F5FAB,
+0xFF2E60A9,
+0xFF2E60A9,
+0xFF2E60A9,
+0xFF2E60A9,
+0xFF2E60A9,
+0xFF2E60A9,
+0xFF2E60A9,
+0xFF2E60A9,
+0xFF2F61AA,
+0xFF2F61AA,
+0xFF2F61AA,
+0xFF2F61AA,
+0xFF2F61AA,
+0xFF2F61AA,
+0xFF2F61AA,
+0xFF2F61AA,
+0xFF2D61AC,
+0xFF2D61AC,
+0xFF2D61AC,
+0xFF2E62AD,
+0xFF2E62AD,
+0xFF2E62AD,
+0xFF2E62AD,
+0xFF2E62AD,
+0xFF2E62AD,
+0xFF2E62AD,
+0xFF2E62AD,
+0xFF2E62AD,
+0xFF2E62AD,
+0xFF2E62AD,
+0xFF2E62AD,
+0xFF2E62AD,
+0xFF2F63AE,
+0xFF2F63AE,
+0xFF2F63AE,
+0xFF2F63AE,
+0xFF2F63AE,
+0xFF2F63AE,
+0xFF2F63AE,
+0xFF2F63AE,
+0xFF2F63AE,
+0xFF2F63AE,
+0xFF2F63AE,
+0xFF2F63AE,
+0xFF2F63AE,
+0xFF3064AF,
+0xFF3064AF,
+0xFF3064AF,
+0xFF3064AF,
+0xFF3064AF,
+0xFF3064AF,
+0xFF3064AF,
+0xFF3064AF,
+0xFF3064AF,
+0xFF3064AF,
+0xFF3064AF,
+0xFF3064AF,
+0xFF3064AF,
+0xFF3064AF,
+0xFF3064AF,
+0xFF3064AF,
+0xFF3064AF,
+0xFF3064AF,
+0xFF3064AF,
+0xFF2F63AF,
+0xFF2F63AF,
+0xFF3064B0,
+0xFF3064B0,
+0xFF3064B0,
+0xFF3064B0,
+0xFF3064B0,
+0xFF3064B0,
+0xFF3064B0,
+0xFF3064B0,
+0xFF3064B0,
+0xFF3064B0,
+0xFF3064B0,
+0xFF3064B0,
+0xFF3064B0,
+0xFF3064B0,
+0xFF2F64B0,
+0xFF2F64B0,
+0xFF2F64B0,
+0xFF2F64B0,
+0xFF2F64B0,
+0xFF2F64B0,
+0xFF2F64B0,
+0xFF2F64B0,
+0xFF2E63AF,
+0xFF2F64B0,
+0xFF2F64B0,
+0xFF2F64B0,
+0xFF2F64B0,
+0xFF2F64B0,
+0xFF2F64B0,
+0xFF2F64B0,
+0xFF3065B1,
+0xFF3065B1,
+0xFF3065B1,
+0xFF3065B1,
+0xFF3065B1,
+0xFF3065B1,
+0xFF3065B1,
+0xFF3065B1,
+0xFF2F64B0,
+0xFF2F64B0,
+0xFF3065B1,
+0xFF3065B1,
+0xFF3065B1,
+0xFF3065B1,
+0xFF3065B1,
+0xFF3065B1,
+0xFF3065B1,
+0xFF3065B1,
+0xFF3065B1,
+0xFF3065B1,
+0xFF3065B1,
+0xFF3065B1,
+0xFF3065B1,
+0xFF3065B1,
+0xFF3065B1,
+0xFF3065B1,
+0xFF3065B1,
+0xFF3065B1,
+0xFF3065B1,
+0xFF3065B1,
+0xFF3065B1,
+0xFF3065B1,
+0xFF3065B1,
+0xFF3065B1,
+0xFF3065B1,
+0xFF3065B1,
+0xFF3065B1,
+0xFF3065B1,
+0xFF3065B1,
+0xFF3065B1,
+0xFF3065B1,
+0xFF3065B1,
+0xFF3065B1,
+0xFF3065B1,
+0xFF3065B1,
+0xFF3065B1,
+0xFF3065B1,
+0xFF3065B1,
+0xFF3065B1,
+0xFF3065B1,
+0xFF3065B1,
+0xFF3065B1,
+0xFF3065B1,
+0xFF2F64B0,
+0xFF2F64B0,
+0xFF2F64B0,
+0xFF3065B1,
+0xFF2F64B0,
+0xFF2F64B0,
+0xFF2F64B0,
+0xFF2F64B0,
+0xFF2F64B0,
+0xFF2F64B0,
+0xFF2E63AF,
+0xFF2F64B0,
+0xFF2F64B0,
+0xFF2F63AF,
+0xFF2F63AF,
+0xFF2F63AF,
+0xFF2F63AF,
+0xFF2F63AF,
+0xFF2F63AF,
+0xFF2F63AF,
+0xFF2F63AF,
+0xFF2E62AE,
+0xFF2E62AE,
+0xFF2F63AE,
+0xFF2E62AD,
+0xFF2E62AD,
+0xFF2E62AD,
+0xFF2E62AD,
+0xFF2E62AD,
+0xFF2E62AD,
+0xFF2E62AD,
+0xFF2D61AC,
+0xFF2D61AC,
+0xFF2D61AC,
+0xFF2D61AC,
+0xFF2D61AC,
+0xFF2D61AC,
+0xFF2D61AC,
+0xFF2C60AB,
+0xFF2C60AB,
+0xFF2C60AB,
+0xFF2C60AB,
+0xFF2C60AB,
+0xFF2C60AB,
+0xFF2B5FAA,
+0xFF2B5FAA,
+0xFF2B5FAA,
+0xFF2B5FAA,
+0xFF2B5FAA,
+0xFF2C5DA9,
+0xFF2C5DA9,
+0xFF2B5CA8,
+0xFF2B5CA8,
+0xFF2B5CA8,
+0xFF2A5BA7,
+0xFF2A5BA7,
+0xFF2A5BA7,
+0xFF2A5BA7,
+0xFF2A5BA7,
+0xFF2B5BA7,
+0xFF2B5BA7,
+0xFF2A5AA6,
+0xFF2A5AA6,
+0xFF2A5AA6,
+0xFF2959A5,
+0xFF2A58A3,
+0xFF2A58A3,
+0xFF2A58A3,
+0xFF2A58A3,
+0xFF2A59A1,
+0xFF2958A0,
+0xFF2958A0,
+0xFF2958A0,
+0xFF29589E,
+0xFF29589E,
+0xFF2A569F,
+0xFF2A569F,
+0xFF2A569F,
+0xFF29559E,
+0xFF29559C,
+0xFF29559C,
+0xFF2A549C,
+0xFF29539B,
+0xFF2A529A,
+0xFF2A529A,
+0xFF2A529A,
+0xFF2A529A,
+0xFF2B519A,
+0xFF2B519A,
+0xFF2A5097,
+0xFF2A5097,
+0xFF284B8B,
+0xFF284B8B,
+0xFF294C8C,
+0xFF294C8C,
+0xFF294C8C,
+0xFF294C8C,
+0xFF284E8F,
+0xFF284E8F,
+0xFF274E91,
+0xFF274E91,
+0xFF274E91,
+0xFF284F92,
+0xFF274F94,
+0xFF285095,
+0xFF285095,
+0xFF295196,
+0xFF2A5196,
+0xFF2A5196,
+0xFF2B5297,
+0xFF2B5297,
+0xFF2B5297,
+0xFF2B5297,
+0xFF2B5297,
+0xFF2B5297,
+0xFF2C5299,
+0xFF2C5299,
+0xFF2C5299,
+0xFF2C5299,
+0xFF2C549A,
+0xFF2C549A,
+0xFF2C549A,
+0xFF2D559B,
+0xFF2D559D,
+0xFF2D559D,
+0xFF2B559D,
+0xFF2B559D,
+0xFF2C569E,
+0xFF2C569E,
+0xFF2C569E,
+0xFF2C569E,
+0xFF2B579E,
+0xFF2B579E,
+0xFF2C589F,
+0xFF2C589F,
+0xFF2C58A1,
+0xFF2D59A2,
+0xFF2D59A2,
+0xFF2D59A2,
+0xFF2B5AA2,
+0xFF2B5AA2,
+0xFF2C5BA3,
+0xFF2C5BA3,
+0xFF2C5BA3,
+0xFF2C5BA3,
+0xFF2C5BA3,
+0xFF2C5BA3,
+0xFF2D5CA4,
+0xFF2D5CA4,
+0xFF2D5DA7,
+0xFF2D5DA7,
+0xFF2D5DA7,
+0xFF2D5DA7,
+0xFF2E5EA8,
+0xFF2E5EA8,
+0xFF2E5CA7,
+0xFF2F5DA8,
+0xFF2F5DA8,
+0xFF2F5DA8,
+0xFF305EA9,
+0xFF305EA9,
+0xFF2F5FA9,
+0xFF2F5FA9,
+0xFF2F5FA9,
+0xFF2F5FA9,
+0xFF2F5FA9,
+0xFF2F5FA9,
+0xFF2F5FAB,
+0xFF2F5FAB,
+0xFF3060AC,
+0xFF3060AC,
+0xFF2F61AA,
+0xFF2F61AA,
+0xFF2F61AA,
+0xFF2F61AA,
+0xFF2F61AA,
+0xFF2F61AA,
+0xFF2F61AA,
+0xFF2F61AA,
+0xFF2F61AA,
+0xFF2F61AA,
+0xFF2F61AA,
+0xFF2F61AA,
+0xFF2F61AA,
+0xFF2F61AA,
+0xFF2F61AA,
+0xFF2E60A9,
+0xFF2E62AD,
+0xFF2E62AD,
+0xFF2E62AD,
+0xFF2E62AD,
+0xFF2E62AD,
+0xFF2F63AE,
+0xFF2F63AE,
+0xFF2F63AE,
+0xFF2F63AE,
+0xFF2F63AE,
+0xFF2F63AE,
+0xFF2E62AD,
+0xFF2F63AE,
+0xFF2F63AE,
+0xFF2F63AE,
+0xFF2F63AE,
+0xFF2F63AE,
+0xFF2F63AE,
+0xFF2F63AE,
+0xFF2F63AE,
+0xFF2F63AE,
+0xFF2F63AE,
+0xFF3064AF,
+0xFF3064AF,
+0xFF3064AF,
+0xFF3064AF,
+0xFF3064AF,
+0xFF3064AF,
+0xFF3064AF,
+0xFF3064AF,
+0xFF3064AF,
+0xFF3064AF,
+0xFF3064AF,
+0xFF3064AF,
+0xFF3064AF,
+0xFF3064AF,
+0xFF3064AF,
+0xFF3064AF,
+0xFF3064AF,
+0xFF3064AF,
+0xFF3064AF,
+0xFF3064AF,
+0xFF3064AF,
+0xFF3064AF,
+0xFF3064AF,
+0xFF3064AF,
+0xFF3064AF,
+0xFF3064AF,
+0xFF3064B0,
+0xFF3064B0,
+0xFF3064B0,
+0xFF3064B0,
+0xFF3064B0,
+0xFF3064B0,
+0xFF3064B0,
+0xFF3064B0,
+0xFF3165B1,
+0xFF3165B1,
+0xFF3165B1,
+0xFF3064B0,
+0xFF3064B0,
+0xFF3064B0,
+0xFF3064B0,
+0xFF3064B0,
+0xFF3065B1,
+0xFF3065B1,
+0xFF2F64B0,
+0xFF2F64B0,
+0xFF2F64B0,
+0xFF2F64B0,
+0xFF3065B1,
+0xFF3065B1,
+0xFF2F64B0,
+0xFF3065B1,
+0xFF3166B2,
+0xFF3166B2,
+0xFF3065B1,
+0xFF3065B1,
+0xFF3065B1,
+0xFF3166B2,
+0xFF3065B1,
+0xFF3065B1,
+0xFF3065B1,
+0xFF3065B1,
+0xFF3065B1,
+0xFF3065B1,
+0xFF3065B1,
+0xFF3065B1,
+0xFF3065B1,
+0xFF3065B1,
+0xFF3065B1,
+0xFF3065B1,
+0xFF3065B1,
+0xFF3065B1,
+0xFF3166B2,
+0xFF3166B2,
+0xFF3166B2,
+0xFF3166B2,
+0xFF3166B2,
+0xFF3166B2,
+0xFF3166B2,
+0xFF3166B2,
+0xFF3166B2,
+0xFF3166B2,
+0xFF3166B2,
+0xFF3166B2,
+0xFF3166B2,
+0xFF3065B1,
+0xFF3065B1,
+0xFF3065B1,
+0xFF3065B1,
+0xFF3065B1,
+0xFF3065B1,
+0xFF3065B1,
+0xFF3065B1,
+0xFF3065B1,
+0xFF3065B1,
+0xFF3065B1,
+0xFF3065B1,
+0xFF3065B1,
+0xFF3065B1,
+0xFF3065B1,
+0xFF3065B1,
+0xFF3065B1,
+0xFF3065B1,
+0xFF3065B1,
+0xFF3065B1,
+0xFF3065B1,
+0xFF3065B1,
+0xFF3065B1,
+0xFF3065B1,
+0xFF3065B1,
+0xFF3065B1,
+0xFF2F64B0,
+0xFF2F64B0,
+0xFF2F64B0,
+0xFF3065B1,
+0xFF3065B1,
+0xFF2F64B0,
+0xFF2F64B0,
+0xFF2F64B0,
+0xFF2F64B0,
+0xFF2F64B0,
+0xFF2E63AF,
+0xFF2F64B0,
+0xFF2F64B0,
+0xFF2F63AF,
+0xFF2F63AF,
+0xFF2F63AF,
+0xFF2F63AF,
+0xFF2F63AF,
+0xFF2F63AF,
+0xFF2F63AF,
+0xFF2F63AF,
+0xFF2F63AF,
+0xFF2F63AF,
+0xFF2F63AE,
+0xFF2F63AE,
+0xFF2E62AD,
+0xFF2E62AD,
+0xFF2E62AD,
+0xFF2F63AE,
+0xFF2F63AE,
+0xFF2E62AD,
+0xFF2E62AD,
+0xFF2D61AC,
+0xFF2E62AD,
+0xFF2E62AD,
+0xFF2D61AC,
+0xFF2D61AC,
+0xFF2D61AC,
+0xFF2D61AC,
+0xFF2C60AB,
+0xFF2C60AB,
+0xFF2C60AB,
+0xFF2C60AB,
+0xFF2D61AC,
+0xFF2C60AB,
+0xFF2B5FAA,
+0xFF2B5FAA,
+0xFF2B5FAA,
+0xFF2B5FAA,
+0xFF2D5EAA,
+0xFF2D5EAA,
+0xFF2C5DA9,
+0xFF2C5DA9,
+0xFF2C5DA9,
+0xFF2B5CA8,
+0xFF2B5CA8,
+0xFF2B5CA8,
+0xFF2B5CA8,
+0xFF2B5CA8,
+0xFF2B5BA7,
+0xFF2B5BA7,
+0xFF2B5BA7,
+0xFF2A5AA6,
+0xFF2A5AA6,
+0xFF2A5AA6,
+0xFF2A58A3,
+0xFF2A58A3,
+0xFF2A58A3,
+0xFF2A58A3,
+0xFF2A59A1,
+0xFF2958A0,
+0xFF2958A0,
+0xFF2958A0,
+0xFF29589E,
+0xFF29589E,
+0xFF2A569F,
+0xFF2A569F,
+0xFF2A569F,
+0xFF2A569F,
+0xFF29559C,
+0xFF29559C,
+0xFF2A549C,
+0xFF29539B,
+0xFF2B539B,
+0xFF2B539B,
+0xFF2B539B,
+0xFF2A529A,
+0xFF2B519A,
+0xFF2B519A,
+0xFF2A5097,
+0xFF2A5097,
+0xFF294C8C,
+0xFF294C8C,
+0xFF274D8E,
+0xFF274D8E,
+0xFF284E8F,
+0xFF284E8F,
+0xFF284D91,
+0xFF284D91,
+0xFF284F92,
+0xFF284F92,
+0xFF284F94,
+0xFF295095,
+0xFF285095,
+0xFF295196,
+0xFF295197,
+0xFF295197,
+0xFF2A5196,
+0xFF2A5196,
+0xFF2B5297,
+0xFF2B5297,
+0xFF2B5198,
+0xFF2B5198,
+0xFF2B5198,
+0xFF2B5198,
+0xFF2B5399,
+0xFF2B5399,
+0xFF2C549A,
+0xFF2C549A,
+0xFF2D559D,
+0xFF2D559D,
+0xFF2D559D,
+0xFF2D559D,
+0xFF2C569E,
+0xFF2C569E,
+0xFF2C569E,
+0xFF2C569E,
+0xFF2C58A1,
+0xFF2C58A1,
+0xFF2C58A1,
+0xFF2C58A1,
+0xFF2C58A1,
+0xFF2C58A1,
+0xFF2A59A1,
+0xFF2A59A1,
+0xFF2A59A1,
+0xFF2A59A1,
+0xFF2B5AA2,
+0xFF2B5AA2,
+0xFF2C5BA3,
+0xFF2C5BA3,
+0xFF2C5BA3,
+0xFF2C5BA3,
+0xFF2C5BA3,
+0xFF2D5CA4,
+0xFF2C5CA6,
+0xFF2C5CA6,
+0xFF2D5DA7,
+0xFF2D5DA7,
+0xFF2D5DA7,
+0xFF2D5DA7,
+0xFF2E5EA8,
+0xFF2E5EA8,
+0xFF2E5EA8,
+0xFF2E5EA8,
+0xFF2E5EA8,
+0xFF2F5FA9,
+0xFF2F5FA9,
+0xFF2F5FA9,
+0xFF2F5FA9,
+0xFF2F5FA9,
+0xFF2F5FA9,
+0xFF2E5EA8,
+0xFF3060AA,
+0xFF3060AA,
+0xFF3060AA,
+0xFF3060AA,
+0xFF3060AC,
+0xFF3060AC,
+0xFF3060AC,
+0xFF3161AD,
+0xFF3061AD,
+0xFF3061AD,
+0xFF3061AD,
+0xFF3061AD,
+0xFF3061AD,
+0xFF2F60AC,
+0xFF2F60AC,
+0xFF2F60AC,
+0xFF3061AD,
+0xFF3061AD,
+0xFF2F60AC,
+0xFF2F60AC,
+0xFF2F60AC,
+0xFF3061AD,
+0xFF3061AD,
+0xFF3061AD,
+0xFF2F63AE,
+0xFF2F63AE,
+0xFF2F63AE,
+0xFF2F63AE,
+0xFF2F63AE,
+0xFF2F63AE,
+0xFF2F63AE,
+0xFF2F63AE,
+0xFF2F63AE,
+0xFF2F63AE,
+0xFF2F63AE,
+0xFF2F63AE,
+0xFF3064AF,
+0xFF3064AF,
+0xFF3064AF,
+0xFF3165B0,
+0xFF3064AF,
+0xFF3064AF,
+0xFF3165B0,
+0xFF3165B0,
+0xFF3064AF,
+0xFF3064AF,
+0xFF3064AF,
+0xFF3064AF,
+0xFF3165B0,
+0xFF2F63AE,
+0xFF2F63AE,
+0xFF3165B0,
+0xFF3165B0,
+0xFF3064AF,
+0xFF3064AF,
+0xFF3165B0,
+0xFF3064AF,
+0xFF3064AF,
+0xFF3064AF,
+0xFF3064AF,
+0xFF3064AF,
+0xFF3064AF,
+0xFF3064AF,
+0xFF3064AF,
+0xFF3064AF,
+0xFF3064AF,
+0xFF3064AF,
+0xFF3064AF,
+0xFF3064AF,
+0xFF3165B0,
+0xFF3064AF,
+0xFF2F63AE,
+0xFF3065B1,
+0xFF2F64B0,
+0xFF2F64B0,
+0xFF2F64B0,
+0xFF3065B1,
+0xFF3065B1,
+0xFF3065B1,
+0xFF2F64B0,
+0xFF2F64B0,
+0xFF3065B1,
+0xFF3065B1,
+0xFF3065B1,
+0xFF3065B1,
+0xFF3065B1,
+0xFF3065B1,
+0xFF2F64B0,
+0xFF3065B1,
+0xFF3065B1,
+0xFF3065B1,
+0xFF3065B1,
+0xFF3065B1,
+0xFF3065B1,
+0xFF3065B1,
+0xFF3065B1,
+0xFF3065B1,
+0xFF3065B1,
+0xFF3065B1,
+0xFF3065B1,
+0xFF2F64B0,
+0xFF3065B1,
+0xFF3065B1,
+0xFF3166B2,
+0xFF3166B2,
+0xFF3166B2,
+0xFF3166B2,
+0xFF3166B2,
+0xFF3166B2,
+0xFF3166B2,
+0xFF3166B2,
+0xFF3166B2,
+0xFF3166B2,
+0xFF3065B1,
+0xFF3065B1,
+0xFF3065B1,
+0xFF3166B2,
+0xFF3166B2,
+0xFF3166B2,
+0xFF3166B2,
+0xFF3065B1,
+0xFF3166B2,
+0xFF3166B2,
+0xFF3166B2,
+0xFF3166B2,
+0xFF3166B2,
+0xFF3166B2,
+0xFF3166B2,
+0xFF3166B2,
+0xFF3166B2,
+0xFF3166B2,
+0xFF3166B2,
+0xFF3166B2,
+0xFF3166B2,
+0xFF3166B2,
+0xFF3166B2,
+0xFF3166B2,
+0xFF3166B2,
+0xFF3166B2,
+0xFF3166B2,
+0xFF3166B2,
+0xFF3166B2,
+0xFF3166B2,
+0xFF3166B2,
+0xFF3166B2,
+0xFF3166B2,
+0xFF3166B2,
+0xFF3166B2,
+0xFF3166B2,
+0xFF3166B2,
+0xFF3166B2,
+0xFF3166B2,
+0xFF2E66B1,
+0xFF2E66B1,
+0xFF2E66B1,
+0xFF2E66B1,
+0xFF2E66B1,
+0xFF2E66B1,
+0xFF2D65B0,
+0xFF2D65B0,
+0xFF3065B1,
+0xFF3065B1,
+0xFF3065B1,
+0xFF2F64B0,
+0xFF2F64B0,
+0xFF2F64B0,
+0xFF2F64B0,
+0xFF2F64B0,
+0xFF2F64B0,
+0xFF2F64B0,
+0xFF2F64B0,
+0xFF2E63AF,
+0xFF2E63AF,
+0xFF2F64B0,
+0xFF2F64B0,
+0xFF2F64B0,
+0xFF2E63AF,
+0xFF2E63AF,
+0xFF2F63AF,
+0xFF2F63AF,
+0xFF2F63AE,
+0xFF2F63AE,
+0xFF2F63AE,
+0xFF2F63AE,
+0xFF2F63AE,
+0xFF2F63AE,
+0xFF2E62AD,
+0xFF2E62AD,
+0xFF2E62AD,
+0xFF2E62AD,
+0xFF2D61AC,
+0xFF2D61AC,
+0xFF2E62AD,
+0xFF2D61AC,
+0xFF2D61AC,
+0xFF2D61AC,
+0xFF2D61AC,
+0xFF2D61AC,
+0xFF2D61AC,
+0xFF2C60AB,
+0xFF2D61AC,
+0xFF2C60AB,
+0xFF2C60AB,
+0xFF2C60AB,
+0xFF2C60AB,
+0xFF2C60AB,
+0xFF2B5FAA,
+0xFF2B5FAA,
+0xFF2B5FAA,
+0xFF2B5FAA,
+0xFF2C5DA9,
+0xFF2C5DA9,
+0xFF2B5CA8,
+0xFF2B5CA8,
+0xFF2B5CA8,
+0xFF2B5CA8,
+0xFF2C5BA9,
+0xFF2C5BA9,
+0xFF2B5BA7,
+0xFF2B5BA7,
+0xFF2B5BA7,
+0xFF2B5BA7,
+0xFF2A5AA4,
+0xFF2A5AA4,
+0xFF2A5AA4,
+0xFF2A5AA4,
+0xFF2B5AA2,
+0xFF2A59A1,
+0xFF2A59A1,
+0xFF2958A0,
+0xFF2958A0,
+0xFF2958A0,
+0xFF2958A0,
+0xFF28579F,
+0xFF28579F,
+0xFF28579F,
+0xFF2A569F,
+0xFF2A569F,
+0xFF29559E,
+0xFF29559E,
+0xFF2A549C,
+0xFF2A549C,
+0xFF2B539B,
+0xFF2B539B,
+0xFF2A529A,
+0xFF2A529A,
+0xFF2B519A,
+0xFF2B519A,
+0xFF294C8C,
+0xFF274D8C,
+0xFF274D8E,
+0xFF284E8F,
+0xFF284E8F,
+0xFF284E8F,
+0xFF294E92,
+0xFF294E92,
+0xFF284F92,
+0xFF284F92,
+0xFF295095,
+0xFF295095,
+0xFF285095,
+0xFF295196,
+0xFF295197,
+0xFF295197,
+0xFF2A5196,
+0xFF2B5297,
+0xFF2B5297,
+0xFF2B5297,
+0xFF2B5198,
+0xFF2C5299,
+0xFF2C5299,
+0xFF2C5299,
+0xFF2B5399,
+0xFF2C549A,
+0xFF2C549A,
+0xFF2D559B,
+0xFF2D559D,
+0xFF2D559D,
+0xFF2E569E,
+0xFF2C569E,
+0xFF2C569E,
+0xFF2C569E,
+0xFF2C569E,
+0xFF2D579F,
+0xFF2C58A1,
+0xFF2C58A1,
+0xFF2C58A1,
+0xFF2C58A1,
+0xFF2C58A1,
+0xFF2C58A1,
+0xFF2A59A1,
+0xFF2A59A1,
+0xFF2B5AA2,
+0xFF2B5AA2,
+0xFF2B5AA2,
+0xFF2C5BA3,
+0xFF2C5BA3,
+0xFF2C5BA3,
+0xFF2C5BA3,
+0xFF2D5CA4,
+0xFF2D5CA4,
+0xFF2D5CA4,
+0xFF2C5CA6,
+0xFF2C5CA6,
+0xFF2D5DA7,
+0xFF2D5DA7,
+0xFF2D5DA7,
+0xFF2E5EA8,
+0xFF2E5EA8,
+0xFF2E5EA8,
+0xFF2F5FA9,
+0xFF2F5FA9,
+0xFF2E5EA8,
+0xFF2F5FA9,
+0xFF2F5FA9,
+0xFF2F5FA9,
+0xFF3060AA,
+0xFF2F5FA9,
+0xFF2F5FA9,
+0xFF2F5FA9,
+0xFF3060AA,
+0xFF3060AA,
+0xFF3060AA,
+0xFF3060AA,
+0xFF3060AC,
+0xFF3060AC,
+0xFF3060AC,
+0xFF3060AC,
+0xFF3061AD,
+0xFF3061AD,
+0xFF3061AD,
+0xFF3061AD,
+0xFF3061AD,
+0xFF3061AD,
+0xFF3061AD,
+0xFF3061AD,
+0xFF3061AD,
+0xFF3061AD,
+0xFF3061AD,
+0xFF3061AD,
+0xFF3061AD,
+0xFF3061AD,
+0xFF3162AE,
+0xFF3162AE,
+0xFF2F63AE,
+0xFF2F63AE,
+0xFF2F63AE,
+0xFF2F63AE,
+0xFF2F63AE,
+0xFF2F63AE,
+0xFF3064AF,
+0xFF3064AF,
+0xFF2F63AE,
+0xFF3064AF,
+0xFF3064AF,
+0xFF3064AF,
+0xFF3064AF,
+0xFF3064AF,
+0xFF3064AF,
+0xFF3064AF,
+0xFF3064AF,
+0xFF3064AF,
+0xFF3165B0,
+0xFF3064AF,
+0xFF3064AF,
+0xFF3064AF,
+0xFF3064AF,
+0xFF3165B0,
+0xFF3165B0,
+0xFF3064AF,
+0xFF3064AF,
+0xFF3165B0,
+0xFF3165B0,
+0xFF3064AF,
+0xFF3064AF,
+0xFF3266B1,
+0xFF3165B0,
+0xFF3165B0,
+0xFF3165B0,
+0xFF3165B0,
+0xFF3165B0,
+0xFF3165B0,
+0xFF3165B0,
+0xFF3165B0,
+0xFF3165B0,
+0xFF3165B0,
+0xFF3165B0,
+0xFF3165B0,
+0xFF3165B0,
+0xFF3266B1,
+0xFF3165B0,
+0xFF3165B0,
+0xFF3065B1,
+0xFF3065B1,
+0xFF3065B1,
+0xFF3065B1,
+0xFF3065B1,
+0xFF3166B2,
+0xFF3065B1,
+0xFF3065B1,
+0xFF3065B1,
+0xFF3166B2,
+0xFF3166B2,
+0xFF3065B1,
+0xFF3065B1,
+0xFF3166B2,
+0xFF3166B2,
+0xFF3065B1,
+0xFF3065B1,
+0xFF3065B1,
+0xFF3065B1,
+0xFF3065B1,
+0xFF3166B2,
+0xFF3166B2,
+0xFF3166B2,
+0xFF3166B2,
+0xFF3166B2,
+0xFF3166B2,
+0xFF3166B2,
+0xFF3166B2,
+0xFF3065B1,
+0xFF3065B1,
+0xFF3166B2,
+0xFF3166B2,
+0xFF3166B2,
+0xFF3166B2,
+0xFF3166B2,
+0xFF3166B2,
+0xFF3166B2,
+0xFF3166B2,
+0xFF3166B2,
+0xFF3166B2,
+0xFF3166B2,
+0xFF3166B2,
+0xFF3166B2,
+0xFF3166B2,
+0xFF3166B2,
+0xFF3166B2,
+0xFF3166B2,
+0xFF3166B2,
+0xFF3166B2,
+0xFF3166B2,
+0xFF3166B2,
+0xFF3166B2,
+0xFF3166B2,
+0xFF3166B2,
+0xFF3166B2,
+0xFF3166B2,
+0xFF3166B2,
+0xFF3166B2,
+0xFF3166B2,
+0xFF3166B2,
+0xFF3166B2,
+0xFF3166B2,
+0xFF3166B2,
+0xFF3166B2,
+0xFF3166B2,
+0xFF3166B2,
+0xFF3166B2,
+0xFF3166B2,
+0xFF3166B2,
+0xFF3166B2,
+0xFF3166B2,
+0xFF3267B3,
+0xFF3166B2,
+0xFF3166B2,
+0xFF3166B2,
+0xFF3166B2,
+0xFF3166B2,
+0xFF3166B2,
+0xFF3166B2,
+0xFF3166B2,
+0xFF2F67B2,
+0xFF2F67B2,
+0xFF2F67B2,
+0xFF2F67B2,
+0xFF2F67B2,
+0xFF2F67B2,
+0xFF2F67B2,
+0xFF2F67B2,
+0xFF3166B2,
+0xFF3166B2,
+0xFF3166B2,
+0xFF3065B1,
+0xFF3065B1,
+0xFF3065B1,
+0xFF3065B1,
+0xFF3065B1,
+0xFF3065B1,
+0xFF3065B1,
+0xFF2F64B0,
+0xFF2F64B0,
+0xFF2F64B0,
+0xFF2F64B0,
+0xFF2F64B0,
+0xFF3065B1,
+0xFF2F64B0,
+0xFF2F64B0,
+0xFF3064B0,
+0xFF3064B0,
+0xFF3064AF,
+0xFF3064AF,
+0xFF2F63AE,
+0xFF2F63AE,
+0xFF2F63AE,
+0xFF2F63AE,
+0xFF2F63AE,
+0xFF2F63AE,
+0xFF2E62AD,
+0xFF2E62AD,
+0xFF2E62AD,
+0xFF2E62AD,
+0xFF2E62AD,
+0xFF2D61AC,
+0xFF2D61AC,
+0xFF2D61AC,
+0xFF2D61AC,
+0xFF2D61AC,
+0xFF2D61AC,
+0xFF2C60AB,
+0xFF2D61AC,
+0xFF2C60AB,
+0xFF2C60AB,
+0xFF2C60AB,
+0xFF2C60AB,
+0xFF2C60AB,
+0xFF2C60AB,
+0xFF2C60AB,
+0xFF2B5FAA,
+0xFF2B5FAA,
+0xFF2D5EAA,
+0xFF2C5DA9,
+0xFF2C5DA9,
+0xFF2B5CA8,
+0xFF2B5CA8,
+0xFF2B5CA8,
+0xFF2C5BA9,
+0xFF2C5BA9,
+0xFF2B5BA7,
+0xFF2B5BA7,
+0xFF2B5BA7,
+0xFF2B5BA7,
+0xFF2B5BA5,
+0xFF2B5BA5,
+0xFF2A5AA4,
+0xFF2A5AA4,
+0xFF2B5AA2,
+0xFF2B5AA2,
+0xFF2A59A1,
+0xFF2A59A1,
+0xFF2A59A1,
+0xFF2A59A1,
+0xFF2958A0,
+0xFF2958A0,
+0xFF28579F,
+0xFF28579F,
+0xFF2A569F,
+0xFF2A569F,
+0xFF2A569F,
+0xFF2A569F,
+0xFF2A549C,
+0xFF2A549C,
+0xFF2C549C,
+0xFF2B539B,
+0xFF2B539B,
+0xFF2A529A,
+0xFF2B519A,
+0xFF2B519A,
+0xFF284E8F,
+0xFF274E8F,
+0xFF274E8F,
+0xFF274E8F,
+0xFF274E91,
+0xFF284F92,
+0xFF284F92,
+0xFF284F92,
+0xFF295095,
+0xFF295095,
+0xFF295095,
+0xFF295095,
+0xFF295197,
+0xFF295197,
+0xFF295197,
+0xFF2A5298,
+0xFF2B5198,
+0xFF2B5198,
+0xFF2B5198,
+0xFF2C5299,
+0xFF2C5299,
+0xFF2C5299,
+0xFF2B5399,
+0xFF2B5399,
+0xFF2C549A,
+0xFF2C549A,
+0xFF2B559D,
+0xFF2B559D,
+0xFF2C569E,
+0xFF2C569E,
+0xFF2C569E,
+0xFF2C569E,
+0xFF2D57A1,
+0xFF2C58A1,
+0xFF2C58A1,
+0xFF2C58A1,
+0xFF2C58A1,
+0xFF2C58A1,
+0xFF2B5AA2,
+0xFF2B5AA2,
+0xFF2B5AA2,
+0xFF2B5AA2,
+0xFF2B5AA2,
+0xFF2B5AA2,
+0xFF2B5BA3,
+0xFF2B5BA3,
+0xFF2B5BA3,
+0xFF2C5CA4,
+0xFF2C5CA6,
+0xFF2C5CA6,
+0xFF2C5CA6,
+0xFF2D5DA7,
+0xFF2D5DA7,
+0xFF2D5DA7,
+0xFF2D5DA7,
+0xFF2D5DA7,
+0xFF2D5DA7,
+0xFF2E5EA8,
+0xFF2E5EA8,
+0xFF2E5EA8,
+0xFF2E5EA8,
+0xFF2F5FA9,
+0xFF2F5FA9,
+0xFF2F5FA9,
+0xFF2E5EA8,
+0xFF2F5FA9,
+0xFF2F5FA9,
+0xFF3060AA,
+0xFF3060AA,
+0xFF3060AA,
+0xFF3060AA,
+0xFF3060AA,
+0xFF2F61AA,
+0xFF2F61AA,
+0xFF2F61AA,
+0xFF3062AB,
+0xFF3061AD,
+0xFF3061AD,
+0xFF3061AD,
+0xFF2F60AC,
+0xFF3061AD,
+0xFF3061AD,
+0xFF3061AD,
+0xFF3061AD,
+0xFF3061AD,
+0xFF3061AD,
+0xFF3061AD,
+0xFF3061AD,
+0xFF3162AE,
+0xFF3162AE,
+0xFF2F63AE,
+0xFF2F63AE,
+0xFF2F63AE,
+0xFF2F63AE,
+0xFF3064AF,
+0xFF3064AF,
+0xFF3064AF,
+0xFF3064AF,
+0xFF3064AF,
+0xFF3064AF,
+0xFF3064AF,
+0xFF3064AF,
+0xFF3064AF,
+0xFF3064AF,
+0xFF3064AF,
+0xFF3064AF,
+0xFF3064AF,
+0xFF3064AF,
+0xFF3064AF,
+0xFF3064AF,
+0xFF3064B0,
+0xFF3064B0,
+0xFF3165B0,
+0xFF3165B0,
+0xFF3165B0,
+0xFF3064AF,
+0xFF3064AF,
+0xFF3064AF,
+0xFF3165B0,
+0xFF3165B0,
+0xFF3165B0,
+0xFF3165B0,
+0xFF3064AF,
+0xFF3165B0,
+0xFF3165B0,
+0xFF3165B0,
+0xFF3165B0,
+0xFF3266B1,
+0xFF3066B0,
+0xFF3066B0,
+0xFF3066B0,
+0xFF3066B0,
+0xFF3066B0,
+0xFF3066B0,
+0xFF3066B0,
+0xFF3066B0,
+0xFF3167B1,
+0xFF3167B1,
+0xFF3167B1,
+0xFF3167B1,
+0xFF3167B1,
+0xFF3167B1,
+0xFF3167B1,
+0xFF3167B1,
+0xFF3167B1,
+0xFF3167B1,
+0xFF3167B1,
+0xFF3167B1,
+0xFF3167B1,
+0xFF3167B1,
+0xFF3167B1,
+0xFF3167B1,
+0xFF3167B1,
+0xFF3167B1,
+0xFF3268B2,
+0xFF3167B1,
+0xFF3167B1,
+0xFF3268B2,
+0xFF3167B1,
+0xFF3167B1,
+0xFF3166B2,
+0xFF3166B2,
+0xFF3166B2,
+0xFF3166B2,
+0xFF3166B2,
+0xFF3166B2,
+0xFF3166B2,
+0xFF3166B2,
+0xFF3267B3,
+0xFF3267B3,
+0xFF3267B3,
+0xFF3166B2,
+0xFF3166B2,
+0xFF3166B2,
+0xFF3267B3,
+0xFF3267B3,
+0xFF2F67B2,
+0xFF2F67B2,
+0xFF2F67B2,
+0xFF2F67B2,
+0xFF2F67B2,
+0xFF2F67B2,
+0xFF2F67B2,
+0xFF2F67B2,
+0xFF2F67B2,
+0xFF2F67B2,
+0xFF2F67B2,
+0xFF2F67B2,
+0xFF2F67B2,
+0xFF3068B3,
+0xFF3068B3,
+0xFF3068B3,
+0xFF2F67B2,
+0xFF2F67B2,
+0xFF2F67B2,
+0xFF3068B3,
+0xFF3068B3,
+0xFF3068B3,
+0xFF2F67B2,
+0xFF2F67B2,
+0xFF2F67B2,
+0xFF3068B3,
+0xFF3068B3,
+0xFF3068B3,
+0xFF3068B3,
+0xFF3068B3,
+0xFF3068B3,
+0xFF3068B3,
+0xFF3068B3,
+0xFF3068B3,
+0xFF2F67B2,
+0xFF2F67B2,
+0xFF2F67B2,
+0xFF3068B3,
+0xFF3068B3,
+0xFF3068B3,
+0xFF2F67B2,
+0xFF2F67B2,
+0xFF2F67B2,
+0xFF2F67B2,
+0xFF2F67B2,
+0xFF2F67B2,
+0xFF2F67B2,
+0xFF2F67B2,
+0xFF2F67B2,
+0xFF2F67B2,
+0xFF2F67B2,
+0xFF2F67B2,
+0xFF2F67B2,
+0xFF2F67B2,
+0xFF2F67B2,
+0xFF2F67B2,
+0xFF2F67B2,
+0xFF2F67B2,
+0xFF2F67B2,
+0xFF2E66B1,
+0xFF2E66B1,
+0xFF2E66B1,
+0xFF3065B1,
+0xFF3065B1,
+0xFF2F67B2,
+0xFF2E66B1,
+0xFF2E66B1,
+0xFF2E66B1,
+0xFF2E66B1,
+0xFF2E66B1,
+0xFF3065B1,
+0xFF3065B1,
+0xFF3065B1,
+0xFF3065B1,
+0xFF2F64B0,
+0xFF2F64B0,
+0xFF3064AF,
+0xFF3064AF,
+0xFF3064AF,
+0xFF3064AF,
+0xFF3064AF,
+0xFF3064AF,
+0xFF3064AF,
+0xFF2F63AE,
+0xFF2F63AE,
+0xFF2F63AE,
+0xFF2F63AE,
+0xFF2F63AE,
+0xFF2F63AE,
+0xFF2E62AD,
+0xFF2E62AD,
+0xFF2E62AD,
+0xFF2E62AD,
+0xFF2E62AD,
+0xFF2D61AC,
+0xFF2D61AC,
+0xFF2D61AC,
+0xFF2D61AC,
+0xFF2D61AC,
+0xFF2D61AC,
+0xFF2D61AC,
+0xFF2D61AC,
+0xFF2D61AC,
+0xFF2D61AC,
+0xFF2C60AB,
+0xFF2C60AB,
+0xFF2D5EAA,
+0xFF2D5EAA,
+0xFF2D5EAA,
+0xFF2C5DA9,
+0xFF2C5DA9,
+0xFF2C5DA9,
+0xFF2C5DA9,
+0xFF2B5CA8,
+0xFF2B5CA8,
+0xFF2B5CA8,
+0xFF2C5CA8,
+0xFF2C5CA8,
+0xFF2B5BA7,
+0xFF2B5BA7,
+0xFF2A5AA4,
+0xFF2A5AA4,
+0xFF2A5AA4,
+0xFF2A5AA4,
+0xFF2A5AA4,
+0xFF2A5AA4,
+0xFF2B5AA2,
+0xFF2B5AA2,
+0xFF2A59A1,
+0xFF2A59A1,
+0xFF2958A0,
+0xFF2958A0,
+0xFF2958A0,
+0xFF2958A0,
+0xFF2B57A0,
+0xFF2A569F,
+0xFF2B559F,
+0xFF2B559F,
+0xFF2A549C,
+0xFF2A549C,
+0xFF2B539B,
+0xFF2B539B,
+0xFF2B539B,
+0xFF2B539B,
+0xFF274E8F,
+0xFF274E8F,
+0xFF274E8F,
+0xFF284F90,
+0xFF284F92,
+0xFF284F92,
+0xFF295093,
+0xFF295093,
+0xFF295095,
+0xFF2A5196,
+0xFF2A5196,
+0xFF2A5196,
+0xFF295197,
+0xFF2A5298,
+0xFF2A5298,
+0xFF2A5298,
+0xFF2C5299,
+0xFF2C5299,
+0xFF2C5299,
+0xFF2C5299,
+0xFF2D539A,
+0xFF2D539A,
+0xFF2C549A,
+0xFF2C549A,
+0xFF2D559B,
+0xFF2D559B,
+0xFF2C569E,
+0xFF2C569E,
+0xFF2D579F,
+0xFF2D579F,
+0xFF2D579F,
+0xFF2D579F,
+0xFF2C58A1,
+0xFF2C58A1,
+0xFF2C58A1,
+0xFF2D59A2,
+0xFF2D59A2,
+0xFF2D59A2,
+0xFF2B5AA2,
+0xFF2B5AA2,
+0xFF2C5BA3,
+0xFF2C5BA3,
+0xFF2C5BA3,
+0xFF2C5BA3,
+0xFF2B5BA3,
+0xFF2C5CA4,
+0xFF2C5CA4,
+0xFF2C5CA4,
+0xFF2E5EA8,
+0xFF2E5EA8,
+0xFF2E5EA8,
+0xFF2E5EA8,
+0xFF2E5EA8,
+0xFF2E5EA8,
+0xFF2F5FA9,
+0xFF2F5FA9,
+0xFF2E5EA8,
+0xFF2E5EA8,
+0xFF2E5EA8,
+0xFF2F5FA9,
+0xFF2F5FA9,
+0xFF2F5FA9,
+0xFF3060AA,
+0xFF3060AA,
+0xFF2F5FA9,
+0xFF2F5FA9,
+0xFF3060AA,
+0xFF3060AA,
+0xFF3060AA,
+0xFF3060AA,
+0xFF3060AA,
+0xFF3060AA,
+0xFF3062AB,
+0xFF3062AB,
+0xFF3062AB,
+0xFF3163AC,
+0xFF3162AE,
+0xFF3162AE,
+0xFF3061AD,
+0xFF3061AD,
+0xFF3061AD,
+0xFF3061AD,
+0xFF3061AD,
+0xFF3061AD,
+0xFF3162AE,
+0xFF3162AE,
+0xFF3162AE,
+0xFF3162AE,
+0xFF3162AE,
+0xFF3162AE,
+0xFF2F63AE,
+0xFF2F63AE,
+0xFF2F63AE,
+0xFF3064AF,
+0xFF3064AF,
+0xFF3064AF,
+0xFF3064AF,
+0xFF3064AF,
+0xFF3064AF,
+0xFF3165B0,
+0xFF3165B0,
+0xFF3165B0,
+0xFF3165B0,
+0xFF3165B0,
+0xFF3165B0,
+0xFF3165B0,
+0xFF3165B0,
+0xFF3165B0,
+0xFF3165B0,
+0xFF3165B0,
+0xFF3165B1,
+0xFF3165B1,
+0xFF3165B0,
+0xFF3165B0,
+0xFF3165B0,
+0xFF3165B0,
+0xFF3064AF,
+0xFF3064AF,
+0xFF3165B0,
+0xFF3266B1,
+0xFF3266B1,
+0xFF3165B0,
+0xFF3165B0,
+0xFF3266B1,
+0xFF3266B1,
+0xFF3266B1,
+0xFF3266B1,
+0xFF3266B1,
+0xFF3066B0,
+0xFF3066B0,
+0xFF3066B0,
+0xFF3066B0,
+0xFF3066B0,
+0xFF3066B0,
+0xFF3066B0,
+0xFF3066B0,
+0xFF3167B1,
+0xFF3167B1,
+0xFF3167B1,
+0xFF3167B1,
+0xFF3167B1,
+0xFF3167B1,
+0xFF3167B1,
+0xFF3167B1,
+0xFF3167B1,
+0xFF3167B1,
+0xFF3167B1,
+0xFF3167B1,
+0xFF3167B1,
+0xFF3268B2,
+0xFF3268B2,
+0xFF3167B1,
+0xFF3167B1,
+0xFF3268B2,
+0xFF3268B2,
+0xFF3167B1,
+0xFF3167B1,
+0xFF3268B2,
+0xFF3268B2,
+0xFF3167B1,
+0xFF3166B2,
+0xFF3166B2,
+0xFF3267B3,
+0xFF3267B3,
+0xFF3267B3,
+0xFF3267B3,
+0xFF3267B3,
+0xFF3267B3,
+0xFF3267B3,
+0xFF3267B3,
+0xFF3267B3,
+0xFF3267B3,
+0xFF3267B3,
+0xFF3267B3,
+0xFF3267B3,
+0xFF3267B3,
+0xFF2F67B2,
+0xFF2F67B2,
+0xFF2F67B2,
+0xFF3068B3,
+0xFF2F67B2,
+0xFF2F67B2,
+0xFF2F67B2,
+0xFF2F67B2,
+0xFF3068B3,
+0xFF3068B3,
+0xFF3068B3,
+0xFF3068B3,
+0xFF3068B3,
+0xFF3068B3,
+0xFF3068B3,
+0xFF3068B3,
+0xFF3068B3,
+0xFF3068B3,
+0xFF3068B3,
+0xFF3068B3,
+0xFF3068B3,
+0xFF3068B3,
+0xFF3068B3,
+0xFF3068B3,
+0xFF3068B3,
+0xFF3068B3,
+0xFF3068B3,
+0xFF3068B3,
+0xFF3068B3,
+0xFF3068B3,
+0xFF3068B3,
+0xFF3068B3,
+0xFF3068B3,
+0xFF3068B3,
+0xFF3068B3,
+0xFF3068B3,
+0xFF3068B3,
+0xFF3068B3,
+0xFF3068B3,
+0xFF3169B4,
+0xFF3068B3,
+0xFF3068B3,
+0xFF3068B3,
+0xFF3068B3,
+0xFF3068B3,
+0xFF3068B3,
+0xFF3068B3,
+0xFF3068B3,
+0xFF2F67B2,
+0xFF2F67B2,
+0xFF2F67B2,
+0xFF2F67B2,
+0xFF2F67B2,
+0xFF2F67B2,
+0xFF2F67B2,
+0xFF2F67B2,
+0xFF2F67B2,
+0xFF2F67B2,
+0xFF2F67B2,
+0xFF2F67B2,
+0xFF2F67B2,
+0xFF2E66B1,
+0xFF3065B1,
+0xFF3065B1,
+0xFF2F67B2,
+0xFF2F67B2,
+0xFF2F67B2,
+0xFF2E66B1,
+0xFF2E66B1,
+0xFF2E66B1,
+0xFF3065B1,
+0xFF3166B2,
+0xFF3065B1,
+0xFF3065B1,
+0xFF3065B1,
+0xFF3065B1,
+0xFF3165B0,
+0xFF3165B0,
+0xFF3165B0,
+0xFF3165B0,
+0xFF3064AF,
+0xFF3064AF,
+0xFF3064AF,
+0xFF3064AF,
+0xFF3064AF,
+0xFF3064AF,
+0xFF2F63AE,
+0xFF2F63AE,
+0xFF2F63AE,
+0xFF2F63AE,
+0xFF2E62AD,
+0xFF2E62AD,
+0xFF2E62AD,
+0xFF2E62AD,
+0xFF2E62AD,
+0xFF2D61AC,
+0xFF2E62AD,
+0xFF2D61AC,
+0xFF2D61AC,
+0xFF2D61AC,
+0xFF2E62AD,
+0xFF2E62AD,
+0xFF2D61AC,
+0xFF2D61AC,
+0xFF2D61AC,
+0xFF2C60AB,
+0xFF2E5FAB,
+0xFF2E5FAB,
+0xFF2D5EAA,
+0xFF2D5EAA,
+0xFF2D5EAA,
+0xFF2D5EAA,
+0xFF2C5DA9,
+0xFF2C5DA9,
+0xFF2B5CA8,
+0xFF2B5CA8,
+0xFF2C5CA8,
+0xFF2C5CA8,
+0xFF2C5CA8,
+0xFF2B5BA7,
+0xFF2B5BA5,
+0xFF2B5BA5,
+0xFF2B5BA5,
+0xFF2B5BA5,
+0xFF2B5BA5,
+0xFF2A5AA4,
+0xFF2B5AA2,
+0xFF2B5AA2,
+0xFF2B5AA2,
+0xFF2A59A1,
+0xFF2A59A1,
+0xFF2958A0,
+0xFF2958A0,
+0xFF2958A0,
+0xFF2B57A0,
+0xFF2B57A0,
+0xFF2B559F,
+0xFF2B559F,
+0xFF2B559D,
+0xFF2A549C,
+0xFF2C549C,
+0xFF2B539B,
+0xFF2B539B,
+0xFF2B539B,
+0xFF275092,
+0xFF275092,
+0xFF275092,
+0xFF275092,
+0xFF295093,
+0xFF295093,
+0xFF2A5196,
+0xFF2A5196,
+0xFF2A5196,
+0xFF2A5196,
+0xFF2A5196,
+0xFF2B5297,
+0xFF2B5198,
+0xFF2B5198,
+0xFF2B5198,
+0xFF2B5198,
+0xFF2C5299,
+0xFF2C5299,
+0xFF2D539A,
+0xFF2D539A,
+0xFF2C549A,
+0xFF2D559B,
+0xFF2D559D,
+0xFF2D559D,
+0xFF2C569E,
+0xFF2C569E,
+0xFF2C569E,
+0xFF2D579F,
+0xFF2C589F,
+0xFF2D59A0,
+0xFF2D59A0,
+0xFF2D59A0,
+0xFF2D59A2,
+0xFF2D59A2,
+0xFF2D59A2,
+0xFF2D59A2,
+0xFF2B5AA2,
+0xFF2C5BA3,
+0xFF2C5BA3,
+0xFF2C5BA3,
+0xFF2C5BA3,
+0xFF2C5BA3,
+0xFF2B5BA5,
+0xFF2B5BA5,
+0xFF2C5CA6,
+0xFF2C5CA6,
+0xFF2C5CA6,
+0xFF2D5DA7,
+0xFF2E5EA8,
+0xFF2E5EA8,
+0xFF2E5EA8,
+0xFF2E5EA8,
+0xFF2F5FA9,
+0xFF2F5FA9,
+0xFF2F5FA9,
+0xFF2F5FA9,
+0xFF2F5FA9,
+0xFF2F5FA9,
+0xFF2F5FA9,
+0xFF2F5FA9,
+0xFF3060AA,
+0xFF3060AA,
+0xFF3060AA,
+0xFF3060AA,
+0xFF3062AB,
+0xFF2F61AA,
+0xFF2F61AA,
+0xFF2F61AA,
+0xFF2F61AA,
+0xFF3062AB,
+0xFF3062AB,
+0xFF3062AB,
+0xFF3062AB,
+0xFF3062AB,
+0xFF3163AC,
+0xFF3163AC,
+0xFF3162AE,
+0xFF3162AE,
+0xFF3162AE,
+0xFF3061AD,
+0xFF3162AE,
+0xFF3162AE,
+0xFF3162AE,
+0xFF3162AE,
+0xFF3162AE,
+0xFF3263AF,
+0xFF3064AF,
+0xFF3064AF,
+0xFF3064AF,
+0xFF3064AF,
+0xFF2F63AE,
+0xFF2F63AE,
+0xFF3064AF,
+0xFF3064AF,
+0xFF3064AF,
+0xFF3165B0,
+0xFF3165B0,
+0xFF3165B0,
+0xFF3165B0,
+0xFF3165B0,
+0xFF3165B0,
+0xFF3266B1,
+0xFF3266B1,
+0xFF3266B1,
+0xFF3165B0,
+0xFF3165B0,
+0xFF3266B1,
+0xFF3266B1,
+0xFF3266B2,
+0xFF3266B2,
+0xFF3266B2,
+0xFF3266B2,
+0xFF3167B1,
+0xFF3167B1,
+0xFF3167B1,
+0xFF3066B0,
+0xFF3066B0,
+0xFF3066B0,
+0xFF3167B1,
+0xFF3268B2,
+0xFF3167B1,
+0xFF3167B1,
+0xFF3167B1,
+0xFF3167B1,
+0xFF3167B1,
+0xFF3167B1,
+0xFF3268B2,
+0xFF3268B2,
+0xFF3268B2,
+0xFF3268B2,
+0xFF3268B2,
+0xFF3268B2,
+0xFF3268B2,
+0xFF3268B2,
+0xFF3268B2,
+0xFF3268B2,
+0xFF3167B1,
+0xFF3167B1,
+0xFF3167B1,
+0xFF3167B1,
+0xFF3167B1,
+0xFF3167B1,
+0xFF3167B1,
+0xFF3167B1,
+0xFF3167B1,
+0xFF3167B1,
+0xFF3268B2,
+0xFF3268B2,
+0xFF3268B2,
+0xFF3268B2,
+0xFF3268B2,
+0xFF3268B2,
+0xFF3167B1,
+0xFF3268B2,
+0xFF3268B2,
+0xFF3167B1,
+0xFF3167B1,
+0xFF3268B2,
+0xFF3268B2,
+0xFF3167B1,
+0xFF3268B2,
+0xFF3268B2,
+0xFF3268B2,
+0xFF3268B2,
+0xFF3268B2,
+0xFF3268B2,
+0xFF3268B2,
+0xFF3268B2,
+0xFF3268B2,
+0xFF3268B2,
+0xFF3268B2,
+0xFF3268B2,
+0xFF3268B2,
+0xFF3268B2,
+0xFF3268B2,
+0xFF3268B2,
+0xFF3068B2,
+0xFF3068B2,
+0xFF3068B2,
+0xFF3068B2,
+0xFF3068B2,
+0xFF3068B2,
+0xFF3068B2,
+0xFF3068B2,
+0xFF3068B2,
+0xFF3068B2,
+0xFF3068B2,
+0xFF3068B2,
+0xFF3068B2,
+0xFF3169B3,
+0xFF3169B3,
+0xFF3169B3,
+0xFF2F69B3,
+0xFF2F69B3,
+0xFF306AB4,
+0xFF306AB4,
+0xFF306AB4,
+0xFF306AB4,
+0xFF306AB4,
+0xFF306AB4,
+0xFF306AB4,
+0xFF306AB4,
+0xFF306AB4,
+0xFF306AB4,
+0xFF306AB4,
+0xFF306AB4,
+0xFF306AB4,
+0xFF306AB4,
+0xFF306AB4,
+0xFF306AB4,
+0xFF306AB4,
+0xFF306AB4,
+0xFF306AB4,
+0xFF306AB4,
+0xFF306AB4,
+0xFF306AB4,
+0xFF306AB4,
+0xFF306AB4,
+0xFF306AB4,
+0xFF306AB4,
+0xFF306AB4,
+0xFF306AB4,
+0xFF306AB4,
+0xFF306AB4,
+0xFF3169B4,
+0xFF3169B4,
+0xFF3169B4,
+0xFF3169B4,
+0xFF3169B4,
+0xFF3169B4,
+0xFF3169B4,
+0xFF3169B4,
+0xFF3169B4,
+0xFF3169B4,
+0xFF3169B4,
+0xFF3068B3,
+0xFF3068B3,
+0xFF3068B3,
+0xFF3068B3,
+0xFF3068B3,
+0xFF3068B3,
+0xFF2F67B2,
+0xFF2F67B2,
+0xFF2F67B2,
+0xFF2E66B1,
+0xFF2F67B2,
+0xFF2F67B2,
+0xFF2F67B2,
+0xFF3166B2,
+0xFF3065B1,
+0xFF3065B1,
+0xFF3065B1,
+0xFF3066B0,
+0xFF3066B0,
+0xFF3165B0,
+0xFF3165B0,
+0xFF3165B1,
+0xFF3165B1,
+0xFF3064B0,
+0xFF3064B0,
+0xFF3064B0,
+0xFF3064B0,
+0xFF3064B0,
+0xFF3064B0,
+0xFF3064B0,
+0xFF3064B0,
+0xFF2F63AF,
+0xFF2F63AF,
+0xFF2F63AF,
+0xFF2F63AF,
+0xFF2F63AF,
+0xFF2E62AE,
+0xFF2F63AE,
+0xFF2E62AD,
+0xFF2E62AD,
+0xFF2E62AD,
+0xFF2E62AD,
+0xFF2D61AC,
+0xFF2F60AC,
+0xFF2E5FAB,
+0xFF2F60AC,
+0xFF2E5FAB,
+0xFF2E5FAB,
+0xFF2E5FAB,
+0xFF2E5FAB,
+0xFF2E5FAB,
+0xFF2D5EAA,
+0xFF2D5EAA,
+0xFF2D5EAA,
+0xFF2C5DA9,
+0xFF2C5DA9,
+0xFF2B5CA8,
+0xFF2B5CA8,
+0xFF2B5CA8,
+0xFF2B5CA8,
+0xFF2B5CA8,
+0xFF2C5CA6,
+0xFF2C5CA6,
+0xFF2C5CA6,
+0xFF2B5BA5,
+0xFF2B5BA5,
+0xFF2A5AA4,
+0xFF2A5AA4,
+0xFF2A5AA4,
+0xFF2B59A4,
+0xFF2A58A3,
+0xFF2A59A1,
+0xFF2A59A1,
+0xFF2A59A1,
+0xFF2A59A1,
+0xFF2B57A0,
+0xFF2B57A0,
+0xFF2B57A0,
+0xFF2B57A0,
+0xFF2B559D,
+0xFF2B559D,
+0xFF2A549C,
+0xFF2A549C,
+0xFF2A549C,
+0xFF2A549C,
+0xFF275092,
+0xFF275092,
+0xFF275092,
+0xFF285193,
+0xFF295093,
+0xFF2A5194,
+0xFF2A5196,
+0xFF2B5297,
+0xFF2B5297,
+0xFF2B5297,
+0xFF2B5297,
+0xFF2B5297,
+0xFF2B5198,
+0xFF2C5299,
+0xFF2C5299,
+0xFF2C5299,
+0xFF2D539A,
+0xFF2D539A,
+0xFF2D539A,
+0xFF2E549B,
+0xFF2D559B,
+0xFF2D559B,
+0xFF2E569E,
+0xFF2E569E,
+0xFF2C569E,
+0xFF2D579F,
+0xFF2D579F,
+0xFF2D579F,
+0xFF2D59A0,
+0xFF2D59A0,
+0xFF2D59A0,
+0xFF2D59A0,
+0xFF2D59A2,
+0xFF2D59A2,
+0xFF2D59A2,
+0xFF2E5AA3,
+0xFF2C5BA3,
+0xFF2C5BA3,
+0xFF2D5CA4,
+0xFF2D5CA4,
+0xFF2D5CA4,
+0xFF2D5CA4,
+0xFF2C5CA6,
+0xFF2C5CA6,
+0xFF2C5CA6,
+0xFF2D5DA7,
+0xFF2D5DA7,
+0xFF2D5DA7,
+0xFF2E5EA8,
+0xFF2E5EA8,
+0xFF2E5EA8,
+0xFF2E5EA8,
+0xFF2F5FA9,
+0xFF2F5FA9,
+0xFF2F5FA9,
+0xFF2F5FA9,
+0xFF3060AA,
+0xFF3060AA,
+0xFF3060AA,
+0xFF3060AA,
+0xFF3060AA,
+0xFF3161AB,
+0xFF3161AB,
+0xFF3161AB,
+0xFF3062AB,
+0xFF3062AB,
+0xFF3062AB,
+0xFF3062AB,
+0xFF3062AB,
+0xFF3062AB,
+0xFF3062AB,
+0xFF3062AB,
+0xFF3062AB,
+0xFF3163AC,
+0xFF3163AC,
+0xFF3163AC,
+0xFF3162AE,
+0xFF3162AE,
+0xFF3162AE,
+0xFF3162AE,
+0xFF3263AF,
+0xFF3263AF,
+0xFF3263AF,
+0xFF3263AF,
+0xFF3263AF,
+0xFF3364B0,
+0xFF3165B0,
+0xFF3165B0,
+0xFF3064AF,
+0xFF3064AF,
+0xFF3064AF,
+0xFF3064AF,
+0xFF3064AF,
+0xFF3165B0,
+0xFF3165B0,
+0xFF3165B0,
+0xFF3266B1,
+0xFF3266B1,
+0xFF3266B1,
+0xFF3266B1,
+0xFF3266B1,
+0xFF3266B1,
+0xFF3266B1,
+0xFF3367B2,
+0xFF3266B1,
+0xFF3266B1,
+0xFF3266B1,
+0xFF3266B1,
+0xFF3367B3,
+0xFF3367B3,
+0xFF3367B3,
+0xFF3367B3,
+0xFF3268B2,
+0xFF3268B2,
+0xFF3268B2,
+0xFF3268B2,
+0xFF3167B1,
+0xFF3167B1,
+0xFF3268B2,
+0xFF3268B2,
+0xFF3268B2,
+0xFF3268B2,
+0xFF3268B2,
+0xFF3268B2,
+0xFF3268B2,
+0xFF3268B2,
+0xFF3268B2,
+0xFF3268B2,
+0xFF3268B2,
+0xFF3268B2,
+0xFF3268B2,
+0xFF3268B2,
+0xFF3268B2,
+0xFF3268B2,
+0xFF3268B2,
+0xFF3268B2,
+0xFF3167B1,
+0xFF3268B2,
+0xFF3268B2,
+0xFF3268B2,
+0xFF3268B2,
+0xFF3268B2,
+0xFF3268B2,
+0xFF3369B3,
+0xFF3268B2,
+0xFF3268B2,
+0xFF3268B2,
+0xFF3268B2,
+0xFF3268B2,
+0xFF3268B2,
+0xFF3268B2,
+0xFF3268B2,
+0xFF3167B1,
+0xFF3268B2,
+0xFF3268B2,
+0xFF3268B2,
+0xFF3268B2,
+0xFF3268B2,
+0xFF3268B2,
+0xFF3167B1,
+0xFF3268B2,
+0xFF3268B2,
+0xFF3268B2,
+0xFF3268B2,
+0xFF3268B2,
+0xFF3268B2,
+0xFF3268B2,
+0xFF3268B2,
+0xFF3369B3,
+0xFF3268B2,
+0xFF3268B2,
+0xFF3369B3,
+0xFF3369B3,
+0xFF3369B3,
+0xFF3268B2,
+0xFF3268B2,
+0xFF3169B3,
+0xFF3169B3,
+0xFF3169B3,
+0xFF3169B3,
+0xFF3169B3,
+0xFF3169B3,
+0xFF3068B2,
+0xFF3068B2,
+0xFF3169B3,
+0xFF3169B3,
+0xFF3169B3,
+0xFF3169B3,
+0xFF3169B3,
+0xFF3169B3,
+0xFF3169B3,
+0xFF326AB4,
+0xFF306AB4,
+0xFF306AB4,
+0xFF306AB4,
+0xFF306AB4,
+0xFF306AB4,
+0xFF306AB4,
+0xFF306AB4,
+0xFF306AB4,
+0xFF316BB5,
+0xFF306AB4,
+0xFF306AB4,
+0xFF306AB4,
+0xFF306AB4,
+0xFF306AB4,
+0xFF306AB4,
+0xFF306AB4,
+0xFF306AB4,
+0xFF306AB4,
+0xFF306AB4,
+0xFF306AB4,
+0xFF306AB4,
+0xFF306AB4,
+0xFF316BB5,
+0xFF316BB5,
+0xFF316BB5,
+0xFF316BB5,
+0xFF316BB5,
+0xFF316BB5,
+0xFF316BB5,
+0xFF316BB5,
+0xFF316BB5,
+0xFF316BB5,
+0xFF3169B4,
+0xFF3169B4,
+0xFF3169B4,
+0xFF3169B4,
+0xFF3169B4,
+0xFF3169B4,
+0xFF3169B4,
+0xFF3169B4,
+0xFF3169B4,
+0xFF3169B4,
+0xFF3169B4,
+0xFF3169B4,
+0xFF3169B4,
+0xFF3068B3,
+0xFF3068B3,
+0xFF3068B3,
+0xFF3068B3,
+0xFF3068B3,
+0xFF3068B3,
+0xFF2F67B2,
+0xFF2F67B2,
+0xFF2F67B2,
+0xFF2F67B2,
+0xFF2F67B2,
+0xFF3166B2,
+0xFF3166B2,
+0xFF3166B2,
+0xFF3166B2,
+0xFF3167B1,
+0xFF3066B0,
+0xFF3165B0,
+0xFF3165B0,
+0xFF3165B1,
+0xFF3165B1,
+0xFF3165B1,
+0xFF3165B1,
+0xFF3165B1,
+0xFF3064B0,
+0xFF3064B0,
+0xFF3064B0,
+0xFF3165B1,
+0xFF3064B0,
+0xFF3064B0,
+0xFF3064B0,
+0xFF3064B0,
+0xFF3064B0,
+0xFF2F63AF,
+0xFF2F63AF,
+0xFF2F63AE,
+0xFF2F63AE,
+0xFF2E62AD,
+0xFF2E62AD,
+0xFF2E62AD,
+0xFF2E62AD,
+0xFF2F60AC,
+0xFF2F60AC,
+0xFF2F60AC,
+0xFF2F60AC,
+0xFF2F60AC,
+0xFF2E5FAB,
+0xFF2E5FAB,
+0xFF2E5FAB,
+0xFF2E5FAB,
+0xFF2E5FAB,
+0xFF2D5EAA,
+0xFF2D5EAA,
+0xFF2C5DA9,
+0xFF2C5DA9,
+0xFF2C5DA9,
+0xFF2C5DA9,
+0xFF2C5DA9,
+0xFF2C5DA9,
+0xFF2D5DA7,
+0xFF2D5DA7,
+0xFF2C5CA6,
+0xFF2C5CA6,
+0xFF2B5BA5,
+0xFF2A5AA4,
+0xFF2A5AA4,
+0xFF2A5AA4,
+0xFF2C5AA5,
+0xFF2B59A4,
+0xFF2A59A1,
+0xFF2A59A1,
+0xFF2A59A1,
+0xFF2A59A1,
+0xFF2C58A1,
+0xFF2C58A1,
+0xFF2C58A1,
+0xFF2C58A1,
+0xFF2C569E,
+0xFF2C569E,
+0xFF2B559D,
+0xFF2B559D,
+0xFF2A549C,
+0xFF2A549C,
+0xFF274F94,
+0xFF274F94,
+0xFF285095,
+0xFF285095,
+0xFF295196,
+0xFF295196,
+0xFF2A5297,
+0xFF2A5297,
+0xFF2C5398,
+0xFF2C5398,
+0xFF2C5398,
+0xFF2C5398,
+0xFF2C5398,
+0xFF2C5398,
+0xFF2C5398,
+0xFF2C5398,
+0xFF2C549A,
+0xFF2C549A,
+0xFF2D559B,
+0xFF2D559B,
+0xFF2E569C,
+0xFF2E569C,
+0xFF2C569E,
+0xFF2C569E,
+0xFF2D579F,
+0xFF2D579F,
+0xFF2C589F,
+0xFF2D59A0,
+0xFF2D59A0,
+0xFF2D59A0,
+0xFF2D59A0,
+0xFF2D59A0,
+0xFF2D59A2,
+0xFF2E5AA3,
+0xFF2C5BA3,
+0xFF2C5BA3,
+0xFF2C5BA3,
+0xFF2D5CA4,
+0xFF2D5CA4,
+0xFF2D5CA4,
+0xFF2D5DA7,
+0xFF2D5DA7,
+0xFF2D5DA7,
+0xFF2D5DA7,
+0xFF2D5DA7,
+0xFF2E5EA8,
+0xFF2D5FA8,
+0xFF2D5FA8,
+0xFF2F5FA9,
+0xFF2F5FA9,
+0xFF2F5FA9,
+0xFF2F5FA9,
+0xFF2F5FA9,
+0xFF2F5FA9,
+0xFF2F5FA9,
+0xFF2F5FA9,
+0xFF3060AA,
+0xFF3060AA,
+0xFF3060AA,
+0xFF3161AB,
+0xFF3161AB,
+0xFF3161AB,
+0xFF3061AD,
+0xFF3061AD,
+0xFF3163AC,
+0xFF3062AB,
+0xFF3062AB,
+0xFF3062AB,
+0xFF3062AB,
+0xFF3062AB,
+0xFF3163AC,
+0xFF3163AC,
+0xFF3064AD,
+0xFF3064AD,
+0xFF3064AD,
+0xFF3064AD,
+0xFF3064AF,
+0xFF3064AF,
+0xFF3064AF,
+0xFF3064AF,
+0xFF3263AF,
+0xFF3364B0,
+0xFF3364B0,
+0xFF3364B0,
+0xFF3364B0,
+0xFF3465B1,
+0xFF3266B1,
+0xFF3266B1,
+0xFF3165B0,
+0xFF3165B0,
+0xFF3165B0,
+0xFF3165B0,
+0xFF3165B0,
+0xFF3165B0,
+0xFF3266B1,
+0xFF3266B1,
+0xFF3465B1,
+0xFF3465B1,
+0xFF3465B1,
+0xFF3566B2,
+0xFF3367B2,
+0xFF3367B2,
+0xFF3367B2,
+0xFF3367B2,
+0xFF3367B2,
+0xFF3367B2,
+0xFF3367B3,
+0xFF3367B3,
+0xFF3367B3,
+0xFF3367B3,
+0xFF3367B3,
+0xFF3367B3,
+0xFF3268B2,
+0xFF3369B3,
+0xFF3369B3,
+0xFF3369B3,
+0xFF3268B2,
+0xFF3268B2,
+0xFF3268B2,
+0xFF3369B3,
+0xFF3268B2,
+0xFF3369B3,
+0xFF3369B3,
+0xFF3268B2,
+0xFF3268B2,
+0xFF3369B3,
+0xFF3369B3,
+0xFF3268B2,
+0xFF3268B2,
+0xFF3268B2,
+0xFF3268B2,
+0xFF3268B2,
+0xFF3268B2,
+0xFF3268B2,
+0xFF3268B2,
+0xFF3268B2,
+0xFF3268B2,
+0xFF3369B3,
+0xFF3369B3,
+0xFF3369B3,
+0xFF3369B3,
+0xFF3369B3,
+0xFF3369B3,
+0xFF3369B3,
+0xFF3268B2,
+0xFF3369B3,
+0xFF3369B3,
+0xFF3369B3,
+0xFF3369B3,
+0xFF3268B2,
+0xFF3369B3,
+0xFF3369B3,
+0xFF3268B2,
+0xFF3369B3,
+0xFF3369B3,
+0xFF3268B2,
+0xFF3268B2,
+0xFF3369B3,
+0xFF3369B3,
+0xFF3268B2,
+0xFF3369B3,
+0xFF3369B3,
+0xFF3369B3,
+0xFF3369B3,
+0xFF3369B3,
+0xFF3369B3,
+0xFF3369B3,
+0xFF3369B3,
+0xFF3369B3,
+0xFF3369B3,
+0xFF3369B3,
+0xFF3369B3,
+0xFF346AB4,
+0xFF346AB4,
+0xFF3369B3,
+0xFF3369B3,
+0xFF326AB4,
+0xFF326AB4,
+0xFF326AB4,
+0xFF326AB4,
+0xFF326AB4,
+0xFF3169B3,
+0xFF3169B3,
+0xFF3169B3,
+0xFF3169B3,
+0xFF3169B3,
+0xFF3169B3,
+0xFF3169B3,
+0xFF3169B3,
+0xFF326AB4,
+0xFF326AB4,
+0xFF326AB4,
+0xFF306AB4,
+0xFF306AB4,
+0xFF316BB5,
+0xFF316BB5,
+0xFF316BB5,
+0xFF316BB5,
+0xFF316BB5,
+0xFF316BB5,
+0xFF316BB5,
+0xFF316BB5,
+0xFF316BB5,
+0xFF316BB5,
+0xFF316BB5,
+0xFF316BB5,
+0xFF316BB5,
+0xFF316BB5,
+0xFF316BB5,
+0xFF316BB5,
+0xFF316BB5,
+0xFF316BB5,
+0xFF316BB5,
+0xFF316BB5,
+0xFF316BB5,
+0xFF316BB5,
+0xFF316BB5,
+0xFF316BB5,
+0xFF316BB5,
+0xFF316BB5,
+0xFF316BB5,
+0xFF316BB5,
+0xFF316BB5,
+0xFF316BB5,
+0xFF306AB4,
+0xFF306AB4,
+0xFF306AB4,
+0xFF306AB4,
+0xFF3169B4,
+0xFF3169B4,
+0xFF3169B4,
+0xFF3169B4,
+0xFF3169B4,
+0xFF3169B4,
+0xFF3169B4,
+0xFF3169B4,
+0xFF3169B4,
+0xFF3068B3,
+0xFF3068B3,
+0xFF3068B3,
+0xFF306AB4,
+0xFF306AB4,
+0xFF3068B3,
+0xFF3068B3,
+0xFF3068B3,
+0xFF3068B3,
+0xFF3068B3,
+0xFF3068B3,
+0xFF3267B3,
+0xFF3267B3,
+0xFF3267B3,
+0xFF3267B3,
+0xFF3167B1,
+0xFF3167B1,
+0xFF3266B1,
+0xFF3266B1,
+0xFF3266B2,
+0xFF3266B2,
+0xFF3266B2,
+0xFF3165B1,
+0xFF3165B1,
+0xFF3165B1,
+0xFF3165B1,
+0xFF3165B1,
+0xFF3266B2,
+0xFF3165B1,
+0xFF3165B1,
+0xFF3064B0,
+0xFF3064B0,
+0xFF3064B0,
+0xFF3064B0,
+0xFF2F63AF,
+0xFF3064AF,
+0xFF2F63AE,
+0xFF3162AE,
+0xFF3162AE,
+0xFF3162AE,
+0xFF3162AE,
+0xFF3061AD,
+0xFF3061AD,
+0xFF3061AD,
+0xFF3061AD,
+0xFF2F60AC,
+0xFF2F60AC,
+0xFF2F60AC,
+0xFF2F60AC,
+0xFF2F60AC,
+0xFF2F60AC,
+0xFF2F60AC,
+0xFF2E5FAB,
+0xFF2D5EAA,
+0xFF2D5EAA,
+0xFF2D5EAA,
+0xFF2D5EAA,
+0xFF2D5EAA,
+0xFF2D5EAA,
+0xFF2D5DA9,
+0xFF2D5DA9,
+0xFF2D5DA9,
+0xFF2C5CA8,
+0xFF2C5CA8,
+0xFF2B5BA7,
+0xFF2B5BA7,
+0xFF2B5BA7,
+0xFF2C5AA5,
+0xFF2C5AA5,
+0xFF2B59A4,
+0xFF2B59A4,
+0xFF2B5AA2,
+0xFF2B5AA2,
+0xFF2D59A2,
+0xFF2C58A1,
+0xFF2D59A2,
+0xFF2C58A1,
+0xFF2D57A1,
+0xFF2C56A0,
+0xFF2C569E,
+0xFF2B559D,
+0xFF2B559D,
+0xFF2B559D,
+0xFF274F94,
+0xFF285095,
+0xFF285095,
+0xFF285095,
+0xFF295196,
+0xFF2A5297,
+0xFF2A5297,
+0xFF2B5398,
+0xFF2C5398,
+0xFF2C5398,
+0xFF2C5398,
+0xFF2C5398,
+0xFF2C5398,
+0xFF2C5398,
+0xFF2C5398,
+0xFF2C5398,
+0xFF2D559B,
+0xFF2B569B,
+0xFF2D559B,
+0xFF2D559B,
+0xFF2E569C,
+0xFF2E569C,
+0xFF2D579F,
+0xFF2D579F,
+0xFF2D579F,
+0xFF2D579F,
+0xFF2C589F,
+0xFF2D59A0,
+0xFF2D59A0,
+0xFF2D59A0,
+0xFF2D59A0,
+0xFF2D59A0,
+0xFF2E5AA3,
+0xFF2E5AA3,
+0xFF2C5BA3,
+0xFF2C5BA3,
+0xFF2D5CA4,
+0xFF2D5CA4,
+0xFF2D5CA4,
+0xFF2D5CA4,
+0xFF2D5DA7,
+0xFF2D5DA7,
+0xFF2D5DA7,
+0xFF2E5EA8,
+0xFF2E5EA8,
+0xFF2E5EA8,
+0xFF2E60A9,
+0xFF2E60A9,
+0xFF3060AA,
+0xFF3060AA,
+0xFF3060AA,
+0xFF3060AA,
+0xFF3060AA,
+0xFF3060AA,
+0xFF3060AA,
+0xFF3060AA,
+0xFF3161AB,
+0xFF3161AB,
+0xFF3161AB,
+0xFF3161AB,
+0xFF3161AB,
+0xFF3161AB,
+0xFF3061AD,
+0xFF3061AD,
+0xFF3062AB,
+0xFF3062AB,
+0xFF3062AB,
+0xFF3062AB,
+0xFF3062AB,
+0xFF3163AC,
+0xFF3163AC,
+0xFF3264AD,
+0xFF3165AE,
+0xFF3165AE,
+0xFF3165AE,
+0xFF3165AE,
+0xFF3165B0,
+0xFF3165B0,
+0xFF3165B0,
+0xFF3266B1,
+0xFF3364B0,
+0xFF3364B0,
+0xFF3364B0,
+0xFF3364B0,
+0xFF3465B1,
+0xFF3465B1,
+0xFF3266B1,
+0xFF3266B1,
+0xFF3165B0,
+0xFF3165B0,
+0xFF3165B0,
+0xFF3165B0,
+0xFF3266B1,
+0xFF3266B1,
+0xFF3367B2,
+0xFF3367B2,
+0xFF3266B1,
+0xFF3266B1,
+0xFF3566B2,
+0xFF3367B2,
+0xFF3367B2,
+0xFF3367B2,
+0xFF3367B2,
+0xFF3468B3,
+0xFF3468B3,
+0xFF3468B3,
+0xFF3468B4,
+0xFF3367B3,
+0xFF3367B3,
+0xFF3367B3,
+0xFF3367B3,
+0xFF3367B3,
+0xFF3268B2,
+0xFF3369B3,
+0xFF3369B3,
+0xFF3369B3,
+0xFF3369B3,
+0xFF3369B3,
+0xFF3369B3,
+0xFF3369B3,
+0xFF3268B2,
+0xFF3369B3,
+0xFF3369B3,
+0xFF3268B2,
+0xFF3268B2,
+0xFF3369B3,
+0xFF3369B3,
+0xFF3268B2,
+0xFF3369B3,
+0xFF3369B3,
+0xFF3369B3,
+0xFF3369B3,
+0xFF3369B3,
+0xFF3369B3,
+0xFF3369B3,
+0xFF3369B3,
+0xFF3268B2,
+0xFF3369B3,
+0xFF3369B3,
+0xFF3369B3,
+0xFF3369B3,
+0xFF3369B3,
+0xFF3369B3,
+0xFF346AB4,
+0xFF3369B3,
+0xFF3369B3,
+0xFF346AB4,
+0xFF346AB4,
+0xFF3369B3,
+0xFF3369B3,
+0xFF3369B3,
+0xFF346AB4,
+0xFF3369B3,
+0xFF3369B3,
+0xFF346AB4,
+0xFF3369B3,
+0xFF3369B3,
+0xFF346AB4,
+0xFF3369B3,
+0xFF3369B3,
+0xFF3369B3,
+0xFF3369B3,
+0xFF3369B3,
+0xFF346AB4,
+0xFF346AB4,
+0xFF346AB4,
+0xFF346AB4,
+0xFF346AB4,
+0xFF346AB4,
+0xFF326AB4,
+0xFF346AB4,
+0xFF326AB4,
+0xFF356BB5,
+0xFF336BB5,
+0xFF346AB4,
+0xFF3169B3,
+0xFF326AB4,
+0xFF326AB4,
+0xFF326AB4,
+0xFF326AB4,
+0xFF326AB4,
+0xFF326AB4,
+0xFF3169B3,
+0xFF3169B3,
+0xFF326AB4,
+0xFF326AB4,
+0xFF326AB4,
+0xFF326AB4,
+0xFF326AB4,
+0xFF326AB4,
+0xFF326AB4,
+0xFF326AB4,
+0xFF306AB4,
+0xFF316BB5,
+0xFF316BB5,
+0xFF316BB5,
+0xFF316BB5,
+0xFF316BB5,
+0xFF316BB5,
+0xFF316BB5,
+0xFF316BB5,
+0xFF316BB5,
+0xFF316BB5,
+0xFF316BB5,
+0xFF316BB5,
+0xFF316BB5,
+0xFF316BB5,
+0xFF316BB5,
+0xFF316BB5,
+0xFF316BB5,
+0xFF316BB5,
+0xFF316BB5,
+0xFF316BB5,
+0xFF316BB5,
+0xFF316BB5,
+0xFF316BB5,
+0xFF316BB5,
+0xFF316BB5,
+0xFF316BB5,
+0xFF316BB5,
+0xFF316BB5,
+0xFF316BB5,
+0xFF316BB5,
+0xFF316BB5,
+0xFF316BB5,
+0xFF316BB5,
+0xFF316BB5,
+0xFF316BB5,
+0xFF326AB5,
+0xFF326AB5,
+0xFF326AB5,
+0xFF326AB5,
+0xFF326AB5,
+0xFF326AB5,
+0xFF326AB5,
+0xFF326AB5,
+0xFF326AB5,
+0xFF326AB5,
+0xFF3169B4,
+0xFF3169B4,
+0xFF316BB5,
+0xFF306AB4,
+0xFF3169B4,
+0xFF3169B4,
+0xFF3068B3,
+0xFF3068B3,
+0xFF3068B3,
+0xFF3169B4,
+0xFF3368B4,
+0xFF3368B4,
+0xFF3267B3,
+0xFF3267B3,
+0xFF3268B2,
+0xFF3268B2,
+0xFF3367B2,
+0xFF3266B1,
+0xFF3266B2,
+0xFF3166B2,
+0xFF3266B2,
+0xFF3266B2,
+0xFF3266B2,
+0xFF3266B2,
+0xFF3266B2,
+0xFF3266B2,
+0xFF3266B2,
+0xFF3165B1,
+0xFF3165B1,
+0xFF3165B1,
+0xFF3165B1,
+0xFF3064B0,
+0xFF3064B0,
+0xFF2F63AF,
+0xFF3064AF,
+0xFF3064AF,
+0xFF3162AE,
+0xFF3162AE,
+0xFF3162AE,
+0xFF3162AE,
+0xFF3162AE,
+0xFF3162AE,
+0xFF3061AD,
+0xFF3061AD,
+0xFF3061AD,
+0xFF3061AD,
+0xFF3061AD,
+0xFF3061AD,
+0xFF3061AD,
+0xFF3061AD,
+0xFF2F60AC,
+0xFF2F60AC,
+0xFF2E5FAB,
+0xFF2E5FAB,
+0xFF2E5FAB,
+0xFF2E5FAB,
+0xFF2E5FAB,
+0xFF2D5EAA,
+0xFF2D5DA9,
+0xFF2D5DA9,
+0xFF2D5DA9,
+0xFF2D5DA9,
+0xFF2C5CA8,
+0xFF2C5CA8,
+0xFF2C5CA8,
+0xFF2C5CA8,
+0xFF2D5BA6,
+0xFF2C5AA5,
+0xFF2C5AA5,
+0xFF2C5AA5,
+0xFF2C5BA3,
+0xFF2C5BA3,
+0xFF2D59A2,
+0xFF2D59A2,
+0xFF2D59A2,
+0xFF2D59A2,
+0xFF2D57A1,
+0xFF2C56A0,
+0xFF2C569E,
+0xFF2B559D,
+0xFF2B559D,
+0xFF2B559D,
+0xFF284F94,
+0xFF295095,
+0xFF2A5196,
+0xFF2B5297,
+0xFF2B5297,
+0xFF2B5297,
+0xFF2C5398,
+0xFF2C5398,
+0xFF2B5297,
+0xFF2C5398,
+0xFF2C5299,
+0xFF2D539A,
+0xFF2D539A,
+0xFF2D539A,
+0xFF2E549B,
+0xFF2D559B,
+0xFF2B569B,
+0xFF2B589C,
+0xFF2C569E,
+0xFF2C569E,
+0xFF2C569E,
+0xFF2C569E,
+0xFF2D579F,
+0xFF2D579F,
+0xFF2E58A0,
+0xFF2E58A0,
+0xFF2E58A2,
+0xFF2E58A2,
+0xFF2D59A2,
+0xFF2D59A2,
+0xFF2E5AA3,
+0xFF2E5AA3,
+0xFF2D5BA6,
+0xFF2D5BA6,
+0xFF2D5BA6,
+0xFF2D5BA6,
+0xFF2D5DA7,
+0xFF2D5DA7,
+0xFF2D5DA7,
+0xFF2D5DA7,
+0xFF2E5EA8,
+0xFF2E5EA8,
+0xFF2E5EA8,
+0xFF2F5FA9,
+0xFF2F5FA9,
+0xFF2F5FA9,
+0xFF3060AA,
+0xFF3060AA,
+0xFF2F5FA9,
+0xFF3060AA,
+0xFF3060AA,
+0xFF3060AA,
+0xFF3060AA,
+0xFF3060AA,
+0xFF3060AA,
+0xFF3060AA,
+0xFF3062AB,
+0xFF3062AB,
+0xFF3062AB,
+0xFF3062AB,
+0xFF3062AB,
+0xFF3163AC,
+0xFF3163AC,
+0xFF3163AC,
+0xFF3162AE,
+0xFF3162AE,
+0xFF3162AE,
+0xFF3162AE,
+0xFF3263AF,
+0xFF3263AF,
+0xFF3263AF,
+0xFF3263AF,
+0xFF3263AF,
+0xFF3263AF,
+0xFF3064AF,
+0xFF3064AF,
+0xFF3165B0,
+0xFF3165B0,
+0xFF3165B0,
+0xFF3165B0,
+0xFF3165B0,
+0xFF3165B0,
+0xFF3165B0,
+0xFF3266B1,
+0xFF3266B1,
+0xFF3266B1,
+0xFF3266B1,
+0xFF3266B1,
+0xFF3367B2,
+0xFF3367B2,
+0xFF3268B2,
+0xFF3268B2,
+0xFF3268B2,
+0xFF3268B2,
+0xFF3268B2,
+0xFF3268B2,
+0xFF3268B2,
+0xFF3268B2,
+0xFF3468B3,
+0xFF3369B3,
+0xFF3369B3,
+0xFF3369B3,
+0xFF3268B2,
+0xFF3268B2,
+0xFF3369B3,
+0xFF3369B3,
+0xFF3369B3,
+0xFF3268B2,
+0xFF3268B2,
+0xFF3268B2,
+0xFF3268B2,
+0xFF3369B3,
+0xFF3468B3,
+0xFF3468B3,
+0xFF3369B3,
+0xFF3369B3,
+0xFF3369B3,
+0xFF3369B3,
+0xFF3369B3,
+0xFF3369B3,
+0xFF3369B3,
+0xFF3369B3,
+0xFF3369B3,
+0xFF3369B3,
+0xFF3369B3,
+0xFF3369B3,
+0xFF3369B3,
+0xFF3369B3,
+0xFF3369B3,
+0xFF3369B3,
+0xFF3369B3,
+0xFF3369B3,
+0xFF3369B3,
+0xFF3369B3,
+0xFF3369B3,
+0xFF3369B3,
+0xFF3169B3,
+0xFF3169B3,
+0xFF3169B3,
+0xFF3169B3,
+0xFF326AB4,
+0xFF326AB4,
+0xFF326AB4,
+0xFF326AB4,
+0xFF326AB4,
+0xFF326AB4,
+0xFF326AB4,
+0xFF3169B3,
+0xFF3169B3,
+0xFF326AB4,
+0xFF326AB4,
+0xFF326AB4,
+0xFF326AB4,
+0xFF326AB4,
+0xFF326AB4,
+0xFF326AB4,
+0xFF326AB4,
+0xFF326AB4,
+0xFF326AB4,
+0xFF326AB4,
+0xFF326AB4,
+0xFF326AB4,
+0xFF326AB4,
+0xFF326AB4,
+0xFF326AB4,
+0xFF326AB4,
+0xFF326AB4,
+0xFF326AB4,
+0xFF326AB4,
+0xFF316BB4,
+0xFF326AB4,
+0xFF316BB4,
+0xFF326AB4,
+0xFF316BB4,
+0xFF326AB4,
+0xFF326AB4,
+0xFF326AB5,
+0xFF326AB5,
+0xFF326AB5,
+0xFF326AB5,
+0xFF326AB5,
+0xFF326AB5,
+0xFF326AB5,
+0xFF326AB5,
+0xFF326AB5,
+0xFF326AB5,
+0xFF326AB5,
+0xFF336BB6,
+0xFF336BB6,
+0xFF336BB6,
+0xFF336BB6,
+0xFF326AB5,
+0xFF316BB4,
+0xFF316BB4,
+0xFF316BB4,
+0xFF316BB4,
+0xFF316BB4,
+0xFF326CB5,
+0xFF326CB5,
+0xFF326CB5,
+0xFF326CB5,
+0xFF326CB5,
+0xFF326CB5,
+0xFF326CB5,
+0xFF326CB5,
+0xFF326CB5,
+0xFF326CB5,
+0xFF326CB5,
+0xFF326CB6,
+0xFF326CB6,
+0xFF326CB6,
+0xFF336DB7,
+0xFF336DB7,
+0xFF326CB6,
+0xFF326CB6,
+0xFF316BB5,
+0xFF326CB6,
+0xFF326CB6,
+0xFF326CB6,
+0xFF326CB6,
+0xFF326CB6,
+0xFF326CB6,
+0xFF326CB6,
+0xFF316BB5,
+0xFF316BB5,
+0xFF326CB6,
+0xFF326CB6,
+0xFF326CB6,
+0xFF316BB5,
+0xFF316BB5,
+0xFF316BB5,
+0xFF316BB5,
+0xFF316BB5,
+0xFF316BB5,
+0xFF316BB5,
+0xFF316BB5,
+0xFF316BB5,
+0xFF316BB5,
+0xFF326CB6,
+0xFF326CB6,
+0xFF316BB5,
+0xFF316BB5,
+0xFF316BB5,
+0xFF306AB4,
+0xFF306AB4,
+0xFF306AB4,
+0xFF3169B4,
+0xFF3169B4,
+0xFF326AB5,
+0xFF3169B4,
+0xFF3267B3,
+0xFF3267B3,
+0xFF3368B4,
+0xFF3368B4,
+0xFF3368B4,
+0xFF3267B3,
+0xFF3267B3,
+0xFF3068B3,
+0xFF3267B3,
+0xFF3368B4,
+0xFF3267B3,
+0xFF3267B3,
+0xFF3166B2,
+0xFF3166B2,
+0xFF3166B2,
+0xFF3166B2,
+0xFF3065B1,
+0xFF2F64B0,
+0xFF3064B0,
+0xFF3064B0,
+0xFF3165B1,
+0xFF3165B1,
+0xFF3064B0,
+0xFF3064B0,
+0xFF3064B0,
+0xFF3064B0,
+0xFF3064AF,
+0xFF2F63AE,
+0xFF3162AE,
+0xFF3162AE,
+0xFF3162AE,
+0xFF3162AE,
+0xFF3061AD,
+0xFF3061AD,
+0xFF2F60AC,
+0xFF2F60AC,
+0xFF2F60AC,
+0xFF2F60AC,
+0xFF3062AB,
+0xFF3062AB,
+0xFF3060AA,
+0xFF3060AA,
+0xFF3060AA,
+0xFF3060AA,
+0xFF2F5FA9,
+0xFF2F5FA9,
+0xFF2F5FA9,
+0xFF2E5EA8,
+0xFF2D5DA7,
+0xFF2D5DA7,
+0xFF2D5DA7,
+0xFF2D5DA7,
+0xFF2C5CA8,
+0xFF2C5CA8,
+0xFF2C5CA8,
+0xFF2B5BA7,
+0xFF2B5BA5,
+0xFF2B5BA5,
+0xFF2B59A4,
+0xFF2B59A4,
+0xFF2B5AA2,
+0xFF2B5AA2,
+0xFF2D59A2,
+0xFF2D59A2,
+0xFF2D59A0,
+0xFF2C589F,
+0xFF2C569E,
+0xFF2C569E,
+0xFF2C569E,
+0xFF2C569E,
+0xFF2A5196,
+0xFF2A5196,
+0xFF2B5297,
+0xFF2B5297,
+0xFF2C5398,
+0xFF2C5398,
+0xFF2B5297,
+0xFF2B5297,
+0xFF2C5398,
+0xFF2C5398,
+0xFF2D539A,
+0xFF2D539A,
+0xFF2D539A,
+0xFF2D539A,
+0xFF2E549B,
+0xFF2D559B,
+0xFF2C579C,
+0xFF2B589C,
+0xFF2C589F,
+0xFF2C589F,
+0xFF2D579F,
+0xFF2D579F,
+0xFF2D579F,
+0xFF2E58A0,
+0xFF2F59A1,
+0xFF2F59A1,
+0xFF2F59A3,
+0xFF2F59A3,
+0xFF2E5AA3,
+0xFF2E5AA3,
+0xFF2E5AA3,
+0xFF2E5AA3,
+0xFF2D5BA6,
+0xFF2D5BA6,
+0xFF2D5BA6,
+0xFF2E5CA7,
+0xFF2D5DA7,
+0xFF2D5DA7,
+0xFF2D5DA7,
+0xFF2D5DA7,
+0xFF2E5EA8,
+0xFF2E5EA8,
+0xFF2F5FA9,
+0xFF2F5FA9,
+0xFF2F5FA9,
+0xFF3060AA,
+0xFF3060AA,
+0xFF3060AA,
+0xFF2F5FA9,
+0xFF3060AA,
+0xFF3161AB,
+0xFF3161AB,
+0xFF3161AB,
+0xFF3161AB,
+0xFF3161AB,
+0xFF3161AB,
+0xFF3062AB,
+0xFF3062AB,
+0xFF3062AB,
+0xFF3062AB,
+0xFF3163AC,
+0xFF3163AC,
+0xFF3264AD,
+0xFF3264AD,
+0xFF3162AE,
+0xFF3162AE,
+0xFF3162AE,
+0xFF3263AF,
+0xFF3263AF,
+0xFF3263AF,
+0xFF3263AF,
+0xFF3364B0,
+0xFF3364B0,
+0xFF3364B0,
+0xFF3165B0,
+0xFF3165B0,
+0xFF3165B0,
+0xFF3266B1,
+0xFF3266B1,
+0xFF3266B1,
+0xFF3266B1,
+0xFF3266B1,
+0xFF3266B1,
+0xFF3266B1,
+0xFF3266B1,
+0xFF3367B2,
+0xFF3367B2,
+0xFF3367B2,
+0xFF3367B2,
+0xFF3367B2,
+0xFF3268B2,
+0xFF3268B2,
+0xFF3268B2,
+0xFF3268B2,
+0xFF3268B2,
+0xFF3268B2,
+0xFF3268B2,
+0xFF3268B2,
+0xFF3369B3,
+0xFF3369B3,
+0xFF3369B3,
+0xFF3369B3,
+0xFF3268B2,
+0xFF3268B2,
+0xFF3369B3,
+0xFF3369B3,
+0xFF3369B3,
+0xFF3369B3,
+0xFF3369B3,
+0xFF3369B3,
+0xFF3369B3,
+0xFF3369B3,
+0xFF3468B3,
+0xFF3468B3,
+0xFF3369B3,
+0xFF3369B3,
+0xFF3369B3,
+0xFF3369B3,
+0xFF3369B3,
+0xFF3369B3,
+0xFF3369B3,
+0xFF3369B3,
+0xFF3369B3,
+0xFF3369B3,
+0xFF3369B3,
+0xFF3369B3,
+0xFF3369B3,
+0xFF3369B3,
+0xFF3369B3,
+0xFF3369B3,
+0xFF346AB4,
+0xFF346AB4,
+0xFF346AB4,
+0xFF346AB4,
+0xFF346AB4,
+0xFF346AB4,
+0xFF3169B3,
+0xFF3169B3,
+0xFF3169B3,
+0xFF3169B3,
+0xFF326AB4,
+0xFF326AB4,
+0xFF326AB4,
+0xFF326AB4,
+0xFF326AB4,
+0xFF326AB4,
+0xFF326AB4,
+0xFF326AB4,
+0xFF326AB4,
+0xFF326AB4,
+0xFF326AB4,
+0xFF326AB4,
+0xFF326AB4,
+0xFF326AB4,
+0xFF326AB4,
+0xFF326AB4,
+0xFF326AB4,
+0xFF326AB4,
+0xFF326AB4,
+0xFF326AB4,
+0xFF326AB4,
+0xFF326AB4,
+0xFF326AB4,
+0xFF326AB4,
+0xFF326AB4,
+0xFF326AB4,
+0xFF326AB4,
+0xFF326AB4,
+0xFF316BB4,
+0xFF316BB4,
+0xFF316BB4,
+0xFF326CB5,
+0xFF326CB5,
+0xFF316BB4,
+0xFF316BB4,
+0xFF316BB4,
+0xFF326AB5,
+0xFF326AB5,
+0xFF326AB5,
+0xFF326AB5,
+0xFF326AB5,
+0xFF326AB5,
+0xFF326AB5,
+0xFF326AB5,
+0xFF326AB5,
+0xFF326AB5,
+0xFF326AB5,
+0xFF336BB6,
+0xFF336BB6,
+0xFF336BB6,
+0xFF326AB5,
+0xFF326AB5,
+0xFF326CB5,
+0xFF326CB5,
+0xFF326CB5,
+0xFF326CB5,
+0xFF326CB5,
+0xFF326CB5,
+0xFF326CB5,
+0xFF326CB5,
+0xFF326CB5,
+0xFF326CB5,
+0xFF316BB4,
+0xFF316BB4,
+0xFF326CB5,
+0xFF326CB5,
+0xFF326CB5,
+0xFF326CB5,
+0xFF326CB6,
+0xFF326CB6,
+0xFF326CB6,
+0xFF336DB7,
+0xFF326CB6,
+0xFF326CB6,
+0xFF326CB6,
+0xFF326CB6,
+0xFF326CB6,
+0xFF326CB6,
+0xFF326CB6,
+0xFF326CB6,
+0xFF326CB6,
+0xFF326CB6,
+0xFF326CB6,
+0xFF326CB6,
+0xFF326CB6,
+0xFF326CB6,
+0xFF326CB6,
+0xFF326CB6,
+0xFF326CB6,
+0xFF316BB5,
+0xFF316BB5,
+0xFF326CB6,
+0xFF316BB5,
+0xFF316BB5,
+0xFF316BB5,
+0xFF316BB5,
+0xFF316BB5,
+0xFF316BB5,
+0xFF316BB5,
+0xFF316BB5,
+0xFF316BB5,
+0xFF316BB5,
+0xFF316BB5,
+0xFF316BB5,
+0xFF316BB5,
+0xFF316BB5,
+0xFF326AB5,
+0xFF326AB5,
+0xFF326AB5,
+0xFF326AB5,
+0xFF3368B4,
+0xFF3368B4,
+0xFF3368B4,
+0xFF3368B4,
+0xFF3368B4,
+0xFF3368B4,
+0xFF3068B3,
+0xFF3068B3,
+0xFF3169B4,
+0xFF3169B4,
+0xFF3267B3,
+0xFF3267B3,
+0xFF3267B3,
+0xFF3166B2,
+0xFF3267B3,
+0xFF3267B3,
+0xFF3166B2,
+0xFF3065B1,
+0xFF3165B1,
+0xFF3165B1,
+0xFF3165B1,
+0xFF3165B1,
+0xFF3064B0,
+0xFF3064B0,
+0xFF3064B0,
+0xFF3064B0,
+0xFF3064AF,
+0xFF3064AF,
+0xFF3263AF,
+0xFF3162AE,
+0xFF3263AF,
+0xFF3162AE,
+0xFF3162AE,
+0xFF3061AD,
+0xFF3061AD,
+0xFF3061AD,
+0xFF3061AD,
+0xFF3061AD,
+0xFF3062AB,
+0xFF3062AB,
+0xFF3060AA,
+0xFF3060AA,
+0xFF3060AA,
+0xFF3060AA,
+0xFF2F5FA9,
+0xFF2F5FA9,
+0xFF3060AA,
+0xFF2F5FA9,
+0xFF2E5EA8,
+0xFF2D5DA7,
+0xFF2D5DA7,
+0xFF2D5DA7,
+0xFF2D5DA9,
+0xFF2C5CA8,
+0xFF2D5DA9,
+0xFF2C5CA8,
+0xFF2C5CA6,
+0xFF2C5CA6,
+0xFF2C5AA5,
+0xFF2C5AA5,
+0xFF2C5BA3,
+0xFF2C5BA3,
+0xFF2D59A2,
+0xFF2D59A2,
+0xFF2D59A0,
+0xFF2D59A0,
+0xFF2D579F,
+0xFF2C569E,
+0xFF2D579F,
+0xFF2D579F,
+0xFF2B5297,
+0xFF2C5398,
+0xFF2C5398,
+0xFF2C5398,
+0xFF2C5398,
+0xFF2C5398,
+0xFF2B5398,
+0xFF2A5297,
+0xFF2B5399,
+0xFF2C549A,
+0xFF2C549A,
+0xFF2D559B,
+0xFF2D559B,
+0xFF2D559B,
+0xFF2E569C,
+0xFF2E569C,
+0xFF2C569E,
+0xFF2C589F,
+0xFF2E58A0,
+0xFF2E58A0,
+0xFF2E58A0,
+0xFF2E58A0,
+0xFF2E58A0,
+0xFF2F59A1,
+0xFF2F59A1,
+0xFF2F59A1,
+0xFF2E5AA3,
+0xFF2E5AA3,
+0xFF2F5BA4,
+0xFF2F5BA4,
+0xFF2D5CA4,
+0xFF2D5CA4,
+0xFF2D5CA4,
+0xFF2D5CA4,
+0xFF2E5DA5,
+0xFF2E5DA5,
+0xFF2F5DA8,
+0xFF2F5DA8,
+0xFF2E5EA8,
+0xFF2E5EA8,
+0xFF2F5FA9,
+0xFF2F5FA9,
+0xFF2F5FA9,
+0xFF2F5FA9,
+0xFF3060AA,
+0xFF3060AA,
+0xFF3060AA,
+0xFF3060AA,
+0xFF3060AA,
+0xFF3060AA,
+0xFF3161AB,
+0xFF3161AB,
+0xFF3161AB,
+0xFF3262AC,
+0xFF3262AC,
+0xFF3262AC,
+0xFF3062AB,
+0xFF3062AB,
+0xFF3163AC,
+0xFF3163AC,
+0xFF3163AC,
+0xFF3264AD,
+0xFF3264AD,
+0xFF3365AE,
+0xFF3263AF,
+0xFF3263AF,
+0xFF3263AF,
+0xFF3263AF,
+0xFF3364B0,
+0xFF3364B0,
+0xFF3165B0,
+0xFF3165B0,
+0xFF3266B1,
+0xFF3266B1,
+0xFF3266B1,
+0xFF3266B1,
+0xFF3266B1,
+0xFF3266B1,
+0xFF3266B1,
+0xFF3367B2,
+0xFF3367B2,
+0xFF3367B2,
+0xFF3367B2,
+0xFF3367B2,
+0xFF3367B2,
+0xFF3367B2,
+0xFF3369B3,
+0xFF3369B3,
+0xFF3268B2,
+0xFF3268B2,
+0xFF3268B2,
+0xFF3268B2,
+0xFF3369B3,
+0xFF3369B3,
+0xFF3369B3,
+0xFF3369B3,
+0xFF3369B3,
+0xFF3369B3,
+0xFF3369B3,
+0xFF3369B3,
+0xFF3369B3,
+0xFF3369B3,
+0xFF3369B3,
+0xFF3369B3,
+0xFF346AB4,
+0xFF346AB4,
+0xFF346AB4,
+0xFF346AB4,
+0xFF346AB4,
+0xFF346AB4,
+0xFF346AB4,
+0xFF346AB4,
+0xFF346AB4,
+0xFF346AB4,
+0xFF346AB4,
+0xFF346AB4,
+0xFF346AB4,
+0xFF346AB4,
+0xFF346AB4,
+0xFF346AB4,
+0xFF346AB4,
+0xFF346AB4,
+0xFF326AB4,
+0xFF326AB4,
+0xFF326AB4,
+0xFF326AB4,
+0xFF326AB4,
+0xFF326AB4,
+0xFF326AB4,
+0xFF326AB4,
+0xFF326AB4,
+0xFF326AB4,
+0xFF326AB4,
+0xFF326AB4,
+0xFF326AB4,
+0xFF326AB4,
+0xFF326AB4,
+0xFF326AB4,
+0xFF3169B3,
+0xFF326AB4,
+0xFF326AB4,
+0xFF326AB4,
+0xFF326AB4,
+0xFF326AB4,
+0xFF326AB4,
+0xFF326AB4,
+0xFF326AB4,
+0xFF336BB5,
+0xFF336BB5,
+0xFF326AB4,
+0xFF326AB4,
+0xFF326AB4,
+0xFF336BB5,
+0xFF336BB5,
+0xFF326AB4,
+0xFF326AB4,
+0xFF326AB4,
+0xFF326AB4,
+0xFF336BB5,
+0xFF336BB5,
+0xFF336BB5,
+0xFF336BB5,
+0xFF336BB5,
+0xFF336BB5,
+0xFF326CB5,
+0xFF326CB5,
+0xFF326CB5,
+0xFF326CB5,
+0xFF326CB5,
+0xFF326CB5,
+0xFF326CB5,
+0xFF326CB5,
+0xFF326CB5,
+0xFF326CB5,
+0xFF316DB5,
+0xFF316DB5,
+0xFF326CB6,
+0xFF326CB6,
+0xFF326CB6,
+0xFF326CB6,
+0xFF326CB6,
+0xFF326CB6,
+0xFF326CB6,
+0xFF326CB6,
+0xFF326CB6,
+0xFF326CB6,
+0xFF326CB6,
+0xFF326CB6,
+0xFF326CB6,
+0xFF326CB6,
+0xFF326CB6,
+0xFF326CB6,
+0xFF336DB6,
+0xFF336DB6,
+0xFF336DB6,
+0xFF336DB6,
+0xFF326CB5,
+0xFF326CB5,
+0xFF326CB5,
+0xFF326CB5,
+0xFF316DB5,
+0xFF316DB5,
+0xFF316DB5,
+0xFF316DB5,
+0xFF316DB5,
+0xFF316DB5,
+0xFF316DB5,
+0xFF326EB6,
+0xFF316DB5,
+0xFF316DB5,
+0xFF316DB5,
+0xFF316DB5,
+0xFF316DB6,
+0xFF316DB6,
+0xFF316DB6,
+0xFF316DB6,
+0xFF326EB7,
+0xFF326EB7,
+0xFF326EB7,
+0xFF316DB6,
+0xFF316DB6,
+0xFF316DB6,
+0xFF316DB6,
+0xFF326EB7,
+0xFF326CB6,
+0xFF336DB7,
+0xFF336DB7,
+0xFF336DB7,
+0xFF326CB6,
+0xFF326CB6,
+0xFF326CB6,
+0xFF326CB6,
+0xFF326CB6,
+0xFF326CB6,
+0xFF326CB6,
+0xFF326CB6,
+0xFF326CB6,
+0xFF326CB6,
+0xFF326CB6,
+0xFF316BB5,
+0xFF326CB6,
+0xFF326CB6,
+0xFF326CB6,
+0xFF326CB6,
+0xFF326CB6,
+0xFF326CB6,
+0xFF326CB6,
+0xFF326CB6,
+0xFF326AB5,
+0xFF326AB5,
+0xFF336BB6,
+0xFF326AB5,
+0xFF3169B4,
+0xFF3169B4,
+0xFF3368B4,
+0xFF3469B5,
+0xFF3169B4,
+0xFF3169B4,
+0xFF3169B4,
+0xFF3169B4,
+0xFF3169B4,
+0xFF3068B3,
+0xFF3267B3,
+0xFF3267B3,
+0xFF3368B4,
+0xFF3368B4,
+0xFF3267B3,
+0xFF3267B3,
+0xFF3166B2,
+0xFF3166B2,
+0xFF3065B1,
+0xFF3065B1,
+0xFF3165B1,
+0xFF3165B1,
+0xFF3165B1,
+0xFF3165B1,
+0xFF3165B0,
+0xFF3165B0,
+0xFF3064AF,
+0xFF3064AF,
+0xFF3263AF,
+0xFF3263AF,
+0xFF3263AF,
+0xFF3162AE,
+0xFF3162AE,
+0xFF3162AE,
+0xFF3162AE,
+0xFF3162AE,
+0xFF3163AC,
+0xFF3062AB,
+0xFF3062AB,
+0xFF2F61AA,
+0xFF2F61AA,
+0xFF2F61AA,
+0xFF3060AA,
+0xFF2F5FA9,
+0xFF3060AA,
+0xFF2F5FA9,
+0xFF2F5FA9,
+0xFF2E5EA8,
+0xFF2E5EA8,
+0xFF2E5EA8,
+0xFF2E5EA8,
+0xFF2D5DA7,
+0xFF2E5EAA,
+0xFF2D5DA9,
+0xFF2D5DA7,
+0xFF2D5DA7,
+0xFF2C5CA6,
+0xFF2C5CA6,
+0xFF2D5CA4,
+0xFF2D5CA4,
+0xFF2C5BA3,
+0xFF2C5BA3,
+0xFF2E5AA1,
+0xFF2E5AA1,
+0xFF2D59A0,
+0xFF2C589F,
+0xFF2C589F,
+0xFF2C589F,
+0xFF2C5398,
+0xFF2C5398,
+0xFF2C5398,
+0xFF2C5398,
+0xFF2C5398,
+0xFF2C5398,
+0xFF2B5398,
+0xFF2B5398,
+0xFF2C549A,
+0xFF2C549A,
+0xFF2D559B,
+0xFF2D559B,
+0xFF2D559B,
+0xFF2E569C,
+0xFF2E569C,
+0xFF2D589D,
+0xFF2D579F,
+0xFF2C589F,
+0xFF2E58A0,
+0xFF2E58A0,
+0xFF2E58A0,
+0xFF2E58A0,
+0xFF2F59A1,
+0xFF2F59A1,
+0xFF305AA2,
+0xFF305AA2,
+0xFF2F5BA4,
+0xFF2F5BA4,
+0xFF2F5BA4,
+0xFF2F5BA4,
+0xFF2E5DA5,
+0xFF2E5DA5,
+0xFF2E5DA5,
+0xFF2E5DA5,
+0xFF2E5DA5,
+0xFF2F5EA6,
+0xFF2F5DA8,
+0xFF305EA9,
+0xFF2F5FA9,
+0xFF2F5FA9,
+0xFF3060AA,
+0xFF3060AA,
+0xFF3060AA,
+0xFF3060AA,
+0xFF3060AA,
+0xFF3060AA,
+0xFF3161AB,
+0xFF3161AB,
+0xFF3060AA,
+0xFF3161AB,
+0xFF3262AC,
+0xFF3262AC,
+0xFF3262AC,
+0xFF3262AC,
+0xFF3262AC,
+0xFF3363AD,
+0xFF3163AC,
+0xFF3163AC,
+0xFF3163AC,
+0xFF3264AD,
+0xFF3264AD,
+0xFF3264AD,
+0xFF3365AE,
+0xFF3365AE,
+0xFF3263AF,
+0xFF3364B0,
+0xFF3364B0,
+0xFF3364B0,
+0xFF3364B0,
+0xFF3364B0,
+0xFF3266B1,
+0xFF3266B1,
+0xFF3266B1,
+0xFF3266B1,
+0xFF3266B1,
+0xFF3266B1,
+0xFF3367B2,
+0xFF3367B2,
+0xFF3367B2,
+0xFF3367B2,
+0xFF3367B2,
+0xFF3367B2,
+0xFF3367B2,
+0xFF3468B3,
+0xFF3468B3,
+0xFF3468B3,
+0xFF3369B3,
+0xFF3369B3,
+0xFF3369B3,
+0xFF3369B3,
+0xFF3369B3,
+0xFF3369B3,
+0xFF3369B3,
+0xFF3369B3,
+0xFF3369B3,
+0xFF3369B3,
+0xFF346AB4,
+0xFF346AB4,
+0xFF3369B3,
+0xFF3369B3,
+0xFF3369B3,
+0xFF3369B3,
+0xFF346AB4,
+0xFF346AB4,
+0xFF346AB4,
+0xFF346AB4,
+0xFF346AB4,
+0xFF346AB4,
+0xFF346AB4,
+0xFF346AB4,
+0xFF356BB5,
+0xFF356BB5,
+0xFF346AB4,
+0xFF346AB4,
+0xFF346AB4,
+0xFF346AB4,
+0xFF346AB4,
+0xFF346AB4,
+0xFF346AB4,
+0xFF346AB4,
+0xFF346AB4,
+0xFF346AB4,
+0xFF326AB4,
+0xFF326AB4,
+0xFF326AB4,
+0xFF326AB4,
+0xFF326AB4,
+0xFF326AB4,
+0xFF326AB4,
+0xFF336BB5,
+0xFF336BB5,
+0xFF336BB5,
+0xFF336BB5,
+0xFF336BB5,
+0xFF336BB5,
+0xFF336BB5,
+0xFF336BB5,
+0xFF326AB4,
+0xFF326AB4,
+0xFF326AB4,
+0xFF336BB5,
+0xFF336BB5,
+0xFF336BB5,
+0xFF326AB4,
+0xFF326AB4,
+0xFF336BB5,
+0xFF336BB5,
+0xFF336BB5,
+0xFF336BB5,
+0xFF336BB5,
+0xFF336BB5,
+0xFF326AB4,
+0xFF336BB5,
+0xFF336BB5,
+0xFF336BB5,
+0xFF336BB5,
+0xFF336BB5,
+0xFF336BB5,
+0xFF336BB5,
+0xFF336BB5,
+0xFF336BB5,
+0xFF336BB5,
+0xFF336BB5,
+0xFF336BB5,
+0xFF326CB5,
+0xFF326CB5,
+0xFF326CB5,
+0xFF326CB5,
+0xFF326CB5,
+0xFF326CB5,
+0xFF326CB5,
+0xFF326CB5,
+0xFF326CB5,
+0xFF326CB5,
+0xFF316DB5,
+0xFF316DB5,
+0xFF326CB6,
+0xFF326CB6,
+0xFF326CB6,
+0xFF326CB6,
+0xFF326CB6,
+0xFF326CB6,
+0xFF326CB6,
+0xFF326CB6,
+0xFF326CB6,
+0xFF336DB7,
+0xFF336DB7,
+0xFF336DB7,
+0xFF336DB7,
+0xFF336DB7,
+0xFF336DB7,
+0xFF336DB7,
+0xFF336DB6,
+0xFF336DB6,
+0xFF336DB6,
+0xFF336DB6,
+0xFF336DB6,
+0xFF326CB5,
+0xFF326CB5,
+0xFF326CB5,
+0xFF326EB6,
+0xFF326EB6,
+0xFF326EB6,
+0xFF326EB6,
+0xFF326EB6,
+0xFF326EB6,
+0xFF326EB6,
+0xFF326EB6,
+0xFF316DB5,
+0xFF316DB5,
+0xFF316DB5,
+0xFF326EB6,
+0xFF316DB6,
+0xFF316DB6,
+0xFF316DB6,
+0xFF316DB6,
+0xFF326EB7,
+0xFF326EB7,
+0xFF326EB7,
+0xFF316DB6,
+0xFF316DB6,
+0xFF316DB6,
+0xFF326EB7,
+0xFF326EB7,
+0xFF326CB6,
+0xFF336DB7,
+0xFF336DB7,
+0xFF336DB7,
+0xFF336DB7,
+0xFF326CB6,
+0xFF326CB6,
+0xFF336DB7,
+0xFF336DB7,
+0xFF336DB7,
+0xFF336DB7,
+0xFF326CB6,
+0xFF326CB6,
+0xFF326CB6,
+0xFF326CB6,
+0xFF326CB6,
+0xFF326CB6,
+0xFF326CB6,
+0xFF326CB6,
+0xFF326CB6,
+0xFF326CB6,
+0xFF326CB6,
+0xFF326CB6,
+0xFF326CB6,
+0xFF336BB6,
+0xFF336BB6,
+0xFF336BB6,
+0xFF336BB6,
+0xFF326AB5,
+0xFF326AB5,
+0xFF3469B5,
+0xFF356AB6,
+0xFF326AB5,
+0xFF326AB5,
+0xFF3169B4,
+0xFF3169B4,
+0xFF3169B4,
+0xFF3169B4,
+0xFF3368B4,
+0xFF3368B4,
+0xFF3368B4,
+0xFF3368B4,
+0xFF3368B4,
+0xFF3368B4,
+0xFF3267B3,
+0xFF3267B3,
+0xFF3166B2,
+0xFF3166B2,
+0xFF3266B2,
+0xFF3266B2,
+0xFF3266B2,
+0xFF3266B2,
+0xFF3165B0,
+0xFF3165B0,
+0xFF3165B0,
+0xFF3165B0,
+0xFF3263AF,
+0xFF3263AF,
+0xFF3263AF,
+0xFF3263AF,
+0xFF3263AF,
+0xFF3162AE,
+0xFF3162AE,
+0xFF3162AE,
+0xFF3163AC,
+0xFF3163AC,
+0xFF3062AB,
+0xFF3062AB,
+0xFF3062AB,
+0xFF3062AB,
+0xFF3060AA,
+0xFF3060AA,
+0xFF3161AB,
+0xFF3060AA,
+0xFF2F5FA9,
+0xFF2F5FA9,
+0xFF2F5FA9,
+0xFF2F5FA9,
+0xFF2E5EA8,
+0xFF2E5EA8,
+0xFF2E5EAA,
+0xFF2D5DA9,
+0xFF2D5DA7,
+0xFF2D5DA7,
+0xFF2C5CA6,
+0xFF2C5CA6,
+0xFF2D5CA4,
+0xFF2D5CA4,
+0xFF2D5CA4,
+0xFF2D5CA4,
+0xFF2E5AA1,
+0xFF2E5AA1,
+0xFF2D59A0,
+0xFF2D59A0,
+0xFF2D59A0,
+0xFF2D59A0,
+0xFF2C5398,
+0xFF2C5398,
+0xFF2C5398,
+0xFF2C5398,
+0xFF2C5398,
+0xFF2D5499,
+0xFF2C5499,
+0xFF2C5499,
+0xFF2C549A,
+0xFF2D559B,
+0xFF2E569C,
+0xFF2E569C,
+0xFF2C579C,
+0xFF2D589D,
+0xFF2D589D,
+0xFF2E599E,
+0xFF2D579F,
+0xFF2E58A0,
+0xFF2E58A0,
+0xFF2F59A1,
+0xFF2F59A1,
+0xFF2F59A1,
+0xFF2F59A1,
+0xFF2F59A1,
+0xFF305AA2,
+0xFF305AA2,
+0xFF2F5BA4,
+0xFF2F5BA4,
+0xFF2F5BA4,
+0xFF305CA5,
+0xFF2E5DA5,
+0xFF2E5DA5,
+0xFF2F5EA6,
+0xFF2F5EA6,
+0xFF2F5EA6,
+0xFF305FA7,
+0xFF305FA7,
+0xFF3160A8,
+0xFF3160A8,
+0xFF3160A8,
+0xFF3160A8,
+0xFF3160A8,
+0xFF3161A9,
+0xFF3161A9,
+0xFF3161AB,
+0xFF3161AB,
+0xFF3161AB,
+0xFF3161AB,
+0xFF3161AB,
+0xFF3161AB,
+0xFF3262AC,
+0xFF3262AC,
+0xFF3163AC,
+0xFF3163AC,
+0xFF3163AC,
+0xFF3163AC,
+0xFF3264AD,
+0xFF3264AD,
+0xFF3264AD,
+0xFF3264AD,
+0xFF3264AD,
+0xFF3365AE,
+0xFF3165AE,
+0xFF3165AE,
+0xFF3165B0,
+0xFF3165B0,
+0xFF3165B0,
+0xFF3266B1,
+0xFF3266B1,
+0xFF3266B1,
+0xFF3266B1,
+0xFF3367B2,
+0xFF3367B2,
+0xFF3367B2,
+0xFF3367B2,
+0xFF3367B2,
+0xFF3367B2,
+0xFF3367B2,
+0xFF3367B2,
+0xFF3367B2,
+0xFF3369B3,
+0xFF3369B3,
+0xFF3369B3,
+0xFF3369B3,
+0xFF3369B3,
+0xFF3369B3,
+0xFF3369B3,
+0xFF3369B3,
+0xFF3369B3,
+0xFF3369B3,
+0xFF3369B3,
+0xFF3369B3,
+0xFF346AB4,
+0xFF346AB4,
+0xFF346AB4,
+0xFF346AB4,
+0xFF326AB4,
+0xFF326AB4,
+0xFF326AB4,
+0xFF326AB4,
+0xFF326AB4,
+0xFF326AB4,
+0xFF326AB4,
+0xFF326AB4,
+0xFF326AB4,
+0xFF326AB4,
+0xFF326AB4,
+0xFF326AB4,
+0xFF326AB4,
+0xFF326AB4,
+0xFF336BB5,
+0xFF336BB5,
+0xFF326AB4,
+0xFF326AB4,
+0xFF326AB4,
+0xFF326AB4,
+0xFF326AB4,
+0xFF326AB4,
+0xFF326AB4,
+0xFF326AB4,
+0xFF326AB4,
+0xFF326AB4,
+0xFF326AB4,
+0xFF326AB4,
+0xFF326AB4,
+0xFF326AB4,
+0xFF316BB4,
+0xFF316BB4,
+0xFF336BB5,
+0xFF336BB5,
+0xFF336BB5,
+0xFF336BB5,
+0xFF336BB5,
+0xFF336BB5,
+0xFF326CB5,
+0xFF326CB5,
+0xFF326CB5,
+0xFF326CB5,
+0xFF326CB5,
+0xFF326CB5,
+0xFF326CB5,
+0xFF326CB5,
+0xFF326CB5,
+0xFF326CB5,
+0xFF326CB5,
+0xFF326CB5,
+0xFF326CB5,
+0xFF336DB6,
+0xFF336DB6,
+0xFF326CB5,
+0xFF326CB5,
+0xFF326CB5,
+0xFF326CB5,
+0xFF326CB5,
+0xFF326CB5,
+0xFF326CB5,
+0xFF326CB5,
+0xFF326CB5,
+0xFF326CB5,
+0xFF336DB6,
+0xFF326CB5,
+0xFF326CB5,
+0xFF326CB5,
+0xFF326CB5,
+0xFF326CB5,
+0xFF326CB5,
+0xFF326CB5,
+0xFF336DB6,
+0xFF316DB5,
+0xFF316DB5,
+0xFF326EB6,
+0xFF326EB6,
+0xFF326EB6,
+0xFF326EB6,
+0xFF316DB5,
+0xFF316DB5,
+0xFF326EB6,
+0xFF326EB6,
+0xFF326EB6,
+0xFF326EB6,
+0xFF326EB6,
+0xFF326EB6,
+0xFF316DB5,
+0xFF316DB5,
+0xFF316DB5,
+0xFF326EB6,
+0xFF326EB6,
+0xFF326EB6,
+0xFF326EB6,
+0xFF326EB6,
+0xFF326EB6,
+0xFF326EB6,
+0xFF326EB6,
+0xFF326EB6,
+0xFF326EB6,
+0xFF326EB6,
+0xFF326EB6,
+0xFF326EB6,
+0xFF316DB5,
+0xFF316DB5,
+0xFF326EB6,
+0xFF326EB6,
+0xFF326EB6,
+0xFF326EB6,
+0xFF326EB6,
+0xFF326EB6,
+0xFF326EB6,
+0xFF326EB6,
+0xFF326EB6,
+0xFF326EB6,
+0xFF326EB6,
+0xFF326EB6,
+0xFF326EB6,
+0xFF326EB6,
+0xFF326EB6,
+0xFF326EB6,
+0xFF326EB6,
+0xFF326EB6,
+0xFF326EB6,
+0xFF316DB5,
+0xFF316DB6,
+0xFF316DB6,
+0xFF326EB7,
+0xFF326EB7,
+0xFF316DB6,
+0xFF326EB7,
+0xFF326EB7,
+0xFF326EB7,
+0xFF326EB7,
+0xFF316DB6,
+0xFF326EB7,
+0xFF326EB7,
+0xFF326EB7,
+0xFF326EB7,
+0xFF326EB7,
+0xFF326EB7,
+0xFF326EB7,
+0xFF316DB6,
+0xFF316DB6,
+0xFF316DB6,
+0xFF316DB6,
+0xFF316DB6,
+0xFF316DB6,
+0xFF316DB6,
+0xFF316DB6,
+0xFF316DB6,
+0xFF326CB6,
+0xFF326CB6,
+0xFF336DB7,
+0xFF326CB6,
+0xFF326CB6,
+0xFF326CB6,
+0xFF336BB6,
+0xFF336BB6,
+0xFF336BB6,
+0xFF336BB6,
+0xFF326AB5,
+0xFF326AB5,
+0xFF326AB5,
+0xFF326AB5,
+0xFF326AB5,
+0xFF3169B4,
+0xFF3169B4,
+0xFF3169B4,
+0xFF3068B3,
+0xFF3169B4,
+0xFF3368B4,
+0xFF3368B4,
+0xFF3368B4,
+0xFF3267B3,
+0xFF3267B3,
+0xFF3267B3,
+0xFF3166B2,
+0xFF3166B2,
+0xFF3166B2,
+0xFF3166B2,
+0xFF3266B1,
+0xFF3165B0,
+0xFF3165B0,
+0xFF3165B0,
+0xFF3165B0,
+0xFF3165B0,
+0xFF3165B0,
+0xFF3165B0,
+0xFF3263AF,
+0xFF3263AF,
+0xFF3263AF,
+0xFF3162AE,
+0xFF3263AF,
+0xFF3162AE,
+0xFF3162AE,
+0xFF3061AD,
+0xFF3162AE,
+0xFF3061AD,
+0xFF3062AB,
+0xFF2F61AA,
+0xFF3062AB,
+0xFF3062AB,
+0xFF3060AA,
+0xFF3060AA,
+0xFF3060AA,
+0xFF3060AA,
+0xFF2F5FA9,
+0xFF2F5FA9,
+0xFF2E5EA8,
+0xFF2E5EA8,
+0xFF2D5DA7,
+0xFF2D5DA7,
+0xFF2D5DA7,
+0xFF2C5CA6,
+0xFF2D5BA6,
+0xFF2D5BA6,
+0xFF2D5CA4,
+0xFF2D5CA4,
+0xFF2C5BA3,
+0xFF2C5BA3,
+0xFF2E5AA1,
+0xFF2D59A0,
+0xFF2D59A0,
+0xFF2D59A0,
+0xFF2C5398,
+0xFF2C5398,
+0xFF2C5398,
+0xFF2C5398,
+0xFF2D5499,
+0xFF2D5499,
+0xFF2D559A,
+0xFF2D559A,
+0xFF2D559B,
+0xFF2E569C,
+0xFF2E569C,
+0xFF2F579D,
+0xFF2D589D,
+0xFF2D589D,
+0xFF2E599E,
+0xFF2F5A9F,
+0xFF2E58A0,
+0xFF2E58A0,
+0xFF2F59A1,
+0xFF2F59A1,
+0xFF2F59A1,
+0xFF2F59A1,
+0xFF2F59A1,
+0xFF305AA2,
+0xFF305AA2,
+0xFF305AA2,
+0xFF2F5BA4,
+0xFF2F5BA4,
+0xFF305CA5,
+0xFF305CA5,
+0xFF2F5EA6,
+0xFF2F5EA6,
+0xFF305FA7,
+0xFF305FA7,
+0xFF305FA7,
+0xFF305FA7,
+0xFF3160A8,
+0xFF3160A8,
+0xFF3261A9,
+0xFF3261A9,
+0xFF3261A9,
+0xFF3261A9,
+0xFF3161A9,
+0xFF3161A9,
+0xFF3262AC,
+0xFF3262AC,
+0xFF3262AC,
+0xFF3262AC,
+0xFF3161AB,
+0xFF3262AC,
+0xFF3262AC,
+0xFF3363AD,
+0xFF3163AC,
+0xFF3163AC,
+0xFF3163AC,
+0xFF3264AD,
+0xFF3365AE,
+0xFF3365AE,
+0xFF3365AE,
+0xFF3365AE,
+0xFF3365AE,
+0xFF3365AE,
+0xFF3165AE,
+0xFF3266AF,
+0xFF3266B1,
+0xFF3266B1,
+0xFF3266B1,
+0xFF3266B1,
+0xFF3367B2,
+0xFF3367B2,
+0xFF3367B2,
+0xFF3367B2,
+0xFF3367B2,
+0xFF3367B2,
+0xFF3367B2,
+0xFF3367B2,
+0xFF3468B3,
+0xFF3468B3,
+0xFF3468B3,
+0xFF3468B3,
+0xFF3369B3,
+0xFF3369B3,
+0xFF3369B3,
+0xFF3369B3,
+0xFF3369B3,
+0xFF3369B3,
+0xFF346AB4,
+0xFF346AB4,
+0xFF346AB4,
+0xFF346AB4,
+0xFF346AB4,
+0xFF346AB4,
+0xFF346AB4,
+0xFF346AB4,
+0xFF346AB4,
+0xFF346AB4,
+0xFF336BB5,
+0xFF336BB5,
+0xFF336BB5,
+0xFF336BB5,
+0xFF336BB5,
+0xFF336BB5,
+0xFF336BB5,
+0xFF336BB5,
+0xFF336BB5,
+0xFF336BB5,
+0xFF336BB5,
+0xFF336BB5,
+0xFF336BB5,
+0xFF336BB5,
+0xFF336BB5,
+0xFF336BB5,
+0xFF326AB4,
+0xFF326AB4,
+0xFF326AB4,
+0xFF336BB5,
+0xFF336BB5,
+0xFF336BB5,
+0xFF336BB5,
+0xFF336BB5,
+0xFF326AB4,
+0xFF326AB4,
+0xFF326AB4,
+0xFF336BB5,
+0xFF336BB5,
+0xFF336BB5,
+0xFF326CB5,
+0xFF326CB5,
+0xFF336BB5,
+0xFF336BB5,
+0xFF336BB5,
+0xFF336BB5,
+0xFF336BB5,
+0xFF336BB5,
+0xFF326CB5,
+0xFF326CB5,
+0xFF336DB6,
+0xFF326CB5,
+0xFF326CB5,
+0xFF326CB5,
+0xFF336DB6,
+0xFF336DB6,
+0xFF336DB6,
+0xFF326CB5,
+0xFF336DB6,
+0xFF336DB6,
+0xFF336DB6,
+0xFF336DB6,
+0xFF336DB6,
+0xFF336DB6,
+0xFF336DB6,
+0xFF336DB6,
+0xFF326CB5,
+0xFF326CB5,
+0xFF326CB5,
+0xFF326CB5,
+0xFF326CB5,
+0xFF336DB6,
+0xFF336DB6,
+0xFF336DB6,
+0xFF326CB5,
+0xFF326CB5,
+0xFF326CB5,
+0xFF336DB6,
+0xFF336DB6,
+0xFF336DB6,
+0xFF336DB6,
+0xFF336DB6,
+0xFF326EB6,
+0xFF326EB6,
+0xFF326EB6,
+0xFF326EB6,
+0xFF326EB6,
+0xFF326EB6,
+0xFF326EB6,
+0xFF326EB6,
+0xFF316DB5,
+0xFF316DB5,
+0xFF316DB5,
+0xFF316DB5,
+0xFF316DB5,
+0xFF316DB5,
+0xFF316DB5,
+0xFF316DB5,
+0xFF316DB5,
+0xFF316DB5,
+0xFF316DB5,
+0xFF326EB6,
+0xFF326EB6,
+0xFF326EB6,
+0xFF326EB6,
+0xFF316DB5,
+0xFF326EB6,
+0xFF326EB6,
+0xFF326EB6,
+0xFF326EB6,
+0xFF326EB6,
+0xFF326EB6,
+0xFF326EB6,
+0xFF326EB6,
+0xFF326EB6,
+0xFF326EB6,
+0xFF326EB6,
+0xFF326EB6,
+0xFF326EB6,
+0xFF326EB6,
+0xFF326EB6,
+0xFF326EB6,
+0xFF336FB7,
+0xFF336FB7,
+0xFF326EB6,
+0xFF326EB6,
+0xFF326EB6,
+0xFF336FB7,
+0xFF336FB7,
+0xFF336FB7,
+0xFF336FB7,
+0xFF326EB6,
+0xFF326EB6,
+0xFF326EB6,
+0xFF326EB7,
+0xFF326EB7,
+0xFF326EB7,
+0xFF326EB7,
+0xFF326EB7,
+0xFF326EB7,
+0xFF336FB8,
+0xFF326EB7,
+0xFF326EB7,
+0xFF326EB7,
+0xFF326EB7,
+0xFF326EB7,
+0xFF336FB8,
+0xFF326EB7,
+0xFF326EB7,
+0xFF326EB7,
+0xFF326EB7,
+0xFF326EB7,
+0xFF326EB7,
+0xFF326EB7,
+0xFF316DB6,
+0xFF316DB6,
+0xFF316DB6,
+0xFF316DB6,
+0xFF316DB6,
+0xFF316DB6,
+0xFF326CB6,
+0xFF326CB6,
+0xFF346EB8,
+0xFF336DB7,
+0xFF326CB6,
+0xFF326CB6,
+0xFF346CB7,
+0xFF346CB7,
+0xFF336BB6,
+0xFF336BB6,
+0xFF336BB6,
+0xFF336BB6,
+0xFF336BB6,
+0xFF326AB5,
+0xFF326AB5,
+0xFF326AB5,
+0xFF326AB5,
+0xFF326AB5,
+0xFF3169B4,
+0xFF3169B4,
+0xFF3368B4,
+0xFF3368B4,
+0xFF3368B4,
+0xFF3368B4,
+0xFF3368B4,
+0xFF3267B3,
+0xFF3267B3,
+0xFF3267B3,
+0xFF3267B3,
+0xFF3166B2,
+0xFF3266B1,
+0xFF3266B1,
+0xFF3165B0,
+0xFF3165B0,
+0xFF3165B0,
+0xFF3165B0,
+0xFF3165B0,
+0xFF3165B0,
+0xFF3364B0,
+0xFF3364B0,
+0xFF3263AF,
+0xFF3263AF,
+0xFF3263AF,
+0xFF3263AF,
+0xFF3162AE,
+0xFF3162AE,
+0xFF3162AE,
+0xFF3162AE,
+0xFF3062AB,
+0xFF3062AB,
+0xFF3062AB,
+0xFF3062AB,
+0xFF3161AB,
+0xFF3161AB,
+0xFF3161AB,
+0xFF3060AA,
+0xFF3060AA,
+0xFF2F5FA9,
+0xFF2F5FA9,
+0xFF2F5FA9,
+0xFF2F5FA9,
+0xFF2E5EA8,
+0xFF2E5EA8,
+0xFF2D5DA7,
+0xFF2E5CA7,
+0xFF2E5CA7,
+0xFF2E5DA5,
+0xFF2D5CA4,
+0xFF2D5CA4,
+0xFF2C5BA3,
+0xFF2E5AA1,
+0xFF2E5AA1,
+0xFF2D59A0,
+0xFF2D59A0,
+0xFF2D5499,
+0xFF2D5499,
+0xFF2D5499,
+0xFF2D5499,
+0xFF2C5499,
+0xFF2D559A,
+0xFF2E569C,
+0xFF2E569C,
+0xFF2C579C,
+0xFF2C579C,
+0xFF2D589D,
+0xFF2D589D,
+0xFF2E599E,
+0xFF2E599E,
+0xFF2E5AA1,
+0xFF2F59A1,
+0xFF2E58A0,
+0xFF3159A1,
+0xFF325AA2,
+0xFF325AA2,
+0xFF305AA2,
+0xFF305AA2,
+0xFF305AA2,
+0xFF315BA3,
+0xFF305CA5,
+0xFF305CA5,
+0xFF305CA5,
+0xFF305CA5,
+0xFF2F5EA6,
+0xFF2F5EA6,
+0xFF305FA7,
+0xFF305FA7,
+0xFF3160A8,
+0xFF3160A8,
+0xFF3160A8,
+0xFF3160A8,
+0xFF3160A8,
+0xFF3261A9,
+0xFF3261A9,
+0xFF3261A9,
+0xFF3362AA,
+0xFF3362AA,
+0xFF3262AA,
+0xFF3262AA,
+0xFF3262AA,
+0xFF3262AA,
+0xFF3262AA,
+0xFF3262AA,
+0xFF3163AC,
+0xFF3163AC,
+0xFF3264AD,
+0xFF3264AD,
+0xFF3264AD,
+0xFF3264AD,
+0xFF3365AE,
+0xFF3365AE,
+0xFF3365AE,
+0xFF3365AE,
+0xFF3165AE,
+0xFF3165AE,
+0xFF3266AF,
+0xFF3266AF,
+0xFF3266B1,
+0xFF3266B1,
+0xFF3266B1,
+0xFF3367B2,
+0xFF3367B2,
+0xFF3367B2,
+0xFF3367B2,
+0xFF3468B3,
+0xFF3468B3,
+0xFF3468B3,
+0xFF3369B3,
+0xFF3369B3,
+0xFF3369B3,
+0xFF3369B3,
+0xFF3369B3,
+0xFF3369B3,
+0xFF3369B3,
+0xFF3369B3,
+0xFF346AB4,
+0xFF346AB4,
+0xFF346AB4,
+0xFF346AB4,
+0xFF346AB4,
+0xFF346AB4,
+0xFF346AB4,
+0xFF346AB4,
+0xFF336BB5,
+0xFF336BB5,
+0xFF336BB5,
+0xFF336BB5,
+0xFF336BB5,
+0xFF336BB5,
+0xFF336BB5,
+0xFF336BB5,
+0xFF336BB5,
+0xFF336BB5,
+0xFF336BB5,
+0xFF336BB5,
+0xFF336BB5,
+0xFF336BB5,
+0xFF336BB5,
+0xFF336BB5,
+0xFF346CB6,
+0xFF346CB6,
+0xFF346CB6,
+0xFF336BB5,
+0xFF336BB5,
+0xFF336BB5,
+0xFF336BB5,
+0xFF336BB5,
+0xFF326CB5,
+0xFF326CB5,
+0xFF326CB5,
+0xFF326CB5,
+0xFF326CB5,
+0xFF326CB5,
+0xFF326CB5,
+0xFF326CB5,
+0xFF326CB5,
+0xFF326CB5,
+0xFF326CB5,
+0xFF326CB5,
+0xFF326CB5,
+0xFF326CB5,
+0xFF326CB5,
+0xFF326CB5,
+0xFF336DB6,
+0xFF336DB6,
+0xFF336DB6,
+0xFF336DB6,
+0xFF336DB6,
+0xFF336DB6,
+0xFF336DB6,
+0xFF336DB6,
+0xFF336DB6,
+0xFF336DB6,
+0xFF336DB6,
+0xFF336DB6,
+0xFF326EB6,
+0xFF326EB6,
+0xFF326EB6,
+0xFF326EB6,
+0xFF326EB6,
+0xFF326EB6,
+0xFF326EB6,
+0xFF326EB6,
+0xFF326EB6,
+0xFF326EB6,
+0xFF326EB6,
+0xFF326EB6,
+0xFF326EB6,
+0xFF316DB5,
+0xFF316DB5,
+0xFF326EB6,
+0xFF326EB6,
+0xFF326EB6,
+0xFF326EB6,
+0xFF326EB6,
+0xFF326EB6,
+0xFF326EB6,
+0xFF326EB6,
+0xFF326EB6,
+0xFF326EB6,
+0xFF326EB6,
+0xFF336FB7,
+0xFF336FB7,
+0xFF326EB6,
+0xFF326EB6,
+0xFF326EB6,
+0xFF326EB6,
+0xFF326EB6,
+0xFF326EB6,
+0xFF326EB6,
+0xFF326EB6,
+0xFF306FB6,
+0xFF306FB6,
+0xFF306FB6,
+0xFF306FB6,
+0xFF306FB6,
+0xFF306FB6,
+0xFF306FB6,
+0xFF306FB6,
+0xFF306FB6,
+0xFF306FB6,
+0xFF306FB6,
+0xFF306FB6,
+0xFF306FB6,
+0xFF306FB6,
+0xFF306FB6,
+0xFF306FB6,
+0xFF326EB6,
+0xFF326EB6,
+0xFF326EB6,
+0xFF336FB7,
+0xFF336FB7,
+0xFF336FB7,
+0xFF336FB7,
+0xFF336FB7,
+0xFF306FB6,
+0xFF306FB6,
+0xFF306FB6,
+0xFF306FB6,
+0xFF306FB6,
+0xFF306FB6,
+0xFF3170B7,
+0xFF3170B7,
+0xFF336FB7,
+0xFF336FB7,
+0xFF336FB7,
+0xFF336FB7,
+0xFF336FB7,
+0xFF336FB7,
+0xFF3470B8,
+0xFF3470B8,
+0xFF336FB7,
+0xFF336FB7,
+0xFF336FB7,
+0xFF336FB7,
+0xFF336FB7,
+0xFF336FB7,
+0xFF336FB7,
+0xFF336FB7,
+0xFF326EB7,
+0xFF336FB8,
+0xFF336FB8,
+0xFF336FB8,
+0xFF336FB8,
+0xFF326EB7,
+0xFF336FB8,
+0xFF336FB8,
+0xFF336FB8,
+0xFF336FB8,
+0xFF336FB8,
+0xFF336FB8,
+0xFF336FB8,
+0xFF336FB8,
+0xFF336FB8,
+0xFF336FB8,
+0xFF326EB7,
+0xFF326EB7,
+0xFF326EB7,
+0xFF326EB7,
+0xFF326EB7,
+0xFF326EB7,
+0xFF326EB7,
+0xFF326EB7,
+0xFF326EB7,
+0xFF326EB7,
+0xFF326EB7,
+0xFF316DB6,
+0xFF326CB6,
+0xFF326CB6,
+0xFF326CB6,
+0xFF326CB6,
+0xFF336DB7,
+0xFF326CB6,
+0xFF326CB6,
+0xFF326CB6,
+0xFF316BB5,
+0xFF316BB5,
+0xFF336BB6,
+0xFF336BB6,
+0xFF326AB5,
+0xFF326AB5,
+0xFF326AB5,
+0xFF326AB5,
+0xFF326AB5,
+0xFF326AB5,
+0xFF3169B4,
+0xFF3169B4,
+0xFF3368B4,
+0xFF3368B4,
+0xFF3267B3,
+0xFF3267B3,
+0xFF3268B2,
+0xFF3167B1,
+0xFF3167B1,
+0xFF3167B1,
+0xFF3266B1,
+0xFF3266B1,
+0xFF3266B1,
+0xFF3266B1,
+0xFF3266B1,
+0xFF3266B1,
+0xFF3165B0,
+0xFF3165B0,
+0xFF3364B0,
+0xFF3263AF,
+0xFF3263AF,
+0xFF3162AE,
+0xFF3162AE,
+0xFF3162AE,
+0xFF3162AE,
+0xFF3061AD,
+0xFF3062AB,
+0xFF3062AB,
+0xFF3062AB,
+0xFF3062AB,
+0xFF3062AB,
+0xFF3062AB,
+0xFF2F61A8,
+0xFF2E60A7,
+0xFF3060AA,
+0xFF3060AA,
+0xFF2F5FA9,
+0xFF2F5FA9,
+0xFF2E5EA8,
+0xFF2E5EA8,
+0xFF2E5EA8,
+0xFF2E5EA8,
+0xFF2E5DA5,
+0xFF2E5DA5,
+0xFF2D5CA4,
+0xFF2D5CA4,
+0xFF2D5CA4,
+0xFF2D5CA4,
+0xFF2C5BA3,
+0xFF2C5BA3,
+0xFF2E559A,
+0xFF2E559A,
+0xFF2D5499,
+0xFF2E559A,
+0xFF2D559A,
+0xFF2D559A,
+0xFF2E569C,
+0xFF2E569C,
+0xFF2C579C,
+0xFF2D589D,
+0xFF2D589D,
+0xFF2E599E,
+0xFF2E599E,
+0xFF2E599E,
+0xFF2E5AA1,
+0xFF2F5BA2,
+0xFF3159A1,
+0xFF325AA2,
+0xFF325AA2,
+0xFF325AA2,
+0xFF305AA2,
+0xFF305AA2,
+0xFF315BA3,
+0xFF315BA3,
+0xFF305CA5,
+0xFF305CA5,
+0xFF305CA5,
+0xFF315DA6,
+0xFF2F5EA6,
+0xFF305FA7,
+0xFF305FA7,
+0xFF305FA7,
+0xFF3160A8,
+0xFF3160A8,
+0xFF3160A8,
+0xFF3160A8,
+0xFF3261A9,
+0xFF3261A9,
+0xFF3261A9,
+0xFF3261A9,
+0xFF3362AA,
+0xFF3362AA,
+0xFF3262AA,
+0xFF3262AA,
+0xFF3262AA,
+0xFF3262AA,
+0xFF3262AA,
+0xFF3262AA,
+0xFF3163AC,
+0xFF3163AC,
+0xFF3264AD,
+0xFF3365AE,
+0xFF3365AE,
+0xFF3365AE,
+0xFF3466AF,
+0xFF3466AF,
+0xFF3365AE,
+0xFF3365AE,
+0xFF3165AE,
+0xFF3266AF,
+0xFF3266AF,
+0xFF3367B0,
+0xFF3367B2,
+0xFF3367B2,
+0xFF3367B2,
+0xFF3367B2,
+0xFF3367B2,
+0xFF3367B2,
+0xFF3468B3,
+0xFF3468B3,
+0xFF3468B3,
+0xFF3468B3,
+0xFF346AB4,
+0xFF346AB4,
+0xFF346AB4,
+0xFF346AB4,
+0xFF346AB4,
+0xFF346AB4,
+0xFF346AB4,
+0xFF346AB4,
+0xFF356BB5,
+0xFF356BB5,
+0xFF356BB5,
+0xFF356BB5,
+0xFF356BB5,
+0xFF356BB5,
+0xFF356BB5,
+0xFF356BB5,
+0xFF336BB5,
+0xFF336BB5,
+0xFF336BB5,
+0xFF336BB5,
+0xFF336BB5,
+0xFF336BB5,
+0xFF346CB6,
+0xFF346CB6,
+0xFF336BB5,
+0xFF336BB5,
+0xFF336BB5,
+0xFF346CB6,
+0xFF346CB6,
+0xFF336BB5,
+0xFF336BB5,
+0xFF336BB5,
+0xFF356DB7,
+0xFF356DB7,
+0xFF346CB6,
+0xFF346CB6,
+0xFF346CB6,
+0xFF336BB5,
+0xFF336BB5,
+0xFF336BB5,
+0xFF336DB6,
+0xFF336DB6,
+0xFF336DB6,
+0xFF336DB6,
+0xFF336DB6,
+0xFF336DB6,
+0xFF336DB6,
+0xFF336DB6,
+0xFF336DB6,
+0xFF336DB6,
+0xFF336DB6,
+0xFF336DB6,
+0xFF336DB6,
+0xFF336DB6,
+0xFF336DB6,
+0xFF336DB6,
+0xFF336DB6,
+0xFF336DB6,
+0xFF336DB6,
+0xFF336DB6,
+0xFF336DB6,
+0xFF346EB7,
+0xFF346EB7,
+0xFF346EB7,
+0xFF336DB6,
+0xFF336DB6,
+0xFF336DB6,
+0xFF336DB6,
+0xFF326EB6,
+0xFF326EB6,
+0xFF326EB6,
+0xFF326EB6,
+0xFF336FB7,
+0xFF326EB6,
+0xFF326EB6,
+0xFF326EB6,
+0xFF326EB6,
+0xFF326EB6,
+0xFF326EB6,
+0xFF336FB7,
+0xFF326EB6,
+0xFF326EB6,
+0xFF326EB6,
+0xFF326EB6,
+0xFF326EB6,
+0xFF326EB6,
+0xFF326EB6,
+0xFF326EB6,
+0xFF326EB6,
+0xFF326EB6,
+0xFF336FB7,
+0xFF336FB7,
+0xFF336FB7,
+0xFF336FB7,
+0xFF336FB7,
+0xFF336FB7,
+0xFF326EB6,
+0xFF326EB6,
+0xFF326EB6,
+0xFF326EB6,
+0xFF326EB6,
+0xFF326EB6,
+0xFF326EB6,
+0xFF326EB6,
+0xFF3170B7,
+0xFF3170B7,
+0xFF3170B7,
+0xFF3170B7,
+0xFF3170B7,
+0xFF3170B7,
+0xFF3170B7,
+0xFF3170B7,
+0xFF3170B7,
+0xFF3170B7,
+0xFF3170B7,
+0xFF3170B7,
+0xFF3170B7,
+0xFF3170B7,
+0xFF3170B7,
+0xFF3170B7,
+0xFF326EB6,
+0xFF326EB6,
+0xFF336FB7,
+0xFF336FB7,
+0xFF336FB7,
+0xFF336FB7,
+0xFF3470B8,
+0xFF3470B8,
+0xFF3170B7,
+0xFF3170B7,
+0xFF3170B7,
+0xFF3170B7,
+0xFF3170B7,
+0xFF3170B7,
+0xFF3271B8,
+0xFF3271B8,
+0xFF3470B8,
+0xFF3470B8,
+0xFF336FB7,
+0xFF336FB7,
+0xFF336FB7,
+0xFF336FB7,
+0xFF3470B8,
+0xFF3470B8,
+0xFF3470B8,
+0xFF3470B8,
+0xFF3470B8,
+0xFF3470B8,
+0xFF3470B8,
+0xFF3470B8,
+0xFF336FB7,
+0xFF336FB7,
+0xFF336FB8,
+0xFF336FB8,
+0xFF3470B9,
+0xFF3470B9,
+0xFF336FB8,
+0xFF336FB8,
+0xFF336FB8,
+0xFF336FB8,
+0xFF326EB7,
+0xFF326EB7,
+0xFF336FB8,
+0xFF336FB8,
+0xFF336FB8,
+0xFF336FB8,
+0xFF336FB8,
+0xFF336FB8,
+0xFF336FB8,
+0xFF336FB8,
+0xFF336FB8,
+0xFF336FB8,
+0xFF336FB8,
+0xFF326EB7,
+0xFF326EB7,
+0xFF326EB7,
+0xFF326EB7,
+0xFF326EB7,
+0xFF326EB7,
+0xFF326EB7,
+0xFF326CB6,
+0xFF326CB6,
+0xFF326CB6,
+0xFF336DB7,
+0xFF336DB7,
+0xFF336DB7,
+0xFF326CB6,
+0xFF326CB6,
+0xFF326CB6,
+0xFF326CB6,
+0xFF336BB6,
+0xFF336BB6,
+0xFF336BB6,
+0xFF336BB6,
+0xFF336BB6,
+0xFF336BB6,
+0xFF326AB5,
+0xFF326AB5,
+0xFF326AB5,
+0xFF326AB5,
+0xFF3368B4,
+0xFF3368B4,
+0xFF3368B4,
+0xFF3368B4,
+0xFF3268B2,
+0xFF3268B2,
+0xFF3268B2,
+0xFF3167B1,
+0xFF3266B1,
+0xFF3266B1,
+0xFF3367B2,
+0xFF3367B2,
+0xFF3367B2,
+0xFF3266B1,
+0xFF3266B1,
+0xFF3165B0,
+0xFF3364B0,
+0xFF3263AF,
+0xFF3263AF,
+0xFF3263AF,
+0xFF3263AF,
+0xFF3162AE,
+0xFF3162AE,
+0xFF3061AD,
+0xFF3062AB,
+0xFF3062AB,
+0xFF3062AB,
+0xFF3062AB,
+0xFF3062AB,
+0xFF3062AB,
+0xFF2F61A8,
+0xFF2E60A7,
+0xFF3060AA,
+0xFF3060AA,
+0xFF3060AA,
+0xFF2F5FA9,
+0xFF2F5FA9,
+0xFF2E5EA8,
+0xFF2E5EA8,
+0xFF2E5EA8,
+0xFF2F5EA6,
+0xFF2E5DA5,
+0xFF2E5DA5,
+0xFF2E5DA5,
+0xFF2E5DA5,
+0xFF2D5CA4,
+0xFF2D5CA4,
+0xFF2C5BA3,
+0xFF2E559A,
+0xFF2E559A,
+0xFF2D559B,
+0xFF2D559B,
+0xFF2E569C,
+0xFF2E569C,
+0xFF2F579D,
+0xFF2F579D,
+0xFF2E599E,
+0xFF2E599E,
+0xFF2E58A0,
+0xFF2E58A0,
+0xFF2D59A0,
+0xFF2E5AA1,
+0xFF2E5AA1,
+0xFF2E5AA1,
+0xFF3159A1,
+0xFF3159A1,
+0xFF305AA2,
+0xFF305AA2,
+0xFF305AA2,
+0xFF315BA3,
+0xFF305CA3,
+0xFF305CA3,
+0xFF305CA5,
+0xFF305CA5,
+0xFF2F5EA6,
+0xFF2F5EA6,
+0xFF305FA7,
+0xFF305FA7,
+0xFF305FA7,
+0xFF305FA7,
+0xFF3160A8,
+0xFF3261A9,
+0xFF3261A9,
+0xFF3261A9,
+0xFF3261A9,
+0xFF3362AA,
+0xFF3262AA,
+0xFF3262AA,
+0xFF3363AB,
+0xFF3363AB,
+0xFF3262AA,
+0xFF3262AA,
+0xFF3363AB,
+0xFF3363AB,
+0xFF3363AB,
+0xFF3363AB,
+0xFF3365AE,
+0xFF3365AE,
+0xFF3365AE,
+0xFF3365AE,
+0xFF3466AF,
+0xFF3466AF,
+0xFF3266AF,
+0xFF3266AF,
+0xFF3266AF,
+0xFF3266AF,
+0xFF3367B2,
+0xFF3367B2,
+0xFF3367B2,
+0xFF3367B2,
+0xFF3367B2,
+0xFF3367B2,
+0xFF3369B3,
+0xFF3369B3,
+0xFF3369B3,
+0xFF3369B3,
+0xFF3369B3,
+0xFF3369B3,
+0xFF3369B3,
+0xFF3369B3,
+0xFF3369B3,
+0xFF3369B3,
+0xFF346AB4,
+0xFF346AB4,
+0xFF346AB4,
+0xFF346AB4,
+0xFF346AB4,
+0xFF346AB4,
+0xFF336BB5,
+0xFF336BB5,
+0xFF336BB5,
+0xFF336BB5,
+0xFF336BB5,
+0xFF336BB5,
+0xFF336BB5,
+0xFF336BB5,
+0xFF326AB4,
+0xFF326AB4,
+0xFF336BB5,
+0xFF336BB5,
+0xFF336BB5,
+0xFF346CB6,
+0xFF346CB6,
+0xFF346CB6,
+0xFF326CB5,
+0xFF326CB5,
+0xFF336DB6,
+0xFF336DB6,
+0xFF336DB6,
+0xFF336DB6,
+0xFF336DB6,
+0xFF336DB6,
+0xFF336DB6,
+0xFF336DB6,
+0xFF336DB6,
+0xFF336DB6,
+0xFF336DB6,
+0xFF336DB6,
+0xFF336DB6,
+0xFF336DB6,
+0xFF336DB6,
+0xFF336DB6,
+0xFF336DB6,
+0xFF336DB6,
+0xFF336DB6,
+0xFF336DB6,
+0xFF336DB6,
+0xFF336DB6,
+0xFF326EB6,
+0xFF336FB7,
+0xFF336FB7,
+0xFF336FB7,
+0xFF326EB6,
+0xFF326EB6,
+0xFF326EB6,
+0xFF336FB7,
+0xFF336DB6,
+0xFF336DB6,
+0xFF336DB6,
+0xFF336DB6,
+0xFF326EB6,
+0xFF326EB6,
+0xFF326EB6,
+0xFF326EB6,
+0xFF336FB7,
+0xFF336FB7,
+0xFF336FB7,
+0xFF336FB7,
+0xFF326EB6,
+0xFF326EB6,
+0xFF326EB6,
+0xFF326EB6,
+0xFF3470B8,
+0xFF336FB7,
+0xFF326EB6,
+0xFF326EB6,
+0xFF326EB6,
+0xFF336FB7,
+0xFF336FB7,
+0xFF336FB7,
+0xFF3470B8,
+0xFF336FB7,
+0xFF336FB7,
+0xFF336FB7,
+0xFF336FB7,
+0xFF336FB7,
+0xFF336FB7,
+0xFF336FB7,
+0xFF3170B7,
+0xFF3170B7,
+0xFF3470B8,
+0xFF3470B8,
+0xFF336FB7,
+0xFF336FB7,
+0xFF336FB7,
+0xFF3470B8,
+0xFF326EB6,
+0xFF336FB7,
+0xFF336FB7,
+0xFF336FB7,
+0xFF336FB7,
+0xFF336FB7,
+0xFF336FB7,
+0xFF3470B8,
+0xFF3271B8,
+0xFF3271B8,
+0xFF3170B7,
+0xFF3170B7,
+0xFF3170B7,
+0xFF3170B7,
+0xFF3170B7,
+0xFF3271B8,
+0xFF3170B7,
+0xFF3271B8,
+0xFF3271B8,
+0xFF3271B8,
+0xFF3170B7,
+0xFF3170B7,
+0xFF3170B7,
+0xFF3271B8,
+0xFF336FB7,
+0xFF326EB6,
+0xFF336FB7,
+0xFF336FB7,
+0xFF3470B8,
+0xFF3470B8,
+0xFF3470B8,
+0xFF3470B8,
+0xFF3271B8,
+0xFF3271B8,
+0xFF3271B8,
+0xFF3170B7,
+0xFF3170B7,
+0xFF3170B7,
+0xFF3271B8,
+0xFF3372B9,
+0xFF3470B8,
+0xFF3470B8,
+0xFF3470B8,
+0xFF3470B8,
+0xFF3470B8,
+0xFF3470B8,
+0xFF3470B8,
+0xFF3470B8,
+0xFF3571B9,
+0xFF3571B9,
+0xFF3571B9,
+0xFF3571B9,
+0xFF3571B9,
+0xFF3470B8,
+0xFF3470B8,
+0xFF3470B8,
+0xFF3470B9,
+0xFF3470B9,
+0xFF3470B9,
+0xFF3470B9,
+0xFF3470B9,
+0xFF3470B9,
+0xFF3470B9,
+0xFF3470B9,
+0xFF3470B9,
+0xFF3470B9,
+0xFF3470B9,
+0xFF3470B9,
+0xFF3470B9,
+0xFF336FB8,
+0xFF336FB8,
+0xFF336FB8,
+0xFF3470B9,
+0xFF3470B9,
+0xFF3470B9,
+0xFF336FB8,
+0xFF336FB8,
+0xFF336FB8,
+0xFF336FB8,
+0xFF336FB8,
+0xFF336FB8,
+0xFF336FB8,
+0xFF336FB8,
+0xFF336FB8,
+0xFF326EB7,
+0xFF326EB7,
+0xFF326EB7,
+0xFF326EB7,
+0xFF346EB8,
+0xFF336DB7,
+0xFF336DB7,
+0xFF336DB7,
+0xFF336DB7,
+0xFF326CB6,
+0xFF326CB6,
+0xFF336DB7,
+0xFF326CB6,
+0xFF326CB6,
+0xFF336BB6,
+0xFF336BB6,
+0xFF336BB6,
+0xFF326AB5,
+0xFF326AB5,
+0xFF326AB5,
+0xFF326AB5,
+0xFF3169B4,
+0xFF3068B3,
+0xFF3068B3,
+0xFF3268B2,
+0xFF3369B3,
+0xFF3369B3,
+0xFF3268B2,
+0xFF3268B2,
+0xFF3268B2,
+0xFF3268B2,
+0xFF3268B2,
+0xFF3266B1,
+0xFF3266B1,
+0xFF3266B1,
+0xFF3165B0,
+0xFF3165B1,
+0xFF3165B1,
+0xFF3165B0,
+0xFF3165B0,
+0xFF3165B0,
+0xFF3165B0,
+0xFF3165B0,
+0xFF3165B0,
+0xFF3264AD,
+0xFF3163AC,
+0xFF3163AC,
+0xFF3163AC,
+0xFF3163AC,
+0xFF3163AC,
+0xFF3062AB,
+0xFF3062AB,
+0xFF3062AB,
+0xFF3062AB,
+0xFF3060AA,
+0xFF3060AA,
+0xFF2F5FA9,
+0xFF2F5FA9,
+0xFF2F5FA9,
+0xFF2F5FA9,
+0xFF2E5EA6,
+0xFF2E5EA6,
+0xFF2E5EA6,
+0xFF2E5EA6,
+0xFF2D5DA5,
+0xFF2D5DA5,
+0xFF2E5DA5,
+0xFF2D5CA4,
+0xFF2E559A,
+0xFF2E559A,
+0xFF2D559B,
+0xFF2E569C,
+0xFF2E569C,
+0xFF2F579D,
+0xFF2F579D,
+0xFF30589E,
+0xFF2E599E,
+0xFF2E599E,
+0xFF2F59A1,
+0xFF2F59A1,
+0xFF2E5AA1,
+0xFF2E5AA1,
+0xFF2F5BA2,
+0xFF2F5BA2,
+0xFF2F59A1,
+0xFF305AA2,
+0xFF305AA2,
+0xFF305AA2,
+0xFF315BA3,
+0xFF305CA3,
+0xFF305CA3,
+0xFF305CA3,
+0xFF315DA6,
+0xFF315DA6,
+0xFF305FA7,
+0xFF305FA7,
+0xFF305FA7,
+0xFF3160A8,
+0xFF3160A8,
+0xFF3160A8,
+0xFF3261A9,
+0xFF3261A9,
+0xFF3261A9,
+0xFF3362AA,
+0xFF3362AA,
+0xFF3362AA,
+0xFF3262AA,
+0xFF3262AA,
+0xFF3363AB,
+0xFF3363AB,
+0xFF3262AA,
+0xFF3363AB,
+0xFF3363AB,
+0xFF3464AC,
+0xFF3464AC,
+0xFF3363AB,
+0xFF3365AE,
+0xFF3365AE,
+0xFF3365AE,
+0xFF3466AF,
+0xFF3466AF,
+0xFF3466AF,
+0xFF3266AF,
+0xFF3266AF,
+0xFF3367B0,
+0xFF3367B0,
+0xFF3367B2,
+0xFF3468B3,
+0xFF3468B3,
+0xFF3468B3,
+0xFF3468B3,
+0xFF3468B3,
+0xFF3369B3,
+0xFF3369B3,
+0xFF3369B3,
+0xFF3369B3,
+0xFF346AB4,
+0xFF346AB4,
+0xFF346AB4,
+0xFF346AB4,
+0xFF346AB4,
+0xFF346AB4,
+0xFF346AB4,
+0xFF356BB5,
+0xFF356BB5,
+0xFF356BB5,
+0xFF356BB5,
+0xFF356BB5,
+0xFF336BB5,
+0xFF336BB5,
+0xFF336BB5,
+0xFF336BB5,
+0xFF336BB5,
+0xFF336BB5,
+0xFF336BB5,
+0xFF336BB5,
+0xFF346CB6,
+0xFF346CB6,
+0xFF346CB6,
+0xFF346CB6,
+0xFF346CB6,
+0xFF346CB6,
+0xFF346CB6,
+0xFF346CB6,
+0xFF326CB5,
+0xFF336DB6,
+0xFF336DB6,
+0xFF336DB6,
+0xFF336DB6,
+0xFF336DB6,
+0xFF336DB6,
+0xFF336DB6,
+0xFF336DB6,
+0xFF336DB6,
+0xFF336DB6,
+0xFF336DB6,
+0xFF336DB6,
+0xFF336DB6,
+0xFF336DB6,
+0xFF336DB6,
+0xFF346EB7,
+0xFF346EB7,
+0xFF346EB7,
+0xFF346EB7,
+0xFF346EB7,
+0xFF346EB7,
+0xFF346EB7,
+0xFF346EB7,
+0xFF326EB6,
+0xFF336FB7,
+0xFF336FB7,
+0xFF336FB7,
+0xFF336FB7,
+0xFF326EB6,
+0xFF336FB7,
+0xFF336FB7,
+0xFF346EB7,
+0xFF346EB7,
+0xFF346EB7,
+0xFF346EB7,
+0xFF336FB7,
+0xFF336FB7,
+0xFF336FB7,
+0xFF336FB7,
+0xFF336FB7,
+0xFF336FB7,
+0xFF336FB7,
+0xFF336FB7,
+0xFF3470B8,
+0xFF336FB7,
+0xFF336FB7,
+0xFF336FB7,
+0xFF336FB7,
+0xFF336FB7,
+0xFF336FB7,
+0xFF336FB7,
+0xFF336FB7,
+0xFF3470B8,
+0xFF336FB7,
+0xFF336FB7,
+0xFF336FB7,
+0xFF336FB7,
+0xFF336FB7,
+0xFF336FB7,
+0xFF336FB7,
+0xFF3470B8,
+0xFF3470B8,
+0xFF3470B8,
+0xFF3170B7,
+0xFF3271B8,
+0xFF3470B8,
+0xFF3470B8,
+0xFF336FB7,
+0xFF336FB7,
+0xFF3470B8,
+0xFF3470B8,
+0xFF336FB7,
+0xFF3470B8,
+0xFF3470B8,
+0xFF3470B8,
+0xFF3470B8,
+0xFF3470B8,
+0xFF3470B8,
+0xFF3470B8,
+0xFF3271B8,
+0xFF3271B8,
+0xFF3271B8,
+0xFF3271B8,
+0xFF3271B8,
+0xFF3271B8,
+0xFF3271B8,
+0xFF3271B8,
+0xFF3271B8,
+0xFF3271B8,
+0xFF3271B8,
+0xFF3271B8,
+0xFF3271B8,
+0xFF3271B8,
+0xFF3271B8,
+0xFF3271B8,
+0xFF3470B8,
+0xFF3470B8,
+0xFF3470B8,
+0xFF3470B8,
+0xFF3571B9,
+0xFF3571B9,
+0xFF3470B8,
+0xFF3470B8,
+0xFF3271B8,
+0xFF3271B8,
+0xFF3372B9,
+0xFF3372B9,
+0xFF3271B8,
+0xFF3271B8,
+0xFF3271B8,
+0xFF3372B9,
+0xFF3571B9,
+0xFF3571B9,
+0xFF3571B9,
+0xFF3571B9,
+0xFF3571B9,
+0xFF3571B9,
+0xFF3571B9,
+0xFF3571B9,
+0xFF3571B9,
+0xFF3571B9,
+0xFF3571B9,
+0xFF3571B9,
+0xFF3571B9,
+0xFF3571B9,
+0xFF3470B8,
+0xFF3470B8,
+0xFF3571BA,
+0xFF3571BA,
+0xFF3571BA,
+0xFF3571BA,
+0xFF3571BA,
+0xFF3571BA,
+0xFF3470B9,
+0xFF3470B9,
+0xFF3470B9,
+0xFF3470B9,
+0xFF3470B9,
+0xFF3470B9,
+0xFF3470B9,
+0xFF3470B9,
+0xFF3470B9,
+0xFF3470B9,
+0xFF3470B9,
+0xFF3470B9,
+0xFF3470B9,
+0xFF3470B9,
+0xFF336FB8,
+0xFF336FB8,
+0xFF336FB8,
+0xFF336FB8,
+0xFF336FB8,
+0xFF336FB8,
+0xFF336FB8,
+0xFF336FB8,
+0xFF336FB8,
+0xFF336FB8,
+0xFF326EB7,
+0xFF326EB7,
+0xFF346EB8,
+0xFF336DB7,
+0xFF336DB7,
+0xFF336DB7,
+0xFF336DB7,
+0xFF326CB6,
+0xFF326CB6,
+0xFF336DB7,
+0xFF326CB6,
+0xFF326CB6,
+0xFF346CB7,
+0xFF336BB6,
+0xFF336BB6,
+0xFF336BB6,
+0xFF336BB6,
+0xFF326AB5,
+0xFF326AB5,
+0xFF326AB5,
+0xFF3169B4,
+0xFF3169B4,
+0xFF3369B3,
+0xFF3369B3,
+0xFF3369B3,
+0xFF3369B3,
+0xFF3369B3,
+0xFF3369B3,
+0xFF3268B2,
+0xFF3268B2,
+0xFF3367B2,
+0xFF3367B2,
+0xFF3266B1,
+0xFF3266B1,
+0xFF3266B2,
+0xFF3165B1,
+0xFF3165B0,
+0xFF3165B0,
+0xFF3165B0,
+0xFF3165B0,
+0xFF3165B0,
+0xFF3165B0,
+0xFF3264AD,
+0xFF3163AC,
+0xFF3163AC,
+0xFF3163AC,
+0xFF3163AC,
+0xFF3163AC,
+0xFF3062AB,
+0xFF3062AB,
+0xFF3062AB,
+0xFF3062AB,
+0xFF3060AA,
+0xFF3060AA,
+0xFF3060AA,
+0xFF2F5FA9,
+0xFF2F5FA9,
+0xFF2F5FA9,
+0xFF2E5EA6,
+0xFF2E5EA6,
+0xFF2E5EA6,
+0xFF2E5EA6,
+0xFF2E5EA6,
+0xFF2D5DA5,
+0xFF2E5DA5,
+0xFF2E5DA5,
+0xFF2D559B,
+0xFF2E569C,
+0xFF2E569C,
+0xFF2F579D,
+0xFF2D589D,
+0xFF2E599E,
+0xFF2E599E,
+0xFF2F5A9F,
+0xFF2F59A1,
+0xFF2F59A1,
+0xFF2E5AA1,
+0xFF2E5AA1,
+0xFF2F5BA2,
+0xFF2F5BA2,
+0xFF2F5BA2,
+0xFF305CA3,
+0xFF305AA2,
+0xFF305AA2,
+0xFF315BA3,
+0xFF305CA3,
+0xFF305CA3,
+0xFF315DA4,
+0xFF315DA6,
+0xFF2F5EA6,
+0xFF305FA7,
+0xFF305FA7,
+0xFF3160A8,
+0xFF3160A8,
+0xFF3261A9,
+0xFF3261A9,
+0xFF3261A9,
+0xFF3261A9,
+0xFF3262AA,
+0xFF3262AA,
+0xFF3262AA,
+0xFF3262AA,
+0xFF3363AB,
+0xFF3363AB,
+0xFF3363AB,
+0xFF3363AB,
+0xFF3464AC,
+0xFF3363AB,
+0xFF3363AB,
+0xFF3363AB,
+0xFF3464AE,
+0xFF3464AE,
+0xFF3365AE,
+0xFF3365AE,
+0xFF3466AF,
+0xFF3466AF,
+0xFF3266AF,
+0xFF3266AF,
+0xFF3367B0,
+0xFF3367B0,
+0xFF3367B0,
+0xFF3367B0,
+0xFF3468B3,
+0xFF3468B3,
+0xFF3468B3,
+0xFF3468B3,
+0xFF346AB4,
+0xFF346AB4,
+0xFF346AB4,
+0xFF3369B3,
+0xFF3369B3,
+0xFF3369B3,
+0xFF3369B3,
+0xFF346AB4,
+0xFF346AB4,
+0xFF356BB5,
+0xFF356BB5,
+0xFF356BB5,
+0xFF336BB5,
+0xFF336BB5,
+0xFF336BB5,
+0xFF336BB5,
+0xFF346CB6,
+0xFF346CB6,
+0xFF346CB6,
+0xFF346CB6,
+0xFF336BB5,
+0xFF336BB5,
+0xFF336BB5,
+0xFF346CB6,
+0xFF346CB6,
+0xFF346CB6,
+0xFF336BB5,
+0xFF336BB5,
+0xFF346EB7,
+0xFF346EB7,
+0xFF346EB7,
+0xFF346EB7,
+0xFF336DB6,
+0xFF336DB6,
+0xFF336DB6,
+0xFF336DB6,
+0xFF336DB6,
+0xFF346EB7,
+0xFF346EB7,
+0xFF336DB6,
+0xFF336DB6,
+0xFF336DB6,
+0xFF336DB6,
+0xFF346EB7,
+0xFF336DB6,
+0xFF336DB6,
+0xFF336DB6,
+0xFF346EB7,
+0xFF346EB7,
+0xFF346EB7,
+0xFF346EB7,
+0xFF346EB7,
+0xFF346EB7,
+0xFF346EB7,
+0xFF346EB7,
+0xFF346EB7,
+0xFF336FB7,
+0xFF336FB7,
+0xFF336FB7,
+0xFF336FB7,
+0xFF336FB7,
+0xFF336FB7,
+0xFF3470B8,
+0xFF3470B8,
+0xFF336FB7,
+0xFF336FB7,
+0xFF336FB7,
+0xFF336FB7,
+0xFF356FB8,
+0xFF356FB8,
+0xFF3470B8,
+0xFF3470B8,
+0xFF3470B8,
+0xFF3470B8,
+0xFF336FB7,
+0xFF336FB7,
+0xFF336FB7,
+0xFF336FB7,
+0xFF3470B8,
+0xFF3470B8,
+0xFF3470B8,
+0xFF3470B8,
+0xFF3470B8,
+0xFF3470B8,
+0xFF336FB7,
+0xFF336FB7,
+0xFF336FB7,
+0xFF3470B8,
+0xFF3470B8,
+0xFF3470B8,
+0xFF3470B8,
+0xFF336FB7,
+0xFF336FB7,
+0xFF336FB7,
+0xFF3470B8,
+0xFF3470B8,
+0xFF3470B8,
+0xFF3470B8,
+0xFF3470B8,
+0xFF3470B8,
+0xFF3271B8,
+0xFF3271B8,
+0xFF3271B8,
+0xFF3271B8,
+0xFF3271B8,
+0xFF3271B8,
+0xFF3470B8,
+0xFF3571B9,
+0xFF3470B8,
+0xFF3470B8,
+0xFF3571B9,
+0xFF3571B9,
+0xFF3571B9,
+0xFF3571B9,
+0xFF3571B9,
+0xFF3571B9,
+0xFF3470B8,
+0xFF3571B9,
+0xFF3571B9,
+0xFF3571B9,
+0xFF3571B9,
+0xFF3571B9,
+0xFF3470B8,
+0xFF3470B8,
+0xFF3470B8,
+0xFF3470B8,
+0xFF3571B9,
+0xFF3571B9,
+0xFF3470B8,
+0xFF3470B8,
+0xFF3470B8,
+0xFF3571B9,
+0xFF3571B9,
+0xFF3571B9,
+0xFF3571B9,
+0xFF3571B9,
+0xFF3571B9,
+0xFF3571B9,
+0xFF3571B9,
+0xFF3470B8,
+0xFF3470B8,
+0xFF3571B9,
+0xFF3473BA,
+0xFF3473BA,
+0xFF3473BA,
+0xFF3372B9,
+0xFF3372B9,
+0xFF3372B9,
+0xFF3672BA,
+0xFF3672BA,
+0xFF3672BA,
+0xFF3672BA,
+0xFF3672BA,
+0xFF3672BA,
+0xFF3672BA,
+0xFF3672BA,
+0xFF3571B9,
+0xFF3571B9,
+0xFF3672BA,
+0xFF3672BA,
+0xFF3672BB,
+0xFF3571BA,
+0xFF3571BA,
+0xFF3571BA,
+0xFF3672BB,
+0xFF3672BB,
+0xFF3672BB,
+0xFF3672BB,
+0xFF3672BB,
+0xFF3672BB,
+0xFF3571BA,
+0xFF3571BA,
+0xFF3571BA,
+0xFF3571BA,
+0xFF3571BA,
+0xFF3571BA,
+0xFF3571BA,
+0xFF3571BA,
+0xFF3571BA,
+0xFF3571BA,
+0xFF3571BA,
+0xFF3571BA,
+0xFF3470B9,
+0xFF3470B9,
+0xFF3470B9,
+0xFF3470B9,
+0xFF3470B9,
+0xFF3470B9,
+0xFF3470B9,
+0xFF3470B9,
+0xFF3470B9,
+0xFF3470B9,
+0xFF3470B9,
+0xFF3470B9,
+0xFF336FB8,
+0xFF336FB8,
+0xFF336FB8,
+0xFF336FB8,
+0xFF326EB7,
+0xFF336FB8,
+0xFF336FB8,
+0xFF326EB7,
+0xFF336DB7,
+0xFF346EB8,
+0xFF336DB7,
+0xFF336DB7,
+0xFF336DB7,
+0xFF336DB7,
+0xFF336DB7,
+0xFF336DB7,
+0xFF336DB7,
+0xFF336DB7,
+0xFF336BB6,
+0xFF336BB6,
+0xFF336BB6,
+0xFF336BB6,
+0xFF336BB5,
+0xFF336BB5,
+0xFF326AB4,
+0xFF326AB4,
+0xFF3369B3,
+0xFF3369B3,
+0xFF3369B3,
+0xFF3369B3,
+0xFF3369B3,
+0xFF3369B3,
+0xFF3268B2,
+0xFF3268B2,
+0xFF3266B1,
+0xFF3266B1,
+0xFF3266B1,
+0xFF3266B1,
+0xFF3165B0,
+0xFF3165B0,
+0xFF3165B0,
+0xFF3165B0,
+0xFF3064AF,
+0xFF3064AF,
+0xFF3064AD,
+0xFF2F63AC,
+0xFF2F63AC,
+0xFF2F63AC,
+0xFF3163AC,
+0xFF3062AB,
+0xFF3062AB,
+0xFF3062AB,
+0xFF3062AB,
+0xFF3062AB,
+0xFF2F61AA,
+0xFF2F61AA,
+0xFF3060AA,
+0xFF2F5FA9,
+0xFF2F5FA9,
+0xFF2F5FA9,
+0xFF2F5FA9,
+0xFF2E5EA8,
+0xFF2E5EA6,
+0xFF2E5EA6,
+0xFF2D5DA5,
+0xFF2D5DA5,
+0xFF2E569C,
+0xFF2E569C,
+0xFF2F579D,
+0xFF30589E,
+0xFF2E599E,
+0xFF2F5A9F,
+0xFF2F5A9F,
+0xFF305BA0,
+0xFF305AA2,
+0xFF305AA2,
+0xFF2F5BA2,
+0xFF2F5BA2,
+0xFF2F5BA2,
+0xFF2F5BA2,
+0xFF305CA3,
+0xFF305CA3,
+0xFF315BA3,
+0xFF305CA3,
+0xFF305CA3,
+0xFF315DA4,
+0xFF315DA4,
+0xFF305FA5,
+0xFF305FA7,
+0xFF305FA7,
+0xFF3160A8,
+0xFF3160A8,
+0xFF3261A9,
+0xFF3261A9,
+0xFF3261A9,
+0xFF3362AA,
+0xFF3362AA,
+0xFF3362AA,
+0xFF3262AA,
+0xFF3262AA,
+0xFF3262AA,
+0xFF3363AB,
+0xFF3363AB,
+0xFF3363AB,
+0xFF3363AB,
+0xFF3464AC,
+0xFF3464AC,
+0xFF3464AC,
+0xFF3464AC,
+0xFF3464AC,
+0xFF3464AE,
+0xFF3565AF,
+0xFF3466AF,
+0xFF3466AF,
+0xFF3567B0,
+0xFF3567B0,
+0xFF3367B0,
+0xFF3367B0,
+0xFF3468B1,
+0xFF3468B1,
+0xFF3468B1,
+0xFF3468B1,
+0xFF3468B3,
+0xFF3468B3,
+0xFF3569B4,
+0xFF3569B4,
+0xFF346AB4,
+0xFF346AB4,
+0xFF346AB4,
+0xFF346AB4,
+0xFF346AB4,
+0xFF346AB4,
+0xFF346AB4,
+0xFF346AB4,
+0xFF356BB5,
+0xFF356BB5,
+0xFF356BB5,
+0xFF356BB5,
+0xFF336BB5,
+0xFF336BB5,
+0xFF346CB6,
+0xFF346CB6,
+0xFF346CB6,
+0xFF346CB6,
+0xFF346CB6,
+0xFF346CB6,
+0xFF336BB5,
+0xFF336BB5,
+0xFF346CB6,
+0xFF346CB6,
+0xFF346CB6,
+0xFF346CB6,
+0xFF346CB6,
+0xFF346CB6,
+0xFF336DB6,
+0xFF336DB6,
+0xFF346EB7,
+0xFF346EB7,
+0xFF346EB7,
+0xFF356FB8,
+0xFF356FB8,
+0xFF356FB8,
+0xFF346EB7,
+0xFF346EB7,
+0xFF346EB7,
+0xFF346EB7,
+0xFF336DB6,
+0xFF336DB6,
+0xFF346EB7,
+0xFF356FB8,
+0xFF346EB7,
+0xFF346EB7,
+0xFF346EB7,
+0xFF346EB7,
+0xFF346EB7,
+0xFF346EB7,
+0xFF346EB7,
+0xFF346EB7,
+0xFF346EB7,
+0xFF346EB7,
+0xFF346EB7,
+0xFF346EB7,
+0xFF336FB7,
+0xFF336FB7,
+0xFF336FB7,
+0xFF336FB7,
+0xFF3470B8,
+0xFF3470B8,
+0xFF3470B8,
+0xFF3470B8,
+0xFF3470B8,
+0xFF3470B8,
+0xFF3470B8,
+0xFF3470B8,
+0xFF356FB8,
+0xFF356FB8,
+0xFF3470B8,
+0xFF3470B8,
+0xFF3470B8,
+0xFF3470B8,
+0xFF3470B8,
+0xFF3470B8,
+0xFF336FB7,
+0xFF336FB7,
+0xFF3470B8,
+0xFF3470B8,
+0xFF3470B8,
+0xFF3470B8,
+0xFF3470B8,
+0xFF3470B8,
+0xFF3470B8,
+0xFF3470B8,
+0xFF3470B8,
+0xFF3470B8,
+0xFF3470B8,
+0xFF3571B9,
+0xFF3470B8,
+0xFF3470B8,
+0xFF336FB7,
+0xFF3470B8,
+0xFF3470B8,
+0xFF3571B9,
+0xFF3571B9,
+0xFF3571B9,
+0xFF3470B8,
+0xFF3470B8,
+0xFF3271B8,
+0xFF3271B8,
+0xFF3372B9,
+0xFF3372B9,
+0xFF3271B8,
+0xFF3271B8,
+0xFF3571B9,
+0xFF3571B9,
+0xFF3571B9,
+0xFF3571B9,
+0xFF3571B9,
+0xFF3571B9,
+0xFF3571B9,
+0xFF3571B9,
+0xFF3672BA,
+0xFF3672BA,
+0xFF3571B9,
+0xFF3571B9,
+0xFF3571B9,
+0xFF3672BA,
+0xFF3672BA,
+0xFF3571B9,
+0xFF3571B9,
+0xFF3470B8,
+0xFF3571B9,
+0xFF3571B9,
+0xFF3571B9,
+0xFF3571B9,
+0xFF3571B9,
+0xFF3571B9,
+0xFF3571B9,
+0xFF3672BA,
+0xFF3672BA,
+0xFF3571B9,
+0xFF3571B9,
+0xFF3571B9,
+0xFF3672BA,
+0xFF3672BA,
+0xFF3571B9,
+0xFF3571B9,
+0xFF3571B9,
+0xFF3571B9,
+0xFF3473BA,
+0xFF3473BA,
+0xFF3473BA,
+0xFF3473BA,
+0xFF3473BA,
+0xFF3372B9,
+0xFF3672BA,
+0xFF3672BA,
+0xFF3672BA,
+0xFF3672BA,
+0xFF3672BA,
+0xFF3571B9,
+0xFF3672BA,
+0xFF3672BA,
+0xFF3672BA,
+0xFF3672BA,
+0xFF3672BA,
+0xFF3773BB,
+0xFF3672BB,
+0xFF3672BB,
+0xFF3672BB,
+0xFF3672BB,
+0xFF3672BB,
+0xFF3672BB,
+0xFF3672BB,
+0xFF3672BB,
+0xFF3672BB,
+0xFF3672BB,
+0xFF3672BB,
+0xFF3672BB,
+0xFF3672BB,
+0xFF3672BB,
+0xFF3672BB,
+0xFF3672BB,
+0xFF3672BB,
+0xFF3571BA,
+0xFF3571BA,
+0xFF3571BA,
+0xFF3571BA,
+0xFF3571BA,
+0xFF3571BA,
+0xFF3571BA,
+0xFF3571BA,
+0xFF3571BA,
+0xFF3571BA,
+0xFF3571BA,
+0xFF3571BA,
+0xFF3571BA,
+0xFF3571BA,
+0xFF3571BA,
+0xFF3470B9,
+0xFF3470B9,
+0xFF3470B9,
+0xFF3470B9,
+0xFF3470B9,
+0xFF336FB8,
+0xFF336FB8,
+0xFF336FB8,
+0xFF336FB8,
+0xFF336FB8,
+0xFF346EB8,
+0xFF346EB8,
+0xFF336DB7,
+0xFF336DB7,
+0xFF336DB7,
+0xFF336DB7,
+0xFF336DB7,
+0xFF336DB7,
+0xFF336DB7,
+0xFF336DB7,
+0xFF336BB6,
+0xFF336BB6,
+0xFF346CB7,
+0xFF346CB7,
+0xFF346CB6,
+0xFF336BB5,
+0xFF336BB5,
+0xFF326AB4,
+0xFF3369B3,
+0xFF3369B3,
+0xFF3369B3,
+0xFF3369B3,
+0xFF3369B3,
+0xFF3369B3,
+0xFF3369B3,
+0xFF3369B3,
+0xFF3367B2,
+0xFF3367B2,
+0xFF3367B2,
+0xFF3266B1,
+0xFF3266B1,
+0xFF3165B0,
+0xFF3165B0,
+0xFF3165B0,
+0xFF3165B0,
+0xFF3165B0,
+0xFF3064AD,
+0xFF3064AD,
+0xFF3064AD,
+0xFF3064AD,
+0xFF3163AC,
+0xFF3163AC,
+0xFF3163AC,
+0xFF3163AC,
+0xFF3163AC,
+0xFF3062AB,
+0xFF3062AB,
+0xFF3062AB,
+0xFF3060AA,
+0xFF3060AA,
+0xFF2F5FA9,
+0xFF2F5FA9,
+0xFF2F5FA9,
+0xFF2F5FA9,
+0xFF2F5FA7,
+0xFF2E5EA6,
+0xFF2E5EA6,
+0xFF2D5DA5,
+0xFF2D589D,
+0xFF2D589D,
+0xFF2E599E,
+0xFF2F5A9F,
+0xFF2F5A9F,
+0xFF305BA0,
+0xFF305BA0,
+0xFF305BA0,
+0xFF305AA2,
+0xFF305AA2,
+0xFF2F5BA2,
+0xFF2F5BA2,
+0xFF2F5BA2,
+0xFF305CA3,
+0xFF305CA3,
+0xFF305CA3,
+0xFF315DA4,
+0xFF315DA4,
+0xFF315DA4,
+0xFF305FA5,
+0xFF305FA5,
+0xFF3160A6,
+0xFF3160A8,
+0xFF3060A8,
+0xFF3161A9,
+0xFF3161A9,
+0xFF3161A9,
+0xFF3161A9,
+0xFF3362AA,
+0xFF3362AA,
+0xFF3362AA,
+0xFF3362AA,
+0xFF3262AA,
+0xFF3363AB,
+0xFF3363AB,
+0xFF3363AB,
+0xFF3264AD,
+0xFF3264AD,
+0xFF3365AE,
+0xFF3365AE,
+0xFF3466AF,
+0xFF3466AF,
+0xFF3466AF,
+0xFF3466AF,
+0xFF3466AF,
+0xFF3466AF,
+0xFF3567B0,
+0xFF3567B0,
+0xFF3367B0,
+0xFF3468B1,
+0xFF3468B1,
+0xFF3468B1,
+0xFF3468B1,
+0xFF3468B1,
+0xFF3468B1,
+0xFF3468B1,
+0xFF346AB4,
+0xFF346AB4,
+0xFF346AB4,
+0xFF346AB4,
+0xFF346AB4,
+0xFF346AB4,
+0xFF346AB4,
+0xFF346AB4,
+0xFF336BB5,
+0xFF336BB5,
+0xFF336BB5,
+0xFF336BB5,
+0xFF336BB5,
+0xFF336BB5,
+0xFF346CB6,
+0xFF346CB6,
+0xFF346CB6,
+0xFF346CB6,
+0xFF346CB6,
+0xFF346CB6,
+0xFF346CB6,
+0xFF346CB6,
+0xFF346CB6,
+0xFF346CB6,
+0xFF336EB4,
+0xFF336EB4,
+0xFF336EB4,
+0xFF346FB5,
+0xFF346FB5,
+0xFF346FB5,
+0xFF346FB5,
+0xFF346FB5,
+0xFF346FB5,
+0xFF346FB5,
+0xFF346FB5,
+0xFF346FB5,
+0xFF3570B6,
+0xFF3570B6,
+0xFF3570B6,
+0xFF3570B6,
+0xFF336FB5,
+0xFF336FB5,
+0xFF336FB5,
+0xFF336FB5,
+0xFF336FB5,
+0xFF336FB5,
+0xFF3470B6,
+0xFF3571B7,
+0xFF3470B6,
+0xFF3470B6,
+0xFF3470B6,
+0xFF3470B6,
+0xFF3470B6,
+0xFF3470B6,
+0xFF3470B6,
+0xFF3470B6,
+0xFF356FB8,
+0xFF356FB8,
+0xFF356FB8,
+0xFF356FB8,
+0xFF3470B8,
+0xFF3470B8,
+0xFF3470B8,
+0xFF3470B8,
+0xFF3571B9,
+0xFF3571B9,
+0xFF3571B9,
+0xFF3571B9,
+0xFF3571B9,
+0xFF3571B9,
+0xFF3470B8,
+0xFF3470B8,
+0xFF3671B7,
+0xFF3671B7,
+0xFF3671B7,
+0xFF3671B7,
+0xFF3671B7,
+0xFF3671B7,
+0xFF3571B7,
+0xFF3571B7,
+0xFF3470B6,
+0xFF3470B6,
+0xFF3470B6,
+0xFF3470B6,
+0xFF3470B6,
+0xFF3470B6,
+0xFF3470B6,
+0xFF3470B6,
+0xFF3571B9,
+0xFF3470B8,
+0xFF3470B8,
+0xFF3470B8,
+0xFF3470B8,
+0xFF3571B9,
+0xFF3571B9,
+0xFF3571B9,
+0xFF3470B8,
+0xFF3470B8,
+0xFF3571B9,
+0xFF3571B9,
+0xFF3571B9,
+0xFF3571B9,
+0xFF3470B8,
+0xFF3470B8,
+0xFF3372B9,
+0xFF3372B9,
+0xFF3372B9,
+0xFF3372B9,
+0xFF3571B9,
+0xFF3571B9,
+0xFF3571B9,
+0xFF3571B9,
+0xFF3571B9,
+0xFF3571B9,
+0xFF3571B9,
+0xFF3672BA,
+0xFF3672BA,
+0xFF3672BA,
+0xFF3672BA,
+0xFF3672BA,
+0xFF3571B9,
+0xFF3571B9,
+0xFF3672BA,
+0xFF3672BA,
+0xFF3672BA,
+0xFF3672BA,
+0xFF3571B9,
+0xFF3571B9,
+0xFF3571B9,
+0xFF3672BA,
+0xFF3672BA,
+0xFF3672BA,
+0xFF3672BA,
+0xFF3672BA,
+0xFF3672BA,
+0xFF3672BA,
+0xFF3672BA,
+0xFF3672BA,
+0xFF3672BA,
+0xFF3672BA,
+0xFF3773BB,
+0xFF3773BB,
+0xFF3773BB,
+0xFF3672BA,
+0xFF3672BA,
+0xFF3672BA,
+0xFF3672BA,
+0xFF3571B9,
+0xFF3672BA,
+0xFF3672BA,
+0xFF3672BA,
+0xFF3672BA,
+0xFF3672BA,
+0xFF3672BA,
+0xFF3672BA,
+0xFF3672BA,
+0xFF3672BB,
+0xFF3672BB,
+0xFF3672BB,
+0xFF3672BB,
+0xFF3672BB,
+0xFF3773BC,
+0xFF3773BC,
+0xFF3773BC,
+0xFF3773BC,
+0xFF3773BC,
+0xFF3773BC,
+0xFF3773BC,
+0xFF3672BB,
+0xFF3773BC,
+0xFF3773BC,
+0xFF3773BC,
+0xFF3773BC,
+0xFF3672BB,
+0xFF3672BB,
+0xFF3672BB,
+0xFF3672BB,
+0xFF3672BB,
+0xFF3672BB,
+0xFF3672BB,
+0xFF3672BB,
+0xFF3672BB,
+0xFF3672BB,
+0xFF3672BB,
+0xFF3672BB,
+0xFF3672BB,
+0xFF3672BB,
+0xFF3672BB,
+0xFF3571BA,
+0xFF3571BA,
+0xFF3571BA,
+0xFF3571BA,
+0xFF3571BA,
+0xFF3571BA,
+0xFF3571BA,
+0xFF3571BA,
+0xFF3571BA,
+0xFF3571BA,
+0xFF3470B9,
+0xFF3470B9,
+0xFF3571BA,
+0xFF3470B9,
+0xFF3470B9,
+0xFF3470B9,
+0xFF3470B9,
+0xFF336FB8,
+0xFF336FB8,
+0xFF3470B9,
+0xFF336FB8,
+0xFF336FB8,
+0xFF336DB7,
+0xFF336DB7,
+0xFF336DB7,
+0xFF336DB7,
+0xFF336DB7,
+0xFF336DB7,
+0xFF326CB6,
+0xFF336DB7,
+0xFF336DB7,
+0xFF336DB7,
+0xFF346CB6,
+0xFF336BB5,
+0xFF336BB5,
+0xFF336BB5,
+0xFF326AB4,
+0xFF326AB4,
+0xFF326AB4,
+0xFF326AB4,
+0xFF346AB4,
+0xFF346AB4,
+0xFF3369B3,
+0xFF3369B3,
+0xFF3468B3,
+0xFF3468B3,
+0xFF3468B3,
+0xFF3367B2,
+0xFF3367B2,
+0xFF3266B1,
+0xFF3266B1,
+0xFF3165B0,
+0xFF3165B0,
+0xFF3165B0,
+0xFF3165B0,
+0xFF3165B0,
+0xFF3064AF,
+0xFF3064AF,
+0xFF3064AF,
+0xFF3064AF,
+0xFF3264AD,
+0xFF3264AD,
+0xFF3163AC,
+0xFF3163AC,
+0xFF3163AC,
+0xFF3062AB,
+0xFF3062AB,
+0xFF3062AB,
+0xFF2F61AA,
+0xFF2F61AA,
+0xFF2F61AA,
+0xFF2F61AA,
+0xFF2E60A9,
+0xFF2E60A9,
+0xFF2D5FA8,
+0xFF2D5FA8,
+0xFF2E599E,
+0xFF2E599E,
+0xFF2F5A9F,
+0xFF305BA0,
+0xFF305BA0,
+0xFF305BA0,
+0xFF305BA0,
+0xFF305BA0,
+0xFF305AA2,
+0xFF305AA2,
+0xFF2F5BA2,
+0xFF2F5BA2,
+0xFF305CA3,
+0xFF305CA3,
+0xFF305CA3,
+0xFF315DA4,
+0xFF325EA5,
+0xFF325EA5,
+0xFF305FA5,
+0xFF3160A6,
+0xFF3160A6,
+0xFF3261A7,
+0xFF3161A9,
+0xFF3161A9,
+0xFF3161A9,
+0xFF3161A9,
+0xFF3262AA,
+0xFF3262AA,
+0xFF3362AA,
+0xFF3362AA,
+0xFF3463AB,
+0xFF3463AB,
+0xFF3363AB,
+0xFF3363AB,
+0xFF3363AB,
+0xFF3363AB,
+0xFF3365AE,
+0xFF3365AE,
+0xFF3365AE,
+0xFF3365AE,
+0xFF3466AF,
+0xFF3466AF,
+0xFF3567B0,
+0xFF3567B0,
+0xFF3567B0,
+0xFF3567B0,
+0xFF3567B0,
+0xFF3668B1,
+0xFF3468B1,
+0xFF3468B1,
+0xFF3468B1,
+0xFF3468B1,
+0xFF3468B1,
+0xFF3468B1,
+0xFF3468B1,
+0xFF3468B1,
+0xFF346AB4,
+0xFF346AB4,
+0xFF356BB5,
+0xFF356BB5,
+0xFF356BB5,
+0xFF356BB5,
+0xFF356BB5,
+0xFF356BB5,
+0xFF346CB6,
+0xFF346CB6,
+0xFF346CB6,
+0xFF346CB6,
+0xFF346CB6,
+0xFF346CB6,
+0xFF346CB6,
+0xFF346CB6,
+0xFF346CB6,
+0xFF346CB6,
+0xFF356DB7,
+0xFF356DB7,
+0xFF356DB7,
+0xFF356DB7,
+0xFF356DB7,
+0xFF356DB7,
+0xFF346FB5,
+0xFF346FB5,
+0xFF346FB5,
+0xFF346FB5,
+0xFF3570B6,
+0xFF3570B6,
+0xFF3570B6,
+0xFF3570B6,
+0xFF3570B6,
+0xFF3570B6,
+0xFF3570B6,
+0xFF3570B6,
+0xFF3570B6,
+0xFF3570B6,
+0xFF3570B6,
+0xFF3570B6,
+0xFF336FB5,
+0xFF3470B6,
+0xFF3470B6,
+0xFF3470B6,
+0xFF3470B6,
+0xFF3571B7,
+0xFF3571B7,
+0xFF3672B8,
+0xFF3470B6,
+0xFF3571B7,
+0xFF3571B7,
+0xFF3571B7,
+0xFF3571B7,
+0xFF3571B7,
+0xFF3571B7,
+0xFF3571B7,
+0xFF3670B9,
+0xFF3670B9,
+0xFF3670B9,
+0xFF3670B9,
+0xFF3571B9,
+0xFF3571B9,
+0xFF3571B9,
+0xFF3571B9,
+0xFF3672BA,
+0xFF3571B9,
+0xFF3571B9,
+0xFF3571B9,
+0xFF3571B9,
+0xFF3571B9,
+0xFF3571B9,
+0xFF3571B9,
+0xFF3772B8,
+0xFF3772B8,
+0xFF3772B8,
+0xFF3772B8,
+0xFF3772B8,
+0xFF3772B8,
+0xFF3672B8,
+0xFF3672B8,
+0xFF3672B8,
+0xFF3672B8,
+0xFF3672B8,
+0xFF3672B8,
+0xFF3571B7,
+0xFF3571B7,
+0xFF3571B7,
+0xFF3571B7,
+0xFF3672BA,
+0xFF3571B9,
+0xFF3470B8,
+0xFF3470B8,
+0xFF3470B8,
+0xFF3571B9,
+0xFF3672BA,
+0xFF3672BA,
+0xFF3571B9,
+0xFF3571B9,
+0xFF3571B9,
+0xFF3571B9,
+0xFF3571B9,
+0xFF3571B9,
+0xFF3571B9,
+0xFF3571B9,
+0xFF3372B9,
+0xFF3372B9,
+0xFF3372B9,
+0xFF3372B9,
+0xFF3672BA,
+0xFF3672BA,
+0xFF3672BA,
+0xFF3672BA,
+0xFF3672BA,
+0xFF3672BA,
+0xFF3672BA,
+0xFF3672BA,
+0xFF3773BB,
+0xFF3773BB,
+0xFF3773BB,
+0xFF3672BA,
+0xFF3672BA,
+0xFF3672BA,
+0xFF3672BA,
+0xFF3773BB,
+0xFF3773BB,
+0xFF3672BA,
+0xFF3672BA,
+0xFF3672BA,
+0xFF3672BA,
+0xFF3672BA,
+0xFF3773BB,
+0xFF3773BB,
+0xFF3672BA,
+0xFF3672BA,
+0xFF3773BB,
+0xFF3773BB,
+0xFF3773BB,
+0xFF3773BB,
+0xFF3773BB,
+0xFF3773BB,
+0xFF3874BC,
+0xFF3874BC,
+0xFF3874BC,
+0xFF3773BB,
+0xFF3773BB,
+0xFF3672BA,
+0xFF3672BA,
+0xFF3672BA,
+0xFF3672BA,
+0xFF3672BA,
+0xFF3773BB,
+0xFF3773BB,
+0xFF3773BB,
+0xFF3773BB,
+0xFF3773BB,
+0xFF3773BB,
+0xFF3773BC,
+0xFF3773BC,
+0xFF3773BC,
+0xFF3773BC,
+0xFF3672BB,
+0xFF3672BB,
+0xFF3773BC,
+0xFF3773BC,
+0xFF3773BC,
+0xFF3773BC,
+0xFF3773BC,
+0xFF3773BC,
+0xFF3773BC,
+0xFF3773BC,
+0xFF3773BC,
+0xFF3773BC,
+0xFF3773BC,
+0xFF3773BC,
+0xFF3773BC,
+0xFF3773BC,
+0xFF3773BC,
+0xFF3773BC,
+0xFF3773BC,
+0xFF3773BC,
+0xFF3672BB,
+0xFF3672BB,
+0xFF3672BB,
+0xFF3672BB,
+0xFF3773BC,
+0xFF3773BC,
+0xFF3672BB,
+0xFF3672BB,
+0xFF3672BB,
+0xFF3672BB,
+0xFF3672BB,
+0xFF3672BB,
+0xFF3571BA,
+0xFF3571BA,
+0xFF3571BA,
+0xFF3571BA,
+0xFF3571BA,
+0xFF3571BA,
+0xFF3571BA,
+0xFF3571BA,
+0xFF3571BA,
+0xFF3470B9,
+0xFF3470B9,
+0xFF3571BA,
+0xFF3571BA,
+0xFF3470B9,
+0xFF3470B9,
+0xFF3571BA,
+0xFF3470B9,
+0xFF336FB8,
+0xFF346EB8,
+0xFF336DB7,
+0xFF336DB7,
+0xFF336DB7,
+0xFF336DB7,
+0xFF346EB8,
+0xFF336DB7,
+0xFF336DB7,
+0xFF336DB7,
+0xFF336DB7,
+0xFF346CB6,
+0xFF336BB5,
+0xFF336BB5,
+0xFF336BB5,
+0xFF336BB5,
+0xFF336BB5,
+0xFF336BB5,
+0xFF326AB4,
+0xFF346AB4,
+0xFF346AB4,
+0xFF346AB4,
+0xFF346AB4,
+0xFF3569B4,
+0xFF3468B3,
+0xFF3468B3,
+0xFF3468B3,
+0xFF3367B2,
+0xFF3367B2,
+0xFF3266B1,
+0xFF3266B1,
+0xFF3266B1,
+0xFF3266B1,
+0xFF3266B1,
+0xFF3165B0,
+0xFF3165B0,
+0xFF3064AF,
+0xFF3064AF,
+0xFF3064AF,
+0xFF3264AD,
+0xFF3264AD,
+0xFF3264AD,
+0xFF3264AD,
+0xFF3163AC,
+0xFF3163AC,
+0xFF3163AC,
+0xFF3163AC,
+0xFF3062AB,
+0xFF3062AB,
+0xFF3062AB,
+0xFF2F61AA,
+0xFF2F61AA,
+0xFF2E60A9,
+0xFF2E60A9,
+0xFF2E60A9,
+0xFF2D5A9E,
+0xFF2E5B9F,
+0xFF2F5CA0,
+0xFF2F5CA0,
+0xFF2F5CA0,
+0xFF2F5CA0,
+0xFF2F5BA2,
+0xFF2F5BA2,
+0xFF305CA3,
+0xFF305CA3,
+0xFF305CA3,
+0xFF305CA3,
+0xFF305CA3,
+0xFF315DA4,
+0xFF315DA4,
+0xFF315DA4,
+0xFF305FA5,
+0xFF305FA5,
+0xFF3160A6,
+0xFF3160A6,
+0xFF3162A7,
+0xFF3162A7,
+0xFF3262AA,
+0xFF3262AA,
+0xFF3262AA,
+0xFF3262AA,
+0xFF3262AA,
+0xFF3262AA,
+0xFF3363AB,
+0xFF3363AB,
+0xFF3462AD,
+0xFF3462AD,
+0xFF3464AE,
+0xFF3365AE,
+0xFF3365AE,
+0xFF3365AE,
+0xFF3365AE,
+0xFF3466AF,
+0xFF3466AF,
+0xFF3466AF,
+0xFF3466AF,
+0xFF3567B0,
+0xFF3567B0,
+0xFF3567B0,
+0xFF3567B0,
+0xFF3567B0,
+0xFF3468B1,
+0xFF3569B2,
+0xFF3569B2,
+0xFF3569B2,
+0xFF3569B2,
+0xFF3569B2,
+0xFF3569B2,
+0xFF3569B2,
+0xFF3569B4,
+0xFF3569B4,
+0xFF356BB5,
+0xFF356BB5,
+0xFF356BB5,
+0xFF366CB6,
+0xFF366CB6,
+0xFF366CB6,
+0xFF366CB6,
+0xFF366CB6,
+0xFF346CB6,
+0xFF346CB6,
+0xFF346CB6,
+0xFF346CB6,
+0xFF356DB7,
+0xFF356DB7,
+0xFF356DB7,
+0xFF356DB7,
+0xFF356DB7,
+0xFF356DB7,
+0xFF356DB7,
+0xFF366EB8,
+0xFF366EB8,
+0xFF366EB8,
+0xFF356DB7,
+0xFF356DB7,
+0xFF346FB5,
+0xFF3570B6,
+0xFF3570B6,
+0xFF3570B6,
+0xFF3570B6,
+0xFF3570B6,
+0xFF3671B7,
+0xFF3570B6,
+0xFF3671B7,
+0xFF3671B7,
+0xFF3671B7,
+0xFF3671B7,
+0xFF3671B7,
+0xFF3671B7,
+0xFF3671B7,
+0xFF3671B7,
+0xFF3470B6,
+0xFF3571B7,
+0xFF3571B7,
+0xFF3672B8,
+0xFF3571B7,
+0xFF3571B7,
+0xFF3672B8,
+0xFF3672B8,
+0xFF3571B7,
+0xFF3571B7,
+0xFF3571B7,
+0xFF3571B7,
+0xFF3672B8,
+0xFF3672B8,
+0xFF3672B8,
+0xFF3672B8,
+0xFF3771BA,
+0xFF3771BA,
+0xFF3771BA,
+0xFF3771BA,
+0xFF3771BA,
+0xFF3771BA,
+0xFF3672BA,
+0xFF3672BA,
+0xFF3672BA,
+0xFF3672BA,
+0xFF3672BA,
+0xFF3672BA,
+0xFF3672BA,
+0xFF3672BA,
+0xFF3571B9,
+0xFF3571B9,
+0xFF3772B8,
+0xFF3772B8,
+0xFF3772B8,
+0xFF3772B8,
+0xFF3873B9,
+0xFF3873B9,
+0xFF3873B9,
+0xFF3873B9,
+0xFF3672B8,
+0xFF3672B8,
+0xFF3773B9,
+0xFF3773B9,
+0xFF3773B9,
+0xFF3672B8,
+0xFF3672B8,
+0xFF3672B8,
+0xFF3773BB,
+0xFF3672BA,
+0xFF3672BA,
+0xFF3672BA,
+0xFF3672BA,
+0xFF3773BB,
+0xFF3773BB,
+0xFF3672BA,
+0xFF3672BA,
+0xFF3672BA,
+0xFF3672BA,
+0xFF3672BA,
+0xFF3672BA,
+0xFF3672BA,
+0xFF3672BA,
+0xFF3773BB,
+0xFF3574BB,
+0xFF3473BA,
+0xFF3473BA,
+0xFF3473BA,
+0xFF3773BB,
+0xFF3773BB,
+0xFF3773BB,
+0xFF3773BB,
+0xFF3773BB,
+0xFF3773BB,
+0xFF3773BB,
+0xFF3773BB,
+0xFF3973BC,
+0xFF3973BC,
+0xFF3973BC,
+0xFF3872BB,
+0xFF3973BC,
+0xFF3872BB,
+0xFF3872BB,
+0xFF3872BB,
+0xFF3872BB,
+0xFF3872BB,
+0xFF3872BB,
+0xFF3872BB,
+0xFF3771BA,
+0xFF3872BB,
+0xFF3872BB,
+0xFF3872BB,
+0xFF3872BB,
+0xFF3872BB,
+0xFF3872BB,
+0xFF3973BC,
+0xFF3874BC,
+0xFF3773BB,
+0xFF3773BB,
+0xFF3773BB,
+0xFF3874BC,
+0xFF3874BC,
+0xFF3874BC,
+0xFF3773BB,
+0xFF3773BB,
+0xFF3773BB,
+0xFF3773BB,
+0xFF3773BB,
+0xFF3773BB,
+0xFF3874BC,
+0xFF3773BB,
+0xFF3773BB,
+0xFF3973BD,
+0xFF3973BD,
+0xFF3973BD,
+0xFF3973BD,
+0xFF3973BD,
+0xFF3973BD,
+0xFF3973BD,
+0xFF3973BD,
+0xFF3872BC,
+0xFF3872BC,
+0xFF3872BC,
+0xFF3973BD,
+0xFF3973BD,
+0xFF3973BD,
+0xFF3973BD,
+0xFF3872BC,
+0xFF3874BD,
+0xFF3874BD,
+0xFF3874BD,
+0xFF3874BD,
+0xFF3874BD,
+0xFF3874BD,
+0xFF3874BD,
+0xFF3773BC,
+0xFF3773BC,
+0xFF3773BC,
+0xFF3773BC,
+0xFF3773BC,
+0xFF3773BC,
+0xFF3773BC,
+0xFF3773BC,
+0xFF3773BC,
+0xFF3773BC,
+0xFF3773BC,
+0xFF3773BC,
+0xFF3773BC,
+0xFF3773BC,
+0xFF3773BC,
+0xFF3773BC,
+0xFF3773BC,
+0xFF3672BB,
+0xFF3672BB,
+0xFF3672BB,
+0xFF3672BB,
+0xFF3672BB,
+0xFF3672BB,
+0xFF3672BB,
+0xFF3672BB,
+0xFF3472BB,
+0xFF3371BA,
+0xFF3571BA,
+0xFF3571BA,
+0xFF3571BA,
+0xFF3470B9,
+0xFF3470B9,
+0xFF3571BA,
+0xFF3571BA,
+0xFF3470B9,
+0xFF356FB9,
+0xFF346EB8,
+0xFF346EB8,
+0xFF346EB8,
+0xFF346EB8,
+0xFF346EB8,
+0xFF346EB8,
+0xFF346EB8,
+0xFF346EB8,
+0xFF336DB7,
+0xFF336DB6,
+0xFF326CB5,
+0xFF346CB6,
+0xFF346CB6,
+0xFF346CB6,
+0xFF346CB6,
+0xFF346CB6,
+0xFF336BB5,
+0xFF336BB5,
+0xFF326AB4,
+0xFF346AB4,
+0xFF346AB4,
+0xFF346AB4,
+0xFF346AB4,
+0xFF3369B3,
+0xFF3369B3,
+0xFF3468B3,
+0xFF3367B2,
+0xFF3367B2,
+0xFF3367B2,
+0xFF3266B1,
+0xFF3367B2,
+0xFF3367B2,
+0xFF3266B1,
+0xFF3165B0,
+0xFF3165B0,
+0xFF3165B0,
+0xFF3165B0,
+0xFF3365AE,
+0xFF3365AE,
+0xFF3264AD,
+0xFF3264AD,
+0xFF3264AD,
+0xFF3264AD,
+0xFF3264AD,
+0xFF3163AC,
+0xFF3163AC,
+0xFF3062AB,
+0xFF3062AB,
+0xFF3062AB,
+0xFF2F61AA,
+0xFF2F61AA,
+0xFF2E60A9,
+0xFF2E60A9,
+0xFF2E5B9F,
+0xFF2E5B9F,
+0xFF2F5CA0,
+0xFF2F5CA0,
+0xFF2F5CA0,
+0xFF2F5CA0,
+0xFF2F5BA2,
+0xFF2E5AA1,
+0xFF315DA4,
+0xFF315DA4,
+0xFF315DA4,
+0xFF315DA4,
+0xFF315DA4,
+0xFF315DA4,
+0xFF325EA5,
+0xFF325EA5,
+0xFF305FA5,
+0xFF3160A6,
+0xFF3160A6,
+0xFF3261A7,
+0xFF3162A7,
+0xFF3263A8,
+0xFF3262AA,
+0xFF3262AA,
+0xFF3262AA,
+0xFF3262AA,
+0xFF3363AB,
+0xFF3363AB,
+0xFF3363AB,
+0xFF3363AB,
+0xFF3563AE,
+0xFF3464AE,
+0xFF3464AE,
+0xFF3365AE,
+0xFF3365AE,
+0xFF3466AF,
+0xFF3466AF,
+0xFF3466AF,
+0xFF3466AF,
+0xFF3567B0,
+0xFF3567B0,
+0xFF3567B0,
+0xFF3668B1,
+0xFF3668B1,
+0xFF3567B0,
+0xFF3668B1,
+0xFF3468B1,
+0xFF3569B2,
+0xFF366AB3,
+0xFF366AB3,
+0xFF366AB3,
+0xFF366AB3,
+0xFF366AB3,
+0xFF366AB3,
+0xFF366AB5,
+0xFF356BB5,
+0xFF366CB6,
+0xFF366CB6,
+0xFF366CB6,
+0xFF366CB6,
+0xFF366CB6,
+0xFF366CB6,
+0xFF366CB6,
+0xFF346CB6,
+0xFF346CB6,
+0xFF346CB6,
+0xFF346CB6,
+0xFF356DB7,
+0xFF356DB7,
+0xFF356DB7,
+0xFF366EB8,
+0xFF366EB8,
+0xFF366EB8,
+0xFF366EB8,
+0xFF366EB8,
+0xFF366EB8,
+0xFF366EB8,
+0xFF366EB8,
+0xFF366EB8,
+0xFF366EB8,
+0xFF3570B6,
+0xFF3570B6,
+0xFF3570B6,
+0xFF3671B7,
+0xFF3671B7,
+0xFF3671B7,
+0xFF3671B7,
+0xFF3671B7,
+0xFF3671B7,
+0xFF3671B7,
+0xFF3671B7,
+0xFF3671B7,
+0xFF3772B8,
+0xFF3772B8,
+0xFF3772B8,
+0xFF3772B8,
+0xFF3571B7,
+0xFF3571B7,
+0xFF3672B8,
+0xFF3672B8,
+0xFF3672B8,
+0xFF3672B8,
+0xFF3672B8,
+0xFF3672B8,
+0xFF3672B8,
+0xFF3672B8,
+0xFF3672B8,
+0xFF3672B8,
+0xFF3672B8,
+0xFF3672B8,
+0xFF3672B8,
+0xFF3672B8,
+0xFF3872BB,
+0xFF3872BB,
+0xFF3872BB,
+0xFF3872BB,
+0xFF3872BB,
+0xFF3872BB,
+0xFF3773BB,
+0xFF3773BB,
+0xFF3773BB,
+0xFF3672BA,
+0xFF3672BA,
+0xFF3672BA,
+0xFF3672BA,
+0xFF3672BA,
+0xFF3672BA,
+0xFF3571B9,
+0xFF3772B8,
+0xFF3772B8,
+0xFF3772B8,
+0xFF3772B8,
+0xFF3772B8,
+0xFF3772B8,
+0xFF3873B9,
+0xFF3873B9,
+0xFF3672B8,
+0xFF3672B8,
+0xFF3773B9,
+0xFF3773B9,
+0xFF3773B9,
+0xFF3773B9,
+0xFF3773B9,
+0xFF3773BB,
+0xFF3773BC,
+0xFF3773BB,
+0xFF3773BB,
+0xFF3773B9,
+0xFF3973BC,
+0xFF3973BC,
+0xFF3872BC,
+0xFF3771BA,
+0xFF3773BB,
+0xFF3773B9,
+0xFF3773BB,
+0xFF3773BB,
+0xFF3872BB,
+0xFF3872BB,
+0xFF3874BC,
+0xFF3874BC,
+0xFF3773BB,
+0xFF3574BB,
+0xFF3574BB,
+0xFF3574BB,
+0xFF3874BC,
+0xFF3973BC,
+0xFF3874BC,
+0xFF3574BB,
+0xFF3675BA,
+0xFF3574B9,
+0xFF3872BB,
+0xFF3973BC,
+0xFF3C72BC,
+0xFF3B73BD,
+0xFF3974BA,
+0xFF3874BA,
+0xFF3A75BB,
+0xFF3973BC,
+0xFF3973BD,
+0xFF3973BD,
+0xFF3A72BC,
+0xFF3973BC,
+0xFF3874BA,
+0xFF3874BA,
+0xFF3773BB,
+0xFF3872BB,
+0xFF3973BC,
+0xFF3973BC,
+0xFF3873B9,
+0xFF3873B9,
+0xFF3973BC,
+0xFF3874BC,
+0xFF3874BC,
+0xFF3773BB,
+0xFF3773BB,
+0xFF3773BB,
+0xFF3773BB,
+0xFF3773BB,
+0xFF3773BB,
+0xFF3672BA,
+0xFF3773BB,
+0xFF3773BB,
+0xFF3773BB,
+0xFF3874BC,
+0xFF3975BD,
+0xFF3975BD,
+0xFF3874BC,
+0xFF3773BB,
+0xFF3973BD,
+0xFF3973BD,
+0xFF3973BD,
+0xFF3973BD,
+0xFF3973BD,
+0xFF3973BD,
+0xFF3973BD,
+0xFF3973BD,
+0xFF3973BD,
+0xFF3973BD,
+0xFF3973BD,
+0xFF3A74BE,
+0xFF3A74BE,
+0xFF3A74BE,
+0xFF3A74BE,
+0xFF3A74BE,
+0xFF3874BD,
+0xFF3975BE,
+0xFF3975BE,
+0xFF3975BE,
+0xFF3975BE,
+0xFF3874BD,
+0xFF3874BD,
+0xFF3874BD,
+0xFF3874BD,
+0xFF3874BD,
+0xFF3874BD,
+0xFF3874BD,
+0xFF3874BD,
+0xFF3874BD,
+0xFF3874BD,
+0xFF3874BD,
+0xFF3874BD,
+0xFF3874BD,
+0xFF3773BC,
+0xFF3773BC,
+0xFF3773BC,
+0xFF3773BC,
+0xFF3773BC,
+0xFF3773BC,
+0xFF3773BC,
+0xFF3773BC,
+0xFF3773BC,
+0xFF3773BC,
+0xFF3773BC,
+0xFF3773BC,
+0xFF3773BC,
+0xFF3672BB,
+0xFF3672BB,
+0xFF3571BA,
+0xFF3571BA,
+0xFF3672BB,
+0xFF3571BA,
+0xFF3571BA,
+0xFF3571BA,
+0xFF3571BA,
+0xFF3672BB,
+0xFF3571BA,
+0xFF356FB9,
+0xFF356FB9,
+0xFF346EB8,
+0xFF336FB8,
+0xFF346EB8,
+0xFF346EB8,
+0xFF346EB8,
+0xFF346EB7,
+0xFF346EB8,
+0xFF346EB7,
+0xFF336DB6,
+0xFF336DB6,
+0xFF336DB6,
+0xFF356DB7,
+0xFF356DB7,
+0xFF356DB7,
+0xFF346CB6,
+0xFF346CB6,
+0xFF336BB5,
+0xFF336BB5,
+0xFF356BB5,
+0xFF346AB4,
+0xFF346AB4,
+0xFF346AB4,
+0xFF346AB4,
+0xFF3369B3,
+0xFF3468B3,
+0xFF3468B3,
+0xFF3468B3,
+0xFF3468B3,
+0xFF3367B2,
+0xFF3367B2,
+0xFF3367B2,
+0xFF3266B1,
+0xFF3165B0,
+0xFF3165B0,
+0xFF3165B0,
+0xFF3165B0,
+0xFF3365AE,
+0xFF3365AE,
+0xFF3365AE,
+0xFF3365AE,
+0xFF3264AD,
+0xFF3264AD,
+0xFF3264AD,
+0xFF3264AD,
+0xFF3163AC,
+0xFF3163AC,
+0xFF3163AC,
+0xFF3062AB,
+0xFF3062AB,
+0xFF2F61AA,
+0xFF2F61AA,
+0xFF2E60A9,
+0xFF2F5BA2,
+0xFF2F5BA2,
+0xFF2F5BA2,
+0xFF305CA3,
+0xFF305CA3,
+0xFF305CA3,
+0xFF305CA3,
+0xFF305CA3,
+0xFF305CA3,
+0xFF305CA3,
+0xFF315DA4,
+0xFF315DA4,
+0xFF305FA5,
+0xFF305FA5,
+0xFF3160A6,
+0xFF3160A6,
+0xFF3160A6,
+0xFF3261A7,
+0xFF3261A7,
+0xFF3362A8,
+0xFF3261A7,
+0xFF3362A8,
+0xFF3362AA,
+0xFF3463AB,
+0xFF3463AB,
+0xFF3463AB,
+0xFF3363AB,
+0xFF3363AB,
+0xFF3363AB,
+0xFF3464AC,
+0xFF3565AD,
+0xFF3565AD,
+0xFF3565AF,
+0xFF3565AF,
+0xFF3565AF,
+0xFF3666B0,
+0xFF3666B0,
+0xFF3666B0,
+0xFF3567B0,
+0xFF3567B0,
+0xFF3668B1,
+0xFF3668B1,
+0xFF3769B2,
+0xFF3769B2,
+0xFF3569B2,
+0xFF366AB3,
+0xFF3569B2,
+0xFF3569B2,
+0xFF356BB5,
+0xFF356BB5,
+0xFF356BB5,
+0xFF366CB6,
+0xFF366CB6,
+0xFF366CB6,
+0xFF366CB6,
+0xFF366CB6,
+0xFF376DB7,
+0xFF346CB6,
+0xFF346CB6,
+0xFF346CB6,
+0xFF356DB7,
+0xFF356DB7,
+0xFF356DB7,
+0xFF346CB6,
+0xFF356EB5,
+0xFF346FB5,
+0xFF346FB5,
+0xFF3570B6,
+0xFF3570B6,
+0xFF3570B6,
+0xFF3570B6,
+0xFF3570B6,
+0xFF3570B6,
+0xFF3570B6,
+0xFF3570B6,
+0xFF3671B7,
+0xFF3671B7,
+0xFF3671B7,
+0xFF3671B7,
+0xFF3671B7,
+0xFF3671B7,
+0xFF3671B7,
+0xFF3671B7,
+0xFF3671B7,
+0xFF3772B8,
+0xFF3772B8,
+0xFF3772B8,
+0xFF3772B8,
+0xFF3772B8,
+0xFF3772B8,
+0xFF3772B8,
+0xFF3772B8,
+0xFF3772B8,
+0xFF3772B8,
+0xFF3772B8,
+0xFF3772B8,
+0xFF3772B8,
+0xFF3772B8,
+0xFF3772B8,
+0xFF3772B8,
+0xFF3772B8,
+0xFF3772B8,
+0xFF3772B8,
+0xFF3873B9,
+0xFF3873B9,
+0xFF3873B9,
+0xFF3873B9,
+0xFF3873B9,
+0xFF3873B9,
+0xFF3873B9,
+0xFF3873B9,
+0xFF3873B9,
+0xFF3873B9,
+0xFF3873B9,
+0xFF3873B9,
+0xFF3873B9,
+0xFF3873B9,
+0xFF3873B9,
+0xFF3873B9,
+0xFF3873B9,
+0xFF3873B9,
+0xFF3873B9,
+0xFF3974BA,
+0xFF3974BA,
+0xFF3974BA,
+0xFF3974BA,
+0xFF3874BA,
+0xFF3874BA,
+0xFF3973BC,
+0xFF3973BC,
+0xFF3973BC,
+0xFF3973BC,
+0xFF3973BC,
+0xFF3973BC,
+0xFF3973BC,
+0xFF3973BC,
+0xFF3973BC,
+0xFF3973BC,
+0xFF3874BC,
+0xFF3874BC,
+0xFF3874BC,
+0xFF3874BC,
+0xFF3874BC,
+0xFF3874BD,
+0xFF3674BF,
+0xFF3674BD,
+0xFF3675BA,
+0xFF3875B8,
+0xFF3A72BC,
+0xFF3A72BD,
+0xFF3C71BF,
+0xFF3A72BD,
+0xFF3672B8,
+0xFF3976B9,
+0xFF3975BB,
+0xFF3772B8,
+0xFF3D73BD,
+0xFF3E73BF,
+0xFF3470B9,
+0xFF3A76BF,
+0xFF3873B9,
+0xFF3571B7,
+0xFF3776BD,
+0xFF3574BB,
+0xFF3871B8,
+0xFF3B74BB,
+0xFF3573BC,
+0xFF3676BD,
+0xFF3478B9,
+0xFF3576B8,
+0xFF3871B8,
+0xFF3E72BD,
+0xFF3F6FBB,
+0xFF3D6FB8,
+0xFF3A75B9,
+0xFF3574B7,
+0xFF3B76B8,
+0xFF3770B7,
+0xFF3871C0,
+0xFF3A71C1,
+0xFF3E73BF,
+0xFF3B74BB,
+0xFF3271B4,
+0xFF3778BA,
+0xFF3574BB,
+0xFF3874BD,
+0xFF3A72BC,
+0xFF3A73BA,
+0xFF3873B5,
+0xFF3774B5,
+0xFF3874BA,
+0xFF3874BC,
+0xFF3874BC,
+0xFF3975BD,
+0xFF3975BD,
+0xFF3874BC,
+0xFF3874BC,
+0xFF3975BD,
+0xFF3A76BE,
+0xFF3975BD,
+0xFF3975BD,
+0xFF3975BD,
+0xFF3975BD,
+0xFF3975BD,
+0xFF3975BD,
+0xFF3975BD,
+0xFF3975BD,
+0xFF3975BD,
+0xFF3874BC,
+0xFF3874BC,
+0xFF3975BD,
+0xFF3975BD,
+0xFF3975BD,
+0xFF3975BD,
+0xFF3975BD,
+0xFF3975BD,
+0xFF3975BD,
+0xFF3975BD,
+0xFF3A74BD,
+0xFF3A74BD,
+0xFF3A74BD,
+0xFF3A74BD,
+0xFF3A74BD,
+0xFF3973BC,
+0xFF3874BC,
+0xFF3975BD,
+0xFF3A76BE,
+0xFF3A76BE,
+0xFF3975BD,
+0xFF3975BD,
+0xFF3874BC,
+0xFF3874BC,
+0xFF3975BD,
+0xFF3975BD,
+0xFF3975BD,
+0xFF3975BD,
+0xFF3874BC,
+0xFF3874BC,
+0xFF3874BC,
+0xFF3975BD,
+0xFF3874BC,
+0xFF3874BC,
+0xFF3874BC,
+0xFF3874BC,
+0xFF3874BC,
+0xFF3874BC,
+0xFF3874BC,
+0xFF3874BC,
+0xFF3874BC,
+0xFF3773BB,
+0xFF3773BB,
+0xFF3773BB,
+0xFF3874BC,
+0xFF3874BC,
+0xFF3773BB,
+0xFF3773BB,
+0xFF3773BB,
+0xFF3872BB,
+0xFF3872BB,
+0xFF3872BB,
+0xFF3771BA,
+0xFF3771BA,
+0xFF3672BA,
+0xFF3672BA,
+0xFF3672BA,
+0xFF3571B9,
+0xFF3571B9,
+0xFF3571B9,
+0xFF3571B9,
+0xFF3271B8,
+0xFF3470B8,
+0xFF3470B8,
+0xFF356FB8,
+0xFF346FB5,
+0xFF346EB7,
+0xFF346EB7,
+0xFF336FB7,
+0xFF336FB7,
+0xFF336FB7,
+0xFF346EB7,
+0xFF336DB6,
+0xFF336DB6,
+0xFF336DB6,
+0xFF336DB6,
+0xFF346CB6,
+0xFF346CB6,
+0xFF366CB6,
+0xFF366CB6,
+0xFF346CB6,
+0xFF336BB5,
+0xFF326AB4,
+0xFF326AB4,
+0xFF3369B3,
+0xFF3369B3,
+0xFF3369B3,
+0xFF346AB4,
+0xFF3468B3,
+0xFF3468B3,
+0xFF3566B2,
+0xFF3566B2,
+0xFF3567B0,
+0xFF3466AF,
+0xFF3466AF,
+0xFF3466AF,
+0xFF3466AF,
+0xFF3466AF,
+0xFF3365AE,
+0xFF3365AE,
+0xFF3264AD,
+0xFF3264AD,
+0xFF3363AD,
+0xFF3363AD,
+0xFF3363AB,
+0xFF3363AB,
+0xFF3262AA,
+0xFF3262AA,
+0xFF3161A9,
+0xFF3161A9,
+0xFF3161A9,
+0xFF3060A8,
+0xFF2F5BA2,
+0xFF2F5BA2,
+0xFF305CA3,
+0xFF305CA3,
+0xFF305CA3,
+0xFF305CA3,
+0xFF305CA3,
+0xFF305CA3,
+0xFF305CA3,
+0xFF315DA4,
+0xFF325EA5,
+0xFF325EA5,
+0xFF305FA5,
+0xFF3160A6,
+0xFF3261A7,
+0xFF3261A7,
+0xFF3362A8,
+0xFF3362A8,
+0xFF3463A9,
+0xFF3463A9,
+0xFF3362A8,
+0xFF3362A8,
+0xFF3463AB,
+0xFF3463AB,
+0xFF3564AC,
+0xFF3564AC,
+0xFF3464AC,
+0xFF3464AC,
+0xFF3464AC,
+0xFF3565AD,
+0xFF3565AD,
+0xFF3666AE,
+0xFF3565AF,
+0xFF3666B0,
+0xFF3666B0,
+0xFF3666B0,
+0xFF3767B1,
+0xFF3767B1,
+0xFF3668B1,
+0xFF3668B1,
+0xFF3668B1,
+0xFF3769B2,
+0xFF3769B2,
+0xFF386AB3,
+0xFF366AB3,
+0xFF366AB3,
+0xFF366AB3,
+0xFF366AB3,
+0xFF356BB5,
+0xFF356BB5,
+0xFF366CB6,
+0xFF366CB6,
+0xFF366CB6,
+0xFF366CB6,
+0xFF366CB6,
+0xFF366CB6,
+0xFF346CB6,
+0xFF346CB6,
+0xFF346CB6,
+0xFF356DB7,
+0xFF366EB8,
+0xFF366EB8,
+0xFF366EB8,
+0xFF356DB7,
+0xFF3570B6,
+0xFF3570B6,
+0xFF3570B6,
+0xFF3570B6,
+0xFF3570B6,
+0xFF3570B6,
+0xFF3671B7,
+0xFF3671B7,
+0xFF3671B7,
+0xFF3671B7,
+0xFF3671B7,
+0xFF3772B8,
+0xFF3772B8,
+0xFF3772B8,
+0xFF3772B8,
+0xFF3772B8,
+0xFF3772B8,
+0xFF3772B8,
+0xFF3772B8,
+0xFF3772B8,
+0xFF3772B8,
+0xFF3772B8,
+0xFF3772B8,
+0xFF3772B8,
+0xFF3772B8,
+0xFF3772B8,
+0xFF3873B9,
+0xFF3873B9,
+0xFF3873B9,
+0xFF3873B9,
+0xFF3873B9,
+0xFF3873B9,
+0xFF3873B9,
+0xFF3873B9,
+0xFF3873B9,
+0xFF3873B9,
+0xFF3873B9,
+0xFF3873B9,
+0xFF3873B9,
+0xFF3873B9,
+0xFF3873B9,
+0xFF3873B9,
+0xFF3873B9,
+0xFF3873B9,
+0xFF3873B9,
+0xFF3873B9,
+0xFF3873B9,
+0xFF3873B9,
+0xFF3974BA,
+0xFF3974BA,
+0xFF3974BA,
+0xFF3974BA,
+0xFF3974BA,
+0xFF3974BA,
+0xFF3974BA,
+0xFF3974BA,
+0xFF3974BA,
+0xFF3974BA,
+0xFF3974BA,
+0xFF3974BA,
+0xFF3974BA,
+0xFF3974BA,
+0xFF3874BA,
+0xFF3874BA,
+0xFF3973BC,
+0xFF3973BC,
+0xFF3973BC,
+0xFF3973BC,
+0xFF3973BC,
+0xFF3973BC,
+0xFF3973BC,
+0xFF3973BC,
+0xFF3973BC,
+0xFF3973BC,
+0xFF3874BC,
+0xFF3874BC,
+0xFF3874BC,
+0xFF3874BC,
+0xFF3874BC,
+0xFF3874BD,
+0xFF3873BF,
+0xFF3674BD,
+0xFF3675B8,
+0xFF3875B8,
+0xFF3974BA,
+0xFF3A72BD,
+0xFF3C71BF,
+0xFF3A72BD,
+0xFF3874BC,
+0xFF3A79C0,
+0xFF3473B8,
+0xFF3B76BC,
+0xFF3F70BC,
+0xFF3E6FBB,
+0xFF3F75BF,
+0xFF3D73BB,
+0xFF4173B8,
+0xFF4475B8,
+0xFF3A6BAE,
+0xFF4873B7,
+0xFF5270B0,
+0xFF4C68A7,
+0xFF4B6EAE,
+0xFF466FAD,
+0xFF4974AB,
+0xFF5378AD,
+0xFF5C75AB,
+0xFF5A6FA6,
+0xFF566EAA,
+0xFF4F72B2,
+0xFF4077B8,
+0xFF3576B8,
+0xFF3572B5,
+0xFF3E79BF,
+0xFF3B74C3,
+0xFF3A73C4,
+0xFF366EB9,
+0xFF3772B8,
+0xFF3E7DC0,
+0xFF3475B7,
+0xFF3776BD,
+0xFF3775BE,
+0xFF3A74BD,
+0xFF3A75BB,
+0xFF3A75B7,
+0xFF3976B9,
+0xFF3975BD,
+0xFF3975BE,
+0xFF3975BD,
+0xFF3975BD,
+0xFF3975BD,
+0xFF3975BD,
+0xFF3975BD,
+0xFF3A76BE,
+0xFF3A76BE,
+0xFF3975BD,
+0xFF3975BD,
+0xFF3975BD,
+0xFF3975BD,
+0xFF3975BD,
+0xFF3975BD,
+0xFF3975BD,
+0xFF3975BD,
+0xFF3975BD,
+0xFF3975BD,
+0xFF3975BD,
+0xFF3975BD,
+0xFF3975BD,
+0xFF3A76BE,
+0xFF3A76BE,
+0xFF3A76BE,
+0xFF3A76BE,
+0xFF3975BD,
+0xFF3975BD,
+0xFF3A74BD,
+0xFF3A74BD,
+0xFF3A74BD,
+0xFF3A74BD,
+0xFF3A74BD,
+0xFF3A74BD,
+0xFF3975BD,
+0xFF3A76BE,
+0xFF3A76BE,
+0xFF3A76BE,
+0xFF3A76BE,
+0xFF3975BD,
+0xFF3975BD,
+0xFF3975BD,
+0xFF3975BD,
+0xFF3A76BE,
+0xFF3A76BE,
+0xFF3975BD,
+0xFF3975BD,
+0xFF3874BC,
+0xFF3975BD,
+0xFF3975BD,
+0xFF3975BD,
+0xFF3975BD,
+0xFF3975BD,
+0xFF3874BC,
+0xFF3874BC,
+0xFF3874BC,
+0xFF3975BD,
+0xFF3975BD,
+0xFF3874BC,
+0xFF3874BC,
+0xFF3874BC,
+0xFF3874BC,
+0xFF3874BC,
+0xFF3874BC,
+0xFF3874BC,
+0xFF3773BB,
+0xFF3973BC,
+0xFF3973BC,
+0xFF3973BC,
+0xFF3872BB,
+0xFF3872BB,
+0xFF3872BB,
+0xFF3773BB,
+0xFF3672BA,
+0xFF3571B9,
+0xFF3571B9,
+0xFF3571B9,
+0xFF3571B9,
+0xFF3372B9,
+0xFF3372B9,
+0xFF3372B9,
+0xFF3571B9,
+0xFF3671B7,
+0xFF3671B7,
+0xFF3570B6,
+0xFF3570B6,
+0xFF3470B8,
+0xFF3470B8,
+0xFF336FB7,
+0xFF336FB7,
+0xFF346EB7,
+0xFF346EB7,
+0xFF346EB7,
+0xFF346EB7,
+0xFF346CB6,
+0xFF346CB6,
+0xFF366CB6,
+0xFF366CB6,
+0xFF346CB6,
+0xFF336BB5,
+0xFF336BB5,
+0xFF326AB4,
+0xFF346AB4,
+0xFF346AB4,
+0xFF346AB4,
+0xFF346AB4,
+0xFF3468B3,
+0xFF3468B3,
+0xFF3667B3,
+0xFF3566B2,
+0xFF3567B0,
+0xFF3567B0,
+0xFF3466AF,
+0xFF3466AF,
+0xFF3466AF,
+0xFF3466AF,
+0xFF3466AF,
+0xFF3365AE,
+0xFF3365AE,
+0xFF3365AE,
+0xFF3464AE,
+0xFF3464AE,
+0xFF3363AB,
+0xFF3363AB,
+0xFF3363AB,
+0xFF3262AA,
+0xFF3262AA,
+0xFF3262AA,
+0xFF3261A9,
+0xFF3261A9,
+0xFF2F5BA2,
+0xFF305CA3,
+0xFF305CA3,
+0xFF305CA3,
+0xFF315DA4,
+0xFF315DA4,
+0xFF315DA4,
+0xFF315DA4,
+0xFF315DA4,
+0xFF325EA5,
+0xFF3160A6,
+0xFF3160A6,
+0xFF3261A7,
+0xFF3261A7,
+0xFF3362A8,
+0xFF3463A9,
+0xFF3463A9,
+0xFF3463A9,
+0xFF3564AA,
+0xFF3564AA,
+0xFF3463A9,
+0xFF3463A9,
+0xFF3463AB,
+0xFF3564AC,
+0xFF3565AD,
+0xFF3565AD,
+0xFF3565AD,
+0xFF3565AD,
+0xFF3565AD,
+0xFF3666AE,
+0xFF3666AE,
+0xFF3666AE,
+0xFF3666B0,
+0xFF3767B1,
+0xFF3767B1,
+0xFF3767B1,
+0xFF3668B1,
+0xFF3769B2,
+0xFF3769B2,
+0xFF3769B2,
+0xFF3569B2,
+0xFF366AB3,
+0xFF366AB3,
+0xFF366AB3,
+0xFF376BB4,
+0xFF376BB4,
+0xFF376BB4,
+0xFF376BB4,
+0xFF366CB6,
+0xFF366CB6,
+0xFF366CB6,
+0xFF376DB7,
+0xFF376DB7,
+0xFF376DB7,
+0xFF356DB7,
+0xFF356DB7,
+0xFF356DB7,
+0xFF356DB7,
+0xFF356DB7,
+0xFF356DB7,
+0xFF366EB8,
+0xFF376FB9,
+0xFF376FB9,
+0xFF366EB8,
+0xFF3671B7,
+0xFF3671B7,
+0xFF3671B7,
+0xFF3671B7,
+0xFF3671B7,
+0xFF3671B7,
+0xFF3772B8,
+0xFF3772B8,
+0xFF3772B8,
+0xFF3772B8,
+0xFF3873B9,
+0xFF3873B9,
+0xFF3873B9,
+0xFF3873B9,
+0xFF3873B9,
+0xFF3873B9,
+0xFF3873B9,
+0xFF3873B9,
+0xFF3873B9,
+0xFF3873B9,
+0xFF3873B9,
+0xFF3974BA,
+0xFF3974BA,
+0xFF3974BA,
+0xFF3873B9,
+0xFF3873B9,
+0xFF3974BA,
+0xFF3974BA,
+0xFF3974BA,
+0xFF3974BA,
+0xFF3974BA,
+0xFF3974BA,
+0xFF3974BA,
+0xFF3974BA,
+0xFF3974BA,
+0xFF3974BA,
+0xFF3974BA,
+0xFF3974BA,
+0xFF3974BA,
+0xFF3A75BB,
+0xFF3974BA,
+0xFF3974BA,
+0xFF3974BA,
+0xFF3974BA,
+0xFF3974BA,
+0xFF3974BA,
+0xFF3974BA,
+0xFF3974BA,
+0xFF3A75BB,
+0xFF3A75BB,
+0xFF3A75BB,
+0xFF3974BA,
+0xFF3974BA,
+0xFF3A75BB,
+0xFF3A75BB,
+0xFF3A75BB,
+0xFF3974BA,
+0xFF3974BA,
+0xFF3874BA,
+0xFF3874BA,
+0xFF3874BA,
+0xFF3975BB,
+0xFF3975BB,
+0xFF3975BB,
+0xFF3A74BD,
+0xFF3A74BD,
+0xFF3A74BD,
+0xFF3A74BD,
+0xFF3A74BD,
+0xFF3A74BD,
+0xFF3975BD,
+0xFF3975BD,
+0xFF3975BD,
+0xFF3975BD,
+0xFF3975BD,
+0xFF3975BD,
+0xFF3975BD,
+0xFF3975BD,
+0xFF3975BD,
+0xFF3A74BD,
+0xFF3B73BD,
+0xFF3B74BB,
+0xFF3975BB,
+0xFF3976B9,
+0xFF3776BB,
+0xFF3975BB,
+0xFF3B73BD,
+0xFF3B73BE,
+0xFF3876C1,
+0xFF3274C0,
+0xFF3274BE,
+0xFF3A76BF,
+0xFF3F6FB7,
+0xFF3F69B1,
+0xFF4670B8,
+0xFF426AB0,
+0xFF476DAE,
+0xFF4D6CAC,
+0xFF566BAC,
+0xFF6165A2,
+0xFF7A6397,
+0xFF866B98,
+0xFF8474A3,
+0xFF6E6592,
+0xFF50456D,
+0xFF3E2948,
+0xFF4C2538,
+0xFF472233,
+0xFF1F0F2A,
+0xFF55628C,
+0xFF4072AD,
+0xFF3477BD,
+0xFF3B7BC3,
+0xFF3270B9,
+0xFF3B74C1,
+0xFF3B74C1,
+0xFF3A76BF,
+0xFF3E7AC2,
+0xFF3874BC,
+0xFF3975BD,
+0xFF3B77C0,
+0xFF3A76BF,
+0xFF3877BE,
+0xFF3877BE,
+0xFF3A76BE,
+0xFF3B75BE,
+0xFF3C74C1,
+0xFF3C74C1,
+0xFF3A74BE,
+0xFF3B75BE,
+0xFF3B75BE,
+0xFF3A74BD,
+0xFF3A74BD,
+0xFF3B75BE,
+0xFF3B75BE,
+0xFF3B75BE,
+0xFF3B75BE,
+0xFF3B75BE,
+0xFF3B75BE,
+0xFF3A74BD,
+0xFF3B75BE,
+0xFF3B75BE,
+0xFF3B75BE,
+0xFF3B75BE,
+0xFF3A76BE,
+0xFF3A76BE,
+0xFF3A76BE,
+0xFF3A76BE,
+0xFF3B75BE,
+0xFF3B75BE,
+0xFF3C76BF,
+0xFF3C76BF,
+0xFF3B75BE,
+0xFF3B75BE,
+0xFF3B75BE,
+0xFF3B75BE,
+0xFF3B75BE,
+0xFF3B75BE,
+0xFF3B75BE,
+0xFF3B75BE,
+0xFF3B75BE,
+0xFF3B75BE,
+0xFF3C76BF,
+0xFF3C76BF,
+0xFF3B75BE,
+0xFF3B75BE,
+0xFF3B75BE,
+0xFF3B75BE,
+0xFF3B75BE,
+0xFF3B75BE,
+0xFF3B75BE,
+0xFF3B75BE,
+0xFF3B75BE,
+0xFF3B75BE,
+0xFF3B75BE,
+0xFF3B75BE,
+0xFF3B75BE,
+0xFF3B75BE,
+0xFF3B75BE,
+0xFF3B75BE,
+0xFF3B75BE,
+0xFF3B75BE,
+0xFF3B75BE,
+0xFF3B75BE,
+0xFF3A74BD,
+0xFF3A74BD,
+0xFF3A74BD,
+0xFF3A74BD,
+0xFF3A74BD,
+0xFF3A74BD,
+0xFF3A74BD,
+0xFF3973BC,
+0xFF3A74BD,
+0xFF3A74BD,
+0xFF3973BC,
+0xFF3973BC,
+0xFF3973BC,
+0xFF3973BC,
+0xFF3973BC,
+0xFF3872BB,
+0xFF3672BA,
+0xFF3672BA,
+0xFF3672BA,
+0xFF3672BA,
+0xFF3672BA,
+0xFF3672BA,
+0xFF3773BB,
+0xFF3773BB,
+0xFF3873B9,
+0xFF3772B8,
+0xFF3772B8,
+0xFF3671B7,
+0xFF3571B9,
+0xFF3470B8,
+0xFF3470B8,
+0xFF336FB7,
+0xFF356FB8,
+0xFF356FB8,
+0xFF346EB7,
+0xFF346EB7,
+0xFF356DB7,
+0xFF356DB7,
+0xFF356DB7,
+0xFF346CB6,
+0xFF346CB6,
+0xFF346CB6,
+0xFF346CB6,
+0xFF346CB6,
+0xFF336BB5,
+0xFF336BB5,
+0xFF356BB5,
+0xFF356BB5,
+0xFF3569B4,
+0xFF3569B4,
+0xFF3468B3,
+0xFF3468B3,
+0xFF3668B1,
+0xFF3567B0,
+0xFF3567B0,
+0xFF3567B0,
+0xFF3567B0,
+0xFF3567B0,
+0xFF3567B0,
+0xFF3466AF,
+0xFF3466AF,
+0xFF3466AF,
+0xFF3365AE,
+0xFF3365AE,
+0xFF3464AC,
+0xFF3464AC,
+0xFF3464AC,
+0xFF3363AB,
+0xFF3363AB,
+0xFF3262AA,
+0xFF3262AA,
+0xFF3262AA,
+0xFF305CA3,
+0xFF305CA3,
+0xFF305CA3,
+0xFF305CA3,
+0xFF315DA4,
+0xFF315DA4,
+0xFF325EA5,
+0xFF325EA5,
+0xFF325EA5,
+0xFF335FA6,
+0xFF3261A7,
+0xFF3261A7,
+0xFF3362A8,
+0xFF3362A8,
+0xFF3463A9,
+0xFF3564AA,
+0xFF3463A9,
+0xFF3463A9,
+0xFF3463A9,
+0xFF3463A9,
+0xFF3463A9,
+0xFF3463A9,
+0xFF3564AC,
+0xFF3564AC,
+0xFF3565AD,
+0xFF3565AD,
+0xFF3565AD,
+0xFF3565AD,
+0xFF3666AE,
+0xFF3666AE,
+0xFF3767AF,
+0xFF3767AF,
+0xFF3767B1,
+0xFF3767B1,
+0xFF3767B1,
+0xFF3769B2,
+0xFF3769B2,
+0xFF3769B2,
+0xFF3769B2,
+0xFF3769B2,
+0xFF366AB3,
+0xFF366AB3,
+0xFF366AB3,
+0xFF376BB4,
+0xFF376BB4,
+0xFF376BB4,
+0xFF376BB4,
+0xFF376BB4,
+0xFF366CB6,
+0xFF366CB6,
+0xFF366CB6,
+0xFF376DB7,
+0xFF376DB7,
+0xFF376DB7,
+0xFF356DB7,
+0xFF356DB7,
+0xFF356DB7,
+0xFF356DB7,
+0xFF366EB8,
+0xFF366EB8,
+0xFF376FB9,
+0xFF376FB9,
+0xFF376FB9,
+0xFF376FB9,
+0xFF3671B7,
+0xFF3772B8,
+0xFF3772B8,
+0xFF3772B8,
+0xFF3772B8,
+0xFF3772B8,
+0xFF3772B8,
+0xFF3772B8,
+0xFF3873B9,
+0xFF3873B9,
+0xFF3873B9,
+0xFF3974BA,
+0xFF3974BA,
+0xFF3974BA,
+0xFF3974BA,
+0xFF3974BA,
+0xFF3974BA,
+0xFF3974BA,
+0xFF3974BA,
+0xFF3974BA,
+0xFF3974BA,
+0xFF3974BA,
+0xFF3974BA,
+0xFF3974BA,
+0xFF3974BA,
+0xFF3974BA,
+0xFF3974BA,
+0xFF3974BA,
+0xFF3974BA,
+0xFF3A75BB,
+0xFF3A75BB,
+0xFF3A75BB,
+0xFF3A75BB,
+0xFF3A75BB,
+0xFF3A75BB,
+0xFF3A75BB,
+0xFF3A75BB,
+0xFF3A75BB,
+0xFF3A75BB,
+0xFF3A75BB,
+0xFF3A75BB,
+0xFF3A75BB,
+0xFF3A75BB,
+0xFF3A75BB,
+0xFF3A75BB,
+0xFF3A75BB,
+0xFF3A75BB,
+0xFF3A75BB,
+0xFF3A75BB,
+0xFF3A75BB,
+0xFF3A75BB,
+0xFF3A75BB,
+0xFF3A75BB,
+0xFF3A75BB,
+0xFF3A75BB,
+0xFF3A75BB,
+0xFF3A75BB,
+0xFF3A75BB,
+0xFF3975BB,
+0xFF3975BB,
+0xFF3975BB,
+0xFF3975BB,
+0xFF3975BB,
+0xFF3975BB,
+0xFF3A74BD,
+0xFF3A74BD,
+0xFF3A74BD,
+0xFF3A74BD,
+0xFF3A74BD,
+0xFF3A74BD,
+0xFF3975BD,
+0xFF3975BD,
+0xFF3975BD,
+0xFF3975BD,
+0xFF3975BD,
+0xFF3975BD,
+0xFF3975BD,
+0xFF3975BD,
+0xFF3975BD,
+0xFF3A75BB,
+0xFF3E74BA,
+0xFF3E74BA,
+0xFF3B76BC,
+0xFF3A76BC,
+0xFF3A76BC,
+0xFF3A76BC,
+0xFF3B75BE,
+0xFF3C74BE,
+0xFF3E74BC,
+0xFF4675B9,
+0xFF5276B4,
+0xFF5871A9,
+0xFF636EA4,
+0xFF7172A8,
+0xFF6F6AA0,
+0xFF7E74A8,
+0xFF8672A3,
+0xFF886C9C,
+0xFF8C6695,
+0xFF90608A,
+0xFF905778,
+0xFF8D5270,
+0xFF582242,
+0xFF2F0016,
+0xFF460C22,
+0xFF64202B,
+0xFF6C1B18,
+0xFF540D07,
+0xFF300C0E,
+0xFF110E23,
+0xFF5C78AA,
+0xFF4576B9,
+0xFF3771BA,
+0xFF3B79C2,
+0xFF3C76BF,
+0xFF3D77C0,
+0xFF3878C0,
+0xFF3575BD,
+0xFF3C78C0,
+0xFF3A74BD,
+0xFF3C76C0,
+0xFF3A76BF,
+0xFF3876BF,
+0xFF3777BF,
+0xFF3B77C0,
+0xFF3C75C2,
+0xFF3D75C2,
+0xFF3C74C1,
+0xFF3B75BF,
+0xFF3B75BE,
+0xFF3B75BE,
+0xFF3B75BE,
+0xFF3B75BE,
+0xFF3B75BE,
+0xFF3C76BF,
+0xFF3C76BF,
+0xFF3B75BE,
+0xFF3B75BE,
+0xFF3B75BE,
+0xFF3B75BE,
+0xFF3B75BE,
+0xFF3B75BE,
+0xFF3C76BF,
+0xFF3C76BF,
+0xFF3B77BF,
+0xFF3B77BF,
+0xFF3B77BF,
+0xFF3B77BF,
+0xFF3C76BF,
+0xFF3C76BF,
+0xFF3C76BF,
+0xFF3C76BF,
+0xFF3C76BF,
+0xFF3C76BF,
+0xFF3C76BF,
+0xFF3C76BF,
+0xFF3C76BF,
+0xFF3C76BF,
+0xFF3C76BF,
+0xFF3C76BF,
+0xFF3B75BE,
+0xFF3C76BF,
+0xFF3C76BF,
+0xFF3C76BF,
+0xFF3C76BF,
+0xFF3B75BE,
+0xFF3C76BF,
+0xFF3C76BF,
+0xFF3C76BF,
+0xFF3C76BF,
+0xFF3C76BF,
+0xFF3B75BE,
+0xFF3B75BE,
+0xFF3B75BE,
+0xFF3B75BE,
+0xFF3C76BF,
+0xFF3C76BF,
+0xFF3C76BF,
+0xFF3C76BF,
+0xFF3C76BF,
+0xFF3C76BF,
+0xFF3C76BF,
+0xFF3C76BF,
+0xFF3B75BE,
+0xFF3B75BE,
+0xFF3A74BD,
+0xFF3A74BD,
+0xFF3A74BD,
+0xFF3B75BE,
+0xFF3B75BE,
+0xFF3A74BD,
+0xFF3A74BD,
+0xFF3A74BD,
+0xFF3A74BD,
+0xFF3A74BD,
+0xFF3A74BD,
+0xFF3A74BD,
+0xFF3973BC,
+0xFF3973BC,
+0xFF3973BC,
+0xFF3975BD,
+0xFF3975BD,
+0xFF3874BC,
+0xFF3874BC,
+0xFF3874BC,
+0xFF3773BB,
+0xFF3773BB,
+0xFF3773BB,
+0xFF3873B9,
+0xFF3873B9,
+0xFF3772B8,
+0xFF3772B8,
+0xFF3672BA,
+0xFF3571B9,
+0xFF3470B8,
+0xFF3470B8,
+0xFF356FB8,
+0xFF356FB8,
+0xFF356FB8,
+0xFF356FB8,
+0xFF356DB7,
+0xFF356DB7,
+0xFF356DB7,
+0xFF356DB7,
+0xFF346CB6,
+0xFF346CB6,
+0xFF346CB6,
+0xFF346CB6,
+0xFF346CB6,
+0xFF346CB6,
+0xFF356BB5,
+0xFF356BB5,
+0xFF3569B4,
+0xFF3569B4,
+0xFF3569B4,
+0xFF3569B4,
+0xFF3668B1,
+0xFF3668B1,
+0xFF3668B1,
+0xFF3668B1,
+0xFF3668B1,
+0xFF3567B0,
+0xFF3567B0,
+0xFF3567B0,
+0xFF3466AF,
+0xFF3466AF,
+0xFF3466AF,
+0xFF3466AF,
+0xFF3464AC,
+0xFF3464AC,
+0xFF3464AC,
+0xFF3464AC,
+0xFF3363AB,
+0xFF3363AB,
+0xFF3363AB,
+0xFF3363AB,
+0xFF305CA3,
+0xFF305CA3,
+0xFF305CA3,
+0xFF315DA4,
+0xFF315DA4,
+0xFF325EA5,
+0xFF305FA5,
+0xFF3160A6,
+0xFF3160A6,
+0xFF3261A7,
+0xFF3261A7,
+0xFF3362A8,
+0xFF3362A8,
+0xFF3463A9,
+0xFF3564AA,
+0xFF3564AA,
+0xFF3362A8,
+0xFF3463A9,
+0xFF3463A9,
+0xFF3564AA,
+0xFF3465AA,
+0xFF3465AA,
+0xFF3464AC,
+0xFF3565AD,
+0xFF3565AD,
+0xFF3565AD,
+0xFF3666AE,
+0xFF3666AE,
+0xFF3666AE,
+0xFF3767AF,
+0xFF3668B1,
+0xFF3668B1,
+0xFF3668B1,
+0xFF3769B2,
+0xFF3769B2,
+0xFF3769B2,
+0xFF386AB3,
+0xFF366AB3,
+0xFF366AB3,
+0xFF366AB3,
+0xFF366AB3,
+0xFF366AB3,
+0xFF366CB4,
+0xFF366CB4,
+0xFF366CB4,
+0xFF366CB4,
+0xFF366CB4,
+0xFF366CB4,
+0xFF366CB4,
+0xFF366CB4,
+0xFF356EB5,
+0xFF356EB5,
+0xFF356EB5,
+0xFF366FB6,
+0xFF366FB6,
+0xFF366FB6,
+0xFF366FB6,
+0xFF366FB6,
+0xFF3770B7,
+0xFF3770B7,
+0xFF3770B7,
+0xFF3770B7,
+0xFF3770B7,
+0xFF3770B7,
+0xFF3871B8,
+0xFF3871B8,
+0xFF3871B8,
+0xFF3871B8,
+0xFF3972B9,
+0xFF3972B9,
+0xFF3873B9,
+0xFF3873B9,
+0xFF3974BA,
+0xFF3974BA,
+0xFF3974BA,
+0xFF3974BA,
+0xFF3974BA,
+0xFF3974BA,
+0xFF3974BA,
+0xFF3974BA,
+0xFF3974BA,
+0xFF3974BA,
+0xFF3974BA,
+0xFF3974BA,
+0xFF3A75BB,
+0xFF3A75BB,
+0xFF3A75BB,
+0xFF3A75BB,
+0xFF3974BA,
+0xFF3974BA,
+0xFF3A74BD,
+0xFF3A74BD,
+0xFF3A74BD,
+0xFF3A74BD,
+0xFF3A74BD,
+0xFF3A74BD,
+0xFF3A75BB,
+0xFF3A75BB,
+0xFF3A75BB,
+0xFF3A75BB,
+0xFF3A75BB,
+0xFF3A75BB,
+0xFF3A75BB,
+0xFF3B76BC,
+0xFF3A75BB,
+0xFF3A75BB,
+0xFF3A75BB,
+0xFF3A75BB,
+0xFF3A75BB,
+0xFF3A75BB,
+0xFF3A75BB,
+0xFF3A75BB,
+0xFF3B75BE,
+0xFF3A74BD,
+0xFF3A74BD,
+0xFF3A74BD,
+0xFF3A74BD,
+0xFF3A74BD,
+0xFF3975BD,
+0xFF3A76BE,
+0xFF3A76BE,
+0xFF3A76BE,
+0xFF3A76BE,
+0xFF3A76BE,
+0xFF3A76BE,
+0xFF3A76BE,
+0xFF3A76BE,
+0xFF3A76BE,
+0xFF3A76BE,
+0xFF3A76BE,
+0xFF3A76BE,
+0xFF3A76BE,
+0xFF3A76BE,
+0xFF3A76BE,
+0xFF3A76BE,
+0xFF3A76BE,
+0xFF3A76BE,
+0xFF3A76BE,
+0xFF3A76BE,
+0xFF3A76BE,
+0xFF3A76BE,
+0xFF3A76BE,
+0xFF3A76BE,
+0xFF3B76BC,
+0xFF3C75BA,
+0xFF3E74BA,
+0xFF3B75BE,
+0xFF3C74BE,
+0xFF3F73BC,
+0xFF3E74BE,
+0xFF3876C1,
+0xFF3C75BA,
+0xFF476BA7,
+0xFF3E4474,
+0xFF644766,
+0xFF875169,
+0xFF9A5B70,
+0xFFAC6376,
+0xFFB56372,
+0xFFBD5B6A,
+0xFFBC4656,
+0xFFB53544,
+0xFFAC2939,
+0xFFAC3C4A,
+0xFF954955,
+0xFF470715,
+0xFF440007,
+0xFF640C18,
+0xFF6D0A0D,
+0xFF760F0A,
+0xFF8B2018,
+0xFF7C281D,
+0xFF3F1B0D,
+0xFF0F0506,
+0xFF383153,
+0xFF6B78AF,
+0xFF4575B7,
+0xFF3F7EC3,
+0xFF3972B7,
+0xFF3A75BB,
+0xFF3A7AC4,
+0xFF3375BF,
+0xFF3B76BC,
+0xFF3E77BC,
+0xFF3D75BF,
+0xFF3B75BF,
+0xFF3A76BF,
+0xFF3876C1,
+0xFF3977C2,
+0xFF3B76C2,
+0xFF3D75C2,
+0xFF3D75C2,
+0xFF3C76C0,
+0xFF3C76BF,
+0xFF3C76BF,
+0xFF3C76BF,
+0xFF3C76BF,
+0xFF3C76BF,
+0xFF3C76BF,
+0xFF3D77C0,
+0xFF3C76BF,
+0xFF3C76BF,
+0xFF3C76BF,
+0xFF3C76BF,
+0xFF3C76BF,
+0xFF3C76BF,
+0xFF3C76BF,
+0xFF3C76BF,
+0xFF3B77BF,
+0xFF3B77BF,
+0xFF3B77BF,
+0xFF3B77BF,
+0xFF3B77BF,
+0xFF3B77BF,
+0xFF3B77BF,
+0xFF3B77BF,
+0xFF3C76BF,
+0xFF3C76BF,
+0xFF3C76BF,
+0xFF3C76BF,
+0xFF3C76BF,
+0xFF3C76BF,
+0xFF3C76BF,
+0xFF3C76BF,
+0xFF3B77BF,
+0xFF3B77BF,
+0xFF3B77BF,
+0xFF3B77BF,
+0xFF3B77BF,
+0xFF3B77BF,
+0xFF3B77BF,
+0xFF3C78C0,
+0xFF3B77BF,
+0xFF3B77BF,
+0xFF3B77BF,
+0xFF3B77BF,
+0xFF3B77BF,
+0xFF3B77BF,
+0xFF3B77BF,
+0xFF3B77BF,
+0xFF3C76BF,
+0xFF3C76BF,
+0xFF3C76BF,
+0xFF3C76BF,
+0xFF3C76BF,
+0xFF3C76BF,
+0xFF3C76BF,
+0xFF3C76BF,
+0xFF3B75BE,
+0xFF3B75BE,
+0xFF3B75BE,
+0xFF3B75BE,
+0xFF3B75BE,
+0xFF3B75BE,
+0xFF3B75BE,
+0xFF3A74BD,
+0xFF3B75BE,
+0xFF3B75BE,
+0xFF3A74BD,
+0xFF3A74BD,
+0xFF3A74BD,
+0xFF3A74BD,
+0xFF3A74BD,
+0xFF3A74BD,
+0xFF3A74BD,
+0xFF3A74BD,
+0xFF3A74BD,
+0xFF3A74BD,
+0xFF3973BC,
+0xFF3973BC,
+0xFF3973BC,
+0xFF3872BB,
+0xFF3873B9,
+0xFF3873B9,
+0xFF3873B9,
+0xFF3873B9,
+0xFF3872BB,
+0xFF3771BA,
+0xFF3670B9,
+0xFF3670B9,
+0xFF3670B9,
+0xFF3670B9,
+0xFF356FB8,
+0xFF356FB8,
+0xFF356FB8,
+0xFF346EB7,
+0xFF346EB7,
+0xFF346EB7,
+0xFF346EB7,
+0xFF346EB7,
+0xFF356DB7,
+0xFF356DB7,
+0xFF346CB6,
+0xFF346CB6,
+0xFF336BB5,
+0xFF336BB5,
+0xFF356BB5,
+0xFF356BB5,
+0xFF366AB5,
+0xFF366AB5,
+0xFF3569B2,
+0xFF3569B2,
+0xFF3569B2,
+0xFF3569B2,
+0xFF3668B1,
+0xFF3668B1,
+0xFF3567B0,
+0xFF3567B0,
+0xFF3567B0,
+0xFF3466AF,
+0xFF3466AF,
+0xFF3466AF,
+0xFF3466AD,
+0xFF3466AD,
+0xFF3464AC,
+0xFF3464AC,
+0xFF3464AC,
+0xFF3363AB,
+0xFF3363AB,
+0xFF3363AB,
+0xFF315DA4,
+0xFF315DA4,
+0xFF315DA4,
+0xFF315DA4,
+0xFF325EA5,
+0xFF335FA6,
+0xFF3160A6,
+0xFF3261A7,
+0xFF3261A7,
+0xFF3362A8,
+0xFF3362A8,
+0xFF3463A9,
+0xFF3463A9,
+0xFF3463A9,
+0xFF3564AA,
+0xFF3564AA,
+0xFF3463A9,
+0xFF3564AA,
+0xFF3564AA,
+0xFF3665AB,
+0xFF3566AB,
+0xFF3566AB,
+0xFF3666AE,
+0xFF3666AE,
+0xFF3666AE,
+0xFF3666AE,
+0xFF3666AE,
+0xFF3767AF,
+0xFF3767AF,
+0xFF3767AF,
+0xFF3668B1,
+0xFF3668B1,
+0xFF3769B2,
+0xFF3769B2,
+0xFF386AB3,
+0xFF366AB3,
+0xFF366AB3,
+0xFF366AB3,
+0xFF366AB3,
+0xFF366AB3,
+0xFF376BB4,
+0xFF366CB4,
+0xFF366CB4,
+0xFF376DB5,
+0xFF376DB5,
+0xFF376DB5,
+0xFF366CB4,
+0xFF366CB4,
+0xFF376DB5,
+0xFF376DB5,
+0xFF356EB5,
+0xFF366FB6,
+0xFF366FB6,
+0xFF366FB6,
+0xFF366FB6,
+0xFF366FB6,
+0xFF3770B7,
+0xFF3770B7,
+0xFF3871B8,
+0xFF3871B8,
+0xFF3871B8,
+0xFF3770B7,
+0xFF3871B8,
+0xFF3871B8,
+0xFF3972B9,
+0xFF3972B9,
+0xFF3972B9,
+0xFF3972B9,
+0xFF3972B9,
+0xFF3A73BA,
+0xFF3974BA,
+0xFF3974BA,
+0xFF3974BA,
+0xFF3974BA,
+0xFF3A75BB,
+0xFF3A75BB,
+0xFF3A75BB,
+0xFF3A75BB,
+0xFF3A75BB,
+0xFF3A75BB,
+0xFF3A75BB,
+0xFF3A75BB,
+0xFF3A75BB,
+0xFF3A75BB,
+0xFF3A75BB,
+0xFF3A75BB,
+0xFF3A75BB,
+0xFF3A75BB,
+0xFF3A75BB,
+0xFF3A75BB,
+0xFF3A74BD,
+0xFF3A74BD,
+0xFF3A74BD,
+0xFF3A74BD,
+0xFF3A74BD,
+0xFF3A74BD,
+0xFF3B76BC,
+0xFF3B76BC,
+0xFF3A75BB,
+0xFF3A75BB,
+0xFF3A75BB,
+0xFF3B76BC,
+0xFF3B76BC,
+0xFF3B76BC,
+0xFF3B76BC,
+0xFF3B76BC,
+0xFF3B76BC,
+0xFF3B76BC,
+0xFF3B76BC,
+0xFF3B76BC,
+0xFF3B76BC,
+0xFF3B76BC,
+0xFF3B75BE,
+0xFF3B75BE,
+0xFF3B75BE,
+0xFF3B75BE,
+0xFF3B75BE,
+0xFF3B75BE,
+0xFF3A76BE,
+0xFF3A76BE,
+0xFF3A76BE,
+0xFF3A76BE,
+0xFF3A76BE,
+0xFF3B77BF,
+0xFF3B77BF,
+0xFF3B77BF,
+0xFF3B77BF,
+0xFF3B77BF,
+0xFF3B77BF,
+0xFF3B77BF,
+0xFF3B77BF,
+0xFF3B77BF,
+0xFF3B77BF,
+0xFF3B77BF,
+0xFF3B77BF,
+0xFF3B77BF,
+0xFF3B77BF,
+0xFF3B77BF,
+0xFF3B77BF,
+0xFF3B77BF,
+0xFF3B77BF,
+0xFF3B77BF,
+0xFF3B77BF,
+0xFF3B77BD,
+0xFF3C77BB,
+0xFF3C77BB,
+0xFF3C76BF,
+0xFF3C76C0,
+0xFF3F75BF,
+0xFF3D75C0,
+0xFF3878C2,
+0xFF3C77BD,
+0xFF5579B5,
+0xFF404370,
+0xFF42162F,
+0xFF6D1D2A,
+0xFF730E14,
+0xFF770304,
+0xFF790000,
+0xFF940A08,
+0xFFB21617,
+0xFFCD3134,
+0xFFCC3B42,
+0xFF9E2931,
+0xFF5B0E14,
+0xFF7F3A3F,
+0xFF9B4047,
+0xFFB64C50,
+0xFFBE4F48,
+0xFFC65A4D,
+0xFF9E3F2B,
+0xFF98573B,
+0xFFAF9972,
+0xFF5C5539,
+0xFF2B141C,
+0xFF32284B,
+0xFF5B7BAE,
+0xFF3D73B1,
+0xFF3E75B8,
+0xFF3E79BF,
+0xFF3777BF,
+0xFF3979C1,
+0xFF3E79BD,
+0xFF3C75B8,
+0xFF3E77BE,
+0xFF3D75BF,
+0xFF3B77C0,
+0xFF3977C2,
+0xFF3A78C3,
+0xFF3A78C1,
+0xFF3C78C1,
+0xFF3D77C0,
+0xFF3D77C0,
+0xFF3C76BF,
+0xFF3C76BF,
+0xFF3D77C0,
+0xFF3D77C0,
+0xFF3D77C0,
+0xFF3D77C0,
+0xFF3D77C0,
+0xFF3D77C0,
+0xFF3D77C0,
+0xFF3D77C0,
+0xFF3D77C0,
+0xFF3D77C0,
+0xFF3D77C0,
+0xFF3D77C0,
+0xFF3C78C0,
+0xFF3C78C0,
+0xFF3C78C0,
+0xFF3C78C0,
+0xFF3C78C0,
+0xFF3C78C0,
+0xFF3C78C0,
+0xFF3C78C0,
+0xFF3C78C0,
+0xFF3C78C0,
+0xFF3C78C0,
+0xFF3D77C0,
+0xFF3C78C0,
+0xFF3D77C0,
+0xFF3C78C0,
+0xFF3D77C0,
+0xFF3C78C0,
+0xFF3C78C0,
+0xFF3C78C0,
+0xFF3C78C0,
+0xFF3C78C0,
+0xFF3B77BF,
+0xFF3B77BF,
+0xFF3C78C0,
+0xFF3C78C0,
+0xFF3C78C0,
+0xFF3C78C0,
+0xFF3B77BF,
+0xFF3B77BF,
+0xFF3B77BF,
+0xFF3C78C0,
+0xFF3C78C0,
+0xFF3B77BF,
+0xFF3C76BF,
+0xFF3C76BF,
+0xFF3D77C0,
+0xFF3D77C0,
+0xFF3D77C0,
+0xFF3D77C0,
+0xFF3C76BF,
+0xFF3C76BF,
+0xFF3C76BF,
+0xFF3C76BF,
+0xFF3B75BE,
+0xFF3C76BF,
+0xFF3C76BF,
+0xFF3C76BF,
+0xFF3C76BF,
+0xFF3B75BE,
+0xFF3B75BE,
+0xFF3B75BE,
+0xFF3B75BE,
+0xFF3B75BE,
+0xFF3B75BE,
+0xFF3B75BE,
+0xFF3B75BE,
+0xFF3B75BE,
+0xFF3973BC,
+0xFF3973BC,
+0xFF3973BC,
+0xFF3973BC,
+0xFF3973BC,
+0xFF3A74BD,
+0xFF3A74BD,
+0xFF3A74BD,
+0xFF3873B9,
+0xFF3873B9,
+0xFF3873B9,
+0xFF3873B9,
+0xFF3973BC,
+0xFF3872BB,
+0xFF3771BA,
+0xFF3771BA,
+0xFF3771BA,
+0xFF3771BA,
+0xFF3670B9,
+0xFF3670B9,
+0xFF356FB8,
+0xFF356FB8,
+0xFF356FB8,
+0xFF356FB8,
+0xFF346EB7,
+0xFF346EB7,
+0xFF356DB7,
+0xFF356DB7,
+0xFF356DB7,
+0xFF346CB6,
+0xFF346CB6,
+0xFF346CB6,
+0xFF366CB6,
+0xFF366CB6,
+0xFF376BB6,
+0xFF366AB5,
+0xFF366AB3,
+0xFF366AB3,
+0xFF3569B2,
+0xFF3569B2,
+0xFF3668B1,
+0xFF3668B1,
+0xFF3668B1,
+0xFF3567B0,
+0xFF3567B0,
+0xFF3567B0,
+0xFF3567B0,
+0xFF3567B0,
+0xFF3466AD,
+0xFF3466AD,
+0xFF3565AD,
+0xFF3565AD,
+0xFF3464AC,
+0xFF3464AC,
+0xFF3464AC,
+0xFF3464AC,
+0xFF305FA5,
+0xFF305FA5,
+0xFF305FA5,
+0xFF305FA5,
+0xFF3160A6,
+0xFF3261A7,
+0xFF3362A8,
+0xFF3362A8,
+0xFF3362A8,
+0xFF3463A9,
+0xFF3463A9,
+0xFF3463A9,
+0xFF3463A9,
+0xFF3463A9,
+0xFF3564AA,
+0xFF3564AA,
+0xFF3465AA,
+0xFF3566AB,
+0xFF3566AB,
+0xFF3566AB,
+0xFF3565AD,
+0xFF3666AE,
+0xFF3666AE,
+0xFF3767AF,
+0xFF3567AE,
+0xFF3668AF,
+0xFF3668AF,
+0xFF3769B0,
+0xFF3769B0,
+0xFF3769B0,
+0xFF3769B2,
+0xFF3769B2,
+0xFF366AB3,
+0xFF366AB3,
+0xFF366AB3,
+0xFF376BB4,
+0xFF376BB4,
+0xFF366CB4,
+0xFF366CB4,
+0xFF366CB4,
+0xFF366CB4,
+0xFF376DB5,
+0xFF376DB5,
+0xFF356EB5,
+0xFF356EB5,
+0xFF356EB5,
+0xFF356EB5,
+0xFF356EB5,
+0xFF366FB6,
+0xFF366FB6,
+0xFF366FB6,
+0xFF3770B7,
+0xFF3770B7,
+0xFF3770B7,
+0xFF3871B8,
+0xFF3871B8,
+0xFF3871B8,
+0xFF3871B8,
+0xFF3972B9,
+0xFF3972B9,
+0xFF3972B9,
+0xFF3972B9,
+0xFF3972B9,
+0xFF3A73BA,
+0xFF3A73BA,
+0xFF3A73BA,
+0xFF3A73BA,
+0xFF3A73BA,
+0xFF3A73BA,
+0xFF3B74BB,
+0xFF3A75BB,
+0xFF3A75BB,
+0xFF3A75BB,
+0xFF3A75BB,
+0xFF3A75BB,
+0xFF3A75BB,
+0xFF3A75BB,
+0xFF3A75BB,
+0xFF3A75BB,
+0xFF3A75BB,
+0xFF3A75BB,
+0xFF3A75BB,
+0xFF3A75BB,
+0xFF3A75BB,
+0xFF3A75BB,
+0xFF3B76BC,
+0xFF3B76BC,
+0xFF3B76BC,
+0xFF3A74BD,
+0xFF3A74BD,
+0xFF3A74BD,
+0xFF3A74BD,
+0xFF3B75BE,
+0xFF3B75BE,
+0xFF3B75BE,
+0xFF3B75BE,
+0xFF3A76BE,
+0xFF3A76BE,
+0xFF3A76BE,
+0xFF3A76BE,
+0xFF3A76BE,
+0xFF3A76BE,
+0xFF3A76BE,
+0xFF3B77BF,
+0xFF3B77BF,
+0xFF3B77BF,
+0xFF3B77BF,
+0xFF3B77BF,
+0xFF3B77BF,
+0xFF3B77BF,
+0xFF3B77BF,
+0xFF3B77BF,
+0xFF3B77BF,
+0xFF3B77BF,
+0xFF3B77BF,
+0xFF3A76BE,
+0xFF3A76BE,
+0xFF3B77BF,
+0xFF3B77BF,
+0xFF3B77BF,
+0xFF3B77BF,
+0xFF3B77BF,
+0xFF3B77BF,
+0xFF3B77BF,
+0xFF3B77BF,
+0xFF3B77BF,
+0xFF3B77BF,
+0xFF3B77BF,
+0xFF3B77BD,
+0xFF3B77BD,
+0xFF3B77BD,
+0xFF3B77BD,
+0xFF3B77BD,
+0xFF3B77BD,
+0xFF3B77BD,
+0xFF3B77BD,
+0xFF3978BD,
+0xFF3978BD,
+0xFF3978BD,
+0xFF3978BD,
+0xFF3978BD,
+0xFF3978BD,
+0xFF3978BD,
+0xFF3978BD,
+0xFF397ABC,
+0xFF397ABE,
+0xFF3A78C1,
+0xFF3A78C3,
+0xFF3A78C1,
+0xFF3A78C1,
+0xFF3979C1,
+0xFF3A79C0,
+0xFF3A75BB,
+0xFF5779B6,
+0xFF605782,
+0xFF57213B,
+0xFFA03640,
+0xFFBA3A39,
+0xFFB33332,
+0xFFA42423,
+0xFF961615,
+0xFF811218,
+0xFF742238,
+0xFF82425A,
+0xFFAF7281,
+0xFFAF6870,
+0xFFAF4F53,
+0xFFB04648,
+0xFFA03F39,
+0xFF631604,
+0xFF582A06,
+0xFF8C7B45,
+0xFF869047,
+0xFF7B8445,
+0xFF614D32,
+0xFF281519,
+0xFF333E5A,
+0xFF5A7EB0,
+0xFF4479BB,
+0xFF3270B9,
+0xFF427EC4,
+0xFF3A77BA,
+0xFF3976B9,
+0xFF407BBD,
+0xFF4077BA,
+0xFF3E77BC,
+0xFF3A78C1,
+0xFF3979C3,
+0xFF3A78C1,
+0xFF3A79C0,
+0xFF397ABC,
+0xFF3B7ABD,
+0xFF3D79BF,
+0xFF3C78BE,
+0xFF3C78BE,
+0xFF3D79BF,
+0xFF3D79BF,
+0xFF3C78BE,
+0xFF3C78BE,
+0xFF3D79BF,
+0xFF3C78BE,
+0xFF3C78BE,
+0xFF3C78BE,
+0xFF3C78BE,
+0xFF3C78BE,
+0xFF3C78BE,
+0xFF3D79BF,
+0xFF3D79BF,
+0xFF3D79BF,
+0xFF3B7ABF,
+0xFF3B7ABF,
+0xFF3B7ABF,
+0xFF3B7ABF,
+0xFF3B7ABF,
+0xFF3B7ABF,
+0xFF3B7ABF,
+0xFF3A79BE,
+0xFF3A79BE,
+0xFF3C78BE,
+0xFF3A79BE,
+0xFF3C78BE,
+0xFF3A79BE,
+0xFF3C78BE,
+0xFF3A79BE,
+0xFF3A79BE,
+0xFF3B7ABF,
+0xFF3B7ABF,
+0xFF3A79BE,
+0xFF3A79BE,
+0xFF3A79BE,
+0xFF3B7ABF,
+0xFF3B7ABF,
+0xFF3B7ABF,
+0xFF3A79BE,
+0xFF3A79BE,
+0xFF3A79BE,
+0xFF3A79BE,
+0xFF3B7ABF,
+0xFF3A79BE,
+0xFF3A79BE,
+0xFF3B77BF,
+0xFF3C78C0,
+0xFF3C78C0,
+0xFF3D79C1,
+0xFF3D79C1,
+0xFF3C78C0,
+0xFF3C78C0,
+0xFF3C78C0,
+0xFF3C78C0,
+0xFF3C78C0,
+0xFF3B77BF,
+0xFF3C78C0,
+0xFF3C78C0,
+0xFF3C78C0,
+0xFF3B77BF,
+0xFF3B77BF,
+0xFF3B77BF,
+0xFF3B77BF,
+0xFF3B77BF,
+0xFF3B77BF,
+0xFF3B77BF,
+0xFF3B77BF,
+0xFF3C76BF,
+0xFF3C76BF,
+0xFF3A74BD,
+0xFF3A74BD,
+0xFF3A74BD,
+0xFF3A74BD,
+0xFF3B73BD,
+0xFF3B73BD,
+0xFF3B73BD,
+0xFF3B73BD,
+0xFF3974BA,
+0xFF3974BA,
+0xFF3974BA,
+0xFF3A75BB,
+0xFF3A74BD,
+0xFF3973BC,
+0xFF3872BB,
+0xFF3872BB,
+0xFF3872BB,
+0xFF3872BB,
+0xFF3872BB,
+0xFF3771BA,
+0xFF3771BA,
+0xFF3670B9,
+0xFF3670B9,
+0xFF3670B9,
+0xFF356FB8,
+0xFF356FB8,
+0xFF356FB8,
+0xFF346EB7,
+0xFF346EB7,
+0xFF346EB7,
+0xFF356DB7,
+0xFF356DB7,
+0xFF356DB7,
+0xFF356DB7,
+0xFF366CB6,
+0xFF366CB6,
+0xFF366CB4,
+0xFF356BB3,
+0xFF356BB3,
+0xFF356BB3,
+0xFF3569B2,
+0xFF3569B2,
+0xFF3569B2,
+0xFF3468B1,
+0xFF3668B1,
+0xFF3668B1,
+0xFF3567B0,
+0xFF3567B0,
+0xFF3567B0,
+0xFF3567B0,
+0xFF3567AE,
+0xFF3466AD,
+0xFF3565AD,
+0xFF3565AD,
+0xFF3565AD,
+0xFF3565AD,
+0xFF305FA5,
+0xFF305FA5,
+0xFF305FA5,
+0xFF3160A6,
+0xFF3261A7,
+0xFF3362A8,
+0xFF3463A9,
+0xFF3463A9,
+0xFF3463A9,
+0xFF3564AA,
+0xFF3564AA,
+0xFF3564AA,
+0xFF3564AA,
+0xFF3564AA,
+0xFF3564AA,
+0xFF3665AB,
+0xFF3566AB,
+0xFF3566AB,
+0xFF3667AC,
+0xFF3667AC,
+0xFF3565AD,
+0xFF3565AD,
+0xFF3666AE,
+0xFF3666AE,
+0xFF3668AF,
+0xFF3668AF,
+0xFF3769B0,
+0xFF386AB1,
+0xFF386AB1,
+0xFF386AB1,
+0xFF386AB3,
+0xFF366AB3,
+0xFF376BB4,
+0xFF376BB4,
+0xFF376BB4,
+0xFF376BB4,
+0xFF376DB5,
+0xFF376DB5,
+0xFF376DB5,
+0xFF376DB5,
+0xFF376DB5,
+0xFF376DB5,
+0xFF366FB6,
+0xFF366FB6,
+0xFF366FB6,
+0xFF366FB6,
+0xFF366FB6,
+0xFF366FB6,
+0xFF3770B7,
+0xFF3770B7,
+0xFF3770B7,
+0xFF3871B8,
+0xFF3871B8,
+0xFF3871B8,
+0xFF3871B8,
+0xFF3871B8,
+0xFF3871B8,
+0xFF3972B9,
+0xFF3A73BA,
+0xFF3A73BA,
+0xFF3A73BA,
+0xFF3A73BA,
+0xFF3A73BA,
+0xFF3B74BB,
+0xFF3A73BA,
+0xFF3A73BA,
+0xFF3B74BB,
+0xFF3B74BB,
+0xFF3B74BB,
+0xFF3B74BB,
+0xFF3B76BC,
+0xFF3B76BC,
+0xFF3A75BB,
+0xFF3B76BC,
+0xFF3B76BC,
+0xFF3B76BC,
+0xFF3B76BC,
+0xFF3B76BC,
+0xFF3B76BC,
+0xFF3B76BC,
+0xFF3B76BC,
+0xFF3B76BC,
+0xFF3B76BC,
+0xFF3B76BC,
+0xFF3B76BC,
+0xFF3B76BC,
+0xFF3B76BC,
+0xFF3B76BC,
+0xFF3B75BE,
+0xFF3B75BE,
+0xFF3B75BE,
+0xFF3B75BE,
+0xFF3B75BE,
+0xFF3B75BE,
+0xFF3B75BE,
+0xFF3B75BE,
+0xFF3B77BF,
+0xFF3B77BF,
+0xFF3A76BE,
+0xFF3A76BE,
+0xFF3A76BE,
+0xFF3B77BF,
+0xFF3B77BF,
+0xFF3B77BF,
+0xFF3B77BF,
+0xFF3B77BF,
+0xFF3B77BF,
+0xFF3B77BF,
+0xFF3B77BF,
+0xFF3B77BF,
+0xFF3B77BF,
+0xFF3B77BF,
+0xFF3B77BF,
+0xFF3B77BF,
+0xFF3B77BF,
+0xFF3B77BF,
+0xFF3B77BF,
+0xFF3B77BF,
+0xFF3B77BF,
+0xFF3B77BF,
+0xFF3B77BF,
+0xFF3B77BF,
+0xFF3B77BF,
+0xFF3B77BF,
+0xFF3B77BF,
+0xFF3C78C0,
+0xFF3C78C0,
+0xFF3C78C0,
+0xFF3C78BE,
+0xFF3C78BE,
+0xFF3C78BE,
+0xFF3C78BE,
+0xFF3C78BE,
+0xFF3C78BE,
+0xFF3C78BE,
+0xFF3C78BE,
+0xFF3A79BE,
+0xFF3A79BE,
+0xFF3A79BE,
+0xFF3A79BE,
+0xFF3A79BE,
+0xFF3A79BE,
+0xFF3A79BE,
+0xFF397ABE,
+0xFF377AC0,
+0xFF377AC0,
+0xFF3A79C0,
+0xFF3A79C0,
+0xFF3979C1,
+0xFF3979C3,
+0xFF3A78C1,
+0xFF3979C1,
+0xFF377BC4,
+0xFF3E75B8,
+0xFF5D73AC,
+0xFF776289,
+0xFF5C0F21,
+0xFF902328,
+0xFF9C2527,
+0xFFA53132,
+0xFFA43D40,
+0xFF722A38,
+0xFF8D7295,
+0xFF291337,
+0xFF4C1221,
+0xFF5D070A,
+0xFF780C0C,
+0xFF6F0200,
+0xFF670E00,
+0xFF470C00,
+0xFF9A874F,
+0xFF7F8A3C,
+0xFF799036,
+0xFF758431,
+0xFF938852,
+0xFF34220A,
+0xFF1C141F,
+0xFF455177,
+0xFF4F79B5,
+0xFF417ABF,
+0xFF3C77BB,
+0xFF3D7ABD,
+0xFF3F7CBD,
+0xFF3A77B8,
+0xFF3C77B9,
+0xFF3C79BC,
+0xFF3979C1,
+0xFF377AC1,
+0xFF3979C0,
+0xFF397ABC,
+0xFF397ABA,
+0xFF3A7BBB,
+0xFF3B7ABD,
+0xFF3A79BE,
+0xFF3C78BE,
+0xFF3B7ABF,
+0xFF3D79BF,
+0xFF3A79BE,
+0xFF3C78BE,
+0xFF3C7BC0,
+0xFF3D79BF,
+0xFF3B7ABF,
+0xFF3C78BE,
+0xFF3A79BE,
+0xFF3D79BF,
+0xFF3B7ABF,
+0xFF3D79BF,
+0xFF3B7ABF,
+0xFF3B7ABF,
+0xFF3A7BBF,
+0xFF3B7ABF,
+0xFF3A7BBF,
+0xFF3B7ABF,
+0xFF3A7BBF,
+0xFF3B7ABF,
+0xFF3B7ABF,
+0xFF3A79BE,
+0xFF3A79BE,
+0xFF3A79BE,
+0xFF3A79BE,
+0xFF3A79BE,
+0xFF3A79BE,
+0xFF3A79BE,
+0xFF3A79BE,
+0xFF3B7ABF,
+0xFF3A7BBF,
+0xFF3B7ABF,
+0xFF3A7BBF,
+0xFF3B7ABF,
+0xFF3A7BBF,
+0xFF3C7BC0,
+0xFF3B7CC0,
+0xFF3B7ABF,
+0xFF3A7BBF,
+0xFF3A79BE,
+0xFF397ABE,
+0xFF3B7ABF,
+0xFF3A7BBF,
+0xFF3B7ABF,
+0xFF3B7ABF,
+0xFF3A79C0,
+0xFF3A79C0,
+0xFF3D79C1,
+0xFF3B7AC1,
+0xFF3D79C1,
+0xFF3B7AC1,
+0xFF3C78C0,
+0xFF3A79C0,
+0xFF3D79C1,
+0xFF3A79C0,
+0xFF3C78C0,
+0xFF3A79C0,
+0xFF3D79C1,
+0xFF3B7AC1,
+0xFF3C78C0,
+0xFF3C78C0,
+0xFF3C78C0,
+0xFF3C78C0,
+0xFF3C78C0,
+0xFF3C78C0,
+0xFF3B77BF,
+0xFF3B77BF,
+0xFF3C76BF,
+0xFF3C76BF,
+0xFF3C76BF,
+0xFF3C76BF,
+0xFF3C76BF,
+0xFF3B75BE,
+0xFF3C74BE,
+0xFF3C74BE,
+0xFF3B73BD,
+0xFF3B73BD,
+0xFF3A75BB,
+0xFF3A75BB,
+0xFF3A75BB,
+0xFF3A75BB,
+0xFF3B75BE,
+0xFF3A74BD,
+0xFF3973BC,
+0xFF3872BB,
+0xFF3973BC,
+0xFF3973BC,
+0xFF3872BB,
+0xFF3872BB,
+0xFF3771BA,
+0xFF3771BA,
+0xFF3771BA,
+0xFF3670B9,
+0xFF3670B9,
+0xFF3670B9,
+0xFF356FB8,
+0xFF356FB8,
+0xFF346EB7,
+0xFF356FB8,
+0xFF366EB8,
+0xFF366EB8,
+0xFF356DB7,
+0xFF356DB7,
+0xFF376DB7,
+0xFF366CB6,
+0xFF366CB4,
+0xFF366CB4,
+0xFF356BB3,
+0xFF356BB3,
+0xFF366AB3,
+0xFF366AB3,
+0xFF3569B2,
+0xFF3569B2,
+0xFF3668B1,
+0xFF3668B1,
+0xFF3668B1,
+0xFF3668B1,
+0xFF3668B1,
+0xFF3567B0,
+0xFF3567AE,
+0xFF3567AE,
+0xFF3666AE,
+0xFF3666AE,
+0xFF3565AD,
+0xFF3565AD,
+0xFF3261A7,
+0xFF3261A7,
+0xFF3362A8,
+0xFF3362A8,
+0xFF3463A9,
+0xFF3463A9,
+0xFF3463A9,
+0xFF3564AA,
+0xFF3564AA,
+0xFF3564AA,
+0xFF3564AA,
+0xFF3665AB,
+0xFF3665AB,
+0xFF3665AB,
+0xFF3564AA,
+0xFF3564AA,
+0xFF3566AB,
+0xFF3667AC,
+0xFF3667AC,
+0xFF3667AC,
+0xFF3666AE,
+0xFF3767AF,
+0xFF3668AF,
+0xFF3769B0,
+0xFF3769B0,
+0xFF3769B0,
+0xFF366BB1,
+0xFF366BB1,
+0xFF366AB3,
+0xFF366AB3,
+0xFF366AB3,
+0xFF366AB3,
+0xFF366AB3,
+0xFF366CB4,
+0xFF366CB4,
+0xFF366CB4,
+0xFF376DB5,
+0xFF376DB5,
+0xFF366FB6,
+0xFF366FB6,
+0xFF356EB5,
+0xFF366FB6,
+0xFF366FB6,
+0xFF3770B7,
+0xFF3671B7,
+0xFF3671B7,
+0xFF3671B7,
+0xFF3570B6,
+0xFF366FB4,
+0xFF3770B5,
+0xFF3871B6,
+0xFF3972B7,
+0xFF3A73B8,
+0xFF3A73B8,
+0xFF3972B7,
+0xFF3972B7,
+0xFF3A73B8,
+0xFF3A73B8,
+0xFF3974B8,
+0xFF3974B8,
+0xFF3A75B9,
+0xFF3A75B9,
+0xFF3A75B9,
+0xFF3A75B9,
+0xFF3A75BB,
+0xFF3A75BB,
+0xFF3A75BB,
+0xFF3A75BB,
+0xFF3A75BB,
+0xFF3A75BB,
+0xFF3B76BC,
+0xFF3C77BD,
+0xFF3C77BD,
+0xFF3C77BD,
+0xFF3B76BC,
+0xFF3B76BC,
+0xFF3B76BC,
+0xFF3C77BD,
+0xFF3B76BC,
+0xFF3B76BC,
+0xFF3B76BC,
+0xFF3C77BD,
+0xFF3C77BD,
+0xFF3C77BD,
+0xFF3D78BE,
+0xFF3D78BE,
+0xFF3C77BD,
+0xFF3C77BD,
+0xFF3C77BD,
+0xFF3C77BD,
+0xFF3C76BF,
+0xFF3C76BF,
+0xFF3C76BF,
+0xFF3C76BF,
+0xFF3D77C0,
+0xFF3D77C0,
+0xFF3C78BE,
+0xFF3B77BD,
+0xFF3B77BD,
+0xFF3B77BD,
+0xFF3C78BE,
+0xFF3C78BE,
+0xFF3B77BD,
+0xFF3B77BD,
+0xFF3B77BD,
+0xFF3C78BE,
+0xFF3C78BE,
+0xFF3C78BE,
+0xFF3C78BE,
+0xFF3C78BE,
+0xFF3C78BE,
+0xFF3C78BE,
+0xFF3C78BE,
+0xFF3C78BE,
+0xFF3C78BE,
+0xFF3C78BE,
+0xFF3C78BE,
+0xFF3D79BF,
+0xFF3D79BF,
+0xFF3D79BF,
+0xFF3A79BE,
+0xFF3A79BE,
+0xFF3A79BE,
+0xFF3A79BE,
+0xFF3A79BE,
+0xFF3A79BE,
+0xFF3A79BE,
+0xFF3A79BE,
+0xFF3A79BE,
+0xFF3A79BE,
+0xFF3A79BE,
+0xFF3A79BE,
+0xFF3A79BE,
+0xFF3A79BE,
+0xFF3A79BE,
+0xFF3A79BE,
+0xFF3A79BE,
+0xFF3A79BE,
+0xFF3A79BE,
+0xFF3A79BE,
+0xFF3A79BE,
+0xFF3A79BE,
+0xFF3A79BE,
+0xFF3A79C0,
+0xFF3978C5,
+0xFF3A78C3,
+0xFF3D78BA,
+0xFF3E7AB9,
+0xFF3D79C1,
+0xFF3C77C3,
+0xFF3C78C1,
+0xFF3A79C0,
+0xFF3778BC,
+0xFF3B78B9,
+0xFF4679BA,
+0xFF556EA4,
+0xFF766287,
+0xFF571C30,
+0xFF852129,
+0xFF8F262A,
+0xFF8A3C49,
+0xFF532C47,
+0xFF8596C4,
+0xFF474C74,
+0xFF5F1923,
+0xFF85140C,
+0xFF93190E,
+0xFF982513,
+0xFF802709,
+0xFFC08B57,
+0xFF9F9445,
+0xFF788529,
+0xFF809435,
+0xFF85953D,
+0xFF81853B,
+0xFF63582A,
+0xFF3D211E,
+0xFF150520,
+0xFF59709C,
+0xFF4D7BB6,
+0xFF3A75B9,
+0xFF3A79C0,
+0xFF3F7CBD,
+0xFF3B78B9,
+0xFF3B7CC0,
+0xFF377AC0,
+0xFF377AC1,
+0xFF377BC2,
+0xFF377CBD,
+0xFF377BBA,
+0xFF397BB8,
+0xFF3B7BBB,
+0xFF3B7ABD,
+0xFF3A7BBF,
+0xFF3B7ABF,
+0xFF3A7BBF,
+0xFF3B7ABF,
+0xFF3A7BBF,
+0xFF3B7ABF,
+0xFF3A7BBF,
+0xFF3B7ABF,
+0xFF3A7BBF,
+0xFF3C7BC0,
+0xFF3B7CC0,
+0xFF3B7ABF,
+0xFF3A7BBF,
+0xFF3B7ABF,
+0xFF3B7CC0,
+0xFF3A7BBF,
+0xFF387BBF,
+0xFF3B7CC0,
+0xFF397CC0,
+0xFF3B7CC0,
+0xFF397CC0,
+0xFF3A7BBF,
+0xFF3A7BBF,
+0xFF3B7CC0,
+0xFF3B7CC0,
+0xFF3B7CC0,
+0xFF3B7CC0,
+0xFF3A7BBF,
+0xFF3A7BBF,
+0xFF3A7BBF,
+0xFF3B7CC0,
+0xFF3B7CC0,
+0xFF397CC0,
+0xFF3A7BBF,
+0xFF387BBF,
+0xFF3A7BBF,
+0xFF387BBF,
+0xFF3A7BBF,
+0xFF387BBF,
+0xFF3B7CC0,
+0xFF397CC0,
+0xFF3B7CC0,
+0xFF3A7DC1,
+0xFF3C7DC1,
+0xFF397CC0,
+0xFF3B7CC0,
+0xFF3A7BBF,
+0xFF3979C0,
+0xFF3A7AC1,
+0xFF3C7BC2,
+0xFF3B7BC2,
+0xFF3B7AC1,
+0xFF3979C0,
+0xFF3A79C0,
+0xFF3A7AC1,
+0xFF3B7AC1,
+0xFF3A7AC1,
+0xFF3B7AC1,
+0xFF3A7AC1,
+0xFF3B7AC1,
+0xFF3A7AC1,
+0xFF3B7AC1,
+0xFF3B7AC1,
+0xFF3A79C0,
+0xFF3A79C0,
+0xFF3A79C0,
+0xFF3A79C0,
+0xFF3C78C0,
+0xFF3C78C0,
+0xFF3C78C0,
+0xFF3C78C0,
+0xFF3C76BF,
+0xFF3C76BF,
+0xFF3C76BF,
+0xFF3C76BF,
+0xFF3B75BE,
+0xFF3B75BE,
+0xFF3C74BE,
+0xFF3C74BE,
+0xFF3C77BD,
+0xFF3B76BC,
+0xFF3B76BC,
+0xFF3A75BB,
+0xFF3A74BD,
+0xFF3A74BD,
+0xFF3A74BD,
+0xFF3973BC,
+0xFF3973BC,
+0xFF3973BC,
+0xFF3973BC,
+0xFF3973BC,
+0xFF3773BB,
+0xFF3773BB,
+0xFF3672BA,
+0xFF3672BA,
+0xFF3672BA,
+0xFF3672BA,
+0xFF3670B9,
+0xFF3670B9,
+0xFF356FB8,
+0xFF356FB8,
+0xFF346EB7,
+0xFF346EB7,
+0xFF366EB8,
+0xFF356DB7,
+0xFF356DB7,
+0xFF356DB7,
+0xFF356EB5,
+0xFF346DB4,
+0xFF346DB4,
+0xFF366CB4,
+0xFF376BB4,
+0xFF376BB4,
+0xFF376BB4,
+0xFF376BB4,
+0xFF366AB3,
+0xFF3569B2,
+0xFF3468B1,
+0xFF3468B1,
+0xFF3769B2,
+0xFF3668B1,
+0xFF3567B0,
+0xFF3567B0,
+0xFF3567B0,
+0xFF3567B0,
+0xFF3567AE,
+0xFF3466AD,
+0xFF3261A7,
+0xFF3261A7,
+0xFF3362A8,
+0xFF3362A8,
+0xFF3463A9,
+0xFF3463A9,
+0xFF3564AA,
+0xFF3564AA,
+0xFF3564AA,
+0xFF3665AB,
+0xFF3665AB,
+0xFF3665AB,
+0xFF3665AB,
+0xFF3665AB,
+0xFF3665AB,
+0xFF3665AB,
+0xFF3667AC,
+0xFF3667AC,
+0xFF3768AD,
+0xFF3768AD,
+0xFF3767AF,
+0xFF3767AF,
+0xFF3769B0,
+0xFF3769B0,
+0xFF386AB1,
+0xFF386AB1,
+0xFF366BB1,
+0xFF366BB1,
+0xFF366AB3,
+0xFF366AB3,
+0xFF376BB4,
+0xFF376BB4,
+0xFF366CB4,
+0xFF366CB4,
+0xFF376DB5,
+0xFF376DB5,
+0xFF376DB5,
+0xFF386EB6,
+0xFF366FB6,
+0xFF366FB6,
+0xFF366FB6,
+0xFF366FB6,
+0xFF3770B7,
+0xFF3770B7,
+0xFF3671B7,
+0xFF3772B8,
+0xFF3772B8,
+0xFF3772B8,
+0xFF3871B6,
+0xFF3871B6,
+0xFF3972B7,
+0xFF3A73B8,
+0xFF3A73B8,
+0xFF3A73B8,
+0xFF3A73B8,
+0xFF3A73B8,
+0xFF3A73B8,
+0xFF3A73B8,
+0xFF3A75B9,
+0xFF3A75B9,
+0xFF3A75B9,
+0xFF3A75B9,
+0xFF3B76BA,
+0xFF3B76BA,
+0xFF3B76BC,
+0xFF3B76BC,
+0xFF3A75BB,
+0xFF3A75BB,
+0xFF3B76BC,
+0xFF3B76BC,
+0xFF3B76BC,
+0xFF3C77BD,
+0xFF3C77BD,
+0xFF3C77BD,
+0xFF3C77BD,
+0xFF3C77BD,
+0xFF3C77BD,
+0xFF3C77BD,
+0xFF3C77BD,
+0xFF3B76BC,
+0xFF3C77BD,
+0xFF3C77BD,
+0xFF3D78BE,
+0xFF3D78BE,
+0xFF3D78BE,
+0xFF3D78BE,
+0xFF3D78BE,
+0xFF3D78BE,
+0xFF3C77BD,
+0xFF3C77BD,
+0xFF3D77C0,
+0xFF3D77C0,
+0xFF3D77C0,
+0xFF3D77C0,
+0xFF3D77C0,
+0xFF3C78C0,
+0xFF3C78BE,
+0xFF3C78BE,
+0xFF3C78BE,
+0xFF3C78BE,
+0xFF3C78BE,
+0xFF3C78BE,
+0xFF3C78BE,
+0xFF3B77BD,
+0xFF3B77BD,
+0xFF3C78BE,
+0xFF3C78BE,
+0xFF3C78BE,
+0xFF3C78BE,
+0xFF3C78BE,
+0xFF3C78BE,
+0xFF3C78BE,
+0xFF3C78BE,
+0xFF3C78BE,
+0xFF3C78BE,
+0xFF3C78BE,
+0xFF3C78BE,
+0xFF3C78BE,
+0xFF3C78BE,
+0xFF3D79BF,
+0xFF3A79BE,
+0xFF3A79BE,
+0xFF3B7ABF,
+0xFF3A79BE,
+0xFF3A79BE,
+0xFF3A79BE,
+0xFF3A79BE,
+0xFF3A79BE,
+0xFF3A79BE,
+0xFF3A79BE,
+0xFF3A79BE,
+0xFF3A79BE,
+0xFF3A79BE,
+0xFF3A79BE,
+0xFF3A79BE,
+0xFF3A79BE,
+0xFF3B7ABF,
+0xFF3B7ABF,
+0xFF3B7ABF,
+0xFF3B7ABF,
+0xFF3B7ABF,
+0xFF3B7ABF,
+0xFF3B7ABF,
+0xFF3B7AC1,
+0xFF3979C3,
+0xFF3A78C1,
+0xFF3D78BA,
+0xFF3E7AB9,
+0xFF3D79BF,
+0xFF3A78C1,
+0xFF3A78C1,
+0xFF3A79C0,
+0xFF4080C0,
+0xFF3879B9,
+0xFF367ABB,
+0xFF457BB7,
+0xFF5973A4,
+0xFF6D5F82,
+0xFF5B1B2C,
+0xFF742634,
+0xFF6E3A50,
+0xFF483E61,
+0xFF5D8AC3,
+0xFF385382,
+0xFF86424D,
+0xFF9D241B,
+0xFFA82216,
+0xFF9E240D,
+0xFF752200,
+0xFFE2B675,
+0xFFC1BD64,
+0xFF96A844,
+0xFF728627,
+0xFF84973E,
+0xFF748330,
+0xFF959056,
+0xFF3B1606,
+0xFF462230,
+0xFF0C0928,
+0xFF647FAE,
+0xFF4A7ABA,
+0xFF3874BA,
+0xFF3C7CBC,
+0xFF3B7CBC,
+0xFF387DC2,
+0xFF367CC4,
+0xFF377BC4,
+0xFF377CC1,
+0xFF377EBE,
+0xFF387EBC,
+0xFF3C7CBC,
+0xFF3F7CBF,
+0xFF3D7CC1,
+0xFF3C7DC1,
+0xFF3C7DC1,
+0xFF3C7DC1,
+0xFF3C7DC1,
+0xFF3B7CC0,
+0xFF3B7CC0,
+0xFF3B7CC0,
+0xFF3B7CC0,
+0xFF3B7CC0,
+0xFF3B7CC0,
+0xFF3B7CC0,
+0xFF3B7CC0,
+0xFF3A7BBF,
+0xFF3B7CC0,
+0xFF3B7CC0,
+0xFF387BBF,
+0xFF397CC0,
+0xFF397CC0,
+0xFF397CC0,
+0xFF397CC0,
+0xFF397CC0,
+0xFF397CC0,
+0xFF387BBF,
+0xFF3B7CC0,
+0xFF3B7CC0,
+0xFF3C7DC1,
+0xFF3B7CC0,
+0xFF3B7CC0,
+0xFF3B7CC0,
+0xFF3B7CC0,
+0xFF3C7DC1,
+0xFF397CC0,
+0xFF397CC0,
+0xFF397CC0,
+0xFF397CC0,
+0xFF387BBF,
+0xFF397CC0,
+0xFF397CC0,
+0xFF397CC0,
+0xFF397CC0,
+0xFF397CC0,
+0xFF3A7DC1,
+0xFF3A7DC1,
+0xFF3A7DC1,
+0xFF397CC0,
+0xFF397CC0,
+0xFF387BBF,
+0xFF3A7AC1,
+0xFF3B7BC2,
+0xFF3B7BC2,
+0xFF3B7BC2,
+0xFF3A7AC1,
+0xFF3A7AC1,
+0xFF3A7AC1,
+0xFF3A7AC1,
+0xFF3B7BC2,
+0xFF3B7BC2,
+0xFF3B7BC2,
+0xFF3A7AC1,
+0xFF3A7AC1,
+0xFF3A7AC1,
+0xFF3A7AC1,
+0xFF3A7AC1,
+0xFF3B7AC1,
+0xFF3B7AC1,
+0xFF3B7AC1,
+0xFF3B7AC1,
+0xFF3C78C0,
+0xFF3C78C0,
+0xFF3C78C0,
+0xFF3C78C0,
+0xFF3D77C0,
+0xFF3D77C0,
+0xFF3D77C0,
+0xFF3D77C0,
+0xFF3C76BF,
+0xFF3C76BF,
+0xFF3C76BF,
+0xFF3B75BE,
+0xFF3C77BD,
+0xFF3B76BC,
+0xFF3B76BC,
+0xFF3B76BC,
+0xFF3B75BE,
+0xFF3B75BE,
+0xFF3A74BD,
+0xFF3A74BD,
+0xFF3A74BD,
+0xFF3A74BD,
+0xFF3A74BD,
+0xFF3973BC,
+0xFF3874BC,
+0xFF3773BB,
+0xFF3773BB,
+0xFF3773BB,
+0xFF3672BA,
+0xFF3672BA,
+0xFF3771BA,
+0xFF3670B9,
+0xFF3670B9,
+0xFF3670B9,
+0xFF356FB8,
+0xFF356FB8,
+0xFF366EB8,
+0xFF366EB8,
+0xFF366EB8,
+0xFF356DB7,
+0xFF356EB5,
+0xFF356EB5,
+0xFF346DB4,
+0xFF346DB4,
+0xFF366CB4,
+0xFF376BB4,
+0xFF376BB4,
+0xFF366AB3,
+0xFF366AB3,
+0xFF3569B2,
+0xFF3569B2,
+0xFF3569B2,
+0xFF3769B2,
+0xFF3769B2,
+0xFF3668B1,
+0xFF3668B1,
+0xFF3668B1,
+0xFF3567B0,
+0xFF3567AE,
+0xFF3567AE,
+0xFF3362A8,
+0xFF3362A8,
+0xFF3362A8,
+0xFF3463A9,
+0xFF3463A9,
+0xFF3564AA,
+0xFF3564AA,
+0xFF3564AA,
+0xFF3665AB,
+0xFF3665AB,
+0xFF3566AB,
+0xFF3566AB,
+0xFF3667AC,
+0xFF3667AC,
+0xFF3667AC,
+0xFF3667AC,
+0xFF3768AD,
+0xFF3768AD,
+0xFF3868B0,
+0xFF3868B0,
+0xFF3769B0,
+0xFF3769B0,
+0xFF386AB1,
+0xFF386AB1,
+0xFF366BB1,
+0xFF366BB1,
+0xFF366AB3,
+0xFF376BB4,
+0xFF366CB4,
+0xFF366CB4,
+0xFF366CB4,
+0xFF366CB4,
+0xFF376DB5,
+0xFF376DB5,
+0xFF386EB6,
+0xFF386EB6,
+0xFF366FB6,
+0xFF366FB6,
+0xFF3770B7,
+0xFF3770B7,
+0xFF3770B7,
+0xFF3770B7,
+0xFF3671B7,
+0xFF3671B7,
+0xFF3772B8,
+0xFF3873B9,
+0xFF3974BA,
+0xFF3974BA,
+0xFF3A73BA,
+0xFF3A73BA,
+0xFF3A73BA,
+0xFF3A73BA,
+0xFF3B74BB,
+0xFF3B74BB,
+0xFF3A75BB,
+0xFF3A75BB,
+0xFF3B76BC,
+0xFF3B76BC,
+0xFF3B76BC,
+0xFF3B76BC,
+0xFF3B76BC,
+0xFF3B76BC,
+0xFF3B76BC,
+0xFF3B76BC,
+0xFF3B76BC,
+0xFF3B76BC,
+0xFF3B76BC,
+0xFF3C77BD,
+0xFF3C77BD,
+0xFF3C77BD,
+0xFF3C77BD,
+0xFF3C77BD,
+0xFF3C78BE,
+0xFF3C78BE,
+0xFF3C78BE,
+0xFF3C78BE,
+0xFF3C78BE,
+0xFF3C78BE,
+0xFF3B77BD,
+0xFF3B77BD,
+0xFF3D79BF,
+0xFF3D79BF,
+0xFF3C78BE,
+0xFF3C78BE,
+0xFF3C78BE,
+0xFF3C78BE,
+0xFF3C78BE,
+0xFF3C78BE,
+0xFF3C78BE,
+0xFF3C78BE,
+0xFF3C78BE,
+0xFF3C78BE,
+0xFF3D79BF,
+0xFF3D79BF,
+0xFF3D79BF,
+0xFF3D79BF,
+0xFF3C78BE,
+0xFF3A79BE,
+0xFF3A79BE,
+0xFF3A79BE,
+0xFF3B7ABF,
+0xFF3B7ABF,
+0xFF3A79BE,
+0xFF3A79BE,
+0xFF3A79BE,
+0xFF3A79BE,
+0xFF3A79BE,
+0xFF3A79BE,
+0xFF3B7ABF,
+0xFF3B7ABF,
+0xFF3A79BE,
+0xFF3A79BE,
+0xFF3C78BE,
+0xFF3C78BE,
+0xFF3A79BE,
+0xFF3A79BE,
+0xFF3A79BE,
+0xFF3A79BE,
+0xFF3A79BE,
+0xFF3B7ABF,
+0xFF3B7ABF,
+0xFF3B7ABF,
+0xFF3B7ABF,
+0xFF3B7ABF,
+0xFF3B7ABF,
+0xFF3B7ABF,
+0xFF3B7ABF,
+0xFF3B7ABF,
+0xFF3B7ABF,
+0xFF3B7ABF,
+0xFF3B7ABF,
+0xFF3B7ABF,
+0xFF3B7ABF,
+0xFF3B7ABF,
+0xFF3B7ABF,
+0xFF3B7ABF,
+0xFF3B7CC0,
+0xFF3B7CC0,
+0xFF3B7CC0,
+0xFF3B7CC0,
+0xFF3B7CC0,
+0xFF3B7CC0,
+0xFF3B7CC0,
+0xFF3B7CC0,
+0xFF3B7CBE,
+0xFF3B7CBE,
+0xFF3E7AC0,
+0xFF3C7BC0,
+0xFF3B7CBE,
+0xFF397CC0,
+0xFF387DC2,
+0xFF397CC0,
+0xFF3C7CBA,
+0xFF3A7AB7,
+0xFF3880BA,
+0xFF387DB8,
+0xFF4278B4,
+0xFF5B74AA,
+0xFF6F5D83,
+0xFF3F1C3A,
+0xFF3D2945,
+0xFF4F5881,
+0xFF4781C1,
+0xFF345892,
+0xFF6A344B,
+0xFF9F2D2D,
+0xFFAB1C16,
+0xFF9E1E05,
+0xFF722900,
+0xFFD4B86F,
+0xFF9BA149,
+0xFF7D9535,
+0xFF8AA146,
+0xFF8DA44C,
+0xFF6A822E,
+0xFF8E9353,
+0xFF623F23,
+0xFF4B1B19,
+0xFF371724,
+0xFF211A3B,
+0xFF6482B8,
+0xFF447ABA,
+0xFF3F81BE,
+0xFF347BBB,
+0xFF357DC5,
+0xFF377CC7,
+0xFF387BC2,
+0xFF377AC0,
+0xFF367DBD,
+0xFF387DBE,
+0xFF3F7BC1,
+0xFF3F79C2,
+0xFF3D7CC1,
+0xFF3A7DC1,
+0xFF3A7DC1,
+0xFF3A7DC1,
+0xFF3A7DC1,
+0xFF397CC0,
+0xFF397CC0,
+0xFF397CC0,
+0xFF3A7DC1,
+0xFF3A7DC1,
+0xFF3A7DC1,
+0xFF3A7DC1,
+0xFF3A7DC1,
+0xFF3A7DC1,
+0xFF3A7DC1,
+0xFF3A7DC1,
+0xFF397CC0,
+0xFF397CC0,
+0xFF3A7DC1,
+0xFF3A7DC1,
+0xFF3A7DC1,
+0xFF3A7DC1,
+0xFF397CC0,
+0xFF397CC0,
+0xFF397CC0,
+0xFF397CC0,
+0xFF3A7DC1,
+0xFF3A7DC1,
+0xFF3C7DC1,
+0xFF3C7DC1,
+0xFF3C7DC1,
+0xFF3D7EC2,
+0xFF3A7DC1,
+0xFF3A7DC1,
+0xFF397CC0,
+0xFF397CC0,
+0xFF397CC0,
+0xFF397CC0,
+0xFF397CC0,
+0xFF397CC0,
+0xFF397CC0,
+0xFF3A7DC1,
+0xFF3A7DC1,
+0xFF3A7DC1,
+0xFF3A7DC1,
+0xFF3A7DC1,
+0xFF397CC0,
+0xFF397CC0,
+0xFF3A7DC1,
+0xFF3A7DC1,
+0xFF3A7DC1,
+0xFF397CC0,
+0xFF397CC0,
+0xFF397CC0,
+0xFF397CC0,
+0xFF3A7DC1,
+0xFF397CC0,
+0xFF397CC0,
+0xFF397CC0,
+0xFF397CC0,
+0xFF397CC0,
+0xFF397CC0,
+0xFF397CC0,
+0xFF397CC0,
+0xFF3B7BC2,
+0xFF3B7BC2,
+0xFF3A7AC1,
+0xFF3A7AC1,
+0xFF3B7AC1,
+0xFF3B7AC1,
+0xFF3B7AC1,
+0xFF3B7AC1,
+0xFF3D79C1,
+0xFF3D79C1,
+0xFF3D79C1,
+0xFF3C78C0,
+0xFF3C78C0,
+0xFF3C78C0,
+0xFF3B77BF,
+0xFF3B77BF,
+0xFF3B77BD,
+0xFF3B77BD,
+0xFF3A76BC,
+0xFF3A76BC,
+0xFF3B75BE,
+0xFF3B75BE,
+0xFF3B75BE,
+0xFF3A74BD,
+0xFF3A74BD,
+0xFF3A74BD,
+0xFF3A74BD,
+0xFF3A74BD,
+0xFF3975BD,
+0xFF3975BD,
+0xFF3874BC,
+0xFF3874BC,
+0xFF3773BB,
+0xFF3773BB,
+0xFF3773BB,
+0xFF3672BA,
+0xFF3672BA,
+0xFF3672BA,
+0xFF3771BA,
+0xFF3771BA,
+0xFF3670B9,
+0xFF3670B9,
+0xFF356FB8,
+0xFF356FB8,
+0xFF3570B6,
+0xFF346FB5,
+0xFF346FB5,
+0xFF356EB5,
+0xFF366CB4,
+0xFF366CB4,
+0xFF376BB4,
+0xFF376BB4,
+0xFF376BB4,
+0xFF366AB3,
+0xFF366AB3,
+0xFF366AB3,
+0xFF366AB3,
+0xFF3569B2,
+0xFF3769B2,
+0xFF3668B1,
+0xFF3668B1,
+0xFF3668B1,
+0xFF3668B1,
+0xFF3567B0,
+0xFF3362A8,
+0xFF3362A8,
+0xFF3463A9,
+0xFF3564AA,
+0xFF3564AA,
+0xFF3564AA,
+0xFF3665AB,
+0xFF3665AB,
+0xFF3766AC,
+0xFF3766AC,
+0xFF3667AC,
+0xFF3667AC,
+0xFF3667AC,
+0xFF3667AC,
+0xFF3768AD,
+0xFF3768AD,
+0xFF3768AD,
+0xFF3869AE,
+0xFF3868B0,
+0xFF3969B1,
+0xFF386AB1,
+0xFF386AB1,
+0xFF386AB1,
+0xFF396BB2,
+0xFF376CB2,
+0xFF376CB2,
+0xFF376BB4,
+0xFF376BB4,
+0xFF366CB4,
+0xFF376DB5,
+0xFF376DB5,
+0xFF376DB5,
+0xFF386EB6,
+0xFF386EB6,
+0xFF386EB6,
+0xFF386EB6,
+0xFF3770B7,
+0xFF3770B7,
+0xFF3770B7,
+0xFF3770B7,
+0xFF3871B8,
+0xFF3871B8,
+0xFF3772B8,
+0xFF3772B8,
+0xFF3873B9,
+0xFF3873B9,
+0xFF3974BA,
+0xFF3974BA,
+0xFF3B74BB,
+0xFF3B74BB,
+0xFF3B74BB,
+0xFF3B74BB,
+0xFF3B74BB,
+0xFF3B74BB,
+0xFF3B76BC,
+0xFF3B76BC,
+0xFF3B76BC,
+0xFF3B76BC,
+0xFF3B76BC,
+0xFF3B76BC,
+0xFF3C77BD,
+0xFF3C77BD,
+0xFF3C77BD,
+0xFF3C77BD,
+0xFF3C77BD,
+0xFF3C77BD,
+0xFF3D78BE,
+0xFF3D78BE,
+0xFF3D78BE,
+0xFF3D78BE,
+0xFF3D78BE,
+0xFF3D78BE,
+0xFF3C78BE,
+0xFF3C78BE,
+0xFF3D79BF,
+0xFF3D79BF,
+0xFF3D79BF,
+0xFF3D79BF,
+0xFF3C78BE,
+0xFF3C78BE,
+0xFF3E7AC0,
+0xFF3D79BF,
+0xFF3D79BF,
+0xFF3C78BE,
+0xFF3C78BE,
+0xFF3C78BE,
+0xFF3C78BE,
+0xFF3D79BF,
+0xFF3D79BF,
+0xFF3D79BF,
+0xFF3D79BF,
+0xFF3D79BF,
+0xFF3D79BF,
+0xFF3D79BF,
+0xFF3D79BF,
+0xFF3D79BF,
+0xFF3B7ABF,
+0xFF3B7ABF,
+0xFF3B7ABF,
+0xFF3B7ABF,
+0xFF3B7ABF,
+0xFF3B7ABF,
+0xFF3B7ABF,
+0xFF3B7ABF,
+0xFF3A79BE,
+0xFF3B7ABF,
+0xFF3B7ABF,
+0xFF3B7ABF,
+0xFF3B7ABF,
+0xFF3B7ABF,
+0xFF3B7ABF,
+0xFF3B7ABF,
+0xFF3D79BF,
+0xFF3D79BF,
+0xFF3B7ABF,
+0xFF3B7ABF,
+0xFF3B7ABF,
+0xFF3B7ABF,
+0xFF3B7ABF,
+0xFF3B7ABF,
+0xFF3B7ABF,
+0xFF3C7BC0,
+0xFF3C7BC0,
+0xFF3C7BC0,
+0xFF3B7ABF,
+0xFF3B7ABF,
+0xFF3C7BC0,
+0xFF3C7BC0,
+0xFF3C7BC0,
+0xFF3C7BC0,
+0xFF3C7BC0,
+0xFF3C7BC0,
+0xFF3C7BC0,
+0xFF3C7BC0,
+0xFF3C7BC0,
+0xFF3C7BC0,
+0xFF3B7CC0,
+0xFF3B7CC0,
+0xFF3B7CC0,
+0xFF3C7DC1,
+0xFF3C7DC1,
+0xFF3B7CC0,
+0xFF3B7CC0,
+0xFF3B7CBE,
+0xFF3C7EBB,
+0xFF3C7DBD,
+0xFF3D7CC1,
+0xFF3F7BC3,
+0xFF3D7CBF,
+0xFF3A7EBD,
+0xFF397EBF,
+0xFF397EBF,
+0xFF3C7CBC,
+0xFF3D7FBC,
+0xFF3B81BD,
+0xFF377EBC,
+0xFF3A7EBF,
+0xFF4678B7,
+0xFF6778B0,
+0xFF4D4F7F,
+0xFF1D2248,
+0xFF607BAA,
+0xFF115199,
+0xFF285397,
+0xFF5E3A5E,
+0xFF91343F,
+0xFFA21D1E,
+0xFF9A200B,
+0xFF743200,
+0xFFBFAB62,
+0xFF98A24B,
+0xFF7B9436,
+0xFF8BA449,
+0xFF97AF59,
+0xFF6D8633,
+0xFF76803B,
+0xFF8D7243,
+0xFF451700,
+0xFF4E1E1A,
+0xFF260717,
+0xFF3F446A,
+0xFF5D81B3,
+0xFF3C79B2,
+0xFF3C81C2,
+0xFF397CC3,
+0xFF3A7CC6,
+0xFF3B7BC2,
+0xFF387BC1,
+0xFF377CBF,
+0xFF397CC0,
+0xFF3F7BC3,
+0xFF3F79C2,
+0xFF3B7CC0,
+0xFF397CC0,
+0xFF397CC0,
+0xFF397CC0,
+0xFF397CC0,
+0xFF397CC0,
+0xFF397CC0,
+0xFF397CC0,
+0xFF3A7DC1,
+0xFF3B7EC2,
+0xFF3B7EC2,
+0xFF3B7EC2,
+0xFF3A7DC1,
+0xFF3A7DC1,
+0xFF3A7DC1,
+0xFF3B7EC2,
+0xFF3A7DC1,
+0xFF3A7DC1,
+0xFF3A7DC1,
+0xFF3A7DC1,
+0xFF3A7DC1,
+0xFF3A7DC1,
+0xFF3A7DC1,
+0xFF3A7DC1,
+0xFF3C7DC1,
+0xFF3A7DC1,
+0xFF3C7DC1,
+0xFF3C7DC1,
+0xFF3C7DC1,
+0xFF3C7DC1,
+0xFF3D7EC2,
+0xFF3D7EC2,
+0xFF3C7DC1,
+0xFF3A7DC1,
+0xFF3C7DC1,
+0xFF3A7DC1,
+0xFF3C7DC1,
+0xFF3A7DC1,
+0xFF3C7DC1,
+0xFF3A7DC1,
+0xFF3C7DC1,
+0xFF3A7DC1,
+0xFF3C7DC1,
+0xFF3A7DC1,
+0xFF3C7DC1,
+0xFF3A7DC1,
+0xFF3C7DC1,
+0xFF3A7DC1,
+0xFF3B7EC2,
+0xFF3B7EC2,
+0xFF3A7DC1,
+0xFF3A7DC1,
+0xFF3A7DC1,
+0xFF3A7DC1,
+0xFF3A7DC1,
+0xFF3B7EC2,
+0xFF3A7DC1,
+0xFF3A7DC1,
+0xFF3A7DC1,
+0xFF3A7DC1,
+0xFF3A7DC1,
+0xFF397CC0,
+0xFF397CC0,
+0xFF397CC0,
+0xFF3B7BC2,
+0xFF3B7BC2,
+0xFF3B7BC2,
+0xFF3B7BC2,
+0xFF3C7BC2,
+0xFF3B7AC1,
+0xFF3B7AC1,
+0xFF3B7AC1,
+0xFF3B7AC1,
+0xFF3D79C1,
+0xFF3D79C1,
+0xFF3D79C1,
+0xFF3C78C0,
+0xFF3C78C0,
+0xFF3C78C0,
+0xFF3C78C0,
+0xFF3C78BE,
+0xFF3B77BD,
+0xFF3B77BD,
+0xFF3B77BD,
+0xFF3C76BF,
+0xFF3C76BF,
+0xFF3C76BF,
+0xFF3B75BE,
+0xFF3B75BE,
+0xFF3B75BE,
+0xFF3B75BE,
+0xFF3B75BE,
+0xFF3A76BE,
+0xFF3975BD,
+0xFF3975BD,
+0xFF3975BD,
+0xFF3874BC,
+0xFF3874BC,
+0xFF3773BB,
+0xFF3773BB,
+0xFF3773BB,
+0xFF3773BB,
+0xFF3771BA,
+0xFF3771BA,
+0xFF3670B9,
+0xFF3670B9,
+0xFF3670B9,
+0xFF356FB8,
+0xFF3570B6,
+0xFF3570B6,
+0xFF346FB5,
+0xFF346FB5,
+0xFF376DB5,
+0xFF376DB5,
+0xFF386CB5,
+0xFF386CB5,
+0xFF376BB4,
+0xFF376BB4,
+0xFF386CB5,
+0xFF386CB5,
+0xFF376BB4,
+0xFF366AB3,
+0xFF386AB3,
+0xFF3769B2,
+0xFF3769B2,
+0xFF3769B2,
+0xFF3769B2,
+0xFF3668B1,
+0xFF3463A9,
+0xFF3463A9,
+0xFF3564AA,
+0xFF3564AA,
+0xFF3665AB,
+0xFF3665AB,
+0xFF3566AB,
+0xFF3566AB,
+0xFF3667AC,
+0xFF3667AC,
+0xFF3667AC,
+0xFF3667AC,
+0xFF3667AC,
+0xFF3768AD,
+0xFF3768AD,
+0xFF3869AE,
+0xFF3868B0,
+0xFF3868B0,
+0xFF386AB1,
+0xFF386AB1,
+0xFF386AB1,
+0xFF386AB1,
+0xFF376CB2,
+0xFF376CB2,
+0xFF376CB2,
+0xFF376CB2,
+0xFF376DB5,
+0xFF376DB5,
+0xFF376DB5,
+0xFF386EB6,
+0xFF366FB6,
+0xFF366FB6,
+0xFF386EB6,
+0xFF386EB6,
+0xFF396FB7,
+0xFF396FB7,
+0xFF3770B7,
+0xFF3770B7,
+0xFF3770B7,
+0xFF3871B8,
+0xFF3871B8,
+0xFF3972B9,
+0xFF3873B9,
+0xFF3974BA,
+0xFF3974BA,
+0xFF3974BA,
+0xFF3974BA,
+0xFF3873B9,
+0xFF3C75BC,
+0xFF3C75BC,
+0xFF3A75BB,
+0xFF3A75BB,
+0xFF3A75BB,
+0xFF3B76BC,
+0xFF3B76BC,
+0xFF3C77BD,
+0xFF3C77BD,
+0xFF3C77BD,
+0xFF3C77BD,
+0xFF3C77BD,
+0xFF3C77BD,
+0xFF3C77BD,
+0xFF3C77BD,
+0xFF3C77BD,
+0xFF3C78BE,
+0xFF3C78BE,
+0xFF3C78BE,
+0xFF3D79BF,
+0xFF3D79BF,
+0xFF3D79BF,
+0xFF3D79BF,
+0xFF3D79BF,
+0xFF3C78BE,
+0xFF3D79BF,
+0xFF3D79BF,
+0xFF3E7AC0,
+0xFF3E7AC0,
+0xFF3D79BF,
+0xFF3D79BF,
+0xFF3D79BF,
+0xFF3C7BBE,
+0xFF3B7ABD,
+0xFF3B7ABD,
+0xFF3A79BC,
+0xFF3A79BC,
+0xFF3A79BC,
+0xFF3B7ABD,
+0xFF3B7ABD,
+0xFF3B7ABF,
+0xFF3B7ABF,
+0xFF3B7ABF,
+0xFF3B7ABF,
+0xFF3B7ABF,
+0xFF3B7ABF,
+0xFF3B7ABF,
+0xFF3B7ABF,
+0xFF3B7ABF,
+0xFF3B7ABF,
+0xFF3B7ABF,
+0xFF3B7ABF,
+0xFF3B7ABF,
+0xFF3B7ABF,
+0xFF3B7ABF,
+0xFF3B7ABF,
+0xFF3B7ABF,
+0xFF3B7ABF,
+0xFF3C7BC0,
+0xFF3C7BC0,
+0xFF3C7BC0,
+0xFF3C7BC0,
+0xFF3C7BC0,
+0xFF3C7BC0,
+0xFF3C7BBE,
+0xFF3C7BBE,
+0xFF3C7BBE,
+0xFF3C7BBE,
+0xFF3C7BBE,
+0xFF3C7BBE,
+0xFF3C7BBE,
+0xFF3C7BBE,
+0xFF3C7BBE,
+0xFF3C7BBE,
+0xFF3D7CBF,
+0xFF3D7CBF,
+0xFF3C7BBE,
+0xFF3C7BBE,
+0xFF3D7CBF,
+0xFF3D7CBF,
+0xFF3C7DC1,
+0xFF3C7DC1,
+0xFF3C7DC1,
+0xFF3C7DC1,
+0xFF3C7DC1,
+0xFF3C7DC1,
+0xFF3C7DC1,
+0xFF3C7DC1,
+0xFF3C7DC1,
+0xFF3C7DC1,
+0xFF3C7DC1,
+0xFF3C7DC1,
+0xFF3C7DC1,
+0xFF3C7DC1,
+0xFF3C7DC1,
+0xFF3C7DBF,
+0xFF3A7EBD,
+0xFF3C7DBD,
+0xFF407BC1,
+0xFF417AC1,
+0xFF4278BE,
+0xFF3F7ABC,
+0xFF3B7DBA,
+0xFF397DBC,
+0xFF3C7CC3,
+0xFF3C7CC4,
+0xFF3D7DC5,
+0xFF3D7DC5,
+0xFF3D7DC4,
+0xFF3F78BD,
+0xFF4874BB,
+0xFF5D80C2,
+0xFF062156,
+0xFF4E75AE,
+0xFF0E509E,
+0xFF1E4F9B,
+0xFF463D6C,
+0xFF672B44,
+0xFF8E242E,
+0xFF83190B,
+0xFF693003,
+0xFFC4B16C,
+0xFF909A43,
+0xFF7E9739,
+0xFF8BA54A,
+0xFF768F3B,
+0xFF677E2E,
+0xFF899448,
+0xFFC8BC72,
+0xFF513200,
+0xFF4F1F09,
+0xFF4C1E20,
+0xFF18020E,
+0xFF545B78,
+0xFF5681B4,
+0xFF427EBD,
+0xFF4279BC,
+0xFF427BC0,
+0xFF3B7EC2,
+0xFF397EC3,
+0xFF3C7CC4,
+0xFF3D7BC4,
+0xFF3E7DC4,
+0xFF3E7DC4,
+0xFF3D7EC2,
+0xFF3D7EC2,
+0xFF3D7EC2,
+0xFF3D7EC2,
+0xFF3D7EC2,
+0xFF3C7DC1,
+0xFF3C7DC1,
+0xFF3C7DC1,
+0xFF3D7EC2,
+0xFF3D7EC2,
+0xFF3D7EC2,
+0xFF3D7EC2,
+0xFF3D7EC2,
+0xFF3D7EC2,
+0xFF3D7EC2,
+0xFF3D7EC2,
+0xFF3D7EC2,
+0xFF3D7EC2,
+0xFF3D7EC2,
+0xFF3D7EC2,
+0xFF3D7EC2,
+0xFF3D7EC2,
+0xFF3D7EC2,
+0xFF3D7EC2,
+0xFF3E7DC2,
+0xFF3D7EC2,
+0xFF3E7DC2,
+0xFF3E7DC2,
+0xFF3E7DC2,
+0xFF3E7DC2,
+0xFF3E7DC2,
+0xFF3E7DC2,
+0xFF3E7DC2,
+0xFF3D7EC2,
+0xFF3E7DC2,
+0xFF3D7EC2,
+0xFF3E7DC2,
+0xFF3D7EC2,
+0xFF3E7DC2,
+0xFF3D7EC2,
+0xFF3E7DC2,
+0xFF3D7EC2,
+0xFF3E7DC2,
+0xFF3D7EC2,
+0xFF3E7DC2,
+0xFF3D7EC2,
+0xFF3E7DC2,
+0xFF3D7EC2,
+0xFF3D7EC2,
+0xFF3D7EC2,
+0xFF3D7EC2,
+0xFF3C7DC1,
+0xFF3C7DC1,
+0xFF3D7EC2,
+0xFF3D7EC2,
+0xFF3D7EC2,
+0xFF3D7EC2,
+0xFF3C7DC1,
+0xFF3C7DC1,
+0xFF3C7DC1,
+0xFF3C7DC1,
+0xFF3C7DC1,
+0xFF3C7DC1,
+0xFF3C7DC1,
+0xFF3A7DC1,
+0xFF3A7DC1,
+0xFF3B7CC0,
+0xFF3B7CC0,
+0xFF3B7CC0,
+0xFF3B7CC0,
+0xFF3B7CC0,
+0xFF3B7CC0,
+0xFF3A7BBF,
+0xFF3B7ABF,
+0xFF3B7ABF,
+0xFF3B7ABF,
+0xFF3A79BE,
+0xFF3A79BE,
+0xFF3A79BE,
+0xFF3A79BE,
+0xFF3B7ABF,
+0xFF3A79BE,
+0xFF3C78BE,
+0xFF3C78BE,
+0xFF3C78C0,
+0xFF3C78C0,
+0xFF3D77C0,
+0xFF3C76BF,
+0xFF3B75BE,
+0xFF3B75BE,
+0xFF3B75BE,
+0xFF3B75BE,
+0xFF3B75BE,
+0xFF3B75BE,
+0xFF3B75BE,
+0xFF3A74BD,
+0xFF3975BD,
+0xFF3975BD,
+0xFF3874BC,
+0xFF3874BC,
+0xFF3773BB,
+0xFF3773BB,
+0xFF3672BA,
+0xFF3672BA,
+0xFF3672BA,
+0xFF3672BA,
+0xFF3670B9,
+0xFF3670B9,
+0xFF3570B6,
+0xFF3570B6,
+0xFF3570B6,
+0xFF3570B6,
+0xFF386EB6,
+0xFF386EB6,
+0xFF376DB5,
+0xFF376DB5,
+0xFF376DB5,
+0xFF376DB5,
+0xFF386CB5,
+0xFF386CB5,
+0xFF386CB5,
+0xFF376BB4,
+0xFF366AB3,
+0xFF366AB3,
+0xFF366AB3,
+0xFF366AB3,
+0xFF3769B2,
+0xFF3769B2,
+0xFF3564AA,
+0xFF3564AA,
+0xFF3564AA,
+0xFF3665AB,
+0xFF3665AB,
+0xFF3766AC,
+0xFF3667AC,
+0xFF3667AC,
+0xFF3667AC,
+0xFF3667AC,
+0xFF3667AC,
+0xFF3768AD,
+0xFF3768AD,
+0xFF3768AD,
+0xFF3869AE,
+0xFF3869AE,
+0xFF3969B1,
+0xFF3969B1,
+0xFF396BB2,
+0xFF396BB2,
+0xFF396BB2,
+0xFF396BB2,
+0xFF376CB2,
+0xFF386DB3,
+0xFF386DB3,
+0xFF386DB3,
+0xFF376DB5,
+0xFF386EB6,
+0xFF386EB6,
+0xFF386EB6,
+0xFF3770B7,
+0xFF3770B7,
+0xFF386EB6,
+0xFF396FB7,
+0xFF396FB7,
+0xFF396FB7,
+0xFF3871B8,
+0xFF3871B8,
+0xFF3871B8,
+0xFF3871B8,
+0xFF3972B9,
+0xFF3972B9,
+0xFF3974BA,
+0xFF3A75BB,
+0xFF3A75BB,
+0xFF3974BA,
+0xFF3974BA,
+0xFF3974BA,
+0xFF3C75BC,
+0xFF3C75BC,
+0xFF3B76BC,
+0xFF3B76BC,
+0xFF3B76BC,
+0xFF3C77BD,
+0xFF3C77BD,
+0xFF3C77BD,
+0xFF3C77BD,
+0xFF3C77BD,
+0xFF3C77BD,
+0xFF3C77BD,
+0xFF3D78BE,
+0xFF3D78BE,
+0xFF3D78BE,
+0xFF3D78BE,
+0xFF3D79BF,
+0xFF3D79BF,
+0xFF3D79BF,
+0xFF3D79BF,
+0xFF3D79BF,
+0xFF3D79BF,
+0xFF3D79BF,
+0xFF3D79BF,
+0xFF3D79BF,
+0xFF3D79BF,
+0xFF3E7AC0,
+0xFF3E7AC0,
+0xFF3E7AC0,
+0xFF3E7AC0,
+0xFF3E7AC0,
+0xFF3E7AC0,
+0xFF3C7BBE,
+0xFF3B7ABD,
+0xFF3B7ABD,
+0xFF3B7ABD,
+0xFF3B7ABD,
+0xFF3B7ABD,
+0xFF3B7ABD,
+0xFF3B7ABD,
+0xFF3B7ABF,
+0xFF3C7BC0,
+0xFF3C7BC0,
+0xFF3C7BC0,
+0xFF3C7BC0,
+0xFF3C7BC0,
+0xFF3C7BC0,
+0xFF3C7BC0,
+0xFF3B7ABF,
+0xFF3C7BC0,
+0xFF3C7BC0,
+0xFF3C7BC0,
+0xFF3C7BC0,
+0xFF3C7BC0,
+0xFF3C7BC0,
+0xFF3C7BC0,
+0xFF3C7BC0,
+0xFF3C7BC0,
+0xFF3C7BC0,
+0xFF3D7CC1,
+0xFF3D7CC1,
+0xFF3D7CC1,
+0xFF3C7BC0,
+0xFF3C7BC0,
+0xFF3D7CBF,
+0xFF3D7CBF,
+0xFF3D7CBF,
+0xFF3D7CBF,
+0xFF3D7CBF,
+0xFF3D7CBF,
+0xFF3D7CBF,
+0xFF3D7CBF,
+0xFF3D7CBF,
+0xFF3D7CBF,
+0xFF3D7CBF,
+0xFF3D7CBF,
+0xFF3D7CBF,
+0xFF3D7CBF,
+0xFF3D7CBF,
+0xFF3E7DC0,
+0xFF3C7DC1,
+0xFF3C7DC1,
+0xFF3C7DC1,
+0xFF3C7DC1,
+0xFF3C7DC1,
+0xFF3C7DC1,
+0xFF3C7DC1,
+0xFF3C7DC1,
+0xFF3C7DC1,
+0xFF3C7DC1,
+0xFF3C7DC1,
+0xFF3C7DC1,
+0xFF3C7DC1,
+0xFF3C7DC1,
+0xFF3C7DC1,
+0xFF3C7DBF,
+0xFF3B7FC0,
+0xFF3D7EC0,
+0xFF3F7BC1,
+0xFF4179C3,
+0xFF417AC1,
+0xFF407BBD,
+0xFF3D7DBB,
+0xFF3C7DBD,
+0xFF3B7BC2,
+0xFF3B7BC5,
+0xFF407ECB,
+0xFF3C7AC5,
+0xFF3D7CC3,
+0xFF3978BD,
+0xFF4482CB,
+0xFF447AC0,
+0xFF406AA6,
+0xFF315F9D,
+0xFF0B4A99,
+0xFF194E9C,
+0xFF2F3E77,
+0xFF45274B,
+0xFF7A2837,
+0xFF7E261C,
+0xFF592400,
+0xFFB09B5A,
+0xFF8F9741,
+0xFF7A9335,
+0xFF849E45,
+0xFF7C9541,
+0xFF657B29,
+0xFF87933D,
+0xFFB8B858,
+0xFFD8C775,
+0xFF4F2900,
+0xFF4E1F0B,
+0xFF431A16,
+0xFF1D0B19,
+0xFF606F98,
+0xFF5178AF,
+0xFF4B79B7,
+0xFF447BBC,
+0xFF3D7EC0,
+0xFF3B80C5,
+0xFF3E7DC4,
+0xFF407CC4,
+0xFF3D7DC4,
+0xFF3C7FC5,
+0xFF3E7FC3,
+0xFF3E7FC3,
+0xFF3E7FC3,
+0xFF3E7FC3,
+0xFF3E7FC3,
+0xFF3E7FC3,
+0xFF3D7EC2,
+0xFF3D7EC2,
+0xFF3E7FC3,
+0xFF3E7FC3,
+0xFF3D7EC2,
+0xFF3E7FC3,
+0xFF3E7FC3,
+0xFF3E7FC3,
+0xFF3E7FC3,
+0xFF3D7EC2,
+0xFF3E7FC3,
+0xFF3E7FC3,
+0xFF3F7EC3,
+0xFF3E7FC3,
+0xFF3F7EC3,
+0xFF3F7EC3,
+0xFF3F7EC3,
+0xFF3F7EC3,
+0xFF407FC4,
+0xFF3F7EC3,
+0xFF3F7EC3,
+0xFF3F7EC3,
+0xFF3F7EC3,
+0xFF3F7EC3,
+0xFF3F7EC3,
+0xFF3E7DC2,
+0xFF3F7EC3,
+0xFF3F7EC3,
+0xFF3F7EC3,
+0xFF3F7EC3,
+0xFF3F7EC3,
+0xFF3F7EC3,
+0xFF3F7EC3,
+0xFF3F7EC3,
+0xFF3F7EC3,
+0xFF3F7EC3,
+0xFF3F7EC3,
+0xFF3F7EC3,
+0xFF3F7EC3,
+0xFF3F7EC3,
+0xFF3F7EC3,
+0xFF3F7EC3,
+0xFF3F7EC3,
+0xFF3E7FC3,
+0xFF3D7EC2,
+0xFF3D7EC2,
+0xFF3D7EC2,
+0xFF3E7FC3,
+0xFF3E7FC3,
+0xFF3D7EC2,
+0xFF3D7EC2,
+0xFF3D7EC2,
+0xFF3D7EC2,
+0xFF3D7EC2,
+0xFF3D7EC2,
+0xFF3D7EC2,
+0xFF3D7EC2,
+0xFF3D7EC2,
+0xFF3B7EC2,
+0xFF3B7EC2,
+0xFF3C7DC1,
+0xFF3C7DC1,
+0xFF3C7DC1,
+0xFF3C7DC1,
+0xFF3B7CC0,
+0xFF3B7CC0,
+0xFF3B7CC0,
+0xFF3B7CC0,
+0xFF3C7BC0,
+0xFF3B7ABF,
+0xFF3B7ABF,
+0xFF3B7ABF,
+0xFF3A79BE,
+0xFF3A79BE,
+0xFF3B7ABF,
+0xFF3B7ABF,
+0xFF3D79BF,
+0xFF3D79BF,
+0xFF3D79C1,
+0xFF3D79C1,
+0xFF3D77C0,
+0xFF3D77C0,
+0xFF3C76BF,
+0xFF3C76BF,
+0xFF3C76BF,
+0xFF3C76BF,
+0xFF3C76BF,
+0xFF3B75BE,
+0xFF3B75BE,
+0xFF3B75BE,
+0xFF3A76BE,
+0xFF3A76BE,
+0xFF3975BD,
+0xFF3975BD,
+0xFF3874BC,
+0xFF3773BB,
+0xFF3773BB,
+0xFF3773BB,
+0xFF3773BB,
+0xFF3672BA,
+0xFF3771BA,
+0xFF3771BA,
+0xFF3671B7,
+0xFF3671B7,
+0xFF3570B6,
+0xFF3570B6,
+0xFF366FB6,
+0xFF386EB6,
+0xFF386EB6,
+0xFF376DB5,
+0xFF376DB5,
+0xFF376DB5,
+0xFF386CB5,
+0xFF386CB5,
+0xFF386CB5,
+0xFF386CB5,
+0xFF376BB4,
+0xFF376BB4,
+0xFF376BB4,
+0xFF366AB3,
+0xFF386AB3,
+0xFF386AB3,
+0xFF3564AA,
+0xFF3665AB,
+0xFF3665AB,
+0xFF3665AB,
+0xFF3766AC,
+0xFF3766AC,
+0xFF3667AC,
+0xFF3667AC,
+0xFF3667AC,
+0xFF3768AD,
+0xFF3768AD,
+0xFF3869AE,
+0xFF3869AE,
+0xFF3869AE,
+0xFF396AAF,
+0xFF396AAF,
+0xFF3A6AB2,
+0xFF3A6AB2,
+0xFF396BB2,
+0xFF3A6CB3,
+0xFF396BB2,
+0xFF396BB2,
+0xFF386DB3,
+0xFF386DB3,
+0xFF386DB3,
+0xFF396EB4,
+0xFF386EB6,
+0xFF386EB6,
+0xFF3770B7,
+0xFF3770B7,
+0xFF3770B7,
+0xFF3770B7,
+0xFF396FB7,
+0xFF396FB7,
+0xFF396FB7,
+0xFF3A70B8,
+0xFF3972B9,
+0xFF3972B9,
+0xFF3A73BA,
+0xFF3A73BA,
+0xFF3A73BA,
+0xFF3A73BA,
+0xFF3974BA,
+0xFF3A75BB,
+0xFF3A75BB,
+0xFF3A75BB,
+0xFF3A75BB,
+0xFF3A75BB,
+0xFF3B76BC,
+0xFF3B76BC,
+0xFF3B76BC,
+0xFF3C77BD,
+0xFF3C77BD,
+0xFF3C77BD,
+0xFF3D78BE,
+0xFF3D78BE,
+0xFF3C77BD,
+0xFF3D78BE,
+0xFF3D78BE,
+0xFF3D78BE,
+0xFF3E79BF,
+0xFF3E79BF,
+0xFF3E79BF,
+0xFF3F7AC0,
+0xFF3E7AC0,
+0xFF3D79BF,
+0xFF3D79BF,
+0xFF3D79BF,
+0xFF3D79BF,
+0xFF3D79BF,
+0xFF3E7AC0,
+0xFF3E7AC0,
+0xFF3B7ABF,
+0xFF3B7ABF,
+0xFF3C7BC0,
+0xFF3C7BC0,
+0xFF3C7BC0,
+0xFF3C7BC0,
+0xFF3C7BC0,
+0xFF3D7CC1,
+0xFF3C7BBE,
+0xFF3C7BBE,
+0xFF3C7BBE,
+0xFF3C7BBE,
+0xFF3C7BBE,
+0xFF3C7BBE,
+0xFF3C7BBE,
+0xFF3C7BBE,
+0xFF3C7BBE,
+0xFF3C7BBE,
+0xFF3C7BBE,
+0xFF3C7BBE,
+0xFF3C7BBE,
+0xFF3C7BBE,
+0xFF3C7BC0,
+0xFF3C7BC0,
+0xFF3C7BBE,
+0xFF3D7CBF,
+0xFF3D7CBF,
+0xFF3D7CBF,
+0xFF3D7CBF,
+0xFF3D7CBF,
+0xFF3D7CBF,
+0xFF3E7DC0,
+0xFF3D7CBF,
+0xFF3D7CBF,
+0xFF3D7CBF,
+0xFF3D7CBF,
+0xFF3D7CBF,
+0xFF3D7CBF,
+0xFF3D7CBF,
+0xFF3D7CBF,
+0xFF3E7DC0,
+0xFF3E7DC0,
+0xFF3D7CBF,
+0xFF3D7CBF,
+0xFF3D7CBF,
+0xFF3E7DC0,
+0xFF3E7DC0,
+0xFF3E7DC0,
+0xFF3D7CBF,
+0xFF3E7DC0,
+0xFF3E7DC0,
+0xFF3E7DC0,
+0xFF3D7EC0,
+0xFF3D7EC0,
+0xFF3D7EC0,
+0xFF3D7EC0,
+0xFF3D7EC2,
+0xFF3D7EC2,
+0xFF3D7EC2,
+0xFF3D7EC2,
+0xFF3D7EC2,
+0xFF3D7EC2,
+0xFF3D7EC2,
+0xFF3D7EC2,
+0xFF3C7DC1,
+0xFF3C7DC1,
+0xFF3D7EC2,
+0xFF3D7EC2,
+0xFF3D7EC2,
+0xFF3D7EC2,
+0xFF3C7DC1,
+0xFF3C7DC1,
+0xFF3C7FC3,
+0xFF3C7FC3,
+0xFF3E7EC5,
+0xFF3D7DC5,
+0xFF3B7EC4,
+0xFF3A7FC2,
+0xFF3D7EBE,
+0xFF3E7FBF,
+0xFF407CC2,
+0xFF4180C7,
+0xFF3D7DC7,
+0xFF3C7FC6,
+0xFF3E81C5,
+0xFF4084C3,
+0xFF387CB9,
+0xFF417FBA,
+0xFF4C7FB8,
+0xFF3F71AE,
+0xFF003981,
+0xFF0F4791,
+0xFF234987,
+0xFF33325E,
+0xFF612638,
+0xFF691C14,
+0xFF602A04,
+0xFFB69D5D,
+0xFF878C3A,
+0xFF81983E,
+0xFF829A46,
+0xFF7B933F,
+0xFF657922,
+0xFFA1B14F,
+0xFFC3CB5B,
+0xFFC3C055,
+0xFFBDAA5D,
+0xFF3C1A00,
+0xFF441406,
+0xFF360B14,
+0xFF270F29,
+0xFF757AA2,
+0xFF547DB3,
+0xFF427EBD,
+0xFF3C7DC1,
+0xFF3E7EC5,
+0xFF407FC2,
+0xFF3E7EBE,
+0xFF3B7EC2,
+0xFF3C81C4,
+0xFF3E7FC3,
+0xFF3F7EC3,
+0xFF3F7EC3,
+0xFF3F7EC3,
+0xFF3F7EC3,
+0xFF3F7EC3,
+0xFF3F7EC3,
+0xFF3F7EC3,
+0xFF407FC4,
+0xFF407FC4,
+0xFF3F7EC3,
+0xFF3F7EC3,
+0xFF407FC4,
+0xFF407FC4,
+0xFF407FC4,
+0xFF3F7EC3,
+0xFF407FC4,
+0xFF407FC4,
+0xFF427EC4,
+0xFF3F7EC3,
+0xFF417DC3,
+0xFF427EC4,
+0xFF427EC4,
+0xFF427EC4,
+0xFF437FC5,
+0xFF427EC4,
+0xFF427EC4,
+0xFF427EC4,
+0xFF427EC4,
+0xFF427EC4,
+0xFF427EC4,
+0xFF427EC4,
+0xFF427EC4,
+0xFF427EC4,
+0xFF427EC4,
+0xFF427EC4,
+0xFF427EC4,
+0xFF427EC4,
+0xFF427EC4,
+0xFF427EC4,
+0xFF427EC4,
+0xFF427EC4,
+0xFF427EC4,
+0xFF427EC4,
+0xFF427EC4,
+0xFF427EC4,
+0xFF427EC4,
+0xFF407FC4,
+0xFF407FC4,
+0xFF3F7EC3,
+0xFF3F7EC3,
+0xFF3F7EC3,
+0xFF407FC4,
+0xFF407FC4,
+0xFF3F7EC3,
+0xFF3F7EC3,
+0xFF407FC4,
+0xFF407FC4,
+0xFF407FC4,
+0xFF3F7EC3,
+0xFF3F7EC3,
+0xFF3F7EC3,
+0xFF3F7EC3,
+0xFF3E7FC3,
+0xFF3C7FC3,
+0xFF3C7FC3,
+0xFF3C7FC3,
+0xFF3B7EC2,
+0xFF3B7EC2,
+0xFF3B7EC2,
+0xFF3B7EC2,
+0xFF3B7EC2,
+0xFF3A7DC1,
+0xFF3A7DC1,
+0xFF3C7DC1,
+0xFF3C7DC1,
+0xFF3C7DC1,
+0xFF3B7CC0,
+0xFF3B7CC0,
+0xFF3B7CC0,
+0xFF3C7BC0,
+0xFF3B7ABF,
+0xFF3B7ABF,
+0xFF3B7ABF,
+0xFF3D79C1,
+0xFF3D79C1,
+0xFF3E78C1,
+0xFF3E78C1,
+0xFF3E78C1,
+0xFF3D77C0,
+0xFF3D77C0,
+0xFF3D77C0,
+0xFF3D77C0,
+0xFF3C76BF,
+0xFF3C76BF,
+0xFF3B75BE,
+0xFF3A76BE,
+0xFF3A76BE,
+0xFF3A76BE,
+0xFF3975BD,
+0xFF3975BD,
+0xFF3975BD,
+0xFF3874BC,
+0xFF3874BC,
+0xFF3874BC,
+0xFF3874BC,
+0xFF3773BB,
+0xFF3773BB,
+0xFF3672B8,
+0xFF3672B8,
+0xFF3672B8,
+0xFF3671B7,
+0xFF3770B7,
+0xFF396FB7,
+0xFF396FB7,
+0xFF396FB7,
+0xFF386EB6,
+0xFF386EB6,
+0xFF386CB5,
+0xFF386CB5,
+0xFF386CB5,
+0xFF386CB5,
+0xFF376BB4,
+0xFF376BB4,
+0xFF376BB4,
+0xFF376BB4,
+0xFF366AB3,
+0xFF366AB3,
+0xFF3665AB,
+0xFF3665AB,
+0xFF3665AB,
+0xFF3766AC,
+0xFF3766AC,
+0xFF3766AC,
+0xFF3667AC,
+0xFF3768AD,
+0xFF3768AD,
+0xFF3768AD,
+0xFF3869AE,
+0xFF3869AE,
+0xFF396AAF,
+0xFF396AAF,
+0xFF396AAF,
+0xFF396AAF,
+0xFF3A6AB2,
+0xFF3A6CB3,
+0xFF3A6CB3,
+0xFF3A6CB3,
+0xFF3A6CB3,
+0xFF386DB3,
+0xFF396EB4,
+0xFF396EB4,
+0xFF396EB4,
+0xFF386EB4,
+0xFF386EB6,
+0xFF366FB6,
+0xFF3770B7,
+0xFF3770B7,
+0xFF3770B7,
+0xFF3871B8,
+0xFF396FB7,
+0xFF396FB7,
+0xFF3A70B8,
+0xFF3B71B9,
+0xFF3972B9,
+0xFF3A73BA,
+0xFF3A73BA,
+0xFF3B74BB,
+0xFF3B74BB,
+0xFF3B74BB,
+0xFF3A75BB,
+0xFF3A75BB,
+0xFF3A75BB,
+0xFF3B76BC,
+0xFF3C77BD,
+0xFF3C77BD,
+0xFF3B76BC,
+0xFF3B76BC,
+0xFF3C77BD,
+0xFF3C77BD,
+0xFF3D78BE,
+0xFF3D78BE,
+0xFF3E79BF,
+0xFF3E79BF,
+0xFF3D78BE,
+0xFF3D78BE,
+0xFF3D78BE,
+0xFF3E79BF,
+0xFF3E79BF,
+0xFF3F7AC0,
+0xFF3F7AC0,
+0xFF3F7BC1,
+0xFF3E7AC0,
+0xFF3E7AC0,
+0xFF3D79BF,
+0xFF3D79BF,
+0xFF3D79BF,
+0xFF3D79BF,
+0xFF3E7AC0,
+0xFF3E7AC0,
+0xFF3B7ABF,
+0xFF3C7BC0,
+0xFF3C7BC0,
+0xFF3C7BC0,
+0xFF3B7ABF,
+0xFF3C7BC0,
+0xFF3C7BC0,
+0xFF3D7CC1,
+0xFF3C7BBE,
+0xFF3C7BBE,
+0xFF3C7BBE,
+0xFF3D7CBF,
+0xFF3D7CBF,
+0xFF3D7CBF,
+0xFF3D7CBF,
+0xFF3C7BBE,
+0xFF3D7CBF,
+0xFF3D7CBF,
+0xFF3D7CBF,
+0xFF3D7CBF,
+0xFF3D7CBF,
+0xFF3D7CBF,
+0xFF3D7CC1,
+0xFF3D7CC1,
+0xFF3D7CBF,
+0xFF3D7CBF,
+0xFF3E7DC0,
+0xFF3E7DC0,
+0xFF3E7DC0,
+0xFF3E7DC0,
+0xFF3E7DC0,
+0xFF3E7DC0,
+0xFF3E7DC0,
+0xFF3E7DC0,
+0xFF3E7DC0,
+0xFF3E7DC0,
+0xFF3E7DC0,
+0xFF3E7DC0,
+0xFF3E7DC0,
+0xFF3E7DC0,
+0xFF3E7DC0,
+0xFF3D7EC0,
+0xFF3E7DC0,
+0xFF3C7DBF,
+0xFF3E7DC0,
+0xFF3E7DC0,
+0xFF3E7DC0,
+0xFF3E7DC0,
+0xFF3D7CBF,
+0xFF3E7DC0,
+0xFF3E7DC0,
+0xFF3E7DC0,
+0xFF3D7EC0,
+0xFF3D7EC0,
+0xFF3D7EC0,
+0xFF3E7FC1,
+0xFF3D7EC2,
+0xFF3D7EC2,
+0xFF3D7EC2,
+0xFF3D7EC2,
+0xFF3D7EC2,
+0xFF3D7EC2,
+0xFF3D7EC2,
+0xFF3D7EC2,
+0xFF3D7EC2,
+0xFF3D7EC2,
+0xFF3D7EC2,
+0xFF3D7EC2,
+0xFF3D7EC2,
+0xFF3D7EC2,
+0xFF3D7EC2,
+0xFF3D7EC2,
+0xFF3E7FC3,
+0xFF3E7FC3,
+0xFF3D7DC4,
+0xFF3B7EC4,
+0xFF3A7FC4,
+0xFF3A7FC2,
+0xFF3B7FC0,
+0xFF3E7EBE,
+0xFF3D7ABD,
+0xFF4382C7,
+0xFF397CC3,
+0xFF3B7EC4,
+0xFF3B7FC0,
+0xFF397DBA,
+0xFF3C81BC,
+0xFF3E7FB7,
+0xFF6499CF,
+0xFF5183BE,
+0xFF01377D,
+0xFF0A428C,
+0xFF104589,
+0xFF283C6F,
+0xFF53273E,
+0xFF621F19,
+0xFF531E00,
+0xFF997B45,
+0xFF919447,
+0xFF7D943C,
+0xFF889F4F,
+0xFF7A913F,
+0xFF667D25,
+0xFF96A844,
+0xFFB2BF49,
+0xFFB5BD46,
+0xFFB6B44F,
+0xFFAD9950,
+0xFF3D0F00,
+0xFF4A130E,
+0xFF3B0F1C,
+0xFF271430,
+0xFF6A7FAA,
+0xFF507FB5,
+0xFF417DBC,
+0xFF3F80C2,
+0xFF4081C1,
+0xFF3E80BD,
+0xFF3A7FC0,
+0xFF3D80C4,
+0xFF4180C5,
+0xFF4180C5,
+0xFF4180C5,
+0xFF407FC2,
+0xFF407FC2,
+0xFF407FC2,
+0xFF427EC6,
+0xFF427EC6,
+0xFF4180C5,
+0xFF3F80C4,
+0xFF407FC2,
+0xFF407FC2,
+0xFF4380C3,
+0xFF437FC5,
+0xFF407FC4,
+0xFF407FC4,
+0xFF437FC5,
+0xFF427EC4,
+0xFF427EC4,
+0xFF427EC4,
+0xFF427EC4,
+0xFF427EC4,
+0xFF427EC4,
+0xFF437FC5,
+0xFF437FC5,
+0xFF437FC5,
+0xFF427EC4,
+0xFF437FC5,
+0xFF437FC5,
+0xFF4480C6,
+0xFF4480C6,
+0xFF437FC5,
+0xFF427EC4,
+0xFF427EC4,
+0xFF427EC4,
+0xFF427EC4,
+0xFF427EC4,
+0xFF427EC4,
+0xFF427EC4,
+0xFF437FC5,
+0xFF437FC5,
+0xFF427EC4,
+0xFF427EC4,
+0xFF427EC4,
+0xFF427EC4,
+0xFF437FC5,
+0xFF437FC5,
+0xFF437FC5,
+0xFF407FC4,
+0xFF407FC4,
+0xFF407FC4,
+0xFF407FC4,
+0xFF4180C5,
+0xFF4180C5,
+0xFF407FC4,
+0xFF3F7EC3,
+0xFF4180C5,
+0xFF4180C5,
+0xFF407FC4,
+0xFF407FC4,
+0xFF407FC4,
+0xFF407FC4,
+0xFF407FC4,
+0xFF407FC4,
+0xFF3F80C4,
+0xFF3F80C4,
+0xFF3F80C4,
+0xFF3E7FC3,
+0xFF3E7FC3,
+0xFF3E7FC3,
+0xFF3D7EC2,
+0xFF3D7EC2,
+0xFF3D7EC2,
+0xFF3D7EC2,
+0xFF3D7EC2,
+0xFF3D7EC2,
+0xFF3D7EC2,
+0xFF3C7DC1,
+0xFF3C7DC1,
+0xFF3C7DC1,
+0xFF3C7BC0,
+0xFF3C7BC0,
+0xFF3B7ABF,
+0xFF3B7ABF,
+0xFF3E7AC2,
+0xFF3E7AC2,
+0xFF3D79C1,
+0xFF3D79C1,
+0xFF3E78C1,
+0xFF3E78C1,
+0xFF3E78C1,
+0xFF3E78C1,
+0xFF3D77C0,
+0xFF3D77C0,
+0xFF3C76BF,
+0xFF3C76BF,
+0xFF3C76BF,
+0xFF3A76BE,
+0xFF3B75BE,
+0xFF3A76BE,
+0xFF3A76BE,
+0xFF3A76BE,
+0xFF3975BD,
+0xFF3975BD,
+0xFF3975BD,
+0xFF3975BD,
+0xFF3874BC,
+0xFF3874BC,
+0xFF3773B9,
+0xFF3773B9,
+0xFF3672B8,
+0xFF3772B8,
+0xFF3871B8,
+0xFF3A70B8,
+0xFF3A70B8,
+0xFF3A70B8,
+0xFF3A70B8,
+0xFF396FB7,
+0xFF396DB6,
+0xFF386CB5,
+0xFF396DB6,
+0xFF386CB5,
+0xFF376BB4,
+0xFF376BB4,
+0xFF376BB4,
+0xFF376BB4,
+0xFF366AB3,
+0xFF366AB3,
+0xFF3566AB,
+0xFF3667AC,
+0xFF3667AC,
+0xFF3768AD,
+0xFF3768AD,
+0xFF3667AC,
+0xFF3768AD,
+0xFF3768AD,
+0xFF3869AE,
+0xFF3869AE,
+0xFF3868B0,
+0xFF3969B1,
+0xFF3A6AB2,
+0xFF3A6AB2,
+0xFF3A6AB2,
+0xFF3969B1,
+0xFF3A6CB3,
+0xFF386DB3,
+0xFF386DB3,
+0xFF396EB4,
+0xFF396EB4,
+0xFF396EB4,
+0xFF396EB4,
+0xFF386EB4,
+0xFF396FB7,
+0xFF3770B7,
+0xFF3871B8,
+0xFF3871B8,
+0xFF3770B7,
+0xFF3671B7,
+0xFF3772B8,
+0xFF3772B8,
+0xFF3972B7,
+0xFF3972B7,
+0xFF3972B7,
+0xFF3A73B8,
+0xFF3A73B8,
+0xFF3B74B9,
+0xFF3B74B9,
+0xFF3C75BA,
+0xFF3B76BA,
+0xFF3B76BA,
+0xFF3B76BA,
+0xFF3B76BA,
+0xFF3B76BA,
+0xFF3B76BA,
+0xFF3C77BB,
+0xFF3C77BB,
+0xFF3D76BD,
+0xFF3E77BE,
+0xFF3D78BE,
+0xFF3E79BF,
+0xFF3E79BF,
+0xFF3E79BF,
+0xFF3E79BF,
+0xFF3F7AC0,
+0xFF3E79BD,
+0xFF3E79BD,
+0xFF3E79BD,
+0xFF3F7ABE,
+0xFF3E7BBE,
+0xFF3E7BBE,
+0xFF3E7BBE,
+0xFF3D7ABD,
+0xFF3E7BBE,
+0xFF3C7BBE,
+0xFF3C7BBE,
+0xFF3C7BBE,
+0xFF3C7BBE,
+0xFF3D7CBF,
+0xFF3D7CBF,
+0xFF3D7CBF,
+0xFF3D7CBF,
+0xFF3D7CBF,
+0xFF3D7CBF,
+0xFF3D7CBF,
+0xFF3D7CBF,
+0xFF3D7CBF,
+0xFF3D7CBF,
+0xFF3D7CBF,
+0xFF3D7CC1,
+0xFF3D7CC1,
+0xFF3D7CC1,
+0xFF3D7CC1,
+0xFF3D7CC1,
+0xFF3D7CC1,
+0xFF3D7CC1,
+0xFF3D7CC1,
+0xFF3E7DC2,
+0xFF3E7DC2,
+0xFF3E7DC2,
+0xFF3E7DC2,
+0xFF3E7DC2,
+0xFF3E7DC2,
+0xFF3E7DC2,
+0xFF3E7DC2,
+0xFF3C7DC1,
+0xFF3C7DC1,
+0xFF3D7EC2,
+0xFF3D7EC2,
+0xFF3D7EC2,
+0xFF3D7EC2,
+0xFF3D7EC2,
+0xFF3D7EC2,
+0xFF3E7FC3,
+0xFF3E7FC3,
+0xFF3D7EC2,
+0xFF3D7EC2,
+0xFF3C7DC1,
+0xFF3D7EC2,
+0xFF3E7FC3,
+0xFF3E7FC3,
+0xFF3C7DBF,
+0xFF3A7EBF,
+0xFF3C7DBF,
+0xFF3A7EBF,
+0xFF3D7EC0,
+0xFF3D7EC0,
+0xFF3D7EC0,
+0xFF3D7EC0,
+0xFF3E7FC1,
+0xFF3E7FC1,
+0xFF3E7FC1,
+0xFF3E7FC1,
+0xFF3E7FC1,
+0xFF3E7FC1,
+0xFF3F7EC1,
+0xFF3F7EC1,
+0xFF3E7FC1,
+0xFF3E7FC1,
+0xFF3E7FC1,
+0xFF3E7FC1,
+0xFF3E7FC1,
+0xFF3D7EC0,
+0xFF3E7FC1,
+0xFF3E7FC1,
+0xFF3D7EC0,
+0xFF3D7EC0,
+0xFF3E7FC1,
+0xFF3E7FC1,
+0xFF3E7FC1,
+0xFF3E7FC1,
+0xFF3E7FC1,
+0xFF3D7EC0,
+0xFF3E7DC0,
+0xFF407FC2,
+0xFF427FC2,
+0xFF417EC1,
+0xFF3F7EC1,
+0xFF3F80C2,
+0xFF3F7EC1,
+0xFF3E7DC0,
+0xFF4180C5,
+0xFF4081C5,
+0xFF3C7CC3,
+0xFF3F80C4,
+0xFF3F7EC1,
+0xFF4080C0,
+0xFF3E7EBC,
+0xFF427FB8,
+0xFF689DD1,
+0xFF487BB4,
+0xFF386AB3,
+0xFF073C8C,
+0xFF04428F,
+0xFF274782,
+0xFF45233E,
+0xFF632526,
+0xFF531B0A,
+0xFF755429,
+0xFF989953,
+0xFF839644,
+0xFF859B50,
+0xFF7B9345,
+0xFF617B24,
+0xFF96AC4A,
+0xFFB9CA58,
+0xFFAEBB45,
+0xFFABB542,
+0xFFBFBB58,
+0xFF8E6B2B,
+0xFF431200,
+0xFF3E0E0E,
+0xFF2C091D,
+0xFF2C223B,
+0xFF7789AF,
+0xFF4C7DB5,
+0xFF3F81BE,
+0xFF3B81BF,
+0xFF3C82C0,
+0xFF3C80C1,
+0xFF4081C5,
+0xFF437FC7,
+0xFF437FC5,
+0xFF4081C3,
+0xFF4081C1,
+0xFF4181BF,
+0xFF4380C1,
+0xFF467EC9,
+0xFF457ECB,
+0xFF3F7FC6,
+0xFF3D81C2,
+0xFF3F80C0,
+0xFF4080C0,
+0xFF437EC0,
+0xFF447FC3,
+0xFF437FC7,
+0xFF4180C7,
+0xFF4480C6,
+0xFF4481C4,
+0xFF4380C3,
+0xFF4380C3,
+0xFF4380C3,
+0xFF4380C3,
+0xFF4380C3,
+0xFF4380C3,
+0xFF4481C4,
+0xFF4380C3,
+0xFF427FC2,
+0xFF4380C3,
+0xFF4481C4,
+0xFF4481C4,
+0xFF4481C4,
+0xFF4380C3,
+0xFF4380C3,
+0xFF4481C4,
+0xFF4481C4,
+0xFF4481C4,
+0xFF4481C4,
+0xFF4481C4,
+0xFF4481C4,
+0xFF4481C4,
+0xFF4481C4,
+0xFF4380C3,
+0xFF4380C3,
+0xFF4380C3,
+0xFF4380C3,
+0xFF4380C3,
+0xFF4380C3,
+0xFF4380C3,
+0xFF4380C3,
+0xFF4380C3,
+0xFF4380C3,
+0xFF4380C3,
+0xFF4380C3,
+0xFF4380C3,
+0xFF4380C3,
+0xFF4380C3,
+0xFF4481C4,
+0xFF4380C3,
+0xFF4380C3,
+0xFF4380C3,
+0xFF4380C3,
+0xFF4380C3,
+0xFF4380C3,
+0xFF427FC2,
+0xFF427FC2,
+0xFF427FC2,
+0xFF407FC2,
+0xFF407FC2,
+0xFF407FC2,
+0xFF407FC2,
+0xFF407FC2,
+0xFF407FC2,
+0xFF3F7EC1,
+0xFF3F7EC1,
+0xFF3F7EC1,
+0xFF3E7DC0,
+0xFF3E7DC0,
+0xFF3E7DC0,
+0xFF3E7DC0,
+0xFF3D7CBF,
+0xFF3E7DC0,
+0xFF3D7CBF,
+0xFF3D7CC1,
+0xFF3D7CC1,
+0xFF3D7CC1,
+0xFF3D7CC1,
+0xFF3C7BC0,
+0xFF3C7BC0,
+0xFF3D79BF,
+0xFF3E7AC0,
+0xFF3E7AC0,
+0xFF3E7AC0,
+0xFF3F7AC0,
+0xFF3E79BF,
+0xFF3D78BE,
+0xFF3D78BE,
+0xFF3E79BF,
+0xFF3D78BE,
+0xFF3D76BD,
+0xFF3B76BC,
+0xFF3B76BC,
+0xFF3B76BC,
+0xFF3B76BC,
+0xFF3B76BC,
+0xFF3B75BE,
+0xFF3A74BD,
+0xFF3A74BD,
+0xFF3A74BD,
+0xFF3973BC,
+0xFF3872BB,
+0xFF3872BB,
+0xFF3872BB,
+0xFF3772B8,
+0xFF3871B8,
+0xFF3871B8,
+0xFF3871B8,
+0xFF3770B7,
+0xFF3770B7,
+0xFF396FB5,
+0xFF396FB5,
+0xFF386EB4,
+0xFF386EB4,
+0xFF396EB4,
+0xFF386DB3,
+0xFF386DB3,
+0xFF386DB3,
+0xFF376CB2,
+0xFF376CB2,
+0xFF3667AC,
+0xFF3667AC,
+0xFF3768AD,
+0xFF3768AD,
+0xFF3768AD,
+0xFF3768AD,
+0xFF3768AD,
+0xFF3869AE,
+0xFF396AAF,
+0xFF396AAF,
+0xFF3969B1,
+0xFF3A6AB2,
+0xFF3B6BB3,
+0xFF3B6BB3,
+0xFF3A6AB2,
+0xFF396BB2,
+0xFF386DB3,
+0xFF386DB3,
+0xFF386DB3,
+0xFF396EB4,
+0xFF396EB4,
+0xFF396EB4,
+0xFF386EB4,
+0xFF386EB4,
+0xFF3770B7,
+0xFF3770B7,
+0xFF3871B8,
+0xFF3871B8,
+0xFF3772B8,
+0xFF3772B8,
+0xFF3772B8,
+0xFF3873B9,
+0xFF3972B7,
+0xFF3A73B8,
+0xFF3A73B8,
+0xFF3A73B8,
+0xFF3B74B9,
+0xFF3B74B9,
+0xFF3C75BA,
+0xFF3C75BA,
+0xFF3B76BA,
+0xFF3B76BA,
+0xFF3B76BA,
+0xFF3B76BA,
+0xFF3B76BA,
+0xFF3B76BA,
+0xFF3C77BB,
+0xFF3C77BB,
+0xFF3D78BE,
+0xFF3E79BF,
+0xFF3E79BF,
+0xFF3E79BF,
+0xFF3E79BF,
+0xFF3F7AC0,
+0xFF3F7AC0,
+0xFF3F7AC0,
+0xFF3F7ABE,
+0xFF3F7ABE,
+0xFF3F7ABE,
+0xFF407BBF,
+0xFF3F7CBF,
+0xFF3F7CBF,
+0xFF3F7CBF,
+0xFF3E7BBE,
+0xFF3D7CBF,
+0xFF3D7CBF,
+0xFF3D7CBF,
+0xFF3D7CBF,
+0xFF3E7DC0,
+0xFF3E7DC0,
+0xFF3E7DC0,
+0xFF3E7DC0,
+0xFF3E7DC0,
+0xFF3E7DC0,
+0xFF3E7DC0,
+0xFF3E7DC0,
+0xFF3E7DC0,
+0xFF3E7DC0,
+0xFF3E7DC0,
+0xFF3E7DC0,
+0xFF3E7DC2,
+0xFF3E7DC2,
+0xFF3E7DC2,
+0xFF3E7DC2,
+0xFF3E7DC2,
+0xFF3E7DC2,
+0xFF3E7DC2,
+0xFF3E7DC2,
+0xFF3E7DC2,
+0xFF3E7DC2,
+0xFF3E7DC2,
+0xFF3E7DC2,
+0xFF3E7DC2,
+0xFF3E7DC2,
+0xFF3E7DC2,
+0xFF3E7DC2,
+0xFF3E7DC2,
+0xFF3D7EC2,
+0xFF3E7DC2,
+0xFF3D7EC2,
+0xFF3E7DC2,
+0xFF3D7EC2,
+0xFF3E7DC2,
+0xFF3D7EC2,
+0xFF3F7EC3,
+0xFF3E7FC3,
+0xFF3F7EC3,
+0xFF3D7EC2,
+0xFF3E7DC2,
+0xFF3D7EC2,
+0xFF3F7EC3,
+0xFF3E7FC3,
+0xFF3D7EC0,
+0xFF3B7FC0,
+0xFF3D7EC0,
+0xFF3C80C1,
+0xFF3E7FC1,
+0xFF3E7FC1,
+0xFF3E7FC1,
+0xFF3E7FC1,
+0xFF3E7FC1,
+0xFF3E7FC1,
+0xFF3E7FC1,
+0xFF3E7FC1,
+0xFF3F7EC1,
+0xFF3F7EC1,
+0xFF3F7EC1,
+0xFF3F7EC1,
+0xFF407FC2,
+0xFF3F80C2,
+0xFF3F80C2,
+0xFF3E7FC1,
+0xFF3E7FC1,
+0xFF3E7FC1,
+0xFF3E7FC1,
+0xFF3F80C2,
+0xFF3E7FC1,
+0xFF3F80C2,
+0xFF3F80C2,
+0xFF3F80C2,
+0xFF3F80C2,
+0xFF3F80C2,
+0xFF3F80C2,
+0xFF407FC2,
+0xFF4080C0,
+0xFF4380C1,
+0xFF447FC1,
+0xFF437EC0,
+0xFF427FC0,
+0xFF4380C1,
+0xFF4180C3,
+0xFF407FC2,
+0xFF3F80C4,
+0xFF4081C5,
+0xFF3E7FC3,
+0xFF4182C6,
+0xFF4380C3,
+0xFF417EBF,
+0xFF4480BF,
+0xFF407BB7,
+0xFF669BD1,
+0xFF4D80B9,
+0xFF5686CE,
+0xFF003381,
+0xFF084797,
+0xFF224887,
+0xFF452C4A,
+0xFF581F25,
+0xFF581F16,
+0xFF6B4725,
+0xFF949551,
+0xFF819443,
+0xFF859B50,
+0xFF80984C,
+0xFF637C28,
+0xFF7B9333,
+0xFFB9CB5D,
+0xFFB0BF48,
+0xFFA1B437,
+0xFFAFB344,
+0xFFC2AC56,
+0xFF5E3501,
+0xFF481407,
+0xFF370510,
+0xFF3B1725,
+0xFF382E49,
+0xFF6F87B7,
+0xFF4B7CB7,
+0xFF4583C0,
+0xFF468AC9,
+0xFF3B7CBE,
+0xFF407FC2,
+0xFF4580C6,
+0xFF4481C4,
+0xFF4182C2,
+0xFF4183C0,
+0xFF4481C0,
+0xFF467FC2,
+0xFF497DC8,
+0xFF487DC9,
+0xFF4180C7,
+0xFF3E81C5,
+0xFF4081C1,
+0xFF4181BF,
+0xFF4380BF,
+0xFF4580C4,
+0xFF4480C8,
+0xFF4480C8,
+0xFF4480C6,
+0xFF4481C4,
+0xFF4481C4,
+0xFF4481C4,
+0xFF4481C4,
+0xFF4481C4,
+0xFF4380C3,
+0xFF4380C3,
+0xFF4582C5,
+0xFF4481C4,
+0xFF4380C3,
+0xFF4380C3,
+0xFF4481C4,
+0xFF4481C4,
+0xFF4380C3,
+0xFF427FC2,
+0xFF4481C4,
+0xFF4481C4,
+0xFF4481C4,
+0xFF4481C4,
+0xFF4481C4,
+0xFF4481C4,
+0xFF4481C4,
+0xFF4481C4,
+0xFF4481C4,
+0xFF4481C4,
+0xFF4380C3,
+0xFF4481C4,
+0xFF4481C4,
+0xFF4481C4,
+0xFF4481C4,
+0xFF4380C3,
+0xFF4380C3,
+0xFF4380C3,
+0xFF4380C3,
+0xFF4380C3,
+0xFF4481C4,
+0xFF4481C4,
+0xFF4481C4,
+0xFF4481C4,
+0xFF4481C4,
+0xFF4481C4,
+0xFF4481C4,
+0xFF4481C4,
+0xFF4380C3,
+0xFF4380C3,
+0xFF4380C3,
+0xFF4380C3,
+0xFF447FC3,
+0xFF447FC3,
+0xFF4380C3,
+0xFF4380C3,
+0xFF4380C3,
+0xFF4380C3,
+0xFF4380C3,
+0xFF4380C3,
+0xFF407FC2,
+0xFF407FC2,
+0xFF407FC2,
+0xFF3F7EC1,
+0xFF3F7EC1,
+0xFF3F7EC1,
+0xFF3E7DC0,
+0xFF3E7DC0,
+0xFF3E7DC0,
+0xFF3E7DC0,
+0xFF3E7DC2,
+0xFF3E7DC2,
+0xFF3E7DC2,
+0xFF3D7CC1,
+0xFF3D7CC1,
+0xFF3C7BC0,
+0xFF3C7BC0,
+0xFF3C7BC0,
+0xFF3E7AC0,
+0xFF3E7AC0,
+0xFF3F7AC0,
+0xFF3F7AC0,
+0xFF3F7AC0,
+0xFF3F7AC0,
+0xFF3F78BF,
+0xFF3F78BF,
+0xFF3E77BE,
+0xFF3E77BE,
+0xFF3C77BD,
+0xFF3C77BD,
+0xFF3C77BD,
+0xFF3B76BC,
+0xFF3C76BF,
+0xFF3C76BF,
+0xFF3B75BE,
+0xFF3B75BE,
+0xFF3A74BD,
+0xFF3A74BD,
+0xFF3973BC,
+0xFF3973BC,
+0xFF3873B9,
+0xFF3873B9,
+0xFF3972B9,
+0xFF3972B9,
+0xFF3871B8,
+0xFF3871B8,
+0xFF396FB5,
+0xFF396FB5,
+0xFF396FB5,
+0xFF396FB5,
+0xFF396EB4,
+0xFF396EB4,
+0xFF396EB4,
+0xFF386DB3,
+0xFF386DB3,
+0xFF386DB3,
+0xFF3768AD,
+0xFF3768AD,
+0xFF3869AE,
+0xFF3768AD,
+0xFF3768AD,
+0xFF3869AE,
+0xFF3869AE,
+0xFF396AAF,
+0xFF396AAF,
+0xFF396AAF,
+0xFF396BB2,
+0xFF396BB2,
+0xFF3A6CB3,
+0xFF3A6CB3,
+0xFF3A6CB3,
+0xFF3A6CB3,
+0xFF396EB4,
+0xFF396EB4,
+0xFF396EB4,
+0xFF396EB4,
+0xFF386EB4,
+0xFF396FB5,
+0xFF396FB5,
+0xFF396FB5,
+0xFF3871B6,
+0xFF3871B6,
+0xFF3972B7,
+0xFF3972B7,
+0xFF3772B8,
+0xFF3873B9,
+0xFF3873B9,
+0xFF3873B9,
+0xFF3A73B8,
+0xFF3B74B9,
+0xFF3B74B9,
+0xFF3B74B9,
+0xFF3C75BA,
+0xFF3C75BA,
+0xFF3C75BA,
+0xFF3C75BA,
+0xFF3B76BA,
+0xFF3B76BA,
+0xFF3B76BA,
+0xFF3C77BB,
+0xFF3C77BB,
+0xFF3D78BC,
+0xFF3D78BC,
+0xFF3D78BC,
+0xFF3F7AC0,
+0xFF3E7AC0,
+0xFF3E7AC0,
+0xFF3E7AC0,
+0xFF3E7AC0,
+0xFF3E7AC0,
+0xFF3E7BBE,
+0xFF3E7BBE,
+0xFF3E7BBE,
+0xFF3E7BBE,
+0xFF3E7BBE,
+0xFF3E7BBE,
+0xFF3F7CBF,
+0xFF3F7CBF,
+0xFF3F7CBF,
+0xFF3F7CBF,
+0xFF3D7CBF,
+0xFF3D7CBF,
+0xFF3D7CBF,
+0xFF3E7DC0,
+0xFF3E7DC0,
+0xFF3D7CBF,
+0xFF3D7CBF,
+0xFF3D7CBF,
+0xFF3E7DC0,
+0xFF3E7DC0,
+0xFF3E7DC0,
+0xFF3E7DC0,
+0xFF3E7DC0,
+0xFF3F7EC1,
+0xFF3F7EC1,
+0xFF3F7EC1,
+0xFF3F7EC1,
+0xFF3F7EC1,
+0xFF3F7EC1,
+0xFF3F7EC1,
+0xFF3F7EC1,
+0xFF3F7EC1,
+0xFF3F7EC1,
+0xFF3F7EC1,
+0xFF3F7EC1,
+0xFF3F7EC1,
+0xFF3F7EC1,
+0xFF3F7EC1,
+0xFF3F7EC1,
+0xFF3F7EC1,
+0xFF3F7EC1,
+0xFF3F7EC1,
+0xFF3F7EC1,
+0xFF3F7EC1,
+0xFF417EC1,
+0xFF3F7EC1,
+0xFF417EC1,
+0xFF3F7EC1,
+0xFF417EC1,
+0xFF3F7EC1,
+0xFF427FC2,
+0xFF407FC2,
+0xFF417EC1,
+0xFF3F7EC1,
+0xFF417EC1,
+0xFF3F7EC1,
+0xFF417EC1,
+0xFF3F7EC1,
+0xFF3F7EC1,
+0xFF3F80C2,
+0xFF407FC2,
+0xFF3F80C2,
+0xFF407FC2,
+0xFF407FC2,
+0xFF407FC2,
+0xFF407FC2,
+0xFF407FC2,
+0xFF407FC2,
+0xFF407FC2,
+0xFF407FC2,
+0xFF427FC2,
+0xFF427FC2,
+0xFF427FC2,
+0xFF407FC2,
+0xFF407FC2,
+0xFF4180C3,
+0xFF4180C3,
+0xFF4180C3,
+0xFF407FC2,
+0xFF407FC2,
+0xFF407FC2,
+0xFF4180C3,
+0xFF4180C3,
+0xFF4180C3,
+0xFF4180C3,
+0xFF4281C4,
+0xFF4281C4,
+0xFF4281C4,
+0xFF4180C3,
+0xFF4180C3,
+0xFF4181C1,
+0xFF4282C2,
+0xFF4481C2,
+0xFF4481C2,
+0xFF4481C2,
+0xFF4481C2,
+0xFF4281C4,
+0xFF4180C3,
+0xFF4081C5,
+0xFF4182C6,
+0xFF3F80C4,
+0xFF4384C8,
+0xFF4481C4,
+0xFF427FC0,
+0xFF4783C2,
+0xFF4580BC,
+0xFF629AD5,
+0xFF457BB7,
+0xFF4D80C2,
+0xFF346AB2,
+0xFF003581,
+0xFF1F4381,
+0xFF433050,
+0xFF55212D,
+0xFF5D2321,
+0xFF5F361A,
+0xFF949551,
+0xFF809641,
+0xFF839A4C,
+0xFF889E53,
+0xFF68802C,
+0xFF667E1E,
+0xFFBED060,
+0xFFADBD43,
+0xFFAFBF43,
+0xFFB2B945,
+0xFFB9AF4D,
+0xFF886722,
+0xFF6A2E16,
+0xFF4F0A0D,
+0xFF4D1119,
+0xFF350E23,
+0xFF4D406B,
+0xFF7682BC,
+0xFF5079B7,
+0xFF447DC0,
+0xFF4A85C7,
+0xFF4580C2,
+0xFF4581C0,
+0xFF4581C0,
+0xFF4182C2,
+0xFF4182C2,
+0xFF4580C2,
+0xFF487FC2,
+0xFF4B7EC0,
+0xFF4B7DC2,
+0xFF4580C6,
+0xFF4480C6,
+0xFF4481C2,
+0xFF4282BF,
+0xFF3F84BF,
+0xFF4283C3,
+0xFF4681C7,
+0xFF4680C9,
+0xFF4580C6,
+0xFF4481C4,
+0xFF4481C4,
+0xFF4481C4,
+0xFF4481C4,
+0xFF4481C4,
+0xFF4481C4,
+0xFF4481C4,
+0xFF4582C5,
+0xFF4582C5,
+0xFF4481C4,
+0xFF4481C4,
+0xFF4481C4,
+0xFF4481C4,
+0xFF4481C4,
+0xFF4380C3,
+0xFF4481C4,
+0xFF4481C4,
+0xFF4481C4,
+0xFF4582C5,
+0xFF4582C5,
+0xFF4582C5,
+0xFF4582C5,
+0xFF4582C5,
+0xFF4582C5,
+0xFF4481C4,
+0xFF4481C4,
+0xFF4481C4,
+0xFF4481C4,
+0xFF4582C5,
+0xFF4481C4,
+0xFF4481C4,
+0xFF4481C4,
+0xFF4481C4,
+0xFF4481C4,
+0xFF4481C4,
+0xFF4481C4,
+0xFF4481C4,
+0xFF4481C4,
+0xFF4481C4,
+0xFF4582C5,
+0xFF4481C4,
+0xFF4481C4,
+0xFF4481C4,
+0xFF4481C4,
+0xFF4481C4,
+0xFF4481C4,
+0xFF4481C4,
+0xFF4481C4,
+0xFF4481C4,
+0xFF4481C4,
+0xFF4481C4,
+0xFF4481C4,
+0xFF4481C4,
+0xFF4380C3,
+0xFF4380C3,
+0xFF4380C3,
+0xFF4380C3,
+0xFF4180C3,
+0xFF4180C3,
+0xFF407FC2,
+0xFF407FC2,
+0xFF407FC2,
+0xFF407FC2,
+0xFF3F7EC1,
+0xFF3F7EC1,
+0xFF3F7EC1,
+0xFF3F7EC1,
+0xFF3E7FC1,
+0xFF3D7EC0,
+0xFF3D7EC2,
+0xFF3C7DC1,
+0xFF3C7DC1,
+0xFF3C7DC1,
+0xFF3C7BC0,
+0xFF3C7BC0,
+0xFF3E7AC0,
+0xFF3E7AC0,
+0xFF3F7BC1,
+0xFF3F7BC1,
+0xFF3F7AC0,
+0xFF3F7AC0,
+0xFF3E79BF,
+0xFF3E79BF,
+0xFF3E79BF,
+0xFF3E79BF,
+0xFF3D78BE,
+0xFF3C77BD,
+0xFF3D78BE,
+0xFF3C77BD,
+0xFF3C76BF,
+0xFF3C76BF,
+0xFF3B75BE,
+0xFF3B75BE,
+0xFF3A74BD,
+0xFF3A74BD,
+0xFF3974BA,
+0xFF3974BA,
+0xFF3974BA,
+0xFF3873B9,
+0xFF3972B9,
+0xFF3871B8,
+0xFF3871B8,
+0xFF3871B8,
+0xFF3A70B8,
+0xFF396FB7,
+0xFF396FB5,
+0xFF396FB5,
+0xFF386EB4,
+0xFF386EB4,
+0xFF386EB4,
+0xFF386EB4,
+0xFF3869AE,
+0xFF3869AE,
+0xFF3869AE,
+0xFF3869AE,
+0xFF3869AE,
+0xFF3869AE,
+0xFF396AAF,
+0xFF3A6BB0,
+0xFF3A6BB0,
+0xFF3A6BB0,
+0xFF396BB2,
+0xFF3A6CB3,
+0xFF3A6CB3,
+0xFF3B6DB4,
+0xFF3B6DB4,
+0xFF396EB4,
+0xFF396EB4,
+0xFF396EB4,
+0xFF3A6FB5,
+0xFF3A6FB5,
+0xFF396FB5,
+0xFF3A70B6,
+0xFF3A70B6,
+0xFF3A70B6,
+0xFF3871B6,
+0xFF3972B7,
+0xFF3972B7,
+0xFF3A73B8,
+0xFF3873B9,
+0xFF3974BA,
+0xFF3974BA,
+0xFF3A75BB,
+0xFF3B74B9,
+0xFF3B74B9,
+0xFF3C75BA,
+0xFF3C75BA,
+0xFF3C75BA,
+0xFF3C75BA,
+0xFF3C75BA,
+0xFF3C75BA,
+0xFF3D78BC,
+0xFF3D78BC,
+0xFF3D78BC,
+0xFF3D78BC,
+0xFF3E79BD,
+0xFF3F7ABE,
+0xFF3F7ABE,
+0xFF3E7BBE,
+0xFF3E7AC0,
+0xFF3E7AC0,
+0xFF3E7AC0,
+0xFF3F7BC1,
+0xFF3F7BC1,
+0xFF3F7BC1,
+0xFF3F7CBF,
+0xFF3F7CBF,
+0xFF3F7CBF,
+0xFF3F7CBF,
+0xFF3F7CBF,
+0xFF3F7CBF,
+0xFF3F7CBF,
+0xFF3F7CBF,
+0xFF407DC0,
+0xFF407DC0,
+0xFF3D7CBF,
+0xFF3D7CBF,
+0xFF3E7DC0,
+0xFF3E7DC0,
+0xFF3E7DC0,
+0xFF3E7DC0,
+0xFF3D7CBF,
+0xFF3C7BBE,
+0xFF3F7EC1,
+0xFF3F7EC1,
+0xFF3F7EC1,
+0xFF3F7EC1,
+0xFF3F7EC1,
+0xFF3F7EC1,
+0xFF3F7EC1,
+0xFF3F7EC1,
+0xFF3F7EC1,
+0xFF3F7EC1,
+0xFF3F7EC1,
+0xFF3F7EC1,
+0xFF3F7EC1,
+0xFF3F7EC1,
+0xFF3F7EC1,
+0xFF3F7EC1,
+0xFF407FC2,
+0xFF407FC2,
+0xFF407FC2,
+0xFF407FC2,
+0xFF407FC2,
+0xFF407FC2,
+0xFF407FC2,
+0xFF407FC2,
+0xFF427FC2,
+0xFF427FC2,
+0xFF427FC2,
+0xFF427FC2,
+0xFF427FC2,
+0xFF427FC2,
+0xFF427FC2,
+0xFF427FC2,
+0xFF427FC2,
+0xFF427FC2,
+0xFF427FC2,
+0xFF4380C3,
+0xFF4380C3,
+0xFF427FC2,
+0xFF427FC2,
+0xFF427FC2,
+0xFF427FC2,
+0xFF407FC2,
+0xFF427FC2,
+0xFF4180C3,
+0xFF4380C3,
+0xFF4180C3,
+0xFF4380C3,
+0xFF4180C3,
+0xFF4380C3,
+0xFF4380C3,
+0xFF4380C3,
+0xFF4380C3,
+0xFF4380C3,
+0xFF4380C3,
+0xFF4380C3,
+0xFF4380C3,
+0xFF4481C4,
+0xFF4281C4,
+0xFF4281C4,
+0xFF4281C4,
+0xFF4281C4,
+0xFF4281C4,
+0xFF4281C4,
+0xFF4281C4,
+0xFF4180C3,
+0xFF4281C4,
+0xFF4281C4,
+0xFF4281C4,
+0xFF4281C4,
+0xFF4281C4,
+0xFF4281C4,
+0xFF4281C4,
+0xFF4282C2,
+0xFF4282C2,
+0xFF4481C2,
+0xFF4481C2,
+0xFF4481C2,
+0xFF4582C3,
+0xFF4281C4,
+0xFF4281C4,
+0xFF4182C6,
+0xFF4182C6,
+0xFF3F80C4,
+0xFF4382C5,
+0xFF4380C1,
+0xFF4582C1,
+0xFF4680BF,
+0xFF558FCE,
+0xFF4E88C7,
+0xFF4680BF,
+0xFF487EBE,
+0xFF5289CC,
+0xFF003B81,
+0xFF1E427E,
+0xFF3B2F53,
+0xFF522738,
+0xFF602328,
+0xFF562810,
+0xFF9B9A57,
+0xFF829843,
+0xFF82994B,
+0xFF8CA355,
+0xFF6A812F,
+0xFF657A1D,
+0xFFA3B547,
+0xFFADBC45,
+0xFFB7C54C,
+0xFFB0B942,
+0xFFB3B548,
+0xFFBFAA57,
+0xFF5B2100,
+0xFF82382B,
+0xFF530D0B,
+0xFF591B28,
+0xFF350723,
+0xFF5C4772,
+0xFF6E7FB7,
+0xFF537CBC,
+0xFF4B82C3,
+0xFF4481C2,
+0xFF4581C0,
+0xFF4481C0,
+0xFF4282C2,
+0xFF4383C3,
+0xFF4681C5,
+0xFF4780C3,
+0xFF4981BE,
+0xFF4980C0,
+0xFF487EC4,
+0xFF467FC6,
+0xFF4580C2,
+0xFF4282BF,
+0xFF3F84BF,
+0xFF4084C1,
+0xFF4581C7,
+0xFF4680C9,
+0xFF4582C5,
+0xFF4582C5,
+0xFF4582C5,
+0xFF4582C5,
+0xFF4582C5,
+0xFF4582C5,
+0xFF4582C5,
+0xFF4582C5,
+0xFF4582C5,
+0xFF4481C4,
+0xFF4481C4,
+0xFF4481C4,
+0xFF4582C5,
+0xFF4683C6,
+0xFF4582C5,
+0xFF4582C5,
+0xFF4481C4,
+0xFF4481C4,
+0xFF4582C5,
+0xFF4582C5,
+0xFF4582C5,
+0xFF4582C5,
+0xFF4582C5,
+0xFF4582C5,
+0xFF4582C5,
+0xFF4582C5,
+0xFF4481C4,
+0xFF4582C5,
+0xFF4582C5,
+0xFF4582C5,
+0xFF4582C5,
+0xFF4481C4,
+0xFF4481C4,
+0xFF4481C4,
+0xFF4481C4,
+0xFF4481C4,
+0xFF4481C4,
+0xFF4582C5,
+0xFF4582C5,
+0xFF4582C5,
+0xFF4582C5,
+0xFF4582C5,
+0xFF4582C5,
+0xFF4582C5,
+0xFF4481C4,
+0xFF4481C4,
+0xFF4481C4,
+0xFF4481C4,
+0xFF4582C5,
+0xFF4582C5,
+0xFF4481C4,
+0xFF4481C4,
+0xFF4481C4,
+0xFF4481C4,
+0xFF4481C4,
+0xFF4481C4,
+0xFF4481C4,
+0xFF4481C4,
+0xFF4281C4,
+0xFF4180C3,
+0xFF4180C3,
+0xFF4180C3,
+0xFF4180C3,
+0xFF4180C3,
+0xFF407FC2,
+0xFF407FC2,
+0xFF3F7EC1,
+0xFF3F7EC1,
+0xFF3E7FC1,
+0xFF3E7FC1,
+0xFF3D7EC2,
+0xFF3D7EC2,
+0xFF3D7EC2,
+0xFF3D7EC2,
+0xFF3D7CC1,
+0xFF3D7CC1,
+0xFF3F7BC1,
+0xFF3E7AC0,
+0xFF3E7AC0,
+0xFF3E7AC0,
+0xFF407BC1,
+0xFF3F7AC0,
+0xFF3F7AC0,
+0xFF3F7AC0,
+0xFF3F7AC0,
+0xFF3F7AC0,
+0xFF3E79BF,
+0xFF3D78BE,
+0xFF3D78BE,
+0xFF3C77BD,
+0xFF3C76BF,
+0xFF3C76BF,
+0xFF3B75BE,
+0xFF3B75BE,
+0xFF3A74BD,
+0xFF3A74BD,
+0xFF3A75BB,
+0xFF3974BA,
+0xFF3974BA,
+0xFF3974BA,
+0xFF3A73BA,
+0xFF3972B9,
+0xFF3972B9,
+0xFF3972B9,
+0xFF3A70B8,
+0xFF3A70B8,
+0xFF3A70B6,
+0xFF396FB5,
+0xFF396FB5,
+0xFF396FB5,
+0xFF386EB4,
+0xFF386EB4,
+0xFF3968AE,
+0xFF3968AE,
+0xFF3869AE,
+0xFF3869AE,
+0xFF3869AE,
+0xFF396AAF,
+0xFF3A6BB0,
+0xFF3A6BB0,
+0xFF396BB0,
+0xFF3A6CB1,
+0xFF3A6CB3,
+0xFF3A6CB3,
+0xFF386DB3,
+0xFF396EB4,
+0xFF396EB4,
+0xFF3A6FB5,
+0xFF396EB4,
+0xFF396FB5,
+0xFF396FB5,
+0xFF396FB5,
+0xFF3A70B6,
+0xFF3A70B6,
+0xFF3B71B7,
+0xFF3B71B7,
+0xFF3972B7,
+0xFF3A73B8,
+0xFF3A73B8,
+0xFF3B74B9,
+0xFF3B74B9,
+0xFF3B74B9,
+0xFF3B74B9,
+0xFF3C75BA,
+0xFF3C75BA,
+0xFF3C75BA,
+0xFF3C75BA,
+0xFF3C75BA,
+0xFF3D76BB,
+0xFF3D76BB,
+0xFF3C77BB,
+0xFF3C77BB,
+0xFF3D78BC,
+0xFF3E79BD,
+0xFF3E79BD,
+0xFF3F7ABE,
+0xFF3E7BBE,
+0xFF3F7CBF,
+0xFF3F7CBF,
+0xFF3F7CBF,
+0xFF3E7BBE,
+0xFF3C7BBE,
+0xFF3C7BBE,
+0xFF3D7CBF,
+0xFF3D7CBF,
+0xFF3E7DC0,
+0xFF3E7DC0,
+0xFF3E7DC0,
+0xFF3E7DC0,
+0xFF3E7DC0,
+0xFF3E7DC0,
+0xFF3F7EC1,
+0xFF3F7EC1,
+0xFF3F7EC1,
+0xFF407FC2,
+0xFF407FC2,
+0xFF417EC1,
+0xFF417EC1,
+0xFF427FC2,
+0xFF427FC2,
+0xFF427FC2,
+0xFF417EC1,
+0xFF417EC1,
+0xFF407DC0,
+0xFF417EC1,
+0xFF417EC1,
+0xFF417EC1,
+0xFF417EC1,
+0xFF417EC1,
+0xFF427FC2,
+0xFF427FC2,
+0xFF427FC2,
+0xFF427FC2,
+0xFF427FC2,
+0xFF427FC2,
+0xFF427FC2,
+0xFF427FC2,
+0xFF427FC2,
+0xFF427FC2,
+0xFF427FC2,
+0xFF4380C3,
+0xFF4380C3,
+0xFF4380C3,
+0xFF4380C3,
+0xFF4380C3,
+0xFF4380C3,
+0xFF4380C3,
+0xFF4380C3,
+0xFF447FC3,
+0xFF447FC3,
+0xFF447FC3,
+0xFF447FC3,
+0xFF447FC3,
+0xFF447FC3,
+0xFF447FC3,
+0xFF447FC3,
+0xFF447FC3,
+0xFF447FC3,
+0xFF447FC3,
+0xFF4580C4,
+0xFF4580C4,
+0xFF447FC3,
+0xFF447FC3,
+0xFF447FC3,
+0xFF447FC1,
+0xFF4380C1,
+0xFF447FC1,
+0xFF4380C1,
+0xFF447FC1,
+0xFF4380C1,
+0xFF447FC1,
+0xFF4380C1,
+0xFF4580C2,
+0xFF4580C2,
+0xFF4580C2,
+0xFF4580C2,
+0xFF4580C2,
+0xFF4580C2,
+0xFF4580C2,
+0xFF4481C2,
+0xFF4481C4,
+0xFF4481C4,
+0xFF4582C5,
+0xFF4582C5,
+0xFF4481C4,
+0xFF4481C4,
+0xFF4481C4,
+0xFF4481C4,
+0xFF4481C4,
+0xFF4481C4,
+0xFF4481C4,
+0xFF4481C4,
+0xFF4481C4,
+0xFF4481C4,
+0xFF4481C4,
+0xFF4481C4,
+0xFF4281C4,
+0xFF4281C4,
+0xFF4282C2,
+0xFF4383C3,
+0xFF4582C3,
+0xFF4481C2,
+0xFF4281C4,
+0xFF4382C5,
+0xFF4182C4,
+0xFF4283C5,
+0xFF4180C3,
+0xFF4281C4,
+0xFF427FC0,
+0xFF4885C4,
+0xFF417BBA,
+0xFF639FDD,
+0xFF3E7EBE,
+0xFF4582C3,
+0xFF4C86C5,
+0xFF4980C0,
+0xFF366DB0,
+0xFF082C68,
+0xFF44436D,
+0xFF422039,
+0xFF5E222A,
+0xFF521F0A,
+0xFF9A9958,
+0xFF859B46,
+0xFF839A4C,
+0xFF90A759,
+0xFF6A802E,
+0xFF6C7F25,
+0xFF96A23C,
+0xFFB6C252,
+0xFFB7C54C,
+0xFFB7C54C,
+0xFFACB945,
+0xFFCDC767,
+0xFFA07236,
+0xFF6B2605,
+0xFF883F30,
+0xFF560B08,
+0xFF63161C,
+0xFF460C22,
+0xFF675784,
+0xFF6A7EB9,
+0xFF477AB9,
+0xFF4586C8,
+0xFF4382C5,
+0xFF4582C5,
+0xFF4681C3,
+0xFF4582C3,
+0xFF4383C3,
+0xFF4284C1,
+0xFF4085BE,
+0xFF4384BE,
+0xFF4A7FC3,
+0xFF4A7FC5,
+0xFF4681C5,
+0xFF4383C1,
+0xFF4583BE,
+0xFF4583C0,
+0xFF4382C7,
+0xFF4282C9,
+0xFF4483C6,
+0xFF4484C4,
+0xFF4484C4,
+0xFF4484C4,
+0xFF4484C4,
+0xFF4484C4,
+0xFF4383C3,
+0xFF4383C3,
+0xFF4383C3,
+0xFF4383C3,
+0xFF4383C3,
+0xFF4383C3,
+0xFF4484C4,
+0xFF4484C4,
+0xFF4484C4,
+0xFF4484C4,
+0xFF4383C3,
+0xFF4383C3,
+0xFF4383C3,
+0xFF4383C3,
+0xFF4383C3,
+0xFF4383C3,
+0xFF4383C3,
+0xFF4383C3,
+0xFF4383C3,
+0xFF4383C3,
+0xFF4383C3,
+0xFF4383C3,
+0xFF4383C3,
+0xFF4484C4,
+0xFF4383C3,
+0xFF4383C3,
+0xFF4383C3,
+0xFF4383C3,
+0xFF4383C3,
+0xFF4383C3,
+0xFF4383C3,
+0xFF4383C3,
+0xFF4383C3,
+0xFF4383C3,
+0xFF4383C3,
+0xFF4383C3,
+0xFF4383C3,
+0xFF4383C3,
+0xFF4383C3,
+0xFF4383C3,
+0xFF4383C3,
+0xFF4383C3,
+0xFF4582C5,
+0xFF4582C5,
+0xFF4582C5,
+0xFF4582C5,
+0xFF4582C5,
+0xFF4481C4,
+0xFF4481C4,
+0xFF4481C4,
+0xFF4481C4,
+0xFF4481C4,
+0xFF4481C4,
+0xFF4481C4,
+0xFF4481C4,
+0xFF4481C4,
+0xFF4380C3,
+0xFF4380C3,
+0xFF4180C3,
+0xFF407FC2,
+0xFF407FC2,
+0xFF407FC2,
+0xFF3F80C2,
+0xFF3F80C2,
+0xFF3E7FC1,
+0xFF3D7EC0,
+0xFF3E7FC1,
+0xFF3D7EC0,
+0xFF3D7EC2,
+0xFF3D7EC2,
+0xFF3E7DC2,
+0xFF3D7CC1,
+0xFF3C7BC0,
+0xFF3B7ABF,
+0xFF3F7BC1,
+0xFF3F7BC1,
+0xFF3E7AC0,
+0xFF3E7AC0,
+0xFF3E7AC0,
+0xFF3E7AC0,
+0xFF3D79BF,
+0xFF3C78BE,
+0xFF3C78BE,
+0xFF3C78BE,
+0xFF3D78BE,
+0xFF3C77BD,
+0xFF3C77BD,
+0xFF3B76BC,
+0xFF3B76BC,
+0xFF3B76BC,
+0xFF3A75BB,
+0xFF3A75BB,
+0xFF3974BA,
+0xFF3974BA,
+0xFF3974BA,
+0xFF3974BA,
+0xFF3A73BA,
+0xFF3A73BA,
+0xFF3972B9,
+0xFF3972B9,
+0xFF3871B8,
+0xFF3871B8,
+0xFF3770B7,
+0xFF3770B7,
+0xFF3770B7,
+0xFF3770B7,
+0xFF3968AE,
+0xFF3A69AF,
+0xFF396AAF,
+0xFF396AAF,
+0xFF396AAF,
+0xFF396AAF,
+0xFF3A6BB0,
+0xFF3A6CB1,
+0xFF3A6CB1,
+0xFF3A6CB1,
+0xFF3B6DB4,
+0xFF396EB4,
+0xFF396EB4,
+0xFF396EB4,
+0xFF3A6FB5,
+0xFF3A70B6,
+0xFF396FB5,
+0xFF396FB5,
+0xFF396FB5,
+0xFF3A70B6,
+0xFF3A70B6,
+0xFF3B71B7,
+0xFF3B71B7,
+0xFF3B71B7,
+0xFF3A73B8,
+0xFF3B74B9,
+0xFF3B74B9,
+0xFF3B74B9,
+0xFF3B74B9,
+0xFF3C75BA,
+0xFF3C75BA,
+0xFF3D76BB,
+0xFF3D76BB,
+0xFF3D76BB,
+0xFF3D76BB,
+0xFF3D76BB,
+0xFF3E77BC,
+0xFF3E77BC,
+0xFF3D78BC,
+0xFF3D78BC,
+0xFF3E79BD,
+0xFF3E79BD,
+0xFF3F7ABE,
+0xFF3F7ABE,
+0xFF3F7CBF,
+0xFF3F7CBF,
+0xFF3F7CBF,
+0xFF3F7CBF,
+0xFF3C7BBE,
+0xFF3C7BBE,
+0xFF3D7CBF,
+0xFF3D7CBF,
+0xFF3E7DC0,
+0xFF3E7DC0,
+0xFF3E7DC0,
+0xFF3E7DC0,
+0xFF3E7DC0,
+0xFF3F7EC1,
+0xFF3F7EC1,
+0xFF3F7EC1,
+0xFF3F7EC1,
+0xFF407FC2,
+0xFF407FC2,
+0xFF407FC2,
+0xFF427FC2,
+0xFF427FC2,
+0xFF427FC2,
+0xFF4380C3,
+0xFF4380C3,
+0xFF427FC2,
+0xFF427FC2,
+0xFF427FC2,
+0xFF427FC2,
+0xFF427FC2,
+0xFF427FC2,
+0xFF427FC2,
+0xFF427FC2,
+0xFF4380C3,
+0xFF4380C3,
+0xFF4380C3,
+0xFF4380C3,
+0xFF4380C3,
+0xFF4380C3,
+0xFF4380C3,
+0xFF4380C3,
+0xFF4380C3,
+0xFF4380C3,
+0xFF4380C3,
+0xFF4380C3,
+0xFF4380C3,
+0xFF4481C4,
+0xFF4481C4,
+0xFF4481C4,
+0xFF4481C4,
+0xFF4481C4,
+0xFF4481C4,
+0xFF4580C4,
+0xFF4580C4,
+0xFF4580C4,
+0xFF4580C4,
+0xFF4580C4,
+0xFF4580C4,
+0xFF447FC3,
+0xFF447FC3,
+0xFF4580C4,
+0xFF4580C4,
+0xFF4580C4,
+0xFF4681C5,
+0xFF4681C5,
+0xFF4580C4,
+0xFF4580C4,
+0xFF4580C4,
+0xFF4580C2,
+0xFF4580C2,
+0xFF4580C2,
+0xFF4580C2,
+0xFF4580C2,
+0xFF4580C2,
+0xFF4580C2,
+0xFF4580C2,
+0xFF4580C2,
+0xFF4580C2,
+0xFF4580C2,
+0xFF4681C3,
+0xFF4681C3,
+0xFF4681C3,
+0xFF4681C3,
+0xFF4582C3,
+0xFF4380C3,
+0xFF4481C4,
+0xFF4582C5,
+0xFF4582C5,
+0xFF4481C4,
+0xFF4481C4,
+0xFF4481C4,
+0xFF4481C4,
+0xFF4481C4,
+0xFF4481C4,
+0xFF4582C5,
+0xFF4582C5,
+0xFF4582C5,
+0xFF4582C5,
+0xFF4481C4,
+0xFF4281C4,
+0xFF4281C4,
+0xFF4281C4,
+0xFF4282C2,
+0xFF4383C3,
+0xFF4582C3,
+0xFF4582C3,
+0xFF4382C5,
+0xFF4382C5,
+0xFF4182C4,
+0xFF4283C5,
+0xFF4382C5,
+0xFF4383C3,
+0xFF4380BF,
+0xFF4884C2,
+0xFF407BB7,
+0xFF65A1DF,
+0xFF4283C5,
+0xFF3E7FC1,
+0xFF4582C1,
+0xFF457FBE,
+0xFF568BCD,
+0xFF133977,
+0xFF333D6E,
+0xFF3B2647,
+0xFF5A202C,
+0xFF511D08,
+0xFF918D4E,
+0xFF899C4B,
+0xFF869B50,
+0xFF92A75A,
+0xFF6A802E,
+0xFF6E8128,
+0xFF768423,
+0xFFB3C054,
+0xFFC0CD57,
+0xFFB3C148,
+0xFFAABC46,
+0xFFA2A33B,
+0xFFCDAE5E,
+0xFF662E00,
+0xFF772F19,
+0xFFAB5852,
+0xFF5E0500,
+0xFF6E2127,
+0xFF380C27,
+0xFF6C658F,
+0xFF6185B9,
+0xFF4681BD,
+0xFF4683C6,
+0xFF4483C8,
+0xFF4682C8,
+0xFF4683C6,
+0xFF4283C5,
+0xFF4084C1,
+0xFF3F86BE,
+0xFF4284BE,
+0xFF4881C4,
+0xFF4881C6,
+0xFF4483C6,
+0xFF4484C4,
+0xFF4783C1,
+0xFF4783C1,
+0xFF4384C8,
+0xFF4184C8,
+0xFF4384C6,
+0xFF4484C4,
+0xFF4484C4,
+0xFF4484C4,
+0xFF4484C4,
+0xFF4484C4,
+0xFF4484C4,
+0xFF4484C4,
+0xFF4585C5,
+0xFF4585C5,
+0xFF4484C4,
+0xFF4484C4,
+0xFF4484C4,
+0xFF4484C4,
+0xFF4484C4,
+0xFF4484C4,
+0xFF4585C5,
+0xFF4585C5,
+0xFF4585C5,
+0xFF4585C5,
+0xFF4585C5,
+0xFF4585C5,
+0xFF4585C5,
+0xFF4585C5,
+0xFF4484C4,
+0xFF4484C4,
+0xFF4484C4,
+0xFF4484C4,
+0xFF4484C4,
+0xFF4484C4,
+0xFF4484C4,
+0xFF4484C4,
+0xFF4484C4,
+0xFF4484C4,
+0xFF4484C4,
+0xFF4484C4,
+0xFF4484C4,
+0xFF4484C4,
+0xFF4484C4,
+0xFF4484C4,
+0xFF4484C4,
+0xFF4484C4,
+0xFF4484C4,
+0xFF4484C4,
+0xFF4484C4,
+0xFF4484C4,
+0xFF4484C4,
+0xFF4383C3,
+0xFF4683C6,
+0xFF4683C6,
+0xFF4683C6,
+0xFF4582C5,
+0xFF4582C5,
+0xFF4582C5,
+0xFF4582C5,
+0xFF4582C5,
+0xFF4582C5,
+0xFF4582C5,
+0xFF4582C5,
+0xFF4481C4,
+0xFF4481C4,
+0xFF4481C4,
+0xFF4481C4,
+0xFF4481C4,
+0xFF4481C4,
+0xFF4180C3,
+0xFF4180C3,
+0xFF4180C3,
+0xFF4180C3,
+0xFF3F80C2,
+0xFF3F80C2,
+0xFF3E7FC1,
+0xFF3D7EC0,
+0xFF3D7EC0,
+0xFF3D7EC2,
+0xFF3E7FC3,
+0xFF407FC4,
+0xFF3F7EC3,
+0xFF3E7DC2,
+0xFF3D7CC1,
+0xFF3D7CC1,
+0xFF3F7BC1,
+0xFF3F7BC1,
+0xFF3F7BC1,
+0xFF3F7BC1,
+0xFF3E7AC0,
+0xFF3E7AC0,
+0xFF3D79BF,
+0xFF3D79BF,
+0xFF3D79BF,
+0xFF3E79BF,
+0xFF3E79BF,
+0xFF3D78BE,
+0xFF3D78BE,
+0xFF3C77BD,
+0xFF3C77BD,
+0xFF3A75BB,
+0xFF3A75BB,
+0xFF3A75BB,
+0xFF3A75BB,
+0xFF3A75BB,
+0xFF3A75BB,
+0xFF3A73BA,
+0xFF3A73BA,
+0xFF3A73BA,
+0xFF3972B9,
+0xFF3972B9,
+0xFF3972B9,
+0xFF3871B8,
+0xFF3871B8,
+0xFF3770B7,
+0xFF3770B7,
+0xFF396AAF,
+0xFF396AAF,
+0xFF3A6BB0,
+0xFF3A6BB0,
+0xFF3A6BB0,
+0xFF3A6BB0,
+0xFF3A6CB1,
+0xFF3A6CB1,
+0xFF3B6DB2,
+0xFF396EB2,
+0xFF396EB4,
+0xFF396EB4,
+0xFF396EB4,
+0xFF396FB5,
+0xFF3A70B6,
+0xFF3B71B7,
+0xFF3A70B8,
+0xFF3871B8,
+0xFF3871B6,
+0xFF3972B7,
+0xFF3972B7,
+0xFF3A73B8,
+0xFF3A73B8,
+0xFF3B74B9,
+0xFF3B74B9,
+0xFF3B74B9,
+0xFF3C75B8,
+0xFF3C75B8,
+0xFF3C75B8,
+0xFF3D76B9,
+0xFF3D76B9,
+0xFF3E77BA,
+0xFF3D76BB,
+0xFF3E77BC,
+0xFF3E77BC,
+0xFF3E77BC,
+0xFF3E79BD,
+0xFF3E79BD,
+0xFF3F7ABE,
+0xFF3F7ABE,
+0xFF3E7BBE,
+0xFF3E7BBE,
+0xFF3E7BBE,
+0xFF3F7CBF,
+0xFF3F7CBF,
+0xFF3F7CBF,
+0xFF3F7CBF,
+0xFF3F7CBF,
+0xFF3D7CBF,
+0xFF3E7DC0,
+0xFF3E7DC0,
+0xFF3E7DC0,
+0xFF3F7EC1,
+0xFF3F7EC1,
+0xFF3F7EC1,
+0xFF3F7EC1,
+0xFF407DC0,
+0xFF417EC1,
+0xFF417EBF,
+0xFF427FC0,
+0xFF427FC0,
+0xFF427FC0,
+0xFF427FC0,
+0xFF427FC0,
+0xFF427FC0,
+0xFF427FC0,
+0xFF427FC0,
+0xFF427FC0,
+0xFF4380C1,
+0xFF4380C1,
+0xFF4380C1,
+0xFF4380C1,
+0xFF4380C1,
+0xFF4380C1,
+0xFF4380C1,
+0xFF4380C1,
+0xFF4481C2,
+0xFF4481C2,
+0xFF4481C2,
+0xFF4481C2,
+0xFF4580C2,
+0xFF4580C2,
+0xFF4580C2,
+0xFF4580C2,
+0xFF4580C2,
+0xFF4580C2,
+0xFF4580C2,
+0xFF4580C2,
+0xFF4580C2,
+0xFF4580C2,
+0xFF4580C2,
+0xFF4580C2,
+0xFF4580C2,
+0xFF4580C2,
+0xFF4580C2,
+0xFF4580C2,
+0xFF4580C2,
+0xFF4580C2,
+0xFF4580C2,
+0xFF4580C2,
+0xFF4580C2,
+0xFF4580C2,
+0xFF4580C2,
+0xFF4580C2,
+0xFF4580C2,
+0xFF4681C3,
+0xFF4681C3,
+0xFF4681C3,
+0xFF4681C3,
+0xFF4681C3,
+0xFF4681C3,
+0xFF4681C3,
+0xFF4681C3,
+0xFF4681C3,
+0xFF4681C3,
+0xFF4681C3,
+0xFF4681C3,
+0xFF4681C3,
+0xFF4681C3,
+0xFF4681C3,
+0xFF4580C2,
+0xFF4681C3,
+0xFF4582C3,
+0xFF4582C3,
+0xFF4582C3,
+0xFF4582C3,
+0xFF4582C3,
+0xFF4683C4,
+0xFF4481C2,
+0xFF4282C2,
+0xFF4383C3,
+0xFF4484C4,
+0xFF4383C3,
+0xFF4383C3,
+0xFF4383C3,
+0xFF4383C3,
+0xFF4383C3,
+0xFF4383C3,
+0xFF4383C3,
+0xFF4484C4,
+0xFF4484C4,
+0xFF4484C4,
+0xFF4383C3,
+0xFF4383C3,
+0xFF4382C5,
+0xFF4283C5,
+0xFF4383C3,
+0xFF4484C4,
+0xFF4484C4,
+0xFF4383C3,
+0xFF4383C3,
+0xFF4484C4,
+0xFF4283C5,
+0xFF4283C5,
+0xFF4484C4,
+0xFF4484C4,
+0xFF4683C2,
+0xFF4682C0,
+0xFF4883BF,
+0xFF5E9AD8,
+0xFF4081C1,
+0xFF4286C7,
+0xFF4484C4,
+0xFF417DBC,
+0xFF5085C7,
+0xFF4B74B2,
+0xFF152E66,
+0xFF433B62,
+0xFF551F2C,
+0xFF561F0B,
+0xFF847B42,
+0xFF8C9C51,
+0xFF889A50,
+0xFF91A659,
+0xFF718735,
+0xFF6B822A,
+0xFF6B811F,
+0xFFB4C75C,
+0xFFB6C351,
+0xFFB9C24D,
+0xFFAAB441,
+0xFF898C21,
+0xFFD6CC6B,
+0xFFCCA965,
+0xFFA5614A,
+0xFF5E0807,
+0xFF7B2524,
+0xFF5F0D0F,
+0xFF661F25,
+0xFF3B1222,
+0xFF6F7597,
+0xFF5A82B3,
+0xFF4984C0,
+0xFF4285C9,
+0xFF4484CC,
+0xFF4583CC,
+0xFF4584C9,
+0xFF4484C4,
+0xFF4485BF,
+0xFF4385C1,
+0xFF4286C7,
+0xFF4186C9,
+0xFF4186C7,
+0xFF4286C5,
+0xFF4883C5,
+0xFF4883C7,
+0xFF4485C7,
+0xFF4286C7,
+0xFF4485C5,
+0xFF4485C5,
+0xFF4485C5,
+0xFF4485C5,
+0xFF4485C5,
+0xFF4485C5,
+0xFF4485C5,
+0xFF4485C5,
+0xFF4485C5,
+0xFF4485C5,
+0xFF4485C5,
+0xFF4485C5,
+0xFF4485C5,
+0xFF4485C5,
+0xFF4485C5,
+0xFF4485C5,
+0xFF4686C6,
+0xFF4686C6,
+0xFF4686C6,
+0xFF4686C6,
+0xFF4585C5,
+0xFF4585C5,
+0xFF4585C5,
+0xFF4585C5,
+0xFF4585C5,
+0xFF4585C5,
+0xFF4585C5,
+0xFF4585C5,
+0xFF4585C5,
+0xFF4686C6,
+0xFF4585C5,
+0xFF4585C5,
+0xFF4585C5,
+0xFF4585C5,
+0xFF4585C5,
+0xFF4585C5,
+0xFF4585C5,
+0xFF4585C5,
+0xFF4585C5,
+0xFF4585C5,
+0xFF4585C5,
+0xFF4585C5,
+0xFF4585C5,
+0xFF4585C5,
+0xFF4585C5,
+0xFF4585C5,
+0xFF4585C5,
+0xFF4585C5,
+0xFF4585C5,
+0xFF4585C5,
+0xFF4585C5,
+0xFF4484C4,
+0xFF4484C4,
+0xFF4484C4,
+0xFF4683C4,
+0xFF4683C4,
+0xFF4582C3,
+0xFF4582C3,
+0xFF4582C3,
+0xFF4582C3,
+0xFF4582C3,
+0xFF4582C3,
+0xFF4681C3,
+0xFF4582C3,
+0xFF4481C4,
+0xFF4481C4,
+0xFF4481C4,
+0xFF4281C4,
+0xFF4281C4,
+0xFF4180C3,
+0xFF4180C3,
+0xFF407FC2,
+0xFF407FC2,
+0xFF407FC2,
+0xFF3F7EC1,
+0xFF407FC2,
+0xFF407FC2,
+0xFF407FC2,
+0xFF3F7EC1,
+0xFF3E7DC0,
+0xFF3E7DC0,
+0xFF3E7DC0,
+0xFF3D7CBF,
+0xFF3D7CBF,
+0xFF3D7CBF,
+0xFF3D7CBF,
+0xFF3C7BC0,
+0xFF3C7BC0,
+0xFF3E7AC0,
+0xFF3E7AC0,
+0xFF3E7AC0,
+0xFF3D79BF,
+0xFF3D79BF,
+0xFF3D79BF,
+0xFF3C78BE,
+0xFF3C78BE,
+0xFF3C77BD,
+0xFF3C77BD,
+0xFF3B76BC,
+0xFF3B76BC,
+0xFF3A75BB,
+0xFF3A75BB,
+0xFF3A75BB,
+0xFF3974BA,
+0xFF3974BA,
+0xFF3974BA,
+0xFF3974BA,
+0xFF3873B9,
+0xFF3873B9,
+0xFF3873B9,
+0xFF3772B8,
+0xFF3772B8,
+0xFF396AAF,
+0xFF3A6BB0,
+0xFF3B6CB1,
+0xFF3B6CB1,
+0xFF3B6CB1,
+0xFF3B6CB1,
+0xFF3A6CB1,
+0xFF3B6DB2,
+0xFF396EB2,
+0xFF3A6FB3,
+0xFF3A6FB5,
+0xFF3A6FB5,
+0xFF396FB5,
+0xFF396FB5,
+0xFF3A70B6,
+0xFF3B71B7,
+0xFF3972B9,
+0xFF3972B9,
+0xFF3A73B8,
+0xFF3A73B8,
+0xFF3B74B9,
+0xFF3B74B9,
+0xFF3C75BA,
+0xFF3C75BA,
+0xFF3B74B9,
+0xFF3C75BA,
+0xFF3C75B8,
+0xFF3D76B9,
+0xFF3D76B9,
+0xFF3D76B9,
+0xFF3E77BA,
+0xFF3E77BA,
+0xFF3E77BC,
+0xFF3E77BC,
+0xFF3F78BD,
+0xFF3F78BD,
+0xFF3F7ABE,
+0xFF3F7ABE,
+0xFF407BBF,
+0xFF407BBF,
+0xFF3E7BBE,
+0xFF3F7CBF,
+0xFF3F7CBF,
+0xFF407DC0,
+0xFF407DC0,
+0xFF407DC0,
+0xFF3F7CBF,
+0xFF3F7CBF,
+0xFF3F7EC1,
+0xFF3F7EC1,
+0xFF3F7EC1,
+0xFF3F7EC1,
+0xFF3F7EC1,
+0xFF3F7EC1,
+0xFF3F7EC1,
+0xFF3F7EC1,
+0xFF417EC1,
+0xFF427FC2,
+0xFF4380C1,
+0xFF4380C1,
+0xFF4380C1,
+0xFF4380C1,
+0xFF4380C1,
+0xFF4380C1,
+0xFF4380C1,
+0xFF4380C1,
+0xFF4380C1,
+0xFF4481C2,
+0xFF4481C2,
+0xFF4481C2,
+0xFF4481C2,
+0xFF4582C3,
+0xFF4481C2,
+0xFF4481C2,
+0xFF4481C2,
+0xFF4481C2,
+0xFF4481C2,
+0xFF4582C3,
+0xFF4582C3,
+0xFF4582C3,
+0xFF4580C2,
+0xFF4580C2,
+0xFF4580C2,
+0xFF4580C2,
+0xFF4580C2,
+0xFF4580C2,
+0xFF4580C2,
+0xFF4580C2,
+0xFF4580C2,
+0xFF4681C3,
+0xFF4681C3,
+0xFF4681C3,
+0xFF4681C3,
+0xFF4681C3,
+0xFF4681C3,
+0xFF4681C3,
+0xFF4580C2,
+0xFF4580C2,
+0xFF4580C2,
+0xFF4580C2,
+0xFF4580C2,
+0xFF4580C2,
+0xFF4580C2,
+0xFF4580C2,
+0xFF4681C3,
+0xFF4681C3,
+0xFF4681C3,
+0xFF4681C3,
+0xFF4681C3,
+0xFF4681C3,
+0xFF4681C3,
+0xFF4681C3,
+0xFF4681C3,
+0xFF4681C3,
+0xFF4681C3,
+0xFF4681C3,
+0xFF4681C3,
+0xFF4681C3,
+0xFF4681C3,
+0xFF4582C3,
+0xFF4681C3,
+0xFF4582C3,
+0xFF4582C3,
+0xFF4582C3,
+0xFF4582C3,
+0xFF4683C4,
+0xFF4683C4,
+0xFF4484C4,
+0xFF4383C3,
+0xFF4383C3,
+0xFF4484C4,
+0xFF4585C5,
+0xFF4484C4,
+0xFF4484C4,
+0xFF4484C4,
+0xFF4484C4,
+0xFF4484C4,
+0xFF4484C4,
+0xFF4484C4,
+0xFF4585C5,
+0xFF4585C5,
+0xFF4484C4,
+0xFF4484C4,
+0xFF4384C4,
+0xFF4384C6,
+0xFF4283C5,
+0xFF4484C4,
+0xFF4585C5,
+0xFF4585C5,
+0xFF4484C4,
+0xFF4484C4,
+0xFF4585C5,
+0xFF4485C7,
+0xFF4283C5,
+0xFF4585C5,
+0xFF4484C2,
+0xFF4985C4,
+0xFF4480BC,
+0xFF548CC9,
+0xFF5894D0,
+0xFF4183C0,
+0xFF4589C8,
+0xFF4182C4,
+0xFF4B88C9,
+0xFF4C83C4,
+0xFF5484C4,
+0xFF2C508E,
+0xFF3B4270,
+0xFF4E1F2F,
+0xFF572212,
+0xFF7A6E3A,
+0xFF919C57,
+0xFF87974E,
+0xFF91A357,
+0xFF798E3F,
+0xFF6C842E,
+0xFF678022,
+0xFF98AF47,
+0xFFBDC95B,
+0xFFC2CA5A,
+0xFF8B9324,
+0xFFCED669,
+0xFFE0E378,
+0xFFE1CC7B,
+0xFF521300,
+0xFF903731,
+0xFFA34442,
+0xFF933535,
+0xFF630D0C,
+0xFF53161D,
+0xFF2D152B,
+0xFF747EA2,
+0xFF5880B4,
+0xFF4A84C3,
+0xFF4584CB,
+0xFF4583CC,
+0xFF4783CB,
+0xFF4784C7,
+0xFF4784C3,
+0xFF4486C3,
+0xFF4087C7,
+0xFF3E88C7,
+0xFF4087C7,
+0xFF4286C7,
+0xFF4784C7,
+0xFF4784C7,
+0xFF4286C7,
+0xFF4186C7,
+0xFF4485C5,
+0xFF4485C5,
+0xFF4485C5,
+0xFF4485C5,
+0xFF4485C5,
+0xFF4485C5,
+0xFF4485C5,
+0xFF4485C5,
+0xFF4384C4,
+0xFF4485C5,
+0xFF4485C5,
+0xFF4485C5,
+0xFF4485C5,
+0xFF4485C5,
+0xFF4586C6,
+0xFF4586C6,
+0xFF4686C6,
+0xFF4686C6,
+0xFF4686C6,
+0xFF4686C6,
+0xFF4585C5,
+0xFF4585C5,
+0xFF4585C5,
+0xFF4585C5,
+0xFF4686C6,
+0xFF4686C6,
+0xFF4585C5,
+0xFF4686C6,
+0xFF4686C6,
+0xFF4686C6,
+0xFF4686C6,
+0xFF4686C6,
+0xFF4686C6,
+0xFF4686C6,
+0xFF4686C6,
+0xFF4686C6,
+0xFF4686C6,
+0xFF4686C6,
+0xFF4686C6,
+0xFF4686C6,
+0xFF4686C6,
+0xFF4686C6,
+0xFF4686C6,
+0xFF4686C6,
+0xFF4686C6,
+0xFF4686C6,
+0xFF4686C6,
+0xFF4686C6,
+0xFF4585C5,
+0xFF4585C5,
+0xFF4585C5,
+0xFF4585C5,
+0xFF4585C5,
+0xFF4585C5,
+0xFF4683C4,
+0xFF4683C4,
+0xFF4683C4,
+0xFF4683C4,
+0xFF4683C4,
+0xFF4683C4,
+0xFF4683C4,
+0xFF4582C3,
+0xFF4681C3,
+0xFF4681C3,
+0xFF4582C5,
+0xFF4582C5,
+0xFF4481C4,
+0xFF4481C4,
+0xFF4481C4,
+0xFF4281C4,
+0xFF4180C3,
+0xFF4180C3,
+0xFF4382C5,
+0xFF4281C4,
+0xFF407FC2,
+0xFF407FC2,
+0xFF407FC2,
+0xFF407FC2,
+0xFF407FC2,
+0xFF3F7EC1,
+0xFF3E7FC1,
+0xFF3D7EC0,
+0xFF3D7CBF,
+0xFF3D7CBF,
+0xFF3D7CBF,
+0xFF3D7CBF,
+0xFF3D7CC1,
+0xFF3D7CC1,
+0xFF3E7AC0,
+0xFF3E7AC0,
+0xFF3E7AC0,
+0xFF3E7AC0,
+0xFF3D79BF,
+0xFF3D79BF,
+0xFF3C78BE,
+0xFF3C78BE,
+0xFF3E79BF,
+0xFF3D78BE,
+0xFF3D78BE,
+0xFF3C77BD,
+0xFF3B76BC,
+0xFF3A75BB,
+0xFF3A75BB,
+0xFF3974BA,
+0xFF3A75BB,
+0xFF3A75BB,
+0xFF3A75BB,
+0xFF3974BA,
+0xFF3974BA,
+0xFF3873B9,
+0xFF3873B9,
+0xFF3873B9,
+0xFF3A6BB0,
+0xFF3A6BB0,
+0xFF3B6CB1,
+0xFF3B6CB1,
+0xFF3B6DB2,
+0xFF3B6DB2,
+0xFF3C6EB3,
+0xFF3C6EB3,
+0xFF396EB2,
+0xFF396EB2,
+0xFF396FB5,
+0xFF396FB5,
+0xFF3A70B6,
+0xFF3A70B6,
+0xFF3B71B7,
+0xFF3B71B7,
+0xFF3972B7,
+0xFF3A73B8,
+0xFF3A73B8,
+0xFF3B74B9,
+0xFF3B74B9,
+0xFF3C75BA,
+0xFF3C75BA,
+0xFF3C75BA,
+0xFF3C75B8,
+0xFF3D76B9,
+0xFF3D76B9,
+0xFF3E77BA,
+0xFF3E77BA,
+0xFF3E77BA,
+0xFF3E77BA,
+0xFF3F78BB,
+0xFF3F7ABE,
+0xFF3E79BD,
+0xFF3E79BD,
+0xFF3F7ABE,
+0xFF407BBF,
+0xFF407BBF,
+0xFF3F7CBF,
+0xFF3E7BBE,
+0xFF3F7CBF,
+0xFF3F7CBF,
+0xFF407DC0,
+0xFF417EC1,
+0xFF417EC1,
+0xFF407DC0,
+0xFF3E7DC0,
+0xFF3E7DC0,
+0xFF417EC1,
+0xFF417EC1,
+0xFF417EC1,
+0xFF427FC2,
+0xFF427FC0,
+0xFF4380C1,
+0xFF4380C1,
+0xFF427FC0,
+0xFF4580C2,
+0xFF4580C2,
+0xFF4580C2,
+0xFF4580C2,
+0xFF4580C2,
+0xFF4580C2,
+0xFF4580C2,
+0xFF4580C2,
+0xFF4481C2,
+0xFF4481C2,
+0xFF4481C2,
+0xFF4582C3,
+0xFF4582C3,
+0xFF4582C3,
+0xFF4582C3,
+0xFF4582C3,
+0xFF4582C3,
+0xFF4582C3,
+0xFF4582C3,
+0xFF4582C3,
+0xFF4582C3,
+0xFF4582C3,
+0xFF4582C3,
+0xFF4582C3,
+0xFF4582C3,
+0xFF4582C3,
+0xFF4582C3,
+0xFF4582C3,
+0xFF4582C3,
+0xFF4582C3,
+0xFF4582C3,
+0xFF4582C3,
+0xFF4582C3,
+0xFF4582C3,
+0xFF4582C3,
+0xFF4582C3,
+0xFF4582C3,
+0xFF4582C3,
+0xFF4582C3,
+0xFF4582C3,
+0xFF4784C5,
+0xFF4683C4,
+0xFF4683C4,
+0xFF4683C4,
+0xFF4582C3,
+0xFF4582C3,
+0xFF4582C3,
+0xFF4582C3,
+0xFF4683C4,
+0xFF4683C4,
+0xFF4683C4,
+0xFF4683C4,
+0xFF4683C4,
+0xFF4683C4,
+0xFF4683C4,
+0xFF4683C4,
+0xFF4683C4,
+0xFF4683C4,
+0xFF4683C4,
+0xFF4683C4,
+0xFF4683C4,
+0xFF4683C4,
+0xFF4683C4,
+0xFF4484C4,
+0xFF4784C5,
+0xFF4484C4,
+0xFF4484C4,
+0xFF4484C4,
+0xFF4484C4,
+0xFF4585C5,
+0xFF4585C5,
+0xFF4585C5,
+0xFF4484C4,
+0xFF4384C4,
+0xFF4384C4,
+0xFF4485C5,
+0xFF4485C5,
+0xFF4485C5,
+0xFF4485C5,
+0xFF4485C5,
+0xFF4485C5,
+0xFF4485C5,
+0xFF4485C5,
+0xFF4485C5,
+0xFF4485C5,
+0xFF4485C5,
+0xFF4485C5,
+0xFF4485C5,
+0xFF4485C7,
+0xFF4286C7,
+0xFF4485C5,
+0xFF4485C5,
+0xFF4585C5,
+0xFF4585C5,
+0xFF4485C5,
+0xFF4485C5,
+0xFF4384C4,
+0xFF4687C7,
+0xFF4383C3,
+0xFF4383C1,
+0xFF4B87C6,
+0xFF437FBB,
+0xFF679FDC,
+0xFF4681BD,
+0xFF4686C3,
+0xFF4185C2,
+0xFF4286C5,
+0xFF4586C8,
+0xFF4984C6,
+0xFF4B80C2,
+0xFF5687CA,
+0xFF283C6F,
+0xFF4B283E,
+0xFF4F2016,
+0xFF6C5E2F,
+0xFF979C59,
+0xFF88954D,
+0xFF8FA155,
+0xFF7E9547,
+0xFF6B832F,
+0xFF6D862B,
+0xFF839937,
+0xFFBCCB62,
+0xFFABB74B,
+0xFFCED971,
+0xFFC8D36A,
+0xFFB1BE4A,
+0xFFD1C766,
+0xFFA1693A,
+0xFF8A2F1C,
+0xFF8C1A10,
+0xFF9B2929,
+0xFF8D333D,
+0xFF631F2E,
+0xFF410B1B,
+0xFF381C35,
+0xFF7982AB,
+0xFF5E83B8,
+0xFF4A80BE,
+0xFF4986C7,
+0xFF4782C6,
+0xFF4A86CC,
+0xFF4282C9,
+0xFF4489CC,
+0xFF4188C6,
+0xFF4189C4,
+0xFF4387C8,
+0xFF4586CA,
+0xFF4685C8,
+0xFF4586C8,
+0xFF4188C8,
+0xFF4188C8,
+0xFF4387C6,
+0xFF4586C6,
+0xFF4586C6,
+0xFF4586C6,
+0xFF4586C6,
+0xFF4586C6,
+0xFF4586C6,
+0xFF4586C6,
+0xFF4586C6,
+0xFF4586C6,
+0xFF4586C6,
+0xFF4586C6,
+0xFF4586C6,
+0xFF4586C6,
+0xFF4586C6,
+0xFF4586C6,
+0xFF4586C6,
+0xFF4586C6,
+0xFF4586C6,
+0xFF4586C6,
+0xFF4586C6,
+0xFF4586C6,
+0xFF4586C6,
+0xFF4586C6,
+0xFF4586C6,
+0xFF4586C6,
+0xFF4586C6,
+0xFF4586C6,
+0xFF4586C6,
+0xFF4586C6,
+0xFF4586C6,
+0xFF4586C6,
+0xFF4586C6,
+0xFF4586C6,
+0xFF4687C7,
+0xFF4586C6,
+0xFF4586C6,
+0xFF4586C6,
+0xFF4586C6,
+0xFF4586C6,
+0xFF4586C6,
+0xFF4586C6,
+0xFF4586C6,
+0xFF4586C6,
+0xFF4586C6,
+0xFF4586C6,
+0xFF4586C6,
+0xFF4586C6,
+0xFF4687C7,
+0xFF4586C6,
+0xFF4586C6,
+0xFF4586C6,
+0xFF4585C5,
+0xFF4585C5,
+0xFF4585C5,
+0xFF4585C5,
+0xFF4784C5,
+0xFF4784C5,
+0xFF4784C5,
+0xFF4784C5,
+0xFF4683C4,
+0xFF4683C4,
+0xFF4683C4,
+0xFF4683C4,
+0xFF4681C3,
+0xFF4681C3,
+0xFF4681C3,
+0xFF4582C3,
+0xFF4582C3,
+0xFF4582C3,
+0xFF4481C2,
+0xFF4481C2,
+0xFF4582C5,
+0xFF4582C5,
+0xFF4481C4,
+0xFF4481C4,
+0xFF4380C3,
+0xFF4380C3,
+0xFF427FC2,
+0xFF407FC2,
+0xFF3F80C2,
+0xFF3F80C2,
+0xFF3F80C2,
+0xFF3F80C2,
+0xFF3F80C2,
+0xFF3E7FC1,
+0xFF3E7DC0,
+0xFF3D7CBF,
+0xFF3C7BBE,
+0xFF3E7DC0,
+0xFF407DC0,
+0xFF3E7BBE,
+0xFF3D79BF,
+0xFF3E7AC0,
+0xFF3F7BC1,
+0xFF3E7AC0,
+0xFF3E79BF,
+0xFF3D78BE,
+0xFF3D78BE,
+0xFF3D78BE,
+0xFF3C77BD,
+0xFF3C77BD,
+0xFF3B76BC,
+0xFF3B76BC,
+0xFF3B76BC,
+0xFF3B76BC,
+0xFF3B76BC,
+0xFF3A75BB,
+0xFF3A75BB,
+0xFF3974BA,
+0xFF3974BA,
+0xFF3974BA,
+0xFF3B6CB1,
+0xFF3B6CB1,
+0xFF3C6DB2,
+0xFF3B6DB2,
+0xFF3B6DB2,
+0xFF3C6EB3,
+0xFF3C6EB3,
+0xFF3A6FB3,
+0xFF3A6FB3,
+0xFF3A6FB3,
+0xFF396FB5,
+0xFF3A70B6,
+0xFF3B71B7,
+0xFF3B71B7,
+0xFF3B71B7,
+0xFF3C72B8,
+0xFF3A73B8,
+0xFF3A73B8,
+0xFF3B74B9,
+0xFF3B74B9,
+0xFF3C75BA,
+0xFF3C75BA,
+0xFF3C75BA,
+0xFF3C75BA,
+0xFF3D76B9,
+0xFF3D76B9,
+0xFF3E77BA,
+0xFF3E77BA,
+0xFF3E77BA,
+0xFF3F78BB,
+0xFF3F78BB,
+0xFF3E79BB,
+0xFF3F7ABE,
+0xFF3F7ABE,
+0xFF3F7ABE,
+0xFF3F7ABE,
+0xFF407BBF,
+0xFF417CC0,
+0xFF407DC0,
+0xFF3F7CBF,
+0xFF407DC0,
+0xFF417EC1,
+0xFF417EC1,
+0xFF427FC2,
+0xFF417EC1,
+0xFF417EC1,
+0xFF3F7EC1,
+0xFF407FC2,
+0xFF427FC2,
+0xFF427FC2,
+0xFF4380C3,
+0xFF4380C3,
+0xFF4380C1,
+0xFF4380C1,
+0xFF4380C1,
+0xFF4481C2,
+0xFF4681C3,
+0xFF4681C3,
+0xFF4681C3,
+0xFF4681C3,
+0xFF4681C3,
+0xFF4681C3,
+0xFF4681C3,
+0xFF4580C2,
+0xFF4582C3,
+0xFF4582C3,
+0xFF4582C3,
+0xFF4582C3,
+0xFF4582C3,
+0xFF4683C4,
+0xFF4683C4,
+0xFF4683C4,
+0xFF4683C4,
+0xFF4683C4,
+0xFF4683C4,
+0xFF4683C4,
+0xFF4683C4,
+0xFF4683C4,
+0xFF4683C4,
+0xFF4683C4,
+0xFF4683C4,
+0xFF4683C4,
+0xFF4683C4,
+0xFF4683C4,
+0xFF4683C4,
+0xFF4683C4,
+0xFF4683C4,
+0xFF4683C4,
+0xFF4683C4,
+0xFF4683C4,
+0xFF4683C4,
+0xFF4683C4,
+0xFF4683C4,
+0xFF4683C4,
+0xFF4683C4,
+0xFF4683C4,
+0xFF4683C4,
+0xFF4484C4,
+0xFF4683C4,
+0xFF4484C4,
+0xFF4683C4,
+0xFF4585C5,
+0xFF4784C5,
+0xFF4585C5,
+0xFF4784C5,
+0xFF4585C5,
+0xFF4784C5,
+0xFF4585C5,
+0xFF4784C5,
+0xFF4585C5,
+0xFF4683C4,
+0xFF4484C4,
+0xFF4784C5,
+0xFF4585C5,
+0xFF4784C5,
+0xFF4585C5,
+0xFF4784C5,
+0xFF4585C5,
+0xFF4585C5,
+0xFF4585C5,
+0xFF4585C5,
+0xFF4585C5,
+0xFF4585C5,
+0xFF4585C5,
+0xFF4585C5,
+0xFF4585C5,
+0xFF4686C6,
+0xFF4586C6,
+0xFF4485C5,
+0xFF4485C5,
+0xFF4485C5,
+0xFF4485C5,
+0xFF4485C5,
+0xFF4485C5,
+0xFF4485C5,
+0xFF4485C5,
+0xFF4485C5,
+0xFF4485C5,
+0xFF4485C5,
+0xFF4485C5,
+0xFF4485C5,
+0xFF4485C5,
+0xFF4485C5,
+0xFF4485C5,
+0xFF4387C8,
+0xFF4387C8,
+0xFF4586C6,
+0xFF4586C6,
+0xFF4686C6,
+0xFF4686C6,
+0xFF4586C6,
+0xFF4586C6,
+0xFF4586C6,
+0xFF4384C4,
+0xFF4787C7,
+0xFF4787C5,
+0xFF4581BF,
+0xFF4A86C2,
+0xFF639BD6,
+0xFF4984BE,
+0xFF4785C2,
+0xFF4688C5,
+0xFF4187C5,
+0xFF4286C5,
+0xFF4A87CA,
+0xFF4782C6,
+0xFF4F8ACE,
+0xFF3A5992,
+0xFF4C3758,
+0xFF482221,
+0xFF5F5025,
+0xFF999A58,
+0xFF8D9951,
+0xFF87994D,
+0xFF869C51,
+0xFF667E30,
+0xFF6A812F,
+0xFF677B22,
+0xFFBECF69,
+0xFFCDDA70,
+0xFFB9C15A,
+0xFFACB84C,
+0xFFB0C24A,
+0xFFC6C55B,
+0xFFA67D3D,
+0xFF560300,
+0xFFA42919,
+0xFF991813,
+0xFF922930,
+0xFF883644,
+0xFF65243A,
+0xFF330823,
+0xFF39284A,
+0xFF7A83AE,
+0xFF5A83B9,
+0xFF4983C2,
+0xFF4784C3,
+0xFF4586C8,
+0xFF4285CB,
+0xFF4186C9,
+0xFF4189C4,
+0xFF4288C4,
+0xFF4685C8,
+0xFF4884CA,
+0xFF4685C8,
+0xFF4387C6,
+0xFF4289C7,
+0xFF4289C7,
+0xFF4387C6,
+0xFF4586C6,
+0xFF4586C6,
+0xFF4586C6,
+0xFF4586C6,
+0xFF4586C6,
+0xFF4586C6,
+0xFF4586C6,
+0xFF4586C6,
+0xFF4586C6,
+0xFF4586C6,
+0xFF4586C6,
+0xFF4586C6,
+0xFF4586C6,
+0xFF4586C6,
+0xFF4586C6,
+0xFF4687C7,
+0xFF4687C7,
+0xFF4687C7,
+0xFF4687C7,
+0xFF4586C6,
+0xFF4586C6,
+0xFF4586C6,
+0xFF4586C6,
+0xFF4586C6,
+0xFF4586C6,
+0xFF4586C6,
+0xFF4586C6,
+0xFF4586C6,
+0xFF4586C6,
+0xFF4586C6,
+0xFF4586C6,
+0xFF4586C6,
+0xFF4586C6,
+0xFF4687C7,
+0xFF4687C7,
+0xFF4586C6,
+0xFF4586C6,
+0xFF4586C6,
+0xFF4687C7,
+0xFF4687C7,
+0xFF4687C7,
+0xFF4687C7,
+0xFF4687C7,
+0xFF4687C7,
+0xFF4586C6,
+0xFF4586C6,
+0xFF4586C6,
+0xFF4586C6,
+0xFF4586C6,
+0xFF4586C6,
+0xFF4586C6,
+0xFF4686C6,
+0xFF4686C6,
+0xFF4686C6,
+0xFF4686C6,
+0xFF4885C6,
+0xFF4784C5,
+0xFF4784C5,
+0xFF4784C5,
+0xFF4784C5,
+0xFF4784C5,
+0xFF4784C5,
+0xFF4784C5,
+0xFF4782C4,
+0xFF4782C4,
+0xFF4782C4,
+0xFF4782C4,
+0xFF4683C4,
+0xFF4582C3,
+0xFF4582C3,
+0xFF4582C3,
+0xFF4582C5,
+0xFF4582C5,
+0xFF4582C5,
+0xFF4481C4,
+0xFF4481C4,
+0xFF4481C4,
+0xFF4380C3,
+0xFF4380C3,
+0xFF4180C3,
+0xFF3F80C2,
+0xFF3F80C2,
+0xFF3F80C2,
+0xFF3F80C2,
+0xFF3E7FC1,
+0xFF3E7DC0,
+0xFF3D7CBF,
+0xFF3D7CBF,
+0xFF3E7DC0,
+0xFF407DC0,
+0xFF3E7BBE,
+0xFF3E7AC0,
+0xFF3E7AC0,
+0xFF3E7AC0,
+0xFF3E7AC0,
+0xFF3E79BF,
+0xFF3E79BF,
+0xFF3E79BF,
+0xFF3E79BF,
+0xFF3D78BE,
+0xFF3D78BE,
+0xFF3C77BD,
+0xFF3C77BD,
+0xFF3B76BC,
+0xFF3B76BC,
+0xFF3B76BC,
+0xFF3B76BC,
+0xFF3A75BB,
+0xFF3A75BB,
+0xFF3A75BB,
+0xFF3A75BB,
+0xFF3C6EB3,
+0xFF3C6EB3,
+0xFF3C6EB3,
+0xFF3C6EB3,
+0xFF3C6EB3,
+0xFF3A6FB3,
+0xFF3A6FB3,
+0xFF3A6FB3,
+0xFF3B70B4,
+0xFF3A71B4,
+0xFF3B71B7,
+0xFF3B71B7,
+0xFF3C72B8,
+0xFF3C72B8,
+0xFF3B74B9,
+0xFF3B74B9,
+0xFF3B74B9,
+0xFF3B74B9,
+0xFF3C75BA,
+0xFF3C75BA,
+0xFF3D76BB,
+0xFF3D76BB,
+0xFF3D76B9,
+0xFF3D76B9,
+0xFF3D78BA,
+0xFF3D78BA,
+0xFF3E79BB,
+0xFF3E79BB,
+0xFF3E79BB,
+0xFF3F7ABC,
+0xFF3F7ABC,
+0xFF3F7ABC,
+0xFF3F7ABC,
+0xFF3E7BBC,
+0xFF3F7CBD,
+0xFF3F7CBD,
+0xFF407DBE,
+0xFF417EBF,
+0xFF417EBF,
+0xFF417EBF,
+0xFF417EBF,
+0xFF417EBF,
+0xFF427FC0,
+0xFF427FC0,
+0xFF427FC0,
+0xFF427FC0,
+0xFF427FC0,
+0xFF4380C1,
+0xFF447FC1,
+0xFF4580C2,
+0xFF4681C3,
+0xFF4681C3,
+0xFF4580C2,
+0xFF447FC1,
+0xFF4681C3,
+0xFF4782C4,
+0xFF4681C3,
+0xFF4681C3,
+0xFF4681C3,
+0xFF4681C3,
+0xFF4782C4,
+0xFF4782C4,
+0xFF4782C4,
+0xFF4782C4,
+0xFF4582C3,
+0xFF4582C3,
+0xFF4582C3,
+0xFF4683C4,
+0xFF4683C4,
+0xFF4784C5,
+0xFF4784C5,
+0xFF4784C5,
+0xFF4784C5,
+0xFF4784C5,
+0xFF4784C5,
+0xFF4784C5,
+0xFF4784C5,
+0xFF4784C5,
+0xFF4784C5,
+0xFF4784C5,
+0xFF4784C3,
+0xFF4784C3,
+0xFF4784C3,
+0xFF4784C3,
+0xFF4784C3,
+0xFF4784C3,
+0xFF4784C3,
+0xFF4784C3,
+0xFF4784C3,
+0xFF4784C3,
+0xFF4784C3,
+0xFF4784C3,
+0xFF4784C3,
+0xFF4784C3,
+0xFF4784C3,
+0xFF4784C3,
+0xFF4484C2,
+0xFF4385C2,
+0xFF4484C2,
+0xFF4486C3,
+0xFF4585C3,
+0xFF4587C4,
+0xFF4686C4,
+0xFF4587C4,
+0xFF4585C3,
+0xFF4486C3,
+0xFF4686C4,
+0xFF4587C4,
+0xFF4686C4,
+0xFF4486C3,
+0xFF4585C3,
+0xFF4486C3,
+0xFF4585C5,
+0xFF4485C5,
+0xFF4686C6,
+0xFF4586C6,
+0xFF4686C6,
+0xFF4586C6,
+0xFF4586C6,
+0xFF4586C6,
+0xFF4586C6,
+0xFF4586C6,
+0xFF4586C6,
+0xFF4586C6,
+0xFF4586C6,
+0xFF4586C6,
+0xFF4586C6,
+0xFF4586C6,
+0xFF4586C6,
+0xFF4387C6,
+0xFF4387C6,
+0xFF4387C6,
+0xFF4387C6,
+0xFF4387C6,
+0xFF4387C6,
+0xFF4387C6,
+0xFF4387C6,
+0xFF4387C6,
+0xFF4387C6,
+0xFF4387C6,
+0xFF4387C6,
+0xFF4387C6,
+0xFF4387C6,
+0xFF4387C6,
+0xFF4488C9,
+0xFF4488C9,
+0xFF4687C7,
+0xFF4687C7,
+0xFF4787C5,
+0xFF4787C5,
+0xFF4687C7,
+0xFF4687C7,
+0xFF4687C7,
+0xFF4485C5,
+0xFF4888C6,
+0xFF4787C5,
+0xFF4985C3,
+0xFF4783BF,
+0xFF679FDA,
+0xFF4782BC,
+0xFF4785C2,
+0xFF498BC8,
+0xFF4187C3,
+0xFF4187C5,
+0xFF4889CB,
+0xFF4483C8,
+0xFF498ACE,
+0xFF517BB7,
+0xFF433B6A,
+0xFF3E2633,
+0xFF52441D,
+0xFF9A9956,
+0xFF8C964D,
+0xFF8EA056,
+0xFF899D55,
+0xFF697F37,
+0xFF6C803B,
+0xFF859849,
+0xFFB5C966,
+0xFFBBCB5E,
+0xFFA9B144,
+0xFFADB643,
+0xFFACC043,
+0xFFC0CA59,
+0xFFA58C3C,
+0xFF5B1700,
+0xFFA22A11,
+0xFFAA1C12,
+0xFF9E1912,
+0xFF872228,
+0xFF794569,
+0xFF472852,
+0xFF330826,
+0xFF412848,
+0xFF768CBE,
+0xFF5387C3,
+0xFF4486C0,
+0xFF4189C3,
+0xFF4589C6,
+0xFF4387C4,
+0xFF4389C7,
+0xFF4488C7,
+0xFF4986C9,
+0xFF4A85C9,
+0xFF4687C9,
+0xFF4488C7,
+0xFF4488C5,
+0xFF4688C5,
+0xFF4687C7,
+0xFF4687C7,
+0xFF4687C7,
+0xFF4687C7,
+0xFF4687C7,
+0xFF4687C7,
+0xFF4687C7,
+0xFF4687C7,
+0xFF4687C7,
+0xFF4687C7,
+0xFF4687C7,
+0xFF4687C7,
+0xFF4687C7,
+0xFF4687C7,
+0xFF4687C7,
+0xFF4687C7,
+0xFF4687C7,
+0xFF4687C7,
+0xFF4687C7,
+0xFF4687C7,
+0xFF4687C7,
+0xFF4687C7,
+0xFF4687C7,
+0xFF4687C7,
+0xFF4687C7,
+0xFF4687C7,
+0xFF4687C7,
+0xFF4687C7,
+0xFF4687C7,
+0xFF4687C7,
+0xFF4687C7,
+0xFF4687C7,
+0xFF4687C7,
+0xFF4687C7,
+0xFF4687C7,
+0xFF4687C7,
+0xFF4687C7,
+0xFF4687C7,
+0xFF4687C7,
+0xFF4687C7,
+0xFF4687C7,
+0xFF4687C7,
+0xFF4687C7,
+0xFF4687C7,
+0xFF4687C7,
+0xFF4687C7,
+0xFF4687C7,
+0xFF4687C7,
+0xFF4586C6,
+0xFF4586C6,
+0xFF4586C6,
+0xFF4586C6,
+0xFF4586C6,
+0xFF4586C6,
+0xFF4687C7,
+0xFF4687C7,
+0xFF4686C6,
+0xFF4686C6,
+0xFF4686C6,
+0xFF4686C6,
+0xFF4686C6,
+0xFF4686C6,
+0xFF4885C6,
+0xFF4885C6,
+0xFF4883C5,
+0xFF4883C5,
+0xFF4883C5,
+0xFF4883C5,
+0xFF4784C5,
+0xFF4683C4,
+0xFF4683C4,
+0xFF4683C4,
+0xFF4582C3,
+0xFF4582C3,
+0xFF4582C3,
+0xFF4582C3,
+0xFF4681C3,
+0xFF4681C3,
+0xFF4681C5,
+0xFF4582C5,
+0xFF4180C3,
+0xFF4081C3,
+0xFF4081C3,
+0xFF4081C3,
+0xFF4180C3,
+0xFF407FC2,
+0xFF3F7EC1,
+0xFF3E7DC0,
+0xFF3E7DC0,
+0xFF3F7EC1,
+0xFF3E7DC0,
+0xFF3D7CBF,
+0xFF3C7BBE,
+0xFF3C7BBE,
+0xFF3E7BBE,
+0xFF3E7BBE,
+0xFF3E7AC0,
+0xFF3E7AC0,
+0xFF3E7AC0,
+0xFF3E7AC0,
+0xFF3D79BF,
+0xFF3D79BF,
+0xFF3C78BE,
+0xFF3C78BE,
+0xFF3D78BC,
+0xFF3C77BB,
+0xFF3C77BB,
+0xFF3C77BB,
+0xFF3B76BA,
+0xFF3B76BA,
+0xFF3B76BA,
+0xFF3A75B9,
+0xFF3C6EB3,
+0xFF3C6EB3,
+0xFF3C6EB3,
+0xFF3C6EB3,
+0xFF3A6FB3,
+0xFF3A6FB3,
+0xFF3A6FB3,
+0xFF3A6FB3,
+0xFF3B72B5,
+0xFF3B72B5,
+0xFF3C72B8,
+0xFF3C72B8,
+0xFF3D73B9,
+0xFF3D73B9,
+0xFF3B74B9,
+0xFF3C75BA,
+0xFF3C75BA,
+0xFF3C75BA,
+0xFF3C75BA,
+0xFF3D76BB,
+0xFF3D76BB,
+0xFF3E77BC,
+0xFF3E77BA,
+0xFF3E77BA,
+0xFF3D78BA,
+0xFF3E79BB,
+0xFF3F7ABC,
+0xFF3F7ABC,
+0xFF3F7ABC,
+0xFF3F7ABC,
+0xFF407BBD,
+0xFF3F7CBD,
+0xFF3F7CBD,
+0xFF3F7CBD,
+0xFF407DBE,
+0xFF407DBE,
+0xFF417EBF,
+0xFF417EBF,
+0xFF417EBF,
+0xFF417EBF,
+0xFF417EBF,
+0xFF417EBF,
+0xFF427FC0,
+0xFF427FC0,
+0xFF427FC0,
+0xFF427FC0,
+0xFF4380C1,
+0xFF4380C1,
+0xFF447FC1,
+0xFF4580C2,
+0xFF4681C3,
+0xFF4681C3,
+0xFF4580C2,
+0xFF4580C2,
+0xFF4681C3,
+0xFF4782C4,
+0xFF4681C3,
+0xFF4681C3,
+0xFF4782C4,
+0xFF4782C4,
+0xFF4782C4,
+0xFF4782C4,
+0xFF4883C5,
+0xFF4784C5,
+0xFF4683C4,
+0xFF4683C4,
+0xFF4683C4,
+0xFF4683C4,
+0xFF4784C5,
+0xFF4784C5,
+0xFF4784C5,
+0xFF4784C5,
+0xFF4784C5,
+0xFF4784C5,
+0xFF4784C5,
+0xFF4784C5,
+0xFF4784C5,
+0xFF4784C5,
+0xFF4784C5,
+0xFF4784C5,
+0xFF4784C3,
+0xFF4784C3,
+0xFF4784C3,
+0xFF4784C3,
+0xFF4784C3,
+0xFF4784C3,
+0xFF4784C3,
+0xFF4784C3,
+0xFF4784C3,
+0xFF4784C3,
+0xFF4784C3,
+0xFF4784C3,
+0xFF4885C4,
+0xFF4885C4,
+0xFF4885C4,
+0xFF4686C4,
+0xFF4587C4,
+0xFF4587C4,
+0xFF4587C4,
+0xFF4587C4,
+0xFF4587C4,
+0xFF4486C3,
+0xFF4486C3,
+0xFF4486C3,
+0xFF4587C4,
+0xFF4587C4,
+0xFF4587C4,
+0xFF4587C4,
+0xFF4587C4,
+0xFF4587C4,
+0xFF4587C4,
+0xFF4587C4,
+0xFF4586C6,
+0xFF4586C6,
+0xFF4586C6,
+0xFF4586C6,
+0xFF4586C6,
+0xFF4586C6,
+0xFF4586C6,
+0xFF4586C6,
+0xFF4586C6,
+0xFF4586C6,
+0xFF4586C6,
+0xFF4586C6,
+0xFF4586C6,
+0xFF4586C6,
+0xFF4687C7,
+0xFF4687C7,
+0xFF4488C7,
+0xFF4488C7,
+0xFF4488C7,
+0xFF4488C7,
+0xFF4488C7,
+0xFF4488C7,
+0xFF4488C7,
+0xFF4488C7,
+0xFF4488C7,
+0xFF4488C7,
+0xFF4488C7,
+0xFF4488C7,
+0xFF4488C7,
+0xFF4488C7,
+0xFF4488C7,
+0xFF4488C7,
+0xFF4488C9,
+0xFF4488C7,
+0xFF4687C7,
+0xFF4687C7,
+0xFF4787C5,
+0xFF4787C5,
+0xFF4687C7,
+0xFF4687C7,
+0xFF4788C8,
+0xFF4485C5,
+0xFF4989C7,
+0xFF4686C3,
+0xFF4B89C6,
+0xFF4F8CC5,
+0xFF5F9AD4,
+0xFF4782BC,
+0xFF4985C3,
+0xFF498BC8,
+0xFF4288C3,
+0xFF4189C4,
+0xFF4588CC,
+0xFF4285C9,
+0xFF468ACB,
+0xFF5B8DCA,
+0xFF343F77,
+0xFF3D334C,
+0xFF3E3514,
+0xFFA09C5C,
+0xFF909A53,
+0xFF86984E,
+0xFF8CA058,
+0xFF6D813A,
+0xFF93A867,
+0xFF768B40,
+0xFF7F9332,
+0xFFB9C95C,
+0xFFB0B848,
+0xFFBAC34C,
+0xFFB9CE4F,
+0xFFB7C450,
+0xFFD9CB73,
+0xFF723B03,
+0xFF8B1D02,
+0xFF9A1005,
+0xFFAA1E11,
+0xFF932526,
+0xFF5D2B4E,
+0xFF6C527F,
+0xFF4A2449,
+0xFF2B0D31,
+0xFF34335D,
+0xFF738EBD,
+0xFF4F87BA,
+0xFF478DC1,
+0xFF4385BF,
+0xFF458AC5,
+0xFF438ACA,
+0xFF4489CA,
+0xFF4986C7,
+0xFF4A86C5,
+0xFF4787C7,
+0xFF4788C8,
+0xFF4888C6,
+0xFF4888C6,
+0xFF4788C8,
+0xFF4788C8,
+0xFF4788C8,
+0xFF4788C8,
+0xFF4788C8,
+0xFF4788C8,
+0xFF4788C8,
+0xFF4788C8,
+0xFF4788C8,
+0xFF4788C8,
+0xFF4788C8,
+0xFF4788C8,
+0xFF4788C8,
+0xFF4687C7,
+0xFF4687C7,
+0xFF4687C7,
+0xFF4788C8,
+0xFF4788C8,
+0xFF4788C8,
+0xFF4788C8,
+0xFF4788C8,
+0xFF4788C8,
+0xFF4788C8,
+0xFF4788C8,
+0xFF4788C8,
+0xFF4788C8,
+0xFF4788C8,
+0xFF4788C8,
+0xFF4788C8,
+0xFF4788C8,
+0xFF4788C8,
+0xFF4788C8,
+0xFF4687C7,
+0xFF4687C7,
+0xFF4687C7,
+0xFF4687C7,
+0xFF4687C7,
+0xFF4687C7,
+0xFF4687C7,
+0xFF4687C7,
+0xFF4788C8,
+0xFF4788C8,
+0xFF4788C8,
+0xFF4687C7,
+0xFF4687C7,
+0xFF4687C7,
+0xFF4687C7,
+0xFF4687C7,
+0xFF4687C7,
+0xFF4687C7,
+0xFF4687C7,
+0xFF4687C7,
+0xFF4687C7,
+0xFF4687C7,
+0xFF4687C7,
+0xFF4687C7,
+0xFF4787C7,
+0xFF4787C7,
+0xFF4787C7,
+0xFF4787C7,
+0xFF4787C7,
+0xFF4787C7,
+0xFF4986C7,
+0xFF4885C6,
+0xFF4986C7,
+0xFF4885C6,
+0xFF4984C6,
+0xFF4885C6,
+0xFF4885C6,
+0xFF4784C5,
+0xFF4784C5,
+0xFF4683C4,
+0xFF4683C4,
+0xFF4683C4,
+0xFF4683C4,
+0xFF4683C4,
+0xFF4782C4,
+0xFF4782C4,
+0xFF4782C6,
+0xFF4683C6,
+0xFF4281C4,
+0xFF4182C4,
+0xFF4182C4,
+0xFF4081C3,
+0xFF4180C3,
+0xFF4180C3,
+0xFF407FC2,
+0xFF407FC2,
+0xFF3F7EC1,
+0xFF3F7EC1,
+0xFF3F7EC1,
+0xFF3E7DC0,
+0xFF3D7CBF,
+0xFF3D7CBF,
+0xFF3F7CBF,
+0xFF3F7CBF,
+0xFF3F7BC1,
+0xFF3F7BC1,
+0xFF3F7BC1,
+0xFF3F7BC1,
+0xFF3E7AC0,
+0xFF3E7AC0,
+0xFF3D79BF,
+0xFF3D79BF,
+0xFF3D78BC,
+0xFF3D78BC,
+0xFF3D78BC,
+0xFF3C77BB,
+0xFF3C77BB,
+0xFF3C77BB,
+0xFF3B76BA,
+0xFF3B76BA,
+0xFF3A6FB3,
+0xFF3A6FB3,
+0xFF3A6FB3,
+0xFF3A6FB3,
+0xFF3B70B4,
+0xFF3B70B4,
+0xFF3A71B4,
+0xFF3A71B4,
+0xFF3C73B6,
+0xFF3C73B6,
+0xFF3C72B8,
+0xFF3D73B9,
+0xFF3D73B9,
+0xFF3D73B9,
+0xFF3E74BA,
+0xFF3E74BA,
+0xFF3E75B8,
+0xFF3E75B8,
+0xFF3F76B9,
+0xFF3F76B9,
+0xFF3E77BA,
+0xFF3E77BA,
+0xFF3E77BA,
+0xFF3F78BB,
+0xFF3E79BB,
+0xFF3F7ABC,
+0xFF3F7ABC,
+0xFF407BBD,
+0xFF3F7CBD,
+0xFF3F7CBD,
+0xFF3F7CBD,
+0xFF407DBE,
+0xFF407DBE,
+0xFF3E7EBE,
+0xFF3F7FBF,
+0xFF3F7FBF,
+0xFF3F7FBF,
+0xFF3F7FBF,
+0xFF3F7FBF,
+0xFF3F7FBF,
+0xFF427FC0,
+0xFF427FC0,
+0xFF427FC0,
+0xFF427FC0,
+0xFF427FC0,
+0xFF4380C1,
+0xFF4380C1,
+0xFF4481C2,
+0xFF4481C2,
+0xFF4481C2,
+0xFF4481C2,
+0xFF4582C3,
+0xFF4582C3,
+0xFF4582C3,
+0xFF4582C3,
+0xFF4582C3,
+0xFF4683C4,
+0xFF4683C4,
+0xFF4683C2,
+0xFF4683C2,
+0xFF4784C3,
+0xFF4784C3,
+0xFF4784C3,
+0xFF4784C3,
+0xFF4784C3,
+0xFF4585C3,
+0xFF4585C3,
+0xFF4585C3,
+0xFF4585C3,
+0xFF4585C3,
+0xFF4585C3,
+0xFF4585C3,
+0xFF4585C3,
+0xFF4585C3,
+0xFF4585C3,
+0xFF4585C3,
+0xFF4585C3,
+0xFF4585C3,
+0xFF4585C3,
+0xFF4585C3,
+0xFF4585C5,
+0xFF4585C5,
+0xFF4585C5,
+0xFF4686C6,
+0xFF4686C6,
+0xFF4686C6,
+0xFF4686C6,
+0xFF4585C5,
+0xFF4686C6,
+0xFF4686C6,
+0xFF4686C6,
+0xFF4585C5,
+0xFF4585C5,
+0xFF4585C5,
+0xFF4585C5,
+0xFF4585C5,
+0xFF4586C6,
+0xFF4586C6,
+0xFF4586C6,
+0xFF4586C6,
+0xFF4586C6,
+0xFF4586C6,
+0xFF4485C5,
+0xFF4485C5,
+0xFF4586C6,
+0xFF4586C6,
+0xFF4586C6,
+0xFF4586C6,
+0xFF4586C6,
+0xFF4586C6,
+0xFF4586C6,
+0xFF4586C6,
+0xFF4586C6,
+0xFF4586C6,
+0xFF4586C6,
+0xFF4586C6,
+0xFF4586C6,
+0xFF4586C6,
+0xFF4687C7,
+0xFF4687C7,
+0xFF4586C6,
+0xFF4586C6,
+0xFF4687C7,
+0xFF4687C7,
+0xFF4687C7,
+0xFF4687C7,
+0xFF4687C7,
+0xFF4687C7,
+0xFF4687C7,
+0xFF4687C7,
+0xFF4687C7,
+0xFF4687C7,
+0xFF4687C7,
+0xFF4687C7,
+0xFF4687C7,
+0xFF4687C7,
+0xFF4687C7,
+0xFF4687C7,
+0xFF4687C7,
+0xFF4687C7,
+0xFF4687C7,
+0xFF4687C7,
+0xFF4687C7,
+0xFF4687C7,
+0xFF4687C7,
+0xFF4687C7,
+0xFF4687C7,
+0xFF4688C5,
+0xFF4787C5,
+0xFF4787C5,
+0xFF4688C5,
+0xFF4688C5,
+0xFF4889C9,
+0xFF4384C4,
+0xFF498BC8,
+0xFF4787C4,
+0xFF4583C0,
+0xFF66A3DC,
+0xFF4A85BF,
+0xFF4C87C1,
+0xFF4B87C3,
+0xFF4789C5,
+0xFF4389C5,
+0xFF438AC8,
+0xFF4388CB,
+0xFF4487CB,
+0xFF4589C6,
+0xFF558DCA,
+0xFF4A66A7,
+0xFF3A4267,
+0xFF363219,
+0xFF9A985D,
+0xFF8C9752,
+0xFF899B51,
+0xFFA5B76D,
+0xFF8FA35B,
+0xFF697F37,
+0xFF687F31,
+0xFF718526,
+0xFFBDCE64,
+0xFFB1BE4C,
+0xFFB5C048,
+0xFFB4C545,
+0xFFAEB742,
+0xFFBBAF59,
+0xFF6A3D06,
+0xFF80210D,
+0xFF90170F,
+0xFF901408,
+0xFF89211E,
+0xFF6C3145,
+0xFF573D64,
+0xFF4F4A82,
+0xFF342D60,
+0xFF290B27,
+0xFF47334E,
+0xFF7691BE,
+0xFF5286BF,
+0xFF4885BE,
+0xFF4789C6,
+0xFF418BCC,
+0xFF418BCA,
+0xFF458AC3,
+0xFF4A88C1,
+0xFF4A88C3,
+0xFF4A87C6,
+0xFF4B88C9,
+0xFF4988CB,
+0xFF4788C8,
+0xFF4789C6,
+0xFF4789C6,
+0xFF4789C6,
+0xFF4789C6,
+0xFF4789C6,
+0xFF4789C6,
+0xFF4789C6,
+0xFF488AC7,
+0xFF488AC7,
+0xFF488AC7,
+0xFF4789C6,
+0xFF4789C6,
+0xFF4789C6,
+0xFF4789C6,
+0xFF4789C6,
+0xFF468AC7,
+0xFF468AC7,
+0xFF468AC7,
+0xFF468AC7,
+0xFF468AC7,
+0xFF468AC7,
+0xFF468AC7,
+0xFF4589C6,
+0xFF4589C6,
+0xFF4589C6,
+0xFF4589C6,
+0xFF4589C6,
+0xFF4589C6,
+0xFF4589C6,
+0xFF4589C6,
+0xFF4589C6,
+0xFF4589C6,
+0xFF4589C6,
+0xFF4589C6,
+0xFF4589C6,
+0xFF4589C6,
+0xFF4589C6,
+0xFF4589C6,
+0xFF4589C6,
+0xFF4589C6,
+0xFF4589C6,
+0xFF4589C6,
+0xFF4589C6,
+0xFF4589C6,
+0xFF4589C6,
+0xFF4589C6,
+0xFF4589C6,
+0xFF468AC7,
+0xFF4589C6,
+0xFF4589C6,
+0xFF4589C6,
+0xFF4789C6,
+0xFF4688C5,
+0xFF4688C5,
+0xFF4688C5,
+0xFF4688C5,
+0xFF4688C5,
+0xFF4688C5,
+0xFF4688C5,
+0xFF4688C5,
+0xFF4688C5,
+0xFF4787C5,
+0xFF4787C5,
+0xFF4787C7,
+0xFF4787C7,
+0xFF4986C7,
+0xFF4686C6,
+0xFF4686C6,
+0xFF4585C5,
+0xFF4585C5,
+0xFF4585C5,
+0xFF4585C5,
+0xFF4585C5,
+0xFF4585C5,
+0xFF4484C4,
+0xFF4683C4,
+0xFF4683C4,
+0xFF4683C4,
+0xFF4683C4,
+0xFF4383C3,
+0xFF4383C3,
+0xFF4282C2,
+0xFF4282C2,
+0xFF4282C2,
+0xFF4282C2,
+0xFF4180C3,
+0xFF4180C3,
+0xFF407FC2,
+0xFF407FC2,
+0xFF3F7EC1,
+0xFF3F7EC1,
+0xFF3F7EC1,
+0xFF3E7DC0,
+0xFF3E7DC0,
+0xFF3E7DC0,
+0xFF407DC0,
+0xFF407DC0,
+0xFF3F7CBF,
+0xFF3F7CBF,
+0xFF3F7CBF,
+0xFF3E7BBE,
+0xFF3E7BBE,
+0xFF3E7BBE,
+0xFF3E79BD,
+0xFF3E79BD,
+0xFF3D78BC,
+0xFF3D78BC,
+0xFF3D78BC,
+0xFF3D78BC,
+0xFF3D76BB,
+0xFF3C75BA,
+0xFF3A6FB3,
+0xFF3A6FB3,
+0xFF3A6FB3,
+0xFF3B70B4,
+0xFF3B70B4,
+0xFF3C71B5,
+0xFF3B72B5,
+0xFF3B72B5,
+0xFF3C73B6,
+0xFF3C73B6,
+0xFF3D73B9,
+0xFF3D73B9,
+0xFF3E74BA,
+0xFF3E74BA,
+0xFF3E74BA,
+0xFF3E74BA,
+0xFF3F76B9,
+0xFF3F76B9,
+0xFF4077BA,
+0xFF4077BA,
+0xFF3F78BB,
+0xFF3F78BB,
+0xFF3F78BB,
+0xFF3F78BB,
+0xFF3F7ABC,
+0xFF3F7ABC,
+0xFF407BBD,
+0xFF407BBD,
+0xFF3F7CBD,
+0xFF407DBE,
+0xFF407DBE,
+0xFF407DBE,
+0xFF3F7FBF,
+0xFF3F7FBF,
+0xFF4080C0,
+0xFF4080C0,
+0xFF3F7FBF,
+0xFF3F7FBF,
+0xFF3F7FBF,
+0xFF4080C0,
+0xFF4380C1,
+0xFF4380C1,
+0xFF4481C2,
+0xFF4481C2,
+0xFF4481C2,
+0xFF4481C2,
+0xFF4582C3,
+0xFF4582C3,
+0xFF4582C3,
+0xFF4582C3,
+0xFF4582C3,
+0xFF4582C3,
+0xFF4683C4,
+0xFF4683C4,
+0xFF4683C4,
+0xFF4683C4,
+0xFF4683C4,
+0xFF4784C5,
+0xFF4784C3,
+0xFF4784C3,
+0xFF4784C3,
+0xFF4784C3,
+0xFF4885C4,
+0xFF4686C4,
+0xFF4686C4,
+0xFF4686C4,
+0xFF4686C4,
+0xFF4686C4,
+0xFF4585C3,
+0xFF4585C3,
+0xFF4585C3,
+0xFF4585C3,
+0xFF4686C4,
+0xFF4686C4,
+0xFF4686C4,
+0xFF4686C4,
+0xFF4686C4,
+0xFF4686C4,
+0xFF4686C4,
+0xFF4686C4,
+0xFF4686C6,
+0xFF4686C6,
+0xFF4686C6,
+0xFF4787C7,
+0xFF4787C7,
+0xFF4787C7,
+0xFF4787C7,
+0xFF4787C7,
+0xFF4686C6,
+0xFF4686C6,
+0xFF4686C6,
+0xFF4686C6,
+0xFF4686C6,
+0xFF4686C6,
+0xFF4686C6,
+0xFF4686C6,
+0xFF4586C6,
+0xFF4586C6,
+0xFF4586C6,
+0xFF4586C6,
+0xFF4687C7,
+0xFF4687C7,
+0xFF4687C7,
+0xFF4687C7,
+0xFF4586C6,
+0xFF4586C6,
+0xFF4687C7,
+0xFF4687C7,
+0xFF4687C7,
+0xFF4687C7,
+0xFF4687C7,
+0xFF4687C7,
+0xFF4687C7,
+0xFF4687C7,
+0xFF4687C7,
+0xFF4687C7,
+0xFF4687C7,
+0xFF4687C7,
+0xFF4687C7,
+0xFF4687C7,
+0xFF4687C7,
+0xFF4687C7,
+0xFF4687C7,
+0xFF4687C7,
+0xFF4687C7,
+0xFF4687C7,
+0xFF4687C7,
+0xFF4687C7,
+0xFF4788C8,
+0xFF4788C8,
+0xFF4788C8,
+0xFF4788C8,
+0xFF4687C7,
+0xFF4687C7,
+0xFF4687C7,
+0xFF4687C7,
+0xFF4687C7,
+0xFF4687C7,
+0xFF4788C8,
+0xFF4788C8,
+0xFF4788C8,
+0xFF4788C8,
+0xFF4788C8,
+0xFF4788C8,
+0xFF4788C8,
+0xFF4788C8,
+0xFF4789C6,
+0xFF4789C6,
+0xFF4888C6,
+0xFF4888C6,
+0xFF4789C6,
+0xFF4789C6,
+0xFF4889C9,
+0xFF4687C7,
+0xFF488AC7,
+0xFF4587C3,
+0xFF4886C3,
+0xFF6AA8E3,
+0xFF4580BA,
+0xFF4C89C2,
+0xFF4B89C4,
+0xFF4688C4,
+0xFF458BC9,
+0xFF448BCB,
+0xFF4388CB,
+0xFF4589CA,
+0xFF4789C3,
+0xFF4C88C4,
+0xFF608BD0,
+0xFF283F6B,
+0xFF2E2F21,
+0xFF959360,
+0xFF909C5A,
+0xFFACC176,
+0xFF97A85A,
+0xFF66782C,
+0xFF6E8439,
+0xFF6D8635,
+0xFF6D8227,
+0xFFABBD57,
+0xFFB1C24F,
+0xFFB4C448,
+0xFFB5C447,
+0xFFA9B040,
+0xFFA99F4A,
+0xFF815A23,
+0xFF6F1908,
+0xFF821210,
+0xFF8B1209,
+0xFF7D100B,
+0xFF651822,
+0xFF533051,
+0xFF415496,
+0xFF304888,
+0xFF422949,
+0xFF321028,
+0xFF424067,
+0xFF748BBD,
+0xFF5986BF,
+0xFF4D89C7,
+0xFF458ACB,
+0xFF428CCB,
+0xFF458CC4,
+0xFF488BC2,
+0xFF4989C6,
+0xFF4B88C7,
+0xFF4989C9,
+0xFF4889C9,
+0xFF488AC7,
+0xFF488AC7,
+0xFF488AC7,
+0xFF488AC7,
+0xFF488AC7,
+0xFF488AC7,
+0xFF488AC7,
+0xFF488AC7,
+0xFF488AC7,
+0xFF488AC7,
+0xFF488AC7,
+0xFF488AC7,
+0xFF488AC7,
+0xFF488AC7,
+0xFF488AC7,
+0xFF488AC7,
+0xFF478BC8,
+0xFF478BC8,
+0xFF478BC8,
+0xFF468AC7,
+0xFF468AC7,
+0xFF468AC7,
+0xFF468AC7,
+0xFF468AC7,
+0xFF468AC7,
+0xFF468AC7,
+0xFF468AC7,
+0xFF468AC7,
+0xFF468AC7,
+0xFF468AC7,
+0xFF468AC7,
+0xFF468AC7,
+0xFF468AC7,
+0xFF468AC7,
+0xFF4589C6,
+0xFF468AC7,
+0xFF468AC7,
+0xFF468AC7,
+0xFF468AC7,
+0xFF468AC7,
+0xFF4589C6,
+0xFF4589C6,
+0xFF468AC7,
+0xFF468AC7,
+0xFF468AC7,
+0xFF468AC7,
+0xFF468AC7,
+0xFF468AC7,
+0xFF478BC8,
+0xFF468AC7,
+0xFF468AC7,
+0xFF468AC7,
+0xFF4789C6,
+0xFF4789C6,
+0xFF4789C6,
+0xFF4789C6,
+0xFF4789C6,
+0xFF4789C6,
+0xFF4789C6,
+0xFF4789C6,
+0xFF4688C5,
+0xFF4688C5,
+0xFF4787C5,
+0xFF4787C5,
+0xFF4787C7,
+0xFF4687C7,
+0xFF4787C7,
+0xFF4687C7,
+0xFF4787C7,
+0xFF4586C6,
+0xFF4686C6,
+0xFF4686C6,
+0xFF4686C6,
+0xFF4686C6,
+0xFF4686C6,
+0xFF4585C5,
+0xFF4784C5,
+0xFF4683C4,
+0xFF4683C4,
+0xFF4683C4,
+0xFF4585C5,
+0xFF4484C4,
+0xFF4383C3,
+0xFF4383C3,
+0xFF4383C3,
+0xFF4383C3,
+0xFF4382C5,
+0xFF4281C4,
+0xFF4180C3,
+0xFF407FC2,
+0xFF407FC2,
+0xFF407FC2,
+0xFF407FC2,
+0xFF407FC2,
+0xFF3F7EC1,
+0xFF407FC2,
+0xFF407DC0,
+0xFF407DC0,
+0xFF407DC0,
+0xFF407DC0,
+0xFF3F7CBF,
+0xFF3F7CBF,
+0xFF3E7BBE,
+0xFF3E7BBE,
+0xFF3F7ABE,
+0xFF3E79BD,
+0xFF3E79BD,
+0xFF3D78BC,
+0xFF3E79BD,
+0xFF3E79BD,
+0xFF3E77BC,
+0xFF3D76BB,
+0xFF3A71B4,
+0xFF3A71B4,
+0xFF3A71B4,
+0xFF3B72B5,
+0xFF3B72B5,
+0xFF3C73B6,
+0xFF3C73B6,
+0xFF3D74B7,
+0xFF3D74B7,
+0xFF3D74B7,
+0xFF3D73B9,
+0xFF3E74BA,
+0xFF3E74BA,
+0xFF3F75BB,
+0xFF3F75BB,
+0xFF3F75BB,
+0xFF4077BA,
+0xFF4077B8,
+0xFF4077B8,
+0xFF4178B9,
+0xFF4079BC,
+0xFF4079BC,
+0xFF4079BC,
+0xFF4079BC,
+0xFF407BBD,
+0xFF407BBD,
+0xFF407DBE,
+0xFF407DBE,
+0xFF407DC0,
+0xFF417EC1,
+0xFF417EC1,
+0xFF417EC1,
+0xFF3F7FBF,
+0xFF3F80C0,
+0xFF4080C0,
+0xFF4080C0,
+0xFF4080C0,
+0xFF4080C0,
+0xFF4181C1,
+0xFF4181C1,
+0xFF4380C1,
+0xFF4481C2,
+0xFF4582C3,
+0xFF4582C3,
+0xFF4582C3,
+0xFF4683C4,
+0xFF4782C4,
+0xFF4782C4,
+0xFF4683C4,
+0xFF4683C4,
+0xFF4683C4,
+0xFF4784C5,
+0xFF4585C5,
+0xFF4585C5,
+0xFF4585C5,
+0xFF4585C5,
+0xFF4686C4,
+0xFF4686C4,
+0xFF4686C4,
+0xFF4686C4,
+0xFF4686C4,
+0xFF4686C4,
+0xFF4686C4,
+0xFF4686C4,
+0xFF4686C4,
+0xFF4686C4,
+0xFF4686C4,
+0xFF4686C4,
+0xFF4686C4,
+0xFF4686C4,
+0xFF4686C4,
+0xFF4686C4,
+0xFF4787C5,
+0xFF4787C5,
+0xFF4787C5,
+0xFF4787C5,
+0xFF4787C5,
+0xFF4787C5,
+0xFF4787C5,
+0xFF4787C5,
+0xFF4687C7,
+0xFF4687C7,
+0xFF4687C7,
+0xFF4687C7,
+0xFF4788C8,
+0xFF4788C8,
+0xFF4788C8,
+0xFF4788C8,
+0xFF4687C7,
+0xFF4687C7,
+0xFF4687C7,
+0xFF4687C7,
+0xFF4687C7,
+0xFF4687C7,
+0xFF4687C7,
+0xFF4687C7,
+0xFF4687C7,
+0xFF4687C7,
+0xFF4687C7,
+0xFF4687C7,
+0xFF4687C7,
+0xFF4788C8,
+0xFF4788C8,
+0xFF4788C8,
+0xFF4687C7,
+0xFF4687C7,
+0xFF4687C7,
+0xFF4788C8,
+0xFF4788C8,
+0xFF4788C8,
+0xFF4788C8,
+0xFF4687C7,
+0xFF4687C7,
+0xFF4788C8,
+0xFF4788C8,
+0xFF4788C8,
+0xFF4788C8,
+0xFF4788C8,
+0xFF4788C8,
+0xFF4788C8,
+0xFF4788C8,
+0xFF4788C8,
+0xFF4888C8,
+0xFF4888C8,
+0xFF4888C8,
+0xFF4888C8,
+0xFF4888C8,
+0xFF4888C8,
+0xFF4989C9,
+0xFF4888C8,
+0xFF4888C8,
+0xFF4888C8,
+0xFF4888C8,
+0xFF4888C8,
+0xFF4888C8,
+0xFF4888C8,
+0xFF4888C8,
+0xFF4888C8,
+0xFF4888C8,
+0xFF4888C8,
+0xFF4989C9,
+0xFF4989C9,
+0xFF4989C9,
+0xFF4989C9,
+0xFF488AC7,
+0xFF488AC7,
+0xFF4989C7,
+0xFF4989C7,
+0xFF4989C6,
+0xFF4989C6,
+0xFF488AC7,
+0xFF488AC7,
+0xFF4788C8,
+0xFF4A8BCB,
+0xFF4789C6,
+0xFF4688C4,
+0xFF4C8AC7,
+0xFF62A0DB,
+0xFF4D88C2,
+0xFF4B88C1,
+0xFF4B89C2,
+0xFF4789C5,
+0xFF458ACD,
+0xFF448ACF,
+0xFF458ACD,
+0xFF4789C6,
+0xFF498AC0,
+0xFF4987C0,
+0xFF548BCE,
+0xFF385C8C,
+0xFF212620,
+0xFFACAA81,
+0xFFA3B173,
+0xFF81964B,
+0xFFA5B364,
+0xFF748332,
+0xFF6F8636,
+0xFF6E8734,
+0xFF6B832D,
+0xFF8AA03C,
+0xFFB5CC57,
+0xFFB2C649,
+0xFFA5B23E,
+0xFF9DA039,
+0xFFB6AE59,
+0xFF977339,
+0xFF5B0A00,
+0xFF730302,
+0xFF7F0000,
+0xFF890C08,
+0xFF861B21,
+0xFF693452,
+0xFF305397,
+0xFF18519E,
+0xFF37467F,
+0xFF3C2B55,
+0xFF300E2F,
+0xFF5B456B,
+0xFF748ABC,
+0xFF5283BE,
+0xFF4D89C8,
+0xFF478BCA,
+0xFF468AC9,
+0xFF458BC9,
+0xFF458ACB,
+0xFF468CCA,
+0xFF458DC7,
+0xFF468CC7,
+0xFF478BC8,
+0xFF498BC8,
+0xFF498BC8,
+0xFF498BC8,
+0xFF498BC8,
+0xFF498BC8,
+0xFF498BC8,
+0xFF498BC8,
+0xFF498BC8,
+0xFF498BC8,
+0xFF498BC8,
+0xFF498BC8,
+0xFF498BC8,
+0xFF498BC8,
+0xFF498BC8,
+0xFF498BC8,
+0xFF478BC8,
+0xFF478BC8,
+0xFF478BC8,
+0xFF478BC8,
+0xFF478BC8,
+0xFF478BC8,
+0xFF478BC8,
+0xFF478BC8,
+0xFF478BC8,
+0xFF478BC8,
+0xFF478BC8,
+0xFF478BC8,
+0xFF478BC8,
+0xFF478BC8,
+0xFF478BC8,
+0xFF478BC8,
+0xFF478BC8,
+0xFF468AC7,
+0xFF468AC7,
+0xFF468AC7,
+0xFF468AC7,
+0xFF478BC8,
+0xFF468AC7,
+0xFF468AC7,
+0xFF478BC8,
+0xFF478BC8,
+0xFF478BC8,
+0xFF478BC8,
+0xFF478BC8,
+0xFF478BC8,
+0xFF478BC8,
+0xFF478BC8,
+0xFF478BC8,
+0xFF478BC8,
+0xFF468AC7,
+0xFF468AC7,
+0xFF468AC7,
+0xFF468AC7,
+0xFF468AC7,
+0xFF468AC7,
+0xFF488AC7,
+0xFF488AC7,
+0xFF488AC7,
+0xFF488AC7,
+0xFF4789C6,
+0xFF4789C6,
+0xFF4789C6,
+0xFF4789C6,
+0xFF4789C6,
+0xFF4589C6,
+0xFF4789C6,
+0xFF4488C5,
+0xFF4687C7,
+0xFF4488C7,
+0xFF4687C7,
+0xFF4687C7,
+0xFF4687C7,
+0xFF4687C7,
+0xFF4586C6,
+0xFF4586C6,
+0xFF4686C6,
+0xFF4585C5,
+0xFF4585C5,
+0xFF4585C5,
+0xFF4784C5,
+0xFF4784C5,
+0xFF4484C4,
+0xFF4484C4,
+0xFF4484C4,
+0xFF4484C4,
+0xFF4383C3,
+0xFF4383C3,
+0xFF4382C5,
+0xFF4281C4,
+0xFF4180C3,
+0xFF4180C3,
+0xFF4180C3,
+0xFF407FC2,
+0xFF407FC2,
+0xFF407FC2,
+0xFF3F7EC1,
+0xFF3F7EC1,
+0xFF417EC1,
+0xFF407DC0,
+0xFF407DC0,
+0xFF407DC0,
+0xFF3F7CBF,
+0xFF3F7CBF,
+0xFF407BBF,
+0xFF3F7ABE,
+0xFF3E79BB,
+0xFF3E79BB,
+0xFF4079BC,
+0xFF4079BC,
+0xFF3F78BB,
+0xFF3E77BA,
+0xFF3C71B5,
+0xFF3B72B5,
+0xFF3B72B5,
+0xFF3C73B6,
+0xFF3C73B6,
+0xFF3D74B7,
+0xFF3D74B7,
+0xFF3D74B7,
+0xFF3D74B7,
+0xFF3F74B8,
+0xFF3F74BA,
+0xFF3F74BA,
+0xFF3F75BB,
+0xFF3F76B9,
+0xFF3F76B9,
+0xFF3F76B9,
+0xFF4077B8,
+0xFF3F79B9,
+0xFF4178B9,
+0xFF407ABA,
+0xFF4079BC,
+0xFF417ABD,
+0xFF417ABD,
+0xFF407BBD,
+0xFF407BBD,
+0xFF417CBE,
+0xFF417EBF,
+0xFF417EBF,
+0xFF417EC1,
+0xFF417EC1,
+0xFF427FC2,
+0xFF4080C0,
+0xFF3F7FBF,
+0xFF4080C0,
+0xFF4181C1,
+0xFF4181C1,
+0xFF4181C1,
+0xFF4181C1,
+0xFF4282C2,
+0xFF4282C2,
+0xFF4481C2,
+0xFF4481C2,
+0xFF4683C4,
+0xFF4683C4,
+0xFF4683C4,
+0xFF4683C4,
+0xFF4782C4,
+0xFF4782C4,
+0xFF4683C4,
+0xFF4784C5,
+0xFF4885C6,
+0xFF4885C6,
+0xFF4585C5,
+0xFF4585C5,
+0xFF4686C6,
+0xFF4787C7,
+0xFF4686C4,
+0xFF4686C4,
+0xFF4787C5,
+0xFF4787C5,
+0xFF4787C5,
+0xFF4787C5,
+0xFF4688C5,
+0xFF4688C5,
+0xFF4686C4,
+0xFF4787C5,
+0xFF4787C5,
+0xFF4787C5,
+0xFF4787C5,
+0xFF4787C5,
+0xFF4787C5,
+0xFF4787C5,
+0xFF4787C5,
+0xFF4787C5,
+0xFF4787C5,
+0xFF4787C5,
+0xFF4787C5,
+0xFF4787C5,
+0xFF4787C5,
+0xFF4787C5,
+0xFF4687C7,
+0xFF4687C7,
+0xFF4687C7,
+0xFF4788C8,
+0xFF4788C8,
+0xFF4788C8,
+0xFF4788C8,
+0xFF4788C8,
+0xFF4788C8,
+0xFF4788C8,
+0xFF4788C8,
+0xFF4788C8,
+0xFF4788C8,
+0xFF4788C8,
+0xFF4788C8,
+0xFF4788C8,
+0xFF4788C8,
+0xFF4788C8,
+0xFF4888C8,
+0xFF4788C8,
+0xFF4788C8,
+0xFF4788C8,
+0xFF4788C8,
+0xFF4788C8,
+0xFF4788C8,
+0xFF4788C8,
+0xFF4788C8,
+0xFF4788C8,
+0xFF4788C8,
+0xFF4788C8,
+0xFF4788C8,
+0xFF4788C8,
+0xFF4788C8,
+0xFF4788C8,
+0xFF4788C8,
+0xFF4788C8,
+0xFF4788C8,
+0xFF4788C8,
+0xFF4788C8,
+0xFF4788C8,
+0xFF4788C8,
+0xFF4788C8,
+0xFF4989C9,
+0xFF4989C9,
+0xFF4989C9,
+0xFF4989C9,
+0xFF4888C8,
+0xFF4888C8,
+0xFF4989C9,
+0xFF4989C9,
+0xFF4989C9,
+0xFF4989C9,
+0xFF4989C9,
+0xFF4989C9,
+0xFF4989C9,
+0xFF4989C9,
+0xFF4989C9,
+0xFF4989C9,
+0xFF4989C9,
+0xFF4989C9,
+0xFF4989C9,
+0xFF4989C9,
+0xFF4A8ACA,
+0xFF4A8ACA,
+0xFF488AC7,
+0xFF488AC7,
+0xFF4989C7,
+0xFF4B88C7,
+0xFF4989C6,
+0xFF4989C6,
+0xFF468AC7,
+0xFF468AC7,
+0xFF478BCA,
+0xFF478BCA,
+0xFF478BCA,
+0xFF4B8DCA,
+0xFF4383C0,
+0xFF67A5E0,
+0xFF4A85BF,
+0xFF4E8BC4,
+0xFF4889BF,
+0xFF468BC6,
+0xFF468BCE,
+0xFF4489CE,
+0xFF488CCD,
+0xFF4789C5,
+0xFF4C8BC0,
+0xFF4D8AC1,
+0xFF4B87C6,
+0xFF5D87B9,
+0xFF6B747D,
+0xFF7F7F63,
+0xFF86955A,
+0xFF869B4C,
+0xFFABBA69,
+0xFF6F812D,
+0xFF6F8634,
+0xFF6E8734,
+0xFF6E8733,
+0xFF728B2D,
+0xFFB6CE5C,
+0xFFA9BD44,
+0xFF9FAB3B,
+0xFFB7BC55,
+0xFFD3CF76,
+0xFF957538,
+0xFF651401,
+0xFF922425,
+0xFFAA302B,
+0xFFAF342F,
+0xFF9E2A2D,
+0xFF62233E,
+0xFF2E569B,
+0xFF0551A5,
+0xFF1B4994,
+0xFF313B76,
+0xFF452348,
+0xFF350E2D,
+0xFF58517A,
+0xFF748CBC,
+0xFF5586C0,
+0xFF4A8AC8,
+0xFF498ACA,
+0xFF468BCC,
+0xFF438DCE,
+0xFF428ECA,
+0xFF428FC5,
+0xFF438FC3,
+0xFF478CC7,
+0xFF498BC8,
+0xFF498BC8,
+0xFF498BC8,
+0xFF498BC8,
+0xFF498BC8,
+0xFF498BC8,
+0xFF498BC8,
+0xFF498BC8,
+0xFF498BC8,
+0xFF498BC8,
+0xFF498BC8,
+0xFF498BC8,
+0xFF498BC8,
+0xFF498BC8,
+0xFF498BC8,
+0xFF488CC9,
+0xFF478BC8,
+0xFF478BC8,
+0xFF478BC8,
+0xFF478BC8,
+0xFF478BC8,
+0xFF478BC8,
+0xFF478BC8,
+0xFF478BC8,
+0xFF478BC8,
+0xFF478BC8,
+0xFF478BC8,
+0xFF478BC8,
+0xFF478BC8,
+0xFF478BC8,
+0xFF478BC8,
+0xFF478BC8,
+0xFF468AC7,
+0xFF468AC7,
+0xFF468AC7,
+0xFF478BC8,
+0xFF478BC8,
+0xFF478BC8,
+0xFF468AC7,
+0xFF478BC8,
+0xFF478BC8,
+0xFF478BC8,
+0xFF478BC8,
+0xFF488CC9,
+0xFF488CC9,
+0xFF488CC9,
+0xFF488CC9,
+0xFF478BC8,
+0xFF468AC7,
+0xFF468AC7,
+0xFF468AC7,
+0xFF468AC7,
+0xFF468AC7,
+0xFF478BC8,
+0xFF478BC8,
+0xFF498BC8,
+0xFF498BC8,
+0xFF498BC8,
+0xFF488AC7,
+0xFF488AC7,
+0xFF4789C6,
+0xFF4789C6,
+0xFF4789C6,
+0xFF4589C6,
+0xFF4589C6,
+0xFF4589C6,
+0xFF4589C6,
+0xFF4589C8,
+0xFF4589C8,
+0xFF4488C7,
+0xFF4488C7,
+0xFF4687C7,
+0xFF4687C7,
+0xFF4687C7,
+0xFF4687C7,
+0xFF4686C6,
+0xFF4686C6,
+0xFF4686C6,
+0xFF4686C6,
+0xFF4885C6,
+0xFF4784C5,
+0xFF4484C4,
+0xFF4484C4,
+0xFF4484C4,
+0xFF4484C4,
+0xFF4484C4,
+0xFF4484C4,
+0xFF4483C6,
+0xFF4382C5,
+0xFF4281C4,
+0xFF4281C4,
+0xFF4281C4,
+0xFF4180C3,
+0xFF407FC2,
+0xFF407FC2,
+0xFF3F7EC1,
+0xFF3F7EC1,
+0xFF417EC1,
+0xFF417EC1,
+0xFF407DC0,
+0xFF407DC0,
+0xFF407DC0,
+0xFF3F7CBF,
+0xFF417CC0,
+0xFF407BBF,
+0xFF3F7ABC,
+0xFF3F7ABC,
+0xFF4079BC,
+0xFF4079BC,
+0xFF3F78BB,
+0xFF3E77BA,
+0xFF3E70B7,
+0xFF3C71B7,
+0xFF3B72B5,
+0xFF3C73B6,
+0xFF3B75B5,
+0xFF3B75B5,
+0xFF3C75B8,
+0xFF3E75B8,
+0xFF3F74B8,
+0xFF4274B9,
+0xFF4274B9,
+0xFF4375BA,
+0xFF4176BA,
+0xFF4077B8,
+0xFF4178B8,
+0xFF3F79B8,
+0xFF3F79B9,
+0xFF3F7ABC,
+0xFF4079BC,
+0xFF3F7ABC,
+0xFF3F7ABC,
+0xFF407BBD,
+0xFF417CBE,
+0xFF427DBF,
+0xFF427DBF,
+0xFF417EBF,
+0xFF417EBF,
+0xFF417EBF,
+0xFF417EBF,
+0xFF417EBF,
+0xFF4080C0,
+0xFF4080C0,
+0xFF4181C1,
+0xFF4380BF,
+0xFF4481C0,
+0xFF4481C0,
+0xFF4481C2,
+0xFF4481C2,
+0xFF4481C2,
+0xFF4582C3,
+0xFF4683C4,
+0xFF4683C4,
+0xFF4783C2,
+0xFF4783C2,
+0xFF4783C2,
+0xFF4783C2,
+0xFF4783C2,
+0xFF4783C2,
+0xFF4885C4,
+0xFF4885C4,
+0xFF4885C4,
+0xFF4885C4,
+0xFF4686C4,
+0xFF4686C4,
+0xFF4686C4,
+0xFF4686C4,
+0xFF4686C4,
+0xFF4686C4,
+0xFF4787C5,
+0xFF4787C5,
+0xFF4787C5,
+0xFF4787C5,
+0xFF4787C5,
+0xFF4787C5,
+0xFF4787C5,
+0xFF4787C5,
+0xFF4787C5,
+0xFF4888C6,
+0xFF4888C6,
+0xFF4888C6,
+0xFF4888C6,
+0xFF4888C6,
+0xFF4888C6,
+0xFF4888C6,
+0xFF4888C6,
+0xFF4888C6,
+0xFF4888C6,
+0xFF4888C6,
+0xFF4888C6,
+0xFF4888C6,
+0xFF4989C7,
+0xFF4888C6,
+0xFF4888C6,
+0xFF4989C7,
+0xFF4888C6,
+0xFF4787C5,
+0xFF4787C5,
+0xFF4888C6,
+0xFF4888C6,
+0xFF4888C6,
+0xFF4888C6,
+0xFF4888C6,
+0xFF4888C6,
+0xFF4888C6,
+0xFF4888C6,
+0xFF4888C6,
+0xFF4888C6,
+0xFF4888C6,
+0xFF4A87C6,
+0xFF4888C6,
+0xFF4888C6,
+0xFF4989C7,
+0xFF4989C7,
+0xFF4989C7,
+0xFF4989C7,
+0xFF4989C7,
+0xFF4989C7,
+0xFF4989C7,
+0xFF4989C7,
+0xFF4989C7,
+0xFF4989C7,
+0xFF4989C7,
+0xFF488AC7,
+0xFF488AC7,
+0xFF488AC7,
+0xFF488AC7,
+0xFF488AC7,
+0xFF498BC8,
+0xFF498BC8,
+0xFF498BC8,
+0xFF498BC8,
+0xFF498BC8,
+0xFF498BC8,
+0xFF498BC8,
+0xFF498BC8,
+0xFF498BC8,
+0xFF498BC8,
+0xFF498BC8,
+0xFF498BC8,
+0xFF498BC8,
+0xFF498BC8,
+0xFF498BC8,
+0xFF498BC8,
+0xFF488AC7,
+0xFF488AC7,
+0xFF498BC8,
+0xFF488AC7,
+0xFF488AC7,
+0xFF488AC7,
+0xFF498BC8,
+0xFF498BC8,
+0xFF498BC8,
+0xFF498BC8,
+0xFF498BC8,
+0xFF498ACA,
+0xFF4A8ACA,
+0xFF4C89C8,
+0xFF4D89C8,
+0xFF4C8AC7,
+0xFF498BC7,
+0xFF468CC8,
+0xFF438EC8,
+0xFF468DCB,
+0xFF438AC8,
+0xFF478DCB,
+0xFF468AC9,
+0xFF5F9FDC,
+0xFF4F8DC8,
+0xFF4F8AC4,
+0xFF4886BF,
+0xFF478CC3,
+0xFF458BC6,
+0xFF478ACE,
+0xFF4689CD,
+0xFF468BC6,
+0xFF4B8CC4,
+0xFF4F8BC1,
+0xFF4B82BA,
+0xFF72A8E4,
+0xFF81A9DA,
+0xFF2C3852,
+0xFF595C53,
+0xFF8B9D61,
+0xFF849C46,
+0xFFACC06B,
+0xFF738732,
+0xFF728B37,
+0xFF6C8935,
+0xFF6C8935,
+0xFF688227,
+0xFFAABD54,
+0xFFAABB49,
+0xFFB1BF4D,
+0xFFC2CE60,
+0xFFB9BD5E,
+0xFF896B2B,
+0xFF802918,
+0xFF932528,
+0xFF821B16,
+0xFF6F0704,
+0xFF7D1015,
+0xFF551633,
+0xFF284A8A,
+0xFF0957AC,
+0xFF0B51A9,
+0xFF1F4B96,
+0xFF393768,
+0xFF482B49,
+0xFF350F26,
+0xFF655570,
+0xFF6D8FBF,
+0xFF4D8BC6,
+0xFF4A8AC7,
+0xFF468AC7,
+0xFF408AC9,
+0xFF4692CE,
+0xFF3F8CC2,
+0xFF4692C6,
+0xFF478DC8,
+0xFF488DC8,
+0xFF488DC8,
+0xFF488DC8,
+0xFF488DC8,
+0xFF488DC8,
+0xFF488DC8,
+0xFF488DC8,
+0xFF488CC9,
+0xFF488CC9,
+0xFF488CC9,
+0xFF488CC9,
+0xFF488CC9,
+0xFF488CC9,
+0xFF488CC9,
+0xFF488CC9,
+0xFF488CC9,
+0xFF488CC9,
+0xFF488CC9,
+0xFF488CC9,
+0xFF478BC8,
+0xFF478BC8,
+0xFF478BC8,
+0xFF488CC9,
+0xFF488CC9,
+0xFF488CC9,
+0xFF488CC9,
+0xFF488CC9,
+0xFF488CC9,
+0xFF488CC9,
+0xFF478BC8,
+0xFF478BC8,
+0xFF478BC8,
+0xFF488CC9,
+0xFF488CC9,
+0xFF488CC9,
+0xFF488CC9,
+0xFF488CC9,
+0xFF488CC9,
+0xFF488CC9,
+0xFF478BC8,
+0xFF478BC8,
+0xFF478BC8,
+0xFF488CC9,
+0xFF478BC8,
+0xFF478BC8,
+0xFF478BC8,
+0xFF468AC7,
+0xFF478CC7,
+0xFF478CC7,
+0xFF478CC7,
+0xFF478CC7,
+0xFF478BC8,
+0xFF478BC8,
+0xFF478BC8,
+0xFF478BC8,
+0xFF478BC8,
+0xFF478BC8,
+0xFF498BC8,
+0xFF498BC8,
+0xFF498BC8,
+0xFF498BC8,
+0xFF498BC8,
+0xFF498BC8,
+0xFF4789C6,
+0xFF488AC7,
+0xFF488AC7,
+0xFF488AC7,
+0xFF4889C9,
+0xFF4889C9,
+0xFF4788C8,
+0xFF4788C8,
+0xFF4787C7,
+0xFF4787C7,
+0xFF4787C7,
+0xFF4787C7,
+0xFF4787C7,
+0xFF4787C7,
+0xFF4787C7,
+0xFF4787C7,
+0xFF4686C4,
+0xFF4686C4,
+0xFF4686C6,
+0xFF4686C6,
+0xFF4585C5,
+0xFF4585C5,
+0xFF4484C4,
+0xFF4484C4,
+0xFF4784C5,
+0xFF4683C4,
+0xFF4582C3,
+0xFF4582C3,
+0xFF4481C2,
+0xFF4481C2,
+0xFF4380C1,
+0xFF4080C0,
+0xFF4181C1,
+0xFF3F80C0,
+0xFF407FC2,
+0xFF407FC2,
+0xFF407FC2,
+0xFF407FC2,
+0xFF417EC1,
+0xFF417EC1,
+0xFF407DC0,
+0xFF407DC0,
+0xFF417CC0,
+0xFF417CC0,
+0xFF417CC0,
+0xFF407BBF,
+0xFF3F7ABE,
+0xFF3E79BD,
+0xFF3F71B8,
+0xFF3D72B8,
+0xFF3D74B7,
+0xFF3B74B7,
+0xFF3C76B6,
+0xFF3B77B6,
+0xFF3D76B9,
+0xFF3F76B9,
+0xFF4075B9,
+0xFF4274B9,
+0xFF4475BA,
+0xFF4375BA,
+0xFF4176B8,
+0xFF4077B8,
+0xFF3F79B8,
+0xFF407AB9,
+0xFF3F7BBA,
+0xFF3F7ABC,
+0xFF407BBD,
+0xFF407BBD,
+0xFF407BBD,
+0xFF417CBE,
+0xFF427DBF,
+0xFF427DBF,
+0xFF417EBF,
+0xFF417EBF,
+0xFF427FC0,
+0xFF427FC0,
+0xFF427FC0,
+0xFF427FC0,
+0xFF4181C1,
+0xFF4181C1,
+0xFF4380BF,
+0xFF4481C0,
+0xFF4582C1,
+0xFF4582C1,
+0xFF4582C3,
+0xFF4582C3,
+0xFF4582C3,
+0xFF4683C4,
+0xFF4683C4,
+0xFF4683C4,
+0xFF4783C2,
+0xFF4783C2,
+0xFF4884C3,
+0xFF4884C3,
+0xFF4985C3,
+0xFF4886C3,
+0xFF4986C5,
+0xFF4986C5,
+0xFF4986C5,
+0xFF4986C5,
+0xFF4787C5,
+0xFF4787C5,
+0xFF4787C5,
+0xFF4787C5,
+0xFF4787C5,
+0xFF4787C5,
+0xFF4787C5,
+0xFF4787C5,
+0xFF4787C5,
+0xFF4888C6,
+0xFF4888C6,
+0xFF4888C6,
+0xFF4888C6,
+0xFF4888C6,
+0xFF4888C6,
+0xFF4888C6,
+0xFF4888C6,
+0xFF4888C6,
+0xFF4888C6,
+0xFF4888C6,
+0xFF4888C6,
+0xFF4888C6,
+0xFF4888C6,
+0xFF4888C6,
+0xFF4888C6,
+0xFF4888C6,
+0xFF4888C6,
+0xFF4888C6,
+0xFF4989C7,
+0xFF4888C6,
+0xFF4888C6,
+0xFF4989C7,
+0xFF4989C7,
+0xFF4888C6,
+0xFF4888C6,
+0xFF4989C7,
+0xFF4989C7,
+0xFF4989C7,
+0xFF4989C7,
+0xFF4989C7,
+0xFF4989C7,
+0xFF4989C7,
+0xFF4989C7,
+0xFF4989C7,
+0xFF4B88C7,
+0xFF4B88C7,
+0xFF4B88C7,
+0xFF4B88C7,
+0xFF4989C7,
+0xFF4989C7,
+0xFF4989C7,
+0xFF4989C7,
+0xFF4989C7,
+0xFF4989C7,
+0xFF4989C7,
+0xFF4A8AC8,
+0xFF4A8AC8,
+0xFF4A8AC8,
+0xFF4989C7,
+0xFF4989C7,
+0xFF498BC8,
+0xFF498BC8,
+0xFF498BC8,
+0xFF498BC8,
+0xFF498BC8,
+0xFF498BC8,
+0xFF498BC8,
+0xFF498BC8,
+0xFF498BC8,
+0xFF498BC8,
+0xFF498BC8,
+0xFF498BC8,
+0xFF498BC8,
+0xFF498BC8,
+0xFF498BC8,
+0xFF498BC8,
+0xFF498BC8,
+0xFF498BC8,
+0xFF4A8CC9,
+0xFF498BC8,
+0xFF498BC8,
+0xFF498BC8,
+0xFF498BC8,
+0xFF498BC8,
+0xFF498BC8,
+0xFF498BC8,
+0xFF498BC8,
+0xFF498BC8,
+0xFF498BC8,
+0xFF498BC8,
+0xFF498BC8,
+0xFF498BC8,
+0xFF498ACA,
+0xFF498BC8,
+0xFF4A8AC8,
+0xFF4A8AC7,
+0xFF4B8BC8,
+0xFF4A8CC8,
+0xFF478DC8,
+0xFF468EC9,
+0xFF458DC8,
+0xFF488FCD,
+0xFF4187C5,
+0xFF468AC7,
+0xFF68A8E5,
+0xFF4B89C4,
+0xFF4B88C1,
+0xFF5391CA,
+0xFF458AC1,
+0xFF4990C8,
+0xFF4D8ED0,
+0xFF498ACA,
+0xFF498BC5,
+0xFF4485BB,
+0xFF5A96CC,
+0xFF7AB3EA,
+0xFF568EC7,
+0xFF5886B8,
+0xFF556B92,
+0xFF243235,
+0xFF849760,
+0xFF839742,
+0xFFBCCE78,
+0xFF7F933C,
+0xFF708935,
+0xFF6E8B37,
+0xFF6B8834,
+0xFF6B852C,
+0xFF90A23E,
+0xFFB7C75C,
+0xFFADBE4E,
+0xFFA3B046,
+0xFFABB054,
+0xFF876E2E,
+0xFF631000,
+0xFF730609,
+0xFF740E09,
+0xFF77110D,
+0xFF962D34,
+0xFF4B102E,
+0xFF2B5094,
+0xFF0459B3,
+0xFF0050B0,
+0xFF0E50A7,
+0xFF325090,
+0xFF332B54,
+0xFF532436,
+0xFF3E1324,
+0xFF5F6386,
+0xFF7193C3,
+0xFF5886C1,
+0xFF508CCA,
+0xFF4B91CD,
+0xFF438FC9,
+0xFF4692C6,
+0xFF458EC3,
+0xFF4990C8,
+0xFF4A8FCA,
+0xFF4A8FCA,
+0xFF4A8FCA,
+0xFF4A8FCA,
+0xFF4A8FCA,
+0xFF4A8FCA,
+0xFF4A8FCA,
+0xFF4A8ECB,
+0xFF4A8ECB,
+0xFF4A8ECB,
+0xFF4A8ECB,
+0xFF498DCA,
+0xFF498DCA,
+0xFF498DCA,
+0xFF498DCA,
+0xFF4A8ECB,
+0xFF4A8ECB,
+0xFF4A8ECB,
+0xFF4A8ECB,
+0xFF498DCA,
+0xFF498DCA,
+0xFF498DCA,
+0xFF498DCA,
+0xFF498DCA,
+0xFF498DCA,
+0xFF498DCA,
+0xFF498DCA,
+0xFF498DCA,
+0xFF498DCA,
+0xFF488CC9,
+0xFF488CC9,
+0xFF488CC9,
+0xFF488CC9,
+0xFF498DCA,
+0xFF498DCA,
+0xFF498DCA,
+0xFF498DCA,
+0xFF498DCA,
+0xFF498DCA,
+0xFF488CC9,
+0xFF488CC9,
+0xFF488CC9,
+0xFF498DCA,
+0xFF498DCA,
+0xFF488CC9,
+0xFF488CC9,
+0xFF488CC9,
+0xFF488DC8,
+0xFF488DC8,
+0xFF488DC8,
+0xFF488DC8,
+0xFF488CC9,
+0xFF488CC9,
+0xFF488CC9,
+0xFF488CC9,
+0xFF488CC9,
+0xFF488CC9,
+0xFF498BC8,
+0xFF498BC8,
+0xFF498BC8,
+0xFF498BC8,
+0xFF498BC8,
+0xFF498BC8,
+0xFF488AC7,
+0xFF488AC7,
+0xFF498BC8,
+0xFF498BC8,
+0xFF498ACA,
+0xFF498ACA,
+0xFF4889C9,
+0xFF4889C9,
+0xFF4989C9,
+0xFF4989C9,
+0xFF4888C8,
+0xFF4888C8,
+0xFF4888C8,
+0xFF4888C8,
+0xFF4888C8,
+0xFF4787C7,
+0xFF4787C5,
+0xFF4787C5,
+0xFF4686C6,
+0xFF4686C6,
+0xFF4686C6,
+0xFF4585C5,
+0xFF4585C5,
+0xFF4585C5,
+0xFF4784C5,
+0xFF4784C5,
+0xFF4683C4,
+0xFF4582C3,
+0xFF4582C3,
+0xFF4582C3,
+0xFF4481C2,
+0xFF4380C1,
+0xFF4181C1,
+0xFF4081C1,
+0xFF407FC2,
+0xFF407FC2,
+0xFF407FC2,
+0xFF407FC2,
+0xFF427FC2,
+0xFF417EC1,
+0xFF417EC1,
+0xFF417EC1,
+0xFF417CC0,
+0xFF417CC0,
+0xFF417CC0,
+0xFF417CC0,
+0xFF407BBF,
+0xFF3F7ABE,
+0xFF3E73B7,
+0xFF3E73B7,
+0xFF3D74B7,
+0xFF3C75B8,
+0xFF3C76B6,
+0xFF3C78B7,
+0xFF3D76B9,
+0xFF3F76B9,
+0xFF4075BB,
+0xFF4176BC,
+0xFF4375BC,
+0xFF4476BB,
+0xFF4277B9,
+0xFF4178B9,
+0xFF407AB9,
+0xFF407AB9,
+0xFF407CBB,
+0xFF407BBD,
+0xFF417CBE,
+0xFF417CBE,
+0xFF427DBF,
+0xFF427DBF,
+0xFF417EBF,
+0xFF427FC0,
+0xFF427FC0,
+0xFF427FC0,
+0xFF4380C1,
+0xFF4380C1,
+0xFF4380C1,
+0xFF4380C1,
+0xFF4481C2,
+0xFF4582C3,
+0xFF4481C0,
+0xFF4582C1,
+0xFF4683C2,
+0xFF4683C2,
+0xFF4683C4,
+0xFF4683C4,
+0xFF4683C4,
+0xFF4784C5,
+0xFF4683C4,
+0xFF4784C5,
+0xFF4784C3,
+0xFF4784C3,
+0xFF4885C4,
+0xFF4986C5,
+0xFF4987C4,
+0xFF4987C4,
+0xFF4986C5,
+0xFF4787C5,
+0xFF4888C6,
+0xFF4888C6,
+0xFF4888C6,
+0xFF4888C6,
+0xFF4888C6,
+0xFF4888C6,
+0xFF4888C6,
+0xFF4888C6,
+0xFF4888C6,
+0xFF4888C6,
+0xFF4888C6,
+0xFF4989C7,
+0xFF4989C7,
+0xFF4989C7,
+0xFF4989C7,
+0xFF4989C7,
+0xFF4989C7,
+0xFF4989C7,
+0xFF4989C7,
+0xFF4989C7,
+0xFF4989C7,
+0xFF4989C7,
+0xFF4989C7,
+0xFF4989C7,
+0xFF4989C7,
+0xFF4989C7,
+0xFF4989C7,
+0xFF4989C7,
+0xFF4989C7,
+0xFF4989C7,
+0xFF4989C7,
+0xFF4888C6,
+0xFF4888C6,
+0xFF4989C7,
+0xFF4A8AC8,
+0xFF4989C7,
+0xFF4A8AC8,
+0xFF4A8AC8,
+0xFF4989C7,
+0xFF4A8AC8,
+0xFF4A8AC8,
+0xFF4A8AC8,
+0xFF4A8AC8,
+0xFF4A8AC8,
+0xFF4A8AC8,
+0xFF4A8AC8,
+0xFF4A8AC8,
+0xFF4A8AC8,
+0xFF4A8AC8,
+0xFF4A8AC8,
+0xFF4A8AC8,
+0xFF4A8AC8,
+0xFF4A8AC8,
+0xFF4A8AC8,
+0xFF4A8AC8,
+0xFF4A8AC8,
+0xFF4A8AC8,
+0xFF4A8AC8,
+0xFF4A8AC8,
+0xFF4A8AC8,
+0xFF498BC8,
+0xFF498BC8,
+0xFF4A8CC9,
+0xFF4A8CC9,
+0xFF498BC8,
+0xFF498BC8,
+0xFF498BC8,
+0xFF498BC8,
+0xFF498BC8,
+0xFF498BC8,
+0xFF498BC8,
+0xFF498BC8,
+0xFF498BC8,
+0xFF498BC8,
+0xFF498BC8,
+0xFF498BC8,
+0xFF498BC8,
+0xFF498BC8,
+0xFF478BC8,
+0xFF488CC9,
+0xFF488CC9,
+0xFF488CC9,
+0xFF478BC8,
+0xFF478BC8,
+0xFF478BC8,
+0xFF488CC9,
+0xFF488CC9,
+0xFF488CC9,
+0xFF488CC9,
+0xFF488CC9,
+0xFF488CC9,
+0xFF488CC9,
+0xFF488CC9,
+0xFF488CC9,
+0xFF4A8CC9,
+0xFF488CC9,
+0xFF478DC9,
+0xFF478FC9,
+0xFF488ECA,
+0xFF498DCA,
+0xFF4C8CC9,
+0xFF4C8CC9,
+0xFF468AC7,
+0xFF4B91CD,
+0xFF488EC9,
+0xFF4A8FC8,
+0xFF67A8E2,
+0xFF4687C1,
+0xFF4D8EC6,
+0xFF498AC0,
+0xFF4B8CC4,
+0xFF4D8EC6,
+0xFF4C8CC9,
+0xFF4C8DC7,
+0xFF4B8CC4,
+0xFF70B1E7,
+0xFF67A4DA,
+0xFF4887BD,
+0xFF498BC5,
+0xFF4D88C0,
+0xFF668CBB,
+0xFF102A37,
+0xFF94A37A,
+0xFF939E52,
+0xFFE5EF99,
+0xFF8C9A42,
+0xFF738B35,
+0xFF718F39,
+0xFF6A8733,
+0xFF6F8930,
+0xFF768B26,
+0xFFAABB51,
+0xFF9FAE47,
+0xFF929D3F,
+0xFF999C4B,
+0xFF5F4610,
+0xFF611807,
+0xFF720A09,
+0xFF800B04,
+0xFFA02D28,
+0xFF80181F,
+0xFF431434,
+0xFF24569F,
+0xFF0060BF,
+0xFF045DC1,
+0xFF0D5CBB,
+0xFF114FA2,
+0xFF324A86,
+0xFF42223A,
+0xFF561E29,
+0xFF401425,
+0xFF796686,
+0xFF798CC4,
+0xFF5986C7,
+0xFF4D8BC6,
+0xFF488FC7,
+0xFF4A91C7,
+0xFF4B92C8,
+0xFF4A8FC8,
+0xFF4A8FCA,
+0xFF4A8FCA,
+0xFF4A8FCA,
+0xFF4A8FCA,
+0xFF4A8FCA,
+0xFF4A8FCA,
+0xFF4A8FCA,
+0xFF4A8FCA,
+0xFF4A8FCA,
+0xFF4A8FCA,
+0xFF4A8FCA,
+0xFF4A8ECB,
+0xFF4A8ECB,
+0xFF4A8ECB,
+0xFF4A8ECB,
+0xFF4A8FCA,
+0xFF4A8FCA,
+0xFF4B90CB,
+0xFF4A8FCA,
+0xFF4A8FCA,
+0xFF4A8FCA,
+0xFF4A8FCA,
+0xFF4A8FCA,
+0xFF4A8FCA,
+0xFF4A8FCA,
+0xFF4A8FCA,
+0xFF4A8FCA,
+0xFF4A8FCA,
+0xFF4A8FCA,
+0xFF4A8FCA,
+0xFF4A8FCA,
+0xFF4A8FCA,
+0xFF4A8FCA,
+0xFF4A8FCA,
+0xFF4A8FCA,
+0xFF4A8FCA,
+0xFF4A8FCA,
+0xFF4A8FCA,
+0xFF4A8FCA,
+0xFF4A8FCA,
+0xFF4A8FCA,
+0xFF4A8FCA,
+0xFF4A8FCA,
+0xFF4A8FCA,
+0xFF4A8FCA,
+0xFF4A8FCA,
+0xFF498EC9,
+0xFF4A8FCA,
+0xFF4A8FCA,
+0xFF4A8FCA,
+0xFF4A8FCA,
+0xFF4A8FCA,
+0xFF4A8FCA,
+0xFF498EC9,
+0xFF498EC9,
+0xFF498DCA,
+0xFF498DCA,
+0xFF488CC9,
+0xFF488CC9,
+0xFF488CC9,
+0xFF478BC8,
+0xFF478BC8,
+0xFF478BC8,
+0xFF498BC8,
+0xFF498BC8,
+0xFF498BC8,
+0xFF498BC8,
+0xFF498BC8,
+0xFF498BC8,
+0xFF498BC8,
+0xFF488AC7,
+0xFF498ACA,
+0xFF498ACA,
+0xFF4A8ACA,
+0xFF4989C9,
+0xFF4989C9,
+0xFF4888C8,
+0xFF4888C8,
+0xFF4888C8,
+0xFF4888C6,
+0xFF4888C6,
+0xFF4787C5,
+0xFF4787C5,
+0xFF4787C5,
+0xFF4686C4,
+0xFF4686C6,
+0xFF4686C6,
+0xFF4885C6,
+0xFF4784C5,
+0xFF4784C5,
+0xFF4683C4,
+0xFF4683C4,
+0xFF4683C4,
+0xFF4582C3,
+0xFF4582C3,
+0xFF4383C3,
+0xFF4282C2,
+0xFF4282C2,
+0xFF4181C1,
+0xFF4181C1,
+0xFF4181C1,
+0xFF427FC2,
+0xFF427FC2,
+0xFF427FC2,
+0xFF417EC1,
+0xFF417EC1,
+0xFF417EC1,
+0xFF427DC1,
+0xFF427DC1,
+0xFF417CC0,
+0xFF407BBF,
+0xFF3E73B7,
+0xFF3E73B7,
+0xFF3E75B8,
+0xFF3E75B8,
+0xFF3D77B7,
+0xFF3C78B7,
+0xFF3E77BA,
+0xFF3E77BA,
+0xFF4076BC,
+0xFF4176BC,
+0xFF4277BD,
+0xFF4277BD,
+0xFF4279BC,
+0xFF407ABA,
+0xFF407ABA,
+0xFF407CBB,
+0xFF407CBB,
+0xFF417CBE,
+0xFF427DBF,
+0xFF437EC0,
+0xFF437EC0,
+0xFF437EC0,
+0xFF427FC0,
+0xFF427FC0,
+0xFF427FC0,
+0xFF4380C1,
+0xFF4380C1,
+0xFF4481C2,
+0xFF4481C2,
+0xFF4481C2,
+0xFF4582C3,
+0xFF4683C4,
+0xFF4582C1,
+0xFF4683C2,
+0xFF4683C2,
+0xFF4784C3,
+0xFF4784C5,
+0xFF4784C5,
+0xFF4784C5,
+0xFF4784C5,
+0xFF4885C6,
+0xFF4885C6,
+0xFF4885C4,
+0xFF4986C5,
+0xFF4986C5,
+0xFF4986C5,
+0xFF4987C4,
+0xFF4A88C5,
+0xFF4888C6,
+0xFF4888C6,
+0xFF4888C6,
+0xFF4888C6,
+0xFF4888C6,
+0xFF4888C6,
+0xFF4989C7,
+0xFF4989C7,
+0xFF4989C7,
+0xFF4989C7,
+0xFF4989C7,
+0xFF4989C7,
+0xFF4989C7,
+0xFF4989C7,
+0xFF4989C7,
+0xFF4989C7,
+0xFF4989C7,
+0xFF4989C7,
+0xFF4989C7,
+0xFF4989C7,
+0xFF4989C7,
+0xFF4989C7,
+0xFF4989C7,
+0xFF4989C7,
+0xFF4989C7,
+0xFF4A8AC8,
+0xFF4A8AC8,
+0xFF4A8AC8,
+0xFF4A8AC8,
+0xFF4A8AC8,
+0xFF4A8AC8,
+0xFF4A8AC8,
+0xFF4A8AC8,
+0xFF4989C7,
+0xFF4A8AC8,
+0xFF4B8BC9,
+0xFF4B8BC9,
+0xFF4B8BC9,
+0xFF4B8BC9,
+0xFF4C8CCA,
+0xFF4A8AC8,
+0xFF4A8AC8,
+0xFF4A8AC8,
+0xFF4B8BC9,
+0xFF4B8BC9,
+0xFF4B8BC9,
+0xFF4B8BC9,
+0xFF4A8AC8,
+0xFF4B8BC9,
+0xFF4B8BC9,
+0xFF4B8BC9,
+0xFF4B8BC9,
+0xFF4B8BC9,
+0xFF4B8BC9,
+0xFF4A8AC8,
+0xFF4A8AC8,
+0xFF4A8AC8,
+0xFF4A8AC8,
+0xFF4B8BC9,
+0xFF4B8BC9,
+0xFF4B8BC9,
+0xFF4B8BC9,
+0xFF4A8CC9,
+0xFF4A8CC9,
+0xFF4A8CC9,
+0xFF4A8CC9,
+0xFF4A8CC9,
+0xFF4A8CC9,
+0xFF4A8CC9,
+0xFF4A8CC9,
+0xFF4A8CC9,
+0xFF4A8CC9,
+0xFF4A8CC9,
+0xFF4A8CC9,
+0xFF4A8CC9,
+0xFF4A8CC9,
+0xFF4A8CC9,
+0xFF4A8CC9,
+0xFF4B8DCA,
+0xFF4B8DCA,
+0xFF488CC9,
+0xFF488CC9,
+0xFF498DCA,
+0xFF498DCA,
+0xFF488CC9,
+0xFF488CC9,
+0xFF488CC9,
+0xFF488CC9,
+0xFF498DCA,
+0xFF498DCA,
+0xFF498DCA,
+0xFF498DCA,
+0xFF498DCA,
+0xFF498DCA,
+0xFF498DCA,
+0xFF498DCA,
+0xFF4A8FCA,
+0xFF498FCA,
+0xFF4691CA,
+0xFF4691CB,
+0xFF4690CD,
+0xFF498FCB,
+0xFF4F8DCA,
+0xFF4F8DCA,
+0xFF4D8DCA,
+0xFF4C8EC8,
+0xFF4588BF,
+0xFF478ABF,
+0xFF67AAE1,
+0xFF4A8DC4,
+0xFF4E91C8,
+0xFF4E8FC5,
+0xFF518FC8,
+0xFF4E8BC4,
+0xFF4685BB,
+0xFF5D9CD2,
+0xFF71B2EA,
+0xFF4F90C6,
+0xFF4788BE,
+0xFF4D90C7,
+0xFF4890CB,
+0xFF5095CE,
+0xFF5E96C9,
+0xFF22465E,
+0xFF566347,
+0xFFE1E3A4,
+0xFFDCE191,
+0xFF9AA44D,
+0xFF768832,
+0xFF748D39,
+0xFF6C8A34,
+0xFF6E8B31,
+0xFF728B26,
+0xFF92A742,
+0xFF8EA241,
+0xFF8D9943,
+0xFF918E49,
+0xFF4A2A00,
+0xFF590A00,
+0xFF8C1E1D,
+0xFFA72A24,
+0xFF98211D,
+0xFF6C0D15,
+0xFF411F40,
+0xFF1B59A4,
+0xFF0870CF,
+0xFF025EC1,
+0xFF004CAC,
+0xFF0352AE,
+0xFF164891,
+0xFF453F6B,
+0xFF491F33,
+0xFF601E28,
+0xFF4D1425,
+0xFF5D4C78,
+0xFF7083BB,
+0xFF5B8CC6,
+0xFF4E8FC9,
+0xFF4C8EC8,
+0xFF488DC6,
+0xFF4B90CB,
+0xFF4B90CB,
+0xFF4B90CB,
+0xFF4B90CB,
+0xFF4B90CB,
+0xFF4B90CB,
+0xFF4B90CB,
+0xFF4B90CB,
+0xFF4B90CB,
+0xFF4B90CB,
+0xFF4B90CB,
+0xFF4B90CB,
+0xFF4A8ECB,
+0xFF4A8ECB,
+0xFF4A8ECB,
+0xFF4A8ECB,
+0xFF4B90CB,
+0xFF4B90CB,
+0xFF4B90CB,
+0xFF4B90CB,
+0xFF4B90CB,
+0xFF4B90CB,
+0xFF4B90CB,
+0xFF4B90CB,
+0xFF4B90CB,
+0xFF4B90CB,
+0xFF4B90CB,
+0xFF4B90CB,
+0xFF4B90CB,
+0xFF4B90CB,
+0xFF4B90CB,
+0xFF4B90CB,
+0xFF4B90CB,
+0xFF4B90CB,
+0xFF4B90CB,
+0xFF4B90CB,
+0xFF4B90CB,
+0xFF4B90CB,
+0xFF4B90CB,
+0xFF4B90CB,
+0xFF4B90CB,
+0xFF4B90CB,
+0xFF4B90CB,
+0xFF4B90CB,
+0xFF4B90CB,
+0xFF4B90CB,
+0xFF4B90CB,
+0xFF4B90CB,
+0xFF4B90CB,
+0xFF4B90CB,
+0xFF4B90CB,
+0xFF4B90CB,
+0xFF4B90CB,
+0xFF4B90CB,
+0xFF4B90CB,
+0xFF4B90CB,
+0xFF4A8ECB,
+0xFF4A8ECB,
+0xFF4A8ECB,
+0xFF4A8ECB,
+0xFF498DCA,
+0xFF498DCA,
+0xFF498DCA,
+0xFF498DCA,
+0xFF498BC8,
+0xFF498BC8,
+0xFF498BC8,
+0xFF498BC8,
+0xFF498BC8,
+0xFF498BC8,
+0xFF498BC8,
+0xFF498BC8,
+0xFF498ACA,
+0xFF498ACA,
+0xFF4A8ACA,
+0xFF4A8ACA,
+0xFF4989C9,
+0xFF4989C9,
+0xFF4989C9,
+0xFF4989C9,
+0xFF4888C6,
+0xFF4888C6,
+0xFF4888C6,
+0xFF4888C6,
+0xFF4888C6,
+0xFF4787C5,
+0xFF4787C7,
+0xFF4787C7,
+0xFF4885C6,
+0xFF4784C5,
+0xFF4784C5,
+0xFF4784C5,
+0xFF4784C5,
+0xFF4683C4,
+0xFF4683C4,
+0xFF4683C4,
+0xFF4484C4,
+0xFF4383C3,
+0xFF4282C2,
+0xFF4282C2,
+0xFF4282C2,
+0xFF4181C1,
+0xFF4380C3,
+0xFF427FC2,
+0xFF427FC2,
+0xFF427FC2,
+0xFF417EC1,
+0xFF417EC1,
+0xFF427DC1,
+0xFF427DC1,
+0xFF427DC1,
+0xFF417CC0,
+0xFF3F74B8,
+0xFF3F74B8,
+0xFF3E75B6,
+0xFF3F76B7,
+0xFF3E78B8,
+0xFF3E78B8,
+0xFF3F78BB,
+0xFF3F78BB,
+0xFF4177BD,
+0xFF4177BD,
+0xFF4177BD,
+0xFF4278BE,
+0xFF4279BC,
+0xFF417BBB,
+0xFF417BBB,
+0xFF407CBB,
+0xFF417DBC,
+0xFF417EBD,
+0xFF427FBE,
+0xFF427FBE,
+0xFF427FBE,
+0xFF427FBE,
+0xFF4380BF,
+0xFF4380BF,
+0xFF4380BF,
+0xFF4481C0,
+0xFF4582C1,
+0xFF4582C1,
+0xFF4582C1,
+0xFF4683C2,
+0xFF4683C2,
+0xFF4784C3,
+0xFF4683C2,
+0xFF4683C2,
+0xFF4784C3,
+0xFF4784C3,
+0xFF4784C5,
+0xFF4784C5,
+0xFF4885C6,
+0xFF4885C6,
+0xFF4986C7,
+0xFF4986C7,
+0xFF4787C5,
+0xFF4888C6,
+0xFF4888C6,
+0xFF4888C6,
+0xFF4888C6,
+0xFF4989C7,
+0xFF4888C6,
+0xFF4888C6,
+0xFF4888C6,
+0xFF4989C7,
+0xFF4989C7,
+0xFF4989C7,
+0xFF4989C7,
+0xFF4989C7,
+0xFF4989C7,
+0xFF4989C7,
+0xFF4989C7,
+0xFF4989C7,
+0xFF4C89C8,
+0xFF4C89C8,
+0xFF4C89C8,
+0xFF4C89C8,
+0xFF4989C6,
+0xFF4A8AC7,
+0xFF4A8AC7,
+0xFF4A8AC7,
+0xFF4A8AC7,
+0xFF4A8AC7,
+0xFF4A8AC7,
+0xFF4A8AC7,
+0xFF4A8AC7,
+0xFF4A8AC7,
+0xFF4A8AC7,
+0xFF4A8AC7,
+0xFF4A8AC7,
+0xFF4A8AC7,
+0xFF4A8AC7,
+0xFF4A8AC7,
+0xFF4B8BC9,
+0xFF4A8AC8,
+0xFF4A8AC8,
+0xFF4B8BC9,
+0xFF4B8BC9,
+0xFF4B8BC9,
+0xFF4B8BC9,
+0xFF4C8CCA,
+0xFF4A8CC9,
+0xFF4A8CC9,
+0xFF4A8CC9,
+0xFF4A8CC9,
+0xFF4A8CC9,
+0xFF4A8CC9,
+0xFF4A8CC9,
+0xFF4A8CC9,
+0xFF4B8DC9,
+0xFF4B8DC9,
+0xFF4A8CC8,
+0xFF4A8CC8,
+0xFF4A8CC8,
+0xFF4A8CC8,
+0xFF4A8CC8,
+0xFF4A8CC8,
+0xFF4A8CC8,
+0xFF4A8CC8,
+0xFF4A8CC8,
+0xFF4A8CC8,
+0xFF4A8CC8,
+0xFF4A8CC8,
+0xFF4A8CC8,
+0xFF4A8CC8,
+0xFF498EC9,
+0xFF498EC9,
+0xFF498EC9,
+0xFF498EC9,
+0xFF498EC9,
+0xFF4A8FCA,
+0xFF4A8FCA,
+0xFF4A8FCA,
+0xFF498EC9,
+0xFF498EC9,
+0xFF498EC9,
+0xFF498EC9,
+0xFF498EC9,
+0xFF4A8FCA,
+0xFF4A8FCA,
+0xFF4A8FCA,
+0xFF498EC9,
+0xFF498EC9,
+0xFF4A8FCA,
+0xFF4A8FCA,
+0xFF498EC9,
+0xFF498EC9,
+0xFF498EC9,
+0xFF4A8FCA,
+0xFF4A8FCA,
+0xFF4A8FCA,
+0xFF4A8FCA,
+0xFF4A8FCA,
+0xFF4A8FCA,
+0xFF4A8FCA,
+0xFF4A8FCA,
+0xFF4A8FCA,
+0xFF4A91C9,
+0xFF4992C9,
+0xFF4991CB,
+0xFF4792CC,
+0xFF4692CE,
+0xFF4791CE,
+0xFF4B8FCC,
+0xFF4E8ECB,
+0xFF4F8BC7,
+0xFF508DC4,
+0xFF5392C7,
+0xFF5A9DD1,
+0xFF5298CC,
+0xFF4A90C4,
+0xFF4E8FC7,
+0xFF4D8BC4,
+0xFF518CC6,
+0xFF528DC5,
+0xFF77B5E8,
+0xFF62A1D4,
+0xFF4E8CC5,
+0xFF4F90CA,
+0xFF4D90C5,
+0xFF488FC5,
+0xFF4490CA,
+0xFF4792CC,
+0xFF5095CC,
+0xFF305E7F,
+0xFF232D22,
+0xFFDBD4A8,
+0xFFE2E39D,
+0xFFA6AE59,
+0xFF798531,
+0xFF7A8E37,
+0xFF6C8D34,
+0xFF6B8E32,
+0xFF748D31,
+0xFF7E953A,
+0xFF799639,
+0xFF768834,
+0xFF958A4C,
+0xFF4B1700,
+0xFF932E24,
+0xFF9F2124,
+0xFF971714,
+0xFF82100F,
+0xFF7C2B34,
+0xFF402C4F,
+0xFF1F64AF,
+0xFF0E7AD5,
+0xFF004FAC,
+0xFF0050AC,
+0xFF0559B3,
+0xFF1054A9,
+0xFF21478E,
+0xFF312F5E,
+0xFF531927,
+0xFF5F1418,
+0xFF470E21,
+0xFF3B254B,
+0xFF7794CC,
+0xFF508ACA,
+0xFF5292CF,
+0xFF4E90CC,
+0xFF4C91CC,
+0xFF4C91CA,
+0xFF4C91CA,
+0xFF4C91CA,
+0xFF4C91CC,
+0xFF4C91CC,
+0xFF4C91CC,
+0xFF4C91CC,
+0xFF4C91CC,
+0xFF4C91CC,
+0xFF4C91CC,
+0xFF4C91CC,
+0xFF4C91CC,
+0xFF4C91CC,
+0xFF4C91CC,
+0xFF4C91CC,
+0xFF4D92CD,
+0xFF4C91CC,
+0xFF4C91CC,
+0xFF4C91CC,
+0xFF4C91CC,
+0xFF4C91CC,
+0xFF4C91CC,
+0xFF4C91CC,
+0xFF4C91CC,
+0xFF4C91CC,
+0xFF4C91CC,
+0xFF4C91CC,
+0xFF4C91CC,
+0xFF4C91CC,
+0xFF4B90CB,
+0xFF4B90CB,
+0xFF4B90CB,
+0xFF4B90CB,
+0xFF4C91CC,
+0xFF4C91CC,
+0xFF4C91CC,
+0xFF4C91CC,
+0xFF4C91CC,
+0xFF4C91CC,
+0xFF4C91CC,
+0xFF4C91CC,
+0xFF4C91CC,
+0xFF4C91CC,
+0xFF4C91CC,
+0xFF4C91CC,
+0xFF4C91CC,
+0xFF4C91CC,
+0xFF4E90CC,
+0xFF4E90CC,
+0xFF4E90CC,
+0xFF4E90CC,
+0xFF4B90CB,
+0xFF4B90CB,
+0xFF4B90CB,
+0xFF4B90CB,
+0xFF4B90CB,
+0xFF4B90CB,
+0xFF4B90CB,
+0xFF4B90CB,
+0xFF4B90CB,
+0xFF4A8FCA,
+0xFF4A8FCA,
+0xFF4A8FCA,
+0xFF498DCA,
+0xFF498DCA,
+0xFF488CC9,
+0xFF488CC9,
+0xFF4A8CC9,
+0xFF4A8CC9,
+0xFF4A8CC9,
+0xFF4A8CC9,
+0xFF498BC8,
+0xFF498BC8,
+0xFF498BC8,
+0xFF498BC8,
+0xFF498BC8,
+0xFF498BC8,
+0xFF498BC8,
+0xFF488AC7,
+0xFF488AC7,
+0xFF488AC7,
+0xFF4989C7,
+0xFF4989C7,
+0xFF4888C6,
+0xFF4888C6,
+0xFF4888C6,
+0xFF4888C6,
+0xFF4686C4,
+0xFF4686C4,
+0xFF4686C6,
+0xFF4686C6,
+0xFF4885C6,
+0xFF4784C5,
+0xFF4784C5,
+0xFF4784C5,
+0xFF4585C5,
+0xFF4484C4,
+0xFF4383C3,
+0xFF4383C3,
+0xFF4282C2,
+0xFF4282C2,
+0xFF4380C1,
+0xFF4380C1,
+0xFF4380C1,
+0xFF427FC0,
+0xFF427FC2,
+0xFF427FC2,
+0xFF427FC2,
+0xFF427FC2,
+0xFF417EC1,
+0xFF417EC1,
+0xFF3F74B8,
+0xFF3F74B6,
+0xFF3E75B6,
+0xFF3F76B7,
+0xFF4077B8,
+0xFF3E78B8,
+0xFF3F78BB,
+0xFF3F78BB,
+0xFF4278BE,
+0xFF4278BE,
+0xFF4278BE,
+0xFF4079BE,
+0xFF417ABD,
+0xFF417CBE,
+0xFF417DBC,
+0xFF417DBC,
+0xFF417EBD,
+0xFF427FBE,
+0xFF427FBE,
+0xFF4380BF,
+0xFF4380BF,
+0xFF4380BF,
+0xFF4380BF,
+0xFF4481C0,
+0xFF4582C1,
+0xFF4582C1,
+0xFF4582C1,
+0xFF4683C2,
+0xFF4683C2,
+0xFF4683C2,
+0xFF4784C3,
+0xFF4885C4,
+0xFF4784C3,
+0xFF4784C3,
+0xFF4885C4,
+0xFF4885C4,
+0xFF4885C6,
+0xFF4885C6,
+0xFF4885C6,
+0xFF4986C7,
+0xFF4986C7,
+0xFF4A87C8,
+0xFF4888C6,
+0xFF4888C6,
+0xFF4989C7,
+0xFF4989C7,
+0xFF4A8AC8,
+0xFF4A8AC8,
+0xFF4989C7,
+0xFF4989C7,
+0xFF4989C7,
+0xFF4989C7,
+0xFF4989C7,
+0xFF4A8AC8,
+0xFF4A8AC8,
+0xFF4A8AC8,
+0xFF4A8AC8,
+0xFF4A8AC8,
+0xFF4A8AC8,
+0xFF4A8AC8,
+0xFF4C89C8,
+0xFF4C89C8,
+0xFF4C89C8,
+0xFF4D8AC9,
+0xFF4A8AC7,
+0xFF4A8AC7,
+0xFF4A8AC7,
+0xFF4A8AC7,
+0xFF4B8BC8,
+0xFF4B8BC8,
+0xFF4B8BC8,
+0xFF4B8BC8,
+0xFF4B8BC8,
+0xFF4B8BC8,
+0xFF4B8BC8,
+0xFF4B8BC8,
+0xFF4B8BC8,
+0xFF4B8BC8,
+0xFF4B8BC8,
+0xFF4B8BC8,
+0xFF4C8CCA,
+0xFF4B8BC9,
+0xFF4B8BC9,
+0xFF4C8CCA,
+0xFF4C8CCA,
+0xFF4B8BC9,
+0xFF4B8BC9,
+0xFF4C8CCA,
+0xFF4A8CC9,
+0xFF4A8CC9,
+0xFF4B8DCA,
+0xFF4B8DCA,
+0xFF4B8DCA,
+0xFF4B8DCA,
+0xFF4B8DCA,
+0xFF4B8DCA,
+0xFF4B8DC9,
+0xFF4B8DC9,
+0xFF4B8DC9,
+0xFF4B8DC9,
+0xFF4B8DC9,
+0xFF4B8DC9,
+0xFF4B8DC9,
+0xFF4B8DC9,
+0xFF4A8CC8,
+0xFF4B8DC9,
+0xFF4B8DC9,
+0xFF4B8DC9,
+0xFF4B8DC9,
+0xFF4B8DC9,
+0xFF4B8DC9,
+0xFF4B8DC9,
+0xFF498EC9,
+0xFF498EC9,
+0xFF498EC9,
+0xFF498EC9,
+0xFF4A8FCA,
+0xFF4A8FCA,
+0xFF4A8FCA,
+0xFF4A8FCA,
+0xFF4A8FCA,
+0xFF4A8FCA,
+0xFF4A8FCA,
+0xFF4A8FCA,
+0xFF4A8FCA,
+0xFF4A8FCA,
+0xFF4A8FCA,
+0xFF4A8FCA,
+0xFF4A8FCA,
+0xFF4B90CB,
+0xFF4B90CB,
+0xFF4B90CB,
+0xFF4B90CB,
+0xFF4A8FCA,
+0xFF4B90CB,
+0xFF4B90CB,
+0xFF4B90CB,
+0xFF4B90CB,
+0xFF4B90CB,
+0xFF4B90CB,
+0xFF4B90CB,
+0xFF4B90CB,
+0xFF4B90CB,
+0xFF4B90C9,
+0xFF4B92C8,
+0xFF4B92CA,
+0xFF4A92CC,
+0xFF4893CD,
+0xFF4793CF,
+0xFF4793CF,
+0xFF4893CD,
+0xFF4C91CC,
+0xFF5592C9,
+0xFF528EC2,
+0xFF4E8CBF,
+0xFF6BAADD,
+0xFF4B8DBF,
+0xFF5295C9,
+0xFF4A8BC1,
+0xFF508EC7,
+0xFF659DD8,
+0xFF74AFE7,
+0xFF4D8CBF,
+0xFF5092C4,
+0xFF4F8DC8,
+0xFF4A8AC7,
+0xFF4F92C9,
+0xFF4C93C9,
+0xFF4994CB,
+0xFF4491C9,
+0xFF4B93CD,
+0xFF5286AE,
+0xFF192227,
+0xFFA49B7E,
+0xFFE9E9AD,
+0xFFB3BA6A,
+0xFF7C8532,
+0xFF798C33,
+0xFF6F8D33,
+0xFF73963C,
+0xFF718D38,
+0xFF748E37,
+0xFF78953B,
+0xFF8A9546,
+0xFFC2A86F,
+0xFF692403,
+0xFF96241A,
+0xFF990E11,
+0xFF9C1210,
+0xFF7F0E12,
+0xFF602333,
+0xFF3F416A,
+0xFF2F7BC7,
+0xFF0066C1,
+0xFF0053B0,
+0xFF0058B2,
+0xFF075CB6,
+0xFF0652A8,
+0xFF114EA1,
+0xFF2E4885,
+0xFF3B1D35,
+0xFF400B13,
+0xFF3C0F23,
+0xFF231435,
+0xFF3B5A90,
+0xFF5B97D5,
+0xFF4D8FCC,
+0xFF4B90CB,
+0xFF4C91CA,
+0xFF4C91CA,
+0xFF4C91CA,
+0xFF4C91CA,
+0xFF4C91CC,
+0xFF4C91CC,
+0xFF4C91CC,
+0xFF4C91CC,
+0xFF4D92CD,
+0xFF4D92CD,
+0xFF4D92CD,
+0xFF4D92CD,
+0xFF4D92CD,
+0xFF4C91CC,
+0xFF4C91CC,
+0xFF4C91CC,
+0xFF4D92CD,
+0xFF4D92CD,
+0xFF4C91CC,
+0xFF4C91CC,
+0xFF4D92CD,
+0xFF4D92CD,
+0xFF4D92CD,
+0xFF4C91CC,
+0xFF4C91CC,
+0xFF4C91CC,
+0xFF4D92CD,
+0xFF4D92CD,
+0xFF4C91CC,
+0xFF4C91CC,
+0xFF4C91CC,
+0xFF4C91CC,
+0xFF4C91CC,
+0xFF4C91CC,
+0xFF4C91CC,
+0xFF4C91CC,
+0xFF4C91CC,
+0xFF4C91CC,
+0xFF4C91CC,
+0xFF4C91CC,
+0xFF4C91CC,
+0xFF4C91CC,
+0xFF4C91CC,
+0xFF4C91CC,
+0xFF4C91CC,
+0xFF4C91CC,
+0xFF4C91CC,
+0xFF4D92CD,
+0xFF4E90CC,
+0xFF4E90CC,
+0xFF4E90CC,
+0xFF4E90CC,
+0xFF4C91CC,
+0xFF4C91CC,
+0xFF4C91CC,
+0xFF4C91CC,
+0xFF4B90CB,
+0xFF4B90CB,
+0xFF4B90CB,
+0xFF4B90CB,
+0xFF4B90CB,
+0xFF4B90CB,
+0xFF4B90CB,
+0xFF4B90CB,
+0xFF4B8FCC,
+0xFF4A8ECB,
+0xFF4A8ECB,
+0xFF4A8ECB,
+0xFF4B8DCA,
+0xFF4B8DCA,
+0xFF4C8ECB,
+0xFF4C8ECB,
+0xFF4A8CC9,
+0xFF4A8CC9,
+0xFF4A8CC9,
+0xFF4A8CC9,
+0xFF4A8CC9,
+0xFF498BC8,
+0xFF498BC8,
+0xFF498BC8,
+0xFF498BC8,
+0xFF498BC8,
+0xFF4A8AC8,
+0xFF4989C7,
+0xFF4989C7,
+0xFF4989C7,
+0xFF4989C7,
+0xFF4888C6,
+0xFF4888C6,
+0xFF4888C6,
+0xFF4888C8,
+0xFF4888C8,
+0xFF4986C7,
+0xFF4986C7,
+0xFF4986C7,
+0xFF4986C7,
+0xFF4585C5,
+0xFF4585C5,
+0xFF4484C4,
+0xFF4484C4,
+0xFF4383C3,
+0xFF4383C3,
+0xFF4481C2,
+0xFF4481C2,
+0xFF4481C2,
+0xFF4380C1,
+0xFF4380C3,
+0xFF427FC2,
+0xFF427FC2,
+0xFF427FC2,
+0xFF427FC2,
+0xFF417EC1,
+0xFF4176B8,
+0xFF4176B8,
+0xFF4176B8,
+0xFF4077B7,
+0xFF4077B7,
+0xFF4178B8,
+0xFF3F79B9,
+0xFF3F78BB,
+0xFF417ABF,
+0xFF417ABF,
+0xFF417ABF,
+0xFF427BC0,
+0xFF437CBF,
+0xFF427DBF,
+0xFF437FBE,
+0xFF417EBD,
+0xFF4380BF,
+0xFF4380BF,
+0xFF4380BF,
+0xFF4380BF,
+0xFF4380BF,
+0xFF4481C0,
+0xFF4481C0,
+0xFF4582C1,
+0xFF4582C1,
+0xFF4683C2,
+0xFF4683C2,
+0xFF4683C2,
+0xFF4683C2,
+0xFF4683C2,
+0xFF4784C3,
+0xFF4885C4,
+0xFF4885C4,
+0xFF4885C4,
+0xFF4986C5,
+0xFF4986C5,
+0xFF4986C5,
+0xFF4986C5,
+0xFF4888C6,
+0xFF4888C6,
+0xFF4888C6,
+0xFF4888C6,
+0xFF4888C6,
+0xFF4989C7,
+0xFF4989C7,
+0xFF4989C7,
+0xFF4A8AC8,
+0xFF4A8AC8,
+0xFF4A8AC8,
+0xFF4A8AC8,
+0xFF4A8AC8,
+0xFF4A8AC8,
+0xFF4A8AC8,
+0xFF4B8BC9,
+0xFF4B8BC9,
+0xFF4B8BC9,
+0xFF4B8BC9,
+0xFF4B8BC9,
+0xFF4D8AC9,
+0xFF4D8AC9,
+0xFF4D8AC9,
+0xFF4D8AC9,
+0xFF4D8AC9,
+0xFF4D8AC9,
+0xFF4C8CC9,
+0xFF4C8CC9,
+0xFF4C8CC9,
+0xFF4C8CC9,
+0xFF4C8CC9,
+0xFF4C8CC9,
+0xFF4C8CC9,
+0xFF4C8CC9,
+0xFF4C8CC9,
+0xFF4C8CC9,
+0xFF4C8CC9,
+0xFF4C8CC9,
+0xFF4C8CC9,
+0xFF4D8DCA,
+0xFF4D8DCA,
+0xFF4D8DCA,
+0xFF4D8DCA,
+0xFF4C8CC9,
+0xFF4C8CC9,
+0xFF4D8DCA,
+0xFF4D8DCA,
+0xFF4C8CC9,
+0xFF4B8DC9,
+0xFF4C8ECA,
+0xFF4B8DC9,
+0xFF4B8DC9,
+0xFF4A8FCA,
+0xFF4A8FCA,
+0xFF4A8FCA,
+0xFF4A8FCA,
+0xFF4A8FCA,
+0xFF4A8FCA,
+0xFF4C8ECA,
+0xFF4C8ECA,
+0xFF4C8ECA,
+0xFF4C8ECA,
+0xFF4C8ECA,
+0xFF4C8ECA,
+0xFF4C8ECA,
+0xFF4C8ECA,
+0xFF4A8FCA,
+0xFF4A8FCA,
+0xFF4A8FCA,
+0xFF4A8FCA,
+0xFF4B90CB,
+0xFF4B90CB,
+0xFF4B90CB,
+0xFF4B90CB,
+0xFF4A8FCA,
+0xFF4A8FCA,
+0xFF4A8FCA,
+0xFF4A8FCA,
+0xFF4A8FCA,
+0xFF4A8FCA,
+0xFF4B90CB,
+0xFF4B90CB,
+0xFF4B90CB,
+0xFF4B90CB,
+0xFF4B90CB,
+0xFF4B90CB,
+0xFF4B90CB,
+0xFF4B90CB,
+0xFF4B90CB,
+0xFF4B90CB,
+0xFF4B90CB,
+0xFF4C91CC,
+0xFF4C91CC,
+0xFF4C91CC,
+0xFF4C91CC,
+0xFF4C91CC,
+0xFF4C91CC,
+0xFF4C91CC,
+0xFF4C91CC,
+0xFF4C91CC,
+0xFF4C91CC,
+0xFF4C91CC,
+0xFF4C91CC,
+0xFF4C91CC,
+0xFF4C91CC,
+0xFF4C91CA,
+0xFF4E91C8,
+0xFF4C91C8,
+0xFF4B91CC,
+0xFF4A92CD,
+0xFF4893CD,
+0xFF4893CD,
+0xFF4793CD,
+0xFF4893CA,
+0xFF4A8EBF,
+0xFF5694C3,
+0xFF4D8AB9,
+0xFF72ACDE,
+0xFF548CBF,
+0xFF518ABF,
+0xFF5190C6,
+0xFF72B3EB,
+0xFF66A1DB,
+0xFF4B88BF,
+0xFF5395C7,
+0xFF4D90C4,
+0xFF4E8ECB,
+0xFF5494D1,
+0xFF4A8DC4,
+0xFF4C92C6,
+0xFF488FC3,
+0xFF5097CB,
+0xFF4D94CC,
+0xFF6396C3,
+0xFF2F3A4E,
+0xFF6F695D,
+0xFFE7E9B7,
+0xFFBCC479,
+0xFF768530,
+0xFF788D32,
+0xFF769035,
+0xFF79973F,
+0xFF739340,
+0xFF748F3E,
+0xFF839A42,
+0xFFC4C172,
+0xFFB98A52,
+0xFF741E00,
+0xFF8C1205,
+0xFF990908,
+0xFFA5090A,
+0xFF9A2430,
+0xFF573452,
+0xFF4B6AA0,
+0xFF1865B7,
+0xFF005ABB,
+0xFF005BBB,
+0xFF0E6DC9,
+0xFF0258AD,
+0xFF004896,
+0xFF1655A2,
+0xFF083473,
+0xFF0F224A,
+0xFF566181,
+0xFF7C94BA,
+0xFF7399C6,
+0xFF5993C5,
+0xFF4D92C9,
+0xFF4992C9,
+0xFF4F97D1,
+0xFF4C93CB,
+0xFF4D92CB,
+0xFF4D92CB,
+0xFF4D92CB,
+0xFF4D92CB,
+0xFF4D92CB,
+0xFF4D92CB,
+0xFF4D92CB,
+0xFF4D92CB,
+0xFF4D92CB,
+0xFF4D92CB,
+0xFF4D92CB,
+0xFF4D92CB,
+0xFF4D92CB,
+0xFF4D92CB,
+0xFF4D92CB,
+0xFF4D92CB,
+0xFF4D92CB,
+0xFF4C91CA,
+0xFF4D92CB,
+0xFF4D92CB,
+0xFF4D92CB,
+0xFF4D92CB,
+0xFF4C91CA,
+0xFF4D92CB,
+0xFF4D92CB,
+0xFF4D92CB,
+0xFF4D92CB,
+0xFF4D92CB,
+0xFF4D92CB,
+0xFF4D92CB,
+0xFF4D92CB,
+0xFF4D92CB,
+0xFF4D92CB,
+0xFF4D92CB,
+0xFF4D92CB,
+0xFF4D92CB,
+0xFF4D92CB,
+0xFF4D92CB,
+0xFF4D92CB,
+0xFF4D92CB,
+0xFF4D92CB,
+0xFF4D92CB,
+0xFF4C91CA,
+0xFF4C91CA,
+0xFF4D92CB,
+0xFF4D92CB,
+0xFF4D92CB,
+0xFF4F91CB,
+0xFF4F91CB,
+0xFF4E90CA,
+0xFF4E90CA,
+0xFF4E90CA,
+0xFF4E90CA,
+0xFF4E90CA,
+0xFF4E90CA,
+0xFF4C91CA,
+0xFF4C91CA,
+0xFF4C91CC,
+0xFF4C91CC,
+0xFF4C91CC,
+0xFF4C91CC,
+0xFF4C91CC,
+0xFF4B90CB,
+0xFF4C91CC,
+0xFF4B90CB,
+0xFF4B90CB,
+0xFF4B90CB,
+0xFF4A8FCA,
+0xFF4A8FCA,
+0xFF4B90CB,
+0xFF4B90CB,
+0xFF498EC9,
+0xFF498EC9,
+0xFF498DCA,
+0xFF498DCA,
+0xFF488CC9,
+0xFF488CC9,
+0xFF488CC9,
+0xFF488CC9,
+0xFF498BC8,
+0xFF498BC8,
+0xFF4A8CC9,
+0xFF498BC8,
+0xFF498BC8,
+0xFF498BC8,
+0xFF4A8AC8,
+0xFF4A8AC8,
+0xFF4989C7,
+0xFF4989C7,
+0xFF4989C7,
+0xFF4989C7,
+0xFF4888C6,
+0xFF4787C5,
+0xFF4787C5,
+0xFF4787C5,
+0xFF4885C6,
+0xFF4885C6,
+0xFF4784C5,
+0xFF4784C5,
+0xFF4784C5,
+0xFF4784C5,
+0xFF4683C4,
+0xFF4582C3,
+0xFF4683C4,
+0xFF4582C3,
+0xFF4481C2,
+0xFF4380C1,
+0xFF4380C1,
+0xFF427FC0,
+0xFF427FC0,
+0xFF427FC0,
+0xFF4479BB,
+0xFF447ABA,
+0xFF447ABA,
+0xFF447ABA,
+0xFF447ABA,
+0xFF437ABA,
+0xFF437ABB,
+0xFF417BBB,
+0xFF427BBE,
+0xFF427BC0,
+0xFF427BC0,
+0xFF417CC0,
+0xFF437EC0,
+0xFF437EC0,
+0xFF4380BF,
+0xFF427FBE,
+0xFF4481C0,
+0xFF4481C0,
+0xFF4481C0,
+0xFF4481C0,
+0xFF4481C0,
+0xFF4481C0,
+0xFF4582C1,
+0xFF4683C2,
+0xFF4683C2,
+0xFF4683C2,
+0xFF4683C2,
+0xFF4683C2,
+0xFF4683C2,
+0xFF4683C2,
+0xFF4784C3,
+0xFF4885C4,
+0xFF4885C4,
+0xFF4986C5,
+0xFF4A87C6,
+0xFF4A87C6,
+0xFF4A87C6,
+0xFF4A87C6,
+0xFF4888C6,
+0xFF4989C7,
+0xFF4A8AC8,
+0xFF4A8AC8,
+0xFF4989C7,
+0xFF4989C7,
+0xFF4989C7,
+0xFF4989C7,
+0xFF4989C7,
+0xFF4989C7,
+0xFF4A8AC8,
+0xFF4A8AC8,
+0xFF4B8BC9,
+0xFF4B8BC9,
+0xFF4B8BC9,
+0xFF4B8BC9,
+0xFF4B8BC9,
+0xFF4B8BC9,
+0xFF4B8BC9,
+0xFF4B8BC9,
+0xFF4E8BCA,
+0xFF4E8BCA,
+0xFF4E8BCA,
+0xFF4E8BCA,
+0xFF4E8BCA,
+0xFF4E8CC9,
+0xFF4C8CC9,
+0xFF4C8CC9,
+0xFF4D8DCA,
+0xFF4D8DCA,
+0xFF4D8DCA,
+0xFF4D8DCA,
+0xFF4D8DCA,
+0xFF4D8DCA,
+0xFF4D8DCA,
+0xFF4D8DCA,
+0xFF4D8DCA,
+0xFF4D8DCA,
+0xFF4D8DCA,
+0xFF4E8ECB,
+0xFF4E8ECB,
+0xFF4E8ECB,
+0xFF4E8ECB,
+0xFF4D8DCA,
+0xFF4D8DCA,
+0xFF4E8ECB,
+0xFF4E8ECB,
+0xFF4D8DCA,
+0xFF4C8ECA,
+0xFF4D8FCB,
+0xFF4C8ECA,
+0xFF4C8ECA,
+0xFF4A8FCA,
+0xFF4A8FCA,
+0xFF4A8FCA,
+0xFF4A8FCA,
+0xFF4A8FCA,
+0xFF4A8FCA,
+0xFF4C8ECA,
+0xFF4C8ECA,
+0xFF4C8ECA,
+0xFF4D8FCB,
+0xFF4D8FCB,
+0xFF4D8FCB,
+0xFF4D8FCB,
+0xFF4D8FCB,
+0xFF4B90CB,
+0xFF4B90CB,
+0xFF4B90CB,
+0xFF4B90CB,
+0xFF4C91CC,
+0xFF4C91CC,
+0xFF4C91CC,
+0xFF4C91CC,
+0xFF4C91CC,
+0xFF4C91CC,
+0xFF4C91CC,
+0xFF4C91CC,
+0xFF4C91CC,
+0xFF4C91CC,
+0xFF4C91CC,
+0xFF4C91CC,
+0xFF4C91CC,
+0xFF4C91CC,
+0xFF4C91CC,
+0xFF4C91CC,
+0xFF4C91CC,
+0xFF4C91CC,
+0xFF4C91CC,
+0xFF4C91CC,
+0xFF4C91CC,
+0xFF4C91CC,
+0xFF4D92CD,
+0xFF4D92CD,
+0xFF4C91CC,
+0xFF4C91CC,
+0xFF4C91CC,
+0xFF4D92CD,
+0xFF4C91CC,
+0xFF4C91CC,
+0xFF4C91CC,
+0xFF4C91CC,
+0xFF4C91CC,
+0xFF4D92CD,
+0xFF4D92CD,
+0xFF4D92CB,
+0xFF4F90C8,
+0xFF4E91C8,
+0xFF4C91CA,
+0xFF4B91CC,
+0xFF4A92CD,
+0xFF4994CE,
+0xFF4994CD,
+0xFF4995C9,
+0xFF5298C9,
+0xFF4E8EBC,
+0xFF5892C0,
+0xFF77ADDC,
+0xFF578BBD,
+0xFF6BA2D8,
+0xFF7AB9EF,
+0xFF5192CA,
+0xFF5391CA,
+0xFF5796CC,
+0xFF4E91C5,
+0xFF4E91C6,
+0xFF5292CF,
+0xFF4D8DCA,
+0xFF5192CA,
+0xFF4E91C6,
+0xFF4E92C3,
+0xFF4C8FC3,
+0xFF4F92C9,
+0xFF5F92C1,
+0xFF4F5E7D,
+0xFF4B4B4B,
+0xFFDADDB2,
+0xFFD5DC96,
+0xFF768532,
+0xFF81963B,
+0xFF7C973A,
+0xFF6D8B31,
+0xFF72923F,
+0xFF6E8B39,
+0xFF778B32,
+0xFFD7CA7C,
+0xFFB16B37,
+0xFF912204,
+0xFFA41A0D,
+0xFFB81E1C,
+0xFFC32323,
+0xFFA63A4A,
+0xFF423F6C,
+0xFF316CB0,
+0xFF1363B8,
+0xFF0B66C3,
+0xFF0C6BC7,
+0xFF0054AC,
+0xFF004290,
+0xFF0B4F98,
+0xFF00387F,
+0xFF336DAC,
+0xFF6A9CCD,
+0xFF6396C3,
+0xFF5692C4,
+0xFF5092C4,
+0xFF5295C9,
+0xFF4E95C9,
+0xFF4D96CD,
+0xFF4A92CC,
+0xFF4F94CD,
+0xFF4F94CD,
+0xFF4F94CD,
+0xFF4F94CD,
+0xFF4F94CD,
+0xFF4F94CD,
+0xFF4F94CD,
+0xFF4F94CD,
+0xFF4F94CD,
+0xFF4F94CD,
+0xFF4F94CD,
+0xFF4F94CD,
+0xFF4F94CD,
+0xFF4E93CC,
+0xFF4E93CC,
+0xFF4E93CC,
+0xFF4E93CC,
+0xFF4E93CC,
+0xFF4E93CC,
+0xFF4E93CC,
+0xFF4E93CC,
+0xFF4F94CD,
+0xFF4E93CC,
+0xFF4E93CC,
+0xFF4E93CC,
+0xFF4E93CC,
+0xFF4E93CC,
+0xFF4E93CC,
+0xFF4E93CC,
+0xFF4E93CC,
+0xFF4E93CC,
+0xFF4D92CB,
+0xFF4D92CB,
+0xFF4D92CB,
+0xFF4E93CC,
+0xFF4E93CC,
+0xFF4E93CC,
+0xFF4E93CC,
+0xFF4E93CC,
+0xFF4E93CC,
+0xFF4D92CB,
+0xFF4D92CB,
+0xFF4D92CB,
+0xFF4D92CB,
+0xFF4D92CB,
+0xFF4D92CB,
+0xFF4E93CC,
+0xFF4E93CC,
+0xFF4F91CB,
+0xFF4F91CB,
+0xFF4F91CB,
+0xFF4F91CB,
+0xFF4F91CB,
+0xFF4F91CB,
+0xFF4F91CB,
+0xFF4F91CB,
+0xFF4E93CC,
+0xFF4E93CC,
+0xFF4D92CD,
+0xFF4D92CD,
+0xFF4D92CD,
+0xFF4C91CC,
+0xFF4C91CC,
+0xFF4C91CC,
+0xFF4C91CC,
+0xFF4C91CC,
+0xFF4B90CB,
+0xFF4B90CB,
+0xFF4A8FCA,
+0xFF4A8FCA,
+0xFF4B90CB,
+0xFF4B90CB,
+0xFF4A8FCA,
+0xFF4A8FCA,
+0xFF4A8ECB,
+0xFF498DCA,
+0xFF498DCA,
+0xFF488CC9,
+0xFF488CC9,
+0xFF488CC9,
+0xFF4A8CC9,
+0xFF4A8CC9,
+0xFF4A8CC9,
+0xFF4A8CC9,
+0xFF4A8CC9,
+0xFF4A8CC9,
+0xFF4A8AC8,
+0xFF4A8AC8,
+0xFF4989C7,
+0xFF4989C7,
+0xFF4989C7,
+0xFF4989C7,
+0xFF4787C5,
+0xFF4787C5,
+0xFF4787C5,
+0xFF4787C5,
+0xFF4986C7,
+0xFF4986C7,
+0xFF4885C6,
+0xFF4885C6,
+0xFF4885C6,
+0xFF4885C6,
+0xFF4784C5,
+0xFF4784C5,
+0xFF4784C5,
+0xFF4683C4,
+0xFF4481C2,
+0xFF4481C2,
+0xFF4380C1,
+0xFF4380C1,
+0xFF427FC0,
+0xFF427FC0,
+0xFF4C7FC0,
+0xFF4A7DBC,
+0xFF497CBB,
+0xFF487BBA,
+0xFF477AB9,
+0xFF4379B7,
+0xFF4379B9,
+0xFF437ABB,
+0xFF437CBF,
+0xFF437CBF,
+0xFF427DC1,
+0xFF427DC1,
+0xFF437EC0,
+0xFF4380C1,
+0xFF4380BF,
+0xFF4481C0,
+0xFF4481C0,
+0xFF4481C0,
+0xFF4481C0,
+0xFF4582C1,
+0xFF4582C1,
+0xFF4683C2,
+0xFF4683C2,
+0xFF4683C2,
+0xFF4683C2,
+0xFF4683C2,
+0xFF4784C3,
+0xFF4784C3,
+0xFF4784C3,
+0xFF4885C4,
+0xFF4885C4,
+0xFF4986C5,
+0xFF4885C4,
+0xFF4A87C6,
+0xFF4B88C7,
+0xFF4A87C6,
+0xFF4B88C7,
+0xFF4B88C7,
+0xFF4A8AC7,
+0xFF4A8AC7,
+0xFF4888C5,
+0xFF4989C6,
+0xFF4A8AC7,
+0xFF4989C6,
+0xFF4989C6,
+0xFF4A8AC7,
+0xFF4A8AC7,
+0xFF4A8AC7,
+0xFF4A8AC7,
+0xFF4A8AC7,
+0xFF4A8AC7,
+0xFF4B8BC8,
+0xFF4C8CC9,
+0xFF4C8CC9,
+0xFF4C8CC9,
+0xFF4C8CC9,
+0xFF4C8CC9,
+0xFF4D8DCA,
+0xFF4D8DCA,
+0xFF4E8ECB,
+0xFF4E8ECB,
+0xFF4D8DCA,
+0xFF4C8CC9,
+0xFF4B8BC8,
+0xFF4C8CC9,
+0xFF4D8EC8,
+0xFF4D8EC8,
+0xFF4D8EC8,
+0xFF4D8EC8,
+0xFF4D8EC8,
+0xFF4D8EC8,
+0xFF4E8FC9,
+0xFF4D8EC8,
+0xFF4D8EC8,
+0xFF4D8EC8,
+0xFF4D8EC8,
+0xFF4C8EC8,
+0xFF4C8EC8,
+0xFF4C8EC8,
+0xFF4C8EC8,
+0xFF4D8EC8,
+0xFF4D8EC8,
+0xFF4D8FC9,
+0xFF4D8FC9,
+0xFF4D8FC9,
+0xFF4D8FC9,
+0xFF4D8FC9,
+0xFF4C8EC8,
+0xFF4B90C9,
+0xFF4B90C9,
+0xFF4C91CA,
+0xFF4C91CA,
+0xFF4C91CA,
+0xFF4C91CA,
+0xFF4B92CA,
+0xFF4B92CA,
+0xFF4B90C9,
+0xFF4C91CA,
+0xFF4C91CA,
+0xFF4C91CA,
+0xFF4C91CA,
+0xFF4C91CA,
+0xFF4C91CA,
+0xFF4C91CA,
+0xFF4C91CA,
+0xFF4C91CA,
+0xFF4C91CA,
+0xFF4C91CA,
+0xFF4C91CA,
+0xFF4C91CA,
+0xFF4C91CA,
+0xFF4C91CA,
+0xFF4C91CA,
+0xFF4C91CA,
+0xFF4C91CA,
+0xFF4C91CA,
+0xFF4C91CA,
+0xFF4C91CA,
+0xFF4C91CA,
+0xFF4D92CB,
+0xFF4C91CA,
+0xFF4D92CB,
+0xFF4D92CB,
+0xFF4D92CB,
+0xFF4D92CB,
+0xFF4D92CB,
+0xFF4D92CB,
+0xFF4D92CB,
+0xFF4D92CB,
+0xFF4D92CB,
+0xFF4D92CB,
+0xFF4D92CB,
+0xFF4D92CB,
+0xFF4D92CB,
+0xFF4D92CB,
+0xFF4D92CB,
+0xFF4D92CB,
+0xFF4D92CB,
+0xFF4D92CB,
+0xFF4D92CB,
+0xFF4E93CC,
+0xFF4E93CC,
+0xFF4E93CC,
+0xFF4E93CC,
+0xFF5293CB,
+0xFF4F90C6,
+0xFF5495CD,
+0xFF4D92CB,
+0xFF4993D0,
+0xFF4994CE,
+0xFF5196CD,
+0xFF4D93C6,
+0xFF4B93C5,
+0xFF4D8FBF,
+0xFF79AFDB,
+0xFF6497C4,
+0xFF81B4E9,
+0xFF6BA4DB,
+0xFF5996CD,
+0xFF5899CF,
+0xFF5A9BD1,
+0xFF5A9DD2,
+0xFF579DD1,
+0xFF579AD1,
+0xFF5899D3,
+0xFF5C9AD5,
+0xFF5D9BD4,
+0xFF5A9BD1,
+0xFF5B9DCF,
+0xFF61A0D3,
+0xFF61A0D6,
+0xFF699BCE,
+0xFF7A91BA,
+0xFF48505B,
+0xFFE1E1BD,
+0xFFD6D795,
+0xFF869143,
+0xFF7C9037,
+0xFF718C2F,
+0xFF6F8E31,
+0xFF6B8933,
+0xFF68842F,
+0xFF647B21,
+0xFFD6C577,
+0xFFA54A1B,
+0xFFAF230A,
+0xFFC62218,
+0xFFCB2320,
+0xFFB82221,
+0xFF7E2B3F,
+0xFF385694,
+0xFF156BBE,
+0xFF0F65B8,
+0xFF0759AB,
+0xFF004DA0,
+0xFF00408E,
+0xFF00327A,
+0xFF0F4A8C,
+0xFF5F9FDD,
+0xFF5698D2,
+0xFF5294C6,
+0xFF5294C4,
+0xFF5294C6,
+0xFF5294C8,
+0xFF5293C9,
+0xFF5293CB,
+0xFF5193CD,
+0xFF5294D0,
+0xFF5193CD,
+0xFF5194CB,
+0xFF5194CB,
+0xFF5194CB,
+0xFF5194CB,
+0xFF5194CB,
+0xFF5194CB,
+0xFF5194CB,
+0xFF5194CB,
+0xFF5194CB,
+0xFF5193CD,
+0xFF5193CD,
+0xFF5193CD,
+0xFF5294CE,
+0xFF5294CE,
+0xFF5294CE,
+0xFF4F94CB,
+0xFF4F94CB,
+0xFF4F94CB,
+0xFF4F94CB,
+0xFF4F94CB,
+0xFF4F94CB,
+0xFF4F94CB,
+0xFF4F94CB,
+0xFF4F94CB,
+0xFF4F94CB,
+0xFF4F94CB,
+0xFF4F94CB,
+0xFF4F94CB,
+0xFF4F94CB,
+0xFF4F94CB,
+0xFF4F94CB,
+0xFF5193CD,
+0xFF5193CD,
+0xFF5193CD,
+0xFF5193CD,
+0xFF5193CD,
+0xFF5193CD,
+0xFF5193CD,
+0xFF5193CD,
+0xFF5193CD,
+0xFF5193CD,
+0xFF5193CD,
+0xFF5193CD,
+0xFF5193CD,
+0xFF5193CD,
+0xFF5092CC,
+0xFF5092CC,
+0xFF5194CB,
+0xFF5194CB,
+0xFF5194CB,
+0xFF5194CB,
+0xFF5194CB,
+0xFF5194CB,
+0xFF5193CD,
+0xFF5193CD,
+0xFF4E93CC,
+0xFF4E93CC,
+0xFF4E93CC,
+0xFF4E93CC,
+0xFF4E93CC,
+0xFF4D92CB,
+0xFF4D92CB,
+0xFF4D92CB,
+0xFF4C91CA,
+0xFF4C91CA,
+0xFF4C91CA,
+0xFF4C91CA,
+0xFF4C91CA,
+0xFF4C91CA,
+0xFF4C91CC,
+0xFF4C91CC,
+0xFF4C91CC,
+0xFF4B90CB,
+0xFF4B90CB,
+0xFF4B90CB,
+0xFF4A8FCA,
+0xFF4A8FCA,
+0xFF4A8FCA,
+0xFF498EC9,
+0xFF4B8DC9,
+0xFF4A8CC8,
+0xFF4A8CC8,
+0xFF4A8CC8,
+0xFF498BC7,
+0xFF498BC7,
+0xFF488AC6,
+0xFF488AC6,
+0xFF488AC7,
+0xFF488AC7,
+0xFF4989C7,
+0xFF4989C7,
+0xFF4989C7,
+0xFF4989C7,
+0xFF4888C6,
+0xFF4888C6,
+0xFF4787C5,
+0xFF4787C5,
+0xFF4787C5,
+0xFF4787C5,
+0xFF4686C4,
+0xFF4686C4,
+0xFF4585C3,
+0xFF4585C3,
+0xFF4585C5,
+0xFF4585C5,
+0xFF4484C4,
+0xFF4484C4,
+0xFF4383C3,
+0xFF4383C3,
+0xFF4282C2,
+0xFF4181C1,
+0xFF5183C2,
+0xFF4D81BD,
+0xFF4C7EBB,
+0xFF4D81BD,
+0xFF4D7FBC,
+0xFF497CBB,
+0xFF477AB9,
+0xFF447ABA,
+0xFF457CBD,
+0xFF437CBF,
+0xFF437EC2,
+0xFF437EC0,
+0xFF4380C1,
+0xFF4481C0,
+0xFF4481C0,
+0xFF4481C0,
+0xFF4582C1,
+0xFF4582C1,
+0xFF4582C1,
+0xFF4582C1,
+0xFF4683C2,
+0xFF4683C2,
+0xFF4784C3,
+0xFF4784C3,
+0xFF4784C3,
+0xFF4885C4,
+0xFF4885C4,
+0xFF4986C5,
+0xFF4986C5,
+0xFF4986C5,
+0xFF4986C5,
+0xFF4A87C6,
+0xFF4A87C6,
+0xFF4C89C8,
+0xFF4C89C8,
+0xFF4B88C7,
+0xFF4A87C6,
+0xFF4B89C6,
+0xFF4989C6,
+0xFF4989C6,
+0xFF4989C6,
+0xFF4A8AC7,
+0xFF4B8BC8,
+0xFF4A8AC7,
+0xFF4A8AC7,
+0xFF4B8BC8,
+0xFF4B8BC8,
+0xFF4B8BC8,
+0xFF4C8CC9,
+0xFF4C8CC9,
+0xFF4C8CC9,
+0xFF4C8CC9,
+0xFF4C8CC9,
+0xFF4C8CC9,
+0xFF4C8CC9,
+0xFF4C8CC9,
+0xFF4C8CC9,
+0xFF4D8DCA,
+0xFF4D8DCA,
+0xFF4D8DCA,
+0xFF4D8DCA,
+0xFF4D8DCA,
+0xFF4D8DCA,
+0xFF4D8DCA,
+0xFF4D8EC8,
+0xFF4D8EC8,
+0xFF4E8FC9,
+0xFF4E8FC9,
+0xFF4D8EC8,
+0xFF4D8EC8,
+0xFF4E8FC9,
+0xFF4E8FC9,
+0xFF4D8EC8,
+0xFF4D8EC8,
+0xFF4D8EC8,
+0xFF4C8EC8,
+0xFF4D8FC9,
+0xFF4D8FC9,
+0xFF4D8FC9,
+0xFF4D8FC9,
+0xFF4E8FC9,
+0xFF4D8FC9,
+0xFF4D8FC9,
+0xFF4E90CA,
+0xFF4E90CA,
+0xFF4E90CA,
+0xFF4D8FC9,
+0xFF4D8FC9,
+0xFF4B90C9,
+0xFF4B90C9,
+0xFF4C91CA,
+0xFF4C91CA,
+0xFF4C91CA,
+0xFF4C91CA,
+0xFF4B92CA,
+0xFF4B92CA,
+0xFF4C91CA,
+0xFF4C91CA,
+0xFF4C91CA,
+0xFF4C91CA,
+0xFF4C91CA,
+0xFF4C91CA,
+0xFF4C91CA,
+0xFF4C91CA,
+0xFF4C91CA,
+0xFF4C91CA,
+0xFF4C91CA,
+0xFF4C91CA,
+0xFF4C91CA,
+0xFF4C91CA,
+0xFF4C91CA,
+0xFF4C91CA,
+0xFF4D92CB,
+0xFF4D92CB,
+0xFF4C91CA,
+0xFF4C91CA,
+0xFF4C91CA,
+0xFF4D92CB,
+0xFF4D92CB,
+0xFF4D92CB,
+0xFF4D92CB,
+0xFF4D92CB,
+0xFF4E93CC,
+0xFF4E93CC,
+0xFF4D92CB,
+0xFF4D92CB,
+0xFF4D92CB,
+0xFF4E93CC,
+0xFF4E93CC,
+0xFF4E93CC,
+0xFF4E93CC,
+0xFF4E93CC,
+0xFF4E93CC,
+0xFF4E93CC,
+0xFF4E93CC,
+0xFF4E93CC,
+0xFF4E93CC,
+0xFF4E93CC,
+0xFF4E93CC,
+0xFF4E93CC,
+0xFF4E93CC,
+0xFF4E93CC,
+0xFF4E93CC,
+0xFF4E93CA,
+0xFF5093C8,
+0xFF5697CD,
+0xFF4F90C8,
+0xFF5193CD,
+0xFF4E96D1,
+0xFF4E96D0,
+0xFF4B8EC3,
+0xFF5193C5,
+0xFF5A99CC,
+0xFF4E8BBA,
+0xFFAEE2FF,
+0xFF77ABDA,
+0xFF558DC0,
+0xFF528EC4,
+0xFF5491C8,
+0xFF5192C8,
+0xFF4E94C8,
+0xFF4F95C9,
+0xFF4E93CA,
+0xFF4F92C9,
+0xFF5290C9,
+0xFF5492CB,
+0xFF5492CB,
+0xFF5492CB,
+0xFF5496CA,
+0xFF5190C5,
+0xFF5592C9,
+0xFF5A8DC2,
+0xFF7191C0,
+0xFF3E4D60,
+0xFFD4D3B4,
+0xFFCBC788,
+0xFF4C5709,
+0xFF71852E,
+0xFF6F892E,
+0xFF678428,
+0xFF69832A,
+0xFF6C842C,
+0xFF5E751B,
+0xFFB8A257,
+0xFFA3360D,
+0xFFC62712,
+0xFFCC1B11,
+0xFFBE1C19,
+0xFFA63235,
+0xFF562845,
+0xFF2E62AD,
+0xFF0764C1,
+0xFF0152A4,
+0xFF004290,
+0xFF044692,
+0xFF003179,
+0xFF467DC0,
+0xFF689FDF,
+0xFF518FCA,
+0xFF5194CB,
+0xFF4F95C9,
+0xFF4E96C8,
+0xFF4E95C9,
+0xFF4F94CB,
+0xFF5295CC,
+0xFF5394CE,
+0xFF5593CE,
+0xFF5394CE,
+0xFF5194CB,
+0xFF5194CB,
+0xFF5194CB,
+0xFF5194CB,
+0xFF5194CB,
+0xFF5194CB,
+0xFF5194CB,
+0xFF5194CB,
+0xFF5295CC,
+0xFF5295CC,
+0xFF5294CE,
+0xFF5294CE,
+0xFF5294CE,
+0xFF5294CE,
+0xFF5294CE,
+0xFF5294CE,
+0xFF4F94CB,
+0xFF4F94CB,
+0xFF4F94CB,
+0xFF4F94CB,
+0xFF4F94CB,
+0xFF4F94CB,
+0xFF4F94CB,
+0xFF4F94CB,
+0xFF4F94CB,
+0xFF4F94CB,
+0xFF4F94CB,
+0xFF4F94CB,
+0xFF4F94CB,
+0xFF4F94CB,
+0xFF4F94CB,
+0xFF4F94CB,
+0xFF5193CD,
+0xFF5193CD,
+0xFF5193CD,
+0xFF5193CD,
+0xFF5193CD,
+0xFF5193CD,
+0xFF5294CE,
+0xFF5294CE,
+0xFF5193CD,
+0xFF5193CD,
+0xFF5193CD,
+0xFF5193CD,
+0xFF5193CD,
+0xFF5193CD,
+0xFF5193CD,
+0xFF5193CD,
+0xFF5295CC,
+0xFF5295CC,
+0xFF5194CB,
+0xFF5194CB,
+0xFF5194CB,
+0xFF5194CB,
+0xFF5193CD,
+0xFF5193CD,
+0xFF4F94CD,
+0xFF4F94CD,
+0xFF4F94CD,
+0xFF4F94CD,
+0xFF4F94CD,
+0xFF4F94CD,
+0xFF4F94CD,
+0xFF4F94CD,
+0xFF4D92CB,
+0xFF4D92CB,
+0xFF4D92CB,
+0xFF4D92CB,
+0xFF4D92CB,
+0xFF4D92CB,
+0xFF4D92CD,
+0xFF4C91CC,
+0xFF4C91CC,
+0xFF4C91CC,
+0xFF4C91CC,
+0xFF4B90CB,
+0xFF4B90CB,
+0xFF4B90CB,
+0xFF4A8FCA,
+0xFF4A8FCA,
+0xFF4C8ECA,
+0xFF4B8DC9,
+0xFF4B8DC9,
+0xFF4B8DC9,
+0xFF4A8CC8,
+0xFF4A8CC8,
+0xFF498BC7,
+0xFF498BC7,
+0xFF498BC8,
+0xFF498BC8,
+0xFF4A8AC8,
+0xFF4A8AC8,
+0xFF4A8AC8,
+0xFF4A8AC8,
+0xFF4A8AC8,
+0xFF4A8AC8,
+0xFF4888C6,
+0xFF4888C6,
+0xFF4888C6,
+0xFF4787C5,
+0xFF4787C5,
+0xFF4686C4,
+0xFF4686C4,
+0xFF4686C4,
+0xFF4585C5,
+0xFF4585C5,
+0xFF4484C4,
+0xFF4484C4,
+0xFF4484C4,
+0xFF4484C4,
+0xFF4383C3,
+0xFF4383C3,
+0xFF5181BF,
+0xFF4C7EB9,
+0xFF4D7EB9,
+0xFF5183BE,
+0xFF5384BF,
+0xFF4F81BE,
+0xFF4A7EBA,
+0xFF477DBB,
+0xFF457CBD,
+0xFF437DBD,
+0xFF437EC0,
+0xFF4481C2,
+0xFF4481C2,
+0xFF4582C1,
+0xFF4682C1,
+0xFF4682C0,
+0xFF4683C2,
+0xFF4683C2,
+0xFF4683C2,
+0xFF4683C2,
+0xFF4784C3,
+0xFF4784C3,
+0xFF4885C4,
+0xFF4885C4,
+0xFF4986C5,
+0xFF4986C5,
+0xFF4A87C6,
+0xFF4A87C6,
+0xFF4A87C6,
+0xFF4A87C6,
+0xFF4B88C7,
+0xFF4B88C7,
+0xFF4A88C5,
+0xFF4B89C6,
+0xFF4B89C6,
+0xFF4B89C6,
+0xFF4C8AC7,
+0xFF4D8BC8,
+0xFF4E8CC9,
+0xFF4D8BC6,
+0xFF4C8AC5,
+0xFF4D8BC6,
+0xFF4C8DC7,
+0xFF4B8CC6,
+0xFF4C8CC9,
+0xFF4C8CC9,
+0xFF4C8CC9,
+0xFF4C8CC9,
+0xFF4F8DC8,
+0xFF4F8DC8,
+0xFF4F8DC8,
+0xFF508EC9,
+0xFF4F8DC8,
+0xFF4F8DC8,
+0xFF4D8EC8,
+0xFF4E8FC9,
+0xFF4E8FC9,
+0xFF4E8FC9,
+0xFF4E8FC9,
+0xFF4E8FC9,
+0xFF4E8FC9,
+0xFF4E8FC9,
+0xFF4F90CA,
+0xFF4F90CA,
+0xFF4E8FC9,
+0xFF4E8FC9,
+0xFF4F90CA,
+0xFF4F90CA,
+0xFF4E8FC9,
+0xFF4E8FC9,
+0xFF4E90CA,
+0xFF4E90CA,
+0xFF4E90CA,
+0xFF4E90CA,
+0xFF4E90CA,
+0xFF4E90CA,
+0xFF4E90CA,
+0xFF4C91CA,
+0xFF4C91CA,
+0xFF4C91CA,
+0xFF4E90CA,
+0xFF4E90CA,
+0xFF4E90CA,
+0xFF4C91CA,
+0xFF4C91CA,
+0xFF4C91CA,
+0xFF4C91CA,
+0xFF4D92CB,
+0xFF4C91CA,
+0xFF4C91CA,
+0xFF4C91CA,
+0xFF4C91CA,
+0xFF4C93CB,
+0xFF4B92CA,
+0xFF4B92CA,
+0xFF4B92CA,
+0xFF4D92CB,
+0xFF4D92CB,
+0xFF4D92CB,
+0xFF4D92CB,
+0xFF4D92CB,
+0xFF4D92CB,
+0xFF4D92CB,
+0xFF4D92CB,
+0xFF4D92CB,
+0xFF4D92CB,
+0xFF4D92CB,
+0xFF4D92CB,
+0xFF4D92CB,
+0xFF4D92CB,
+0xFF4D92CB,
+0xFF4D92CB,
+0xFF4E93CA,
+0xFF4E93CA,
+0xFF4E93CA,
+0xFF4D92C9,
+0xFF4E93CA,
+0xFF4E93CA,
+0xFF4E93CA,
+0xFF4E93CA,
+0xFF4E93CA,
+0xFF4E93CA,
+0xFF4E93CA,
+0xFF4E93CA,
+0xFF4E93CA,
+0xFF4E93CA,
+0xFF4E93CA,
+0xFF4F94CB,
+0xFF4E93CA,
+0xFF4E93CA,
+0xFF4E93CA,
+0xFF4E93CA,
+0xFF4E93CA,
+0xFF4F94CB,
+0xFF4F94CB,
+0xFF4F94CB,
+0xFF4E93CA,
+0xFF4F94CB,
+0xFF4F94CB,
+0xFF4F94CB,
+0xFF4F94CB,
+0xFF4F94CB,
+0xFF4F94CB,
+0xFF4F94CB,
+0xFF5396CB,
+0xFF4D90C5,
+0xFF4F94CD,
+0xFF4F94CD,
+0xFF5396CB,
+0xFF4E91C6,
+0xFF5698D2,
+0xFF5693CA,
+0xFF5587BA,
+0xFF306090,
+0xFF3870A1,
+0xFF538FC1,
+0xFF5593C2,
+0xFF5997C8,
+0xFF5493C9,
+0xFF4F92C9,
+0xFF4E95C9,
+0xFF4E96C8,
+0xFF5194C9,
+0xFF5192C8,
+0xFF5491C7,
+0xFF5592C9,
+0xFF5492CD,
+0xFF5293CD,
+0xFF5194CB,
+0xFF5192CA,
+0xFF5997D0,
+0xFF5C93CB,
+0xFF6691C4,
+0xFF4D657D,
+0xFFB3AF92,
+0xFFE8E3A3,
+0xFF778536,
+0xFF6B832D,
+0xFF6A8129,
+0xFF768A31,
+0xFF6F862C,
+0xFF6C832B,
+0xFF6A7926,
+0xFFA18241,
+0xFF951A00,
+0xFFC51B0C,
+0xFFC5190B,
+0xFFAB2420,
+0xFF692A3D,
+0xFF444677,
+0xFF225CAE,
+0xFF0657B3,
+0xFF07489C,
+0xFF00357F,
+0xFF145096,
+0xFF5E9BDE,
+0xFF5794D7,
+0xFF5691D3,
+0xFF5C94CF,
+0xFF5992C9,
+0xFF5693CA,
+0xFF5295CA,
+0xFF4C97CE,
+0xFF4B98D0,
+0xFF4F95D0,
+0xFF5294D0,
+0xFF5394CE,
+0xFF5394CC,
+0xFF5295CC,
+0xFF5295CA,
+0xFF5295CA,
+0xFF5295CA,
+0xFF5295CC,
+0xFF5295CC,
+0xFF5295CC,
+0xFF5295CC,
+0xFF5396CD,
+0xFF5295CC,
+0xFF5295CC,
+0xFF5295CC,
+0xFF5295CC,
+0xFF5295CC,
+0xFF5295CC,
+0xFF5295CC,
+0xFF5295CC,
+0xFF5295CC,
+0xFF5295CC,
+0xFF5295CC,
+0xFF5295CC,
+0xFF5295CC,
+0xFF5295CC,
+0xFF5295CC,
+0xFF5295CC,
+0xFF5295CC,
+0xFF5295CC,
+0xFF5295CC,
+0xFF5295CC,
+0xFF5295CC,
+0xFF5295CC,
+0xFF5295CC,
+0xFF5295CC,
+0xFF5295CC,
+0xFF5295CC,
+0xFF5295CC,
+0xFF5295CC,
+0xFF5295CC,
+0xFF5295CC,
+0xFF5396CD,
+0xFF5295CC,
+0xFF5295CC,
+0xFF5295CC,
+0xFF5295CC,
+0xFF5295CC,
+0xFF5295CC,
+0xFF5295CC,
+0xFF5295CC,
+0xFF5396CD,
+0xFF5295CC,
+0xFF5295CC,
+0xFF5295CC,
+0xFF5295CC,
+0xFF5295CC,
+0xFF5295CC,
+0xFF5295CC,
+0xFF5295CC,
+0xFF5295CC,
+0xFF5295CC,
+0xFF5295CC,
+0xFF4F94CB,
+0xFF4F94CB,
+0xFF4F94CB,
+0xFF4F94CB,
+0xFF5092CC,
+0xFF5193CD,
+0xFF5193CD,
+0xFF5193CD,
+0xFF5092CC,
+0xFF5092CC,
+0xFF4E93CC,
+0xFF4E93CC,
+0xFF4D92CB,
+0xFF4D92CB,
+0xFF4D92CB,
+0xFF4C91CA,
+0xFF4C91CA,
+0xFF4C91CA,
+0xFF4B90C9,
+0xFF4B90C9,
+0xFF4B90CB,
+0xFF4B90CB,
+0xFF4A8FCA,
+0xFF4A8FCA,
+0xFF4C8ECA,
+0xFF4B8DC9,
+0xFF4B8DC9,
+0xFF4B8DC9,
+0xFF4A8CC8,
+0xFF4A8CC8,
+0xFF4A8CC8,
+0xFF498BC7,
+0xFF498BC7,
+0xFF498BC7,
+0xFF4A8AC8,
+0xFF4A8AC8,
+0xFF4A8AC8,
+0xFF4A8AC8,
+0xFF4989C7,
+0xFF4888C6,
+0xFF4888C6,
+0xFF4787C5,
+0xFF4787C5,
+0xFF4787C5,
+0xFF4686C4,
+0xFF4686C4,
+0xFF4784C3,
+0xFF4784C3,
+0xFF4784C3,
+0xFF4784C3,
+0xFF4683C4,
+0xFF4683C4,
+0xFF5283BE,
+0xFF5081BB,
+0xFF5182BC,
+0xFF5788C2,
+0xFF5A88C3,
+0xFF5384BF,
+0xFF4E80BB,
+0xFF4D81BD,
+0xFF477EBE,
+0xFF457FBF,
+0xFF4581C0,
+0xFF4481C0,
+0xFF4582C1,
+0xFF4583C0,
+0xFF4682C0,
+0xFF4783C1,
+0xFF4784C3,
+0xFF4784C3,
+0xFF4784C3,
+0xFF4784C3,
+0xFF4784C3,
+0xFF4885C4,
+0xFF4885C4,
+0xFF4986C5,
+0xFF4986C5,
+0xFF4A87C6,
+0xFF4A87C6,
+0xFF4A87C6,
+0xFF4A87C6,
+0xFF4A87C6,
+0xFF4B88C7,
+0xFF4B88C7,
+0xFF4B89C6,
+0xFF4B89C6,
+0xFF4B89C6,
+0xFF4C8AC7,
+0xFF4E8CC9,
+0xFF518FCA,
+0xFF508EC9,
+0xFF4E8CC7,
+0xFF4D8BC6,
+0xFF4E8CC7,
+0xFF4C8DC7,
+0xFF4C8DC7,
+0xFF4D8DCA,
+0xFF4E8ECB,
+0xFF4E8ECB,
+0xFF4D8EC8,
+0xFF4F8DC8,
+0xFF4F8DC8,
+0xFF4F8DC8,
+0xFF508EC9,
+0xFF508EC9,
+0xFF518FCA,
+0xFF4F90CA,
+0xFF4E8FC9,
+0xFF4F90CA,
+0xFF4F90CA,
+0xFF4F90CA,
+0xFF4F90CA,
+0xFF4F90CA,
+0xFF4F90CA,
+0xFF4F90CA,
+0xFF5091CB,
+0xFF4F90CA,
+0xFF4F90CA,
+0xFF5091CB,
+0xFF5091CB,
+0xFF4F90CA,
+0xFF4F90CA,
+0xFF4E90CA,
+0xFF4F91CB,
+0xFF4F91CB,
+0xFF4F91CB,
+0xFF4F91CB,
+0xFF4F91CB,
+0xFF4D92CB,
+0xFF4D92CB,
+0xFF4D92CB,
+0xFF4D92CB,
+0xFF4F91CB,
+0xFF4F91CB,
+0xFF4D92CB,
+0xFF4D92CB,
+0xFF4D92CB,
+0xFF4D92CB,
+0xFF4D92CB,
+0xFF4D92CB,
+0xFF4D92CB,
+0xFF4D92CB,
+0xFF4D92CB,
+0xFF4E93CC,
+0xFF4D94CC,
+0xFF4D94CC,
+0xFF4C93CB,
+0xFF4C93CB,
+0xFF4D92CB,
+0xFF4D92CB,
+0xFF4D92CB,
+0xFF4D92CB,
+0xFF4D92CB,
+0xFF4D92CB,
+0xFF4E93CC,
+0xFF4E93CC,
+0xFF4E93CC,
+0xFF4E93CC,
+0xFF4E93CC,
+0xFF4E93CC,
+0xFF4E93CC,
+0xFF4E93CC,
+0xFF4E93CC,
+0xFF4E93CC,
+0xFF4E93CA,
+0xFF4E93CA,
+0xFF4E93CA,
+0xFF4E93CA,
+0xFF4E93CA,
+0xFF4F94CB,
+0xFF4F94CB,
+0xFF4F94CB,
+0xFF4E93CA,
+0xFF4F94CB,
+0xFF4F94CB,
+0xFF4F94CB,
+0xFF4E93CA,
+0xFF4E93CA,
+0xFF4F94CB,
+0xFF4F94CB,
+0xFF4F94CB,
+0xFF4F94CB,
+0xFF4F94CB,
+0xFF4F94CB,
+0xFF4F94CB,
+0xFF4F94CB,
+0xFF4F94CB,
+0xFF4F94CB,
+0xFF4F94CB,
+0xFF4F94CB,
+0xFF4F94CB,
+0xFF4F94CB,
+0xFF4F94CB,
+0xFF4F94CB,
+0xFF4F94CB,
+0xFF4F94CB,
+0xFF5093C8,
+0xFF4E94C8,
+0xFF4F96CE,
+0xFF4D94CA,
+0xFF5092C6,
+0xFF5594C9,
+0xFF5693CC,
+0xFF5089C0,
+0xFF83B2E6,
+0xFF386899,
+0xFF5E97CC,
+0xFF5291C4,
+0xFF5898C8,
+0xFF5395C7,
+0xFF4D8EC4,
+0xFF5396CD,
+0xFF4F96CA,
+0xFF5096C9,
+0xFF5295CA,
+0xFF5594C9,
+0xFF5693C9,
+0xFF5794CB,
+0xFF5495CF,
+0xFF5294D0,
+0xFF5095CE,
+0xFF5294CE,
+0xFF4F90CA,
+0xFF5691CB,
+0xFF5A8EC7,
+0xFF6486A2,
+0xFF908E77,
+0xFFECE3A8,
+0xFF7A883B,
+0xFF6D852F,
+0xFF768A35,
+0xFF6E822B,
+0xFF6E852B,
+0xFF748831,
+0xFF71792E,
+0xFF704711,
+0xFFB1301B,
+0xFFC01B15,
+0xFFB01910,
+0xFF953034,
+0xFF35254A,
+0xFF2E5493,
+0xFF1455A7,
+0xFF004197,
+0xFF002874,
+0xFF316AAD,
+0xFF619FDC,
+0xFF5597D3,
+0xFF5192D2,
+0xFF4F8FCD,
+0xFF5C94CD,
+0xFF5992C7,
+0xFF5794CA,
+0xFF5196CD,
+0xFF4D98CF,
+0xFF4D98CF,
+0xFF5196CF,
+0xFF5395CF,
+0xFF5495CB,
+0xFF5396CB,
+0xFF5396CB,
+0xFF5396CB,
+0xFF5396CB,
+0xFF5396CB,
+0xFF5396CD,
+0xFF5396CD,
+0xFF5396CD,
+0xFF5396CD,
+0xFF5396CD,
+0xFF5396CD,
+0xFF5396CD,
+0xFF5396CD,
+0xFF5396CD,
+0xFF5396CD,
+0xFF5396CD,
+0xFF5396CD,
+0xFF5396CD,
+0xFF5396CD,
+0xFF5396CD,
+0xFF5396CD,
+0xFF5396CD,
+0xFF5396CD,
+0xFF5396CD,
+0xFF5396CD,
+0xFF5396CD,
+0xFF5396CD,
+0xFF5396CD,
+0xFF5396CD,
+0xFF5396CD,
+0xFF5396CD,
+0xFF5396CD,
+0xFF5396CD,
+0xFF5396CD,
+0xFF5396CD,
+0xFF5396CD,
+0xFF5396CD,
+0xFF5396CD,
+0xFF5396CD,
+0xFF5396CD,
+0xFF5396CD,
+0xFF5396CD,
+0xFF5396CD,
+0xFF5396CD,
+0xFF5396CD,
+0xFF5396CD,
+0xFF5396CD,
+0xFF5396CD,
+0xFF5396CD,
+0xFF5396CD,
+0xFF5396CD,
+0xFF5396CD,
+0xFF5396CD,
+0xFF5396CD,
+0xFF5396CD,
+0xFF5396CD,
+0xFF5396CD,
+0xFF5295CC,
+0xFF5295CC,
+0xFF5295CC,
+0xFF5295CC,
+0xFF5095CC,
+0xFF5095CC,
+0xFF4F94CB,
+0xFF4F94CB,
+0xFF5294CE,
+0xFF5294CE,
+0xFF5294CE,
+0xFF5294CE,
+0xFF5193CD,
+0xFF5193CD,
+0xFF4F94CD,
+0xFF4F94CD,
+0xFF4E93CC,
+0xFF4E93CC,
+0xFF4E93CC,
+0xFF4D92CB,
+0xFF4D92CB,
+0xFF4D92CB,
+0xFF4C91CA,
+0xFF4C91CA,
+0xFF4C91CC,
+0xFF4C91CC,
+0xFF4C91CC,
+0xFF4B90CB,
+0xFF4D8FCB,
+0xFF4C8ECA,
+0xFF4C8ECA,
+0xFF4C8ECA,
+0xFF4B8DC9,
+0xFF4A8CC8,
+0xFF4A8CC8,
+0xFF498BC7,
+0xFF498BC7,
+0xFF498BC7,
+0xFF4A8AC8,
+0xFF4A8AC8,
+0xFF4B8BC9,
+0xFF4A8AC8,
+0xFF4A8AC8,
+0xFF4989C7,
+0xFF4888C6,
+0xFF4888C6,
+0xFF4888C6,
+0xFF4888C6,
+0xFF4787C5,
+0xFF4787C5,
+0xFF4885C4,
+0xFF4885C4,
+0xFF4885C4,
+0xFF4885C4,
+0xFF4784C5,
+0xFF4683C4,
+0xFF5A88C3,
+0xFF5B8AC2,
+0xFF5F8EC6,
+0xFF6493CB,
+0xFF6390C9,
+0xFF5A88C3,
+0xFF5283BE,
+0xFF5183C0,
+0xFF4B81BF,
+0xFF4882C1,
+0xFF4682C1,
+0xFF4582C1,
+0xFF4582C1,
+0xFF4583C0,
+0xFF4783C1,
+0xFF4884C0,
+0xFF4785C2,
+0xFF4785C2,
+0xFF4785C2,
+0xFF4886C3,
+0xFF4886C3,
+0xFF4987C4,
+0xFF4987C4,
+0xFF4987C4,
+0xFF4A88C5,
+0xFF4A88C5,
+0xFF4989C6,
+0xFF4989C6,
+0xFF4989C6,
+0xFF4989C6,
+0xFF4989C6,
+0xFF4A8AC7,
+0xFF4D8BC8,
+0xFF4C8AC7,
+0xFF4C8AC5,
+0xFF4D8BC6,
+0xFF518FCA,
+0xFF5391CC,
+0xFF518FCA,
+0xFF4E8CC5,
+0xFF4E8CC5,
+0xFF4F8DC6,
+0xFF4F8DC6,
+0xFF4E8CC5,
+0xFF508EC9,
+0xFF518FCA,
+0xFF518FCA,
+0xFF508EC9,
+0xFF508EC9,
+0xFF508EC7,
+0xFF4F8DC6,
+0xFF508EC7,
+0xFF518FC8,
+0xFF518FC8,
+0xFF4E8FC7,
+0xFF4E8FC7,
+0xFF4E8FC7,
+0xFF4F90C8,
+0xFF5091C9,
+0xFF5091C9,
+0xFF4E91C8,
+0xFF4E91C8,
+0xFF4E91C8,
+0xFF4F92C9,
+0xFF4F92C9,
+0xFF4F92C9,
+0xFF5093CA,
+0xFF4F92C9,
+0xFF4F92C9,
+0xFF4F92C9,
+0xFF4F92C9,
+0xFF5093CA,
+0xFF4E93CA,
+0xFF4E93CA,
+0xFF4E93CA,
+0xFF4E93CA,
+0xFF4E93CA,
+0xFF4E93CA,
+0xFF4D94CA,
+0xFF4D94CA,
+0xFF4E93CC,
+0xFF4D92CB,
+0xFF4D92CB,
+0xFF4D92CB,
+0xFF4D92CB,
+0xFF4D92CB,
+0xFF4E93CC,
+0xFF4E93CC,
+0xFF4E93CC,
+0xFF4E93CC,
+0xFF4E93CC,
+0xFF4E93CC,
+0xFF4E93CC,
+0xFF4E93CC,
+0xFF4E93CC,
+0xFF4E93CC,
+0xFF4E93CA,
+0xFF4E93CA,
+0xFF4E93CA,
+0xFF4E93CA,
+0xFF4E93CA,
+0xFF4E93CA,
+0xFF4E93CA,
+0xFF4E93CA,
+0xFF4E93CA,
+0xFF4E93CA,
+0xFF4F94CB,
+0xFF4F94CB,
+0xFF4F94CB,
+0xFF4F94CB,
+0xFF4F94CB,
+0xFF4F94CB,
+0xFF4F94CB,
+0xFF4F94CB,
+0xFF4F94CB,
+0xFF4F94CB,
+0xFF4F94CB,
+0xFF4F94CB,
+0xFF4F94CB,
+0xFF4F94CB,
+0xFF4F94CB,
+0xFF4F94CB,
+0xFF4F94CB,
+0xFF4F94CB,
+0xFF4F94CB,
+0xFF4F94CB,
+0xFF4F94CB,
+0xFF5095CC,
+0xFF4F94CB,
+0xFF5095CC,
+0xFF5095CC,
+0xFF5095CC,
+0xFF5095CC,
+0xFF5095CC,
+0xFF5095CC,
+0xFF5095CC,
+0xFF4F94CB,
+0xFF5095CC,
+0xFF5095CC,
+0xFF5095CC,
+0xFF5095CC,
+0xFF5095CC,
+0xFF5095CC,
+0xFF5095CC,
+0xFF5295CC,
+0xFF4F94CB,
+0xFF5198CC,
+0xFF5299CD,
+0xFF5197CB,
+0xFF5491C7,
+0xFF598CC1,
+0xFF90C2F7,
+0xFF5B92C8,
+0xFF5D96CB,
+0xFF5894C6,
+0xFF5795C6,
+0xFF5698CC,
+0xFF4E94C8,
+0xFF5399CD,
+0xFF5298CC,
+0xFF5096C9,
+0xFF5295C9,
+0xFF5496CA,
+0xFF5695CA,
+0xFF5695CA,
+0xFF5695CB,
+0xFF5395CF,
+0xFF5196CF,
+0xFF5398D1,
+0xFF5398D1,
+0xFF5294D0,
+0xFF5596D0,
+0xFF5A97D0,
+0xFF6B94B4,
+0xFF8E9082,
+0xFFD8D09F,
+0xFF858F46,
+0xFF677B26,
+0xFF758B36,
+0xFF6C862F,
+0xFF6A862F,
+0xFF718433,
+0xFF828043,
+0xFF562500,
+0xFFA72C1D,
+0xFFAB191A,
+0xFF9B282D,
+0xFF5A1F35,
+0xFF3D528B,
+0xFF12509B,
+0xFF064690,
+0xFF002F73,
+0xFF4D8BC8,
+0xFF62A3D9,
+0xFF4D94C8,
+0xFF4B94C7,
+0xFF569DD5,
+0xFF559AD1,
+0xFF5194C8,
+0xFF5599CA,
+0xFF5298CB,
+0xFF5198CC,
+0xFF5298CB,
+0xFF5497CB,
+0xFF5995CB,
+0xFF5995C9,
+0xFF5597C7,
+0xFF5498C7,
+0xFF5497CB,
+0xFF5497CC,
+0xFF5497CC,
+0xFF5497CC,
+0xFF5497CC,
+0xFF5497CC,
+0xFF5497CC,
+0xFF5497CC,
+0xFF5396CB,
+0xFF5497CC,
+0xFF5497CC,
+0xFF5497CC,
+0xFF5497CE,
+0xFF5497CE,
+0xFF5497CE,
+0xFF5497CE,
+0xFF5497CC,
+0xFF5497CC,
+0xFF5497CC,
+0xFF5497CC,
+0xFF5497CC,
+0xFF5497CC,
+0xFF5497CC,
+0xFF5497CC,
+0xFF5497CC,
+0xFF5497CC,
+0xFF5497CC,
+0xFF5497CC,
+0xFF5497CC,
+0xFF5497CC,
+0xFF5497CC,
+0xFF5497CC,
+0xFF5396CD,
+0xFF5396CD,
+0xFF5396CD,
+0xFF5396CD,
+0xFF5497CE,
+0xFF5497CE,
+0xFF5497CE,
+0xFF5497CE,
+0xFF5497CE,
+0xFF5497CE,
+0xFF5497CE,
+0xFF5497CE,
+0xFF5497CE,
+0xFF5396CD,
+0xFF5396CD,
+0xFF5396CD,
+0xFF5497CC,
+0xFF5497CC,
+0xFF5497CC,
+0xFF5497CC,
+0xFF5396CB,
+0xFF5396CB,
+0xFF5396CB,
+0xFF5396CB,
+0xFF5396CD,
+0xFF5396CD,
+0xFF5396CD,
+0xFF5396CD,
+0xFF5396CD,
+0xFF5396CD,
+0xFF5396CD,
+0xFF5396CD,
+0xFF5295CC,
+0xFF5295CC,
+0xFF5295CC,
+0xFF5295CC,
+0xFF5295CC,
+0xFF5295CC,
+0xFF5194CB,
+0xFF5194CB,
+0xFF5193CD,
+0xFF5193CD,
+0xFF4E93CC,
+0xFF4E93CC,
+0xFF4E93CC,
+0xFF4D92CB,
+0xFF4D92CB,
+0xFF4D92CB,
+0xFF4D92CD,
+0xFF4D92CD,
+0xFF4C91CC,
+0xFF4C91CC,
+0xFF4B90CB,
+0xFF4B90CB,
+0xFF4B90CB,
+0xFF4A8FCA,
+0xFF4C8ECA,
+0xFF4C8ECA,
+0xFF4B8DC9,
+0xFF4B8DC9,
+0xFF4A8CC8,
+0xFF4A8CC8,
+0xFF4A8CC8,
+0xFF4A8CC8,
+0xFF4A8CC9,
+0xFF498BC8,
+0xFF498BC8,
+0xFF488AC7,
+0xFF4989C7,
+0xFF4989C7,
+0xFF4989C7,
+0xFF4989C7,
+0xFF4888C6,
+0xFF4888C6,
+0xFF4986C5,
+0xFF4986C5,
+0xFF4986C5,
+0xFF4885C4,
+0xFF4784C3,
+0xFF4683C2,
+0xFF5B8AC2,
+0xFF5E8DC3,
+0xFF6592C9,
+0xFF6996CD,
+0xFF6895CE,
+0xFF618EC7,
+0xFF5987C2,
+0xFF5385C0,
+0xFF4D83BF,
+0xFF4984C0,
+0xFF4783C1,
+0xFF4582C1,
+0xFF4583C0,
+0xFF4684C1,
+0xFF4884C0,
+0xFF4985C1,
+0xFF4985C3,
+0xFF4886C3,
+0xFF4886C3,
+0xFF4886C3,
+0xFF4987C4,
+0xFF4987C4,
+0xFF4A88C5,
+0xFF4A88C5,
+0xFF4B89C6,
+0xFF4B89C6,
+0xFF4A8AC7,
+0xFF4A8AC7,
+0xFF4A8AC7,
+0xFF4A8AC7,
+0xFF4A8AC7,
+0xFF4B8BC8,
+0xFF4D8BC8,
+0xFF4D8BC8,
+0xFF4D8BC6,
+0xFF4E8CC7,
+0xFF5290CB,
+0xFF5593CE,
+0xFF5492CB,
+0xFF5290C9,
+0xFF508EC7,
+0xFF508EC7,
+0xFF4F8DC6,
+0xFF4F8DC6,
+0xFF508EC9,
+0xFF5290CB,
+0xFF5290CB,
+0xFF518FCA,
+0xFF5290C9,
+0xFF5290C9,
+0xFF5290C9,
+0xFF518FC8,
+0xFF518FC8,
+0xFF518FC8,
+0xFF4F90C8,
+0xFF4E8FC7,
+0xFF4E8FC7,
+0xFF4F90C8,
+0xFF5091C9,
+0xFF5091C9,
+0xFF4F92C9,
+0xFF4F92C9,
+0xFF4F92C9,
+0xFF5093CA,
+0xFF5093CA,
+0xFF5093CA,
+0xFF5093CA,
+0xFF5093CA,
+0xFF5093CA,
+0xFF5093CA,
+0xFF5093CA,
+0xFF5093CA,
+0xFF4E93CA,
+0xFF4E93CA,
+0xFF4E93CA,
+0xFF4E93CA,
+0xFF4E93CA,
+0xFF4E93CA,
+0xFF4C93C9,
+0xFF4C93C9,
+0xFF4E93CC,
+0xFF4E93CC,
+0xFF4E93CC,
+0xFF4E93CC,
+0xFF4E93CC,
+0xFF4E93CC,
+0xFF4E93CC,
+0xFF4E93CC,
+0xFF4E93CC,
+0xFF4E93CC,
+0xFF4E93CC,
+0xFF4F94CD,
+0xFF4F94CD,
+0xFF4F94CD,
+0xFF4E93CC,
+0xFF4E93CC,
+0xFF4F94CB,
+0xFF4F94CB,
+0xFF4F94CB,
+0xFF4F94CB,
+0xFF4F94CB,
+0xFF4F94CB,
+0xFF4F94CB,
+0xFF4F94CB,
+0xFF5095CC,
+0xFF5095CC,
+0xFF5095CC,
+0xFF5095CC,
+0xFF5095CC,
+0xFF5095CC,
+0xFF5095CC,
+0xFF5095CC,
+0xFF4F94CB,
+0xFF5095CC,
+0xFF5095CC,
+0xFF5095CC,
+0xFF5095CC,
+0xFF5095CC,
+0xFF5095CC,
+0xFF5095CC,
+0xFF5095CC,
+0xFF5095CC,
+0xFF5095CC,
+0xFF5095CC,
+0xFF5095CC,
+0xFF5095CC,
+0xFF5095CC,
+0xFF5196CD,
+0xFF5095CC,
+0xFF5095CC,
+0xFF5196CD,
+0xFF5196CD,
+0xFF5196CD,
+0xFF5196CD,
+0xFF5196CD,
+0xFF5196CD,
+0xFF5196CD,
+0xFF5297CE,
+0xFF5297CE,
+0xFF5297CE,
+0xFF5196CD,
+0xFF5196CD,
+0xFF5297CE,
+0xFF5297CE,
+0xFF5196CF,
+0xFF5398CF,
+0xFF4D93C6,
+0xFF5295C9,
+0xFF589BD0,
+0xFF5390C6,
+0xFF87BBED,
+0xFF5B8FC1,
+0xFF5693C9,
+0xFF5796CC,
+0xFF5694C7,
+0xFF5796C9,
+0xFF5497CC,
+0xFF569BD2,
+0xFF5095CC,
+0xFF5298CC,
+0xFF5497CC,
+0xFF5597CB,
+0xFF5597CB,
+0xFF5697CD,
+0xFF5697CF,
+0xFF5497CE,
+0xFF5297CE,
+0xFF5299CF,
+0xFF5295CC,
+0xFF5194CB,
+0xFF559AD3,
+0xFF5297D0,
+0xFF5496D2,
+0xFF6191B7,
+0xFF7F8883,
+0xFFD1CEA5,
+0xFF98A25D,
+0xFF647624,
+0xFF738936,
+0xFF708935,
+0xFF6B852E,
+0xFF768439,
+0xFF847846,
+0xFF3F0700,
+0xFFA02B24,
+0xFF941B24,
+0xFF70283E,
+0xFF46355F,
+0xFF2B5398,
+0xFF00408B,
+0xFF024184,
+0xFF5F9DD8,
+0xFF5D9CD1,
+0xFF5699CD,
+0xFF519BCC,
+0xFF4F9BCD,
+0xFF5198CC,
+0xFF4F95C8,
+0xFF549CCC,
+0xFF4F97C7,
+0xFF519ACD,
+0xFF5299CD,
+0xFF5399CC,
+0xFF5698CA,
+0xFF5A96CA,
+0xFF5A96C8,
+0xFF5698C8,
+0xFF5399CA,
+0xFF5598CC,
+0xFF5598CD,
+0xFF5598CD,
+0xFF5598CD,
+0xFF5598CD,
+0xFF5598CD,
+0xFF5598CD,
+0xFF5598CD,
+0xFF5497CC,
+0xFF5497CC,
+0xFF5497CC,
+0xFF5598CD,
+0xFF5598CF,
+0xFF5598CF,
+0xFF5598CF,
+0xFF5598CF,
+0xFF5598CD,
+0xFF5598CD,
+0xFF5598CD,
+0xFF5598CD,
+0xFF5598CD,
+0xFF5598CD,
+0xFF5598CD,
+0xFF5598CD,
+0xFF5497CC,
+0xFF5497CC,
+0xFF5497CC,
+0xFF5497CC,
+0xFF5497CC,
+0xFF5497CC,
+0xFF5497CC,
+0xFF5497CC,
+0xFF5497CE,
+0xFF5497CE,
+0xFF5497CE,
+0xFF5497CE,
+0xFF5497CE,
+0xFF5497CE,
+0xFF5497CE,
+0xFF5497CE,
+0xFF5497CE,
+0xFF5497CE,
+0xFF5497CE,
+0xFF5497CE,
+0xFF5497CE,
+0xFF5497CE,
+0xFF5497CE,
+0xFF5497CE,
+0xFF5497CC,
+0xFF5497CC,
+0xFF5497CC,
+0xFF5497CC,
+0xFF5497CC,
+0xFF5497CC,
+0xFF5497CC,
+0xFF5497CC,
+0xFF5497CE,
+0xFF5497CE,
+0xFF5497CE,
+0xFF5497CE,
+0xFF5497CE,
+0xFF5396CD,
+0xFF5396CD,
+0xFF5396CD,
+0xFF5396CD,
+0xFF5396CD,
+0xFF5396CD,
+0xFF5396CD,
+0xFF5396CD,
+0xFF5295CC,
+0xFF5295CC,
+0xFF5295CC,
+0xFF5193CD,
+0xFF5193CD,
+0xFF4F94CD,
+0xFF4F94CD,
+0xFF4F94CD,
+0xFF4E93CC,
+0xFF4E93CC,
+0xFF4E93CC,
+0xFF4E93CE,
+0xFF4D92CD,
+0xFF4D92CD,
+0xFF4D92CD,
+0xFF4C91CC,
+0xFF4C91CC,
+0xFF4B90CB,
+0xFF4B90CB,
+0xFF4D8FCB,
+0xFF4D8FCB,
+0xFF4C8ECA,
+0xFF4C8ECA,
+0xFF4B8DC9,
+0xFF4B8DC9,
+0xFF4B8DC9,
+0xFF4B8DC9,
+0xFF4A8CC9,
+0xFF4A8CC9,
+0xFF498BC8,
+0xFF498BC8,
+0xFF4A8AC8,
+0xFF4A8AC8,
+0xFF4A8AC8,
+0xFF4A8AC8,
+0xFF4A8AC8,
+0xFF4989C7,
+0xFF4A87C6,
+0xFF4A87C6,
+0xFF4986C5,
+0xFF4986C5,
+0xFF4885C4,
+0xFF4784C3,
+0xFF5683BA,
+0xFF5886BA,
+0xFF5E89BE,
+0xFF638EC3,
+0xFF6691C8,
+0xFF628FC8,
+0xFF5C8AC5,
+0xFF5687C2,
+0xFF4D83BF,
+0xFF4A85C1,
+0xFF4884C2,
+0xFF4884C2,
+0xFF4884C2,
+0xFF4884C2,
+0xFF4A85C1,
+0xFF4985C1,
+0xFF4A86C4,
+0xFF4A86C4,
+0xFF4A86C4,
+0xFF4A86C4,
+0xFF4A88C5,
+0xFF4A88C5,
+0xFF4B89C6,
+0xFF4B89C6,
+0xFF4A8AC7,
+0xFF4A8AC7,
+0xFF4B8BC8,
+0xFF4B8BC8,
+0xFF4B8BC8,
+0xFF4B8BC8,
+0xFF4B8BC8,
+0xFF4C8CC9,
+0xFF4C8AC5,
+0xFF4D8BC6,
+0xFF4E8CC7,
+0xFF4F8DC8,
+0xFF518FC8,
+0xFF5593CC,
+0xFF5896CF,
+0xFF5997D0,
+0xFF5290C9,
+0xFF518FC8,
+0xFF518EC7,
+0xFF508DC6,
+0xFF528FC8,
+0xFF5592CB,
+0xFF5591CD,
+0xFF5490CC,
+0xFF5491CA,
+0xFF5693CC,
+0xFF5794CD,
+0xFF5693CC,
+0xFF5492CB,
+0xFF5391CA,
+0xFF5492CB,
+0xFF5694CD,
+0xFF5192CA,
+0xFF5293CB,
+0xFF5194CB,
+0xFF5093CA,
+0xFF4F92C9,
+0xFF4F92C9,
+0xFF4E93CA,
+0xFF4F94CB,
+0xFF5093CA,
+0xFF5093CA,
+0xFF5194CB,
+0xFF5093CA,
+0xFF5093CA,
+0xFF5093CA,
+0xFF4E93CA,
+0xFF4F94CB,
+0xFF4E93CA,
+0xFF4E93CA,
+0xFF4D94CA,
+0xFF4D94CA,
+0xFF4D94CA,
+0xFF4D94CA,
+0xFF4D94CA,
+0xFF4D94CA,
+0xFF4E95CB,
+0xFF4E95CB,
+0xFF4E95CB,
+0xFF4E95CB,
+0xFF4E95CB,
+0xFF4E95CB,
+0xFF4E95CB,
+0xFF4E95CB,
+0xFF4E95CB,
+0xFF4E95CB,
+0xFF5095CC,
+0xFF5095CC,
+0xFF5095CC,
+0xFF5095CC,
+0xFF5095CC,
+0xFF5095CC,
+0xFF5295CC,
+0xFF5295CC,
+0xFF5095CC,
+0xFF5095CC,
+0xFF5095CC,
+0xFF5095CC,
+0xFF5095CC,
+0xFF5095CC,
+0xFF5095CC,
+0xFF5196CD,
+0xFF5196CD,
+0xFF5196CD,
+0xFF5196CD,
+0xFF5196CD,
+0xFF5196CD,
+0xFF5196CD,
+0xFF5095CC,
+0xFF5095CC,
+0xFF5196CD,
+0xFF5196CD,
+0xFF5196CD,
+0xFF5196CD,
+0xFF5196CD,
+0xFF5196CD,
+0xFF5196CD,
+0xFF5196CD,
+0xFF5297CE,
+0xFF5297CE,
+0xFF5196CD,
+0xFF5196CD,
+0xFF5196CD,
+0xFF5297CE,
+0xFF5297CE,
+0xFF5297CE,
+0xFF5297CE,
+0xFF5297CE,
+0xFF5297CE,
+0xFF5297CE,
+0xFF5297CE,
+0xFF5297CE,
+0xFF5297CE,
+0xFF5398CF,
+0xFF5398CF,
+0xFF5398CF,
+0xFF5297CE,
+0xFF5297CE,
+0xFF5398CF,
+0xFF5398CF,
+0xFF5398D1,
+0xFF4F94CB,
+0xFF5899CF,
+0xFF5392C7,
+0xFF5490C2,
+0xFF83BFF1,
+0xFF5593C4,
+0xFF5D9DCD,
+0xFF5799CB,
+0xFF5698CC,
+0xFF5598CD,
+0xFF579ACF,
+0xFF5194C9,
+0xFF5196CD,
+0xFF569BD2,
+0xFF5396CB,
+0xFF5697CD,
+0xFF5796CC,
+0xFF5597CB,
+0xFF5598CD,
+0xFF5398D3,
+0xFF5197D2,
+0xFF5198CE,
+0xFF5399CC,
+0xFF599BCD,
+0xFF5594C7,
+0xFF5298CB,
+0xFF5198CE,
+0xFF5499D4,
+0xFF6598C3,
+0xFF73868C,
+0xFFBBC2A3,
+0xFFA9B978,
+0xFF657B28,
+0xFF6F8532,
+0xFF70842F,
+0xFF738634,
+0xFF7E8340,
+0xFF5B4722,
+0xFF4F1706,
+0xFF871E1A,
+0xFF8C2F41,
+0xFF37214F,
+0xFF38528F,
+0xFF002B6D,
+0xFF2D69A8,
+0xFF68A6E1,
+0xFF5A99CF,
+0xFF5796CB,
+0xFF5394CA,
+0xFF539AD2,
+0xFF539AD2,
+0xFF5899CF,
+0xFF5294C6,
+0xFF569FCC,
+0xFF529ACA,
+0xFF5499D2,
+0xFF5499D4,
+0xFF539AD0,
+0xFF549ACE,
+0xFF5699CD,
+0xFF5799CD,
+0xFF5699D0,
+0xFF5499D0,
+0xFF5598CD,
+0xFF5699CE,
+0xFF5699CE,
+0xFF5699CE,
+0xFF5699CE,
+0xFF5699CE,
+0xFF5699CE,
+0xFF5699CE,
+0xFF5598CD,
+0xFF5598CD,
+0xFF5598CD,
+0xFF5598CD,
+0xFF5598CD,
+0xFF5699CE,
+0xFF5699CE,
+0xFF5699CE,
+0xFF5598CD,
+0xFF5598CD,
+0xFF5598CD,
+0xFF5598CD,
+0xFF5598CD,
+0xFF5598CD,
+0xFF5598CD,
+0xFF5598CD,
+0xFF5598CD,
+0xFF5598CD,
+0xFF5598CD,
+0xFF5598CD,
+0xFF5598CD,
+0xFF5598CD,
+0xFF5598CD,
+0xFF5598CD,
+0xFF5598CD,
+0xFF5598CD,
+0xFF5598CD,
+0xFF5598CD,
+0xFF5598CD,
+0xFF5598CD,
+0xFF5598CD,
+0xFF5598CD,
+0xFF5598CD,
+0xFF5598CD,
+0xFF5598CD,
+0xFF5598CD,
+0xFF5598CD,
+0xFF5598CD,
+0xFF5598CD,
+0xFF5598CD,
+0xFF5399CD,
+0xFF5399CD,
+0xFF5399CD,
+0xFF5399CD,
+0xFF5399CD,
+0xFF5399CD,
+0xFF5598CD,
+0xFF5598CD,
+0xFF5497CC,
+0xFF5497CC,
+0xFF5497CC,
+0xFF5497CC,
+0xFF5497CE,
+0xFF5497CE,
+0xFF5596CE,
+0xFF5495CD,
+0xFF5596CE,
+0xFF5596CE,
+0xFF5596CE,
+0xFF5596CE,
+0xFF5396CD,
+0xFF5396CD,
+0xFF5396CD,
+0xFF5295CC,
+0xFF5295CC,
+0xFF5295CC,
+0xFF5095CC,
+0xFF5095CC,
+0xFF5095CE,
+0xFF4F94CD,
+0xFF4F94CD,
+0xFF4F94CD,
+0xFF4F94CD,
+0xFF4E93CC,
+0xFF4E93CC,
+0xFF4E93CC,
+0xFF4D92CD,
+0xFF4D92CD,
+0xFF4C91CC,
+0xFF4C91CC,
+0xFF4D8FCB,
+0xFF4D8FCB,
+0xFF4D8FCB,
+0xFF4D8FCB,
+0xFF4C8ECA,
+0xFF4B8DC9,
+0xFF4B8DC9,
+0xFF4B8DC9,
+0xFF4A8CC8,
+0xFF4A8CC8,
+0xFF4A8CC8,
+0xFF4A8CC8,
+0xFF4A8CC9,
+0xFF498BC8,
+0xFF4A8AC8,
+0xFF4A8AC8,
+0xFF4A8AC8,
+0xFF4A8AC8,
+0xFF4B88C7,
+0xFF4B88C7,
+0xFF4A87C6,
+0xFF4A87C6,
+0xFF4A86C5,
+0xFF4985C4,
+0xFF5281B9,
+0xFF5180B6,
+0xFF5281B9,
+0xFF5584BC,
+0xFF5B8AC2,
+0xFF5F8DC8,
+0xFF5B8CC6,
+0xFF5587C2,
+0xFF4D83BF,
+0xFF4C84C1,
+0xFF4A85C1,
+0xFF4985C3,
+0xFF4985C3,
+0xFF4985C3,
+0xFF4A85C1,
+0xFF4985C1,
+0xFF4B87C5,
+0xFF4A88C5,
+0xFF4B87C5,
+0xFF4A88C5,
+0xFF4A88C5,
+0xFF4B89C6,
+0xFF4B89C6,
+0xFF4C8AC7,
+0xFF4A8AC7,
+0xFF4A8AC7,
+0xFF4B8BC8,
+0xFF4B8BC8,
+0xFF4B8BC8,
+0xFF4B8BC8,
+0xFF4B8BC8,
+0xFF4C8CC9,
+0xFF4E8CC7,
+0xFF508EC9,
+0xFF508EC9,
+0xFF4F8DC8,
+0xFF508EC7,
+0xFF5391CA,
+0xFF5896CF,
+0xFF5C9AD3,
+0xFF5391CA,
+0xFF5290C9,
+0xFF508EC7,
+0xFF4F8DC6,
+0xFF5390C9,
+0xFF5492CB,
+0xFF5593CE,
+0xFF5492CB,
+0xFF5592CB,
+0xFF5895CC,
+0xFF5A97CE,
+0xFF5A97CE,
+0xFF5895CC,
+0xFF5695CB,
+0xFF5997D0,
+0xFF5C9AD3,
+0xFF5896CF,
+0xFF5697CF,
+0xFF5596CE,
+0xFF5295CC,
+0xFF5093CA,
+0xFF4F92C9,
+0xFF4E93CA,
+0xFF4F94CB,
+0xFF5093CA,
+0xFF5194CB,
+0xFF5194CB,
+0xFF5194CB,
+0xFF5093CA,
+0xFF5093CA,
+0xFF4E93CA,
+0xFF4F94CB,
+0xFF4F94CB,
+0xFF4F94CB,
+0xFF4F94CB,
+0xFF4E95CB,
+0xFF4F94CB,
+0xFF4E95CB,
+0xFF4F94CB,
+0xFF4E95CB,
+0xFF4F94CB,
+0xFF4E95CB,
+0xFF5095CC,
+0xFF4F96CC,
+0xFF5095CC,
+0xFF4F96CC,
+0xFF5095CC,
+0xFF4E95CB,
+0xFF5196CD,
+0xFF5196CD,
+0xFF5196CD,
+0xFF5196CD,
+0xFF5196CD,
+0xFF5196CD,
+0xFF5196CD,
+0xFF5196CD,
+0xFF5396CD,
+0xFF5396CD,
+0xFF5396CD,
+0xFF5196CD,
+0xFF5196CD,
+0xFF5196CD,
+0xFF5196CD,
+0xFF5196CD,
+0xFF5196CD,
+0xFF5196CD,
+0xFF5196CD,
+0xFF5196CD,
+0xFF5297CE,
+0xFF5297CE,
+0xFF5297CE,
+0xFF5297CE,
+0xFF5196CD,
+0xFF5196CD,
+0xFF5297CE,
+0xFF5297CE,
+0xFF5297CE,
+0xFF5297CE,
+0xFF5196CD,
+0xFF5196CD,
+0xFF5297CE,
+0xFF5297CE,
+0xFF5398CF,
+0xFF5297CE,
+0xFF5297CE,
+0xFF5297CE,
+0xFF5297CE,
+0xFF5398CF,
+0xFF5598CF,
+0xFF5598CF,
+0xFF5598CF,
+0xFF5398CF,
+0xFF5398CF,
+0xFF5398CF,
+0xFF5398CF,
+0xFF5398CF,
+0xFF5297CE,
+0xFF5398CF,
+0xFF5398CF,
+0xFF5398CF,
+0xFF5297CE,
+0xFF5298CC,
+0xFF5398CF,
+0xFF549ACE,
+0xFF5396CD,
+0xFF589BD0,
+0xFF5A99CF,
+0xFF5490C4,
+0xFF7FB9EB,
+0xFF538FC1,
+0xFF589ACC,
+0xFF5096C7,
+0xFF5496C8,
+0xFF5598CC,
+0xFF5499D0,
+0xFF5095CC,
+0xFF589BD0,
+0xFF5598CD,
+0xFF5297CE,
+0xFF589BD2,
+0xFF5998CE,
+0xFF5897CD,
+0xFF5698CC,
+0xFF549ACE,
+0xFF5399D4,
+0xFF529AD4,
+0xFF529BCE,
+0xFF559BCC,
+0xFF5698C8,
+0xFF5999C9,
+0xFF569ACB,
+0xFF549ACE,
+0xFF5496D0,
+0xFF5F95C4,
+0xFF7695AA,
+0xFF8B9D8F,
+0xFFBCCE94,
+0xFF5C6F1D,
+0xFF728533,
+0xFF758735,
+0xFF748233,
+0xFF8A8A4C,
+0xFF3B1D01,
+0xFF4F1811,
+0xFF6D2026,
+0xFF521C36,
+0xFF434F89,
+0xFF013076,
+0xFF5083C4,
+0xFF659DD8,
+0xFF5998CD,
+0xFF589ACC,
+0xFF5998CD,
+0xFF5798CE,
+0xFF559AD5,
+0xFF559AD3,
+0xFF5495CB,
+0xFF599BCD,
+0xFF559CCA,
+0xFF5098CA,
+0xFF5698D2,
+0xFF5698D4,
+0xFF539AD2,
+0xFF539ACE,
+0xFF549ACE,
+0xFF549ACE,
+0xFF5499D2,
+0xFF5698D2,
+0xFF5699CE,
+0xFF5699CE,
+0xFF549ACE,
+0xFF549ACE,
+0xFF549ACE,
+0xFF5699CE,
+0xFF5699CE,
+0xFF5699CE,
+0xFF5699CE,
+0xFF5699CE,
+0xFF5699CE,
+0xFF5699CE,
+0xFF549ACE,
+0xFF549ACE,
+0xFF5699CE,
+0xFF5699CE,
+0xFF5699CE,
+0xFF5699CE,
+0xFF5699CE,
+0xFF5699CE,
+0xFF549ACE,
+0xFF549ACE,
+0xFF5499D0,
+0xFF549ACE,
+0xFF5699CE,
+0xFF5699CE,
+0xFF5699CE,
+0xFF5699CE,
+0xFF5499D0,
+0xFF549ACE,
+0xFF5798CE,
+0xFF5799CD,
+0xFF5699CE,
+0xFF5699CE,
+0xFF5699CE,
+0xFF5699CE,
+0xFF5699CE,
+0xFF5699CE,
+0xFF5699CE,
+0xFF5699CE,
+0xFF5699CE,
+0xFF5699CE,
+0xFF5699CE,
+0xFF5699CE,
+0xFF5699CE,
+0xFF5699CE,
+0xFF5699CE,
+0xFF5699CE,
+0xFF549ACE,
+0xFF549ACE,
+0xFF549ACE,
+0xFF549ACE,
+0xFF549ACE,
+0xFF549ACE,
+0xFF5699CE,
+0xFF5699CE,
+0xFF5699CE,
+0xFF5699CE,
+0xFF5699CE,
+0xFF5699CE,
+0xFF5699D0,
+0xFF5598CF,
+0xFF5697CF,
+0xFF5697CF,
+0xFF5596CE,
+0xFF5596CE,
+0xFF5596CE,
+0xFF5596CE,
+0xFF5497CE,
+0xFF5396CD,
+0xFF5396CD,
+0xFF5396CD,
+0xFF5396CD,
+0xFF5396CD,
+0xFF5396CD,
+0xFF5196CD,
+0xFF5294CE,
+0xFF5095CE,
+0xFF5294CE,
+0xFF5095CE,
+0xFF4F94CD,
+0xFF4F94CB,
+0xFF4F94CD,
+0xFF4E93CC,
+0xFF4E93CC,
+0xFF4D92CB,
+0xFF4D92CD,
+0xFF4D92CD,
+0xFF4D92CD,
+0xFF4F91CD,
+0xFF4F91CD,
+0xFF4F91CD,
+0xFF4E90CC,
+0xFF4D8FCB,
+0xFF4C8ECA,
+0xFF4C8ECA,
+0xFF4B8DC9,
+0xFF4B8DC9,
+0xFF4B8DC9,
+0xFF4B8DC9,
+0xFF4A8CC9,
+0xFF4A8CC9,
+0xFF4A8AC8,
+0xFF4A8AC8,
+0xFF4A8AC8,
+0xFF4A8AC8,
+0xFF4C89C8,
+0xFF4B88C7,
+0xFF4B88C7,
+0xFF4B88C7,
+0xFF4A87C6,
+0xFF4986C5,
+0xFF4C80BC,
+0xFF4C80BA,
+0xFF4E82BE,
+0xFF5084C0,
+0xFF5185C1,
+0xFF5286C2,
+0xFF5086C2,
+0xFF4F85C1,
+0xFF4D85C2,
+0xFF4D85C2,
+0xFF4B86C2,
+0xFF4B86C2,
+0xFF4B86C2,
+0xFF4B86C2,
+0xFF4A86C2,
+0xFF4A86C2,
+0xFF4A88C5,
+0xFF4888C5,
+0xFF4B89C6,
+0xFF4989C6,
+0xFF4A8AC7,
+0xFF4A8AC7,
+0xFF4C8AC7,
+0xFF4C8AC7,
+0xFF4D8BC8,
+0xFF4E8CC9,
+0xFF4E8CC9,
+0xFF4E8CC9,
+0xFF4E8CC9,
+0xFF4E8CC9,
+0xFF4E8CC9,
+0xFF4F8DCA,
+0xFF508CC8,
+0xFF518EC7,
+0xFF518EC7,
+0xFF518EC7,
+0xFF518EC7,
+0xFF5390C9,
+0xFF5694CD,
+0xFF5896CF,
+0xFF5091C9,
+0xFF4F90C8,
+0xFF5091C9,
+0xFF5192CA,
+0xFF5492CB,
+0xFF5293CB,
+0xFF5293CB,
+0xFF5394CC,
+0xFF5693C9,
+0xFF5B97CD,
+0xFF5F9BD1,
+0xFF5F9CD2,
+0xFF5D9AD0,
+0xFF5A97CD,
+0xFF5996CD,
+0xFF5998CE,
+0xFF5998CE,
+0xFF5798CE,
+0xFF5697CD,
+0xFF5596CC,
+0xFF5194CB,
+0xFF5093CA,
+0xFF5093CA,
+0xFF5194CB,
+0xFF4F95C9,
+0xFF4F95C9,
+0xFF5096CA,
+0xFF5096CA,
+0xFF5096CA,
+0xFF5096CA,
+0xFF5194C9,
+0xFF5194C9,
+0xFF5295CA,
+0xFF5295CA,
+0xFF5295CA,
+0xFF5096CA,
+0xFF5295CA,
+0xFF5096CA,
+0xFF5295CA,
+0xFF5197CB,
+0xFF5396CB,
+0xFF5197CB,
+0xFF5396CB,
+0xFF5197CB,
+0xFF5396CB,
+0xFF5197CB,
+0xFF5396CB,
+0xFF5197CB,
+0xFF5497CC,
+0xFF5396CB,
+0xFF5396CB,
+0xFF5396CB,
+0xFF5497CC,
+0xFF5497CC,
+0xFF5497CC,
+0xFF5396CB,
+0xFF5596CC,
+0xFF5497CC,
+0xFF5497CC,
+0xFF5497CC,
+0xFF5497CC,
+0xFF5497CC,
+0xFF5497CC,
+0xFF5497CC,
+0xFF5497CC,
+0xFF5497CC,
+0xFF5497CC,
+0xFF5598CD,
+0xFF5598CD,
+0xFF5497CC,
+0xFF5497CC,
+0xFF5497CC,
+0xFF5598CD,
+0xFF5598CD,
+0xFF5598CD,
+0xFF5598CD,
+0xFF5598CD,
+0xFF5598CD,
+0xFF5598CD,
+0xFF5598CD,
+0xFF5598CD,
+0xFF5598CD,
+0xFF5598CD,
+0xFF5598CD,
+0xFF5598CD,
+0xFF5598CD,
+0xFF5598CD,
+0xFF5598CD,
+0xFF5798CE,
+0xFF5798CE,
+0xFF5798CE,
+0xFF5699CE,
+0xFF5699D0,
+0xFF5699D0,
+0xFF5499D0,
+0xFF5499D0,
+0xFF5297CE,
+0xFF5398CF,
+0xFF5399CD,
+0xFF5399CD,
+0xFF5699CE,
+0xFF5598CC,
+0xFF589BD0,
+0xFF5799CD,
+0xFF5998CB,
+0xFF5C9ACD,
+0xFF5593C6,
+0xFF7CBAED,
+0xFF5995C9,
+0xFF5C9ACD,
+0xFF5796CB,
+0xFF5697CD,
+0xFF5798CE,
+0xFF5798CE,
+0xFF5699D0,
+0xFF5699D0,
+0xFF5699CE,
+0xFF5699CE,
+0xFF5699CE,
+0xFF5699CE,
+0xFF5798CE,
+0xFF5798CE,
+0xFF5699CE,
+0xFF5699CE,
+0xFF5499D0,
+0xFF539AD0,
+0xFF539ACE,
+0xFF539BCD,
+0xFF549ACD,
+0xFF5699CD,
+0xFF5497CB,
+0xFF5B9DD1,
+0xFF5A97CE,
+0xFF6095C9,
+0xFF6A95C0,
+0xFF607E86,
+0xFFCADBA7,
+0xFF616D1B,
+0xFF6E7D2C,
+0xFF748535,
+0xFF79863E,
+0xFF77723B,
+0xFF411701,
+0xFF4D1B1E,
+0xFF3D1E30,
+0xFF403C61,
+0xFF0C2965,
+0xFF5D8CD2,
+0xFF689ADF,
+0xFF5D98D4,
+0xFF569ACB,
+0xFF559CC8,
+0xFF5699CD,
+0xFF5699CE,
+0xFF5499D0,
+0xFF5499D0,
+0xFF5699CE,
+0xFF5699CD,
+0xFF559BCE,
+0xFF559BCF,
+0xFF5499D0,
+0xFF5499D0,
+0xFF559AD1,
+0xFF559BCF,
+0xFF579ACF,
+0xFF579ACF,
+0xFF579AD1,
+0xFF589BD0,
+0xFF5799CD,
+0xFF579ACE,
+0xFF549BD1,
+0xFF539CD1,
+0xFF549BD1,
+0xFF559BCF,
+0xFF559BCF,
+0xFF559BCF,
+0xFF559AD1,
+0xFF5499D0,
+0xFF5699CE,
+0xFF549ACE,
+0xFF549CCE,
+0xFF549CCE,
+0xFF559AD1,
+0xFF5699D0,
+0xFF5698CC,
+0xFF5B9DD1,
+0xFF5396CB,
+0xFF559BCF,
+0xFF569DD3,
+0xFF539AD0,
+0xFF549BD3,
+0xFF559CD2,
+0xFF5399CD,
+0xFF5399CD,
+0xFF559BCF,
+0xFF569BD2,
+0xFF5299D1,
+0xFF5299CF,
+0xFF5C9BD0,
+0xFF5A99CC,
+0xFF589ACE,
+0xFF579ACF,
+0xFF579ACF,
+0xFF579ACF,
+0xFF579ACF,
+0xFF579ACF,
+0xFF579ACF,
+0xFF579ACF,
+0xFF5699CE,
+0xFF579ACF,
+0xFF579ACF,
+0xFF579ACF,
+0xFF579ACF,
+0xFF5699CE,
+0xFF579ACF,
+0xFF579ACF,
+0xFF579ACF,
+0xFF579ACF,
+0xFF5699CE,
+0xFF5699CE,
+0xFF5699CE,
+0xFF5699CE,
+0xFF5699CE,
+0xFF5699CE,
+0xFF5699CE,
+0xFF5699CE,
+0xFF5699CE,
+0xFF5699CE,
+0xFF5699CE,
+0xFF5699CE,
+0xFF5699CE,
+0xFF5598CD,
+0xFF5598CD,
+0xFF5598CD,
+0xFF5598CD,
+0xFF5598CD,
+0xFF5598CD,
+0xFF5598CD,
+0xFF5497CC,
+0xFF5497CC,
+0xFF5596CC,
+0xFF5596CC,
+0xFF5596CC,
+0xFF5497CC,
+0xFF5596CE,
+0xFF5396CD,
+0xFF5495CD,
+0xFF5396CD,
+0xFF5095CC,
+0xFF5096CA,
+0xFF5095CC,
+0xFF5095CC,
+0xFF4F94CB,
+0xFF4F94CB,
+0xFF4D94CC,
+0xFF4D94CC,
+0xFF4C93CB,
+0xFF4D92CB,
+0xFF4D92CB,
+0xFF4D92CB,
+0xFF4D92CD,
+0xFF4C91CC,
+0xFF4B90CB,
+0xFF4A8FCA,
+0xFF4D8FCB,
+0xFF4C8ECA,
+0xFF4D8DCA,
+0xFF4D8DCA,
+0xFF4C8CC9,
+0xFF4C8CC9,
+0xFF4B8BC8,
+0xFF4B8BC8,
+0xFF4C8CC9,
+0xFF4C8CC9,
+0xFF4B8BC8,
+0xFF4B8BC8,
+0xFF4A8AC7,
+0xFF4989C6,
+0xFF4989C6,
+0xFF4989C6,
+0xFF4880BD,
+0xFF4981BE,
+0xFF4A82BF,
+0xFF4B83C0,
+0xFF4D85C2,
+0xFF4E86C3,
+0xFF4E86C3,
+0xFF4D85C2,
+0xFF4E86C3,
+0xFF4E86C3,
+0xFF4C87C3,
+0xFF4C87C3,
+0xFF4C87C3,
+0xFF4C87C3,
+0xFF4B87C3,
+0xFF4A88C3,
+0xFF4B89C6,
+0xFF4989C6,
+0xFF4989C6,
+0xFF4A8AC7,
+0xFF4A8AC7,
+0xFF4A8AC7,
+0xFF4D8BC8,
+0xFF4D8BC8,
+0xFF4D8BC8,
+0xFF4E8CC9,
+0xFF4E8CC9,
+0xFF4E8CC9,
+0xFF4E8CC9,
+0xFF4F8DCA,
+0xFF4F8DCA,
+0xFF508EC9,
+0xFF518EC7,
+0xFF518EC7,
+0xFF518EC7,
+0xFF518EC7,
+0xFF528FC8,
+0xFF5390C9,
+0xFF5593CC,
+0xFF5795CE,
+0xFF5293CB,
+0xFF5192CA,
+0xFF5091C9,
+0xFF5192CA,
+0xFF5192CA,
+0xFF5192CA,
+0xFF5194CB,
+0xFF5495CB,
+0xFF5693C9,
+0xFF5A96CA,
+0xFF5D99CD,
+0xFF5E9ACE,
+0xFF5B98CE,
+0xFF5996CC,
+0xFF5895CB,
+0xFF5895CB,
+0xFF5897CD,
+0xFF5796CC,
+0xFF5596CC,
+0xFF5495CB,
+0xFF5295CC,
+0xFF5295CC,
+0xFF5295CC,
+0xFF5295CC,
+0xFF5194C9,
+0xFF5096CA,
+0xFF5295CA,
+0xFF5096CA,
+0xFF5396CB,
+0xFF5396CB,
+0xFF5396CB,
+0xFF5396CB,
+0xFF5396CB,
+0xFF5396CB,
+0xFF5396CB,
+0xFF5396CB,
+0xFF5396CB,
+0xFF5497CC,
+0xFF5497CC,
+0xFF5497CC,
+0xFF5497CC,
+0xFF5497CC,
+0xFF5497CC,
+0xFF5497CC,
+0xFF5497CC,
+0xFF5497CC,
+0xFF5497CC,
+0xFF5497CC,
+0xFF5497CC,
+0xFF5497CC,
+0xFF5497CC,
+0xFF5497CC,
+0xFF5497CC,
+0xFF5598CD,
+0xFF5497CC,
+0xFF5497CC,
+0xFF5596CC,
+0xFF5596CC,
+0xFF5497CC,
+0xFF5497CC,
+0xFF5497CC,
+0xFF5598CD,
+0xFF5598CD,
+0xFF5598CD,
+0xFF5497CC,
+0xFF5598CD,
+0xFF5598CD,
+0xFF5598CD,
+0xFF5598CD,
+0xFF5598CD,
+0xFF5598CD,
+0xFF5598CD,
+0xFF5598CD,
+0xFF5598CD,
+0xFF5598CD,
+0xFF5598CD,
+0xFF5598CD,
+0xFF5598CD,
+0xFF5598CD,
+0xFF5598CD,
+0xFF5598CD,
+0xFF5598CD,
+0xFF5699CE,
+0xFF5699CE,
+0xFF5699CE,
+0xFF5699CE,
+0xFF5699CE,
+0xFF5699CE,
+0xFF5798CE,
+0xFF5798CE,
+0xFF5798CE,
+0xFF5699CE,
+0xFF5699D0,
+0xFF5699D0,
+0xFF5499D0,
+0xFF5499D0,
+0xFF559AD1,
+0xFF5398CF,
+0xFF589ED2,
+0xFF549ACE,
+0xFF579ACE,
+0xFF5699CD,
+0xFF5698CC,
+0xFF5897CA,
+0xFF5997C8,
+0xFF5391C0,
+0xFF7BB9EA,
+0xFF609FD2,
+0xFF5695CA,
+0xFF5897CC,
+0xFF5A99CF,
+0xFF5899CF,
+0xFF5798D0,
+0xFF5699D0,
+0xFF5798D0,
+0xFF5699D0,
+0xFF579ACF,
+0xFF579ACF,
+0xFF579ACF,
+0xFF579ACF,
+0xFF579ACF,
+0xFF579ACF,
+0xFF579ACF,
+0xFF579ACF,
+0xFF559AD1,
+0xFF559AD1,
+0xFF549BCF,
+0xFF549BCF,
+0xFF549BCF,
+0xFF549BCF,
+0xFF5699CD,
+0xFF5A9CD0,
+0xFF5A96CA,
+0xFF5C95CA,
+0xFF6196CA,
+0xFF5E879B,
+0xFFC4D5A8,
+0xFF666F20,
+0xFF768532,
+0xFF748233,
+0xFF838846,
+0xFF4D3F12,
+0xFF451A0A,
+0xFF452028,
+0xFF171C39,
+0xFF1A3967,
+0xFF6791CB,
+0xFF6598D9,
+0xFF5891D4,
+0xFF5A9AD7,
+0xFF569DCB,
+0xFF539CC7,
+0xFF559DCF,
+0xFF569CD0,
+0xFF569CD0,
+0xFF569CD0,
+0xFF569CD0,
+0xFF569CD0,
+0xFF569CD0,
+0xFF569CD0,
+0xFF559BCF,
+0xFF559BCF,
+0xFF579ACF,
+0xFF579ACF,
+0xFF579ACF,
+0xFF579ACF,
+0xFF579ACF,
+0xFF579ACE,
+0xFF579ACE,
+0xFF579ACE,
+0xFF549BCF,
+0xFF559CD2,
+0xFF559CD2,
+0xFF559CD2,
+0xFF569CD0,
+0xFF559BCF,
+0xFF559BCF,
+0xFF559BCF,
+0xFF579ACF,
+0xFF579ACE,
+0xFF569CCF,
+0xFF569CCF,
+0xFF559BCF,
+0xFF559AD1,
+0xFF5DA0D5,
+0xFF5396CA,
+0xFF5C9FD3,
+0xFF589BD0,
+0xFF559AD1,
+0xFF559CD2,
+0xFF569DD3,
+0xFF5197CB,
+0xFF589CCD,
+0xFF5C9ED0,
+0xFF579ACE,
+0xFF5097CD,
+0xFF549DD4,
+0xFF579ED6,
+0xFF5799CD,
+0xFF5998CB,
+0xFF579ACE,
+0xFF579ACF,
+0xFF579ACF,
+0xFF579ACF,
+0xFF579ACF,
+0xFF579ACF,
+0xFF579ACF,
+0xFF579ACF,
+0xFF579ACF,
+0xFF579ACF,
+0xFF579ACF,
+0xFF579ACF,
+0xFF579ACF,
+0xFF579ACF,
+0xFF579ACF,
+0xFF579ACF,
+0xFF579ACF,
+0xFF579ACF,
+0xFF579ACF,
+0xFF579ACF,
+0xFF579ACF,
+0xFF579ACF,
+0xFF579ACF,
+0xFF579ACF,
+0xFF579ACF,
+0xFF579ACF,
+0xFF5699CE,
+0xFF579ACF,
+0xFF579ACF,
+0xFF579ACF,
+0xFF5699CE,
+0xFF5699CE,
+0xFF5699CE,
+0xFF5699CE,
+0xFF5699CE,
+0xFF5699CE,
+0xFF5598CD,
+0xFF5598CD,
+0xFF5598CD,
+0xFF5598CD,
+0xFF5596CC,
+0xFF5697CD,
+0xFF5697CD,
+0xFF5697CD,
+0xFF5697CF,
+0xFF5596CE,
+0xFF5596CE,
+0xFF5396CD,
+0xFF5396CB,
+0xFF5197CB,
+0xFF5096CA,
+0xFF5096CA,
+0xFF5095CC,
+0xFF5095CC,
+0xFF4E95CB,
+0xFF4E95CB,
+0xFF4D94CC,
+0xFF4D94CC,
+0xFF4D92CB,
+0xFF4D92CB,
+0xFF4D92CD,
+0xFF4D92CD,
+0xFF4C91CC,
+0xFF4B90CB,
+0xFF4D8FCB,
+0xFF4D8FCB,
+0xFF4E8ECB,
+0xFF4D8DCA,
+0xFF4D8DCA,
+0xFF4D8DCA,
+0xFF4C8CC9,
+0xFF4C8CC9,
+0xFF4C8CC9,
+0xFF4C8CC9,
+0xFF4B8BC8,
+0xFF4B8BC8,
+0xFF4B8BC8,
+0xFF4A8AC7,
+0xFF4A8AC7,
+0xFF4A8AC7,
+0xFF4981BE,
+0xFF4981BE,
+0xFF4A82BF,
+0xFF4B83C0,
+0xFF4C84C1,
+0xFF4D85C2,
+0xFF4D85C2,
+0xFF4D85C2,
+0xFF4D85C2,
+0xFF4D85C2,
+0xFF4C87C3,
+0xFF4C87C3,
+0xFF4C88C4,
+0xFF4C88C4,
+0xFF4C88C4,
+0xFF4B89C4,
+0xFF4C8AC7,
+0xFF4A8AC7,
+0xFF4C8AC7,
+0xFF4D8BC8,
+0xFF4D8BC8,
+0xFF4D8BC8,
+0xFF4E8CC9,
+0xFF4E8CC9,
+0xFF4E8CC9,
+0xFF4E8CC9,
+0xFF4F8DCA,
+0xFF4F8DCA,
+0xFF4F8DC8,
+0xFF508EC9,
+0xFF508EC9,
+0xFF518FCA,
+0xFF508EC7,
+0xFF518FC8,
+0xFF518FC8,
+0xFF518FC8,
+0xFF5290C9,
+0xFF5391CA,
+0xFF5492CB,
+0xFF5694CD,
+0xFF5495CD,
+0xFF5293CB,
+0xFF5192CA,
+0xFF5192CA,
+0xFF5192CA,
+0xFF5192CA,
+0xFF5293CB,
+0xFF5594CA,
+0xFF5693C9,
+0xFF5995CB,
+0xFF5A97CD,
+0xFF5A97CD,
+0xFF5A97CD,
+0xFF5996CC,
+0xFF5796CB,
+0xFF5695CA,
+0xFF5796CC,
+0xFF5695CB,
+0xFF5495CB,
+0xFF5495CB,
+0xFF5495CB,
+0xFF5596CC,
+0xFF5497CE,
+0xFF5497CE,
+0xFF5396CB,
+0xFF5396CB,
+0xFF5596CC,
+0xFF5497CC,
+0xFF5596CC,
+0xFF5596CC,
+0xFF5495CB,
+0xFF5495CB,
+0xFF5697CD,
+0xFF5697CD,
+0xFF5697CD,
+0xFF5697CD,
+0xFF5697CD,
+0xFF5697CD,
+0xFF5697CD,
+0xFF5697CD,
+0xFF5596CC,
+0xFF5596CC,
+0xFF5596CC,
+0xFF5596CC,
+0xFF5596CC,
+0xFF5596CC,
+0xFF5596CC,
+0xFF5596CC,
+0xFF5697CD,
+0xFF5697CD,
+0xFF5697CD,
+0xFF5697CD,
+0xFF5697CD,
+0xFF5697CD,
+0xFF5697CD,
+0xFF5697CD,
+0xFF5697CD,
+0xFF5697CD,
+0xFF5697CD,
+0xFF5697CD,
+0xFF5798CE,
+0xFF5798CE,
+0xFF5798CE,
+0xFF5798CE,
+0xFF5798CE,
+0xFF5798CE,
+0xFF5798CE,
+0xFF5697CD,
+0xFF5699CE,
+0xFF5699CE,
+0xFF5699CE,
+0xFF5699CE,
+0xFF5699CE,
+0xFF5699CE,
+0xFF5699CE,
+0xFF5699CE,
+0xFF5699CE,
+0xFF5699CE,
+0xFF5699CE,
+0xFF5699CE,
+0xFF5699CE,
+0xFF5699CE,
+0xFF579ACF,
+0xFF579ACF,
+0xFF579ACF,
+0xFF579ACF,
+0xFF579ACF,
+0xFF579ACF,
+0xFF5899CF,
+0xFF5899CF,
+0xFF5899CF,
+0xFF579ACF,
+0xFF579ACF,
+0xFF559BCF,
+0xFF559BCF,
+0xFF559BCF,
+0xFF549ACE,
+0xFF579DD1,
+0xFF5396CB,
+0xFF5497CC,
+0xFF5799CD,
+0xFF5A9CD0,
+0xFF599BCD,
+0xFF589ACC,
+0xFF5999C9,
+0xFF7DBDED,
+0xFF5C9BCE,
+0xFF5496C8,
+0xFF589ACE,
+0xFF5B9DD1,
+0xFF5899CF,
+0xFF579ACF,
+0xFF579AD1,
+0xFF559AD1,
+0xFF579ACF,
+0xFF559BCF,
+0xFF569CD0,
+0xFF569CD0,
+0xFF569CCF,
+0xFF569CCF,
+0xFF589BD0,
+0xFF589BD0,
+0xFF589BD0,
+0xFF589BD0,
+0xFF569CD0,
+0xFF569CD0,
+0xFF559CD0,
+0xFF559CD0,
+0xFF549DD0,
+0xFF559CD0,
+0xFF559DCF,
+0xFF589BCF,
+0xFF5799CB,
+0xFF5B99CC,
+0xFF5F99CB,
+0xFF6794A9,
+0xFF9CB18A,
+0xFF757F36,
+0xFF748630,
+0xFF788132,
+0xFF8C7F48,
+0xFF331900,
+0xFF44211B,
+0xFF241625,
+0xFF092648,
+0xFF71A5D4,
+0xFF6398CE,
+0xFF5A95CF,
+0xFF5CA0DD,
+0xFF539BD5,
+0xFF539CC9,
+0xFF559EC9,
+0xFF559DCF,
+0xFF559CD0,
+0xFF559CD0,
+0xFF559CD0,
+0xFF559CD0,
+0xFF559CD0,
+0xFF559CD0,
+0xFF569DD1,
+0xFF569CD0,
+0xFF569CD0,
+0xFF569CD0,
+0xFF569CD0,
+0xFF569CCF,
+0xFF569CCF,
+0xFF569CCF,
+0xFF569CCF,
+0xFF549DD0,
+0xFF559CD0,
+0xFF589BCF,
+0xFF589BCF,
+0xFF559CD2,
+0xFF549DD2,
+0xFF559CD2,
+0xFF559CD0,
+0xFF559DCF,
+0xFF559DCD,
+0xFF569CCD,
+0xFF589BCF,
+0xFF5C9BD1,
+0xFF5A9BD1,
+0xFF559DCF,
+0xFF529ED0,
+0xFF519ACF,
+0xFF59A0D6,
+0xFF5598CC,
+0xFF5496C8,
+0xFF5A9DD1,
+0xFF599CD0,
+0xFF5399CC,
+0xFF599BCB,
+0xFF5895C1,
+0xFF5A97C3,
+0xFF5B9DCF,
+0xFF559CD0,
+0xFF559ED3,
+0xFF559ED3,
+0xFF5399CD,
+0xFF569CD0,
+0xFF569CD0,
+0xFF569CD0,
+0xFF569CD0,
+0xFF569CD0,
+0xFF569CD0,
+0xFF569CD0,
+0xFF569CD0,
+0xFF569CD0,
+0xFF569CD0,
+0xFF569CD0,
+0xFF569CD0,
+0xFF569CD0,
+0xFF569CD0,
+0xFF569CD0,
+0xFF569CD0,
+0xFF569CD0,
+0xFF569CD0,
+0xFF569CD0,
+0xFF569CD0,
+0xFF569CD0,
+0xFF569CD0,
+0xFF569CD0,
+0xFF569CD0,
+0xFF569CD0,
+0xFF569CD0,
+0xFF569CD0,
+0xFF569CD0,
+0xFF569CD0,
+0xFF569CD0,
+0xFF569CD0,
+0xFF559BCF,
+0xFF559BCF,
+0xFF579ACF,
+0xFF579ACF,
+0xFF579ACF,
+0xFF579ACF,
+0xFF579ACF,
+0xFF5699CE,
+0xFF5699CE,
+0xFF5699CE,
+0xFF5699CE,
+0xFF5699CE,
+0xFF5699CE,
+0xFF5699CE,
+0xFF5598CF,
+0xFF5598CF,
+0xFF5598CF,
+0xFF5497CE,
+0xFF5497CC,
+0xFF5497CC,
+0xFF5298CC,
+0xFF5197CB,
+0xFF5196CD,
+0xFF5196CD,
+0xFF5095CC,
+0xFF5095CC,
+0xFF4F94CB,
+0xFF4F94CB,
+0xFF4E93CC,
+0xFF4E93CC,
+0xFF4E93CC,
+0xFF4E93CC,
+0xFF4F91CB,
+0xFF4E90CA,
+0xFF4E90CC,
+0xFF4E90CC,
+0xFF4E90CC,
+0xFF4E90CC,
+0xFF4D8FCB,
+0xFF4D8FCB,
+0xFF4D8DCA,
+0xFF4D8DCA,
+0xFF4C8CC9,
+0xFF4C8CC9,
+0xFF4C8CC9,
+0xFF4C8CC9,
+0xFF4B8BC8,
+0xFF4B8BC8,
+0xFF4B8BC8,
+0xFF4B8BC8,
+0xFF4B83C0,
+0xFF4B83C0,
+0xFF4B83C0,
+0xFF4C84C1,
+0xFF4C84C1,
+0xFF4D85C2,
+0xFF4D85C2,
+0xFF4D85C2,
+0xFF4D85C2,
+0xFF4B86C2,
+0xFF4C87C3,
+0xFF4C87C3,
+0xFF4C88C4,
+0xFF4C88C4,
+0xFF4C88C4,
+0xFF4B89C4,
+0xFF4C8AC7,
+0xFF4A8AC7,
+0xFF4D8BC8,
+0xFF4D8BC8,
+0xFF4E8CC9,
+0xFF4E8CC9,
+0xFF4E8CC9,
+0xFF4F8DCA,
+0xFF4E8CC9,
+0xFF4F8DCA,
+0xFF4F8DCA,
+0xFF508ECB,
+0xFF508EC9,
+0xFF508EC9,
+0xFF518FCA,
+0xFF5290CB,
+0xFF518FC8,
+0xFF5290C9,
+0xFF5290C9,
+0xFF5391CA,
+0xFF5391CA,
+0xFF5391CA,
+0xFF5492CB,
+0xFF5593CC,
+0xFF5293CB,
+0xFF5293CB,
+0xFF5394CC,
+0xFF5394CC,
+0xFF5394CC,
+0xFF5293CB,
+0xFF5293CB,
+0xFF5493C9,
+0xFF5794CB,
+0xFF5894CA,
+0xFF5895CB,
+0xFF5996CC,
+0xFF5996CC,
+0xFF5895CB,
+0xFF5695CA,
+0xFF5695CA,
+0xFF5796CC,
+0xFF5796CC,
+0xFF5596CC,
+0xFF5596CC,
+0xFF5697CD,
+0xFF5697CD,
+0xFF5598CF,
+0xFF5598CF,
+0xFF5596CC,
+0xFF5697CD,
+0xFF5697CD,
+0xFF5697CD,
+0xFF5596CC,
+0xFF5596CC,
+0xFF5596CC,
+0xFF5596CC,
+0xFF5697CD,
+0xFF5697CD,
+0xFF5697CD,
+0xFF5697CD,
+0xFF5697CD,
+0xFF5697CD,
+0xFF5697CD,
+0xFF5697CD,
+0xFF5697CD,
+0xFF5697CD,
+0xFF5697CD,
+0xFF5697CD,
+0xFF5697CD,
+0xFF5697CD,
+0xFF5697CD,
+0xFF5697CD,
+0xFF5798CE,
+0xFF5798CE,
+0xFF5798CE,
+0xFF5798CE,
+0xFF5798CE,
+0xFF5798CE,
+0xFF5798CE,
+0xFF5798CE,
+0xFF5798CE,
+0xFF5798CE,
+0xFF5798CE,
+0xFF5798CE,
+0xFF5798CE,
+0xFF5798CE,
+0xFF5798CE,
+0xFF5798CE,
+0xFF5899CF,
+0xFF5798CE,
+0xFF5798CE,
+0xFF5798CE,
+0xFF5699CE,
+0xFF5699CE,
+0xFF579ACF,
+0xFF579ACF,
+0xFF5699CE,
+0xFF5699CE,
+0xFF5699CE,
+0xFF579ACF,
+0xFF579ACF,
+0xFF579ACF,
+0xFF579ACF,
+0xFF579ACF,
+0xFF579ACF,
+0xFF579ACF,
+0xFF579ACF,
+0xFF579ACF,
+0xFF579ACF,
+0xFF579ACF,
+0xFF579ACF,
+0xFF579ACF,
+0xFF5899CF,
+0xFF5899CF,
+0xFF579ACF,
+0xFF579ACF,
+0xFF559BCF,
+0xFF559BCF,
+0xFF559BCF,
+0xFF559BCF,
+0xFF589ED2,
+0xFF549ACE,
+0xFF599CD1,
+0xFF60A3D7,
+0xFF5B9DD1,
+0xFF5395C9,
+0xFF599BCD,
+0xFF5698CA,
+0xFF75B7E7,
+0xFF5799C9,
+0xFF5698CA,
+0xFF5A9ECF,
+0xFF599CD0,
+0xFF549ACD,
+0xFF599CD1,
+0xFF569CD0,
+0xFF569BD2,
+0xFF569BD2,
+0xFF569CD0,
+0xFF569CD0,
+0xFF569CD0,
+0xFF569CD0,
+0xFF569CCF,
+0xFF569CCF,
+0xFF599CD1,
+0xFF599CD1,
+0xFF599CD1,
+0xFF589BD0,
+0xFF569CD0,
+0xFF569CD0,
+0xFF559CD0,
+0xFF559CD0,
+0xFF559ED1,
+0xFF539CCF,
+0xFF56A0D1,
+0xFF559DCF,
+0xFF569CCD,
+0xFF5B9DCF,
+0xFF5B9ACD,
+0xFF6E9EB5,
+0xFF6E8568,
+0xFF9BA767,
+0xFF6A7B2B,
+0xFF81873D,
+0xFF685127,
+0xFF3A1D0D,
+0xFF25161B,
+0xFF131E34,
+0xFF7BA8CF,
+0xFF5A9ACA,
+0xFF5E9CCF,
+0xFF5B9CD2,
+0xFF529DD4,
+0xFF529FD5,
+0xFF559FCE,
+0xFF57A0CD,
+0xFF569ED0,
+0xFF569DD1,
+0xFF569DD1,
+0xFF569DD1,
+0xFF569DD1,
+0xFF569DD1,
+0xFF569DD1,
+0xFF569DD1,
+0xFF579DD1,
+0xFF579DD1,
+0xFF579DD1,
+0xFF579DD1,
+0xFF579DD0,
+0xFF579DD0,
+0xFF579DD0,
+0xFF569ED0,
+0xFF539FD3,
+0xFF559ED1,
+0xFF599CD0,
+0xFF599CD0,
+0xFF569DD1,
+0xFF559ED3,
+0xFF569DD3,
+0xFF569DD1,
+0xFF579DCE,
+0xFF579ECC,
+0xFF579DCE,
+0xFF599DCE,
+0xFF5D9CD2,
+0xFF5B9CD2,
+0xFF569ED0,
+0xFF539FD0,
+0xFF519DD1,
+0xFF57A0D5,
+0xFF5CA2D6,
+0xFF599DCE,
+0xFF5E9ECE,
+0xFF5C9BC7,
+0xFF5B96C0,
+0xFF7EB8E0,
+0xFF93CDF5,
+0xFF619ECA,
+0xFF5296C7,
+0xFF589FD3,
+0xFF59A0D4,
+0xFF579ED2,
+0xFF539CD1,
+0xFF57A0D5,
+0xFF569DD1,
+0xFF579DD1,
+0xFF579DD1,
+0xFF579DD1,
+0xFF579DD1,
+0xFF579DD1,
+0xFF579DD1,
+0xFF579DD1,
+0xFF579DD1,
+0xFF579DD1,
+0xFF589ED2,
+0xFF589ED2,
+0xFF579DD1,
+0xFF579DD1,
+0xFF579DD1,
+0xFF589ED2,
+0xFF579DD1,
+0xFF579DD1,
+0xFF579DD1,
+0xFF579DD1,
+0xFF579DD1,
+0xFF579DD1,
+0xFF579DD1,
+0xFF579DD1,
+0xFF579DD1,
+0xFF579DD1,
+0xFF579DD1,
+0xFF579DD1,
+0xFF579DD1,
+0xFF569CD0,
+0xFF569CD0,
+0xFF569CD0,
+0xFF589BD0,
+0xFF589BD0,
+0xFF589BD0,
+0xFF589BD0,
+0xFF579ACF,
+0xFF579ACF,
+0xFF579ACF,
+0xFF579ACF,
+0xFF579ACF,
+0xFF5699CE,
+0xFF5699CE,
+0xFF5699CE,
+0xFF5699D0,
+0xFF5699D0,
+0xFF5598CF,
+0xFF5598CF,
+0xFF5598CD,
+0xFF5598CD,
+0xFF5298CC,
+0xFF5298CC,
+0xFF5297CE,
+0xFF5196CD,
+0xFF5196CD,
+0xFF5196CD,
+0xFF5095CC,
+0xFF5095CC,
+0xFF4F94CD,
+0xFF4F94CD,
+0xFF4F94CD,
+0xFF4F94CD,
+0xFF5092CC,
+0xFF4F91CB,
+0xFF4F91CD,
+0xFF4F91CD,
+0xFF4F91CD,
+0xFF4E90CC,
+0xFF4E90CC,
+0xFF4D8FCB,
+0xFF4E8ECB,
+0xFF4E8ECB,
+0xFF4C8CC9,
+0xFF4C8CC9,
+0xFF4C8CC9,
+0xFF4C8CC9,
+0xFF4C8CC9,
+0xFF4C8CC9,
+0xFF4B8BC8,
+0xFF4B8BC8,
+0xFF4D85C2,
+0xFF4D85C2,
+0xFF4D85C2,
+0xFF4D85C2,
+0xFF4D85C2,
+0xFF4D85C2,
+0xFF4E86C3,
+0xFF4E86C3,
+0xFF4C87C3,
+0xFF4C87C3,
+0xFF4D88C4,
+0xFF4C88C4,
+0xFF4D89C5,
+0xFF4D89C5,
+0xFF4D8BC6,
+0xFF4D8BC6,
+0xFF4D8BC8,
+0xFF4D8BC8,
+0xFF4D8BC8,
+0xFF4E8CC9,
+0xFF4E8CC7,
+0xFF4F8DC8,
+0xFF4F8DC8,
+0xFF508EC9,
+0xFF4F8DC8,
+0xFF508EC9,
+0xFF508EC9,
+0xFF518FCA,
+0xFF518FCA,
+0xFF518FCA,
+0xFF5091CB,
+0xFF5192CC,
+0xFF5091C9,
+0xFF5192CA,
+0xFF5192CA,
+0xFF5293CB,
+0xFF5293CB,
+0xFF5293CB,
+0xFF5293CB,
+0xFF5293CB,
+0xFF5293CB,
+0xFF5293CB,
+0xFF5394CA,
+0xFF5394CA,
+0xFF5394CA,
+0xFF5394CA,
+0xFF5394CA,
+0xFF5493C9,
+0xFF5895CC,
+0xFF5895CC,
+0xFF5895CC,
+0xFF5895CC,
+0xFF5897CD,
+0xFF5897CD,
+0xFF5796CC,
+0xFF5695CB,
+0xFF5796CC,
+0xFF5897CD,
+0xFF5798CE,
+0xFF5697CD,
+0xFF5697CD,
+0xFF5596CC,
+0xFF5697CD,
+0xFF5798CE,
+0xFF5796CC,
+0xFF5897CD,
+0xFF5998CE,
+0xFF5998CE,
+0xFF5897CD,
+0xFF5897CD,
+0xFF5897CD,
+0xFF5897CD,
+0xFF5998CE,
+0xFF5998CE,
+0xFF5998CE,
+0xFF5897CD,
+0xFF5897CD,
+0xFF5897CD,
+0xFF5998CE,
+0xFF5998CE,
+0xFF5798CE,
+0xFF5798CE,
+0xFF5798CE,
+0xFF5798CE,
+0xFF5798CE,
+0xFF5798CE,
+0xFF5798CE,
+0xFF5798CE,
+0xFF5798CE,
+0xFF5798CE,
+0xFF5798CE,
+0xFF5798CE,
+0xFF5798CE,
+0xFF5798CE,
+0xFF5798CE,
+0xFF5798CE,
+0xFF5798CE,
+0xFF5798CE,
+0xFF5798CE,
+0xFF5798CE,
+0xFF5899CF,
+0xFF5899CF,
+0xFF5899CF,
+0xFF5899CF,
+0xFF5899CF,
+0xFF5899CF,
+0xFF5798CE,
+0xFF5798CE,
+0xFF5798CE,
+0xFF5899CF,
+0xFF5899CF,
+0xFF5899CF,
+0xFF579ACF,
+0xFF579ACF,
+0xFF579ACF,
+0xFF579ACF,
+0xFF579ACF,
+0xFF589BD0,
+0xFF589BD0,
+0xFF589BD0,
+0xFF579ACF,
+0xFF589BD0,
+0xFF589BD0,
+0xFF589BD0,
+0xFF589BD0,
+0xFF589BD0,
+0xFF589BD0,
+0xFF589BD0,
+0xFF589BD0,
+0xFF589BD0,
+0xFF589BD0,
+0xFF589BD0,
+0xFF569CD0,
+0xFF569CD0,
+0xFF569CD0,
+0xFF569CD0,
+0xFF569CCF,
+0xFF579DD0,
+0xFF5598CC,
+0xFF5497CB,
+0xFF5799CD,
+0xFF5D9FD1,
+0xFF5799CB,
+0xFF7BBDEF,
+0xFF5B9FD0,
+0xFF599DCE,
+0xFF5B9ED2,
+0xFF589ED1,
+0xFF5399CC,
+0xFF58A0D2,
+0xFF579DD1,
+0xFF569DD1,
+0xFF569DD1,
+0xFF569DD1,
+0xFF569DD1,
+0xFF569DD1,
+0xFF569ED0,
+0xFF569ED0,
+0xFF569ED0,
+0xFF569ED0,
+0xFF579DD0,
+0xFF579DD0,
+0xFF579DD0,
+0xFF579DD0,
+0xFF579DD1,
+0xFF579DD1,
+0xFF569DD1,
+0xFF569DD1,
+0xFF56A0D1,
+0xFF549ECF,
+0xFF57A1D2,
+0xFF559FD0,
+0xFF579FD1,
+0xFF599FD0,
+0xFF589CCD,
+0xFF6CA2BE,
+0xFF556D5F,
+0xFF9EAA7C,
+0xFF707C3A,
+0xFF848549,
+0xFF3B230B,
+0xFF372325,
+0xFF142132,
+0xFF80A7C6,
+0xFF6096C4,
+0xFF5B9DCF,
+0xFF559BCE,
+0xFF59A2D5,
+0xFF539FD1,
+0xFF509CCE,
+0xFF52A0D0,
+0xFF54A1CF,
+0xFF569FD2,
+0xFF579ED2,
+0xFF579FD1,
+0xFF579FD1,
+0xFF579FD1,
+0xFF579FD1,
+0xFF579FD1,
+0xFF58A0D2,
+0xFF579FD1,
+0xFF579FD1,
+0xFF579FD1,
+0xFF579FD1,
+0xFF589ED1,
+0xFF589ED1,
+0xFF589ED1,
+0xFF579FD1,
+0xFF569FD4,
+0xFF569FD2,
+0xFF589ED1,
+0xFF589ECF,
+0xFF579FD1,
+0xFF579ED2,
+0xFF569FD2,
+0xFF579FD1,
+0xFF5A9ECD,
+0xFF5B9ECB,
+0xFF5B9DCD,
+0xFF5A9ECF,
+0xFF589ED2,
+0xFF589ED1,
+0xFF589ECF,
+0xFF589ECF,
+0xFF59A1D3,
+0xFF559ED1,
+0xFF4F98CF,
+0xFF589FD3,
+0xFF5D9DCB,
+0xFF5E96BB,
+0xFF8AB3CF,
+0xFFD8FFFF,
+0xFF69A3CB,
+0xFF5698C8,
+0xFF5BA2D6,
+0xFF589FD3,
+0xFF5397C8,
+0xFF5DA1D2,
+0xFF59A2D7,
+0xFF519CD3,
+0xFF559ED1,
+0xFF569ED0,
+0xFF569ED0,
+0xFF569ED0,
+0xFF569ED0,
+0xFF569ED0,
+0xFF569ED0,
+0xFF569ED0,
+0xFF579FD1,
+0xFF579FD1,
+0xFF589ED1,
+0xFF589ED1,
+0xFF589ED1,
+0xFF589ED1,
+0xFF589ED1,
+0xFF589ED1,
+0xFF5A9DD1,
+0xFF5A9DD1,
+0xFF5A9DD1,
+0xFF5A9DD1,
+0xFF5A9DD1,
+0xFF599CD0,
+0xFF599CD0,
+0xFF599CD0,
+0xFF599CD0,
+0xFF599CD0,
+0xFF599CD0,
+0xFF599CD0,
+0xFF599CD0,
+0xFF599CD0,
+0xFF599CD0,
+0xFF599CD0,
+0xFF579DD1,
+0xFF579DD1,
+0xFF569CD0,
+0xFF569CD0,
+0xFF569CD0,
+0xFF569CD0,
+0xFF569CD0,
+0xFF569CD0,
+0xFF579ACF,
+0xFF579ACF,
+0xFF579ACF,
+0xFF579ACF,
+0xFF5699CE,
+0xFF5699CE,
+0xFF5699D0,
+0xFF5699D0,
+0xFF5598CD,
+0xFF5598CD,
+0xFF5598CD,
+0xFF5598CD,
+0xFF5598CF,
+0xFF5497CE,
+0xFF5297CE,
+0xFF5297CE,
+0xFF5196CD,
+0xFF5196CD,
+0xFF5295CC,
+0xFF5295CC,
+0xFF5194CB,
+0xFF5194CB,
+0xFF5194CB,
+0xFF5093CA,
+0xFF5092CC,
+0xFF5092CC,
+0xFF5092CC,
+0xFF4F91CB,
+0xFF4F91CB,
+0xFF4E90CA,
+0xFF4F90CA,
+0xFF4F90CA,
+0xFF4D8DCA,
+0xFF4D8DCA,
+0xFF4D8DCA,
+0xFF4D8DCA,
+0xFF4E8CC9,
+0xFF4E8CC9,
+0xFF4E8CC9,
+0xFF4E8CC9,
+0xFF4D85C2,
+0xFF4D85C2,
+0xFF4E86C3,
+0xFF4E86C3,
+0xFF4E86C3,
+0xFF4E86C3,
+0xFF4E86C3,
+0xFF4F87C4,
+0xFF4D88C4,
+0xFF4D88C4,
+0xFF4C88C4,
+0xFF4D89C5,
+0xFF4D89C5,
+0xFF4E8AC6,
+0xFF4D8BC6,
+0xFF4D8BC6,
+0xFF4E8CC9,
+0xFF4E8CC9,
+0xFF4E8CC9,
+0xFF4E8CC9,
+0xFF4F8DC8,
+0xFF4F8DC8,
+0xFF508EC9,
+0xFF518FCA,
+0xFF518FCA,
+0xFF518FCA,
+0xFF5290CB,
+0xFF5290CB,
+0xFF5290CB,
+0xFF5290CB,
+0xFF5192CC,
+0xFF5293CD,
+0xFF5293CB,
+0xFF5293CB,
+0xFF5293CB,
+0xFF5394CC,
+0xFF5394CC,
+0xFF5394CC,
+0xFF5394CC,
+0xFF5394CC,
+0xFF5394CC,
+0xFF5495CD,
+0xFF5394CA,
+0xFF5394CA,
+0xFF5394CA,
+0xFF5495CB,
+0xFF5596CC,
+0xFF5596CC,
+0xFF5897CD,
+0xFF5996CD,
+0xFF5895CC,
+0xFF5996CD,
+0xFF5998CE,
+0xFF5998CE,
+0xFF5897CD,
+0xFF5897CD,
+0xFF5796CC,
+0xFF5998CE,
+0xFF5899CF,
+0xFF5798CE,
+0xFF5697CD,
+0xFF5596CC,
+0xFF5697CD,
+0xFF5798CE,
+0xFF5796CC,
+0xFF5897CD,
+0xFF5998CE,
+0xFF5998CE,
+0xFF5998CE,
+0xFF5998CE,
+0xFF5A99CF,
+0xFF5A99CF,
+0xFF5A99CF,
+0xFF5A99CF,
+0xFF5A99CF,
+0xFF5998CE,
+0xFF5998CE,
+0xFF5998CE,
+0xFF5A99CF,
+0xFF5A99CF,
+0xFF5899CF,
+0xFF5899CF,
+0xFF5899CF,
+0xFF5899CF,
+0xFF5899CF,
+0xFF5899CF,
+0xFF5899CF,
+0xFF5899CF,
+0xFF5899CF,
+0xFF5899CF,
+0xFF5899CF,
+0xFF5899CF,
+0xFF5899CF,
+0xFF5899CF,
+0xFF5899CF,
+0xFF5899CF,
+0xFF5798CE,
+0xFF5798CE,
+0xFF5798CE,
+0xFF5899CF,
+0xFF5899CF,
+0xFF5899CF,
+0xFF5899CF,
+0xFF5899CF,
+0xFF5899CF,
+0xFF5899CF,
+0xFF5899CF,
+0xFF5899CF,
+0xFF5899CF,
+0xFF5899CF,
+0xFF599AD0,
+0xFF589BD0,
+0xFF589BD0,
+0xFF589BD0,
+0xFF589BD0,
+0xFF589BD0,
+0xFF589BD0,
+0xFF589BD0,
+0xFF599CD1,
+0xFF599CD1,
+0xFF589BD0,
+0xFF589BD0,
+0xFF589BD0,
+0xFF599CD1,
+0xFF599CD1,
+0xFF599CD1,
+0xFF599CD1,
+0xFF589BD0,
+0xFF599CD1,
+0xFF599CD1,
+0xFF599CD1,
+0xFF599CD1,
+0xFF579DD1,
+0xFF579DD1,
+0xFF579DD1,
+0xFF579DD0,
+0xFF579DD0,
+0xFF5AA0D3,
+0xFF599CD0,
+0xFF5CA0D1,
+0xFF5A9CCE,
+0xFF5B9DCF,
+0xFF71B3E5,
+0xFF5C9ED0,
+0xFF579BCC,
+0xFF569CCD,
+0xFF569CCF,
+0xFF589ED1,
+0xFF5AA2D4,
+0xFF549CCE,
+0xFF549BCF,
+0xFF5AA1D5,
+0xFF569DD1,
+0xFF569DD1,
+0xFF569DD1,
+0xFF569DD1,
+0xFF579FD1,
+0xFF579FD1,
+0xFF579FD1,
+0xFF579FD1,
+0xFF579FD1,
+0xFF589ED1,
+0xFF589ED1,
+0xFF589ED1,
+0xFF589ED2,
+0xFF589ED2,
+0xFF589ED2,
+0xFF569DD1,
+0xFF58A0D2,
+0xFF559FD0,
+0xFF58A2D3,
+0xFF54A0D1,
+0xFF56A0D1,
+0xFF57A1D2,
+0xFF559DCD,
+0xFF65A0C0,
+0xFF658385,
+0xFF87957B,
+0xFF7A8052,
+0xFF66633A,
+0xFF2C1A16,
+0xFF141124,
+0xFF7A9DBD,
+0xFF629CC4,
+0xFF629ED0,
+0xFF5EA0D4,
+0xFF59A2D5,
+0xFF4E9ACC,
+0xFF58A2D3,
+0xFF59A3D2,
+0xFF519DCE,
+0xFF54A0D1,
+0xFF57A0D3,
+0xFF589FD3,
+0xFF58A0D2,
+0xFF58A0D2,
+0xFF58A0D2,
+0xFF58A0D2,
+0xFF58A0D2,
+0xFF58A0D2,
+0xFF579FD1,
+0xFF579FD1,
+0xFF589ED1,
+0xFF589ED1,
+0xFF589ED1,
+0xFF589ED1,
+0xFF589ED1,
+0xFF589ED1,
+0xFF589FD3,
+0xFF57A0D3,
+0xFF58A0D2,
+0xFF58A0D0,
+0xFF599FD2,
+0xFF599FD2,
+0xFF58A0D2,
+0xFF599FD0,
+0xFF5C9ED0,
+0xFF5C9ECE,
+0xFF5C9ECE,
+0xFF599FD0,
+0xFF57A1D2,
+0xFF57A1D2,
+0xFF5B9FD0,
+0xFF5C9ED0,
+0xFF5AA0D1,
+0xFF579FD1,
+0xFF5DA6D9,
+0xFF5CA0CF,
+0xFF5D92BA,
+0xFF8FBCDB,
+0xFFE0FFFF,
+0xFF8AB6D1,
+0xFF609BC5,
+0xFF559BCE,
+0xFF59A0D4,
+0xFF5AA0D3,
+0xFF5EA0D0,
+0xFF5CA0CF,
+0xFF539CD1,
+0xFF56A2D6,
+0xFF579ED2,
+0xFF579FD1,
+0xFF579FD1,
+0xFF579FD1,
+0xFF579FD1,
+0xFF579FD1,
+0xFF579FD1,
+0xFF579FD1,
+0xFF579FD1,
+0xFF58A0D2,
+0xFF599FD2,
+0xFF599FD2,
+0xFF589ED1,
+0xFF589ED1,
+0xFF589ED1,
+0xFF599FD2,
+0xFF5B9ED2,
+0xFF5B9ED2,
+0xFF5A9DD1,
+0xFF5A9DD1,
+0xFF5A9DD1,
+0xFF5A9DD1,
+0xFF5A9DD1,
+0xFF5A9DD1,
+0xFF5A9DD1,
+0xFF5A9DD1,
+0xFF5A9DD1,
+0xFF5A9DD1,
+0xFF5A9DD1,
+0xFF599CD0,
+0xFF599CD0,
+0xFF5A9DD1,
+0xFF579DD1,
+0xFF579DD1,
+0xFF579DD1,
+0xFF579DD1,
+0xFF579DD1,
+0xFF579DD1,
+0xFF569CD0,
+0xFF569CD0,
+0xFF589BD0,
+0xFF589BD0,
+0xFF589BD0,
+0xFF579ACF,
+0xFF579ACF,
+0xFF579ACF,
+0xFF579AD1,
+0xFF579AD1,
+0xFF5699CE,
+0xFF5699CE,
+0xFF5699CE,
+0xFF5699CE,
+0xFF5598CF,
+0xFF5598CF,
+0xFF5398CF,
+0xFF5297CE,
+0xFF5297CE,
+0xFF5297CE,
+0xFF5396CD,
+0xFF5295CC,
+0xFF5295CC,
+0xFF5295CC,
+0xFF5295CC,
+0xFF5194CB,
+0xFF5194CB,
+0xFF5193CD,
+0xFF5092CC,
+0xFF5092CC,
+0xFF4F91CB,
+0xFF4F91CB,
+0xFF5091CB,
+0xFF5091CB,
+0xFF4E8ECB,
+0xFF4E8ECB,
+0xFF4E8ECB,
+0xFF4D8DCA,
+0xFF4F8DCA,
+0xFF4F8DCA,
+0xFF4F8DCA,
+0xFF4E8CC9,
+0xFF4E86C3,
+0xFF4E86C3,
+0xFF4F87C4,
+0xFF4F87C4,
+0xFF4E86C3,
+0xFF4F87C4,
+0xFF4D88C4,
+0xFF4E89C5,
+0xFF4D88C4,
+0xFF4E89C5,
+0xFF4D89C5,
+0xFF4E8AC6,
+0xFF4D8BC6,
+0xFF4D8BC6,
+0xFF4D8BC6,
+0xFF4E8CC7,
+0xFF4F8DC8,
+0xFF4F8DC8,
+0xFF4F8DC8,
+0xFF4F8DC8,
+0xFF4F8DC8,
+0xFF508EC9,
+0xFF518FCA,
+0xFF5290CB,
+0xFF5290CB,
+0xFF5391CC,
+0xFF5192CA,
+0xFF5192CA,
+0xFF5192CA,
+0xFF5192CA,
+0xFF5293CB,
+0xFF5394CC,
+0xFF5295CC,
+0xFF5295CC,
+0xFF5295CA,
+0xFF5295CA,
+0xFF5295CA,
+0xFF5396CB,
+0xFF5394CA,
+0xFF5394CA,
+0xFF5495CB,
+0xFF5596CC,
+0xFF5596CC,
+0xFF5495CB,
+0xFF5495CB,
+0xFF5596CC,
+0xFF5697CD,
+0xFF5596CC,
+0xFF5897CD,
+0xFF5897CD,
+0xFF5998CE,
+0xFF5998CE,
+0xFF5998CE,
+0xFF5998CE,
+0xFF5998CE,
+0xFF5998CE,
+0xFF5998CE,
+0xFF5998CE,
+0xFF5A99CE,
+0xFF5A99CE,
+0xFF5A99CE,
+0xFF5998CD,
+0xFF5998CD,
+0xFF5A99CE,
+0xFF5897CD,
+0xFF5A99CF,
+0xFF5B9AD0,
+0xFF5B9AD0,
+0xFF5A99CF,
+0xFF5A99CF,
+0xFF5B9AD0,
+0xFF5B9AD0,
+0xFF599AD0,
+0xFF5899CF,
+0xFF5899CF,
+0xFF5899CF,
+0xFF5899CF,
+0xFF5899CF,
+0xFF5899CF,
+0xFF5899CF,
+0xFF5899CF,
+0xFF5899CF,
+0xFF5899CF,
+0xFF5899CF,
+0xFF5899CF,
+0xFF5899CF,
+0xFF5899CF,
+0xFF5899CF,
+0xFF599AD0,
+0xFF599AD0,
+0xFF599AD0,
+0xFF599AD0,
+0xFF599AD0,
+0xFF5899CF,
+0xFF599AD0,
+0xFF599AD0,
+0xFF5899CF,
+0xFF5899CF,
+0xFF5899CF,
+0xFF5899CF,
+0xFF579ACF,
+0xFF589BD0,
+0xFF589BD0,
+0xFF589BD0,
+0xFF589BD0,
+0xFF589BD0,
+0xFF589BD0,
+0xFF589BD0,
+0xFF589BD0,
+0xFF589BD0,
+0xFF589BD0,
+0xFF589BD0,
+0xFF589BD0,
+0xFF569CD0,
+0xFF569CD0,
+0xFF579DD1,
+0xFF579DD1,
+0xFF579DD1,
+0xFF579DD1,
+0xFF579DD1,
+0xFF579DD1,
+0xFF579DD1,
+0xFF579DD1,
+0xFF579DD1,
+0xFF589ED2,
+0xFF589ED2,
+0xFF579DD1,
+0xFF579DD1,
+0xFF5A9DD1,
+0xFF5A9DD1,
+0xFF5A9DD1,
+0xFF5A9DD1,
+0xFF5A9DD1,
+0xFF5A9DD1,
+0xFF5A9DD1,
+0xFF5A9DD1,
+0xFF589BCF,
+0xFF5B9FD0,
+0xFF589ACC,
+0xFF5D9FD1,
+0xFF5597C9,
+0xFF78BAEA,
+0xFF62A2D2,
+0xFF5A9CCE,
+0xFF5CA0D1,
+0xFF5CA2D5,
+0xFF549CCE,
+0xFF569ED0,
+0xFF579FD1,
+0xFF5AA2D4,
+0xFF5BA2D6,
+0xFF559CD0,
+0xFF579ED2,
+0xFF579ED2,
+0xFF579FD1,
+0xFF579FD1,
+0xFF599FD2,
+0xFF599FD2,
+0xFF599FD0,
+0xFF58A0D0,
+0xFF58A0D0,
+0xFF58A0D0,
+0xFF599FD2,
+0xFF599FD2,
+0xFF5B9ED2,
+0xFF5B9ED2,
+0xFF5A9DD1,
+0xFF589ED1,
+0xFF58A0D2,
+0xFF56A0D1,
+0xFF58A2D3,
+0xFF57A1D2,
+0xFF56A0D1,
+0xFF57A1D2,
+0xFF56A0D1,
+0xFF5F9FC5,
+0xFF7EA7B9,
+0xFF475A58,
+0xFF423B28,
+0xFF2C2012,
+0xFF1A1D2E,
+0xFF839BBF,
+0xFF6A9DCA,
+0xFF5E9CCF,
+0xFF5F9DD0,
+0xFF5A9CD0,
+0xFF59A0D4,
+0xFF539DCE,
+0xFF599FD0,
+0xFF5BA2D0,
+0xFF579FD1,
+0xFF58A1D4,
+0xFF58A0D2,
+0xFF599FD2,
+0xFF599FD2,
+0xFF599FD2,
+0xFF599FD2,
+0xFF599FD2,
+0xFF599FD0,
+0xFF599FD0,
+0xFF599FD0,
+0xFF5AA0D1,
+0xFF5CA0D1,
+0xFF5CA0D1,
+0xFF5CA0D1,
+0xFF5CA0D1,
+0xFF5CA0D1,
+0xFF5CA0D1,
+0xFF5C9FD3,
+0xFF5AA0D3,
+0xFF5AA2D4,
+0xFF5AA2D4,
+0xFF5AA0D1,
+0xFF5CA0CF,
+0xFF5CA0CF,
+0xFF5CA0CF,
+0xFF5D9FD3,
+0xFF5D9FD3,
+0xFF5EA0D4,
+0xFF5BA1D2,
+0xFF58A2D1,
+0xFF58A2D1,
+0xFF5D9FD3,
+0xFF5D9FD3,
+0xFF5BA1D4,
+0xFF5CA2D3,
+0xFF5C9CCA,
+0xFF6096BC,
+0xFF96BAD2,
+0xFFE5FFFF,
+0xFF99C6E5,
+0xFF5D94BB,
+0xFF5E9ECE,
+0xFF5EA1D5,
+0xFF5CA0D1,
+0xFF599DCE,
+0xFF5EA2D3,
+0xFF5CA2D3,
+0xFF579ED2,
+0xFF589FD3,
+0xFF599FD2,
+0xFF599FD0,
+0xFF599FD0,
+0xFF599FD0,
+0xFF599FD0,
+0xFF599FD0,
+0xFF599FD0,
+0xFF599FD0,
+0xFF599FD0,
+0xFF5AA0D1,
+0xFF5AA0D1,
+0xFF5AA0D1,
+0xFF5B9FD0,
+0xFF5B9FD0,
+0xFF5B9FD0,
+0xFF5CA0D1,
+0xFF5C9FD3,
+0xFF5C9FD3,
+0xFF5C9FD3,
+0xFF5B9ED2,
+0xFF5B9ED2,
+0xFF5B9ED2,
+0xFF5B9ED2,
+0xFF5B9ED2,
+0xFF5B9ED2,
+0xFF5B9ED2,
+0xFF5C9FD3,
+0xFF5B9ED2,
+0xFF5B9ED2,
+0xFF5A9DD1,
+0xFF5A9DD1,
+0xFF5B9ED2,
+0xFF5A9DD1,
+0xFF5A9DD1,
+0xFF589ED2,
+0xFF589ED2,
+0xFF589ED2,
+0xFF589ED2,
+0xFF579DD1,
+0xFF579DD1,
+0xFF589ED2,
+0xFF579DD1,
+0xFF579DD1,
+0xFF569CD0,
+0xFF569CD0,
+0xFF569CD0,
+0xFF569CD0,
+0xFF589BD0,
+0xFF579ACF,
+0xFF5899CF,
+0xFF5899CF,
+0xFF5899CF,
+0xFF579ACF,
+0xFF5699CE,
+0xFF5699CE,
+0xFF5699CE,
+0xFF5598CD,
+0xFF5598CD,
+0xFF5497CC,
+0xFF5396CB,
+0xFF5495CB,
+0xFF5495CB,
+0xFF5495CB,
+0xFF5295CA,
+0xFF5295CA,
+0xFF5095CC,
+0xFF5194CB,
+0xFF5194CB,
+0xFF5194CB,
+0xFF5093CA,
+0xFF5092CC,
+0xFF5092CC,
+0xFF5091CB,
+0xFF5091CB,
+0xFF4F8FCC,
+0xFF4F8FCC,
+0xFF508ECB,
+0xFF508ECB,
+0xFF4F8DCA,
+0xFF4F8DCA,
+0xFF4E86C3,
+0xFF4F87C4,
+0xFF4F87C4,
+0xFF5088C5,
+0xFF4F87C4,
+0xFF4D88C4,
+0xFF4E89C5,
+0xFF4E89C5,
+0xFF4F8AC6,
+0xFF4F8AC6,
+0xFF4F8BC7,
+0xFF4F8BC7,
+0xFF4F8DC8,
+0xFF4F8DC8,
+0xFF4F8DC8,
+0xFF4F8DC8,
+0xFF508EC9,
+0xFF4F8DC8,
+0xFF4F8DC8,
+0xFF508EC9,
+0xFF508EC9,
+0xFF518FCA,
+0xFF5290CB,
+0xFF5391CC,
+0xFF5492CD,
+0xFF5492CD,
+0xFF5293CB,
+0xFF5293CB,
+0xFF5293CB,
+0xFF5293CB,
+0xFF5394CC,
+0xFF5394CC,
+0xFF5396CD,
+0xFF5295CC,
+0xFF5295CA,
+0xFF5396CB,
+0xFF5396CB,
+0xFF5396CB,
+0xFF5495CB,
+0xFF5495CB,
+0xFF5495CB,
+0xFF5596CC,
+0xFF5697CD,
+0xFF5697CD,
+0xFF5697CD,
+0xFF5798CE,
+0xFF5697CD,
+0xFF5495CB,
+0xFF5998CE,
+0xFF5998CE,
+0xFF5998CE,
+0xFF5998CE,
+0xFF5A99CF,
+0xFF5A99CF,
+0xFF5998CE,
+0xFF5A99CF,
+0xFF5A99CF,
+0xFF5A99CF,
+0xFF5A99CE,
+0xFF5B9ACF,
+0xFF5C9BD0,
+0xFF5C9BD0,
+0xFF5B9ACF,
+0xFF5B9ACF,
+0xFF5B9AD0,
+0xFF5C9BD1,
+0xFF5C9BD1,
+0xFF5C9BD1,
+0xFF5B9AD0,
+0xFF5A99CF,
+0xFF5A99CF,
+0xFF599AD0,
+0xFF599AD0,
+0xFF5899CF,
+0xFF5899CF,
+0xFF5899CF,
+0xFF5899CF,
+0xFF5899CF,
+0xFF5899CF,
+0xFF5899CF,
+0xFF599AD0,
+0xFF599AD0,
+0xFF599AD0,
+0xFF599AD0,
+0xFF599AD0,
+0xFF599AD0,
+0xFF599AD0,
+0xFF599AD0,
+0xFF599AD0,
+0xFF5A9BD1,
+0xFF5A9BD1,
+0xFF5A9BD1,
+0xFF599AD0,
+0xFF599AD0,
+0xFF599AD0,
+0xFF5A9BD1,
+0xFF5899CF,
+0xFF5899CF,
+0xFF5899CF,
+0xFF599AD0,
+0xFF589BD0,
+0xFF589BD0,
+0xFF589BD0,
+0xFF589BD0,
+0xFF589BD0,
+0xFF599CD1,
+0xFF599CD1,
+0xFF599CD1,
+0xFF599CD1,
+0xFF599CD1,
+0xFF599CD1,
+0xFF599CD1,
+0xFF569CD0,
+0xFF579DD1,
+0xFF579DD1,
+0xFF579DD1,
+0xFF579DD1,
+0xFF579DD1,
+0xFF589ED2,
+0xFF589ED2,
+0xFF589ED2,
+0xFF589ED2,
+0xFF589ED2,
+0xFF589ED2,
+0xFF589ED2,
+0xFF589ED2,
+0xFF589ED2,
+0xFF589ED2,
+0xFF5B9ED2,
+0xFF5B9ED2,
+0xFF5B9ED2,
+0xFF5B9ED2,
+0xFF5B9ED2,
+0xFF5B9ED2,
+0xFF5B9ED2,
+0xFF5B9FD0,
+0xFF589CCD,
+0xFF5EA0D2,
+0xFF5C9ED0,
+0xFF5597C9,
+0xFF7BBDED,
+0xFF5EA0D0,
+0xFF5B9BCB,
+0xFF5D9FCF,
+0xFF599CD0,
+0xFF589ED1,
+0xFF5CA2D5,
+0xFF59A1D3,
+0xFF579DD0,
+0xFF58A0D2,
+0xFF589ED2,
+0xFF59A0D4,
+0xFF599FD3,
+0xFF58A0D2,
+0xFF599FD2,
+0xFF599FD2,
+0xFF599FD2,
+0xFF599FD2,
+0xFF5B9FD0,
+0xFF599FD0,
+0xFF59A1D1,
+0xFF58A2D1,
+0xFF5AA0D3,
+0xFF5AA0D3,
+0xFF5B9ED2,
+0xFF5B9ED2,
+0xFF5B9ED2,
+0xFF5B9ED2,
+0xFF599FD2,
+0xFF58A0D2,
+0xFF5AA2D4,
+0xFF5AA2D4,
+0xFF58A0D2,
+0xFF58A0D2,
+0xFF5AA2D4,
+0xFF5DA0CB,
+0xFF689DBC,
+0xFF6D8899,
+0xFF251B1C,
+0xFF13040B,
+0xFF8694B1,
+0xFF7A9FCC,
+0xFF6198CE,
+0xFF5FA0D8,
+0xFF609FD4,
+0xFF5EA0D4,
+0xFF5BA1D4,
+0xFF5CA2D3,
+0xFF5EA2D1,
+0xFF5A9CCC,
+0xFF62A5D9,
+0xFF5B9ED2,
+0xFF5DA0D4,
+0xFF5BA1D4,
+0xFF5DA0D4,
+0xFF5AA0D3,
+0xFF5DA0D4,
+0xFF5BA1D4,
+0xFF5DA1D2,
+0xFF5DA1D2,
+0xFF5DA1D2,
+0xFF5DA1D2,
+0xFF5EA0D2,
+0xFF5DA1D2,
+0xFF5EA0D2,
+0xFF5EA2D3,
+0xFF5FA1D3,
+0xFF5FA1D3,
+0xFF5EA0D2,
+0xFF5DA1D2,
+0xFF5BA3D5,
+0xFF5BA3D5,
+0xFF5EA0D2,
+0xFF60A0D0,
+0xFF60A0CE,
+0xFF5EA0D0,
+0xFF5C9FD3,
+0xFF5BA1D5,
+0xFF5EA1D6,
+0xFF5BA1D4,
+0xFF5BA1D2,
+0xFF5BA1D2,
+0xFF5EA0D4,
+0xFF5EA0D4,
+0xFF5DA0D4,
+0xFF61A0CC,
+0xFF6193B8,
+0xFF9BC3DD,
+0xFFE6FFFF,
+0xFFA7CAE0,
+0xFF5F93B8,
+0xFF619FCE,
+0xFF5EA0D2,
+0xFF5C9FD3,
+0xFF5D9FD1,
+0xFF60A2D2,
+0xFF5B9FD0,
+0xFF5A9DD1,
+0xFF5FA3D4,
+0xFF5EA2D3,
+0xFF5DA1D2,
+0xFF5BA1D2,
+0xFF5DA1D2,
+0xFF5BA1D2,
+0xFF5DA1D2,
+0xFF5BA1D2,
+0xFF5DA1D2,
+0xFF5BA1D2,
+0xFF5DA1D2,
+0xFF5BA1D2,
+0xFF5DA1D2,
+0xFF5DA1D2,
+0xFF5DA1D2,
+0xFF5CA0D1,
+0xFF5EA0D2,
+0xFF5DA1D2,
+0xFF5C9FD3,
+0xFF5C9FD3,
+0xFF5C9FD3,
+0xFF5C9FD3,
+0xFF5C9FD3,
+0xFF5C9FD3,
+0xFF5C9FD3,
+0xFF5C9FD3,
+0xFF5B9ED2,
+0xFF5C9FD3,
+0xFF5C9FD3,
+0xFF5C9FD3,
+0xFF5B9ED2,
+0xFF5B9ED2,
+0xFF5B9ED2,
+0xFF5C9FD3,
+0xFF5B9ED2,
+0xFF5B9ED2,
+0xFF599FD3,
+0xFF599FD3,
+0xFF599FD3,
+0xFF589ED2,
+0xFF589ED2,
+0xFF589ED2,
+0xFF589ED2,
+0xFF589ED2,
+0xFF579DD1,
+0xFF579DD1,
+0xFF569CD0,
+0xFF569CD0,
+0xFF569CD0,
+0xFF569CD0,
+0xFF599AD0,
+0xFF599AD0,
+0xFF599AD0,
+0xFF599AD0,
+0xFF579ACF,
+0xFF579ACF,
+0xFF579ACF,
+0xFF5699CE,
+0xFF5699CE,
+0xFF5598CD,
+0xFF5497CC,
+0xFF5497CC,
+0xFF5596CC,
+0xFF5596CC,
+0xFF5596CC,
+0xFF5495CB,
+0xFF5396CB,
+0xFF5197CB,
+0xFF5295CC,
+0xFF5295CC,
+0xFF5194CB,
+0xFF5194CB,
+0xFF5193CD,
+0xFF5092CC,
+0xFF5192CC,
+0xFF5192CC,
+0xFF5090CD,
+0xFF5090CD,
+0xFF518FCC,
+0xFF518FCC,
+0xFF508ECB,
+0xFF508ECB,
+0xFF4E86C3,
+0xFF4F87C4,
+0xFF4D88C4,
+0xFF4E89C5,
+0xFF4E89C5,
+0xFF4E89C5,
+0xFF4F8AC6,
+0xFF4E8AC6,
+0xFF4E8AC6,
+0xFF4F8BC7,
+0xFF4F8BC7,
+0xFF508CC8,
+0xFF4F8DC8,
+0xFF4F8DC8,
+0xFF508EC9,
+0xFF518FCA,
+0xFF4F8DC6,
+0xFF508EC7,
+0xFF518FC8,
+0xFF5290C9,
+0xFF5290C9,
+0xFF5290C9,
+0xFF5391CA,
+0xFF5391CA,
+0xFF5391CA,
+0xFF5492CB,
+0xFF5394CC,
+0xFF5394CC,
+0xFF5293CB,
+0xFF5293CB,
+0xFF5394CC,
+0xFF5495CD,
+0xFF5396CB,
+0xFF5396CB,
+0xFF5497CC,
+0xFF5497CC,
+0xFF5497CC,
+0xFF5497CC,
+0xFF5596CC,
+0xFF5697CD,
+0xFF5697CD,
+0xFF5798CE,
+0xFF5798CE,
+0xFF5798CE,
+0xFF589ACE,
+0xFF589ACE,
+0xFF5A99CE,
+0xFF5B9ACF,
+0xFF5A99CF,
+0xFF5A99CF,
+0xFF5B9AD0,
+0xFF5B9AD0,
+0xFF5B9AD0,
+0xFF5B9AD0,
+0xFF5A99CE,
+0xFF5998CD,
+0xFF5B9ACF,
+0xFF5B9ACF,
+0xFF5B9ACF,
+0xFF5B9ACF,
+0xFF5B9ACF,
+0xFF5B9ACF,
+0xFF5B9ACD,
+0xFF5B9ACD,
+0xFF5A9CD0,
+0xFF5A9CD0,
+0xFF5A9CD0,
+0xFF599BCF,
+0xFF599BCF,
+0xFF599BCF,
+0xFF599BCF,
+0xFF599BCF,
+0xFF5A9CD0,
+0xFF599CD0,
+0xFF599CD0,
+0xFF599CD0,
+0xFF599CD0,
+0xFF599CD0,
+0xFF599CD0,
+0xFF599CD0,
+0xFF5A9DD1,
+0xFF599CD0,
+0xFF599CD0,
+0xFF599CD0,
+0xFF599CD0,
+0xFF599CD0,
+0xFF599CD0,
+0xFF599CD0,
+0xFF589BCF,
+0xFF589BCF,
+0xFF589BCF,
+0xFF589BCF,
+0xFF599CD0,
+0xFF599CD0,
+0xFF599CD0,
+0xFF589BCF,
+0xFF589BCF,
+0xFF589BCF,
+0xFF589BCF,
+0xFF589BCF,
+0xFF589BCF,
+0xFF599CD0,
+0xFF589ED1,
+0xFF589ED1,
+0xFF599FD2,
+0xFF599FD2,
+0xFF599FD2,
+0xFF599FD2,
+0xFF599FD2,
+0xFF599FD2,
+0xFF589ED1,
+0xFF589ED1,
+0xFF5A9DD1,
+0xFF5B9ED2,
+0xFF5B9ED2,
+0xFF5B9ED2,
+0xFF5B9ED2,
+0xFF5B9ED2,
+0xFF5B9ED2,
+0xFF5C9FD3,
+0xFF5B9ED2,
+0xFF5B9ED2,
+0xFF5A9DD1,
+0xFF5A9DD1,
+0xFF5A9DD1,
+0xFF5B9ED2,
+0xFF5C9FD3,
+0xFF5C9FD3,
+0xFF5A9DD1,
+0xFF5C9FD3,
+0xFF599DCE,
+0xFF5DA1D2,
+0xFF5D9FD1,
+0xFF5C9ED0,
+0xFF5B9DCF,
+0xFF5EA0D2,
+0xFF5D9FD1,
+0xFF61A1D1,
+0xFF5B9BCB,
+0xFF7DBDED,
+0xFF5A9ACA,
+0xFF5D9DCD,
+0xFF5E9ECE,
+0xFF5EA0D0,
+0xFF5C9FD3,
+0xFF5C9FD3,
+0xFF5C9FD3,
+0xFF5AA0D3,
+0xFF5DA0D4,
+0xFF5BA1D4,
+0xFF5DA0D4,
+0xFF5AA0D3,
+0xFF5C9FD3,
+0xFF5AA0D3,
+0xFF5C9FD3,
+0xFF5CA0D1,
+0xFF5CA0D1,
+0xFF5CA0D1,
+0xFF5D9FD1,
+0xFF5CA0D1,
+0xFF5AA2D2,
+0xFF58A2D1,
+0xFF599FD0,
+0xFF5AA0D1,
+0xFF5DA1D2,
+0xFF5FA1D3,
+0xFF5EA0D2,
+0xFF5D9FD1,
+0xFF5FA1D3,
+0xFF5EA2D3,
+0xFF5DA1D2,
+0xFF5BA1D2,
+0xFF5BA1D4,
+0xFF5BA1D4,
+0xFF5CA2D5,
+0xFF5EA2D1,
+0xFF609FC8,
+0xFF81A8C7,
+0xFF423D51,
+0xFF201327,
+0xFF5B698C,
+0xFF7BA0CD,
+0xFF659AD0,
+0xFF619FD8,
+0xFF5E9FD5,
+0xFF5DA0D4,
+0xFF5EA0D0,
+0xFF5FA1D1,
+0xFF5FA1D3,
+0xFF609FD2,
+0xFF619FD2,
+0xFF619FD2,
+0xFF5FA1D3,
+0xFF5EA2D3,
+0xFF5FA1D3,
+0xFF5EA2D3,
+0xFF5FA1D3,
+0xFF5EA2D3,
+0xFF5FA1D3,
+0xFF5FA1D3,
+0xFF60A2D4,
+0xFF60A2D4,
+0xFF62A2D2,
+0xFF60A2D2,
+0xFF61A1D1,
+0xFF5FA1D1,
+0xFF61A1D1,
+0xFF5FA1D1,
+0xFF5FA1D1,
+0xFF5FA1D1,
+0xFF5FA1D5,
+0xFF5FA1D3,
+0xFF61A1D1,
+0xFF62A0CF,
+0xFF63A0CF,
+0xFF61A1D1,
+0xFF5BA2D6,
+0xFF5BA4D9,
+0xFF5CA3D9,
+0xFF62A5DA,
+0xFF639FD3,
+0xFF609CCE,
+0xFF5FA3D4,
+0xFF5EA4D5,
+0xFF62A2D2,
+0xFF6195BC,
+0xFFA1C0D5,
+0xFFEBFFFF,
+0xFFACD1EC,
+0xFF6494B8,
+0xFF66A1CD,
+0xFF61A1D1,
+0xFF5FA1D5,
+0xFF5EA1D5,
+0xFF60A2D6,
+0xFF5FA3D4,
+0xFF60A2D4,
+0xFF5FA1D3,
+0xFF61A1D1,
+0xFF60A0CE,
+0xFF5FA1D3,
+0xFF5DA1D2,
+0xFF5EA0D2,
+0xFF5DA1D2,
+0xFF5EA0D2,
+0xFF5EA2D3,
+0xFF5FA1D3,
+0xFF5FA3D4,
+0xFF5EA0D2,
+0xFF5DA1D2,
+0xFF5EA0D2,
+0xFF5EA0D2,
+0xFF5EA0D2,
+0xFF5EA0D2,
+0xFF609FD2,
+0xFF5EA0D2,
+0xFF5EA0D2,
+0xFF5EA0D2,
+0xFF5EA0D2,
+0xFF5EA0D2,
+0xFF5EA0D2,
+0xFF5EA0D2,
+0xFF5D9FD1,
+0xFF5D9FD1,
+0xFF5EA0D2,
+0xFF5EA0D2,
+0xFF5EA0D2,
+0xFF5EA0D2,
+0xFF5EA0D2,
+0xFF5EA0D2,
+0xFF5EA0D2,
+0xFF5EA0D2,
+0xFF5DA0D4,
+0xFF5DA0D4,
+0xFF5C9FD3,
+0xFF5C9FD3,
+0xFF5C9FD3,
+0xFF5B9ED2,
+0xFF5B9ED2,
+0xFF5A9DD1,
+0xFF5B9ED2,
+0xFF5B9ED2,
+0xFF589ED1,
+0xFF589ED1,
+0xFF589ED1,
+0xFF589ED1,
+0xFF579DD0,
+0xFF579DD0,
+0xFF5A9BD1,
+0xFF5A9BD1,
+0xFF599AD0,
+0xFF599AD0,
+0xFF589BD0,
+0xFF579ACF,
+0xFF579ACF,
+0xFF579ACF,
+0xFF5699CE,
+0xFF5699CE,
+0xFF5598CD,
+0xFF5598CD,
+0xFF5697CD,
+0xFF5697CD,
+0xFF5697CD,
+0xFF5697CD,
+0xFF5396CB,
+0xFF5396CB,
+0xFF5396CB,
+0xFF5295CA,
+0xFF5295CA,
+0xFF5295CA,
+0xFF5194CB,
+0xFF5194CB,
+0xFF5293CB,
+0xFF5293CB,
+0xFF5192CC,
+0xFF5091CB,
+0xFF5091CB,
+0xFF4F90CA,
+0xFF4F8FCC,
+0xFF4F8FCC,
+0xFF4F87C4,
+0xFF4F87C4,
+0xFF4E89C5,
+0xFF4E89C5,
+0xFF4E89C5,
+0xFF4F8AC6,
+0xFF4E8AC6,
+0xFF4F8BC7,
+0xFF4E8AC6,
+0xFF4F8BC7,
+0xFF4F8BC7,
+0xFF508CC8,
+0xFF4F8DC8,
+0xFF4F8DC8,
+0xFF508EC9,
+0xFF518FCA,
+0xFF508EC7,
+0xFF518FC8,
+0xFF5290C9,
+0xFF5290C9,
+0xFF5391CA,
+0xFF5391CA,
+0xFF5492CB,
+0xFF5492CB,
+0xFF5492CB,
+0xFF5593CC,
+0xFF5495CD,
+0xFF5495CD,
+0xFF5394CC,
+0xFF5394CC,
+0xFF5394CC,
+0xFF5495CD,
+0xFF5396CB,
+0xFF5396CB,
+0xFF5497CC,
+0xFF5497CC,
+0xFF5497CC,
+0xFF5497CC,
+0xFF5697CD,
+0xFF5798CE,
+0xFF5697CD,
+0xFF5798CE,
+0xFF5798CE,
+0xFF5798CE,
+0xFF589ACE,
+0xFF589ACE,
+0xFF5A99CE,
+0xFF5B9ACF,
+0xFF5B9AD0,
+0xFF5C9BD1,
+0xFF5C9BD1,
+0xFF5C9BD1,
+0xFF5C9BD1,
+0xFF5B9AD0,
+0xFF5B9ACF,
+0xFF5B9ACF,
+0xFF5B9ACF,
+0xFF5B9ACF,
+0xFF5C9BD0,
+0xFF5C9BD0,
+0xFF5C9BD0,
+0xFF5C9BD0,
+0xFF5B9ACD,
+0xFF5B9ACD,
+0xFF5A9CD0,
+0xFF5A9CD0,
+0xFF5A9CD0,
+0xFF5A9CD0,
+0xFF5A9CD0,
+0xFF5A9CD0,
+0xFF5A9CD0,
+0xFF5A9CD0,
+0xFF599CD0,
+0xFF599CD0,
+0xFF599CD0,
+0xFF599CD0,
+0xFF599CD0,
+0xFF599CD0,
+0xFF5A9DD1,
+0xFF5A9DD1,
+0xFF5A9DD1,
+0xFF5A9DD1,
+0xFF5A9DD1,
+0xFF5A9DD1,
+0xFF5A9DD1,
+0xFF5A9DD1,
+0xFF5A9DD1,
+0xFF5A9DD1,
+0xFF5A9DD1,
+0xFF5A9DD1,
+0xFF5A9DD1,
+0xFF5A9DD1,
+0xFF5A9DD1,
+0xFF5B9ED2,
+0xFF5A9DD1,
+0xFF5A9DD1,
+0xFF599CD0,
+0xFF599CD0,
+0xFF599CD0,
+0xFF599CD0,
+0xFF599CD0,
+0xFF5A9DD1,
+0xFF599FD2,
+0xFF599FD2,
+0xFF599FD2,
+0xFF599FD2,
+0xFF599FD2,
+0xFF599FD2,
+0xFF599FD2,
+0xFF599FD2,
+0xFF599FD2,
+0xFF599FD2,
+0xFF5A9DD1,
+0xFF5B9ED2,
+0xFF5B9ED2,
+0xFF5B9ED2,
+0xFF5B9ED2,
+0xFF5B9ED2,
+0xFF5B9ED2,
+0xFF5C9FD3,
+0xFF5C9FD3,
+0xFF5C9FD3,
+0xFF5B9ED2,
+0xFF5B9ED2,
+0xFF5B9ED2,
+0xFF5C9FD3,
+0xFF5C9FD3,
+0xFF5C9FD3,
+0xFF5EA1D5,
+0xFF5B9FD0,
+0xFF5EA2D3,
+0xFF5B9FD0,
+0xFF5D9FD1,
+0xFF5D9FD1,
+0xFF5D9FD1,
+0xFF63A3D3,
+0xFF5F9FCF,
+0xFF5898C8,
+0xFF80C0F0,
+0xFF63A3D3,
+0xFF5E9ECE,
+0xFF61A1D1,
+0xFF63A3D3,
+0xFF5D9DCD,
+0xFF5EA0D2,
+0xFF5DA0D4,
+0xFF5EA0D4,
+0xFF5DA0D4,
+0xFF5FA1D5,
+0xFF5EA1D5,
+0xFF5DA0D4,
+0xFF5DA0D4,
+0xFF5DA0D4,
+0xFF5EA1D5,
+0xFF5FA1D3,
+0xFF5FA1D3,
+0xFF5FA1D3,
+0xFF5FA1D3,
+0xFF5FA1D3,
+0xFF5DA1D2,
+0xFF5AA2D2,
+0xFF5AA2D2,
+0xFF5BA1D2,
+0xFF5DA1D2,
+0xFF5FA1D3,
+0xFF5FA1D3,
+0xFF61A0D3,
+0xFF61A0D3,
+0xFF61A0D3,
+0xFF5FA1D3,
+0xFF5FA1D3,
+0xFF5FA1D3,
+0xFF5FA1D5,
+0xFF5FA1D5,
+0xFF5FA1D5,
+0xFF5FA1D3,
+0xFF5FA1D1,
+0xFF6C9CC4,
+0xFF9BA1C1,
+0xFF24203B,
+0xFF151E3D,
+0xFF8CA8CF,
+0xFF73A5D8,
+0xFF609FD5,
+0xFF5EA0D4,
+0xFF5FA1D3,
+0xFF61A1CF,
+0xFF62A2D0,
+0xFF60A2D4,
+0xFF62A1D4,
+0xFF64A0D2,
+0xFF64A0D2,
+0xFF61A0D3,
+0xFF5FA1D3,
+0xFF5FA1D3,
+0xFF5FA1D3,
+0xFF5FA1D3,
+0xFF5FA1D3,
+0xFF61A0D3,
+0xFF61A0D3,
+0xFF62A1D4,
+0xFF62A1D4,
+0xFF62A2D2,
+0xFF62A2D2,
+0xFF62A2D2,
+0xFF62A2D2,
+0xFF62A2D2,
+0xFF62A2D2,
+0xFF62A2D2,
+0xFF62A2D2,
+0xFF63A1D2,
+0xFF63A1D2,
+0xFF63A1D0,
+0xFF63A1D0,
+0xFF64A0D2,
+0xFF62A1D4,
+0xFF5EA4D7,
+0xFF5AA3D6,
+0xFF5CA3D7,
+0xFF5B9DD1,
+0xFF649BD1,
+0xFF6CA4D7,
+0xFF63A3D1,
+0xFF61A0CB,
+0xFF6499C1,
+0xFF98C1E1,
+0xFFE9FFFF,
+0xFFB7D2E7,
+0xFF6E9BBC,
+0xFF67A0CB,
+0xFF63A1D2,
+0xFF5FA1D3,
+0xFF61A0D3,
+0xFF5FA1D3,
+0xFF5FA2D6,
+0xFF5FA2D6,
+0xFF60A2D4,
+0xFF62A2D2,
+0xFF64A1D0,
+0xFF62A0CF,
+0xFF61A1D1,
+0xFF5FA1D3,
+0xFF5FA1D3,
+0xFF5FA1D3,
+0xFF5FA1D3,
+0xFF60A2D4,
+0xFF62A1D4,
+0xFF60A2D4,
+0xFF62A1D4,
+0xFF60A2D4,
+0xFF62A1D4,
+0xFF62A1D4,
+0xFF62A1D4,
+0xFF62A1D4,
+0xFF62A1D4,
+0xFF62A1D4,
+0xFF62A1D4,
+0xFF60A2D4,
+0xFF60A2D4,
+0xFF60A2D4,
+0xFF5FA1D3,
+0xFF5FA1D3,
+0xFF5FA1D3,
+0xFF5FA1D3,
+0xFF5FA1D3,
+0xFF5FA1D3,
+0xFF5FA1D3,
+0xFF5FA1D3,
+0xFF5FA1D3,
+0xFF5FA1D3,
+0xFF5FA1D3,
+0xFF5FA1D3,
+0xFF5EA0D4,
+0xFF5DA0D4,
+0xFF5DA0D4,
+0xFF5DA0D4,
+0xFF5DA0D4,
+0xFF5C9FD3,
+0xFF5C9FD3,
+0xFF5C9FD3,
+0xFF5C9FD3,
+0xFF5B9ED2,
+0xFF5B9ED2,
+0xFF589ED1,
+0xFF589ED1,
+0xFF589ED1,
+0xFF589ED1,
+0xFF5A9DD1,
+0xFF5B9CD2,
+0xFF5A9BD1,
+0xFF5A9BD1,
+0xFF5A9BD1,
+0xFF589BD0,
+0xFF589BD0,
+0xFF589BD0,
+0xFF589BD0,
+0xFF589BD0,
+0xFF579ACF,
+0xFF579ACF,
+0xFF5699CE,
+0xFF5697CD,
+0xFF5697CD,
+0xFF5697CD,
+0xFF5697CD,
+0xFF5497CC,
+0xFF5497CC,
+0xFF5497CC,
+0xFF5497CC,
+0xFF5396CB,
+0xFF5396CB,
+0xFF5396CD,
+0xFF5396CD,
+0xFF5394CC,
+0xFF5293CB,
+0xFF5293CD,
+0xFF5192CC,
+0xFF5091CB,
+0xFF5091CB,
+0xFF5091CB,
+0xFF5091CB,
+0xFF4D88C4,
+0xFF4E89C5,
+0xFF4F8AC6,
+0xFF4F8AC6,
+0xFF4E8AC6,
+0xFF4E8AC6,
+0xFF4F8BC7,
+0xFF4F8BC7,
+0xFF4E8CC7,
+0xFF4F8DC8,
+0xFF4F8DC8,
+0xFF4F8DC8,
+0xFF508CC8,
+0xFF518DC9,
+0xFF528ECA,
+0xFF528ECA,
+0xFF5290C9,
+0xFF5391CA,
+0xFF5391CA,
+0xFF5492CB,
+0xFF5493C9,
+0xFF5493C9,
+0xFF5594CA,
+0xFF5594CA,
+0xFF5594CA,
+0xFF5695CB,
+0xFF5796CC,
+0xFF5796CC,
+0xFF5695CB,
+0xFF5695CB,
+0xFF5495CB,
+0xFF5596CC,
+0xFF5497CC,
+0xFF5497CC,
+0xFF5598CD,
+0xFF5598CD,
+0xFF5798CE,
+0xFF5798CE,
+0xFF589ACE,
+0xFF589ACE,
+0xFF5799CD,
+0xFF5799CD,
+0xFF5799CD,
+0xFF5799CD,
+0xFF5A99CE,
+0xFF5A99CE,
+0xFF5A99CE,
+0xFF5B9ACF,
+0xFF5C9BD0,
+0xFF5C9BD0,
+0xFF5B9ACF,
+0xFF5B9ACF,
+0xFF5B9ACF,
+0xFF5B9ACF,
+0xFF5B9ACF,
+0xFF5C9BD0,
+0xFF5C9BCE,
+0xFF5C9BCE,
+0xFF5C9BCE,
+0xFF5C9BCE,
+0xFF5C9BCE,
+0xFF5C9BCE,
+0xFF5C9BCE,
+0xFF5C9BCE,
+0xFF5A9CD0,
+0xFF599CD0,
+0xFF599CD0,
+0xFF599CD0,
+0xFF599CD0,
+0xFF599CD0,
+0xFF5A9DD1,
+0xFF5A9DD1,
+0xFF599CD0,
+0xFF599CD0,
+0xFF599CD0,
+0xFF5A9DD1,
+0xFF5A9DD1,
+0xFF5A9DD1,
+0xFF5B9ED2,
+0xFF5B9ED2,
+0xFF5B9FD0,
+0xFF5B9FD0,
+0xFF5B9FD0,
+0xFF5B9FD0,
+0xFF5B9FD0,
+0xFF5B9FD0,
+0xFF5CA0D1,
+0xFF5CA0D1,
+0xFF5B9FD0,
+0xFF5B9FD0,
+0xFF5CA0D1,
+0xFF5CA0D1,
+0xFF5CA0D1,
+0xFF5CA0D1,
+0xFF5CA0D1,
+0xFF5CA0D1,
+0xFF5B9FD0,
+0xFF5B9FD0,
+0xFF5A9ECF,
+0xFF5A9ECF,
+0xFF5B9FD0,
+0xFF5B9FD0,
+0xFF5CA0D1,
+0xFF5CA0D1,
+0xFF5B9FD0,
+0xFF5B9FD0,
+0xFF5AA0D1,
+0xFF5AA0D1,
+0xFF5AA0D1,
+0xFF5AA0D1,
+0xFF5AA0D1,
+0xFF5AA0D1,
+0xFF5CA0D1,
+0xFF5D9FD1,
+0xFF5D9FD1,
+0xFF5D9FD1,
+0xFF5D9FD1,
+0xFF5D9FD1,
+0xFF5EA0D2,
+0xFF5EA0D2,
+0xFF5EA0D2,
+0xFF5EA0D2,
+0xFF5EA0D2,
+0xFF5EA0D2,
+0xFF5EA0D2,
+0xFF5EA0D2,
+0xFF5EA0D2,
+0xFF5EA0D2,
+0xFF5C9ED0,
+0xFF62A4D4,
+0xFF5C9ECE,
+0xFF5FA1D1,
+0xFF60A0D0,
+0xFF64A4D4,
+0xFF5E9ECE,
+0xFF5E9CCB,
+0xFF619FCE,
+0xFF7FBDEC,
+0xFF62A0D1,
+0xFF609ECF,
+0xFF66A6D6,
+0xFF60A0D0,
+0xFF5E9ECE,
+0xFF63A3D3,
+0xFF62A1D4,
+0xFF60A2D4,
+0xFF62A1D4,
+0xFF60A2D4,
+0xFF62A1D4,
+0xFF60A2D4,
+0xFF60A2D4,
+0xFF5FA1D3,
+0xFF60A2D4,
+0xFF60A2D4,
+0xFF62A1D4,
+0xFF62A1D4,
+0xFF62A2D2,
+0xFF62A2D2,
+0xFF62A2D2,
+0xFF60A2D2,
+0xFF5CA3D1,
+0xFF5CA5D2,
+0xFF5DA4D2,
+0xFF5FA3D2,
+0xFF60A2D2,
+0xFF62A2D2,
+0xFF63A1D2,
+0xFF63A3D3,
+0xFF63A3D3,
+0xFF62A2D2,
+0xFF62A2D2,
+0xFF62A2D2,
+0xFF62A1D4,
+0xFF62A1D4,
+0xFF63A1D4,
+0xFF64A2D5,
+0xFF66A4D7,
+0xFF6B9ECB,
+0xFF84A2C6,
+0xFF4E5A74,
+0xFF131023,
+0xFF858CA6,
+0xFF6B9CC7,
+0xFF5DA0D4,
+0xFF5FA1D3,
+0xFF62A2D2,
+0xFF63A1D2,
+0xFF63A1D2,
+0xFF63A2D5,
+0xFF63A2D5,
+0xFF64A2D3,
+0xFF64A2D1,
+0xFF63A3D3,
+0xFF63A3D3,
+0xFF63A3D3,
+0xFF63A3D3,
+0xFF63A3D3,
+0xFF63A3D3,
+0xFF64A2D3,
+0xFF64A2D3,
+0xFF63A1D2,
+0xFF63A1D2,
+0xFF63A1D2,
+0xFF64A2D3,
+0xFF64A2D3,
+0xFF64A2D3,
+0xFF64A2D1,
+0xFF63A3D3,
+0xFF63A3D3,
+0xFF64A2D3,
+0xFF67A1CF,
+0xFF67A1CF,
+0xFF65A2D1,
+0xFF65A3D4,
+0xFF64A3D6,
+0xFF64A3D6,
+0xFF62A4D8,
+0xFF60A3D7,
+0xFF63A5D9,
+0xFF65A4D7,
+0xFF69A3D5,
+0xFF659DCE,
+0xFF70A6D2,
+0xFF6696BA,
+0xFF99BBD6,
+0xFFE5FFFF,
+0xFFBDE2FF,
+0xFF6B99BB,
+0xFF6A9FC7,
+0xFF649ECC,
+0xFF67A6D9,
+0xFF63A5D9,
+0xFF64A2D3,
+0xFF63A3D3,
+0xFF61A3D5,
+0xFF61A3D7,
+0xFF63A2D5,
+0xFF64A2D3,
+0xFF65A2D1,
+0xFF66A3D2,
+0xFF64A2D3,
+0xFF63A3D3,
+0xFF63A3D3,
+0xFF63A3D3,
+0xFF63A3D3,
+0xFF63A3D3,
+0xFF64A2D3,
+0xFF63A3D3,
+0xFF63A1D2,
+0xFF62A2D2,
+0xFF63A1D2,
+0xFF63A1D2,
+0xFF64A2D3,
+0xFF64A2D3,
+0xFF64A2D3,
+0xFF63A3D3,
+0xFF63A3D3,
+0xFF63A3D3,
+0xFF63A3D3,
+0xFF62A2D2,
+0xFF62A2D2,
+0xFF62A2D2,
+0xFF62A2D2,
+0xFF62A2D2,
+0xFF62A2D2,
+0xFF62A2D2,
+0xFF62A2D2,
+0xFF61A1D1,
+0xFF61A1D1,
+0xFF61A1D1,
+0xFF61A1D1,
+0xFF5FA1D1,
+0xFF5FA1D3,
+0xFF5FA1D3,
+0xFF5FA1D3,
+0xFF5FA1D3,
+0xFF5FA1D3,
+0xFF5FA1D3,
+0xFF5EA0D2,
+0xFF5EA0D2,
+0xFF5EA0D2,
+0xFF5CA0D1,
+0xFF5CA0D1,
+0xFF5B9FD0,
+0xFF5B9ED2,
+0xFF5B9ED2,
+0xFF5B9ED2,
+0xFF5B9ED2,
+0xFF5C9ED2,
+0xFF5C9ED2,
+0xFF5B9DD1,
+0xFF5B9DD1,
+0xFF599CD0,
+0xFF599CD0,
+0xFF599CD0,
+0xFF599CD0,
+0xFF599CD0,
+0xFF589BCF,
+0xFF589BCF,
+0xFF579ACE,
+0xFF5899CF,
+0xFF5798CE,
+0xFF5798CE,
+0xFF5798CE,
+0xFF5598CD,
+0xFF5598CD,
+0xFF5598CD,
+0xFF5598CD,
+0xFF5497CC,
+0xFF5497CC,
+0xFF5497CC,
+0xFF5396CB,
+0xFF5396CD,
+0xFF5295CC,
+0xFF5295CC,
+0xFF5194CB,
+0xFF5194CB,
+0xFF5093CA,
+0xFF5192CA,
+0xFF5192CA,
+0xFF4E89C5,
+0xFF4E89C5,
+0xFF4F8AC6,
+0xFF4F8BC7,
+0xFF4F8BC7,
+0xFF4F8BC7,
+0xFF508CC8,
+0xFF508CC8,
+0xFF508EC9,
+0xFF508EC9,
+0xFF518FCA,
+0xFF518FCA,
+0xFF528ECA,
+0xFF538FCB,
+0xFF538FCB,
+0xFF5491CA,
+0xFF5391CA,
+0xFF5492CB,
+0xFF5492CB,
+0xFF5593CC,
+0xFF5594CA,
+0xFF5594CA,
+0xFF5695CB,
+0xFF5695CB,
+0xFF5695CB,
+0xFF5695CB,
+0xFF5796CC,
+0xFF5796CC,
+0xFF5796CC,
+0xFF5796CC,
+0xFF5596CC,
+0xFF5596CC,
+0xFF5798CE,
+0xFF5699CE,
+0xFF5699CE,
+0xFF579ACF,
+0xFF5899CF,
+0xFF5899CF,
+0xFF599BCF,
+0xFF599BCF,
+0xFF5799CD,
+0xFF5799CD,
+0xFF589ACE,
+0xFF589ACE,
+0xFF5A99CE,
+0xFF5B9ACF,
+0xFF5B9ACF,
+0xFF5B9ACF,
+0xFF5C9BD0,
+0xFF5C9BD0,
+0xFF5C9BD0,
+0xFF5C9BD0,
+0xFF5C9BD0,
+0xFF5C9BD0,
+0xFF5C9BD0,
+0xFF5C9BD0,
+0xFF5D9CCF,
+0xFF5D9CCF,
+0xFF5D9CCF,
+0xFF5D9CCF,
+0xFF5D9CCF,
+0xFF5D9CCF,
+0xFF5D9CCF,
+0xFF5B9DCF,
+0xFF5A9CD0,
+0xFF5A9DD1,
+0xFF5A9DD1,
+0xFF5A9DD1,
+0xFF5A9DD1,
+0xFF5A9DD1,
+0xFF5B9ED2,
+0xFF5B9ED2,
+0xFF5B9ED2,
+0xFF5B9ED2,
+0xFF5B9ED2,
+0xFF5B9ED2,
+0xFF5B9ED2,
+0xFF5B9ED2,
+0xFF5B9ED2,
+0xFF5C9FD3,
+0xFF5B9FD0,
+0xFF5B9FD0,
+0xFF5B9FD0,
+0xFF5CA0D1,
+0xFF5CA0D1,
+0xFF5CA0D1,
+0xFF5CA0D1,
+0xFF5CA0D1,
+0xFF5B9FD0,
+0xFF5CA0D1,
+0xFF5DA1D2,
+0xFF5CA0D1,
+0xFF5CA0D1,
+0xFF5B9FD0,
+0xFF5CA0D1,
+0xFF5DA1D2,
+0xFF5CA0D1,
+0xFF5CA0D1,
+0xFF5D9FD1,
+0xFF5CA0D1,
+0xFF5D9FD1,
+0xFF5CA0D1,
+0xFF5EA0D2,
+0xFF5DA1D2,
+0xFF5CA0D1,
+0xFF5CA0D1,
+0xFF5CA0D1,
+0xFF5BA1D2,
+0xFF5DA1D2,
+0xFF5BA1D2,
+0xFF5DA1D2,
+0xFF5DA1D2,
+0xFF5FA1D3,
+0xFF5FA1D3,
+0xFF5FA1D3,
+0xFF5FA1D3,
+0xFF5FA1D3,
+0xFF5FA1D3,
+0xFF5FA1D3,
+0xFF5FA1D3,
+0xFF5FA1D3,
+0xFF5FA1D3,
+0xFF5FA1D3,
+0xFF5FA1D3,
+0xFF5FA1D3,
+0xFF5FA1D3,
+0xFF5FA1D3,
+0xFF5FA1D1,
+0xFF60A2D2,
+0xFF5D9FCF,
+0xFF5C9ECE,
+0xFF67A9D9,
+0xFF5D9DCD,
+0xFF5F9FCF,
+0xFF65A3D2,
+0xFF63A1D0,
+0xFF7CBAE9,
+0xFF62A0CF,
+0xFF64A2D3,
+0xFF63A1D2,
+0xFF61A1D1,
+0xFF5F9FCF,
+0xFF65A5D5,
+0xFF61A1D1,
+0xFF64A3D6,
+0xFF63A2D5,
+0xFF63A2D5,
+0xFF63A2D5,
+0xFF63A2D5,
+0xFF63A2D5,
+0xFF62A1D4,
+0xFF60A2D4,
+0xFF62A1D4,
+0xFF62A1D4,
+0xFF62A1D4,
+0xFF63A2D5,
+0xFF63A3D3,
+0xFF64A4D4,
+0xFF64A2D3,
+0xFF63A3D3,
+0xFF60A4D3,
+0xFF5EA5D3,
+0xFF60A4D3,
+0xFF61A3D3,
+0xFF63A3D3,
+0xFF63A3D3,
+0xFF64A2D3,
+0xFF65A3D4,
+0xFF64A4D4,
+0xFF63A3D3,
+0xFF63A3D3,
+0xFF63A3D3,
+0xFF64A2D5,
+0xFF64A2D5,
+0xFF65A1D5,
+0xFF66A2D6,
+0xFF659FD1,
+0xFF699FCE,
+0xFF70A0C8,
+0xFF819FBB,
+0xFF332F3D,
+0xFF505163,
+0xFF7DAAD1,
+0xFF62A4D4,
+0xFF64A4D2,
+0xFF66A3D2,
+0xFF68A2D4,
+0xFF66A2D6,
+0xFF64A4D4,
+0xFF61A3D3,
+0xFF63A3D3,
+0xFF63A3D1,
+0xFF64A4D4,
+0xFF64A4D4,
+0xFF64A4D4,
+0xFF64A4D4,
+0xFF65A3D4,
+0xFF65A3D4,
+0xFF65A3D4,
+0xFF65A3D4,
+0xFF65A3D4,
+0xFF65A3D4,
+0xFF65A3D4,
+0xFF65A3D4,
+0xFF65A3D4,
+0xFF65A3D4,
+0xFF65A3D2,
+0xFF66A4D3,
+0xFF64A3D6,
+0xFF65A3D4,
+0xFF68A3CF,
+0xFF69A2CF,
+0xFF67A4D1,
+0xFF66A4D5,
+0xFF63A5D7,
+0xFF63A5D9,
+0xFF65A3D6,
+0xFF65A3D4,
+0xFF65A3D4,
+0xFF67A4D3,
+0xFF64A1D0,
+0xFF6EA4D0,
+0xFF6A9AC0,
+0xFF94B8D8,
+0xFFE7FFFF,
+0xFFCEECFF,
+0xFF6D9BBF,
+0xFF689ECA,
+0xFF69A3D1,
+0xFF68A6D5,
+0xFF60A2D4,
+0xFF62A4D8,
+0xFF65A5D5,
+0xFF66A4D5,
+0xFF64A4D4,
+0xFF64A4D4,
+0xFF65A3D4,
+0xFF66A4D3,
+0xFF67A4D3,
+0xFF67A4D3,
+0xFF65A3D4,
+0xFF64A4D4,
+0xFF64A4D4,
+0xFF64A4D4,
+0xFF65A3D4,
+0xFF65A3D4,
+0xFF65A3D4,
+0xFF65A3D4,
+0xFF64A2D3,
+0xFF64A2D3,
+0xFF64A2D3,
+0xFF64A2D3,
+0xFF65A3D4,
+0xFF65A3D4,
+0xFF65A3D4,
+0xFF65A3D4,
+0xFF63A3D3,
+0xFF63A3D3,
+0xFF63A3D3,
+0xFF63A3D3,
+0xFF63A3D3,
+0xFF63A3D3,
+0xFF63A3D3,
+0xFF63A3D3,
+0xFF62A2D2,
+0xFF62A2D2,
+0xFF62A2D2,
+0xFF62A2D2,
+0xFF62A2D2,
+0xFF62A2D2,
+0xFF62A2D2,
+0xFF62A2D2,
+0xFF62A1D4,
+0xFF60A2D4,
+0xFF62A1D4,
+0xFF60A2D4,
+0xFF60A2D4,
+0xFF60A2D4,
+0xFF5FA1D3,
+0xFF5FA1D3,
+0xFF5FA1D3,
+0xFF5EA0D2,
+0xFF5EA0D2,
+0xFF5CA0D1,
+0xFF5C9FD3,
+0xFF5C9FD3,
+0xFF5C9FD3,
+0xFF5B9ED2,
+0xFF5D9FD3,
+0xFF5D9FD3,
+0xFF5C9ED2,
+0xFF5C9ED2,
+0xFF5A9DD1,
+0xFF5A9DD1,
+0xFF5A9DD1,
+0xFF599CD0,
+0xFF599CD0,
+0xFF589BCF,
+0xFF589BCF,
+0xFF589BCF,
+0xFF599AD0,
+0xFF599AD0,
+0xFF5899CF,
+0xFF599AD0,
+0xFF5699CE,
+0xFF5699CE,
+0xFF5598CD,
+0xFF5598CD,
+0xFF5497CC,
+0xFF5497CC,
+0xFF5497CC,
+0xFF5497CC,
+0xFF5396CD,
+0xFF5396CD,
+0xFF5396CD,
+0xFF5295CC,
+0xFF5194CB,
+0xFF5194CB,
+0xFF5293CB,
+0xFF5293CB,
+0xFF4D8AC3,
+0xFF4E8BC4,
+0xFF4F8CC5,
+0xFF4F8CC5,
+0xFF4F8CC5,
+0xFF4F8DC6,
+0xFF4F8DC6,
+0xFF508EC7,
+0xFF518FC8,
+0xFF518FC8,
+0xFF5290C9,
+0xFF5290C9,
+0xFF5390C9,
+0xFF5491CA,
+0xFF5592CB,
+0xFF5592CB,
+0xFF5492CB,
+0xFF5293C9,
+0xFF5594CA,
+0xFF5695CB,
+0xFF5695CB,
+0xFF5695CB,
+0xFF5695CB,
+0xFF5796CC,
+0xFF5695CB,
+0xFF5695CB,
+0xFF5796CC,
+0xFF5897CD,
+0xFF5897CC,
+0xFF5897CC,
+0xFF5897CC,
+0xFF5799CD,
+0xFF589ACE,
+0xFF589ACE,
+0xFF589ACE,
+0xFF589ACE,
+0xFF599BCF,
+0xFF599BCF,
+0xFF599BCF,
+0xFF599BCF,
+0xFF5A99CE,
+0xFF5A99CE,
+0xFF5B9ACF,
+0xFF5B9ACF,
+0xFF5B9ACF,
+0xFF5C9BD0,
+0xFF5C9BD0,
+0xFF5C9BD0,
+0xFF5D9CCF,
+0xFF5D9CCF,
+0xFF5E9DD0,
+0xFF5E9DD0,
+0xFF5E9DD0,
+0xFF5E9DD0,
+0xFF5E9DD0,
+0xFF5D9CCF,
+0xFF5B9DCF,
+0xFF5C9ED0,
+0xFF5C9ED0,
+0xFF5C9ED0,
+0xFF5C9ED0,
+0xFF5C9ED0,
+0xFF5C9ED0,
+0xFF5C9ED0,
+0xFF5C9ED0,
+0xFF5C9ED0,
+0xFF5C9ED0,
+0xFF5C9ED0,
+0xFF5C9ED0,
+0xFF5D9FD1,
+0xFF5D9FD1,
+0xFF5D9FD1,
+0xFF5D9FD1,
+0xFF5D9FD1,
+0xFF5D9FD1,
+0xFF5D9FD1,
+0xFF5D9FD1,
+0xFF5D9FD1,
+0xFF5D9FD1,
+0xFF5D9FD1,
+0xFF5D9FD1,
+0xFF5D9FD1,
+0xFF5D9FD1,
+0xFF5D9FD1,
+0xFF5D9FD1,
+0xFF5D9FD1,
+0xFF5D9FD1,
+0xFF5D9FD1,
+0xFF5D9FD1,
+0xFF5D9FD1,
+0xFF5EA0D2,
+0xFF5EA0D2,
+0xFF5D9FD1,
+0xFF5D9FD1,
+0xFF5D9FD1,
+0xFF5EA0D2,
+0xFF5EA0D2,
+0xFF5EA0D2,
+0xFF609FD2,
+0xFF5EA0D2,
+0xFF609FD2,
+0xFF5EA0D2,
+0xFF61A0D3,
+0xFF5FA1D3,
+0xFF5EA0D2,
+0xFF5FA1D3,
+0xFF5FA1D3,
+0xFF5EA2D3,
+0xFF5FA1D3,
+0xFF5FA3D4,
+0xFF60A2D4,
+0xFF60A2D4,
+0xFF5FA1D1,
+0xFF61A1D1,
+0xFF61A1D1,
+0xFF61A1D1,
+0xFF62A2D2,
+0xFF62A2D2,
+0xFF62A2D2,
+0xFF62A2D2,
+0xFF62A2D2,
+0xFF62A2D2,
+0xFF62A2D2,
+0xFF62A2D2,
+0xFF63A3D3,
+0xFF62A2D2,
+0xFF62A2D2,
+0xFF62A2D2,
+0xFF62A2D2,
+0xFF64A4D2,
+0xFF63A3D1,
+0xFF62A2D0,
+0xFF619FCE,
+0xFF66A4D3,
+0xFF609DCC,
+0xFF7EBBEA,
+0xFF6CA9D8,
+0xFF64A1D0,
+0xFF64A2D1,
+0xFF65A3D2,
+0xFF63A3D3,
+0xFF65A5D5,
+0xFF63A3D3,
+0xFF64A4D4,
+0xFF66A4D5,
+0xFF65A3D4,
+0xFF65A3D4,
+0xFF65A3D4,
+0xFF65A3D4,
+0xFF64A4D4,
+0xFF63A3D3,
+0xFF63A3D3,
+0xFF63A3D3,
+0xFF63A3D3,
+0xFF64A2D3,
+0xFF65A3D4,
+0xFF65A3D4,
+0xFF66A4D5,
+0xFF65A3D4,
+0xFF64A4D4,
+0xFF62A4D4,
+0xFF62A4D4,
+0xFF61A3D3,
+0xFF64A4D4,
+0xFF64A4D2,
+0xFF66A4D3,
+0xFF65A3D2,
+0xFF65A3D2,
+0xFF64A4D2,
+0xFF64A4D2,
+0xFF64A4D2,
+0xFF64A4D2,
+0xFF65A3D4,
+0xFF65A3D4,
+0xFF66A2D4,
+0xFF68A2D4,
+0xFF6CA4D5,
+0xFF69A1D0,
+0xFF6BA8D4,
+0xFF79A4C6,
+0xFF6A707E,
+0xFF323846,
+0xFF83ABCF,
+0xFF67A2CE,
+0xFF68A5D1,
+0xFF68A5D2,
+0xFF6DA2D8,
+0xFF69A2D7,
+0xFF63A5D5,
+0xFF60A7D3,
+0xFF63A5D5,
+0xFF65A5D5,
+0xFF65A5D5,
+0xFF65A5D5,
+0xFF65A5D5,
+0xFF65A5D5,
+0xFF65A5D3,
+0xFF65A5D3,
+0xFF65A5D3,
+0xFF65A5D3,
+0xFF66A4D3,
+0xFF66A4D3,
+0xFF66A4D3,
+0xFF66A4D3,
+0xFF66A4D3,
+0xFF66A4D3,
+0xFF66A4D3,
+0xFF66A4D3,
+0xFF66A4D7,
+0xFF66A4D5,
+0xFF67A4D0,
+0xFF67A4D0,
+0xFF67A4D1,
+0xFF66A6D6,
+0xFF63A7D8,
+0xFF64A6D8,
+0xFF68A4D6,
+0xFF6BA3D4,
+0xFF6AA2D1,
+0xFF67A2CE,
+0xFF6AA8CF,
+0xFF659BBF,
+0xFF92B6D6,
+0xFFE4FFFF,
+0xFFD6F6FF,
+0xFF789FBC,
+0xFF6D9EC6,
+0xFF6DA8D4,
+0xFF67A5D6,
+0xFF61A3D5,
+0xFF64A6D8,
+0xFF64A6D8,
+0xFF64A6D8,
+0xFF66A6D6,
+0xFF68A5D1,
+0xFF69A4D0,
+0xFF67A4D1,
+0xFF66A4D3,
+0xFF65A5D5,
+0xFF65A5D5,
+0xFF66A4D5,
+0xFF66A4D3,
+0xFF66A4D3,
+0xFF66A4D3,
+0xFF66A4D3,
+0xFF66A4D3,
+0xFF66A4D3,
+0xFF66A4D3,
+0xFF66A4D3,
+0xFF66A4D3,
+0xFF66A4D3,
+0xFF66A4D3,
+0xFF66A4D3,
+0xFF66A4D3,
+0xFF66A4D3,
+0xFF66A4D3,
+0xFF65A5D3,
+0xFF65A5D3,
+0xFF65A5D3,
+0xFF65A5D3,
+0xFF65A5D3,
+0xFF65A5D3,
+0xFF65A5D3,
+0xFF65A5D3,
+0xFF65A5D3,
+0xFF65A5D3,
+0xFF65A5D3,
+0xFF64A4D2,
+0xFF64A4D2,
+0xFF64A4D2,
+0xFF64A4D2,
+0xFF64A4D2,
+0xFF63A3D3,
+0xFF63A3D3,
+0xFF64A2D3,
+0xFF63A3D3,
+0xFF63A3D3,
+0xFF62A2D2,
+0xFF62A2D2,
+0xFF62A2D2,
+0xFF63A3D3,
+0xFF60A2D2,
+0xFF5FA1D3,
+0xFF5EA0D2,
+0xFF5EA0D2,
+0xFF5EA0D2,
+0xFF5D9FD1,
+0xFF5C9ED0,
+0xFF5EA0D2,
+0xFF5D9FD1,
+0xFF5D9FD1,
+0xFF5D9FD1,
+0xFF5B9FD0,
+0xFF5B9FD0,
+0xFF5A9DD1,
+0xFF5A9DD1,
+0xFF599CD0,
+0xFF599CD0,
+0xFF599CD0,
+0xFF599CD0,
+0xFF599AD0,
+0xFF599AD0,
+0xFF599AD0,
+0xFF599AD0,
+0xFF5798CE,
+0xFF5798CE,
+0xFF5798CE,
+0xFF5798CE,
+0xFF5697CD,
+0xFF5697CD,
+0xFF5497CC,
+0xFF5497CC,
+0xFF5497CC,
+0xFF5497CC,
+0xFF5396CB,
+0xFF5396CB,
+0xFF5295CA,
+0xFF5295CA,
+0xFF5295CA,
+0xFF5194C9,
+0xFF4E8BC4,
+0xFF4F8CC5,
+0xFF508DC6,
+0xFF508DC6,
+0xFF508EC7,
+0xFF508EC7,
+0xFF508EC7,
+0xFF518FC8,
+0xFF518FC8,
+0xFF5290C9,
+0xFF5290C9,
+0xFF5391CA,
+0xFF5491CA,
+0xFF5491CA,
+0xFF5592CB,
+0xFF5693CC,
+0xFF5594CA,
+0xFF5394CA,
+0xFF5695CB,
+0xFF5695CB,
+0xFF5695CB,
+0xFF5695CB,
+0xFF5796CC,
+0xFF5796CC,
+0xFF5796CC,
+0xFF5796CC,
+0xFF5897CD,
+0xFF5998CE,
+0xFF5998CD,
+0xFF5A99CE,
+0xFF5A99CE,
+0xFF5A99CE,
+0xFF589ACE,
+0xFF589ACE,
+0xFF589ACE,
+0xFF589ACE,
+0xFF599BCF,
+0xFF599BCF,
+0xFF599BCF,
+0xFF589ACE,
+0xFF5C9BD0,
+0xFF5C9BD0,
+0xFF5C9BD0,
+0xFF5C9BD0,
+0xFF5C9BD0,
+0xFF5D9CD1,
+0xFF5D9CD1,
+0xFF5D9CD1,
+0xFF5D9CCF,
+0xFF5E9DD0,
+0xFF5F9ED1,
+0xFF5F9ED1,
+0xFF609FD2,
+0xFF5F9ED1,
+0xFF5E9DD0,
+0xFF5E9DD0,
+0xFF5C9ED0,
+0xFF5D9FD1,
+0xFF5D9FD1,
+0xFF5D9FD1,
+0xFF5D9FD1,
+0xFF5D9FD1,
+0xFF5D9FD1,
+0xFF5D9FD1,
+0xFF5D9FD1,
+0xFF5D9FD1,
+0xFF5D9FD1,
+0xFF5D9FD1,
+0xFF5EA0D2,
+0xFF5EA0D2,
+0xFF5EA0D2,
+0xFF5EA0D2,
+0xFF5FA1D3,
+0xFF5EA0D2,
+0xFF5EA0D2,
+0xFF5EA0D2,
+0xFF609FD2,
+0xFF5EA0D2,
+0xFF609FD2,
+0xFF5EA0D2,
+0xFF5EA0D2,
+0xFF5EA0D2,
+0xFF5EA0D2,
+0xFF5EA0D2,
+0xFF5EA0D2,
+0xFF5EA0D2,
+0xFF5EA0D2,
+0xFF5EA0D2,
+0xFF5EA0D2,
+0xFF5FA1D3,
+0xFF5FA1D3,
+0xFF5FA1D3,
+0xFF5FA1D3,
+0xFF5FA1D3,
+0xFF5FA1D3,
+0xFF61A0D3,
+0xFF61A0D3,
+0xFF61A0D3,
+0xFF62A0D3,
+0xFF61A0D3,
+0xFF62A1D4,
+0xFF62A1D4,
+0xFF62A1D4,
+0xFF62A1D4,
+0xFF62A1D4,
+0xFF60A2D4,
+0xFF62A1D4,
+0xFF61A3D5,
+0xFF63A2D5,
+0xFF61A3D5,
+0xFF63A2D5,
+0xFF63A2D5,
+0xFF63A3D3,
+0xFF63A3D3,
+0xFF63A3D3,
+0xFF63A3D3,
+0xFF63A3D3,
+0xFF64A4D4,
+0xFF63A3D3,
+0xFF63A3D3,
+0xFF63A3D3,
+0xFF63A3D3,
+0xFF63A3D3,
+0xFF63A3D3,
+0xFF64A4D4,
+0xFF64A4D4,
+0xFF64A4D4,
+0xFF64A4D4,
+0xFF66A6D4,
+0xFF62A2D0,
+0xFF67A7D5,
+0xFF62A2D0,
+0xFF65A3D2,
+0xFF619FCE,
+0xFF83C0EF,
+0xFF68A5D4,
+0xFF619ECD,
+0xFF67A4D3,
+0xFF69A6D5,
+0xFF62A0CF,
+0xFF68A6D7,
+0xFF64A4D4,
+0xFF65A5D5,
+0xFF64A4D4,
+0xFF66A4D5,
+0xFF66A4D5,
+0xFF66A4D5,
+0xFF66A4D5,
+0xFF66A4D5,
+0xFF66A4D5,
+0xFF64A4D4,
+0xFF64A4D4,
+0xFF65A5D5,
+0xFF65A5D5,
+0xFF65A3D4,
+0xFF66A4D5,
+0xFF67A5D6,
+0xFF67A5D6,
+0xFF67A5D6,
+0xFF66A4D5,
+0xFF65A5D5,
+0xFF64A4D4,
+0xFF64A4D4,
+0xFF65A3D4,
+0xFF66A4D3,
+0xFF67A5D4,
+0xFF66A4D3,
+0xFF65A3D2,
+0xFF65A5D3,
+0xFF65A5D3,
+0xFF65A5D3,
+0xFF65A5D3,
+0xFF66A4D5,
+0xFF66A4D5,
+0xFF67A3D5,
+0xFF67A4D3,
+0xFF6AA4D2,
+0xFF67A4D3,
+0xFF60A2D4,
+0xFF6EA2CA,
+0xFF92A6BE,
+0xFF2B3A4F,
+0xFF6285A5,
+0xFF76A7CF,
+0xFF69A4CE,
+0xFF67A4D1,
+0xFF6AA1D7,
+0xFF69A2D7,
+0xFF62A6D3,
+0xFF61A8D4,
+0xFF64A6D6,
+0xFF66A6D6,
+0xFF65A5D5,
+0xFF65A5D5,
+0xFF65A5D5,
+0xFF65A5D5,
+0xFF65A5D3,
+0xFF65A5D3,
+0xFF65A5D3,
+0xFF65A5D3,
+0xFF66A4D3,
+0xFF66A4D3,
+0xFF66A4D3,
+0xFF66A4D3,
+0xFF66A4D3,
+0xFF66A4D3,
+0xFF66A4D3,
+0xFF66A4D3,
+0xFF67A5D6,
+0xFF67A5D6,
+0xFF67A6D2,
+0xFF67A6D2,
+0xFF67A6D2,
+0xFF66A6D4,
+0xFF64A6D6,
+0xFF66A6D6,
+0xFF68A4D6,
+0xFF6CA6D4,
+0xFF6EA4D2,
+0xFF6CA3CA,
+0xFF689EC0,
+0xFF8AB9D5,
+0xFFE0FEFF,
+0xFFDBF9FF,
+0xFF82ABC9,
+0xFF6B9DC2,
+0xFF6CA3CC,
+0xFF69A6D3,
+0xFF65A5D5,
+0xFF67A9DB,
+0xFF64A4D2,
+0xFF6CAAD9,
+0xFF66A6D6,
+0xFF66A6D4,
+0xFF68A5D1,
+0xFF6AA5D1,
+0xFF67A6D2,
+0xFF65A5D3,
+0xFF65A5D5,
+0xFF65A5D5,
+0xFF66A6D4,
+0xFF67A5D4,
+0xFF67A5D4,
+0xFF67A5D4,
+0xFF67A5D4,
+0xFF67A5D4,
+0xFF67A5D4,
+0xFF67A5D4,
+0xFF67A5D4,
+0xFF67A5D4,
+0xFF67A5D4,
+0xFF67A5D4,
+0xFF67A5D4,
+0xFF66A4D3,
+0xFF66A4D3,
+0xFF66A4D3,
+0xFF65A5D3,
+0xFF65A5D3,
+0xFF65A5D3,
+0xFF65A5D3,
+0xFF65A5D3,
+0xFF65A5D3,
+0xFF65A5D3,
+0xFF65A5D3,
+0xFF66A6D4,
+0xFF66A6D4,
+0xFF65A5D3,
+0xFF65A5D3,
+0xFF65A5D3,
+0xFF65A5D3,
+0xFF65A5D3,
+0xFF65A5D3,
+0xFF66A4D5,
+0xFF66A4D5,
+0xFF65A3D4,
+0xFF65A3D4,
+0xFF64A4D4,
+0xFF63A3D3,
+0xFF63A3D3,
+0xFF62A2D2,
+0xFF64A4D4,
+0xFF63A3D3,
+0xFF60A2D4,
+0xFF60A2D4,
+0xFF5FA1D3,
+0xFF5FA1D3,
+0xFF5EA0D2,
+0xFF5EA0D2,
+0xFF5FA1D3,
+0xFF5EA0D2,
+0xFF5EA0D2,
+0xFF5EA0D2,
+0xFF5CA0D1,
+0xFF5CA0D1,
+0xFF5B9ED2,
+0xFF5B9ED2,
+0xFF5B9ED2,
+0xFF5B9ED2,
+0xFF5A9DD1,
+0xFF5A9DD1,
+0xFF5A9BD1,
+0xFF5A9BD1,
+0xFF599AD0,
+0xFF599AD0,
+0xFF599AD0,
+0xFF599AD0,
+0xFF5899CF,
+0xFF5899CF,
+0xFF5798CE,
+0xFF5798CE,
+0xFF5699CE,
+0xFF5598CD,
+0xFF5598CD,
+0xFF5598CD,
+0xFF5497CC,
+0xFF5497CC,
+0xFF5396CB,
+0xFF5396CB,
+0xFF5295CA,
+0xFF5295CA,
+0xFF4E8CC5,
+0xFF4F8DC6,
+0xFF508EC7,
+0xFF518FC8,
+0xFF518FC8,
+0xFF518FC8,
+0xFF5290C9,
+0xFF5290C9,
+0xFF5290C9,
+0xFF5391CA,
+0xFF5491CA,
+0xFF5592CB,
+0xFF5592CB,
+0xFF5592CB,
+0xFF5792CC,
+0xFF5794CD,
+0xFF5594CA,
+0xFF5495CB,
+0xFF5596CC,
+0xFF5596CC,
+0xFF5596CC,
+0xFF5596CC,
+0xFF5796CC,
+0xFF5897CD,
+0xFF5998CD,
+0xFF5998CD,
+0xFF5998CD,
+0xFF5A99CE,
+0xFF5B9ACF,
+0xFF5B9ACF,
+0xFF5B9ACF,
+0xFF5B9ACF,
+0xFF5B9ACF,
+0xFF5B9ACF,
+0xFF5A99CE,
+0xFF5B9ACF,
+0xFF5B9ACF,
+0xFF5C9BD0,
+0xFF5C9BD0,
+0xFF5B9ACF,
+0xFF5D9CD1,
+0xFF5D9CD1,
+0xFF5D9CD1,
+0xFF5D9CD1,
+0xFF5E9DD2,
+0xFF5E9DD2,
+0xFF5E9DD2,
+0xFF5E9DD2,
+0xFF5E9DD0,
+0xFF5E9DD0,
+0xFF5F9ED1,
+0xFF5F9ED1,
+0xFF5F9ED1,
+0xFF5F9ED1,
+0xFF5F9FCF,
+0xFF5F9FCF,
+0xFF5EA0D0,
+0xFF5EA0D0,
+0xFF5EA0D0,
+0xFF5EA0D0,
+0xFF5FA1D1,
+0xFF5FA1D1,
+0xFF5FA1D1,
+0xFF5FA1D1,
+0xFF61A1D1,
+0xFF61A1D1,
+0xFF61A1D1,
+0xFF61A1D1,
+0xFF61A1D1,
+0xFF61A1D1,
+0xFF61A1D1,
+0xFF61A1D1,
+0xFF61A1D1,
+0xFF61A1D1,
+0xFF61A1D1,
+0xFF61A1D1,
+0xFF62A0D1,
+0xFF61A1D1,
+0xFF62A0D1,
+0xFF61A1D1,
+0xFF61A1D1,
+0xFF62A2D2,
+0xFF62A2D2,
+0xFF62A2D2,
+0xFF62A2D2,
+0xFF62A2D2,
+0xFF62A2D2,
+0xFF62A2D2,
+0xFF63A3D3,
+0xFF62A2D2,
+0xFF62A2D2,
+0xFF62A2D2,
+0xFF63A3D3,
+0xFF63A3D3,
+0xFF62A2D2,
+0xFF62A2D2,
+0xFF64A2D3,
+0xFF64A2D3,
+0xFF65A1D3,
+0xFF64A2D3,
+0xFF64A2D3,
+0xFF64A2D3,
+0xFF64A2D3,
+0xFF64A2D3,
+0xFF65A3D4,
+0xFF64A4D4,
+0xFF65A3D4,
+0xFF64A4D4,
+0xFF65A3D4,
+0xFF64A4D4,
+0xFF65A3D4,
+0xFF65A3D4,
+0xFF66A4D5,
+0xFF65A3D4,
+0xFF65A3D4,
+0xFF65A3D4,
+0xFF66A4D5,
+0xFF66A4D5,
+0xFF66A4D5,
+0xFF66A4D5,
+0xFF65A3D4,
+0xFF65A3D4,
+0xFF65A3D4,
+0xFF65A3D4,
+0xFF66A4D5,
+0xFF66A4D5,
+0xFF67A5D6,
+0xFF67A5D6,
+0xFF67A7D5,
+0xFF63A3D1,
+0xFF67A6D2,
+0xFF69A8D4,
+0xFF63A0CD,
+0xFF7FBCE9,
+0xFF6EA8D6,
+0xFF629CCA,
+0xFF69A3D1,
+0xFF69A6D3,
+0xFF65A2D1,
+0xFF66A4D3,
+0xFF67A5D6,
+0xFF64A2D3,
+0xFF67A6D9,
+0xFF64A4D4,
+0xFF67A5D6,
+0xFF67A4D3,
+0xFF66A4D3,
+0xFF66A4D3,
+0xFF67A5D4,
+0xFF67A5D4,
+0xFF65A5D3,
+0xFF65A5D3,
+0xFF67A7D5,
+0xFF66A6D4,
+0xFF65A5D3,
+0xFF66A6D4,
+0xFF68A6D7,
+0xFF68A6D7,
+0xFF67A5D6,
+0xFF66A4D5,
+0xFF67A5D6,
+0xFF67A5D6,
+0xFF67A5D4,
+0xFF68A5D4,
+0xFF68A5D4,
+0xFF68A5D4,
+0xFF67A6D2,
+0xFF67A6D2,
+0xFF66A6D2,
+0xFF64A7D2,
+0xFF64A7D2,
+0xFF64A7D2,
+0xFF66A6D4,
+0xFF66A6D4,
+0xFF67A5D4,
+0xFF67A5D4,
+0xFF64A4D0,
+0xFF66A9D6,
+0xFF63A2D8,
+0xFF6EA3D7,
+0xFF7BA0CA,
+0xFF7E9BBD,
+0xFF203A5B,
+0xFF8AAED0,
+0xFF6EA3CF,
+0xFF66A4D5,
+0xFF67A4D3,
+0xFF66A4D3,
+0xFF62A6D3,
+0xFF63A7D4,
+0xFF68A4D6,
+0xFF69A5D7,
+0xFF66A6D4,
+0xFF64A7D4,
+0xFF64A7D4,
+0xFF64A7D4,
+0xFF64A7D4,
+0xFF64A7D4,
+0xFF66A6D4,
+0xFF66A6D4,
+0xFF66A6D4,
+0xFF66A6D4,
+0xFF66A6D4,
+0xFF66A6D4,
+0xFF66A6D4,
+0xFF66A6D4,
+0xFF67A7D5,
+0xFF67A7D5,
+0xFF67A7D5,
+0xFF67A7D7,
+0xFF67A7D7,
+0xFF67A7D5,
+0xFF68A6D5,
+0xFF68A7D3,
+0xFF68A7D3,
+0xFF68A6D5,
+0xFF66A6D4,
+0xFF66A6D2,
+0xFF6AA4CC,
+0xFF72A4C7,
+0xFF83AAC7,
+0xFFDEFEFF,
+0xFFE0FBFF,
+0xFF8DB0C6,
+0xFF689CC1,
+0xFF6BA8D5,
+0xFF6BA9D8,
+0xFF62A2D0,
+0xFF67A7D7,
+0xFF68A8D6,
+0xFF67A4D0,
+0xFF68A3CD,
+0xFF6AA5D1,
+0xFF68A5D1,
+0xFF67A7D5,
+0xFF67A7D5,
+0xFF67A7D5,
+0xFF67A7D5,
+0xFF66A6D4,
+0xFF66A6D4,
+0xFF67A7D5,
+0xFF67A7D5,
+0xFF67A7D5,
+0xFF66A6D4,
+0xFF66A6D4,
+0xFF67A7D5,
+0xFF67A7D5,
+0xFF67A7D5,
+0xFF66A6D4,
+0xFF66A6D4,
+0xFF67A5D4,
+0xFF67A5D4,
+0xFF67A5D4,
+0xFF67A5D4,
+0xFF67A5D4,
+0xFF67A5D4,
+0xFF67A5D4,
+0xFF67A5D4,
+0xFF67A5D4,
+0xFF67A5D4,
+0xFF67A5D4,
+0xFF67A5D4,
+0xFF67A5D4,
+0xFF67A5D4,
+0xFF67A5D4,
+0xFF67A5D4,
+0xFF67A5D4,
+0xFF66A4D3,
+0xFF66A4D3,
+0xFF66A4D3,
+0xFF66A4D3,
+0xFF66A4D3,
+0xFF68A5D4,
+0xFF68A5D4,
+0xFF66A4D3,
+0xFF66A4D3,
+0xFF66A4D5,
+0xFF66A4D5,
+0xFF65A3D4,
+0xFF65A3D4,
+0xFF65A5D5,
+0xFF64A4D4,
+0xFF63A3D3,
+0xFF63A3D3,
+0xFF63A3D3,
+0xFF63A3D3,
+0xFF61A3D3,
+0xFF60A2D2,
+0xFF60A2D2,
+0xFF60A2D2,
+0xFF5EA2D1,
+0xFF5EA2D1,
+0xFF5DA1D2,
+0xFF5DA1D2,
+0xFF5CA0D1,
+0xFF5CA0D1,
+0xFF5C9FD3,
+0xFF5C9FD3,
+0xFF5B9ED2,
+0xFF5B9ED2,
+0xFF5A9DD2,
+0xFF5A9DD2,
+0xFF5A9BD1,
+0xFF5A9BD1,
+0xFF5A9BD1,
+0xFF5A9BD1,
+0xFF599AD0,
+0xFF599AD0,
+0xFF5899CF,
+0xFF5899CF,
+0xFF579ACF,
+0xFF5699CE,
+0xFF5699CE,
+0xFF5699CE,
+0xFF5598CD,
+0xFF5598CD,
+0xFF5298CC,
+0xFF5298CC,
+0xFF5298CC,
+0xFF5298CC,
+0xFF508DC6,
+0xFF508EC7,
+0xFF528FC8,
+0xFF518FC8,
+0xFF5290C9,
+0xFF5290C9,
+0xFF5391CA,
+0xFF5391CA,
+0xFF5391CA,
+0xFF5492CB,
+0xFF5592CB,
+0xFF5592CB,
+0xFF5693CC,
+0xFF5693CC,
+0xFF5794CD,
+0xFF5895CE,
+0xFF5695CB,
+0xFF5596CC,
+0xFF5596CC,
+0xFF5697CD,
+0xFF5596CC,
+0xFF5596CC,
+0xFF5897CD,
+0xFF5897CD,
+0xFF5A99CE,
+0xFF5A99CE,
+0xFF5A99CE,
+0xFF5B9ACF,
+0xFF5B9ACF,
+0xFF5C9BD0,
+0xFF5C9BD0,
+0xFF5C9BD0,
+0xFF5C9BD0,
+0xFF5B9ACF,
+0xFF5B9ACF,
+0xFF5C9BD0,
+0xFF5D9CD1,
+0xFF5D9CD1,
+0xFF5D9CD1,
+0xFF5D9CCF,
+0xFF5E9DD2,
+0xFF5E9DD0,
+0xFF5E9DD2,
+0xFF5E9DD0,
+0xFF5E9DD0,
+0xFF5F9ED1,
+0xFF5F9ED1,
+0xFF5F9ED1,
+0xFF609FD2,
+0xFF609FD2,
+0xFF609FD2,
+0xFF609FD2,
+0xFF609FD2,
+0xFF609FD2,
+0xFF61A1D1,
+0xFF61A1D1,
+0xFF61A1D1,
+0xFF5FA1D1,
+0xFF61A1D1,
+0xFF5FA1D1,
+0xFF62A2D2,
+0xFF60A2D2,
+0xFF62A2D2,
+0xFF62A2D0,
+0xFF62A2D2,
+0xFF62A2D2,
+0xFF61A1D1,
+0xFF61A1D1,
+0xFF61A1D1,
+0xFF61A1CF,
+0xFF62A0CF,
+0xFF62A0D1,
+0xFF62A0D3,
+0xFF62A0D3,
+0xFF62A0D1,
+0xFF61A1D1,
+0xFF61A1CF,
+0xFF61A1CF,
+0xFF63A1D2,
+0xFF63A1D2,
+0xFF63A1D0,
+0xFF62A2D0,
+0xFF63A3D3,
+0xFF63A3D3,
+0xFF63A3D3,
+0xFF64A4D4,
+0xFF64A4D4,
+0xFF64A4D4,
+0xFF64A4D4,
+0xFF63A3D3,
+0xFF63A3D3,
+0xFF63A3D3,
+0xFF64A4D4,
+0xFF64A4D4,
+0xFF63A3D3,
+0xFF63A1D2,
+0xFF66A2D4,
+0xFF66A2D4,
+0xFF66A2D4,
+0xFF65A3D4,
+0xFF64A4D4,
+0xFF64A4D4,
+0xFF64A4D4,
+0xFF64A4D4,
+0xFF66A4D5,
+0xFF66A4D3,
+0xFF66A4D3,
+0xFF66A4D3,
+0xFF66A4D3,
+0xFF65A3D2,
+0xFF65A3D4,
+0xFF65A3D4,
+0xFF65A3D2,
+0xFF65A3D2,
+0xFF64A4D4,
+0xFF64A4D4,
+0xFF66A4D5,
+0xFF66A4D5,
+0xFF66A4D5,
+0xFF65A3D4,
+0xFF66A4D5,
+0xFF66A4D5,
+0xFF66A4D5,
+0xFF66A4D3,
+0xFF66A4D3,
+0xFF68A5D2,
+0xFF6EA4D2,
+0xFF6DA6D3,
+0xFF68A5D2,
+0xFF67A6D2,
+0xFF64A3CF,
+0xFF63A2CD,
+0xFF82BFEC,
+0xFF69A6D3,
+0xFF68A2D0,
+0xFF6AA4D2,
+0xFF6AA4D2,
+0xFF66A3D0,
+0xFF6AA7D6,
+0xFF68A5D4,
+0xFF68A6D7,
+0xFF67A5D6,
+0xFF66A6D6,
+0xFF68A6D7,
+0xFF67A5D4,
+0xFF67A5D4,
+0xFF67A5D4,
+0xFF67A5D4,
+0xFF67A5D4,
+0xFF68A6D5,
+0xFF66A6D4,
+0xFF66A6D4,
+0xFF67A7D5,
+0xFF66A6D4,
+0xFF66A6D4,
+0xFF66A6D4,
+0xFF68A6D5,
+0xFF68A6D5,
+0xFF67A5D6,
+0xFF66A4D3,
+0xFF67A5D6,
+0xFF67A5D4,
+0xFF68A6D5,
+0xFF68A6D5,
+0xFF68A5D4,
+0xFF67A5D4,
+0xFF67A6D2,
+0xFF67A7D3,
+0xFF67A7D3,
+0xFF65A8D3,
+0xFF65A8D3,
+0xFF67A7D3,
+0xFF67A7D5,
+0xFF67A7D5,
+0xFF68A6D5,
+0xFF67A7D3,
+0xFF64A9D3,
+0xFF66AAD7,
+0xFF65A7DB,
+0xFF68A4DA,
+0xFF6EA0D3,
+0xFF86ABD7,
+0xFF425979,
+0xFF6E88A9,
+0xFF72A5D0,
+0xFF69A7D6,
+0xFF69A7D6,
+0xFF67A7D5,
+0xFF64A8D5,
+0xFF64A8D5,
+0xFF69A6D5,
+0xFF6CA6D6,
+0xFF68A6D5,
+0xFF67A7D3,
+0xFF67A7D3,
+0xFF67A7D5,
+0xFF67A7D5,
+0xFF67A7D5,
+0xFF67A7D5,
+0xFF67A7D5,
+0xFF67A7D5,
+0xFF67A7D5,
+0xFF67A7D5,
+0xFF67A7D5,
+0xFF68A8D6,
+0xFF66A9D6,
+0xFF68A8D6,
+0xFF66A9D6,
+0xFF68A8D6,
+0xFF66A9D6,
+0xFF66A8D8,
+0xFF67A7D7,
+0xFF68A6D5,
+0xFF68A7D3,
+0xFF69A6D3,
+0xFF69A6D3,
+0xFF66A9D4,
+0xFF6CABD4,
+0xFF6BA0C2,
+0xFF85AECA,
+0xFFDFFBFF,
+0xFFE3FCFF,
+0xFF9CBCD3,
+0xFF709DBA,
+0xFF6CA7D1,
+0xFF63A5D5,
+0xFF66A8D8,
+0xFF6CACDA,
+0xFF63A3D1,
+0xFF66A5D1,
+0xFF6DA8D4,
+0xFF6CA7D1,
+0xFF6BA6D0,
+0xFF69A6D2,
+0xFF68A8D6,
+0xFF66A8D8,
+0xFF68A8D6,
+0xFF68A8D6,
+0xFF69A8D4,
+0xFF68A7D3,
+0xFF68A8D6,
+0xFF68A8D6,
+0xFF67A7D5,
+0xFF67A7D5,
+0xFF67A7D5,
+0xFF67A7D5,
+0xFF68A8D6,
+0xFF68A8D6,
+0xFF67A7D5,
+0xFF67A7D5,
+0xFF68A6D5,
+0xFF68A6D5,
+0xFF69A7D6,
+0xFF69A7D6,
+0xFF69A7D6,
+0xFF69A7D6,
+0xFF68A6D5,
+0xFF68A6D5,
+0xFF68A6D5,
+0xFF68A6D5,
+0xFF68A6D5,
+0xFF68A6D5,
+0xFF68A6D5,
+0xFF68A6D5,
+0xFF68A6D5,
+0xFF68A6D5,
+0xFF68A6D5,
+0xFF68A6D5,
+0xFF68A6D5,
+0xFF67A5D4,
+0xFF67A5D4,
+0xFF67A5D4,
+0xFF68A5D4,
+0xFF68A5D4,
+0xFF67A5D4,
+0xFF67A5D4,
+0xFF67A5D4,
+0xFF67A5D4,
+0xFF67A5D6,
+0xFF66A4D3,
+0xFF65A5D5,
+0xFF64A4D2,
+0xFF64A4D4,
+0xFF64A4D2,
+0xFF64A4D4,
+0xFF65A5D3,
+0xFF64A4D4,
+0xFF62A4D4,
+0xFF61A3D3,
+0xFF60A2D2,
+0xFF5FA3D2,
+0xFF5FA3D2,
+0xFF5EA2D3,
+0xFF5DA1D2,
+0xFF5DA1D2,
+0xFF5DA1D2,
+0xFF5CA0D1,
+0xFF5C9FD3,
+0xFF5C9FD3,
+0xFF5B9ED2,
+0xFF5B9ED2,
+0xFF5B9ED2,
+0xFF5C9DD3,
+0xFF5C9DD3,
+0xFF5A9BD1,
+0xFF5A9BD1,
+0xFF5A9BD1,
+0xFF599AD0,
+0xFF599AD0,
+0xFF5899CF,
+0xFF579ACF,
+0xFF579ACF,
+0xFF579ACF,
+0xFF5699CE,
+0xFF5699CE,
+0xFF5598CD,
+0xFF5598CD,
+0xFF5399CD,
+0xFF5497CC,
+0xFF5298CC,
+0xFF528DC7,
+0xFF528FC8,
+0xFF548FC9,
+0xFF5390C9,
+0xFF5390C9,
+0xFF5390C9,
+0xFF5491CA,
+0xFF5592CB,
+0xFF5592C9,
+0xFF5592C9,
+0xFF5592C9,
+0xFF5693CA,
+0xFF5695CB,
+0xFF5796CC,
+0xFF5695CB,
+0xFF5695CB,
+0xFF5897CD,
+0xFF5897CD,
+0xFF5897CD,
+0xFF5897CD,
+0xFF5998CE,
+0xFF5998CE,
+0xFF5A99CE,
+0xFF5A99CE,
+0xFF5B9ACF,
+0xFF5B9ACF,
+0xFF5B9ACF,
+0xFF5B9ACF,
+0xFF5B9ACF,
+0xFF5B9ACF,
+0xFF5C9BCE,
+0xFF5C9BCE,
+0xFF599BCD,
+0xFF5A9CCE,
+0xFF5B9DCF,
+0xFF5B9DCF,
+0xFF5D9CCF,
+0xFF5D9CCF,
+0xFF5E9DD0,
+0xFF5F9FCF,
+0xFF5F9ED1,
+0xFF5F9FCF,
+0xFF609ED1,
+0xFF609ECF,
+0xFF609ECF,
+0xFF619FD0,
+0xFF619FD0,
+0xFF62A0D1,
+0xFF619FD2,
+0xFF619FD2,
+0xFF62A0D1,
+0xFF62A0D1,
+0xFF62A0D1,
+0xFF62A0D1,
+0xFF63A1D2,
+0xFF64A2D3,
+0xFF63A1D0,
+0xFF62A2D0,
+0xFF63A1D0,
+0xFF62A2D0,
+0xFF63A1D0,
+0xFF63A3D1,
+0xFF64A2D1,
+0xFF63A3CF,
+0xFF63A3D1,
+0xFF63A3D1,
+0xFF61A3D3,
+0xFF63A3D3,
+0xFF63A3D1,
+0xFF64A3CF,
+0xFF68A2D0,
+0xFF69A1D2,
+0xFF67A0D7,
+0xFF65A1D7,
+0xFF63A2D5,
+0xFF61A3D3,
+0xFF62A5D0,
+0xFF62A5D0,
+0xFF64A4D2,
+0xFF65A3D2,
+0xFF65A4D0,
+0xFF65A4D0,
+0xFF64A4D2,
+0xFF63A5D5,
+0xFF62A4D4,
+0xFF61A3D3,
+0xFF63A3D3,
+0xFF64A4D2,
+0xFF66A4D3,
+0xFF64A2D1,
+0xFF62A2D0,
+0xFF66A6D4,
+0xFF60A2D2,
+0xFF65A5D5,
+0xFF64A4D2,
+0xFF65A3D2,
+0xFF66A3D2,
+0xFF66A3D2,
+0xFF65A3D2,
+0xFF64A4D2,
+0xFF63A5D5,
+0xFF62A6D5,
+0xFF60A7D5,
+0xFF62A6D5,
+0xFF65A5D3,
+0xFF66A5D1,
+0xFF67A4D0,
+0xFF67A5CE,
+0xFF68A5D1,
+0xFF67A6D2,
+0xFF65A5D3,
+0xFF64A4D2,
+0xFF67A4D1,
+0xFF67A6D2,
+0xFF61A5D2,
+0xFF62A9D5,
+0xFF68A8D6,
+0xFF66A4D3,
+0xFF65A5D5,
+0xFF65A4D7,
+0xFF69A7DA,
+0xFF64A2D5,
+0xFF6CA9D8,
+0xFF65A4CF,
+0xFF66A5CE,
+0xFF7AB4DA,
+0xFF446E96,
+0xFF709AC2,
+0xFF71A8D1,
+0xFF66A3CF,
+0xFF619ECA,
+0xFF83C1EA,
+0xFF65A2CE,
+0xFF69A6D2,
+0xFF6BA8D4,
+0xFF66A3CF,
+0xFF69A6D3,
+0xFF68A7D3,
+0xFF68A7D3,
+0xFF68A7D3,
+0xFF67A5D4,
+0xFF67A5D4,
+0xFF67A5D4,
+0xFF68A6D5,
+0xFF68A6D5,
+0xFF67A7D3,
+0xFF67A7D3,
+0xFF67A7D3,
+0xFF67A7D3,
+0xFF67A7D3,
+0xFF67A7D3,
+0xFF67A7D3,
+0xFF68A8D4,
+0xFF67A7D3,
+0xFF67A7D3,
+0xFF67A7D3,
+0xFF67A7D3,
+0xFF67A7D3,
+0xFF68A8D6,
+0xFF68A8D4,
+0xFF68A8D6,
+0xFF67A7D3,
+0xFF67A7D3,
+0xFF68A8D4,
+0xFF69A8D4,
+0xFF68A8D4,
+0xFF68A8D4,
+0xFF68A8D4,
+0xFF67A7D3,
+0xFF68A8D4,
+0xFF68A8D4,
+0xFF69A8D4,
+0xFF69A8D4,
+0xFF68A7D3,
+0xFF69A8D4,
+0xFF68A8D4,
+0xFF66A9D4,
+0xFF65AAD4,
+0xFF63A7D4,
+0xFF69A9D7,
+0xFF6EA8D8,
+0xFF749FCA,
+0xFF7F91B5,
+0xFF516588,
+0xFF75A9CE,
+0xFF68A9D3,
+0xFF69A5D7,
+0xFF69A7DA,
+0xFF63A7D4,
+0xFF63A8D2,
+0xFF68A8D4,
+0xFF6AA9D4,
+0xFF68A7D2,
+0xFF69A8D3,
+0xFF69A8D3,
+0xFF66A5D1,
+0xFF6BA8D5,
+0xFF6AA7D4,
+0xFF6BA8D7,
+0xFF67A5D4,
+0xFF69A7D6,
+0xFF68A8D6,
+0xFF68A8D6,
+0xFF66A9D6,
+0xFF65A8D3,
+0xFF64A9D3,
+0xFF65A8D3,
+0xFF65A8D3,
+0xFF67A7D5,
+0xFF68A8D6,
+0xFF6AAAD8,
+0xFF66A6D4,
+0xFF69A7D6,
+0xFF67A5D4,
+0xFF6CA9D8,
+0xFF6DAAD7,
+0xFF6BAAD5,
+0xFF6CA4C7,
+0xFF85AEC4,
+0xFFDCF9FF,
+0xFFE8FDFF,
+0xFFA7C3D9,
+0xFF709EC0,
+0xFF6DA8D2,
+0xFF69A8D4,
+0xFF68A8D6,
+0xFF69A9D7,
+0xFF69A8D4,
+0xFF69A8D4,
+0xFF69A8D4,
+0xFF6AA7D4,
+0xFF6AA7D3,
+0xFF6AA7D3,
+0xFF69A8D4,
+0xFF69A8D4,
+0xFF67A7D5,
+0xFF69A8D4,
+0xFF69A8D4,
+0xFF69A8D4,
+0xFF69A8D4,
+0xFF68A7D3,
+0xFF69A8D4,
+0xFF69A8D4,
+0xFF69A8D4,
+0xFF69A8D4,
+0xFF69A8D4,
+0xFF68A7D3,
+0xFF68A7D3,
+0xFF68A7D3,
+0xFF68A7D3,
+0xFF68A7D3,
+0xFF68A7D3,
+0xFF68A7D3,
+0xFF69A8D4,
+0xFF69A8D4,
+0xFF69A8D4,
+0xFF68A7D3,
+0xFF68A7D3,
+0xFF68A7D3,
+0xFF68A7D3,
+0xFF69A8D4,
+0xFF69A8D4,
+0xFF69A8D4,
+0xFF69A8D4,
+0xFF68A7D3,
+0xFF68A7D3,
+0xFF68A7D3,
+0xFF68A7D3,
+0xFF68A7D3,
+0xFF68A7D3,
+0xFF68A7D3,
+0xFF68A7D3,
+0xFF68A7D3,
+0xFF68A7D3,
+0xFF68A7D3,
+0xFF68A7D3,
+0xFF68A7D3,
+0xFF67A6D2,
+0xFF67A5D4,
+0xFF67A6D2,
+0xFF68A6D5,
+0xFF67A6D2,
+0xFF67A5D4,
+0xFF67A6D2,
+0xFF66A4D3,
+0xFF66A5D1,
+0xFF66A4D3,
+0xFF65A5D3,
+0xFF62A5D2,
+0xFF62A5D2,
+0xFF61A4D1,
+0xFF61A4D1,
+0xFF61A3D3,
+0xFF61A3D3,
+0xFF60A2D2,
+0xFF60A2D2,
+0xFF5FA1D1,
+0xFF5EA0D2,
+0xFF5CA0D1,
+0xFF5CA0D1,
+0xFF5CA0D1,
+0xFF5DA1D2,
+0xFF5C9FD3,
+0xFF5B9ED2,
+0xFF5A9DD1,
+0xFF5A9DD1,
+0xFF5A9DD1,
+0xFF5A9DD1,
+0xFF599CD0,
+0xFF589BCF,
+0xFF589BD0,
+0xFF589BD0,
+0xFF589BD0,
+0xFF579ACF,
+0xFF5798CE,
+0xFF5798CE,
+0xFF5798CE,
+0xFF5699CE,
+0xFF5697CD,
+0xFF5598CD,
+0xFF528DC7,
+0xFF538EC8,
+0xFF548FC9,
+0xFF5590CA,
+0xFF5390C9,
+0xFF5491CA,
+0xFF5592CB,
+0xFF5693CC,
+0xFF5693CA,
+0xFF5693CA,
+0xFF5693CA,
+0xFF5794CB,
+0xFF5796CC,
+0xFF5796CC,
+0xFF5796CC,
+0xFF5695CB,
+0xFF5897CD,
+0xFF5897CD,
+0xFF5897CD,
+0xFF5998CE,
+0xFF5998CE,
+0xFF5A99CF,
+0xFF5A99CE,
+0xFF5A99CE,
+0xFF5B9ACF,
+0xFF5C9BD0,
+0xFF5C9BD0,
+0xFF5C9BD0,
+0xFF5C9BD0,
+0xFF5C9BD0,
+0xFF5C9BCE,
+0xFF5C9BCE,
+0xFF5B9DCF,
+0xFF5B9DCF,
+0xFF5C9ED0,
+0xFF5C9ED0,
+0xFF5E9DD0,
+0xFF5E9DD0,
+0xFF5E9ECE,
+0xFF5F9FCF,
+0xFF5F9FCF,
+0xFF5F9FCF,
+0xFF619FD0,
+0xFF619FD0,
+0xFF619FCE,
+0xFF62A0CF,
+0xFF62A0CF,
+0xFF62A0CF,
+0xFF62A0D1,
+0xFF63A1D4,
+0xFF63A1D2,
+0xFF63A1D2,
+0xFF63A1D2,
+0xFF63A1D2,
+0xFF64A2D3,
+0xFF64A2D3,
+0xFF64A2D1,
+0xFF64A2D1,
+0xFF64A2D1,
+0xFF64A2D1,
+0xFF64A2D1,
+0xFF64A2D1,
+0xFF64A3CF,
+0xFF64A3CF,
+0xFF64A4D0,
+0xFF64A4D2,
+0xFF64A4D4,
+0xFF64A4D4,
+0xFF64A4D0,
+0xFF66A3CF,
+0xFF68A3CF,
+0xFF69A1D0,
+0xFF69A0D6,
+0xFF66A2D8,
+0xFF65A3D6,
+0xFF62A5D2,
+0xFF62A5CF,
+0xFF62A5CF,
+0xFF65A3D2,
+0xFF65A3D2,
+0xFF65A4CF,
+0xFF66A5CE,
+0xFF65A5D1,
+0xFF62A5D2,
+0xFF63A5D5,
+0xFF66A8D8,
+0xFF67A7D5,
+0xFF64A3CF,
+0xFF65A2CF,
+0xFF6AA7D4,
+0xFF69A8D4,
+0xFF65A4D0,
+0xFF64A4D2,
+0xFF68A8D6,
+0xFF67A6D2,
+0xFF64A3CF,
+0xFF68A5D2,
+0xFF68A5D2,
+0xFF67A5D4,
+0xFF66A6D4,
+0xFF63A7D4,
+0xFF61A8D4,
+0xFF61A8D6,
+0xFF63A7D4,
+0xFF64A7D2,
+0xFF67A6D1,
+0xFF68A6CF,
+0xFF68A6CF,
+0xFF69A7D0,
+0xFF68A7D2,
+0xFF67A7D3,
+0xFF66A6D2,
+0xFF67A4D0,
+0xFF68A7D2,
+0xFF61A8D2,
+0xFF5EA7D0,
+0xFF63A3CF,
+0xFF65A4D0,
+0xFF68A6D5,
+0xFF67A7D5,
+0xFF61A1D1,
+0xFF6AA8D7,
+0xFF67A0CB,
+0xFF72A8CE,
+0xFF78ABCA,
+0xFF376481,
+0xFF000825,
+0xFF7198B9,
+0xFF6EA3CB,
+0xFF63A1CA,
+0xFF87C5EE,
+0xFF65A3CC,
+0xFF6BA9D2,
+0xFF6BA9D2,
+0xFF6AA7D3,
+0xFF67A4D0,
+0xFF68A7D3,
+0xFF69A8D4,
+0xFF69A8D4,
+0xFF68A7D3,
+0xFF68A6D5,
+0xFF68A6D5,
+0xFF68A6D5,
+0xFF69A7D6,
+0xFF68A8D4,
+0xFF68A8D4,
+0xFF68A8D4,
+0xFF68A8D4,
+0xFF68A8D4,
+0xFF68A8D4,
+0xFF68A8D4,
+0xFF68A8D4,
+0xFF68A8D4,
+0xFF68A8D4,
+0xFF68A8D4,
+0xFF68A8D4,
+0xFF68A8D4,
+0xFF68A8D4,
+0xFF68A8D4,
+0xFF69A9D5,
+0xFF68A8D4,
+0xFF68A8D4,
+0xFF68A8D4,
+0xFF68A8D4,
+0xFF68A8D4,
+0xFF68A8D4,
+0xFF68A8D4,
+0xFF68A8D4,
+0xFF67A7D3,
+0xFF68A8D4,
+0xFF69A8D4,
+0xFF69A8D4,
+0xFF69A8D4,
+0xFF69A8D4,
+0xFF69A8D4,
+0xFF6AA9D5,
+0xFF68A8D4,
+0xFF64A7D2,
+0xFF68ABD5,
+0xFF67AAD4,
+0xFF66A5D1,
+0xFF75A8D5,
+0xFF85A1C8,
+0xFF556F92,
+0xFF6995B8,
+0xFF76ADD4,
+0xFF69A3D1,
+0xFF64A2D3,
+0xFF6AAAD6,
+0xFF6BACD6,
+0xFF66A5D0,
+0xFF68A5D1,
+0xFF6CABD6,
+0xFF66A5D0,
+0xFF6AA9D4,
+0xFF6CA9D5,
+0xFF6EA8D6,
+0xFF6DAAD7,
+0xFF67A4D3,
+0xFF6DAAD9,
+0xFF6AA8D7,
+0xFF6AA9D5,
+0xFF69A9D5,
+0xFF69A9D5,
+0xFF69AAD4,
+0xFF67AAD5,
+0xFF66A9D4,
+0xFF66A9D4,
+0xFF68A7D3,
+0xFF69A8D4,
+0xFF6AA9D5,
+0xFF6BAAD6,
+0xFF6DABDA,
+0xFF70AEDD,
+0xFF66A4D3,
+0xFF6CA9D5,
+0xFF6CA4C9,
+0xFF77A5BF,
+0xFFD3F3FF,
+0xFFE6FFFF,
+0xFFB9D4E7,
+0xFF759AB5,
+0xFF70A7D0,
+0xFF6AA8D7,
+0xFF69A7D6,
+0xFF6AA9D5,
+0xFF6AA9D5,
+0xFF6AA9D5,
+0xFF69A8D4,
+0xFF69A8D4,
+0xFF69A8D4,
+0xFF6AA9D5,
+0xFF6AA9D5,
+0xFF69A8D4,
+0xFF69A8D4,
+0xFF69A8D4,
+0xFF69A8D4,
+0xFF6AA9D5,
+0xFF6AA9D5,
+0xFF6AA9D5,
+0xFF69A8D4,
+0xFF69A8D4,
+0xFF6AA9D5,
+0xFF6AA9D5,
+0xFF6AA9D5,
+0xFF69A8D4,
+0xFF69A8D4,
+0xFF69A8D4,
+0xFF69A8D4,
+0xFF69A8D4,
+0xFF69A8D4,
+0xFF69A8D4,
+0xFF69A8D4,
+0xFF69A8D4,
+0xFF69A8D4,
+0xFF6AA9D5,
+0xFF69A8D4,
+0xFF69A8D4,
+0xFF69A8D4,
+0xFF69A8D4,
+0xFF69A8D4,
+0xFF69A8D4,
+0xFF6AA9D5,
+0xFF6AA9D5,
+0xFF69A8D4,
+0xFF69A8D4,
+0xFF69A8D4,
+0xFF69A8D4,
+0xFF69A8D4,
+0xFF69A8D4,
+0xFF69A8D4,
+0xFF69A8D4,
+0xFF68A7D3,
+0xFF68A7D3,
+0xFF68A7D3,
+0xFF68A7D3,
+0xFF68A7D3,
+0xFF68A7D3,
+0xFF68A7D3,
+0xFF68A7D3,
+0xFF68A7D3,
+0xFF68A7D3,
+0xFF67A6D2,
+0xFF67A6D2,
+0xFF67A6D2,
+0xFF66A5D1,
+0xFF66A5D1,
+0xFF66A5D1,
+0xFF66A6D4,
+0xFF63A6D3,
+0xFF64A4D2,
+0xFF62A5D2,
+0xFF62A4D4,
+0xFF61A3D3,
+0xFF61A3D3,
+0xFF60A2D2,
+0xFF60A2D2,
+0xFF5FA1D1,
+0xFF5EA0D2,
+0xFF5DA1D2,
+0xFF5DA1D2,
+0xFF5DA1D2,
+0xFF5CA0D1,
+0xFF5CA0D1,
+0xFF5B9ED2,
+0xFF5B9ED2,
+0xFF5B9ED2,
+0xFF5A9DD1,
+0xFF5A9DD1,
+0xFF599CD0,
+0xFF599CD1,
+0xFF599CD1,
+0xFF599CD1,
+0xFF589BD0,
+0xFF5899CF,
+0xFF5899CF,
+0xFF5899CF,
+0xFF5798CE,
+0xFF5798CE,
+0xFF5697CD,
+0xFF528FC8,
+0xFF5390C9,
+0xFF5491CA,
+0xFF5592CB,
+0xFF5491CA,
+0xFF5592CB,
+0xFF5693CA,
+0xFF5794CB,
+0xFF5895CC,
+0xFF5895CC,
+0xFF5796CC,
+0xFF5796CC,
+0xFF5796CC,
+0xFF5897CD,
+0xFF5897CD,
+0xFF5897CD,
+0xFF5897CC,
+0xFF5897CC,
+0xFF5998CD,
+0xFF5A99CE,
+0xFF5A99CE,
+0xFF5B9ACF,
+0xFF5B9ACF,
+0xFF5B9ACF,
+0xFF5C9BD0,
+0xFF5D9CD1,
+0xFF5D9CCF,
+0xFF5D9CCF,
+0xFF5D9CCF,
+0xFF5D9CCF,
+0xFF5E9DD0,
+0xFF5E9DD0,
+0xFF5E9DD0,
+0xFF5F9ED1,
+0xFF5F9FCF,
+0xFF5F9FCF,
+0xFF5F9FCF,
+0xFF5F9FCF,
+0xFF5F9FCF,
+0xFF60A0D0,
+0xFF60A0D0,
+0xFF61A1D1,
+0xFF62A0D1,
+0xFF63A1D2,
+0xFF63A1D0,
+0xFF63A1D0,
+0xFF63A1D0,
+0xFF63A1D0,
+0xFF64A2D3,
+0xFF64A2D3,
+0xFF64A2D3,
+0xFF64A2D3,
+0xFF64A2D3,
+0xFF64A2D3,
+0xFF65A3D2,
+0xFF65A3D2,
+0xFF65A3D2,
+0xFF65A3D2,
+0xFF65A3D2,
+0xFF65A3D2,
+0xFF65A3D2,
+0xFF65A3D2,
+0xFF65A3D2,
+0xFF65A3D2,
+0xFF66A5D1,
+0xFF65A5D3,
+0xFF65A5D5,
+0xFF65A5D5,
+0xFF64A4D2,
+0xFF65A4CF,
+0xFF66A3CF,
+0xFF66A3CF,
+0xFF68A4D6,
+0xFF68A4D6,
+0xFF66A4D3,
+0xFF65A5D1,
+0xFF65A6D0,
+0xFF66A5D0,
+0xFF66A4D3,
+0xFF66A4D3,
+0xFF67A6CF,
+0xFF66A5CE,
+0xFF67A6D1,
+0xFF67A6D2,
+0xFF65A4D0,
+0xFF62A1CD,
+0xFF64A3CF,
+0xFF6AA7D3,
+0xFF6BA4D1,
+0xFF6BA4D1,
+0xFF68A3CF,
+0xFF65A2CE,
+0xFF68A7D2,
+0xFF67A6D1,
+0xFF66A5D0,
+0xFF6BA8D4,
+0xFF68A5D2,
+0xFF68A5D2,
+0xFF67A6D2,
+0xFF66A6D2,
+0xFF64A7D2,
+0xFF63A8D2,
+0xFF64A8D5,
+0xFF65A8D3,
+0xFF67A7D3,
+0xFF67A6D1,
+0xFF68A5D1,
+0xFF68A5D1,
+0xFF69A6D2,
+0xFF68A7D2,
+0xFF67A7D3,
+0xFF65A8D5,
+0xFF6AA9D5,
+0xFF67A8D2,
+0xFF62AAD2,
+0xFF64A9D2,
+0xFF68A8D4,
+0xFF6BA8D4,
+0xFF6BA9D0,
+0xFF67A7CD,
+0xFF67AAD4,
+0xFF69A8D1,
+0xFF81B1D7,
+0xFF4C6F8B,
+0xFFB6D0DF,
+0xFFEAFFFF,
+0xFF052A3D,
+0xFF82B1CD,
+0xFF6EA6CB,
+0xFF81BFE8,
+0xFF6AA8D1,
+0xFF69A7D0,
+0xFF6CA9D5,
+0xFF67A4D0,
+0xFF6BA8D4,
+0xFF6AA7D3,
+0xFF6AA7D4,
+0xFF6BA8D5,
+0xFF6AA9D5,
+0xFF69A8D4,
+0xFF69A8D4,
+0xFF69A8D4,
+0xFF69A7D6,
+0xFF6AA8D7,
+0xFF69A8D4,
+0xFF69A8D4,
+0xFF69A8D4,
+0xFF69A8D4,
+0xFF6AA9D5,
+0xFF6AA9D5,
+0xFF6AA9D5,
+0xFF6AA9D5,
+0xFF6AA9D5,
+0xFF6AA9D5,
+0xFF6AA9D5,
+0xFF6AA9D5,
+0xFF6AA9D5,
+0xFF6AA9D5,
+0xFF6AA9D5,
+0xFF6AA9D5,
+0xFF6AA9D5,
+0xFF6AA9D5,
+0xFF6AA9D5,
+0xFF6AA9D5,
+0xFF69A8D4,
+0xFF69A8D4,
+0xFF6AA9D5,
+0xFF6AA9D5,
+0xFF6AA9D5,
+0xFF6AA9D5,
+0xFF6AA9D5,
+0xFF6AA9D5,
+0xFF6AA9D5,
+0xFF6AA9D5,
+0xFF6AA9D5,
+0xFF6AA9D5,
+0xFF6AA7D4,
+0xFF69A8D4,
+0xFF6BAAD5,
+0xFF6AA9D4,
+0xFF6AA9D5,
+0xFF6EA9D5,
+0xFF76AAD2,
+0xFF709AC0,
+0xFF415F83,
+0xFF84A6CB,
+0xFF73A8D0,
+0xFF6EADD6,
+0xFF6EACD1,
+0xFF67A1C7,
+0xFF73A9D5,
+0xFF6EA7D4,
+0xFF68A6D5,
+0xFF69ACD9,
+0xFF6CABD7,
+0xFF6BAAD6,
+0xFF69A6D2,
+0xFF6DAAD6,
+0xFF67A4D1,
+0xFF6CABD7,
+0xFF6BAAD6,
+0xFF6BAAD5,
+0xFF6CAAD3,
+0xFF6EA9D1,
+0xFF6EA9D3,
+0xFF6CA9D5,
+0xFF6BA9D8,
+0xFF6BA9D8,
+0xFF6DACD7,
+0xFF6BA9D2,
+0xFF6CA6D4,
+0xFF6DA7D5,
+0xFF6AA5D1,
+0xFF6BA8D4,
+0xFF6EAEDC,
+0xFF6CA6CE,
+0xFF7AA3BF,
+0xFFCCEBFF,
+0xFFEBFFFF,
+0xFFBFDCEE,
+0xFF6E9CB6,
+0xFF75ABCF,
+0xFF6EA7D2,
+0xFF6DA7D5,
+0xFF6BA8D5,
+0xFF6BAAD6,
+0xFF6BAAD6,
+0xFF6BAAD6,
+0xFF6AA9D5,
+0xFF6AA9D5,
+0xFF6AA9D5,
+0xFF6BAAD6,
+0xFF6BAAD6,
+0xFF6BAAD6,
+0xFF6BAAD6,
+0xFF6BAAD6,
+0xFF6BAAD6,
+0xFF6BAAD6,
+0xFF6BAAD6,
+0xFF6BAAD6,
+0xFF6AA9D5,
+0xFF6AA9D5,
+0xFF6BAAD6,
+0xFF6BAAD6,
+0xFF6BAAD6,
+0xFF6AA9D5,
+0xFF6AA9D5,
+0xFF6AA9D5,
+0xFF6AA9D5,
+0xFF6AA9D5,
+0xFF6AA9D5,
+0xFF6AA9D5,
+0xFF6AA9D5,
+0xFF6AA9D5,
+0xFF6AA9D5,
+0xFF6BAAD6,
+0xFF6AA9D5,
+0xFF6AA9D5,
+0xFF6AA9D5,
+0xFF6AA9D5,
+0xFF6AA9D5,
+0xFF6AA9D5,
+0xFF6BAAD6,
+0xFF6BAAD6,
+0xFF6AA9D5,
+0xFF6AA9D5,
+0xFF6AA9D5,
+0xFF6AA9D5,
+0xFF6AA9D5,
+0xFF6AA9D5,
+0xFF6AA9D5,
+0xFF6AA9D5,
+0xFF69A8D4,
+0xFF69A8D4,
+0xFF6AA9D5,
+0xFF69A8D4,
+0xFF69A8D4,
+0xFF69A8D4,
+0xFF69A8D4,
+0xFF69A8D4,
+0xFF69A8D4,
+0xFF68A7D3,
+0xFF68A7D3,
+0xFF68A7D3,
+0xFF67A6D2,
+0xFF67A6D2,
+0xFF67A6D2,
+0xFF67A6D2,
+0xFF68A6D5,
+0xFF66A6D4,
+0xFF67A5D4,
+0xFF65A5D3,
+0xFF65A5D3,
+0xFF64A4D2,
+0xFF64A4D4,
+0xFF63A3D3,
+0xFF63A3D3,
+0xFF62A2D2,
+0xFF62A2D2,
+0xFF5FA1D1,
+0xFF60A2D4,
+0xFF5FA1D3,
+0xFF5EA0D2,
+0xFF5D9FD1,
+0xFF5D9FD3,
+0xFF5D9FD3,
+0xFF5C9ED2,
+0xFF5C9ED2,
+0xFF5C9ED2,
+0xFF5C9ED2,
+0xFF5B9DD1,
+0xFF5B9DD1,
+0xFF5B9DD1,
+0xFF5B9DD1,
+0xFF5A9BD1,
+0xFF599AD0,
+0xFF599AD0,
+0xFF5899CF,
+0xFF5899CF,
+0xFF5798CE,
+0xFF5390C9,
+0xFF5491CA,
+0xFF5592CB,
+0xFF5592CB,
+0xFF5592CB,
+0xFF5693CC,
+0xFF5693CA,
+0xFF5794CB,
+0xFF5996CD,
+0xFF5996CD,
+0xFF5796CC,
+0xFF5796CC,
+0xFF5897CD,
+0xFF5998CE,
+0xFF5998CE,
+0xFF5998CE,
+0xFF5998CD,
+0xFF5998CD,
+0xFF5A99CE,
+0xFF5B9ACF,
+0xFF5C9BD0,
+0xFF5C9BD0,
+0xFF5C9BD0,
+0xFF5C9BD0,
+0xFF5D9CD1,
+0xFF5D9CD1,
+0xFF5D9CCF,
+0xFF5E9DD0,
+0xFF5E9DD0,
+0xFF5E9DD0,
+0xFF5F9ED1,
+0xFF5F9ED1,
+0xFF5F9ED1,
+0xFF609FD2,
+0xFF60A0D0,
+0xFF60A0D0,
+0xFF60A0D0,
+0xFF60A0D0,
+0xFF61A1D1,
+0xFF61A1D1,
+0xFF61A1D1,
+0xFF61A1D1,
+0xFF63A1D2,
+0xFF64A2D3,
+0xFF64A2D1,
+0xFF64A2D1,
+0xFF64A2D1,
+0xFF63A1D0,
+0xFF65A3D4,
+0xFF66A4D5,
+0xFF66A4D5,
+0xFF65A3D4,
+0xFF65A3D4,
+0xFF65A3D4,
+0xFF65A3D2,
+0xFF65A3D2,
+0xFF65A3D2,
+0xFF65A3D2,
+0xFF66A4D3,
+0xFF66A4D3,
+0xFF66A4D3,
+0xFF66A4D3,
+0xFF66A4D3,
+0xFF66A4D3,
+0xFF67A6D2,
+0xFF66A4D3,
+0xFF66A4D5,
+0xFF65A5D5,
+0xFF65A5D3,
+0xFF65A5D1,
+0xFF65A6D0,
+0xFF66A5D0,
+0xFF67A6D2,
+0xFF67A5D4,
+0xFF67A6D2,
+0xFF67A6D1,
+0xFF67A6D1,
+0xFF67A6D1,
+0xFF68A5D4,
+0xFF66A4D3,
+0xFF66A7D1,
+0xFF68A9D3,
+0xFF68A7D3,
+0xFF65A4D0,
+0xFF67A5D4,
+0xFF69A9D7,
+0xFF69A9D5,
+0xFF66A5D1,
+0xFF69A4D0,
+0xFF6CA5D2,
+0xFF6AA5D1,
+0xFF6BA8D4,
+0xFF6AA9D4,
+0xFF6BAAD5,
+0xFF68A5D1,
+0xFF67A4D0,
+0xFF68A5D2,
+0xFF68A5D2,
+0xFF67A6D2,
+0xFF67A6D2,
+0xFF67A7D3,
+0xFF67A8D2,
+0xFF67A7D3,
+0xFF67A8D2,
+0xFF68A7D2,
+0xFF69A6D2,
+0xFF68A5D1,
+0xFF67A6D1,
+0xFF67A6D2,
+0xFF67A7D3,
+0xFF67A7D3,
+0xFF67A7D3,
+0xFF69A9D7,
+0xFF63A3CF,
+0xFF64A7D1,
+0xFF67AAD4,
+0xFF6AA9D4,
+0xFF6AA8D1,
+0xFF6BA7CB,
+0xFF6BA7CB,
+0xFF6AAACE,
+0xFF72A8CC,
+0xFF6485A4,
+0xFF000519,
+0xFF505559,
+0xFFBCC7C9,
+0xFF7596A5,
+0xFF76A5BF,
+0xFF83BBE0,
+0xFF68A6CF,
+0xFF6BA9D2,
+0xFF69A7D0,
+0xFF6CA9D5,
+0xFF68A5D1,
+0xFF6DAAD6,
+0xFF6BA8D4,
+0xFF6BA8D5,
+0xFF6BA8D5,
+0xFF6AA9D5,
+0xFF6AA9D5,
+0xFF6AA9D5,
+0xFF6AA9D5,
+0xFF6AA8D7,
+0xFF6BAAD6,
+0xFF6AA9D5,
+0xFF6AA9D5,
+0xFF6AA9D5,
+0xFF6AA9D5,
+0xFF6AA9D5,
+0xFF6AA9D5,
+0xFF6AA9D5,
+0xFF6AA9D5,
+0xFF6BAAD6,
+0xFF6BAAD6,
+0xFF6BAAD6,
+0xFF6BAAD6,
+0xFF6BAAD6,
+0xFF6BAAD6,
+0xFF6BAAD6,
+0xFF6BAAD6,
+0xFF6BAAD6,
+0xFF6BAAD6,
+0xFF6BAAD6,
+0xFF6BAAD6,
+0xFF6BAAD6,
+0xFF6AA9D5,
+0xFF6AA9D5,
+0xFF6BAAD6,
+0xFF6BAAD6,
+0xFF6BAAD6,
+0xFF6BAAD6,
+0xFF6BAAD6,
+0xFF6BAAD6,
+0xFF6BAAD6,
+0xFF6BAAD6,
+0xFF6DAAD6,
+0xFF6FAAD6,
+0xFF6DA8D4,
+0xFF6BA9D2,
+0xFF6BAAD5,
+0xFF6CACD8,
+0xFF68A7D3,
+0xFF6CA9D5,
+0xFF82B2DA,
+0xFF41577C,
+0xFF889FC1,
+0xFF75A5CB,
+0xFF6DA9CE,
+0xFF6DA9CD,
+0xFF97CDF3,
+0xFF7EACD0,
+0xFF73A0C7,
+0xFF72A8D4,
+0xFF70ADD9,
+0xFF6AA7D3,
+0xFF6CA9D5,
+0xFF6DACD7,
+0xFF6EADD8,
+0xFF6CABD7,
+0xFF68A7D2,
+0xFF6BAAD5,
+0xFF6CAAD3,
+0xFF6FAAD2,
+0xFF70AAD2,
+0xFF70A9D4,
+0xFF6FAAD6,
+0xFF6FA9D7,
+0xFF6FA9D7,
+0xFF6DA8D0,
+0xFF6CA7CF,
+0xFF72ABD8,
+0xFF72ABD8,
+0xFF6EA9D5,
+0xFF6DABD4,
+0xFF6BA6CE,
+0xFF75A6C6,
+0xFFC8E4F9,
+0xFFE5FBFF,
+0xFFC9E6F8,
+0xFF7CA4BD,
+0xFF72AACD,
+0xFF6BA9D2,
+0xFF71AAD7,
+0xFF72ABD8,
+0xFF6CA9D6,
+0xFF6CABD7,
+0xFF6CABD7,
+0xFF6CABD7,
+0xFF6BAAD6,
+0xFF6BAAD6,
+0xFF6BAAD6,
+0xFF6CABD7,
+0xFF6BAAD6,
+0xFF6CABD7,
+0xFF6CABD7,
+0xFF6CABD7,
+0xFF6CABD7,
+0xFF6CABD7,
+0xFF6CABD7,
+0xFF6CABD7,
+0xFF6BAAD6,
+0xFF6BAAD6,
+0xFF6BAAD6,
+0xFF6BAAD6,
+0xFF6BAAD6,
+0xFF6BAAD6,
+0xFF6BAAD6,
+0xFF6BAAD6,
+0xFF6BAAD6,
+0xFF6BAAD6,
+0xFF6BAAD6,
+0xFF6BAAD6,
+0xFF6BAAD6,
+0xFF6BAAD6,
+0xFF6BAAD6,
+0xFF6BAAD6,
+0xFF6BAAD6,
+0xFF6BAAD6,
+0xFF6BAAD6,
+0xFF6BAAD6,
+0xFF6BAAD6,
+0xFF6BAAD6,
+0xFF6BAAD6,
+0xFF6BAAD6,
+0xFF6BAAD6,
+0xFF6BAAD6,
+0xFF6BAAD6,
+0xFF6BAAD6,
+0xFF6BAAD6,
+0xFF6BAAD6,
+0xFF6AA9D5,
+0xFF6AA9D5,
+0xFF6AA9D5,
+0xFF6AA9D5,
+0xFF6AA9D5,
+0xFF6AA9D5,
+0xFF6AA9D5,
+0xFF6AA9D5,
+0xFF69A8D4,
+0xFF69A8D4,
+0xFF69A8D4,
+0xFF69A8D4,
+0xFF69A8D4,
+0xFF68A7D3,
+0xFF68A7D3,
+0xFF68A7D3,
+0xFF68A7D3,
+0xFF68A7D3,
+0xFF69A7D6,
+0xFF68A6D5,
+0xFF68A6D5,
+0xFF67A5D4,
+0xFF67A5D4,
+0xFF65A5D3,
+0xFF65A5D5,
+0xFF65A5D5,
+0xFF64A4D4,
+0xFF64A4D4,
+0xFF63A3D3,
+0xFF63A3D3,
+0xFF63A2D5,
+0xFF60A2D4,
+0xFF61A0D3,
+0xFF5EA0D2,
+0xFF5EA0D2,
+0xFF5EA0D4,
+0xFF5D9FD3,
+0xFF5D9FD3,
+0xFF5D9FD3,
+0xFF5D9FD3,
+0xFF5C9ED2,
+0xFF5C9ED2,
+0xFF5C9ED2,
+0xFF5B9DD1,
+0xFF5A9BD1,
+0xFF5A9BD1,
+0xFF5A9BD1,
+0xFF599AD0,
+0xFF599AD0,
+0xFF5899CF,
+0xFF5491C8,
+0xFF5491C8,
+0xFF5592C9,
+0xFF5693CA,
+0xFF5693CA,
+0xFF5693CA,
+0xFF5695CB,
+0xFF5796CC,
+0xFF5897CD,
+0xFF5897CD,
+0xFF5897CC,
+0xFF5897CC,
+0xFF5998CD,
+0xFF5998CD,
+0xFF5A99CE,
+0xFF5B9ACF,
+0xFF5A99CE,
+0xFF5A99CE,
+0xFF5B9ACF,
+0xFF5C9BD0,
+0xFF5D9CD1,
+0xFF5D9CD1,
+0xFF5D9CCF,
+0xFF5D9CCF,
+0xFF5E9DD0,
+0xFF5E9DD0,
+0xFF5E9DD0,
+0xFF5E9DD0,
+0xFF5F9ED1,
+0xFF5F9ED1,
+0xFF5F9FCF,
+0xFF60A0D0,
+0xFF619FD0,
+0xFF619FD0,
+0xFF62A0D1,
+0xFF62A0D1,
+0xFF62A0D1,
+0xFF63A1D2,
+0xFF63A1D2,
+0xFF64A2D3,
+0xFF63A1D0,
+0xFF63A1D0,
+0xFF64A2D1,
+0xFF65A3D2,
+0xFF65A3D2,
+0xFF65A3D2,
+0xFF64A2D1,
+0xFF64A2D1,
+0xFF66A4D3,
+0xFF66A4D3,
+0xFF66A4D3,
+0xFF66A4D3,
+0xFF66A4D3,
+0xFF65A3D2,
+0xFF65A3D2,
+0xFF66A4D3,
+0xFF66A4D3,
+0xFF66A4D3,
+0xFF66A4D3,
+0xFF66A4D3,
+0xFF66A4D3,
+0xFF66A4D3,
+0xFF67A5D4,
+0xFF67A5D4,
+0xFF67A4D1,
+0xFF66A4D3,
+0xFF66A4D7,
+0xFF65A4D7,
+0xFF66A6D6,
+0xFF64A7D2,
+0xFF64A7D1,
+0xFF64A8CF,
+0xFF66A7D1,
+0xFF67A6D1,
+0xFF67A6D1,
+0xFF68A5D1,
+0xFF68A5D1,
+0xFF68A5D2,
+0xFF67A5D6,
+0xFF68A6D7,
+0xFF64A4D2,
+0xFF65A5D3,
+0xFF68A6D7,
+0xFF69A7D8,
+0xFF65A7D7,
+0xFF61A8D6,
+0xFF61A8D6,
+0xFF62A9D7,
+0xFF6AAADA,
+0xFF67A5D6,
+0xFF64A4D2,
+0xFF6BABD9,
+0xFF60A3CE,
+0xFF66A6D2,
+0xFF68A5D2,
+0xFF6BA5D3,
+0xFF6AA7D4,
+0xFF69A8D4,
+0xFF69A8D3,
+0xFF69A8D3,
+0xFF69A8D3,
+0xFF69A8D1,
+0xFF6AA7D3,
+0xFF6AA7D3,
+0xFF6AA7D3,
+0xFF6AA7D3,
+0xFF6AA7D4,
+0xFF69A8D4,
+0xFF69A7D6,
+0xFF68A8D4,
+0xFF68A8D4,
+0xFF69A9D5,
+0xFF6BA8D7,
+0xFF68A5D4,
+0xFF6AA8D7,
+0xFF68A8D4,
+0xFF68A5D1,
+0xFF6AA8CF,
+0xFF6CA8CC,
+0xFF74ACCF,
+0xFF7AAAD0,
+0xFF8AADCD,
+0xFF111D33,
+0xFF7D7B86,
+0xFF1A1511,
+0xFF4F5352,
+0xFF839DAC,
+0xFF94C0DD,
+0xFF75ACD3,
+0xFF6CA9D5,
+0xFF6CA9D5,
+0xFF6CA9D5,
+0xFF6CA9D5,
+0xFF6DAAD6,
+0xFF69A6D2,
+0xFF6DAAD6,
+0xFF6CA9D5,
+0xFF6CA9D5,
+0xFF6CA9D5,
+0xFF6CA9D5,
+0xFF6BA8D5,
+0xFF6BA8D5,
+0xFF6CA9D6,
+0xFF6CA9D6,
+0xFF6CA9D6,
+0xFF6CA9D5,
+0xFF6CA9D5,
+0xFF6CA9D5,
+0xFF6CA9D5,
+0xFF6CA9D5,
+0xFF6CA9D5,
+0xFF6CA9D5,
+0xFF6CA9D5,
+0xFF6CA9D5,
+0xFF6CA9D5,
+0xFF6CA9D5,
+0xFF6CA9D5,
+0xFF6CA9D5,
+0xFF6CA9D5,
+0xFF6CA9D5,
+0xFF6CABD6,
+0xFF6CABD6,
+0xFF6CABD6,
+0xFF6BAAD5,
+0xFF6BAAD5,
+0xFF6BAAD5,
+0xFF6CA9D5,
+0xFF6CA9D5,
+0xFF6DAAD6,
+0xFF6DAAD6,
+0xFF6DAAD6,
+0xFF6DAAD6,
+0xFF6DAAD6,
+0xFF6DAAD6,
+0xFF6DAAD6,
+0xFF6DABD4,
+0xFF71ABD3,
+0xFF6CA7CF,
+0xFF6CADD5,
+0xFF6AADD7,
+0xFF69A9D5,
+0xFF6FACD9,
+0xFF70AAD8,
+0xFF78A3CE,
+0xFF899CC4,
+0xFF415377,
+0xFF89B0D9,
+0xFF73A8D0,
+0xFF6CAAD1,
+0xFFC1F7FF,
+0xFFD7FBFF,
+0xFFA3C3DC,
+0xFF79A2C2,
+0xFF72A4C9,
+0xFF75ACD3,
+0xFF6EACD5,
+0xFF6BABD7,
+0xFF69ACD7,
+0xFF6DAED8,
+0xFF6EADD6,
+0xFF6CACD2,
+0xFF6DABD2,
+0xFF6DABD4,
+0xFF6FAAD4,
+0xFF6FAAD6,
+0xFF70A9D6,
+0xFF74A8D7,
+0xFF74A9D5,
+0xFF74AED4,
+0xFF72ACD2,
+0xFF70A9D4,
+0xFF6DA6D3,
+0xFF6BA9D8,
+0xFF71AAD5,
+0xFF74A1BE,
+0xFFB5D4E8,
+0xFFECFCFF,
+0xFFE6F9FF,
+0xFF7CA5C3,
+0xFF70A8CD,
+0xFF6FADD4,
+0xFF6DACD5,
+0xFF73AEDA,
+0xFF6BA6D2,
+0xFF6EABD7,
+0xFF6EABD7,
+0xFF6EABD7,
+0xFF6EABD7,
+0xFF6EABD7,
+0xFF6DAAD6,
+0xFF6EABD7,
+0xFF6EABD7,
+0xFF6DAAD6,
+0xFF6DAAD6,
+0xFF6EABD7,
+0xFF6EABD7,
+0xFF6EABD7,
+0xFF6DAAD6,
+0xFF6DAAD6,
+0xFF6DAAD6,
+0xFF6DAAD6,
+0xFF6DAAD6,
+0xFF6DAAD6,
+0xFF6DAAD6,
+0xFF6DAAD6,
+0xFF6DAAD6,
+0xFF6DAAD6,
+0xFF6DAAD6,
+0xFF6DAAD6,
+0xFF6DAAD6,
+0xFF6DAAD6,
+0xFF6DAAD6,
+0xFF6DAAD6,
+0xFF6DAAD6,
+0xFF6DAAD6,
+0xFF6DAAD6,
+0xFF6DAAD6,
+0xFF6DAAD6,
+0xFF6DAAD6,
+0xFF6DAAD6,
+0xFF6DAAD6,
+0xFF6DAAD6,
+0xFF6DAAD6,
+0xFF6DAAD6,
+0xFF6CA9D5,
+0xFF6CA9D5,
+0xFF6CA9D5,
+0xFF6DAAD6,
+0xFF6CA9D5,
+0xFF6CA9D5,
+0xFF6CA9D5,
+0xFF6CA9D5,
+0xFF6CA9D6,
+0xFF6CA9D6,
+0xFF6CA9D6,
+0xFF6CA9D6,
+0xFF6CA9D6,
+0xFF6BA8D5,
+0xFF6BA8D5,
+0xFF6BA8D5,
+0xFF6AA9D5,
+0xFF6AA9D5,
+0xFF6AA9D5,
+0xFF69A8D4,
+0xFF69A8D4,
+0xFF69A8D4,
+0xFF69A8D4,
+0xFF69A8D4,
+0xFF69A6D3,
+0xFF69A6D3,
+0xFF69A6D3,
+0xFF69A6D3,
+0xFF68A5D4,
+0xFF67A5D4,
+0xFF67A5D4,
+0xFF67A5D4,
+0xFF66A4D3,
+0xFF66A4D3,
+0xFF65A3D4,
+0xFF65A3D4,
+0xFF65A3D4,
+0xFF63A3D3,
+0xFF63A1D2,
+0xFF61A1D1,
+0xFF61A1D1,
+0xFF609FD2,
+0xFF5EA0D2,
+0xFF5EA0D2,
+0xFF5EA0D2,
+0xFF5D9FD1,
+0xFF5D9FD1,
+0xFF5C9ED0,
+0xFF5C9ED2,
+0xFF5B9DD1,
+0xFF5B9DD1,
+0xFF5A9CD0,
+0xFF599CD1,
+0xFF599CD1,
+0xFF599CD1,
+0xFF599CD1,
+0xFF5592C9,
+0xFF5592C9,
+0xFF5693CA,
+0xFF5693CA,
+0xFF5794CB,
+0xFF5794CB,
+0xFF5796CC,
+0xFF5796CC,
+0xFF5897CD,
+0xFF5897CD,
+0xFF5998CD,
+0xFF5998CD,
+0xFF5A99CE,
+0xFF5B9ACF,
+0xFF5B9ACF,
+0xFF5C9BD0,
+0xFF5C9BD0,
+0xFF5C9BD0,
+0xFF5D9CD1,
+0xFF5D9CD1,
+0xFF5E9DD2,
+0xFF5E9DD2,
+0xFF5E9DD0,
+0xFF5E9DD0,
+0xFF5E9DD0,
+0xFF5E9DD0,
+0xFF5F9ED1,
+0xFF5F9ED1,
+0xFF609FD2,
+0xFF609FD2,
+0xFF60A0D0,
+0xFF61A1D1,
+0xFF62A0D1,
+0xFF62A0D1,
+0xFF63A1D2,
+0xFF63A1D2,
+0xFF63A1D2,
+0xFF64A2D3,
+0xFF64A2D3,
+0xFF65A3D4,
+0xFF64A2D1,
+0xFF65A3D2,
+0xFF65A3D2,
+0xFF65A3D2,
+0xFF66A4D3,
+0xFF66A4D3,
+0xFF66A4D3,
+0xFF65A3D2,
+0xFF66A4D3,
+0xFF67A5D4,
+0xFF67A5D4,
+0xFF67A5D4,
+0xFF67A5D4,
+0xFF66A4D3,
+0xFF66A4D3,
+0xFF66A4D3,
+0xFF67A5D4,
+0xFF67A5D4,
+0xFF67A5D4,
+0xFF67A5D4,
+0xFF67A5D4,
+0xFF67A5D4,
+0xFF67A5D4,
+0xFF67A6D2,
+0xFF68A5D2,
+0xFF68A5D4,
+0xFF67A5D8,
+0xFF67A5D8,
+0xFF66A6D6,
+0xFF65A8D3,
+0xFF64A9D2,
+0xFF64A9D0,
+0xFF66A7CF,
+0xFF67A8D0,
+0xFF69A7D0,
+0xFF69A6D2,
+0xFF69A6D2,
+0xFF68A7D3,
+0xFF68A6D7,
+0xFF67A7D7,
+0xFF66A8D8,
+0xFF67A7D7,
+0xFF69A5D7,
+0xFF69A5D7,
+0xFF68A6D5,
+0xFF68A7D2,
+0xFF6BA9D2,
+0xFF6FAAD2,
+0xFF72A7D1,
+0xFF71A6D2,
+0xFF6DA6D3,
+0xFF6CA9D6,
+0xFF63A6D1,
+0xFF6AAAD6,
+0xFF6EA8D6,
+0xFF6CA6D4,
+0xFF6AA7D4,
+0xFF69A8D4,
+0xFF69A8D4,
+0xFF69A8D3,
+0xFF6AA7D3,
+0xFF6AA8D1,
+0xFF6DA8D2,
+0xFF6DA8D2,
+0xFF6DA8D4,
+0xFF6BA8D5,
+0xFF6AA8D7,
+0xFF6AA8D7,
+0xFF68A8D6,
+0xFF69A9D5,
+0xFF69AAD4,
+0xFF6AA9D4,
+0xFF6CA9D8,
+0xFF6DA9DB,
+0xFF6DABDC,
+0xFF68A6D5,
+0xFF6BA8D4,
+0xFF71ACD4,
+0xFF6FA7CA,
+0xFF74A7C6,
+0xFF6F93B3,
+0xFF31455D,
+0xFF211B27,
+0xFFCABABB,
+0xFF402F28,
+0xFF4E4D4B,
+0xFF173142,
+0xFF78A3C3,
+0xFF71A8CF,
+0xFF6BA8D4,
+0xFF6FACD8,
+0xFF6CA9D5,
+0xFF6AA7D3,
+0xFF6CA9D5,
+0xFF70ADD9,
+0xFF6BA8D4,
+0xFF6CA9D5,
+0xFF6DAAD6,
+0xFF6DAAD6,
+0xFF6DAAD6,
+0xFF6CA9D6,
+0xFF6CA9D6,
+0xFF6DAAD7,
+0xFF6DAAD6,
+0xFF6DAAD6,
+0xFF6DAAD6,
+0xFF6DAAD6,
+0xFF6DAAD6,
+0xFF6DAAD6,
+0xFF6DAAD6,
+0xFF6DAAD6,
+0xFF6DAAD6,
+0xFF6DAAD6,
+0xFF6DAAD6,
+0xFF6DAAD6,
+0xFF6DAAD6,
+0xFF6DAAD6,
+0xFF6DAAD6,
+0xFF6DAAD6,
+0xFF6DAAD6,
+0xFF6CABD6,
+0xFF6CABD6,
+0xFF6CABD6,
+0xFF6CABD6,
+0xFF6CABD6,
+0xFF6CABD6,
+0xFF6DAAD6,
+0xFF6DAAD6,
+0xFF6EABD7,
+0xFF6EABD7,
+0xFF6DAAD6,
+0xFF6DAAD6,
+0xFF6EABD7,
+0xFF6EABD7,
+0xFF6DAAD6,
+0xFF6FAAD4,
+0xFF6FA9D1,
+0xFF72ADD5,
+0xFF6DAED8,
+0xFF68ABD5,
+0xFF6AA9D4,
+0xFF72ADD9,
+0xFF70A8D7,
+0xFF77A3D0,
+0xFF93ADD2,
+0xFF596C8D,
+0xFF768EB2,
+0xFF86ACD1,
+0xFF6EA8D0,
+0xFF70A8CD,
+0xFFC2E4FD,
+0xFFE8FFFF,
+0xFFCBE9FF,
+0xFF86ABC6,
+0xFF77A5C7,
+0xFF71A9CE,
+0xFF69A7D0,
+0xFF6CADD7,
+0xFF6FB0D8,
+0xFF6CACD2,
+0xFF6EACD3,
+0xFF6EACD3,
+0xFF6EABD7,
+0xFF6EABD7,
+0xFF70AAD8,
+0xFF71AAD7,
+0xFF74A8D7,
+0xFF74A9D3,
+0xFF72AACF,
+0xFF71ABD0,
+0xFF72ACD4,
+0xFF72ADD9,
+0xFF75B0DC,
+0xFF6FA1C6,
+0xFFA9C8DD,
+0xFFEBFEFF,
+0xFFE5F7FF,
+0xFF92AEC3,
+0xFF78AACD,
+0xFF70AFDA,
+0xFF6CADD7,
+0xFF6AA9D4,
+0xFF73B1DA,
+0xFF6DA8D2,
+0xFF71ACD8,
+0xFF6FACD8,
+0xFF6FACD8,
+0xFF6FACD8,
+0xFF6FACD8,
+0xFF6FACD8,
+0xFF6FACD8,
+0xFF6FACD8,
+0xFF6EABD7,
+0xFF6EABD7,
+0xFF6FACD8,
+0xFF6FACD8,
+0xFF6FACD8,
+0xFF6EABD7,
+0xFF6EABD7,
+0xFF6EABD7,
+0xFF6EABD7,
+0xFF6EABD7,
+0xFF6EABD7,
+0xFF6EABD7,
+0xFF6EABD7,
+0xFF6EABD7,
+0xFF6EABD7,
+0xFF6EABD7,
+0xFF6EABD7,
+0xFF6EABD7,
+0xFF6EABD7,
+0xFF6EABD7,
+0xFF6EABD7,
+0xFF6EABD7,
+0xFF6EABD7,
+0xFF6EABD7,
+0xFF6EABD7,
+0xFF6EABD7,
+0xFF6EABD7,
+0xFF6EABD7,
+0xFF6EABD7,
+0xFF6EABD7,
+0xFF6DAAD6,
+0xFF6DAAD6,
+0xFF6DAAD6,
+0xFF6DAAD6,
+0xFF6DAAD6,
+0xFF6DAAD6,
+0xFF6DAAD6,
+0xFF6DAAD6,
+0xFF6DAAD6,
+0xFF6DAAD6,
+0xFF6DAAD7,
+0xFF6DAAD7,
+0xFF6DAAD7,
+0xFF6DAAD7,
+0xFF6CA9D6,
+0xFF6CA9D6,
+0xFF6CA9D6,
+0xFF6BA8D5,
+0xFF6BAAD6,
+0xFF6BAAD6,
+0xFF6BAAD6,
+0xFF6AA9D5,
+0xFF6AA9D5,
+0xFF6AA9D5,
+0xFF6AA9D5,
+0xFF6AA9D5,
+0xFF6AA7D4,
+0xFF6AA7D4,
+0xFF6AA7D4,
+0xFF69A6D3,
+0xFF69A6D5,
+0xFF69A6D5,
+0xFF68A6D5,
+0xFF68A6D5,
+0xFF66A4D3,
+0xFF67A5D4,
+0xFF67A5D6,
+0xFF66A4D5,
+0xFF66A4D5,
+0xFF65A3D4,
+0xFF64A2D3,
+0xFF64A2D3,
+0xFF62A2D2,
+0xFF62A2D2,
+0xFF5FA1D1,
+0xFF5EA0D2,
+0xFF5FA1D3,
+0xFF5EA0D2,
+0xFF5D9FD1,
+0xFF5C9ED0,
+0xFF5C9ED2,
+0xFF5C9ED2,
+0xFF5B9DD1,
+0xFF5B9DD1,
+0xFF5A9DD2,
+0xFF5A9DD2,
+0xFF5A9DD2,
+0xFF5A9DD2,
+0xFF5594CA,
+0xFF5594CA,
+0xFF5695CB,
+0xFF5695CB,
+0xFF5796CB,
+0xFF5796CB,
+0xFF5897CC,
+0xFF5897CC,
+0xFF5998CD,
+0xFF5A99CE,
+0xFF5B9ACF,
+0xFF5B9ACF,
+0xFF5B9ACD,
+0xFF5B9ACD,
+0xFF5C9BCE,
+0xFF5D9CCF,
+0xFF5E9CCF,
+0xFF5E9CCF,
+0xFF5F9DD0,
+0xFF5F9DD0,
+0xFF5F9DD0,
+0xFF5F9DD0,
+0xFF609ED1,
+0xFF609ED1,
+0xFF609ECF,
+0xFF609ECF,
+0xFF619FD0,
+0xFF619FD0,
+0xFF62A0D1,
+0xFF62A0D1,
+0xFF63A1D2,
+0xFF63A1D2,
+0xFF63A1D0,
+0xFF64A2D1,
+0xFF64A2D1,
+0xFF65A3D2,
+0xFF65A3D2,
+0xFF65A3D2,
+0xFF65A3D2,
+0xFF66A4D3,
+0xFF66A4D3,
+0xFF66A4D3,
+0xFF66A4D3,
+0xFF66A4D3,
+0xFF66A4D3,
+0xFF67A5D4,
+0xFF67A5D4,
+0xFF67A5D4,
+0xFF67A6D2,
+0xFF67A6D2,
+0xFF68A7D3,
+0xFF68A7D3,
+0xFF67A6D2,
+0xFF67A6D2,
+0xFF67A6D2,
+0xFF67A6D2,
+0xFF68A7D3,
+0xFF68A7D3,
+0xFF68A7D3,
+0xFF68A7D3,
+0xFF68A7D3,
+0xFF68A7D3,
+0xFF68A7D3,
+0xFF68A7D3,
+0xFF69A6D3,
+0xFF69A6D3,
+0xFF69A5D7,
+0xFF68A6D9,
+0xFF67A7D7,
+0xFF65A8D5,
+0xFF65AAD3,
+0xFF65AAD1,
+0xFF68A9D1,
+0xFF68A9D1,
+0xFF6AA8D1,
+0xFF6AA7D3,
+0xFF69A8D4,
+0xFF69A7D6,
+0xFF66A8D8,
+0xFF66A8D8,
+0xFF62A6D5,
+0xFF6BABD9,
+0xFF6FA9D9,
+0xFF6FA5D3,
+0xFF78A9D2,
+0xFF85B1D4,
+0xFF84A9C4,
+0xFF7898B1,
+0xFF6C86A1,
+0xFF809DBB,
+0xFF87AFD3,
+0xFF76AAD2,
+0xFF6FADD6,
+0xFF67A8D2,
+0xFF6BA6D2,
+0xFF6DA8D4,
+0xFF69A8D4,
+0xFF68A8D6,
+0xFF68A8D6,
+0xFF6AA9D5,
+0xFF6BA8D4,
+0xFF6BA9D2,
+0xFF6DA8D2,
+0xFF6EA7D2,
+0xFF6DA8D4,
+0xFF6BA8D5,
+0xFF6BA9D8,
+0xFF6AAADA,
+0xFF69A9D7,
+0xFF69A9D5,
+0xFF6AA9D2,
+0xFF6BAAD3,
+0xFF69A9D5,
+0xFF69A9D7,
+0xFF6BABD9,
+0xFF68A7D3,
+0xFF70ABD7,
+0xFF73AAD1,
+0xFF6EA3C3,
+0xFF80ACC5,
+0xFF5A7789,
+0xFF00010C,
+0xFF412F2F,
+0xFF967973,
+0xFF311811,
+0xFF484244,
+0xFF031F34,
+0xFF7AABCB,
+0xFF6FA9D1,
+0xFF73B0DC,
+0xFF68A5D1,
+0xFF6AA7D3,
+0xFF6FACD8,
+0xFF6EABD7,
+0xFF6CA9D5,
+0xFF6FACD8,
+0xFF6DAAD6,
+0xFF6EABD7,
+0xFF6EABD7,
+0xFF6EABD7,
+0xFF6DAAD6,
+0xFF6DAAD6,
+0xFF6EABD7,
+0xFF6EABD7,
+0xFF6EABD7,
+0xFF6EACD5,
+0xFF6EACD5,
+0xFF6EACD5,
+0xFF6EACD5,
+0xFF6EACD5,
+0xFF6EACD5,
+0xFF6EACD5,
+0xFF6DABD4,
+0xFF6EACD5,
+0xFF6EACD5,
+0xFF6EACD5,
+0xFF6EACD5,
+0xFF6EACD5,
+0xFF6EACD5,
+0xFF6EACD5,
+0xFF6EACD5,
+0xFF6EACD5,
+0xFF6EACD5,
+0xFF6EACD5,
+0xFF6EACD5,
+0xFF6EACD5,
+0xFF6FADD6,
+0xFF6FADD6,
+0xFF71ACD6,
+0xFF71ACD6,
+0xFF70ABD5,
+0xFF70ABD5,
+0xFF71ACD6,
+0xFF71ACD6,
+0xFF70ABD5,
+0xFF70ABD7,
+0xFF6EA8D6,
+0xFF73B0DD,
+0xFF6BABD7,
+0xFF6CADD7,
+0xFF6FADD6,
+0xFF71AAD5,
+0xFF70A6D4,
+0xFF7EAFD8,
+0xFF81AACA,
+0xFF748EA9,
+0xFF4C506B,
+0xFFA0ABC9,
+0xFF78A8D0,
+0xFF71ABD3,
+0xFF79A1C4,
+0xFFB9D7F1,
+0xFFE4F9FF,
+0xFFE4FBFF,
+0xFFB2D4ED,
+0xFF7DAAC7,
+0xFF74AACE,
+0xFF73AFD4,
+0xFF6CAAD1,
+0xFF72B0D7,
+0xFF70AED5,
+0xFF70AED7,
+0xFF6EADD8,
+0xFF6EADD9,
+0xFF6FACD9,
+0xFF71ACD8,
+0xFF74AAD8,
+0xFF74ABD4,
+0xFF73ADD3,
+0xFF72AED3,
+0xFF6EADD6,
+0xFF70ABD3,
+0xFF76AAD1,
+0xFF91B6D3,
+0xFFE8F8FF,
+0xFFECFAFF,
+0xFFA6C6DD,
+0xFF73A2C0,
+0xFF76AED3,
+0xFF6FACD8,
+0xFF6BABD9,
+0xFF72B2DE,
+0xFF6EA9D1,
+0xFF75B0D8,
+0xFF72ADD7,
+0xFF72ADD7,
+0xFF72ADD7,
+0xFF72ADD7,
+0xFF72ADD7,
+0xFF71ACD6,
+0xFF72ADD7,
+0xFF72ADD7,
+0xFF71ACD6,
+0xFF71ACD6,
+0xFF72ADD7,
+0xFF72ADD7,
+0xFF72ADD7,
+0xFF72ADD7,
+0xFF71ACD6,
+0xFF71ACD6,
+0xFF71ACD6,
+0xFF71ACD6,
+0xFF71ACD6,
+0xFF71ACD6,
+0xFF71ACD6,
+0xFF71ACD6,
+0xFF72ADD7,
+0xFF72ADD7,
+0xFF71ACD6,
+0xFF71ACD6,
+0xFF71ACD6,
+0xFF71ACD6,
+0xFF71ACD6,
+0xFF71ACD6,
+0xFF71ACD6,
+0xFF71ACD6,
+0xFF71ACD8,
+0xFF71ACD8,
+0xFF71ACD8,
+0xFF71ACD8,
+0xFF71ACD8,
+0xFF71ACD8,
+0xFF70ABD7,
+0xFF70ABD7,
+0xFF70ABD7,
+0xFF70ABD7,
+0xFF70ABD7,
+0xFF70ABD7,
+0xFF70ABD7,
+0xFF70ABD7,
+0xFF70ABD7,
+0xFF70ABD7,
+0xFF70ABD7,
+0xFF70ABD7,
+0xFF70ABD7,
+0xFF70ABD7,
+0xFF6FAAD6,
+0xFF6FAAD6,
+0xFF6DAAD7,
+0xFF6CA9D6,
+0xFF6DAAD7,
+0xFF6DAAD7,
+0xFF6BAAD6,
+0xFF6BAAD6,
+0xFF6BAAD6,
+0xFF6BAAD6,
+0xFF6BAAD6,
+0xFF6BAAD6,
+0xFF6BA8D4,
+0xFF6BA8D4,
+0xFF6BA8D5,
+0xFF6AA7D4,
+0xFF69A6D3,
+0xFF69A6D3,
+0xFF68A7D3,
+0xFF69A8D4,
+0xFF67A5D4,
+0xFF67A5D4,
+0xFF68A6D5,
+0xFF68A6D5,
+0xFF67A5D4,
+0xFF67A5D4,
+0xFF66A4D3,
+0xFF65A3D2,
+0xFF64A4D2,
+0xFF63A3D1,
+0xFF62A2D0,
+0xFF62A2D2,
+0xFF62A2D2,
+0xFF61A1D1,
+0xFF60A0D0,
+0xFF5F9FCF,
+0xFF5EA0D2,
+0xFF5D9FD1,
+0xFF5D9FD3,
+0xFF5C9ED2,
+0xFF5C9ED2,
+0xFF5C9ED2,
+0xFF5B9ED2,
+0xFF5A9DD1,
+0xFF5695CB,
+0xFF5695CB,
+0xFF5695CB,
+0xFF5796CC,
+0xFF5897CC,
+0xFF5897CC,
+0xFF5998CD,
+0xFF5998CD,
+0xFF5A99CE,
+0xFF5B9ACF,
+0xFF5C9BD0,
+0xFF5C9BD0,
+0xFF5C9BCE,
+0xFF5C9BCE,
+0xFF5C9BCE,
+0xFF5D9CCF,
+0xFF5F9DD0,
+0xFF5F9DD0,
+0xFF5F9DD0,
+0xFF5F9DD0,
+0xFF5F9DD0,
+0xFF609ED1,
+0xFF609ED1,
+0xFF609ECF,
+0xFF619FD0,
+0xFF619FD0,
+0xFF62A0D1,
+0xFF62A0D1,
+0xFF63A1D2,
+0xFF63A1D2,
+0xFF63A1D2,
+0xFF64A2D1,
+0xFF65A3D2,
+0xFF65A3D2,
+0xFF66A4D3,
+0xFF66A4D3,
+0xFF65A3D2,
+0xFF65A3D2,
+0xFF66A4D3,
+0xFF66A4D3,
+0xFF67A5D4,
+0xFF67A5D4,
+0xFF67A5D4,
+0xFF67A5D4,
+0xFF67A5D4,
+0xFF67A5D4,
+0xFF68A6D5,
+0xFF68A7D3,
+0xFF67A6D2,
+0xFF68A7D3,
+0xFF68A7D3,
+0xFF68A7D3,
+0xFF68A7D3,
+0xFF68A7D3,
+0xFF68A7D3,
+0xFF68A7D3,
+0xFF68A7D3,
+0xFF68A7D3,
+0xFF69A8D4,
+0xFF69A8D4,
+0xFF69A8D4,
+0xFF69A8D4,
+0xFF69A8D4,
+0xFF69A8D4,
+0xFF6AA7D3,
+0xFF6AA7D4,
+0xFF6AA6D8,
+0xFF69A7D8,
+0xFF69A7D8,
+0xFF68A8D6,
+0xFF66A9D3,
+0xFF66AAD1,
+0xFF69AAD0,
+0xFF6AA9D2,
+0xFF6AA9D4,
+0xFF6BA8D5,
+0xFF69A7D6,
+0xFF68A8D6,
+0xFF66A9D6,
+0xFF66A9D6,
+0xFF6AAAD6,
+0xFF6DA6D1,
+0xFF7BA7CE,
+0xFF7EA1C1,
+0xFF688299,
+0xFF435464,
+0xFF2F3942,
+0xFF31363C,
+0xFF41414B,
+0xFF1F232F,
+0xFF162538,
+0xFF3E5A72,
+0xFF82AECB,
+0xFF7CB1D3,
+0xFF72A6CE,
+0xFF71A7D3,
+0xFF6CA9D6,
+0xFF6BAAD6,
+0xFF6AAAD8,
+0xFF6AAAD8,
+0xFF6BAAD6,
+0xFF6CA9D5,
+0xFF6EA9D3,
+0xFF6FA8D3,
+0xFF6EA9D5,
+0xFF6DAAD7,
+0xFF6DABDA,
+0xFF6CACDC,
+0xFF6BABD9,
+0xFF6CABD7,
+0xFF6DABD2,
+0xFF6DABD2,
+0xFF6BACD6,
+0xFF6BABD7,
+0xFF70AFDB,
+0xFF6EABD8,
+0xFF70ABD7,
+0xFF6FA5CB,
+0xFF7CA8C3,
+0xFFA7C6D8,
+0xFFBDCCD1,
+0xFFEAE5E1,
+0xFFFFE5DA,
+0xFFDAB4A7,
+0xFF715047,
+0xFF362B2F,
+0xFF5D788D,
+0xFF7EB0D1,
+0xFF72ACD4,
+0xFF6CA9D5,
+0xFF70ADD9,
+0xFF71AEDA,
+0xFF6CA9D5,
+0xFF6FACD8,
+0xFF6DAAD6,
+0xFF6DAAD6,
+0xFF6EABD7,
+0xFF6EABD7,
+0xFF6FACD8,
+0xFF6EABD7,
+0xFF6EABD7,
+0xFF6EABD7,
+0xFF6FACD8,
+0xFF6FACD8,
+0xFF6FADD6,
+0xFF6FADD6,
+0xFF6FADD6,
+0xFF6FADD6,
+0xFF6FADD6,
+0xFF6FADD6,
+0xFF6FADD6,
+0xFF6FADD6,
+0xFF6EACD5,
+0xFF6EACD5,
+0xFF6FADD6,
+0xFF6FADD6,
+0xFF6FADD6,
+0xFF6FADD6,
+0xFF6FADD6,
+0xFF6EACD5,
+0xFF70AED7,
+0xFF70AED7,
+0xFF70AED7,
+0xFF70AED7,
+0xFF70AED7,
+0xFF70AED7,
+0xFF70AED7,
+0xFF71AFD8,
+0xFF72ADD7,
+0xFF72ADD7,
+0xFF71ACD6,
+0xFF72ADD7,
+0xFF72ADD7,
+0xFF72ADD7,
+0xFF72ADD7,
+0xFF71ACD8,
+0xFF72ACDC,
+0xFF6FACDB,
+0xFF6BAAD6,
+0xFF72B1DA,
+0xFF70ABD3,
+0xFF75ACD5,
+0xFF76ACD8,
+0xFF74A9D1,
+0xFF78AACB,
+0xFF91B1CA,
+0xFF3B364D,
+0xFF504D68,
+0xFF8AB0D5,
+0xFF75ACD5,
+0xFF80ADD4,
+0xFF7A9EBE,
+0xFFB4CFE4,
+0xFFE4FBFF,
+0xFFE2FDFF,
+0xFFD0F1FF,
+0xFF9AC2DB,
+0xFF74A1BE,
+0xFF79AECE,
+0xFF73ABD0,
+0xFF73AED8,
+0xFF71AEDA,
+0xFF71AEDA,
+0xFF71AEDA,
+0xFF72ADD9,
+0xFF72ADD7,
+0xFF72ADD7,
+0xFF72ADD7,
+0xFF71ACD4,
+0xFF72B0D7,
+0xFF71B0D9,
+0xFF74ACCF,
+0xFF82A9C6,
+0xFFD6F1FF,
+0xFFEEFEFF,
+0xFFB9D0E2,
+0xFF77A2C2,
+0xFF77AFD4,
+0xFF73ADD3,
+0xFF70AED7,
+0xFF70AEDD,
+0xFF73B2DE,
+0xFF71ACD4,
+0xFF75AFD5,
+0xFF72ADD5,
+0xFF73AED8,
+0xFF73AED8,
+0xFF73AED8,
+0xFF72ADD7,
+0xFF72ADD7,
+0xFF72ADD7,
+0xFF72ADD7,
+0xFF72ADD7,
+0xFF72ADD7,
+0xFF73AED8,
+0xFF73AED8,
+0xFF73AED8,
+0xFF72ADD7,
+0xFF72ADD7,
+0xFF71ACD6,
+0xFF72ADD7,
+0xFF72ADD7,
+0xFF72ADD7,
+0xFF71ACD6,
+0xFF72ADD7,
+0xFF72ADD7,
+0xFF72ADD7,
+0xFF73AED8,
+0xFF72ADD7,
+0xFF72ADD7,
+0xFF72ADD7,
+0xFF71ACD6,
+0xFF71ACD6,
+0xFF71ACD6,
+0xFF71ACD6,
+0xFF71ACD6,
+0xFF72ADD9,
+0xFF72ADD9,
+0xFF72ADD9,
+0xFF72ADD9,
+0xFF71ACD8,
+0xFF71ACD8,
+0xFF71ACD8,
+0xFF71ACD8,
+0xFF71ACD8,
+0xFF71ACD8,
+0xFF71ACD8,
+0xFF71ACD8,
+0xFF71ACD8,
+0xFF71ACD8,
+0xFF71ACD8,
+0xFF71ACD8,
+0xFF71ACD8,
+0xFF71ACD8,
+0xFF70ABD7,
+0xFF70ABD7,
+0xFF70ABD7,
+0xFF70ABD7,
+0xFF6DAAD7,
+0xFF6DAAD7,
+0xFF6DAAD7,
+0xFF6DAAD7,
+0xFF6CABD7,
+0xFF6BAAD6,
+0xFF6BAAD6,
+0xFF6BAAD6,
+0xFF6BAAD6,
+0xFF6BAAD6,
+0xFF6CA9D5,
+0xFF6CA9D5,
+0xFF6CA9D6,
+0xFF6BA8D5,
+0xFF6AA7D4,
+0xFF69A6D3,
+0xFF68A7D3,
+0xFF69A8D4,
+0xFF68A6D5,
+0xFF68A6D5,
+0xFF69A7D6,
+0xFF69A7D6,
+0xFF68A6D5,
+0xFF67A5D4,
+0xFF67A5D4,
+0xFF66A4D3,
+0xFF65A5D3,
+0xFF64A4D2,
+0xFF63A3D1,
+0xFF62A2D0,
+0xFF62A2D2,
+0xFF62A2D2,
+0xFF61A1D1,
+0xFF5F9FCF,
+0xFF5FA1D3,
+0xFF5EA0D2,
+0xFF5EA0D4,
+0xFF5D9FD3,
+0xFF5D9FD3,
+0xFF5D9FD3,
+0xFF5B9ED2,
+0xFF5B9ED2,
+0xFF5796CB,
+0xFF5796CB,
+0xFF5897CC,
+0xFF5897CC,
+0xFF5897CC,
+0xFF5998CD,
+0xFF5A99CE,
+0xFF5B9ACF,
+0xFF5B9ACD,
+0xFF5B9ACD,
+0xFF5C9BCE,
+0xFF5D9CCF,
+0xFF5D9CCF,
+0xFF5D9CCF,
+0xFF5D9CCF,
+0xFF5D9CCF,
+0xFF5F9DCE,
+0xFF609ECF,
+0xFF609ECF,
+0xFF609ECF,
+0xFF609ECF,
+0xFF619FD0,
+0xFF62A0D1,
+0xFF63A1D2,
+0xFF63A1D2,
+0xFF63A1D0,
+0xFF63A1D0,
+0xFF64A2D1,
+0xFF64A2D1,
+0xFF64A2D1,
+0xFF64A2D1,
+0xFF64A2D1,
+0xFF67A4D3,
+0xFF67A4D1,
+0xFF67A4D1,
+0xFF67A4D1,
+0xFF67A4D1,
+0xFF67A4D1,
+0xFF68A5D2,
+0xFF68A5D2,
+0xFF67A6D2,
+0xFF67A6D2,
+0xFF67A6D2,
+0xFF67A6D2,
+0xFF68A7D3,
+0xFF68A7D3,
+0xFF68A7D3,
+0xFF68A7D3,
+0xFF68A7D3,
+0xFF68A7D2,
+0xFF68A7D2,
+0xFF68A7D2,
+0xFF68A7D2,
+0xFF69A8D3,
+0xFF69A8D3,
+0xFF69A8D3,
+0xFF69A8D3,
+0xFF68A7D2,
+0xFF68A7D3,
+0xFF69A8D4,
+0xFF69A8D4,
+0xFF68A7D3,
+0xFF68A7D3,
+0xFF69A8D4,
+0xFF6AA9D4,
+0xFF6AA9D4,
+0xFF6AA8D7,
+0xFF6AA8D9,
+0xFF6AA8D9,
+0xFF6AA8D7,
+0xFF6AA9D4,
+0xFF6AA9D2,
+0xFF69A9CF,
+0xFF6BAAD3,
+0xFF6BAAD6,
+0xFF68A6D5,
+0xFF6DABDA,
+0xFF6CAAD9,
+0xFF68A9D3,
+0xFF6BA9D2,
+0xFF72A8D4,
+0xFF87B2D5,
+0xFF7D8FA7,
+0xFF5B5B63,
+0xFF6F6460,
+0xFF524233,
+0xFF907F6F,
+0xFFBEAB9C,
+0xFFE1CBBE,
+0xFFB6A095,
+0xFF6A5951,
+0xFF484340,
+0xFF09131C,
+0xFF4B647A,
+0xFF8DB3D8,
+0xFF7AA9D5,
+0xFF71A7D3,
+0xFF6EABD7,
+0xFF6EADD9,
+0xFF6CACDA,
+0xFF69A9D7,
+0xFF6CABD7,
+0xFF70ABD5,
+0xFF70A9D4,
+0xFF72ABD8,
+0xFF70AAD8,
+0xFF6DABDA,
+0xFF6BABDB,
+0xFF6DABDA,
+0xFF6EABD7,
+0xFF71ADD2,
+0xFF71ADD2,
+0xFF6FAFD5,
+0xFF6CABD4,
+0xFF70AED7,
+0xFF71ACD6,
+0xFF71AAD7,
+0xFF77A7CB,
+0xFF95B4C8,
+0xFFE8F5FB,
+0xFFF8F1E9,
+0xFFF1DCCB,
+0xFFD7B29F,
+0xFFCBA290,
+0xFF956F62,
+0xFF302021,
+0xFF7D91A9,
+0xFF7FABD0,
+0xFF74ABD4,
+0xFF71ACD8,
+0xFF71ACD8,
+0xFF71ACD8,
+0xFF71ACD6,
+0xFF71ACD6,
+0xFF71ACD6,
+0xFF71ACD6,
+0xFF71ACD6,
+0xFF71ACD6,
+0xFF71ACD6,
+0xFF71ACD6,
+0xFF71ACD6,
+0xFF71ACD6,
+0xFF72ADD7,
+0xFF72ADD7,
+0xFF71ACD6,
+0xFF71ACD6,
+0xFF71ACD6,
+0xFF71ACD6,
+0xFF71ACD6,
+0xFF71ACD6,
+0xFF71ACD6,
+0xFF71ACD6,
+0xFF72ADD7,
+0xFF72ADD7,
+0xFF72ADD7,
+0xFF72ADD7,
+0xFF72ADD7,
+0xFF72ADD7,
+0xFF72ADD7,
+0xFF72ADD7,
+0xFF72ADD5,
+0xFF72ADD5,
+0xFF72ADD5,
+0xFF72ADD5,
+0xFF72ADD5,
+0xFF73AED6,
+0xFF73AED6,
+0xFF73AED6,
+0xFF73AED6,
+0xFF73AED6,
+0xFF73AED6,
+0xFF73AED6,
+0xFF73AED6,
+0xFF73AED6,
+0xFF72ADD5,
+0xFF72ADD7,
+0xFF71AEDB,
+0xFF71AEDB,
+0xFF73AEDA,
+0xFF74AFD7,
+0xFF77AED5,
+0xFF77AED5,
+0xFF73AED8,
+0xFF73AED6,
+0xFF76AED3,
+0xFF88ACCC,
+0xFF9393AD,
+0xFF54516C,
+0xFF7E9CBE,
+0xFF7CACD2,
+0xFF7AABD4,
+0xFF7DADD5,
+0xFF77A2C4,
+0xFFA3C5DE,
+0xFFDFF6FF,
+0xFFE2F5FC,
+0xFFEAFBFF,
+0xFFCCE2EF,
+0xFF86AAC2,
+0xFF7AA8CA,
+0xFF77ADD9,
+0xFF72AFDC,
+0xFF73AEDA,
+0xFF78B3DD,
+0xFF74AED4,
+0xFF74B0D5,
+0xFF6CACD2,
+0xFF74B3DC,
+0xFF71B0D9,
+0xFF6DADD3,
+0xFF73B1D6,
+0xFF7AABC9,
+0xFFC7E1F2,
+0xFFEAFDFF,
+0xFFBFDEFA,
+0xFF77A2C4,
+0xFF79ADD2,
+0xFF75AFD5,
+0xFF74AFD7,
+0xFF74AFD9,
+0xFF74AFDB,
+0xFF74AFD9,
+0xFF74AFD7,
+0xFF74B0D5,
+0xFF74AED6,
+0xFF75AFD7,
+0xFF75AFD7,
+0xFF75AFD7,
+0xFF75AFD7,
+0xFF75AFD7,
+0xFF75AFD7,
+0xFF75AFD7,
+0xFF75AFD7,
+0xFF75AFD7,
+0xFF75AFD7,
+0xFF74AED6,
+0xFF74AED6,
+0xFF74AED6,
+0xFF74AED6,
+0xFF74AED6,
+0xFF74AFD7,
+0xFF74AFD7,
+0xFF74AFD7,
+0xFF74AFD7,
+0xFF74AFD7,
+0xFF74AFD7,
+0xFF74AFD7,
+0xFF73AED6,
+0xFF73AED6,
+0xFF73AED6,
+0xFF73AED6,
+0xFF73AED6,
+0xFF73AED6,
+0xFF73AED6,
+0xFF73AED6,
+0xFF73AED6,
+0xFF73AED8,
+0xFF73AED8,
+0xFF73AED8,
+0xFF73AED8,
+0xFF72ADD7,
+0xFF72ADD7,
+0xFF72ADD7,
+0xFF72ADD7,
+0xFF72ADD7,
+0xFF72ADD7,
+0xFF72ADD7,
+0xFF72ADD7,
+0xFF72ADD7,
+0xFF72ADD7,
+0xFF72ADD7,
+0xFF72ADD7,
+0xFF73ACD9,
+0xFF72ABD8,
+0xFF71ACD8,
+0xFF71ACD8,
+0xFF71ACD8,
+0xFF71ACD8,
+0xFF71ACD8,
+0xFF71ACD8,
+0xFF6EABD7,
+0xFF6EABD7,
+0xFF6EABD7,
+0xFF6EABD7,
+0xFF6DAAD6,
+0xFF6DAAD6,
+0xFF6CABD6,
+0xFF6CABD6,
+0xFF6BAAD5,
+0xFF6BAAD5,
+0xFF6AA9D4,
+0xFF6AA9D4,
+0xFF6AA9D4,
+0xFF6AA9D4,
+0xFF6AA9D4,
+0xFF6AA9D4,
+0xFF68A7D3,
+0xFF68A7D3,
+0xFF67A7D3,
+0xFF68A8D4,
+0xFF67A7D3,
+0xFF67A7D3,
+0xFF67A7D5,
+0xFF67A7D5,
+0xFF67A6D2,
+0xFF67A6D2,
+0xFF66A5D1,
+0xFF65A4D0,
+0xFF65A3D2,
+0xFF64A2D1,
+0xFF63A3D1,
+0xFF62A2D0,
+0xFF61A1D1,
+0xFF61A1D1,
+0xFF5FA1D3,
+0xFF5EA0D2,
+0xFF5EA0D2,
+0xFF5D9FD1,
+0xFF5C9ED0,
+0xFF5C9ED0,
+0xFF5796CB,
+0xFF5897CC,
+0xFF5998CD,
+0xFF5998CD,
+0xFF5998CD,
+0xFF5A99CE,
+0xFF5B9ACF,
+0xFF5B9ACF,
+0xFF5C9BCE,
+0xFF5C9BCE,
+0xFF5D9CCF,
+0xFF5D9CCF,
+0xFF5D9CCF,
+0xFF5E9DD0,
+0xFF5E9DD0,
+0xFF5E9DD0,
+0xFF5F9DCE,
+0xFF609ECF,
+0xFF609ECF,
+0xFF609ECF,
+0xFF609ECF,
+0xFF619FD0,
+0xFF62A0D1,
+0xFF63A1D2,
+0xFF64A2D1,
+0xFF64A2D1,
+0xFF64A2D1,
+0xFF65A3D2,
+0xFF65A3D2,
+0xFF66A4D3,
+0xFF66A4D3,
+0xFF66A4D3,
+0xFF67A4D1,
+0xFF67A4D1,
+0xFF68A5D2,
+0xFF68A5D2,
+0xFF68A5D2,
+0xFF68A5D2,
+0xFF68A5D2,
+0xFF69A6D3,
+0xFF68A7D3,
+0xFF68A7D3,
+0xFF68A7D3,
+0xFF68A7D3,
+0xFF68A7D3,
+0xFF68A7D3,
+0xFF69A8D4,
+0xFF69A8D4,
+0xFF69A8D3,
+0xFF69A8D3,
+0xFF69A8D3,
+0xFF69A8D3,
+0xFF69A8D3,
+0xFF69A8D3,
+0xFF69A8D3,
+0xFF6AA9D4,
+0xFF6AA9D4,
+0xFF69A8D3,
+0xFF69A8D4,
+0xFF6AA9D5,
+0xFF6AA9D5,
+0xFF69A8D4,
+0xFF69A8D4,
+0xFF6AA9D4,
+0xFF6AA9D2,
+0xFF6AA9D2,
+0xFF6AA9D5,
+0xFF6AA8D7,
+0xFF6BA8D7,
+0xFF6BA8D7,
+0xFF6EA9D5,
+0xFF6EA9D3,
+0xFF70AED7,
+0xFF6CAAD3,
+0xFF6DACD8,
+0xFF6BA9D8,
+0xFF69A6D5,
+0xFF6CA7D3,
+0xFF6FA9CE,
+0xFF78AACB,
+0xFF83A7C7,
+0xFF4B6075,
+0xFF58555C,
+0xFF9A8780,
+0xFF93745F,
+0xFF4E2A10,
+0xFF6B4930,
+0xFF785841,
+0xFF6F4F3A,
+0xFF876653,
+0xFF997865,
+0xFF624B3D,
+0xFF615853,
+0xFF171B24,
+0xFF1A2C44,
+0xFF87A8C9,
+0xFF81AED5,
+0xFF72A7D1,
+0xFF6EA9D5,
+0xFF6EADD9,
+0xFF6DADDB,
+0xFF6FAEDA,
+0xFF73AEDA,
+0xFF70A9D4,
+0xFF72ABD8,
+0xFF71ACD8,
+0xFF6DABDA,
+0xFF6CACDA,
+0xFF6EADD9,
+0xFF6FADD6,
+0xFF72ACD2,
+0xFF72ACD1,
+0xFF6FADD2,
+0xFF6EACD3,
+0xFF72ADD7,
+0xFF73ACD9,
+0xFF72A8D4,
+0xFF7DA8CA,
+0xFFAEC1D0,
+0xFFF0EFED,
+0xFFF9E3D5,
+0xFFDFBFA8,
+0xFFBA957B,
+0xFF6A442F,
+0xFF462418,
+0xFF352629,
+0xFF374761,
+0xFF87AED5,
+0xFF76ABD5,
+0xFF72ADD9,
+0xFF72ADD9,
+0xFF72ADD7,
+0xFF72ADD7,
+0xFF72ADD7,
+0xFF72ADD7,
+0xFF72ADD7,
+0xFF72ADD7,
+0xFF72ADD7,
+0xFF72ADD7,
+0xFF72ADD7,
+0xFF72ADD7,
+0xFF72ADD7,
+0xFF73AED8,
+0xFF73AED8,
+0xFF73AED8,
+0xFF73AED8,
+0xFF73AED8,
+0xFF73AED8,
+0xFF73AED8,
+0xFF73AED8,
+0xFF73AED8,
+0xFF73AED8,
+0xFF73AED8,
+0xFF73AED8,
+0xFF73AED8,
+0xFF73AED8,
+0xFF73AED8,
+0xFF73AED8,
+0xFF73AED8,
+0xFF73AED6,
+0xFF73AED6,
+0xFF73AED6,
+0xFF73AED6,
+0xFF73AED6,
+0xFF73AED6,
+0xFF73AED6,
+0xFF74AFD7,
+0xFF74AFD7,
+0xFF73AED6,
+0xFF73AED6,
+0xFF74AFD7,
+0xFF74AFD7,
+0xFF73AED6,
+0xFF73AED6,
+0xFF73AED6,
+0xFF73AED6,
+0xFF73AEDA,
+0xFF74AFD9,
+0xFF75AFD7,
+0xFF75AFD5,
+0xFF75AFD5,
+0xFF75AFD5,
+0xFF74AFD9,
+0xFF74AFDB,
+0xFF72ACD4,
+0xFF83ADD3,
+0xFF9AA9CA,
+0xFF4E5977,
+0xFF506B89,
+0xFF8CB3D4,
+0xFF79A9D1,
+0xFF77AAD5,
+0xFF77ABD3,
+0xFF79A6C7,
+0xFF95B4C8,
+0xFFE2F6FF,
+0xFFE7F5F8,
+0xFFEDFAFF,
+0xFFE5FBFF,
+0xFFAACAE1,
+0xFF7AA5C7,
+0xFF78A8D0,
+0xFF7CB0D8,
+0xFF76ADD4,
+0xFF75AFD4,
+0xFF76B2D6,
+0xFF74B4D8,
+0xFF6FAFD3,
+0xFF73B3D9,
+0xFF75B1D6,
+0xFF77ACCC,
+0xFF9AC2DB,
+0xFFE8FFFF,
+0xFFD2ECFD,
+0xFF749FC1,
+0xFF7AAFD7,
+0xFF78AFD6,
+0xFF76B0D6,
+0xFF75B0D8,
+0xFF75B0D8,
+0xFF76B0D8,
+0xFF76B0D8,
+0xFF76B0D6,
+0xFF75AFD5,
+0xFF75AFD7,
+0xFF75AFD7,
+0xFF76B0D8,
+0xFF76B0D8,
+0xFF76B0D8,
+0xFF76B0D8,
+0xFF76B0D8,
+0xFF76B0D8,
+0xFF75AFD7,
+0xFF75AFD7,
+0xFF75AFD7,
+0xFF75AFD7,
+0xFF75AFD7,
+0xFF75AFD7,
+0xFF75AFD7,
+0xFF75AFD7,
+0xFF74AFD7,
+0xFF74AFD7,
+0xFF74AFD7,
+0xFF74AFD7,
+0xFF74AFD7,
+0xFF74AFD7,
+0xFF74AFD7,
+0xFF74AFD7,
+0xFF75B0D8,
+0xFF75B0D8,
+0xFF75B0D8,
+0xFF75B0D8,
+0xFF74AFD7,
+0xFF74AFD7,
+0xFF74AFD7,
+0xFF74AFD7,
+0xFF75B0DA,
+0xFF75B0DA,
+0xFF75B0DA,
+0xFF75B0DA,
+0xFF74AFD9,
+0xFF74AFD9,
+0xFF74AFD9,
+0xFF74AFD9,
+0xFF74AFD9,
+0xFF74AFD9,
+0xFF74AFD9,
+0xFF73AED8,
+0xFF73AED8,
+0xFF73AED8,
+0xFF73AED8,
+0xFF73AED8,
+0xFF73ACD9,
+0xFF73ACD9,
+0xFF72ADD9,
+0xFF72ADD9,
+0xFF72ADD9,
+0xFF72ADD9,
+0xFF72ADD9,
+0xFF72ADD9,
+0xFF6FACD8,
+0xFF6FACD8,
+0xFF6FACD8,
+0xFF6FACD8,
+0xFF6FACD8,
+0xFF6EABD7,
+0xFF6EABD7,
+0xFF6DACD7,
+0xFF6CABD6,
+0xFF6CABD6,
+0xFF6CABD6,
+0xFF6BAAD5,
+0xFF6BAAD5,
+0xFF6AA9D4,
+0xFF6AA9D4,
+0xFF6AA9D4,
+0xFF69A8D4,
+0xFF69A8D4,
+0xFF68A8D4,
+0xFF68A8D4,
+0xFF68A8D4,
+0xFF67A7D3,
+0xFF67A7D5,
+0xFF67A7D5,
+0xFF68A7D3,
+0xFF68A7D3,
+0xFF67A6D2,
+0xFF66A5D1,
+0xFF66A4D3,
+0xFF65A3D2,
+0xFF64A4D2,
+0xFF64A4D2,
+0xFF62A2D2,
+0xFF62A2D2,
+0xFF60A2D4,
+0xFF5FA1D3,
+0xFF5FA1D3,
+0xFF5EA0D2,
+0xFF5D9FD1,
+0xFF5D9FD1,
+0xFF5897CA,
+0xFF5998CB,
+0xFF5A99CC,
+0xFF5A99CC,
+0xFF5B9ACD,
+0xFF5B9ACD,
+0xFF5C9BCE,
+0xFF5C9BCE,
+0xFF5E9DD0,
+0xFF5E9DD0,
+0xFF5F9DCE,
+0xFF5F9DCE,
+0xFF5F9DCE,
+0xFF5F9DCE,
+0xFF609ECF,
+0xFF609ECF,
+0xFF619FD0,
+0xFF619FD0,
+0xFF619FCE,
+0xFF62A0CF,
+0xFF62A0CF,
+0xFF62A0CF,
+0xFF63A1D0,
+0xFF64A2D1,
+0xFF64A2D1,
+0xFF65A3D2,
+0xFF65A4D0,
+0xFF66A5D1,
+0xFF67A6D2,
+0xFF67A6D2,
+0xFF67A6D2,
+0xFF67A6D2,
+0xFF68A5D2,
+0xFF68A5D2,
+0xFF68A5D2,
+0xFF69A6D3,
+0xFF68A5D2,
+0xFF68A5D2,
+0xFF69A6D3,
+0xFF69A6D3,
+0xFF69A6D3,
+0xFF69A6D3,
+0xFF6AA7D3,
+0xFF6AA7D3,
+0xFF6AA7D3,
+0xFF6AA7D3,
+0xFF6AA7D3,
+0xFF6AA7D3,
+0xFF6BA8D4,
+0xFF6BA8D4,
+0xFF6BA8D4,
+0xFF6BA8D4,
+0xFF6BA8D4,
+0xFF6BA8D4,
+0xFF6BA8D4,
+0xFF6BA8D4,
+0xFF6CA9D5,
+0xFF6CA9D5,
+0xFF6CA9D5,
+0xFF6DAAD6,
+0xFF6DAAD6,
+0xFF6CA9D5,
+0xFF6CA9D5,
+0xFF6DAAD6,
+0xFF6DABD4,
+0xFF6CAAD3,
+0xFF6BAAD5,
+0xFF6BAAD6,
+0xFF6CA9D6,
+0xFF6FA9D7,
+0xFF70A9D6,
+0xFF70A9D4,
+0xFF6DA8D2,
+0xFF6EABD7,
+0xFF6EACDB,
+0xFF6EABDA,
+0xFF73ACD9,
+0xFF74AAD0,
+0xFF7AA9C5,
+0xFF86A7BA,
+0xFF646F75,
+0xFF443F3C,
+0xFF9D8B7F,
+0xFFCFB4A1,
+0xFFC9A690,
+0xFF552F18,
+0xFF7C5842,
+0xFF54311E,
+0xFF583728,
+0xFF4F2F22,
+0xFF573A2C,
+0xFF705649,
+0xFF635147,
+0xFF554A46,
+0xFF1A1519,
+0xFF28323E,
+0xFF8BA9C5,
+0xFF83AFD4,
+0xFF76AAD2,
+0xFF73AEDA,
+0xFF6EADD9,
+0xFF6DACD8,
+0xFF6FACD8,
+0xFF72ADD7,
+0xFF73ACD7,
+0xFF72ADD9,
+0xFF6FACDB,
+0xFF6FADDC,
+0xFF6FAEDA,
+0xFF70AED7,
+0xFF75ACD3,
+0xFF75ADD0,
+0xFF74AED3,
+0xFF70ABD3,
+0xFF75B2E1,
+0xFF70AADA,
+0xFF7AAED6,
+0xFF7EA1BD,
+0xFFC0CAD4,
+0xFFF8EDEB,
+0xFFF5D8CA,
+0xFFBA947F,
+0xFF916D55,
+0xFF452612,
+0xFF3C251F,
+0xFF342D35,
+0xFF000120,
+0xFF7293BC,
+0xFF78ABD6,
+0xFF73AED8,
+0xFF73AED8,
+0xFF73AED8,
+0xFF73AED8,
+0xFF73AED6,
+0xFF73AED6,
+0xFF73AED6,
+0xFF73AED6,
+0xFF73AED6,
+0xFF73AED6,
+0xFF73AED6,
+0xFF73AED6,
+0xFF73AED6,
+0xFF74AFD7,
+0xFF74AFD7,
+0xFF74AFD7,
+0xFF74AFD7,
+0xFF74AFD7,
+0xFF75B0D8,
+0xFF75B0D8,
+0xFF75B0D8,
+0xFF75B0D8,
+0xFF75B0D8,
+0xFF75B0D8,
+0xFF75B0D8,
+0xFF75B0D8,
+0xFF75B0D8,
+0xFF75B0D8,
+0xFF75B0D8,
+0xFF75B0D8,
+0xFF75B0D8,
+0xFF74AFD7,
+0xFF74B0D5,
+0xFF74B0D5,
+0xFF74B0D5,
+0xFF74B0D5,
+0xFF74B0D5,
+0xFF74B0D5,
+0xFF74B0D5,
+0xFF74B0D5,
+0xFF75B1D6,
+0xFF75B1D6,
+0xFF75B1D6,
+0xFF76B0D6,
+0xFF75AFD5,
+0xFF75AFD5,
+0xFF75AFD5,
+0xFF78AFD6,
+0xFF78B0D5,
+0xFF78B0D5,
+0xFF76B0D5,
+0xFF73B1D6,
+0xFF73B1D8,
+0xFF76AFDC,
+0xFF78AEDD,
+0xFF78AEDD,
+0xFF7FB2DF,
+0xFF81ACD6,
+0xFF80A2C7,
+0xFF425978,
+0xFF95B0CB,
+0xFF82ADCF,
+0xFF7BAFD6,
+0xFF79B0D7,
+0xFF7BB1D7,
+0xFF7CAACB,
+0xFF86ACC3,
+0xFFCDE9F7,
+0xFFE0F3FA,
+0xFFE7F2F8,
+0xFFEDF7FF,
+0xFFE1F3FF,
+0xFF9CB6CD,
+0xFF7AA3C3,
+0xFF7CB0D5,
+0xFF76B0D6,
+0xFF73B1D6,
+0xFF77B4D3,
+0xFF75B0D0,
+0xFF74AFD1,
+0xFF7EB1D0,
+0xFF90B4CC,
+0xFFD9F9FF,
+0xFFD3F7FF,
+0xFF7AA6C3,
+0xFF80B2D5,
+0xFF77AFD4,
+0xFF79B0D7,
+0xFF77B1D9,
+0xFF76B1D9,
+0xFF76B2D7,
+0xFF77B1D7,
+0xFF77B1D6,
+0xFF77B1D7,
+0xFF77B1D7,
+0xFF77B1D7,
+0xFF77B1D7,
+0xFF77B1D7,
+0xFF77B1D7,
+0xFF77B1D7,
+0xFF77B1D7,
+0xFF77B1D7,
+0xFF77B1D7,
+0xFF76B0D6,
+0xFF76B0D6,
+0xFF76B0D6,
+0xFF76B0D6,
+0xFF76B0D6,
+0xFF76B0D6,
+0xFF76B0D6,
+0xFF76B0D6,
+0xFF75B1D6,
+0xFF75B1D6,
+0xFF75B1D6,
+0xFF75B1D6,
+0xFF75B1D6,
+0xFF75B1D6,
+0xFF75B1D6,
+0xFF75B1D6,
+0xFF75B1D6,
+0xFF75B1D6,
+0xFF75B1D6,
+0xFF75B1D6,
+0xFF75B1D6,
+0xFF75B1D6,
+0xFF75B1D6,
+0xFF75B1D6,
+0xFF75B0D8,
+0xFF75B0D8,
+0xFF75B0D8,
+0xFF75B0D8,
+0xFF75B0D8,
+0xFF75B0D8,
+0xFF75B0D8,
+0xFF75B0D8,
+0xFF75B0D8,
+0xFF75B0D8,
+0xFF75B0D8,
+0xFF75B0D8,
+0xFF75B0D8,
+0xFF74AFD7,
+0xFF74AFD7,
+0xFF74AFD7,
+0xFF75AED9,
+0xFF74ADD8,
+0xFF74ADD8,
+0xFF74ADD8,
+0xFF73AED8,
+0xFF73AED8,
+0xFF73AED8,
+0xFF73AED8,
+0xFF72ADD7,
+0xFF72ADD7,
+0xFF72ADD7,
+0xFF72ADD7,
+0xFF72ADD7,
+0xFF6FADD6,
+0xFF6FADD6,
+0xFF6FADD6,
+0xFF6EADD6,
+0xFF6EADD6,
+0xFF6EADD6,
+0xFF6DACD5,
+0xFF6CABD4,
+0xFF6CABD4,
+0xFF6BAAD5,
+0xFF6BAAD5,
+0xFF6BAAD5,
+0xFF6BAAD5,
+0xFF69AAD4,
+0xFF69AAD4,
+0xFF68A8D4,
+0xFF68A8D4,
+0xFF68A8D4,
+0xFF68A8D4,
+0xFF69A8D4,
+0xFF68A7D3,
+0xFF68A7D3,
+0xFF67A6D2,
+0xFF67A6D2,
+0xFF67A6D2,
+0xFF66A4D3,
+0xFF66A4D3,
+0xFF64A4D2,
+0xFF64A4D2,
+0xFF63A3D3,
+0xFF63A3D3,
+0xFF62A2D2,
+0xFF62A2D2,
+0xFF61A1D1,
+0xFF61A1D1,
+0xFF5998CB,
+0xFF5A99CC,
+0xFF5B9ACD,
+0xFF5C9BCE,
+0xFF5C9BCE,
+0xFF5C9BCE,
+0xFF5C9BCE,
+0xFF5C9BCE,
+0xFF5F9ED1,
+0xFF5F9ED1,
+0xFF5F9DCE,
+0xFF5F9DCE,
+0xFF609ECF,
+0xFF609ECF,
+0xFF619FD0,
+0xFF619FD0,
+0xFF62A0D1,
+0xFF62A0D1,
+0xFF63A1D0,
+0xFF63A1D0,
+0xFF64A2D1,
+0xFF64A2D1,
+0xFF65A3D2,
+0xFF65A3D2,
+0xFF65A3D2,
+0xFF65A3D2,
+0xFF66A5D1,
+0xFF66A5D1,
+0xFF67A6D2,
+0xFF67A6D2,
+0xFF67A6D2,
+0xFF68A7D3,
+0xFF68A5D2,
+0xFF68A5D2,
+0xFF69A6D3,
+0xFF69A6D3,
+0xFF69A6D3,
+0xFF69A6D3,
+0xFF69A6D3,
+0xFF6AA7D4,
+0xFF6AA7D4,
+0xFF6AA7D4,
+0xFF6AA7D3,
+0xFF6AA7D3,
+0xFF6BA8D4,
+0xFF6BA8D4,
+0xFF6BA8D4,
+0xFF6BA8D4,
+0xFF6CA9D5,
+0xFF6CA9D5,
+0xFF6CA9D5,
+0xFF6CA9D5,
+0xFF6CA9D5,
+0xFF6CA9D5,
+0xFF6CA9D5,
+0xFF6CA9D5,
+0xFF6DAAD6,
+0xFF6DAAD6,
+0xFF6DAAD6,
+0xFF6EABD7,
+0xFF6EABD7,
+0xFF6DAAD6,
+0xFF6DAAD6,
+0xFF6EACD5,
+0xFF70ABD5,
+0xFF6EACD5,
+0xFF6DACD5,
+0xFF6DACD7,
+0xFF6EABD8,
+0xFF70ABD7,
+0xFF71AAD7,
+0xFF73A9D7,
+0xFF6FA8D3,
+0xFF6DAAD6,
+0xFF71AEDD,
+0xFF6EA8D6,
+0xFF74A7D2,
+0xFF7FACCD,
+0xFF87A7BC,
+0xFF5E6F76,
+0xFF4B423B,
+0xFF715C4B,
+0xFFEAD1BD,
+0xFFFFE7D1,
+0xFFAF8C76,
+0xFF815D47,
+0xFFAB8673,
+0xFF987464,
+0xFF5F4234,
+0xFF3B2015,
+0xFF3A2218,
+0xFF321C11,
+0xFF624B43,
+0xFF67534C,
+0xFF3D2C24,
+0xFF1E1A1B,
+0xFF465769,
+0xFF87A8C7,
+0xFF7FABD0,
+0xFF76ABD5,
+0xFF70ABD7,
+0xFF71B0DC,
+0xFF72ADD7,
+0xFF73ACD7,
+0xFF73ADD5,
+0xFF73ACD7,
+0xFF70ADDA,
+0xFF6FAEDA,
+0xFF70AFDB,
+0xFF71AFD8,
+0xFF76ADD4,
+0xFF76AED1,
+0xFF75B0D2,
+0xFF71ACD4,
+0xFF6BA8D7,
+0xFF77ADDC,
+0xFF7AA6C9,
+0xFF91ADC3,
+0xFFE7F0F7,
+0xFFF4EBE6,
+0xFFDFC9BC,
+0xFFA28573,
+0xFF4E3320,
+0xFF342113,
+0xFF2A2124,
+0xFF3E4557,
+0xFF587190,
+0xFF8AB1DA,
+0xFF78ADD5,
+0xFF74AFD7,
+0xFF74AFD9,
+0xFF74AFD7,
+0xFF74AFD7,
+0xFF74AFD7,
+0xFF74AFD7,
+0xFF74AFD7,
+0xFF74AFD7,
+0xFF74AFD7,
+0xFF74AFD7,
+0xFF74AFD7,
+0xFF74AFD7,
+0xFF74AFD7,
+0xFF75B0D8,
+0xFF75B0D8,
+0xFF75B0D8,
+0xFF75B0D8,
+0xFF75B0D8,
+0xFF75B0D8,
+0xFF75B0D8,
+0xFF75B0D8,
+0xFF75B0D8,
+0xFF75B0D8,
+0xFF75B0D8,
+0xFF75B0D8,
+0xFF75B0D8,
+0xFF75B0D8,
+0xFF75B0D8,
+0xFF75B0D8,
+0xFF75B0D8,
+0xFF75B0D8,
+0xFF75B1D6,
+0xFF75B1D6,
+0xFF75B1D6,
+0xFF75B1D6,
+0xFF75B1D6,
+0xFF75B1D6,
+0xFF75B1D6,
+0xFF75B1D6,
+0xFF76B2D7,
+0xFF76B2D7,
+0xFF76B2D7,
+0xFF76B2D7,
+0xFF77B1D7,
+0xFF77B1D7,
+0xFF77B1D7,
+0xFF77B1D7,
+0xFF7AB0D6,
+0xFF7AB0D4,
+0xFF79B1D4,
+0xFF77B1D6,
+0xFF73B3D7,
+0xFF73B3D9,
+0xFF77B0DD,
+0xFF79AFDD,
+0xFF7AB0DF,
+0xFF72ABD8,
+0xFF79B4E0,
+0xFF89B6DD,
+0xFF516580,
+0xFF8495AF,
+0xFF84ADCD,
+0xFF7AB0D6,
+0xFF79B0D7,
+0xFF74AED6,
+0xFF78B2D8,
+0xFF79AED0,
+0xFF7EA8C1,
+0xFFC1E1F0,
+0xFFE6F5FC,
+0xFFE9F1F4,
+0xFFEAF1F7,
+0xFFEBF7FF,
+0xFFC8E1F7,
+0xFF8AAFCA,
+0xFF7AABCC,
+0xFF79AFD1,
+0xFF7AB3D1,
+0xFF7BB2D0,
+0xFF7FB0CE,
+0xFF83ABC5,
+0xFFD2EEFF,
+0xFFE0FCFF,
+0xFF78A5C4,
+0xFF77ABD0,
+0xFF7BB1D3,
+0xFF7BB1D5,
+0xFF79B1D6,
+0xFF77B1D7,
+0xFF74B2D9,
+0xFF75B3D8,
+0xFF77B3D7,
+0xFF78B2D7,
+0xFF7AB2D7,
+0xFF7AB1D8,
+0xFF78B2D8,
+0xFF78B2D8,
+0xFF78B2D8,
+0xFF78B2D8,
+0xFF78B2D8,
+0xFF78B2D8,
+0xFF78B2D8,
+0xFF78B2D8,
+0xFF77B1D7,
+0xFF77B1D7,
+0xFF77B1D7,
+0xFF77B1D7,
+0xFF77B1D7,
+0xFF77B1D7,
+0xFF77B1D7,
+0xFF77B1D7,
+0xFF76B2D7,
+0xFF76B2D7,
+0xFF76B2D7,
+0xFF76B2D7,
+0xFF76B2D7,
+0xFF76B2D7,
+0xFF76B2D7,
+0xFF76B2D7,
+0xFF76B2D7,
+0xFF76B2D7,
+0xFF76B2D7,
+0xFF75B1D6,
+0xFF75B1D6,
+0xFF75B1D6,
+0xFF75B1D6,
+0xFF75B1D6,
+0xFF75B0D8,
+0xFF75B0D8,
+0xFF75B0D8,
+0xFF75B0D8,
+0xFF75B0D8,
+0xFF75B0D8,
+0xFF75B0D8,
+0xFF75B0D8,
+0xFF75B0D8,
+0xFF75B0D8,
+0xFF75B0D8,
+0xFF75B0D8,
+0xFF75B0D8,
+0xFF75B0D8,
+0xFF75B0D8,
+0xFF75B0D8,
+0xFF76AFDA,
+0xFF75AED9,
+0xFF75AED9,
+0xFF75AED9,
+0xFF74AFD9,
+0xFF74AFD9,
+0xFF74AFD9,
+0xFF74AFD9,
+0xFF73AED8,
+0xFF73AED8,
+0xFF73AED8,
+0xFF73AED8,
+0xFF72ADD7,
+0xFF72ADD7,
+0xFF70AED7,
+0xFF6FADD6,
+0xFF70AED7,
+0xFF6FAED7,
+0xFF70AED7,
+0xFF6EADD6,
+0xFF6EADD6,
+0xFF6DACD5,
+0xFF6CABD6,
+0xFF6CABD6,
+0xFF6DACD7,
+0xFF6CABD6,
+0xFF6BAAD5,
+0xFF69AAD4,
+0xFF69A9D5,
+0xFF68A8D4,
+0xFF68A8D4,
+0xFF69A9D5,
+0xFF69A8D4,
+0xFF69A8D4,
+0xFF69A8D4,
+0xFF68A7D3,
+0xFF68A7D3,
+0xFF68A7D3,
+0xFF68A6D5,
+0xFF68A6D5,
+0xFF65A5D3,
+0xFF65A5D3,
+0xFF65A5D5,
+0xFF64A4D4,
+0xFF64A4D4,
+0xFF63A3D3,
+0xFF63A3D3,
+0xFF62A2D2,
+0xFF5998CB,
+0xFF5A99CC,
+0xFF5C9BCE,
+0xFF5C9BCE,
+0xFF5D9CCF,
+0xFF5D9CCF,
+0xFF5E9CCD,
+0xFF5E9CCD,
+0xFF609ECF,
+0xFF609ECF,
+0xFF609ECF,
+0xFF609ECF,
+0xFF609ECF,
+0xFF619FD0,
+0xFF619FD0,
+0xFF62A0D1,
+0xFF64A1D0,
+0xFF64A1D0,
+0xFF65A2D1,
+0xFF65A2D1,
+0xFF66A3D2,
+0xFF66A3D2,
+0xFF67A4D1,
+0xFF67A4D1,
+0xFF67A4D1,
+0xFF68A5D2,
+0xFF68A5D2,
+0xFF68A5D2,
+0xFF68A5D2,
+0xFF68A5D2,
+0xFF68A5D2,
+0xFF68A5D2,
+0xFF68A5D2,
+0xFF69A6D3,
+0xFF69A6D3,
+0xFF69A6D3,
+0xFF69A6D2,
+0xFF69A6D2,
+0xFF6AA7D3,
+0xFF6AA7D3,
+0xFF6BA8D4,
+0xFF6BA8D4,
+0xFF6BA8D4,
+0xFF6BA8D4,
+0xFF6DA8D4,
+0xFF6EA9D5,
+0xFF6EA9D3,
+0xFF6EA9D3,
+0xFF6FAAD6,
+0xFF6FAAD6,
+0xFF6FAAD6,
+0xFF6FAAD6,
+0xFF6FAAD6,
+0xFF6FAAD6,
+0xFF6FAAD4,
+0xFF70ABD5,
+0xFF70ABD5,
+0xFF70ABD5,
+0xFF70ABD5,
+0xFF71ACD6,
+0xFF71ACD6,
+0xFF70ABD5,
+0xFF70ABD5,
+0xFF71ACD6,
+0xFF72ABD6,
+0xFF71ACD6,
+0xFF6EADD6,
+0xFF6EADD6,
+0xFF6FACD8,
+0xFF71ACD8,
+0xFF74AAD8,
+0xFF74AAD6,
+0xFF74ADD8,
+0xFF71AEDA,
+0xFF6FACD9,
+0xFF71AAD5,
+0xFF82B0D4,
+0xFF7B9AB6,
+0xFF97A8B2,
+0xFF908F8D,
+0xFF6F5B50,
+0xFFA88D7C,
+0xFFFAE4CF,
+0xFFEFD6C0,
+0xFFB1957F,
+0xFFF3D3BE,
+0xFFD6B5A2,
+0xFFAE9181,
+0xFF654F41,
+0xFF3E2D23,
+0xFF291C14,
+0xFF33241F,
+0xFF271410,
+0xFF4A3733,
+0xFF45322C,
+0xFF2A201F,
+0xFF0F1521,
+0xFF768AA2,
+0xFF87A8C7,
+0xFF7FACD3,
+0xFF74AAD6,
+0xFF77B2DE,
+0xFF72ADD7,
+0xFF75AFD7,
+0xFF75ACD3,
+0xFF75ACD5,
+0xFF73AEDA,
+0xFF71AEDA,
+0xFF71B0DB,
+0xFF72B0D9,
+0xFF77AED5,
+0xFF77AFD2,
+0xFF70ABCB,
+0xFF7BB7DB,
+0xFF77B2DE,
+0xFF78ACD4,
+0xFF85A7C2,
+0xFFC0D6E4,
+0xFFE1EFF2,
+0xFFDFE5E1,
+0xFFD8DACF,
+0xFF6F6C5D,
+0xFF1E1408,
+0xFF2D2825,
+0xFF242D3E,
+0xFF91ACC9,
+0xFF8EBDDB,
+0xFF76AED1,
+0xFF76B0D6,
+0xFF75B1D6,
+0xFF75B0D8,
+0xFF75B1D6,
+0xFF75B1D6,
+0xFF75B1D6,
+0xFF75B1D6,
+0xFF75B1D6,
+0xFF76B0D6,
+0xFF76B0D6,
+0xFF76B0D6,
+0xFF76B0D6,
+0xFF76B0D6,
+0xFF76B0D6,
+0xFF77B1D7,
+0xFF77B1D7,
+0xFF75B1D6,
+0xFF75B1D6,
+0xFF75B1D6,
+0xFF76B2D7,
+0xFF76B2D7,
+0xFF76B2D7,
+0xFF76B2D7,
+0xFF76B2D7,
+0xFF76B2D7,
+0xFF76B2D7,
+0xFF76B2D7,
+0xFF76B2D7,
+0xFF76B2D7,
+0xFF76B2D7,
+0xFF76B2D7,
+0xFF76B2D7,
+0xFF76B2D7,
+0xFF76B2D7,
+0xFF76B2D7,
+0xFF76B2D7,
+0xFF76B2D7,
+0xFF76B2D7,
+0xFF76B2D7,
+0xFF76B2D7,
+0xFF77B3D8,
+0xFF77B3D8,
+0xFF77B3D8,
+0xFF77B3D8,
+0xFF78B2D8,
+0xFF78B2D8,
+0xFF78B2D8,
+0xFF78B2D8,
+0xFF7BB0D8,
+0xFF7BB1D7,
+0xFF7BB1D7,
+0xFF78B2D7,
+0xFF74B4D8,
+0xFF73B4DA,
+0xFF75B3DA,
+0xFF77B2DC,
+0xFF76B1D9,
+0xFF7AB5DD,
+0xFF73B2D5,
+0xFF7FB0D0,
+0xFF7B89A4,
+0xFF5D6B88,
+0xFF8BB5DB,
+0xFF79B0D9,
+0xFF7CB1D9,
+0xFF7AB1D8,
+0xFF78B6DF,
+0xFF73B1D8,
+0xFF73ADD2,
+0xFF78ABC8,
+0xFFA9CCE0,
+0xFFE1F7FF,
+0xFFE5EEF5,
+0xFFEAEFF3,
+0xFFF3FAFF,
+0xFFE4F5FF,
+0xFFA8C4D9,
+0xFF86B0C9,
+0xFF77ACCB,
+0xFF80B3D2,
+0xFF81A7BC,
+0xFFC9E8FA,
+0xFFEAFFFF,
+0xFF7597B2,
+0xFF81AFD1,
+0xFF7EB4D8,
+0xFF7AAFCF,
+0xFF84B9D9,
+0xFF7BB1D5,
+0xFF78B2D7,
+0xFF75B3DA,
+0xFF74B4DA,
+0xFF76B4D9,
+0xFF78B4D8,
+0xFF7CB2D8,
+0xFF7CB2D8,
+0xFF7BB3D8,
+0xFF79B3D8,
+0xFF79B3D8,
+0xFF79B3D8,
+0xFF79B3D8,
+0xFF79B3D8,
+0xFF79B3D8,
+0xFF78B2D7,
+0xFF79B3D8,
+0xFF79B3D8,
+0xFF78B2D7,
+0xFF78B2D7,
+0xFF78B2D7,
+0xFF78B2D7,
+0xFF78B2D7,
+0xFF78B2D7,
+0xFF77B3D8,
+0xFF77B3D8,
+0xFF77B3D8,
+0xFF77B3D8,
+0xFF77B3D8,
+0xFF77B3D8,
+0xFF77B3D8,
+0xFF77B3D8,
+0xFF77B3D8,
+0xFF77B3D8,
+0xFF77B3D8,
+0xFF77B3D8,
+0xFF77B3D8,
+0xFF77B3D8,
+0xFF77B3D8,
+0xFF77B3D8,
+0xFF77B3D8,
+0xFF77B3D8,
+0xFF77B3D8,
+0xFF77B3D8,
+0xFF76B2D7,
+0xFF76B2D7,
+0xFF76B2D7,
+0xFF76B2D7,
+0xFF76B2D7,
+0xFF76B2D7,
+0xFF76B2D7,
+0xFF76B2D7,
+0xFF76B2D7,
+0xFF76B2D7,
+0xFF76B2D7,
+0xFF76B2D7,
+0xFF75B0D8,
+0xFF75B0D8,
+0xFF75B0D8,
+0xFF75B0D8,
+0xFF75B0D8,
+0xFF75B0D8,
+0xFF75B0D8,
+0xFF75B0D8,
+0xFF74AFD7,
+0xFF74AFD7,
+0xFF74AFD7,
+0xFF74AFD7,
+0xFF73AED6,
+0xFF73AED6,
+0xFF72ADD5,
+0xFF72ADD5,
+0xFF72ADD5,
+0xFF70AED5,
+0xFF72ADD5,
+0xFF70AED5,
+0xFF70AED7,
+0xFF6FADD6,
+0xFF6FADD6,
+0xFF6EACD5,
+0xFF6FADD6,
+0xFF6EACD5,
+0xFF6DAAD6,
+0xFF6BAAD5,
+0xFF6AA9D4,
+0xFF6AA9D4,
+0xFF6AA9D4,
+0xFF6AA9D4,
+0xFF6AA9D4,
+0xFF6AA9D4,
+0xFF69A8D4,
+0xFF69A8D4,
+0xFF69A8D4,
+0xFF68A7D3,
+0xFF68A7D3,
+0xFF68A7D3,
+0xFF67A6D2,
+0xFF67A6D2,
+0xFF67A5D4,
+0xFF66A4D3,
+0xFF66A4D3,
+0xFF65A3D2,
+0xFF65A3D2,
+0xFF64A2D1,
+0xFF5B9ACD,
+0xFF5B9ACD,
+0xFF5C9BCE,
+0xFF5D9CCF,
+0xFF5D9CCF,
+0xFF5D9CCF,
+0xFF5F9DCE,
+0xFF5F9DCE,
+0xFF609ECF,
+0xFF609ECF,
+0xFF619FD0,
+0xFF619FD0,
+0xFF619FD0,
+0xFF62A0D1,
+0xFF63A1D2,
+0xFF63A1D2,
+0xFF64A1D0,
+0xFF65A2D1,
+0xFF66A3D2,
+0xFF66A3D2,
+0xFF66A3D2,
+0xFF67A4D3,
+0xFF67A4D1,
+0xFF67A4D1,
+0xFF69A6D3,
+0xFF69A6D3,
+0xFF69A6D3,
+0xFF69A6D3,
+0xFF69A6D3,
+0xFF69A6D3,
+0xFF69A6D3,
+0xFF69A6D3,
+0xFF69A6D3,
+0xFF6AA7D4,
+0xFF6AA7D4,
+0xFF6AA7D4,
+0xFF6AA7D3,
+0xFF6AA7D3,
+0xFF6BA8D4,
+0xFF6BA8D4,
+0xFF6BA8D4,
+0xFF6CA9D5,
+0xFF6CA9D5,
+0xFF6CA9D5,
+0xFF6EA9D5,
+0xFF6FAAD6,
+0xFF6FAAD4,
+0xFF6FAAD4,
+0xFF70ABD7,
+0xFF70ABD7,
+0xFF70ABD7,
+0xFF70ABD7,
+0xFF70ABD7,
+0xFF70ABD7,
+0xFF71ACD6,
+0xFF71ACD6,
+0xFF71ACD6,
+0xFF71ACD6,
+0xFF71ACD6,
+0xFF72ADD7,
+0xFF72ADD7,
+0xFF71ACD6,
+0xFF71ACD6,
+0xFF73ACD7,
+0xFF74AAD8,
+0xFF72ABD8,
+0xFF6FADD6,
+0xFF6EADD6,
+0xFF6EADD8,
+0xFF71ACD6,
+0xFF75ABD7,
+0xFF75ABD7,
+0xFF73ACD7,
+0xFF72ADD7,
+0xFF73B0DC,
+0xFF74ABD2,
+0xFF84ABCC,
+0xFF7A8FA4,
+0xFF8D8C91,
+0xFF796860,
+0xFF927565,
+0xFFCAAB96,
+0xFFF6E0C9,
+0xFFE6D2BA,
+0xFFCBB19A,
+0xFFC4A48F,
+0xFFCAA794,
+0xFFAD8E7C,
+0xFF4E3B2C,
+0xFF3E3226,
+0xFF281F18,
+0xFF281D1B,
+0xFF352323,
+0xFF2A1615,
+0xFF332019,
+0xFF362923,
+0xFF363137,
+0xFF27303F,
+0xFF92ACC7,
+0xFF7CA4C7,
+0xFF7BAFD7,
+0xFF71AAD5,
+0xFF74AED6,
+0xFF79B0D7,
+0xFF79AFD5,
+0xFF77AED5,
+0xFF74AFD9,
+0xFF72AFDB,
+0xFF72B1DC,
+0xFF73B1DA,
+0xFF78AFD6,
+0xFF79AFD3,
+0xFF77AECD,
+0xFF78ADCC,
+0xFF7CAACE,
+0xFF80A4C4,
+0xFFADC2D3,
+0xFFE2F1F6,
+0xFFDDEDED,
+0xFFD7E6E1,
+0xFFD1DDD3,
+0xFFDAE2D7,
+0xFFA5A6A1,
+0xFF212830,
+0xFF8DA6C4,
+0xFF85B0D3,
+0xFF73B0CF,
+0xFF75B8D5,
+0xFF74B3D6,
+0xFF76B2D7,
+0xFF76B2D7,
+0xFF76B2D7,
+0xFF76B2D7,
+0xFF76B2D7,
+0xFF76B2D7,
+0xFF76B2D7,
+0xFF77B1D7,
+0xFF77B1D7,
+0xFF77B1D7,
+0xFF77B1D7,
+0xFF77B1D7,
+0xFF77B1D7,
+0xFF78B2D8,
+0xFF78B2D8,
+0xFF77B3D8,
+0xFF77B3D8,
+0xFF77B3D8,
+0xFF77B3D8,
+0xFF77B3D8,
+0xFF77B3D8,
+0xFF77B3D8,
+0xFF77B3D8,
+0xFF77B3D8,
+0xFF77B3D8,
+0xFF77B3D8,
+0xFF77B3D8,
+0xFF77B3D8,
+0xFF78B4D9,
+0xFF78B4D9,
+0xFF78B4D9,
+0xFF78B4D9,
+0xFF78B4D9,
+0xFF78B4D9,
+0xFF78B4D9,
+0xFF78B4D9,
+0xFF78B4D9,
+0xFF78B4D9,
+0xFF78B4D9,
+0xFF77B3D8,
+0xFF78B4D9,
+0xFF78B4D9,
+0xFF78B4D9,
+0xFF79B3D9,
+0xFF79B3D9,
+0xFF79B3D9,
+0xFF79B3D9,
+0xFF79B3D9,
+0xFF79B3D9,
+0xFF7BB2D9,
+0xFF79B3D9,
+0xFF78B4D9,
+0xFF76B5D8,
+0xFF76B5D8,
+0xFF76B5D8,
+0xFF7CB6DC,
+0xFF78B2D8,
+0xFF75B6D6,
+0xFF87BAD9,
+0xFF99ACCA,
+0xFF505F80,
+0xFF90B7DE,
+0xFF80B5DD,
+0xFF7DB3D9,
+0xFF7AB1D8,
+0xFF79B7DE,
+0xFF72B3DB,
+0xFF76B7DD,
+0xFF78B4D6,
+0xFF79ABC6,
+0xFF97BCCF,
+0xFFDFF2FF,
+0xFFE1ECF2,
+0xFFDEE3E7,
+0xFFEFF6FE,
+0xFFE9FBFF,
+0xFFC7E2F5,
+0xFF8AB2CB,
+0xFF80A5BF,
+0xFFC5E0F1,
+0xFFECFFFF,
+0xFF7C97AC,
+0xFF86A8C3,
+0xFF80ADCC,
+0xFF7EB0D1,
+0xFF81B4D3,
+0xFF77AECD,
+0xFF7BB3D6,
+0xFF78B4D8,
+0xFF75B5D9,
+0xFF75B5D9,
+0xFF76B4D9,
+0xFF79B3D8,
+0xFF7BB3D8,
+0xFF7BB3D8,
+0xFF7BB3D8,
+0xFF79B3D8,
+0xFF79B3D8,
+0xFF79B3D8,
+0xFF79B3D8,
+0xFF79B3D8,
+0xFF79B3D8,
+0xFF79B3D8,
+0xFF79B3D8,
+0xFF79B3D8,
+0xFF79B3D8,
+0xFF79B3D8,
+0xFF79B3D8,
+0xFF79B3D8,
+0xFF79B3D8,
+0xFF79B3D8,
+0xFF78B4D9,
+0xFF78B4D9,
+0xFF78B4D9,
+0xFF78B4D9,
+0xFF78B4D9,
+0xFF78B4D9,
+0xFF78B4D9,
+0xFF78B4D9,
+0xFF78B4D9,
+0xFF78B4D9,
+0xFF78B4D9,
+0xFF78B4D9,
+0xFF78B4D9,
+0xFF77B3D8,
+0xFF77B3D8,
+0xFF77B3D8,
+0xFF78B4D9,
+0xFF78B4D9,
+0xFF78B4D9,
+0xFF78B4D9,
+0xFF78B4D9,
+0xFF78B4D9,
+0xFF78B4D9,
+0xFF78B4D9,
+0xFF78B4D9,
+0xFF78B4D9,
+0xFF78B4D9,
+0xFF77B3D8,
+0xFF77B3D8,
+0xFF77B3D8,
+0xFF77B3D8,
+0xFF77B3D8,
+0xFF76B1D9,
+0xFF76B1D9,
+0xFF76B1D9,
+0xFF76B1D9,
+0xFF76B1D9,
+0xFF76B1D9,
+0xFF76B1D9,
+0xFF76B1D9,
+0xFF76B1D9,
+0xFF75B0D8,
+0xFF75B0D8,
+0xFF75B0D8,
+0xFF75B0D8,
+0xFF74AFD7,
+0xFF74AFD7,
+0xFF74AFD7,
+0xFF73AED6,
+0xFF73AED6,
+0xFF73AED6,
+0xFF72ADD5,
+0xFF72ADD7,
+0xFF70AED7,
+0xFF70AED7,
+0xFF6FADD6,
+0xFF70AED7,
+0xFF6FADD6,
+0xFF6EABD7,
+0xFF6EABD7,
+0xFF6DAAD6,
+0xFF6BAAD5,
+0xFF6CA9D5,
+0xFF6BAAD5,
+0xFF6AA9D4,
+0xFF6AA9D4,
+0xFF6AA9D5,
+0xFF69A8D4,
+0xFF69A8D4,
+0xFF69A8D4,
+0xFF69A8D4,
+0xFF69A8D4,
+0xFF68A7D3,
+0xFF68A7D3,
+0xFF68A6D5,
+0xFF67A5D4,
+0xFF67A5D4,
+0xFF66A4D3,
+0xFF66A4D3,
+0xFF65A3D2,
+0xFF5C9BCE,
+0xFF5D9CCF,
+0xFF5D9CCF,
+0xFF5E9DD0,
+0xFF5F9DCE,
+0xFF5F9DCE,
+0xFF609ECF,
+0xFF609ECF,
+0xFF609ECF,
+0xFF619FD0,
+0xFF619FD0,
+0xFF62A0D1,
+0xFF64A1D0,
+0xFF64A1D0,
+0xFF65A2D1,
+0xFF65A2D1,
+0xFF65A2D1,
+0xFF66A3D2,
+0xFF67A4D3,
+0xFF68A5D4,
+0xFF68A5D2,
+0xFF68A5D2,
+0xFF68A5D2,
+0xFF69A6D3,
+0xFF69A6D3,
+0xFF69A6D3,
+0xFF6AA7D4,
+0xFF6AA7D4,
+0xFF6AA7D3,
+0xFF6AA7D3,
+0xFF6AA7D3,
+0xFF6AA7D3,
+0xFF69A8D4,
+0xFF6AA9D5,
+0xFF6AA9D5,
+0xFF6BAAD6,
+0xFF6BA8D4,
+0xFF6CA9D5,
+0xFF6CA9D5,
+0xFF6DAAD6,
+0xFF6DAAD6,
+0xFF6DAAD6,
+0xFF6FAAD4,
+0xFF70ABD5,
+0xFF70ABD5,
+0xFF70ABD5,
+0xFF70ABD5,
+0xFF71ACD6,
+0xFF71ACD8,
+0xFF71ACD8,
+0xFF71ACD8,
+0xFF71ACD8,
+0xFF71ACD8,
+0xFF71ACD8,
+0xFF71ACD6,
+0xFF72ADD7,
+0xFF72ADD7,
+0xFF72ADD7,
+0xFF72ADD5,
+0xFF73AED6,
+0xFF73AED6,
+0xFF72ADD5,
+0xFF72ADD5,
+0xFF73ACD7,
+0xFF77ABDA,
+0xFF77ABDA,
+0xFF70AED7,
+0xFF6FAFD5,
+0xFF6FAED7,
+0xFF71AFD8,
+0xFF76ACD8,
+0xFF76ADD6,
+0xFF73ADD5,
+0xFF75B0DA,
+0xFF72B0D9,
+0xFF77ABD2,
+0xFF8BADC9,
+0xFF657181,
+0xFF564845,
+0xFF6B4E3E,
+0xFFC3A188,
+0xFFB99A7E,
+0xFFB79F83,
+0xFFEBD6BB,
+0xFF9D8169,
+0xFF87634D,
+0xFFA57B65,
+0xFF9F7A67,
+0xFF422B19,
+0xFF443727,
+0xFF443B34,
+0xFF291E1C,
+0xFF342222,
+0xFF331E1B,
+0xFF28160C,
+0xFF28170F,
+0xFF271B1B,
+0xFF56545F,
+0xFF99ABC1,
+0xFF91B4D2,
+0xFF82B3DB,
+0xFF7AB4DC,
+0xFF78B2D8,
+0xFF74ACD1,
+0xFF7CB2D6,
+0xFF7BB1D7,
+0xFF77B1D9,
+0xFF74B1DD,
+0xFF73B2DD,
+0xFF74B1DD,
+0xFF76B0D8,
+0xFF7AAED3,
+0xFF7EAFCD,
+0xFF81A6C0,
+0xFF96ACC4,
+0xFFC5D0E2,
+0xFFE6EDF3,
+0xFFE3ECE9,
+0xFFDFEFEC,
+0xFFC7D8D2,
+0xFFD0DAD2,
+0xFFB7BDB9,
+0xFFA7AFB2,
+0xFF9BAEBF,
+0xFF8DB5D9,
+0xFF7CB3DC,
+0xFF6FB1D1,
+0xFF6FB4D1,
+0xFF75B4D7,
+0xFF77B3D7,
+0xFF77B3D8,
+0xFF77B3D8,
+0xFF77B3D8,
+0xFF77B3D8,
+0xFF77B3D8,
+0xFF78B4D9,
+0xFF79B3D9,
+0xFF78B2D8,
+0xFF78B2D8,
+0xFF78B2D8,
+0xFF78B2D8,
+0xFF78B2D8,
+0xFF79B3D9,
+0xFF79B3D9,
+0xFF78B4D9,
+0xFF78B4D9,
+0xFF78B4D9,
+0xFF78B4D9,
+0xFF78B4D9,
+0xFF78B4D9,
+0xFF78B4D9,
+0xFF78B4D9,
+0xFF78B4D9,
+0xFF78B4D9,
+0xFF78B4D9,
+0xFF79B5DA,
+0xFF79B5DA,
+0xFF79B5DA,
+0xFF79B5DA,
+0xFF79B5DA,
+0xFF78B4D8,
+0xFF78B4D8,
+0xFF79B5D9,
+0xFF79B5D9,
+0xFF79B5D9,
+0xFF79B5D9,
+0xFF79B5D9,
+0xFF79B5D9,
+0xFF78B4D8,
+0xFF78B4D8,
+0xFF78B4D8,
+0xFF78B4D8,
+0xFF79B5D9,
+0xFF79B5D9,
+0xFF78B4D8,
+0xFF76B5D8,
+0xFF76B8DA,
+0xFF75B7DA,
+0xFF77B4E0,
+0xFF7CB2E0,
+0xFF7EB1DC,
+0xFF7DB3D7,
+0xFF77B7D2,
+0xFF77B7D2,
+0xFF7BB0D8,
+0xFF7CB1DB,
+0xFF74B3D6,
+0xFF7AB2D3,
+0xFF93B3D9,
+0xFF587295,
+0xFF88ACCC,
+0xFF83B0D1,
+0xFF7DB1D6,
+0xFF79B3D9,
+0xFF76B2D6,
+0xFF78B7D8,
+0xFF76B5D6,
+0xFF78B7D6,
+0xFF7BB4D1,
+0xFF7FB1CC,
+0xFF85ADC6,
+0xFFC3DFF4,
+0xFFE0F3FF,
+0xFFD0DEEB,
+0xFFE8F4FF,
+0xFFEEFCFF,
+0xFFE2F2FF,
+0xFFDAECF8,
+0xFFEEFEFF,
+0xFF8A9DAC,
+0xFF7D98AB,
+0xFF95B5CA,
+0xFFADD0E6,
+0xFF8CB4CE,
+0xFF80B1D1,
+0xFF80B8DB,
+0xFF77B6D9,
+0xFF76B6D9,
+0xFF77B6D9,
+0xFF79B5D9,
+0xFF7AB4D9,
+0xFF7AB4DA,
+0xFF7AB4DA,
+0xFF7AB4DA,
+0xFF7AB4D9,
+0xFF7AB4D9,
+0xFF7AB4D9,
+0xFF7AB4D9,
+0xFF7AB4D9,
+0xFF7AB4D9,
+0xFF7AB4D9,
+0xFF7AB4D9,
+0xFF7AB4D9,
+0xFF7AB4D9,
+0xFF7AB4D9,
+0xFF7AB4D9,
+0xFF7AB4D9,
+0xFF7AB4D9,
+0xFF7AB4D9,
+0xFF7AB4D9,
+0xFF79B5D9,
+0xFF79B5D9,
+0xFF79B5D9,
+0xFF79B5D9,
+0xFF79B5D9,
+0xFF79B5D9,
+0xFF79B5D9,
+0xFF79B5D9,
+0xFF78B4D8,
+0xFF78B4D8,
+0xFF78B4D8,
+0xFF78B4D8,
+0xFF78B4D8,
+0xFF78B4D8,
+0xFF78B4D8,
+0xFF78B4D8,
+0xFF78B4D8,
+0xFF78B4D8,
+0xFF78B4D8,
+0xFF78B4D8,
+0xFF78B4D8,
+0xFF78B4D8,
+0xFF78B4D8,
+0xFF78B4D8,
+0xFF79B5D9,
+0xFF79B5D9,
+0xFF79B5D9,
+0xFF79B5D9,
+0xFF79B5D9,
+0xFF78B4D8,
+0xFF78B4D8,
+0xFF78B4D8,
+0xFF78B4D9,
+0xFF77B3D8,
+0xFF77B3D8,
+0xFF77B3D8,
+0xFF77B3D8,
+0xFF77B3D8,
+0xFF78B2D8,
+0xFF78B2D8,
+0xFF78B2DA,
+0xFF78B2DA,
+0xFF78B2DA,
+0xFF77B1D9,
+0xFF77B1D9,
+0xFF76B0D8,
+0xFF76B0D8,
+0xFF76B0D8,
+0xFF75AFD7,
+0xFF75AFD7,
+0xFF75AFD7,
+0xFF74AED6,
+0xFF74AED6,
+0xFF72ADD5,
+0xFF72ADD7,
+0xFF72ADD7,
+0xFF72ADD7,
+0xFF72ADD7,
+0xFF72ADD9,
+0xFF71ACD8,
+0xFF71ACD8,
+0xFF6EABD7,
+0xFF70ABD7,
+0xFF6EABD7,
+0xFF6BAAD5,
+0xFF6BAAD5,
+0xFF6BAAD6,
+0xFF6AA9D5,
+0xFF6AA9D5,
+0xFF69A8D4,
+0xFF69A8D4,
+0xFF69A8D4,
+0xFF69A8D4,
+0xFF69A8D4,
+0xFF69A8D4,
+0xFF68A7D3,
+0xFF68A7D3,
+0xFF67A6D2,
+0xFF67A6D2,
+0xFF67A6D2,
+0xFF5D9CCF,
+0xFF5E9DD0,
+0xFF5E9DD0,
+0xFF5E9DD0,
+0xFF5F9DCE,
+0xFF609ECF,
+0xFF619FD0,
+0xFF619FD0,
+0xFF619FD0,
+0xFF619FD0,
+0xFF62A0D1,
+0xFF63A1D0,
+0xFF65A2D1,
+0xFF66A3D2,
+0xFF66A3D2,
+0xFF66A3D2,
+0xFF66A3D2,
+0xFF67A4D3,
+0xFF68A5D4,
+0xFF69A6D5,
+0xFF69A6D3,
+0xFF69A6D3,
+0xFF69A6D3,
+0xFF6AA7D4,
+0xFF69A6D3,
+0xFF69A6D3,
+0xFF69A6D3,
+0xFF6AA7D4,
+0xFF6AA7D3,
+0xFF6BA8D4,
+0xFF6BA8D4,
+0xFF6BA8D4,
+0xFF6BA8D5,
+0xFF6CA9D6,
+0xFF6CA9D6,
+0xFF6CA9D5,
+0xFF6CA9D5,
+0xFF6DAAD6,
+0xFF6FAAD6,
+0xFF6EABD7,
+0xFF6EABD7,
+0xFF6EACD5,
+0xFF70ABD5,
+0xFF70ABD5,
+0xFF71ACD6,
+0xFF71ACD6,
+0xFF71ACD6,
+0xFF72ADD7,
+0xFF71ACD6,
+0xFF71ACD6,
+0xFF71ACD8,
+0xFF71ACD6,
+0xFF71ACD8,
+0xFF72ADD7,
+0xFF72ADD7,
+0xFF72ADD7,
+0xFF73AED8,
+0xFF72ADD7,
+0xFF72ADD5,
+0xFF73AED6,
+0xFF73AED6,
+0xFF73AED6,
+0xFF72ADD5,
+0xFF74AED6,
+0xFF78ACDB,
+0xFF78ADD9,
+0xFF74AFD7,
+0xFF72B0D7,
+0xFF72B0D9,
+0xFF74AFD9,
+0xFF77AED7,
+0xFF77AED7,
+0xFF76B0D8,
+0xFF71ACD4,
+0xFF71ACD4,
+0xFF7FB1D4,
+0xFF90B0C9,
+0xFF5B6370,
+0xFF34211B,
+0xFF62412E,
+0xFFA7856C,
+0xFF9F8064,
+0xFF573E20,
+0xFFE9D1B5,
+0xFF82664E,
+0xFF5E3C23,
+0xFF9D735B,
+0xFF8E654F,
+0xFF472C19,
+0xFF3E2C1E,
+0xFF40332A,
+0xFF554842,
+0xFF2B1814,
+0xFF311C17,
+0xFF362418,
+0xFF28170D,
+0xFF30211E,
+0xFF231D21,
+0xFF2C3343,
+0xFF455D75,
+0xFF5F88A8,
+0xFF6A9ABE,
+0xFF7FADCF,
+0xFF8BB8D9,
+0xFF86B1D3,
+0xFF83B1D3,
+0xFF7CB2D8,
+0xFF78B2D8,
+0xFF77B1D9,
+0xFF7AB0D6,
+0xFF7DAECE,
+0xFF81ADC6,
+0xFFA6CBDE,
+0xFFC5DFEE,
+0xFFE0E8F5,
+0xFFF2F3F8,
+0xFFE5E7E4,
+0xFFC9D0C9,
+0xFFA5B4B1,
+0xFFD5E5E4,
+0xFFCED8D7,
+0xFF9AA5A7,
+0xFFACBDC7,
+0xFF637F95,
+0xFF7FAFD5,
+0xFF74AFD9,
+0xFF7ABCDE,
+0xFF72B4D4,
+0xFF76B5D8,
+0xFF78B4D8,
+0xFF78B4D9,
+0xFF78B4D9,
+0xFF78B4D9,
+0xFF78B4D9,
+0xFF78B4D9,
+0xFF78B4D9,
+0xFF79B3D9,
+0xFF79B3D9,
+0xFF79B3D9,
+0xFF79B3D9,
+0xFF79B3D9,
+0xFF79B3D9,
+0xFF79B3D9,
+0xFF7AB4DA,
+0xFF78B4D9,
+0xFF78B4D9,
+0xFF78B4D9,
+0xFF78B4D9,
+0xFF78B4D9,
+0xFF78B4D9,
+0xFF79B5DA,
+0xFF79B5DA,
+0xFF78B4D9,
+0xFF79B5DA,
+0xFF79B5DA,
+0xFF79B5DA,
+0xFF79B5DA,
+0xFF79B5DA,
+0xFF79B5DA,
+0xFF79B5DA,
+0xFF78B4D8,
+0xFF78B4D8,
+0xFF79B5D9,
+0xFF79B5D9,
+0xFF79B5D9,
+0xFF79B5D9,
+0xFF79B5D9,
+0xFF79B5D9,
+0xFF78B4D8,
+0xFF78B4D8,
+0xFF7AB4D9,
+0xFF79B5D9,
+0xFF7AB4D9,
+0xFF79B5D9,
+0xFF7AB4D9,
+0xFF77B6D9,
+0xFF74B9D8,
+0xFF74B9DA,
+0xFF78B6DF,
+0xFF7CB2DE,
+0xFF80B1DA,
+0xFF80B2D5,
+0xFF7AB8D1,
+0xFF7AB7D3,
+0xFF80B1DA,
+0xFF7EB1DC,
+0xFF7AB9DC,
+0xFF77B3D5,
+0xFF82B2D6,
+0xFF89ADCF,
+0xFF5A7894,
+0xFF95B7D3,
+0xFF84B4DA,
+0xFF78B2D8,
+0xFF7BB6D8,
+0xFF7BB6D6,
+0xFF79B4D4,
+0xFF7BB6D6,
+0xFF7CB9D8,
+0xFF79B4D4,
+0xFF7CB1D0,
+0xFF83B0CD,
+0xFF9CBED9,
+0xFFBCD6ED,
+0xFFA1B6CB,
+0xFFD5E5F4,
+0xFFF0FBFF,
+0xFFEEF7FC,
+0xFFB4BECA,
+0xFF8F9FAF,
+0xFFDDF4FF,
+0xFFB8D3E6,
+0xFFB6D1E4,
+0xFFA8CBE1,
+0xFF7EACCD,
+0xFF7DB5D8,
+0xFF78B7DA,
+0xFF78B7DA,
+0xFF78B7D8,
+0xFF7AB6DA,
+0xFF7BB5DB,
+0xFF7BB5DB,
+0xFF7AB4DA,
+0xFF79B5D9,
+0xFF7BB5DA,
+0xFF7BB5DA,
+0xFF7BB5DA,
+0xFF7BB5DA,
+0xFF7BB5DA,
+0xFF7AB4D9,
+0xFF7AB4D9,
+0xFF7AB4D9,
+0xFF7AB4D9,
+0xFF7AB4D9,
+0xFF7AB4D9,
+0xFF7AB4D9,
+0xFF7AB4D9,
+0xFF7AB4D9,
+0xFF7AB4D9,
+0xFF7AB4D9,
+0xFF79B5D9,
+0xFF79B5D9,
+0xFF79B5D9,
+0xFF79B5D9,
+0xFF79B5D9,
+0xFF79B5D9,
+0xFF79B5D9,
+0xFF79B5D9,
+0xFF7AB6DA,
+0xFF7AB6DA,
+0xFF7AB6DA,
+0xFF7AB6DA,
+0xFF7AB6DA,
+0xFF7AB6DA,
+0xFF79B5D9,
+0xFF79B5D9,
+0xFF79B5D9,
+0xFF79B5D9,
+0xFF79B5D9,
+0xFF79B5D9,
+0xFF79B5D9,
+0xFF79B5D9,
+0xFF79B5D9,
+0xFF79B5D9,
+0xFF79B5D9,
+0xFF79B5D9,
+0xFF79B5D9,
+0xFF79B5D9,
+0xFF79B5D9,
+0xFF79B5D9,
+0xFF79B5D9,
+0xFF79B5D9,
+0xFF78B4D9,
+0xFF78B4D9,
+0xFF79B3D9,
+0xFF78B4D9,
+0xFF78B4D9,
+0xFF78B4D9,
+0xFF79B3D9,
+0xFF79B3D9,
+0xFF78B2D8,
+0xFF78B2D8,
+0xFF78B2DA,
+0xFF78B2D8,
+0xFF77B1D9,
+0xFF77B1D9,
+0xFF76B0D8,
+0xFF76B0D8,
+0xFF77B1D9,
+0xFF76B0D8,
+0xFF75AFD7,
+0xFF75AFD7,
+0xFF74AED6,
+0xFF74AED6,
+0xFF73AED8,
+0xFF73AED8,
+0xFF73AED8,
+0xFF73AED8,
+0xFF73AEDA,
+0xFF72ADD9,
+0xFF72ADD9,
+0xFF71ACD8,
+0xFF71ACD8,
+0xFF6EABD7,
+0xFF6DAAD6,
+0xFF6CABD6,
+0xFF6BAAD6,
+0xFF6BAAD6,
+0xFF6AA9D5,
+0xFF6AA9D5,
+0xFF69A8D4,
+0xFF69A8D4,
+0xFF6AA9D5,
+0xFF69A8D4,
+0xFF69A8D4,
+0xFF69A8D4,
+0xFF69A8D4,
+0xFF68A7D3,
+0xFF68A7D3,
+0xFF67A6D2,
+0xFF5E9CCD,
+0xFF5E9CCD,
+0xFF5F9DCE,
+0xFF609ECF,
+0xFF619DCF,
+0xFF619DCF,
+0xFF629FCE,
+0xFF629FCE,
+0xFF64A1D0,
+0xFF65A2D1,
+0xFF65A2D1,
+0xFF66A3D2,
+0xFF68A2D2,
+0xFF69A3D1,
+0xFF69A3D1,
+0xFF6AA4D2,
+0xFF68A5D2,
+0xFF68A5D2,
+0xFF69A6D3,
+0xFF69A6D3,
+0xFF69A6D3,
+0xFF69A6D3,
+0xFF6AA7D3,
+0xFF6AA7D3,
+0xFF6AA7D3,
+0xFF6AA7D3,
+0xFF6AA7D3,
+0xFF6BA8D4,
+0xFF6BA8D4,
+0xFF6CA9D5,
+0xFF6CA9D5,
+0xFF6CA9D5,
+0xFF6FAAD6,
+0xFF6FAAD6,
+0xFF6FAAD6,
+0xFF70ABD5,
+0xFF70ABD5,
+0xFF70ABD5,
+0xFF71AAD5,
+0xFF71ACD6,
+0xFF71ACD6,
+0xFF71ACD6,
+0xFF71ACD6,
+0xFF71ACD4,
+0xFF71ACD4,
+0xFF71ACD4,
+0xFF71ACD4,
+0xFF71ACD4,
+0xFF73ADD5,
+0xFF73ADD5,
+0xFF73ACD7,
+0xFF74AED6,
+0xFF74ADD8,
+0xFF74AED6,
+0xFF74AED6,
+0xFF75AFD7,
+0xFF75AFD7,
+0xFF75AFD7,
+0xFF75AFD7,
+0xFF75AFD7,
+0xFF75AFD7,
+0xFF75AFD7,
+0xFF75AFD7,
+0xFF75AFD7,
+0xFF75AFD7,
+0xFF75AFD7,
+0xFF75AFD5,
+0xFF76B0D8,
+0xFF75B0DA,
+0xFF76AFDA,
+0xFF76B0D8,
+0xFF76B0D8,
+0xFF77B3D8,
+0xFF74B0D5,
+0xFF75B1D6,
+0xFF7FB1D2,
+0xFF89A9C0,
+0xFF3B454F,
+0xFF2F1D19,
+0xFF503325,
+0xFF7E6350,
+0xFF6D513B,
+0xFF4B2B12,
+0xFFC2A48A,
+0xFF786048,
+0xFF3F250E,
+0xFF967258,
+0xFF79533C,
+0xFF513122,
+0xFF472F23,
+0xFF533F34,
+0xFF4F3B32,
+0xFF513A32,
+0xFF2F1810,
+0xFF2B1B0E,
+0xFF322419,
+0xFF2E201D,
+0xFF392F30,
+0xFF5A575E,
+0xFF4C5461,
+0xFF415973,
+0xFF587593,
+0xFF516983,
+0xFF5F748F,
+0xFF778CA9,
+0xFF8CABCA,
+0xFF85B6D6,
+0xFF7AB1D0,
+0xFF7DAECE,
+0xFF86B0C8,
+0xFFACCEDA,
+0xFFD6EFF4,
+0xFFD9EAF1,
+0xFFCFDADE,
+0xFFCACFD2,
+0xFFC6CAC9,
+0xFFA1A6A0,
+0xFFB7BDB9,
+0xFFD3DFDF,
+0xFFD9E6EC,
+0xFF9BAAB1,
+0xFFADBFCB,
+0xFF9BB2C2,
+0xFF6C8FA5,
+0xFF6C9DBE,
+0xFF7FB6DD,
+0xFF78B2D8,
+0xFF79B5DA,
+0xFF7AB4D9,
+0xFF7AB4D9,
+0xFF7AB4D9,
+0xFF7AB4D9,
+0xFF7AB4D9,
+0xFF7AB4D9,
+0xFF7AB4D9,
+0xFF7AB4D9,
+0xFF7AB4D9,
+0xFF7AB4D9,
+0xFF7AB4D9,
+0xFF7AB4D9,
+0xFF7AB4D9,
+0xFF7AB4D9,
+0xFF7AB4D9,
+0xFF7AB4D9,
+0xFF7BB5DA,
+0xFF7BB5DA,
+0xFF7BB5DA,
+0xFF7BB5DA,
+0xFF7BB5DA,
+0xFF7BB5DA,
+0xFF7BB5DA,
+0xFF7BB5DA,
+0xFF7BB5DA,
+0xFF7BB5DA,
+0xFF7BB5DA,
+0xFF7BB5DA,
+0xFF7BB5DA,
+0xFF7BB5DA,
+0xFF7BB5DA,
+0xFF7BB5DA,
+0xFF7BB5DA,
+0xFF7BB5DA,
+0xFF7BB5DA,
+0xFF7BB5DA,
+0xFF7BB5DA,
+0xFF7BB5DA,
+0xFF7BB5DA,
+0xFF7BB5DA,
+0xFF7BB5DA,
+0xFF7BB5DA,
+0xFF7DB5DA,
+0xFF7BB5DA,
+0xFF7DB5DA,
+0xFF7BB5DA,
+0xFF7DB5DA,
+0xFF7AB6DA,
+0xFF78B7D8,
+0xFF78B7D8,
+0xFF7BB6D8,
+0xFF7EB4D8,
+0xFF7FB4D6,
+0xFF7EB4D6,
+0xFF7BB6D6,
+0xFF7EB6D9,
+0xFF7FB0D9,
+0xFF80B3DE,
+0xFF76B5D8,
+0xFF76B8D8,
+0xFF79B9D4,
+0xFF8DBCD6,
+0xFF536482,
+0xFFA2B1D2,
+0xFF87B1D7,
+0xFF7DB5DA,
+0xFF7EB8DD,
+0xFF7CB4D9,
+0xFF7FB5D7,
+0xFF7EB4D6,
+0xFF7AB5D7,
+0xFF7AB6D8,
+0xFF7CB9D8,
+0xFF7DB5D6,
+0xFF7FB1D6,
+0xFF82AED5,
+0xFF88B2DA,
+0xFF94B6D2,
+0xFFA6BAC3,
+0xFFACBABD,
+0xFF4E5A66,
+0xFF303D4E,
+0xFF738297,
+0xFFC7D7EE,
+0xFFCFE4F9,
+0xFFBCDAF2,
+0xFF87B5D6,
+0xFF81B7DB,
+0xFF7FB5D7,
+0xFF7EB6D7,
+0xFF7BB7DC,
+0xFF7BB6DE,
+0xFF7BB7DC,
+0xFF7CB6DB,
+0xFF7DB8D8,
+0xFF7DB8D8,
+0xFF7BB6D8,
+0xFF7BB5DA,
+0xFF7BB5DA,
+0xFF7BB5DA,
+0xFF7BB5DA,
+0xFF7BB5DA,
+0xFF7BB5DA,
+0xFF7BB5DA,
+0xFF7BB5DA,
+0xFF7BB5DA,
+0xFF7BB5DA,
+0xFF7BB5DA,
+0xFF7BB5DA,
+0xFF7BB5DA,
+0xFF7BB5DA,
+0xFF7BB5DA,
+0xFF7BB5DA,
+0xFF7BB5DA,
+0xFF7BB5DA,
+0xFF7BB5DA,
+0xFF7BB5DA,
+0xFF7BB5DA,
+0xFF7BB5DA,
+0xFF7BB5DA,
+0xFF7BB5DA,
+0xFF7BB5DA,
+0xFF7BB5DA,
+0xFF7BB5DA,
+0xFF7BB5DA,
+0xFF7BB5DA,
+0xFF7BB5DA,
+0xFF7BB5DA,
+0xFF7BB5DA,
+0xFF7BB5DA,
+0xFF7BB5DA,
+0xFF7BB5DA,
+0xFF7AB4D9,
+0xFF7AB4D9,
+0xFF7AB4D9,
+0xFF7AB4D9,
+0xFF7BB5DA,
+0xFF7BB5DA,
+0xFF7BB5DA,
+0xFF7BB5DA,
+0xFF7BB5DA,
+0xFF7BB5DA,
+0xFF7BB5DA,
+0xFF7BB5DA,
+0xFF7AB4D9,
+0xFF7BB5DA,
+0xFF7DB5DA,
+0xFF7BB5DA,
+0xFF7BB5DA,
+0xFF7AB4D9,
+0xFF7AB4D9,
+0xFF79B3D8,
+0xFF78B4D8,
+0xFF78B4D8,
+0xFF79B3D9,
+0xFF79B3D8,
+0xFF79B3D9,
+0xFF78B2D8,
+0xFF78B2D8,
+0xFF77B1D7,
+0xFF76B2D7,
+0xFF76B2D7,
+0xFF76B2D7,
+0xFF75B1D6,
+0xFF75B1D6,
+0xFF74B0D5,
+0xFF74AFD7,
+0xFF74AFD7,
+0xFF74AFD7,
+0xFF74AFD7,
+0xFF73AED8,
+0xFF73AED8,
+0xFF72ADD7,
+0xFF72ADD7,
+0xFF6FADD6,
+0xFF6EACD5,
+0xFF6FADD6,
+0xFF6EACD5,
+0xFF6DAAD6,
+0xFF6CA9D5,
+0xFF6CA9D5,
+0xFF6CA9D5,
+0xFF6CA9D5,
+0xFF6BA8D4,
+0xFF6BA8D5,
+0xFF6BA8D5,
+0xFF6AA9D5,
+0xFF6AA9D5,
+0xFF6AA9D5,
+0xFF6AA9D5,
+0xFF69A8D4,
+0xFF68A7D3,
+0xFF5F9DCE,
+0xFF5F9DCE,
+0xFF609ECF,
+0xFF619FD0,
+0xFF629ED0,
+0xFF629ED0,
+0xFF63A0CF,
+0xFF63A0CF,
+0xFF65A2D1,
+0xFF65A2D1,
+0xFF66A3D2,
+0xFF67A4D3,
+0xFF69A3D1,
+0xFF69A3D1,
+0xFF6AA4D2,
+0xFF6AA4D2,
+0xFF68A5D2,
+0xFF69A6D3,
+0xFF69A6D3,
+0xFF6AA7D4,
+0xFF6AA7D4,
+0xFF6AA7D4,
+0xFF6AA7D3,
+0xFF6BA8D4,
+0xFF6BA8D4,
+0xFF6BA8D4,
+0xFF6BA8D4,
+0xFF6BA8D4,
+0xFF6CA9D5,
+0xFF6CA9D5,
+0xFF6DAAD6,
+0xFF6DAAD6,
+0xFF71AAD7,
+0xFF71AAD7,
+0xFF71AAD5,
+0xFF71AAD5,
+0xFF72ABD6,
+0xFF72ABD6,
+0xFF72ABD6,
+0xFF72ABD6,
+0xFF72ADD7,
+0xFF72ADD7,
+0xFF72ADD5,
+0xFF73AED6,
+0xFF73AED6,
+0xFF73AED6,
+0xFF73AED6,
+0xFF73AED6,
+0xFF74AED6,
+0xFF74AED6,
+0xFF74AED6,
+0xFF75AFD7,
+0xFF75AFD7,
+0xFF75AFD7,
+0xFF75AFD7,
+0xFF75AFD7,
+0xFF75AFD7,
+0xFF75AFD7,
+0xFF75AFD7,
+0xFF76B0D8,
+0xFF76B0D8,
+0xFF76B0D8,
+0xFF76B0D8,
+0xFF76B0D8,
+0xFF75B1D6,
+0xFF75B1D6,
+0xFF78AFD6,
+0xFF78AFD6,
+0xFF77B1D9,
+0xFF77B1D9,
+0xFF76B0D8,
+0xFF76B0D6,
+0xFF74B0D4,
+0xFF76B2D6,
+0xFF78B2D7,
+0xFF7EAFCF,
+0xFF92B2C9,
+0xFF3D4751,
+0xFF322320,
+0xFF5B4035,
+0xFF584131,
+0xFF5B402D,
+0xFF6A482F,
+0xFF9F7D64,
+0xFF6A543D,
+0xFF331D06,
+0xFF88664D,
+0xFF67432D,
+0xFF553528,
+0xFF402419,
+0xFF624A3E,
+0xFF553F34,
+0xFF786056,
+0xFF432D22,
+0xFF261609,
+0xFF2C1E13,
+0xFF382720,
+0xFF43312D,
+0xFF574747,
+0xFFAAA5AC,
+0xFFA2B4C8,
+0xFF56718C,
+0xFF8195AE,
+0xFF7C8DA7,
+0xFF627593,
+0xFF486380,
+0xFF85ADC6,
+0xFF85AFC7,
+0xFFA0C4DA,
+0xFFBAD7E7,
+0xFFDDF2F5,
+0xFFD6E5E2,
+0xFFC3CFCD,
+0xFFD4DFDB,
+0xFFA4ADA8,
+0xFF69726D,
+0xFFEEF7F2,
+0xFFE2EBE8,
+0xFFC8D2D4,
+0xFFC8D5DB,
+0xFF8A9CA6,
+0xFF617886,
+0xFF608194,
+0xFF78A0B9,
+0xFF7FB0CE,
+0xFF7FB5D7,
+0xFF7DB3D9,
+0xFF7EB6DB,
+0xFF7BB5DA,
+0xFF7BB5DA,
+0xFF7BB5DA,
+0xFF7BB5DA,
+0xFF7BB5DA,
+0xFF7BB5DA,
+0xFF7BB5DA,
+0xFF7BB5DA,
+0xFF7BB5DA,
+0xFF7BB5DA,
+0xFF7BB5DA,
+0xFF7BB5DA,
+0xFF7BB5DA,
+0xFF7BB5DA,
+0xFF7BB5DA,
+0xFF7BB5DA,
+0xFF7BB5DA,
+0xFF7BB5DA,
+0xFF7BB5DA,
+0xFF7BB5DA,
+0xFF7BB5DA,
+0xFF7BB5DA,
+0xFF7BB5DA,
+0xFF7BB5DA,
+0xFF7BB5DA,
+0xFF7BB5DA,
+0xFF7BB5DA,
+0xFF7BB5DA,
+0xFF7BB5DA,
+0xFF7BB5DA,
+0xFF7BB5DA,
+0xFF7BB5DA,
+0xFF7BB5DA,
+0xFF7BB5DA,
+0xFF7BB5DA,
+0xFF7BB5DA,
+0xFF7CB6DB,
+0xFF7CB6DB,
+0xFF7CB6DB,
+0xFF7CB6DB,
+0xFF7EB6DB,
+0xFF7EB6DB,
+0xFF7EB6DB,
+0xFF7EB6DB,
+0xFF7EB6DB,
+0xFF7EB6DB,
+0xFF7DB5DA,
+0xFF7BB5DA,
+0xFF7BB7D9,
+0xFF7CB7D9,
+0xFF7EB6D7,
+0xFF7FB6D5,
+0xFF7FB6D5,
+0xFF7EB6D7,
+0xFF7CB7D9,
+0xFF7EB6DB,
+0xFF82B3DE,
+0xFF82B6DE,
+0xFF79B7DC,
+0xFF75B7D7,
+0xFF78BBD5,
+0xFF8ABCD5,
+0xFF677091,
+0xFF5C6083,
+0xFF9BB9DD,
+0xFF82B2D6,
+0xFF7DB5DA,
+0xFF80B8DD,
+0xFF81B6D8,
+0xFF81B6D8,
+0xFF81BBE0,
+0xFF78B7DA,
+0xFF78B9D9,
+0xFF77B6D7,
+0xFF7DB7DD,
+0xFF83B8E2,
+0xFF7DB1E0,
+0xFF82ADD0,
+0xFFBCD4DE,
+0xFFEAF9FC,
+0xFF697784,
+0xFF2C394A,
+0xFF465268,
+0xFF5D6C81,
+0xFFACBED4,
+0xFFACCAE4,
+0xFF8EBCDD,
+0xFF7FB5D7,
+0xFF81B6D6,
+0xFF80B7D6,
+0xFF7CB6DC,
+0xFF7BB6DE,
+0xFF7BB7DC,
+0xFF7DB7DC,
+0xFF7DB8D8,
+0xFF7DB8D6,
+0xFF7CB7D9,
+0xFF7CB6DB,
+0xFF7CB6DB,
+0xFF7CB6DB,
+0xFF7CB6DB,
+0xFF7CB6DB,
+0xFF7CB6DB,
+0xFF7CB6DB,
+0xFF7CB6DB,
+0xFF7CB6DB,
+0xFF7CB6DB,
+0xFF7CB6DB,
+0xFF7CB6DB,
+0xFF7CB6DB,
+0xFF7CB6DB,
+0xFF7CB6DB,
+0xFF7CB6DB,
+0xFF7CB6DB,
+0xFF7CB6DB,
+0xFF7CB6DB,
+0xFF7CB6DB,
+0xFF7CB6DB,
+0xFF7CB6DB,
+0xFF7CB6DB,
+0xFF7CB6DB,
+0xFF7CB6DB,
+0xFF7CB6DB,
+0xFF7CB6DB,
+0xFF7CB6DB,
+0xFF7CB6DB,
+0xFF7CB6DB,
+0xFF7CB6DB,
+0xFF7CB6DB,
+0xFF7CB6DB,
+0xFF7BB5DA,
+0xFF7BB5DA,
+0xFF7BB5DA,
+0xFF7BB5DA,
+0xFF7BB5DA,
+0xFF7BB5DA,
+0xFF7BB5DA,
+0xFF7BB5DA,
+0xFF7BB5DA,
+0xFF7BB5DA,
+0xFF7BB5DA,
+0xFF7BB5DA,
+0xFF7BB5DA,
+0xFF7BB5DA,
+0xFF7DB5DA,
+0xFF7DB5DA,
+0xFF7DB5DA,
+0xFF7DB5DA,
+0xFF7BB5DA,
+0xFF7BB5DA,
+0xFF7AB4D9,
+0xFF7AB4D9,
+0xFF79B5D9,
+0xFF79B5D9,
+0xFF7AB4D9,
+0xFF7AB4D9,
+0xFF7AB4D9,
+0xFF79B3D8,
+0xFF78B2D8,
+0xFF78B2D8,
+0xFF77B3D7,
+0xFF77B3D7,
+0xFF77B3D8,
+0xFF76B2D7,
+0xFF76B2D7,
+0xFF75B1D6,
+0xFF75B0D8,
+0xFF75B0D8,
+0xFF74AFD7,
+0xFF74AFD7,
+0xFF74AFD9,
+0xFF73AED8,
+0xFF73AED8,
+0xFF73AED8,
+0xFF70AED7,
+0xFF70AED7,
+0xFF70AED7,
+0xFF6FADD6,
+0xFF6EABD7,
+0xFF6EABD7,
+0xFF6EABD7,
+0xFF6DAAD6,
+0xFF6DAAD6,
+0xFF6DAAD6,
+0xFF6CA9D6,
+0xFF6CA9D6,
+0xFF6AA9D5,
+0xFF6AA9D5,
+0xFF6AA9D5,
+0xFF6AA9D5,
+0xFF69A8D4,
+0xFF69A8D4,
+0xFF609ECF,
+0xFF619FD0,
+0xFF62A0D1,
+0xFF62A0D1,
+0xFF62A0CF,
+0xFF63A1D0,
+0xFF64A1D0,
+0xFF65A2D1,
+0xFF66A3D2,
+0xFF66A3D2,
+0xFF67A4D1,
+0xFF68A5D2,
+0xFF68A5D2,
+0xFF68A5D2,
+0xFF6BA5D3,
+0xFF6BA5D3,
+0xFF69A6D3,
+0xFF6AA7D4,
+0xFF6AA7D4,
+0xFF6BA8D5,
+0xFF6BA8D4,
+0xFF6BA8D4,
+0xFF6BA8D4,
+0xFF6CA9D5,
+0xFF6CA9D5,
+0xFF6CA9D5,
+0xFF6CA9D5,
+0xFF6DAAD6,
+0xFF6DABD4,
+0xFF6DABD4,
+0xFF6EACD5,
+0xFF6EACD5,
+0xFF72ABD6,
+0xFF72ABD6,
+0xFF72ABD6,
+0xFF72ABD6,
+0xFF73ACD7,
+0xFF73ACD7,
+0xFF73ACD7,
+0xFF73ACD7,
+0xFF73ADD5,
+0xFF73ADD5,
+0xFF72ADD5,
+0xFF73AED6,
+0xFF73AED6,
+0xFF74AFD7,
+0xFF74AFD7,
+0xFF74AFD7,
+0xFF76B0D8,
+0xFF76B0D8,
+0xFF76B0D8,
+0xFF76B0D8,
+0xFF76B0D8,
+0xFF76B0D8,
+0xFF76B0D8,
+0xFF76B0D8,
+0xFF76B0D8,
+0xFF76B0D8,
+0xFF76B0D8,
+0xFF76B0D8,
+0xFF76B0D8,
+0xFF76B0D8,
+0xFF77B1D9,
+0xFF77B1D9,
+0xFF76B2D7,
+0xFF76B2D7,
+0xFF7AB2D7,
+0xFF7AB1D8,
+0xFF78B2DA,
+0xFF77B1D9,
+0xFF77B1D9,
+0xFF77B1D7,
+0xFF78B4D8,
+0xFF75B1D5,
+0xFF79B3D8,
+0xFF7FB0D0,
+0xFF96B6CD,
+0xFF47515D,
+0xFF362827,
+0xFF593E33,
+0xFF2C1609,
+0xFF371D0C,
+0xFF623F29,
+0xFF7C5943,
+0xFF6B5540,
+0xFF371E0A,
+0xFF78553F,
+0xFF65402D,
+0xFF563629,
+0xFF43281F,
+0xFF644E43,
+0xFF361F17,
+0xFF482F28,
+0xFF3C231C,
+0xFF402E24,
+0xFF38261A,
+0xFF462E22,
+0xFF4C3126,
+0xFF4F322A,
+0xFF584C4E,
+0xFFA0B7C9,
+0xFF96BED8,
+0xFF708FAE,
+0xFF91B2D1,
+0xFF8FB6D3,
+0xFF88ADC7,
+0xFF536E7F,
+0xFFD0E3F1,
+0xFFDAECFA,
+0xFFC6D4DF,
+0xFFCFD8DF,
+0xFFD1DCDE,
+0xFFC9DDDC,
+0xFFBFD5D2,
+0xFF667570,
+0xFFDBE7E3,
+0xFFDAE6E6,
+0xFFD2DDDF,
+0xFFD7E3E3,
+0xFFADBDBC,
+0xFFBFD4D7,
+0xFF294751,
+0xFF9FC8DA,
+0xFF85B5CC,
+0xFF84B6D1,
+0xFF81B4D3,
+0xFF8ABFDE,
+0xFF7CB2D4,
+0xFF7DB5D8,
+0xFF7BB5DA,
+0xFF7BB5DA,
+0xFF7BB5DA,
+0xFF7BB5DA,
+0xFF7BB5DA,
+0xFF7BB5DA,
+0xFF7BB5DA,
+0xFF7CB6DB,
+0xFF7CB6DB,
+0xFF7CB6DB,
+0xFF7CB6DB,
+0xFF7CB6DB,
+0xFF7CB6DB,
+0xFF7CB6DB,
+0xFF7CB6DB,
+0xFF7CB6DB,
+0xFF7CB6DB,
+0xFF7CB6DB,
+0xFF7CB6DB,
+0xFF7CB6DB,
+0xFF7CB6DB,
+0xFF7CB6DB,
+0xFF7CB6DB,
+0xFF7CB6DB,
+0xFF7CB6DB,
+0xFF7CB6DB,
+0xFF7CB6DB,
+0xFF7CB6DB,
+0xFF7CB6DB,
+0xFF7CB6DB,
+0xFF7CB6DB,
+0xFF7CB7D9,
+0xFF7CB7D9,
+0xFF7CB7D9,
+0xFF7CB7D9,
+0xFF7DB8DA,
+0xFF7DB8DA,
+0xFF7DB8DA,
+0xFF7DB8DA,
+0xFF7FB7DA,
+0xFF7FB7DA,
+0xFF7FB7DA,
+0xFF7FB7DA,
+0xFF7FB7DA,
+0xFF7FB7DA,
+0xFF7EB6D9,
+0xFF7EB6D9,
+0xFF7DB7DC,
+0xFF7FB7DA,
+0xFF80B6DA,
+0xFF80B6D8,
+0xFF7FB7D8,
+0xFF7FB7D8,
+0xFF7CB8DA,
+0xFF7DB7DC,
+0xFF7FB4DE,
+0xFF80B5DD,
+0xFF7DB9DE,
+0xFF78B7D8,
+0xFF7DB9D5,
+0xFF8DB9D4,
+0xFF8B91B5,
+0xFF353456,
+0xFF8E9BBB,
+0xFF97B6D5,
+0xFF7EB2D7,
+0xFF84C0E4,
+0xFF7FB6D4,
+0xFF7CB3D1,
+0xFF77B6D9,
+0xFF76B7DD,
+0xFF78BADD,
+0xFF78B9D9,
+0xFF7FB8D6,
+0xFF81B7D9,
+0xFF7EB5DE,
+0xFF82AFD0,
+0xFFC6DCE7,
+0xFFEFFAFE,
+0xFF90A0AD,
+0xFF405161,
+0xFF56687C,
+0xFF3E5368,
+0xFF566F85,
+0xFF6488A2,
+0xFF85B7D8,
+0xFF81B9DC,
+0xFF81B8D6,
+0xFF81B8D7,
+0xFF7DB7DC,
+0xFF7DB7DD,
+0xFF7DB7DD,
+0xFF7FB7DC,
+0xFF80B8D9,
+0xFF80B8D9,
+0xFF7FB7DA,
+0xFF7FB7DA,
+0xFF7FB7DA,
+0xFF7FB7DA,
+0xFF7FB7DA,
+0xFF7FB7DA,
+0xFF7FB7DA,
+0xFF7FB7DA,
+0xFF7FB7DA,
+0xFF7FB7DA,
+0xFF7FB7DA,
+0xFF7FB7DA,
+0xFF7FB7DA,
+0xFF7FB7DA,
+0xFF7FB7DA,
+0xFF7FB7DA,
+0xFF7FB7DA,
+0xFF7FB7DA,
+0xFF7FB7DA,
+0xFF7FB7DA,
+0xFF7FB7DA,
+0xFF7FB7DA,
+0xFF7FB7DA,
+0xFF7FB7DA,
+0xFF7FB7DA,
+0xFF7FB7DA,
+0xFF7FB7DA,
+0xFF7FB7DA,
+0xFF7FB7DA,
+0xFF7FB7DA,
+0xFF7FB7DA,
+0xFF7FB7DA,
+0xFF7DB8DA,
+0xFF7DB8DA,
+0xFF7DB8DA,
+0xFF7DB8DA,
+0xFF7DB8DA,
+0xFF7DB8DA,
+0xFF7CB7D9,
+0xFF7CB7D9,
+0xFF7CB7D9,
+0xFF7CB7D9,
+0xFF7CB7D9,
+0xFF7CB7D9,
+0xFF7CB7D9,
+0xFF7CB7D9,
+0xFF7CB7D9,
+0xFF7CB7D9,
+0xFF7EB6DB,
+0xFF7EB6DB,
+0xFF7EB6DB,
+0xFF7EB6DB,
+0xFF7CB6DB,
+0xFF7BB5DA,
+0xFF7BB5DA,
+0xFF7BB5DA,
+0xFF7BB5DA,
+0xFF7BB5DA,
+0xFF7BB5DA,
+0xFF7BB5DA,
+0xFF7AB4D9,
+0xFF7AB4D9,
+0xFF7AB4D9,
+0xFF79B3D8,
+0xFF78B4D8,
+0xFF78B4D8,
+0xFF78B4D8,
+0xFF78B4D8,
+0xFF77B3D8,
+0xFF77B3D8,
+0xFF76B2D7,
+0xFF76B2D7,
+0xFF75B0D8,
+0xFF75B0D8,
+0xFF74AFD7,
+0xFF74AFD7,
+0xFF75B0DA,
+0xFF74AFD9,
+0xFF74AFD9,
+0xFF73AED8,
+0xFF73AED8,
+0xFF73AED8,
+0xFF70AED7,
+0xFF6FADD6,
+0xFF6FADD6,
+0xFF6FADD6,
+0xFF6EABD7,
+0xFF6EABD7,
+0xFF6DAAD6,
+0xFF6DAAD6,
+0xFF6BAAD6,
+0xFF6BAAD6,
+0xFF6BAAD6,
+0xFF6BAAD6,
+0xFF6AA9D5,
+0xFF6AA9D5,
+0xFF619FD0,
+0xFF62A0D1,
+0xFF63A1D2,
+0xFF63A1D2,
+0xFF63A1D0,
+0xFF64A2D1,
+0xFF66A3D2,
+0xFF66A3D2,
+0xFF66A3D2,
+0xFF67A4D3,
+0xFF68A5D2,
+0xFF68A5D2,
+0xFF68A5D2,
+0xFF69A6D3,
+0xFF6BA5D3,
+0xFF6CA6D4,
+0xFF6AA7D4,
+0xFF6AA7D4,
+0xFF6BA8D5,
+0xFF6BA8D5,
+0xFF6BA8D4,
+0xFF6CA9D5,
+0xFF6CA9D5,
+0xFF6DAAD6,
+0xFF6DAAD6,
+0xFF6DAAD6,
+0xFF6DAAD6,
+0xFF6EABD7,
+0xFF6EACD5,
+0xFF6EACD5,
+0xFF6FADD6,
+0xFF71ACD6,
+0xFF73ACD7,
+0xFF73ACD7,
+0xFF73ACD7,
+0xFF73ACD7,
+0xFF74ADD8,
+0xFF74ADD8,
+0xFF74ADD8,
+0xFF74ADD8,
+0xFF74AED6,
+0xFF74AED6,
+0xFF73AED6,
+0xFF74AFD7,
+0xFF74AFD7,
+0xFF74AFD7,
+0xFF74AFD7,
+0xFF74AFD7,
+0xFF77B1D9,
+0xFF77B1D9,
+0xFF77B1D9,
+0xFF77B1D9,
+0xFF77B1D9,
+0xFF77B1D9,
+0xFF77B1D9,
+0xFF77B1D9,
+0xFF77B1D9,
+0xFF77B1D9,
+0xFF77B1D9,
+0xFF77B1D9,
+0xFF77B1D9,
+0xFF77B1D9,
+0xFF77B1D9,
+0xFF77B1D7,
+0xFF78B2D8,
+0xFF78B2D8,
+0xFF7AB2D7,
+0xFF7BB3D8,
+0xFF79B3DB,
+0xFF78B2DA,
+0xFF78B2D8,
+0xFF78B2D8,
+0xFF79B5D9,
+0xFF77B3D7,
+0xFF78B2D7,
+0xFF7FB0D0,
+0xFF98B8D1,
+0xFF3E4A56,
+0xFF3A2C2B,
+0xFF3C241A,
+0xFF29150A,
+0xFF341D0F,
+0xFF482714,
+0xFF6B4B36,
+0xFF684E3D,
+0xFF361C0B,
+0xFF5A3723,
+0xFF603B29,
+0xFF54362B,
+0xFF51392F,
+0xFF442D25,
+0xFF2C180F,
+0xFF7E655E,
+0xFF412821,
+0xFF462F27,
+0xFF412B1E,
+0xFF503524,
+0xFF513122,
+0xFF553329,
+0xFF4C3C3C,
+0xFF8499AA,
+0xFF93B8D3,
+0xFF99B8D7,
+0xFF9FC0DF,
+0xFF87AFC8,
+0xFF9FC2D5,
+0xFFD2E3ED,
+0xFFE2E9F1,
+0xFF9CA5AC,
+0xFF8E999F,
+0xFFCFDAE0,
+0xFFC3D2D5,
+0xFF9AB0AE,
+0xFF7D9391,
+0xFF243433,
+0xFFE0EEEF,
+0xFFDBE9EC,
+0xFFD2DDDF,
+0xFFD0DCDA,
+0xFF7F8D8D,
+0xFFA8BDC0,
+0xFF203C47,
+0xFF476C7F,
+0xFFA0CAE2,
+0xFF95BFD8,
+0xFF7EACC6,
+0xFF2D5E7C,
+0xFF89C0DF,
+0xFF7EB6D9,
+0xFF7CB6DB,
+0xFF7CB6DB,
+0xFF7CB6DB,
+0xFF7CB6DB,
+0xFF7CB6DB,
+0xFF7CB6DB,
+0xFF7CB6DB,
+0xFF7CB6DB,
+0xFF7CB6DB,
+0xFF7CB6DB,
+0xFF7CB6DB,
+0xFF7CB6DB,
+0xFF7CB6DB,
+0xFF7CB6DB,
+0xFF7CB6DB,
+0xFF7DB7DC,
+0xFF7DB7DC,
+0xFF7DB7DC,
+0xFF7DB7DC,
+0xFF7DB7DC,
+0xFF7DB7DC,
+0xFF7DB7DC,
+0xFF7DB7DC,
+0xFF7DB7DC,
+0xFF7DB7DC,
+0xFF7DB7DC,
+0xFF7DB7DC,
+0xFF7DB7DC,
+0xFF7DB7DC,
+0xFF7DB7DC,
+0xFF7DB7DC,
+0xFF7DB8DA,
+0xFF7DB8DA,
+0xFF7DB8DA,
+0xFF7DB8DA,
+0xFF7DB8DA,
+0xFF7DB8DA,
+0xFF7DB8DA,
+0xFF7DB8DA,
+0xFF80B8DB,
+0xFF80B8DB,
+0xFF80B8DB,
+0xFF7FB7DA,
+0xFF7FB7DA,
+0xFF7FB7DA,
+0xFF7FB7DA,
+0xFF7FB7DA,
+0xFF7EB8DD,
+0xFF80B8DD,
+0xFF80B8DD,
+0xFF80B8DB,
+0xFF80B8D9,
+0xFF80B8D9,
+0xFF7DB9DB,
+0xFF7EB8DD,
+0xFF7FB4DC,
+0xFF7FB4DC,
+0xFF80BADF,
+0xFF7EBADC,
+0xFF7DB8D6,
+0xFF89B6D3,
+0xFFA4B4D6,
+0xFF5B5C7B,
+0xFF5D5B71,
+0xFFABB7CF,
+0xFF8BB6D6,
+0xFF7AB2D3,
+0xFF7FB5D1,
+0xFF85BDD8,
+0xFF80BADF,
+0xFF7FBBE0,
+0xFF7BB7DB,
+0xFF80BBDB,
+0xFF82B9D7,
+0xFF7FB4D3,
+0xFF80B6DC,
+0xFF86B2CF,
+0xFFD4E6F2,
+0xFFEAF3F8,
+0xFF9DAFBB,
+0xFFB0C5D6,
+0xFFCFE6F8,
+0xFFA1BAD0,
+0xFF9AB8D0,
+0xFF8DB4D1,
+0xFF84BADC,
+0xFF80BBDD,
+0xFF82B9D7,
+0xFF81B8D6,
+0xFF80B8DB,
+0xFF80B8DD,
+0xFF80B8DD,
+0xFF80B8DD,
+0xFF80B8DB,
+0xFF80B8DB,
+0xFF80B8DB,
+0xFF80B8DB,
+0xFF80B8DB,
+0xFF80B8DB,
+0xFF80B8DB,
+0xFF80B8DB,
+0xFF80B8DB,
+0xFF80B8DB,
+0xFF80B8DB,
+0xFF80B8DB,
+0xFF80B8DB,
+0xFF80B8DB,
+0xFF80B8DB,
+0xFF80B8DB,
+0xFF80B8DB,
+0xFF80B8DB,
+0xFF80B8DB,
+0xFF80B8DB,
+0xFF80B8DB,
+0xFF80B8DB,
+0xFF80B8DB,
+0xFF80B8DB,
+0xFF80B8DB,
+0xFF80B8DB,
+0xFF80B8DB,
+0xFF7FB7DA,
+0xFF7FB7DA,
+0xFF7FB7DA,
+0xFF7FB7DA,
+0xFF7FB7DA,
+0xFF7FB7DA,
+0xFF7FB7DA,
+0xFF7EB9DB,
+0xFF7EB9DB,
+0xFF7EB9DB,
+0xFF7EB9DB,
+0xFF7DB8DA,
+0xFF7DB8DA,
+0xFF7DB8DA,
+0xFF7DB8DA,
+0xFF7DB8DA,
+0xFF7DB8DA,
+0xFF7DB8DA,
+0xFF7DB8DA,
+0xFF7DB8DA,
+0xFF7DB8DA,
+0xFF7DB8DA,
+0xFF7DB8DA,
+0xFF7FB7DC,
+0xFF7FB7DC,
+0xFF7FB7DC,
+0xFF7EB6DB,
+0xFF7CB6DB,
+0xFF7CB6DB,
+0xFF7CB6DB,
+0xFF7CB6DB,
+0xFF7CB6DB,
+0xFF7CB6DB,
+0xFF7CB6DB,
+0xFF7BB5DA,
+0xFF7BB5DA,
+0xFF7BB5DA,
+0xFF7BB5DA,
+0xFF7AB4D9,
+0xFF7AB4D9,
+0xFF79B5D9,
+0xFF79B5D9,
+0xFF79B5D9,
+0xFF78B4D9,
+0xFF78B4D9,
+0xFF78B4D9,
+0xFF77B3D8,
+0xFF76B1D9,
+0xFF76B1D9,
+0xFF76B1D9,
+0xFF75B0D8,
+0xFF75B0DA,
+0xFF75B0DA,
+0xFF75B0DA,
+0xFF74AFD9,
+0xFF74AFD9,
+0xFF73AED8,
+0xFF71AFD8,
+0xFF70AED7,
+0xFF70AED7,
+0xFF6FADD6,
+0xFF6FACD8,
+0xFF6FACD8,
+0xFF6EABD7,
+0xFF6EABD7,
+0xFF6CABD7,
+0xFF6BAAD6,
+0xFF6BAAD6,
+0xFF6BAAD6,
+0xFF6BAAD6,
+0xFF6BAAD6,
+0xFF62A0CF,
+0xFF63A1D0,
+0xFF64A2D1,
+0xFF64A2D1,
+0xFF64A2D1,
+0xFF65A3D2,
+0xFF67A4D1,
+0xFF67A4D1,
+0xFF67A4D1,
+0xFF68A5D2,
+0xFF68A5D2,
+0xFF69A6D3,
+0xFF69A6D2,
+0xFF69A6D2,
+0xFF6AA7D3,
+0xFF6AA7D3,
+0xFF6AA7D3,
+0xFF6BA8D4,
+0xFF6CA9D5,
+0xFF6CA9D5,
+0xFF6CA9D5,
+0xFF6CA9D5,
+0xFF6FAAD6,
+0xFF70ABD7,
+0xFF70ABD5,
+0xFF70ABD5,
+0xFF70ABD5,
+0xFF70ABD5,
+0xFF71ACD6,
+0xFF71ACD6,
+0xFF71ACD6,
+0xFF71ACD6,
+0xFF73ACD7,
+0xFF73ACD7,
+0xFF74ADD8,
+0xFF74ADD8,
+0xFF74AED6,
+0xFF75AFD7,
+0xFF75AFD7,
+0xFF75AFD7,
+0xFF76B0D8,
+0xFF76B0D8,
+0xFF76B0D8,
+0xFF76B0D8,
+0xFF77B1D7,
+0xFF77B1D7,
+0xFF77B1D7,
+0xFF77B1D7,
+0xFF77B1D7,
+0xFF77B1D7,
+0xFF77B1D7,
+0xFF77B1D7,
+0xFF78B2D8,
+0xFF78B2D8,
+0xFF78B2D8,
+0xFF78B2D8,
+0xFF78B2D8,
+0xFF78B2D8,
+0xFF7AB1D8,
+0xFF7AB1D8,
+0xFF7AB1D8,
+0xFF7AB1D8,
+0xFF7AB1D8,
+0xFF78B2D8,
+0xFF78B2D8,
+0xFF79B3D8,
+0xFF7BB3D8,
+0xFF7BB3D8,
+0xFF79B3DB,
+0xFF7AB4DC,
+0xFF7AB4DA,
+0xFF7AB4DA,
+0xFF76B0D5,
+0xFF7DB8DA,
+0xFF79B3D8,
+0xFF7FB0D0,
+0xFF9ABAD3,
+0xFF3F4B57,
+0xFF342927,
+0xFF271106,
+0xFF251309,
+0xFF372416,
+0xFF39190A,
+0xFF593827,
+0xFF5F4536,
+0xFF3E2312,
+0xFF4E2B18,
+0xFF6B4835,
+0xFF5B3F33,
+0xFF493328,
+0xFF3B271E,
+0xFF230F08,
+0xFF553C35,
+0xFF391E17,
+0xFF371E17,
+0xFF553D31,
+0xFF553924,
+0xFF72533F,
+0xFF4E3026,
+0xFF463639,
+0xFF5F6C7D,
+0xFF4E6881,
+0xFF7285A3,
+0xFFB2C3DD,
+0xFFC3D6E5,
+0xFFE4F5FD,
+0xFFE1E6EC,
+0xFFDFE2E7,
+0xFFA3ADAE,
+0xFFB6C8C8,
+0xFF809A9B,
+0xFFA9C3C4,
+0xFF7C8E8E,
+0xFF142223,
+0xFF516067,
+0xFFE9F6FE,
+0xFFDDE6EB,
+0xFFCFD7D9,
+0xFFABB4B3,
+0xFF596466,
+0xFF71828A,
+0xFF748796,
+0xFF000C1F,
+0xFF72889F,
+0xFF587088,
+0xFF000922,
+0xFF5E8BAA,
+0xFF82B8DA,
+0xFF7FB7DA,
+0xFF7FB7DA,
+0xFF7FB7DA,
+0xFF7FB7DA,
+0xFF7FB7DA,
+0xFF7FB7DA,
+0xFF7FB7DA,
+0xFF7FB7DA,
+0xFF7FB7DA,
+0xFF7FB7DA,
+0xFF7FB7DA,
+0xFF7FB7DA,
+0xFF7FB7DA,
+0xFF7FB7DA,
+0xFF7FB7DA,
+0xFF7FB7DA,
+0xFF7FB7DA,
+0xFF7FB7DA,
+0xFF7FB7DA,
+0xFF7FB7DA,
+0xFF80B8DB,
+0xFF80B8DB,
+0xFF80B8DB,
+0xFF80B8DB,
+0xFF80B8DB,
+0xFF80B8DB,
+0xFF80B8DB,
+0xFF80B8DB,
+0xFF80B8DB,
+0xFF80B8DB,
+0xFF80B8DB,
+0xFF80B8DB,
+0xFF7EB9DB,
+0xFF7EB9DB,
+0xFF7EB9DB,
+0xFF7EB9DB,
+0xFF7EB9DB,
+0xFF7EB9DB,
+0xFF80B8DB,
+0xFF80B8DB,
+0xFF80B8DB,
+0xFF80B8DB,
+0xFF80B8DB,
+0xFF80B8DB,
+0xFF80B8DB,
+0xFF80B8DB,
+0xFF80B8DB,
+0xFF7EB8DD,
+0xFF7DB9DE,
+0xFF7DB9DE,
+0xFF7EB8DD,
+0xFF80B8DB,
+0xFF80B8D9,
+0xFF80B8D9,
+0xFF80B8DB,
+0xFF80B8DD,
+0xFF82B7DF,
+0xFF81B6DE,
+0xFF80BADF,
+0xFF80BCDE,
+0xFF7ABAD6,
+0xFF7FB6D4,
+0xFF9ABEDE,
+0xFF8F9BB5,
+0xFF695966,
+0xFF716573,
+0xFF9EB8D3,
+0xFF89B7D8,
+0xFF8AB9D7,
+0xFF84B5D5,
+0xFF88BADF,
+0xFF81B3D8,
+0xFF89B7D9,
+0xFF8AB8D9,
+0xFF88BBDA,
+0xFF8ABDDC,
+0xFF8DBEDF,
+0xFF90B5D0,
+0xFFE1EDFB,
+0xFFF1F8FF,
+0xFFA8BBC9,
+0xFFD1EBFA,
+0xFFCFEAFD,
+0xFF8AA9BE,
+0xFF92B6D0,
+0xFF8BB8D7,
+0xFF84BCDF,
+0xFF7DB9DB,
+0xFF82B9D7,
+0xFF83B8D7,
+0xFF82B8DA,
+0xFF82B8DE,
+0xFF82B8DE,
+0xFF82B8DE,
+0xFF81B9DE,
+0xFF7FBADC,
+0xFF81B9DC,
+0xFF81B9DC,
+0xFF81B9DC,
+0xFF81B9DC,
+0xFF81B9DC,
+0xFF81B9DC,
+0xFF81B9DC,
+0xFF81B9DC,
+0xFF81B9DC,
+0xFF81B9DC,
+0xFF81B9DC,
+0xFF81B9DC,
+0xFF81B9DC,
+0xFF81B9DC,
+0xFF81B9DC,
+0xFF81B9DC,
+0xFF80B8DB,
+0xFF80B8DB,
+0xFF80B8DB,
+0xFF80B8DB,
+0xFF80B8DB,
+0xFF80B8DB,
+0xFF80B8DB,
+0xFF80B8DB,
+0xFF80B8DB,
+0xFF80B8DB,
+0xFF80B8DB,
+0xFF80B8DB,
+0xFF80B8DB,
+0xFF80B8DB,
+0xFF80B8DB,
+0xFF80B8DB,
+0xFF80B8DB,
+0xFF80B8DB,
+0xFF80B8DB,
+0xFF80B8DB,
+0xFF80B8DB,
+0xFF80B8DB,
+0xFF80B8DB,
+0xFF80B8DB,
+0xFF80B8DB,
+0xFF80B8DB,
+0xFF80B8DB,
+0xFF80B8DB,
+0xFF80B8DB,
+0xFF80B8DB,
+0xFF80B8DB,
+0xFF80B8DB,
+0xFF81B7DB,
+0xFF81B7DB,
+0xFF7FB7DA,
+0xFF7FB7DA,
+0xFF7FB7DA,
+0xFF7FB7DA,
+0xFF7DB8DA,
+0xFF7DB8DA,
+0xFF7DB7DC,
+0xFF7CB6DB,
+0xFF7CB6DB,
+0xFF7CB6DB,
+0xFF7EB6DB,
+0xFF7DB5DA,
+0xFF7DB5DA,
+0xFF7BB5DA,
+0xFF7BB5DA,
+0xFF7BB5DA,
+0xFF7BB5DA,
+0xFF7BB5DA,
+0xFF7AB4D9,
+0xFF7AB4D9,
+0xFF79B3D9,
+0xFF79B3D9,
+0xFF78B4D9,
+0xFF77B3D8,
+0xFF77B2DA,
+0xFF76B1D9,
+0xFF76B1D9,
+0xFF76B1D9,
+0xFF75B0D8,
+0xFF74AFD7,
+0xFF74AFD7,
+0xFF74AFD7,
+0xFF74AFD7,
+0xFF73AED6,
+0xFF73AED8,
+0xFF72ADD7,
+0xFF70AED7,
+0xFF70AED7,
+0xFF6FACD8,
+0xFF6EABD7,
+0xFF6DAAD6,
+0xFF6DAAD6,
+0xFF6DAAD6,
+0xFF6DAAD6,
+0xFF6DAAD6,
+0xFF6CA9D5,
+0xFF63A1D0,
+0xFF64A2D1,
+0xFF64A2D1,
+0xFF65A3D2,
+0xFF65A3D2,
+0xFF66A4D3,
+0xFF68A5D2,
+0xFF68A5D2,
+0xFF68A5D2,
+0xFF68A5D2,
+0xFF69A6D3,
+0xFF6AA7D4,
+0xFF6AA7D3,
+0xFF6AA7D3,
+0xFF6AA7D3,
+0xFF6BA8D4,
+0xFF6BA8D4,
+0xFF6CA9D5,
+0xFF6CA9D5,
+0xFF6DAAD6,
+0xFF6DAAD6,
+0xFF6DAAD6,
+0xFF70ABD7,
+0xFF71ACD8,
+0xFF71ACD6,
+0xFF71ACD6,
+0xFF71ACD6,
+0xFF72ADD7,
+0xFF72ADD7,
+0xFF72ADD7,
+0xFF72ADD7,
+0xFF72ADD7,
+0xFF74ADD8,
+0xFF74ADD8,
+0xFF74ADD8,
+0xFF75AED9,
+0xFF75AFD7,
+0xFF75AFD7,
+0xFF76B0D8,
+0xFF76B0D8,
+0xFF77B1D9,
+0xFF77B1D9,
+0xFF77B1D9,
+0xFF77B1D9,
+0xFF77B1D7,
+0xFF77B1D7,
+0xFF77B1D7,
+0xFF77B1D7,
+0xFF77B1D7,
+0xFF78B2D8,
+0xFF78B2D8,
+0xFF78B2D8,
+0xFF78B2D8,
+0xFF79B3D9,
+0xFF79B3D9,
+0xFF79B3D9,
+0xFF79B3D9,
+0xFF79B3D9,
+0xFF7BB2D9,
+0xFF7BB2D9,
+0xFF7BB2D9,
+0xFF7BB2D9,
+0xFF7BB2D9,
+0xFF7BB2D9,
+0xFF79B3D8,
+0xFF79B3D8,
+0xFF7CB4D9,
+0xFF7CB4D9,
+0xFF7AB4DA,
+0xFF7BB5DB,
+0xFF7BB5DB,
+0xFF7BB5DA,
+0xFF79B4D6,
+0xFF7CB7D9,
+0xFF79B3D8,
+0xFF83B4D5,
+0xFF97B9D2,
+0xFF616F7C,
+0xFF201614,
+0xFF2D1B11,
+0xFF26150D,
+0xFF342216,
+0xFF3D2012,
+0xFF4C2C1D,
+0xFF64483A,
+0xFF412517,
+0xFF411E0B,
+0xFF6E4A3A,
+0xFF52362A,
+0xFF4B352A,
+0xFF3D2B21,
+0xFF1B0801,
+0xFF341D15,
+0xFF654A43,
+0xFF412821,
+0xFF5E4338,
+0xFF361A05,
+0xFF896E5B,
+0xFF644942,
+0xFF4C4044,
+0xFF8B97A7,
+0xFF859AAF,
+0xFF94A1B4,
+0xFFBCC5D4,
+0xFFBBC4C9,
+0xFFD1DAD9,
+0xFFCCCDD1,
+0xFFE2E6E9,
+0xFF939D9F,
+0xFF91A3A5,
+0xFF92AEAF,
+0xFF91ABAC,
+0xFF0F1D1E,
+0xFF232D2F,
+0xFFF3FFFF,
+0xFFBBC8D0,
+0xFFA8B1B6,
+0xFF9FA7AA,
+0xFF899297,
+0xFF525D63,
+0xFF3A4855,
+0xFF576776,
+0xFF1A2737,
+0xFF102133,
+0xFF000920,
+0xFF43627E,
+0xFF95C2E3,
+0xFF85BADC,
+0xFF81B7DB,
+0xFF80B8DB,
+0xFF80B8DB,
+0xFF80B8DB,
+0xFF80B8DB,
+0xFF80B8DB,
+0xFF80B8DB,
+0xFF80B8DB,
+0xFF80B8DB,
+0xFF80B8DB,
+0xFF80B8DB,
+0xFF80B8DB,
+0xFF80B8DB,
+0xFF80B8DB,
+0xFF80B8DB,
+0xFF80B8DB,
+0xFF7FB7DA,
+0xFF80B8DB,
+0xFF80B8DB,
+0xFF80B8DB,
+0xFF80B8DB,
+0xFF80B8DB,
+0xFF80B8DB,
+0xFF80B8DB,
+0xFF80B8DB,
+0xFF80B8DB,
+0xFF80B8DB,
+0xFF80B8DB,
+0xFF80B8DB,
+0xFF80B8DB,
+0xFF80B8DB,
+0xFF80B8DB,
+0xFF7EB9DB,
+0xFF7EB9DB,
+0xFF7EB9DB,
+0xFF7EB9DB,
+0xFF7FBADC,
+0xFF7FBADC,
+0xFF81B9DC,
+0xFF81B9DC,
+0xFF81B9DC,
+0xFF81B9DC,
+0xFF81B9DC,
+0xFF81B9DC,
+0xFF81B9DC,
+0xFF81B9DC,
+0xFF81B9DC,
+0xFF81B9DE,
+0xFF7FB9DF,
+0xFF7FB9DF,
+0xFF7FB9DE,
+0xFF81B9DC,
+0xFF82B8DA,
+0xFF82B8DA,
+0xFF81B9DA,
+0xFF81B9DC,
+0xFF82B8DE,
+0xFF83BBE0,
+0xFF7EB8DD,
+0xFF7FBBDD,
+0xFF7CBBDA,
+0xFF7DB9D5,
+0xFF85B6D4,
+0xFFA2B8CF,
+0xFF89747D,
+0xFF674C53,
+0xFF84899C,
+0xFFA0BAD3,
+0xFF8DB1D1,
+0xFF8CB7D9,
+0xFF8EBADF,
+0xFF93BEE1,
+0xFF96BFDF,
+0xFF93BFDC,
+0xFF92C1DF,
+0xFF94C5E5,
+0xFF97C4E5,
+0xFF9CBCD5,
+0xFFE6F0FC,
+0xFFEBF2FA,
+0xFFA2B5C3,
+0xFFD2EFFF,
+0xFFCAE7F9,
+0xFF88A8BF,
+0xFF92BBD7,
+0xFF88BADB,
+0xFF7EB8DD,
+0xFF7FBBDD,
+0xFF83BAD9,
+0xFF84B9D8,
+0xFF84B9DB,
+0xFF84B8DD,
+0xFF84B8DF,
+0xFF83B9DF,
+0xFF82BADF,
+0xFF80BADF,
+0xFF82BADD,
+0xFF82BADD,
+0xFF82BADD,
+0xFF82BADD,
+0xFF82BADD,
+0xFF82BADD,
+0xFF82BADD,
+0xFF82BADD,
+0xFF81B9DC,
+0xFF81B9DC,
+0xFF81B9DC,
+0xFF81B9DC,
+0xFF82BADD,
+0xFF82BADD,
+0xFF82BADD,
+0xFF82BADD,
+0xFF81B9DC,
+0xFF81B9DC,
+0xFF81B9DC,
+0xFF81B9DC,
+0xFF81B9DC,
+0xFF81B9DC,
+0xFF81B9DC,
+0xFF80B8DB,
+0xFF81B9DC,
+0xFF81B9DC,
+0xFF81B9DC,
+0xFF81B9DC,
+0xFF81B9DC,
+0xFF81B9DC,
+0xFF81B9DC,
+0xFF81B9DC,
+0xFF81B9DC,
+0xFF81B9DC,
+0xFF81B9DC,
+0xFF81B9DC,
+0xFF81B9DC,
+0xFF81B9DC,
+0xFF81B9DC,
+0xFF80B8DB,
+0xFF80B8DB,
+0xFF80B8DB,
+0xFF80B8DB,
+0xFF80B8DB,
+0xFF80B8DB,
+0xFF80B8DB,
+0xFF80B8DB,
+0xFF80B8DB,
+0xFF82B8DC,
+0xFF82B8DC,
+0xFF80B8DB,
+0xFF80B8DB,
+0xFF80B8DB,
+0xFF80B8DB,
+0xFF7EB9DB,
+0xFF7EB9DB,
+0xFF7DB7DC,
+0xFF7DB7DC,
+0xFF7DB7DC,
+0xFF7CB6DB,
+0xFF7EB6DB,
+0xFF7EB6DB,
+0xFF7EB6DB,
+0xFF7EB6DB,
+0xFF7CB6DB,
+0xFF7CB6DB,
+0xFF7BB5DA,
+0xFF7BB5DA,
+0xFF7BB5DA,
+0xFF7BB5DA,
+0xFF7AB4DA,
+0xFF7AB4DA,
+0xFF79B5DA,
+0xFF78B4D9,
+0xFF78B3DB,
+0xFF77B2DA,
+0xFF77B2DA,
+0xFF77B2DA,
+0xFF76B1D9,
+0xFF75B0D8,
+0xFF75B0D8,
+0xFF75B0D8,
+0xFF75B0D8,
+0xFF75B0D8,
+0xFF74AFD9,
+0xFF73AED8,
+0xFF71AFD8,
+0xFF71AFD8,
+0xFF70ADD9,
+0xFF6FACD8,
+0xFF6FACD8,
+0xFF6EABD7,
+0xFF6EABD7,
+0xFF6EABD7,
+0xFF6DAAD6,
+0xFF6DAAD6,
+0xFF64A3CF,
+0xFF65A4D0,
+0xFF65A4D0,
+0xFF66A5D1,
+0xFF66A5D1,
+0xFF67A6D2,
+0xFF68A7D3,
+0xFF68A7D3,
+0xFF69A6D2,
+0xFF69A6D2,
+0xFF6AA7D3,
+0xFF6AA7D3,
+0xFF6BA8D4,
+0xFF6BA8D4,
+0xFF6BA9D2,
+0xFF6CAAD3,
+0xFF6CAAD3,
+0xFF6DABD4,
+0xFF6DABD4,
+0xFF6EACD5,
+0xFF70ABD5,
+0xFF70ABD5,
+0xFF71ACD6,
+0xFF72ADD7,
+0xFF72ADD7,
+0xFF72ADD7,
+0xFF73ADD5,
+0xFF74AED6,
+0xFF74AED6,
+0xFF74AED6,
+0xFF74AED6,
+0xFF75AFD7,
+0xFF75AFD7,
+0xFF75AFD7,
+0xFF76B0D8,
+0xFF76B0D8,
+0xFF76B0D8,
+0xFF77B1D9,
+0xFF77B1D7,
+0xFF77B1D7,
+0xFF77B1D7,
+0xFF77B1D7,
+0xFF77B1D7,
+0xFF77B1D7,
+0xFF78B2D8,
+0xFF78B2D8,
+0xFF78B2D7,
+0xFF78B2D7,
+0xFF79B3D8,
+0xFF79B3D8,
+0xFF79B3D8,
+0xFF79B3D8,
+0xFF7CB4D9,
+0xFF7CB4D9,
+0xFF7CB4D9,
+0xFF7CB4D9,
+0xFF7CB4D9,
+0xFF7CB4D9,
+0xFF7CB4D9,
+0xFF7CB4D9,
+0xFF7CB4D9,
+0xFF7CB4D9,
+0xFF7CB4D9,
+0xFF7CB4D9,
+0xFF7BB5DA,
+0xFF7BB5DA,
+0xFF7DB5D8,
+0xFF7DB5DA,
+0xFF7BB5DB,
+0xFF7CB6DC,
+0xFF7EB5DC,
+0xFF7DB5DA,
+0xFF80B8DB,
+0xFF7CB4D7,
+0xFF7BB3D8,
+0xFF85B6D7,
+0xFF97B9D2,
+0xFF60707D,
+0xFF160E0C,
+0xFF36251D,
+0xFF1F1108,
+0xFF29180E,
+0xFF381E11,
+0xFF472A1A,
+0xFF6D5042,
+0xFF412416,
+0xFF381706,
+0xFF775645,
+0xFF45291B,
+0xFF5A4437,
+0xFF402F25,
+0xFF211006,
+0xFF341E13,
+0xFF3C241A,
+0xFF3E231C,
+0xFF60453C,
+0xFF412517,
+0xFF877062,
+0xFF796660,
+0xFF2E292D,
+0xFF6C7E8C,
+0xFF95ADB9,
+0xFFE1EBED,
+0xFFCFD5D1,
+0xFFD4DED6,
+0xFFCAD4CC,
+0xFFD1D7D5,
+0xFFDADFE2,
+0xFF6D787E,
+0xFF738289,
+0xFF37464B,
+0xFF738184,
+0xFF758082,
+0xFFC4CED0,
+0xFFBBC6CA,
+0xFFAEB9BD,
+0xFF919A9F,
+0xFFC4CFD5,
+0xFF6C7D87,
+0xFF30404D,
+0xFF23313E,
+0xFF313F4A,
+0xFF21323C,
+0xFF031A28,
+0xFF61849A,
+0xFF97C0DE,
+0xFF8CB8DB,
+0xFF80B0D4,
+0xFF82B8DC,
+0xFF81B9DC,
+0xFF81B9DC,
+0xFF81B9DC,
+0xFF81B9DC,
+0xFF81B9DC,
+0xFF81B9DC,
+0xFF81B9DC,
+0xFF81B9DC,
+0xFF81B9DC,
+0xFF81B9DC,
+0xFF81B9DC,
+0xFF81B9DC,
+0xFF81B9DC,
+0xFF81B9DC,
+0xFF81B9DC,
+0xFF80B8DB,
+0xFF80B8DB,
+0xFF81B9DC,
+0xFF81B9DC,
+0xFF81B9DC,
+0xFF81B9DC,
+0xFF81B9DC,
+0xFF81B9DC,
+0xFF81B9DC,
+0xFF81B9DC,
+0xFF81B9DC,
+0xFF81B9DC,
+0xFF81B9DC,
+0xFF81B9DC,
+0xFF81B9DC,
+0xFF81B9DC,
+0xFF81B9DC,
+0xFF81B9DC,
+0xFF81B9DC,
+0xFF81B9DC,
+0xFF82BADD,
+0xFF82BADD,
+0xFF82BADD,
+0xFF82BADD,
+0xFF82BADD,
+0xFF82BADD,
+0xFF82BADD,
+0xFF82BADD,
+0xFF82BADD,
+0xFF82BADD,
+0xFF82BADD,
+0xFF82BADF,
+0xFF83B8E0,
+0xFF83B8E0,
+0xFF83B9DF,
+0xFF83B9DD,
+0xFF83B9DB,
+0xFF82BBD9,
+0xFF80BBD9,
+0xFF80BBDB,
+0xFF7FBADA,
+0xFF81BCDE,
+0xFF7EB9DB,
+0xFF7FBADA,
+0xFF81BCDA,
+0xFF83BCD9,
+0xFF82B8D4,
+0xFFA0BCD2,
+0xFF988892,
+0xFF705053,
+0xFF60494F,
+0xFFBDB9C7,
+0xFFAABFDE,
+0xFF9CC0E4,
+0xFF9CC2E6,
+0xFF9DC4E5,
+0xFF99C2DE,
+0xFF9AC6E1,
+0xFF98C7E5,
+0xFF94C3E1,
+0xFF90BBDB,
+0xFF9EBCD6,
+0xFFEDF5FF,
+0xFFF4F8FF,
+0xFF9EB4C1,
+0xFFD0EDFD,
+0xFFD1EEFF,
+0xFF85A7C0,
+0xFF88B3D3,
+0xFF88BCE1,
+0xFF80BCE0,
+0xFF7FBBDD,
+0xFF83BAD9,
+0xFF86B9D8,
+0xFF87B9DA,
+0xFF87B9DC,
+0xFF87B9DE,
+0xFF85B9E0,
+0xFF81BBE0,
+0xFF81BBE0,
+0xFF83BBDE,
+0xFF84BADE,
+0xFF84BADE,
+0xFF84BADE,
+0xFF84BADE,
+0xFF84BADE,
+0xFF84BADE,
+0xFF84BADE,
+0xFF83B9DD,
+0xFF83B9DD,
+0xFF83B9DD,
+0xFF84BADE,
+0xFF84BADE,
+0xFF84BADE,
+0xFF84BADE,
+0xFF84BADE,
+0xFF83B9DD,
+0xFF83B9DD,
+0xFF83B9DD,
+0xFF83B9DD,
+0xFF83B9DD,
+0xFF83B9DD,
+0xFF83B9DD,
+0xFF83B9DD,
+0xFF83B9DD,
+0xFF83B9DD,
+0xFF83B9DD,
+0xFF83B9DD,
+0xFF83B9DD,
+0xFF83B9DD,
+0xFF83B9DD,
+0xFF83B9DD,
+0xFF83B9DD,
+0xFF83B9DD,
+0xFF82B8DC,
+0xFF82B8DC,
+0xFF82B8DC,
+0xFF82B8DC,
+0xFF82B8DC,
+0xFF82B8DC,
+0xFF82B8DC,
+0xFF82B8DC,
+0xFF82B8DC,
+0xFF82B8DC,
+0xFF82B8DC,
+0xFF82B8DC,
+0xFF82B8DC,
+0xFF82B8DC,
+0xFF83B9DD,
+0xFF82B8DC,
+0xFF82B8DC,
+0xFF82B8DC,
+0xFF80B8DB,
+0xFF80B8DB,
+0xFF81B9DC,
+0xFF81B9DC,
+0xFF81B9DC,
+0xFF80B8DB,
+0xFF80B8DB,
+0xFF7FB7DA,
+0xFF7FB7DA,
+0xFF7FB7DA,
+0xFF80B6DA,
+0xFF80B8DB,
+0xFF7CB7D9,
+0xFF7CB7D9,
+0xFF7CB7D9,
+0xFF7CB7D9,
+0xFF7CB6DB,
+0xFF7BB5DA,
+0xFF7BB5DA,
+0xFF7BB5DA,
+0xFF7BB5DA,
+0xFF7AB4D9,
+0xFF7AB4DA,
+0xFF7AB4DA,
+0xFF79B3D9,
+0xFF79B3D9,
+0xFF78B2D8,
+0xFF78B2D8,
+0xFF76B2D7,
+0xFF76B2D7,
+0xFF77B2DA,
+0xFF76B1D9,
+0xFF75B0D8,
+0xFF74AFD7,
+0xFF74AFD7,
+0xFF74AFD7,
+0xFF73AED8,
+0xFF73AED8,
+0xFF70AED7,
+0xFF70AED7,
+0xFF70AED7,
+0xFF6FADD6,
+0xFF6FACD8,
+0xFF6EABD7,
+0xFF64A3CF,
+0xFF65A4D0,
+0xFF66A5D1,
+0xFF67A6D2,
+0xFF67A6D2,
+0xFF68A7D3,
+0xFF68A7D3,
+0xFF69A8D3,
+0xFF69A6D2,
+0xFF6AA7D3,
+0xFF6BA8D4,
+0xFF6BA8D4,
+0xFF6BA8D4,
+0xFF6BA8D4,
+0xFF6CAAD3,
+0xFF6CAAD3,
+0xFF6DABD4,
+0xFF6DABD4,
+0xFF6EACD5,
+0xFF6FADD6,
+0xFF71ACD6,
+0xFF71ACD6,
+0xFF72ADD7,
+0xFF72ADD7,
+0xFF73AED8,
+0xFF73AED6,
+0xFF74AED6,
+0xFF75AFD7,
+0xFF75AFD7,
+0xFF75AFD7,
+0xFF75AFD7,
+0xFF75AFD7,
+0xFF76B0D8,
+0xFF76B0D8,
+0xFF76B0D8,
+0xFF77B1D9,
+0xFF77B1D9,
+0xFF77B1D7,
+0xFF78B2D8,
+0xFF78B2D8,
+0xFF78B2D8,
+0xFF78B2D8,
+0xFF78B2D8,
+0xFF79B3D9,
+0xFF79B3D9,
+0xFF7AB4DA,
+0xFF7AB4D9,
+0xFF7AB4D9,
+0xFF7AB4D9,
+0xFF7AB4D9,
+0xFF7AB4D9,
+0xFF7AB4D9,
+0xFF7CB4D9,
+0xFF7CB4D9,
+0xFF7CB4D9,
+0xFF7CB4D9,
+0xFF7DB5DA,
+0xFF7DB5DA,
+0xFF7DB5DA,
+0xFF7DB5DA,
+0xFF7DB5DA,
+0xFF7DB5DA,
+0xFF7DB5DA,
+0xFF7DB5DA,
+0xFF7EB6DB,
+0xFF7EB6DB,
+0xFF7FB5D9,
+0xFF7FB5D9,
+0xFF7EB6DB,
+0xFF7CB6DB,
+0xFF7EB6DB,
+0xFF7EB6D9,
+0xFF7DB5D8,
+0xFF80B8DB,
+0xFF7DB5DA,
+0xFF83B4D5,
+0xFF99BDD5,
+0xFF2E404E,
+0xFF1D1717,
+0xFF2D1F16,
+0xFF180B03,
+0xFF291B10,
+0xFF321B0D,
+0xFF482B1D,
+0xFF66493B,
+0xFF3C1C0F,
+0xFF371605,
+0xFF826351,
+0xFF3A200F,
+0xFF554233,
+0xFF3B2D22,
+0xFF23150A,
+0xFF432F24,
+0xFF4A3226,
+0xFF3F271D,
+0xFF553D33,
+0xFF584235,
+0xFF645246,
+0xFFA19692,
+0xFFCDCED0,
+0xFFC1D4DB,
+0xFF8DA4AA,
+0xFFAFB8B5,
+0xFFD4DAD0,
+0xFFD3DDD2,
+0xFFC8D4CA,
+0xFFC8D2D1,
+0xFFE0EBED,
+0xFF313E44,
+0xFF1A272D,
+0xFFB6BFC4,
+0xFFE9F3F5,
+0xFFDAE5E7,
+0xFFCDD9D9,
+0xFFBBC5C4,
+0xFFC9D5D5,
+0xFFD1E0E3,
+0xFFDAEBF3,
+0xFF687B89,
+0xFF253847,
+0xFF253640,
+0xFF172933,
+0xFF153039,
+0xFF678B99,
+0xFF96C4DE,
+0xFF87BAD9,
+0xFF86B7D8,
+0xFF86B6DA,
+0xFF82B8DC,
+0xFF81B9DC,
+0xFF81B9DC,
+0xFF81B9DC,
+0xFF81B9DC,
+0xFF81B9DC,
+0xFF81B9DC,
+0xFF81B9DC,
+0xFF81B9DC,
+0xFF81B9DC,
+0xFF81B9DC,
+0xFF81B9DC,
+0xFF81B9DC,
+0xFF81B9DC,
+0xFF81B9DC,
+0xFF81B9DC,
+0xFF82BADD,
+0xFF82BADD,
+0xFF82BADD,
+0xFF82BADD,
+0xFF82BADD,
+0xFF82BADD,
+0xFF82BADD,
+0xFF82BADD,
+0xFF82BADD,
+0xFF82BADD,
+0xFF82BADD,
+0xFF82BADD,
+0xFF82BADD,
+0xFF82BADD,
+0xFF82BADD,
+0xFF82BADD,
+0xFF82BADD,
+0xFF82BADD,
+0xFF82BADD,
+0xFF82BADD,
+0xFF82BADD,
+0xFF82BADD,
+0xFF82BADD,
+0xFF82BADD,
+0xFF82BADD,
+0xFF82BADD,
+0xFF82BADD,
+0xFF82BADD,
+0xFF82BADD,
+0xFF82BADD,
+0xFF83BBDE,
+0xFF84BADE,
+0xFF85B9E0,
+0xFF87B8E0,
+0xFF85B9DE,
+0xFF84BADC,
+0xFF84BBDA,
+0xFF84BBDA,
+0xFF83BCDA,
+0xFF83BCDA,
+0xFF83BCDA,
+0xFF84BDDB,
+0xFF85BADC,
+0xFF85BADA,
+0xFF87B9DA,
+0xFF87BAD9,
+0xFF8DC0DD,
+0xFF9DBDD4,
+0xFFB0ADB8,
+0xFF604347,
+0xFF7B5552,
+0xFF755B5E,
+0xFFC4C5D9,
+0xFFAABFDE,
+0xFF9DC0E0,
+0xFF99C4E4,
+0xFF98C6E0,
+0xFF92C1DB,
+0xFF8DBEDC,
+0xFF8EBFDD,
+0xFF8EB9D9,
+0xFFA0BCD4,
+0xFFEAF0FC,
+0xFFF1F5FE,
+0xFF9CB2C0,
+0xFFBAD7E9,
+0xFFD0EDFF,
+0xFF86A8C1,
+0xFF93C0E1,
+0xFF84BAE0,
+0xFF7FBBDF,
+0xFF81BDDF,
+0xFF84BBD9,
+0xFF87BAD9,
+0xFF88BADB,
+0xFF88BADD,
+0xFF88BADF,
+0xFF87BBE0,
+0xFF83BDE2,
+0xFF83BDE2,
+0xFF84BCDF,
+0xFF85BBDF,
+0xFF85BBDF,
+0xFF85BBDF,
+0xFF85BBDF,
+0xFF85BBDF,
+0xFF85BBDF,
+0xFF85BBDF,
+0xFF84BADE,
+0xFF84BADE,
+0xFF84BADE,
+0xFF84BADE,
+0xFF84BADE,
+0xFF84BADE,
+0xFF85BBDF,
+0xFF85BBDF,
+0xFF85BBDF,
+0xFF85BBDF,
+0xFF84BADE,
+0xFF84BADE,
+0xFF84BADE,
+0xFF84BADE,
+0xFF84BADE,
+0xFF84BADE,
+0xFF83B9DD,
+0xFF83B9DD,
+0xFF83B9DD,
+0xFF83B9DD,
+0xFF84BADE,
+0xFF84BADE,
+0xFF84BADE,
+0xFF84BADE,
+0xFF83B9DD,
+0xFF83B9DD,
+0xFF83B9DD,
+0xFF83B9DD,
+0xFF83B9DD,
+0xFF83B9DD,
+0xFF83B9DD,
+0xFF83B9DD,
+0xFF83B9DD,
+0xFF83B9DD,
+0xFF83B9DD,
+0xFF83B9DD,
+0xFF83B9DD,
+0xFF83B9DD,
+0xFF83B9DD,
+0xFF83B9DD,
+0xFF83B9DD,
+0xFF83B9DD,
+0xFF82B8DC,
+0xFF82B8DC,
+0xFF82B8DC,
+0xFF81B9DC,
+0xFF81B9DC,
+0xFF81B9DC,
+0xFF81B9DC,
+0xFF81B9DC,
+0xFF80B8DB,
+0xFF80B8DB,
+0xFF80B8DB,
+0xFF80B8DB,
+0xFF81B7DB,
+0xFF81B7DB,
+0xFF7FB7DA,
+0xFF7DB8DA,
+0xFF7DB8DA,
+0xFF7DB8DA,
+0xFF7CB6DB,
+0xFF7CB6DB,
+0xFF7CB6DB,
+0xFF7CB6DB,
+0xFF7BB5DA,
+0xFF7BB5DA,
+0xFF7AB4DA,
+0xFF7AB4DA,
+0xFF7AB4DA,
+0xFF7AB4DA,
+0xFF79B3D9,
+0xFF79B3D9,
+0xFF76B2D7,
+0xFF76B2D7,
+0xFF77B2DA,
+0xFF76B1D9,
+0xFF75B0D8,
+0xFF74AFD7,
+0xFF74AFD7,
+0xFF74AFD7,
+0xFF74AFD9,
+0xFF73AED8,
+0xFF71AFD8,
+0xFF71AFD8,
+0xFF71AFD8,
+0xFF70AED7,
+0xFF6FACD8,
+0xFF6FACD8,
+0xFF66A5D1,
+0xFF66A5D1,
+0xFF67A6D1,
+0xFF67A6D1,
+0xFF68A7D2,
+0xFF68A7D2,
+0xFF6AA7D3,
+0xFF6AA7D3,
+0xFF6BA8D4,
+0xFF6BA9D2,
+0xFF6BA9D2,
+0xFF6CAAD3,
+0xFF6CAAD3,
+0xFF6CAAD3,
+0xFF6FAAD4,
+0xFF6FAAD4,
+0xFF70ABD5,
+0xFF71ACD6,
+0xFF71ACD4,
+0xFF72ADD5,
+0xFF72ADD5,
+0xFF73AED6,
+0xFF74AED6,
+0xFF75AFD7,
+0xFF75AFD7,
+0xFF75AFD7,
+0xFF75AFD7,
+0xFF75AFD5,
+0xFF78AFD6,
+0xFF78AFD6,
+0xFF79B0D7,
+0xFF79B0D7,
+0xFF77B1D7,
+0xFF77B1D7,
+0xFF77B1D7,
+0xFF78B2D8,
+0xFF78B2D8,
+0xFF78B2D8,
+0xFF7AB1D8,
+0xFF7AB2D7,
+0xFF7AB2D7,
+0xFF7BB3D8,
+0xFF7BB3D8,
+0xFF7BB3D8,
+0xFF7CB4D9,
+0xFF7CB4D9,
+0xFF7CB4D9,
+0xFF7CB4D9,
+0xFF7DB5D8,
+0xFF7DB5D8,
+0xFF7DB5D8,
+0xFF7DB5D8,
+0xFF7DB5D8,
+0xFF7DB5D8,
+0xFF7DB5D8,
+0xFF7DB5D8,
+0xFF7EB6D9,
+0xFF7EB6D9,
+0xFF7EB6D9,
+0xFF7EB6D9,
+0xFF7EB6D9,
+0xFF7EB6D9,
+0xFF7FB5D9,
+0xFF7EB6D9,
+0xFF7EB6D9,
+0xFF7FB7DA,
+0xFF80B6DA,
+0xFF80B6DA,
+0xFF7FB7DC,
+0xFF7FB7DC,
+0xFF7FB7DC,
+0xFF7FB7DA,
+0xFF7EB6D9,
+0xFF7FB7DA,
+0xFF7FB7DC,
+0xFF83B4D5,
+0xFF9ABED8,
+0xFF233644,
+0xFF1E1A19,
+0xFF1D1008,
+0xFF1B1108,
+0xFF261A0E,
+0xFF301A0C,
+0xFF4C3022,
+0xFF5A3A2D,
+0xFF422112,
+0xFF3D1C0B,
+0xFF7A5B47,
+0xFF3E2511,
+0xFF523F2E,
+0xFF37291C,
+0xFF291B10,
+0xFF443224,
+0xFF6A5447,
+0xFF3C261B,
+0xFF3D2920,
+0xFF716356,
+0xFFE2DACF,
+0xFFE1E0DB,
+0xFFEDF3F1,
+0xFF182828,
+0xFF6D7F81,
+0xFFC0CACB,
+0xFFCAD0CE,
+0xFFD6E0D8,
+0xFFBDC8C2,
+0xFFC4D2D5,
+0xFFADBCC1,
+0xFF798788,
+0xFFE7F5F5,
+0xFFD6E1E3,
+0xFF9FAAAC,
+0xFFDDE9E9,
+0xFFD0DFDC,
+0xFFCAD6D2,
+0xFFC7D7D4,
+0xFFA1B9BD,
+0xFFC8E1E8,
+0xFF6B818C,
+0xFF172D38,
+0xFF1A3139,
+0xFF314D58,
+0xFFA0CADA,
+0xFF89BDD3,
+0xFF83BCD9,
+0xFF80BBDB,
+0xFF81B8D7,
+0xFF84B9D9,
+0xFF82B8DA,
+0xFF83B9DB,
+0xFF83B9DB,
+0xFF83B9DB,
+0xFF83B9DB,
+0xFF83B9DB,
+0xFF83B9DB,
+0xFF83B9DB,
+0xFF83B9DB,
+0xFF83B9DB,
+0xFF83B9DB,
+0xFF83B9DB,
+0xFF83B9DB,
+0xFF83B9DB,
+0xFF83B9DB,
+0xFF83B9DB,
+0xFF83B9DB,
+0xFF83B9DB,
+0xFF83B9DB,
+0xFF83B9DB,
+0xFF83B9DB,
+0xFF84BADC,
+0xFF84BADC,
+0xFF84BADC,
+0xFF84BADC,
+0xFF84BADC,
+0xFF84BADC,
+0xFF84BADC,
+0xFF84BADC,
+0xFF84BADC,
+0xFF84BADC,
+0xFF84BADC,
+0xFF84BADC,
+0xFF84BADC,
+0xFF84BADC,
+0xFF84BADC,
+0xFF84BADC,
+0xFF84BADC,
+0xFF84BADC,
+0xFF84BADC,
+0xFF84BADC,
+0xFF84BADC,
+0xFF84BADC,
+0xFF84BADC,
+0xFF85BBDD,
+0xFF85BBDD,
+0xFF85BBDD,
+0xFF85BBDF,
+0xFF85B9DE,
+0xFF87B9DE,
+0xFF85BADC,
+0xFF85BADA,
+0xFF85BADA,
+0xFF87BAD9,
+0xFF87BAD9,
+0xFF87BAD9,
+0xFF89BADA,
+0xFF8DBBDC,
+0xFF92BDE0,
+0xFF98BEE2,
+0xFF9CC0E4,
+0xFF9DC1E5,
+0xFF9BC4E4,
+0xFFA0C2DD,
+0xFFC0CDE0,
+0xFF584D55,
+0xFF825C53,
+0xFF73483F,
+0xFF7A6164,
+0xFFC7C9D8,
+0xFF9CBED9,
+0xFF8FC2E1,
+0xFF88C0D9,
+0xFF8AC4DC,
+0xFF80BCD8,
+0xFF89C0DE,
+0xFF8BB8D5,
+0xFFA1C0D5,
+0xFFEDF6FF,
+0xFFF4F8FF,
+0xFF9DB3C1,
+0xFF9EBBCD,
+0xFFDAF3FF,
+0xFF88A8C1,
+0xFF8DB9DC,
+0xFF86BCE2,
+0xFF82BCE1,
+0xFF83BEE0,
+0xFF86BBDA,
+0xFF88BBDA,
+0xFF89BADB,
+0xFF89BADB,
+0xFF89B9DD,
+0xFF86BADF,
+0xFF82BCE1,
+0xFF82BCE1,
+0xFF85BBDF,
+0xFF86BBDD,
+0xFF86BBDD,
+0xFF86BBDD,
+0xFF86BBDD,
+0xFF86BBDD,
+0xFF86BBDD,
+0xFF86BBDD,
+0xFF86BBDD,
+0xFF86BBDD,
+0xFF86BBDD,
+0xFF86BBDD,
+0xFF86BBDD,
+0xFF86BBDD,
+0xFF85BADC,
+0xFF85BADC,
+0xFF86BBDD,
+0xFF86BBDD,
+0xFF86BBDD,
+0xFF85BADC,
+0xFF85BADC,
+0xFF85BADC,
+0xFF86BBDD,
+0xFF86BBDD,
+0xFF86BBDD,
+0xFF86BBDD,
+0xFF86BBDD,
+0xFF86BBDD,
+0xFF86BBDD,
+0xFF86BBDD,
+0xFF86BBDD,
+0xFF86BBDD,
+0xFF85BADC,
+0xFF85BADC,
+0xFF85BADC,
+0xFF85BADC,
+0xFF85BADC,
+0xFF85BADC,
+0xFF85BADC,
+0xFF85BADC,
+0xFF86BBDD,
+0xFF86BBDD,
+0xFF85BADC,
+0xFF85BADC,
+0xFF85BADC,
+0xFF84B9DB,
+0xFF84B9DB,
+0xFF84B9DB,
+0xFF84B9DB,
+0xFF84B9DB,
+0xFF84B9DB,
+0xFF83B9DB,
+0xFF83B9DB,
+0xFF83B9DB,
+0xFF83B9DB,
+0xFF83B9DB,
+0xFF82B8DC,
+0xFF82B8DC,
+0xFF82B8DC,
+0xFF82B8DC,
+0xFF82B8DC,
+0xFF82B8DC,
+0xFF82B8DC,
+0xFF82B8DC,
+0xFF81B9DC,
+0xFF80B8DB,
+0xFF80B8DB,
+0xFF80B8DB,
+0xFF80B8DB,
+0xFF7FB7DA,
+0xFF7FB7DA,
+0xFF7FB7DA,
+0xFF7EB6D9,
+0xFF7EB6D9,
+0xFF7EB6DB,
+0xFF7DB5DA,
+0xFF7DB5DA,
+0xFF7CB4D9,
+0xFF7AB4D9,
+0xFF7AB4D9,
+0xFF7BB5DA,
+0xFF7AB4D9,
+0xFF79B3D9,
+0xFF78B2D8,
+0xFF77B1D7,
+0xFF77B1D7,
+0xFF76B2D7,
+0xFF76B2D7,
+0xFF75B0D8,
+0xFF75B0D8,
+0xFF74AFD7,
+0xFF74AFD7,
+0xFF73AED6,
+0xFF73AED6,
+0xFF73AED8,
+0xFF72ADD7,
+0xFF67A6D2,
+0xFF67A6D2,
+0xFF68A7D2,
+0xFF68A7D2,
+0xFF69A8D3,
+0xFF69A8D3,
+0xFF6AA7D3,
+0xFF6BA8D4,
+0xFF6CAAD3,
+0xFF6CAAD3,
+0xFF6CAAD3,
+0xFF6DABD4,
+0xFF6DABD4,
+0xFF6DABD4,
+0xFF70ABD5,
+0xFF70ABD5,
+0xFF71ACD6,
+0xFF72ADD7,
+0xFF72ADD5,
+0xFF72ADD5,
+0xFF73AED6,
+0xFF74AFD7,
+0xFF75AFD7,
+0xFF75AFD7,
+0xFF75AFD7,
+0xFF75AFD7,
+0xFF75AFD5,
+0xFF76B0D6,
+0xFF78AFD6,
+0xFF79B0D7,
+0xFF79B0D7,
+0xFF79B0D7,
+0xFF77B1D7,
+0xFF77B1D7,
+0xFF78B2D8,
+0xFF78B2D8,
+0xFF79B3D9,
+0xFF79B3D9,
+0xFF7BB3D8,
+0xFF7BB3D8,
+0xFF7BB3D8,
+0xFF7BB3D8,
+0xFF7CB4D9,
+0xFF7CB4D9,
+0xFF7DB5DA,
+0xFF7DB5DA,
+0xFF7DB5DA,
+0xFF7DB5DA,
+0xFF7DB5D8,
+0xFF7DB5D8,
+0xFF7EB6D9,
+0xFF7EB6D9,
+0xFF7EB6D9,
+0xFF7EB6D9,
+0xFF7EB6D9,
+0xFF7EB6D9,
+0xFF7FB7DA,
+0xFF7FB7DA,
+0xFF7FB7DA,
+0xFF7FB7DA,
+0xFF7FB7DA,
+0xFF7FB7DA,
+0xFF80B6DA,
+0xFF80B6DA,
+0xFF7FB7DA,
+0xFF7FB7DA,
+0xFF80B6DA,
+0xFF80B6DA,
+0xFF7FB7DC,
+0xFF7FB7DA,
+0xFF7FB7DA,
+0xFF7FB7DA,
+0xFF7FB7D8,
+0xFF81B9DA,
+0xFF80B8DD,
+0xFF81B3D4,
+0xFF97BCD6,
+0xFF627584,
+0xFF0E0E0E,
+0xFF1D130A,
+0xFF1C1209,
+0xFF281C10,
+0xFF261304,
+0xFF513728,
+0xFF523223,
+0xFF4C2B1A,
+0xFF371603,
+0xFF6B4C38,
+0xFF4C311C,
+0xFF56412E,
+0xFF3B2D20,
+0xFF2C2014,
+0xFF261607,
+0xFF4A382A,
+0xFF68564A,
+0xFF342319,
+0xFFC5BBB1,
+0xFFBDBBAF,
+0xFFEDF2EB,
+0xFFD9E4E0,
+0xFFC0D0CF,
+0xFFD0E0E0,
+0xFFDFEAEE,
+0xFFDBE5E7,
+0xFFCFDBD9,
+0xFFC9D7D7,
+0xFFAFC1C5,
+0xFFCBDEE2,
+0xFFD6E9E5,
+0xFFC5D6D0,
+0xFF9BA9A9,
+0xFF879596,
+0xFFDBE7E5,
+0xFFB8C4C2,
+0xFFADB9B5,
+0xFFCADAD9,
+0xFFB1C9CB,
+0xFF637C81,
+0xFF3E555B,
+0xFF1C343E,
+0xFF0A2632,
+0xFF93B8CA,
+0xFF8BBDD6,
+0xFF81BAD8,
+0xFF81BCDC,
+0xFF7BB6D6,
+0xFF83BEDE,
+0xFF84BCDD,
+0xFF83B9DB,
+0xFF83B9DB,
+0xFF84BADC,
+0xFF84BADC,
+0xFF84BADC,
+0xFF84BADC,
+0xFF84BADC,
+0xFF84BADC,
+0xFF83B9DB,
+0xFF83B9DB,
+0xFF83B9DB,
+0xFF83B9DB,
+0xFF83B9DB,
+0xFF84BADC,
+0xFF84BADC,
+0xFF84BADC,
+0xFF84BADC,
+0xFF84BADC,
+0xFF84BADC,
+0xFF84BADC,
+0xFF84BADC,
+0xFF84BADC,
+0xFF84BADC,
+0xFF84BADC,
+0xFF84BADC,
+0xFF84BADC,
+0xFF84BADC,
+0xFF84BADC,
+0xFF84BADC,
+0xFF84BADC,
+0xFF84BADC,
+0xFF84BADC,
+0xFF85BBDD,
+0xFF85BBDD,
+0xFF85BBDD,
+0xFF85BBDD,
+0xFF85BBDD,
+0xFF85BBDD,
+0xFF85BBDD,
+0xFF85BBDD,
+0xFF86BCDE,
+0xFF85BBDD,
+0xFF85BBDD,
+0xFF85BBDD,
+0xFF85BBDD,
+0xFF85BBDD,
+0xFF85BBDD,
+0xFF84BADC,
+0xFF86BBDD,
+0xFF86BBDD,
+0xFF86BBDB,
+0xFF86BBDB,
+0xFF89BCDB,
+0xFF8CBDDD,
+0xFF8FBEDC,
+0xFF92BFDE,
+0xFF95C0E2,
+0xFF98C0E3,
+0xFF9DC1E5,
+0xFF9FC1E6,
+0xFFA2C0E6,
+0xFFA0C0E6,
+0xFF9CC3E4,
+0xFF9EC3E0,
+0xFFA9C5DB,
+0xFFABB3BE,
+0xFF5B423E,
+0xFF7C5246,
+0xFF643C32,
+0xFF8F7B7C,
+0xFFB3C5D9,
+0xFF8BB8D5,
+0xFF87BDD9,
+0xFF7DB9D5,
+0xFF7FBCDB,
+0xFF86BFDD,
+0xFF88B7D3,
+0xFFA9C8DC,
+0xFFEEF7FE,
+0xFFF0F7FD,
+0xFF96ABBC,
+0xFF95B0C5,
+0xFFDCF2FF,
+0xFF8BA7BF,
+0xFF8FBBDE,
+0xFF87BBE2,
+0xFF86BCE2,
+0xFF86BCDE,
+0xFF87BCDB,
+0xFF89BCDB,
+0xFF8ABBDC,
+0xFF8ABBDC,
+0xFF8ABADE,
+0xFF89BBDE,
+0xFF85BDE0,
+0xFF83BEE0,
+0xFF86BCDE,
+0xFF87BCDE,
+0xFF87BCDE,
+0xFF87BCDE,
+0xFF87BCDE,
+0xFF87BCDE,
+0xFF87BCDE,
+0xFF87BCDE,
+0xFF87BCDE,
+0xFF87BCDE,
+0xFF87BCDE,
+0xFF87BCDE,
+0xFF87BCDE,
+0xFF87BCDE,
+0xFF86BBDD,
+0xFF86BBDD,
+0xFF87BCDE,
+0xFF86BBDD,
+0xFF86BBDD,
+0xFF86BBDD,
+0xFF86BBDD,
+0xFF86BBDD,
+0xFF86BBDD,
+0xFF86BBDD,
+0xFF86BBDD,
+0xFF86BBDD,
+0xFF86BBDD,
+0xFF86BBDD,
+0xFF86BBDD,
+0xFF86BBDD,
+0xFF86BBDD,
+0xFF86BBDD,
+0xFF86BBDD,
+0xFF86BBDD,
+0xFF86BBDD,
+0xFF86BBDD,
+0xFF86BBDD,
+0xFF86BBDD,
+0xFF86BBDD,
+0xFF86BBDD,
+0xFF86BBDD,
+0xFF86BBDD,
+0xFF86BBDD,
+0xFF85BADC,
+0xFF85BADC,
+0xFF85BADC,
+0xFF85BADC,
+0xFF85BADC,
+0xFF85BADC,
+0xFF85BADC,
+0xFF85BADC,
+0xFF85BADC,
+0xFF84BADC,
+0xFF83B9DB,
+0xFF83B9DB,
+0xFF83B9DB,
+0xFF83B9DD,
+0xFF83B9DD,
+0xFF83B9DD,
+0xFF83B9DD,
+0xFF82B8DC,
+0xFF82B8DC,
+0xFF82B8DC,
+0xFF82B8DC,
+0xFF81B7DB,
+0xFF80B8DB,
+0xFF80B8DB,
+0xFF80B8DB,
+0xFF80B8DB,
+0xFF7FB7DA,
+0xFF7FB7DA,
+0xFF7FB7DA,
+0xFF7FB7DA,
+0xFF7FB7DA,
+0xFF7EB6DB,
+0xFF7EB6DB,
+0xFF7DB5DA,
+0xFF7DB5DA,
+0xFF7BB5DA,
+0xFF7BB5DA,
+0xFF7BB5DA,
+0xFF7AB4D9,
+0xFF79B3D9,
+0xFF78B2D8,
+0xFF78B2D8,
+0xFF78B2D8,
+0xFF77B3D8,
+0xFF77B3D8,
+0xFF76B1D9,
+0xFF76B1D9,
+0xFF75B0D8,
+0xFF75B0D8,
+0xFF74AFD7,
+0xFF74AFD7,
+0xFF73AED8,
+0xFF73AED8,
+0xFF69A6D2,
+0xFF69A6D2,
+0xFF6AA7D3,
+0xFF6AA7D3,
+0xFF6BA9D2,
+0xFF6BA9D2,
+0xFF6CAAD3,
+0xFF6CAAD3,
+0xFF6FAAD4,
+0xFF6FAAD4,
+0xFF6FAAD2,
+0xFF70ABD3,
+0xFF71ACD4,
+0xFF71ACD4,
+0xFF72ADD5,
+0xFF72ADD5,
+0xFF74AED6,
+0xFF74AED6,
+0xFF74AED6,
+0xFF75AFD7,
+0xFF75AFD5,
+0xFF75AFD5,
+0xFF76B0D6,
+0xFF76B0D6,
+0xFF76B0D6,
+0xFF76B0D6,
+0xFF78AFD6,
+0xFF78AFD6,
+0xFF79B1D6,
+0xFF79B1D6,
+0xFF7AB2D7,
+0xFF7AB2D7,
+0xFF78B2D7,
+0xFF79B3D8,
+0xFF79B3D8,
+0xFF79B3D8,
+0xFF7CB4D9,
+0xFF7CB4D9,
+0xFF7CB4D9,
+0xFF7CB4D9,
+0xFF7CB4D7,
+0xFF7DB5D8,
+0xFF7EB4D8,
+0xFF7EB4D8,
+0xFF7FB5D9,
+0xFF7FB5D9,
+0xFF7FB5D9,
+0xFF7FB5D9,
+0xFF7EB6D9,
+0xFF7EB6D9,
+0xFF7FB7DA,
+0xFF7FB7DA,
+0xFF7FB7DA,
+0xFF7FB7DA,
+0xFF80B6DA,
+0xFF80B6DA,
+0xFF80B6DA,
+0xFF80B6DA,
+0xFF80B6DA,
+0xFF80B6DA,
+0xFF80B6DA,
+0xFF80B6DA,
+0xFF80B6DA,
+0xFF80B6DA,
+0xFF81B7DB,
+0xFF81B7DB,
+0xFF81B7D9,
+0xFF81B7D9,
+0xFF80B8DB,
+0xFF80B8DB,
+0xFF80B8DB,
+0xFF80B8D9,
+0xFF81B7D9,
+0xFF82B8DA,
+0xFF80B8DD,
+0xFF86B8D9,
+0xFF95BAD5,
+0xFF728896,
+0xFF080A09,
+0xFF1C130A,
+0xFF170D04,
+0xFF281C10,
+0xFF2C1B0B,
+0xFF553E2C,
+0xFF4E2F1D,
+0xFF4E2D1A,
+0xFF391805,
+0xFF5F402C,
+0xFF563A25,
+0xFF4D3624,
+0xFF39291C,
+0xFF34281C,
+0xFF281B0A,
+0xFF594C3B,
+0xFF9C8E81,
+0xFF94877E,
+0xFF988F86,
+0xFFE2DFD6,
+0xFFDEE3DC,
+0xFFDAE6E2,
+0xFFA3B5B7,
+0xFFC6D9DD,
+0xFFC5D4D7,
+0xFFCFDEE1,
+0xFFB6C8CC,
+0xFFD2E5E9,
+0xFF82979A,
+0xFF869C9A,
+0xFFD7ECE7,
+0xFF546962,
+0xFFC8DCDB,
+0xFF3E4E4E,
+0xFFEAF4F3,
+0xFF879190,
+0xFF848F91,
+0xFFEFFDFF,
+0xFF869598,
+0xFF132527,
+0xFF24393E,
+0xFF15313C,
+0xFF61879E,
+0xFF92C1DF,
+0xFF84B8DD,
+0xFF87BDE3,
+0xFF85B7DA,
+0xFF89BEDE,
+0xFF7EB9DB,
+0xFF80BCDE,
+0xFF83BBDC,
+0xFF84BADC,
+0xFF84BADC,
+0xFF84BADC,
+0xFF85BBDD,
+0xFF85BBDD,
+0xFF85BBDD,
+0xFF85BBDD,
+0xFF84BADC,
+0xFF84BADC,
+0xFF84BADC,
+0xFF84BADC,
+0xFF84BADC,
+0xFF84BADC,
+0xFF85BBDD,
+0xFF85BBDD,
+0xFF86BBDD,
+0xFF86BBDD,
+0xFF86BBDD,
+0xFF86BBDD,
+0xFF86BBDD,
+0xFF86BBDD,
+0xFF86BBDD,
+0xFF86BBDD,
+0xFF86BBDD,
+0xFF86BBDD,
+0xFF86BBDD,
+0xFF86BBDD,
+0xFF86BBDD,
+0xFF86BBDD,
+0xFF86BBDD,
+0xFF86BBDD,
+0xFF87BCDC,
+0xFF87BCDC,
+0xFF87BCDC,
+0xFF87BCDC,
+0xFF87BCDC,
+0xFF87BCDC,
+0xFF87BCDC,
+0xFF87BCDC,
+0xFF87BCDC,
+0xFF87BCDC,
+0xFF87BCDC,
+0xFF87BCDC,
+0xFF87BCDC,
+0xFF87BCDC,
+0xFF87BCDC,
+0xFF86BDDC,
+0xFF87BEDD,
+0xFF88BFDE,
+0xFF89BEDD,
+0xFF8CBFDE,
+0xFF8FC0E0,
+0xFF92C0E1,
+0xFF96C1E1,
+0xFF99C2E2,
+0xFF9CC3E4,
+0xFF9EC2E4,
+0xFF9EC2E4,
+0xFF9EC0E3,
+0xFF9EC0E3,
+0xFF9CC0E2,
+0xFF96C1E1,
+0xFF94C1DE,
+0xFF90BAD2,
+0xFFADCADA,
+0xFF9A9DA6,
+0xFF5F4745,
+0xFF804F3E,
+0xFF6C4234,
+0xFF958E96,
+0xFFAABED6,
+0xFF8FBADA,
+0xFF89BFE3,
+0xFF86C1E3,
+0xFF88C1DF,
+0xFF8BBDD6,
+0xFFACCDDE,
+0xFFF4FFFF,
+0xFFF3FBFE,
+0xFF8FA4B5,
+0xFF89A4B9,
+0xFFDFF4FF,
+0xFF8DA7C0,
+0xFF93BEE1,
+0xFF8ABBE3,
+0xFF88BDDF,
+0xFF88BDDD,
+0xFF8ABDDC,
+0xFF8ABDDC,
+0xFF8ABCDD,
+0xFF8ABCDF,
+0xFF8BBCDD,
+0xFF8ABCDF,
+0xFF87BDE1,
+0xFF86BEE1,
+0xFF89BEE0,
+0xFF8BBDDE,
+0xFF8BBDDE,
+0xFF8BBDDE,
+0xFF8BBDDE,
+0xFF8BBDDE,
+0xFF8BBDDE,
+0xFF8ABCDD,
+0xFF8ABCDD,
+0xFF8ABCDD,
+0xFF8ABCDD,
+0xFF8ABCDD,
+0xFF8ABCDD,
+0xFF8ABCDD,
+0xFF8ABCDD,
+0xFF89BBDC,
+0xFF8ABCDD,
+0xFF8ABCDD,
+0xFF8ABCDD,
+0xFF8ABCDD,
+0xFF8ABCDD,
+0xFF8ABCDD,
+0xFF89BBDC,
+0xFF89BBDC,
+0xFF89BBDC,
+0xFF89BBDC,
+0xFF89BBDC,
+0xFF89BBDC,
+0xFF89BBDC,
+0xFF89BBDC,
+0xFF89BBDC,
+0xFF89BBDC,
+0xFF87BCDC,
+0xFF87BCDC,
+0xFF87BCDC,
+0xFF87BCDC,
+0xFF87BCDC,
+0xFF87BCDC,
+0xFF87BCDC,
+0xFF87BCDC,
+0xFF86BBDB,
+0xFF86BBDB,
+0xFF86BBDB,
+0xFF86BBDB,
+0xFF86BBDB,
+0xFF86BBDB,
+0xFF86BBDB,
+0xFF86BBDB,
+0xFF89BBDE,
+0xFF88BADD,
+0xFF86BBDD,
+0xFF86BBDD,
+0xFF86BBDD,
+0xFF85BADC,
+0xFF84BADC,
+0xFF84BADC,
+0xFF84BADC,
+0xFF84BADC,
+0xFF83B9DB,
+0xFF83B9DB,
+0xFF84B9DB,
+0xFF84B9DB,
+0xFF84B9DB,
+0xFF83B9DB,
+0xFF82B8DA,
+0xFF82B8DA,
+0xFF82B8DA,
+0xFF82B8DA,
+0xFF81B7D9,
+0xFF81B7D9,
+0xFF81B7DB,
+0xFF81B7DB,
+0xFF80B8DB,
+0xFF80B8DB,
+0xFF7FB7DA,
+0xFF7FB7DA,
+0xFF7EB6D9,
+0xFF7EB6D9,
+0xFF7EB6D9,
+0xFF7EB6D9,
+0xFF7BB5DA,
+0xFF7BB5DA,
+0xFF7AB4D9,
+0xFF79B3D8,
+0xFF79B3D8,
+0xFF78B2D7,
+0xFF78B2D7,
+0xFF78B2D7,
+0xFF78B2D8,
+0xFF78B2D8,
+0xFF76B2D7,
+0xFF76B2D7,
+0xFF75B0D8,
+0xFF75B0D8,
+0xFF74AFD7,
+0xFF74AFD7,
+0xFF6AA7D3,
+0xFF6AA7D3,
+0xFF6BA8D4,
+0xFF6BA8D4,
+0xFF6CAAD3,
+0xFF6CAAD3,
+0xFF6DABD4,
+0xFF6DABD4,
+0xFF70ABD5,
+0xFF70ABD5,
+0xFF70ABD3,
+0xFF71ACD4,
+0xFF72ADD5,
+0xFF72ADD5,
+0xFF73AED6,
+0xFF73AED6,
+0xFF75AFD7,
+0xFF75AFD7,
+0xFF75AFD7,
+0xFF75AFD7,
+0xFF76B0D6,
+0xFF76B0D6,
+0xFF76B0D6,
+0xFF76B0D6,
+0xFF77B1D7,
+0xFF77B1D7,
+0xFF79B0D7,
+0xFF79B0D7,
+0xFF7AB2D7,
+0xFF7BB3D8,
+0xFF7BB3D8,
+0xFF7BB3D8,
+0xFF79B3D8,
+0xFF7AB4D9,
+0xFF7AB4D9,
+0xFF7AB4D9,
+0xFF7DB5DA,
+0xFF7DB5DA,
+0xFF7DB5DA,
+0xFF7DB5DA,
+0xFF7DB5D8,
+0xFF7DB5D8,
+0xFF7FB5D9,
+0xFF7FB5D9,
+0xFF7FB5D9,
+0xFF80B6DA,
+0xFF80B6DA,
+0xFF80B6DA,
+0xFF7FB7DA,
+0xFF7FB7DA,
+0xFF7FB7DA,
+0xFF7FB7DA,
+0xFF80B8DB,
+0xFF80B8DB,
+0xFF81B7DB,
+0xFF81B7DB,
+0xFF81B7DB,
+0xFF81B7DB,
+0xFF81B7DB,
+0xFF81B7DB,
+0xFF81B7DB,
+0xFF81B7DB,
+0xFF81B7DB,
+0xFF81B7DB,
+0xFF82B8DC,
+0xFF82B8DC,
+0xFF82B8DA,
+0xFF82B8DA,
+0xFF81B9DC,
+0xFF81B9DC,
+0xFF81B9DA,
+0xFF81B9DA,
+0xFF81B7D9,
+0xFF84BADC,
+0xFF81B7DD,
+0xFF84B6D7,
+0xFFA0C5E0,
+0xFF314858,
+0xFF1D2122,
+0xFF120B03,
+0xFF140A01,
+0xFF2E2015,
+0xFF2A1909,
+0xFF5A4331,
+0xFF422311,
+0xFF563522,
+0xFF3D1E0A,
+0xFF5D3E2A,
+0xFF5C3D28,
+0xFF452C18,
+0xFF3A281C,
+0xFF3B2F23,
+0xFF3E3222,
+0xFFF8EDDB,
+0xFFB2AB9B,
+0xFFC4BEB2,
+0xFFA7A39A,
+0xFFEDEEE8,
+0xFFD9E6DF,
+0xFFCADDDB,
+0xFFA0B3B7,
+0xFFBACDD3,
+0xFFC8DADE,
+0xFFA7B9BB,
+0xFFA9BBBF,
+0xFFCDE0E4,
+0xFF6B8387,
+0xFF99B1B1,
+0xFF3C514C,
+0xFF758A85,
+0xFF6B7F80,
+0xFF6F8185,
+0xFFF5FFFF,
+0xFF707B7D,
+0xFF39464C,
+0xFF59666C,
+0xFF212C30,
+0xFF202F34,
+0xFF193038,
+0xFF4F7081,
+0xFF9AC9E5,
+0xFF7FB5D9,
+0xFF87BCE4,
+0xFF85B9E0,
+0xFF8ABADE,
+0xFF89BBDE,
+0xFF81BCDE,
+0xFF82BDDF,
+0xFF84BCDD,
+0xFF85BBDD,
+0xFF85BBDD,
+0xFF85BBDD,
+0xFF85BBDD,
+0xFF85BBDD,
+0xFF85BBDD,
+0xFF85BBDD,
+0xFF85BBDD,
+0xFF85BBDD,
+0xFF85BBDD,
+0xFF86BCDE,
+0xFF86BCDE,
+0xFF86BCDE,
+0xFF86BCDE,
+0xFF86BCDE,
+0xFF87BCDE,
+0xFF87BCDE,
+0xFF87BCDE,
+0xFF87BCDE,
+0xFF88BDDF,
+0xFF88BDDF,
+0xFF88BDDF,
+0xFF88BDDF,
+0xFF87BCDE,
+0xFF87BCDE,
+0xFF88BDDF,
+0xFF88BDDF,
+0xFF88BDDF,
+0xFF88BDDF,
+0xFF88BDDF,
+0xFF89BEE0,
+0xFF88BDDD,
+0xFF88BDDD,
+0xFF88BDDD,
+0xFF88BDDD,
+0xFF88BDDD,
+0xFF88BDDD,
+0xFF88BDDD,
+0xFF88BDDD,
+0xFF88BDDD,
+0xFF88BDDD,
+0xFF88BDDD,
+0xFF89BEDE,
+0xFF89BEDE,
+0xFF89BEDE,
+0xFF8ABFDF,
+0xFF8ABFDF,
+0xFF8BC0DF,
+0xFF8CC1E0,
+0xFF8FC2E1,
+0xFF91C2E2,
+0xFF91C4E3,
+0xFF92C3E3,
+0xFF95C2E3,
+0xFF98C1E1,
+0xFF96BFDF,
+0xFF96BFDF,
+0xFF94BFDF,
+0xFF93BEDE,
+0xFF96BDDE,
+0xFF94BDDD,
+0xFF8FBEDC,
+0xFF8CBFDA,
+0xFF8FC1DA,
+0xFF90BAD0,
+0xFFA5BBD0,
+0xFF9A97A0,
+0xFF734B3F,
+0xFF7A4B39,
+0xFF492D2A,
+0xFFA5A1AF,
+0xFFA4BDDC,
+0xFF90BCE3,
+0xFF8BBDE0,
+0xFF89BCDB,
+0xFF87B7CE,
+0xFFB3D7E5,
+0xFFE8F3F5,
+0xFFF1FBFD,
+0xFF8BA2B4,
+0xFF84A0B6,
+0xFFE1F6FF,
+0xFF8EA6BE,
+0xFF96BEE1,
+0xFF8ABCE1,
+0xFF8BBDDE,
+0xFF8ABDDA,
+0xFF8BBEDD,
+0xFF89BEDE,
+0xFF8BBDE0,
+0xFF8BBDE0,
+0xFF8CBDDE,
+0xFF8BBDDE,
+0xFF89BEE0,
+0xFF88BEE0,
+0xFF8ABFDF,
+0xFF8CBEDF,
+0xFF8CBEDF,
+0xFF8CBEDF,
+0xFF8CBEDF,
+0xFF8CBEDF,
+0xFF8BBDDE,
+0xFF8BBDDE,
+0xFF8BBDDE,
+0xFF8BBDDE,
+0xFF8BBDDE,
+0xFF8CBEDF,
+0xFF8BBDDE,
+0xFF8BBDDE,
+0xFF8BBDDE,
+0xFF8BBDDE,
+0xFF8BBDDE,
+0xFF8BBDDE,
+0xFF8BBDDE,
+0xFF8CBEDF,
+0xFF8CBEDF,
+0xFF8BBDDE,
+0xFF8BBDDE,
+0xFF8BBDDE,
+0xFF8BBDDE,
+0xFF8BBDDE,
+0xFF8BBDDE,
+0xFF8BBDDE,
+0xFF8BBDDE,
+0xFF8BBDDE,
+0xFF8BBDDE,
+0xFF8BBDDE,
+0xFF88BDDD,
+0xFF88BDDD,
+0xFF88BDDD,
+0xFF88BDDD,
+0xFF88BDDD,
+0xFF88BDDD,
+0xFF88BDDD,
+0xFF88BDDD,
+0xFF88BDDD,
+0xFF88BDDD,
+0xFF88BDDD,
+0xFF88BDDD,
+0xFF88BDDD,
+0xFF88BDDD,
+0xFF88BDDD,
+0xFF88BDDD,
+0xFF8ABCDF,
+0xFF8ABCDF,
+0xFF87BCDE,
+0xFF87BCDE,
+0xFF87BCDE,
+0xFF86BBDD,
+0xFF85BBDD,
+0xFF85BBDD,
+0xFF84BADC,
+0xFF84BADC,
+0xFF84BADC,
+0xFF84BADC,
+0xFF85BADC,
+0xFF85BADC,
+0xFF85BADC,
+0xFF85BADC,
+0xFF83B9DB,
+0xFF83B9DB,
+0xFF83B9DB,
+0xFF83B9DB,
+0xFF83B9DB,
+0xFF82B8DA,
+0xFF82B8DC,
+0xFF82B8DC,
+0xFF81B9DC,
+0xFF80B8DB,
+0xFF80B8DB,
+0xFF80B8DB,
+0xFF7FB7DA,
+0xFF7FB7DA,
+0xFF7FB7DA,
+0xFF7EB6D9,
+0xFF7EB6DB,
+0xFF7CB6DB,
+0xFF7BB5DA,
+0xFF7AB4D9,
+0xFF7AB4D9,
+0xFF7AB4D9,
+0xFF79B3D8,
+0xFF79B3D8,
+0xFF79B3D9,
+0xFF79B3D9,
+0xFF77B3D8,
+0xFF76B2D7,
+0xFF76B1D9,
+0xFF76B1D9,
+0xFF75B0D8,
+0xFF75B0D8,
+0xFF6AA8D1,
+0xFF6BA9D2,
+0xFF6BA9D2,
+0xFF6CAAD3,
+0xFF6FAAD4,
+0xFF6FAAD4,
+0xFF6FAAD2,
+0xFF70ABD3,
+0xFF70ABD3,
+0xFF71ACD4,
+0xFF71ACD4,
+0xFF72ADD5,
+0xFF74AED4,
+0xFF74AED4,
+0xFF75AFD5,
+0xFF75AFD5,
+0xFF77AED5,
+0xFF77AED5,
+0xFF78AFD6,
+0xFF78AFD6,
+0xFF78AFD6,
+0xFF78AFD6,
+0xFF79B0D7,
+0xFF79B0D7,
+0xFF7AB2D7,
+0xFF7AB2D7,
+0xFF7AB2D7,
+0xFF7BB3D8,
+0xFF7BB3D8,
+0xFF7CB4D9,
+0xFF7CB4D9,
+0xFF7CB4D9,
+0xFF7AB4D9,
+0xFF7AB4D9,
+0xFF7DB5DA,
+0xFF7DB5DA,
+0xFF7DB5D8,
+0xFF7EB6D9,
+0xFF7EB6D9,
+0xFF7EB6D9,
+0xFF7FB5D9,
+0xFF7FB5D9,
+0xFF80B6DA,
+0xFF80B6DA,
+0xFF80B6D8,
+0xFF80B6D8,
+0xFF80B6D8,
+0xFF80B6D8,
+0xFF81B7D9,
+0xFF81B7D9,
+0xFF81B7D9,
+0xFF81B7D9,
+0xFF81B7D9,
+0xFF81B7D9,
+0xFF81B7D9,
+0xFF81B7D9,
+0xFF82B8DA,
+0xFF82B8DA,
+0xFF83B9DB,
+0xFF83B9DB,
+0xFF83B9DB,
+0xFF83B9DB,
+0xFF83B9DB,
+0xFF83B9DB,
+0xFF84B8DD,
+0xFF84B8DD,
+0xFF83B9DB,
+0xFF83B9DB,
+0xFF82BADD,
+0xFF82BADD,
+0xFF83B9DB,
+0xFF83B9DB,
+0xFF85BADC,
+0xFF82B8DA,
+0xFF83B9DF,
+0xFF89BADB,
+0xFF95BDD7,
+0xFF0D2434,
+0xFF121617,
+0xFF150E06,
+0xFF1C1209,
+0xFF2C1E13,
+0xFF261505,
+0xFF4A3522,
+0xFF482915,
+0xFF583724,
+0xFF4B2C18,
+0xFF563723,
+0xFF563722,
+0xFF4D3221,
+0xFF3A281E,
+0xFF21140B,
+0xFF281F0E,
+0xFFEDE6D4,
+0xFF858273,
+0xFFE4E4D8,
+0xFFD8DBD2,
+0xFFDFEAE4,
+0xFFBED7D4,
+0xFFB4D0D1,
+0xFFA0B5BA,
+0xFFC3D6DA,
+0xFFB8CCCD,
+0xFF9DAFAF,
+0xFFC6D2D2,
+0xFF798788,
+0xFF00111A,
+0xFF667D85,
+0xFF425252,
+0xFFE7F5F5,
+0xFF5D6E75,
+0xFFD7EAF1,
+0xFF526569,
+0xFF1F3236,
+0xFF1E2D34,
+0xFF424C55,
+0xFF242D34,
+0xFF1E2F39,
+0xFF4A697D,
+0xFF9FCBE4,
+0xFF86BDDC,
+0xFF85C0E2,
+0xFF85BBDD,
+0xFF86BBDD,
+0xFF88BCE1,
+0xFF84BADE,
+0xFF89BFE1,
+0xFF87BDDF,
+0xFF87BCDC,
+0xFF87BCDC,
+0xFF87BCDC,
+0xFF87BCDC,
+0xFF87BCDC,
+0xFF87BCDC,
+0xFF88BDDD,
+0xFF88BDDD,
+0xFF88BDDD,
+0xFF88BDDD,
+0xFF88BDDD,
+0xFF88BDDD,
+0xFF88BDDD,
+0xFF88BDDD,
+0xFF88BDDD,
+0xFF88BDDD,
+0xFF88BDDD,
+0xFF88BDDD,
+0xFF88BDDD,
+0xFF89BEDE,
+0xFF89BEDE,
+0xFF89BEDE,
+0xFF89BEDE,
+0xFF89BEDE,
+0xFF89BEDE,
+0xFF89BEDE,
+0xFF89BEDE,
+0xFF89BEDE,
+0xFF89BEDE,
+0xFF8ABFDF,
+0xFF8ABFDF,
+0xFF8ABFDF,
+0xFF8BBDDE,
+0xFF8BBDDE,
+0xFF8BBDDE,
+0xFF8BBDDE,
+0xFF8BBDDE,
+0xFF8CBEDF,
+0xFF8CBEDF,
+0xFF8CBEDF,
+0xFF8BBDDE,
+0xFF8BBDDE,
+0xFF8CBEDF,
+0xFF8CBEDF,
+0xFF8DBFE0,
+0xFF8DBFE0,
+0xFF8DBFE0,
+0xFF8EC0E1,
+0xFF8FC0E0,
+0xFF8FC0DE,
+0xFF92C0E1,
+0xFF93C1E2,
+0xFF8EC3E3,
+0xFF8DC2E2,
+0xFF8EC0E1,
+0xFF8EBFDF,
+0xFF8DBEDE,
+0xFF8CBFDE,
+0xFF8AC0DC,
+0xFF8AC0DC,
+0xFF8DBEDC,
+0xFF8DBEDC,
+0xFF8CBFDE,
+0xFF8AC0DC,
+0xFF8ABDD8,
+0xFF8FBED8,
+0xFF94BBDA,
+0xFFAFC1D7,
+0xFF7F7073,
+0xFF6D4B41,
+0xFF673B2E,
+0xFF5D3F3D,
+0xFFA9ADC8,
+0xFF9BB5DA,
+0xFF96B8DB,
+0xFF95BEDC,
+0xFF91BDD6,
+0xFFB7DBEB,
+0xFFEAF5F9,
+0xFFF2FBFF,
+0xFF87A2B5,
+0xFF86A5BA,
+0xFFE0F5FF,
+0xFF8CA5BB,
+0xFF96BFDF,
+0xFF8BBDE0,
+0xFF8DBEDC,
+0xFF8CBED9,
+0xFF8AC0DC,
+0xFF89C0DF,
+0xFF8ABFE1,
+0xFF8ABFE1,
+0xFF8DBEDF,
+0xFF8DBEDE,
+0xFF8CBEDF,
+0xFF8ABFDF,
+0xFF8CBEDF,
+0xFF8CBEDF,
+0xFF8CBEDF,
+0xFF8CBEDF,
+0xFF8CBEDF,
+0xFF8CBEDF,
+0xFF8CBEDF,
+0xFF8CBEDF,
+0xFF8CBEDF,
+0xFF8CBEDF,
+0xFF8CBEDF,
+0xFF8CBEDF,
+0xFF8CBEDF,
+0xFF8CBEDF,
+0xFF8CBEDF,
+0xFF8BBDDE,
+0xFF8CBEDF,
+0xFF8CBEDF,
+0xFF8CBEDF,
+0xFF8CBEDF,
+0xFF8CBEDF,
+0xFF8CBEDF,
+0xFF8CBEDF,
+0xFF8BBDDE,
+0xFF8CBEDF,
+0xFF8CBEDF,
+0xFF8CBEDF,
+0xFF8CBEDF,
+0xFF8CBEDF,
+0xFF8CBEDF,
+0xFF8CBEDF,
+0xFF8CBEDF,
+0xFF8CBEDF,
+0xFF8CBEDF,
+0xFF8CBEDF,
+0xFF8BBDDE,
+0xFF8BBDDE,
+0xFF8BBDDE,
+0xFF8BBDDE,
+0xFF8BBDDE,
+0xFF8BBDDE,
+0xFF8BBDDE,
+0xFF8BBDDE,
+0xFF8BBDDE,
+0xFF8BBDDE,
+0xFF8BBDDE,
+0xFF8ABCDD,
+0xFF8ABCDD,
+0xFF8BBDDE,
+0xFF8ABCDD,
+0xFF8ABCDD,
+0xFF8ABCDD,
+0xFF87BCDC,
+0xFF87BCDC,
+0xFF87BCDE,
+0xFF87BCDE,
+0xFF86BBDD,
+0xFF86BBDD,
+0xFF86BBDD,
+0xFF86BBDD,
+0xFF86BBDD,
+0xFF85BADC,
+0xFF85BADC,
+0xFF85BADC,
+0xFF84BADC,
+0xFF83B9DB,
+0xFF83B9DB,
+0xFF83B9DB,
+0xFF83B9DB,
+0xFF83B9DB,
+0xFF83B9DB,
+0xFF83B9DB,
+0xFF82B8DA,
+0xFF82B8DA,
+0xFF82B8DA,
+0xFF81B7D9,
+0xFF81B7D9,
+0xFF80B6D8,
+0xFF80B6D8,
+0xFF7FB7D8,
+0xFF7FB7DA,
+0xFF7FB7DA,
+0xFF7EB6D9,
+0xFF7EB6D9,
+0xFF7DB5D8,
+0xFF7DB5D8,
+0xFF7AB4D9,
+0xFF7AB4D9,
+0xFF7AB4D9,
+0xFF79B3D8,
+0xFF79B3D9,
+0xFF78B2D8,
+0xFF78B2D8,
+0xFF77B1D7,
+0xFF76B2D7,
+0xFF76B2D7,
+0xFF6BA9D2,
+0xFF6CAAD3,
+0xFF6CAAD3,
+0xFF6DABD4,
+0xFF70ABD5,
+0xFF70ABD5,
+0xFF70ABD3,
+0xFF71ACD4,
+0xFF71ACD4,
+0xFF72ADD5,
+0xFF72ADD5,
+0xFF73AED6,
+0xFF74AED4,
+0xFF75AFD5,
+0xFF75AFD5,
+0xFF76B0D6,
+0xFF78AFD6,
+0xFF78AFD6,
+0xFF78AFD6,
+0xFF79B0D7,
+0xFF79B0D7,
+0xFF79B0D7,
+0xFF7AB1D8,
+0xFF7AB1D8,
+0xFF7BB3D8,
+0xFF7BB3D8,
+0xFF7BB3D8,
+0xFF7CB4D9,
+0xFF7CB4D9,
+0xFF7DB5DA,
+0xFF7DB5DA,
+0xFF7EB6DB,
+0xFF7BB5DA,
+0xFF7BB5DA,
+0xFF7EB6DB,
+0xFF7EB6DB,
+0xFF7EB6D9,
+0xFF7FB7DA,
+0xFF7FB7DA,
+0xFF7FB7DA,
+0xFF80B6DA,
+0xFF80B6DA,
+0xFF80B6DA,
+0xFF81B7DB,
+0xFF81B7D9,
+0xFF81B7D9,
+0xFF81B7D9,
+0xFF81B7D9,
+0xFF81B7D9,
+0xFF81B7D9,
+0xFF82B8DA,
+0xFF82B8DA,
+0xFF82B8DA,
+0xFF82B8DA,
+0xFF82B8DA,
+0xFF82B8DA,
+0xFF83B9DB,
+0xFF83B9DB,
+0xFF83B9DB,
+0xFF83B9DB,
+0xFF83B9DB,
+0xFF83B9DB,
+0xFF83B9DB,
+0xFF83B9DB,
+0xFF85B9DE,
+0xFF85BADC,
+0xFF84BADC,
+0xFF84BADC,
+0xFF83BBDE,
+0xFF83BBDC,
+0xFF84BADC,
+0xFF84BADC,
+0xFF85BADC,
+0xFF85BADC,
+0xFF82B8DC,
+0xFF88B9DA,
+0xFFA0C8E2,
+0xFF001928,
+0xFF0A1010,
+0xFF140D05,
+0xFF1E1109,
+0xFF2A190F,
+0xFF2C1B0B,
+0xFF402B18,
+0xFF5A3B27,
+0xFF53321F,
+0xFF533422,
+0xFF482917,
+0xFF5A3926,
+0xFF533626,
+0xFF321E17,
+0xFF1F120A,
+0xFF342D1D,
+0xFFE2DFCE,
+0xFFADAFA1,
+0xFFDBE1D5,
+0xFFC1CBC2,
+0xFFDAEBE5,
+0xFFA2BEBF,
+0xFF829FA3,
+0xFFC2D7DC,
+0xFFBACCD0,
+0xFF677679,
+0xFFB2C0C1,
+0xFF7F8B89,
+0xFF0F1D1E,
+0xFF485A66,
+0xFF283B49,
+0xFFAEBDC0,
+0xFF99A7A8,
+0xFF74858D,
+0xFF2B3E45,
+0xFF1E3137,
+0xFF26393F,
+0xFF273840,
+0xFF384953,
+0xFF142634,
+0xFF587185,
+0xFFA3C8E3,
+0xFF8BB9DA,
+0xFF87BCDE,
+0xFF81B7D9,
+0xFF87BCDC,
+0xFF8CC1E1,
+0xFF84BADE,
+0xFF8BC1E5,
+0xFF88BDDF,
+0xFF89BBDC,
+0xFF89BEDE,
+0xFF89BEDE,
+0xFF89BEDE,
+0xFF89BEDE,
+0xFF89BEDE,
+0xFF89BEDE,
+0xFF89BEDE,
+0xFF89BEDE,
+0xFF89BEDE,
+0xFF89BEDE,
+0xFF89BEDE,
+0xFF89BEDE,
+0xFF89BEDE,
+0xFF89BEDE,
+0xFF89BEDE,
+0xFF89BEDE,
+0xFF89BEDE,
+0xFF89BEDE,
+0xFF89BEDE,
+0xFF8ABFDF,
+0xFF8ABFDF,
+0xFF8ABFDF,
+0xFF8ABFDF,
+0xFF8ABFDF,
+0xFF89BEDE,
+0xFF89BEDE,
+0xFF89BEDE,
+0xFF8ABFDF,
+0xFF8ABFDF,
+0xFF8ABFDF,
+0xFF8ABFDF,
+0xFF8ABFDF,
+0xFF8CBEDF,
+0xFF8CBEDF,
+0xFF8CBEDF,
+0xFF8CBEDF,
+0xFF8CBEDF,
+0xFF8DBFE0,
+0xFF8DBFE0,
+0xFF8DBFE0,
+0xFF8EC0E1,
+0xFF8EC0E1,
+0xFF8DBFE0,
+0xFF8DBFE0,
+0xFF8DBFE0,
+0xFF8DBFE0,
+0xFF8DBFE0,
+0xFF8DC0DF,
+0xFF8EBFDF,
+0xFF8EBFDD,
+0xFF91BEDF,
+0xFF8FBDDE,
+0xFF8ABFDF,
+0xFF89C0DF,
+0xFF8ABFDF,
+0xFF8CBEDF,
+0xFF8DBEDF,
+0xFF8ABFDE,
+0xFF88C1DE,
+0xFF88C1DC,
+0xFF8AC0DC,
+0xFF8DC0DD,
+0xFF8DC0DF,
+0xFF8BC0DF,
+0xFF8BC0DF,
+0xFF90C2E3,
+0xFF8FBDE1,
+0xFF99BAD9,
+0xFFB3BCCB,
+0xFF695D5D,
+0xFF573325,
+0xFF6F4A41,
+0xFF5C505C,
+0xFFB9C0DA,
+0xFF9FB8D6,
+0xFF94B7D5,
+0xFF8FB7D0,
+0xFFC0DFF1,
+0xFFF0FBFF,
+0xFFE0EBF1,
+0xFF7F9EB2,
+0xFF8EB1C7,
+0xFFDEF3FF,
+0xFF8DA6BA,
+0xFF95BEDC,
+0xFF8CBEDF,
+0xFF91C0DC,
+0xFF8DBFD8,
+0xFF8BC1DD,
+0xFF8AC1E0,
+0xFF8AC0E4,
+0xFF8BC0E2,
+0xFF8EBFE0,
+0xFF90BEDF,
+0xFF8EBFDF,
+0xFF8DC0DF,
+0xFF8DBFE0,
+0xFF8DBFE0,
+0xFF8DBFE0,
+0xFF8DBFE0,
+0xFF8DBFE0,
+0xFF8CBEDF,
+0xFF8CBEDF,
+0xFF8CBEDF,
+0xFF8CBEDF,
+0xFF8DBFE0,
+0xFF8DBFE0,
+0xFF8DBFE0,
+0xFF8DBFE0,
+0xFF8DBFE0,
+0xFF8DBFE0,
+0xFF8CBEDF,
+0xFF8CBEDF,
+0xFF8CBEDF,
+0xFF8CBEDF,
+0xFF8CBEDF,
+0xFF8CBEDF,
+0xFF8CBEDF,
+0xFF8CBEDF,
+0xFF8CBEDF,
+0xFF8CBEDF,
+0xFF8CBEDF,
+0xFF8CBEDF,
+0xFF8CBEDF,
+0xFF8CBEDF,
+0xFF8CBEDF,
+0xFF8CBEDF,
+0xFF8CBEDF,
+0xFF8CBEDF,
+0xFF8CBEDF,
+0xFF8CBEDF,
+0xFF8CBEDF,
+0xFF8CBEDF,
+0xFF8CBEDF,
+0xFF8CBEDF,
+0xFF8CBEDF,
+0xFF8CBEDF,
+0xFF8CBEDF,
+0xFF8CBEDF,
+0xFF8CBEDF,
+0xFF8CBEDF,
+0xFF8BBDDE,
+0xFF8BBDDE,
+0xFF8BBDDE,
+0xFF8BBDDE,
+0xFF8BBDDE,
+0xFF8BBDDE,
+0xFF8BBDDE,
+0xFF89BEDE,
+0xFF88BDDD,
+0xFF88BDDF,
+0xFF88BDDF,
+0xFF88BDDF,
+0xFF87BCDE,
+0xFF87BCDE,
+0xFF87BCDE,
+0xFF87BCDE,
+0xFF87BCDE,
+0xFF86BBDD,
+0xFF86BBDD,
+0xFF85BADC,
+0xFF84BADC,
+0xFF84BADC,
+0xFF84BADC,
+0xFF84BADC,
+0xFF83B9DB,
+0xFF83B9DB,
+0xFF83B9DB,
+0xFF83B9DB,
+0xFF83B9DB,
+0xFF82B8DA,
+0xFF82B8DA,
+0xFF82B8DA,
+0xFF81B7D9,
+0xFF81B7D9,
+0xFF81B7D9,
+0xFF80B8DB,
+0xFF80B8DB,
+0xFF7FB7DA,
+0xFF7FB7DA,
+0xFF7EB6D9,
+0xFF7EB6D9,
+0xFF7BB5DA,
+0xFF7BB5DA,
+0xFF7BB5DA,
+0xFF7AB4D9,
+0xFF7AB4DA,
+0xFF79B3D9,
+0xFF79B3D9,
+0xFF78B2D8,
+0xFF77B3D8,
+0xFF77B3D8,
+0xFF6EA9D3,
+0xFF6FAAD4,
+0xFF6FAAD4,
+0xFF70ABD5,
+0xFF71ACD6,
+0xFF71ACD6,
+0xFF72ADD5,
+0xFF72ADD5,
+0xFF74AED6,
+0xFF74AED6,
+0xFF74AED4,
+0xFF75AFD5,
+0xFF75AFD5,
+0xFF76B0D6,
+0xFF76B0D6,
+0xFF76B0D6,
+0xFF78AFD6,
+0xFF79B0D7,
+0xFF79B0D7,
+0xFF79B0D7,
+0xFF7AB1D8,
+0xFF7BB2D9,
+0xFF7BB3D8,
+0xFF7BB3D8,
+0xFF7CB4D9,
+0xFF7CB4D9,
+0xFF7CB4D9,
+0xFF7DB5DA,
+0xFF7DB5DA,
+0xFF7EB6DB,
+0xFF7EB6D9,
+0xFF7EB6D9,
+0xFF7CB7D9,
+0xFF7CB7D9,
+0xFF7FB7DA,
+0xFF7FB7DA,
+0xFF80B8DB,
+0xFF80B8DB,
+0xFF80B8DB,
+0xFF80B8DB,
+0xFF81B7DB,
+0xFF81B7DB,
+0xFF82B8DA,
+0xFF82B8DA,
+0xFF82B8DA,
+0xFF82B8DA,
+0xFF83B8DA,
+0xFF83B8DA,
+0xFF82B8DA,
+0xFF82B8DA,
+0xFF83B9DB,
+0xFF83B9DB,
+0xFF83B9DB,
+0xFF83B9DB,
+0xFF83B9DB,
+0xFF83B9DB,
+0xFF83B9DB,
+0xFF83B9DB,
+0xFF83B9DB,
+0xFF83B9DB,
+0xFF84BADC,
+0xFF84BADC,
+0xFF84BADC,
+0xFF84BADC,
+0xFF85BADC,
+0xFF85BADC,
+0xFF85BADC,
+0xFF84BBDA,
+0xFF84BCDD,
+0xFF84BCDD,
+0xFF85BBDD,
+0xFF85BCDB,
+0xFF86BBDB,
+0xFF85BADC,
+0xFF83B9DD,
+0xFF8BBCDD,
+0xFF99C1DB,
+0xFF4D6776,
+0xFF000908,
+0xFF120E05,
+0xFF150600,
+0xFF311F15,
+0xFF261406,
+0xFF493423,
+0xFF583925,
+0xFF563320,
+0xFF4B2C1A,
+0xFF412210,
+0xFF593623,
+0xFF422213,
+0xFF2A160F,
+0xFF190C06,
+0xFF70685B,
+0xFFB4B2A3,
+0xFFCFD3C5,
+0xFFD8E2D9,
+0xFFC6D5CE,
+0xFFC5D8D6,
+0xFF8CA1A4,
+0xFFABBFC6,
+0xFFB3C4CB,
+0xFF4C5A5D,
+0xFFD8E0E3,
+0xFF7E888A,
+0xFF0D1F1F,
+0xFF829599,
+0xFF1B2B3B,
+0xFF2B3B4B,
+0xFFA0B2B6,
+0xFF667A79,
+0xFF556A6F,
+0xFF273A40,
+0xFF323F45,
+0xFF27363B,
+0xFF1F333C,
+0xFF072432,
+0xFF799FB6,
+0xFF9FCBE6,
+0xFF8CBBD9,
+0xFF91BFE0,
+0xFF8FBCDD,
+0xFF8FBDDE,
+0xFF8FC0E0,
+0xFF89BEDE,
+0xFF87BCDC,
+0xFF8ABFDF,
+0xFF8ABCDD,
+0xFF8BBDDE,
+0xFF8ABFDF,
+0xFF8ABFDF,
+0xFF8ABFDF,
+0xFF8ABFDF,
+0xFF8ABFDF,
+0xFF8ABFDF,
+0xFF8ABFDF,
+0xFF8ABFDF,
+0xFF8ABFDF,
+0xFF8ABFDF,
+0xFF8ABFDF,
+0xFF8ABFDF,
+0xFF8ABFDF,
+0xFF8ABFDF,
+0xFF8ABFDF,
+0xFF8ABFDF,
+0xFF8ABFDF,
+0xFF8ABFDF,
+0xFF8ABFDF,
+0xFF8ABFDF,
+0xFF8ABFDF,
+0xFF8ABFDF,
+0xFF8BC0E0,
+0xFF8BC0E0,
+0xFF8ABFDF,
+0xFF8ABFDF,
+0xFF8ABFDF,
+0xFF8ABFDF,
+0xFF8ABFDF,
+0xFF8ABFDF,
+0xFF8ABFDF,
+0xFF8ABFDF,
+0xFF8DBFE0,
+0xFF8DBFE0,
+0xFF8DBFE0,
+0xFF8DBFE0,
+0xFF8DBFE0,
+0xFF8DBFE0,
+0xFF8DBFE0,
+0xFF8DBFE0,
+0xFF8FC0E1,
+0xFF8FC0E1,
+0xFF8FC0E1,
+0xFF8FC0E1,
+0xFF8EBFE0,
+0xFF8EBFE0,
+0xFF8EBFE0,
+0xFF8DC0DF,
+0xFF8BC0DF,
+0xFF8BC1DD,
+0xFF8FBDDE,
+0xFF8FBDDF,
+0xFF8ABFE1,
+0xFF89BFE1,
+0xFF8EBEE2,
+0xFF91BDE0,
+0xFF92BDE0,
+0xFF90BEDF,
+0xFF8AC1DF,
+0xFF8AC3E0,
+0xFF8BC0DF,
+0xFF8DC0DF,
+0xFF8EBFE0,
+0xFF8DBFE2,
+0xFF8ABEE3,
+0xFF8CBEE3,
+0xFF91BFE3,
+0xFF96BFDF,
+0xFF9CC0D8,
+0xFFB7CBD4,
+0xFF69655C,
+0xFF554233,
+0xFF594338,
+0xFF655C5D,
+0xFFACC0D8,
+0xFF9CBFDD,
+0xFF98B8CF,
+0xFFCBE5F6,
+0xFFEDF7FF,
+0xFFD8E6F1,
+0xFF779AAE,
+0xFF9CC0D6,
+0xFFDCF3FF,
+0xFF8FAABB,
+0xFF93BFDC,
+0xFF8DBFE0,
+0xFF92C1DB,
+0xFF8FC1DA,
+0xFF8CC2DE,
+0xFF8AC3E1,
+0xFF8AC2E5,
+0xFF8CC0E5,
+0xFF8FC0E1,
+0xFF91BFE0,
+0xFF91C0DE,
+0xFF8FC0DE,
+0xFF8FC0E0,
+0xFF8FC0E1,
+0xFF8FC0E1,
+0xFF8FC0E1,
+0xFF8FC0E1,
+0xFF8FC0E1,
+0xFF8EBFE0,
+0xFF8EBFE0,
+0xFF8EBFE0,
+0xFF8EBFE0,
+0xFF8FC0E1,
+0xFF8FC0E1,
+0xFF8FC0E1,
+0xFF8FC0E1,
+0xFF8EBFE0,
+0xFF8EBFE0,
+0xFF8EBFE0,
+0xFF8EBFE0,
+0xFF8EBFE0,
+0xFF8EBFE0,
+0xFF8EBFE0,
+0xFF8EBFE0,
+0xFF8EBFE0,
+0xFF8EBFE0,
+0xFF8EBFE0,
+0xFF8EBFE0,
+0xFF8EBFE0,
+0xFF8EBFE0,
+0xFF8EBFE0,
+0xFF8EBFE0,
+0xFF8EBFE0,
+0xFF8EBFE0,
+0xFF8DBFE0,
+0xFF8DBFE0,
+0xFF8DBFE0,
+0xFF8DBFE0,
+0xFF8DBFE0,
+0xFF8DBFE0,
+0xFF8DBFE0,
+0xFF8DBFE0,
+0xFF8DBFE0,
+0xFF8DBFE0,
+0xFF8CBEDF,
+0xFF8CBEDF,
+0xFF8CBEDF,
+0xFF8CBEDF,
+0xFF8CBEDF,
+0xFF8CBEDF,
+0xFF8CBEDF,
+0xFF8CBEDF,
+0xFF8CBEDF,
+0xFF8CBEDF,
+0xFF8ABFDF,
+0xFF8ABFDF,
+0xFF8ABFDF,
+0xFF8ABFDF,
+0xFF89BEDE,
+0xFF89BEDE,
+0xFF89BEE0,
+0xFF88BDDF,
+0xFF88BDDF,
+0xFF88BDDF,
+0xFF8ABCDF,
+0xFF88BDDF,
+0xFF87BCDE,
+0xFF87BCDE,
+0xFF87BCDE,
+0xFF86BBDD,
+0xFF85BBDD,
+0xFF84BADC,
+0xFF84BADC,
+0xFF84BADC,
+0xFF84BADC,
+0xFF83B9DB,
+0xFF83B9DB,
+0xFF83B9DB,
+0xFF83B9DB,
+0xFF82B8DA,
+0xFF82B8DA,
+0xFF82B8DA,
+0xFF80B8DB,
+0xFF80B8DB,
+0xFF80B8DB,
+0xFF80B8DB,
+0xFF7FB7DA,
+0xFF7FB7DA,
+0xFF7EB6D9,
+0xFF7EB6D9,
+0xFF7CB6DB,
+0xFF7BB5DA,
+0xFF7BB5DA,
+0xFF7AB4D9,
+0xFF7AB4D9,
+0xFF79B3D8,
+0xFF79B3D9,
+0xFF79B3D9,
+0xFF6FAAD2,
+0xFF6FAAD2,
+0xFF70ABD3,
+0xFF71ACD4,
+0xFF72ADD5,
+0xFF72ADD5,
+0xFF72ADD5,
+0xFF73AFD4,
+0xFF75AFD7,
+0xFF75AFD5,
+0xFF75AFD5,
+0xFF75AFD4,
+0xFF76B0D6,
+0xFF76B0D5,
+0xFF76B0D6,
+0xFF77B1D7,
+0xFF79B0D7,
+0xFF79B0D7,
+0xFF7AB1D8,
+0xFF7AB1D8,
+0xFF7BB2D9,
+0xFF7BB3D8,
+0xFF7CB4D9,
+0xFF7CB4D9,
+0xFF7CB4D9,
+0xFF7CB4D9,
+0xFF7DB5DA,
+0xFF7DB5DA,
+0xFF7EB6DB,
+0xFF7EB6DB,
+0xFF7FB7DA,
+0xFF7FB7DA,
+0xFF7FB7DA,
+0xFF7DB8DA,
+0xFF80B8DB,
+0xFF80B8DB,
+0xFF80B8DB,
+0xFF81B9DA,
+0xFF81B9DC,
+0xFF81B9DA,
+0xFF82B8DC,
+0xFF82B8DA,
+0xFF82B8DA,
+0xFF83B9DB,
+0xFF83B9DB,
+0xFF83B9DB,
+0xFF84B9DB,
+0xFF84B9DB,
+0xFF83B9DB,
+0xFF83B9DB,
+0xFF83B9DB,
+0xFF83B9DB,
+0xFF84BADC,
+0xFF84BADC,
+0xFF84BADC,
+0xFF84BADC,
+0xFF84BADC,
+0xFF84BADC,
+0xFF84BADC,
+0xFF85BBDD,
+0xFF85BBDD,
+0xFF85BBDD,
+0xFF85BBDD,
+0xFF85BBDD,
+0xFF86BBDD,
+0xFF86BBDB,
+0xFF86BBDB,
+0xFF86BBDB,
+0xFF85BBDD,
+0xFF84BCDD,
+0xFF86BBDB,
+0xFF86BBDB,
+0xFF8ABCDD,
+0xFF88BADB,
+0xFF87BDE3,
+0xFF85BADC,
+0xFF8DB9D6,
+0xFFABC8DA,
+0xFF0F171A,
+0xFF0D0802,
+0xFF120500,
+0xFF33221A,
+0xFF1D0B00,
+0xFF452F21,
+0xFF513122,
+0xFF502F1C,
+0xFF462715,
+0xFF3C1F0D,
+0xFF583925,
+0xFF381D0C,
+0xFF220F09,
+0xFF6B605C,
+0xFFC5C1B6,
+0xFF55574A,
+0xFFA7AFA4,
+0xFFB0BDB4,
+0xFFBAC9C4,
+0xFFBBCBCA,
+0xFF96A5AA,
+0xFFCDDEE5,
+0xFF91A0A7,
+0xFFEBF8FE,
+0xFF99A0A8,
+0xFF091217,
+0xFF53686B,
+0xFF263E42,
+0xFF243443,
+0xFF495764,
+0xFF5E7273,
+0xFF2F4543,
+0xFF1D3235,
+0xFF23383D,
+0xFF1D3037,
+0xFF142833,
+0xFF294654,
+0xFF92B8CB,
+0xFF96C5E1,
+0xFF88BDDD,
+0xFF8CBEDF,
+0xFF8FBDDE,
+0xFF92BDDD,
+0xFF8FBCDB,
+0xFF89BADA,
+0xFF8EC0E1,
+0xFF8ABFDE,
+0xFF8BC0DF,
+0xFF8CBEDF,
+0xFF8DBFE0,
+0xFF8CBEDF,
+0xFF8ABFDF,
+0xFF8ABFDF,
+0xFF8ABFDF,
+0xFF8ABFDF,
+0xFF8ABFDF,
+0xFF8ABFDF,
+0xFF8ABFDF,
+0xFF8ABFDF,
+0xFF8ABFDF,
+0xFF8CBEDF,
+0xFF8BC0E0,
+0xFF8DBFE0,
+0xFF8BC0E0,
+0xFF8DBFE0,
+0xFF8BC0E0,
+0xFF8ABFDF,
+0xFF8ABFDF,
+0xFF8ABFDF,
+0xFF8ABFDF,
+0xFF8BC0E0,
+0xFF8BC0E0,
+0xFF8DBFE0,
+0xFF8BC0E0,
+0xFF8DBFE0,
+0xFF8BC0E0,
+0xFF8DBFE0,
+0xFF8BC0E0,
+0xFF8DBFE0,
+0xFF8BC0E0,
+0xFF8DBFE0,
+0xFF8DBFE0,
+0xFF8DBFE0,
+0xFF8DBFE0,
+0xFF8DBFE0,
+0xFF8DBFE0,
+0xFF8DBFE0,
+0xFF8DBFE0,
+0xFF8DBFE0,
+0xFF8DBFE0,
+0xFF8EBFE0,
+0xFF8EBFE0,
+0xFF8EBFE0,
+0xFF8EBFDF,
+0xFF8EBFE0,
+0xFF8EBFDF,
+0xFF8EBFE0,
+0xFF8DC0DF,
+0xFF8BC0DF,
+0xFF8CC1E0,
+0xFF91BFE0,
+0xFF92C0E2,
+0xFF8DC2E2,
+0xFF8FC1E2,
+0xFF91BFE1,
+0xFF93BEE1,
+0xFF95BDE1,
+0xFF92BFE0,
+0xFF8EC1E0,
+0xFF8DC2E1,
+0xFF8EC1E0,
+0xFF8FC0E0,
+0xFF91BFE0,
+0xFF8EBFE0,
+0xFF8FC1E6,
+0xFF90C2E7,
+0xFF8FBCE3,
+0xFF92BEE1,
+0xFF92BFDC,
+0xFF9ABFD1,
+0xFFB5C8CC,
+0xFF6B6C64,
+0xFF564535,
+0xFF4B3A30,
+0xFF676E76,
+0xFFB4C7D8,
+0xFF9FB6C6,
+0xFFD3E6F5,
+0xFFEEFAFF,
+0xFFC5D5E4,
+0xFF7596A9,
+0xFFA6CBDD,
+0xFFDBF5FF,
+0xFF91AEBE,
+0xFF93C1DB,
+0xFF8EC1E0,
+0xFF90C2DB,
+0xFF8FC1D8,
+0xFF8EC1DC,
+0xFF8CC1E0,
+0xFF8EC0E5,
+0xFF8EC0E5,
+0xFF8FC0E0,
+0xFF91C0DE,
+0xFF91C0DC,
+0xFF91C0DC,
+0xFF90C1E1,
+0xFF90C1E2,
+0xFF90C1E2,
+0xFF90C1E2,
+0xFF90C1E2,
+0xFF90C1E2,
+0xFF8FC0E1,
+0xFF8FC0E1,
+0xFF8FC0E1,
+0xFF8FC0E1,
+0xFF8FC0E1,
+0xFF8FC0E1,
+0xFF8FC0E1,
+0xFF8FC0E1,
+0xFF8FC0E1,
+0xFF8FC0E1,
+0xFF90C1E2,
+0xFF8FC0E1,
+0xFF8FC0E1,
+0xFF8FC0E1,
+0xFF8FC0E1,
+0xFF8FC0E1,
+0xFF8FC0E1,
+0xFF8FC0E1,
+0xFF8FC0E1,
+0xFF8FC0E1,
+0xFF8FC0E1,
+0xFF8FC0E1,
+0xFF8FC0E1,
+0xFF8FC0E1,
+0xFF8FC0E1,
+0xFF8FC0E1,
+0xFF8DBFE0,
+0xFF8DBFE0,
+0xFF8DBFE0,
+0xFF8DC0DF,
+0xFF8DBFE0,
+0xFF8DC0DF,
+0xFF8EBFE0,
+0xFF8DC0DF,
+0xFF8DBEDF,
+0xFF8CBEDF,
+0xFF8DBEDF,
+0xFF8DBFE0,
+0xFF8DBFE0,
+0xFF8DBFE0,
+0xFF8DBFE0,
+0xFF8DBFE0,
+0xFF8DBFE0,
+0xFF8DBFE0,
+0xFF8EBFE0,
+0xFF8DBFE0,
+0xFF8DBFE0,
+0xFF8DBFE0,
+0xFF8DBFE0,
+0xFF8DBFE0,
+0xFF8CBEDF,
+0xFF8CBEDF,
+0xFF8CBEE1,
+0xFF8BBDE0,
+0xFF8BBDE0,
+0xFF8BBDE0,
+0xFF8BBDE0,
+0xFF8BBDE0,
+0xFF8BBDE0,
+0xFF89BEDE,
+0xFF8ABCDF,
+0xFF88BDDD,
+0xFF87BCDE,
+0xFF86BCDE,
+0xFF86BBDD,
+0xFF85BBDD,
+0xFF84BADC,
+0xFF84BADC,
+0xFF84BADC,
+0xFF84BADC,
+0xFF83B9DB,
+0xFF83B9DB,
+0xFF83B9DB,
+0xFF83B9DB,
+0xFF81B9DC,
+0xFF81B9DC,
+0xFF81B9DC,
+0xFF80B8DB,
+0xFF80B8DB,
+0xFF7FB7DA,
+0xFF7FB7DA,
+0xFF7EB6D9,
+0xFF7EB6D9,
+0xFF7CB6DB,
+0xFF7CB6DB,
+0xFF7BB5DA,
+0xFF7AB4D9,
+0xFF7AB4D9,
+0xFF7AB4D9,
+0xFF7AB4D9,
+0xFF70ACD1,
+0xFF70ACD1,
+0xFF70ACD1,
+0xFF71ADD2,
+0xFF72AED3,
+0xFF73AFD4,
+0xFF75AFD5,
+0xFF74AED3,
+0xFF75AFD5,
+0xFF75AFD4,
+0xFF76B0D5,
+0xFF76B1D3,
+0xFF79B1D6,
+0xFF79B1D4,
+0xFF7AB2D7,
+0xFF7AB2D7,
+0xFF78B2D7,
+0xFF78B2D7,
+0xFF79B3D8,
+0xFF7AB4D9,
+0xFF7CB4D9,
+0xFF7DB5DA,
+0xFF7DB5DA,
+0xFF7DB5D8,
+0xFF7EB6D9,
+0xFF7EB6D9,
+0xFF7EB6D9,
+0xFF7FB7DA,
+0xFF80B6DA,
+0xFF80B6DA,
+0xFF81B7DB,
+0xFF80B8DB,
+0xFF80B8D9,
+0xFF80B8D9,
+0xFF80B8D9,
+0xFF81B9DA,
+0xFF82B8DA,
+0xFF82B9D8,
+0xFF82B8DA,
+0xFF83BAD9,
+0xFF84BADC,
+0xFF84BBDA,
+0xFF84BBDA,
+0xFF84BBDA,
+0xFF84BBDA,
+0xFF84BBDA,
+0xFF84BBDA,
+0xFF84BBDA,
+0xFF85BCDB,
+0xFF85BCDB,
+0xFF85BCDB,
+0xFF85BCDB,
+0xFF85BCDB,
+0xFF85BCDB,
+0xFF85BCDB,
+0xFF85BCDB,
+0xFF86BBDB,
+0xFF86BBDB,
+0xFF86BBDB,
+0xFF87BCDC,
+0xFF87BCDC,
+0xFF87BCDC,
+0xFF87BCDC,
+0xFF87BCDC,
+0xFF87BCDC,
+0xFF87BCDC,
+0xFF89BBDC,
+0xFF89BBDC,
+0xFF86BCDE,
+0xFF86BCDE,
+0xFF89BBDC,
+0xFF8CBADB,
+0xFF8DBADB,
+0xFF8BBCDD,
+0xFF86BEE3,
+0xFF84BCE1,
+0xFF8DC0DF,
+0xFFA7CADE,
+0xFF141D24,
+0xFF0E0808,
+0xFF0D0200,
+0xFF271813,
+0xFF291610,
+0xFF2D160E,
+0xFF482C20,
+0xFF482819,
+0xFF412412,
+0xFF6E533E,
+0xFF7E654F,
+0xFF210E00,
+0xFF291C13,
+0xFF2F2822,
+0xFF4E4F49,
+0xFF5F665F,
+0xFFDEEBE4,
+0xFFCDDCD5,
+0xFFBBC7C3,
+0xFFB9C5C3,
+0xFFA1AFB0,
+0xFFAEBDC2,
+0xFFDAEBF2,
+0xFF9DAEB8,
+0xFF0A1B25,
+0xFF30414B,
+0xFF80949B,
+0xFF2D4247,
+0xFF293C42,
+0xFF243638,
+0xFF253737,
+0xFF213333,
+0xFF1F3135,
+0xFF152B36,
+0xFF102F41,
+0xFF6D93AA,
+0xFFA5CDE6,
+0xFF97C3DC,
+0xFF8ABCD7,
+0xFF8EC1E0,
+0xFF8DC0DF,
+0xFF8DBEDE,
+0xFF8EBFDF,
+0xFF8EBFDF,
+0xFF8CBEDF,
+0xFF8CBEDF,
+0xFF8CBEDF,
+0xFF8CBEDF,
+0xFF8DBEDF,
+0xFF8CBEDF,
+0xFF8CBEDF,
+0xFF8CBEDF,
+0xFF8CBEDF,
+0xFF8CBEDF,
+0xFF8DBFE0,
+0xFF8DBFE0,
+0xFF8DBFE0,
+0xFF8DBFE0,
+0xFF8CBEDF,
+0xFF8CBEDF,
+0xFF8DBEDF,
+0xFF8CBEDF,
+0xFF8DBEDF,
+0xFF8DBFE0,
+0xFF8EBFE0,
+0xFF8DBFE0,
+0xFF8DC0DF,
+0xFF8DC0DF,
+0xFF8DC0DF,
+0xFF8DC0DF,
+0xFF8DC0DF,
+0xFF8DC0DF,
+0xFF8EBFDF,
+0xFF8DC0DF,
+0xFF8FC0E0,
+0xFF8EC1E0,
+0xFF8FC0E0,
+0xFF8EC1E0,
+0xFF8FC0E0,
+0xFF8EC1E0,
+0xFF8FC0E0,
+0xFF8FC0E0,
+0xFF8FC0E0,
+0xFF8FC0E0,
+0xFF8FC0E0,
+0xFF8FC0E0,
+0xFF8FC0E0,
+0xFF8FC0E0,
+0xFF8FC0E0,
+0xFF8FC0E0,
+0xFF8FC0E0,
+0xFF8FC0E0,
+0xFF8FC0E0,
+0xFF8FC0DE,
+0xFF8FC0E0,
+0xFF8FC0DE,
+0xFF8FC0E0,
+0xFF90C1E1,
+0xFF8FC0E0,
+0xFF90C1E1,
+0xFF92C0E1,
+0xFF92C0E1,
+0xFF90C1E1,
+0xFF90C1E1,
+0xFF92C0E1,
+0xFF93C0E1,
+0xFF93C0E1,
+0xFF92C1DF,
+0xFF90C1DF,
+0xFF90C1DF,
+0xFF90C1DF,
+0xFF92C1DF,
+0xFF92C1DF,
+0xFF92C1DF,
+0xFF91C0DE,
+0xFF8FC0E0,
+0xFF90C1E9,
+0xFF91C1E7,
+0xFF95BEDC,
+0xFF99BED8,
+0xFF9CC5DB,
+0xFFACC8D6,
+0xFF6C6C6A,
+0xFF433528,
+0xFF554536,
+0xFF7C736A,
+0xFFB6BFC4,
+0xFFDCEEFA,
+0xFFEDFAFF,
+0xFFBACBDD,
+0xFF7B98A6,
+0xFFBEE0EC,
+0xFFDCF6FF,
+0xFF8FAEC0,
+0xFF94C3DD,
+0xFF8DC3DF,
+0xFF91C4DF,
+0xFF90C2D9,
+0xFF93C1D9,
+0xFF94C0DD,
+0xFF96BDE4,
+0xFF93BFE4,
+0xFF8FC2DF,
+0xFF8DC3DB,
+0xFF90C2D9,
+0xFF90C2D9,
+0xFF92C1DF,
+0xFF92C0E1,
+0xFF92C0E1,
+0xFF92C0E1,
+0xFF91BFE0,
+0xFF91BFE0,
+0xFF91BFE0,
+0xFF91BFE0,
+0xFF92C0E1,
+0xFF92C0E1,
+0xFF92C0E1,
+0xFF92C0E1,
+0xFF92C0E1,
+0xFF92C0E1,
+0xFF92C0E1,
+0xFF92C0E1,
+0xFF90C1E1,
+0xFF90C1E1,
+0xFF90C1E1,
+0xFF90C1E1,
+0xFF90C1E1,
+0xFF90C1E1,
+0xFF90C1E1,
+0xFF90C1E1,
+0xFF90C1E1,
+0xFF8FC0E0,
+0xFF8FC0E0,
+0xFF8FC0E0,
+0xFF8EC1E0,
+0xFF8EC1E0,
+0xFF8EC1E0,
+0xFF8EC1E0,
+0xFF8FC0E0,
+0xFF8FC0E0,
+0xFF8FC0E0,
+0xFF8FC0DE,
+0xFF8FC0E0,
+0xFF8FC0DE,
+0xFF91BFE0,
+0xFF8FC0DE,
+0xFF91BFE0,
+0xFF8FC0E0,
+0xFF91BFE0,
+0xFF8FC0E0,
+0xFF8FC0E1,
+0xFF8FC0E1,
+0xFF8FC0E1,
+0xFF8FC0E1,
+0xFF8FC0E0,
+0xFF8FC0E0,
+0xFF91BFE0,
+0xFF8FC0E0,
+0xFF8FC0E0,
+0xFF8EBFDF,
+0xFF8EBFDF,
+0xFF8EBFDF,
+0xFF8EBFE0,
+0xFF8EBFE0,
+0xFF8EBFE0,
+0xFF8EBFE0,
+0xFF8EBFE0,
+0xFF8EBFE0,
+0xFF8EBFE0,
+0xFF8EBFE0,
+0xFF8DBEDF,
+0xFF8CBFDE,
+0xFF8DBEDF,
+0xFF8BBEDD,
+0xFF8BBDDE,
+0xFF88BDDD,
+0xFF8ABCDD,
+0xFF88BDDD,
+0xFF88BDDD,
+0xFF87BCDC,
+0xFF87BCDC,
+0xFF86BBDB,
+0xFF84BBDA,
+0xFF84BBDA,
+0xFF84BADC,
+0xFF85BBDD,
+0xFF83B9DB,
+0xFF83B9DB,
+0xFF83B9DB,
+0xFF82B8DA,
+0xFF82B8DA,
+0xFF81B7D9,
+0xFF81B7D9,
+0xFF81B7D9,
+0xFF81B7D9,
+0xFF7FB7DA,
+0xFF7FB7DA,
+0xFF7EB6D9,
+0xFF7EB6D9,
+0xFF7EB6D9,
+0xFF7DB5D8,
+0xFF7CB4D7,
+0xFF73ADD3,
+0xFF72AED3,
+0xFF73ADD3,
+0xFF73AFD4,
+0xFF75AFD5,
+0xFF76B0D5,
+0xFF76B0D6,
+0xFF75AFD4,
+0xFF78AFD6,
+0xFF76B0D5,
+0xFF78B0D5,
+0xFF79B1D6,
+0xFF79B1D6,
+0xFF7AB2D5,
+0xFF7BB1D7,
+0xFF7AB2D7,
+0xFF7AB2D7,
+0xFF79B3D8,
+0xFF79B3D8,
+0xFF7AB4D9,
+0xFF7DB5DA,
+0xFF7DB5DA,
+0xFF7DB5D8,
+0xFF7EB6D9,
+0xFF7EB6D9,
+0xFF7EB6D9,
+0xFF7FB7DA,
+0xFF7FB7DA,
+0xFF81B7DB,
+0xFF81B7DB,
+0xFF81B7DB,
+0xFF81B7DB,
+0xFF81B7D9,
+0xFF81B9DA,
+0xFF82B8DA,
+0xFF82B8DA,
+0xFF82B9D8,
+0xFF83BAD9,
+0xFF83BAD9,
+0xFF83BAD9,
+0xFF84BBDA,
+0xFF84BBDA,
+0xFF84BBDA,
+0xFF84BBDA,
+0xFF85BCDB,
+0xFF85BCDB,
+0xFF85BCDB,
+0xFF85BCDB,
+0xFF85BCDB,
+0xFF85BCDB,
+0xFF85BCDB,
+0xFF85BCDB,
+0xFF85BCDB,
+0xFF85BCDB,
+0xFF86BBDB,
+0xFF86BBDB,
+0xFF87BCDC,
+0xFF87BCDC,
+0xFF87BCDC,
+0xFF87BCDC,
+0xFF87BCDC,
+0xFF87BCDC,
+0xFF88BDDD,
+0xFF88BDDD,
+0xFF88BDDD,
+0xFF8ABCDD,
+0xFF8BBCDC,
+0xFF8ABCDD,
+0xFF87BDDF,
+0xFF87BEDD,
+0xFF8ABCDD,
+0xFF8DBBDC,
+0xFF92BDDD,
+0xFF8CBADB,
+0xFF85BDE2,
+0xFF87C1E6,
+0xFF88BDDD,
+0xFF9CC2D9,
+0xFF313D49,
+0xFF0B090C,
+0xFF080202,
+0xFF1A0F0B,
+0xFF36231D,
+0xFF351C15,
+0xFF391D11,
+0xFF341707,
+0xFF684D38,
+0xFF957F68,
+0xFF2D1B07,
+0xFF241707,
+0xFF1A1108,
+0xFF201D18,
+0xFF333532,
+0xFF828B8A,
+0xFFCDDCD9,
+0xFFCEDEDB,
+0xFFCAD9D6,
+0xFFD2DEDC,
+0xFF95A3A3,
+0xFFB1C0C3,
+0xFFA9BAC1,
+0xFF14272E,
+0xFF2F414D,
+0xFF6F818D,
+0xFF24373E,
+0xFF283B41,
+0xFF2A3E3D,
+0xFF253938,
+0xFF1B2F30,
+0xFF172A30,
+0xFF1E303A,
+0xFF637D8E,
+0xFFA4C9E3,
+0xFF9AC7E4,
+0xFF8FBEDA,
+0xFF8CBBD7,
+0xFF90C1DF,
+0xFF8EBFDD,
+0xFF8ABDDC,
+0xFF8FC2E1,
+0xFF8DBFE0,
+0xFF8DBFE0,
+0xFF8DBFE0,
+0xFF8DBFE0,
+0xFF8DBFE0,
+0xFF8DBFE0,
+0xFF8EBFE0,
+0xFF8EBFE0,
+0xFF8DBFE0,
+0xFF8DBFE0,
+0xFF8DBFE0,
+0xFF8DBFE0,
+0xFF8DBFE0,
+0xFF8DBFE0,
+0xFF8EC0E1,
+0xFF8EC0E1,
+0xFF8FC0E1,
+0xFF8FC0E1,
+0xFF8FC0E1,
+0xFF8FC0E0,
+0xFF8FC0E1,
+0xFF8FC0E0,
+0xFF8FC0E1,
+0xFF8FC0E0,
+0xFF8FC0E0,
+0xFF8EC1E0,
+0xFF8EC1E0,
+0xFF8EC1E0,
+0xFF8FC0E0,
+0xFF8FC0E0,
+0xFF8FC0E0,
+0xFF8FC0E0,
+0xFF8FC0E0,
+0xFF8FC0E0,
+0xFF90C1E1,
+0xFF90C1E1,
+0xFF90C1E1,
+0xFF90C1E1,
+0xFF90C1E1,
+0xFF90C1E1,
+0xFF8FC0E0,
+0xFF8FC0E0,
+0xFF8FC0E0,
+0xFF90C1E1,
+0xFF90C1E1,
+0xFF90C1E1,
+0xFF90C1E1,
+0xFF90C1E1,
+0xFF90C1E1,
+0xFF90C1E1,
+0xFF90C1DF,
+0xFF90C1DF,
+0xFF90C1DF,
+0xFF90C1DF,
+0xFF90C1DF,
+0xFF90C1DF,
+0xFF92C0E1,
+0xFF92C0E1,
+0xFF92C0E1,
+0xFF92C0E1,
+0xFF92C0E1,
+0xFF92C0E1,
+0xFF92C1DF,
+0xFF92C1DF,
+0xFF92C1DF,
+0xFF92C1DF,
+0xFF93C2E0,
+0xFF93C2E0,
+0xFF93C2E0,
+0xFF93C2E0,
+0xFF93C2E0,
+0xFF93C2DE,
+0xFF94C4DB,
+0xFF92C4DF,
+0xFF91C3E8,
+0xFF92C2E8,
+0xFF96BFDF,
+0xFF96BFDD,
+0xFF91C3E4,
+0xFF9AC3DF,
+0xFFB4C8D3,
+0xFF93948F,
+0xFF493A27,
+0xFF988871,
+0xFF7B7567,
+0xFFFAFFF9,
+0xFFEBF6FC,
+0xFFB2C4D2,
+0xFF8198A6,
+0xFFD2ECFB,
+0xFFDBF2FF,
+0xFF94B3C7,
+0xFF96C4DE,
+0xFF8CC1E0,
+0xFF8EC4E0,
+0xFF92C4DF,
+0xFF95C2D9,
+0xFF98C0DA,
+0xFF98BEE3,
+0xFF95BFE5,
+0xFF90C3E2,
+0xFF8DC5DE,
+0xFF91C3DA,
+0xFF93C3DA,
+0xFF93C2E0,
+0xFF93C1E2,
+0xFF93C1E2,
+0xFF93C1E2,
+0xFF93C1E2,
+0xFF93C1E2,
+0xFF93C1E2,
+0xFF93C1E2,
+0xFF93C1E2,
+0xFF93C1E2,
+0xFF93C1E2,
+0xFF93C1E2,
+0xFF92C0E1,
+0xFF92C0E1,
+0xFF93C1E2,
+0xFF93C1E2,
+0xFF90C1E1,
+0xFF90C1E1,
+0xFF90C1E1,
+0xFF90C1E1,
+0xFF90C1E1,
+0xFF90C1E1,
+0xFF90C1E1,
+0xFF90C1E1,
+0xFF90C1E1,
+0xFF90C1E1,
+0xFF90C1E1,
+0xFF90C1E1,
+0xFF90C1E1,
+0xFF8FC2E1,
+0xFF90C1E1,
+0xFF90C1E1,
+0xFF90C1E1,
+0xFF90C1E1,
+0xFF90C1DF,
+0xFF90C1DF,
+0xFF92C1DF,
+0xFF92C1DF,
+0xFF92C1DF,
+0xFF91C0DE,
+0xFF92C1DF,
+0xFF91C0DE,
+0xFF91BFE0,
+0xFF91BFE0,
+0xFF8FC0E1,
+0xFF8FC0E1,
+0xFF8FC0E1,
+0xFF8FC0E1,
+0xFF91BFE0,
+0xFF91BFE0,
+0xFF91BFE0,
+0xFF91BFE0,
+0xFF91BFE0,
+0xFF91BFE0,
+0xFF91BFE0,
+0xFF91BFE0,
+0xFF91BFE1,
+0xFF91BFE1,
+0xFF91BFE1,
+0xFF91BFE1,
+0xFF91BFE1,
+0xFF91BFE1,
+0xFF91BFE1,
+0xFF91BFE1,
+0xFF8EBFDF,
+0xFF8EBFDF,
+0xFF8EBFDF,
+0xFF8DBEDE,
+0xFF8CBFDE,
+0xFF8BBEDD,
+0xFF8BBDDE,
+0xFF8ABCDD,
+0xFF88BDDD,
+0xFF88BDDD,
+0xFF87BCDC,
+0xFF86BBDB,
+0xFF85BCDB,
+0xFF84BBDA,
+0xFF84BADC,
+0xFF84BADC,
+0xFF84BADC,
+0xFF84BADC,
+0xFF83B9DB,
+0xFF83B9DB,
+0xFF83B9DB,
+0xFF83B9DB,
+0xFF82B8DA,
+0xFF82B8DA,
+0xFF82B8DA,
+0xFF81B7D9,
+0xFF80B8DB,
+0xFF7FB7DA,
+0xFF7FB7DA,
+0xFF7EB6D9,
+0xFF7EB6D9,
+0xFF7DB5D8,
+0xFF78AFD8,
+0xFF75AFD7,
+0xFF77AED7,
+0xFF76B0D8,
+0xFF78AFD8,
+0xFF79B0D7,
+0xFF78AFD8,
+0xFF78AFD6,
+0xFF7AAFD9,
+0xFF79B0D7,
+0xFF7AAFD7,
+0xFF7BB0D8,
+0xFF7BB0D8,
+0xFF7CB2D8,
+0xFF7DB1D9,
+0xFF7CB2D8,
+0xFF7CB4D9,
+0xFF7CB4D7,
+0xFF7DB5D8,
+0xFF7DB5D8,
+0xFF7EB6D9,
+0xFF7EB6D9,
+0xFF80B6DA,
+0xFF80B6DA,
+0xFF80B6D8,
+0xFF81B7D9,
+0xFF81B7D9,
+0xFF81B7D9,
+0xFF82B8DA,
+0xFF82B8DA,
+0xFF83B8DA,
+0xFF83B8DA,
+0xFF84B9DB,
+0xFF83B9DB,
+0xFF84B9DB,
+0xFF84B9DB,
+0xFF84B9D9,
+0xFF85BADA,
+0xFF85BADA,
+0xFF85BADA,
+0xFF86BBDB,
+0xFF86BBDB,
+0xFF86BBDB,
+0xFF86BBDB,
+0xFF87BCDC,
+0xFF87BCDC,
+0xFF87BCDC,
+0xFF87BCDC,
+0xFF87BCDC,
+0xFF87BCDC,
+0xFF87BCDC,
+0xFF87BCDC,
+0xFF87BCDC,
+0xFF87BCDC,
+0xFF89BBDC,
+0xFF8ABCDD,
+0xFF8ABCDD,
+0xFF8ABCDD,
+0xFF8ABCDD,
+0xFF8ABCDD,
+0xFF8ABCDD,
+0xFF8ABCDD,
+0xFF8BBDDE,
+0xFF8BBDDE,
+0xFF88BDDC,
+0xFF8BBEDD,
+0xFF8CBDDE,
+0xFF8CBDDE,
+0xFF89BEE0,
+0xFF88BFDE,
+0xFF8BBDDE,
+0xFF8EBCDD,
+0xFF90BBDB,
+0xFF8DBADB,
+0xFF8AC0E4,
+0xFF87BFE2,
+0xFF8ABFDF,
+0xFFA1C9E2,
+0xFF40505F,
+0xFF02050A,
+0xFF090909,
+0xFF0D0802,
+0xFF322117,
+0xFF563F2F,
+0xFF331702,
+0xFF3A1E08,
+0xFF351C06,
+0xFF261400,
+0xFF170B00,
+0xFF191106,
+0xFF201B15,
+0xFF272622,
+0xFF535756,
+0xFFA0AAAB,
+0xFFB6C5C8,
+0xFFACC0C1,
+0xFFAFC1C1,
+0xFFC9D9D9,
+0xFF93A6A4,
+0xFFBACCCC,
+0xFF849899,
+0xFF829599,
+0xFF6F8185,
+0xFF24363A,
+0xFF2C3B40,
+0xFF2B3A3D,
+0xFF2B3B3B,
+0xFF233537,
+0xFF374B52,
+0xFF768C9A,
+0xFFA7BDD4,
+0xFFA4C2DC,
+0xFF98C1DD,
+0xFF90BFDB,
+0xFF92C1DF,
+0xFF94C3E1,
+0xFF8FC0DE,
+0xFF8EBFDD,
+0xFF8EBFDF,
+0xFF8EBFDF,
+0xFF8EC0E1,
+0xFF8EC0E1,
+0xFF8EC0E1,
+0xFF8EC0E1,
+0xFF8EC0E1,
+0xFF8EC0E1,
+0xFF90C1E2,
+0xFF90C1E2,
+0xFF8FC0E0,
+0xFF8FC0E0,
+0xFF8FC0E0,
+0xFF8FC0E0,
+0xFF8FC0E0,
+0xFF8FC0E0,
+0xFF8FC0E0,
+0xFF90C1E1,
+0xFF90C1E1,
+0xFF90C1E1,
+0xFF90C1E1,
+0xFF90C1DF,
+0xFF92C0E1,
+0xFF92C1DF,
+0xFF92C0E1,
+0xFF90C1DF,
+0xFF90C1DF,
+0xFF90C1DF,
+0xFF90C1DF,
+0xFF90C1DF,
+0xFF90C1DF,
+0xFF90C1DF,
+0xFF90C1DF,
+0xFF90C1DF,
+0xFF92C1DF,
+0xFF92C1DF,
+0xFF93C2E0,
+0xFF93C2E0,
+0xFF93C2E0,
+0xFF93C2E0,
+0xFF93C2E0,
+0xFF93C2E0,
+0xFF92C0E1,
+0xFF92C0E1,
+0xFF92C0E1,
+0xFF93C1E2,
+0xFF93C1E2,
+0xFF93C1E2,
+0xFF93C2E0,
+0xFF93C2E0,
+0xFF93C2E0,
+0xFF93C2E0,
+0xFF93C2E0,
+0xFF93C2E0,
+0xFF93C2E0,
+0xFF93C2E0,
+0xFF93C2E0,
+0xFF93C2E0,
+0xFF93C2E0,
+0xFF93C2E0,
+0xFF93C2E0,
+0xFF93C2E0,
+0xFF93C2E0,
+0xFF93C2E0,
+0xFF93C2E0,
+0xFF93C2E0,
+0xFF93C2E0,
+0xFF93C2E0,
+0xFF93C2E0,
+0xFF94C3E1,
+0xFF94C3E1,
+0xFF94C3E1,
+0xFF94C3E1,
+0xFF92C4DF,
+0xFF92C5DA,
+0xFF90C4D9,
+0xFF91C2E0,
+0xFF92C3E4,
+0xFF95C1E6,
+0xFF94C2E6,
+0xFF91C1E5,
+0xFF94C1E2,
+0xFF9BC0DB,
+0xFFAEC8D7,
+0xFFA1AAA7,
+0xFF88806B,
+0xFFAD976E,
+0xFFBBA981,
+0xFFFEFFF3,
+0xFFAAB9BE,
+0xFF92A3B5,
+0xFFDEF0FF,
+0xFFE1F1FF,
+0xFF94ACC4,
+0xFF98BFDC,
+0xFF90BEE0,
+0xFF91C3E6,
+0xFF91C2E3,
+0xFF94C4DB,
+0xFF95C3DB,
+0xFF95C2E1,
+0xFF94C2E4,
+0xFF91C3E8,
+0xFF8FC4E6,
+0xFF94C3E1,
+0xFF94C3DF,
+0xFF94C3E1,
+0xFF94C3E1,
+0xFF93C2E0,
+0xFF93C2E0,
+0xFF93C2E0,
+0xFF93C2E0,
+0xFF93C2E0,
+0xFF93C2E0,
+0xFF94C3E1,
+0xFF94C3E1,
+0xFF93C2E0,
+0xFF93C2E0,
+0xFF93C2E0,
+0xFF93C2E0,
+0xFF93C2E0,
+0xFF93C2E0,
+0xFF93C2E0,
+0xFF93C2E0,
+0xFF93C2E0,
+0xFF93C2E0,
+0xFF93C2E0,
+0xFF93C2E0,
+0xFF93C2E0,
+0xFF93C2E0,
+0xFF93C2E0,
+0xFF93C2E0,
+0xFF93C2E0,
+0xFF93C2E0,
+0xFF93C2E0,
+0xFF91C2E0,
+0xFF93C1E2,
+0xFF93C1E2,
+0xFF93C2E0,
+0xFF93C2E0,
+0xFF93C2E0,
+0xFF93C2E0,
+0xFF93C2E0,
+0xFF93C2E0,
+0xFF93C2E0,
+0xFF92C1DF,
+0xFF92C1DF,
+0xFF92C1DF,
+0xFF92C1DF,
+0xFF92C1DF,
+0xFF92C0E1,
+0xFF92C0E1,
+0xFF90C1E2,
+0xFF90C1E2,
+0xFF92C0E1,
+0xFF92C0E1,
+0xFF92C0E1,
+0xFF92C0E1,
+0xFF92C0E1,
+0xFF92C0E1,
+0xFF92C0E1,
+0xFF92C0E1,
+0xFF92C0E1,
+0xFF92C0E1,
+0xFF92C0E1,
+0xFF92C0E1,
+0xFF92C0E1,
+0xFF92C0E1,
+0xFF92C0E1,
+0xFF92C0E1,
+0xFF90C1E1,
+0xFF8FC0E0,
+0xFF8FC0E0,
+0xFF8EBFDF,
+0xFF8EBFDF,
+0xFF8DBEDE,
+0xFF8CBEDF,
+0xFF8CBEDF,
+0xFF8BBDDE,
+0xFF8BBDDE,
+0xFF88BDDD,
+0xFF88BDDD,
+0xFF87BCDC,
+0xFF87BCDC,
+0xFF86BBDD,
+0xFF86BBDD,
+0xFF86BBDB,
+0xFF86BBDB,
+0xFF86BBDB,
+0xFF85BADA,
+0xFF84BADC,
+0xFF84BADC,
+0xFF84BADC,
+0xFF84BADC,
+0xFF83B9DB,
+0xFF82B8DA,
+0xFF82B8DA,
+0xFF81B7D9,
+0xFF80B8DB,
+0xFF80B8DB,
+0xFF7FB7DA,
+0xFF7EB6D9,
+0xFF78AEDA,
+0xFF78AEDA,
+0xFF78AEDA,
+0xFF78AEDA,
+0xFF78AFD8,
+0xFF79B0D9,
+0xFF79B0D9,
+0xFF7AAFD9,
+0xFF7BB0DA,
+0xFF7BB0DA,
+0xFF7BB0DA,
+0xFF7CB1DB,
+0xFF7CB1D9,
+0xFF7CB1D9,
+0xFF7DB1D9,
+0xFF7DB3D9,
+0xFF7EB4D8,
+0xFF7EB6D9,
+0xFF7EB6D9,
+0xFF7FB7DA,
+0xFF7FB7DA,
+0xFF80B8DB,
+0xFF81B7DB,
+0xFF81B7DB,
+0xFF81B7D9,
+0xFF81B7D9,
+0xFF82B8DA,
+0xFF82B8DA,
+0xFF83B9DB,
+0xFF83B9DB,
+0xFF84B9DB,
+0xFF84B9DB,
+0xFF85BADC,
+0xFF85BADC,
+0xFF85BADC,
+0xFF86BBDD,
+0xFF86BBDB,
+0xFF86BBDB,
+0xFF86BBDB,
+0xFF87BCDC,
+0xFF87BCDC,
+0xFF87BCDC,
+0xFF87BCDC,
+0xFF87BCDC,
+0xFF89BBDC,
+0xFF88BDDD,
+0xFF8ABCDD,
+0xFF88BDDD,
+0xFF8ABCDD,
+0xFF88BDDD,
+0xFF8ABCDD,
+0xFF8BBDDE,
+0xFF8BBDDE,
+0xFF8BBDDE,
+0xFF8BBDDE,
+0xFF8BBDDE,
+0xFF8BBDDE,
+0xFF8BBDDE,
+0xFF8BBDDE,
+0xFF8BBDDE,
+0xFF8BBDDE,
+0xFF8BBDDE,
+0xFF8BBDDE,
+0xFF8CBEDF,
+0xFF8BBEDD,
+0xFF8BBEDD,
+0xFF8FBDDF,
+0xFF8DBEDF,
+0xFF8ABFE1,
+0xFF8ABFE1,
+0xFF8BC0E0,
+0xFF8EBFDD,
+0xFF92BEDB,
+0xFF90BDDC,
+0xFF8DC2E4,
+0xFF86BCE0,
+0xFF89BEDE,
+0xFF98C2DB,
+0xFF5E7585,
+0xFF000C14,
+0xFF4D565B,
+0xFF060805,
+0xFF1C130A,
+0xFF685648,
+0xFF5D4430,
+0xFF482F1B,
+0xFF251400,
+0xFF251909,
+0xFF221C10,
+0xFF221F18,
+0xFF1B1A16,
+0xFF313330,
+0xFF888E8E,
+0xFFDEEAEA,
+0xFFB5C7C9,
+0xFF90A5A8,
+0xFFA2B5B9,
+0xFFBBCFD0,
+0xFF869A99,
+0xFF869A99,
+0xFF778B8A,
+0xFF415554,
+0xFF384848,
+0xFF2E3C3D,
+0xFF323D3F,
+0xFF354042,
+0xFF2D3B3C,
+0xFF15272B,
+0xFF4A5D6B,
+0xFFB4CDE1,
+0xFFA1BFDB,
+0xFF99BCDC,
+0xFF96C2DF,
+0xFF8FBEDA,
+0xFF91C0DE,
+0xFF93C2E0,
+0xFF8FC0DE,
+0xFF91C2E0,
+0xFF92C3E3,
+0xFF8FC0E0,
+0xFF8EC0E1,
+0xFF8EC0E1,
+0xFF8EC0E1,
+0xFF8FC1E2,
+0xFF8FC1E2,
+0xFF8FC1E2,
+0xFF90C1E2,
+0xFF90C1E1,
+0xFF90C1E1,
+0xFF90C1E1,
+0xFF90C1E1,
+0xFF90C1E1,
+0xFF90C1E1,
+0xFF90C1E1,
+0xFF90C1E1,
+0xFF90C1E1,
+0xFF90C1E1,
+0xFF90C1DF,
+0xFF90C1DF,
+0xFF90C1DF,
+0xFF92C1DF,
+0xFF92C1DF,
+0xFF92C1DF,
+0xFF93C2E0,
+0xFF91C2E0,
+0xFF91C2E0,
+0xFF91C2E0,
+0xFF91C2E0,
+0xFF91C2E0,
+0xFF91C2E0,
+0xFF91C2E0,
+0xFF91C2E0,
+0xFF93C2E0,
+0xFF93C2E0,
+0xFF93C2E0,
+0xFF93C2E0,
+0xFF93C2E0,
+0xFF93C2E0,
+0xFF93C2E0,
+0xFF93C2E0,
+0xFF93C1E2,
+0xFF93C1E2,
+0xFF93C1E2,
+0xFF93C1E2,
+0xFF93C1E2,
+0xFF93C1E2,
+0xFF94C3E1,
+0xFF94C3E1,
+0xFF94C3E1,
+0xFF94C3E1,
+0xFF94C3E1,
+0xFF94C3E1,
+0xFF94C3E1,
+0xFF94C3E1,
+0xFF94C3E1,
+0xFF94C3E1,
+0xFF93C2E0,
+0xFF93C2E0,
+0xFF93C2E0,
+0xFF93C2E0,
+0xFF93C2E0,
+0xFF93C2E0,
+0xFF94C3E1,
+0xFF94C3E1,
+0xFF94C3E1,
+0xFF94C3E1,
+0xFF94C3E1,
+0xFF94C3E1,
+0xFF94C3E1,
+0xFF94C3E1,
+0xFF94C3E1,
+0xFF92C4DD,
+0xFF90C4D9,
+0xFF90C4D9,
+0xFF91C3DC,
+0xFF92C3E1,
+0xFF93C4E5,
+0xFF93C4E5,
+0xFF92C3E4,
+0xFF94C2E3,
+0xFF97C4E5,
+0xFF95BDD7,
+0xFFA6C2CE,
+0xFFA6B0A7,
+0xFF7D6E47,
+0xFFA89263,
+0xFFCDC7A7,
+0xFFBCC0B2,
+0xFFA4ABB1,
+0xFFE6F1FF,
+0xFFE4F1FF,
+0xFF97ABC4,
+0xFF9BBFDF,
+0xFF9AC6E9,
+0xFF99C7EB,
+0xFF8FC0E1,
+0xFF91C5DD,
+0xFF91C5DB,
+0xFF94C3DD,
+0xFF94C3E1,
+0xFF92C2E8,
+0xFF92C2E8,
+0xFF94C2E3,
+0xFF94C3DF,
+0xFF94C3E1,
+0xFF94C3E1,
+0xFF94C3E1,
+0xFF94C3E1,
+0xFF94C3E1,
+0xFF94C3E1,
+0xFF94C3E1,
+0xFF94C3E1,
+0xFF94C3E1,
+0xFF94C3E1,
+0xFF94C3E1,
+0xFF94C3E1,
+0xFF94C3E1,
+0xFF94C3E1,
+0xFF94C3E1,
+0xFF94C3E1,
+0xFF94C3E1,
+0xFF94C3E1,
+0xFF94C3E1,
+0xFF94C3E1,
+0xFF94C3E1,
+0xFF94C3E1,
+0xFF94C3E1,
+0xFF94C3E1,
+0xFF94C3E1,
+0xFF94C3E1,
+0xFF95C2E1,
+0xFF94C3E1,
+0xFF95C2E1,
+0xFF95C2E1,
+0xFF95C2E1,
+0xFF95C2E1,
+0xFF94C3E1,
+0xFF94C3E1,
+0xFF94C3E1,
+0xFF93C2E0,
+0xFF93C2E0,
+0xFF93C2E0,
+0xFF93C2E0,
+0xFF93C2E0,
+0xFF93C2E0,
+0xFF93C2E0,
+0xFF93C2E0,
+0xFF93C2E0,
+0xFF93C1E2,
+0xFF93C1E2,
+0xFF90C1E2,
+0xFF90C1E1,
+0xFF93C1E2,
+0xFF93C1E2,
+0xFF93C1E2,
+0xFF93C1E2,
+0xFF93C1E2,
+0xFF93C1E2,
+0xFF93C1E2,
+0xFF93C1E2,
+0xFF92C0E1,
+0xFF92C0E1,
+0xFF92C0E1,
+0xFF92C0E1,
+0xFF92C0E1,
+0xFF92C0E1,
+0xFF92C0E1,
+0xFF92C0E1,
+0xFF90C1E1,
+0xFF90C1E1,
+0xFF8FC0E0,
+0xFF8FC0E0,
+0xFF8FC0E0,
+0xFF8FC0E0,
+0xFF8EBFE0,
+0xFF8DBFE0,
+0xFF8CBEDF,
+0xFF8CBEDF,
+0xFF8CBEDF,
+0xFF8ABFDF,
+0xFF8ABFDF,
+0xFF89BEDE,
+0xFF88BDDF,
+0xFF88BDDF,
+0xFF87BCDC,
+0xFF87BCDC,
+0xFF87BCDC,
+0xFF87BCDC,
+0xFF85BBDD,
+0xFF85BBDD,
+0xFF85BBDD,
+0xFF85BBDD,
+0xFF84BADC,
+0xFF83B9DB,
+0xFF83B9DB,
+0xFF82B8DA,
+0xFF81B9DC,
+0xFF81B9DC,
+0xFF80B8DB,
+0xFF7FB7DA,
+0xFF75AFD7,
+0xFF76B0D8,
+0xFF76B0D8,
+0xFF76B0D8,
+0xFF77B1D9,
+0xFF77B1D9,
+0xFF77B1D9,
+0xFF7AB1DA,
+0xFF7BB2D9,
+0xFF7BB2D9,
+0xFF7BB2D9,
+0xFF7BB2D9,
+0xFF7CB3DA,
+0xFF7CB3DA,
+0xFF7DB2DA,
+0xFF7EB4DA,
+0xFF7FB5D9,
+0xFF7FB5D7,
+0xFF80B6D8,
+0xFF81B7D9,
+0xFF81B7D9,
+0xFF81B7D9,
+0xFF82B8DA,
+0xFF82B8DA,
+0xFF83B8DA,
+0xFF83B8DA,
+0xFF84B9D9,
+0xFF84B9D9,
+0xFF84B9D9,
+0xFF85BADA,
+0xFF85BADA,
+0xFF85BADA,
+0xFF88BADB,
+0xFF88BADB,
+0xFF88BADB,
+0xFF89BBDC,
+0xFF89BBDC,
+0xFF89BBDC,
+0xFF89BBDC,
+0xFF89BBDC,
+0xFF89BBDC,
+0xFF89BBDC,
+0xFF8ABCDD,
+0xFF8ABCDD,
+0xFF8BBCDD,
+0xFF8BBDDE,
+0xFF8CBDDE,
+0xFF8BBDDE,
+0xFF8CBDDE,
+0xFF8BBDDE,
+0xFF8CBDDE,
+0xFF8DBEDF,
+0xFF8DBEDF,
+0xFF8DBEDF,
+0xFF8DBEDF,
+0xFF8DBEDF,
+0xFF8DBEDF,
+0xFF8DBEDF,
+0xFF8DBEDF,
+0xFF8DBEDF,
+0xFF8DBEDF,
+0xFF8DBEDF,
+0xFF8DBEDF,
+0xFF8CBEDF,
+0xFF8CBFDE,
+0xFF8CBFDE,
+0xFF90BEE0,
+0xFF90BEE0,
+0xFF8DBFE2,
+0xFF8BC0E2,
+0xFF8BC0E0,
+0xFF8EC1DE,
+0xFF90BDDA,
+0xFF93C0DF,
+0xFF8BBDDE,
+0xFF8DC2E4,
+0xFF92C4E5,
+0xFF93BFDC,
+0xFFA6C2D7,
+0xFF2E4452,
+0xFF233947,
+0xFF001018,
+0xFF000405,
+0xFF716A64,
+0xFF4B3D32,
+0xFF4F4134,
+0xFF160C00,
+0xFF757165,
+0xFF24251D,
+0xFF1E231D,
+0xFF2A302E,
+0xFF262F2C,
+0xFF535D5C,
+0xFF859491,
+0xFFACBFBD,
+0xFFD0E6E4,
+0xFFC0D5D8,
+0xFFA8BDC2,
+0xFF7D9293,
+0xFF718785,
+0xFF3F5553,
+0xFF2B3F3D,
+0xFF2A3A39,
+0xFF2D3939,
+0xFF2E3839,
+0xFF232D2E,
+0xFF111C1E,
+0xFF132229,
+0xFF001523,
+0xFFA3BFD7,
+0xFF9BBEDE,
+0xFF96BEE2,
+0xFF93C0DF,
+0xFF90BFDD,
+0xFF90BFDD,
+0xFF91C0DE,
+0xFF91C2E0,
+0xFF8FC0DE,
+0xFF90C1E1,
+0xFF92C3E3,
+0xFF90C1E1,
+0xFF90C1E1,
+0xFF90C1E1,
+0xFF91C2E2,
+0xFF91C2E2,
+0xFF91C2E2,
+0xFF91C2E2,
+0xFF91C2E2,
+0xFF92C0E1,
+0xFF92C1DF,
+0xFF92C1DF,
+0xFF92C1DF,
+0xFF93C2E0,
+0xFF93C2E0,
+0xFF93C2E0,
+0xFF93C2E0,
+0xFF94C3E1,
+0xFF94C3DF,
+0xFF94C3DF,
+0xFF94C3DF,
+0xFF94C3DF,
+0xFF94C3DF,
+0xFF94C3DF,
+0xFF94C3DF,
+0xFF93C2DE,
+0xFF93C2DE,
+0xFF93C2DE,
+0xFF94C3DF,
+0xFF94C3DF,
+0xFF94C3DF,
+0xFF94C3DF,
+0xFF94C3DF,
+0xFF93C2DE,
+0xFF94C3DF,
+0xFF94C3DF,
+0xFF94C3DF,
+0xFF95C2DF,
+0xFF95C2DF,
+0xFF95C2DF,
+0xFF95C2DF,
+0xFF94C1E0,
+0xFF94C1E0,
+0xFF95C2E1,
+0xFF95C2E1,
+0xFF95C2E1,
+0xFF95C2E1,
+0xFF95C2E1,
+0xFF95C2E1,
+0xFF95C2E1,
+0xFF95C2E1,
+0xFF95C2DF,
+0xFF95C2DF,
+0xFF95C2DF,
+0xFF95C2DF,
+0xFF95C2DF,
+0xFF95C2DF,
+0xFF94C3E1,
+0xFF94C3E1,
+0xFF94C3E1,
+0xFF94C3E1,
+0xFF94C3E1,
+0xFF94C3E1,
+0xFF94C3E1,
+0xFF94C3E1,
+0xFF95C4E0,
+0xFF95C4E0,
+0xFF95C4E0,
+0xFF95C4E0,
+0xFF95C4E0,
+0xFF95C4E0,
+0xFF95C4E0,
+0xFF95C4DE,
+0xFF93C6DB,
+0xFF93C5DC,
+0xFF93C5E0,
+0xFF92C5E0,
+0xFF92C6DC,
+0xFF92C6DB,
+0xFF91C5DD,
+0xFF94C3DF,
+0xFF93BFDC,
+0xFF9BC4E0,
+0xFF96C2DB,
+0xFFA4C6D2,
+0xFFBAC5BD,
+0xFF827C62,
+0xFF9D875E,
+0xFFDBC8A0,
+0xFFC1BCA8,
+0xFFF2F7F3,
+0xFFE6EEF9,
+0xFF9BADC5,
+0xFF98BFDE,
+0xFF97C5E7,
+0xFF91BEDF,
+0xFF99C8E6,
+0xFF8EC8E0,
+0xFF8EC8DE,
+0xFF92C4DB,
+0xFF95C3DD,
+0xFF94C2E3,
+0xFF94C2E3,
+0xFF95C4E0,
+0xFF95C4DE,
+0xFF95C4E0,
+0xFF95C4E0,
+0xFF95C4E0,
+0xFF95C4E0,
+0xFF95C4E0,
+0xFF95C4E0,
+0xFF95C4E0,
+0xFF95C4E0,
+0xFF95C4E0,
+0xFF95C4E0,
+0xFF94C3DF,
+0xFF94C3DF,
+0xFF94C3DF,
+0xFF94C3DF,
+0xFF94C3DF,
+0xFF94C3DF,
+0xFF96C3E0,
+0xFF96C3E0,
+0xFF96C3E0,
+0xFF96C3E0,
+0xFF96C3E0,
+0xFF96C3E0,
+0xFF96C3E0,
+0xFF96C3E0,
+0xFF96C3E0,
+0xFF96C3E0,
+0xFF96C2DF,
+0xFF95C2DF,
+0xFF96C2DF,
+0xFF96C2DF,
+0xFF96C2DF,
+0xFF96C2DF,
+0xFF96C3E0,
+0xFF94C3DF,
+0xFF94C3DF,
+0xFF94C3DF,
+0xFF94C3DF,
+0xFF94C3DF,
+0xFF94C3DF,
+0xFF94C3DF,
+0xFF94C3DF,
+0xFF94C3DF,
+0xFF94C3E1,
+0xFF94C3E1,
+0xFF94C3E1,
+0xFF94C3E1,
+0xFF93C1E2,
+0xFF93C1E2,
+0xFF94C2E3,
+0xFF94C3E1,
+0xFF94C3E1,
+0xFF93C2E0,
+0xFF93C2E0,
+0xFF93C2E0,
+0xFF93C2E0,
+0xFF93C2E0,
+0xFF92C1DF,
+0xFF92C1DF,
+0xFF92C0E1,
+0xFF92C0E1,
+0xFF92C0E1,
+0xFF92C0E1,
+0xFF92C0E1,
+0xFF92C0E1,
+0xFF92C0E1,
+0xFF92C0E1,
+0xFF92C0E1,
+0xFF92C0E1,
+0xFF92C0E1,
+0xFF90C1E1,
+0xFF90C1E2,
+0xFF90C1E2,
+0xFF8EBFE0,
+0xFF8DBFE0,
+0xFF8EC0E1,
+0xFF8EC0E1,
+0xFF8DBFE0,
+0xFF8CBEDF,
+0xFF8BBDDE,
+0xFF8BBDDE,
+0xFF89BEDE,
+0xFF88BDDD,
+0xFF88BDDD,
+0xFF87BCDC,
+0xFF87BCDC,
+0xFF86BBDB,
+0xFF86BBDB,
+0xFF86BBDB,
+0xFF84BADC,
+0xFF84BADC,
+0xFF83B9DB,
+0xFF83B9DB,
+0xFF83B9DB,
+0xFF83B9DB,
+0xFF82B8DA,
+0xFF81B7D9,
+0xFF76B0D6,
+0xFF76B0D6,
+0xFF77B1D7,
+0xFF77B1D7,
+0xFF77B1D7,
+0xFF78B2D8,
+0xFF79B3D9,
+0xFF7BB2D9,
+0xFF7BB2D9,
+0xFF7CB4D9,
+0xFF7CB4D9,
+0xFF7DB5DA,
+0xFF7DB5DA,
+0xFF7EB6DB,
+0xFF7EB6DB,
+0xFF7EB6DB,
+0xFF80B6DA,
+0xFF80B6D8,
+0xFF81B7D9,
+0xFF81B7D9,
+0xFF82B8DA,
+0xFF82B8DA,
+0xFF82B8DA,
+0xFF82B8DA,
+0xFF84B9DB,
+0xFF84B9DB,
+0xFF84B9D9,
+0xFF85BADA,
+0xFF85BADA,
+0xFF86BBDB,
+0xFF86BBDB,
+0xFF86BBDB,
+0xFF88BADB,
+0xFF89BBDC,
+0xFF89BBDC,
+0xFF89BBDC,
+0xFF89BBDC,
+0xFF8ABCDD,
+0xFF8ABCDD,
+0xFF8ABCDD,
+0xFF8ABCDD,
+0xFF8BBDDE,
+0xFF8CBDDE,
+0xFF8CBDDE,
+0xFF8CBDDE,
+0xFF8DBEDF,
+0xFF8DBEDF,
+0xFF8DBEDF,
+0xFF8DBEDF,
+0xFF8DBEDF,
+0xFF8DBEDF,
+0xFF8DBEDF,
+0xFF8EBFE0,
+0xFF8EBFE0,
+0xFF8EBFE0,
+0xFF8EBFE0,
+0xFF8EBFE0,
+0xFF8EBFE0,
+0xFF8EBFE0,
+0xFF8EBFE0,
+0xFF8FC0E1,
+0xFF8FC0E1,
+0xFF8FC0E1,
+0xFF8FC0E0,
+0xFF8EC1DE,
+0xFF8FC0DE,
+0xFF91BFE0,
+0xFF91BFE1,
+0xFF8EC0E5,
+0xFF8CC1E3,
+0xFF8CC1E1,
+0xFF8EC1DE,
+0xFF93C0DD,
+0xFF93C0DD,
+0xFF94C2E3,
+0xFF8CBDDE,
+0xFF90C2E3,
+0xFF90BDDC,
+0xFF95B9D1,
+0xFFAACADF,
+0xFFACCFE5,
+0xFFAECADF,
+0xFF9BADBB,
+0xFF616A71,
+0xFF3B3C3E,
+0xFF201F1B,
+0xFF171812,
+0xFF61665F,
+0xFF1F2823,
+0xFF242F2B,
+0xFF2C3836,
+0xFF263232,
+0xFF7C8B88,
+0xFFE3F3F0,
+0xFFA9BCB6,
+0xFF9BAFAD,
+0xFFAABFC2,
+0xFF9DB5B9,
+0xFF71898B,
+0xFF809898,
+0xFF4D6565,
+0xFF233736,
+0xFF2D3D3D,
+0xFF222D2F,
+0xFF242C2F,
+0xFF10181B,
+0xFF1C252A,
+0xFF1D2B34,
+0xFF162D3D,
+0xFF55758C,
+0xFF9EC5E6,
+0xFF96C2E5,
+0xFF94C2E3,
+0xFF97C6E4,
+0xFF93C2E0,
+0xFF90BFDD,
+0xFF93C4E2,
+0xFF94C5E3,
+0xFF91C2E2,
+0xFF90C1E1,
+0xFF92C3E3,
+0xFF92C3E3,
+0xFF92C3E3,
+0xFF92C3E3,
+0xFF92C3E3,
+0xFF92C3E3,
+0xFF92C3E3,
+0xFF92C3E1,
+0xFF93C2E0,
+0xFF93C2E0,
+0xFF93C2E0,
+0xFF93C2E0,
+0xFF93C2E0,
+0xFF93C2E0,
+0xFF93C2E0,
+0xFF93C2E0,
+0xFF94C3DF,
+0xFF94C3DF,
+0xFF94C3DF,
+0xFF94C3DF,
+0xFF94C3DF,
+0xFF94C3DF,
+0xFF94C3DF,
+0xFF94C3DF,
+0xFF94C3DF,
+0xFF94C3DF,
+0xFF94C3DF,
+0xFF94C3DF,
+0xFF94C3DF,
+0xFF94C3DF,
+0xFF94C3DF,
+0xFF94C3DF,
+0xFF94C3DF,
+0xFF94C3DF,
+0xFF94C3DF,
+0xFF95C4E0,
+0xFF96C3E0,
+0xFF96C3E0,
+0xFF96C3E0,
+0xFF95C2DF,
+0xFF95C2E1,
+0xFF95C2E1,
+0xFF95C2E1,
+0xFF95C2E1,
+0xFF95C2E1,
+0xFF96C3E2,
+0xFF96C3E2,
+0xFF96C3E2,
+0xFF96C3E2,
+0xFF96C3E2,
+0xFF96C3E0,
+0xFF96C3E0,
+0xFF96C3E0,
+0xFF96C3E0,
+0xFF96C3E0,
+0xFF96C3E0,
+0xFF95C4E2,
+0xFF95C4E2,
+0xFF95C4E2,
+0xFF95C4E2,
+0xFF95C4E2,
+0xFF95C4E2,
+0xFF95C4E2,
+0xFF95C4E2,
+0xFF95C4E0,
+0xFF95C4E0,
+0xFF95C4E0,
+0xFF95C4E0,
+0xFF95C4E0,
+0xFF96C5E1,
+0xFF96C5E1,
+0xFF96C5DF,
+0xFF98C6DE,
+0xFF98C6DE,
+0xFF94C6E1,
+0xFF92C5E0,
+0xFF93C6D9,
+0xFF92C7D7,
+0xFF93C7DC,
+0xFF94C6DD,
+0xFF99C5DE,
+0xFF9DC9E4,
+0xFF93C4E4,
+0xFF93BFD8,
+0xFFBFD7E1,
+0xFFFAFFF6,
+0xFFB8A587,
+0xFF7F6542,
+0xFFCAB69B,
+0xFFFFF4E6,
+0xFFF3F3F5,
+0xFF95A5B5,
+0xFF9FC4DF,
+0xFF94C2E3,
+0xFFA0CBEB,
+0xFF90BDDA,
+0xFF90C8E1,
+0xFF8FC9DF,
+0xFF97C5DD,
+0xFF9AC4DD,
+0xFF98C3E3,
+0xFF97C4E3,
+0xFF96C5E1,
+0xFF94C6DF,
+0xFF96C5DF,
+0xFF96C5E1,
+0xFF96C5E1,
+0xFF96C5E1,
+0xFF96C5E1,
+0xFF96C5E1,
+0xFF95C4E0,
+0xFF95C4E0,
+0xFF96C5E1,
+0xFF96C5E1,
+0xFF95C4E0,
+0xFF95C4E0,
+0xFF95C4E0,
+0xFF95C4E0,
+0xFF95C4E0,
+0xFF95C4E0,
+0xFF96C3E0,
+0xFF96C3E0,
+0xFF96C3E0,
+0xFF96C3E0,
+0xFF96C3E0,
+0xFF96C3E0,
+0xFF96C3E0,
+0xFF96C3E0,
+0xFF97C3E0,
+0xFF97C3E0,
+0xFF97C3E0,
+0xFF97C3E0,
+0xFF97C3E0,
+0xFF99C2E0,
+0xFF99C2E0,
+0xFF99C2E0,
+0xFF97C4E1,
+0xFF95C4E0,
+0xFF95C4E0,
+0xFF94C3DF,
+0xFF94C3DF,
+0xFF94C3DF,
+0xFF95C4E0,
+0xFF95C4E0,
+0xFF95C4E0,
+0xFF95C4E0,
+0xFF95C4E2,
+0xFF95C4E2,
+0xFF95C4E2,
+0xFF94C3E1,
+0xFF94C2E3,
+0xFF94C3E1,
+0xFF95C4E2,
+0xFF95C4E2,
+0xFF94C3E1,
+0xFF94C3E1,
+0xFF94C3E1,
+0xFF93C2E0,
+0xFF93C2E0,
+0xFF93C2E0,
+0xFF93C2E0,
+0xFF93C2E0,
+0xFF93C1E2,
+0xFF93C1E2,
+0xFF93C1E2,
+0xFF93C1E2,
+0xFF92C0E1,
+0xFF92C0E1,
+0xFF92C0E1,
+0xFF92C0E1,
+0xFF92C0E1,
+0xFF92C0E1,
+0xFF92C0E1,
+0xFF92C0E1,
+0xFF90C1E2,
+0xFF90C1E2,
+0xFF8FC0E1,
+0xFF8FC0E1,
+0xFF8FC0E1,
+0xFF8EC0E1,
+0xFF8EC0E1,
+0xFF8DBFE0,
+0xFF8CBEDF,
+0xFF8BBDDE,
+0xFF8CBEDF,
+0xFF89BEDE,
+0xFF89BEDE,
+0xFF88BDDD,
+0xFF88BDDD,
+0xFF87BCDC,
+0xFF86BBDB,
+0xFF86BBDB,
+0xFF85BBDD,
+0xFF85BBDD,
+0xFF84BADC,
+0xFF84BADC,
+0xFF84BADC,
+0xFF84BADC,
+0xFF83B9DB,
+0xFF82B8DA,
+0xFF78B0D5,
+0xFF79B1D6,
+0xFF7AB2D7,
+0xFF7AB2D7,
+0xFF7AB2D7,
+0xFF7BB3D8,
+0xFF7BB3D8,
+0xFF7DB3D7,
+0xFF7DB3D7,
+0xFF7EB4D8,
+0xFF7EB4D8,
+0xFF7FB5D9,
+0xFF80B6DA,
+0xFF80B6DA,
+0xFF81B7DB,
+0xFF81B7DB,
+0xFF81B7D9,
+0xFF81B7D9,
+0xFF82B8DA,
+0xFF82B8DA,
+0xFF83B9DB,
+0xFF83B9DB,
+0xFF83B9DB,
+0xFF83B9DB,
+0xFF85BADA,
+0xFF85BADA,
+0xFF86BBDB,
+0xFF86BBDB,
+0xFF86BBDB,
+0xFF87BCDC,
+0xFF87BCDC,
+0xFF87BCDC,
+0xFF8ABCDD,
+0xFF8ABCDD,
+0xFF8ABCDD,
+0xFF8ABCDD,
+0xFF8BBCDD,
+0xFF8CBDDE,
+0xFF8CBDDD,
+0xFF8CBDDD,
+0xFF8DBEDE,
+0xFF8DBEDE,
+0xFF8DBEDE,
+0xFF8EBFDF,
+0xFF8EBFDF,
+0xFF8EBFDF,
+0xFF8EBFDF,
+0xFF8FC0E0,
+0xFF8EBFDF,
+0xFF8FC0E0,
+0xFF8FC0E0,
+0xFF8FC0E0,
+0xFF8FC0E0,
+0xFF90C1E1,
+0xFF90C1E1,
+0xFF90C1E1,
+0xFF92C0E1,
+0xFF92C0E1,
+0xFF92C0E1,
+0xFF92C0E1,
+0xFF92C0E1,
+0xFF92C0E1,
+0xFF92C0E1,
+0xFF90C1DF,
+0xFF8FC2DD,
+0xFF90C2DD,
+0xFF93C0E1,
+0xFF93BFE2,
+0xFF90C0E6,
+0xFF8FC1E4,
+0xFF8DC2E1,
+0xFF8FC2DD,
+0xFF8FBDD7,
+0xFF97C3DE,
+0xFF90BDDC,
+0xFF97C5E6,
+0xFF8CBDDE,
+0xFF97C5E6,
+0xFF99C2DE,
+0xFF99C2DE,
+0xFF94BFDF,
+0xFF9CC5E5,
+0xFF9DC0DC,
+0xFFA8C4DA,
+0xFFB7CDDB,
+0xFFBACBD3,
+0xFF121D21,
+0xFF626E6E,
+0xFF576565,
+0xFF2B3939,
+0xFF304040,
+0xFF2B3D3D,
+0xFF8B9E9C,
+0xFF7A8D89,
+0xFFA3B4AC,
+0xFFACBFB9,
+0xFFB1C4C8,
+0xFF9EB5BB,
+0xFF566F73,
+0xFF4E676B,
+0xFF334C50,
+0xFF475C61,
+0xFF26373E,
+0xFF263039,
+0xFF333A42,
+0xFF131720,
+0xFF2C333B,
+0xFF223039,
+0xFF193340,
+0xFF2F5265,
+0xFFA8D4ED,
+0xFF8FBEDC,
+0xFF90BFDD,
+0xFF92C1DF,
+0xFF95C4E2,
+0xFF97C6E4,
+0xFF95C4E2,
+0xFF90BFDD,
+0xFF91C0DE,
+0xFF98C7E5,
+0xFF92C3E1,
+0xFF92C3E1,
+0xFF92C3E1,
+0xFF92C3E1,
+0xFF92C3E1,
+0xFF92C3E1,
+0xFF92C3E1,
+0xFF92C3E1,
+0xFF94C3E1,
+0xFF94C3E1,
+0xFF94C3DF,
+0xFF94C3DF,
+0xFF94C3DF,
+0xFF94C3DF,
+0xFF94C3DF,
+0xFF94C3DF,
+0xFF94C3DF,
+0xFF94C3DF,
+0xFF94C3DF,
+0xFF94C3DF,
+0xFF94C3DF,
+0xFF94C3DF,
+0xFF94C3DF,
+0xFF94C3DF,
+0xFF95C4E0,
+0xFF95C4E0,
+0xFF95C4E0,
+0xFF95C4E0,
+0xFF95C4E0,
+0xFF95C4E0,
+0xFF95C4E0,
+0xFF95C4E0,
+0xFF95C4E0,
+0xFF95C4E0,
+0xFF95C4E0,
+0xFF95C4E0,
+0xFF96C5E1,
+0xFF96C5E1,
+0xFF95C4E0,
+0xFF95C4E0,
+0xFF95C4E0,
+0xFF95C4E0,
+0xFF95C4E0,
+0xFF95C4E0,
+0xFF95C4E0,
+0xFF96C5E1,
+0xFF96C5E1,
+0xFF96C5E1,
+0xFF96C5E1,
+0xFF96C5E1,
+0xFF96C5E1,
+0xFF96C5E1,
+0xFF96C5E1,
+0xFF96C5E1,
+0xFF96C5E1,
+0xFF96C5E1,
+0xFF96C5E1,
+0xFF96C5E1,
+0xFF96C5E1,
+0xFF96C5E1,
+0xFF96C5E1,
+0xFF96C5E1,
+0xFF96C5E1,
+0xFF96C5E1,
+0xFF96C5E1,
+0xFF96C5E1,
+0xFF96C5DF,
+0xFF96C5DF,
+0xFF96C5DF,
+0xFF96C5DF,
+0xFF97C6E0,
+0xFF98C6E0,
+0xFF9AC3DF,
+0xFF9BC4E0,
+0xFF98C6E0,
+0xFF94C6DF,
+0xFF96C5DF,
+0xFF95C7DE,
+0xFF93CADF,
+0xFF95C9DE,
+0xFF94C4D8,
+0xFF95C3DA,
+0xFF98C7E3,
+0xFF99C1DA,
+0xFFC1D9E5,
+0xFFEFFAFE,
+0xFFE0E0E2,
+0xFFAE9F9A,
+0xFF502B19,
+0xFF825F4C,
+0xFFEBDED8,
+0xFFA7B2B8,
+0xFFA4C4D9,
+0xFF98C4E1,
+0xFF96BEE1,
+0xFF9CC7E9,
+0xFF95C7E2,
+0xFF95C7E0,
+0xFF9BC5DE,
+0xFF9EC3E0,
+0xFF9CC2E6,
+0xFF99C4E6,
+0xFF97C6E4,
+0xFF95C7E0,
+0xFF96C5DF,
+0xFF97C5DF,
+0xFF97C5DF,
+0xFF97C5DF,
+0xFF97C5DF,
+0xFF97C5DF,
+0xFF97C5DF,
+0xFF97C5DF,
+0xFF98C6E0,
+0xFF98C6E0,
+0xFF98C6E0,
+0xFF98C6E0,
+0xFF97C5DF,
+0xFF97C5DF,
+0xFF98C6E0,
+0xFF98C6E0,
+0xFF97C5DF,
+0xFF97C5DF,
+0xFF97C5DF,
+0xFF97C5DF,
+0xFF97C5DF,
+0xFF97C5DF,
+0xFF97C5DF,
+0xFF97C5DF,
+0xFF98C4DF,
+0xFF98C4DF,
+0xFF9AC3DF,
+0xFF9AC3DF,
+0xFF9BC4E0,
+0xFF9CC3E0,
+0xFF9CC3E0,
+0xFF9CC5E1,
+0xFF99C5E0,
+0xFF97C5DF,
+0xFF97C5DF,
+0xFF96C4DE,
+0xFF96C4DE,
+0xFF96C4DE,
+0xFF96C5DF,
+0xFF96C5DF,
+0xFF96C5E1,
+0xFF96C5E1,
+0xFF95C4E0,
+0xFF95C4E0,
+0xFF95C4E0,
+0xFF95C4E0,
+0xFF95C4E2,
+0xFF95C4E2,
+0xFF95C4E2,
+0xFF95C4E0,
+0xFF95C4E0,
+0xFF95C4E0,
+0xFF95C4E0,
+0xFF94C3DF,
+0xFF94C3DF,
+0xFF94C3DF,
+0xFF94C3E1,
+0xFF94C3E1,
+0xFF94C3E1,
+0xFF94C3E1,
+0xFF94C3E1,
+0xFF94C3E1,
+0xFF93C2E0,
+0xFF93C2E0,
+0xFF94C1E0,
+0xFF94C1E0,
+0xFF94C1E2,
+0xFF94C1E2,
+0xFF93C1E2,
+0xFF93C1E2,
+0xFF92C0E1,
+0xFF92C0E1,
+0xFF92C0E1,
+0xFF90C1E1,
+0xFF90C1E2,
+0xFF90C1E2,
+0xFF8FC0E1,
+0xFF8EBFE0,
+0xFF8EBFE0,
+0xFF8CBEDF,
+0xFF8CBFDE,
+0xFF8CBFDE,
+0xFF8BBEDD,
+0xFF8BBEDD,
+0xFF8ABDDC,
+0xFF8ABDDC,
+0xFF88BDDD,
+0xFF87BCDC,
+0xFF87BCDC,
+0xFF87BCDC,
+0xFF86BBDB,
+0xFF86BBDB,
+0xFF86BBDB,
+0xFF86BBDB,
+0xFF85BADC,
+0xFF84B9DB,
+0xFF7AB0D4,
+0xFF7BB1D5,
+0xFF7BB1D5,
+0xFF7CB2D6,
+0xFF7CB2D6,
+0xFF7CB2D6,
+0xFF7DB3D7,
+0xFF7DB3D7,
+0xFF7FB4D6,
+0xFF7FB4D6,
+0xFF80B5D7,
+0xFF81B6D8,
+0xFF82B7D9,
+0xFF82B7D9,
+0xFF83B8DA,
+0xFF83B8DA,
+0xFF82B8DA,
+0xFF83B9DB,
+0xFF83B9DB,
+0xFF84BADC,
+0xFF84BADC,
+0xFF84BADC,
+0xFF85BBDD,
+0xFF85BBDD,
+0xFF86BBDB,
+0xFF86BBDB,
+0xFF86BBDB,
+0xFF87BCDC,
+0xFF87BCDC,
+0xFF87BCDC,
+0xFF88BDDD,
+0xFF88BDDD,
+0xFF8BBDDE,
+0xFF8BBEDD,
+0xFF8BBDDE,
+0xFF8CBFDE,
+0xFF8DBEDF,
+0xFF8DBEDE,
+0xFF8DBEDE,
+0xFF8DBEDE,
+0xFF8EBFDF,
+0xFF8EBFDF,
+0xFF8EBFDF,
+0xFF8FC0E0,
+0xFF8FC0E0,
+0xFF8FC0E0,
+0xFF90C1E1,
+0xFF90C1E1,
+0xFF90C1E1,
+0xFF90C1DF,
+0xFF90C1E1,
+0xFF91C2E0,
+0xFF91C2E2,
+0xFF91C2E0,
+0xFF91C2E2,
+0xFF92C3E1,
+0xFF93C1E2,
+0xFF93C2E0,
+0xFF93C1E2,
+0xFF93C2E0,
+0xFF93C1E2,
+0xFF93C2E0,
+0xFF93C1E2,
+0xFF93C2E0,
+0xFF92C4DD,
+0xFF92C4DD,
+0xFF94C1E2,
+0xFF94C0E3,
+0xFF91C1E5,
+0xFF90C2E3,
+0xFF90C3E2,
+0xFF90C3DE,
+0xFF98C6E0,
+0xFF94C0DB,
+0xFF93C0DD,
+0xFF94C3E1,
+0xFF93C4E4,
+0xFF8EBFDF,
+0xFF94C3DF,
+0xFF93C2E0,
+0xFF93C3E7,
+0xFF8EC0E3,
+0xFF94C2E4,
+0xFF98C4E1,
+0xFF9DC1D9,
+0xFFB0CDDD,
+0xFF253B46,
+0xFF2A3C40,
+0xFF58676A,
+0xFF3D4D4D,
+0xFF26383A,
+0xFF3B4F50,
+0xFFA0B4B3,
+0xFFCADDDB,
+0xFFE0F1EB,
+0xFFBFCFCC,
+0xFF667A7B,
+0xFF84999E,
+0xFF4C6569,
+0xFF799598,
+0xFFA2BEC2,
+0xFF496068,
+0xFF223440,
+0xFF323E4A,
+0xFF2D3341,
+0xFF1C222E,
+0xFF2D363F,
+0xFF24323D,
+0xFF233E49,
+0xFF042838,
+0xFFA5D2E7,
+0xFF96C5DF,
+0xFF97C6E2,
+0xFF95C4E2,
+0xFF94C3E1,
+0xFF93C2E0,
+0xFF92C1DF,
+0xFF95C4E2,
+0xFF96C5E3,
+0xFF92C1DF,
+0xFF94C3E1,
+0xFF92C4DF,
+0xFF92C3E1,
+0xFF92C4DF,
+0xFF92C3E1,
+0xFF92C4DF,
+0xFF92C4DF,
+0xFF92C4DF,
+0xFF95C4E2,
+0xFF95C4E2,
+0xFF95C4E0,
+0xFF95C4E0,
+0xFF95C4E0,
+0xFF95C4E0,
+0xFF95C4E0,
+0xFF95C4E0,
+0xFF95C4E0,
+0xFF95C4E0,
+0xFF95C4E0,
+0xFF95C4E0,
+0xFF95C4E0,
+0xFF96C5E1,
+0xFF96C5E1,
+0xFF96C5E1,
+0xFF95C4E0,
+0xFF95C4E0,
+0xFF95C4E0,
+0xFF95C4E0,
+0xFF95C4E0,
+0xFF95C4E0,
+0xFF96C5E1,
+0xFF96C5E1,
+0xFF96C5E1,
+0xFF96C5E1,
+0xFF96C5E1,
+0xFF96C5E1,
+0xFF96C5E1,
+0xFF96C5E1,
+0xFF96C5E1,
+0xFF96C5E1,
+0xFF96C5E1,
+0xFF96C5E1,
+0xFF96C5E1,
+0xFF96C5E1,
+0xFF96C5E1,
+0xFF96C5E1,
+0xFF96C5E1,
+0xFF96C5E1,
+0xFF97C6E2,
+0xFF97C6E2,
+0xFF97C6E2,
+0xFF97C6E2,
+0xFF97C6E2,
+0xFF97C6E2,
+0xFF97C6E2,
+0xFF97C6E2,
+0xFF97C6E2,
+0xFF97C6E2,
+0xFF97C6E2,
+0xFF97C6E2,
+0xFF97C6E2,
+0xFF97C6E2,
+0xFF97C6E2,
+0xFF97C6E2,
+0xFF97C6E2,
+0xFF97C6E2,
+0xFF97C6E0,
+0xFF97C6E0,
+0xFF97C6E0,
+0xFF97C6E0,
+0xFF97C6E0,
+0xFF98C6E0,
+0xFF9CC5E3,
+0xFF9DC4E3,
+0xFF99C5E0,
+0xFF97C5DF,
+0xFF95C7E2,
+0xFF96CAE2,
+0xFF93CADF,
+0xFF94C8DD,
+0xFF99C8DC,
+0xFF9AC7DE,
+0xFF98C5E2,
+0xFF9CC1DB,
+0xFFC1D8E8,
+0xFFEAFAFF,
+0xFFBBCCDE,
+0xFFB9BBC7,
+0xFFE6CBC2,
+0xFF654133,
+0xFF67504A,
+0xFF9C9291,
+0xFFC5C8CD,
+0xFFB4C1D1,
+0xFFA6C0DB,
+0xFFA0C3E3,
+0xFF99C7E1,
+0xFF98C7E1,
+0xFF9CC4DE,
+0xFF9CC3E0,
+0xFF99C4E4,
+0xFF98C5E4,
+0xFF9AC6E1,
+0xFF99C7DF,
+0xFF99C7E1,
+0xFF99C7E1,
+0xFF99C7E1,
+0xFF99C7E1,
+0xFF98C6E0,
+0xFF98C6E0,
+0xFF98C6E0,
+0xFF98C6E0,
+0xFF99C7E1,
+0xFF99C7E1,
+0xFF99C7E1,
+0xFF98C6E0,
+0xFF98C6E0,
+0xFF98C6E0,
+0xFF98C6E0,
+0xFF99C7E1,
+0xFF98C6E0,
+0xFF98C6E0,
+0xFF98C6E0,
+0xFF98C6E0,
+0xFF98C6E0,
+0xFF98C6E0,
+0xFF98C6E0,
+0xFF98C6E0,
+0xFF99C5E0,
+0xFF99C5E0,
+0xFF9BC4E0,
+0xFF9CC5E1,
+0xFF9EC5E2,
+0xFF9EC5E2,
+0xFF9FC6E3,
+0xFF9FC6E3,
+0xFF9CC5E1,
+0xFF99C5E0,
+0xFF99C5E0,
+0xFF97C5DF,
+0xFF97C5DF,
+0xFF97C5DF,
+0xFF97C5DF,
+0xFF96C5DF,
+0xFF96C5E1,
+0xFF96C5E1,
+0xFF96C5E1,
+0xFF96C5E1,
+0xFF96C5E1,
+0xFF95C4E0,
+0xFF95C4E0,
+0xFF95C4E0,
+0xFF96C5E1,
+0xFF96C5E1,
+0xFF95C4E0,
+0xFF95C4E0,
+0xFF95C4E0,
+0xFF95C4E0,
+0xFF95C4E0,
+0xFF95C4E0,
+0xFF95C4E2,
+0xFF95C4E2,
+0xFF95C4E2,
+0xFF95C4E2,
+0xFF95C4E2,
+0xFF95C4E2,
+0xFF94C3E1,
+0xFF94C3E1,
+0xFF96C3E2,
+0xFF95C2E1,
+0xFF95C2E3,
+0xFF95C2E3,
+0xFF93C1E2,
+0xFF93C1E2,
+0xFF92C0E1,
+0xFF92C0E1,
+0xFF93C1E2,
+0xFF93C1E2,
+0xFF90C1E2,
+0xFF90C1E2,
+0xFF90C1E2,
+0xFF8FC0E1,
+0xFF8FC0E1,
+0xFF8EBFDF,
+0xFF8DBEDE,
+0xFF8CBFDE,
+0xFF8CBFDE,
+0xFF8BBEDD,
+0xFF8BBEDD,
+0xFF8BBEDD,
+0xFF8BBDDE,
+0xFF88BDDD,
+0xFF88BDDD,
+0xFF88BDDD,
+0xFF87BCDC,
+0xFF87BCDC,
+0xFF87BCDC,
+0xFF87BCDC,
+0xFF86BBDD,
+0xFF85BADC,
+0xFF7EB2D7,
+0xFF7DB1D6,
+0xFF7EB3D5,
+0xFF7EB3D5,
+0xFF7EB3D5,
+0xFF7EB3D5,
+0xFF7FB4D6,
+0xFF80B5D7,
+0xFF82B4D7,
+0xFF83B5D8,
+0xFF84B6D9,
+0xFF85B7DA,
+0xFF85B7D8,
+0xFF85B7D8,
+0xFF85B7D8,
+0xFF86B8D9,
+0xFF85BADC,
+0xFF84BADC,
+0xFF85BBDD,
+0xFF85BBDD,
+0xFF86BBDD,
+0xFF86BBDD,
+0xFF86BBDB,
+0xFF86BBDB,
+0xFF88BDDD,
+0xFF88BDDD,
+0xFF88BDDD,
+0xFF88BDDD,
+0xFF8BBDDE,
+0xFF8BBDDE,
+0xFF8CBEDF,
+0xFF8CBEDF,
+0xFF8CBFDE,
+0xFF8CBFDC,
+0xFF8CBFDE,
+0xFF8DC0DD,
+0xFF8EBFDF,
+0xFF8EBFDD,
+0xFF8EBFDD,
+0xFF8FC0DE,
+0xFF90C1DF,
+0xFF90C1DF,
+0xFF90C1DF,
+0xFF90C1DF,
+0xFF91C2E0,
+0xFF91C2E0,
+0xFF91C2E0,
+0xFF91C2E0,
+0xFF92C3E1,
+0xFF92C4DF,
+0xFF93C4E2,
+0xFF93C5E0,
+0xFF92C3E1,
+0xFF92C4DF,
+0xFF92C3E1,
+0xFF93C5E0,
+0xFF94C3E1,
+0xFF94C3DF,
+0xFF94C3E1,
+0xFF94C3DF,
+0xFF94C3E1,
+0xFF94C3DF,
+0xFF94C3E1,
+0xFF94C3DF,
+0xFF93C5DC,
+0xFF95C5DC,
+0xFF97C2E2,
+0xFF97C2E5,
+0xFF95C3E5,
+0xFF93C4E4,
+0xFF92C5E2,
+0xFF93C5DE,
+0xFF96C4DC,
+0xFF97C3DC,
+0xFF97C3DE,
+0xFF96C3E0,
+0xFF95C4E2,
+0xFF93C4E2,
+0xFF93C4E2,
+0xFF93C4E4,
+0xFF93C5E6,
+0xFF8EC3E3,
+0xFF92C7E7,
+0xFF95C8E5,
+0xFF96C4DE,
+0xFFA1C7DC,
+0xFF5E7B89,
+0xFF2B424A,
+0xFF3B4D51,
+0xFF2C3B3E,
+0xFF546366,
+0xFFE1F3F5,
+0xFFDEF2F3,
+0xFFACC0C1,
+0xFF415353,
+0xFF283A3A,
+0xFF9FB1B3,
+0xFFA5B9BA,
+0xFF647C7C,
+0xFF93AFB0,
+0xFF496569,
+0xFF1F3741,
+0xFF2A3D4B,
+0xFF324251,
+0xFF242D3E,
+0xFF1B2330,
+0xFF37414B,
+0xFF283943,
+0xFF243C48,
+0xFF0F303F,
+0xFF85AEC0,
+0xFF9CCAE1,
+0xFF95C4DE,
+0xFF92C1DD,
+0xFF98C5E2,
+0xFF99C6E3,
+0xFF93C0DD,
+0xFF96C3E0,
+0xFF98C5E2,
+0xFF94C1DE,
+0xFF97C4E1,
+0xFF96C5DF,
+0xFF96C5E1,
+0xFF96C5DF,
+0xFF96C5E1,
+0xFF96C5DF,
+0xFF96C5DF,
+0xFF96C5E1,
+0xFF94C5E3,
+0xFF94C5E3,
+0xFF94C5E3,
+0xFF94C5E3,
+0xFF94C6E1,
+0xFF95C7E2,
+0xFF97C6E2,
+0xFF97C6E2,
+0xFF96C5E1,
+0xFF95C4E0,
+0xFF95C4E0,
+0xFF96C5E1,
+0xFF96C5E1,
+0xFF97C6E2,
+0xFF96C5E1,
+0xFF96C5E1,
+0xFF96C5E1,
+0xFF96C5E1,
+0xFF96C5E1,
+0xFF96C5E1,
+0xFF96C5E1,
+0xFF97C6E2,
+0xFF97C6E2,
+0xFF97C6E2,
+0xFF97C6E2,
+0xFF97C6E2,
+0xFF97C6E2,
+0xFF97C6E2,
+0xFF97C6E2,
+0xFF98C7E3,
+0xFF98C7E3,
+0xFF98C7E3,
+0xFF97C6E0,
+0xFF97C6E0,
+0xFF97C6E0,
+0xFF98C7E1,
+0xFF98C7E1,
+0xFF98C7E1,
+0xFF97C6E0,
+0xFF97C6E0,
+0xFF98C7E1,
+0xFF98C7E1,
+0xFF98C7E1,
+0xFF98C7E1,
+0xFF98C7E1,
+0xFF98C7E1,
+0xFF98C7E1,
+0xFF98C7E1,
+0xFF99C7E1,
+0xFF99C7E1,
+0xFF99C7E1,
+0xFF99C7E1,
+0xFF99C7E1,
+0xFF99C7E1,
+0xFF99C7E1,
+0xFF99C7E1,
+0xFF99C7E1,
+0xFF99C7E1,
+0xFF99C7E1,
+0xFF99C7E1,
+0xFF99C7E1,
+0xFF99C7E1,
+0xFF99C7DF,
+0xFF99C6E3,
+0xFF9DC5E9,
+0xFF9EC4E9,
+0xFF9FC3E3,
+0xFF9CC5E1,
+0xFF95C8E3,
+0xFF92CAE3,
+0xFF95C9E1,
+0xFF9AC8E0,
+0xFF9EC6DF,
+0xFF9FC4DE,
+0xFF9CC5E3,
+0xFF9EC1DD,
+0xFFC6DDEF,
+0xFFE5FAFF,
+0xFFA5C8DB,
+0xFFA3C0CE,
+0xFFD5DDE0,
+0xFFFFF5F4,
+0xFF866765,
+0xFF63342E,
+0xFF9F6758,
+0xFFE1B6AD,
+0xFFC6C2D0,
+0xFFA9C1D9,
+0xFFA0CAE3,
+0xFF93C2DC,
+0xFF9DC9E2,
+0xFF9ECAE3,
+0xFF91C5DD,
+0xFF9BCDE4,
+0xFF9CC5DB,
+0xFF9FC5DC,
+0xFF9BC8DF,
+0xFF9AC8E0,
+0xFF9AC8E0,
+0xFF9AC8E0,
+0xFF9AC8E0,
+0xFF9AC8E0,
+0xFF9AC8E0,
+0xFF9AC8E0,
+0xFF9AC8E0,
+0xFF9AC8E0,
+0xFF9AC8E0,
+0xFF9AC8E0,
+0xFF9AC8E0,
+0xFF9AC8E0,
+0xFF9AC8E0,
+0xFF9AC8E0,
+0xFF99C7E1,
+0xFF99C7E1,
+0xFF99C7DF,
+0xFF99C7DF,
+0xFF99C7DF,
+0xFF99C7DF,
+0xFF99C7DF,
+0xFF99C7DF,
+0xFF9AC6DF,
+0xFF9AC6DF,
+0xFF9CC6DF,
+0xFF9DC7E0,
+0xFF9FC7E1,
+0xFF9FC7E1,
+0xFF9EC6E0,
+0xFF9DC5DF,
+0xFF9DC7E0,
+0xFF9CC6DF,
+0xFF9CC6DF,
+0xFF99C5DE,
+0xFF98C4DD,
+0xFF97C5DD,
+0xFF97C5DF,
+0xFF97C5DF,
+0xFF98C6E0,
+0xFF98C6E0,
+0xFF98C6E0,
+0xFF98C6E0,
+0xFF98C6E0,
+0xFF98C6E0,
+0xFF98C6E0,
+0xFF98C6E0,
+0xFF97C5DF,
+0xFF97C5DF,
+0xFF97C5DF,
+0xFF97C5DF,
+0xFF97C5DF,
+0xFF97C5DF,
+0xFF96C4DE,
+0xFF96C4DE,
+0xFF95C2DF,
+0xFF96C3E0,
+0xFF96C3E0,
+0xFF96C3E0,
+0xFF96C3E0,
+0xFF96C3E0,
+0xFF96C3E0,
+0xFF96C3E0,
+0xFF96C3E2,
+0xFF96C3E2,
+0xFF96C3E2,
+0xFF96C3E2,
+0xFF96C3E2,
+0xFF95C2E1,
+0xFF95C2E1,
+0xFF95C2E1,
+0xFF94C3E1,
+0xFF93C2E0,
+0xFF93C1E2,
+0xFF93C1E2,
+0xFF93C1E2,
+0xFF92C0E1,
+0xFF92C0E1,
+0xFF90C1E1,
+0xFF90C1E1,
+0xFF90C1DF,
+0xFF8FC0E0,
+0xFF8EBFDF,
+0xFF8DBEDE,
+0xFF8CBFDE,
+0xFF8CBFDE,
+0xFF8CBFDE,
+0xFF8BBEDD,
+0xFF8BBEDD,
+0xFF8ABCDD,
+0xFF8ABCDD,
+0xFF89BBDC,
+0xFF88BADB,
+0xFF86BBDB,
+0xFF86BBDB,
+0xFF7FB1D6,
+0xFF7DB1D6,
+0xFF80B2D5,
+0xFF7FB4D6,
+0xFF81B3D6,
+0xFF7FB4D6,
+0xFF82B4D7,
+0xFF82B7D9,
+0xFF85B7DA,
+0xFF86B8DB,
+0xFF86B8DB,
+0xFF87B9DC,
+0xFF87B9DA,
+0xFF87B9DA,
+0xFF88BADB,
+0xFF88BADB,
+0xFF85BADA,
+0xFF84BBDA,
+0xFF86BBDD,
+0xFF87BCDC,
+0xFF88BDDF,
+0xFF88BDDD,
+0xFF89BEDE,
+0xFF89BEDE,
+0xFF8CBEDF,
+0xFF8ABFDE,
+0xFF8CBEDF,
+0xFF8CBFDE,
+0xFF8DBFE0,
+0xFF8DC0DF,
+0xFF8DBFE0,
+0xFF8DC0DF,
+0xFF8EC1DE,
+0xFF8EC1DE,
+0xFF8EC1DE,
+0xFF8FC2DD,
+0xFF90C1DF,
+0xFF91C3DE,
+0xFF91C2E0,
+0xFF91C3DE,
+0xFF92C3E1,
+0xFF92C4DF,
+0xFF93C4E2,
+0xFF93C5E0,
+0xFF93C4E2,
+0xFF94C6E1,
+0xFF94C5E3,
+0xFF94C6E1,
+0xFF94C6E1,
+0xFF94C6DF,
+0xFF94C6E1,
+0xFF94C6DF,
+0xFF94C6E1,
+0xFF94C6DF,
+0xFF94C6E1,
+0xFF94C6DF,
+0xFF96C5E1,
+0xFF96C5DF,
+0xFF96C5E1,
+0xFF96C5DF,
+0xFF96C5E1,
+0xFF96C5DF,
+0xFF96C5E1,
+0xFF96C5DF,
+0xFF96C6DC,
+0xFF96C6DD,
+0xFF98C4E1,
+0xFF98C3E5,
+0xFF97C4E5,
+0xFF96C5E3,
+0xFF94C6DF,
+0xFF96C6DD,
+0xFF98C6DE,
+0xFF99C5DE,
+0xFF99C5E0,
+0xFF98C6E0,
+0xFF97C6E2,
+0xFF95C6E4,
+0xFF95C6E4,
+0xFF95C6E4,
+0xFF93C4E2,
+0xFF96C9E6,
+0xFF90C3E0,
+0xFF91C4DF,
+0xFF99C8E2,
+0xFF9DC7DD,
+0xFFA5C6D7,
+0xFF4B636F,
+0xFF3A4B52,
+0xFF778588,
+0xFFD5E3E4,
+0xFFBAC8C9,
+0xFF849696,
+0xFF6F8183,
+0xFFAFC2C6,
+0xFFCCDEE2,
+0xFFCCDCDC,
+0xFFA2B4B4,
+0xFF5C7270,
+0xFF526C6B,
+0xFF314D50,
+0xFF264148,
+0xFF2F4552,
+0xFF7D8E9E,
+0xFF1A2737,
+0xFF14202E,
+0xFF303C48,
+0xFF2B3C46,
+0xFF29414D,
+0xFF133342,
+0xFF799EB1,
+0xFF9FC9E1,
+0xFF9CCAE4,
+0xFF98C7E3,
+0xFF93C0DD,
+0xFF95C2DF,
+0xFF9DCAE7,
+0xFF94C2DC,
+0xFF9AC7E4,
+0xFF99C7E1,
+0xFF98C6E0,
+0xFF98C6E0,
+0xFF98C6E0,
+0xFF97C6E0,
+0xFF97C6E0,
+0xFF97C6E0,
+0xFF97C6E0,
+0xFF97C6E0,
+0xFF97C6E2,
+0xFF95C6E4,
+0xFF95C6E4,
+0xFF95C6E4,
+0xFF95C7E2,
+0xFF95C7E2,
+0xFF97C6E2,
+0xFF97C6E2,
+0xFF97C6E2,
+0xFF97C6E2,
+0xFF96C5E1,
+0xFF97C6E2,
+0xFF97C6E2,
+0xFF98C7E3,
+0xFF97C6E2,
+0xFF97C6E2,
+0xFF98C7E3,
+0xFF98C7E3,
+0xFF98C7E3,
+0xFF98C7E3,
+0xFF98C7E3,
+0xFF98C7E3,
+0xFF98C7E3,
+0xFF98C7E3,
+0xFF98C7E3,
+0xFF98C7E3,
+0xFF98C7E3,
+0xFF98C7E3,
+0xFF98C7E3,
+0xFF98C7E3,
+0xFF98C7E3,
+0xFF98C7E1,
+0xFF98C7E1,
+0xFF98C7E1,
+0xFF98C7E1,
+0xFF99C8E2,
+0xFF99C8E2,
+0xFF98C7E1,
+0xFF98C7E1,
+0xFF98C7E1,
+0xFF98C7E1,
+0xFF98C7E1,
+0xFF98C7E1,
+0xFF98C7E1,
+0xFF98C7E1,
+0xFF98C7E1,
+0xFF98C7E1,
+0xFF98C7E1,
+0xFF99C7E1,
+0xFF99C7E1,
+0xFF9AC8E2,
+0xFF9AC8E2,
+0xFF9AC8E2,
+0xFF9AC8E2,
+0xFF9AC8E2,
+0xFF9AC8E2,
+0xFF9AC8E2,
+0xFF9AC8E2,
+0xFF9AC8E2,
+0xFF9AC8E2,
+0xFF9AC8E2,
+0xFF9AC8E2,
+0xFF9AC8E0,
+0xFF9AC7E4,
+0xFF9CC7EA,
+0xFF9DC5E9,
+0xFFA0C4E4,
+0xFF9DC6E2,
+0xFF97C9E4,
+0xFF94CAE4,
+0xFF99C8E4,
+0xFF9BC7E2,
+0xFFA0C5DF,
+0xFFA0C5E0,
+0xFF9DC6E4,
+0xFF9EC1DD,
+0xFFC9DEEF,
+0xFFE3FAFF,
+0xFF9EC9DC,
+0xFF9BC4D6,
+0xFFC7DDE8,
+0xFFF6F5FB,
+0xFFFFF7FB,
+0xFFAD7F7F,
+0xFF703024,
+0xFF764034,
+0xFF9A878B,
+0xFFBCC5D4,
+0xFFADC9DF,
+0xFFA2CAE3,
+0xFFA4C9E4,
+0xFF99C3DC,
+0xFF98CCE2,
+0xFF93C7DC,
+0xFF9CC6DC,
+0xFFA2C8DF,
+0xFF9BC8DF,
+0xFF9AC8E0,
+0xFF9AC8E0,
+0xFF9AC8E0,
+0xFF9AC8E0,
+0xFF9AC8E0,
+0xFF9AC8E0,
+0xFF9AC8E0,
+0xFF9AC8E0,
+0xFF9AC8E0,
+0xFF9AC8E0,
+0xFF9AC8E0,
+0xFF9AC8E0,
+0xFF9AC8E0,
+0xFF9AC8E0,
+0xFF9AC8E0,
+0xFF9AC8E2,
+0xFF9AC8E2,
+0xFF9AC8E0,
+0xFF9AC8E0,
+0xFF9AC8E0,
+0xFF9AC8E0,
+0xFF9AC8E0,
+0xFF9AC8E0,
+0xFF9BC7E0,
+0xFF9AC6DF,
+0xFF9CC6DF,
+0xFF9DC7E0,
+0xFF9FC7E1,
+0xFF9FC7E1,
+0xFF9EC6E0,
+0xFF9DC5DF,
+0xFF9EC6E0,
+0xFF9DC7E0,
+0xFF9CC6DF,
+0xFF9CC6DF,
+0xFF9BC5DE,
+0xFF99C5DE,
+0xFF99C5E0,
+0xFF98C6E0,
+0xFF98C6E0,
+0xFF98C6E0,
+0xFF98C6E0,
+0xFF98C6E0,
+0xFF98C6E0,
+0xFF99C5E0,
+0xFF99C5E0,
+0xFF99C5E0,
+0xFF99C5E0,
+0xFF98C6E0,
+0xFF98C6E0,
+0xFF98C6E0,
+0xFF98C6E0,
+0xFF98C6E0,
+0xFF98C6E0,
+0xFF97C5DF,
+0xFF96C3E0,
+0xFF96C3E0,
+0xFF96C3E0,
+0xFF96C3E0,
+0xFF96C3E0,
+0xFF96C3E0,
+0xFF96C3E0,
+0xFF96C3E0,
+0xFF96C3E2,
+0xFF96C3E2,
+0xFF96C3E2,
+0xFF95C2E1,
+0xFF95C2E1,
+0xFF94C1E0,
+0xFF94C1E0,
+0xFF94C1E0,
+0xFF94C3E1,
+0xFF94C3E1,
+0xFF94C2E3,
+0xFF93C1E2,
+0xFF93C1E2,
+0xFF93C1E2,
+0xFF93C1E2,
+0xFF93C1E2,
+0xFF93C2E0,
+0xFF90C1DF,
+0xFF90C1E1,
+0xFF8FC0E0,
+0xFF8FC0E0,
+0xFF8EBFDF,
+0xFF8DC0DF,
+0xFF8DC0DF,
+0xFF8CBFDE,
+0xFF8CBFDE,
+0xFF8BBDDE,
+0xFF8BBDDE,
+0xFF8ABCDD,
+0xFF8ABCDD,
+0xFF87BCDC,
+0xFF87BCDC,
+0xFF7FB3D8,
+0xFF7EB4D8,
+0xFF80B4D9,
+0xFF80B6DA,
+0xFF82B6DB,
+0xFF81B7DB,
+0xFF83B7DC,
+0xFF83B9DD,
+0xFF84B9DB,
+0xFF84B9DB,
+0xFF85BADC,
+0xFF85BADC,
+0xFF85BADC,
+0xFF86BBDD,
+0xFF86BBDD,
+0xFF86BBDB,
+0xFF88BDDD,
+0xFF88BDDC,
+0xFF8BBDDE,
+0xFF8BBEDD,
+0xFF8CBEDF,
+0xFF8CBFDE,
+0xFF8CBFDE,
+0xFF8DC0DF,
+0xFF8EBFDF,
+0xFF8DC0DD,
+0xFF8EBFDF,
+0xFF8FC0DE,
+0xFF8FC0E0,
+0xFF8FC0DE,
+0xFF8FC0E0,
+0xFF90C1DF,
+0xFF91C2E0,
+0xFF91C3DE,
+0xFF91C3DE,
+0xFF92C4DD,
+0xFF94C3DF,
+0xFF95C4DE,
+0xFF95C4E0,
+0xFF95C4DE,
+0xFF96C5E1,
+0xFF96C5DF,
+0xFF97C6E2,
+0xFF97C6E0,
+0xFF97C6E2,
+0xFF98C7E1,
+0xFF98C7E3,
+0xFF98C7E1,
+0xFF98C7E1,
+0xFF98C8DF,
+0xFF99C8E2,
+0xFF99C9E0,
+0xFF98C7E1,
+0xFF98C8DF,
+0xFF99C8E2,
+0xFF99C9E0,
+0xFF99C7E1,
+0xFF9AC8E0,
+0xFF9AC8E2,
+0xFF9AC8E0,
+0xFF9AC8E2,
+0xFF9AC8E0,
+0xFF9AC8E2,
+0xFF9AC8E0,
+0xFF9AC9DD,
+0xFF9AC8DF,
+0xFF9BC7E2,
+0xFF9DC6E4,
+0xFF9BC7E4,
+0xFF9AC8E2,
+0xFF9AC8E0,
+0xFF9AC8E0,
+0xFF9CC8E1,
+0xFF9CC8E1,
+0xFF9CC8E1,
+0xFF9CC8E1,
+0xFF9BC9E3,
+0xFF99C8E2,
+0xFF99C8E6,
+0xFF99C8E4,
+0xFF9CC8E1,
+0xFF99C5DE,
+0xFFA1CDE6,
+0xFF9BC9E0,
+0xFF9BC5DB,
+0xFFA2C8DD,
+0xFFABCCDD,
+0xFF8DA8B3,
+0xFFAFC0C7,
+0xFFBEC9CB,
+0xFFA1ACA8,
+0xFFB3BEB8,
+0xFFBECDCA,
+0xFFC6D8D8,
+0xFFD0E5EA,
+0xFFB9CED3,
+0xFF8B9B9B,
+0xFFA1B1B0,
+0xFF4F6361,
+0xFF3D5653,
+0xFF213D3E,
+0xFF3F5B5F,
+0xFF98B1B8,
+0xFF152934,
+0xFF2B3B48,
+0xFF3E4C57,
+0xFF909EA7,
+0xFF24353F,
+0xFF2D4351,
+0xFF1C374A,
+0xFF55758E,
+0xFFAACFEA,
+0xFF96C2DD,
+0xFF96C4DE,
+0xFF9DCBE5,
+0xFF97C5DF,
+0xFF9AC6E1,
+0xFF9AC6DF,
+0xFF9BC7E2,
+0xFF99C5DE,
+0xFF9AC6DF,
+0xFF9AC6DF,
+0xFF9AC6DF,
+0xFF99C7DF,
+0xFF99C7DF,
+0xFF99C7DF,
+0xFF99C7DF,
+0xFF98C7E1,
+0xFF99C8E4,
+0xFF99C8E4,
+0xFF98C7E3,
+0xFF98C7E3,
+0xFF98C7E3,
+0xFF98C7E3,
+0xFF99C6E3,
+0xFF99C6E3,
+0xFF9AC8E2,
+0xFF99C7E1,
+0xFF99C7E1,
+0xFF99C7E1,
+0xFF9AC8E2,
+0xFF9AC8E2,
+0xFF9AC8E2,
+0xFF9AC8E2,
+0xFF9AC8E2,
+0xFF9AC8E2,
+0xFF9AC8E2,
+0xFF9AC8E2,
+0xFF9AC8E2,
+0xFF9AC8E2,
+0xFF9AC8E2,
+0xFF9AC8E2,
+0xFF9AC8E2,
+0xFF9AC8E2,
+0xFF9AC8E2,
+0xFF9AC8E2,
+0xFF9AC8E2,
+0xFF9AC8E2,
+0xFF9AC8E2,
+0xFF9AC8E2,
+0xFF9AC8E0,
+0xFF9BC9E1,
+0xFF9BC9E1,
+0xFF9BC9E1,
+0xFF9BC9E1,
+0xFF9BC9E1,
+0xFF9AC8E0,
+0xFF9AC8E0,
+0xFF9BC9E1,
+0xFF9AC8E0,
+0xFF9AC8E0,
+0xFF9AC8E0,
+0xFF9AC8E0,
+0xFF9AC8E0,
+0xFF9AC8E0,
+0xFF9AC8E0,
+0xFF9BC7E0,
+0xFF9BC7E0,
+0xFF9BC7E0,
+0xFF9CC8E1,
+0xFF9CC8E1,
+0xFF9CC8E1,
+0xFF9CC8E1,
+0xFF9CC8E1,
+0xFF9CC8E1,
+0xFF9CC8E1,
+0xFF9CC8E1,
+0xFF9CC8E1,
+0xFF9CC8E1,
+0xFF9CC8E1,
+0xFF9CC8E1,
+0xFF9BC9E3,
+0xFF9AC9E7,
+0xFF9BC8E5,
+0xFF9CC9E0,
+0xFF9CC9E0,
+0xFF9BC8E5,
+0xFF9BC8E5,
+0xFF9EC7E3,
+0xFF9EC8E1,
+0xFF9DC9E2,
+0xFF9CC8E3,
+0xFF9CC9E6,
+0xFF9DC1D7,
+0xFFD1E4EB,
+0xFFE4F8FF,
+0xFF9FC5D8,
+0xFF9EC4DB,
+0xFFD0E0EF,
+0xFFEEF0FC,
+0xFFEDE9F7,
+0xFFBAAFBD,
+0xFFC4B0BC,
+0xFF8C757F,
+0xFF6C555B,
+0xFF62555E,
+0xFF9AA0B0,
+0xFFB8CAE2,
+0xFFA6BFDE,
+0xFFA3C4E3,
+0xFF9BC8DF,
+0xFF9DD0E5,
+0xFF9BCDE6,
+0xFF97C6E0,
+0xFF9BC9E1,
+0xFF9CC8E1,
+0xFF9CC8E1,
+0xFF9CC8E1,
+0xFF9CC8E1,
+0xFF9CC8E1,
+0xFF9CC8E1,
+0xFF9CC8E1,
+0xFF9CC8E1,
+0xFF9CC8E1,
+0xFF9CC8E1,
+0xFF9CC8E1,
+0xFF9CC8E1,
+0xFF9CC8E1,
+0xFF9CC8E1,
+0xFF9CC8E1,
+0xFF9BC9E1,
+0xFF9BC9E1,
+0xFF9BC9E1,
+0xFF9BC9E1,
+0xFF9BC9E1,
+0xFF9BC9E1,
+0xFF9BC9E1,
+0xFF9BC9E1,
+0xFF9CC9E0,
+0xFF9CC9E0,
+0xFF9DC7DF,
+0xFF9DC7DF,
+0xFF9FC7E0,
+0xFF9FC7E0,
+0xFFA1C6E0,
+0xFFA0C5DF,
+0xFFA1C6E0,
+0xFF9FC7E0,
+0xFF9EC6DF,
+0xFF9DC7DF,
+0xFF9DC7E0,
+0xFF9BC7E0,
+0xFF9BC7E0,
+0xFF9BC7E0,
+0xFF9AC6DF,
+0xFF9AC6DF,
+0xFF9AC6DF,
+0xFF9AC6DF,
+0xFF9AC6DF,
+0xFF9CC6DF,
+0xFF9CC6DF,
+0xFF9AC6DF,
+0xFF9AC6DF,
+0xFF9AC6DF,
+0xFF9AC6DF,
+0xFF99C5DE,
+0xFF99C5DE,
+0xFF99C5DE,
+0xFF99C5E0,
+0xFF99C5E0,
+0xFF99C5E0,
+0xFF99C5E0,
+0xFF98C4DF,
+0xFF98C4DF,
+0xFF98C4DF,
+0xFF97C3DE,
+0xFF98C4DF,
+0xFF98C4DF,
+0xFF96C3E0,
+0xFF96C3E0,
+0xFF96C3E0,
+0xFF95C2DF,
+0xFF95C2DF,
+0xFF94C1DE,
+0xFF94C1DE,
+0xFF94C1DE,
+0xFF95C2DF,
+0xFF95C2DF,
+0xFF94C1E0,
+0xFF94C1E0,
+0xFF94C1E0,
+0xFF93C0DF,
+0xFF93C0DF,
+0xFF92C1DF,
+0xFF92C1DF,
+0xFF92C1DF,
+0xFF92C1DF,
+0xFF91C0DE,
+0xFF8FC0DE,
+0xFF8FC0DE,
+0xFF8EBFDD,
+0xFF8EBFDD,
+0xFF8DBEDE,
+0xFF8DBEDE,
+0xFF8DBEDE,
+0xFF8CBDDD,
+0xFF8BBEDD,
+0xFF8BBEDD,
+0xFF8ABDDC,
+0xFF8ABDDC,
+0xFF80B5D7,
+0xFF7FB5D7,
+0xFF81B6D8,
+0xFF82B8DA,
+0xFF83B8DA,
+0xFF82B8DA,
+0xFF84B9DB,
+0xFF84BADC,
+0xFF87BCDC,
+0xFF86BDDC,
+0xFF88BDDD,
+0xFF87BEDD,
+0xFF88BDDD,
+0xFF88BFDE,
+0xFF89BEDE,
+0xFF89BEDE,
+0xFF8CBFDE,
+0xFF8DBEDC,
+0xFF8EBFDD,
+0xFF8EBFDD,
+0xFF8EBFDD,
+0xFF8EBFDD,
+0xFF91C0DE,
+0xFF91C0DE,
+0xFF92C1DF,
+0xFF92C1DD,
+0xFF92C1DD,
+0xFF92C1DD,
+0xFF93C2DE,
+0xFF93C2DE,
+0xFF94C3DF,
+0xFF94C3DF,
+0xFF95C4E0,
+0xFF95C4DE,
+0xFF95C4DE,
+0xFF96C5DF,
+0xFF96C5DF,
+0xFF97C6E0,
+0xFF98C6E0,
+0xFF98C8DF,
+0xFF99C7E1,
+0xFF98C8DF,
+0xFF9AC8E2,
+0xFF99C9E0,
+0xFF9AC8E2,
+0xFF9ACAE1,
+0xFF9BC9E3,
+0xFF9ACAE1,
+0xFF9CCAE2,
+0xFF9BCBE2,
+0xFF9CCAE2,
+0xFF9BCBE2,
+0xFF9CCAE2,
+0xFF9CCAE2,
+0xFF9CCAE2,
+0xFF9DCBE3,
+0xFF9CCAE2,
+0xFF9CCAE2,
+0xFF9DC9E2,
+0xFF9CCAE2,
+0xFF9ECAE3,
+0xFF9DCBE3,
+0xFF9ECAE3,
+0xFF9DCBE2,
+0xFF9DCCE0,
+0xFF9ECBE0,
+0xFF9ECAE3,
+0xFFA0C9E5,
+0xFFA0CAE3,
+0xFF9ECAE3,
+0xFF9ECBE2,
+0xFF9ECBE2,
+0xFF9ECAE3,
+0xFF9ECAE3,
+0xFF9ECAE3,
+0xFF9ECAE3,
+0xFF9ECBE2,
+0xFF9DCBE3,
+0xFF9DCBE5,
+0xFF9ECAE5,
+0xFFA0C8E1,
+0xFFA3C9E0,
+0xFF9EC7DD,
+0xFFA3CCE0,
+0xFF9FC8DC,
+0xFFA5CADD,
+0xFFACCBDD,
+0xFFCEE9F4,
+0xFFCADBE2,
+0xFFC2CECE,
+0xFFC8D1CC,
+0xFFC9D3CA,
+0xFFBFCCC5,
+0xFFC2D5D1,
+0xFFA0B5BA,
+0xFF72878C,
+0xFF9AACAC,
+0xFF839390,
+0xFF344944,
+0xFF5E7471,
+0xFF7C9695,
+0xFFB4CECF,
+0xFF0F282D,
+0xFF283F45,
+0xFF30434A,
+0xFF6F8088,
+0xFFBBC9D2,
+0xFF3B4C56,
+0xFF314453,
+0xFF274054,
+0xFF213C57,
+0xFFB2D4F0,
+0xFFA2CBE7,
+0xFF9BC9E3,
+0xFF9AC8E2,
+0xFF9BC9E1,
+0xFF9BC7E0,
+0xFF9CC8E1,
+0xFF9AC6DF,
+0xFF9BC7E0,
+0xFF9BC7E0,
+0xFF9BC7E0,
+0xFF9BC7E0,
+0xFF9BC7E0,
+0xFF9BC7E0,
+0xFF9AC8E0,
+0xFF9AC8E0,
+0xFF9AC8E0,
+0xFF9BC9E3,
+0xFF9BC9E3,
+0xFF9BC8E5,
+0xFF9BC9E3,
+0xFF9BC8E5,
+0xFF9BC9E3,
+0xFF9BC9E3,
+0xFF9BC9E3,
+0xFF9CC8E3,
+0xFF9BC9E1,
+0xFF9CC8E3,
+0xFF9BC9E1,
+0xFF9CC8E3,
+0xFF9BC9E1,
+0xFF9CC8E3,
+0xFF9BC9E1,
+0xFF9CC8E3,
+0xFF9BC9E1,
+0xFF9CC8E3,
+0xFF9BC9E1,
+0xFF9CC8E3,
+0xFF9BC9E1,
+0xFF9CC8E3,
+0xFF9BC9E1,
+0xFF9DC9E4,
+0xFF9CCAE2,
+0xFF9DC9E4,
+0xFF9DC9E2,
+0xFF9DC9E4,
+0xFF9DC9E2,
+0xFF9DC9E4,
+0xFF9DC9E2,
+0xFF9CC9E0,
+0xFF9BC9E0,
+0xFF9DC9E2,
+0xFF9CCAE2,
+0xFF9DC9E2,
+0xFF9BC9E1,
+0xFF9CC8E1,
+0xFF9BC9E1,
+0xFF9CC8E1,
+0xFF9BC9E1,
+0xFF9CC8E1,
+0xFF9BC9E1,
+0xFF9CC8E1,
+0xFF9BC9E1,
+0xFF9CC8E1,
+0xFF9CC8E1,
+0xFF9CC8E1,
+0xFF9CC8E1,
+0xFF9CC8E1,
+0xFF9CC8E1,
+0xFF9CC8E1,
+0xFF9CC8E1,
+0xFF9CC8E1,
+0xFF9CC8E1,
+0xFF9DC9E2,
+0xFF9DC9E2,
+0xFF9DC9E2,
+0xFF9DC9E2,
+0xFF9DC9E2,
+0xFF9DC9E2,
+0xFF9DC9E2,
+0xFF9DC9E2,
+0xFF9CCAE2,
+0xFF9ACAE1,
+0xFF9BCADE,
+0xFF9BCADE,
+0xFF9CC8E3,
+0xFF9EC7E3,
+0xFF9FC7E1,
+0xFF9FC7E1,
+0xFF9DC9E2,
+0xFF9CCAE2,
+0xFF9DCBE5,
+0xFF9EC1D5,
+0xFFD6E7EE,
+0xFFE1F2F9,
+0xFF9EC3D6,
+0xFFA1C5DD,
+0xFFC9D9E8,
+0xFFF2F8FF,
+0xFFE7F0FF,
+0xFFA2ADC1,
+0xFFB6C0D9,
+0xFFC0C5D9,
+0xFFD3CBD6,
+0xFFD0C9D1,
+0xFFA4AABA,
+0xFF838FA5,
+0xFFAEBAD4,
+0xFFB7CBE6,
+0xFFA1C4DA,
+0xFF98C5DA,
+0xFF98C7E1,
+0xFF9CCBE7,
+0xFF9CCAE2,
+0xFF9CC8E1,
+0xFF9CC8E1,
+0xFF9CC8E1,
+0xFF9CC8E1,
+0xFF9CC8E1,
+0xFF9CC8E1,
+0xFF9CC8E1,
+0xFF9CC8E1,
+0xFF9CC8E1,
+0xFF9CC8E1,
+0xFF9CC8E1,
+0xFF9CC8E1,
+0xFF9CC8E1,
+0xFF9CC8E1,
+0xFF9CC8E1,
+0xFF9CC8E1,
+0xFF9CC8E1,
+0xFF9CC8E1,
+0xFF9BC9E1,
+0xFF9CC8E1,
+0xFF9BC9E1,
+0xFF9CC8E1,
+0xFF9CC8E1,
+0xFF9DCAE1,
+0xFF9CC9E0,
+0xFF9EC8E0,
+0xFF9EC8E0,
+0xFF9FC7E0,
+0xFF9FC7E0,
+0xFFA2C7E1,
+0xFFA2C7E1,
+0xFFA2C7E1,
+0xFFA2C7E1,
+0xFFA1C6E0,
+0xFF9FC7E0,
+0xFF9FC7E1,
+0xFF9EC8E1,
+0xFF9EC8E1,
+0xFF9CC8E1,
+0xFF9BC7E0,
+0xFF9BC7E0,
+0xFF9BC7E0,
+0xFF9BC7E0,
+0xFF9DC7E0,
+0xFF9DC7E0,
+0xFF9DC7E0,
+0xFF9DC7E0,
+0xFF9CC6DF,
+0xFF9AC6DF,
+0xFF9AC6DF,
+0xFF9AC6DF,
+0xFF9AC6DF,
+0xFF9AC6DF,
+0xFF9AC6E1,
+0xFF99C5E0,
+0xFF9BC7E2,
+0xFF9AC6E1,
+0xFF99C5E0,
+0xFF99C5E0,
+0xFF98C4DF,
+0xFF98C4DF,
+0xFF99C5E0,
+0xFF99C5E0,
+0xFF97C4E1,
+0xFF97C4E1,
+0xFF96C3E0,
+0xFF96C3E0,
+0xFF96C3E0,
+0xFF96C3E0,
+0xFF96C3E0,
+0xFF96C3E0,
+0xFF95C2DF,
+0xFF95C2DF,
+0xFF95C2E1,
+0xFF94C1E0,
+0xFF94C1E0,
+0xFF94C1E0,
+0xFF94C1E0,
+0xFF94C1E0,
+0xFF91C0DE,
+0xFF91C0DE,
+0xFF92C1DF,
+0xFF92C1DF,
+0xFF8FC0DE,
+0xFF8FC0DE,
+0xFF8EBFDD,
+0xFF8EBFDD,
+0xFF8EBFDF,
+0xFF8EBFDF,
+0xFF8EBFDF,
+0xFF8EBFDF,
+0xFF8CBFDE,
+0xFF8CBFDE,
+0xFF8CBFDE,
+0xFF8CBFDE,
+0xFF83B5D6,
+0xFF81B6D6,
+0xFF85B8D7,
+0xFF84B9D8,
+0xFF87BAD9,
+0xFF85BAD9,
+0xFF88BBDA,
+0xFF87BCDB,
+0xFF8ABDDC,
+0xFF89BEDD,
+0xFF8BBEDB,
+0xFF89BFDB,
+0xFF8CBFDC,
+0xFF8AC0DC,
+0xFF8CBFDC,
+0xFF8CBFDC,
+0xFF8FBEDA,
+0xFF8FBEDA,
+0xFF90BFDB,
+0xFF91C0DC,
+0xFF91C0DC,
+0xFF92C1DD,
+0xFF94C1DE,
+0xFF94C2DC,
+0xFF94C2DC,
+0xFF95C3DD,
+0xFF95C3DD,
+0xFF96C4DE,
+0xFF96C4DE,
+0xFF97C5DF,
+0xFF98C4DF,
+0xFF98C4DF,
+0xFF99C7E1,
+0xFF99C7DF,
+0xFF99C7DF,
+0xFF9AC8E0,
+0xFF9AC8E0,
+0xFF9BC9E1,
+0xFF9CC8E1,
+0xFF9BC9E0,
+0xFF9DC9E2,
+0xFF9CCAE1,
+0xFF9DC9E2,
+0xFF9DCBE2,
+0xFF9ECAE3,
+0xFF9DCBE2,
+0xFF9FCBE4,
+0xFF9ECCE3,
+0xFF9FCCE3,
+0xFF9FCDE4,
+0xFFA0CDE4,
+0xFF9FCDE4,
+0xFFA0CDE4,
+0xFFA0CDE4,
+0xFFA0CDE4,
+0xFFA1CEE5,
+0xFFA0CDE4,
+0xFFA0CDE4,
+0xFFA2CCE4,
+0xFFA0CDE4,
+0xFFA2CCE4,
+0xFFA0CDE4,
+0xFFA2CCE4,
+0xFFA0CDE4,
+0xFFA0CDE2,
+0xFFA0CDE2,
+0xFFA1CDE6,
+0xFFA3CDE6,
+0xFFA3CDE5,
+0xFFA4CDE3,
+0xFFA4CDE1,
+0xFFA4CDE3,
+0xFFA2CCE5,
+0xFFA0CCE7,
+0xFFA0CCE5,
+0xFFA0CDE4,
+0xFFA0CDE2,
+0xFFA2CCE2,
+0xFFA2CCE5,
+0xFFA3CBE5,
+0xFFA4C8E2,
+0xFFA8CCE4,
+0xFFA4CADF,
+0xFFA5CBE0,
+0xFFA7CDE0,
+0xFFA4C7DA,
+0xFFA9C9D8,
+0xFFBBD3DF,
+0xFFC4D5DC,
+0xFFD6E2E0,
+0xFFCFDAD2,
+0xFFC5D1C7,
+0xFFA9B9AE,
+0xFF859892,
+0xFF96ACAA,
+0xFFD3E8E9,
+0xFF899C9A,
+0xFF42524F,
+0xFF6C817C,
+0xFFB2C8C5,
+0xFF9FB8B5,
+0xFF3C5456,
+0xFF1F373B,
+0xFF2D4247,
+0xFF304349,
+0xFF6C7E82,
+0xFFE2F4F8,
+0xFF4E5F66,
+0xFF516570,
+0xFF213649,
+0xFF1F3751,
+0xFF8FADC9,
+0xFFA1C9E3,
+0xFFA0CCE5,
+0xFF99C5DE,
+0xFF9CC9E0,
+0xFFA1CBE3,
+0xFF9CC6DE,
+0xFFA3CDE5,
+0xFF9FC9E1,
+0xFF9FC9E1,
+0xFF9FC9E1,
+0xFF9FC9E1,
+0xFF9DCAE1,
+0xFF9DCAE1,
+0xFF9DCAE1,
+0xFF9DC9E2,
+0xFF9DC9E2,
+0xFF9DC9E2,
+0xFF9DC9E2,
+0xFF9DC9E4,
+0xFF9DC9E2,
+0xFF9DC9E4,
+0xFF9DC9E2,
+0xFF9ECAE3,
+0xFF9ECAE3,
+0xFF9FC9E2,
+0xFF9ECBE2,
+0xFFA0CAE3,
+0xFF9ECBE2,
+0xFFA0CAE3,
+0xFF9ECBE2,
+0xFFA0CAE3,
+0xFF9ECBE2,
+0xFFA1CBE4,
+0xFF9FCCE3,
+0xFFA1CBE4,
+0xFF9ECBE2,
+0xFFA0CAE3,
+0xFF9ECBE2,
+0xFFA0CAE3,
+0xFF9ECBE2,
+0xFFA0CAE3,
+0xFF9ECBE2,
+0xFFA0CAE3,
+0xFFA0CAE2,
+0xFFA0CAE3,
+0xFFA0CAE2,
+0xFFA0CAE3,
+0xFFA0CAE2,
+0xFF9FC9E1,
+0xFF9DCAE1,
+0xFF9FC9E1,
+0xFF9DCAE1,
+0xFF9FC9E1,
+0xFF9DCAE1,
+0xFF9FC9E1,
+0xFF9DCAE1,
+0xFF9FC9E1,
+0xFF9DCAE1,
+0xFF9FC9E2,
+0xFF9DC9E2,
+0xFF9FC9E2,
+0xFF9DC9E2,
+0xFF9EC8E1,
+0xFF9EC8E1,
+0xFF9EC8E1,
+0xFF9EC8E1,
+0xFF9FC9E2,
+0xFF9FC9E2,
+0xFF9FC9E2,
+0xFF9FC9E2,
+0xFF9FC9E2,
+0xFF9FC9E2,
+0xFF9FC9E1,
+0xFF9FC9E1,
+0xFF9FC9E1,
+0xFF9FC9E1,
+0xFF9FC9E1,
+0xFF9FC9E1,
+0xFF9FC9E1,
+0xFF9FC9E1,
+0xFF9FC9DF,
+0xFF9DCADD,
+0xFF9DCADD,
+0xFF9CCBDD,
+0xFF9BCBE1,
+0xFF9CCAE2,
+0xFF9FC9E1,
+0xFFA0C8E1,
+0xFFA0C9DF,
+0xFFA0CAE0,
+0xFFA0CAE2,
+0xFFA1C1D6,
+0xFFDDEBF6,
+0xFFDDEBF6,
+0xFFA2C2D7,
+0xFFA4C7DB,
+0xFFD6EAF3,
+0xFFE4F1F7,
+0xFFE3F1FE,
+0xFF9CAFC0,
+0xFFACC8DE,
+0xFFA6C6DB,
+0xFFABC6D7,
+0xFFAEC8D7,
+0xFFACC9DB,
+0xFFBCCFE0,
+0xFF6E6E7A,
+0xFF9FA1AE,
+0xFFB8CFE1,
+0xFFA2C5D9,
+0xFFA7CDE4,
+0xFFA0C8E1,
+0xFF9FC9E1,
+0xFF9FC9E1,
+0xFF9FC9E1,
+0xFF9FC9E1,
+0xFF9FC9E1,
+0xFF9FC9E1,
+0xFF9FC9E1,
+0xFF9FC9E1,
+0xFF9FC9E1,
+0xFF9FC9E1,
+0xFF9FC9E1,
+0xFF9FC9E1,
+0xFF9FC9E1,
+0xFF9FC9E1,
+0xFF9EC8E0,
+0xFF9EC8E0,
+0xFF9FC9E2,
+0xFF9FC9E2,
+0xFF9FC9E2,
+0xFF9DC9E2,
+0xFF9FC9E2,
+0xFF9DC9E2,
+0xFF9FC9E1,
+0xFF9FC9E1,
+0xFF9FC9E1,
+0xFF9FC9E1,
+0xFFA0C8E1,
+0xFF9FC7E0,
+0xFFA2C8DF,
+0xFFA2C8DF,
+0xFFA4C8E0,
+0xFFA5C9E1,
+0xFFA5C9E1,
+0xFFA4C8E0,
+0xFFA3C7DF,
+0xFFA2C8DF,
+0xFFA2C7E1,
+0xFFA0C8E1,
+0xFF9FC9E2,
+0xFF9EC8E1,
+0xFF9EC8E1,
+0xFF9EC8E1,
+0xFF9EC8E1,
+0xFF9EC8E1,
+0xFFA0C8E2,
+0xFFA0C8E2,
+0xFF9FC7E0,
+0xFF9EC8E0,
+0xFF9EC8E1,
+0xFF9FC9E2,
+0xFF9FC9E2,
+0xFF9FC9E2,
+0xFF9EC8E1,
+0xFF9EC8E1,
+0xFF9EC8E1,
+0xFF9EC8E1,
+0xFF9EC8E1,
+0xFF9EC8E1,
+0xFF9DC7E0,
+0xFF9CC6DF,
+0xFF9CC6DF,
+0xFF9CC6DF,
+0xFF9CC6DF,
+0xFF9AC6DF,
+0xFF98C6E0,
+0xFF98C6E0,
+0xFF98C6E0,
+0xFF98C6E0,
+0xFF98C6E0,
+0xFF97C5DF,
+0xFF97C5DF,
+0xFF97C5DF,
+0xFF97C5DF,
+0xFF97C5DF,
+0xFF96C3E0,
+0xFF96C3E0,
+0xFF95C2DF,
+0xFF95C2DF,
+0xFF95C2DF,
+0xFF95C2DF,
+0xFF92C1DD,
+0xFF93C2DE,
+0xFF93C2DE,
+0xFF93C2DE,
+0xFF93C2E0,
+0xFF93C2E0,
+0xFF92C1DF,
+0xFF92C1DF,
+0xFF90C1DF,
+0xFF90C1DF,
+0xFF90C1DF,
+0xFF8FC0DE,
+0xFF8FC0E0,
+0xFF8FC0E0,
+0xFF8EBFDF,
+0xFF8EBFDF,
+0xFF8CB9D8,
+0xFF8CBBD7,
+0xFF8EBBD8,
+0xFF8FBED8,
+0xFF91BEDB,
+0xFF90BFD9,
+0xFF92BFDC,
+0xFF93C2DC,
+0xFF92BFDC,
+0xFF91C0DA,
+0xFF92C0DA,
+0xFF92C2D9,
+0xFF93C1DB,
+0xFF93C3DA,
+0xFF93C1DB,
+0xFF93C1D9,
+0xFF94C2DC,
+0xFF96C2DB,
+0xFF96C2DB,
+0xFF96C2DB,
+0xFF96C2DB,
+0xFF97C3DC,
+0xFF97C3DC,
+0xFF99C3DC,
+0xFF9AC4DD,
+0xFF9AC4DC,
+0xFF9AC4DC,
+0xFF9BC5DD,
+0xFF9BC5DD,
+0xFF9CC6DE,
+0xFF9CC6DE,
+0xFF9CC6DE,
+0xFF9EC8E1,
+0xFF9CC8E1,
+0xFF9CC8E1,
+0xFF9DC9E2,
+0xFF9DC9E2,
+0xFF9ECBE2,
+0xFFA0CAE2,
+0xFF9ECBE2,
+0xFFA1CBE3,
+0xFF9FCCE3,
+0xFFA1CBE3,
+0xFFA0CDE4,
+0xFFA2CCE4,
+0xFFA0CDE4,
+0xFFA3CDE5,
+0xFFA1CEE5,
+0xFFA3CDE5,
+0xFFA2CFE4,
+0xFFA4CEE6,
+0xFFA2CFE4,
+0xFFA4CEE6,
+0xFFA4CEE4,
+0xFFA5CFE7,
+0xFFA5CFE5,
+0xFFA4CEE6,
+0xFFA4CEE4,
+0xFFA6CEE7,
+0xFFA5CFE5,
+0xFFA6CEE7,
+0xFFA5CFE5,
+0xFFA6CEE7,
+0xFFA5CFE5,
+0xFFA5D0E3,
+0xFFA3D0E5,
+0xFFA3D0E7,
+0xFFA5CFE7,
+0xFFA6CFE3,
+0xFFA8CEE1,
+0xFFA8CEE1,
+0xFFA9CFE4,
+0xFFA6CEE8,
+0xFFA3CFEA,
+0xFFA3CFE8,
+0xFFA3D0E7,
+0xFFA5D0E3,
+0xFFA6CFE1,
+0xFFA8CEE5,
+0xFFA9CDE7,
+0xFFADD1E9,
+0xFFA6CCE1,
+0xFFA8D1E7,
+0xFFA3CCE0,
+0xFFA5CEE0,
+0xFFABD0E0,
+0xFFB5D2E0,
+0xFFD1E9F3,
+0xFFBBCDD1,
+0xFFAEBCBC,
+0xFF8F9E97,
+0xFF91A197,
+0xFFADBEB6,
+0xFFCFE2DC,
+0xFFC2D6D4,
+0xFF5B6F6E,
+0xFF576A68,
+0xFFCCDFDD,
+0xFFDBEFED,
+0xFF516563,
+0xFF788D8E,
+0xFF273C3F,
+0xFF24393E,
+0xFF495C62,
+0xFF26383C,
+0xFF90A2A6,
+0xFF9DAFB1,
+0xFF5E7072,
+0xFF71848B,
+0xFF475A68,
+0xFF12273C,
+0xFF607A93,
+0xFFB3D8F2,
+0xFF99C5DE,
+0xFFA4D1E8,
+0xFFA0CDE4,
+0xFFA1CBE3,
+0xFFA0CAE2,
+0xFFA5CFE7,
+0xFFA0CAE2,
+0xFFA1CBE3,
+0xFFA1CBE3,
+0xFFA1CBE3,
+0xFFA1CBE3,
+0xFFA1CBE3,
+0xFF9FCCE3,
+0xFF9FCBE4,
+0xFFA1CBE4,
+0xFFA1CBE4,
+0xFFA1CBE3,
+0xFFA2CAE4,
+0xFFA1CBE3,
+0xFFA2CAE4,
+0xFFA1CBE3,
+0xFFA3CBE4,
+0xFFA2CCE4,
+0xFFA3CBE4,
+0xFFA2CCE4,
+0xFFA3CBE4,
+0xFFA2CCE2,
+0xFFA3CBE4,
+0xFFA2CCE2,
+0xFFA3CBE4,
+0xFFA2CCE2,
+0xFFA3CBE4,
+0xFFA2CCE2,
+0xFFA3CBE4,
+0xFFA2CCE2,
+0xFFA3CBE4,
+0xFFA2CCE2,
+0xFFA3CBE4,
+0xFFA2CCE2,
+0xFFA2CAE3,
+0xFFA1CBE1,
+0xFFA2CAE3,
+0xFFA2CBE1,
+0xFFA2CAE3,
+0xFFA2CBE1,
+0xFFA4C9E3,
+0xFFA2CAE3,
+0xFFA2CAE3,
+0xFFA1CBE3,
+0xFFA2CAE3,
+0xFFA1CBE3,
+0xFFA2CAE3,
+0xFFA1CBE3,
+0xFFA2CAE3,
+0xFFA0CAE2,
+0xFFA1C9E2,
+0xFFA0CAE2,
+0xFFA1C9E3,
+0xFFA0CAE3,
+0xFFA1C9E3,
+0xFFA0CAE3,
+0xFFA1C9E3,
+0xFFA0CAE3,
+0xFFA0CAE3,
+0xFFA0CAE3,
+0xFFA0CAE3,
+0xFFA0CAE3,
+0xFFA0CAE3,
+0xFFA0CAE3,
+0xFFA0CAE3,
+0xFFA0CAE3,
+0xFFA0CAE2,
+0xFFA0CAE2,
+0xFFA0CAE2,
+0xFFA0CAE2,
+0xFFA0CAE2,
+0xFFA0CAE2,
+0xFFA0CAE2,
+0xFFA0CAE0,
+0xFFA1CAE0,
+0xFFA1CADE,
+0xFFA0CBDE,
+0xFF9ECBDE,
+0xFF9ECBE0,
+0xFFA0CAE2,
+0xFFA1C9E3,
+0xFFA1C9E2,
+0xFFA1CAE0,
+0xFFA2CBDF,
+0xFFA2CBE1,
+0xFFA4C5D8,
+0xFFDEEEFB,
+0xFFD4E4F3,
+0xFFA6C5DA,
+0xFFA8C9DC,
+0xFFD2E5EB,
+0xFFE7F5F8,
+0xFFE2F0F9,
+0xFFA0B5C6,
+0xFFAACEE4,
+0xFF9DCAE1,
+0xFFA3CDE3,
+0xFF9FC9DF,
+0xFFA4CAE1,
+0xFFADC8DB,
+0xFFC2C4D0,
+0xFF221F28,
+0xFF9FA9B5,
+0xFFB6CBDC,
+0xFFA3C2D7,
+0xFFA3C9E0,
+0xFFA1C9E2,
+0xFFA0CAE2,
+0xFFA0CAE2,
+0xFFA0CAE2,
+0xFFA0CAE2,
+0xFFA0CAE2,
+0xFFA0CAE2,
+0xFFA0CAE2,
+0xFFA0CAE2,
+0xFFA0CAE2,
+0xFFA0CAE2,
+0xFFA0CAE2,
+0xFF9FC9E1,
+0xFF9FC9E1,
+0xFF9FC9E1,
+0xFF9FC9E1,
+0xFFA0C8E2,
+0xFFA0C8E2,
+0xFFA0C8E2,
+0xFF9FC9E2,
+0xFF9FC9E2,
+0xFF9FC9E2,
+0xFF9FC9E1,
+0xFF9FC9E1,
+0xFF9FC9E1,
+0xFF9FC9E1,
+0xFFA0C8E1,
+0xFFA2C7E1,
+0xFFA3C9E0,
+0xFFA4C8E0,
+0xFFA5C9E1,
+0xFFA7C9E2,
+0xFFA7C9E2,
+0xFFA6C8E1,
+0xFFA5C7E0,
+0xFFA3C7DF,
+0xFFA3C8E2,
+0xFFA3C8E2,
+0xFFA0C8E2,
+0xFF9FC9E2,
+0xFF9FC9E2,
+0xFF9FC9E2,
+0xFF9FC9E2,
+0xFFA0CAE3,
+0xFFA1C9E3,
+0xFFA1C9E3,
+0xFFA1C9E2,
+0xFFA1C9E2,
+0xFFA0CAE3,
+0xFFA0CAE3,
+0xFFA0CAE3,
+0xFFA0CAE3,
+0xFFA0CAE3,
+0xFF9FC9E2,
+0xFF9FC9E2,
+0xFF9FC9E2,
+0xFF9FC9E2,
+0xFF9FC9E2,
+0xFF9FC9E2,
+0xFF9EC8E1,
+0xFF9EC8E1,
+0xFF9EC8E1,
+0xFF9EC8E1,
+0xFF9CC8E1,
+0xFF9CC8E3,
+0xFF9AC8E2,
+0xFF9AC8E2,
+0xFF99C7E1,
+0xFF99C7E1,
+0xFF98C6E0,
+0xFF98C6E0,
+0xFF98C6E0,
+0xFF97C5DF,
+0xFF97C5DF,
+0xFF97C4E1,
+0xFF96C3E0,
+0xFF96C3E0,
+0xFF96C3E0,
+0xFF96C3E0,
+0xFF95C2DF,
+0xFF94C3DF,
+0xFF94C3DF,
+0xFF94C3DF,
+0xFF94C3DF,
+0xFF94C3E1,
+0xFF93C2E0,
+0xFF93C2E0,
+0xFF93C2E0,
+0xFF90C1DF,
+0xFF90C1DF,
+0xFF90C1DF,
+0xFF90C1DF,
+0xFF8FC0E0,
+0xFF8FC0E0,
+0xFF8FC0E0,
+0xFF8EBFDF,
+0xFF9CBFDB,
+0xFF9CC1DB,
+0xFF9EC2DC,
+0xFF9FC5DC,
+0xFFA0C4DE,
+0xFF9FC5DC,
+0xFFA0C4DE,
+0xFFA0C6DD,
+0xFFA3C7E1,
+0xFFA2C8DF,
+0xFFA3C7DF,
+0xFFA2C8DD,
+0xFFA4C8E0,
+0xFFA3C9DE,
+0xFFA4C8E0,
+0xFFA2C8DF,
+0xFFA1C9E2,
+0xFFA0CAE2,
+0xFFA0CAE2,
+0xFF9FC9E1,
+0xFF9FC9E1,
+0xFF9FC9E1,
+0xFF9FC9E1,
+0xFF9FC7E0,
+0xFFA0C8E1,
+0xFFA0C9DF,
+0xFFA0C9DF,
+0xFFA1CAE0,
+0xFFA1CAE0,
+0xFFA1CAE0,
+0xFFA1CAE0,
+0xFFA1CAE0,
+0xFFA1CBE3,
+0xFFA2CCE4,
+0xFFA2CCE4,
+0xFFA2CCE4,
+0xFFA2CCE4,
+0xFFA2CCE2,
+0xFFA4CDE3,
+0xFFA3CDE3,
+0xFFA4CDE3,
+0xFFA3CDE3,
+0xFFA4CDE3,
+0xFFA4CEE4,
+0xFFA5CEE4,
+0xFFA4CEE4,
+0xFFA6CFE5,
+0xFFA5CFE5,
+0xFFA6CFE5,
+0xFFA6D1E4,
+0xFFA7D0E6,
+0xFFA6D1E4,
+0xFFA7D0E6,
+0xFFA7D0E4,
+0xFFA8D1E7,
+0xFFA8D1E5,
+0xFFA8D1E7,
+0xFFA8D1E5,
+0xFFAAD0E7,
+0xFFA8D1E5,
+0xFFAAD0E7,
+0xFFA8D1E5,
+0xFFAAD0E7,
+0xFFA8D1E5,
+0xFFA7D2E5,
+0xFFA7D1E7,
+0xFFA5D2E9,
+0xFFA7D1E7,
+0xFFA8D1E3,
+0xFFABD2E3,
+0xFFADD0E3,
+0xFFACD0E6,
+0xFFA9D1EB,
+0xFFA6D2ED,
+0xFFA6D2EB,
+0xFFA6D3E8,
+0xFFA8D3E4,
+0xFFABD2E3,
+0xFFADD0E6,
+0xFFADD0E6,
+0xFFA7CBE1,
+0xFFA7D2E5,
+0xFFA1D0E4,
+0xFFA8D8EC,
+0xFFA8D7E7,
+0xFFA4CEDC,
+0xFFB3D1DC,
+0xFFD5ECF4,
+0xFF96A8AC,
+0xFFADBDBD,
+0xFFB2C6C4,
+0xFFBED2D0,
+0xFFBFD5D2,
+0xFFAABEBC,
+0xFF849493,
+0xFFBBCBCB,
+0xFFD7EBEA,
+0xFFC7DBDA,
+0xFF3C504F,
+0xFF5A6E6F,
+0xFF94A7AB,
+0xFF12252B,
+0xFF6D8087,
+0xFF75868E,
+0xFF1D2E35,
+0xFFBDCCCF,
+0xFF94A6A6,
+0xFF91A4A2,
+0xFFC9DDDE,
+0xFFB7CBD2,
+0xFF5C6F7D,
+0xFF183346,
+0xFFB6DCF1,
+0xFFA2CFE6,
+0xFFA3D0E7,
+0xFFA5D2E9,
+0xFFA5CFE5,
+0xFFA5CFE5,
+0xFFA1CAE0,
+0xFFA6CFE5,
+0xFFA5CEE4,
+0xFFA5CEE4,
+0xFFA5CEE4,
+0xFFA4CEE4,
+0xFFA4CEE6,
+0xFFA4CEE6,
+0xFFA4CEE6,
+0xFFA4CEE6,
+0xFFA5CDE6,
+0xFFA5CEE4,
+0xFFA7CCE6,
+0xFFA5CEE4,
+0xFFA7CCE6,
+0xFFA5CEE4,
+0xFFA7CDE4,
+0xFFA5CEE4,
+0xFFA7CDE4,
+0xFFA6CFE5,
+0xFFA8CEE5,
+0xFFA6CFE3,
+0xFFA7CDE4,
+0xFFA5CEE2,
+0xFFA7CDE4,
+0xFFA6CFE3,
+0xFFA7CDE4,
+0xFFA5CEE2,
+0xFFA7CDE4,
+0xFFA5CEE2,
+0xFFA7CDE4,
+0xFFA5CEE2,
+0xFFA7CDE4,
+0xFFA4CDE1,
+0xFFA7CDE4,
+0xFFA5CEE2,
+0xFFA7CDE4,
+0xFFA7CDE2,
+0xFFA7CDE4,
+0xFFA6CCE1,
+0xFFA7CBE3,
+0xFFA6CCE3,
+0xFFA6CCE3,
+0xFFA4CDE3,
+0xFFA6CCE3,
+0xFFA4CDE3,
+0xFFA6CCE3,
+0xFFA4CDE3,
+0xFFA6CBE5,
+0xFFA4CCE5,
+0xFFA5CAE4,
+0xFFA3CBE4,
+0xFFA5CAE4,
+0xFFA3CBE4,
+0xFFA5CAE4,
+0xFFA3CBE4,
+0xFFA5CAE5,
+0xFFA3CBE5,
+0xFFA3CBE5,
+0xFFA3CBE5,
+0xFFA3CBE4,
+0xFFA3CBE4,
+0xFFA3CBE4,
+0xFFA3CBE4,
+0xFFA3CBE4,
+0xFFA3CBE4,
+0xFFA3CBE4,
+0xFFA3CBE4,
+0xFFA3CBE4,
+0xFFA3CBE4,
+0xFFA3CBE4,
+0xFFA3CBE4,
+0xFFA3CBE4,
+0xFFA3CBE4,
+0xFFA2CAE3,
+0xFFA3CBE4,
+0xFFA3CCE2,
+0xFFA5CBE2,
+0xFFA7C9E2,
+0xFFA7C9E4,
+0xFFA6C9E9,
+0xFFA3CAE9,
+0xFFA1CBE3,
+0xFFA4CEE4,
+0xFFA3CCE0,
+0xFFA7C8D9,
+0xFFE0F2FF,
+0xFFCCDEEC,
+0xFFABC7DC,
+0xFFACC9DB,
+0xFFD5E4EB,
+0xFFEFF9FB,
+0xFFE7F1FA,
+0xFF9FB2C0,
+0xFFA8C9DC,
+0xFFA9CFE6,
+0xFFA0C5E2,
+0xFFA8CCEC,
+0xFFA3C8E3,
+0xFFAECCE4,
+0xFFBACBDF,
+0xFF808696,
+0xFF3C373E,
+0xFFD1D4DD,
+0xFFB3CEE1,
+0xFFA0C8E1,
+0xFFA3CBE4,
+0xFFA2CAE3,
+0xFFA2CAE3,
+0xFFA2CAE3,
+0xFFA2CAE3,
+0xFFA2CAE3,
+0xFFA2CAE3,
+0xFFA2CAE3,
+0xFFA2CAE3,
+0xFFA2CAE3,
+0xFFA2CAE3,
+0xFFA2CAE3,
+0xFFA2CAE3,
+0xFFA2CAE3,
+0xFFA1C9E2,
+0xFFA1C9E2,
+0xFFA3C8E3,
+0xFFA3C8E3,
+0xFFA3C8E3,
+0xFFA1C9E3,
+0xFFA1C9E3,
+0xFFA1C9E3,
+0xFFA1C9E2,
+0xFFA1C9E2,
+0xFFA1C9E2,
+0xFFA1C9E2,
+0xFFA3C9E0,
+0xFFA3C9E0,
+0xFFA4C8E0,
+0xFFA6C8E1,
+0xFFA6C8E1,
+0xFFA9C9E2,
+0xFFA9C9E0,
+0xFFA6C9DF,
+0xFFA5C7E0,
+0xFFA4C8E0,
+0xFFA4C9E3,
+0xFFA4C9E3,
+0xFFA2CAE3,
+0xFFA1C9E2,
+0xFFA1C9E3,
+0xFFA1C9E3,
+0xFFA1C9E3,
+0xFFA1C9E3,
+0xFFA1C9E2,
+0xFFA2CAE3,
+0xFFA4C9E3,
+0xFFA1C9E2,
+0xFFA0CAE2,
+0xFFA0CAE2,
+0xFFA0CAE2,
+0xFFA0CAE2,
+0xFFA0CAE2,
+0xFFA0CAE2,
+0xFFA0CAE3,
+0xFFA0CAE3,
+0xFFA0CAE3,
+0xFFA0CAE3,
+0xFFA0CAE3,
+0xFFA0CAE3,
+0xFFA0CAE3,
+0xFF9FC9E2,
+0xFF9FC9E2,
+0xFF9DC9E2,
+0xFF9DC9E2,
+0xFF9CCAE2,
+0xFF9CCAE2,
+0xFF9BC9E1,
+0xFF9BC9E1,
+0xFF9AC8E0,
+0xFF99C7E1,
+0xFF99C7E1,
+0xFF99C7E1,
+0xFF99C7E1,
+0xFF98C6E0,
+0xFF98C6E0,
+0xFF97C5DF,
+0xFF97C5DF,
+0xFF97C5DF,
+0xFF97C5DF,
+0xFF96C3E0,
+0xFF96C3E0,
+0xFF95C4E0,
+0xFF94C3DF,
+0xFF94C3DF,
+0xFF94C3DF,
+0xFF94C3E1,
+0xFF94C3E1,
+0xFF93C2E0,
+0xFF93C2E0,
+0xFF91C2E0,
+0xFF90C1DF,
+0xFF90C1DF,
+0xFF8FC0DE,
+0xFF8FC0DE,
+0xFF8FC0DE,
+0xFFA9C5DD,
+0xFFA7C5DD,
+0xFFAAC6DC,
+0xFFA9C8DD,
+0xFFABC7DD,
+0xFFAAC6DC,
+0xFFA9C5DB,
+0xFFAAC6DC,
+0xFFACC8DE,
+0xFFACC8DD,
+0xFFACC8DD,
+0xFFACC8DD,
+0xFFADC9DE,
+0xFFADC9DE,
+0xFFADC9DE,
+0xFFAAC9DD,
+0xFFABCEE2,
+0xFFABCEE4,
+0xFFABCEE4,
+0xFFABCEE4,
+0xFFABCEE4,
+0xFFABCEE4,
+0xFFABCEE4,
+0xFFABCEE2,
+0xFFABCEE2,
+0xFFADCDE2,
+0xFFADCDE2,
+0xFFADCDE2,
+0xFFADCDE2,
+0xFFADCDE2,
+0xFFADCDE2,
+0xFFABCEE2,
+0xFFAACEE4,
+0xFFA9CFE4,
+0xFFA9CFE6,
+0xFFA9CFE4,
+0xFFAACEE4,
+0xFFAACEE4,
+0xFFAACEE4,
+0xFFAACEE4,
+0xFFAACEE4,
+0xFFAACEE4,
+0xFFAACEE4,
+0xFFA9CFE4,
+0xFFABCFE5,
+0xFFAAD0E5,
+0xFFAAD0E5,
+0xFFAAD0E5,
+0xFFAAD0E3,
+0xFFAAD0E3,
+0xFFAAD0E3,
+0xFFABD1E4,
+0xFFAAD0E3,
+0xFFAAD0E3,
+0xFFABD1E6,
+0xFFABD1E4,
+0xFFACD0E6,
+0xFFACD1E4,
+0xFFACD0E6,
+0xFFABD1E6,
+0xFFACD0E6,
+0xFFABD1E6,
+0xFFABD1E6,
+0xFFABD1E6,
+0xFFABD1E4,
+0xFFA9D2E6,
+0xFFAAD3E9,
+0xFFAAD3E7,
+0xFFACD3E4,
+0xFFADD2E2,
+0xFFAED1E4,
+0xFFAED1E5,
+0xFFACD1EB,
+0xFFA9D3EC,
+0xFFAAD4EC,
+0xFFAAD5E8,
+0xFFABD5E5,
+0xFFADD4E5,
+0xFFAFD2E6,
+0xFFAFD2E8,
+0xFFAFD5E8,
+0xFFABD6E7,
+0xFFAAD9ED,
+0xFFA3D3E7,
+0xFFA9D8E8,
+0xFFADD7E5,
+0xFFB5D3DE,
+0xFFBCD3DB,
+0xFFADBFC3,
+0xFFCBDDDF,
+0xFFADC1C0,
+0xFFB5C9C8,
+0xFFB0C6C4,
+0xFFC0D4D3,
+0xFFCADADA,
+0xFFA4B4B4,
+0xFF6E8281,
+0xFF859B99,
+0xFF4A5E5F,
+0xFF90A4A5,
+0xFF516468,
+0xFF14272B,
+0xFFC7D8DF,
+0xFF37484F,
+0xFF5E6D72,
+0xFFECFBFE,
+0xFF6E817F,
+0xFF445755,
+0xFF768888,
+0xFF738589,
+0xFFB2C5CC,
+0xFF324957,
+0xFF68899C,
+0xFFBFE5FA,
+0xFFA8D1E7,
+0xFFA5CEE4,
+0xFFA7D0E6,
+0xFFA9D2E6,
+0xFFA6CFE5,
+0xFFA7D0E4,
+0xFFA7D0E6,
+0xFFA7D0E4,
+0xFFA7D0E6,
+0xFFA7D0E6,
+0xFFA7D0E6,
+0xFFA7CFE8,
+0xFFA7CFE8,
+0xFFA7D0E6,
+0xFFAAD0E7,
+0xFFAAD0E5,
+0xFFABCFE5,
+0xFFAAD0E5,
+0xFFAACEE4,
+0xFFA9CFE4,
+0xFFAACEE4,
+0xFFA9CFE4,
+0xFFAACEE4,
+0xFFAAD0E5,
+0xFFABCFE5,
+0xFFAAD0E3,
+0xFFAACEE4,
+0xFFA9CFE2,
+0xFFAACEE4,
+0xFFAAD0E3,
+0xFFAAD0E3,
+0xFFAAD0E3,
+0xFFAAD0E3,
+0xFFAAD0E3,
+0xFFAAD0E3,
+0xFFAAD0E3,
+0xFFAAD0E3,
+0xFFAAD0E3,
+0xFFA9CFE4,
+0xFFA9CFE2,
+0xFFA9CFE4,
+0xFFAACFE2,
+0xFFAACEE4,
+0xFFAACFE2,
+0xFFAACEE4,
+0xFFAACEE4,
+0xFFA9CDE3,
+0xFFA8CEE3,
+0xFFA8CEE5,
+0xFFA8CEE3,
+0xFFA8CEE5,
+0xFFA8CEE5,
+0xFFA7CDE4,
+0xFFA7CDE4,
+0xFFA7CDE4,
+0xFFA7CDE4,
+0xFFA8CCE6,
+0xFFA7CDE4,
+0xFFA8CCE6,
+0xFFA6CBE5,
+0xFFA7CBE5,
+0xFFA6CBE5,
+0xFFA6CBE5,
+0xFFA4CCE5,
+0xFFA4CDE3,
+0xFFA4CDE3,
+0xFFA4CDE3,
+0xFFA4CDE3,
+0xFFA4CCE5,
+0xFFA4CDE3,
+0xFFA4CCE5,
+0xFFA4CDE3,
+0xFFA4CCE5,
+0xFFA4CDE3,
+0xFFA6CCE3,
+0xFFA4CDE3,
+0xFFA6CCE3,
+0xFFA6CBE5,
+0xFFA6CBE5,
+0xFFA4CCE5,
+0xFFA4CDE3,
+0xFFA7CDE4,
+0xFFABCBE4,
+0xFFACCAE6,
+0xFFA8C9E8,
+0xFFA6CBE8,
+0xFFA3CDE6,
+0xFFA6D0E6,
+0xFFA3CCE0,
+0xFFA9CADB,
+0xFFE0F3FF,
+0xFFC8DBEA,
+0xFFADC9DE,
+0xFFADC8D9,
+0xFFDBE8F0,
+0xFFE8EFF5,
+0xFFE4EEF7,
+0xFFA2B4C2,
+0xFFB0CDDF,
+0xFFA9CDE5,
+0xFFA9CCEA,
+0xFFA8CBEB,
+0xFFA8CBE7,
+0xFFA7C9E2,
+0xFFB1CDE5,
+0xFFCAD7EA,
+0xFF4B4048,
+0xFF91878F,
+0xFFBBCEDF,
+0xFFA9CBE4,
+0xFFA5CAE4,
+0xFFA3CBE4,
+0xFFA3CBE4,
+0xFFA3CBE4,
+0xFFA3CBE4,
+0xFFA3CBE4,
+0xFFA5CAE4,
+0xFFA3CBE4,
+0xFFA3CBE4,
+0xFFA3CBE4,
+0xFFA3CBE4,
+0xFFA3CBE4,
+0xFFA3CBE4,
+0xFFA2CAE3,
+0xFFA2CAE3,
+0xFFA4C9E3,
+0xFFA4C9E3,
+0xFFA4C9E3,
+0xFFA5C8E4,
+0xFFA4C9E3,
+0xFFA4C9E3,
+0xFFA2CAE3,
+0xFFA4CAE1,
+0xFFA2CBE1,
+0xFFA3C9E0,
+0xFFA4CAE1,
+0xFFA4CAE1,
+0xFFA5C9E1,
+0xFFA5C9E1,
+0xFFA6C8E1,
+0xFFA8C8E1,
+0xFFA9C9E2,
+0xFFA9C9E2,
+0xFFA8C8DF,
+0xFFA7C7E0,
+0xFFA6C8E1,
+0xFFA6CAE2,
+0xFFA6CAE2,
+0xFFA5CAE4,
+0xFFA4C9E3,
+0xFFA3C8E2,
+0xFFA3C8E2,
+0xFFA4C9E3,
+0xFFA4C9E3,
+0xFFA4C9E3,
+0xFFA4C9E3,
+0xFFA4C9E3,
+0xFFA4C9E3,
+0xFFA3CBE4,
+0xFFA3CBE4,
+0xFFA3CBE4,
+0xFFA3CCE2,
+0xFFA3CCE2,
+0xFFA3CCE2,
+0xFFA3CBE4,
+0xFFA2CAE3,
+0xFFA1C9E2,
+0xFFA2CAE3,
+0xFFA2CAE3,
+0xFFA2CAE3,
+0xFFA2CAE3,
+0xFFA1C9E3,
+0xFFA1C9E3,
+0xFFA0CAE3,
+0xFFA0CAE3,
+0xFF9ECBE2,
+0xFF9ECAE3,
+0xFF9ECAE3,
+0xFF9DC9E2,
+0xFF9DC9E2,
+0xFF9DC9E4,
+0xFF9DC9E4,
+0xFF9CC8E3,
+0xFF9CC8E3,
+0xFF9CC8E3,
+0xFF9BC7E2,
+0xFF9BC7E2,
+0xFF9AC6E1,
+0xFF9AC6E1,
+0xFF9AC6E1,
+0xFF9AC6E1,
+0xFF98C6E0,
+0xFF98C5E2,
+0xFF97C5DF,
+0xFF97C4E1,
+0xFF97C4E1,
+0xFF97C4E1,
+0xFF97C4E1,
+0xFF97C4E1,
+0xFF97C4E1,
+0xFF95C4E2,
+0xFF94C3DF,
+0xFF94C3E1,
+0xFF91C2E0,
+0xFF91C2E0,
+0xFF90C1DF,
+0xFFB0C6DB,
+0xFFAEC7DB,
+0xFFB2C8DD,
+0xFFB1CADE,
+0xFFB2C9DB,
+0xFFB0C7D9,
+0xFFB0C7D9,
+0xFFB2C9DB,
+0xFFB6CDDF,
+0xFFB5CCDE,
+0xFFB5CCDE,
+0xFFB4CBDB,
+0xFFB4CBDB,
+0xFFB5CCDC,
+0xFFB6CDDD,
+0xFFB6CDDD,
+0xFFB4CEDF,
+0xFFB4CEDF,
+0xFFB5CFE0,
+0xFFB6CFE3,
+0xFFACC5D9,
+0xFFB2CBDF,
+0xFFB6CFE3,
+0xFFB7D1E2,
+0xFFB7D1E2,
+0xFFB9D0E2,
+0xFFB7CEE0,
+0xFFB8CFE1,
+0xFFBBD2E4,
+0xFFBAD1E3,
+0xFFB9CFE4,
+0xFFB7D0E4,
+0xFFB4CFE2,
+0xFFB5D2E4,
+0xFFB5D1E6,
+0xFFB6D3E5,
+0xFFB6D3E5,
+0xFFB6D3E5,
+0xFFB3D2E4,
+0xFFB1D0E2,
+0xFFB3D2E4,
+0xFFB3D2E4,
+0xFFB3D2E4,
+0xFFB1D2E3,
+0xFFB2D1E3,
+0xFFB0D1E2,
+0xFFB0D1E2,
+0xFFB1D2E3,
+0xFFB2D3E6,
+0xFFB2D3E6,
+0xFFB2D3E6,
+0xFFB1D2E5,
+0xFFB1D2E5,
+0xFFB1D2E5,
+0xFFAED1E5,
+0xFFAED1E4,
+0xFFAFD2E6,
+0xFFAFD2E5,
+0xFFAFD2E6,
+0xFFAED3E6,
+0xFFAFD2E6,
+0xFFAED3E6,
+0xFFAED3E6,
+0xFFAED3E6,
+0xFFAFD2E5,
+0xFFAFD2E5,
+0xFFAFD2E6,
+0xFFAED3E6,
+0xFFB0D3E6,
+0xFFB0D3E6,
+0xFFB0D3E6,
+0xFFB0D3E7,
+0xFFAED2E8,
+0xFFAED4E9,
+0xFFAFD5EA,
+0xFFAED4E7,
+0xFFAED4E7,
+0xFFAFD4E7,
+0xFFAFD3E9,
+0xFFB0D5E8,
+0xFFB0D5E7,
+0xFFAED5E6,
+0xFFADD6E8,
+0xFFADD6E8,
+0xFFAFD5E8,
+0xFFB1D5E5,
+0xFFB9D5E3,
+0xFFC7DDE8,
+0xFFDAEBF2,
+0xFFE0F0F0,
+0xFFD8E6E6,
+0xFFDDECE9,
+0xFFC4D4D3,
+0xFF9FAFAE,
+0xFF9BADAD,
+0xFFB2C4C4,
+0xFFC2D6D5,
+0xFF6B7F7D,
+0xFF475B5A,
+0xFF7F9392,
+0xFF243837,
+0xFF687C7B,
+0xFF9EB2B1,
+0xFF172B2A,
+0xFFC7D9D9,
+0xFFE2F4F4,
+0xFF394949,
+0xFFDBEBEB,
+0xFF7A8A8A,
+0xFF101F22,
+0xFF38454D,
+0xFF6B7C86,
+0xFF2F4958,
+0xFF4E6B7D,
+0xFFBCDBEF,
+0xFFAED1E5,
+0xFFAED1E5,
+0xFFB0D5E8,
+0xFFACD2E7,
+0xFFADD3E6,
+0xFFACD2E7,
+0xFFACD2E5,
+0xFFACD2E7,
+0xFFACD2E7,
+0xFFACD2E7,
+0xFFACD2E9,
+0xFFACD2E9,
+0xFFACD2E9,
+0xFFADD2E5,
+0xFFADD2E5,
+0xFFAED1E5,
+0xFFAED3E6,
+0xFFAFD2E6,
+0xFFAED3E6,
+0xFFAFD2E6,
+0xFFAED3E6,
+0xFFAFD2E6,
+0xFFAED3E6,
+0xFFAFD2E6,
+0xFFAED3E5,
+0xFFB0D3E7,
+0xFFAFD4E6,
+0xFFB0D3E7,
+0xFFAFD4E6,
+0xFFAFD4E6,
+0xFFAFD4E6,
+0xFFAFD4E6,
+0xFFAED3E5,
+0xFFAED3E5,
+0xFFAED3E5,
+0xFFAED3E5,
+0xFFAED3E5,
+0xFFAED3E6,
+0xFFAED3E5,
+0xFFADD2E5,
+0xFFAED1E4,
+0xFFAED1E5,
+0xFFAED1E4,
+0xFFADD0E4,
+0xFFACD1E4,
+0xFFABD0E3,
+0xFFABD0E3,
+0xFFABCFE5,
+0xFFABD0E3,
+0xFFAACEE4,
+0xFFAACEE4,
+0xFFAACEE4,
+0xFFAACEE4,
+0xFFAACEE4,
+0xFFAACEE4,
+0xFFABCDE6,
+0xFFAACEE4,
+0xFFABCDE6,
+0xFFAACEE6,
+0xFFABCDE6,
+0xFFAACEE6,
+0xFFA9CFE4,
+0xFFA8CEE3,
+0xFFA8CEE3,
+0xFFA8CEE3,
+0xFFA8CEE3,
+0xFFA8CEE3,
+0xFFA7CDE4,
+0xFFA7CDE2,
+0xFFA9CFE6,
+0xFFA9CFE4,
+0xFFA9CFE6,
+0xFFA9CFE4,
+0xFFA9CDE3,
+0xFFA8CEE3,
+0xFFA9CDE3,
+0xFFA9CDE3,
+0xFFA8CCE4,
+0xFFA8CEE5,
+0xFFA6D0E6,
+0xFFA6D0E6,
+0xFFA8CEE5,
+0xFFAACCE5,
+0xFFADCBE7,
+0xFFADCCE8,
+0xFFA9CFE6,
+0xFFA6CFE3,
+0xFFA8CEE1,
+0xFFADCCE0,
+0xFFE1F6FF,
+0xFFC6D8EE,
+0xFFAFCCDE,
+0xFFB2CFDD,
+0xFFD5E6ED,
+0xFFE9F4F8,
+0xFFE5F2FB,
+0xFF9EB0BE,
+0xFFB3D0E2,
+0xFFABCEE4,
+0xFFABCDE6,
+0xFFABCDE8,
+0xFFABCDE6,
+0xFFA8CAE3,
+0xFFAED2EA,
+0xFFB5CCDE,
+0xFFA9A3AD,
+0xFF2B212A,
+0xFFB5BDD0,
+0xFFB4CCE4,
+0xFFAACCE5,
+0xFFA5CDE6,
+0xFFA8CDE7,
+0xFFA7CCE6,
+0xFFA6CBE5,
+0xFFA8CDE7,
+0xFFAACEE8,
+0xFFA6CBE5,
+0xFFA6CBE5,
+0xFFA6CBE5,
+0xFFA4CDE3,
+0xFFA4CDE3,
+0xFFA3CCE2,
+0xFFA3CCE2,
+0xFFA5CBE2,
+0xFFA5CBE2,
+0xFFA6CAE2,
+0xFFA6CAE2,
+0xFFA7C9E4,
+0xFFA6CAE2,
+0xFFA6CAE0,
+0xFFA5CBE0,
+0xFFA6CAE0,
+0xFFA5CBE0,
+0xFFA6CAE0,
+0xFFA6CAE0,
+0xFFA6CAE0,
+0xFFA7CBE3,
+0xFFA6CAE2,
+0xFFA6CAE4,
+0xFFA8CAE5,
+0xFFACCBE7,
+0xFFA8C8E1,
+0xFFABC9E3,
+0xFFABC9E3,
+0xFFA9C9E2,
+0xFFA9C9E2,
+0xFFAACAE1,
+0xFFABCBE4,
+0xFFABCBE4,
+0xFFA8CAE3,
+0xFFA8CAE3,
+0xFFA6CAE2,
+0xFFA6CAE2,
+0xFFA7CBE3,
+0xFFA7CBE3,
+0xFFA7CBE3,
+0xFFA7CBE3,
+0xFFA6CAE2,
+0xFFA7CBE3,
+0xFFA8CCE4,
+0xFFA8CCE2,
+0xFFA7CBE1,
+0xFFA7CBE1,
+0xFFA8CBE1,
+0xFFA8CBE1,
+0xFFA7CBE1,
+0xFFA9CDE3,
+0xFFA8CCE4,
+0xFFA7CBE3,
+0xFFA5CBE2,
+0xFFA6CBE5,
+0xFFA6CBE5,
+0xFFA5CAE4,
+0xFFA3C8E2,
+0xFFA7CDE4,
+0xFFA4CCE5,
+0xFFA3CBE4,
+0xFFA2CAE3,
+0xFFA2CAE3,
+0xFFA3CDE6,
+0xFFA1CBE4,
+0xFFA1CAE6,
+0xFF9FC8E4,
+0xFF9DC6E2,
+0xFF9DC6E2,
+0xFF9EC8E1,
+0xFF9FC9E2,
+0xFF9FC9E2,
+0xFF9FC9E2,
+0xFF9EC8E1,
+0xFF9FC9E2,
+0xFF9EC7E3,
+0xFFA0CCE5,
+0xFF9AC6E1,
+0xFF99C5E0,
+0xFF9BC7E2,
+0xFF9CC8E3,
+0xFF9DC9E4,
+0xFF98C4DF,
+0xFF9BC7E4,
+0xFF9CC8E3,
+0xFF99C6E3,
+0xFF99C8E4,
+0xFF95C7E2,
+0xFF94C6E1,
+0xFFB8CBDC,
+0xFFB8CBDC,
+0xFFB9CCDD,
+0xFFBBCEDF,
+0xFFBACDDE,
+0xFFB8CBDA,
+0xFFB9CCDD,
+0xFFBACDDC,
+0xFFBDCEE0,
+0xFFBCCFDE,
+0xFFBDCEDE,
+0xFFBDD0DE,
+0xFFBECFDF,
+0xFFBED1DF,
+0xFFC0D1E1,
+0xFFC0D3E2,
+0xFFC0D3E2,
+0xFFBDD3E1,
+0xFFBACDDE,
+0xFFB8CBDC,
+0xFFB4C6DA,
+0xFFBBCEDF,
+0xFFBED1E2,
+0xFFC2D5E4,
+0xFFC1D4E3,
+0xFFC3D4E4,
+0xFFC2D3E3,
+0xFFC2D3E3,
+0xFFC5D6E6,
+0xFFC4D5E7,
+0xFFC1D2E4,
+0xFFC1D2E4,
+0xFFBED3E4,
+0xFFBED5E5,
+0xFFBFD4E5,
+0xFFBED5E5,
+0xFFC0D5E6,
+0xFFBFD6E6,
+0xFFBED5E5,
+0xFFBAD4E3,
+0xFFBDD4E4,
+0xFFBBD5E4,
+0xFFBCD6E5,
+0xFFBCD6E5,
+0xFFBCD6E7,
+0xFFBBD7E5,
+0xFFBBD6E7,
+0xFFBCD7E8,
+0xFFBBD6E7,
+0xFFBBD6E7,
+0xFFBBD6E7,
+0xFFBAD5E6,
+0xFFBAD5E8,
+0xFFBAD5E8,
+0xFFB8D5E7,
+0xFFB8D5E7,
+0xFFB8D5E7,
+0xFFB8D5E7,
+0xFFB7D6E8,
+0xFFB8D7E9,
+0xFFB7D6EA,
+0xFFB7D6EA,
+0xFFB5D6E9,
+0xFFB4D5E8,
+0xFFB6D5E7,
+0xFFB6D6E5,
+0xFFB6D5E7,
+0xFFB6D5E7,
+0xFFB5D4E6,
+0xFFB4D5E6,
+0xFFB4D5E6,
+0xFFB4D5E6,
+0xFFB3D4E7,
+0xFFB2D5E8,
+0xFFB2D5E8,
+0xFFB3D6E9,
+0xFFB3D6E9,
+0xFFB3D6E9,
+0xFFB4D7EB,
+0xFFB4D7EA,
+0xFFB4D8E8,
+0xFFB3D7E7,
+0xFFB5D8EB,
+0xFFB4D7EA,
+0xFFB6D7EA,
+0xFFB6D6E5,
+0xFFB9D5E3,
+0xFFC5DBE6,
+0xFFC0D1D8,
+0xFFD2E0E1,
+0xFFD2DEDC,
+0xFFBCC8C4,
+0xFFA9B8B5,
+0xFFBFCFCC,
+0xFFBACECD,
+0xFFB8CCCB,
+0xFF6E817F,
+0xFF293C3A,
+0xFF697C7A,
+0xFF405351,
+0xFF435654,
+0xFFE6FAF8,
+0xFF374B49,
+0xFF586C6A,
+0xFFF0FFFF,
+0xFFC4D6D6,
+0xFF778989,
+0xFFD8EAEC,
+0xFFBDCCCF,
+0xFF9AA9AE,
+0xFF09161C,
+0xFF374850,
+0xFF485B69,
+0xFFB0CAD9,
+0xFFBCD7E8,
+0xFFB9D6E8,
+0xFFB2D3E6,
+0xFFB4D7EB,
+0xFFABD0E3,
+0xFFB2D7EA,
+0xFFB0D5E8,
+0xFFB0D5E8,
+0xFFB0D5E8,
+0xFFB0D5E8,
+0xFFB1D4E8,
+0xFFB0D4EA,
+0xFFB0D4EA,
+0xFFB0D4EA,
+0xFFB1D4E8,
+0xFFB1D4E7,
+0xFFB1D4E7,
+0xFFB1D4E7,
+0xFFB2D5E8,
+0xFFB2D5E8,
+0xFFB2D5E8,
+0xFFB2D5E8,
+0xFFB1D4E7,
+0xFFB2D5E8,
+0xFFB2D5E8,
+0xFFB2D5E8,
+0xFFB2D5E8,
+0xFFB2D5E8,
+0xFFB2D5E8,
+0xFFB2D5E8,
+0xFFB2D6E6,
+0xFFB1D6E6,
+0xFFB2D6E6,
+0xFFB1D6E6,
+0xFFB2D6E6,
+0xFFB1D6E6,
+0xFFB2D5E8,
+0xFFB1D6E8,
+0xFFB2D5E8,
+0xFFB2D5E8,
+0xFFB1D4E7,
+0xFFB1D4E7,
+0xFFB1D4E7,
+0xFFB1D4E7,
+0xFFB1D4E7,
+0xFFB0D3E6,
+0xFFB1D4E8,
+0xFFB0D5E8,
+0xFFAFD4E7,
+0xFFAFD4E7,
+0xFFAFD4E7,
+0xFFAFD4E7,
+0xFFAED3E6,
+0xFFAED3E6,
+0xFFAFD2E8,
+0xFFAFD2E8,
+0xFFAED1E7,
+0xFFAED1E7,
+0xFFAED1E7,
+0xFFAED1E7,
+0xFFAED1E7,
+0xFFAED1E7,
+0xFFACD1E4,
+0xFFABD1E4,
+0xFFACD1E4,
+0xFFAAD0E3,
+0xFFABCFE5,
+0xFFAAD0E5,
+0xFFABCFE5,
+0xFFAAD0E5,
+0xFFABCFE5,
+0xFFABCFE5,
+0xFFABCFE5,
+0xFFABCFE5,
+0xFFABD0E3,
+0xFFABD0E3,
+0xFFABD0E3,
+0xFFACCFE3,
+0xFFADCDE4,
+0xFFACCFE5,
+0xFFA8D1E5,
+0xFFA9D2E6,
+0xFFAAD0E5,
+0xFFACCFE5,
+0xFFB1CDE5,
+0xFFB2CEE6,
+0xFFADD0E6,
+0xFFAAD0E3,
+0xFFACD1E4,
+0xFFAECDE1,
+0xFFE2F4FF,
+0xFFC3D5EB,
+0xFFB0CDDF,
+0xFFB5D1DD,
+0xFFD4E7ED,
+0xFFE7F5F8,
+0xFFE5F2FB,
+0xFF9FB1BF,
+0xFFB5D2E4,
+0xFFADD0E4,
+0xFFAED1E7,
+0xFFADD0E6,
+0xFFB1D3EC,
+0xFFACD0E8,
+0xFFA5CEE2,
+0xFFBAD5E6,
+0xFFD9D9E3,
+0xFF160C15,
+0xFF524F60,
+0xFFCAD5E9,
+0xFFAFCEE3,
+0xFFA8CEE5,
+0xFFA8CEE5,
+0xFFA9CDE5,
+0xFFA9CBE4,
+0xFFA9CBE4,
+0xFFAACCE5,
+0xFFA8CCE4,
+0xFFA9CDE5,
+0xFFA7CDE4,
+0xFFA7CDE4,
+0xFFA5CEE4,
+0xFFA7CDE4,
+0xFFA7CDE4,
+0xFFA7CDE4,
+0xFFA8CCE4,
+0xFFA8CCE4,
+0xFFA8CCE4,
+0xFFA9CBE4,
+0xFFA8CCE4,
+0xFFA8CCE2,
+0xFFA8CDE0,
+0xFFA8CDE0,
+0xFFA8CDE0,
+0xFFA9CEE1,
+0xFFA8CDE0,
+0xFFA8CCE2,
+0xFFA8CCE4,
+0xFFA8CCE4,
+0xFFA6CAE4,
+0xFFA6C8E3,
+0xFFA6C8E3,
+0xFFABCBE4,
+0xFFABCBE4,
+0xFFACCCE5,
+0xFFADCDE6,
+0xFFADCDE4,
+0xFFABCBE2,
+0xFFAACAE1,
+0xFFABCBE2,
+0xFFADCDE4,
+0xFFABCEE4,
+0xFFABCEE4,
+0xFFAACEE4,
+0xFFA9CDE5,
+0xFFA7CDE4,
+0xFFA8CCE4,
+0xFFA8CCE4,
+0xFFA8CCE4,
+0xFFAACCE5,
+0xFFABCEE4,
+0xFFABCEE4,
+0xFFABCEE2,
+0xFFABCEE2,
+0xFFABCEE2,
+0xFFABCEE2,
+0xFFAACDE1,
+0xFFABCEE2,
+0xFFAACDE3,
+0xFFAACDE3,
+0xFFAACEE6,
+0xFFAACEE6,
+0xFFA9CEE8,
+0xFFA8CEE5,
+0xFFA9CFE6,
+0xFFA9CFE6,
+0xFFA7CDE4,
+0xFFA7CDE4,
+0xFFA8CEE5,
+0xFFA9CEE8,
+0xFFA6CEE7,
+0xFFA3CBE4,
+0xFFA5CDE7,
+0xFFA7CFE9,
+0xFFAACFEA,
+0xFFA9CEE8,
+0xFFA7CCE6,
+0xFFA4CAE1,
+0xFFA3C8E2,
+0xFFA3C9E0,
+0xFFA6CAE2,
+0xFFA5C9E1,
+0xFFA0C6DD,
+0xFFA3C9E0,
+0xFFA2C8DF,
+0xFFA4CCE5,
+0xFFA4CCE5,
+0xFFA1C9E2,
+0xFFA2CAE4,
+0xFFA4CCE6,
+0xFFA2CAE4,
+0xFFA0C8E2,
+0xFFA2CCE5,
+0xFF9CC8E1,
+0xFF92C0DA,
+0xFF95C4DE,
+0xFFBECFDF,
+0xFFBECFDF,
+0xFFC0D1E1,
+0xFFC1D2E2,
+0xFFC0D1E1,
+0xFFBFD1DF,
+0xFFC0D1E1,
+0xFFC1D3E1,
+0xFFC1D1E1,
+0xFFC1D3E1,
+0xFFC2D2E1,
+0xFFC2D4E0,
+0xFFC4D4E3,
+0xFFC4D6E2,
+0xFFC6D6E5,
+0xFFC5D7E5,
+0xFFC4D7E5,
+0xFFC6D9E7,
+0xFFBACBDB,
+0xFFB0C1D1,
+0xFFB3C4D6,
+0xFFBFD0E2,
+0xFFC3D4E6,
+0xFFC8D9E9,
+0xFFC4D5E5,
+0xFFC7D7E6,
+0xFFC6D6E5,
+0xFFC6D6E5,
+0xFFC8D8E7,
+0xFFC8D8E8,
+0xFFC6D6E6,
+0xFFC7D7E7,
+0xFFC7D7E7,
+0xFFC6D7E7,
+0xFFC7D7E7,
+0xFFC6D7E7,
+0xFFC7D7E7,
+0xFFC7D8E8,
+0xFFC7D8E8,
+0xFFC4D7E6,
+0xFFC7D8E8,
+0xFFC6D9E8,
+0xFFC6D9E8,
+0xFFC6D9E8,
+0xFFC5D8E9,
+0xFFC3D9E7,
+0xFFC3D8E9,
+0xFFC4D9EA,
+0xFFC5D8E9,
+0xFFC5D8E9,
+0xFFC3D8E9,
+0xFFC3D8E9,
+0xFFC3D8E9,
+0xFFC2D7E8,
+0xFFC2D7E8,
+0xFFC2D7E8,
+0xFFC1D8EA,
+0xFFC1D8EA,
+0xFFC2D9EB,
+0xFFC2D9EB,
+0xFFC2D9EB,
+0xFFC1D8EA,
+0xFFC0D7E9,
+0xFFBDD7E8,
+0xFFBDD7E6,
+0xFFBDD7E6,
+0xFFBCD6E5,
+0xFFBCD6E5,
+0xFFBCD6E7,
+0xFFBAD5E6,
+0xFFBAD5E6,
+0xFFBAD5E6,
+0xFFBAD5E6,
+0xFFB8D5E5,
+0xFFB8D5E7,
+0xFFB9D6E8,
+0xFFB9D6E8,
+0xFFB8D5E7,
+0xFFB7D4E6,
+0xFFB6D3E5,
+0xFFB8D5E5,
+0xFFB7D4E4,
+0xFFB7D6E8,
+0xFFB6D5E7,
+0xFFB9D6E8,
+0xFFB9D5E3,
+0xFFBCD3E1,
+0xFFC7DBE4,
+0xFFCDDFE3,
+0xFFC7D5D6,
+0xFFC0CCCA,
+0xFFB7C3BF,
+0xFFC0D0CD,
+0xFFCBDEDA,
+0xFFC4DAD8,
+0xFF869A99,
+0xFF2C3C3B,
+0xFF738181,
+0xFFC6D6D5,
+0xFFAFBFBE,
+0xFFF1FFFF,
+0xFF617472,
+0xFF172929,
+0xFFCDDFDF,
+0xFFBFD3D2,
+0xFF8A9E9D,
+0xFF9DB1B2,
+0xFF8A9DA1,
+0xFF889B9F,
+0xFFADC0C6,
+0xFFC1D4DA,
+0xFF1A2C36,
+0xFF122835,
+0xFF2B4252,
+0xFFC8E2F3,
+0xFFBBD8EA,
+0xFFB7D6EA,
+0xFFB5D6E9,
+0xFFB6D9EC,
+0xFFB2D5E8,
+0xFFB3D6E9,
+0xFFB3D6E9,
+0xFFB3D6E9,
+0xFFB3D6E9,
+0xFFB6D7EA,
+0xFFB4D7EB,
+0xFFB4D7EB,
+0xFFB4D7EB,
+0xFFB6D7EA,
+0xFFB6D7EA,
+0xFFB6D7EA,
+0xFFB6D7EA,
+0xFFB6D7EA,
+0xFFB6D7EA,
+0xFFB6D7EA,
+0xFFB6D7EA,
+0xFFB6D7EA,
+0xFFB6D7EA,
+0xFFB6D7EA,
+0xFFB6D7EA,
+0xFFB6D7EA,
+0xFFB7D8EB,
+0xFFB7D8EB,
+0xFFB7D8EB,
+0xFFB7D8EB,
+0xFFB5D8EB,
+0xFFB7D8EB,
+0xFFB5D8EB,
+0xFFB7D8EB,
+0xFFB5D8EB,
+0xFFB7D8EB,
+0xFFB5D8EB,
+0xFFB7D8EB,
+0xFFB7D8EB,
+0xFFB7D8EB,
+0xFFB7D8EB,
+0xFFB7D8EB,
+0xFFB7D8EB,
+0xFFB7D8EB,
+0xFFB4D7EA,
+0xFFB4D7EA,
+0xFFB4D7EA,
+0xFFB4D7EA,
+0xFFB4D7EA,
+0xFFB3D6EA,
+0xFFB3D6EA,
+0xFFB3D6EA,
+0xFFB3D6EA,
+0xFFB2D5E9,
+0xFFB2D5E9,
+0xFFB1D4E8,
+0xFFB1D4E8,
+0xFFB0D3E7,
+0xFFB0D3E7,
+0xFFB0D3E7,
+0xFFB0D3E7,
+0xFFB0D3E7,
+0xFFAFD4E7,
+0xFFB0D3E7,
+0xFFAFD4E7,
+0xFFB0D3E7,
+0xFFAFD4E7,
+0xFFAFD2E8,
+0xFFAED2E8,
+0xFFAFD2E8,
+0xFFAFD2E8,
+0xFFAFD2E6,
+0xFFAFD2E6,
+0xFFAED1E5,
+0xFFAED1E5,
+0xFFAED1E5,
+0xFFB0D0E5,
+0xFFB1D0E5,
+0xFFB2D1E6,
+0xFFAFD2E6,
+0xFFAED3E6,
+0xFFAFD2E6,
+0xFFB2D1E6,
+0xFFB6CEE6,
+0xFFB7D0E6,
+0xFFB4D3E7,
+0xFFAFD3E3,
+0xFFB3D4E5,
+0xFFB4CFE0,
+0xFFE4F3FF,
+0xFFC2D1E6,
+0xFFB5CFE0,
+0xFFB9D4DF,
+0xFFD6E7EE,
+0xFFE9F4F8,
+0xFFE7F1FA,
+0xFFA0B2BE,
+0xFFB5D5E4,
+0xFFAED5E6,
+0xFFB1D4E8,
+0xFFB0D3E9,
+0xFFADD1E9,
+0xFFAED4E9,
+0xFFAED4E7,
+0xFFB4D0DE,
+0xFFD8DCE5,
+0xFF42373F,
+0xFF14040F,
+0xFFBFBBCA,
+0xFFB9CFE4,
+0xFFABCFE5,
+0xFFACCFE5,
+0xFFADD0E6,
+0xFFAECEE5,
+0xFFACCCE3,
+0xFFADCDE4,
+0xFFABCEE4,
+0xFFABCEE4,
+0xFFAACEE4,
+0xFFAACEE4,
+0xFFA9CFE4,
+0xFFA9CDE3,
+0xFFA9CDE3,
+0xFFA9CDE3,
+0xFFA9CDE3,
+0xFFA9CDE5,
+0xFFA8CEE5,
+0xFFA9CDE5,
+0xFFA8CEE5,
+0xFFA8CEE5,
+0xFFA8CEE3,
+0xFFA8CEE3,
+0xFFA8CEE3,
+0xFFA9CFE4,
+0xFFA8CEE3,
+0xFFA8CEE5,
+0xFFA9CFE6,
+0xFFABCFE7,
+0xFFABCFE7,
+0xFFABCFE7,
+0xFFAACEE6,
+0xFFABCDE6,
+0xFFABCDE6,
+0xFFABCEE4,
+0xFFACCFE5,
+0xFFADD0E6,
+0xFFACCFE5,
+0xFFACCFE5,
+0xFFACCFE5,
+0xFFAACDE3,
+0xFFA9CDE3,
+0xFFAACEE4,
+0xFFABD1E6,
+0xFFABD1E6,
+0xFFA8D1E5,
+0xFFAAD0E7,
+0xFFACD2E9,
+0xFFABCFE5,
+0xFFABCFE5,
+0xFFACD0E6,
+0xFFACD0E6,
+0xFFACD0E6,
+0xFFACD0E6,
+0xFFACD0E6,
+0xFFACD0E6,
+0xFFADD1E7,
+0xFFACD0E6,
+0xFFABCFE5,
+0xFFACD0E6,
+0xFFACD0E6,
+0xFFACD0E6,
+0xFFABCFE7,
+0xFFAAD0E7,
+0xFFAAD0E7,
+0xFFA8D1E5,
+0xFFA8D1E5,
+0xFFA8D1E5,
+0xFFA7D0E4,
+0xFFA7D0E6,
+0xFFA8CEE5,
+0xFFA8CEE5,
+0xFFA6CCE1,
+0xFFA6CCE1,
+0xFFA7CBE1,
+0xFFA7CCDF,
+0xFFA7CADE,
+0xFFA8CBDE,
+0xFFA9CCE0,
+0xFFACCDE0,
+0xFFA9C8DC,
+0xFFACC8DD,
+0xFFAAC9DD,
+0xFFACCDE0,
+0xFFA9CADD,
+0xFFA8CBDF,
+0xFFA6C9DD,
+0xFFA9CCE0,
+0xFFA8CBE1,
+0xFFA6C9DF,
+0xFFA9CBE4,
+0xFFA5C9E1,
+0xFFA1C5DD,
+0xFFA0C6DD,
+0xFF9FC8DE,
+0xFFA2CCE2,
+0xFFC3D0E0,
+0xFFC2D2DF,
+0xFFC5D3E0,
+0xFFC6D4E1,
+0xFFC6D4E1,
+0xFFC6D4E1,
+0xFFC6D4E1,
+0xFFC7D5E2,
+0xFFC6D4E1,
+0xFFC6D4E1,
+0xFFC7D5E2,
+0xFFC8D6E1,
+0xFFC8D6E3,
+0xFFC8D6E1,
+0xFFC8D6E3,
+0xFFC6D6E3,
+0xFFC5D7E3,
+0xFFC4D6E4,
+0xFFB8C9D9,
+0xFFB5C6D6,
+0xFFBCCDDD,
+0xFFBCCDDD,
+0xFFBCCDDD,
+0xFFCBDBEA,
+0xFFC9D9E8,
+0xFFCADAE7,
+0xFFC9D9E6,
+0xFFC7D7E4,
+0xFFCBD9E6,
+0xFFCCD9E9,
+0xFFCCD9E9,
+0xFFCDDAEA,
+0xFFCDD9E9,
+0xFFCDD9E7,
+0xFFCDD9E7,
+0xFFCCD8E6,
+0xFFCDD9E7,
+0xFFCEDAE8,
+0xFFCDDBE8,
+0xFFCCDAE7,
+0xFFCDDBE8,
+0xFFCDDBE8,
+0xFFCDDAEA,
+0xFFCDDAEA,
+0xFFCADAE9,
+0xFFC9D9E8,
+0xFFCADAE9,
+0xFFCADAE9,
+0xFFCDDAEA,
+0xFFCDDAEA,
+0xFFCDDAEA,
+0xFFCADAE9,
+0xFFCCD9E9,
+0xFFCADAE9,
+0xFFCADAE9,
+0xFFCADAE9,
+0xFFCBDBEB,
+0xFFC9DAEA,
+0xFFCADAEA,
+0xFFC8D9E9,
+0xFFC9D9E9,
+0xFFC8D9E9,
+0xFFC9D9E9,
+0xFFC9DAEA,
+0xFFC9DCEA,
+0xFFC7DDEA,
+0xFFC9DCEA,
+0xFFC6DCE9,
+0xFFC8DBEA,
+0xFFC6DCEA,
+0xFFC5DBE9,
+0xFFC5DBE9,
+0xFFC5DBE9,
+0xFFC4DBE9,
+0xFFC3DAEA,
+0xFFC3DAEA,
+0xFFC3DAEA,
+0xFFC2D9E9,
+0xFFC0D7E7,
+0xFFBFD6E6,
+0xFFBDD4E2,
+0xFFBCD3E3,
+0xFFBCD6E7,
+0xFFBAD4E5,
+0xFFBBD5E4,
+0xFFBDD4E2,
+0xFFBFD5E0,
+0xFFC9DCE3,
+0xFFCEE0E4,
+0xFF9FADAE,
+0xFFBECDCA,
+0xFFD3E2DD,
+0xFFD8E8E5,
+0xFFC5D9D7,
+0xFF415755,
+0xFF4D6361,
+0xFF96A6A5,
+0xFFE2F0F0,
+0xFFDCECEB,
+0xFFE0F0EF,
+0xFF778786,
+0xFF243735,
+0xFF687A7A,
+0xFFDBEDED,
+0xFFA2B6B5,
+0xFF99ADAE,
+0xFF92A5A9,
+0xFF4C5F63,
+0xFFDFF2F8,
+0xFFB7CAD0,
+0xFF465960,
+0xFF3A4E57,
+0xFF1B2E3C,
+0xFF1C3240,
+0xFFB0CAD9,
+0xFFBBD6E7,
+0xFFB6D3E5,
+0xFFBAD9EB,
+0xFFB5D6E9,
+0xFFB8D9EA,
+0xFFB8D7E9,
+0xFFB8D7E9,
+0xFFB8D7E9,
+0xFFB9D8EA,
+0xFFB9D8EA,
+0xFFB9D8EA,
+0xFFB9D8EC,
+0xFFB9D8EC,
+0xFFB9D8EC,
+0xFFB8D9EC,
+0xFFB9D8EC,
+0xFFB8D9EC,
+0xFFB9D8EC,
+0xFFB8D9EC,
+0xFFB9D8EC,
+0xFFB8D9EC,
+0xFFBAD9ED,
+0xFFB9DAED,
+0xFFBAD9ED,
+0xFFB9DAED,
+0xFFBAD9ED,
+0xFFB9DAED,
+0xFFBAD9ED,
+0xFFBAD9ED,
+0xFFBAD9ED,
+0xFFBAD9ED,
+0xFFBAD9ED,
+0xFFBAD9ED,
+0xFFBAD9ED,
+0xFFB9DAED,
+0xFFBAD9ED,
+0xFFB9DAED,
+0xFFBAD9ED,
+0xFFB9DAED,
+0xFFBAD9ED,
+0xFFB9DAED,
+0xFFBAD9ED,
+0xFFB9DAED,
+0xFFB9DAED,
+0xFFB9DAED,
+0xFFB8D9EC,
+0xFFB8D9EC,
+0xFFB8D9EC,
+0xFFB8D9EC,
+0xFFB7D8EB,
+0xFFB5D8EB,
+0xFFB7D7EC,
+0xFFB5D8EB,
+0xFFB7D7EC,
+0xFFB4D7EA,
+0xFFB6D6EB,
+0xFFB3D6E9,
+0xFFB3D6EA,
+0xFFB3D6E9,
+0xFFB2D5E9,
+0xFFB2D5E8,
+0xFFB3D6EA,
+0xFFB3D6EA,
+0xFFB5D5EA,
+0xFFB3D6EA,
+0xFFB4D4E9,
+0xFFB2D5E9,
+0xFFB4D4E9,
+0xFFB2D5E9,
+0xFFB4D4EB,
+0xFFB2D5E9,
+0xFFB4D4E9,
+0xFFB2D5E9,
+0xFFB4D4E9,
+0xFFB1D4E8,
+0xFFB3D3E8,
+0xFFB3D4E7,
+0xFFB6D2E7,
+0xFFB5D4E8,
+0xFFB2D5E8,
+0xFFB2D5E8,
+0xFFB2D5E8,
+0xFFB5D4E8,
+0xFFBBD1E8,
+0xFFBBD1E6,
+0xFFB7D6E8,
+0xFFB3D4E5,
+0xFFB7D8E7,
+0xFFB7D2E3,
+0xFFE3F4FF,
+0xFFC1D0E3,
+0xFFB8D2E1,
+0xFFBED6E2,
+0xFFD9E8EF,
+0xFFEAF3F8,
+0xFFE9F0F8,
+0xFFA5B3BC,
+0xFFB8D8E5,
+0xFFB1D8E9,
+0xFFB4D7EB,
+0xFFB5D5EA,
+0xFFB3D6EC,
+0xFFB2D6EC,
+0xFFB4D7EA,
+0xFFB7CEDC,
+0xFFDAD9DF,
+0xFF655055,
+0xFF2A070E,
+0xFF957D8A,
+0xFFC5D6E6,
+0xFFB1D4E8,
+0xFFB0D0E5,
+0xFFB2D2E7,
+0xFFB2D1E6,
+0xFFB0CFE4,
+0xFFB0CFE4,
+0xFFB0D0E5,
+0xFFAFCFE4,
+0xFFADD0E4,
+0xFFADD0E6,
+0xFFABCFE5,
+0xFFABCFE5,
+0xFFABCFE5,
+0xFFACCFE5,
+0xFFACCFE5,
+0xFFAACEE6,
+0xFFA9CFE6,
+0xFFA9CFE6,
+0xFFA9CFE6,
+0xFFA9CFE6,
+0xFFA9CFE6,
+0xFFA9CFE4,
+0xFFA9CFE4,
+0xFFABD1E6,
+0xFFAAD0E5,
+0xFFA9CFE4,
+0xFFAACEE4,
+0xFFABCFE5,
+0xFFABCFE5,
+0xFFACCFE5,
+0xFFABCFE5,
+0xFFABCEE4,
+0xFFACD0E6,
+0xFFADD0E6,
+0xFFAACDE1,
+0xFFABCEE2,
+0xFFAFD2E6,
+0xFFAFD2E6,
+0xFFADD0E4,
+0xFFB0D3E7,
+0xFFAFD2E6,
+0xFFAFD4E7,
+0xFFB0D5E8,
+0xFFAED4E7,
+0xFFACD2E7,
+0xFFACD2E7,
+0xFFADD3E8,
+0xFFAFD3E9,
+0xFFAFD4E7,
+0xFFAFD3E9,
+0xFFAFD3E9,
+0xFFAED2E8,
+0xFFAED2E8,
+0xFFAED2E8,
+0xFFAED2E8,
+0xFFB0D4EA,
+0xFFAED2E8,
+0xFFAED2E8,
+0xFFAFD3E9,
+0xFFAFD3E9,
+0xFFAED1E7,
+0xFFAED1E7,
+0xFFAED2E8,
+0xFFACD2E7,
+0xFFAAD0E3,
+0xFFABD1E4,
+0xFFAAD0E3,
+0xFFAAD0E3,
+0xFFABD0E3,
+0xFFA9CEE1,
+0xFFACCFE2,
+0xFFADD0E3,
+0xFFABCFDF,
+0xFFACCBDD,
+0xFFACCCDB,
+0xFFB1CEDE,
+0xFFB4D1DF,
+0xFFB5D2E0,
+0xFFB6D2E0,
+0xFFC6DDEB,
+0xFFC8DEEC,
+0xFFC9E0EE,
+0xFFC9E3F2,
+0xFFBEDAE8,
+0xFFB4CFE0,
+0xFFAAC7D7,
+0xFFAFCCDE,
+0xFFAEC9DE,
+0xFFAFCADF,
+0xFFB9D5EA,
+0xFFB7D3E8,
+0xFFA9C8DD,
+0xFFA5C4D8,
+0xFFA5C5DA,
+0xFFA4C7DA,
+0xFFC5D1DF,
+0xFFC5D3DE,
+0xFFC7D3DF,
+0xFFC8D4E0,
+0xFFC8D4E0,
+0xFFC9D5E1,
+0xFFC9D5E1,
+0xFFC9D5E1,
+0xFFC9D5E1,
+0xFFCAD6E2,
+0xFFCBD7E3,
+0xFFCBD8E1,
+0xFFCBD7E3,
+0xFFCBD8E1,
+0xFFCBD7E3,
+0xFFCBD7E3,
+0xFFC7D7E4,
+0xFFCBDBE8,
+0xFFBECEDD,
+0xFFB1C1D0,
+0xFFB7C7D6,
+0xFFBBCBDA,
+0xFFBFCFDE,
+0xFFCBD8E8,
+0xFFCEDCE9,
+0xFFD0DEE9,
+0xFFCFDDE8,
+0xFFCDDBE6,
+0xFFCFDBE7,
+0xFFD0DCEA,
+0xFFD0DCEA,
+0xFFD2DEEC,
+0xFFD2DCE8,
+0xFFD3DDE9,
+0xFFD2DCE8,
+0xFFD1DBE7,
+0xFFD2DCE8,
+0xFFD3DDE9,
+0xFFD4DEEA,
+0xFFD3DDE9,
+0xFFD2DCE8,
+0xFFD2DCE8,
+0xFFD2DCE8,
+0xFFD3DDE9,
+0xFFD3DDE9,
+0xFFD3DDE9,
+0xFFD3DDE9,
+0xFFD4DEEA,
+0xFFD4DCE9,
+0xFFD4DCE9,
+0xFFD4DCE9,
+0xFFD3DDE9,
+0xFFD4DCE9,
+0xFFD3DDE9,
+0xFFD3DDE9,
+0xFFD3DDE9,
+0xFFD4DEEA,
+0xFFD1DDE9,
+0xFFD3DDE9,
+0xFFD0DCE8,
+0xFFD2DBEA,
+0xFFD1DDEB,
+0xFFD4DDEC,
+0xFFD2DEEC,
+0xFFD1DFEA,
+0xFFCFE0EA,
+0xFFD1DFEA,
+0xFFCFE0EA,
+0xFFD1DFEC,
+0xFFCFDFEC,
+0xFFCEDEEB,
+0xFFCEDEEB,
+0xFFCEDEEB,
+0xFFCCDEEA,
+0xFFCCDEEA,
+0xFFCDDFEB,
+0xFFCDDFED,
+0xFFCDDFED,
+0xFFCBDDEB,
+0xFFCADCEA,
+0xFFC9DBE9,
+0xFFC8DAE8,
+0xFFC9DAEA,
+0xFFC6D9E8,
+0xFFC6D9E8,
+0xFFC5D8E6,
+0xFFC4D6E0,
+0xFFCADBE2,
+0xFFDAE9EC,
+0xFFC8D6D7,
+0xFF9BAAA7,
+0xFF8A9A97,
+0xFFBFD2D0,
+0xFFBED4D1,
+0xFFD9F2EF,
+0xFFE4FDFA,
+0xFFD9EDEB,
+0xFFE2F5F3,
+0xFFAABDBB,
+0xFF728583,
+0xFF3C4F4D,
+0xFF283C3A,
+0xFFDDF1F0,
+0xFFABBFBE,
+0xFFAABEBF,
+0xFFB0C4C5,
+0xFF6E8185,
+0xFFC8D9E0,
+0xFFDDEEF6,
+0xFF899AA2,
+0xFF82939B,
+0xFF495A64,
+0xFF21333F,
+0xFF1C2F3E,
+0xFF6B8091,
+0xFFD3EAFC,
+0xFFC0DBEC,
+0xFFBBD8E8,
+0xFFBFDCEE,
+0xFFBDDAEA,
+0xFFBCD9E9,
+0xFFBCD9E9,
+0xFFBDD8E9,
+0xFFBED9EA,
+0xFFBED9EA,
+0xFFBED9EA,
+0xFFBDDAEC,
+0xFFBDDAEC,
+0xFFBDDAEC,
+0xFFBBDAEC,
+0xFFBDDAEC,
+0xFFBBDAEC,
+0xFFBDDAEC,
+0xFFBBDAEC,
+0xFFBDDAEC,
+0xFFBBDAEC,
+0xFFBEDBED,
+0xFFBCDBED,
+0xFFBEDBED,
+0xFFBCDBED,
+0xFFBEDBED,
+0xFFBCDBED,
+0xFFBEDBED,
+0xFFBEDBED,
+0xFFBEDBED,
+0xFFBEDBED,
+0xFFBEDBED,
+0xFFBEDBED,
+0xFFBEDBED,
+0xFFBCDBED,
+0xFFBEDBED,
+0xFFBCDBED,
+0xFFBDDAEC,
+0xFFBBDAEC,
+0xFFBDDAEC,
+0xFFBBDAEC,
+0xFFBDDAEC,
+0xFFBBDAEC,
+0xFFBBDAEE,
+0xFFBBDAEE,
+0xFFBBDAEC,
+0xFFBBDAEC,
+0xFFBBDAEC,
+0xFFBBDAEC,
+0xFFBBDAEC,
+0xFFB9DAEB,
+0xFFBAD9ED,
+0xFFB9DAEB,
+0xFFBAD9ED,
+0xFFB9DAEB,
+0xFFBAD9ED,
+0xFFB8D9EA,
+0xFFB8D9EC,
+0xFFB8D9EA,
+0xFFB8D9EC,
+0xFFB8D9EA,
+0xFFB7D8EB,
+0xFFB7D8EB,
+0xFFB8D7EB,
+0xFFB7D8EB,
+0xFFB8D7EB,
+0xFFB6D7EA,
+0xFFB7D6EA,
+0xFFB6D7EA,
+0xFFB7D6EB,
+0xFFB6D7EA,
+0xFFB7D6EA,
+0xFFB6D7EA,
+0xFFB7D6EA,
+0xFFB6D7EA,
+0xFFB7D6EA,
+0xFFB7D6E8,
+0xFFB7D6E8,
+0xFFB6D7E8,
+0xFFB3D8E8,
+0xFFB4D9E9,
+0xFFB4D9E9,
+0xFFB7D8E9,
+0xFFBBD6E9,
+0xFFBBD6E9,
+0xFFB8D9EA,
+0xFFB4D8E6,
+0xFFB7DBE9,
+0xFFBAD7E7,
+0xFFE2F5FF,
+0xFFC0D3E4,
+0xFFBBD7E3,
+0xFFBDD8E1,
+0xFFDAE7EF,
+0xFFEDF2F8,
+0xFFECEFF6,
+0xFFA9B3BC,
+0xFFBDDBE6,
+0xFFB5DAEA,
+0xFFBBD7EC,
+0xFFBBD5EC,
+0xFFBAD9EE,
+0xFFB8D7EC,
+0xFFBAD7E9,
+0xFFC5D3E0,
+0xFFE9DAE1,
+0xFF72494D,
+0xFF4A0C11,
+0xFF7C4D57,
+0xFFD2D9E9,
+0xFFB5D8EB,
+0xFFB2D3E6,
+0xFFB5D4E8,
+0xFFB7D3E8,
+0xFFB4D3E7,
+0xFFB3D2E7,
+0xFFB2D2E7,
+0xFFB1D1E6,
+0xFFAFD2E6,
+0xFFAFD2E6,
+0xFFAED1E5,
+0xFFAED1E5,
+0xFFAED1E5,
+0xFFB0D0E5,
+0xFFAED1E5,
+0xFFADD1E7,
+0xFFADD1E7,
+0xFFACD2E7,
+0xFFACD2E7,
+0xFFACD2E7,
+0xFFACD2E7,
+0xFFADD1E7,
+0xFFADD1E7,
+0xFFADD1E7,
+0xFFAED2E8,
+0xFFAED2E8,
+0xFFAFD2E6,
+0xFFAFD2E6,
+0xFFAFD2E6,
+0xFFB2D2E7,
+0xFFB0D3E7,
+0xFFB3D3E8,
+0xFFB2D5E9,
+0xFFB4D4E9,
+0xFFB3D4E7,
+0xFFB3D4E7,
+0xFFB4D5E8,
+0xFFB3D4E7,
+0xFFB2D3E6,
+0xFFB3D4E7,
+0xFFB3D4E7,
+0xFFB3D4E7,
+0xFFB4D5E8,
+0xFFB2D5E8,
+0xFFB2D5E9,
+0xFFB2D5E9,
+0xFFB3D6EA,
+0xFFB4D7EB,
+0xFFB4D7EA,
+0xFFB3D6EA,
+0xFFB3D6EA,
+0xFFB2D7EA,
+0xFFB2D7EA,
+0xFFB1D7EC,
+0xFFB0D6EB,
+0xFFB0D6EB,
+0xFFB0D6EB,
+0xFFB2D7EA,
+0xFFB2D7EA,
+0xFFB2D5E9,
+0xFFB3D4E7,
+0xFFB3D4E7,
+0xFFB5D6E9,
+0xFFB3D6E9,
+0xFFAED1E4,
+0xFFAFD2E5,
+0xFFAFD2E5,
+0xFFB2D3E4,
+0xFFB2D3E4,
+0xFFAFCFDE,
+0xFFB4D1E1,
+0xFFB0CCDA,
+0xFFB4D0DC,
+0xFFBDD5E1,
+0xFFC4DCE6,
+0xFFCBE1EC,
+0xFFD2E6F1,
+0xFFD4E8F1,
+0xFFD5E7F1,
+0xFFDDEBF4,
+0xFFDAE8F1,
+0xFFD7E8F0,
+0xFFD8EAF4,
+0xFFD5E9F4,
+0xFFCDE0EE,
+0xFFB7CDDB,
+0xFFB2C8D6,
+0xFFB6CBDC,
+0xFFBED3E4,
+0xFFC2D7E8,
+0xFFBED3E4,
+0xFFBCD3E5,
+0xFFB7CEDE,
+0xFFAEC8D9,
+0xFFB4CEDD,
+0xFFC6D2DE,
+0xFFC7D4DD,
+0xFFC8D5DE,
+0xFFCBD5DF,
+0xFFCBD5DF,
+0xFFCCD6E0,
+0xFFCCD6E0,
+0xFFCBD5DF,
+0xFFCCD6E0,
+0xFFCCD6E0,
+0xFFCDD7E1,
+0xFFCED8E2,
+0xFFCED8E2,
+0xFFCFD9E3,
+0xFFCFD9E3,
+0xFFCDDAE3,
+0xFFCBD9E4,
+0xFFCCDCE9,
+0xFFC1D1E0,
+0xFFAFBFCE,
+0xFFB3C0D0,
+0xFFBAC7D7,
+0xFFC2CFDF,
+0xFFC6D4E1,
+0xFFC9D7E2,
+0xFFCFDCE5,
+0xFFD1DEE7,
+0xFFD1DEE7,
+0xFFD4DEE8,
+0xFFD4DEEA,
+0xFFD4DEEA,
+0xFFD5DFEB,
+0xFFD5DDE8,
+0xFFD6DEE9,
+0xFFD5DDE8,
+0xFFD4DCE7,
+0xFFD5DDE8,
+0xFFD7DFEA,
+0xFFD7DFEA,
+0xFFD6DEE9,
+0xFFD6DEE9,
+0xFFD6DEE9,
+0xFFD6DEE9,
+0xFFD6DEE9,
+0xFFD6DEE9,
+0xFFD6DFE8,
+0xFFD6DEE9,
+0xFFD7E0E9,
+0xFFD7DEE8,
+0xFFD7DEE8,
+0xFFD7DEE8,
+0xFFD7DEE8,
+0xFFD7DEE8,
+0xFFD7DEE8,
+0xFFD6DFE8,
+0xFFD6DFE8,
+0xFFD6DFE8,
+0xFFD6DFE8,
+0xFFD7E0E9,
+0xFFD7DFEA,
+0xFFD8E0EB,
+0xFFD7DFEA,
+0xFFD7DFEA,
+0xFFD7DFEA,
+0xFFD5DFE9,
+0xFFD5DFE8,
+0xFFD5DFE9,
+0xFFD5DFE9,
+0xFFD5DFE9,
+0xFFD5DFE9,
+0xFFD5DFE9,
+0xFFD5DFE9,
+0xFFD2DFE8,
+0xFFD2DFE8,
+0xFFD2DFE8,
+0xFFD2DFE8,
+0xFFD2DEEA,
+0xFFD1DDE9,
+0xFFD1DDE9,
+0xFFD0DCE8,
+0xFFD1DDE9,
+0xFFD2DEEA,
+0xFFD2E0ED,
+0xFFD0DEEB,
+0xFFCEDEEB,
+0xFFCCDCE9,
+0xFFCAD8E1,
+0xFFCDDCE3,
+0xFFD6E4E7,
+0xFFD0DEDE,
+0xFF9FADAD,
+0xFF96A6A3,
+0xFF607371,
+0xFF748886,
+0xFF96AFAC,
+0xFF95AEAB,
+0xFFDDF3F0,
+0xFF738986,
+0xFF394D4B,
+0xFF415553,
+0xFF2C403E,
+0xFF90A4A2,
+0xFFCBDFDE,
+0xFF819594,
+0xFF55696A,
+0xFF506264,
+0xFFCDDFE3,
+0xFFD8E7EE,
+0xFFCCDBE2,
+0xFFC9D6DE,
+0xFF56636C,
+0xFF1F2D36,
+0xFF243441,
+0xFF203240,
+0xFF182B3A,
+0xFFB2C7D8,
+0xFFC3DDEC,
+0xFFBCD6E5,
+0xFFC4DEED,
+0xFFBDD7E6,
+0xFFC0DAE9,
+0xFFC0DAE7,
+0xFFC2D9E7,
+0xFFC2D9E7,
+0xFFC2D9E7,
+0xFFC2D9E7,
+0xFFC0DAE9,
+0xFFC0DAE9,
+0xFFBFDAEB,
+0xFFBFDAEB,
+0xFFBFDAEB,
+0xFFBFDAEB,
+0xFFBFDAEB,
+0xFFBFDAEB,
+0xFFC0DBEC,
+0xFFC0DBEC,
+0xFFBFDAEB,
+0xFFBFDAEB,
+0xFFBFDAEB,
+0xFFBFDAEB,
+0xFFBFDAEB,
+0xFFBFDAEB,
+0xFFBFDAEB,
+0xFFBFDAEB,
+0xFFC0DAEB,
+0xFFC0DAEB,
+0xFFC0DAEB,
+0xFFC0DAEB,
+0xFFBFDAEB,
+0xFFC0DBEC,
+0xFFC0DBEC,
+0xFFC0DBEC,
+0xFFBFDAEB,
+0xFFC0DBEC,
+0xFFC0DBEE,
+0xFFC0DBEC,
+0xFFC0DBEE,
+0xFFBEDBED,
+0xFFBFDCEE,
+0xFFBFDCEE,
+0xFFBFDAED,
+0xFFBFDAEB,
+0xFFBFDAEB,
+0xFFBEDBEB,
+0xFFBEDBEB,
+0xFFBEDBEB,
+0xFFBEDBEB,
+0xFFBEDBEB,
+0xFFBEDBED,
+0xFFBDDAEA,
+0xFFBDDAEC,
+0xFFBBDBEA,
+0xFFBBDAEC,
+0xFFBBDBEA,
+0xFFBBDAEC,
+0xFFBBDBEA,
+0xFFBCD9EB,
+0xFFBCD9EB,
+0xFFBCD9EB,
+0xFFBCD9EB,
+0xFFBCD9EB,
+0xFFBAD9EB,
+0xFFBCD8ED,
+0xFFBAD9EB,
+0xFFBCD8ED,
+0xFFBAD9EB,
+0xFFBCD8ED,
+0xFFBAD9EB,
+0xFFBAD9EB,
+0xFFBAD9EB,
+0xFFBAD9EB,
+0xFFBAD9EB,
+0xFFBAD9EB,
+0xFFB9DAEB,
+0xFFB7DBEB,
+0xFFB6DBEB,
+0xFFB8DCEC,
+0xFFBADBEC,
+0xFFBED9EC,
+0xFFBDD8EB,
+0xFFBBDBEA,
+0xFFB7DBE9,
+0xFFBADBEA,
+0xFFBEDBEB,
+0xFFDDF2FF,
+0xFFC3D6E7,
+0xFFBFDBE7,
+0xFFBFDAE3,
+0xFFDBE8F0,
+0xFFEDF2F8,
+0xFFEEEFF4,
+0xFFAAB5BB,
+0xFFC0DDE5,
+0xFFB9DDE9,
+0xFFBFDAEF,
+0xFFC0D6ED,
+0xFFBCD7EC,
+0xFFBDD8ED,
+0xFFC0D9ED,
+0xFFCCD2E0,
+0xFFF7D4DA,
+0xFF844445,
+0xFF731D20,
+0xFF96575F,
+0xFFD9DBE8,
+0xFFB9DAED,
+0xFFB6D5E9,
+0xFFB8D7EB,
+0xFFBAD6EB,
+0xFFB9D5EA,
+0xFFB8D4E9,
+0xFFB5D4E9,
+0xFFB5D4E9,
+0xFFB4D4E9,
+0xFFB3D3E8,
+0xFFB3D3E8,
+0xFFB3D3E8,
+0xFFB3D3E8,
+0xFFB2D2E7,
+0xFFB2D2E7,
+0xFFB2D2E7,
+0xFFB0D3E7,
+0xFFB0D3E7,
+0xFFAFD4E7,
+0xFFB0D3E7,
+0xFFB0D3E7,
+0xFFB0D3E7,
+0xFFB0D3E7,
+0xFFAFD2E6,
+0xFFB3D3E8,
+0xFFB4D5E8,
+0xFFB5D4E6,
+0xFFB5D4E6,
+0xFFB7D4E6,
+0xFFB7D4E6,
+0xFFB7D4E6,
+0xFFB6D3E5,
+0xFFB6D3E5,
+0xFFB8D5E7,
+0xFFBBD8E8,
+0xFFBBD6E7,
+0xFFB8D3E4,
+0xFFB9D4E5,
+0xFFBBD6E7,
+0xFFB8D3E4,
+0xFFBAD5E6,
+0xFFBBD6E7,
+0xFFB9D4E5,
+0xFFB9D4E5,
+0xFFB9D6E8,
+0xFFBAD7E9,
+0xFFBAD7E9,
+0xFFBBD8EA,
+0xFFB9D8EA,
+0xFFB8D7E9,
+0xFFB7D8E9,
+0xFFB5D8EB,
+0xFFB6D9EC,
+0xFFB5DAED,
+0xFFB5DAED,
+0xFFB4D9EC,
+0xFFB4D9EC,
+0xFFB6D9EC,
+0xFFB6D7EA,
+0xFFB6D5E7,
+0xFFB8D5E5,
+0xFFB8D5E5,
+0xFFB7D4E4,
+0xFFB9D6E8,
+0xFFB7D4E4,
+0xFFBEDBEB,
+0xFFBFDBE9,
+0xFFBBD7E5,
+0xFFB9D3E0,
+0xFFBAD1DF,
+0xFFC4DAE7,
+0xFFC9DDE8,
+0xFFCFE1EB,
+0xFFD7E8F0,
+0xFFDBEAF1,
+0xFFDBE8F0,
+0xFFDAE7ED,
+0xFFDCE7ED,
+0xFFDFE8ED,
+0xFFDDE5E8,
+0xFFDDE5E8,
+0xFFDAE3E8,
+0xFFD9E4EA,
+0xFFDDEAF2,
+0xFFDEECF7,
+0xFFC6D6E3,
+0xFFBCCCD9,
+0xFFC3D3E2,
+0xFFC2D2E1,
+0xFFC3D3E2,
+0xFFC2D2E1,
+0xFFC4D5E5,
+0xFFC8DAE8,
+0xFFC6D8E6,
+0xFFC7DAE8,
+0xFFC8D2DC,
+0xFFCAD4DD,
+0xFFCBD5DE,
+0xFFCCD5DE,
+0xFFCCD5DE,
+0xFFCDD6DF,
+0xFFCDD5E0,
+0xFFCCD4DF,
+0xFFCCD4DF,
+0xFFCDD5E0,
+0xFFCDD5E0,
+0xFFCED6E1,
+0xFFCFD7E2,
+0xFFD0D8E3,
+0xFFD0D8E3,
+0xFFCFD9E3,
+0xFFCCD8E4,
+0xFFC1CFDA,
+0xFFBFCDDA,
+0xFFC0CEDB,
+0xFFC2CEDC,
+0xFFBAC6D4,
+0xFFBECAD8,
+0xFFC3CFDB,
+0xFFC6D2DE,
+0xFFCED8E2,
+0xFFD2DCE6,
+0xFFD2DCE5,
+0xFFD5DEE7,
+0xFFD6DEE9,
+0xFFD5DDE8,
+0xFFD6DEE9,
+0xFFD5DFE9,
+0xFFD5DFE8,
+0xFFD4DEE7,
+0xFFD4DEE7,
+0xFFD5DFE8,
+0xFFD6E0E9,
+0xFFD8E1EA,
+0xFFD7E0E9,
+0xFFD7E0E9,
+0xFFD8E1EA,
+0xFFD8E1EA,
+0xFFD7E0E9,
+0xFFD6DFE8,
+0xFFD6DFE6,
+0xFFD6DFE8,
+0xFFD7E0E7,
+0xFFD8E1E8,
+0xFFD8E1E8,
+0xFFD8E1E8,
+0xFFD8E1E8,
+0xFFD8E1E8,
+0xFFD8E1E8,
+0xFFD8E1E8,
+0xFFD8E1E8,
+0xFFD8E1E8,
+0xFFD8E1E8,
+0xFFDAE1E9,
+0xFFDAE1EB,
+0xFFDAE1EB,
+0xFFDAE1EB,
+0xFFDAE1EB,
+0xFFDAE1EB,
+0xFFDBE2EC,
+0xFFDBE2EA,
+0xFFDBE2EC,
+0xFFDBE2EC,
+0xFFDAE3EC,
+0xFFDAE3EC,
+0xFFDAE3EC,
+0xFFDAE3EC,
+0xFFDAE3EC,
+0xFFDAE3EC,
+0xFFDAE3EC,
+0xFFD9E2EB,
+0xFFD8E0EB,
+0xFFD8E0EB,
+0xFFD7DFEA,
+0xFFD7DFEA,
+0xFFD7DFEA,
+0xFFD7DFEA,
+0xFFD7E1ED,
+0xFFD5DFEB,
+0xFFD4E0EC,
+0xFFD3E0E9,
+0xFFD0DDE5,
+0xFFD3E0E6,
+0xFFD1DCE0,
+0xFFDCE8E8,
+0xFFDDE9E9,
+0xFFDAE9E6,
+0xFFE3F3F2,
+0xFFDBEFED,
+0xFFB8CECC,
+0xFFCBE4E1,
+0xFF7F9593,
+0xFF2F4845,
+0xFF374D4B,
+0xFF324846,
+0xFF3E5452,
+0xFFE2F8F6,
+0xFFA3B7B6,
+0xFF96AAA9,
+0xFF798B8D,
+0xFFE4F6F8,
+0xFFCCDBDE,
+0xFFBDCAD0,
+0xFFD1DEE4,
+0xFFABB6BC,
+0xFF96A0A9,
+0xFF3B454E,
+0xFF1B2934,
+0xFF223241,
+0xFF243644,
+0xFF6A7D8C,
+0xFFD4EAF8,
+0xFFCAE1EF,
+0xFFC8DFED,
+0xFFC7DFEB,
+0xFFC7DDEA,
+0xFFC7DDEA,
+0xFFC9DDE8,
+0xFFC9DDE8,
+0xFFC8DBE9,
+0xFFC8DBE9,
+0xFFC6DCEA,
+0xFFC6DCEA,
+0xFFC5DCEA,
+0xFFC5DCEA,
+0xFFC5DCEA,
+0xFFC5DCEA,
+0xFFC5DCEA,
+0xFFC5DCEA,
+0xFFC5DCEA,
+0xFFC5DCEA,
+0xFFC4DBE9,
+0xFFC4DBE9,
+0xFFC4DBE9,
+0xFFC4DBE9,
+0xFFC4DBE9,
+0xFFC4DBE9,
+0xFFC4DBE9,
+0xFFC3DAE8,
+0xFFC3DAEA,
+0xFFC3DAEA,
+0xFFC3DAEA,
+0xFFC3DAEA,
+0xFFC4DBEB,
+0xFFC4DBEB,
+0xFFC2DCEB,
+0xFFC2DCEB,
+0xFFC2DCEB,
+0xFFC3DDEC,
+0xFFC3DDEE,
+0xFFC2DCEB,
+0xFFC2DCED,
+0xFFC1DCED,
+0xFFC1DCED,
+0xFFC1DDEB,
+0xFFC1DBEA,
+0xFFC1DBEA,
+0xFFC1DBEA,
+0xFFC1DBEA,
+0xFFC1DBEA,
+0xFFC0DCEA,
+0xFFC1DDEB,
+0xFFC1DDEB,
+0xFFC0DBEC,
+0xFFC0DCEA,
+0xFFC0DBEC,
+0xFFBFDCEA,
+0xFFBFDCEC,
+0xFFBFDCEA,
+0xFFBFDCEC,
+0xFFBFDCEA,
+0xFFC0DBEC,
+0xFFC0DBEC,
+0xFFC0DBEC,
+0xFFC0DBEC,
+0xFFC0DBEC,
+0xFFBFDCEC,
+0xFFC0DBEE,
+0xFFBFDCEC,
+0xFFC0DBEE,
+0xFFBFDCEC,
+0xFFC0DBEE,
+0xFFBFDCEC,
+0xFFBFDCEC,
+0xFFBFDCEC,
+0xFFBFDCEC,
+0xFFBFDCEC,
+0xFFBFDCEE,
+0xFFBFDCEE,
+0xFFBDDCEE,
+0xFFBDDCEE,
+0xFFBEDDEF,
+0xFFC0DDEF,
+0xFFC4DAEF,
+0xFFC3D9EE,
+0xFFC0DBEC,
+0xFFC1DEEE,
+0xFFBDDDEC,
+0xFFC2DDEE,
+0xFFDCEFFF,
+0xFFC6D7E9,
+0xFFC5DCEC,
+0xFFC4DAE7,
+0xFFDBE8F0,
+0xFFEAF1F7,
+0xFFEBEEF3,
+0xFFABB6BC,
+0xFFC2DFE7,
+0xFFBEE0EA,
+0xFFC2DBEF,
+0xFFC3D9EE,
+0xFFC6DCF1,
+0xFFC2DBEF,
+0xFFC0D9ED,
+0xFFD7D3E2,
+0xFFFFCFD6,
+0xFF87292A,
+0xFF9B3334,
+0xFFD58D91,
+0xFFDAD8E5,
+0xFFBCDBED,
+0xFFB9D8EA,
+0xFFBDDAEC,
+0xFFBDD8EB,
+0xFFBDD8EB,
+0xFFBCD7EA,
+0xFFBAD6EB,
+0xFFBAD6EB,
+0xFFB8D7EB,
+0xFFB8D7EB,
+0xFFB7D6EA,
+0xFFB7D6EA,
+0xFFB7D6EA,
+0xFFB7D6EA,
+0xFFB9D5EA,
+0xFFB8D5E7,
+0xFFB8D5E5,
+0xFFB8D5E5,
+0xFFB6D6E5,
+0xFFB8D5E7,
+0xFFB8D5E7,
+0xFFB8D5E7,
+0xFFB8D5E7,
+0xFFB9D6E8,
+0xFFBBD6E9,
+0xFFBAD5E6,
+0xFFBAD4E3,
+0xFFBAD4E3,
+0xFFBED5E3,
+0xFFBFD6E4,
+0xFFBFD6E4,
+0xFFBFD5E3,
+0xFFC1D7E5,
+0xFFC2D5E4,
+0xFFBFD2E0,
+0xFFBFD2E0,
+0xFFC3D6E4,
+0xFFCADCEA,
+0xFFCDDFED,
+0xFFD0E2F0,
+0xFFD4E6F4,
+0xFFD3E5F3,
+0xFFCBDDEB,
+0xFFC5D7E5,
+0xFFC3D6E5,
+0xFFC3D6E5,
+0xFFC0D6E4,
+0xFFC1D8E6,
+0xFFBED8E5,
+0xFFBDD9E7,
+0xFFBCD9E7,
+0xFFBADAE9,
+0xFFBAD9EB,
+0xFFB9DAED,
+0xFFB7DAED,
+0xFFB9DAED,
+0xFFBADBEC,
+0xFFBADAE9,
+0xFFBAD7E7,
+0xFFBCD8E6,
+0xFFBFD9E6,
+0xFFC0D7E5,
+0xFFBED4E1,
+0xFFBFD5E3,
+0xFFC1D4E3,
+0xFFCEE1F0,
+0xFFD1E3F1,
+0xFFCDDFED,
+0xFFCBDBE8,
+0xFFC9DAE4,
+0xFFD6E4ED,
+0xFFD9E6EE,
+0xFFDEE9EF,
+0xFFE2EBF2,
+0xFFE2E9EF,
+0xFFE3E8EC,
+0xFFE3E7EA,
+0xFFE7E8EC,
+0xFFE9EAEE,
+0xFFEAEBED,
+0xFFEBECEE,
+0xFFE8ECEF,
+0xFFE4E9ED,
+0xFFE3ECF1,
+0xFFE1EBF4,
+0xFFCAD7E0,
+0xFFC7D3DF,
+0xFFC7D3E1,
+0xFFC1CDDB,
+0xFFC7D3E1,
+0xFFC9D5E3,
+0xFFC6D2E2,
+0xFFC9D7E4,
+0xFFC9D7E4,
+0xFFC3D1DE,
+0xFFC8D2DB,
+0xFFC9D3DC,
+0xFFCBD4DD,
+0xFFCBD4DD,
+0xFFCBD4DD,
+0xFFCCD5DE,
+0xFFCCD4DF,
+0xFFCBD3DE,
+0xFFCDD5E0,
+0xFFCDD5E0,
+0xFFCED6E1,
+0xFFCED6E1,
+0xFFCFD7E2,
+0xFFCFD7E2,
+0xFFD0D8E3,
+0xFFCFD9E3,
+0xFFCAD6E2,
+0xFFC5D3DE,
+0xFFC5D1DF,
+0xFFBBC7D5,
+0xFFBCC8D6,
+0xFFC3CFDD,
+0xFFCAD6E2,
+0xFFC1CDD9,
+0xFFCCD6E0,
+0xFFD2DCE5,
+0xFFD6DFE8,
+0xFFD5DEE7,
+0xFFD5DEE7,
+0xFFD5DEE7,
+0xFFD5DDE8,
+0xFFD5DDE8,
+0xFFD5DFE8,
+0xFFD5DFE8,
+0xFFD5DFE8,
+0xFFD4DEE7,
+0xFFD5DFE8,
+0xFFD7E1EA,
+0xFFD8E1EA,
+0xFFD7E0E9,
+0xFFD7E0E9,
+0xFFD7E0E9,
+0xFFD8E1EA,
+0xFFD8E1EA,
+0xFFD8E1E8,
+0xFFD8E1E8,
+0xFFD8E1E8,
+0xFFD9E2E9,
+0xFFD9E2E7,
+0xFFD9E2E7,
+0xFFD9E2E7,
+0xFFD9E2E7,
+0xFFDAE3E8,
+0xFFDAE3E8,
+0xFFDAE3E8,
+0xFFDAE3E8,
+0xFFDCE5EA,
+0xFFDBE4E9,
+0xFFDBE2EA,
+0xFFDAE1E9,
+0xFFDAE1E9,
+0xFFDBE2EA,
+0xFFDCE3EB,
+0xFFDCE3EB,
+0xFFDEE2EB,
+0xFFDEE2EB,
+0xFFDEE2EB,
+0xFFDDE1EA,
+0xFFDBE2EA,
+0xFFDBE2EA,
+0xFFDBE2EA,
+0xFFDBE2EA,
+0xFFDAE1E9,
+0xFFDBE2EA,
+0xFFDCE3EB,
+0xFFDCE3EB,
+0xFFDBE2EC,
+0xFFDBE2EC,
+0xFFDCE3ED,
+0xFFDDE4EE,
+0xFFDDE4EE,
+0xFFDCE3ED,
+0xFFDCE3ED,
+0xFFD8E1EA,
+0xFFD8E1EA,
+0xFFD8E2EB,
+0xFFD7E2E8,
+0xFFDBE6EA,
+0xFFD0DBDD,
+0xFFD0DBDD,
+0xFFDBE7E7,
+0xFFE2F1EE,
+0xFFCCDCDB,
+0xFF9AADAB,
+0xFF708483,
+0xFF384C4B,
+0xFF1A302E,
+0xFF1B312F,
+0xFF1F3533,
+0xFF586E6C,
+0xFFC3D7D6,
+0xFF6F8382,
+0xFFB1C5C4,
+0xFF647877,
+0xFF7F9191,
+0xFFBDCFCF,
+0xFF808F92,
+0xFFB5C3C6,
+0xFFD1DFE2,
+0xFFB3C1C4,
+0xFF96A1A5,
+0xFFAEB9BF,
+0xFF727F88,
+0xFF192734,
+0xFF1C2C39,
+0xFF374957,
+0xFFE0F3FF,
+0xFFCBDEEC,
+0xFFCEE1EF,
+0xFFCFE3EE,
+0xFFCFE1ED,
+0xFFCFE1EB,
+0xFFCFE0EA,
+0xFFCFE0E8,
+0xFFCFE0EA,
+0xFFCDDFE9,
+0xFFCDDFEB,
+0xFFCDDFEB,
+0xFFCCE0EB,
+0xFFCCE0EB,
+0xFFCCE0EB,
+0xFFCCE0EB,
+0xFFCCE0EB,
+0xFFCCE0EB,
+0xFFCCE0EB,
+0xFFCCE0EB,
+0xFFCBDFEA,
+0xFFCBDFEA,
+0xFFCBDFEA,
+0xFFCBDFEA,
+0xFFCBDFEA,
+0xFFCBDFEA,
+0xFFCADEE9,
+0xFFCADEE9,
+0xFFC9DCEA,
+0xFFC9DCEA,
+0xFFC9DCEA,
+0xFFC9DCEA,
+0xFFC9DCEA,
+0xFFC9DCEA,
+0xFFC7DDEA,
+0xFFC7DDEA,
+0xFFC6DCEA,
+0xFFC6DCEA,
+0xFFC7DDEB,
+0xFFC6DCEA,
+0xFFC4DBE9,
+0xFFC4DBE9,
+0xFFC4DBE9,
+0xFFC5DCEA,
+0xFFC6DCE9,
+0xFFC6DCE9,
+0xFFC6DCE9,
+0xFFC6DCE9,
+0xFFC6DDEB,
+0xFFC6DDEB,
+0xFFC6DDEB,
+0xFFC6DDEB,
+0xFFC6DDEB,
+0xFFC6DDEB,
+0xFFC3DDEA,
+0xFFC3DDEA,
+0xFFC3DDEA,
+0xFFC3DDEA,
+0xFFC3DDEA,
+0xFFC3DDEA,
+0xFFC3DDEA,
+0xFFC3DDEA,
+0xFFC5DCEA,
+0xFFC3DDEC,
+0xFFC3DDEC,
+0xFFC3DDEC,
+0xFFC3DDEC,
+0xFFC3DDEC,
+0xFFC4DEED,
+0xFFC3DFED,
+0xFFC4DEED,
+0xFFC3DFED,
+0xFFC3DFED,
+0xFFC3DFEB,
+0xFFC3DFEB,
+0xFFC2DEEC,
+0xFFC2DDEE,
+0xFFC2DDEE,
+0xFFC2DDEE,
+0xFFC1DEEE,
+0xFFC2DFEF,
+0xFFC3DEEF,
+0xFFC7DCEF,
+0xFFC6DBEC,
+0xFFC2DCEB,
+0xFFC5E1EF,
+0xFFC2DEEC,
+0xFFC5DFEE,
+0xFFDBECFC,
+0xFFC7D8E8,
+0xFFC7DEEC,
+0xFFC6DCE7,
+0xFFDAE9F0,
+0xFFE9F2F7,
+0xFFE8EFF5,
+0xFFA9B6BC,
+0xFFC4E1E7,
+0xFFC0E0EB,
+0xFFC4DEEF,
+0xFFC5DCEE,
+0xFFC4DBEB,
+0xFFC6E0EF,
+0xFFC3DEF1,
+0xFFDFD4E4,
+0xFFFFACAF,
+0xFF8F1C19,
+0xFF871B19,
+0xFFF9B2B6,
+0xFFDAD7E0,
+0xFFC0DCEA,
+0xFFBFDBE9,
+0xFFC2DCEB,
+0xFFC3DAEA,
+0xFFC2D9E9,
+0xFFC2D9E9,
+0xFFBED8E9,
+0xFFBFD9EA,
+0xFFBED9EA,
+0xFFBDD8E9,
+0xFFBDD8E9,
+0xFFBDD6EA,
+0xFFBDD7E8,
+0xFFBDD6EA,
+0xFFBDD7E8,
+0xFFBFD6E4,
+0xFFBFD7E3,
+0xFFBFD7E3,
+0xFFBFD6E4,
+0xFFBFD6E4,
+0xFFBFD6E4,
+0xFFBFD6E6,
+0xFFBFD6E4,
+0xFFC0D5E6,
+0xFFC0D6E4,
+0xFFC2D5E3,
+0xFFC4D8E3,
+0xFFCADCE8,
+0xFFD2E4EE,
+0xFFD8E9F3,
+0xFFDAEBF5,
+0xFFD6E4EF,
+0xFFDCEAF5,
+0xFFD7E5F0,
+0xFFC9D6DF,
+0xFFC8D4E0,
+0xFFD7E4ED,
+0xFFE3F0F9,
+0xFFE5EFF9,
+0xFFE1EBF5,
+0xFFE7F1FB,
+0xFFE7F1FB,
+0xFFDEE8F2,
+0xFFD6E0EC,
+0xFFD5E1ED,
+0xFFD6E2EE,
+0xFFD4E2ED,
+0xFFC8DAE6,
+0xFFC6DAE5,
+0xFFC3D9E6,
+0xFFC2DAE6,
+0xFFC0DAE9,
+0xFFBFDBE9,
+0xFFBEDBEB,
+0xFFBDDAEA,
+0xFFBCD9E9,
+0xFFBFDBE9,
+0xFFBFD9E8,
+0xFFC0D8E4,
+0xFFC5DBE8,
+0xFFCCE0EB,
+0xFFCCDEE8,
+0xFFC8D9E3,
+0xFFCDDBE6,
+0xFFC8D4E0,
+0xFFD2DEEA,
+0xFFDCE6F0,
+0xFFE1EBF5,
+0xFFE3ECF5,
+0xFFDBE4EB,
+0xFFE0E7EF,
+0xFFE6EBF1,
+0xFFE5EAEE,
+0xFFE6E9EE,
+0xFFE9EAEE,
+0xFFECECEE,
+0xFFEEEEF0,
+0xFFEEECEF,
+0xFFEEECEF,
+0xFFEFEDEE,
+0xFFEAE8E9,
+0xFFE9E9EB,
+0xFFE7EBEE,
+0xFFE5EAEE,
+0xFFDCE3E9,
+0xFFC6CFD8,
+0xFFCAD4DE,
+0xFFC2CCD8,
+0xFFC5CFDB,
+0xFFC5CEDD,
+0xFFC0C9D8,
+0xFFC1CAD9,
+0xFFC3CCDB,
+0xFFC1CBD7,
+0xFFC5D1DD,
+0xFFCAD4DE,
+0xFFCBD5DF,
+0xFFCBD5DF,
+0xFFCBD5DF,
+0xFFCAD4DE,
+0xFFC9D3DD,
+0xFFCAD4DE,
+0xFFCCD6E0,
+0xFFCED8E2,
+0xFFCED8E2,
+0xFFCED8E4,
+0xFFCED8E4,
+0xFFCED8E4,
+0xFFCED8E4,
+0xFFCFD9E5,
+0xFFD0DAE6,
+0xFFCDDAE3,
+0xFFCFDCE5,
+0xFFD2DCE8,
+0xFFD1DBE7,
+0xFFCED8E4,
+0xFFCCD6E2,
+0xFFCCD6E2,
+0xFFCDD7E3,
+0xFFD3DBE6,
+0xFFD3DCE5,
+0xFFD3DCE5,
+0xFFD4DDE4,
+0xFFD6DDE5,
+0xFFD7DEE6,
+0xFFD7DEE8,
+0xFFD6DFE8,
+0xFFD4DEE7,
+0xFFD5DFE8,
+0xFFD5DFE8,
+0xFFD5DFE8,
+0xFFD6E0E9,
+0xFFD6E0E9,
+0xFFD7E0E9,
+0xFFD7E0E9,
+0xFFD8E1EA,
+0xFFD8E1EA,
+0xFFD8E1EA,
+0xFFD8E1EA,
+0xFFD8E1E8,
+0xFFD9E2E9,
+0xFFDAE1E9,
+0xFFDAE3EA,
+0xFFD9E2E7,
+0xFFD9E4E8,
+0xFFD9E4E8,
+0xFFDAE5E9,
+0xFFD9E4E8,
+0xFFD9E4E8,
+0xFFD8E3E7,
+0xFFD8E3E7,
+0xFFDAE3E8,
+0xFFDAE3E8,
+0xFFDAE3E8,
+0xFFDBE4E9,
+0xFFDBE4E9,
+0xFFDBE4E9,
+0xFFDBE4E9,
+0xFFDBE4E9,
+0xFFDCE3E9,
+0xFFDCE3E9,
+0xFFDBE2E8,
+0xFFDBE2E8,
+0xFFDCE3E9,
+0xFFDDE4EA,
+0xFFDDE4EA,
+0xFFDBE2E8,
+0xFFDDE4EA,
+0xFFDDE4EA,
+0xFFDCE3EB,
+0xFFDCE3EB,
+0xFFDCE3EB,
+0xFFDCE3EB,
+0xFFDDE4EC,
+0xFFDDE4EC,
+0xFFE0E4ED,
+0xFFDCE3EB,
+0xFFDAE1E9,
+0xFFDDE6ED,
+0xFFDBE4EB,
+0xFFD8E1E8,
+0xFFDBE4EB,
+0xFFDBE4E9,
+0xFFD8E2E4,
+0xFFDCE6E8,
+0xFFE0ECEC,
+0xFFDAE6E6,
+0xFF7B8989,
+0xFF758584,
+0xFF677777,
+0xFF829494,
+0xFF97A7A7,
+0xFFBBCBCB,
+0xFFE1F1F1,
+0xFFEFFFFF,
+0xFFB1C3C3,
+0xFF314343,
+0xFFA4B6B6,
+0xFF3E5050,
+0xFF97A9A9,
+0xFFAEC1BF,
+0xFFBED0D0,
+0xFFBCCCCC,
+0xFFC1D1D1,
+0xFFA4B4B4,
+0xFF7E8E8D,
+0xFF7B8B8B,
+0xFF7C8991,
+0xFF596571,
+0xFF1D2B36,
+0xFF0E1E2B,
+0xFFD7E7F4,
+0xFFD5E5F2,
+0xFFD2E2EF,
+0xFFD6E7F1,
+0xFFD5E3EC,
+0xFFD5E4EB,
+0xFFD6E3EB,
+0xFFD6E3EB,
+0xFFD5E3EC,
+0xFFD5E3EC,
+0xFFD5E3EE,
+0xFFD3E4EE,
+0xFFD5E3EC,
+0xFFD5E3EC,
+0xFFD4E2EB,
+0xFFD5E3EC,
+0xFFD5E3EC,
+0xFFD5E3EC,
+0xFFD5E3EC,
+0xFFD5E3EC,
+0xFFD4E2EB,
+0xFFD4E2EB,
+0xFFD4E2EB,
+0xFFD4E2EB,
+0xFFD4E2EB,
+0xFFD4E2EB,
+0xFFD4E2EB,
+0xFFD3E1EA,
+0xFFD2E3ED,
+0xFFD2E3ED,
+0xFFD1E2EC,
+0xFFD1E2EC,
+0xFFCFE1EB,
+0xFFCFE1EB,
+0xFFCFE1EB,
+0xFFCFE1EB,
+0xFFCDDFEB,
+0xFFCDDFEB,
+0xFFCCE0EB,
+0xFFCCE0EB,
+0xFFCCE0EB,
+0xFFCCE0EB,
+0xFFCCE0EB,
+0xFFCCE0EB,
+0xFFCBDFEA,
+0xFFCBDFEA,
+0xFFCCE0EB,
+0xFFCBDFEA,
+0xFFCADDEB,
+0xFFCADDEB,
+0xFFCADDEB,
+0xFFCADDEB,
+0xFFC7DDEA,
+0xFFC8DEEB,
+0xFFC8DEEB,
+0xFFC7DDEA,
+0xFFC6DEEA,
+0xFFC5DDE9,
+0xFFC5DDE9,
+0xFFC6DEEA,
+0xFFC8E0EC,
+0xFFC7DFEB,
+0xFFC7DDEA,
+0xFFC6DDEB,
+0xFFC6DDEB,
+0xFFC6DDEB,
+0xFFC6DDEB,
+0xFFC6DDEB,
+0xFFC7DEEC,
+0xFFC4DEEB,
+0xFFC5DCEA,
+0xFFC4DEEB,
+0xFFC4DEEB,
+0xFFC3DEE9,
+0xFFC4DFEA,
+0xFFC5E0EB,
+0xFFC6E0ED,
+0xFFC5DFEC,
+0xFFC4DEEB,
+0xFFC2DEEA,
+0xFFC2DEE9,
+0xFFC3DEE9,
+0xFFC7DDEA,
+0xFFC7DDEA,
+0xFFC9E1ED,
+0xFFBFDAE3,
+0xFFC6E3EB,
+0xFFC5E0E9,
+0xFFD7E9F5,
+0xFFC9DBE7,
+0xFFC7DFE9,
+0xFFC5DCE4,
+0xFFDAECF0,
+0xFFE4F2F5,
+0xFFE4F1F7,
+0xFFA7B8BF,
+0xFFC8E5EB,
+0xFFC0E1EA,
+0xFFC3DFED,
+0xFFC4DEED,
+0xFFC3DEE9,
+0xFFC4E0EB,
+0xFFC0E0EF,
+0xFFE8DBE5,
+0xFFEC8483,
+0xFF9C1710,
+0xFF7D1A15,
+0xFFFFD3D4,
+0xFFDBD8DF,
+0xFFC3D9E4,
+0xFFCBDFEA,
+0xFFD9EDF8,
+0xFFDEF0FC,
+0xFFD6E8F4,
+0xFFCCDEEA,
+0xFFC7D9E7,
+0xFFC4D6E4,
+0xFFC6D9E7,
+0xFFC5D8E6,
+0xFFC0D6E3,
+0xFFC5D8E7,
+0xFFCCDFED,
+0xFFCBDEED,
+0xFFC6D8E6,
+0xFFC6D7E1,
+0xFFCADBE3,
+0xFFD3E4EC,
+0xFFD9EAF4,
+0xFFD3E4EE,
+0xFFC7D8E2,
+0xFFC4D4E1,
+0xFFC9DAE4,
+0xFFD0DEEB,
+0xFFDBE9F4,
+0xFFDEEBF4,
+0xFFDCE9F1,
+0xFFE3EDF6,
+0xFFE6F1F7,
+0xFFE4EFF5,
+0xFFE6F1F7,
+0xFFE7F0F7,
+0xFFE3ECF3,
+0xFFDEE7EE,
+0xFFDDE4EA,
+0xFFE2E9F1,
+0xFFE9F0F6,
+0xFFEAF1F7,
+0xFFE8EDF3,
+0xFFE9EEF4,
+0xFFEAEFF5,
+0xFFE9EEF4,
+0xFFE9EEF4,
+0xFFEBEFF8,
+0xFFECF0F9,
+0xFFEAEEF7,
+0xFFE6EFF6,
+0xFFE0EDF5,
+0xFFD9E7F0,
+0xFFD0DEE9,
+0xFFC7D8E2,
+0xFFC4D7E5,
+0xFFC2D8E5,
+0xFFC4DAE8,
+0xFFC3DAE8,
+0xFFC2D9E7,
+0xFFC2D8E5,
+0xFFC4D7E5,
+0xFFC9DBE5,
+0xFFDFEDF8,
+0xFFE6F3FC,
+0xFFE9F3FC,
+0xFFE7F0F7,
+0xFFE9F0F8,
+0xFFE2E9F1,
+0xFFDEE5ED,
+0xFFE4E9EF,
+0xFFE8EDF3,
+0xFFE8EBF2,
+0xFFE7EAEF,
+0xFFE9ECF1,
+0xFFECEDF1,
+0xFFE9EAEE,
+0xFFECEBF0,
+0xFFEEEEF0,
+0xFFEDEBEE,
+0xFFEFEDF0,
+0xFFF4F0F1,
+0xFFF2EEEF,
+0xFFF2EEEF,
+0xFFEEECED,
+0xFFEBEBED,
+0xFFEBECF0,
+0xFFD0D3D8,
+0xFFD7DEE4,
+0xFFCFD8E1,
+0xFFC3CBD6,
+0xFFC9D1DE,
+0xFFC7CFDC,
+0xFFC3CADA,
+0xFFBEC5D5,
+0xFFBEC5D5,
+0xFFBFC8D7,
+0xFFC2CBDA,
+0xFFC3CCDB,
+0xFFC9D3DD,
+0xFFCAD4DE,
+0xFFCBD5DF,
+0xFFCBD5DF,
+0xFFCBD5DF,
+0xFFCBD5DF,
+0xFFCCD6E0,
+0xFFCDD7E1,
+0xFFCDD7E1,
+0xFFCED8E2,
+0xFFCED8E4,
+0xFFCED8E4,
+0xFFCED8E4,
+0xFFCED8E4,
+0xFFCFD9E5,
+0xFFD0DAE6,
+0xFFCEDBE4,
+0xFFCFDCE5,
+0xFFD2DCE8,
+0xFFD2DCE8,
+0xFFD1DBE7,
+0xFFD0DAE6,
+0xFFD0DAE6,
+0xFFD0DAE4,
+0xFFD3DBE6,
+0xFFD3DCE5,
+0xFFD4DDE4,
+0xFFD5DEE5,
+0xFFD7DEE6,
+0xFFD7DEE6,
+0xFFD7DEE8,
+0xFFD6DFE8,
+0xFFD5DEE7,
+0xFFD4DEE7,
+0xFFD6DFE8,
+0xFFD6E0E9,
+0xFFD7E0E9,
+0xFFD8E1EA,
+0xFFD8E1EA,
+0xFFD8E1EA,
+0xFFD9E0EA,
+0xFFD8E1EA,
+0xFFD8DFE9,
+0xFFD7E0E9,
+0xFFD9E0E8,
+0xFFDAE1E9,
+0xFFDBE2EA,
+0xFFDCE3EB,
+0xFFDAE3EA,
+0xFFD9E4E8,
+0xFFDAE3E8,
+0xFFD9E4E8,
+0xFFDAE3E8,
+0xFFDAE5E9,
+0xFFDBE4E9,
+0xFFDBE4E9,
+0xFFDBE4E9,
+0xFFDBE4E9,
+0xFFDBE2E8,
+0xFFDAE3E8,
+0xFFDBE2E8,
+0xFFDBE4E9,
+0xFFDDE4EA,
+0xFFDDE4EA,
+0xFFDCE3E9,
+0xFFDDE4EA,
+0xFFDEE5EB,
+0xFFDDE4EA,
+0xFFDDE4EA,
+0xFFDDE4EA,
+0xFFDDE4EA,
+0xFFDCE3E9,
+0xFFDDE4EA,
+0xFFDDE4EA,
+0xFFDDE4EC,
+0xFFDEE5ED,
+0xFFDEE5ED,
+0xFFDDE4EC,
+0xFFDDE4EC,
+0xFFDDE4EA,
+0xFFDBE0E6,
+0xFFDEE3E9,
+0xFFDCE3E9,
+0xFFDDE4EA,
+0xFFDCE5EA,
+0xFFDDE6EB,
+0xFFDEE7EC,
+0xFFD7E0E5,
+0xFFD9E3E5,
+0xFFD7E1E3,
+0xFFD7E3E3,
+0xFFC9D5D5,
+0xFFCCDADA,
+0xFFD3E1E1,
+0xFFDDEBEC,
+0xFFA4B2B3,
+0xFFDFEDEE,
+0xFFD9E7E8,
+0xFFDDEBEC,
+0xFFCFDDDE,
+0xFF314141,
+0xFF657575,
+0xFF9FB1B1,
+0xFF768888,
+0xFFBBCECC,
+0xFFBCCFCD,
+0xFFBACAC9,
+0xFFBCCCCB,
+0xFFB9C9C8,
+0xFFA9B9B8,
+0xFFA5B5B2,
+0xFFADBDBC,
+0xFF8C979D,
+0xFF7C8690,
+0xFF66737C,
+0xFF212D39,
+0xFF94A0AC,
+0xFFE4F0FC,
+0xFFD9E5F1,
+0xFFD6E3EC,
+0xFFDAE4ED,
+0xFFDAE5EB,
+0xFFDBE4EB,
+0xFFDAE5EB,
+0xFFDAE5EB,
+0xFFD8E5ED,
+0xFFD8E5ED,
+0xFFD8E5ED,
+0xFFD9E6EE,
+0xFFDBE6EC,
+0xFFDBE5EE,
+0xFFDAE5EB,
+0xFFDAE4ED,
+0xFFDAE5EB,
+0xFFDBE5EE,
+0xFFDBE6EC,
+0xFFDBE5EE,
+0xFFDAE5EB,
+0xFFDAE4ED,
+0xFFDAE5EB,
+0xFFDBE5EE,
+0xFFDAE5EB,
+0xFFDAE4ED,
+0xFFD8E5ED,
+0xFFD8E5ED,
+0xFFD8E5ED,
+0xFFD7E4EC,
+0xFFD6E5EC,
+0xFFD6E5EC,
+0xFFD6E5EC,
+0xFFD5E4EB,
+0xFFD5E4EB,
+0xFFD7E5EE,
+0xFFD7E5EE,
+0xFFD5E6EE,
+0xFFD5E6EE,
+0xFFD5E6EE,
+0xFFD4E5ED,
+0xFFD4E5ED,
+0xFFD5E6EE,
+0xFFD3E4EC,
+0xFFD3E4EC,
+0xFFD2E3ED,
+0xFFD2E3ED,
+0xFFD1E2EC,
+0xFFD1E2EC,
+0xFFD2E3ED,
+0xFFD2E3ED,
+0xFFCFE1EB,
+0xFFCFE1EB,
+0xFFCFE1EB,
+0xFFCFE1EB,
+0xFFCDE1EA,
+0xFFCDE1EA,
+0xFFCDE1EA,
+0xFFCDE1EA,
+0xFFCBDFE8,
+0xFFCBDFE8,
+0xFFCADEE9,
+0xFFCADEE9,
+0xFFCBDFEA,
+0xFFCADEE9,
+0xFFCADEE9,
+0xFFC9DDE8,
+0xFFC9DFEA,
+0xFFC8DEE9,
+0xFFC8DEE9,
+0xFFC9DFEA,
+0xFFC9DFEA,
+0xFFC8DEE9,
+0xFFC8DFE7,
+0xFFC8DFE7,
+0xFFC8DCE5,
+0xFFC9DDE6,
+0xFFCADEE7,
+0xFFCBDFE8,
+0xFFCBE2E8,
+0xFFCEE2E9,
+0xFFD1E2EA,
+0xFFD2E3EB,
+0xFFD3E4EB,
+0xFFCDE0E6,
+0xFFD0E5EA,
+0xFFCCE1E6,
+0xFFD8E7EE,
+0xFFD3E0E8,
+0xFFD2E5EB,
+0xFFCFE2E6,
+0xFFDDEBEE,
+0xFFE7F2F6,
+0xFFE5F2F8,
+0xFFA6B7BF,
+0xFFCAE1E9,
+0xFFC4DFE8,
+0xFFC7E1EE,
+0xFFC8E3EE,
+0xFFC8E3EA,
+0xFFC0DBE2,
+0xFFC6E2ED,
+0xFFF2DDE4,
+0xFFCF5550,
+0xFFAD1F15,
+0xFFA44C48,
+0xFFFFDBDB,
+0xFFD5D3D6,
+0xFFD5E4E9,
+0xFFE4F1F7,
+0xFFEAF7FD,
+0xFFE9F4FA,
+0xFFE6F1F7,
+0xFFE3EDF6,
+0xFFDFE9F2,
+0xFFDCE9F1,
+0xFFDAE7EF,
+0xFFD6E4ED,
+0xFFD5E3EC,
+0xFFDDEAF3,
+0xFFE4F1FA,
+0xFFE2EFF8,
+0xFFDDE7F0,
+0xFFE0EBF1,
+0xFFE3ECF1,
+0xFFE6EFF6,
+0xFFE7F2F8,
+0xFFE4EDF6,
+0xFFDEE8F1,
+0xFFE0E9F2,
+0xFFE4EDF6,
+0xFFE4EDF6,
+0xFFEAF3FA,
+0xFFE9F0F6,
+0xFFE7EEF4,
+0xFFECF1F5,
+0xFFEDF2F6,
+0xFFEBF0F4,
+0xFFEBF0F3,
+0xFFE9EEF1,
+0xFFEAEFF2,
+0xFFEAEFF2,
+0xFFE8EDF0,
+0xFFE9EDF0,
+0xFFECF0F3,
+0xFFEEF2F5,
+0xFFEEF2F3,
+0xFFEBECEE,
+0xFFEEEFF1,
+0xFFF1F2F6,
+0xFFF0F1F5,
+0xFFEDEEF2,
+0xFFEAEBEF,
+0xFFE7EBEE,
+0xFFE6EBEF,
+0xFFE7EEF4,
+0xFFE1EAF1,
+0xFFDBE4ED,
+0xFFD7E1EA,
+0xFFD3E1EC,
+0xFFD2E3ED,
+0xFFD2E2EF,
+0xFFD0E2EE,
+0xFFCCDCE9,
+0xFFC7D8E2,
+0xFFC8D6DF,
+0xFFD6E3EC,
+0xFFE7F1FA,
+0xFFEDF6FD,
+0xFFEEF3F9,
+0xFFEDF2F6,
+0xFFEEF1F6,
+0xFFE9ECF1,
+0xFFE6E9EE,
+0xFFE8ECEF,
+0xFFECEDF2,
+0xFFEBECF0,
+0xFFEBECF0,
+0xFFECEDF1,
+0xFFEEEFF1,
+0xFFEFEFF1,
+0xFFF0F0F2,
+0xFFF1F1F3,
+0xFFEFEFF1,
+0xFFEFEFF1,
+0xFFF0EEF1,
+0xFFEFEDEE,
+0xFFF0EEF1,
+0xFFF1EFF2,
+0xFFECECEE,
+0xFFEBECF0,
+0xFFCBD0D4,
+0xFFDBE2E8,
+0xFFD8DFE7,
+0xFFD4DDE6,
+0xFFD0D8E3,
+0xFFCAD2DF,
+0xFFC2C9D9,
+0xFFBAC1D1,
+0xFFB6BDCD,
+0xFFB5BECD,
+0xFFBCC5D4,
+0xFFC3CCDB,
+0xFFC6D2DE,
+0xFFC6D2DE,
+0xFFC7D3DF,
+0xFFC8D4E0,
+0xFFC9D5E1,
+0xFFCAD6E2,
+0xFFCBD7E3,
+0xFFCBD7E3,
+0xFFCAD6E2,
+0xFFCBD7E3,
+0xFFCBD7E3,
+0xFFCCD8E4,
+0xFFCCD8E4,
+0xFFCCD8E4,
+0xFFCDD9E5,
+0xFFCDD9E5,
+0xFFCFD9E3,
+0xFFD0DAE4,
+0xFFD1DBE7,
+0xFFD2DCE8,
+0xFFD2DBEA,
+0xFFD2DBEA,
+0xFFD2DCE8,
+0xFFD2DCE6,
+0xFFD3DBE6,
+0xFFD3DCE5,
+0xFFD4DDE4,
+0xFFD5DEE5,
+0xFFD6DFE8,
+0xFFD6DFE8,
+0xFFD6DEE9,
+0xFFD5DDE8,
+0xFFD5DDE8,
+0xFFD5DDE8,
+0xFFD7DDE9,
+0xFFD7DFEA,
+0xFFD9DFEB,
+0xFFD9DFEB,
+0xFFD9DFEB,
+0xFFD9DFEB,
+0xFFDBDFEA,
+0xFFD8DFE9,
+0xFFDADEE9,
+0xFFD8DFE9,
+0xFFDBDFEA,
+0xFFDCE0EB,
+0xFFDEE2ED,
+0xFFDDE4EC,
+0xFFDBE2EA,
+0xFFDAE3EA,
+0xFFDAE1E9,
+0xFFD9E2E9,
+0xFFDAE1E9,
+0xFFDAE3EA,
+0xFFDCE3EB,
+0xFFDDE4EC,
+0xFFDDE4EC,
+0xFFDDE4EC,
+0xFFDDE1EA,
+0xFFDBE2EA,
+0xFFDDE1EA,
+0xFFDCE3EB,
+0xFFDFE3EC,
+0xFFDEE5ED,
+0xFFDDE4EC,
+0xFFDEE7EE,
+0xFFDEE7EE,
+0xFFDCE5EC,
+0xFFDBE4EB,
+0xFFDBE4EB,
+0xFFDCE5EC,
+0xFFDDE6ED,
+0xFFDCE5EC,
+0xFFDDE6ED,
+0xFFDEE7EC,
+0xFFDFE8ED,
+0xFFDEE7EC,
+0xFFDDE6EB,
+0xFFDCE5EA,
+0xFFDCE5EA,
+0xFFDDE4EA,
+0xFFE0E8EB,
+0xFFDFE7EA,
+0xFFDEE6E9,
+0xFFDCE6E8,
+0xFFDDE7E9,
+0xFFDBE5E7,
+0xFFD0DADC,
+0xFFC3CED0,
+0xFFD5E0E2,
+0xFFBDC8CA,
+0xFFAAB5B7,
+0xFF3B4747,
+0xFF2F3B3B,
+0xFF475353,
+0xFF859393,
+0xFFDFEDEE,
+0xFFC9D7D8,
+0xFFCDDDDD,
+0xFF718181,
+0xFF778787,
+0xFFB0C0C0,
+0xFFA9B9B9,
+0xFF95A5A5,
+0xFFA6B6B6,
+0xFFA8B8B8,
+0xFFB5C3C3,
+0xFFC2D0D0,
+0xFFBCCBC8,
+0xFFBDCCC9,
+0xFFAEBDBA,
+0xFFA7B3B3,
+0xFF818C92,
+0xFF8E97A0,
+0xFF78828B,
+0xFF37414B,
+0xFF5E6872,
+0xFFEBF5FF,
+0xFFDAE4ED,
+0xFFE0EBF1,
+0xFFDDE6ED,
+0xFFDDE6EB,
+0xFFDEE5EB,
+0xFFDEE5EB,
+0xFFDEE5EB,
+0xFFDDE6ED,
+0xFFDCE7ED,
+0xFFDCE7ED,
+0xFFDDE6ED,
+0xFFDDE6EB,
+0xFFDDE6ED,
+0xFFDDE6EB,
+0xFFDCE5EC,
+0xFFDCE5EA,
+0xFFDDE6ED,
+0xFFDEE7EC,
+0xFFDDE6ED,
+0xFFDDE6EB,
+0xFFDDE6ED,
+0xFFDDE6EB,
+0xFFDDE6ED,
+0xFFDDE6EB,
+0xFFDDE6ED,
+0xFFDCE5EC,
+0xFFDCE5EC,
+0xFFDBE6EC,
+0xFFDBE6EC,
+0xFFD9E6EC,
+0xFFD9E6EC,
+0xFFD9E6EC,
+0xFFD9E6EC,
+0xFFD9E6EC,
+0xFFD9E6EC,
+0xFFD9E6EC,
+0xFFD8E5EB,
+0xFFD8E5EB,
+0xFFD7E6ED,
+0xFFD7E6ED,
+0xFFD7E6ED,
+0xFFD7E6ED,
+0xFFD9E6EE,
+0xFFD9E6EE,
+0xFFD9E6EF,
+0xFFD9E6EF,
+0xFFD8E5EE,
+0xFFD8E5EE,
+0xFFD8E6EF,
+0xFFD8E6EF,
+0xFFD7E5EE,
+0xFFD7E5EE,
+0xFFD6E4ED,
+0xFFD7E5EE,
+0xFFD7E5EE,
+0xFFD6E4ED,
+0xFFD6E4ED,
+0xFFD3E4EC,
+0xFFD3E4EC,
+0xFFD2E5EC,
+0xFFD2E5EC,
+0xFFD2E5EC,
+0xFFD2E4EE,
+0xFFD2E4EE,
+0xFFD1E3ED,
+0xFFD1E3ED,
+0xFFD0E2EC,
+0xFFCFE1EB,
+0xFFD0E2EC,
+0xFFD0E2EC,
+0xFFD0E3EA,
+0xFFCEE1E8,
+0xFFCEE1E8,
+0xFFCFE0E7,
+0xFFD1DEE4,
+0xFFD7E0E7,
+0xFFDCE3E9,
+0xFFE1E8EE,
+0xFFE4EDF2,
+0xFFE7F0F5,
+0xFFEAF2F5,
+0xFFEDF2F6,
+0xFFEAEFF3,
+0xFFE7EFF2,
+0xFFE7F1F3,
+0xFFE1EBED,
+0xFFE9ECF1,
+0xFFEAEDF2,
+0xFFE9F1F4,
+0xFFE6EEF1,
+0xFFE6EBEE,
+0xFFECF1F5,
+0xFFE8EFF7,
+0xFFAAB4BE,
+0xFFD1DFEA,
+0xFFCBDDE9,
+0xFFC8DEEB,
+0xFFC5DDE7,
+0xFFC9E2E6,
+0xFFCADFE2,
+0xFFCEDDE2,
+0xFFFFE1E1,
+0xFFA51F16,
+0xFFAB180E,
+0xFFC37C78,
+0xFFF2DDDC,
+0xFFE8E6E7,
+0xFFEBF3F5,
+0xFFF2F7FA,
+0xFFEDF2F5,
+0xFFEBEFF2,
+0xFFEDF1F4,
+0xFFEEF2F5,
+0xFFEBEFF2,
+0xFFEBF0F3,
+0xFFEAEFF2,
+0xFFE8EDF1,
+0xFFE7ECF0,
+0xFFE9EEF2,
+0xFFECF1F5,
+0xFFEEF1F6,
+0xFFECEFF4,
+0xFFEEF2F5,
+0xFFEEF2F5,
+0xFFEEF2F5,
+0xFFEBF0F3,
+0xFFEAEDF2,
+0xFFEAEFF3,
+0xFFEDF0F5,
+0xFFEFF2F7,
+0xFFEFF2F7,
+0xFFEFF2F7,
+0xFFF0F1F5,
+0xFFEFF0F4,
+0xFFF1F2F6,
+0xFFF1F2F4,
+0xFFF0F0F2,
+0xFFEDEEF0,
+0xFFEAEEEF,
+0xFFEAEEEF,
+0xFFECF0F1,
+0xFFEDF1F2,
+0xFFF0F1F3,
+0xFFF1F3F2,
+0xFFF0F2F1,
+0xFFEFF1F0,
+0xFFEFF1F0,
+0xFFEEF0EF,
+0xFFF1F2F4,
+0xFFF0F1F3,
+0xFFE7E8EA,
+0xFFE4E5E7,
+0xFFE9EAEC,
+0xFFEBEFF0,
+0xFFEBEFF2,
+0xFFE8EDF1,
+0xFFE6EBF1,
+0xFFE4EBF1,
+0xFFE4EDF6,
+0xFFE3EDF6,
+0xFFE1EBF5,
+0xFFDDEAF3,
+0xFFD3DDE6,
+0xFFCDD7E0,
+0xFFCED9DF,
+0xFFE2EBF2,
+0xFFE9F0F6,
+0xFFEDF2F6,
+0xFFEDEEF2,
+0xFFF0F1F5,
+0xFFEBEFF2,
+0xFFE9EDF0,
+0xFFE8ECEF,
+0xFFE8ECED,
+0xFFEAEEF1,
+0xFFEBEFF0,
+0xFFEBEFF0,
+0xFFECF0F1,
+0xFFEBEFF0,
+0xFFEFF0F2,
+0xFFEDEEF0,
+0xFFEBECEE,
+0xFFE8ECEF,
+0xFFE7EBEE,
+0xFFE8ECEF,
+0xFFECEDEF,
+0xFFEBEAEF,
+0xFFEDECF1,
+0xFFE7E8EC,
+0xFFE7EAEF,
+0xFFC6CBCF,
+0xFFD9E0E6,
+0xFFD5DCE4,
+0xFFD7DEE8,
+0xFFD9DFEB,
+0xFFD5DBE7,
+0xFFCED6E3,
+0xFFC6CDDD,
+0xFFBBC4D3,
+0xFFB3BCCD,
+0xFFB5BECF,
+0xFFBAC6D6,
+0xFFC5D1DD,
+0xFFC5D1DD,
+0xFFC5D1DD,
+0xFFC6D2DE,
+0xFFC7D3DF,
+0xFFC8D4E0,
+0xFFC9D5E1,
+0xFFC9D5E1,
+0xFFC8D4E0,
+0xFFC9D5E1,
+0xFFCAD6E2,
+0xFFCAD6E2,
+0xFFCAD6E2,
+0xFFCBD7E3,
+0xFFCBD7E3,
+0xFFCCD8E4,
+0xFFCED8E2,
+0xFFCED8E2,
+0xFFCFD9E5,
+0xFFD0DAE6,
+0xFFD1DAE9,
+0xFFD1DAE9,
+0xFFD1DBE7,
+0xFFD2DCE8,
+0xFFD2DAE5,
+0xFFD3DCE5,
+0xFFD4DDE6,
+0xFFD5DEE5,
+0xFFD5DEE7,
+0xFFD5DEE7,
+0xFFD5DDE8,
+0xFFD5DDE8,
+0xFFD6DCE8,
+0xFFD6DCE8,
+0xFFD7DDE9,
+0xFFD8DEEA,
+0xFFD9DFEB,
+0xFFD9DFEB,
+0xFFDBDFEB,
+0xFFDBDFEB,
+0xFFDADEE9,
+0xFFDADEE9,
+0xFFD9DDE8,
+0xFFDADEE9,
+0xFFDADEE9,
+0xFFDCE0EB,
+0xFFDDE1EC,
+0xFFDEE2ED,
+0xFFDBE2EA,
+0xFFDAE1E9,
+0xFFDAE1E9,
+0xFFDAE1E9,
+0xFFDAE1E9,
+0xFFDBE2EA,
+0xFFDCE3EB,
+0xFFDCE3EB,
+0xFFDEE2EB,
+0xFFDEE2EB,
+0xFFDDE1EA,
+0xFFDDE1EA,
+0xFFDDE1EA,
+0xFFDEE2EB,
+0xFFDFE3EC,
+0xFFDEE5ED,
+0xFFDEE5ED,
+0xFFDDE6ED,
+0xFFDDE6ED,
+0xFFDBE4EB,
+0xFFDAE3EA,
+0xFFDAE3EA,
+0xFFDCE5EC,
+0xFFDEE7EE,
+0xFFDDE6ED,
+0xFFDEE7EE,
+0xFFDFE8ED,
+0xFFDFE8ED,
+0xFFDEE7EC,
+0xFFDDE6EB,
+0xFFDCE5EA,
+0xFFDBE4E9,
+0xFFDEE6E9,
+0xFFDEE6E9,
+0xFFDDE5E8,
+0xFFE0E8EB,
+0xFFDFE9EB,
+0xFFDFE9EB,
+0xFFDEE8EA,
+0xFFD5E0E2,
+0xFFB2BDBF,
+0xFF8E9C9D,
+0xFFA5B0B2,
+0xFF808E8F,
+0xFFB2BEBE,
+0xFFEEFAFA,
+0xFFDCE8E8,
+0xFFD5E3E3,
+0xFFB6C4C5,
+0xFFBDCDCD,
+0xFF99A9A9,
+0xFF95A5A5,
+0xFF748484,
+0xFF6B7B7B,
+0xFF607070,
+0xFF99A7A8,
+0xFFC0CECF,
+0xFFD4DFE1,
+0xFFC7D2D4,
+0xFFC3CED0,
+0xFFCBD5D6,
+0xFFD6E0E1,
+0xFFA5AFB0,
+0xFF697375,
+0xFFABB4BB,
+0xFFD0D9E2,
+0xFF8A939C,
+0xFF232C35,
+0xFF434C55,
+0xFFEEF7FF,
+0xFFDEE7EE,
+0xFFDDE4EA,
+0xFFDFE6EC,
+0xFFE1E6EA,
+0xFFE1E6EA,
+0xFFE1E6EA,
+0xFFE1E6EC,
+0xFFDFE6EC,
+0xFFDEE7EE,
+0xFFDEE7EC,
+0xFFDEE5EB,
+0xFFDFE6EC,
+0xFFDFE6EC,
+0xFFDEE5EB,
+0xFFDEE5EB,
+0xFFDEE5EB,
+0xFFDFE6EC,
+0xFFE0E7ED,
+0xFFDFE6EC,
+0xFFDEE5EB,
+0xFFDEE5EB,
+0xFFDEE5EB,
+0xFFDFE6EC,
+0xFFDFE6EC,
+0xFFDEE5EB,
+0xFFDEE5EB,
+0xFFDEE5EB,
+0xFFDDE7E9,
+0xFFDDE6EB,
+0xFFDCE7EB,
+0xFFDDE6EB,
+0xFFDCE7EB,
+0xFFDDE6EB,
+0xFFDCE7EB,
+0xFFDEE7EC,
+0xFFDCE7EB,
+0xFFDDE6EB,
+0xFFDCE7EB,
+0xFFDCE7EB,
+0xFFDCE7EB,
+0xFFDCE7ED,
+0xFFDCE7EB,
+0xFFDCE5EC,
+0xFFDDE6ED,
+0xFFDDE6ED,
+0xFFDEE7EE,
+0xFFDEE7EE,
+0xFFDDE6ED,
+0xFFDBE6EC,
+0xFFDBE6EC,
+0xFFDCE7ED,
+0xFFDBE6EC,
+0xFFDBE6EC,
+0xFFDCE7ED,
+0xFFDCE6EF,
+0xFFDCE7ED,
+0xFFDCE6EF,
+0xFFD9E6EC,
+0xFFD9E6EC,
+0xFFD8E7EC,
+0xFFD8E7EC,
+0xFFD8E7EC,
+0xFFD8E7EE,
+0xFFD8E7EE,
+0xFFD8E7EE,
+0xFFD8E7EE,
+0xFFD8E7EE,
+0xFFD7E6ED,
+0xFFD7E6ED,
+0xFFD7E6ED,
+0xFFD6E5EC,
+0xFFD5E4E9,
+0xFFD6E5EA,
+0xFFD9E7EA,
+0xFFE3EBEE,
+0xFFE7EBEE,
+0xFFEDECF1,
+0xFFEFEFF1,
+0xFFEEF2F3,
+0xFFEFF3F4,
+0xFFF2F2F4,
+0xFFF1F1F1,
+0xFFF3F3F5,
+0xFFF3F5F4,
+0xFFF1F5F6,
+0xFFEEF2F1,
+0xFFF2F0F3,
+0xFFF4F2F3,
+0xFFF3F4F6,
+0xFFF1F2F4,
+0xFFEFEFF1,
+0xFFEEEFF4,
+0xFFE9ECF3,
+0xFFB5B9C4,
+0xFFE4EAF6,
+0xFFDDE7F3,
+0xFFD3E3F0,
+0xFFCBDDE7,
+0xFFCBDEE2,
+0xFFD3DFDF,
+0xFFE0DCD9,
+0xFFF4BDB8,
+0xFFA41409,
+0xFF9C0900,
+0xFFEDB3B1,
+0xFFF1E7E6,
+0xFFF3F2F0,
+0xFFF2F4F3,
+0xFFF1F3F2,
+0xFFF2F2F2,
+0xFFF4F4F4,
+0xFFF4F4F4,
+0xFFF3F1F2,
+0xFFF0F0F0,
+0xFFF0F0F0,
+0xFFEFF1F0,
+0xFFEFEFEF,
+0xFFEEF0EF,
+0xFFEEEEF0,
+0xFFEEEEEE,
+0xFFF0F0F2,
+0xFFF2F2F4,
+0xFFF1F1F3,
+0xFFF1F1F3,
+0xFFF1F1F3,
+0xFFF0F1F3,
+0xFFEFF0F2,
+0xFFEFF0F2,
+0xFFEFF0F4,
+0xFFF0F1F3,
+0xFFF0F1F5,
+0xFFEFF0F2,
+0xFFF2F2F4,
+0xFFF4F4F6,
+0xFFF3F3F5,
+0xFFF2F2F4,
+0xFFF1EFF2,
+0xFFEEEEEE,
+0xFFE9EBEA,
+0xFFE7EBEA,
+0xFFE8ECEB,
+0xFFECF0EF,
+0xFFF1F3F2,
+0xFFF1F3F2,
+0xFFF0F2EF,
+0xFFEFF1EE,
+0xFFF2F4F1,
+0xFFEEF0ED,
+0xFFF0F2F1,
+0xFFEFF1F0,
+0xFFE3E5E4,
+0xFFE1E3E2,
+0xFFE9EBEA,
+0xFFEEEFF1,
+0xFFEBECEE,
+0xFFEBECF0,
+0xFFECEDF1,
+0xFFECEFF4,
+0xFFECF1F7,
+0xFFEAF1F7,
+0xFFE8EFF7,
+0xFFE6EDF5,
+0xFFDBE2EA,
+0xFFD9E0E6,
+0xFFDFE6EC,
+0xFFEDF2F6,
+0xFFECEFF4,
+0xFFECEDF1,
+0xFFEEEEF0,
+0xFFF0F1F3,
+0xFFE8E9EB,
+0xFFE8ECED,
+0xFFE8ECED,
+0xFFE7EBEC,
+0xFFE8ECED,
+0xFFEAEEEF,
+0xFFECF0F1,
+0xFFECF0F1,
+0xFFE8ECED,
+0xFFEAEEEF,
+0xFFE7EBEC,
+0xFFE3E8EB,
+0xFFE4E9EC,
+0xFFE2E7EA,
+0xFFE2E7EB,
+0xFFE6EBEE,
+0xFFEAEBF0,
+0xFFE7E8ED,
+0xFFE0E3E8,
+0xFFE2E7EB,
+0xFFC7CCD2,
+0xFFD3DAE0,
+0xFFCFD6DC,
+0xFFD3DAE2,
+0xFFD2D9E3,
+0xFFD0D6E2,
+0xFFCCD2DE,
+0xFFC4CCD9,
+0xFFB9C2D1,
+0xFFB3BCCD,
+0xFFB3BFCF,
+0xFFB9C5D5,
+0xFFC3D1DE,
+0xFFC3D1DE,
+0xFFC3D1DE,
+0xFFC4D2DF,
+0xFFC5D3E0,
+0xFFC5D3E0,
+0xFFC5D3E0,
+0xFFC5D3E0,
+0xFFC5D3DE,
+0xFFC6D4DF,
+0xFFC8D4E0,
+0xFFC9D5E1,
+0xFFC9D5E1,
+0xFFC9D5E1,
+0xFFCAD6E2,
+0xFFCAD6E2,
+0xFFCDD7E1,
+0xFFCED8E2,
+0xFFCFD9E5,
+0xFFD0DAE6,
+0xFFD0D9E8,
+0xFFD0D9E8,
+0xFFD0DAE6,
+0xFFD1DBE7,
+0xFFD1DBE5,
+0xFFD1DBE4,
+0xFFD2DCE5,
+0xFFD3DDE6,
+0xFFD3DDE7,
+0xFFD3DDE7,
+0xFFD3DDE9,
+0xFFD4DCE9,
+0xFFD6DCEA,
+0xFFD6DCEA,
+0xFFD7DDEB,
+0xFFD7DDEB,
+0xFFD8DEEA,
+0xFFD8DEEA,
+0xFFD8DEEA,
+0xFFD8DEEA,
+0xFFD7DDE9,
+0xFFD8DEEA,
+0xFFD8DFE9,
+0xFFD8DFE9,
+0xFFD9E0EA,
+0xFFDAE1EB,
+0xFFDAE1EB,
+0xFFDAE1EB,
+0xFFDBE2EC,
+0xFFDBE2EC,
+0xFFDBE2EC,
+0xFFDBE2EC,
+0xFFDCE3ED,
+0xFFDCE3ED,
+0xFFDCE3ED,
+0xFFDBE2EC,
+0xFFDCE0E9,
+0xFFDCE0E9,
+0xFFDCE0E9,
+0xFFDDE1EA,
+0xFFDEE2EB,
+0xFFDFE3EC,
+0xFFDFE3EC,
+0xFFDEE5ED,
+0xFFDDE4EC,
+0xFFDCE5EC,
+0xFFDCE5EC,
+0xFFDBE4EB,
+0xFFDBE4EB,
+0xFFDBE4EB,
+0xFFDCE5EA,
+0xFFDEE7EC,
+0xFFDEE7EC,
+0xFFDEE7EC,
+0xFFDEE7EC,
+0xFFDEE7EC,
+0xFFDCE5EA,
+0xFFDCE5EA,
+0xFFDBE4E9,
+0xFFDCE5EA,
+0xFFDEE5EB,
+0xFFDFE6EC,
+0xFFDFE7EA,
+0xFFE1E9EC,
+0xFFE0EAEC,
+0xFFDFE9EB,
+0xFFDEE9EB,
+0xFFD7E2E4,
+0xFFCAD8DB,
+0xFF657477,
+0xFF707E81,
+0xFFA7B7B7,
+0xFFACBABA,
+0xFFAAB8B8,
+0xFFAFBEBB,
+0xFFB6C5C2,
+0xFFB5C8C6,
+0xFF99ACAA,
+0xFF7C8F8D,
+0xFF324543,
+0xFF819191,
+0xFF9BABAB,
+0xFFCEDCDF,
+0xFFB6C4C7,
+0xFFC1CCD0,
+0xFFCCD5DA,
+0xFFDDE4EA,
+0xFFB0B7BD,
+0xFF676C72,
+0xFF60656B,
+0xFF464950,
+0xFF1D2228,
+0xFFBABFC5,
+0xFFE9F0F8,
+0xFFF9FFFF,
+0xFF4F565E,
+0xFF20272F,
+0xFFF4FBFF,
+0xFFE0E7EF,
+0xFFE3E8EE,
+0xFFE2E7EB,
+0xFFE3E7EA,
+0xFFE3E7EA,
+0xFFE2E7EA,
+0xFFE2E7EB,
+0xFFE0E8EB,
+0xFFDFE8ED,
+0xFFDFE8ED,
+0xFFDFE6EC,
+0xFFE2E7EB,
+0xFFE2E7EB,
+0xFFE2E7EB,
+0xFFE1E6EA,
+0xFFE1E6EA,
+0xFFE2E7EB,
+0xFFE3E8EC,
+0xFFE2E7EB,
+0xFFE2E7EB,
+0xFFE2E7EB,
+0xFFE2E7EB,
+0xFFE2E7EB,
+0xFFE2E7EB,
+0xFFE2E7EB,
+0xFFE0E8EB,
+0xFFE0E8EB,
+0xFFE0E8EA,
+0xFFE0E8EB,
+0xFFDEE8EA,
+0xFFDFE7EA,
+0xFFDEE8EA,
+0xFFDFE7EA,
+0xFFDEE8EA,
+0xFFE1E9EC,
+0xFFE0EAEC,
+0xFFE1E9EC,
+0xFFDFE9EB,
+0xFFDFE9EB,
+0xFFDFE9EB,
+0xFFDFE8ED,
+0xFFE0EAEC,
+0xFFDFE6EC,
+0xFFDFE6EC,
+0xFFDFE6EC,
+0xFFDFE6EC,
+0xFFDFE6EC,
+0xFFE0E7ED,
+0xFFE0E7ED,
+0xFFE0E7ED,
+0xFFDEE5EB,
+0xFFDEE5EB,
+0xFFDEE5EB,
+0xFFDFE6EC,
+0xFFDEE7EE,
+0xFFDEE7EC,
+0xFFDEE7EE,
+0xFFDEE7EC,
+0xFFDEE7EC,
+0xFFDEE7EC,
+0xFFDEE7EC,
+0xFFDDE6EB,
+0xFFDDE6ED,
+0xFFDDE6ED,
+0xFFDEE7EE,
+0xFFDEE7EE,
+0xFFDDE6ED,
+0xFFDDE6ED,
+0xFFDDE6ED,
+0xFFDCE5EA,
+0xFFDBE4E9,
+0xFFDCE5EA,
+0xFFE0E9EE,
+0xFFE4EEF0,
+0xFFECF1F4,
+0xFFEFF0F2,
+0xFFF2F0F3,
+0xFFF2F0F1,
+0xFFF0F2F1,
+0xFFEEF2F1,
+0xFFF0F0F0,
+0xFFF1F0EE,
+0xFFF2F0F1,
+0xFFF2F2F0,
+0xFFEFF1F0,
+0xFFF1F3F0,
+0xFFF0F0F0,
+0xFFF2F1EF,
+0xFFEFF1F0,
+0xFFF0F0F0,
+0xFFF2F0F3,
+0xFFF0EEF3,
+0xFFEDEEF3,
+0xFFC1C1C9,
+0xFFF7F5FF,
+0xFFEFF1FE,
+0xFFE5EDF8,
+0xFFDDEAF2,
+0xFFDCEAEB,
+0xFFE6E5E1,
+0xFFFFE5DB,
+0xFFD18275,
+0xFFAC150A,
+0xFF9C110A,
+0xFFFFDFE0,
+0xFFF2F0F3,
+0xFFF0F0F0,
+0xFFF0F2EF,
+0xFFEFEFED,
+0xFFF1F0EE,
+0xFFF4F3F1,
+0xFFF2F1EF,
+0xFFF4F0EF,
+0xFFF6F5F3,
+0xFFF1F0EE,
+0xFFEDEDEB,
+0xFFEDECEA,
+0xFFEFEFED,
+0xFFF4F2F3,
+0xFFF4F3F1,
+0xFFF3F1F2,
+0xFFF3F1F2,
+0xFFF3F1F2,
+0xFFF2F0F1,
+0xFFF3F1F2,
+0xFFF4F4F4,
+0xFFF4F4F4,
+0xFFF1F1F1,
+0xFFF1F1F3,
+0xFFF2F2F2,
+0xFFF0F1F3,
+0xFFEFF0F2,
+0xFFF1F2F4,
+0xFFF2F3F5,
+0xFFEDEEF2,
+0xFFE9EAEE,
+0xFFE8E7EC,
+0xFFE7E7E9,
+0xFFE5E6E8,
+0xFFE6EAEB,
+0xFFE9EDEE,
+0xFFECF0F1,
+0xFFECF0EF,
+0xFFEBEFEE,
+0xFFEFF1F0,
+0xFFF1F3F2,
+0xFFF1F3F2,
+0xFFEDEFEE,
+0xFFF1F3F2,
+0xFFF1F3F2,
+0xFFE7E8EA,
+0xFFE3E4E6,
+0xFFE4E8E9,
+0xFFE7E8EA,
+0xFFEBEBED,
+0xFFECECEE,
+0xFFEEEEF0,
+0xFFEEEFF3,
+0xFFEFF0F4,
+0xFFECEFF4,
+0xFFEAEDF4,
+0xFFE8EDF3,
+0xFFE4E9EF,
+0xFFE5EAEE,
+0xFFECF1F5,
+0xFFEDF1F4,
+0xFFEAEEF1,
+0xFFE9EAEE,
+0xFFEEEEF0,
+0xFFEAEBED,
+0xFFEAEBED,
+0xFFEAEEEF,
+0xFFEAEEEF,
+0xFFE8ECED,
+0xFFE8ECED,
+0xFFEAEEEF,
+0xFFEBEFF0,
+0xFFE9EDEE,
+0xFFE6EAED,
+0xFFE8ECEF,
+0xFFE5EAED,
+0xFFE3E8EC,
+0xFFE4E9ED,
+0xFFE0E8EB,
+0xFFDDE4EA,
+0xFFE1E6EA,
+0xFFE0E3EA,
+0xFFD9DCE3,
+0xFFD7DAE1,
+0xFFD6DBE1,
+0xFFC5CACE,
+0xFFC7CCD0,
+0xFFCED3D7,
+0xFFD4D9DF,
+0xFFD5DAE0,
+0xFFD5DCE4,
+0xFFD3D9E5,
+0xFFCAD2DF,
+0xFFC1CAD9,
+0xFFBDC6D5,
+0xFFBAC6D6,
+0xFFB9C6D6,
+0xFFC3D1DE,
+0xFFC3D1DE,
+0xFFC3D1DE,
+0xFFC3D1DE,
+0xFFC4D2DF,
+0xFFC4D2DF,
+0xFFC4D2DF,
+0xFFC4D2DF,
+0xFFC5D3DE,
+0xFFC6D4DF,
+0xFFC8D4E0,
+0xFFC8D4E0,
+0xFFC8D4E0,
+0xFFC8D4E0,
+0xFFC9D5E1,
+0xFFC9D5E1,
+0xFFCDD7E1,
+0xFFCED8E2,
+0xFFCED8E4,
+0xFFCED8E4,
+0xFFCED7E6,
+0xFFCED7E6,
+0xFFCFD9E5,
+0xFFCFD9E5,
+0xFFD0DAE6,
+0xFFD0DAE4,
+0xFFD1DBE5,
+0xFFD1DBE4,
+0xFFD2DCE6,
+0xFFD2DCE6,
+0xFFD2DCE8,
+0xFFD3DDE9,
+0xFFD4DCE9,
+0xFFD4DCE9,
+0xFFD4DCE9,
+0xFFD5DDEA,
+0xFFD5DDE8,
+0xFFD5DDE8,
+0xFFD5DDE8,
+0xFFD5DDE8,
+0xFFD6DEE9,
+0xFFD7DFEA,
+0xFFD7E0E9,
+0xFFD8E1EA,
+0xFFD8E1EA,
+0xFFD8E1EA,
+0xFFD8E1EA,
+0xFFD8E1EA,
+0xFFD9E2EB,
+0xFFD9E2EB,
+0xFFDAE1EB,
+0xFFDAE3EC,
+0xFFDBE2EC,
+0xFFDAE3EC,
+0xFFDAE1EB,
+0xFFD8DFE9,
+0xFFD8DFE7,
+0xFFD9E0E8,
+0xFFDAE1E9,
+0xFFDBE2EA,
+0xFFDCE3EB,
+0xFFDCE3EB,
+0xFFDDE4EC,
+0xFFDDE4EC,
+0xFFDBE2EA,
+0xFFDBE4EB,
+0xFFDBE4EB,
+0xFFDCE5EC,
+0xFFDCE5EC,
+0xFFDBE4EB,
+0xFFDBE4E9,
+0xFFDCE5EA,
+0xFFDEE7EC,
+0xFFDEE7EC,
+0xFFDDE6EB,
+0xFFDCE5EA,
+0xFFDBE4E9,
+0xFFDAE3E8,
+0xFFDBE4E9,
+0xFFDCE5EA,
+0xFFDEE5EB,
+0xFFE2E9EF,
+0xFFE2EAED,
+0xFFE0E8EB,
+0xFFDCE6E8,
+0xFFDDE7E9,
+0xFFDBE6E8,
+0xFFD0DEDF,
+0xFFC0CFD2,
+0xFFC2D1D4,
+0xFFC0CFD2,
+0xFF98A8A8,
+0xFF879797,
+0xFF92A2A1,
+0xFFA3B2AF,
+0xFFA3B3B0,
+0xFFA7B7B4,
+0xFF9CACAB,
+0xFF869695,
+0xFFC1D1D0,
+0xFF9DABAC,
+0xFF9BA9AA,
+0xFFA8B6B9,
+0xFFC0CBD1,
+0xFFB2BBC2,
+0xFF868F98,
+0xFF5A616B,
+0xFF383C47,
+0xFF3C404B,
+0xFF666874,
+0xFF6C6E7A,
+0xFF585B64,
+0xFF82868F,
+0xFFECF1F7,
+0xFFE9F0F8,
+0xFF80878F,
+0xFF262D35,
+0xFFF7FEFF,
+0xFFE2E7ED,
+0xFFDEE3E7,
+0xFFE3E7EA,
+0xFFE3E7EA,
+0xFFE3E7EA,
+0xFFE3E7EA,
+0xFFE2E7EB,
+0xFFE2E7EB,
+0xFFE0E7ED,
+0xFFE0E7ED,
+0xFFE2E7EB,
+0xFFE2E7EB,
+0xFFE2E7EB,
+0xFFE3E8EC,
+0xFFE3E8EC,
+0xFFE3E8EC,
+0xFFE3E8EC,
+0xFFE3E8EC,
+0xFFE2E7EB,
+0xFFE2E7EB,
+0xFFE2E7EB,
+0xFFE2E7EB,
+0xFFE3E8EC,
+0xFFE3E8EC,
+0xFFE3E8EC,
+0xFFE2E7EB,
+0xFFE0E8EA,
+0xFFE0E8EA,
+0xFFE0E8EA,
+0xFFE0E8EA,
+0xFFE0E8EB,
+0xFFE0E8EB,
+0xFFE0E8EB,
+0xFFE0E8EB,
+0xFFE2E7EB,
+0xFFE0E8EB,
+0xFFE1E6EA,
+0xFFDFE7EA,
+0xFFE1E6EA,
+0xFFDFE7EA,
+0xFFE1E6EA,
+0xFFE2E7EB,
+0xFFE3E8EC,
+0xFFE2E7EB,
+0xFFE1E6EA,
+0xFFE1E6EA,
+0xFFE1E6EA,
+0xFFE3E8EC,
+0xFFE5EAEE,
+0xFFE6EBEF,
+0xFFE3E8EC,
+0xFFE4E9ED,
+0xFFE5E8ED,
+0xFFE3E8EC,
+0xFFE3E8EE,
+0xFFE3E8EC,
+0xFFE3E8EE,
+0xFFE4E9ED,
+0xFFE2E7EB,
+0xFFE2E7EB,
+0xFFE3E8EC,
+0xFFE2E7EB,
+0xFFE2E7EB,
+0xFFE2E7EB,
+0xFFE3E8EE,
+0xFFE3E8EC,
+0xFFE0E5EB,
+0xFFE1E6EA,
+0xFFE1E6EC,
+0xFFE1E6EA,
+0xFFE1E6EA,
+0xFFE3E8EC,
+0xFFE8EDF1,
+0xFFEDF2F5,
+0xFFEDF1F2,
+0xFFEFF0F2,
+0xFFF2F0F3,
+0xFFF3F1F2,
+0xFFF2F4F3,
+0xFFF2F4F1,
+0xFFF4F4F4,
+0xFFF5F4F2,
+0xFFF4F2F3,
+0xFFF1F1EF,
+0xFFEFF1F0,
+0xFFF1F3F2,
+0xFFF2F2F2,
+0xFFF1F1F1,
+0xFFF0F0F0,
+0xFFF3F3F3,
+0xFFF1EFF2,
+0xFFEFEFF1,
+0xFFEEEFF3,
+0xFFC0C1C6,
+0xFFF3F1FC,
+0xFFEDEBF8,
+0xFFE4EBF5,
+0xFFE3ECF3,
+0xFFE4EEEF,
+0xFFF6ECE3,
+0xFFFFECDB,
+0xFFB34E3A,
+0xFFA40C00,
+0xFFB4302B,
+0xFFFFEBED,
+0xFFE8EBF0,
+0xFFEDF1F2,
+0xFFF2F4F3,
+0xFFEFEFEF,
+0xFFECECEC,
+0xFFEFEDEE,
+0xFFEFEDEE,
+0xFFEFEDEE,
+0xFFF2F0F1,
+0xFFF0EEEF,
+0xFFEDEDED,
+0xFFEEEEEE,
+0xFFF1F1F1,
+0xFFF3F3F3,
+0xFFF2F2F2,
+0xFFF2F0F1,
+0xFFF2F0F1,
+0xFFF3F1F2,
+0xFFF2F0F1,
+0xFFF2F0F1,
+0xFFF3F3F3,
+0xFFF2F2F2,
+0xFFF1F1F1,
+0xFFF1F1F1,
+0xFFF2F4F3,
+0xFFF0F2F1,
+0xFFEEF2F1,
+0xFFEEEFF1,
+0xFFE8ECEF,
+0xFFE5E6EA,
+0xFFE0E1E6,
+0xFFDFE0E5,
+0xFFE0E1E5,
+0xFFE6E7EB,
+0xFFE5E9EA,
+0xFFE7EBEE,
+0xFFE9EDEE,
+0xFFECEDEF,
+0xFFEDEFEE,
+0xFFEDEEF0,
+0xFFEDEFEE,
+0xFFEDEEF0,
+0xFFEBEDEC,
+0xFFEEEFF1,
+0xFFEFF0F2,
+0xFFE9EAEC,
+0xFFE5E6E8,
+0xFFE7E8EC,
+0xFFE6E7E9,
+0xFFEBEBED,
+0xFFEDEBEE,
+0xFFEDEDEF,
+0xFFEEEEF0,
+0xFFEDEEF2,
+0xFFECEDF1,
+0xFFE9ECF1,
+0xFFE9ECF1,
+0xFFE9ECF1,
+0xFFE9ECF1,
+0xFFECF0F3,
+0xFFE7EBEE,
+0xFFEAEBEF,
+0xFFE7E8EC,
+0xFFEAEAEC,
+0xFFE3E4E6,
+0xFFEAEBED,
+0xFFEAEEEF,
+0xFFEAEEF1,
+0xFFE8ECED,
+0xFFE8ECED,
+0xFFE9EDEE,
+0xFFEBECEE,
+0xFFE7EBEC,
+0xFFE8E9ED,
+0xFFE5E9EC,
+0xFFE1E4E9,
+0xFFDDE2E6,
+0xFFDDE2E8,
+0xFFDCE1E7,
+0xFFDCE1E7,
+0xFFDDE2E8,
+0xFFDCE1E7,
+0xFFDBDEE5,
+0xFFDCE1E7,
+0xFFDBE0E4,
+0xFFD0D5D9,
+0xFFC6CBCF,
+0xFFD6DBDF,
+0xFFDBE0E4,
+0xFFD5DADE,
+0xFFD7DCE2,
+0xFFD5D9E4,
+0xFFCCD2DE,
+0xFFC4CCD9,
+0xFFBCC8D6,
+0xFFB6C2D2,
+0xFFAFBCCC,
+0xFFC2D0DD,
+0xFFC2D0DD,
+0xFFC3D1DE,
+0xFFC3D1DE,
+0xFFC3D1DE,
+0xFFC3D1DE,
+0xFFC4D2DD,
+0xFFC5D3DE,
+0xFFC7D3DF,
+0xFFC7D3DF,
+0xFFC8D5DE,
+0xFFC9D6DF,
+0xFFC9D6DF,
+0xFFC9D6DF,
+0xFFC9D6DF,
+0xFFC9D6DF,
+0xFFCCD6E0,
+0xFFCCD6E0,
+0xFFCCD6E2,
+0xFFCCD6E2,
+0xFFCDD6E5,
+0xFFCDD6E5,
+0xFFCCD8E6,
+0xFFCCD8E4,
+0xFFCDD9E5,
+0xFFCDDAE3,
+0xFFCEDBE4,
+0xFFCEDBE4,
+0xFFCEDAE6,
+0xFFCEDAE6,
+0xFFCFDBE9,
+0xFFD0DCE8,
+0xFFD2DCE8,
+0xFFD2DCE6,
+0xFFD2DCE6,
+0xFFD2DCE6,
+0xFFD2DCE6,
+0xFFD3DDE7,
+0xFFD3DDE7,
+0xFFD4DEE8,
+0xFFD5DFE8,
+0xFFD5DFE8,
+0xFFD5DFE8,
+0xFFD5DFE8,
+0xFFD5E0E6,
+0xFFD6E1E7,
+0xFFD6E1E7,
+0xFFD6E1E7,
+0xFFD6E0E9,
+0xFFD6E0E9,
+0xFFD7E0E9,
+0xFFD7E1EA,
+0xFFD8E1EA,
+0xFFD7E1EA,
+0xFFD6DFE8,
+0xFFD5DEE7,
+0xFFD6DFE6,
+0xFFD7E0E7,
+0xFFD8E1E8,
+0xFFD9E2E9,
+0xFFDAE3EA,
+0xFFDAE3EA,
+0xFFDBE4EB,
+0xFFDBE4EB,
+0xFFDBE2E8,
+0xFFDBE2E8,
+0xFFDCE3E9,
+0xFFDCE3E9,
+0xFFDBE2E8,
+0xFFDAE1E7,
+0xFFDBE2E8,
+0xFFDEE5EB,
+0xFFDDE4EA,
+0xFFDDE4EA,
+0xFFDDE4EA,
+0xFFDCE3E9,
+0xFFDBE2E8,
+0xFFDBE2E8,
+0xFFDCE3E9,
+0xFFDDE4EA,
+0xFFDBE2E8,
+0xFFDEE5EB,
+0xFFDDE4EA,
+0xFFDDE4EA,
+0xFFDBE5E7,
+0xFFDDE7E9,
+0xFFDEE9ED,
+0xFFD5E3E6,
+0xFFABBABD,
+0xFF92A4A6,
+0xFF76888A,
+0xFF758787,
+0xFF91A3A3,
+0xFF99ACAA,
+0xFFAEBEBB,
+0xFFCAD9D6,
+0xFFC3CFCD,
+0xFFA7B3B1,
+0xFF9EAAA8,
+0xFF96A2A2,
+0xFF949FA1,
+0xFF939EA0,
+0xFF8C979B,
+0xFF747D84,
+0xFF757E87,
+0xFF808893,
+0xFF818994,
+0xFF8C929E,
+0xFF8F95A3,
+0xFF828594,
+0xFF8B8E9D,
+0xFF696D79,
+0xFF5F636C,
+0xFFF3F8FE,
+0xFFE7ECF2,
+0xFFCDD2D8,
+0xFF72777D,
+0xFFEBF0F6,
+0xFFE3E6ED,
+0xFFE8EBF0,
+0xFFE6E7EB,
+0xFFE6E7EB,
+0xFFE6E7E9,
+0xFFE4E8E9,
+0xFFE3E8EB,
+0xFFE3E8EC,
+0xFFE1E8EE,
+0xFFE1E8EE,
+0xFFE2E7EB,
+0xFFE2E7EB,
+0xFFE2E7EB,
+0xFFE3E8EC,
+0xFFE4E9ED,
+0xFFE4E9ED,
+0xFFE3E8EC,
+0xFFE2E7EB,
+0xFFE2E7EB,
+0xFFE2E7EB,
+0xFFE2E7EB,
+0xFFE2E7EB,
+0xFFE3E8EC,
+0xFFE3E8EC,
+0xFFE3E8EC,
+0xFFE2E7EB,
+0xFFE2E7EA,
+0xFFE2E7EA,
+0xFFE2E7EA,
+0xFFE2E7EA,
+0xFFE2E7EA,
+0xFFE2E7EA,
+0xFFE2E7EA,
+0xFFE2E7EA,
+0xFFE4E7EC,
+0xFFE3E8EC,
+0xFFE4E7EC,
+0xFFE2E7EB,
+0xFFE3E6EB,
+0xFFE3E8EC,
+0xFFE4E7EC,
+0xFFE4E7EC,
+0xFFE4E8EB,
+0xFFE3E7EA,
+0xFFE2E6E9,
+0xFFE3E7EA,
+0xFFE5E9EC,
+0xFFE7EBEE,
+0xFFE9EDF0,
+0xFFEAEEF1,
+0xFFE9EDF0,
+0xFFEAEEF1,
+0xFFEBECF0,
+0xFFE8ECEF,
+0xFFE6E9EE,
+0xFFE6EAED,
+0xFFE7EAEF,
+0xFFE8ECEF,
+0xFFE3E7EA,
+0xFFE4E8EB,
+0xFFE5E9EC,
+0xFFE5E9EC,
+0xFFE5E9EC,
+0xFFE5E9EC,
+0xFFE4E7EC,
+0xFFE4E8EB,
+0xFFE5E8ED,
+0xFFE5E9EC,
+0xFFE6E9EE,
+0xFFE8ECEF,
+0xFFEBECF0,
+0xFFECEDF1,
+0xFFEFF0F4,
+0xFFF2F3F7,
+0xFFEFF3F6,
+0xFFF1F2F6,
+0xFFF2F0F5,
+0xFFF2F0F3,
+0xFFEFF0F2,
+0xFFEEF0EF,
+0xFFEFEFF1,
+0xFFF0EEEF,
+0xFFF4EFF3,
+0xFFEFEDEE,
+0xFFEEEFF1,
+0xFFF0F1F3,
+0xFFF3F3F5,
+0xFFF1F1F3,
+0xFFF1F1F3,
+0xFFF1F2F4,
+0xFFEBEFF0,
+0xFFEBF1EF,
+0xFFE8F1F0,
+0xFFB4BCBE,
+0xFFE8E8F0,
+0xFFE1E4ED,
+0xFFDEE5ED,
+0xFFDEE7EC,
+0xFFDEE8E9,
+0xFFF6E4DA,
+0xFFFFDAC1,
+0xFF9B280D,
+0xFFA61206,
+0xFFD45A57,
+0xFFFFECF1,
+0xFFE5EAF0,
+0xFFE7ECEF,
+0xFFECF2F2,
+0xFFECF0F1,
+0xFFEDEEF0,
+0xFFF2F2F4,
+0xFFF0F0F2,
+0xFFEBEBED,
+0xFFECEDEF,
+0xFFEEEFF1,
+0xFFEFF0F2,
+0xFFF1F2F4,
+0xFFF2F3F5,
+0xFFF1F2F4,
+0xFFF0F1F3,
+0xFFF1F1F3,
+0xFFF2F2F4,
+0xFFF2F2F4,
+0xFFF2F2F4,
+0xFFF2F2F2,
+0xFFF2F2F2,
+0xFFF2F2F2,
+0xFFF1F3F2,
+0xFFEFF1F0,
+0xFFECF0EF,
+0xFFECF0EF,
+0xFFECF2F0,
+0xFFE7EBEC,
+0xFFE0E5E8,
+0xFFE0E3E8,
+0xFFDDE0E7,
+0xFFDBDEE5,
+0xFFDEE1E8,
+0xFFE5E6EB,
+0xFFE6E7EB,
+0xFFE7E8ED,
+0xFFE8E9ED,
+0xFFECEBF0,
+0xFFEEEEF0,
+0xFFECEBF0,
+0xFFE8E8EA,
+0xFFEBEAEF,
+0xFFEBEBED,
+0xFFECEBF0,
+0xFFEAE9EE,
+0xFFE7E6EB,
+0xFFE6E7EB,
+0xFFE9EAEF,
+0xFFECEDF1,
+0xFFEDEDEF,
+0xFFECECEE,
+0xFFEBEBED,
+0xFFEBEBED,
+0xFFEBECEE,
+0xFFEBECEE,
+0xFFE8ECEF,
+0xFFE8ECEF,
+0xFFE9EDF0,
+0xFFE7EBEE,
+0xFFE6EAED,
+0xFFE5E9EC,
+0xFFE7EBEE,
+0xFFE4E8EB,
+0xFFE4E5E9,
+0xFFE5E6EA,
+0xFFEAEBEF,
+0xFFEAEBEF,
+0xFFE9EAEF,
+0xFFE8E9ED,
+0xFFE9EAEE,
+0xFFE9EAEE,
+0xFFE8E7EC,
+0xFFE4E5E9,
+0xFFE3E2E8,
+0xFFE0E1E6,
+0xFFDDDEE3,
+0xFFD9DCE1,
+0xFFD6D9E0,
+0xFFD7DAE1,
+0xFFD9DCE5,
+0xFFD8DCE5,
+0xFFD5D9E2,
+0xFFD9DEE4,
+0xFFD9DEE4,
+0xFFD9DEE2,
+0xFFD2D7DB,
+0xFFC3C8CB,
+0xFFD9DDE0,
+0xFFD8DCDF,
+0xFFD6DADD,
+0xFFD4D7DC,
+0xFFCED2DB,
+0xFFC6CDD7,
+0xFFC2CAD7,
+0xFFBECAD8,
+0xFFBCC8D8,
+0xFFB8C5D5,
+0xFFBECEDB,
+0xFFBFCFDC,
+0xFFC2D0DD,
+0xFFC3D1DE,
+0xFFC2D0DD,
+0xFFC2D0DD,
+0xFFC4D2DD,
+0xFFC5D3DE,
+0xFFC7D3DF,
+0xFFC8D4E0,
+0xFFC9D5E1,
+0xFFCAD6E2,
+0xFFCAD6E2,
+0xFFC9D5E1,
+0xFFC9D5E1,
+0xFFC9D6DF,
+0xFFCCD6E0,
+0xFFCBD5DF,
+0xFFCBD5E1,
+0xFFCCD6E2,
+0xFFCED7E6,
+0xFFCFD8E7,
+0xFFCDD9E7,
+0xFFCCD8E6,
+0xFFCDD9E7,
+0xFFCDD9E5,
+0xFFCDD9E5,
+0xFFCDDAE3,
+0xFFCDDAE3,
+0xFFCDD9E5,
+0xFFCFDBE7,
+0xFFD0DCE8,
+0xFFCFDCE5,
+0xFFCFDCE5,
+0xFFCEDBE4,
+0xFFCEDBE4,
+0xFFCFDCE5,
+0xFFD0DDE6,
+0xFFD1DEE7,
+0xFFD2DFE8,
+0xFFD4DEE7,
+0xFFD1DEE6,
+0xFFD3DDE6,
+0xFFD3DDE6,
+0xFFD3DEE4,
+0xFFD4DFE5,
+0xFFD5E0E6,
+0xFFD5E0E6,
+0xFFD6E0E9,
+0xFFD6E0E9,
+0xFFD5DFE8,
+0xFFD6E0E9,
+0xFFD7E1EA,
+0xFFD7E1EA,
+0xFFD5DFE8,
+0xFFD4DEE7,
+0xFFD5E0E6,
+0xFFD6E1E7,
+0xFFD6E1E7,
+0xFFD7E2E8,
+0xFFD8E3E9,
+0xFFD8E3E9,
+0xFFD9E4EA,
+0xFFDAE3EA,
+0xFFDBE2EA,
+0xFFDBE2E8,
+0xFFDBE2EA,
+0xFFDAE1E7,
+0xFFD7DEE6,
+0xFFD6DDE3,
+0xFFDAE1E9,
+0xFFDFE6EC,
+0xFFDBE2EA,
+0xFFDCE3E9,
+0xFFDDE4EA,
+0xFFDCE3E9,
+0xFFDCE3E9,
+0xFFDCE3E9,
+0xFFDDE4EA,
+0xFFE0E5EB,
+0xFFE5E9F2,
+0xFFE1E6EC,
+0xFFDDE2E8,
+0xFFDFE7EA,
+0xFFDEE6E9,
+0xFFDBE5E7,
+0xFFDDE8EC,
+0xFFDCE7EB,
+0xFFCCD9DF,
+0xFFB6C5CA,
+0xFFBCCBCE,
+0xFFC0CFD2,
+0xFFCBDBDB,
+0xFFC8D8D7,
+0xFFC4D2D3,
+0xFFBFCBCB,
+0xFFB4BDBC,
+0xFFA4AAAA,
+0xFFB9BDBE,
+0xFFCBCFD0,
+0xFFDDE1E2,
+0xFFFBFFFF,
+0xFFEFF0F4,
+0xFFEFF0F4,
+0xFFD5D4DA,
+0xFF97979F,
+0xFFA5A5AD,
+0xFFACAFB8,
+0xFF9D9FAB,
+0xFF5E626D,
+0xFF353945,
+0xFF363A45,
+0xFF81868C,
+0xFFECF1F7,
+0xFFE2E7ED,
+0xFFE6EBF1,
+0xFFEDF2F8,
+0xFFE6EBF1,
+0xFFE1E4E9,
+0xFFE3E6EB,
+0xFFE5E6EA,
+0xFFE5E6EA,
+0xFFE5E6EA,
+0xFFE3E7EA,
+0xFFE3E7EA,
+0xFFE2E7EA,
+0xFFE2E7EB,
+0xFFE2E7EB,
+0xFFE5E8ED,
+0xFFE4E8EB,
+0xFFE4E8EB,
+0xFFE5E9EC,
+0xFFE7EBEE,
+0xFFE6EBEE,
+0xFFE5E9EC,
+0xFFE3E8EB,
+0xFFE3E8EC,
+0xFFE3E8EC,
+0xFFE3E8EC,
+0xFFE3E8EC,
+0xFFE4E9ED,
+0xFFE4E9ED,
+0xFFE4E9ED,
+0xFFE3E8EC,
+0xFFE2E7EA,
+0xFFE2E7EA,
+0xFFE3E7EA,
+0xFFE2E7EA,
+0xFFE4E8EB,
+0xFFE4E8EB,
+0xFFE5E9EC,
+0xFFE5E9EC,
+0xFFE4E7EC,
+0xFFE3E6EB,
+0xFFE3E6EB,
+0xFFE3E6EB,
+0xFFE3E6EB,
+0xFFE3E6EB,
+0xFFE4E7EC,
+0xFFE4E7EC,
+0xFFE2E6E9,
+0xFFE3E7EA,
+0xFFE4E8EB,
+0xFFE7EBEE,
+0xFFE9EDF0,
+0xFFEBEFF2,
+0xFFEBEFF2,
+0xFFEBEFF2,
+0xFFEFF0F4,
+0xFFEFF0F4,
+0xFFEFF0F4,
+0xFFEDEEF2,
+0xFFEAEBEF,
+0xFFE9EAEE,
+0xFFEBECF0,
+0xFFECEDF1,
+0xFFE9EAEC,
+0xFFE9EDEE,
+0xFFEDEEF0,
+0xFFEEEFF1,
+0xFFEEEFF3,
+0xFFECEDEF,
+0xFFEBECEE,
+0xFFEBECEE,
+0xFFECECEE,
+0xFFECEDEF,
+0xFFEDEEF0,
+0xFFEFF0F2,
+0xFFF2F1F6,
+0xFFF2F2F4,
+0xFFF2F2F4,
+0xFFF1F2F4,
+0xFFEEF1F6,
+0xFFF0F1F6,
+0xFFF1F0F5,
+0xFFF0EFF4,
+0xFFEFF0F4,
+0xFFEEEFF1,
+0xFFEFEFF1,
+0xFFF0EEF1,
+0xFFEFEDF0,
+0xFFEDEBEE,
+0xFFEEEFF1,
+0xFFEEEFF1,
+0xFFF4F4F6,
+0xFFF2F0F3,
+0xFFF2F1F6,
+0xFFEFF0F2,
+0xFFE9EDEE,
+0xFFEBF1F1,
+0xFFE7F0EF,
+0xFFB1B9BB,
+0xFFE4E7EC,
+0xFFE4E7EE,
+0xFFE2E9EF,
+0xFFE0E8EB,
+0xFFE6EAEB,
+0xFFFFE6DB,
+0xFFFFAE91,
+0xFFA01B00,
+0xFFA41A0D,
+0xFFEF8784,
+0xFFFFE5E9,
+0xFFEAEDF2,
+0xFFE8EDF0,
+0xFFECF2F2,
+0xFFE9EDF0,
+0xFFE5E9EC,
+0xFFE6E7EB,
+0xFFE0E1E5,
+0xFFE0E1E5,
+0xFFE9EAEE,
+0xFFEBEFF2,
+0xFFEAEEF1,
+0xFFE9EDF0,
+0xFFEBEFF2,
+0xFFEEF2F5,
+0xFFF2F3F7,
+0xFFF0F1F5,
+0xFFEEEDF2,
+0xFFEFEFF1,
+0xFFF2F2F4,
+0xFFF3F3F3,
+0xFFF1F1F1,
+0xFFF0F2F1,
+0xFFEEF2F3,
+0xFFE9EDEE,
+0xFFE1E7E7,
+0xFFE5EBEB,
+0xFFE6ECEC,
+0xFFDFE4E7,
+0xFFD8DDE1,
+0xFFDBE0E6,
+0xFFDADFE5,
+0xFFD7DBE4,
+0xFFD9DEE4,
+0xFFE0E1E6,
+0xFFE6E7EC,
+0xFFECEBF1,
+0xFFECEBF1,
+0xFFEBEAEF,
+0xFFEBEAEF,
+0xFFEAE9EE,
+0xFFE8E7EC,
+0xFFE8E7EC,
+0xFFECEBF0,
+0xFFECEBF0,
+0xFFE8E7EC,
+0xFFE6E5EB,
+0xFFE6E5EB,
+0xFFE7E8ED,
+0xFFECEDF1,
+0xFFECEBF0,
+0xFFEAEAEC,
+0xFFE8E7EC,
+0xFFE9E9EB,
+0xFFEAEBEF,
+0xFFEBECF0,
+0xFFE9EAEE,
+0xFFE6EAED,
+0xFFE3E7EA,
+0xFFE1E5E8,
+0xFFDDE0E5,
+0xFFE4E7EC,
+0xFFE3E6EB,
+0xFFDEE1E6,
+0xFFDDDEE3,
+0xFFE7E8ED,
+0xFFEDEEF3,
+0xFFEBECF1,
+0xFFE8E9EE,
+0xFFE7E8ED,
+0xFFE7E8ED,
+0xFFE6E7EC,
+0xFFE4E3E9,
+0xFFDFE0E5,
+0xFFDAD9DF,
+0xFFD9DADF,
+0xFFDDDDE5,
+0xFFDFDFE7,
+0xFFDADAE2,
+0xFFD8D8E0,
+0xFFD7DAE3,
+0xFFD3D6DF,
+0xFFD5D8E1,
+0xFFD9DDE6,
+0xFFD2D7DD,
+0xFFD1D6DA,
+0xFFCED3D6,
+0xFFC2C7CA,
+0xFFDCE0E3,
+0xFFD6D9DE,
+0xFFD4D7DC,
+0xFFD1D4DB,
+0xFFCDD1DA,
+0xFFCBD2DC,
+0xFFC8D0DB,
+0xFFC3CDD9,
+0xFFBCC8D8,
+0xFFB7C4D5,
+0xFFBFD1DF,
+0xFFBCCEDC,
+0xFFC0D0DD,
+0xFFC0D0DD,
+0xFFC1CFDA,
+0xFFC2D0DB,
+0xFFC4D0DC,
+0xFFC5D1DD,
+0xFFC4D2DF,
+0xFFC5D3E0,
+0xFFC4D2DF,
+0xFFC5D3E0,
+0xFFC7D5E2,
+0xFFC7D5E2,
+0xFFC9D5E3,
+0xFFC9D5E1,
+0xFFC8D5DE,
+0xFFC9D6DE,
+0xFFC9D6DF,
+0xFFC2CEDA,
+0xFFCAD3E2,
+0xFFCED7E6,
+0xFFD3DCED,
+0xFFCED7E6,
+0xFFD1DAE9,
+0xFFD0DAE6,
+0xFFCFD9E5,
+0xFFCFD9E3,
+0xFFCFD9E3,
+0xFFD1DBE4,
+0xFFD3DDE6,
+0xFFD5DFE8,
+0xFFD3DDE7,
+0xFFD2DCE6,
+0xFFD2DCE6,
+0xFFD3DDE7,
+0xFFD4DEE7,
+0xFFD4DEE7,
+0xFFD4DEE7,
+0xFFD4DEE7,
+0xFFD3DCE5,
+0xFFD3DDE6,
+0xFFD5DEE5,
+0xFFD6DFE6,
+0xFFD5DEE5,
+0xFFD4DDE4,
+0xFFD5DEE5,
+0xFFD6DFE6,
+0xFFD8E1EA,
+0xFFD5DEE7,
+0xFFD9E2E9,
+0xFFD6DFE6,
+0xFFD5DEE5,
+0xFFD8E1E8,
+0xFFD3DCE3,
+0xFFD7E0E7,
+0xFFD5DEE5,
+0xFFD7E0E7,
+0xFFD7E0E7,
+0xFFD6DFE6,
+0xFFD6DFE8,
+0xFFD7E0E9,
+0xFFD8E1EA,
+0xFFD7E0E9,
+0xFFD9E0EA,
+0xFFDAE1E9,
+0xFFD8DFE9,
+0xFFD4DBE3,
+0xFFD2DBE4,
+0xFFD6DFE6,
+0xFFD9E2EB,
+0xFFDAE3EA,
+0xFFD8DFE9,
+0xFFDBE2EA,
+0xFFE0E4ED,
+0xFFE1E5EE,
+0xFFE2E7ED,
+0xFFE3E8EE,
+0xFFE4E9EF,
+0xFFE5E8F1,
+0xFFE5E7F3,
+0xFFE6E9F2,
+0xFFE2E5EA,
+0xFFDFE5E5,
+0xFFE1E7E7,
+0xFFE1E6E9,
+0xFFE9F0F6,
+0xFFDFE6EE,
+0xFFC5CCD6,
+0xFFC0C9D2,
+0xFFC1CAD1,
+0xFFBEC9CD,
+0xFFC2CDD1,
+0xFFD6E1E5,
+0xFFE5F0F6,
+0xFFF0F9FF,
+0xFFFAFDFF,
+0xFFFAF9FE,
+0xFFFFFAFE,
+0xFFFDF7F9,
+0xFFFFFBFC,
+0xFFFEF4F3,
+0xFFFFFBF9,
+0xFFFFFBF8,
+0xFFA99795,
+0xFF463636,
+0xFF6A5C5B,
+0xFF4F4544,
+0xFF2A2627,
+0xFF424244,
+0xFF4E4F53,
+0xFF7F8084,
+0xFFB3B7BA,
+0xFFE3E6EB,
+0xFFE9ECF1,
+0xFFE2E5EA,
+0xFFE1E6EA,
+0xFFE3E8EC,
+0xFFE2E7EB,
+0xFFE2E7EB,
+0xFFE3E6EB,
+0xFFE3E6EB,
+0xFFE3E6EB,
+0xFFE3E7EA,
+0xFFE3E7EA,
+0xFFE4E8EB,
+0xFFE4E8EB,
+0xFFE3E7EA,
+0xFFE6E7E9,
+0xFFE9E9EB,
+0xFFE9EAEC,
+0xFFEBECEE,
+0xFFEEEFF1,
+0xFFECF0F1,
+0xFFEBECEE,
+0xFFE4E8E9,
+0xFFE5E9EC,
+0xFFE3E7EA,
+0xFFE3E7EA,
+0xFFE5E9EC,
+0xFFE6EAED,
+0xFFE5E9EC,
+0xFFE4E7EC,
+0xFFE4E7EC,
+0xFFE3E6EB,
+0xFFE6E9EE,
+0xFFEBECF1,
+0xFFE8EBF0,
+0xFFEAEBF0,
+0xFFEAEBF0,
+0xFFE9EAEF,
+0xFFE7E8ED,
+0xFFE9EAEF,
+0xFFE6E7EC,
+0xFFE6E7EC,
+0xFFE6E7EC,
+0xFFE6E9EE,
+0xFFE7EAEF,
+0xFFE5E8ED,
+0xFFE6E9EE,
+0xFFE4E8EB,
+0xFFE6EAEB,
+0xFFEAEBED,
+0xFFECEDEF,
+0xFFEDEEF0,
+0xFFECEDEF,
+0xFFEBECEE,
+0xFFEAEBED,
+0xFFEFEFF1,
+0xFFF0F0F2,
+0xFFEFEFF1,
+0xFFECECEE,
+0xFFEBEBED,
+0xFFECECEE,
+0xFFEDEDEF,
+0xFFEAEBED,
+0xFFE8E9EB,
+0xFFECEDEF,
+0xFFF0F0F2,
+0xFFF1F1F1,
+0xFFF1F1F3,
+0xFFF2F2F2,
+0xFFF2F2F2,
+0xFFF1F1F1,
+0xFFEFEDEE,
+0xFFF0F0F0,
+0xFFF1F1F1,
+0xFFEFEFEF,
+0xFFEFEFF1,
+0xFFF1F1F3,
+0xFFF1F2F4,
+0xFFF0F1F3,
+0xFFE7EAEF,
+0xFFE8EBF0,
+0xFFECEDF2,
+0xFFEDEEF2,
+0xFFEEEFF3,
+0xFFEEEFF3,
+0xFFEDEEF2,
+0xFFEDECF1,
+0xFFEFEFF1,
+0xFFEEEEF0,
+0xFFECECEE,
+0xFFEBEBED,
+0xFFF1EFF2,
+0xFFF5F3F4,
+0xFFF1EFF2,
+0xFFEAEAEC,
+0xFFEBEAEF,
+0xFFEDEEF3,
+0xFFEEEFF4,
+0xFFB7B8BD,
+0xFFEAEBEF,
+0xFFE8E9ED,
+0xFFE3E6EB,
+0xFFE6E7EB,
+0xFFEDE7E9,
+0xFFFFE4DA,
+0xFFF37857,
+0xFFBD2A08,
+0xFF9F2716,
+0xFFFFC2BD,
+0xFFFFE7E9,
+0xFFEEECF1,
+0xFFF1F1F3,
+0xFFE7E9E8,
+0xFFE8E9EB,
+0xFFE7E8EA,
+0xFFE4E5E7,
+0xFFDBDCDE,
+0xFFDFE3E6,
+0xFFE5E9EC,
+0xFFE7E8EC,
+0xFFEAEBEF,
+0xFFEDEEF2,
+0xFFEDEEF2,
+0xFFECEDF1,
+0xFFEEEDF2,
+0xFFEEEDF2,
+0xFFEFEDF2,
+0xFFEDEBEE,
+0xFFEEECED,
+0xFFF0F0F2,
+0xFFF1F1F3,
+0xFFECEDEF,
+0xFFE2E6E9,
+0xFFDDE1E4,
+0xFFDBE0E3,
+0xFFD9DEE2,
+0xFFD8E0E3,
+0xFFD8E0E3,
+0xFFD8DFE5,
+0xFFD8DFE5,
+0xFFD9E0E6,
+0xFFD9E0E6,
+0xFFDADFE5,
+0xFFE1E2E6,
+0xFFE8E7EC,
+0xFFE9E8ED,
+0xFFE8E7EC,
+0xFFEAE9EE,
+0xFFEDECF1,
+0xFFEAE9EE,
+0xFFE7E6EB,
+0xFFE5E4EA,
+0xFFE8E7ED,
+0xFFE8E9ED,
+0xFFE6E7EB,
+0xFFE4E5E9,
+0xFFE4E5E9,
+0xFFE6E7EB,
+0xFFE8E9ED,
+0xFFEAEBEF,
+0xFFEAEBEF,
+0xFFE5E6EB,
+0xFFE3E4E8,
+0xFFE6E5EB,
+0xFFE5E4EA,
+0xFFE5E4EA,
+0xFFE8E9EE,
+0xFFE3E4E9,
+0xFFE5E6EB,
+0xFFE1E1E9,
+0xFFDDDDE5,
+0xFFDDDDE5,
+0xFFDBDBE3,
+0xFFDBDEE7,
+0xFFE5E8EF,
+0xFFE8ECEF,
+0xFFE8ECEF,
+0xFFE6EAED,
+0xFFE2E5EA,
+0xFFE0E3E8,
+0xFFDEE1E8,
+0xFFDEDEE6,
+0xFFD8DBE2,
+0xFFDDDDE5,
+0xFFD8DBE2,
+0xFFD8DBE4,
+0xFFDCDFE8,
+0xFFDDE0E9,
+0xFFDADDE6,
+0xFFD6D9E0,
+0xFFD3D6DD,
+0xFFDBDEE7,
+0xFFD5D8E1,
+0xFFD1D8E0,
+0xFFD0D7DD,
+0xFFCED6D8,
+0xFFBBC3C5,
+0xFFD5D9E2,
+0xFFD2D6E1,
+0xFFCCD3DD,
+0xFFCAD1DB,
+0xFFCBD1DD,
+0xFFCCD2DE,
+0xFFC9CDD6,
+0xFFC2C9D3,
+0xFFBDC5D8,
+0xFFBAC5DB,
+0xFFBDD0DF,
+0xFFBED1DF,
+0xFFBDCDDC,
+0xFFC1D1DE,
+0xFFC1CFDC,
+0xFFC3D1DC,
+0xFFC7D3DF,
+0xFFC5D1DD,
+0xFFC7D5E2,
+0xFFC4D2DF,
+0xFFC7D5E2,
+0xFFC6D6E3,
+0xFFC4D2DF,
+0xFFC6D4E1,
+0xFFCCD8E6,
+0xFFCBD7E3,
+0xFFCDD9E5,
+0xFFC8D6E1,
+0xFFCBD7E3,
+0xFFC9D5E1,
+0xFFCDD9E5,
+0xFFCCD8E4,
+0xFFCCD8E6,
+0xFFCCD8E6,
+0xFFCDD9E7,
+0xFFCFD8E7,
+0xFFCFD8E7,
+0xFFD0DAE6,
+0xFFD1DBE5,
+0xFFD2DCE5,
+0xFFD1DCE2,
+0xFFD0DBE1,
+0xFFD1DBE4,
+0xFFD3DDE7,
+0xFFD4DEE8,
+0xFFD4DEE8,
+0xFFD3DDE6,
+0xFFD3DDE6,
+0xFFD5DEE7,
+0xFFD6DFE8,
+0xFFD6DFE8,
+0xFFD6DFE8,
+0xFFD6DFE6,
+0xFFD6DFE6,
+0xFFD7DEE6,
+0xFFD8DFE7,
+0xFFD7DEE6,
+0xFFD6DDE5,
+0xFFD5DEE7,
+0xFFD4DDE6,
+0xFFD8E1E8,
+0xFFD7E0E7,
+0xFFD7E0E7,
+0xFFD8E1E8,
+0xFFD6DFE6,
+0xFFD7E0E7,
+0xFFDBE4EB,
+0xFFD9E2E9,
+0xFFD8E1E8,
+0xFFD8E1E8,
+0xFFD9E2EB,
+0xFFD9E2EB,
+0xFFD8E1EA,
+0xFFD7DEE8,
+0xFFDEE5ED,
+0xFFDDE1EA,
+0xFFD7DBE4,
+0xFFCFD6DE,
+0xFFCCD3DB,
+0xFFCFD6DE,
+0xFFD4DBE3,
+0xFFD8DFE7,
+0xFFD8DFE7,
+0xFFDEE2EB,
+0xFFE2E6EF,
+0xFFE3E8EE,
+0xFFE3E6ED,
+0xFFE3E6EB,
+0xFFE4E7EC,
+0xFFE5E5ED,
+0xFFDFDFE9,
+0xFFE0E0EA,
+0xFFE3E7EA,
+0xFFE0E4E5,
+0xFFE6EAEB,
+0xFFE4E9ED,
+0xFFECF0FB,
+0xFFD5D8E7,
+0xFFB9BCCF,
+0xFFBFC4D8,
+0xFFBCC1D4,
+0xFFC2C8D8,
+0xFFA0A7B7,
+0xFF818898,
+0xFF676E81,
+0xFF6A6F82,
+0xFF7E808F,
+0xFFB6B4C1,
+0xFFEDE5F0,
+0xFFE5DAE2,
+0xFFC3B7B9,
+0xFF8B7D7C,
+0xFF594841,
+0xFF3C2821,
+0xFF402722,
+0xFF452C27,
+0xFF442F2A,
+0xFF312320,
+0xFFEEE8E8,
+0xFFFBFBFD,
+0xFFF2F3F7,
+0xFFEEF1F6,
+0xFFECEFF4,
+0xFFE8EDF1,
+0xFFE3E6EB,
+0xFFE3E8EC,
+0xFFE3E8EC,
+0xFFE1E6EA,
+0xFFE4E9ED,
+0xFFDCE1E5,
+0xFFE3E6EB,
+0xFFE8EBF0,
+0xFFEDF0F5,
+0xFFECEFF4,
+0xFFE8EBF0,
+0xFFE5E9EC,
+0xFFE4E8EB,
+0xFFE4E8EB,
+0xFFEAEAEC,
+0xFFEBEBED,
+0xFFEBEBED,
+0xFFE9EAEC,
+0xFFE9EAEC,
+0xFFE8ECED,
+0xFFE9EAEC,
+0xFFE6EAEB,
+0xFFE8ECED,
+0xFFE9EDEE,
+0xFFE8ECEF,
+0xFFE7EBEE,
+0xFFE8ECEF,
+0xFFE8ECEF,
+0xFFE6E9EE,
+0xFFE4E7EC,
+0xFFE4E5EA,
+0xFFE9EAEF,
+0xFFEBECF1,
+0xFFE9EAEF,
+0xFFE8E9EE,
+0xFFEAEBF0,
+0xFFEAEBF0,
+0xFFE7E8ED,
+0xFFE4E5EA,
+0xFFE5E6EB,
+0xFFE9EAEF,
+0xFFEBECF1,
+0xFFE9ECF1,
+0xFFE8EBF0,
+0xFFE6E9EE,
+0xFFE7EAEF,
+0xFFE7EBEE,
+0xFFE7EBEC,
+0xFFE9EAEC,
+0xFFE9EAEC,
+0xFFE9EAEC,
+0xFFE9EAEC,
+0xFFEAEBED,
+0xFFEAEBED,
+0xFFEDEDEF,
+0xFFEFEFF1,
+0xFFEFEFF1,
+0xFFEDEDEF,
+0xFFEBEBED,
+0xFFECECEE,
+0xFFEBEBED,
+0xFFE9E9EB,
+0xFFE5E6E8,
+0xFFE8E9EB,
+0xFFEDEDEF,
+0xFFF1F1F1,
+0xFFF2F2F2,
+0xFFF1F1F1,
+0xFFF1EFF0,
+0xFFF1F0EE,
+0xFFF2F0F1,
+0xFFF1F1F1,
+0xFFF0F0F0,
+0xFFEEEEEE,
+0xFFEEEEEE,
+0xFFF0F0F2,
+0xFFEEEFF1,
+0xFFECEDF1,
+0xFFE7EBEE,
+0xFFE7EBEE,
+0xFFE8EBF0,
+0xFFEAEEF1,
+0xFFECEDF1,
+0xFFECEDF1,
+0xFFEBECF0,
+0xFFEAEBEF,
+0xFFEBECF0,
+0xFFE9EAEC,
+0xFFE9E8ED,
+0xFFEBEBED,
+0xFFEBEBED,
+0xFFE8E8EA,
+0xFFE6E6E8,
+0xFFE7E7E9,
+0xFFEBEAEF,
+0xFFEEEFF4,
+0xFFEEEEF6,
+0xFFB4B7BE,
+0xFFE7E8EC,
+0xFFE6E7E9,
+0xFFE6E7EB,
+0xFFEAE9E7,
+0xFFF4EADE,
+0xFFFFDCC4,
+0xFFD3401F,
+0xFFB81700,
+0xFFB65243,
+0xFFFFE5E1,
+0xFFF0DEDE,
+0xFFEDEDEF,
+0xFFEBEBED,
+0xFFE7E7E9,
+0xFFE7E8EA,
+0xFFE8E9EB,
+0xFFE5E6E8,
+0xFFE0E1E5,
+0xFFE1E5E8,
+0xFFE4E8EB,
+0xFFE9EAEE,
+0xFFEBECF0,
+0xFFECEDF1,
+0xFFECEDF1,
+0xFFEDECF1,
+0xFFEDECF1,
+0xFFEEEDF2,
+0xFFEEEEF0,
+0xFFEDEBEE,
+0xFFEDEDED,
+0xFFEEEEF0,
+0xFFECEDEF,
+0xFFEAEBEF,
+0xFFE4E8EB,
+0xFFE0E3E8,
+0xFFDCE1E5,
+0xFFDADFE3,
+0xFFDCE1E5,
+0xFFDDE2E8,
+0xFFD9E1E4,
+0xFFDBE0E6,
+0xFFDBE3E6,
+0xFFE0E5EB,
+0xFFE1E6EA,
+0xFFE4E8EB,
+0xFFE8E9ED,
+0xFFE7E8EC,
+0xFFE5E6EA,
+0xFFE7E8EC,
+0xFFE7E8EC,
+0xFFE6E7EC,
+0xFFE6E7EC,
+0xFFE3E4E9,
+0xFFE4E5EA,
+0xFFE3E6EB,
+0xFFE2E6E9,
+0xFFE3E7EA,
+0xFFE5E9EC,
+0xFFE7EBEE,
+0xFFE7EBEE,
+0xFFEAEEF1,
+0xFFE8ECEF,
+0xFFE5E6EB,
+0xFFE4E5E9,
+0xFFE5E6EB,
+0xFFE3E4E8,
+0xFFE0E1E6,
+0xFFE0E1E6,
+0xFFE1E2E7,
+0xFFE0E3EA,
+0xFFDBDEE5,
+0xFFD7DAE1,
+0xFFD7DAE3,
+0xFFD4D7E0,
+0xFFD5D9E4,
+0xFFDEE2EB,
+0xFFE2E5EA,
+0xFFE3E7EA,
+0xFFE0E3E8,
+0xFFDBE0E4,
+0xFFDADDE4,
+0xFFD9DDE6,
+0xFFDADDE6,
+0xFFD7DBE4,
+0xFFD9DBE7,
+0xFFD4D8E1,
+0xFFD4D6E2,
+0xFFD5D9E2,
+0xFFD8DBE4,
+0xFFD6DAE3,
+0xFFD7DBE4,
+0xFFDBDEE5,
+0xFFDADAE2,
+0xFFD4D7E0,
+0xFFD7DEE6,
+0xFFD3DCE1,
+0xFFD3DCDB,
+0xFFB7C0BF,
+0xFFD4D8E1,
+0xFFCFD3DF,
+0xFFCBD2DC,
+0xFFC8D1DA,
+0xFFCCD2DE,
+0xFFD1D5E0,
+0xFFCFD2D7,
+0xFFC8CDD3,
+0xFFC2C9D9,
+0xFFBFC7DC,
+0xFFBCCFE0,
+0xFFBCCFDE,
+0xFFC3D3E3,
+0xFFBECEDD,
+0xFFC3D1DE,
+0xFFC1CDDB,
+0xFFC5D1DD,
+0xFFC4D0DC,
+0xFFC1CDD9,
+0xFFC1CFDA,
+0xFFC4D2DD,
+0xFFC5D3DE,
+0xFFC4D0DC,
+0xFFC4D1DA,
+0xFFC6D0DA,
+0xFFC3CFDB,
+0xFFC3D0E0,
+0xFFC1D1E1,
+0xFFCAD8E5,
+0xFFC6D4DF,
+0xFFC7D5DE,
+0xFFC9D7E0,
+0xFFCAD8E3,
+0xFFCDDBE6,
+0xFFC9D7E4,
+0xFFCBD7E7,
+0xFFCCD8E8,
+0xFFCCD8E8,
+0xFFCFDBE7,
+0xFFD1DEE7,
+0xFFD3DEE4,
+0xFFD0DBE1,
+0xFFD0DAE3,
+0xFFD3DDE7,
+0xFFD4DEE8,
+0xFFD3DDE7,
+0xFFD3DDE7,
+0xFFD4DEE8,
+0xFFD5DEE7,
+0xFFD5DEE7,
+0xFFD6DFE8,
+0xFFD6DFE8,
+0xFFD6DFE8,
+0xFFD7E0E9,
+0xFFDAE1EB,
+0xFFDCE3ED,
+0xFFDBE2EA,
+0xFFD9E0E8,
+0xFFDAE1EB,
+0xFFDAE1EB,
+0xFFD8DFE9,
+0xFFD7DEE8,
+0xFFD6DDE5,
+0xFFD7DEE6,
+0xFFDBE2EA,
+0xFFDCE3EB,
+0xFFE1E8F0,
+0xFFDCE3EB,
+0xFFD9E0E8,
+0xFFDCE3EB,
+0xFFDDE4EE,
+0xFFDBE2EC,
+0xFFD9E0EA,
+0xFFD9E0E8,
+0xFFE7EAF1,
+0xFFE5E8ED,
+0xFFE1E4E9,
+0xFFDCE1E5,
+0xFFD8DDE3,
+0xFFD7DCE2,
+0xFFD9DEE4,
+0xFFDDE2E8,
+0xFFD9DEE4,
+0xFFDDE0E5,
+0xFFE1E4E9,
+0xFFE1E5E8,
+0xFFE3E4E8,
+0xFFE3E4E8,
+0xFFE3E4E8,
+0xFFE4E5E9,
+0xFFE3E4E9,
+0xFFE7E8ED,
+0xFFDFE3E6,
+0xFFE5E9EA,
+0xFFE7ECF0,
+0xFFE5E9F2,
+0xFFF9FCFF,
+0xFF454962,
+0xFF313453,
+0xFF383C5F,
+0xFF373B5E,
+0xFF3B3F62,
+0xFF4A4E71,
+0xFF43476C,
+0xFF3F4369,
+0xFF35395E,
+0xFF2B304D,
+0xFF14162D,
+0xFF1E192D,
+0xFF473F4E,
+0xFF81767C,
+0xFFADA1A1,
+0xFFAB9C97,
+0xFF67544D,
+0xFF594039,
+0xFF563D38,
+0xFF4B3834,
+0xFF4A3E3E,
+0xFFF7F5FA,
+0xFFD3D6DF,
+0xFFD7DAE9,
+0xFFDEE4F2,
+0xFFE7EEF6,
+0xFFE4EBF1,
+0xFFE5EAF0,
+0xFFDFE6EC,
+0xFFE2E9EF,
+0xFFDDE4EA,
+0xFFE0E5EB,
+0xFFDEE3E9,
+0xFFE3E8EE,
+0xFFE8EDF3,
+0xFFEBF0F6,
+0xFFE8EDF1,
+0xFFE1E6EA,
+0xFFDDE2E6,
+0xFFDDE2E6,
+0xFFDFE2E7,
+0xFFE2E6E9,
+0xFFE7E8EC,
+0xFFE9EAEE,
+0xFFE7EBEE,
+0xFFE6EAED,
+0xFFE4E9EC,
+0xFFE6EAED,
+0xFFE6EAED,
+0xFFE6EAED,
+0xFFE9EDF0,
+0xFFEAEEF1,
+0xFFE8ECEF,
+0xFFEAEBEF,
+0xFFEDEEF2,
+0xFFEBECF0,
+0xFFE7E8EC,
+0xFFE3E7EA,
+0xFFE7EBEE,
+0xFFE8ECEF,
+0xFFE5E9EC,
+0xFFE4E8EB,
+0xFFE6EAED,
+0xFFE6EAED,
+0xFFE3E7EA,
+0xFFE2E5EA,
+0xFFE1E4E9,
+0xFFE1E4E9,
+0xFFE2E5EA,
+0xFFE3E6EB,
+0xFFE4E7EC,
+0xFFE7EAEF,
+0xFFE9ECF1,
+0xFFEAEEF1,
+0xFFEAEEF1,
+0xFFE9EDF0,
+0xFFE8ECEF,
+0xFFE7EBEE,
+0xFFE8ECEF,
+0xFFEAEBEF,
+0xFFEAEBEF,
+0xFFEAEBEF,
+0xFFECEDF1,
+0xFFECEDF1,
+0xFFEBECF0,
+0xFFEAEBEF,
+0xFFE9EAEE,
+0xFFE8E9ED,
+0xFFE6E7EB,
+0xFFE5E6EA,
+0xFFE6E7EB,
+0xFFEBECF0,
+0xFFF0F1F3,
+0xFFF2F3F5,
+0xFFF0F1F3,
+0xFFF1F1F3,
+0xFFF3F3F3,
+0xFFF1F1F3,
+0xFFF1F1F3,
+0xFFEFEFF1,
+0xFFEDEEF0,
+0xFFEEEFF1,
+0xFFEFF0F4,
+0xFFEEEFF3,
+0xFFECEDF1,
+0xFFE9EAEE,
+0xFFE9EAEC,
+0xFFEAEBEF,
+0xFFEAEBEF,
+0xFFEBECF0,
+0xFFEBECF0,
+0xFFEAEBEF,
+0xFFE9EAEE,
+0xFFE8E9ED,
+0xFFE2E6E9,
+0xFFE4E5EA,
+0xFFE6E7EB,
+0xFFE8E9ED,
+0xFFE7E8EC,
+0xFFE8E9ED,
+0xFFEAEBEF,
+0xFFE8ECEB,
+0xFFEBF1F1,
+0xFFE7F0F5,
+0xFFAFB8BD,
+0xFFDEE6E8,
+0xFFE1E7E7,
+0xFFE2E6E9,
+0xFFECEADE,
+0xFFF7EBC1,
+0xFFFAB886,
+0xFFC51C00,
+0xFFC11404,
+0xFFDE918B,
+0xFFFDE9EA,
+0xFFE0DEDF,
+0xFFE4E9EC,
+0xFFE6E7EB,
+0xFFE7E8EC,
+0xFFE6E7EB,
+0xFFE5E6EA,
+0xFFE0E4E7,
+0xFFE1E4E9,
+0xFFE1E4E9,
+0xFFE3E6EB,
+0xFFE7EAEF,
+0xFFE8EBF0,
+0xFFE9EDF0,
+0xFFE8ECEF,
+0xFFEAEBEF,
+0xFFEBECF0,
+0xFFEAEBED,
+0xFFE9EAEC,
+0xFFECECEE,
+0xFFEDEEF0,
+0xFFEDEEF0,
+0xFFE9EAEC,
+0xFFE6E7E9,
+0xFFE5E6E8,
+0xFFE4E5E9,
+0xFFE0E4E7,
+0xFFDFE3E6,
+0xFFE1E5E8,
+0xFFE4E7EC,
+0xFFE2E7EA,
+0xFFE1E4E9,
+0xFFE0E5E8,
+0xFFE3E6EB,
+0xFFE4E9EC,
+0xFFE2E7EB,
+0xFFDFE7EA,
+0xFFDDE5E8,
+0xFFDCE4E7,
+0xFFDFE4E8,
+0xFFDEE3E7,
+0xFFDDE2E8,
+0xFFDFE4EA,
+0xFFDDE2E8,
+0xFFDEE3E7,
+0xFFDFE4E8,
+0xFFE1E6EA,
+0xFFE4E9ED,
+0xFFE7ECF0,
+0xFFE7ECEF,
+0xFFE6EBEE,
+0xFFE7ECEF,
+0xFFE2E8E8,
+0xFFE1E5E8,
+0xFFE3E7E8,
+0xFFE4E8EB,
+0xFFE3E7E8,
+0xFFE0E4E7,
+0xFFDADFE2,
+0xFFDBE0E3,
+0xFFDDE2E6,
+0xFFD8E0E3,
+0xFFD6DEE1,
+0xFFD7DEE4,
+0xFFD4DBE1,
+0xFFD2DBE2,
+0xFFD8DFE7,
+0xFFDADFE5,
+0xFFDADFE5,
+0xFFD8DDE3,
+0xFFD2D9E1,
+0xFFD3D7E0,
+0xFFD1D8E2,
+0xFFD3D7E2,
+0xFFD0D7E1,
+0xFFD1D5E1,
+0xFFCCD3DD,
+0xFFCED2DE,
+0xFFCED5DF,
+0xFFD0D4DF,
+0xFFCED5DD,
+0xFFD2D9E1,
+0xFFDADFE5,
+0xFFD8DBE2,
+0xFFD5D8DF,
+0xFFD4DBE1,
+0xFFD2DCDE,
+0xFFCFD8D3,
+0xFFB6BCBA,
+0xFFD2D5DA,
+0xFFCDD1DA,
+0xFFC9D0D6,
+0xFFC6CFD4,
+0xFFCDD4DA,
+0xFFD8DDE1,
+0xFFD9DDDC,
+0xFFD6DADB,
+0xFFD1D8E2,
+0xFFD0D8E5,
+0xFFB9CADC,
+0xFFB8C8D8,
+0xFFC3D0E1,
+0xFFC1CEDE,
+0xFFC6CFDE,
+0xFFC6D0DC,
+0xFFC2CCD6,
+0xFFC8D2DC,
+0xFFCAD4DE,
+0xFFCBD5DF,
+0xFFC9D3DC,
+0xFFCBD5DE,
+0xFFD6E0E9,
+0xFFD9E2E9,
+0xFFD0D9DE,
+0xFFCED7E0,
+0xFFC8D4E2,
+0xFFC3D0E0,
+0xFFC6D4DF,
+0xFFC3D1DA,
+0xFFC5D4DB,
+0xFFC9D8DF,
+0xFFC9D8DF,
+0xFFCFDDE6,
+0xFFCEDAE6,
+0xFFD0DCE8,
+0xFFD2DBEA,
+0xFFD0D9E8,
+0xFFCFD9E5,
+0xFFD1D9E4,
+0xFFD2DBE4,
+0xFFD1DAE3,
+0xFFD1DBE4,
+0xFFD2DCE6,
+0xFFD2DCE6,
+0xFFD1DBE5,
+0xFFD3DDE7,
+0xFFD5DFE9,
+0xFFD5DEE7,
+0xFFD2DBE4,
+0xFFD5DEE7,
+0xFFD4DDE6,
+0xFFD6DFE8,
+0xFFD9E2EB,
+0xFFDDE4EE,
+0xFFDCE3ED,
+0xFFDDE4EC,
+0xFFDFE6EE,
+0xFFE4EBF5,
+0xFFE4EBF5,
+0xFFD9E0EA,
+0xFFD4DBE5,
+0xFFCFD6DE,
+0xFFCDD4DC,
+0xFFD6DDE5,
+0xFFD6DDE5,
+0xFFDAE1E9,
+0xFFD5DCE4,
+0xFFD3DAE2,
+0xFFD7DEE6,
+0xFFD7DEE8,
+0xFFD4DBE5,
+0xFFD6DDE7,
+0xFFDEE2EB,
+0xFFE5E8ED,
+0xFFE6E7EB,
+0xFFE5E9EC,
+0xFFE5E9EC,
+0xFFE1E4E9,
+0xFFDBDEE3,
+0xFFDBDEE3,
+0xFFDDE0E5,
+0xFFDEE1E6,
+0xFFDFE2E7,
+0xFFE3E4E8,
+0xFFE2E3E7,
+0xFFE3E4E6,
+0xFFE4E5E7,
+0xFFE7E7E9,
+0xFFE7E7E9,
+0xFFE5E6EA,
+0xFFE9EAEE,
+0xFFE8ECEF,
+0xFFE9EEF1,
+0xFFEDF2F8,
+0xFFE2E8F4,
+0xFFCFD4EA,
+0xFF2D3250,
+0xFF35395F,
+0xFF363964,
+0xFF363964,
+0xFF41446F,
+0xFF404370,
+0xFF3B3E6B,
+0xFF373969,
+0xFF3C3F6A,
+0xFF3C4063,
+0xFF363A55,
+0xFF35334B,
+0xFF242031,
+0xFF1E1621,
+0xFF0F060B,
+0xFF120606,
+0xFF322421,
+0xFF422E2D,
+0xFF44302F,
+0xFF473738,
+0xFF877E83,
+0xFFEBEAF2,
+0xFFDBDFEB,
+0xFFDADDEE,
+0xFFD8DEEE,
+0xFFDEE5EF,
+0xFFDFE6EC,
+0xFFDBE2E8,
+0xFFD1D8DE,
+0xFFD7DEE4,
+0xFFDAE1E7,
+0xFFD9DDE6,
+0xFFDADFE5,
+0xFFE1E6EC,
+0xFFE1E6EC,
+0xFFDFE4EA,
+0xFFDCE1E7,
+0xFFDBE0E6,
+0xFFDCE1E5,
+0xFFDFE4E8,
+0xFFE1E6EA,
+0xFFE1E6EA,
+0xFFE4E9ED,
+0xFFE5EAF0,
+0xFFE4E9ED,
+0xFFE2E7EB,
+0xFFE0E5E9,
+0xFFE0E5E9,
+0xFFE1E6E9,
+0xFFE2E6E9,
+0xFFE5E9EC,
+0xFFE7EBEE,
+0xFFE6EAED,
+0xFFE9EAEE,
+0xFFEAEBEF,
+0xFFEAEBEF,
+0xFFE8E9ED,
+0xFFE5E9EC,
+0xFFE5E9EC,
+0xFFE4E8EB,
+0xFFE3E7EA,
+0xFFE3E7EA,
+0xFFE4E8EB,
+0xFFE4E8EB,
+0xFFE3E7EA,
+0xFFE6E9EE,
+0xFFE1E4E9,
+0xFFD9DCE1,
+0xFFD9DCE1,
+0xFFDDE0E5,
+0xFFE1E4E9,
+0xFFE7EAEF,
+0xFFE9ECF1,
+0xFFE9EDF0,
+0xFFEAEEF1,
+0xFFEBEFF2,
+0xFFEAEEF1,
+0xFFEAEEF1,
+0xFFEAEEF1,
+0xFFEBECF0,
+0xFFEAEBEF,
+0xFFE7E8EC,
+0xFFE9EAEE,
+0xFFE9EAEE,
+0xFFE8E9ED,
+0xFFE8E9ED,
+0xFFE8E9ED,
+0xFFE8E9ED,
+0xFFE7E8EC,
+0xFFE5E6EA,
+0xFFE6E7EB,
+0xFFE8E9ED,
+0xFFECEDF1,
+0xFFEDEEF0,
+0xFFEDEEF0,
+0xFFEFEFF1,
+0xFFF0F0F2,
+0xFFF0F0F2,
+0xFFF1F1F3,
+0xFFEFF0F2,
+0xFFEEEFF1,
+0xFFEDEEF2,
+0xFFEDEEF2,
+0xFFEDEEF2,
+0xFFECEDF1,
+0xFFEBECEE,
+0xFFEBECEE,
+0xFFEAEBED,
+0xFFEAEBED,
+0xFFEBECF0,
+0xFFEBECF0,
+0xFFEAEBEF,
+0xFFEAEBEF,
+0xFFE5E8ED,
+0xFFE3E6EB,
+0xFFE0E3E8,
+0xFFE1E4EB,
+0xFFE5E8EF,
+0xFFE6EBF1,
+0xFFE4E7EE,
+0xFFDEE2E5,
+0xFFE6EAE9,
+0xFFEBF1EF,
+0xFFE8F1F6,
+0xFFAEB9BD,
+0xFFDBE5E6,
+0xFFDCE5E4,
+0xFFDCE1E4,
+0xFFEBE4D4,
+0xFFFFEBB5,
+0xFFD27C43,
+0xFFC81A01,
+0xFFC6211B,
+0xFFFFCDD2,
+0xFFE1DEE5,
+0xFFD7DFE2,
+0xFFE2ECEE,
+0xFFE4E9ED,
+0xFFECEDF2,
+0xFFE6E7EC,
+0xFFE0E1E6,
+0xFFD9DCE1,
+0xFFDFE2E7,
+0xFFE0E3E8,
+0xFFE2E5EA,
+0xFFE5E8ED,
+0xFFE6E9EE,
+0xFFE7EBEE,
+0xFFE7EBEE,
+0xFFE9EAEE,
+0xFFE8E9ED,
+0xFFE5E6E8,
+0xFFE2E3E5,
+0xFFE5E6EA,
+0xFFE8E9ED,
+0xFFEAEBEF,
+0xFFE8E9ED,
+0xFFE4E5E9,
+0xFFE2E3E7,
+0xFFE4E5E9,
+0xFFE6E7EB,
+0xFFE2E3E7,
+0xFFE5E6EA,
+0xFFE8E9ED,
+0xFFE7EBEE,
+0xFFE6EAED,
+0xFFE3E6EB,
+0xFFE1E4E9,
+0xFFE0E3E8,
+0xFFDFE4E8,
+0xFFDEE6E9,
+0xFFDCE4E7,
+0xFFDBE3E6,
+0xFFDFE4EA,
+0xFFDEE3E9,
+0xFFDCE1E7,
+0xFFDDE2E8,
+0xFFDCE1E7,
+0xFFDCE1E5,
+0xFFDEE3E7,
+0xFFE1E6EA,
+0xFFE6EBEF,
+0xFFE7ECEF,
+0xFFE6EBEE,
+0xFFE3E9E9,
+0xFFE3E8EB,
+0xFFDDE3E3,
+0xFFDEE3E6,
+0xFFE3E9E9,
+0xFFE4E9EC,
+0xFFE5EBEB,
+0xFFE3E8EB,
+0xFFDDE2E5,
+0xFFDBE3E5,
+0xFFDCE4E7,
+0xFFD9E3E5,
+0xFFD9E2E7,
+0xFFD9E2E7,
+0xFFD3DCE3,
+0xFFCDD8DE,
+0xFFCED7DE,
+0xFFD7DBE4,
+0xFFD6DAE3,
+0xFFD5D9E2,
+0xFFD2D6DF,
+0xFFD1D5E0,
+0xFFCED5DF,
+0xFFCFD3DF,
+0xFFCBD1DD,
+0xFFC9CFDB,
+0xFFC8CEDA,
+0xFFC7CDD9,
+0xFFC7CED8,
+0xFFC8CFD9,
+0xFFCAD1D9,
+0xFFCED7DE,
+0xFFD3DAE2,
+0xFFD6D9E0,
+0xFFD4D7DE,
+0xFFCBD2DA,
+0xFFD1DBDD,
+0xFFC8D1CE,
+0xFFB9BFBD,
+0xFFCED1D6,
+0xFFCBD0D6,
+0xFFCED5DB,
+0xFFCBD4D9,
+0xFFD2D9DF,
+0xFFDCE1E4,
+0xFFDDE2DE,
+0xFFD9DEDA,
+0xFFD5DCE2,
+0xFFD4DDE4,
+0xFFBEC9DB,
+0xFFC0CCDC,
+0xFFBCC5D4,
+0xFFCDD7E3,
+0xFFD1D7E3,
+0xFFD8DFE9,
+0xFFD4D8E1,
+0xFFD9DEE4,
+0xFFE3E8EE,
+0xFFDCE1E7,
+0xFFDCE1E5,
+0xFFDDE2E5,
+0xFFE1E6E9,
+0xFFE8ECED,
+0xFFE2E6E5,
+0xFFDBDFE0,
+0xFFD7DEE4,
+0xFFC8D1D8,
+0xFFC2CBD2,
+0xFFC4CDD4,
+0xFFCDD6DF,
+0xFFD7E0E9,
+0xFFDAE4ED,
+0xFFE1ECF2,
+0xFFDEE7EE,
+0xFFE0E9F0,
+0xFFDFE6EE,
+0xFFD8DFE9,
+0xFFD4D8E4,
+0xFFD4D6E5,
+0xFFD7D9E8,
+0xFFD9DCEB,
+0xFFD2DAE5,
+0xFFD3DDE6,
+0xFFD2DCE5,
+0xFFD1DBE4,
+0xFFD2DBE4,
+0xFFD4DDE6,
+0xFFD4DDE6,
+0xFFD3DCE5,
+0xFFD8DFE9,
+0xFFD6DDE7,
+0xFFD8DFE9,
+0xFFDDE4EE,
+0xFFDCE3ED,
+0xFFD7DEE8,
+0xFFD7DEE8,
+0xFFDDE4EE,
+0xFFD4DBE5,
+0xFFD9E0EA,
+0xFFD1D8E2,
+0xFFD2D9E3,
+0xFFD1D8E2,
+0xFFD1D8E2,
+0xFFDEE2EB,
+0xFFDEE2EB,
+0xFFD6DAE3,
+0xFFD4D8E1,
+0xFFD5D9E2,
+0xFFD6DAE3,
+0xFFD3D7E2,
+0xFFD1D5E0,
+0xFFD8DCE7,
+0xFFE2E6EF,
+0xFFE6EAED,
+0xFFE6E7E9,
+0xFFE7E8EA,
+0xFFE8E9EB,
+0xFFE4E8EB,
+0xFFDFE3E6,
+0xFFDFE3E6,
+0xFFE2E6E9,
+0xFFE0E4E7,
+0xFFE0E4E7,
+0xFFDFE3E6,
+0xFFDFE3E6,
+0xFFE1E5E8,
+0xFFE3E7EA,
+0xFFE5E6E8,
+0xFFE4E5E7,
+0xFFE7E8EA,
+0xFFDEDFE3,
+0xFFE4E8EB,
+0xFFE4E9ED,
+0xFFE2E6F1,
+0xFFF5FBFF,
+0xFF585C77,
+0xFF2B2F52,
+0xFF262952,
+0xFF1F2350,
+0xFF2F3360,
+0xFF3B3F6C,
+0xFF3F426D,
+0xFF434671,
+0xFF343764,
+0xFF2B2F55,
+0xFF212443,
+0xFF22243D,
+0xFF1D1B31,
+0xFF211E33,
+0xFF282536,
+0xFF24222F,
+0xFF24212A,
+0xFF161118,
+0xFF120610,
+0xFF0C000A,
+0xFF150B14,
+0xFFD5D0D7,
+0xFFE5E5ED,
+0xFFDCDFE8,
+0xFFDBDDE9,
+0xFFD9DDE8,
+0xFFDEE5ED,
+0xFFD6DFE6,
+0xFFD1DAE1,
+0xFFD2DBE2,
+0xFFD1D8E0,
+0xFFD5DCE4,
+0xFFD3DAE4,
+0xFFD5DCE4,
+0xFFD5DCE4,
+0xFFD5DCE4,
+0xFFD4DBE3,
+0xFFD3DAE0,
+0xFFD6DDE3,
+0xFFDBE2E8,
+0xFFE3E8EE,
+0xFFE5EAF0,
+0xFFE3EAF0,
+0xFFE3EAF0,
+0xFFE1E8F0,
+0xFFDEE5EB,
+0xFFDBE2E8,
+0xFFDAE1E7,
+0xFFDAE1E7,
+0xFFDBE3E6,
+0xFFDFE4E8,
+0xFFE2E7EB,
+0xFFE5E8ED,
+0xFFE6E9EE,
+0xFFE7E8EC,
+0xFFE6E7EB,
+0xFFE9E8ED,
+0xFFE9EAEE,
+0xFFE7EBEE,
+0xFFE3E7EA,
+0xFFE1E5E8,
+0xFFE3E7EA,
+0xFFE5E9EC,
+0xFFE5E9EC,
+0xFFE5E9EC,
+0xFFE7EBEE,
+0xFFE6EAED,
+0xFFE3E7EA,
+0xFFDADFE2,
+0xFFDBE0E3,
+0xFFDDE2E5,
+0xFFDFE4E7,
+0xFFE5EAED,
+0xFFE7EBEE,
+0xFFE8ECEF,
+0xFFECEDF1,
+0xFFEBEFF2,
+0xFFEBEFF2,
+0xFFEAEEF1,
+0xFFE9EDF0,
+0xFFE7EBEE,
+0xFFE5E9EC,
+0xFFE4E7EC,
+0xFFE5E8ED,
+0xFFE4E7EC,
+0xFFE3E6EB,
+0xFFE4E7EC,
+0xFFE6E9EE,
+0xFFE8EBF0,
+0xFFE9ECF1,
+0xFFEAEBF0,
+0xFFEBECF1,
+0xFFEBECF0,
+0xFFEAEBEF,
+0xFFEAEBEF,
+0xFFECEDF1,
+0xFFEDEEF2,
+0xFFEDEEF2,
+0xFFEDEEF2,
+0xFFEEEFF3,
+0xFFEFF0F4,
+0xFFECEDF1,
+0xFFE9EAEE,
+0xFFE7E8EC,
+0xFFE8E9EE,
+0xFFE9EAEE,
+0xFFEEEEF0,
+0xFFEDEDED,
+0xFFECECEC,
+0xFFECECEC,
+0xFFEBECEE,
+0xFFEBECEE,
+0xFFE8ECEF,
+0xFFE8ECEF,
+0xFFE1E4E9,
+0xFFE0E3EA,
+0xFFDEE3E9,
+0xFFE0E4ED,
+0xFFE5E9F2,
+0xFFE4EBF3,
+0xFFE0E4ED,
+0xFFD8DDE3,
+0xFFE7E8EA,
+0xFFEFF0F2,
+0xFFEBEEF3,
+0xFFAFB6BC,
+0xFFD7E1E3,
+0xFFD6E1E3,
+0xFFD5DDE0,
+0xFFEEDBCD,
+0xFFFFCC9D,
+0xFFB83E0D,
+0xFFCB2A18,
+0xFFEF6769,
+0xFFFFD8E7,
+0xFFD7D6E6,
+0xFFD4DDE6,
+0xFFDAE5E9,
+0xFFE3E8EE,
+0xFFEBEEF5,
+0xFFE5E8EF,
+0xFFDDE0E7,
+0xFFD8DBE2,
+0xFFDFE2E9,
+0xFFDDE2E8,
+0xFFDFE4EA,
+0xFFE3E8EC,
+0xFFE4E9ED,
+0xFFE6EAED,
+0xFFE6EAED,
+0xFFE6EAEB,
+0xFFE5E9EA,
+0xFFE2E6E7,
+0xFFDEE2E5,
+0xFFDDE0E5,
+0xFFDEE1E8,
+0xFFE2E5EA,
+0xFFE5E8ED,
+0xFFE6E7EC,
+0xFFE4E5EA,
+0xFFE7E6EC,
+0xFFEBEAF0,
+0xFFE4E3E9,
+0xFFE4E3E9,
+0xFFE5E4EA,
+0xFFE5E6EB,
+0xFFE6E7EC,
+0xFFE4E4EC,
+0xFFE1E1E9,
+0xFFDEDEE6,
+0xFFDBDEE3,
+0xFFDEE1E6,
+0xFFDDE0E5,
+0xFFDCDFE4,
+0xFFDFE2E7,
+0xFFE0E3E8,
+0xFFE0E1E6,
+0xFFDFE0E5,
+0xFFDFE0E5,
+0xFFE0E1E5,
+0xFFE2E1E6,
+0xFFE5E4E9,
+0xFFE7E6EB,
+0xFFE7E7E9,
+0xFFE6E6E8,
+0xFFE4E5E7,
+0xFFE3E7EA,
+0xFFDEE2E5,
+0xFFDFE2E7,
+0xFFE3E7EA,
+0xFFE3E6EB,
+0xFFE4E8EB,
+0xFFE2E7EB,
+0xFFDDE2E6,
+0xFFDBE3E6,
+0xFFDAE1E7,
+0xFFD8E1E6,
+0xFFD8E1E8,
+0xFFD8E3E9,
+0xFFD5DFE8,
+0xFFD2DCE5,
+0xFFD2DBE4,
+0xFFD6DAE3,
+0xFFD6D9E0,
+0xFFD5D8E1,
+0xFFD4D7E0,
+0xFFD4D6E2,
+0xFFD2D6E1,
+0xFFD1D3DF,
+0xFFCED2DD,
+0xFFCDD1DC,
+0xFFCED2DD,
+0xFFC9D0DA,
+0xFFC6CDD7,
+0xFFC7CED8,
+0xFFCCD3DB,
+0xFFCFD6DE,
+0xFFCED5DD,
+0xFFCDD1DC,
+0xFFCED2DD,
+0xFFC8D0DB,
+0xFFCFD8DF,
+0xFFC6CED0,
+0xFFBBC0C3,
+0xFFCACDD4,
+0xFFC9CDD6,
+0xFFCCD3DB,
+0xFFCBD4DB,
+0xFFD3DAE2,
+0xFFDBE0E4,
+0xFFDADEDD,
+0xFFD6DAD9,
+0xFFD1D9DC,
+0xFFD0D9DE,
+0xFFBCC7D9,
+0xFFBECADA,
+0xFFB3BCCD,
+0xFFC7D1DD,
+0xFFDEE4F0,
+0xFFD8DFE9,
+0xFFE3E7F0,
+0xFFD9DEE4,
+0xFFD6DBE1,
+0xFFD0D5DB,
+0xFFE4E9ED,
+0xFFE5EAED,
+0xFFD4D8D9,
+0xFFDADEDF,
+0xFFE4E6E5,
+0xFFDFE1E0,
+0xFFDFE3E6,
+0xFFDFE4E8,
+0xFFD7DEE4,
+0xFFD3DAE2,
+0xFFD2D9E1,
+0xFFD5DEE7,
+0xFFCDD6DD,
+0xFFC3CCD3,
+0xFFC9D2D7,
+0xFFD3DCE1,
+0xFFDFE6EC,
+0xFFE5E9F2,
+0xFFE1E3EF,
+0xFFD9DBE8,
+0xFFD5D4E6,
+0xFFD0D2E1,
+0xFFD1D9E4,
+0xFFD3DDE6,
+0xFFD3DDE6,
+0xFFD1DBE4,
+0xFFCFD8E1,
+0xFFCED7E0,
+0xFFD2DBE4,
+0xFFD6DFE8,
+0xFFDCE3ED,
+0xFFD8DFE9,
+0xFFD9E0EA,
+0xFFDDE4EE,
+0xFFDAE1EB,
+0xFFD2D9E3,
+0xFFCFD6E0,
+0xFFD4DBE5,
+0xFFD1D8E2,
+0xFFD8DFE9,
+0xFFD5DCE6,
+0xFFD9E0EA,
+0xFFDAE1EB,
+0xFFD7DEE6,
+0xFFDDE1EA,
+0xFFD8DCE5,
+0xFFDBDFE8,
+0xFFDCE0E9,
+0xFFDCE0E9,
+0xFFD8DCE5,
+0xFFD2D6DF,
+0xFFD0D4DF,
+0xFFD6DAE5,
+0xFFDEE1EA,
+0xFFDCDFE4,
+0xFFDBDFE2,
+0xFFDDE1E4,
+0xFFE1E5E8,
+0xFFE1E4E9,
+0xFFDEE3E7,
+0xFFDEE1E6,
+0xFFDFE4E8,
+0xFFDDE2E6,
+0xFFDDE2E6,
+0xFFDCE1E5,
+0xFFDDE2E6,
+0xFFDFE4E8,
+0xFFE0E5E9,
+0xFFDFE3E6,
+0xFFDDE1E4,
+0xFFDFE2E7,
+0xFFDEE1E6,
+0xFFDFE4EA,
+0xFFDCE3ED,
+0xFFE0E6F6,
+0xFFB2B8CE,
+0xFF353A58,
+0xFF393E64,
+0xFF3C416B,
+0xFF292D5A,
+0xFF3F4370,
+0xFF3B406A,
+0xFF393C65,
+0xFF30335C,
+0xFF2D3157,
+0xFF2C3053,
+0xFF313550,
+0xFF24263D,
+0xFF27283D,
+0xFF232136,
+0xFF16172B,
+0xFF151726,
+0xFF121423,
+0xFF151422,
+0xFF1A1422,
+0xFF140C19,
+0xFF030009,
+0xFFD3D2DA,
+0xFFE4E7EE,
+0xFFDBE0E6,
+0xFFD8DBE2,
+0xFFDADFE5,
+0xFFD0D7DF,
+0xFFD5DEE5,
+0xFFD2DBE2,
+0xFFD6DFE6,
+0xFFD5DCE6,
+0xFFD4DBE5,
+0xFFD1D8E2,
+0xFFD8DFE9,
+0xFFD5DCE4,
+0xFFD8DFE7,
+0xFFDAE1E9,
+0xFFD9E0E8,
+0xFFD6DDE3,
+0xFFD6DDE3,
+0xFFDADFE5,
+0xFFDCE1E7,
+0xFFDBE2EA,
+0xFFDAE3EA,
+0xFFDBE2EA,
+0xFFDCE3EB,
+0xFFDCE3EB,
+0xFFDBE2EA,
+0xFFDAE1E7,
+0xFFDAE1E7,
+0xFFDFE4EA,
+0xFFE0E5E9,
+0xFFE4E7EC,
+0xFFE6E9EE,
+0xFFE7E8EC,
+0xFFE6E7EB,
+0xFFEAE9EE,
+0xFFECEDF1,
+0xFFEAEEF1,
+0xFFE5E9EC,
+0xFFE3E7EA,
+0xFFE5E9EC,
+0xFFE6EAED,
+0xFFE5E9EC,
+0xFFE5E9EC,
+0xFFE7EBEE,
+0xFFE4E8EB,
+0xFFE4E8EB,
+0xFFDCE1E4,
+0xFFDDE2E5,
+0xFFDCE1E4,
+0xFFDBE0E3,
+0xFFE2E7EA,
+0xFFE5E9EC,
+0xFFEAEBEF,
+0xFFECEDF1,
+0xFFEBEFF2,
+0xFFE9EDF0,
+0xFFE8ECEF,
+0xFFE8ECEF,
+0xFFE6EAED,
+0xFFE4E8EB,
+0xFFE3E6EB,
+0xFFE2E5EA,
+0xFFE1E4E9,
+0xFFE1E4E9,
+0xFFE1E4E9,
+0xFFE4E7EC,
+0xFFE7EAEF,
+0xFFE9ECF1,
+0xFFEDEEF3,
+0xFFEEEFF3,
+0xFFECEDF1,
+0xFFE9EAEE,
+0xFFE8E9ED,
+0xFFEBECF0,
+0xFFEBECF0,
+0xFFEAEBEF,
+0xFFE8E9ED,
+0xFFEAEBEF,
+0xFFEAEBEF,
+0xFFE8E9ED,
+0xFFE5E6EA,
+0xFFE3E4E8,
+0xFFE5E6EA,
+0xFFE8E9ED,
+0xFFEEEEF0,
+0xFFEDEDED,
+0xFFECECEC,
+0xFFEBEBEB,
+0xFFEAEBED,
+0xFFEAEBED,
+0xFFE8ECEF,
+0xFFE7EBEE,
+0xFFE1E4EB,
+0xFFDBDEE5,
+0xFFD8DCE5,
+0xFFDBDFE8,
+0xFFDBE2EC,
+0xFFD9E0EA,
+0xFFD8DFE9,
+0xFFDCE0E9,
+0xFFE6E7EB,
+0xFFF1F1F3,
+0xFFEDEEF2,
+0xFFAFB4B8,
+0xFFD0DBDF,
+0xFFD1DCDE,
+0xFFD2D8D4,
+0xFFF5D4C3,
+0xFFF88A65,
+0xFFC43411,
+0xFFBF362C,
+0xFFFFB0B8,
+0xFFEBC8DC,
+0xFFCDCEE2,
+0xFFD0D8E3,
+0xFFD0DBDF,
+0xFFDDE2E8,
+0xFFE7EAF1,
+0xFFE4E7EE,
+0xFFDEE1E8,
+0xFFDDE0E7,
+0xFFE0E3EA,
+0xFFDCE1E7,
+0xFFDDE2E8,
+0xFFE3E8EC,
+0xFFE3E8EC,
+0xFFE4E8EB,
+0xFFE3E7EA,
+0xFFE3E7EA,
+0xFFE3E7E8,
+0xFFE2E6E9,
+0xFFDFE4E7,
+0xFFE0E5EB,
+0xFFDDE1EA,
+0xFFDFE4EA,
+0xFFE6E9F0,
+0xFFE9ECF1,
+0xFFE9EAEF,
+0xFFE8E7ED,
+0xFFEAE9EF,
+0xFFE7E6EC,
+0xFFE4E3E9,
+0xFFE0DFE5,
+0xFFDFDFE7,
+0xFFDFDFE7,
+0xFFDCDFE8,
+0xFFDADDE6,
+0xFFD8DBE4,
+0xFFD6D9E2,
+0xFFD9DCE3,
+0xFFD8DBE4,
+0xFFD7DAE1,
+0xFFDBDEE7,
+0xFFDEE1E8,
+0xFFE0E0EA,
+0xFFDFDFE7,
+0xFFDFDFE7,
+0xFFDFE0E5,
+0xFFE1E0E6,
+0xFFE2E1E7,
+0xFFE2E1E7,
+0xFFE2E1E6,
+0xFFE2E1E6,
+0xFFE3E2E7,
+0xFFE3E4E9,
+0xFFDEE1E6,
+0xFFDFE2E7,
+0xFFE0E3E8,
+0xFFDFE2E7,
+0xFFDFE2E7,
+0xFFDEE1E6,
+0xFFDCE1E5,
+0xFFDBE0E6,
+0xFFD6DDE3,
+0xFFD3DAE2,
+0xFFD2D9E1,
+0xFFD3DCE5,
+0xFFD5DEE7,
+0xFFD5DEE7,
+0xFFD6DDE7,
+0xFFD8DCE5,
+0xFFD9DCE5,
+0xFFD8DBE4,
+0xFFD8DAE6,
+0xFFD9DBE7,
+0xFFD8DCE8,
+0xFFD7DBE7,
+0xFFD6DAE6,
+0xFFD0D6E2,
+0xFFD1D7E3,
+0xFFCFD7E2,
+0xFFCCD4DF,
+0xFFCDD5E0,
+0xFFCDD6DF,
+0xFFC9D2DB,
+0xFFC3CCD5,
+0xFFC2C8D4,
+0xFFC5CDDA,
+0xFFC5CEDD,
+0xFFC1CBD7,
+0xFFC0C7CF,
+0xFFB6BBC1,
+0xFFC2C6D1,
+0xFFC9CDD9,
+0xFFC5CDD8,
+0xFFC7CFDA,
+0xFFCFD7E2,
+0xFFD5DCE4,
+0xFFD7DBDE,
+0xFFD4D9DC,
+0xFFCFD8DD,
+0xFFCCD7DD,
+0xFFA6B7CB,
+0xFFA9B8CB,
+0xFFA5B2C5,
+0xFFAFBCCC,
+0xFFCFD8E7,
+0xFFC8D2DE,
+0xFFD1DBE5,
+0xFFC3CDD7,
+0xFFB6C0CA,
+0xFFB7C1CA,
+0xFFD0D9E0,
+0xFFD4DDE2,
+0xFFC9D1D4,
+0xFFD3DBDE,
+0xFFE1E6E9,
+0xFFE3E7EA,
+0xFFE3E8EE,
+0xFFE7ECF2,
+0xFFD4DBE3,
+0xFFCCD3DB,
+0xFFC8D1D8,
+0xFFCED9DF,
+0xFFCCD6DF,
+0xFFBDC7D0,
+0xFFBBC5CE,
+0xFFC0CAD3,
+0xFFC8D0DB,
+0xFFCFD7E2,
+0xFFD1D7E3,
+0xFFCFD5E1,
+0xFFD2D6E2,
+0xFFD3D9E5,
+0xFFD2DBE4,
+0xFFD1DAE3,
+0xFFD1DAE3,
+0xFFCFD8E1,
+0xFFCDD4DC,
+0xFFCBD2DA,
+0xFFD0D7DF,
+0xFFD5DCE4,
+0xFFDCE0E9,
+0xFFDADEE7,
+0xFFDADEE7,
+0xFFDCE0E9,
+0xFFDADEE7,
+0xFFD5D9E2,
+0xFFD0D4DD,
+0xFFCFD3DC,
+0xFFCFD6E0,
+0xFFD3DAE4,
+0xFFD1D8E0,
+0xFFD8DFE7,
+0xFFE0E4ED,
+0xFFE2E6EF,
+0xFFE3E7F0,
+0xFFDDE2E8,
+0xFFDEE1E8,
+0xFFE0E3EA,
+0xFFE0E3EA,
+0xFFDADDE4,
+0xFFD4D7DE,
+0xFFD3D6DF,
+0xFFD4D7E0,
+0xFFD5D8E1,
+0xFFD8DBE2,
+0xFFD8DDE1,
+0xFFDCE1E5,
+0xFFE0E5E9,
+0xFFE2E7ED,
+0xFFDEE5EB,
+0xFFDDE2E8,
+0xFFDAE1E7,
+0xFFD8DFE5,
+0xFFD8DFE5,
+0xFFD8DFE7,
+0xFFD8DFE7,
+0xFFDAE1E9,
+0xFFDBE2EA,
+0xFFDAE1E9,
+0xFFD8DFE7,
+0xFFD7DBE6,
+0xFFD9DDE9,
+0xFFD8DBEA,
+0xFFD9DEF1,
+0xFFE8ECFF,
+0xFF424765,
+0xFF3C4266,
+0xFF454C76,
+0xFF3A416F,
+0xFF3C4371,
+0xFF474B78,
+0xFF40456D,
+0xFF363A60,
+0xFF404467,
+0xFF3A3D5E,
+0xFF333856,
+0xFF29304A,
+0xFF272D43,
+0xFF1C1E33,
+0xFF1B1C30,
+0xFF1D2033,
+0xFF191C2B,
+0xFF161827,
+0xFF141321,
+0xFF110B19,
+0xFF0D0713,
+0xFF04010C,
+0xFFBDBDC5,
+0xFFE2E9EF,
+0xFFD9E3E5,
+0xFFDCE4E7,
+0xFFD3DAE0,
+0xFFD1DAE1,
+0xFFDAE3EC,
+0xFFD1DAE3,
+0xFFCFD8E1,
+0xFFD6DDE7,
+0xFFD7DEE8,
+0xFFD9DDE6,
+0xFFD9DDE6,
+0xFFDEE2EB,
+0xFFE1E5EE,
+0xFFE2E6EF,
+0xFFDFE3EC,
+0xFFDADFE5,
+0xFFD7DCE2,
+0xFFD8DDE3,
+0xFFD9DEE4,
+0xFFD3DAE2,
+0xFFD3DAE2,
+0xFFD4DBE3,
+0xFFD7DEE6,
+0xFFD9E0E8,
+0xFFDAE1E9,
+0xFFDDE1EA,
+0xFFDDE2E8,
+0xFFDDE2E8,
+0xFFDFE4EA,
+0xFFE1E4E9,
+0xFFE2E5EA,
+0xFFE4E5EA,
+0xFFE6E7EC,
+0xFFE9EAEF,
+0xFFEBECF1,
+0xFFE9EDF0,
+0xFFE7EBEE,
+0xFFE5E9EC,
+0xFFE4E8EB,
+0xFFE4E8EB,
+0xFFE5E9EC,
+0xFFE5E9EC,
+0xFFE6EAED,
+0xFFE5E9EC,
+0xFFE4E8EB,
+0xFFDBDEE3,
+0xFFDCDFE4,
+0xFFDDE0E5,
+0xFFDBDEE3,
+0xFFE2E5EA,
+0xFFE1E5E8,
+0xFFE8E9ED,
+0xFFEAEBED,
+0xFFEBECEE,
+0xFFE9EAEC,
+0xFFE9EAEE,
+0xFFE9EAEE,
+0xFFE5E9EC,
+0xFFE2E6E9,
+0xFFDFE2E7,
+0xFFDFE2E7,
+0xFFDEE1E6,
+0xFFDEE1E6,
+0xFFDFE2E7,
+0xFFE1E4E9,
+0xFFE3E6EB,
+0xFFE5E8ED,
+0xFFE7E8EC,
+0xFFE7E8EA,
+0xFFE7E8EA,
+0xFFE7E8EA,
+0xFFE7E8EA,
+0xFFE7E8EA,
+0xFFE7E8EA,
+0xFFE6E7E9,
+0xFFE7E8EA,
+0xFFE7E8EA,
+0xFFE7E8EA,
+0xFFE6E7E9,
+0xFFE5E6E8,
+0xFFE5E6E8,
+0xFFE7E8EA,
+0xFFE9EAEC,
+0xFFECECEC,
+0xFFEBEBEB,
+0xFFEAEAEA,
+0xFFEAEAEA,
+0xFFE9EAEC,
+0xFFE8E9EB,
+0xFFE6EAED,
+0xFFE6EAED,
+0xFFE4E7EE,
+0xFFDDE0E7,
+0xFFD7DBE4,
+0xFFD5D9E2,
+0xFFD3D7E2,
+0xFFCED2DD,
+0xFFCCD3DD,
+0xFFD2D6DF,
+0xFFE2E5EC,
+0xFFEEF1F6,
+0xFFEAEFF2,
+0xFFACB6B7,
+0xFFC8D7DC,
+0xFFCDD9D9,
+0xFFD5D6C6,
+0xFFFFD2B8,
+0xFFCE4630,
+0xFFD53C2C,
+0xFFC76361,
+0xFFF8C3CB,
+0xFFDFCEDE,
+0xFFCFD5E5,
+0xFFCCD5DE,
+0xFFD3DCE1,
+0xFFD7DCE2,
+0xFFDEE1E6,
+0xFFDEE1E8,
+0xFFDADDE4,
+0xFFDFE2E9,
+0xFFDFE2E9,
+0xFFDDE0E5,
+0xFFDDE0E5,
+0xFFE0E3E8,
+0xFFE1E4E9,
+0xFFE1E4E9,
+0xFFE0E3E8,
+0xFFDEE3E7,
+0xFFDEE3E6,
+0xFFDEE3E7,
+0xFFDCE1E5,
+0xFFDFE6EC,
+0xFFDCE3EB,
+0xFFDCE3E9,
+0xFFE1E6EC,
+0xFFE4E7EC,
+0xFFE1E4E9,
+0xFFE1E2E6,
+0xFFE1E2E6,
+0xFFE3E4E9,
+0xFFDFE0E5,
+0xFFDCDCE4,
+0xFFD9DCE3,
+0xFFD6DAE3,
+0xFFD4D8E3,
+0xFFD0D7E1,
+0xFFCFD5E1,
+0xFFCED6E1,
+0xFFCFD7E2,
+0xFFCFD5E3,
+0xFFD0D6E2,
+0xFFD4DAE8,
+0xFFD7DDE9,
+0xFFD9DCEB,
+0xFFDADEEA,
+0xFFD9DBE8,
+0xFFDADCE8,
+0xFFDBDDE9,
+0xFFDCDFE8,
+0xFFDEDEE8,
+0xFFDDDDE5,
+0xFFDEDEE6,
+0xFFE0E0E8,
+0xFFDCDFE6,
+0xFFDDE0E7,
+0xFFDEDEE6,
+0xFFDEDEE6,
+0xFFDFDFE7,
+0xFFDDDDE5,
+0xFFDCDCE4,
+0xFFDCDFE6,
+0xFFDDE0E7,
+0xFFD8DBE2,
+0xFFD4D7DE,
+0xFFD0D5DB,
+0xFFCED2DB,
+0xFFCED2DB,
+0xFFCCD3DB,
+0xFFCAD1DB,
+0xFFCACED9,
+0xFFCBCFDA,
+0xFFCCD0DB,
+0xFFCAD0DC,
+0xFFC9CFDB,
+0xFFC7CDDB,
+0xFFC5CDDA,
+0xFFC5CDDA,
+0xFFC8D1E0,
+0xFFC7D0DF,
+0xFFC5D1E1,
+0xFFC6D2E2,
+0xFFC7D3E3,
+0xFFC3CFDD,
+0xFFBBC9D6,
+0xFFB6C2D0,
+0xFFBAC3D4,
+0xFFBCC8D8,
+0xFFB9C6D7,
+0xFFB2BECE,
+0xFFB6BECB,
+0xFFB3B9C5,
+0xFFB8BBCA,
+0xFFC0C6D6,
+0xFFC2CBDC,
+0xFFC3CCDD,
+0xFFC6CFE0,
+0xFFCAD2DF,
+0xFFCAD1DB,
+0xFFCAD1D9,
+0xFFC7D1DA,
+0xFFC0CDD6,
+0xFF91A3B7,
+0xFF9AABBF,
+0xFF9DACBF,
+0xFFAAB7C8,
+0xFFB6C2D2,
+0xFFC4D0DE,
+0xFFB7C3D1,
+0xFFB8C4D0,
+0xFFB7C3CF,
+0xFFB3BFCB,
+0xFFB9C3CD,
+0xFFBAC4CD,
+0xFFC9D2D9,
+0xFFD9E2E9,
+0xFFD9E0E6,
+0xFFDEE3E9,
+0xFFE2E7ED,
+0xFFD9DDE6,
+0xFFC6CAD3,
+0xFFD1D8E0,
+0xFFD7E0E9,
+0xFFD6E0E9,
+0xFFCCD9E2,
+0xFFBDCAD3,
+0xFFB6C3CC,
+0xFFB9C6CF,
+0xFFC1CED7,
+0xFFCED8E2,
+0xFFD2DCE5,
+0xFFD2DBE2,
+0xFFD2DBE2,
+0xFFD4DDE4,
+0xFFD4DDE6,
+0xFFCED7E0,
+0xFFCAD3DC,
+0xFFCBD4DD,
+0xFFCCD3DB,
+0xFFCBD2DA,
+0xFFCDD4DC,
+0xFFD1D8E0,
+0xFFD8DCE5,
+0xFFD7DBE4,
+0xFFD7DBE4,
+0xFFD8DCE5,
+0xFFDADEE7,
+0xFFDADEE7,
+0xFFD4D8E1,
+0xFFCFD3DC,
+0xFFD1D8E2,
+0xFFCFD6DE,
+0xFFCAD1D9,
+0xFFCED5DD,
+0xFFDADEE7,
+0xFFE1E6EC,
+0xFFE4E9EF,
+0xFFDFE4EA,
+0xFFDEE1E8,
+0xFFE2E5EC,
+0xFFE3E6ED,
+0xFFDEE1E8,
+0xFFDCDFE6,
+0xFFDDE0E7,
+0xFFDBDEE7,
+0xFFD6DAE3,
+0xFFD6DAE3,
+0xFFD6DBE1,
+0xFFD5DCE4,
+0xFFD6DDE5,
+0xFFD7DEE6,
+0xFFD5DCE4,
+0xFFD2D9E1,
+0xFFD0D7DF,
+0xFFCFD8DF,
+0xFFCFD8E1,
+0xFFCED7E0,
+0xFFCFD8E1,
+0xFFD1DAE3,
+0xFFD3DCE5,
+0xFFD3DBE6,
+0xFFD2DAE5,
+0xFFD0D6E2,
+0xFFCFD5E3,
+0xFFD0D5E8,
+0xFFD6DCF2,
+0xFFA3A8C6,
+0xFF313759,
+0xFF373F66,
+0xFF353C68,
+0xFF414876,
+0xFF383F6D,
+0xFF3D416E,
+0xFF373C64,
+0xFF3B3F64,
+0xFF323757,
+0xFF323554,
+0xFF2D324F,
+0xFF262D47,
+0xFF272F46,
+0xFF22273D,
+0xFF222439,
+0xFF252839,
+0xFF1A1D2C,
+0xFF0E101D,
+0xFF1A1A26,
+0xFF1A1722,
+0xFF18121C,
+0xFF000007,
+0xFFE9ECF3,
+0xFFDEE7EC,
+0xFFDDE8EC,
+0xFFD5DEE3,
+0xFFD7E0E7,
+0xFFD4DDE6,
+0xFFD1DAE3,
+0xFFD3DCE5,
+0xFFD7E0E9,
+0xFFD5DCE6,
+0xFFD5DCE6,
+0xFFE6EAF3,
+0xFFDBDFE8,
+0xFFD9DDE6,
+0xFFD9DDE6,
+0xFFD8DCE5,
+0xFFD6DBE1,
+0xFFD6DBE1,
+0xFFD9DEE4,
+0xFFDDE2E8,
+0xFFE0E5EB,
+0xFFDBE0E6,
+0xFFD6DBE1,
+0xFFD2D7DD,
+0xFFCED5DD,
+0xFFD2D6DF,
+0xFFD5D9E2,
+0xFFD9DDE6,
+0xFFDDE1EA,
+0xFFDDE2E8,
+0xFFDFE4EA,
+0xFFDFE2E9,
+0xFFDDE0E5,
+0xFFDDE0E7,
+0xFFE2E5EA,
+0xFFE5E6EB,
+0xFFE2E5EA,
+0xFFE2E5EA,
+0xFFE5E9EC,
+0xFFE5E9EC,
+0xFFE1E5E8,
+0xFFE1E5E8,
+0xFFE5E9EC,
+0xFFE8ECEF,
+0xFFE7EBEE,
+0xFFE6E9EE,
+0xFFE3E6EB,
+0xFFD9DCE1,
+0xFFDFE2E7,
+0xFFE3E6EB,
+0xFFE1E4E9,
+0xFFE3E6EB,
+0xFFDCDFE4,
+0xFFE3E4E8,
+0xFFE6E7E9,
+0xFFE8E9EB,
+0xFFE7E8EA,
+0xFFE7E8EC,
+0xFFE7E8EC,
+0xFFE3E7EA,
+0xFFE0E4E7,
+0xFFDCDFE4,
+0xFFDCDFE4,
+0xFFDCDFE4,
+0xFFDDE0E5,
+0xFFDDE0E5,
+0xFFDEE1E6,
+0xFFDFE2E7,
+0xFFE0E4E7,
+0xFFE4E5E7,
+0xFFE3E4E6,
+0xFFE5E6E8,
+0xFFE9EAEC,
+0xFFEBECEE,
+0xFFE9EAEC,
+0xFFE8E9EB,
+0xFFE9EAEC,
+0xFFEBECEE,
+0xFFE9EAEC,
+0xFFE7E8EA,
+0xFFE6E7E9,
+0xFFE7E8EA,
+0xFFE8E9EB,
+0xFFE9EAEC,
+0xFFE9EAEC,
+0xFFEAEBED,
+0xFFE9EBEA,
+0xFFE9E9EB,
+0xFFE8E9EB,
+0xFFE8E9EB,
+0xFFE8E9EB,
+0xFFE5E9EC,
+0xFFE5E8ED,
+0xFFE2E5EC,
+0xFFE0E3EA,
+0xFFDCE0E9,
+0xFFDADEE7,
+0xFFD8DCE7,
+0xFFD5D9E4,
+0xFFD0D4DF,
+0xFFCCD0D9,
+0xFFDEE2EB,
+0xFFECF1F7,
+0xFFE9F1F3,
+0xFFADB7B8,
+0xFFC8D5DD,
+0xFFCDD6D1,
+0xFFDBD5B5,
+0xFFFFD0AA,
+0xFFAC1907,
+0xFFB41C17,
+0xFFFFBABC,
+0xFFEAD5DE,
+0xFFDBD8E3,
+0xFFD6DDE7,
+0xFFD9E0E6,
+0xFFD7DCDF,
+0xFFD6D9DE,
+0xFFD8DBE0,
+0xFFD7DADF,
+0xFFD3D6DB,
+0xFFDDE0E7,
+0xFFDBDEE3,
+0xFFDCDFE4,
+0xFFDEE1E6,
+0xFFDCDFE4,
+0xFFDDE0E5,
+0xFFDEE1E6,
+0xFFDDE0E7,
+0xFFDBE0E6,
+0xFFDADFE5,
+0xFFD8DDE3,
+0xFFD4DBE1,
+0xFFD5DEE3,
+0xFFD6DFE4,
+0xFFD6DFE4,
+0xFFD6DDE3,
+0xFFD6DBDF,
+0xFFD5DADE,
+0xFFD6DADD,
+0xFFD8DCDF,
+0xFFD5D8DD,
+0xFFD4D9DF,
+0xFFD5DAE0,
+0xFFD3DAE2,
+0xFFD0D9E2,
+0xFFCBD5DF,
+0xFFC8D2DC,
+0xFFC6D2DE,
+0xFFC2CEDC,
+0xFFC1CDDB,
+0xFFC0CCDC,
+0xFFC6CFDE,
+0xFFCBD4E5,
+0xFFCAD3E2,
+0xFFCAD3E4,
+0xFFCED5E5,
+0xFFD0D7E7,
+0xFFD3D9E7,
+0xFFD6DCEA,
+0xFFD9DFEB,
+0xFFD9DFEB,
+0xFFD8DFE9,
+0xFFD9DDE8,
+0xFFDADEE9,
+0xFFD9DDE8,
+0xFFDBDFE8,
+0xFFDBDEE7,
+0xFFDADDE4,
+0xFFDCDFE6,
+0xFFDADDE4,
+0xFFD8DBE2,
+0xFFDBDEE5,
+0xFFDBDBE3,
+0xFFD7DAE1,
+0xFFD6D9E0,
+0xFFD6D9E0,
+0xFFD4D7DE,
+0xFFD3D6DD,
+0xFFD0D4DD,
+0xFFCCD0D9,
+0xFFCACED9,
+0xFFCAD0DC,
+0xFFCDD3DF,
+0xFFCDD3DF,
+0xFFC9D1DE,
+0xFFC4CCD9,
+0xFFC1CAD9,
+0xFFC1CAD9,
+0xFFBBC7D7,
+0xFFB5C0D2,
+0xFFB1BECF,
+0xFFB5C2D5,
+0xFFB7C4D7,
+0xFFB3C2D5,
+0xFFB1C1D1,
+0xFFB2C2D2,
+0xFFB1BECF,
+0xFFB5C4D7,
+0xFFAEBFD1,
+0xFFACBCCC,
+0xFFAFBBC9,
+0xFFB7BECE,
+0xFFACB2C2,
+0xFFB4BBCD,
+0xFFB3BED2,
+0xFFB2BED4,
+0xFFB5C0D4,
+0xFFB6C1D3,
+0xFFBBC4D3,
+0xFFC1CBD7,
+0xFFC0CCDA,
+0xFFBAC8D5,
+0xFFA8B9CB,
+0xFFAABBCB,
+0xFFB8C8D8,
+0xFFB7C4D4,
+0xFFB5C1D1,
+0xFFC0CCDA,
+0xFFC1CDDB,
+0xFFC8D4E2,
+0xFFC0CCDA,
+0xFFBFCBD9,
+0xFFCBD7E3,
+0xFFC9D3DF,
+0xFFC2CAD5,
+0xFFD1D9E4,
+0xFFD2D9E3,
+0xFFD4D8E1,
+0xFFD6DBE1,
+0xFFD0D5DB,
+0xFFD7DBE4,
+0xFFCFD6E0,
+0xFFCFD7E2,
+0xFFCED8E2,
+0xFFCAD6E2,
+0xFFC9D5E1,
+0xFFC0CED7,
+0xFFC1D0D7,
+0xFFC1D0D7,
+0xFFC5D3D6,
+0xFFC3D1D2,
+0xFFC8D4D4,
+0xFFC7D3D1,
+0xFFCCD6D7,
+0xFFCFD8DF,
+0xFFD2D9E3,
+0xFFCFD6E0,
+0xFFCDD4DE,
+0xFFD1D8E0,
+0xFFD4DBE3,
+0xFFD6DDE5,
+0xFFDAE1E9,
+0xFFDDE1EA,
+0xFFDDE1EA,
+0xFFD9DDE6,
+0xFFDADEE7,
+0xFFD8DCE5,
+0xFFD4D8E1,
+0xFFD8DBE4,
+0xFFD3D7E0,
+0xFFD2D9E1,
+0xFFCFD6DE,
+0xFFC8CFD7,
+0xFFC8CFD5,
+0xFFD4D9DF,
+0xFFDDE2E8,
+0xFFDFE4EA,
+0xFFDFE4E8,
+0xFFDBE0E4,
+0xFFDDE2E6,
+0xFFDFE4EA,
+0xFFE0E5EB,
+0xFFDFE4EA,
+0xFFDDE2E8,
+0xFFDCE1E7,
+0xFFDBDFE8,
+0xFFD7DBE4,
+0xFFD4DBE3,
+0xFFD3DAE4,
+0xFFD3DAE4,
+0xFFD4DBE5,
+0xFFD3DAE4,
+0xFFCED5DF,
+0xFFC8CFD9,
+0xFFC5CED7,
+0xFFC4CCD7,
+0xFFC2CAD5,
+0xFFC2CAD5,
+0xFFC2CCD6,
+0xFFC5CFD9,
+0xFFC7D1DD,
+0xFFCAD2DD,
+0xFFCCD5DE,
+0xFFCAD2DD,
+0xFFCBD2E4,
+0xFFD3D9EF,
+0xFF5D6280,
+0xFF373D5F,
+0xFF323A61,
+0xFF313862,
+0xFF363D69,
+0xFF39406C,
+0xFF383D67,
+0xFF383D65,
+0xFF34385E,
+0xFF2D3154,
+0xFF2E3152,
+0xFF2B304E,
+0xFF282F4C,
+0xFF2A2F4C,
+0xFF262A43,
+0xFF1D1F34,
+0xFF131929,
+0xFF141A26,
+0xFF1B1F28,
+0xFF20232A,
+0xFF1D1C22,
+0xFF100D14,
+0xFF000005,
+0xFFECEFF6,
+0xFFD3DCE3,
+0xFFD3E0E8,
+0xFFD0DAE3,
+0xFFD0DAE4,
+0xFFD5DEE7,
+0xFFD3DCE5,
+0xFFCFD6DE,
+0xFFCFD6DE,
+0xFFD7DBE4,
+0xFFDADEE7,
+0xFFDCDFE8,
+0xFFDDE0E9,
+0xFFDBDEE5,
+0xFFD7DAE1,
+0xFFD6D9E0,
+0xFFD8DBE2,
+0xFFDADDE4,
+0xFFDADDE2,
+0xFFDDE0E5,
+0xFFE1E4E9,
+0xFFE4E7EC,
+0xFFE0E3E8,
+0xFFDADDE2,
+0xFFD5DAE0,
+0xFFD9DCE3,
+0xFFD9DEE4,
+0xFFD8DDE3,
+0xFFD9DEE4,
+0xFFDDE1EA,
+0xFFDFE3EC,
+0xFFDFE3EC,
+0xFFDCE1E7,
+0xFFD7DBE4,
+0xFFD7DCE2,
+0xFFDDE0E7,
+0xFFE3E6EB,
+0xFFDADDE2,
+0xFFDEE1E6,
+0xFFDFE2E7,
+0xFFDFE2E7,
+0xFFDFE2E7,
+0xFFE3E6EB,
+0xFFE6E9EE,
+0xFFE7EAEF,
+0xFFE3E6ED,
+0xFFDFE2E9,
+0xFFDDE0E7,
+0xFFE0E3EA,
+0xFFE2E5EC,
+0xFFDFE2E9,
+0xFFDBDEE5,
+0xFFDBDEE3,
+0xFFE2E3E7,
+0xFFE7E7E9,
+0xFFE8E9ED,
+0xFFE6E7EB,
+0xFFE6E7EB,
+0xFFE7E8EC,
+0xFFE1E4E9,
+0xFFDCDFE4,
+0xFFDCDFE4,
+0xFFDBDEE3,
+0xFFDADDE2,
+0xFFDCDFE4,
+0xFFDFE2E7,
+0xFFDDE0E5,
+0xFFDDE1E4,
+0xFFDFE3E6,
+0xFFE1E2E4,
+0xFFE6E6E6,
+0xFFEAEAEA,
+0xFFECECEC,
+0xFFEEEEEE,
+0xFFEFEFEF,
+0xFFEEF0EF,
+0xFFEEF0EF,
+0xFFEEF0EF,
+0xFFEEF0EF,
+0xFFEEEEEE,
+0xFFEBEBEB,
+0xFFE8E8E8,
+0xFFE8E8E8,
+0xFFEBEBEB,
+0xFFECEDEF,
+0xFFEAEBED,
+0xFFE8ECED,
+0xFFE7E8EC,
+0xFFE5E9EC,
+0xFFE5E9EC,
+0xFFE3E7EA,
+0xFFE0E3E8,
+0xFFE1E4E9,
+0xFFE0E3EA,
+0xFFDDE0E7,
+0xFFDBDEE5,
+0xFFDCDFE6,
+0xFFDCDFE8,
+0xFFDBDFE8,
+0xFFDBDFE8,
+0xFFDCE0E9,
+0xFFE5EAF0,
+0xFFEAEFF3,
+0xFFEBF0F4,
+0xFFB1B6BA,
+0xFFD1D8E2,
+0xFFD8D8D0,
+0xFFF1E4B0,
+0xFFE5A871,
+0xFF9B1300,
+0xFF9E1912,
+0xFFFFE6E9,
+0xFFE1DEE5,
+0xFFE5E8F1,
+0xFFDEE3E9,
+0xFFE4E8E9,
+0xFFE6EAE9,
+0xFFE7E8EA,
+0xFFEAEBEF,
+0xFFE3E4E8,
+0xFFD5D6DA,
+0xFFD2D3D8,
+0xFFD5D6DB,
+0xFFDCDDE2,
+0xFFD8D9DE,
+0xFFD6D6DE,
+0xFFD0D0D8,
+0xFFD4D7DE,
+0xFFD4D7E0,
+0xFFD3D7E0,
+0xFFCED2DB,
+0xFFD0D7DF,
+0xFFCFD6DE,
+0xFFD0D9DE,
+0xFFCFDADC,
+0xFFCDD8DA,
+0xFFCDD7D9,
+0xFFCDD7D9,
+0xFFD0D8DB,
+0xFFD1D9DC,
+0xFFD1D9DC,
+0xFFCDD6DB,
+0xFFD0D9DE,
+0xFFD2DBE2,
+0xFFD0DAE3,
+0xFFCAD7E0,
+0xFFC5D3DE,
+0xFFC3D1DC,
+0xFFC0D0DD,
+0xFFBCCCDB,
+0xFFB4C6D4,
+0xFFB1C2D2,
+0xFFB4C4D3,
+0xFFB4C4D4,
+0xFFB2C2D1,
+0xFFB3C3D3,
+0xFFB9C6D6,
+0xFFBAC7D7,
+0xFFBECAD8,
+0xFFC3CFDD,
+0xFFC6D2E0,
+0xFFC7D3E1,
+0xFFC8D4E0,
+0xFFCBD5E1,
+0xFFCDD7E1,
+0xFFD3DBE6,
+0xFFCDD6DF,
+0xFFD1D8E2,
+0xFFD4DBE3,
+0xFFD1D5DE,
+0xFFD1D5DE,
+0xFFD5DAE0,
+0xFFD2D7DD,
+0xFFD5D8DD,
+0xFFD5D8DD,
+0xFFD4D7DC,
+0xFFD6D9DE,
+0xFFDADDE2,
+0xFFDDE0E5,
+0xFFDCDFE6,
+0xFFD8DDE3,
+0xFFD7DBE4,
+0xFFD6DAE5,
+0xFFD1D8E2,
+0xFFD2D9E3,
+0xFFCAD2DD,
+0xFFC8D0DD,
+0xFFC0C9D8,
+0xFFBDC6D5,
+0xFFB0BCCC,
+0xFFB3BED0,
+0xFFB0BDD0,
+0xFFACB8CE,
+0xFFA7B6CB,
+0xFFA2B1C6,
+0xFFA2B1C8,
+0xFFA6B7CB,
+0xFFA5B6CA,
+0xFFA5B7CB,
+0xFFA0B5C8,
+0xFFA3B6C7,
+0xFFA3B0C0,
+0xFFAFBBC9,
+0xFF9FA8B7,
+0xFFA5AEBF,
+0xFFA0AFC4,
+0xFFA3B3CA,
+0xFFA5B5CC,
+0xFFA5B4C9,
+0xFFA8B5C6,
+0xFFADBACB,
+0xFFAFBFCF,
+0xFFADBECE,
+0xFFB5C5D4,
+0xFFC2D0DD,
+0xFFBDC9D7,
+0xFFC5D1DF,
+0xFFC2CCD8,
+0xFFC5CFDB,
+0xFFCDD7E3,
+0xFFD0DAE6,
+0xFFD3DCEB,
+0xFFCFD8E7,
+0xFFC9D2E1,
+0xFFC1CAD9,
+0xFFC5CDDA,
+0xFFCAD0DC,
+0xFFC9CFDB,
+0xFFD5D9E2,
+0xFFDADFE3,
+0xFFDADDE2,
+0xFFD2D7DD,
+0xFFD3D7E2,
+0xFFCBD1DF,
+0xFFC5CCDE,
+0xFFC7D0E1,
+0xFFC2CEDE,
+0xFFBFCBD7,
+0xFFC5D3DC,
+0xFFC7D4DA,
+0xFFC6D4D7,
+0xFFC6D4D5,
+0xFFC1CFD0,
+0xFFC5D1D1,
+0xFFC4CFD1,
+0xFFC2CBD2,
+0xFFC6CFD8,
+0xFFC8CEDA,
+0xFFC8D1DA,
+0xFFCDD4DE,
+0xFFCFD8DF,
+0xFFD3DAE4,
+0xFFD8DFE7,
+0xFFDAE1EB,
+0xFFD9E0E8,
+0xFFD6DAE3,
+0xFFD5D9E2,
+0xFFD4D8E1,
+0xFFD1D5DE,
+0xFFD5D9E2,
+0xFFD6DAE3,
+0xFFD4DBE3,
+0xFFD4DBE3,
+0xFFD1D8DE,
+0xFFD2D9DF,
+0xFFDADFE5,
+0xFFDDE2E8,
+0xFFDCE1E5,
+0xFFDBE0E4,
+0xFFDBE0E4,
+0xFFDADFE3,
+0xFFD9DEE4,
+0xFFD9DEE4,
+0xFFD9DEE4,
+0xFFD7DEE4,
+0xFFD9DEE4,
+0xFFD8DFE7,
+0xFFD6DDE7,
+0xFFD5DCE6,
+0xFFD4DBE5,
+0xFFD4DBE5,
+0xFFD4DBE5,
+0xFFD3DAE4,
+0xFFD0D7E1,
+0xFFCDD4DE,
+0xFFC7CDD9,
+0xFFC3CBD6,
+0xFFBEC6D1,
+0xFFBBC3CE,
+0xFFB9C1CE,
+0xFFBAC4D0,
+0xFFBCC6D2,
+0xFFBEC8D2,
+0xFFBDC7D0,
+0xFFC3CDD7,
+0xFFBFC8D9,
+0xFFD0D8EF,
+0xFF3C4360,
+0xFF343A5C,
+0xFF31395E,
+0xFF434B72,
+0xFF3F4670,
+0xFF3D426C,
+0xFF363B63,
+0xFF32375F,
+0xFF31355A,
+0xFF2D3154,
+0xFF2D304F,
+0xFF292C4B,
+0xFF272C4A,
+0xFF292D4A,
+0xFF2A2B47,
+0xFF272940,
+0xFF212639,
+0xFF1D2331,
+0xFF171E28,
+0xFF131720,
+0xFF191921,
+0xFF121119,
+0xFF000007,
+0xFFC5C9D2,
+0xFFD7E1EA,
+0xFFCAD7E0,
+0xFFCCD6E0,
+0xFFCAD2DD,
+0xFFCAD3DC,
+0xFFCDD6DF,
+0xFFCED5DD,
+0xFFCFD6DE,
+0xFFD8DCE5,
+0xFFDFE3EC,
+0xFFE1E4ED,
+0xFFE1E4ED,
+0xFFDFE2E9,
+0xFFDDE0E7,
+0xFFDDE0E7,
+0xFFE1E4EB,
+0xFFE4E7EC,
+0xFFE3E6EB,
+0xFFE1E4E9,
+0xFFE0E3E8,
+0xFFE5E6EA,
+0xFFE6E7EB,
+0xFFE1E4E9,
+0xFFDCDFE4,
+0xFFD9DCE3,
+0xFFD5DAE0,
+0xFFD4D9DF,
+0xFFD6DAE3,
+0xFFD6DAE3,
+0xFFD7DBE4,
+0xFFD7DBE4,
+0xFFD4DBE3,
+0xFFD4D8E1,
+0xFFD2D9E1,
+0xFFD9DDE6,
+0xFFDEE3E9,
+0xFFD7DCE2,
+0xFFDBDEE3,
+0xFFDCDFE6,
+0xFFDBDEE3,
+0xFFDCDFE6,
+0xFFE0E3EA,
+0xFFE3E6ED,
+0xFFE4E7EE,
+0xFFE2E5EE,
+0xFFDDE0E7,
+0xFFDADDE6,
+0xFFD9DEE4,
+0xFFDBDEE7,
+0xFFDADFE5,
+0xFFDCDFE8,
+0xFFE0E3EA,
+0xFFE0E1E5,
+0xFFE2E3E7,
+0xFFE5E6EA,
+0xFFE6E7EB,
+0xFFE5E6EB,
+0xFFE0E3E8,
+0xFFDCDFE4,
+0xFFD8DDE1,
+0xFFDBDEE5,
+0xFFDBDEE3,
+0xFFDEE1E6,
+0xFFE4E7EC,
+0xFFE6E9EE,
+0xFFE4E7EC,
+0xFFE0E4E7,
+0xFFDEE2E5,
+0xFFEBECEE,
+0xFFEEEEEE,
+0xFFEFEFEF,
+0xFFEDEFEE,
+0xFFEEEEEE,
+0xFFEEF0EF,
+0xFFEEF0EF,
+0xFFEEF0EF,
+0xFFEDEEF0,
+0xFFEDEFEE,
+0xFFECEEED,
+0xFFE9EBEA,
+0xFFE8E8E8,
+0xFFE7E7E7,
+0xFFE9E9E9,
+0xFFEBECEE,
+0xFFE9EDF0,
+0xFFE8ECEF,
+0xFFE5E8ED,
+0xFFE4E8EB,
+0xFFE5E8ED,
+0xFFE2E5EA,
+0xFFDEE1E6,
+0xFFDDE2E8,
+0xFFDFE2E9,
+0xFFDBE0E6,
+0xFFDADDE6,
+0xFFD8DCE5,
+0xFFD8DBE4,
+0xFFD7DBE4,
+0xFFD7DBE6,
+0xFFD8DCE5,
+0xFFE4E7EC,
+0xFFEDF0F5,
+0xFFECF1F7,
+0xFFADB4BC,
+0xFFD1D5E0,
+0xFFE0D9CF,
+0xFFF0D5A0,
+0xFFD38D52,
+0xFF9F1B02,
+0xFFA62F2B,
+0xFFFFDDE1,
+0xFFD9E2E9,
+0xFFD2D9DF,
+0xFFE3E8EC,
+0xFFE2E6E5,
+0xFFEAECE9,
+0xFFEAEBED,
+0xFFE6E7E9,
+0xFFE5E6EA,
+0xFFDADBDF,
+0xFFD4D5D9,
+0xFFDADBE0,
+0xFFD6D7DC,
+0xFFDBDBE3,
+0xFFD6D6DE,
+0xFFCBCED7,
+0xFFC9CCD5,
+0xFFC8CCD7,
+0xFFCDD1DD,
+0xFFCCD2DE,
+0xFFCFD5E1,
+0xFFC9D2DB,
+0xFFCBD5DE,
+0xFFCAD7DD,
+0xFFCAD7DD,
+0xFFCAD7DD,
+0xFFCED9DF,
+0xFFD0DBE1,
+0xFFD1DCE2,
+0xFFD1DBE4,
+0xFFCDDAE2,
+0xFFCBD8E1,
+0xFFC7D5E0,
+0xFFC4D2DF,
+0xFFBFCFDE,
+0xFFBCCEDC,
+0xFFBBCCDC,
+0xFFBACDDC,
+0xFFB8CBDC,
+0xFFB0C5D6,
+0xFFAEC1D2,
+0xFFADC0D1,
+0xFFACBFD0,
+0xFFAABDCE,
+0xFFA9BCCD,
+0xFFACBDCF,
+0xFFAEBFCF,
+0xFFAABBCB,
+0xFFAABACA,
+0xFFACBCCC,
+0xFFAFBFCF,
+0xFFB0C0CF,
+0xFFB2C2D1,
+0xFFB6C6D3,
+0xFFB9C7D4,
+0xFFBDC9D7,
+0xFFC0CCD8,
+0xFFC3CDD9,
+0xFFC4CED8,
+0xFFC9D1DC,
+0xFFC9D2DB,
+0xFFC6CDD7,
+0xFFCAD1D9,
+0xFFCBD2DA,
+0xFFCBD2DA,
+0xFFCBD2DA,
+0xFFCDD1DA,
+0xFFCBD2DA,
+0xFFCED2DB,
+0xFFCDD4DC,
+0xFFCBD2DC,
+0xFFC7D0D9,
+0xFFC5CDD8,
+0xFFC0CAD4,
+0xFFBCC6D2,
+0xFFB5C1CF,
+0xFFB1BDCD,
+0xFFABB8C9,
+0xFFABB8CB,
+0xFFA9B8CD,
+0xFFA5B4CB,
+0xFFA1B1CA,
+0xFF9FAFC8,
+0xFF9AABC5,
+0xFF99AAC6,
+0xFF9AAEC7,
+0xFF9DB3CA,
+0xFF97ADC2,
+0xFF99B2C8,
+0xFF98AEC3,
+0xFF94A5B7,
+0xFFACB9CA,
+0xFF9EAAB8,
+0xFF9DAABA,
+0xFF9AACC4,
+0xFF94A8C3,
+0xFF95A9C4,
+0xFF9AABC5,
+0xFF9BABC4,
+0xFF9CACC3,
+0xFF9FB1C7,
+0xFFA0B5CA,
+0xFFC3CDD7,
+0xFFCBD5DF,
+0xFFBFC7D2,
+0xFFCAD3DC,
+0xFFD0D7E1,
+0xFFC8CFD9,
+0xFFCDD5E0,
+0xFFC6CED9,
+0xFFC2CAD7,
+0xFFC6CEDB,
+0xFFBEC6D3,
+0xFFC5CBD9,
+0xFFC1C7D5,
+0xFFC5C9D5,
+0xFFD1D5E1,
+0xFFD3D8DE,
+0xFFDADFE2,
+0xFFDAE0E0,
+0xFFCFD4DA,
+0xFFCFD3DF,
+0xFFC3C8DC,
+0xFFC0C6DE,
+0xFFC1C7DF,
+0xFFBCC4D9,
+0xFFBEC7D8,
+0xFFBFCBD7,
+0xFFC6D0D9,
+0xFFC8D2DB,
+0xFFCBD5DE,
+0xFFCCD6E0,
+0xFFCBD5E1,
+0xFFCAD4E0,
+0xFFC3CDD9,
+0xFFC2CCD6,
+0xFFC1C9D6,
+0xFFC1CBD5,
+0xFFC6CED9,
+0xFFC5CFD8,
+0xFFC6CED9,
+0xFFCAD3DC,
+0xFFCDD5E0,
+0xFFCED7E0,
+0xFFC9D0DA,
+0xFFCBD2DC,
+0xFFD1D8E2,
+0xFFD1D8E2,
+0xFFD2D9E3,
+0xFFD4DBE5,
+0xFFD6DDE5,
+0xFFD3DCE3,
+0xFFD0D9DE,
+0xFFCFD8DD,
+0xFFD3DAE0,
+0xFFD4DBE1,
+0xFFD5DCE2,
+0xFFD8DFE5,
+0xFFDBE2E8,
+0xFFD8DFE5,
+0xFFD5DCE4,
+0xFFD3DAE2,
+0xFFD2D9E1,
+0xFFD1DAE1,
+0xFFD2D9E1,
+0xFFD2D9E3,
+0xFFD7DEE8,
+0xFFDADEE9,
+0xFFDADEE9,
+0xFFD7DBE6,
+0xFFD5D9E4,
+0xFFD4D8E3,
+0xFFD4D8E3,
+0xFFD1D8E2,
+0xFFD0D7E1,
+0xFFCED5DF,
+0xFFCAD0DC,
+0xFFC4CCD7,
+0xFFC1C9D4,
+0xFFC1C9D4,
+0xFFC2CAD7,
+0xFFC3CDD7,
+0xFFC3D0D8,
+0xFFC9D6DF,
+0xFFCCD8E8,
+0xFFC1CCE2,
+0xFF2B3451,
+0xFF293251,
+0xFF2F3559,
+0xFF3B4165,
+0xFF383E62,
+0xFF393D62,
+0xFF383C62,
+0xFF31355A,
+0xFF2D3154,
+0xFF2C3151,
+0xFF2A2E4B,
+0xFF292D48,
+0xFF2C2D49,
+0xFF272741,
+0xFF23203B,
+0xFF202038,
+0xFF23253A,
+0xFF212639,
+0xFF1A2133,
+0xFF151B2B,
+0xFF0C0E1D,
+0xFF090B1A,
+0xFF00000E,
+0xFF707682,
+0xFFDBE5F1,
+0xFFCAD4DE,
+0xFFCAD2DD,
+0xFFC8D0DB,
+0xFFC8D1DA,
+0xFFCBD4DD,
+0xFFCAD3DC,
+0xFFCBD4DD,
+0xFFD5DCE4,
+0xFFE0E4ED,
+0xFFE2E5EC,
+0xFFE0E3EA,
+0xFFDDE0E7,
+0xFFDADDE4,
+0xFFD9DCE3,
+0xFFDDE0E7,
+0xFFE2E5EA,
+0xFFE5E8ED,
+0xFFE2E7EB,
+0xFFE0E3E8,
+0xFFE3E4E8,
+0xFFE1E2E6,
+0xFFDBDEE3,
+0xFFDADDE2,
+0xFFDDE2E8,
+0xFFDCE1E7,
+0xFFD8DCE5,
+0xFFD4DBE5,
+0xFFD6DDE7,
+0xFFD4DBE5,
+0xFFD4DBE5,
+0xFFD4DDE6,
+0xFFD4DBE5,
+0xFFD0D9E2,
+0xFFD2D9E3,
+0xFFD5DCE4,
+0xFFDCE0E9,
+0xFFDBE0E6,
+0xFFD9DDE6,
+0xFFD6DBE1,
+0xFFD6DAE3,
+0xFFD9DDE6,
+0xFFDADEE7,
+0xFFDADEE7,
+0xFFD6DAE5,
+0xFFD4D8E1,
+0xFFD5D9E4,
+0xFFD6DDE5,
+0xFFD9DDE8,
+0xFFD6DDE5,
+0xFFD9DDE8,
+0xFFDCE0E9,
+0xFFE1E4E9,
+0xFFE1E4E9,
+0xFFE2E5EA,
+0xFFE3E6EB,
+0xFFE0E3EA,
+0xFFDADFE5,
+0xFFD8DDE3,
+0xFFD6DDE3,
+0xFFD8DCE5,
+0xFFD6DBE1,
+0xFFDBE0E6,
+0xFFE3E8EE,
+0xFFE4E9ED,
+0xFFE5EAEE,
+0xFFE7EAEF,
+0xFFE4E8EB,
+0xFFE8E9EB,
+0xFFE9EAEC,
+0xFFEBECEE,
+0xFFE9EDEE,
+0xFFEBECEE,
+0xFFE9EDEE,
+0xFFE9EDEE,
+0xFFE7EBEC,
+0xFFE9EDF0,
+0xFFE9EDEE,
+0xFFE9EDEE,
+0xFFE8ECED,
+0xFFE8E9EB,
+0xFFE8E9EB,
+0xFFE9EAEC,
+0xFFEBECEE,
+0xFFE9ECF1,
+0xFFE8EDF1,
+0xFFE6EBF1,
+0xFFE2E7EB,
+0xFFE0E5EB,
+0xFFDBE0E6,
+0xFFDADFE5,
+0xFFDBE2EA,
+0xFFDBDFE8,
+0xFFD7DEE6,
+0xFFD6DAE5,
+0xFFD2D9E3,
+0xFFD3D7E2,
+0xFFD0D7E1,
+0xFFCFD5E1,
+0xFFD2D6DF,
+0xFFE3E4E8,
+0xFFECF0F3,
+0xFFE7F0F7,
+0xFFA6B0B9,
+0xFFC7CFDA,
+0xFFE4D9D3,
+0xFFF0C39A,
+0xFFC56E41,
+0xFF991405,
+0xFFA83837,
+0xFFFCE2E5,
+0xFFD2E1E6,
+0xFFCFDADE,
+0xFFDCE4E7,
+0xFFE3E9E9,
+0xFFE2E6E5,
+0xFFE0E4E5,
+0xFFDFE3E6,
+0xFFDBDEE3,
+0xFFC8CBD0,
+0xFFC7C8CD,
+0xFFDBDCE1,
+0xFFD9D9E1,
+0xFFD9D9E3,
+0xFFD0D3DC,
+0xFFCCCEDA,
+0xFFC8CAD7,
+0xFFC8CCD8,
+0xFFC4CAD8,
+0xFFC7CFDC,
+0xFFC5CCDC,
+0xFFC0C9D8,
+0xFFBDC9D7,
+0xFFBCCAD7,
+0xFFBCCAD7,
+0xFFBBC9D6,
+0xFFBBC8D8,
+0xFFBBC8D8,
+0xFFB9C9D8,
+0xFFB8C8D8,
+0xFFB7C7D7,
+0xFFB4C3D6,
+0xFFAFC0D2,
+0xFFAEBFD3,
+0xFFAABCD2,
+0xFFA4B9CE,
+0xFFA1B5CD,
+0xFF9FB3CB,
+0xFFA3B8CD,
+0xFFA3B9CE,
+0xFFA6BBD0,
+0xFFA6BBD0,
+0xFFA5BACF,
+0xFFA6BBD0,
+0xFFA9BED3,
+0xFFAFC1D7,
+0xFFABBDD3,
+0xFFAABCD2,
+0xFFAABCD2,
+0xFFABBDD1,
+0xFFABBDD1,
+0xFFABBDD1,
+0xFFABBDD1,
+0xFFABBECF,
+0xFFAEBFD1,
+0xFFB2C3D5,
+0xFFB1C2D4,
+0xFFB0BFD2,
+0xFFB5C5D5,
+0xFFBAC7D8,
+0xFFBBC8D8,
+0xFFBECADA,
+0xFFBCC8D6,
+0xFFBBC7D5,
+0xFFBCC8D6,
+0xFFBFCBD9,
+0xFFC3CCDB,
+0xFFC2CEDC,
+0xFFC4CDDC,
+0xFFC3CFDD,
+0xFFC5D1DD,
+0xFFCBD7E3,
+0xFFCDD9E7,
+0xFFC5D3E0,
+0xFFC6D3E3,
+0xFFB6C6D6,
+0xFFADBCCF,
+0xFFAABBCF,
+0xFFAABAD3,
+0xFFA4B5CF,
+0xFFA0B1CD,
+0xFF9CAFCD,
+0xFF99ACCC,
+0xFF97ACCB,
+0xFF98ACCD,
+0xFF95ACCC,
+0xFF8EA8C3,
+0xFF92ACC5,
+0xFF92ACC7,
+0xFF8CA4BE,
+0xFF98AAC2,
+0xFFABBCD0,
+0xFF91A1B1,
+0xFF98A9BB,
+0xFF93A8C3,
+0xFF8FA6C6,
+0xFF92A9C9,
+0xFF95A9CA,
+0xFF95A8C9,
+0xFF9BAECE,
+0xFF9DB2CF,
+0xFF98B0CC,
+0xFFBDC9D5,
+0xFFCCD8E4,
+0xFFC3CDD7,
+0xFFC4CED8,
+0xFF848C97,
+0xFFADB5C0,
+0xFFC3CDD9,
+0xFFBCC5D4,
+0xFFBEC7D8,
+0xFFB2BBCC,
+0xFFB5BECF,
+0xFFAFB8C9,
+0xFFA9B2C3,
+0xFFB4BBCD,
+0xFFBAC1D1,
+0xFFC4CCD7,
+0xFFC3CCD1,
+0xFFBFCACE,
+0xFFC2CAD5,
+0xFFBEC7D8,
+0xFFBBC3DA,
+0xFFC2C9E3,
+0xFFBDC4DE,
+0xFFBAC4DD,
+0xFFBBC6DA,
+0xFFB2BDCF,
+0xFFB8C4D2,
+0xFFC0CCDA,
+0xFFC2CEDE,
+0xFFCDD8EA,
+0xFFC3CEE2,
+0xFFC1CCE0,
+0xFFBCC8D8,
+0xFFBBC7D5,
+0xFFBFCBD9,
+0xFFC9D5E3,
+0xFFD1DDE9,
+0xFFCDD9E5,
+0xFFC4D0DC,
+0xFFBFCBD7,
+0xFFC0CAD6,
+0xFFC8D2DC,
+0xFFC9D3DD,
+0xFFCAD4DE,
+0xFFCED6E1,
+0xFFCAD3DC,
+0xFFC9D1DC,
+0xFFCFD8E1,
+0xFFD2DBE4,
+0xFFD4DDE4,
+0xFFD5DEE5,
+0xFFD7E0E5,
+0xFFD8DFE7,
+0xFFD4DBE1,
+0xFFD0D7DF,
+0xFFD1D8E0,
+0xFFD1D8E0,
+0xFFCED5DD,
+0xFFCCD3DD,
+0xFFCBD4DD,
+0xFFCCD5DE,
+0xFFCBD5DE,
+0xFFCBD5DF,
+0xFFCBD3DE,
+0xFFCCD2DE,
+0xFFCFD5E1,
+0xFFD0D6E2,
+0xFFD0D6E2,
+0xFFD1D7E3,
+0xFFD3DAE4,
+0xFFD6DCE8,
+0xFFD7DDE9,
+0xFFDBE3EE,
+0xFFDBE3EE,
+0xFFD9E1EC,
+0xFFD6DEEB,
+0xFFD1D9E6,
+0xFFCCD6E2,
+0xFFCBD5E1,
+0xFFC8D4E0,
+0xFFC3D1DA,
+0xFFC9D7E4,
+0xFFC9D6E9,
+0xFFAEB8D3,
+0xFF222B4A,
+0xFF313A5B,
+0xFF313759,
+0xFF303658,
+0xFF2E3255,
+0xFF303457,
+0xFF34385B,
+0xFF2E3255,
+0xFF292E4E,
+0xFF2A2F4D,
+0xFF282C49,
+0xFF292D48,
+0xFF2A2C45,
+0xFF2A2A42,
+0xFF29273F,
+0xFF26243C,
+0xFF202237,
+0xFF1D2236,
+0xFF1F2438,
+0xFF22273A,
+0xFF2D2E42,
+0xFF151426,
+0xFF000012,
+0xFF959BAB,
+0xFFBECAD8,
+0xFFBECCD9,
+0xFFC7D1DD,
+0xFFC6D0DC,
+0xFFC8D2DC,
+0xFFCAD3DC,
+0xFFC9D2DB,
+0xFFCDD6DF,
+0xFFDAE1EB,
+0xFFE1E8F0,
+0xFFE1E5EE,
+0xFFDCDFE6,
+0xFFDADDE4,
+0xFFD8DBE2,
+0xFFD7DAE1,
+0xFFD9DCE3,
+0xFFDFE2E9,
+0xFFE2E7EB,
+0xFFE2E7ED,
+0xFFE0E5E9,
+0xFFDDE0E5,
+0xFFDEE1E6,
+0xFFDBE0E6,
+0xFFD9DEE4,
+0xFFD6DDE5,
+0xFFD4DBE3,
+0xFFD3DAE4,
+0xFFD4DDE6,
+0xFFD5DBE7,
+0xFFD2DBE4,
+0xFFD2DAE5,
+0xFFD6DFE8,
+0xFFD5DEE7,
+0xFFD0D9E2,
+0xFFCCD5DE,
+0xFFCCD5DE,
+0xFFCDD4DE,
+0xFFCFD6DE,
+0xFFD2D9E3,
+0xFFD5DCE6,
+0xFFD7DEE8,
+0xFFD7DEE8,
+0xFFD4DBE5,
+0xFFD1D8E2,
+0xFFD0D6E2,
+0xFFCED5DF,
+0xFFCDD3DF,
+0xFFCCD5DE,
+0xFFCDD5E0,
+0xFFCFD8E1,
+0xFFD3DBE6,
+0xFFD9E0EA,
+0xFFE0E4ED,
+0xFFDFE4EA,
+0xFFDEE2EB,
+0xFFDCE0E9,
+0xFFD7DEE6,
+0xFFD3DAE2,
+0xFFD3DAE4,
+0xFFD4DDE6,
+0xFFD7E0E9,
+0xFFD4DDE4,
+0xFFDAE1E9,
+0xFFDFE6EC,
+0xFFDCE3E9,
+0xFFE0E5EB,
+0xFFE4E9EF,
+0xFFE3E6EB,
+0xFFE6EAED,
+0xFFE7EBEE,
+0xFFE7EBEE,
+0xFFE6EBEE,
+0xFFE7ECEF,
+0xFFE8EDF0,
+0xFFE8EDF1,
+0xFFE7ECF0,
+0xFFE4E9ED,
+0xFFE4E9ED,
+0xFFE3E8EB,
+0xFFE4E9EC,
+0xFFE5EAED,
+0xFFE7EBEE,
+0xFFE7EBEE,
+0xFFE6E9EE,
+0xFFE5EAF0,
+0xFFE7ECF2,
+0xFFE6EBF1,
+0xFFDFE4EA,
+0xFFD8DDE3,
+0xFFD1D8E0,
+0xFFD2D9E1,
+0xFFD8E1EA,
+0xFFD1D9E4,
+0xFFD0D8E3,
+0xFFCFD7E2,
+0xFFCED6E1,
+0xFFCDD5E2,
+0xFFCAD4E0,
+0xFFC8D2DE,
+0xFFC9D0DA,
+0xFFE4E5E9,
+0xFFF0F1F5,
+0xFFEAF1F9,
+0xFFAEB8C2,
+0xFFC9D5E1,
+0xFFDDD5D3,
+0xFFBA8D6C,
+0xFF691900,
+0xFF9F2D22,
+0xFFB65A5B,
+0xFFEAD5DA,
+0xFFC9D8DF,
+0xFFD2DFE5,
+0xFFCED7DC,
+0xFFDFE4E8,
+0xFFE2E6E9,
+0xFFDDE2E6,
+0xFFD6DBDF,
+0xFFCFD4DA,
+0xFFC7CAD1,
+0xFFCCCFD6,
+0xFFCACDD4,
+0xFFD4D4DE,
+0xFFD0D2DE,
+0xFFCDCFDC,
+0xFFCACEDA,
+0xFFCFD2E1,
+0xFFC0C6D6,
+0xFFC6CDDD,
+0xFFBDC6D7,
+0xFFC2CBDC,
+0xFFB8C3D5,
+0xFFB6C3D6,
+0xFFB2C1D6,
+0xFFAEBDD2,
+0xFFAABBCF,
+0xFFA9B9D0,
+0xFFA9B9D0,
+0xFFA7B9D1,
+0xFFA6B8D0,
+0xFFA6B8D0,
+0xFFA3B4CE,
+0xFFA2B3CD,
+0xFFA0B4CD,
+0xFFA0B4CD,
+0xFF9EB2CD,
+0xFF9DB1CC,
+0xFF9DB2CD,
+0xFF97ADC5,
+0xFF99AFC7,
+0xFF99AFC7,
+0xFF98AEC6,
+0xFF97ADC5,
+0xFF98AEC6,
+0xFF9BB1C9,
+0xFF9CB2CA,
+0xFFA6BAD3,
+0xFFA7BDD5,
+0xFFA5BBD3,
+0xFFA1B7CF,
+0xFFA1B7CF,
+0xFFA5BBD2,
+0xFFABC1D8,
+0xFFAEC2DA,
+0xFFB2C4DC,
+0xFFB1C3D9,
+0xFFB1C3D9,
+0xFFB3C5DB,
+0xFFB5C5DC,
+0xFFB4C5D9,
+0xFFB5C6DA,
+0xFFBAC9DE,
+0xFFBAC9DC,
+0xFFBCCBDE,
+0xFFBDCCDF,
+0xFFBDCCE1,
+0xFFBCCBE0,
+0xFFBBCADF,
+0xFFB9C8DD,
+0xFFB6C7D9,
+0xFFB3C4D6,
+0xFFB6C7D9,
+0xFFB7CADB,
+0xFFB0C2D6,
+0xFFA7BCD1,
+0xFF9EB2CA,
+0xFF9BB1C9,
+0xFF9BB0CB,
+0xFF94ACC8,
+0xFF8DA4C3,
+0xFF88A0C2,
+0xFF869EC0,
+0xFF819BBE,
+0xFF809ABF,
+0xFF809CC3,
+0xFF7D99BE,
+0xFF83A0C2,
+0xFF7F9CBC,
+0xFF83A0C0,
+0xFF859EBD,
+0xFF879CB9,
+0xFFA1B3CB,
+0xFF96A7B9,
+0xFF8D9FB3,
+0xFF869DBC,
+0xFF859FC2,
+0xFF87A1C6,
+0xFF859DC3,
+0xFF8298BF,
+0xFF859BC2,
+0xFF859DBF,
+0xFF7C96B7,
+0xFFA4B5C7,
+0xFF9FB0C2,
+0xFFA8B7CA,
+0xFFA5B4C7,
+0xFF7C8B9E,
+0xFF808FA2,
+0xFFA3B4C8,
+0xFFA5B6CA,
+0xFF9EB0C6,
+0xFFA4B6CE,
+0xFFA3B5CD,
+0xFFA1B3CB,
+0xFFA2B4CC,
+0xFFB2C2D9,
+0xFFA9B8CF,
+0xFFACBBD0,
+0xFFA9BACC,
+0xFFA3B6C5,
+0xFFABBCCE,
+0xFFA9BACE,
+0xFFA9B9D0,
+0xFFA8B8D1,
+0xFFA4B4CD,
+0xFFA5B3CD,
+0xFFA7B5CF,
+0xFFA6B5CC,
+0xFFAAB9D0,
+0xFFB3C1DB,
+0xFFB3C1DB,
+0xFFB8C6E1,
+0xFFBDCBE6,
+0xFFB9C7E1,
+0xFFBCCBDE,
+0xFFB7C7D7,
+0xFFB8C8D8,
+0xFFC0D0E0,
+0xFFC9D6E6,
+0xFFCCD9E9,
+0xFFCBD9E6,
+0xFFC9D7E4,
+0xFFC1CFDC,
+0xFFC5D3E0,
+0xFFC5D1DF,
+0xFFC7D3DF,
+0xFFCEDAE6,
+0xFFCDDAE3,
+0xFFC7D3DF,
+0xFFCAD7E0,
+0xFFCED8E1,
+0xFFCDD7E0,
+0xFFCAD4DD,
+0xFFC8D3D9,
+0xFFC8D1DA,
+0xFFC6CFD6,
+0xFFC5CED7,
+0xFFC7D0D9,
+0xFFCBD4DD,
+0xFFC9D2DB,
+0xFFC7CFDA,
+0xFFC5CFD9,
+0xFFC6D0DA,
+0xFFC4D1DA,
+0xFFC2CEDA,
+0xFFC0CCD8,
+0xFFC0CAD6,
+0xFFC1CBD7,
+0xFFC2CCD8,
+0xFFC2CCD8,
+0xFFC3CDD9,
+0xFFC7D1DB,
+0xFFCBD5E1,
+0xFFCDD7E3,
+0xFFD0DAE6,
+0xFFD2DCE8,
+0xFFD3DDE9,
+0xFFD1DDEB,
+0xFFCDD9E7,
+0xFFC9D5E3,
+0xFFC5D3E0,
+0xFFC2D2E1,
+0xFFC0D1E1,
+0xFFC0D1E5,
+0xFFBECCE7,
+0xFF9CA6C9,
+0xFF1F274C,
+0xFF2F375C,
+0xFF31375B,
+0xFF2C3053,
+0xFF303354,
+0xFF2D3051,
+0xFF2F3253,
+0xFF292C4D,
+0xFF282B4C,
+0xFF2B2E4D,
+0xFF252A47,
+0xFF252B45,
+0xFF232941,
+0xFF21263C,
+0xFF202038,
+0xFF1F1D33,
+0xFF1B1C30,
+0xFF191A2C,
+0xFF17182A,
+0xFF181729,
+0xFF161125,
+0xFF161125,
+0xFF060719,
+0xFF313848,
+0xFFC0CDDD,
+0xFFB0C2D0,
+0xFFADBECE,
+0xFFB4C4D3,
+0xFFBCC8D4,
+0xFFC1CBD5,
+0xFFC5CFD9,
+0xFFCED8E1,
+0xFFDAE3EC,
+0xFFDEE5ED,
+0xFFDAE1E9,
+0xFFD9DDE6,
+0xFFD5D9E2,
+0xFFD8DCE5,
+0xFFDBDFE8,
+0xFFDEE2EB,
+0xFFE0E4ED,
+0xFFDFE6EC,
+0xFFDDE4EC,
+0xFFDAE1E9,
+0xFFD8DFE7,
+0xFFDAE1E9,
+0xFFD8E1E8,
+0xFFD5DEE5,
+0xFFD3DCE5,
+0xFFCFD7E2,
+0xFFCED6E1,
+0xFFD0DAE4,
+0xFFD1D9E6,
+0xFFCED8E2,
+0xFFCFD9E5,
+0xFFD4DEE8,
+0xFFD5DFE9,
+0xFFD2DCE6,
+0xFFCFD8E1,
+0xFFCED7E0,
+0xFFC8D1DA,
+0xFFC8D1DA,
+0xFFC9D1DC,
+0xFFCBD3DE,
+0xFFCED6E1,
+0xFFD1D9E4,
+0xFFD1D9E4,
+0xFFCFD7E2,
+0xFFCDD5E2,
+0xFFCAD2DD,
+0xFFC8D0DD,
+0xFFC7D1DB,
+0xFFC7D1DD,
+0xFFC7D1DB,
+0xFFC9D3DF,
+0xFFCBD5DF,
+0xFFD4DDE6,
+0xFFD7DEE8,
+0xFFD6DFE8,
+0xFFD3DCE5,
+0xFFCFD7E2,
+0xFFCDD7E1,
+0xFFCCD6E0,
+0xFFCCD6E0,
+0xFFCDD7E1,
+0xFFCDD7E1,
+0xFFD6DEE9,
+0xFFDAE3EC,
+0xFFD7E0E9,
+0xFFDAE1E9,
+0xFFE0E7EF,
+0xFFE2E7ED,
+0xFFE5EAF0,
+0xFFE3E8EE,
+0xFFE0E5EB,
+0xFFDAE1E7,
+0xFFD9E0E8,
+0xFFDAE1E9,
+0xFFDBE2EA,
+0xFFDBE2EA,
+0xFFDEE5ED,
+0xFFDDE4EC,
+0xFFDBE2EA,
+0xFFDCE3EB,
+0xFFDEE5EB,
+0xFFE1E6EC,
+0xFFDFE4EA,
+0xFFDEE3E9,
+0xFFDADEE7,
+0xFFDCE0E9,
+0xFFD9E0E8,
+0xFFD5DCE4,
+0xFFD0D7DF,
+0xFFCAD3DC,
+0xFFC9D1DC,
+0xFFCCD6E0,
+0xFFC5D1DD,
+0xFFC5D1DF,
+0xFFC5D3E0,
+0xFFC5D2E2,
+0xFFC4D1E2,
+0xFFC0D0E0,
+0xFFBDCDDD,
+0xFFBFC9D5,
+0xFFE2E3E8,
+0xFFF2F0F5,
+0xFFE7EAF3,
+0xFFA5ADBA,
+0xFFBFCCDD,
+0xFFDADEE1,
+0xFFAA9173,
+0xFF552000,
+0xFF480000,
+0xFFA96D6C,
+0xFFE9DCE3,
+0xFFCCD6E0,
+0xFFCAD4DE,
+0xFFD0DAE4,
+0xFFD8DFE9,
+0xFFD9DDE6,
+0xFFD3DAE4,
+0xFFC7CED8,
+0xFFC6CDD7,
+0xFFBABEC9,
+0xFFC1C5D0,
+0xFFB2B6C1,
+0xFFC6C8D5,
+0xFFC9CDD9,
+0xFFC3C6D5,
+0xFFC2C8D8,
+0xFFBEC5D5,
+0xFFB9C2D3,
+0xFFB9C5D5,
+0xFFBDCADB,
+0xFFBCC9DA,
+0xFFB5C4D9,
+0xFFB0C0D9,
+0xFFABBCD6,
+0xFFA8B9D5,
+0xFFA6B7D3,
+0xFFA3B6D4,
+0xFFA3B6D4,
+0xFFA1B6D3,
+0xFFA0B5D2,
+0xFF9FB4D1,
+0xFFA0B5D4,
+0xFFA2B7D6,
+0xFFA3B6D4,
+0xFFA0B3D1,
+0xFF9CAFCD,
+0xFF99ACCA,
+0xFF98ABC9,
+0xFF9AAFCA,
+0xFF96AEC8,
+0xFF92AAC4,
+0xFF8FA7C1,
+0xFF90A8C4,
+0xFF93ABC7,
+0xFF93ABC7,
+0xFF91A9C5,
+0xFF94A9C8,
+0xFF93AAC9,
+0xFF96ADCC,
+0xFF99B0CF,
+0xFF9BB2D1,
+0xFF9CB4D0,
+0xFF9DB5D1,
+0xFFA0B5D0,
+0xFFA6BAD3,
+0xFFA3B5CD,
+0xFFA5B7CF,
+0xFFA7B9D1,
+0xFFA2B4CC,
+0xFFA4B6CE,
+0xFFAABCD4,
+0xFFAABAD3,
+0xFFACBCD5,
+0xFFB2C2DB,
+0xFFB3C5DD,
+0xFFAFC0DA,
+0xFFAABBD5,
+0xFFA6B7D1,
+0xFFA0B4CD,
+0xFF9BB1C9,
+0xFF97AFC9,
+0xFF8EA8C1,
+0xFF90AAC3,
+0xFF8FA9C4,
+0xFF7E99B4,
+0xFF7F9AB7,
+0xFF819EBC,
+0xFF7B98B8,
+0xFF7997B9,
+0xFF7391B5,
+0xFF7090B7,
+0xFF6F8FB6,
+0xFF6A8BB4,
+0xFF6A8BB4,
+0xFF6A8DB7,
+0xFF698AB3,
+0xFF6A8AB1,
+0xFF6D8BB1,
+0xFF708EB4,
+0xFF758FB2,
+0xFF768AAB,
+0xFF91A2BE,
+0xFF92A3B7,
+0xFF77899F,
+0xFF758EAD,
+0xFF6F8BB2,
+0xFF728EB6,
+0xFF7793BB,
+0xFF788FBB,
+0xFF768DB7,
+0xFF7690B5,
+0xFF7491B3,
+0xFF92A6BE,
+0xFF9CB0C8,
+0xFF92A6BE,
+0xFFA5B9D1,
+0xFF9BAFC7,
+0xFF9DB1C9,
+0xFF9CB2CA,
+0xFF9DB2CD,
+0xFF9DB5D1,
+0xFF91A9C5,
+0xFF88A1BF,
+0xFF859EBC,
+0xFF95ADC9,
+0xFF6D85A1,
+0xFF9EB3CE,
+0xFF9CB1CC,
+0xFFA2B8D0,
+0xFF9FB7CF,
+0xFFA4BCD4,
+0xFFAEC4DC,
+0xFFB2C6DF,
+0xFFA5B9D1,
+0xFFA8BAD0,
+0xFFA3B4C8,
+0xFF9FB0C2,
+0xFF9EADC0,
+0xFF8C9BAE,
+0xFF95A4B7,
+0xFFA7B6CB,
+0xFFA3B2C9,
+0xFFB4C3DA,
+0xFFACBBD2,
+0xFFABBCD0,
+0xFFA9BBCF,
+0xFFACBED2,
+0xFFB1C4D5,
+0xFFB3C4D6,
+0xFFB5C6D6,
+0xFFB8C9D9,
+0xFFB9CADA,
+0xFFB9CADA,
+0xFFB6C8D6,
+0xFFB5C5D4,
+0xFFB6C6D3,
+0xFFBDCDDA,
+0xFFBFD0DA,
+0xFFBBCBD8,
+0xFFC0CED9,
+0xFFC5D2DB,
+0xFFCBD5DE,
+0xFFCCD6E0,
+0xFFCCD6DF,
+0xFFCED6E1,
+0xFFCBD4DD,
+0xFFC6CED9,
+0xFFC3CBD6,
+0xFFC3CBD6,
+0xFFC1CBD7,
+0xFFC0CAD6,
+0xFFBFCBD9,
+0xFFC1CDDB,
+0xFFC2D0DD,
+0xFFC1CFDC,
+0xFFBECEDD,
+0xFFB7C4D4,
+0xFFB5C5D4,
+0xFFB5C2D2,
+0xFFB1C1D0,
+0xFFB4C1D1,
+0xFFB7C5D2,
+0xFFB9C7D4,
+0xFFBAC8D5,
+0xFFC4D1E1,
+0xFFC3D3E2,
+0xFFC4D1E1,
+0xFFC0D0DF,
+0xFFBACADA,
+0xFFB4C5D5,
+0xFFAFC0D0,
+0xFFACBFCE,
+0xFFABBECD,
+0xFFAABCD0,
+0xFFADBCD9,
+0xFF98A5C7,
+0xFF1B2549,
+0xFF20264A,
+0xFF272C4C,
+0xFF252946,
+0xFF292D48,
+0xFF292D48,
+0xFF2C304D,
+0xFF2B2F4C,
+0xFF292C4B,
+0xFF282C49,
+0xFF232943,
+0xFF232941,
+0xFF1F253B,
+0xFF1E2339,
+0xFF202136,
+0xFF232136,
+0xFF262739,
+0xFF282A39,
+0xFF222431,
+0xFF1C1B29,
+0xFF181423,
+0xFF0D0918,
+0xFF000110,
+0xFF5C6373,
+0xFFC1D1E0,
+0xFFB5C8D7,
+0xFFB1C6D7,
+0xFFBACDDC,
+0xFFBACAD7,
+0xFFC1CDD9,
+0xFFC4D0DC,
+0xFFCBD5DF,
+0xFFD0DAE4,
+0xFFD2DBE4,
+0xFFD3DCE5,
+0xFFD6DDE5,
+0xFFD3DAE2,
+0xFFD6DDE5,
+0xFFDDE1EA,
+0xFFDEE5ED,
+0xFFDEE5ED,
+0xFFDCE3EB,
+0xFFDAE1E9,
+0xFFD7E0E9,
+0xFFD7E1EA,
+0xFFD5DFE9,
+0xFFD1DEE7,
+0xFFD1DEE7,
+0xFFD2DEEA,
+0xFFCEDAE6,
+0xFFCAD6E2,
+0xFFCAD6E2,
+0xFFCFDBE9,
+0xFFCFD9E5,
+0xFFCED8E4,
+0xFFCFD9E5,
+0xFFD0DAE4,
+0xFFD0DAE4,
+0xFFD0D9E2,
+0xFFCFD8E1,
+0xFFD0DAE4,
+0xFFCCD9E2,
+0xFFCBD5E1,
+0xFFC8D4E0,
+0xFFCCD6E2,
+0xFFCDD9E5,
+0xFFD0DCE8,
+0xFFD1DDE9,
+0xFFD3DFEB,
+0xFFD1DDE9,
+0xFFD0DCE8,
+0xFFD0DCE8,
+0xFFCFDBE7,
+0xFFCBD9E4,
+0xFFCAD6E2,
+0xFFC9D5E1,
+0xFFC9D3DF,
+0xFFCDD7E3,
+0xFFD0DAE6,
+0xFFCEDAE6,
+0xFFCBD7E3,
+0xFFC9D5E3,
+0xFFC7D3E1,
+0xFFC3D1DE,
+0xFFC1CDDB,
+0xFFC2CEDA,
+0xFFC7D3DF,
+0xFFCCD6E0,
+0xFFCAD4DE,
+0xFFCFD8E1,
+0xFFD6DFE8,
+0xFFD9E2EB,
+0xFFD7DEE8,
+0xFFD7E0E9,
+0xFFD6DDE7,
+0xFFD1DAE3,
+0xFFCED6E1,
+0xFFCBD5DF,
+0xFFCBD3DE,
+0xFFCAD4DE,
+0xFFCAD2DD,
+0xFFC7D1DB,
+0xFFC7CFDA,
+0xFFC6CED9,
+0xFFC7D0D9,
+0xFFC8D1DA,
+0xFFC8CFD9,
+0xFFC7CED8,
+0xFFCBCFD8,
+0xFFCBCFD8,
+0xFFCAD1D9,
+0xFFCCD3DB,
+0xFFCED7E0,
+0xFFCAD4DE,
+0xFFC2CCD8,
+0xFFBDC9D7,
+0xFFBBC9D6,
+0xFFB9C9D8,
+0xFFB9CADA,
+0xFFB9CADC,
+0xFFB7C9DD,
+0xFFB5C7DB,
+0xFFB1C3D7,
+0xFFAFBFCE,
+0xFFDADDE4,
+0xFFF5F4FA,
+0xFFEEF1FA,
+0xFFA9B0C0,
+0xFFB5C6DA,
+0xFFD2D9DF,
+0xFF9D8968,
+0xFF542900,
+0xFF410400,
+0xFF703F3B,
+0xFFEADEE8,
+0xFFC7D0DF,
+0xFFC5D3E0,
+0xFFCAD6E4,
+0xFFCBD3E0,
+0xFFCBD3E0,
+0xFFC5CDDA,
+0xFFB9C1CE,
+0xFFBFC7D4,
+0xFFA3A9B7,
+0xFFA1A7B5,
+0xFF999FAD,
+0xFFABAEBF,
+0xFFB8BECE,
+0xFFACB2C2,
+0xFFB2B9CB,
+0xFFAEB7C8,
+0xFFAFBACC,
+0xFFAEBBCC,
+0xFFB4C3D6,
+0xFFB0BFD2,
+0xFFAFC0D4,
+0xFFA9BAD4,
+0xFFA5B9D4,
+0xFFA3B6D4,
+0xFFA1B6D3,
+0xFF9FB4D3,
+0xFF9AB1D0,
+0xFF99B0CF,
+0xFF99B0CF,
+0xFF97AECD,
+0xFF9AB1D0,
+0xFF9DB2CF,
+0xFF9BAECC,
+0xFF99ADC8,
+0xFF9AABC5,
+0xFF9AABC5,
+0xFF99ABC3,
+0xFF97A9C1,
+0xFF98ACC4,
+0xFF9CAEC6,
+0xFF9BAFC7,
+0xFF9CB0C9,
+0xFFA0B4CD,
+0xFFA5B9D2,
+0xFFA8BCD5,
+0xFFA4B8D3,
+0xFF99ADC8,
+0xFF93A8C3,
+0xFF98ADC8,
+0xFF9BB0CB,
+0xFF98ADC8,
+0xFF99AFC7,
+0xFF9FB3CB,
+0xFFA1B3C9,
+0xFFA4B5C9,
+0xFFABBCD0,
+0xFFAABBCF,
+0xFFA6B7CB,
+0xFFACBDD1,
+0xFFAEBED5,
+0xFFA1B3C9,
+0xFFA4B6CE,
+0xFFA6B8D0,
+0xFFA4B8D1,
+0xFFA2B6CF,
+0xFF9FB3CE,
+0xFF9AAFCA,
+0xFF93A8C3,
+0xFF8AA2BE,
+0xFF869EBA,
+0xFF86A0BB,
+0xFF7E98B3,
+0xFF7F98B6,
+0xFF7E99B6,
+0xFF7E99B7,
+0xFF7390B0,
+0xFF728FAF,
+0xFF6D8BAD,
+0xFF6C8AAE,
+0xFF6D8DB3,
+0xFF7191B8,
+0xFF7092B8,
+0xFF7091BA,
+0xFF6E91B9,
+0xFF6D8EB7,
+0xFF6686AF,
+0xFF7393BC,
+0xFF6E8BB3,
+0xFF6B87AC,
+0xFF7589AC,
+0xFF8B9FBA,
+0xFF8E9FB1,
+0xFF718699,
+0xFF6E87A6,
+0xFF6B89AD,
+0xFF6D8BB1,
+0xFF6E8BB3,
+0xFF728AB6,
+0xFF728BB4,
+0xFF718DB2,
+0xFF728FB1,
+0xFF859AB7,
+0xFF889DBA,
+0xFF768BA6,
+0xFF5F748F,
+0xFF7D92AD,
+0xFF7C94AE,
+0xFF809AB5,
+0xFF89A2C0,
+0xFF8FAAC8,
+0xFF90AACB,
+0xFF84A1C1,
+0xFF87A4C4,
+0xFF849FBD,
+0xFF0C2745,
+0xFF8CA5C3,
+0xFF88A1BF,
+0xFF8CA6C1,
+0xFF90AAC5,
+0xFF94ADCB,
+0xFFA2BAD6,
+0xFFAEC3DE,
+0xFFAEC0D6,
+0xFFA4B5C5,
+0xFF8E9FA9,
+0xFF76858A,
+0xFF627272,
+0xFF2E3C3C,
+0xFF354343,
+0xFF536162,
+0xFF626F75,
+0xFF839099,
+0xFFAAB8C5,
+0xFFA2B4C8,
+0xFFA0B5CA,
+0xFFA4B9CE,
+0xFFA4B9CE,
+0xFFA3B5CB,
+0xFFA7B9CD,
+0xFFAFC1D5,
+0xFFB2C5D6,
+0xFFB2C5D6,
+0xFFB4C7D6,
+0xFFBACBDB,
+0xFFB5C7D5,
+0xFFAFC1CF,
+0xFFB0C2CE,
+0xFFB5C7D5,
+0xFFC1D1DE,
+0xFFC6D4DF,
+0xFFC9D6DF,
+0xFFC8D2DE,
+0xFFC5CFD9,
+0xFFC7D1DD,
+0xFFCBD5DF,
+0xFFCBD5E1,
+0xFFCBD5E1,
+0xFFC9D3DF,
+0xFFC7D0DF,
+0xFFC4CDDC,
+0xFFBFCBDB,
+0xFFBBC8D8,
+0xFFB5C5D4,
+0xFFB1C1D0,
+0xFFAEBFCF,
+0xFFB1C4D5,
+0xFFAFC4D7,
+0xFFB0C2D6,
+0xFFAEC3D4,
+0xFFAFC2D3,
+0xFFAFC2D3,
+0xFFAEC1D2,
+0xFFACBFD0,
+0xFFA8BBCC,
+0xFFA7BCCD,
+0xFFABBDD1,
+0xFFABC0D3,
+0xFFACC1D4,
+0xFFABC2D4,
+0xFFABC1D6,
+0xFFABC2D2,
+0xFFABC3CF,
+0xFFB0C6D3,
+0xFFAEBED5,
+0xFFBAC8E3,
+0xFF1C2743,
+0xFF222946,
+0xFF1C223A,
+0xFF191E32,
+0xFF1E2134,
+0xFF232639,
+0xFF292B40,
+0xFF2D2F46,
+0xFF282C45,
+0xFF22273D,
+0xFF21283B,
+0xFF22293B,
+0xFF26283D,
+0xFF2D2E42,
+0xFF302F41,
+0xFF2A2939,
+0xFF212330,
+0xFF191D28,
+0xFF11151E,
+0xFF0B0E17,
+0xFF0E0E18,
+0xFF0C0C18,
+0xFF080C18,
+0xFF2A3440,
+0xFFD0E0EF,
+0xFFBACDDC,
+0xFFB7CADB,
+0xFFBBCEDD,
+0xFFC2D2E1,
+0xFFC7D5E2,
+0xFFC7D5E2,
+0xFFC6D2DE,
+0xFFC7D3DF,
+0xFFCBD5DF,
+0xFFCED6E1,
+0xFFD1DAE3,
+0xFFD1DAE3,
+0xFFD1DAE3,
+0xFFD5DCE6,
+0xFFD7E0E9,
+0xFFD6DFE8,
+0xFFD2DBE4,
+0xFFD0D9E2,
+0xFFCED8E1,
+0xFFC9D5E1,
+0xFFCBD9E4,
+0xFFCBD9E6,
+0xFFC9D7E4,
+0xFFC4D2DF,
+0xFFBECCD9,
+0xFFBECCD9,
+0xFFC5D3E0,
+0xFFC7D4E4,
+0xFFC7D3E1,
+0xFFC5D1DF,
+0xFFC3CFDB,
+0xFFC6D0DA,
+0xFFC8D2DC,
+0xFFCAD3DC,
+0xFFC8D2DC,
+0xFFC7D3DF,
+0xFFC6D4DF,
+0xFFC8D4E2,
+0xFFC9D7E4,
+0xFFCCD8E6,
+0xFFCBD9E6,
+0xFFCAD8E5,
+0xFFC9D7E4,
+0xFFC9D7E4,
+0xFFC6D4E1,
+0xFFC3D1DE,
+0xFFC1CFDC,
+0xFFC1CFDC,
+0xFFBFCFDC,
+0xFFC2D0DD,
+0xFFC3D1DE,
+0xFFC1CFDC,
+0xFFC3CFDD,
+0xFFC5D1DF,
+0xFFC5D3E0,
+0xFFC3D1DE,
+0xFFC0CDDD,
+0xFFBFCCDC,
+0xFFBCCCDB,
+0xFFC0CDDD,
+0xFFBFCDDA,
+0xFFBFCDDA,
+0xFFBFCBD7,
+0xFFBECAD6,
+0xFFC2CCD6,
+0xFFC3CDD7,
+0xFFC4CED8,
+0xFFC8D0DB,
+0xFFCAD4DE,
+0xFFCDD5E2,
+0xFFCBD5E1,
+0xFFC8D2DE,
+0xFFC4D0DC,
+0xFFC5CEDD,
+0xFFC2CEDC,
+0xFFC3CCDB,
+0xFFC1CDDB,
+0xFFC2CCD8,
+0xFFC2CCD8,
+0xFFC2CCD8,
+0xFFC4CEDA,
+0xFFC7CFDA,
+0xFFC9D1DC,
+0xFFC7CED8,
+0xFFCACED7,
+0xFFC9D0DA,
+0xFFD0D7E1,
+0xFFD4DCE7,
+0xFFCED8E2,
+0xFFC0CCDA,
+0xFFB8C5D5,
+0xFFB3C4D4,
+0xFFB0C3D4,
+0xFFABC0D3,
+0xFFA9BED3,
+0xFFA8BED5,
+0xFFA4BDD3,
+0xFFA0B8D0,
+0xFF9EB3C4,
+0xFFD4DDE4,
+0xFFEDF2F6,
+0xFFE6EFF6,
+0xFFA3B1BE,
+0xFFA1B5CD,
+0xFFB7BFC2,
+0xFF90754A,
+0xFF6F3704,
+0xFF5E1000,
+0xFF50100E,
+0xFFD3C9D4,
+0xFFB7C8DA,
+0xFFB9CADC,
+0xFFBFD0E0,
+0xFFC9D7E4,
+0xFFC8D4E2,
+0xFFBECADA,
+0xFFB3BCCD,
+0xFFB5BECF,
+0xFFACB3C5,
+0xFF9CA3B5,
+0xFF9097A9,
+0xFF9398AB,
+0xFFA9B0C2,
+0xFF9AA1B3,
+0xFF9CA4B7,
+0xFFA6B1C3,
+0xFF9AA7BA,
+0xFFABBACD,
+0xFFA1B2C6,
+0xFFA7B9CD,
+0xFF9FB4C7,
+0xFFA0B6CD,
+0xFFA0B6CE,
+0xFFA1B6D1,
+0xFF9DB5CF,
+0xFF98B2CD,
+0xFF95AFCA,
+0xFF96B0CB,
+0xFF99B3CE,
+0xFF94AEC7,
+0xFF95ADC5,
+0xFF95ABC2,
+0xFF93A8BD,
+0xFF9AACC0,
+0xFFA7B8CA,
+0xFFB2C1D4,
+0xFFB7C4D4,
+0xFFC3CFDD,
+0xFFC9D5E1,
+0xFFD3DDE9,
+0xFFD5E1ED,
+0xFFD3DFED,
+0xFFD0DCEA,
+0xFFD1DDED,
+0xFFD3DFEF,
+0xFFC4D1E2,
+0xFFBDCADB,
+0xFFB9C9D9,
+0xFFBFCFDF,
+0xFFC0D0E0,
+0xFFBACADA,
+0xFFB5C5D5,
+0xFFB6C6D5,
+0xFFB8C6D3,
+0xFFC3D1DC,
+0xFFCEDCE9,
+0xFFCFDDEA,
+0xFFCCDCEB,
+0xFFCCDCEB,
+0xFFC0D0E0,
+0xFFAABBCB,
+0xFF9BACBE,
+0xFF9AACC0,
+0xFF98ADC2,
+0xFF97ACC1,
+0xFF92A8BF,
+0xFF8BA1B9,
+0xFF879DB5,
+0xFF869CB4,
+0xFF889AB2,
+0xFF90A0B9,
+0xFF899BB3,
+0xFF899AB4,
+0xFF92A6BF,
+0xFF8EA2BB,
+0xFF8196B1,
+0xFF8499B4,
+0xFF869EBA,
+0xFF879EBD,
+0xFF88A1BF,
+0xFF8DA6C5,
+0xFF8FAAC8,
+0xFF89A3C4,
+0xFF7F99BA,
+0xFF7793B8,
+0xFF7895BD,
+0xFF7292BB,
+0xFF708DB5,
+0xFF708CB1,
+0xFF7387A8,
+0xFF889CB5,
+0xFF95A7B5,
+0xFF7D93A0,
+0xFF7D99B1,
+0xFF809FBE,
+0xFF7C9ABC,
+0xFF7593B7,
+0xFF7992BA,
+0xFF7A94B9,
+0xFF7390B0,
+0xFF6F8EAB,
+0xFF93A7C2,
+0xFF9BB0CB,
+0xFF879DB5,
+0xFF021830,
+0xFFA4B9D4,
+0xFF91A6C1,
+0xFF90A8C4,
+0xFF879FBB,
+0xFF849DBB,
+0xFF7F98B6,
+0xFF839EBB,
+0xFF86A1BE,
+0xFF809AB5,
+0xFF809AB5,
+0xFF87A1BC,
+0xFF849EB9,
+0xFF8BA5C0,
+0xFF8CA6C1,
+0xFF8EA6C2,
+0xFF8EA3BE,
+0xFF97ABC3,
+0xFFA1B2C4,
+0xFF7C8A95,
+0xFF526063,
+0xFF4E5A56,
+0xFF545F57,
+0xFF353F36,
+0xFF3B453C,
+0xFF333D35,
+0xFF2F3A36,
+0xFF454F50,
+0xFFABB6BC,
+0xFFABBBCA,
+0xFFACBED2,
+0xFFB3C5D9,
+0xFFB5C7DB,
+0xFFB1C2D6,
+0xFFAFC0D4,
+0xFFAFC0D2,
+0xFFABBCCE,
+0xFFA9BACA,
+0xFFA6B8C6,
+0xFFACBECC,
+0xFFADBFCD,
+0xFFAFC1CF,
+0xFFB6C8D6,
+0xFFB9CBD9,
+0xFFC0D0DF,
+0xFFC1CFDA,
+0xFFC5D1DD,
+0xFFC3CDD9,
+0xFFBEC8D4,
+0xFFC0CAD6,
+0xFFC6D0DC,
+0xFFC5D1DD,
+0xFFC7D1DD,
+0xFFC5CFDB,
+0xFFC5CFDB,
+0xFFC5CEDD,
+0xFFC3CFDF,
+0xFFBFCFDE,
+0xFFBCCDDD,
+0xFFB9CADA,
+0xFFB6C7D7,
+0xFFBBCEDF,
+0xFFBCCFE0,
+0xFFBACFE0,
+0xFFB7CCDD,
+0xFFB2C8D6,
+0xFFABC1CF,
+0xFFA5B8C9,
+0xFF9FB2C3,
+0xFF9FB4C7,
+0xFF9EB5C7,
+0xFF9FB5CA,
+0xFF9FB8CC,
+0xFFA0B9CD,
+0xFFA1BACE,
+0xFFA3B9D0,
+0xFFA3B8CB,
+0xFFA4BAC7,
+0xFFA5BBC8,
+0xFFA9BBCF,
+0xFFBECDE4,
+0xFF222E48,
+0xFF202A43,
+0xFF242B3E,
+0xFF131929,
+0xFF1B1E2D,
+0xFF1E202D,
+0xFF1E1F31,
+0xFF25283B,
+0xFF26293C,
+0xFF1F2437,
+0xFF222838,
+0xFF222838,
+0xFF202334,
+0xFF1E1F31,
+0xFF171628,
+0xFF0F0E1E,
+0xFF0F111E,
+0xFF151723,
+0xFF12171D,
+0xFF0C1117,
+0xFF0E1118,
+0xFF0A0D14,
+0xFF040B15,
+0xFF1E2A36,
+0xFFBECEDD,
+0xFFAEBFCF,
+0xFFBBCEDF,
+0xFFB8CBDC,
+0xFFBBCCDC,
+0xFFBFD0E0,
+0xFFBFCFDE,
+0xFFBCCCDB,
+0xFFC1CFDC,
+0xFFC5D3DE,
+0xFFC7D0DF,
+0xFFC4CEDA,
+0xFFC7D1DB,
+0xFFC6D0DA,
+0xFFC8D2DC,
+0xFFCBD5DF,
+0xFFCAD4DD,
+0xFFC1CED7,
+0xFFBBC8D1,
+0xFFB8C6D1,
+0xFFB3C3D0,
+0xFFB2C4D2,
+0xFFB1C2D2,
+0xFFB2C3D3,
+0xFFB4C5D5,
+0xFFB4C5D5,
+0xFFB6C7D7,
+0xFFBCCEDC,
+0xFFBDCDDC,
+0xFFBECEDD,
+0xFFBFCCDC,
+0xFFBECCD9,
+0xFFC1CDDB,
+0xFFC8D2DE,
+0xFFCAD4E0,
+0xFFCAD4E0,
+0xFFBECBDB,
+0xFFBAC7D7,
+0xFFB4C4D3,
+0xFFB1C1D0,
+0xFFB0C0CF,
+0xFFB0C0CF,
+0xFFB0C1D1,
+0xFFB1C2D2,
+0xFFB2C3D3,
+0xFFB1C2D2,
+0xFFB2C4D2,
+0xFFB3C5D3,
+0xFFB5C5D4,
+0xFFB4C6D2,
+0xFFB5C7D5,
+0xFFB6C8D6,
+0xFFB9CBD9,
+0xFFB6C8D6,
+0xFFB5C5D4,
+0xFFB4C5D5,
+0xFFB2C3D3,
+0xFFAFC0D0,
+0xFFB0C1D1,
+0xFFB4C5D5,
+0xFFB6C7D7,
+0xFFB8C9D9,
+0xFFB8CAD8,
+0xFFBBCBDA,
+0xFFBFCFDE,
+0xFFBECEDD,
+0xFFBAC8D5,
+0xFFB7C5D2,
+0xFFB3C1CE,
+0xFFB6C2D0,
+0xFFB7C3D3,
+0xFFB5C1D1,
+0xFFB4C0D0,
+0xFFB6C2D2,
+0xFFB9C5D5,
+0xFFBCC8D8,
+0xFFBECADA,
+0xFFC0CCDA,
+0xFFC3CCDB,
+0xFFC4CDDC,
+0xFFC4CDDC,
+0xFFC8D2DE,
+0xFFCDD7E3,
+0xFFD2DCE6,
+0xFFD3DAE4,
+0xFFD5DCE6,
+0xFFD7DEE8,
+0xFFDAE2ED,
+0xFFDAE4EE,
+0xFFD0DCE8,
+0xFFC1CFDC,
+0xFFB7C7D7,
+0xFFB1C2D4,
+0xFFAABFD2,
+0xFFA3B9CE,
+0xFF9DB6CC,
+0xFF9BB5CC,
+0xFF9AB4CD,
+0xFF95B1C9,
+0xFF94AABF,
+0xFFD3DDE6,
+0xFFECF4F7,
+0xFFE7F2F8,
+0xFFA0B0BD,
+0xFF8EA4BB,
+0xFFA8B1B0,
+0xFFB19862,
+0xFFD49D5C,
+0xFF711E00,
+0xFF550C06,
+0xFF8D7582,
+0xFFB1B2C6,
+0xFFAEAFC3,
+0xFFB7B8CA,
+0xFFBCB9CA,
+0xFFBAB9C9,
+0xFFB4BBCD,
+0xFFB3BED2,
+0xFFA6B1C5,
+0xFFADB5CA,
+0xFF9CA3B6,
+0xFFA0A7B9,
+0xFFA1A9BC,
+0xFFAEB7C8,
+0xFF969FAE,
+0xFF95A1B1,
+0xFF909BAF,
+0xFF95A1B7,
+0xFF9CABC0,
+0xFFA4B5C9,
+0xFF9EB0C6,
+0xFF99AEC3,
+0xFF98ADC2,
+0xFF9BB0C5,
+0xFF9CB2C7,
+0xFF9CB2C7,
+0xFF99AFC4,
+0xFF98AEC3,
+0xFF9BB4C8,
+0xFFA3B9CE,
+0xFFB3CADC,
+0xFFBACDDE,
+0xFFBDCEDE,
+0xFFBFCFDE,
+0xFFC8D8E7,
+0xFFD7E4F4,
+0xFFDEEAF6,
+0xFFDFE8F1,
+0xFFDBE2EA,
+0xFFDFE3EC,
+0xFFE4E9EF,
+0xFFE8EFF7,
+0xFFE8EFF7,
+0xFFDEE5EF,
+0xFFD1D7E3,
+0xFFC8D0DB,
+0xFFC8D0DD,
+0xFFCBD5E1,
+0xFFCED8E4,
+0xFFCCD9E2,
+0xFFCDDAE3,
+0xFFCDDAE3,
+0xFFCCD8E4,
+0xFFCAD7E0,
+0xFFCDD7E1,
+0xFFD4DEE7,
+0xFFD4DEE8,
+0xFFD0DCE8,
+0xFFD2DEEA,
+0xFFCEDCE9,
+0xFFBECBDB,
+0xFFADBDCC,
+0xFFACBCCC,
+0xFFB0C1D1,
+0xFFB9CADA,
+0xFFBACBDD,
+0xFFAFC0D2,
+0xFFA6B7C9,
+0xFFADBED0,
+0xFFBCCCDC,
+0xFFBCC9DA,
+0xFFBFCBDB,
+0xFFD4DCEF,
+0xFFDEE6F9,
+0xFFDCE4F7,
+0xFFD3DEF0,
+0xFFCFDCEF,
+0xFFBECDE0,
+0xFFBECFE3,
+0xFFBECFE3,
+0xFFBCCCE3,
+0xFFBBCDE5,
+0xFFBBCDE5,
+0xFFABBFD8,
+0xFF95AAC5,
+0xFF879FBB,
+0xFF87A1C4,
+0xFF87A1C6,
+0xFF86A0C3,
+0xFF8FA8C7,
+0xFF9FB3CE,
+0xFFA5B6CA,
+0xFF9DAEB8,
+0xFF9EB0BA,
+0xFF97B0C4,
+0xFF9AB6CE,
+0xFF99B4CF,
+0xFF9DB8D5,
+0xFFA9C2E1,
+0xFFA9C0DF,
+0xFFA5BFD8,
+0xFFAAC4DB,
+0xFFACBBCE,
+0xFFB1C2D4,
+0xFFB7C8DC,
+0xFF728397,
+0xFFB4C4DB,
+0xFFA0B0C7,
+0xFFB1C3DB,
+0xFFA9BBD1,
+0xFFADBFD5,
+0xFFA7B9CF,
+0xFFA6BBCE,
+0xFFABC0D3,
+0xFF98ADC0,
+0xFFA7BCCF,
+0xFFA5BACD,
+0xFFAABFD4,
+0xFFA4BCD4,
+0xFF9DB5CD,
+0xFF9DB3CA,
+0xFF9EB0C4,
+0xFFACBCCB,
+0xFFBCC9D2,
+0xFF798287,
+0xFF3D4343,
+0xFF535854,
+0xFF6F746D,
+0xFF43463F,
+0xFF3B3E37,
+0xFF454742,
+0xFF2D322E,
+0xFF393D3C,
+0xFF5B6064,
+0xFF919AA3,
+0xFFCBD4E3,
+0xFFC6CFDE,
+0xFFCBD4E5,
+0xFFC1CCDE,
+0xFFC1CCDE,
+0xFFB9C5D5,
+0xFFBFCBD9,
+0xFFBECAD6,
+0xFFC0CDD6,
+0xFFBBC8D1,
+0xFFC1CDD9,
+0xFFC9D5E3,
+0xFFC7D3E3,
+0xFFC4CFE1,
+0xFFCBD7E7,
+0xFFC5D1DD,
+0xFFC7D1DB,
+0xFFCCD4E1,
+0xFFC2CAD7,
+0xFFBFC9D5,
+0xFFC4D0DC,
+0xFFC4D2DB,
+0xFFCFDCE5,
+0xFFD1D9E4,
+0xFFCDD5E0,
+0xFFCBD5E1,
+0xFFC6D2DE,
+0xFFC6D6E3,
+0xFFBDCFDD,
+0xFFC5D7E5,
+0xFFC1D1E0,
+0xFFC0CDDD,
+0xFFCAD8E5,
+0xFFCADBE5,
+0xFFC2D4DE,
+0xFFC7D9E3,
+0xFFBFD1DB,
+0xFFB9C9D6,
+0xFFABBBCB,
+0xFFA3B6C7,
+0xFFA0B5C8,
+0xFF97B0C4,
+0xFF94AFC4,
+0xFF97B0C6,
+0xFF9CB2C9,
+0xFFA5B7CD,
+0xFFA2B3C7,
+0xFFA1B2C4,
+0xFF9BAEBF,
+0xFFA8B9CD,
+0xFFBECDE4,
+0xFF5D6983,
+0xFF17213A,
+0xFF181F32,
+0xFF191F2F,
+0xFF0E121E,
+0xFF242633,
+0xFF262837,
+0xFF1F2130,
+0xFF262835,
+0xFF232733,
+0xFF1B1E2D,
+0xFF0A1020,
+0xFF030615,
+0xFF1F2231,
+0xFF06071B,
+0xFF1F1D32,
+0xFF2A293B,
+0xFF1F1E2C,
+0xFF171721,
+0xFF17181D,
+0xFF12151A,
+0xFF0F141A,
+0xFF020B14,
+0xFF091523,
+0xFFCDDAED,
+0xFFB1C0D5,
+0xFFB5C6DA,
+0xFFB9CBE1,
+0xFFB9CBE1,
+0xFFB0C2D8,
+0xFFB8CADE,
+0xFFB9CCDD,
+0xFFBACCD8,
+0xFFBDCFDB,
+0xFFC0CDDE,
+0xFFBCC9DA,
+0xFFBFCBD9,
+0xFFBECAD6,
+0xFFC2D0DD,
+0xFFBAC8D3,
+0xFFB8C9D1,
+0xFFB5C7D1,
+0xFFB1C4D2,
+0xFFAFC2D1,
+0xFFADC3D1,
+0xFFB5CBD9,
+0xFFB8CADE,
+0xFFB8CAE0,
+0xFFB3C5DB,
+0xFFBACCE0,
+0xFFB8CBDC,
+0xFFBDD0DF,
+0xFFBACDDB,
+0xFFBACDDB,
+0xFFB8C9D9,
+0xFFC1D2E2,
+0xFFBDCDDD,
+0xFFC5D2E3,
+0xFFC3CFDF,
+0xFFC4D0E0,
+0xFFBFCCDF,
+0xFFB9C8DB,
+0xFFB7C8DA,
+0xFFA8BBCA,
+0xFFACBFD0,
+0xFFA7BCCF,
+0xFF9FB4C9,
+0xFFA1B6CB,
+0xFFA5B7CF,
+0xFFA4B6CC,
+0xFFA5B7CB,
+0xFFACBFD0,
+0xFFB2C3D3,
+0xFFB0C3D1,
+0xFFAEC1D0,
+0xFFAEC4D2,
+0xFFABC1CF,
+0xFFAAC1CF,
+0xFFAAC0CE,
+0xFFABC2D2,
+0xFFA2B9C9,
+0xFFA5BCCC,
+0xFFA3BACA,
+0xFFA2B9CB,
+0xFFA2B9CB,
+0xFFA5BCCE,
+0xFFA7BED0,
+0xFFA4B9CC,
+0xFFABC0D3,
+0xFFAFC4D7,
+0xFFACC1D4,
+0xFFB0C5D8,
+0xFFAFC2D3,
+0xFFB3C4D6,
+0xFFB7C6D9,
+0xFFAFBED1,
+0xFFB8C5D6,
+0xFFBDC8DA,
+0xFFC1CDDD,
+0xFFC0C9D8,
+0xFFC5CEDD,
+0xFFD0DAE6,
+0xFFD1D9E6,
+0xFFD1DBE7,
+0xFFC8D2DE,
+0xFFC4D0DC,
+0xFFB9C5D1,
+0xFFBFCCD5,
+0xFFC3CDD7,
+0xFFC8D0DB,
+0xFFD0D8E3,
+0xFFCFD7E2,
+0xFFD5DFE9,
+0xFFD5E1ED,
+0xFFCAD7E7,
+0xFFB9CADC,
+0xFFB0C2D6,
+0xFFA5B9D1,
+0xFFA8BED5,
+0xFF9DB5CD,
+0xFF9CB6CD,
+0xFF94AEC7,
+0xFF96B0CB,
+0xFF92A6BE,
+0xFFD3D9E5,
+0xFFF1F4F9,
+0xFFE8F3F7,
+0xFF9EB1B8,
+0xFF9CB1C4,
+0xFFB2BCB4,
+0xFFC4B16F,
+0xFFD4A557,
+0xFF752600,
+0xFF540400,
+0xFF723E4A,
+0xFFE5BFD4,
+0xFFDFBACC,
+0xFFC39EB0,
+0xFFBD93A7,
+0xFFDEC1D7,
+0xFFC5C3D8,
+0xFFB0BCD2,
+0xFFA0ACC4,
+0xFFAAB5CB,
+0xFF99A2B3,
+0xFF919AA9,
+0xFFB7C3D3,
+0xFFB9C7D4,
+0xFF9CABB2,
+0xFFA1AFB8,
+0xFF98A3B5,
+0xFFA2ADC3,
+0xFFA6B2C8,
+0xFFACBBD2,
+0xFFA0B2CA,
+0xFF9CAEC4,
+0xFFA5B6C8,
+0xFFAFBFCE,
+0xFFB2C4D2,
+0xFFB5C7D3,
+0xFFBACBD3,
+0xFFC3D1DA,
+0xFFBECEDB,
+0xFFCBDBE8,
+0xFFD8E4F0,
+0xFFDAE4ED,
+0xFFE5E9F2,
+0xFFE6EAF5,
+0xFFDCE4F1,
+0xFFD6DEEB,
+0xFFDBDFE8,
+0xFFDCDFE4,
+0xFFDEDEE6,
+0xFFE3E3EB,
+0xFFE4E7EC,
+0xFFE5E8ED,
+0xFFE6E9F0,
+0xFFE4E8F1,
+0xFFDCE0EC,
+0xFFD2D8E6,
+0xFFC6CDDD,
+0xFFC4CEDA,
+0xFFC4CED8,
+0xFFC7D1DA,
+0xFFC8D5DD,
+0xFFC9D6DE,
+0xFFC7D5DE,
+0xFFC6D3DC,
+0xFFCCD4DF,
+0xFFCCD3DD,
+0xFFCFD7E2,
+0xFFD1DBE7,
+0xFFCAD6E6,
+0xFFC1CEDF,
+0xFFBCC9DC,
+0xFFBAC7DA,
+0xFFBBC8D9,
+0xFFC9D6E6,
+0xFFD1DDEB,
+0xFFD7E1ED,
+0xFFE0E9F2,
+0xFFE5ECF4,
+0xFFE5EAEE,
+0xFFE5EAEE,
+0xFFE2E9EF,
+0xFFD1D8E0,
+0xFFE5E8F1,
+0xFFE9E7F2,
+0xFFE8E7EF,
+0xFFE6E6EE,
+0xFFE1E4ED,
+0xFFD4DBE3,
+0xFFD3DCE5,
+0xFFD0DAE4,
+0xFFCFD9E5,
+0xFFCDD6E5,
+0xFFC5D0E2,
+0xFFBFCCDD,
+0xFFB9CADC,
+0xFFB6C8DE,
+0xFFB6C7E1,
+0xFFAEC1DF,
+0xFFACC0DB,
+0xFFB1C5DE,
+0xFFACBDD1,
+0xFFABB8C8,
+0xFFA3ACB3,
+0xFFA7B0B7,
+0xFFB2C4D2,
+0xFFA6BBCE,
+0xFFAEC3D6,
+0xFFB8CAE0,
+0xFFB9C9E0,
+0xFFB2C3D7,
+0xFFBCCBDE,
+0xFFC6D3E4,
+0xFF484F59,
+0xFF59626B,
+0xFF575F6A,
+0xFF808893,
+0xFFC0C8D5,
+0xFFA0AAB6,
+0xFF5C6373,
+0xFF4A5460,
+0xFF59636D,
+0xFFACB6BF,
+0xFFB4BEC7,
+0xFF8E9BA3,
+0xFF87919A,
+0xFF8B98A0,
+0xFFB2BCC5,
+0xFFD1DFEA,
+0xFFC5D6E6,
+0xFFBBCCDC,
+0xFFC4D4E1,
+0xFFCAD8E1,
+0xFFD1DCE2,
+0xFFD5DDDF,
+0xFF6F7372,
+0xFF41433E,
+0xFF595A52,
+0xFF54544C,
+0xFF303028,
+0xFF3E3E36,
+0xFF23241E,
+0xFF343530,
+0xFF595B58,
+0xFF252628,
+0xFF5D6065,
+0xFFD9DDE6,
+0xFFCED2DB,
+0xFFD5D9E4,
+0xFFCFD5E1,
+0xFFD2D8E4,
+0xFFD1D7E3,
+0xFFCDD6DF,
+0xFFCFD8E1,
+0xFFC8D1D8,
+0xFFC9D2D9,
+0xFFCAD4DD,
+0xFFC3CDD7,
+0xFFC7D1DD,
+0xFFC9D2E1,
+0xFFCBD4E3,
+0xFFC9D6DF,
+0xFFCBD5DF,
+0xFFD0D8E5,
+0xFFCDD7E3,
+0xFFC6D2DE,
+0xFFC0CED9,
+0xFFC6D4DD,
+0xFFC1CFD8,
+0xFFC7D1DB,
+0xFFCAD2DD,
+0xFFC4CED8,
+0xFFBDCAD3,
+0xFFBDCED8,
+0xFFBACCD8,
+0xFFBFCFDE,
+0xFFB8C5D5,
+0xFFC2CBDA,
+0xFFC9D3DF,
+0xFFC3D0D9,
+0xFFC5D2DA,
+0xFFC1CED6,
+0xFFC3D0D8,
+0xFFC7D1DD,
+0xFFC2CEDC,
+0xFFBDCDDD,
+0xFFB2C5D6,
+0xFFB3CADA,
+0xFFACC6D7,
+0xFFAEC5D7,
+0xFFBCCEE2,
+0xFFBCCBDE,
+0xFFBFCCDF,
+0xFFC1D1E1,
+0xFFB8C9D9,
+0xFFB8C7DA,
+0xFFC5D4E9,
+0xFF8490A8,
+0xFF222C45,
+0xFF1C2336,
+0xFF0D1321,
+0xFF080C18,
+0xFF131521,
+0xFF1A1927,
+0xFF232230,
+0xFF181B24,
+0xFF0F121B,
+0xFF060918,
+0xFF010413,
+0xFF282E3C,
+0xFF111725,
+0xFF222337,
+0xFF25263A,
+0xFF1F1C31,
+0xFF191627,
+0xFF15141C,
+0xFF0E0F13,
+0xFF131418,
+0xFF050A0E,
+0xFF09121B,
+0xFF091221,
+0xFFD1DCEE,
+0xFFBCC9DC,
+0xFFB9C6D9,
+0xFFB0BFD2,
+0xFFADBFD3,
+0xFFABBDD3,
+0xFFAEC0D4,
+0xFFA6B9CA,
+0xFFAEC2CD,
+0xFFB0C2CE,
+0xFFB5C5D5,
+0xFFBBCBDB,
+0xFFBECCD7,
+0xFFBFCDD8,
+0xFFBBC9D6,
+0xFFC4D4E3,
+0xFFBED0DA,
+0xFFB3C7D2,
+0xFFB3C9D7,
+0xFFB2C8D6,
+0xFFB7CBD6,
+0xFFB5C9D4,
+0xFFB4C5D5,
+0xFFB2C3D5,
+0xFFB1C2D6,
+0xFFB7C8DA,
+0xFFB5C8D7,
+0xFFB7CAD8,
+0xFFB8CEDB,
+0xFFB4CAD7,
+0xFFB5CADB,
+0xFFB0C5D8,
+0xFFBACCE2,
+0xFFB3C4D8,
+0xFFB1C2D6,
+0xFFB3C2D5,
+0xFFB6C5DA,
+0xFFB1C0D3,
+0xFFAFC0D2,
+0xFFB2C5D6,
+0xFFAABFD0,
+0xFFAAC1D1,
+0xFFB4CBDD,
+0xFFB9D0E2,
+0xFFBCD1E6,
+0xFFBACFE2,
+0xFFB2C4D8,
+0xFFB3C6D7,
+0xFFB6C9DA,
+0xFFB8CBDA,
+0xFFB9CFDD,
+0xFFBBD1DF,
+0xFFBBD2E0,
+0xFFBAD1DF,
+0xFFBBD2E2,
+0xFFBBD2E2,
+0xFFB8CFDF,
+0xFFB8CFDF,
+0xFFBDD2E3,
+0xFFB9D0E0,
+0xFFB1C6D9,
+0xFFABC2D4,
+0xFFA7BCCF,
+0xFFA7BED0,
+0xFFA6BBD0,
+0xFFA8BED3,
+0xFFAEC3D8,
+0xFFB9CEE1,
+0xFFBDD2E3,
+0xFFBED1E2,
+0xFFBCCDDF,
+0xFFC1D1E1,
+0xFFC7D4E4,
+0xFFC9D5E3,
+0xFFCAD4E0,
+0xFFCBD3DE,
+0xFFD3DBE6,
+0xFFD7DFEA,
+0xFFD5DDE8,
+0xFFD5DDE8,
+0xFFCFD9E3,
+0xFFC7D4DD,
+0xFFC7D4DD,
+0xFFC4D2DB,
+0xFFC5D1DD,
+0xFFC2CCD8,
+0xFFC0CAD6,
+0xFFC0CAD4,
+0xFFC4CED8,
+0xFFC0CDD6,
+0xFFBECCD9,
+0xFFC1D1E0,
+0xFFBECFE1,
+0xFFBFD1E5,
+0xFFB7CCDF,
+0xFFAFC4D9,
+0xFFB1C6DB,
+0xFFB0C5DA,
+0xFFA3B7CF,
+0xFFA1B0C3,
+0xFFD7DBE7,
+0xFFECEFF6,
+0xFFE8F3F7,
+0xFFA4B5BD,
+0xFFB5C6D8,
+0xFFC4CAC6,
+0xFFD3C78D,
+0xFFC8A65E,
+0xFFC6895A,
+0xFF96553F,
+0xFF57242B,
+0xFFB88DA0,
+0xFFA67C8A,
+0xFF774252,
+0xFF823D4F,
+0xFFC58C9F,
+0xFFDBC8DB,
+0xFFC0C3D6,
+0xFFB1B8CB,
+0xFFA9B0C3,
+0xFF9AA1B3,
+0xFF8E95A5,
+0xFFA7B3C3,
+0xFFB1BFCC,
+0xFF8B9AA1,
+0xFF95A2AB,
+0xFF9CA5B6,
+0xFFB1B7CD,
+0xFFB9C4D8,
+0xFFBBC8DB,
+0xFFAAB9CE,
+0xFFBFCEE3,
+0xFFCEDBEB,
+0xFFDCE8F4,
+0xFFDDEBF6,
+0xFFD2E1E8,
+0xFFD0DBE1,
+0xFFD4DDE4,
+0xFFD6E0EA,
+0xFFD5DFE9,
+0xFFD2D9E3,
+0xFFD5D8DF,
+0xFFDFE0E5,
+0xFFDBDBE3,
+0xFFD4DAE6,
+0xFFD2DAE5,
+0xFFD8DDE3,
+0xFFD7DBDE,
+0xFFDADBE0,
+0xFFDDDEE3,
+0xFFDDE1E4,
+0xFFDDE1E4,
+0xFFDEE1E6,
+0xFFE0E4ED,
+0xFFDFE3EE,
+0xFFD9DFED,
+0xFFD5DBE9,
+0xFFCFD7E4,
+0xFFCAD2DD,
+0xFFC7D1DA,
+0xFFCAD4DD,
+0xFFCAD7DF,
+0xFFCAD6E2,
+0xFFC9D5E1,
+0xFFC7D1DD,
+0xFFC9D3DF,
+0xFFCAD6E4,
+0xFFC3D0E0,
+0xFFB2C2D2,
+0xFFA8B7CA,
+0xFFA9B8CD,
+0xFFADBCD1,
+0xFFB8C7DA,
+0xFFBDCADB,
+0xFFC7D3E1,
+0xFFD4DCE7,
+0xFFDFE4EA,
+0xFFE4E8EB,
+0xFFE9E9E9,
+0xFFE7E9E8,
+0xFFE6EBEE,
+0xFFD4D9DC,
+0xFFE6E5EB,
+0xFFE7E5EA,
+0xFFEBE6EC,
+0xFFE8E6EB,
+0xFFE4E5EA,
+0xFFDBE0E6,
+0xFFD5DCE2,
+0xFFCED7DE,
+0xFFCCD2DE,
+0xFFCAD2DF,
+0xFFC4CBDD,
+0xFFBCC7D9,
+0xFFB6C6D6,
+0xFFB3C4D6,
+0xFFB1C1DA,
+0xFFAEC0D8,
+0xFFAEC2DB,
+0xFFA4B9CE,
+0xFFA6B9CA,
+0xFFACBAC5,
+0xFF9CA3A9,
+0xFFA6ADB3,
+0xFFADBDCA,
+0xFFACBFD0,
+0xFFB9CADC,
+0xFFBACBDD,
+0xFFADBED0,
+0xFFAABACA,
+0xFFBAC6D6,
+0xFFC2CEDC,
+0xFF302B27,
+0xFF2A2623,
+0xFF2E2A29,
+0xFF312D2C,
+0xFF6E6A69,
+0xFF2D2C2A,
+0xFF322E2F,
+0xFF3C3B39,
+0xFF353432,
+0xFF2D2C28,
+0xFF2E2D29,
+0xFF1C1D17,
+0xFF23221E,
+0xFF12130E,
+0xFF262523,
+0xFF686A69,
+0xFF969EA1,
+0xFFB0BABC,
+0xFFB5BDBF,
+0xFF858B8B,
+0xFF717672,
+0xFF6E716A,
+0xFF5F5F55,
+0xFF5A5A4E,
+0xFF3E3F31,
+0xFF4B4C3E,
+0xFF404034,
+0xFF313125,
+0xFF2C2E23,
+0xFF41423A,
+0xFF3C3F38,
+0xFF383A37,
+0xFF6D6D6F,
+0xFFE5E5E7,
+0xFFCECED0,
+0xFFBFC0C4,
+0xFFC8CCCF,
+0xFFBABDC2,
+0xFFC3C8CC,
+0xFFCFD7DA,
+0xFFB5BDC0,
+0xFFCFD9DB,
+0xFFD2DBE0,
+0xFFC2CBD0,
+0xFFCCD7DB,
+0xFFCDD8DC,
+0xFFCAD5DB,
+0xFFCAD5DB,
+0xFFC5CFD9,
+0xFFC9D3DF,
+0xFFC6D2DE,
+0xFFC9D5E1,
+0xFFD2E0ED,
+0xFFCFDDEA,
+0xFFCDDBE8,
+0xFFCBD7E5,
+0xFFCCD8E4,
+0xFFC5CFDB,
+0xFFC9D3DD,
+0xFFC7D1DB,
+0xFFC1CDD9,
+0xFFBFCDDA,
+0xFFB9C6D6,
+0xFFBFCBDB,
+0xFF9FA4B7,
+0xFFB0B3C4,
+0xFFCDD3DF,
+0xFFCFD6E0,
+0xFFCFD3DE,
+0xFFCFD3DE,
+0xFFBEC2CE,
+0xFFD4DAE8,
+0xFFCCD6E2,
+0xFFB7C5D0,
+0xFF7B8D97,
+0xFF97A9B3,
+0xFFC2D4DE,
+0xFFC6D7E1,
+0xFFD3DFED,
+0xFFD0DAE6,
+0xFFCBD9E4,
+0xFFD2E3ED,
+0xFFC2D0DB,
+0xFFCAD8E5,
+0xFFA2AFC2,
+0xFF1B263A,
+0xFF252C3C,
+0xFF0F1521,
+0xFF111520,
+0xFF090B17,
+0xFF080814,
+0xFF2F2F3B,
+0xFF040710,
+0xFF02050E,
+0xFF070A19,
+0xFF2A303E,
+0xFF1C2230,
+0xFF2B313F,
+0xFF252638,
+0xFF1A1B2D,
+0xFF201D2E,
+0xFF171522,
+0xFF0E0D15,
+0xFF0F1014,
+0xFF07080C,
+0xFF0C1115,
+0xFF00070F,
+0xFF0E1621,
+0xFFD9E0F0,
+0xFFBAC3D2,
+0xFFBAC4D0,
+0xFFBBC7D3,
+0xFFB4C4D1,
+0xFFB3C5D3,
+0xFFB3C4D4,
+0xFFB1C2D2,
+0xFFAEC0CA,
+0xFFB5C6D0,
+0xFFB7C7D4,
+0xFFBECCD7,
+0xFFBFCCD4,
+0xFFC3D0D8,
+0xFFC0CCDA,
+0xFFB5C2D2,
+0xFFBECEDB,
+0xFFB7C9D5,
+0xFFBCD0DB,
+0xFFCDDFE9,
+0xFFD4E3E6,
+0xFFD6E1E5,
+0xFFD6E0E9,
+0xFFD7E1EB,
+0xFFCEDAE6,
+0xFFC1CDDB,
+0xFFBDCBD6,
+0xFFB5C7D1,
+0xFFB2C6CF,
+0xFFA7BFCB,
+0xFFACC3D3,
+0xFFABC4D8,
+0xFFA3BCD2,
+0xFFA4BDD3,
+0xFFA2BBD1,
+0xFFA6BDCF,
+0xFFA7B8C8,
+0xFFACBCCB,
+0xFFB3C4D4,
+0xFFADC0CF,
+0xFFB7CDDA,
+0xFFB5CBD6,
+0xFFC4DBE3,
+0xFFC3DAE0,
+0xFFD1E5EC,
+0xFFCADEE7,
+0xFFB2C5D3,
+0xFFAEC1D0,
+0xFFB2C5D6,
+0xFFB3C6D5,
+0xFFB1C7D4,
+0xFFB1C7D2,
+0xFFB6C9D7,
+0xFFB6C8D6,
+0xFFB5C6D6,
+0xFFB4C5D5,
+0xFFB6C7D7,
+0xFFB1C2D2,
+0xFFBCCCDC,
+0xFFB8C9D9,
+0xFFBECEDE,
+0xFFBACBDB,
+0xFFB8C8D8,
+0xFFBFD0E0,
+0xFFBFCFDF,
+0xFFBDCEDE,
+0xFFBECEDE,
+0xFFBDCEDE,
+0xFFBED0DE,
+0xFFBBCBD8,
+0xFFBCCCD9,
+0xFFC1CFDA,
+0xFFBAC7D0,
+0xFFC9D4DA,
+0xFFDFE8ED,
+0xFFDFE6EC,
+0xFFD7DEE4,
+0xFFD6DDE3,
+0xFFDAE1E9,
+0xFFD0D9E0,
+0xFFCED8E1,
+0xFFC5D2DB,
+0xFFC2CFD8,
+0xFFB7C5D0,
+0xFFB7C5D2,
+0xFFBFCDD8,
+0xFFBFCBD7,
+0xFFC0CAD4,
+0xFFBEC8D1,
+0xFFC4CED7,
+0xFFC5D2DA,
+0xFFC0CDD6,
+0xFFBECAD6,
+0xFFC0CEDB,
+0xFFC5D3E0,
+0xFFCCDAE5,
+0xFFD4E2ED,
+0xFFD4E0EC,
+0xFFCCD6E2,
+0xFFD1D9E4,
+0xFFE2E4F0,
+0xFFECF0F9,
+0xFFE6EFF8,
+0xFFABB5BF,
+0xFFCCD5E6,
+0xFFD8D9DD,
+0xFFE4DABF,
+0xFFC5B385,
+0xFFA68A5A,
+0xFFFCE2BF,
+0xFFECDADA,
+0xFFBCAEBB,
+0xFFCEBDC7,
+0xFFFFDAE2,
+0xFFA04B52,
+0xFF5E0C12,
+0xFF5B323A,
+0xFFE6D6E0,
+0xFFC2BCC8,
+0xFFB7B6C6,
+0xFFA6A9BC,
+0xFFA6ADC0,
+0xFFCAD6E6,
+0xFFBAC8D5,
+0xFF8D99A7,
+0xFFABB4C3,
+0xFFBFC2D1,
+0xFFC0C3D2,
+0xFFCCD3E3,
+0xFFC5CEDD,
+0xFFD4DDEE,
+0xFFDBE4F5,
+0xFFD6DFEE,
+0xFFD4DEEA,
+0xFFD0DAE6,
+0xFFC5CFD9,
+0xFFCFD8E1,
+0xFFCFD7E2,
+0xFFE0E8F5,
+0xFFDCE4F1,
+0xFFDBDFEB,
+0xFFD8DAE6,
+0xFFD9D9E3,
+0xFFCFD3DE,
+0xFFC4D1DA,
+0xFFC9D7E0,
+0xFFC7D4DA,
+0xFFC9D3D5,
+0xFFCED6D9,
+0xFFD5DADD,
+0xFFD7DCDF,
+0xFFD5DADD,
+0xFFD1D6DA,
+0xFFCAD1D7,
+0xFFC4CBD3,
+0xFFBFC6D0,
+0xFFC0C6D2,
+0xFFBFC7D2,
+0xFFBFC7D2,
+0xFFBFC9D3,
+0xFFBFC9D3,
+0xFFBEC8D4,
+0xFFBCC5D4,
+0xFFB7C4D4,
+0xFFB4C6D4,
+0xFFB3C9D7,
+0xFFB5CBD9,
+0xFFB0C7D7,
+0xFFA5BCCE,
+0xFF9FB5CA,
+0xFF9EB4C9,
+0xFF9FB4C9,
+0xFFA2B4CA,
+0xFFA6B7C9,
+0xFFB6C3D3,
+0xFFC2CCD8,
+0xFFC8CFD9,
+0xFFD3D8DE,
+0xFFDFE2E7,
+0xFFDFE4E7,
+0xFFDBE5E7,
+0xFFC9D3D5,
+0xFFD7DAE1,
+0xFFD8D8E0,
+0xFFDCDBE3,
+0xFFD9D9E1,
+0xFFD3D7E0,
+0xFFCFD8E1,
+0xFFCBD5DF,
+0xFFC1CDD9,
+0xFFBFC8D9,
+0xFFBBC6D8,
+0xFFB4BFD3,
+0xFFAAB9CE,
+0xFFA3B5CB,
+0xFF9EB2CA,
+0xFF9DB1CA,
+0xFF9BB1C9,
+0xFF97AFC9,
+0xFF9AB3C9,
+0xFF9BB2C4,
+0xFF9EB1BF,
+0xFF9DA7B0,
+0xFF9EA8B1,
+0xFF9DB0BF,
+0xFF9FB6C8,
+0xFF9FB4C9,
+0xFFA3B8CD,
+0xFFA4B9CE,
+0xFFA1B6C9,
+0xFFADBED0,
+0xFFC7D8E8,
+0xFF3B3127,
+0xFF2C2419,
+0xFF3E342B,
+0xFF261D14,
+0xFF2E251E,
+0xFF373026,
+0xFF342B22,
+0xFF362F25,
+0xFF342D23,
+0xFF2C281C,
+0xFF2E281C,
+0xFF2C281C,
+0xFF1F1B10,
+0xFF2F2B20,
+0xFF29251C,
+0xFF221F18,
+0xFF1B1A16,
+0xFF454641,
+0xFF4F4E49,
+0xFF36362E,
+0xFF2E2B22,
+0xFF353327,
+0xFF454233,
+0xFF363324,
+0xFF322F1E,
+0xFF2D2B1C,
+0xFF403E31,
+0xFF303123,
+0xFF28281E,
+0xFF1C1C12,
+0xFF2C2D25,
+0xFF23221D,
+0xFF1D1916,
+0xFF5C5855,
+0xFF575350,
+0xFF363530,
+0xFF4F504B,
+0xFF51534E,
+0xFF414642,
+0xFF545857,
+0xFF303634,
+0xFF6B7171,
+0xFF989DA0,
+0xFF3D4343,
+0xFFDFE5E5,
+0xFFD7DDDB,
+0xFFD5DBD7,
+0xFFD5DBDB,
+0xFFD3D8DE,
+0xFFAEB5BD,
+0xFFB9C4C8,
+0xFFC5D0D4,
+0xFFACB7BD,
+0xFFA7B0B7,
+0xFFB8C1CA,
+0xFFCED7E0,
+0xFFCFD8E1,
+0xFFD5DEE5,
+0xFFCFD7DA,
+0xFFCBD0D4,
+0xFFD4D7DC,
+0xFFDEE3E9,
+0xFFB0B7BF,
+0xFFBEC5CD,
+0xFFB1B4BD,
+0xFFBCBCC4,
+0xFFD2D1D6,
+0xFFA9A9AB,
+0xFF99979A,
+0xFF747275,
+0xFF5F5E64,
+0xFF8C8C94,
+0xFF767B81,
+0xFF4E575C,
+0xFF535E62,
+0xFF5D6B6E,
+0xFF616C72,
+0xFF9FA9B2,
+0xFFA1A7B3,
+0xFFCAD2DD,
+0xFFCCD6E0,
+0xFFCAD7DF,
+0xFFCDDAE2,
+0xFFCFDBE7,
+0xFFB6C1D5,
+0xFF151D32,
+0xFF232A3A,
+0xFF323844,
+0xFF1B1D2A,
+0xFF0D0F1C,
+0xFF11111D,
+0xFF0E101C,
+0xFF00010A,
+0xFF1A1E29,
+0xFF333947,
+0xFF2A3040,
+0xFF272D3B,
+0xFF1A202E,
+0xFF1B1D2C,
+0xFF181A29,
+0xFF100F1D,
+0xFF16141F,
+0xFF0D0C12,
+0xFF0C0D11,
+0xFF090A0C,
+0xFF0B0F12,
+0xFF060B11,
+0xFF1B1F2A,
+0xFFE7EEF8,
+0xFFE2E9F3,
+0xFFE0E7ED,
+0xFFE0E7ED,
+0xFFDBE6EC,
+0xFFD0DDE5,
+0xFFCFDBE7,
+0xFFD2DEEC,
+0xFFD3E0E9,
+0xFFDAE7EF,
+0xFFDFECF5,
+0xFFE0EAF3,
+0xFFDBE6EA,
+0xFFE0EBEF,
+0xFFD4DCE9,
+0xFFD3DCED,
+0xFFD6E2F0,
+0xFFCFDDE8,
+0xFFD2E3ED,
+0xFFD9E8EF,
+0xFFDAE4E6,
+0xFFD5DDDF,
+0xFFDDE2E8,
+0xFFD8DCE7,
+0xFFD4DAE6,
+0xFFD9E1EC,
+0xFFD4DEE7,
+0xFFD4E1E9,
+0xFFC9DAE2,
+0xFFC2D6DF,
+0xFFB7CDDB,
+0xFFA9C0D2,
+0xFFA6BCD1,
+0xFFA5BED2,
+0xFFA7C1D2,
+0xFFBED4E2,
+0xFFCCDCE9,
+0xFFCCDAE7,
+0xFFC7D5E2,
+0xFFCBDBE8,
+0xFFD3E5F1,
+0xFFD6E8F2,
+0xFFCCDFE5,
+0xFFD1E4EA,
+0xFFCDDEE5,
+0xFFD4E5ED,
+0xFFD2E2EF,
+0xFFC1D3E1,
+0xFFBECFDF,
+0xFFB7CAD8,
+0xFFC3D7E2,
+0xFFC1D5DE,
+0xFFC0D2DE,
+0xFFC3D3E0,
+0xFFC5D5E2,
+0xFFCAD8E5,
+0xFFCFDDEA,
+0xFFCDD9E7,
+0xFFD8E4F2,
+0xFFD6E2F0,
+0xFFCCD8E6,
+0xFFCDD9E5,
+0xFFC9D5E1,
+0xFFC9D5E1,
+0xFFC5D1DD,
+0xFFC0CCD8,
+0xFFC6D2DE,
+0xFFCDDBE6,
+0xFFCDDBE4,
+0xFFCADBE3,
+0xFFCCDAE3,
+0xFFCCD9E1,
+0xFFD5E0E6,
+0xFFDCE5EA,
+0xFFDFE6EC,
+0xFFE9F0F6,
+0xFFE1E8EE,
+0xFFD6DDE3,
+0xFFDBE2EA,
+0xFFD5DEE5,
+0xFFD7E1EA,
+0xFFD1DEE7,
+0xFFCFDBE7,
+0xFFD7E5F0,
+0xFFD3E1EE,
+0xFFD1DFEA,
+0xFFD3DFEB,
+0xFFD6E0EA,
+0xFFCFD9E2,
+0xFFD0DBE1,
+0xFFCFDAE0,
+0xFFCBD5DE,
+0xFFCCD6E0,
+0xFFCCD6E0,
+0xFFD1DBE5,
+0xFFD4DEE8,
+0xFFD8E1EA,
+0xFFD4DDE6,
+0xFFDDE1EC,
+0xFFD2D6DF,
+0xFFDFE2E7,
+0xFFEDF2F6,
+0xFFE7EEF4,
+0xFFAFB8C1,
+0xFFD4DCE9,
+0xFFD9DEE4,
+0xFFDEDED6,
+0xFFCFC9B1,
+0xFF80794F,
+0xFFD5CD9F,
+0xFFD8CFAE,
+0xFFE0D5B9,
+0xFFE5D4B8,
+0xFFFFE3C7,
+0xFF832F17,
+0xFF640C00,
+0xFF835234,
+0xFFE7CFB3,
+0xFFD5C8B7,
+0xFFC4BFBB,
+0xFF9797A3,
+0xFF9DA4B7,
+0xFFCCD5E6,
+0xFFADB6C5,
+0xFF8B92A2,
+0xFFAFB5C3,
+0xFFC2C6CF,
+0xFFCED2DB,
+0xFFC9CFDB,
+0xFFBDC5D0,
+0xFFD0D6E2,
+0xFFC3CBD6,
+0xFFC6CEDB,
+0xFFC5CDDA,
+0xFFBEC5D5,
+0xFFC0C8D5,
+0xFFC0C8D5,
+0xFFD0D8E5,
+0xFFCFD9E5,
+0xFFCCD4E1,
+0xFFCBCEDD,
+0xFFCED0DD,
+0xFFD0D4E0,
+0xFFD2DAE5,
+0xFFC6D4DD,
+0xFFCDDEE6,
+0xFFC9D8DF,
+0xFFD3E1E4,
+0xFFD7E0E5,
+0xFFDBE3E6,
+0xFFDCE4E7,
+0xFFDAE2E5,
+0xFFD7DEE4,
+0xFFD6DDE3,
+0xFFD6DDE5,
+0xFFD6DDE5,
+0xFFDBE2EC,
+0xFFD6DEE9,
+0xFFCFD7E2,
+0xFFC8D2DC,
+0xFFC4CEDA,
+0xFFC3CDD9,
+0xFFC1CAD9,
+0xFFBCC9D9,
+0xFFB4C7D6,
+0xFFB1C7D5,
+0xFFB2C9D7,
+0xFFB4CBDB,
+0xFFB5CCDC,
+0xFFB5CCDC,
+0xFFB3CADA,
+0xFFAEC3D4,
+0xFFAEC1D2,
+0xFFB7C8D8,
+0xFFC3D0E0,
+0xFFC2CEDC,
+0xFFC2CAD7,
+0xFFC8CEDA,
+0xFFCED2DD,
+0xFFCACED7,
+0xFFC9D2D7,
+0xFFBAC3C8,
+0xFFCACFD5,
+0xFFCCCFD6,
+0xFFD1D1DB,
+0xFFC9CCD5,
+0xFFC2CBD4,
+0xFFC4CED8,
+0xFFBECAD6,
+0xFFB6C4D1,
+0xFFB4C0D0,
+0xFFB3BED0,
+0xFFACB9CC,
+0xFFA1B0C3,
+0xFF9BACC0,
+0xFF98AAC0,
+0xFF96A8BE,
+0xFF92A6BE,
+0xFF8CA2B9,
+0xFF93A9BE,
+0xFF8FA4B5,
+0xFF98A8B5,
+0xFFA5AEB5,
+0xFFBFC8CF,
+0xFFC2D2E1,
+0xFFC0D3E4,
+0xFFAFC1D5,
+0xFFA9BBCF,
+0xFFA6B8CC,
+0xFFA0B2C6,
+0xFFA3B4C4,
+0xFFBFCFDE,
+0xFF31291E,
+0xFF231D11,
+0xFF453D32,
+0xFF3E382C,
+0xFF2F281E,
+0xFF2B271B,
+0xFF383226,
+0xFF2D2A1B,
+0xFF353223,
+0xFF211F10,
+0xFF312E1F,
+0xFF201E0F,
+0xFF333124,
+0xFF28261A,
+0xFF2C2920,
+0xFF151209,
+0xFF18140B,
+0xFF1F1810,
+0xFF3B342C,
+0xFF2A2319,
+0xFF262014,
+0xFF2A2416,
+0xFF393325,
+0xFF393323,
+0xFF2C2618,
+0xFF3E3B2C,
+0xFF292519,
+0xFF413F32,
+0xFF29261D,
+0xFF221F16,
+0xFF211E17,
+0xFF221F18,
+0xFF28241B,
+0xFF464438,
+0xFF373529,
+0xFF3E3E32,
+0xFF414234,
+0xFF35372A,
+0xFF37392E,
+0xFF3D4037,
+0xFF32332E,
+0xFF2A2B26,
+0xFF272624,
+0xFF34332F,
+0xFF908D88,
+0xFFA7A49B,
+0xFF9C988D,
+0xFF787469,
+0xFF706D68,
+0xFF545550,
+0xFF575C55,
+0xFF565E53,
+0xFF2E332C,
+0xFF292B26,
+0xFF343432,
+0xFF494949,
+0xFF797B78,
+0xFF696A64,
+0xFF79796F,
+0xFF646054,
+0xFF81796E,
+0xFF80796F,
+0xFF95928B,
+0xFFA0A098,
+0xFF717165,
+0xFF4B493A,
+0xFF494635,
+0xFF464030,
+0xFF5A5343,
+0xFF61594E,
+0xFF857E76,
+0xFF898681,
+0xFF9FA09B,
+0xFF545653,
+0xFF4F5450,
+0xFF525655,
+0xFF686C6F,
+0xFF8C8F98,
+0xFFBEC0CF,
+0xFFD3D6E7,
+0xFFD0D8E5,
+0xFFC6D0DA,
+0xFFC7D1DA,
+0xFFCFD8E7,
+0xFFD6DDF7,
+0xFF232845,
+0xFF272C3F,
+0xFF1C2232,
+0xFF2F3044,
+0xFF2E2F41,
+0xFF1E202D,
+0xFF0F111D,
+0xFF2E303D,
+0xFF303342,
+0xFF262B3E,
+0xFF202538,
+0xFF1D2331,
+0xFF191F2D,
+0xFF1C1E2D,
+0xFF141623,
+0xFF161620,
+0xFF0D0D15,
+0xFF0A0B0F,
+0xFF0C0D0F,
+0xFF0B0C10,
+0xFF0C0D11,
+0xFF02050C,
+0xFF2C2F36,
+0xFFF4F5FA,
+0xFFE3E4E8,
+0xFFE1E3E2,
+0xFFEDEFEC,
+0xFFE6EAEB,
+0xFFE4E9ED,
+0xFFDEE5ED,
+0xFFD8DFE9,
+0xFFE1E8F0,
+0xFFDEE5EB,
+0xFFDFE6EE,
+0xFFDEE3E9,
+0xFFDADFE2,
+0xFFC0C5C9,
+0xFFE2E4F1,
+0xFFDDE0EF,
+0xFFDADEEA,
+0xFFDBE2EC,
+0xFFD9E2EB,
+0xFFD3DCE3,
+0xFFDCE3EB,
+0xFFE0E4ED,
+0xFFD5D7E4,
+0xFFD9DBEA,
+0xFFDADCEB,
+0xFFD9DBEA,
+0xFFDBDFEA,
+0xFFCDD4DC,
+0xFFCED7DE,
+0xFFC4D1D9,
+0xFFC8D6E1,
+0xFFC6D6E3,
+0xFFBFCFDC,
+0xFFC4D5DF,
+0xFFCADBE3,
+0xFFD1E0E7,
+0xFFD3DDE7,
+0xFFD1DBE5,
+0xFFD1DBE5,
+0xFFD0DAE4,
+0xFFD0DCE8,
+0xFFCEDAE6,
+0xFFCFD9E5,
+0xFFCAD3E2,
+0xFFC5CEDD,
+0xFFC2CBDA,
+0xFFC5CEDF,
+0xFFC8D4E4,
+0xFFC2CFDF,
+0xFFC3D3E0,
+0xFFC1D1DE,
+0xFFC2D4DE,
+0xFFC6D7DF,
+0xFFCBD9E2,
+0xFFCBD9E2,
+0xFFCFDCE5,
+0xFFD2DFE7,
+0xFFD0DAE3,
+0xFFD3DDE6,
+0xFFD3DDE6,
+0xFFD8E2EB,
+0xFFD4DFE5,
+0xFFCFDAE0,
+0xFFD1DCE2,
+0xFFDBE6EA,
+0xFFD5E0E4,
+0xFFD3DEE2,
+0xFFD8E3E7,
+0xFFD1E0E5,
+0xFFD5E4EB,
+0xFFD2DFE7,
+0xFFD6E3E9,
+0xFFD8E2EB,
+0xFFE1EAF3,
+0xFFD1D8E2,
+0xFFBEC4D0,
+0xFFCED4E0,
+0xFFD8DEEA,
+0xFFD3DBE6,
+0xFFD0DAE4,
+0xFFCFD9E3,
+0xFFCEDAE6,
+0xFFCFDBE7,
+0xFFD5E3F0,
+0xFFD0DEEB,
+0xFFCEDAE6,
+0xFFDEEAF6,
+0xFFD4DEE8,
+0xFFD2DBE4,
+0xFFD2DBE4,
+0xFFD4DDE6,
+0xFFD2DBE4,
+0xFFD4DCE7,
+0xFFD1D9E4,
+0xFFD1DBE7,
+0xFFD2DCE8,
+0xFFD1D9E6,
+0xFFCED6E3,
+0xFFD5D9E5,
+0xFFCBD0D6,
+0xFFDFE3E2,
+0xFFEEF3EF,
+0xFFEBEFEE,
+0xFFA9B1B3,
+0xFFC9D8DD,
+0xFFC6D5DA,
+0xFFC7D3D3,
+0xFFCED4CA,
+0xFFCDC8B4,
+0xFF837546,
+0xFFE0C870,
+0xFFDAB950,
+0xFFEEC863,
+0xFFC59237,
+0xFF934E03,
+0xFF955307,
+0xFFDBB354,
+0xFFCAB155,
+0xFFC8B674,
+0xFFC5BD98,
+0xFF959794,
+0xFFAFB6C6,
+0xFFB9C0D2,
+0xFF8E94A2,
+0xFFA5A9B4,
+0xFFBDC2C8,
+0xFFCDD5D8,
+0xFFC7CED4,
+0xFFB0B4BF,
+0xFFC1C5D0,
+0xFFBEC5CD,
+0xFFC8D1DA,
+0xFFC9D1DE,
+0xFFC7CEDE,
+0xFFC5CADD,
+0xFFC3CADA,
+0xFFBECAD8,
+0xFFBDCBD6,
+0xFFC4D2DB,
+0xFFC9D6DF,
+0xFFD0D8E5,
+0xFFCFD5E3,
+0xFFCFD7E4,
+0xFFD1DBE5,
+0xFFC7D4DC,
+0xFFC8D5DD,
+0xFFC9D3DD,
+0xFFD7E1EA,
+0xFFD6DFE8,
+0xFFD7E0E7,
+0xFFD7E0E7,
+0xFFD6DFE6,
+0xFFD6DDE5,
+0xFFD7DEE6,
+0xFFD9E2E9,
+0xFFDBE4EB,
+0xFFD8E1E8,
+0xFFD3DCE5,
+0xFFCDD5E0,
+0xFFC9D3DD,
+0xFFCCD6E2,
+0xFFCFDBE7,
+0xFFCFDBE7,
+0xFFCBD9E6,
+0xFFC5D3E0,
+0xFFC3D1DE,
+0xFFC3D1DE,
+0xFFC4D2DD,
+0xFFC2D3DD,
+0xFFC6D7DF,
+0xFFC7D8DF,
+0xFFC5D6DD,
+0xFFC2D3DA,
+0xFFCDDBE4,
+0xFFD0DDE6,
+0xFFD0DAE6,
+0xFFD3DAEA,
+0xFFD3D9E9,
+0xFFCCD1E4,
+0xFFC6CCDC,
+0xFFCED5DF,
+0xFFC4CBD1,
+0xFFDADDE4,
+0xFFDFDFE7,
+0xFFE1E1E9,
+0xFFD7DAE3,
+0xFFD1D8E0,
+0xFFD3DDE6,
+0xFFD1DEE6,
+0xFFCCD9E1,
+0xFFCED8E2,
+0xFFCFD9E5,
+0xFFC8D4E0,
+0xFFC3CFDB,
+0xFFC0CED9,
+0xFFC1CFDC,
+0xFFC4D0DE,
+0xFFBFCBDB,
+0xFFBCC9DA,
+0xFFBFCCDC,
+0xFFCAD6E4,
+0xFFD0D7DF,
+0xFFA7A7A9,
+0xFFC6C6C8,
+0xFFDDE4EE,
+0xFFD8E1F0,
+0xFFD3DCED,
+0xFFD0D9EA,
+0xFFC4D0E0,
+0xFFC9D5E3,
+0xFFC8D2DE,
+0xFFC3CBD6,
+0xFF2B2519,
+0xFF292317,
+0xFF443E32,
+0xFF373327,
+0xFF2B271B,
+0xFF2E2A1E,
+0xFF333021,
+0xFF252314,
+0xFF252412,
+0xFF2C2B19,
+0xFF2B291A,
+0xFF202111,
+0xFF2E2F21,
+0xFF232317,
+0xFF2A2A20,
+0xFF1E1B12,
+0xFF160F07,
+0xFF1C130C,
+0xFF443B32,
+0xFF281F16,
+0xFF292317,
+0xFF211B0F,
+0xFF2E281A,
+0xFF282214,
+0xFF241E10,
+0xFF262014,
+0xFF2C261A,
+0xFF3F392D,
+0xFF292218,
+0xFF272016,
+0xFF2D261E,
+0xFF342D23,
+0xFF332D21,
+0xFF383526,
+0xFF353223,
+0xFF272516,
+0xFF232210,
+0xFF313222,
+0xFF3A3B2D,
+0xFF343428,
+0xFF2A2720,
+0xFF2F2A26,
+0xFF2B2320,
+0xFF302722,
+0xFF3D332A,
+0xFF42362A,
+0xFF554838,
+0xFF645848,
+0xFF362E23,
+0xFF4D493D,
+0xFF3E412E,
+0xFF2F3420,
+0xFF2E2F1D,
+0xFF363427,
+0xFF312D24,
+0xFF322E25,
+0xFF312F23,
+0xFF2B2819,
+0xFF37301D,
+0xFF50452F,
+0xFF6A5B44,
+0xFF564732,
+0xFF5C5040,
+0xFF534C3A,
+0xFF514F38,
+0xFF5B573C,
+0xFF4F482C,
+0xFF473B21,
+0xFF665740,
+0xFF594A37,
+0xFF584C3E,
+0xFF655D52,
+0xFF4C483D,
+0xFF524F46,
+0xFF66665C,
+0xFF4A4A42,
+0xFF565553,
+0xFFB5B2B9,
+0xFFE3E1EF,
+0xFFDAD9E9,
+0xFFD6D9E8,
+0xFFCDD4DE,
+0xFFD6DDE5,
+0xFFCED4E2,
+0xFFD0D5F2,
+0xFF242947,
+0xFF24293F,
+0xFF262B3F,
+0xFF202239,
+0xFF212237,
+0xFF1D1F2E,
+0xFF1C202C,
+0xFF2B2E3F,
+0xFF2F3146,
+0xFF21263C,
+0xFF1D2236,
+0xFF1C2232,
+0xFF232635,
+0xFF232532,
+0xFF161824,
+0xFF14141E,
+0xFF131419,
+0xFF090A0E,
+0xFF0D0E10,
+0xFF0A0B0F,
+0xFF07080D,
+0xFF0B0C11,
+0xFF302F34,
+0xFFC5C3C6,
+0xFFD6D5D1,
+0xFF908D84,
+0xFF6F6C63,
+0xFF807D76,
+0xFF797873,
+0xFF959492,
+0xFFCCCCCA,
+0xFFB8B9B4,
+0xFFB2B3AE,
+0xFFB8B8B6,
+0xFFC7C7C5,
+0xFFA7A6A2,
+0xFF82817D,
+0xFFA2A0A3,
+0xFFCFCDD2,
+0xFFDFDFE1,
+0xFFDDDFDE,
+0xFFDDDEE0,
+0xFFE0E4E5,
+0xFFD7DBDE,
+0xFFDEE1E6,
+0xFFDBDBE3,
+0xFFE0DEE9,
+0xFFE3E1EC,
+0xFFD9D8E0,
+0xFFDFDEE3,
+0xFFDCDCDE,
+0xFFDBDCDE,
+0xFFDCE0E1,
+0xFFD7DADF,
+0xFFD8DDE1,
+0xFFDEE3E7,
+0xFFDEE3E6,
+0xFFD8DEDC,
+0xFFDAE0DE,
+0xFFC2C6C9,
+0xFFC1C5C8,
+0xFFBDC1C4,
+0xFFA8ADB0,
+0xFFB0B5B8,
+0xFF787D81,
+0xFF8C8F96,
+0xFFB9BCC5,
+0xFFCCCEDA,
+0xFFC0C3CC,
+0xFFE5E8F1,
+0xFFDEE2EB,
+0xFFDEE5ED,
+0xFFD6E1E7,
+0xFFD3E0E8,
+0xFFCAD7DF,
+0xFFC4D1D9,
+0xFFC2CFD7,
+0xFFC3CDD6,
+0xFFC2CDD3,
+0xFFC6CFD6,
+0xFFC5CED5,
+0xFFC6CDD5,
+0xFFC9D0D6,
+0xFFCAD1D7,
+0xFFDAE2E5,
+0xFFE7EFF2,
+0xFFE2EAEC,
+0xFFDFE7E9,
+0xFFDCE5E4,
+0xFFD5DEDD,
+0xFFD7DFE1,
+0xFFD1D9DC,
+0xFFD2DCDE,
+0xFFB9C1C4,
+0xFFC3CBCD,
+0xFFD3D8DB,
+0xFFDADDE2,
+0xFFA6A6AE,
+0xFF8F8F97,
+0xFFBFBFC9,
+0xFFDADDE6,
+0xFFCCD0D9,
+0xFFD1D8E0,
+0xFFC9D0D8,
+0xFFC8D1DA,
+0xFFD1D9E4,
+0xFFCED6E1,
+0xFFD6DDE5,
+0xFFC4C9CD,
+0xFF7B8083,
+0xFFAEB2B5,
+0xFFC4C5C7,
+0xFFB2B3B5,
+0xFF8D8E90,
+0xFF7A7E7F,
+0xFFBDC1C4,
+0xFFD8DCDF,
+0xFFD6DBE1,
+0xFFD9DDE6,
+0xFFD6D9E2,
+0xFFD9DCE3,
+0xFFD6D7DC,
+0xFFCECFD1,
+0xFFE2E7E1,
+0xFFEFF4EE,
+0xFFF1F3F2,
+0xFFB4B9BC,
+0xFFCFDADC,
+0xFFCFDFDF,
+0xFFCCD8D8,
+0xFFD0D6D2,
+0xFFE0DED1,
+0xFFA79A6E,
+0xFF947A1B,
+0xFFCCA52E,
+0xFFCD9E28,
+0xFFDEA439,
+0xFF9B5000,
+0xFF955100,
+0xFFA57B0B,
+0xFFCEB541,
+0xFFBDA649,
+0xFFB6A668,
+0xFFA4A289,
+0xFF9EA09D,
+0xFF999A9F,
+0xFF6F6E74,
+0xFFCCCACD,
+0xFFE6E6E6,
+0xFFEFF5F1,
+0xFFE5EBE9,
+0xFFECECEE,
+0xFFEEEEF0,
+0xFFE6EBE7,
+0xFFE8EEEC,
+0xFFD3D7DA,
+0xFFD1D1D9,
+0xFFE0DFE7,
+0xFFD8DBE4,
+0xFFCFD8DF,
+0xFFD2DDE3,
+0xFFD8E3E7,
+0xFFD7E2E6,
+0xFFD4DBE5,
+0xFFCBD3DE,
+0xFFC6D0DC,
+0xFFC7D1DB,
+0xFFD0D9E0,
+0xFFCCD5DC,
+0xFFCBD3DE,
+0xFFCCD4E1,
+0xFFD0D8E3,
+0xFFD1DAE3,
+0xFFD4DDE6,
+0xFFD6DFE8,
+0xFFD5DBE7,
+0xFFCED7E0,
+0xFFC8D1DA,
+0xFFC4CDD4,
+0xFFC4CDD4,
+0xFFC7D1DA,
+0xFFCAD4DE,
+0xFFC7D3DF,
+0xFFC5D1DD,
+0xFFC2D0DB,
+0xFFBFCDD8,
+0xFFBDCBD8,
+0xFFBFCBDB,
+0xFFBCC8D8,
+0xFFBBC7D5,
+0xFFBBC7D5,
+0xFFB9C7D2,
+0xFFBBC9D2,
+0xFFBECDD4,
+0xFFBDCCD3,
+0xFFC0CDD5,
+0xFFC4D1DA,
+0xFFC5CFDB,
+0xFFC6D0DC,
+0xFFCAD1E1,
+0xFFC6CDDF,
+0xFFC3C8DC,
+0xFFC8CEDE,
+0xFFD6DDE5,
+0xFFCED3D7,
+0xFFE4E7EC,
+0xFFE8E9EE,
+0xFFE5E5ED,
+0xFFD9DCE3,
+0xFFD2D9E1,
+0xFFD1DCE2,
+0xFFCDD8DE,
+0xFFC9D6DE,
+0xFFCCD6DF,
+0xFFCCD6E0,
+0xFFC8D2DC,
+0xFFC7D1DB,
+0xFFC8D5DE,
+0xFFCBD8E1,
+0xFFCBD5DF,
+0xFFCED8E2,
+0xFFCDD9E7,
+0xFFCCD8E4,
+0xFFCAD4DE,
+0xFFCDD2D8,
+0xFFAAA8A9,
+0xFFBCBABB,
+0xFFC8CCD5,
+0xFFC2CAD7,
+0xFFC2CAD7,
+0xFFC0C8D5,
+0xFFB5BECD,
+0xFFB6C0CC,
+0xFFB7BFCA,
+0xFFB3BBC6,
+0xFF1E1A0F,
+0xFF332F24,
+0xFF282419,
+0xFF38362A,
+0xFF2D2B1E,
+0xFF2C2A1D,
+0xFF2D2B1C,
+0xFF222313,
+0xFF2B2C1A,
+0xFF20210F,
+0xFF272818,
+0xFF212315,
+0xFF232518,
+0xFF1B1D12,
+0xFF11120A,
+0xFF0F0E09,
+0xFF100D08,
+0xFF342F2B,
+0xFF35302A,
+0xFF28231D,
+0xFF27231A,
+0xFF28241B,
+0xFF2A261B,
+0xFF1F1B10,
+0xFF221E13,
+0xFF2A2418,
+0xFF2D271B,
+0xFF393126,
+0xFF392F25,
+0xFF32281E,
+0xFF3F3229,
+0xFF483B32,
+0xFF4A4235,
+0xFF343122,
+0xFF272415,
+0xFF21200E,
+0xFF2A2819,
+0xFF282617,
+0xFF323023,
+0xFF363227,
+0xFF352E26,
+0xFF2F261F,
+0xFF322721,
+0xFF55473E,
+0xFF534336,
+0xFF513E2F,
+0xFF6B5643,
+0xFF61503E,
+0xFF392D1F,
+0xFF423C2C,
+0xFF363820,
+0xFF2C2F14,
+0xFF2E3018,
+0xFF2D2C18,
+0xFF292519,
+0xFF282216,
+0xFF352F21,
+0xFF433C29,
+0xFF564C31,
+0xFF645639,
+0xFF665738,
+0xFF5A492D,
+0xFF65563F,
+0xFF493E2A,
+0xFF575139,
+0xFF635D43,
+0xFF50442A,
+0xFF403017,
+0xFF6A5540,
+0xFF695645,
+0xFF4A3A2B,
+0xFF44382C,
+0xFF463E33,
+0xFF403A2E,
+0xFF504A3C,
+0xFF443D33,
+0xFF3D3834,
+0xFF747071,
+0xFFB1AEB9,
+0xFFAEACB9,
+0xFFD6D6E2,
+0xFFDBDEE5,
+0xFFB8BDC0,
+0xFFD5D9E2,
+0xFFCED2ED,
+0xFF282B4C,
+0xFF262A43,
+0xFF262B41,
+0xFF262743,
+0xFF1B1D36,
+0xFF1B1E2F,
+0xFF0F1221,
+0xFF27293E,
+0xFF262A43,
+0xFF272B46,
+0xFF20243D,
+0xFF303247,
+0xFF282B3C,
+0xFF101221,
+0xFF181A26,
+0xFF15181F,
+0xFF090C11,
+0xFF0D0E12,
+0xFF0B0C10,
+0xFF0E0F14,
+0xFF0A0B10,
+0xFF0D0C12,
+0xFF272528,
+0xFF4F4B48,
+0xFF625B53,
+0xFF564E41,
+0xFF4C4332,
+0xFF49412E,
+0xFF645D4A,
+0xFF534C39,
+0xFF6B654F,
+0xFF59543E,
+0xFF635E48,
+0xFF57503E,
+0xFF777060,
+0xFF615847,
+0xFF584F3E,
+0xFF534A3B,
+0xFF57503E,
+0xFF494431,
+0xFF706D5A,
+0xFF716E5D,
+0xFF979888,
+0xFF65695B,
+0xFF9DA095,
+0xFFD8D8D0,
+0xFF96938E,
+0xFF898480,
+0xFFA7A09A,
+0xFF9F9890,
+0xFFA39A91,
+0xFF766F65,
+0xFF928B83,
+0xFF8D8582,
+0xFFC6BEBB,
+0xFFADA5A2,
+0xFFCAC3BB,
+0xFFA9A397,
+0xFFA29C90,
+0xFF767269,
+0xFF928F86,
+0xFFADAB9E,
+0xFF767465,
+0xFF4B493A,
+0xFF4D4B3E,
+0xFF555146,
+0xFF49453A,
+0xFF4A463D,
+0xFF5E5B52,
+0xFF98958C,
+0xFF88887E,
+0xFFB8B9B1,
+0xFF848983,
+0xFF8C9290,
+0xFFEAF2F5,
+0xFFE4EDF4,
+0xFFDDE6EF,
+0xFFE2E9F1,
+0xFFDDE4EC,
+0xFFE8ECF5,
+0xFFE4E9EF,
+0xFFDDE0E7,
+0xFFDEE1E6,
+0xFFE3E4E8,
+0xFFE2E3E5,
+0xFFE7E8EA,
+0xFFE8EAE9,
+0xFFE1E3E2,
+0xFFEBEDEC,
+0xFFD5D7D4,
+0xFFCACCC9,
+0xFFD8D6D7,
+0xFFA9A5A6,
+0xFF46423F,
+0xFF6A6760,
+0xFF908C83,
+0xFF8E8A81,
+0xFF8E8781,
+0xFF615A54,
+0xFF98908D,
+0xFF908B87,
+0xFF7E7B76,
+0xFF9C9B97,
+0xFFABABAB,
+0xFFBEBFC1,
+0xFFCDCDD5,
+0xFFCAC9CE,
+0xFF8C8781,
+0xFF585246,
+0xFF474133,
+0xFF423B2B,
+0xFF4E4639,
+0xFF564E41,
+0xFF5D5548,
+0xFF5D5548,
+0xFF5C5646,
+0xFF777163,
+0xFFA29E93,
+0xFF908B85,
+0xFF87827E,
+0xFF9B948E,
+0xFF635C52,
+0xFF585449,
+0xFFD5D6D0,
+0xFFE9EDEC,
+0xFFEBEBF3,
+0xFFB4B4BE,
+0xFF9B9CA0,
+0xFFA2A4A3,
+0xFF93968F,
+0xFF828276,
+0xFFA8A390,
+0xFFA19678,
+0xFFA3915F,
+0xFFB69955,
+0xFFC09843,
+0xFFDFA051,
+0xFFA2410E,
+0xFFA84A14,
+0xFF8A5B03,
+0xFFD3B753,
+0xFFEACD6F,
+0xFFCAB161,
+0xFFBEB17A,
+0xFF59512D,
+0xFF645947,
+0xFF6B5E56,
+0xFF766963,
+0xFF8C837C,
+0xFF97978B,
+0xFFA9AC9B,
+0xFF8A8776,
+0xFFA9A693,
+0xFF787A65,
+0xFFB0AF9B,
+0xFF857E6C,
+0xFFCCC3B4,
+0xFFA3998F,
+0xFFB9B2AA,
+0xFFD7D6D2,
+0xFFCDCFCC,
+0xFFC1C2BD,
+0xFFC7C9C6,
+0xFFD0D1D6,
+0xFFD6DAE3,
+0xFFD1D9E4,
+0xFFDBE4ED,
+0xFFE8EDF1,
+0xFFE5ECF2,
+0xFFD8E2EE,
+0xFFC9D2E1,
+0xFFD0D6E2,
+0xFFCED4E0,
+0xFFCFD5E1,
+0xFFD2D8E4,
+0xFFD4DCE9,
+0xFFD2DAE5,
+0xFFCFD8E1,
+0xFFCBD5DE,
+0xFFC4CED7,
+0xFFC6D3DB,
+0xFFC6D4DF,
+0xFFBFCFDC,
+0xFFB9C9D6,
+0xFFB6C8D4,
+0xFFB6C8D4,
+0xFFB6C8D6,
+0xFFB2C1D4,
+0xFFAEBDD2,
+0xFFAEBDD2,
+0xFFB1C0D5,
+0xFFB1C0D5,
+0xFFB1C0D3,
+0xFFB2C1D4,
+0xFFB2C1D4,
+0xFFAEBBCC,
+0xFFB0BDCE,
+0xFFB5C1D1,
+0xFFBAC6D6,
+0xFFBFC8D7,
+0xFFC0CAD6,
+0xFFC9D1DE,
+0xFFD5DCE6,
+0xFFDFE4E7,
+0xFFD2D6D5,
+0xFFE3E7E8,
+0xFFE2E6E9,
+0xFFDDE0E5,
+0xFFD3D8DE,
+0xFFCDD4DC,
+0xFFC8D3D9,
+0xFFC7D1DA,
+0xFFC4D1DA,
+0xFFC7D1DD,
+0xFFC5CFDB,
+0xFFC2C9D9,
+0xFFC3CADA,
+0xFFC7CEE0,
+0xFFC8D1E0,
+0xFFC2CEDA,
+0xFFBFCDD6,
+0xFFB5C7D3,
+0xFFB9CBD5,
+0xFFB2C3CB,
+0xFFB4BFC5,
+0xFFAAAEAF,
+0xFF9CA0A1,
+0xFFA8B2BB,
+0xFFA8B6C3,
+0xFFABB9C6,
+0xFFA9B7C4,
+0xFFA5B5C4,
+0xFFA1B1C0,
+0xFFB1C1CE,
+0xFFC9D9E6,
+0xFF181409,
+0xFF332F24,
+0xFF282419,
+0xFF2B291D,
+0xFF272518,
+0xFF29271A,
+0xFF292718,
+0xFF222313,
+0xFF222311,
+0xFF2C2D1B,
+0xFF242515,
+0xFF2B2D1F,
+0xFF17170B,
+0xFF0E1005,
+0xFF1B1C16,
+0xFF151610,
+0xFF0F0E0A,
+0xFF2A2925,
+0xFF171611,
+0xFF15140F,
+0xFF2D2C27,
+0xFF212119,
+0xFF191911,
+0xFF1A170E,
+0xFF1C1A0E,
+0xFF181409,
+0xFF322C20,
+0xFF2F271A,
+0xFF2E2418,
+0xFF322618,
+0xFF514134,
+0xFF3E3023,
+0xFF3C3226,
+0xFF342E20,
+0xFF272113,
+0xFF312D21,
+0xFF2B271B,
+0xFF1A180C,
+0xFF231F14,
+0xFF474338,
+0xFF383129,
+0xFF2D241B,
+0xFF392F25,
+0xFF4B3D30,
+0xFF4C3B2B,
+0xFF614E3D,
+0xFF634E39,
+0xFF4E3D29,
+0xFF413525,
+0xFF3C3724,
+0xFF383820,
+0xFF2E2E12,
+0xFF44442A,
+0xFF373621,
+0xFF1D1A0B,
+0xFF1F190D,
+0xFF2E2619,
+0xFF4D4532,
+0xFF5B5034,
+0xFF524525,
+0xFF584827,
+0xFF544325,
+0xFF5A4A31,
+0xFF5D4E39,
+0xFF453D28,
+0xFF554D38,
+0xFF4C3D28,
+0xFF422D18,
+0xFF58412F,
+0xFF624B3B,
+0xFF604E40,
+0xFF403225,
+0xFF403728,
+0xFF383121,
+0xFF3B3422,
+0xFF322B1B,
+0xFF322920,
+0xFF302B27,
+0xFF3E393D,
+0xFF3D3A41,
+0xFF807F84,
+0xFF999999,
+0xFF4D5049,
+0xFF7D8182,
+0xFF8789A0,
+0xFF272A49,
+0xFF292D46,
+0xFF22273D,
+0xFF252644,
+0xFF1D1F38,
+0xFF181B2C,
+0xFF0D101F,
+0xFF20253B,
+0xFF353956,
+0xFF3A3D5C,
+0xFF323653,
+0xFF1E2037,
+0xFF0F1223,
+0xFF242635,
+0xFF161824,
+0xFF13161D,
+0xFF0C0F14,
+0xFF0F1015,
+0xFF0D0E13,
+0xFF08090E,
+0xFF0C0B11,
+0xFF0A080D,
+0xFF2C2829,
+0xFF6E6761,
+0xFF5C5449,
+0xFF544937,
+0xFF564A34,
+0xFF4B3F29,
+0xFF4E422A,
+0xFF3E3218,
+0xFF544B2E,
+0xFF564D2E,
+0xFF5E5538,
+0xFF574B33,
+0xFF635741,
+0xFF62533E,
+0xFF584932,
+0xFF63553B,
+0xFF6A5E44,
+0xFF675E41,
+0xFF4E472B,
+0xFF3A341A,
+0xFF433F26,
+0xFF494931,
+0xFF4B4A35,
+0xFF5F5C49,
+0xFF363020,
+0xFF4E4536,
+0xFF554939,
+0xFF4B3E2D,
+0xFF473A29,
+0xFF635646,
+0xFF65574A,
+0xFF55493D,
+0xFF52453C,
+0xFF564A3E,
+0xFF5A4E40,
+0xFF685B4A,
+0xFF635844,
+0xFF605845,
+0xFF5A523F,
+0xFF7D7663,
+0xFF5C5640,
+0xFF4E4830,
+0xFF544E36,
+0xFF443C25,
+0xFF58503B,
+0xFF463E29,
+0xFF5C543F,
+0xFF5A5340,
+0xFF46412E,
+0xFF3A3728,
+0xFF4D4D41,
+0xFF464741,
+0xFFBABCB9,
+0xFFDCE0E1,
+0xFFD2D6D9,
+0xFFDBDCE0,
+0xFFCCCDCF,
+0xFFD0D0D2,
+0xFFB8B8B8,
+0xFF9E9C9D,
+0xFF92918F,
+0xFF7E7A77,
+0xFF64615C,
+0xFF6B6861,
+0xFF8F8C85,
+0xFF8D8A81,
+0xFF928F86,
+0xFF666458,
+0xFF524E43,
+0xFF615851,
+0xFF645A51,
+0xFF62584C,
+0xFF5F5645,
+0xFF655949,
+0xFF5D5240,
+0xFF5C4E41,
+0xFF56483B,
+0xFF4E4236,
+0xFF5B5145,
+0xFF696051,
+0xFF5D5749,
+0xFF40392F,
+0xFF58544B,
+0xFF74706D,
+0xFF847F79,
+0xFF554C3B,
+0xFF4F442E,
+0xFF493F26,
+0xFF3F331B,
+0xFF5D5139,
+0xFF62533C,
+0xFF52462E,
+0xFF5F5339,
+0xFF5D5437,
+0xFF554B30,
+0xFF554A36,
+0xFF625646,
+0xFF625648,
+0xFF5B4F3F,
+0xFF594D37,
+0xFF4D4633,
+0xFFD0D3CA,
+0xFFF3F9F9,
+0xFFEEEEFA,
+0xFFB5B2BD,
+0xFF615859,
+0xFF736A63,
+0xFF706959,
+0xFF5E5842,
+0xFF867F65,
+0xFF776D52,
+0xFF6E6347,
+0xFF735D38,
+0xFF895E27,
+0xFF7A3100,
+0xFF921F02,
+0xFFA83D1D,
+0xFFA8783A,
+0xFF968132,
+0xFF987B2B,
+0xFF917521,
+0xFFCEBA61,
+0xFF7F6E26,
+0xFF6F5F3D,
+0xFF756355,
+0xFF65574C,
+0xFF665C50,
+0xFF666350,
+0xFF5D5C47,
+0xFF67634A,
+0xFF605C41,
+0xFF625E41,
+0xFF666143,
+0xFF7E7357,
+0xFF7B6D52,
+0xFF70614A,
+0xFF6B604C,
+0xFF958C7D,
+0xFF7E7669,
+0xFF706454,
+0xFF998D81,
+0xFFBAB3AB,
+0xFFD7D3D0,
+0xFFD2D2D2,
+0xFFE1E3E2,
+0xFFE0DCD9,
+0xFFEBEBE9,
+0xFFDEE5EB,
+0xFFD3DDE7,
+0xFFD7DDE9,
+0xFFD2D8E4,
+0xFFCED4E0,
+0xFFD0D8E5,
+0xFFD4DCE9,
+0xFFD4DEE8,
+0xFFD2DCE6,
+0xFFCFDCE5,
+0xFFD1DEE7,
+0xFFCCDAE3,
+0xFFC5D3DE,
+0xFFBFCFDC,
+0xFFC0D0DF,
+0xFFC2D2E1,
+0xFFC0D0DD,
+0xFFBCCCDB,
+0xFFBCCBDE,
+0xFFB9C8DD,
+0xFFBAC9DE,
+0xFFBBCADF,
+0xFFB8C7DC,
+0xFFB7C6DB,
+0xFFBDC9DF,
+0xFFC1CDE3,
+0xFFC2CDE1,
+0xFFC1CCDE,
+0xFFC7D3E3,
+0xFFCED7E6,
+0xFFCCD6E2,
+0xFFD0D8E3,
+0xFFD5DEE7,
+0xFFD6DDE5,
+0xFFDCE1E5,
+0xFFCACFD2,
+0xFFD9DEE1,
+0xFFD8DDE1,
+0xFFD4D9DF,
+0xFFCED5DD,
+0xFFCCD5DE,
+0xFFC4CED8,
+0xFFC2CFD8,
+0xFFC3CFDB,
+0xFFC4D0DE,
+0xFFC3CCDB,
+0xFFC0C7D9,
+0xFFC2C7DA,
+0xFFC6CBDE,
+0xFFC5CCDC,
+0xFFC0CAD4,
+0xFFB6C4CD,
+0xFFB7C9D3,
+0xFFB9CBD5,
+0xFFBFD0D8,
+0xFFBFCCD2,
+0xFFB6BABB,
+0xFFA6AAAB,
+0xFFC8D2DB,
+0xFFC2D0DB,
+0xFFC8D6E3,
+0xFFCAD8E5,
+0xFFC7D7E6,
+0xFFBCCEDC,
+0xFFBCCEDC,
+0xFFB9CBD9,
+0xFF282117,
+0xFF393228,
+0xFF2C251B,
+0xFF231F14,
+0xFF2B271B,
+0xFF2B271B,
+0xFF2E2B1C,
+0xFF2A2819,
+0xFF282715,
+0xFF292816,
+0xFF282617,
+0xFF1B1C0E,
+0xFF1F1D11,
+0xFF121208,
+0xFF0F0E09,
+0xFF14150F,
+0xFF1B1C17,
+0xFF161712,
+0xFF1F201B,
+0xFF14150F,
+0xFF191C15,
+0xFF21241B,
+0xFF13140C,
+0xFF15170C,
+0xFF17170B,
+0xFF242216,
+0xFF322C20,
+0xFF2B2316,
+0xFF32291A,
+0xFF3D3121,
+0xFF4F3F30,
+0xFF403323,
+0xFF594F43,
+0xFF372F24,
+0xFF31281F,
+0xFF251E16,
+0xFF28231F,
+0xFF221D19,
+0xFF15120D,
+0xFF28231D,
+0xFF2E2A21,
+0xFF363024,
+0xFF40382B,
+0xFF524938,
+0xFF443925,
+0xFF4C402A,
+0xFF4E3F28,
+0xFF443724,
+0xFF3D3528,
+0xFF383526,
+0xFF2F2C19,
+0xFF38361F,
+0xFF35341F,
+0xFF2E2D1B,
+0xFF28261A,
+0xFF29251C,
+0xFF382E25,
+0xFF483C2E,
+0xFF4E422A,
+0xFF4C3E23,
+0xFF423417,
+0xFF45371C,
+0xFF5B4A36,
+0xFF49392A,
+0xFF3A3122,
+0xFF3D3425,
+0xFF372718,
+0xFF463022,
+0xFF5E4739,
+0xFF574032,
+0xFF544035,
+0xFF403023,
+0xFF362A1A,
+0xFF3A321F,
+0xFF453D28,
+0xFF47402D,
+0xFF3F3828,
+0xFF373125,
+0xFF35322D,
+0xFF33322E,
+0xFF67645D,
+0xFF5A584C,
+0xFF5E5F4D,
+0xFF72736B,
+0xFFA2A4B1,
+0xFF2A2C43,
+0xFF2E3347,
+0xFF23283C,
+0xFF232742,
+0xFF1E2339,
+0xFF1B1E2D,
+0xFF0E1120,
+0xFF20253B,
+0xFF3A3E5B,
+0xFF282B4C,
+0xFF202342,
+0xFF272940,
+0xFF26293C,
+0xFF1C1E2D,
+0xFF141622,
+0xFF11141D,
+0xFF0D1017,
+0xFF0C0F16,
+0xFF090C13,
+0xFF191921,
+0xFF0A0911,
+0xFF0B090E,
+0xFF352F2F,
+0xFF554C45,
+0xFF574E3F,
+0xFF5D503D,
+0xFF594A35,
+0xFF584838,
+0xFF4D3D2D,
+0xFF71624D,
+0xFF5E523A,
+0xFF40341C,
+0xFF5B4F37,
+0xFF564732,
+0xFF5E4F3C,
+0xFF5B4A38,
+0xFF5C4B37,
+0xFF6D5D44,
+0xFF6E5E44,
+0xFF6C5E44,
+0xFF5D5137,
+0xFF50462D,
+0xFF362F15,
+0xFF3A3517,
+0xFF605A3A,
+0xFF5F553A,
+0xFF645840,
+0xFF61523B,
+0xFF64543D,
+0xFF5D4D34,
+0xFF56462F,
+0xFF60513C,
+0xFF635441,
+0xFF514434,
+0xFF483A2D,
+0xFF524535,
+0xFF6A5D4C,
+0xFF665A42,
+0xFF53472D,
+0xFF594F36,
+0xFF5A5037,
+0xFF524733,
+0xFF463B27,
+0xFF5E533F,
+0xFF665B45,
+0xFF695D43,
+0xFF584C32,
+0xFF594D33,
+0xFF62563E,
+0xFF4C412F,
+0xFF4F4838,
+0xFF322C20,
+0xFF3C382D,
+0xFF454239,
+0xFF494941,
+0xFF625F56,
+0xFF4E4B42,
+0xFF5B574E,
+0xFF3A362B,
+0xFF4B4539,
+0xFF413B2D,
+0xFF4B4336,
+0xFF504738,
+0xFF594D3D,
+0xFF5E5341,
+0xFF564B37,
+0xFF3B301C,
+0xFF413922,
+0xFF585039,
+0xFF615A40,
+0xFF584D37,
+0xFF5D503D,
+0xFF5C4D3A,
+0xFF564730,
+0xFF64563C,
+0xFF68583F,
+0xFF675740,
+0xFF645341,
+0xFF6C5B4B,
+0xFF584838,
+0xFF594C39,
+0xFF655943,
+0xFF554E34,
+0xFF4F4730,
+0xFF615B45,
+0xFF5A5541,
+0xFF6D6854,
+0xFF5F5941,
+0xFF5D563C,
+0xFF585135,
+0xFF5B5136,
+0xFF50442A,
+0xFF40341A,
+0xFF473C20,
+0xFF6A5F3F,
+0xFF6D6340,
+0xFF695E3E,
+0xFF5E5238,
+0xFF655943,
+0xFF594A37,
+0xFF51422D,
+0xFF695A3D,
+0xFF5E573B,
+0xFFCED6C7,
+0xFFECF7F3,
+0xFFEEEEF8,
+0xFFB7B0B8,
+0xFF63524B,
+0xFF6B5945,
+0xFF6E5F42,
+0xFF8E815E,
+0xFF877A57,
+0xFF5C5430,
+0xFF464227,
+0xFF5B472E,
+0xFF874E30,
+0xFF812609,
+0xFF9C1F0B,
+0xFFA93C27,
+0xFF7D532D,
+0xFF766A3A,
+0xFF6C5521,
+0xFF8F7626,
+0xFFF4DF60,
+0xFFA99620,
+0xFF5E4E1D,
+0xFF615547,
+0xFF5C5543,
+0xFF514F3A,
+0xFF6B6652,
+0xFF5E5C47,
+0xFF4A4C36,
+0xFF4B4B33,
+0xFF585335,
+0xFF564D2C,
+0xFF665D3E,
+0xFF514628,
+0xFF4E4327,
+0xFF61553B,
+0xFF6C5E44,
+0xFF79684E,
+0xFF806749,
+0xFF7A5F42,
+0xFF735D45,
+0xFF84745D,
+0xFF746756,
+0xFFAEA191,
+0xFFA69686,
+0xFFAB9F91,
+0xFFD5D6D1,
+0xFFDFE7E9,
+0xFFD8E1E6,
+0xFFD7E0E9,
+0xFFCED7E0,
+0xFFCDD7E1,
+0xFFCBD5DF,
+0xFFC7D4DD,
+0xFFC6D3DC,
+0xFFC6D4DF,
+0xFFC5D3DE,
+0xFFC4D2DD,
+0xFFC5D3E0,
+0xFFC0CCDA,
+0xFFC3CFDD,
+0xFFC7D3E1,
+0xFFC7D3E1,
+0xFFCCD5E4,
+0xFFD3DCEB,
+0xFFD4DDEE,
+0xFFCCD5E6,
+0xFFC7D0E1,
+0xFFCBD4E5,
+0xFFCDD6E7,
+0xFFCCD5E4,
+0xFFCBD4E3,
+0xFFCAD4E0,
+0xFFC7D1DD,
+0xFFCED8E2,
+0xFFCED6E1,
+0xFFCFD8E1,
+0xFFCFD6E0,
+0xFFCFD6DE,
+0xFFCDD4DE,
+0xFFCBD1DD,
+0xFFB2B8C4,
+0xFFC1C7D3,
+0xFFC5CBD9,
+0xFFC2CAD7,
+0xFFC9D1DE,
+0xFFCFD8E7,
+0xFFC6D2E0,
+0xFFC8D4E2,
+0xFFC1CFDC,
+0xFFCAD8E5,
+0xFFBFCBD9,
+0xFFC6CFDE,
+0xFFCAD1E1,
+0xFFCCD2E2,
+0xFFCED1E0,
+0xFFCCD0DB,
+0xFFD0D7E1,
+0xFFD2DCE6,
+0xFFC9D5E1,
+0xFFCAD7E0,
+0xFFC9D2D9,
+0xFFC2C2C2,
+0xFFA5A5A7,
+0xFFCED5DD,
+0xFFC0CAD4,
+0xFFC5CDDA,
+0xFFC6D0DC,
+0xFFC4D0DE,
+0xFFC5D1DF,
+0xFFBDCBD8,
+0xFFC1CFDC,
+0xFF251E16,
+0xFF322B23,
+0xFF2B241C,
+0xFF272018,
+0xFF201C11,
+0xFF1E1A0F,
+0xFF2F2B1F,
+0xFF231F13,
+0xFF2A2819,
+0xFF312F20,
+0xFF151306,
+0xFF2A281B,
+0xFF1D1A11,
+0xFF14110A,
+0xFF100F0A,
+0xFF11100B,
+0xFF272622,
+0xFF141510,
+0xFF181914,
+0xFF13140F,
+0xFF0E110A,
+0xFF161912,
+0xFF181B12,
+0xFF16170F,
+0xFF1D1D13,
+0xFF242216,
+0xFF312D21,
+0xFF342E22,
+0xFF41372B,
+0xFF4A3E30,
+0xFF433528,
+0xFF4B3D30,
+0xFF42382E,
+0xFF30271E,
+0xFF28211B,
+0xFF2C2421,
+0xFF231D1D,
+0xFF1E1A19,
+0xFF110D0C,
+0xFF23201B,
+0xFF2B271E,
+0xFF2D291D,
+0xFF433D2D,
+0xFF4F4A36,
+0xFF423C26,
+0xFF544C35,
+0xFF524731,
+0xFF443927,
+0xFF292317,
+0xFF3B372B,
+0xFF393323,
+0xFF302B17,
+0xFF2D2C18,
+0xFF272516,
+0xFF252317,
+0xFF27231A,
+0xFF3C3229,
+0xFF46382B,
+0xFF4F402B,
+0xFF47391F,
+0xFF51462A,
+0xFF40341A,
+0xFF483727,
+0xFF362619,
+0xFF463C30,
+0xFF3A3024,
+0xFF655548,
+0xFF4B382A,
+0xFF573F33,
+0xFF675042,
+0xFF463325,
+0xFF413122,
+0xFF3F3422,
+0xFF453D2A,
+0xFF3E3621,
+0xFF48412E,
+0xFF453E2C,
+0xFF3A3426,
+0xFF161408,
+0xFF474539,
+0xFF605C50,
+0xFF565342,
+0xFF57573F,
+0xFF505143,
+0xFF6F6F79,
+0xFF38394E,
+0xFF27293E,
+0xFF24293F,
+0xFF21253E,
+0xFF22273B,
+0xFF191D29,
+0xFF131723,
+0xFF282D43,
+0xFF353956,
+0xFF2F3251,
+0xFF2B2F4C,
+0xFF272942,
+0xFF1A1D30,
+0xFF1D1F2E,
+0xFF171925,
+0xFF0F121B,
+0xFF0A0D16,
+0xFF080B14,
+0xFF171925,
+0xFF11111B,
+0xFF0E0D15,
+0xFF0A080D,
+0xFF2E2926,
+0xFF5C534A,
+0xFF504436,
+0xFF564734,
+0xFF544532,
+0xFF564637,
+0xFF5B4B3C,
+0xFF504332,
+0xFF473A27,
+0xFF3F301D,
+0xFF675843,
+0xFF493824,
+0xFF4C3B27,
+0xFF574531,
+0xFF5B4935,
+0xFF67553D,
+0xFF635339,
+0xFF5C4E34,
+0xFF52462C,
+0xFF5F553C,
+0xFF443D21,
+0xFF504728,
+0xFF5C5334,
+0xFF53482C,
+0xFF695B41,
+0xFF524229,
+0xFF423219,
+0xFF5B4B32,
+0xFF605037,
+0xFF62533C,
+0xFF483924,
+0xFF493C2B,
+0xFF4B3F2F,
+0xFF605543,
+0xFF625741,
+0xFF5B5235,
+0xFF665B3D,
+0xFF766B4D,
+0xFF4C4125,
+0xFF4B3F27,
+0xFF413620,
+0xFF534633,
+0xFF6C604A,
+0xFF574B31,
+0xFF4D4226,
+0xFF5E5337,
+0xFF52462E,
+0xFF564B37,
+0xFF42392A,
+0xFF2C2618,
+0xFF363226,
+0xFF38362A,
+0xFF373529,
+0xFF353223,
+0xFF4D4737,
+0xFF403929,
+0xFF423B2B,
+0xFF433A29,
+0xFF413926,
+0xFF453827,
+0xFF4B3E2B,
+0xFF63543F,
+0xFF5B4C35,
+0xFF615339,
+0xFF524429,
+0xFF564B2F,
+0xFF584D2F,
+0xFF615638,
+0xFF64593D,
+0xFF53442D,
+0xFF564730,
+0xFF63553A,
+0xFF5B4D30,
+0xFF5B4C2F,
+0xFF79694F,
+0xFF6C5B47,
+0xFF645542,
+0xFF5E4F3C,
+0xFF534731,
+0xFF5F5639,
+0xFF635D3D,
+0xFF645D40,
+0xFF555033,
+0xFF69654C,
+0xFF68634D,
+0xFF423C24,
+0xFF504A30,
+0xFF615A3E,
+0xFF635C40,
+0xFF453B22,
+0xFF5C5237,
+0xFF605539,
+0xFF5A5130,
+0xFF726A45,
+0xFF615935,
+0xFF584F32,
+0xFF4E432D,
+0xFF514431,
+0xFF4D3E29,
+0xFF7F7051,
+0xFF5A5538,
+0xFFC8D0C1,
+0xFFEFF9F8,
+0xFFF4F4FE,
+0xFFB6ACB4,
+0xFF5C4B41,
+0xFF5A4830,
+0xFF776745,
+0xFF807349,
+0xFF75693F,
+0xFF635B36,
+0xFF444229,
+0xFF5D4732,
+0xFF863A2A,
+0xFF972918,
+0xFFAA281A,
+0xFFA43D2C,
+0xFF75513B,
+0xFF655F3F,
+0xFF6E592A,
+0xFF795E0D,
+0xFFE6CA43,
+0xFFEFD75B,
+0xFF3D2B00,
+0xFF554C3D,
+0xFF4F4D38,
+0xFF54543C,
+0xFF5F5A44,
+0xFF56513D,
+0xFF4D4F3A,
+0xFF414129,
+0xFF544B2C,
+0xFF6F6240,
+0xFF5D5234,
+0xFF433A1D,
+0xFF3D3415,
+0xFF574C2E,
+0xFF59482A,
+0xFF6C5535,
+0xFF7D5D37,
+0xFF82603A,
+0xFF7B5F3A,
+0xFF5A4321,
+0xFF6F5C3E,
+0xFF79684E,
+0xFF7E6A51,
+0xFF726350,
+0xFF8C8A7E,
+0xFFC5CBC9,
+0xFFCFD8DD,
+0xFFC7D1DA,
+0xFFCAD4DD,
+0xFFC8D5DD,
+0xFFC1CED7,
+0xFFC3D1DC,
+0xFFC4D2DD,
+0xFFBFCDDA,
+0xFFC2D0DD,
+0xFFCAD6E2,
+0xFFC4CED8,
+0xFFCBD4DD,
+0xFFC8CFD9,
+0xFFCED2DB,
+0xFFBDC1CA,
+0xFF8B9096,
+0xFFB1B6BA,
+0xFFB1B6B9,
+0xFFD1D6DA,
+0xFFD6DDE3,
+0xFFC5CCD4,
+0xFFCCD3DB,
+0xFFC6CDD7,
+0xFFCAD3DC,
+0xFFC7D0D9,
+0xFFBEC7D0,
+0xFFC6CFD8,
+0xFFC7D0D7,
+0xFFC5CCD2,
+0xFFCDD4DA,
+0xFFDEE6E9,
+0xFFCED5DB,
+0xFFCFD6DE,
+0xFFCBD2DC,
+0xFFCDD4DE,
+0xFFC7CED8,
+0xFFB2BBC4,
+0xFFC0C9D2,
+0xFFC4CDD6,
+0xFFC6CED9,
+0xFFCCD6E0,
+0xFFC9D3DD,
+0xFFBEC8D2,
+0xFFBEC8D2,
+0xFFC0C8D3,
+0xFFC4CAD6,
+0xFFCACCD9,
+0xFFC5C3CE,
+0xFFD6D4D9,
+0xFFD7D5D8,
+0xFFD2D5DC,
+0xFFCCD1D7,
+0xFFC4CBD1,
+0xFFC5C9CA,
+0xFFBDB8B4,
+0xFF9A9591,
+0xFFD0D1D3,
+0xFFC9CED2,
+0xFFCED1D8,
+0xFFD1D4DB,
+0xFFD3D7E0,
+0xFFC9D0D8,
+0xFFC5CCD6,
+0xFFBCC5CC,
+0xFF231E18,
+0xFF2E2923,
+0xFF1E1913,
+0xFF231E18,
+0xFF28231D,
+0xFF1B1610,
+0xFF2A261D,
+0xFF302C23,
+0xFF312D22,
+0xFF2D291E,
+0xFF19170B,
+0xFF26231A,
+0xFF25221B,
+0xFF120F0A,
+0xFF130F0C,
+0xFF0C0805,
+0xFF2F2A26,
+0xFF221D19,
+0xFF14110C,
+0xFF1E1B16,
+0xFF1A1914,
+0xFF11100B,
+0xFF0D0C07,
+0xFF1C1C14,
+0xFF1E1E16,
+0xFF2D2A21,
+0xFF2B271E,
+0xFF3B342C,
+0xFF443A31,
+0xFF3F3229,
+0xFF31241B,
+0xFF4B4137,
+0xFF362F25,
+0xFF231F14,
+0xFF29241E,
+0xFF24211C,
+0xFF130F0E,
+0xFF24201F,
+0xFF0C0807,
+0xFF2E2B26,
+0xFF2C2920,
+0xFF363324,
+0xFF383320,
+0xFF403B25,
+0xFF4E4830,
+0xFF534B34,
+0xFF30250F,
+0xFF3F3724,
+0xFF2F291D,
+0xFF3A3428,
+0xFF3A3323,
+0xFF302917,
+0xFF292615,
+0xFF343223,
+0xFF2E2C20,
+0xFF3B342A,
+0xFF4D4037,
+0xFF5A4A3D,
+0xFF50412C,
+0xFF51452D,
+0xFF3A3015,
+0xFF3B301A,
+0xFF2F1F10,
+0xFF332518,
+0xFF42392A,
+0xFF504736,
+0xFF574A39,
+0xFF473624,
+0xFF584332,
+0xFF65503F,
+0xFF3B2817,
+0xFF3D2E1B,
+0xFF514634,
+0xFF443C29,
+0xFF413A28,
+0xFF342D1B,
+0xFF393222,
+0xFF3C3628,
+0xFF4A4738,
+0xFF423F30,
+0xFF40382D,
+0xFF585141,
+0xFF55503A,
+0xFF2F2D20,
+0xFF32303B,
+0xFF42425A,
+0xFF292B44,
+0xFF252740,
+0xFF21253E,
+0xFF171C2F,
+0xFF1B222C,
+0xFF0C131D,
+0xFF23283B,
+0xFF3E425B,
+0xFF2B2F4A,
+0xFF262A45,
+0xFF23253C,
+0xFF26293C,
+0xFF181A29,
+0xFF131522,
+0xFF10121E,
+0xFF050713,
+0xFF0E101D,
+0xFF1C1E2B,
+0xFF10101C,
+0xFF090810,
+0xFF100E11,
+0xFF1E1916,
+0xFF574E45,
+0xFF5A4E40,
+0xFF3D301F,
+0xFF473A27,
+0xFF5C5040,
+0xFF473E2D,
+0xFF473B2B,
+0xFF473C2A,
+0xFF2E2110,
+0xFF5C4D3A,
+0xFF8F7F66,
+0xFF6E5E44,
+0xFF4F3D25,
+0xFF5C4A32,
+0xFF69593F,
+0xFF504026,
+0xFF54482E,
+0xFF544A2F,
+0xFF534E30,
+0xFF575234,
+0xFF443D23,
+0xFF4A3F2B,
+0xFF423524,
+0xFF594939,
+0xFF4B3B2B,
+0xFF433421,
+0xFF4E3F2A,
+0xFF524630,
+0xFF5B503A,
+0xFF504531,
+0xFF4F4734,
+0xFF4B4330,
+0xFF514934,
+0xFF4A4327,
+0xFF534D2B,
+0xFF69613C,
+0xFF8E8661,
+0xFF49411D,
+0xFF5B5233,
+0xFF3D361A,
+0xFF584D37,
+0xFF6C614D,
+0xFF473C28,
+0xFF524731,
+0xFF5C513B,
+0xFF4D452E,
+0xFF4C4431,
+0xFF352E1C,
+0xFF474131,
+0xFF494637,
+0xFF363427,
+0xFF2F2D20,
+0xFF242014,
+0xFF403A2C,
+0xFF332B1E,
+0xFF362F1F,
+0xFF3B3223,
+0xFF382F1E,
+0xFF372A1A,
+0xFF3F3221,
+0xFF5E4F3C,
+0xFF62533E,
+0xFF564732,
+0xFF4D3E27,
+0xFF53472F,
+0xFF463A20,
+0xFF62563C,
+0xFF62563E,
+0xFF483C2C,
+0xFF4E4232,
+0xFF6D624C,
+0xFF63593E,
+0xFF5D5437,
+0xFF4F452A,
+0xFF534930,
+0xFF716650,
+0xFF4C412B,
+0xFF615A40,
+0xFF656042,
+0xFF5A5738,
+0xFF413D20,
+0xFF413F26,
+0xFF64634F,
+0xFF4D4A39,
+0xFF403B27,
+0xFF3E3923,
+0xFF5A543A,
+0xFF5A5339,
+0xFF504831,
+0xFF585039,
+0xFF5F553C,
+0xFF6B6447,
+0xFF58542F,
+0xFF5E5A37,
+0xFF605A42,
+0xFF48412F,
+0xFF32281C,
+0xFF534A39,
+0xFF685E43,
+0xFF47432A,
+0xFFCDD0C7,
+0xFFEEF1F6,
+0xFFEAE6F4,
+0xFFBAB3BB,
+0xFF4A413A,
+0xFF4A422B,
+0xFF655C3B,
+0xFF776F48,
+0xFF69613A,
+0xFF615B39,
+0xFF525037,
+0xFF61402D,
+0xFF9D3C2B,
+0xFFA82918,
+0xFFB33624,
+0xFFA64938,
+0xFF5D3D2E,
+0xFF4C4624,
+0xFF87742F,
+0xFF927517,
+0xFFB89328,
+0xFFC4A249,
+0xFF4D3916,
+0xFF585043,
+0xFF3F3E2A,
+0xFF595843,
+0xFF4F4933,
+0xFF57513B,
+0xFF4A4531,
+0xFF2D270F,
+0xFF665537,
+0xFF725D3E,
+0xFF635339,
+0xFF3F3319,
+0xFF342B0E,
+0xFF4E4325,
+0xFF5E4E2D,
+0xFF715A38,
+0xFF7F623A,
+0xFF85683E,
+0xFF745D33,
+0xFF55431B,
+0xFF685A35,
+0xFF716243,
+0xFF726147,
+0xFF665946,
+0xFF78786C,
+0xFF9CA5A2,
+0xFFC0CBD1,
+0xFFCBD8E1,
+0xFFCBD8E1,
+0xFFC9D8DF,
+0xFFCCDAE3,
+0xFFC7D5E0,
+0xFFC9D6E6,
+0xFFCCD9E9,
+0xFFD1DDEB,
+0xFFD4DEE8,
+0xFFDFE4EA,
+0xFFE3E7E8,
+0xFFE9E9E7,
+0xFFC7C6C2,
+0xFF827D7A,
+0xFF65625B,
+0xFF5D5E4E,
+0xFF575A47,
+0xFF66685A,
+0xFFA5A89F,
+0xFFC6CBC5,
+0xFFC8CCCD,
+0xFFDADFE5,
+0xFFCDD4DC,
+0xFFCAD1DB,
+0xFFCAD1DB,
+0xFFD0D7DF,
+0xFFC8CFD5,
+0xFFA7AFB1,
+0xFFE4EDEC,
+0xFFC6CFCC,
+0xFF9FA5A1,
+0xFF919690,
+0xFFBEC3BD,
+0xFF9EA39F,
+0xFF999F9B,
+0xFF7E837F,
+0xFF6B706C,
+0xFF70726F,
+0xFF828483,
+0xFF868A89,
+0xFFCBCFD0,
+0xFFC3C9C9,
+0xFFB7BCBF,
+0xFFB4B7BC,
+0xFFA4A3A9,
+0xFFB0ABB2,
+0xFFBAB1B6,
+0xFF9B8D8A,
+0xFF8C7F77,
+0xFF7F7774,
+0xFF9E9B96,
+0xFFBBBAB5,
+0xFFAFABA2,
+0xFF9D9183,
+0xFF998D7D,
+0xFFACA89D,
+0xFF909088,
+0xFFD4D1CC,
+0xFF9D9A95,
+0xFF8E8D89,
+0xFFA5A4A0,
+0xFF747371,
+0xFF969792,
+0xFF322922,
+0xFF2F261F,
+0xFF1D140F,
+0xFF19100B,
+0xFF150C07,
+0xFF1E1510,
+0xFF2F261F,
+0xFF251C15,
+0xFF30271E,
+0xFF1B1209,
+0xFF322B21,
+0xFF1B140A,
+0xFF332C24,
+0xFF28211B,
+0xFF160E0B,
+0xFF1B1310,
+0xFF281D19,
+0xFF271C18,
+0xFF120904,
+0xFF1B120D,
+0xFF18110B,
+0xFF110C06,
+0xFF140F09,
+0xFF1D1812,
+0xFF2D2822,
+0xFF181109,
+0xFF2E2721,
+0xFF433A33,
+0xFF3C312B,
+0xFF30231D,
+0xFF2F2019,
+0xFF473A32,
+0xFF352F23,
+0xFF2F2B20,
+0xFF2D2920,
+0xFF2B2620,
+0xFF1B1613,
+0xFF1F1A17,
+0xFF140F0C,
+0xFF2A231D,
+0xFF1E170D,
+0xFF282212,
+0xFF48402D,
+0xFF433B26,
+0xFF493E28,
+0xFF473C26,
+0xFF3B2F19,
+0xFF342917,
+0xFF352D20,
+0xFF2F291D,
+0xFF453C2D,
+0xFF32291A,
+0xFF1F1909,
+0xFF4A4738,
+0xFF2C281C,
+0xFF302A1E,
+0xFF514539,
+0xFF504333,
+0xFF493C29,
+0xFF4A3F29,
+0xFF302A12,
+0xFF2D2613,
+0xFF2A1E10,
+0xFF483C30,
+0xFF362D1E,
+0xFF483F2E,
+0xFF392C1C,
+0xFF413122,
+0xFF5E4B3C,
+0xFF554231,
+0xFF382715,
+0xFF5D4E3B,
+0xFF433826,
+0xFF42392A,
+0xFF3E3629,
+0xFF332B20,
+0xFF292317,
+0xFF433D2F,
+0xFF332D1D,
+0xFF494232,
+0xFF45392D,
+0xFF54483A,
+0xFF453F29,
+0xFF322E22,
+0xFF423F4A,
+0xFF2B2941,
+0xFF262544,
+0xFF282947,
+0xFF1F233C,
+0xFF171C2F,
+0xFF171E28,
+0xFF151C26,
+0xFF232939,
+0xFF373C52,
+0xFF2D314C,
+0xFF272B46,
+0xFF26283F,
+0xFF212437,
+0xFF151726,
+0xFF171926,
+0xFF0A0C18,
+0xFF090B18,
+0xFF232534,
+0xFF1C1E2D,
+0xFF1B1B27,
+0xFF0B0A12,
+0xFF110F10,
+0xFF17140F,
+0xFF534D41,
+0xFF52493A,
+0xFF473A2A,
+0xFF493E2C,
+0xFF4C4532,
+0xFF453E2B,
+0xFF58513E,
+0xFF2F2714,
+0xFF372C1A,
+0xFF7C6D58,
+0xFFD0C1A4,
+0xFF726241,
+0xFF705F41,
+0xFF8F7E62,
+0xFF6C5B3D,
+0xFF56482B,
+0xFF4F4329,
+0xFF4B4428,
+0xFF524D2D,
+0xFF4B4829,
+0xFF403A22,
+0xFF423A27,
+0xFF5D5141,
+0xFF514535,
+0xFF483B2A,
+0xFF463926,
+0xFF4F4430,
+0xFF534832,
+0xFF504831,
+0xFF423A25,
+0xFF3E3724,
+0xFF59533D,
+0xFF413A20,
+0xFF3F3919,
+0xFF6A623D,
+0xFF6C643D,
+0xFF615934,
+0xFF554D29,
+0xFF544E2C,
+0xFF352E11,
+0xFF484127,
+0xFF706A52,
+0xFF4C442F,
+0xFF4A442E,
+0xFF4B432E,
+0xFF47412B,
+0xFF453F29,
+0xFF534E38,
+0xFF55523F,
+0xFF383725,
+0xFF373528,
+0xFF343428,
+0xFF353125,
+0xFF464236,
+0xFF292315,
+0xFF352F21,
+0xFF413A2A,
+0xFF3D3425,
+0xFF2F2313,
+0xFF584C3C,
+0xFF625544,
+0xFF665946,
+0xFF4A3D2A,
+0xFF4A3E28,
+0xFF342913,
+0xFF3B3118,
+0xFF60563D,
+0xFF544933,
+0xFF514537,
+0xFF382F20,
+0xFF4D422E,
+0xFF655B40,
+0xFF675E41,
+0xFF645A3F,
+0xFF4D422C,
+0xFF6B634E,
+0xFF453D28,
+0xFF423C24,
+0xFF5B5638,
+0xFF514E2F,
+0xFF484729,
+0xFF4F4D36,
+0xFF373624,
+0xFF434132,
+0xFF322F1C,
+0xFF3F3A24,
+0xFF5A563D,
+0xFF4B452D,
+0xFF48412E,
+0xFF4C4532,
+0xFF625C44,
+0xFF595538,
+0xFF585532,
+0xFF555533,
+0xFF3D3B24,
+0xFF232011,
+0xFF28241B,
+0xFF5B5549,
+0xFF666249,
+0xFF3D3B24,
+0xFFC1C4BB,
+0xFFF4F5F9,
+0xFFF7F3FF,
+0xFFB6AEB9,
+0xFF38332D,
+0xFF43412C,
+0xFF6A6744,
+0xFF626037,
+0xFF615D37,
+0xFF504C29,
+0xFF5F5A3D,
+0xFF4E2A14,
+0xFF9F392A,
+0xFFCA4C3E,
+0xFFBA4F3D,
+0xFF782D1A,
+0xFF644A39,
+0xFF413A0E,
+0xFFAE9C3A,
+0xFFB39827,
+0xFF987519,
+0xFF7A5B1B,
+0xFF544528,
+0xFF443E30,
+0xFF42412D,
+0xFF3E402A,
+0xFF504B37,
+0xFF48422C,
+0xFF4B4632,
+0xFF615942,
+0xFF6A593D,
+0xFF574328,
+0xFF42361C,
+0xFF2A2309,
+0xFF4F492F,
+0xFF686346,
+0xFF6A5F43,
+0xFF5E4D2F,
+0xFF6C5837,
+0xFF77633E,
+0xFF6F6039,
+0xFF665831,
+0xFF6D613B,
+0xFF726543,
+0xFF6F6146,
+0xFF5F543E,
+0xFF696655,
+0xFFB1B4AB,
+0xFFD2D9DF,
+0xFFCCD4DF,
+0xFFCCD7DD,
+0xFFC9D6DC,
+0xFFCBDAE1,
+0xFFCBD9E4,
+0xFFC1CEDE,
+0xFFC4D0E0,
+0xFFCFD8E7,
+0xFFD7DEE6,
+0xFFDFE1E0,
+0xFFD1D1C7,
+0xFF878475,
+0xFF58513F,
+0xFF534739,
+0xFF564E3B,
+0xFF504C31,
+0xFF565537,
+0xFF494931,
+0xFF51503C,
+0xFF7F8072,
+0xFF62635B,
+0xFFA7A9A4,
+0xFFCDCFCE,
+0xFFE3E4E6,
+0xFFCFD1D0,
+0xFFD9D9D9,
+0xFFBABBB6,
+0xFFA6A69E,
+0xFFA9A99F,
+0xFF7E7F71,
+0xFF505141,
+0xFF615F50,
+0xFF969787,
+0xFF626456,
+0xFF606254,
+0xFF646555,
+0xFF4B493A,
+0xFF474435,
+0xFF474337,
+0xFF504C40,
+0xFF656356,
+0xFF828276,
+0xFF6D6D63,
+0xFF625F58,
+0xFF6D6864,
+0xFF756969,
+0xFF645250,
+0xFF6B554A,
+0xFF6D574A,
+0xFF68574D,
+0xFF685B52,
+0xFF6A6257,
+0xFF6E6254,
+0xFF887861,
+0xFF9E8E77,
+0xFF5C5342,
+0xFF5E5649,
+0xFF7F7569,
+0xFF62584C,
+0xFF585045,
+0xFF625A4F,
+0xFF574E45,
+0xFF5F574C,
+0xFF594B40,
+0xFF4E4035,
+0xFF4A3C33,
+0xFF55473E,
+0xFF4E3F38,
+0xFF51423B,
+0xFF4B3D34,
+0xFF42342B,
+0xFF45372C,
+0xFF483A2F,
+0xFF483A2D,
+0xFF45372C,
+0xFF57493E,
+0xFF493B32,
+0xFF3F3128,
+0xFF44352E,
+0xFF33201A,
+0xFF3E2B27,
+0xFF32201C,
+0xFF2B1915,
+0xFF3E2F2A,
+0xFF1E110B,
+0xFF1C0F09,
+0xFF1F140E,
+0xFF322721,
+0xFF2C1F17,
+0xFF1D100A,
+0xFF5C4D46,
+0xFF44332C,
+0xFF32211A,
+0xFF23100A,
+0xFF3A2921,
+0xFF2D2317,
+0xFF282214,
+0xFF292317,
+0xFF292017,
+0xFF30271E,
+0xFF231910,
+0xFF281B13,
+0xFF34271E,
+0xFF3A2C21,
+0xFF3F3222,
+0xFF564535,
+0xFF372614,
+0xFF5A4834,
+0xFF483622,
+0xFF4C3A26,
+0xFF392816,
+0xFF463C30,
+0xFF3E362B,
+0xFF42382C,
+0xFF3A3024,
+0xFF271F12,
+0xFF2B2517,
+0xFF302A1C,
+0xFF322A1D,
+0xFF483C30,
+0xFF493D2D,
+0xFF4A3F2D,
+0xFF39311E,
+0xFF35301C,
+0xFF3D3727,
+0xFF322C20,
+0xFF302A1E,
+0xFF32281F,
+0xFF392C24,
+0xFF33241D,
+0xFF34231B,
+0xFF503E34,
+0xFF402E22,
+0xFF473626,
+0xFF554535,
+0xFF493B2E,
+0xFF3E342A,
+0xFF201712,
+0xFF261E1B,
+0xFF1C150F,
+0xFF231D11,
+0xFF2F2615,
+0xFF302513,
+0xFF46382B,
+0xFF392C1C,
+0xFF413924,
+0xFF565344,
+0xFF4B4851,
+0xFF201E36,
+0xFF313052,
+0xFF1C1C3E,
+0xFF1C203B,
+0xFF1D2235,
+0xFF131925,
+0xFF0F1521,
+0xFF212437,
+0xFF43455C,
+0xFF31324E,
+0xFF2C2D49,
+0xFF292B42,
+0xFF1D2031,
+0xFF181A29,
+0xFF131522,
+0xFF0E0D1B,
+0xFF151422,
+0xFF1F2130,
+0xFF202231,
+0xFF161622,
+0xFF0C0D12,
+0xFF070705,
+0xFF2C2C24,
+0xFF423E32,
+0xFF433D2D,
+0xFF3F3627,
+0xFF3C3322,
+0xFF393420,
+0xFF312C16,
+0xFF847E68,
+0xFFA19984,
+0xFF483D29,
+0xFF493B21,
+0xFFAB9B7A,
+0xFF8F7D59,
+0xFFBCA887,
+0xFF493415,
+0xFF594928,
+0xFF554627,
+0xFF564B2F,
+0xFF514A2D,
+0xFF5A5734,
+0xFF4C4C2A,
+0xFF322E13,
+0xFF47432A,
+0xFF49432D,
+0xFF443E28,
+0xFF504831,
+0xFF423B21,
+0xFF383117,
+0xFF4B4428,
+0xFF504A30,
+0xFF49432B,
+0xFF3B331E,
+0xFF524A33,
+0xFF4C4227,
+0xFF584D2D,
+0xFF6A5E36,
+0xFF5F532B,
+0xFF493F1C,
+0xFF4B4223,
+0xFF2B2503,
+0xFF4A4424,
+0xFF423D1F,
+0xFF5B573C,
+0xFF3B351D,
+0xFF464229,
+0xFF4F4931,
+0xFF444025,
+0xFF444025,
+0xFF99957A,
+0xFF4A4831,
+0xFF252412,
+0xFF2E2B22,
+0xFF212119,
+0xFF4D4D41,
+0xFF494A3C,
+0xFF2C2A1B,
+0xFF403E2F,
+0xFF3E3B2A,
+0xFF332D1D,
+0xFF383121,
+0xFF544D3B,
+0xFF514837,
+0xFF514936,
+0xFF4B4431,
+0xFF37311B,
+0xFF413B25,
+0xFF3C361E,
+0xFF58543B,
+0xFF625C46,
+0xFF504434,
+0xFF413622,
+0xFF44381E,
+0xFF685D3F,
+0xFF64593B,
+0xFF5F5339,
+0xFF594C39,
+0xFF403322,
+0xFF392C1B,
+0xFF2D220E,
+0xFF5E5439,
+0xFF554E31,
+0xFF544F32,
+0xFF48422A,
+0xFF45402D,
+0xFF393323,
+0xFF292613,
+0xFF2F2D16,
+0xFF504E35,
+0xFF605B45,
+0xFF393421,
+0xFF484330,
+0xFF696750,
+0xFF4F5031,
+0xFF535530,
+0xFF454928,
+0xFF333720,
+0xFF191B0E,
+0xFF21221C,
+0xFF535349,
+0xFF50523C,
+0xFF292D14,
+0xFFBEC7B6,
+0xFFF0F6F2,
+0xFFF5F1FF,
+0xFFB6B0BC,
+0xFF423D39,
+0xFF484732,
+0xFF3E421D,
+0xFF50562A,
+0xFF5C5D35,
+0xFF5C5832,
+0xFF6B613E,
+0xFF765136,
+0xFF802419,
+0xFF7C140B,
+0xFF904333,
+0xFF62321B,
+0xFF514022,
+0xFF433E00,
+0xFFFFF570,
+0xFFC9B329,
+0xFF705703,
+0xFF493709,
+0xFF59513A,
+0xFF515242,
+0xFF464833,
+0xFF3B3D27,
+0xFF3D3C27,
+0xFF474631,
+0xFF494730,
+0xFF504A34,
+0xFF4B402A,
+0xFF544933,
+0xFF433F26,
+0xFF2A2A12,
+0xFF585A44,
+0xFF656752,
+0xFF585542,
+0xFF46412E,
+0xFF443D2A,
+0xFF3C341D,
+0xFF534C30,
+0xFF615839,
+0xFF6F6542,
+0xFF685B39,
+0xFF645639,
+0xFF5B5034,
+0xFF64593D,
+0xFF827B68,
+0xFFB7B5B6,
+0xFFCFD2D9,
+0xFF898F8F,
+0xFF707978,
+0xFFB6C0C2,
+0xFFE0EBF1,
+0xFFCDD6E5,
+0xFFD1DAEB,
+0xFFD3D9E7,
+0xFFD6DBDF,
+0xFFC5C6BE,
+0xFF5D5B46,
+0xFF534E31,
+0xFF5B5032,
+0xFF5F4F35,
+0xFF514328,
+0xFF4C4528,
+0xFF817C5E,
+0xFF454126,
+0xFF555138,
+0xFF76715B,
+0xFF46442F,
+0xFF4D4A39,
+0xFF555241,
+0xFFB0AA9A,
+0xFFBAB3A1,
+0xFF867A6A,
+0xFF857865,
+0xFF756450,
+0xFF66543C,
+0xFF69583E,
+0xFF63533A,
+0xFF594E38,
+0xFF8A8370,
+0xFF7F7A64,
+0xFF5D5842,
+0xFF5C563E,
+0xFF4F482E,
+0xFF564A32,
+0xFF4E4228,
+0xFF5B4F35,
+0xFF5C5036,
+0xFF625B41,
+0xFF564E37,
+0xFF524A35,
+0xFF564936,
+0xFF675445,
+0xFF694F42,
+0xFF6A4A3D,
+0xFF6B4B3E,
+0xFF6D5247,
+0xFF675348,
+0xFF645447,
+0xFF5B4A3A,
+0xFF816B53,
+0xFFB29C84,
+0xFF695A45,
+0xFF645746,
+0xFF6A5949,
+0xFF695848,
+0xFF635344,
+0xFF605041,
+0xFF635145,
+0xFF665446,
+0xFF513E30,
+0xFF5A463B,
+0xFF5A463B,
+0xFF564239,
+0xFF58443B,
+0xFF655148,
+0xFF564239,
+0xFF503C31,
+0xFF614D42,
+0xFF635042,
+0xFF624F41,
+0xFF655244,
+0xFF6E5B4D,
+0xFF685547,
+0xFF584439,
+0xFF675348,
+0xFF69524A,
+0xFF715851,
+0xFF68514B,
+0xFF715A52,
+0xFF665249,
+0xFF6B594F,
+0xFF6E5C52,
+0xFF6A584E,
+0xFF645248,
+0xFF6B594F,
+0xFF68544B,
+0xFF624E43,
+0xFF563F37,
+0xFF675146,
+0xFF6C534C,
+0xFF5E483D,
+0xFF615142,
+0xFF534636,
+0xFF5B4E3E,
+0xFF514132,
+0xFF6A584C,
+0xFF4F3D31,
+0xFF513E30,
+0xFF604A3D,
+0xFF5D473A,
+0xFF5B4436,
+0xFF5A4335,
+0xFF442A1B,
+0xFF543A29,
+0xFF4D3420,
+0xFF5D4430,
+0xFF513C29,
+0xFF483829,
+0xFF423429,
+0xFF392B1E,
+0xFF3B2D20,
+0xFF312316,
+0xFF4E4033,
+0xFF2A1C0F,
+0xFF271A0A,
+0xFF6C5C4D,
+0xFF483828,
+0xFF382B1A,
+0xFF3D3220,
+0xFF271E0D,
+0xFF393222,
+0xFF2B2519,
+0xFF251F13,
+0xFF281B13,
+0xFF21120B,
+0xFF362722,
+0xFF271813,
+0xFF3B2A22,
+0xFF4A382C,
+0xFF4D3C2C,
+0xFF4B3A2A,
+0xFF55473A,
+0xFF372A22,
+0xFF1C1211,
+0xFF2C2324,
+0xFF150D0A,
+0xFF2D251A,
+0xFF2D220E,
+0xFF483C22,
+0xFF493A23,
+0xFF4D4129,
+0xFF2E2808,
+0xFF5B5640,
+0xFF474246,
+0xFF312F44,
+0xFF2E2D4D,
+0xFF2A2A4C,
+0xFF282C45,
+0xFF23283B,
+0xFF1B212F,
+0xFF101624,
+0xFF1A1C31,
+0xFF444561,
+0xFF262648,
+0xFF303150,
+0xFF1F2138,
+0xFF131627,
+0xFF171926,
+0xFF151724,
+0xFF0B0A18,
+0xFF201F2D,
+0xFF323345,
+0xFF1C1E2D,
+0xFF090915,
+0xFF0A0B10,
+0xFF060604,
+0xFF36382D,
+0xFF3B392A,
+0xFF484534,
+0xFF494134,
+0xFF30281B,
+0xFF27220F,
+0xFF4D4834,
+0xFF403A22,
+0xFF7E765F,
+0xFFE7DBC5,
+0xFF7F6F55,
+0xFFA18E6D,
+0xFFC8B491,
+0xFF573E1F,
+0xFF4D3617,
+0xFF6C5837,
+0xFF625231,
+0xFF54462B,
+0xFF51472C,
+0xFF4C4729,
+0xFF504D2E,
+0xFF353116,
+0xFF504C33,
+0xFF413D24,
+0xFF554F37,
+0xFF625C44,
+0xFF443E24,
+0xFF474225,
+0xFF443F22,
+0xFF524C32,
+0xFF372F18,
+0xFF3A321D,
+0xFF4B402A,
+0xFF53452B,
+0xFF615231,
+0xFF64552C,
+0xFF64552C,
+0xFF5C4F2C,
+0xFF403716,
+0xFF4D4423,
+0xFF514B2B,
+0xFF3E391C,
+0xFF555136,
+0xFF444027,
+0xFF332F16,
+0xFF4F4B32,
+0xFF454126,
+0xFF332E11,
+0xFF7C785D,
+0xFF4D4832,
+0xFF252211,
+0xFF2A271E,
+0xFF201D16,
+0xFF3E3E32,
+0xFF333527,
+0xFF2E2F1F,
+0xFF353324,
+0xFF353221,
+0xFF403D2C,
+0xFF443E2E,
+0xFF3E3828,
+0xFF413A28,
+0xFF4A4331,
+0xFF4D4634,
+0xFF2A2511,
+0xFF4E4935,
+0xFF2A250F,
+0xFF4A4531,
+0xFF55503C,
+0xFF3A321F,
+0xFF30250F,
+0xFF504527,
+0xFF695E3E,
+0xFF6D6242,
+0xFF52472B,
+0xFF574833,
+0xFF493C2B,
+0xFF4D402F,
+0xFF3D321E,
+0xFF483E23,
+0xFF423B1E,
+0xFF70694D,
+0xFF534D35,
+0xFF4A4331,
+0xFF322B1B,
+0xFF362F1D,
+0xFF423C26,
+0xFF68624A,
+0xFF605A42,
+0xFF38301D,
+0xFF564E3B,
+0xFF5C563E,
+0xFF5C5739,
+0xFF4D4B24,
+0xFF565632,
+0xFF4F4D34,
+0xFF272415,
+0xFF2B271E,
+0xFF403A2E,
+0xFF6D694E,
+0xFF2C2B0D,
+0xFFC2C5B0,
+0xFFF4F7F0,
+0xFFF2EFF8,
+0xFFB5B2BB,
+0xFF23221D,
+0xFF4E503B,
+0xFF565A37,
+0xFF555A31,
+0xFF40421D,
+0xFF514E2D,
+0xFF6C5F3F,
+0xFF744A32,
+0xFF70160D,
+0xFF660500,
+0xFF612316,
+0xFF5B391E,
+0xFF4D3F10,
+0xFF898228,
+0xFFEEDF46,
+0xFFEDDC48,
+0xFF6F5D15,
+0xFF504225,
+0xFF42402B,
+0xFF595A4A,
+0xFF575642,
+0xFF43422D,
+0xFF4A4935,
+0xFF373622,
+0xFF4F4E39,
+0xFF36341F,
+0xFF433E2B,
+0xFF43412C,
+0xFF32341C,
+0xFF2F331C,
+0xFF474A35,
+0xFF606151,
+0xFF525343,
+0xFF3C3D2F,
+0xFF28291B,
+0xFF363523,
+0xFF3D371F,
+0xFF74694D,
+0xFF655637,
+0xFF5F502F,
+0xFF605539,
+0xFF57492E,
+0xFF615032,
+0xFF5A4A33,
+0xFF524741,
+0xFFAEA9A6,
+0xFF77776D,
+0xFF55584D,
+0xFF464B45,
+0xFFC1C9CB,
+0xFFD3DBE6,
+0xFFD1D7E7,
+0xFFD8DCE8,
+0xFFDBDFE2,
+0xFF9A9B8D,
+0xFF59583C,
+0xFF4E4622,
+0xFF615431,
+0xFF695938,
+0xFF615233,
+0xFF44391D,
+0xFF797256,
+0xFF3A341A,
+0xFF433D23,
+0xFF726C54,
+0xFF3B371E,
+0xFF3B351F,
+0xFF3E3820,
+0xFF383019,
+0xFF8D836A,
+0xFF56462D,
+0xFF645337,
+0xFF70583C,
+0xFF745B3C,
+0xFF846A49,
+0xFF72593B,
+0xFF5C4C35,
+0xFF7F745E,
+0xFF79715A,
+0xFF474026,
+0xFF4E4429,
+0xFF44391D,
+0xFF605134,
+0xFF5C4B2D,
+0xFF6C593B,
+0xFF625133,
+0xFF6C5E41,
+0xFF6A5F43,
+0xFF685A40,
+0xFF64523C,
+0xFF533D28,
+0xFF5C3F2D,
+0xFF6C4737,
+0xFF603A2D,
+0xFF715348,
+0xFF6E564A,
+0xFF584537,
+0xFF5E4B3A,
+0xFF8E765C,
+0xFFB29A80,
+0xFF56462F,
+0xFF5E4F3A,
+0xFF6E5C48,
+0xFF62503C,
+0xFF5B4837,
+0xFF665344,
+0xFF5F493B,
+0xFF5A4436,
+0xFF513B2D,
+0xFF4C3628,
+0xFF584235,
+0xFF5B453A,
+0xFF553F34,
+0xFF564035,
+0xFF553F34,
+0xFF4D372C,
+0xFF584034,
+0xFF584133,
+0xFF594234,
+0xFF5C4537,
+0xFF6D5648,
+0xFF5D4638,
+0xFF634C3E,
+0xFF624B3D,
+0xFF5F4538,
+0xFF6D5346,
+0xFF74594E,
+0xFF5F4538,
+0xFF6C5245,
+0xFF6D5648,
+0xFF715A4A,
+0xFF654E3E,
+0xFF5C4533,
+0xFF6E5443,
+0xFF6A4F3E,
+0xFF644936,
+0xFF6A4D3D,
+0xFF6A4D3B,
+0xFF785849,
+0xFF725545,
+0xFF6E5244,
+0xFF735749,
+0xFF745948,
+0xFF684D3C,
+0xFF8B6E5C,
+0xFF6B4E3C,
+0xFF745747,
+0xFF755546,
+0xFF6D4D40,
+0xFF78584D,
+0xFF77574C,
+0xFF76594B,
+0xFF755848,
+0xFF795E4B,
+0xFF664C35,
+0xFF412611,
+0xFF654B3C,
+0xFF5D4638,
+0xFF644E40,
+0xFF584234,
+0xFF695244,
+0xFF62483B,
+0xFF5F4536,
+0xFF593F2E,
+0xFF5B4432,
+0xFF4A3522,
+0xFF4A3522,
+0xFF4C3726,
+0xFF372416,
+0xFF463629,
+0xFF362A1C,
+0xFF261A0E,
+0xFF2B1D12,
+0xFF2C1B13,
+0xFF2D1E17,
+0xFF34251E,
+0xFF39281E,
+0xFF322012,
+0xFF3E2C18,
+0xFF392713,
+0xFF3B2B1C,
+0xFF271A12,
+0xFF211716,
+0xFF1F1617,
+0xFF140D07,
+0xFF3D3425,
+0xFF302509,
+0xFF453815,
+0xFF544621,
+0xFF594D23,
+0xFF7F784A,
+0xFF4D4B25,
+0xFF626054,
+0xFF35343C,
+0xFF2D2D47,
+0xFF30314F,
+0xFF2B3044,
+0xFF0E1424,
+0xFF070D1D,
+0xFF1E2336,
+0xFF272942,
+0xFF49496B,
+0xFF3E3D65,
+0xFF37375D,
+0xFF1F2138,
+0xFF242736,
+0xFF191B28,
+0xFF11131F,
+0xFF141321,
+0xFF252432,
+0xFF2C2B3D,
+0xFF0B0A1A,
+0xFF0B0E17,
+0xFF0C1013,
+0xFF0D0F0A,
+0xFF2D2F22,
+0xFF4C4A3B,
+0xFF4B4839,
+0xFF645E52,
+0xFF383226,
+0xFF31291E,
+0xFF312A1A,
+0xFF463E29,
+0xFF43371F,
+0xFF72624B,
+0xFFC1AD94,
+0xFF9B8465,
+0xFF8B7253,
+0xFF4F3119,
+0xFF745840,
+0xFF8E7556,
+0xFF5F4A2B,
+0xFF56452B,
+0xFF675B43,
+0xFF443C25,
+0xFF443E26,
+0xFF2D270F,
+0xFF4C4630,
+0xFF4D4731,
+0xFF423A23,
+0xFF5B533C,
+0xFF2F280E,
+0xFF484326,
+0xFF464124,
+0xFF453E24,
+0xFF3E361F,
+0xFF382D19,
+0xFF372B15,
+0xFF4E3E25,
+0xFF5A492B,
+0xFF66522D,
+0xFF645328,
+0xFF63562C,
+0xFF584C26,
+0xFF685D3D,
+0xFF41381B,
+0xFF504831,
+0xFF59533D,
+0xFF3B351F,
+0xFF322C14,
+0xFF48422A,
+0xFF2F2911,
+0xFF433B24,
+0xFF746E58,
+0xFF5F5846,
+0xFF282212,
+0xFF4B4537,
+0xFF2E2A1E,
+0xFF323023,
+0xFF393A2C,
+0xFF343223,
+0xFF312F20,
+0xFF373425,
+0xFF4E483A,
+0xFF352E1E,
+0xFF342D1D,
+0xFF393021,
+0xFF433A29,
+0xFF3C3322,
+0xFF362F1D,
+0xFF433C2A,
+0xFF26210D,
+0xFF494431,
+0xFF46412D,
+0xFF2C2411,
+0xFF595238,
+0xFF706746,
+0xFF615934,
+0xFF544C27,
+0xFF554C2B,
+0xFF53472D,
+0xFF3A2F19,
+0xFF362B17,
+0xFF514630,
+0xFF494023,
+0xFF4E472A,
+0xFF5F583C,
+0xFF332D15,
+0xFF504939,
+0xFF332B1E,
+0xFF453929,
+0xFF645744,
+0xFF7E6F58,
+0xFF65563F,
+0xFF5A4935,
+0xFF6D5B47,
+0xFF6F5E44,
+0xFF8A7A58,
+0xFF7F7045,
+0xFF72633A,
+0xFF7D6C4E,
+0xFF73614B,
+0xFF584234,
+0xFF452F1A,
+0xFF6F5836,
+0xFF6E5C38,
+0xFF978C76,
+0xFFF2EEE5,
+0xFFEEECF1,
+0xFFB3B4B8,
+0xFF212820,
+0xFF2F3420,
+0xFF5D5C3E,
+0xFF514E2F,
+0xFF43462B,
+0xFF56543F,
+0xFF524532,
+0xFF592B1C,
+0xFF78160D,
+0xFF750E07,
+0xFF68281F,
+0xFF644125,
+0xFF3E2B00,
+0xFFD1C454,
+0xFFE0D032,
+0xFFE9D84A,
+0xFF6C5C21,
+0xFF504533,
+0xFF595643,
+0xFF4B4A36,
+0xFF3F3826,
+0xFF382F20,
+0xFF3F372A,
+0xFF494637,
+0xFF3A3B29,
+0xFF292C17,
+0xFF2B2C1A,
+0xFF2E311C,
+0xFF1B1F08,
+0xFF464A31,
+0xFF474631,
+0xFF5D5A47,
+0xFF504D3A,
+0xFF4C4B37,
+0xFF272A17,
+0xFF23220D,
+0xFF40341A,
+0xFF635234,
+0xFF6D5938,
+0xFF796646,
+0xFF50442C,
+0xFF453923,
+0xFF533D26,
+0xFF604733,
+0xFF554434,
+0xFF4A3D2D,
+0xFF504831,
+0xFF45402A,
+0xFF2D2E1C,
+0xFF7F827B,
+0xFFD0D3DA,
+0xFFD3D7E3,
+0xFFD9DBE8,
+0xFFA8A9AD,
+0xFF6F7062,
+0xFF5A593D,
+0xFF524A26,
+0xFF6A5D3A,
+0xFF756446,
+0xFF68583E,
+0xFF41351D,
+0xFF78705B,
+0xFF2C2610,
+0xFF49422F,
+0xFF7D7864,
+0xFF35331E,
+0xFF3A3521,
+0xFF37321E,
+0xFF38321C,
+0xFF8F8770,
+0xFF57492F,
+0xFF554629,
+0xFF695435,
+0xFF806949,
+0xFF806645,
+0xFF715A3B,
+0xFF493824,
+0xFF6F6452,
+0xFF766E59,
+0xFF564E37,
+0xFF695F46,
+0xFF56482E,
+0xFF746349,
+0xFF6E5A3F,
+0xFF816C51,
+0xFF725E45,
+0xFF695940,
+0xFF65563F,
+0xFF62513D,
+0xFF614E3D,
+0xFF583E31,
+0xFF523225,
+0xFF583323,
+0xFF593424,
+0xFF5E4236,
+0xFF5E483B,
+0xFF5B493B,
+0xFF665543,
+0xFF7A654A,
+0xFFAF9A7F,
+0xFF61523B,
+0xFF524630,
+0xFF54442D,
+0xFF52402A,
+0xFF4F3C2B,
+0xFF4C3B29,
+0xFF544130,
+0xFF604D3C,
+0xFF4F382A,
+0xFF533C2E,
+0xFF543C30,
+0xFF4C3428,
+0xFF543C32,
+0xFF50382E,
+0xFF563E34,
+0xFF563B30,
+0xFF5E4437,
+0xFF5D4334,
+0xFF5F4536,
+0xFF5C4032,
+0xFF715547,
+0xFF5A3E30,
+0xFF6E5244,
+0xFF583C2E,
+0xFF65493B,
+0xFF64483A,
+0xFF5F4234,
+0xFF664939,
+0xFF644938,
+0xFF654A37,
+0xFF5D402E,
+0xFF725641,
+0xFF694E39,
+0xFF5F432D,
+0xFF6A4A35,
+0xFF64412D,
+0xFF6A4733,
+0xFF6A4733,
+0xFF785541,
+0xFF785541,
+0xFF714E3B,
+0xFF765340,
+0xFF7D5A47,
+0xFF5C3925,
+0xFF805D49,
+0xFF775440,
+0xFF775441,
+0xFF7C5946,
+0xFF745042,
+0xFF765244,
+0xFF6E4C40,
+0xFF6B493D,
+0xFF735344,
+0xFF795A46,
+0xFF70513D,
+0xFF634430,
+0xFF6E4E3F,
+0xFF715444,
+0xFF705544,
+0xFF705544,
+0xFF7A5A4B,
+0xFF725243,
+0xFF785746,
+0xFF583925,
+0xFF624631,
+0xFF826752,
+0xFF806552,
+0xFF785D4C,
+0xFF775B4D,
+0xFF876D60,
+0xFF685547,
+0xFF6B584A,
+0xFF725B4D,
+0xFF6A5345,
+0xFF6C5649,
+0xFF645143,
+0xFF6E5B4A,
+0xFF67523F,
+0xFF715844,
+0xFF563D29,
+0xFF5E4737,
+0xFF5B483A,
+0xFF483A31,
+0xFF3F3229,
+0xFF3C3022,
+0xFF382912,
+0xFF5B4B29,
+0xFF837247,
+0xFF7E6B40,
+0xFF796938,
+0xFF625922,
+0xFF615D2E,
+0xFF84826B,
+0xFF343331,
+0xFF35364A,
+0xFF383957,
+0xFF1E223B,
+0xFF0C1127,
+0xFF32374B,
+0xFF30354B,
+0xFF070922,
+0xFF333453,
+0xFF3C3B63,
+0xFF29294D,
+0xFF1D1F34,
+0xFF131723,
+0xFF141623,
+0xFF0F111E,
+0xFF1B1D2C,
+0xFF333544,
+0xFF28293B,
+0xFF0D101F,
+0xFF0F131C,
+0xFF050608,
+0xFF19160D,
+0xFF373123,
+0xFF484232,
+0xFF4E4735,
+0xFF3F3828,
+0xFF31291C,
+0xFF3B3125,
+0xFF413829,
+0xFF564A34,
+0xFF55452C,
+0xFF4B3921,
+0xFF503B20,
+0xFFC3A88B,
+0xFF7C5F41,
+0xFF54341B,
+0xFF5D3F25,
+0xFF604527,
+0xFF664F30,
+0xFF4E3A21,
+0xFF42311D,
+0xFF473C28,
+0xFF433824,
+0xFF3D2E19,
+0xFF3E2E17,
+0xFF43341F,
+0xFF40311C,
+0xFF54442D,
+0xFF53452B,
+0xFF50472A,
+0xFF453E22,
+0xFF4E472D,
+0xFF413620,
+0xFF271805,
+0xFF46361F,
+0xFF5C462E,
+0xFF5A4324,
+0xFF7B6540,
+0xFF65522A,
+0xFF73643B,
+0xFF625630,
+0xFF504527,
+0xFF575036,
+0xFF443C29,
+0xFF4C4533,
+0xFF37301E,
+0xFF1F1805,
+0xFF59513C,
+0xFF4C442F,
+0xFF423723,
+0xFF867B69,
+0xFF514837,
+0xFF201909,
+0xFF373020,
+0xFF484234,
+0xFF373529,
+0xFF2E2C20,
+0xFF39372A,
+0xFF454233,
+0xFF403D2E,
+0xFF322C1E,
+0xFF413B2B,
+0xFF383222,
+0xFF3E3629,
+0xFF4A4034,
+0xFF3F3627,
+0xFF2E2717,
+0xFF5D5646,
+0xFF2C2616,
+0xFF3B3424,
+0xFF4B4432,
+0xFF302916,
+0xFF413A20,
+0xFF5B5535,
+0xFF4D4723,
+0xFF534B26,
+0xFF655D39,
+0xFF564D30,
+0xFF42381D,
+0xFF4C4229,
+0xFF585135,
+0xFF504A2A,
+0xFF534D2B,
+0xFF60593C,
+0xFF3C351B,
+0xFF5A5140,
+0xFF372B1B,
+0xFF4F422F,
+0xFF7B6D53,
+0xFF6C5B41,
+0xFF615036,
+0xFF4A3824,
+0xFF4C3820,
+0xFF7D6445,
+0xFF846B43,
+0xFFA58D61,
+0xFF90784C,
+0xFF997C5A,
+0xFF785A3E,
+0xFF84614B,
+0xFF7C5A3F,
+0xFF977750,
+0xFF836944,
+0xFFA4957E,
+0xFFF2EBE1,
+0xFFF4F2F5,
+0xFFB4B5B7,
+0xFF252B21,
+0xFF2B2E1B,
+0xFF302A12,
+0xFF48422A,
+0xFF252614,
+0xFF403E2F,
+0xFF413527,
+0xFF5F3328,
+0xFF75120C,
+0xFF720905,
+0xFF682B26,
+0xFF5F3E1D,
+0xFF624C00,
+0xFFF3E163,
+0xFFE1D239,
+0xFFB4A526,
+0xFF6A5C2B,
+0xFF4C4236,
+0xFF4D4A37,
+0xFF494834,
+0xFF241E0E,
+0xFF30281B,
+0xFF3F372C,
+0xFF453F33,
+0xFF2C2D1D,
+0xFF181B0A,
+0xFF252719,
+0xFF212413,
+0xFF3C4029,
+0xFF484A32,
+0xFF37321C,
+0xFF635D47,
+0xFF48422A,
+0xFF3F3921,
+0xFF33311A,
+0xFF38341B,
+0xFF423419,
+0xFF604D2D,
+0xFF6C5837,
+0xFF5B4A2C,
+0xFF3B301A,
+0xFF534737,
+0xFF543E30,
+0xFF462F21,
+0xFF4D3C2A,
+0xFF4C402A,
+0xFF3B3418,
+0xFF423E23,
+0xFF35341F,
+0xFF4A4A3E,
+0xFFDADCDB,
+0xFFE1E2E7,
+0xFFE2E1E6,
+0xFF575652,
+0xFF63604D,
+0xFF696446,
+0xFF645C38,
+0xFF796F4B,
+0xFF57492C,
+0xFF6E6046,
+0xFF463E27,
+0xFF746D5A,
+0xFF3C3724,
+0xFF413C29,
+0xFF777461,
+0xFF3A3724,
+0xFF312E1B,
+0xFF43402D,
+0xFF443F29,
+0xFF89816A,
+0xFF50442A,
+0xFF524427,
+0xFF615032,
+0xFF766142,
+0xFF695233,
+0xFF665136,
+0xFF483924,
+0xFF645945,
+0xFF817662,
+0xFF5A4F39,
+0xFF5E523A,
+0xFF594930,
+0xFF76624A,
+0xFF6D5740,
+0xFF6D573F,
+0xFF5B472F,
+0xFF675740,
+0xFF5A4935,
+0xFF61503E,
+0xFF635041,
+0xFF543C30,
+0xFF51352A,
+0xFF4A291A,
+0xFF593827,
+0xFF583C2E,
+0xFF5B4537,
+0xFF5D4C3C,
+0xFF63503F,
+0xFF675139,
+0xFFB6A186,
+0xFF4F3F26,
+0xFF4B3B22,
+0xFF56452B,
+0xFF47331A,
+0xFF45331B,
+0xFF4B3921,
+0xFF544027,
+0xFF59452C,
+0xFF5F4439,
+0xFF53382D,
+0xFF563B30,
+0xFF50352C,
+0xFF573C33,
+0xFF5C4138,
+0xFF593E33,
+0xFF503429,
+0xFF593D31,
+0xFF5E4234,
+0xFF5A3E30,
+0xFF624535,
+0xFF624537,
+0xFF56392B,
+0xFF67473C,
+0xFF54362B,
+0xFF6A4D3F,
+0xFF593C2E,
+0xFF6C4C3D,
+0xFF60412F,
+0xFF5F432E,
+0xFF644832,
+0xFF6B4C37,
+0xFF70513C,
+0xFF664A34,
+0xFF664830,
+0xFF69452F,
+0xFF744E39,
+0xFF69432E,
+0xFF734F39,
+0xFF704C36,
+0xFF77513C,
+0xFF6F4934,
+0xFF724C37,
+0xFF75513B,
+0xFF68452F,
+0xFF78553F,
+0xFF795640,
+0xFF845F4C,
+0xFF714C3A,
+0xFF795643,
+0xFF543020,
+0xFF664536,
+0xFF715041,
+0xFF6A4938,
+0xFF704F3E,
+0xFF755141,
+0xFF745342,
+0xFF715240,
+0xFF6C4D3B,
+0xFF634231,
+0xFF6E4A3A,
+0xFF6F4B3B,
+0xFF73503D,
+0xFF704F3C,
+0xFF7D5D48,
+0xFF71523D,
+0xFF81624E,
+0xFF664532,
+0xFF775343,
+0xFF7E5A4A,
+0xFF775645,
+0xFF755546,
+0xFF775647,
+0xFF744F3F,
+0xFF6E4937,
+0xFF785843,
+0xFF7B5F47,
+0xFF765B40,
+0xFF9B7D65,
+0xFF7A5744,
+0xFF805C4C,
+0xFF896857,
+0xFF8B6C58,
+0xFF80664F,
+0xFF806B4E,
+0xFFAA9578,
+0xFF8E7755,
+0xFFA28B5F,
+0xFF997E4F,
+0xFF8F7246,
+0xFF8D7245,
+0xFF937F4A,
+0xFF887C4A,
+0xFF9A9673,
+0xFF403E31,
+0xFF373646,
+0xFF383958,
+0xFF1D1F45,
+0xFF34385B,
+0xFF333855,
+0xFF0D1329,
+0xFF000216,
+0xFF4A4F65,
+0xFF373B58,
+0xFF10142F,
+0xFF000412,
+0xFF080C17,
+0xFF191B2A,
+0xFF202133,
+0xFF36394C,
+0xFF2E3346,
+0xFF192032,
+0xFF040C19,
+0xFF050E15,
+0xFF090909,
+0xFF1C0E03,
+0xFF5B4837,
+0xFF3E2B1A,
+0xFF635240,
+0xFF271803,
+0xFF3A2E18,
+0xFF261B07,
+0xFF392C19,
+0xFF5F4D37,
+0xFF5A462D,
+0xFF574426,
+0xFF40290A,
+0xFF775A3A,
+0xFF6C4E2C,
+0xFF68492A,
+0xFF634628,
+0xFF503919,
+0xFF5A4528,
+0xFF47331B,
+0xFF55432F,
+0xFF3E311E,
+0xFF53442F,
+0xFFEBD3BB,
+0xFFAC8E76,
+0xFF573B26,
+0xFF583C27,
+0xFF4D2D18,
+0xFF6D5139,
+0xFF59482A,
+0xFF463B1D,
+0xFF453921,
+0xFF463722,
+0xFF2C1A04,
+0xFF543C24,
+0xFF6A482C,
+0xFF8F6E4F,
+0xFF6F5532,
+0xFF6F5836,
+0xFF3B2B09,
+0xFF635636,
+0xFF423B1F,
+0xFF544F39,
+0xFF241D0D,
+0xFF4B4338,
+0xFF302A1E,
+0xFF181204,
+0xFF423B2B,
+0xFF4D4230,
+0xFF4B3B2B,
+0xFF786956,
+0xFF554D3A,
+0xFF2B2412,
+0xFF463D2E,
+0xFF3E362B,
+0xFF2B2620,
+0xFF201D16,
+0xFF3A332B,
+0xFF342E22,
+0xFF3B3829,
+0xFF403F2D,
+0xFF302F1D,
+0xFF3A3728,
+0xFF312B1F,
+0xFF4F473C,
+0xFF473E35,
+0xFF2C231A,
+0xFF464034,
+0xFF2A2418,
+0xFF41392C,
+0xFF645D4D,
+0xFF362F1C,
+0xFF322A13,
+0xFF645D40,
+0xFF595031,
+0xFF3B3010,
+0xFF675C3C,
+0xFF504728,
+0xFF51482B,
+0xFF322B0E,
+0xFF4C4727,
+0xFF4E4A25,
+0xFF5F5A34,
+0xFF574E2D,
+0xFF66583B,
+0xFF64543D,
+0xFF4E3E27,
+0xFF665939,
+0xFF6E613E,
+0xFF7C6C48,
+0xFF4F3E20,
+0xFF342812,
+0xFF4E3E25,
+0xFF8F734C,
+0xFFC1A073,
+0xFF9D7C4F,
+0xFF6C4B20,
+0xFF79582F,
+0xFF8D6A44,
+0xFFA2795B,
+0xFF8F6648,
+0xFF9F7B57,
+0xFF644A29,
+0xFFB9AE9A,
+0xFFF4F4EC,
+0xFFEDF1F4,
+0xFFB6B7B9,
+0xFF4F4B40,
+0xFF342D1A,
+0xFF352E1B,
+0xFF3B3623,
+0xFF312F23,
+0xFF413F33,
+0xFF3D3727,
+0xFF532D20,
+0xFF7F221B,
+0xFF821E1C,
+0xFF6A3531,
+0xFF4E320B,
+0xFF846D05,
+0xFFCFBD35,
+0xFFE3D550,
+0xFF7B6F09,
+0xFF7F784C,
+0xFF393323,
+0xFF4E4935,
+0xFF494633,
+0xFF2F3022,
+0xFF28281C,
+0xFF383629,
+0xFF3D3B2E,
+0xFF333426,
+0xFF18190B,
+0xFF242015,
+0xFF171307,
+0xFF3D3A27,
+0xFF423D27,
+0xFF4A442C,
+0xFF554B32,
+0xFF5C5036,
+0xFF4E4228,
+0xFF382C14,
+0xFF403218,
+0xFF433319,
+0xFF6B5C3F,
+0xFF605333,
+0xFF574C30,
+0xFF504531,
+0xFF43392D,
+0xFF41342E,
+0xFF291C16,
+0xFF413A2A,
+0xFF48462F,
+0xFF2D2D15,
+0xFF343620,
+0xFF303320,
+0xFF353729,
+0xFF84867B,
+0xFFA2A298,
+0xFF848075,
+0xFF3D3624,
+0xFF696246,
+0xFF726948,
+0xFF6B633F,
+0xFF746C48,
+0xFF504A2A,
+0xFF625D40,
+0xFF3C381F,
+0xFF6F6D56,
+0xFF272510,
+0xFF2C2916,
+0xFF6F6E5C,
+0xFF262513,
+0xFF282514,
+0xFF363320,
+0xFF37321C,
+0xFF817B61,
+0xFF43391E,
+0xFF4C4125,
+0xFF56482D,
+0xFF5B4B32,
+0xFF5E4C36,
+0xFF63533C,
+0xFF4F432B,
+0xFF675D44,
+0xFF93876F,
+0xFF6C5D46,
+0xFF615137,
+0xFF5C4B31,
+0xFF5A4530,
+0xFF6D5843,
+0xFF665239,
+0xFF6F5B43,
+0xFF4A3726,
+0xFF544333,
+0xFF635240,
+0xFF584838,
+0xFF544234,
+0xFF594638,
+0xFF452B1C,
+0xFF4A2F1E,
+0xFF553C28,
+0xFF59432E,
+0xFF47301E,
+0xFF48311F,
+0xFF684F3B,
+0xFFAE957F,
+0xFF644F34,
+0xFF756041,
+0xFF7D6646,
+0xFF887151,
+0xFF7B6444,
+0xFF87704E,
+0xFF9C855C,
+0xFFA38C62,
+0xFF5C4136,
+0xFF4A2F24,
+0xFF563B30,
+0xFF50352A,
+0xFF573C33,
+0xFF4D3126,
+0xFF54382D,
+0xFF5C3E33,
+0xFF55382A,
+0xFF563929,
+0xFF533626,
+0xFF634334,
+0xFF6C4C3D,
+0xFF613F33,
+0xFF725044,
+0xFF613F33,
+0xFF5F3F32,
+0xFF5E3E2F,
+0xFF694434,
+0xFF5B3624,
+0xFF563621,
+0xFF63432E,
+0xFF65422C,
+0xFF6F4F38,
+0xFF6A4C34,
+0xFF64442D,
+0xFF704733,
+0xFF734835,
+0xFF6E4531,
+0xFF704731,
+0xFF6D442E,
+0xFF6C432D,
+0xFF744B35,
+0xFF774E38,
+0xFF765039,
+0xFF613B24,
+0xFF603C24,
+0xFF77533D,
+0xFF6C4832,
+0xFF704C36,
+0xFF704B38,
+0xFF77523F,
+0xFF684331,
+0xFF6E4937,
+0xFF775240,
+0xFF724B3A,
+0xFF7E5746,
+0xFF6A4533,
+0xFF6F4C39,
+0xFF724F3B,
+0xFF76513E,
+0xFF78523F,
+0xFF764D3B,
+0xFF7E5541,
+0xFF6B4530,
+0xFF78543C,
+0xFF734F39,
+0xFF88644E,
+0xFF7E5A44,
+0xFF7D5742,
+0xFF79533E,
+0xFF7A5441,
+0xFF7C5341,
+0xFF79503E,
+0xFF7F5141,
+0xFF744936,
+0xFF7D5740,
+0xFF775339,
+0xFF785539,
+0xFF8C664F,
+0xFF693F2F,
+0xFF85594C,
+0xFF845949,
+0xFF7E5843,
+0xFF745236,
+0xFF7C5E3C,
+0xFFA1835F,
+0xFF8E7147,
+0xFF8C6C3D,
+0xFF886837,
+0xFF886839,
+0xFFA88C5D,
+0xFF8E774B,
+0xFF776942,
+0xFF7A725B,
+0xFF4F4C47,
+0xFF343547,
+0xFF333655,
+0xFF2D3156,
+0xFF3D4166,
+0xFF242946,
+0xFF080E24,
+0xFF12172B,
+0xFF43485C,
+0xFF1D213A,
+0xFF050A20,
+0xFF1F2535,
+0xFF323544,
+0xFF313244,
+0xFF2E2F41,
+0xFF2E3144,
+0xFF252A3D,
+0xFF0A1121,
+0xFF040C19,
+0xFF09101A,
+0xFF0F0B0C,
+0xFF351D11,
+0xFFA48571,
+0xFF9E826D,
+0xFF9F8670,
+0xFF897459,
+0xFF877255,
+0xFF7D674F,
+0xFF897159,
+0xFF8F7159,
+0xFF816246,
+0xFF6E5133,
+0xFF836644,
+0xFF6C4A27,
+0xFF734F2D,
+0xFF633F1D,
+0xFF775635,
+0xFF634626,
+0xFF593E21,
+0xFF5B3F27,
+0xFF583E27,
+0xFF432F17,
+0xFF432B13,
+0xFF8A664C,
+0xFFDDB59B,
+0xFFC19B84,
+0xFF916852,
+0xFF7A4D36,
+0xFF6F452C,
+0xFF533417,
+0xFF695032,
+0xFF432B13,
+0xFF6C523B,
+0xFF6F533B,
+0xFF765438,
+0xFF795030,
+0xFF714B27,
+0xFF4F3510,
+0xFF4B3510,
+0xFF503C1B,
+0xFF7E6D51,
+0xFF40341A,
+0xFF4A3F2B,
+0xFF302416,
+0xFF44382C,
+0xFF362C20,
+0xFF211809,
+0xFF3E3121,
+0xFF5D4D3D,
+0xFF66513E,
+0xFF7A6854,
+0xFF463926,
+0xFF2A220D,
+0xFF453C2B,
+0xFF32291A,
+0xFF1E180C,
+0xFF372E25,
+0xFF382E24,
+0xFF2C2012,
+0xFF2F2615,
+0xFF312A17,
+0xFF2F2A16,
+0xFF3B3421,
+0xFF2C2010,
+0xFF4B3D30,
+0xFF3B2D20,
+0xFF322618,
+0xFF393021,
+0xFF3E3526,
+0xFF413525,
+0xFF4F4231,
+0xFF41321F,
+0xFF55462F,
+0xFF5D4D33,
+0xFF5B4A2E,
+0xFF503F21,
+0xFF7A694B,
+0xFF5E4F30,
+0xFF635636,
+0xFF554828,
+0xFF483E1B,
+0xFF3C320E,
+0xFF796D47,
+0xFF6B5B39,
+0xFF7A6747,
+0xFF7C644A,
+0xFF685034,
+0xFF6C5C3B,
+0xFF70603C,
+0xFF79633C,
+0xFF836C4A,
+0xFF2F1F05,
+0xFF887557,
+0xFFC5A67A,
+0xFFBA9463,
+0xFF885E34,
+0xFF794F27,
+0xFF845D32,
+0xFF8B6139,
+0xFF7D4F2E,
+0xFF6A3D1E,
+0xFF6D4424,
+0xFF65482A,
+0xFFAA9F8B,
+0xFFEEEEE4,
+0xFFEFEFEF,
+0xFFB7B6B2,
+0xFF4F4734,
+0xFF453921,
+0xFF453825,
+0xFF423626,
+0xFF372D21,
+0xFF3C3427,
+0xFF2D2413,
+0xFF3E1D0E,
+0xFF520200,
+0xFF580300,
+0xFF52271E,
+0xFF4A3405,
+0xFFA48E17,
+0xFFCFBA2D,
+0xFFAD9C2A,
+0xFF504500,
+0xFF65613B,
+0xFF4D4A39,
+0xFF3D3825,
+0xFF262010,
+0xFF313224,
+0xFF262719,
+0xFF403D2E,
+0xFF3E3B2C,
+0xFF29271A,
+0xFF28261A,
+0xFF373028,
+0xFF261D14,
+0xFF342D1D,
+0xFF2F2913,
+0xFF4C4229,
+0xFF675C40,
+0xFF5F5033,
+0xFF584527,
+0xFF614D32,
+0xFF655138,
+0xFF634F34,
+0xFF77664A,
+0xFF5D4F32,
+0xFF4F4428,
+0xFF4A3F29,
+0xFF271E0F,
+0xFF1F140E,
+0xFF1B120D,
+0xFF201D0E,
+0xFF282A15,
+0xFF353823,
+0xFF3B3E29,
+0xFF363928,
+0xFF3D402F,
+0xFF585649,
+0xFF605D4E,
+0xFF645C49,
+0xFF776D54,
+0xFF84795B,
+0xFF786E4B,
+0xFF5D5531,
+0xFF6E6846,
+0xFF423D1F,
+0xFF4A492D,
+0xFF2C2C14,
+0xFF72715D,
+0xFF242311,
+0xFF292718,
+0xFF737164,
+0xFF232114,
+0xFF242112,
+0xFF3D3A29,
+0xFF332E1A,
+0xFF706C53,
+0xFF40391D,
+0xFF544A2F,
+0xFF4A3E24,
+0xFF41321B,
+0xFF51422F,
+0xFF675843,
+0xFF55492F,
+0xFF6C6145,
+0xFF92846A,
+0xFF615138,
+0xFF5B4A2C,
+0xFF574426,
+0xFF614B34,
+0xFF57412A,
+0xFF6F5A3D,
+0xFF675235,
+0xFF513B24,
+0xFF5F4934,
+0xFF443018,
+0xFF5F4D35,
+0xFF503E28,
+0xFF5C4732,
+0xFF4E351F,
+0xFF533920,
+0xFF6E5439,
+0xFF745A3F,
+0xFF896F56,
+0xFF927861,
+0xFFA48A73,
+0xFFA99177,
+0xFF9E8566,
+0xFFC3AC8A,
+0xFF99835E,
+0xFFB59F78,
+0xFF9F8962,
+0xFFB9A37A,
+0xFFB9A477,
+0xFFAA9664,
+0xFF61473A,
+0xFF4F3528,
+0xFF583C30,
+0xFF583C30,
+0xFF61453A,
+0xFF5B3D32,
+0xFF583A2F,
+0xFF68483B,
+0xFF4F2F20,
+0xFF664735,
+0xFF614230,
+0xFF775645,
+0xFF61402F,
+0xFF745042,
+0xFF664234,
+0xFF704C3E,
+0xFF644032,
+0xFF6B4636,
+0xFF6A3E31,
+0xFF704535,
+0xFF76503D,
+0xFF724C37,
+0xFF79533E,
+0xFF87634D,
+0xFF74543D,
+0xFF66432D,
+0xFF7B503D,
+0xFF724331,
+0xFF724530,
+0xFF7F553F,
+0xFF845A42,
+0xFF794F37,
+0xFF835941,
+0xFF865C44,
+0xFF784E36,
+0xFF7B5139,
+0xFF6B4129,
+0xFF6C432D,
+0xFF6B422C,
+0xFF714B34,
+0xFF6A442D,
+0xFF603721,
+0xFF704731,
+0xFF764C36,
+0xFF744A34,
+0xFF6C422C,
+0xFF714731,
+0xFF6F452F,
+0xFF7B513B,
+0xFF774D35,
+0xFF6E442C,
+0xFF744A32,
+0xFF744730,
+0xFF784C33,
+0xFF81533B,
+0xFF76482E,
+0xFF764830,
+0xFF8D6148,
+0xFF7C5239,
+0xFF7C543A,
+0xFF835B41,
+0xFF7A5038,
+0xFF764932,
+0xFF7A4D38,
+0xFF7A4C3D,
+0xFF764B3B,
+0xFF7E5543,
+0xFF7D5440,
+0xFF875C49,
+0xFF815441,
+0xFF724333,
+0xFF8B5C4C,
+0xFF835345,
+0xFF855747,
+0xFF79503A,
+0xFF774F35,
+0xFF79532F,
+0xFF967147,
+0xFF82592D,
+0xFF8F6B39,
+0xFF9F814B,
+0xFFA08A59,
+0xFF9B886A,
+0xFF7F7166,
+0xFF6A6068,
+0xFF4B485B,
+0xFF3A3A54,
+0xFF2D314E,
+0xFF2D324F,
+0xFF2A304A,
+0xFF1E223B,
+0xFF10152B,
+0xFF181D31,
+0xFF41465C,
+0xFF21253E,
+0xFF20243D,
+0xFF1D1F38,
+0xFF191931,
+0xFF09071C,
+0xFF0B0A1A,
+0xFF0C0B19,
+0xFF131521,
+0xFF121622,
+0xFF212330,
+0xFF141321,
+0xFF080003,
+0xFF47291F,
+0xFFA8826F,
+0xFFB7937D,
+0xFF9D7B60,
+0xFFA58667,
+0xFFA17E5E,
+0xFF9E7758,
+0xFFB4886D,
+0xFFAA7B5F,
+0xFF9C6D51,
+0xFFA07354,
+0xFFA47758,
+0xFFA77958,
+0xFF8E603F,
+0xFF704221,
+0xFF784B2C,
+0xFF9F7658,
+0xFF997052,
+0xFF9A7155,
+0xFF9A7155,
+0xFF9E765C,
+0xFF9B7457,
+0xFF9C6F50,
+0xFF9B6C4E,
+0xFFA97B61,
+0xFF8E5F45,
+0xFFA46E54,
+0xFF855031,
+0xFF835031,
+0xFF936446,
+0xFF8C5C45,
+0xFFA97B63,
+0xFF9F7056,
+0xFF8E6142,
+0xFF9B6F4A,
+0xFF856238,
+0xFF6B5428,
+0xFF655228,
+0xFF4A2D0B,
+0xFF725337,
+0xFF70563D,
+0xFF644E37,
+0xFF644D3B,
+0xFF6A5343,
+0xFF442F1E,
+0xFF402B18,
+0xFF57422D,
+0xFF644E37,
+0xFF644B35,
+0xFF463018,
+0xFF524229,
+0xFF362A12,
+0xFF4B4128,
+0xFF4B402A,
+0xFF5D523C,
+0xFF4E422C,
+0xFF54422E,
+0xFF3E2914,
+0xFF45331B,
+0xFF54422A,
+0xFF58472D,
+0xFF5D4930,
+0xFF4D351D,
+0xFF7D654D,
+0xFF472F17,
+0xFF331F07,
+0xFF3C2A12,
+0xFF3B2B12,
+0xFF503E26,
+0xFF553F28,
+0xFF51351F,
+0xFF664830,
+0xFF573921,
+0xFF6F5137,
+0xFF67492F,
+0xFF7F6145,
+0xFF876C4E,
+0xFF937A5B,
+0xFF765E3C,
+0xFF4C3513,
+0xFF5D4624,
+0xFF89714F,
+0xFF846A49,
+0xFFA28567,
+0xFF7C5D40,
+0xFF6D4E32,
+0xFF765C41,
+0xFF5E4527,
+0xFF927150,
+0xFF755431,
+0xFFA78A6C,
+0xFF6F512F,
+0xFF8F693C,
+0xFFC19564,
+0xFF926339,
+0xFF976741,
+0xFF7E502C,
+0xFF906240,
+0xFF936242,
+0xFFA17254,
+0xFF794C2D,
+0xFF7C583E,
+0xFFCDBCA8,
+0xFFFBF4E4,
+0xFFF4EDE3,
+0xFFC8C1B1,
+0xFF65573A,
+0xFF5F4F2D,
+0xFF5B452D,
+0xFF4C331F,
+0xFF3D2314,
+0xFF432C1C,
+0xFF341F0C,
+0xFF401F0E,
+0xFF420600,
+0xFF460A00,
+0xFF472A18,
+0xFF3D2C00,
+0xFFC7AE30,
+0xFFC9AE23,
+0xFFAC9535,
+0xFF433300,
+0xFF676043,
+0xFF3B3829,
+0xFF3D352A,
+0xFF20180D,
+0xFF2D271B,
+0xFF403A2A,
+0xFF5B503C,
+0xFF4B402E,
+0xFF271F12,
+0xFF2E271D,
+0xFF3F362F,
+0xFF241B12,
+0xFF181101,
+0xFF2E2611,
+0xFF594D33,
+0xFF56472A,
+0xFF6B5838,
+0xFF543D1D,
+0xFF644B2D,
+0xFF705739,
+0xFF4D3318,
+0xFF7B6445,
+0xFF5E4B2B,
+0xFF463517,
+0xFF4F4126,
+0xFF31250D,
+0xFF180C00,
+0xFF181101,
+0xFF1D1A09,
+0xFF272612,
+0xFF393B26,
+0xFF32341F,
+0xFF303121,
+0xFF413F30,
+0xFF464034,
+0xFF554B3F,
+0xFF6D604F,
+0xFF897A63,
+0xFF96876A,
+0xFF766949,
+0xFF695E3E,
+0xFF666040,
+0xFF3F3B1E,
+0xFF56543D,
+0xFF201F0D,
+0xFF616155,
+0xFF222218,
+0xFF32322A,
+0xFF74746C,
+0xFF202018,
+0xFF1B180F,
+0xFF333124,
+0xFF312E1B,
+0xFF6F6A54,
+0xFF3D371D,
+0xFF463F23,
+0xFF43391E,
+0xFF3B2F17,
+0xFF584C36,
+0xFF564732,
+0xFF504228,
+0xFF55452B,
+0xFF9E8C74,
+0xFF57432A,
+0xFF564122,
+0xFF654E2E,
+0xFF6C5237,
+0xFF6F5638,
+0xFF896F4C,
+0xFF836742,
+0xFF876A4A,
+0xFF9B7E5E,
+0xFFA58866,
+0xFFA98F6A,
+0xFFAC926F,
+0xFFB99C7A,
+0xFFB79771,
+0xFFC2A07A,
+0xFFC8A882,
+0xFFCAAC86,
+0xFFCAAC88,
+0xFFB89C77,
+0xFFBBA17E,
+0xFFAA926E,
+0xFF96805B,
+0xFFB19D78,
+0xFF715F37,
+0xFF95835B,
+0xFF8F8057,
+0xFF928358,
+0xFF807146,
+0xFF8C7E51,
+0xFF52382B,
+0xFF543A2D,
+0xFF593D31,
+0xFF492D21,
+0xFF5C3E33,
+0xFF624235,
+0xFF523225,
+0xFF4F2E1F,
+0xFF735241,
+0xFF6E4D3A,
+0xFF623F2C,
+0xFF74513E,
+0xFF65422F,
+0xFF73503D,
+0xFF654131,
+0xFF654131,
+0xFF684333,
+0xFF835949,
+0xFF754738,
+0xFF754737,
+0xFF784D3A,
+0xFF8A614D,
+0xFF774E3A,
+0xFF9E7863,
+0xFF7B5842,
+0xFF78553F,
+0xFF704532,
+0xFF885947,
+0xFF7A4D38,
+0xFF90664E,
+0xFF6E462C,
+0xFF875F45,
+0xFF7F573D,
+0xFF956B52,
+0xFF966952,
+0xFF82563D,
+0xFF875942,
+0xFF7D5138,
+0xFF865C43,
+0xFF774F35,
+0xFF886046,
+0xFF7B5138,
+0xFF855940,
+0xFF865840,
+0xFF7E4E37,
+0xFF82543C,
+0xFF80543B,
+0xFF855940,
+0xFF7A4B31,
+0xFF815238,
+0xFF77492F,
+0xFF895B41,
+0xFF794A2E,
+0xFF825035,
+0xFF9C664A,
+0xFF8A5438,
+0xFF925F42,
+0xFF976648,
+0xFF845738,
+0xFF855A3A,
+0xFF885C3F,
+0xFF7A4E31,
+0xFF7C4D31,
+0xFF7D4D36,
+0xFF7C4D3B,
+0xFF744535,
+0xFF805340,
+0xFF82553E,
+0xFF8D5F48,
+0xFF8D5D47,
+0xFF87543F,
+0xFF7B4732,
+0xFF8A5742,
+0xFF885842,
+0xFF83543A,
+0xFF7B4C2E,
+0xFFA57753,
+0xFFA07349,
+0xFF8A6030,
+0xFFB69260,
+0xFF9C834D,
+0xFF7F6D45,
+0xFF6E5E51,
+0xFF352933,
+0xFF362D4A,
+0xFF403C5F,
+0xFF434463,
+0xFF2A2E49,
+0xFF32384E,
+0xFF2E3547,
+0xFF202538,
+0xFF181D30,
+0xFF0C1127,
+0xFF343851,
+0xFF30344F,
+0xFF333754,
+0xFF303150,
+0xFF262743,
+0xFF2A283E,
+0xFF2B2A3A,
+0xFF21202E,
+0xFF1C1C28,
+0xFF222433,
+0xFF201F2F,
+0xFF15111F,
+0xFF0E0002,
+0xFF6D4B3F,
+0xFF91674F,
+0xFFA78063,
+0xFFA37F5F,
+0xFF8C6642,
+0xFF845C38,
+0xFF976646,
+0xFFB37E5E,
+0xFFA56E50,
+0xFF9C6547,
+0xFF8E593A,
+0xFFA06B4C,
+0xFF9A6546,
+0xFF9E694A,
+0xFFAB7859,
+0xFFA16E4F,
+0xFF744325,
+0xFF815234,
+0xFF936446,
+0xFF9A6D4C,
+0xFF815433,
+0xFF8E6140,
+0xFF885736,
+0xFFA37051,
+0xFF6A371A,
+0xFF7D472B,
+0xFFA66B4D,
+0xFF925737,
+0xFF885230,
+0xFF9B6946,
+0xFF895A3C,
+0xFF98694B,
+0xFF8D5C3C,
+0xFF9A6A46,
+0xFF8A5D34,
+0xFF9D7B4D,
+0xFF685223,
+0xFF5F4A1D,
+0xFF704F2C,
+0xFF987356,
+0xFF9F7D61,
+0xFFA38468,
+0xFF9F8169,
+0xFF9D7F67,
+0xFF997A65,
+0xFF9B7D65,
+0xFFA28269,
+0xFF9D7D64,
+0xFF947559,
+0xFF9C7E62,
+0xFF9A8266,
+0xFF907D5F,
+0xFF918064,
+0xFF948365,
+0xFFA99978,
+0xFF917E5E,
+0xFF9B8264,
+0xFF9F8467,
+0xFFA18367,
+0xFF9E8064,
+0xFFB19275,
+0xFFAE8C70,
+0xFFA98467,
+0xFF987152,
+0xFF957151,
+0xFF987756,
+0xFF836646,
+0xFFA18466,
+0xFF9C7D61,
+0xFF9C7A5F,
+0xFFA57D63,
+0xFFA37960,
+0xFFA17960,
+0xFFA77F66,
+0xFFA17C61,
+0xFFAB886A,
+0xFF8B6848,
+0xFFA58461,
+0xFF927450,
+0xFF947652,
+0xFFA38563,
+0xFFA38563,
+0xFFA68564,
+0xFFAC8B6A,
+0xFF9F7C5C,
+0xFF9C7B5A,
+0xFF957A5C,
+0xFF9E8365,
+0xFFB18D6B,
+0xFF97734F,
+0xFFAC8B68,
+0xFFAC8C65,
+0xFF936A3C,
+0xFF9C7240,
+0xFF9B7141,
+0xFF9B7045,
+0xFF976D47,
+0xFF916643,
+0xFF825734,
+0xFF865E3B,
+0xFF8F6847,
+0xFFB19474,
+0xFFA7967C,
+0xFF877D64,
+0xFFA69F85,
+0xFF9A9172,
+0xFF8A7B52,
+0xFF846D44,
+0xFF896A4D,
+0xFF85634A,
+0xFF8C6A51,
+0xFF73533C,
+0xFF704F3C,
+0xFF4B2413,
+0xFF3A0200,
+0xFF461300,
+0xFF59411D,
+0xFF918134,
+0xFFE8D143,
+0xFFD4BA29,
+0xFF78600A,
+0xFF4F3D0D,
+0xFF6D6447,
+0xFF231E0A,
+0xFF393021,
+0xFF2C2314,
+0xFF2F2815,
+0xFF423A25,
+0xFF50442C,
+0xFF443822,
+0xFF32291A,
+0xFF30281D,
+0xFF3D3327,
+0xFF413525,
+0xFF362A14,
+0xFF524429,
+0xFF7B6A4C,
+0xFF614D2A,
+0xFF644C26,
+0xFF5F4520,
+0xFF6A4D2B,
+0xFF654826,
+0xFF593E20,
+0xFF6A4F31,
+0xFF6E5536,
+0xFF756041,
+0xFF6E5B3D,
+0xFF6A593D,
+0xFF584630,
+0xFF31200C,
+0xFF201500,
+0xFF322A15,
+0xFF37321C,
+0xFF383621,
+0xFF393623,
+0xFF383526,
+0xFF2A2418,
+0xFF2B2316,
+0xFF6B5F4F,
+0xFF867762,
+0xFF928268,
+0xFF7D6E4F,
+0xFF6E5F40,
+0xFF776A4A,
+0xFF4B4024,
+0xFF514A30,
+0xFF201907,
+0xFF645E50,
+0xFF251E14,
+0xFF3A3329,
+0xFF756E66,
+0xFF181107,
+0xFF140C01,
+0xFF3B3422,
+0xFF463E27,
+0xFF8A8367,
+0xFF544B2C,
+0xFF3D3212,
+0xFF3F3212,
+0xFF594A2B,
+0xFF756649,
+0xFF867559,
+0xFF928163,
+0xFF9F8C6E,
+0xFFB7A287,
+0xFFB19A7B,
+0xFFA8916F,
+0xFFC3AB87,
+0xFFC9AF8E,
+0xFFC9AF8C,
+0xFFC7AB83,
+0xFFD0B389,
+0xFFCCAF87,
+0xFFC9AC84,
+0xFFCFB286,
+0xFFC9AC80,
+0xFFC8AB81,
+0xFFCCAF85,
+0xFFC4A579,
+0xFFBE9F73,
+0xFF9C7C53,
+0xFF9F8258,
+0xFF977C51,
+0xFFAC9468,
+0xFFA0895F,
+0xFF9E895E,
+0xFF7D6A42,
+0xFF8C7951,
+0xFF503E16,
+0xFF85734B,
+0xFF78673C,
+0xFF837247,
+0xFF79673F,
+0xFF7E6F48,
+0xFF4B3122,
+0xFF4C3223,
+0xFF44281A,
+0xFF482C1E,
+0xFF4A2D1F,
+0xFF523225,
+0xFF4D2C1D,
+0xFF795545,
+0xFF603D2A,
+0xFF54311D,
+0xFF7F5A47,
+0xFF714E3A,
+0xFF4F2C18,
+0xFF724F3B,
+0xFF583522,
+0xFF6E4B38,
+0xFF542F1D,
+0xFF58321F,
+0xFF693E2D,
+0xFF6F4431,
+0xFF744B37,
+0xFF714B36,
+0xFF704A35,
+0xFF66422C,
+0xFF5B3B26,
+0xFF70503B,
+0xFF623925,
+0xFF6F4431,
+0xFF5E351F,
+0xFF805B41,
+0xFF735034,
+0xFF6E4B2D,
+0xFF593417,
+0xFF7D5639,
+0xFF7C4E36,
+0xFF95674D,
+0xFF93634C,
+0xFF8D5F45,
+0xFF855C40,
+0xFF855E41,
+0xFF8C6546,
+0xFF896042,
+0xFF86573B,
+0xFF845237,
+0xFF9B6A4C,
+0xFF966749,
+0xFF76492A,
+0xFF885B3C,
+0xFF905E43,
+0xFF89563B,
+0xFF855436,
+0xFF976648,
+0xFF875435,
+0xFF9B6647,
+0xFF8F5638,
+0xFF9E6547,
+0xFF9D6647,
+0xFFA26D4D,
+0xFF9E704F,
+0xFF845736,
+0xFF986B4A,
+0xFF8E6140,
+0xFF89583A,
+0xFF8B583D,
+0xFF9E6752,
+0xFF89553F,
+0xFF9C6D51,
+0xFF986B4A,
+0xFF8D5C3B,
+0xFFA06E4D,
+0xFF956041,
+0xFF996244,
+0xFF9D6848,
+0xFFA36F4A,
+0xFFA57048,
+0xFFAC774D,
+0xFFA06B41,
+0xFFA27242,
+0xFFAD864D,
+0xFF987B43,
+0xFFCEBB93,
+0xFF615441,
+0xFF22171F,
+0xFF342B48,
+0xFF28234B,
+0xFF212048,
+0xFF161A37,
+0xFF0B1127,
+0xFF242A3A,
+0xFF3E4452,
+0xFF1F2231,
+0xFF191C2D,
+0xFF15172C,
+0xFF3E425D,
+0xFF3F4263,
+0xFF2C3053,
+0xFF303553,
+0xFF252B45,
+0xFF272940,
+0xFF232639,
+0xFF272A3D,
+0xFF2E3144,
+0xFF313447,
+0xFF131426,
+0xFF0A0813,
+0xFF0C0000,
+0xFF896950,
+0xFFA78059,
+0xFFB48E67,
+0xFFBF9974,
+0xFF906845,
+0xFFA67B59,
+0xFFB88766,
+0xFFAE7C59,
+0xFFA46F4F,
+0xFFA67151,
+0xFFA26B4C,
+0xFF9A6344,
+0xFF996244,
+0xFF7F4A2B,
+0xFF986548,
+0xFF865336,
+0xFF623111,
+0xFF805231,
+0xFF996E4C,
+0xFFA57D59,
+0xFF8F6743,
+0xFF916945,
+0xFF9E704E,
+0xFF7C4727,
+0xFF7F4629,
+0xFF8A4D31,
+0xFF985B3C,
+0xFF9C6642,
+0xFFAD8057,
+0xFF937046,
+0xFFA88C64,
+0xFF82663F,
+0xFF9C7953,
+0xFF977049,
+0xFF986E44,
+0xFF795427,
+0xFF7F6437,
+0xFF725A2E,
+0xFF93714C,
+0xFF9A7654,
+0xFFAC8866,
+0xFFA07D5D,
+0xFFA98867,
+0xFF9E7B5B,
+0xFFA27D60,
+0xFFA57E5F,
+0xFFAC8365,
+0xFFB4886B,
+0xFFAC8365,
+0xFF9F7658,
+0xFFA67F60,
+0xFF9B7858,
+0xFFAF916F,
+0xFF8F734E,
+0xFF978057,
+0xFF9B8259,
+0xFFAC8C66,
+0xFFA88462,
+0xFFAB8463,
+0xFFB28969,
+0xFFAA7D5C,
+0xFFB07F5E,
+0xFFBA8563,
+0xFFA06A46,
+0xFFA36F48,
+0xFFAE7D55,
+0xFFB1845D,
+0xFFB38764,
+0xFF9F7150,
+0xFF99684A,
+0xFF8C5E3D,
+0xFFA07251,
+0xFF95684B,
+0xFF996D50,
+0xFF8A6344,
+0xFF896543,
+0xFFA27F59,
+0xFFA07F56,
+0xFF6B4A21,
+0xFFA08059,
+0xFFA68660,
+0xFFB59471,
+0xFFBD9C79,
+0xFFA3835D,
+0xFF9F7F58,
+0xFF94794E,
+0xFF9E895C,
+0xFFA38C62,
+0xFF8E6C47,
+0xFF997752,
+0xFFAD946C,
+0xFF977C51,
+0xFF9B7747,
+0xFF9E7B45,
+0xFFA0884C,
+0xFF816C33,
+0xFF806538,
+0xFF7C5F37,
+0xFF81613A,
+0xFF7D6139,
+0xFF68572B,
+0xFF8C7F53,
+0xFF8C8058,
+0xFF817A50,
+0xFF6F6E3E,
+0xFF6F6937,
+0xFF957F4E,
+0xFF917045,
+0xFF8B6340,
+0xFFA47B5B,
+0xFF997752,
+0xFFA17D5D,
+0xFFA57662,
+0xFF622A1B,
+0xFF591B06,
+0xFF723A17,
+0xFF9B7B3E,
+0xFFCFBC53,
+0xFFE4D32E,
+0xFFF5E345,
+0xFFA08A37,
+0xFF7C673C,
+0xFF9B8E6B,
+0xFF564D2C,
+0xFF5E5335,
+0xFF5A5132,
+0xFF595532,
+0xFF5D5936,
+0xFF5B5437,
+0xFF413A20,
+0xFF3E3725,
+0xFF3F3825,
+0xFF4B3F27,
+0xFF625135,
+0xFF755E3F,
+0xFF6F5532,
+0xFF836A42,
+0xFF705528,
+0xFF8A6E3F,
+0xFF947849,
+0xFFA58A5D,
+0xFF8C7048,
+0xFF80643F,
+0xFF765937,
+0xFF6E5335,
+0xFF7D6244,
+0xFF8B7053,
+0xFF7A5C42,
+0xFF76563F,
+0xFF84664E,
+0xFF795E43,
+0xFF826D50,
+0xFF6A593D,
+0xFF54482E,
+0xFF2F2A14,
+0xFF232210,
+0xFF232416,
+0xFF242215,
+0xFF615E4D,
+0xFF857F69,
+0xFF83785C,
+0xFF685837,
+0xFF6E5A37,
+0xFF78613F,
+0xFF69512F,
+0xFF654E2F,
+0xFF2C1B01,
+0xFF7A6A53,
+0xFF2A1907,
+0xFF41301E,
+0xFF81705E,
+0xFF2F1E0A,
+0xFF4D3D26,
+0xFF96866C,
+0xFFB5A584,
+0xFFC1AF8B,
+0xFFC6B48E,
+0xFFB4A179,
+0xFFC1AB82,
+0xFFCFB88F,
+0xFFD1B993,
+0xFFC5AD87,
+0xFFC9B18B,
+0xFFC8B08A,
+0xFFCAB08D,
+0xFFC7AD88,
+0xFFAA9168,
+0xFFB39B6F,
+0xFFA38A61,
+0xFFB29970,
+0xFF9D8555,
+0xFFA38B5B,
+0xFFB9A173,
+0xFFBEA678,
+0xFFA08858,
+0xFF9A8252,
+0xFF8E7648,
+0xFF90794D,
+0xFF816C3F,
+0xFF5D481D,
+0xFF57411A,
+0xFF4C3911,
+0xFF614E23,
+0xFF826F44,
+0xFF806F41,
+0xFF89784C,
+0xFF6B5830,
+0xFF624E29,
+0xFF49330E,
+0xFF907A53,
+0xFF7B643B,
+0xFF8A7149,
+0xFFB59B78,
+0xFF987E5D,
+0xFF4E3425,
+0xFF4D3324,
+0xFF422618,
+0xFF4A2E20,
+0xFF533326,
+0xFF5A3A2B,
+0xFF4F2E1D,
+0xFF65422F,
+0xFF734E3B,
+0xFF613D27,
+0xFF7C5943,
+0xFF5A3721,
+0xFF573720,
+0xFF76563F,
+0xFF5F3F2A,
+0xFF755540,
+0xFF7A5743,
+0xFF57331D,
+0xFF784F3B,
+0xFF7A513D,
+0xFF67412C,
+0xFF724E38,
+0xFF77533D,
+0xFF67442E,
+0xFF4B2C17,
+0xFF674833,
+0xFF714B36,
+0xFF6F4630,
+0xFF734F35,
+0xFF745236,
+0xFF8E6D4E,
+0xFF644324,
+0xFF896849,
+0xFF6A4528,
+0xFF865A3F,
+0xFF82543A,
+0xFF7B4D33,
+0xFF7F5338,
+0xFF7D5637,
+0xFF9E7A5A,
+0xFF75512F,
+0xFF8F6847,
+0xFF7E4F31,
+0xFF865537,
+0xFF875636,
+0xFF906241,
+0xFF885D3B,
+0xFF835836,
+0xFF714224,
+0xFF905F41,
+0xFF9A674A,
+0xFF8B5839,
+0xFF9B6647,
+0xFF986142,
+0xFF773E20,
+0xFF9B6342,
+0xFF804A28,
+0xFF9E6947,
+0xFF986746,
+0xFF7F512F,
+0xFF8E603E,
+0xFF714322,
+0xFF976948,
+0xFF986749,
+0xFF905A40,
+0xFF834D33,
+0xFF8D5C3C,
+0xFF9B6B47,
+0xFF8E5D35,
+0xFFB37D57,
+0xFFA56F4D,
+0xFF96603E,
+0xFF9E6A42,
+0xFF9F6C3F,
+0xFFB17D4D,
+0xFFB27D4B,
+0xFF9D673B,
+0xFFA17141,
+0xFFA48046,
+0xFF957E4C,
+0xFF796B51,
+0xFF1B1311,
+0xFF292139,
+0xFF3C385D,
+0xFF3E3D69,
+0xFF282A53,
+0xFF151A37,
+0xFF252B41,
+0xFF191F2F,
+0xFF191F2D,
+0xFF030615,
+0xFF0D101F,
+0xFF131629,
+0xFF363A53,
+0xFF2E3154,
+0xFF2C3056,
+0xFF2A2F4F,
+0xFF2D324F,
+0xFF282C45,
+0xFF262B3F,
+0xFF262B3F,
+0xFF282A3F,
+0xFF202237,
+0xFF0A0B1D,
+0xFF07060E,
+0xFF0F0200,
+0xFF846546,
+0xFF9C754A,
+0xFFB69165,
+0xFFA27B52,
+0xFF845936,
+0xFFA97D5A,
+0xFFD3A281,
+0xFFA2704D,
+0xFF9A6A46,
+0xFF92603D,
+0xFFA0694A,
+0xFFA2694B,
+0xFF915A3B,
+0xFF824D2D,
+0xFF986546,
+0xFF835232,
+0xFF815030,
+0xFF744825,
+0xFF8F6944,
+0xFF815E38,
+0xFF7F5D37,
+0xFF89633E,
+0xFF865B38,
+0xFF8A5938,
+0xFF854C2F,
+0xFFA86D4F,
+0xFF9D6745,
+0xFF996C43,
+0xFF806031,
+0xFF735F2D,
+0xFF5D5322,
+0xFF7B6F3F,
+0xFF897145,
+0xFF89683D,
+0xFF9F7D50,
+0xFF68471A,
+0xFF876F41,
+0xFF70592D,
+0xFF674E25,
+0xFF7E603A,
+0xFF6C4C25,
+0xFF92724B,
+0xFF957850,
+0xFFA18158,
+0xFF906D47,
+0xFF8D6541,
+0xFFA27653,
+0xFFAF815F,
+0xFFA67A57,
+0xFF8D613E,
+0xFFA77B58,
+0xFF9C714E,
+0xFF9B7550,
+0xFF927249,
+0xFF816639,
+0xFF927748,
+0xFFAB8A5F,
+0xFFA27C55,
+0xFFA57D59,
+0xFF9E7652,
+0xFFA17550,
+0xFFC1916B,
+0xFFA9754D,
+0xFFBC875D,
+0xFFCF9C6F,
+0xFFA67749,
+0xFFB4895E,
+0xFFA4794F,
+0xFF996B47,
+0xFF996B47,
+0xFFA3784E,
+0xFFA57B53,
+0xFFAA825E,
+0xFF916D49,
+0xFF84623D,
+0xFFC6A981,
+0xFFB4976B,
+0xFF7D6233,
+0xFF775C2D,
+0xFFC7AC7F,
+0xFFAF9469,
+0xFFD3B78F,
+0xFFB79E75,
+0xFF836C40,
+0xFF836D3C,
+0xFF685723,
+0xFF928950,
+0xFF796E36,
+0xFF7E6837,
+0xFF8F774B,
+0xFFA59365,
+0xFFA18F5F,
+0xFF907947,
+0xFF948147,
+0xFF7D7534,
+0xFF706C2C,
+0xFF756C35,
+0xFF6C5E2D,
+0xFF705C2A,
+0xFF917B4A,
+0xFF655021,
+0xFF786336,
+0xFF6E552D,
+0xFF967F55,
+0xFF938554,
+0xFF867541,
+0xFFA37F4F,
+0xFF93673A,
+0xFF865F34,
+0xFF9D7C51,
+0xFF937C4A,
+0xFF9D8056,
+0xFFA5755E,
+0xFF4A0D00,
+0xFF450300,
+0xFF6D3407,
+0xFF967724,
+0xFFD9CA4B,
+0xFFE0D428,
+0xFFE8DB3F,
+0xFF7F6D1B,
+0xFF847347,
+0xFF908859,
+0xFF726E3F,
+0xFF676336,
+0xFF615D30,
+0xFF626131,
+0xFF666537,
+0xFF4D4B24,
+0xFF3F3C19,
+0xFF4B4B29,
+0xFF625F3C,
+0xFF8A8359,
+0xFF8D8255,
+0xFF8A794E,
+0xFF8A7548,
+0xFF7D6937,
+0xFF98844F,
+0xFFAF9C62,
+0xFFAF9C64,
+0xFF9D8954,
+0xFF948250,
+0xFF776537,
+0xFF57441A,
+0xFF544119,
+0xFF68542F,
+0xFF937D58,
+0xFF816947,
+0xFF7D6342,
+0xFF866C4B,
+0xFF88704A,
+0xFF948159,
+0xFF8E8059,
+0xFF726A46,
+0xFF302D0E,
+0xFF25280D,
+0xFF292D16,
+0xFF232710,
+0xFF484A32,
+0xFF6F6E50,
+0xFF6C6642,
+0xFF696037,
+0xFF86774C,
+0xFF867348,
+0xFF735D34,
+0xFF89764E,
+0xFF92825E,
+0xFFC3B592,
+0xFFBCAD8C,
+0xFFB5A687,
+0xFFBAAB8C,
+0xFF9D8E6D,
+0xFFA19370,
+0xFFA79974,
+0xFFB2A37A,
+0xFFA89A6D,
+0xFFA89769,
+0xFF958554,
+0xFFA18F5F,
+0xFF8F7A4B,
+0xFF9C875A,
+0xFFA38E61,
+0xFF998457,
+0xFF968154,
+0xFF958055,
+0xFF897447,
+0xFF806E3E,
+0xFF705E2C,
+0xFF7F6D3D,
+0xFF8F7D4D,
+0xFF93814F,
+0xFF8E7C4A,
+0xFFB5A373,
+0xFFBFAD7F,
+0xFF998757,
+0xFF735E2F,
+0xFF6A5528,
+0xFF5E4B20,
+0xFF5F5027,
+0xFF4C3E17,
+0xFF574926,
+0xFF594B28,
+0xFF61532C,
+0xFF665B2E,
+0xFF706537,
+0xFF6F6236,
+0xFF564720,
+0xFF63512D,
+0xFF64502B,
+0xFF907A53,
+0xFF927B52,
+0xFF765C37,
+0xFF8D7050,
+0xFF8F7254,
+0xFF4F3828,
+0xFF4A3021,
+0xFF563A2C,
+0xFF4D3123,
+0xFF5E3E2F,
+0xFF523223,
+0xFF634231,
+0xFF62412E,
+0xFF5B3824,
+0xFF603D27,
+0xFF6A4A31,
+0xFF63452B,
+0xFF53381D,
+0xFF6E5338,
+0xFF543A21,
+0xFF785C44,
+0xFF4A2C14,
+0xFF604027,
+0xFF79553D,
+0xFF6F4B33,
+0xFF714F36,
+0xFF67472E,
+0xFF714E38,
+0xFF6A4A33,
+0xFF6C503A,
+0xFF654933,
+0xFF66422C,
+0xFF7F5942,
+0xFF815F44,
+0xFF5D3E21,
+0xFF6D5030,
+0xFF806341,
+0xFF6B4E2E,
+0xFF6C4D2E,
+0xFF906B4E,
+0xFF80573B,
+0xFF784C2F,
+0xFF7E5738,
+0xFF81603F,
+0xFF806240,
+0xFF735531,
+0xFF74522F,
+0xFF916646,
+0xFF895A3C,
+0xFF865837,
+0xFF7C4F2E,
+0xFF916B47,
+0xFF7A5634,
+0xFF774E30,
+0xFF6E4225,
+0xFF835438,
+0xFF8C593C,
+0xFF9C664A,
+0xFF875032,
+0xFF915C3D,
+0xFF925D3D,
+0xFF9A6847,
+0xFF8F5D3C,
+0xFF905D3E,
+0xFF815030,
+0xFF875636,
+0xFF825335,
+0xFF946748,
+0xFF996C4D,
+0xFF8C5D41,
+0xFF99684A,
+0xFF82502F,
+0xFF8A5533,
+0xFFA36B46,
+0xFF8D5532,
+0xFF7F4628,
+0xFF9F6A48,
+0xFFA27349,
+0xFFB28657,
+0xFFB68854,
+0xFF9F713D,
+0xFFA07143,
+0xFF895E33,
+0xFFBA986A,
+0xFFB39C7A,
+0xFF332A23,
+0xFF1D1B29,
+0xFF2B2A4A,
+0xFF474670,
+0xFF2A2D56,
+0xFF34385E,
+0xFF343957,
+0xFF1B213B,
+0xFF0E122B,
+0xFF080A1F,
+0xFF040517,
+0xFF000110,
+0xFF00000F,
+0xFF31364A,
+0xFF3D4061,
+0xFF34385E,
+0xFF272B50,
+0xFF282B4C,
+0xFF222641,
+0xFF2F3148,
+0xFF2E3045,
+0xFF28293D,
+0xFF1B1C30,
+0xFF0C0B1B,
+0xFF0F0C13,
+0xFF100100,
+0xFF8B6C4F,
+0xFF987148,
+0xFFA57E53,
+0xFF966C42,
+0xFF9D714A,
+0xFF8F613D,
+0xFFB48362,
+0xFFA57453,
+0xFF986A48,
+0xFF8B5A39,
+0xFF9D6745,
+0xFF945E3C,
+0xFF814C2A,
+0xFF905E3B,
+0xFF8A5A36,
+0xFF956743,
+0xFF936541,
+0xFF9A6F4C,
+0xFF95734D,
+0xFF82653D,
+0xFF896942,
+0xFF8B6944,
+0xFF86603C,
+0xFF774C2A,
+0xFF7C4B2A,
+0xFF9A6A46,
+0xFF936E44,
+0xFF85693A,
+0xFF90804C,
+0xFF8E8952,
+0xFF898C55,
+0xFF7E7C49,
+0xFF827042,
+0xFF998155,
+0xFF94794C,
+0xFF7D6738,
+0xFF827443,
+0xFF5C5221,
+0xFF6D6033,
+0xFF796B3E,
+0xFF5E4C1E,
+0xFF746232,
+0xFF897745,
+0xFF978350,
+0xFF9B7F50,
+0xFF967447,
+0xFFAC855C,
+0xFFA57B53,
+0xFFA57E57,
+0xFFA57E57,
+0xFFB0865E,
+0xFFA37951,
+0xFFA48255,
+0xFFB29365,
+0xFF9E8857,
+0xFFA79160,
+0xFFB99C70,
+0xFFA3835A,
+0xFFA6865D,
+0xFFB99C72,
+0xFFAB8E62,
+0xFFAA8B5D,
+0xFFC2A072,
+0xFF866232,
+0xFFA1814E,
+0xFFAC915C,
+0xFFA58E5C,
+0xFF998352,
+0xFF9E8658,
+0xFF9D8253,
+0xFFAD915F,
+0xFFA78B59,
+0xFF9F8757,
+0xFF776233,
+0xFF837141,
+0xFF897B4A,
+0xFFA69964,
+0xFF8E814C,
+0xFFA29560,
+0xFFBAAD78,
+0xFF9C8F5B,
+0xFFA29463,
+0xFF918551,
+0xFF928952,
+0xFF8A854B,
+0xFF858545,
+0xFF79833E,
+0xFF96A059,
+0xFF919050,
+0xFF958F53,
+0xFFA39E66,
+0xFF9D9A63,
+0xFF85844E,
+0xFF898C53,
+0xFF757F40,
+0xFF6F7A36,
+0xFF929D5B,
+0xFF818344,
+0xFF82763A,
+0xFF977C47,
+0xFF8F6238,
+0xFF86502E,
+0xFF682F14,
+0xFF4C1600,
+0xFF633617,
+0xFF744622,
+0xFF90522B,
+0xFFB1784B,
+0xFF9C7E4C,
+0xFF998E56,
+0xFF8D8D4F,
+0xFF988F58,
+0xFF926B4A,
+0xFF3C0400,
+0xFF460800,
+0xFF885424,
+0xFF9E8622,
+0xFFC4BC33,
+0xFFDFD736,
+0xFFC1B92A,
+0xFF7E7321,
+0xFF87824A,
+0xFF7F8346,
+0xFF878F53,
+0xFF6C7137,
+0xFF636830,
+0xFF7E8349,
+0xFF777A43,
+0xFF61642F,
+0xFF747740,
+0xFF82884C,
+0xFF818749,
+0xFF909457,
+0xFF84884D,
+0xFF858851,
+0xFF7B7C43,
+0xFF7D7E42,
+0xFF828244,
+0xFF8C8C4C,
+0xFF818040,
+0xFF7B793C,
+0xFF88864B,
+0xFF76753C,
+0xFF6B6A32,
+0xFF797842,
+0xFF7A7943,
+0xFF93925C,
+0xFF9A9764,
+0xFF989260,
+0xFF888250,
+0xFF817E4B,
+0xFF868451,
+0xFF8E8E5C,
+0xFF878B59,
+0xFF62683A,
+0xFF6F764A,
+0xFF697148,
+0xFF626940,
+0xFF676C43,
+0xFF777A4D,
+0xFF7C7E4C,
+0xFF71713B,
+0xFF929159,
+0xFF76753D,
+0xFF6E6D37,
+0xFF7D7B48,
+0xFF86854F,
+0xFF979562,
+0xFF858352,
+0xFF858352,
+0xFF848353,
+0xFF6D6C3C,
+0xFF747241,
+0xFF757342,
+0xFF817F4C,
+0xFF75743E,
+0xFF706D36,
+0xFF807D46,
+0xFF716C35,
+0xFF746F38,
+0xFF8B8551,
+0xFF8E8753,
+0xFF827B45,
+0xFF77703A,
+0xFF645F28,
+0xFF68632C,
+0xFF6F6A33,
+0xFF66612A,
+0xFF746E3A,
+0xFF746E3A,
+0xFF928B57,
+0xFF908857,
+0xFFAA9F71,
+0xFF9D9265,
+0xFF7E7147,
+0xFF62532A,
+0xFF64552E,
+0xFF52441F,
+0xFF655B38,
+0xFF766D4E,
+0xFF5B5235,
+0xFF675E3F,
+0xFF5A522E,
+0xFF6F6A42,
+0xFF645F35,
+0xFF575228,
+0xFF5F5730,
+0xFF685F38,
+0xFF695D35,
+0xFF796B44,
+0xFF63542B,
+0xFF68562E,
+0xFF685431,
+0xFF725B3B,
+0xFF523B2B,
+0xFF4D3626,
+0xFF4B3122,
+0xFF503426,
+0xFF4C2F1F,
+0xFF5F4230,
+0xFF684937,
+0xFF52331E,
+0xFF583821,
+0xFF6D4F35,
+0xFF63482B,
+0xFF62492B,
+0xFF533B1F,
+0xFF634E31,
+0xFF6A553A,
+0xFF402B10,
+0xFF553D21,
+0xFF674C31,
+0xFF64442B,
+0xFF65432A,
+0xFF56381E,
+0xFF5A3C22,
+0xFF5C3C25,
+0xFF65472F,
+0xFF6E543D,
+0xFF4B2F19,
+0xFF67432D,
+0xFF7E5A42,
+0xFF624025,
+0xFF614225,
+0xFF765939,
+0xFF846A47,
+0xFF674F2D,
+0xFF775D3C,
+0xFF836243,
+0xFF724D30,
+0xFF7F583B,
+0xFF623F1F,
+0xFF6F5232,
+0xFF836B47,
+0xFF6A502D,
+0xFF896B49,
+0xFF754E2F,
+0xFF865A3D,
+0xFF76492A,
+0xFF855C3C,
+0xFF92704D,
+0xFF755433,
+0xFF684728,
+0xFF815C3F,
+0xFF875B40,
+0xFF7D4E32,
+0xFF905D42,
+0xFF925F42,
+0xFF966547,
+0xFF784727,
+0xFF7C4E2D,
+0xFFA87757,
+0xFF865535,
+0xFF8B5A3A,
+0xFF9B6A4C,
+0xFF835436,
+0xFF7A4F2F,
+0xFF92694B,
+0xFF7E5235,
+0xFF946949,
+0xFFA17956,
+0xFF8C603D,
+0xFFA57352,
+0xFF966141,
+0xFF976243,
+0xFF905F3E,
+0xFF977049,
+0xFF946F42,
+0xFF8A6231,
+0xFFAC804F,
+0xFF845829,
+0xFFC29B72,
+0xFFA28567,
+0xFF736252,
+0xFF18151C,
+0xFF1B1D36,
+0xFF3E4067,
+0xFF404370,
+0xFF353A64,
+0xFF3A3F65,
+0xFF2F3452,
+0xFF333752,
+0xFF383955,
+0xFF31334A,
+0xFF262739,
+0xFF313340,
+0xFF222632,
+0xFF292E42,
+0xFF474C6C,
+0xFF383C62,
+0xFF2D2F56,
+0xFF292C4F,
+0xFF2A2B49,
+0xFF2C2E47,
+0xFF1E1E36,
+0xFF16172B,
+0xFF1B1A2C,
+0xFF0B0916,
+0xFF0B080F,
+0xFF31241C,
+0xFF94795C,
+0xFF937048,
+0xFF9D7A52,
+0xFF876238,
+0xFF81572F,
+0xFF976B44,
+0xFF9E7350,
+0xFF9E7652,
+0xFF86603B,
+0xFFA07A53,
+0xFF8E623D,
+0xFF8A5E37,
+0xFF9A734A,
+0xFF89673A,
+0xFF957346,
+0xFF8F6E41,
+0xFF856238,
+0xFF88693D,
+0xFF725B2F,
+0xFF857345,
+0xFF816C41,
+0xFF70592F,
+0xFF9A8159,
+0xFF81643C,
+0xFF82623B,
+0xFF896C42,
+0xFF7F6D3B,
+0xFF9E955E,
+0xFF828047,
+0xFF868A4F,
+0xFF848F53,
+0xFF5B642B,
+0xFF98925E,
+0xFF948856,
+0xFF8A804D,
+0xFF8E8854,
+0xFF6B6A34,
+0xFF8D8D59,
+0xFF7C7C4A,
+0xFF757340,
+0xFF817A46,
+0xFF6A632D,
+0xFF878049,
+0xFF867D44,
+0xFF92814B,
+0xFF8A733F,
+0xFF917545,
+0xFFAC9061,
+0xFF9F8457,
+0xFFA4895A,
+0xFFA58658,
+0xFFA68A5A,
+0xFFB7A06C,
+0xFF8D7C48,
+0xFF8C7F4B,
+0xFF9A8C5B,
+0xFF715F2F,
+0xFF9C8A5A,
+0xFF918150,
+0xFF9A8C5B,
+0xFF9D915D,
+0xFF908450,
+0xFFA1915D,
+0xFF7A6A36,
+0xFF9D905B,
+0xFF9B925B,
+0xFFA6A169,
+0xFF8E8B54,
+0xFF7F7945,
+0xFF6F6832,
+0xFF94884E,
+0xFF988C52,
+0xFF80773E,
+0xFF837E44,
+0xFF7D7C43,
+0xFF8B8C52,
+0xFF9E9F63,
+0xFF808145,
+0xFFA2A266,
+0xFF9F9F63,
+0xFF8A8950,
+0xFF7E7D44,
+0xFF7F8044,
+0xFF85894C,
+0xFF808948,
+0xFF84914B,
+0xFF7B8B42,
+0xFF8C9C51,
+0xFF919D55,
+0xFF828B48,
+0xFF7A8040,
+0xFF91975B,
+0xFF848F55,
+0xFF78864B,
+0xFF748245,
+0xFF788245,
+0xFF898A4E,
+0xFF807A3E,
+0xFF88793E,
+0xFF573C05,
+0xFF4E1F00,
+0xFF5F2903,
+0xFF663111,
+0xFF4C1B00,
+0xFF3E1300,
+0xFF3C0A00,
+0xFF7C3710,
+0xFF9C5529,
+0xFFB98756,
+0xFFAF965D,
+0xFF949655,
+0xFF89874E,
+0xFF966E4B,
+0xFF4D1300,
+0xFF531D01,
+0xFFA17A41,
+0xFF9F8E22,
+0xFFD1CB3F,
+0xFFB9B31D,
+0xFFA09B19,
+0xFF96943F,
+0xFFA3A566,
+0xFF95A05C,
+0xFF7F8E4B,
+0xFF7D8949,
+0xFF899354,
+0xFF969F60,
+0xFF8B9153,
+0xFF8F9557,
+0xFF8F9855,
+0xFF88944A,
+0xFF879349,
+0xFF7B8642,
+0xFF909C5A,
+0xFF93A261,
+0xFF7E8D4C,
+0xFF8A9654,
+0xFF707D38,
+0xFF848F4B,
+0xFF8C9752,
+0xFF808946,
+0xFF919A57,
+0xFF7E8947,
+0xFF919C5A,
+0xFF9AA465,
+0xFF8C9657,
+0xFF939D5E,
+0xFF9DA667,
+0xFF889152,
+0xFF798145,
+0xFF7F874C,
+0xFF81894E,
+0xFF7F894D,
+0xFF8A9559,
+0xFF839154,
+0xFF97A56A,
+0xFF899660,
+0xFF8A9761,
+0xFF859058,
+0xFF8B965C,
+0xFF7C8647,
+0xFF8A9553,
+0xFF848F4D,
+0xFF6F793A,
+0xFF818C50,
+0xFF7E884B,
+0xFF85904E,
+0xFF7B8441,
+0xFF899253,
+0xFF778142,
+0xFF757F42,
+0xFF858F52,
+0xFF798346,
+0xFF818B4E,
+0xFF8B9357,
+0xFF60682C,
+0xFF7B8445,
+0xFF7F8547,
+0xFF72783C,
+0xFF787E42,
+0xFF7F844A,
+0xFF666B31,
+0xFF82854C,
+0xFF7A7F45,
+0xFF80854B,
+0xFF7C8147,
+0xFF7B8046,
+0xFF666E33,
+0xFF767B43,
+0xFF7A7F49,
+0xFF7F844E,
+0xFF707240,
+0xFFA7A676,
+0xFF848154,
+0xFF767147,
+0xFF645C35,
+0xFF6C643D,
+0xFF645C37,
+0xFF534D2B,
+0xFF676242,
+0xFF625D3D,
+0xFF504C29,
+0xFF605E37,
+0xFF68693F,
+0xFF606135,
+0xFF757748,
+0xFF626337,
+0xFF6C6B3F,
+0xFF504D22,
+0xFF565127,
+0xFF5B542A,
+0xFF635B34,
+0xFF524824,
+0xFF493C19,
+0xFF533D2F,
+0xFF4F382A,
+0xFF3F281A,
+0xFF4C3223,
+0xFF482E1D,
+0xFF6D523F,
+0xFF4F3220,
+0xFF5D412B,
+0xFF5D432A,
+0xFF61472C,
+0xFF6C5536,
+0xFF4F3A1B,
+0xFF655436,
+0xFF4C3D1E,
+0xFF625437,
+0xFF332407,
+0xFF604D2F,
+0xFF80694A,
+0xFF523418,
+0xFF644529,
+0xFF6D4F33,
+0xFF634529,
+0xFF997960,
+0xFF907258,
+0xFF43270F,
+0xFF51351D,
+0xFF75513B,
+0xFF89634C,
+0xFF654127,
+0xFF816245,
+0xFF9C7F5F,
+0xFF7B6140,
+0xFF564221,
+0xFF6F5838,
+0xFF644729,
+0xFF805E42,
+0xFF775438,
+0xFF715233,
+0xFF72593A,
+0xFF7A6341,
+0xFF7C6442,
+0xFF765939,
+0xFF896447,
+0xFF92694D,
+0xFF855C40,
+0xFF6F4A2D,
+0xFF775839,
+0xFF664C2B,
+0xFF523719,
+0xFF7D5E3F,
+0xFF714C2F,
+0xFF7E5537,
+0xFF724528,
+0xFF9E6F51,
+0xFF825536,
+0xFF815435,
+0xFF8B5E3F,
+0xFF906344,
+0xFF8C5D3F,
+0xFF855638,
+0xFF9A6B4F,
+0xFF704326,
+0xFF855C3E,
+0xFF734A2E,
+0xFF885C41,
+0xFF876343,
+0xFF7B653E,
+0xFF634D26,
+0xFF725034,
+0xFF764C33,
+0xFFA17254,
+0xFF855A3A,
+0xFF856745,
+0xFF6A4E29,
+0xFF87643E,
+0xFFA87D53,
+0xFF7E4E20,
+0xFF916946,
+0xFF766257,
+0xFF352E35,
+0xFF131524,
+0xFF222744,
+0xFF4D527C,
+0xFF3D4171,
+0xFF353C6A,
+0xFF3D426A,
+0xFF414663,
+0xFF31364C,
+0xFF2A2C43,
+0xFF242539,
+0xFF302F3F,
+0xFF212330,
+0xFF0A0E1A,
+0xFF1B2034,
+0xFF494D72,
+0xFF373A63,
+0xFF43456B,
+0xFF3B3E61,
+0xFF272A49,
+0xFF2D314C,
+0xFF2D2F48,
+0xFF212237,
+0xFF222133,
+0xFF161620,
+0xFF09080D,
+0xFF61584F,
+0xFF735E41,
+0xFF8E724B,
+0xFF977E56,
+0xFF8B6E46,
+0xFF7D5C33,
+0xFFAE8B63,
+0xFF93734A,
+0xFF94794E,
+0xFF927D50,
+0xFF8C7748,
+0xFF745E2F,
+0xFF816D3B,
+0xFFA99966,
+0xFF9A915A,
+0xFFABA26B,
+0xFF898049,
+0xFF8A7E4A,
+0xFF736934,
+0xFF827C48,
+0xFF686530,
+0xFF847E4C,
+0xFF675F2E,
+0xFF4E4617,
+0xFF8E8657,
+0xFF857F4B,
+0xFF9F9E66,
+0xFF8A9257,
+0xFF7A8648,
+0xFF7B8347,
+0xFF858F50,
+0xFF859556,
+0xFF788849,
+0xFF798347,
+0xFF767F46,
+0xFF7A884D,
+0xFF738247,
+0xFF869157,
+0xFF949F65,
+0xFF7C874F,
+0xFF707942,
+0xFF575A23,
+0xFF74753C,
+0xFF7D8347,
+0xFF7E8245,
+0xFF676228,
+0xFF786F36,
+0xFF857A44,
+0xFF584F18,
+0xFF837E47,
+0xFF908B54,
+0xFF9D9660,
+0xFF817A43,
+0xFF757539,
+0xFF74783D,
+0xFF7E814C,
+0xFF767644,
+0xFF696734,
+0xFF5C5B25,
+0xFF80834C,
+0xFF98A065,
+0xFF576125,
+0xFF6E783C,
+0xFF61662E,
+0xFF7C8149,
+0xFF697138,
+0xFF6B763C,
+0xFF6A783D,
+0xFF87955A,
+0xFF818C52,
+0xFF586024,
+0xFF6F7034,
+0xFF7A7C3D,
+0xFF909754,
+0xFF8A9551,
+0xFF707F3C,
+0xFF7C8D49,
+0xFF6C7C3B,
+0xFF8C9A5C,
+0xFF6E7A3C,
+0xFFA2AE6E,
+0xFF677230,
+0xFF788442,
+0xFF64732E,
+0xFF7F904A,
+0xFF849853,
+0xFF8EA25B,
+0xFF8C9953,
+0xFF86934D,
+0xFF778842,
+0xFF94A561,
+0xFF697837,
+0xFF98A466,
+0xFF919B5E,
+0xFF6C763A,
+0xFF636C35,
+0xFF7B7543,
+0xFF815F39,
+0xFF5B310B,
+0xFF5C3B10,
+0xFF533908,
+0xFF907A41,
+0xFF9F8F54,
+0xFF878049,
+0xFF98935C,
+0xFF928B54,
+0xFF937A44,
+0xFF945728,
+0xFF7F2B00,
+0xFFAB451D,
+0xFFB16237,
+0xFF9F8F54,
+0xFF857E4A,
+0xFF743E24,
+0xFF4D0F00,
+0xFF3F1900,
+0xFFA4904B,
+0xFFA19527,
+0xFFC9C03D,
+0xFFD8D14C,
+0xFF8C8A13,
+0xFF878935,
+0xFF959C59,
+0xFF879653,
+0xFF7D8D4C,
+0xFF758544,
+0xFF788744,
+0xFF909B59,
+0xFF949D5C,
+0xFF8E9955,
+0xFF818C47,
+0xFF849149,
+0xFF91A15A,
+0xFF788649,
+0xFF808E51,
+0xFF899A56,
+0xFF8C9D56,
+0xFF889952,
+0xFF879651,
+0xFF909D58,
+0xFF8E9B56,
+0xFF919E58,
+0xFF8A9751,
+0xFF8F9F58,
+0xFF91A158,
+0xFF8F9F58,
+0xFF889752,
+0xFF93A05B,
+0xFF97A361,
+0xFF788341,
+0xFF778142,
+0xFF778144,
+0xFF798547,
+0xFF879653,
+0xFF7A8B45,
+0xFF6C8039,
+0xFF788D48,
+0xFF859A55,
+0xFF7C914E,
+0xFF6B803B,
+0xFF70843D,
+0xFF7D8E47,
+0xFF819349,
+0xFF687831,
+0xFF768540,
+0xFF839251,
+0xFF6E7D3C,
+0xFF819148,
+0xFF94A557,
+0xFF87974E,
+0xFF7F9147,
+0xFF72833C,
+0xFF7D8E48,
+0xFF72833D,
+0xFF7C8D47,
+0xFF8B9A55,
+0xFF74833E,
+0xFF606F2C,
+0xFF6E7A38,
+0xFF717D3D,
+0xFF798545,
+0xFF6C783A,
+0xFF5C672B,
+0xFF7E8B53,
+0xFF6B7842,
+0xFF74814B,
+0xFF6D7C45,
+0xFF7D8C55,
+0xFF586A30,
+0xFF637239,
+0xFF606F36,
+0xFF697841,
+0xFF6A7741,
+0xFF6E7844,
+0xFF5E6633,
+0xFF5B6131,
+0xFF777A4D,
+0xFF7B7E51,
+0xFF515226,
+0xFF5D5E32,
+0xFF59582C,
+0xFF4D4F20,
+0xFF686A39,
+0xFF888C5A,
+0xFF787F4C,
+0xFF7B8350,
+0xFF6E7843,
+0xFF68723D,
+0xFF59632E,
+0xFF68703F,
+0xFF545C2D,
+0xFF666C40,
+0xFF898E65,
+0xFF757750,
+0xFF80825B,
+0xFF7C695A,
+0xFF311E0F,
+0xFF543E30,
+0xFF4C3726,
+0xFF4B3422,
+0xFF4F3924,
+0xFF5E4531,
+0xFF58422A,
+0xFF554025,
+0xFF665335,
+0xFF6E5E3D,
+0xFF5E4F2E,
+0xFF675C3C,
+0xFF605736,
+0xFF585232,
+0xFF574E2F,
+0xFF5E5131,
+0xFF786847,
+0xFF675031,
+0xFF594022,
+0xFF553E1F,
+0xFF61482A,
+0xFF81664B,
+0xFF5A4025,
+0xFF584026,
+0xFF6E543B,
+0xFF65422C,
+0xFF67442E,
+0xFF7B5B42,
+0xFF56381C,
+0xFF9A7F61,
+0xFF7E6747,
+0xFF5D4A29,
+0xFF6E5B3A,
+0xFF775C3E,
+0xFF715436,
+0xFF624326,
+0xFF705335,
+0xFF7D6647,
+0xFF766241,
+0xFF9D8869,
+0xFF563D1E,
+0xFF7F5D42,
+0xFF785539,
+0xFF6F4A30,
+0xFFA07E62,
+0xFF5B4023,
+0xFF574020,
+0xFF604929,
+0xFF6D5234,
+0xFF745536,
+0xFF7F5C3C,
+0xFF7B5435,
+0xFF986F4F,
+0xFF805737,
+0xFF7A5131,
+0xFF8B6040,
+0xFF784D2D,
+0xFF774C2C,
+0xFF956A4A,
+0xFF8C6345,
+0xFF8C6345,
+0xFF7E573A,
+0xFF754E31,
+0xFF7D5639,
+0xFF886A48,
+0xFF6F6037,
+0xFF786A43,
+0xFF2A1000,
+0xFF947559,
+0xFF846040,
+0xFF82613E,
+0xFF836F4E,
+0xFF624F2E,
+0xFF785E3B,
+0xFF7D5D37,
+0xFF704E21,
+0xFFA78A6C,
+0xFF665B5F,
+0xFF1E1F34,
+0xFF0B1127,
+0xFF464C6C,
+0xFF454C78,
+0xFF3D4375,
+0xFF3D4472,
+0xFF24294F,
+0xFF070D27,
+0xFF010619,
+0xFF000011,
+0xFF00010E,
+0xFF02020E,
+0xFF02020E,
+0xFF00000E,
+0xFF2F334C,
+0xFF45496F,
+0xFF3E426F,
+0xFF363A60,
+0xFF45496C,
+0xFF3D4260,
+0xFF191E3B,
+0xFF292D46,
+0xFF36384D,
+0xFF2D2F3E,
+0xFF252831,
+0xFF161719,
+0xFF3D3B2F,
+0xFF66583D,
+0xFF9A8864,
+0xFF8D7E57,
+0xFF76643C,
+0xFF7D663C,
+0xFFAB9367,
+0xFF917C4F,
+0xFF8B7D4E,
+0xFF988E5D,
+0xFF88814D,
+0xFF766F3B,
+0xFF89834F,
+0xFF7F7F49,
+0xFFAFB47A,
+0xFF798146,
+0xFFA7AC72,
+0xFF94975E,
+0xFF777A41,
+0xFF767E43,
+0xFF767E43,
+0xFF6B7038,
+0xFF8E915A,
+0xFF2F3100,
+0xFF6C703D,
+0xFF626A31,
+0xFF737E42,
+0xFF819355,
+0xFF4D5F21,
+0xFF717D3F,
+0xFF778345,
+0xFF6F7F40,
+0xFF7F9252,
+0xFF6B7D3F,
+0xFF6C8043,
+0xFF61793D,
+0xFF677C41,
+0xFF68763B,
+0xFF515C22,
+0xFF7B8850,
+0xFF8D9A64,
+0xFF525B24,
+0xFF818950,
+0xFF7A8447,
+0xFF7F894C,
+0xFF7B7F44,
+0xFF7F8046,
+0xFF7B7C42,
+0xFF797D42,
+0xFF878F54,
+0xFF788246,
+0xFF60682C,
+0xFF586225,
+0xFF515F21,
+0xFF516123,
+0xFF3E4B13,
+0xFF57612C,
+0xFF8E9760,
+0xFF454E15,
+0xFF4C5C1E,
+0xFF617536,
+0xFF4B6121,
+0xFF738949,
+0xFF86985E,
+0xFF49581F,
+0xFF54652E,
+0xFF73844D,
+0xFF81955A,
+0xFFA5B77B,
+0xFF576528,
+0xFF687436,
+0xFF626C2D,
+0xFF737F3D,
+0xFF7D8E48,
+0xFF677B33,
+0xFF778D45,
+0xFF819852,
+0xFF5D7332,
+0xFF788E4D,
+0xFF708244,
+0xFF8DA060,
+0xFF6B7C38,
+0xFF70843D,
+0xFF768A42,
+0xFF6E843C,
+0xFF859C56,
+0xFF748946,
+0xFF6C7838,
+0xFF939F5F,
+0xFF6B7E3E,
+0xFF687D3C,
+0xFF677A3A,
+0xFF758345,
+0xFF979C62,
+0xFF7E7D47,
+0xFF736C3E,
+0xFF4E3811,
+0xFF431600,
+0xFF411300,
+0xFF7A5A34,
+0xFF736133,
+0xFF8C834A,
+0xFFADAF6E,
+0xFF9AA563,
+0xFF838F47,
+0xFF8F9444,
+0xFF64580C,
+0xFFAB8345,
+0xFFC7794B,
+0xFFB73C1B,
+0xFFB24423,
+0xFF9F7744,
+0xFF988251,
+0xFF642A14,
+0xFF450B00,
+0xFF523708,
+0xFFAB9F55,
+0xFF928419,
+0xFFAB9F25,
+0xFFB1AB33,
+0xFF76740D,
+0xFF636619,
+0xFF8F9859,
+0xFF869155,
+0xFF6E7E3F,
+0xFF7D8E4A,
+0xFF85944F,
+0xFF808B49,
+0xFFA0AB67,
+0xFF84914C,
+0xFF899952,
+0xFF9DAC67,
+0xFF8A9956,
+0xFF768447,
+0xFF6F7D3F,
+0xFF94A45B,
+0xFF98A85D,
+0xFF8F9F56,
+0xFF899952,
+0xFF7D8C47,
+0xFF798843,
+0xFF8C9C55,
+0xFF8B9D53,
+0xFF8B9D51,
+0xFF8A9C50,
+0xFFA5B76D,
+0xFF7F9049,
+0xFF8A9954,
+0xFF838F4D,
+0xFF70793A,
+0xFF757E3F,
+0xFF8A9457,
+0xFF7D8949,
+0xFF6D7C37,
+0xFF7F9049,
+0xFF758941,
+0xFF7F934B,
+0xFF7A9047,
+0xFF7B9149,
+0xFF798D46,
+0xFF798D45,
+0xFF93A85D,
+0xFF738539,
+0xFF798B41,
+0xFF80914A,
+0xFF758544,
+0xFF70813D,
+0xFF82944A,
+0xFF95A859,
+0xFF889D50,
+0xFF758A3F,
+0xFF82964E,
+0xFF9AAE66,
+0xFF71853E,
+0xFF7B8F48,
+0xFF899D56,
+0xFF899D56,
+0xFF98A965,
+0xFF839450,
+0xFF768743,
+0xFF788945,
+0xFF6D7D3C,
+0xFF7C8C4E,
+0xFF5F6E37,
+0xFF30410B,
+0xFF677842,
+0xFF576A33,
+0xFF60733C,
+0xFF8A9F66,
+0xFF596E33,
+0xFF5B7035,
+0xFF50652C,
+0xFF6D8048,
+0xFF61753A,
+0xFF43551B,
+0xFF6B7A43,
+0xFF74824D,
+0xFF67743F,
+0xFF727C48,
+0xFF5B642F,
+0xFF69723B,
+0xFF596327,
+0xFF788347,
+0xFF69743A,
+0xFF69763E,
+0xFF6E7D44,
+0xFF627138,
+0xFF617337,
+0xFF55672D,
+0xFF576530,
+0xFF606E3D,
+0xFF455025,
+0xFF515C32,
+0xFF636B42,
+0xFF6B734A,
+0xFF544333,
+0xFF655444,
+0xFF3D2C1A,
+0xFF6C5B49,
+0xFF412F1B,
+0xFF705E48,
+0xFF4D3B25,
+0xFF45341A,
+0xFF5F5033,
+0xFF615434,
+0xFF534926,
+0xFF6C6440,
+0xFF554F2D,
+0xFF5D5936,
+0xFF656241,
+0xFF4D4A29,
+0xFF383210,
+0xFF908766,
+0xFF554625,
+0xFF8F7F5E,
+0xFF4E3F1E,
+0xFF655534,
+0xFF6C593B,
+0xFF968365,
+0xFF49381C,
+0xFF443317,
+0xFF785E45,
+0xFF62462E,
+0xFF5D4328,
+0xFF5B4627,
+0xFF887555,
+0xFF443413,
+0xFF6D5D3C,
+0xFF5A4727,
+0xFF6C5536,
+0xFF9B8063,
+0xFF896B4F,
+0xFF6A5133,
+0xFF7C674A,
+0xFF917E5E,
+0xFF6D5A3C,
+0xFF685132,
+0xFF70553A,
+0xFF735539,
+0xFF75553C,
+0xFF6E5336,
+0xFF61492D,
+0xFF5E492A,
+0xFF4D3918,
+0xFF685131,
+0xFF7D6543,
+0xFF886E4B,
+0xFF795B39,
+0xFF896744,
+0xFF795231,
+0xFF7A5430,
+0xFF8D6542,
+0xFF643E1A,
+0xFF724E2C,
+0xFF8C6A47,
+0xFF815E3E,
+0xFF987557,
+0xFF7D583D,
+0xFF9D785B,
+0xFF8C6E4C,
+0xFF7B623A,
+0xFF766037,
+0xFF8A744D,
+0xFF684F30,
+0xFF8F7657,
+0xFF745E39,
+0xFF75633D,
+0xFF584C26,
+0xFF655B37,
+0xFF6D643D,
+0xFF4E471D,
+0xFF69643A,
+0xFF727057,
+0xFF2B2D39,
+0xFF1F2441,
+0xFF1C2340,
+0xFF474D6F,
+0xFF414874,
+0xFF3F4674,
+0xFF1F2650,
+0xFF141A3A,
+0xFF1F2639,
+0xFF1D232F,
+0xFF1B1E27,
+0xFF0C0C14,
+0xFF05040C,
+0xFF00000C,
+0xFF000010,
+0xFF414562,
+0xFF525582,
+0xFF3D4171,
+0xFF393E66,
+0xFF373D5F,
+0xFF37405D,
+0xFF414B64,
+0xFF232B40,
+0xFF080F1F,
+0xFF151C26,
+0xFF2C3137,
+0xFF11191B,
+0xFF3A3D34,
+0xFF6E6850,
+0xFF453C1B,
+0xFF57512D,
+0xFF645F37,
+0xFF73683B,
+0xFF8B7F4F,
+0xFF887E4D,
+0xFF6C6634,
+0xFF918F5C,
+0xFF575725,
+0xFF848452,
+0xFF757745,
+0xFF6A713D,
+0xFF5D6631,
+0xFF7D8752,
+0xFF6C7641,
+0xFF58612A,
+0xFF67723A,
+0xFF6D783E,
+0xFF919F64,
+0xFF545F23,
+0xFF7D864D,
+0xFF5E6532,
+0xFF5B622F,
+0xFF767D47,
+0xFF6C753C,
+0xFF919F64,
+0xFF5A682D,
+0xFF6A733C,
+0xFF495219,
+0xFF6D783E,
+0xFF57662B,
+0xFF7A8C52,
+0xFF52652D,
+0xFF4C5F28,
+0xFF32410A,
+0xFF7D804B,
+0xFF797C47,
+0xFF68713C,
+0xFF56632D,
+0xFF848D56,
+0xFF535C23,
+0xFF4B561C,
+0xFF6B7539,
+0xFF586025,
+0xFF6A6F35,
+0xFF74793F,
+0xFF798347,
+0xFF6D7B3E,
+0xFF4A5A1C,
+0xFF6B7B3D,
+0xFF758749,
+0xFF748A4A,
+0xFF809656,
+0xFF64783D,
+0xFF4B5A23,
+0xFF728045,
+0xFF97A769,
+0xFF6D8241,
+0xFF718746,
+0xFF7F9856,
+0xFF637939,
+0xFF697B41,
+0xFF7D8C55,
+0xFF4E5B26,
+0xFF636D38,
+0xFF747F47,
+0xFF838C53,
+0xFF92955C,
+0xFF5B6125,
+0xFF5C682A,
+0xFF758544,
+0xFF6B7F3A,
+0xFF829850,
+0xFFB8CF87,
+0xFF607731,
+0xFF708645,
+0xFF526828,
+0xFF798B4F,
+0xFF7B8E4E,
+0xFF7F934E,
+0xFF738740,
+0xFF778B44,
+0xFF819651,
+0xFF798E4B,
+0xFF637539,
+0xFF67743E,
+0xFF515E29,
+0xFF6E7D42,
+0xFF66783A,
+0xFF879A5A,
+0xFF6C763A,
+0xFF968E5D,
+0xFF7D6740,
+0xFF442506,
+0xFF361300,
+0xFF543811,
+0xFF927D52,
+0xFF6C6134,
+0xFF9B976A,
+0xFF807E4E,
+0xFF8E8E58,
+0xFF8B8D4C,
+0xFF858734,
+0xFFFBF78B,
+0xFFF1E97E,
+0xFF8E8334,
+0xFF9C6D39,
+0xFFCA583D,
+0xFFAD351C,
+0xFFA25E31,
+0xFFC99A6E,
+0xFF4C1200,
+0xFF350500,
+0xFF6E5829,
+0xFF9D8F46,
+0xFFA58F2A,
+0xFF9D8919,
+0xFF7F760F,
+0xFFA2A049,
+0xFF8D8D4D,
+0xFF828653,
+0xFF838A56,
+0xFF788148,
+0xFF899651,
+0xFF9BA661,
+0xFF949D5A,
+0xFF8C9753,
+0xFF81904B,
+0xFF778844,
+0xFF627130,
+0xFF849050,
+0xFF899450,
+0xFF89954B,
+0xFF95A253,
+0xFF9BA859,
+0xFF939F55,
+0xFF8C9953,
+0xFF94A35E,
+0xFF83924D,
+0xFF7E8F48,
+0xFF90A55A,
+0xFF7F9447,
+0xFFA3B86D,
+0xFF7B8C45,
+0xFF5F6E29,
+0xFF6B7737,
+0xFF6A7236,
+0xFF696C33,
+0xFF797C43,
+0xFF6B7538,
+0xFF7B8747,
+0xFF788442,
+0xFF7D8A44,
+0xFF6B7832,
+0xFF929F59,
+0xFF677331,
+0xFF6E7A38,
+0xFF6F7B39,
+0xFF73803B,
+0xFF808D47,
+0xFF748139,
+0xFF818E48,
+0xFF71803B,
+0xFF8C9B58,
+0xFF869554,
+0xFF8E9F5B,
+0xFF859650,
+0xFF879854,
+0xFF869753,
+0xFF8D9D5C,
+0xFF92A261,
+0xFF728241,
+0xFF889857,
+0xFF5E712F,
+0xFF788B49,
+0xFF657534,
+0xFF8B9B5A,
+0xFF99A968,
+0xFF596928,
+0xFF647433,
+0xFF6B7B3D,
+0xFF5C6B34,
+0xFF36440F,
+0xFF606F38,
+0xFF60713A,
+0xFF485B23,
+0xFF6A7E43,
+0xFF677D3F,
+0xFF5F7535,
+0xFF607638,
+0xFF61793B,
+0xFF506928,
+0xFF6A8342,
+0xFF7C9254,
+0xFF74894E,
+0xFF697D40,
+0xFF64783B,
+0xFF6C8043,
+0xFF75894A,
+0xFF4D621F,
+0xFF879C57,
+0xFF4A5F1E,
+0xFF748849,
+0xFF81965B,
+0xFF53682D,
+0xFF536728,
+0xFF54682B,
+0xFF5F7039,
+0xFF5C6C3B,
+0xFF536034,
+0xFF4D5A2F,
+0xFF616C42,
+0xFF657045,
+0xFF4F4231,
+0xFF433623,
+0xFF544734,
+0xFF473B25,
+0xFF53442F,
+0xFF473821,
+0xFF44361C,
+0xFF4B4024,
+0xFF4F4625,
+0xFF5B532F,
+0xFF79734F,
+0xFF3C3813,
+0xFF63603D,
+0xFF565330,
+0xFF81815F,
+0xFF424220,
+0xFF3B3C1A,
+0xFF7C7C58,
+0xFF595331,
+0xFF605834,
+0xFF615935,
+0xFF605834,
+0xFF746949,
+0xFF7C7151,
+0xFF3F3617,
+0xFF413618,
+0xFF655438,
+0xFF604C31,
+0xFF5E4F32,
+0xFF675A3A,
+0xFF8B8060,
+0xFF665C39,
+0xFF706343,
+0xFF615231,
+0xFF604D2F,
+0xFF887054,
+0xFF755D41,
+0xFF574225,
+0xFF514022,
+0xFF5A4B2C,
+0xFF5B4A2C,
+0xFF928163,
+0xFF6A5538,
+0xFF634B2F,
+0xFF897155,
+0xFF756041,
+0xFF59482A,
+0xFF564625,
+0xFF8E7E5D,
+0xFF6D5A39,
+0xFF5A4A26,
+0xFF66542E,
+0xFF7B6540,
+0xFF755B36,
+0xFF6E502C,
+0xFF8B6B45,
+0xFF896845,
+0xFF8A6C48,
+0xFF795F3A,
+0xFF806844,
+0xFF5C4221,
+0xFF73583A,
+0xFF815F44,
+0xFF98795C,
+0xFF927C57,
+0xFF7F6D45,
+0xFF76643C,
+0xFF8A7B52,
+0xFF978964,
+0xFF5A502C,
+0xFF514922,
+0xFF78734B,
+0xFF706843,
+0xFF9C9771,
+0xFF96946D,
+0xFF2D2F0A,
+0xFF5D6445,
+0xFF586257,
+0xFF282F41,
+0xFF191F41,
+0xFF222848,
+0xFF454B6D,
+0xFF42476F,
+0xFF2D355C,
+0xFF242A4E,
+0xFF2C334F,
+0xFF303548,
+0xFF202430,
+0xFF191923,
+0xFF1C1C24,
+0xFF1D1C24,
+0xFF1D1D27,
+0xFF000012,
+0xFF4A4E6B,
+0xFF565986,
+0xFF424675,
+0xFF393E64,
+0xFF303656,
+0xFF222C47,
+0xFF1B223C,
+0xFF050B21,
+0xFF080D20,
+0xFF2F333F,
+0xFF0F141A,
+0xFF040C0E,
+0xFF090F05,
+0xFF7D7B62,
+0xFF54512E,
+0xFF555732,
+0xFF676840,
+0xFFA8A57A,
+0xFF8A8657,
+0xFF727040,
+0xFF80804E,
+0xFF5D5F2E,
+0xFF777B49,
+0xFF8B8E5F,
+0xFF4E5424,
+0xFF7A8253,
+0xFF565F30,
+0xFF434F1F,
+0xFF74804E,
+0xFF798651,
+0xFF55622C,
+0xFF6C7B42,
+0xFF7F8E55,
+0xFF68773C,
+0xFF606D35,
+0xFF8F9967,
+0xFF7B8352,
+0xFF414A15,
+0xFF505922,
+0xFF67743E,
+0xFF7C8953,
+0xFF6A7440,
+0xFF555F2A,
+0xFF707942,
+0xFF626D35,
+0xFF66733D,
+0xFF6F7D48,
+0xFF778552,
+0xFF485220,
+0xFF656735,
+0xFF747742,
+0xFF58612A,
+0xFF667139,
+0xFFB4BF87,
+0xFF5A632C,
+0xFF434C15,
+0xFF414A13,
+0xFF525923,
+0xFF596128,
+0xFF7D854A,
+0xFF677236,
+0xFF647436,
+0xFF627436,
+0xFF687A3C,
+0xFF4B5F20,
+0xFF6B8141,
+0xFF556B2D,
+0xFF718349,
+0xFF859459,
+0xFF687639,
+0xFF576728,
+0xFF677C3B,
+0xFF657C38,
+0xFF799250,
+0xFF748A4A,
+0xFF83955B,
+0xFF5F6C36,
+0xFF87915C,
+0xFF6D7641,
+0xFF778049,
+0xFF80884F,
+0xFF83844B,
+0xFFA1A46B,
+0xFF646F33,
+0xFF94A668,
+0xFF8A9D5B,
+0xFF6D813C,
+0xFF778C47,
+0xFF8FA461,
+0xFF748849,
+0xFF7F9155,
+0xFF56682C,
+0xFF425416,
+0xFF80904F,
+0xFF7D8E4A,
+0xFF879854,
+0xFF849453,
+0xFF859557,
+0xFF68773E,
+0xFF454F1D,
+0xFF4D5325,
+0xFF595828,
+0xFF7A7744,
+0xFF817E47,
+0xFF837544,
+0xFF95714D,
+0xFF68391D,
+0xFF471500,
+0xFF764D2F,
+0xFF655428,
+0xFF74713E,
+0xFF828153,
+0xFF696A3E,
+0xFF6E6F45,
+0xFF7A7949,
+0xFF817B3D,
+0xFFDCD483,
+0xFFE0D267,
+0xFFEBDE75,
+0xFFB5AF61,
+0xFF825F29,
+0xFFB74F32,
+0xFFB64229,
+0xFFC2744E,
+0xFFAC724D,
+0xFF440B00,
+0xFF330600,
+0xFF90804F,
+0xFF898139,
+0xFFB39E43,
+0xFFAA9431,
+0xFF6D6206,
+0xFF999443,
+0xFF949456,
+0xFF9FA26D,
+0xFF7C804D,
+0xFF8B9358,
+0xFF9EA965,
+0xFF858F4A,
+0xFF818646,
+0xFF858B4D,
+0xFF828E4C,
+0xFF7D8C49,
+0xFF444F13,
+0xFFB9C386,
+0xFF8E9954,
+0xFF818D41,
+0xFF9DA85C,
+0xFFA0AA61,
+0xFF87924D,
+0xFF8F9A56,
+0xFFA3AF6F,
+0xFF7D8947,
+0xFF74843D,
+0xFF85974D,
+0xFF62742A,
+0xFF899B51,
+0xFF6C7B36,
+0xFF727E3C,
+0xFF7F894C,
+0xFF8B9358,
+0xFF7C7F48,
+0xFF6D723A,
+0xFF767F46,
+0xFF758044,
+0xFF818D4D,
+0xFF6A7533,
+0xFF767F3C,
+0xFF757E3B,
+0xFF828B4A,
+0xFF70793A,
+0xFF7F8849,
+0xFF737E3C,
+0xFF86914D,
+0xFF919E58,
+0xFF98A560,
+0xFF81904D,
+0xFF7A8948,
+0xFF808E50,
+0xFF8A9958,
+0xFF758443,
+0xFF94A362,
+0xFF7D8C4B,
+0xFF798847,
+0xFF92A160,
+0xFF8C9B5A,
+0xFF778645,
+0xFF6A7A39,
+0xFF657534,
+0xFF7E8D4C,
+0xFF73823F,
+0xFF849350,
+0xFF697833,
+0xFF7E8D48,
+0xFF728140,
+0xFF7C8B50,
+0xFF707F46,
+0xFF849358,
+0xFF819357,
+0xFF596B31,
+0xFF697D40,
+0xFF627736,
+0xFF718844,
+0xFF718747,
+0xFF455B1B,
+0xFF617736,
+0xFF657E3C,
+0xFF8EA464,
+0xFF607638,
+0xFF506628,
+0xFF647A3A,
+0xFF73894B,
+0xFF728B4A,
+0xFF6A833F,
+0xFF738C48,
+0xFF566C2B,
+0xFF4A6022,
+0xFF475C21,
+0xFF50652A,
+0xFF657B3D,
+0xFF607437,
+0xFF53662E,
+0xFF32430F,
+0xFF4C5C2F,
+0xFF48572C,
+0xFF6B784C,
+0xFF3D4A1C,
+0xFF342E18,
+0xFF554F37,
+0xFF3C341D,
+0xFF423A23,
+0xFF433B24,
+0xFF575036,
+0xFF4A4326,
+0xFF645E3E,
+0xFF5D5936,
+0xFF5F5B36,
+0xFF625E39,
+0xFF494720,
+0xFF43411B,
+0xFF51512D,
+0xFF3C3C1A,
+0xFF686947,
+0xFF2F3712,
+0xFF5B633E,
+0xFF60623D,
+0xFF4A4A26,
+0xFF6C6C46,
+0xFF787852,
+0xFF6E6C46,
+0xFF4F4D27,
+0xFF484824,
+0xFF474421,
+0xFF5D5435,
+0xFF5C5334,
+0xFF4B4626,
+0xFF474423,
+0xFF6A6A48,
+0xFF716E4B,
+0xFF565030,
+0xFF7C7151,
+0xFF68593C,
+0xFF67563A,
+0xFF9C8B6F,
+0xFF4E3F22,
+0xFF554828,
+0xFF534828,
+0xFF605633,
+0xFF4E4421,
+0xFFA59876,
+0xFF413412,
+0xFF6D603E,
+0xFF756845,
+0xFF6B633F,
+0xFF6F6743,
+0xFF847755,
+0xFF756845,
+0xFF716743,
+0xFF615831,
+0xFF71633E,
+0xFF71623B,
+0xFF6B5732,
+0xFFA69069,
+0xFFA58F6A,
+0xFF75613C,
+0xFFA0906C,
+0xFF7A6C49,
+0xFF493918,
+0xFF342403,
+0xFF5A4226,
+0xFF897658,
+0xFF584E2B,
+0xFF67633D,
+0xFF4A481F,
+0xFF55582D,
+0xFF7E8559,
+0xFF525D32,
+0xFF59613A,
+0xFF3D411C,
+0xFF696540,
+0xFF8B8561,
+0xFF373310,
+0xFF2A2811,
+0xFF5A5C57,
+0xFF2B2F3B,
+0xFF313550,
+0xFF292C4D,
+0xFF272A4B,
+0xFF424767,
+0xFF3D4164,
+0xFF292F4F,
+0xFF313653,
+0xFF2C324A,
+0xFF22273D,
+0xFF232639,
+0xFF272636,
+0xFF302E3C,
+0xFF272530,
+0xFF0E0E1A,
+0xFF000011,
+0xFF5A5E79,
+0xFF50557B,
+0xFF333860,
+0xFF1E2343,
+0xFF222641,
+0xFF1A203A,
+0xFF181C37,
+0xFF10112D,
+0xFF32324A,
+0xFF2A273C,
+0xFF12101D,
+0xFF111214,
+0xFF000200,
+0xFF928F6E,
+0xFFA6A47B,
+0xFF84865E,
+0xFF777952,
+0xFF6E6A47,
+0xFF3E3A15,
+0xFF67683E,
+0xFF494C1F,
+0xFF65683D,
+0xFF9DA075,
+0xFF63693D,
+0xFF6A7145,
+0xFF848A5E,
+0xFF5F663A,
+0xFF767D51,
+0xFF949D6E,
+0xFF798555,
+0xFF808E5B,
+0xFF56632E,
+0xFF6D7B46,
+0xFF47561F,
+0xFF4D5B26,
+0xFF72804F,
+0xFF2E3A0A,
+0xFF59632F,
+0xFF58622D,
+0xFF5E6B36,
+0xFF52632F,
+0xFF819361,
+0xFF435420,
+0xFF58602D,
+0xFF505724,
+0xFF888E5E,
+0xFF4E5627,
+0xFF4D592B,
+0xFF616D3D,
+0xFF64713C,
+0xFF75824A,
+0xFF636E34,
+0xFF6C773D,
+0xFF7E8951,
+0xFF5D6631,
+0xFF818854,
+0xFF7A7E4B,
+0xFF636734,
+0xFF838A54,
+0xFF586027,
+0xFF495317,
+0xFF7A8447,
+0xFF7E8A4C,
+0xFF5E6C2F,
+0xFF758547,
+0xFF67753A,
+0xFF919F64,
+0xFF596428,
+0xFF7F8A4E,
+0xFF8F995C,
+0xFFA2AC6F,
+0xFF6C7A3C,
+0xFF809051,
+0xFF647638,
+0xFF708244,
+0xFF68763B,
+0xFF7E8B53,
+0xFF737E46,
+0xFF3F4C14,
+0xFF88955D,
+0xFF616E36,
+0xFF616930,
+0xFF8A935A,
+0xFF66733B,
+0xFF718047,
+0xFF6E7D42,
+0xFF93A365,
+0xFF728043,
+0xFF758346,
+0xFF78864B,
+0xFF79874C,
+0xFF77854A,
+0xFF7C8C4E,
+0xFF6F7D40,
+0xFF728042,
+0xFF6D7B3E,
+0xFF869155,
+0xFF8A955B,
+0xFF777E48,
+0xFF6E703F,
+0xFF71653B,
+0xFF6B4D2B,
+0xFF835838,
+0xFFA97F59,
+0xFF8C5634,
+0xFF661504,
+0xFF661305,
+0xFF83432A,
+0xFF89613E,
+0xFF6D6033,
+0xFF979765,
+0xFF716E43,
+0xFF47441B,
+0xFF6A6841,
+0xFF5C5829,
+0xFFD5C68F,
+0xFFA6914E,
+0xFF786113,
+0xFF836C20,
+0xFF7D692A,
+0xFF9B713F,
+0xFFB25A36,
+0xFFBB593C,
+0xFF9E593A,
+0xFF733B20,
+0xFF571E0B,
+0xFF3E1400,
+0xFF867C4B,
+0xFF999A56,
+0xFFA29747,
+0xFF655500,
+0xFF5B4C00,
+0xFF857D2C,
+0xFF7C7B38,
+0xFFACB272,
+0xFF8C9556,
+0xFF899452,
+0xFF9AA560,
+0xFF8F9855,
+0xFF98975F,
+0xFFA09D68,
+0xFF9B9F62,
+0xFF6F7839,
+0xFF61692D,
+0xFF929C5F,
+0xFF8F9B59,
+0xFF879651,
+0xFF5A6722,
+0xFF94A05E,
+0xFF848E51,
+0xFF636D31,
+0xFF858D52,
+0xFF71773B,
+0xFF99A25F,
+0xFF848E47,
+0xFF89934C,
+0xFF88934E,
+0xFF8D9856,
+0xFF707A3B,
+0xFF9AA467,
+0xFF8A9458,
+0xFF9AA266,
+0xFF879155,
+0xFF5A6732,
+0xFF85925D,
+0xFF626D33,
+0xFF6E783B,
+0xFF8D9655,
+0xFF7D8645,
+0xFF909958,
+0xFF788140,
+0xFF737E3C,
+0xFF879250,
+0xFF7E8945,
+0xFF7F8C47,
+0xFF899855,
+0xFF6B7B3A,
+0xFF6A793E,
+0xFF889659,
+0xFF7F8B4B,
+0xFF929D59,
+0xFF747F3B,
+0xFF798440,
+0xFF616C27,
+0xFF909B56,
+0xFF838E49,
+0xFF88934E,
+0xFF707B36,
+0xFF89944F,
+0xFF707B36,
+0xFF6F7B33,
+0xFF9BA860,
+0xFF808E43,
+0xFF849245,
+0xFF7E8E45,
+0xFF5A6A29,
+0xFF768949,
+0xFF90A361,
+0xFF607331,
+0xFF667939,
+0xFF849757,
+0xFFA4B871,
+0xFF849851,
+0xFF576A2A,
+0xFF4C5F1F,
+0xFF7D904E,
+0xFF738644,
+0xFF546328,
+0xFF6B7A3F,
+0xFF536227,
+0xFF6C7B40,
+0xFF63773C,
+0xFF778C51,
+0xFF6B8143,
+0xFF62783A,
+0xFF697D42,
+0xFF54682D,
+0xFF4F622A,
+0xFF667941,
+0xFF4B5E26,
+0xFF64773F,
+0xFF50632C,
+0xFF5C6E3A,
+0xFF4D5F2D,
+0xFF566838,
+0xFF465828,
+0xFF495B29,
+0xFF434128,
+0xFF46442B,
+0xFF615D44,
+0xFF484429,
+0xFF49452A,
+0xFF575336,
+0xFF686544,
+0xFF4C4926,
+0xFF62603A,
+0xFF74724B,
+0xFF74724B,
+0xFF595730,
+0xFF5F5F39,
+0xFF2E2E08,
+0xFF646440,
+0xFF575836,
+0xFF2C3613,
+0xFF3C4623,
+0xFF3C401D,
+0xFF1C1E00,
+0xFF7C7E57,
+0xFF777952,
+0xFF6A6A44,
+0xFF4D4F28,
+0xFF4D512C,
+0xFF6A6E49,
+0xFF4B4827,
+0xFF6A6746,
+0xFF353415,
+0xFF444827,
+0xFF696F4D,
+0xFF2E320F,
+0xFF5A5736,
+0xFF746E4E,
+0xFF665D3E,
+0xFF847B5C,
+0xFF837A5B,
+0xFF52492A,
+0xFF67613F,
+0xFF655F3B,
+0xFF756F4B,
+0xFF817D58,
+0xFF504C27,
+0xFF716D47,
+0xFF635F39,
+0xFF828057,
+0xFF6C6D43,
+0xFF8C8A63,
+0xFF6C6843,
+0xFF534D2B,
+0xFF54502B,
+0xFF807A56,
+0xFF79714C,
+0xFF524A23,
+0xFF50441E,
+0xFF6E623C,
+0xFF5A512A,
+0xFF6D653E,
+0xFF746E4A,
+0xFF605A36,
+0xFF6E6848,
+0xFF7B7253,
+0xFFA09579,
+0xFF7D7457,
+0xFF817E5D,
+0xFF5F613C,
+0xFF313912,
+0xFF1D2A00,
+0xFF435726,
+0xFF5A6E3D,
+0xFF7D8C63,
+0xFF424A25,
+0xFF2C2C06,
+0xFF464320,
+0xFF151400,
+0xFF161709,
+0xFF434250,
+0xFF31324E,
+0xFF323554,
+0xFF333657,
+0xFF303354,
+0xFF313455,
+0xFF333655,
+0xFF383D5A,
+0xFF2D334D,
+0xFF282C45,
+0xFF31334A,
+0xFF2C2D41,
+0xFF201F2F,
+0xFF0E0C19,
+0xFF05030E,
+0xFF03030F,
+0xFF07081A,
+0xFF5D617C,
+0xFF3D4268,
+0xFF31365E,
+0xFF3E4363,
+0xFF333752,
+0xFF292D48,
+0xFF292D46,
+0xFF464660,
+0xFF3B3750,
+0xFF0A051B,
+0xFF0B0716,
+0xFF090A0E,
+0xFF0B0D00,
+0xFF696947,
+0xFF6A6B3F,
+0xFF50572D,
+0xFF6F754F,
+0xFF555533,
+0xFF7A7756,
+0xFF2C3109,
+0xFF373C13,
+0xFF75774F,
+0xFF51572B,
+0xFF969F72,
+0xFF444D20,
+0xFF293203,
+0xFF444D1E,
+0xFF8E9866,
+0xFF677341,
+0xFF616F3C,
+0xFF74824F,
+0xFFC0CC9A,
+0xFF707C4A,
+0xFF465421,
+0xFF4A5825,
+0xFF60703F,
+0xFF6F7D4A,
+0xFF57642E,
+0xFF4D5820,
+0xFF424F19,
+0xFF879864,
+0xFF49602C,
+0xFF5A6E39,
+0xFF47511D,
+0xFF545B27,
+0xFF5E6635,
+0xFF586230,
+0xFF525E30,
+0xFF3F4D1C,
+0xFF52612A,
+0xFF5D6C31,
+0xFF536124,
+0xFF8E995D,
+0xFF6F7C44,
+0xFF4F5924,
+0xFF5D612F,
+0xFF5E6230,
+0xFF79804D,
+0xFF6E7541,
+0xFF818A51,
+0xFF808A4E,
+0xFF7A8246,
+0xFF606A2D,
+0xFF5F6D2F,
+0xFF6C7A3D,
+0xFF586329,
+0xFF4E571E,
+0xFF717B3E,
+0xFF747E41,
+0xFF8D9559,
+0xFF91995D,
+0xFF576125,
+0xFF6F7A3E,
+0xFF677739,
+0xFF7C8B50,
+0xFF808B51,
+0xFF96A167,
+0xFF828D53,
+0xFF89965E,
+0xFF42541A,
+0xFF819057,
+0xFF88955D,
+0xFFA1AC74,
+0xFF93A06A,
+0xFF8F9E67,
+0xFF63703A,
+0xFF5F6934,
+0xFF707B43,
+0xFF858E57,
+0xFF79844A,
+0xFF59642A,
+0xFF6D7B40,
+0xFF5E6C31,
+0xFF58662B,
+0xFF7B894E,
+0xFF545F27,
+0xFF7D864F,
+0xFF747B45,
+0xFF777B48,
+0xFF767846,
+0xFF63562A,
+0xFF91684A,
+0xFF854D32,
+0xFFFDC39E,
+0xFFA86344,
+0xFFC87062,
+0xFFEE9B8D,
+0xFF9F664B,
+0xFF705029,
+0xFF908557,
+0xFF6F6F3D,
+0xFF9F9B6C,
+0xFF7F7B4E,
+0xFF6B683D,
+0xFF4A4616,
+0xFF7A6B34,
+0xFF826D34,
+0xFF8D773E,
+0xFF957E48,
+0xFF6E5829,
+0xFF856036,
+0xFFA5613A,
+0xFF994E2E,
+0xFF9B6245,
+0xFF471700,
+0xFF764630,
+0xFF4D2A0C,
+0xFF948E5A,
+0xFF858745,
+0xFF807728,
+0xFF6F600B,
+0xFF82741C,
+0xFF9E9643,
+0xFF8B8B43,
+0xFF626926,
+0xFF808646,
+0xFF7C8544,
+0xFF7E8947,
+0xFF656B2D,
+0xFF6A6734,
+0xFFA9A371,
+0xFF93945A,
+0xFF747A3A,
+0xFF888E50,
+0xFF8F975B,
+0xFF95A163,
+0xFF7E8C4E,
+0xFF8B9759,
+0xFF5A6529,
+0xFF767F46,
+0xFF8C945B,
+0xFF535820,
+0xFF7C8246,
+0xFF929956,
+0xFF8B924E,
+0xFFA0A763,
+0xFF7D8643,
+0xFF80884C,
+0xFF6B7539,
+0xFF8C955C,
+0xFF8C955C,
+0xFF7D874B,
+0xFF7B844B,
+0xFF717B47,
+0xFF7A8450,
+0xFF747D46,
+0xFF646C31,
+0xFF8C9556,
+0xFF929B5C,
+0xFF5B6425,
+0xFF656D31,
+0xFF858F52,
+0xFF838D4E,
+0xFF7E8A48,
+0xFF8D9957,
+0xFF788442,
+0xFF99A867,
+0xFF939E62,
+0xFF9FAA6E,
+0xFF818B4C,
+0xFF6D7834,
+0xFF6A7330,
+0xFF919B56,
+0xFF6B7530,
+0xFF737D36,
+0xFF6E7833,
+0xFF727C37,
+0xFF828C47,
+0xFF8F9954,
+0xFF818B44,
+0xFF929E56,
+0xFF97A359,
+0xFF859147,
+0xFF889448,
+0xFF77853A,
+0xFF677832,
+0xFF91A560,
+0xFF899D58,
+0xFF627631,
+0xFF546423,
+0xFF9AAA69,
+0xFF85964F,
+0xFF61722B,
+0xFF728243,
+0xFF6C7A3C,
+0xFF728140,
+0xFF798847,
+0xFF6A783D,
+0xFF5C6A2F,
+0xFF647237,
+0xFF556429,
+0xFF788A50,
+0xFF485A20,
+0xFF75874D,
+0xFF586932,
+0xFF586730,
+0xFF718049,
+0xFF47561F,
+0xFF798752,
+0xFF606E39,
+0xFF556632,
+0xFF738450,
+0xFF7B8D59,
+0xFF435521,
+0xFF445823,
+0xFF4A5E2B,
+0xFF556936,
+0xFF4C4C30,
+0xFF3C3C20,
+0xFF4B4B2F,
+0xFF4D4D31,
+0xFF494A2B,
+0xFF4B4C2C,
+0xFF444422,
+0xFF63633F,
+0xFF62623C,
+0xFF83845C,
+0xFF585931,
+0xFF62633B,
+0xFF6A6842,
+0xFF5A5832,
+0xFF524F2C,
+0xFF6F6F4D,
+0xFF404725,
+0xFF3F4624,
+0xFF3B3F1C,
+0xFF797B56,
+0xFF494B24,
+0xFF54562F,
+0xFF6B6C44,
+0xFF54562F,
+0xFF424822,
+0xFF565A35,
+0xFF4E4E2C,
+0xFF4D4C2D,
+0xFF404122,
+0xFF6A6F4F,
+0xFF4D5735,
+0xFF585F3D,
+0xFF3C3D1D,
+0xFF525132,
+0xFF575637,
+0xFF595839,
+0xFF575735,
+0xFF646442,
+0xFF70704C,
+0xFF54542E,
+0xFF464620,
+0xFF80825A,
+0xFF595E35,
+0xFF454B1F,
+0xFFB6BE8F,
+0xFF394213,
+0xFF565F30,
+0xFF737A4E,
+0xFF6B6F4A,
+0xFF4D4E2E,
+0xFF3B3B19,
+0xFF7C7958,
+0xFF736F4C,
+0xFF7F7D57,
+0xFF585630,
+0xFF999A72,
+0xFF696B44,
+0xFF62673F,
+0xFF535432,
+0xFF7A7B59,
+0xFF2D2C0E,
+0xFF353416,
+0xFF37371B,
+0xFF555436,
+0xFF585536,
+0xFF464526,
+0xFF36401D,
+0xFF516238,
+0xFF415524,
+0xFF4C5E2E,
+0xFF485328,
+0xFF485027,
+0xFF434A20,
+0xFF373D19,
+0xFF434831,
+0xFF242925,
+0xFF3C4155,
+0xFF313656,
+0xFF2D3653,
+0xFF2C3350,
+0xFF2D3051,
+0xFF2F2F51,
+0xFF2A2B4A,
+0xFF303352,
+0xFF2F3350,
+0xFF2D314A,
+0xFF222439,
+0xFF000211,
+0xFF00000A,
+0xFF09080E,
+0xFF020107,
+0xFF01010B,
+0xFF070A1D,
+0xFF535876,
+0xFF3F446C,
+0xFF3C436D,
+0xFF2B3056,
+0xFF272C4C,
+0xFF373D55,
+0xFF3D4456,
+0xFF181B2A,
+0xFF070616,
+0xFF0D091A,
+0xFF0E0A18,
+0xFF04040C,
+0xFF13160F,
+0xFF727354,
+0xFF454B1F,
+0xFF4A552A,
+0xFF4E592F,
+0xFF767A55,
+0xFF434520,
+0xFF333810,
+0xFF73784F,
+0xFF61633B,
+0xFF505628,
+0xFF606E3B,
+0xFF455620,
+0xFF95A66F,
+0xFF7C8E54,
+0xFF5A6C32,
+0xFF607238,
+0xFF74884D,
+0xFF70814A,
+0xFF68723E,
+0xFF606837,
+0xFF6F7947,
+0xFF697543,
+0xFF404E1B,
+0xFF8E9D66,
+0xFFA4B277,
+0xFF545F23,
+0xFF505B21,
+0xFF63723B,
+0xFF5A7139,
+0xFF61763E,
+0xFF536028,
+0xFF7F8A50,
+0xFF62713A,
+0xFF73844D,
+0xFF74824F,
+0xFF414E19,
+0xFF374208,
+0xFF727E40,
+0xFF576325,
+0xFF99A769,
+0xFF516025,
+0xFF414E18,
+0xFF5B6131,
+0xFFA3A979,
+0xFF626A39,
+0xFF858F5A,
+0xFF88965B,
+0xFF556123,
+0xFF636D2E,
+0xFF808C4C,
+0xFF506021,
+0xFF5A6A2C,
+0xFF636E34,
+0xFF6E773E,
+0xFF889456,
+0xFF7B8747,
+0xFF828A4E,
+0xFF8C9459,
+0xFF5A632A,
+0xFF79844A,
+0xFF707B41,
+0xFF717C42,
+0xFF6E763D,
+0xFF767E43,
+0xFF616C30,
+0xFFB6C489,
+0xFF4C5E24,
+0xFF6A7C42,
+0xFF93A16C,
+0xFF8A9762,
+0xFF85935E,
+0xFF65723D,
+0xFF4E5826,
+0xFF6D7544,
+0xFF8B925F,
+0xFF5C632F,
+0xFF5C652C,
+0xFF8D985C,
+0xFF808E51,
+0xFF5A692E,
+0xFF5D6C33,
+0xFF54632C,
+0xFF596631,
+0xFF555D2A,
+0xFF676E3A,
+0xFF8F9662,
+0xFF7B8550,
+0xFF6C6A39,
+0xFF745831,
+0xFF855932,
+0xFF9E6C3B,
+0xFFE1AB7D,
+0xFFFFCAAF,
+0xFFFFDFC8,
+0xFFC5A481,
+0xFF837247,
+0xFF585022,
+0xFF746E3E,
+0xFF817B49,
+0xFF7A7440,
+0xFF807D48,
+0xFF6C6932,
+0xFF7B743D,
+0xFF867F49,
+0xFF82774A,
+0xFF9E916E,
+0xFF978A6A,
+0xFF6B5434,
+0xFFBC956E,
+0xFF9B6B45,
+0xFFAD8063,
+0xFF6A4228,
+0xFF7B5C3F,
+0xFF705D35,
+0xFF9F9C65,
+0xFF6E6B24,
+0xFF8B7B23,
+0xFFB4A03F,
+0xFFADA13F,
+0xFF8E892E,
+0xFF8C8E45,
+0xFF898D50,
+0xFFACAF7A,
+0xFF80854F,
+0xFF596128,
+0xFF848951,
+0xFF94915E,
+0xFFA9A671,
+0xFF9EA466,
+0xFF727D3B,
+0xFF646D2A,
+0xFF818A4B,
+0xFF576125,
+0xFF707B41,
+0xFF687138,
+0xFF687138,
+0xFF828A51,
+0xFF767E45,
+0xFF81894D,
+0xFF747D3E,
+0xFF96A05B,
+0xFF8A9550,
+0xFF8C9753,
+0xFF717B3E,
+0xFF848D56,
+0xFF69713E,
+0xFF777F4E,
+0xFF5A622F,
+0xFF969D67,
+0xFF8D925C,
+0xFF5B5F2C,
+0xFF5C612B,
+0xFF676A31,
+0xFF676B30,
+0xFF787C41,
+0xFF8A9054,
+0xFF747C43,
+0xFF474E18,
+0xFF8D965F,
+0xFF5E672E,
+0xFF5E682B,
+0xFF566021,
+0xFF828B4A,
+0xFF8C9554,
+0xFF7C8242,
+0xFF757B3B,
+0xFF7C8745,
+0xFF697631,
+0xFF8E9955,
+0xFF8E9955,
+0xFF6F7A36,
+0xFF808B46,
+0xFF75803C,
+0xFF7A8541,
+0xFF828D49,
+0xFF96A15D,
+0xFF7C8743,
+0xFF919E59,
+0xFFA5B26C,
+0xFF73803A,
+0xFF6F7C34,
+0xFF697630,
+0xFF505C1A,
+0xFF798543,
+0xFF8B9755,
+0xFF6C7836,
+0xFF7B8747,
+0xFF798545,
+0xFF63702A,
+0xFF73803A,
+0xFF636F31,
+0xFF556325,
+0xFF707F3C,
+0xFF687935,
+0xFF607032,
+0xFF5D6F33,
+0xFF536529,
+0xFF718345,
+0xFF5B6A2F,
+0xFF516025,
+0xFF314009,
+0xFF62713A,
+0xFF5B6832,
+0xFF49561E,
+0xFF535E26,
+0xFF6E7843,
+0xFF4A5624,
+0xFF626E3C,
+0xFF515F2C,
+0xFF41521E,
+0xFF4A5D26,
+0xFF495C25,
+0xFF546833,
+0xFF5F7340,
+0xFF4B4B2F,
+0xFF3E3E22,
+0xFF525236,
+0xFF393C1F,
+0xFF464A29,
+0xFF5C603D,
+0xFF5A5B39,
+0xFF4B4B27,
+0xFF868662,
+0xFF595933,
+0xFF626039,
+0xFF40401A,
+0xFF5F5C39,
+0xFF6A6A48,
+0xFF5A5A38,
+0xFF30310F,
+0xFF444728,
+0xFF242708,
+0xFF8E8F6F,
+0xFF555533,
+0xFF3B3D18,
+0xFF74764F,
+0xFF4C4E27,
+0xFF3B4018,
+0xFF7C825C,
+0xFF414725,
+0xFF636445,
+0xFF49492D,
+0xFF686B4E,
+0xFF55593E,
+0xFF1A2004,
+0xFF2B3115,
+0xFF6A6D50,
+0xFF6B6C4D,
+0xFF303314,
+0xFF2C2F10,
+0xFF5D6140,
+0xFF444825,
+0xFF616540,
+0xFF3C4119,
+0xFF6B7047,
+0xFF686F43,
+0xFF333A10,
+0xFF5B6439,
+0xFF657046,
+0xFF7F8A60,
+0xFF687349,
+0xFF3F4720,
+0xFF757C5B,
+0xFF303515,
+0xFF2C2D0E,
+0xFF363516,
+0xFF4B4829,
+0xFF585834,
+0xFF70724B,
+0xFF484F26,
+0xFF434925,
+0xFF5B613F,
+0xFF505634,
+0xFF474B2A,
+0xFF363A19,
+0xFF313415,
+0xFF282D0F,
+0xFF454829,
+0xFF4B4829,
+0xFF7B7B59,
+0xFF37411C,
+0xFF64754B,
+0xFF66774B,
+0xFF455528,
+0xFF4C5528,
+0xFF394215,
+0xFF414C21,
+0xFF687450,
+0xFF3C4736,
+0xFF3A4446,
+0xFF363C56,
+0xFF313558,
+0xFF2C3350,
+0xFF2C314E,
+0xFF2E2F4E,
+0xFF2A2948,
+0xFF212240,
+0xFF191A36,
+0xFF181A33,
+0xFF07091E,
+0xFF020315,
+0xFF070713,
+0xFF07080D,
+0xFF06050A,
+0xFF050608,
+0xFF000108,
+0xFF515368,
+0xFF474C6A,
+0xFF3E436B,
+0xFF313660,
+0xFF373B61,
+0xFF414664,
+0xFF2D3349,
+0xFF050B1B,
+0xFF050915,
+0xFF080814,
+0xFF100E1C,
+0xFF060412,
+0xFF040612,
+0xFF121711,
+0xFF454A2A,
+0xFF798152,
+0xFF576534,
+0xFF637042,
+0xFF778055,
+0xFF535A30,
+0xFF767D53,
+0xFF747A4E,
+0xFF64673C,
+0xFF4B5322,
+0xFF94A26D,
+0xFF6D7F45,
+0xFF37490F,
+0xFF607236,
+0xFF7B8D51,
+0xFF6C7E42,
+0xFF3D5116,
+0xFF5F7137,
+0xFF5F6934,
+0xFF454C19,
+0xFF717948,
+0xFF394311,
+0xFF4A5722,
+0xFF7A8950,
+0xFF849255,
+0xFF606E30,
+0xFF636E32,
+0xFF435219,
+0xFF5E733B,
+0xFF73884F,
+0xFF637237,
+0xFF586629,
+0xFF55642B,
+0xFF6A7B44,
+0xFF62703D,
+0xFF3E4B16,
+0xFF646D34,
+0xFF576124,
+0xFF7A8648,
+0xFF5C6A2D,
+0xFF8D9C61,
+0xFF6C7941,
+0xFF3E4613,
+0xFF6D7343,
+0xFF4B5523,
+0xFF6C7644,
+0xFF6C7944,
+0xFF6F7A40,
+0xFF8B9556,
+0xFF95A15F,
+0xFF748342,
+0xFF606E30,
+0xFF616C30,
+0xFF626C2F,
+0xFF768242,
+0xFF707C3A,
+0xFF949C60,
+0xFF8F975E,
+0xFF767F48,
+0xFF505924,
+0xFF919B66,
+0xFF7D8651,
+0xFF6C743B,
+0xFF676F36,
+0xFF848D54,
+0xFF818E56,
+0xFF4D5B26,
+0xFF4A5B27,
+0xFF74824F,
+0xFF5D6B38,
+0xFF626E3C,
+0xFF4D5927,
+0xFF4C5425,
+0xFF7A8052,
+0xFF646836,
+0xFF5C602D,
+0xFF787F49,
+0xFF7D864D,
+0xFF6D7B40,
+0xFF637136,
+0xFF35440D,
+0xFF74814B,
+0xFF99A36F,
+0xFF535B28,
+0xFF49501D,
+0xFF6B7340,
+0xFF697640,
+0xFF838852,
+0xFF736236,
+0xFF8C7041,
+0xFF94733D,
+0xFFC5A46F,
+0xFF6C4E28,
+0xFFA08864,
+0xFF908156,
+0xFF898152,
+0xFF7E7647,
+0xFF6F6937,
+0xFF7A753E,
+0xFF77723A,
+0xFF918C54,
+0xFF8B8950,
+0xFF6B6A32,
+0xFF575725,
+0xFF56542B,
+0xFF989471,
+0xFFA39E7E,
+0xFF5D5330,
+0xFF9B855C,
+0xFF886D42,
+0xFF7F633C,
+0xFF7E6640,
+0xFF95865B,
+0xFF7F7746,
+0xFF8E8E52,
+0xFF7B792F,
+0xFF857A21,
+0xFF7C6D0E,
+0xFF7E7A19,
+0xFF95953D,
+0xFF7E813A,
+0xFF959B5F,
+0xFF727540,
+0xFFABAF7C,
+0xFF727A41,
+0xFF949C63,
+0xFF8D8D5B,
+0xFF6E703E,
+0xFF798146,
+0xFF838F51,
+0xFF606A2B,
+0xFF8C9458,
+0xFF8A9458,
+0xFF6A733A,
+0xFF7B844B,
+0xFF969F66,
+0xFF606930,
+0xFF7F894D,
+0xFF838D50,
+0xFF8A9455,
+0xFF929D5B,
+0xFF9CA765,
+0xFF838D4E,
+0xFF778145,
+0xFF8F9764,
+0xFF596132,
+0xFF6B7344,
+0xFF414717,
+0xFF919865,
+0xFF929663,
+0xFF666934,
+0xFF7B7E49,
+0xFF656831,
+0xFF8E9359,
+0xFF7A7F45,
+0xFF5E662B,
+0xFF7C844B,
+0xFF545D26,
+0xFF858E59,
+0xFF535C27,
+0xFF646D36,
+0xFF747C41,
+0xFF8C9256,
+0xFF737838,
+0xFF7D7F40,
+0xFF848949,
+0xFF7E8746,
+0xFF6C7735,
+0xFF636E2C,
+0xFF616C28,
+0xFF909956,
+0xFF949D5A,
+0xFF97A05D,
+0xFF737E3A,
+0xFF7D8846,
+0xFF8D9856,
+0xFF707C3A,
+0xFF8F9C57,
+0xFF9BA863,
+0xFF98A55F,
+0xFF75823A,
+0xFF93A05A,
+0xFF707C3C,
+0xFF7A8445,
+0xFF778240,
+0xFF6D7937,
+0xFF677132,
+0xFF7E8A4A,
+0xFF67742F,
+0xFF667230,
+0xFF657133,
+0xFF6A783B,
+0xFF8E9D5C,
+0xFF70803F,
+0xFF8B9B5C,
+0xFF4D5D1F,
+0xFF738345,
+0xFF8B9B5D,
+0xFF6B793C,
+0xFF869459,
+0xFF8B9862,
+0xFF4D5722,
+0xFF515B26,
+0xFF5C672F,
+0xFF5C652E,
+0xFF616A35,
+0xFF616A3B,
+0xFF636F41,
+0xFF647241,
+0xFF576532,
+0xFF465721,
+0xFF31420C,
+0xFF475925,
+0xFF566834,
+0xFF544F32,
+0xFF4A4629,
+0xFF464529,
+0xFF57573B,
+0xFF545535,
+0xFF3E3F1D,
+0xFF4C4B2C,
+0xFF4B4A2B,
+0xFF5E5B3C,
+0xFF63603F,
+0xFF4E4A27,
+0xFF5A5736,
+0xFF585739,
+0xFF626344,
+0xFF3F4424,
+0xFF6C6F50,
+0xFF454627,
+0xFF454426,
+0xFF8D8C6D,
+0xFF61613F,
+0xFF525331,
+0xFF585C37,
+0xFF737953,
+0xFF595F3B,
+0xFF545B39,
+0xFF3D4425,
+0xFF32351A,
+0xFF1C1E06,
+0xFF32341F,
+0xFF52513F,
+0xFF1D1C0A,
+0xFF5E5D4B,
+0xFF373621,
+0xFF5E6048,
+0xFF62654A,
+0xFF34371C,
+0xFF2D3214,
+0xFF727757,
+0xFF595F3B,
+0xFF3F461D,
+0xFF9AA175,
+0xFF383F13,
+0xFF454C23,
+0xFF464C2A,
+0xFF6C7055,
+0xFF1B1F08,
+0xFF33351F,
+0xFF53553F,
+0xFF33351D,
+0xFF7E8166,
+0xFF68694A,
+0xFF555637,
+0xFF39381C,
+0xFF242304,
+0xFF4C4D23,
+0xFF6B6D45,
+0xFF666747,
+0xFF656549,
+0xFF555637,
+0xFF161A00,
+0xFF494D28,
+0xFF4A4E29,
+0xFF474D2B,
+0xFF8B8F6E,
+0xFFC4C6A1,
+0xFF777951,
+0xFF323B10,
+0xFF424F23,
+0xFF6B7751,
+0xFF414D27,
+0xFF4F5829,
+0xFF626C3A,
+0xFF182300,
+0xFF273212,
+0xFF1E2A20,
+0xFF333D46,
+0xFF373D57,
+0xFF2C2F50,
+0xFF302F4F,
+0xFF2F2E4D,
+0xFF2D2D49,
+0xFF292B44,
+0xFF27283D,
+0xFF222337,
+0xFF171928,
+0xFF0F111D,
+0xFF0C0C16,
+0xFF0A0A12,
+0xFF06060E,
+0xFF0A0B10,
+0xFF010506,
+0xFF03080C,
+0xFF5E6376,
+0xFF474B68,
+0xFF3C4065,
+0xFF3B3F64,
+0xFF3D405F,
+0xFF2C2E47,
+0xFF101326,
+0xFF101324,
+0xFF0C0D1F,
+0xFF050716,
+0xFF0B0A18,
+0xFF171624,
+0xFF151726,
+0xFF090E0A,
+0xFF79815C,
+0xFF5E6B35,
+0xFF697841,
+0xFF9CAA75,
+0xFF7C8856,
+0xFF7A8656,
+0xFF5B6533,
+0xFF4F5927,
+0xFF636B3A,
+0xFF848C59,
+0xFF6C7641,
+0xFF7E8853,
+0xFF424C1A,
+0xFF69733F,
+0xFF74814B,
+0xFF7E8B55,
+0xFF47541F,
+0xFF303D08,
+0xFF5D6631,
+0xFF5E6732,
+0xFF4F5622,
+0xFF8A925F,
+0xFF3B4513,
+0xFF616E39,
+0xFF8B9B5D,
+0xFF7E8E4F,
+0xFF748247,
+0xFF435018,
+0xFF5B6E37,
+0xFF798C54,
+0xFF5C6E32,
+0xFF49571A,
+0xFF57622A,
+0xFF6F7945,
+0xFF606C3E,
+0xFF495527,
+0xFF5B622E,
+0xFF8C945B,
+0xFF636C35,
+0xFF6F7A42,
+0xFF8D985C,
+0xFF586327,
+0xFF4E571E,
+0xFF707942,
+0xFF545C2D,
+0xFF666D43,
+0xFF525930,
+0xFF636B3A,
+0xFF848D4E,
+0xFF747F3B,
+0xFF707C3A,
+0xFF838F4F,
+0xFF828C4D,
+0xFF677230,
+0xFF88934F,
+0xFF65702E,
+0xFF677134,
+0xFF828B54,
+0xFF58612C,
+0xFF6B7342,
+0xFF4A5422,
+0xFF6A7442,
+0xFF79824D,
+0xFF727B44,
+0xFF5E6833,
+0xFF454F1D,
+0xFF535E33,
+0xFF434E24,
+0xFF879365,
+0xFF3D4919,
+0xFF3C4516,
+0xFF4E5728,
+0xFF8E9667,
+0xFF868D5A,
+0xFF595E28,
+0xFF7A7F47,
+0xFF757A44,
+0xFF5B622C,
+0xFF5E6732,
+0xFF3C470F,
+0xFF636E36,
+0xFF2E3900,
+0xFF7E884C,
+0xFF5D662D,
+0xFF404616,
+0xFFA3AB7A,
+0xFF707B43,
+0xFF8A9259,
+0xFF666330,
+0xFF756D3C,
+0xFF665F2B,
+0xFFA9A36F,
+0xFF494515,
+0xFF94915E,
+0xFF857F4B,
+0xFF928F58,
+0xFF838049,
+0xFF8D8C54,
+0xFF99985F,
+0xFF8F8E55,
+0xFF928D56,
+0xFFA09D66,
+0xFF7A7A46,
+0xFF7A7C4A,
+0xFF999B6C,
+0xFF9FA172,
+0xFF828153,
+0xFF9E9A6B,
+0xFF978F5E,
+0xFFA09661,
+0xFF9A905B,
+0xFF5E5721,
+0xFF828047,
+0xFF9FA162,
+0xFF8B904D,
+0xFF656B21,
+0xFF787B2C,
+0xFFA3A655,
+0xFF585D0D,
+0xFF70782D,
+0xFF818A47,
+0xFF7F8849,
+0xFF7D874A,
+0xFF899354,
+0xFF717C3A,
+0xFF6D773A,
+0xFF545A2A,
+0xFF5E6539,
+0xFF8B9360,
+0xFF7C8651,
+0xFF666F3A,
+0xFF88915A,
+0xFF7E884B,
+0xFF7E8A4A,
+0xFF7E8A4C,
+0xFF818F52,
+0xFF576228,
+0xFF545F25,
+0xFF687337,
+0xFF7E884C,
+0xFF6C753E,
+0xFF7D864D,
+0xFF798347,
+0xFF7B8348,
+0xFF9DA470,
+0xFF525926,
+0xFF727946,
+0xFF5A612E,
+0xFF656C39,
+0xFF4C5320,
+0xFF5F6632,
+0xFF4B521E,
+0xFF666F3A,
+0xFF656E39,
+0xFF7D864F,
+0xFF646F35,
+0xFFACB77B,
+0xFF626D33,
+0xFF545F27,
+0xFF626C38,
+0xFF4B5322,
+0xFF515825,
+0xFF7B804A,
+0xFF64672E,
+0xFF848549,
+0xFF6D7134,
+0xFF6F7338,
+0xFF767C40,
+0xFF585E20,
+0xFF777D3D,
+0xFF8A914E,
+0xFF848B48,
+0xFF979D5D,
+0xFF737C3B,
+0xFF7B8443,
+0xFF8F9A58,
+0xFF606D28,
+0xFFA6B36E,
+0xFF6E7E35,
+0xFF91A156,
+0xFF97A85A,
+0xFF7F8F46,
+0xFF737F41,
+0xFF4D581C,
+0xFF899555,
+0xFF6D7C39,
+0xFF737F3D,
+0xFF6C7B38,
+0xFF6B7A39,
+0xFF6D7B3D,
+0xFF6E7C41,
+0xFF67753A,
+0xFF7C8A4D,
+0xFF7E8A4C,
+0xFF859153,
+0xFF5F6B2D,
+0xFF828E50,
+0xFF6A7638,
+0xFF646F33,
+0xFF8D985E,
+0xFF505B23,
+0xFF616A35,
+0xFF858E59,
+0xFF646D38,
+0xFF5F6734,
+0xFF5C6435,
+0xFF60693C,
+0xFF4F5A2F,
+0xFF4B582C,
+0xFF637042,
+0xFF4F5D2C,
+0xFF505E2B,
+0xFF33400B,
+0xFF616E39,
+0xFF524D2F,
+0xFF2E2A0D,
+0xFF444327,
+0xFF404024,
+0xFF6F704E,
+0xFF616240,
+0xFF343515,
+0xFF3A391B,
+0xFF524E31,
+0xFF555233,
+0xFF484526,
+0xFF322F10,
+0xFF444428,
+0xFF42452A,
+0xFF7B8263,
+0xFF555A3A,
+0xFF4A492A,
+0xFF6D6A4B,
+0xFF555435,
+0xFF535434,
+0xFF3B3F1E,
+0xFF333917,
+0xFF505735,
+0xFF5C6341,
+0xFF252C0B,
+0xFF727958,
+0xFF272B10,
+0xFF30341B,
+0xFF1D1F0A,
+0xFF272516,
+0xFF1A160A,
+0xFF3C382C,
+0xFF32311D,
+0xFF1E2008,
+0xFF4A4D32,
+0xFF44472A,
+0xFF41452A,
+0xFF53583A,
+0xFF242909,
+0xFF545C37,
+0xFF5F673E,
+0xFF626940,
+0xFF4A502A,
+0xFF4B4E2F,
+0xFF22240E,
+0xFF535240,
+0xFF51503E,
+0xFF373624,
+0xFF4C4B36,
+0xFF46462C,
+0xFF7F7F63,
+0xFF48492A,
+0xFF616044,
+0xFF484728,
+0xFF73744A,
+0xFF5D5E34,
+0xFF5A593B,
+0xFF616147,
+0xFF3F3F23,
+0xFF4C502D,
+0xFF535830,
+0xFF484F26,
+0xFF666C48,
+0xFF626844,
+0xFF80855D,
+0xFF3F441B,
+0xFF394215,
+0xFF515C31,
+0xFF485430,
+0xFF343E19,
+0xFF374013,
+0xFF6A7344,
+0xFF848F64,
+0xFF010C00,
+0xFF1C2824,
+0xFF3A4450,
+0xFF282E46,
+0xFF2B2E4D,
+0xFF2B2847,
+0xFF35304E,
+0xFF2D2D47,
+0xFF26283D,
+0xFF232438,
+0xFF1E202F,
+0xFF161620,
+0xFF0E0E16,
+0xFF0A0B10,
+0xFF08090E,
+0xFF06070C,
+0xFF04080B,
+0xFF000200,
+0xFF4E5452,
+0xFF5E6472,
+0xFF40445F,
+0xFF3B3F62,
+0xFF34375A,
+0xFF2C2D4B,
+0xFF23233B,
+0xFF2A2B3F,
+0xFF292B3A,
+0xFF262739,
+0xFF323443,
+0xFF464855,
+0xFF262835,
+0xFF1E202F,
+0xFF212524,
+0xFFD1DCB4,
+0xFF5C6A2F,
+0xFF505F24,
+0xFF7B8A51,
+0xFF8E9D66,
+0xFF516029,
+0xFF85925C,
+0xFF808A55,
+0xFF5D6732,
+0xFF7D8651,
+0xFF6D7641,
+0xFFBCC491,
+0xFF5B6236,
+0xFF7D8458,
+0xFF818B59,
+0xFF97A16D,
+0xFF7E8856,
+0xFF3C4614,
+0xFF707A46,
+0xFF858D5A,
+0xFF81895A,
+0xFF5D6438,
+0xFF646D40,
+0xFF778351,
+0xFF56682E,
+0xFF91A365,
+0xFF65723A,
+0xFF515E28,
+0xFF576832,
+0xFF455821,
+0xFF4E6024,
+0xFF7C8B50,
+0xFF767F4A,
+0xFF525A29,
+0xFF677248,
+0xFF566136,
+0xFF696F3F,
+0xFF565A27,
+0xFF747D48,
+0xFF757E47,
+0xFF7C864A,
+0xFF858F52,
+0xFF626C2D,
+0xFF6F793D,
+0xFF6E7542,
+0xFF5F6539,
+0xFF545930,
+0xFF585E2E,
+0xFF50591A,
+0xFF717A37,
+0xFF8A9553,
+0xFF707A3B,
+0xFF7C8745,
+0xFF838E4C,
+0xFF9CA765,
+0xFFA1AB6C,
+0xFF99A269,
+0xFF808954,
+0xFF6B7340,
+0xFF474F1C,
+0xFF6B7543,
+0xFF4B5521,
+0xFF59632E,
+0xFF6F7A42,
+0xFF48521D,
+0xFF6A7442,
+0xFF717950,
+0xFF394118,
+0xFF909867,
+0xFF434D18,
+0xFF6E7846,
+0xFF798150,
+0xFF646B38,
+0xFF4D541E,
+0xFF82884C,
+0xFF858B4D,
+0xFF6A6F37,
+0xFF787D47,
+0xFF8D945E,
+0xFF6B743D,
+0xFF737C45,
+0xFF8A935A,
+0xFFB0BA7D,
+0xFF6B743B,
+0xFF5D6335,
+0xFFBDC397,
+0xFF636C37,
+0xFF6E763D,
+0xFF858853,
+0xFF545722,
+0xFF6D723C,
+0xFF727943,
+0xFF9DA66D,
+0xFF6F743A,
+0xFFA0A167,
+0xFF85844B,
+0xFF929158,
+0xFFA5A66C,
+0xFFB8B97F,
+0xFFADAE74,
+0xFF9F9D64,
+0xFF928F58,
+0xFF747742,
+0xFF5F6330,
+0xFF5A5E2B,
+0xFF8A8F59,
+0xFF8A8D58,
+0xFFAAAA74,
+0xFFAAA971,
+0xFFABAC73,
+0xFF7B7C42,
+0xFF8A8E51,
+0xFF7F8442,
+0xFF909753,
+0xFF9AA15B,
+0xFF88924B,
+0xFF99A35A,
+0xFF7C863F,
+0xFF6C7732,
+0xFF88934F,
+0xFFA5AF70,
+0xFF798344,
+0xFF838F4D,
+0xFFADBA75,
+0xFF94A15B,
+0xFF8B9757,
+0xFF828C58,
+0xFF7E875A,
+0xFF67713F,
+0xFF6E7846,
+0xFF6E7549,
+0xFF485021,
+0xFF656E35,
+0xFF949E61,
+0xFF7F8D50,
+0xFF87955A,
+0xFF748247,
+0xFF3B460C,
+0xFF859056,
+0xFF848D58,
+0xFF5C6433,
+0xFF5D6333,
+0xFF79804A,
+0xFFA4AC73,
+0xFF737745,
+0xFF616435,
+0xFF686B3C,
+0xFF4B4E1F,
+0xFF8F9567,
+0xFF757B4B,
+0xFF535B28,
+0xFF5D6532,
+0xFF545C29,
+0xFF4C5622,
+0xFF737D48,
+0xFF5D6A32,
+0xFF6C7A3F,
+0xFF5D6B30,
+0xFF6E7B45,
+0xFF4B5523,
+0xFF5A6233,
+0xFF757B4D,
+0xFF585C2A,
+0xFF5C5F2A,
+0xFF87884F,
+0xFF5D5E24,
+0xFF7D8047,
+0xFF5B5F24,
+0xFF6B6F34,
+0xFF8A8E51,
+0xFF7D8242,
+0xFF858A48,
+0xFF8C9252,
+0xFF818747,
+0xFF828B4C,
+0xFF889152,
+0xFF7D8846,
+0xFF84914C,
+0xFF7B8842,
+0xFF57671E,
+0xFFA8B96B,
+0xFF798940,
+0xFF94A062,
+0xFF7D884C,
+0xFF889454,
+0xFF5B6A27,
+0xFF788744,
+0xFF677635,
+0xFF6E7C3F,
+0xFF919F64,
+0xFF7E8B53,
+0xFF6F7D42,
+0xFF818C50,
+0xFF6E7A3C,
+0xFF808A4B,
+0xFF838D4E,
+0xFF949C60,
+0xFF7D854A,
+0xFF879057,
+0xFF6E7941,
+0xFF7D8651,
+0xFF868F5A,
+0xFF78814C,
+0xFF636B38,
+0xFF6A7241,
+0xFF444D1E,
+0xFF666F42,
+0xFF414C21,
+0xFF455226,
+0xFF435024,
+0xFF667244,
+0xFF4E5A2A,
+0xFF798351,
+0xFF46501C,
+0xFF494829,
+0xFF414022,
+0xFF505034,
+0xFF333617,
+0xFF6A6E4B,
+0xFF4B4F2C,
+0xFF454928,
+0xFF3B3C1D,
+0xFF333415,
+0xFF5C5B3C,
+0xFF3A391A,
+0xFF353616,
+0xFF373A1F,
+0xFF8C9075,
+0xFF3E4526,
+0xFF3D4321,
+0xFF565831,
+0xFF5D5E36,
+0xFF2C2C0A,
+0xFF4D4E2F,
+0xFF2E3116,
+0xFF2F3318,
+0xFF495031,
+0xFF353C1B,
+0xFF1B2200,
+0xFF515934,
+0xFF343A16,
+0xFF303614,
+0xFF4C4F34,
+0xFF555440,
+0xFF252316,
+0xFF131104,
+0xFF272611,
+0xFF404024,
+0xFF565A39,
+0xFF676B4A,
+0xFF8B8E71,
+0xFF22260D,
+0xFF60644D,
+0xFF2C3019,
+0xFF404429,
+0xFF4F5233,
+0xFF595D3C,
+0xFF282909,
+0xFF3E3E24,
+0xFF2F2D16,
+0xFF36341D,
+0xFF514F38,
+0xFF5B5B43,
+0xFF2E2E14,
+0xFF333415,
+0xFF5A5B3C,
+0xFF2F2F13,
+0xFF424323,
+0xFF676A3F,
+0xFF5A5D32,
+0xFF4C4D2E,
+0xFF5C5C40,
+0xFF454829,
+0xFF323814,
+0xFF3E451C,
+0xFF555E33,
+0xFF272F08,
+0xFF2A320D,
+0xFF828661,
+0xFF3C421C,
+0xFF202801,
+0xFF49542C,
+0xFF6C7651,
+0xFF5C673F,
+0xFF4E562D,
+0xFF30380F,
+0xFF69744A,
+0xFF424C33,
+0xFF424C4D,
+0xFF343D4E,
+0xFF2E344C,
+0xFF232742,
+0xFF2D2C4B,
+0xFF322F4E,
+0xFF292943,
+0xFF23253A,
+0xFF222335,
+0xFF212330,
+0xFF1B1B25,
+0xFF101018,
+0xFF090911,
+0xFF05060B,
+0xFF07080A,
+0xFF000500,
+0xFF0D1402,
+0xFF586051,
+0xFF6E757D,
+0xFF2B3046,
+0xFF2B2F52,
+0xFF2E3056,
+0xFF222244,
+0xFF1B1C38,
+0xFF18192E,
+0xFF1D1F2E,
+0xFF2A2C3B,
+0xFF2E303D,
+0xFF191B27,
+0xFF0F111D,
+0xFF131524,
+0xFF191D1C,
+0xFF38421D,
+0xFF2C3901,
+0xFFA8B87A,
+0xFF96A668,
+0xFF8B9B5D,
+0xFF6E7C3F,
+0xFF737E44,
+0xFF949D64,
+0xFF6D763F,
+0xFF757C48,
+0xFF2F3602,
+0xFF979D6D,
+0xFF6D744B,
+0xFF545B32,
+0xFF5D6639,
+0xFFA2AC7A,
+0xFFA6B282,
+0xFF465222,
+0xFF5D6939,
+0xFF9BA479,
+0xFF8A916F,
+0xFF262D0C,
+0xFF788059,
+0xFF637042,
+0xFF667741,
+0xFF85965F,
+0xFF66733D,
+0xFF86935E,
+0xFF5C6A37,
+0xFF6C7D47,
+0xFF697841,
+0xFF76834E,
+0xFF343A0A,
+0xFF8A9064,
+0xFF4F572E,
+0xFF565E35,
+0xFF585B30,
+0xFF828654,
+0xFF7A8249,
+0xFF81894E,
+0xFF6E763B,
+0xFF879051,
+0xFF76803B,
+0xFF78813E,
+0xFF798148,
+0xFF818854,
+0xFF737A46,
+0xFF7D854C,
+0xFF576021,
+0xFF7F8847,
+0xFF8B9455,
+0xFF80884C,
+0xFF7F894A,
+0xFF7E884B,
+0xFF98A065,
+0xFF525923,
+0xFF899160,
+0xFF798150,
+0xFF4C5421,
+0xFF656E37,
+0xFF737C43,
+0xFF646D34,
+0xFF5F6831,
+0xFF505922,
+0xFF47501B,
+0xFF646C39,
+0xFF586031,
+0xFF6A723F,
+0xFF697135,
+0xFF7E8849,
+0xFF6F793D,
+0xFF596229,
+0xFF555C26,
+0xFF565E22,
+0xFFA9B06A,
+0xFF7E853F,
+0xFF81874B,
+0xFF767B41,
+0xFF9CA468,
+0xFF959D62,
+0xFF6A713D,
+0xFFCCD39F,
+0xFF9BA36A,
+0xFF636A36,
+0xFFA3A580,
+0xFFA5A984,
+0xFFB1B885,
+0xFF7C844B,
+0xFF9B9E65,
+0xFF81844B,
+0xFF656B2F,
+0xFF7D8549,
+0xFF6C7536,
+0xFF919759,
+0xFF84854B,
+0xFF82834A,
+0xFF7C7D44,
+0xFFB2B37A,
+0xFF9E9F65,
+0xFFB1B276,
+0xFFB2B073,
+0xFFA3A367,
+0xFF787B42,
+0xFF7B824C,
+0xFF737842,
+0xFF939860,
+0xFF888B54,
+0xFF9A9D66,
+0xFFCACB92,
+0xFFA6A76E,
+0xFFB4B57B,
+0xFF787C3F,
+0xFF6A6E31,
+0xFFAFB575,
+0xFF9CA360,
+0xFF8F9855,
+0xFF808A45,
+0xFF7A8541,
+0xFF707A3B,
+0xFF737D3E,
+0xFF96A061,
+0xFF828C4D,
+0xFF94A060,
+0xFF8F9B59,
+0xFF85924C,
+0xFF788442,
+0xFF687138,
+0xFF7A834E,
+0xFF3C4510,
+0xFF737B4A,
+0xFF484C29,
+0xFF5B5F3C,
+0xFF72784A,
+0xFF929966,
+0xFF8B9360,
+0xFF646E39,
+0xFF7F8954,
+0xFF3F4813,
+0xFF525B26,
+0xFFC1C797,
+0xFFB6BB93,
+0xFF45471F,
+0xFF525624,
+0xFF676B38,
+0xFF606638,
+0xFF999E75,
+0xFF5D623A,
+0xFF6C7149,
+0xFFB4B990,
+0xFF42481C,
+0xFFA6AC7C,
+0xFF5E6633,
+0xFF626A37,
+0xFF6C7642,
+0xFF6C7642,
+0xFF919B66,
+0xFF59632F,
+0xFF646E3A,
+0xFF687240,
+0xFF5D6637,
+0xFF6E7647,
+0xFF666C3E,
+0xFF4E5220,
+0xFF5E622F,
+0xFF797C47,
+0xFF959861,
+0xFF8C8F56,
+0xFF7E8247,
+0xFF888C51,
+0xFF8D9154,
+0xFF767B3B,
+0xFF808545,
+0xFF969C5E,
+0xFF909658,
+0xFF9FA569,
+0xFF8D9559,
+0xFF899155,
+0xFF737D3E,
+0xFF85904E,
+0xFF83904B,
+0xFFA7B46E,
+0xFF687530,
+0xFF657131,
+0xFFA2AC6F,
+0xFF757F40,
+0xFF586424,
+0xFF4F5B1D,
+0xFF7F8A4E,
+0xFF727D45,
+0xFF828D55,
+0xFF7C874F,
+0xFF7F8A4E,
+0xFF7D874A,
+0xFF869051,
+0xFF868F50,
+0xFF80884C,
+0xFF949961,
+0xFF848B55,
+0xFF77804B,
+0xFF939D69,
+0xFF7A824F,
+0xFF8B9360,
+0xFF4C5421,
+0xFF828A57,
+0xFF676F3C,
+0xFF535D2B,
+0xFF4C5624,
+0xFF5B6737,
+0xFF6B7948,
+0xFF4A5729,
+0xFF525E30,
+0xFF5E6A3C,
+0xFF404C1E,
+0xFF546032,
+0xFF525635,
+0xFF515534,
+0xFF404324,
+0xFF434627,
+0xFF4D532F,
+0xFF505632,
+0xFF5A5E3D,
+0xFF424526,
+0xFF4B4E2F,
+0xFF616445,
+0xFF353918,
+0xFF656948,
+0xFF64684D,
+0xFF5B5F44,
+0xFF656C4D,
+0xFF373D19,
+0xFF8A8D62,
+0xFF53562B,
+0xFF6B6D48,
+0xFF414524,
+0xFF2B3012,
+0xFF32361B,
+0xFF5C6246,
+0xFF414829,
+0xFF525937,
+0xFF323A15,
+0xFF3D431F,
+0xFF313715,
+0xFF4C4F30,
+0xFF25280D,
+0xFF252712,
+0xFF383723,
+0xFF37371D,
+0xFF4F5030,
+0xFF656944,
+0xFF939774,
+0xFF383B1E,
+0xFF4C4E38,
+0xFF6D705D,
+0xFF222512,
+0xFF1F210B,
+0xFF24270A,
+0xFF343515,
+0xFF191A00,
+0xFF302F11,
+0xFF343317,
+0xFF37361A,
+0xFF262509,
+0xFF54543A,
+0xFF4F4F33,
+0xFF1F2000,
+0xFF666747,
+0xFF747556,
+0xFF8C8D6D,
+0xFF4A4D22,
+0xFF909368,
+0xFF5B5C3C,
+0xFF5A5D40,
+0xFF4B5030,
+0xFF818763,
+0xFF7C855A,
+0xFF899267,
+0xFF646F47,
+0xFF555D38,
+0xFF979D79,
+0xFF434925,
+0xFF39401E,
+0xFF4B5532,
+0xFF5B663E,
+0xFF444C25,
+0xFF636943,
+0xFF3F4521,
+0xFF7A815F,
+0xFF49523D,
+0xFF3E474E,
+0xFF2A3247,
+0xFF21273D,
+0xFF252942,
+0xFF333251,
+0xFF31304F,
+0xFF292B44,
+0xFF202237,
+0xFF1A1B2D,
+0xFF181A27,
+0xFF13131D,
+0xFF0C0C14,
+0xFF090913,
+0xFF08090E,
+0xFF080A07,
+0xFF000400,
+0xFF616C4C,
+0xFF737D64,
+0xFF4D5557,
+0xFF363D50,
+0xFF323757,
+0xFF282C51,
+0xFF292C4B,
+0xFF2B2D46,
+0xFF212236,
+0xFF1B1D2C,
+0xFF111322,
+0xFF151724,
+0xFF141720,
+0xFF1A1D26,
+0xFF0D0F1C,
+0xFF101511,
+0xFF707A55,
+0xFFA2AF77,
+0xFF58682A,
+0xFF829254,
+0xFF8D9D5F,
+0xFF667439,
+0xFF8E9762,
+0xFF525828,
+0xFF646A3A,
+0xFF6F7545,
+0xFF808354,
+0xFF818759,
+0xFF4B4F2A,
+0xFF454B25,
+0xFF697247,
+0xFF838F5F,
+0xFF2F3D0C,
+0xFF6A7847,
+0xFF303E0D,
+0xFF2A350A,
+0xFF1C2603,
+0xFF141E00,
+0xFF37411C,
+0xFF323F13,
+0xFF4F5F2E,
+0xFF4E5F2B,
+0xFF818D5B,
+0xFF5E6A38,
+0xFF52602D,
+0xFF6B7946,
+0xFF6A7847,
+0xFF515A2B,
+0xFF4D5327,
+0xFF62673F,
+0xFF525832,
+0xFF656B45,
+0xFF676942,
+0xFF626337,
+0xFF8F945E,
+0xFF5A6227,
+0xFF7B834A,
+0xFFA3AB70,
+0xFF88914E,
+0xFF707A35,
+0xFF80854B,
+0xFF8C945B,
+0xFF5C6428,
+0xFF949D5E,
+0xFF7C8546,
+0xFF5B6327,
+0xFF586025,
+0xFF7C8449,
+0xFF8B9559,
+0xFF636D31,
+0xFF7B834A,
+0xFFB7BE8A,
+0xFF868E5F,
+0xFF394112,
+0xFF505924,
+0xFF889158,
+0xFF879154,
+0xFF525C20,
+0xFF757E45,
+0xFF808751,
+0xFF6D743E,
+0xFF848B55,
+0xFF7E824F,
+0xFF5F642C,
+0xFF616727,
+0xFF767F3C,
+0xFF848D4E,
+0xFF697336,
+0xFF7E864B,
+0xFF92985A,
+0xFF808741,
+0xFF676E28,
+0xFF75793C,
+0xFF7E8349,
+0xFF696F33,
+0xFF8C9459,
+0xFF8F9660,
+0xFFA9B07A,
+0xFFB9C186,
+0xFFA0A771,
+0xFF74764E,
+0xFF888A62,
+0xFF8A8E5B,
+0xFFA8AD73,
+0xFF83894D,
+0xFF888E50,
+0xFFAAB072,
+0xFF6D7635,
+0xFF737C3B,
+0xFF717739,
+0xFF8D9156,
+0xFF7E8148,
+0xFF8A8D54,
+0xFFAFB077,
+0xFF9A9B61,
+0xFF929357,
+0xFF9F9F5F,
+0xFFA5A768,
+0xFF696F33,
+0xFF626A2F,
+0xFF8C9459,
+0xFF91965E,
+0xFF898E56,
+0xFFA9AC75,
+0xFF696C33,
+0xFF8D9057,
+0xFF85884F,
+0xFF646A2E,
+0xFF63692D,
+0xFF8C9458,
+0xFFB5BE7F,
+0xFF818B4C,
+0xFF687331,
+0xFF828C4D,
+0xFF6F793D,
+0xFF6F793D,
+0xFF858F53,
+0xFF768043,
+0xFF586426,
+0xFF788444,
+0xFFA5B16F,
+0xFF8C9755,
+0xFF727C3F,
+0xFF6D753A,
+0xFF6E763D,
+0xFF73794B,
+0xFF38391A,
+0xFF49492F,
+0xFF494A28,
+0xFF686A42,
+0xFF6B7145,
+0xFF686E42,
+0xFF5B6133,
+0xFF545A2C,
+0xFF898C5F,
+0xFFC6C8A0,
+0xFF7D7E5C,
+0xFF3E3F1D,
+0xFF64673C,
+0xFF4A4D20,
+0xFF43451E,
+0xFF545833,
+0xFF585C39,
+0xFF393D1A,
+0xFF535732,
+0xFF767B52,
+0xFF93996B,
+0xFF6D7343,
+0xFF777F4C,
+0xFF5A622F,
+0xFF6E7645,
+0xFF798351,
+0xFF737B4C,
+0xFF30390C,
+0xFF30370D,
+0xFF5B6236,
+0xFF505829,
+0xFF5B6131,
+0xFF7A814E,
+0xFF868A58,
+0xFF898D5B,
+0xFF626633,
+0xFF989D65,
+0xFF73783E,
+0xFF868A4F,
+0xFF747A3C,
+0xFF767A3D,
+0xFF9BA163,
+0xFF676D2F,
+0xFF91975B,
+0xFF74793F,
+0xFF474C14,
+0xFF949C63,
+0xFF767E43,
+0xFF7F874C,
+0xFF707A3D,
+0xFF687233,
+0xFF717B3C,
+0xFF697336,
+0xFF808A4D,
+0xFF8C9659,
+0xFF535D20,
+0xFF697239,
+0xFF7C874F,
+0xFF717B46,
+0xFF79834E,
+0xFF77824A,
+0xFF6B763A,
+0xFF6C7637,
+0xFF929C5D,
+0xFF656E2F,
+0xFF848C51,
+0xFF848953,
+0xFF9DA471,
+0xFF7F8756,
+0xFF5A6432,
+0xFF858D5C,
+0xFF535B2A,
+0xFF626A39,
+0xFF707847,
+0xFF666E3D,
+0xFF707A46,
+0xFF76804C,
+0xFF84915C,
+0xFF586633,
+0xFF475524,
+0xFF768254,
+0xFF566234,
+0xFF495429,
+0xFF4F5A30,
+0xFF313713,
+0xFF626846,
+0xFF282D0D,
+0xFF5C6141,
+0xFF4A4E2B,
+0xFF494D2A,
+0xFF1E2201,
+0xFF424526,
+0xFF515638,
+0xFF4E5333,
+0xFF4A512F,
+0xFF777E5D,
+0xFF82886C,
+0xFF20260A,
+0xFF43482A,
+0xFF292F0D,
+0xFF7A7F56,
+0xFF4F5529,
+0xFF5F643B,
+0xFF4F532E,
+0xFF494F2B,
+0xFF5A603E,
+0xFF585D3D,
+0xFF585D3F,
+0xFF222709,
+0xFF1B2002,
+0xFF252A0C,
+0xFF454A2C,
+0xFF2E3313,
+0xFF313715,
+0xFF3D4321,
+0xFF7F8362,
+0xFF686949,
+0xFF6B6C4A,
+0xFF353614,
+0xFF494A2A,
+0xFF54573C,
+0xFF646650,
+0xFF797B66,
+0xFF6D6F59,
+0xFF77775D,
+0xFF5E5F40,
+0xFF676648,
+0xFF3D3C1E,
+0xFF4E4A2F,
+0xFF545033,
+0xFF535031,
+0xFF423F20,
+0xFF555637,
+0xFF383B1C,
+0xFF515532,
+0xFF656946,
+0xFF4D5031,
+0xFF565A37,
+0xFF757B4F,
+0xFF343A0E,
+0xFF414522,
+0xFF323516,
+0xFF444A28,
+0xFF4C522E,
+0xFF5E663D,
+0xFF2F3A10,
+0xFF87926A,
+0xFF58603B,
+0xFF353B17,
+0xFF515735,
+0xFF3F4627,
+0xFF3E4524,
+0xFF363E17,
+0xFF6E764D,
+0xFF474D29,
+0xFF393E1E,
+0xFF50563C,
+0xFF53594D,
+0xFF333947,
+0xFF21273F,
+0xFF22283E,
+0xFF272C42,
+0xFF2E2F4B,
+0xFF30304C,
+0xFF26283F,
+0xFF1C1F32,
+0xFF171928,
+0xFF141622,
+0xFF12121C,
+0xFF0D0D15,
+0xFF0A0A14,
+0xFF090A0F,
+0xFF000600,
+0xFF081000,
+0xFF6F7C50,
+0xFF77835F,
+0xFF4D5651,
+0xFF363D4F,
+0xFF313656,
+0xFF262A4D,
+0xFF1C2039,
+0xFF1F2235,
+0xFF16192A,
+0xFF111423,
+0xFF131426,
+0xFF111322,
+0xFF222430,
+0xFF11141D,
+0xFF070A13,
+0xFF0D120B,
+0xFF8D986E,
+0xFF8B995E,
+0xFF5D6B30,
+0xFFAFBC84,
+0xFF5A6732,
+0xFF737C4F,
+0xFF434724,
+0xFF575839,
+0xFF525333,
+0xFF565833,
+0xFF66673F,
+0xFF4B4D25,
+0xFF5A5E39,
+0xFF656B45,
+0xFF636C41,
+0xFF4E5A2C,
+0xFF1B2800,
+0xFF6A7749,
+0xFF687643,
+0xFF414F1C,
+0xFF475426,
+0xFF586338,
+0xFF4E592F,
+0xFF3E4B20,
+0xFF3B4A1F,
+0xFF3A471B,
+0xFF465224,
+0xFF404C1C,
+0xFF404E1D,
+0xFF4D5A2C,
+0xFF505B30,
+0xFF485027,
+0xFF434722,
+0xFF5B5D38,
+0xFF4A4E2B,
+0xFF6C704D,
+0xFF545432,
+0xFF4D4D27,
+0xFF686B3C,
+0xFF595D2A,
+0xFF424516,
+0xFF818552,
+0xFF6C7236,
+0xFF8A9050,
+0xFF9DA067,
+0xFF6A6F35,
+0xFF7D8345,
+0xFF717739,
+0xFF6E7438,
+0xFF7B8048,
+0xFF929963,
+0xFFA0A773,
+0xFF6F7640,
+0xFF788047,
+0xFF646C31,
+0xFF99A06A,
+0xFF454B1D,
+0xFF5E6436,
+0xFF59602A,
+0xFF6A7237,
+0xFF6C7438,
+0xFF444C10,
+0xFF50581F,
+0xFF767B43,
+0xFF4D5218,
+0xFF7D8347,
+0xFF767940,
+0xFF55581F,
+0xFF7C8045,
+0xFF898D52,
+0xFF646C30,
+0xFF757D41,
+0xFF7E8349,
+0xFF6A7034,
+0xFF55591C,
+0xFF606427,
+0xFF85864D,
+0xFF63662F,
+0xFF666B35,
+0xFF636832,
+0xFF959A62,
+0xFFBEC488,
+0xFFAAB070,
+0xFFB5BB7B,
+0xFF80834A,
+0xFF8D9059,
+0xFF7D8047,
+0xFF8A9054,
+0xFFB1B779,
+0xFF787E40,
+0xFFBDC385,
+0xFF676D2F,
+0xFF8B9153,
+0xFF969C5E,
+0xFF73793D,
+0xFF919759,
+0xFF808648,
+0xFFB7BB7E,
+0xFF9FA064,
+0xFFAFB172,
+0xFF8B8D4E,
+0xFF63672A,
+0xFF80894A,
+0xFF6E783B,
+0xFF7B8548,
+0xFF969E63,
+0xFF9FA76C,
+0xFF9CA167,
+0xFF989D63,
+0xFF676C32,
+0xFF53581E,
+0xFF53581E,
+0xFF585D23,
+0xFF8B9358,
+0xFF8D955A,
+0xFF596327,
+0xFF707A3E,
+0xFF859054,
+0xFF656E37,
+0xFF929B64,
+0xFF5F6831,
+0xFF475019,
+0xFF6F7841,
+0xFF4B541B,
+0xFF879152,
+0xFF7F8849,
+0xFF5D6627,
+0xFF82884C,
+0xFF7D824A,
+0xFF6E7144,
+0xFF232206,
+0xFF5E5C45,
+0xFF5D5C40,
+0xFF434223,
+0xFF545432,
+0xFF4F4F2D,
+0xFF31310F,
+0xFF3E3E1A,
+0xFF2D2D09,
+0xFF2E2E0C,
+0xFF727153,
+0xFF383719,
+0xFF5D5D37,
+0xFF33350E,
+0xFF5E5F3D,
+0xFF4C4D2D,
+0xFF515532,
+0xFF474B28,
+0xFF444A26,
+0xFF585F36,
+0xFF737A4E,
+0xFF697140,
+0xFF616936,
+0xFF4D5522,
+0xFF535B2C,
+0xFF7B8256,
+0xFF4C5129,
+0xFF505630,
+0xFF494D28,
+0xFF646B41,
+0xFF4D5526,
+0xFF626A37,
+0xFF6F7744,
+0xFF565C2C,
+0xFF5D6335,
+0xFF656B3B,
+0xFF787F49,
+0xFF646C31,
+0xFF90965A,
+0xFFA0A86C,
+0xFF878D51,
+0xFF80864A,
+0xFF7B8145,
+0xFF63682E,
+0xFF676C34,
+0xFF6B703A,
+0xFF7A7F49,
+0xFF777C46,
+0xFF636832,
+0xFF6F773E,
+0xFF586025,
+0xFF687035,
+0xFF687035,
+0xFF737B3F,
+0xFF858D51,
+0xFF879154,
+0xFF677037,
+0xFF636C35,
+0xFF535C27,
+0xFF7E8752,
+0xFF606932,
+0xFF8A935A,
+0xFF6F773B,
+0xFF70793A,
+0xFF3E460A,
+0xFF6E763D,
+0xFF8E925F,
+0xFF6E7444,
+0xFF929A69,
+0xFF444E1C,
+0xFF4E5627,
+0xFF495024,
+0xFF6A7145,
+0xFF5B6236,
+0xFF666E3F,
+0xFF737D4B,
+0xFF757F4B,
+0xFF8A9762,
+0xFF45531E,
+0xFF6A7845,
+0xFF5F6B3B,
+0xFF1E2900,
+0xFF333E14,
+0xFF444F27,
+0xFF343A16,
+0xFF6D7351,
+0xFF4E5333,
+0xFF424526,
+0xFF5B5C3A,
+0xFF343513,
+0xFF3B3C1C,
+0xFF2B2E0F,
+0xFF2C3113,
+0xFF353C1B,
+0xFF636D4B,
+0xFF7A8462,
+0xFF3A4024,
+0xFF21270D,
+0xFF2E3217,
+0xFF383D1D,
+0xFF797D5A,
+0xFF3C401B,
+0xFF636840,
+0xFF373C14,
+0xFF3F461D,
+0xFF383F16,
+0xFF454B25,
+0xFF8D936F,
+0xFF757A5A,
+0xFF7E8365,
+0xFF23270C,
+0xFF44482D,
+0xFF595E3E,
+0xFF515735,
+0xFF8D936D,
+0xFF737953,
+0xFF777B58,
+0xFF3F401E,
+0xFF3B3C1A,
+0xFF656647,
+0xFF3D4025,
+0xFF20220C,
+0xFF41432D,
+0xFF5A5D42,
+0xFF5D5E3F,
+0xFF6B6C4C,
+0xFF79785A,
+0xFFA3A284,
+0xFF979378,
+0xFF747053,
+0xFF9D9976,
+0xFF8C8966,
+0xFF454926,
+0xFF3B411D,
+0xFF4D532D,
+0xFF5A603A,
+0xFF797F5D,
+0xFF555936,
+0xFF42481C,
+0xFF3B4115,
+0xFF50542F,
+0xFF4E5231,
+0xFF505634,
+0xFF5D633F,
+0xFF4B532A,
+0xFF384319,
+0xFF979F7A,
+0xFF303715,
+0xFF383F1D,
+0xFF585D3D,
+0xFF636A49,
+0xFF545B39,
+0xFF505831,
+0xFF424920,
+0xFF535734,
+0xFF464A2F,
+0xFF383B2A,
+0xFF4F5352,
+0xFF2B3141,
+0xFF1A203A,
+0xFF272D45,
+0xFF2F334C,
+0xFF2D2E4A,
+0xFF32334F,
+0xFF1D1F36,
+0xFF171A2D,
+0xFF161827,
+0xFF151723,
+0xFF14141E,
+0xFF0F0F17,
+0xFF090913,
+0xFF050608,
+0xFF000400,
+0xFF485230,
+0xFF798754,
+0xFF738257,
+0xFF434D45,
+0xFF272E40,
+0xFF323956,
+0xFF303555,
+0xFF2C3049,
+0xFF1D2033,
+0xFF232637,
+0xFF2A2D3E,
+0xFF313244,
+0xFF313244,
+0xFF1D1F2C,
+0xFF060814,
+0xFF0B0E17,
+0xFF060B04,
+0xFF5B663E,
+0xFF67743E,
+0xFF73804A,
+0xFF94A16C,
+0xFF3F4B1B,
+0xFF252D04,
+0xFF44472A,
+0xFF515139,
+0xFF48462F,
+0xFF3F3E22,
+0xFF50502E,
+0xFF7D7F5A,
+0xFF8B8F6A,
+0xFF5D643B,
+0xFF5E6738,
+0xFF4E5A2A,
+0xFF455224,
+0xFF515E30,
+0xFF687945,
+0xFF6A7B45,
+0xFF7F8D58,
+0xFF576534,
+0xFF758056,
+0xFF2D3810,
+0xFF4C5830,
+0xFF38451A,
+0xFF313C11,
+0xFF616A3D,
+0xFF535F31,
+0xFF6A754A,
+0xFF50582F,
+0xFF5C623C,
+0xFF4A4B29,
+0xFF535432,
+0xFF5D5E3C,
+0xFF555634,
+0xFF7D7A5B,
+0xFF464320,
+0xFF65663C,
+0xFF777A4D,
+0xFF5B5D35,
+0xFF7B7E51,
+0xFF6B6D3B,
+0xFFA4A770,
+0xFF82854C,
+0xFF6E7237,
+0xFF7B8143,
+0xFF6D7335,
+0xFF73783E,
+0xFF868B53,
+0xFF6C733F,
+0xFF79804D,
+0xFF5F6632,
+0xFF7A814B,
+0xFF4D551A,
+0xFF6D743E,
+0xFF93996B,
+0xFF7F8557,
+0xFF767D47,
+0xFFA2AA6F,
+0xFF60682D,
+0xFF777F44,
+0xFF858A54,
+0xFF757A42,
+0xFF878B50,
+0xFF56571B,
+0xFF5B5C22,
+0xFF8E8F56,
+0xFF777640,
+0xFF6E6E38,
+0xFF73783E,
+0xFF858B4F,
+0xFF73763D,
+0xFF75783F,
+0xFF6F7036,
+0xFF717238,
+0xFF898953,
+0xFF83834F,
+0xFF9C9E6C,
+0xFF5D622C,
+0xFFA7AC72,
+0xFF858B4D,
+0xFFB0B773,
+0xFFA2A965,
+0xFFB0B676,
+0xFF6C7033,
+0xFFA8AC6F,
+0xFF6D7134,
+0xFFB2BB7C,
+0xFFB2BB7C,
+0xFF92985C,
+0xFFA3A96D,
+0xFF9B9E65,
+0xFF8F9358,
+0xFF60682C,
+0xFF9BA465,
+0xFF7B8443,
+0xFFC6CC8C,
+0xFF9EA363,
+0xFFACAD71,
+0xFF73773C,
+0xFF70763A,
+0xFFA9B374,
+0xFF626C2D,
+0xFF5B6528,
+0xFF929C5F,
+0xFF9AA267,
+0xFF90985D,
+0xFF71763C,
+0xFF72773D,
+0xFF838850,
+0xFF7E864D,
+0xFF6F773E,
+0xFF616A33,
+0xFF626B34,
+0xFF6D7840,
+0xFF848F57,
+0xFF87925A,
+0xFF5D662F,
+0xFF555E29,
+0xFF697140,
+0xFF616938,
+0xFF646C39,
+0xFF5E6531,
+0xFF676F36,
+0xFF7E8349,
+0xFF777C42,
+0xFF72753E,
+0xFF6C6C3A,
+0xFF98966D,
+0xFF2F2A0D,
+0xFF140E00,
+0xFF534D33,
+0xFF676245,
+0xFF817C5F,
+0xFF3E391C,
+0xFFB3AD93,
+0xFF332D13,
+0xFF817C5C,
+0xFF423F1E,
+0xFF7A7758,
+0xFF515031,
+0xFF80805C,
+0xFF61613B,
+0xFF3A3B19,
+0xFF797B56,
+0xFFA0A57C,
+0xFF4F5529,
+0xFF474E24,
+0xFF7F865C,
+0xFF4B5324,
+0xFF6A7241,
+0xFF57602B,
+0xFF929A67,
+0xFF747A4C,
+0xFF50552D,
+0xFF3B3F1C,
+0xFF2C300D,
+0xFF525631,
+0xFF71784E,
+0xFF525A29,
+0xFF58602D,
+0xFF7B8350,
+0xFF656F3D,
+0xFF454E21,
+0xFF596233,
+0xFF88915A,
+0xFF6B7539,
+0xFF3D470B,
+0xFF889255,
+0xFFA7B175,
+0xFF61692E,
+0xFF71793E,
+0xFF575C24,
+0xFF727741,
+0xFF7D824C,
+0xFF696D3A,
+0xFF767A47,
+0xFF868A57,
+0xFF6A6E3B,
+0xFF6C713B,
+0xFF797E48,
+0xFF666E35,
+0xFF717940,
+0xFF757D42,
+0xFF6F773C,
+0xFF5D662D,
+0xFF555E27,
+0xFF7A834E,
+0xFF6D7641,
+0xFF6D7641,
+0xFF88915A,
+0xFF646C31,
+0xFF7D854A,
+0xFF81894E,
+0xFF6C743B,
+0xFF767D4A,
+0xFF6E7542,
+0xFF6D7542,
+0xFF737D4B,
+0xFF424A1B,
+0xFF6D7448,
+0xFF7A8158,
+0xFF61683F,
+0xFF383F15,
+0xFF7B8457,
+0xFF5E6A38,
+0xFF677341,
+0xFF5B6934,
+0xFF768451,
+0xFF475323,
+0xFF444F24,
+0xFF515C32,
+0xFF505B33,
+0xFF4B4F2C,
+0xFF565A39,
+0xFF525334,
+0xFF363517,
+0xFF514E2D,
+0xFF3E3B1A,
+0xFF5D5C3D,
+0xFF3C3D1E,
+0xFF383D1F,
+0xFF5A6140,
+0xFF66704E,
+0xFF626C4A,
+0xFF3D4329,
+0xFF1A2006,
+0xFF25290E,
+0xFF161900,
+0xFFA1A489,
+0xFF36391C,
+0xFF3F4322,
+0xFF4E522D,
+0xFF70764A,
+0xFF4B5121,
+0xFF505628,
+0xFF82885C,
+0xFF42471F,
+0xFF8E926F,
+0xFF262B0B,
+0xFF313618,
+0xFF3A4122,
+0xFF6C7352,
+0xFF3E4524,
+0xFF393F1D,
+0xFF464A27,
+0xFF565A37,
+0xFF3A3E1D,
+0xFF595C3D,
+0xFF404328,
+0xFF32351A,
+0xFF4A4D32,
+0xFF3B3E1F,
+0xFF565735,
+0xFFA1A37E,
+0xFF434223,
+0xFF535233,
+0xFF6A6649,
+0xFF7E7B5C,
+0xFF908E68,
+0xFF7D7E56,
+0xFF747B52,
+0xFF565E35,
+0xFF2D360B,
+0xFF757E53,
+0xFF656D46,
+0xFF5C623C,
+0xFF575E34,
+0xFF5D6438,
+0xFF5D633D,
+0xFF646A46,
+0xFF6B714F,
+0xFFAAB08E,
+0xFF414721,
+0xFF878F68,
+0xFF3E4422,
+0xFF2A3110,
+0xFF555C3B,
+0xFF515836,
+0xFF7E8462,
+0xFFA4AA86,
+0xFF8B916B,
+0xFF5B5F3A,
+0xFF3C401B,
+0xFF3E4227,
+0xFF4A4B45,
+0xFF3D4049,
+0xFF282B3E,
+0xFF21253E,
+0xFF262C46,
+0xFF2C324C,
+0xFF313550,
+0xFF262841,
+0xFF191B30,
+0xFF131627,
+0xFF10121F,
+0xFF0D1019,
+0xFF0B0B13,
+0xFF0A0B10,
+0xFF08090E,
+0xFF030502,
+0xFF2A321B,
+0xFF68734B,
+0xFF899861,
+0xFF849467,
+0xFF727B76,
+0xFF2F3648,
+0xFF262D49,
+0xFF262B49,
+0xFF1D213C,
+0xFF292B42,
+0xFF282A3F,
+0xFF191C2F,
+0xFF1F2032,
+0xFF262837,
+0xFF030512,
+0xFF0F111D,
+0xFF0B0B17,
+0xFF090B08,
+0xFF656C4B,
+0xFF636C3D,
+0xFFA7B17F,
+0xFF596331,
+0xFF344010,
+0xFF80895E,
+0xFF989E7A,
+0xFF424526,
+0xFF2B2B13,
+0xFF36361E,
+0xFF49492D,
+0xFF696A4A,
+0xFF555934,
+0xFF767D51,
+0xFF67713C,
+0xFF5C6933,
+0xFF5C693B,
+0xFF313E12,
+0xFF6F7C4E,
+0xFF72804F,
+0xFF434F1D,
+0xFF556131,
+0xFF646F45,
+0xFF27320A,
+0xFF626F44,
+0xFF202D01,
+0xFF697547,
+0xFF586134,
+0xFF374015,
+0xFF969F74,
+0xFF60683F,
+0xFF5F653F,
+0xFF70714F,
+0xFF535331,
+0xFF4B4A2B,
+0xFF5E5D3E,
+0xFF807D5C,
+0xFF8B8867,
+0xFF696945,
+0xFF51512D,
+0xFF585834,
+0xFF4C4C26,
+0xFF5C5D33,
+0xFF5F6132,
+0xFF7D804B,
+0xFF80834A,
+0xFF65682F,
+0xFF9A9E63,
+0xFF797F43,
+0xFF676C32,
+0xFF757946,
+0xFF818552,
+0xFF9DA46E,
+0xFF777F46,
+0xFF646C33,
+0xFF616834,
+0xFF5D6333,
+0xFF858B5B,
+0xFF7F8650,
+0xFF747C43,
+0xFF565B25,
+0xFF777B48,
+0xFF585A28,
+0xFF7C7F4A,
+0xFF7C7D43,
+0xFFA7A86E,
+0xFF77763E,
+0xFF9A9865,
+0xFF7B7748,
+0xFF838150,
+0xFF7B7C43,
+0xFF61642B,
+0xFF7B7B45,
+0xFF888751,
+0xFF9A9A5E,
+0xFF4C4C10,
+0xFF5B5A22,
+0xFF8F8F59,
+0xFF7C7F46,
+0xFF8B9056,
+0xFF9EA369,
+0xFFACB478,
+0xFF98A15E,
+0xFFABB570,
+0xFF868F50,
+0xFF93995D,
+0xFF696D30,
+0xFF575B1E,
+0xFFA5AD71,
+0xFFA3AB6F,
+0xFF959A60,
+0xFF70753B,
+0xFF898C55,
+0xFF777A43,
+0xFF7C8448,
+0xFFACB677,
+0xFF8C9554,
+0xFFA5AB6B,
+0xFF828747,
+0xFF979B60,
+0xFF878C54,
+0xFF6B743B,
+0xFF919B5E,
+0xFF737F3F,
+0xFF929E60,
+0xFF99A567,
+0xFF8E985C,
+0xFF697337,
+0xFF99A168,
+0xFF6B733A,
+0xFF69703A,
+0xFF6E753F,
+0xFF555C26,
+0xFF6D7641,
+0xFF6E7742,
+0xFFB4BE89,
+0xFF656F3A,
+0xFF98A26D,
+0xFF2F3801,
+0xFF949B67,
+0xFF585E32,
+0xFF71764D,
+0xFF686E42,
+0xFF7C7F50,
+0xFF787C49,
+0xFF727442,
+0xFF6F6E40,
+0xFF656438,
+0xFF6A673C,
+0xFF77734D,
+0xFF766F52,
+0xFF4F482E,
+0xFF6D6348,
+0xFF8A8065,
+0xFF8E8469,
+0xFF7F755C,
+0xFF847C69,
+0xFF7F7762,
+0xFF6E6848,
+0xFF75714C,
+0xFF8D8963,
+0xFF504E27,
+0xFF5B5C34,
+0xFF4F5028,
+0xFF54562E,
+0xFF949768,
+0xFF7D854C,
+0xFF969E63,
+0xFF525B24,
+0xFF6E7643,
+0xFF78824E,
+0xFF656F3A,
+0xFF525B26,
+0xFF5A622F,
+0xFF646A3E,
+0xFF3F431E,
+0xFF3A3E1D,
+0xFF4A4E2B,
+0xFF5A6138,
+0xFF4A5125,
+0xFF69713E,
+0xFF68723E,
+0xFF737D49,
+0xFF5D6937,
+0xFF5B6739,
+0xFF3A4616,
+0xFF657038,
+0xFF747F45,
+0xFF879258,
+0xFF838E52,
+0xFF6F7A40,
+0xFF828B52,
+0xFF697239,
+0xFF80884F,
+0xFF4D541E,
+0xFF787F4B,
+0xFF7C804D,
+0xFF4A4E1B,
+0xFF939564,
+0xFF757746,
+0xFF818351,
+0xFF929663,
+0xFF626936,
+0xFF606733,
+0xFF7A8249,
+0xFF5E662B,
+0xFF687034,
+0xFF5F672C,
+0xFF7F8851,
+0xFF6E7742,
+0xFF666E3B,
+0xFF7B8350,
+0xFF6C753E,
+0xFF7D864F,
+0xFF818A53,
+0xFF737C45,
+0xFF5E6732,
+0xFF747D48,
+0xFF717B46,
+0xFF616B37,
+0xFF626A3B,
+0xFF4B5228,
+0xFF626842,
+0xFF484E2A,
+0xFF5E663F,
+0xFF5B633A,
+0xFF525E30,
+0xFF394515,
+0xFF768451,
+0xFF505E2B,
+0xFF7B8757,
+0xFF556133,
+0xFF5D663B,
+0xFF515930,
+0xFF474725,
+0xFF393917,
+0xFF4C482B,
+0xFF464124,
+0xFF4D4727,
+0xFF635E3E,
+0xFF7F7C5D,
+0xFF1C1D00,
+0xFF6B7052,
+0xFF6D7453,
+0xFF2B3512,
+0xFF5A6442,
+0xFF2C3218,
+0xFF3A3E25,
+0xFF2E3116,
+0xFF52553A,
+0xFF35371F,
+0xFF5B5D45,
+0xFF4A4D2E,
+0xFF555934,
+0xFF292F03,
+0xFF515425,
+0xFF434617,
+0xFF45481B,
+0xFF676941,
+0xFF60643F,
+0xFF313415,
+0xFF282D0D,
+0xFF464B2D,
+0xFF737A59,
+0xFF484F2E,
+0xFF343B19,
+0xFF454B27,
+0xFF444A26,
+0xFF5C603B,
+0xFF282E0A,
+0xFF4E5132,
+0xFF525739,
+0xFF313417,
+0xFF2C2F10,
+0xFF7B7F5A,
+0xFF767851,
+0xFFABAD88,
+0xFF40401E,
+0xFF484826,
+0xFF848460,
+0xFF57552C,
+0xFFADB083,
+0xFF414A1F,
+0xFF667347,
+0xFF5F6C3E,
+0xFF8B9769,
+0xFF313C12,
+0xFF525A31,
+0xFF41481E,
+0xFF99A076,
+0xFF434A21,
+0xFF4A502A,
+0xFF404624,
+0xFF2D3011,
+0xFF202401,
+0xFF585C39,
+0xFF606344,
+0xFF6F7454,
+0xFF4D5232,
+0xFF767C58,
+0xFF222802,
+0xFF2C3109,
+0xFF565A35,
+0xFF4B4F2A,
+0xFF878C64,
+0xFF7C8067,
+0xFF4B4C50,
+0xFF2E2F41,
+0xFF23253A,
+0xFF1B2036,
+0xFF30344F,
+0xFF2F3451,
+0xFF2C3049,
+0xFF1D2238,
+0xFF16192C,
+0xFF131627,
+0xFF121421,
+0xFF10131C,
+0xFF0E0F14,
+0xFF0D0E12,
+0xFF090A0C,
+0xFF020500,
+0xFF60694C,
+0xFF737E53,
+0xFF3A4912,
+0xFF67734B,
+0xFF59625F,
+0xFF2F3649,
+0xFF2F354F,
+0xFF272C49,
+0xFF262A45,
+0xFF1C1E35,
+0xFF111328,
+0xFF0E1124,
+0xFF121423,
+0xFF151724,
+0xFF1E202D,
+0xFF0F111D,
+0xFF0B0B17,
+0xFF0B0D0C,
+0xFF363C22,
+0xFF575F38,
+0xFF596237,
+0xFF1E2700,
+0xFF343F14,
+0xFF6D764B,
+0xFF5B6238,
+0xFF5A5E39,
+0xFF393C1F,
+0xFF27270D,
+0xFF5C5C40,
+0xFF4C502D,
+0xFF787D54,
+0xFF757D4C,
+0xFF5E692F,
+0xFF6D783E,
+0xFF232F01,
+0xFF354016,
+0xFF808B61,
+0xFF354015,
+0xFF586134,
+0xFF3F481B,
+0xFF576238,
+0xFF59643A,
+0xFF849062,
+0xFF919D6D,
+0xFF616A3D,
+0xFF50592C,
+0xFF596237,
+0xFF9DA47A,
+0xFF596036,
+0xFF7F845B,
+0xFF71734E,
+0xFF555533,
+0xFF656445,
+0xFF464324,
+0xFF666141,
+0xFF868360,
+0xFF7E7B5A,
+0xFF81815F,
+0xFF83835F,
+0xFF6F6F49,
+0xFFA9A983,
+0xFF45461C,
+0xFF777947,
+0xFF92955E,
+0xFF757841,
+0xFF7C7F46,
+0xFF72783C,
+0xFF72783C,
+0xFF757A42,
+0xFF727741,
+0xFF8F975E,
+0xFF4E551F,
+0xFF7D8451,
+0xFF585E30,
+0xFF595F33,
+0xFF848A5C,
+0xFF4C5320,
+0xFF727945,
+0xFF666A38,
+0xFF7D8051,
+0xFF67693A,
+0xFF606231,
+0xFF8D8D59,
+0xFF9A9A66,
+0xFFA09C6C,
+0xFF918D5E,
+0xFF747041,
+0xFF979363,
+0xFF8A8953,
+0xFF9B9A64,
+0xFF6F6D3C,
+0xFFB7B584,
+0xFF8A884F,
+0xFFA4A267,
+0xFF96955F,
+0xFF7E7E48,
+0xFF8C9055,
+0xFFC9CF93,
+0xFF7E864D,
+0xFF899356,
+0xFF9AA561,
+0xFFACB772,
+0xFF869051,
+0xFFA6AE72,
+0xFF777A41,
+0xFF767940,
+0xFF8F975B,
+0xFFA7B174,
+0xFF979F64,
+0xFF62672F,
+0xFF929560,
+0xFF7F844E,
+0xFF7D864D,
+0xFF455014,
+0xFF889255,
+0xFF8A9354,
+0xFF797D42,
+0xFF64672E,
+0xFF6F7640,
+0xFF646D36,
+0xFF869155,
+0xFFA5B173,
+0xFF778345,
+0xFF929E60,
+0xFF778145,
+0xFF798347,
+0xFFB0B87F,
+0xFF6A7239,
+0xFF434A14,
+0xFF828953,
+0xFF59622D,
+0xFF7E8752,
+0xFF7B8551,
+0xFF5B6531,
+0xFF98A570,
+0xFF7C8651,
+0xFF5C642B,
+0xFF707743,
+0xFF9A9C74,
+0xFF61633C,
+0xFF64663E,
+0xFF5C5D31,
+0xFF6B6C40,
+0xFF6C6A41,
+0xFF7E7A55,
+0xFF4B4523,
+0xFF625C3A,
+0xFF786F50,
+0xFF5E5439,
+0xFF63573D,
+0xFFA59A7E,
+0xFF968B6F,
+0xFF463B1F,
+0xFF5B4F37,
+0xFF554837,
+0xFF726753,
+0xFF786F4E,
+0xFFA39E74,
+0xFF9A9669,
+0xFF545124,
+0xFF717044,
+0xFF5D5E32,
+0xFF393C0D,
+0xFF7D824C,
+0xFFAAB370,
+0xFF717B34,
+0xFF6B7536,
+0xFF667034,
+0xFF77824A,
+0xFF657038,
+0xFF737C45,
+0xFF939B68,
+0xFF52582C,
+0xFF4D512C,
+0xFF595D3A,
+0xFF1E2200,
+0xFF4F562A,
+0xFF697140,
+0xFF5A6430,
+0xFF5C6934,
+0xFFA4B07E,
+0xFF293706,
+0xFF566433,
+0xFF5E6C39,
+0xFF44531A,
+0xFF88975C,
+0xFF96A469,
+0xFF738146,
+0xFF92A065,
+0xFF8C975D,
+0xFF535E24,
+0xFF7D864D,
+0xFF6B743D,
+0xFF7C834D,
+0xFF757946,
+0xFF818552,
+0xFF747644,
+0xFF646635,
+0xFF8D8F5E,
+0xFF5A5E2C,
+0xFF7F8253,
+0xFF6B723F,
+0xFF6D743E,
+0xFF6D753A,
+0xFF828A4E,
+0xFF666E32,
+0xFF5D662F,
+0xFF818956,
+0xFF808857,
+0xFF495120,
+0xFF59612E,
+0xFF5E6732,
+0xFF727B44,
+0xFF707B43,
+0xFF5E6732,
+0xFF616B36,
+0xFF59642C,
+0xFF5B6530,
+0xFF656D3E,
+0xFF92996F,
+0xFF606642,
+0xFF5F6543,
+0xFF4C542F,
+0xFF545C35,
+0xFF535E33,
+0xFF5F6B3B,
+0xFF556330,
+0xFF5D6B36,
+0xFF596533,
+0xFF616D3D,
+0xFF6C7548,
+0xFF3A4318,
+0xFF4C4624,
+0xFF585232,
+0xFF2E270B,
+0xFF5B5235,
+0xFF5D5232,
+0xFF6E6544,
+0xFF433E20,
+0xFF484729,
+0xFF6D7051,
+0xFF424928,
+0xFF3E4825,
+0xFF46502D,
+0xFF343A1E,
+0xFF20240B,
+0xFF2D3015,
+0xFF444428,
+0xFF4A4D32,
+0xFF838669,
+0xFF606141,
+0xFF585A35,
+0xFF676941,
+0xFF7A7B51,
+0xFF2E2F07,
+0xFF31330C,
+0xFF4B4C2A,
+0xFF383B1C,
+0xFF373A1D,
+0xFF1E2305,
+0xFF2E3313,
+0xFF4A502E,
+0xFF737B54,
+0xFF262E07,
+0xFF2E3611,
+0xFF3B431C,
+0xFF61683E,
+0xFF98A176,
+0xFF5F653F,
+0xFF575E3C,
+0xFF474C2E,
+0xFF454A2C,
+0xFF414725,
+0xFF3A3E19,
+0xFF4F542C,
+0xFF93956D,
+0xFF676941,
+0xFF6A6D42,
+0xFF5D5F30,
+0xFF7E8454,
+0xFF404E1D,
+0xFF6A7A49,
+0xFF869763,
+0xFF313F0E,
+0xFF232E03,
+0xFF7B865C,
+0xFF676F46,
+0xFF62693F,
+0xFF444B22,
+0xFF515530,
+0xFF4F5332,
+0xFF38391A,
+0xFF363717,
+0xFF2C2D0D,
+0xFF26260A,
+0xFF46462A,
+0xFF505634,
+0xFF3B411B,
+0xFFA4AA7E,
+0xFF63663B,
+0xFF6E7049,
+0xFF636540,
+0xFF5A5E39,
+0xFF4B4E39,
+0xFF393945,
+0xFF2D2D47,
+0xFF1F2136,
+0xFF21263C,
+0xFF2C304B,
+0xFF343855,
+0xFF20263E,
+0xFF13182C,
+0xFF16192A,
+0xFF121524,
+0xFF121420,
+0xFF0A0D14,
+0xFF121317,
+0xFF0E100F,
+0xFF020500,
+0xFF373B2A,
+0xFF535A39,
+0xFF7A855A,
+0xFF677542,
+0xFF36411F,
+0xFF474F51,
+0xFF1D2339,
+0xFF242A44,
+0xFF232943,
+0xFF44495F,
+0xFF34364B,
+0xFF272A3D,
+0xFF232637,
+0xFF1E202D,
+0xFF20222F,
+0xFF22212F,
+0xFF0E0D1B,
+0xFF0D0C1A,
+0xFF08090D,
+0xFF454938,
+0xFF171E00,
+0xFF464D2C,
+0xFF474E2D,
+0xFF535A39,
+0xFF7B835E,
+0xFF737C4D,
+0xFF575F30,
+0xFF5A603A,
+0xFF494D2C,
+0xFF4D512E,
+0xFF61663E,
+0xFF878D5F,
+0xFF9BA46F,
+0xFF8B965A,
+0xFF5B662C,
+0xFF6A7346,
+0xFF626A43,
+0xFF828A63,
+0xFF555D36,
+0xFF4B5229,
+0xFF777E54,
+0xFF575F36,
+0xFF626D42,
+0xFF3E4A18,
+0xFF808A56,
+0xFF848E5C,
+0xFF727B4C,
+0xFF636A3E,
+0xFF8D9367,
+0xFF8C9264,
+0xFF6D7043,
+0xFF7A7B53,
+0xFF72724E,
+0xFF6D6A4B,
+0xFF575234,
+0xFF3C3813,
+0xFF525029,
+0xFF3D3B15,
+0xFF575830,
+0xFF64653B,
+0xFF7C7D53,
+0xFF5E5F37,
+0xFF98996F,
+0xFF939563,
+0xFF747742,
+0xFF939661,
+0xFF83864F,
+0xFF82884A,
+0xFF9BA161,
+0xFF959D61,
+0xFF5D652A,
+0xFF99A166,
+0xFF8A915D,
+0xFF656A41,
+0xFF373B18,
+0xFF737754,
+0xFF353A12,
+0xFF5D6335,
+0xFF5C6232,
+0xFF818759,
+0xFF646A3E,
+0xFF696C41,
+0xFF6C6D43,
+0xFF68673B,
+0xFF737148,
+0xFF4C4721,
+0xFF938E66,
+0xFF66602E,
+0xFF908D56,
+0xFF827F4C,
+0xFF8D8959,
+0xFF706B41,
+0xFFC0BB91,
+0xFF898653,
+0xFFA4A16C,
+0xFF989663,
+0xFF8F8F5B,
+0xFF90955B,
+0xFF99A165,
+0xFF8F985F,
+0xFF7E894D,
+0xFF99A660,
+0xFF7D8A42,
+0xFF929F5A,
+0xFF717B3E,
+0xFF6A6D38,
+0xFF5B5D2B,
+0xFF788246,
+0xFFA5AF72,
+0xFFABB475,
+0xFF898F53,
+0xFFB0B37E,
+0xFFAFB380,
+0xFF78804D,
+0xFF747E49,
+0xFF636C35,
+0xFF5C642B,
+0xFFACAF78,
+0xFF3E430B,
+0xFF434C15,
+0xFF7F8A52,
+0xFFB3BE82,
+0xFF9DA86C,
+0xFF566125,
+0xFF9BA66A,
+0xFF5C652C,
+0xFFB2BB82,
+0xFF9DA66D,
+0xFF8F985F,
+0xFF6F7841,
+0xFF8C955E,
+0xFF555E29,
+0xFFA0A974,
+0xFF59632F,
+0xFF68723E,
+0xFF98A570,
+0xFF5D6732,
+0xFF858D52,
+0xFF81864E,
+0xFF75764C,
+0xFF83845C,
+0xFF525329,
+0xFF939266,
+0xFF98956C,
+0xFF8A8460,
+0xFF7A7356,
+0xFF8E846B,
+0xFF7F755C,
+0xFF83775F,
+0xFF483C24,
+0xFF372811,
+0xFF7F7157,
+0xFF796B4E,
+0xFF847659,
+0xFF86785D,
+0xFF61523D,
+0xFF887C64,
+0xFF857D56,
+0xFF696536,
+0xFF797545,
+0xFF898756,
+0xFF807F4F,
+0xFF636534,
+0xFF626633,
+0xFF676C32,
+0xFF646E25,
+0xFF6E792D,
+0xFF949D5A,
+0xFF7F894A,
+0xFF667135,
+0xFF7A854B,
+0xFF5F6831,
+0xFF737B48,
+0xFF696E45,
+0xFF7A7E59,
+0xFF7C805B,
+0xFF62673E,
+0xFF495120,
+0xFF6F7843,
+0xFF76804B,
+0xFF9FAC77,
+0xFFA5B382,
+0xFF5F6F3E,
+0xFF364711,
+0xFF5D6E37,
+0xFF52642A,
+0xFF798B51,
+0xFF6A7940,
+0xFF75844B,
+0xFF738249,
+0xFF9BA870,
+0xFF606E33,
+0xFF7F8A50,
+0xFF5B642B,
+0xFF434C13,
+0xFF555C26,
+0xFF939A64,
+0xFF9EA36D,
+0xFF666A37,
+0xFF777947,
+0xFF787C4A,
+0xFF6E7142,
+0xFF767D4A,
+0xFF666D37,
+0xFF7B8348,
+0xFF8C9659,
+0xFF5F692D,
+0xFF737C45,
+0xFF7D8552,
+0xFF697341,
+0xFF687240,
+0xFF6F7945,
+0xFF68723D,
+0xFF89945C,
+0xFF536028,
+0xFF9AA46F,
+0xFF6B7842,
+0xFF65723A,
+0xFF495620,
+0xFF40491A,
+0xFF454E23,
+0xFF494F29,
+0xFF2F3511,
+0xFF3D4520,
+0xFF3E461F,
+0xFF434F21,
+0xFF525E2E,
+0xFF697543,
+0xFF525F2A,
+0xFF66703E,
+0xFF586132,
+0xFF434A1E,
+0xFF82895F,
+0xFF3D3212,
+0xFF7F7456,
+0xFF54492D,
+0xFF615338,
+0xFF655838,
+0xFF817656,
+0xFF777053,
+0xFF8F8B6E,
+0xFF424324,
+0xFF292F0D,
+0xFF272F0A,
+0xFF474E2C,
+0xFF383E22,
+0xFF2A2E13,
+0xFF404326,
+0xFF7D7D61,
+0xFF585B3E,
+0xFF3A3D1E,
+0xFF686947,
+0xFF72744F,
+0xFF565630,
+0xFF383812,
+0xFF31310D,
+0xFF3D3D1B,
+0xFF646546,
+0xFF2F2F13,
+0xFF393C1F,
+0xFF181B00,
+0xFF252A0A,
+0xFF2A300C,
+0xFF5D653E,
+0xFF535B32,
+0xFF757D58,
+0xFF141C00,
+0xFF959E71,
+0xFF98A174,
+0xFF899168,
+0xFF545C37,
+0xFF313817,
+0xFF42492A,
+0xFF656B49,
+0xFF212701,
+0xFF696E45,
+0xFF70764A,
+0xFF1B2100,
+0xFF6D7345,
+0xFF9C9F70,
+0xFF4D5524,
+0xFF374514,
+0xFF61733F,
+0xFF97A874,
+0xFF34420F,
+0xFF3C471C,
+0xFF6C774D,
+0xFF505831,
+0xFF2D340B,
+0xFF7D8259,
+0xFF5D5F38,
+0xFF575839,
+0xFF4B4A2E,
+0xFF4B4A2C,
+0xFF363517,
+0xFF58543B,
+0xFF191800,
+0xFF777B58,
+0xFF3A3F17,
+0xFF66693C,
+0xFF545529,
+0xFF2C2D05,
+0xFF484A25,
+0xFF646847,
+0xFF414433,
+0xFF353746,
+0xFF2C2C48,
+0xFF23253C,
+0xFF26283F,
+0xFF2A2E49,
+0xFF2B2F4C,
+0xFF21253E,
+0xFF1C2135,
+0xFF1F2233,
+0xFF1D212D,
+0xFF151821,
+0xFF191C23,
+0xFF111216,
+0xFF0D0F0C,
+0xFF040800,
+0xFF555A43,
+0xFF182000,
+0xFF717A4F,
+0xFF535E33,
+0xFF404A2F,
+0xFF3C4349,
+0xFF2A2F45,
+0xFF252B43,
+0xFF191F35,
+0xFF2C3144,
+0xFF202336,
+0xFF23253A,
+0xFF202336,
+0xFF2E303F,
+0xFF292B38,
+0xFF1F1E2E,
+0xFF111020,
+0xFF0C0B19,
+0xFF08090D,
+0xFF5B5F50,
+0xFF373D23,
+0xFF242A0E,
+0xFF62684C,
+0xFF5B6049,
+0xFF4B5233,
+0xFFA0A97C,
+0xFF384112,
+0xFF454D24,
+0xFF373D17,
+0xFF575E35,
+0xFF767C50,
+0xFF424A1B,
+0xFF78804D,
+0xFF828D53,
+0xFF3C470F,
+0xFF525B2E,
+0xFF596037,
+0xFF525930,
+0xFF2B3008,
+0xFF959A71,
+0xFF787D54,
+0xFF3E471C,
+0xFF586134,
+0xFF656F3A,
+0xFF747D46,
+0xFF424C18,
+0xFF394110,
+0xFF41471B,
+0xFF878D61,
+0xFF6F7341,
+0xFF3C400E,
+0xFF838458,
+0xFF5B5B35,
+0xFF73704F,
+0xFF726D4D,
+0xFFB0AC86,
+0xFF838256,
+0xFF6D6E44,
+0xFF515226,
+0xFF898B5C,
+0xFF666839,
+0xFF7A7B51,
+0xFF68693F,
+0xFF7B7D4E,
+0xFF656736,
+0xFF5A5C2B,
+0xFF727741,
+0xFF92975D,
+0xFF6B7337,
+0xFF727A3E,
+0xFF80884D,
+0xFF868D57,
+0xFF5D6333,
+0xFF888C69,
+0xFF474A2B,
+0xFF494C2D,
+0xFF484C2B,
+0xFF5C603B,
+0xFF555A31,
+0xFF696E46,
+0xFF7C8159,
+0xFF65673F,
+0xFF3A3C15,
+0xFF696947,
+0xFF252203,
+0xFF5B5639,
+0xFF8D8765,
+0xFF595623,
+0xFF7F7D44,
+0xFF85824D,
+0xFF898757,
+0xFF524D25,
+0xFFD2CFA6,
+0xFFA29E6F,
+0xFF706E3D,
+0xFF9B9B69,
+0xFF959765,
+0xFFA4A973,
+0xFF8F985F,
+0xFF465119,
+0xFF5C6A2D,
+0xFFACBB76,
+0xFF92A35C,
+0xFF97A661,
+0xFF5E6A2A,
+0xFF6C703E,
+0xFF7F8351,
+0xFFA2AB72,
+0xFF768043,
+0xFFB8C182,
+0xFFA1A76B,
+0xFF575C26,
+0xFF8A915E,
+0xFF66703E,
+0xFF4B5523,
+0xFF8A935E,
+0xFF4C531D,
+0xFF6F743C,
+0xFF878C54,
+0xFF5A632E,
+0xFF6A753D,
+0xFF98A369,
+0xFF768145,
+0xFF616C30,
+0xFF859054,
+0xFF737C43,
+0xFF808950,
+0xFF939C63,
+0xFF9DA66D,
+0xFF97A069,
+0xFF6A733C,
+0xFF77804B,
+0xFFBDC691,
+0xFF6A7440,
+0xFF96A06C,
+0xFF555F2B,
+0xFF87925A,
+0xFF82884C,
+0xFF989B62,
+0xFF8A8C5D,
+0xFF86875B,
+0xFF8D8C5E,
+0xFF605D30,
+0xFF6F6A44,
+0xFF908A68,
+0xFF61583B,
+0xFF574D34,
+0xFF685B48,
+0xFF625544,
+0xFFA49484,
+0xFF7E6F5C,
+0xFF4D3C28,
+0xFF67573E,
+0xFF8C7E61,
+0xFF706245,
+0xFF3C2D16,
+0xFF4A3F23,
+0xFF8E865F,
+0xFFB5AE80,
+0xFF9F9B6C,
+0xFF696737,
+0xFF848353,
+0xFF777646,
+0xFF787A4B,
+0xFF7A7F49,
+0xFF565C1C,
+0xFF76803B,
+0xFF939959,
+0xFF828A4E,
+0xFF727C40,
+0xFF828B52,
+0xFF565F28,
+0xFF464E1B,
+0xFF5C6138,
+0xFF737850,
+0xFF3D421A,
+0xFF676D41,
+0xFF6E7742,
+0xFF67723A,
+0xFF7A844F,
+0xFF7A8752,
+0xFF768453,
+0xFF5F6F3E,
+0xFF82935C,
+0xFF63773A,
+0xFF56682E,
+0xFF5D6F35,
+0xFF56682E,
+0xFF72844A,
+0xFF9BAA71,
+0xFF79884F,
+0xFF87955A,
+0xFF849257,
+0xFF5E692F,
+0xFF3C460A,
+0xFF70783F,
+0xFF737B42,
+0xFF81864E,
+0xFF9EA36D,
+0xFF757745,
+0xFF6F7341,
+0xFF494F1F,
+0xFF919865,
+0xFF8A915B,
+0xFF969E65,
+0xFF737C43,
+0xFF868F56,
+0xFF454E19,
+0xFF5C6431,
+0xFF687240,
+0xFF757F4D,
+0xFF79834E,
+0xFF4B5820,
+0xFF6D7A42,
+0xFF5F6C34,
+0xFF9DAA74,
+0xFFA0AD78,
+0xFF7A8751,
+0xFF707D48,
+0xFF7C8556,
+0xFF889166,
+0xFF5F663D,
+0xFF363C16,
+0xFF49512A,
+0xFF4E572C,
+0xFF515D2D,
+0xFF55612F,
+0xFF5E6B36,
+0xFF7F8C57,
+0xFF545E2C,
+0xFF454E1F,
+0xFF464D23,
+0xFF50572D,
+0xFF5A4D2D,
+0xFF736548,
+0xFF6E6045,
+0xFF504227,
+0xFF8F8262,
+0xFF615837,
+0xFFA8A282,
+0xFF585536,
+0xFF2A2B0B,
+0xFF262A09,
+0xFF444A26,
+0xFF646A46,
+0xFF2A2F11,
+0xFF2B2E13,
+0xFF626246,
+0xFF4E4F30,
+0xFF2F3011,
+0xFF666748,
+0xFF616240,
+0xFF434520,
+0xFF575934,
+0xFF2E300B,
+0xFF5A5C37,
+0xFF474826,
+0xFF383919,
+0xFF515233,
+0xFF404326,
+0xFF45482B,
+0xFF323717,
+0xFF424826,
+0xFF3F4722,
+0xFF49512C,
+0xFF616B48,
+0xFF343E19,
+0xFF677248,
+0xFF3E491E,
+0xFF182300,
+0xFF323D13,
+0xFF3C441F,
+0xFF767E59,
+0xFF3A4219,
+0xFF374015,
+0xFF7C8357,
+0xFF6D7448,
+0xFF474E24,
+0xFF9CA377,
+0xFF444A1C,
+0xFF5C6634,
+0xFF546231,
+0xFF90A16D,
+0xFF8C9A67,
+0xFF404E1B,
+0xFF4D582D,
+0xFF566139,
+0xFF5E6641,
+0xFF5C623C,
+0xFF757A51,
+0xFF6E7049,
+0xFF767557,
+0xFF403C21,
+0xFF423E21,
+0xFF807C61,
+0xFF4F4931,
+0xFF686449,
+0xFF6D6E4C,
+0xFF777C53,
+0xFF505125,
+0xFF616334,
+0xFF525329,
+0xFF62643F,
+0xFF676B50,
+0xFF6C6F66,
+0xFF2F3140,
+0xFF262743,
+0xFF21233A,
+0xFF23253C,
+0xFF2A2B47,
+0xFF272B46,
+0xFF272C42,
+0xFF2A2F42,
+0xFF262938,
+0xFF1F212D,
+0xFF16161E,
+0xFF0E0F14,
+0xFF0B0C0E,
+0xFF050801,
+0xFF0E1100,
+0xFF3F4328,
+0xFF717952,
+0xFF30380F,
+0xFF4E5931,
+0xFF5C664E,
+0xFF6C7379,
+0xFF30354B,
+0xFF30364C,
+0xFF293043,
+0xFF252B3B,
+0xFF252B3B,
+0xFF282A41,
+0xFF2D2F46,
+0xFF2D2E43,
+0xFF2C2D41,
+0xFF2F2E40,
+0xFF242333,
+0xFF0D0D19,
+0xFF08090B,
+0xFF5E6150,
+0xFF4B4F34,
+0xFF25290E,
+0xFF22260D,
+0xFF323520,
+0xFF1B2009,
+0xFF394320,
+0xFF3F4A22,
+0xFF4A542F,
+0xFF303811,
+0xFF3B4216,
+0xFF596132,
+0xFF6D7448,
+0xFF535A2E,
+0xFF5D6532,
+0xFF565E2D,
+0xFF8C9367,
+0xFF282F05,
+0xFF909668,
+0xFF46491A,
+0xFF6F7243,
+0xFF686B3E,
+0xFF50572B,
+0xFF727C4A,
+0xFF899158,
+0xFF959D62,
+0xFF5D662F,
+0xFF8D9562,
+0xFF7C8254,
+0xFF585B2E,
+0xFF575927,
+0xFF7B7D4B,
+0xFF8D9061,
+0xFF7B7C54,
+0xFF524F2E,
+0xFF36320F,
+0xFF8F8D64,
+0xFF9B9A6C,
+0xFF909462,
+0xFF676B39,
+0xFF7D814F,
+0xFF757849,
+0xFF606338,
+0xFF5B5D35,
+0xFF7E8058,
+0xFF595C31,
+0xFF4E5122,
+0xFF818553,
+0xFF7C804E,
+0xFF6C733F,
+0xFF717842,
+0xFF7F8853,
+0xFF404819,
+0xFF777E55,
+0xFF545835,
+0xFF404324,
+0xFF55593E,
+0xFF61654A,
+0xFF484D2F,
+0xFF565C3A,
+0xFF767C58,
+0xFF151B00,
+0xFF484D25,
+0xFF4F512C,
+0xFF3C3C20,
+0xFF2F2D18,
+0xFF403B28,
+0xFF514B31,
+0xFF918F5F,
+0xFF5F5E26,
+0xFF8C8B53,
+0xFF959561,
+0xFF7B784B,
+0xFF949367,
+0xFFA5A277,
+0xFF706F41,
+0xFF717040,
+0xFFA4A876,
+0xFF606636,
+0xFF5B6332,
+0xFF75824D,
+0xFF8E9D64,
+0xFF96A665,
+0xFFA6BA75,
+0xFF74853F,
+0xFF4B5A19,
+0xFF9BA26F,
+0xFF888C5A,
+0xFFAEB77E,
+0xFF7D874B,
+0xFF868E52,
+0xFF9EA66D,
+0xFF7B824E,
+0xFF4F5525,
+0xFF626B3C,
+0xFF57612F,
+0xFF59622D,
+0xFF666E35,
+0xFF464B13,
+0xFFA3A872,
+0xFF636B38,
+0xFF7E8653,
+0xFF929B64,
+0xFF323B02,
+0xFF677037,
+0xFF4E571E,
+0xFF646C33,
+0xFF6F773E,
+0xFF959D64,
+0xFF889057,
+0xFF7B824C,
+0xFF4D541E,
+0xFFCAD39C,
+0xFF818A53,
+0xFF6B743F,
+0xFFA3AD78,
+0xFFA7B17C,
+0xFF78814A,
+0xFF8D9357,
+0xFF8D9156,
+0xFF8C8C58,
+0xFF71713F,
+0xFF888653,
+0xFF7E7C4B,
+0xFF88835B,
+0xFF504A26,
+0xFF6C6342,
+0xFF8F8669,
+0xFF8D806D,
+0xFF7F7164,
+0xFF493830,
+0xFF64534B,
+0xFF524233,
+0xFF463724,
+0xFF988972,
+0xFF796B51,
+0xFF50442A,
+0xFF5F5436,
+0xFF4A421D,
+0xFFA9A17A,
+0xFF625C38,
+0xFF8C8863,
+0xFF57552C,
+0xFF8D8B64,
+0xFF686842,
+0xFF797953,
+0xFF76774B,
+0xFF585C2A,
+0xFF6F7140,
+0xFF6C703D,
+0xFF4E5521,
+0xFF818852,
+0xFF8F9662,
+0xFF787F4C,
+0xFF8E936A,
+0xFF595E36,
+0xFF6C7148,
+0xFF676D3F,
+0xFF505922,
+0xFF7B864C,
+0xFF656F3A,
+0xFF869260,
+0xFF465325,
+0xFF647443,
+0xFF44561A,
+0xFF7F9153,
+0xFF536529,
+0xFF5B6D33,
+0xFF67793F,
+0xFF697B41,
+0xFF728148,
+0xFF7C8B52,
+0xFF89985D,
+0xFF717F44,
+0xFF636E32,
+0xFF657133,
+0xFF6D773B,
+0xFF9BA569,
+0xFF5E662D,
+0xFF848B55,
+0xFF5D612E,
+0xFF595D2A,
+0xFF8E9562,
+0xFF7F8652,
+0xFF929963,
+0xFF5D642E,
+0xFF666D39,
+0xFF5F6632,
+0xFF626A37,
+0xFF5D6532,
+0xFF646E3A,
+0xFF49531E,
+0xFF808E53,
+0xFF677538,
+0xFF707E43,
+0xFF66753C,
+0xFF657340,
+0xFF6D7B4A,
+0xFF5E6C39,
+0xFF788653,
+0xFF99A577,
+0xFF566234,
+0xFF545D32,
+0xFF333C11,
+0xFF5E673A,
+0xFF565F30,
+0xFF64713C,
+0xFF63703A,
+0xFF4B5822,
+0xFF919E69,
+0xFF535D2B,
+0xFF474E22,
+0xFF62673F,
+0xFF4D522A,
+0xFF6E5F40,
+0xFF5D4E31,
+0xFF54462B,
+0xFF483D21,
+0xFF59502F,
+0xFF908A68,
+0xFF8A8565,
+0xFF474425,
+0xFF434223,
+0xFF30310F,
+0xFF717550,
+0xFF2E320F,
+0xFF393C1F,
+0xFF595C3F,
+0xFF434425,
+0xFF4C4D2D,
+0xFF717250,
+0xFF4A4C27,
+0xFF80815F,
+0xFF383917,
+0xFF2E2F0F,
+0xFF4D4E2E,
+0xFF4B4C2C,
+0xFF5A5E3D,
+0xFF494D2C,
+0xFF353918,
+0xFF2B2F0E,
+0xFF3B411F,
+0xFF4C5230,
+0xFF313715,
+0xFF4A512F,
+0xFF3B4220,
+0xFF4E5836,
+0xFF818B68,
+0xFF525D35,
+0xFF3E491F,
+0xFF485329,
+0xFF626D43,
+0xFF555D34,
+0xFFACB58A,
+0xFF2F380B,
+0xFF2C3508,
+0xFF9AA177,
+0xFF5D643B,
+0xFFABB18B,
+0xFF30370E,
+0xFF394112,
+0xFF9EA876,
+0xFF455123,
+0xFF5E6C3B,
+0xFF6E7A48,
+0xFF566232,
+0xFF2D350C,
+0xFF2D350E,
+0xFF3F4523,
+0xFF3D411E,
+0xFF51532B,
+0xFF34350D,
+0xFF797657,
+0xFF575338,
+0xFF8A8568,
+0xFF5A5538,
+0xFF655F47,
+0xFF4F4B30,
+0xFF636442,
+0xFF51532B,
+0xFF7B7950,
+0xFF646337,
+0xFF4E4D21,
+0xFF535432,
+0xFF3F4231,
+0xFF4B4F4E,
+0xFF2D3041,
+0xFF272942,
+0xFF21233A,
+0xFF202239,
+0xFF292B44,
+0xFF272942,
+0xFF262B3F,
+0xFF232939,
+0xFF171926,
+0xFF060912,
+0xFF121318,
+0xFF0C0D11,
+0xFF08090B,
+0xFF060902,
+0xFF2A2D18,
+0xFF1F2404,
+0xFF6A724B,
+0xFF646C43,
+0xFF38421F,
+0xFF545C47,
+0xFF3E4347,
+0xFF363B4E,
+0xFF31364A,
+0xFF3A4056,
+0xFF282D40,
+0xFF22273B,
+0xFF272844,
+0xFF32334F,
+0xFF2A2B40,
+0xFF303145,
+0xFF323143,
+0xFF131220,
+0xFF0F0F19,
+0xFF080A07,
+0xFFABAE9B,
+0xFF5C6045,
+0xFF353A1C,
+0xFF363B1D,
+0xFF2D3118,
+0xFF363C22,
+0xFF4B5435,
+0xFF596442,
+0xFF404A27,
+0xFF5F6742,
+0xFF5F663C,
+0xFF666D43,
+0xFF777D57,
+0xFF3E441E,
+0xFF50572B,
+0xFF868E5F,
+0xFF636A3E,
+0xFF7A8253,
+0xFF888F5C,
+0xFF595D2B,
+0xFF4B4C20,
+0xFF505326,
+0xFF8D9468,
+0xFF777F4C,
+0xFF696E36,
+0xFF868B51,
+0xFF5A632C,
+0xFF7F8754,
+0xFF9CA274,
+0xFF616435,
+0xFF595B29,
+0xFF7D7F4D,
+0xFFBABD8E,
+0xFF6C6F44,
+0xFF73704D,
+0xFF3C3813,
+0xFF69683C,
+0xFF8A8C5B,
+0xFF9EA572,
+0xFF616835,
+0xFF7F8555,
+0xFF7C8254,
+0xFF262800,
+0xFF2E330B,
+0xFF393B16,
+0xFF343911,
+0xFF515427,
+0xFF666C3C,
+0xFF575C33,
+0xFF62673E,
+0xFF4F5726,
+0xFF7D8556,
+0xFF444B22,
+0xFF6F7551,
+0xFF313512,
+0xFF636947,
+0xFF393D24,
+0xFF41452E,
+0xFF282C13,
+0xFF1C2206,
+0xFF707555,
+0xFF424826,
+0xFF515733,
+0xFF4A4E2D,
+0xFF1F2109,
+0xFF3D3C2A,
+0xFF2A261A,
+0xFF393420,
+0xFF85835A,
+0xFF6F6F3B,
+0xFF454813,
+0xFF8C8E5D,
+0xFF43441A,
+0xFF55562E,
+0xFF65663C,
+0xFF939566,
+0xFF797B4A,
+0xFF535724,
+0xFF909865,
+0xFF97A16D,
+0xFF54612C,
+0xFFB0BF86,
+0xFF7E9151,
+0xFF849853,
+0xFF71853E,
+0xFF96A665,
+0xFF949D68,
+0xFF9FA673,
+0xFF5C642B,
+0xFF586226,
+0xFF364004,
+0xFF909960,
+0xFF767E4B,
+0xFF313908,
+0xFF7F8756,
+0xFF525A27,
+0xFF778047,
+0xFF414B0F,
+0xFF676F34,
+0xFF7C834D,
+0xFF737949,
+0xFF666E3D,
+0xFF606932,
+0xFF717A41,
+0xFFA5AE75,
+0xFF5D662D,
+0xFF616930,
+0xFF596128,
+0xFF939B62,
+0xFF838B52,
+0xFF636A34,
+0xFF79804A,
+0xFFA5AC76,
+0xFF616A33,
+0xFF8F9863,
+0xFFAEB782,
+0xFF6F7843,
+0xFF606932,
+0xFF9FA567,
+0xFF9DA164,
+0xFFA0A168,
+0xFF7A7A44,
+0xFF4E4D15,
+0xFF888653,
+0xFF68633B,
+0xFF736D49,
+0xFF6B633E,
+0xFF655C3B,
+0xFF817660,
+0xFF75675C,
+0xFF40312C,
+0xFF5D4E49,
+0xFF66584D,
+0xFF3C2F1F,
+0xFF726552,
+0xFF61553D,
+0xFF7A6E54,
+0xFF5A5132,
+0xFFA9A07F,
+0xFF686240,
+0xFF484326,
+0xFF777255,
+0xFF625F3C,
+0xFF757251,
+0xFF636246,
+0xFF49482C,
+0xFF818062,
+0xFF929270,
+0xFF494721,
+0xFF3F4016,
+0xFF4A4D20,
+0xFF5B5E2F,
+0xFF777B49,
+0xFF7D8051,
+0xFF575A2F,
+0xFF72774E,
+0xFF878C63,
+0xFF575D2D,
+0xFF4D541E,
+0xFF565F26,
+0xFF606A35,
+0xFF65713F,
+0xFF475325,
+0xFF62703F,
+0xFF546328,
+0xFF758546,
+0xFF57662B,
+0xFF506228,
+0xFF707F46,
+0xFF718047,
+0xFF7D8C53,
+0xFF5D6C33,
+0xFF69783D,
+0xFF6D7B3E,
+0xFF99A468,
+0xFF697537,
+0xFF6F793C,
+0xFF8B9559,
+0xFF6A7239,
+0xFF757C46,
+0xFF3B3F0C,
+0xFF6B6F3C,
+0xFF7A814D,
+0xFF888F5B,
+0xFFB3BA86,
+0xFF69703C,
+0xFF5A612E,
+0xFF79804D,
+0xFF7D8353,
+0xFF676F3C,
+0xFF424B16,
+0xFF606B33,
+0xFF798448,
+0xFF6C7A3C,
+0xFF6B7B3D,
+0xFF606F36,
+0xFF70814D,
+0xFF667647,
+0xFF6E7E4D,
+0xFF546231,
+0xFF768453,
+0xFF697545,
+0xFF6F7849,
+0xFF576031,
+0xFF788250,
+0xFF58622E,
+0xFF4D5A24,
+0xFF68753D,
+0xFF66733D,
+0xFF7D8753,
+0xFF676F3E,
+0xFF545B2F,
+0xFF4B5027,
+0xFF666B43,
+0xFF796C4C,
+0xFF45371A,
+0xFF504529,
+0xFF5D5639,
+0xFF5E5A37,
+0xFF686542,
+0xFF31310F,
+0xFF737351,
+0xFF3B3C1C,
+0xFF3A3B19,
+0xFF747651,
+0xFF3C3E19,
+0xFF6F7051,
+0xFF444428,
+0xFF434425,
+0xFF555732,
+0xFF84875C,
+0xFF5B5E31,
+0xFF6E7049,
+0xFF4B4C2C,
+0xFF4E5136,
+0xFF4A4C34,
+0xFF272911,
+0xFF4A4E33,
+0xFF2C3111,
+0xFF2B310D,
+0xFF3F451F,
+0xFF525A33,
+0xFF565E37,
+0xFF68704B,
+0xFF636A49,
+0xFF333A1B,
+0xFF3A4324,
+0xFF2D3617,
+0xFF323C19,
+0xFF505A35,
+0xFF5C643D,
+0xFF59613A,
+0xFF50592E,
+0xFF7B8457,
+0xFF3A4314,
+0xFF202900,
+0xFF646C43,
+0xFFA3AB86,
+0xFF2D3311,
+0xFF353B17,
+0xFF6E7549,
+0xFF6D7546,
+0xFF7C855A,
+0xFF596237,
+0xFF919A6D,
+0xFF636C3F,
+0xFF4C522C,
+0xFF7E8261,
+0xFF76795C,
+0xFF1F2000,
+0xFF6C6E46,
+0xFF797A50,
+0xFF53502F,
+0xFF888467,
+0xFF6C6749,
+0xFF6C6749,
+0xFF130E00,
+0xFF4D492C,
+0xFF525230,
+0xFF72724C,
+0xFF87835D,
+0xFF69663D,
+0xFF45431A,
+0xFF676849,
+0xFF6A6B65,
+0xFF373A43,
+0xFF272C3F,
+0xFF272C42,
+0xFF24263D,
+0xFF1F2138,
+0xFF292941,
+0xFF28293E,
+0xFF24273A,
+0xFF161C2A,
+0xFF030511,
+0xFF080B12,
+0xFF07080C,
+0xFF050608,
+0xFF0A0A0C,
+0xFF080903,
+0xFF1D210A,
+0xFF353B19,
+0xFF60673E,
+0xFF414920,
+0xFF0F1900,
+0xFF303821,
+0xFF424846,
+0xFF313842,
+0xFF3A3F53,
+0xFF3D415A,
+0xFF363A55,
+0xFF323653,
+0xFF2C2D4C,
+0xFF242543,
+0xFF2F3044,
+0xFF2D2F3E,
+0xFF151422,
+0xFF080812,
+0xFF0E0D13,
+0xFF141510,
+0xFF373A27,
+0xFF3E4325,
+0xFF8D916E,
+0xFF666A45,
+0xFF575B36,
+0xFF606640,
+0xFF585F3D,
+0xFF545E3C,
+0xFF2A3110,
+0xFF1C2302,
+0xFF2C3210,
+0xFF616745,
+0xFF272B10,
+0xFF606547,
+0xFF121800,
+0xFF656C40,
+0xFF646C3D,
+0xFF5D6534,
+0xFF767C4C,
+0xFF6D7345,
+0xFF373914,
+0xFF5C5E39,
+0xFF484F23,
+0xFF838A57,
+0xFF6D7039,
+0xFF73783E,
+0xFF939C65,
+0xFF707944,
+0xFF676A3B,
+0xFF7E8051,
+0xFF686A38,
+0xFF676B38,
+0xFFA6AC7C,
+0xFF777A4F,
+0xFF716F49,
+0xFF67653E,
+0xFF313206,
+0xFF838755,
+0xFF7A824F,
+0xFF6F7746,
+0xFF4F5728,
+0xFF838A60,
+0xFF30340F,
+0xFF636945,
+0xFF909471,
+0xFF565D34,
+0xFF5D6335,
+0xFF5D6438,
+0xFF989E7A,
+0xFF515735,
+0xFF5B6239,
+0xFF7F865D,
+0xFF676E4C,
+0xFF3C4321,
+0xFF5B613B,
+0xFF777D59,
+0xFF171B02,
+0xFF1E230D,
+0xFF444932,
+0xFF1D250D,
+0xFF21270B,
+0xFF555C3D,
+0xFF252C0B,
+0xFF585D3F,
+0xFF373B22,
+0xFF282A15,
+0xFF3D3B2C,
+0xFF46442F,
+0xFF5A5A36,
+0xFF696A3E,
+0xFF4A5024,
+0xFF555C33,
+0xFF252809,
+0xFF5D6140,
+0xFF76794E,
+0xFF4B521F,
+0xFF515825,
+0xFF848D56,
+0xFF5A6628,
+0xFF899759,
+0xFF697841,
+0xFF6D7C43,
+0xFFA6B773,
+0xFF61722B,
+0xFF91A25C,
+0xFF9BAB6A,
+0xFF758046,
+0xFF707942,
+0xFF485015,
+0xFF6D773B,
+0xFFA9B377,
+0xFF505B23,
+0xFF848E5C,
+0xFF505A28,
+0xFF3D4512,
+0xFF828B54,
+0xFF98A263,
+0xFF606B29,
+0xFF677132,
+0xFF798146,
+0xFF888E5E,
+0xFF737949,
+0xFF686F39,
+0xFF979F66,
+0xFF81894E,
+0xFF7B8348,
+0xFF8B9056,
+0xFF787D43,
+0xFF858A52,
+0xFF6C7139,
+0xFF838850,
+0xFF889057,
+0xFF525923,
+0xFF626933,
+0xFF9EA571,
+0xFF606733,
+0xFF636A37,
+0xFFB4BB85,
+0xFFAAB072,
+0xFF464C0E,
+0xFF949760,
+0xFF7E814C,
+0xFF7D7D47,
+0xFF8C8C58,
+0xFF68653C,
+0xFF69653F,
+0xFF79744A,
+0xFF7C7751,
+0xFF90896D,
+0xFF7A6E5E,
+0xFF2C1F17,
+0xFF2B1E18,
+0xFF4A3D34,
+0xFF584C3E,
+0xFF6C6050,
+0xFF6D624E,
+0xFF7B7156,
+0xFF595235,
+0xFF635D3D,
+0xFF625D3F,
+0xFF6B654F,
+0xFF6B654F,
+0xFF555134,
+0xFF6F6B50,
+0xFF706B57,
+0xFF666050,
+0xFF66614E,
+0xFF5E5943,
+0xFF858063,
+0xFF918E6D,
+0xFF7A7754,
+0xFF86875F,
+0xFF7C7E4F,
+0xFF585A2B,
+0xFF717248,
+0xFF80825A,
+0xFF83855D,
+0xFF5B6133,
+0xFF818854,
+0xFF3F4811,
+0xFF666E3B,
+0xFF8C9566,
+0xFF475025,
+0xFF6A7344,
+0xFF788349,
+0xFF576527,
+0xFF627035,
+0xFF536227,
+0xFF6E7B43,
+0xFF727F47,
+0xFF57642C,
+0xFF6F7C44,
+0xFF344207,
+0xFF748245,
+0xFF6F7A3E,
+0xFF818D4F,
+0xFF646E32,
+0xFF6D773B,
+0xFF737A44,
+0xFF49501C,
+0xFF505422,
+0xFF6E7240,
+0xFF676B39,
+0xFF565A27,
+0xFF898D5A,
+0xFF3B3F0C,
+0xFF969A68,
+0xFF707442,
+0xFF686B3C,
+0xFF626936,
+0xFF626935,
+0xFF7B844B,
+0xFF748042,
+0xFF758345,
+0xFF718143,
+0xFF86955C,
+0xFF879864,
+0xFF748453,
+0xFF576738,
+0xFF7D8D5C,
+0xFF42501F,
+0xFF576532,
+0xFF63703B,
+0xFF5F6C37,
+0xFF636D38,
+0xFF656F3A,
+0xFF646F37,
+0xFF657038,
+0xFF68723D,
+0xFF3D4713,
+0xFF6D7544,
+0xFF4E5426,
+0xFF5A5D32,
+0xFF4C4E26,
+0xFF5B5030,
+0xFF504728,
+0xFF494225,
+0xFF666344,
+0xFF52522E,
+0xFF2E3009,
+0xFF3D411C,
+0xFF616542,
+0xFF646545,
+0xFF424321,
+0xFF5B5B37,
+0xFF33330F,
+0xFF353416,
+0xFF595A3B,
+0xFF4A4B2B,
+0xFF2C2E09,
+0xFF5C5F32,
+0xFF727548,
+0xFF6D6F48,
+0xFF4D512E,
+0xFF404326,
+0xFF393D22,
+0xFF50543B,
+0xFF686F50,
+0xFF525937,
+0xFF343E19,
+0xFF222A01,
+0xFF455026,
+0xFF3A421B,
+0xFF606745,
+0xFF444B2A,
+0xFF3A4122,
+0xFF434C2D,
+0xFF2B3415,
+0xFF4C5633,
+0xFF232D08,
+0xFF626A45,
+0xFF39411C,
+0xFF6A724B,
+0xFF586037,
+0xFF545D32,
+0xFF3D461B,
+0xFF929A73,
+0xFF111800,
+0xFF5B613F,
+0xFF3F4521,
+0xFF636A3E,
+0xFF525A2B,
+0xFF6F744C,
+0xFF414520,
+0xFF72774F,
+0xFF7D825A,
+0xFF565A39,
+0xFF5E5F40,
+0xFF4C4C32,
+0xFF2D2E0F,
+0xFF777850,
+0xFF5E5F35,
+0xFF4D4A29,
+0xFF797657,
+0xFF4D4A29,
+0xFF817C5C,
+0xFF575234,
+0xFF3E3B1C,
+0xFF3B3817,
+0xFF6D6A47,
+0xFF48421E,
+0xFF615C36,
+0xFF74704A,
+0xFF616147,
+0xFF626365,
+0xFF2E3140,
+0xFF262D3F,
+0xFF293043,
+0xFF202539,
+0xFF1E2035,
+0xFF26243A,
+0xFF25263A,
+0xFF242738,
+0xFF181B2A,
+0xFF0A0C18,
+0xFF04070E,
+0xFF08090B,
+0xFF080A09,
+0xFF060608,
+0xFF13140E,
+0xFF21250C,
+0xFF464C28,
+0xFF1F2600,
+0xFF454C23,
+0xFF49502E,
+0xFF242C14,
+0xFF353D32,
+0xFF42474B,
+0xFF454A5D,
+0xFF363A53,
+0xFF42475D,
+0xFF3B3F58,
+0xFF373854,
+0xFF36384F,
+0xFF1F2130,
+0xFF181B24,
+0xFF0B0B15,
+0xFF0D0E13,
+0xFF070709,
+0xFF1E1F19,
+0xFF333623,
+0xFF303517,
+0xFF373B18,
+0xFF636742,
+0xFF6C704B,
+0xFF373D19,
+0xFF3B4221,
+0xFF414A2D,
+0xFF1E2408,
+0xFF1F2509,
+0xFF2C3113,
+0xFF262A0F,
+0xFF323520,
+0xFF292D16,
+0xFF3E4323,
+0xFF565C36,
+0xFF4B5228,
+0xFF4B5226,
+0xFF555B2F,
+0xFF747950,
+0xFF686949,
+0xFF525633,
+0xFF52582C,
+0xFF979E6B,
+0xFF8A8D58,
+0xFF73763F,
+0xFF6C753E,
+0xFF424B16,
+0xFF646836,
+0xFF7E804F,
+0xFF6C6E3D,
+0xFF9B9F6D,
+0xFF73794B,
+0xFF7E8458,
+0xFF797750,
+0xFF73714A,
+0xFF7D7E52,
+0xFF6B7141,
+0xFF919968,
+0xFF37410F,
+0xFF656E41,
+0xFF6C724C,
+0xFF676C4C,
+0xFF393E1E,
+0xFF363C16,
+0xFFB4BB8F,
+0xFF606837,
+0xFFD6DEAF,
+0xFF5C623E,
+0xFF464B2B,
+0xFF676D49,
+0xFF898F6B,
+0xFF202706,
+0xFF555C3B,
+0xFF505634,
+0xFF545939,
+0xFF545942,
+0xFF1B200A,
+0xFF464E36,
+0xFF232C11,
+0xFF353E23,
+0xFF606850,
+0xFF171F07,
+0xFF0E1300,
+0xFF5D6349,
+0xFF54583F,
+0xFF272913,
+0xFF424226,
+0xFF898B64,
+0xFF6A7044,
+0xFF626B3E,
+0xFF747F55,
+0xFF212807,
+0xFF434A28,
+0xFF888F63,
+0xFF717946,
+0xFF545D28,
+0xFF525D25,
+0xFF738143,
+0xFF738143,
+0xFF5E6D36,
+0xFF6F7E47,
+0xFF8E9E5D,
+0xFF8FA05C,
+0xFFB2C281,
+0xFF6E7C3E,
+0xFF77854A,
+0xFF5E692F,
+0xFF7E864A,
+0xFF99A263,
+0xFF919D5F,
+0xFF77854A,
+0xFF596631,
+0xFFA7B17D,
+0xFF5E6633,
+0xFFA4AC73,
+0xFF6D7635,
+0xFF77823E,
+0xFF7A8541,
+0xFF6E783B,
+0xFF717542,
+0xFF505422,
+0xFF7B804A,
+0xFF596126,
+0xFF7F874C,
+0xFF9BA368,
+0xFF7B8046,
+0xFF8E9359,
+0xFF797E46,
+0xFF979C64,
+0xFF8D925A,
+0xFF575C24,
+0xFF6A713B,
+0xFF585F29,
+0xFF9CA36F,
+0xFF565D29,
+0xFF828956,
+0xFF6F7640,
+0xFF818749,
+0xFF747A3C,
+0xFF6F7340,
+0xFF5B5D2C,
+0xFF888B56,
+0xFF5F5F2D,
+0xFF8E8C63,
+0xFF7E7A54,
+0xFF716E41,
+0xFF7E7B50,
+0xFF635D3D,
+0xFF534D35,
+0xFF766D5E,
+0xFF3F372C,
+0xFF483E34,
+0xFF352C1D,
+0xFF7E7663,
+0xFF6E664F,
+0xFF9B9478,
+0xFF6A6545,
+0xFF797552,
+0xFF4C4727,
+0xFF544E36,
+0xFF736D57,
+0xFF393518,
+0xFF5E5A3F,
+0xFF413C28,
+0xFF494333,
+0xFF716A58,
+0xFF504A34,
+0xFF363016,
+0xFF686346,
+0xFF565036,
+0xFF514C2E,
+0xFF716E45,
+0xFFA6A577,
+0xFF7C7B4F,
+0xFF5A5B31,
+0xFF373711,
+0xFF989A72,
+0xFF888C5A,
+0xFF676E3A,
+0xFF848B58,
+0xFF737B4C,
+0xFF7D8259,
+0xFF5D6438,
+0xFF737C45,
+0xFF828D51,
+0xFF737E42,
+0xFF616F34,
+0xFF7B864C,
+0xFF4A571F,
+0xFF8A955D,
+0xFF7C8951,
+0xFF788349,
+0xFF626D33,
+0xFF758044,
+0xFF727E40,
+0xFF8E985C,
+0xFF677037,
+0xFF5E6531,
+0xFF6C7340,
+0xFF727546,
+0xFF5B5E31,
+0xFFADB081,
+0xFF9DA16F,
+0xFF5B5F2C,
+0xFF8C905D,
+0xFF6F7340,
+0xFF686C39,
+0xFF6B6F3D,
+0xFF878B59,
+0xFF797D4A,
+0xFF585F29,
+0xFF848E52,
+0xFF566224,
+0xFF839154,
+0xFF66753A,
+0xFF798752,
+0xFF465723,
+0xFF768856,
+0xFF819361,
+0xFF4E5F2B,
+0xFF43511C,
+0xFF66733D,
+0xFF424F19,
+0xFF9CA671,
+0xFF6B7540,
+0xFF555F2A,
+0xFF87915C,
+0xFF6E7844,
+0xFF414918,
+0xFF6F7545,
+0xFF414717,
+0xFF6F7245,
+0xFF5F6233,
+0xFF443E1C,
+0xFF504B2B,
+0xFF575435,
+0xFF4B4C2C,
+0xFF3D441B,
+0xFF2B330A,
+0xFF606841,
+0xFF303612,
+0xFF4D512E,
+0xFF4A4B29,
+0xFF4D4D29,
+0xFF565632,
+0xFF3A391A,
+0xFF393A1B,
+0xFF737454,
+0xFF343815,
+0xFF353914,
+0xFF646843,
+0xFF5E623D,
+0xFF535933,
+0xFF515731,
+0xFF6D754E,
+0xFF66704B,
+0xFF49542C,
+0xFF1D2800,
+0xFF222E06,
+0xFF434E26,
+0xFF56623C,
+0xFF394320,
+0xFF2B3513,
+0xFF343D1E,
+0xFF475031,
+0xFF7F8667,
+0xFF5D6442,
+0xFF919972,
+0xFF545C33,
+0xFF303813,
+0xFF656C4A,
+0xFF44492B,
+0xFF5F6348,
+0xFF393E20,
+0xFF494E2E,
+0xFF404624,
+0xFF6B714D,
+0xFF585E3A,
+0xFF41481F,
+0xFF959D6E,
+0xFF565C2E,
+0xFF3A3B19,
+0xFF2C2D0D,
+0xFF3C3E19,
+0xFF454722,
+0xFF4F5031,
+0xFF434128,
+0xFF797762,
+0xFF414024,
+0xFF53542C,
+0xFF6A6B3F,
+0xFF40401C,
+0xFF4E4E2C,
+0xFF6B6B47,
+0xFF67653F,
+0xFF75724F,
+0xFF676443,
+0xFF4E4B2C,
+0xFF333011,
+0xFF746E4C,
+0xFF4C4622,
+0xFF635F3A,
+0xFFADAC97,
+0xFF3F4247,
+0xFF292E42,
+0xFF2D3447,
+0xFF2B3245,
+0xFF1E2337,
+0xFF222538,
+0xFF27253A,
+0xFF232438,
+0xFF202332,
+0xFF191D29,
+0xFF121420,
+0xFF121318,
+0xFF0D0F0E,
+0xFF030502,
+0xFF030303,
+0xFF191A14,
+0xFF2B2D15,
+0xFF454926,
+0xFF3D431D,
+0xFF7C835A,
+0xFF6C744F,
+0xFFA9B295,
+0xFF4B5443,
+0xFF757B7B,
+0xFF5C6174,
+0xFF353A4E,
+0xFF596068,
+0xFF2B3238,
+0xFF2A2E3A,
+0xFF181C28,
+0xFF0D1015,
+0xFF181C1F,
+0xFF08090E,
+0xFF16171B,
+0xFF111111,
+0xFF404139,
+0xFF6D6E5C,
+0xFF4F5237,
+0xFF66694C,
+0xFF4E5136,
+0xFF4C4E36,
+0xFF3E422B,
+0xFF111600,
+0xFF242913,
+0xFF3F422D,
+0xFF20230E,
+0xFF35371F,
+0xFF1A1C04,
+0xFF4C4D3B,
+0xFF2C2E19,
+0xFF565A3F,
+0xFF5B6040,
+0xFF6C7352,
+0xFF565D3B,
+0xFF505630,
+0xFF242B02,
+0xFF797D5A,
+0xFF424621,
+0xFF33390B,
+0xFF6F7341,
+0xFF868654,
+0xFF797B49,
+0xFF535C27,
+0xFF98A16C,
+0xFF757947,
+0xFF8B8D5C,
+0xFF626435,
+0xFF8D9063,
+0xFF686F43,
+0xFF4F5529,
+0xFF64623B,
+0xFF737148,
+0xFF5F6237,
+0xFF535B2C,
+0xFF949E6C,
+0xFF667242,
+0xFF354015,
+0xFF777F5A,
+0xFF72785C,
+0xFF2A3110,
+0xFF40491A,
+0xFF8F9964,
+0xFFA4AF77,
+0xFF6A7440,
+0xFFA3AC81,
+0xFF535B36,
+0xFF767E59,
+0xFF3C441F,
+0xFF202803,
+0xFF808766,
+0xFF1A1E05,
+0xFF575A45,
+0xFF0D1200,
+0xFF515640,
+0xFF1C2506,
+0xFF4F5839,
+0xFF263015,
+0xFF737C67,
+0xFF1B2413,
+0xFF1F2614,
+0xFF0B1300,
+0xFFA1A889,
+0xFF0D1300,
+0xFF81865E,
+0xFF93996B,
+0xFF353E09,
+0xFFA6B57C,
+0xFF64753E,
+0xFF2E3B0F,
+0xFF3B481C,
+0xFF838F5D,
+0xFF8A9761,
+0xFF637038,
+0xFF59662E,
+0xFF6B793E,
+0xFF5F6E35,
+0xFF2E3C09,
+0xFF8F9D6A,
+0xFFBFCC94,
+0xFFABB97E,
+0xFF5D6B30,
+0xFF5C6A2F,
+0xFF85925C,
+0xFF545F27,
+0xFFA1AA6B,
+0xFF909956,
+0xFF9BA863,
+0xFF9FAE6D,
+0xFF818F54,
+0xFF96A36D,
+0xFF59602C,
+0xFF8D955C,
+0xFF6D7637,
+0xFF7B8642,
+0xFF7C8944,
+0xFF717B3C,
+0xFF9EA36B,
+0xFF6B703A,
+0xFF787D43,
+0xFF6D7337,
+0xFF9BA165,
+0xFFA7AD71,
+0xFF848A4E,
+0xFF898F53,
+0xFF7A7F45,
+0xFF676C32,
+0xFF82874F,
+0xFF858A52,
+0xFF80854F,
+0xFF777C46,
+0xFF5A5E2B,
+0xFF919563,
+0xFF585E2E,
+0xFF666D37,
+0xFF848D4E,
+0xFF747C40,
+0xFF72784A,
+0xFF4F5129,
+0xFF636639,
+0xFF7B7C50,
+0xFF72734B,
+0xFF7B7952,
+0xFF89885A,
+0xFF6C6B3F,
+0xFF76724D,
+0xFF7A7758,
+0xFF514B31,
+0xFFAAA58F,
+0xFF47402E,
+0xFF4C4532,
+0xFF68624A,
+0xFF4D482B,
+0xFF5E5939,
+0xFF8D8964,
+0xFF5B582F,
+0xFF83815A,
+0xFF4F4C2B,
+0xFF908D6E,
+0xFF73704F,
+0xFF565332,
+0xFF453F25,
+0xFF342E16,
+0xFF383115,
+0xFF726B4E,
+0xFF716B49,
+0xFF7A7454,
+0xFF5F5742,
+0xFF4F4730,
+0xFF57522C,
+0xFF797649,
+0xFF858257,
+0xFF828057,
+0xFF666340,
+0xFF6B6B45,
+0xFFA6A77B,
+0xFF707442,
+0xFF8A8D5E,
+0xFF6D7345,
+0xFF54562E,
+0xFF8B9165,
+0xFF6D7440,
+0xFF4A5219,
+0xFF949E62,
+0xFF545F23,
+0xFF707940,
+0xFF5F6A30,
+0xFF5B642D,
+0xFF6A753D,
+0xFF677037,
+0xFF6B743B,
+0xFF6B7539,
+0xFF687236,
+0xFF636B32,
+0xFF7F8650,
+0xFF6B6F3D,
+0xFF606334,
+0xFF62653A,
+0xFF93966B,
+0xFF3B3C12,
+0xFF97986C,
+0xFF676937,
+0xFF9B9E69,
+0xFF757841,
+0xFF7F824B,
+0xFF8D905B,
+0xFF878B58,
+0xFF737744,
+0xFF787F4B,
+0xFF7E8750,
+0xFF69743A,
+0xFF49571C,
+0xFF58672C,
+0xFF97A66D,
+0xFF5E6F38,
+0xFF384B14,
+0xFF61743D,
+0xFF42531C,
+0xFF54632C,
+0xFF435018,
+0xFF6B7842,
+0xFF949E69,
+0xFF555F2B,
+0xFF535D2B,
+0xFF6E7846,
+0xFF4D5524,
+0xFF5D6534,
+0xFF818757,
+0xFF7F8653,
+0xFF646835,
+0xFF4C4F1A,
+0xFF504D2C,
+0xFF464526,
+0xFF515233,
+0xFF3F4523,
+0xFF3C471F,
+0xFF343F15,
+0xFF38421D,
+0xFF454C2A,
+0xFF474B2A,
+0xFF626343,
+0xFF494927,
+0xFF5E5B3A,
+0xFF49482A,
+0xFF38391A,
+0xFF373B1A,
+0xFF2A300C,
+0xFF2A300E,
+0xFF434927,
+0xFF616743,
+0xFF737B54,
+0xFF525A31,
+0xFF5F6A40,
+0xFF313E13,
+0xFF606F44,
+0xFF69784D,
+0xFF505F34,
+0xFF5C6B42,
+0xFF424E28,
+0xFF535F3B,
+0xFF1C2804,
+0xFF232D0B,
+0xFF495331,
+0xFF333A1B,
+0xFF444929,
+0xFF282C09,
+0xFF5C603B,
+0xFF5D5E3E,
+0xFF515233,
+0xFF63664B,
+0xFF505338,
+0xFF31351A,
+0xFF212608,
+0xFF3F4523,
+0xFF343A16,
+0xFF4F552F,
+0xFF535A31,
+0xFF7A8253,
+0xFF4F5529,
+0xFF4E4F2F,
+0xFF38391A,
+0xFF7E7F5D,
+0xFF3F401E,
+0xFF404122,
+0xFF57573D,
+0xFF44442A,
+0xFF333415,
+0xFF676840,
+0xFF4F5026,
+0xFF787856,
+0xFF545432,
+0xFF7D7D59,
+0xFF43431D,
+0xFF5F5C39,
+0xFF73704F,
+0xFF626142,
+0xFF666344,
+0xFF676044,
+0xFF2F250A,
+0xFF7E795B,
+0xFF81806E,
+0xFF2F323B,
+0xFF292E44,
+0xFF272F44,
+0xFF232A3D,
+0xFF1A1D30,
+0xFF2B2C40,
+0xFF303145,
+0xFF292A3C,
+0xFF212433,
+0xFF1B1F2A,
+0xFF15151F,
+0xFF1D1D25,
+0xFF080C0D,
+0xFF060805,
+0xFF000000,
+0xFF303024,
+0xFF6A6D50,
+0xFF868A65,
+0xFF858B65,
+0xFF6B714B,
+0xFF757B55,
+0xFF59603F,
+0xFF757D66,
+0xFF4B5348,
+0xFF484C55,
+0xFF373B46,
+0xFF48514C,
+0xFF040B03,
+0xFF000604,
+0xFF000300,
+0xFFCFD5CB,
+0xFFDEE2D4,
+0xFF1C1F18,
+0xFF010400,
+0xFF0D0E08,
+0xFF48483E,
+0xFF353624,
+0xFF454731,
+0xFF343620,
+0xFF272B14,
+0xFF5A5E47,
+0xFF383D26,
+0xFF484C3B,
+0xFF161A09,
+0xFF575A49,
+0xFF40422D,
+0xFF5F6149,
+0xFF42452A,
+0xFF171901,
+0xFF676B52,
+0xFF2F331A,
+0xFF5A5E43,
+0xFF393E20,
+0xFF575C3C,
+0xFF949A76,
+0xFF4A502A,
+0xFF5A603C,
+0xFF3F461D,
+0xFF3E4617,
+0xFF5F6633,
+0xFF888A58,
+0xFF686A38,
+0xFF5D6631,
+0xFF8F9863,
+0xFF6F7341,
+0xFF656839,
+0xFF606137,
+0xFF7B7C54,
+0xFF5F6237,
+0xFF585B30,
+0xFF747249,
+0xFF59572E,
+0xFF81875B,
+0xFF707849,
+0xFF838D5B,
+0xFF838C5D,
+0xFF4B5429,
+0xFFA3AB86,
+0xFF565D3E,
+0xFF0C1300,
+0xFF626C38,
+0xFFA0AB71,
+0xFF87925A,
+0xFF3F4917,
+0xFF60673E,
+0xFF3D4520,
+0xFF8A926D,
+0xFF6B734C,
+0xFF343C15,
+0xFF7E8563,
+0xFF1E2209,
+0xFF444732,
+0xFF0C1100,
+0xFF0B1000,
+0xFF73795D,
+0xFF313A1B,
+0xFF151E01,
+0xFF6C765D,
+0xFF464F3A,
+0xFF162007,
+0xFF2B3415,
+0xFF818C64,
+0xFFB5C095,
+0xFF535D2B,
+0xFF848D58,
+0xFF768147,
+0xFF6D7F41,
+0xFF8CA063,
+0xFF485922,
+0xFF63743E,
+0xFF65733E,
+0xFF96A46F,
+0xFF4A5721,
+0xFF5F6C34,
+0xFF717E46,
+0xFF74834A,
+0xFF9EAC77,
+0xFFBFCD98,
+0xFF83925B,
+0xFF8C9B62,
+0xFF536126,
+0xFF3D4C11,
+0xFF69783F,
+0xFF869459,
+0xFF8E9859,
+0xFF8E9955,
+0xFF9DAD66,
+0xFFA7B872,
+0xFF6A783A,
+0xFF8D9B60,
+0xFF5F682F,
+0xFF7E874E,
+0xFF99A166,
+0xFF8F995C,
+0xFF869252,
+0xFF687434,
+0xFF858A50,
+0xFF8A8F55,
+0xFF7E8349,
+0xFF82874D,
+0xFFB2B77D,
+0xFF777C42,
+0xFF787B42,
+0xFF878C52,
+0xFF898E56,
+0xFF787F49,
+0xFF7C8149,
+0xFF5C6129,
+0xFF9A9F69,
+0xFF797B49,
+0xFF7A7C4A,
+0xFF939765,
+0xFF7D8051,
+0xFF7A814D,
+0xFFA1A769,
+0xFF81874B,
+0xFF858859,
+0xFF8E9068,
+0xFF686B40,
+0xFF777951,
+0xFF5C5C36,
+0xFF6B6B45,
+0xFFB4B387,
+0xFF3D3C0E,
+0xFF68663F,
+0xFF706D4A,
+0xFF322F10,
+0xFF918D72,
+0xFF8A856F,
+0xFF45402A,
+0xFF656043,
+0xFF676242,
+0xFF4E4A27,
+0xFF6C6A43,
+0xFF7D7F4E,
+0xFF767847,
+0xFF787951,
+0xFF5B5B35,
+0xFF7D7E56,
+0xFF4D4D27,
+0xFF706C4F,
+0xFF4A4629,
+0xFF5B5734,
+0xFF5C5832,
+0xFF8B885F,
+0xFF797552,
+0xFF69614C,
+0xFF584D39,
+0xFF5D5433,
+0xFF565127,
+0xFF403D12,
+0xFFA6A37A,
+0xFF4F4D27,
+0xFF615F38,
+0xFF5F6034,
+0xFF747846,
+0xFF666D3A,
+0xFF5F6633,
+0xFF494F21,
+0xFF53592B,
+0xFF747B48,
+0xFF525925,
+0xFF919862,
+0xFF8A935A,
+0xFF6A753B,
+0xFF57622A,
+0xFF545E29,
+0xFF77824A,
+0xFF454E15,
+0xFF7D874B,
+0xFF838D51,
+0xFF7F874C,
+0xFF6E733B,
+0xFF858853,
+0xFF9A9C6B,
+0xFF727445,
+0xFF606137,
+0xFF74754B,
+0xFF797A4E,
+0xFF87895A,
+0xFF60602E,
+0xFF8F8F5B,
+0xFF73763D,
+0xFF84874E,
+0xFF5E632B,
+0xFF848855,
+0xFF8B8D5C,
+0xFF747645,
+0xFF787C49,
+0xFF464D17,
+0xFF5B662C,
+0xFF68763B,
+0xFF717E46,
+0xFF64713B,
+0xFF77864F,
+0xFF586932,
+0xFF566730,
+0xFF63743D,
+0xFF819059,
+0xFF78854F,
+0xFF5F6937,
+0xFF525B2C,
+0xFF5E6738,
+0xFF687142,
+0xFF6A7442,
+0xFF646C39,
+0xFF7F8754,
+0xFF69703D,
+0xFF646835,
+0xFF797C47,
+0xFF3D4023,
+0xFF353A1C,
+0xFF454C2D,
+0xFF4D5735,
+0xFF5A6640,
+0xFF243008,
+0xFF26300D,
+0xFF464D2E,
+0xFF4C4F34,
+0xFF2C2A11,
+0xFF353116,
+0xFF504F33,
+0xFF49492F,
+0xFF303316,
+0xFF333A18,
+0xFF404A25,
+0xFF404725,
+0xFF505735,
+0xFF6C7351,
+0xFF6F7954,
+0xFF6D7953,
+0xFF3A4920,
+0xFF304117,
+0xFF405125,
+0xFF2C3D11,
+0xFF3D4E22,
+0xFF5A6B3F,
+0xFF64734A,
+0xFF4F5E35,
+0xFF4C5B32,
+0xFF424E26,
+0xFF49532E,
+0xFF383F20,
+0xFF36391E,
+0xFF8D896E,
+0xFF696248,
+0xFF40361D,
+0xFF5F583C,
+0xFF4F4C2B,
+0xFF585937,
+0xFF2E3412,
+0xFF39401E,
+0xFF2B310D,
+0xFF5A603C,
+0xFF474B2A,
+0xFF656946,
+0xFF747950,
+0xFF51562D,
+0xFF4A4E2D,
+0xFF484C2B,
+0xFF5A5E39,
+0xFF343813,
+0xFF585C3B,
+0xFF5D6140,
+0xFF3F4320,
+0xFF3B3F1A,
+0xFF5E6039,
+0xFF484A25,
+0xFF525132,
+0xFF737253,
+0xFF413E1D,
+0xFF5B5835,
+0xFF464324,
+0xFF50502E,
+0xFFABB289,
+0xFF484C29,
+0xFF261D0C,
+0xFF4B3F33,
+0xFF504936,
+0xFF444236,
+0xFF383745,
+0xFF2B2F48,
+0xFF2B324C,
+0xFF232941,
+0xFF222337,
+0xFF252436,
+0xFF1C1D2F,
+0xFF282B3A,
+0xFF1F232F,
+0xFF252934,
+0xFF22222C,
+0xFF2D3039,
+0xFF0A0E17,
+0xFF0A0E11,
+0xFF0D0D05,
+0xFF73725D,
+0xFF92976F,
+0xFFB0B78B,
+0xFF1A2100,
+0xFF6C724C,
+0xFF72744D,
+0xFF555934,
+0xFF838C6F,
+0xFF444D38,
+0xFF2F3325,
+0xFF4F554B,
+0xFF141C0F,
+0xFF000500,
+0xFF000300,
+0xFF929783,
+0xFFE4EBC9,
+0xFFCCD4AD,
+0xFFD5DBBF,
+0xFF646953,
+0xFF000200,
+0xFF414234,
+0xFF221F0E,
+0xFF63624E,
+0xFF4B4C3C,
+0xFF1D220C,
+0xFF64704C,
+0xFF5B6946,
+0xFF131A08,
+0xFF212517,
+0xFF262715,
+0xFF74745C,
+0xFF555539,
+0xFF707453,
+0xFF4F5531,
+0xFF5A613F,
+0xFF101600,
+0xFF4B5137,
+0xFF313415,
+0xFF919572,
+0xFF525631,
+0xFF232800,
+0xFF636B44,
+0xFF3A4318,
+0xFF4D5725,
+0xFF868F5A,
+0xFF747B45,
+0xFF636A34,
+0xFF8F9863,
+0xFF949C69,
+0xFF5C6232,
+0xFF8D9367,
+0xFF393915,
+0xFF64613E,
+0xFF706B41,
+0xFF615D30,
+0xFF8E8B62,
+0xFF45461E,
+0xFFA6AD81,
+0xFF576031,
+0xFF4C5423,
+0xFFABB183,
+0xFFADB48A,
+0xFF3F4720,
+0xFF626A45,
+0xFF2B330A,
+0xFF6F7843,
+0xFF677039,
+0xFF6F7746,
+0xFF5C633A,
+0xFF4E5134,
+0xFF52563B,
+0xFF848A68,
+0xFF474D27,
+0xFF5F663D,
+0xFF4D542B,
+0xFF474B28,
+0xFF3A3F21,
+0xFF121700,
+0xFF717662,
+0xFF3F422D,
+0xFF33371E,
+0xFF616B49,
+0xFF47512C,
+0xFF404D22,
+0xFF485529,
+0xFF737F51,
+0xFF758151,
+0xFF657642,
+0xFF60713A,
+0xFF86955A,
+0xFF617133,
+0xFF8A9B64,
+0xFF73844D,
+0xFF9FB173,
+0xFF2C3C00,
+0xFF6C7944,
+0xFF6C7846,
+0xFF4A5324,
+0xFF3D4A15,
+0xFF5C6A2D,
+0xFFB9C789,
+0xFF506022,
+0xFF829156,
+0xFF87995D,
+0xFF516325,
+0xFF445916,
+0xFF728744,
+0xFF718444,
+0xFFA8B879,
+0xFF677538,
+0xFF657433,
+0xFF97AB64,
+0xFF889C54,
+0xFFB3C27F,
+0xFF404C0A,
+0xFFABBC78,
+0xFF7B894B,
+0xFFABB27C,
+0xFF7F8652,
+0xFF7B844D,
+0xFF747D44,
+0xFF7E864D,
+0xFF9CA167,
+0xFF81864E,
+0xFFAAAF77,
+0xFFA5A871,
+0xFF656831,
+0xFF696933,
+0xFF90935E,
+0xFF6D7343,
+0xFF818956,
+0xFF90985F,
+0xFF71793E,
+0xFF444614,
+0xFF787846,
+0xFF6D6D3B,
+0xFF70703E,
+0xFF474918,
+0xFF818552,
+0xFF64672E,
+0xFF8F9259,
+0xFF828550,
+0xFF626435,
+0xFF4F5129,
+0xFF8A8C67,
+0xFF8D8A69,
+0xFF5F5C39,
+0xFF6A6B41,
+0xFF5A5B2F,
+0xFF5F5C33,
+0xFF75714C,
+0xFF504F30,
+0xFF434226,
+0xFFA8A68D,
+0xFF2C280D,
+0xFF797454,
+0xFF716D4A,
+0xFF7A7555,
+0xFF383911,
+0xFF8D925A,
+0xFF747C41,
+0xFF8A9261,
+0xFF838A5E,
+0xFF7F8555,
+0xFF656B3F,
+0xFF303112,
+0xFF505132,
+0xFF66673D,
+0xFF9EA071,
+0xFF6D6E42,
+0xFF4D4B25,
+0xFF7F795F,
+0xFF736B54,
+0xFF918668,
+0xFF7C724F,
+0xFF5A572E,
+0xFF868559,
+0xFF817E53,
+0xFF9F9E70,
+0xFF606231,
+0xFF494D1A,
+0xFF7F8A50,
+0xFF849257,
+0xFF4B541D,
+0xFF545C29,
+0xFF5E6836,
+0xFF717A4B,
+0xFF868C5C,
+0xFF606734,
+0xFF6F7C46,
+0xFF44531C,
+0xFF717F4A,
+0xFF7D8A55,
+0xFF69743A,
+0xFF7A8448,
+0xFF6C763A,
+0xFF84894F,
+0xFF585824,
+0xFF7C7A49,
+0xFF837D4D,
+0xFF726E3F,
+0xFF76744B,
+0xFF555428,
+0xFF9D9D69,
+0xFF60602A,
+0xFF7B7946,
+0xFF757541,
+0xFF818650,
+0xFF323A01,
+0xFF545B25,
+0xFF8F9360,
+0xFF6E6B3E,
+0xFF737043,
+0xFF7B7949,
+0xFF6D6F3D,
+0xFF6B723C,
+0xFF5D662D,
+0xFF7E8750,
+0xFF57602B,
+0xFF4E5824,
+0xFF74804E,
+0xFF465421,
+0xFF637440,
+0xFF5D6E3A,
+0xFF697744,
+0xFF364214,
+0xFF757E53,
+0xFF444B1F,
+0xFF5D6735,
+0xFF68733B,
+0xFF5F6A32,
+0xFF78824D,
+0xFF606835,
+0xFF727546,
+0xFF828556,
+0xFF32361B,
+0xFF383F20,
+0xFF273011,
+0xFF283313,
+0xFF3B4624,
+0xFF222D0B,
+0xFF1E2708,
+0xFF1E2408,
+0xFF282A14,
+0xFF2F2E19,
+0xFF48462F,
+0xFF35351B,
+0xFF43462B,
+0xFF515638,
+0xFF454F2C,
+0xFF59633E,
+0xFF434A28,
+0xFF363D1B,
+0xFF161D00,
+0xFF535D3A,
+0xFF48542E,
+0xFF4C5B34,
+0xFF2D3C13,
+0xFF192A00,
+0xFF3B4C22,
+0xFF404F26,
+0xFF54633A,
+0xFF5D6941,
+0xFF67734B,
+0xFF4F5A32,
+0xFF414C24,
+0xFF3E4422,
+0xFF242408,
+0xFF605C43,
+0xFF544A31,
+0xFF322610,
+0xFF554633,
+0xFF6A5E46,
+0xFF4C4825,
+0xFF393913,
+0xFF464C28,
+0xFF454C2A,
+0xFF424824,
+0xFF585E3A,
+0xFF3C401F,
+0xFF6C704D,
+0xFF33380F,
+0xFF62673E,
+0xFF2A2E0D,
+0xFF303413,
+0xFF383E1A,
+0xFF4B512D,
+0xFF363C1A,
+0xFF949A76,
+0xFF828661,
+0xFF898E66,
+0xFF333712,
+0xFF3F401E,
+0xFF666747,
+0xFF525132,
+0xFF3E3E1C,
+0xFF585534,
+0xFF817E5F,
+0xFF414220,
+0xFF5E673A,
+0xFF1E2500,
+0xFF171100,
+0xFF3E3526,
+0xFF595441,
+0xFF38362A,
+0xFF272229,
+0xFF2B283B,
+0xFF2B2E41,
+0xFF292E41,
+0xFF1D1C2E,
+0xFF1D1C2E,
+0xFF242335,
+0xFF1A1C29,
+0xFF191C25,
+0xFF15181F,
+0xFF36373C,
+0xFF1C1D22,
+0xFF06090E,
+0xFF020605,
+0xFF151304,
+0xFF5A593D,
+0xFF6F744B,
+0xFF6B7246,
+0xFF484E2A,
+0xFF4C502D,
+0xFF505328,
+0xFF777D51,
+0xFF444E29,
+0xFF424D2F,
+0xFF848973,
+0xFF5C6051,
+0xFF767C72,
+0xFF585E54,
+0xFF242819,
+0xFF151900,
+0xFFAEB58B,
+0xFFB9C192,
+0xFFA6AC86,
+0xFF595E40,
+0xFF5F604E,
+0xFF151304,
+0xFF151203,
+0xFF696655,
+0xFF262715,
+0xFF52583C,
+0xFF708053,
+0xFF78875C,
+0xFF262D1B,
+0xFF090B00,
+0xFF181705,
+0xFF58583E,
+0xFF696947,
+0xFF868B63,
+0xFF878E64,
+0xFF5B663E,
+0xFF0C1200,
+0xFF181E04,
+0xFF838667,
+0xFFABAC8A,
+0xFF202200,
+0xFF73784F,
+0xFF7F885D,
+0xFF808C5E,
+0xFF8B9863,
+0xFF6D7840,
+0xFF666F38,
+0xFFB7C089,
+0xFF808A55,
+0xFF707A45,
+0xFF56602C,
+0xFF959C70,
+0xFF42441F,
+0xFF484522,
+0xFF888457,
+0xFF888455,
+0xFF6A6640,
+0xFF80825A,
+0xFF828A5B,
+0xFF76804E,
+0xFF373B08,
+0xFFC8CC9A,
+0xFF767C50,
+0xFF5F673E,
+0xFF3A4318,
+0xFF8D9667,
+0xFF6D763F,
+0xFF777E48,
+0xFF7A8052,
+0xFF3F441C,
+0xFF505336,
+0xFF5C6143,
+0xFF767C56,
+0xFF5D643A,
+0xFF777E54,
+0xFF42471E,
+0xFF787D55,
+0xFF2C300F,
+0xFF6F755B,
+0xFF232611,
+0xFF3C3E28,
+0xFF4F4F35,
+0xFF868C68,
+0xFF6F784B,
+0xFF313B07,
+0xFF909B63,
+0xFF7B844F,
+0xFF545E29,
+0xFF5B6C36,
+0xFF9CAD76,
+0xFF516025,
+0xFF94A368,
+0xFF7D8C55,
+0xFF697A43,
+0xFFB2C283,
+0xFF69793A,
+0xFF38450F,
+0xFFA0AC7A,
+0xFF727C4A,
+0xFFBECB95,
+0xFF606F2E,
+0xFFBFD08C,
+0xFF4E5E1F,
+0xFFA8BB7B,
+0xFF768B4A,
+0xFF324704,
+0xFF768D47,
+0xFF6B803B,
+0xFF5A6D2D,
+0xFF6D7D3F,
+0xFF3A480B,
+0xFF768645,
+0xFF61772E,
+0xFF94AA5F,
+0xFF93A35A,
+0xFF4A5A13,
+0xFF8FA35B,
+0xFF92A661,
+0xFF6C753C,
+0xFFACB37D,
+0xFF778248,
+0xFF677335,
+0xFF929B5C,
+0xFFADB677,
+0xFF878F54,
+0xFF90985F,
+0xFF70733E,
+0xFF53531F,
+0xFF777542,
+0xFF8E8E5C,
+0xFF4F5225,
+0xFF757D4E,
+0xFF7C854E,
+0xFF828B54,
+0xFF757947,
+0xFF5A5C2D,
+0xFF666535,
+0xFF6F6E3E,
+0xFF5C5E2F,
+0xFF686A39,
+0xFF7B7E45,
+0xFF61652A,
+0xFF8A8A54,
+0xFF707241,
+0xFF62673E,
+0xFF6D714C,
+0xFF898665,
+0xFF83815B,
+0xFF74774A,
+0xFF717445,
+0xFFA29F74,
+0xFF5D5B34,
+0xFF525230,
+0xFF4C4D2D,
+0xFF858664,
+0xFF4D4D29,
+0xFF736F4A,
+0xFF58542F,
+0xFF5F5D37,
+0xFF636639,
+0xFF454D12,
+0xFF98A466,
+0xFF8F9964,
+0xFF838D59,
+0xFF8A935C,
+0xFF5A622F,
+0xFF373B16,
+0xFF434722,
+0xFF636939,
+0xFF808754,
+0xFF535627,
+0xFF52542C,
+0xFF5F5F3D,
+0xFF3F3A1C,
+0xFF988F70,
+0xFF7F7753,
+0xFF908E67,
+0xFF606135,
+0xFF9F9F6D,
+0xFF848450,
+0xFF848654,
+0xFF848B55,
+0xFF768446,
+0xFF8F9D5F,
+0xFF586027,
+0xFF626935,
+0xFF596331,
+0xFF3A4314,
+0xFF585B2E,
+0xFF545A2C,
+0xFF525F2A,
+0xFF879862,
+0xFF435420,
+0xFF778550,
+0xFF46531B,
+0xFF586327,
+0xFF96A064,
+0xFF81864C,
+0xFF7C7C46,
+0xFF73703D,
+0xFF958D5C,
+0xFF716B3B,
+0xFF8C895E,
+0xFF4C4E1F,
+0xFF8B8E57,
+0xFF73743B,
+0xFF787645,
+0xFF717040,
+0xFF767D49,
+0xFF646D38,
+0xFF5B642F,
+0xFF525926,
+0xFF565328,
+0xFF817C52,
+0xFF9A9667,
+0xFF555523,
+0xFF7A814B,
+0xFF576027,
+0xFF707741,
+0xFF5C602D,
+0xFF59602C,
+0xFF808A56,
+0xFF374514,
+0xFF485827,
+0xFF495A26,
+0xFF758350,
+0xFF515D2F,
+0xFF697245,
+0xFF676F40,
+0xFF545E2A,
+0xFF6D7B40,
+0xFF5A682D,
+0xFF57612C,
+0xFF68703F,
+0xFF646A3A,
+0xFF525526,
+0xFF2D3415,
+0xFF505A38,
+0xFF232D0B,
+0xFF313A1B,
+0xFF2D361B,
+0xFF0F1400,
+0xFF1A1F08,
+0xFF232710,
+0xFF20240D,
+0xFF363822,
+0xFF32341E,
+0xFF2C2F14,
+0xFF434828,
+0xFF474D2B,
+0xFF4A512F,
+0xFF3D4422,
+0xFF222A05,
+0xFF303813,
+0xFF4A522D,
+0xFF252D08,
+0xFF838D68,
+0xFF929C77,
+0xFF404A25,
+0xFF232D08,
+0xFF333D18,
+0xFF36401B,
+0xFF666D4B,
+0xFF4F5533,
+0xFF414626,
+0xFF2E3112,
+0xFF272A0B,
+0xFF565235,
+0xFF968A70,
+0xFF5D4D34,
+0xFF42341A,
+0xFF52432C,
+0xFF40341E,
+0xFF393218,
+0xFF413E1B,
+0xFF393B16,
+0xFF404324,
+0xFF43482A,
+0xFF474E2C,
+0xFF3E4422,
+0xFF333818,
+0xFF252906,
+0xFF484D24,
+0xFF646940,
+0xFF6C704F,
+0xFF5D6242,
+0xFF353819,
+0xFF393C1D,
+0xFF2A2E0D,
+0xFF4D5130,
+0xFF7D7E5C,
+0xFF8B8F6A,
+0xFF797D58,
+0xFF616540,
+0xFF393D18,
+0xFF484A25,
+0xFF494A28,
+0xFF434321,
+0xFF7C7B5C,
+0xFF6D6F4A,
+0xFF474D21,
+0xFF4A5022,
+0xFFB8B690,
+0xFF7C7958,
+0xFF5B5A3E,
+0xFF46412E,
+0xFF372825,
+0xFF251619,
+0xFF2A2627,
+0xFF3A3B40,
+0xFF242335,
+0xFF211E33,
+0xFF211A2C,
+0xFF221F2A,
+0xFF303136,
+0xFF202123,
+0xFF383836,
+0xFF0C0D08,
+0xFF020500,
+0xFF1E2012,
+0xFF54523D,
+0xFF444023,
+0xFF363715,
+0xFF515534,
+0xFF515437,
+0xFF3A3E1D,
+0xFF3A3E0C,
+0xFF909761,
+0xFF8C986A,
+0xFF7E8967,
+0xFF000300,
+0xFF0A0C07,
+0xFF2F3237,
+0xFF23272A,
+0xFF31322C,
+0xFF424331,
+0xFF1F2302,
+0xFF595E36,
+0xFF5A5E3B,
+0xFF6A6D50,
+0xFF3F402E,
+0xFF403E31,
+0xFF373327,
+0xFF3A3726,
+0xFF57573F,
+0xFF3E441E,
+0xFF8E9B65,
+0xFF919F6C,
+0xFF393E28,
+0xFF252519,
+0xFF1C1906,
+0xFF3E3D21,
+0xFF6F6D47,
+0xFF878A5F,
+0xFF969C70,
+0xFF202800,
+0xFF151A00,
+0xFF121600,
+0xFFDEDEC2,
+0xFFA9A987,
+0xFF3F4016,
+0xFF929566,
+0xFF868E5D,
+0xFF414B17,
+0xFF86905B,
+0xFFAEB981,
+0xFF656F3A,
+0xFF9AA771,
+0xFF819059,
+0xFF617339,
+0xFF75864F,
+0xFF4A5823,
+0xFF70794C,
+0xFF7D8357,
+0xFF838554,
+0xFF929463,
+0xFF5F6139,
+0xFF202500,
+0xFF646D3E,
+0xFF8A935E,
+0xFF8F925B,
+0xFFACAF7A,
+0xFFB2B888,
+0xFF394213,
+0xFF525E2C,
+0xFF43501B,
+0xFF99A06A,
+0xFFBBBF8C,
+0xFF4B4E1F,
+0xFF7F8257,
+0xFF747B51,
+0xFF5B6439,
+0xFF868F60,
+0xFF3F4718,
+0xFF83895D,
+0xFF676941,
+0xFF3A3B19,
+0xFF717455,
+0xFF32351A,
+0xFF4D5035,
+0xFF3A361B,
+0xFF636041,
+0xFF5B5C34,
+0xFF737647,
+0xFF90955F,
+0xFF6F743A,
+0xFF3B3E05,
+0xFF9CA46B,
+0xFFA9B680,
+0xFF9EAD76,
+0xFF4D5A24,
+0xFF9CA971,
+0xFF88975E,
+0xFF79884D,
+0xFF94A466,
+0xFFA2B274,
+0xFF4C5923,
+0xFF8A9762,
+0xFFC7D49C,
+0xFF687639,
+0xFF8A9958,
+0xFFB6C783,
+0xFF8E9E5F,
+0xFF9FB272,
+0xFF485D1A,
+0xFF94A964,
+0xFF859A55,
+0xFF7A8F4C,
+0xFF5A6C30,
+0xFF7F8E53,
+0xFF404E10,
+0xFF758640,
+0xFF5D7426,
+0xFF748B39,
+0xFF7C8F3E,
+0xFF809344,
+0xFF80964B,
+0xFF8FA35C,
+0xFF6E7D3A,
+0xFF9FAB69,
+0xFF64732E,
+0xFF93A35A,
+0xFF7C883C,
+0xFF78843A,
+0xFF54611C,
+0xFF899356,
+0xFF7A7C4A,
+0xFF7A7847,
+0xFF504D18,
+0xFF82804D,
+0xFF4E5021,
+0xFF656B3D,
+0xFF76804C,
+0xFF97A16F,
+0xFF585F33,
+0xFF52582C,
+0xFF676B39,
+0xFF616332,
+0xFF62653A,
+0xFF707344,
+0xFF7E8247,
+0xFF6A6F2F,
+0xFF83864F,
+0xFF8B8F5D,
+0xFF878E64,
+0xFF575E34,
+0xFF707147,
+0xFF818354,
+0xFF7A814D,
+0xFF9DA470,
+0xFF757448,
+0xFF45461E,
+0xFF757750,
+0xFF6C7148,
+0xFF565C2E,
+0xFF757849,
+0xFF494A1E,
+0xFF7D7E52,
+0xFF888B5C,
+0xFF505723,
+0xFF7E884C,
+0xFF5B662A,
+0xFF95A068,
+0xFF5C6A2F,
+0xFF98A466,
+0xFF4D591B,
+0xFF9DA671,
+0xFF5A6231,
+0xFF394110,
+0xFF798150,
+0xFF6B7143,
+0xFF464C20,
+0xFF696E46,
+0xFF62643D,
+0xFF55532C,
+0xFF55532C,
+0xFF83855E,
+0xFF94976C,
+0xFF82854E,
+0xFF8C8F56,
+0xFF8B8E59,
+0xFF454A14,
+0xFF778345,
+0xFF727D41,
+0xFF6E7240,
+0xFF67693A,
+0xFF7D8353,
+0xFF989E6E,
+0xFF848758,
+0xFF3F4515,
+0xFF75814F,
+0xFF6A7B47,
+0xFF71824E,
+0xFF586631,
+0xFF3C4913,
+0xFF7A854D,
+0xFF7B8549,
+0xFF545C21,
+0xFF7B7F44,
+0xFFB3B27A,
+0xFF9A9462,
+0xFF7A7646,
+0xFF9F9E70,
+0xFF6A6E3C,
+0xFF7D844E,
+0xFF6C713B,
+0xFF535526,
+0xFF545627,
+0xFF8F9663,
+0xFF4D5522,
+0xFF5B6531,
+0xFF5F6535,
+0xFF88865D,
+0xFF565328,
+0xFF555424,
+0xFF777947,
+0xFF949D66,
+0xFF767F46,
+0xFF5F6630,
+0xFF686D37,
+0xFF7A8249,
+0xFF68713A,
+0xFF596631,
+0xFF63713C,
+0xFF7F9059,
+0xFF6F7E45,
+0xFF616E38,
+0xFF505A25,
+0xFF535D28,
+0xFF59632E,
+0xFF55622A,
+0xFF424F19,
+0xFF384210,
+0xFF58602F,
+0xFF8F9360,
+0xFF5F622D,
+0xFF2F3917,
+0xFF404A27,
+0xFF384220,
+0xFF363D1E,
+0xFF20250F,
+0xFF252817,
+0xFF1C1F0C,
+0xFF343722,
+0xFF21250E,
+0xFF2B3019,
+0xFF30351E,
+0xFF242A0E,
+0xFF4E5533,
+0xFF555D38,
+0xFF5C643F,
+0xFF68704B,
+0xFF2D3510,
+0xFF3C441D,
+0xFF353D16,
+0xFF656D48,
+0xFF2E3611,
+0xFF575F3A,
+0xFF6E7553,
+0xFF303614,
+0xFF353A1A,
+0xFF535838,
+0xFF26290C,
+0xFF29290D,
+0xFF343219,
+0xFF312F16,
+0xFF3B3620,
+0xFF473F28,
+0xFF3E2C14,
+0xFF5A442C,
+0xFF3C2C13,
+0xFF60543C,
+0xFF3B331E,
+0xFF342E16,
+0xFF403C1F,
+0xFF3F3E1F,
+0xFF27270D,
+0xFF2B2D15,
+0xFF464A2F,
+0xFF626749,
+0xFF393E20,
+0xFF676A4B,
+0xFF64663F,
+0xFF62643D,
+0xFF363C1A,
+0xFF2F3416,
+0xFF2F3217,
+0xFF222206,
+0xFF2C2D0E,
+0xFF696849,
+0xFF2D2C0D,
+0xFF6E6F4D,
+0xFF555934,
+0xFF5E633B,
+0xFF585F35,
+0xFF697047,
+0xFF2A2E0B,
+0xFF1C1D00,
+0xFF767757,
+0xFF838361,
+0xFF50502A,
+0xFF3A3B11,
+0xFF95986B,
+0xFF9B9E73,
+0xFF90906C,
+0xFF5C5038,
+0xFFB18F86,
+0xFF643E3D,
+0xFF45312A,
+0xFF3B302C,
+0xFF2A232B,
+0xFF241E2C,
+0xFF332733,
+0xFF2A2126,
+0xFF454442,
+0xFF1E1F19,
+0xFF35322B,
+0xFF0C0A00,
+0xFF191B06,
+0xFF55583D,
+0xFF5D593C,
+0xFF4D482A,
+0xFF454426,
+0xFF5C5C40,
+0xFF8F8F75,
+0xFF3B3C1C,
+0xFF101200,
+0xFF737A47,
+0xFF6E7951,
+0xFF303A1F,
+0xFF1B2113,
+0xFF5B5D5A,
+0xFF5D6164,
+0xFF191D1E,
+0xFF6C6D65,
+0xFF1E1D0B,
+0xFF7B7960,
+0xFF3F3E20,
+0xFF343515,
+0xFF656647,
+0xFF171700,
+0xFF4A4734,
+0xFF0A0500,
+0xFF5D5842,
+0xFF868664,
+0xFF595F33,
+0xFF78834B,
+0xFF444D1E,
+0xFF4C4E38,
+0xFF1C1A0D,
+0xFF1F1A06,
+0xFF4D4A2B,
+0xFFA29F76,
+0xFFB7B686,
+0xFF7A7D50,
+0xFF161B00,
+0xFF3A3E1D,
+0xFF494C2F,
+0xFF67664A,
+0xFFA9A987,
+0xFF979668,
+0xFFDBDEA9,
+0xFF7B824C,
+0xFF7C854C,
+0xFF717940,
+0xFF99A26B,
+0xFFA3AD79,
+0xFFC5D29D,
+0xFF75864F,
+0xFF8A9E63,
+0xFF82965B,
+0xFF94A66C,
+0xFF96A36E,
+0xFF7F8955,
+0xFF656C39,
+0xFF8E9464,
+0xFF32380C,
+0xFF585E32,
+0xFF676F3E,
+0xFF99A06A,
+0xFFBDBE84,
+0xFF818248,
+0xFFD6DFAA,
+0xFF5E6B36,
+0xFF5C6B34,
+0xFF5B6832,
+0xFF6E7541,
+0xFFD4D6A4,
+0xFF5D5F30,
+0xFF777A4B,
+0xFF9DA572,
+0xFF414B16,
+0xFF656F3B,
+0xFF707845,
+0xFF818457,
+0xFF5D5F37,
+0xFF737550,
+0xFF202101,
+0xFF141700,
+0xFF5B5C3C,
+0xFF302B0D,
+0xFF484220,
+0xFF8A875E,
+0xFF959363,
+0xFF6C6B35,
+0xFF626129,
+0xFF89884F,
+0xFF9C9F66,
+0xFF697239,
+0xFF4A571F,
+0xFF737D48,
+0xFFBBC590,
+0xFF5C6A2F,
+0xFF879759,
+0xFF92A264,
+0xFF455419,
+0xFF3D4A14,
+0xFFAFBC84,
+0xFF839153,
+0xFF82934F,
+0xFF82934D,
+0xFF7D8E4A,
+0xFF819454,
+0xFF7B8E4E,
+0xFF465A15,
+0xFFA3B971,
+0xFF7A8E49,
+0xFF718442,
+0xFF738344,
+0xFF98A867,
+0xFF899952,
+0xFF728536,
+0xFF6F8634,
+0xFF96AE5A,
+0xFF9DB05E,
+0xFFA0B362,
+0xFF91A75C,
+0xFF62782F,
+0xFF4D5F15,
+0xFFABBB72,
+0xFF8B9D53,
+0xFF839549,
+0xFF616F22,
+0xFF6E7C31,
+0xFF8B9B54,
+0xFF7D8949,
+0xFF696E38,
+0xFF92905F,
+0xFF6A6732,
+0xFF868350,
+0xFF504F1F,
+0xFF919767,
+0xFF3D4713,
+0xFFA2AE7C,
+0xFF667242,
+0xFF485220,
+0xFF6C733F,
+0xFF747B47,
+0xFF7E8454,
+0xFF8A8E5C,
+0xFFAFB376,
+0xFF848949,
+0xFFB3B67F,
+0xFF868A58,
+0xFF7B8354,
+0xFF575F30,
+0xFF747846,
+0xFFA3A774,
+0xFF666F38,
+0xFF8B945D,
+0xFF7A7C4D,
+0xFF97986C,
+0xFF686E40,
+0xFF545C2B,
+0xFF5C652E,
+0xFF676F36,
+0xFF4B4F1C,
+0xFF787C49,
+0xFF767E45,
+0xFF778144,
+0xFF8D9959,
+0xFF636F2D,
+0xFF829052,
+0xFF8B9A59,
+0xFFABB873,
+0xFF54601E,
+0xFF7B8549,
+0xFF525B26,
+0xFF969E6D,
+0xFF535B2C,
+0xFF7B8354,
+0xFF666D41,
+0xFF6A7147,
+0xFF898F63,
+0xFF5F6034,
+0xFF646539,
+0xFF60653C,
+0xFF5F6738,
+0xFF5C6129,
+0xFF81844B,
+0xFF7E804E,
+0xFF7B7F4C,
+0xFF646E31,
+0xFF7D874A,
+0xFF757745,
+0xFF4A4C1D,
+0xFF484A19,
+0xFFB4B886,
+0xFF767847,
+0xFF4F5525,
+0xFF909C6C,
+0xFFAABA89,
+0xFF51622E,
+0xFF475520,
+0xFF4E5B26,
+0xFF5D6732,
+0xFF555E25,
+0xFF545C21,
+0xFF53571C,
+0xFFA8A96F,
+0xFF94915E,
+0xFF7C7A49,
+0xFF505220,
+0xFF606733,
+0xFF97A067,
+0xFF858E57,
+0xFF787B4C,
+0xFF66693C,
+0xFF7D8451,
+0xFF6A723F,
+0xFF58622E,
+0xFF878F60,
+0xFF909167,
+0xFF505127,
+0xFF5F6130,
+0xFF5E652F,
+0xFF929D65,
+0xFF869157,
+0xFF707741,
+0xFF797E46,
+0xFF656A30,
+0xFF586226,
+0xFF7C8951,
+0xFF52612A,
+0xFF6D7F43,
+0xFF5E6E30,
+0xFF606E31,
+0xFF5A652B,
+0xFF545F27,
+0xFF58652F,
+0xFF4F5E27,
+0xFF3C4A15,
+0xFF444D1E,
+0xFF343C0B,
+0xFF686D35,
+0xFF666930,
+0xFF4B5532,
+0xFF222C09,
+0xFF29300F,
+0xFF2D3118,
+0xFF323524,
+0xFF414135,
+0xFF262719,
+0xFF1C1F0C,
+0xFF1B200A,
+0xFF0A1200,
+0xFF1F280D,
+0xFF3C4526,
+0xFF525D35,
+0xFF6D754C,
+0xFF373F1A,
+0xFF727A55,
+0xFF727D53,
+0xFF586339,
+0xFF2C370D,
+0xFF404B23,
+0xFF3D4520,
+0xFF666D4B,
+0xFF747959,
+0xFF313417,
+0xFF34341A,
+0xFF414127,
+0xFF3E3C25,
+0xFF3F3D28,
+0xFF3B3623,
+0xFF625D4A,
+0xFF403927,
+0xFF312413,
+0xFF5C4631,
+0xFF503A23,
+0xFF493922,
+0xFF2A1F09,
+0xFF35301D,
+0xFF363320,
+0xFF59543E,
+0xFF403B25,
+0xFF24210E,
+0xFF31301E,
+0xFF3F412C,
+0xFF323520,
+0xFF2F321D,
+0xFF373921,
+0xFF605F40,
+0xFF4B4C2A,
+0xFF3D4222,
+0xFF3F4529,
+0xFF42442E,
+0xFF35351D,
+0xFF2F2B0E,
+0xFF464324,
+0xFF5E5B3C,
+0xFF636243,
+0xFF282C07,
+0xFF121900,
+0xFF576031,
+0xFF323B0E,
+0xFF2F3511,
+0xFF212705,
+0xFF303111,
+0xFF494829,
+0xFF665F42,
+0xFF454020,
+0xFF444B22,
+0xFF9BA276,
+0xFFA19E73,
+0xFF6B5033,
+0xFFC98A85,
+0xFFC67E82,
+0xFFBD8A86,
+0xFF68473E,
+0xFF322119,
+0xFF3C312B,
+0xFF53413F,
+0xFF564742,
+0xFF3B372B,
+0xFF191A0C,
+0xFF4B473B,
+0xFF25200D,
+0xFF5E5E3C,
+0xFF676840,
+0xFFA6A27D,
+0xFF383313,
+0xFF585437,
+0xFF67664A,
+0xFF858666,
+0xFF1E2000,
+0xFF6E6F45,
+0xFF676944,
+0xFF323625,
+0xFF2D3329,
+0xFF40433C,
+0xFF979A91,
+0xFF40463A,
+0xFF3C4031,
+0xFF939580,
+0xFF6D6B56,
+0xFF231E0B,
+0xFF38311E,
+0xFF99957A,
+0xFF4F4F2D,
+0xFF949470,
+0xFF696945,
+0xFF070400,
+0xFF5B5835,
+0xFF636236,
+0xFF7A7C4D,
+0xFF83895B,
+0xFF4D512C,
+0xFF51503C,
+0xFF5A5446,
+0xFF28220C,
+0xFF6B6646,
+0xFFAAA677,
+0xFFA6A471,
+0xFF686A3B,
+0xFF484A22,
+0xFF3A3B19,
+0xFF757455,
+0xFF908C6F,
+0xFF474421,
+0xFF918F5C,
+0xFF949559,
+0xFFA0A668,
+0xFF585E20,
+0xFF91945B,
+0xFF757A44,
+0xFF969C6C,
+0xFF6E7846,
+0xFF485720,
+0xFF9AAC70,
+0xFFA4B67A,
+0xFF8FA165,
+0xFF9FAD72,
+0xFF69743A,
+0xFF99A26D,
+0xFF7D8353,
+0xFF464C20,
+0xFF5F6235,
+0xFF585C2A,
+0xFFB4B780,
+0xFF9E9E60,
+0xFF818344,
+0xFF6C753E,
+0xFFCCD9A4,
+0xFF7D8C53,
+0xFF7E8951,
+0xFF747846,
+0xFFCBCA9A,
+0xFF7A794B,
+0xFFC8CA99,
+0xFFA9B279,
+0xFF6C773D,
+0xFF647139,
+0xFF606835,
+0xFF737647,
+0xFF95966A,
+0xFF6B6D45,
+0xFF40451D,
+0xFF575C34,
+0xFF7F7F59,
+0xFF6D6743,
+0xFF5B532E,
+0xFFA29A73,
+0xFFA9A276,
+0xFF5A5724,
+0xFF5D5A25,
+0xFFCCC992,
+0xFFACAD73,
+0xFF969E62,
+0xFF4C571B,
+0xFF5A652D,
+0xFF8F9A62,
+0xFF657034,
+0xFF6B793B,
+0xFF808E51,
+0xFF57652A,
+0xFF9FAC74,
+0xFF5B692C,
+0xFFC0D18D,
+0xFF708238,
+0xFF586A20,
+0xFFA5B971,
+0xFF9AAD6D,
+0xFF5F7232,
+0xFF718540,
+0xFF81954E,
+0xFF73843E,
+0xFF96A760,
+0xFF9EB066,
+0xFF98A959,
+0xFF71802B,
+0xFF90A34A,
+0xFF768C37,
+0xFF89A14B,
+0xFFBFD37E,
+0xFFB8CE7C,
+0xFF6B8339,
+0xFF627A30,
+0xFF90A558,
+0xFFA6B86C,
+0xFF80914A,
+0xFF5D6E2A,
+0xFF4F5E1D,
+0xFF576625,
+0xFF7D904E,
+0xFF819150,
+0xFF90985D,
+0xFF8B8B55,
+0xFF888250,
+0xFF979363,
+0xFF878755,
+0xFF8D9460,
+0xFF637038,
+0xFFA3B279,
+0xFF7D8C51,
+0xFFA5B577,
+0xFFA9B478,
+0xFF99A366,
+0xFF9DA76A,
+0xFFA1A96D,
+0xFFA3A868,
+0xFF929357,
+0xFFB4B47E,
+0xFF959765,
+0xFF666E3B,
+0xFF9CA471,
+0xFF929963,
+0xFF727943,
+0xFF707B43,
+0xFF515C24,
+0xFF828653,
+0xFF737744,
+0xFFA7B07B,
+0xFF69743A,
+0xFF707B3F,
+0xFF667033,
+0xFF6B7539,
+0xFF616B2E,
+0xFF7A8543,
+0xFF839048,
+0xFF69772A,
+0xFF9AAB5D,
+0xFF63732C,
+0xFF5E6E27,
+0xFF99A75C,
+0xFF818E48,
+0xFF79844A,
+0xFF7F8957,
+0xFF80895A,
+0xFF5E673A,
+0xFF343D10,
+0xFF5E673C,
+0xFF697247,
+0xFF4E5529,
+0xFF737745,
+0xFF626633,
+0xFF454D1E,
+0xFF636B3A,
+0xFF515822,
+0xFF4E531D,
+0xFF595C2D,
+0xFF7A7E4C,
+0xFF798344,
+0xFF8F9857,
+0xFF72753E,
+0xFF3D3F0D,
+0xFF626433,
+0xFF6A6E3C,
+0xFF797B4A,
+0xFF242A00,
+0xFFB6C294,
+0xFF3D4B1A,
+0xFF717F4A,
+0xFF4B5A23,
+0xFF414E19,
+0xFF757F4B,
+0xFF57612C,
+0xFF838C53,
+0xFF8D9357,
+0xFF7E8247,
+0xFF696734,
+0xFF5E5E2A,
+0xFF72773F,
+0xFF596327,
+0xFF6C7A3D,
+0xFF768147,
+0xFF656B3B,
+0xFF7D8355,
+0xFF606934,
+0xFF414A13,
+0xFF616B37,
+0xFF606837,
+0xFF3A4014,
+0xFF6A7042,
+0xFF686F3B,
+0xFF525D25,
+0xFF5E6B33,
+0xFF616E36,
+0xFF5F682F,
+0xFF7C8147,
+0xFF5D6327,
+0xFF525A1E,
+0xFF586329,
+0xFF627136,
+0xFF809353,
+0xFF627231,
+0xFF788648,
+0xFF5F6D30,
+0xFF6A7741,
+0xFF424F1A,
+0xFF5E6C39,
+0xFF586635,
+0xFF596235,
+0xFF4A5221,
+0xFF747941,
+0xFF75793E,
+0xFF656D48,
+0xFF353C1A,
+0xFF373C1E,
+0xFF2F331A,
+0xFF424333,
+0xFF2E2F21,
+0xFF2C2D1F,
+0xFF3D402F,
+0xFF414630,
+0xFF6F785D,
+0xFF4C5739,
+0xFF4A5533,
+0xFF69744C,
+0xFF7C875D,
+0xFF1F2700,
+0xFF939B72,
+0xFF7C895D,
+0xFF3D4D20,
+0xFF566337,
+0xFF646F45,
+0xFF454F2A,
+0xFF6F7654,
+0xFF1D2204,
+0xFF3C3E26,
+0xFF44432E,
+0xFF413E2B,
+0xFF474431,
+0xFF332D1D,
+0xFF453F2F,
+0xFF312B1B,
+0xFF4B4434,
+0xFF342917,
+0xFF5D4B35,
+0xFF7A6852,
+0xFF60553F,
+0xFF47412B,
+0xFF33301F,
+0xFF413E2D,
+0xFF494431,
+0xFF3B3422,
+0xFF2F271A,
+0xFF534D41,
+0xFF0A0600,
+0xFF141203,
+0xFF1C1D0D,
+0xFF34331F,
+0xFF5A593D,
+0xFF6F7050,
+0xFF464D2C,
+0xFF555B3F,
+0xFF4E503A,
+0xFF6F6D58,
+0xFF736D53,
+0xFF7C7759,
+0xFF7A7558,
+0xFF787758,
+0xFF585C37,
+0xFF4B5427,
+0xFF606C3A,
+0xFF3B4918,
+0xFF37421A,
+0xFF1E2503,
+0xFF36391A,
+0xFF4C4B2D,
+0xFF211A00,
+0xFF3A3518,
+0xFF656B49,
+0xFF6A7148,
+0xFF7E7D51,
+0xFF735C3A,
+0xFFB07567,
+0xFFA15C55,
+0xFF713D2F,
+0xFF866651,
+0xFF69593F,
+0xFF453E22,
+0xFF392A17,
+0xFF564936,
+0xFF6F6B52,
+0xFF605E45,
+0xFF37321C,
+0xFF393417,
+0xFF75734C,
+0xFFABAA7C,
+0xFF7E7A54,
+0xFF3F3917,
+0xFF625D3F,
+0xFF5C583B,
+0xFF50502E,
+0xFF42421C,
+0xFF63643C,
+0xFF505131,
+0xFF585A4C,
+0xFF30332A,
+0xFF797D6C,
+0xFF4A4F38,
+0xFF576043,
+0xFF8E9574,
+0xFF484929,
+0xFF514D30,
+0xFF3C3523,
+0xFF776F5C,
+0xFF8E896C,
+0xFF73714B,
+0xFF6A6B41,
+0xFF8F9064,
+0xFF67653E,
+0xFF626037,
+0xFF3D3C0C,
+0xFF757444,
+0xFF494B23,
+0xFF6C6D4D,
+0xFF292410,
+0xFF0C0500,
+0xFF39311A,
+0xFFA29C7A,
+0xFF777343,
+0xFF72713B,
+0xFF777648,
+0xFF6D6E44,
+0xFF80805A,
+0xFF4A4724,
+0xFF858060,
+0xFF555229,
+0xFF96955D,
+0xFFACAE6D,
+0xFF9BA05D,
+0xFF9DA260,
+0xFF656529,
+0xFF51511B,
+0xFF4A5020,
+0xFF515B29,
+0xFF707F46,
+0xFF899B5F,
+0xFF738249,
+0xFF97A56A,
+0xFF96A165,
+0xFF707A3E,
+0xFFACB580,
+0xFF8D9562,
+0xFF818757,
+0xFF414415,
+0xFFA9AB79,
+0xFFB6B77E,
+0xFF959555,
+0xFF7B7D3E,
+0xFF374009,
+0xFFD4E1AC,
+0xFF8B9862,
+0xFF414B16,
+0xFF888C5A,
+0xFFB9B88A,
+0xFFC1C092,
+0xFF929463,
+0xFFA3AB72,
+0xFFA3AE74,
+0xFF56602B,
+0xFF5D6532,
+0xFFC1C593,
+0xFF616334,
+0xFF737949,
+0xFF767C4E,
+0xFF6C7244,
+0xFF46491C,
+0xFF5A552D,
+0xFF544C25,
+0xFF1C1500,
+0xFF6F683C,
+0xFF989464,
+0xFF96935E,
+0xFF85824B,
+0xFF9A9960,
+0xFF6E7738,
+0xFF798547,
+0xFF6F7A40,
+0xFF707B41,
+0xFF586225,
+0xFF7C8848,
+0xFF6F7B3D,
+0xFF9AA86B,
+0xFF4D5B20,
+0xFFB2C083,
+0xFF899A53,
+0xFF889A4E,
+0xFF5B7021,
+0xFF6C8136,
+0xFFAABD7B,
+0xFF5E6E30,
+0xFF3F4F0E,
+0xFF748340,
+0xFF7A8944,
+0xFF97A75E,
+0xFF98A657,
+0xFF859441,
+0xFF83933A,
+0xFFBBCE75,
+0xFF576D1A,
+0xFF8DA351,
+0xFF8FA251,
+0xFF7E9344,
+0xFF576E26,
+0xFFA8C076,
+0xFF879C4D,
+0xFF6F8233,
+0xFF7B8F48,
+0xFF5A6D2D,
+0xFF6F7E45,
+0xFF647338,
+0xFF607532,
+0xFF6C803B,
+0xFF76813F,
+0xFF808449,
+0xFF716E39,
+0xFF83804D,
+0xFF727240,
+0xFF767D49,
+0xFF414F14,
+0xFF364608,
+0xFF3F4F10,
+0xFF5F6F2E,
+0xFF4B5717,
+0xFF859151,
+0xFF76813F,
+0xFF7D8643,
+0xFFABB070,
+0xFF8A8B51,
+0xFF80804E,
+0xFF7A7C4B,
+0xFF919865,
+0xFFABB47D,
+0xFF7A8247,
+0xFF81894E,
+0xFF515C22,
+0xFF838E56,
+0xFF5F6633,
+0xFF929965,
+0xFF717A43,
+0xFF6B763A,
+0xFF98A466,
+0xFF6F7B3D,
+0xFFA7B175,
+0xFF909A5B,
+0xFF85924D,
+0xFF77853A,
+0xFF718331,
+0xFFB7C977,
+0xFF637426,
+0xFF75853A,
+0xFF8A974F,
+0xFF65722D,
+0xFF5D682E,
+0xFFA7B17D,
+0xFF646E3C,
+0xFF485122,
+0xFF283404,
+0xFF566234,
+0xFF333A11,
+0xFF454B1F,
+0xFF828654,
+0xFF555C26,
+0xFF555D2A,
+0xFF555D2C,
+0xFF656D3C,
+0xFF3E4414,
+0xFF52582A,
+0xFF515825,
+0xFF8A9455,
+0xFF7A8340,
+0xFF878D51,
+0xFF7F844C,
+0xFF676B38,
+0xFF5B5F2D,
+0xFF5D5F30,
+0xFF4F5225,
+0xFFB8C194,
+0xFF7B8757,
+0xFF76834D,
+0xFF727F49,
+0xFF4A5420,
+0xFF545E2C,
+0xFF57612D,
+0xFF757E49,
+0xFF757D44,
+0xFF7E8349,
+0xFF979763,
+0xFF656833,
+0xFF6F773B,
+0xFF8D9959,
+0xFF667534,
+0xFF728043,
+0xFF5A622F,
+0xFF8E9562,
+0xFF79804A,
+0xFF687138,
+0xFF727B46,
+0xFF676F3C,
+0xFF474E22,
+0xFF6D7546,
+0xFF758048,
+0xFF627035,
+0xFF66753C,
+0xFF6D7A42,
+0xFF4C551C,
+0xFF889057,
+0xFF65682F,
+0xFF6C7137,
+0xFF687138,
+0xFF69773C,
+0xFF7E8E4D,
+0xFF687B39,
+0xFF6B793C,
+0xFF515E26,
+0xFF43501B,
+0xFF65713F,
+0xFF4F5D2A,
+0xFF4E5C2B,
+0xFF677345,
+0xFF4A5223,
+0xFF6E733D,
+0xFF5E6128,
+0xFF444A28,
+0xFF474C2C,
+0xFF303419,
+0xFF2A2E17,
+0xFF3F432C,
+0xFF262914,
+0xFF343724,
+0xFF323723,
+0xFF596149,
+0xFF4D5639,
+0xFF4B5634,
+0xFF424E28,
+0xFF444E29,
+0xFF48532B,
+0xFF3D481E,
+0xFF879468,
+0xFF768858,
+0xFF415522,
+0xFF95A679,
+0xFF36451A,
+0xFF3C4822,
+0xFF273011,
+0xFF1C2208,
+0xFF161904,
+0xFF3F402E,
+0xFF363425,
+0xFF3B392A,
+0xFF43402F,
+0xFF403D2C,
+0xFF2B2815,
+0xFF373622,
+0xFF323019,
+0xFF383218,
+0xFF5E583E,
+0xFF2A280F,
+0xFF494833,
+0xFF565541,
+0xFF5F5C4B,
+0xFF4B4432,
+0xFF6A6150,
+0xFF494031,
+0xFF291F15,
+0xFF120A00,
+0xFF1E180C,
+0xFF3A362A,
+0xFF444130,
+0xFF524D37,
+0xFF2F2F13,
+0xFF5F6645,
+0xFF171E00,
+0xFF30321A,
+0xFF443F29,
+0xFF3C351B,
+0xFF514A2E,
+0xFF605B3D,
+0xFF575735,
+0xFF555A32,
+0xFF556133,
+0xFF869461,
+0xFF5D6D3C,
+0xFF424E26,
+0xFF394320,
+0xFF171C00,
+0xFF393C1D,
+0xFF7B7A5B,
+0xFF69684A,
+0xFF7F7F63,
+0xFF676A4B,
+0xFF4B5229,
+0xFF56542B,
+0xFF94805D,
+0xFF866C4B,
+0xFF5B4722,
+0xFF90845C,
+0xFF5D5A2F,
+0xFF535428,
+0xFF58562D,
+0xFFC0BC96,
+0xFF9E9973,
+0xFF4A4420,
+0xFF6B6742,
+0xFF908C66,
+0xFF59572E,
+0xFF4C4B1F,
+0xFF88845F,
+0xFF433D1B,
+0xFF5B5734,
+0xFF918E6B,
+0xFF514E2B,
+0xFF7A7852,
+0xFF626039,
+0xFF595935,
+0xFF8F9277,
+0xFF696D52,
+0xFF5E653B,
+0xFFA9B182,
+0xFF879365,
+0xFF5D6639,
+0xFF494C1F,
+0xFF828059,
+0xFF554E32,
+0xFF7D765A,
+0xFF9B9772,
+0xFF87855C,
+0xFFB0B283,
+0xFF414216,
+0xFF45431C,
+0xFF5B5930,
+0xFF555225,
+0xFF77764A,
+0xFF595935,
+0xFF434224,
+0xFF28220A,
+0xFF5C543D,
+0xFF655E41,
+0xFFB8B38D,
+0xFF545020,
+0xFF797641,
+0xFF858353,
+0xFF565529,
+0xFF54522B,
+0xFF5B5932,
+0xFF8B8761,
+0xFF848252,
+0xFFA7A96A,
+0xFF535611,
+0xFFADB36D,
+0xFF808240,
+0xFF6D6B2E,
+0xFF76753F,
+0xFF626536,
+0xFF5E6836,
+0xFF5D6A32,
+0xFF58672C,
+0xFF515B27,
+0xFFBEC792,
+0xFF5F672E,
+0xFF6D753C,
+0xFF646D36,
+0xFF9BA46F,
+0xFF8E9663,
+0xFF5E6531,
+0xFFB7BA83,
+0xFF84854B,
+0xFF9C9C5E,
+0xFF8D8E52,
+0xFF686F3B,
+0xFF646E3C,
+0xFFD0DAA8,
+0xFF4C5624,
+0xFF717445,
+0xFF636536,
+0xFFC8CA9B,
+0xFFA0A273,
+0xFF6C7340,
+0xFF7F8754,
+0xFF8B9362,
+0xFF7A8251,
+0xFF898D5B,
+0xFF4E521F,
+0xFF767D49,
+0xFF6C7540,
+0xFF7E8752,
+0xFF616835,
+0xFFC6C599,
+0xFF59542C,
+0xFF646134,
+0xFF949262,
+0xFF7D7B4A,
+0xFF777542,
+0xFF8A8953,
+0xFF75763D,
+0xFF606A2D,
+0xFF627032,
+0xFF626D31,
+0xFF798347,
+0xFF7A8246,
+0xFF838C4D,
+0xFF4B5516,
+0xFF7D894B,
+0xFFB4BF85,
+0xFF657336,
+0xFF7D8E47,
+0xFF86994A,
+0xFF5F7221,
+0xFF9AAC60,
+0xFF59692A,
+0xFF9EAC71,
+0xFF637136,
+0xFF5F6B2D,
+0xFF95A25D,
+0xFFAAB76F,
+0xFF808C40,
+0xFF93A051,
+0xFF677424,
+0xFF889647,
+0xFF65772D,
+0xFF41520C,
+0xFF82934C,
+0xFF52661E,
+0xFF8FA45F,
+0xFF41570F,
+0xFF869B4E,
+0xFF6A7F32,
+0xFF5B6F2A,
+0xFF758749,
+0xFF53622B,
+0xFF65773D,
+0xFF9AB169,
+0xFF758D41,
+0xFF7A8A41,
+0xFF3F4805,
+0xFF7F8044,
+0xFF6A6A34,
+0xFF676B38,
+0xFF353E09,
+0xFF616C30,
+0xFF7A8948,
+0xFF4A581A,
+0xFF798547,
+0xFF6F7B3D,
+0xFF818B4C,
+0xFF697533,
+0xFF8F9857,
+0xFF8F9356,
+0xFF84834D,
+0xFF676437,
+0xFF5B5C32,
+0xFF808656,
+0xFF88915A,
+0xFF868F50,
+0xFF77803F,
+0xFF6E783C,
+0xFF767F4A,
+0xFF6C6F40,
+0xFF696C3F,
+0xFF7E8653,
+0xFF49541C,
+0xFFA4AE72,
+0xFF6C763A,
+0xFF7C854C,
+0xFF9BA569,
+0xFF525E1E,
+0xFF7F8C46,
+0xFF5E6E23,
+0xFF90A151,
+0xFF909F4E,
+0xFFA5B366,
+0xFF5D6826,
+0xFF3B4509,
+0xFF8D975B,
+0xFF919A61,
+0xFF414B16,
+0xFF3F4914,
+0xFF7E8B55,
+0xFF525C2A,
+0xFF3E431B,
+0xFF4D4F27,
+0xFF747647,
+0xFF464A17,
+0xFF4F5622,
+0xFF495120,
+0xFF636A40,
+0xFF777E54,
+0xFF606839,
+0xFF414A15,
+0xFF566023,
+0xFF65702C,
+0xFFA5AE6D,
+0xFF7D8748,
+0xFF636C35,
+0xFF4F5724,
+0xFF6A6B3F,
+0xFF8E8F65,
+0xFF757C50,
+0xFF9AA374,
+0xFF58622D,
+0xFF616A35,
+0xFF646C39,
+0xFF515928,
+0xFF50592A,
+0xFF727A49,
+0xFF909763,
+0xFF797D4A,
+0xFFA7A977,
+0xFF6F743C,
+0xFF6F793A,
+0xFF99A661,
+0xFF54631E,
+0xFF707C3A,
+0xFF727943,
+0xFF929761,
+0xFF81864C,
+0xFF767C40,
+0xFF434B12,
+0xFF67703B,
+0xFF687142,
+0xFF7B8755,
+0xFF6A7940,
+0xFF4E5D22,
+0xFF617339,
+0xFF78874E,
+0xFF5B662C,
+0xFF737B42,
+0xFF4C4F1A,
+0xFF767B45,
+0xFF626B34,
+0xFF69773C,
+0xFF718142,
+0xFF748747,
+0xFF606D37,
+0xFF596533,
+0xFF5B6739,
+0xFF586436,
+0xFF5E6C39,
+0xFF52602D,
+0xFF4C582A,
+0xFF4A5223,
+0xFF636534,
+0xFF5C5C2A,
+0xFF46492A,
+0xFF484B2E,
+0xFF3F432A,
+0xFF272B12,
+0xFF22280C,
+0xFF3B4125,
+0xFF393F25,
+0xFF323A22,
+0xFF485136,
+0xFF363F20,
+0xFF414B26,
+0xFF4D5732,
+0xFF252F0C,
+0xFF1E2803,
+0xFF59643A,
+0xFF8B9B6C,
+0xFF6C7E4A,
+0xFF8A9E69,
+0xFF6C7E4E,
+0xFF2E3D12,
+0xFF384420,
+0xFF1A2306,
+0xFF1E230D,
+0xFF262916,
+0xFF1C1E10,
+0xFF232416,
+0xFF2E2F1F,
+0xFF20210F,
+0xFF272914,
+0xFF22240E,
+0xFF1E2008,
+0xFF3F4328,
+0xFF2E3112,
+0xFF303314,
+0xFF55583B,
+0xFF4B4B31,
+0xFF45432C,
+0xFF443F29,
+0xFF645E46,
+0xFF433B26,
+0xFF342C19,
+0xFF312A18,
+0xFF3C3427,
+0xFF302A1C,
+0xFF514B3D,
+0xFF43402D,
+0xFF4F4A34,
+0xFF4F5031,
+0xFF717856,
+0xFF161D00,
+0xFF272809,
+0xFF454126,
+0xFF514A2E,
+0xFF463F22,
+0xFF373214,
+0xFF3B3B17,
+0xFF5A6137,
+0xFF616D3F,
+0xFF93A372,
+0xFF536535,
+0xFF5C6D41,
+0xFF44502A,
+0xFF1D2403,
+0xFF282D0D,
+0xFF3D3E1C,
+0xFF6D6E4C,
+0xFF2F2E12,
+0xFF4C4F32,
+0xFF464E27,
+0xFF444D20,
+0xFF848355,
+0xFF7A7848,
+0xFF696838,
+0xFF4D4F1E,
+0xFF838553,
+0xFF8F9360,
+0xFF737544,
+0xFFD8D7A7,
+0xFF635F32,
+0xFF7D764C,
+0xFFA6A37A,
+0xFF817F56,
+0xFF3E3C13,
+0xFF53512A,
+0xFF615D38,
+0xFF524E2B,
+0xFF9F9B78,
+0xFFACA883,
+0xFF312D08,
+0xFF797750,
+0xFF59582C,
+0xFF6B6940,
+0xFF3F3F1D,
+0xFF888A65,
+0xFFC4C896,
+0xFF9AA16D,
+0xFF677341,
+0xFF3E4A1A,
+0xFF565D2A,
+0xFF8D8C5E,
+0xFF87815D,
+0xFF5E5836,
+0xFF5F5D34,
+0xFF6F7044,
+0xFF3B3C10,
+0xFF57582E,
+0xFF32300A,
+0xFF5E5C36,
+0xFF7B784F,
+0xFF716F46,
+0xFF64613E,
+0xFF848162,
+0xFF6E694C,
+0xFF564F32,
+0xFF4C4624,
+0xFF817E55,
+0xFF5A5626,
+0xFF807E4B,
+0xFF858353,
+0xFF353205,
+0xFF79774E,
+0xFF68663D,
+0xFFB6B587,
+0xFFAAAA74,
+0xFF8C8E4D,
+0xFF959851,
+0xFFA4AA62,
+0xFFA6A866,
+0xFF8D8D4F,
+0xFF818249,
+0xFF353C09,
+0xFFA4B07E,
+0xFF39460E,
+0xFF6E7B43,
+0xFF262E00,
+0xFF848A5C,
+0xFF5B5F2C,
+0xFF7C834D,
+0xFF8C955E,
+0xFF949E69,
+0xFF848F57,
+0xFFA7B077,
+0xFF52571F,
+0xFF5C6025,
+0xFF4E4F13,
+0xFF606429,
+0xFF5B5F2C,
+0xFF626A39,
+0xFFC2CA9B,
+0xFF7E8657,
+0xFF9AA070,
+0xFF5B6131,
+0xFFCED1A2,
+0xFF7E8154,
+0xFF76794C,
+0xFF858B5F,
+0xFF6D7347,
+0xFF686E40,
+0xFFB6BD8A,
+0xFF747B45,
+0xFF8C935D,
+0xFF78814A,
+0xFF5E6730,
+0xFF818855,
+0xFF292A00,
+0xFF403F13,
+0xFF686836,
+0xFF585B26,
+0xFF797C45,
+0xFFB0B07A,
+0xFF858551,
+0xFF80834E,
+0xFF757F43,
+0xFF8B965A,
+0xFF707A3E,
+0xFF727A3F,
+0xFF757A40,
+0xFF868C50,
+0xFFA6AF70,
+0xFFBEC88B,
+0xFF5A632A,
+0xFF2B3600,
+0xFF596922,
+0xFF849748,
+0xFF9BAE5D,
+0xFF809246,
+0xFF7B894C,
+0xFF77814C,
+0xFF6A753D,
+0xFF848E52,
+0xFF8F9A58,
+0xFF66702B,
+0xFF9BA560,
+0xFF5F6924,
+0xFF4A540F,
+0xFF85904C,
+0xFF828E4E,
+0xFF384608,
+0xFF71803F,
+0xFF98A867,
+0xFF778B46,
+0xFF4C6019,
+0xFF677B33,
+0xFF687C34,
+0xFF9FB06C,
+0xFF3F4F10,
+0xFF56652C,
+0xFF223400,
+0xFF6C863C,
+0xFFA9C173,
+0xFF475811,
+0xFF64712C,
+0xFF7A8342,
+0xFF4B5016,
+0xFF49501D,
+0xFF808855,
+0xFFA5B074,
+0xFF3F4B0D,
+0xFF646D34,
+0xFF919A61,
+0xFF8F975B,
+0xFF778142,
+0xFF737F3F,
+0xFF737D40,
+0xFF777A43,
+0xFFA7A574,
+0xFF817E53,
+0xFF919064,
+0xFF7B7F4C,
+0xFF5D652A,
+0xFFABB171,
+0xFFB4BA7A,
+0xFF747C41,
+0xFF6E7541,
+0xFF717344,
+0xFF7D7F50,
+0xFF727946,
+0xFF929B66,
+0xFF39420B,
+0xFF666F38,
+0xFF5E662D,
+0xFF899357,
+0xFF798344,
+0xFF7D8947,
+0xFF374301,
+0xFF5C6923,
+0xFF8B9849,
+0xFF606C22,
+0xFF61692E,
+0xFF909761,
+0xFF98A065,
+0xFF60682D,
+0xFF5D662F,
+0xFF545E29,
+0xFF86905B,
+0xFF78804F,
+0xFF4B4D25,
+0xFF65663E,
+0xFF525425,
+0xFF747846,
+0xFF676E3A,
+0xFF4C5423,
+0xFF3F451F,
+0xFF585E38,
+0xFF7D8554,
+0xFF505922,
+0xFF555F23,
+0xFF717B3E,
+0xFF8D9758,
+0xFF9AA668,
+0xFF323D03,
+0xFF6A723F,
+0xFF807F53,
+0xFFA19F76,
+0xFF575D31,
+0xFF7B8354,
+0xFF9EA675,
+0xFF727848,
+0xFF686E3E,
+0xFF595F31,
+0xFF82895D,
+0xFF9EA778,
+0xFF686E3E,
+0xFF505724,
+0xFF787A48,
+0xFF5B6028,
+0xFF768043,
+0xFF7B8745,
+0xFF5D6A25,
+0xFF939D5E,
+0xFF585D27,
+0xFF777947,
+0xFF5C5D24,
+0xFF64682D,
+0xFF595C25,
+0xFF5A612D,
+0xFF6A7442,
+0xFF6E7C49,
+0xFF485A20,
+0xFF627438,
+0xFF4A5C22,
+0xFF728148,
+0xFF6B793E,
+0xFF6B743B,
+0xFF616630,
+0xFF535523,
+0xFF565F2A,
+0xFF89965E,
+0xFF6E7E40,
+0xFF697B3F,
+0xFF5D6937,
+0xFF5D693B,
+0xFF475227,
+0xFF4B582A,
+0xFF455320,
+0xFF4F5D28,
+0xFF626E3E,
+0xFF4D5526,
+0xFF66673B,
+0xFF6A693B,
+0xFF49492F,
+0xFF424228,
+0xFF2D2F17,
+0xFF30361A,
+0xFF37411E,
+0xFF616D47,
+0xFF7A8662,
+0xFF424C2A,
+0xFF273011,
+0xFF434A29,
+0xFF505833,
+0xFF3C441F,
+0xFF242E0B,
+0xFF2A3411,
+0xFF4A562E,
+0xFF5B6B3C,
+0xFF7B8D59,
+0xFF8A9C68,
+0xFF435525,
+0xFF3A4920,
+0xFF374220,
+0xFF384126,
+0xFF262B17,
+0xFF36382A,
+0xFF1F2114,
+0xFF222417,
+0xFF2F3123,
+0xFF262916,
+0xFF252910,
+0xFF383F20,
+0xFF3A4120,
+0xFF636D4A,
+0xFF88946E,
+0xFF49532E,
+0xFF3E4221,
+0xFF535234,
+0xFF4D4A2B,
+0xFF5D583A,
+0xFF696444,
+0xFF4B4626,
+0xFF494627,
+0xFF939274,
+0xFF4B4932,
+0xFF403B27,
+0xFF2D2814,
+0xFF4F4A34,
+0xFF5B5A3E,
+0xFF5E5F3F,
+0xFF969E79,
+0xFF3A421B,
+0xFF4B4D28,
+0xFF4B4827,
+0xFF484124,
+0xFF585134,
+0xFF403C19,
+0xFF44441E,
+0xFF52592F,
+0xFF455224,
+0xFF526336,
+0xFF243709,
+0xFF627347,
+0xFF4A5932,
+0xFF1D2705,
+0xFF353A1A,
+0xFF676942,
+0xFF71734C,
+0xFF323615,
+0xFF4B512F,
+0xFF6E744E,
+0xFF343910,
+0xFF55582B,
+0xFF606334,
+0xFF696F41,
+0xFF4E5426,
+0xFF6E6D3F,
+0xFF928F62,
+0xFF7D7C4E,
+0xFF828155,
+0xFF67623A,
+0xFF726D45,
+0xFFB6B48D,
+0xFF5F5D36,
+0xFF66643E,
+0xFF5A5832,
+0xFF54512E,
+0xFF625E3B,
+0xFFB4B08D,
+0xFF928C6A,
+0xFF2F2907,
+0xFF5E5B32,
+0xFF545221,
+0xFFB7B584,
+0xFF78754C,
+0xFFA4A07B,
+0xFF75734C,
+0xFF3B3D15,
+0xFF586037,
+0xFF283308,
+0xFF2E3406,
+0xFF949667,
+0xFF605D34,
+0xFF434017,
+0xFF4C4B1F,
+0xFF525329,
+0xFF34350D,
+0xFF222200,
+0xFF5D5A3B,
+0xFF83805F,
+0xFF47431E,
+0xFF46441D,
+0xFFC6C49D,
+0xFF626039,
+0xFF47431E,
+0xFF7F7B56,
+0xFF7A7650,
+0xFF302F03,
+0xFF6A673A,
+0xFF7D7B4A,
+0xFF878554,
+0xFFB4B282,
+0xFFACAB7F,
+0xFF434214,
+0xFF74743E,
+0xFF7A7E41,
+0xFF919653,
+0xFF9EA45C,
+0xFF959853,
+0xFFA3A866,
+0xFFBCC083,
+0xFF596126,
+0xFF7E8B56,
+0xFF9BA974,
+0xFF55642B,
+0xFF84915B,
+0xFF212800,
+0xFF646941,
+0xFF7A8052,
+0xFF323B06,
+0xFF656F3A,
+0xFF99A86F,
+0xFF404F14,
+0xFF7C8C4E,
+0xFF7F8A4E,
+0xFF6E783C,
+0xFF6B733A,
+0xFFA5AA72,
+0xFF595E28,
+0xFF535724,
+0xFF8F9263,
+0xFFB8BE90,
+0xFF434B1A,
+0xFF646C3B,
+0xFFB1B787,
+0xFF42481C,
+0xFF7A7A54,
+0xFF81815B,
+0xFF34350B,
+0xFF7E8152,
+0xFF535C27,
+0xFF757E47,
+0xFF868B55,
+0xFF9A9E6B,
+0xFF4E5722,
+0xFF737A47,
+0xFF5B5C30,
+0xFF666839,
+0xFF6C7137,
+0xFF6A7032,
+0xFF838949,
+0xFF5B6125,
+0xFFB9B985,
+0xFFCACC9B,
+0xFFA8AF79,
+0xFF818A53,
+0xFF848B55,
+0xFF555A24,
+0xFF8A8D54,
+0xFF90965A,
+0xFFD5DB9F,
+0xFF51591D,
+0xFF464F16,
+0xFF838E52,
+0xFF77843E,
+0xFF9FAF64,
+0xFF95A658,
+0xFF54641B,
+0xFF7C874D,
+0xFF87915D,
+0xFFB0B984,
+0xFF464E15,
+0xFF8B9455,
+0xFF959B5B,
+0xFF696F33,
+0xFF70783F,
+0xFF616930,
+0xFF616930,
+0xFF717A41,
+0xFF8F995D,
+0xFF96A165,
+0xFF3C4A0C,
+0xFF879655,
+0xFF73823F,
+0xFF687736,
+0xFF546423,
+0xFF8E9D5C,
+0xFF7B8A47,
+0xFFA1B06F,
+0xFF5C7029,
+0xFF698437,
+0xFF6F893F,
+0xFF697B3D,
+0xFF5D6C31,
+0xFF748040,
+0xFF455014,
+0xFF4C5526,
+0xFF6D7649,
+0xFF9CA56E,
+0xFF7D844E,
+0xFF7C7F52,
+0xFF595B2C,
+0xFF898F53,
+0xFF879051,
+0xFF677238,
+0xFF505924,
+0xFF656738,
+0xFF9B986B,
+0xFF454112,
+0xFFBABA84,
+0xFF62682A,
+0xFF989E5E,
+0xFFAAAF6F,
+0xFF82864B,
+0xFF373B08,
+0xFF5C602E,
+0xFF777745,
+0xFF73733F,
+0xFF868B53,
+0xFF959C66,
+0xFF42481C,
+0xFF63693B,
+0xFF878C52,
+0xFF889150,
+0xFFAEB776,
+0xFF5E6829,
+0xFF636D31,
+0xFF6B7539,
+0xFF646D2A,
+0xFF5C6524,
+0xFF646835,
+0xFF9A9D6E,
+0xFF7D824A,
+0xFF7A7F47,
+0xFF464A18,
+0xFF454B1D,
+0xFF393F13,
+0xFF4B5027,
+0xFF6A6B41,
+0xFF807E55,
+0xFF6B6C40,
+0xFF7F8253,
+0xFF474D1F,
+0xFF42481C,
+0xFF424822,
+0xFF3B4219,
+0xFF6A713E,
+0xFF727A41,
+0xFF787F4B,
+0xFF656C38,
+0xFF5C652E,
+0xFF707B43,
+0xFF5B662E,
+0xFF6A733E,
+0xFF6A693B,
+0xFF9C9B6F,
+0xFF4C4F22,
+0xFF696F43,
+0xFF555A31,
+0xFF74764E,
+0xFF61633B,
+0xFF85885D,
+0xFF737A4E,
+0xFF495225,
+0xFF52582A,
+0xFF212800,
+0xFF4B4D1B,
+0xFF888D55,
+0xFF656D34,
+0xFF6C763A,
+0xFF848C51,
+0xFF6C7139,
+0xFF666839,
+0xFF5D5C2E,
+0xFF898754,
+0xFF676630,
+0xFF767443,
+0xFF6D713F,
+0xFF697142,
+0xFF5E6C39,
+0xFF3F5117,
+0xFF5F7336,
+0xFF4B5D21,
+0xFF596B2D,
+0xFF9CAC6E,
+0xFF5C6A2D,
+0xFF5B602A,
+0xFF4E521F,
+0xFF6A733E,
+0xFF7F8C56,
+0xFF637239,
+0xFF51622B,
+0xFF414D1F,
+0xFF5E693E,
+0xFF626D42,
+0xFF72804F,
+0xFF55642D,
+0xFF53622B,
+0xFF64703E,
+0xFF4E5627,
+0xFF7A7D50,
+0xFFA8A97D,
+0xFF3B3922,
+0xFF37371F,
+0xFF33361B,
+0xFF363D1C,
+0xFF39451D,
+0xFF5F6E43,
+0xFF35441B,
+0xFF232F07,
+0xFF2A3411,
+0xFF323917,
+0xFF636947,
+0xFF353B19,
+0xFF363D1B,
+0xFF2C3613,
+0xFF434F29,
+0xFF4B5A2F,
+0xFF9CAC7B,
+0xFF758350,
+0xFF334014,
+0xFF535D38,
+0xFF121900,
+0xFF40452E,
+0xFF2F3221,
+0xFF2D2E20,
+0xFF29291D,
+0xFF4B4D3F,
+0xFF666757,
+0xFF3A3D28,
+0xFF404429,
+0xFF777E5D,
+0xFF6A724D,
+0xFF6F7954,
+0xFF37431D,
+0xFF424C27,
+0xFF333716,
+0xFF454223,
+0xFF5E5836,
+0xFF615B37,
+0xFF413F19,
+0xFF42421C,
+0xFF4F542B,
+0xFF343813,
+0xFF5B5E3F,
+0xFF77775B,
+0xFF4F4E32,
+0xFF49482C,
+0xFF474627,
+0xFF363715,
+0xFF394017,
+0xFF4C5329,
+0xFF5D6035,
+0xFF75734C,
+0xFF474222,
+0xFF5A5434,
+0xFF6D6A47,
+0xFF5B5D35,
+0xFF515A2F,
+0xFF4C592D,
+0xFF304218,
+0xFF1E3006,
+0xFF3F5026,
+0xFF687750,
+0xFF232D0B,
+0xFF6A6F4F,
+0xFF7C7C56,
+0xFF272800,
+0xFF3A4117,
+0xFF949F74,
+0xFF737A51,
+0xFF676E44,
+0xFF76794C,
+0xFF585E32,
+0xFF80875D,
+0xFF40451C,
+0xFF423F16,
+0xFF646136,
+0xFF898A60,
+0xFF8A8B61,
+0xFF615932,
+0xFF4D451E,
+0xFF282700,
+0xFF97986C,
+0xFF464519,
+0xFF6D6B42,
+0xFF514F28,
+0xFF4F4D27,
+0xFF413D1A,
+0xFF6C6644,
+0xFF615B3B,
+0xFF635E38,
+0xFF84814C,
+0xFF817E47,
+0xFFB2AE81,
+0xFF7A754F,
+0xFF6F6945,
+0xFF43431F,
+0xFF555D34,
+0xFF253005,
+0xFF454B1F,
+0xFF44471A,
+0xFF838556,
+0xFF5D5C2E,
+0xFF4A4B1F,
+0xFF54572C,
+0xFF262801,
+0xFF80805C,
+0xFF4E4B2A,
+0xFF413C1C,
+0xFF403C17,
+0xFF76744D,
+0xFF87885C,
+0xFF5A5B2F,
+0xFF75734A,
+0xFF403E15,
+0xFFB7B68A,
+0xFF636536,
+0xFFA7A678,
+0xFF929161,
+0xFF7D7D4B,
+0xFF696736,
+0xFF8C8B5F,
+0xFF4E4D1D,
+0xFF52561B,
+0xFF797E3C,
+0xFFA1A761,
+0xFF8A904A,
+0xFF676928,
+0xFFACB171,
+0xFF93995B,
+0xFF737D41,
+0xFF929F69,
+0xFF66743F,
+0xFF515E26,
+0xFF5E6834,
+0xFF515530,
+0xFF2B2C0A,
+0xFF8B8D65,
+0xFF7B8151,
+0xFF4B561E,
+0xFF6E7D42,
+0xFF77894B,
+0xFF334606,
+0xFFA5B577,
+0xFF677238,
+0xFF88915C,
+0xFFCFD6A2,
+0xFF7B7E45,
+0xFF9B9E65,
+0xFF909260,
+0xFFE2E9B6,
+0xFF636D39,
+0xFF99A671,
+0xFFB9C391,
+0xFF676E42,
+0xFF4F4F29,
+0xFF1C1A00,
+0xFF797A4E,
+0xFF535725,
+0xFF79824D,
+0xFF656E37,
+0xFF545923,
+0xFF8A8C5A,
+0xFF737A46,
+0xFF7C8350,
+0xFF707145,
+0xFF707241,
+0xFF8A9054,
+0xFF848D4A,
+0xFF737D38,
+0xFF969C5E,
+0xFF717341,
+0xFFA3A576,
+0xFFB3BA87,
+0xFF747B47,
+0xFF868856,
+0xFF767944,
+0xFF63662D,
+0xFFA2A76D,
+0xFF575C22,
+0xFF8A9257,
+0xFF4E571E,
+0xFF3D470A,
+0xFF9BA862,
+0xFF4B590E,
+0xFF697930,
+0xFF566522,
+0xFF69733E,
+0xFF636B3A,
+0xFF515824,
+0xFF7A8249,
+0xFF9FA569,
+0xFF91975B,
+0xFF7A7F47,
+0xFF9BA06A,
+0xFF5B622F,
+0xFF69703C,
+0xFF80854F,
+0xFF788047,
+0xFF808950,
+0xFF757F43,
+0xFF6E7839,
+0xFF545E1F,
+0xFF444F15,
+0xFF58662B,
+0xFF99A769,
+0xFF869552,
+0xFF73823D,
+0xFF71853D,
+0xFF5B7329,
+0xFF889F59,
+0xFF485C21,
+0xFF667740,
+0xFF91A163,
+0xFF3B490E,
+0xFF3C4818,
+0xFF656E41,
+0xFF4A531E,
+0xFF636734,
+0xFFA2A175,
+0xFF7F7C4F,
+0xFF83844A,
+0xFF949A5C,
+0xFFB0B980,
+0xFF545D28,
+0xFF797A4E,
+0xFF888558,
+0xFF6B6835,
+0xFF8C8B52,
+0xFF979C5A,
+0xFF898E4B,
+0xFFAAAA6C,
+0xFF55541B,
+0xFF5B5B29,
+0xFF7F7E4E,
+0xFF9C9964,
+0xFF85824B,
+0xFF989960,
+0xFF6E723F,
+0xFF7D7D57,
+0xFF51522A,
+0xFF7A7D48,
+0xFF82884A,
+0xFFA2A86C,
+0xFF9DA26A,
+0xFF7D814F,
+0xFF7F8351,
+0xFF888D55,
+0xFF676A35,
+0xFF75764A,
+0xFF9F9E72,
+0xFF888856,
+0xFF777745,
+0xFF55562A,
+0xFF6C6D43,
+0xFF474921,
+0xFF64653D,
+0xFF767549,
+0xFF525123,
+0xFF616435,
+0xFF5E6434,
+0xFF52582C,
+0xFF363B12,
+0xFF737955,
+0xFF383F16,
+0xFF444B18,
+0xFF666B35,
+0xFF7A7C4B,
+0xFF6E7144,
+0xFF43491B,
+0xFF565E2D,
+0xFF3C4510,
+0xFF6E7541,
+0xFFACAA7A,
+0xFF817E51,
+0xFF626538,
+0xFF91976B,
+0xFF2C2D0B,
+0xFF444525,
+0xFF81815D,
+0xFF5D5F37,
+0xFF171E00,
+0xFF414A1B,
+0xFF81895A,
+0xFF39400D,
+0xFF525721,
+0xFF90955F,
+0xFF5F6632,
+0xFF404714,
+0xFF6D6F3E,
+0xFF565529,
+0xFF4C4A24,
+0xFF413D18,
+0xFF7C774D,
+0xFF878054,
+0xFF807C4F,
+0xFF77764A,
+0xFF4C5327,
+0xFF4E5A2A,
+0xFF4E5F28,
+0xFF637539,
+0xFF47591B,
+0xFF586B2B,
+0xFF8C9F5F,
+0xFF607031,
+0xFF5E662B,
+0xFF656D34,
+0xFF79814E,
+0xFF586530,
+0xFF5E6C37,
+0xFF465723,
+0xFF424E20,
+0xFF576335,
+0xFF535F2F,
+0xFF46541F,
+0xFF49581F,
+0xFF5A6930,
+0xFF596631,
+0xFF4D5524,
+0xFF5F6235,
+0xFFBBBC90,
+0xFF2F2D18,
+0xFF38381E,
+0xFF2B3010,
+0xFF3A441F,
+0xFF2A3910,
+0xFF415226,
+0xFF2B3C0F,
+0xFF29390C,
+0xFF39441C,
+0xFF363D1B,
+0xFF3D4224,
+0xFF303517,
+0xFF1F2605,
+0xFF343E1B,
+0xFF46512F,
+0xFF4C5832,
+0xFF687146,
+0xFF282F03,
+0xFF4F562D,
+0xFF545A38,
+0xFF3C3F24,
+0xFF464832,
+0xFF2F2E1C,
+0xFF252314,
+0xFF252316,
+0xFF2E2F1F,
+0xFF3E3D2B,
+0xFF4B4D35,
+0xFF5A5D40,
+0xFF575D3B,
+0xFF454B25,
+0xFF4C542D,
+0xFF3F4926,
+0xFF292E0E,
+0xFF4D4C2E,
+0xFF524B2E,
+0xFF716847,
+0xFF7D7753,
+0xFF383812,
+0xFF474E24,
+0xFF636F41,
+0xFF4A572B,
+0xFF3D4422,
+0xFF303515,
+0xFF414425,
+0xFF3E3F1F,
+0xFF626343,
+0xFF3F411C,
+0xFF3D441A,
+0xFF2B3206,
+0xFF5E6134,
+0xFF727349,
+0xFF494623,
+0xFF8D8A67,
+0xFF54542E,
+0xFF686D44,
+0xFF687146,
+0xFF37461D,
+0xFF20300B,
+0xFF344620,
+0xFF2E3E17,
+0xFF2C3B14,
+0xFF141F00,
+0xFF4D5232,
+0xFF484421,
+0xFF5A582F,
+0xFFC8D29D,
+0xFF47591F,
+0xFF667240,
+0xFF4A5324,
+0xFF4F5529,
+0xFF54562E,
+0xFF616540,
+0xFF393B16,
+0xFF44401A,
+0xFF89875E,
+0xFF656C42,
+0xFF73794D,
+0xFF7E754C,
+0xFF403508,
+0xFF7B7B47,
+0xFF92975D,
+0xFF74783D,
+0xFF97985F,
+0xFF9B9E69,
+0xFF707243,
+0xFF433F1A,
+0xFF2C2606,
+0xFF544B2E,
+0xFF524C28,
+0xFF777441,
+0xFF716E37,
+0xFF877F51,
+0xFF9E956C,
+0xFF8E865F,
+0xFF514F26,
+0xFF767E4F,
+0xFF6B7445,
+0xFF636A3E,
+0xFF5E6436,
+0xFF616435,
+0xFF76794A,
+0xFF8D9365,
+0xFF62683C,
+0xFF62643C,
+0xFF818258,
+0xFF4A471E,
+0xFF757249,
+0xFF605D34,
+0xFF56542B,
+0xFF999C6F,
+0xFF4F5223,
+0xFF3A390B,
+0xFFCBCA9C,
+0xFF787A4B,
+0xFF717445,
+0xFF898B5C,
+0xFF737546,
+0xFF50501C,
+0xFF727240,
+0xFF727145,
+0xFF464515,
+0xFF616528,
+0xFFB4BB77,
+0xFFAAB16D,
+0xFF939856,
+0xFF6B6C30,
+0xFFA1A56A,
+0xFF596125,
+0xFF899357,
+0xFF8A955D,
+0xFF414B16,
+0xFF454E19,
+0xFF494F1F,
+0xFF747651,
+0xFF424122,
+0xFF6E6E48,
+0xFF878A5B,
+0xFF39420B,
+0xFF7C874B,
+0xFF7B894B,
+0xFF425213,
+0xFF728043,
+0xFF9CA971,
+0xFF36400E,
+0xFF8A915D,
+0xFFA4A86B,
+0xFF848947,
+0xFFB3B77C,
+0xFFB7BE88,
+0xFF8F9C66,
+0xFFB9C792,
+0xFF97A371,
+0xFF939C6D,
+0xFF33360B,
+0xFF4A491D,
+0xFF5D5D2B,
+0xFF929761,
+0xFF67723A,
+0xFF727D45,
+0xFF1C1F00,
+0xFF777741,
+0xFF979C66,
+0xFF7D814F,
+0xFF7A794D,
+0xFF89885A,
+0xFF474D0F,
+0xFF57611C,
+0xFF7D8643,
+0xFFA3A96D,
+0xFF5F5E30,
+0xFF98966D,
+0xFF565A28,
+0xFFAAAE7B,
+0xFF61612D,
+0xFF75753F,
+0xFFA1A56A,
+0xFF62682C,
+0xFF454A12,
+0xFF505721,
+0xFF767F46,
+0xFF727C3F,
+0xFF8D9A54,
+0xFF748139,
+0xFF55611F,
+0xFF586329,
+0xFF515928,
+0xFF5C6433,
+0xFF727943,
+0xFFA5AD72,
+0xFFA6AB73,
+0xFF5B6026,
+0xFF888E52,
+0xFF9FA46A,
+0xFF626933,
+0xFF696E38,
+0xFF6F723B,
+0xFF898C53,
+0xFF5D652A,
+0xFF7D8549,
+0xFF707636,
+0xFF565C1E,
+0xFF404912,
+0xFF838D58,
+0xFF909B5F,
+0xFF737F41,
+0xFF879653,
+0xFFAEC27D,
+0xFF6D823F,
+0xFF334708,
+0xFF54652E,
+0xFF364711,
+0xFF4F6029,
+0xFF4A5922,
+0xFF4D5B28,
+0xFF778351,
+0xFF4F5622,
+0xFFA0A270,
+0xFFBDB989,
+0xFF76703E,
+0xFF939158,
+0xFF919256,
+0xFFC6CE92,
+0xFF7A8247,
+0xFF9FA16F,
+0xFF767642,
+0xFFA1A06A,
+0xFF78783C,
+0xFF747939,
+0xFF858746,
+0xFF99975A,
+0xFF817F44,
+0xFF81804A,
+0xFF62602D,
+0xFFB8B27E,
+0xFF807B44,
+0xFFBAB885,
+0xFFA2A473,
+0xFF7C7A53,
+0xFF787650,
+0xFF717044,
+0xFF5E5D2D,
+0xFF6F6E3E,
+0xFF838556,
+0xFF58592F,
+0xFF4C4D25,
+0xFF7C7D55,
+0xFF45431A,
+0xFF96946B,
+0xFF6E6B40,
+0xFF848154,
+0xFF6D6A3D,
+0xFF78754A,
+0xFF747148,
+0xFF6E6D41,
+0xFF4A491B,
+0xFF656436,
+0xFF868857,
+0xFF414814,
+0xFF5F6633,
+0xFF4C5226,
+0xFF41461E,
+0xFF5C623C,
+0xFF4A5128,
+0xFF2A3000,
+0xFF686A39,
+0xFF747347,
+0xFF74724B,
+0xFF82825E,
+0xFF494B24,
+0xFF6C6F42,
+0xFF777948,
+0xFFAEAC7B,
+0xFF595726,
+0xFF707243,
+0xFF7C7E56,
+0xFF3B3A1C,
+0xFF48472B,
+0xFF5B5839,
+0xFF51512B,
+0xFF485021,
+0xFF67713F,
+0xFF5E6635,
+0xFF3F4613,
+0xFF737842,
+0xFF5D612E,
+0xFF474D1F,
+0xFF31360D,
+0xFF635F3C,
+0xFF625B3E,
+0xFF888366,
+0xFF383316,
+0xFF544D30,
+0xFF615837,
+0xFF78724E,
+0xFF45431D,
+0xFF4A4F27,
+0xFF5A6338,
+0xFF4B5725,
+0xFF617037,
+0xFF4C5C1D,
+0xFF495918,
+0xFF6B803D,
+0xFF839654,
+0xFF6D7738,
+0xFF838D50,
+0xFF5B6531,
+0xFF54622F,
+0xFF62733F,
+0xFF4A5B27,
+0xFF5C6838,
+0xFF6B7745,
+0xFF65723D,
+0xFF526128,
+0xFF56652A,
+0xFF4C5B22,
+0xFF5F6C37,
+0xFF515B29,
+0xFF676E3B,
+0xFFC6CA97,
+0xFF33311A,
+0xFF57573B,
+0xFF444A26,
+0xFF424D23,
+0xFF425128,
+0xFF495A2E,
+0xFF475929,
+0xFF4E5E31,
+0xFF57623A,
+0xFF535A38,
+0xFF2B2F14,
+0xFF161A00,
+0xFF292E10,
+0xFF585F3E,
+0xFF2A3515,
+0xFF414B29,
+0xFF585E3A,
+0xFF4F532E,
+0xFF60613F,
+0xFF4B4C2D,
+0xFF505036,
+0xFF3D3D25,
+0xFF2B2815,
+0xFF373423,
+0xFF333220,
+0xFF292814,
+0xFF41402B,
+0xFF3E3E26,
+0xFF38381C,
+0xFF414524,
+0xFF2F3310,
+0xFF2A300C,
+0xFF4B5030,
+0xFF3E4124,
+0xFF4E4A31,
+0xFF534C32,
+0xFF544B2C,
+0xFF4D4926,
+0xFF666843,
+0xFF525A31,
+0xFF5A6739,
+0xFF3A471B,
+0xFF525C39,
+0xFF626948,
+0xFF424826,
+0xFF2E3211,
+0xFF525331,
+0xFF646843,
+0xFF6B7047,
+0xFFA4AA7E,
+0xFFC0C394,
+0xFF4D4E22,
+0xFF3E3E18,
+0xFF797955,
+0xFF83855E,
+0xFF383F16,
+0xFF4C572F,
+0xFF46552E,
+0xFF253511,
+0xFF283915,
+0xFF2B3B16,
+0xFF25340D,
+0xFF152100,
+0xFF2C3210,
+0xFF5F5B38,
+0xFF838055,
+0xFFC6D497,
+0xFF879A5A,
+0xFF5D6A35,
+0xFF333B0C,
+0xFF5F6233,
+0xFF4A4B1F,
+0xFF3D3F17,
+0xFF2C2C06,
+0xFF48421E,
+0xFFA39F79,
+0xFF596132,
+0xFF8C9360,
+0xFF908A5A,
+0xFF67602C,
+0xFFC0C38C,
+0xFFA4A971,
+0xFF6C6F36,
+0xFFC4C58C,
+0xFF686B34,
+0xFF454716,
+0xFF514E25,
+0xFF96906E,
+0xFF3A3114,
+0xFF463D1C,
+0xFF7F7B4B,
+0xFF6E6834,
+0xFF958D5E,
+0xFF6C6036,
+0xFF6A6138,
+0xFF504D20,
+0xFF909764,
+0xFF3E4814,
+0xFF3A4211,
+0xFF858B5B,
+0xFF646B38,
+0xFF858D5A,
+0xFFE1E9BA,
+0xFF767C4E,
+0xFF4E5124,
+0xFF727145,
+0xFF716D40,
+0xFF676034,
+0xFF5B562C,
+0xFF59582C,
+0xFF9C9F70,
+0xFF8B8F5D,
+0xFF313302,
+0xFF7C7E4D,
+0xFF6F7341,
+0xFF5A5E2C,
+0xFF696C3D,
+0xFF424614,
+0xFF666934,
+0xFF8D8D5B,
+0xFF838254,
+0xFF7C7B4B,
+0xFF5C6224,
+0xFF8B924E,
+0xFFAEB572,
+0xFF838949,
+0xFF818249,
+0xFF8F925B,
+0xFF585D23,
+0xFF343C01,
+0xFF888F59,
+0xFF3F4310,
+0xFF858957,
+0xFF5E6031,
+0xFF222000,
+0xFF413E1B,
+0xFF3B3C14,
+0xFF787B4C,
+0xFFA0A56B,
+0xFF525A1E,
+0xFF5C6629,
+0xFF616C30,
+0xFF69743A,
+0xFFA5B078,
+0xFF5B6435,
+0xFF343C09,
+0xFF858B4B,
+0xFFCDD28F,
+0xFF6B7030,
+0xFF636B30,
+0xFFBDCA94,
+0xFF74854F,
+0xFF364411,
+0xFFA8B27E,
+0xFF444718,
+0xFF8D8F5D,
+0xFF5F5F2B,
+0xFF6F743C,
+0xFF7C8651,
+0xFF48531B,
+0xFF3D4009,
+0xFF85864D,
+0xFF6D7238,
+0xFF686D37,
+0xFF6C6B3F,
+0xFF767547,
+0xFF50561A,
+0xFF969F5C,
+0xFF767F3E,
+0xFF757A40,
+0xFF737246,
+0xFF706E45,
+0xFF464A18,
+0xFF8A8F57,
+0xFF9A9A64,
+0xFF56571E,
+0xFF757B3F,
+0xFF91995D,
+0xFF3F4610,
+0xFF3B440D,
+0xFF8D965D,
+0xFFA0AC6C,
+0xFF68752F,
+0xFF8F9C56,
+0xFF626D31,
+0xFF89935F,
+0xFF5B6437,
+0xFF565E2F,
+0xFF808950,
+0xFF91995E,
+0xFF616832,
+0xFF7F874E,
+0xFF666E32,
+0xFF878F53,
+0xFFAEB67D,
+0xFF8A8F59,
+0xFF9C9F66,
+0xFF93965D,
+0xFF8B9056,
+0xFFA3A96D,
+0xFF909253,
+0xFF606427,
+0xFF7D844E,
+0xFF4B561E,
+0xFF909960,
+0xFF929E60,
+0xFF9BAA69,
+0xFF97AA68,
+0xFF728545,
+0xFF384B0B,
+0xFF3F4E13,
+0xFF59682F,
+0xFF1A2900,
+0xFF515F2A,
+0xFF65733E,
+0xFF7E8853,
+0xFF868D59,
+0xFF969964,
+0xFFA29F6A,
+0xFFABA66F,
+0xFF97945D,
+0xFFA6A56D,
+0xFF92985C,
+0xFF485014,
+0xFF878C54,
+0xFF53561F,
+0xFF86874D,
+0xFF9E9F63,
+0xFF7A7E41,
+0xFF6A6B2F,
+0xFF817C45,
+0xFFA39C68,
+0xFF7A7744,
+0xFF5B5523,
+0xFF786E3B,
+0xFFA49D69,
+0xFF7B7845,
+0xFF8C8B5D,
+0xFF96946D,
+0xFF7A7653,
+0xFF6D6944,
+0xFF524E28,
+0xFF7F7C51,
+0xFF706F43,
+0xFF686640,
+0xFF545430,
+0xFFB2AF8C,
+0xFF94926C,
+0xFF7C7852,
+0xFF6F6A44,
+0xFFD1CCA4,
+0xFFBDB590,
+0xFF5D5531,
+0xFF908864,
+0xFF8F8A62,
+0xFF504C1F,
+0xFF716E41,
+0xFF5A5929,
+0xFF474E18,
+0xFF565D29,
+0xFF2B3105,
+0xFF4A4E29,
+0xFF6A704A,
+0xFF3D441B,
+0xFF4A4D1E,
+0xFF858756,
+0xFFA19E73,
+0xFF68633D,
+0xFF605D3C,
+0xFF585836,
+0xFF57582E,
+0xFF8A8959,
+0xFF73713E,
+0xFF83834F,
+0xFF545826,
+0xFF54572C,
+0xFF353617,
+0xFF504F33,
+0xFF605D3E,
+0xFF54562F,
+0xFF61693A,
+0xFF8F9965,
+0xFF757D4A,
+0xFF7D8651,
+0xFF7B7F4C,
+0xFF404412,
+0xFF494F23,
+0xFF3D3F1A,
+0xFF403B1E,
+0xFF3B331C,
+0xFF4D472F,
+0xFF3B351D,
+0xFF433B24,
+0xFF3B3418,
+0xFF1E1800,
+0xFF726E4B,
+0xFF656742,
+0xFF5B6239,
+0xFF374011,
+0xFF5B6530,
+0xFF6A7636,
+0xFF5B6A27,
+0xFF556A27,
+0xFF859856,
+0xFF8A9654,
+0xFF95A163,
+0xFF3B4812,
+0xFF485925,
+0xFF647541,
+0xFF404E1B,
+0xFF626E3C,
+0xFF63703B,
+0xFF626F39,
+0xFF45521A,
+0xFF5B6A31,
+0xFF62713A,
+0xFF6B7946,
+0xFF5A6334,
+0xFF515824,
+0xFF959C66,
+0xFF343516,
+0xFF6F7350,
+0xFF717952,
+0xFF5A653B,
+0xFF56653C,
+0xFF57683E,
+0xFF596A3E,
+0xFF4A592E,
+0xFF505C36,
+0xFF676E4D,
+0xFF31371B,
+0xFF31351C,
+0xFF51553A,
+0xFF5A6044,
+0xFF3B4127,
+0xFF31371D,
+0xFF383B1E,
+0xFF444526,
+0xFF57563A,
+0xFF5F5E42,
+0xFF37351C,
+0xFF2A280F,
+0xFF323019,
+0xFF43412A,
+0xFF27250E,
+0xFF323019,
+0xFF3D3B24,
+0xFF3C3A21,
+0xFF28260D,
+0xFF5A5A3E,
+0xFF818263,
+0xFF404122,
+0xFF4C4C32,
+0xFF494931,
+0xFF55503C,
+0xFF524C36,
+0xFF5A5538,
+0xFF494627,
+0xFF373818,
+0xFF363C18,
+0xFF293108,
+0xFF29340C,
+0xFF5F6647,
+0xFF555C3D,
+0xFF484D2D,
+0xFF242A06,
+0xFF1E2200,
+0xFF70754D,
+0xFF999E76,
+0xFF90926A,
+0xFF76794C,
+0xFF66693C,
+0xFF4B4D25,
+0xFF4F542C,
+0xFF2F360D,
+0xFF4A552D,
+0xFF323E1A,
+0xFF293714,
+0xFF182708,
+0xFF152403,
+0xFF32401D,
+0xFF0C1B00,
+0xFF4D5933,
+0xFF3D431D,
+0xFF4A4620,
+0xFFAEAD7D,
+0xFFC7D695,
+0xFF778746,
+0xFF2E3607,
+0xFF282900,
+0xFF6A6835,
+0xFF4A4911,
+0xFF626933,
+0xFF494C1D,
+0xFF4D4520,
+0xFF8D845D,
+0xFF898756,
+0xFF9D9E64,
+0xFFA7A76B,
+0xFF4E4F15,
+0xFF656839,
+0xFF474921,
+0xFF514F29,
+0xFFD4D2AB,
+0xFF717344,
+0xFF707241,
+0xFF959363,
+0xFFB4AF87,
+0xFF3B3215,
+0xFF473E1F,
+0xFF666137,
+0xFF817D4D,
+0xFF9E9366,
+0xFF55491F,
+0xFF6D643B,
+0xFF666336,
+0xFF3C430D,
+0xFF464F18,
+0xFF424B16,
+0xFFBCC590,
+0xFF8B945D,
+0xFFBFCA92,
+0xFFC5CF9B,
+0xFF212900,
+0xFF3B3D0E,
+0xFF827F52,
+0xFFA9A173,
+0xFF82794E,
+0xFF3D360C,
+0xFF4B481D,
+0xFF46491A,
+0xFF979E6B,
+0xFF454716,
+0xFF686A38,
+0xFF646836,
+0xFF868D5A,
+0xFF848B57,
+0xFF2D3100,
+0xFF363904,
+0xFFB4B482,
+0xFF9E9B6E,
+0xFF828151,
+0xFF5E6329,
+0xFF818A4B,
+0xFF838C4B,
+0xFF898F53,
+0xFF555521,
+0xFF4D4D1B,
+0xFF8F925B,
+0xFF7E814A,
+0xFF8D8D5B,
+0xFF535121,
+0xFF8D8A5D,
+0xFF747144,
+0xFF4C4B1F,
+0xFF929165,
+0xFF55562A,
+0xFF676937,
+0xFF7E8247,
+0xFF5F6326,
+0xFF5C5F26,
+0xFF6A6F37,
+0xFF666B33,
+0xFF585F29,
+0xFFA4AC7D,
+0xFF757D4A,
+0xFF7D8345,
+0xFF79803C,
+0xFF686E2E,
+0xFF879155,
+0xFF6C7A45,
+0xFF879864,
+0xFF3E4C17,
+0xFFB5C28C,
+0xFF565D27,
+0xFF7B8048,
+0xFF8E915C,
+0xFF5F6630,
+0xFF4A5722,
+0xFF8D9A64,
+0xFF969B61,
+0xFF6B7133,
+0xFF90995A,
+0xFF6A7237,
+0xFF4E5021,
+0xFF6F7142,
+0xFFC5CA90,
+0xFF848D4E,
+0xFF6F773B,
+0xFF6D723A,
+0xFF626339,
+0xFFC1C298,
+0xFF606731,
+0xFF899155,
+0xFF757B3F,
+0xFF757B3F,
+0xFF767F40,
+0xFF828C4F,
+0xFF707940,
+0xFF616C34,
+0xFF626D31,
+0xFF8E9A5A,
+0xFF94A15B,
+0xFF7C8B46,
+0xFF7C8951,
+0xFF525E2E,
+0xFF667146,
+0xFF394213,
+0xFF515C22,
+0xFF98A266,
+0xFF717A43,
+0xFF79824B,
+0xFF8C965A,
+0xFF8D975A,
+0xFF7A834A,
+0xFF616930,
+0xFFA9A973,
+0xFFAFAF79,
+0xFF757841,
+0xFF61642B,
+0xFF6D6D31,
+0xFF5B5B1F,
+0xFF646C31,
+0xFF848E52,
+0xFF757F42,
+0xFF4F5B1B,
+0xFF697938,
+0xFF7A8D4B,
+0xFF5B6C28,
+0xFF7A8944,
+0xFF889550,
+0xFF85914F,
+0xFF5A652B,
+0xFF4F5A22,
+0xFF4E5921,
+0xFF828D53,
+0xFF495118,
+0xFF91945D,
+0xFF9E9D64,
+0xFF84814A,
+0xFF605C2C,
+0xFF5C5A29,
+0xFF797C45,
+0xFF7E8349,
+0xFF858D54,
+0xFF7D8248,
+0xFF767A3D,
+0xFF8D9252,
+0xFF7C8045,
+0xFF7E7D47,
+0xFFA39A6F,
+0xFF6B5F37,
+0xFFA9A075,
+0xFF776F41,
+0xFF7C703E,
+0xFFB1A573,
+0xFF706A38,
+0xFF959265,
+0xFFA19D77,
+0xFF8C8865,
+0xFF837D5D,
+0xFF6E6844,
+0xFF555026,
+0xFF555225,
+0xFF66643D,
+0xFF413F19,
+0xFF9A9871,
+0xFFBEBC95,
+0xFF7A7555,
+0xFF9E9878,
+0xFF645B3A,
+0xFFA4997B,
+0xFF63573F,
+0xFF372B13,
+0xFF5D5232,
+0xFF6F6541,
+0xFF877F58,
+0xFF575429,
+0xFF686C3A,
+0xFF676E3B,
+0xFF54562E,
+0xFF797B56,
+0xFF5B613D,
+0xFF2C330A,
+0xFF4A4D1E,
+0xFF686836,
+0xFF8E8A5D,
+0xFFCCC7A1,
+0xFF504D2A,
+0xFF585834,
+0xFF706F43,
+0xFF50501E,
+0xFF95955F,
+0xFF61642D,
+0xFF69703C,
+0xFF707648,
+0xFF3A3C17,
+0xFF4E4F2D,
+0xFF383814,
+0xFF585A32,
+0xFF6F7748,
+0xFF7B8755,
+0xFF59632F,
+0xFF7A824F,
+0xFF565A28,
+0xFF606636,
+0xFF52592D,
+0xFF3B3F1A,
+0xFF423C22,
+0xFF342C15,
+0xFF343017,
+0xFF3C381F,
+0xFF2B250F,
+0xFF3F381E,
+0xFF1D1700,
+0xFF95916C,
+0xFF6F6F49,
+0xFF7F845C,
+0xFF555A31,
+0xFF434B18,
+0xFF6E7839,
+0xFF9DAA65,
+0xFF586B29,
+0xFF768B4A,
+0xFF8E9D5A,
+0xFF8C9A5C,
+0xFF5B6A33,
+0xFF42531F,
+0xFF657640,
+0xFF596732,
+0xFF687540,
+0xFF5A6430,
+0xFF545E2A,
+0xFF5E6B36,
+0xFF616F3A,
+0xFF4E5C29,
+0xFF3D4A1C,
+0xFF3E4A1C,
+0xFF505825,
+0xFF7A834E,
+0xFF565D34,
+0xFF777F56,
+0xFF7E865D,
+0xFF525D33,
+0xFF3A461E,
+0xFF4B5A33,
+0xFF404F28,
+0xFF22310A,
+0xFF46522E,
+0xFF444D2E,
+0xFF353E21,
+0xFF393F25,
+0xFF454930,
+0xFF3E422B,
+0xFF262914,
+0xFF30331E,
+0xFF3D3C27,
+0xFF404028,
+0xFF2B2912,
+0xFF3A3A20,
+0xFF2A2A10,
+0xFF2D2D11,
+0xFF353519,
+0xFF36361A,
+0xFF49492D,
+0xFF47472B,
+0xFF424226,
+0xFF434128,
+0xFF35331A,
+0xFF38361F,
+0xFF323019,
+0xFF2D2B14,
+0xFF2F2F15,
+0xFF51533B,
+0xFF403F2B,
+0xFF2E2D18,
+0xFF37361A,
+0xFF333214,
+0xFF212105,
+0xFF292A0B,
+0xFF4C4E29,
+0xFF414522,
+0xFF626548,
+0xFF5A5F41,
+0xFF636947,
+0xFF444A24,
+0xFF31360D,
+0xFF2E330A,
+0xFF4C4E27,
+0xFF51532C,
+0xFF63653D,
+0xFF7F8559,
+0xFF686E42,
+0xFF353C12,
+0xFF1F2A02,
+0xFF2D3915,
+0xFF283615,
+0xFF455234,
+0xFF313E22,
+0xFF142103,
+0xFF142201,
+0xFF2C3814,
+0xFF8F9B73,
+0xFF252C03,
+0xFF393711,
+0xFF9B9A6E,
+0xFFADB87E,
+0xFF37450A,
+0xFF272901,
+0xFF423E19,
+0xFF726A39,
+0xFF9A955E,
+0xFF747845,
+0xFF606233,
+0xFF473D19,
+0xFF8E805B,
+0xFF888051,
+0xFF6D6A33,
+0xFF6B6C32,
+0xFF696C35,
+0xFF505328,
+0xFF525331,
+0xFF4B4829,
+0xFF8F8A6A,
+0xFF505129,
+0xFF47481C,
+0xFF8F8C5F,
+0xFF625D35,
+0xFF4B4223,
+0xFF6C6646,
+0xFF5E5B30,
+0xFF666232,
+0xFF7D7245,
+0xFF493D13,
+0xFF736B44,
+0xFF777447,
+0xFF676B38,
+0xFF464F16,
+0xFF808954,
+0xFF9EA772,
+0xFF566129,
+0xFF444E19,
+0xFF343E0A,
+0xFF212900,
+0xFF606233,
+0xFF787447,
+0xFF978B61,
+0xFF76693F,
+0xFF544B22,
+0xFF6A673C,
+0xFF7F8253,
+0xFF808754,
+0xFF737544,
+0xFF848654,
+0xFF686C3A,
+0xFF7E8551,
+0xFF8A915B,
+0xFFB4B981,
+0xFF494C17,
+0xFF9B9B69,
+0xFF888558,
+0xFF979666,
+0xFF6B703A,
+0xFF9FA76C,
+0xFF5E662A,
+0xFF8C9157,
+0xFF9F9E6E,
+0xFF716F3F,
+0xFF81814D,
+0xFF7A7A44,
+0xFF7F7D4D,
+0xFF9B976A,
+0xFF605C2F,
+0xFF666336,
+0xFFAAAC7B,
+0xFF828653,
+0xFF9CA06D,
+0xFF757A42,
+0xFF7F8444,
+0xFF848949,
+0xFF61612B,
+0xFF787846,
+0xFF636631,
+0xFF454A14,
+0xFF616938,
+0xFF868E5B,
+0xFF687034,
+0xFF6A7334,
+0xFF454D11,
+0xFF6F7A40,
+0xFF73814E,
+0xFF84925F,
+0xFF596831,
+0xFFA7B47C,
+0xFF495116,
+0xFF6E763D,
+0xFF545B27,
+0xFFA5AD7A,
+0xFF8D9967,
+0xFF596631,
+0xFFA8B178,
+0xFF707A3D,
+0xFF7C8846,
+0xFF939D60,
+0xFF606431,
+0xFF5E602F,
+0xFFA2AA6F,
+0xFF3E4708,
+0xFF8A9256,
+0xFF656D34,
+0xFF6B6E41,
+0xFF636637,
+0xFF778246,
+0xFF829150,
+0xFF858F52,
+0xFF667033,
+0xFF616D2F,
+0xFF677537,
+0xFF475216,
+0xFF788649,
+0xFF6D793B,
+0xFF808F4E,
+0xFF697833,
+0xFFC3D291,
+0xFF84915B,
+0xFF495525,
+0xFF586338,
+0xFF222E00,
+0xFF8B995E,
+0xFF889659,
+0xFF58632B,
+0xFF8A945F,
+0xFF9BA66E,
+0xFF384309,
+0xFF6A7539,
+0xFFC5CD92,
+0xFF82834A,
+0xFFB8B980,
+0xFF83864D,
+0xFF676A31,
+0xFF86834E,
+0xFF64632D,
+0xFF41460C,
+0xFF394307,
+0xFF9DA76A,
+0xFF727E3E,
+0xFF354504,
+0xFF6C803B,
+0xFF4F5E1B,
+0xFF5C6826,
+0xFFA0AB67,
+0xFF6A7332,
+0xFF485015,
+0xFF4B531A,
+0xFF808952,
+0xFF414A13,
+0xFF677037,
+0xFF7F844A,
+0xFF67682F,
+0xFF93925C,
+0xFF878353,
+0xFF7A7847,
+0xFF999965,
+0xFF40450D,
+0xFF5D662D,
+0xFF596327,
+0xFF73793B,
+0xFF808449,
+0xFFABAD7B,
+0xFF59562B,
+0xFF534828,
+0xFF605134,
+0xFF807350,
+0xFF655931,
+0xFF998B5E,
+0xFF6A5C2D,
+0xFF857D4F,
+0xFF4F4A20,
+0xFF5E5A34,
+0xFF4E4826,
+0xFF82795A,
+0xFF6C6342,
+0xFF716C44,
+0xFF504D24,
+0xFF696540,
+0xFF484620,
+0xFFA09E77,
+0xFF93916A,
+0xFF858060,
+0xFF463F22,
+0xFF564D2E,
+0xFF9D9276,
+0xFF685944,
+0xFF6E5F4A,
+0xFF54452E,
+0xFF6E6043,
+0xFF453818,
+0xFF5E5430,
+0xFF706E45,
+0xFF828359,
+0xFF63603D,
+0xFF5D5D3B,
+0xFF686C4B,
+0xFF5E633B,
+0xFF484D17,
+0xFFA6A670,
+0xFF575024,
+0xFFCBC6A0,
+0xFF4F4F29,
+0xFF53552D,
+0xFF7B7D4C,
+0xFF71743D,
+0xFF757841,
+0xFF7D824C,
+0xFF4C5520,
+0xFF78804F,
+0xFF52582A,
+0xFF4A4D22,
+0xFF44461E,
+0xFF656B3F,
+0xFF515A2B,
+0xFF828E5E,
+0xFF4E5A28,
+0xFF434D1B,
+0xFF717749,
+0xFF5E6436,
+0xFF4C5526,
+0xFF4B5027,
+0xFF393416,
+0xFF4A4327,
+0xFF141300,
+0xFF474628,
+0xFF444027,
+0xFF251F05,
+0xFF908C69,
+0xFF827E58,
+0xFF4F5028,
+0xFF5E6038,
+0xFF595B33,
+0xFF474A1B,
+0xFF777D3F,
+0xFF7F8A46,
+0xFF627535,
+0xFF637738,
+0xFF859556,
+0xFF748245,
+0xFF73844D,
+0xFF3E511A,
+0xFF475821,
+0xFF495821,
+0xFF5C6836,
+0xFF384112,
+0xFF596235,
+0xFF515A2D,
+0xFF414D1F,
+0xFF566335,
+0xFF4C592E,
+0xFF3F4A1F,
+0xFF535C2D,
+0xFF565E2B,
+0xFF5B6737,
+0xFF576335,
+0xFF5D683E,
+0xFF354018,
+0xFF343E19,
+0xFF56623E,
+0xFF2B3614,
+0xFF32401F,
+0xFF5E694B,
+0xFF2F3A1C,
+0xFF444F2F,
+0xFF384124,
+0xFF2D321C,
+0xFF262916,
+0xFF1F200E,
+0xFF2A2B19,
+0xFF2A2B19,
+0xFF2D2F1A,
+0xFF3B3A25,
+0xFF5F6149,
+0xFF323518,
+0xFF2E3112,
+0xFF363A19,
+0xFF696D4A,
+0xFF626643,
+0xFF232706,
+0xFF343718,
+0xFF4C4C30,
+0xFF26260E,
+0xFF3C3B27,
+0xFF3B3827,
+0xFF272612,
+0xFF272A0F,
+0xFF252C0D,
+0xFF384126,
+0xFF353B21,
+0xFF3F4426,
+0xFF313415,
+0xFF2E2A0F,
+0xFF413C1F,
+0xFF7A7452,
+0xFF7A7555,
+0xFF3D391E,
+0xFF6E6F50,
+0xFFB1B590,
+0xFF6C7246,
+0xFF454B1B,
+0xFF474A1D,
+0xFF3F4018,
+0xFF464622,
+0xFF4B4D28,
+0xFF555A32,
+0xFF5B6437,
+0xFF3D491B,
+0xFF3B4721,
+0xFF394726,
+0xFF4C593D,
+0xFF58654B,
+0xFF283519,
+0xFF131D02,
+0xFF3F4A2C,
+0xFF687450,
+0xFF727F54,
+0xFF283106,
+0xFF575733,
+0xFF666342,
+0xFF474C24,
+0xFF495027,
+0xFF424323,
+0xFF5F5A3A,
+0xFF60542E,
+0xFF4C401A,
+0xFF6C6644,
+0xFF443E1E,
+0xFF5B4E2B,
+0xFF887A55,
+0xFF777046,
+0xFF312E03,
+0xFF9A996D,
+0xFF94956B,
+0xFF6E7049,
+0xFF50502C,
+0xFF5E5A37,
+0xFF706C49,
+0xFF494925,
+0xFF31310B,
+0xFF8D8964,
+0xFF625C38,
+0xFF5D5435,
+0xFF4D4822,
+0xFF545221,
+0xFF696734,
+0xFF51481D,
+0xFF534A23,
+0xFF706B43,
+0xFF7F7E52,
+0xFF545625,
+0xFF49501C,
+0xFF929A69,
+0xFF525C2A,
+0xFFA9B583,
+0xFFABB787,
+0xFF364214,
+0xFF686F43,
+0xFF525027,
+0xFFA7A076,
+0xFF94865F,
+0xFFAC9D76,
+0xFF685C34,
+0xFF767147,
+0xFF949A6C,
+0xFF404819,
+0xFF737544,
+0xFF7C7E4D,
+0xFF1B2200,
+0xFF68713C,
+0xFF7E884C,
+0xFF8B9357,
+0xFF70703C,
+0xFF72703F,
+0xFF2D2B00,
+0xFF9B9A6A,
+0xFF808251,
+0xFF666A37,
+0xFF767B43,
+0xFF61642D,
+0xFF575427,
+0xFFB4B184,
+0xFF5D602B,
+0xFF5F622D,
+0xFF7F7C4F,
+0xFF89845A,
+0xFF656237,
+0xFFC3C594,
+0xFFB9C289,
+0xFF728042,
+0xFF324002,
+0xFF6E7A3A,
+0xFF87904D,
+0xFF878D4D,
+0xFF4E511C,
+0xFF5E5D2D,
+0xFF6E703E,
+0xFF737842,
+0xFF4F5724,
+0xFF8C9461,
+0xFF79824B,
+0xFF5D682E,
+0xFF424D15,
+0xFF43501A,
+0xFF6E7A4A,
+0xFF546030,
+0xFF445119,
+0xFF828D51,
+0xFF8F995C,
+0xFF404910,
+0xFF4B5324,
+0xFF97A075,
+0xFF788456,
+0xFF4B5725,
+0xFF5D6A35,
+0xFF8F9E63,
+0xFF7E8F4B,
+0xFF83924F,
+0xFF879057,
+0xFF6C743B,
+0xFF7B8445,
+0xFF6F7A36,
+0xFF899452,
+0xFF555F23,
+0xFF606733,
+0xFF858E59,
+0xFF859556,
+0xFF677A38,
+0xFF6D7F43,
+0xFF839259,
+0xFF748348,
+0xFF39490B,
+0xFF758443,
+0xFF647433,
+0xFF6E7D3C,
+0xFF7F8F4E,
+0xFF627231,
+0xFF869658,
+0xFF34430C,
+0xFF94A271,
+0xFF738054,
+0xFF5B6938,
+0xFF6D7C43,
+0xFF3D4C11,
+0xFF47541C,
+0xFF424F19,
+0xFF45511F,
+0xFF4C5924,
+0xFF6C7A3D,
+0xFFA4AE6F,
+0xFF939458,
+0xFFA3A367,
+0xFF94955B,
+0xFF6D6D37,
+0xFF979062,
+0xFF726E41,
+0xFF4C501D,
+0xFF969F68,
+0xFF858E55,
+0xFF727E40,
+0xFF60742F,
+0xFF667A35,
+0xFF596827,
+0xFF8C965A,
+0xFFA1A572,
+0xFF6E703E,
+0xFF3E410A,
+0xFFDADFA7,
+0xFF656C39,
+0xFF434B18,
+0xFF6F783F,
+0xFF525A1F,
+0xFF878957,
+0xFF8B8B59,
+0xFF797840,
+0xFF827F48,
+0xFF74723F,
+0xFF434611,
+0xFF838E52,
+0xFF8E995D,
+0xFF687035,
+0xFF515522,
+0xFF35370F,
+0xFF6B6849,
+0xFF4C3D28,
+0xFF56462F,
+0xFF6A5B3E,
+0xFFA29471,
+0xFF85734D,
+0xFF6A5B34,
+0xFF8A815A,
+0xFF565129,
+0xFF646138,
+0xFF4E4923,
+0xFF615734,
+0xFF584D2D,
+0xFF534A2B,
+0xFF645F3F,
+0xFF6A6545,
+0xFF524F2C,
+0xFFB5B38D,
+0xFF5F5D37,
+0xFF54502D,
+0xFF756F4D,
+0xFF483F1E,
+0xFF74694B,
+0xFF45371D,
+0xFF3E2E17,
+0xFF5D4C3C,
+0xFF5A4935,
+0xFF7A664D,
+0xFF4C3B1D,
+0xFF60573A,
+0xFF645F42,
+0xFF3E371B,
+0xFF575235,
+0xFF555436,
+0xFF3F4119,
+0xFF585C1F,
+0xFFBCBE7F,
+0xFF3A3609,
+0xFFB6B28D,
+0xFF3A3C15,
+0xFF5F6736,
+0xFF8D9559,
+0xFF687130,
+0xFF50581F,
+0xFF7C834F,
+0xFF6C7642,
+0xFF5B6530,
+0xFF4F5620,
+0xFF4D541E,
+0xFF606734,
+0xFF555D2E,
+0xFF556133,
+0xFF667347,
+0xFF293608,
+0xFF475325,
+0xFF666D43,
+0xFF4C5327,
+0xFF5A6432,
+0xFF6C7443,
+0xFF424019,
+0xFF64603B,
+0xFF363810,
+0xFF2B3008,
+0xFF474828,
+0xFF585738,
+0xFF848158,
+0xFF605D32,
+0xFF505125,
+0xFF53542A,
+0xFF64653D,
+0xFF3F4112,
+0xFF83874A,
+0xFF626B28,
+0xFF506022,
+0xFF4F6328,
+0xFF7B8A51,
+0xFF4F5E27,
+0xFF84975F,
+0xFF566B32,
+0xFF4E6225,
+0xFF516329,
+0xFF3B4717,
+0xFF3F471E,
+0xFF595F3B,
+0xFF222A05,
+0xFF2C370F,
+0xFF5E6B40,
+0xFF424E28,
+0xFF465129,
+0xFF485126,
+0xFF495225,
+0xFF404E19,
+0xFF3A4817,
+0xFF4C572D,
+0xFF515B36,
+0xFF46502B,
+0xFF47512E,
+0xFF2E391B,
+0xFF3F492E,
+0xFF374428,
+0xFF435032,
+0xFF475232,
+0xFF3B4427,
+0xFF2F341E,
+0xFF232615,
+0xFF282617,
+0xFF373526,
+0xFF242515,
+0xFF323321,
+0xFF484A35,
+0xFF51533B,
+0xFF454A2C,
+0xFF292F0D,
+0xFF555B37,
+0xFF444A24,
+0xFF656B45,
+0xFF777D59,
+0xFF565A39,
+0xFF484B2E,
+0xFF2C2B16,
+0xFF262513,
+0xFF2C291A,
+0xFF383725,
+0xFF575C3E,
+0xFF313B19,
+0xFF5A6449,
+0xFF4F593E,
+0xFF636C4D,
+0xFF36391A,
+0xFF47432A,
+0xFF585135,
+0xFF5F5436,
+0xFF3B3211,
+0xFF373117,
+0xFF3C3B1D,
+0xFFADAF88,
+0xFFC2C89A,
+0xFF9DA471,
+0xFF6F7243,
+0xFF505129,
+0xFF282804,
+0xFF4B4C2A,
+0xFF61683F,
+0xFF4C5528,
+0xFF616E40,
+0xFF6D7953,
+0xFF283615,
+0xFF2D3921,
+0xFF2A361E,
+0xFF1E280F,
+0xFF293318,
+0xFF2F3A1C,
+0xFF242F0D,
+0xFF3F4C20,
+0xFF596237,
+0xFF363614,
+0xFF605C3F,
+0xFF393A1B,
+0xFF3A3D1E,
+0xFF414024,
+0xFF7D785A,
+0xFF7A6B4C,
+0xFF928163,
+0xFF7F735B,
+0xFF483C22,
+0xFF615231,
+0xFF675932,
+0xFF726A45,
+0xFF918D68,
+0xFF55522F,
+0xFFA8A884,
+0xFF757752,
+0xFF43431D,
+0xFF4D4723,
+0xFF66603C,
+0xFF4F4F2D,
+0xFF636341,
+0xFF595434,
+0xFF655F3F,
+0xFF5D5433,
+0xFF555028,
+0xFF83814E,
+0xFF6A6933,
+0xFF5D542B,
+0xFF665C38,
+0xFF5E5931,
+0xFFA3A276,
+0xFF6B6D3E,
+0xFF7C8350,
+0xFFA2A87A,
+0xFF576031,
+0xFFAAB688,
+0xFF5E6B3D,
+0xFF667146,
+0xFF363D13,
+0xFF4C4A21,
+0xFF9E966F,
+0xFF80714A,
+0xFFBDAE87,
+0xFF796D45,
+0xFF969167,
+0xFF595F33,
+0xFF343C0D,
+0xFF666839,
+0xFF555726,
+0xFF5B622F,
+0xFF757E47,
+0xFF6A7437,
+0xFF98A162,
+0xFF6D6D39,
+0xFF434110,
+0xFF2B2900,
+0xFF7A7949,
+0xFF55562A,
+0xFF4F5321,
+0xFF555A24,
+0xFF838651,
+0xFF302D00,
+0xFF636033,
+0xFF313301,
+0xFF787B46,
+0xFF7D7A4D,
+0xFF625F34,
+0xFF514E23,
+0xFFBDC18F,
+0xFFB8C486,
+0xFF455612,
+0xFF657836,
+0xFFA9BA76,
+0xFFBEC984,
+0xFF979D5D,
+0xFFA1A371,
+0xFF6D6F40,
+0xFF808250,
+0xFF9AA16B,
+0xFF777E4B,
+0xFF575F2C,
+0xFF919B66,
+0xFF8D9762,
+0xFF76834D,
+0xFF64713C,
+0xFF7D895B,
+0xFF849060,
+0xFF6A753D,
+0xFF889456,
+0xFF899356,
+0xFF414A11,
+0xFF616A3D,
+0xFFA1A980,
+0xFF5D683D,
+0xFF303E0D,
+0xFF687643,
+0xFFA5B77D,
+0xFFA2B772,
+0xFF6B7F3A,
+0xFF869054,
+0xFF474F14,
+0xFF45500E,
+0xFF919C57,
+0xFF8B9654,
+0xFF6B7538,
+0xFF707942,
+0xFF5D6A32,
+0xFF6D803E,
+0xFF607733,
+0xFF64783D,
+0xFF384B13,
+0xFF54632A,
+0xFF768648,
+0xFF81924E,
+0xFF82934D,
+0xFF7D8D4C,
+0xFF6D7D3C,
+0xFF556526,
+0xFF49591B,
+0xFF75834E,
+0xFFBBC998,
+0xFF839062,
+0xFF5D6B3A,
+0xFF606F38,
+0xFF4B5A1F,
+0xFF4D5C23,
+0xFF52612A,
+0xFF616E40,
+0xFF485623,
+0xFF7D8B4E,
+0xFF98A361,
+0xFFA7A96A,
+0xFF9D9D5F,
+0xFF818246,
+0xFF9C9C66,
+0xFF989167,
+0xFF514C24,
+0xFF7B7E4F,
+0xFFA8B17A,
+0xFF909962,
+0xFF646F33,
+0xFF80944F,
+0xFF596D28,
+0xFF667436,
+0xFF3D460F,
+0xFF75764A,
+0xFFA09F73,
+0xFF74743E,
+0xFF72753E,
+0xFFA1A477,
+0xFF939969,
+0xFF929B62,
+0xFF6A7237,
+0xFF767A48,
+0xFF646432,
+0xFFAEAD74,
+0xFF8A884D,
+0xFF706E3B,
+0xFF6D6F3D,
+0xFF909B5F,
+0xFF475518,
+0xFF656E35,
+0xFF4F5525,
+0xFF575836,
+0xFF646047,
+0xFF796959,
+0xFF53402F,
+0xFF3D2D13,
+0xFF594928,
+0xFF63502F,
+0xFF645430,
+0xFF7B6E4C,
+0xFF847F59,
+0xFF5C572F,
+0xFF625D35,
+0xFF746A46,
+0xFF635838,
+0xFF8D8368,
+0xFF656043,
+0xFF797456,
+0xFFA3A07D,
+0xFF64613E,
+0xFF95936D,
+0xFF9B9772,
+0xFFA59F7B,
+0xFF312807,
+0xFFA79C7C,
+0xFF6D5D43,
+0xFF4C3C25,
+0xFF5A483A,
+0xFF3E2B1C,
+0xFF533D26,
+0xFF5B472C,
+0xFF40341E,
+0xFF5D553E,
+0xFF564B35,
+0xFF5C553B,
+0xFF59583A,
+0xFF484B20,
+0xFF909553,
+0xFF888A48,
+0xFF504C1F,
+0xFF817D58,
+0xFF676C44,
+0xFF58622E,
+0xFF515C1A,
+0xFF838E49,
+0xFF666E35,
+0xFF707944,
+0xFF7B8551,
+0xFF535E26,
+0xFF505A1E,
+0xFF4D5519,
+0xFF616834,
+0xFF454D1C,
+0xFF576438,
+0xFF304013,
+0xFF2D3A0E,
+0xFF5C683A,
+0xFF535B32,
+0xFF485124,
+0xFF626C38,
+0xFF848D58,
+0xFF68663D,
+0xFF6D6B42,
+0xFF666C3E,
+0xFF3E4519,
+0xFF464A27,
+0xFF464624,
+0xFF656438,
+0xFF5E5D2D,
+0xFF414014,
+0xFF76774D,
+0xFF504E27,
+0xFF79784A,
+0xFF909155,
+0xFF787F3C,
+0xFF5C6B30,
+0xFF44571F,
+0xFF707E49,
+0xFF5C6D37,
+0xFF4D6028,
+0xFF63783D,
+0xFF4A5E21,
+0xFF4A5C22,
+0xFF283406,
+0xFF616942,
+0xFF555A3A,
+0xFF323918,
+0xFF39431E,
+0xFF455129,
+0xFF495531,
+0xFF36421C,
+0xFF3A421B,
+0xFF4F572E};
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __IMAGE_320x240_ARGB8888_H */
diff --git a/Core/Inc/life_augmented_argb8888.h b/Core/Inc/life_augmented_argb8888.h
new file mode 100644
index 0000000..0429209
--- /dev/null
+++ b/Core/Inc/life_augmented_argb8888.h
@@ -0,0 +1,76839 @@
+/**
+  ******************************************************************************
+  * @file    LCD_DSI/LCD_DSI_VideoMode_SingleBuffer/Inc/life_augmented_argb8888.h
+  * @author  MCD Application Team
+  * @brief   This file contains ARGB8888 image 320x240.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __LIFE_AUGMENTED_ARGB8888_H
+#define __LIFE_AUGMENTED_ARGB8888_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+
+const uint32_t life_augmented_argb8888[76800] =
+{
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFEFFFD,
+0xFFFEFFFD,
+0xFFFCFFFD,
+0xFFFCFFFD,
+0xFFFBFFFD,
+0xFFFBFFFD,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFEFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFEFFFD,
+0xFFFEFFFD,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFDFF,
+0xFFFFFDFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFCFFFD,
+0xFFF9FFFD,
+0xFFFBFFFF,
+0xFFFEFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFEFFFD,
+0xFFFCFFFD,
+0xFFFCFFFD,
+0xFFFBFFFD,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFEFFFB,
+0xFFF9FFFD,
+0xFFFBFFFD,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFDFF,
+0xFFFFFDFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFD,
+0xFFFEFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFEFFFD,
+0xFFFEFFFD,
+0xFFFEFFFD,
+0xFFFEFFFD,
+0xFFFEFFFD,
+0xFFFEFFFD,
+0xFFFEFFFD,
+0xFFFEFFFD,
+0xFFFEFFFD,
+0xFFFEFFFD,
+0xFFFEFFFD,
+0xFFFEFFFD,
+0xFFFEFFFD,
+0xFFFEFFFD,
+0xFFFEFFFD,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFD,
+0xFFFEFFFD,
+0xFFFFFFFD,
+0xFFFEFFFD,
+0xFFFFFFFD,
+0xFFFEFFFD,
+0xFFFFFFFD,
+0xFFFEFFFD,
+0xFFFFFFFD,
+0xFFFEFFFD,
+0xFFFFFFFD,
+0xFFFEFFFD,
+0xFFFFFFFD,
+0xFFFEFFFD,
+0xFFFFFFFD,
+0xFFFEFFFD,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFD,
+0xFFFEFFFD,
+0xFFFEFFFD,
+0xFFFEFFFD,
+0xFFFEFFFD,
+0xFFFEFFFD,
+0xFFFEFFFD,
+0xFFFEFFFD,
+0xFFFEFFFD,
+0xFFFEFFFD,
+0xFFFEFFFD,
+0xFFFEFFFD,
+0xFFFEFFFD,
+0xFFFEFFFD,
+0xFFFEFFFD,
+0xFFFEFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFEFFFD,
+0xFFFBFFFF,
+0xFFFBFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFCFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFEFFFD,
+0xFFFEFFFD,
+0xFFFFFEFF,
+0xFFFFFDFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFDFF,
+0xFFFFFDFF,
+0xFFFFFDFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFDFF,
+0xFFFFFDFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFFFFFB,
+0xFFFFFEFD,
+0xFFFFFFFB,
+0xFFFFFEFD,
+0xFFFFFFFB,
+0xFFFFFEFD,
+0xFFFFFFFB,
+0xFFFFFEFD,
+0xFFFFFFFB,
+0xFFFFFEFD,
+0xFFFFFFFB,
+0xFFFFFEFD,
+0xFFFFFFFB,
+0xFFFFFEFD,
+0xFFFFFFFB,
+0xFFFFFEFD,
+0xFFFFFFFB,
+0xFFFFFEFD,
+0xFFFFFFFB,
+0xFFFFFEFD,
+0xFFFFFFFB,
+0xFFFFFEFD,
+0xFFFFFFFB,
+0xFFFFFEFD,
+0xFFFFFFFB,
+0xFFFFFEFD,
+0xFFFFFFFB,
+0xFFFFFEFD,
+0xFFFFFFFB,
+0xFFFFFEFD,
+0xFFFFFFFB,
+0xFFFFFFFD,
+0xFFFEFFFB,
+0xFFFFFFFD,
+0xFFFEFFFB,
+0xFFFFFFFD,
+0xFFFEFFFB,
+0xFFFFFFFD,
+0xFFFEFFFB,
+0xFFFFFFFD,
+0xFFFEFFFB,
+0xFFFFFFFD,
+0xFFFEFFFB,
+0xFFFFFFFD,
+0xFFFEFFFB,
+0xFFFFFFFD,
+0xFFFEFFFD,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFD,
+0xFFFFFFFF,
+0xFFFEFFFD,
+0xFFFFFFFF,
+0xFFFEFFFD,
+0xFFFFFFFF,
+0xFFFEFFFD,
+0xFFFFFFFF,
+0xFFFEFFFD,
+0xFFFFFFFF,
+0xFFFEFFFD,
+0xFFFFFFFF,
+0xFFFEFFFD,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFD,
+0xFFFCFFFB,
+0xFFFEFFFD,
+0xFFFCFFFB,
+0xFFFEFFFD,
+0xFFFCFFFB,
+0xFFFEFFFD,
+0xFFFCFFFB,
+0xFFFEFFFD,
+0xFFFCFFFB,
+0xFFFEFFFD,
+0xFFFCFFFB,
+0xFFFEFFFD,
+0xFFFCFFFB,
+0xFFFEFFFD,
+0xFFFEFFFB,
+0xFFFFFFFD,
+0xFFFFFFFB,
+0xFFFFFFFD,
+0xFFFFFFFB,
+0xFFFFFFFD,
+0xFFFFFFFB,
+0xFFFFFFFD,
+0xFFFFFFFB,
+0xFFFFFFFD,
+0xFFFFFFFB,
+0xFFFFFFFD,
+0xFFFFFFFB,
+0xFFFFFFFD,
+0xFFFFFFFB,
+0xFFFFFFFD,
+0xFFFFFFFB,
+0xFFFFFFFD,
+0xFFFFFFFB,
+0xFFFFFEFD,
+0xFFFFFFFB,
+0xFFFFFEFD,
+0xFFFFFFFB,
+0xFFFFFEFD,
+0xFFFFFFFB,
+0xFFFFFEFD,
+0xFFFFFFFB,
+0xFFFFFEFD,
+0xFFFFFFFB,
+0xFFFFFEFD,
+0xFFFFFFFB,
+0xFFFFFEFD,
+0xFFFFFFFB,
+0xFFFFFFFD,
+0xFFFFFFFB,
+0xFFFFFFFD,
+0xFFFFFFFB,
+0xFFFFFFFD,
+0xFFFFFFFB,
+0xFFFFFFFD,
+0xFFFFFFFB,
+0xFFFFFFFD,
+0xFFFFFFFB,
+0xFFFFFFFD,
+0xFFFFFFFB,
+0xFFFFFFFD,
+0xFFFFFFFB,
+0xFFFFFFFD,
+0xFFFEFFFD,
+0xFFFBFFFD,
+0xFFFBFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFCFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFDFF,
+0xFFFFFDFF,
+0xFFFFFDFF,
+0xFFFFFDFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFCFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFD,
+0xFFFFFFFF,
+0xFFFEFFFD,
+0xFFFFFFFF,
+0xFFFEFFFD,
+0xFFFFFFFF,
+0xFFFEFFFD,
+0xFFFFFFFF,
+0xFFFEFFFD,
+0xFFFFFFFF,
+0xFFFEFFFD,
+0xFFFFFFFF,
+0xFFFEFFFD,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFEFF,
+0xFFFFFDFF,
+0xFFFFFDFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFFFFFD,
+0xFFFEFFFD,
+0xFFFBFFFD,
+0xFFFBFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFCFFFF,
+0xFFFBFFFF,
+0xFFFCFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFDFF,
+0xFFFFFDFF,
+0xFFFFFDFF,
+0xFFFFFDFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFEFD,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFFFEFF,
+0xFFFFFDFF,
+0xFFFFFDFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFEFFFD,
+0xFFF9FFFD,
+0xFFF9FFFD,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFD,
+0xFFFCFFFD,
+0xFFFBFFFB,
+0xFFFBFFFB,
+0xFFFCFFFB,
+0xFFFCFFFD,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFEFFFD,
+0xFFFEFFFD,
+0xFFFEFFFD,
+0xFFFCFFFD,
+0xFFFCFFFB,
+0xFFFCFFFD,
+0xFFFCFFFD,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFB,
+0xFFFFFFFB,
+0xFFFFFFFD,
+0xFFFEFFFD,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFDFF,
+0xFFFFFDFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFEFFFB,
+0xFFFCFFFD,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFEFFFB,
+0xFFFEFFFA,
+0xFFFCFFFA,
+0xFFFCFFFB,
+0xFFFCFFFD,
+0xFFFCFFFD,
+0xFFFCFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFCFFFF,
+0xFFFCFFFD,
+0xFFFCFFFD,
+0xFFFCFFFD,
+0xFFFCFFFD,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFB,
+0xFFFFFFFB,
+0xFFFEFFFB,
+0xFFFEFFFD,
+0xFFFEFFFD,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFDFF,
+0xFFFFFDFF,
+0xFFFFFDFF,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFEFB,
+0xFFFFFEFB,
+0xFFFFFFFB,
+0xFFFFFFFB,
+0xFFFEFFFD,
+0xFFFCFFFD,
+0xFFFCFFFD,
+0xFFFCFFFD,
+0xFFFBFFFC,
+0xFFFCFFFD,
+0xFFFAFCFB,
+0xFFFCFFFF,
+0xFFFEFFFF,
+0xFFFAFEFD,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFEFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFEFE,
+0xFFFEFEFE,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFEFE,
+0xFFFEFEFE,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFEFE,
+0xFFFDFFFE,
+0xFFFDFFFE,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFEFEFC,
+0xFFFEFEFC,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFDFE,
+0xFFFFFEFC,
+0xFFFEFFFA,
+0xFFFEFFFB,
+0xFFFEFFFB,
+0xFFFEFFFD,
+0xFFF9FBF8,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFDFF,
+0xFFFFFDFF,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFDFD,
+0xFFFFFCFD,
+0xFFFFFEFD,
+0xFFFFFFFD,
+0xFFFEFFFD,
+0xFFFCFFFD,
+0xFFFCFFFD,
+0xFFFCFFFD,
+0xFFFBFFFC,
+0xFFFEFFFD,
+0xFFFEFFFD,
+0xFFFEFFFD,
+0xFFFEFFFD,
+0xFFFEFFFD,
+0xFFFEFFFD,
+0xFFFBFDFA,
+0xFFFFFFFD,
+0xFFFEFEFE,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFAFBFD,
+0xFFFDFEFF,
+0xFFFDFEFF,
+0xFFFFFEFF,
+0xFFFEFEFF,
+0xFFFFFDFF,
+0xFFFFFDFF,
+0xFFFFFDFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFEFC,
+0xFFFEFEFC,
+0xFFFEFEFC,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFEFEFC,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFEFEFE,
+0xFFFDFFFE,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFEFE,
+0xFFFEFEFE,
+0xFFFEFEFE,
+0xFFFEFEFE,
+0xFFFEFEFE,
+0xFFFEFEFE,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFEFE,
+0xFFFDFFFE,
+0xFFFEFEFE,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFEFEFE,
+0xFFFDFFFE,
+0xFFFEFEFE,
+0xFFFDFFFE,
+0xFFFEFEFE,
+0xFFFDFFFE,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFEFF,
+0xFFFFFFFF,
+0xFFFCFEFD,
+0xFFFCFFFD,
+0xFFFBFDFA,
+0xFFFBFDF8,
+0xFFFEFFFD,
+0xFFFEFFFD,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFDFF,
+0xFFFFFCFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFCFFFF,
+0xFFFCFFFD,
+0xFFFCFFFD,
+0xFFFFFFFB,
+0xFFFEFDF9,
+0xFFFFFDFA,
+0xFFFFFEFB,
+0xFFFFFDFA,
+0xFFFDFCFA,
+0xFFFFFEFC,
+0xFFFFFFFB,
+0xFFFFFFFA,
+0xFFFEFFF9,
+0xFFFEFFFA,
+0xFFFEFFFB,
+0xFFFDFFFC,
+0xFFFEFFFD,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFEFEFC,
+0xFFFDFFFC,
+0xFFFEFFFD,
+0xFFFEFFFD,
+0xFFFEFFFD,
+0xFFFDFFFC,
+0xFFFDFFFC,
+0xFFFDFFFC,
+0xFFFDFFFC,
+0xFFFDFFFC,
+0xFFFDFFFC,
+0xFFFDFFFC,
+0xFFFEFFFD,
+0xFFFEFFFD,
+0xFFFDFFFC,
+0xFFFDFFFC,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFDFFFE,
+0xFFFDFFFE,
+0xFFFDFFFE,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFDFEFF,
+0xFFFDFEFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFCFFFF,
+0xFFFBFFFF,
+0xFFFAFFFF,
+0xFFF9FEFF,
+0xFFFEFFFF,
+0xFFFEFFFD,
+0xFFFBFDF8,
+0xFFFEFFFD,
+0xFFFEFFFD,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFCFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFDFF,
+0xFFFFFEFF,
+0xFFFEFFFF,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFCFFFD,
+0xFFFEFFFD,
+0xFFFFFEFC,
+0xFFFFFEFD,
+0xFFFFFDFD,
+0xFFFFFBFB,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFF9FFFD,
+0xFFF7FFFD,
+0xFFF9FFFF,
+0xFFF8FFFF,
+0xFFF7FFFF,
+0xFFF5FFFF,
+0xFFF4FFFF,
+0xFFF2FFFF,
+0xFFF4FFFF,
+0xFFF4FFFF,
+0xFFF3FFFF,
+0xFFF4FFFF,
+0xFFF4FFFF,
+0xFFF5FFFF,
+0xFFF5FFFF,
+0xFFF4FFFF,
+0xFFF5FFFF,
+0xFFF4FFFF,
+0xFFF4FFFF,
+0xFFF4FFFF,
+0xFFF4FFFF,
+0xFFF4FFFF,
+0xFFF4FFFF,
+0xFFF4FFFF,
+0xFFF4FFFF,
+0xFFF4FFFF,
+0xFFF4FFFF,
+0xFFF4FFFF,
+0xFFF4FFFF,
+0xFFF4FFFF,
+0xFFF4FFFF,
+0xFFF4FFFF,
+0xFFF4FFFF,
+0xFFF4FFFF,
+0xFFF4FFFF,
+0xFFF4FFFF,
+0xFFF4FFFF,
+0xFFF4FFFF,
+0xFFF4FFFF,
+0xFFF4FFFF,
+0xFFF4FFFF,
+0xFFF4FFFF,
+0xFFF4FFFF,
+0xFFF4FFFF,
+0xFFF4FFFF,
+0xFFF4FFFF,
+0xFFF4FFFF,
+0xFFF5FFFF,
+0xFFF7FFFF,
+0xFFF7FFFF,
+0xFFF7FFFF,
+0xFFF7FFFF,
+0xFFF7FFFF,
+0xFFF7FFFF,
+0xFFF7FFFF,
+0xFFF7FFFF,
+0xFFF6FFFF,
+0xFFF6FFFF,
+0xFFF6FFFF,
+0xFFF6FFFF,
+0xFFF6FFFF,
+0xFFF6FFFF,
+0xFFF6FFFF,
+0xFFF6FFFF,
+0xFFF4FFFF,
+0xFFF4FFFF,
+0xFFF3FFFF,
+0xFFF3FFFF,
+0xFFF3FFFF,
+0xFFF3FFFF,
+0xFFF3FFFF,
+0xFFF3FFFF,
+0xFFF4FFFF,
+0xFFF4FFFF,
+0xFFF4FFFF,
+0xFFF3FFFF,
+0xFFF3FFFF,
+0xFFF3FFFF,
+0xFFF3FFFF,
+0xFFF3FFFF,
+0xFFF4FFFF,
+0xFFF4FFFF,
+0xFFF5FFFF,
+0xFFF4FFFF,
+0xFFF5FFFF,
+0xFFF4FFFF,
+0xFFF5FFFF,
+0xFFF4FFFF,
+0xFFF5FFFF,
+0xFFF4FFFF,
+0xFFF5FFFF,
+0xFFF4FFFF,
+0xFFF5FFFF,
+0xFFF4FFFF,
+0xFFF5FFFF,
+0xFFF4FFFF,
+0xFFF5FFFF,
+0xFFF4FFFF,
+0xFFF5FFFF,
+0xFFF4FFFF,
+0xFFF5FFFF,
+0xFFF4FFFF,
+0xFFF5FFFF,
+0xFFF4FFFF,
+0xFFF5FFFF,
+0xFFF4FFFF,
+0xFFF5FFFF,
+0xFFF4FFFF,
+0xFFF5FFFF,
+0xFFF4FFFF,
+0xFFF5FFFF,
+0xFFF4FFFF,
+0xFFF4FFFF,
+0xFFF4FFFF,
+0xFFF4FFFF,
+0xFFF4FFFF,
+0xFFF4FFFF,
+0xFFF4FFFF,
+0xFFF4FFFF,
+0xFFF4FFFF,
+0xFFF4FFFF,
+0xFFF4FFFF,
+0xFFF4FFFF,
+0xFFF4FFFF,
+0xFFF4FFFF,
+0xFFF4FFFF,
+0xFFF4FFFF,
+0xFFF4FFFF,
+0xFFF4FFFF,
+0xFFF4FFFF,
+0xFFF4FFFF,
+0xFFF4FFFF,
+0xFFF4FFFF,
+0xFFF4FFFF,
+0xFFF4FFFF,
+0xFFF4FFFF,
+0xFFF4FFFF,
+0xFFF4FFFF,
+0xFFF4FFFF,
+0xFFF4FFFF,
+0xFFF4FFFF,
+0xFFF4FFFF,
+0xFFF4FFFF,
+0xFFF4FFFF,
+0xFFF5FFFF,
+0xFFF5FFFF,
+0xFFF5FFFF,
+0xFFF5FFFF,
+0xFFF5FFFF,
+0xFFF5FFFF,
+0xFFF5FFFF,
+0xFFF5FFFF,
+0xFFF4FFFF,
+0xFFF4FFFF,
+0xFFF4FFFF,
+0xFFF4FFFF,
+0xFFF4FFFF,
+0xFFF4FFFF,
+0xFFF4FFFF,
+0xFFF5FFFF,
+0xFFF5FFFF,
+0xFFF4FFFF,
+0xFFF4FFFF,
+0xFFF4FFFF,
+0xFFF4FFFF,
+0xFFF4FFFF,
+0xFFF4FFFF,
+0xFFF4FFFF,
+0xFFF4FFFF,
+0xFFF4FFFF,
+0xFFF4FFFF,
+0xFFF4FFFF,
+0xFFF4FFFF,
+0xFFF3FFFF,
+0xFFF3FFFF,
+0xFFF3FFFF,
+0xFFF5FFFF,
+0xFFF5FFFF,
+0xFFF5FFFF,
+0xFFF4FFFF,
+0xFFF4FFFF,
+0xFFF4FFFF,
+0xFFF4FFFF,
+0xFFF4FFFF,
+0xFFF5FFFF,
+0xFFF5FFFF,
+0xFFF5FFFF,
+0xFFF5FFFF,
+0xFFF4FFFF,
+0xFFF4FFFF,
+0xFFF4FFFF,
+0xFFF3FFFF,
+0xFFF1FFFF,
+0xFFEDFFFF,
+0xFFF2FFFF,
+0xFFF7FFFF,
+0xFFF8FDFF,
+0xFFFEFFFF,
+0xFFFEFFFD,
+0xFFFAFCF7,
+0xFFFEFFFD,
+0xFFFEFFFD,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFBFFFF,
+0xFFFCFFFF,
+0xFFFEFFFD,
+0xFFFFFFFD,
+0xFFFFFBFA,
+0xFFFFFDFF,
+0xFFFFFDFF,
+0xFFFFFDFF,
+0xFFFFFEFF,
+0xFFF7FAFF,
+0xFFFBFFFF,
+0xFFF6FFFF,
+0xFFF1FFFF,
+0xFFF0FFFF,
+0xFFEDFFFF,
+0xFFD6EDFB,
+0xFFBAD4E3,
+0xFFA5C2D2,
+0xFF92B3C4,
+0xFF7FA4B6,
+0xFF769CAF,
+0xFF739CAE,
+0xFF709BAC,
+0xFF709BAC,
+0xFF719CAD,
+0xFF6F9DAC,
+0xFF6F9DAD,
+0xFF6F9DAD,
+0xFF719AAE,
+0xFF7399B0,
+0xFF7399B0,
+0xFF7399B0,
+0xFF7399B0,
+0xFF7399B0,
+0xFF7399B0,
+0xFF7399B0,
+0xFF7399B0,
+0xFF7399B0,
+0xFF7399B0,
+0xFF749AB1,
+0xFF759BB2,
+0xFF759BB2,
+0xFF759BB2,
+0xFF759BB2,
+0xFF749AB1,
+0xFF749AB1,
+0xFF749AB1,
+0xFF749AB1,
+0xFF759BB2,
+0xFF759BB2,
+0xFF759BB2,
+0xFF759BB2,
+0xFF769CB3,
+0xFF769CB3,
+0xFF769CB3,
+0xFF769CB3,
+0xFF769CB3,
+0xFF769CB3,
+0xFF769CB3,
+0xFF769CB3,
+0xFF769CB1,
+0xFF769CB1,
+0xFF769CB1,
+0xFF769CB1,
+0xFF769CB1,
+0xFF769CB1,
+0xFF769CB1,
+0xFF769CB1,
+0xFF799FB4,
+0xFF799FB4,
+0xFF799FB4,
+0xFF799FB4,
+0xFF799FB4,
+0xFF799FB4,
+0xFF799FB4,
+0xFF769FB3,
+0xFF769FB5,
+0xFF76A0B6,
+0xFF76A0B6,
+0xFF77A1B7,
+0xFF77A1B7,
+0xFF78A2B8,
+0xFF78A2B8,
+0xFF78A2B8,
+0xFF78A2B8,
+0xFF78A2B8,
+0xFF78A2B8,
+0xFF78A2B8,
+0xFF78A2B8,
+0xFF78A2B8,
+0xFF78A2B8,
+0xFF78A2B8,
+0xFF78A2B8,
+0xFF78A2B8,
+0xFF7AA3B9,
+0xFF79A3B9,
+0xFF7AA3B9,
+0xFF79A3B9,
+0xFF7BA4BA,
+0xFF7AA4BA,
+0xFF7AA3B9,
+0xFF79A3B9,
+0xFF7AA3B9,
+0xFF79A3B9,
+0xFF7AA3B9,
+0xFF7AA4BA,
+0xFF7BA4BA,
+0xFF7AA4BA,
+0xFF7BA4BA,
+0xFF7AA5B8,
+0xFF7BA4BA,
+0xFF7AA5B8,
+0xFF7BA4BA,
+0xFF7AA5B8,
+0xFF7BA4BA,
+0xFF7AA5B8,
+0xFF7CA5BB,
+0xFF7BA6B9,
+0xFF7CA5BB,
+0xFF7BA6B9,
+0xFF7CA5BB,
+0xFF7BA6B9,
+0xFF7CA5BB,
+0xFF7BA5BB,
+0xFF7CA6BC,
+0xFF7CA6BC,
+0xFF7CA6BC,
+0xFF7CA6BC,
+0xFF7CA6BC,
+0xFF7CA6BC,
+0xFF7CA6BC,
+0xFF7CA6BC,
+0xFF7DA7BD,
+0xFF7DA7BD,
+0xFF7DA7BD,
+0xFF7DA7BD,
+0xFF7DA7BD,
+0xFF7DA7BD,
+0xFF7DA7BD,
+0xFF7DA7BD,
+0xFF7EA9BC,
+0xFF7EA9BC,
+0xFF7EA9BC,
+0xFF7EA9BC,
+0xFF7EA9BC,
+0xFF7EA9BC,
+0xFF7EA9BC,
+0xFF7DA8BB,
+0xFF7EA9BC,
+0xFF7EA9BC,
+0xFF7EA9BC,
+0xFF7EA9BC,
+0xFF7FAABD,
+0xFF7FAABD,
+0xFF7FAABD,
+0xFF80ABBE,
+0xFF80A9BF,
+0xFF80A9BF,
+0xFF80A9BF,
+0xFF80A9BF,
+0xFF80A9BF,
+0xFF81AAC0,
+0xFF81AAC0,
+0xFF81AAC0,
+0xFF83ACC2,
+0xFF83ACC2,
+0xFF83ACC2,
+0xFF83ACC2,
+0xFF83ACC2,
+0xFF83ACC2,
+0xFF83ACC2,
+0xFF83ACC2,
+0xFF85ABC2,
+0xFF85ABC2,
+0xFF85ABC2,
+0xFF86ACC3,
+0xFF86ACC3,
+0xFF86ACC3,
+0xFF86ACC3,
+0xFF86ACC3,
+0xFF86ACC3,
+0xFF86ACC3,
+0xFF86ACC3,
+0xFF86ACC3,
+0xFF86ACC3,
+0xFF87ADC4,
+0xFF87ADC4,
+0xFF85AEC4,
+0xFF84ADC1,
+0xFF84ADC1,
+0xFF84ADC1,
+0xFF84ADC1,
+0xFF84ADC1,
+0xFF84ADC1,
+0xFF84ADC1,
+0xFF84ADC1,
+0xFF85AEC2,
+0xFF85AEC2,
+0xFF85AEC2,
+0xFF85AEC2,
+0xFF85AEC2,
+0xFF85AEC2,
+0xFF85AEC2,
+0xFF84ADC1,
+0xFF85AEC4,
+0xFF88AEC1,
+0xFF88A9B8,
+0xFFBFD7E1,
+0xFFF3FEFF,
+0xFFFBFFFF,
+0xFFFAFCF9,
+0xFFFEFFFB,
+0xFFFEFFFB,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFDFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFCFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFCF7FB,
+0xFFFFFCFF,
+0xFFFEFEFF,
+0xFFF7FFFF,
+0xFFF1FFFF,
+0xFFF1FFFF,
+0xFFD8EFFD,
+0xFFA3BFD4,
+0xFF7999B0,
+0xFF5B7E94,
+0xFF5B8198,
+0xFF5D859F,
+0xFF56829D,
+0xFF5685A1,
+0xFF5B8EAB,
+0xFF588EAA,
+0xFF558EAB,
+0xFF558EAC,
+0xFF528EAA,
+0xFF538FAB,
+0xFF528FAB,
+0xFF528FAB,
+0xFF528FAB,
+0xFF5790AE,
+0xFF578FB0,
+0xFF588EB0,
+0xFF578FB0,
+0xFF588EB0,
+0xFF578FB0,
+0xFF578DAF,
+0xFF568EAF,
+0xFF588EB0,
+0xFF578FB0,
+0xFF588EB0,
+0xFF5890B1,
+0xFF5A90B2,
+0xFF5991B2,
+0xFF5A90B2,
+0xFF5991B2,
+0xFF5991B2,
+0xFF5991B2,
+0xFF5991B2,
+0xFF5991B2,
+0xFF5A92B3,
+0xFF5A92B3,
+0xFF5A92B3,
+0xFF5A92B3,
+0xFF5A92B3,
+0xFF5A92B3,
+0xFF5A92B3,
+0xFF5A92B3,
+0xFF5B93B4,
+0xFF5B93B4,
+0xFF5B93B4,
+0xFF5B93B4,
+0xFF5B94B2,
+0xFF5B94B2,
+0xFF5B94B2,
+0xFF5B94B2,
+0xFF5B94B2,
+0xFF5B94B2,
+0xFF5B94B2,
+0xFF5C95B3,
+0xFF5B94B2,
+0xFF5B94B2,
+0xFF5B94B2,
+0xFF5B94B2,
+0xFF5B94B2,
+0xFF5B94B2,
+0xFF5B94B2,
+0xFF5B94B2,
+0xFF5B94B2,
+0xFF5B94B2,
+0xFF5B94B2,
+0xFF5C95B3,
+0xFF5C95B3,
+0xFF5C95B3,
+0xFF5C95B3,
+0xFF5C95B3,
+0xFF5C95B3,
+0xFF5C95B3,
+0xFF5C95B3,
+0xFF5C95B3,
+0xFF5D96B4,
+0xFF5D96B4,
+0xFF5D96B4,
+0xFF5D96B4,
+0xFF5D96B4,
+0xFF5D96B4,
+0xFF5D96B4,
+0xFF5D96B4,
+0xFF5E97B5,
+0xFF5E97B5,
+0xFF5E97B5,
+0xFF5E97B5,
+0xFF5E97B5,
+0xFF5E97B5,
+0xFF5E97B5,
+0xFF5E97B5,
+0xFF5E97B5,
+0xFF5E97B5,
+0xFF5F98B6,
+0xFF5F98B5,
+0xFF5F98B5,
+0xFF5F98B5,
+0xFF5F98B5,
+0xFF5F98B5,
+0xFF5F98B5,
+0xFF5F98B5,
+0xFF5F98B5,
+0xFF5F98B5,
+0xFF6099B6,
+0xFF6099B6,
+0xFF6099B6,
+0xFF6099B6,
+0xFF619AB7,
+0xFF619AB7,
+0xFF619AB7,
+0xFF619AB7,
+0xFF629BB9,
+0xFF629BB9,
+0xFF629BB9,
+0xFF629BB9,
+0xFF629BB9,
+0xFF639CBA,
+0xFF639CBA,
+0xFF639CBA,
+0xFF639CBA,
+0xFF639CBA,
+0xFF639CBA,
+0xFF649DBB,
+0xFF649DBB,
+0xFF649DBB,
+0xFF659EBC,
+0xFF659EBC,
+0xFF639EBC,
+0xFF639EBC,
+0xFF639EBC,
+0xFF639EBC,
+0xFF639EBC,
+0xFF649FBD,
+0xFF649FBD,
+0xFF649FBD,
+0xFF65A0BE,
+0xFF65A0BE,
+0xFF65A0BE,
+0xFF65A0BE,
+0xFF65A0BE,
+0xFF65A0BE,
+0xFF66A1BF,
+0xFF66A1BF,
+0xFF66A1C1,
+0xFF66A1C1,
+0xFF66A1C1,
+0xFF66A1C1,
+0xFF66A1C1,
+0xFF66A1C1,
+0xFF66A1C1,
+0xFF66A1C1,
+0xFF65A0C0,
+0xFF65A0C0,
+0xFF65A0C0,
+0xFF66A1C1,
+0xFF66A1C1,
+0xFF66A1C1,
+0xFF66A1C1,
+0xFF67A2C2,
+0xFF69A1C2,
+0xFF69A1C2,
+0xFF69A1C2,
+0xFF69A1C2,
+0xFF69A1C2,
+0xFF6AA2C3,
+0xFF6AA2C3,
+0xFF6AA2C3,
+0xFF6AA2C3,
+0xFF6AA2C3,
+0xFF6AA2C3,
+0xFF6AA2C3,
+0xFF6BA3C4,
+0xFF6BA3C4,
+0xFF6CA4C5,
+0xFF6CA4C5,
+0xFF6BA4C2,
+0xFF69A4C2,
+0xFF69A4C2,
+0xFF6AA5C3,
+0xFF6AA5C3,
+0xFF6AA5C3,
+0xFF6AA5C3,
+0xFF6BA6C4,
+0xFF6AA5C3,
+0xFF6AA5C3,
+0xFF6BA6C4,
+0xFF6BA6C4,
+0xFF6BA6C4,
+0xFF6BA6C4,
+0xFF6CA7C5,
+0xFF6CA7C5,
+0xFF6FA8C5,
+0xFF6BA1B9,
+0xFF73A2B4,
+0xFF6D8F9B,
+0xFFE2F3FD,
+0xFFFBFFFF,
+0xFFFDFFFE,
+0xFFFEFFFA,
+0xFFFFFFFB,
+0xFFFFFFFB,
+0xFFFFFEFD,
+0xFFFFFEFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFEFF,
+0xFFFFFDFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFEFFFD,
+0xFFFEFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFDFEFF,
+0xFFF9FFFF,
+0xFFF3FFFF,
+0xFFEAFFFF,
+0xFFA3C3D2,
+0xFF5F8695,
+0xFF507B8E,
+0xFF55839A,
+0xFF56859F,
+0xFF5688A3,
+0xFF5689A6,
+0xFF558AA9,
+0xFF578EAD,
+0xFF528DAF,
+0xFF4B87AB,
+0xFF4B89AE,
+0xFF4B89AE,
+0xFF4B89B0,
+0xFF4C8AB1,
+0xFF4C8AB1,
+0xFF4C8AAF,
+0xFF4C8AAF,
+0xFF4C8AAF,
+0xFF4B8BB1,
+0xFF4A8BB1,
+0xFF4B8BB1,
+0xFF4A8BB1,
+0xFF4B8BB1,
+0xFF4A8BB1,
+0xFF4B8BB1,
+0xFF4A8BB1,
+0xFF4D8DB3,
+0xFF4C8DB3,
+0xFF4D8DB3,
+0xFF4C8DB3,
+0xFF4D8DB3,
+0xFF4C8DB3,
+0xFF4D8DB3,
+0xFF4B8CB2,
+0xFF4C8DB5,
+0xFF4C8DB5,
+0xFF4C8DB5,
+0xFF4C8DB5,
+0xFF4C8DB5,
+0xFF4D8EB6,
+0xFF4D8EB6,
+0xFF4D8EB6,
+0xFF4C8DB5,
+0xFF4C8DB5,
+0xFF4D8EB6,
+0xFF4D8EB6,
+0xFF4E8FB7,
+0xFF4E8FB7,
+0xFF4F90B8,
+0xFF4F90B6,
+0xFF5191B5,
+0xFF5191B5,
+0xFF5191B5,
+0xFF5292B6,
+0xFF5292B6,
+0xFF5292B6,
+0xFF5393B7,
+0xFF5393B7,
+0xFF5393B7,
+0xFF5393B7,
+0xFF5494B8,
+0xFF5494B8,
+0xFF5494B8,
+0xFF5595B9,
+0xFF5595B9,
+0xFF5694B9,
+0xFF5995B9,
+0xFF5A94B9,
+0xFF5A94B9,
+0xFF5A94B9,
+0xFF5A94B9,
+0xFF5A94B9,
+0xFF5A94B9,
+0xFF5A94B9,
+0xFF5A94B9,
+0xFF5B95BA,
+0xFF5B95BA,
+0xFF5B95BA,
+0xFF5C96BB,
+0xFF5C96BB,
+0xFF5D97BC,
+0xFF5D98BA,
+0xFF5D98BA,
+0xFF5D98B8,
+0xFF5D98B8,
+0xFF5E99B9,
+0xFF5E99B9,
+0xFF5E99B9,
+0xFF5F9ABA,
+0xFF5F9ABA,
+0xFF5E99B9,
+0xFF5E99B9,
+0xFF5F9ABA,
+0xFF5F9ABA,
+0xFF609BBB,
+0xFF609BBB,
+0xFF619CBC,
+0xFF619CBC,
+0xFF619CBC,
+0xFF619CBA,
+0xFF619CBA,
+0xFF619CBA,
+0xFF619CBA,
+0xFF619CBA,
+0xFF619CBA,
+0xFF619CBA,
+0xFF619CBA,
+0xFF619CBA,
+0xFF619CBA,
+0xFF619CBA,
+0xFF619CBA,
+0xFF619CBA,
+0xFF619CBA,
+0xFF619CBA,
+0xFF609BBB,
+0xFF609BBB,
+0xFF609BBB,
+0xFF609BBB,
+0xFF609BBB,
+0xFF609BBB,
+0xFF609BBB,
+0xFF609BBB,
+0xFF609BBB,
+0xFF609BBB,
+0xFF609BBB,
+0xFF609BBB,
+0xFF609BBB,
+0xFF609BBB,
+0xFF609BBB,
+0xFF5F9BBD,
+0xFF5D9CBF,
+0xFF5C9ABF,
+0xFF5C9ABF,
+0xFF5C9ABF,
+0xFF5C9ABF,
+0xFF5C9ABF,
+0xFF5C9ABF,
+0xFF5C9ABF,
+0xFF5C9ABF,
+0xFF5C9ABF,
+0xFF5C9ABF,
+0xFF5C9ABF,
+0xFF5C9ABF,
+0xFF5C9ABF,
+0xFF5C9ABF,
+0xFF5B9BBF,
+0xFF5A9AC0,
+0xFF599AC0,
+0xFF599AC0,
+0xFF599AC0,
+0xFF599AC0,
+0xFF5899BF,
+0xFF5899BF,
+0xFF5899BF,
+0xFF5B9CC2,
+0xFF5A9BC1,
+0xFF5A9BC1,
+0xFF5A9BC1,
+0xFF5A9BC1,
+0xFF5A9BC1,
+0xFF599AC0,
+0xFF599AC0,
+0xFF5A9BC3,
+0xFF5A9BC3,
+0xFF5A9BC3,
+0xFF5A9BC3,
+0xFF5A9BC3,
+0xFF599AC2,
+0xFF599AC2,
+0xFF599AC2,
+0xFF599AC2,
+0xFF599AC2,
+0xFF599AC2,
+0xFF599AC2,
+0xFF599AC2,
+0xFF599AC2,
+0xFF599AC2,
+0xFF599AC0,
+0xFF5A9ABE,
+0xFF5A9ABE,
+0xFF5A9ABE,
+0xFF5A9ABE,
+0xFF5A9ABE,
+0xFF5A9ABE,
+0xFF5A9ABE,
+0xFF5A9ABE,
+0xFF5A9ABE,
+0xFF5A9ABE,
+0xFF5999BD,
+0xFF5999BD,
+0xFF5999BD,
+0xFF5999BD,
+0xFF5999BD,
+0xFF589ABD,
+0xFF599BBE,
+0xFF61A0BF,
+0xFF71A7BF,
+0xFF7197AA,
+0xFFD0E2F0,
+0xFFFBFFFF,
+0xFFFCFCFE,
+0xFFFFFFFD,
+0xFFFFFFFB,
+0xFFFFFFFB,
+0xFFFFFEFD,
+0xFFFFFFFD,
+0xFFFBFFFF,
+0xFFFBFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFB,
+0xFFFFFFFB,
+0xFFFFFFFB,
+0xFFFFFFFB,
+0xFFFEFFFF,
+0xFFFCFFFF,
+0xFFF6FFFF,
+0xFFF2FFFF,
+0xFFE2F8FF,
+0xFF89A6B8,
+0xFF4E7487,
+0xFF4C7B8F,
+0xFF53879D,
+0xFF4F87A0,
+0xFF518AA7,
+0xFF4C84A5,
+0xFF4782A2,
+0xFF427EA0,
+0xFF3D799D,
+0xFF39779C,
+0xFF39799F,
+0xFF3877A0,
+0xFF3778A0,
+0xFF3879A3,
+0xFF3A79A5,
+0xFF3B7AA6,
+0xFF3A79A4,
+0xFF3A79A4,
+0xFF3B7AA5,
+0xFF3B7CA6,
+0xFF397CA6,
+0xFF397EA7,
+0xFF397EA7,
+0xFF3A7FA8,
+0xFF3B80A9,
+0xFF3C81AA,
+0xFF3C81AB,
+0xFF3D82AC,
+0xFF3D82AC,
+0xFF3B82AC,
+0xFF3B82AC,
+0xFF3C83AD,
+0xFF3D84AE,
+0xFF3E85AF,
+0xFF3E85AF,
+0xFF3E85AF,
+0xFF3F88B3,
+0xFF3F88B3,
+0xFF3F88B3,
+0xFF3F88B3,
+0xFF3F88B3,
+0xFF4089B4,
+0xFF4089B4,
+0xFF4089B4,
+0xFF418AB5,
+0xFF428BB6,
+0xFF428BB6,
+0xFF438CB7,
+0xFF448DB8,
+0xFF468DB7,
+0xFF478EB8,
+0xFF478EB8,
+0xFF4B90B9,
+0xFF4B90B9,
+0xFF4D90BA,
+0xFF4C91BA,
+0xFF4E91BB,
+0xFF4D92B9,
+0xFF4F92BC,
+0xFF4F93BA,
+0xFF4F92BC,
+0xFF4F93BA,
+0xFF5094BB,
+0xFF5195BC,
+0xFF5195BC,
+0xFF5296BD,
+0xFF5397BE,
+0xFF5596BE,
+0xFF5696BC,
+0xFF5795BC,
+0xFF5896BD,
+0xFF5997BE,
+0xFF5A98BF,
+0xFF5B99C0,
+0xFF5C9AC1,
+0xFF5D9BC0,
+0xFF5D9BC2,
+0xFF5D9BC0,
+0xFF5D9BC0,
+0xFF5E9CC1,
+0xFF5F9DC2,
+0xFF5F9DC2,
+0xFF609EC3,
+0xFF609EC3,
+0xFF61A0C3,
+0xFF61A0C3,
+0xFF639FC3,
+0xFF62A1C4,
+0xFF64A0C4,
+0xFF65A1C5,
+0xFF65A1C5,
+0xFF65A1C3,
+0xFF67A3C5,
+0xFF67A3C5,
+0xFF67A3C5,
+0xFF68A4C6,
+0xFF69A5C7,
+0xFF69A5C7,
+0xFF6AA6C8,
+0xFF6AA6C8,
+0xFF6AA7C6,
+0xFF6AA7C6,
+0xFF6AA7C6,
+0xFF6AA7C6,
+0xFF6AA7C6,
+0xFF6AA7C6,
+0xFF6AA7C6,
+0xFF6AA7C6,
+0xFF6AA6C8,
+0xFF69A6C5,
+0xFF69A5C7,
+0xFF68A5C4,
+0xFF67A3C5,
+0xFF67A4C3,
+0xFF66A2C4,
+0xFF66A2C4,
+0xFF66A2C4,
+0xFF63A2C3,
+0xFF65A1C3,
+0xFF62A1C2,
+0xFF61A0C3,
+0xFF61A0C1,
+0xFF609FC2,
+0xFF609FC2,
+0xFF609FC2,
+0xFF609FC2,
+0xFF609FC2,
+0xFF5F9EC1,
+0xFF5E9DC0,
+0xFF5E9DC0,
+0xFF5D9CBF,
+0xFF5D9BC0,
+0xFF5B9BC1,
+0xFF5A99C2,
+0xFF5998C1,
+0xFF5998C1,
+0xFF5897C0,
+0xFF5796BF,
+0xFF5695BE,
+0xFF5596BE,
+0xFF5594BF,
+0xFF5394BE,
+0xFF5493BE,
+0xFF5293BD,
+0xFF5293BD,
+0xFF5293BD,
+0xFF5293BD,
+0xFF5192BC,
+0xFF4D92BB,
+0xFF4A92BA,
+0xFF4C91BA,
+0xFF4991B9,
+0xFF4B90B9,
+0xFF4890B8,
+0xFF4A8FB9,
+0xFF488FB9,
+0xFF458CB6,
+0xFF458CB6,
+0xFF448BB5,
+0xFF438AB4,
+0xFF4289B3,
+0xFF4188B2,
+0xFF4087B1,
+0xFF3F88B1,
+0xFF3E87B2,
+0xFF3E87B2,
+0xFF3E87B2,
+0xFF3D86B1,
+0xFF3D86B1,
+0xFF3C85B0,
+0xFF3C85B0,
+0xFF3C85B0,
+0xFF3C85B0,
+0xFF3B84AF,
+0xFF3B84AF,
+0xFF3A83AE,
+0xFF3A83AE,
+0xFF3982AD,
+0xFF3982AD,
+0xFF3980AA,
+0xFF3B80AA,
+0xFF3A7FA8,
+0xFF3A7FA8,
+0xFF397EA7,
+0xFF397CA6,
+0xFF377CA5,
+0xFF377CA5,
+0xFF377CA5,
+0xFF367BA4,
+0xFF367BA4,
+0xFF3679A3,
+0xFF3579A0,
+0xFF3477A1,
+0xFF3477A1,
+0xFF3376A0,
+0xFF32779E,
+0xFF30759C,
+0xFF64A5C5,
+0xFF6599B1,
+0xFF7093A6,
+0xFFF4FFFF,
+0xFFFBFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFCFFFD,
+0xFFFBFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFCFCFA,
+0xFFFFFFFB,
+0xFFFEFDF8,
+0xFFFEFFFD,
+0xFFF9FFFF,
+0xFFF4FFFF,
+0xFFECFFFF,
+0xFF84A5B6,
+0xFF467088,
+0xFF487A95,
+0xFF4A819F,
+0xFF4883A1,
+0xFF4784A3,
+0xFF3B7A9B,
+0xFF38769B,
+0xFF38769D,
+0xFF37779D,
+0xFF37779D,
+0xFF38789E,
+0xFF39799F,
+0xFF397AA2,
+0xFF397AA2,
+0xFF397AA2,
+0xFF397AA2,
+0xFF3A7BA5,
+0xFF3B7CA6,
+0xFF3B7BA7,
+0xFF3B7BA7,
+0xFF3A7DA8,
+0xFF3B7EA9,
+0xFF3B7EA9,
+0xFF3C7FAA,
+0xFF3B80AA,
+0xFF3C81AB,
+0xFF3C81AB,
+0xFF3C81AB,
+0xFF3B82AE,
+0xFF3B82AE,
+0xFF3D84B0,
+0xFF3C85B0,
+0xFF3C85B0,
+0xFF3D86B1,
+0xFF3E87B2,
+0xFF3E87B2,
+0xFF3D88B2,
+0xFF3D87B4,
+0xFF3D8AB8,
+0xFF3C88B9,
+0xFF3C88B9,
+0xFF3D89BA,
+0xFF3D8BBB,
+0xFF3D8BBB,
+0xFF3D8BB9,
+0xFF3D8BB9,
+0xFF3F8CBA,
+0xFF408DBB,
+0xFF448EBB,
+0xFF428CB9,
+0xFF458FBC,
+0xFF458EB9,
+0xFF4790BB,
+0xFF478EBA,
+0xFF4990BA,
+0xFF4990BA,
+0xFF4C91BB,
+0xFF4A91BB,
+0xFF4D92BC,
+0xFF4B93BB,
+0xFF4E93BD,
+0xFF4E93BC,
+0xFF4E93BD,
+0xFF5095BE,
+0xFF4F94BD,
+0xFF5297C0,
+0xFF5093BD,
+0xFF5396C0,
+0xFF5495BF,
+0xFF5497C1,
+0xFF5498BF,
+0xFF5498BF,
+0xFF5498BF,
+0xFF5599C0,
+0xFF569AC1,
+0xFF579BC2,
+0xFF5A9BC3,
+0xFF5B9CC2,
+0xFF5C9BC4,
+0xFF5D9DC3,
+0xFF5D9DC3,
+0xFF5C9CC2,
+0xFF5D9DC3,
+0xFF5F9FC5,
+0xFF5F9FC5,
+0xFF5E9EC4,
+0xFF5F9FC3,
+0xFF60A0C4,
+0xFF619FC4,
+0xFF60A0C4,
+0xFF62A0C5,
+0xFF63A1C6,
+0xFF63A1C6,
+0xFF64A3C6,
+0xFF65A4C7,
+0xFF65A4C7,
+0xFF67A3C7,
+0xFF67A3C7,
+0xFF69A5C7,
+0xFF6AA6C8,
+0xFF6BA6C8,
+0xFF69A4C6,
+0xFF69A5C7,
+0xFF69A5C7,
+0xFF6AA6C8,
+0xFF6AA6C8,
+0xFF6AA6C8,
+0xFF6AA6C8,
+0xFF69A5C7,
+0xFF69A5C7,
+0xFF67A6C9,
+0xFF67A6C7,
+0xFF67A6C9,
+0xFF66A5C6,
+0xFF66A5C8,
+0xFF66A5C6,
+0xFF65A4C7,
+0xFF64A3C6,
+0xFF63A2C5,
+0xFF63A3C6,
+0xFF64A3C6,
+0xFF62A2C5,
+0xFF60A0C4,
+0xFF60A0C3,
+0xFF60A0C4,
+0xFF60A0C4,
+0xFF5F9FC3,
+0xFF5F9FC3,
+0xFF5E9EC2,
+0xFF5E9EC2,
+0xFF5C9EC1,
+0xFF5C9EC1,
+0xFF5B9CC2,
+0xFF5B9CC2,
+0xFF5B9CC4,
+0xFF5A9BC5,
+0xFF599AC4,
+0xFF5899C3,
+0xFF5798C2,
+0xFF5798C2,
+0xFF5697C1,
+0xFF5396C0,
+0xFF5696C2,
+0xFF5396C1,
+0xFF5494C0,
+0xFF5295C0,
+0xFF5194BF,
+0xFF5194BF,
+0xFF5093C0,
+0xFF4E92BF,
+0xFF4C93BD,
+0xFF4B94BD,
+0xFF4B92BC,
+0xFF4A93BC,
+0xFF4A91BB,
+0xFF4891BA,
+0xFF4990BC,
+0xFF4891BC,
+0xFF468FBA,
+0xFF468FBA,
+0xFF468FBA,
+0xFF458EB9,
+0xFF438DBA,
+0xFF428CB9,
+0xFF3F8CB8,
+0xFF3F8CB8,
+0xFF3E8BB9,
+0xFF3D8BB9,
+0xFF3C8AB8,
+0xFF3C8AB8,
+0xFF3C89B7,
+0xFF3B88B6,
+0xFF3D87B6,
+0xFF3E88B7,
+0xFF3D87B4,
+0xFF3D87B4,
+0xFF3D87B4,
+0xFF3C86B3,
+0xFF3B85B2,
+0xFF3B85B2,
+0xFF3B85B2,
+0xFF3B85B2,
+0xFF3B84B1,
+0xFF3B82B0,
+0xFF3A81AD,
+0xFF3A81AD,
+0xFF3C81AB,
+0xFF3980AA,
+0xFF3980AC,
+0xFF387FAB,
+0xFF367DA9,
+0xFF387FAB,
+0xFF387DA7,
+0xFF3A7FA8,
+0xFF387BA6,
+0xFF387BA6,
+0xFF3A7FA9,
+0xFF31769F,
+0xFF468AAF,
+0xFF66A1BF,
+0xFF6691A4,
+0xFFACC6D3,
+0xFFF8FFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFDFBFE,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFB,
+0xFFFFFFFB,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFDFDFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFEFFFD,
+0xFFFCFFFF,
+0xFFF7FFFF,
+0xFFF2FFFF,
+0xFFB0CBD6,
+0xFF4D7083,
+0xFF46748B,
+0xFF457B97,
+0xFF4580A0,
+0xFF407FA2,
+0xFF39799C,
+0xFF36769A,
+0xFF36769A,
+0xFF36779F,
+0xFF3677A1,
+0xFF36779F,
+0xFF3778A0,
+0xFF3778A0,
+0xFF3879A1,
+0xFF397AA2,
+0xFF397AA2,
+0xFF397AA2,
+0xFF397AA2,
+0xFF3A7BA5,
+0xFF397CA6,
+0xFF397CA7,
+0xFF397CA7,
+0xFF397EA8,
+0xFF3A7FA9,
+0xFF3A7FA9,
+0xFF3A7FA9,
+0xFF3B7FAC,
+0xFF3A81AD,
+0xFF3C80AD,
+0xFF3A81AD,
+0xFF3B82B0,
+0xFF3A83B0,
+0xFF3C85B2,
+0xFF3B85B2,
+0xFF3B85B4,
+0xFF3A87B5,
+0xFF3A87B5,
+0xFF3B88B6,
+0xFF3B88B6,
+0xFF3A88B6,
+0xFF3C8ABB,
+0xFF3B89BA,
+0xFF3B89BA,
+0xFF3A8ABB,
+0xFF3B8BBC,
+0xFF3B8BBC,
+0xFF3B8BBC,
+0xFF3B8CBB,
+0xFF3E8CBC,
+0xFF3F8DBD,
+0xFF428EBF,
+0xFF408DBB,
+0xFF458FBE,
+0xFF448EBB,
+0xFF4790BD,
+0xFF468FBA,
+0xFF4891BC,
+0xFF4891BC,
+0xFF4990BE,
+0xFF4992BD,
+0xFF4B92BE,
+0xFF4A93BC,
+0xFF4C93BF,
+0xFF4C93BD,
+0xFF4C93BF,
+0xFF4E95BF,
+0xFF4D94BE,
+0xFF5297C0,
+0xFF4F94BE,
+0xFF5396C0,
+0xFF5295C0,
+0xFF5497C1,
+0xFF5398C1,
+0xFF5199C1,
+0xFF5398C1,
+0xFF5499C2,
+0xFF559AC3,
+0xFF579AC4,
+0xFF589CC3,
+0xFF599DC4,
+0xFF5B9CC4,
+0xFF5C9DC5,
+0xFF5C9DC3,
+0xFF5B9CC2,
+0xFF5C9DC3,
+0xFF5E9FC5,
+0xFF5F9FC5,
+0xFF5E9EC4,
+0xFF5F9FC5,
+0xFF60A0C6,
+0xFF60A0C6,
+0xFF60A0C6,
+0xFF61A1C7,
+0xFF62A2C6,
+0xFF64A2C7,
+0xFF64A2C7,
+0xFF65A4C7,
+0xFF66A5C8,
+0xFF68A4C8,
+0xFF68A4C6,
+0xFF68A4C6,
+0xFF69A5C7,
+0xFF6AA5C7,
+0xFF6AA5C7,
+0xFF6AA6C8,
+0xFF6AA6C8,
+0xFF6AA6C8,
+0xFF6BA7C9,
+0xFF6BA7C9,
+0xFF6AA6C8,
+0xFF6AA6CA,
+0xFF6AA6CA,
+0xFF67A6C9,
+0xFF67A6C9,
+0xFF67A6C9,
+0xFF66A5C8,
+0xFF66A5C8,
+0xFF66A5C8,
+0xFF66A5C8,
+0xFF64A3C6,
+0xFF63A2C5,
+0xFF63A3C6,
+0xFF62A2C6,
+0xFF62A2C6,
+0xFF61A1C5,
+0xFF5FA1C4,
+0xFF5FA1C4,
+0xFF5FA1C4,
+0xFF5E9FC5,
+0xFF5E9FC5,
+0xFF5D9EC4,
+0xFF5D9EC4,
+0xFF5C9DC3,
+0xFF5A9EC3,
+0xFF5B9CC4,
+0xFF599DC4,
+0xFF5B9CC6,
+0xFF589BC5,
+0xFF599AC4,
+0xFF5699C3,
+0xFF5798C2,
+0xFF5598C2,
+0xFF5497C2,
+0xFF5297C1,
+0xFF5497C2,
+0xFF5297C1,
+0xFF5295C2,
+0xFF5195C2,
+0xFF5094C1,
+0xFF4E95C1,
+0xFF4F93C0,
+0xFF4C93BF,
+0xFF4B94BF,
+0xFF4B94BD,
+0xFF4A93BE,
+0xFF4A93BE,
+0xFF4992BD,
+0xFF4891BC,
+0xFF4891BC,
+0xFF4791BE,
+0xFF458FBC,
+0xFF458FBC,
+0xFF458FBE,
+0xFF428FBD,
+0xFF418EBC,
+0xFF3F8DBB,
+0xFF3F8DBD,
+0xFF3C8DBC,
+0xFF3C8DBC,
+0xFF3B8CBB,
+0xFF3B8CBB,
+0xFF3B8CBB,
+0xFF3C8ABA,
+0xFF3B89B9,
+0xFF3B89B9,
+0xFF3D89BA,
+0xFF3B87B8,
+0xFF3B88B6,
+0xFF3B88B6,
+0xFF3A87B5,
+0xFF3986B4,
+0xFF3986B4,
+0xFF3986B4,
+0xFF3986B4,
+0xFF3A84B3,
+0xFF3A82B2,
+0xFF3A81AF,
+0xFF3A81AD,
+0xFF3980AC,
+0xFF3980AC,
+0xFF3980AE,
+0xFF3780AD,
+0xFF3980AE,
+0xFF387FAB,
+0xFF397EA8,
+0xFF3A7FA9,
+0xFF397CA7,
+0xFF377AA5,
+0xFF377AA5,
+0xFF3477A1,
+0xFF5393B7,
+0xFF6197B3,
+0xFF638699,
+0xFFE3F5FF,
+0xFFFBFFFF,
+0xFFFCFAFB,
+0xFFFDFBFE,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFD,
+0xFFFFFEFB,
+0xFFFFFEFB,
+0xFFFFFFFD,
+0xFFFEFFFF,
+0xFFFCFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFDFCFA,
+0xFFFEFFFF,
+0xFFF6FEFF,
+0xFFF4FFFF,
+0xFFEEFFFF,
+0xFF648191,
+0xFF42677A,
+0xFF44728A,
+0xFF4A7D9A,
+0xFF437A99,
+0xFF387393,
+0xFF387496,
+0xFF357495,
+0xFF347396,
+0xFF39789B,
+0xFF37779D,
+0xFF36779F,
+0xFF3778A0,
+0xFF3778A0,
+0xFF3879A1,
+0xFF3879A1,
+0xFF397AA2,
+0xFF397AA2,
+0xFF397AA2,
+0xFF3A7BA3,
+0xFF387BA5,
+0xFF397CA6,
+0xFF397CA7,
+0xFF397EA8,
+0xFF397EA8,
+0xFF3A7FA9,
+0xFF3A7EAB,
+0xFF387FAB,
+0xFF3980AE,
+0xFF3982AF,
+0xFF3A81AF,
+0xFF3982AF,
+0xFF3A82B2,
+0xFF3983B2,
+0xFF3B85B4,
+0xFF3986B4,
+0xFF3985B6,
+0xFF3987B7,
+0xFF3987B7,
+0xFF3A88B8,
+0xFF3A88B8,
+0xFF3888B9,
+0xFF3A8ABB,
+0xFF3989BC,
+0xFF3989BC,
+0xFF398BBD,
+0xFF3A8CBE,
+0xFF3A8CBC,
+0xFF3A8CBC,
+0xFF3A8CBC,
+0xFF3C8CBD,
+0xFF3D8EBD,
+0xFF418FBF,
+0xFF3F8DBB,
+0xFF4390BE,
+0xFF428FBB,
+0xFF4690BD,
+0xFF458FBC,
+0xFF4791BE,
+0xFF4791BE,
+0xFF4890C0,
+0xFF4892BF,
+0xFF4A93C0,
+0xFF4994BE,
+0xFF4B94C1,
+0xFF4B94BF,
+0xFF4B94C1,
+0xFF4D96C1,
+0xFF4C95C0,
+0xFF5097C1,
+0xFF4D94C0,
+0xFF5297C1,
+0xFF5195C2,
+0xFF5398C2,
+0xFF5398C1,
+0xFF5398C1,
+0xFF5497C1,
+0xFF5598C2,
+0xFF5699C3,
+0xFF599AC4,
+0xFF5A9BC3,
+0xFF5A9BC3,
+0xFF5C9CC2,
+0xFF5D9DC3,
+0xFF5D9DC3,
+0xFF5C9CC2,
+0xFF5D9DC1,
+0xFF5F9FC3,
+0xFF609EC3,
+0xFF5E9EC2,
+0xFF5F9FC5,
+0xFF60A0C6,
+0xFF60A0C4,
+0xFF61A1C5,
+0xFF62A0C5,
+0xFF63A1C6,
+0xFF64A2C7,
+0xFF64A3C6,
+0xFF66A2C6,
+0xFF68A4C8,
+0xFF69A5C7,
+0xFF68A4C6,
+0xFF69A4C6,
+0xFF69A4C4,
+0xFF6AA5C5,
+0xFF6AA5C5,
+0xFF6AA7C6,
+0xFF6BA8C7,
+0xFF6BA7C9,
+0xFF6BA7C9,
+0xFF6BA7C9,
+0xFF6BA7C9,
+0xFF6BA7C9,
+0xFF6AA6C8,
+0xFF69A5C7,
+0xFF6AA6C8,
+0xFF69A5C7,
+0xFF68A4C6,
+0xFF68A4C6,
+0xFF69A5C7,
+0xFF68A4C6,
+0xFF65A4C5,
+0xFF64A3C6,
+0xFF64A3C6,
+0xFF63A2C5,
+0xFF63A2C5,
+0xFF62A1C4,
+0xFF60A0C3,
+0xFF60A0C4,
+0xFF60A0C4,
+0xFF5F9FC3,
+0xFF5F9FC3,
+0xFF5E9EC4,
+0xFF5E9EC4,
+0xFF5D9DC3,
+0xFF5C9DC3,
+0xFF5C9CC2,
+0xFF5B9CC2,
+0xFF599DC4,
+0xFF579CC3,
+0xFF579BC2,
+0xFF559AC1,
+0xFF5599C0,
+0xFF5499C0,
+0xFF5398C1,
+0xFF5098C0,
+0xFF5398C1,
+0xFF5098C0,
+0xFF5196C0,
+0xFF4F96C0,
+0xFF4E95BF,
+0xFF4D96BF,
+0xFF4D94BE,
+0xFF4B94BF,
+0xFF4B94BF,
+0xFF4A95BF,
+0xFF4993C0,
+0xFF4993C0,
+0xFF4892BF,
+0xFF4791BE,
+0xFF4791BE,
+0xFF4791C0,
+0xFF458FBE,
+0xFF4390BE,
+0xFF438FC0,
+0xFF418FBF,
+0xFF418FBF,
+0xFF408EBE,
+0xFF3F8DBE,
+0xFF3C8CBD,
+0xFF3B8DBD,
+0xFF3B8DBD,
+0xFF3A8CBC,
+0xFF3A8CBC,
+0xFF3A8ABB,
+0xFF3989BA,
+0xFF3989BA,
+0xFF3C8ABA,
+0xFF3A88B8,
+0xFF3A88B8,
+0xFF3A88B8,
+0xFF3987B7,
+0xFF3886B6,
+0xFF3886B6,
+0xFF3886B6,
+0xFF3986B4,
+0xFF3A84B3,
+0xFF3A83B0,
+0xFF3A81AF,
+0xFF3A81AD,
+0xFF3B7FAC,
+0xFF3B80AA,
+0xFF3B7FAC,
+0xFF387FAB,
+0xFF3B7FAC,
+0xFF387DA7,
+0xFF397EA8,
+0xFF3A7DA7,
+0xFF3C7DA7,
+0xFF3A7BA5,
+0xFF397AA4,
+0xFF4080A6,
+0xFF5C98BA,
+0xFF5C8EA7,
+0xFF83A3B2,
+0xFFF2FFFF,
+0xFFFCFFFF,
+0xFFFFFEFF,
+0xFFFDFDFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFD,
+0xFFFFFFFB,
+0xFFFFFEFB,
+0xFFFFFFFD,
+0xFFFEFFFF,
+0xFFFCFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFDFA,
+0xFFFFFFFD,
+0xFFF5FDFF,
+0xFFF2FFFF,
+0xFFC8E2F1,
+0xFF45687C,
+0xFF436D86,
+0xFF43728E,
+0xFF447998,
+0xFF397290,
+0xFF346F8F,
+0xFF397494,
+0xFF3B7799,
+0xFF397597,
+0xFF387498,
+0xFF367499,
+0xFF37779D,
+0xFF36779F,
+0xFF3778A0,
+0xFF3879A1,
+0xFF3879A1,
+0xFF3879A1,
+0xFF397AA2,
+0xFF397AA2,
+0xFF397AA2,
+0xFF387CA3,
+0xFF387BA5,
+0xFF397CA6,
+0xFF387DA7,
+0xFF397EA8,
+0xFF397EA8,
+0xFF3A7EAB,
+0xFF387FAB,
+0xFF387FAD,
+0xFF3881AE,
+0xFF3982AF,
+0xFF3981B1,
+0xFF3981B1,
+0xFF3983B2,
+0xFF3A84B3,
+0xFF3985B6,
+0xFF3884B5,
+0xFF3886B6,
+0xFF3886B6,
+0xFF3787B8,
+0xFF3888B9,
+0xFF3888B9,
+0xFF3888B9,
+0xFF3A8ABD,
+0xFF3989BC,
+0xFF3989BC,
+0xFF398BBD,
+0xFF3A8CBE,
+0xFF3A8CBC,
+0xFF3A8CBC,
+0xFF3B8DBD,
+0xFF3C8CBD,
+0xFF3D8EBD,
+0xFF418FBF,
+0xFF3F8DBB,
+0xFF4390BE,
+0xFF428FBD,
+0xFF4690BD,
+0xFF458FBC,
+0xFF4791C0,
+0xFF4791C0,
+0xFF4791C0,
+0xFF4892C1,
+0xFF4892BF,
+0xFF4993C0,
+0xFF4A94C1,
+0xFF4A94C1,
+0xFF4A94C1,
+0xFF4C96C3,
+0xFF4C95C0,
+0xFF4F98C3,
+0xFF4D94C0,
+0xFF5097C3,
+0xFF4F96C2,
+0xFF5198C4,
+0xFF5297C1,
+0xFF5398C1,
+0xFF5497C1,
+0xFF5598C2,
+0xFF5899C3,
+0xFF599AC4,
+0xFF5A9BC3,
+0xFF5A9BC3,
+0xFF5C9CC2,
+0xFF5D9DC3,
+0xFF5D9DC3,
+0xFF5C9CC2,
+0xFF5E9CC1,
+0xFF609EC3,
+0xFF609EC3,
+0xFF5F9DC2,
+0xFF5F9FC5,
+0xFF60A0C6,
+0xFF60A0C4,
+0xFF61A1C5,
+0xFF62A0C5,
+0xFF63A1C6,
+0xFF64A3C6,
+0xFF64A3C6,
+0xFF66A2C6,
+0xFF68A4C8,
+0xFF69A5C7,
+0xFF68A4C6,
+0xFF69A4C4,
+0xFF6AA5C5,
+0xFF6AA5C5,
+0xFF6AA5C5,
+0xFF6AA7C6,
+0xFF6BA8C7,
+0xFF6BA7C9,
+0xFF6CA8CA,
+0xFF6CA8CA,
+0xFF6BA7C9,
+0xFF6BA7C9,
+0xFF6AA6C8,
+0xFF6AA6C8,
+0xFF6AA6C8,
+0xFF6AA6C8,
+0xFF69A5C7,
+0xFF68A4C6,
+0xFF69A5C7,
+0xFF68A4C6,
+0xFF67A3C5,
+0xFF64A3C6,
+0xFF64A3C6,
+0xFF63A2C5,
+0xFF63A2C5,
+0xFF62A1C4,
+0xFF61A0C3,
+0xFF619FC4,
+0xFF60A0C4,
+0xFF5F9FC3,
+0xFF5F9FC3,
+0xFF5E9EC4,
+0xFF5E9EC4,
+0xFF5D9DC3,
+0xFF5C9CC2,
+0xFF5C9CC2,
+0xFF5B9CC2,
+0xFF599DC4,
+0xFF579CC3,
+0xFF569BC2,
+0xFF559AC1,
+0xFF5499C0,
+0xFF5499C0,
+0xFF5199C1,
+0xFF5098C0,
+0xFF5199C1,
+0xFF5098C0,
+0xFF4F96C0,
+0xFF4F96C0,
+0xFF4D96BF,
+0xFF4D96BF,
+0xFF4C95BE,
+0xFF4B94BD,
+0xFF4A94C1,
+0xFF4A94C1,
+0xFF4993C0,
+0xFF4993C0,
+0xFF4892BF,
+0xFF4892BF,
+0xFF4791C0,
+0xFF4791C0,
+0xFF4690C1,
+0xFF438FC0,
+0xFF438FC0,
+0xFF418FBF,
+0xFF418FC0,
+0xFF408EBF,
+0xFF3D8DBE,
+0xFF3C8CBD,
+0xFF3B8DBD,
+0xFF398DBC,
+0xFF3A8CBC,
+0xFF3A8CBC,
+0xFF3A8ABB,
+0xFF3989BA,
+0xFF3989BA,
+0xFF3A8BBA,
+0xFF3987B7,
+0xFF3A88B8,
+0xFF3A88B8,
+0xFF3987B7,
+0xFF3987B7,
+0xFF3886B6,
+0xFF3886B6,
+0xFF3986B4,
+0xFF3A84B1,
+0xFF3A83B0,
+0xFF3A81AD,
+0xFF3A81AD,
+0xFF3B80AA,
+0xFF3B80AA,
+0xFF3B7FAC,
+0xFF3A7EAB,
+0xFF3A7FA9,
+0xFF377CA6,
+0xFF3A7DA7,
+0xFF3A7DA7,
+0xFF3C7DA5,
+0xFF3A7BA3,
+0xFF3A7BA1,
+0xFF4A89AC,
+0xFF568DAB,
+0xFF4F7C93,
+0xFFCAE6F4,
+0xFFF2FFFF,
+0xFFF9FDFE,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFCFDFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFD,
+0xFFFFFFFB,
+0xFFFFFEFB,
+0xFFFFFFFD,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFFFEFD,
+0xFFFFFEFB,
+0xFFFFFFFB,
+0xFFFFFFFB,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFCFCFA,
+0xFFFBFFFF,
+0xFFF3FFFF,
+0xFFAFC9D8,
+0xFF395D75,
+0xFF3E6B88,
+0xFF396E90,
+0xFF3C7499,
+0xFF397398,
+0xFF367294,
+0xFF3B7698,
+0xFF3D789A,
+0xFF367294,
+0xFF367296,
+0xFF39779C,
+0xFF36769C,
+0xFF36779F,
+0xFF36779F,
+0xFF3778A0,
+0xFF3879A1,
+0xFF3879A1,
+0xFF3879A1,
+0xFF3879A3,
+0xFF397AA4,
+0xFF377AA4,
+0xFF387BA5,
+0xFF387BA6,
+0xFF387DA7,
+0xFF387DA7,
+0xFF397EA8,
+0xFF377EAA,
+0xFF387FAB,
+0xFF377EAA,
+0xFF387FAB,
+0xFF3881AE,
+0xFF3982AF,
+0xFF3982AF,
+0xFF3982AF,
+0xFF3983B2,
+0xFF3A84B3,
+0xFF3885B3,
+0xFF3885B3,
+0xFF3886B6,
+0xFF3886B6,
+0xFF3787B8,
+0xFF3888B9,
+0xFF3888B9,
+0xFF3888B9,
+0xFF3C8ABB,
+0xFF3989BA,
+0xFF3989BA,
+0xFF3A8ABB,
+0xFF3B8BBC,
+0xFF3B8BBC,
+0xFF3B8BBC,
+0xFF3C8DBC,
+0xFF3C8DBC,
+0xFF3D8EBD,
+0xFF418FBF,
+0xFF3F8DBB,
+0xFF4390BE,
+0xFF448EBB,
+0xFF4690BD,
+0xFF458FBC,
+0xFF4791C0,
+0xFF4791C0,
+0xFF4791BE,
+0xFF4892BF,
+0xFF4892BF,
+0xFF4993C0,
+0xFF4A94C1,
+0xFF4A94C1,
+0xFF4A95BF,
+0xFF4C97C1,
+0xFF4C95C0,
+0xFF4F98C3,
+0xFF4D94C0,
+0xFF5097C3,
+0xFF4F96C2,
+0xFF5198C4,
+0xFF5297C1,
+0xFF5398C2,
+0xFF5497C1,
+0xFF5598C2,
+0xFF5899C3,
+0xFF599AC4,
+0xFF5B9AC3,
+0xFF5B9AC3,
+0xFF5D9BC2,
+0xFF5E9CC3,
+0xFF5E9CC1,
+0xFF5E9CC1,
+0xFF5E9CC1,
+0xFF609EC3,
+0xFF609EC3,
+0xFF5F9DC2,
+0xFF5F9FC3,
+0xFF60A0C4,
+0xFF61A1C5,
+0xFF61A1C5,
+0xFF62A1C4,
+0xFF63A2C5,
+0xFF64A3C6,
+0xFF65A4C7,
+0xFF66A2C4,
+0xFF68A4C6,
+0xFF68A4C6,
+0xFF68A4C6,
+0xFF69A6C5,
+0xFF6AA7C6,
+0xFF6AA7C6,
+0xFF6AA7C6,
+0xFF6BA6C6,
+0xFF6CA7C7,
+0xFF6DA8C8,
+0xFF6DA8C8,
+0xFF6CA9C8,
+0xFF6CA9C8,
+0xFF6BA8C7,
+0xFF6AA7C6,
+0xFF6AA7C6,
+0xFF6AA7C6,
+0xFF6AA6C8,
+0xFF69A5C7,
+0xFF69A5C7,
+0xFF69A5C7,
+0xFF68A4C6,
+0xFF67A3C5,
+0xFF66A2C6,
+0xFF66A2C6,
+0xFF65A1C5,
+0xFF65A1C5,
+0xFF64A0C4,
+0xFF61A0C3,
+0xFF619FC4,
+0xFF609EC3,
+0xFF609EC3,
+0xFF609EC3,
+0xFF609EC3,
+0xFF5F9DC2,
+0xFF5E9CC3,
+0xFF5D9BC2,
+0xFF5D9BC2,
+0xFF5D9DC3,
+0xFF599DC2,
+0xFF579DC1,
+0xFF569BC2,
+0xFF559AC1,
+0xFF5499C0,
+0xFF5499C0,
+0xFF5398BF,
+0xFF5297BE,
+0xFF5199C1,
+0xFF5098C0,
+0xFF4F97BF,
+0xFF4F97BF,
+0xFF4E96BE,
+0xFF4E96BE,
+0xFF4C95BE,
+0xFF4B94BD,
+0xFF4B94C1,
+0xFF4B94C1,
+0xFF4A93C0,
+0xFF4A93C0,
+0xFF4992BF,
+0xFF4992BF,
+0xFF4890C0,
+0xFF4791C0,
+0xFF4690BF,
+0xFF4390BE,
+0xFF438FC0,
+0xFF428EBF,
+0xFF418FBF,
+0xFF408EBE,
+0xFF3F8DBD,
+0xFF3C8DBC,
+0xFF3B8DBC,
+0xFF3B8DBC,
+0xFF3A8CBB,
+0xFF3A8CBB,
+0xFF3A8BBA,
+0xFF398AB9,
+0xFF3B89B9,
+0xFF3C8ABA,
+0xFF3A86B7,
+0xFF3A87B5,
+0xFF3B88B6,
+0xFF3B88B6,
+0xFF3A87B5,
+0xFF3986B4,
+0xFF3986B4,
+0xFF3986B4,
+0xFF3A84B1,
+0xFF3984AE,
+0xFF3982AD,
+0xFF3980AC,
+0xFF3B80AA,
+0xFF3B80AA,
+0xFF3C7FAA,
+0xFF3B7EA9,
+0xFF3C7FAA,
+0xFF397CA7,
+0xFF3B7EA9,
+0xFF3A7DA7,
+0xFF3B7CA4,
+0xFF397AA0,
+0xFF3C7CA0,
+0xFF508BAB,
+0xFF5887A1,
+0xFF5D8295,
+0xFFEEFFFF,
+0xFFF7FFFF,
+0xFFFEFFFF,
+0xFFFEFDFB,
+0xFFFFFFFF,
+0xFFFCFDFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFEFB,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFFFEFB,
+0xFFFFFEFB,
+0xFFFFFFFB,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFBFFFE,
+0xFFFBFFFF,
+0xFFF3FFFF,
+0xFF95ACBA,
+0xFF34576B,
+0xFF376481,
+0xFF366C90,
+0xFF3A759D,
+0xFF327097,
+0xFF327095,
+0xFF387498,
+0xFF3A7597,
+0xFF377294,
+0xFF377397,
+0xFF38769B,
+0xFF36779D,
+0xFF34759D,
+0xFF36779F,
+0xFF3778A0,
+0xFF3879A1,
+0xFF3879A1,
+0xFF3879A1,
+0xFF3879A1,
+0xFF397AA4,
+0xFF397AA4,
+0xFF377AA4,
+0xFF387BA5,
+0xFF377CA6,
+0xFF387DA7,
+0xFF387DA7,
+0xFF397EA8,
+0xFF377EAA,
+0xFF387FAB,
+0xFF377EAA,
+0xFF387FAB,
+0xFF3980AC,
+0xFF3982AD,
+0xFF3982AF,
+0xFF3A83B0,
+0xFF3A83B0,
+0xFF3A84B3,
+0xFF3A84B3,
+0xFF3885B3,
+0xFF3885B3,
+0xFF3886B6,
+0xFF3987B7,
+0xFF3889B8,
+0xFF3A88B9,
+0xFF3A88B8,
+0xFF3B89BA,
+0xFF3B89B9,
+0xFF3B89BA,
+0xFF3A8BBA,
+0xFF3B8BBC,
+0xFF3B8CBB,
+0xFF3B8CBB,
+0xFF3C8DBC,
+0xFF3C8DBC,
+0xFF3F8DBB,
+0xFF418FBD,
+0xFF408DB9,
+0xFF458FBC,
+0xFF448EBB,
+0xFF4690BD,
+0xFF458FBC,
+0xFF4791BE,
+0xFF4791BE,
+0xFF4791BE,
+0xFF4892BF,
+0xFF4892BF,
+0xFF4994BE,
+0xFF4A94C1,
+0xFF4A95BF,
+0xFF4A95BF,
+0xFF4D96C1,
+0xFF4C95C0,
+0xFF4F96C0,
+0xFF4D94C0,
+0xFF5097C1,
+0xFF5195C2,
+0xFF5398C2,
+0xFF5297C1,
+0xFF5398C2,
+0xFF5497C1,
+0xFF5699C3,
+0xFF5899C3,
+0xFF599AC4,
+0xFF5B9AC3,
+0xFF5B9AC3,
+0xFF5D9BC4,
+0xFF5E9CC3,
+0xFF5E9CC3,
+0xFF5E9CC1,
+0xFF5F9DC2,
+0xFF609EC3,
+0xFF609EC3,
+0xFF5F9DC2,
+0xFF5F9FC3,
+0xFF60A0C4,
+0xFF61A1C5,
+0xFF61A1C5,
+0xFF62A1C4,
+0xFF63A2C5,
+0xFF64A3C6,
+0xFF65A4C7,
+0xFF67A3C5,
+0xFF68A4C6,
+0xFF68A4C6,
+0xFF68A4C6,
+0xFF69A6C5,
+0xFF6AA7C6,
+0xFF6BA8C7,
+0xFF6AA7C6,
+0xFF6CA7C7,
+0xFF6DA8C8,
+0xFF6DA8C8,
+0xFF6EA9C9,
+0xFF6DAAC9,
+0xFF6CA9C8,
+0xFF6CA9C8,
+0xFF6BA8C7,
+0xFF6AA7C6,
+0xFF6AA7C6,
+0xFF6AA6C8,
+0xFF69A5C7,
+0xFF69A5C7,
+0xFF69A5C7,
+0xFF68A4C6,
+0xFF67A3C5,
+0xFF66A2C6,
+0xFF66A2C6,
+0xFF65A1C5,
+0xFF65A1C5,
+0xFF64A0C4,
+0xFF62A1C4,
+0xFF619FC4,
+0xFF609EC3,
+0xFF5F9DC2,
+0xFF609EC3,
+0xFF609EC3,
+0xFF5F9DC2,
+0xFF5E9CC3,
+0xFF5D9BC2,
+0xFF5D9BC2,
+0xFF5D9DC3,
+0xFF599DC2,
+0xFF579CC3,
+0xFF579BC2,
+0xFF559AC1,
+0xFF5599C0,
+0xFF5499C0,
+0xFF5398BF,
+0xFF5297BE,
+0xFF5398C1,
+0xFF5098C0,
+0xFF4F97BF,
+0xFF4F97BF,
+0xFF4E96BE,
+0xFF4E96BE,
+0xFF4D94BE,
+0xFF4B94BD,
+0xFF4C93BF,
+0xFF4B94BF,
+0xFF4B92C0,
+0xFF4A93BE,
+0xFF4992BF,
+0xFF4992BF,
+0xFF4891BE,
+0xFF4891BE,
+0xFF478FBF,
+0xFF458FBE,
+0xFF448EBD,
+0xFF428FBD,
+0xFF428EBF,
+0xFF408EBC,
+0xFF3F8DBD,
+0xFF3E8CBC,
+0xFF3D8EBD,
+0xFF3B8DBC,
+0xFF3B8DBC,
+0xFF3B8DBC,
+0xFF3B8CBB,
+0xFF3A8BBA,
+0xFF3C8ABA,
+0xFF3D8BB9,
+0xFF3A87B5,
+0xFF3A87B5,
+0xFF3B88B6,
+0xFF3B88B6,
+0xFF3A87B5,
+0xFF3986B4,
+0xFF3986B4,
+0xFF3885B1,
+0xFF3A84B1,
+0xFF3984AE,
+0xFF3883AD,
+0xFF3881AC,
+0xFF3980AC,
+0xFF3B80AA,
+0xFF3C7FAA,
+0xFF3B7EA9,
+0xFF3B7EA9,
+0xFF3A7DA8,
+0xFF3A7DA8,
+0xFF3A7DA7,
+0xFF3B7CA4,
+0xFF3B7B9F,
+0xFF407FA2,
+0xFF5188A6,
+0xFF50798F,
+0xFFA3BFCD,
+0xFFF0FFFF,
+0xFFF7FFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFEFB,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFD,
+0xFFFFFEFB,
+0xFFFFFEFB,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFDFFFE,
+0xFFF8FFFF,
+0xFFF1FFFF,
+0xFF8EA8B5,
+0xFF35586C,
+0xFF3A6681,
+0xFF356A8A,
+0xFF367096,
+0xFF337198,
+0xFF35739A,
+0xFF39759A,
+0xFF3C769B,
+0xFF397496,
+0xFF377294,
+0xFF37759A,
+0xFF35769C,
+0xFF3176A0,
+0xFF3479A3,
+0xFF3477A1,
+0xFF3778A0,
+0xFF3879A1,
+0xFF3778A0,
+0xFF3778A0,
+0xFF3778A0,
+0xFF377AA4,
+0xFF387BA5,
+0xFF377AA4,
+0xFF387BA5,
+0xFF387DA7,
+0xFF387DA7,
+0xFF387CA9,
+0xFF397DAA,
+0xFF387FAB,
+0xFF387FAB,
+0xFF397EA8,
+0xFF3A7FA9,
+0xFF3B80AA,
+0xFF3A81AB,
+0xFF3A81AD,
+0xFF3A83AE,
+0xFF3A83AE,
+0xFF3A84B1,
+0xFF3A84B1,
+0xFF3A84B1,
+0xFF3A84B1,
+0xFF3986B4,
+0xFF3A87B5,
+0xFF3A88B6,
+0xFF3B87B8,
+0xFF3B88B6,
+0xFF3C88B9,
+0xFF3C89B7,
+0xFF3C88B9,
+0xFF3C8AB8,
+0xFF3D8BBB,
+0xFF3D8BB9,
+0xFF3D8BB9,
+0xFF3E8CBA,
+0xFF3E8CBA,
+0xFF408DBB,
+0xFF428FBD,
+0xFF428CB9,
+0xFF458FBC,
+0xFF458EB9,
+0xFF4790BB,
+0xFF468FBA,
+0xFF4891BC,
+0xFF4891BC,
+0xFF4891BC,
+0xFF4992BD,
+0xFF4992BD,
+0xFF4A93BC,
+0xFF4A93BE,
+0xFF4B94BD,
+0xFF4B94BD,
+0xFF4D94BE,
+0xFF4D94BE,
+0xFF5196BF,
+0xFF5095BF,
+0xFF5297C0,
+0xFF5396C1,
+0xFF5398C2,
+0xFF5297C1,
+0xFF5198C2,
+0xFF5499C3,
+0xFF559AC4,
+0xFF579AC4,
+0xFF579AC4,
+0xFF5A9BC5,
+0xFF5A9BC3,
+0xFF5C9BC4,
+0xFF5D9DC3,
+0xFF5D9DC3,
+0xFF5D9DC3,
+0xFF5E9EC2,
+0xFF5F9FC3,
+0xFF5F9FC3,
+0xFF5F9FC3,
+0xFF5F9FC3,
+0xFF60A0C4,
+0xFF61A1C5,
+0xFF61A1C5,
+0xFF61A1C4,
+0xFF62A2C5,
+0xFF63A3C6,
+0xFF64A4C7,
+0xFF64A3C4,
+0xFF66A5C6,
+0xFF67A6C7,
+0xFF67A6C7,
+0xFF67A6C7,
+0xFF68A7C8,
+0xFF68A7C8,
+0xFF68A7C8,
+0xFF6BA7C9,
+0xFF6BA7C9,
+0xFF6CA8CA,
+0xFF6DA9CB,
+0xFF6DA9CB,
+0xFF6CA8CA,
+0xFF6BA7C9,
+0xFF6BA7C9,
+0xFF6AA6C8,
+0xFF6AA6C8,
+0xFF68A7C8,
+0xFF67A6C7,
+0xFF66A5C6,
+0xFF67A6C7,
+0xFF66A5C6,
+0xFF64A3C4,
+0xFF64A3C6,
+0xFF64A3C6,
+0xFF63A2C5,
+0xFF63A2C5,
+0xFF62A0C5,
+0xFF62A0C5,
+0xFF619FC4,
+0xFF5F9FC3,
+0xFF5E9EC2,
+0xFF5F9FC3,
+0xFF5F9FC5,
+0xFF5E9EC4,
+0xFF5D9DC3,
+0xFF5C9CC2,
+0xFF5C9CC2,
+0xFF5C9DC3,
+0xFF5B9CC4,
+0xFF589BC5,
+0xFF599AC4,
+0xFF5699C3,
+0xFF5798C2,
+0xFF5598C2,
+0xFF5497C1,
+0xFF5396C0,
+0xFF5497C2,
+0xFF5297C1,
+0xFF5196C0,
+0xFF5196C0,
+0xFF5095BF,
+0xFF5095BF,
+0xFF4F94BE,
+0xFF4C93BD,
+0xFF4E93BD,
+0xFF4C93BD,
+0xFF4D91BE,
+0xFF4B92BC,
+0xFF4A91BD,
+0xFF4A91BD,
+0xFF4990BC,
+0xFF4891BC,
+0xFF4790BD,
+0xFF458FBC,
+0xFF448EBB,
+0xFF428FBB,
+0xFF428FBD,
+0xFF418EBA,
+0xFF408DBB,
+0xFF3D8BB9,
+0xFF3D8EBB,
+0xFF3C8DBA,
+0xFF3C8DBA,
+0xFF3C8DBA,
+0xFF3D8BB9,
+0xFF3B89B7,
+0xFF3C89B7,
+0xFF3D8AB6,
+0xFF3B85B2,
+0xFF3C86B3,
+0xFF3D87B4,
+0xFF3D87B4,
+0xFF3C86B3,
+0xFF3B85B2,
+0xFF3B85B2,
+0xFF3A84B1,
+0xFF3885B1,
+0xFF3784B0,
+0xFF3683AF,
+0xFF3781AE,
+0xFF3881AE,
+0xFF3980AC,
+0xFF3A7FA9,
+0xFF3B7EA9,
+0xFF397DAA,
+0xFF397DAA,
+0xFF387CA9,
+0xFF397EA8,
+0xFF397DA4,
+0xFF3D7DA1,
+0xFF4581A3,
+0xFF4D7F9A,
+0xFF4F7083,
+0xFFE5F9FF,
+0xFFF7FFFF,
+0xFFFBFFFF,
+0xFFFEFDFB,
+0xFFFFFFFD,
+0xFFFDFBFC,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFB,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFD,
+0xFFFFFEFD,
+0xFFFFFEFB,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFCFFFF,
+0xFFFAFFFF,
+0xFFF4FFFF,
+0xFF9EB8C7,
+0xFF2B4F65,
+0xFF37637C,
+0xFF356686,
+0xFF387093,
+0xFF347095,
+0xFF37759C,
+0xFF35739A,
+0xFF387297,
+0xFF377294,
+0xFF3A7295,
+0xFF3A7597,
+0xFF367499,
+0xFF35769E,
+0xFF3077A3,
+0xFF2E75A1,
+0xFF3477A1,
+0xFF3778A0,
+0xFF3879A1,
+0xFF3778A0,
+0xFF3778A0,
+0xFF3778A0,
+0xFF377AA4,
+0xFF387BA5,
+0xFF377AA4,
+0xFF387BA5,
+0xFF387DA7,
+0xFF387DA7,
+0xFF387CA9,
+0xFF397DAA,
+0xFF387FAB,
+0xFF387FA9,
+0xFF397EA8,
+0xFF3A7FA9,
+0xFF3B80AA,
+0xFF3A81AB,
+0xFF3A81AB,
+0xFF3B82AC,
+0xFF3A83AE,
+0xFF3B84AF,
+0xFF3A84B1,
+0xFF3A84B1,
+0xFF3A84B1,
+0xFF3B85B2,
+0xFF3A87B5,
+0xFF3B88B6,
+0xFF3B88B6,
+0xFF3B88B6,
+0xFF3C89B7,
+0xFF3C89B7,
+0xFF3C89B7,
+0xFF3C8AB8,
+0xFF3D8BBB,
+0xFF3D8BB9,
+0xFF3D8BBB,
+0xFF3E8CBA,
+0xFF3E8CBA,
+0xFF408DBB,
+0xFF428FBD,
+0xFF428CB9,
+0xFF458FBC,
+0xFF458EB9,
+0xFF4790BD,
+0xFF468FBA,
+0xFF4891BC,
+0xFF4891BC,
+0xFF4891BC,
+0xFF4992BD,
+0xFF4992BB,
+0xFF4A93BC,
+0xFF4A93BC,
+0xFF4B94BD,
+0xFF4C93BD,
+0xFF4D94BE,
+0xFF4F94BD,
+0xFF5196BF,
+0xFF5194BE,
+0xFF5396C0,
+0xFF5396C0,
+0xFF5398C1,
+0xFF5097C1,
+0xFF5198C2,
+0xFF5499C3,
+0xFF559AC4,
+0xFF579AC4,
+0xFF579AC4,
+0xFF5A9BC5,
+0xFF5A9BC5,
+0xFF5B9CC4,
+0xFF5D9CC5,
+0xFF5D9DC3,
+0xFF5D9DC3,
+0xFF5E9EC2,
+0xFF5F9FC3,
+0xFF5F9FC3,
+0xFF5F9FC3,
+0xFF5F9FC3,
+0xFF60A0C4,
+0xFF61A1C5,
+0xFF62A2C6,
+0xFF61A1C4,
+0xFF62A2C5,
+0xFF63A3C6,
+0xFF64A4C7,
+0xFF64A3C4,
+0xFF67A6C7,
+0xFF68A7C8,
+0xFF67A6C7,
+0xFF66A5C6,
+0xFF67A6C7,
+0xFF68A7C8,
+0xFF69A8C9,
+0xFF6AA6C8,
+0xFF6BA7C9,
+0xFF6CA8CA,
+0xFF6DA9CB,
+0xFF6DA9CB,
+0xFF6CA8CA,
+0xFF6BA7C9,
+0xFF6AA6C8,
+0xFF6AA6C8,
+0xFF6AA6C8,
+0xFF67A6C7,
+0xFF66A5C6,
+0xFF66A5C6,
+0xFF66A5C6,
+0xFF66A5C6,
+0xFF64A3C4,
+0xFF65A4C7,
+0xFF64A3C6,
+0xFF63A2C5,
+0xFF62A2C5,
+0xFF62A0C5,
+0xFF61A1C5,
+0xFF60A0C4,
+0xFF5F9FC3,
+0xFF5E9EC2,
+0xFF5F9FC3,
+0xFF5F9FC5,
+0xFF5E9EC4,
+0xFF5D9DC3,
+0xFF5B9CC2,
+0xFF5B9CC2,
+0xFF5C9DC5,
+0xFF5B9CC6,
+0xFF5A9BC5,
+0xFF599AC4,
+0xFF5899C3,
+0xFF5798C2,
+0xFF5598C2,
+0xFF5497C1,
+0xFF5396C1,
+0xFF5497C2,
+0xFF5297C1,
+0xFF5196C0,
+0xFF5196C0,
+0xFF5095BF,
+0xFF5095BF,
+0xFF4F94BE,
+0xFF4E93BD,
+0xFF4E93BD,
+0xFF4C93BD,
+0xFF4D92BC,
+0xFF4B92BC,
+0xFF4A91BB,
+0xFF4A91BB,
+0xFF4990BC,
+0xFF4891BC,
+0xFF468FBA,
+0xFF448FB9,
+0xFF448EBB,
+0xFF418EBA,
+0xFF428FBB,
+0xFF418EBA,
+0xFF408DB9,
+0xFF3D8BB9,
+0xFF3C8DBA,
+0xFF3B8CB9,
+0xFF3B8CBB,
+0xFF3B8CB9,
+0xFF3C8AB8,
+0xFF3B89B7,
+0xFF3C89B7,
+0xFF3D8AB6,
+0xFF3986B4,
+0xFF3C86B3,
+0xFF3D87B6,
+0xFF3D87B4,
+0xFF3C86B3,
+0xFF3B85B2,
+0xFF3B85B2,
+0xFF3A84B1,
+0xFF3885B1,
+0xFF3784B0,
+0xFF3683B1,
+0xFF3582B0,
+0xFF3781B0,
+0xFF3881AE,
+0xFF3A7EAB,
+0xFF3B7EA9,
+0xFF3B7FAC,
+0xFF3B7FAC,
+0xFF367DA9,
+0xFF397EA8,
+0xFF387CA3,
+0xFF3D7C9F,
+0xFF477FA0,
+0xFF47758D,
+0xFF7A94A3,
+0xFFF4FFFF,
+0xFFF8FFFF,
+0xFFFCFDFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFCFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFCFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFDFC,
+0xFFFFFCF9,
+0xFFFFFFFD,
+0xFFFDFDFD,
+0xFFF9FDFE,
+0xFFF9FFFF,
+0xFFF2FDFF,
+0xFFC4D8E3,
+0xFF294D63,
+0xFF2D5A77,
+0xFF326383,
+0xFF376C8E,
+0xFF3A7295,
+0xFF377196,
+0xFF387499,
+0xFF3A7499,
+0xFF387297,
+0xFF3B7396,
+0xFF397496,
+0xFF387498,
+0xFF35759B,
+0xFF32759F,
+0xFF3276A3,
+0xFF3276A3,
+0xFF3578A2,
+0xFF3778A0,
+0xFF3778A0,
+0xFF3778A0,
+0xFF3778A2,
+0xFF3879A3,
+0xFF377AA4,
+0xFF387BA5,
+0xFF3679A4,
+0xFF377AA5,
+0xFF377CA6,
+0xFF387DA7,
+0xFF397EA8,
+0xFF397EA8,
+0xFF3A7FA9,
+0xFF3B80AA,
+0xFF377EA8,
+0xFF387FAB,
+0xFF3980AC,
+0xFF3980AC,
+0xFF3B82AE,
+0xFF3C85B0,
+0xFF3B84B1,
+0xFF3A83B0,
+0xFF3A84B1,
+0xFF3A84B1,
+0xFF3986B4,
+0xFF3A87B5,
+0xFF3B88B6,
+0xFF3B88B6,
+0xFF3A88B8,
+0xFF3987B7,
+0xFF3C8ABA,
+0xFF3B89B9,
+0xFF3B89B9,
+0xFF3B8CBB,
+0xFF3C8CBD,
+0xFF3B8CBB,
+0xFF3B8BBC,
+0xFF3C8DBC,
+0xFF3B8CBB,
+0xFF3E8CBC,
+0xFF3F8DBD,
+0xFF428FBD,
+0xFF428FBD,
+0xFF458FBC,
+0xFF458FBE,
+0xFF458FBC,
+0xFF4790BD,
+0xFF4891BE,
+0xFF4792BC,
+0xFF4893BD,
+0xFF4994BE,
+0xFF4994BE,
+0xFF4B94BF,
+0xFF4B94BF,
+0xFF4C95BE,
+0xFF4C95BE,
+0xFF4D94BE,
+0xFF4D94BE,
+0xFF5095BF,
+0xFF5196C0,
+0xFF5297C1,
+0xFF5398C2,
+0xFF5198C2,
+0xFF5099C2,
+0xFF5299C3,
+0xFF539AC4,
+0xFF569BC4,
+0xFF569BC4,
+0xFF579AC4,
+0xFF589BC5,
+0xFF5B9FC6,
+0xFF5C9DC5,
+0xFF5B9CC2,
+0xFF5C9DC3,
+0xFF5D9EC4,
+0xFF5E9FC5,
+0xFF5EA0C3,
+0xFF5EA0C3,
+0xFF5F9FC3,
+0xFF60A0C4,
+0xFF60A0C4,
+0xFF61A1C5,
+0xFF62A2C6,
+0xFF63A3C7,
+0xFF63A3C6,
+0xFF64A4C7,
+0xFF65A4C7,
+0xFF66A5C8,
+0xFF66A5C8,
+0xFF66A5C8,
+0xFF66A5C6,
+0xFF66A5C6,
+0xFF67A6C7,
+0xFF67A6C7,
+0xFF6AA6C8,
+0xFF6BA7C9,
+0xFF6BA7C9,
+0xFF6CA8CA,
+0xFF6CA8CA,
+0xFF6BA7C9,
+0xFF69A8C9,
+0xFF68A7C8,
+0xFF67A6C9,
+0xFF68A7CA,
+0xFF68A7CA,
+0xFF67A6C9,
+0xFF66A5C8,
+0xFF65A4C7,
+0xFF65A4C7,
+0xFF65A4C7,
+0xFF63A3C7,
+0xFF63A3C7,
+0xFF62A2C6,
+0xFF61A3C6,
+0xFF61A1C5,
+0xFF60A2C5,
+0xFF60A2C5,
+0xFF5FA1C4,
+0xFF5D9EC4,
+0xFF5E9FC5,
+0xFF5E9FC5,
+0xFF5C9DC3,
+0xFF5C9DC5,
+0xFF5A9EC5,
+0xFF599DC4,
+0xFF589CC3,
+0xFF599CC6,
+0xFF589BC6,
+0xFF579AC5,
+0xFF5699C4,
+0xFF5497C2,
+0xFF5396C1,
+0xFF5396C1,
+0xFF5195C2,
+0xFF5397C4,
+0xFF5397C4,
+0xFF5296C3,
+0xFF4F96C2,
+0xFF4E95C1,
+0xFF4D94C0,
+0xFF4D94C0,
+0xFF4C93BF,
+0xFF4D94C0,
+0xFF4B94BF,
+0xFF4C93BF,
+0xFF4A93BE,
+0xFF4A93BE,
+0xFF4A93BE,
+0xFF4992BF,
+0xFF4791BE,
+0xFF458FBC,
+0xFF458FBC,
+0xFF458FBC,
+0xFF428FBB,
+0xFF418EBC,
+0xFF3F8DBB,
+0xFF3E8CBA,
+0xFF3B8CB9,
+0xFF3C8DBC,
+0xFF3B8DBC,
+0xFF3A8CBC,
+0xFF3A8CBB,
+0xFF3A8BBA,
+0xFF3A8BBA,
+0xFF3B89B9,
+0xFF3B89B7,
+0xFF3A88B8,
+0xFF3B88B6,
+0xFF3B87B8,
+0xFF3A87B5,
+0xFF3986B4,
+0xFF3986B4,
+0xFF3885B3,
+0xFF3885B3,
+0xFF3885B1,
+0xFF3784B0,
+0xFF3482B0,
+0xFF3482B0,
+0xFF3781B0,
+0xFF3881AE,
+0xFF3B7FAC,
+0xFF3A7EAB,
+0xFF397DAC,
+0xFF397DAC,
+0xFF377EAC,
+0xFF357CA8,
+0xFF3A7BA3,
+0xFF407CA0,
+0xFF417896,
+0xFF40697F,
+0xFFCDE1EC,
+0xFFF5FEFF,
+0xFFFCFFFF,
+0xFFFEFEFE,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFCFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFCFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFB,
+0xFFFAFAF8,
+0xFFFCFFFF,
+0xFFF9FFFF,
+0xFFF1FEFF,
+0xFFE9FBFF,
+0xFF2C4758,
+0xFF295570,
+0xFF2E6383,
+0xFF356B8D,
+0xFF397192,
+0xFF3A7295,
+0xFF367095,
+0xFF377196,
+0xFF387297,
+0xFF387297,
+0xFF387297,
+0xFF397399,
+0xFF367499,
+0xFF35759B,
+0xFF34759D,
+0xFF3376A1,
+0xFF3376A1,
+0xFF3677A1,
+0xFF36779F,
+0xFF3778A0,
+0xFF3879A1,
+0xFF3879A3,
+0xFF3879A3,
+0xFF377AA4,
+0xFF377AA4,
+0xFF397CA7,
+0xFF3A7DA8,
+0xFF397EA8,
+0xFF377CA6,
+0xFF367BA5,
+0xFF367BA5,
+0xFF387DA7,
+0xFF3A7FA9,
+0xFF3980AC,
+0xFF3A81AD,
+0xFF3B82AE,
+0xFF3982AD,
+0xFF3881AC,
+0xFF3982AD,
+0xFF3881AE,
+0xFF3780AD,
+0xFF3A84B1,
+0xFF3A84B1,
+0xFF3986B4,
+0xFF3986B4,
+0xFF3A87B5,
+0xFF3A87B5,
+0xFF3987B7,
+0xFF3886B6,
+0xFF3B89B9,
+0xFF3987B7,
+0xFF3888B9,
+0xFF3989BA,
+0xFF3A8ABB,
+0xFF3A8ABB,
+0xFF3A8ABB,
+0xFF3B8BBC,
+0xFF3C8DBC,
+0xFF3D8EBD,
+0xFF408EBE,
+0xFF418FBF,
+0xFF438FC0,
+0xFF4390BE,
+0xFF458FBE,
+0xFF458FBE,
+0xFF4891BE,
+0xFF4891BE,
+0xFF4893BD,
+0xFF4994BE,
+0xFF4994BE,
+0xFF4A95BF,
+0xFF4B94BF,
+0xFF4C95C0,
+0xFF4D96C1,
+0xFF4D96BF,
+0xFF4E95BF,
+0xFF4E95BF,
+0xFF5196C0,
+0xFF5297C1,
+0xFF5398C2,
+0xFF5499C3,
+0xFF5097C1,
+0xFF5098C0,
+0xFF5198C2,
+0xFF5499C2,
+0xFF559AC3,
+0xFF579BC2,
+0xFF579AC4,
+0xFF589CC3,
+0xFF599DC4,
+0xFF5B9CC2,
+0xFF5B9CC2,
+0xFF5B9CC2,
+0xFF5C9DC3,
+0xFF5D9FC2,
+0xFF5D9FC2,
+0xFF5E9EC2,
+0xFF60A0C4,
+0xFF60A0C4,
+0xFF62A0C5,
+0xFF61A1C5,
+0xFF63A1C6,
+0xFF62A2C6,
+0xFF63A2C5,
+0xFF64A3C6,
+0xFF66A5C8,
+0xFF66A5C8,
+0xFF67A6C9,
+0xFF67A6C9,
+0xFF67A6C7,
+0xFF67A6C7,
+0xFF68A7C8,
+0xFF68A7C8,
+0xFF6AA6C8,
+0xFF6BA7C9,
+0xFF6BA7C9,
+0xFF6CA8CA,
+0xFF6CA8CA,
+0xFF6BA7C9,
+0xFF6AA6C8,
+0xFF68A7C8,
+0xFF67A6C9,
+0xFF67A6C9,
+0xFF67A6C9,
+0xFF67A6C9,
+0xFF67A6C9,
+0xFF66A5C8,
+0xFF66A5C8,
+0xFF66A5C8,
+0xFF64A3C6,
+0xFF63A3C7,
+0xFF62A2C6,
+0xFF60A2C5,
+0xFF61A1C5,
+0xFF5FA1C4,
+0xFF5FA1C4,
+0xFF5FA1C4,
+0xFF5D9EC4,
+0xFF5E9FC5,
+0xFF5D9EC4,
+0xFF5C9DC3,
+0xFF5B9CC2,
+0xFF599DC4,
+0xFF599DC4,
+0xFF579BC2,
+0xFF599CC6,
+0xFF589BC6,
+0xFF579AC5,
+0xFF5699C4,
+0xFF5598C3,
+0xFF5499C3,
+0xFF5398C2,
+0xFF5398C2,
+0xFF5296C3,
+0xFF5297C1,
+0xFF5097C3,
+0xFF4F96C0,
+0xFF4E95C1,
+0xFF4E95BF,
+0xFF4E95C1,
+0xFF4C95C0,
+0xFF4A93BE,
+0xFF4994BE,
+0xFF4992BD,
+0xFF4893BD,
+0xFF4992BD,
+0xFF4792BC,
+0xFF4690BD,
+0xFF458FBC,
+0xFF448EBB,
+0xFF4390BC,
+0xFF428FBB,
+0xFF428FBB,
+0xFF408EBC,
+0xFF3F8DBB,
+0xFF3D8EBB,
+0xFF3C8DBA,
+0xFF3A8CBC,
+0xFF398BBB,
+0xFF398BBB,
+0xFF388ABA,
+0xFF398AB9,
+0xFF3889B8,
+0xFF3A88B8,
+0xFF3A88B8,
+0xFF3A88B8,
+0xFF3A88B8,
+0xFF3B87B8,
+0xFF3B87B8,
+0xFF3A87B5,
+0xFF3986B4,
+0xFF3986B4,
+0xFF3A87B5,
+0xFF3B85B2,
+0xFF3784B0,
+0xFF3583B1,
+0xFF3583B1,
+0xFF3882B1,
+0xFF3982AF,
+0xFF3B7FAC,
+0xFF3A7FA9,
+0xFF3C7FAC,
+0xFF397DAC,
+0xFF377EAC,
+0xFF3A7EAB,
+0xFF3D7CA5,
+0xFF3C7799,
+0xFF3F718C,
+0xFF4D7083,
+0xFFEFFDFF,
+0xFFFCFFFF,
+0xFFFCFCFE,
+0xFFFCFBF9,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFEFDFB,
+0xFFFDFDFB,
+0xFFFDFFFE,
+0xFFF9FFFF,
+0xFFF5FFFF,
+0xFFF0FFFF,
+0xFF3F5968,
+0xFF2F5268,
+0xFF2A5977,
+0xFF32688A,
+0xFF376F90,
+0xFF3A7293,
+0xFF397194,
+0xFF376F92,
+0xFF377196,
+0xFF387297,
+0xFF377398,
+0xFF357398,
+0xFF36749B,
+0xFF35759B,
+0xFF35759B,
+0xFF35759B,
+0xFF36769C,
+0xFF36759E,
+0xFF35769E,
+0xFF36779F,
+0xFF3879A1,
+0xFF3879A1,
+0xFF397AA4,
+0xFF3879A3,
+0xFF3679A3,
+0xFF3679A3,
+0xFF3578A2,
+0xFF3679A3,
+0xFF387BA5,
+0xFF3A7DA7,
+0xFF3C7FA9,
+0xFF3C7FA9,
+0xFF3B7EA8,
+0xFF397EA8,
+0xFF357CA8,
+0xFF367FAC,
+0xFF3881AE,
+0xFF3982AF,
+0xFF3982AF,
+0xFF3A84B1,
+0xFF3B85B4,
+0xFF3C86B5,
+0xFF3C86B5,
+0xFF3C86B5,
+0xFF3A87B5,
+0xFF3B88B6,
+0xFF3B87B8,
+0xFF3B87B8,
+0xFF3B87B8,
+0xFF3B87B8,
+0xFF3B89BA,
+0xFF3B89BA,
+0xFF3B89BA,
+0xFF3C8ABB,
+0xFF3B8BBC,
+0xFF3B8BBC,
+0xFF3C8CBD,
+0xFF3C8CBD,
+0xFF3C8CBD,
+0xFF3D8DBE,
+0xFF3F8DBE,
+0xFF408EBE,
+0xFF428EBF,
+0xFF428EBF,
+0xFF428EBF,
+0xFF428FBD,
+0xFF4690BD,
+0xFF4690BD,
+0xFF4791BE,
+0xFF4791BE,
+0xFF4892BF,
+0xFF4993C0,
+0xFF4993C0,
+0xFF4A95BF,
+0xFF4B94BF,
+0xFF4B94BF,
+0xFF4C93BF,
+0xFF4D94C0,
+0xFF4E95BF,
+0xFF4F96C0,
+0xFF5297C1,
+0xFF5297C1,
+0xFF5398C1,
+0xFF5398BF,
+0xFF5499C2,
+0xFF5599C0,
+0xFF569AC1,
+0xFF5A9BC1,
+0xFF5B9CC4,
+0xFF5B9CC2,
+0xFF5C9DC3,
+0xFF5D9DC1,
+0xFF5D9DC1,
+0xFF5E9EC2,
+0xFF5E9EC2,
+0xFF5F9FC2,
+0xFF5F9FC2,
+0xFF5F9FC2,
+0xFF609FC2,
+0xFF609FC2,
+0xFF639FC3,
+0xFF61A0C3,
+0xFF64A0C4,
+0xFF62A1C4,
+0xFF65A1C5,
+0xFF65A1C5,
+0xFF66A2C4,
+0xFF67A3C5,
+0xFF67A3C5,
+0xFF68A4C6,
+0xFF68A4C6,
+0xFF68A4C6,
+0xFF69A5C7,
+0xFF69A5C7,
+0xFF6AA5C7,
+0xFF6AA5C7,
+0xFF6BA6C8,
+0xFF6BA6C8,
+0xFF6BA6C8,
+0xFF6BA6C8,
+0xFF6AA5C7,
+0xFF69A5C7,
+0xFF69A5C7,
+0xFF68A4C6,
+0xFF68A4C6,
+0xFF68A4C6,
+0xFF68A4C6,
+0xFF68A4C6,
+0xFF67A3C5,
+0xFF64A3C4,
+0xFF63A2C3,
+0xFF63A2C5,
+0xFF62A1C4,
+0xFF61A1C4,
+0xFF61A0C3,
+0xFF5F9FC2,
+0xFF5F9FC2,
+0xFF5F9FC2,
+0xFF5F9FC3,
+0xFF60A0C4,
+0xFF5F9FC3,
+0xFF5E9EC2,
+0xFF5E9EC2,
+0xFF5C9DC3,
+0xFF5C9DC3,
+0xFF599DC4,
+0xFF589BC5,
+0xFF579CC5,
+0xFF559AC3,
+0xFF5499C2,
+0xFF5398C1,
+0xFF5398C1,
+0xFF5398C1,
+0xFF5199C1,
+0xFF5097C1,
+0xFF4F97BF,
+0xFF4F96C0,
+0xFF4E96BE,
+0xFF4C95BE,
+0xFF4C96BD,
+0xFF4C95BE,
+0xFF4B94BD,
+0xFF4B96C0,
+0xFF4996C2,
+0xFF4A94C1,
+0xFF4794C0,
+0xFF4993C0,
+0xFF4693BF,
+0xFF4592BE,
+0xFF4491BD,
+0xFF428FBD,
+0xFF428FBD,
+0xFF428FBD,
+0xFF418FBD,
+0xFF408EBC,
+0xFF3F8DBB,
+0xFF3C8DBA,
+0xFF3B8CB9,
+0xFF3B8DBD,
+0xFF3B8DBD,
+0xFF3B8DBD,
+0xFF3A8CBC,
+0xFF3A8ABB,
+0xFF3A8ABB,
+0xFF3B89BA,
+0xFF3B89BA,
+0xFF3987B8,
+0xFF3987B8,
+0xFF3987B7,
+0xFF3987B7,
+0xFF3886B6,
+0xFF3785B5,
+0xFF3785B5,
+0xFF3986B4,
+0xFF3B84AF,
+0xFF3A83AC,
+0xFF3882AF,
+0xFF3781AE,
+0xFF3781AE,
+0xFF3980AC,
+0xFF3B7EA9,
+0xFF3B7EA8,
+0xFF3B7BA7,
+0xFF3B7EA9,
+0xFF367AA7,
+0xFF387BA6,
+0xFF3A789D,
+0xFF3A6F8F,
+0xFF3C6980,
+0xFF98B5C5,
+0xFFF8FFFF,
+0xFFFFFFFF,
+0xFFFEFCFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFEFEFC,
+0xFFFEFEFE,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFAFFFF,
+0xFFF7FFFF,
+0xFFEEFFFF,
+0xFF7D97A6,
+0xFF29495E,
+0xFF2B556E,
+0xFF2D5F80,
+0xFF346C8F,
+0xFF387091,
+0xFF397192,
+0xFF397194,
+0xFF387093,
+0xFF387297,
+0xFF377398,
+0xFF35739A,
+0xFF35739A,
+0xFF35749D,
+0xFF35759B,
+0xFF35759B,
+0xFF357599,
+0xFF37759A,
+0xFF36769A,
+0xFF36769C,
+0xFF36779F,
+0xFF3778A0,
+0xFF3879A1,
+0xFF397AA4,
+0xFF3879A3,
+0xFF3679A3,
+0xFF3679A3,
+0xFF397CA6,
+0xFF397CA6,
+0xFF387BA5,
+0xFF377AA4,
+0xFF387BA5,
+0xFF3A7DA7,
+0xFF3A7DA7,
+0xFF3A7DA7,
+0xFF3A7FA9,
+0xFF3980AC,
+0xFF3980AC,
+0xFF3980AC,
+0xFF3881AC,
+0xFF3982AD,
+0xFF3982AF,
+0xFF3A83B0,
+0xFF3B82B0,
+0xFF3A83B0,
+0xFF3B84B1,
+0xFF3C85B2,
+0xFF3C85B2,
+0xFF3D86B3,
+0xFF3D85B5,
+0xFF3C86B5,
+0xFF3D87B6,
+0xFF3D87B6,
+0xFF3D87B6,
+0xFF3C89B7,
+0xFF3D8AB8,
+0xFF3D8AB8,
+0xFF3E8ABB,
+0xFF3E8BB9,
+0xFF408CBD,
+0xFF418EBC,
+0xFF438DBC,
+0xFF448EBD,
+0xFF468EBE,
+0xFF468FBC,
+0xFF468FBC,
+0xFF4790BD,
+0xFF4891BC,
+0xFF4891BC,
+0xFF4A91BD,
+0xFF4992BD,
+0xFF4B92BE,
+0xFF4B94BF,
+0xFF4C93BF,
+0xFF4C93BD,
+0xFF4D94BE,
+0xFF4F94BE,
+0xFF4F94BE,
+0xFF5095BE,
+0xFF5196BF,
+0xFF5295BF,
+0xFF5396C0,
+0xFF5498BF,
+0xFF5596BC,
+0xFF5596BC,
+0xFF5596BC,
+0xFF5697BD,
+0xFF5898BC,
+0xFF5999BD,
+0xFF5B9BBF,
+0xFF5B9BBF,
+0xFF5C9BBE,
+0xFF5D9CBF,
+0xFF5D9CBF,
+0xFF5E9DC0,
+0xFF5F9EC1,
+0xFF5F9EBF,
+0xFF5F9EC1,
+0xFF5F9EBF,
+0xFF629EC2,
+0xFF639EC0,
+0xFF649EC3,
+0xFF65A0C2,
+0xFF66A0C5,
+0xFF67A2C4,
+0xFF67A2C4,
+0xFF68A3C5,
+0xFF68A3C5,
+0xFF68A3C3,
+0xFF69A4C6,
+0xFF69A4C4,
+0xFF6AA5C7,
+0xFF6AA5C5,
+0xFF6AA5C7,
+0xFF6BA6C6,
+0xFF6CA4C7,
+0xFF6DA5C6,
+0xFF6DA5C8,
+0xFF6BA6C6,
+0xFF6DA5C8,
+0xFF6BA6C6,
+0xFF6DA5C8,
+0xFF6BA6C6,
+0xFF6CA7C9,
+0xFF6BA6C6,
+0xFF6AA5C7,
+0xFF6AA5C5,
+0xFF6AA5C7,
+0xFF6AA5C5,
+0xFF69A4C6,
+0xFF67A2C2,
+0xFF66A2C4,
+0xFF66A2C4,
+0xFF65A1C3,
+0xFF64A0C2,
+0xFF639FC1,
+0xFF639FC1,
+0xFF609FC0,
+0xFF609FC2,
+0xFF5F9EC1,
+0xFF5F9EC1,
+0xFF5E9DC0,
+0xFF5E9DC0,
+0xFF5D9CBF,
+0xFF5C9ABF,
+0xFF5B9BBF,
+0xFF5A9AC0,
+0xFF5C9DC3,
+0xFF599DC4,
+0xFF579BC2,
+0xFF569AC1,
+0xFF5599C0,
+0xFF5498BF,
+0xFF5498BF,
+0xFF5398BF,
+0xFF5398BF,
+0xFF5297BE,
+0xFF5196BD,
+0xFF5095BC,
+0xFF4F94BB,
+0xFF4C94BA,
+0xFF4C94BA,
+0xFF4C94BC,
+0xFF4A93BC,
+0xFF4994BE,
+0xFF4992BD,
+0xFF4992BD,
+0xFF4891BC,
+0xFF4891BC,
+0xFF4790BB,
+0xFF468FBA,
+0xFF4790BB,
+0xFF4691BB,
+0xFF4690BD,
+0xFF458FBC,
+0xFF438DBA,
+0xFF428CB9,
+0xFF3F8CB8,
+0xFF3F8CB8,
+0xFF3D8BB9,
+0xFF3D8BB9,
+0xFF3C8ABA,
+0xFF3C8AB8,
+0xFF3C88B9,
+0xFF3C89B7,
+0xFF3D87B6,
+0xFF3D87B6,
+0xFF3E88B7,
+0xFF3E88B7,
+0xFF3D87B6,
+0xFF3D87B4,
+0xFF3B85B4,
+0xFF3B85B2,
+0xFF3A84B1,
+0xFF3B84AF,
+0xFF3E83AC,
+0xFF3F83AA,
+0xFF3B82AC,
+0xFF3982AD,
+0xFF3A81AD,
+0xFF3C81AB,
+0xFF3E7FA7,
+0xFF3E7EA4,
+0xFF3E7EA4,
+0xFF3C7DA5,
+0xFF3C7DA7,
+0xFF407FA8,
+0xFF387093,
+0xFF3B6A86,
+0xFF375A6E,
+0xFFEEFFFF,
+0xFFF7FCFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFEFEFC,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFDFCFA,
+0xFFFEFFFF,
+0xFFF8FFFF,
+0xFFF1FFFF,
+0xFFD6EDFB,
+0xFF204055,
+0xFF274F69,
+0xFF22516F,
+0xFF366B8D,
+0xFF3A7295,
+0xFF397194,
+0xFF387093,
+0xFF397196,
+0xFF397196,
+0xFF387298,
+0xFF357196,
+0xFF35739A,
+0xFF35739A,
+0xFF34749A,
+0xFF35759B,
+0xFF36749B,
+0xFF37759A,
+0xFF37759A,
+0xFF36769A,
+0xFF37779D,
+0xFF36779F,
+0xFF3778A0,
+0xFF3879A1,
+0xFF3879A3,
+0xFF3879A3,
+0xFF377AA4,
+0xFF377AA4,
+0xFF3477A1,
+0xFF387BA5,
+0xFF3D7EA6,
+0xFF3C7DA5,
+0xFF3B7CA4,
+0xFF3B7CA4,
+0xFF3E7FA7,
+0xFF3F80A8,
+0xFF3C7FA9,
+0xFF3C7FA9,
+0xFF3C7FA9,
+0xFF3E81AB,
+0xFF4083AD,
+0xFF4285AF,
+0xFF4386B0,
+0xFF4386B0,
+0xFF4687B1,
+0xFF4487B1,
+0xFF4588B2,
+0xFF4689B3,
+0xFF4689B3,
+0xFF478AB4,
+0xFF478AB5,
+0xFF478AB5,
+0xFF478AB5,
+0xFF478CB6,
+0xFF478CB6,
+0xFF478CB6,
+0xFF488DB7,
+0xFF478EB8,
+0xFF478EBA,
+0xFF478EB8,
+0xFF4990BC,
+0xFF4A91BB,
+0xFF4C91BB,
+0xFF4D92BC,
+0xFF4F92BD,
+0xFF4F92BC,
+0xFF5093BD,
+0xFF5093BD,
+0xFF5296BD,
+0xFF5296BD,
+0xFF5495BD,
+0xFF5397BE,
+0xFF5596BE,
+0xFF5498BF,
+0xFF5697BF,
+0xFF5697BD,
+0xFF5798BE,
+0xFF5898BE,
+0xFF5999BF,
+0xFF5999BF,
+0xFF5A9AC0,
+0xFF5B99BE,
+0xFF5C9ABF,
+0xFF5C9ABF,
+0xFF619DC1,
+0xFF619DC1,
+0xFF619DC1,
+0xFF619DC1,
+0xFF639DC2,
+0xFF649EC3,
+0xFF66A1C3,
+0xFF66A1C3,
+0xFF66A1C3,
+0xFF66A1C3,
+0xFF67A2C4,
+0xFF68A3C5,
+0xFF68A3C5,
+0xFF68A3C3,
+0xFF68A3C5,
+0xFF69A4C4,
+0xFF6BA3C6,
+0xFF6CA4C5,
+0xFF6CA4C7,
+0xFF6DA5C6,
+0xFF6EA6C9,
+0xFF6FA7C8,
+0xFF6FA7C8,
+0xFF6FA7C8,
+0xFF70A8C9,
+0xFF70A9C7,
+0xFF71A9CA,
+0xFF71AAC8,
+0xFF71A9CA,
+0xFF71AAC8,
+0xFF72AACB,
+0xFF73ACCA,
+0xFF72A8CA,
+0xFF72A9C8,
+0xFF73A9CB,
+0xFF72ABC9,
+0xFF73A9CB,
+0xFF72ABC9,
+0xFF73A9CB,
+0xFF72ABC9,
+0xFF74ACCD,
+0xFF72ABC9,
+0xFF71A9CA,
+0xFF71AAC8,
+0xFF72AACB,
+0xFF72ABC9,
+0xFF70A8C9,
+0xFF6FA8C6,
+0xFF6FA7C8,
+0xFF6FA7C8,
+0xFF6EA6C7,
+0xFF6DA5C6,
+0xFF6DA5C6,
+0xFF6CA4C5,
+0xFF6AA5C5,
+0xFF6AA5C7,
+0xFF69A4C6,
+0xFF68A3C5,
+0xFF68A3C5,
+0xFF68A3C5,
+0xFF67A2C4,
+0xFF67A1C6,
+0xFF66A0C5,
+0xFF65A1C5,
+0xFF62A1C4,
+0xFF61A0C3,
+0xFF609FC2,
+0xFF5F9EC1,
+0xFF5E9DC0,
+0xFF5C9CBF,
+0xFF5C9CC0,
+0xFF5C9CC0,
+0xFF5C9CC0,
+0xFF5B9BBF,
+0xFF5A9ABE,
+0xFF599BBE,
+0xFF589ABD,
+0xFF5799BC,
+0xFF5799BC,
+0xFF5599BE,
+0xFF5498BF,
+0xFF5297BE,
+0xFF5397BE,
+0xFF5296BD,
+0xFF5296BD,
+0xFF5296BD,
+0xFF5195BC,
+0xFF5094BB,
+0xFF4E92B9,
+0xFF4E92B9,
+0xFF4E91BB,
+0xFF4C91BA,
+0xFF4B90B9,
+0xFF4A8FB8,
+0xFF498EB7,
+0xFF498EB8,
+0xFF468DB7,
+0xFF458CB6,
+0xFF458CB8,
+0xFF458CB6,
+0xFF468AB7,
+0xFF468BB5,
+0xFF468BB5,
+0xFF468BB5,
+0xFF4388B2,
+0xFF4388B2,
+0xFF4388B2,
+0xFF4287B0,
+0xFF4186B0,
+0xFF4186AF,
+0xFF4186AF,
+0xFF4286AD,
+0xFF4583A8,
+0xFF4482A7,
+0xFF4283AB,
+0xFF4083AD,
+0xFF4182AA,
+0xFF4282A8,
+0xFF4480A4,
+0xFF4580A2,
+0xFF437FA3,
+0xFF407EA3,
+0xFF417FA6,
+0xFF3B779C,
+0xFF356788,
+0xFF3F6780,
+0xFF678190,
+0xFFF4FFFF,
+0xFFFEFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFEFEFE,
+0xFFFDFDFD,
+0xFFFEFFFF,
+0xFFFEFFFD,
+0xFFFDFFFC,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFBFDFC,
+0xFFF8FFFF,
+0xFFF2FFFF,
+0xFF4B6677,
+0xFF294F66,
+0xFF245371,
+0xFF366B8D,
+0xFF397194,
+0xFF3B7396,
+0xFF376F92,
+0xFF376F92,
+0xFF3A7297,
+0xFF377196,
+0xFF387298,
+0xFF357196,
+0xFF377398,
+0xFF357398,
+0xFF35739A,
+0xFF367499,
+0xFF367499,
+0xFF37759A,
+0xFF36769A,
+0xFF36769A,
+0xFF36779F,
+0xFF3778A0,
+0xFF3778A0,
+0xFF3778A0,
+0xFF3778A2,
+0xFF3879A3,
+0xFF377AA4,
+0xFF387BA5,
+0xFF387BA5,
+0xFF387BA5,
+0xFF397AA2,
+0xFF397AA2,
+0xFF3C7DA5,
+0xFF4081A9,
+0xFF4181A7,
+0xFF3F7FA5,
+0xFF3F7DA2,
+0xFF3B799E,
+0xFF357398,
+0xFF306E93,
+0xFF2A688D,
+0xFF246287,
+0xFF225E83,
+0xFF205C81,
+0xFF205C81,
+0xFF205C81,
+0xFF205C81,
+0xFF205C81,
+0xFF205C81,
+0xFF205C81,
+0xFF205C81,
+0xFF205C81,
+0xFF205C81,
+0xFF1F5D82,
+0xFF1F5D82,
+0xFF1F5D82,
+0xFF1F5D84,
+0xFF1F5F85,
+0xFF1F5F85,
+0xFF1F5F85,
+0xFF1E5E84,
+0xFF1E5E82,
+0xFF1F5D82,
+0xFF205E83,
+0xFF225E83,
+0xFF235F83,
+0xFF235F83,
+0xFF235F83,
+0xFF246084,
+0xFF246084,
+0xFF246084,
+0xFF246084,
+0xFF246084,
+0xFF246084,
+0xFF256183,
+0xFF256183,
+0xFF266183,
+0xFF266183,
+0xFF266183,
+0xFF266183,
+0xFF296182,
+0xFF296182,
+0xFF2A6082,
+0xFF2A6082,
+0xFF286081,
+0xFF286081,
+0xFF286081,
+0xFF286081,
+0xFF2A6082,
+0xFF2B6183,
+0xFF2B6183,
+0xFF2C6382,
+0xFF2B6183,
+0xFF2B6281,
+0xFF2C6284,
+0xFF2C6382,
+0xFF2C6284,
+0xFF2C6382,
+0xFF2D6385,
+0xFF2D6483,
+0xFF2E6385,
+0xFF2E6383,
+0xFF2E6385,
+0xFF2E6383,
+0xFF2E6385,
+0xFF2E6383,
+0xFF2E6383,
+0xFF2E6382,
+0xFF2F6484,
+0xFF2F6483,
+0xFF306585,
+0xFF306584,
+0xFF306585,
+0xFF306584,
+0xFF306585,
+0xFF316685,
+0xFF306585,
+0xFF306584,
+0xFF316686,
+0xFF316685,
+0xFF316686,
+0xFF316685,
+0xFF316686,
+0xFF306785,
+0xFF316686,
+0xFF306785,
+0xFF306585,
+0xFF2F6684,
+0xFF316686,
+0xFF316886,
+0xFF326787,
+0xFF316685,
+0xFF326787,
+0xFF326786,
+0xFF316686,
+0xFF316685,
+0xFF316686,
+0xFF316686,
+0xFF306786,
+0xFF306786,
+0xFF316887,
+0xFF306786,
+0xFF306688,
+0xFF306688,
+0xFF306688,
+0xFF2F6587,
+0xFF2F6587,
+0xFF2F6587,
+0xFF306889,
+0xFF306889,
+0xFF306889,
+0xFF306889,
+0xFF306889,
+0xFF306889,
+0xFF2E698B,
+0xFF2E698B,
+0xFF2E698B,
+0xFF2D688A,
+0xFF2D688A,
+0xFF2D688A,
+0xFF2C688A,
+0xFF2C688A,
+0xFF2C688A,
+0xFF2C688A,
+0xFF2B6A8D,
+0xFF2B6A8D,
+0xFF2A698C,
+0xFF2B6A8D,
+0xFF2D698D,
+0xFF2D698D,
+0xFF2C688C,
+0xFF2C688C,
+0xFF2D698D,
+0xFF2D698D,
+0xFF2D698D,
+0xFF2B6A8D,
+0xFF2B698E,
+0xFF2B698E,
+0xFF2B698E,
+0xFF2B698E,
+0xFF2C6A91,
+0xFF2B6B91,
+0xFF2C6A91,
+0xFF2C6A91,
+0xFF2C6A91,
+0xFF2C6A8F,
+0xFF2C6A8F,
+0xFF2C6A8F,
+0xFF2C6A8F,
+0xFF2D6B90,
+0xFF2D6B90,
+0xFF2D6B90,
+0xFF2C6A8F,
+0xFF2C6B8E,
+0xFF2D6C8F,
+0xFF2F6B8D,
+0xFF31698A,
+0xFF31698A,
+0xFF2E6A8F,
+0xFF2B6B8F,
+0xFF2C6A8F,
+0xFF2E6A8C,
+0xFF306987,
+0xFF316886,
+0xFF306987,
+0xFF336B8C,
+0xFF326C91,
+0xFF2F6587,
+0xFF3A6784,
+0xFF2D4D62,
+0xFFD0E2EE,
+0xFFF8FFFF,
+0xFFFFFEFF,
+0xFFFFFDFE,
+0xFFFFFFFF,
+0xFFFDFFFE,
+0xFFFDFFFE,
+0xFFFEFFFF,
+0xFFFEFFFD,
+0xFFFEFFFD,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFB,
+0xFFFFFFFD,
+0xFFFBFCFE,
+0xFFF8FFFF,
+0xFFBDD1DC,
+0xFF1D3C50,
+0xFF305975,
+0xFF2A5F81,
+0xFF346E93,
+0xFF356F94,
+0xFF377196,
+0xFF336D92,
+0xFF356F94,
+0xFF387297,
+0xFF367095,
+0xFF377196,
+0xFF387297,
+0xFF387297,
+0xFF387297,
+0xFF377398,
+0xFF357398,
+0xFF367499,
+0xFF36769C,
+0xFF35769E,
+0xFF34759D,
+0xFF36779F,
+0xFF36779F,
+0xFF3778A0,
+0xFF3778A0,
+0xFF3778A2,
+0xFF3879A3,
+0xFF397AA4,
+0xFF397AA4,
+0xFF3778A0,
+0xFF3A7BA3,
+0xFF3C7DA5,
+0xFF3D7EA6,
+0xFF3D7DA3,
+0xFF36769C,
+0xFF2A688F,
+0xFF205C81,
+0xFF1F577A,
+0xFF1F5577,
+0xFF1E5476,
+0xFF1E5476,
+0xFF1F5675,
+0xFF1F5675,
+0xFF205776,
+0xFF215877,
+0xFF205575,
+0xFF215676,
+0xFF215676,
+0xFF205575,
+0xFF1F5474,
+0xFF1F5474,
+0xFF1F5474,
+0xFF205575,
+0xFF1F5473,
+0xFF205574,
+0xFF215675,
+0xFF205574,
+0xFF1F5474,
+0xFF1F5675,
+0xFF205776,
+0xFF1F5675,
+0xFF1F5675,
+0xFF1F5675,
+0xFF205575,
+0xFF205574,
+0xFF225574,
+0xFF225574,
+0xFF225574,
+0xFF225574,
+0xFF205574,
+0xFF1F5474,
+0xFF1F5474,
+0xFF1F5474,
+0xFF1F5473,
+0xFF1F5473,
+0xFF1F5473,
+0xFF1F5473,
+0xFF1E5372,
+0xFF1F5473,
+0xFF215471,
+0xFF215471,
+0xFF225371,
+0xFF225371,
+0xFF225371,
+0xFF215270,
+0xFF215473,
+0xFF1F5474,
+0xFF215374,
+0xFF225475,
+0xFF225475,
+0xFF225475,
+0xFF225475,
+0xFF225574,
+0xFF225475,
+0xFF225574,
+0xFF225475,
+0xFF225574,
+0xFF225475,
+0xFF225574,
+0xFF205575,
+0xFF215675,
+0xFF245677,
+0xFF245776,
+0xFF245677,
+0xFF235675,
+0xFF235576,
+0xFF235675,
+0xFF235675,
+0xFF235673,
+0xFF235675,
+0xFF245774,
+0xFF245776,
+0xFF245774,
+0xFF235675,
+0xFF235673,
+0xFF245776,
+0xFF245774,
+0xFF255877,
+0xFF255875,
+0xFF255877,
+0xFF255875,
+0xFF255877,
+0xFF255875,
+0xFF255877,
+0xFF235975,
+0xFF255877,
+0xFF235975,
+0xFF255877,
+0xFF235975,
+0xFF255877,
+0xFF245A76,
+0xFF275A79,
+0xFF275A77,
+0xFF285979,
+0xFF285977,
+0xFF285979,
+0xFF285977,
+0xFF275A79,
+0xFF285B7A,
+0xFF285B7A,
+0xFF285B7A,
+0xFF285B7A,
+0xFF275A79,
+0xFF27597A,
+0xFF285A7B,
+0xFF265B7B,
+0xFF255A7A,
+0xFF255A7A,
+0xFF285A7B,
+0xFF295A7A,
+0xFF295A7A,
+0xFF295A7A,
+0xFF2A5B7B,
+0xFF295C7B,
+0xFF295C7B,
+0xFF295C7B,
+0xFF295C7B,
+0xFF285D7C,
+0xFF285D7C,
+0xFF285D7C,
+0xFF285D7C,
+0xFF285D7C,
+0xFF285D7C,
+0xFF295E7D,
+0xFF295E7D,
+0xFF275E7C,
+0xFF275E7C,
+0xFF285D7C,
+0xFF295E7D,
+0xFF2A5F7E,
+0xFF2A5F7E,
+0xFF2C5E7F,
+0xFF2B5D7E,
+0xFF2B5D7E,
+0xFF2B5D7E,
+0xFF2B5D7E,
+0xFF295E7E,
+0xFF2A5F7F,
+0xFF2A5F7F,
+0xFF2B6080,
+0xFF2B6080,
+0xFF2A5F7F,
+0xFF29607F,
+0xFF2A5F7F,
+0xFF2A5F7F,
+0xFF2A5F7F,
+0xFF2B6080,
+0xFF2B6080,
+0xFF2B607F,
+0xFF2A5F7E,
+0xFF2A5F7E,
+0xFF2B607F,
+0xFF2B607F,
+0xFF2B607F,
+0xFF2A617F,
+0xFF2B6280,
+0xFF2C627E,
+0xFF2F607E,
+0xFF2E617E,
+0xFF2B6384,
+0xFF296486,
+0xFF296486,
+0xFF2B6482,
+0xFF2C627E,
+0xFF2E617C,
+0xFF2D637F,
+0xFF2B607F,
+0xFF2B6183,
+0xFF2F6281,
+0xFF335B75,
+0xFF415C6F,
+0xFFF5FFFF,
+0xFFFCFFFF,
+0xFFFFFDFF,
+0xFFFEFCFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFCFFFF,
+0xFFFCFEFB,
+0xFFFEFFFD,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFBFFFF,
+0xFFF4FFFF,
+0xFF46606F,
+0xFF30546C,
+0xFF275674,
+0xFF346A8E,
+0xFF387297,
+0xFF346E93,
+0xFF367095,
+0xFF346E93,
+0xFF377196,
+0xFF387297,
+0xFF346E93,
+0xFF367095,
+0xFF397398,
+0xFF387298,
+0xFF377397,
+0xFF377397,
+0xFF357398,
+0xFF36749B,
+0xFF36759E,
+0xFF3576A0,
+0xFF34759F,
+0xFF3576A0,
+0xFF36779F,
+0xFF3778A0,
+0xFF367AA1,
+0xFF367AA1,
+0xFF367AA1,
+0xFF3879A1,
+0xFF3A7AA0,
+0xFF3D7DA3,
+0xFF3D7BA0,
+0xFF367499,
+0xFF28668B,
+0xFF1E5A7E,
+0xFF1B557A,
+0xFF1F577A,
+0xFF265879,
+0xFF27556F,
+0xFF275169,
+0xFF264E67,
+0xFF234B64,
+0xFF20495F,
+0xFF1D465C,
+0xFF1C455B,
+0xFF1F455C,
+0xFF20465D,
+0xFF21455B,
+0xFF21455D,
+0xFF21455D,
+0xFF20445C,
+0xFF1F455C,
+0xFF21455D,
+0xFF21455B,
+0xFF20445A,
+0xFF22465C,
+0xFF22465C,
+0xFF21455B,
+0xFF20445A,
+0xFF21455B,
+0xFF20465D,
+0xFF20465B,
+0xFF20465D,
+0xFF20465B,
+0xFF21455B,
+0xFF20445A,
+0xFF20445A,
+0xFF21445A,
+0xFF214458,
+0xFF214458,
+0xFF20445A,
+0xFF20445A,
+0xFF20445C,
+0xFF1F4359,
+0xFF1F4359,
+0xFF1F4359,
+0xFF1F4359,
+0xFF1F4359,
+0xFF1F4359,
+0xFF1F4359,
+0xFF1F4457,
+0xFF204357,
+0xFF204357,
+0xFF204357,
+0xFF1F4256,
+0xFF1F4258,
+0xFF1F435B,
+0xFF1E445B,
+0xFF1F435B,
+0xFF1F435B,
+0xFF1F435B,
+0xFF1E425A,
+0xFF1E425A,
+0xFF1E425A,
+0xFF1F435B,
+0xFF1F435B,
+0xFF1F435B,
+0xFF1E425A,
+0xFF1E425A,
+0xFF1E425A,
+0xFF1E445B,
+0xFF1E445B,
+0xFF1D4159,
+0xFF1D4159,
+0xFF1E425A,
+0xFF1E425A,
+0xFF1E425A,
+0xFF1E425A,
+0xFF1E425A,
+0xFF1E4258,
+0xFF1F435B,
+0xFF1F4359,
+0xFF1F435B,
+0xFF1F4359,
+0xFF1F435B,
+0xFF1F4359,
+0xFF1F435B,
+0xFF1F4359,
+0xFF1E425A,
+0xFF1E4258,
+0xFF1E425A,
+0xFF1E4258,
+0xFF1E425A,
+0xFF1F4359,
+0xFF1E445B,
+0xFF1E4459,
+0xFF1E445B,
+0xFF1E4459,
+0xFF1E445B,
+0xFF1E4459,
+0xFF1E445B,
+0xFF1E4459,
+0xFF1F455C,
+0xFF1F455A,
+0xFF1E425A,
+0xFF1E4258,
+0xFF20425B,
+0xFF1F4359,
+0xFF20445C,
+0xFF20445A,
+0xFF21455D,
+0xFF21455D,
+0xFF21455D,
+0xFF20445C,
+0xFF20445C,
+0xFF22465E,
+0xFF21475E,
+0xFF20465D,
+0xFF20455F,
+0xFF224660,
+0xFF22445D,
+0xFF23465C,
+0xFF23455E,
+0xFF23465C,
+0xFF23455E,
+0xFF22465C,
+0xFF23455E,
+0xFF21455B,
+0xFF23475F,
+0xFF23475D,
+0xFF23475F,
+0xFF23475D,
+0xFF23475F,
+0xFF23475D,
+0xFF23475F,
+0xFF23475D,
+0xFF22485D,
+0xFF22485D,
+0xFF23475D,
+0xFF24485E,
+0xFF25495F,
+0xFF264A60,
+0xFF264A60,
+0xFF264A60,
+0xFF254760,
+0xFF24485E,
+0xFF254760,
+0xFF24485E,
+0xFF254961,
+0xFF25495F,
+0xFF264A62,
+0xFF264A60,
+0xFF254961,
+0xFF25495F,
+0xFF254961,
+0xFF25495F,
+0xFF254961,
+0xFF264A60,
+0xFF264A60,
+0xFF274B61,
+0xFF274B61,
+0xFF274B61,
+0xFF274B61,
+0xFF274B61,
+0xFF274B61,
+0xFF274B61,
+0xFF264C5F,
+0xFF284D60,
+0xFF284B5F,
+0xFF274B61,
+0xFF254D66,
+0xFF244E66,
+0xFF244E66,
+0xFF244E64,
+0xFF274D60,
+0xFF284D5F,
+0xFF264C5F,
+0xFF284E63,
+0xFF285167,
+0xFF264A60,
+0xFF2C495B,
+0xFFBDCFDB,
+0xFFF9FFFF,
+0xFFFEFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFCFDFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFDFFFE,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFDFE,
+0xFFFFFDFE,
+0xFFFEFFFF,
+0xFFF5FFFF,
+0xFFBED8E7,
+0xFF22465E,
+0xFF2A5577,
+0xFF306084,
+0xFF366B8D,
+0xFF396F91,
+0xFF376F90,
+0xFF376F92,
+0xFF387093,
+0xFF397194,
+0xFF397196,
+0xFF367095,
+0xFF367297,
+0xFF357398,
+0xFF35739A,
+0xFF357599,
+0xFF37779B,
+0xFF37759A,
+0xFF35739A,
+0xFF36749D,
+0xFF3776A1,
+0xFF34739E,
+0xFF3978A3,
+0xFF3778A2,
+0xFF33779E,
+0xFF357AA1,
+0xFF327B9E,
+0xFF377D9F,
+0xFF387A9D,
+0xFF3E7DA0,
+0xFF346F91,
+0xFF21597A,
+0xFF235A79,
+0xFF245979,
+0xFF235675,
+0xFF275674,
+0xFF224B69,
+0xFF21455F,
+0xFF324D5E,
+0xFF506673,
+0xFF798C9A,
+0xFF9BAFBA,
+0xFFB4C6D0,
+0xFFC6D8E2,
+0xFFD6E7EF,
+0xFFE2F0F9,
+0xFFE1EFF8,
+0xFFE2EFF7,
+0xFFE2EFF8,
+0xFFE2EFF8,
+0xFFE2EFF8,
+0xFFE1EFF8,
+0xFFE2EFF8,
+0xFFE2EFF8,
+0xFFE2EFF8,
+0xFFE2EFF7,
+0xFFE2EFF7,
+0xFFE2EFF7,
+0xFFE2EFF7,
+0xFFE2EFF7,
+0xFFE2EFF8,
+0xFFE2EFF7,
+0xFFE2EFF8,
+0xFFE2EFF7,
+0xFFE2EFF7,
+0xFFE2EFF7,
+0xFFE2EFF7,
+0xFFE4EEF7,
+0xFFE4EEF7,
+0xFFE4EEF7,
+0xFFE2EFF7,
+0xFFE2EFF7,
+0xFFE2EFF8,
+0xFFE2EFF7,
+0xFFE2EFF7,
+0xFFE2EFF7,
+0xFFE2EFF7,
+0xFFE2EFF7,
+0xFFE2EFF7,
+0xFFE2EFF7,
+0xFFE2EFF7,
+0xFFE4EEF7,
+0xFFE4EEF7,
+0xFFE4EEF7,
+0xFFE4EEF7,
+0xFFE4EEF7,
+0xFFE2EFF8,
+0xFFE2EFF8,
+0xFFE2EFF8,
+0xFFE2EFF8,
+0xFFE2EFF8,
+0xFFE2EFF8,
+0xFFE2EFF8,
+0xFFE2EFF8,
+0xFFE2EFF8,
+0xFFE2EFF8,
+0xFFE2EFF8,
+0xFFE2EFF8,
+0xFFE2EFF8,
+0xFFE2EFF8,
+0xFFE2EFF8,
+0xFFE2EFF8,
+0xFFE2EFF8,
+0xFFE2EFF8,
+0xFFE2EFF8,
+0xFFE2EFF8,
+0xFFE2EFF8,
+0xFFE2EFF8,
+0xFFE2EFF8,
+0xFFE2EFF7,
+0xFFE2EFF8,
+0xFFE2EFF7,
+0xFFE2EFF8,
+0xFFE2EFF7,
+0xFFE2EFF8,
+0xFFE2EFF7,
+0xFFE2EFF8,
+0xFFE2EFF7,
+0xFFE2EFF8,
+0xFFE2EFF7,
+0xFFE2EFF8,
+0xFFE2EFF7,
+0xFFE2EFF8,
+0xFFE2EFF7,
+0xFFE2EFF8,
+0xFFE2EFF7,
+0xFFE2EFF8,
+0xFFE2EFF7,
+0xFFE2EFF8,
+0xFFE2EFF7,
+0xFFE2EFF8,
+0xFFE2EFF7,
+0xFFE2EFF8,
+0xFFE2EFF7,
+0xFFE2EFF8,
+0xFFE2EFF7,
+0xFFE4EEF8,
+0xFFE2EFF7,
+0xFFE2EFF8,
+0xFFE2EFF7,
+0xFFE2EFF8,
+0xFFE2EFF8,
+0xFFE2EFF8,
+0xFFE2EFF8,
+0xFFE2EFF8,
+0xFFE2EFF8,
+0xFFE2EFF8,
+0xFFE2EFF8,
+0xFFE2EFF8,
+0xFFE2EFF8,
+0xFFE4EEF8,
+0xFFE4EEF7,
+0xFFE4EEF8,
+0xFFE4EEF7,
+0xFFE4EEF8,
+0xFFE2EFF7,
+0xFFE4EEF8,
+0xFFE2EFF7,
+0xFFE2EFF8,
+0xFFE2EFF7,
+0xFFE2EFF8,
+0xFFE2EFF7,
+0xFFE2EFF8,
+0xFFE2EFF7,
+0xFFE2EFF8,
+0xFFE2EFF7,
+0xFFE3F0F8,
+0xFFE3F0F8,
+0xFFE2EFF7,
+0xFFE2EFF7,
+0xFFE2EFF7,
+0xFFE2EFF7,
+0xFFE2EFF7,
+0xFFE2EFF7,
+0xFFE4EEF8,
+0xFFE2EFF7,
+0xFFE4EEF8,
+0xFFE2EFF7,
+0xFFE2EFF8,
+0xFFE2EFF7,
+0xFFE2EFF8,
+0xFFE2EFF7,
+0xFFE2EFF8,
+0xFFE2EFF7,
+0xFFE2EFF8,
+0xFFE2EFF7,
+0xFFE2EFF8,
+0xFFE2EFF7,
+0xFFE2EFF7,
+0xFFE2EFF7,
+0xFFE2EFF7,
+0xFFE2EFF7,
+0xFFE2EFF7,
+0xFFE2EFF7,
+0xFFE2EFF7,
+0xFFE2EFF7,
+0xFFE2EFF7,
+0xFFE2EFF7,
+0xFFE4EFF5,
+0xFFE2EFF7,
+0xFFE2EFF7,
+0xFFE1F0F7,
+0xFFE1F0F7,
+0xFFE1F0F7,
+0xFFE2EFF5,
+0xFFE2EFF5,
+0xFFE2EFF5,
+0xFFE1EEF6,
+0xFFE2EFF7,
+0xFFE7F4FC,
+0xFFF2FBFF,
+0xFFFBFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFBFFFE,
+0xFFFBFFFC,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFDFF,
+0xFFFFFEFF,
+0xFFFBFFFF,
+0xFFF2FFFF,
+0xFF5B7E92,
+0xFF24516E,
+0xFF28587C,
+0xFF3A6B93,
+0xFF3B7092,
+0xFF356C8B,
+0xFF376F90,
+0xFF376F90,
+0xFF386E92,
+0xFF397194,
+0xFF397196,
+0xFF367095,
+0xFF367297,
+0xFF35739A,
+0xFF34749A,
+0xFF337397,
+0xFF347498,
+0xFF357398,
+0xFF347299,
+0xFF36749B,
+0xFF3875A1,
+0xFF36739F,
+0xFF37769F,
+0xFF33749C,
+0xFF377BA2,
+0xFF34789D,
+0xFF367A9F,
+0xFF3B7DA0,
+0xFF327192,
+0xFF215C7C,
+0xFF235A78,
+0xFF2A5C77,
+0xFF29576F,
+0xFF244C65,
+0xFF26495F,
+0xFF4C6B80,
+0xFF95B0C5,
+0xFFCEE3F4,
+0xFFF4FFFF,
+0xFFF7FFFF,
+0xFFF8FFFF,
+0xFFF9FFFF,
+0xFFF9FFFF,
+0xFFFBFFFF,
+0xFFFCFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFEFE,
+0xFFFEFEFE,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFDFDFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFBFFFE,
+0xFFFAFFFE,
+0xFFFEFFFB,
+0xFFFFFFFB,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFBFFFF,
+0xFFE6F8FF,
+0xFF234C62,
+0xFF275A79,
+0xFF2B5D80,
+0xFF3B6D92,
+0xFF386D8F,
+0xFF396F91,
+0xFF366E91,
+0xFF366E91,
+0xFF376F94,
+0xFF387095,
+0xFF387095,
+0xFF367095,
+0xFF357196,
+0xFF367297,
+0xFF367499,
+0xFF347396,
+0xFF357497,
+0xFF387498,
+0xFF377398,
+0xFF38739B,
+0xFF38769F,
+0xFF36759E,
+0xFF35779A,
+0xFF387A9D,
+0xFF3A789D,
+0xFF417CA4,
+0xFF386F98,
+0xFF265D84,
+0xFF266183,
+0xFF245D7A,
+0xFF235971,
+0xFF1F4E60,
+0xFF395A6B,
+0xFF99AFBD,
+0xFFEBF7FF,
+0xFFF8FFFF,
+0xFFF7FFFF,
+0xFFF7FFFF,
+0xFFF8FFFF,
+0xFFF9FFFF,
+0xFFF7FEFF,
+0xFFF9FEFF,
+0xFFFBFFFF,
+0xFFFCFFFF,
+0xFFFDFEFF,
+0xFFFCFCFC,
+0xFFFEFEFE,
+0xFFFEFEFE,
+0xFFFFFDFE,
+0xFFFEFEFE,
+0xFFFEFEFE,
+0xFFFEFEFF,
+0xFFFEFEFF,
+0xFFFEFEFF,
+0xFFFEFEFF,
+0xFFFEFEFF,
+0xFFFEFEFF,
+0xFFFEFEFF,
+0xFFFEFEFF,
+0xFFFEFEFF,
+0xFFFEFEFF,
+0xFFFEFEFF,
+0xFFFEFEFF,
+0xFFFEFEFF,
+0xFFFEFEFF,
+0xFFFEFEFF,
+0xFFFEFEFF,
+0xFFFEFEFF,
+0xFFFEFEFF,
+0xFFFEFEFF,
+0xFFFEFEFF,
+0xFFFEFEFF,
+0xFFFEFEFF,
+0xFFFEFEFF,
+0xFFFEFEFF,
+0xFFFEFEFF,
+0xFFFEFEFF,
+0xFFFEFEFF,
+0xFFFEFEFF,
+0xFFFEFEFF,
+0xFFFEFEFF,
+0xFFFEFEFF,
+0xFFFEFEFF,
+0xFFFEFEFF,
+0xFFFEFEFF,
+0xFFFEFEFF,
+0xFFFEFEFF,
+0xFFFEFEFF,
+0xFFFEFEFF,
+0xFFFEFEFF,
+0xFFFEFEFF,
+0xFFFEFEFF,
+0xFFFEFEFF,
+0xFFFEFEFF,
+0xFFFEFEFF,
+0xFFFEFEFF,
+0xFFFEFEFF,
+0xFFFEFEFF,
+0xFFFEFEFF,
+0xFFFEFEFF,
+0xFFFEFEFF,
+0xFFFEFEFF,
+0xFFFEFEFF,
+0xFFFEFEFF,
+0xFFFEFEFF,
+0xFFFEFEFF,
+0xFFFEFEFF,
+0xFFFEFEFF,
+0xFFFEFEFF,
+0xFFFEFEFF,
+0xFFFEFEFF,
+0xFFFEFEFF,
+0xFFFEFEFF,
+0xFFFEFEFF,
+0xFFFEFEFF,
+0xFFFEFEFF,
+0xFFFEFEFF,
+0xFFFEFEFF,
+0xFFFEFEFF,
+0xFFFEFEFF,
+0xFFFEFEFF,
+0xFFFEFEFF,
+0xFFFEFEFF,
+0xFFFEFEFF,
+0xFFFEFEFF,
+0xFFFEFEFF,
+0xFFFEFEFF,
+0xFFFEFEFF,
+0xFFFEFEFF,
+0xFFFEFEFF,
+0xFFFEFEFF,
+0xFFFEFEFF,
+0xFFFEFEFF,
+0xFFFEFEFF,
+0xFFFEFEFF,
+0xFFFEFEFF,
+0xFFFEFEFF,
+0xFFFEFEFF,
+0xFFFEFEFF,
+0xFFFEFEFF,
+0xFFFEFEFF,
+0xFFFEFEFF,
+0xFFFEFEFF,
+0xFFFEFEFF,
+0xFFFEFEFF,
+0xFFFEFEFF,
+0xFFFEFEFF,
+0xFFFEFEFF,
+0xFFFEFEFF,
+0xFFFEFEFF,
+0xFFFEFEFF,
+0xFFFEFEFF,
+0xFFFEFEFF,
+0xFFFEFEFF,
+0xFFFEFEFF,
+0xFFFEFEFF,
+0xFFFEFEFF,
+0xFFFEFEFF,
+0xFFFEFEFF,
+0xFFFEFEFF,
+0xFFFEFEFF,
+0xFFFEFEFF,
+0xFFFEFEFF,
+0xFFFEFEFF,
+0xFFFEFEFF,
+0xFFFEFEFF,
+0xFFFEFEFF,
+0xFFFEFEFF,
+0xFFFEFEFF,
+0xFFFEFEFF,
+0xFFFEFEFF,
+0xFFFEFEFF,
+0xFFFEFEFF,
+0xFFFEFEFF,
+0xFFFEFEFF,
+0xFFFEFEFF,
+0xFFFEFEFF,
+0xFFFEFEFF,
+0xFFFEFEFF,
+0xFFFEFEFF,
+0xFFFEFEFF,
+0xFFFEFEFF,
+0xFFFEFEFF,
+0xFFFEFEFF,
+0xFFFEFEFF,
+0xFFFEFEFF,
+0xFFFEFEFF,
+0xFFFEFEFF,
+0xFFFEFEFF,
+0xFFFEFEFF,
+0xFFFEFEFF,
+0xFFFEFEFF,
+0xFFFEFEFF,
+0xFFFEFEFF,
+0xFFFEFEFF,
+0xFFFEFEFF,
+0xFFFEFEFF,
+0xFFFEFEFF,
+0xFFFEFEFE,
+0xFFFEFEFE,
+0xFFFEFEFE,
+0xFFFEFEFE,
+0xFFFEFEFE,
+0xFFFEFEFE,
+0xFFFEFEFE,
+0xFFFEFEFE,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFDFE,
+0xFFFFFFFF,
+0xFFFCFFFF,
+0xFFFBFFFF,
+0xFFFCFFFA,
+0xFFFEFFFB,
+0xFFFFFEFF,
+0xFFFEFDFF,
+0xFFF8FFFF,
+0xFF90A7B5,
+0xFF24546B,
+0xFF27607E,
+0xFF356A8C,
+0xFF396B90,
+0xFF346A8C,
+0xFF396F91,
+0xFF366E91,
+0xFF376F92,
+0xFF376F94,
+0xFF367095,
+0xFF367095,
+0xFF367095,
+0xFF377196,
+0xFF377196,
+0xFF397398,
+0xFF377196,
+0xFF387297,
+0xFF3A769A,
+0xFF387499,
+0xFF387499,
+0xFF37759C,
+0xFF36769C,
+0xFF37779B,
+0xFF357598,
+0xFF3F799E,
+0xFF31678D,
+0xFF295B80,
+0xFF2F5F83,
+0xFF215270,
+0xFF204E66,
+0xFF3E6878,
+0xFFB3D3DE,
+0xFFF0FFFF,
+0xFFF8FFFF,
+0xFFFEFFFF,
+0xFFFEFCFF,
+0xFFFDFDFD,
+0xFFFEFFFF,
+0xFFFBFFFF,
+0xFFFBFFFF,
+0xFFFBFFFF,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFEFE,
+0xFFFEFEFE,
+0xFFFEFEFE,
+0xFFFEFEFE,
+0xFFFEFEFE,
+0xFFFEFEFE,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFDFE,
+0xFFFFFFFF,
+0xFFFCFFFF,
+0xFFFBFFFF,
+0xFFF8FFFA,
+0xFFFCFFFB,
+0xFFFFFEFF,
+0xFFFEFEFF,
+0xFFF4FFFF,
+0xFF3A5769,
+0xFF275D77,
+0xFF246382,
+0xFF376D91,
+0xFF366A8F,
+0xFF386E92,
+0xFF356D90,
+0xFF376F94,
+0xFF376F94,
+0xFF367096,
+0xFF357196,
+0xFF357195,
+0xFF377196,
+0xFF377196,
+0xFF397194,
+0xFF3A7295,
+0xFF387093,
+0xFF3A7297,
+0xFF3A7499,
+0xFF377398,
+0xFF377398,
+0xFF37759A,
+0xFF38769B,
+0xFF38769D,
+0xFF3C789D,
+0xFF296186,
+0xFF2A5F7F,
+0xFF2B5D78,
+0xFF29566D,
+0xFF385B6E,
+0xFFAFC9D6,
+0xFFF0FEFF,
+0xFFF8FFFF,
+0xFFFCFFFF,
+0xFFFEFFFF,
+0xFFFAFAF8,
+0xFFFFFEFA,
+0xFFFFFEFB,
+0xFFFFFBF8,
+0xFFFEFFFF,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFEFFFF,
+0xFFFCFEFD,
+0xFFFDFDFD,
+0xFFFEFEFE,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFEFE,
+0xFFFEFEFE,
+0xFFFEFEFE,
+0xFFFEFEFE,
+0xFFFEFEFE,
+0xFFFEFEFE,
+0xFFFEFEFE,
+0xFFFEFEFE,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFEFE,
+0xFFFEFEFE,
+0xFFFEFEFE,
+0xFFFEFEFE,
+0xFFFEFEFE,
+0xFFFEFEFE,
+0xFFFEFEFE,
+0xFFFEFEFE,
+0xFFFEFEFE,
+0xFFFEFEFE,
+0xFFFEFEFE,
+0xFFFEFEFE,
+0xFFFEFEFE,
+0xFFFEFEFE,
+0xFFFEFEFE,
+0xFFFEFEFE,
+0xFFFEFEFE,
+0xFFFEFEFE,
+0xFFFEFEFE,
+0xFFFEFEFE,
+0xFFFEFEFE,
+0xFFFEFEFE,
+0xFFFEFEFE,
+0xFFFEFEFE,
+0xFFFEFEFE,
+0xFFFEFEFE,
+0xFFFEFEFE,
+0xFFFEFEFE,
+0xFFFEFEFE,
+0xFFFEFEFE,
+0xFFFEFEFE,
+0xFFFEFEFE,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFEFE,
+0xFFFEFEFE,
+0xFFFEFEFE,
+0xFFFEFEFE,
+0xFFFEFEFE,
+0xFFFEFEFE,
+0xFFFEFEFE,
+0xFFFEFEFE,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFEFE,
+0xFFFEFEFE,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFEFFFF,
+0xFFFAFFFE,
+0xFFF7FFFC,
+0xFFFBFFFD,
+0xFFFFFEFF,
+0xFFFCFFFF,
+0xFFBFD1E5,
+0xFF294E68,
+0xFF2A637E,
+0xFF2A6988,
+0xFF336B8E,
+0xFF366C90,
+0xFF356B8F,
+0xFF376F92,
+0xFF376F94,
+0xFF376F94,
+0xFF367096,
+0xFF357196,
+0xFF357195,
+0xFF377397,
+0xFF387395,
+0xFF397194,
+0xFF3B7195,
+0xFF3A7096,
+0xFF3A7297,
+0xFF387298,
+0xFF377398,
+0xFF37759A,
+0xFF38789B,
+0xFF38769B,
+0xFF37729A,
+0xFF276187,
+0xFF2C6284,
+0xFF2C5E77,
+0xFF224B5F,
+0xFF6C8C99,
+0xFFF1FFFF,
+0xFFF7FEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFEFCFD,
+0xFFFDFDFB,
+0xFFFEFFFD,
+0xFFFFFFFB,
+0xFFFFFBF8,
+0xFFFFFDFA,
+0xFFFEFEFE,
+0xFFFDFEFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFEFE,
+0xFFFDFDFD,
+0xFFFDFDFD,
+0xFFFEFEFE,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFBFFFC,
+0xFFF8FFFF,
+0xFFF9FFFF,
+0xFFFEFEFE,
+0xFFF5FCFF,
+0xFF58768E,
+0xFF2F5E7C,
+0xFF2D6684,
+0xFF326F8E,
+0xFF326C91,
+0xFF366E93,
+0xFF33698D,
+0xFF386E92,
+0xFF376D93,
+0xFF376F94,
+0xFF356F95,
+0xFF347095,
+0xFF337196,
+0xFF377397,
+0xFF377294,
+0xFF387093,
+0xFF3C7298,
+0xFF3C7298,
+0xFF3B729B,
+0xFF38729A,
+0xFF35739A,
+0xFF37779B,
+0xFF367699,
+0xFF317195,
+0xFF28668F,
+0xFF276187,
+0xFF2A5D7A,
+0xFF2B5466,
+0xFFBAD2DE,
+0xFFF7FFFF,
+0xFFFEFCFD,
+0xFFFFFBFB,
+0xFFFFFDFC,
+0xFFFFFFFD,
+0xFFFEFFFF,
+0xFFFCFFFF,
+0xFFFAFEFF,
+0xFFFDFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFEFE,
+0xFFFDFDFD,
+0xFFFEFDFB,
+0xFFFFFEFC,
+0xFFFFFEFC,
+0xFFFFFEFC,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFEFE,
+0xFFFEFEFE,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFDFE,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFEFFFD,
+0xFFF9FFFF,
+0xFFF8FFFF,
+0xFFF7FBFC,
+0xFFE9F7FF,
+0xFF29506D,
+0xFF2F6388,
+0xFF2D6385,
+0xFF366E8F,
+0xFF306A8F,
+0xFF326C91,
+0xFF397194,
+0xFF396F91,
+0xFF376D91,
+0xFF376F94,
+0xFF356F95,
+0xFF347095,
+0xFF337196,
+0xFF367296,
+0xFF397196,
+0xFF396F93,
+0xFF3A7096,
+0xFF3B7098,
+0xFF39729D,
+0xFF35739C,
+0xFF34739C,
+0xFF36769A,
+0xFF327194,
+0xFF286788,
+0xFF296486,
+0xFF2B5E7D,
+0xFF345D73,
+0xFFDEFAFF,
+0xFFF7FFFF,
+0xFFFEFCFD,
+0xFFFFFDFA,
+0xFFFFFCFA,
+0xFFFFFEFB,
+0xFFFDFFFE,
+0xFFF8FDFF,
+0xFFF9FFFF,
+0xFFFBFFFF,
+0xFFFBFFFF,
+0xFFFCFFFF,
+0xFFFCFDFF,
+0xFFFCFEFD,
+0xFFFEFEFE,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFD,
+0xFFFFFFFF,
+0xFFF9FCFF,
+0xFFF8FFFF,
+0xFFF7FFFF,
+0xFF88A3AE,
+0xFF2F5E7C,
+0xFF2D648B,
+0xFF37698E,
+0xFF3A6C8F,
+0xFF356D92,
+0xFF326C91,
+0xFF346C8F,
+0xFF376D8F,
+0xFF386D8F,
+0xFF376D91,
+0xFF356F94,
+0xFF347095,
+0xFF357196,
+0xFF367296,
+0xFF397196,
+0xFF3A7094,
+0xFF3A7096,
+0xFF356F97,
+0xFF35729E,
+0xFF35749F,
+0xFF33749C,
+0xFF36769A,
+0xFF2B6789,
+0xFF2C6582,
+0xFF2E6077,
+0xFF41677A,
+0xFFEDFFFF,
+0xFFF7FFFF,
+0xFFFDFCFF,
+0xFFFFFEFD,
+0xFFFFFFFB,
+0xFFFFFFFB,
+0xFFFEFFFF,
+0xFFFBFFFF,
+0xFFFBFFFF,
+0xFFF9FFFF,
+0xFFF9FFFF,
+0xFFFBFFFF,
+0xFFFEFFFF,
+0xFFFEFFFD,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFEFCFF,
+0xFFFEFEFF,
+0xFFF8FFFF,
+0xFFEEFFFF,
+0xFF375B6B,
+0xFF2D6282,
+0xFF2D678D,
+0xFF386890,
+0xFF3A6A90,
+0xFF356B8F,
+0xFF326D8F,
+0xFF346C8F,
+0xFF376D8F,
+0xFF386D8F,
+0xFF376D8F,
+0xFF356F94,
+0xFF347095,
+0xFF357196,
+0xFF377197,
+0xFF397196,
+0xFF3A7094,
+0xFF3C739A,
+0xFF3C779F,
+0xFF35749F,
+0xFF33749E,
+0xFF33749C,
+0xFF2C6A8F,
+0xFF2A6381,
+0xFF306077,
+0xFF416774,
+0xFFEDFFFF,
+0xFFF4FFFF,
+0xFFFAFDFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFDFFFC,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFBFFFF,
+0xFFFBFFFF,
+0xFFFCFFFF,
+0xFFFEFFFF,
+0xFFFFFFFB,
+0xFFFFFFFB,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFCFBF9,
+0xFFFFFFFD,
+0xFFFDFBFE,
+0xFFFFFEFF,
+0xFFFBFAFF,
+0xFFF4FEFF,
+0xFFAECEDB,
+0xFF2A596D,
+0xFF306987,
+0xFF326A8F,
+0xFF386890,
+0xFF3B6891,
+0xFF366B8D,
+0xFF346C8D,
+0xFF366C90,
+0xFF376D8F,
+0xFF386D8D,
+0xFF386D8F,
+0xFF376F94,
+0xFF367096,
+0xFF367098,
+0xFF377197,
+0xFF397196,
+0xFF397194,
+0xFF326C92,
+0xFF347299,
+0xFF30719B,
+0xFF3477A1,
+0xFF2C6C92,
+0xFF31698C,
+0xFF346583,
+0xFF395C70,
+0xFFF3FFFF,
+0xFFFAFFFF,
+0xFFF8FFFF,
+0xFFF6FFFF,
+0xFFF9FFFF,
+0xFFFBFFFF,
+0xFFFBFCFE,
+0xFFFDFEFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFEFB,
+0xFFFFFFF8,
+0xFFFFFFFA,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFEFDFF,
+0xFFFCFCFF,
+0xFFF4FFFF,
+0xFF557E92,
+0xFF306881,
+0xFF316C8A,
+0xFF346A8E,
+0xFF386890,
+0xFF3B6891,
+0xFF366B8D,
+0xFF356C8B,
+0xFF366C8E,
+0xFF386D8F,
+0xFF376C8C,
+0xFF386D8D,
+0xFF376F94,
+0xFF367096,
+0xFF377199,
+0xFF397097,
+0xFF3A7096,
+0xFF387093,
+0xFF3A769A,
+0xFF37779B,
+0xFF32769D,
+0xFF2E6F97,
+0xFF2E6A8E,
+0xFF336685,
+0xFF2A4F69,
+0xFFDCF3FF,
+0xFFFBFFFF,
+0xFFFEFDF9,
+0xFFF8FDF9,
+0xFFF9FFFF,
+0xFFF9FFFF,
+0xFFFBFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFFFEFB,
+0xFFFFFEFB,
+0xFFFFFEFA,
+0xFFFFFFFA,
+0xFFFFFFFA,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFDFDFF,
+0xFFFCFFFF,
+0xFFF8FEFF,
+0xFFD9EEFF,
+0xFF295B74,
+0xFF2A6A86,
+0xFF316C8C,
+0xFF346A8C,
+0xFF386890,
+0xFF396991,
+0xFF376C8C,
+0xFF366D8C,
+0xFF376C8E,
+0xFF376C8E,
+0xFF376C8C,
+0xFF376E8D,
+0xFF376F94,
+0xFF367098,
+0xFF396F9B,
+0xFF397099,
+0xFF396F95,
+0xFF387093,
+0xFF317091,
+0xFF327496,
+0xFF307499,
+0xFF2F6F93,
+0xFF316887,
+0xFF2A546D,
+0xFFADC8DB,
+0xFFF2FFFF,
+0xFFFAFFFF,
+0xFFFFFFFB,
+0xFFFFFFFD,
+0xFFF8F8F8,
+0xFFFEFFFF,
+0xFFFAFAFC,
+0xFFFFFFFF,
+0xFFFEFCFD,
+0xFFFFFEFD,
+0xFFFFFEFB,
+0xFFFFFFFA,
+0xFFFFFFFA,
+0xFFFFFFFB,
+0xFFFFFFFB,
+0xFFFFFEFD,
+0xFFFFFEFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFDFDFB,
+0xFFFFFFFD,
+0xFFFCFCFE,
+0xFFFBFFFF,
+0xFFF5FFFF,
+0xFF81A0B4,
+0xFF2C6381,
+0xFF337396,
+0xFF316C8C,
+0xFF356A8C,
+0xFF37698E,
+0xFF386A8F,
+0xFF366D8C,
+0xFF366D8C,
+0xFF376C8E,
+0xFF376C8E,
+0xFF376C8C,
+0xFF376D8F,
+0xFF376E95,
+0xFF367098,
+0xFF386E9A,
+0xFF386F98,
+0xFF3A7096,
+0xFF387093,
+0xFF347394,
+0xFF357797,
+0xFF2B6F92,
+0xFF317091,
+0xFF316280,
+0xFF688BA1,
+0xFFF1FFFF,
+0xFFF8FFFF,
+0xFFFCFFFF,
+0xFFFAFCF9,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFFFEFD,
+0xFFFFFEFB,
+0xFFFFFEFB,
+0xFFFFFFFB,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFD,
+0xFFFCFCFA,
+0xFFFFFFFF,
+0xFFF9FEFF,
+0xFFECFFFF,
+0xFF395F74,
+0xFF336E8E,
+0xFF2E7093,
+0xFF306B8D,
+0xFF356A8C,
+0xFF37698C,
+0xFF366B8D,
+0xFF346C8D,
+0xFF346C8D,
+0xFF376B90,
+0xFF376C8E,
+0xFF386D8D,
+0xFF376D8F,
+0xFF376E95,
+0xFF356E99,
+0xFF386E9A,
+0xFF396E98,
+0xFF3B6F94,
+0xFF397192,
+0xFF2F6E8D,
+0xFF367898,
+0xFF2C7190,
+0xFF2D6A87,
+0xFF2B5971,
+0xFFEAFFFF,
+0xFFF5FCFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFDFDFD,
+0xFFFEFEFF,
+0xFFFFFFFF,
+0xFFFCFCFC,
+0xFFFBFBFB,
+0xFFFEFEFE,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFDFFFE,
+0xFFFEFFFF,
+0xFFFEFEFE,
+0xFFF8FFFF,
+0xFFAAC7D9,
+0xFF32607A,
+0xFF377395,
+0xFF2D6D91,
+0xFF306A8F,
+0xFF346A8C,
+0xFF37698A,
+0xFF356A8A,
+0xFF316C8C,
+0xFF326D8F,
+0xFF376B90,
+0xFF396B8E,
+0xFF386D8D,
+0xFF376D8F,
+0xFF346E96,
+0xFF356E99,
+0xFF396E98,
+0xFF396E96,
+0xFF397196,
+0xFF377294,
+0xFF387496,
+0xFF306F90,
+0xFF2F6E8D,
+0xFF2F657F,
+0xFF99BCCF,
+0xFFF0FFFF,
+0xFFFEFFFF,
+0xFFFFFCFF,
+0xFFFFFEFF,
+0xFFFFFDFF,
+0xFFFFFFFF,
+0xFFFDFDFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFEFE,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFD,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFB,
+0xFFFFFEFB,
+0xFFFFFFFF,
+0xFFFCFFFF,
+0xFFF9FFFF,
+0xFFFBFFFF,
+0xFFFEFFFD,
+0xFFFFFFFA,
+0xFFFFFFFA,
+0xFFFFFFFA,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFDFFFE,
+0xFFF3FFFF,
+0xFF5A7F99,
+0xFF346A8E,
+0xFF357398,
+0xFF2E6C93,
+0xFF326A8D,
+0xFF33698B,
+0xFF37698A,
+0xFF356A8A,
+0xFF336B90,
+0xFF346C91,
+0xFF396B8E,
+0xFF3A6B8C,
+0xFF396C8B,
+0xFF386D8F,
+0xFF346F99,
+0xFF346F99,
+0xFF396F95,
+0xFF3A7094,
+0xFF367296,
+0xFF347297,
+0xFF377397,
+0xFF346F91,
+0xFF386E90,
+0xFF406A82,
+0xFFEFFFFF,
+0xFFFBFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFEFFFD,
+0xFFFCFFFD,
+0xFFFCFFFF,
+0xFFFEFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFDFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFD,
+0xFFFFFCFB,
+0xFFFFFDFB,
+0xFFFFFDFF,
+0xFFFEFFFF,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFDFF,
+0xFFFFFDFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFD,
+0xFFFEFFFD,
+0xFFFEFFFD,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFDFD,
+0xFFFFFDFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFCFFFF,
+0xFFFBFFFF,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFDFB,
+0xFFFFFEFA,
+0xFFFFFFFF,
+0xFFFCFFFF,
+0xFFF9FFFF,
+0xFFF9FFFF,
+0xFFFFFFFD,
+0xFFFFFFFA,
+0xFFFFFEF8,
+0xFFFFFFFA,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFDFDFD,
+0xFFFEFFFF,
+0xFFFBFFFF,
+0xFFD8EEF9,
+0xFF31607E,
+0xFF346F97,
+0xFF35739A,
+0xFF2A668B,
+0xFF326A8D,
+0xFF346989,
+0xFF356A8A,
+0xFF356A8C,
+0xFF346C91,
+0xFF346C91,
+0xFF376B90,
+0xFF396B8C,
+0xFF3B6C8D,
+0xFF396D92,
+0xFF346F99,
+0xFF346F99,
+0xFF386E92,
+0xFF387091,
+0xFF337295,
+0xFF317298,
+0xFF347299,
+0xFF3A7297,
+0xFF326081,
+0xFFA1C2D5,
+0xFFF7FFFF,
+0xFFFEFFFA,
+0xFFFDFDFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFCFFFD,
+0xFFFBFFFD,
+0xFFFBFFFF,
+0xFFFCFFFF,
+0xFFFFFEFF,
+0xFFFFFDFF,
+0xFFFFFDFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFD,
+0xFFFFFDFB,
+0xFFFFFDFD,
+0xFFFFFEFF,
+0xFFFEFFFF,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFDFF,
+0xFFFFFDFF,
+0xFFFFFDFF,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFFFFFB,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFD,
+0xFFFFFFFB,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFFFFFD,
+0xFFFEFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFD,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFB,
+0xFFFFFEFB,
+0xFFFFFFFD,
+0xFFFEFFFF,
+0xFFFBFFFF,
+0xFFFCFFFF,
+0xFFFFFFFF,
+0xFFFFFEFB,
+0xFFFFFEFB,
+0xFFFFFFFD,
+0xFFFEFFFF,
+0xFFFCFFFF,
+0xFFFEFFFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFF9FDFE,
+0xFFF4FFFF,
+0xFF809FB3,
+0xFF34698B,
+0xFF3C7AA1,
+0xFF316D92,
+0xFF326A8D,
+0xFF346989,
+0xFF346989,
+0xFF356A8A,
+0xFF356A8C,
+0xFF346C91,
+0xFF346C91,
+0xFF366A8F,
+0xFF366B8D,
+0xFF3A6C8F,
+0xFF376D91,
+0xFF356F97,
+0xFF356F97,
+0xFF386E92,
+0xFF376F90,
+0xFF337295,
+0xFF327296,
+0xFF36759E,
+0xFF397196,
+0xFF3E6A85,
+0xFFE9FFFF,
+0xFFF7FFFF,
+0xFFFEFFFD,
+0xFFFEFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFB,
+0xFFFFFFFA,
+0xFFFFFFFA,
+0xFFFFFEFB,
+0xFFFFFFFB,
+0xFFFFFFFB,
+0xFFFCFFFD,
+0xFFFBFFFF,
+0xFFFCFFFF,
+0xFFFEFFFF,
+0xFFFFFDFF,
+0xFFFFFDFF,
+0xFFFFFDFF,
+0xFFFFFEFD,
+0xFFFFFFFB,
+0xFFFFFFFB,
+0xFFFEFFFD,
+0xFFFEFFFD,
+0xFFFEFFFF,
+0xFFFEFFFD,
+0xFFFEFFFF,
+0xFFFEFFFD,
+0xFFFEFFFD,
+0xFFFEFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFEFFFF,
+0xFFFFFFFD,
+0xFFFFFFFB,
+0xFFFFFFFB,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFB,
+0xFFFEFFFB,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFEFFFF,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFEFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFDFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFEFFFD,
+0xFFFEFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFEFD,
+0xFFFFFEFD,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFEFB,
+0xFFFFFEFB,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFEFF,
+0xFFFFFEFD,
+0xFFFFFEFF,
+0xFFFEFFFF,
+0xFFFBFFFF,
+0xFFFBFFFF,
+0xFFFCFFFF,
+0xFFFFFFFD,
+0xFFFFFEFA,
+0xFFF9FFFF,
+0xFFEAFFFF,
+0xFF34607B,
+0xFF40779E,
+0xFF38769F,
+0xFF2C668B,
+0xFF336A89,
+0xFF356887,
+0xFF366988,
+0xFF356A8A,
+0xFF356B8D,
+0xFF356B8F,
+0xFF356B91,
+0xFF356B8F,
+0xFF356B8F,
+0xFF366A8F,
+0xFF366C90,
+0xFF366D96,
+0xFF376E95,
+0xFF386E92,
+0xFF376F90,
+0xFF347394,
+0xFF347498,
+0xFF3778A2,
+0xFF326A8F,
+0xFF83A7BF,
+0xFFEEFFFF,
+0xFFF4FFFF,
+0xFFFCFFFF,
+0xFFFFFFFF,
+0xFFFFFDFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFA,
+0xFFFFFFF8,
+0xFFFFFFFA,
+0xFFFFFFFA,
+0xFFFFFFFB,
+0xFFFFFFFD,
+0xFFFCFFFF,
+0xFFFBFFFF,
+0xFFFCFFFF,
+0xFFFEFFFF,
+0xFFFFFEFF,
+0xFFFFFDFF,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFFFFFB,
+0xFFFEFFFB,
+0xFFFEFFFD,
+0xFFFEFFFD,
+0xFFFEFFFF,
+0xFFFEFFFD,
+0xFFFEFFFF,
+0xFFFEFFFD,
+0xFFFEFFFF,
+0xFFFEFFFD,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFF9FFFF,
+0xFFF9FFFF,
+0xFFFBFFFF,
+0xFFFCFFFF,
+0xFFFFFFFF,
+0xFFFFFFFB,
+0xFFFFFFF8,
+0xFFFFFFFA,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFEFFFD,
+0xFFFEFFFD,
+0xFFFEFFFB,
+0xFFFEFFFB,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFBFFFF,
+0xFFF9FFFF,
+0xFFFCFFFF,
+0xFFFFFFFF,
+0xFFFFFDFF,
+0xFFFFFCFF,
+0xFFFFFCFF,
+0xFFFFFDFF,
+0xFFFFFEFD,
+0xFFFFFFFD,
+0xFFFFFFFB,
+0xFFFFFFFB,
+0xFFFFFFFB,
+0xFFFFFFFB,
+0xFFFFFEFB,
+0xFFFFFEFD,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFFFFFB,
+0xFFFFFFFB,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFCFFFF,
+0xFFF9FFFF,
+0xFFF9FFFF,
+0xFFFCFFFF,
+0xFFFEFFFD,
+0xFFFDFEF9,
+0xFFF5FFFF,
+0xFFA4C9E3,
+0xFF326A8D,
+0xFF3C7AA3,
+0xFF2C6B94,
+0xFF30688B,
+0xFF366988,
+0xFF386785,
+0xFF376886,
+0xFF356A8A,
+0xFF356B8D,
+0xFF356B8F,
+0xFF356B8F,
+0xFF356B91,
+0xFF346C91,
+0xFF356B91,
+0xFF356D92,
+0xFF376C94,
+0xFF386D95,
+0xFF386E92,
+0xFF376F90,
+0xFF367294,
+0xFF36769C,
+0xFF3676A2,
+0xFF32688E,
+0xFFD2EFFF,
+0xFFF3FFFF,
+0xFFF8FFFF,
+0xFFFBFFFE,
+0xFFFFFFFF,
+0xFFFFFDFE,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFEFFFB,
+0xFFFEFFFA,
+0xFFFFFFFB,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFCFFFD,
+0xFFFBFFFD,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFCFFFF,
+0xFFF9FFFF,
+0xFFF9FFFF,
+0xFFFCFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFA,
+0xFFFFFFF8,
+0xFFFFFFF8,
+0xFFFFFFFB,
+0xFFFFFFFD,
+0xFFFEFFFD,
+0xFFFEFFFD,
+0xFFFCFFFB,
+0xFFFCFFFD,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFCFFFF,
+0xFFF9FFFF,
+0xFFF9FFFF,
+0xFFFEFFFF,
+0xFFFFFEFF,
+0xFFFFFDFF,
+0xFFFFFBFF,
+0xFFFFFCFD,
+0xFFFFFCFD,
+0xFFFFFDFD,
+0xFFFFFFFD,
+0xFFFFFFFB,
+0xFFFFFFFB,
+0xFFFFFFFB,
+0xFFFFFFFB,
+0xFFFFFEFD,
+0xFFFFFEFD,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFEFFFF,
+0xFFFBFFFF,
+0xFFF9FFFF,
+0xFFF9FFFF,
+0xFFFEFFFF,
+0xFFFEFFFD,
+0xFFFCFFFF,
+0xFFF0FFFF,
+0xFF497A9A,
+0xFF3A79A4,
+0xFF3B7CA6,
+0xFF2D6B92,
+0xFF316789,
+0xFF386987,
+0xFF386783,
+0xFF396884,
+0xFF356A8A,
+0xFF346A8E,
+0xFF356B8F,
+0xFF356B8F,
+0xFF346C91,
+0xFF346C91,
+0xFF366E93,
+0xFF356D92,
+0xFF376C94,
+0xFF386E94,
+0xFF386E90,
+0xFF366E8F,
+0xFF357497,
+0xFF38789E,
+0xFF3474A0,
+0xFF497B9E,
+0xFFEEFFFF,
+0xFFF9FFFF,
+0xFFF9FFFF,
+0xFFF9FDFE,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFBFFFF,
+0xFFFBFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFFFFFF,
+0xFFFFFEFD,
+0xFFFFFEFB,
+0xFFFFFFFA,
+0xFFFFFFF8,
+0xFFFFFFFA,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFD,
+0xFFFEFFFD,
+0xFFFEFFFD,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFFFFFD,
+0xFFFFFEFB,
+0xFFFFFDFB,
+0xFFFFFDFB,
+0xFFFFFCFD,
+0xFFFFFDFD,
+0xFFFFFEFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFEFD,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFCFFFF,
+0xFFFBFFFF,
+0xFFFBFFFF,
+0xFFFBFFFF,
+0xFFFFFFFD,
+0xFFFCFFFD,
+0xFFF4FFFF,
+0xFFCDEDFC,
+0xFF356D92,
+0xFF3276A3,
+0xFF33729B,
+0xFF2C688C,
+0xFF326789,
+0xFF356684,
+0xFF396884,
+0xFF396886,
+0xFF34698B,
+0xFF336B8E,
+0xFF346A8E,
+0xFF356B8F,
+0xFF356B8F,
+0xFF356D92,
+0xFF366E93,
+0xFF356C93,
+0xFF376D93,
+0xFF396D92,
+0xFF386D8D,
+0xFF376F90,
+0xFF357599,
+0xFF397AA0,
+0xFF34729B,
+0xFF81AECD,
+0xFFF0FFFF,
+0xFFFEFFFD,
+0xFFFBFFFF,
+0xFFFAFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFDFF,
+0xFFFFFDFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFEFFFF,
+0xFFF9FFFF,
+0xFFFBFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFD,
+0xFFFFFDFB,
+0xFFFFFDFB,
+0xFFFFFEFA,
+0xFFFFFFFA,
+0xFFFEFFFB,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFEFD,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFD,
+0xFFFFFEFD,
+0xFFFFFEFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFFFEFB,
+0xFFFFFDFA,
+0xFFFFFEFA,
+0xFFFFFFFA,
+0xFFFFFFFB,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFEFFFF,
+0xFFFFFFFB,
+0xFFFBFFFF,
+0xFFEEFFFF,
+0xFF7BA4BA,
+0xFF35739A,
+0xFF3C80AD,
+0xFF336E96,
+0xFF2C6487,
+0xFF356A8A,
+0xFF376A89,
+0xFF396884,
+0xFF376886,
+0xFF33698B,
+0xFF336B90,
+0xFF346A8E,
+0xFF356B8F,
+0xFF366A8F,
+0xFF366C90,
+0xFF356D92,
+0xFF346B92,
+0xFF366C92,
+0xFF396D92,
+0xFF396E8E,
+0xFF376F90,
+0xFF34789D,
+0xFF3A7EA5,
+0xFF316B91,
+0xFFBBE3FD,
+0xFFF7FFFF,
+0xFFFFFFFB,
+0xFFFBFFFE,
+0xFFFEFFFF,
+0xFFFFFDFE,
+0xFFFFFDFE,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFD,
+0xFFFFFDFD,
+0xFFFFFDFD,
+0xFFFFFEFD,
+0xFFFFFEFF,
+0xFFFEFFFF,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFCFD,
+0xFFFFFDFA,
+0xFFFFFFFA,
+0xFFFFFFFA,
+0xFFFCFFFF,
+0xFFFBFFFF,
+0xFFFEFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFEFFFF,
+0xFFFFFFFD,
+0xFFFFFFFB,
+0xFFFFFFFB,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFEFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFB,
+0xFFFFFDFA,
+0xFFFFFFF8,
+0xFFFFFFFA,
+0xFFFCFFFD,
+0xFFFCFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFB,
+0xFFFFFFFB,
+0xFFFFFFFD,
+0xFFFDFFFE,
+0xFFFDFFFE,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFDFDFD,
+0xFFFFFFFD,
+0xFFFFFEFB,
+0xFFF9FFFF,
+0xFFE7FFFF,
+0xFF3B6E8D,
+0xFF3B7AA3,
+0xFF3C7DA7,
+0xFF2F6589,
+0xFF336685,
+0xFF346989,
+0xFF316686,
+0xFF366785,
+0xFF366988,
+0xFF33698D,
+0xFF336B90,
+0xFF336B90,
+0xFF346A8E,
+0xFF386A8D,
+0xFF376C8E,
+0xFF346C8F,
+0xFF366E93,
+0xFF366B93,
+0xFF376B90,
+0xFF3A6D8C,
+0xFF366E8F,
+0xFF397EA7,
+0xFF397CA6,
+0xFF366B8D,
+0xFFE5FFFF,
+0xFFF8FFFF,
+0xFFFFFFFA,
+0xFFFEFFFD,
+0xFFFDFFFE,
+0xFFFFFEFF,
+0xFFFEFCFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFEFD,
+0xFFFFFDFA,
+0xFFFEFEFC,
+0xFFFBFFFE,
+0xFFFCFFFF,
+0xFFF9FFFD,
+0xFFFCFFFF,
+0xFFFCFEFB,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFEFD,
+0xFFFFFEFD,
+0xFFFFFDFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFEFE,
+0xFFFEFEFE,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFEFE,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFEFFFF,
+0xFFFCFFFF,
+0xFFFEFFFF,
+0xFFFCFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFEFFFF,
+0xFFFCFFFF,
+0xFFFEFFFF,
+0xFFFCFFFF,
+0xFFFEFFFF,
+0xFFFBFFFE,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFDFEFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFDFEFF,
+0xFFFDFEFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFBFFFF,
+0xFFFCFFFF,
+0xFFFEF9FD,
+0xFFFFFDFD,
+0xFFFDFCF8,
+0xFFFEFFFB,
+0xFFF8FEFE,
+0xFFF9FFFF,
+0xFFFCFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFDFF,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFD,
+0xFFFFFFFB,
+0xFFFFFFFB,
+0xFFFCFBF7,
+0xFFFFFFFD,
+0xFFFEFFFF,
+0xFFFAFFFF,
+0xFFF9FFFF,
+0xFFF9FFFF,
+0xFFFCFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFDFFFE,
+0xFFFDFFFE,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFCFFFF,
+0xFFFEFFFF,
+0xFFFCFFFF,
+0xFFFEFFFF,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFDFEFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFEFF,
+0xFFFFFFFF,
+0xFFFEFEFE,
+0xFFFEFFFF,
+0xFFF9FFFF,
+0xFFFAFFFF,
+0xFFFFFEFF,
+0xFFFFFEFB,
+0xFFFDFCF7,
+0xFFFEFFFA,
+0xFFFBFFFD,
+0xFFFBFFFF,
+0xFFFCFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFCFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFB,
+0xFFFFFFFB,
+0xFFFEFFFD,
+0xFFFCFFFF,
+0xFFFAFEFD,
+0xFFFCFEFB,
+0xFFFFFFFD,
+0xFFFFFEFD,
+0xFFFFFEFD,
+0xFFFFFDFE,
+0xFFF3FFFF,
+0xFF9CC6DF,
+0xFF3B759A,
+0xFF4281AA,
+0xFF316F96,
+0xFF336685,
+0xFF356684,
+0xFF336888,
+0xFF33688A,
+0xFF356887,
+0xFF366889,
+0xFF33698D,
+0xFF336B90,
+0xFF336B90,
+0xFF346A8E,
+0xFF386A8B,
+0xFF396B8C,
+0xFF346C8F,
+0xFF336D92,
+0xFF356C93,
+0xFF366C90,
+0xFF3A6D8C,
+0xFF376F90,
+0xFF3780AB,
+0xFF387DA7,
+0xFF5481A0,
+0xFFEBFFFF,
+0xFFF9FFFF,
+0xFFFFFFFA,
+0xFFFFFFFB,
+0xFFFDFDFB,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFAF7,
+0xFFFFFEFB,
+0xFFFDFFFE,
+0xFFF9FFFF,
+0xFFF5FFFF,
+0xFFEFFFFF,
+0xFFF1FFFF,
+0xFFE0F3F7,
+0xFFE2F3FA,
+0xFFE4F3FA,
+0xFFE4F3FA,
+0xFFE5F2FA,
+0xFFE5F2FB,
+0xFFE5F2FB,
+0xFFE5F1FD,
+0xFFE4F2FD,
+0xFFE5F3FC,
+0xFFE3F4FB,
+0xFFE5F4FB,
+0xFFE3F4FB,
+0xFFE5F4FB,
+0xFFE3F4FB,
+0xFFE3F4FB,
+0xFFE3F4FB,
+0xFFE3F4FB,
+0xFFE3F4FC,
+0xFFE4F5FD,
+0xFFE3F6FD,
+0xFFE4F5FD,
+0xFFE3F6FD,
+0xFFE3F6FD,
+0xFFE4F7FE,
+0xFFE4F7FE,
+0xFFE4F7FD,
+0xFFE4F7FE,
+0xFFE4F7FE,
+0xFFE5F6FE,
+0xFFE5F6FE,
+0xFFE5F6FE,
+0xFFE5F6FE,
+0xFFE4F5FF,
+0xFFE4F5FD,
+0xFFE4F5FF,
+0xFFE4F5FF,
+0xFFE4F5FF,
+0xFFE4F5FF,
+0xFFE4F5FF,
+0xFFE3F6FD,
+0xFFE3F6FD,
+0xFFE3F6FC,
+0xFFE3F6FD,
+0xFFE3F6FC,
+0xFFE3F6FD,
+0xFFE3F6FC,
+0xFFE3F6FD,
+0xFFE3F6FC,
+0xFFE4F5FD,
+0xFFE4F5FC,
+0xFFE4F5FD,
+0xFFE4F5FC,
+0xFFE4F5FD,
+0xFFE4F5FC,
+0xFFE4F5FD,
+0xFFE4F5FD,
+0xFFE3F6FD,
+0xFFE3F6FD,
+0xFFE3F6FD,
+0xFFE3F6FD,
+0xFFE3F6FD,
+0xFFE3F6FD,
+0xFFE3F6FD,
+0xFFE3F6FD,
+0xFFE3F6FD,
+0xFFE3F6FD,
+0xFFE3F6FD,
+0xFFE3F6FD,
+0xFFE3F6FD,
+0xFFE3F6FD,
+0xFFE3F6FD,
+0xFFE3F6FD,
+0xFFE3F4FC,
+0xFFE3F4FB,
+0xFFE3F4FC,
+0xFFE3F4FC,
+0xFFE3F4FC,
+0xFFE2F5FC,
+0xFFE3F5FF,
+0xFFE3F6FD,
+0xFFE4F6FF,
+0xFFE4F7FE,
+0xFFE3F6FD,
+0xFFE3F6FD,
+0xFFE4F5FD,
+0xFFE5F6FE,
+0xFFE5F6FD,
+0xFFE5F6FF,
+0xFFDCEFFD,
+0xFFF2FFFF,
+0xFFFBFFFF,
+0xFFFBFBFD,
+0xFFFFFFFD,
+0xFFFDFFFC,
+0xFFFAFFFF,
+0xFFF6FEFF,
+0xFFFCFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFDFF,
+0xFFFFFEFF,
+0xFFFFFEFD,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFB,
+0xFFFFFDF8,
+0xFFFFFEF9,
+0xFFFFFFFB,
+0xFFFDFFFE,
+0xFFF7FFFF,
+0xFFF7FFFF,
+0xFFF2FFFF,
+0xFFECFEFF,
+0xFFDDEEF6,
+0xFFDCEDF4,
+0xFFDCEDF4,
+0xFFDCEDF4,
+0xFFDDEEF5,
+0xFFDDEEF5,
+0xFFDEEFF7,
+0xFFDFF0F7,
+0xFFE0F1F9,
+0xFFE0F1F9,
+0xFFE0F1F9,
+0xFFE0F1F9,
+0xFFE0F3FA,
+0xFFE0F3FA,
+0xFFE0F2FC,
+0xFFE0F3FA,
+0xFFE0F1F9,
+0xFFE1F2FA,
+0xFFE1F4FB,
+0xFFE0F3FA,
+0xFFE1F4FB,
+0xFFE2F4FE,
+0xFFE2F4FE,
+0xFFE2F4FE,
+0xFFE1F3FD,
+0xFFE1F4FB,
+0xFFE3F6FD,
+0xFFE4F5FD,
+0xFFE4F5FD,
+0xFFE5F6FE,
+0xFFE6F5FC,
+0xFFE4F5FD,
+0xFFEBFFFF,
+0xFFF2FFFF,
+0xFFFAFDFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFEFFFB,
+0xFFF8FEFC,
+0xFFFBFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFEFFFD,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFB,
+0xFFFEFFFD,
+0xFFFCFFFD,
+0xFFFBFFFF,
+0xFFFCFFFD,
+0xFFFEFFFA,
+0xFFFFFEFB,
+0xFFFFFEFB,
+0xFFFFFDFE,
+0xFFFCFDFF,
+0xFFF0FFFF,
+0xFF5284A5,
+0xFF3B7CA4,
+0xFF4583AA,
+0xFF2C6487,
+0xFF356684,
+0xFF376684,
+0xFF346989,
+0xFF326789,
+0xFF35678A,
+0xFF36688B,
+0xFF33698D,
+0xFF346A90,
+0xFF336B90,
+0xFF346A8E,
+0xFF396A8A,
+0xFF386B8A,
+0xFF336B8C,
+0xFF336D92,
+0xFF356C93,
+0xFF366C90,
+0xFF3A6D8C,
+0xFF367193,
+0xFF3781B0,
+0xFF387BA6,
+0xFF78A0B9,
+0xFFF1FFFF,
+0xFFFAFFFF,
+0xFFFFFFFB,
+0xFFFFFFFB,
+0xFFFEFFFA,
+0xFFFFFDFE,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFCFF,
+0xFFFFFDFF,
+0xFFFBFFFF,
+0xFFEFFFFF,
+0xFFC7E3EF,
+0xFF7BA0B0,
+0xFF558093,
+0xFF5D8A9F,
+0xFF5C8AA1,
+0xFF5B8BA1,
+0xFF5B8BA1,
+0xFF5B8BA1,
+0xFF5C8CA2,
+0xFF5D8BA2,
+0xFF5D8BA2,
+0xFF5E8BA2,
+0xFF5E8BA2,
+0xFF5F8CA3,
+0xFF628CA4,
+0xFF608DA4,
+0xFF628CA4,
+0xFF608DA4,
+0xFF608DA4,
+0xFF5F8CA3,
+0xFF618EA5,
+0xFF618DA6,
+0xFF628EA7,
+0xFF618FA7,
+0xFF628EA7,
+0xFF618FA7,
+0xFF618FA7,
+0xFF6290A8,
+0xFF638FA8,
+0xFF658FA7,
+0xFF658FA8,
+0xFF6690A9,
+0xFF6690A9,
+0xFF6690A9,
+0xFF6690A9,
+0xFF6690A9,
+0xFF6692AD,
+0xFF6692AB,
+0xFF6793AE,
+0xFF6793AE,
+0xFF6793AE,
+0xFF6793AE,
+0xFF6793AE,
+0xFF6894AF,
+0xFF6995AE,
+0xFF6896AD,
+0xFF6896AE,
+0xFF6997AE,
+0xFF6997AF,
+0xFF6997AE,
+0xFF6B97B0,
+0xFF6B98AF,
+0xFF6D99B2,
+0xFF6D9AB1,
+0xFF6D99B2,
+0xFF6D9AB1,
+0xFF6D99B2,
+0xFF6E9BB2,
+0xFF709AB3,
+0xFF709AB3,
+0xFF6E9AB3,
+0xFF6E9CB4,
+0xFF6E9CB4,
+0xFF6E9CB4,
+0xFF6E9CB4,
+0xFF6E9CB4,
+0xFF6E9CB4,
+0xFF6E9CB4,
+0xFF6E9CB4,
+0xFF6E9CB4,
+0xFF6F9DB5,
+0xFF6F9DB5,
+0xFF6F9DB5,
+0xFF6F9DB5,
+0xFF6F9DB5,
+0xFF709EB6,
+0xFF719DB6,
+0xFF719EB5,
+0xFF719DB6,
+0xFF709EB6,
+0xFF709EB6,
+0xFF719FB7,
+0xFF719FB9,
+0xFF719FB7,
+0xFF6E9CB6,
+0xFF6D9BB3,
+0xFF6D9BB3,
+0xFF6D9BB3,
+0xFF6F9CB3,
+0xFF6F9CB3,
+0xFF6E9BB2,
+0xFF6D9AB1,
+0xFF709DB4,
+0xFF7EA1B4,
+0xFFF1FFFF,
+0xFFFBFFFF,
+0xFFFEFFFF,
+0xFFFEFEFC,
+0xFFFCFFFF,
+0xFFFBFFFF,
+0xFFFCFFFF,
+0xFFFEFFFF,
+0xFFFFFFFD,
+0xFFFFFFFB,
+0xFFFEFFFD,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFDFF,
+0xFFFFFEFD,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFEFB,
+0xFFFFFFFA,
+0xFFFFFFFB,
+0xFFFCFCFA,
+0xFFFAFFFF,
+0xFFF5FFFF,
+0xFFEAFEFF,
+0xFF7A94A5,
+0xFF4A6A7F,
+0xFF476D84,
+0xFF456F87,
+0xFF467088,
+0xFF48728A,
+0xFF4A748C,
+0xFF4B758D,
+0xFF4B7790,
+0xFF4C7990,
+0xFF4E7A93,
+0xFF4F7B94,
+0xFF507C95,
+0xFF517D96,
+0xFF537F98,
+0xFF55819A,
+0xFF55839D,
+0xFF55839B,
+0xFF59879F,
+0xFF5B89A1,
+0xFF5C8CA3,
+0xFF5C8CA3,
+0xFF5E8EA5,
+0xFF608FA9,
+0xFF6291AB,
+0xFF6392AC,
+0xFF6593AD,
+0xFF6896AE,
+0xFF6997AF,
+0xFF6B97B0,
+0xFF6E9BB2,
+0xFF6E9BB2,
+0xFF6F99B1,
+0xFF6F9AAD,
+0xFF6C93A4,
+0xFFB8D6E1,
+0xFFF5FFFF,
+0xFFF9FCFF,
+0xFFFEFCFF,
+0xFFFDFDFD,
+0xFFFCFFFF,
+0xFFFBFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFD,
+0xFFFFFFFB,
+0xFFFFFFFA,
+0xFFFFFFFB,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFB,
+0xFFFFFFFB,
+0xFFFEFFFD,
+0xFFFBFFFF,
+0xFFF9FFFD,
+0xFFFCFFFF,
+0xFFFFFFFB,
+0xFFFFFFFA,
+0xFFFFFCF9,
+0xFFFEFFFF,
+0xFFF7FFFF,
+0xFFCCE8FF,
+0xFF397399,
+0xFF3C81AB,
+0xFF3D799E,
+0xFF2E6383,
+0xFF376684,
+0xFF366583,
+0xFF37698A,
+0xFF306587,
+0xFF35678A,
+0xFF34688D,
+0xFF34688D,
+0xFF33698F,
+0xFF346A90,
+0xFF346A8E,
+0xFF396A8B,
+0xFF386B8A,
+0xFF346A8C,
+0xFF336E90,
+0xFF356D92,
+0xFF366C92,
+0xFF386D8D,
+0xFF377397,
+0xFF3783B4,
+0xFF377AA5,
+0xFF98B8CD,
+0xFFF4FFFF,
+0xFFFBFFFF,
+0xFFFFFFFD,
+0xFFFFFFFB,
+0xFFFFFFFB,
+0xFFFEFCFD,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFDFF,
+0xFFFBFCFF,
+0xFFF4FFFF,
+0xFF95B1BD,
+0xFF547D91,
+0xFF568AA2,
+0xFF568FAC,
+0xFF5693B2,
+0xFF5291B2,
+0xFF5192B2,
+0xFF5193B3,
+0xFF5194B1,
+0xFF5293B1,
+0xFF5493B2,
+0xFF5693B2,
+0xFF5792B2,
+0xFF5893B3,
+0xFF5794B3,
+0xFF5895B4,
+0xFF5895B4,
+0xFF5995B7,
+0xFF5996B5,
+0xFF5995B7,
+0xFF5695B6,
+0xFF5897B8,
+0xFF5897B8,
+0xFF5998BB,
+0xFF5998B9,
+0xFF5998BB,
+0xFF5998B9,
+0xFF5A99BC,
+0xFF5A99BC,
+0xFF5D99BD,
+0xFF5E98BD,
+0xFF5E98BD,
+0xFF5E98BD,
+0xFF5F99BE,
+0xFF5F99BE,
+0xFF5F99BE,
+0xFF5E9ABF,
+0xFF5F9BC0,
+0xFF5F9BC0,
+0xFF5F9BC0,
+0xFF609CC1,
+0xFF609CC1,
+0xFF619CC4,
+0xFF619CC4,
+0xFF5F9DC2,
+0xFF5E9DC0,
+0xFF5E9DC0,
+0xFF5F9EC1,
+0xFF5F9EC1,
+0xFF609FC2,
+0xFF609FC2,
+0xFF609FC2,
+0xFF639FC3,
+0xFF639FC3,
+0xFF639FC3,
+0xFF639FC3,
+0xFF64A0C4,
+0xFF64A0C4,
+0xFF64A0C4,
+0xFF65A1C5,
+0xFF65A1C5,
+0xFF66A2C6,
+0xFF64A3C6,
+0xFF64A3C6,
+0xFF64A3C6,
+0xFF65A4C7,
+0xFF65A4C7,
+0xFF65A4C7,
+0xFF65A4C7,
+0xFF66A5C8,
+0xFF66A5C8,
+0xFF67A6C9,
+0xFF67A6C9,
+0xFF67A6C9,
+0xFF68A7CA,
+0xFF68A7CA,
+0xFF68A7CA,
+0xFF69A8CB,
+0xFF69A8CB,
+0xFF69A8CB,
+0xFF6AA9CC,
+0xFF69A9CC,
+0xFF69A9CC,
+0xFF6AAACE,
+0xFF6AAACD,
+0xFF6BABCF,
+0xFF6BABCE,
+0xFF6DACCF,
+0xFF6DACCD,
+0xFF6DACCD,
+0xFF6EABCA,
+0xFF6EABCA,
+0xFF70ABC9,
+0xFF6EA7C2,
+0xFF6F9EB2,
+0xFFC2D9E7,
+0xFFF8FFFF,
+0xFFFEFFFF,
+0xFFFFFFFD,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFEFFFF,
+0xFFFFFFFB,
+0xFFFFFFFA,
+0xFFFEFFFA,
+0xFFFCFFFB,
+0xFFFEFFFD,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFD,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFEFD,
+0xFFFFFEFB,
+0xFFFEFAF7,
+0xFFFFFFFD,
+0xFFFBFFFF,
+0xFFF3FEFF,
+0xFFE6FAFF,
+0xFF486575,
+0xFF476B83,
+0xFF497693,
+0xFF437A99,
+0xFF417C9E,
+0xFF427D9F,
+0xFF447FA1,
+0xFF4680A5,
+0xFF4783A7,
+0xFF4884A8,
+0xFF4884A8,
+0xFF4A86AA,
+0xFF4B87AB,
+0xFF4C88AD,
+0xFF4C8AAF,
+0xFF508CB1,
+0xFF508EB3,
+0xFF5290B5,
+0xFF5391B6,
+0xFF5393B7,
+0xFF5696BA,
+0xFF5799BC,
+0xFF589ABD,
+0xFF599BBE,
+0xFF5B9DC0,
+0xFF5D9EC4,
+0xFF5EA0C3,
+0xFF61A1C5,
+0xFF63A3C6,
+0xFF64A3C6,
+0xFF65A4C5,
+0xFF6DA9CB,
+0xFF6AA7C6,
+0xFF6DAAC9,
+0xFF73ACC9,
+0xFF75A8BD,
+0xFF769BAB,
+0xFFF2FFFF,
+0xFFFCFFFF,
+0xFFFDFBFE,
+0xFFFFFEFF,
+0xFFFCFDFF,
+0xFFFEFFFF,
+0xFFFFFEFF,
+0xFFFFFDFF,
+0xFFFFFEFB,
+0xFFFFFFFA,
+0xFFFFFFF8,
+0xFFFFFFFA,
+0xFFFFFEFB,
+0xFFFFFEFD,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFEFB,
+0xFFFFFFFB,
+0xFFFEFFFF,
+0xFFFBFFFF,
+0xFFFBFFFF,
+0xFFFBFFFF,
+0xFFFFFEFB,
+0xFFFFFDF9,
+0xFFFFFFFD,
+0xFFF9FFFF,
+0xFFEEFFFF,
+0xFF789FBE,
+0xFF3F7EA9,
+0xFF4084B1,
+0xFF316B90,
+0xFF316384,
+0xFF356686,
+0xFF346585,
+0xFF356788,
+0xFF336588,
+0xFF35678A,
+0xFF34688D,
+0xFF34688D,
+0xFF34688D,
+0xFF34688D,
+0xFF35698E,
+0xFF37698A,
+0xFF386A8B,
+0xFF346A8C,
+0xFF346C8F,
+0xFF366C92,
+0xFF366C92,
+0xFF366E91,
+0xFF36769C,
+0xFF3A86B7,
+0xFF3879A1,
+0xFFB0CDDF,
+0xFFF6FFFF,
+0xFFFCFFFF,
+0xFFFEFFFD,
+0xFFFEFFFA,
+0xFFFFFFFD,
+0xFFFFFDFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFBFFFF,
+0xFFF5FFFF,
+0xFF9EB9C0,
+0xFF4D7581,
+0xFF53879C,
+0xFF4B88A4,
+0xFF4586A6,
+0xFF36779D,
+0xFF3C7DA3,
+0xFF3D7EA4,
+0xFF3D7FA2,
+0xFF3E80A3,
+0xFF3F7FA2,
+0xFF437FA3,
+0xFF447EA3,
+0xFF447EA3,
+0xFF4280A5,
+0xFF4082A5,
+0xFF4082A5,
+0xFF4082A5,
+0xFF4182A8,
+0xFF4183A6,
+0xFF4283A9,
+0xFF4084A9,
+0xFF4185AA,
+0xFF4185AA,
+0xFF4286AD,
+0xFF4286AB,
+0xFF4286AD,
+0xFF4286AB,
+0xFF4387AE,
+0xFF4488AF,
+0xFF4687AF,
+0xFF4687AF,
+0xFF4687AF,
+0xFF4788B0,
+0xFF4589B0,
+0xFF468AB1,
+0xFF468AB1,
+0xFF4689B3,
+0xFF4689B3,
+0xFF458AB3,
+0xFF458AB3,
+0xFF468BB4,
+0xFF468BB4,
+0xFF478CB6,
+0xFF478CB6,
+0xFF458CB6,
+0xFF478FB7,
+0xFF478FB7,
+0xFF4890B8,
+0xFF4890B8,
+0xFF4991B9,
+0xFF4991B9,
+0xFF4A92BA,
+0xFF4C91BA,
+0xFF4C91BA,
+0xFF4C91BA,
+0xFF4C91BA,
+0xFF4D92BB,
+0xFF4D92BB,
+0xFF4E93BC,
+0xFF4E93BC,
+0xFF5093BD,
+0xFF5094BB,
+0xFF5094BB,
+0xFF5094BB,
+0xFF5195BC,
+0xFF5195BC,
+0xFF5195BC,
+0xFF5195BC,
+0xFF5296BD,
+0xFF5397BE,
+0xFF5397BE,
+0xFF5397BE,
+0xFF5498BF,
+0xFF5498BF,
+0xFF5599C0,
+0xFF5599C0,
+0xFF5599C0,
+0xFF5599C0,
+0xFF5599C0,
+0xFF5499C0,
+0xFF5499C0,
+0xFF559AC1,
+0xFF559AC1,
+0xFF539BC3,
+0xFF549CC2,
+0xFF5499C2,
+0xFF559AC1,
+0xFF579BC2,
+0xFF569ABF,
+0xFF5599BE,
+0xFF5698BB,
+0xFF5A9CBF,
+0xFF60A1C1,
+0xFF65A5C1,
+0xFF6598AD,
+0xFFD6EEFA,
+0xFFF6FFFF,
+0xFFFDFDFD,
+0xFFFFFFFD,
+0xFFF5F6F8,
+0xFFFCFFFF,
+0xFFFFFFFF,
+0xFFFFFFFB,
+0xFFFFFFFA,
+0xFFFEFFFA,
+0xFFFCFFFB,
+0xFFFCFFFD,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFEFD,
+0xFFFFFEFB,
+0xFFFFFFFB,
+0xFFFAFCFB,
+0xFFF9FFFF,
+0xFFF1FFFF,
+0xFF5A7787,
+0xFF477086,
+0xFF417290,
+0xFF457DA0,
+0xFF4888AE,
+0xFF4589B0,
+0xFF4589B0,
+0xFF4589B0,
+0xFF4689B3,
+0xFF4489B2,
+0xFF4489B2,
+0xFF4489B2,
+0xFF458AB3,
+0xFF458AB3,
+0xFF458AB4,
+0xFF438AB4,
+0xFF468BB5,
+0xFF448BB5,
+0xFF448BB5,
+0xFF458CB6,
+0xFF448CB4,
+0xFF458DB5,
+0xFF458EB7,
+0xFF448DB6,
+0xFF438CB5,
+0xFF448DB6,
+0xFF458EB7,
+0xFF458EB7,
+0xFF468DB7,
+0xFF468EB6,
+0xFF498EB5,
+0xFF498FB3,
+0xFF4B8FB2,
+0xFF498BAE,
+0xFF589ABC,
+0xFF67A4C1,
+0xFF6CA3B8,
+0xFF8BB2C1,
+0xFFEFFFFF,
+0xFFFCFFFF,
+0xFFFFFDFF,
+0xFFFFFDFE,
+0xFFFCFDFF,
+0xFFFEFFFF,
+0xFFFFFDFF,
+0xFFFFFDFF,
+0xFFFFFEFB,
+0xFFFFFFFA,
+0xFFFEFFF8,
+0xFFFEFFFA,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFD,
+0xFFFFFFFB,
+0xFFFFFFFA,
+0xFFFFFFFB,
+0xFFFEFFFF,
+0xFFFCFFFF,
+0xFFFBFFFF,
+0xFFFBFFFF,
+0xFFFFFEFB,
+0xFFFFFCF8,
+0xFFFFFFFF,
+0xFFF4FFFF,
+0xFFDFFFFF,
+0xFF427497,
+0xFF4386B1,
+0xFF3E83AD,
+0xFF2C6487,
+0xFF2F6182,
+0xFF33688A,
+0xFF346689,
+0xFF336485,
+0xFF376889,
+0xFF35678A,
+0xFF33678C,
+0xFF34688D,
+0xFF34688D,
+0xFF36688D,
+0xFF356A8C,
+0xFF37698C,
+0xFF366B8D,
+0xFF356B8D,
+0xFF346C8D,
+0xFF366C90,
+0xFF366C92,
+0xFF346E94,
+0xFF3778A2,
+0xFF3C88B9,
+0xFF39799F,
+0xFFC3DDEC,
+0xFFFAFFFF,
+0xFFFCFFFF,
+0xFFFDFFFE,
+0xFFFDFDFB,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFCFFFF,
+0xFFF5FFFF,
+0xFFEAFEFF,
+0xFF4D6F79,
+0xFF538292,
+0xFF49819A,
+0xFF397897,
+0xFF307197,
+0xFF3376A0,
+0xFF34759F,
+0xFF34759D,
+0xFF35769E,
+0xFF35769C,
+0xFF37779B,
+0xFF38769B,
+0xFF3B779C,
+0xFF3B769E,
+0xFF39799F,
+0xFF367A9F,
+0xFF3579A0,
+0xFF3479A0,
+0xFF367AA1,
+0xFF367BA2,
+0xFF387CA3,
+0xFF377CA3,
+0xFF377CA5,
+0xFF367EA6,
+0xFF387DA6,
+0xFF377FA7,
+0xFF397EA7,
+0xFF377FA7,
+0xFF3A7FA8,
+0xFF3980AA,
+0xFF3980AA,
+0xFF3980AA,
+0xFF3A81AB,
+0xFF3A81AB,
+0xFF3B82AC,
+0xFF3A83AC,
+0xFF3A83AC,
+0xFF3B84AF,
+0xFF3C85B0,
+0xFF3C87B1,
+0xFF3C87B1,
+0xFF3C87B1,
+0xFF3D87B4,
+0xFF3D87B4,
+0xFF3C89B5,
+0xFF3C89B5,
+0xFF3A87B3,
+0xFF3A89B4,
+0xFF3B88B4,
+0xFF3B88B4,
+0xFF3C89B5,
+0xFF3C89B5,
+0xFF3D8AB6,
+0xFF3D8AB6,
+0xFF418BB8,
+0xFF418BB8,
+0xFF418BB8,
+0xFF428CB9,
+0xFF428CB9,
+0xFF438DBA,
+0xFF438DBA,
+0xFF458EB9,
+0xFF458EB9,
+0xFF458EB7,
+0xFF478EB8,
+0xFF468FB8,
+0xFF488FB9,
+0xFF4790B9,
+0xFF488FB9,
+0xFF4790B9,
+0xFF4990BA,
+0xFF4891BA,
+0xFF4990BA,
+0xFF4992BB,
+0xFF4A91BB,
+0xFF4A93BC,
+0xFF4B92BC,
+0xFF4B92BC,
+0xFF4A91BB,
+0xFF4B92BC,
+0xFF4B92BC,
+0xFF4A93BC,
+0xFF4A93BC,
+0xFF4B94BD,
+0xFF4B94BF,
+0xFF4B94BD,
+0xFF4B94BD,
+0xFF4C93BD,
+0xFF4C93BD,
+0xFF4E93BC,
+0xFF4C91B8,
+0xFF4E92B9,
+0xFF5697BD,
+0xFF5D9DC0,
+0xFF629EBA,
+0xFF6794A7,
+0xFFF0FFFF,
+0xFFFBFFFF,
+0xFFFFFFFD,
+0xFFFFFEFD,
+0xFFFEFFFF,
+0xFFFBFCFF,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFFFFFB,
+0xFFFFFFFB,
+0xFFFCFFFD,
+0xFFFCFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFD,
+0xFFFFFEFB,
+0xFFFFFEFC,
+0xFFFEFFFF,
+0xFFF2FDFF,
+0xFFD2E8F3,
+0xFF375C6F,
+0xFF3D6F8A,
+0xFF437FA1,
+0xFF498DB4,
+0xFF478EB8,
+0xFF468FBA,
+0xFF468FBA,
+0xFF458EB9,
+0xFF458EB9,
+0xFF438DBA,
+0xFF428CB9,
+0xFF428CB9,
+0xFF418BB8,
+0xFF418BB8,
+0xFF3F8CBA,
+0xFF3E8BB9,
+0xFF3D8AB8,
+0xFF3C89B7,
+0xFF3C89B7,
+0xFF3B88B4,
+0xFF3D87B4,
+0xFF3E88B5,
+0xFF3E88B5,
+0xFF3A87B3,
+0xFF3A87B5,
+0xFF3A87B3,
+0xFF3A87B3,
+0xFF3B85B2,
+0xFF3A84B1,
+0xFF3B84AF,
+0xFF3D86AF,
+0xFF3C84AC,
+0xFF3B80A7,
+0xFF397DA2,
+0xFF5498BD,
+0xFF69A6C5,
+0xFF6A9DB2,
+0xFFBADBEA,
+0xFFF5FFFF,
+0xFFFDFCFF,
+0xFFFFFCFB,
+0xFFFFFEFD,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFFFEFF,
+0xFFFFFDFF,
+0xFFFFFEFD,
+0xFFFFFFFA,
+0xFFFEFFFA,
+0xFFFCFFFB,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFFFFFD,
+0xFFFFFEFB,
+0xFFFFFEFA,
+0xFFFFFEFB,
+0xFFFFFFFF,
+0xFFFCFFFF,
+0xFFFAFFFF,
+0xFFFEFFFF,
+0xFFFFFEFB,
+0xFFFFFDFA,
+0xFFFCFFFF,
+0xFFEFFFFF,
+0xFFA1CAE6,
+0xFF407AA0,
+0xFF4487B2,
+0xFF3376A0,
+0xFF2B6386,
+0xFF2E6383,
+0xFF32688E,
+0xFF31658A,
+0xFF366485,
+0xFF3A6788,
+0xFF36668A,
+0xFF35678C,
+0xFF36688B,
+0xFF36688B,
+0xFF37678B,
+0xFF36688B,
+0xFF356A8C,
+0xFF356B8D,
+0xFF346C8D,
+0xFF356B8D,
+0xFF376C8E,
+0xFF356B91,
+0xFF326D95,
+0xFF3679A4,
+0xFF3E8ABB,
+0xFF3C789D,
+0xFFCFE6F4,
+0xFFFBFFFF,
+0xFFFCFFFF,
+0xFFFBFFFE,
+0xFFFDFFFC,
+0xFFFEFEFE,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFCFFFF,
+0xFFF5FFFF,
+0xFFA3BACA,
+0xFF486B7F,
+0xFF47758D,
+0xFF407796,
+0xFF357196,
+0xFF35739C,
+0xFF3875A1,
+0xFF3974A0,
+0xFF37759E,
+0xFF36759E,
+0xFF36779D,
+0xFF34789D,
+0xFF35799E,
+0xFF37789E,
+0xFF3877A0,
+0xFF3978A1,
+0xFF3879A1,
+0xFF3879A3,
+0xFF377AA4,
+0xFF397AA4,
+0xFF387BA5,
+0xFF3A7BA5,
+0xFF397CA6,
+0xFF397CA7,
+0xFF387DA7,
+0xFF3A7DA8,
+0xFF3A7FA9,
+0xFF3B7EA9,
+0xFF3A7FA9,
+0xFF3C7FAA,
+0xFF3C80AD,
+0xFF3982AD,
+0xFF3982AD,
+0xFF3982AD,
+0xFF3A83AE,
+0xFF3A83AE,
+0xFF3A85AF,
+0xFF3A85AF,
+0xFF3986B2,
+0xFF3986B2,
+0xFF3A87B3,
+0xFF3A87B3,
+0xFF3A87B3,
+0xFF3A88B6,
+0xFF3A88B6,
+0xFF3A88B6,
+0xFF3889B6,
+0xFF3A8BB8,
+0xFF3A8BB8,
+0xFF3A8BB8,
+0xFF3A8BB8,
+0xFF3B8CB9,
+0xFF3B8CB9,
+0xFF3E8CBA,
+0xFF3E8CBA,
+0xFF3E8CBA,
+0xFF3E8CBA,
+0xFF3F8CBA,
+0xFF408DBB,
+0xFF408DBB,
+0xFF418EBC,
+0xFF418EBC,
+0xFF418EBC,
+0xFF4590BA,
+0xFF4590BA,
+0xFF468FBA,
+0xFF4691BB,
+0xFF4790BB,
+0xFF4792BC,
+0xFF4891BC,
+0xFF4792BC,
+0xFF4891BC,
+0xFF4792BC,
+0xFF4992BD,
+0xFF4893BD,
+0xFF4992BD,
+0xFF4994BE,
+0xFF4A93BE,
+0xFF4A93BE,
+0xFF4C93BF,
+0xFF4E92BF,
+0xFF4E92BF,
+0xFF4C93BF,
+0xFF4C93BF,
+0xFF4C93BF,
+0xFF4D94C2,
+0xFF4D94C0,
+0xFF4D94C0,
+0xFF4E93BD,
+0xFF4E93BD,
+0xFF5093BD,
+0xFF5192BA,
+0xFF5192BA,
+0xFF5494BA,
+0xFF5C97B9,
+0xFF5A8CA5,
+0xFFACCDDC,
+0xFFF6FFFF,
+0xFFFFFFFD,
+0xFFFFFCF8,
+0xFFFFFBF8,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFEFF,
+0xFFFFFDFF,
+0xFFFFFDFF,
+0xFFFFFEFF,
+0xFFFEFFFF,
+0xFFFCFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFD,
+0xFFFFFEFD,
+0xFFFEFCFD,
+0xFFFBFFFF,
+0xFFF5FFFF,
+0xFF7993A2,
+0xFF3B657D,
+0xFF336C8A,
+0xFF4A8EB5,
+0xFF4792BC,
+0xFF448EBB,
+0xFF448EBB,
+0xFF448EBB,
+0xFF428FBB,
+0xFF418EBA,
+0xFF418EBC,
+0xFF408DBB,
+0xFF408DBB,
+0xFF3E8CBA,
+0xFF3E8CBA,
+0xFF3D8BBB,
+0xFF3D8BBB,
+0xFF3D8BBB,
+0xFF3C8ABA,
+0xFF3C8ABA,
+0xFF3C8ABA,
+0xFF3E88B9,
+0xFF3E88B7,
+0xFF3D87B6,
+0xFF3D87B6,
+0xFF3D87B8,
+0xFF3E88B7,
+0xFF3D87B6,
+0xFF3B85B2,
+0xFF3C85B2,
+0xFF3B82AE,
+0xFF3E85AF,
+0xFF3C81AA,
+0xFF3C80A7,
+0xFF3F80A6,
+0xFF5C9DC3,
+0xFF68A0C1,
+0xFF6E97AB,
+0xFFEBFFFF,
+0xFFFBFFFF,
+0xFFFFFDFE,
+0xFFFFFFFA,
+0xFFFCFDF7,
+0xFFF9FFFD,
+0xFFF9FFFF,
+0xFFFEFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFB,
+0xFFFCFFFB,
+0xFFFBFFFF,
+0xFFFCFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFFFFFB,
+0xFFFFFFFA,
+0xFFFFFEFA,
+0xFFFFFEFB,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFAFDFF,
+0xFFFEFFFF,
+0xFFFFFBFA,
+0xFFFFFFFD,
+0xFFF8FFFF,
+0xFFEBFFFF,
+0xFF5385A6,
+0xFF4786AF,
+0xFF4889B1,
+0xFF28668D,
+0xFF2E6486,
+0xFF316686,
+0xFF30668C,
+0xFF306489,
+0xFF3A6889,
+0xFF376485,
+0xFF36668A,
+0xFF35678C,
+0xFF37678B,
+0xFF37678B,
+0xFF376889,
+0xFF36688B,
+0xFF356A8C,
+0xFF346A8E,
+0xFF356B8F,
+0xFF356B8D,
+0xFF376C8E,
+0xFF356B8F,
+0xFF306E95,
+0xFF377AA5,
+0xFF418BBA,
+0xFF3C789D,
+0xFFD3E9F6,
+0xFFF9FDFE,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFCFFFD,
+0xFFFDFFFC,
+0xFFFEFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFCFFFF,
+0xFFF5FFFF,
+0xFF859BB0,
+0xFF456981,
+0xFF447391,
+0xFF3A7297,
+0xFF34729B,
+0xFF3977A0,
+0xFF35709A,
+0xFF3A749C,
+0xFF39749C,
+0xFF37759C,
+0xFF36779F,
+0xFF34789F,
+0xFF34789F,
+0xFF3579A0,
+0xFF3579A0,
+0xFF3778A0,
+0xFF3877A0,
+0xFF3879A3,
+0xFF397AA4,
+0xFF3A7BA5,
+0xFF3A7BA5,
+0xFF3A7BA5,
+0xFF3A7BA5,
+0xFF397CA7,
+0xFF3A7DA8,
+0xFF3A7DA8,
+0xFF3B7EA9,
+0xFF3B7EA9,
+0xFF3C7FAA,
+0xFF3C7FAC,
+0xFF3C80AD,
+0xFF3881AC,
+0xFF3782AC,
+0xFF3883AD,
+0xFF3883AD,
+0xFF3984AE,
+0xFF3A85AF,
+0xFF3A84B1,
+0xFF3885B1,
+0xFF3986B2,
+0xFF3988B3,
+0xFF3987B5,
+0xFF3987B5,
+0xFF3987B5,
+0xFF3889B6,
+0xFF3A88B6,
+0xFF3889B6,
+0xFF398AB9,
+0xFF398AB9,
+0xFF398AB9,
+0xFF3A8BBA,
+0xFF3A8BBA,
+0xFF3A8BBA,
+0xFF3B8CBB,
+0xFF3B8CBB,
+0xFF3C8DBC,
+0xFF3C8DBC,
+0xFF3F8DBD,
+0xFF3F8DBD,
+0xFF3F8DBD,
+0xFF408EBE,
+0xFF408EBE,
+0xFF408EBC,
+0xFF428FBB,
+0xFF448FB9,
+0xFF4590BA,
+0xFF4590BA,
+0xFF4691BB,
+0xFF4691BB,
+0xFF4792BC,
+0xFF4792BC,
+0xFF4792BC,
+0xFF4792BC,
+0xFF4792BC,
+0xFF4893BD,
+0xFF4893BD,
+0xFF4893BD,
+0xFF4893BD,
+0xFF4A93BE,
+0xFF4B92BE,
+0xFF4B92BE,
+0xFF4B92BE,
+0xFF4A93C0,
+0xFF4C93C1,
+0xFF4C93C1,
+0xFF4C93C1,
+0xFF4C93BF,
+0xFF4F93C0,
+0xFF4D91BE,
+0xFF4D91BE,
+0xFF5194BF,
+0xFF5394BE,
+0xFF5191B7,
+0xFF528EB3,
+0xFF578CAB,
+0xFF597E91,
+0xFFEAFFFF,
+0xFFFBFFFF,
+0xFFFFFEFB,
+0xFFFFFEFB,
+0xFFFFFEFD,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFEFF,
+0xFFFFFCFF,
+0xFFFFFDFF,
+0xFFFFFEFF,
+0xFFFEFFFF,
+0xFFFCFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFF8FDFF,
+0xFFF1FFFF,
+0xFF355669,
+0xFF3B6A86,
+0xFF377397,
+0xFF478EB8,
+0xFF428FBD,
+0xFF4390BE,
+0xFF428FBD,
+0xFF428FBD,
+0xFF408EBC,
+0xFF3F8DBB,
+0xFF3F8DBB,
+0xFF3E8CBC,
+0xFF3E8CBC,
+0xFF3B8CBB,
+0xFF3B8CBB,
+0xFF3B8BBC,
+0xFF3A8ABB,
+0xFF3A8ABB,
+0xFF3A8ABB,
+0xFF3989BA,
+0xFF3B89BA,
+0xFF3D89BA,
+0xFF3E88B9,
+0xFF3D87B8,
+0xFF3C86B7,
+0xFF3D86B9,
+0xFF3C88B9,
+0xFF3A87B5,
+0xFF3A84B1,
+0xFF3E87B4,
+0xFF3B82AE,
+0xFF3C83AF,
+0xFF3C81AB,
+0xFF4384AC,
+0xFF4989AF,
+0xFF62A0C5,
+0xFF6295B4,
+0xFFA1C0D2,
+0xFFF1FFFF,
+0xFFFEFFFF,
+0xFFFFFDFD,
+0xFFFFFCF7,
+0xFFFFFFFA,
+0xFFF9FFFD,
+0xFFF9FFFF,
+0xFFFEFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFCFFFD,
+0xFFFBFFFF,
+0xFFFCFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFF8,
+0xFFFFFFF6,
+0xFFFFFEFA,
+0xFFFFFEFD,
+0xFFFFFEFF,
+0xFFFEFFFF,
+0xFFFBFFFF,
+0xFFFDFFFE,
+0xFFFFFFFD,
+0xFFFCFFFF,
+0xFFEFFFFF,
+0xFFC1E4F7,
+0xFF447FA1,
+0xFF4B8FB6,
+0xFF3D779C,
+0xFF326789,
+0xFF2E6081,
+0xFF336586,
+0xFF336588,
+0xFF326487,
+0xFF356687,
+0xFF366788,
+0xFF346689,
+0xFF35678A,
+0xFF36688B,
+0xFF36688B,
+0xFF37698C,
+0xFF356A8C,
+0xFF34698B,
+0xFF34688D,
+0xFF35698E,
+0xFF366C90,
+0xFF376C8E,
+0xFF346C8D,
+0xFF326E93,
+0xFF3A7BA5,
+0xFF438DBC,
+0xFF417DA2,
+0xFFD2E8F5,
+0xFFFAFEFF,
+0xFFFEFEFF,
+0xFFFEFFFF,
+0xFFFAFFFC,
+0xFFFCFFFB,
+0xFFFDFDFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFCFFFF,
+0xFFF7FFFF,
+0xFF8298A6,
+0xFF406379,
+0xFF3B6C8A,
+0xFF337198,
+0xFF32759F,
+0xFF34749A,
+0xFF377699,
+0xFF397597,
+0xFF397496,
+0xFF38739B,
+0xFF3875A1,
+0xFF3978A4,
+0xFF3676A2,
+0xFF34789F,
+0xFF367A9F,
+0xFF3778A0,
+0xFF3879A1,
+0xFF397AA4,
+0xFF397AA4,
+0xFF377AA4,
+0xFF377AA4,
+0xFF377AA4,
+0xFF387BA5,
+0xFF397CA7,
+0xFF3A7DA8,
+0xFF3A7FA9,
+0xFF3A7FA9,
+0xFF397EA8,
+0xFF397EA8,
+0xFF3A7EAB,
+0xFF3B7FAC,
+0xFF3881AE,
+0xFF3881AE,
+0xFF3982AF,
+0xFF3A83B0,
+0xFF3A83B0,
+0xFF3983B0,
+0xFF3A84B1,
+0xFF3A84B1,
+0xFF3B85B4,
+0xFF3986B4,
+0xFF3986B4,
+0xFF3A87B5,
+0xFF3A87B5,
+0xFF3987B5,
+0xFF3B87B8,
+0xFF3A88B8,
+0xFF3B89BA,
+0xFF3C8ABB,
+0xFF3C8ABB,
+0xFF3C8ABB,
+0xFF3B89BA,
+0xFF3A8ABB,
+0xFF3B8BBC,
+0xFF3C8CBD,
+0xFF3C8DBC,
+0xFF3C8DBC,
+0xFF3C8DBC,
+0xFF3D8EBD,
+0xFF3D8EBD,
+0xFF3E8FBE,
+0xFF3E8FBE,
+0xFF408EBE,
+0xFF428FBD,
+0xFF428FBB,
+0xFF4390BC,
+0xFF4390BC,
+0xFF458FBC,
+0xFF458FBC,
+0xFF468FBC,
+0xFF468FBC,
+0xFF4790BD,
+0xFF4891BE,
+0xFF4891BE,
+0xFF4891BE,
+0xFF4892BF,
+0xFF4892BF,
+0xFF4892BF,
+0xFF4893BD,
+0xFF4A93BC,
+0xFF4A93BC,
+0xFF4794C0,
+0xFF4794C2,
+0xFF4A92C2,
+0xFF4C93C1,
+0xFF4E92BF,
+0xFF4E93BD,
+0xFF4A91BB,
+0xFF4D94C0,
+0xFF4990BC,
+0xFF5094C1,
+0xFF5095BE,
+0xFF4F91B4,
+0xFF4E89A9,
+0xFF507C95,
+0xFF8BA3AF,
+0xFFF5FFFF,
+0xFFFAFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFDFDFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFDFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFEFDF9,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFEFDFF,
+0xFFFFFFFF,
+0xFFFEFEFE,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFEFF,
+0xFFFAFFFF,
+0xFF9BB2C2,
+0xFF365E77,
+0xFF326987,
+0xFF4181A5,
+0xFF4A91BB,
+0xFF448EBB,
+0xFF4390BE,
+0xFF418FBD,
+0xFF408EBC,
+0xFF3F8DBB,
+0xFF3F8DBB,
+0xFF3D8EBB,
+0xFF3C8DBC,
+0xFF3C8DBC,
+0xFF3B8CBB,
+0xFF3B8CBB,
+0xFF3B8BBC,
+0xFF3A8ABB,
+0xFF3B89BA,
+0xFF3A88B9,
+0xFF3B89BA,
+0xFF3C8ABB,
+0xFF3B89B9,
+0xFF3B89B9,
+0xFF3D87B8,
+0xFF3D86B9,
+0xFF3B87BB,
+0xFF3987B8,
+0xFF3788B3,
+0xFF3887B0,
+0xFF3C85B0,
+0xFF3D84B0,
+0xFF3A84B3,
+0xFF3C85B2,
+0xFF3C7BA4,
+0xFF5F99BF,
+0xFF629DBF,
+0xFF5E8CA4,
+0xFFE6FAFF,
+0xFFF7FCFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFEFFFF,
+0xFFFDFFFE,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFF8,
+0xFFFFFFF6,
+0xFFFFFEFB,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFEFE,
+0xFFF8FFFF,
+0xFFEDFFFF,
+0xFF7BA5BB,
+0xFF4C8BAE,
+0xFF5091B9,
+0xFF33698B,
+0xFF326383,
+0xFF316282,
+0xFF336484,
+0xFF346586,
+0xFF346586,
+0xFF346687,
+0xFF346687,
+0xFF35678A,
+0xFF35678A,
+0xFF35678A,
+0xFF36688B,
+0xFF34698B,
+0xFF34698B,
+0xFF34698B,
+0xFF34698B,
+0xFF34688D,
+0xFF366A8F,
+0xFF366B8D,
+0xFF356B8D,
+0xFF326C91,
+0xFF3A7BA3,
+0xFF4791BE,
+0xFF4180A3,
+0xFFD0E8F4,
+0xFFFCFFFF,
+0xFFFEFEFF,
+0xFFFEFEFF,
+0xFFFAFFFB,
+0xFFFCFFFB,
+0xFFFEFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFF6FDFF,
+0xFFAEBECB,
+0xFF335368,
+0xFF3A6987,
+0xFF347094,
+0xFF307197,
+0xFF337397,
+0xFF357497,
+0xFF3B7897,
+0xFF397496,
+0xFF37729A,
+0xFF35729E,
+0xFF3574A0,
+0xFF3777A3,
+0xFF397AA2,
+0xFF34789D,
+0xFF3778A0,
+0xFF3879A1,
+0xFF3879A3,
+0xFF397AA4,
+0xFF377AA4,
+0xFF377AA4,
+0xFF377AA4,
+0xFF387BA5,
+0xFF397CA7,
+0xFF397CA7,
+0xFF397EA8,
+0xFF397EA8,
+0xFF397EA8,
+0xFF3A7FA9,
+0xFF3A7EAB,
+0xFF387FAB,
+0xFF3980AE,
+0xFF3881AE,
+0xFF3982AF,
+0xFF3982AF,
+0xFF3982AF,
+0xFF3A83B0,
+0xFF3983B0,
+0xFF3A84B1,
+0xFF3A84B3,
+0xFF3B85B4,
+0xFF3986B4,
+0xFF3986B4,
+0xFF3A87B5,
+0xFF3A87B5,
+0xFF3B87B8,
+0xFF3B87B8,
+0xFF3C88BA,
+0xFF3C88BA,
+0xFF3C88BA,
+0xFF3C88BA,
+0xFF3B89BA,
+0xFF3C8ABB,
+0xFF3A8ABB,
+0xFF3B8BBC,
+0xFF3B8CBB,
+0xFF3B8CBB,
+0xFF3B8CBB,
+0xFF3C8DBC,
+0xFF3C8DBC,
+0xFF3D8EBD,
+0xFF3D8EBD,
+0xFF3D8EBD,
+0xFF418FBD,
+0xFF428FBD,
+0xFF428FBB,
+0xFF4390BC,
+0xFF458FBC,
+0xFF458FBC,
+0xFF468FBC,
+0xFF468FBC,
+0xFF4790BD,
+0xFF4790BD,
+0xFF4891BE,
+0xFF4891BE,
+0xFF4791BE,
+0xFF4791BE,
+0xFF4791BE,
+0xFF4792BC,
+0xFF4992BB,
+0xFF4893BB,
+0xFF4594BF,
+0xFF4694C2,
+0xFF4993C2,
+0xFF4B92C0,
+0xFF4D91BE,
+0xFF4D92BC,
+0xFF4C93BD,
+0xFF4A91BD,
+0xFF4C95C2,
+0xFF4990BC,
+0xFF4E93BA,
+0xFF4484A7,
+0xFF457A99,
+0xFF4C7287,
+0xFFD0E1E8,
+0xFFFBFFFF,
+0xFFFBFFFF,
+0xFFFCFFFF,
+0xFFFCFDFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFEFEFE,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFFFEFB,
+0xFFFEFDF9,
+0xFFFDFDFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFEFFFF,
+0xFFF8FFFF,
+0xFF476476,
+0xFF32607A,
+0xFF306B8D,
+0xFF4B8FB6,
+0xFF458CB8,
+0xFF448EBB,
+0xFF428FBD,
+0xFF408EBC,
+0xFF3F8DBB,
+0xFF3E8CBA,
+0xFF3C8DBA,
+0xFF3C8DBA,
+0xFF3C8DBC,
+0xFF3C8DBC,
+0xFF3B8CBB,
+0xFF3B8CBB,
+0xFF3A8ABB,
+0xFF3A8ABB,
+0xFF3B89BA,
+0xFF3B89BA,
+0xFF3B89BA,
+0xFF3B89BA,
+0xFF3A88B8,
+0xFF3A88B8,
+0xFF3D87B8,
+0xFF3C85B8,
+0xFF3A86BA,
+0xFF3886B7,
+0xFF3687B2,
+0xFF3887AE,
+0xFF3A83AC,
+0xFF3F86B2,
+0xFF3983B2,
+0xFF3780AD,
+0xFF4483AC,
+0xFF5C94B7,
+0xFF5D92B1,
+0xFF7AA0B5,
+0xFFF2FFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFEFE,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFA,
+0xFFFFFFF8,
+0xFFFFFEFD,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFF4FDFF,
+0xFFDFFFFF,
+0xFF51839C,
+0xFF538FB4,
+0xFF4B89B0,
+0xFF2A5F81,
+0xFF326383,
+0xFF336484,
+0xFF326383,
+0xFF336485,
+0xFF346586,
+0xFF336586,
+0xFF346687,
+0xFF35678A,
+0xFF35678A,
+0xFF35678A,
+0xFF36688B,
+0xFF34698B,
+0xFF34698B,
+0xFF34698B,
+0xFF356A8C,
+0xFF346A8E,
+0xFF35698E,
+0xFF376C8E,
+0xFF366B8D,
+0xFF336B90,
+0xFF3B7BA1,
+0xFF4C97C1,
+0xFF4584A7,
+0xFFC9E0EE,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFEFFFF,
+0xFFFCFEFB,
+0xFFFEFFFB,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFF7FFFF,
+0xFF2D4C60,
+0xFF325E79,
+0xFF2F627F,
+0xFF37708E,
+0xFF397597,
+0xFF37759A,
+0xFF377398,
+0xFF367199,
+0xFF37759C,
+0xFF37769F,
+0xFF31759C,
+0xFF34789F,
+0xFF3A79A2,
+0xFF37769F,
+0xFF3778A0,
+0xFF3879A1,
+0xFF3879A1,
+0xFF3879A1,
+0xFF3879A3,
+0xFF397AA4,
+0xFF377AA4,
+0xFF387BA5,
+0xFF397CA7,
+0xFF387BA6,
+0xFF387DA7,
+0xFF387DA7,
+0xFF397EA8,
+0xFF3A7FA9,
+0xFF3A7FA9,
+0xFF387FA9,
+0xFF3980AC,
+0xFF3881AC,
+0xFF3982AD,
+0xFF3982AD,
+0xFF3982AF,
+0xFF3A83B0,
+0xFF3983B0,
+0xFF3A84B1,
+0xFF3A84B3,
+0xFF3A84B3,
+0xFF3986B4,
+0xFF3986B4,
+0xFF3A87B5,
+0xFF3A87B5,
+0xFF3A87B5,
+0xFF3B87B8,
+0xFF3C88BA,
+0xFF3B87B9,
+0xFF3B87B8,
+0xFF3C88B9,
+0xFF3B89B9,
+0xFF3C8ABA,
+0xFF3A8BBA,
+0xFF3A8BBA,
+0xFF3A8BBA,
+0xFF3B8CBB,
+0xFF3B8CBB,
+0xFF3B8CBB,
+0xFF3C8DBC,
+0xFF3C8DBC,
+0xFF3D8EBD,
+0xFF3D8EBD,
+0xFF408EBC,
+0xFF408EBC,
+0xFF418EBC,
+0xFF428FBD,
+0xFF4390BE,
+0xFF4390BE,
+0xFF458FBC,
+0xFF458FBC,
+0xFF4690BD,
+0xFF4690BD,
+0xFF4690BD,
+0xFF4791BE,
+0xFF4791BE,
+0xFF4791BE,
+0xFF4791BE,
+0xFF4792BC,
+0xFF4792BA,
+0xFF4792BC,
+0xFF4791BE,
+0xFF4892C1,
+0xFF4892BF,
+0xFF4992BF,
+0xFF4A91BD,
+0xFF4D91BE,
+0xFF4C93BF,
+0xFF4790BD,
+0xFF4A94C1,
+0xFF4992BB,
+0xFF5393B9,
+0xFF437B9E,
+0xFF467893,
+0xFF54778A,
+0xFFF4FFFF,
+0xFFFBFFFF,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFDFFFE,
+0xFFFDFFFE,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFDFCFA,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFBFCFF,
+0xFFFCFDFF,
+0xFFFDFFFE,
+0xFFFBFFFF,
+0xFFF6FDFF,
+0xFFC9D9E6,
+0xFF2D4D62,
+0xFF346381,
+0xFF39779C,
+0xFF458CB6,
+0xFF428CB9,
+0xFF418EBC,
+0xFF408EBE,
+0xFF3F8DBD,
+0xFF3C8DBC,
+0xFF3B8CBB,
+0xFF3B8CBB,
+0xFF3B8CBB,
+0xFF3B8CBB,
+0xFF3B8CBB,
+0xFF3B8CBB,
+0xFF3A8BBA,
+0xFF3B89B9,
+0xFF3B89B9,
+0xFF3C8ABB,
+0xFF3C8ABB,
+0xFF3C88BA,
+0xFF3A88B8,
+0xFF3A88B6,
+0xFF3A87B5,
+0xFF3D85B7,
+0xFF3D84B8,
+0xFF3985B6,
+0xFF3886B4,
+0xFF3586B1,
+0xFF3786AF,
+0xFF3984AE,
+0xFF3B82AE,
+0xFF3980AC,
+0xFF3C81AB,
+0xFF4F8FB3,
+0xFF5B94B2,
+0xFF5887A1,
+0xFFBEDDEF,
+0xFFF7FFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFEFE,
+0xFFFEFEFE,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFB,
+0xFFFFFFFB,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFEFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFF5FFFF,
+0xFFA0C9DB,
+0xFF5289A7,
+0xFF5C96BC,
+0xFF377199,
+0xFF2A5F81,
+0xFF346585,
+0xFF346585,
+0xFF316282,
+0xFF336485,
+0xFF336485,
+0xFF326485,
+0xFF356788,
+0xFF35678A,
+0xFF35678A,
+0xFF35678A,
+0xFF35678A,
+0xFF33688A,
+0xFF34698B,
+0xFF356A8C,
+0xFF356A8C,
+0xFF356B8F,
+0xFF346A8E,
+0xFF396B8E,
+0xFF376C8E,
+0xFF33698D,
+0xFF39779E,
+0xFF4F9AC2,
+0xFF4988AB,
+0xFFB9D3E2,
+0xFFF9FFFF,
+0xFFFAFFFF,
+0xFFFEFFFF,
+0xFFFEFEFC,
+0xFFFFFFFB,
+0xFFFFFFFF,
+0xFFFEFEFE,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFCFCFC,
+0xFFF9FFFF,
+0xFFABC1CF,
+0xFF214458,
+0xFF2C566E,
+0xFF285A75,
+0xFF2F6685,
+0xFF3A7499,
+0xFF39739B,
+0xFF38739D,
+0xFF36769C,
+0xFF36779D,
+0xFF34789D,
+0xFF32769B,
+0xFF37759E,
+0xFF3A78A1,
+0xFF3877A0,
+0xFF3778A0,
+0xFF3879A1,
+0xFF3879A1,
+0xFF3879A3,
+0xFF3879A3,
+0xFF377AA4,
+0xFF387BA5,
+0xFF387BA6,
+0xFF387BA6,
+0xFF377CA6,
+0xFF387DA7,
+0xFF397EA8,
+0xFF3A7FA9,
+0xFF3A7FA9,
+0xFF3A7FA9,
+0xFF387FAB,
+0xFF3881AC,
+0xFF3881AC,
+0xFF3881AC,
+0xFF3982AF,
+0xFF3982AF,
+0xFF3983B0,
+0xFF3983B0,
+0xFF3A84B3,
+0xFF3A84B3,
+0xFF3885B3,
+0xFF3986B4,
+0xFF3986B4,
+0xFF3A87B5,
+0xFF3A87B5,
+0xFF3A87B5,
+0xFF3B87B8,
+0xFF3B87B9,
+0xFF3A86B7,
+0xFF3B87B8,
+0xFF3B89B9,
+0xFF3C8ABA,
+0xFF398AB9,
+0xFF398AB9,
+0xFF3A8BBA,
+0xFF3A8BBA,
+0xFF3B8CBB,
+0xFF3B8CBB,
+0xFF3C8DBC,
+0xFF3C8DBC,
+0xFF3C8DBC,
+0xFF3C8DBC,
+0xFF3F8DBD,
+0xFF3F8DBB,
+0xFF418EBC,
+0xFF418EBC,
+0xFF428FBD,
+0xFF428FBD,
+0xFF458FBC,
+0xFF458FBC,
+0xFF458FBC,
+0xFF458FBC,
+0xFF458FBC,
+0xFF4690BD,
+0xFF4690BD,
+0xFF4690BD,
+0xFF4690BD,
+0xFF4690BD,
+0xFF4792BC,
+0xFF4792BC,
+0xFF4891BE,
+0xFF4891BE,
+0xFF4892BF,
+0xFF4892BF,
+0xFF4A91BD,
+0xFF4A91BD,
+0xFF4992BF,
+0xFF4993C0,
+0xFF4895C1,
+0xFF4D94BE,
+0xFF417DA2,
+0xFF3D6F90,
+0xFF3D6780,
+0xFFA1C1D0,
+0xFFF3FFFF,
+0xFFF9FDFE,
+0xFFFCFFFF,
+0xFFFBFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFCFCFC,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFDFE,
+0xFFFFFDFE,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFCFFFF,
+0xFFF5FFFF,
+0xFF627C8B,
+0xFF335970,
+0xFF2A5D7C,
+0xFF498AB2,
+0xFF428CB9,
+0xFF4491BF,
+0xFF3B89B9,
+0xFF3F8DBD,
+0xFF3E8CBC,
+0xFF3B8CBB,
+0xFF3B8CBB,
+0xFF3B8CBB,
+0xFF3B8CBB,
+0xFF3B8CBB,
+0xFF3A8BBA,
+0xFF3A8BBA,
+0xFF398AB9,
+0xFF3B89B9,
+0xFF3B89B9,
+0xFF3B89BA,
+0xFF3B89BA,
+0xFF3B87B9,
+0xFF3A86B7,
+0xFF3A87B5,
+0xFF3A87B5,
+0xFF3D85B7,
+0xFF3D85B7,
+0xFF3986B4,
+0xFF3887B2,
+0xFF3786AF,
+0xFF3786AF,
+0xFF3C87B1,
+0xFF3980AC,
+0xFF3C7FAA,
+0xFF4081A7,
+0xFF5191B4,
+0xFF5890AB,
+0xFF61879C,
+0xFFEDFFFF,
+0xFFF9FFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFEFE,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFEFE,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFEFFFF,
+0xFFF0FFFF,
+0xFF6090A7,
+0xFF5793B5,
+0xFF6097BE,
+0xFF285C84,
+0xFF306285,
+0xFF346585,
+0xFF336484,
+0xFF326383,
+0xFF346586,
+0xFF336485,
+0xFF326384,
+0xFF356687,
+0xFF356788,
+0xFF356788,
+0xFF35678A,
+0xFF35678A,
+0xFF33688A,
+0xFF34698B,
+0xFF34698B,
+0xFF356A8C,
+0xFF356B8D,
+0xFF33698B,
+0xFF396B8E,
+0xFF396B8E,
+0xFF34688D,
+0xFF377398,
+0xFF529CC3,
+0xFF4F8EAF,
+0xFFA6C3D5,
+0xFFF7FFFF,
+0xFFF9FEFF,
+0xFFFEFFFF,
+0xFFFFFDFE,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFDFFFE,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFF9FDFE,
+0xFFF9FFFF,
+0xFF899BA5,
+0xFF24475B,
+0xFF27536C,
+0xFF265573,
+0xFF2C6183,
+0xFF3B7299,
+0xFF3B79A2,
+0xFF34759B,
+0xFF2F7398,
+0xFF34789B,
+0xFF35769C,
+0xFF36719B,
+0xFF3B76A0,
+0xFF37769F,
+0xFF3778A0,
+0xFF3778A0,
+0xFF3879A1,
+0xFF3879A3,
+0xFF3879A3,
+0xFF377AA4,
+0xFF377AA4,
+0xFF377AA4,
+0xFF387BA5,
+0xFF397CA7,
+0xFF397CA7,
+0xFF387DA7,
+0xFF387DA7,
+0xFF397EA8,
+0xFF3B80AA,
+0xFF387FAB,
+0xFF387FAB,
+0xFF3980AC,
+0xFF3980AC,
+0xFF3982AF,
+0xFF3982AF,
+0xFF3982AF,
+0xFF3982AF,
+0xFF3983B0,
+0xFF3A84B1,
+0xFF3A84B3,
+0xFF3A84B3,
+0xFF3986B4,
+0xFF3986B4,
+0xFF3A87B5,
+0xFF3A87B5,
+0xFF3B87B8,
+0xFF3A86B7,
+0xFF3A86B7,
+0xFF3B87B8,
+0xFF3B89B9,
+0xFF3B89B9,
+0xFF3B89B9,
+0xFF3A88B8,
+0xFF3A8BBA,
+0xFF3A8BBA,
+0xFF3B8CBB,
+0xFF3B8CBB,
+0xFF3B8BBC,
+0xFF3C8CBD,
+0xFF3C8CBD,
+0xFF3C8DBC,
+0xFF3C8DBC,
+0xFF3C8DBC,
+0xFF3F8DBD,
+0xFF3F8DBD,
+0xFF408EBC,
+0xFF418FBD,
+0xFF428FBD,
+0xFF428FBD,
+0xFF428FBD,
+0xFF428FBD,
+0xFF458FBC,
+0xFF458FBC,
+0xFF458FBC,
+0xFF4690BD,
+0xFF4690BD,
+0xFF4690BD,
+0xFF4491BD,
+0xFF4690BD,
+0xFF4990BE,
+0xFF4990BE,
+0xFF4791BE,
+0xFF4792BC,
+0xFF4A91BD,
+0xFF4A91BD,
+0xFF4892BF,
+0xFF4693BF,
+0xFF4592BE,
+0xFF4E93BC,
+0xFF366C90,
+0xFF3E6A87,
+0xFF385B71,
+0xFFEBFFFF,
+0xFFF8FFFF,
+0xFFFEFFFF,
+0xFFFDFFFE,
+0xFFFCFEFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFCFCFC,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFEFE,
+0xFFFEFEFE,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFCFCFC,
+0xFFF9FEFF,
+0xFFE7FDFF,
+0xFF274A5E,
+0xFF2B5973,
+0xFF2E6689,
+0xFF4B8FBC,
+0xFF428EBF,
+0xFF3E8CBC,
+0xFF3B8BBC,
+0xFF3C8CBD,
+0xFF3C8CBD,
+0xFF3B8BBC,
+0xFF3B8BBC,
+0xFF3B8CBB,
+0xFF3B8CBB,
+0xFF3B8CBB,
+0xFF3A8BBA,
+0xFF398AB9,
+0xFF398AB9,
+0xFF3C8ABA,
+0xFF3B89B9,
+0xFF3B89B9,
+0xFF3A88B8,
+0xFF3B87B8,
+0xFF3B88B6,
+0xFF3A87B3,
+0xFF3C86B3,
+0xFF3E84B7,
+0xFF3E84B7,
+0xFF3B86B0,
+0xFF3886AD,
+0xFF3885AF,
+0xFF3885B1,
+0xFF3983B0,
+0xFF3980AC,
+0xFF4180A9,
+0xFF4382A5,
+0xFF5392B1,
+0xFF51859B,
+0xFF9BB8C8,
+0xFFF5FFFF,
+0xFFFBFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFEFE,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFDFF,
+0xFFFCFAFF,
+0xFFF8FFFF,
+0xFFC4E0EE,
+0xFF538BA6,
+0xFF61A1C4,
+0xFF477CA4,
+0xFF2D5D85,
+0xFF326384,
+0xFF326383,
+0xFF316282,
+0xFF336484,
+0xFF366788,
+0xFF346586,
+0xFF326384,
+0xFF346586,
+0xFF346687,
+0xFF346687,
+0xFF35678A,
+0xFF35678A,
+0xFF34698B,
+0xFF34698B,
+0xFF34698B,
+0xFF356A8C,
+0xFF346A8C,
+0xFF33698B,
+0xFF386A8D,
+0xFF39698D,
+0xFF36688D,
+0xFF346E93,
+0xFF539BC1,
+0xFF5495B5,
+0xFF8EB1C5,
+0xFFF2FFFF,
+0xFFF8FFFF,
+0xFFFFFFFF,
+0xFFFFFCFF,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFF9FFFF,
+0xFF889EAC,
+0xFF1C3F55,
+0xFF2B536D,
+0xFF214F70,
+0xFF2A6084,
+0xFF377398,
+0xFF39799D,
+0xFF33749A,
+0xFF35769C,
+0xFF36769C,
+0xFF36749D,
+0xFF3977A0,
+0xFF37769F,
+0xFF3778A0,
+0xFF3778A0,
+0xFF3879A1,
+0xFF3879A3,
+0xFF3879A3,
+0xFF377AA4,
+0xFF377AA4,
+0xFF3679A3,
+0xFF387BA5,
+0xFF397CA7,
+0xFF397CA7,
+0xFF377CA6,
+0xFF377CA6,
+0xFF397EA8,
+0xFF3A7FA9,
+0xFF387FAB,
+0xFF387FAB,
+0xFF387FAB,
+0xFF3980AC,
+0xFF3881AE,
+0xFF3982AF,
+0xFF3982AF,
+0xFF3982AF,
+0xFF3983B0,
+0xFF3983B0,
+0xFF3983B2,
+0xFF3A84B3,
+0xFF3885B3,
+0xFF3986B4,
+0xFF3986B4,
+0xFF3986B4,
+0xFF3A86B7,
+0xFF3A86B7,
+0xFF3A86B7,
+0xFF3B87B8,
+0xFF3B89B9,
+0xFF3B89B9,
+0xFF3B89B9,
+0xFF3A88B8,
+0xFF3A8BBA,
+0xFF3A8BBA,
+0xFF3A8BBA,
+0xFF3B8CBB,
+0xFF3B8BBC,
+0xFF3B8BBC,
+0xFF3C8CBD,
+0xFF3C8CBD,
+0xFF3C8DBC,
+0xFF3C8DBC,
+0xFF3E8CBC,
+0xFF3F8DBD,
+0xFF3F8DBB,
+0xFF408EBC,
+0xFF418EBC,
+0xFF418EBC,
+0xFF418EBC,
+0xFF428FBD,
+0xFF448EBB,
+0xFF448EBB,
+0xFF458FBC,
+0xFF458FBC,
+0xFF458FBC,
+0xFF458FBC,
+0xFF4491BD,
+0xFF4690BD,
+0xFF4790BD,
+0xFF488FBD,
+0xFF4891BC,
+0xFF4891BC,
+0xFF4891BC,
+0xFF4791BE,
+0xFF4693C1,
+0xFF428FBB,
+0xFF4A95BF,
+0xFF4384AC,
+0xFF356788,
+0xFF365B75,
+0xFF7792A3,
+0xFFF2FFFF,
+0xFFFBFFFF,
+0xFFFEFFFF,
+0xFFFCFEFD,
+0xFFFEFFFF,
+0xFFFEFEFE,
+0xFFFEFEFE,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFDFDFD,
+0xFFFFFFFD,
+0xFFFEFFFF,
+0xFFFAFBFD,
+0xFFFEFEFF,
+0xFFF8FFFF,
+0xFF8DAABA,
+0xFF254F68,
+0xFF275A79,
+0xFF3F7DA2,
+0xFF468CBD,
+0xFF3D8BBC,
+0xFF398BBB,
+0xFF3D8FBF,
+0xFF3B8DBD,
+0xFF3C8CBD,
+0xFF3B8BBC,
+0xFF3B8BBC,
+0xFF3B8CBB,
+0xFF3B8CBB,
+0xFF3A8BBA,
+0xFF398AB9,
+0xFF3889B8,
+0xFF398AB9,
+0xFF3B89B9,
+0xFF3B89B9,
+0xFF3A88B8,
+0xFF3987B7,
+0xFF3A86B7,
+0xFF3B88B6,
+0xFF3C86B3,
+0xFF3D86B3,
+0xFF3E84B7,
+0xFF3C84B4,
+0xFF3B86AE,
+0xFF3886AD,
+0xFF3885AF,
+0xFF3784B0,
+0xFF3882B1,
+0xFF387FAB,
+0xFF4381A8,
+0xFF4B86A8,
+0xFF528EA8,
+0xFF4E7D8F,
+0xFFE2F6FF,
+0xFFFAFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFEFE,
+0xFFFEFEFE,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFEFFFF,
+0xFFFCFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFDFF,
+0xFFFCFBFF,
+0xFFF1FFFF,
+0xFF87ACBE,
+0xFF639CB9,
+0xFF64A3C6,
+0xFF2C6087,
+0xFF356289,
+0xFF346284,
+0xFF326081,
+0xFF316282,
+0xFF346585,
+0xFF346585,
+0xFF336484,
+0xFF346586,
+0xFF336485,
+0xFF346687,
+0xFF346687,
+0xFF35678A,
+0xFF35678A,
+0xFF36688B,
+0xFF36688B,
+0xFF36688B,
+0xFF34698B,
+0xFF346A8C,
+0xFF33698B,
+0xFF37698C,
+0xFF39698D,
+0xFF38688E,
+0xFF32688E,
+0xFF5498BD,
+0xFF599AB8,
+0xFF739DB3,
+0xFFEEFFFF,
+0xFFFBFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFDFE,
+0xFFFFFFFD,
+0xFFFFFFFB,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFBFBF9,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFCFDFF,
+0xFFF9FFFF,
+0xFFA2B3C3,
+0xFF1A3C55,
+0xFF2A5774,
+0xFF215471,
+0xFF2B6481,
+0xFF347396,
+0xFF38789E,
+0xFF36759E,
+0xFF35749D,
+0xFF37769F,
+0xFF37769F,
+0xFF36779F,
+0xFF36779F,
+0xFF3778A0,
+0xFF3778A0,
+0xFF3778A0,
+0xFF3879A1,
+0xFF397AA4,
+0xFF397AA4,
+0xFF377AA4,
+0xFF377AA4,
+0xFF387BA5,
+0xFF387BA5,
+0xFF377CA6,
+0xFF387DA7,
+0xFF387DA7,
+0xFF397EA8,
+0xFF387FAB,
+0xFF387FAB,
+0xFF387FAB,
+0xFF387FAB,
+0xFF3980AC,
+0xFF3A81AD,
+0xFF3982AD,
+0xFF3881AC,
+0xFF3A83B0,
+0xFF3A83B0,
+0xFF3983B0,
+0xFF3A84B1,
+0xFF3A84B3,
+0xFF3B85B4,
+0xFF3B85B4,
+0xFF3B85B4,
+0xFF3A87B5,
+0xFF3A87B5,
+0xFF3B88B6,
+0xFF3C89B7,
+0xFF3C89B7,
+0xFF3C89B7,
+0xFF3B89B9,
+0xFF3B89B9,
+0xFF3B89B9,
+0xFF3C8ABA,
+0xFF3C8ABB,
+0xFF3C8ABB,
+0xFF3A8ABB,
+0xFF3B8BBC,
+0xFF3B8BBC,
+0xFF3B8BBC,
+0xFF3A8CBB,
+0xFF3B8DBC,
+0xFF3C8DBC,
+0xFF3C8DBC,
+0xFF3D8EBD,
+0xFF3D8EBD,
+0xFF3F8DBB,
+0xFF3F8DBB,
+0xFF408EBC,
+0xFF408EBC,
+0xFF418EBC,
+0xFF428FBD,
+0xFF428FBB,
+0xFF4390BC,
+0xFF4390BC,
+0xFF4390BC,
+0xFF458FBE,
+0xFF458FBE,
+0xFF458FBC,
+0xFF4790BD,
+0xFF488FBB,
+0xFF488FBB,
+0xFF4690BD,
+0xFF4592BE,
+0xFF4492C0,
+0xFF4592BE,
+0xFF5196C0,
+0xFF2E6A8F,
+0xFF2B5A78,
+0xFF2C4F63,
+0xFFCFE2F0,
+0xFFF5FEFF,
+0xFFF9FDFF,
+0xFFFDFDFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFDFDFD,
+0xFFFEFEFE,
+0xFFFEFEFE,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFCFF,
+0xFFFFFEFF,
+0xFFFEFEFC,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFEFFDFF,
+0xFF2F5266,
+0xFF20526D,
+0xFF225D7F,
+0xFF4889B3,
+0xFF438DBE,
+0xFF3D8DC0,
+0xFF3C8FC1,
+0xFF388BBD,
+0xFF3B8DBD,
+0xFF3B8DBD,
+0xFF3A8CBC,
+0xFF3A8CBC,
+0xFF3B8BBC,
+0xFF3A8ABB,
+0xFF3989BA,
+0xFF3989BA,
+0xFF3B89B9,
+0xFF3B89B9,
+0xFF3A88B8,
+0xFF3A88B8,
+0xFF3A86B7,
+0xFF3A86B7,
+0xFF3A87B5,
+0xFF3B88B6,
+0xFF3C86B3,
+0xFF3D86B3,
+0xFF3C84B4,
+0xFF3B85B2,
+0xFF3886AD,
+0xFF3886AD,
+0xFF3983B0,
+0xFF3983B2,
+0xFF3C84B6,
+0xFF3A7EAB,
+0xFF4381A8,
+0xFF4E87A5,
+0xFF4B7F95,
+0xFF749AA7,
+0xFFF5FFFF,
+0xFFFCFCFE,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFEFE,
+0xFFFEFEFE,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFDFF,
+0xFFFFFEFF,
+0xFFFCFFFF,
+0xFFFBFFFF,
+0xFFFCFFFD,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFCFE,
+0xFFFCFFFF,
+0xFFDFF9FF,
+0xFF6390A7,
+0xFF649DBB,
+0xFF5490B2,
+0xFF2B5D82,
+0xFF335F84,
+0xFF346284,
+0xFF326081,
+0xFF326383,
+0xFF336484,
+0xFF316282,
+0xFF336484,
+0xFF366788,
+0xFF346586,
+0xFF336586,
+0xFF346687,
+0xFF35678A,
+0xFF35678A,
+0xFF36688B,
+0xFF36688B,
+0xFF36688B,
+0xFF34698B,
+0xFF356B8D,
+0xFF346A8C,
+0xFF37698C,
+0xFF39698D,
+0xFF3A678E,
+0xFF306489,
+0xFF5595B9,
+0xFF5B9CBA,
+0xFF5D8DA3,
+0xFFE6FFFF,
+0xFFF9FFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFEFEFF,
+0xFFFFFEFA,
+0xFFFFFFFB,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFCFEFD,
+0xFFFEFFFF,
+0xFFFFFEFF,
+0xFFF7FDFF,
+0xFFA7BDD2,
+0xFF1C4058,
+0xFF2E5C73,
+0xFF215771,
+0xFF2A6381,
+0xFF387498,
+0xFF39749E,
+0xFF3774A0,
+0xFF3778A2,
+0xFF31749E,
+0xFF36779F,
+0xFF36779F,
+0xFF3778A0,
+0xFF3778A0,
+0xFF3778A0,
+0xFF3879A1,
+0xFF3879A3,
+0xFF397AA4,
+0xFF387BA5,
+0xFF377AA4,
+0xFF377AA4,
+0xFF387BA5,
+0xFF387DA7,
+0xFF387DA7,
+0xFF387DA7,
+0xFF387DA7,
+0xFF3A7EAB,
+0xFF387FAB,
+0xFF377EAA,
+0xFF387FAB,
+0xFF3980AC,
+0xFF3980AC,
+0xFF3881AC,
+0xFF3881AC,
+0xFF3A83B0,
+0xFF3A83B0,
+0xFF3983B0,
+0xFF3983B0,
+0xFF3A84B3,
+0xFF3A84B3,
+0xFF3B85B4,
+0xFF3B85B4,
+0xFF3986B4,
+0xFF3A87B5,
+0xFF3C89B7,
+0xFF3C89B7,
+0xFF3B88B6,
+0xFF3B88B6,
+0xFF3B89B9,
+0xFF3B89B9,
+0xFF3B89B9,
+0xFF3B89B9,
+0xFF3B89BA,
+0xFF3C8ABB,
+0xFF3A8ABB,
+0xFF3A8ABB,
+0xFF3A8ABB,
+0xFF3B8BBC,
+0xFF3A8CBB,
+0xFF3B8DBC,
+0xFF3C8DBC,
+0xFF3C8DBC,
+0xFF3C8DBC,
+0xFF3C8DBC,
+0xFF3F8DBB,
+0xFF3F8DBB,
+0xFF408EBC,
+0xFF408EBC,
+0xFF418EBC,
+0xFF428FBD,
+0xFF428FBB,
+0xFF428FBB,
+0xFF4390BC,
+0xFF4390BE,
+0xFF458FC0,
+0xFF458FC0,
+0xFF4390BE,
+0xFF458FBC,
+0xFF498DBA,
+0xFF488FBB,
+0xFF4491BD,
+0xFF4391BF,
+0xFF4192BF,
+0xFF448EBB,
+0xFF498AB2,
+0xFF215779,
+0xFF2B5770,
+0xFF456272,
+0xFFF5FFFF,
+0xFFFCFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFBFBFB,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFBFBFB,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFDFDFB,
+0xFFFFFFFD,
+0xFFFEFDFB,
+0xFFFFFFFF,
+0xFFF6FDFF,
+0xFFBFD2E0,
+0xFF1C455B,
+0xFF1E5573,
+0xFF2C6C92,
+0xFF4C93BF,
+0xFF3E87BA,
+0xFF3C8CBF,
+0xFF398CBE,
+0xFF378DBE,
+0xFF3B8DBD,
+0xFF3A8CBC,
+0xFF3A8CBC,
+0xFF3A8CBC,
+0xFF3A8ABB,
+0xFF3A8ABB,
+0xFF3989BA,
+0xFF3888B9,
+0xFF3B89B9,
+0xFF3A88B8,
+0xFF3987B7,
+0xFF3987B7,
+0xFF3A86B7,
+0xFF3B87B8,
+0xFF3A87B5,
+0xFF3A87B5,
+0xFF3C84B4,
+0xFF3C84B4,
+0xFF3B85B2,
+0xFF3885B1,
+0xFF3885AF,
+0xFF3784AE,
+0xFF3882AF,
+0xFF3981B1,
+0xFF3880B0,
+0xFF3A7EAB,
+0xFF4482A7,
+0xFF4E84A0,
+0xFF4D7889,
+0xFFBCD8E3,
+0xFFF9FFFF,
+0xFFFFFEFF,
+0xFFFEFEFE,
+0xFFFEFEFE,
+0xFFFEFEFE,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFBFFFF,
+0xFFF6FFFC,
+0xFFFAFFFB,
+0xFFFEFFFD,
+0xFFFCFBFF,
+0xFFFFFEFF,
+0xFFFFFDFC,
+0xFFF8FFFF,
+0xFFA2C7D9,
+0xFF659BB5,
+0xFF6EA5C3,
+0xFF39708F,
+0xFF2B5B7F,
+0xFF346286,
+0xFF326082,
+0xFF336182,
+0xFF346283,
+0xFF346283,
+0xFF326383,
+0xFF326383,
+0xFF336485,
+0xFF336485,
+0xFF336485,
+0xFF356687,
+0xFF35678A,
+0xFF346689,
+0xFF346689,
+0xFF36688B,
+0xFF36688B,
+0xFF34698B,
+0xFF356B8D,
+0xFF33698B,
+0xFF356A8C,
+0xFF386A8D,
+0xFF3E6A8F,
+0xFF37678D,
+0xFF4682A6,
+0xFF65A4C3,
+0xFF5C92AA,
+0xFFC6EBFB,
+0xFFF7FEFF,
+0xFFFFFDFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFDF9,
+0xFFFFFFFA,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFDFDFB,
+0xFFFEFFFD,
+0xFFF8FCFD,
+0xFFFCFFFF,
+0xFFFDFDFF,
+0xFFFCFFFF,
+0xFFF5FEFF,
+0xFFB2C8D5,
+0xFF1C4559,
+0xFF275B73,
+0xFF285B76,
+0xFF295E7E,
+0xFF3C739A,
+0xFF36739F,
+0xFF3679A4,
+0xFF3378A2,
+0xFF3576A0,
+0xFF3877A0,
+0xFF3877A0,
+0xFF37769F,
+0xFF3778A0,
+0xFF397AA2,
+0xFF397AA2,
+0xFF3778A0,
+0xFF377AA4,
+0xFF377AA4,
+0xFF387BA5,
+0xFF387BA5,
+0xFF387BA5,
+0xFF397CA6,
+0xFF397CA7,
+0xFF397EA8,
+0xFF397EA8,
+0xFF397EA8,
+0xFF3A7FA9,
+0xFF3A7FA9,
+0xFF3980AC,
+0xFF3980AC,
+0xFF3A81AD,
+0xFF3A81AD,
+0xFF3982AD,
+0xFF3982AD,
+0xFF3A83B0,
+0xFF3A83B0,
+0xFF3983B0,
+0xFF3A84B1,
+0xFF3B85B2,
+0xFF3B85B2,
+0xFF3B85B2,
+0xFF3C86B3,
+0xFF3D87B4,
+0xFF3D87B4,
+0xFF3B88B6,
+0xFF3A87B5,
+0xFF3A87B5,
+0xFF3A87B5,
+0xFF3B87B8,
+0xFF3C88B9,
+0xFF3C8ABA,
+0xFF3C8ABA,
+0xFF3B89BA,
+0xFF3B89BA,
+0xFF3B89BA,
+0xFF3A8ABB,
+0xFF388ABA,
+0xFF398BBB,
+0xFF3A8CBC,
+0xFF3B8DBD,
+0xFF3C8DBC,
+0xFF3C8DBC,
+0xFF3C8DBC,
+0xFF3C8DBC,
+0xFF3F8DBD,
+0xFF3F8DBD,
+0xFF3F8DBB,
+0xFF3F8DBB,
+0xFF418EBC,
+0xFF428FBD,
+0xFF428FBD,
+0xFF4390BE,
+0xFF428EBF,
+0xFF428EBF,
+0xFF428FBD,
+0xFF458FBC,
+0xFF478EBA,
+0xFF478EBA,
+0xFF428FBB,
+0xFF3F90BD,
+0xFF4290BE,
+0xFF4D96BF,
+0xFF2D6B90,
+0xFF225373,
+0xFF20445A,
+0xFF9EB4C2,
+0xFFF9FFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFDFF,
+0xFFFFFEFF,
+0xFFFDFDFB,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFCFDFF,
+0xFFF5FFFF,
+0xFF597485,
+0xFF25516A,
+0xFF155070,
+0xFF4388B1,
+0xFF458FBE,
+0xFF3E87BA,
+0xFF3C8ABB,
+0xFF398DBC,
+0xFF398FBE,
+0xFF398BBB,
+0xFF398BBB,
+0xFF3A8ABB,
+0xFF3989BA,
+0xFF3989BA,
+0xFF3989BA,
+0xFF3B89B9,
+0xFF3B89B9,
+0xFF3987B7,
+0xFF3A88B8,
+0xFF3B88B6,
+0xFF3B88B6,
+0xFF3B88B6,
+0xFF3A87B5,
+0xFF3986B4,
+0xFF3986B4,
+0xFF3C84B6,
+0xFF3D87B6,
+0xFF3986B2,
+0xFF3685AE,
+0xFF3784B0,
+0xFF3784B0,
+0xFF3882B1,
+0xFF3981B1,
+0xFF3A81AF,
+0xFF3D80AB,
+0xFF4181A4,
+0xFF4B7E99,
+0xFF537382,
+0xFFF2FFFF,
+0xFFFAFEFF,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFDFBFC,
+0xFFFBFFFF,
+0xFFF9FFFD,
+0xFFFCFFFD,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFF2FFFF,
+0xFF72A1B5,
+0xFF65A1BD,
+0xFF6CA2BE,
+0xFF2A5B7B,
+0xFF316283,
+0xFF326082,
+0xFF336182,
+0xFF336182,
+0xFF346283,
+0xFF346283,
+0xFF326383,
+0xFF326383,
+0xFF336485,
+0xFF346586,
+0xFF346586,
+0xFF356687,
+0xFF35678A,
+0xFF35678A,
+0xFF35678A,
+0xFF36688B,
+0xFF37698C,
+0xFF36688B,
+0xFF356A8C,
+0xFF32688A,
+0xFF346A8C,
+0xFF37698C,
+0xFF3B698D,
+0xFF37678D,
+0xFF3B759A,
+0xFF69A8C7,
+0xFF629EB6,
+0xFF9DC8D9,
+0xFFF5FFFF,
+0xFFFFFDFF,
+0xFFFBFFFF,
+0xFFFAFFFF,
+0xFFFFFFFB,
+0xFFFFFDF8,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFEFFFF,
+0xFFFBFFFF,
+0xFFFCFFFF,
+0xFFFDFEFF,
+0xFFF9FAFF,
+0xFFFEFFFF,
+0xFFF5FFFF,
+0xFFBBD7E5,
+0xFF1F485C,
+0xFF2E5B72,
+0xFF295A78,
+0xFF2D6387,
+0xFF39749C,
+0xFF32739D,
+0xFF31749F,
+0xFF34759F,
+0xFF36759E,
+0xFF3877A0,
+0xFF3978A1,
+0xFF3778A0,
+0xFF36779F,
+0xFF3879A1,
+0xFF397AA2,
+0xFF3679A3,
+0xFF377AA4,
+0xFF377AA4,
+0xFF387BA5,
+0xFF387BA5,
+0xFF387BA5,
+0xFF397CA7,
+0xFF397CA7,
+0xFF397EA8,
+0xFF397EA8,
+0xFF3A7FA9,
+0xFF3A7FA9,
+0xFF3980AC,
+0xFF3980AC,
+0xFF3980AC,
+0xFF3980AC,
+0xFF3982AD,
+0xFF3982AD,
+0xFF3982AF,
+0xFF3982AF,
+0xFF3983B0,
+0xFF3983B0,
+0xFF3A84B1,
+0xFF3A84B1,
+0xFF3B85B2,
+0xFF3B85B2,
+0xFF3C86B3,
+0xFF3C86B3,
+0xFF3A87B5,
+0xFF3A87B5,
+0xFF3B88B6,
+0xFF3B88B6,
+0xFF3B87B8,
+0xFF3B87B8,
+0xFF3B89B9,
+0xFF3B89B9,
+0xFF3B89BA,
+0xFF3B89BA,
+0xFF3C8ABB,
+0xFF3C8ABB,
+0xFF3989BA,
+0xFF398BBB,
+0xFF3A8CBC,
+0xFF3A8CBC,
+0xFF3B8CBB,
+0xFF3B8CBB,
+0xFF3C8DBC,
+0xFF3C8DBC,
+0xFF3E8CBC,
+0xFF3E8CBC,
+0xFF3E8CBA,
+0xFF3F8DBB,
+0xFF408DBB,
+0xFF418EBC,
+0xFF418EBC,
+0xFF428EBF,
+0xFF418FC0,
+0xFF428EBF,
+0xFF428FBD,
+0xFF438DBA,
+0xFF458EBB,
+0xFF468FBC,
+0xFF4390BE,
+0xFF418FBD,
+0xFF4592BE,
+0xFF4A8FB8,
+0xFF1A5577,
+0xFF28546F,
+0xFF284557,
+0xFFF0FFFF,
+0xFFFBFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFCFAFB,
+0xFFFFFFFF,
+0xFFFDFFFC,
+0xFFFFFFFD,
+0xFFFBFFFF,
+0xFFE8FBFF,
+0xFF23465C,
+0xFF245671,
+0xFF29688B,
+0xFF408AB7,
+0xFF3E8CBD,
+0xFF3E8ABC,
+0xFF3E8ABC,
+0xFF3B8DBD,
+0xFF378BBA,
+0xFF398BBB,
+0xFF398BBB,
+0xFF3989BA,
+0xFF3989BA,
+0xFF3989BA,
+0xFF3989BA,
+0xFF3B89B9,
+0xFF3B89B9,
+0xFF3A88B8,
+0xFF3A88B8,
+0xFF3B88B6,
+0xFF3B88B6,
+0xFF3A87B5,
+0xFF3A87B5,
+0xFF3986B4,
+0xFF3985B6,
+0xFF3A81B5,
+0xFF3B85B6,
+0xFF3786AF,
+0xFF3486AE,
+0xFF3784B0,
+0xFF3983B2,
+0xFF3981B1,
+0xFF3B82B0,
+0xFF3A7FA9,
+0xFF3D7EA6,
+0xFF4382A3,
+0xFF427289,
+0xFFA1B7C5,
+0xFFF9FFFF,
+0xFFFBFDFC,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFD,
+0xFFFEFDFB,
+0xFFFBFFFF,
+0xFFFBFFFD,
+0xFFF8FDF9,
+0xFFFCFCFA,
+0xFFFEFCFF,
+0xFFFDFCFF,
+0xFFF8FFFF,
+0xFFC9E4ED,
+0xFF6197AF,
+0xFF6CACC8,
+0xFF52849F,
+0xFF2C5976,
+0xFF336182,
+0xFF316283,
+0xFF336182,
+0xFF336182,
+0xFF346283,
+0xFF346283,
+0xFF346283,
+0xFF356384,
+0xFF336485,
+0xFF346586,
+0xFF346586,
+0xFF356687,
+0xFF366788,
+0xFF366788,
+0xFF35678A,
+0xFF36688B,
+0xFF36688B,
+0xFF36688B,
+0xFF356A8C,
+0xFF32688A,
+0xFF33698B,
+0xFF356A8C,
+0xFF39668D,
+0xFF39698F,
+0xFF31698E,
+0xFF67A4C3,
+0xFF66A4BD,
+0xFF74A3B5,
+0xFFF2FFFF,
+0xFFFCFFFF,
+0xFFF9FFFF,
+0xFFFBFFFF,
+0xFFFFFFFD,
+0xFFFFFCF9,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFCFDFF,
+0xFFFDFEFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFF9FAFE,
+0xFFFCFFFF,
+0xFFF7FFFF,
+0xFFCCDFED,
+0xFF23495E,
+0xFF31607A,
+0xFF295C79,
+0xFF285E80,
+0xFF3D78A2,
+0xFF3978A3,
+0xFF37769F,
+0xFF36769C,
+0xFF37779D,
+0xFF39799F,
+0xFF3778A0,
+0xFF35769E,
+0xFF36779F,
+0xFF3A7BA3,
+0xFF3879A3,
+0xFF3879A3,
+0xFF377AA4,
+0xFF377AA4,
+0xFF377AA4,
+0xFF377AA4,
+0xFF387BA5,
+0xFF397CA6,
+0xFF397EA8,
+0xFF397EA8,
+0xFF397EA8,
+0xFF3A7FA9,
+0xFF3A7FA9,
+0xFF3B80AA,
+0xFF3980AC,
+0xFF3980AC,
+0xFF3980AC,
+0xFF3980AC,
+0xFF3982AD,
+0xFF3982AD,
+0xFF3982AF,
+0xFF3A83B0,
+0xFF3A83B0,
+0xFF3B84B1,
+0xFF3B85B2,
+0xFF3B85B2,
+0xFF3B85B2,
+0xFF3B85B2,
+0xFF3B85B4,
+0xFF3C86B5,
+0xFF3D87B6,
+0xFF3E88B7,
+0xFF3B87B8,
+0xFF3B87B8,
+0xFF3B87B8,
+0xFF3C88B9,
+0xFF3B89BA,
+0xFF3C8ABB,
+0xFF3C8ABB,
+0xFF3C8ABB,
+0xFF3A8ABB,
+0xFF3A8ABB,
+0xFF3B8CBB,
+0xFF3B8CBB,
+0xFF3B8CBB,
+0xFF3B8CBB,
+0xFF3B8CBB,
+0xFF3C8DBC,
+0xFF3C8DBC,
+0xFF3C8DBC,
+0xFF3C8DBC,
+0xFF3C8DBC,
+0xFF3E8CBC,
+0xFF3E8CBC,
+0xFF3F8DBD,
+0xFF3F8DBD,
+0xFF3E8EBF,
+0xFF418FBF,
+0xFF438DBC,
+0xFF438CB9,
+0xFF428CB9,
+0xFF4390BE,
+0xFF4390BE,
+0xFF418EBC,
+0xFF448DB8,
+0xFF3A7BA1,
+0xFF205775,
+0xFF244D63,
+0xFF748A98,
+0xFFF7FFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFCFB,
+0xFFFFFEFF,
+0xFFFEFEFE,
+0xFFFDFFFE,
+0xFFFCFEFD,
+0xFFF5FFFF,
+0xFF8FAABD,
+0xFF204A63,
+0xFF215877,
+0xFF3F80A6,
+0xFF3F8CBA,
+0xFF3989BC,
+0xFF3F8BBC,
+0xFF3D89BA,
+0xFF3D8EBD,
+0xFF388AB9,
+0xFF3A8ABB,
+0xFF3A8ABB,
+0xFF3B89B9,
+0xFF3B89B9,
+0xFF3A88B8,
+0xFF3A88B8,
+0xFF3B87B8,
+0xFF3B87B8,
+0xFF3B88B6,
+0xFF3B88B6,
+0xFF3B88B6,
+0xFF3A87B5,
+0xFF3986B4,
+0xFF3986B4,
+0xFF3885B3,
+0xFF3884B5,
+0xFF3980B4,
+0xFF3983B4,
+0xFF3486AE,
+0xFF3486AC,
+0xFF3784B2,
+0xFF3781B0,
+0xFF3881AE,
+0xFF3C81AB,
+0xFF3D81A8,
+0xFF3A799C,
+0xFF417A97,
+0xFF426B7F,
+0xFFE6F4FF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFDFCFA,
+0xFFFFFFFD,
+0xFFFCFFFF,
+0xFFFAFFFE,
+0xFFFCFEFB,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFCFFFF,
+0xFFF2FFFF,
+0xFF8BAFBD,
+0xFF6EA7C2,
+0xFF70AFCE,
+0xFF2F617C,
+0xFF36627D,
+0xFF315E7F,
+0xFF336182,
+0xFF336182,
+0xFF336182,
+0xFF346283,
+0xFF346283,
+0xFF346283,
+0xFF346283,
+0xFF336485,
+0xFF346586,
+0xFF336485,
+0xFF346586,
+0xFF356687,
+0xFF356687,
+0xFF346689,
+0xFF35678A,
+0xFF35678A,
+0xFF36688B,
+0xFF34698B,
+0xFF34698B,
+0xFF346A8C,
+0xFF346A8C,
+0xFF37678D,
+0xFF3A6A90,
+0xFF2E648A,
+0xFF5591B3,
+0xFF6BABC6,
+0xFF6699AE,
+0xFFDDF4FF,
+0xFFF6FEFF,
+0xFFF7FFFF,
+0xFFFBFFFF,
+0xFFFEFEFE,
+0xFFFFFEFD,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFDFEFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFCFCFC,
+0xFFFDFEFF,
+0xFFFCFFFF,
+0xFFF9FDFE,
+0xFFFEFFFF,
+0xFFFFFEFF,
+0xFFF8FFFF,
+0xFFD1EBFA,
+0xFF294F62,
+0xFF2F5F76,
+0xFF2D637F,
+0xFF2E648A,
+0xFF336D95,
+0xFF3B79A0,
+0xFF37779D,
+0xFF35759B,
+0xFF36769C,
+0xFF36779F,
+0xFF36779F,
+0xFF3778A0,
+0xFF3778A0,
+0xFF3879A3,
+0xFF3879A3,
+0xFF377AA4,
+0xFF377AA4,
+0xFF377AA4,
+0xFF377AA4,
+0xFF387BA5,
+0xFF387BA5,
+0xFF387DA7,
+0xFF387DA7,
+0xFF397EA8,
+0xFF397EA8,
+0xFF3A7FA9,
+0xFF3A7FA9,
+0xFF387FAB,
+0xFF3980AC,
+0xFF3980AC,
+0xFF3980AC,
+0xFF3881AC,
+0xFF3982AD,
+0xFF3982AF,
+0xFF3A83B0,
+0xFF3A83B0,
+0xFF3A83B0,
+0xFF3A84B1,
+0xFF3A84B1,
+0xFF3B85B2,
+0xFF3B85B2,
+0xFF3B85B4,
+0xFF3B85B4,
+0xFF3C86B5,
+0xFF3D87B6,
+0xFF3A86B7,
+0xFF3B87B8,
+0xFF3B87B8,
+0xFF3B87B8,
+0xFF3B89BA,
+0xFF3B89BA,
+0xFF3B89BA,
+0xFF3B89BA,
+0xFF3989BA,
+0xFF3A8ABB,
+0xFF3A8BBA,
+0xFF3A8BBA,
+0xFF3A8BBA,
+0xFF3A8BBA,
+0xFF3B8CBB,
+0xFF3C8DBC,
+0xFF3B8CBB,
+0xFF3B8CBB,
+0xFF3B8CBB,
+0xFF3B8CBB,
+0xFF3D8BBB,
+0xFF3E8CBC,
+0xFF3E8CBC,
+0xFF3C8DBC,
+0xFF3C8EBE,
+0xFF3D8EBD,
+0xFF428CBB,
+0xFF438DBA,
+0xFF418EBC,
+0xFF408EBC,
+0xFF408CBD,
+0xFF428CBB,
+0xFF4E93BD,
+0xFF266588,
+0xFF275A75,
+0xFF234659,
+0xFFD8E8F5,
+0xFFF9FEFF,
+0xFFFFFFFF,
+0xFFFEFDFB,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFCFB,
+0xFFFFFEFD,
+0xFFFFFFFF,
+0xFFFCFFFF,
+0xFFFBFFFF,
+0xFFEEFFFF,
+0xFF395D73,
+0xFF2D607F,
+0xFF225E82,
+0xFF478CB5,
+0xFF3F8DBD,
+0xFF388ABC,
+0xFF3E8ABB,
+0xFF3B88B6,
+0xFF3C8ABA,
+0xFF3A8BBA,
+0xFF3989BA,
+0xFF3989BA,
+0xFF3B89B9,
+0xFF3A88B8,
+0xFF3A88B8,
+0xFF3A88B8,
+0xFF3B87B8,
+0xFF3B87B8,
+0xFF3B88B6,
+0xFF3A87B5,
+0xFF3A87B5,
+0xFF3986B4,
+0xFF3986B4,
+0xFF3885B3,
+0xFF3885B3,
+0xFF3885B3,
+0xFF3A83B6,
+0xFF3882B3,
+0xFF3584AD,
+0xFF3685AC,
+0xFF3882AF,
+0xFF3880B0,
+0xFF3980AC,
+0xFF3C81AA,
+0xFF3E7EA2,
+0xFF3B7694,
+0xFF3D6F88,
+0xFF7091A2,
+0xFFF9FFFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFCFEFB,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFDFDFB,
+0xFFFFFFFF,
+0xFFFDFEFF,
+0xFFFCFDFF,
+0xFFFEFFFD,
+0xFFFFFFFD,
+0xFFFFFDFF,
+0xFFF7FEFF,
+0xFFDEF8FF,
+0xFF6E98AE,
+0xFF73ACC9,
+0xFF5B98B5,
+0xFF2A5977,
+0xFF345D7B,
+0xFF356080,
+0xFF325F80,
+0xFF326081,
+0xFF336182,
+0xFF346283,
+0xFF346283,
+0xFF346283,
+0xFF346283,
+0xFF356384,
+0xFF356384,
+0xFF336485,
+0xFF346586,
+0xFF346586,
+0xFF356687,
+0xFF346689,
+0xFF346689,
+0xFF35678A,
+0xFF35678A,
+0xFF35678C,
+0xFF34698B,
+0xFF356B8D,
+0xFF33698B,
+0xFF38688E,
+0xFF39698F,
+0xFF32688E,
+0xFF3C7799,
+0xFF75B2CE,
+0xFF6EA2B8,
+0xFFA3C2D6,
+0xFFF1FFFF,
+0xFFF6FFFF,
+0xFFFCFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFDFFFE,
+0xFFFAFEFD,
+0xFFFCFFFF,
+0xFFFEFFFF,
+0xFFFFFEFF,
+0xFFFCFBFF,
+0xFFF8FFFF,
+0xFFD8EEF9,
+0xFF2E576B,
+0xFF2E607B,
+0xFF326383,
+0xFF31658A,
+0xFF377398,
+0xFF36769C,
+0xFF37779D,
+0xFF36769C,
+0xFF37769F,
+0xFF3877A0,
+0xFF3778A0,
+0xFF36779F,
+0xFF3879A1,
+0xFF3879A1,
+0xFF377AA4,
+0xFF377AA4,
+0xFF377AA4,
+0xFF377AA4,
+0xFF387BA5,
+0xFF387BA5,
+0xFF397CA7,
+0xFF397CA7,
+0xFF397CA7,
+0xFF3A7DA8,
+0xFF397EA8,
+0xFF3A7FA9,
+0xFF3A7FA9,
+0xFF3A7FA9,
+0xFF3980AC,
+0xFF3980AC,
+0xFF3980AC,
+0xFF3A81AD,
+0xFF3982AF,
+0xFF3982AF,
+0xFF3A83B0,
+0xFF3A83B0,
+0xFF3983B0,
+0xFF3A84B1,
+0xFF3B85B2,
+0xFF3B85B2,
+0xFF3B85B4,
+0xFF3B85B4,
+0xFF3B85B4,
+0xFF3B85B4,
+0xFF3C86B5,
+0xFF3D87B6,
+0xFF3C88B9,
+0xFF3C88B9,
+0xFF3A88B8,
+0xFF3A88B8,
+0xFF3A88B8,
+0xFF3B89B9,
+0xFF3B89B9,
+0xFF3B89B9,
+0xFF3C8ABA,
+0xFF3C8ABA,
+0xFF398AB9,
+0xFF3A8BBA,
+0xFF3A8ABB,
+0xFF3B8BBC,
+0xFF3B8BBC,
+0xFF3B8BBC,
+0xFF3B8BBC,
+0xFF3B8BBC,
+0xFF3B8BBC,
+0xFF3B8BBC,
+0xFF3D8BBC,
+0xFF3B8BBC,
+0xFF3C8EBD,
+0xFF3C8DBC,
+0xFF3F8CBA,
+0xFF418EBC,
+0xFF408EBE,
+0xFF3C8DBC,
+0xFF3F8DBE,
+0xFF468EBE,
+0xFF4184AE,
+0xFF1D5878,
+0xFF2C5A71,
+0xFF486877,
+0xFFF3FFFF,
+0xFFFCFFFF,
+0xFFFDFDFD,
+0xFFFFFEFC,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFEFC,
+0xFFFFFFFF,
+0xFFFCFFFF,
+0xFFF1FEFF,
+0xFFBAD4E1,
+0xFF25516A,
+0xFF266183,
+0xFF2F729C,
+0xFF448EBB,
+0xFF3D8BBC,
+0xFF3A8ABB,
+0xFF3B89B9,
+0xFF3A88B6,
+0xFF3A86B7,
+0xFF3C8ABA,
+0xFF3B89B9,
+0xFF3B89B9,
+0xFF3B87B8,
+0xFF3B87B8,
+0xFF3B88B6,
+0xFF3B88B6,
+0xFF3C86B5,
+0xFF3C86B5,
+0xFF3C86B5,
+0xFF3C86B5,
+0xFF3B85B4,
+0xFF3B85B4,
+0xFF3885B1,
+0xFF3885B1,
+0xFF3885B1,
+0xFF3885B3,
+0xFF3B85B6,
+0xFF3781B0,
+0xFF3683AD,
+0xFF3785AC,
+0xFF3881AC,
+0xFF3980AC,
+0xFF3A81AD,
+0xFF3C80A7,
+0xFF377697,
+0xFF417791,
+0xFF3F6578,
+0xFFC0D6E3,
+0xFFFCFFFF,
+0xFFFFFCFF,
+0xFFFFFFFF,
+0xFFFDFFFE,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFD,
+0xFFFFFFFF,
+0xFFFDFCFF,
+0xFFFEFDFF,
+0xFFFEFFFF,
+0xFFFAFCFB,
+0xFFFDFDFD,
+0xFFF7FFFF,
+0xFFA5C5DC,
+0xFF6C9DBB,
+0xFF74ADCA,
+0xFF366F8C,
+0xFF32617F,
+0xFF305B7B,
+0xFF386181,
+0xFF325D7D,
+0xFF336081,
+0xFF336182,
+0xFF336182,
+0xFF346283,
+0xFF346283,
+0xFF346283,
+0xFF356384,
+0xFF356384,
+0xFF346586,
+0xFF346586,
+0xFF346586,
+0xFF356687,
+0xFF35678A,
+0xFF346689,
+0xFF35678A,
+0xFF36688B,
+0xFF35678C,
+0xFF326789,
+0xFF356B8D,
+0xFF316789,
+0xFF37698E,
+0xFF36678F,
+0xFF356C93,
+0xFF2B658A,
+0xFF67A2C0,
+0xFF76AAC2,
+0xFF759BB0,
+0xFFE8FFFF,
+0xFFF8FFFF,
+0xFFFBFCFE,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFDFCFA,
+0xFFFFFFFB,
+0xFFFFFFFD,
+0xFFFCFFFF,
+0xFFFBFFFF,
+0xFFF5F9FC,
+0xFFFFFDFF,
+0xFFFFFEFF,
+0xFFFEFCFD,
+0xFFF6FFFF,
+0xFFDDF9FF,
+0xFF345D73,
+0xFF315F79,
+0xFF2E6383,
+0xFF2D698D,
+0xFF327298,
+0xFF38789E,
+0xFF38789E,
+0xFF37769F,
+0xFF37769F,
+0xFF3778A0,
+0xFF3778A0,
+0xFF3879A1,
+0xFF3879A1,
+0xFF377AA4,
+0xFF377AA4,
+0xFF377AA4,
+0xFF377AA4,
+0xFF387BA5,
+0xFF387BA5,
+0xFF387BA6,
+0xFF397CA7,
+0xFF397CA7,
+0xFF397CA7,
+0xFF397EA8,
+0xFF397EA8,
+0xFF3A7FA9,
+0xFF3A7FA9,
+0xFF3980AC,
+0xFF3980AC,
+0xFF3980AC,
+0xFF3980AC,
+0xFF3982AF,
+0xFF3982AF,
+0xFF3A83B0,
+0xFF3A83B0,
+0xFF3882AF,
+0xFF3983B0,
+0xFF3B85B2,
+0xFF3B85B2,
+0xFF3B85B4,
+0xFF3B85B4,
+0xFF3A84B3,
+0xFF3A84B3,
+0xFF3B85B4,
+0xFF3D87B6,
+0xFF3C88B9,
+0xFF3B87B8,
+0xFF3987B7,
+0xFF3987B7,
+0xFF3A88B8,
+0xFF3B89B9,
+0xFF3A88B8,
+0xFF3B89B9,
+0xFF3B89B9,
+0xFF3B89B9,
+0xFF398AB9,
+0xFF398AB9,
+0xFF3A8ABB,
+0xFF3A8ABB,
+0xFF3A8ABB,
+0xFF3B8BBC,
+0xFF3B8BBC,
+0xFF3B8BBC,
+0xFF3B8BBC,
+0xFF3B8BBC,
+0xFF3D8BBC,
+0xFF3B8BBC,
+0xFF3C8EBD,
+0xFF3B8DBC,
+0xFF3D8BB9,
+0xFF3E8CBA,
+0xFF3D8EBD,
+0xFF3C8DBC,
+0xFF408EBF,
+0xFF478FBF,
+0xFF2E6F97,
+0xFF2A6180,
+0xFF275064,
+0xFFAAC5D0,
+0xFFF6FFFF,
+0xFFF8FCFF,
+0xFFFEFFFF,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFEFC,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFAFFFF,
+0xFFF1FFFF,
+0xFF5D7E91,
+0xFF2D5E7C,
+0xFF236387,
+0xFF3E87B4,
+0xFF3E8CBD,
+0xFF3A88B9,
+0xFF3A8ABB,
+0xFF398AB9,
+0xFF3D8BBB,
+0xFF3A86B7,
+0xFF3D89BA,
+0xFF3B87B8,
+0xFF3A88B8,
+0xFF3B87B8,
+0xFF3B87B8,
+0xFF3B88B6,
+0xFF3A87B5,
+0xFF3C86B5,
+0xFF3C86B5,
+0xFF3B85B4,
+0xFF3B85B4,
+0xFF3B85B4,
+0xFF3A84B3,
+0xFF3885B1,
+0xFF3885B1,
+0xFF3885B1,
+0xFF3885B1,
+0xFF3A84B3,
+0xFF3680AF,
+0xFF3883AD,
+0xFF3A83AC,
+0xFF3980AA,
+0xFF3C81AB,
+0xFF3D82AC,
+0xFF3B7CA2,
+0xFF347190,
+0xFF3D6F86,
+0xFF516E7E,
+0xFFF2FFFF,
+0xFFFEFFFF,
+0xFFFFFEFF,
+0xFFFEFEFE,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFCFFFD,
+0xFFFEFFFF,
+0xFFFFFEFF,
+0xFFFFFDFF,
+0xFFFDFDFF,
+0xFFFDFFFE,
+0xFFFFFFFF,
+0xFFF2FFFF,
+0xFF7299B6,
+0xFF6CA2C6,
+0xFF669DBB,
+0xFF245A76,
+0xFF306181,
+0xFF346182,
+0xFF365F7F,
+0xFF365F7F,
+0xFF336081,
+0xFF326081,
+0xFF336182,
+0xFF336182,
+0xFF336182,
+0xFF346283,
+0xFF346283,
+0xFF356384,
+0xFF346586,
+0xFF336485,
+0xFF346586,
+0xFF356687,
+0xFF36668A,
+0xFF356589,
+0xFF35678A,
+0xFF36688B,
+0xFF36688D,
+0xFF326789,
+0xFF346A8C,
+0xFF316789,
+0xFF386A8F,
+0xFF33678E,
+0xFF356C93,
+0xFF2C668B,
+0xFF49809F,
+0xFF73A6C1,
+0xFF6B99B0,
+0xFFB5D6E5,
+0xFFF8FFFF,
+0xFFFDFBFE,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFEFE,
+0xFFFFFEFF,
+0xFFFFFFFB,
+0xFFFFFFFB,
+0xFFFEFDFB,
+0xFFFEFFFF,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFEFD,
+0xFFFFFEFF,
+0xFFF9FFFF,
+0xFFE4FAFF,
+0xFF356279,
+0xFF2B6482,
+0xFF276689,
+0xFF2D6D93,
+0xFF34749A,
+0xFF37779D,
+0xFF37779D,
+0xFF37779D,
+0xFF3778A0,
+0xFF3879A1,
+0xFF3778A0,
+0xFF3879A1,
+0xFF3879A3,
+0xFF3879A3,
+0xFF3679A3,
+0xFF3679A3,
+0xFF377AA4,
+0xFF377AA4,
+0xFF387BA5,
+0xFF387BA5,
+0xFF397CA7,
+0xFF397CA7,
+0xFF387DA7,
+0xFF397EA8,
+0xFF397EA8,
+0xFF397EA8,
+0xFF3980AC,
+0xFF3980AC,
+0xFF3980AC,
+0xFF3980AC,
+0xFF3881AC,
+0xFF3982AD,
+0xFF3982AF,
+0xFF3982AF,
+0xFF3882AF,
+0xFF3983B0,
+0xFF3A84B1,
+0xFF3A84B1,
+0xFF3A84B3,
+0xFF3A84B3,
+0xFF3B85B4,
+0xFF3B85B4,
+0xFF3B85B4,
+0xFF3C86B5,
+0xFF3B88B6,
+0xFF3B88B6,
+0xFF3987B7,
+0xFF3987B7,
+0xFF3A88B8,
+0xFF3A88B8,
+0xFF3B87B8,
+0xFF3B87B8,
+0xFF3B89B9,
+0xFF3B89B9,
+0xFF398AB9,
+0xFF398AB9,
+0xFF3989BA,
+0xFF3989BA,
+0xFF3A8ABB,
+0xFF3A8ABB,
+0xFF3A8ABB,
+0xFF3B8BBC,
+0xFF3B8BBE,
+0xFF3B8BBE,
+0xFF3B8BBE,
+0xFF3B8BBC,
+0xFF3A8CBB,
+0xFF3B8DBC,
+0xFF3B8EBA,
+0xFF3A8BB8,
+0xFF3D8BBB,
+0xFF3F8DBE,
+0xFF3F8DBE,
+0xFF3F89B6,
+0xFF236389,
+0xFF2C5F7C,
+0xFF2B4E61,
+0xFFEEFFFF,
+0xFFF7FFFF,
+0xFFFBFFFF,
+0xFFFEFFFF,
+0xFFFCFCFC,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFEFEFE,
+0xFFFDFDFD,
+0xFFFFFFFF,
+0xFFF6FDFF,
+0xFFE4FBFF,
+0xFF2D536A,
+0xFF306786,
+0xFF2B6F96,
+0xFF408CBE,
+0xFF3989BE,
+0xFF3987B8,
+0xFF3B89B9,
+0xFF388ABA,
+0xFF3B8CBB,
+0xFF3C88B9,
+0xFF3E88B9,
+0xFF3B88B6,
+0xFF3B88B6,
+0xFF3B88B6,
+0xFF3B88B6,
+0xFF3D87B6,
+0xFF3C86B5,
+0xFF3C86B5,
+0xFF3B85B4,
+0xFF3B85B2,
+0xFF3B85B2,
+0xFF3B85B2,
+0xFF3A84B1,
+0xFF3A84B1,
+0xFF3A84B1,
+0xFF3784B0,
+0xFF3784B0,
+0xFF3983B0,
+0xFF3680AD,
+0xFF3A81AF,
+0xFF3A81AD,
+0xFF3A7FA8,
+0xFF3D81A8,
+0xFF3C7FA9,
+0xFF34759B,
+0xFF326F8B,
+0xFF336276,
+0xFF98AEB9,
+0xFFF9FFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFEFEFE,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFD,
+0xFFFDFDFD,
+0xFFFFFDFF,
+0xFFFFFDFF,
+0xFFFCFDFF,
+0xFFFBFFFF,
+0xFFF5FDFF,
+0xFFC6DCE9,
+0xFF6695B3,
+0xFF68A2C7,
+0xFF4A7F9F,
+0xFF2A5B7B,
+0xFF2C5D7E,
+0xFF325F80,
+0xFF37607E,
+0xFF37607E,
+0xFF325F7E,
+0xFF326081,
+0xFF336182,
+0xFF336182,
+0xFF336182,
+0xFF336182,
+0xFF346283,
+0xFF346283,
+0xFF336485,
+0xFF336485,
+0xFF336485,
+0xFF356687,
+0xFF356589,
+0xFF346488,
+0xFF346689,
+0xFF35678A,
+0xFF39698D,
+0xFF336588,
+0xFF346A8C,
+0xFF31698A,
+0xFF356B8F,
+0xFF32688E,
+0xFF346B92,
+0xFF366E93,
+0xFF33688A,
+0xFF6A9FBE,
+0xFF6EA4BE,
+0xFF6D98AB,
+0xFFEDFFFF,
+0xFFFBFFFF,
+0xFFFAFDFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFC,
+0xFFFFFFFB,
+0xFFFFFFFB,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFAFBFD,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFDFDFD,
+0xFFFFFEFD,
+0xFFFFFAFA,
+0xFFFFFEFF,
+0xFFF7FFFF,
+0xFFE4FFFF,
+0xFF3C6C83,
+0xFF2F6886,
+0xFF2D698D,
+0xFF2E6C91,
+0xFF34749A,
+0xFF37769F,
+0xFF36779F,
+0xFF36779F,
+0xFF36779F,
+0xFF3778A0,
+0xFF3778A0,
+0xFF3879A1,
+0xFF3879A1,
+0xFF3879A1,
+0xFF3679A3,
+0xFF3679A4,
+0xFF377AA5,
+0xFF387BA5,
+0xFF387BA5,
+0xFF387BA6,
+0xFF397CA7,
+0xFF387DA7,
+0xFF397EA8,
+0xFF397EA8,
+0xFF397EA8,
+0xFF387FAB,
+0xFF387FAB,
+0xFF387FAB,
+0xFF387FAB,
+0xFF3980AC,
+0xFF3881AC,
+0xFF3980AE,
+0xFF3982AF,
+0xFF3982AF,
+0xFF3983B0,
+0xFF3A83B0,
+0xFF3983B0,
+0xFF3A84B3,
+0xFF3A84B3,
+0xFF3B85B4,
+0xFF3C86B5,
+0xFF3B85B4,
+0xFF3B85B4,
+0xFF3986B4,
+0xFF3A87B5,
+0xFF3A88B8,
+0xFF3A88B8,
+0xFF3A88B8,
+0xFF3A88B8,
+0xFF3A86B7,
+0xFF3B87B8,
+0xFF3B89B9,
+0xFF3B89B9,
+0xFF3B89B9,
+0xFF398AB9,
+0xFF3B89BA,
+0xFF3989BA,
+0xFF3B89BA,
+0xFF3989BA,
+0xFF3C8ABB,
+0xFF3A8ABB,
+0xFF3D8ABE,
+0xFF3B8BBE,
+0xFF3D8ABE,
+0xFF3B8BBC,
+0xFF388ABA,
+0xFF3C8EBD,
+0xFF3C8FBB,
+0xFF398AB9,
+0xFF3D8BBC,
+0xFF408EBF,
+0xFF3C88B9,
+0xFF377EAA,
+0xFF256388,
+0xFF2D5C76,
+0xFF7C97A8,
+0xFFF4FFFF,
+0xFFF7FFFF,
+0xFFFCFFFF,
+0xFFFDFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFEFEFF,
+0xFFFFFFFF,
+0xFFFBF9FA,
+0xFFF8FFFF,
+0xFF86A5B7,
+0xFF30627D,
+0xFF28688C,
+0xFF3A83AE,
+0xFF3B88BC,
+0xFF3A8ABF,
+0xFF3C89BD,
+0xFF3D89BB,
+0xFF3A88B8,
+0xFF3A88B8,
+0xFF3A86B7,
+0xFF3A87B5,
+0xFF3A87B5,
+0xFF3B88B6,
+0xFF3B88B6,
+0xFF3B88B6,
+0xFF3D87B6,
+0xFF3C86B5,
+0xFF3B85B4,
+0xFF3B85B4,
+0xFF3B85B2,
+0xFF3B85B2,
+0xFF3B85B2,
+0xFF3B85B2,
+0xFF3A84B1,
+0xFF3983B0,
+0xFF3683AF,
+0xFF3683AF,
+0xFF3983B0,
+0xFF3881AC,
+0xFF3D81AE,
+0xFF3C81AB,
+0xFF397EA7,
+0xFF3C7FA9,
+0xFF3B7CA4,
+0xFF306F92,
+0xFF366C86,
+0xFF335A6B,
+0xFFF2FFFF,
+0xFFFDFEFF,
+0xFFFCFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFDFE,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFCFE,
+0xFFFFFEFF,
+0xFFF7FFFF,
+0xFFF4FFFF,
+0xFFF0FFFF,
+0xFF81A4B8,
+0xFF629BB6,
+0xFF69A8C9,
+0xFF29597F,
+0xFF305C81,
+0xFF346083,
+0xFF315C7E,
+0xFF365F7B,
+0xFF37607C,
+0xFF33607D,
+0xFF33607F,
+0xFF326081,
+0xFF326081,
+0xFF336182,
+0xFF336182,
+0xFF346283,
+0xFF346283,
+0xFF336485,
+0xFF336485,
+0xFF336387,
+0xFF346488,
+0xFF356589,
+0xFF356589,
+0xFF346689,
+0xFF36668A,
+0xFF39658A,
+0xFF38668A,
+0xFF33698B,
+0xFF316C8C,
+0xFF316C8C,
+0xFF336B8E,
+0xFF35698E,
+0xFF35698E,
+0xFF34688D,
+0xFF477FA2,
+0xFF67A3C5,
+0xFF679DB9,
+0xFF98BDD0,
+0xFFEEFFFF,
+0xFFF7FEFF,
+0xFFFFFFFF,
+0xFFFBFFFE,
+0xFFFCFFFF,
+0xFFFEFDFF,
+0xFFFEFCFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFBFF,
+0xFFFFFDFF,
+0xFFFFFEFD,
+0xFFFFFFFD,
+0xFFFCFFFF,
+0xFFFBFFFF,
+0xFFFCFFFF,
+0xFFFEFFFF,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFCFFFF,
+0xFFF7FFFF,
+0xFFECFFFF,
+0xFF406D84,
+0xFF346B8A,
+0xFF316B90,
+0xFF2C6A91,
+0xFF3677A1,
+0xFF33739F,
+0xFF3677A1,
+0xFF36779F,
+0xFF34759D,
+0xFF38799F,
+0xFF3A7BA1,
+0xFF397AA0,
+0xFF37789E,
+0xFF3879A3,
+0xFF387BA8,
+0xFF377BA8,
+0xFF377CA6,
+0xFF377CA5,
+0xFF377CA6,
+0xFF377CA6,
+0xFF387DA7,
+0xFF387DA7,
+0xFF397DAA,
+0xFF397DAA,
+0xFF3A7EAB,
+0xFF3A7EAB,
+0xFF3A7EAB,
+0xFF3B7FAC,
+0xFF3B7FAC,
+0xFF3A81AD,
+0xFF3C80AD,
+0xFF3A81AD,
+0xFF3980AC,
+0xFF3982AD,
+0xFF3A81AD,
+0xFF3982AD,
+0xFF3A83B0,
+0xFF3A83B0,
+0xFF3A84B1,
+0xFF3A84B1,
+0xFF3A84B1,
+0xFF3B85B2,
+0xFF3986B2,
+0xFF3A87B3,
+0xFF3A87B5,
+0xFF3B88B6,
+0xFF3A88B6,
+0xFF3A88B6,
+0xFF3B88B6,
+0xFF3B88B6,
+0xFF3B87B8,
+0xFF3B87B8,
+0xFF3C88B9,
+0xFF3B89B9,
+0xFF3D89BA,
+0xFF3C8ABA,
+0xFF3C88B9,
+0xFF3B89B9,
+0xFF3C88BA,
+0xFF3C8ABB,
+0xFF3D89BB,
+0xFF3C8ABB,
+0xFF3D89BB,
+0xFF3C8ABB,
+0xFF398BBD,
+0xFF3A8CBC,
+0xFF3B8CBB,
+0xFF3F8DBD,
+0xFF3989BA,
+0xFF408EBE,
+0xFF438CB9,
+0xFF2A6B93,
+0xFF2D6586,
+0xFF2B556D,
+0xFFD8ECF7,
+0xFFF8FFFF,
+0xFFF9FDFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFDFEFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFDFF,
+0xFFFFFDFF,
+0xFFFFFEFF,
+0xFFFEFFFF,
+0xFFFCFFFF,
+0xFFFCFFFD,
+0xFFFFFFFB,
+0xFFFFFEFB,
+0xFFFFFDFD,
+0xFFFFFDFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFDFF,
+0xFFFFFDFF,
+0xFFFFFFFD,
+0xFFF4FFFF,
+0xFF3C697E,
+0xFF317194,
+0xFF26739F,
+0xFF3A8ABB,
+0xFF3C8ABB,
+0xFF3D89BB,
+0xFF3D89BD,
+0xFF3E87BA,
+0xFF3E86B6,
+0xFF3D87B4,
+0xFF3788B3,
+0xFF3588B4,
+0xFF3B89B7,
+0xFF3B88B6,
+0xFF3B88B6,
+0xFF3A87B5,
+0xFF3B85B4,
+0xFF3C84B4,
+0xFF3B84B1,
+0xFF3B84B1,
+0xFF3C85B2,
+0xFF3C85B2,
+0xFF3B84B1,
+0xFF3A83B0,
+0xFF3983B0,
+0xFF3882AF,
+0xFF3683AF,
+0xFF3882AF,
+0xFF3881AE,
+0xFF4084B1,
+0xFF3A7FA8,
+0xFF3C81AA,
+0xFF397DAA,
+0xFF3B7EAB,
+0xFF3E7CA5,
+0xFF2F6587,
+0xFF37617A,
+0xFF6B8795,
+0xFFF7FFFF,
+0xFFFFFFFD,
+0xFFFBFFFF,
+0xFFFCFFFF,
+0xFFFDFBFE,
+0xFFFFFDFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFEFEFE,
+0xFFF9FFFF,
+0xFFF2FFFF,
+0xFFD4F3FF,
+0xFF618FA7,
+0xFF64A0BC,
+0xFF508BAB,
+0xFF2B597D,
+0xFF335A81,
+0xFF345E84,
+0xFF315C7E,
+0xFF37607C,
+0xFF345E77,
+0xFF34607D,
+0xFF33607F,
+0xFF326081,
+0xFF336182,
+0xFF336182,
+0xFF346283,
+0xFF346283,
+0xFF346283,
+0xFF336485,
+0xFF336485,
+0xFF336387,
+0xFF346488,
+0xFF356589,
+0xFF356589,
+0xFF346689,
+0xFF36668A,
+0xFF396588,
+0xFF386688,
+0xFF33698B,
+0xFF306B8B,
+0xFF316C8C,
+0xFF336B8C,
+0xFF37698C,
+0xFF37698C,
+0xFF34688F,
+0xFF30678E,
+0xFF609EC3,
+0xFF5D9AB9,
+0xFF5D8FA6,
+0xFFD4F5FF,
+0xFFF3FFFF,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFCFEFD,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFDFF,
+0xFFFFFDFF,
+0xFFFFFDFF,
+0xFFFFFCFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFCFFFD,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFEFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFF7FFFF,
+0xFFE9FFFF,
+0xFF46738A,
+0xFF356887,
+0xFF356F94,
+0xFF306F98,
+0xFF30739E,
+0xFF3376A0,
+0xFF3376A0,
+0xFF3879A1,
+0xFF37789E,
+0xFF38789E,
+0xFF38789E,
+0xFF3778A0,
+0xFF397AA4,
+0xFF367AA7,
+0xFF3579A6,
+0xFF367BA5,
+0xFF377CA5,
+0xFF377CA6,
+0xFF377CA6,
+0xFF377CA6,
+0xFF387DA7,
+0xFF387CA9,
+0xFF397DAA,
+0xFF397DAA,
+0xFF397DAA,
+0xFF3A7EAB,
+0xFF3A7EAB,
+0xFF3B7FAC,
+0xFF3B7FAC,
+0xFF3B7FAC,
+0xFF3B7FAC,
+0xFF3980AC,
+0xFF3980AC,
+0xFF3A81AD,
+0xFF3A81AD,
+0xFF3A83B0,
+0xFF3A83B0,
+0xFF3983B0,
+0xFF3983B0,
+0xFF3A84B1,
+0xFF3A84B1,
+0xFF3885B1,
+0xFF3986B2,
+0xFF3986B4,
+0xFF3986B4,
+0xFF3987B5,
+0xFF3987B5,
+0xFF3A87B5,
+0xFF3A87B5,
+0xFF3A86B7,
+0xFF3B87B8,
+0xFF3B87B8,
+0xFF3C88B9,
+0xFF3C88B9,
+0xFF3C88B9,
+0xFF3C88B9,
+0xFF3C88B9,
+0xFF3C88BA,
+0xFF3C88BA,
+0xFF3D89BB,
+0xFF3D89BB,
+0xFF3C88BA,
+0xFF3B89BA,
+0xFF3A8ABD,
+0xFF398BBB,
+0xFF3D8BBB,
+0xFF3E8CBC,
+0xFF3888B9,
+0xFF3C8ABA,
+0xFF3F86B2,
+0xFF29678C,
+0xFF2E6180,
+0xFF527589,
+0xFFF4FFFF,
+0xFFFCFFFF,
+0xFFFEFFFF,
+0xFFFEFEFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFEFFFD,
+0xFFFFFFFF,
+0xFFFFFDFF,
+0xFFFFFCFF,
+0xFFFFFEFF,
+0xFFFCFFFF,
+0xFFFBFFFF,
+0xFFFCFFFB,
+0xFFFFFFFA,
+0xFFFFFEFA,
+0xFFFFFCFD,
+0xFFFFFDFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFBFF,
+0xFFFFFEFF,
+0xFFF9FFFF,
+0xFFBBD4DB,
+0xFF2D637D,
+0xFF287299,
+0xFF2D7EAD,
+0xFF3B8EC0,
+0xFF3A88B8,
+0xFF3B87B8,
+0xFF3B87B9,
+0xFF3D86B9,
+0xFF3F85B6,
+0xFF3E87B4,
+0xFF3788B3,
+0xFF3689B3,
+0xFF3987B5,
+0xFF3A87B5,
+0xFF3A87B5,
+0xFF3986B4,
+0xFF3B85B4,
+0xFF3A84B3,
+0xFF3A84B1,
+0xFF3A84B1,
+0xFF3A84B1,
+0xFF3983B0,
+0xFF3983B0,
+0xFF3A83B0,
+0xFF3982AF,
+0xFF3982AF,
+0xFF3982AF,
+0xFF3982AF,
+0xFF3C80AF,
+0xFF3478A5,
+0xFF3E83AA,
+0xFF3C81A8,
+0xFF3D81AE,
+0xFF3C7FAC,
+0xFF316B93,
+0xFF316283,
+0xFF34576D,
+0xFFC5D9E4,
+0xFFFCFFFF,
+0xFFFEFFFA,
+0xFFF9FFFF,
+0xFFFBFFFF,
+0xFFFFFCFF,
+0xFFFFFDFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFDFCFA,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFEFDFF,
+0xFFFDFDFF,
+0xFFF3FFFF,
+0xFF95BED4,
+0xFF5C93B1,
+0xFF679DBF,
+0xFF37698C,
+0xFF2E5B7C,
+0xFF315C7C,
+0xFF325E81,
+0xFF305D7E,
+0xFF38617D,
+0xFF325B77,
+0xFF34607D,
+0xFF33607F,
+0xFF32617F,
+0xFF336280,
+0xFF336182,
+0xFF346283,
+0xFF346283,
+0xFF346283,
+0xFF336485,
+0xFF336485,
+0xFF336485,
+0xFF346586,
+0xFF336586,
+0xFF346687,
+0xFF346689,
+0xFF356589,
+0xFF39658A,
+0xFF38668A,
+0xFF33698D,
+0xFF326A8D,
+0xFF326A8B,
+0xFF346A8C,
+0xFF37698A,
+0xFF38698A,
+0xFF386A8F,
+0xFF31698E,
+0xFF39779C,
+0xFF6AA6C8,
+0xFF5E94B0,
+0xFF729BB1,
+0xFFEAFFFF,
+0xFFF3FFFF,
+0xFFFEFFFF,
+0xFFFFFCFD,
+0xFFFFFFFD,
+0xFFFFFDFE,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFCFEFD,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFCFFFF,
+0xFFF5FFFF,
+0xFFEBFFFF,
+0xFF567F95,
+0xFF316685,
+0xFF336F93,
+0xFF31729A,
+0xFF357AA3,
+0xFF31769F,
+0xFF3578A2,
+0xFF37769F,
+0xFF37759C,
+0xFF37769F,
+0xFF3879A3,
+0xFF357AA4,
+0xFF357AA4,
+0xFF3479A3,
+0xFF367BA4,
+0xFF377BA2,
+0xFF377AA4,
+0xFF387BA5,
+0xFF387BA6,
+0xFF397CA7,
+0xFF387DA7,
+0xFF387DA7,
+0xFF397DAA,
+0xFF397DAA,
+0xFF397DAA,
+0xFF397DAA,
+0xFF3A7EAB,
+0xFF3A7EAB,
+0xFF3B80AA,
+0xFF3B80AA,
+0xFF3980AC,
+0xFF3980AC,
+0xFF3A81AD,
+0xFF3A81AD,
+0xFF3982AD,
+0xFF3A83AE,
+0xFF3A83B0,
+0xFF3A83B0,
+0xFF3A84B1,
+0xFF3A84B1,
+0xFF3885B1,
+0xFF3885B1,
+0xFF3986B2,
+0xFF3986B2,
+0xFF3986B4,
+0xFF3986B4,
+0xFF3986B4,
+0xFF3A87B5,
+0xFF3A87B5,
+0xFF3A87B5,
+0xFF3B87B8,
+0xFF3B87B8,
+0xFF3B87B8,
+0xFF3B87B8,
+0xFF3C88B9,
+0xFF3C88B9,
+0xFF3C88B9,
+0xFF3C88B9,
+0xFF3B89BA,
+0xFF3B89BA,
+0xFF3B89BA,
+0xFF3B89BA,
+0xFF3C8ABA,
+0xFF398AB9,
+0xFF3889B8,
+0xFF3B8CBB,
+0xFF3D8BBB,
+0xFF3E8BB9,
+0xFF3077A3,
+0xFF2B678C,
+0xFF2E5C76,
+0xFFAECBDB,
+0xFFF5FFFF,
+0xFFF9FDFE,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFEFCFF,
+0xFFFEFCFD,
+0xFFFEFFFD,
+0xFFFFFFFD,
+0xFFFFFDFF,
+0xFFFFFDFF,
+0xFFFFFDFF,
+0xFFFEFFFF,
+0xFFFCFFFD,
+0xFFFCFFFB,
+0xFFFFFFFB,
+0xFFFFFEFB,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFF9FFFF,
+0xFFEEFFFF,
+0xFF5E8898,
+0xFF367392,
+0xFF2F7AA2,
+0xFF3A88B8,
+0xFF3688B8,
+0xFF3788B7,
+0xFF3987B5,
+0xFF3A86B7,
+0xFF3D87B8,
+0xFF3F85B6,
+0xFF3E86B6,
+0xFF3A88B6,
+0xFF3987B5,
+0xFF3B85B6,
+0xFF3B85B6,
+0xFF3986B4,
+0xFF3885B3,
+0xFF3785B3,
+0xFF3586B3,
+0xFF3586B1,
+0xFF3586B1,
+0xFF3485B0,
+0xFF3685B0,
+0xFF3683AD,
+0xFF3883AD,
+0xFF3A81AD,
+0xFF3C80AD,
+0xFF3C80AD,
+0xFF3D80AD,
+0xFF4082B2,
+0xFF3A7EAB,
+0xFF3B80A9,
+0xFF377CA5,
+0xFF3B80AA,
+0xFF3C7DA7,
+0xFF275E85,
+0xFF346180,
+0xFF405D6F,
+0xFFF4FFFF,
+0xFFF9FFFF,
+0xFFFEFFFD,
+0xFFFBFFFF,
+0xFFFCFFFF,
+0xFFFEFCFD,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFEFFFA,
+0xFFFFFFFD,
+0xFFFEFDFF,
+0xFFFFFEFF,
+0xFFFEFDFF,
+0xFFF1FFFF,
+0xFF5A8DA8,
+0xFF5A99BC,
+0xFF5D8FB4,
+0xFF2C587B,
+0xFF345D7B,
+0xFF305C79,
+0xFF315E7F,
+0xFF315E7F,
+0xFF37607E,
+0xFF345D79,
+0xFF345F7F,
+0xFF33607F,
+0xFF32617F,
+0xFF32617F,
+0xFF336182,
+0xFF336182,
+0xFF346283,
+0xFF346283,
+0xFF326384,
+0xFF336485,
+0xFF336485,
+0xFF346586,
+0xFF336586,
+0xFF336586,
+0xFF346689,
+0xFF356589,
+0xFF376589,
+0xFF36668A,
+0xFF33678C,
+0xFF326A8D,
+0xFF326A8B,
+0xFF356A8A,
+0xFF38698A,
+0xFF3A688A,
+0xFF3B6D90,
+0xFF33698D,
+0xFF296589,
+0xFF4D89AD,
+0xFF67A0BE,
+0xFF5F8EAA,
+0xFF8BAFC7,
+0xFFEEFFFF,
+0xFFF9FCFF,
+0xFFFFFEFF,
+0xFFFEFFFF,
+0xFFFDFFFE,
+0xFFFFFDFF,
+0xFFFFFEFF,
+0xFFFEFFFD,
+0xFFFBFFFC,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFCFFFF,
+0xFFF1FEFF,
+0xFFEBFFFF,
+0xFF648A9F,
+0xFF386B88,
+0xFF347396,
+0xFF2E7299,
+0xFF357AA4,
+0xFF32759F,
+0xFF3675A0,
+0xFF38769F,
+0xFF3978A1,
+0xFF3879A3,
+0xFF3578A2,
+0xFF3479A2,
+0xFF367BA2,
+0xFF377BA2,
+0xFF377BA2,
+0xFF377AA4,
+0xFF377AA4,
+0xFF387BA6,
+0xFF387BA6,
+0xFF387DA7,
+0xFF387DA7,
+0xFF387CA9,
+0xFF387CA9,
+0xFF397DAA,
+0xFF397DAA,
+0xFF3A7EAB,
+0xFF3A7EAB,
+0xFF3A7FA9,
+0xFF3A7FA9,
+0xFF3980AC,
+0xFF3980AC,
+0xFF3980AC,
+0xFF3980AC,
+0xFF3982AD,
+0xFF3982AD,
+0xFF3982AF,
+0xFF3A83B0,
+0xFF3A84B1,
+0xFF3A84B1,
+0xFF3885B1,
+0xFF3986B2,
+0xFF3986B2,
+0xFF3986B2,
+0xFF3986B4,
+0xFF3986B4,
+0xFF3986B4,
+0xFF3986B4,
+0xFF3A87B5,
+0xFF3A87B5,
+0xFF3A86B7,
+0xFF3B87B8,
+0xFF3B87B8,
+0xFF3B87B8,
+0xFF3B87B8,
+0xFF3C88B9,
+0xFF3C88B9,
+0xFF3C88B9,
+0xFF3B89BA,
+0xFF3A88B9,
+0xFF3A88B9,
+0xFF3A88B8,
+0xFF3C89B7,
+0xFF3C8AB8,
+0xFF3888B9,
+0xFF3989BA,
+0xFF3D8AB8,
+0xFF4089B6,
+0xFF286D97,
+0xFF336E90,
+0xFF375D72,
+0xFFEEFFFF,
+0xFFF6FFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFCFD,
+0xFFFFFEFD,
+0xFFFFFFFB,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFDFF,
+0xFFFFFEFF,
+0xFFFEFFFF,
+0xFFFCFFFD,
+0xFFFCFFFB,
+0xFFFFFFFB,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFCFDFF,
+0xFFF2FFFF,
+0xFFD5F8FF,
+0xFF2F6581,
+0xFF3B7CA2,
+0xFF327BA6,
+0xFF3D8AB8,
+0xFF3A88B8,
+0xFF3889B6,
+0xFF3A88B6,
+0xFF3D87B6,
+0xFF3E86B6,
+0xFF3D85B7,
+0xFF3D85B7,
+0xFF3C86B5,
+0xFF3986B4,
+0xFF3B85B6,
+0xFF3B85B6,
+0xFF3A84B3,
+0xFF3885B3,
+0xFF3785B3,
+0xFF3586B3,
+0xFF3485B0,
+0xFF3485B0,
+0xFF3485B0,
+0xFF3685B0,
+0xFF3683AD,
+0xFF3883AD,
+0xFF3A81AD,
+0xFF3C80AD,
+0xFF3C81AB,
+0xFF3D80AB,
+0xFF397BAB,
+0xFF3C80AD,
+0xFF3A81AB,
+0xFF3981A9,
+0xFF3B80A7,
+0xFF2D6D91,
+0xFF2B6185,
+0xFF29526E,
+0xFF9BB1BF,
+0xFFF8FFFF,
+0xFFFAFFFF,
+0xFFFCFFFD,
+0xFFFAFEFD,
+0xFFFEFFFD,
+0xFFFDFDFD,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFD,
+0xFFFEFFFB,
+0xFFFDFFFC,
+0xFFFFFEFF,
+0xFFFEFEFF,
+0xFFF8FBFF,
+0xFFBDD6EC,
+0xFF4C88AA,
+0xFF569AC1,
+0xFF44719A,
+0xFF30567A,
+0xFF365D7A,
+0xFF305C75,
+0xFF31607E,
+0xFF305E7F,
+0xFF325D7D,
+0xFF376080,
+0xFF335E7E,
+0xFF325F7E,
+0xFF33607F,
+0xFF33607F,
+0xFF33607F,
+0xFF346180,
+0xFF336182,
+0xFF336182,
+0xFF346283,
+0xFF356384,
+0xFF336484,
+0xFF346585,
+0xFF346586,
+0xFF346586,
+0xFF346687,
+0xFF346687,
+0xFF356589,
+0xFF346689,
+0xFF32668B,
+0xFF32688C,
+0xFF33698B,
+0xFF37698A,
+0xFF3A688A,
+0xFF3B698A,
+0xFF356687,
+0xFF3C7193,
+0xFF2C668B,
+0xFF2E6A8F,
+0xFF5894B8,
+0xFF6199BA,
+0xFF598AAA,
+0xFFA1C4DA,
+0xFFF5FFFF,
+0xFFFCFFFF,
+0xFFF4FBFF,
+0xFFF7FEFF,
+0xFFFFFFFD,
+0xFFFFFEF9,
+0xFFFFFFFA,
+0xFFFEFDF9,
+0xFFFEFFFD,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFCFFFF,
+0xFFFBFFFF,
+0xFFF1FFFF,
+0xFF6D93A6,
+0xFF316886,
+0xFF3A7BA3,
+0xFF3279A5,
+0xFF3676A2,
+0xFF3776A1,
+0xFF3776A1,
+0xFF3877A2,
+0xFF3778A0,
+0xFF37789E,
+0xFF38799F,
+0xFF397B9E,
+0xFF397AA2,
+0xFF397AA2,
+0xFF397AA2,
+0xFF397AA2,
+0xFF377AA4,
+0xFF387BA5,
+0xFF387BA6,
+0xFF387BA6,
+0xFF397CA7,
+0xFF397CA7,
+0xFF397EA8,
+0xFF397EA8,
+0xFF397EA8,
+0xFF3A7FA9,
+0xFF3A7FA9,
+0xFF3A7FA9,
+0xFF387FAB,
+0xFF3980AC,
+0xFF3980AC,
+0xFF3980AC,
+0xFF3980AC,
+0xFF3A81AD,
+0xFF3982AD,
+0xFF3982AD,
+0xFF3983B0,
+0xFF3983B0,
+0xFF3A84B1,
+0xFF3A84B1,
+0xFF3B85B2,
+0xFF3B85B2,
+0xFF3A87B3,
+0xFF3A87B3,
+0xFF3986B4,
+0xFF3986B4,
+0xFF3986B4,
+0xFF3A87B5,
+0xFF3A87B5,
+0xFF3A87B5,
+0xFF3B88B6,
+0xFF3B88B6,
+0xFF3B87B8,
+0xFF3B87B8,
+0xFF3B87B8,
+0xFF3B87B8,
+0xFF3A88B8,
+0xFF3A88B8,
+0xFF3A88B8,
+0xFF3B87B8,
+0xFF3D87B4,
+0xFF3E8BB9,
+0xFF3A8ABB,
+0xFF3888B9,
+0xFF3B88B6,
+0xFF357CA8,
+0xFF2E719B,
+0xFF316686,
+0xFF8AA7B7,
+0xFFF3FFFF,
+0xFFFBFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFDFC,
+0xFFFFFEFB,
+0xFFFFFFFB,
+0xFFFFFFFB,
+0xFFFFFEFD,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFEFFFB,
+0xFFFEFFFB,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFCFFFF,
+0xFFFBFFFF,
+0xFFFCFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFF0FFFF,
+0xFF83B2D0,
+0xFF36779F,
+0xFF3578A5,
+0xFF3980AE,
+0xFF4087B5,
+0xFF3E87B4,
+0xFF3A88B6,
+0xFF3A88B6,
+0xFF3D87B4,
+0xFF3D85B5,
+0xFF3D85B7,
+0xFF3C83B7,
+0xFF3C84B6,
+0xFF3B83B3,
+0xFF3B85B4,
+0xFF3B85B4,
+0xFF3B85B4,
+0xFF3A84B3,
+0xFF3983B2,
+0xFF3983B2,
+0xFF3983B0,
+0xFF3983B0,
+0xFF3984AE,
+0xFF3984AE,
+0xFF3982AD,
+0xFF3982AD,
+0xFF3982AB,
+0xFF3982AB,
+0xFF3881AA,
+0xFF387FA9,
+0xFF3B82B0,
+0xFF337AA8,
+0xFF347FA9,
+0xFF367FA8,
+0xFF3C82A6,
+0xFF205F80,
+0xFF2D607F,
+0xFF23475D,
+0xFFF2FFFF,
+0xFFFAFEFF,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFCFEFB,
+0xFFFDFFFA,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFD,
+0xFFFCFFFB,
+0xFFFBFFFC,
+0xFFFFFEFF,
+0xFFFBFDFF,
+0xFFF0FFFF,
+0xFF7097B6,
+0xFF5195BA,
+0xFF5499C2,
+0xFF2D5A81,
+0xFF35597D,
+0xFF355C79,
+0xFF305C75,
+0xFF31607C,
+0xFF305F7D,
+0xFF315C7E,
+0xFF345F81,
+0xFF335E7E,
+0xFF325F7E,
+0xFF325F7E,
+0xFF33607F,
+0xFF33607F,
+0xFF33607F,
+0xFF336182,
+0xFF336182,
+0xFF346283,
+0xFF346283,
+0xFF336484,
+0xFF346585,
+0xFF336485,
+0xFF346586,
+0xFF346586,
+0xFF346687,
+0xFF346687,
+0xFF346689,
+0xFF326789,
+0xFF33678C,
+0xFF34698B,
+0xFF36688B,
+0xFF3A688A,
+0xFF3B698B,
+0xFF38698A,
+0xFF346689,
+0xFF387095,
+0xFF326E93,
+0xFF2D6B90,
+0xFF5B99BE,
+0xFF5490B4,
+0xFF598AA8,
+0xFFAFCCDE,
+0xFFEAFCFF,
+0xFFF5FFFF,
+0xFFF8FFFF,
+0xFFFEFFFD,
+0xFFFFFEF7,
+0xFFFFFDFA,
+0xFFFFFEFB,
+0xFFFFFFFD,
+0xFFFEFFFF,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFCFEFD,
+0xFFFFFEFA,
+0xFFFBFFFF,
+0xFFECFFFF,
+0xFF759EB2,
+0xFF326A8B,
+0xFF34759D,
+0xFF3A7AA6,
+0xFF3679A4,
+0xFF3477A2,
+0xFF3576A0,
+0xFF37779D,
+0xFF39799D,
+0xFF3A799C,
+0xFF38789B,
+0xFF38799F,
+0xFF3879A1,
+0xFF3879A1,
+0xFF397AA2,
+0xFF377AA4,
+0xFF377AA4,
+0xFF387BA6,
+0xFF387BA6,
+0xFF397CA7,
+0xFF397CA7,
+0xFF387DA7,
+0xFF397EA8,
+0xFF397EA8,
+0xFF397EA8,
+0xFF3A7FA9,
+0xFF3A7FA9,
+0xFF387FAB,
+0xFF387FAB,
+0xFF387FAB,
+0xFF3980AC,
+0xFF3980AC,
+0xFF3980AC,
+0xFF3982AD,
+0xFF3982AD,
+0xFF3982AF,
+0xFF3882AF,
+0xFF3882AF,
+0xFF3983B0,
+0xFF3A84B1,
+0xFF3A84B1,
+0xFF3986B2,
+0xFF3986B2,
+0xFF3986B4,
+0xFF3986B4,
+0xFF3986B4,
+0xFF3986B4,
+0xFF3A87B5,
+0xFF3A87B5,
+0xFF3A87B5,
+0xFF3A87B5,
+0xFF3A86B7,
+0xFF3A86B7,
+0xFF3A86B7,
+0xFF3B87B8,
+0xFF3A88B8,
+0xFF3A88B8,
+0xFF3A88B8,
+0xFF3B88B6,
+0xFF3D87B4,
+0xFF3B88B4,
+0xFF3888B9,
+0xFF3A8ABB,
+0xFF3C88B9,
+0xFF2B729E,
+0xFF35749D,
+0xFF2D5C78,
+0xFFE1F7FF,
+0xFFF7FFFF,
+0xFFFCFFFF,
+0xFFFDFFFE,
+0xFFFBFCFE,
+0xFFFFFFFF,
+0xFFFFFEFB,
+0xFFFFFCF8,
+0xFFFFFFFB,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFB,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFCFFFF,
+0xFFFBFFFF,
+0xFFFBFFFF,
+0xFFFCFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFBFFFF,
+0xFFEDFFFF,
+0xFF3D749B,
+0xFF3B83B5,
+0xFF367CAD,
+0xFF4488B9,
+0xFF4588B5,
+0xFF3B82AE,
+0xFF3986B4,
+0xFF3886B4,
+0xFF3B85B2,
+0xFF3C85B2,
+0xFF3C83B7,
+0xFF3C83B7,
+0xFF3C84B4,
+0xFF3B83B3,
+0xFF3B85B4,
+0xFF3B85B4,
+0xFF3A84B3,
+0xFF3A84B3,
+0xFF3A82B2,
+0xFF3A82B2,
+0xFF3A81AF,
+0xFF3A81AF,
+0xFF3B82AE,
+0xFF3A81AD,
+0xFF3980AC,
+0xFF3980AC,
+0xFF3980AC,
+0xFF3980AA,
+0xFF3780AB,
+0xFF367FAA,
+0xFF3680AD,
+0xFF3882B1,
+0xFF3380AC,
+0xFF3B86AE,
+0xFF30799A,
+0xFF175773,
+0xFF13425C,
+0xFF557284,
+0xFFF8FFFF,
+0xFFFFFFFF,
+0xFFFBFFFF,
+0xFFFCFFFF,
+0xFFFEFFFD,
+0xFFFEFFFA,
+0xFFFEFFFB,
+0xFFFBFDF8,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFCFFFD,
+0xFFFDFFFC,
+0xFFFFFEFF,
+0xFFF8FFFF,
+0xFFC8EFFF,
+0xFF4681A9,
+0xFF4C94BC,
+0xFF3C80A7,
+0xFF27577B,
+0xFF345B7C,
+0xFF335C7A,
+0xFF325E79,
+0xFF315F79,
+0xFF305D7A,
+0xFF315D80,
+0xFF325D80,
+0xFF335E80,
+0xFF335E7E,
+0xFF335E7E,
+0xFF345F7F,
+0xFF33607F,
+0xFF33607F,
+0xFF346180,
+0xFF346180,
+0xFF336182,
+0xFF346283,
+0xFF356384,
+0xFF356384,
+0xFF356384,
+0xFF336484,
+0xFF346585,
+0xFF356686,
+0xFF346786,
+0xFF346687,
+0xFF346689,
+0xFF35678A,
+0xFF35678C,
+0xFF36688B,
+0xFF38688C,
+0xFF38698A,
+0xFF366788,
+0xFF396B8E,
+0xFF32688C,
+0xFF2D678C,
+0xFF306E95,
+0xFF307096,
+0xFF5899C1,
+0xFF5191B5,
+0xFF4C85A3,
+0xFFA3CDE3,
+0xFFEFFFFF,
+0xFFFCFFFF,
+0xFFFDFDFD,
+0xFFFFFEFD,
+0xFFFFFDFB,
+0xFFFFFCFD,
+0xFFFFFDFF,
+0xFFFEFFFF,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFCFEFD,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFF9FDFE,
+0xFFFBFFFF,
+0xFFF1FFFF,
+0xFF83A7BD,
+0xFF3A6F91,
+0xFF3578A3,
+0xFF337CA9,
+0xFF347BA5,
+0xFF34789F,
+0xFF36769A,
+0xFF39789B,
+0xFF3C789C,
+0xFF39789B,
+0xFF39799F,
+0xFF38799F,
+0xFF3879A1,
+0xFF3879A1,
+0xFF397AA2,
+0xFF397AA2,
+0xFF397AA4,
+0xFF397AA4,
+0xFF387BA5,
+0xFF387BA5,
+0xFF397CA7,
+0xFF397CA7,
+0xFF387DA7,
+0xFF397EA8,
+0xFF397EA8,
+0xFF397EA8,
+0xFF3A7FA9,
+0xFF3A7FA9,
+0xFF387FAB,
+0xFF387FAB,
+0xFF3980AC,
+0xFF3980AC,
+0xFF3980AC,
+0xFF3881AC,
+0xFF3881AC,
+0xFF3881AC,
+0xFF3982AF,
+0xFF3982AF,
+0xFF3983B0,
+0xFF3983B0,
+0xFF3983B0,
+0xFF3983B0,
+0xFF3885B1,
+0xFF3885B1,
+0xFF3986B2,
+0xFF3986B2,
+0xFF3986B4,
+0xFF3986B4,
+0xFF3986B4,
+0xFF3A87B5,
+0xFF3986B4,
+0xFF3A87B5,
+0xFF3A87B5,
+0xFF3A87B5,
+0xFF3B87B8,
+0xFF3B87B8,
+0xFF3B87B8,
+0xFF3B88B6,
+0xFF3D87B4,
+0xFF3A87B3,
+0xFF3785B5,
+0xFF3C8ABB,
+0xFF3886B6,
+0xFF2E75A1,
+0xFF336D92,
+0xFF6189A2,
+0xFFEFFFFF,
+0xFFFCFFFF,
+0xFFFDFFFE,
+0xFFFEFFFF,
+0xFFFDFEFF,
+0xFFFFFFFF,
+0xFFFFFEFB,
+0xFFFFFDFA,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFB,
+0xFFFFFFFB,
+0xFFFFFFFB,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFCFFFF,
+0xFFFBFFFF,
+0xFFFBFFFF,
+0xFFFEFFFF,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFF3FDFF,
+0xFFBAD8F0,
+0xFF3776A1,
+0xFF3784B8,
+0xFF3C83B7,
+0xFF3D83B4,
+0xFF4386B3,
+0xFF4186B0,
+0xFF3986B2,
+0xFF3886B4,
+0xFF3B85B2,
+0xFF3B85B2,
+0xFF3985B7,
+0xFF3985B7,
+0xFF3B85B4,
+0xFF3B85B2,
+0xFF3A84B1,
+0xFF3A84B1,
+0xFF3983B0,
+0xFF3983B0,
+0xFF3A83B0,
+0xFF3982AF,
+0xFF3A81AF,
+0xFF3A81AF,
+0xFF3C80AF,
+0xFF3B7FAE,
+0xFF3A7EAD,
+0xFF3A7EAD,
+0xFF3B7FAE,
+0xFF3B7FAC,
+0xFF3A7EAD,
+0xFF367FAC,
+0xFF3280B0,
+0xFF3788B7,
+0xFF2A7BA8,
+0xFF25749B,
+0xFF05506F,
+0xFF04425B,
+0xFF0E394C,
+0xFFC2DAE6,
+0xFFF9FDFF,
+0xFFFFFFFD,
+0xFFFCFEFD,
+0xFFFAFEFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFEFFFB,
+0xFFFEFFFB,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFEFFFD,
+0xFFFCFEFD,
+0xFFFFFFFF,
+0xFFECFEFF,
+0xFF6EAACF,
+0xFF2A78A6,
+0xFF3D88B0,
+0xFF25678A,
+0xFF2C6181,
+0xFF305D7C,
+0xFF305D7E,
+0xFF325F7E,
+0xFF2E5C76,
+0xFF2F5D77,
+0xFF336183,
+0xFF305C81,
+0xFF336081,
+0xFF345F7F,
+0xFF345F7F,
+0xFF345F7F,
+0xFF33607F,
+0xFF346180,
+0xFF346180,
+0xFF346180,
+0xFF336182,
+0xFF346283,
+0xFF356384,
+0xFF356384,
+0xFF356384,
+0xFF356384,
+0xFF346585,
+0xFF356686,
+0xFF366787,
+0xFF356887,
+0xFF356788,
+0xFF35678A,
+0xFF35678C,
+0xFF35678C,
+0xFF36688D,
+0xFF36688B,
+0xFF35678A,
+0xFF36688B,
+0xFF386D8F,
+0xFF366E91,
+0xFF326E93,
+0xFF2C6C92,
+0xFF33779E,
+0xFF5098BE,
+0xFF4D95BB,
+0xFF45809E,
+0xFFA0C0CF,
+0xFFF2FFFF,
+0xFFFBFFFF,
+0xFFFFFEFF,
+0xFFFFFDFF,
+0xFFFFFDFF,
+0xFFFFFDFF,
+0xFFFFFEFF,
+0xFFFCFFFF,
+0xFFFCFFFD,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFEFFFD,
+0xFFFEFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFAFEFF,
+0xFFFCFFFF,
+0xFFFDFEFF,
+0xFFFFFEFF,
+0xFFFAFEFF,
+0xFFF0FFFF,
+0xFF8BAFC7,
+0xFF346E93,
+0xFF347BA5,
+0xFF3881AA,
+0xFF357DA5,
+0xFF34759B,
+0xFF37759A,
+0xFF39779C,
+0xFF3A789D,
+0xFF39799F,
+0xFF38799F,
+0xFF3879A1,
+0xFF3879A1,
+0xFF3879A1,
+0xFF397AA2,
+0xFF397AA4,
+0xFF397AA4,
+0xFF387BA5,
+0xFF387BA5,
+0xFF387BA6,
+0xFF387BA6,
+0xFF387DA7,
+0xFF387DA7,
+0xFF387DA7,
+0xFF397EA8,
+0xFF3A7FA9,
+0xFF3A7FA9,
+0xFF387FAB,
+0xFF387FAB,
+0xFF3980AC,
+0xFF3980AC,
+0xFF3980AC,
+0xFF3980AC,
+0xFF3881AC,
+0xFF3982AD,
+0xFF3982AF,
+0xFF3982AF,
+0xFF3982AF,
+0xFF3882AF,
+0xFF3983B0,
+0xFF3983B0,
+0xFF3A84B1,
+0xFF3885B1,
+0xFF3885B1,
+0xFF3885B1,
+0xFF3885B3,
+0xFF3986B4,
+0xFF3986B4,
+0xFF3986B4,
+0xFF3986B4,
+0xFF3986B4,
+0xFF3A87B5,
+0xFF3A87B5,
+0xFF3A86B7,
+0xFF3B87B8,
+0xFF3B87B8,
+0xFF3B88B6,
+0xFF3986B2,
+0xFF3D8AB6,
+0xFF3B88B6,
+0xFF3C88B9,
+0xFF2E7CAD,
+0xFF3478A5,
+0xFF316686,
+0xFFB6D7EA,
+0xFFF7FFFF,
+0xFFFEFEFC,
+0xFFFDFFFE,
+0xFFFDFEFF,
+0xFFFEFFFF,
+0xFFFDFDFD,
+0xFFFFFEFB,
+0xFFFFFDFA,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFB,
+0xFFFFFFFB,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFEFD,
+0xFFFCFFFF,
+0xFFF0FFFF,
+0xFF668FAB,
+0xFF4084B1,
+0xFF3787BC,
+0xFF3A86B8,
+0xFF3C84B4,
+0xFF3E83AD,
+0xFF3E85AF,
+0xFF3986B2,
+0xFF3887B2,
+0xFF3986B2,
+0xFF3986B2,
+0xFF3886B7,
+0xFF3886B6,
+0xFF3885B1,
+0xFF3885AF,
+0xFF3983B0,
+0xFF3983B0,
+0xFF3882AF,
+0xFF3982AF,
+0xFF3982AF,
+0xFF3A81AF,
+0xFF3C80AF,
+0xFF3C80AF,
+0xFF3C80AF,
+0xFF3B7FB0,
+0xFF387EAF,
+0xFF387EAF,
+0xFF3880B0,
+0xFF3781B0,
+0xFF3582B0,
+0xFF3182B1,
+0xFF2579A8,
+0xFF156B9A,
+0xFF176B99,
+0xFF14668C,
+0xFF004764,
+0xFF064459,
+0xFF224757,
+0xFFF2FFFF,
+0xFFFEFFFF,
+0xFFFFFBFA,
+0xFFFEFFFF,
+0xFFFCFFFF,
+0xFFFEFEFF,
+0xFFFFFEFF,
+0xFFFDFDFB,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFDFEFF,
+0xFFF9FFFF,
+0xFFE6FFFF,
+0xFF1B6C97,
+0xFF1E7EB0,
+0xFF29749B,
+0xFF094867,
+0xFF17506D,
+0xFF205370,
+0xFF2A587A,
+0xFF305E80,
+0xFF31607C,
+0xFF31607C,
+0xFF2E5F80,
+0xFF2D5E7F,
+0xFF325F80,
+0xFF325F7E,
+0xFF325F80,
+0xFF325F80,
+0xFF336081,
+0xFF336081,
+0xFF336081,
+0xFF336081,
+0xFF356283,
+0xFF356283,
+0xFF346283,
+0xFF346283,
+0xFF346283,
+0xFF356384,
+0xFF366486,
+0xFF346585,
+0xFF346585,
+0xFF346585,
+0xFF356687,
+0xFF346689,
+0xFF35678C,
+0xFF33678C,
+0xFF34688D,
+0xFF34688D,
+0xFF35698E,
+0xFF356A8C,
+0xFF386A8D,
+0xFF356A8C,
+0xFF336B8E,
+0xFF306C91,
+0xFF2E6F95,
+0xFF2D7299,
+0xFF4C96BD,
+0xFF4C90B5,
+0xFF48819F,
+0xFF91B7CE,
+0xFFF1FFFF,
+0xFFFCFFFF,
+0xFFFBFFFF,
+0xFFFAFDFF,
+0xFFFFFDFF,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFFFFFB,
+0xFFFBFBF9,
+0xFFFEFFFD,
+0xFFFEFFFD,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFCFFFF,
+0xFFF1FFFF,
+0xFF8EB6CF,
+0xFF387395,
+0xFF3A81AB,
+0xFF3680AD,
+0xFF397EA7,
+0xFF34759D,
+0xFF3879A1,
+0xFF3778A0,
+0xFF3778A0,
+0xFF36779F,
+0xFF36779F,
+0xFF3B7CA4,
+0xFF3879A1,
+0xFF397AA2,
+0xFF3879A1,
+0xFF397AA2,
+0xFF397AA4,
+0xFF3A7BA5,
+0xFF387BA5,
+0xFF387BA5,
+0xFF397CA7,
+0xFF397CA7,
+0xFF387DA7,
+0xFF387DA7,
+0xFF397EA8,
+0xFF397EA8,
+0xFF3A7FA9,
+0xFF3B80AA,
+0xFF3B80AA,
+0xFF3B80AA,
+0xFF3980AC,
+0xFF387FAB,
+0xFF3980AC,
+0xFF3980AC,
+0xFF3980AC,
+0xFF3881AC,
+0xFF3982AD,
+0xFF3982AD,
+0xFF3982AD,
+0xFF3883AD,
+0xFF3983B0,
+0xFF3983B0,
+0xFF3A84B1,
+0xFF3A84B1,
+0xFF3B85B2,
+0xFF3B85B2,
+0xFF3B85B2,
+0xFF3C86B3,
+0xFF3885B3,
+0xFF3885B3,
+0xFF3885B3,
+0xFF3986B4,
+0xFF3986B4,
+0xFF3986B4,
+0xFF3986B4,
+0xFF3A87B5,
+0xFF3C89B7,
+0xFF3885B3,
+0xFF3C86B3,
+0xFF3E88B7,
+0xFF2E7BAF,
+0xFF3477A4,
+0xFF3B6782,
+0xFFEDFFFF,
+0xFFFBFFFF,
+0xFFFFFFFD,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFEFFFF,
+0xFFFCFFFF,
+0xFFFEFFFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFEFD,
+0xFFFFFEFD,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFCFCFE,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFEFE,
+0xFFFEFCFD,
+0xFFFFFEFD,
+0xFFF8FFFF,
+0xFFD6F5FF,
+0xFF457A9C,
+0xFF3D86B1,
+0xFF3B8DBC,
+0xFF3586B5,
+0xFF3786B1,
+0xFF3F8AB4,
+0xFF3883AB,
+0xFF3887B0,
+0xFF3586B1,
+0xFF3786B1,
+0xFF3684B2,
+0xFF3785B5,
+0xFF3785B3,
+0xFF3786AF,
+0xFF3786AD,
+0xFF3683AD,
+0xFF3984AE,
+0xFF3A83AE,
+0xFF3A81AD,
+0xFF3C80AF,
+0xFF3D81B0,
+0xFF3E80B2,
+0xFF3D7FB1,
+0xFF3A7EAF,
+0xFF3880B2,
+0xFF3682B3,
+0xFF3384B3,
+0xFF2C83B0,
+0xFF217CA8,
+0xFF14739F,
+0xFF0D6E9B,
+0xFF096999,
+0xFF11709E,
+0xFF166F9B,
+0xFF085C80,
+0xFF004C66,
+0xFF013C4E,
+0xFF8DABB5,
+0xFFF7FFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFF9FEFF,
+0xFFF1FFFF,
+0xFF91C4D9,
+0xFF1675A1,
+0xFF1A83B3,
+0xFF156185,
+0xFF114E6A,
+0xFF114D67,
+0xFF144D68,
+0xFF194B6C,
+0xFF1D4E6F,
+0xFF225373,
+0xFF275876,
+0xFF2C5E7F,
+0xFF2F6182,
+0xFF2F5D7E,
+0xFF315F80,
+0xFF336081,
+0xFF336182,
+0xFF346182,
+0xFF336182,
+0xFF346182,
+0xFF336182,
+0xFF336081,
+0xFF336182,
+0xFF336182,
+0xFF346283,
+0xFF346283,
+0xFF346283,
+0xFF346284,
+0xFF346284,
+0xFF366787,
+0xFF366787,
+0xFF366787,
+0xFF356788,
+0xFF36688B,
+0xFF33678C,
+0xFF32688E,
+0xFF32688E,
+0xFF34688F,
+0xFF35698E,
+0xFF37698A,
+0xFF356A8A,
+0xFF346A8C,
+0xFF336B8E,
+0xFF316D92,
+0xFF2F6F95,
+0xFF2F729C,
+0xFF4D92BC,
+0xFF478CB5,
+0xFF457FA4,
+0xFF8EB0CB,
+0xFFEFFFFF,
+0xFFF1FFFF,
+0xFFF8FFFF,
+0xFFF9FDFF,
+0xFFFFFFFF,
+0xFFFEFAF9,
+0xFFFCFBF9,
+0xFFFFFFFB,
+0xFFFCFEFB,
+0xFFFCFEFD,
+0xFFFEFEFE,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFF9FFFF,
+0xFFEDFFFF,
+0xFF9DC7DF,
+0xFF316B90,
+0xFF3F84AE,
+0xFF3F86B2,
+0xFF3980AC,
+0xFF2B6F9C,
+0xFF367BA5,
+0xFF377AA4,
+0xFF34759D,
+0xFF397AA2,
+0xFF36779F,
+0xFF3B7CA4,
+0xFF35769E,
+0xFF3A7BA3,
+0xFF3879A1,
+0xFF397AA4,
+0xFF397AA4,
+0xFF387BA5,
+0xFF387BA5,
+0xFF397CA7,
+0xFF397CA7,
+0xFF387DA7,
+0xFF387DA7,
+0xFF397EA8,
+0xFF397EA8,
+0xFF397EA8,
+0xFF3A7FA9,
+0xFF3A7FA9,
+0xFF3A7FA9,
+0xFF387FAB,
+0xFF387FAB,
+0xFF3980AC,
+0xFF3980AC,
+0xFF3980AC,
+0xFF3980AC,
+0xFF3982AD,
+0xFF3982AD,
+0xFF3982AD,
+0xFF3982AD,
+0xFF3A83B0,
+0xFF3983B0,
+0xFF3983B0,
+0xFF3983B0,
+0xFF3A84B1,
+0xFF3A84B1,
+0xFF3A84B1,
+0xFF3B85B2,
+0xFF3885B3,
+0xFF3885B3,
+0xFF3885B3,
+0xFF3986B4,
+0xFF3986B4,
+0xFF3986B4,
+0xFF3986B4,
+0xFF3986B4,
+0xFF3785B5,
+0xFF3C89B7,
+0xFF3B84AF,
+0xFF367FAC,
+0xFF347DB0,
+0xFF32719C,
+0xFF94B8CE,
+0xFFF0FFFF,
+0xFFFCFFFF,
+0xFFFFFFFD,
+0xFFFEFFFF,
+0xFFFCFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFCFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFD,
+0xFFFFFEFD,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFEFEFE,
+0xFFFFFDFE,
+0xFFFEFCFD,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFBFBFB,
+0xFFF3FFFF,
+0xFF8EB7D3,
+0xFF4583AA,
+0xFF458EB7,
+0xFF3889B4,
+0xFF3586B3,
+0xFF3485B0,
+0xFF3885AF,
+0xFF3D88B2,
+0xFF3986B0,
+0xFF3887B2,
+0xFF3986B4,
+0xFF3985B6,
+0xFF3A84B5,
+0xFF3784B2,
+0xFF3483AC,
+0xFF3482A9,
+0xFF3A85AF,
+0xFF3A83AE,
+0xFF3881AC,
+0xFF3780AD,
+0xFF3780AD,
+0xFF3880B0,
+0xFF3882B1,
+0xFF3581B2,
+0xFF3785B5,
+0xFF2E80B0,
+0xFF2179A7,
+0xFF1672A1,
+0xFF0E6F9C,
+0xFF086F9A,
+0xFF056F99,
+0xFF046F9B,
+0xFF0972A1,
+0xFF0D6F9C,
+0xFF18759E,
+0xFF00496B,
+0xFF014B64,
+0xFF0B4050,
+0xFFE9FFFF,
+0xFFF7FFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFDFF,
+0xFFF7FFFF,
+0xFFE3FFFF,
+0xFF3A7D97,
+0xFF0E739F,
+0xFF147BA8,
+0xFF045070,
+0xFF114F68,
+0xFF15536C,
+0xFF14506A,
+0xFF164B6B,
+0xFF184A6B,
+0xFF194B6E,
+0xFF1A4F6F,
+0xFF1C5170,
+0xFF1E5372,
+0xFF2E5F7F,
+0xFF2F6081,
+0xFF315F81,
+0xFF2F6081,
+0xFF305E80,
+0xFF2E5F80,
+0xFF315F81,
+0xFF306182,
+0xFF356385,
+0xFF336485,
+0xFF326384,
+0xFF326384,
+0xFF326384,
+0xFF336485,
+0xFF346586,
+0xFF356687,
+0xFF336484,
+0xFF336484,
+0xFF346585,
+0xFF346687,
+0xFF35678A,
+0xFF33678C,
+0xFF32688E,
+0xFF31698E,
+0xFF33698F,
+0xFF34688D,
+0xFF366889,
+0xFF376A89,
+0xFF356A8A,
+0xFF366B8B,
+0xFF346C8F,
+0xFF326C91,
+0xFF316B93,
+0xFF33709C,
+0xFF468DBB,
+0xFF438AB8,
+0xFF3E7FA9,
+0xFF76A9C8,
+0xFFEBFFFF,
+0xFFF2FFFF,
+0xFFF8FFFF,
+0xFFF9FFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFDFDFB,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFD,
+0xFFFFFEFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFEFFFF,
+0xFFFBFFFF,
+0xFFF8FFFF,
+0xFFF0FFFF,
+0xFFADD1E9,
+0xFF3F7398,
+0xFF3C80AF,
+0xFF3D89BB,
+0xFF3F89B8,
+0xFF2A739E,
+0xFF2E739C,
+0xFF3A7EA5,
+0xFF3579A0,
+0xFF3579A0,
+0xFF36779F,
+0xFF3C7DA5,
+0xFF36759E,
+0xFF3A79A2,
+0xFF397AA2,
+0xFF397AA2,
+0xFF397AA4,
+0xFF3A7BA5,
+0xFF387BA5,
+0xFF387BA5,
+0xFF387DA7,
+0xFF387DA7,
+0xFF387DA7,
+0xFF387DA7,
+0xFF397EA8,
+0xFF397EA8,
+0xFF397EA8,
+0xFF397EA8,
+0xFF397EA8,
+0xFF397EA8,
+0xFF3B7FAC,
+0xFF3B7FAC,
+0xFF3980AC,
+0xFF3980AC,
+0xFF3A81AD,
+0xFF3A81AD,
+0xFF3A81AD,
+0xFF3982AD,
+0xFF3982AD,
+0xFF3982AD,
+0xFF3982AD,
+0xFF3A83AE,
+0xFF3A83B0,
+0xFF3A83B0,
+0xFF3983B0,
+0xFF3983B0,
+0xFF3A84B1,
+0xFF3A84B1,
+0xFF3A84B1,
+0xFF3A84B1,
+0xFF3B85B4,
+0xFF3B85B4,
+0xFF3B85B4,
+0xFF3986B4,
+0xFF3684B4,
+0xFF3A86B7,
+0xFF3B84AF,
+0xFF3A7EAB,
+0xFF3980AE,
+0xFF376F94,
+0xFFDEF9FF,
+0xFFF6FFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFCFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFEFEFE,
+0xFFFFFEFF,
+0xFFFFFEFD,
+0xFFFFFCFB,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFBFFFF,
+0xFFEDFFFF,
+0xFF588AAB,
+0xFF4C8FB9,
+0xFF4890B8,
+0xFF3A85AD,
+0xFF3786B1,
+0xFF3886B4,
+0xFF3582AE,
+0xFF3984AE,
+0xFF3B84AF,
+0xFF3B84B1,
+0xFF3A84B5,
+0xFF3A82B4,
+0xFF3D80B4,
+0xFF3B81B2,
+0xFF3B84AF,
+0xFF3B84AF,
+0xFF387FAD,
+0xFF387FAD,
+0xFF3882AF,
+0xFF3885B3,
+0xFF3588B4,
+0xFF3087B4,
+0xFF2681AD,
+0xFF1D7CA8,
+0xFF0F729C,
+0xFF0A719C,
+0xFF06709A,
+0xFF046F9B,
+0xFF05709C,
+0xFF07729E,
+0xFF0875A0,
+0xFF0874A2,
+0xFF0773A1,
+0xFF086F9A,
+0xFF07658B,
+0xFF00516F,
+0xFF05475F,
+0xFF4F7D8A,
+0xFFF2FFFF,
+0xFFFDFEFF,
+0xFFFEFFFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFF1FFFF,
+0xFFB6EAFF,
+0xFF186987,
+0xFF13769F,
+0xFF0C6C96,
+0xFF085171,
+0xFF14526B,
+0xFF125069,
+0xFF14506C,
+0xFF164F6D,
+0xFF174D6F,
+0xFF174D71,
+0xFF174D6F,
+0xFF164D6B,
+0xFF164D6B,
+0xFF124767,
+0xFF194B6C,
+0xFF215374,
+0xFF295B7C,
+0xFF2D5F80,
+0xFF306283,
+0xFF326485,
+0xFF336586,
+0xFF2F6182,
+0xFF306283,
+0xFF316384,
+0xFF316384,
+0xFF326485,
+0xFF326485,
+0xFF336586,
+0xFF336586,
+0xFF366788,
+0xFF366787,
+0xFF356686,
+0xFF346786,
+0xFF326787,
+0xFF326789,
+0xFF32688E,
+0xFF32688E,
+0xFF33698F,
+0xFF34688D,
+0xFF356A8A,
+0xFF376A89,
+0xFF386B8A,
+0xFF366B8B,
+0xFF366B8D,
+0xFF366A91,
+0xFF396D95,
+0xFF2E6490,
+0xFF2C6E9E,
+0xFF448EBF,
+0xFF3A88B8,
+0xFF3B80A7,
+0xFF76A3B8,
+0xFFEAFFFF,
+0xFFF2FFFF,
+0xFFF8FFFF,
+0xFFFCFDFF,
+0xFFFBFAFF,
+0xFFFFFFFF,
+0xFFFEFEFE,
+0xFFFDFBFC,
+0xFFFCFBF9,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFDFD,
+0xFFFFFDFD,
+0xFFFFFEFB,
+0xFFFFFFFB,
+0xFFFFFFFD,
+0xFFFEFFFD,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFDFFFE,
+0xFFF9FFFF,
+0xFFEEFFFF,
+0xFFB3D6F2,
+0xFF38729A,
+0xFF3D84B2,
+0xFF3E87B4,
+0xFF3F88B3,
+0xFF3277A0,
+0xFF34789F,
+0xFF377BA2,
+0xFF34789F,
+0xFF3879A1,
+0xFF3778A0,
+0xFF3978A1,
+0xFF3978A1,
+0xFF3879A1,
+0xFF397AA2,
+0xFF397AA4,
+0xFF397AA4,
+0xFF387BA5,
+0xFF387BA5,
+0xFF377CA6,
+0xFF387DA7,
+0xFF387DA7,
+0xFF387DA7,
+0xFF387DA7,
+0xFF387DA7,
+0xFF397EA8,
+0xFF397EA8,
+0xFF397EA8,
+0xFF397EA8,
+0xFF3A7EAB,
+0xFF3A7EAB,
+0xFF3980AC,
+0xFF3980AC,
+0xFF3980AC,
+0xFF3980AC,
+0xFF3A81AD,
+0xFF3A81AD,
+0xFF3982AD,
+0xFF3982AD,
+0xFF3982AD,
+0xFF3982AD,
+0xFF3982AF,
+0xFF3982AF,
+0xFF3882AF,
+0xFF3882AF,
+0xFF3A84B1,
+0xFF3A84B1,
+0xFF3A84B1,
+0xFF3A84B1,
+0xFF3A84B3,
+0xFF3A84B3,
+0xFF3B85B4,
+0xFF3B85B4,
+0xFF3886B6,
+0xFF3682B3,
+0xFF3E87B4,
+0xFF3F84AE,
+0xFF3C7AA3,
+0xFF6897B5,
+0xFFF0FFFF,
+0xFFFBFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFCFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFEFEFE,
+0xFFFFFFFD,
+0xFFFFFEFB,
+0xFFFFFAFA,
+0xFFFFFBFF,
+0xFFF9FCFF,
+0xFFF5FFFF,
+0xFFB8D7E9,
+0xFF4F87AC,
+0xFF5195C2,
+0xFF4388B1,
+0xFF3D87AE,
+0xFF3986B2,
+0xFF3A88B6,
+0xFF3A87B5,
+0xFF3983B0,
+0xFF3982AF,
+0xFF3A83B0,
+0xFF3983B4,
+0xFF3B82B6,
+0xFF3D80B4,
+0xFF3A80B1,
+0xFF3880B0,
+0xFF3582AE,
+0xFF3684B2,
+0xFF3687B4,
+0xFF3286B4,
+0xFF267FAB,
+0xFF1774A0,
+0xFF0C6F99,
+0xFF076E97,
+0xFF06719B,
+0xFF07749D,
+0xFF04749C,
+0xFF03729D,
+0xFF02719C,
+0xFF04709E,
+0xFF06719F,
+0xFF06719F,
+0xFF06719F,
+0xFF0874A3,
+0xFF0D749F,
+0xFF00587D,
+0xFF05526E,
+0xFF0A4357,
+0xFFBDE2EB,
+0xFFF3FEFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFF6FDFF,
+0xFFEAFFFF,
+0xFF5096B0,
+0xFF106A8D,
+0xFF1A7499,
+0xFF03557A,
+0xFF0A4D6A,
+0xFF124E6A,
+0xFF144D6A,
+0xFF144D6A,
+0xFF154E6C,
+0xFF154D6E,
+0xFF154D72,
+0xFF164E71,
+0xFF15516D,
+0xFF17536F,
+0xFF1A5371,
+0xFF195172,
+0xFF174F70,
+0xFF154D6E,
+0xFF164E6F,
+0xFF1A5273,
+0xFF215779,
+0xFF255B7D,
+0xFF306688,
+0xFF306688,
+0xFF306587,
+0xFF2E6385,
+0xFF2E6385,
+0xFF2E6385,
+0xFF2F6486,
+0xFF306587,
+0xFF326487,
+0xFF326485,
+0xFF326584,
+0xFF306682,
+0xFF316685,
+0xFF326787,
+0xFF33678C,
+0xFF34688F,
+0xFF33678E,
+0xFF34688D,
+0xFF366B8D,
+0xFF366B8B,
+0xFF356A89,
+0xFF356A8A,
+0xFF37698E,
+0xFF386991,
+0xFF376891,
+0xFF396E98,
+0xFF38719C,
+0xFF30719B,
+0xFF418AB5,
+0xFF3B85AC,
+0xFF397DA0,
+0xFF679AB5,
+0xFFE8FFFF,
+0xFFF7FFFF,
+0xFFF9FFFF,
+0xFFFCFFFF,
+0xFFFDFDFF,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFFFFFB,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFD,
+0xFFFFFDFD,
+0xFFFFFEFB,
+0xFFFFFFFB,
+0xFFFEFFFF,
+0xFFFCFFFF,
+0xFFFEFFFF,
+0xFFFFFFFD,
+0xFFFEFDFB,
+0xFFFEFFFF,
+0xFFF8FFFF,
+0xFFEEFFFF,
+0xFFC0E4FC,
+0xFF497B9C,
+0xFF4382AB,
+0xFF448BB5,
+0xFF4489B3,
+0xFF30759E,
+0xFF3277A0,
+0xFF387BA5,
+0xFF3677A1,
+0xFF33749E,
+0xFF3A7BA3,
+0xFF3879A1,
+0xFF3978A1,
+0xFF3978A1,
+0xFF397AA4,
+0xFF397AA4,
+0xFF377AA4,
+0xFF377AA4,
+0xFF387BA5,
+0xFF387BA5,
+0xFF397CA6,
+0xFF397CA6,
+0xFF397CA7,
+0xFF397CA7,
+0xFF387DA7,
+0xFF397EA8,
+0xFF397EA8,
+0xFF397EA8,
+0xFF3A7FA9,
+0xFF3A7FA9,
+0xFF3A7EAB,
+0xFF3A7EAB,
+0xFF3B7FAC,
+0xFF3B7FAC,
+0xFF3B7FAC,
+0xFF3980AC,
+0xFF3982AD,
+0xFF3982AD,
+0xFF3982AD,
+0xFF3982AD,
+0xFF3982AD,
+0xFF3982AD,
+0xFF3982AD,
+0xFF3982AD,
+0xFF3A83B0,
+0xFF3A83B0,
+0xFF3A83B0,
+0xFF3A83B0,
+0xFF3B84B1,
+0xFF3B84B1,
+0xFF3B84B1,
+0xFF3A84B3,
+0xFF3986B4,
+0xFF3784B2,
+0xFF3D87B6,
+0xFF3D80AB,
+0xFF3C7193,
+0xFFBCDFF5,
+0xFFF5FFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFDFF,
+0xFFFFFDFF,
+0xFFFFFEFF,
+0xFFFEFFFF,
+0xFFFCFFFF,
+0xFFFCFEFB,
+0xFFFFFEFB,
+0xFFFFFCFC,
+0xFFFFFEFF,
+0xFFF8FFFF,
+0xFFEBFFFF,
+0xFF759EB4,
+0xFF5993B9,
+0xFF5598C5,
+0xFF3E81AB,
+0xFF3C83AD,
+0xFF3581B2,
+0xFF3381B2,
+0xFF3682B4,
+0xFF3781B2,
+0xFF3983B0,
+0xFF3784B2,
+0xFF3583B4,
+0xFF3481B5,
+0xFF3780B3,
+0xFF3581B3,
+0xFF3482B3,
+0xFF2F85B4,
+0xFF1F7EAC,
+0xFF1277A3,
+0xFF086F9A,
+0xFF046E98,
+0xFF07729C,
+0xFF09769F,
+0xFF08759E,
+0xFF03729D,
+0xFF02719C,
+0xFF02719C,
+0xFF05709E,
+0xFF07709F,
+0xFF0A70A0,
+0xFF0C70A1,
+0xFF0D71A2,
+0xFF0C72A2,
+0xFF046D9C,
+0xFF086D97,
+0xFF00577B,
+0xFF084E68,
+0xFF2B5969,
+0xFFEBFFFF,
+0xFFFBFFFF,
+0xFFFEFDFB,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFD,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFCFFFF,
+0xFFF5FFFF,
+0xFFDEFFFF,
+0xFF126283,
+0xFF137399,
+0xFF1A6D8F,
+0xFF084F6F,
+0xFF114E6D,
+0xFF164F6C,
+0xFF184F6D,
+0xFF184F6D,
+0xFF15506E,
+0xFF134E6E,
+0xFF124C71,
+0xFF114C6E,
+0xFF124F6C,
+0xFF14516D,
+0xFF114E6D,
+0xFF13506F,
+0xFF155271,
+0xFF165372,
+0xFF165372,
+0xFF155271,
+0xFF155070,
+0xFF144F6F,
+0xFF124D6D,
+0xFF185373,
+0xFF235B7C,
+0xFF2A6283,
+0xFF2F6788,
+0xFF31698A,
+0xFF32688A,
+0xFF31678B,
+0xFF30648B,
+0xFF306489,
+0xFF316685,
+0xFF316783,
+0xFF326882,
+0xFF356885,
+0xFF356788,
+0xFF35678C,
+0xFF34668B,
+0xFF34688D,
+0xFF346A8C,
+0xFF346B8A,
+0xFF336A89,
+0xFF34698B,
+0xFF376890,
+0xFF396991,
+0xFF3C6D96,
+0xFF31658C,
+0xFF33698F,
+0xFF2E6A8F,
+0xFF2C7097,
+0xFF3B83AB,
+0xFF3C87AF,
+0xFF3C7B9E,
+0xFF6D92AC,
+0xFFEEFFFF,
+0xFFF2FFFF,
+0xFFF7FFFF,
+0xFFF8FBFF,
+0xFFFEFDFF,
+0xFFFFFFFD,
+0xFFFFFEFA,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFEFFFF,
+0xFFFCFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFEFD,
+0xFFFEFDFB,
+0xFFFCFDFF,
+0xFFF8FFFF,
+0xFFEEFFFF,
+0xFFC6E6FB,
+0xFF4F80A0,
+0xFF4F8BB0,
+0xFF4D90BA,
+0xFF468BB5,
+0xFF3479A2,
+0xFF31769F,
+0xFF31749E,
+0xFF3A7BA5,
+0xFF35769E,
+0xFF3879A1,
+0xFF3877A0,
+0xFF3978A1,
+0xFF397AA4,
+0xFF397AA4,
+0xFF3679A3,
+0xFF3679A3,
+0xFF377AA4,
+0xFF387BA5,
+0xFF387BA5,
+0xFF387BA5,
+0xFF387BA6,
+0xFF397CA7,
+0xFF387DA7,
+0xFF397EA8,
+0xFF397EA8,
+0xFF397EA8,
+0xFF397EA8,
+0xFF397EA8,
+0xFF397DAA,
+0xFF3A7EAB,
+0xFF3A7EAB,
+0xFF3A7EAB,
+0xFF3A7EAB,
+0xFF3B7FAC,
+0xFF3980AC,
+0xFF3881AC,
+0xFF3881AC,
+0xFF3982AD,
+0xFF3982AD,
+0xFF3982AD,
+0xFF3982AD,
+0xFF3982AD,
+0xFF3982AF,
+0xFF3982AF,
+0xFF3A83B0,
+0xFF3A83B0,
+0xFF3A83B0,
+0xFF3A83B0,
+0xFF3A83B0,
+0xFF3A83B0,
+0xFF3781AE,
+0xFF3A87B5,
+0xFF3987B7,
+0xFF3C7FA9,
+0xFF56829D,
+0xFFEDFFFF,
+0xFFF8FFFF,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFDFF,
+0xFFFFFDFF,
+0xFFFFFEFF,
+0xFFFCFFFF,
+0xFFFBFFFF,
+0xFFF9FEF8,
+0xFFFFFFFA,
+0xFFFFFDFD,
+0xFFFFFEFF,
+0xFFF5FFFF,
+0xFFD3F2FF,
+0xFF5F8EA8,
+0xFF5F9BC0,
+0xFF5295C0,
+0xFF3B80AA,
+0xFF3881AE,
+0xFF3987B8,
+0xFF3484B7,
+0xFF3481B5,
+0xFF3684B4,
+0xFF3487B3,
+0xFF3387B3,
+0xFF3088B6,
+0xFF2D85B5,
+0xFF287EB1,
+0xFF1F77A9,
+0xFF146EA0,
+0xFF0A6A9A,
+0xFF07709F,
+0xFF0574A1,
+0xFF0776A3,
+0xFF0776A3,
+0xFF0574A1,
+0xFF02739F,
+0xFF03729F,
+0xFF05749F,
+0xFF01709B,
+0xFF04719C,
+0xFF0772A0,
+0xFF0A73A2,
+0xFF0D71A2,
+0xFF0C70A1,
+0xFF0C6E9F,
+0xFF086D9B,
+0xFF0C72A2,
+0xFF03668F,
+0xFF075D80,
+0xFF0A4A63,
+0xFF94B8C6,
+0xFFF3FFFF,
+0xFFFFFFFF,
+0xFFFFFEFD,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFCFFFD,
+0xFFFEFFFB,
+0xFFFFFFFB,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFF9FFFF,
+0xFFEFFFFF,
+0xFF8CBDCE,
+0xFF075F83,
+0xFF0D6F96,
+0xFF0C5776,
+0xFF0F4C68,
+0xFF144A6C,
+0xFF154A6A,
+0xFF184B6A,
+0xFF174C6B,
+0xFF13506F,
+0xFF115071,
+0xFF144F71,
+0xFF144F6F,
+0xFF11516D,
+0xFF10516D,
+0xFF115270,
+0xFF115272,
+0xFF125172,
+0xFF135273,
+0xFF145374,
+0xFF145374,
+0xFF155173,
+0xFF155173,
+0xFF185476,
+0xFF175375,
+0xFF165173,
+0xFF144F71,
+0xFF165173,
+0xFF1A5577,
+0xFF225A7D,
+0xFF275F84,
+0xFF30658D,
+0xFF31678D,
+0xFF326988,
+0xFF346A84,
+0xFF346A82,
+0xFF356883,
+0xFF366485,
+0xFF366486,
+0xFF35678C,
+0xFF34688D,
+0xFF336B8C,
+0xFF336C8A,
+0xFF326A8B,
+0xFF33698D,
+0xFF376891,
+0xFF386890,
+0xFF36688D,
+0xFF3A6F91,
+0xFF376D8F,
+0xFF367095,
+0xFF306C91,
+0xFF327298,
+0xFF3B7AA3,
+0xFF417FA6,
+0xFF41779B,
+0xFF527E99,
+0xFFEAFFFF,
+0xFFF4FFFF,
+0xFFFBFFFF,
+0xFFFEFEFC,
+0xFFFEFDF9,
+0xFFFFFFFB,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFD,
+0xFFFFFCF9,
+0xFFFFFEF9,
+0xFFFFFFFA,
+0xFFFCFFFD,
+0xFFF3FEFF,
+0xFFF0FFFF,
+0xFFD3F0FF,
+0xFF58849F,
+0xFF4F8DB2,
+0xFF5299C3,
+0xFF4A8FB9,
+0xFF30759F,
+0xFF387BA5,
+0xFF3578A2,
+0xFF3677A1,
+0xFF3778A2,
+0xFF3877A0,
+0xFF3978A1,
+0xFF397AA2,
+0xFF397AA2,
+0xFF3879A3,
+0xFF3879A3,
+0xFF377AA4,
+0xFF387BA5,
+0xFF387BA5,
+0xFF387BA5,
+0xFF387BA5,
+0xFF387BA5,
+0xFF387BA6,
+0xFF397CA7,
+0xFF397CA7,
+0xFF3A7DA8,
+0xFF387DA7,
+0xFF397EA8,
+0xFF397EA8,
+0xFF397EA8,
+0xFF397DAA,
+0xFF3A7EAB,
+0xFF3A7EAB,
+0xFF3A7EAB,
+0xFF3980AC,
+0xFF3980AC,
+0xFF3980AC,
+0xFF3980AC,
+0xFF3980AC,
+0xFF3980AC,
+0xFF3A81AD,
+0xFF3A81AD,
+0xFF3A81AD,
+0xFF3A81AD,
+0xFF3982AF,
+0xFF3982AF,
+0xFF3982AF,
+0xFF3982AF,
+0xFF3982AF,
+0xFF3982AF,
+0xFF3881AC,
+0xFF3E88B5,
+0xFF3A8ABB,
+0xFF3D80AA,
+0xFF9CC1D4,
+0xFFF4FFFF,
+0xFFFCFFFF,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFDFF,
+0xFFFFFDFF,
+0xFFFEFFFF,
+0xFFFBFFFF,
+0xFFF9FFFD,
+0xFFFCFFFB,
+0xFFFFFFFA,
+0xFFFFFDFC,
+0xFFFBFBFF,
+0xFFF0FFFF,
+0xFF9AC0D5,
+0xFF5E96B1,
+0xFF5E9DC0,
+0xFF4388B1,
+0xFF3781AE,
+0xFF3381B1,
+0xFF3788BD,
+0xFF3487BD,
+0xFF3083B5,
+0xFF2D83B2,
+0xFF1F7CA7,
+0xFF1679A0,
+0xFF0C739C,
+0xFF06709A,
+0xFF056E9D,
+0xFF06719F,
+0xFF0773A2,
+0xFF0975A4,
+0xFF0773A4,
+0xFF0672A3,
+0xFF0672A3,
+0xFF0672A3,
+0xFF0672A1,
+0xFF02719F,
+0xFF036F9E,
+0xFF036F9D,
+0xFF05719F,
+0xFF05719F,
+0xFF06719D,
+0xFF07709D,
+0xFF07709D,
+0xFF0A719E,
+0xFF0C719F,
+0xFF0C719D,
+0xFF0A719E,
+0xFF005C84,
+0xFF045779,
+0xFF104C64,
+0xFFE6FFFF,
+0xFFFBFFFF,
+0xFFFFFEFF,
+0xFFFFFCFB,
+0xFFFFFEFF,
+0xFFFEFFFF,
+0xFFFCFFFF,
+0xFFFBFFFD,
+0xFFFEFFF8,
+0xFFFFFFFA,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFF5FFFF,
+0xFFE6FFFF,
+0xFF235F77,
+0xFF136B8F,
+0xFF0C688D,
+0xFF094C69,
+0xFF164E69,
+0xFF184A6B,
+0xFF184A6B,
+0xFF194C6B,
+0xFF164D6C,
+0xFF124E70,
+0xFF104F70,
+0xFF124F6E,
+0xFF13506D,
+0xFF10506C,
+0xFF0F506C,
+0xFF135472,
+0xFF115272,
+0xFF105171,
+0xFF115272,
+0xFF135273,
+0xFF145374,
+0xFF145374,
+0xFF145374,
+0xFF125172,
+0xFF135273,
+0xFF155475,
+0xFF185476,
+0xFF185476,
+0xFF175375,
+0xFF175375,
+0xFF185478,
+0xFF175179,
+0xFF1B557B,
+0xFF215C7C,
+0xFF29627F,
+0xFF2E6782,
+0xFF326A85,
+0xFF346989,
+0xFF34698B,
+0xFF34688D,
+0xFF326A8D,
+0xFF306B8B,
+0xFF306B8B,
+0xFF316C8E,
+0xFF346A90,
+0xFF356991,
+0xFF376890,
+0xFF39698D,
+0xFF37698A,
+0xFF366D8C,
+0xFF346C8D,
+0xFF366E91,
+0xFF326C92,
+0xFF346E96,
+0xFF3E79A3,
+0xFF3C7BA4,
+0xFF3E769B,
+0xFF58809A,
+0xFFEBFFFF,
+0xFFF2FFFF,
+0xFFFCFFFF,
+0xFFFFFFFD,
+0xFFFFFDFA,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFBFFFF,
+0xFFFCFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFFFEFB,
+0xFFFFFFFA,
+0xFFFFFFFA,
+0xFFFBFCF7,
+0xFFFCFFFF,
+0xFFF7FFFF,
+0xFFF4FFFF,
+0xFFD8F3FF,
+0xFF5C8BA5,
+0xFF5792B4,
+0xFF5999BF,
+0xFF4D90BA,
+0xFF3376A1,
+0xFF31719D,
+0xFF3778A2,
+0xFF3778A2,
+0xFF3778A0,
+0xFF3978A1,
+0xFF3A79A2,
+0xFF3879A1,
+0xFF3679A3,
+0xFF3679A3,
+0xFF3879A3,
+0xFF377AA4,
+0xFF377AA4,
+0xFF367BA4,
+0xFF377AA4,
+0xFF367BA4,
+0xFF387BA6,
+0xFF377CA6,
+0xFF397CA7,
+0xFF387DA7,
+0xFF387DA7,
+0xFF387DA7,
+0xFF387DA7,
+0xFF397EA8,
+0xFF397DAA,
+0xFF397DAA,
+0xFF397DAA,
+0xFF397DAA,
+0xFF3A7EAB,
+0xFF3A7EAB,
+0xFF3A7EAB,
+0xFF3B7FAC,
+0xFF3980AC,
+0xFF3980AC,
+0xFF3980AC,
+0xFF3980AC,
+0xFF3980AC,
+0xFF3980AE,
+0xFF3980AE,
+0xFF3A81AF,
+0xFF3A81AF,
+0xFF3A81AF,
+0xFF3982AD,
+0xFF3982AD,
+0xFF3B82AE,
+0xFF438CB7,
+0xFF458FBC,
+0xFF437FA1,
+0xFFE5FFFF,
+0xFFF7FFFF,
+0xFFFFFFFF,
+0xFFFEFDFB,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFD,
+0xFFFFFFFB,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFDFF,
+0xFFFFFEFF,
+0xFFFEFFFF,
+0xFFFBFFFF,
+0xFFF8FFFC,
+0xFFFCFFFB,
+0xFFFEFDF9,
+0xFFFFFEFF,
+0xFFF9FFFF,
+0xFFEDFFFF,
+0xFF6A98B2,
+0xFF61A0C1,
+0xFF5BA3C9,
+0xFF307FAA,
+0xFF3286B4,
+0xFF2782B1,
+0xFF1D79AC,
+0xFF1671A6,
+0xFF1470A1,
+0xFF0D6E9B,
+0xFF0C739C,
+0xFF08749B,
+0xFF04749C,
+0xFF03749E,
+0xFF0576A2,
+0xFF0376A3,
+0xFF0176A2,
+0xFF0073A2,
+0xFF0674A5,
+0xFF0670A2,
+0xFF056FA3,
+0xFF0670A4,
+0xFF0671A5,
+0xFF0571A2,
+0xFF06719F,
+0xFF06719F,
+0xFF0873A1,
+0xFF0873A1,
+0xFF0873A1,
+0xFF07729E,
+0xFF09709B,
+0xFF086F9A,
+0xFF096E9A,
+0xFF076E99,
+0xFF036A97,
+0xFF06638C,
+0xFF0B5673,
+0xFF5F92A5,
+0xFFF1FFFF,
+0xFFFFFFFF,
+0xFFFFFBFF,
+0xFFFFFDFF,
+0xFFFFFEFF,
+0xFFFEFFFF,
+0xFFFBFFFF,
+0xFFFBFFFD,
+0xFFFEFFFA,
+0xFFFFFFFA,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFEFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFDFE,
+0xFFFFFDFE,
+0xFFFEFFFF,
+0xFFF0FFFF,
+0xFFACE0F8,
+0xFF0F5879,
+0xFF0E6183,
+0xFF105F80,
+0xFF0D4A69,
+0xFF154865,
+0xFF1C4F6E,
+0xFF154867,
+0xFF154C6A,
+0xFF134E6C,
+0xFF134E70,
+0xFF144F71,
+0xFF13506F,
+0xFF13506D,
+0xFF124F6B,
+0xFF124F6B,
+0xFF11506F,
+0xFF125170,
+0xFF125170,
+0xFF125170,
+0xFF145170,
+0xFF155271,
+0xFF155173,
+0xFF165274,
+0xFF135273,
+0xFF135273,
+0xFF145376,
+0xFF145477,
+0xFF155578,
+0xFF155578,
+0xFF155578,
+0xFF145477,
+0xFF16567A,
+0xFF155579,
+0xFF145477,
+0xFF135474,
+0xFF145575,
+0xFF175878,
+0xFF1C5B7E,
+0xFF1F5E81,
+0xFF28678A,
+0xFF2A698C,
+0xFF2D6C8D,
+0xFF316D8F,
+0xFF326C91,
+0xFF336B90,
+0xFF356B91,
+0xFF376B92,
+0xFF39698D,
+0xFF396A8B,
+0xFF366B8B,
+0xFF356C8B,
+0xFF366C8E,
+0xFF366C90,
+0xFF346B92,
+0xFF316C96,
+0xFF3778A2,
+0xFF397AA0,
+0xFF387091,
+0xFF45738B,
+0xFFEAFFFF,
+0xFFF5FFFF,
+0xFFFBFBFD,
+0xFFFFFEFB,
+0xFFFEFFF9,
+0xFFFEFFFB,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFF9FDFE,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFCFFFD,
+0xFFFEFFFB,
+0xFFFFFFFB,
+0xFFFEFFFD,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFEFFFF,
+0xFFFCFFFF,
+0xFFFBFFFF,
+0xFFF6FFFF,
+0xFFE1F8FF,
+0xFF6E93A5,
+0xFF6095B5,
+0xFF5998C1,
+0xFF5795C4,
+0xFF3474A2,
+0xFF31719D,
+0xFF3477A1,
+0xFF34789F,
+0xFF397AA2,
+0xFF37759C,
+0xFF3A79A2,
+0xFF3479A3,
+0xFF2D749E,
+0xFF397AA4,
+0xFF3879A1,
+0xFF357AA1,
+0xFF347CA2,
+0xFF367BA4,
+0xFF347CA4,
+0xFF377CA5,
+0xFF357DA5,
+0xFF377CA5,
+0xFF367EA6,
+0xFF357DA5,
+0xFF367EA6,
+0xFF377EA8,
+0xFF367DA7,
+0xFF367DA7,
+0xFF367DA7,
+0xFF397EA8,
+0xFF397EA8,
+0xFF3A7DA8,
+0xFF3A7DAA,
+0xFF3A7CAC,
+0xFF3B7DAD,
+0xFF3A7EAD,
+0xFF3B7FAC,
+0xFF3B80AA,
+0xFF3B80AA,
+0xFF3B7FAC,
+0xFF387CAB,
+0xFF3F81B3,
+0xFF3D7FB1,
+0xFF3D7FAF,
+0xFF3A7EAB,
+0xFF3982AB,
+0xFF3881AC,
+0xFF3D84B2,
+0xFF5295C0,
+0xFF4A8BAB,
+0xFF7BABBF,
+0xFFF1FFFF,
+0xFFFFFFFF,
+0xFFFFFEFB,
+0xFFFFFEFC,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFFFEFF,
+0xFFFFFEFB,
+0xFFFFFFFA,
+0xFFFEFFFB,
+0xFFFEFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFB,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFEFFFF,
+0xFFFCFFFF,
+0xFFFBFFFA,
+0xFFFEFFFB,
+0xFFFFFFFD,
+0xFFFBFEFF,
+0xFFF2FFFF,
+0xFFBADAEF,
+0xFF6398B8,
+0xFF5DA6CF,
+0xFF2A85B1,
+0xFF1075A3,
+0xFF076D9D,
+0xFF0972A2,
+0xFF0973A3,
+0xFF0771A1,
+0xFF0771A1,
+0xFF0772A0,
+0xFF0773A1,
+0xFF0473A0,
+0xFF0473A0,
+0xFF0574A1,
+0xFF0574A2,
+0xFF0474A2,
+0xFF0575A3,
+0xFF0576A2,
+0xFF0473A0,
+0xFF04709E,
+0xFF046EA0,
+0xFF046EA2,
+0xFF0570A4,
+0xFF0672A3,
+0xFF09729F,
+0xFF0A749E,
+0xFF09729F,
+0xFF0873A1,
+0xFF0670A0,
+0xFF066F9E,
+0xFF0C6F98,
+0xFF0C6E95,
+0xFF0B6E98,
+0xFF0A719E,
+0xFF016C9A,
+0xFF015F85,
+0xFF104E65,
+0xFFCAEEFA,
+0xFFF7FFFF,
+0xFFFDFBFF,
+0xFFFFFCFF,
+0xFFFFFBFF,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFCFFFD,
+0xFFFCFFFD,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFEFFFF,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFEFFFF,
+0xFFFDFBFC,
+0xFFFFFCFD,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFBFFFF,
+0xFFEAFFFF,
+0xFF4382A1,
+0xFF0D5D82,
+0xFF166586,
+0xFF074E6C,
+0xFF114C6A,
+0xFF194C69,
+0xFF164966,
+0xFF174A67,
+0xFF144D6A,
+0xFF134E6C,
+0xFF134E6E,
+0xFF134E6E,
+0xFF13506D,
+0xFF13506C,
+0xFF134F6B,
+0xFF134F6B,
+0xFF13506D,
+0xFF125170,
+0xFF145170,
+0xFF145170,
+0xFF145170,
+0xFF155271,
+0xFF155173,
+0xFF165274,
+0xFF135273,
+0xFF145374,
+0xFF135376,
+0xFF145477,
+0xFF135577,
+0xFF135577,
+0xFF135577,
+0xFF135577,
+0xFF145679,
+0xFF145679,
+0xFF13577A,
+0xFF13577A,
+0xFF13577A,
+0xFF13577A,
+0xFF15597C,
+0xFF175B7E,
+0xFF105576,
+0xFF145678,
+0xFF19597C,
+0xFF1F5E81,
+0xFF236285,
+0xFF2A668A,
+0xFF2F698E,
+0xFF326C91,
+0xFF346A8E,
+0xFF346A8E,
+0xFF336B8C,
+0xFF346C8D,
+0xFF346C8D,
+0xFF356D90,
+0xFF346E94,
+0xFF316F98,
+0xFF2C6F99,
+0xFF32769D,
+0xFF37799C,
+0xFF3B7491,
+0xFF467086,
+0xFFE8FFFF,
+0xFFF8FFFF,
+0xFFFCFDFF,
+0xFFFFFFFB,
+0xFFFEFFFA,
+0xFFFEFFFF,
+0xFFFBFCFE,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFDFFFE,
+0xFFFCFEFB,
+0xFFFFFFFB,
+0xFFFFFFFB,
+0xFFFEFFFD,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFEFFFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFBFFFF,
+0xFFF8FFFF,
+0xFFE3FAFF,
+0xFF638DA6,
+0xFF699FC5,
+0xFF649FCB,
+0xFF4F8DBC,
+0xFF33739F,
+0xFF3879A3,
+0xFF3778A0,
+0xFF37779D,
+0xFF3C789D,
+0xFF36749B,
+0xFF3378A2,
+0xFF357CA8,
+0xFF3677A1,
+0xFF3778A0,
+0xFF3579A0,
+0xFF3479A0,
+0xFF357AA3,
+0xFF357AA3,
+0xFF367BA4,
+0xFF367BA4,
+0xFF367BA4,
+0xFF377CA5,
+0xFF367BA4,
+0xFF377CA5,
+0xFF387DA7,
+0xFF387DA7,
+0xFF387DA7,
+0xFF397EA8,
+0xFF3A7DA8,
+0xFF3B7EA9,
+0xFF3C7FA9,
+0xFF3C7FAA,
+0xFF3C7FAC,
+0xFF3C7EAE,
+0xFF3A7EAB,
+0xFF377EAA,
+0xFF397EA7,
+0xFF397EA7,
+0xFF3D81AE,
+0xFF3B7FAE,
+0xFF3C80B1,
+0xFF3B7FB0,
+0xFF3A7EAD,
+0xFF3A7EAB,
+0xFF3982AB,
+0xFF367FA8,
+0xFF4B92C0,
+0xFF5897C0,
+0xFF5288A2,
+0xFFC5E9F7,
+0xFFF8FFFF,
+0xFFFFFBFA,
+0xFFFFFDFA,
+0xFFFFFFFD,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFFFEFF,
+0xFFFFFEFB,
+0xFFFFFFFA,
+0xFFFEFFFB,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFB,
+0xFFFEFFFB,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFEFFFD,
+0xFFFCFEFB,
+0xFFFCFCFC,
+0xFFF9FFFF,
+0xFFEDFFFF,
+0xFF729CB4,
+0xFF5B97BC,
+0xFF4B9CC9,
+0xFF0F74A2,
+0xFF0371A2,
+0xFF0373A3,
+0xFF0676A6,
+0xFF0575A5,
+0xFF0373A3,
+0xFF0373A1,
+0xFF0575A3,
+0xFF0474A2,
+0xFF0474A2,
+0xFF0574A2,
+0xFF0675A3,
+0xFF0574A2,
+0xFF0473A1,
+0xFF03729F,
+0xFF02719C,
+0xFF05729B,
+0xFF05729D,
+0xFF0670A0,
+0xFF0771A3,
+0xFF0772A6,
+0xFF0773A4,
+0xFF0A719C,
+0xFF0A7098,
+0xFF09709B,
+0xFF0871A0,
+0xFF056F9F,
+0xFF046F9D,
+0xFF0C6F98,
+0xFF0D6F96,
+0xFF0B6E98,
+0xFF086D9B,
+0xFF006895,
+0xFF0E668A,
+0xFF376B80,
+0xFFE6FFFF,
+0xFFF9FFFF,
+0xFFFFFDFF,
+0xFFFFFBFF,
+0xFFFFFBFF,
+0xFFFFFDFF,
+0xFFFFFFFB,
+0xFFFEFFFB,
+0xFFFCFFFD,
+0xFFFEFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFD,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFEFFFF,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFEFFFF,
+0xFFFCFDFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFCFB,
+0xFFFFFAFC,
+0xFFFFFFFF,
+0xFFF3FEFF,
+0xFFE0FFFF,
+0xFF0D4E6C,
+0xFF0D5B7F,
+0xFF145D7E,
+0xFF074969,
+0xFF114C6A,
+0xFF144C67,
+0xFF174A67,
+0xFF184B68,
+0xFF164B6A,
+0xFF144D6B,
+0xFF134E6E,
+0xFF124F6E,
+0xFF124F6C,
+0xFF124F6B,
+0xFF134F6B,
+0xFF134F6B,
+0xFF13506D,
+0xFF13506F,
+0xFF145170,
+0xFF145170,
+0xFF145170,
+0xFF145170,
+0xFF155173,
+0xFF155173,
+0xFF145374,
+0xFF145374,
+0xFF135474,
+0xFF135474,
+0xFF125476,
+0xFF135577,
+0xFF135577,
+0xFF135577,
+0xFF135578,
+0xFF145679,
+0xFF16587B,
+0xFF16587B,
+0xFF14587B,
+0xFF13577A,
+0xFF13577A,
+0xFF14587B,
+0xFF15597C,
+0xFF15597C,
+0xFF14587B,
+0xFF16587B,
+0xFF16587B,
+0xFF16587B,
+0xFF18587C,
+0xFF17597C,
+0xFF1A6082,
+0xFF1D6385,
+0xFF24698A,
+0xFF2B6D8D,
+0xFF2F7090,
+0xFF307191,
+0xFF307094,
+0xFF2F7098,
+0xFF2E6F99,
+0xFF31729A,
+0xFF2F7396,
+0xFF30718F,
+0xFF3A7289,
+0xFF3C677A,
+0xFFE0FCFF,
+0xFFF5FFFF,
+0xFFFFFEFF,
+0xFFFCFBF9,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFDFEFF,
+0xFFFFFFFF,
+0xFFFFFCFF,
+0xFFFFFDFF,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFEFFFD,
+0xFFFEFFFD,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFF9FFFF,
+0xFFF2FFFF,
+0xFFD7F3FF,
+0xFF6790AE,
+0xFF69A1C6,
+0xFF66A5CE,
+0xFF4180A9,
+0xFF306F98,
+0xFF3A7AA0,
+0xFF347299,
+0xFF3A789D,
+0xFF3A7AA0,
+0xFF3477A2,
+0xFF377CA6,
+0xFF367AA1,
+0xFF38799F,
+0xFF397AA2,
+0xFF397AA2,
+0xFF397AA2,
+0xFF397AA2,
+0xFF3A7BA5,
+0xFF3A7BA5,
+0xFF3A7BA5,
+0xFF3A7BA5,
+0xFF3A7BA5,
+0xFF3A7BA5,
+0xFF3B7CA6,
+0xFF3B7CA6,
+0xFF3B7BA7,
+0xFF3B7BA7,
+0xFF3C7CA8,
+0xFF3A7DA7,
+0xFF377CA3,
+0xFF367EA4,
+0xFF387DA6,
+0xFF397EA8,
+0xFF377EA8,
+0xFF3781A8,
+0xFF3880A8,
+0xFF3880A8,
+0xFF377FA7,
+0xFF387FA9,
+0xFF367FAA,
+0xFF3580AA,
+0xFF3580A8,
+0xFF3782AA,
+0xFF3882A9,
+0xFF3C84AC,
+0xFF599DCA,
+0xFF5D99BE,
+0xFF6996AD,
+0xFFE9FFFF,
+0xFFF9FFFF,
+0xFFFFFFFD,
+0xFFFCFCFA,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFEFF,
+0xFFFFFEFD,
+0xFFFFFFFB,
+0xFFFEFFFD,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFEFFFB,
+0xFFFEFFFA,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFFFFFF,
+0xFFF8FFFF,
+0xFFD4F4FF,
+0xFF598CA7,
+0xFF5DA1C6,
+0xFF4195C1,
+0xFF056C99,
+0xFF0473A1,
+0xFF0675A3,
+0xFF0574A2,
+0xFF0373A1,
+0xFF0373A1,
+0xFF0373A1,
+0xFF0676A4,
+0xFF0473A1,
+0xFF0473A1,
+0xFF0574A1,
+0xFF0574A1,
+0xFF0672A0,
+0xFF05719F,
+0xFF04709E,
+0xFF03709B,
+0xFF07729C,
+0xFF07729C,
+0xFF0772A0,
+0xFF0773A2,
+0xFF0573A4,
+0xFF0773A2,
+0xFF0A6F99,
+0xFF0C6D97,
+0xFF0B6D9A,
+0xFF096E9C,
+0xFF05709E,
+0xFF03709B,
+0xFF087097,
+0xFF0B7197,
+0xFF096E9C,
+0xFF066B99,
+0xFF086B95,
+0xFF0C5C7F,
+0xFF99C6D9,
+0xFFF0FFFF,
+0xFFFAFFFF,
+0xFFFFFEFF,
+0xFFFFFBFF,
+0xFFFFFDFF,
+0xFFFFFDFF,
+0xFFFFFEFD,
+0xFFFEFFFD,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFEFFFF,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFD,
+0xFFFFFFFD,
+0xFFFFFDFF,
+0xFFFFFEFF,
+0xFFFEFFFF,
+0xFFFCFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFEFE,
+0xFFFFFFFD,
+0xFFFFFEFB,
+0xFFFFFCFE,
+0xFFFDFEFF,
+0xFFEFFFFF,
+0xFF7DA7B7,
+0xFF125572,
+0xFF0C587A,
+0xFF0B4F72,
+0xFF0E4D6C,
+0xFF114D69,
+0xFF104964,
+0xFF174D67,
+0xFF194C69,
+0xFF184B6A,
+0xFF154C6B,
+0xFF124D6D,
+0xFF124F6E,
+0xFF124F6C,
+0xFF124F6C,
+0xFF134F6B,
+0xFF14506C,
+0xFF13506D,
+0xFF13506F,
+0xFF145170,
+0xFF145170,
+0xFF145170,
+0xFF145170,
+0xFF155173,
+0xFF155173,
+0xFF145374,
+0xFF145374,
+0xFF135474,
+0xFF135474,
+0xFF135376,
+0xFF125476,
+0xFF135577,
+0xFF135577,
+0xFF135578,
+0xFF145679,
+0xFF15577A,
+0xFF15577A,
+0xFF13577A,
+0xFF13577A,
+0xFF14587B,
+0xFF15597C,
+0xFF12587A,
+0xFF12587A,
+0xFF12587A,
+0xFF13597B,
+0xFF145A7C,
+0xFF155B7D,
+0xFF155B7D,
+0xFF125B7E,
+0xFF0E5D7E,
+0xFF0E5D7E,
+0xFF105B7B,
+0xFF115A7A,
+0xFF135A7A,
+0xFF175C7D,
+0xFF1B5F82,
+0xFF1F6388,
+0xFF23678E,
+0xFF286C93,
+0xFF287194,
+0xFF2D7696,
+0xFF2D738D,
+0xFF326E86,
+0xFF35657C,
+0xFFDAF9FF,
+0xFFF4FEFF,
+0xFFFEFFFF,
+0xFFF8FEFE,
+0xFFFCFFFF,
+0xFFFFFFFF,
+0xFFFFFBFC,
+0xFFFFFCFF,
+0xFFFFFAFF,
+0xFFFFFDFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFAFFFF,
+0xFFF7FFFF,
+0xFFF1FFFF,
+0xFFB5D4E8,
+0xFF6A9CB7,
+0xFF68A5C4,
+0xFF68A6CB,
+0xFF3C7CA2,
+0xFF327097,
+0xFF39779C,
+0xFF37779B,
+0xFF38789E,
+0xFF3778A2,
+0xFF32759F,
+0xFF35799E,
+0xFF367A9F,
+0xFF3879A1,
+0xFF3978A1,
+0xFF3978A1,
+0xFF3978A1,
+0xFF3978A3,
+0xFF3978A3,
+0xFF3978A3,
+0xFF3978A3,
+0xFF3978A3,
+0xFF397AA4,
+0xFF3A79A4,
+0xFF397AA4,
+0xFF3B7AA6,
+0xFF3A7AA6,
+0xFF3B7AA6,
+0xFF387BA5,
+0xFF397EA5,
+0xFF3880A6,
+0xFF3A7FA8,
+0xFF3A7FA8,
+0xFF3880A8,
+0xFF3880A8,
+0xFF3880A8,
+0xFF3880A8,
+0xFF3A7FA8,
+0xFF3A82AA,
+0xFF3883AA,
+0xFF3583A9,
+0xFF3686AB,
+0xFF3482A8,
+0xFF357CA6,
+0xFF4D90BA,
+0xFF5DA1C8,
+0xFF5F97B8,
+0xFFB0CFE4,
+0xFFF4FFFF,
+0xFFF8FDFF,
+0xFFFEFFFD,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFCFFFB,
+0xFFFCFFFA,
+0xFFFFFFFB,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFF8FCFD,
+0xFFFCFFFF,
+0xFFFCFEFD,
+0xFFF4FFFF,
+0xFF8AB5C8,
+0xFF5695B4,
+0xFF509EC4,
+0xFF1C77A3,
+0xFF066F9C,
+0xFF0776A4,
+0xFF0574A2,
+0xFF02719F,
+0xFF0474A2,
+0xFF0474A2,
+0xFF0373A1,
+0xFF0474A2,
+0xFF0372A0,
+0xFF0372A0,
+0xFF03729F,
+0xFF05719F,
+0xFF05719F,
+0xFF05719F,
+0xFF05719F,
+0xFF06719D,
+0xFF09739D,
+0xFF09739D,
+0xFF08719E,
+0xFF06719F,
+0xFF0672A1,
+0xFF06719F,
+0xFF0C6F99,
+0xFF0D6D97,
+0xFF0E6D99,
+0xFF0B6D9A,
+0xFF05709C,
+0xFF04719A,
+0xFF067097,
+0xFF067097,
+0xFF066F9E,
+0xFF086C9D,
+0xFF0D6992,
+0xFF145978,
+0xFFE4FFFF,
+0xFFF3FFFF,
+0xFFFBFFFF,
+0xFFFEFEFE,
+0xFFFFFEFF,
+0xFFFFFDFF,
+0xFFFFFDFF,
+0xFFFFFDFD,
+0xFFFFFFFD,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFEFFFF,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFD,
+0xFFFEFFFD,
+0xFFFFFDFF,
+0xFFFFFEFF,
+0xFFFEFFFF,
+0xFFFCFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFEFCFD,
+0xFFFFFFFB,
+0xFFFFFDFA,
+0xFFFFFDFF,
+0xFFF8FDFF,
+0xFFEAFFFF,
+0xFF1C4C60,
+0xFF0D5470,
+0xFF0D5878,
+0xFF0B4A6D,
+0xFF0F4A6A,
+0xFF114D69,
+0xFF104C66,
+0xFF124A63,
+0xFF1A4D6A,
+0xFF194A6A,
+0xFF164B6B,
+0xFF124D6D,
+0xFF114E6D,
+0xFF124F6C,
+0xFF134E6C,
+0xFF154E6B,
+0xFF14506C,
+0xFF124F6C,
+0xFF13506F,
+0xFF13506F,
+0xFF145170,
+0xFF145170,
+0xFF145170,
+0xFF145170,
+0xFF155271,
+0xFF135273,
+0xFF145374,
+0xFF145374,
+0xFF135474,
+0xFF135474,
+0xFF135474,
+0xFF135577,
+0xFF145678,
+0xFF135578,
+0xFF135578,
+0xFF145679,
+0xFF145679,
+0xFF145679,
+0xFF15577A,
+0xFF14587B,
+0xFF15597C,
+0xFF155B7D,
+0xFF145A7C,
+0xFF125B7C,
+0xFF125B7C,
+0xFF125C7F,
+0xFF125C7F,
+0xFF115B7E,
+0xFF105C7E,
+0xFF0E5C82,
+0xFF105E84,
+0xFF146084,
+0xFF166083,
+0xFF155E81,
+0xFF165C7E,
+0xFF165A7F,
+0xFF165A7F,
+0xFF125A80,
+0xFF105C80,
+0xFF116184,
+0xFF0D6082,
+0xFF116182,
+0xFF11607F,
+0xFF145E7B,
+0xFF18526A,
+0xFFD6F3FF,
+0xFFF2FFFF,
+0xFFF6FDFF,
+0xFFFFFFFF,
+0xFFFFFDFF,
+0xFFFFFBFC,
+0xFFFFFAFC,
+0xFFFFFDFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFCFFFF,
+0xFFF8FFFF,
+0xFFF0FFFF,
+0xFF95BCCD,
+0xFF73A7BF,
+0xFF6EABCA,
+0xFF5D9DC1,
+0xFF2F6D92,
+0xFF3D7DA1,
+0xFF36779D,
+0xFF2E7299,
+0xFF397AA2,
+0xFF367AA1,
+0xFF31779B,
+0xFF357B9F,
+0xFF3579A0,
+0xFF3778A2,
+0xFF3879A3,
+0xFF3879A3,
+0xFF3879A3,
+0xFF3879A3,
+0xFF3979A5,
+0xFF3979A5,
+0xFF3979A5,
+0xFF377AA5,
+0xFF3A7AA6,
+0xFF387BA6,
+0xFF3B7BA7,
+0xFF3A7DA8,
+0xFF3C7CA8,
+0xFF3A7DA8,
+0xFF367BA4,
+0xFF377CA5,
+0xFF387BA5,
+0xFF397CA6,
+0xFF397CA7,
+0xFF397CA7,
+0xFF3A7DA8,
+0xFF3A7DA8,
+0xFF3B7CA6,
+0xFF397CA6,
+0xFF3882A9,
+0xFF3381A7,
+0xFF3686AB,
+0xFF347FA7,
+0xFF3D7DAB,
+0xFF66A3CF,
+0xFF63A3C7,
+0xFF6496B1,
+0xFFE9FCFF,
+0xFFFCFFFF,
+0xFFFDFFFE,
+0xFFFCFFFD,
+0xFFFBFFFF,
+0xFFFAFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFCFFFB,
+0xFFFCFFFA,
+0xFFFFFFFA,
+0xFFFFFFFB,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFBFFFF,
+0xFFF9FFFF,
+0xFFEAFFFF,
+0xFF5189A0,
+0xFF4F9BBD,
+0xFF439BC3,
+0xFF096A95,
+0xFF06719F,
+0xFF0574A2,
+0xFF0372A0,
+0xFF0372A0,
+0xFF0675A3,
+0xFF0574A2,
+0xFF01709D,
+0xFF03729F,
+0xFF04709E,
+0xFF04709E,
+0xFF05719F,
+0xFF06719F,
+0xFF06719F,
+0xFF0772A0,
+0xFF08739F,
+0xFF09729F,
+0xFF09739D,
+0xFF0A719A,
+0xFF09709B,
+0xFF066F9C,
+0xFF05709E,
+0xFF066F9C,
+0xFF0C6F99,
+0xFF0E6E98,
+0xFF0F6E9A,
+0xFF0B6C97,
+0xFF086F9A,
+0xFF07739A,
+0xFF036F95,
+0xFF026F98,
+0xFF0571A2,
+0xFF0B6FA0,
+0xFF17698E,
+0xFF69A1BA,
+0xFFEBFFFF,
+0xFFF7FEFF,
+0xFFFCFFFF,
+0xFFFCFEFB,
+0xFFFCFFFF,
+0xFFFEFEFF,
+0xFFFFFDFF,
+0xFFFFFDFD,
+0xFFFFFFFD,
+0xFFFEFFFF,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFD,
+0xFFFEFFFD,
+0xFFFEFFFD,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFEFFFF,
+0xFFFCFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFDFE,
+0xFFFFFFFB,
+0xFFFFFFFB,
+0xFFFEFCFF,
+0xFFF7FFFF,
+0xFFABD0E0,
+0xFF0D455C,
+0xFF0A516F,
+0xFF0A5373,
+0xFF0D496B,
+0xFF124B69,
+0xFF114D69,
+0xFF124E68,
+0xFF114962,
+0xFF184B66,
+0xFF194A6A,
+0xFF184B6A,
+0xFF124D6B,
+0xFF114E6D,
+0xFF124D6B,
+0xFF134E6C,
+0xFF164F6C,
+0xFF164F6C,
+0xFF134E6C,
+0xFF13506F,
+0xFF13506F,
+0xFF13506F,
+0xFF13506F,
+0xFF145170,
+0xFF145170,
+0xFF155271,
+0xFF135273,
+0xFF135273,
+0xFF145374,
+0xFF145374,
+0xFF135474,
+0xFF135474,
+0xFF135577,
+0xFF145678,
+0xFF135578,
+0xFF135578,
+0xFF145679,
+0xFF15577A,
+0xFF15577A,
+0xFF15577A,
+0xFF13577A,
+0xFF13577A,
+0xFF13597B,
+0xFF115A7B,
+0xFF10597A,
+0xFF0F5A7A,
+0xFF0F5B7D,
+0xFF0F5E7F,
+0xFF105F80,
+0xFF115F83,
+0xFF115C83,
+0xFF0F5D83,
+0xFF0F5D83,
+0xFF0E5C80,
+0xFF125C81,
+0xFF145D80,
+0xFF195F83,
+0xFF1A6084,
+0xFF166286,
+0xFF116184,
+0xFF0B5F83,
+0xFF0F6588,
+0xFF0A5F84,
+0xFF085D82,
+0xFF075C81,
+0xFF0F5879,
+0xFF15475E,
+0xFFC8E5F5,
+0xFFF4FFFF,
+0xFFFCFFFF,
+0xFFFFFBFC,
+0xFFFFFDFB,
+0xFFFFFCFB,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFEFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFDFF,
+0xFFFDFDFF,
+0xFFFEFFFF,
+0xFFF7FFFF,
+0xFFEAFFFF,
+0xFF719BAB,
+0xFF6AA1BF,
+0xFF6FAFD3,
+0xFF4686AA,
+0xFF2F7096,
+0xFF30759C,
+0xFF3078A0,
+0xFF32779E,
+0xFF367BA2,
+0xFF2E789D,
+0xFF327CA1,
+0xFF3378A1,
+0xFF3378A1,
+0xFF3479A3,
+0xFF3479A2,
+0xFF357AA4,
+0xFF367BA5,
+0xFF367BA5,
+0xFF377CA6,
+0xFF357CA8,
+0xFF347BA5,
+0xFF347BA7,
+0xFF337AA4,
+0xFF337AA6,
+0xFF337AA6,
+0xFF337AA6,
+0xFF317AA5,
+0xFF3580AA,
+0xFF3580A8,
+0xFF3580A8,
+0xFF367FA8,
+0xFF367FAA,
+0xFF367FAC,
+0xFF367FAC,
+0xFF367FAC,
+0xFF3982AD,
+0xFF3681A9,
+0xFF3382A9,
+0xFF2A7EA3,
+0xFF2A7FA6,
+0xFF2675A0,
+0xFF3E82B3,
+0xFF65A4D0,
+0xFF5E99B9,
+0xFF8AB4CA,
+0xFFF7FFFF,
+0xFFFFFDFF,
+0xFFFFFFFD,
+0xFFFCFFFD,
+0xFFF7FFFF,
+0xFFF8FEFE,
+0xFFFFFEFF,
+0xFFFFFDFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFBFFFD,
+0xFFFBFFFA,
+0xFFFFFFF8,
+0xFFFFFFFA,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFDFEFF,
+0xFFF3FAFF,
+0xFFF2FFFF,
+0xFFA8CEDB,
+0xFF4487A2,
+0xFF459DC1,
+0xFF2585AF,
+0xFF086F9A,
+0xFF0772A0,
+0xFF0473A1,
+0xFF0372A0,
+0xFF02719F,
+0xFF01709E,
+0xFF006F9D,
+0xFF006F9C,
+0xFF0473A0,
+0xFF05719F,
+0xFF05719F,
+0xFF0772A0,
+0xFF0873A1,
+0xFF0873A1,
+0xFF0972A1,
+0xFF08719E,
+0xFF08729C,
+0xFF06709A,
+0xFF086F98,
+0xFF096E9A,
+0xFF0A6F9B,
+0xFF09709D,
+0xFF09709D,
+0xFF0B6E98,
+0xFF0C6D98,
+0xFF0E6D99,
+0xFF0A6B96,
+0xFF096E98,
+0xFF097099,
+0xFF026E95,
+0xFF026F9A,
+0xFF0474A6,
+0xFF0F71A0,
+0xFF1A6181,
+0xFFC9F4FF,
+0xFFF0FFFF,
+0xFFFBFFFF,
+0xFFFCFEFB,
+0xFFFCFFFD,
+0xFFFBFFFF,
+0xFFFEFFFF,
+0xFFFFFDFF,
+0xFFFFFDFD,
+0xFFFFFFFD,
+0xFFFEFFFF,
+0xFFFCFFFF,
+0xFFFEFFFF,
+0xFFFFFFFD,
+0xFFFFFFFB,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFD,
+0xFFFEFFFD,
+0xFFFEFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFDFE,
+0xFFFFFDFA,
+0xFFFFFFFD,
+0xFFFEFFFF,
+0xFFF1FFFF,
+0xFF3D6A7F,
+0xFF0C4965,
+0xFF0E5372,
+0xFF084D6C,
+0xFF0D4868,
+0xFF154C6A,
+0xFF124B66,
+0xFF124C64,
+0xFF134B64,
+0xFF164964,
+0xFF184969,
+0xFF174A69,
+0xFF134C6A,
+0xFF124D6B,
+0xFF124D6B,
+0xFF134E6C,
+0xFF164F6C,
+0xFF164F6C,
+0xFF134E6C,
+0xFF134E6C,
+0xFF144F6D,
+0xFF144F6D,
+0xFF13506F,
+0xFF13506F,
+0xFF145170,
+0xFF155271,
+0xFF125170,
+0xFF135271,
+0xFF155475,
+0xFF155475,
+0xFF135474,
+0xFF135474,
+0xFF135474,
+0xFF135575,
+0xFF135577,
+0xFF115677,
+0xFF145678,
+0xFF145678,
+0xFF15577A,
+0xFF15577A,
+0xFF145679,
+0xFF125679,
+0xFF155B7F,
+0xFF135C7F,
+0xFF125B7E,
+0xFF105A7D,
+0xFF0E5A7C,
+0xFF0C5B7C,
+0xFF0D5B7F,
+0xFF0E5C80,
+0xFF105A81,
+0xFF105B82,
+0xFF0F5F84,
+0xFF106085,
+0xFF115F85,
+0xFF125E82,
+0xFF125C81,
+0xFF115B80,
+0xFF116081,
+0xFF085B7D,
+0xFF17698E,
+0xFF0E6086,
+0xFF0F6189,
+0xFF146590,
+0xFF0A5E8C,
+0xFF05547D,
+0xFF105272,
+0xFF11435C,
+0xFFC1DEF0,
+0xFFEEFCFF,
+0xFFFCFFFF,
+0xFFFFFEFA,
+0xFFFEFFFA,
+0xFFFDFFFC,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFD,
+0xFFFFFFFB,
+0xFFFFFFFB,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFEFFFF,
+0xFFF7FFFD,
+0xFFF6FFFF,
+0xFFC8E1E8,
+0xFF6799B2,
+0xFF63A3C6,
+0xFF62A6CB,
+0xFF2E769E,
+0xFF2E79A1,
+0xFF3482A9,
+0xFF2F7B9F,
+0xFF327EA2,
+0xFF307BA2,
+0xFF337EA6,
+0xFF327DA5,
+0xFF327DA5,
+0xFF307DA7,
+0xFF307EA5,
+0xFF307DA7,
+0xFF307DA7,
+0xFF307FA8,
+0xFF307FA8,
+0xFF307FAA,
+0xFF2F7EA7,
+0xFF2C7DA8,
+0xFF2C7EA6,
+0xFF2B7CA7,
+0xFF2B7CA7,
+0xFF2A7BA6,
+0xFF287BA7,
+0xFF2178A3,
+0xFF2079A3,
+0xFF1D79A0,
+0xFF1B77A0,
+0xFF1B74A0,
+0xFF1A709F,
+0xFF1870A0,
+0xFF176F9D,
+0xFF0F6A96,
+0xFF0E6C92,
+0xFF0B6B91,
+0xFF0B6D92,
+0xFF0C6E95,
+0xFF0F6C97,
+0xFF4294C4,
+0xFF559CC6,
+0xFF5991AA,
+0xFFCBEBFA,
+0xFFFCFEFF,
+0xFFFFFAFF,
+0xFFFFFEFC,
+0xFFFCFFFB,
+0xFFF9FFFD,
+0xFFFCFFFF,
+0xFFFFFDFF,
+0xFFFFFDFF,
+0xFFFFFEFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFDFF,
+0xFFFFFFFF,
+0xFFFBFFFD,
+0xFFF9FFFA,
+0xFFFEFFF8,
+0xFFFFFFFA,
+0xFFFFFEFF,
+0xFFFFFDFF,
+0xFFFFFEFF,
+0xFFF7FFFF,
+0xFFE7FFFF,
+0xFF5F92A7,
+0xFF4594B5,
+0xFF3999C1,
+0xFF076E97,
+0xFF06719D,
+0xFF0672A0,
+0xFF05719F,
+0xFF05719F,
+0xFF04709E,
+0xFF016D9B,
+0xFF026E9C,
+0xFF05719F,
+0xFF0672A0,
+0xFF07729E,
+0xFF07729E,
+0xFF09729F,
+0xFF09729F,
+0xFF09729F,
+0xFF0A719E,
+0xFF09709D,
+0xFF086F9A,
+0xFF046F99,
+0xFF056F97,
+0xFF0B6E98,
+0xFF0D6E9B,
+0xFF0C6E9B,
+0xFF0C6E9B,
+0xFF096E9A,
+0xFF0A6D97,
+0xFF0C6D98,
+0xFF096A94,
+0xFF0B6C96,
+0xFF0A6D97,
+0xFF056C95,
+0xFF07749F,
+0xFF0779AB,
+0xFF0F709D,
+0xFF3F7B97,
+0xFFE9FFFF,
+0xFFF8FFFF,
+0xFFFFFFFF,
+0xFFFEFFFB,
+0xFFFCFFFB,
+0xFFF9FDFC,
+0xFFFEFFFF,
+0xFFFFFEFF,
+0xFFFFFDFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFD,
+0xFFFFFFFB,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFEFFFD,
+0xFFFEFFFD,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFD,
+0xFFFDFDFD,
+0xFFF8FFFF,
+0xFFD9F3FF,
+0xFF0C4058,
+0xFF0B4C6A,
+0xFF084B68,
+0xFF0D4E6C,
+0xFF0C4765,
+0xFF114A67,
+0xFF144C67,
+0xFF124A63,
+0xFF144A64,
+0xFF154B65,
+0xFF174A67,
+0xFF154A69,
+0xFF144B6A,
+0xFF144D6B,
+0xFF124D6B,
+0xFF134E6C,
+0xFF164F6C,
+0xFF164F6C,
+0xFF134E6C,
+0xFF134E6C,
+0xFF144F6D,
+0xFF144F6D,
+0xFF13506F,
+0xFF13506F,
+0xFF145170,
+0xFF145170,
+0xFF135271,
+0xFF145372,
+0xFF155475,
+0xFF155475,
+0xFF135474,
+0xFF125373,
+0xFF135474,
+0xFF135474,
+0xFF135577,
+0xFF115677,
+0xFF135577,
+0xFF135577,
+0xFF145679,
+0xFF15577A,
+0xFF15577A,
+0xFF16587B,
+0xFF12567B,
+0xFF12587C,
+0xFF125B7E,
+0xFF115B7E,
+0xFF0F5B7D,
+0xFF0D5C7D,
+0xFF0E5C80,
+0xFF115D81,
+0xFF145E83,
+0xFF135D84,
+0xFF105B82,
+0xFF0E5C82,
+0xFF0F5D83,
+0xFF105E84,
+0xFF115F85,
+0xFF126084,
+0xFF126283,
+0xFF126283,
+0xFF0E5E81,
+0xFF0E5E83,
+0xFF17648E,
+0xFF0F5D8B,
+0xFF0C5E8D,
+0xFF0D5E8B,
+0xFF07557B,
+0xFF0C4F6C,
+0xFF0D3D54,
+0xFFB9D9E8,
+0xFFECFDFF,
+0xFFF9FFFF,
+0xFFFCFFFD,
+0xFFFEFFFB,
+0xFFFEFFFD,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFEFFFF,
+0xFFFFFFFB,
+0xFFFFFFFB,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFDFF,
+0xFFFFFEFF,
+0xFFFAFEFD,
+0xFFFCFFFD,
+0xFFFFFFFB,
+0xFFF2FFFF,
+0xFF7BA5BB,
+0xFF4C8BAC,
+0xFF509AC1,
+0xFF2F7EA7,
+0xFF176893,
+0xFF13668E,
+0xFF176B8F,
+0xFF17698E,
+0xFF17668F,
+0xFF1A6994,
+0xFF176893,
+0xFF166993,
+0xFF156892,
+0xFF146992,
+0xFF136891,
+0xFF126790,
+0xFF126790,
+0xFF0F678F,
+0xFF116893,
+0xFF106792,
+0xFF106792,
+0xFF0F6892,
+0xFF106993,
+0xFF106993,
+0xFF106993,
+0xFF0E6995,
+0xFF0E6B97,
+0xFF0B6C97,
+0xFF096F97,
+0xFF096F97,
+0xFF0D6E9B,
+0xFF0D6D9D,
+0xFF0E6EA0,
+0xFF0D6FA0,
+0xFF0C719D,
+0xFF0D759C,
+0xFF097198,
+0xFF0C729A,
+0xFF086D97,
+0xFF0F709D,
+0xFF4FAAD7,
+0xFF4D97BC,
+0xFF6A9AAE,
+0xFFEEFFFF,
+0xFFFEFDFF,
+0xFFFFFBFF,
+0xFFFFFFFB,
+0xFFFEFFFB,
+0xFFFCFFFD,
+0xFFFBFCFE,
+0xFFFFFDFF,
+0xFFFFFDFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFDFF,
+0xFFFFFEFF,
+0xFFFBFFFD,
+0xFFF9FFFB,
+0xFFFEFFFA,
+0xFFFFFFFA,
+0xFFFFFDFF,
+0xFFFFFCFF,
+0xFFFFFDFF,
+0xFFF5FFFF,
+0xFFC5EEFF,
+0xFF3A7B99,
+0xFF3C94BA,
+0xFF2489B3,
+0xFF026D99,
+0xFF04719C,
+0xFF026E9C,
+0xFF036F9D,
+0xFF0773A1,
+0xFF0975A3,
+0xFF0773A1,
+0xFF0975A3,
+0xFF0A75A3,
+0xFF05709C,
+0xFF07729E,
+0xFF08719E,
+0xFF07709D,
+0xFF07709D,
+0xFF086F9C,
+0xFF086F9C,
+0xFF096E9C,
+0xFF086F9A,
+0xFF047097,
+0xFF067098,
+0xFF0C6D98,
+0xFF106D99,
+0xFF0E6D9B,
+0xFF0B6D9A,
+0xFF096E9A,
+0xFF096E9A,
+0xFF0A6D97,
+0xFF0A6B95,
+0xFF0C6C96,
+0xFF0A6B96,
+0xFF076C98,
+0xFF0D78A4,
+0xFF0E7CAD,
+0xFF126E97,
+0xFFA5D3EB,
+0xFFF1FFFF,
+0xFFF9FCFF,
+0xFFFFFFFD,
+0xFFFFFFFB,
+0xFFFCFEF9,
+0xFFFCFFFF,
+0xFFFEFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFB,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFEFFFD,
+0xFFFCFFFF,
+0xFFFEFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFEFFFF,
+0xFFF2FFFF,
+0xFF6E92A2,
+0xFF0A435E,
+0xFF0A4C6C,
+0xFF0C4B6A,
+0xFF0E4B67,
+0xFF0E4B67,
+0xFF0F4B65,
+0xFF144A64,
+0xFF164964,
+0xFF164964,
+0xFF144A64,
+0xFF134B66,
+0xFF144C67,
+0xFF154C6A,
+0xFF154C6A,
+0xFF144D6A,
+0xFF144D6A,
+0xFF154E6B,
+0xFF164F6C,
+0xFF134E6C,
+0xFF134E6C,
+0xFF134E6C,
+0xFF134E6C,
+0xFF144F6D,
+0xFF15506E,
+0xFF145170,
+0xFF155271,
+0xFF145170,
+0xFF145170,
+0xFF135271,
+0xFF145372,
+0xFF155475,
+0xFF155475,
+0xFF145374,
+0xFF125373,
+0xFF135577,
+0xFF115677,
+0xFF135577,
+0xFF135577,
+0xFF145678,
+0xFF145678,
+0xFF16567A,
+0xFF16587B,
+0xFF15577A,
+0xFF13577A,
+0xFF14587D,
+0xFF145A7E,
+0xFF125B7E,
+0xFF115B7E,
+0xFF105A7F,
+0xFF0F597E,
+0xFF125B7E,
+0xFF155B7F,
+0xFF145C82,
+0xFF135D84,
+0xFF0F5D83,
+0xFF0E5E83,
+0xFF0D5F84,
+0xFF0D6082,
+0xFF105F80,
+0xFF135F81,
+0xFF155F82,
+0xFF135F83,
+0xFF115F86,
+0xFF105F88,
+0xFF12618C,
+0xFF13628D,
+0xFF0C5B84,
+0xFF055175,
+0xFF0B516B,
+0xFF073E52,
+0xFFA7CBD7,
+0xFFF0FFFF,
+0xFFF8FDFF,
+0xFFFFFFFD,
+0xFFFFFFFB,
+0xFFFEFFFD,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFAFEFF,
+0xFFFEFFFF,
+0xFFFFFEFC,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFF6FCFC,
+0xFFFCFFFD,
+0xFFFFFEF8,
+0xFFFAFEFF,
+0xFFDBFAFF,
+0xFF3D7493,
+0xFF3F8CB6,
+0xFF3F97C5,
+0xFF0A638F,
+0xFF0E678F,
+0xFF106A8F,
+0xFF0E668C,
+0xFF12658F,
+0xFF136692,
+0xFF106792,
+0xFF106993,
+0xFF116A94,
+0xFF0E6A93,
+0xFF0D6992,
+0xFF0C6992,
+0xFF0D6A93,
+0xFF0E6B94,
+0xFF0D6A95,
+0xFF0C6C96,
+0xFF0D6D97,
+0xFF0D6D97,
+0xFF0D6D97,
+0xFF0C6D97,
+0xFF0C6D97,
+0xFF0D6E99,
+0xFF0E6D9D,
+0xFF0C6C9C,
+0xFF076E97,
+0xFF056F97,
+0xFF096E9C,
+0xFF0C6DA0,
+0xFF0A6EA2,
+0xFF096FA0,
+0xFF066F9C,
+0xFF0A749C,
+0xFF0A6F99,
+0xFF0F719E,
+0xFF0B6B9B,
+0xFF2A89B7,
+0xFF449DC9,
+0xFF468CAE,
+0xFFACD1E1,
+0xFFF0FFFF,
+0xFFFFFEFF,
+0xFFFFFBFF,
+0xFFFFFFFB,
+0xFFFDFEF8,
+0xFFFEFFFB,
+0xFFFEFEFE,
+0xFFFFFCFF,
+0xFFFFFCFF,
+0xFFFFFFFF,
+0xFFFCFFFF,
+0xFFFCFFFD,
+0xFFFEFFFD,
+0xFFFFFEFF,
+0xFFFFFDFF,
+0xFFFFFBFF,
+0xFFFFFDFF,
+0xFFF7FDFB,
+0xFFF9FFFD,
+0xFFFCFFFB,
+0xFFFFFFFB,
+0xFFFFFDFF,
+0xFFFFFBFF,
+0xFFFFFDFF,
+0xFFEFFFFF,
+0xFF74ACC7,
+0xFF3486AC,
+0xFF3494BE,
+0xFF0F76A3,
+0xFF05729D,
+0xFF0773A1,
+0xFF07749F,
+0xFF08739F,
+0xFF08739F,
+0xFF08739F,
+0xFF08739F,
+0xFF08739F,
+0xFF09729F,
+0xFF09729F,
+0xFF066F9C,
+0xFF09709B,
+0xFF09709B,
+0xFF076E99,
+0xFF086D99,
+0xFF096E9A,
+0xFF0C6E9B,
+0xFF096E9A,
+0xFF067098,
+0xFF086F98,
+0xFF0C6D9A,
+0xFF0F6B9A,
+0xFF0D6C9A,
+0xFF0B6C99,
+0xFF076E9B,
+0xFF066D98,
+0xFF096C96,
+0xFF0B6C97,
+0xFF086892,
+0xFF096A95,
+0xFF086D99,
+0xFF1C83B0,
+0xFF1379A9,
+0xFF217097,
+0xFFE4FFFF,
+0xFFF9FFFF,
+0xFFFFFFFF,
+0xFFFFFFFB,
+0xFFFFFFFA,
+0xFFFEFFFB,
+0xFFFEFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFEFFFB,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFEFFFD,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFFFDFF,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFEFFFD,
+0xFFFDFFFC,
+0xFFFFFFFF,
+0xFFFFFDFF,
+0xFFF8FDFF,
+0xFFEBFFFF,
+0xFF123D50,
+0xFF084562,
+0xFF054767,
+0xFF0F4A68,
+0xFF114A67,
+0xFF0E4C65,
+0xFF0E4C65,
+0xFF134963,
+0xFF174964,
+0xFF164964,
+0xFF144A64,
+0xFF124B66,
+0xFF134C67,
+0xFF154A69,
+0xFF164B6A,
+0xFF154C6A,
+0xFF144D6A,
+0xFF154E6B,
+0xFF164F6C,
+0xFF134E6C,
+0xFF134E6C,
+0xFF134E6C,
+0xFF134E6C,
+0xFF144F6D,
+0xFF144F6D,
+0xFF145170,
+0xFF155271,
+0xFF145170,
+0xFF145170,
+0xFF135271,
+0xFF145372,
+0xFF155475,
+0xFF155475,
+0xFF145374,
+0xFF125373,
+0xFF125476,
+0xFF105576,
+0xFF135577,
+0xFF135577,
+0xFF145678,
+0xFF145678,
+0xFF16567A,
+0xFF16567A,
+0xFF145679,
+0xFF15577A,
+0xFF16577D,
+0xFF14587D,
+0xFF13597D,
+0xFF115A7D,
+0xFF11597F,
+0xFF10597C,
+0xFF13597B,
+0xFF145A7C,
+0xFF165A7F,
+0xFF155A81,
+0xFF115C83,
+0xFF0E5D84,
+0xFF0C5E83,
+0xFF0D5F84,
+0xFF125E82,
+0xFF145E81,
+0xFF165F82,
+0xFF155F84,
+0xFF115F85,
+0xFF105F86,
+0xFF0F6187,
+0xFF10628A,
+0xFF0E6189,
+0xFF095B81,
+0xFF004D6E,
+0xFF0C526C,
+0xFF073B50,
+0xFF95B6C5,
+0xFFF4FFFF,
+0xFFF7FBFE,
+0xFFFEFEFC,
+0xFFFFFFFB,
+0xFFFDFFFC,
+0xFFFEFFFF,
+0xFFFBFCFE,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFDFE,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFDFE,
+0xFFFFFFFF,
+0xFFFCFFFF,
+0xFFFEFFFF,
+0xFFFFFDF7,
+0xFFFFFEFC,
+0xFFECFFFF,
+0xFF81AFC9,
+0xFF3986B2,
+0xFF3493C3,
+0xFF1979A3,
+0xFF06668C,
+0xFF0A6A90,
+0xFF0D6990,
+0xFF116593,
+0xFF106492,
+0xFF0C6793,
+0xFF0B6891,
+0xFF0D6A95,
+0xFF0D6A95,
+0xFF0B6B95,
+0xFF0B6B95,
+0xFF0A6B95,
+0xFF0A6B95,
+0xFF0A6B95,
+0xFF0A6B95,
+0xFF0A6D97,
+0xFF0A6D97,
+0xFF0A6D97,
+0xFF0B6E98,
+0xFF0A6F99,
+0xFF0C6E9B,
+0xFF0D6C9C,
+0xFF0C6C9C,
+0xFF067098,
+0xFF057198,
+0xFF096D9E,
+0xFF096D9F,
+0xFF086DA1,
+0xFF0770A0,
+0xFF06719D,
+0xFF047097,
+0xFF086D99,
+0xFF0E709D,
+0xFF096999,
+0xFF3F9AC7,
+0xFF4194BC,
+0xFF4686A2,
+0xFFE7FFFF,
+0xFFF9FFFF,
+0xFFFBFCFF,
+0xFFFFFEFF,
+0xFFFFFFFB,
+0xFFFAFBF5,
+0xFFFFFFFB,
+0xFFFFFFFD,
+0xFFFFFCFF,
+0xFFFFFDFF,
+0xFFFFFEFF,
+0xFFFCFFFF,
+0xFFFCFFFD,
+0xFFFEFFFD,
+0xFFFFFEFF,
+0xFFFFFCFF,
+0xFFFFFAFE,
+0xFFFFFDFF,
+0xFFFCFFFF,
+0xFFF9FFFF,
+0xFFF8FDF9,
+0xFFFFFFFD,
+0xFFFFFDFF,
+0xFFFFFDFF,
+0xFFF9FEFF,
+0xFFE9FFFF,
+0xFF2D7395,
+0xFF2A89B5,
+0xFF2B8DBA,
+0xFF046B98,
+0xFF0873A1,
+0xFF04709E,
+0xFF08739F,
+0xFF08739F,
+0xFF08719E,
+0xFF08719E,
+0xFF07709D,
+0xFF07709D,
+0xFF066F9C,
+0xFF066F9C,
+0xFF086F9A,
+0xFF09709B,
+0xFF086F9A,
+0xFF086D99,
+0xFF086D99,
+0xFF096E9A,
+0xFF0B6D9A,
+0xFF096E9A,
+0xFF097099,
+0xFF097099,
+0xFF0C6D9A,
+0xFF0C6B99,
+0xFF0B6C99,
+0xFF096B98,
+0xFF076C9A,
+0xFF076C98,
+0xFF0A6B96,
+0xFF0A6995,
+0xFF0D6D97,
+0xFF0B6A96,
+0xFF1274A1,
+0xFF2689B3,
+0xFF1E7AA3,
+0xFF74B6D8,
+0xFFEDFFFF,
+0xFFFEFFFF,
+0xFFFFFEFF,
+0xFFFFFFFB,
+0xFFFFFFFA,
+0xFFFEFFFB,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFDFF,
+0xFFFFFEFF,
+0xFFFEFFFD,
+0xFFFCFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFBFFFF,
+0xFFFCFFFF,
+0xFFFFFDFF,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFEFFFD,
+0xFFFEFFFD,
+0xFFFCFEFD,
+0xFFFEFFFF,
+0xFFF3FFFF,
+0xFF9EBFD0,
+0xFF05374E,
+0xFF094663,
+0xFF0A496A,
+0xFF124968,
+0xFF124A65,
+0xFF0C4C65,
+0xFF0E4C65,
+0xFF134965,
+0xFF164765,
+0xFF164966,
+0xFF144A66,
+0xFF124B66,
+0xFF134C67,
+0xFF154B67,
+0xFF164C68,
+0xFF154C6A,
+0xFF154C6A,
+0xFF154E6B,
+0xFF154E6B,
+0xFF164F6C,
+0xFF154E6B,
+0xFF154E6C,
+0xFF154E6C,
+0xFF144F6D,
+0xFF144F6D,
+0xFF14516E,
+0xFF14516E,
+0xFF145170,
+0xFF145170,
+0xFF135271,
+0xFF135271,
+0xFF145372,
+0xFF145372,
+0xFF145372,
+0xFF135472,
+0xFF125474,
+0xFF125474,
+0xFF135577,
+0xFF135577,
+0xFF145678,
+0xFF145678,
+0xFF155578,
+0xFF165679,
+0xFF16567A,
+0xFF15577A,
+0xFF15567C,
+0xFF16577D,
+0xFF14587D,
+0xFF14587D,
+0xFF14587D,
+0xFF13597D,
+0xFF13597B,
+0xFF13597B,
+0xFF15597E,
+0xFF155A81,
+0xFF125C83,
+0xFF0F5D83,
+0xFF0E5E83,
+0xFF0E5E83,
+0xFF125E82,
+0xFF125E82,
+0xFF145E81,
+0xFF146082,
+0xFF106083,
+0xFF0D6183,
+0xFF0D6384,
+0xFF0C6587,
+0xFF0D6287,
+0xFF13678C,
+0xFF075B80,
+0xFF004B6F,
+0xFF084768,
+0xFF0E3D57,
+0xFF93AEBF,
+0xFFF4FFFF,
+0xFFFCFFFF,
+0xFFFAF9F5,
+0xFFFFFFFB,
+0xFFFCFBF9,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFDFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFEFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFDFA,
+0xFFFFFFFD,
+0xFFF9FFFF,
+0xFFCCECFF,
+0xFF3079A4,
+0xFF2888BA,
+0xFF2A8DB6,
+0xFF056C8F,
+0xFF066990,
+0xFF0A6A94,
+0xFF0F6693,
+0xFF106794,
+0xFF0C6793,
+0xFF0B6893,
+0xFF096993,
+0xFF0A6A94,
+0xFF0B6A96,
+0xFF0C6B97,
+0xFF0B6C97,
+0xFF0A6B96,
+0xFF0B6C97,
+0xFF0B6C97,
+0xFF096C96,
+0xFF096C96,
+0xFF076C98,
+0xFF076C98,
+0xFF096E9A,
+0xFF0B6D9A,
+0xFF0F6B9A,
+0xFF0D6E9B,
+0xFF077198,
+0xFF067298,
+0xFF096E9C,
+0xFF086C9D,
+0xFF086E9E,
+0xFF07709D,
+0xFF047097,
+0xFF047096,
+0xFF076E99,
+0xFF0C6E9B,
+0xFF1778A5,
+0xFF3B94BE,
+0xFF3C87A7,
+0xFF7DB1C7,
+0xFFF1FFFF,
+0xFFFCFDFF,
+0xFFF9FDFF,
+0xFFFEFFFF,
+0xFFFFFFFD,
+0xFFFFFEFA,
+0xFFFFFFFA,
+0xFFFFFCFB,
+0xFFFFFDFF,
+0xFFFFFDFF,
+0xFFFFFEFF,
+0xFFFEFFFF,
+0xFFFBFFFB,
+0xFFFCFFFB,
+0xFFFFFEFF,
+0xFFFFFCFF,
+0xFFFFFBFF,
+0xFFFFFDFF,
+0xFFFDFEFF,
+0xFFF9FFFF,
+0xFFFCFFFF,
+0xFFFFFFFF,
+0xFFFCFAFF,
+0xFFFAFDFF,
+0xFFF2FFFF,
+0xFF99C3D9,
+0xFF2578A0,
+0xFF248DBD,
+0xFF1579AA,
+0xFF086D9B,
+0xFF066F9C,
+0xFF0A73A0,
+0xFF07709D,
+0xFF07709D,
+0xFF09709B,
+0xFF086F9A,
+0xFF086F9A,
+0xFF086F9A,
+0xFF076E99,
+0xFF076E99,
+0xFF096E9A,
+0xFF0A6F9B,
+0xFF096E98,
+0xFF0B6E98,
+0xFF0B6E98,
+0xFF0B6E98,
+0xFF0D6E99,
+0xFF0B6E98,
+0xFF0B6E98,
+0xFF0B6E98,
+0xFF0A6C99,
+0xFF096B9A,
+0xFF096B98,
+0xFF096B98,
+0xFF076C98,
+0xFF096B98,
+0xFF0E6B97,
+0xFF0D6A95,
+0xFF0D6D97,
+0xFF066791,
+0xFF2687B2,
+0xFF2C88AF,
+0xFF287295,
+0xFFC8FAFF,
+0xFFF4FFFF,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFFFFFB,
+0xFFFFFFFB,
+0xFFFFFFFB,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFEFFFF,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFFFFFF,
+0xFFFFFDFF,
+0xFFFFFDFF,
+0xFFFFFFFD,
+0xFFFCFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFCFFFF,
+0xFFFEFFFF,
+0xFFFFFDFF,
+0xFFFFFDFF,
+0xFFFEFFFF,
+0xFFFCFFFD,
+0xFFFBFDF8,
+0xFFFCFFFF,
+0xFFFBFFFF,
+0xFFF1FFFF,
+0xFF305B6E,
+0xFF084059,
+0xFF094867,
+0xFF094665,
+0xFF134867,
+0xFF134965,
+0xFF0E4C65,
+0xFF0D4B64,
+0xFF124864,
+0xFF164765,
+0xFF164966,
+0xFF144A66,
+0xFF124B66,
+0xFF124B66,
+0xFF154B67,
+0xFF154B67,
+0xFF154C6A,
+0xFF154C6A,
+0xFF144D6A,
+0xFF154E6B,
+0xFF164F6C,
+0xFF154E6B,
+0xFF154E6C,
+0xFF154E6C,
+0xFF134E6C,
+0xFF144F6D,
+0xFF13506D,
+0xFF13506D,
+0xFF145170,
+0xFF145170,
+0xFF125170,
+0xFF135271,
+0xFF135271,
+0xFF145372,
+0xFF145372,
+0xFF145372,
+0xFF135474,
+0xFF125474,
+0xFF135577,
+0xFF135577,
+0xFF145678,
+0xFF145678,
+0xFF155578,
+0xFF155578,
+0xFF16567A,
+0xFF15577A,
+0xFF15567C,
+0xFF15567C,
+0xFF15567C,
+0xFF16577D,
+0xFF14587D,
+0xFF14587B,
+0xFF10597A,
+0xFF115A7B,
+0xFF125B7C,
+0xFF125B7E,
+0xFF125C81,
+0xFF115C83,
+0xFF0F5D83,
+0xFF0F5D83,
+0xFF0F5D81,
+0xFF125E82,
+0xFF145E83,
+0xFF145E81,
+0xFF135F81,
+0xFF0E6181,
+0xFF0B6482,
+0xFF0A6582,
+0xFF0F6588,
+0xFF0D6186,
+0xFF0F628A,
+0xFF0F5E87,
+0xFF02476E,
+0xFF094464,
+0xFF09364D,
+0xFF86A3B1,
+0xFFF0FFFF,
+0xFFFBFFFF,
+0xFFFBFBF9,
+0xFFFFFEFD,
+0xFFFFFEFF,
+0xFFFFFDFF,
+0xFFFFFAFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFDFEFF,
+0xFFFEFFFF,
+0xFFFDFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFEEFFFF,
+0xFF5493BC,
+0xFF227CAE,
+0xFF278EB7,
+0xFF087299,
+0xFF02688E,
+0xFF0B6B95,
+0xFF0F6894,
+0xFF116895,
+0xFF0D6894,
+0xFF0C6994,
+0xFF0B6893,
+0xFF096993,
+0xFF096894,
+0xFF0B6A96,
+0xFF0B6A96,
+0xFF0B6C97,
+0xFF0C6D98,
+0xFF0B6C97,
+0xFF0B6C97,
+0xFF096C96,
+0xFF096B98,
+0xFF066B97,
+0xFF096B98,
+0xFF0A6B98,
+0xFF0E6A99,
+0xFF0C6D98,
+0xFF077198,
+0xFF067298,
+0xFF096E9A,
+0xFF0B6D9C,
+0xFF086F9C,
+0xFF07719B,
+0xFF056F96,
+0xFF087299,
+0xFF066F9C,
+0xFF056C99,
+0xFF298BB8,
+0xFF368EB2,
+0xFF367892,
+0xFFC8EFFF,
+0xFFF6FFFF,
+0xFFFEFEFE,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFBFBF9,
+0xFFFFFFFB,
+0xFFFFFFFB,
+0xFFFFFDFC,
+0xFFFFFDFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFEFFFF,
+0xFFFBFFFD,
+0xFFFCFFFD,
+0xFFFFFEFF,
+0xFFFFFDFF,
+0xFFFFFCFE,
+0xFFFFFEFF,
+0xFFFAFBFD,
+0xFFFCFFFF,
+0xFFFEFFFF,
+0xFFFCFDFF,
+0xFFFFFEFF,
+0xFFF7FFFF,
+0xFFE7FFFF,
+0xFF3C7892,
+0xFF2483AF,
+0xFF1785B6,
+0xFF0A70A0,
+0xFF0C6E9D,
+0xFF0A719E,
+0xFF056C99,
+0xFF086F9C,
+0xFF086F9C,
+0xFF086F9A,
+0xFF086F9A,
+0xFF086F9A,
+0xFF086F9A,
+0xFF086F9A,
+0xFF086F9A,
+0xFF0A6F9B,
+0xFF0A6F9B,
+0xFF0C6F99,
+0xFF0B6E98,
+0xFF0B6E98,
+0xFF0B6E98,
+0xFF0C6D98,
+0xFF0C6D98,
+0xFF0B6A96,
+0xFF0A6B96,
+0xFF096B9A,
+0xFF076C9A,
+0xFF076C98,
+0xFF076C98,
+0xFF096B98,
+0xFF0C6B97,
+0xFF0F6A96,
+0xFF0C6793,
+0xFF0D6A95,
+0xFF0E6E98,
+0xFF3794BD,
+0xFF3383A8,
+0xFF5B94B1,
+0xFFE6FFFF,
+0xFFF8FFFF,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFFFFFB,
+0xFFFEFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFEFFFF,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFEFFFF,
+0xFFFFFDFF,
+0xFFFFFDFF,
+0xFFFFFFFD,
+0xFFFEFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFCFFFF,
+0xFFFCFFFB,
+0xFFFEFFFA,
+0xFFFCFFFF,
+0xFFF5FFFF,
+0xFFD2ECFD,
+0xFF0A3953,
+0xFF0D4A67,
+0xFF084562,
+0xFF134F6B,
+0xFF134965,
+0xFF134963,
+0xFF104964,
+0xFF104964,
+0xFF114866,
+0xFF134867,
+0xFF134867,
+0xFF134A68,
+0xFF134B66,
+0xFF134B66,
+0xFF144A66,
+0xFF154B67,
+0xFF144C67,
+0xFF154D68,
+0xFF154C6A,
+0xFF154C6A,
+0xFF164D6B,
+0xFF164D6B,
+0xFF154E6B,
+0xFF154E6B,
+0xFF134E6C,
+0xFF134E6C,
+0xFF13506D,
+0xFF13506D,
+0xFF14516E,
+0xFF14516E,
+0xFF145170,
+0xFF145170,
+0xFF155271,
+0xFF155271,
+0xFF165372,
+0xFF145372,
+0xFF125373,
+0xFF135474,
+0xFF145575,
+0xFF145575,
+0xFF135577,
+0xFF145678,
+0xFF135577,
+0xFF135577,
+0xFF155779,
+0xFF155779,
+0xFF15577A,
+0xFF15577A,
+0xFF15577A,
+0xFF16587B,
+0xFF17597C,
+0xFF145A7C,
+0xFF0F5B7B,
+0xFF0C5D7B,
+0xFF0C5D7B,
+0xFF0E5D7E,
+0xFF115D7F,
+0xFF125C81,
+0xFF115D81,
+0xFF115D81,
+0xFF0F5D83,
+0xFF105E82,
+0xFF145C82,
+0xFF175C83,
+0xFF175D81,
+0xFF145E81,
+0xFF0D627F,
+0xFF0A6381,
+0xFF09607E,
+0xFF12668A,
+0xFF126188,
+0xFF145F89,
+0xFF0D567F,
+0xFF01456A,
+0xFF04415E,
+0xFF0A3A4E,
+0xFF7494A1,
+0xFFF2FFFF,
+0xFFF9FFFF,
+0xFFFDFDFF,
+0xFFFCFCFE,
+0xFFFFFDFF,
+0xFFFFFEFF,
+0xFFFFFDFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFDFDFF,
+0xFFFEFFFF,
+0xFFFCFFFF,
+0xFFFEFFFF,
+0xFFFFFDFC,
+0xFFF5FFFF,
+0xFFA8DAFB,
+0xFF1E6F9A,
+0xFF1E83AF,
+0xFF0E7BA4,
+0xFF02688E,
+0xFF0C6C92,
+0xFF116A94,
+0xFF0E6791,
+0xFF0E6A93,
+0xFF0E6A93,
+0xFF0D6894,
+0xFF0B6893,
+0xFF0B6893,
+0xFF0B6893,
+0xFF0C6994,
+0xFF0B6B95,
+0xFF0C6C96,
+0xFF0C6C96,
+0xFF0C6B97,
+0xFF0B6C97,
+0xFF0A6B96,
+0xFF096C96,
+0xFF096A95,
+0xFF096A95,
+0xFF0D6A96,
+0xFF0A6B95,
+0xFF076F94,
+0xFF076F94,
+0xFF0B6E98,
+0xFF0C6D9A,
+0xFF0A6F9B,
+0xFF0A6F99,
+0xFF0A7096,
+0xFF0A7299,
+0xFF046F9D,
+0xFF05719F,
+0xFF258FB9,
+0xFF348AAB,
+0xFF568AA0,
+0xFFECFFFF,
+0xFFF9FFFF,
+0xFFFFFFFD,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFEFDFB,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFC,
+0xFFFFFDFE,
+0xFFFEFEFF,
+0xFFFEFFFF,
+0xFFFBFBFB,
+0xFFFEFFFF,
+0xFFFCFFFF,
+0xFFEAFEFF,
+0xFFB5E7FE,
+0xFF1C6B8C,
+0xFF157FA9,
+0xFF0B7BAB,
+0xFF086E9E,
+0xFF0A6C9B,
+0xFF066B99,
+0xFF0A6F9D,
+0xFF0A6F9B,
+0xFF0A6F9B,
+0xFF0A6F9B,
+0xFF0A6F9B,
+0xFF0A6F9B,
+0xFF0A6F9B,
+0xFF0A6F99,
+0xFF0A6F99,
+0xFF0B6E98,
+0xFF0B6E98,
+0xFF0B6E98,
+0xFF0B6E98,
+0xFF0B6C97,
+0xFF0B6C97,
+0xFF0A6B96,
+0xFF0B6A96,
+0xFF0C6994,
+0xFF0A6995,
+0xFF0A6A9A,
+0xFF096B9A,
+0xFF096B98,
+0xFF096C96,
+0xFF0A6B96,
+0xFF0B6B95,
+0xFF0F6894,
+0xFF0B648E,
+0xFF0C6793,
+0xFF2A86AF,
+0xFF3B93B9,
+0xFF387D9E,
+0xFFB8DEF1,
+0xFFF2FFFF,
+0xFFFBFFFF,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFEFFFF,
+0xFFFEFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFCFFFF,
+0xFFFEFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFCFFFF,
+0xFFFCFFFB,
+0xFFFBFEF7,
+0xFFFBFFFF,
+0xFFF2FFFF,
+0xFF6A8A9F,
+0xFF0B405F,
+0xFF0D4C6D,
+0xFF0C4965,
+0xFF0F4B65,
+0xFF134963,
+0xFF134963,
+0xFF124864,
+0xFF114964,
+0xFF104966,
+0xFF114A67,
+0xFF114A67,
+0xFF134A68,
+0xFF134B66,
+0xFF144A66,
+0xFF144A66,
+0xFF134B66,
+0xFF144C67,
+0xFF154D68,
+0xFF154C6A,
+0xFF154C6A,
+0xFF164D6B,
+0xFF164D6B,
+0xFF154E6B,
+0xFF154E6B,
+0xFF134E6C,
+0xFF134E6C,
+0xFF124F6C,
+0xFF124F6C,
+0xFF14516E,
+0xFF14516E,
+0xFF145170,
+0xFF145170,
+0xFF145170,
+0xFF155271,
+0xFF165372,
+0xFF165372,
+0xFF145374,
+0xFF135474,
+0xFF135474,
+0xFF145575,
+0xFF135577,
+0xFF135577,
+0xFF135577,
+0xFF115677,
+0xFF125778,
+0xFF125778,
+0xFF13577A,
+0xFF15577A,
+0xFF15577A,
+0xFF16587B,
+0xFF16587B,
+0xFF145A7C,
+0xFF0F5B7D,
+0xFF0C5C7D,
+0xFF0D5C7B,
+0xFF105C7C,
+0xFF115C7C,
+0xFF125C7F,
+0xFF125C7F,
+0xFF115D81,
+0xFF0F5D83,
+0xFF0F5D83,
+0xFF145C84,
+0xFF165B82,
+0xFF185C83,
+0xFF155E81,
+0xFF106081,
+0xFF0D6281,
+0xFF0C6180,
+0xFF0F6284,
+0xFF136187,
+0xFF17628A,
+0xFF146289,
+0xFF145F86,
+0xFF004869,
+0xFF06435F,
+0xFF0E3D51,
+0xFF6A8A99,
+0xFFF1FFFF,
+0xFFF8FFFF,
+0xFFFCFFFF,
+0xFFFFFFFF,
+0xFFFFFDFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFBFFFF,
+0xFFFDFEFF,
+0xFFFFFDFD,
+0xFFF8FDFF,
+0xFFE1FFFF,
+0xFF2A6E93,
+0xFF1577A4,
+0xFF1180AD,
+0xFF066A8E,
+0xFF0A688A,
+0xFF0D6990,
+0xFF0E6791,
+0xFF0D6992,
+0xFF0D6992,
+0xFF0E6A93,
+0xFF0E6995,
+0xFF0C6994,
+0xFF0B6893,
+0xFF0B6893,
+0xFF0B6893,
+0xFF0A6A94,
+0xFF0A6A94,
+0xFF0A6A94,
+0xFF0B6B95,
+0xFF0B6C97,
+0xFF0B6C97,
+0xFF0A6B96,
+0xFF0B6A96,
+0xFF096894,
+0xFF096A95,
+0xFF066C92,
+0xFF076D93,
+0xFF0A6B96,
+0xFF0C6B99,
+0xFF0A6D97,
+0xFF0B6E97,
+0xFF0B6D94,
+0xFF096E98,
+0xFF006F9D,
+0xFF0C7FAE,
+0xFF1A8AB2,
+0xFF1B7290,
+0xFFA4CADF,
+0xFFF5FFFF,
+0xFFF9FDFF,
+0xFFFCFCFA,
+0xFFFCFEFB,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFBFBFB,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFCFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFDFFFE,
+0xFFFFFFFF,
+0xFFFEFEFF,
+0xFFFEFEFE,
+0xFFFEFFFF,
+0xFFF4FCFF,
+0xFFE9FFFF,
+0xFF5396B3,
+0xFF16769E,
+0xFF1483AE,
+0xFF0374A0,
+0xFF066C9C,
+0xFF0D6D9D,
+0xFF086A99,
+0xFF1072A1,
+0xFF0D6F9C,
+0xFF0D6F9C,
+0xFF0C6E9B,
+0xFF0A6F9B,
+0xFF0A6F9B,
+0xFF096E9A,
+0xFF096E98,
+0xFF096E98,
+0xFF0A6D97,
+0xFF0A6D97,
+0xFF096C96,
+0xFF0A6D97,
+0xFF0A6B96,
+0xFF096A95,
+0xFF096A95,
+0xFF0A6A94,
+0xFF0D6A93,
+0xFF0D6A95,
+0xFF0B6A9A,
+0xFF0A6A9A,
+0xFF0A6B96,
+0xFF096A94,
+0xFF096A94,
+0xFF096991,
+0xFF0E6791,
+0xFF0D648F,
+0xFF0F6894,
+0xFF4198C3,
+0xFF408FB6,
+0xFF4B87A3,
+0xFFEDFFFF,
+0xFFF9FEFF,
+0xFFFCFFFF,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFD,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFCFFFF,
+0xFFFBFFFF,
+0xFFFCFFFB,
+0xFFFFFFF8,
+0xFFFAFFFE,
+0xFFF0FFFF,
+0xFF173D54,
+0xFF134B6C,
+0xFF0F4F72,
+0xFF0D4A66,
+0xFF114B63,
+0xFF124A63,
+0xFF134963,
+0xFF164765,
+0xFF154865,
+0xFF114A67,
+0xFF0E4B67,
+0xFF0F4B67,
+0xFF114A67,
+0xFF144A66,
+0xFF164966,
+0xFF134B66,
+0xFF134B66,
+0xFF144C67,
+0xFF164C68,
+0xFF164B6A,
+0xFF154A69,
+0xFF154C6A,
+0xFF154C6A,
+0xFF154E6B,
+0xFF154E6B,
+0xFF134F6B,
+0xFF14506C,
+0xFF13506D,
+0xFF13506D,
+0xFF13506D,
+0xFF14516E,
+0xFF145170,
+0xFF155271,
+0xFF145170,
+0xFF155271,
+0xFF155271,
+0xFF165372,
+0xFF165274,
+0xFF145374,
+0xFF145374,
+0xFF135474,
+0xFF125474,
+0xFF135575,
+0xFF115677,
+0xFF115677,
+0xFF115677,
+0xFF115878,
+0xFF115878,
+0xFF125778,
+0xFF13577A,
+0xFF13577A,
+0xFF14587B,
+0xFF13597D,
+0xFF125A80,
+0xFF11597F,
+0xFF13577C,
+0xFF16587B,
+0xFF14587B,
+0xFF125B7C,
+0xFF115D7D,
+0xFF0F5E7F,
+0xFF0F5D81,
+0xFF115C83,
+0xFF125B84,
+0xFF145B85,
+0xFF145B85,
+0xFF135E85,
+0xFF106085,
+0xFF0E6183,
+0xFF106083,
+0xFF116184,
+0xFF0B5E7E,
+0xFF126587,
+0xFF0E5E81,
+0xFF126287,
+0xFF176387,
+0xFF004668,
+0xFF0B4865,
+0xFF06394E,
+0xFF618794,
+0xFFECFFFF,
+0xFFF5FFFF,
+0xFFFCFFFF,
+0xFFFCFBF9,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFDFF,
+0xFFFFFEFF,
+0xFFFEFFFD,
+0xFFFCFFFD,
+0xFFFCFFFF,
+0xFFFCFDFF,
+0xFFFFFEFD,
+0xFFFBFEFF,
+0xFFEBFFFF,
+0xFF639AB8,
+0xFF0D6D9D,
+0xFF0F7DAE,
+0xFF096B8E,
+0xFF096685,
+0xFF0C6689,
+0xFF0F6890,
+0xFF0C688F,
+0xFF0C688F,
+0xFF0D6990,
+0xFF0D6992,
+0xFF0C6992,
+0xFF0C6992,
+0xFF0B6891,
+0xFF0A6790,
+0xFF0B6891,
+0xFF0B6891,
+0xFF096991,
+0xFF0A6A92,
+0xFF0B6B95,
+0xFF0B6B95,
+0xFF0B6B95,
+0xFF0B6A96,
+0xFF0A6997,
+0xFF096A97,
+0xFF096C95,
+0xFF096C95,
+0xFF0A6997,
+0xFF0A6997,
+0xFF0B6A96,
+0xFF0C6B97,
+0xFF0D6894,
+0xFF096B98,
+0xFF0171A3,
+0xFF0D85B7,
+0xFF0C83AD,
+0xFF1E7795,
+0xFFE4FFFF,
+0xFFFEFEFF,
+0xFFFDFEFF,
+0xFFFEFFFD,
+0xFFFFFFFD,
+0xFFFFFEFC,
+0xFFFDFDFD,
+0xFFFEFEFF,
+0xFFFCFFFF,
+0xFFFEFFFF,
+0xFFFFFFFB,
+0xFFFFFFFB,
+0xFFFFFEFD,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFFFFFF,
+0xFFFCFAFB,
+0xFFFFFEFC,
+0xFFFDFFFE,
+0xFFF8FFFF,
+0xFFE0FFFF,
+0xFF0F6186,
+0xFF0B77A5,
+0xFF0778A0,
+0xFF006F97,
+0xFF0A6F9D,
+0xFF0C6C9E,
+0xFF1171A1,
+0xFF056595,
+0xFF0C6D9A,
+0xFF0B6D9A,
+0xFF0B6D9A,
+0xFF0B6D9A,
+0xFF0A6D97,
+0xFF0A6D97,
+0xFF0A6D97,
+0xFF0A6D97,
+0xFF096C96,
+0xFF086B95,
+0xFF096C96,
+0xFF0A6D97,
+0xFF0B6C96,
+0xFF096A94,
+0xFF096A94,
+0xFF0B6B95,
+0xFF0D6A93,
+0xFF0E6A93,
+0xFF0D6998,
+0xFF0C6897,
+0xFF0C6994,
+0xFF096991,
+0xFF086A91,
+0xFF09698F,
+0xFF0D6990,
+0xFF0F678F,
+0xFF257CA7,
+0xFF499AC5,
+0xFF448CB4,
+0xFF8DBFDA,
+0xFFF4FFFF,
+0xFFFFFFFA,
+0xFFFCFFFB,
+0xFFFCFFFD,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFB,
+0xFFFFFDFD,
+0xFFFFFEFF,
+0xFFFCFFFF,
+0xFFFBFFFF,
+0xFFFCFFFB,
+0xFFFFFEF9,
+0xFFF9FFFF,
+0xFF9DBACC,
+0xFF13425E,
+0xFF175375,
+0xFF09496C,
+0xFF124F6B,
+0xFF0F4961,
+0xFF104A62,
+0xFF134963,
+0xFF164765,
+0xFF154865,
+0xFF0F4B67,
+0xFF0E4B67,
+0xFF0F4B67,
+0xFF114A67,
+0xFF144A66,
+0xFF144A66,
+0xFF134B66,
+0xFF124B66,
+0xFF144C67,
+0xFF154D68,
+0xFF154A69,
+0xFF144B69,
+0xFF154C6A,
+0xFF154C6A,
+0xFF154E6B,
+0xFF154E6B,
+0xFF134F6B,
+0xFF14506C,
+0xFF13506D,
+0xFF13506D,
+0xFF13506D,
+0xFF14516E,
+0xFF145170,
+0xFF155271,
+0xFF155271,
+0xFF155271,
+0xFF155271,
+0xFF165372,
+0xFF165274,
+0xFF145374,
+0xFF145374,
+0xFF135474,
+0xFF125474,
+0xFF125474,
+0xFF115677,
+0xFF115677,
+0xFF105576,
+0xFF105777,
+0xFF105777,
+0xFF115878,
+0xFF125679,
+0xFF13577A,
+0xFF13577A,
+0xFF12587A,
+0xFF145980,
+0xFF13587F,
+0xFF16567C,
+0xFF16567A,
+0xFF14587B,
+0xFF125B7B,
+0xFF105C7C,
+0xFF0E5D7E,
+0xFF0F5D81,
+0xFF115C83,
+0xFF125B84,
+0xFF125B84,
+0xFF125D85,
+0xFF105E84,
+0xFF115F85,
+0xFF106085,
+0xFF105E82,
+0xFF105E82,
+0xFF126283,
+0xFF0D6080,
+0xFF116486,
+0xFF116186,
+0xFF105F86,
+0xFF156087,
+0xFF024B6C,
+0xFF0A4C66,
+0xFF073F50,
+0xFF577F89,
+0xFFEEFFFF,
+0xFFF6FFFF,
+0xFFFEFFFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFDFF,
+0xFFFFFCFD,
+0xFFFEFFFD,
+0xFFFAFFFC,
+0xFFFBFFFF,
+0xFFFCFEFD,
+0xFFFFFEFF,
+0xFFFEFFFF,
+0xFFF3FFFF,
+0xFFADD7EF,
+0xFF0A638F,
+0xFF0973A3,
+0xFF0D6D93,
+0xFF0E6988,
+0xFF0B6588,
+0xFF0E688D,
+0xFF0F6890,
+0xFF0C688F,
+0xFF0B678E,
+0xFF0B678E,
+0xFF0D6992,
+0xFF0D6A93,
+0xFF0D6992,
+0xFF0B6891,
+0xFF0C6992,
+0xFF0B6891,
+0xFF0A6790,
+0xFF086890,
+0xFF0B6891,
+0xFF0A6A92,
+0xFF0D6A95,
+0xFF0B6B95,
+0xFF0B6A98,
+0xFF0C6B99,
+0xFF0C6D98,
+0xFF0A6B96,
+0xFF096A97,
+0xFF096896,
+0xFF0A6995,
+0xFF0E6B97,
+0xFF0F6A97,
+0xFF066897,
+0xFF0074A7,
+0xFF097FAD,
+0xFF097599,
+0xFF5CA6C1,
+0xFFF0FFFF,
+0xFFFFF9FF,
+0xFFFFFFFF,
+0xFFFDFFFE,
+0xFFFEFDFB,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFDFEFF,
+0xFFFCFFFF,
+0xFFFAFEFD,
+0xFFFFFFFD,
+0xFFFFFFFB,
+0xFFFFFEFD,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFCFFFF,
+0xFFFBFFFF,
+0xFFF8FCFD,
+0xFFFFFDFE,
+0xFFFFFEFD,
+0xFFFFFEFB,
+0xFFF9FFFF,
+0xFFF1FFFF,
+0xFF81B1C5,
+0xFF0E6995,
+0xFF0474A6,
+0xFF05759D,
+0xFF047097,
+0xFF086D99,
+0xFF0C6E9D,
+0xFF076797,
+0xFF10719E,
+0xFF0A6B98,
+0xFF0A6B98,
+0xFF096B98,
+0xFF096C96,
+0xFF096C96,
+0xFF096C96,
+0xFF0A6B96,
+0xFF096C96,
+0xFF0A6B96,
+0xFF086B95,
+0xFF0A6B96,
+0xFF0B6C97,
+0xFF0B6C96,
+0xFF0A6B95,
+0xFF0B6B95,
+0xFF0C6C96,
+0xFF0C6992,
+0xFF0D6992,
+0xFF0C6794,
+0xFF0C6794,
+0xFF0B6893,
+0xFF0B6891,
+0xFF09698F,
+0xFF0C6A90,
+0xFF0D698E,
+0xFF0C648A,
+0xFF489BC5,
+0xFF4D97BE,
+0xFF4B83A6,
+0xFFE1FFFF,
+0xFFF7FFFF,
+0xFFFFFFF8,
+0xFFFEFFFB,
+0xFFFCFFFD,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFEFFFF,
+0xFFFCFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFEFCFF,
+0xFFFFF9F7,
+0xFFFFFDFB,
+0xFFFFFEFF,
+0xFFF9FAFE,
+0xFFFCFFFF,
+0xFFFCFEFB,
+0xFFFFFEFF,
+0xFFF7FFFF,
+0xFF37607E,
+0xFF165277,
+0xFF135275,
+0xFF0D4C6B,
+0xFF0A4763,
+0xFF0F4B65,
+0xFF114A65,
+0xFF124A65,
+0xFF114964,
+0xFF114964,
+0xFF104964,
+0xFF0E4A64,
+0xFF114A65,
+0xFF114A65,
+0xFF124A65,
+0xFF134B66,
+0xFF124B66,
+0xFF124B66,
+0xFF124B66,
+0xFF124B66,
+0xFF144C67,
+0xFF144D68,
+0xFF144D6A,
+0xFF144D6A,
+0xFF144D6A,
+0xFF154E6B,
+0xFF14506C,
+0xFF14506C,
+0xFF144F6D,
+0xFF134E6C,
+0xFF124F6E,
+0xFF13506F,
+0xFF125170,
+0xFF125170,
+0xFF125172,
+0xFF125172,
+0xFF135273,
+0xFF145374,
+0xFF135271,
+0xFF135472,
+0xFF145573,
+0xFF145573,
+0xFF115373,
+0xFF105272,
+0xFF125474,
+0xFF125776,
+0xFF115677,
+0xFF115677,
+0xFF125778,
+0xFF125778,
+0xFF12587A,
+0xFF12587A,
+0xFF13597B,
+0xFF13597B,
+0xFF12587A,
+0xFF13597B,
+0xFF15597C,
+0xFF15597C,
+0xFF13597B,
+0xFF10597A,
+0xFF105A7D,
+0xFF105C7E,
+0xFF115D7F,
+0xFF125E82,
+0xFF125E82,
+0xFF115C83,
+0xFF115C83,
+0xFF105E82,
+0xFF115F83,
+0xFF126084,
+0xFF135E85,
+0xFF135E85,
+0xFF126084,
+0xFF126084,
+0xFF126086,
+0xFF116186,
+0xFF126188,
+0xFF126188,
+0xFF106083,
+0xFF075472,
+0xFF084E67,
+0xFF0B4457,
+0xFF4D757F,
+0xFFEBFFFF,
+0xFFF9FFFF,
+0xFFFFFEFF,
+0xFFFFFCF9,
+0xFFFFFEFB,
+0xFFFFFFFD,
+0xFFFCFAFB,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFEFE,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFEFD,
+0xFFFFFEFD,
+0xFFFEFFFF,
+0xFFFBFFFF,
+0xFFFBFFFF,
+0xFFFCFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFBFEFF,
+0xFFE7FFFF,
+0xFF0F5B7F,
+0xFF0B6E98,
+0xFF0A6A94,
+0xFF0B678E,
+0xFF10688E,
+0xFF0E668C,
+0xFF0F678F,
+0xFF0E678F,
+0xFF0E678F,
+0xFF0E678F,
+0xFF0E678F,
+0xFF0C688F,
+0xFF0F6890,
+0xFF0D6990,
+0xFF0F6B94,
+0xFF0F6B94,
+0xFF0E6A93,
+0xFF0B6891,
+0xFF0B6790,
+0xFF0B6891,
+0xFF0D6992,
+0xFF0C6994,
+0xFF0D6A95,
+0xFF096894,
+0xFF0B6A98,
+0xFF0A6B98,
+0xFF096C96,
+0xFF0C6F99,
+0xFF0F6F99,
+0xFF0B6894,
+0xFF0A6695,
+0xFF076D9D,
+0xFF0579AA,
+0xFF05729B,
+0xFF1A6781,
+0xFFC4F2FF,
+0xFFF6FFFF,
+0xFFFFFDFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFCFFFF,
+0xFFFBFCFE,
+0xFFFFFEFB,
+0xFFFFFEFA,
+0xFFFFFFFA,
+0xFFF3FFFF,
+0xFFE3FFFF,
+0xFF23637F,
+0xFF0D6C9C,
+0xFF0570A6,
+0xFF086F9A,
+0xFF066C94,
+0xFF076C96,
+0xFF096E98,
+0xFF0B6D9A,
+0xFF096B98,
+0xFF0A6B98,
+0xFF0A6B96,
+0xFF0A6B96,
+0xFF0B6C97,
+0xFF0A6B96,
+0xFF0A6B95,
+0xFF0B6B95,
+0xFF096A94,
+0xFF0C6C96,
+0xFF0B6C96,
+0xFF0C6C96,
+0xFF0C6C96,
+0xFF0C6C96,
+0xFF0B6B95,
+0xFF0C6994,
+0xFF0A6A94,
+0xFF0B6893,
+0xFF0B6893,
+0xFF0E6995,
+0xFF0B6692,
+0xFF086892,
+0xFF0C6C96,
+0xFF0F6892,
+0xFF106890,
+0xFF0E688D,
+0xFF1A7296,
+0xFF53A5CA,
+0xFF5799B9,
+0xFF7EA4BB,
+0xFFEDFFFF,
+0xFFF9FFFF,
+0xFFFBFDF8,
+0xFFFEFFFD,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFDFEFF,
+0xFFFFFFFF,
+0xFFFFFDFB,
+0xFFFFFAF8,
+0xFFFFFEFF,
+0xFFFEFFFF,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFFFEFF,
+0xFFD6E6F6,
+0xFF144566,
+0xFF16567C,
+0xFF175677,
+0xFF104D69,
+0xFF0E4A64,
+0xFF114D65,
+0xFF104964,
+0xFF104964,
+0xFF114964,
+0xFF104964,
+0xFF114964,
+0xFF114A65,
+0xFF124A65,
+0xFF114A65,
+0xFF124A65,
+0xFF124B66,
+0xFF134B66,
+0xFF124B66,
+0xFF134B66,
+0xFF124B66,
+0xFF144C67,
+0xFF134C67,
+0xFF154C6A,
+0xFF144D6A,
+0xFF154C6A,
+0xFF154E6B,
+0xFF154E6B,
+0xFF14506C,
+0xFF164F6D,
+0xFF134E6C,
+0xFF134E6E,
+0xFF13506F,
+0xFF13506F,
+0xFF125170,
+0xFF145072,
+0xFF125172,
+0xFF155173,
+0xFF135273,
+0xFF135271,
+0xFF135472,
+0xFF155473,
+0xFF135472,
+0xFF125373,
+0xFF115373,
+0xFF135474,
+0xFF135575,
+0xFF125476,
+0xFF105576,
+0xFF115677,
+0xFF115677,
+0xFF125679,
+0xFF115779,
+0xFF13577A,
+0xFF12587A,
+0xFF135879,
+0xFF135A7A,
+0xFF15597C,
+0xFF13597B,
+0xFF13597B,
+0xFF10597A,
+0xFF115A7D,
+0xFF105A7D,
+0xFF125C7F,
+0xFF115D7F,
+0xFF125E82,
+0xFF115D81,
+0xFF115D81,
+0xFF0F5D81,
+0xFF105E82,
+0xFF115F83,
+0xFF135E85,
+0xFF135E85,
+0xFF145F86,
+0xFF145F86,
+0xFF115F85,
+0xFF115F85,
+0xFF116087,
+0xFF0F6189,
+0xFF13678C,
+0xFF0F6284,
+0xFF045371,
+0xFF0C526B,
+0xFF0E4257,
+0xFF4E7383,
+0xFFEFFFFF,
+0xFFF6FDFF,
+0xFFFFFFFF,
+0xFFFDF9F6,
+0xFFFFFEFC,
+0xFFFFFFFD,
+0xFFFDFDFD,
+0xFFFCFCFC,
+0xFFFEFEFE,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFEFD,
+0xFFFFFEFD,
+0xFFFEFFFF,
+0xFFFBFFFF,
+0xFFF9FFFF,
+0xFFFCFFFF,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFDFF,
+0xFFECFFFF,
+0xFF256A87,
+0xFF0A668D,
+0xFF096691,
+0xFF096490,
+0xFF0E668C,
+0xFF0F648B,
+0xFF0E668C,
+0xFF0E668E,
+0xFF0D668E,
+0xFF0D668E,
+0xFF0E678F,
+0xFF0E678F,
+0xFF0E678F,
+0xFF0E678F,
+0xFF0D6992,
+0xFF0E6A93,
+0xFF0E6A93,
+0xFF0D6992,
+0xFF0C6891,
+0xFF0D6992,
+0xFF0D6992,
+0xFF0D6992,
+0xFF09668F,
+0xFF0B6893,
+0xFF0C6B99,
+0xFF0B6C99,
+0xFF076A94,
+0xFF096A94,
+0xFF0C6C96,
+0xFF0D6A95,
+0xFF0F6E9C,
+0xFF056C99,
+0xFF00709C,
+0xFF0B6D90,
+0xFF3D788A,
+0xFFEBFFFF,
+0xFFF8FCFF,
+0xFFFFFDFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFAFEFF,
+0xFFFEFFFF,
+0xFFFFFCF9,
+0xFFFFFBF7,
+0xFFFDFEF9,
+0xFFF1FFFF,
+0xFFADDDF1,
+0xFF0E587B,
+0xFF09679A,
+0xFF056DA4,
+0xFF0A6C9B,
+0xFF096A94,
+0xFF076A91,
+0xFF076D95,
+0xFF096C96,
+0xFF076996,
+0xFF0A6B96,
+0xFF0A6B96,
+0xFF0B6C97,
+0xFF0B6C97,
+0xFF0C6C96,
+0xFF0C6C96,
+0xFF0C6C96,
+0xFF0C6C96,
+0xFF0B6B95,
+0xFF0B6B95,
+0xFF0B6B95,
+0xFF0A6A94,
+0xFF0C6994,
+0xFF0B6893,
+0xFF0B6893,
+0xFF0B6893,
+0xFF0A6A94,
+0xFF0A6792,
+0xFF106993,
+0xFF0C6891,
+0xFF0A6A94,
+0xFF0C6992,
+0xFF0F6892,
+0xFF0E668E,
+0xFF096187,
+0xFF4397BC,
+0xFF509FC0,
+0xFF5790AB,
+0xFFC9E5F3,
+0xFFF8FFFF,
+0xFFFAFFFF,
+0xFFFCFFFD,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFEFD,
+0xFFFEFAF9,
+0xFFFEFFFF,
+0xFFFAFEFF,
+0xFFF8FDF9,
+0xFFFBFFFF,
+0xFFF7FFFF,
+0xFF738D9E,
+0xFF184967,
+0xFF1E5A7C,
+0xFF114D69,
+0xFF0C465E,
+0xFF124A61,
+0xFF124A61,
+0xFF114962,
+0xFF114964,
+0xFF134965,
+0xFF124A65,
+0xFF134965,
+0xFF124A65,
+0xFF134965,
+0xFF114964,
+0xFF134965,
+0xFF124A65,
+0xFF144A66,
+0xFF134B66,
+0xFF144A66,
+0xFF134B66,
+0xFF154B67,
+0xFF144C67,
+0xFF164C68,
+0xFF154D68,
+0xFF164C68,
+0xFF154D68,
+0xFF164D6B,
+0xFF154E6B,
+0xFF174E6C,
+0xFF164F6C,
+0xFF154E6C,
+0xFF134E6C,
+0xFF144F6F,
+0xFF13506F,
+0xFF155070,
+0xFF155271,
+0xFF165171,
+0xFF155271,
+0xFF155271,
+0xFF135271,
+0xFF165372,
+0xFF145372,
+0xFF145374,
+0xFF135474,
+0xFF145374,
+0xFF135474,
+0xFF135376,
+0xFF125476,
+0xFF125476,
+0xFF135577,
+0xFF135577,
+0xFF125778,
+0xFF145679,
+0xFF125679,
+0xFF155779,
+0xFF135879,
+0xFF16587B,
+0xFF14587B,
+0xFF14587B,
+0xFF13597B,
+0xFF13597B,
+0xFF10597A,
+0xFF125B7E,
+0xFF115B7E,
+0xFF125C7F,
+0xFF125C7F,
+0xFF125C81,
+0xFF115D81,
+0xFF115D81,
+0xFF115D81,
+0xFF135D84,
+0xFF145E85,
+0xFF135F83,
+0xFF135F83,
+0xFF115F83,
+0xFF115F85,
+0xFF105F86,
+0xFF0E6088,
+0xFF0C6188,
+0xFF0C6186,
+0xFF0E6286,
+0xFF105C7C,
+0xFF12536F,
+0xFF0F425D,
+0xFF476C86,
+0xFFEBFFFF,
+0xFFF6FFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFEFEFC,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFAFAFA,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFEFFFD,
+0xFFFBFFFD,
+0xFFF9FFFF,
+0xFFFCFFFF,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFEFFFFF,
+0xFF4888A3,
+0xFF085E81,
+0xFF086189,
+0xFF0A638B,
+0xFF0D658B,
+0xFF10658C,
+0xFF0D658B,
+0xFF0D658B,
+0xFF0E668E,
+0xFF0E668E,
+0xFF0F678F,
+0xFF0F678F,
+0xFF0E678F,
+0xFF0E678F,
+0xFF0D668E,
+0xFF0E678F,
+0xFF0D6992,
+0xFF0D6992,
+0xFF0D6992,
+0xFF0E6A93,
+0xFF0D6992,
+0xFF0D6992,
+0xFF09668F,
+0xFF0B6891,
+0xFF0B6B95,
+0xFF0A6995,
+0xFF0C6995,
+0xFF0A6792,
+0xFF086892,
+0xFF0A6B95,
+0xFF096894,
+0xFF086B95,
+0xFF046E95,
+0xFF09607E,
+0xFF97C6D8,
+0xFFF1FFFF,
+0xFFFBFFFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFFFDFE,
+0xFFFFFFFD,
+0xFFFBFFFF,
+0xFFEDFFFF,
+0xFF447C93,
+0xFF0C5C81,
+0xFF086495,
+0xFF05699D,
+0xFF0A6C9B,
+0xFF096C96,
+0xFF086A8F,
+0xFF096B90,
+0xFF086B95,
+0xFF086A97,
+0xFF0A6B96,
+0xFF0C6C96,
+0xFF0C6C96,
+0xFF0C6C96,
+0xFF0C6C96,
+0xFF0C6C96,
+0xFF0B6B95,
+0xFF0B6B95,
+0xFF0C6994,
+0xFF0C6994,
+0xFF0B6893,
+0xFF0B6893,
+0xFF0B6893,
+0xFF0B6893,
+0xFF0B6893,
+0xFF0C6994,
+0xFF0E6B94,
+0xFF0B6891,
+0xFF106993,
+0xFF0F6892,
+0xFF116A92,
+0xFF0A668D,
+0xFF0D6990,
+0xFF0A638B,
+0xFF126790,
+0xFF54A3CA,
+0xFF589FBF,
+0xFF6498B0,
+0xFFEDFFFF,
+0xFFF7FFFF,
+0xFFFAFEFD,
+0xFFFDFFFC,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFEFC,
+0xFFFFFFFF,
+0xFFFCFFFF,
+0xFFF9FEFF,
+0xFFFCFFFF,
+0xFFF8FFFF,
+0xFFE9FFFF,
+0xFF1E4459,
+0xFF265C78,
+0xFF1F5C79,
+0xFF104964,
+0xFF124A61,
+0xFF154D64,
+0xFF10465E,
+0xFF124864,
+0xFF124864,
+0xFF134965,
+0xFF134965,
+0xFF134965,
+0xFF134965,
+0xFF124864,
+0xFF124864,
+0xFF134965,
+0xFF134965,
+0xFF144A66,
+0xFF144A66,
+0xFF144A66,
+0xFF144A66,
+0xFF144A66,
+0xFF154B67,
+0xFF164C68,
+0xFF164C68,
+0xFF164C68,
+0xFF164C68,
+0xFF154C6A,
+0xFF164D6B,
+0xFF164D6B,
+0xFF174E6C,
+0xFF164F6D,
+0xFF154E6C,
+0xFF134E6E,
+0xFF144F6F,
+0xFF155070,
+0xFF165171,
+0xFF155070,
+0xFF155070,
+0xFF145170,
+0xFF145170,
+0xFF155173,
+0xFF165274,
+0xFF145374,
+0xFF145374,
+0xFF145374,
+0xFF135273,
+0xFF135376,
+0xFF145477,
+0xFF135577,
+0xFF135577,
+0xFF145678,
+0xFF145679,
+0xFF145679,
+0xFF15577A,
+0xFF15577A,
+0xFF15577A,
+0xFF15577A,
+0xFF16587B,
+0xFF15597C,
+0xFF15597C,
+0xFF13597B,
+0xFF13597D,
+0xFF10597C,
+0xFF115A7D,
+0xFF115B7E,
+0xFF125C81,
+0xFF125C81,
+0xFF125C81,
+0xFF115D81,
+0xFF115C83,
+0xFF125D84,
+0xFF125D84,
+0xFF135E85,
+0xFF115F83,
+0xFF115F83,
+0xFF115F85,
+0xFF115F86,
+0xFF105F88,
+0xFF0E6189,
+0xFF10658C,
+0xFF0D6287,
+0xFF0D5D82,
+0xFF115A7B,
+0xFF165576,
+0xFF0E4363,
+0xFF486D87,
+0xFFEDFFFF,
+0xFFF8FFFF,
+0xFFF9FDFE,
+0xFFFCFCFA,
+0xFFFFFEFC,
+0xFFFFFFFD,
+0xFFFCFDFF,
+0xFFFCFDFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFEFFFD,
+0xFFFCFFFD,
+0xFFFBFFFF,
+0xFFFCFFFF,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFF1FFFF,
+0xFF6EA6BF,
+0xFF065576,
+0xFF075C81,
+0xFF0A6489,
+0xFF0F648B,
+0xFF10658C,
+0xFF0E638A,
+0xFF0D658B,
+0xFF0D658D,
+0xFF0E668E,
+0xFF0E668E,
+0xFF0E668E,
+0xFF0D668E,
+0xFF0D668E,
+0xFF0D668E,
+0xFF0E678F,
+0xFF0D6992,
+0xFF0D6992,
+0xFF0D6992,
+0xFF0D6992,
+0xFF0D6992,
+0xFF0D6990,
+0xFF0C6A90,
+0xFF0D6B91,
+0xFF086890,
+0xFF0A6792,
+0xFF126897,
+0xFF0F6795,
+0xFF07678F,
+0xFF096B92,
+0xFF096993,
+0xFF08668C,
+0xFF076485,
+0xFF0F5770,
+0xFFE5FFFF,
+0xFFF3FDFF,
+0xFFFCFFFF,
+0xFFFDFDFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFCFFFF,
+0xFFF8FCFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFF5FFFF,
+0xFFD9FBFF,
+0xFF0F4F6A,
+0xFF0D6088,
+0xFF086493,
+0xFF07699A,
+0xFF0A6C9B,
+0xFF0A6D97,
+0xFF0B6B91,
+0xFF0B6C8F,
+0xFF0A6B96,
+0xFF0B6C97,
+0xFF0B6A96,
+0xFF0B6B95,
+0xFF0B6B95,
+0xFF0A6A94,
+0xFF0A6A94,
+0xFF0A6A94,
+0xFF096993,
+0xFF096993,
+0xFF0B6893,
+0xFF0B6893,
+0xFF0B6893,
+0xFF0B6893,
+0xFF0C6994,
+0xFF0C6994,
+0xFF0D6A95,
+0xFF0D6A93,
+0xFF0E6C92,
+0xFF0D6990,
+0xFF0F6894,
+0xFF0E6590,
+0xFF136891,
+0xFF0C648A,
+0xFF0D6990,
+0xFF07638A,
+0xFF2E83AC,
+0xFF539EC5,
+0xFF5693B2,
+0xFFA3CEE1,
+0xFFF1FFFF,
+0xFFF7FDFD,
+0xFFFEFFFF,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFEFE,
+0xFFFFFFFF,
+0xFFFEFEFE,
+0xFFFEFFFF,
+0xFFFAFFFF,
+0xFFFBFFFF,
+0xFFFAFFFF,
+0xFFF1FFFF,
+0xFF9BC1D4,
+0xFF154B65,
+0xFF25617D,
+0xFF195673,
+0xFF0C4965,
+0xFF0F4B65,
+0xFF124B66,
+0xFF124A65,
+0xFF124766,
+0xFF124766,
+0xFF134867,
+0xFF134867,
+0xFF134867,
+0xFF134867,
+0xFF124766,
+0xFF124766,
+0xFF134867,
+0xFF134867,
+0xFF134867,
+0xFF134867,
+0xFF144968,
+0xFF144968,
+0xFF144968,
+0xFF144968,
+0xFF144B69,
+0xFF144B69,
+0xFF144B69,
+0xFF154C6A,
+0xFF154C6B,
+0xFF154C6B,
+0xFF154E6C,
+0xFF164F6D,
+0xFF164E6F,
+0xFF154D6E,
+0xFF134E6E,
+0xFF134E6E,
+0xFF144F71,
+0xFF155072,
+0xFF145072,
+0xFF145072,
+0xFF145072,
+0xFF145072,
+0xFF145074,
+0xFF155175,
+0xFF145376,
+0xFF145376,
+0xFF145376,
+0xFF135275,
+0xFF145478,
+0xFF145478,
+0xFF135578,
+0xFF135578,
+0xFF145679,
+0xFF14557B,
+0xFF14557B,
+0xFF15567C,
+0xFF15567C,
+0xFF14557B,
+0xFF12567B,
+0xFF13577C,
+0xFF15597E,
+0xFF165A7F,
+0xFF145A7E,
+0xFF13587F,
+0xFF10587E,
+0xFF10587E,
+0xFF105A7F,
+0xFF115B82,
+0xFF115C83,
+0xFF115C83,
+0xFF115C83,
+0xFF115C83,
+0xFF0F5C86,
+0xFF0E5D86,
+0xFF0F5E85,
+0xFF106085,
+0xFF116184,
+0xFF126084,
+0xFF145F86,
+0xFF135E85,
+0xFF0E5D84,
+0xFF0D5F85,
+0xFF14668C,
+0xFF17678C,
+0xFF115D81,
+0xFF195F83,
+0xFF1C5B7E,
+0xFF114260,
+0xFF8EADC1,
+0xFFF2FFFF,
+0xFFF9FEFF,
+0xFFFFFFFD,
+0xFFFFFEFA,
+0xFFFFFFFD,
+0xFFFEFFFF,
+0xFFFBFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFEFFFD,
+0xFFFCFFFD,
+0xFFFCFFFF,
+0xFFFEFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFEFEFE,
+0xFFF1FFFF,
+0xFF8FBDD4,
+0xFF064B6A,
+0xFF065677,
+0xFF0B6085,
+0xFF0E638A,
+0xFF0E638C,
+0xFF0E638A,
+0xFF0E638A,
+0xFF0F648B,
+0xFF0F648B,
+0xFF0E668C,
+0xFF0E668C,
+0xFF0E668E,
+0xFF0E668E,
+0xFF0E678F,
+0xFF0D668E,
+0xFF0D668E,
+0xFF0E678F,
+0xFF0E678F,
+0xFF0E678F,
+0xFF0F6890,
+0xFF0D6990,
+0xFF0D6B91,
+0xFF0D6B8F,
+0xFF08688E,
+0xFF0B6790,
+0xFF146897,
+0xFF136796,
+0xFF096991,
+0xFF0A6C91,
+0xFF06668C,
+0xFF055E80,
+0xFF095670,
+0xFF6198AC,
+0xFFF0FFFF,
+0xFFFCFFFF,
+0xFFFEFFFF,
+0xFFFDFFFE,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFFFFFF,
+0xFFF6FEFF,
+0xFFEEFFFF,
+0xFF77A2B2,
+0xFF0D5676,
+0xFF055E86,
+0xFF0B6894,
+0xFF096A97,
+0xFF096B98,
+0xFF0A6B96,
+0xFF0C6A90,
+0xFF0D6B8F,
+0xFF0B6A96,
+0xFF0B6A96,
+0xFF096894,
+0xFF096993,
+0xFF0B6893,
+0xFF0B6893,
+0xFF0B6893,
+0xFF0B6893,
+0xFF0B6893,
+0xFF0B6893,
+0xFF0C6992,
+0xFF0C6992,
+0xFF0D6992,
+0xFF0E6A93,
+0xFF0E6A93,
+0xFF0E6A93,
+0xFF0E6A93,
+0xFF0E6A93,
+0xFF0C688D,
+0xFF0D6990,
+0xFF0F6894,
+0xFF0F6391,
+0xFF13668E,
+0xFF0F6489,
+0xFF0D678C,
+0xFF0A668D,
+0xFF4198C3,
+0xFF519BC2,
+0xFF51839E,
+0xFFE6FFFF,
+0xFFF5FFFF,
+0xFFFBFFFE,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFCFDFF,
+0xFFF9FDFF,
+0xFFFAFFFF,
+0xFFF5FCFF,
+0xFFEEFFFF,
+0xFF376980,
+0xFF21627E,
+0xFF21617D,
+0xFF0D4A66,
+0xFF0E4B68,
+0xFF0C4864,
+0xFF104966,
+0xFF124967,
+0xFF124766,
+0xFF134867,
+0xFF134867,
+0xFF134867,
+0xFF134867,
+0xFF124766,
+0xFF124766,
+0xFF124766,
+0xFF134867,
+0xFF134867,
+0xFF134867,
+0xFF134867,
+0xFF144968,
+0xFF144968,
+0xFF144968,
+0xFF144968,
+0xFF144B69,
+0xFF144B69,
+0xFF144B69,
+0xFF154C6A,
+0xFF154C6A,
+0xFF154C6B,
+0xFF154E6C,
+0xFF154E6C,
+0xFF164F6D,
+0xFF154D6E,
+0xFF134E6E,
+0xFF134E6E,
+0xFF144F6F,
+0xFF144F6F,
+0xFF145072,
+0xFF145072,
+0xFF134F71,
+0xFF145072,
+0xFF145074,
+0xFF155175,
+0xFF145376,
+0xFF145376,
+0xFF145376,
+0xFF145376,
+0xFF135376,
+0xFF135376,
+0xFF135377,
+0xFF135578,
+0xFF135578,
+0xFF135578,
+0xFF14557B,
+0xFF145679,
+0xFF15567C,
+0xFF14557B,
+0xFF14557B,
+0xFF13577C,
+0xFF14587D,
+0xFF15597E,
+0xFF15597E,
+0xFF145A7E,
+0xFF13587F,
+0xFF10587E,
+0xFF11597F,
+0xFF105A7F,
+0xFF115B82,
+0xFF115D81,
+0xFF115C83,
+0xFF115C83,
+0xFF0F5C86,
+0xFF0E5D86,
+0xFF0F5E85,
+0xFF0D5F84,
+0xFF106083,
+0xFF126182,
+0xFF155F82,
+0xFF155F84,
+0xFF135E85,
+0xFF156389,
+0xFF0C5C81,
+0xFF136388,
+0xFF115F85,
+0xFF155F84,
+0xFF15597C,
+0xFF1F5778,
+0xFF204861,
+0xFFE8FFFF,
+0xFFF9FFFF,
+0xFFFFFEFA,
+0xFFFFFFFA,
+0xFFFFFFFB,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFCFFFD,
+0xFFFCFFFF,
+0xFFFEFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFEFEFC,
+0xFFF4FFFF,
+0xFFA7CDE0,
+0xFF084460,
+0xFF055270,
+0xFF0B5F81,
+0xFF0F628A,
+0xFF0F628C,
+0xFF0E638A,
+0xFF0E638A,
+0xFF0F648B,
+0xFF0F648B,
+0xFF0D658B,
+0xFF0D658B,
+0xFF0D658D,
+0xFF0D658D,
+0xFF0F678F,
+0xFF0D668E,
+0xFF0C658D,
+0xFF0D668E,
+0xFF0D668E,
+0xFF0D668E,
+0xFF0E678F,
+0xFF0D6990,
+0xFF0B678C,
+0xFF0C6A8E,
+0xFF0C6A8E,
+0xFF0E678F,
+0xFF136595,
+0xFF126695,
+0xFF0C6992,
+0xFF0C6D90,
+0xFF005C7E,
+0xFF075876,
+0xFF0D4A5F,
+0xFFC9EFFC,
+0xFFF6FFFF,
+0xFFFFFEFF,
+0xFFFDFDFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFF7FFFF,
+0xFFE7FFFF,
+0xFF154C61,
+0xFF055475,
+0xFF015D86,
+0xFF0D6A95,
+0xFF0B6A96,
+0xFF096A95,
+0xFF096993,
+0xFF0B698F,
+0xFF0C688F,
+0xFF0B6893,
+0xFF086793,
+0xFF096993,
+0xFF096993,
+0xFF0B6893,
+0xFF0B6893,
+0xFF0B6893,
+0xFF0C6994,
+0xFF0C6994,
+0xFF0D6A95,
+0xFF0C6992,
+0xFF0D6A93,
+0xFF0E6A93,
+0xFF0E6A93,
+0xFF0E6A93,
+0xFF0D6992,
+0xFF0C6891,
+0xFF0B678E,
+0xFF0A668B,
+0xFF0E688D,
+0xFF0E6791,
+0xFF106490,
+0xFF14668E,
+0xFF11648C,
+0xFF0B658A,
+0xFF167299,
+0xFF449BC6,
+0xFF488DB4,
+0xFF82A8BF,
+0xFFF1FFFF,
+0xFFF8FFFF,
+0xFFFEFFFD,
+0xFFFFFEFC,
+0xFFFEFDFB,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFD,
+0xFFFFFCFB,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFAFFFF,
+0xFFF7FFFF,
+0xFFC7E2F7,
+0xFF144D68,
+0xFF1E6382,
+0xFF1B5B77,
+0xFF094561,
+0xFF144F6D,
+0xFF164F6D,
+0xFF164B6A,
+0xFF114463,
+0xFF134965,
+0xFF124A65,
+0xFF124A65,
+0xFF114964,
+0xFF114964,
+0xFF114964,
+0xFF114964,
+0xFF114964,
+0xFF124A65,
+0xFF124A65,
+0xFF124A65,
+0xFF124A65,
+0xFF134B66,
+0xFF134B66,
+0xFF134B66,
+0xFF124A65,
+0xFF134B66,
+0xFF144C67,
+0xFF144C67,
+0xFF154D68,
+0xFF154D68,
+0xFF154C6A,
+0xFF164D6B,
+0xFF164D6B,
+0xFF154E6B,
+0xFF154E6C,
+0xFF154E6C,
+0xFF154E6C,
+0xFF134E6C,
+0xFF144F6D,
+0xFF144F6F,
+0xFF155070,
+0xFF13506F,
+0xFF13506F,
+0xFF145072,
+0xFF145072,
+0xFF155173,
+0xFF155173,
+0xFF145374,
+0xFF145374,
+0xFF145374,
+0xFF135474,
+0xFF135376,
+0xFF135376,
+0xFF145477,
+0xFF145477,
+0xFF145478,
+0xFF145477,
+0xFF155579,
+0xFF145679,
+0xFF145679,
+0xFF145679,
+0xFF15577A,
+0xFF13577A,
+0xFF14587B,
+0xFF13597B,
+0xFF145A7E,
+0xFF115A7D,
+0xFF115A7D,
+0xFF0F597C,
+0xFF105A7F,
+0xFF115B7E,
+0xFF125C81,
+0xFF115D81,
+0xFF115C84,
+0xFF0F5D84,
+0xFF0E5E83,
+0xFF0F5F82,
+0xFF116081,
+0xFF135F7F,
+0xFF155E7F,
+0xFF155E7F,
+0xFF145D80,
+0xFF176186,
+0xFF115D81,
+0xFF105F80,
+0xFF1A6688,
+0xFF135E7E,
+0xFF196283,
+0xFF21607F,
+0xFF1D4A67,
+0xFFB4D0E5,
+0xFFF5FEFF,
+0xFFFFFFFB,
+0xFFFFFCF8,
+0xFFFEFAF7,
+0xFFFCFFFF,
+0xFFF8FDFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFEFD,
+0xFFFFFFFD,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFEFFFD,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFDFF,
+0xFFFFFEFF,
+0xFFFFFFFB,
+0xFFF5FFFF,
+0xFFB2D3E4,
+0xFF0B3F57,
+0xFF024C67,
+0xFF0A5D7D,
+0xFF0F6388,
+0xFF0F628C,
+0xFF10638B,
+0xFF10638B,
+0xFF0F648B,
+0xFF0F648B,
+0xFF0F648B,
+0xFF0F648B,
+0xFF0F648B,
+0xFF0D658B,
+0xFF0E668C,
+0xFF0D658B,
+0xFF0C648C,
+0xFF0D658D,
+0xFF0E668E,
+0xFF0E668E,
+0xFF0D668E,
+0xFF0C688F,
+0xFF0A668B,
+0xFF0B698D,
+0xFF0F698C,
+0xFF0F678D,
+0xFF106492,
+0xFF126695,
+0xFF0F6890,
+0xFF086587,
+0xFF005A79,
+0xFF054F68,
+0xFF3C6778,
+0xFFEFFFFF,
+0xFFFBFFFF,
+0xFFFDFBFE,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFDFDFF,
+0xFFFFFFFF,
+0xFFFEFEFC,
+0xFFF4FFFF,
+0xFFA2CCDC,
+0xFF094964,
+0xFF045477,
+0xFF046087,
+0xFF0B6B95,
+0xFF0A6A94,
+0xFF0B6893,
+0xFF0B6891,
+0xFF0D6990,
+0xFF0C688F,
+0xFF0B6893,
+0xFF0A6793,
+0xFF0C6994,
+0xFF0C6992,
+0xFF0D6992,
+0xFF0D6992,
+0xFF0D6992,
+0xFF0E6A93,
+0xFF0E6A93,
+0xFF0F6B94,
+0xFF0D6992,
+0xFF0D6992,
+0xFF0F6892,
+0xFF0F6892,
+0xFF0E6791,
+0xFF0E6791,
+0xFF0E678F,
+0xFF0D668E,
+0xFF0D678C,
+0xFF0D678C,
+0xFF0C658D,
+0xFF0E668E,
+0xFF12638E,
+0xFF11638B,
+0xFF0B6389,
+0xFF2D86AE,
+0xFF3F96C1,
+0xFF4387AA,
+0xFFCDEAFC,
+0xFFF4FBFF,
+0xFFFAFEFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFD,
+0xFFFFFEFF,
+0xFFFEFCFD,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFF9FDFF,
+0xFFF2FFFF,
+0xFF6A8CA5,
+0xFF1A5774,
+0xFF1F6682,
+0xFF124F6B,
+0xFF114A65,
+0xFF0F4866,
+0xFF114867,
+0xFF144565,
+0xFF174866,
+0xFF134965,
+0xFF124A65,
+0xFF114964,
+0xFF114964,
+0xFF114964,
+0xFF114964,
+0xFF114964,
+0xFF124A65,
+0xFF124A65,
+0xFF124A65,
+0xFF114964,
+0xFF124A65,
+0xFF134B66,
+0xFF134B66,
+0xFF134B66,
+0xFF124A65,
+0xFF124A65,
+0xFF134B66,
+0xFF144C67,
+0xFF154D68,
+0xFF154D68,
+0xFF154D68,
+0xFF154C6A,
+0xFF154E6B,
+0xFF154E6B,
+0xFF154E6B,
+0xFF164F6D,
+0xFF134E6C,
+0xFF134E6C,
+0xFF134E6C,
+0xFF144F6D,
+0xFF15506E,
+0xFF13506F,
+0xFF13506F,
+0xFF145170,
+0xFF145170,
+0xFF145072,
+0xFF155173,
+0xFF145374,
+0xFF155475,
+0xFF145374,
+0xFF145374,
+0xFF135474,
+0xFF135474,
+0xFF145477,
+0xFF145477,
+0xFF145477,
+0xFF145477,
+0xFF165679,
+0xFF155578,
+0xFF145678,
+0xFF135578,
+0xFF135578,
+0xFF145679,
+0xFF13577A,
+0xFF14587B,
+0xFF165C7E,
+0xFF145A7C,
+0xFF115A7B,
+0xFF10597A,
+0xFF115A7D,
+0xFF115C7C,
+0xFF125C7F,
+0xFF125C7F,
+0xFF125C81,
+0xFF125C81,
+0xFF0E5C80,
+0xFF0F5E7F,
+0xFF105F7E,
+0xFF125E7E,
+0xFF145F7F,
+0xFF145D7E,
+0xFF176083,
+0xFF105A7F,
+0xFF166286,
+0xFF126084,
+0xFF105F80,
+0xFF126182,
+0xFF176282,
+0xFF1E6080,
+0xFF205171,
+0xFF86A5BA,
+0xFFF7FFFF,
+0xFFFEFDF9,
+0xFFFFFEFA,
+0xFFFFFDFA,
+0xFFFBFFFF,
+0xFFFBFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFEFB,
+0xFFFFFFFD,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFEFFFD,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFDFF,
+0xFFFFFEFF,
+0xFFFEFFFA,
+0xFFF7FFFF,
+0xFFB6D3E3,
+0xFF0A3A51,
+0xFF014761,
+0xFF095A78,
+0xFF0F6187,
+0xFF0D6088,
+0xFF11648C,
+0xFF10638B,
+0xFF10638B,
+0xFF0F648B,
+0xFF0F648B,
+0xFF0F648B,
+0xFF0F648B,
+0xFF0F648B,
+0xFF0F648B,
+0xFF0C648A,
+0xFF0C648C,
+0xFF0D658D,
+0xFF0E668E,
+0xFF0E668E,
+0xFF0E668E,
+0xFF0D668E,
+0xFF0D698E,
+0xFF0B678C,
+0xFF0E688B,
+0xFF0E668C,
+0xFF0E6592,
+0xFF116796,
+0xFF0D658D,
+0xFF045A7D,
+0xFF004E6C,
+0xFF07455C,
+0xFF9CB9C7,
+0xFFF7FFFF,
+0xFFFCFFFF,
+0xFFFEFEFE,
+0xFFFFFFFD,
+0xFFFDFCFA,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFEFEFE,
+0xFFFBFDFA,
+0xFFF1FFFF,
+0xFF35657B,
+0xFF044B69,
+0xFF005175,
+0xFF0C688F,
+0xFF096991,
+0xFF096993,
+0xFF0C688F,
+0xFF0D6990,
+0xFF0E6A91,
+0xFF0E6A93,
+0xFF0D6A95,
+0xFF0D6A95,
+0xFF0E6B94,
+0xFF0F6B94,
+0xFF0E6A93,
+0xFF0D6992,
+0xFF0D6992,
+0xFF0D6992,
+0xFF0D6992,
+0xFF0E6A93,
+0xFF0C6891,
+0xFF0C6891,
+0xFF0E6791,
+0xFF0D6690,
+0xFF0E6791,
+0xFF0E6791,
+0xFF0F6890,
+0xFF0F6890,
+0xFF106991,
+0xFF0D668E,
+0xFF08648B,
+0xFF0E668E,
+0xFF0F628C,
+0xFF0F628C,
+0xFF0A638D,
+0xFF3E97BF,
+0xFF398CB4,
+0xFF4F8CAB,
+0xFFEEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFDFCFA,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFCFD,
+0xFFFFFEFF,
+0xFFFBFBFB,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFF8FFFF,
+0xFFEEFFFF,
+0xFF1C4360,
+0xFF2B6884,
+0xFF185B75,
+0xFF104C66,
+0xFF104863,
+0xFF124968,
+0xFF134867,
+0xFF184763,
+0xFF184761,
+0xFF134965,
+0xFF114A65,
+0xFF114A65,
+0xFF114A65,
+0xFF114A65,
+0xFF114A65,
+0xFF114A65,
+0xFF114A65,
+0xFF114A65,
+0xFF114A65,
+0xFF114A65,
+0xFF114A65,
+0xFF114A65,
+0xFF114A65,
+0xFF114A65,
+0xFF114A65,
+0xFF124B66,
+0xFF124B66,
+0xFF124B66,
+0xFF134C67,
+0xFF144D68,
+0xFF144D68,
+0xFF154E6B,
+0xFF134F6B,
+0xFF134F6B,
+0xFF134F6B,
+0xFF134F6B,
+0xFF134F6B,
+0xFF144F6D,
+0xFF13506D,
+0xFF13506D,
+0xFF13506D,
+0xFF13506F,
+0xFF13506F,
+0xFF125170,
+0xFF125170,
+0xFF135271,
+0xFF135271,
+0xFF145372,
+0xFF145372,
+0xFF135271,
+0xFF135271,
+0xFF125373,
+0xFF125373,
+0xFF135474,
+0xFF135474,
+0xFF135474,
+0xFF145575,
+0xFF135575,
+0xFF135575,
+0xFF135575,
+0xFF145678,
+0xFF145678,
+0xFF155779,
+0xFF135879,
+0xFF135879,
+0xFF135A7A,
+0xFF135A7A,
+0xFF135A7A,
+0xFF115A7A,
+0xFF115A7B,
+0xFF115A7A,
+0xFF115A7B,
+0xFF115A7A,
+0xFF15597C,
+0xFF145A7C,
+0xFF125D7D,
+0xFF115D7D,
+0xFF0F5E7D,
+0xFF0F5E7D,
+0xFF115D81,
+0xFF135D82,
+0xFF155F86,
+0xFF125D84,
+0xFF126087,
+0xFF105F86,
+0xFF0E6085,
+0xFF106287,
+0xFF126084,
+0xFF1F6386,
+0xFF205372,
+0xFF8BAABF,
+0xFFF6FFFF,
+0xFFFFFFFB,
+0xFFFFFDF9,
+0xFFFFFEFB,
+0xFFFCFFFF,
+0xFFFAFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFEFB,
+0xFFFFFFFD,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFDFF,
+0xFFFFFEFF,
+0xFFFEFFFB,
+0xFFF5FFFF,
+0xFFB5D1DF,
+0xFF0A384F,
+0xFF054862,
+0xFF0B5A78,
+0xFF14668B,
+0xFF0E6088,
+0xFF10628A,
+0xFF0F6388,
+0xFF0F6388,
+0xFF0F6388,
+0xFF106489,
+0xFF106489,
+0xFF10638B,
+0xFF0E638A,
+0xFF0F648B,
+0xFF0F648B,
+0xFF0F648B,
+0xFF0F648B,
+0xFF0F648B,
+0xFF0D658B,
+0xFF0D658B,
+0xFF0C668B,
+0xFF0A668B,
+0xFF0C688D,
+0xFF0A6487,
+0xFF0F678D,
+0xFF0E6592,
+0xFF0D6491,
+0xFF11668D,
+0xFF004A6B,
+0xFF054A69,
+0xFF07374D,
+0xFFF1FFFF,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFEFFFF,
+0xFFFFFEFD,
+0xFFFFFDFC,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFD,
+0xFFFFFFFD,
+0xFFF9FDFC,
+0xFFDFF6FC,
+0xFF033951,
+0xFF044F6F,
+0xFF015579,
+0xFF0F6B90,
+0xFF0E6C92,
+0xFF0E6C92,
+0xFF0E6A91,
+0xFF106991,
+0xFF0F6890,
+0xFF0D6992,
+0xFF0C6994,
+0xFF0C6994,
+0xFF0D6992,
+0xFF0F6890,
+0xFF0F6890,
+0xFF0E678F,
+0xFF0E678F,
+0xFF0E678F,
+0xFF0D668E,
+0xFF0D668E,
+0xFF0E678F,
+0xFF0E678F,
+0xFF0E668E,
+0xFF0D658D,
+0xFF0D658D,
+0xFF0D658D,
+0xFF0E668E,
+0xFF0D668E,
+0xFF0D668E,
+0xFF0B678E,
+0xFF0B648C,
+0xFF0C648A,
+0xFF0F628C,
+0xFF085F8A,
+0xFF1A77A3,
+0xFF3790BA,
+0xFF357FA2,
+0xFF98CAE3,
+0xFFF4FFFF,
+0xFFFFFEFF,
+0xFFFCFDFF,
+0xFFFEFFFF,
+0xFFFFFFFD,
+0xFFFFFEFC,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFEFE,
+0xFFFDFFFE,
+0xFFFFFFFF,
+0xFFFCFEFD,
+0xFFFCFEFB,
+0xFFF7FFFF,
+0xFF94B0C6,
+0xFF265370,
+0xFF205E77,
+0xFF13556F,
+0xFF0C4A63,
+0xFF0C4864,
+0xFF0E4969,
+0xFF104869,
+0xFF144563,
+0xFF144661,
+0xFF104765,
+0xFF0D4965,
+0xFF0D4965,
+0xFF0D4965,
+0xFF0D4965,
+0xFF0D4965,
+0xFF0D4965,
+0xFF0D4965,
+0xFF0D4965,
+0xFF0D4965,
+0xFF0D4965,
+0xFF0D4965,
+0xFF0D4965,
+0xFF0D4965,
+0xFF0D4965,
+0xFF0D4965,
+0xFF0E4A66,
+0xFF0F4B67,
+0xFF0F4B67,
+0xFF0F4B67,
+0xFF104C68,
+0xFF104C68,
+0xFF104D6A,
+0xFF104D6A,
+0xFF104D6A,
+0xFF104D6A,
+0xFF114E6B,
+0xFF114E6B,
+0xFF114E6D,
+0xFF0F4E6D,
+0xFF0F4E6D,
+0xFF0F4E6D,
+0xFF104F70,
+0xFF104F70,
+0xFF115071,
+0xFF105171,
+0xFF115071,
+0xFF115272,
+0xFF125172,
+0xFF115272,
+0xFF135273,
+0xFF125373,
+0xFF125373,
+0xFF125474,
+0xFF135376,
+0xFF125474,
+0xFF135376,
+0xFF135577,
+0xFF135577,
+0xFF135577,
+0xFF135577,
+0xFF145678,
+0xFF145678,
+0xFF125778,
+0xFF125679,
+0xFF125778,
+0xFF13597B,
+0xFF135A7A,
+0xFF13597B,
+0xFF135A7A,
+0xFF115A7B,
+0xFF115A7A,
+0xFF115A7B,
+0xFF135A7A,
+0xFF17597B,
+0xFF17597B,
+0xFF135C7C,
+0xFF125D7D,
+0xFF115D7D,
+0xFF115D7F,
+0xFF115C83,
+0xFF125D84,
+0xFF155E87,
+0xFF115C84,
+0xFF115F86,
+0xFF105F86,
+0xFF0C5C81,
+0xFF0F5F82,
+0xFF186488,
+0xFF1C5E80,
+0xFF1A4967,
+0xFFBFDBF0,
+0xFFF5FEFF,
+0xFFFFFFFB,
+0xFFFFFEFA,
+0xFFFFFEFB,
+0xFFFAFEFF,
+0xFFFBFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFEFD,
+0xFFFFFFFD,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFDFF,
+0xFFFFFEFF,
+0xFFFCFEF9,
+0xFFF5FFFF,
+0xFFA2BFCF,
+0xFF0B3B52,
+0xFF094C66,
+0xFF0B5A78,
+0xFF116186,
+0xFF116389,
+0xFF106288,
+0xFF106288,
+0xFF0E6287,
+0xFF0E6287,
+0xFF0E6287,
+0xFF0F6388,
+0xFF0F628A,
+0xFF0F628A,
+0xFF0F628A,
+0xFF0F648B,
+0xFF0F648B,
+0xFF0F648B,
+0xFF0F648B,
+0xFF0F648B,
+0xFF0D658B,
+0xFF0D658B,
+0xFF0D678C,
+0xFF0C668B,
+0xFF0B658A,
+0xFF116991,
+0xFF0D6491,
+0xFF136793,
+0xFF075B80,
+0xFF004565,
+0xFF053D58,
+0xFF6C8FA3,
+0xFFF1FEFF,
+0xFFFCFEFD,
+0xFFFBFFFF,
+0xFFFDFFFE,
+0xFFFFFDFC,
+0xFFFFFDFD,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFBFA,
+0xFFFCFCFC,
+0xFFF7FFFF,
+0xFF6E8C96,
+0xFF043D58,
+0xFF004A6C,
+0xFF0B6085,
+0xFF126E95,
+0xFF0D698E,
+0xFF0D698E,
+0xFF0E678F,
+0xFF0E678F,
+0xFF0F678F,
+0xFF0D6690,
+0xFF0B6692,
+0xFF0B6692,
+0xFF0F6892,
+0xFF0E678F,
+0xFF0E678F,
+0xFF0E678F,
+0xFF0D668E,
+0xFF0D668E,
+0xFF0D668E,
+0xFF0E678F,
+0xFF0E678F,
+0xFF0E678F,
+0xFF0E668E,
+0xFF0E668E,
+0xFF0D658D,
+0xFF0D658D,
+0xFF0D658D,
+0xFF0D658D,
+0xFF09658E,
+0xFF08648B,
+0xFF0D668E,
+0xFF0D658D,
+0xFF126790,
+0xFF08618D,
+0xFF2A8CBB,
+0xFF2D86B0,
+0xFF3C7998,
+0xFFDCFFFF,
+0xFFF8FFFF,
+0xFFFFFFFF,
+0xFFFAFEFF,
+0xFFFEFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFD,
+0xFFF9FEFA,
+0xFFFBFDFA,
+0xFFFCFFFD,
+0xFFF9FFFD,
+0xFFEFFFFF,
+0xFF3F637B,
+0xFF275A79,
+0xFF24627B,
+0xFF1B5D77,
+0xFF175874,
+0xFF175979,
+0xFF185A7D,
+0xFF18587C,
+0xFF1C5779,
+0xFF1E5677,
+0xFF1B5877,
+0xFF195877,
+0xFF195877,
+0xFF195877,
+0xFF195877,
+0xFF195877,
+0xFF195877,
+0xFF195877,
+0xFF195877,
+0xFF195877,
+0xFF195877,
+0xFF195877,
+0xFF195877,
+0xFF195877,
+0xFF195877,
+0xFF195877,
+0xFF1C5978,
+0xFF1C5978,
+0xFF1C5978,
+0xFF1C5978,
+0xFF1B5A79,
+0xFF1B5A79,
+0xFF1B5A7B,
+0xFF1B5A7B,
+0xFF1B5A7B,
+0xFF1B5A7B,
+0xFF1B5A7B,
+0xFF1A5B7B,
+0xFF1A5B7B,
+0xFF1A5B7B,
+0xFF1A5B7B,
+0xFF1A5B7B,
+0xFF19597C,
+0xFF19597C,
+0xFF19597C,
+0xFF185A7C,
+0xFF19597C,
+0xFF195B7D,
+0xFF1A5A7D,
+0xFF195B7D,
+0xFF1B5B7E,
+0xFF1A5C7E,
+0xFF1A5C7E,
+0xFF185D7E,
+0xFF1A5C7F,
+0xFF185D7E,
+0xFF1A5C7F,
+0xFF185C7F,
+0xFF195D80,
+0xFF195D80,
+0xFF195D80,
+0xFF195D80,
+0xFF195D80,
+0xFF185E80,
+0xFF185E82,
+0xFF185E80,
+0xFF195F83,
+0xFF195F81,
+0xFF195F83,
+0xFF195F81,
+0xFF176083,
+0xFF176081,
+0xFF176083,
+0xFF195F81,
+0xFF1C5E80,
+0xFF1C5E80,
+0xFF1A6082,
+0xFF176184,
+0xFF156185,
+0xFF166188,
+0xFF176188,
+0xFF176089,
+0xFF155C86,
+0xFF176089,
+0xFF176289,
+0xFF186488,
+0xFF176184,
+0xFF196283,
+0xFF1F6386,
+0xFF265F7D,
+0xFF386079,
+0xFFEDFFFF,
+0xFFF9FFFF,
+0xFFFFFFFB,
+0xFFFFFCF7,
+0xFFFEFDF9,
+0xFFFCFFFF,
+0xFFF9FDFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFEFFFD,
+0xFFF5FFFF,
+0xFF8BACBF,
+0xFF0E415C,
+0xFF0F526F,
+0xFF105C7C,
+0xFF115F83,
+0xFF14638A,
+0xFF106288,
+0xFF106288,
+0xFF0F6187,
+0xFF0F6187,
+0xFF0F6187,
+0xFF0F6187,
+0xFF0F6187,
+0xFF0E6287,
+0xFF0F6388,
+0xFF0F6388,
+0xFF10638B,
+0xFF10638B,
+0xFF0F648B,
+0xFF0F648B,
+0xFF10658C,
+0xFF10658C,
+0xFF0C648A,
+0xFF0C648A,
+0xFF0B658A,
+0xFF0E678F,
+0xFF0E628E,
+0xFF12658D,
+0xFF005173,
+0xFF064966,
+0xFF0F3751,
+0xFFD5EAFB,
+0xFFF8FFFF,
+0xFFFBFFFC,
+0xFFFAFFFF,
+0xFFFBFFFF,
+0xFFFFFDFE,
+0xFFFFFDFD,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFD,
+0xFFFCFFFF,
+0xFFEFFFFF,
+0xFF19404F,
+0xFF084561,
+0xFF004A6B,
+0xFF10688E,
+0xFF0D6990,
+0xFF0E688B,
+0xFF0E668A,
+0xFF0D668E,
+0xFF0D6690,
+0xFF10658E,
+0xFF0E668E,
+0xFF0B6692,
+0xFF0B6692,
+0xFF0E6791,
+0xFF0F678F,
+0xFF0E668E,
+0xFF0E668E,
+0xFF0E668E,
+0xFF0E668E,
+0xFF0E668E,
+0xFF0F678F,
+0xFF0E668C,
+0xFF0E668C,
+0xFF10658C,
+0xFF10658C,
+0xFF0F648B,
+0xFF0F648B,
+0xFF0F648B,
+0xFF0D658B,
+0xFF09658C,
+0xFF09658C,
+0xFF0D658D,
+0xFF11668F,
+0xFF0B638B,
+0xFF106D98,
+0xFF258BBB,
+0xFF277EA9,
+0xFF719FB7,
+0xFFF0FFFF,
+0xFFFAFEFF,
+0xFFFDFEFF,
+0xFFFBFFFF,
+0xFFFBFFFE,
+0xFFFFFEFF,
+0xFFFFFDFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFCFEFB,
+0xFFFCFFFD,
+0xFFFCFFFD,
+0xFFFAFFFB,
+0xFFFBFFFF,
+0xFFEFFFFF,
+0xFF21455B,
+0xFF295B76,
+0xFF2A627B,
+0xFF25617B,
+0xFF22627E,
+0xFF226383,
+0xFF226487,
+0xFF226286,
+0xFF256185,
+0xFF286081,
+0xFF26617F,
+0xFF26617F,
+0xFF26617F,
+0xFF26617F,
+0xFF26617F,
+0xFF26617F,
+0xFF26617F,
+0xFF26617F,
+0xFF26617F,
+0xFF26617F,
+0xFF26617F,
+0xFF26617F,
+0xFF26617F,
+0xFF26617F,
+0xFF26617F,
+0xFF26617F,
+0xFF28617F,
+0xFF28617F,
+0xFF28617F,
+0xFF28617F,
+0xFF26617F,
+0xFF26617F,
+0xFF266181,
+0xFF266181,
+0xFF266181,
+0xFF266181,
+0xFF266181,
+0xFF266181,
+0xFF256281,
+0xFF246180,
+0xFF246180,
+0xFF246180,
+0xFF256183,
+0xFF256183,
+0xFF256183,
+0xFF256183,
+0xFF256183,
+0xFF256183,
+0xFF256183,
+0xFF256183,
+0xFF256183,
+0xFF256183,
+0xFF236283,
+0xFF226182,
+0xFF226182,
+0xFF226182,
+0xFF226182,
+0xFF226182,
+0xFF236283,
+0xFF236283,
+0xFF236285,
+0xFF236283,
+0xFF236285,
+0xFF216282,
+0xFF226184,
+0xFF216282,
+0xFF226184,
+0xFF216282,
+0xFF226184,
+0xFF216282,
+0xFF216184,
+0xFF216282,
+0xFF216184,
+0xFF216282,
+0xFF246180,
+0xFF246180,
+0xFF216282,
+0xFF206284,
+0xFF206285,
+0xFF206285,
+0xFF226288,
+0xFF226288,
+0xFF236186,
+0xFF206083,
+0xFF216282,
+0xFF20617F,
+0xFF25627F,
+0xFF28617E,
+0xFF1D536F,
+0xFF1D4962,
+0xFFDBF8FF,
+0xFFF1FFFF,
+0xFFF9FEFF,
+0xFFFFFFFD,
+0xFFFCFBF7,
+0xFFFFFFFD,
+0xFFFEFFFF,
+0xFFFBFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFF1FFFF,
+0xFF6B91A8,
+0xFF124B69,
+0xFF105576,
+0xFF135F81,
+0xFF136185,
+0xFF106085,
+0xFF116186,
+0xFF0F6187,
+0xFF106288,
+0xFF116389,
+0xFF116389,
+0xFF106288,
+0xFF0F6187,
+0xFF0E6086,
+0xFF0F6388,
+0xFF0F6388,
+0xFF0F628A,
+0xFF10638B,
+0xFF0F648B,
+0xFF0F648B,
+0xFF0F648B,
+0xFF0F648B,
+0xFF0E6189,
+0xFF10658C,
+0xFF0C658D,
+0xFF0B648C,
+0xFF11638B,
+0xFF0F5D83,
+0xFF045070,
+0xFF0F4B67,
+0xFF456177,
+0xFFF7FFFF,
+0xFFF9FFFF,
+0xFFFAFFFC,
+0xFFFAFFFF,
+0xFFFCFFFF,
+0xFFFFFEFF,
+0xFFFFFEFD,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFEFE,
+0xFFF8FFFF,
+0xFFA0C0CB,
+0xFF083B4E,
+0xFF064763,
+0xFF08567A,
+0xFF136B93,
+0xFF09658C,
+0xFF0F678B,
+0xFF0F678B,
+0xFF0D668E,
+0xFF0D6690,
+0xFF11668F,
+0xFF11668F,
+0xFF0E6791,
+0xFF0C6891,
+0xFF0D668E,
+0xFF0E668E,
+0xFF0D658D,
+0xFF0D658D,
+0xFF0D658D,
+0xFF0D658D,
+0xFF0E668E,
+0xFF0F678F,
+0xFF0D658B,
+0xFF0D658B,
+0xFF0F648B,
+0xFF0F648B,
+0xFF10658C,
+0xFF0F648B,
+0xFF0F648B,
+0xFF0D658B,
+0xFF0C668B,
+0xFF0E678F,
+0xFF0D628B,
+0xFF106490,
+0xFF036089,
+0xFF1A7BA5,
+0xFF1C83B0,
+0xFF1E7096,
+0xFFC6E9FD,
+0xFFF4FDFF,
+0xFFFCFFFF,
+0xFFFCFDFF,
+0xFFF9FFFD,
+0xFFFAFFFC,
+0xFFFFFBFF,
+0xFFFFFBFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFBFDF8,
+0xFFFEFFFD,
+0xFFF7FBFA,
+0xFFFBFFFF,
+0xFFF1FFFF,
+0xFF5D7D8C,
+0xFF1D475D,
+0xFF214E65,
+0xFF204F69,
+0xFF1E516C,
+0xFF1C526E,
+0xFF1A5371,
+0xFF1A5273,
+0xFF1C5171,
+0xFF1F506E,
+0xFF21506C,
+0xFF21506A,
+0xFF21506A,
+0xFF21506A,
+0xFF21506A,
+0xFF21506A,
+0xFF21506A,
+0xFF21506A,
+0xFF21506A,
+0xFF21506A,
+0xFF21506A,
+0xFF21506A,
+0xFF21506A,
+0xFF21506A,
+0xFF21506A,
+0xFF21506A,
+0xFF21506A,
+0xFF204F69,
+0xFF204F69,
+0xFF204F69,
+0xFF204F6B,
+0xFF204F6B,
+0xFF204F6B,
+0xFF204F6B,
+0xFF21506C,
+0xFF21506C,
+0xFF21506C,
+0xFF21506C,
+0xFF1F516C,
+0xFF1E506B,
+0xFF1E506B,
+0xFF1E506B,
+0xFF21506C,
+0xFF21506C,
+0xFF21506C,
+0xFF21506C,
+0xFF21506C,
+0xFF21506C,
+0xFF21506C,
+0xFF21506C,
+0xFF1F516C,
+0xFF1F516C,
+0xFF1F516C,
+0xFF1F516C,
+0xFF1F516C,
+0xFF1F516C,
+0xFF1F516C,
+0xFF1F516C,
+0xFF1F516C,
+0xFF1F516C,
+0xFF1F506E,
+0xFF1F516C,
+0xFF1F506E,
+0xFF1D506B,
+0xFF1E4F6D,
+0xFF1D506B,
+0xFF1F506E,
+0xFF1E516C,
+0xFF1F506E,
+0xFF1E516C,
+0xFF1E516E,
+0xFF1E516C,
+0xFF1E516E,
+0xFF1E516C,
+0xFF1F516C,
+0xFF1F516C,
+0xFF1E516E,
+0xFF1E516E,
+0xFF1E5170,
+0xFF1E5170,
+0xFF21506E,
+0xFF21506E,
+0xFF1F4C69,
+0xFF24546B,
+0xFF215167,
+0xFF1C4B5F,
+0xFF244F62,
+0xFF244A5D,
+0xFF618295,
+0xFFEBFFFF,
+0xFFF2FFFF,
+0xFFF8FFFF,
+0xFFFCFFFF,
+0xFFFBFBF9,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFDFFFE,
+0xFFF1FFFF,
+0xFF406E86,
+0xFF145376,
+0xFF11577B,
+0xFF145E83,
+0xFF166284,
+0xFF0E5E7F,
+0xFF106085,
+0xFF116186,
+0xFF126287,
+0xFF136388,
+0xFF136388,
+0xFF136388,
+0xFF106288,
+0xFF0F6187,
+0xFF0F6187,
+0xFF106288,
+0xFF0F6388,
+0xFF0F6388,
+0xFF0F6388,
+0xFF0E6287,
+0xFF0F628A,
+0xFF0F628A,
+0xFF116389,
+0xFF10638B,
+0xFF0D668E,
+0xFF0D658D,
+0xFF136388,
+0xFF0F587B,
+0xFF105574,
+0xFF0B3F57,
+0xFFB1C4D5,
+0xFFFAFEFF,
+0xFFF8FEFC,
+0xFFFBFFFD,
+0xFFFCFFFF,
+0xFFFDFEFF,
+0xFFFFFDFE,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFCFFFF,
+0xFFF1FFFF,
+0xFF396475,
+0xFF0D4963,
+0xFF044B69,
+0xFF156588,
+0xFF116991,
+0xFF0B678E,
+0xFF0E668A,
+0xFF0E668A,
+0xFF0E668E,
+0xFF0E6590,
+0xFF11648E,
+0xFF10658C,
+0xFF0E678F,
+0xFF0C688F,
+0xFF0C668B,
+0xFF0D658B,
+0xFF0F648B,
+0xFF0F648B,
+0xFF0F648B,
+0xFF0F648B,
+0xFF10658C,
+0xFF10658C,
+0xFF0F648B,
+0xFF0F648B,
+0xFF10638B,
+0xFF10638B,
+0xFF10638B,
+0xFF10638B,
+0xFF10638B,
+0xFF0F648B,
+0xFF0C648A,
+0xFF0F648B,
+0xFF0F608B,
+0xFF0A618C,
+0xFF076A93,
+0xFF197EA8,
+0xFF1D7DA7,
+0xFF377D9F,
+0xFFEBFFFF,
+0xFFFEFEFF,
+0xFFFFFFFF,
+0xFFFEFFFD,
+0xFFFBFFFB,
+0xFFFCFFFD,
+0xFFFFFDFF,
+0xFFFFFDFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFDFDFB,
+0xFFFDFDFB,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFBFFFF,
+0xFFF7FFFF,
+0xFFECFFFF,
+0xFFB1CFDA,
+0xFFACC9DB,
+0xFFABCADF,
+0xFFABCBE0,
+0xFFA7CCDF,
+0xFFA7CBE1,
+0xFFA7CBE1,
+0xFFA8CBE1,
+0xFFAACADF,
+0xFFAACBDE,
+0xFFAACBDC,
+0xFFABCADE,
+0xFFAACBDC,
+0xFFABCADE,
+0xFFAACBDC,
+0xFFABCADE,
+0xFFAACBDC,
+0xFFABCADE,
+0xFFAACBDC,
+0xFFABCADE,
+0xFFAACBDC,
+0xFFABCADE,
+0xFFAACBDC,
+0xFFABCADE,
+0xFFABCADC,
+0xFFABCADE,
+0xFFABCADC,
+0xFFABCADE,
+0xFFABCADE,
+0xFFABCADE,
+0xFFABCADE,
+0xFFABCADE,
+0xFFAACBDE,
+0xFFABCADE,
+0xFFAACBDE,
+0xFFABCADE,
+0xFFAACBDE,
+0xFFAACBDE,
+0xFFAACBDE,
+0xFFAACBDE,
+0xFFAACBDE,
+0xFFAAC9DD,
+0xFFAAC9DD,
+0xFFAAC9DD,
+0xFFAAC9DD,
+0xFFAAC9DD,
+0xFFAAC9DD,
+0xFFAAC9DD,
+0xFFAAC9DD,
+0xFFAACBDE,
+0xFFAACBDE,
+0xFFAACBDE,
+0xFFAACBDE,
+0xFFAACBDE,
+0xFFAACBDE,
+0xFFAACBDE,
+0xFFAACBDE,
+0xFFAACBDE,
+0xFFAACBDE,
+0xFFAACBDE,
+0xFFA9CADD,
+0xFFA9CADD,
+0xFFA9CADD,
+0xFFA9CADD,
+0xFFA9CADD,
+0xFFAACBDE,
+0xFFAACBDE,
+0xFFAACBDE,
+0xFFAACBDE,
+0xFFAACBDE,
+0xFFAACBDE,
+0xFFAACBDE,
+0xFFAACBDE,
+0xFFAACBDE,
+0xFFAACBDE,
+0xFFA8CBDF,
+0xFFA8CBDF,
+0xFFAACADF,
+0xFFABCADF,
+0xFFADC9DE,
+0xFFAEC9DC,
+0xFFADCADA,
+0xFFACC9D7,
+0xFFABCBD6,
+0xFFA5C6CF,
+0xFFC4DFEA,
+0xFFEBFFFF,
+0xFFF0FFFF,
+0xFFF7FFFF,
+0xFFFBFFFF,
+0xFFFCFDFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFCFFFF,
+0xFFF0FFFF,
+0xFF20536E,
+0xFF195D82,
+0xFF175C85,
+0xFF135D82,
+0xFF156183,
+0xFF11607F,
+0xFF106083,
+0xFF106085,
+0xFF116186,
+0xFF116186,
+0xFF116186,
+0xFF116186,
+0xFF106288,
+0xFF106288,
+0xFF0F6187,
+0xFF106288,
+0xFF0F6388,
+0xFF0F6388,
+0xFF0E6287,
+0xFF0E6287,
+0xFF0E6189,
+0xFF106288,
+0xFF14638A,
+0xFF0C5E86,
+0xFF0C658D,
+0xFF0F678D,
+0xFF146084,
+0xFF155A7B,
+0xFF175471,
+0xFF1F4C63,
+0xFFF4FFFF,
+0xFFFEFFFF,
+0xFFFAFEFD,
+0xFFFCFFFF,
+0xFFFEFFFF,
+0xFFFEFDFF,
+0xFFFEFEFE,
+0xFFFEFEFC,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFCFFFF,
+0xFFF8FFFF,
+0xFFD2ECF9,
+0xFF093D55,
+0xFF0B506F,
+0xFF0A5678,
+0xFF13678B,
+0xFF096187,
+0xFF0E678F,
+0xFF0C658D,
+0xFF0C658D,
+0xFF0D658D,
+0xFF0F648D,
+0xFF10638D,
+0xFF10638B,
+0xFF0D658B,
+0xFF0C6689,
+0xFF0D658B,
+0xFF0D658B,
+0xFF0F648B,
+0xFF0F648B,
+0xFF0F648B,
+0xFF0F648B,
+0xFF0F648B,
+0xFF0F648B,
+0xFF10658C,
+0xFF0F648B,
+0xFF10638B,
+0xFF10638B,
+0xFF0F628A,
+0xFF0F628A,
+0xFF0F628A,
+0xFF0E6287,
+0xFF0F6388,
+0xFF0C6085,
+0xFF11638B,
+0xFF07608A,
+0xFF07719B,
+0xFF127CA4,
+0xFF10688E,
+0xFF8DC8E6,
+0xFFEFFFFF,
+0xFFFDFCFF,
+0xFFFFFEFC,
+0xFFFEFFF9,
+0xFFF9FEF7,
+0xFFFCFFFB,
+0xFFFFFEFF,
+0xFFFFFDFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFCFD,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFAFAFC,
+0xFFFEFFFF,
+0xFFFAFEFF,
+0xFFF8FFFF,
+0xFFF7FFFF,
+0xFFF7FFFF,
+0xFFF8FFFF,
+0xFFF8FFFF,
+0xFFF7FFFF,
+0xFFF7FFFF,
+0xFFF8FFFF,
+0xFFF9FFFF,
+0xFFF7FFFF,
+0xFFF6FFFF,
+0xFFF4FFFF,
+0xFFF6FFFF,
+0xFFF4FFFF,
+0xFFF6FFFF,
+0xFFF4FFFF,
+0xFFF6FFFF,
+0xFFF4FFFF,
+0xFFF6FFFF,
+0xFFF4FFFF,
+0xFFF6FFFF,
+0xFFF4FFFF,
+0xFFF6FFFF,
+0xFFF4FFFF,
+0xFFF6FFFF,
+0xFFF6FFFF,
+0xFFF7FFFF,
+0xFFF7FFFF,
+0xFFF7FFFF,
+0xFFF7FFFF,
+0xFFF7FFFF,
+0xFFF7FFFF,
+0xFFF7FFFF,
+0xFFF5FFFF,
+0xFFF6FFFF,
+0xFFF4FFFF,
+0xFFF6FFFF,
+0xFFF4FFFF,
+0xFFF4FFFF,
+0xFFF4FFFF,
+0xFFF4FFFF,
+0xFFF4FFFF,
+0xFFF7FFFF,
+0xFFF7FFFF,
+0xFFF7FFFF,
+0xFFF7FFFF,
+0xFFF7FFFF,
+0xFFF7FFFF,
+0xFFF7FFFF,
+0xFFF7FFFF,
+0xFFF7FFFF,
+0xFFF7FFFF,
+0xFFF7FFFF,
+0xFFF7FFFF,
+0xFFF5FFFF,
+0xFFF5FFFF,
+0xFFF5FFFF,
+0xFFF5FFFF,
+0xFFF7FFFF,
+0xFFF7FFFF,
+0xFFF7FFFF,
+0xFFF7FFFF,
+0xFFF7FFFF,
+0xFFF7FFFF,
+0xFFF7FFFF,
+0xFFF7FFFF,
+0xFFF7FFFF,
+0xFFF7FFFF,
+0xFFF8FFFF,
+0xFFF8FFFF,
+0xFFF8FFFF,
+0xFFF8FFFF,
+0xFFF8FFFF,
+0xFFF7FFFF,
+0xFFF7FFFF,
+0xFFF5FFFF,
+0xFFF5FFFF,
+0xFFF5FFFF,
+0xFFF7FFFF,
+0xFFF8FFFF,
+0xFFF9FFFF,
+0xFFF8FFFF,
+0xFFF8FFFF,
+0xFFF5FFFF,
+0xFFF4FFFF,
+0xFFF3FFFF,
+0xFFF2FFFF,
+0xFFF9FFFF,
+0xFFFEFEFF,
+0xFFFEFBFF,
+0xFFFEFAF9,
+0xFFFFFEFB,
+0xFFFCFBF9,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFAFAFA,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFEFFFD,
+0xFFFEFFFD,
+0xFFFEFFFD,
+0xFFFEFFFD,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFCFFFF,
+0xFFD3E9F6,
+0xFF17506D,
+0xFF1A648B,
+0xFF19608A,
+0xFF125C83,
+0xFF146080,
+0xFF11607F,
+0xFF106083,
+0xFF106085,
+0xFF106085,
+0xFF106085,
+0xFF0F5F84,
+0xFF106085,
+0xFF116186,
+0xFF126287,
+0xFF0F6187,
+0xFF106288,
+0xFF106288,
+0xFF106288,
+0xFF0F6187,
+0xFF0F6187,
+0xFF0F6388,
+0xFF116389,
+0xFF126087,
+0xFF105F86,
+0xFF0C608C,
+0xFF11648C,
+0xFF146080,
+0xFF1D5E7C,
+0xFF184D6C,
+0xFF789CB2,
+0xFFF4FFFF,
+0xFFFEFEFE,
+0xFFFCFEFB,
+0xFFFEFEFE,
+0xFFFCFBFF,
+0xFFFFFEFF,
+0xFFFEFFFF,
+0xFFFDFFFC,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFBFFFF,
+0xFFEFFEFF,
+0xFF7A99AB,
+0xFF094561,
+0xFF085476,
+0xFF0D6186,
+0xFF0E638A,
+0xFF0C6186,
+0xFF0F678D,
+0xFF08658E,
+0xFF08658E,
+0xFF0E638A,
+0xFF10628A,
+0xFF0F628C,
+0xFF0F628C,
+0xFF0C6488,
+0xFF0C6587,
+0xFF0D6589,
+0xFF0F648B,
+0xFF0F648B,
+0xFF0F648B,
+0xFF0F648B,
+0xFF0F648B,
+0xFF0F648B,
+0xFF0E638A,
+0xFF10638B,
+0xFF10638B,
+0xFF0F628A,
+0xFF0F628A,
+0xFF0F6388,
+0xFF0F6388,
+0xFF0F6388,
+0xFF0F6388,
+0xFF136388,
+0xFF106085,
+0xFF106287,
+0xFF06628B,
+0xFF0473A0,
+0xFF0C77A1,
+0xFF216D8D,
+0xFFDAFFFF,
+0xFFF1FFFF,
+0xFFF7FAFF,
+0xFFFFFFFA,
+0xFFFFFFF6,
+0xFFFFFFF8,
+0xFFFFFFFB,
+0xFFFFFEFF,
+0xFFFFFDFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFDFF,
+0xFFFFFDFF,
+0xFFFFFEFF,
+0xFFFEFDFF,
+0xFFFEFEFF,
+0xFFFEFFFD,
+0xFFFDFDFB,
+0xFFFFFEFF,
+0xFFFFFDFF,
+0xFFFFFEFF,
+0xFFFFFDFC,
+0xFFFFFDFC,
+0xFFFFFEFB,
+0xFFFFFEFB,
+0xFFFFFEFA,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFDFE,
+0xFFFEFEFC,
+0xFFFCFFFD,
+0xFFF7FDF9,
+0xFFFBFFFF,
+0xFFFCFFFF,
+0xFFFCFCFE,
+0xFFFFFDFF,
+0xFFFFFDFF,
+0xFFFFFEFB,
+0xFFFFFBF8,
+0xFFFFFFFD,
+0xFFFEFCFD,
+0xFFFDFDFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFEFFFD,
+0xFFFEFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFCFFFF,
+0xFFF7FEFF,
+0xFFA5BFCE,
+0xFF185371,
+0xFF156087,
+0xFF165F88,
+0xFF115B82,
+0xFF156181,
+0xFF105F7E,
+0xFF105E82,
+0xFF106085,
+0xFF126086,
+0xFF116186,
+0xFF115F85,
+0xFF106085,
+0xFF106085,
+0xFF106085,
+0xFF105F86,
+0xFF0F6187,
+0xFF126188,
+0xFF106288,
+0xFF126188,
+0xFF0F6187,
+0xFF106288,
+0xFF116388,
+0xFF0F5D83,
+0xFF18668D,
+0xFF0C5F89,
+0xFF0F6189,
+0xFF186383,
+0xFF24617E,
+0xFF1C4861,
+0xFFDEF9FF,
+0xFFF8FFFF,
+0xFFFDFDFB,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFDFEFF,
+0xFFFEFFFF,
+0xFFFDFFFE,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFF9FFFF,
+0xFFECFFFF,
+0xFF204A62,
+0xFF165576,
+0xFF0C5A80,
+0xFF11658A,
+0xFF0F648B,
+0xFF14688D,
+0xFF0C6188,
+0xFF0A668F,
+0xFF0A668F,
+0xFF0F628A,
+0xFF106288,
+0xFF10618C,
+0xFF0E638C,
+0xFF0E6388,
+0xFF0C6587,
+0xFF0F6489,
+0xFF0F648B,
+0xFF10658C,
+0xFF10658C,
+0xFF10658C,
+0xFF0F648B,
+0xFF0E638A,
+0xFF0E638A,
+0xFF0F628A,
+0xFF0E6287,
+0xFF0E6189,
+0xFF0E6287,
+0xFF0F6388,
+0xFF0F6388,
+0xFF106489,
+0xFF12648A,
+0xFF116186,
+0xFF146489,
+0xFF0D6185,
+0xFF08668C,
+0xFF0675A2,
+0xFF0B6E97,
+0xFF5A96B2,
+0xFFE7FFFF,
+0xFFF1FDFF,
+0xFFFCFFFF,
+0xFFFBFAF5,
+0xFFFFFFF6,
+0xFFFFFFFA,
+0xFFFCFDF8,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFCFB,
+0xFFFFFEFF,
+0xFFFEFEFE,
+0xFFFEFFFA,
+0xFFFEFFFB,
+0xFFFCFEFD,
+0xFFFBFFFF,
+0xFFF5FFFF,
+0xFF5E7D8F,
+0xFF1B5875,
+0xFF186488,
+0xFF135D84,
+0xFF145E85,
+0xFF0F597E,
+0xFF135F81,
+0xFF145F86,
+0xFF115F85,
+0xFF135E85,
+0xFF115F85,
+0xFF135E85,
+0xFF115F85,
+0xFF115F85,
+0xFF115F85,
+0xFF115F85,
+0xFF106085,
+0xFF126086,
+0xFF116186,
+0xFF136187,
+0xFF126287,
+0xFF126287,
+0xFF136388,
+0xFF115F85,
+0xFF156389,
+0xFF126188,
+0xFF136188,
+0xFF1E668C,
+0xFF1E5774,
+0xFF577889,
+0xFFF1FFFF,
+0xFFF9FFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFB,
+0xFFFCFFFD,
+0xFFFCFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFCFFFF,
+0xFFFEFFFF,
+0xFFFFFDFF,
+0xFFFFFDFF,
+0xFFFFFFFD,
+0xFFFEFFFD,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFDFEFF,
+0xFFFEFFFF,
+0xFFFFFFFB,
+0xFFFFFFFB,
+0xFFFAFCFB,
+0xFFFEFFFF,
+0xFFFDFDFF,
+0xFFF5FFFF,
+0xFFA0C5DF,
+0xFF104869,
+0xFF17597C,
+0xFF196388,
+0xFF106085,
+0xFF0E6287,
+0xFF0F6388,
+0xFF0F6489,
+0xFF10658E,
+0xFF10638D,
+0xFF11638B,
+0xFF10628A,
+0xFF10628A,
+0xFF0E638A,
+0xFF0E638A,
+0xFF0D6589,
+0xFF0D6287,
+0xFF0F6388,
+0xFF0F6388,
+0xFF0E6287,
+0xFF0D6088,
+0xFF0D6088,
+0xFF0D6289,
+0xFF0D6289,
+0xFF0D6186,
+0xFF0E6286,
+0xFF0F6388,
+0xFF106489,
+0xFF116389,
+0xFF106288,
+0xFF106288,
+0xFF136289,
+0xFF126087,
+0xFF106288,
+0xFF0B6387,
+0xFF0A6B8E,
+0xFF0B709A,
+0xFF116186,
+0xFFC0E4FA,
+0xFFF7FFFF,
+0xFFFCFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFEFFFD,
+0xFFFFFFFB,
+0xFFFFFFFB,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFDFE,
+0xFFFFFDFE,
+0xFFFFFFFF,
+0xFFFDFDFD,
+0xFFFFFFFB,
+0xFFF9FBF6,
+0xFFFEFFFF,
+0xFFF7FFFF,
+0xFFEEFFFF,
+0xFF284E65,
+0xFF246382,
+0xFF186285,
+0xFF115B82,
+0xFF0F5A81,
+0xFF125C81,
+0xFF125C81,
+0xFF125E82,
+0xFF125D84,
+0xFF135E85,
+0xFF135E85,
+0xFF135E85,
+0xFF135E85,
+0xFF115F85,
+0xFF115F85,
+0xFF115F85,
+0xFF115F85,
+0xFF115F85,
+0xFF126086,
+0xFF126086,
+0xFF126086,
+0xFF126086,
+0xFF126086,
+0xFF146286,
+0xFF115F83,
+0xFF105E84,
+0xFF166188,
+0xFF1F6388,
+0xFF1B4E6B,
+0xFFB7D2DD,
+0xFFF8FFFF,
+0xFFFCFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFEFFFB,
+0xFFFCFFFA,
+0xFFFCFFFD,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFCFFFF,
+0xFFFEFFFF,
+0xFFFFFDFF,
+0xFFFFFCFF,
+0xFFFFFFFB,
+0xFFFEFFFD,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFDFEFF,
+0xFFFFFFFB,
+0xFFFFFFFA,
+0xFFFFFFFD,
+0xFFFEFFFF,
+0xFFFCFFFF,
+0xFFEEFFFF,
+0xFF3E6D8B,
+0xFF17577B,
+0xFF1A5E83,
+0xFF125C7F,
+0xFF15658A,
+0xFF12668A,
+0xFF106489,
+0xFF10658A,
+0xFF10628A,
+0xFF10628A,
+0xFF12618A,
+0xFF12618A,
+0xFF10628A,
+0xFF0F628A,
+0xFF0E638A,
+0xFF0E6388,
+0xFF0E6287,
+0xFF0E6286,
+0xFF0E6287,
+0xFF0E6287,
+0xFF0E6189,
+0xFF0E6189,
+0xFF0F628A,
+0xFF0F6388,
+0xFF106488,
+0xFF106488,
+0xFF116388,
+0xFF106287,
+0xFF106287,
+0xFF116087,
+0xFF116087,
+0xFF116087,
+0xFF105F86,
+0xFF10638B,
+0xFF056387,
+0xFF066488,
+0xFF10658A,
+0xFF377491,
+0xFFEEFFFF,
+0xFFFAFAFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFCFDFF,
+0xFFFDFEFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFBFCFE,
+0xFFF7FFFF,
+0xFFABCADE,
+0xFF1A4965,
+0xFF266286,
+0xFF165F82,
+0xFF105B82,
+0xFF0F5D81,
+0xFF145E81,
+0xFF115C7C,
+0xFF115D81,
+0xFF115D81,
+0xFF125E82,
+0xFF125E82,
+0xFF125E82,
+0xFF135F83,
+0xFF135E85,
+0xFF135E85,
+0xFF115F85,
+0xFF115F85,
+0xFF115F85,
+0xFF115F85,
+0xFF115F85,
+0xFF115F85,
+0xFF115F85,
+0xFF115F85,
+0xFF126084,
+0xFF105E82,
+0xFF17658B,
+0xFF196187,
+0xFF1E5F7F,
+0xFF28586F,
+0xFFEFFFFF,
+0xFFFAFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFD,
+0xFFFEFFFB,
+0xFFFFFFFA,
+0xFFFFFFFB,
+0xFFFEFFFF,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFEFFFF,
+0xFFFFFEFF,
+0xFFFFFDFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFDFEFF,
+0xFFFFFFFD,
+0xFFFFFFFB,
+0xFFFFFCF9,
+0xFFFFFDFF,
+0xFFF6FFFF,
+0xFFD4EEFF,
+0xFF164968,
+0xFF1F6184,
+0xFF1C6286,
+0xFF166083,
+0xFF136388,
+0xFF0E6286,
+0xFF0D6186,
+0xFF0A5F84,
+0xFF0E6088,
+0xFF0F6189,
+0xFF12618A,
+0xFF12618A,
+0xFF11638B,
+0xFF0F628A,
+0xFF0E6388,
+0xFF0D6287,
+0xFF0F6388,
+0xFF0E6287,
+0xFF0F6187,
+0xFF0F6187,
+0xFF106288,
+0xFF106288,
+0xFF106288,
+0xFF106288,
+0xFF106287,
+0xFF106385,
+0xFF116184,
+0xFF116184,
+0xFF116184,
+0xFF126086,
+0xFF126086,
+0xFF106085,
+0xFF0E6085,
+0xFF075F85,
+0xFF056690,
+0xFF0D678C,
+0xFF135472,
+0xFFA5D0E3,
+0xFFF1FFFF,
+0xFFFBFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFCFFFF,
+0xFFFBFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFDFCFA,
+0xFFFCFCFC,
+0xFFFCFFFF,
+0xFFEEFFFF,
+0xFF4C718B,
+0xFF2A5F81,
+0xFF205C81,
+0xFF14587F,
+0xFF125E82,
+0xFF115F83,
+0xFF105B7B,
+0xFF135E7E,
+0xFF125C7F,
+0xFF115D81,
+0xFF115D81,
+0xFF115D81,
+0xFF125E82,
+0xFF125E82,
+0xFF125D84,
+0xFF125D84,
+0xFF115F85,
+0xFF115F85,
+0xFF115F85,
+0xFF115F85,
+0xFF115F85,
+0xFF115F85,
+0xFF115F85,
+0xFF105E84,
+0xFF126084,
+0xFF125E82,
+0xFF186488,
+0xFF1C6284,
+0xFF1A5672,
+0xFF83ACBE,
+0xFFF4FFFF,
+0xFFFEFDFF,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFCFFFD,
+0xFFFEFFFB,
+0xFFFFFEFB,
+0xFFFFFEFB,
+0xFFFFFFFF,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFEFFFF,
+0xFFFFFFFD,
+0xFFFFFEFD,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFEFFFF,
+0xFFFEFFFD,
+0xFFFFFFFB,
+0xFFFFFCFA,
+0xFFFFFEFF,
+0xFFF1FFFF,
+0xFF7295A9,
+0xFF225978,
+0xFF195D80,
+0xFF195F83,
+0xFF186488,
+0xFF106085,
+0xFF0F6387,
+0xFF0F6388,
+0xFF0E6287,
+0xFF0F6189,
+0xFF10628A,
+0xFF12618A,
+0xFF13628B,
+0xFF13628B,
+0xFF106288,
+0xFF0F6388,
+0xFF0F6388,
+0xFF106489,
+0xFF0F6388,
+0xFF0F6187,
+0xFF116087,
+0xFF126188,
+0xFF136188,
+0xFF126087,
+0xFF126086,
+0xFF115F83,
+0xFF116184,
+0xFF116184,
+0xFF106083,
+0xFF115F83,
+0xFF115F83,
+0xFF105E84,
+0xFF0F5F84,
+0xFF106689,
+0xFF035D82,
+0xFF025F8A,
+0xFF09597E,
+0xFF2F5E72,
+0xFFEBFFFF,
+0xFFF0FFFF,
+0xFFF9FFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFF8FDFF,
+0xFFFBFFFF,
+0xFFFCFFFF,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFF8FFFF,
+0xFFDDF7FF,
+0xFF1E4D6B,
+0xFF235D83,
+0xFF1F5D86,
+0xFF15567E,
+0xFF125C81,
+0xFF0E5A7C,
+0xFF0E5978,
+0xFF145F7E,
+0xFF125C7F,
+0xFF115D81,
+0xFF115D81,
+0xFF115D81,
+0xFF115D81,
+0xFF125E82,
+0xFF125E82,
+0xFF125E82,
+0xFF125E82,
+0xFF125E82,
+0xFF115F83,
+0xFF115F83,
+0xFF115F85,
+0xFF115F85,
+0xFF115F85,
+0xFF115F85,
+0xFF135F83,
+0xFF166085,
+0xFF196388,
+0xFF1F6181,
+0xFF1D4D63,
+0xFFDFFCFF,
+0xFFF8FFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFEFFFD,
+0xFFFEFFFB,
+0xFFFFFEFB,
+0xFFFFFEFB,
+0xFFFFFFFD,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFEFDFF,
+0xFFFEFFFF,
+0xFFFCFFFD,
+0xFFFFFFFB,
+0xFFFFFBF9,
+0xFFFEFDFF,
+0xFFEBFFFF,
+0xFF1F4D65,
+0xFF245F81,
+0xFF1A6084,
+0xFF186086,
+0xFF115F83,
+0xFF106287,
+0xFF106488,
+0xFF0E6287,
+0xFF12668B,
+0xFF116389,
+0xFF116389,
+0xFF126188,
+0xFF126188,
+0xFF126188,
+0xFF106287,
+0xFF106287,
+0xFF0F6388,
+0xFF0F6388,
+0xFF0F628A,
+0xFF0F6187,
+0xFF116087,
+0xFF126086,
+0xFF145F86,
+0xFF145F86,
+0xFF135F83,
+0xFF135F83,
+0xFF136185,
+0xFF136185,
+0xFF115F83,
+0xFF105E82,
+0xFF105E82,
+0xFF115F83,
+0xFF0D6082,
+0xFF0A6385,
+0xFF045E81,
+0xFF075C85,
+0xFF0D4E6E,
+0xFFAECAD6,
+0xFFF7FFFF,
+0xFFF8FFFF,
+0xFFF9FFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFDFF,
+0xFFFFFDFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFCFEFD,
+0xFFFCFBF9,
+0xFFFFFDFE,
+0xFFFCFFFF,
+0xFFEEFFFF,
+0xFF7499AC,
+0xFF1F5474,
+0xFF1F5F85,
+0xFF195883,
+0xFF175882,
+0xFF0F587B,
+0xFF0D5979,
+0xFF135E7D,
+0xFF115C7B,
+0xFF125C7F,
+0xFF115D81,
+0xFF115D81,
+0xFF115D81,
+0xFF115D81,
+0xFF115D81,
+0xFF115D81,
+0xFF115D81,
+0xFF115D81,
+0xFF125E82,
+0xFF105E82,
+0xFF105E82,
+0xFF115F85,
+0xFF115F85,
+0xFF115F85,
+0xFF135F83,
+0xFF135D82,
+0xFF176184,
+0xFF1E678A,
+0xFF195672,
+0xFF5A7F91,
+0xFFF1FFFF,
+0xFFF9FCFF,
+0xFFFFFCFF,
+0xFFFFFDFD,
+0xFFFFFEFB,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFEFD,
+0xFFFFFEFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFD,
+0xFFFEFFFD,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFEFDFF,
+0xFFFCFDFF,
+0xFFFAFFFB,
+0xFFFFFFFB,
+0xFFFFFBF9,
+0xFFFAFFFF,
+0xFFA4C4D9,
+0xFF1A4F6E,
+0xFF216184,
+0xFF1A6386,
+0xFF166085,
+0xFF115F83,
+0xFF116388,
+0xFF0C6084,
+0xFF0F6388,
+0xFF0D6186,
+0xFF106288,
+0xFF126188,
+0xFF126087,
+0xFF126086,
+0xFF116186,
+0xFF116186,
+0xFF116186,
+0xFF0F6186,
+0xFF0F6187,
+0xFF0E6086,
+0xFF105F86,
+0xFF115F85,
+0xFF135E85,
+0xFF155F86,
+0xFF155F84,
+0xFF155F84,
+0xFF135F83,
+0xFF146084,
+0xFF126084,
+0xFF105E82,
+0xFF105E82,
+0xFF126084,
+0xFF146286,
+0xFF106385,
+0xFF045D7D,
+0xFF005173,
+0xFF0D5375,
+0xFF33617B,
+0xFFF5FFFF,
+0xFFFBFBF9,
+0xFFFAFFFC,
+0xFFF9FFFD,
+0xFFFEFFFD,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFDFF,
+0xFFFFFDFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFBFDFC,
+0xFFFFFFFD,
+0xFFFFFEFD,
+0xFFFFFEFF,
+0xFFF8FFFF,
+0xFFE4FFFF,
+0xFF1B4D66,
+0xFF245F7D,
+0xFF216386,
+0xFF13547E,
+0xFF165983,
+0xFF11577B,
+0xFF125B7C,
+0xFF145F7F,
+0xFF0E5979,
+0xFF115B7E,
+0xFF115B7E,
+0xFF115B7E,
+0xFF115B7E,
+0xFF115B80,
+0xFF125C81,
+0xFF115D81,
+0xFF115D81,
+0xFF115D81,
+0xFF115D81,
+0xFF115D81,
+0xFF125E82,
+0xFF125E82,
+0xFF125E82,
+0xFF125E82,
+0xFF125E82,
+0xFF155F84,
+0xFF176083,
+0xFF1A6181,
+0xFF1A526B,
+0xFFBFD9E6,
+0xFFF8FFFF,
+0xFFFEFEFF,
+0xFFFFFDFF,
+0xFFFFFEFD,
+0xFFFFFEFB,
+0xFFFFFEFD,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFDFEFF,
+0xFFFCFEFB,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFF0FEFF,
+0xFF3F6982,
+0xFF1C587A,
+0xFF1E6287,
+0xFF135D82,
+0xFF115D81,
+0xFF126084,
+0xFF0F6186,
+0xFF0E6085,
+0xFF12668A,
+0xFF0E6286,
+0xFF0F6186,
+0xFF116186,
+0xFF115F85,
+0xFF115F85,
+0xFF115F85,
+0xFF106083,
+0xFF106083,
+0xFF0E6085,
+0xFF0E6086,
+0xFF0E6086,
+0xFF105F86,
+0xFF115F85,
+0xFF145E85,
+0xFF155D83,
+0xFF155D83,
+0xFF155F84,
+0xFF135E85,
+0xFF135E85,
+0xFF105E84,
+0xFF0E5E83,
+0xFF106085,
+0xFF126287,
+0xFF126084,
+0xFF0E5E81,
+0xFF005674,
+0xFF0A5773,
+0xFF0A3953,
+0xFFD6F0FF,
+0xFFF8FDFF,
+0xFFFFFEFC,
+0xFFFEFFFF,
+0xFFFCFFFD,
+0xFFFEFFFB,
+0xFFFFFFFB,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFCF9,
+0xFFFFFEFD,
+0xFFF8FCFF,
+0xFFF0FFFF,
+0xFF6A97AE,
+0xFF185371,
+0xFF236482,
+0xFF135577,
+0xFF175B82,
+0xFF13577E,
+0xFF15597E,
+0xFF13597D,
+0xFF10597C,
+0xFF0F597C,
+0xFF0F597C,
+0xFF105A7D,
+0xFF105A7D,
+0xFF105A7D,
+0xFF115B80,
+0xFF115B80,
+0xFF125C81,
+0xFF115D81,
+0xFF115D81,
+0xFF115D81,
+0xFF115D81,
+0xFF115D81,
+0xFF125E82,
+0xFF125E82,
+0xFF125E82,
+0xFF135D82,
+0xFF145D80,
+0xFF1D6385,
+0xFF1F6080,
+0xFF2C5C73,
+0xFFF0FFFF,
+0xFFFCFDFF,
+0xFFFEFFFF,
+0xFFFFFEFF,
+0xFFFFFEFD,
+0xFFFFFEFB,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFCFDFF,
+0xFFFEFFFF,
+0xFFFFFFFD,
+0xFFFAFCFB,
+0xFFF8FFFF,
+0xFFD1E8F6,
+0xFF174A67,
+0xFF1F6086,
+0xFF175F85,
+0xFF146084,
+0xFF146286,
+0xFF0F5D81,
+0xFF106085,
+0xFF116388,
+0xFF0B5D82,
+0xFF0F6186,
+0xFF0F5F84,
+0xFF106085,
+0xFF115F85,
+0xFF126086,
+0xFF126084,
+0xFF126084,
+0xFF115F83,
+0xFF106083,
+0xFF0F6186,
+0xFF116186,
+0xFF126086,
+0xFF146084,
+0xFF145E83,
+0xFF145C82,
+0xFF145C82,
+0xFF145E83,
+0xFF135E85,
+0xFF126086,
+0xFF106085,
+0xFF0F5F84,
+0xFF106085,
+0xFF115F83,
+0xFF0C5A7E,
+0xFF075373,
+0xFF004D68,
+0xFF05435A,
+0xFF7A97A7,
+0xFFF5FFFF,
+0xFFFDFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFB,
+0xFFFFFFFB,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFBF8,
+0xFFFFFEFA,
+0xFFFFF8F6,
+0xFFFFFCFB,
+0xFFF7FFFF,
+0xFFD2F2FF,
+0xFF144B69,
+0xFF1D6283,
+0xFF1D607D,
+0xFF175A77,
+0xFF125679,
+0xFF13577C,
+0xFF175880,
+0xFF155980,
+0xFF145980,
+0xFF125B7E,
+0xFF115A7D,
+0xFF115A7D,
+0xFF115A7D,
+0xFF115A7D,
+0xFF115A7D,
+0xFF115B7E,
+0xFF115B7E,
+0xFF115B7E,
+0xFF125C7F,
+0xFF125C7F,
+0xFF145E81,
+0xFF135D80,
+0xFF105A7F,
+0xFF125C81,
+0xFF145E83,
+0xFF105A7F,
+0xFF176083,
+0xFF206284,
+0xFF1B5471,
+0xFF89AFC4,
+0xFFF7FFFF,
+0xFFFFFEFF,
+0xFFFEFFFF,
+0xFFFDFEFF,
+0xFFFFFEFD,
+0xFFFFFDFD,
+0xFFFFFDFF,
+0xFFFFFEFF,
+0xFFF9FFFF,
+0xFFF9FFFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFBFCFE,
+0xFFFFFEFD,
+0xFFFBFCFE,
+0xFFF0FFFF,
+0xFF6B90A2,
+0xFF21597A,
+0xFF1D6188,
+0xFF155F86,
+0xFF145F86,
+0xFF126086,
+0xFF126086,
+0xFF116186,
+0xFF106085,
+0xFF106085,
+0xFF106085,
+0xFF106085,
+0xFF115F85,
+0xFF135F83,
+0xFF135F83,
+0xFF135F83,
+0xFF135F83,
+0xFF135F81,
+0xFF126084,
+0xFF0E5E81,
+0xFF106083,
+0xFF126084,
+0xFF135F81,
+0xFF135D80,
+0xFF145E81,
+0xFF135D82,
+0xFF115D81,
+0xFF0E5C82,
+0xFF105F86,
+0xFF105F86,
+0xFF0E5E83,
+0xFF106085,
+0xFF115F83,
+0xFF075174,
+0xFF004765,
+0xFF084861,
+0xFF1E4C5C,
+0xFFF5FFFF,
+0xFFFDFCFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFEFF,
+0xFFFFFDFE,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFCFFFD,
+0xFFFEFFFD,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFEFB,
+0xFFFFFBF8,
+0xFFFFFCFB,
+0xFFFCFCFE,
+0xFFE9FFFF,
+0xFF447186,
+0xFF1B5C7A,
+0xFF1E6788,
+0xFF155A77,
+0xFF145772,
+0xFF115675,
+0xFF13577A,
+0xFF16577F,
+0xFF165781,
+0xFF13587F,
+0xFF125A80,
+0xFF115A7D,
+0xFF115A7D,
+0xFF115A7D,
+0xFF115A7D,
+0xFF115A7D,
+0xFF115A7D,
+0xFF115A7D,
+0xFF105A7D,
+0xFF115B7E,
+0xFF115B7E,
+0xFF125C7F,
+0xFF125C7F,
+0xFF115B80,
+0xFF125C81,
+0xFF135D82,
+0xFF125B7E,
+0xFF1C6284,
+0xFF23607F,
+0xFF1A4963,
+0xFFE7FFFF,
+0xFFF6FDFF,
+0xFFFEFCFD,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFEFF,
+0xFFFFFDFD,
+0xFFFFFDFF,
+0xFFFEFFFF,
+0xFFF9FFFF,
+0xFFF9FFFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFCFFFF,
+0xFFFEFFFF,
+0xFFFFFCFD,
+0xFFFBFFFF,
+0xFFE9FFFF,
+0xFF1C4C62,
+0xFF216083,
+0xFF1B6089,
+0xFF145E85,
+0xFF135E85,
+0xFF126086,
+0xFF126086,
+0xFF116186,
+0xFF116186,
+0xFF116186,
+0xFF106085,
+0xFF115F85,
+0xFF115F85,
+0xFF135F83,
+0xFF135F83,
+0xFF135F83,
+0xFF135F83,
+0xFF135F81,
+0xFF116081,
+0xFF0F5F82,
+0xFF106083,
+0xFF116081,
+0xFF125E80,
+0xFF135D80,
+0xFF135D80,
+0xFF125E82,
+0xFF0F5D81,
+0xFF126188,
+0xFF0A5980,
+0xFF105F86,
+0xFF0E5C82,
+0xFF0F5B7D,
+0xFF0C5576,
+0xFF004465,
+0xFF084460,
+0xFF043347,
+0xFFE3FFFF,
+0xFFF9FDFF,
+0xFFFFFEFD,
+0xFFFEFFFF,
+0xFFFDFEFF,
+0xFFFFFDFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFFFFFD,
+0xFFFEFFFB,
+0xFFFCFFFB,
+0xFFFCFFFD,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFDF9FA,
+0xFFFFFBFC,
+0xFFF8FFFF,
+0xFF94B7CA,
+0xFF174F68,
+0xFF1D6283,
+0xFF176081,
+0xFF105775,
+0xFF115673,
+0xFF135671,
+0xFF155777,
+0xFF15567E,
+0xFF145480,
+0xFF12557F,
+0xFF13587F,
+0xFF13597D,
+0xFF13597B,
+0xFF13597B,
+0xFF13597B,
+0xFF13597D,
+0xFF13597D,
+0xFF13597D,
+0xFF115A7D,
+0xFF115A7D,
+0xFF115A7D,
+0xFF115A7D,
+0xFF115A7D,
+0xFF125B7E,
+0xFF125B7E,
+0xFF125B7E,
+0xFF165C7E,
+0xFF1E6384,
+0xFF1E5573,
+0xFF62859B,
+0xFFEFFFFF,
+0xFFFBFFFF,
+0xFFFFFFFF,
+0xFFFAFBFD,
+0xFFFEFFFF,
+0xFFFFFEFF,
+0xFFFFFDFF,
+0xFFFFFFFF,
+0xFFFCFFFF,
+0xFFFBFFFF,
+0xFFFBFFFF,
+0xFFFEFFFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFB,
+0xFFFFFFFB,
+0xFFFEFFFF,
+0xFFFCFFFF,
+0xFFFEFFFF,
+0xFFFCFDFF,
+0xFFFFFDFF,
+0xFFF7FFFF,
+0xFF92BBCD,
+0xFF17536D,
+0xFF1F6184,
+0xFF196189,
+0xFF125D84,
+0xFF105E84,
+0xFF115F85,
+0xFF115F85,
+0xFF115F83,
+0xFF115F83,
+0xFF115F83,
+0xFF115F83,
+0xFF125E82,
+0xFF125E82,
+0xFF125E82,
+0xFF125E82,
+0xFF135D80,
+0xFF135D80,
+0xFF135D80,
+0xFF135F81,
+0xFF105F80,
+0xFF0F5F80,
+0xFF0F5E7F,
+0xFF105C7E,
+0xFF125C7F,
+0xFF125C7F,
+0xFF115D81,
+0xFF0F5D81,
+0xFF09587F,
+0xFF136289,
+0xFF126086,
+0xFF0E587B,
+0xFF175C7D,
+0xFF0C4D6B,
+0xFF0C4562,
+0xFF0A384F,
+0xFFBEDAE6,
+0xFFF5FFFF,
+0xFFFEFFFF,
+0xFFFEFDFB,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFB,
+0xFFFEFFF8,
+0xFFFEFFFA,
+0xFFFEFFFB,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFCFFFF,
+0xFFF9FFFF,
+0xFFDBEEFC,
+0xFF1B4961,
+0xFF226180,
+0xFF226788,
+0xFF105678,
+0xFF115878,
+0xFF125776,
+0xFF155873,
+0xFF175876,
+0xFF15567E,
+0xFF13547E,
+0xFF14557D,
+0xFF13577C,
+0xFF14587B,
+0xFF13597B,
+0xFF13597B,
+0xFF13597B,
+0xFF13597D,
+0xFF13597D,
+0xFF13597D,
+0xFF13597D,
+0xFF12587C,
+0xFF115A7D,
+0xFF10597C,
+0xFF10597C,
+0xFF125B7E,
+0xFF10597C,
+0xFF115A7D,
+0xFF1B5F82,
+0xFF20617F,
+0xFF194B64,
+0xFFC4DEEF,
+0xFFF3FDFF,
+0xFFFCFFFF,
+0xFFFBFDFC,
+0xFFFEFFFF,
+0xFFFAFAFC,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFEFFFF,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFEFFFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFEFFFD,
+0xFFFEFFFF,
+0xFFFCFFFF,
+0xFFFDFEFF,
+0xFFFEFFFF,
+0xFFFEFEFF,
+0xFFF1FFFF,
+0xFF33657C,
+0xFF1C5F7C,
+0xFF1F6589,
+0xFF125A82,
+0xFF115C83,
+0xFF105E84,
+0xFF105E84,
+0xFF105E84,
+0xFF105E82,
+0xFF105E82,
+0xFF125E82,
+0xFF125E82,
+0xFF115D81,
+0xFF115D81,
+0xFF115D81,
+0xFF115D81,
+0xFF125C7F,
+0xFF125C7F,
+0xFF125C7F,
+0xFF125E80,
+0xFF0F5E7F,
+0xFF0F5E7F,
+0xFF105C7E,
+0xFF105C7E,
+0xFF125C7F,
+0xFF125C7F,
+0xFF115D81,
+0xFF0E5C80,
+0xFF0F5F84,
+0xFF105E84,
+0xFF105A7D,
+0xFF14597A,
+0xFF104D69,
+0xFF124862,
+0xFF0C3A51,
+0xFF96B7C8,
+0xFFF4FFFF,
+0xFFFCFFFF,
+0xFFFEFFFD,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFEFDFF,
+0xFFFFFFFF,
+0xFFFEFEFF,
+0xFFFFFEFF,
+0xFFFEFFFF,
+0xFFFEFFFB,
+0xFFFEFFF8,
+0xFFFEFFFA,
+0xFFFEFFFD,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFCFFFF,
+0xFFF7FFFF,
+0xFFF2FFFF,
+0xFFEDFFFF,
+0xFF33576D,
+0xFF265D7B,
+0xFF266689,
+0xFF165679,
+0xFF115375,
+0xFF13577A,
+0xFF135879,
+0xFF145774,
+0xFF165775,
+0xFF145679,
+0xFF14557B,
+0xFF14557B,
+0xFF15567C,
+0xFF13577A,
+0xFF13577A,
+0xFF13577A,
+0xFF14587B,
+0xFF14587B,
+0xFF14587B,
+0xFF14587B,
+0xFF145A7C,
+0xFF12587A,
+0xFF145A7C,
+0xFF13597D,
+0xFF12587C,
+0xFF13597D,
+0xFF12587C,
+0xFF155B7F,
+0xFF216385,
+0xFF24607C,
+0xFF3A6578,
+0xFFEFFFFF,
+0xFFFBFFFF,
+0xFFFEFFFF,
+0xFFFBFDFC,
+0xFFFDFFFE,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFD,
+0xFFFBFCFE,
+0xFFF8FFFF,
+0xFFC6DFF3,
+0xFF174E6C,
+0xFF1C6284,
+0xFF135C7F,
+0xFF135D82,
+0xFF125E82,
+0xFF125E82,
+0xFF125E82,
+0xFF125E82,
+0xFF125E82,
+0xFF125E82,
+0xFF125C81,
+0xFF125C81,
+0xFF125C7F,
+0xFF125C7F,
+0xFF115D7F,
+0xFF115D7F,
+0xFF125C7F,
+0xFF125C7F,
+0xFF125C7F,
+0xFF125C7F,
+0xFF125E82,
+0xFF115D81,
+0xFF115D7F,
+0xFF135D80,
+0xFF135D80,
+0xFF125C7F,
+0xFF105C80,
+0xFF105C80,
+0xFF126084,
+0xFF135D80,
+0xFF125778,
+0xFF1A5672,
+0xFF1B4B62,
+0xFF13394E,
+0xFF97B6C8,
+0xFFF1FFFF,
+0xFFFAFFFF,
+0xFFFAFAFA,
+0xFFFDFFFC,
+0xFFFDFFFC,
+0xFFFFFEFF,
+0xFFFFFDFE,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFB,
+0xFFFFFFFA,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFBFFFF,
+0xFFF4FFFF,
+0xFFE9FFFF,
+0xFF567F95,
+0xFF225874,
+0xFF1F5B7D,
+0xFF1D5D81,
+0xFF165578,
+0xFF155477,
+0xFF14557B,
+0xFF12567B,
+0xFF135577,
+0xFF135577,
+0xFF145678,
+0xFF145678,
+0xFF16567A,
+0xFF16567C,
+0xFF15577A,
+0xFF13577A,
+0xFF13577A,
+0xFF13577A,
+0xFF13577A,
+0xFF14587B,
+0xFF14587B,
+0xFF14587B,
+0xFF13597B,
+0xFF155B7D,
+0xFF145A7E,
+0xFF13597D,
+0xFF12587C,
+0xFF13597D,
+0xFF185E82,
+0xFF236484,
+0xFF1B516B,
+0xFF8BB0C2,
+0xFFF5FFFF,
+0xFFFCFDFF,
+0xFFFBFBFD,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFEFEFC,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFB,
+0xFFFFFFFB,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFDF9,
+0xFFFEFFFF,
+0xFFF4FFFF,
+0xFF66869F,
+0xFF215C7C,
+0xFF1D6689,
+0xFF145E81,
+0xFF125E80,
+0xFF125E82,
+0xFF125E82,
+0xFF125E82,
+0xFF125E82,
+0xFF135D82,
+0xFF125C81,
+0xFF125C81,
+0xFF125C81,
+0xFF135D80,
+0xFF125C7F,
+0xFF115D7F,
+0xFF115D7F,
+0xFF125C7F,
+0xFF125C7F,
+0xFF125C7F,
+0xFF125C7F,
+0xFF115D81,
+0xFF115D81,
+0xFF125C7F,
+0xFF125C7F,
+0xFF115B7E,
+0xFF105A7D,
+0xFF105A7F,
+0xFF105C7E,
+0xFF0D577A,
+0xFF135A7A,
+0xFF1C5C78,
+0xFF1F536B,
+0xFF173D50,
+0xFF9CB8C6,
+0xFFF2FFFF,
+0xFFF4FDFF,
+0xFFFFFFFF,
+0xFFFFFEFC,
+0xFFFEFFFB,
+0xFFFEFFFB,
+0xFFFFFFFB,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFCFBFF,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFFFFFB,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFF8FFFF,
+0xFFF0FFFF,
+0xFF688DA0,
+0xFF18516E,
+0xFF1C5E80,
+0xFF226085,
+0xFF155176,
+0xFF175176,
+0xFF175377,
+0xFF14547A,
+0xFF12537B,
+0xFF10547B,
+0xFF105479,
+0xFF135673,
+0xFF155674,
+0xFF155578,
+0xFF155579,
+0xFF145679,
+0xFF145679,
+0xFF145679,
+0xFF145679,
+0xFF15577A,
+0xFF15577A,
+0xFF13577A,
+0xFF13577A,
+0xFF14587B,
+0xFF14587B,
+0xFF15597C,
+0xFF14587B,
+0xFF13577A,
+0xFF165A7D,
+0xFF1A6082,
+0xFF205F7E,
+0xFF1F4D67,
+0xFFE9FFFF,
+0xFFF8FFFF,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFEFDFB,
+0xFFFFFFFB,
+0xFFFBFFFD,
+0xFFFBFFFF,
+0xFFFFFFFD,
+0xFFFFFEFD,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFF8,
+0xFFFEFFF8,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFEFFFF,
+0xFFFFFFFD,
+0xFFFFFFFA,
+0xFFFCFFFF,
+0xFFEDFFFF,
+0xFF1D455F,
+0xFF235F83,
+0xFF1B6389,
+0xFF0E5A7C,
+0xFF125E80,
+0xFF115D81,
+0xFF115D81,
+0xFF125C81,
+0xFF125C81,
+0xFF135B81,
+0xFF135B81,
+0xFF135C7F,
+0xFF135C7F,
+0xFF125C7F,
+0xFF125C7F,
+0xFF115D7F,
+0xFF105C7E,
+0xFF115B7E,
+0xFF115B7E,
+0xFF115B7E,
+0xFF115B7E,
+0xFF115B80,
+0xFF105A7F,
+0xFF115A7D,
+0xFF115A7D,
+0xFF10597C,
+0xFF0F597C,
+0xFF115B7E,
+0xFF145E81,
+0xFF1A6384,
+0xFF1D5F7F,
+0xFF19526D,
+0xFF164559,
+0xFFBBD8E8,
+0xFFF2FFFF,
+0xFFF8FDFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFF9,
+0xFFF8F9F1,
+0xFFFFFFFA,
+0xFFFBFBF9,
+0xFFFEFFFF,
+0xFFFEFDFF,
+0xFFFFFEFB,
+0xFFFFFEF8,
+0xFFFFFEFD,
+0xFFFFFEFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFBFFFF,
+0xFFF8FFFF,
+0xFFF1FFFF,
+0xFF7B9CAB,
+0xFF1C4C63,
+0xFF206282,
+0xFF1E678A,
+0xFF135377,
+0xFF165276,
+0xFF185277,
+0xFF155175,
+0xFF145277,
+0xFF13547A,
+0xFF11557C,
+0xFF11557A,
+0xFF135673,
+0xFF145571,
+0xFF145575,
+0xFF135578,
+0xFF145679,
+0xFF145679,
+0xFF145679,
+0xFF145679,
+0xFF145679,
+0xFF145679,
+0xFF145679,
+0xFF125679,
+0xFF13577A,
+0xFF125679,
+0xFF14587B,
+0xFF14587B,
+0xFF125679,
+0xFF175B7E,
+0xFF1B5F82,
+0xFF205B79,
+0xFF65899F,
+0xFFEFFFFF,
+0xFFF7FFFF,
+0xFFFEFFFA,
+0xFFFFFEFF,
+0xFFFEFCFF,
+0xFFFFFEFD,
+0xFFFFFFFB,
+0xFFFBFFFD,
+0xFFFBFFFF,
+0xFFFFFFFD,
+0xFFFFFDFD,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFA,
+0xFFFEFFFA,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFF7FFFF,
+0xFF95B4C8,
+0xFF225371,
+0xFF216185,
+0xFF115B80,
+0xFF125E7E,
+0xFF105C7C,
+0xFF105A7D,
+0xFF105A7D,
+0xFF115B80,
+0xFF125A80,
+0xFF125A80,
+0xFF125A80,
+0xFF125B7E,
+0xFF115B7E,
+0xFF115B7E,
+0xFF115B7E,
+0xFF0F5B7D,
+0xFF0F5B7D,
+0xFF105A7D,
+0xFF105A7D,
+0xFF105A7D,
+0xFF105A7D,
+0xFF115A7D,
+0xFF115A7D,
+0xFF115A7D,
+0xFF115A7D,
+0xFF115A7D,
+0xFF125B7E,
+0xFF165F80,
+0xFF1D6283,
+0xFF20617F,
+0xFF1B546F,
+0xFF2F5C71,
+0xFFD6F7FF,
+0xFFEFFFFF,
+0xFFF8FFFF,
+0xFFFDFDFD,
+0xFFFFFFFD,
+0xFFFDFDFF,
+0xFFFFFFFF,
+0xFFFFFFFB,
+0xFFFFFFF8,
+0xFFFFFFFA,
+0xFFFFFFFD,
+0xFFFDFEFF,
+0xFFFFFFFF,
+0xFFFFFFFA,
+0xFFFFFEF8,
+0xFFFFFEFD,
+0xFFFFFEFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFEF9,
+0xFFFFFFFA,
+0xFFFFFFFF,
+0xFFFDFEFF,
+0xFFFCFFFF,
+0xFFFBFFFF,
+0xFFFAFFFF,
+0xFFFBFFFF,
+0xFFFEFFFD,
+0xFFFDFDFB,
+0xFFFEFDFB,
+0xFFFFFFFF,
+0xFFF7FEFF,
+0xFFF3FFFF,
+0xFFEDFFFF,
+0xFF698C9F,
+0xFF1B4D66,
+0xFF225F7C,
+0xFF206282,
+0xFF135879,
+0xFF115174,
+0xFF145374,
+0xFF145374,
+0xFF135273,
+0xFF145477,
+0xFF145477,
+0xFF135577,
+0xFF125476,
+0xFF125474,
+0xFF125572,
+0xFF135575,
+0xFF135577,
+0xFF145679,
+0xFF12567B,
+0xFF145679,
+0xFF145679,
+0xFF155578,
+0xFF165679,
+0xFF165679,
+0xFF155779,
+0xFF16587A,
+0xFF145678,
+0xFF14587B,
+0xFF13577A,
+0xFF115578,
+0xFF1D6184,
+0xFF1F6386,
+0xFF154B67,
+0xFFCFE7F3,
+0xFFF5FDFF,
+0xFFFEFFFF,
+0xFFFCFCFA,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFDFE,
+0xFFFFFFFD,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFB,
+0xFFFCFFFD,
+0xFFF6FFFF,
+0xFFEAFFFF,
+0xFF336178,
+0xFF24617E,
+0xFF1C6586,
+0xFF0D597B,
+0xFF0F5C7A,
+0xFF0F5A77,
+0xFF115A7B,
+0xFF13597B,
+0xFF13597D,
+0xFF115A7D,
+0xFF115A7D,
+0xFF105A7D,
+0xFF105A7F,
+0xFF0F5B7F,
+0xFF0F5B7F,
+0xFF105C80,
+0xFF105C7E,
+0xFF0E5A7C,
+0xFF0F5A7A,
+0xFF0F5A7A,
+0xFF105B7B,
+0xFF10597A,
+0xFF12587A,
+0xFF145A7E,
+0xFF145A7E,
+0xFF0F577D,
+0xFF166085,
+0xFF1D6689,
+0xFF1B607F,
+0xFF215E7A,
+0xFF174960,
+0xFF6B91A4,
+0xFFEBFFFF,
+0xFFEDFEFF,
+0xFFF9FFFF,
+0xFFFCFFFD,
+0xFFFDFFF9,
+0xFFFFFFFA,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFA,
+0xFFFFFEF9,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFCFFFF,
+0xFFFAFFFF,
+0xFFFBFFFF,
+0xFFFEFFFF,
+0xFFFEFFFA,
+0xFFFFFFFB,
+0xFFFFFFFF,
+0xFFF9FEFF,
+0xFFF4FFFF,
+0xFFE9FFFF,
+0xFF597F96,
+0xFF20526D,
+0xFF266382,
+0xFF1E6080,
+0xFF175979,
+0xFF115373,
+0xFF125373,
+0xFF125373,
+0xFF135474,
+0xFF165777,
+0xFF135474,
+0xFF135474,
+0xFF135474,
+0xFF135474,
+0xFF125474,
+0xFF135575,
+0xFF135575,
+0xFF135577,
+0xFF125679,
+0xFF12567B,
+0xFF145679,
+0xFF145678,
+0xFF155578,
+0xFF165777,
+0xFF165777,
+0xFF155779,
+0xFF135577,
+0xFF165A7D,
+0xFF13577A,
+0xFF16587B,
+0xFF145678,
+0xFF216184,
+0xFF1D5C7D,
+0xFF3A6880,
+0xFFEFFDFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFCFCFC,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFCFCFC,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFD,
+0xFFFFFFFB,
+0xFFFFFFFA,
+0xFFFCFFFF,
+0xFFF2FFFF,
+0xFFC0E1F0,
+0xFF184B66,
+0xFF1D5D80,
+0xFF176186,
+0xFF0C587C,
+0xFF156080,
+0xFF115878,
+0xFF115779,
+0xFF125679,
+0xFF12587A,
+0xFF12587A,
+0xFF10597C,
+0xFF0F597C,
+0xFF0E587D,
+0xFF0E587D,
+0xFF115B80,
+0xFF0F597C,
+0xFF0E587B,
+0xFF105B7B,
+0xFF135C7D,
+0xFF135C7D,
+0xFF115A7B,
+0xFF13597B,
+0xFF165A7D,
+0xFF115578,
+0xFF1A5E81,
+0xFF1C6083,
+0xFF1F6181,
+0xFF1D5D79,
+0xFF1A506A,
+0xFF305D72,
+0xFFC2E1F3,
+0xFFECFFFF,
+0xFFF7FFFF,
+0xFFFBFFFF,
+0xFFFEFFFF,
+0xFFFFFFFD,
+0xFFFEFFFB,
+0xFFFDFFFA,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFCF9,
+0xFFFFFDF9,
+0xFFFEFDF9,
+0xFFFAFEFF,
+0xFFF2FFFF,
+0xFFDEF9FF,
+0xFF365E78,
+0xFF1B5072,
+0xFF246084,
+0xFF216184,
+0xFF155779,
+0xFF0F4F72,
+0xFF115174,
+0xFF135376,
+0xFF125275,
+0xFF145376,
+0xFF145376,
+0xFF145376,
+0xFF145376,
+0xFF135376,
+0xFF135376,
+0xFF135376,
+0xFF145477,
+0xFF135577,
+0xFF135577,
+0xFF105477,
+0xFF105477,
+0xFF125476,
+0xFF125474,
+0xFF135474,
+0xFF145575,
+0xFF135575,
+0xFF135577,
+0xFF14587D,
+0xFF12567B,
+0xFF0F5378,
+0xFF18587C,
+0xFF1A5678,
+0xFF255E7C,
+0xFF255875,
+0xFF96BBCE,
+0xFFF5FFFF,
+0xFFFFFFFF,
+0xFFFCFCFC,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFDFDFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFCFFFF,
+0xFFF2FFFF,
+0xFF5F7E92,
+0xFF245575,
+0xFF25638A,
+0xFF135882,
+0xFF115882,
+0xFF13577E,
+0xFF14587D,
+0xFF15597C,
+0xFF145A7C,
+0xFF145A7C,
+0xFF145A7C,
+0xFF145A7E,
+0xFF125B7E,
+0xFF125B7E,
+0xFF125B7E,
+0xFF10597C,
+0xFF125B7E,
+0xFF155B7F,
+0xFF145A7C,
+0xFF125679,
+0xFF145678,
+0xFF16587A,
+0xFF175C7D,
+0xFF185C7F,
+0xFF25698C,
+0xFF1C5E7E,
+0xFF225F7B,
+0xFF1F5369,
+0xFF30596B,
+0xFF98B3C4,
+0xFFF2FFFF,
+0xFFF8FFFF,
+0xFFFEFEFF,
+0xFFFBFAFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFCFDFF,
+0xFFFFFEFF,
+0xFFFEFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFEFEFE,
+0xFFFFFFFF,
+0xFFFFFDFE,
+0xFFFFFEFD,
+0xFFFFFEFD,
+0xFFFFFCFB,
+0xFFFFFFFF,
+0xFFF8FFFF,
+0xFFF1FFFF,
+0xFF9DBDCC,
+0xFF214E65,
+0xFF215876,
+0xFF215F84,
+0xFF206189,
+0xFF0F5174,
+0xFF0B4D6F,
+0xFF0E4E72,
+0xFF105073,
+0xFF0F4F73,
+0xFF115174,
+0xFF135176,
+0xFF0F4E71,
+0xFF125075,
+0xFF125174,
+0xFF115175,
+0xFF105073,
+0xFF105074,
+0xFF105073,
+0xFF0F5174,
+0xFF0F5174,
+0xFF0F5579,
+0xFF0F5577,
+0xFF105576,
+0xFF125474,
+0xFF135474,
+0xFF145575,
+0xFF135577,
+0xFF115578,
+0xFF0E537A,
+0xFF0E537A,
+0xFF14587F,
+0xFF1A587D,
+0xFF296182,
+0xFF30627D,
+0xFF19435B,
+0xFFE8FFFF,
+0xFFF6FFFF,
+0xFFFEFEFE,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFEFE,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFF9FFFF,
+0xFFEEFFFF,
+0xFF26465B,
+0xFF2D5E7F,
+0xFF1F5D84,
+0xFF135882,
+0xFF0D547E,
+0xFF185C83,
+0xFF16587B,
+0xFF14587B,
+0xFF13597B,
+0xFF13597B,
+0xFF13597B,
+0xFF13597D,
+0xFF13597D,
+0xFF13597D,
+0xFF14587D,
+0xFF14587D,
+0xFF165A7D,
+0xFF195B7E,
+0xFF1B5B7E,
+0xFF1F5E81,
+0xFF236283,
+0xFF246384,
+0xFF256183,
+0xFF246082,
+0xFF1D5674,
+0xFF1B4E69,
+0xFF2F5C71,
+0xFF95B6C5,
+0xFFEEFFFF,
+0xFFF5FFFF,
+0xFFFCFDFF,
+0xFFFFFDFF,
+0xFFFDF7F9,
+0xFFFFFDFF,
+0xFFFCFAFD,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFDFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFEFDFF,
+0xFFFDFCFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFEFDF9,
+0xFFFFFEFF,
+0xFFFBFFFF,
+0xFFF1FFFF,
+0xFFD0EDFB,
+0xFF3F6C7F,
+0xFF195168,
+0xFF1A5B77,
+0xFF206584,
+0xFF1E6384,
+0xFF1C6083,
+0xFF206285,
+0xFF226286,
+0xFF24648A,
+0xFF236387,
+0xFF1F5F85,
+0xFF226286,
+0xFF25658B,
+0xFF226286,
+0xFF236389,
+0xFF236387,
+0xFF226288,
+0xFF226286,
+0xFF226288,
+0xFF226286,
+0xFF226288,
+0xFF216288,
+0xFF1C6286,
+0xFF1C6284,
+0xFF1D6283,
+0xFF1F6181,
+0xFF206181,
+0xFF206083,
+0xFF206285,
+0xFF1E6289,
+0xFF1B628C,
+0xFF1B628C,
+0xFF20638D,
+0xFF1F5D82,
+0xFF2A5F7F,
+0xFF19455E,
+0xFF95B8CC,
+0xFFEDFFFF,
+0xFFF9FFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFCFCFC,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFCFFFF,
+0xFFFBFFFF,
+0xFFFBFFFF,
+0xFFFBFFFF,
+0xFFF9FFFF,
+0xFFF5FFFF,
+0xFFABC3CD,
+0xFF22485B,
+0xFF275F7A,
+0xFF1D5F81,
+0xFF1C6588,
+0xFF1B6588,
+0xFF1C6383,
+0xFF1E6382,
+0xFF1D6184,
+0xFF1D6186,
+0xFF1D6186,
+0xFF1D6186,
+0xFF1D6186,
+0xFF1D6186,
+0xFF1D6186,
+0xFF1F6086,
+0xFF216185,
+0xFF206084,
+0xFF205E83,
+0xFF246084,
+0xFF245E83,
+0xFF21597C,
+0xFF1A5275,
+0xFF1A4C6D,
+0xFF24506B,
+0xFF5E829A,
+0xFFBDD8EB,
+0xFFF0FFFF,
+0xFFF2FFFF,
+0xFFF7FFFF,
+0xFFFCFFFF,
+0xFFFEFFFD,
+0xFFF9F9F7,
+0xFFFFFFFD,
+0xFFFFFDFE,
+0xFFFEFCFF,
+0xFFFFFDFF,
+0xFFFFFDFF,
+0xFFFFFAFF,
+0xFFFFFCFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFDFF,
+0xFFFFFEFF,
+0xFFFEFEFF,
+0xFFFFFFFD,
+0xFFFFFFFB,
+0xFFFFFFFD,
+0xFFFDFEFF,
+0xFFE2EBF2,
+0xFF5C6F7E,
+0xFF1D3E51,
+0xFF215168,
+0xFF1F5971,
+0xFF1D5B74,
+0xFF1B5972,
+0xFF1B556D,
+0xFF205670,
+0xFF215675,
+0xFF1F5473,
+0xFF1F5473,
+0xFF1F5473,
+0xFF1D5271,
+0xFF1E5372,
+0xFF1F5473,
+0xFF1F5473,
+0xFF1E5372,
+0xFF1E5372,
+0xFF1E5372,
+0xFF1E5372,
+0xFF1E5372,
+0xFF1E5372,
+0xFF1F5473,
+0xFF1E5573,
+0xFF1D5673,
+0xFF1D5673,
+0xFF1E5671,
+0xFF1F556F,
+0xFF21546F,
+0xFF1F5571,
+0xFF1E5574,
+0xFF1D5576,
+0xFF1B5779,
+0xFF175274,
+0xFF1D5375,
+0xFF20516F,
+0xFF1D455E,
+0xFF8DACBE,
+0xFFEDFFFF,
+0xFFF3FFFF,
+0xFFFCFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFBFFFF,
+0xFFFBFFFF,
+0xFFF7FFFF,
+0xFFDEF2FB,
+0xFF204150,
+0xFF28566D,
+0xFF215974,
+0xFF195472,
+0xFF185571,
+0xFF215B73,
+0xFF1A5269,
+0xFF1E5671,
+0xFF1E5774,
+0xFF1F5674,
+0xFF1F5674,
+0xFF1F5674,
+0xFF1F5674,
+0xFF205574,
+0xFF1F5473,
+0xFF1F5271,
+0xFF1F506E,
+0xFF204F6B,
+0xFF214E6B,
+0xFF24506B,
+0xFF406985,
+0xFF78A2BB,
+0xFFB0D4EC,
+0xFFEAFFFF,
+0xFFEFFFFF,
+0xFFF2FCFF,
+0xFFFBFFFF,
+0xFFFFFEFF,
+0xFFFFFDFE,
+0xFFFFFFFB,
+0xFFFDFEF9,
+0xFFFEFFFD,
+0xFFFCFFFD,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFDFF,
+0xFFFFFCFF,
+0xFFFFFCFE,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFDFE,
+0xFFFFFEFD,
+0xFFFFFDFA,
+0xFFFFFEFA,
+0xFFFFFEFA,
+0xFFFFFFFF,
+0xFFFAFDFF,
+0xFFDBE2EC,
+0xFF7D8A9A,
+0xFF8CA1B4,
+0xFF7B97AC,
+0xFF81A1B6,
+0xFF7D9EB1,
+0xFF7F9EB0,
+0xFF859FAE,
+0xFF869DAD,
+0xFF839FAD,
+0xFF829FAF,
+0xFF819EAE,
+0xFF83A0B0,
+0xFF84A1B1,
+0xFF83A0B0,
+0xFF819EAE,
+0xFF829FAF,
+0xFF829FAF,
+0xFF829FAF,
+0xFF829FAF,
+0xFF829FAF,
+0xFF829FAF,
+0xFF83A0B0,
+0xFF83A0B0,
+0xFF81A1B0,
+0xFF7FA0AF,
+0xFF7FA1AD,
+0xFF80A0AD,
+0xFF82A0AB,
+0xFF82A0AB,
+0xFF80A0AD,
+0xFF7FA0B1,
+0xFF7DA0B3,
+0xFF7DA0B4,
+0xFF7DA0B3,
+0xFF81A0B2,
+0xFF97B1BE,
+0xFFE6F7FF,
+0xFFF8FFFF,
+0xFFFBFDFC,
+0xFFFFFFFB,
+0xFFFFFFFD,
+0xFFFDFDFD,
+0xFFFDFDFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFEFE,
+0xFFFEFEFE,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFEFFFF,
+0xFFF8FFFF,
+0xFFCDDDEA,
+0xFF7892A3,
+0xFF7F9EB3,
+0xFF83A3B8,
+0xFF7E9DB1,
+0xFF809BAC,
+0xFF87A3B1,
+0xFF80A0AD,
+0xFF7FA0AF,
+0xFF80A0AF,
+0xFF80A0AF,
+0xFF80A0AF,
+0xFF80A0AF,
+0xFF829FAF,
+0xFF839FAD,
+0xFF92AEBC,
+0xFF9EB8C5,
+0xFFBAD2DE,
+0xFFDCF2FF,
+0xFFF0FFFF,
+0xFFF1FFFF,
+0xFFF0FFFF,
+0xFFF4FFFF,
+0xFFF5FFFF,
+0xFFF8FFFF,
+0xFFFCFFFF,
+0xFFFFFFFF,
+0xFFFFFEFD,
+0xFFFFFCFC,
+0xFFFFFCFC,
+0xFFFFFEFF,
+0xFFFEFFFF,
+0xFFF3F9F9,
+0xFFF9FFFF,
+0xFFF8FFFF,
+0xFFFCFFFF,
+0xFFFFFFFD,
+0xFFFFFEFB,
+0xFFFFFBF8,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFB,
+0xFFFFFEFA,
+0xFFFDFCF8,
+0xFFFFFFFB,
+0xFFFFFFFD,
+0xFFF9FBFA,
+0xFFFCFFFF,
+0xFFF7FEFF,
+0xFFF8FFFF,
+0xFFF0FCFF,
+0xFFF4FFFF,
+0xFFF1FFFF,
+0xFFF4FFFF,
+0xFFF7FFFF,
+0xFFF8FFFF,
+0xFFF9FFFF,
+0xFFF5FFFF,
+0xFFF4FFFF,
+0xFFF4FFFF,
+0xFFF2FFFF,
+0xFFF4FFFF,
+0xFFF4FFFF,
+0xFFF3FFFF,
+0xFFF4FFFF,
+0xFFF4FFFF,
+0xFFF4FFFF,
+0xFFF4FFFF,
+0xFFF4FFFF,
+0xFFF3FFFF,
+0xFFF3FFFF,
+0xFFF3FFFF,
+0xFFF3FFFF,
+0xFFF4FFFF,
+0xFFF4FFFF,
+0xFFF4FFFF,
+0xFFF4FFFF,
+0xFFF4FFFF,
+0xFFF4FFFF,
+0xFFF2FFFF,
+0xFFF1FFFF,
+0xFFF0FFFF,
+0xFFF1FFFF,
+0xFFF5FFFF,
+0xFFF5FEFF,
+0xFFFCFFFF,
+0xFFFFFEFA,
+0xFFFFFEF8,
+0xFFFFFCF6,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFDFDFD,
+0xFFFEFEFE,
+0xFFFEFEFE,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFDFEFF,
+0xFFFAFEFF,
+0xFFF5FFFF,
+0xFFF4FFFF,
+0xFFF0FEFF,
+0xFFF5FFFF,
+0xFFF8FFFF,
+0xFFF7FFFF,
+0xFFF5FFFF,
+0xFFF4FFFF,
+0xFFF4FFFF,
+0xFFF4FFFF,
+0xFFF4FFFF,
+0xFFF5FFFF,
+0xFFF5FFFF,
+0xFFF5FFFF,
+0xFFF7FFFF,
+0xFFF7FFFF,
+0xFFF7FFFF,
+0xFFF8FFFF,
+0xFFFBFFFF,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFCFFFD,
+0xFFFDFFFA,
+0xFFFFFFFB,
+0xFFFEFDF9,
+0xFFFFFCF9,
+0xFFFFFDFD,
+0xFFFFFBFD,
+0xFFFFFEFF,
+0xFFFCFDFF,
+0xFFFBFFFF,
+0xFFF8FFFF,
+0xFFF6FFFD,
+0xFFFBFFFD,
+0xFFFCFEFB,
+0xFFFEFDF9,
+0xFFFFFEFB,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFBFFFD,
+0xFFF9FFFD,
+0xFFFCFFFD,
+0xFFFCFFFD,
+0xFFFCFFFD,
+0xFFFCFFFD,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFBFFFF,
+0xFFFBFFFF,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFCFFFF,
+0xFFFBFFFF,
+0xFFFBFFFF,
+0xFFFBFFFF,
+0xFFFBFFFF,
+0xFFFBFFFF,
+0xFFFBFFFF,
+0xFFFBFFFF,
+0xFFFBFFFF,
+0xFFFBFFFF,
+0xFFFBFFFF,
+0xFFFBFFFF,
+0xFFFBFFFF,
+0xFFFBFFFF,
+0xFFFBFFFF,
+0xFFFBFFFF,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFBFFFF,
+0xFFF9FFFF,
+0xFFF9FFFF,
+0xFFF9FFFF,
+0xFFF9FFFF,
+0xFFF9FFFF,
+0xFFFBFFFF,
+0xFFFCFFFF,
+0xFFFEFFFF,
+0xFFFFFFFD,
+0xFFFFFFFB,
+0xFFFFFFFA,
+0xFFFFFEFB,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFEFFFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFEFFFF,
+0xFFFCFFFF,
+0xFFF9FFFF,
+0xFFF9FFFF,
+0xFFF9FFFF,
+0xFFFCFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFCFFFF,
+0xFFFBFFFF,
+0xFFFBFFFF,
+0xFFFBFFFF,
+0xFFFBFFFF,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFEFFFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFB,
+0xFFFFFFFD,
+0xFFFFFFFB,
+0xFFFCFFFB,
+0xFFFCFFFB,
+0xFFFCFFFB,
+0xFFFEFFFD,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFEFFFD,
+0xFFFBFFFD,
+0xFFFBFFFD,
+0xFFFCFFFD,
+0xFFFEFFFD,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFCFFFF,
+0xFFF9FFFF,
+0xFFF8FFFF,
+0xFFFCFFFF,
+0xFFFEFFFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFEFFFD,
+0xFFFEFFFD,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFD,
+0xFFFFFFFD,
+0xFFFFFFFB,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFBFFFF,
+0xFFFCFFFF,
+0xFFFFFFFD,
+0xFFFFFFFA,
+0xFFFFFEFB,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFB,
+0xFFFFFFFB,
+0xFFFFFFFB,
+0xFFFFFFFA,
+0xFFFFFEFB,
+0xFFFFFFFA,
+0xFFFEFFFA,
+0xFFFCFFFB,
+0xFFFEFFFD,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFD,
+0xFFFEFFFB,
+0xFFFEFFFB,
+0xFFFEFFFB,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFBFFFF,
+0xFFFCFFFF,
+0xFFFFFDFF,
+0xFFFFFCFF,
+0xFFFFFBFF,
+0xFFFFFCFD,
+0xFFFFFEFB,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFEFFFF,
+0xFFFBFFFF,
+0xFFFBFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFDFD,
+0xFFFFFDFD,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFD,
+0xFFFFFEFB,
+0xFFFFFEFB,
+0xFFFFFEFD,
+0xFFFFFFFF,
+0xFFFCFFFF,
+0xFFFBFFFF,
+0xFFFBFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFEFD,
+0xFFFFFEFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFBFFFF,
+0xFFFCFFFF,
+0xFFFEFFFD,
+0xFFFFFFFB,
+0xFFFFFFFB,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFB,
+0xFFFFFFFD,
+0xFFFFFFFB,
+0xFFFFFFFB,
+0xFFFFFFFB,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFEFFFF,
+0xFFFBFFFF,
+0xFFFBFFFF,
+0xFFFBFFFD,
+0xFFFEFFFB,
+0xFFFFFFFB,
+0xFFFFFEFB,
+0xFFFFFDFD,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFFFEFF,
+0xFFFFFDFF,
+0xFFFFFCFF,
+0xFFFFFBFF,
+0xFFFFFCFD,
+0xFFFFFDFD,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFEFFFF,
+0xFFFBFFFF,
+0xFFFBFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFD,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFD,
+0xFFFFFEFB,
+0xFFFFFDFD,
+0xFFFFFFFD,
+0xFFFEFFFF,
+0xFFFBFFFF,
+0xFFF8FFFF,
+0xFFF9FFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFEFD,
+0xFFFFFEFD,
+0xFFFFFEFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFDFD,
+0xFFFFFDFD,
+0xFFFFFDFF,
+0xFFFFFDFF,
+0xFFFFFEFF,
+0xFFFEFFFF,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFCFFFD,
+0xFFFFFFFB,
+0xFFFFFFFB,
+0xFFFFFEFB,
+0xFFFFFEFD,
+0xFFFFFDFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFB,
+0xFFFFFFFB,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFB,
+0xFFFFFEFB,
+0xFFFFFEFB,
+0xFFFFFEFD,
+0xFFFFFEFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFEFFFF,
+0xFFFBFFFF,
+0xFFF9FFFF,
+0xFFFBFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFD,
+0xFFFEFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFDFF,
+0xFFFFFDFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFEFF,
+0xFFFFFCFD,
+0xFFFFFCFD,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFDFF,
+0xFFFFFDFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFB,
+0xFFFFFFFB,
+0xFFFFFFFD,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFB,
+0xFFFFFEFB,
+0xFFFFFEFB,
+0xFFFFFEFB,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFCFFFD,
+0xFFFEFFFD,
+0xFFFEFFFD,
+0xFFFEFFFD,
+0xFFFEFFFD,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFDFF,
+0xFFFFFDFF,
+0xFFFFFDFF,
+0xFFFFFDFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFDFF,
+0xFFFFFDFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFEFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFEFFFF,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFEFFFF,
+0xFFFFFFFD,
+0xFFFFFEFB,
+0xFFFFFEFB,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFEFFFD,
+0xFFFCFFFD,
+0xFFFEFFFD,
+0xFFFEFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFFFEFB,
+0xFFFFFFFB,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFCFFFF,
+0xFFFEFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFEFFFB,
+0xFFFEFFFD,
+0xFFFEFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFCFFFF,
+0xFFFEFFFF,
+0xFFFEFFFD,
+0xFFFEFFFB,
+0xFFFEFFFA,
+0xFFFEFFFA,
+0xFFFFFFFB,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFEFFFD,
+0xFFFFFFFD,
+0xFFFFFEFD,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFEFFFF,
+0xFFFBFFFF,
+0xFFFBFFFF,
+0xFFFCFFFF,
+0xFFFFFFFD,
+0xFFFFFEFB,
+0xFFFFFEFB,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFEFFFD,
+0xFFFCFFFD,
+0xFFFEFFFD,
+0xFFFFFFFB,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFD,
+0xFFFFFEFB,
+0xFFFFFEFB,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFD,
+0xFFFEFFFB,
+0xFFFEFFFD,
+0xFFFEFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFCFFFF,
+0xFFFBFFFF,
+0xFFFCFFFF,
+0xFFFEFFFD,
+0xFFFEFFFB,
+0xFFFEFFFA,
+0xFFFEFFFA,
+0xFFFEFFFB,
+0xFFFEFFFD,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFDFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFD,
+0xFFFEFFFD,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFA,
+0xFFFFFFFB,
+0xFFFCFFFF,
+0xFFFBFFFF,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFEFFFB,
+0xFFFEFFFB,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFFFA,
+0xFFFFFFF8,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFEFFFD,
+0xFFFEFFFD,
+0xFFFFFFFB,
+0xFFFFFFFA,
+0xFFFFFEFB,
+0xFFFFFFFD,
+0xFFFEFFFF,
+0xFFFCFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFEFFFF,
+0xFFFCFFFF,
+0xFFFEFFFF,
+0xFFFFFDFF,
+0xFFFFFEFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFD,
+0xFFFCFFFB,
+0xFFFCFFFB,
+0xFFFFFFFF,
+0xFFFFFDFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFEFFFA,
+0xFFFEFFFB,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFCFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFD,
+0xFFFEFFFD,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFEFFFD,
+0xFFFEFFFD,
+0xFFFEFFFF,
+0xFFFEFFFD,
+0xFFFFFFFB,
+0xFFFFFFFB,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFA,
+0xFFFFFFFB,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFCFFFB,
+0xFFFCFFFB,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFF8,
+0xFFFFFFF8,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFFFFFB,
+0xFFFFFFFB,
+0xFFFEFFFD,
+0xFFFFFFFD,
+0xFFFFFFFB,
+0xFFFFFEFB,
+0xFFFFFEFB,
+0xFFFFFEFF,
+0xFFFEFFFF,
+0xFFFCFFFF,
+0xFFFEFFFF,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFDFF,
+0xFFFFFEFF,
+0xFFFEFFFD,
+0xFFFCFFFB,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFD,
+0xFFFBFFFB,
+0xFFFCFFFB,
+0xFFFFFEFF,
+0xFFFFFDFF,
+0xFFFFFDFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFCFFFA,
+0xFFFEFFFA,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFD,
+0xFFFEFFFD,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFEFFFD,
+0xFFFEFFFD,
+0xFFFEFFFF,
+0xFFFEFFFD,
+0xFFFFFFFB,
+0xFFFFFFFB,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFCFFFF,
+0xFFFCFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFDFF,
+0xFFFFFEFF,
+0xFFFCFFFF,
+0xFFFBFFFF,
+0xFFFCFFFF,
+0xFFFEFFFD,
+0xFFFFFFFB,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFD,
+0xFFFFFFFB,
+0xFFFFFFFB,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFB,
+0xFFFFFFFB,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFD,
+0xFFFFFDFD,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFCFFFF,
+0xFFFBFFFF,
+0xFFFCFFFB,
+0xFFFCFFFB,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFB,
+0xFFFCFFF6,
+0xFFFCFFF6,
+0xFFFEFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFCFFFD,
+0xFFFCFFFF,
+0xFFFFFEFF,
+0xFFFFFDFF,
+0xFFFFFDFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFCFFFB,
+0xFFFEFFFB,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFEFFFF,
+0xFFFCFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFBFFFF,
+0xFFFCFFFF,
+0xFFFFFEFD,
+0xFFFFFEFD,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFCFD,
+0xFFFFFDFF,
+0xFFFEFFFF,
+0xFFFBFFFF,
+0xFFFEFFFF,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFD,
+0xFFFFFFFB,
+0xFFFEFFFD,
+0xFFFCFFFF,
+0xFFFEFFFF,
+0xFFFFFEFB,
+0xFFFFFEFA,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFCFFFF,
+0xFFFBFFFF,
+0xFFFBFFFD,
+0xFFFCFFFB,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFFFB,
+0xFFFCFFF8,
+0xFFFCFFF8,
+0xFFFEFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFCFFFF,
+0xFFFEFFFF,
+0xFFFFFEFF,
+0xFFFFFDFF,
+0xFFFFFDFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFEFFFD,
+0xFFFEFFFD,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFCFFFF,
+0xFFFEFFFF,
+0xFFFFFCFF,
+0xFFFFFDFF,
+0xFFFEFFFD,
+0xFFFEFFFD,
+0xFFFFFDFD,
+0xFFFFFDFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFDFF,
+0xFFFFFCFF,
+0xFFFFFDFF,
+0xFFFEFFFF,
+0xFFFBFFFF,
+0xFFFBFFFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFBFFFF,
+0xFFFBFFFF,
+0xFFFBFFFF,
+0xFFFBFFFF,
+0xFFFCFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFBFFFF,
+0xFFF8FFFF,
+0xFFF9FFFF,
+0xFFFFFFFA,
+0xFFFFFFF8,
+0xFFFFFFF8,
+0xFFFFFFFB,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFD,
+0xFFFEFFFD,
+0xFFFFFFFD,
+0xFFFFFDFF,
+0xFFFFFEFF,
+0xFFFEFFFF,
+0xFFFCFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFEFF,
+0xFFFFFDFF,
+0xFFFFFEFD,
+0xFFFFFEFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFDFF,
+0xFFFFFFFD,
+0xFFFFFFFB,
+0xFFFEFFFD,
+0xFFFEFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFCFFFF,
+0xFFFFFFFF,
+0xFFFFFDFF,
+0xFFFFFDFD,
+0xFFFCFFFB,
+0xFFFCFFFB,
+0xFFFFFEFF,
+0xFFFFFDFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFDFF,
+0xFFFFFCFF,
+0xFFFFFDFF,
+0xFFFEFFFF,
+0xFFFBFFFF,
+0xFFFBFFFF,
+0xFFFFFFFD,
+0xFFFFFEFD,
+0xFFFFFFFF,
+0xFFFCFFFF,
+0xFFFBFFFF,
+0xFFF9FFFF,
+0xFFFBFFFF,
+0xFFFBFFFF,
+0xFFFBFFFF,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFEFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFEFFFF,
+0xFFFBFFFF,
+0xFFF8FFFF,
+0xFFF9FFFF,
+0xFFFFFFFB,
+0xFFFFFFFA,
+0xFFFFFFF8,
+0xFFFFFFFA,
+0xFFFFFEFD,
+0xFFFFFEFF,
+0xFFFEFFFF,
+0xFFFCFFFF,
+0xFFFCFFFD,
+0xFFFFFFFF,
+0xFFFFFCFF,
+0xFFFFFBFF,
+0xFFFFFDFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFD,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFDFF,
+0xFFFFFDFF,
+0xFFFFFFFD,
+0xFFFFFFFB,
+0xFFFFFFFD,
+0xFFFEFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFB,
+0xFFFFFFFB,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFA,
+0xFFFEFFF8,
+0xFFFCFFFA,
+0xFFFEFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFD,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFEFFFD,
+0xFFFEFFFB,
+0xFFFEFFFD,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFEFFFF,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFEFFFF,
+0xFFFEFFFD,
+0xFFFFFFFD,
+0xFFFFFDFF,
+0xFFFFFDFF,
+0xFFFFFEFB,
+0xFFFFFFFA,
+0xFFFFFDFD,
+0xFFFFFDFF,
+0xFFFEFFFF,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFFFFFF,
+0xFFFFFAFF,
+0xFFFFFBFF,
+0xFFFFFDFD,
+0xFFFFFFFB,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFFFFFB,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFDFF,
+0xFFFFFDFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFEFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFFFFFB,
+0xFFFFFFFB,
+0xFFFEFFFD,
+0xFFFEFFFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFEFFFF,
+0xFFFEFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFEFFFB,
+0xFFFEFFFB,
+0xFFFEFFFB,
+0xFFFEFFFD,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFD,
+0xFFFFFFFD,
+0xFFFEFFFD,
+0xFFFEFFFF,
+0xFFFFFFFD,
+0xFFFFFFFB,
+0xFFFFFFFB,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFEFFFD,
+0xFFFEFFFD,
+0xFFFFFFFA,
+0xFFFFFFF8,
+0xFFFFFFFB,
+0xFFFFFFFD,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFEFB,
+0xFFFFFEFB,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFEFD,
+0xFFFFFDFF,
+0xFFFFFDFF,
+0xFFFFFEFF,
+0xFFFFFDFF,
+0xFFFFFDFF,
+0xFFFFFDFF,
+0xFFFEFFFF,
+0xFFFCFFFF,
+0xFFFCFFFD,
+0xFFFFFFFF,
+0xFFFFFBFF,
+0xFFFFFBFF,
+0xFFFFFEFB,
+0xFFFFFFFA,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFDFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFEFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFFFFFB,
+0xFFFFFFFB,
+0xFFFEFFFD,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFEFFFF,
+0xFFFEFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFDFB,
+0xFFFFFFFD,
+0xFFFDFFFE,
+0xFFFEFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFFFFFB,
+0xFFFFFFFF,
+0xFFFEFCFD,
+0xFFFFFDFE,
+0xFFFFFEFF,
+0xFFFEFDFF,
+0xFFFFFFFF,
+0xFFFFFEFA,
+0xFFFFFFFB,
+0xFFFBFFFF,
+0xFFFCFFFF,
+0xFFFFFFFB,
+0xFFFFFFFA,
+0xFFFFFEFA,
+0xFFFEFDF9,
+0xFFFFFEF8,
+0xFFFFFDF7,
+0xFFFFFEFB,
+0xFFFFFEFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFA,
+0xFFFFFEF8,
+0xFFFFFFFA,
+0xFFFFFFFB,
+0xFFFFFFFD,
+0xFFFFFDFE,
+0xFFFEFFFF,
+0xFFFDFEFF,
+0xFFFDFCFF,
+0xFFFFFDFF,
+0xFFFFFCFF,
+0xFFFFFDFF,
+0xFFFFFEFF,
+0xFFFFFFFB,
+0xFFFEFFFA,
+0xFFFEFFFB,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFDFF,
+0xFFFFFDFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFEFCFD,
+0xFFFFFFFD,
+0xFFFEFFFD,
+0xFFFDFFFC,
+0xFFFCFEFD,
+0xFFFFFFFF,
+0xFFFDFDFD,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFDFF,
+0xFFFFFEFF,
+0xFFFFFFFB,
+0xFFFBFCF7,
+0xFFFEFFFD,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFEFFFF,
+0xFFFFFFFD,
+0xFFFFFFFB,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFEFFFD,
+0xFFFEFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFDFBFC,
+0xFFFEFFFF,
+0xFFFAFBFF,
+0xFFFDFDFF,
+0xFFFFFEFF,
+0xFFFEFEFC,
+0xFFFFFFFB,
+0xFFFCFEFD,
+0xFFFEFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFCFBF9,
+0xFFFFFEFC,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFFFFFB,
+0xFFFEFEFC,
+0xFFFBFFFF,
+0xFFF8FFFF,
+0xFFFCFFFF,
+0xFFFEFEFE,
+0xFFFFFEFD,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFEFA,
+0xFFFFFEF8,
+0xFFFFFFFA,
+0xFFFFFFFB,
+0xFFFFFDFE,
+0xFFFFFFFF,
+0xFFFDFDFB,
+0xFFFDFFFE,
+0xFFFCFFFF,
+0xFFFCFEFF,
+0xFFFCFCFF,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFFFFFA,
+0xFFFEFFF8,
+0xFFFCFFFA,
+0xFFFEFFFD,
+0xFFFEFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFEFC,
+0xFFFBFDFC,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFCFF,
+0xFFFFFDFE,
+0xFFFFFFFB,
+0xFFFEFFFB,
+0xFFFBFFFF,
+0xFFFAFDFF,
+0xFFFCFFFF,
+0xFFF8FBFF,
+0xFFFEFFFD,
+0xFFFFFFFB,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFD,
+0xFFFEFFFB,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFF8FB,
+0xFFFFFDFF,
+0xFFFEFFFF,
+0xFFFBFFFF,
+0xFFFCFFFF,
+0xFFFAFBFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFCFFFF,
+0xFFFAFFFF,
+0xFFF5FDFF,
+0xFFF7FEFF,
+0xFFFAFFFF,
+0xFFFEFFFD,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFAFAF8,
+0xFFFFFFFD,
+0xFFF8FFFF,
+0xFFEEFFFF,
+0xFFEAFFFF,
+0xFFEBFFFF,
+0xFFF1FFFF,
+0xFFF9FFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFEFB,
+0xFFFFFFFA,
+0xFFFFFFFD,
+0xFFFEFFFF,
+0xFFFDFDFF,
+0xFFFFFDFE,
+0xFFFFFEF8,
+0xFFFFFEF9,
+0xFFF9FFFF,
+0xFFF2FCFF,
+0xFFF8FFFF,
+0xFFF7FFFF,
+0xFFFEFFFB,
+0xFFFFFFF8,
+0xFFFCFFFA,
+0xFFFCFFFB,
+0xFFFEFFFA,
+0xFFFEFFFB,
+0xFFFBFFFF,
+0xFFFBFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFEFDF9,
+0xFFFFFFFD,
+0xFFFCFFFF,
+0xFFFBFFFF,
+0xFFF6FDFF,
+0xFFF7FCFF,
+0xFFFCFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFDFF,
+0xFFFFFEFF,
+0xFFFDFEF8,
+0xFFFEFFFD,
+0xFFFCFFFF,
+0xFFFBFFFF,
+0xFFFBFFFF,
+0xFFFCFFFF,
+0xFFFEFFFF,
+0xFFFFFFFB,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFEFFFB,
+0xFFFEFFFB,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFAFD,
+0xFFFFFDFF,
+0xFFF9FDFE,
+0xFFF8FFFF,
+0xFFFBFFFF,
+0xFFF8FFFF,
+0xFFDFF3FE,
+0xFFDAF6FF,
+0xFFD9F8FF,
+0xFFDDFFFF,
+0xFFD2F7FF,
+0xFFDEFDFF,
+0xFFF5FFFF,
+0xFFFFFFFA,
+0xFFFBFBFB,
+0xFFFFFEFF,
+0xFFFDFCFA,
+0xFFFFFFFD,
+0xFFFEFFFF,
+0xFFF1FFFF,
+0xFFB4D8EE,
+0xFF6695B1,
+0xFF6A94AD,
+0xFFD7F8FF,
+0xFFF2FFFF,
+0xFFFBFFFF,
+0xFFFCFFFF,
+0xFFFFFFFF,
+0xFFFFFEFD,
+0xFFFFFFFD,
+0xFFFEFFFF,
+0xFFFCFFFF,
+0xFFFFFEFF,
+0xFFFCFFFF,
+0xFFF7FFFF,
+0xFFEDFFFF,
+0xFFDAFFFF,
+0xFFBAE3F9,
+0xFFA9C6D6,
+0xFFF2FFFF,
+0xFFFCFFFD,
+0xFFFFFFFA,
+0xFFFFFFFD,
+0xFFFEFFFD,
+0xFFFFFFFB,
+0xFFFEFFFB,
+0xFFF9FFFD,
+0xFFF9FFFD,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFEFA,
+0xFFFFFFFD,
+0xFFFBFFFF,
+0xFFD2D9E3,
+0xFFD3DAEC,
+0xFFD6DEEB,
+0xFFFBFFFF,
+0xFFFAFCFB,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFDFF,
+0xFFFEFCFD,
+0xFFFFFFFA,
+0xFFFCFFFF,
+0xFFD1D4E3,
+0xFFD3D5EA,
+0xFFDCDFF2,
+0xFFFBFFFF,
+0xFFFEFFFF,
+0xFFFFFFFB,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFEFFFD,
+0xFFFEFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFA,
+0xFFFBFEF7,
+0xFFFBFFFD,
+0xFFF9FFFF,
+0xFFFBFFFF,
+0xFFEDFFFF,
+0xFF63A2C5,
+0xFF4093BD,
+0xFF4195C3,
+0xFF3B93C1,
+0xFF3897C5,
+0xFF4C93B1,
+0xFFEFFFFF,
+0xFFFFFFF3,
+0xFFFFFFFB,
+0xFFFFFFFD,
+0xFFFFFEFB,
+0xFFFFFCFB,
+0xFFF8FCFD,
+0xFFF0FFFF,
+0xFFA8D9F9,
+0xFF5393B9,
+0xFF518BB0,
+0xFFCDFBFF,
+0xFFEEFFFF,
+0xFFF8FFFF,
+0xFFFCFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFEFDFF,
+0xFFECFDFF,
+0xFFD5FFFF,
+0xFF66B5D3,
+0xFF3092B9,
+0xFF3C98BF,
+0xFF5A96B2,
+0xFFE6FFFF,
+0xFFF9FFFF,
+0xFFFFFDFF,
+0xFFFFFCFF,
+0xFFFFFCFF,
+0xFFFFFDFF,
+0xFFFFFFFF,
+0xFFFBFFFF,
+0xFFFBFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFB,
+0xFFFDFEFF,
+0xFFF2F9FF,
+0xFF000215,
+0xFF000621,
+0xFF192138,
+0xFFF2F9FF,
+0xFFFCFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFB,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFCFF,
+0xFFFFFFFF,
+0xFFF9FCF5,
+0xFFFCFFFF,
+0xFF00051B,
+0xFF000221,
+0xFF383C57,
+0xFFF8FBFF,
+0xFFFEFFFF,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFFFFFB,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFEFFFA,
+0xFFFCFFF8,
+0xFFFCFFFD,
+0xFFFBFFFF,
+0xFFFAFDFF,
+0xFFECFFFF,
+0xFF64A4C7,
+0xFF3E97C3,
+0xFF3D9DD0,
+0xFF38A1D8,
+0xFF36ABE1,
+0xFF4AA6CD,
+0xFFEBFFFF,
+0xFFFFFFF4,
+0xFFFCFDF8,
+0xFFFEFFFF,
+0xFFFFFDFE,
+0xFFFEFEFE,
+0xFFFCFFFF,
+0xFFF0FFFF,
+0xFFA2D4F5,
+0xFF5394BC,
+0xFF5492B7,
+0xFFC9F8FF,
+0xFFEEFFFF,
+0xFFF9FFFF,
+0xFFFEFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFCFFFF,
+0xFFF9FFFF,
+0xFFF8FFFF,
+0xFFDFFFFF,
+0xFF4A99BA,
+0xFF3CA3CC,
+0xFF39A4D0,
+0xFF3995BC,
+0xFF629AB3,
+0xFFE6FFFF,
+0xFFF8FFFF,
+0xFFFFFDFF,
+0xFFFFFBFF,
+0xFFFFFBFF,
+0xFFFFFDFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFCFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFEFFFF,
+0xFFF9FFFF,
+0xFF07112C,
+0xFF0A1438,
+0xFF242D4C,
+0xFFF9FFFF,
+0xFFFBFFFF,
+0xFFFFFFFF,
+0xFFFFFFFB,
+0xFFFFFFFA,
+0xFFFFFFFD,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFDFDFF,
+0xFFFEFFFB,
+0xFFFBFFFF,
+0xFF010423,
+0xFF0B0F35,
+0xFF454869,
+0xFFFBFDFF,
+0xFFFCFFFF,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFDFF,
+0xFFFFFFFB,
+0xFFFFFFFB,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFEFDF9,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFEFDFF,
+0xFFF5FEFF,
+0xFFC5E3EE,
+0xFFB1E0F4,
+0xFFADECFF,
+0xFF5EB1DB,
+0xFF36A4D9,
+0xFF439ECA,
+0xFFE5FFFF,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFAFBFF,
+0xFFFAFFFF,
+0xFFFBFFFF,
+0xFFFDFFFC,
+0xFFEFFEFF,
+0xFFAAD4ED,
+0xFF4E84A6,
+0xFF5283A3,
+0xFFD3F7FF,
+0xFFF7FFFF,
+0xFFFFFFFB,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFF8FFFF,
+0xFFE6FFFF,
+0xFF78ADCF,
+0xFF439ECA,
+0xFF3897C3,
+0xFF75B6D6,
+0xFFDEFFFF,
+0xFFEFFFFF,
+0xFFF8FFFF,
+0xFFF7FFFF,
+0xFFF9FFFF,
+0xFFFFFDFF,
+0xFFFFFDFF,
+0xFFFFFFFF,
+0xFFFEFFFD,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFDFDFD,
+0xFFF9FCFF,
+0xFFF3F9FF,
+0xFF0A1236,
+0xFF0A1240,
+0xFF262E55,
+0xFFF9FEFF,
+0xFFFCFFFF,
+0xFFFFFFFF,
+0xFFFFFFFB,
+0xFFFFFFFA,
+0xFFFFFFFB,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFDFCFF,
+0xFFFEFFFF,
+0xFFFCFFFB,
+0xFFF4FBFF,
+0xFF05092E,
+0xFF0B0F3E,
+0xFF464A70,
+0xFFF8FCFF,
+0xFFFCFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFDFF,
+0xFFFFFFFB,
+0xFFFFFFFB,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFD,
+0xFFFEFAFB,
+0xFFFFFEFF,
+0xFFFDFCFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFF9FFFF,
+0xFFEEFFFF,
+0xFFDBFFFF,
+0xFF6EB4D8,
+0xFF39A1D4,
+0xFF49A4D1,
+0xFFE7FFFF,
+0xFFFCFDFF,
+0xFFFCFBFF,
+0xFFFEFFFF,
+0xFFFBFFFF,
+0xFFF9FEFF,
+0xFFFFFFFD,
+0xFFF7FFFF,
+0xFFE0FFFF,
+0xFFD4FAFF,
+0xFFD5F5FF,
+0xFFECFFFF,
+0xFFFBFFFF,
+0xFFFFFEFB,
+0xFFFFFEFD,
+0xFFFFFEFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFB,
+0xFFF5FFFF,
+0xFFD6FFFF,
+0xFF468BB4,
+0xFF429FCB,
+0xFF69BBE1,
+0xFFE3FFFF,
+0xFFF6FFFF,
+0xFFFFFFFD,
+0xFFFCFBF7,
+0xFFF8FFFF,
+0xFFF8FFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFEFFFD,
+0xFFFEFFFF,
+0xFFFFFEFF,
+0xFFFFFDFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFD,
+0xFFFEFFFD,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFEFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFEFFFD,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFEFF,
+0xFFF8FEFF,
+0xFF030D31,
+0xFF0B1546,
+0xFF232C55,
+0xFFF9FEFF,
+0xFFFBFEFF,
+0xFFFFFFFF,
+0xFFFFFFFB,
+0xFFFFFFFB,
+0xFFFFFFFD,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFD,
+0xFFFEFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFCFCFE,
+0xFFF9FEFA,
+0xFFFBFFFF,
+0xFF00042C,
+0xFF0B0F3F,
+0xFF474B70,
+0xFFF9FEFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFEFFFD,
+0xFFFEFFFF,
+0xFFF4FFFF,
+0xFFE3FFFF,
+0xFF70B2D2,
+0xFF3CA0D2,
+0xFF4BA2CF,
+0xFFEAFFFF,
+0xFFFFFFFF,
+0xFFFEFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFBFC,
+0xFFFCFFFF,
+0xFFF2FFFF,
+0xFFEFFFFF,
+0xFFF7FFFF,
+0xFFF9FEFF,
+0xFFFCFFFF,
+0xFFFFFFFF,
+0xFFFFFBFF,
+0xFFFFFDFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFDFC,
+0xFFF3FFFF,
+0xFFABE2FF,
+0xFF4796BD,
+0xFF4195B9,
+0xFFB6F8FF,
+0xFFEDFFFF,
+0xFFFCFBFF,
+0xFFFFFBFF,
+0xFFFFFDFF,
+0xFFFDFEFF,
+0xFFFCFFFF,
+0xFFFEFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFEFEFF,
+0xFFFEFEFF,
+0xFFFDFDFF,
+0xFFFBFEFF,
+0xFFFEFFFF,
+0xFFFFFBFA,
+0xFFFFFEFD,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFEFB,
+0xFFFFFBF8,
+0xFFFFFDFF,
+0xFFFFFCFF,
+0xFFFFFAFF,
+0xFFFFFCFF,
+0xFFFBFFFD,
+0xFFF8FFFC,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFFFFFB,
+0xFFFFFFFB,
+0xFFFFFEFF,
+0xFFFCFCFE,
+0xFFFEFEFF,
+0xFFFEFFFF,
+0xFFF9FCF5,
+0xFFFFFFFA,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFDFF,
+0xFFFFFEFF,
+0xFFFCFCFA,
+0xFFFFFFFB,
+0xFFFEFFFD,
+0xFFFBFDFC,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFEFF,
+0xFFFDFBFE,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFEFDFB,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFF9FDFE,
+0xFFFFFFFF,
+0xFFFFFDFE,
+0xFFFEFDFB,
+0xFFFFFFFF,
+0xFFFBFFFF,
+0xFFF8FEFE,
+0xFFFCFEFB,
+0xFFFFFFFD,
+0xFFFFFDFF,
+0xFFFEFBFF,
+0xFFFFFFFF,
+0xFFFEFFFD,
+0xFFFCFFFB,
+0xFFFCFFFB,
+0xFFFCFFFD,
+0xFFFCFEFD,
+0xFFFFFFFD,
+0xFFFFFEFD,
+0xFFFFFBFA,
+0xFFFFFFFD,
+0xFFFDFDFB,
+0xFFFEFFFD,
+0xFFFFFFFB,
+0xFFFEFEFC,
+0xFFFEFEFF,
+0xFFFEFDFF,
+0xFFFFFDFF,
+0xFFFFFDFF,
+0xFFFFFEFF,
+0xFFFFFDFE,
+0xFFFFFEFD,
+0xFFFFFEFB,
+0xFFFFFDFA,
+0xFFFFFFFB,
+0xFFFFFFFB,
+0xFFFBFDFA,
+0xFFFCFFFF,
+0xFFFBFFFF,
+0xFFFBFFFF,
+0xFFFCFEFD,
+0xFFFFFCFC,
+0xFFFFFDFF,
+0xFFFFFDFF,
+0xFFFEFEFF,
+0xFFFFFEFB,
+0xFFFEFDF9,
+0xFFFFFFFF,
+0xFFFDFEFF,
+0xFFFBFFFE,
+0xFFFBFFFC,
+0xFFFBFFFE,
+0xFFFEFFFF,
+0xFFFEFBFF,
+0xFFFFFDFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFB,
+0xFFFFFDFA,
+0xFFFFFFFB,
+0xFFFBFDFC,
+0xFFFEFFFF,
+0xFFFFFDFF,
+0xFFFEFCFF,
+0xFFFCFFFD,
+0xFFFBFFFB,
+0xFFFBFBFB,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFBFCFF,
+0xFFFFFEFF,
+0xFFFFFDFF,
+0xFFFFFDFF,
+0xFFFCFDFF,
+0xFFFCFFFF,
+0xFFFDFFF7,
+0xFFFFFFF8,
+0xFFFDFBFC,
+0xFFFEFDFF,
+0xFFFCFFFF,
+0xFFFEFFFF,
+0xFFFFFDFE,
+0xFFFFFDFC,
+0xFFFEFFFF,
+0xFFFCFFFF,
+0xFFFCFCFE,
+0xFFFFFEFF,
+0xFFFFFDFF,
+0xFFFFFBFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFAFCFB,
+0xFFFCFFFD,
+0xFFFCFFFA,
+0xFFFDFFF9,
+0xFFFFFFFF,
+0xFFFEFEFF,
+0xFFFEFFFB,
+0xFFFEFFFB,
+0xFFFFFFFF,
+0xFFFDFEFF,
+0xFFFCFFFF,
+0xFFFAFEFD,
+0xFFFEFFFF,
+0xFFFEFEFE,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFEFFFF,
+0xFFFDFFFE,
+0xFFFEFFFA,
+0xFFFFFFFA,
+0xFFFCFDF8,
+0xFFFEFFFA,
+0xFFFEFFFD,
+0xFFFEFFFD,
+0xFFFFFEFC,
+0xFFFEFFFF,
+0xFFF8FEFF,
+0xFF040E31,
+0xFF051342,
+0xFF26325A,
+0xFFF9FFFF,
+0xFFFDFEFF,
+0xFFFFFFFD,
+0xFFFDFCF8,
+0xFFFFFDFF,
+0xFFFFFDFF,
+0xFFFDFFFE,
+0xFFFEFFFD,
+0xFFFCFAFB,
+0xFFFFFDFF,
+0xFFFFFBFF,
+0xFFFFFDFE,
+0xFFFFFFFB,
+0xFFFFFFFA,
+0xFFFCFDF7,
+0xFFFEFFFD,
+0xFFFEFFFF,
+0xFFFDFEFF,
+0xFFFEFFFF,
+0xFFFDFFFE,
+0xFFFEFEFC,
+0xFFFFFFFD,
+0xFFFDFDFB,
+0xFFFFFFFD,
+0xFFFEFFFF,
+0xFFFEFFFD,
+0xFFFBFFFA,
+0xFFFCFFFB,
+0xFFFEFFFF,
+0xFFFDFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFEFDFB,
+0xFFFFFFFD,
+0xFFFFFDFF,
+0xFFFFFCFF,
+0xFFFFFCFF,
+0xFFFFFDFE,
+0xFFFEFEF6,
+0xFFFFFFFA,
+0xFFFEFFFF,
+0xFFFBFCFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFDFDFF,
+0xFFF8FBFF,
+0xFF010630,
+0xFF0D1442,
+0xFF434866,
+0xFFFBFEFF,
+0xFFFFFEFF,
+0xFFFFFEFD,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFB,
+0xFFFEFFFB,
+0xFFFFFEFF,
+0xFFF7FFFF,
+0xFFE6FFFF,
+0xFF72B1D0,
+0xFF3EA0D1,
+0xFF4DA1CD,
+0xFFEAFFFF,
+0xFFFFFFFF,
+0xFFFEFEFF,
+0xFFFEFFFF,
+0xFFFEFEFF,
+0xFFFEFFFF,
+0xFFF7FFFF,
+0xFFF1FFFF,
+0xFFECFFFF,
+0xFFEDFFFF,
+0xFFF2FFFF,
+0xFFF7FFFF,
+0xFFF8FFFF,
+0xFFFEFFFF,
+0xFFFFFDFF,
+0xFFFFFCFF,
+0xFFFCFDFF,
+0xFFF9FFFF,
+0xFFF5FFFF,
+0xFFE4FFFF,
+0xFF97DFFF,
+0xFF459EC8,
+0xFF4597BC,
+0xFFC6FFFF,
+0xFFE3FFFF,
+0xFFF3FFFF,
+0xFFFFFDFF,
+0xFFFFFCFF,
+0xFFFFFFFF,
+0xFFFCFEFB,
+0xFFFFFEFC,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFF9FCFF,
+0xFFF9FFFF,
+0xFFF4FFFF,
+0xFFEFFFFF,
+0xFFF4FFFF,
+0xFFF1FFFF,
+0xFFF0FFFF,
+0xFFF0FFFF,
+0xFFF5FFFF,
+0xFFF7FFFF,
+0xFFFBFDF8,
+0xFFFFFFFA,
+0xFFFEFCFD,
+0xFFFFFAFF,
+0xFFFFF8FF,
+0xFFFFFDFF,
+0xFFFCFFFD,
+0xFFF9FFFD,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFFFFFB,
+0xFFFFFFFB,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFDFEFF,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFBFFFF,
+0xFFF8FAFF,
+0xFFFBFCFF,
+0xFFFBFCFF,
+0xFFFCFDFF,
+0xFFFCFEFF,
+0xFFF9FCFF,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFAFEFF,
+0xFFFCFCFF,
+0xFFFEFEFF,
+0xFFFEFFFF,
+0xFFFEFEFE,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFCFAFB,
+0xFFFEFFFF,
+0xFFFBFEFF,
+0xFFFBFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFBFC,
+0xFFFFFFFF,
+0xFFFBFFFF,
+0xFFFBFFFF,
+0xFFFEFFFD,
+0xFFFDFDFB,
+0xFFFFFCFF,
+0xFFFFFDFF,
+0xFFFEFEFF,
+0xFFF8FDF9,
+0xFFFBFFFD,
+0xFFFBFFFF,
+0xFFFAFDFF,
+0xFFFEFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFDFC,
+0xFFFFFFFB,
+0xFFFFFFFD,
+0xFFFAFCF9,
+0xFFFBFDFA,
+0xFFFEFFFF,
+0xFFFEFEFF,
+0xFFFBFDFF,
+0xFFF9FAFF,
+0xFFFCFDFF,
+0xFFFBFCFF,
+0xFFFEFDFF,
+0xFFFBFBFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFDFDFF,
+0xFFFDFEFF,
+0xFFFCFFFF,
+0xFFF6F9FF,
+0xFFFBFFFF,
+0xFFF8FFFF,
+0xFFFCFFFF,
+0xFFFFFDFF,
+0xFFFFF9FF,
+0xFFFFFDFF,
+0xFFFCFFFF,
+0xFFFCFCFE,
+0xFFFFFFFF,
+0xFFF8FBFF,
+0xFFFBFFFF,
+0xFFF9FFFF,
+0xFFF6FFFF,
+0xFFF8FFFF,
+0xFFF9FFFF,
+0xFFFCFEFF,
+0xFFFCFCFF,
+0xFFFDFEFF,
+0xFFFAFEFD,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFAFAFF,
+0xFFFFFEFF,
+0xFFFAFDFF,
+0xFFF8FFFF,
+0xFFF9FFFF,
+0xFFF8F5FF,
+0xFFFFFDFF,
+0xFFF4FCFF,
+0xFFF6FFFC,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFBFCF7,
+0xFFFFFFFD,
+0xFFFEFFFF,
+0xFFFDFCFF,
+0xFFFFFDFF,
+0xFFFFFEFF,
+0xFFFCFFFF,
+0xFFFBFFFF,
+0xFFFCFFFB,
+0xFFFBFFFC,
+0xFFFEFEFF,
+0xFFFCFEFF,
+0xFFF7FFFF,
+0xFFF2FCFF,
+0xFFFCFEFF,
+0xFFFEFEFF,
+0xFFFAFEFF,
+0xFFFBFFFF,
+0xFFFEFFFF,
+0xFFFEFDFF,
+0xFFFFFBFF,
+0xFFFFFDFF,
+0xFFFFFEFF,
+0xFFFFFDFE,
+0xFFFEFFFD,
+0xFFF6FBF7,
+0xFFFBFFFC,
+0xFFFCFFFF,
+0xFFFCFCFF,
+0xFFFEFEFF,
+0xFFFAFBFF,
+0xFFFCFFFF,
+0xFFF8FBFF,
+0xFFFBFFFF,
+0xFFF7FDFF,
+0xFFF9FFFF,
+0xFFF8FCFF,
+0xFFFEFEFF,
+0xFFFFFDFF,
+0xFFFBF9FF,
+0xFFFCFFFF,
+0xFFFBFFFF,
+0xFFFCFFFB,
+0xFFFEFFFA,
+0xFFFFFEFA,
+0xFFFFFEFF,
+0xFFFDFEFF,
+0xFFFEFFFF,
+0xFFFFFEFF,
+0xFFFBFDFF,
+0xFFF6FDFF,
+0xFF010F34,
+0xFF061846,
+0xFF202F58,
+0xFFF4FAFF,
+0xFFFCFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFAFF,
+0xFFFEFBFF,
+0xFFFBFFFC,
+0xFFFCFFFB,
+0xFFFFFEFF,
+0xFFFFFDFF,
+0xFFFFFDFF,
+0xFFFFFEFF,
+0xFFFCFDFF,
+0xFFF9FDFF,
+0xFFFAFFFF,
+0xFFF9FFFF,
+0xFFF9FFFF,
+0xFFF7FDFF,
+0xFFF9FDFF,
+0xFFFAFDFF,
+0xFFFEFFFF,
+0xFFFDFEFF,
+0xFFFFFFFF,
+0xFFFCFCFC,
+0xFFFBFDFC,
+0xFFFEFFFF,
+0xFFFCFEFB,
+0xFFFEFFFD,
+0xFFFDFDFF,
+0xFFFEFDFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFEFEFF,
+0xFFFFFEFF,
+0xFFFFFDFF,
+0xFFFFFDFF,
+0xFFFEFEFF,
+0xFFFCFFFF,
+0xFFF8FDFF,
+0xFFF6FCFF,
+0xFFFBFFFF,
+0xFFFDFEFF,
+0xFFFFFEFF,
+0xFFFEFFFF,
+0xFFFBFEFF,
+0xFF000833,
+0xFF050D3B,
+0xFF444B67,
+0xFFFCFEFF,
+0xFFFFFDFF,
+0xFFFFFDFD,
+0xFFFFFEFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFD,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFB,
+0xFFFEFFFB,
+0xFFFFFEFF,
+0xFFF7FFFF,
+0xFFE6FFFF,
+0xFF72B1D0,
+0xFF3EA0D1,
+0xFF4DA1CD,
+0xFFEAFFFF,
+0xFFFFFFFF,
+0xFFFEFEFE,
+0xFFFCFFFF,
+0xFFFBFFFF,
+0xFFF1FFFF,
+0xFFBCE6F4,
+0xFFB2E9FE,
+0xFFB0E8FF,
+0xFFB1E9FF,
+0xFFB5E4FE,
+0xFFC4E9FB,
+0xFFF2FFFF,
+0xFFF9FFFF,
+0xFFFEFFFD,
+0xFFFAFEFF,
+0xFFF7FFFF,
+0xFFD5EFFC,
+0xFFB3E5FE,
+0xFFA7F0FF,
+0xFF71C9F7,
+0xFF3B9BCD,
+0xFF3B97C6,
+0xFF98ECFF,
+0xFFADF5FF,
+0xFFB3E4F5,
+0xFFEAFCFF,
+0xFFFBFEFF,
+0xFFFCFEFB,
+0xFFFDFEF8,
+0xFFFFFEFB,
+0xFFFFFFFD,
+0xFFF6FBF7,
+0xFFF9FFFF,
+0xFFFBFFFF,
+0xFFEFFFFF,
+0xFFE2FFFF,
+0xFFD4FFFF,
+0xFFB3EBFF,
+0xFFAEE6FF,
+0xFFBEF2FF,
+0xFFDAFFFF,
+0xFFE3FFFF,
+0xFFE9FFFF,
+0xFFF7FFFF,
+0xFFFBFFF8,
+0xFFF8FFFA,
+0xFFFCFFFF,
+0xFFFFFEFF,
+0xFFFFFAFC,
+0xFFFCFAFB,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFB,
+0xFFFFFFFB,
+0xFFFFFCFD,
+0xFFFFFEFF,
+0xFFFEFFFF,
+0xFFFBFFFF,
+0xFFF8FFFF,
+0xFFD0DBEF,
+0xFF737DA1,
+0xFF333E6B,
+0xFF131D4E,
+0xFF192150,
+0xFF222A51,
+0xFF606688,
+0xFFB2B7D5,
+0xFFF9FEFF,
+0xFFF9FDFF,
+0xFFFBFFFF,
+0xFFD8DEEA,
+0xFFB0B6C6,
+0xFFABAFBB,
+0xFFE9ECF3,
+0xFFFFFFFF,
+0xFFFDFDFB,
+0xFFFFFFFF,
+0xFFFAFDFF,
+0xFFD7DBE7,
+0xFFABB1BF,
+0xFFAFAEBC,
+0xFFF6F5FD,
+0xFFFFFEFF,
+0xFFFFFDFE,
+0xFFFBFFFF,
+0xFFF9FDFE,
+0xFFFEFFFD,
+0xFFFEFEFC,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFEFEFC,
+0xFFFCFFFF,
+0xFFE5EAEE,
+0xFFA9AFBB,
+0xFFAEB1C4,
+0xFFE4E5F7,
+0xFFFBF9FF,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFFFFFB,
+0xFFFAFCF9,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFF9FDFF,
+0xFFF9FEFF,
+0xFF9399B9,
+0xFF474F76,
+0xFF18214C,
+0xFF121E46,
+0xFF212E51,
+0xFF586182,
+0xFFB1B8D2,
+0xFFF8FFFF,
+0xFFFAFDFF,
+0xFFFCFEFF,
+0xFFD9DBE8,
+0xFFB5B4C6,
+0xFFADAFBE,
+0xFFEBF0F4,
+0xFFFBFFFF,
+0xFFFFFDFF,
+0xFFFFFCFF,
+0xFFC5C7DC,
+0xFFACB2C8,
+0xFFAAADBC,
+0xFFFBFEFF,
+0xFFF8FEFF,
+0xFFA8AFCB,
+0xFF4D5677,
+0xFF1E284B,
+0xFF182245,
+0xFF414C6C,
+0xFF8E95B1,
+0xFFF9FEFF,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFAFFFF,
+0xFFF8FEFF,
+0xFFF7FDFF,
+0xFFE9EFFF,
+0xFF7F85A9,
+0xFF3B4569,
+0xFF132344,
+0xFF182748,
+0xFF5A5E81,
+0xFFA9ACCB,
+0xFFF7FFFF,
+0xFFF9FFFF,
+0xFFFDFDFB,
+0xFFFEFEF4,
+0xFFFFFFF8,
+0xFFFBFDF8,
+0xFFFDFCFF,
+0xFFFFFEFF,
+0xFFFFFBFC,
+0xFFFFFFFD,
+0xFFFAFEFD,
+0xFFF9FFFF,
+0xFFF9FFFF,
+0xFFF9FFFF,
+0xFFB3B8D6,
+0xFF5D678A,
+0xFF1C3150,
+0xFF102747,
+0xFF1C2C4E,
+0xFF495474,
+0xFF959FBA,
+0xFFF7FEFF,
+0xFFF5FBFF,
+0xFFFBFFFF,
+0xFFFEFFFD,
+0xFFFCFBF6,
+0xFFFFFEFD,
+0xFFFCFBF9,
+0xFFFBFCF7,
+0xFFFEFFFF,
+0xFFFCFEFF,
+0xFFB9BACE,
+0xFFAFAECD,
+0xFFB5B4D3,
+0xFFFCFDFF,
+0xFFF7FDFF,
+0xFFDDE5FC,
+0xFF6C7592,
+0xFF2E385B,
+0xFF101A3D,
+0xFF23284E,
+0xFF484C6F,
+0xFF8889A7,
+0xFFFBFDFF,
+0xFFF9FFFF,
+0xFFF9FFFF,
+0xFFF6FCFA,
+0xFFFCFEFB,
+0xFFFFFEFF,
+0xFFFDFAFF,
+0xFFFDFBFF,
+0xFFB3B1C6,
+0xFFB5B5CF,
+0xFFB5B9DC,
+0xFFA9B5DD,
+0xFF041644,
+0xFF001645,
+0xFF152A55,
+0xFFC4CDEE,
+0xFFB1B5D0,
+0xFFB4B4CE,
+0xFFB2B3C8,
+0xFFE7E5F3,
+0xFFFEFEFF,
+0xFFFBFFFF,
+0xFFF9FFFB,
+0xFFF8FAF7,
+0xFFFBFCFE,
+0xFFFBFDFF,
+0xFFF8FDFF,
+0xFFC1C9E0,
+0xFF6C7592,
+0xFF2A3757,
+0xFF152245,
+0xFF19254B,
+0xFF3E4B6E,
+0xFF8790B1,
+0xFFECF2FF,
+0xFFFBFEFF,
+0xFFFCFFFF,
+0xFFFBFCFF,
+0xFFFCFDFF,
+0xFFFFFFFF,
+0xFFFBFAFF,
+0xFFFFFEFF,
+0xFFFEFCFF,
+0xFFFFFCFF,
+0xFFFFFDFF,
+0xFFFFFDFE,
+0xFFFCFCFA,
+0xFFFCFFFF,
+0xFFF9FFFF,
+0xFFF4FDFF,
+0xFF9DA7C0,
+0xFF55607E,
+0xFF1C294B,
+0xFF172447,
+0xFF1D2A4D,
+0xFF465073,
+0xFF8F98B7,
+0xFFF8FCFF,
+0xFFF8FBFF,
+0xFFF8FCFF,
+0xFFF5FCFF,
+0xFF000A34,
+0xFF05123F,
+0xFF434C69,
+0xFFF9FCFF,
+0xFFFFFEFF,
+0xFFFFFEFD,
+0xFFFFFEFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFB,
+0xFFFEFFFB,
+0xFFFFFEFF,
+0xFFF7FFFF,
+0xFFE6FFFF,
+0xFF72B1D0,
+0xFF3EA0D1,
+0xFF4DA1CD,
+0xFFEAFFFF,
+0xFFFFFFFF,
+0xFFFEFEFE,
+0xFFFCFFFF,
+0xFFF9FFFF,
+0xFFEBFFFF,
+0xFF679EB2,
+0xFF4F94B3,
+0xFF4A92B8,
+0xFF4B94BD,
+0xFF4993BA,
+0xFF6AA3C0,
+0xFFEDFFFF,
+0xFFF6FFFC,
+0xFFFBFFFD,
+0xFFF9FFFF,
+0xFFF5FFFF,
+0xFFA2C3D4,
+0xFF4C8EAE,
+0xFF429BC5,
+0xFF3C9ECF,
+0xFF41A6DA,
+0xFF44A8DA,
+0xFF3899C6,
+0xFF3F99BC,
+0xFF4689A3,
+0xFFCDE9F7,
+0xFFF9FFFF,
+0xFFFCFFFD,
+0xFFFFFFFA,
+0xFFFFFFFB,
+0xFFFCFEFD,
+0xFFF7FFFF,
+0xFFECFFFF,
+0xFFE6FFFF,
+0xFFA7D5E5,
+0xFF63A0BC,
+0xFF4992B3,
+0xFF4C98BC,
+0xFF4A96BA,
+0xFF4E94B8,
+0xFF4B8DAF,
+0xFF609FBE,
+0xFFA4DBF0,
+0xFFE2FFFF,
+0xFFE9FFFF,
+0xFFF2FFFF,
+0xFFF9FFFF,
+0xFFFDFBFC,
+0xFFFFFDFF,
+0xFFFFFEFF,
+0xFFFFFDFE,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFDFE,
+0xFFFFFEFF,
+0xFFF9FBFF,
+0xFFDADFF3,
+0xFF2B324E,
+0xFF00082A,
+0xFF04113D,
+0xFF051344,
+0xFF051246,
+0xFF000D41,
+0xFF091545,
+0xFF050D3B,
+0xFF00052F,
+0xFF0A0F2F,
+0xFFB8BECC,
+0xFFF8FFFF,
+0xFF7E899F,
+0xFF00011C,
+0xFF00061B,
+0xFFB2B8C6,
+0xFFFBFCFF,
+0xFFFDFDFD,
+0xFFFEFFFF,
+0xFFFCFFFF,
+0xFF757C8E,
+0xFF00041C,
+0xFF010318,
+0xFFCBCADA,
+0xFFFFFDFF,
+0xFFFFFEFF,
+0xFFFEFEFE,
+0xFFFEFFFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFCFCFC,
+0xFFFEFFFD,
+0xFFFBFFFF,
+0xFF9DA0AF,
+0xFF02061F,
+0xFF000322,
+0xFFA4A4C0,
+0xFFFEFCFF,
+0xFFFEFCFF,
+0xFFFFFFFF,
+0xFFFCFEFB,
+0xFFFBFFFF,
+0xFFF5FCFF,
+0xFFF9FFFF,
+0xFF6E748C,
+0xFF000324,
+0xFF000A32,
+0xFF05123E,
+0xFF04123F,
+0xFF031440,
+0xFF01123D,
+0xFF03103A,
+0xFF000A2D,
+0xFF091231,
+0xFFBFC6E0,
+0xFFF9FDFF,
+0xFF80829B,
+0xFF020321,
+0xFF000118,
+0xFFC0C7CF,
+0xFFFBFFFF,
+0xFFFFFDFF,
+0xFFFCFAFF,
+0xFF404763,
+0xFF000626,
+0xFF000724,
+0xFFF2F8FF,
+0xFF1B2347,
+0xFF00062A,
+0xFF09123B,
+0xFF04103A,
+0xFF08153F,
+0xFF06143B,
+0xFF00092B,
+0xFF000922,
+0xFF898F9D,
+0xFFF9FFFF,
+0xFFF6FEFF,
+0xFFF7FFFF,
+0xFF656F93,
+0xFF000431,
+0xFF000B39,
+0xFF01103B,
+0xFF00123A,
+0xFF05173D,
+0xFF060D37,
+0xFF02072D,
+0xFF0B1435,
+0xFFBFC7DE,
+0xFFFCFFFF,
+0xFFFEFFFA,
+0xFFFEFFF7,
+0xFFFDFEF8,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFEFEFE,
+0xFFFBFFFF,
+0xFFF7FFFF,
+0xFFA6ADC0,
+0xFF0D122F,
+0xFF050A32,
+0xFF04103A,
+0xFF00153A,
+0xFF00173B,
+0xFF000F37,
+0xFF08163D,
+0xFF030D30,
+0xFF000928,
+0xFF7B85A0,
+0xFFF5FEFF,
+0xFFF7FFFF,
+0xFFFBFFFC,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFB,
+0xFFFEFFFF,
+0xFFFBFEFF,
+0xFF0F1233,
+0xFF040730,
+0xFF040931,
+0xFFF8FDFF,
+0xFF4F5673,
+0xFF000124,
+0xFF010F34,
+0xFF04133C,
+0xFF020F39,
+0xFF08113C,
+0xFF050C36,
+0xFF090D33,
+0xFF010626,
+0xFF878EA8,
+0xFFF2FBFF,
+0xFFF9FFFF,
+0xFFFCFFFF,
+0xFFFFFEFF,
+0xFFFFFCFF,
+0xFFFFFBFF,
+0xFF080520,
+0xFF09092D,
+0xFF000731,
+0xFF000936,
+0xFF051B4A,
+0xFF001B4A,
+0xFF021945,
+0xFF000A2E,
+0xFF060B2B,
+0xFF080B2A,
+0xFF03051E,
+0xFFABADBC,
+0xFFFCFFFF,
+0xFFF9FFFF,
+0xFFF8FFFF,
+0xFFFCFFFF,
+0xFFFBFFFF,
+0xFFC9CFE7,
+0xFF1B2445,
+0xFF020C30,
+0xFF020E34,
+0xFF010E38,
+0xFF020F3B,
+0xFF04133E,
+0xFF020F3B,
+0xFF020E36,
+0xFF00062A,
+0xFF585D7A,
+0xFFF7FCFF,
+0xFFFCFEFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFDFF,
+0xFFFFFDFF,
+0xFFFFFCFF,
+0xFFFFFDFF,
+0xFFFFFCFF,
+0xFFFEFCFF,
+0xFFFEFFFF,
+0xFFF7FDFF,
+0xFF707B8F,
+0xFF000E2B,
+0xFF000E2F,
+0xFF021639,
+0xFF03163E,
+0xFF011240,
+0xFF000E3D,
+0xFF0A1640,
+0xFF040D34,
+0xFF00062A,
+0xFF737895,
+0xFFF8FFFF,
+0xFFF4FFFF,
+0xFF000530,
+0xFF061441,
+0xFF3E4965,
+0xFFF9FFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFB,
+0xFFFEFFFB,
+0xFFFFFEFF,
+0xFFF7FFFF,
+0xFFE6FFFF,
+0xFF72B1D0,
+0xFF3EA0D1,
+0xFF4DA1CD,
+0xFFEAFFFF,
+0xFFFFFFFF,
+0xFFFEFEFE,
+0xFFFCFFFF,
+0xFFF6FFFA,
+0xFFEEFFFF,
+0xFF6696AC,
+0xFF4B8BAE,
+0xFF4992BB,
+0xFF4FA2CE,
+0xFF42A1CF,
+0xFF66B2D4,
+0xFFEAFFFF,
+0xFFFAFFFC,
+0xFFFBFFFF,
+0xFFF8FFFF,
+0xFFF3FFFF,
+0xFF9FBFCE,
+0xFF4A89A8,
+0xFF4196BF,
+0xFF3C9DCA,
+0xFF3FA5D6,
+0xFF3EA6D9,
+0xFF379BCD,
+0xFF3E9BC6,
+0xFF478CAB,
+0xFFCAE6F2,
+0xFFF9FEFF,
+0xFFFEFFFD,
+0xFFFEFFFB,
+0xFFFBFFFF,
+0xFFF2FFFF,
+0xFFEDFFFF,
+0xFFCCFAFF,
+0xFF4A99BA,
+0xFF3C9CC4,
+0xFF419ECA,
+0xFF4198C5,
+0xFF4694BA,
+0xFF4C94BA,
+0xFF4F94BE,
+0xFF4A94C3,
+0xFF409FCD,
+0xFF3798C2,
+0xFF499CBA,
+0xFFBAF7FF,
+0xFFEBFFFF,
+0xFFFBFFFF,
+0xFFFFFDFF,
+0xFFFFF9FB,
+0xFFFEFEFE,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFCFFFF,
+0xFFF7FBFF,
+0xFF979ABB,
+0xFF01042F,
+0xFF0D113E,
+0xFF060F36,
+0xFF000C2E,
+0xFF000E2D,
+0xFF31405F,
+0xFF394869,
+0xFF1D2A4C,
+0xFF00092C,
+0xFF060F38,
+0xFF0F183F,
+0xFF000429,
+0xFF848EB2,
+0xFF96A4C9,
+0xFF041235,
+0xFF000B29,
+0xFFB6BCD2,
+0xFFFAFDFF,
+0xFFFFFFFF,
+0xFFF9FAFC,
+0xFFF9FDFF,
+0xFF7D849E,
+0xFF080E30,
+0xFF060B29,
+0xFFD3D5EA,
+0xFFFAF7FF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFBFBF9,
+0xFFFDFEF9,
+0xFFFFFFFB,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFDFFFC,
+0xFFFCFFFF,
+0xFFA5A9C2,
+0xFF070B2E,
+0xFF070A33,
+0xFFA6A6C8,
+0xFFFEFDFF,
+0xFFFFFEFF,
+0xFFFEFFFF,
+0xFFFBFFFF,
+0xFFF8FFFF,
+0xFFF1F8FF,
+0xFF121B3C,
+0xFF020B34,
+0xFF0C1842,
+0xFF051338,
+0xFF000927,
+0xFF2B3C56,
+0xFF44566E,
+0xFF1F2E4B,
+0xFF000C2F,
+0xFF010D35,
+0xFF08113A,
+0xFF000229,
+0xFF9BA3C8,
+0xFF98A0C5,
+0xFF081037,
+0xFF040D2E,
+0xFFC3CADA,
+0xFFFBFFFF,
+0xFFFEFEFF,
+0xFFFBFEFF,
+0xFF444F6D,
+0xFF011039,
+0xFF081341,
+0xFF182051,
+0xFF0A1240,
+0xFF050E35,
+0xFF030E2E,
+0xFF32405B,
+0xFF2D3C59,
+0xFF071635,
+0xFF031032,
+0xFF0D173A,
+0xFF000728,
+0xFF636E8E,
+0xFFF2FFFF,
+0xFF2E3B5D,
+0xFF000C36,
+0xFF07123F,
+0xFF010D33,
+0xFF0B1A39,
+0xFF314560,
+0xFF263753,
+0xFF01092D,
+0xFF0B1038,
+0xFF101846,
+0xFF000028,
+0xFFA3AAC4,
+0xFFFBFFFF,
+0xFFFFFFFB,
+0xFFFFFFF6,
+0xFFFCFBF7,
+0xFFFFFEFF,
+0xFFFEFCFF,
+0xFFFEFEFF,
+0xFFF8FEFF,
+0xFF505676,
+0xFF02062C,
+0xFF0C0E37,
+0xFF0B0D36,
+0xFF03092D,
+0xFF1A2842,
+0xFF36455C,
+0xFF303754,
+0xFF02082A,
+0xFF00072B,
+0xFF0E183C,
+0xFF000B33,
+0xFF162343,
+0xFFF4FFFF,
+0xFFF7FFFF,
+0xFFF7FAFF,
+0xFFFEFEFF,
+0xFFFFFEFF,
+0xFFF9F9FF,
+0xFFF8FEFF,
+0xFF172144,
+0xFF061340,
+0xFF142251,
+0xFF43507C,
+0xFF000B35,
+0xFF08163B,
+0xFF00082B,
+0xFF0D1D3E,
+0xFF364765,
+0xFF1F2D4A,
+0xFF030C2D,
+0xFF090E36,
+0xFF0E133D,
+0xFF00052E,
+0xFF50597A,
+0xFFF5FCFF,
+0xFFFBFFFF,
+0xFFFEFDFF,
+0xFFFDF8FF,
+0xFFFFFBFF,
+0xFF07041F,
+0xFF040728,
+0xFF000A2E,
+0xFF001038,
+0xFF041B45,
+0xFF001A4B,
+0xFF001644,
+0xFF000C2E,
+0xFF040926,
+0xFF060A23,
+0xFF000012,
+0xFFB1B4BD,
+0xFFFBFFFF,
+0xFFF6FFFF,
+0xFFF4FFFF,
+0xFFFAFDFF,
+0xFF757996,
+0xFF00002A,
+0xFF0D1845,
+0xFF020B34,
+0xFF020C2F,
+0xFF182140,
+0xFF3A4362,
+0xFF313C5C,
+0xFF071134,
+0xFF010E31,
+0xFF061034,
+0xFF091135,
+0xFF090F2F,
+0xFFE0E2F9,
+0xFFFEFEFF,
+0xFFFFFEFF,
+0xFFFFFEFB,
+0xFFFEFAF7,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFCFDFF,
+0xFFF9FCFF,
+0xFFF9FEFF,
+0xFF20264A,
+0xFF05113B,
+0xFF061540,
+0xFF001136,
+0xFF000827,
+0xFF152A49,
+0xFF334367,
+0xFF2C385E,
+0xFF020A2E,
+0xFF040A2E,
+0xFF090E34,
+0xFF040A2E,
+0xFF212844,
+0xFFF4FFFF,
+0xFF000C3D,
+0xFF021442,
+0xFF3D4B68,
+0xFFF7FEFF,
+0xFFFEFFFF,
+0xFFFFFEFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFB,
+0xFFFEFFFB,
+0xFFFFFEFF,
+0xFFF7FFFF,
+0xFFE6FFFF,
+0xFF72B1D0,
+0xFF3EA0D1,
+0xFF4DA1CD,
+0xFFEAFFFF,
+0xFFFFFFFF,
+0xFFFEFEFE,
+0xFFFCFFFD,
+0xFFFCFFFD,
+0xFFF2FFFF,
+0xFFDEFFFF,
+0xFFCFFFFF,
+0xFFCBFFFF,
+0xFF57A8D5,
+0xFF3B9FD1,
+0xFF62B6DB,
+0xFFE8FFFF,
+0xFFF9FEF8,
+0xFFFCFFFF,
+0xFFFBFFFF,
+0xFFF8FFFF,
+0xFFE1F7FF,
+0xFFC3F1FF,
+0xFFBBFDFF,
+0xFF7FD4FD,
+0xFF41A2CF,
+0xFF3799C8,
+0xFF99F4FF,
+0xFFB1FDFF,
+0xFFBCF0FF,
+0xFFEDFFFF,
+0xFFFCFFFF,
+0xFFFEFFFB,
+0xFFFAFFFB,
+0xFFF6FFFF,
+0xFFE7FFFF,
+0xFFC1F0FF,
+0xFF478CB6,
+0xFF46A3CF,
+0xFF3B9CC9,
+0xFF53A6CE,
+0xFF97DDFF,
+0xFFC0FDFF,
+0xFFC8FFFF,
+0xFFC0F5FF,
+0xFFA0DEFF,
+0xFF57AAD4,
+0xFF3A9AC4,
+0xFF43A4CE,
+0xFF4092B7,
+0xFFAFDDFE,
+0xFFECFFFF,
+0xFFFCFFFF,
+0xFFFFFCF9,
+0xFFFEFFFF,
+0xFFFBFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFCFFFF,
+0xFFF7FFFF,
+0xFF949FB1,
+0xFF00022C,
+0xFF121447,
+0xFF020532,
+0xFF454B6D,
+0xFFD0D8EB,
+0xFFF7FFFF,
+0xFFF4FDFF,
+0xFFF5FFFF,
+0xFFF4FFFF,
+0xFFF0FBFF,
+0xFF76819D,
+0xFF00092C,
+0xFF05103D,
+0xFF02103F,
+0xFF293B69,
+0xFF071843,
+0xFF020E34,
+0xFFB0B7D1,
+0xFFFAFDFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFBFFFF,
+0xFF7D86A5,
+0xFF060F36,
+0xFF02082C,
+0xFFCDD1EA,
+0xFFFFFEFF,
+0xFFFFFDFC,
+0xFFFFFEFC,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFDFEF9,
+0xFFFDFDFB,
+0xFFFEFEFC,
+0xFFFCFEFD,
+0xFFFBFDFF,
+0xFFA4A7C6,
+0xFF060932,
+0xFF090C37,
+0xFFA5A8C9,
+0xFFFEFDFF,
+0xFFFEFFFF,
+0xFFF8FCFF,
+0xFFF9FDFF,
+0xFFF5FCFF,
+0xFF000626,
+0xFF0C1540,
+0xFF030E3B,
+0xFF0D1A3D,
+0xFFA7B5CF,
+0xFFF2FFFF,
+0xFFF4FFFF,
+0xFFF5FFFF,
+0xFFF5FFFF,
+0xFFF5FFFF,
+0xFF838CAB,
+0xFF070F34,
+0xFF0B143D,
+0xFF000633,
+0xFF3A4974,
+0xFF061743,
+0xFF00072A,
+0xFFBEC7D8,
+0xFFFBFFFF,
+0xFFFEFFFF,
+0xFFF9FFFF,
+0xFF455473,
+0xFF031545,
+0xFF0E1951,
+0xFF050F44,
+0xFF000934,
+0xFF9099BA,
+0xFFF7FFFF,
+0xFFF7FFFF,
+0xFFF3FFFF,
+0xFFF4FFFF,
+0xFFA6B0CB,
+0xFF030E2E,
+0xFF07133D,
+0xFF020F3C,
+0xFF3C4B76,
+0xFF000D37,
+0xFF071039,
+0xFF141C40,
+0xFFC5CCE6,
+0xFFF6FEFF,
+0xFFF4FFFF,
+0xFFF4FFFF,
+0xFFF8FEFF,
+0xFF6D7196,
+0xFF000432,
+0xFF0D1846,
+0xFF000026,
+0xFFE2EAFF,
+0xFFFEFFFF,
+0xFFFFFFFA,
+0xFFFFFFFA,
+0xFFFDFCFA,
+0xFFFFFEFF,
+0xFFF9FBFF,
+0xFF393F63,
+0xFF020935,
+0xFF101340,
+0xFF080A33,
+0xFF8487A8,
+0xFFF9FDFF,
+0xFFF5FEFF,
+0xFFF7FFFF,
+0xFFF7F8FF,
+0xFFFCFCFF,
+0xFFA9AECB,
+0xFF0F1839,
+0xFF020E38,
+0xFF09173E,
+0xFF061532,
+0xFFF4FFFF,
+0xFFFBFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFEFEFF,
+0xFFF5FDFF,
+0xFF152445,
+0xFF051745,
+0xFF061A4C,
+0xFF001141,
+0xFF03123D,
+0xFF404A6D,
+0xFFE3EFFF,
+0xFFF2FFFF,
+0xFFF2FFFF,
+0xFFF2FEFF,
+0xFFF6FEFF,
+0xFF787D9D,
+0xFF050A32,
+0xFF0B1341,
+0xFF020B36,
+0xFF7A80A0,
+0xFFF3F8FF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFCFF,
+0xFFCBCADC,
+0xFFCBCDE4,
+0xFFC9D3EE,
+0xFFBBCCEA,
+0xFF02183F,
+0xFF02194B,
+0xFF1A305F,
+0xFFDAE5FF,
+0xFFCBD0E4,
+0xFFCCCFDE,
+0xFFCCCFD6,
+0xFFF0F4F7,
+0xFFF4F9FC,
+0xFFF8FFFF,
+0xFFF7FFFF,
+0xFF6C6F8E,
+0xFF03062F,
+0xFF0E1644,
+0xFF00042E,
+0xFF67708F,
+0xFFEBF3FF,
+0xFFF9FEFF,
+0xFFF8FDFF,
+0xFFF8FEFF,
+0xFFF6FEFF,
+0xFFBFC9E4,
+0xFF273250,
+0xFF000A2D,
+0xFF0B1337,
+0xFF000220,
+0xFFE2E5F8,
+0xFFFEFFFF,
+0xFFFEFDF8,
+0xFFFFFFFA,
+0xFFFBFCF6,
+0xFFFEFFFD,
+0xFFFAFFFF,
+0xFFF8FFFF,
+0xFF060F2E,
+0xFF040C3A,
+0xFF030D3E,
+0xFF07153C,
+0xFF8D9EBC,
+0xFFF0FFFF,
+0xFFEEFFFF,
+0xFFF4FFFF,
+0xFFF4FBFF,
+0xFFF9FEFF,
+0xFFB7BBD4,
+0xFF252B4B,
+0xFF01092D,
+0xFF091135,
+0xFF27335B,
+0xFF011246,
+0xFF001242,
+0xFF3D4D67,
+0xFFF7FFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFCFFFD,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFB,
+0xFFFEFFFB,
+0xFFFFFEFF,
+0xFFF7FFFF,
+0xFFE6FFFF,
+0xFF72B1D0,
+0xFF3EA0D1,
+0xFF4DA1CD,
+0xFFEAFFFF,
+0xFFFFFFFF,
+0xFFFEFEFE,
+0xFFFEFFFD,
+0xFFFEFFFD,
+0xFFFAFEFF,
+0xFFF5FDFF,
+0xFFEEFFFF,
+0xFFD9FFFF,
+0xFF6AB0D4,
+0xFF3B9BCD,
+0xFF5EB1D9,
+0xFFE9FFFF,
+0xFFFEFFFB,
+0xFFFFFEFF,
+0xFFFDFCFF,
+0xFFF9FCFF,
+0xFFF7FFFF,
+0xFFF2FFFF,
+0xFFE4FFFF,
+0xFF9FE1FF,
+0xFF4A9BC6,
+0xFF4191B6,
+0xFFC6FFFF,
+0xFFDFFFFF,
+0xFFF2FFFF,
+0xFFFCFFFD,
+0xFFFFFEF9,
+0xFFFFFFFA,
+0xFFF5FEFB,
+0xFFF1FFFF,
+0xFFD3FFFF,
+0xFF4093BD,
+0xFF44A3D3,
+0xFF448BB7,
+0xFFA1D6F6,
+0xFFE6FFFF,
+0xFFECFFFF,
+0xFFEAFFFF,
+0xFFEBFFFF,
+0xFFEEFFFF,
+0xFFE8FFFF,
+0xFFE4FFFF,
+0xFFB2E5FF,
+0xFF4493BE,
+0xFF45A0CF,
+0xFF4394BF,
+0xFFC2FBFF,
+0xFFF1FFFF,
+0xFFFDFFF4,
+0xFFFEFFFF,
+0xFFFBFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFBFFFF,
+0xFFD1DEF1,
+0xFF000322,
+0xFF101745,
+0xFF000330,
+0xFFA5A6C4,
+0xFFFCFEFF,
+0xFFFBFCFE,
+0xFFFEFFFF,
+0xFFFBFCFF,
+0xFFFCFFFF,
+0xFFF6FBFE,
+0xFFF9FFFF,
+0xFFF8FFFF,
+0xFFE4EFFF,
+0xFF0A163E,
+0xFF031346,
+0xFF001446,
+0xFF0B1D4B,
+0xFF000630,
+0xFFB2B9D6,
+0xFFFEFEFF,
+0xFFFBFBFB,
+0xFFFDFFFE,
+0xFFF9FDFF,
+0xFF7880A4,
+0xFF040F3C,
+0xFF030B32,
+0xFFCACFEC,
+0xFFFEFEFF,
+0xFFFEFDFB,
+0xFFFFFDFC,
+0xFFFFFFFD,
+0xFFFEFEFC,
+0xFFFEFEFC,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFEFF,
+0xFFFCFEFF,
+0xFFA5AACA,
+0xFF050A34,
+0xFF050A30,
+0xFFA6ACC6,
+0xFFFAFDFF,
+0xFFFBFFFE,
+0xFFFBFFFF,
+0xFFF8FFFF,
+0xFF1A2042,
+0xFF0F1640,
+0xFF030A36,
+0xFF3A4266,
+0xFFF3FFFF,
+0xFFF7FFFF,
+0xFFF9FFFF,
+0xFFF8FDFF,
+0xFFFCFFFF,
+0xFFFAFAFF,
+0xFFFEFEFF,
+0xFFFBFDFF,
+0xFFE9EEFF,
+0xFF11193D,
+0xFF0A1744,
+0xFF021446,
+0xFF051D4B,
+0xFF000F30,
+0xFFC0CCDA,
+0xFFF9FEFF,
+0xFFFEFFFD,
+0xFFF9FFFF,
+0xFF3F5273,
+0xFF001042,
+0xFF08154A,
+0xFF030B3A,
+0xFFBAC1DE,
+0xFFF9FFFF,
+0xFFFBFEFF,
+0xFFFCFFFF,
+0xFFFAFFFF,
+0xFFF9FEFF,
+0xFFFBFFFF,
+0xFFD4DAF0,
+0xFF000C33,
+0xFF051546,
+0xFF031346,
+0xFF091642,
+0xFF0A1030,
+0xFFFBFDFF,
+0xFFFBFBFF,
+0xFFFEFFFF,
+0xFFFCFFFF,
+0xFFF6F9FF,
+0xFFFEFDFF,
+0xFFFBFDFF,
+0xFF7E84A8,
+0xFF06123C,
+0xFF061340,
+0xFF3E486B,
+0xFFFAF9FF,
+0xFFFFFEFF,
+0xFFFEFDF9,
+0xFFFBFBFD,
+0xFFFCFEFF,
+0xFF7A7F9C,
+0xFF000833,
+0xFF0A1240,
+0xFF11163C,
+0xFFF8FDFF,
+0xFFF6FCFF,
+0xFFF9FFFF,
+0xFFF8FFFF,
+0xFFF8FFFF,
+0xFFFFFDFF,
+0xFFFBF9FF,
+0xFFFEFDFF,
+0xFFF9FEFF,
+0xFF3F476B,
+0xFF000B33,
+0xFF041237,
+0xFF35405E,
+0xFFF7FAFF,
+0xFFFDFBFF,
+0xFFFEFBFF,
+0xFFF9F9FF,
+0xFFF5FFFF,
+0xFF13243E,
+0xFF051C46,
+0xFF001848,
+0xFF000D38,
+0xFF6B789A,
+0xFFF9FEFF,
+0xFFFCFEFF,
+0xFFF8FFFF,
+0xFFF7FEFF,
+0xFFF9FEFF,
+0xFFFAFFFF,
+0xFFFBFEFF,
+0xFFBCC0DB,
+0xFF020933,
+0xFF070F3D,
+0xFF00052F,
+0xFFF0F3FF,
+0xFFFCFCFF,
+0xFFFFFFFF,
+0xFFFBFBFB,
+0xFFFFFFFF,
+0xFFFCFFFF,
+0xFFF9FFFF,
+0xFFF4FFFF,
+0xFF000F30,
+0xFF021648,
+0xFF1D2E5C,
+0xFFF5FDFF,
+0xFFFCFFFF,
+0xFFFEFFFF,
+0xFFFDFFFA,
+0xFFF9FBF6,
+0xFFFCFFFF,
+0xFFF6FEFF,
+0xFFAFB4D1,
+0xFF00002B,
+0xFF0F123F,
+0xFF020C2F,
+0xFFD4E0F6,
+0xFFF8FFFF,
+0xFFF9FEFF,
+0xFFFEFFFF,
+0xFFFFFEFF,
+0xFFF9F9FF,
+0xFFFCFEFF,
+0xFFF8FEFF,
+0xFFF7FFFF,
+0xFF6D7993,
+0xFF000A2D,
+0xFF0A1438,
+0xFF0D1732,
+0xFFF5FEFF,
+0xFFFBFFFF,
+0xFFFFFFFA,
+0xFFFFFFFB,
+0xFFF5FAFD,
+0xFFF7FFFF,
+0xFF2E3959,
+0xFF08143E,
+0xFF09123D,
+0xFF323C5F,
+0xFFF5FFFF,
+0xFFF6FFFF,
+0xFFF5FEFF,
+0xFFF9FFFF,
+0xFFFAFDFF,
+0xFFFEFFFF,
+0xFFFFFDFF,
+0xFFFFFDFF,
+0xFFF6FDFF,
+0xFF5D6782,
+0xFF000731,
+0xFF081245,
+0xFF07184E,
+0xFF021442,
+0xFF44546D,
+0xFFF2FCFF,
+0xFFFEFEFF,
+0xFFFFFFFF,
+0xFFFEFFFB,
+0xFFFCFFFA,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFDFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFB,
+0xFFFEFFFB,
+0xFFFFFEFF,
+0xFFF7FFFF,
+0xFFE6FFFF,
+0xFF72B1D0,
+0xFF3EA0D1,
+0xFF4DA1CD,
+0xFFEAFFFF,
+0xFFFFFFFF,
+0xFFFEFEFE,
+0xFFFEFFFD,
+0xFFFCFEFB,
+0xFFFFFFFF,
+0xFFFFFDFF,
+0xFFF8FFFF,
+0xFFE4FFFF,
+0xFF68A7CA,
+0xFF3F9BCE,
+0xFF62B4DC,
+0xFFE8FFFF,
+0xFFFEFFFB,
+0xFFFFFAFF,
+0xFFFFFDFF,
+0xFFFFFEFF,
+0xFFFEFFFF,
+0xFFFDFFFE,
+0xFFEFFFFF,
+0xFFA2DDFD,
+0xFF4A95BD,
+0xFF4B94B5,
+0xFFCBFFFF,
+0xFFF1FFFF,
+0xFFFFFFFB,
+0xFFFFFDF9,
+0xFFFFFEFA,
+0xFFFFFFFB,
+0xFFF5FFFF,
+0xFFE1FFFF,
+0xFF63A3BF,
+0xFF42A4D1,
+0xFF3897C5,
+0xFFB7E9FF,
+0xFFEEFFFF,
+0xFFF9FFFF,
+0xFFFFFFF8,
+0xFFF9FEF8,
+0xFFFBFFFD,
+0xFFFCFFFF,
+0xFFFAFEFF,
+0xFFFBFFFF,
+0xFFEEFFFF,
+0xFFCDFFFF,
+0xFF4594BF,
+0xFF42A3D0,
+0xFF4F9FC0,
+0xFFE3FFFF,
+0xFFF9FFFB,
+0xFFFCFFFF,
+0xFFFDFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFEFF,
+0xFFF9FFFF,
+0xFF1C2B4A,
+0xFF081740,
+0xFF000630,
+0xFFA6A9CA,
+0xFFFEFDFF,
+0xFFFFFEFF,
+0xFFFFFFFA,
+0xFFFFFFFA,
+0xFFFFFEFF,
+0xFFFDFBFE,
+0xFFFFFFFA,
+0xFFFEFFF8,
+0xFFF8FDF6,
+0xFFF8FFFF,
+0xFFEFF8FF,
+0xFF020F3B,
+0xFF021744,
+0xFF031845,
+0xFF05103D,
+0xFFB4B9D9,
+0xFFFCFCFF,
+0xFFFFFEFF,
+0xFFFDFDFD,
+0xFFFBFFFF,
+0xFF7D87AA,
+0xFF030E3B,
+0xFF000730,
+0xFFCDD2EF,
+0xFFFCFDFF,
+0xFFFFFFFB,
+0xFFFFFEFF,
+0xFFFFFCFD,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFDFEFF,
+0xFFFDFEFF,
+0xFFFFFEFF,
+0xFFFCFEFF,
+0xFFA3A7CA,
+0xFF020A31,
+0xFF030C2D,
+0xFFA6ACC2,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFF8FEFF,
+0xFF878EA8,
+0xFF040B37,
+0xFF080E3E,
+0xFF2D3157,
+0xFFF9FEFF,
+0xFFF9FFFF,
+0xFFFBFFFD,
+0xFFFDFFFC,
+0xFFFFFFFF,
+0xFFFFFDFF,
+0xFFFFFDFF,
+0xFFFFFEFD,
+0xFFFFFFFF,
+0xFFFCFEFF,
+0xFFF7FEFF,
+0xFF000C36,
+0xFF081A4C,
+0xFF011949,
+0xFF000E30,
+0xFFC3CDD9,
+0xFFFCFFFF,
+0xFFFDFFFC,
+0xFFF8FFFF,
+0xFF405276,
+0xFF031749,
+0xFF051141,
+0xFF41496E,
+0xFFF8FDFF,
+0xFFFBFEFF,
+0xFFFFFEFF,
+0xFFFAF9F7,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFF9F9FB,
+0xFFFBFFFF,
+0xFF5E688B,
+0xFF00113F,
+0xFF09194D,
+0xFF000C38,
+0xFFA2A6BF,
+0xFFF9F9FF,
+0xFFFFFFFD,
+0xFFFFFEF9,
+0xFFFEFEFC,
+0xFFFFFFFF,
+0xFFFFFDFF,
+0xFFFCFBFF,
+0xFFF8FEFF,
+0xFF131E3E,
+0xFF071441,
+0xFF000730,
+0xFFF8FAFF,
+0xFFFFFEFF,
+0xFFFCFCFC,
+0xFFFEFFFF,
+0xFFE0E5FB,
+0xFF000526,
+0xFF0C153E,
+0xFF0A133A,
+0xFFF7FEFF,
+0xFFF4FAFF,
+0xFFF9FFFF,
+0xFFF7FDFD,
+0xFFFBFFFF,
+0xFFFCFFFF,
+0xFFFCFBFF,
+0xFFFFFDFF,
+0xFFFFFCFF,
+0xFFFEFEFF,
+0xFFF8FEFF,
+0xFF313C5C,
+0xFF06143B,
+0xFF00062A,
+0xFFB0B2CB,
+0xFFFFFDFF,
+0xFFFFFBFF,
+0xFFFFFEFF,
+0xFFF7FFFF,
+0xFF11223C,
+0xFF021943,
+0xFF001645,
+0xFF1F2F51,
+0xFFF7FFFF,
+0xFFFEFEFF,
+0xFFFEFCFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFDFEF9,
+0xFFFFFFFD,
+0xFFFEFFFF,
+0xFFF9FCFF,
+0xFF6E7496,
+0xFF09123D,
+0xFF040B39,
+0xFF797DA2,
+0xFFFCFEFF,
+0xFFFDFDFD,
+0xFFFFFFFB,
+0xFFFFFFFA,
+0xFFFFFFFA,
+0xFFFCFFFF,
+0xFFF2FAFF,
+0xFF051235,
+0xFF011144,
+0xFF273461,
+0xFFF8FDFF,
+0xFFFCFDFF,
+0xFFFFFFFB,
+0xFFFBFCF4,
+0xFFFFFFFA,
+0xFFFCFFFF,
+0xFFF7FDFF,
+0xFF03092D,
+0xFF111240,
+0xFF04062F,
+0xFFE1E7FF,
+0xFFF3FCFF,
+0xFFFBFFFD,
+0xFFFEFFFA,
+0xFFFBFBF9,
+0xFFFFFEFF,
+0xFFFFFDFF,
+0xFFFDFCFF,
+0xFFFCFEFD,
+0xFFFAFFFF,
+0xFFF8FFFF,
+0xFF5F6887,
+0xFF040D34,
+0xFF041133,
+0xFF708090,
+0xFFF7FFFF,
+0xFFFEFFFD,
+0xFFFEFEFE,
+0xFFF9FFFF,
+0xFFA4AEC7,
+0xFF00072F,
+0xFF05103D,
+0xFF222A4E,
+0xFFF8FEFF,
+0xFFFBFFFF,
+0xFFFCFFFD,
+0xFFFEFFFD,
+0xFFFDFDFB,
+0xFFFFFFFB,
+0xFFFFFEFB,
+0xFFFFFEFB,
+0xFFFFFEFF,
+0xFFF9FFFF,
+0xFFF4FDFF,
+0xFF515680,
+0xFF050C42,
+0xFF09184F,
+0xFF031543,
+0xFF3A4862,
+0xFFF7FFFF,
+0xFFFEFEFF,
+0xFFFFFFFF,
+0xFFFEFFFA,
+0xFFFCFFF8,
+0xFFFEFFFD,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFB,
+0xFFFEFFFB,
+0xFFFFFEFF,
+0xFFF7FFFF,
+0xFFE6FFFF,
+0xFF72B1D0,
+0xFF3EA0D1,
+0xFF4DA1CD,
+0xFFEAFFFF,
+0xFFFFFFFF,
+0xFFFEFEFE,
+0xFFFEFFFD,
+0xFFFCFFFD,
+0xFFFEFFFD,
+0xFFFFFEFF,
+0xFFF8FFFF,
+0xFFE5FFFF,
+0xFF6CA8CC,
+0xFF439ACF,
+0xFF65B2DE,
+0xFFE9FFFF,
+0xFFFEFFFD,
+0xFFFFFDFF,
+0xFFFFFCFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFA,
+0xFFEEFFFF,
+0xFF9FDFFB,
+0xFF4698BE,
+0xFF4994B4,
+0xFFCAFFFF,
+0xFFF0FFFF,
+0xFFFFFEFF,
+0xFFFFFAFF,
+0xFFFFFBFF,
+0xFFFFFEFF,
+0xFFF0FFFF,
+0xFFACE8FF,
+0xFF4296BB,
+0xFF429DC9,
+0xFF83CDF0,
+0xFFE8FFFF,
+0xFFFBFFFF,
+0xFFFEFFFD,
+0xFFFFFFFB,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFEFD,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFF9FFFF,
+0xFFEDFFFF,
+0xFFB0E2F9,
+0xFF3F9AC6,
+0xFF3A96BF,
+0xFFAFE0F1,
+0xFFF0FFFF,
+0xFFFBFFFF,
+0xFFFDFCFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFEFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFDFDFB,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFEFF,
+0xFFC1C6DC,
+0xFF000630,
+0xFF091642,
+0xFF3C4262,
+0xFFFCFDFF,
+0xFFFFFEFF,
+0xFFFAF9F7,
+0xFFFFFEFF,
+0xFFFEFEFF,
+0xFFFFFEFF,
+0xFFFDFBFF,
+0xFFFFFEFB,
+0xFFFFFFF8,
+0xFFFFFFF7,
+0xFFFCFEFD,
+0xFFFBFFFF,
+0xFF9CA3BD,
+0xFF000C30,
+0xFF091C46,
+0xFF010937,
+0xFFB4B7D8,
+0xFFFFFCFF,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFAFEFF,
+0xFF7A84A7,
+0xFF020F3B,
+0xFF000A30,
+0xFFCAD1EB,
+0xFFFCFFFF,
+0xFFFDFCF8,
+0xFFFFFEFF,
+0xFFFFFDFF,
+0xFFFFFEFF,
+0xFFFEFEFE,
+0xFFFDFEFF,
+0xFFFDFEFF,
+0xFFFFFEFF,
+0xFFF8FAFF,
+0xFFA3A8C8,
+0xFF040C31,
+0xFF030C2B,
+0xFFA3ACBD,
+0xFFFBFFFF,
+0xFFFCFFFF,
+0xFFF8FFFF,
+0xFF0B1435,
+0xFF0D1345,
+0xFF030736,
+0xFFF0F0FF,
+0xFFF9F7FF,
+0xFFFFFFFF,
+0xFFFFFFFB,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFDFF,
+0xFFFFFDFF,
+0xFFFFFDFA,
+0xFFFFFFFB,
+0xFFFEFFFF,
+0xFFF8FEFF,
+0xFFA1ACCA,
+0xFF000B37,
+0xFF091B4D,
+0xFF000A33,
+0xFFC3C9D7,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFBFFFF,
+0xFF425276,
+0xFF001240,
+0xFF000C34,
+0xFFAFB6D0,
+0xFFFBFFFF,
+0xFFFFFFFF,
+0xFFFFFCFF,
+0xFFFFFCFF,
+0xFFFFFBFF,
+0xFFFFFDFF,
+0xFFFFFFFD,
+0xFFFEFFFF,
+0xFFCFD5ED,
+0xFF00082E,
+0xFF0C1A4B,
+0xFF000D34,
+0xFFF8FEFF,
+0xFFFDFEFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFCFFFF,
+0xFF798092,
+0xFF030C33,
+0xFF020B34,
+0xFFB6BDD0,
+0xFFF9FFFF,
+0xFFF9FCFF,
+0xFFFBFFFF,
+0xFF5A617D,
+0xFF060E32,
+0xFF010C2C,
+0xFFAFB6D0,
+0xFFF9FFFF,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFBFF,
+0xFFFFFCFF,
+0xFFFBFFFF,
+0xFFF0F9FF,
+0xFF000929,
+0xFF0C163A,
+0xFF212240,
+0xFFFFFCFF,
+0xFFFFFBFF,
+0xFFFFFDFF,
+0xFFF6FDFF,
+0xFF162441,
+0xFF06184A,
+0xFF000D3B,
+0xFFA5ADC2,
+0xFFFBFEFF,
+0xFFFFFEFF,
+0xFFFFFDFF,
+0xFFFFFDFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFCFFFF,
+0xFFF2FAFF,
+0xFF000929,
+0xFF0A113D,
+0xFF2A2E53,
+0xFFFBFFFF,
+0xFFFEFFFF,
+0xFFFEFFFD,
+0xFFFEFFFA,
+0xFFFFFFF8,
+0xFFFFFFFF,
+0xFFF7FBFF,
+0xFF070E38,
+0xFF071347,
+0xFF232E5B,
+0xFFFBFDFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFCFCFA,
+0xFFFEFEFC,
+0xFFFBFFFF,
+0xFF8B91B1,
+0xFF010A33,
+0xFF0C1139,
+0xFF7E81A0,
+0xFFFEFDFF,
+0xFFFFFEFF,
+0xFFFFFFF8,
+0xFFFFFFF8,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFF8,
+0xFFFFFEFA,
+0xFFFDFDFF,
+0xFFFBFDFF,
+0xFF0B1038,
+0xFF0A163E,
+0xFF000E2A,
+0xFFF2FFFF,
+0xFFFEFEFF,
+0xFFFFFDFF,
+0xFFF8FAFF,
+0xFF1A2044,
+0xFF0D1641,
+0xFF00082F,
+0xFFE5EBFF,
+0xFFFBFEFF,
+0xFFFFFFFD,
+0xFFFFFFFA,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFFFFFB,
+0xFFFFFEFB,
+0xFFFFFFFB,
+0xFFFBFFFC,
+0xFFF9FFFF,
+0xFFF8FDFF,
+0xFF070D3D,
+0xFF09164A,
+0xFF02133F,
+0xFF3F4D67,
+0xFFF7FFFF,
+0xFFFFFDFF,
+0xFFFFFEFF,
+0xFFFEFFFB,
+0xFFFCFFFA,
+0xFFFEFFFD,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFB,
+0xFFFEFFFB,
+0xFFFFFEFF,
+0xFFF7FFFF,
+0xFFE6FFFF,
+0xFF72B1D0,
+0xFF3EA0D1,
+0xFF4DA1CD,
+0xFFEAFFFF,
+0xFFFFFFFF,
+0xFFFEFEFE,
+0xFFFEFFFF,
+0xFFFCFFFD,
+0xFFFCFFFD,
+0xFFFFFFFF,
+0xFFF7FFFF,
+0xFFE3FFFF,
+0xFF6CA8CC,
+0xFF4499CF,
+0xFF65B2DE,
+0xFFE9FFFF,
+0xFFFEFFFD,
+0xFFFFFDFF,
+0xFFFFFDFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFEFFFA,
+0xFFEDFFFF,
+0xFF9DE0FB,
+0xFF4599BE,
+0xFF4993B6,
+0xFFCDFFFF,
+0xFFF2FFFF,
+0xFFFFFDFF,
+0xFFFFFBFF,
+0xFFFFFBFF,
+0xFFFDFDFD,
+0xFFEAFFFF,
+0xFF63B1D5,
+0xFF3D9FCE,
+0xFF459AC3,
+0xFFCFFFFF,
+0xFFEBFFFF,
+0xFFF8FFFF,
+0xFFF8FFFF,
+0xFFF8FFFF,
+0xFFF9FFFF,
+0xFFFBFFFF,
+0xFFFBFFFF,
+0xFFF9FFFF,
+0xFFF7FFFF,
+0xFFF5FFFF,
+0xFFF4FFFF,
+0xFFE3FFFF,
+0xFF53ABD3,
+0xFF3E9DC9,
+0xFF6BA7C1,
+0xFFE9FFFF,
+0xFFF3FAFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFEFE,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFEFFFF,
+0xFFFCFDFF,
+0xFFFAF9FF,
+0xFF5C607B,
+0xFF020D3B,
+0xFF000633,
+0xFFD2D8F0,
+0xFFF5F8FF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFCFCFE,
+0xFFFDFEFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFEFD,
+0xFFFFFCF9,
+0xFFFFFEFB,
+0xFFFEFAF9,
+0xFFFFFFFF,
+0xFFF8FEFF,
+0xFF0F1E3D,
+0xFF0A1942,
+0xFF040B35,
+0xFFB7B7D9,
+0xFFFFFCFF,
+0xFFFFFDFF,
+0xFFFCFBF9,
+0xFFFBFFFF,
+0xFF7E87A8,
+0xFF03103A,
+0xFF000A2D,
+0xFFC9D4EA,
+0xFFFBFFFF,
+0xFFFFFFFB,
+0xFFFEFCFF,
+0xFFFFFEFF,
+0xFFFFFDFE,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFAFEFF,
+0xFFFFFEFF,
+0xFFFEFDFF,
+0xFFA3A8C6,
+0xFF040C30,
+0xFF040F2B,
+0xFFA3ABBE,
+0xFFFBFFFF,
+0xFFF8FDFF,
+0xFFBBC3D8,
+0xFF00082C,
+0xFF060E3F,
+0xFF565B85,
+0xFFFCFAFF,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFFFFFB,
+0xFFFFFEFC,
+0xFFFFFEFF,
+0xFFFFFDFF,
+0xFFFFFDFE,
+0xFFFFFFFA,
+0xFFFAF9F4,
+0xFFFEFFFD,
+0xFFFAFEFF,
+0xFFF8FEFF,
+0xFF172145,
+0xFF081245,
+0xFF000934,
+0xFFC8CBDC,
+0xFFFFFFFF,
+0xFFFFFEFC,
+0xFFFBFDFF,
+0xFF435176,
+0xFF00113F,
+0xFF040E31,
+0xFFDDE4F7,
+0xFFFCFFFF,
+0xFFFFFFFD,
+0xFFFFFCFF,
+0xFFFFFBFF,
+0xFFFFFCFF,
+0xFFFFFDFF,
+0xFFFFFFFD,
+0xFFFEFFFF,
+0xFFF6FBFF,
+0xFF00072B,
+0xFF051342,
+0xFF16244B,
+0xFFF9FFFF,
+0xFFFDFFFC,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFEFCFF,
+0xFFFFFEFF,
+0xFFFEFFFF,
+0xFFADB1BD,
+0xFF060E33,
+0xFF020B34,
+0xFF8994A8,
+0xFFF8FFFF,
+0xFFF9FFFF,
+0xFFF3FAFF,
+0xFF040F2F,
+0xFF0A173A,
+0xFF0F1A38,
+0xFFF7FFFF,
+0xFFFBFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFEFF,
+0xFFFCFFFF,
+0xFFFEFEFF,
+0xFFFFFEFF,
+0xFFFFFDFF,
+0xFFFFFBFF,
+0xFFFDFAFF,
+0xFFFBFFFF,
+0xFFF5FFFF,
+0xFF52617E,
+0xFF091639,
+0xFF000124,
+0xFFDAD7F2,
+0xFFFFFAFF,
+0xFFFFFDFF,
+0xFFF8FFFF,
+0xFF162345,
+0xFF08154A,
+0xFF000C38,
+0xFFF0F4FF,
+0xFFFFFFFB,
+0xFFFFFEFB,
+0xFFFFFDFF,
+0xFFFFFDFF,
+0xFFFFFEFF,
+0xFFFFFDFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFCFFFF,
+0xFFF7FFFF,
+0xFF212C48,
+0xFF0B123C,
+0xFF060C30,
+0xFFFBFFFF,
+0xFFF8FCFB,
+0xFFFEFFFF,
+0xFFFFFFFD,
+0xFFFFFFFA,
+0xFFFFFEFF,
+0xFFF9FBFF,
+0xFF070E38,
+0xFF071345,
+0xFF252E59,
+0xFFFCFDFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFF6FCFF,
+0xFF242E52,
+0xFF081340,
+0xFF00092D,
+0xFFF8FDFF,
+0xFFFEFBFF,
+0xFFFFFBFF,
+0xFFFFFDFF,
+0xFFFDFFFE,
+0xFFFBFEFF,
+0xFFFBFEFF,
+0xFFFBFEFF,
+0xFFFDFEFF,
+0xFFFEFDF9,
+0xFFFDFBFC,
+0xFFFEFCFF,
+0xFFFBFBFF,
+0xFF9295C0,
+0xFF020D3B,
+0xFF000930,
+0xFF9EACC7,
+0xFFFBFDFF,
+0xFFFFFDFF,
+0xFFDADDFC,
+0xFF030832,
+0xFF060D39,
+0xFF464C6E,
+0xFFFBFEFF,
+0xFFFFFFFF,
+0xFFFFFEFB,
+0xFFFFFEFB,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFB,
+0xFFFEFFFA,
+0xFFF8FEFE,
+0xFFFBFDFF,
+0xFF8A90B4,
+0xFF020F3C,
+0xFF05143F,
+0xFF424E68,
+0xFFF7FDFF,
+0xFFFFFDFF,
+0xFFFFFEFF,
+0xFFFEFFFD,
+0xFFFCFFFB,
+0xFFFEFFFD,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFB,
+0xFFFEFFFB,
+0xFFFFFEFF,
+0xFFF7FFFF,
+0xFFE6FFFF,
+0xFF72B1D0,
+0xFF3EA0D1,
+0xFF4DA1CD,
+0xFFEAFFFF,
+0xFFFFFFFF,
+0xFFFEFEFE,
+0xFFFEFFFF,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFF4FFFF,
+0xFFE2FFFF,
+0xFF6CA8CC,
+0xFF419CCB,
+0xFF64B3DC,
+0xFFEAFFFF,
+0xFFFFFFFF,
+0xFFFFFEFD,
+0xFFFFFDFD,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFBFFFF,
+0xFFEAFFFF,
+0xFF9BE1FB,
+0xFF4698BD,
+0xFF4D91B6,
+0xFFD2FEFF,
+0xFFF7FFFF,
+0xFFFFFEFF,
+0xFFFFFFFA,
+0xFFFEFFFA,
+0xFFFAFFFE,
+0xFFE2FFFF,
+0xFF429ECD,
+0xFF35A0D6,
+0xFF78CCF1,
+0xFFD0FFFF,
+0xFFE0FFFF,
+0xFFE6FFFF,
+0xFFEAFFFF,
+0xFFEAFFFF,
+0xFFE7FFFF,
+0xFFE7FFFF,
+0xFFE7FFFF,
+0xFFE6FFFF,
+0xFFE3FFFF,
+0xFFE4FFFF,
+0xFFE8FFFF,
+0xFFDFFFFF,
+0xFF95E7FF,
+0xFF4099C3,
+0xFF5699B6,
+0xFFDDFFFF,
+0xFFF8FFFF,
+0xFFFFFDFF,
+0xFFFFFEFF,
+0xFFFEFFFF,
+0xFFFFFFFD,
+0xFFFFFFFB,
+0xFFFFFFFB,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFEFEFE,
+0xFFFEFFFB,
+0xFFFCFEF9,
+0xFFFDFEFF,
+0xFFFEFEFF,
+0xFFFCFEFF,
+0xFF181C37,
+0xFF0A1741,
+0xFF07153A,
+0xFFF7FFFF,
+0xFFFBFFFF,
+0xFFFEFFFF,
+0xFFFFFEFF,
+0xFFFBFFFF,
+0xFFFCFFFF,
+0xFFFAFFFC,
+0xFFFCFFFB,
+0xFFFFFFFD,
+0xFFFFFAFE,
+0xFFFFF9FF,
+0xFFFFFCFF,
+0xFFFDFBFE,
+0xFFFBFFFF,
+0xFF5D6B86,
+0xFF051338,
+0xFF01062E,
+0xFFBAB9D9,
+0xFFFFFCFF,
+0xFFFFFDFF,
+0xFFFFFEFC,
+0xFFFBFFFF,
+0xFF7B84A3,
+0xFF010F36,
+0xFF000D2F,
+0xFFCDD5EA,
+0xFFFAFEFF,
+0xFFFFFFFB,
+0xFFFDFDFF,
+0xFFFFFEFF,
+0xFFFDFBFC,
+0xFFFFFEFF,
+0xFFFCFFFF,
+0xFFFAFEFF,
+0xFFFDFDFD,
+0xFFFEFEFF,
+0xFFA3A8C5,
+0xFF020C2F,
+0xFF020D2B,
+0xFFA4ACC3,
+0xFFF9FDFF,
+0xFFFBFFFF,
+0xFF79839E,
+0xFF061034,
+0xFF020B36,
+0xFFB0B5DB,
+0xFFFCFDFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFDFEF9,
+0xFFFEFEFC,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFEFEFC,
+0xFFFEFFF9,
+0xFFFFFFFA,
+0xFFFAFCF9,
+0xFFFCFFFF,
+0xFFFAFCFF,
+0xFF6F7396,
+0xFF070B3B,
+0xFF050833,
+0xFFC7C8DC,
+0xFFFEFDFF,
+0xFFFFFFFD,
+0xFFFCFFFF,
+0xFF465278,
+0xFF03113E,
+0xFF00082C,
+0xFFF8FEFF,
+0xFFFBFFFF,
+0xFFFEFFFD,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFCFFFF,
+0xFFF9FEFF,
+0xFF01092D,
+0xFF081645,
+0xFF29385F,
+0xFFF8FFFF,
+0xFFFCFFFD,
+0xFFFCFFFF,
+0xFFFAFDFF,
+0xFFFBFFFF,
+0xFFFCFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFAFCFB,
+0xFFCDD1DD,
+0xFF030A34,
+0xFF030C37,
+0xFF808B9F,
+0xFFF7FFFF,
+0xFFF7FEFF,
+0xFFCCD4E7,
+0xFF00092C,
+0xFF04133C,
+0xFF6E7D9E,
+0xFFF5FFFF,
+0xFFF9FEFF,
+0xFFFCFDFF,
+0xFFFCFCFF,
+0xFFFCFCFF,
+0xFFFEFCFF,
+0xFFFEFCFF,
+0xFFFFFCFF,
+0xFFFFFCFF,
+0xFFFEFCFF,
+0xFFFAFCFF,
+0xFFF7FFFF,
+0xFFF2FFFF,
+0xFFADC2E1,
+0xFF00092F,
+0xFF071039,
+0xFF9396B7,
+0xFFFFFDFF,
+0xFFFDFDFF,
+0xFFF7FFFF,
+0xFF18244A,
+0xFF031044,
+0xFF041038,
+0xFFFEFEFF,
+0xFFFFFCF5,
+0xFFFFFFFB,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFEFF,
+0xFFFBFFFF,
+0xFFF5FFFF,
+0xFF46546E,
+0xFF071039,
+0xFF000125,
+0xFFF8FCFF,
+0xFFFCFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFEFEFF,
+0xFFF7FBFF,
+0xFF061034,
+0xFF071441,
+0xFF232F55,
+0xFFFBFEFF,
+0xFFFFFFFF,
+0xFFFDFDFF,
+0xFFFEFFFF,
+0xFFFBFFFF,
+0xFFF7FFFF,
+0xFF000D32,
+0xFF0A1845,
+0xFF3B496E,
+0xFFF5FEFF,
+0xFFFCFBFF,
+0xFFFFFAFF,
+0xFFFCFCFF,
+0xFFF9FEFF,
+0xFFF8FFFF,
+0xFFF7FFFF,
+0xFFF7FFFF,
+0xFFF8FFFF,
+0xFFFAFEFF,
+0xFFFBFEFF,
+0xFFFBFDFF,
+0xFFF6F9FF,
+0xFFE1E5FF,
+0xFF040C3D,
+0xFF000C3C,
+0xFF5E6B8D,
+0xFFF9FFFF,
+0xFFFAFEFF,
+0xFF979BBE,
+0xFF030734,
+0xFF040931,
+0xFFA2A5C4,
+0xFFFEFDFF,
+0xFFFFFDFF,
+0xFFFFFCFF,
+0xFFFFFDFF,
+0xFFFEFFFF,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFB,
+0xFFF8FAF7,
+0xFFFEFFFF,
+0xFFE7ECFF,
+0xFF00062C,
+0xFF020F39,
+0xFF434C69,
+0xFFF9FEFF,
+0xFFFFFDFF,
+0xFFFFFEFF,
+0xFFFEFFFF,
+0xFFFCFFFF,
+0xFFFEFFFD,
+0xFFFEFFFD,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFB,
+0xFFFEFFFB,
+0xFFFFFEFF,
+0xFFF7FFFF,
+0xFFE6FFFF,
+0xFF72B1D0,
+0xFF3EA0D1,
+0xFF4DA1CD,
+0xFFEAFFFF,
+0xFFFFFFFF,
+0xFFFEFEFE,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFF5FFFF,
+0xFFE2FFFF,
+0xFF6AA9CA,
+0xFF409DC9,
+0xFF64B3DA,
+0xFFEBFFFF,
+0xFFFFFEFF,
+0xFFFFFEFD,
+0xFFFFFEFD,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFCFFFF,
+0xFFEBFFFF,
+0xFF9DE0FB,
+0xFF4699BB,
+0xFF4F90B6,
+0xFFD2FEFF,
+0xFFF7FFFF,
+0xFFFFFFFD,
+0xFFFCFFFA,
+0xFFF9FFFA,
+0xFFF9FFFF,
+0xFFDAFFFF,
+0xFF3494C6,
+0xFF35A6DE,
+0xFF63BBE3,
+0xFF78BDDE,
+0xFF7FBCDB,
+0xFF82B9D7,
+0xFF82B7D6,
+0xFF82B7D6,
+0xFF80B9D6,
+0xFF7EBAD4,
+0xFF7EBBD0,
+0xFF7EBAD2,
+0xFF7DBAD6,
+0xFF7EBAD6,
+0xFF86BAD0,
+0xFF7DBBD4,
+0xFF64BCE2,
+0xFF46A2C9,
+0xFF4790B0,
+0xFFC6F5FF,
+0xFFF5FFFF,
+0xFFFEFCFF,
+0xFFFFFEFF,
+0xFFFEFFFF,
+0xFFFFFFFD,
+0xFFFFFFFB,
+0xFFFFFFFB,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFB,
+0xFFFEFFFB,
+0xFFFCFDFF,
+0xFFFCFFFF,
+0xFFFAFBFF,
+0xFF020724,
+0xFF05143D,
+0xFF2B3B5D,
+0xFFF4FEFF,
+0xFFFBFFFF,
+0xFFFFFFFF,
+0xFFFDFCFF,
+0xFFFCFFFF,
+0xFFFAFFFF,
+0xFFFBFFFB,
+0xFFFBFFFA,
+0xFFFFFDFE,
+0xFFFFFDFF,
+0xFFFFF8FF,
+0xFFFFFCFF,
+0xFFFFFEFF,
+0xFFF7FBFF,
+0xFFA0ACC6,
+0xFF000D30,
+0xFF03082E,
+0xFFB9BAD8,
+0xFFFFF9FF,
+0xFFFFFDFF,
+0xFFFFFFFD,
+0xFFFAFEFF,
+0xFF7C85A4,
+0xFF020E36,
+0xFF010B2E,
+0xFFCBD3E8,
+0xFFFBFFFF,
+0xFFFEFEFC,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFBFFFE,
+0xFFFCFFFF,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFA7ACC9,
+0xFF020C30,
+0xFF010B2E,
+0xFFA6ADC7,
+0xFFFAFEFF,
+0xFFFBFFFF,
+0xFF4F5875,
+0xFF071437,
+0xFF00082F,
+0xFFE6ECFF,
+0xFFFAFDFF,
+0xFFFDFEFF,
+0xFFFDFEFF,
+0xFFFCFEFD,
+0xFFFDFFFC,
+0xFFFEFFFD,
+0xFFFEFFFF,
+0xFFFEFEFC,
+0xFFFFFFFD,
+0xFFFDFEF9,
+0xFFFFFFFB,
+0xFFFEFFFF,
+0xFFF7FAFF,
+0xFFA6AAC7,
+0xFF080B38,
+0xFF040732,
+0xFFC5C6DA,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFCFFFF,
+0xFF485178,
+0xFF061242,
+0xFF000126,
+0xFFF8FEFF,
+0xFFFBFFFF,
+0xFFFEFFFB,
+0xFFFFFFFB,
+0xFFFFFFFD,
+0xFFFEFFFF,
+0xFFFCFFFF,
+0xFFFBFFFF,
+0xFFFBFFFF,
+0xFFF4F9FF,
+0xFF040C30,
+0xFF071846,
+0xFF2A3C62,
+0xFFF7FFFF,
+0xFFFCFFFF,
+0xFFFBFEFF,
+0xFFFCFFFF,
+0xFFFAFEFF,
+0xFFFCFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFBFCFE,
+0xFFCCCFDE,
+0xFF000833,
+0xFF020D3A,
+0xFF8189A0,
+0xFFF8FFFF,
+0xFFF7FEFF,
+0xFFA8B0C3,
+0xFF000C31,
+0xFF091A46,
+0xFF021438,
+0xFF000A2C,
+0xFF040A2C,
+0xFF06092A,
+0xFF06092C,
+0xFF06092C,
+0xFF08082A,
+0xFF080928,
+0xFF080928,
+0xFF080928,
+0xFF06092C,
+0xFF050B2D,
+0xFF000A28,
+0xFF000E2A,
+0xFF001535,
+0xFF05193E,
+0xFF05123E,
+0xFF63698B,
+0xFFFCFFFF,
+0xFFFBFEFF,
+0xFFF3FDFF,
+0xFF18284C,
+0xFF031344,
+0xFF0E1A40,
+0xFFF7F7FF,
+0xFFFFFFF8,
+0xFFFFFFFA,
+0xFFFCFFFD,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFEFFFF,
+0xFFFFFEFF,
+0xFFFEFEFF,
+0xFFF9FFFF,
+0xFFF4FFFF,
+0xFF53617B,
+0xFF060F3A,
+0xFF050A32,
+0xFFF0F3FF,
+0xFFFEFFFF,
+0xFFFEFEFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFEFEFF,
+0xFFF6FCFF,
+0xFF041131,
+0xFF06153E,
+0xFF233052,
+0xFFFBFFFF,
+0xFFFFFFFF,
+0xFFFCFEFD,
+0xFFFCFFFF,
+0xFFFBFFFF,
+0xFFD7E1EB,
+0xFF00082C,
+0xFF041644,
+0xFF081740,
+0xFF000A30,
+0xFF050831,
+0xFF06082F,
+0xFF05092E,
+0xFF040A2C,
+0xFF010C2A,
+0xFF000D28,
+0xFF000D27,
+0xFF000E25,
+0xFF020E26,
+0xFF000722,
+0xFF00092A,
+0xFF00072C,
+0xFF0A1240,
+0xFF0C1647,
+0xFF0C1649,
+0xFF2D375A,
+0xFFF8FFFF,
+0xFFF8FFFF,
+0xFF666E92,
+0xFF0B1240,
+0xFF050A32,
+0xFFD2D6F3,
+0xFFFEFCFF,
+0xFFFFFCFF,
+0xFFFFFDFF,
+0xFFFFFDFF,
+0xFFFCFFFF,
+0xFFFBFFFF,
+0xFFF9FFFF,
+0xFFFCFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFDFFFA,
+0xFFF9FFFF,
+0xFF010B2F,
+0xFF0A1743,
+0xFF3D4665,
+0xFFFBFDFF,
+0xFFFFFDFF,
+0xFFFFFEFF,
+0xFFFEFFFF,
+0xFFFCFFFF,
+0xFFFEFFFD,
+0xFFFEFFFB,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFB,
+0xFFFEFFFB,
+0xFFFFFEFF,
+0xFFF7FFFF,
+0xFFE6FFFF,
+0xFF72B1D0,
+0xFF3EA0D1,
+0xFF4DA1CD,
+0xFFEAFFFF,
+0xFFFFFFFF,
+0xFFFEFEFE,
+0xFFFEFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFDFF,
+0xFFF8FFFF,
+0xFFE5FFFF,
+0xFF6AA9C8,
+0xFF3E9EC8,
+0xFF62B4D9,
+0xFFEDFFFF,
+0xFFFFFEFF,
+0xFFFFFEFD,
+0xFFFFFEFD,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFF0FFFF,
+0xFF9EE0FA,
+0xFF4599BB,
+0xFF4A92BA,
+0xFFCDFFFF,
+0xFFF0FFFF,
+0xFFFBFFFF,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFBFFFF,
+0xFFCDEDFA,
+0xFF419CC8,
+0xFF33A5DB,
+0xFF40A2D1,
+0xFF3C94C2,
+0xFF3E94C3,
+0xFF4195C3,
+0xFF4297C0,
+0xFF4297BE,
+0xFF4497C3,
+0xFF4397C5,
+0xFF4099C1,
+0xFF4199BF,
+0xFF4497BF,
+0xFF4597BF,
+0xFF4698C0,
+0xFF3D96C0,
+0xFF3AA1CC,
+0xFF3DA0C7,
+0xFF4392B1,
+0xFFB8ECFF,
+0xFFF1FFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFD,
+0xFFFFFFFA,
+0xFFFFFFFB,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFDFDFF,
+0xFFFFFFFF,
+0xFFFEFFFA,
+0xFFFDFFFA,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFBFCFF,
+0xFF000323,
+0xFF02143C,
+0xFF3A4D6E,
+0xFFF5FFFF,
+0xFFF9FEFA,
+0xFFFFFFFB,
+0xFFFFFFFD,
+0xFFFEFFFF,
+0xFFFBFFFF,
+0xFFFBFFFF,
+0xFFFCFFFF,
+0xFFFCFAFD,
+0xFFFFFDFF,
+0xFFFFFEFF,
+0xFFFDFBFC,
+0xFFFEFFFF,
+0xFFF9FFFF,
+0xFFA5B3D0,
+0xFF000A2F,
+0xFF081035,
+0xFFB4B8D3,
+0xFFFFFCFF,
+0xFFFFFEFD,
+0xFFFEFEFE,
+0xFFFBFFFF,
+0xFF7F88A7,
+0xFF051139,
+0xFF000529,
+0xFFCCD2EA,
+0xFFFCFFFF,
+0xFFFDFDFB,
+0xFFFEFFFF,
+0xFFFEFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFBFFFE,
+0xFFFCFFFF,
+0xFFFFFFFB,
+0xFFFDFCFF,
+0xFFA7ACCA,
+0xFF000932,
+0xFF040D34,
+0xFFA2A9C6,
+0xFFFCFEFF,
+0xFFFAFCFF,
+0xFF444D6A,
+0xFF071437,
+0xFF000427,
+0xFFF1F8FF,
+0xFFF9FFFF,
+0xFFFBFFFF,
+0xFFFBFFFF,
+0xFFFCFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFDFE,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFBFBF9,
+0xFFFEFFFF,
+0xFFFBFFFF,
+0xFFB2B9CC,
+0xFF000630,
+0xFF040933,
+0xFFC6C9DC,
+0xFFFEFFFF,
+0xFFFDFDFD,
+0xFFFBFDFF,
+0xFF454E77,
+0xFF071345,
+0xFF00042A,
+0xFFF8FDFF,
+0xFFFBFFFF,
+0xFFFEFFF8,
+0xFFFFFFF8,
+0xFFFEFFFA,
+0xFFFCFFFA,
+0xFFFBFFFD,
+0xFFFBFFFF,
+0xFFFBFFFF,
+0xFFF9FEFF,
+0xFF030E2E,
+0xFF001240,
+0xFF25395E,
+0xFFF8FFFF,
+0xFFFEFFFF,
+0xFFFCFCFF,
+0xFFFEFEFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFEFE,
+0xFFFEFEFE,
+0xFFFEFFFF,
+0xFFC9CEE1,
+0xFF000835,
+0xFF03103D,
+0xFF878DA7,
+0xFFF7FAFF,
+0xFFFCFEFF,
+0xFFA7AEC0,
+0xFF000A31,
+0xFF061B48,
+0xFF051B44,
+0xFF011339,
+0xFF051137,
+0xFF071037,
+0xFF051139,
+0xFF051139,
+0xFF071039,
+0xFF080F39,
+0xFF080F3D,
+0xFF07103B,
+0xFF060F36,
+0xFF050F33,
+0xFF061336,
+0xFF031134,
+0xFF000D30,
+0xFF05173D,
+0xFF00052D,
+0xFF565D7A,
+0xFFFCFFFF,
+0xFFFBFFFF,
+0xFFF0FFFF,
+0xFF122546,
+0xFF011641,
+0xFF07173B,
+0xFFFCFEFF,
+0xFFFFFFFB,
+0xFFFCFFFA,
+0xFFFBFFFA,
+0xFFFBFFFB,
+0xFFFBFFFD,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFBFFFF,
+0xFFF5FFFF,
+0xFF4E5C76,
+0xFF091142,
+0xFF020635,
+0xFFEEF0FF,
+0xFFFBFCFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFCFFFF,
+0xFFF5FEFF,
+0xFF04122D,
+0xFF06153E,
+0xFF223152,
+0xFFF9FFFF,
+0xFFFEFFFB,
+0xFFFEFFFA,
+0xFFF8FDF7,
+0xFFFBFFFD,
+0xFFC3CDD7,
+0xFF000D31,
+0xFF0B1D4D,
+0xFF061441,
+0xFF02113A,
+0xFF041036,
+0xFF041036,
+0xFF041038,
+0xFF041038,
+0xFF04103A,
+0xFF03103A,
+0xFF02113A,
+0xFF02113A,
+0xFF05173D,
+0xFF000C32,
+0xFF07193D,
+0xFF021438,
+0xFF000D31,
+0xFF020F39,
+0xFF020D3A,
+0xFF192241,
+0xFFF6FFFF,
+0xFFF8FFFF,
+0xFF646E92,
+0xFF020C3F,
+0xFF000833,
+0xFFD9E0FC,
+0xFFFCFFFF,
+0xFFFFFFFB,
+0xFFFFFEFB,
+0xFFFFFFFD,
+0xFFFCFFFF,
+0xFFFBFFFF,
+0xFFFBFFFF,
+0xFFFCFFFF,
+0xFFFFFEFF,
+0xFFFFFEFD,
+0xFFFEFCFD,
+0xFFFFFFFD,
+0xFFFEFFFA,
+0xFFF6FDFF,
+0xFF091337,
+0xFF05123F,
+0xFF3F4869,
+0xFFF8FDFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFEFFFF,
+0xFFFCFFFF,
+0xFFFEFFFF,
+0xFFFEFFFD,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFB,
+0xFFFEFFFB,
+0xFFFFFEFF,
+0xFFF7FFFF,
+0xFFE6FFFF,
+0xFF72B1D0,
+0xFF3EA0D1,
+0xFF4DA1CD,
+0xFFEAFFFF,
+0xFFFFFFFF,
+0xFFFEFEFE,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFDFF,
+0xFFF9FFFF,
+0xFFE3FFFF,
+0xFF69AAC6,
+0xFF3E9DC9,
+0xFF62B4DA,
+0xFFEDFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFDFF,
+0xFFF2FFFF,
+0xFF9FDFFA,
+0xFF4698BD,
+0xFF4993BA,
+0xFFCBFFFF,
+0xFFF0FFFF,
+0xFFFBFFFF,
+0xFFFCFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFD9F5FF,
+0xFF3F96C1,
+0xFF37A5DA,
+0xFF5EBBE7,
+0xFF75C8F0,
+0xFF77C4EE,
+0xFF7CC7EE,
+0xFF76C5E6,
+0xFF76C5E6,
+0xFF7AC2EA,
+0xFF7AC1EB,
+0xFF78C3EB,
+0xFF79C5E9,
+0xFF7DC3E5,
+0xFF7EC2E5,
+0xFF78C0E6,
+0xFF77C2E9,
+0xFF79C9EC,
+0xFF77C2E1,
+0xFF7DBBD4,
+0xFFCFF9FF,
+0xFFF0FFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFD,
+0xFFFFFFFA,
+0xFFFFFFFB,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFEFFFA,
+0xFFFAFDF6,
+0xFFFCFFFF,
+0xFFFBFEFF,
+0xFFFBFDFF,
+0xFF000527,
+0xFF061742,
+0xFF25375B,
+0xFFF7FFFF,
+0xFFFDFFFC,
+0xFFFFFEFB,
+0xFFFFFEFB,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFAFEFD,
+0xFFFCFFFF,
+0xFFFFFEFF,
+0xFFFEF9FD,
+0xFFFFFEFD,
+0xFFFFFFFB,
+0xFFFAFFFB,
+0xFFF4FDFF,
+0xFF9AA7C7,
+0xFF000C36,
+0xFF030D31,
+0xFFB4BAD4,
+0xFFFEFEFF,
+0xFFFFFFFD,
+0xFFFDFFFE,
+0xFFFBFFFF,
+0xFF767F9E,
+0xFF060F38,
+0xFF00082D,
+0xFFD0D4ED,
+0xFFFEFEFF,
+0xFFFFFFFD,
+0xFFFCFEFD,
+0xFFFFFFFF,
+0xFFFEFCFD,
+0xFFFFFDFE,
+0xFFFCFFFF,
+0xFFFBFFFC,
+0xFFFFFDFA,
+0xFFFFFEFF,
+0xFF9DA2C2,
+0xFF020B36,
+0xFF040D34,
+0xFFA2A9C6,
+0xFFFBFDFF,
+0xFFFCFEFF,
+0xFF4F5875,
+0xFF081538,
+0xFF000428,
+0xFFE6EDFF,
+0xFFF9FFFF,
+0xFFFBFFFD,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFDFFFE,
+0xFFFEFEFE,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFCFF,
+0xFFFFFEFF,
+0xFFFEFEFC,
+0xFFF7FCF8,
+0xFFF9FFFF,
+0xFF9DA5B8,
+0xFF050E39,
+0xFF000733,
+0xFFC3CADD,
+0xFFFBFFFF,
+0xFFFCFEFD,
+0xFFFCFEFF,
+0xFF444D74,
+0xFF050F40,
+0xFF02062B,
+0xFFFAFCFF,
+0xFFFCFFFF,
+0xFFFEFFFA,
+0xFFFFFFFA,
+0xFFFFFFFA,
+0xFFFEFFF8,
+0xFFFCFFFB,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFF9FEFF,
+0xFF030C2B,
+0xFF011341,
+0xFF263961,
+0xFFF9FFFF,
+0xFFFEFEFF,
+0xFFFFFEFF,
+0xFFFEFDFF,
+0xFFFFFFFF,
+0xFFFDFDFD,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFEFDFF,
+0xFFCDD2E6,
+0xFF000834,
+0xFF04113E,
+0xFF7D849E,
+0xFFFBFFFF,
+0xFFFCFFFF,
+0xFFAAB0C0,
+0xFF000A31,
+0xFF041646,
+0xFF3D507A,
+0xFF69799D,
+0xFF6A7595,
+0xFF6B7493,
+0xFF6A7593,
+0xFF687595,
+0xFF6B7495,
+0xFF6B7397,
+0xFF6A739A,
+0xFF6A7498,
+0xFF6C7797,
+0xFF6A7591,
+0xFF6C7691,
+0xFF69728F,
+0xFF6E7C99,
+0xFF687595,
+0xFF697291,
+0xFF9A9EB7,
+0xFFFEFEFF,
+0xFFFCFFFF,
+0xFFF3FFFF,
+0xFF112444,
+0xFF001640,
+0xFF02143A,
+0xFFF9FFFF,
+0xFFFCFCFC,
+0xFFFCFFFD,
+0xFFFBFFFB,
+0xFFFBFFFB,
+0xFFFCFFFB,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFCFFFF,
+0xFFF7FFFF,
+0xFF505C74,
+0xFF0A1241,
+0xFF000130,
+0xFFF1F3FF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFEFEFC,
+0xFFFEFFFF,
+0xFFFBFFFF,
+0xFFF5FEFF,
+0xFF04122D,
+0xFF04163E,
+0xFF223152,
+0xFFFBFFFF,
+0xFFFFFFFB,
+0xFFFCFDF8,
+0xFFFEFFFB,
+0xFFFCFFFD,
+0xFFD8E0EB,
+0xFF000B32,
+0xFF021245,
+0xFF2B3966,
+0xFF707EA5,
+0xFF697696,
+0xFF697792,
+0xFF6C7594,
+0xFF6C7596,
+0xFF6C7498,
+0xFF6C7499,
+0xFF6B749B,
+0xFF69759B,
+0xFF687598,
+0xFF697897,
+0xFF667793,
+0xFF64758F,
+0xFF697993,
+0xFF6B7996,
+0xFF646C90,
+0xFF7E849E,
+0xFFFBFFFF,
+0xFFF9FFFF,
+0xFF6D779B,
+0xFF000C3C,
+0xFF000731,
+0xFFD3DFF9,
+0xFFFBFFFF,
+0xFFFFFFFA,
+0xFFFFFFFA,
+0xFFFFFFFB,
+0xFFFEFFFF,
+0xFFFCFFFF,
+0xFFFBFFFF,
+0xFFFEFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFEFEFC,
+0xFFFDFFFC,
+0xFFF9FFFF,
+0xFF020E36,
+0xFF000B3B,
+0xFF444C70,
+0xFFF8FDFF,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFEFFFF,
+0xFFFCFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFB,
+0xFFFEFFFB,
+0xFFFFFEFF,
+0xFFF7FFFF,
+0xFFE6FFFF,
+0xFF72B1D0,
+0xFF3EA0D1,
+0xFF4DA1CD,
+0xFFEAFFFF,
+0xFFFFFFFF,
+0xFFFEFEFE,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFF7FFFF,
+0xFFE1FFFF,
+0xFF68AACA,
+0xFF3E9CD0,
+0xFF62B3E0,
+0xFFEBFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFCFFFD,
+0xFFFBFFFD,
+0xFFFFFFFF,
+0xFFF0FFFF,
+0xFF9FDFFB,
+0xFF4898BD,
+0xFF4A92B8,
+0xFFCDFFFF,
+0xFFF4FFFF,
+0xFFFFFEFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFEFF,
+0xFFE4FEFF,
+0xFF3A91BE,
+0xFF38A1D1,
+0xFF8CD7F4,
+0xFFD6FFFF,
+0xFFE7FFFF,
+0xFFE8FFFF,
+0xFFE7FFFF,
+0xFFE9FFFF,
+0xFFEDFFFF,
+0xFFF0FFFF,
+0xFFEEFFFF,
+0xFFEEFFFF,
+0xFFEDFFFF,
+0xFFEDFFFF,
+0xFFEDFFFF,
+0xFFEEFFFF,
+0xFFEFFFFF,
+0xFFF1FFFF,
+0xFFF0FFFF,
+0xFFF0FFFF,
+0xFFFEFFFF,
+0xFFFFFDFE,
+0xFFFFFEFF,
+0xFFFEFFFF,
+0xFFFFFFFD,
+0xFFFFFFFA,
+0xFFFFFFFB,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFEFDFF,
+0xFFFFFFFF,
+0xFFFEFFFA,
+0xFFFEFFFA,
+0xFFFCFFFF,
+0xFFFAFDFF,
+0xFFF7F9FF,
+0xFF1E2446,
+0xFF061340,
+0xFF09173E,
+0xFFF6FCFF,
+0xFFFFFEFF,
+0xFFFFFCFD,
+0xFFFFFCFD,
+0xFFFDFCFA,
+0xFFFBFDFA,
+0xFFFCFFFD,
+0xFFFAFEFD,
+0xFFFFFEFF,
+0xFFFFFDFF,
+0xFFFFFBFA,
+0xFFFFFEFA,
+0xFFFCFFFB,
+0xFFF8FFFF,
+0xFF637293,
+0xFF04133E,
+0xFF00082E,
+0xFFB5BCD6,
+0xFFFCFFFF,
+0xFFFEFFFD,
+0xFFFCFFFF,
+0xFFF7FEFF,
+0xFF7A83A2,
+0xFF030C35,
+0xFF070C32,
+0xFFC1C5E0,
+0xFFFEFEFF,
+0xFFFFFFFD,
+0xFFFCFEFD,
+0xFFFEFFFF,
+0xFFFFFDFE,
+0xFFFFFEFF,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFFFEFD,
+0xFFFFFDFF,
+0xFF8589AE,
+0xFF070F3D,
+0xFF010A31,
+0xFFA8AFCB,
+0xFFFEFEFF,
+0xFFFCFFFF,
+0xFF79839E,
+0xFF000C2F,
+0xFF050D34,
+0xFFAEB3D1,
+0xFFFBFEFF,
+0xFFFEFEFC,
+0xFFFEFEFC,
+0xFFFEFEFC,
+0xFFFFFEFC,
+0xFFFFFDFE,
+0xFFFFFDFF,
+0xFFFFFDFF,
+0xFFFFFEFF,
+0xFFFCFAFD,
+0xFFFEFFFD,
+0xFFFBFFFF,
+0xFFF6FEFF,
+0xFF5B6580,
+0xFF071240,
+0xFF000936,
+0xFFC0CBDF,
+0xFFF6FFFF,
+0xFFFCFFFB,
+0xFFFBFFFF,
+0xFF465171,
+0xFF060F38,
+0xFF000324,
+0xFFFBFCFF,
+0xFFFFFDFF,
+0xFFFFFEFF,
+0xFFFFFDFF,
+0xFFFFFEFD,
+0xFFFFFFFA,
+0xFFFFFFFB,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFAFCFF,
+0xFF050C28,
+0xFF061745,
+0xFF283A62,
+0xFFFAFDFF,
+0xFFFEFEFC,
+0xFFFFFFFB,
+0xFFFCFDF8,
+0xFFFFFEFC,
+0xFFFFFEFC,
+0xFFFFFFFA,
+0xFFFFFFFB,
+0xFFFDFAFF,
+0xFFCDCFE4,
+0xFF000734,
+0xFF01103B,
+0xFF838EA2,
+0xFFF4FDFF,
+0xFFF9FEFF,
+0xFFCCD2E0,
+0xFF020E36,
+0xFF010F40,
+0xFF6A769C,
+0xFFF7FEFF,
+0xFFFCFEFF,
+0xFFFEFEFF,
+0xFFFBFFFF,
+0xFFFBFFFF,
+0xFFFBFFFF,
+0xFFFBFFFF,
+0xFFF8FFFF,
+0xFFF8FFFF,
+0xFFF5FDFF,
+0xFFF9FFFF,
+0xFFFCFFFF,
+0xFFFCFCFF,
+0xFFF9FCFF,
+0xFFFAFDFF,
+0xFFFCFDFF,
+0xFFFFFDFF,
+0xFFFFFDFE,
+0xFFFFFFFF,
+0xFFF6FFFF,
+0xFF162743,
+0xFF031847,
+0xFF0B1C47,
+0xFFF3F9FF,
+0xFFFEFFFF,
+0xFFFEFEFF,
+0xFFFEFFFF,
+0xFFFEFFFD,
+0xFFFFFFFA,
+0xFFFFFFFA,
+0xFFFFFDFD,
+0xFFFFFDFF,
+0xFFFFFDFF,
+0xFFF7FFFF,
+0xFF545F71,
+0xFF081037,
+0xFF01062E,
+0xFFF1F4FF,
+0xFFFEFFFF,
+0xFFFDFCFF,
+0xFFFEFDFF,
+0xFFFEFFFF,
+0xFFFBFFFF,
+0xFFF5FDFF,
+0xFF041133,
+0xFF061540,
+0xFF233053,
+0xFFFCFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFDFDFD,
+0xFFFBFFFF,
+0xFF010937,
+0xFF040F45,
+0xFF344068,
+0xFFF5FEFF,
+0xFFF9FEFF,
+0xFFFBFFFF,
+0xFFFEFEFF,
+0xFFFEFEFF,
+0xFFFFFDFF,
+0xFFFFFDFF,
+0xFFFFFCFF,
+0xFFFEFDFF,
+0xFFFEFDFF,
+0xFFFCFEFF,
+0xFFF9FDFF,
+0xFFF9FFFF,
+0xFFF8FEFF,
+0xFFF7FDFF,
+0xFFF9FEFF,
+0xFFFBFCFF,
+0xFFFFFEFF,
+0xFFFEFCFF,
+0xFF989EBE,
+0xFF030F37,
+0xFF000F33,
+0xFF96A4BE,
+0xFFF6FDFF,
+0xFFFEFFFB,
+0xFFFFFEFB,
+0xFFFFFEFD,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFCFFFB,
+0xFFFEFFFB,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFEFFFA,
+0xFFFEFFFD,
+0xFFFAFBFF,
+0xFFE3E8FE,
+0xFF000738,
+0xFF0B174B,
+0xFF40486C,
+0xFFF9FFFF,
+0xFFFFFFFF,
+0xFFFFFFFB,
+0xFFFEFFFD,
+0xFFFCFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFFFFFB,
+0xFFFEFFFB,
+0xFFFFFFFF,
+0xFFF7FFFF,
+0xFFE4FFFF,
+0xFF71B2D2,
+0xFF3CA0D1,
+0xFF4BA2CD,
+0xFFEBFFFF,
+0xFFFFFEFF,
+0xFFFEFEFE,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFF4FFFF,
+0xFFDFFFFF,
+0xFF68AACC,
+0xFF409BD2,
+0xFF64B2E2,
+0xFFEBFFFF,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFCFFFD,
+0xFFFBFFFD,
+0xFFFEFFFF,
+0xFFF0FFFF,
+0xFFA1DEFD,
+0xFF4997BE,
+0xFF4A93B6,
+0xFFCDFFFF,
+0xFFF4FFFF,
+0xFFFFFEFF,
+0xFFFEFFFF,
+0xFFFEFFFD,
+0xFFFFFDFC,
+0xFFEDFFFF,
+0xFF54A6CE,
+0xFF3EA0CD,
+0xFF61ABC6,
+0xFFDCFFFF,
+0xFFF4FFFF,
+0xFFFEFEFC,
+0xFFFBFFFF,
+0xFFFCFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFDFF,
+0xFFFFFDFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFF9FFFF,
+0xFFF7FFFF,
+0xFFF7FFFF,
+0xFFF7FFFF,
+0xFFF4FCFF,
+0xFFFEFFFF,
+0xFFFFFEFB,
+0xFFFFFCFC,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFCFFFF,
+0xFFF7FFFF,
+0xFFEEFFFF,
+0xFFEAFFFF,
+0xFFEBFFFF,
+0xFFF0FFFF,
+0xFFF7FFFF,
+0xFFF8FEFE,
+0xFFFCFFFD,
+0xFFFDFFFA,
+0xFFFCFDFF,
+0xFFFEFEFF,
+0xFFFEFDFF,
+0xFF646786,
+0xFF06113F,
+0xFF000532,
+0xFFC2C7DD,
+0xFFFFFDFF,
+0xFFFFFAFE,
+0xFFFFFBFE,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFEFFFD,
+0xFFFEFFFD,
+0xFFFDFBFE,
+0xFFFFFDFF,
+0xFFFEFCFD,
+0xFFFFFFFF,
+0xFFFCFFFF,
+0xFFF6FEFF,
+0xFF07163D,
+0xFF061846,
+0xFF020E34,
+0xFFB3BBD2,
+0xFFF9FCFF,
+0xFFFFFFFD,
+0xFFFEFFFF,
+0xFFFBFFFF,
+0xFF919AB7,
+0xFF040D34,
+0xFF030B32,
+0xFFA3A8C6,
+0xFFFBFEFF,
+0xFFFEFFFF,
+0xFFFEFFFD,
+0xFFFEFEFC,
+0xFFFFFDFF,
+0xFFFFFCFF,
+0xFFFEFEFE,
+0xFFFEFFFF,
+0xFFFFFEFF,
+0xFFF9F8FF,
+0xFF63688E,
+0xFF020D3B,
+0xFF000B33,
+0xFFA3ADC8,
+0xFFFBFEFF,
+0xFFF9FCFF,
+0xFFC2CADF,
+0xFF000A2D,
+0xFF09123D,
+0xFF474C72,
+0xFFFCFEFF,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFFFFFB,
+0xFFFFFEFD,
+0xFFFFFDFF,
+0xFFFFFCFF,
+0xFFFFFDFF,
+0xFFFFFEFF,
+0xFFFEFEFE,
+0xFFFCFFFD,
+0xFFF7FFFF,
+0xFFF7FFFF,
+0xFF071135,
+0xFF0B154A,
+0xFF000836,
+0xFFC0CDE0,
+0xFFF6FFFF,
+0xFFFCFFFB,
+0xFFF8FDFF,
+0xFF45506E,
+0xFF07133B,
+0xFF000326,
+0xFFFCFCFF,
+0xFFFFFDFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFB,
+0xFFFFFEFB,
+0xFFFFFDFF,
+0xFFFFFEFF,
+0xFFFCFEFF,
+0xFF070E2A,
+0xFF011240,
+0xFF273661,
+0xFFF9FFFF,
+0xFFFDFEF9,
+0xFFFFFFF7,
+0xFFFFFFF8,
+0xFFFFFFFB,
+0xFFFFFFFB,
+0xFFFDFCF7,
+0xFFFFFFFB,
+0xFFFFFEFF,
+0xFFCBCCE1,
+0xFF020E38,
+0xFF000D37,
+0xFF7E8B9C,
+0xFFF8FFFF,
+0xFFF9FFFF,
+0xFFF8FFFF,
+0xFF060F36,
+0xFF071142,
+0xFF0B123C,
+0xFFF8FCFF,
+0xFFFDFDFF,
+0xFFFEFEFC,
+0xFFFDFFFA,
+0xFFFDFFFA,
+0xFFFEFEFF,
+0xFFFDFEFF,
+0xFFFBFFFC,
+0xFFFAFFFC,
+0xFFFBFFFF,
+0xFFF8FDFF,
+0xFFFCFDFF,
+0xFFFEFFFF,
+0xFFB8BAC9,
+0xFFB3B4C8,
+0xFFADACBE,
+0xFFFCF9FF,
+0xFFFFFCFF,
+0xFFFFFEFF,
+0xFFF7FFFF,
+0xFF132440,
+0xFF001443,
+0xFF071843,
+0xFFF9FEFF,
+0xFFFDFCFF,
+0xFFFFFDFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFB,
+0xFFFFFFFA,
+0xFFFFFEFB,
+0xFFFFFDFF,
+0xFFFFFDFF,
+0xFFF9FFFF,
+0xFF535B70,
+0xFF080F39,
+0xFF02072F,
+0xFFF0F3FF,
+0xFFFBFCFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFCFFFF,
+0xFFF5FDFF,
+0xFF041134,
+0xFF061441,
+0xFF232F55,
+0xFFFBFEFF,
+0xFFFFFEFF,
+0xFFFFFDFF,
+0xFFFFFDFF,
+0xFFFFFEFF,
+0xFFFBFDFF,
+0xFF252A52,
+0xFF0C1445,
+0xFF000631,
+0xFFF7FEFF,
+0xFFFCFEFF,
+0xFFFFFFFF,
+0xFFFFFFFB,
+0xFFFFFFFA,
+0xFFFFFDFD,
+0xFFFFFCFF,
+0xFFFFFBFF,
+0xFFFFFCFF,
+0xFFFFFEFF,
+0xFFFDFCFA,
+0xFFFFFFFF,
+0xFFFEFEFF,
+0xFFBABCC9,
+0xFF9497A8,
+0xFF8C8FA0,
+0xFFE2E4F1,
+0xFFFFFBFF,
+0xFFFFFDFF,
+0xFFDBE1FB,
+0xFF000628,
+0xFF09193B,
+0xFF394963,
+0xFFF5FFFF,
+0xFFFBFFFF,
+0xFFFFFFFD,
+0xFFFFFEFD,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFEFFFB,
+0xFFFEFFFB,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFCFFFB,
+0xFFFBFFFF,
+0xFFF9FFFF,
+0xFF8A90B0,
+0xFF010D3F,
+0xFF021041,
+0xFF3F4A68,
+0xFFF8FFFF,
+0xFFFEFFFF,
+0xFFFFFFFA,
+0xFFFEFFFD,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFDFDFF,
+0xFFFFFFFD,
+0xFFFFFFFB,
+0xFFFEFFFA,
+0xFFFDFFFA,
+0xFFFEFFFD,
+0xFFF4FFFF,
+0xFFE4FFFF,
+0xFF6EB0D0,
+0xFF399FD0,
+0xFF4CA5D1,
+0xFFECFFFF,
+0xFFFFFDFD,
+0xFFFFFEFF,
+0xFFFFFDFF,
+0xFFFEFEFE,
+0xFFFEFFFF,
+0xFFFBFFFF,
+0xFFF0FFFF,
+0xFFE2FFFF,
+0xFF67A6C9,
+0xFF459AD1,
+0xFF65AFDE,
+0xFFEBFFFF,
+0xFFFFFFFB,
+0xFFFFFFFB,
+0xFFFDFCF8,
+0xFFFFFFFD,
+0xFFFDFFFC,
+0xFFFEFFFF,
+0xFFEEFFFF,
+0xFFA2DDFF,
+0xFF4D98C0,
+0xFF458EB1,
+0xFFCEFFFF,
+0xFFF0FFFF,
+0xFFFCFFFF,
+0xFFFBFFFF,
+0xFFFBFDFC,
+0xFFFFFCFD,
+0xFFF1FFFF,
+0xFF8ED0F0,
+0xFF3E9AC1,
+0xFF3F97BB,
+0xFFB4F6FF,
+0xFFEDFFFF,
+0xFFFCFEFD,
+0xFFFFFFFF,
+0xFFFAFAFA,
+0xFFFFFFFD,
+0xFFFCFCFC,
+0xFFFAFDFF,
+0xFFFEFEFF,
+0xFFFFFCFB,
+0xFFFEFFFF,
+0xFFEBFFFF,
+0xFFD8FFFF,
+0xFFA9E0FE,
+0xFFACDEF7,
+0xFFD4ECF8,
+0xFFFBFFFF,
+0xFFFFFDFE,
+0xFFFFFDFD,
+0xFFFDFDFF,
+0xFFFBFFFF,
+0xFFF7FFFF,
+0xFFE5FFFF,
+0xFF7FC0DC,
+0xFF4597BC,
+0xFF4496BC,
+0xFF7ABDDA,
+0xFFE2FFFF,
+0xFFF2FFFF,
+0xFFF9FFFF,
+0xFFFDFFFE,
+0xFFFFFFFF,
+0xFFFFFDFF,
+0xFFFEF9FF,
+0xFFD7D5EA,
+0xFF000837,
+0xFF030F41,
+0xFF2C3350,
+0xFFFBFEFF,
+0xFFFFFEFF,
+0xFFFFFCFF,
+0xFFFFFDFF,
+0xFFFFFDFF,
+0xFFFFFEFF,
+0xFFFEFDFB,
+0xFFFFFFFB,
+0xFFFFFFFD,
+0xFFFDFDFD,
+0xFFFDFEFF,
+0xFFFDFDFF,
+0xFF99A0BA,
+0xFF000E3D,
+0xFF02194B,
+0xFF021033,
+0xFFB1B9CC,
+0xFFFEFEFF,
+0xFFFFFEFB,
+0xFFFAF8FD,
+0xFFFEFDFF,
+0xFFC2C8E2,
+0xFF01092D,
+0xFF020B32,
+0xFF616A89,
+0xFFF7FFFF,
+0xFFFCFFFF,
+0xFFFEFEFC,
+0xFFFFFEFD,
+0xFFFFFDFF,
+0xFFFFFCFF,
+0xFFFFFEFD,
+0xFFFEFDFB,
+0xFFFBFCFF,
+0xFFF9FEFF,
+0xFF08143C,
+0xFF0A1849,
+0xFF000D39,
+0xFF9EA9C7,
+0xFFFBFFFF,
+0xFFFCFFFF,
+0xFFF6FCFF,
+0xFF0C1631,
+0xFF05123F,
+0xFF000835,
+0xFFE1E3FA,
+0xFFFCFBFF,
+0xFFFFFDFF,
+0xFFFFFEFF,
+0xFFFFFBFF,
+0xFFFFFBFF,
+0xFFFFFBFF,
+0xFFFFFCFF,
+0xFFFFFEFF,
+0xFFFCFCFA,
+0xFFFCFFFD,
+0xFFF8FFFF,
+0xFF848DAA,
+0xFF030E3C,
+0xFF0D1752,
+0xFF000536,
+0xFFC1C9DC,
+0xFFF6FEFF,
+0xFFFCFFFF,
+0xFFF8FFFF,
+0xFF475476,
+0xFF05123E,
+0xFF00032B,
+0xFFFBFCFF,
+0xFFFEFEFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFFFFFD,
+0xFFFFFEFB,
+0xFFFFFEFB,
+0xFFFFFFFF,
+0xFFFBFFFF,
+0xFFF8FFFF,
+0xFF030E2A,
+0xFF011144,
+0xFF2B3A65,
+0xFFF5FDFF,
+0xFFFEFFFA,
+0xFFFFFEF9,
+0xFFFFFEFA,
+0xFFFEFDFB,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFCDCEE2,
+0xFF00042F,
+0xFF06133D,
+0xFF848C9F,
+0xFFF6FFFF,
+0xFFF9FFFF,
+0xFFF6FFFF,
+0xFF5A6082,
+0xFF050C3A,
+0xFF030A38,
+0xFF989EC2,
+0xFFF9FFFF,
+0xFFFBFFFF,
+0xFFFBFFFB,
+0xFFF9FEFA,
+0xFFFEFFFF,
+0xFFFFFEFF,
+0xFFFEFEFC,
+0xFFFEFFFA,
+0xFFFBFFFB,
+0xFFF8FFFF,
+0xFFF9FFFF,
+0xFFDCE2F8,
+0xFF000320,
+0xFF000928,
+0xFF131732,
+0xFFFEFBFF,
+0xFFFFFCFF,
+0xFFFEFDFF,
+0xFFF5FFFF,
+0xFF122742,
+0xFF001740,
+0xFF051840,
+0xFFF9FFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFB,
+0xFFFFFFFB,
+0xFFFEFFFF,
+0xFFFBFFFF,
+0xFFF8FFFF,
+0xFF515A79,
+0xFF0B1047,
+0xFF000033,
+0xFFEEF3FF,
+0xFFFCFFFF,
+0xFFFDFDFD,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFCFFFF,
+0xFFF6FEFF,
+0xFF041334,
+0xFF051342,
+0xFF212F56,
+0xFFF8FFFF,
+0xFFFCFFFF,
+0xFFFFFEFF,
+0xFFFEFBFF,
+0xFFFFFDFF,
+0xFFFCFEFF,
+0xFF9197B1,
+0xFF020A2F,
+0xFF050D3E,
+0xFF60658F,
+0xFFFBFEFF,
+0xFFFEFFFF,
+0xFFFCFDF5,
+0xFFFFFFF8,
+0xFFFFFEFD,
+0xFFFFFAFE,
+0xFFFFFBFF,
+0xFFFFFDFF,
+0xFFFFFEF9,
+0xFFFFFFFB,
+0xFFFEFEFF,
+0xFFF9FAFF,
+0xFF030627,
+0xFF04082B,
+0xFF00031B,
+0xFFF9FFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFF8FFFF,
+0xFF222D4D,
+0xFF051338,
+0xFF000C2D,
+0xFFCDDAED,
+0xFFF7FFFF,
+0xFFFCFFFF,
+0xFFFEFFFA,
+0xFFFFFFFD,
+0xFFFCFAFB,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFF9FBFA,
+0xFFFBFFFF,
+0xFFF8FFFD,
+0xFFF3FFFF,
+0xFFF4FFFF,
+0xFF07143E,
+0xFF081643,
+0xFF021138,
+0xFF404F66,
+0xFFF7FFFF,
+0xFFFBFFFF,
+0xFFFEFFFD,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFDFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFD,
+0xFFFFFFFB,
+0xFFFFFFFB,
+0xFFFEFFFD,
+0xFFFAFCF9,
+0xFFF5FFFF,
+0xFFE3FFFF,
+0xFF73B5D7,
+0xFF399FD0,
+0xFF4BA4D0,
+0xFFEBFFFF,
+0xFFFFFBFC,
+0xFFFFFAFF,
+0xFFFFFDFF,
+0xFFFFFEFF,
+0xFFFCFEFD,
+0xFFFCFFFF,
+0xFFF2FFFF,
+0xFFE2FFFF,
+0xFF69A8CB,
+0xFF459AD0,
+0xFF68B2DF,
+0xFFE9FFFF,
+0xFFFEFFFB,
+0xFFFFFEFA,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFF9FDFE,
+0xFFEDFFFF,
+0xFFA1DDFF,
+0xFF4693BD,
+0xFF4A93B6,
+0xFFCEFFFF,
+0xFFEEFFFF,
+0xFFF8FEFC,
+0xFFFBFFFF,
+0xFFFEFFFF,
+0xFFFFFBFB,
+0xFFF8FFFF,
+0xFFD9FFFF,
+0xFF4994B4,
+0xFF449FCC,
+0xFF53A2CB,
+0xFFDEFFFF,
+0xFFF0FFFF,
+0xFFF9FFFF,
+0xFFFFFFFF,
+0xFFFCFCFA,
+0xFFFEFFFF,
+0xFFFBFFFF,
+0xFFF9FEFF,
+0xFFF9FDFF,
+0xFFF2FFFF,
+0xFFDDFFFF,
+0xFF69ABCB,
+0xFF4290B7,
+0xFF4486A8,
+0xFFD8F4FF,
+0xFFF8FDFF,
+0xFFFFFEFF,
+0xFFFFFCFD,
+0xFFFFFFFF,
+0xFFF4FFFF,
+0xFFEAFFFF,
+0xFF75ABC3,
+0xFF3E99C5,
+0xFF38A7DC,
+0xFF37A6DD,
+0xFF3D9CC8,
+0xFF70AAC2,
+0xFFE7FFFF,
+0xFFF2FFFF,
+0xFFFCFDFF,
+0xFFFDFCFF,
+0xFFFFFEFF,
+0xFFFFFDFF,
+0xFFFDFBFF,
+0xFF2E335B,
+0xFF0D1846,
+0xFF01092D,
+0xFF848CA3,
+0xFFFBFEFF,
+0xFFFCFFFF,
+0xFFFFFEFF,
+0xFFFBFBFD,
+0xFFFFFEFC,
+0xFFFDFCFA,
+0xFFFFFFFB,
+0xFFFDFFFE,
+0xFFFCFFFF,
+0xFFFCFEFF,
+0xFFEBEDFF,
+0xFF030B30,
+0xFF03194B,
+0xFF041B4D,
+0xFF00092C,
+0xFFB7BED0,
+0xFFFFFFFF,
+0xFFFFFDFC,
+0xFFFFFDFF,
+0xFFFBF9FF,
+0xFFF8FDFF,
+0xFF010A29,
+0xFF0E1A42,
+0xFF010E31,
+0xFFF5FFFF,
+0xFFF7FEFF,
+0xFFFEFEFF,
+0xFFFFFDFF,
+0xFFFBFAFF,
+0xFFFFFEFF,
+0xFFFDFBFC,
+0xFFFFFEFF,
+0xFFFBFEFF,
+0xFFA0A7C3,
+0xFF000B38,
+0xFF021245,
+0xFF000B36,
+0xFFA8B3D1,
+0xFFF7FEFF,
+0xFFF9FDFC,
+0xFFFBFFFF,
+0xFF8E95A8,
+0xFF010E3A,
+0xFF091643,
+0xFF171E3B,
+0xFFF5FAFF,
+0xFFFCFEFF,
+0xFFFDFEFF,
+0xFFFFFEFF,
+0xFFFFFDFF,
+0xFFFFFDFF,
+0xFFFFFDFF,
+0xFFFEFEFF,
+0xFFFCFFFF,
+0xFFF8FFFF,
+0xFFDCE5F4,
+0xFF050F33,
+0xFF091346,
+0xFF07124A,
+0xFF040F3D,
+0xFFC6CFE0,
+0xFFFBFFFF,
+0xFFFBFCFE,
+0xFFF9FFFF,
+0xFF404E71,
+0xFF04113D,
+0xFF00032B,
+0xFFFBFCFF,
+0xFFFEFEFF,
+0xFFFEFFFF,
+0xFFFCFFFD,
+0xFFFEFFFD,
+0xFFFFFDFB,
+0xFFFFFDFB,
+0xFFFEFFFF,
+0xFFF9FFFF,
+0xFFF6FFFF,
+0xFF000C2C,
+0xFF071448,
+0xFF2D3A67,
+0xFFF8FFFF,
+0xFFFAFCF7,
+0xFFFFFDFA,
+0xFFFFFEFB,
+0xFFFFFFFD,
+0xFFFDFFFE,
+0xFFFDFDFD,
+0xFFFEFEFF,
+0xFFFFFDFF,
+0xFFCECFE3,
+0xFF000833,
+0xFF000C36,
+0xFF83899F,
+0xFFF7FEFF,
+0xFFF9FFFF,
+0xFFF8FFFF,
+0xFFE2E8FF,
+0xFF01062C,
+0xFF111545,
+0xFF000431,
+0xFFE3EBFF,
+0xFFF7FFFF,
+0xFFF9FFFF,
+0xFFFBFFFF,
+0xFFFCFFFF,
+0xFFFBFCFF,
+0xFFFFFFFD,
+0xFFFAFCF7,
+0xFFF6FFFA,
+0xFFF7FFFF,
+0xFFF6FDFF,
+0xFF232B4F,
+0xFF08143A,
+0xFF00072A,
+0xFFADB2CF,
+0xFFFEFDFF,
+0xFFFFFCFF,
+0xFFFFFEFF,
+0xFFF5FFFF,
+0xFF0D223D,
+0xFF001840,
+0xFF04183D,
+0xFFF8FEFF,
+0xFFFBFAFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFFFFFB,
+0xFFFCFFFD,
+0xFFF9FFFF,
+0xFFF7FFFF,
+0xFF51597D,
+0xFF070C46,
+0xFF02053A,
+0xFFF0F5FF,
+0xFFFCFFFF,
+0xFFFEFEFC,
+0xFFFFFFFD,
+0xFFFEFDFB,
+0xFFFEFFFF,
+0xFFF6FEFF,
+0xFF000D2F,
+0xFF071546,
+0xFF202D57,
+0xFFF7FFFF,
+0xFFF7FDF9,
+0xFFFCFCFE,
+0xFFFFFDFF,
+0xFFFFFEFF,
+0xFFFAFAFF,
+0xFFF9FFFF,
+0xFF040B27,
+0xFF111747,
+0xFF000735,
+0xFFB7BDD5,
+0xFFF9FDFF,
+0xFFFCFFFD,
+0xFFFAFDF6,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFEFCFF,
+0xFFFDFFFC,
+0xFFFAFEFF,
+0xFFF9FEFF,
+0xFF4B506E,
+0xFF0C0F3A,
+0xFF060B33,
+0xFF7B829C,
+0xFFF8FFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFF7FDFF,
+0xFFAFB9D4,
+0xFF00092B,
+0xFF071538,
+0xFF13213E,
+0xFFF1FCFF,
+0xFFF9FFFF,
+0xFFFCFFFF,
+0xFFFEFEFE,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFCFFFF,
+0xFFF8FFFF,
+0xFFF7FFFF,
+0xFFF4FFFF,
+0xFF445277,
+0xFF061445,
+0xFF0B194A,
+0xFF04133A,
+0xFF3F4E65,
+0xFFF5FFFF,
+0xFFF9FFFF,
+0xFFFCFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFDFF,
+0xFFFFFDFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFF9FBFA,
+0xFFFCFFFF,
+0xFFF1FFFF,
+0xFFE3FFFF,
+0xFF71B1D5,
+0xFF399DCF,
+0xFF4CA5CF,
+0xFFE4FFFF,
+0xFFFEFFFF,
+0xFFFFFDFF,
+0xFFFDF5FF,
+0xFFFFFDFF,
+0xFFFFFEFD,
+0xFFFFFEFA,
+0xFFF5FFFF,
+0xFFDDFFFF,
+0xFF66ABCC,
+0xFF419DD0,
+0xFF60B1DE,
+0xFFE6FFFF,
+0xFFFAFFFF,
+0xFFFEFFFF,
+0xFFFDFEFF,
+0xFFFBFFFF,
+0xFFF7FFFF,
+0xFFF8FEFE,
+0xFFEDFFFF,
+0xFF9FDFFF,
+0xFF4899C4,
+0xFF4A92BA,
+0xFFCFFFFF,
+0xFFF0FFFF,
+0xFFFCFFFF,
+0xFFF8FEFA,
+0xFFFAFFF9,
+0xFFFFFFFB,
+0xFFFBFFFF,
+0xFFEDFFFF,
+0xFFA9D6F3,
+0xFF4595CA,
+0xFF3F98D0,
+0xFF5DA5CB,
+0xFFD9FFFF,
+0xFFEDFFFF,
+0xFFF5FFFF,
+0xFFFBFFFF,
+0xFFF9FFFD,
+0xFFFAFFFE,
+0xFFF6FFFF,
+0xFFF0FFFF,
+0xFFDEFFFF,
+0xFF69B3DA,
+0xFF3E94C3,
+0xFF4799C8,
+0xFF89C5E7,
+0xFFF0FFFF,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFF0FFFF,
+0xFFC9FBFF,
+0xFF4290B7,
+0xFF41A4DB,
+0xFF35A5E4,
+0xFF32A5E4,
+0xFF3DA5DC,
+0xFF418FB3,
+0xFFC0F3FF,
+0xFFF0FFFF,
+0xFFFCFFFF,
+0xFFFCFDFF,
+0xFFFFFEFF,
+0xFFFCFBFF,
+0xFFFBFDFF,
+0xFFEEF4FF,
+0xFF000322,
+0xFF0B1338,
+0xFF00072B,
+0xFF7C85A4,
+0xFFEEF9FF,
+0xFFF7FFFF,
+0xFFF8FFFD,
+0xFFFAFFF9,
+0xFFFCFFFB,
+0xFFFAFEFF,
+0xFFFBFFFF,
+0xFFF8FDFF,
+0xFFD5DAF8,
+0xFF090E38,
+0xFF0A1445,
+0xFF031749,
+0xFF051A47,
+0xFF020F32,
+0xFFB4B9CF,
+0xFFFDFCFF,
+0xFFFEFAFB,
+0xFFFFFDFF,
+0xFFFEFEFF,
+0xFFF9FFFF,
+0xFF515B74,
+0xFF010D37,
+0xFF05103E,
+0xFF4A5277,
+0xFFF8FEFF,
+0xFFFBFDFF,
+0xFFFCFFFF,
+0xFFF9FFFF,
+0xFFF8FFFF,
+0xFFFBFFFF,
+0xFFF9FCFF,
+0xFFD5DAFA,
+0xFF020A38,
+0xFF0B184D,
+0xFF0A1A4D,
+0xFF000A31,
+0xFFA4AEC9,
+0xFFFAFCFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFAFEFF,
+0xFF20294A,
+0xFF000D37,
+0xFF05133A,
+0xFF21304F,
+0xFFEFFCFF,
+0xFFF5FDFF,
+0xFFFBFFFF,
+0xFFF7FBFA,
+0xFFFDFEFF,
+0xFFFCFFFF,
+0xFFF9FEFF,
+0xFFF8FFFF,
+0xFFD8E3F9,
+0xFF041131,
+0xFF07153C,
+0xFF061340,
+0xFF0A1849,
+0xFF000931,
+0xFFBFC6D6,
+0xFFFAFFFF,
+0xFFFEFFFF,
+0xFFFBFFFF,
+0xFF424F6F,
+0xFF051139,
+0xFF03072C,
+0xFFFAFAFF,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFCFFFF,
+0xFFFEFFFD,
+0xFFFFFEFB,
+0xFFFFFDFD,
+0xFFFEFFFF,
+0xFFF9FFFF,
+0xFFF7FFFF,
+0xFF040E31,
+0xFF051046,
+0xFF2D3866,
+0xFFF5FDFF,
+0xFFFEFFFD,
+0xFFFFFDFD,
+0xFFFFFCFC,
+0xFFFFFFFD,
+0xFFFDFFFE,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFCFF,
+0xFFCDCDE5,
+0xFF030A38,
+0xFF060E3D,
+0xFF8589A6,
+0xFFFBFFFF,
+0xFFF9FFFB,
+0xFFF8FFFC,
+0xFFF8FFFF,
+0xFF757C98,
+0xFF030737,
+0xFF121548,
+0xFF060B31,
+0xFFCED4EC,
+0xFFF5FEFF,
+0xFFF9FFFF,
+0xFFF4F9FC,
+0xFFFBFFFF,
+0xFFFAFFF9,
+0xFFFBFFFD,
+0xFFF9FFFF,
+0xFFF8FFFF,
+0xFF333661,
+0xFF05083B,
+0xFF08113A,
+0xFF394261,
+0xFFF5FAFF,
+0xFFFEFEFF,
+0xFFFFFBFF,
+0xFFFFFEFF,
+0xFFF7FFFF,
+0xFF162840,
+0xFF011740,
+0xFF07193F,
+0xFFFAFDFF,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFEFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFFFFFB,
+0xFFFEFFFD,
+0xFFFBFFFF,
+0xFFF6FEFF,
+0xFF545B78,
+0xFF0A0D42,
+0xFF020435,
+0xFFEFF5FF,
+0xFFFBFFFE,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFDFBFC,
+0xFFFEFEFF,
+0xFFF3F9FF,
+0xFF081236,
+0xFF091549,
+0xFF222F5B,
+0xFFF7FFFF,
+0xFFFBFFFF,
+0xFFFFFFFF,
+0xFFFFFCFD,
+0xFFFFFFFD,
+0xFFFEFFFF,
+0xFFF9FFFF,
+0xFFAFB8C9,
+0xFF00052A,
+0xFF0A113D,
+0xFF000629,
+0xFFA7B1CA,
+0xFFF3FBFF,
+0xFFFBFFFF,
+0xFFFCFFFF,
+0xFFFBFDFC,
+0xFFFCFFFF,
+0xFFFAFFFF,
+0xFFF8FFFF,
+0xFFF5FFFF,
+0xFF4A5573,
+0xFF00082F,
+0xFF0A113B,
+0xFF171D41,
+0xFFF9FEFF,
+0xFFFBFEFF,
+0xFFFEFEFE,
+0xFFFEFFFF,
+0xFFFAFEFF,
+0xFFF7FFFF,
+0xFF45506C,
+0xFF000C2F,
+0xFF050E37,
+0xFF21294E,
+0xFFF2F7FF,
+0xFFFBFEFF,
+0xFFF9FDFF,
+0xFFFEFFFB,
+0xFFF9FEF7,
+0xFFF6FBF5,
+0xFFFBFFFF,
+0xFFF6FDFF,
+0xFFF7FFFF,
+0xFF535C7D,
+0xFF000937,
+0xFF040F47,
+0xFF0B1550,
+0xFF081446,
+0xFF3D476A,
+0xFFF5FDFF,
+0xFFFBFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFEFFFB,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFDFF,
+0xFFFFFAFE,
+0xFFFFFFFF,
+0xFFF8FFFF,
+0xFFD8F2FF,
+0xFFD0FAFF,
+0xFFCAFFFF,
+0xFF61B0DB,
+0xFF3CA2D3,
+0xFF49AAD5,
+0xFFC9FFFF,
+0xFFD1F2FF,
+0xFFDDF0FF,
+0xFFF8FFFF,
+0xFFFFFEFF,
+0xFFFCFFFF,
+0xFFDEF2FB,
+0xFFD5FCFF,
+0xFFC7FFFF,
+0xFF54A9CE,
+0xFF3EA3D7,
+0xFF56B2E1,
+0xFFCCFFFF,
+0xFFD6F7FF,
+0xFFDEF2FD,
+0xFFF4FFFF,
+0xFFF4FFFF,
+0xFFE4F8FF,
+0xFFD7F4FF,
+0xFFD0FFFF,
+0xFF83D5FD,
+0xFF43A0CC,
+0xFF4599C5,
+0xFFB0F6FF,
+0xFFCFFDFF,
+0xFFD7F3FF,
+0xFFF5FFFF,
+0xFFFBFFFD,
+0xFFFCFFFB,
+0xFFFBFFFC,
+0xFFFBFFFF,
+0xFFEAFFFF,
+0xFF7BB6E0,
+0xFF4494C7,
+0xFF49A0CB,
+0xFF4998B9,
+0xFFA4DBF0,
+0xFFE0FFFF,
+0xFFE4FFFF,
+0xFFE6FFFF,
+0xFFE7FFFF,
+0xFFE3FFFF,
+0xFFACDFF4,
+0xFF5B9DBD,
+0xFF499DC9,
+0xFF4498C6,
+0xFF6EAFD5,
+0xFFDFFFFF,
+0xFFF2FFFF,
+0xFFFFFFFB,
+0xFFFCFEFD,
+0xFFFCFFFF,
+0xFFFDFFFE,
+0xFFEEFFFF,
+0xFFB2E9FF,
+0xFF4699C5,
+0xFF40A5DD,
+0xFF37A9E8,
+0xFF33A6E7,
+0xFF3AA4DE,
+0xFF4799C1,
+0xFFABE1F9,
+0xFFF0FFFF,
+0xFFFCFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFCFFFF,
+0xFFFBFFFF,
+0xFFF9FFFF,
+0xFFBAC2D5,
+0xFF000728,
+0xFF091239,
+0xFF000A30,
+0xFF253252,
+0xFFA4B4C4,
+0xFFF4FFFF,
+0xFFF5FFFF,
+0xFFF7FFFF,
+0xFFF8FFFF,
+0xFFDCE2FA,
+0xFF626888,
+0xFF010930,
+0xFF0A1240,
+0xFF000B38,
+0xFF3F507C,
+0xFF03123B,
+0xFF030B2F,
+0xFFB4B8D1,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFEFCFF,
+0xFFFDFEFF,
+0xFFF9FFFF,
+0xFFEFF8FF,
+0xFF020C2F,
+0xFF06113E,
+0xFF020A38,
+0xFF393E66,
+0xFFD5D9F4,
+0xFFF9FFFF,
+0xFFF5FFFF,
+0xFFF1FDFF,
+0xFFF8FFFF,
+0xFF8D93AD,
+0xFF090E36,
+0xFF0A1243,
+0xFF031044,
+0xFF091744,
+0xFF000D30,
+0xFFA3ABC2,
+0xFFFEFEFF,
+0xFFFFFDFF,
+0xFFFCFCFC,
+0xFFFCFFFF,
+0xFFF7FFFF,
+0xFF0C1A37,
+0xFF000F36,
+0xFF06183E,
+0xFF000F2E,
+0xFF8392A9,
+0xFFF0FCFF,
+0xFFF7FFFF,
+0xFFF8FFFF,
+0xFFF7FEFF,
+0xFFE0E8FB,
+0xFF6A748F,
+0xFF00082C,
+0xFF030F37,
+0xFF000E33,
+0xFF45547B,
+0xFF061443,
+0xFF000A32,
+0xFFC7CEDE,
+0xFFFBFFFF,
+0xFFFFFFFF,
+0xFFFBFEFF,
+0xFF49556F,
+0xFF091336,
+0xFF010626,
+0xFFFAFBFF,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFCFFFF,
+0xFFFEFFFF,
+0xFFFFFDFD,
+0xFFFFFDFD,
+0xFFFEFFFF,
+0xFFFBFFFF,
+0xFFF9FEFF,
+0xFF03092D,
+0xFF071144,
+0xFF303964,
+0xFFF6FCFF,
+0xFFFEFFFF,
+0xFFFFFBFC,
+0xFFFFFDFE,
+0xFFFEFFFD,
+0xFFFCFFFD,
+0xFFFFFFFF,
+0xFFFEFDFF,
+0xFFFFFBFF,
+0xFFD0CDE8,
+0xFF00022F,
+0xFF050C3A,
+0xFF8586A5,
+0xFFFCFEFF,
+0xFFF7FCF8,
+0xFFFBFFFA,
+0xFFF8FFFF,
+0xFFF8FFFF,
+0xFF42466C,
+0xFF020635,
+0xFF0F143E,
+0xFF040A2C,
+0xFF5A6076,
+0xFFE0E7F7,
+0xFFF8FFFF,
+0xFFF7FFFF,
+0xFFF9FFFF,
+0xFFF3F9FF,
+0xFF878DA3,
+0xFF0B0F32,
+0xFF0D0D3F,
+0xFF090B3C,
+0xFF131939,
+0xFFF7FFFF,
+0xFFF9FFFF,
+0xFFFAFDFF,
+0xFFFFFDFF,
+0xFFFFFEFF,
+0xFFF7FFFF,
+0xFF15233D,
+0xFF03143F,
+0xFF07153C,
+0xFFFBFFFF,
+0xFFFDFBFC,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFDFF,
+0xFFFFFDFF,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFEFFFD,
+0xFFFBFFFF,
+0xFFF8FFFF,
+0xFF555C76,
+0xFF0D1140,
+0xFF020530,
+0xFFF4F7FF,
+0xFFFCFFFF,
+0xFFFFFFFF,
+0xFFFFFDFE,
+0xFFFFFEFF,
+0xFFFEFEFF,
+0xFFF4FAFF,
+0xFF060E33,
+0xFF081247,
+0xFF212D57,
+0xFFF8FFFF,
+0xFFF8FCFB,
+0xFFFDFBFC,
+0xFFFFFEFD,
+0xFFFFFFFB,
+0xFFFEFFFA,
+0xFFFBFFFF,
+0xFFF8FFFF,
+0xFF737A96,
+0xFF010930,
+0xFF0B143D,
+0xFF030C33,
+0xFF404966,
+0xFFCCD2E8,
+0xFFF9FFFF,
+0xFFF9FFFF,
+0xFFF7FFFF,
+0xFFF5FFFF,
+0xFF9EAAC0,
+0xFF0F1D38,
+0xFF061437,
+0xFF09153B,
+0xFF060E32,
+0xFFE7EDFF,
+0xFFFBFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFF8F8F8,
+0xFFFCFFFF,
+0xFFF9FFFF,
+0xFFF5FDFF,
+0xFF151E3D,
+0xFF080F39,
+0xFF09103E,
+0xFF090E36,
+0xFF7B80A0,
+0xFFE9EEFF,
+0xFFFBFFFF,
+0xFFF9FFFF,
+0xFFF9FFFF,
+0xFFF4FAFF,
+0xFFA7ADC5,
+0xFF171C3C,
+0xFF0A0F35,
+0xFF060D3B,
+0xFF394074,
+0xFF0A134C,
+0xFF030D40,
+0xFF454D72,
+0xFFF6FCFF,
+0xFFFBFFFF,
+0xFFFEFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFB,
+0xFFFEFFFB,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFAFEFF,
+0xFFFEFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFEFEFF,
+0xFFEDFFFF,
+0xFF4489B0,
+0xFF3696C9,
+0xFF2F99CD,
+0xFF3CAADF,
+0xFF39A8DD,
+0xFF34A4D4,
+0xFF33A0C7,
+0xFF3C99B8,
+0xFF599AB0,
+0xFFE2FFFF,
+0xFFF2FFFF,
+0xFFEBFFFF,
+0xFF4C90B5,
+0xFF3595C5,
+0xFF329CCE,
+0xFF36A8DC,
+0xFF34A7DE,
+0xFF38A7DE,
+0xFF3A9CCD,
+0xFF4092BA,
+0xFF669FBD,
+0xFFE0FFFF,
+0xFFE5FFFF,
+0xFF9BC6D9,
+0xFF408FB8,
+0xFF359AD0,
+0xFF37A5DA,
+0xFF33A7D8,
+0xFF33A8D4,
+0xFF32A2D0,
+0xFF2F98C8,
+0xFF3E89B1,
+0xFFCCEBFD,
+0xFFF6FFFF,
+0xFFFBFFFF,
+0xFFF7FCF8,
+0xFFFFFFFB,
+0xFFF9FFFF,
+0xFFEBFFFF,
+0xFF91C5DD,
+0xFF3E92B7,
+0xFF42A4D1,
+0xFF3B9CC9,
+0xFF3796C2,
+0xFF57B0DC,
+0xFF5CB3DE,
+0xFF54ACD4,
+0xFF4199C1,
+0xFF3E9BC4,
+0xFF49A2CA,
+0xFF4692B6,
+0xFF7FB8D5,
+0xFFE5FFFF,
+0xFFF3FFFF,
+0xFFFCFFFF,
+0xFFFFFEFC,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFF2FFFF,
+0xFFD7FFFF,
+0xFF428AB0,
+0xFF42A3D6,
+0xFF32A3DD,
+0xFF38AAE6,
+0xFF3DA1D5,
+0xFF4B8CB2,
+0xFFD6FCFF,
+0xFFF5FFFF,
+0xFFFFFFFF,
+0xFFFCFFFF,
+0xFFFBFFFF,
+0xFFF9FDFE,
+0xFFFCFFFF,
+0xFFF9FEFF,
+0xFFF6FDFF,
+0xFFC7CDE3,
+0xFF060C2C,
+0xFF040C33,
+0xFF0A133E,
+0xFF000B35,
+0xFF00072F,
+0xFF111E41,
+0xFF121E44,
+0xFF040C3A,
+0xFF000635,
+0xFF060E3D,
+0xFF0C133D,
+0xFF000021,
+0xFFADB8D6,
+0xFF94A0C6,
+0xFF060F36,
+0xFF03072A,
+0xFFB7B9D2,
+0xFFFEFCFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFDFEFF,
+0xFFF8FEFC,
+0xFFF8FFFF,
+0xFFC4D0E0,
+0xFF000A28,
+0xFF0C1540,
+0xFF0B1240,
+0xFF00022A,
+0xFF0A0F35,
+0xFF2B345D,
+0xFF1D294F,
+0xFF01092E,
+0xFF060B31,
+0xFF0A1239,
+0xFF030C33,
+0xFF96A4C9,
+0xFF031233,
+0xFF020D29,
+0xFFA7AEC1,
+0xFFFDFDFF,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFF9FBFA,
+0xFFF4FEFF,
+0xFFF5FFFF,
+0xFF293452,
+0xFF00042C,
+0xFF0B1844,
+0xFF000B36,
+0xFF00062F,
+0xFF091640,
+0xFF14204A,
+0xFF050E39,
+0xFF030A36,
+0xFF050C38,
+0xFF0A113D,
+0xFF00072E,
+0xFFA0ABC7,
+0xFF98A7C6,
+0xFF000C3D,
+0xFF000936,
+0xFFC3CADD,
+0xFFF7FAFF,
+0xFFFFFFFF,
+0xFFFAFDFF,
+0xFF495166,
+0xFF060F2C,
+0xFF00041F,
+0xFFFEFDFF,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFDFD,
+0xFFFFFDFD,
+0xFFFEFFFF,
+0xFFFCFFFF,
+0xFFFBFEFF,
+0xFF070A29,
+0xFF0C133F,
+0xFF2F375C,
+0xFFF9FFFF,
+0xFFFEFFFF,
+0xFFFFFDFF,
+0xFFFFFDFF,
+0xFFFCFEFB,
+0xFFFCFFFD,
+0xFFFEFEFF,
+0xFFFDFCFF,
+0xFFFFFCFF,
+0xFFCFCDE5,
+0xFF02062B,
+0xFF0D1238,
+0xFF8685A4,
+0xFFFDFCFF,
+0xFFFEFFFD,
+0xFFFCFFF8,
+0xFFFCFFFA,
+0xFFF8FDFF,
+0xFFF9FEFF,
+0xFF575C7C,
+0xFF000329,
+0xFF10133C,
+0xFF080D35,
+0xFF00052D,
+0xFF070B38,
+0xFF1C204F,
+0xFF080C3C,
+0xFF000434,
+0xFF090D3D,
+0xFF0E1040,
+0xFF080733,
+0xFF2F3253,
+0xFFF8FFFF,
+0xFFF4FEFF,
+0xFFF9FFFF,
+0xFFFCFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFF9FEFF,
+0xFF182140,
+0xFF0A1542,
+0xFF091337,
+0xFFFCFFFF,
+0xFFFDFDF5,
+0xFFFFFFFA,
+0xFFFFFFFD,
+0xFFFFFDFF,
+0xFFFFFDFF,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFEFFFD,
+0xFFFCFFFF,
+0xFFF9FFFF,
+0xFF585F72,
+0xFF0A0E34,
+0xFF020629,
+0xFFE9EDF8,
+0xFFFEFFFF,
+0xFFFDFDFD,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFCFCFF,
+0xFFF7FCFF,
+0xFF090F31,
+0xFF0C1443,
+0xFF242C53,
+0xFFF8FFFF,
+0xFFFBFFFC,
+0xFFFFFEFF,
+0xFFFFFEFD,
+0xFFFEFDF8,
+0xFFFFFFFA,
+0xFFFCFFFD,
+0xFFF9FFFF,
+0xFFF8FFFF,
+0xFF8086A6,
+0xFF000632,
+0xFF070D3F,
+0xFF0B1145,
+0xFF000539,
+0xFF000635,
+0xFF151D4B,
+0xFF07133B,
+0xFF00082E,
+0xFF000C33,
+0xFF0A163C,
+0xFF00082B,
+0xFF121B38,
+0xFFEBF2FF,
+0xFFFAFEFF,
+0xFFFEFFFF,
+0xFFFEFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFEFEFC,
+0xFFFCFFFF,
+0xFFF7FCFF,
+0xFFF6FDFF,
+0xFF3C4161,
+0xFF030832,
+0xFF0B0F3F,
+0xFF080C3C,
+0xFF040835,
+0xFF060B33,
+0xFF282C52,
+0xFF13173D,
+0xFF020532,
+0xFF050833,
+0xFF0E1036,
+0xFF020526,
+0xFF3C4063,
+0xFFF7FCFF,
+0xFF000432,
+0xFF0E1541,
+0xFF3E4562,
+0xFFF9FEFF,
+0xFFFCFFFF,
+0xFFFEFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFFFFFB,
+0xFFFEFFFB,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFAFFFB,
+0xFFFEFFFD,
+0xFFFDFFFE,
+0xFFEDFFFF,
+0xFF4A8FB8,
+0xFF3898CA,
+0xFF3599CA,
+0xFF3B9DCA,
+0xFF419AC6,
+0xFF3B97C0,
+0xFF369DC0,
+0xFF3B99B5,
+0xFF5D9FB5,
+0xFFDFFFFF,
+0xFFF2FFFF,
+0xFFE8FFFF,
+0xFF579CC3,
+0xFF3A99C9,
+0xFF389AC9,
+0xFF359AC6,
+0xFF3B9CC7,
+0xFF3998C4,
+0xFF3C9BCB,
+0xFF3C8FBB,
+0xFF659DBE,
+0xFFE0FFFF,
+0xFFE8FFFF,
+0xFF97C0D2,
+0xFF3F8EB9,
+0xFF3899CE,
+0xFF3797C7,
+0xFF3C9DC7,
+0xFF3B9EC5,
+0xFF349AC2,
+0xFF37A0CF,
+0xFF3D8CB5,
+0xFFCBEAFF,
+0xFFF9FFFF,
+0xFFF9FCFF,
+0xFFFEFFFF,
+0xFFFFFEFA,
+0xFFFFFFFB,
+0xFFF5FFFC,
+0xFFE9FFFF,
+0xFFB0F0FF,
+0xFF56A9D1,
+0xFF3994C0,
+0xFF3E9DCD,
+0xFF3999CC,
+0xFF3F9FD2,
+0xFF3E9BC7,
+0xFF3D99C2,
+0xFF3E96BE,
+0xFF529EC0,
+0xFFACE4FF,
+0xFFE4FFFF,
+0xFFF4FFFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFDFEFF,
+0xFFFEFFFF,
+0xFFF3FEFF,
+0xFFE9FFFF,
+0xFF8BBFD7,
+0xFF4594BB,
+0xFF44A3D3,
+0xFF42A2D2,
+0xFF4294BC,
+0xFF84B6D1,
+0xFFEDFFFF,
+0xFFF4FBFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFCFFFF,
+0xFFFEFFFD,
+0xFFFEFFFD,
+0xFFFBFFFE,
+0xFFFCFFFF,
+0xFFFBFFFF,
+0xFFFBFEFF,
+0xFF5B607E,
+0xFF01062C,
+0xFF020B36,
+0xFF06113F,
+0xFF000D3A,
+0xFF081542,
+0xFF050F40,
+0xFF000B39,
+0xFF00052E,
+0xFF282E4E,
+0xFFDEE5F8,
+0xFFF6FDFF,
+0xFF7F86A2,
+0xFF00001D,
+0xFF020321,
+0xFFB1B2C7,
+0xFFFFFDFF,
+0xFFFEFCFF,
+0xFFFDFCFF,
+0xFFFEFFFF,
+0xFFFBFFFC,
+0xFFF9FFFF,
+0xFFF7FFFF,
+0xFFE4EDFC,
+0xFF29324F,
+0xFF000027,
+0xFF0D123C,
+0xFF050C3A,
+0xFF040C3B,
+0xFF0D1543,
+0xFF040931,
+0xFF03092B,
+0xFF111834,
+0xFFDFE9FF,
+0xFFBAC6E0,
+0xFF00051D,
+0xFF00081B,
+0xFF9FA5B3,
+0xFFFDFDFF,
+0xFFFEFCFF,
+0xFFFEFDFF,
+0xFFFCFFFF,
+0xFFF8FFFF,
+0xFFF6FFFF,
+0xFFF7FDFF,
+0xFF9096B6,
+0xFF020B32,
+0xFF000B35,
+0xFF061441,
+0xFF04123F,
+0xFF000D39,
+0xFF08143E,
+0xFF030734,
+0xFF01042F,
+0xFF1E2248,
+0xFFCFD4F4,
+0xFFF4FFFF,
+0xFF74829F,
+0xFF031044,
+0xFF000738,
+0xFFCDD2E6,
+0xFFFEFFFF,
+0xFFFEFEFE,
+0xFFFEFFFF,
+0xFF3B4252,
+0xFF00061B,
+0xFF030619,
+0xFFFEFDFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFEFF,
+0xFFFFFEFD,
+0xFFFEFFFF,
+0xFFFCFFFF,
+0xFFFCFBFF,
+0xFF05071E,
+0xFF000121,
+0xFF202743,
+0xFFFBFFFF,
+0xFFF8F9FB,
+0xFFFFFDFF,
+0xFFFDFBFF,
+0xFFFEFFFD,
+0xFFFCFFFD,
+0xFFFDFDFD,
+0xFFFFFEFF,
+0xFFFFFDFF,
+0xFFC7C6D8,
+0xFF060A25,
+0xFF00001B,
+0xFF7C7D92,
+0xFFFEFCFF,
+0xFFFEFFFF,
+0xFFFDFFF7,
+0xFFFEFFF8,
+0xFFFCFFFB,
+0xFFFBFFFF,
+0xFFF9FFFF,
+0xFFB7BBD6,
+0xFF141939,
+0xFF01052B,
+0xFF080C39,
+0xFF090D3D,
+0xFF090F43,
+0xFF080D44,
+0xFF080E42,
+0xFF030737,
+0xFF050831,
+0xFF9898BA,
+0xFFFCFDFF,
+0xFFF7FCFF,
+0xFFF9FFFD,
+0xFFF8FEFC,
+0xFFFBFFFE,
+0xFFFEFCFD,
+0xFFFFFEFF,
+0xFFF9FCFF,
+0xFF0B1129,
+0xFF00082D,
+0xFF040B28,
+0xFFFCFDFF,
+0xFFFFFFF7,
+0xFFFFFFFA,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFDFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFCFFFF,
+0xFFFAFFFF,
+0xFF444A58,
+0xFF020524,
+0xFF020621,
+0xFFF1F4FB,
+0xFFFBFDFA,
+0xFFFFFFFF,
+0xFFFFFDFF,
+0xFFFFFEFF,
+0xFFFDFBFF,
+0xFFF8FBFF,
+0xFF00041E,
+0xFF02082C,
+0xFF19203D,
+0xFFF4FBFF,
+0xFFFCFFFB,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFC,
+0xFFFFFFFB,
+0xFFFBFFFA,
+0xFFF9FFFF,
+0xFFF9FFFF,
+0xFFF8FFFF,
+0xFFD5D8F9,
+0xFF2A2D58,
+0xFF000031,
+0xFF050A41,
+0xFF050F44,
+0xFF061041,
+0xFF081541,
+0xFF010F36,
+0xFF000A30,
+0xFF000A2D,
+0xFF79809C,
+0xFFF6FBFF,
+0xFFFAFEFF,
+0xFFFEFFFF,
+0xFFFBFBFD,
+0xFFFFFDFF,
+0xFFFEFCFF,
+0xFFFFFEFF,
+0xFFFFFFFB,
+0xFFFDFEF9,
+0xFFFEFFFF,
+0xFFFBFFFF,
+0xFFF8FDFF,
+0xFF9BA0BE,
+0xFF0F143A,
+0xFF000531,
+0xFF070E3C,
+0xFF09103E,
+0xFF070B38,
+0xFF0C103F,
+0xFF0B0D3D,
+0xFF050833,
+0xFF0D0E2C,
+0xFF8B8DA4,
+0xFFF9FEFF,
+0xFFF5FBFF,
+0xFF000724,
+0xFF000421,
+0xFF363C52,
+0xFFFBFFFF,
+0xFFFCFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFEFFFB,
+0xFFFEFFFB,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFAFAFF,
+0xFFFBFFFF,
+0xFFF8FFFB,
+0xFFF8FFFA,
+0xFFFAFFFA,
+0xFFF5FFFF,
+0xFFC9E6F6,
+0xFFC5EBFF,
+0xFFC3EEFF,
+0xFFC0EAFF,
+0xFFC7EAFF,
+0xFFC7E9FF,
+0xFFC4ECF6,
+0xFFC9EEF6,
+0xFFCDE5F1,
+0xFFF4FFFF,
+0xFFFAFDFF,
+0xFFFBFFFF,
+0xFFCADFF0,
+0xFFC6E7FA,
+0xFFC6EDFC,
+0xFFC5F1FE,
+0xFFC0EEFD,
+0xFFBFECFF,
+0xFFC2ECFF,
+0xFFC7EBFF,
+0xFFD6EBFC,
+0xFFF3FFFF,
+0xFFF8FFFF,
+0xFFE3F2F9,
+0xFFCBEAFC,
+0xFFC3EBFF,
+0xFFC1EAFF,
+0xFFC7EDFF,
+0xFFC4E9FC,
+0xFFC6ECFF,
+0xFFC2F1FF,
+0xFFBFE4F4,
+0xFFEEFCFF,
+0xFFFDFDFF,
+0xFFFFFDFF,
+0xFFFFFDFF,
+0xFFFFFDFF,
+0xFFF8F9FB,
+0xFFF9FFFD,
+0xFFF4FFFF,
+0xFFEEFFFF,
+0xFFE8FFFF,
+0xFFD4F7FF,
+0xFFA3CFEA,
+0xFF83BBE0,
+0xFF75AFD4,
+0xFF88BBD6,
+0xFFA6D4E4,
+0xFFCAF0FD,
+0xFFE9FFFF,
+0xFFEEFFFF,
+0xFFF2FFFF,
+0xFFFAFEFF,
+0xFFFFFFFB,
+0xFFFAFCF9,
+0xFFFCFFFF,
+0xFFFEFFFF,
+0xFFFDFEFF,
+0xFFFCFFFF,
+0xFFF7FDFD,
+0xFFF8FFFF,
+0xFFEEFFFF,
+0xFFA3D3E9,
+0xFF6EABCA,
+0xFF6FACCB,
+0xFFA4D6ED,
+0xFFEBFFFF,
+0xFFF5FFFF,
+0xFFF8FFFF,
+0xFFFCFFFF,
+0xFFFDFFFE,
+0xFFFEFDFB,
+0xFFFFFFFA,
+0xFFFFFDF8,
+0xFFFFFFFB,
+0xFFFCFCFA,
+0xFFFFFFFF,
+0xFFFAFBFF,
+0xFFFEFEFF,
+0xFFFAFDFF,
+0xFFA1A7BD,
+0xFF646B87,
+0xFF3C4564,
+0xFF374260,
+0xFF48536F,
+0xFF7F8AA0,
+0xFFD7E0EF,
+0xFFF8FFFF,
+0xFFF8FBFF,
+0xFFFBFEFF,
+0xFFDBDFEB,
+0xFFC0C3D4,
+0xFFC0C1D3,
+0xFFEDECFC,
+0xFFFEFDFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFEFFFF,
+0xFFFBFFFF,
+0xFFFBFFFD,
+0xFFF6FFFC,
+0xFFF7FFFF,
+0xFFD4DDEE,
+0xFF777E9B,
+0xFF42486C,
+0xFF2B3155,
+0xFF303656,
+0xFF666A83,
+0xFFAEB1C2,
+0xFFF9FFFF,
+0xFFF8FFFF,
+0xFFEAF4FF,
+0xFFB7C1CD,
+0xFFBAC2CD,
+0xFFE5E9F2,
+0xFFFEFFFF,
+0xFFFFFEFF,
+0xFFFEFDFF,
+0xFF61657E,
+0xFF697293,
+0xFF636989,
+0xFFF9FBFF,
+0xFFFBFCFF,
+0xFFF9FFFF,
+0xFFB9C2D3,
+0xFF6D788E,
+0xFF3A455B,
+0xFF384355,
+0xFF4B5366,
+0xFF8789A0,
+0xFFD7D7EF,
+0xFFFCFDFF,
+0xFFFAFDFF,
+0xFFF8FFFF,
+0xFF3D4868,
+0xFF051145,
+0xFF000435,
+0xFFF6F8FF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFF8F9FB,
+0xFFCFD6E0,
+0xFFBDC5D2,
+0xFFBABCC9,
+0xFFFCFCFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFEFF,
+0xFFFFFEFD,
+0xFFFEFFFD,
+0xFFFEFFFF,
+0xFFFFFEFF,
+0xFFBFBFC9,
+0xFFBEC3D6,
+0xFFC6CCDC,
+0xFFF9FEFF,
+0xFFFEFFFF,
+0xFFFFFCFF,
+0xFFFFFDFF,
+0xFFFEFFFF,
+0xFFFCFFFB,
+0xFFFFFFFD,
+0xFFFEFEFE,
+0xFFFFFDFF,
+0xFFF5F3FE,
+0xFFB6BAC6,
+0xFFC3C9D5,
+0xFFE2E2EC,
+0xFFFFFEFF,
+0xFFFCFCFC,
+0xFFFFFFFB,
+0xFFFEFFF9,
+0xFFFBFEF7,
+0xFFFEFFFB,
+0xFFF7FBFC,
+0xFFF9FEFF,
+0xFFF9FFFF,
+0xFFCCD3E6,
+0xFF727A91,
+0xFF414864,
+0xFF39425F,
+0xFF424B68,
+0xFF69738C,
+0xFFB3BBD0,
+0xFFF7FCFF,
+0xFFFCFEFF,
+0xFFF9F9FF,
+0xFFFCFFFF,
+0xFFFBFFFF,
+0xFFF9FFFF,
+0xFFFCFFFF,
+0xFFFFFFFD,
+0xFFFEFEFE,
+0xFFFEFFFF,
+0xFFC6CAD3,
+0xFFBCC1D4,
+0xFFB9BFCF,
+0xFFFEFEFF,
+0xFFFFFEFF,
+0xFFFFFFFB,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFDFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFCFFFF,
+0xFFFBFFFF,
+0xFFD4D8E1,
+0xFFC1C3D8,
+0xFFB6B9CC,
+0xFFFAFEFF,
+0xFFFEFFFD,
+0xFFFDFDFF,
+0xFFFDFBFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFCFFFF,
+0xFFBFC2D1,
+0xFFBBC0D6,
+0xFFC3C9D9,
+0xFFFBFFFF,
+0xFFFEFFFA,
+0xFFFEFCFF,
+0xFFFFFDFF,
+0xFFFFFCFF,
+0xFFFFFDFF,
+0xFFFEFFFF,
+0xFFFBFFFF,
+0xFFF6FBFF,
+0xFFFBFFFF,
+0xFFFCFFFF,
+0xFFFBFDFF,
+0xFFE0E4FD,
+0xFF868BA9,
+0xFF4F5875,
+0xFF303C56,
+0xFF38445A,
+0xFF626D81,
+0xFFA6AEC3,
+0xFFF5FCFF,
+0xFFFAFEFF,
+0xFFFEFFFF,
+0xFFFDFDFD,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFDFDFD,
+0xFFFDFBFC,
+0xFFFFFDFE,
+0xFFFEFEFF,
+0xFFFEFFFF,
+0xFFFAFEFF,
+0xFFF9FFFF,
+0xFFF4FCFF,
+0xFFC2CEDE,
+0xFF758096,
+0xFF3F4962,
+0xFF39405C,
+0xFF424764,
+0xFF656986,
+0xFFB4B6CD,
+0xFFF8FAFF,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFBFFFF,
+0xFFB9C0CA,
+0xFFBEC4D0,
+0xFFCDD1DA,
+0xFFFAFDFF,
+0xFFFEFFFF,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFEFFFD,
+0xFFFEFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFEFFFF,
+0xFFF8FFF8,
+0xFFF9FFF8,
+0xFFFBFFFB,
+0xFFFBFFFF,
+0xFFF9FFFF,
+0xFFF8FFFF,
+0xFFF7FFFF,
+0xFFF5FFFF,
+0xFFFBFEFF,
+0xFFFBFDFF,
+0xFFFCFFFF,
+0xFFFBFFFF,
+0xFFF9FEFF,
+0xFFFCFFFF,
+0xFFFFFEFF,
+0xFFFEFCFF,
+0xFFFFFEFF,
+0xFFFEFFFF,
+0xFFF9FFFF,
+0xFFF8FFFF,
+0xFFF0FEFF,
+0xFFF5FFFF,
+0xFFF5FFFF,
+0xFFF6FFFF,
+0xFFFCFFFF,
+0xFFFEFDFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFF7FFFF,
+0xFFF7FFFF,
+0xFFF7FFFF,
+0xFFF8FFFF,
+0xFFFBFFFF,
+0xFFF7FCFF,
+0xFFF5FFFF,
+0xFFF7FFFF,
+0xFFFBFEFF,
+0xFFFFFDFF,
+0xFFFFFDFF,
+0xFFFFFBFF,
+0xFFFFFDFF,
+0xFFFFFEFF,
+0xFFFDFFFA,
+0xFFFEFFFB,
+0xFFFDFEFF,
+0xFFFEFEFF,
+0xFFFAFFFF,
+0xFFF5FFFF,
+0xFFE9FFFF,
+0xFFE7FFFF,
+0xFFECFFFF,
+0xFFEFFFFF,
+0xFFF6FFFF,
+0xFFFBFFFF,
+0xFFFAFDFF,
+0xFFFEFFFF,
+0xFFFDFDFB,
+0xFFFEFFFB,
+0xFFFBFFFD,
+0xFFF9FFFD,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFCFDFF,
+0xFFFEFFFF,
+0xFFFFFFF8,
+0xFFF8FEFA,
+0xFFEDFFFF,
+0xFFE7FFFF,
+0xFFE7FFFF,
+0xFFECFFFF,
+0xFFF6FFFF,
+0xFFFAFFFE,
+0xFFFAFFFF,
+0xFFFBFFFF,
+0xFFFEFEFE,
+0xFFFFFFFD,
+0xFFFFFDF9,
+0xFFFFFEF8,
+0xFFFFFFFA,
+0xFFFFFEFB,
+0xFFFFFEFA,
+0xFFFFFFFB,
+0xFFFEFEFC,
+0xFFFEFFFF,
+0xFFFCFEFF,
+0xFFFBFEFF,
+0xFFF9FEFF,
+0xFFF5FCFF,
+0xFFF8FFFF,
+0xFFF9FFFF,
+0xFFF9FFFF,
+0xFFFCFFFD,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFDFEFF,
+0xFFFEFEFF,
+0xFFFEFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFDFCFF,
+0xFFFEFDFF,
+0xFFFEFDFF,
+0xFFFEFFFF,
+0xFFFDFFF9,
+0xFFFCFFFA,
+0xFFFBFFFD,
+0xFFF4FCFF,
+0xFFF8FFFF,
+0xFFF7FDFF,
+0xFFF9FEFF,
+0xFFF9FCFF,
+0xFFFCFEFF,
+0xFFFEFFFF,
+0xFFFCFFFF,
+0xFFFAFFFF,
+0xFFFAFFFF,
+0xFFF9FFFF,
+0xFFFBFFFF,
+0xFFFBFFFF,
+0xFFFDFFFE,
+0xFFFEFFFF,
+0xFFF9FBFF,
+0xFF494C6B,
+0xFF000632,
+0xFF00042E,
+0xFF9799B2,
+0xFFFCFEFF,
+0xFFFBFFFF,
+0xFFFAFFFF,
+0xFFF9FFFF,
+0xFFF9FFFF,
+0xFFF8FDFF,
+0xFFFCFFFF,
+0xFFFDFDFF,
+0xFFFEFEFF,
+0xFFFBFEFF,
+0xFFF9FFFF,
+0xFFF4FAFF,
+0xFF020A2F,
+0xFF0C1649,
+0xFF0C1341,
+0xFFFCFDFF,
+0xFFFEFDFF,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFAFFFF,
+0xFFFBFFFF,
+0xFFFCFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFEFF,
+0xFFFFFEFD,
+0xFFFEFFFD,
+0xFFFEFFFD,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFCFFFF,
+0xFFFBFFFF,
+0xFFFCFFFF,
+0xFFFDFEFF,
+0xFFFFFEFF,
+0xFFFEFDFF,
+0xFFFEFFFD,
+0xFFF9FEF8,
+0xFFFFFFFB,
+0xFFFFFFFD,
+0xFFFEFCFF,
+0xFFFFFEFF,
+0xFFFCFFFF,
+0xFFFBFFFF,
+0xFFFBFCFE,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFCFCFC,
+0xFFFFFFFD,
+0xFFFFFFFB,
+0xFFFEFFFA,
+0xFFFEFFFB,
+0xFFFCFFFF,
+0xFFFBFFFF,
+0xFFF8FFFF,
+0xFFF9FFFF,
+0xFFF8FFFF,
+0xFFF5FFFF,
+0xFFF5FFFF,
+0xFFF7FFFF,
+0xFFF8FFFF,
+0xFFF8FFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFEFEFF,
+0xFFFDFEFF,
+0xFFFCFFFF,
+0xFFFBFFFC,
+0xFFFFFFFB,
+0xFFFDFDFB,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFBFFFF,
+0xFFFCFFFF,
+0xFFFFFEFF,
+0xFFFEFCFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFEFFFD,
+0xFFFCFFFD,
+0xFFFBFFFF,
+0xFFFBFDFF,
+0xFFFCFEFF,
+0xFFFEFFFF,
+0xFFFDFDFB,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFEFCFF,
+0xFFFFFFFF,
+0xFFFDFEFF,
+0xFFFBFEFF,
+0xFFFBFFFF,
+0xFFFBFFFF,
+0xFFFAFFF9,
+0xFFFEFFF8,
+0xFFFFFEFF,
+0xFFFFFAFF,
+0xFFFFFDFF,
+0xFFFFFDFF,
+0xFFFDFDFF,
+0xFFFEFFFF,
+0xFFFCFFFF,
+0xFFFBFFFE,
+0xFFFEFFFB,
+0xFFFBFDFA,
+0xFFFCFFFF,
+0xFFFBFEFF,
+0xFFF9FFFF,
+0xFFF8FFFF,
+0xFFF8FFFF,
+0xFFF9FFFF,
+0xFFFBFFFF,
+0xFFFCFFFF,
+0xFFFCFDFF,
+0xFFFFFFFF,
+0xFFFFFEFA,
+0xFFFFFDFA,
+0xFFFFFDFF,
+0xFFFFFDFF,
+0xFFFDFDFF,
+0xFFFFFFFF,
+0xFFFFFDFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFEFCFD,
+0xFFFEFFFD,
+0xFFFBFFFC,
+0xFFF9FFFF,
+0xFFF5FFFF,
+0xFFF5FFFF,
+0xFFF4FFFF,
+0xFFF7FFFF,
+0xFFF7FDFF,
+0xFFFAFEFF,
+0xFFFCFFFF,
+0xFFFEFFFF,
+0xFFFBFDFC,
+0xFFFCFEFB,
+0xFFFCFFFD,
+0xFFFAFEFD,
+0xFFFBFFFF,
+0xFFFCFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFEFFFD,
+0xFFFEFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFA,
+0xFFFFFFFA,
+0xFFFEFFFD,
+0xFFFBFFFF,
+0xFFF9FFFF,
+0xFFF9FFFF,
+0xFFFBFFFF,
+0xFFFCFFFF,
+0xFFFFFDFF,
+0xFFFFFCFF,
+0xFFFFFDFF,
+0xFFFEFFFF,
+0xFFFBFFFF,
+0xFFF9FFFF,
+0xFFFBFFFF,
+0xFFFCFFFF,
+0xFFFEFFFF,
+0xFFFEFFFD,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFBFFFF,
+0xFFFBFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFBFFFF,
+0xFFF8FFFF,
+0xFFF8FFFB,
+0xFFF9FFFB,
+0xFFFCFFFF,
+0xFFFEFFFF,
+0xFFFEFFFD,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFDFF,
+0xFFFFFDFD,
+0xFFFFFEFB,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFCFFFF,
+0xFFF7FFFF,
+0xFFF5FFFF,
+0xFFF5FFFF,
+0xFFF7FFFF,
+0xFFF9FFFF,
+0xFFFCFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFA,
+0xFFFCFFFA,
+0xFFF8FFFD,
+0xFFF9FFFD,
+0xFFFFFFFD,
+0xFFFFFEFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFB,
+0xFFFFFFFB,
+0xFFFBFFFF,
+0xFFF8FFFF,
+0xFFF8FFFF,
+0xFFF9FFFF,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFB,
+0xFFFFFFFA,
+0xFFFFFEFB,
+0xFFFFFEFB,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFEFEFF,
+0xFFFEFEFF,
+0xFFFFFDFF,
+0xFFFFFDFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFB,
+0xFFFFFFFB,
+0xFFFEFFFD,
+0xFFFEFFFD,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFEFFFA,
+0xFFFCFFFB,
+0xFFFBFFFF,
+0xFFFBFFFF,
+0xFFFCFFFF,
+0xFFFEFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFEFFFF,
+0xFFFEFEFF,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFBFFFC,
+0xFFFEFFFA,
+0xFFFBFDF8,
+0xFFFCFFFF,
+0xFFD8DDF1,
+0xFF00042E,
+0xFF0C1442,
+0xFF030C2D,
+0xFFEFF7FF,
+0xFFF7FEFF,
+0xFFFCFFFF,
+0xFFFEFDFF,
+0xFFFFFEFF,
+0xFFFFFDFF,
+0xFFFEFCFF,
+0xFFFEFEFF,
+0xFFFCFFFF,
+0xFFF8FFFF,
+0xFFF6FFFF,
+0xFF61698E,
+0xFF060D3B,
+0xFF09103C,
+0xFF74789B,
+0xFFFCFEFF,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFEFFFB,
+0xFFFFFFFB,
+0xFFFFFFFB,
+0xFFFEFFFF,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFEFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFEFFFD,
+0xFFFCFFFA,
+0xFFFFFFFA,
+0xFFFFFFFB,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFCFFFD,
+0xFFFCFFFD,
+0xFFFEFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFEFEFF,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFBFFFF,
+0xFFF9FFFF,
+0xFFF9FFFF,
+0xFFF9FFFF,
+0xFFF9FFFD,
+0xFFFBFFFB,
+0xFFFFFFFB,
+0xFFFFFFFB,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFCFFFB,
+0xFFFCFFFA,
+0xFFFFFFFB,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFEFEFF,
+0xFFFEFEFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFB,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFEFFFD,
+0xFFFEFFFD,
+0xFFFCFFFF,
+0xFFFEFEFF,
+0xFFFEFEFF,
+0xFFFEFFFF,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFCFFFF,
+0xFFFEFFFA,
+0xFFFEFFFA,
+0xFFFFFEFF,
+0xFFFFFDFF,
+0xFFFFFCFF,
+0xFFFFFDFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFCFFFF,
+0xFFFCFFFD,
+0xFFFEFFFD,
+0xFFFEFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFD,
+0xFFFFFFFA,
+0xFFFFFFFA,
+0xFFFFFDFD,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFDFF,
+0xFFFFFDFF,
+0xFFFFFDFF,
+0xFFFFFEFF,
+0xFFFEFFFF,
+0xFFFBFFFF,
+0xFFF9FFFF,
+0xFFF8FFFF,
+0xFFF8FFFF,
+0xFFF9FFFF,
+0xFFFCFFFF,
+0xFFFEFFFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFEFFFB,
+0xFFFEFFFB,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFEFFFD,
+0xFFFEFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFBFB,
+0xFFFFFCFA,
+0xFFFFFFFD,
+0xFFFBFFFF,
+0xFFFBFFFF,
+0xFFFCFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFDFF,
+0xFFFFFDFF,
+0xFFFFFDFF,
+0xFFFFFEFF,
+0xFFFCFFFF,
+0xFFF9FFFF,
+0xFFF9FFFF,
+0xFFFBFFFF,
+0xFFFCFFFD,
+0xFFFFFFFB,
+0xFFFFFFFD,
+0xFFFFFEFD,
+0xFFFFFDFD,
+0xFFFFFEFF,
+0xFFFEFFFF,
+0xFFFCFFFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFCFFFD,
+0xFFFCFFFB,
+0xFFFCFFF8,
+0xFFFCFFFA,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFEFD,
+0xFFFFFDFF,
+0xFFFFFEFF,
+0xFFFEFFFB,
+0xFFFEFFFB,
+0xFFFEFFFF,
+0xFFFFFEFF,
+0xFFFFFDFB,
+0xFFFFFDFB,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFEFFFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFB,
+0xFFFCFFFD,
+0xFFF9FFFF,
+0xFFFBFFFF,
+0xFFFFFEFF,
+0xFFFFFDFD,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFB,
+0xFFFFFFFA,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFDFF,
+0xFFFFFDFF,
+0xFFFFFDFD,
+0xFFFFFEFB,
+0xFFFFFFFB,
+0xFFFFFFFB,
+0xFFFEFFFD,
+0xFFFEFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFA,
+0xFFFFFFFA,
+0xFFFFFEFB,
+0xFFFFFEFF,
+0xFFFFFDFF,
+0xFFFFFEFF,
+0xFFFFFFFB,
+0xFFFFFFFB,
+0xFFFEFFFB,
+0xFFFEFFFD,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFB,
+0xFFFFFFFB,
+0xFFFFFEFF,
+0xFFFFFDFF,
+0xFFFFFEFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFEFFFB,
+0xFFFFFFF8,
+0xFFFEFFFA,
+0xFFFAFEFD,
+0xFFF9FDFF,
+0xFF4A4E71,
+0xFF050E39,
+0xFF06123A,
+0xFF071434,
+0xFFEEF6FF,
+0xFFFAFDFF,
+0xFFFEFEFF,
+0xFFFBF8FF,
+0xFFFDFAFF,
+0xFFFFFEFF,
+0xFFF9FEFF,
+0xFFF8FFFF,
+0xFFF3FFFF,
+0xFF8894AE,
+0xFF000730,
+0xFF0E1541,
+0xFF020727,
+0xFFFAFCFF,
+0xFFFEFEFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFB,
+0xFFFFFFFB,
+0xFFFEFFFD,
+0xFFFEFFFD,
+0xFFFEFFFD,
+0xFFFEFFFF,
+0xFFFFFEFF,
+0xFFFEFFFF,
+0xFFFEFFFB,
+0xFFFEFFF8,
+0xFFFFFFFA,
+0xFFFFFFFB,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFEFFFD,
+0xFFFEFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFDFF,
+0xFFFFFDFF,
+0xFFFFFDFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFEFFFD,
+0xFFFCFFFA,
+0xFFFCFFFB,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFBFFFB,
+0xFFFCFFFA,
+0xFFFFFFFA,
+0xFFFFFFFA,
+0xFFFFFFFB,
+0xFFFFFFFB,
+0xFFFEFFFB,
+0xFFFEFFFB,
+0xFFFFFFFB,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFEFEFF,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFFFFFA,
+0xFFFFFFFB,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFEFFFB,
+0xFFFEFFFD,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFEFFFA,
+0xFFFEFFFB,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFDFF,
+0xFFFFFDFF,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFEFFFD,
+0xFFFCFFFD,
+0xFFFEFFFD,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFDFF,
+0xFFFFFDFF,
+0xFFFFFDFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFB,
+0xFFFFFFFA,
+0xFFFFFFFA,
+0xFFFFFEFD,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFDFF,
+0xFFFFFCFF,
+0xFFFFFDFF,
+0xFFFFFDFF,
+0xFFFFFFFF,
+0xFFFCFFFF,
+0xFFFBFFFF,
+0xFFF9FFFF,
+0xFFFBFFFF,
+0xFFFCFFFF,
+0xFFFEFFFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFB,
+0xFFFFFFFA,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFDFF,
+0xFFFFFDFF,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFEFFFD,
+0xFFFEFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFCFD,
+0xFFFFFCFB,
+0xFFFFFFFB,
+0xFFFEFFFD,
+0xFFFEFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFBFFFD,
+0xFFFBFFFD,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFD,
+0xFFFFFDFD,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFA,
+0xFFFFFFFA,
+0xFFFFFFFA,
+0xFFFFFEFB,
+0xFFFFFEFB,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFEFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFEFFFB,
+0xFFFBFFFA,
+0xFFF9FFFA,
+0xFFFBFFFD,
+0xFFFEFFFD,
+0xFFFFFFFA,
+0xFFFFFEFA,
+0xFFFFFDFD,
+0xFFFFFEFF,
+0xFFFBFFFF,
+0xFFFBFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFEFFFF,
+0xFFFFFEFF,
+0xFFFFFDFF,
+0xFFFFFDFF,
+0xFFFFFDFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFEFFFF,
+0xFFFFFFFD,
+0xFFFFFFFA,
+0xFFFEFFFD,
+0xFFFEFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFDFF,
+0xFFFFFDFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFD,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFD,
+0xFFFFFEFD,
+0xFFFFFEFD,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFFFB,
+0xFFFFFFFB,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFF8,
+0xFFFFFFF4,
+0xFFFFFFF6,
+0xFFFFFEFA,
+0xFFFFFDFF,
+0xFFFFFDFF,
+0xFFFFFDFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFEFFFD,
+0xFFFFFFFB,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFFFB,
+0xFFFCFBF7,
+0xFFFFFFFB,
+0xFFFDFDFD,
+0xFFFEFEFF,
+0xFFFBFEFF,
+0xFF121838,
+0xFF0A1542,
+0xFF0A1849,
+0xFF000635,
+0xFF858DB2,
+0xFFF6FCFF,
+0xFFF8FFFF,
+0xFFF8FFFF,
+0xFFF5FFFF,
+0xFFF4FFFF,
+0xFFD4E3F6,
+0xFF3F4E6D,
+0xFF000B31,
+0xFF0D143E,
+0xFF000427,
+0xFFB2B5C4,
+0xFFFEFFFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFB,
+0xFFFFFFF8,
+0xFFFFFFFA,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFDFF,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFFFFFA,
+0xFFFFFFFA,
+0xFFFFFFFB,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFFFFFD,
+0xFFFFFFFB,
+0xFFFFFEFB,
+0xFFFFFFFB,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFFFFFA,
+0xFFFFFFFB,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFB,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFEFFFD,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFEFFFD,
+0xFFFEFFFD,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFFFFFB,
+0xFFFFFFFB,
+0xFFFEFFFB,
+0xFFFEFFFB,
+0xFFFFFFFB,
+0xFFFFFFFB,
+0xFFFFFFFB,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFDFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFFFFFB,
+0xFFFFFFFB,
+0xFFFEFFFB,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFDFD,
+0xFFFFFDFD,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFEFFFF,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFB,
+0xFFFFFFF8,
+0xFFFFFFFA,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFB,
+0xFFFFFFFA,
+0xFFFFFFFB,
+0xFFFFFEFF,
+0xFFFFFDFF,
+0xFFFFFDFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFD,
+0xFFFFFFFD,
+0xFFFFFDFF,
+0xFFFFFCFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFCFFFD,
+0xFFFCFFFD,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFEFFFF,
+0xFFFCFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFB,
+0xFFFFFFFA,
+0xFFFFFFFA,
+0xFFFFFEFB,
+0xFFFFFEFD,
+0xFFFFFDFF,
+0xFFFFFEFF,
+0xFFFEFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFEFFFA,
+0xFFF9FFFA,
+0xFFF9FFFA,
+0xFFFBFFFB,
+0xFFFEFFFB,
+0xFFFFFEFB,
+0xFFFFFEFB,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFCFFFD,
+0xFFFCFFFD,
+0xFFFFFFFD,
+0xFFFFFEFD,
+0xFFFFFDFD,
+0xFFFFFEFB,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFDFF,
+0xFFFFFDFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFDFF,
+0xFFFFFEFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFEFFFD,
+0xFFFEFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFDFF,
+0xFFFFFDFD,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFEFFFD,
+0xFFFEFFFD,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFA,
+0xFFFFFFFA,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFB,
+0xFFFFFFF8,
+0xFFFFFFF8,
+0xFFFFFEFB,
+0xFFFFFEFF,
+0xFFFFFDFF,
+0xFFFFFDFF,
+0xFFFFFDFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFEFFFD,
+0xFFFCFFFD,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFFFEFA,
+0xFFFFFFFB,
+0xFFFCFBF9,
+0xFFFDFDFD,
+0xFFFEFDFF,
+0xFFFAFAFF,
+0xFFFBFEFF,
+0xFF1B2445,
+0xFF000A37,
+0xFF0B154A,
+0xFF00093A,
+0xFF00092D,
+0xFF22304B,
+0xFF374761,
+0xFF384963,
+0xFF0C1D37,
+0xFF000927,
+0xFF06133D,
+0xFF0D1641,
+0xFF000428,
+0xFF8D92A8,
+0xFFFDFEFF,
+0xFFFBFCF7,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFB,
+0xFFFFFFFA,
+0xFFFFFFFB,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFDFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFB,
+0xFFFFFFFB,
+0xFFFFFFFB,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFFFFFB,
+0xFFFFFFFB,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFB,
+0xFFFFFFFB,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFFFFFB,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFCFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFD,
+0xFFFFFFFB,
+0xFFFFFFFB,
+0xFFFFFFFA,
+0xFFFFFFFA,
+0xFFFFFFFB,
+0xFFFFFFFB,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFB,
+0xFFFEFFFB,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFDFF,
+0xFFFFFDFF,
+0xFFFFFEFD,
+0xFFFFFFFB,
+0xFFFFFFFD,
+0xFFFCFFFD,
+0xFFFBFFFF,
+0xFFFBFFFF,
+0xFFFCFFFF,
+0xFFFEFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFEFD,
+0xFFFFFEFD,
+0xFFFFFEFD,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFB,
+0xFFFFFFFA,
+0xFFFFFFFA,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFB,
+0xFFFFFFFA,
+0xFFFFFFFB,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFD,
+0xFFFCFFFB,
+0xFFFCFFFD,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFEFFFB,
+0xFFFEFFFA,
+0xFFFFFFFA,
+0xFFFEFFFB,
+0xFFFCFFFF,
+0xFFFBFFFF,
+0xFFFBFFFF,
+0xFFFCFFFF,
+0xFFFFFFFD,
+0xFFFFFFFB,
+0xFFFFFFFD,
+0xFFFEFFFF,
+0xFFFCFFFF,
+0xFFFBFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFBFFFF,
+0xFFFBFFFF,
+0xFFFCFFFF,
+0xFFFEFFFF,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFEFF,
+0xFFFEFEFF,
+0xFFFFFFFF,
+0xFFFEFFFB,
+0xFFFCFFFB,
+0xFFFCFFFB,
+0xFFFEFFFF,
+0xFFFFFEFF,
+0xFFFFFCFF,
+0xFFFFFDFF,
+0xFFFEFFFF,
+0xFFFCFFFD,
+0xFFFFFFFA,
+0xFFFFFFFA,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFEFFFD,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFEFFFD,
+0xFFFEFFFD,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFEFFFF,
+0xFFFCFFFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFEFD,
+0xFFFFFDFD,
+0xFFFFFEFD,
+0xFFFFFFFD,
+0xFFFCFFFF,
+0xFFFBFFFF,
+0xFFFCFFFF,
+0xFFFEFFFF,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFEFFFF,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFEFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFB,
+0xFFFFFFF8,
+0xFFFFFFFA,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFDFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFEFFFD,
+0xFFFCFFFD,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFCFBF7,
+0xFFFFFFFA,
+0xFFFEFFF9,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFEFFFF,
+0xFFFBFFFF,
+0xFF7F8699,
+0xFF070F36,
+0xFF000836,
+0xFF05123E,
+0xFF02143C,
+0xFF000F37,
+0xFF00133B,
+0xFF02143A,
+0xFF021037,
+0xFF00032E,
+0xFF272B50,
+0xFFD6D8EF,
+0xFFFCFEFF,
+0xFFFDFEFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFDFF,
+0xFFFFFDFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFB,
+0xFFFFFFFA,
+0xFFFFFEFB,
+0xFFFFFEFF,
+0xFFFFFDFF,
+0xFFFFFDFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFFFFFB,
+0xFFFFFFFB,
+0xFFFFFFFB,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFDFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFFFFFB,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFEFFFD,
+0xFFFEFFFB,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFFFEFF,
+0xFFFFFDFF,
+0xFFFFFDFF,
+0xFFFFFDFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFCFFFF,
+0xFFFCFFFD,
+0xFFFFFFFB,
+0xFFFFFFFB,
+0xFFFFFEFB,
+0xFFFFFFFB,
+0xFFFFFFFB,
+0xFFFFFFFF,
+0xFFFFFDFF,
+0xFFFFFDFF,
+0xFFFEFFFF,
+0xFFFCFFFB,
+0xFFFBFFFA,
+0xFFFBFFFA,
+0xFFFCFFFB,
+0xFFFEFFFD,
+0xFFFFFEFF,
+0xFFFFFDFF,
+0xFFFFFEFF,
+0xFFFFFEFD,
+0xFFFFFFFF,
+0xFFFCFFFF,
+0xFFF9FFFF,
+0xFFF9FFFF,
+0xFFFCFFFB,
+0xFFFEFFFA,
+0xFFFFFFFB,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFFFFFB,
+0xFFFFFFFB,
+0xFFFFFFFB,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFEFFFB,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFB,
+0xFFFFFFFB,
+0xFFFFFFFB,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFBFFFD,
+0xFFFBFFFD,
+0xFFFEFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFEFFFB,
+0xFFFCFFFA,
+0xFFFEFFFA,
+0xFFFEFFFB,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFEFFFF,
+0xFFFFFFFD,
+0xFFFFFFFB,
+0xFFFFFEFD,
+0xFFFFFEFF,
+0xFFFCFFFF,
+0xFFFBFFFF,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFEFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFBFFFF,
+0xFFFBFFFF,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFB,
+0xFFFEFFFD,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFDFF,
+0xFFFFFCFF,
+0xFFFFFDFF,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFFFEFB,
+0xFFFFFEFB,
+0xFFFFFFFD,
+0xFFFEFFFF,
+0xFFFFFFFD,
+0xFFFFFFFB,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFCFFFF,
+0xFFFEFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFCFFFB,
+0xFFFCFFFB,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFDFF,
+0xFFFFFEFF,
+0xFFFEFFFD,
+0xFFFCFFFD,
+0xFFFCFFFD,
+0xFFFEFFFD,
+0xFFFFFEFD,
+0xFFFFFDFD,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFCFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFEFFFF,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFCFFFD,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFB,
+0xFFFFFFFA,
+0xFFFFFFFB,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFEFFFD,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFB,
+0xFFFFFFFB,
+0xFFFEFEFC,
+0xFFFEFFFF,
+0xFFFAFBFF,
+0xFFFDFCFF,
+0xFFFFFFFF,
+0xFFFDFDFB,
+0xFFFEFFFD,
+0xFFFBFEFF,
+0xFFF9FEFF,
+0xFFA8AECE,
+0xFF5C668A,
+0xFF29375A,
+0xFF19274A,
+0xFF182649,
+0xFF3C4669,
+0xFF7A83A4,
+0xFFD3D8F8,
+0xFFFBFDFF,
+0xFFFCFEFF,
+0xFFF9FAFE,
+0xFFFCFEFD,
+0xFFFEFFFB,
+0xFFFFFFFB,
+0xFFFFFFFB,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFD,
+0xFFFFFFFB,
+0xFFFFFFFB,
+0xFFFFFEFD,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFDFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFB,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFB,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFDFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFFFEFD,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFEFFFF,
+0xFFFCFFFF,
+0xFFFCFFFB,
+0xFFFEFFFB,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFD,
+0xFFFCFFFD,
+0xFFFBFFFF,
+0xFFFCFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFDFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFCFFFF,
+0xFFFBFFFF,
+0xFFFCFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFEFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFCFF,
+0xFFFFFDFF,
+0xFFFFFFFF,
+0xFFFCFFFD,
+0xFFFBFFFA,
+0xFFF9FFF8,
+0xFFFBFFFA,
+0xFFFCFFFD,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFD,
+0xFFFFFFFD,
+0xFFFEFFFF,
+0xFFFBFFFF,
+0xFFFBFFFF,
+0xFFFCFFFF,
+0xFFFEFFFB,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFB,
+0xFFFFFFFB,
+0xFFFFFFFB,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFEFFFD,
+0xFFFEFFFB,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFB,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFBFFFF,
+0xFFFCFFFF,
+0xFFFFFEFD,
+0xFFFFFDFD,
+0xFFFFFDFF,
+0xFFFFFEFF,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFCFF,
+0xFFFFFCFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFCFD,
+0xFFFFFDFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFCFFFD,
+0xFFFCFFFB,
+0xFFFBFFFD,
+0xFFFCFFFB,
+0xFFFFFFFA,
+0xFFFFFFFA,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFDFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFFFFFA,
+0xFFFFFFFB,
+0xFFFFFEFF,
+0xFFFFFDFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFDFB,
+0xFFFFFEFB,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFFFDFF,
+0xFFFFFDFF,
+0xFFFCFFFF,
+0xFFFBFFFF,
+0xFFFFFFFA,
+0xFFFFFFFA,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFDFF,
+0xFFFFFDFF,
+0xFFFFFEFF,
+0xFFFEFFFF,
+0xFFFCFFFD,
+0xFFFEFFFD,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFEFF,
+0xFFFFFDFF,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFEFFFB,
+0xFFFEFFFB,
+0xFFFEFFFB,
+0xFFFEFFFD,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFFFFFA,
+0xFFFFFFFA,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFD,
+0xFFFEFFFF,
+0xFFFEFEFF,
+0xFFFEFEFF,
+0xFFFEFFFF,
+0xFFFEFFFB,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFB,
+0xFFFFFFFB,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFEFEFE,
+0xFFFAFBFD,
+0xFFFCFFFF,
+0xFFFAFDFF,
+0xFFFCFFFF,
+0xFFFEFFFF,
+0xFFFCFEFD,
+0xFFFEFFFF,
+0xFFFFFEFF,
+0xFFFEFFFF,
+0xFFFBFCFF,
+0xFFF9FCFF,
+0xFFFCFEFF,
+0xFFF7F9FF,
+0xFFFCFEFF,
+0xFFFCFEFF,
+0xFFFCFBFF,
+0xFFFEFEFF,
+0xFFFBFBFF,
+0xFFFCFDFF,
+0xFFFEFFFF,
+0xFFFEFFFD,
+0xFFFCFFFD,
+0xFFFBFFFA,
+0xFFFEFFFB,
+0xFFFEFFFB,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFB,
+0xFFFEFFFD,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFEFD,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFA,
+0xFFFEFFFA,
+0xFFFEFFFB,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFFFFFB,
+0xFFFFFFFB,
+0xFFFFFFFD,
+0xFFFEFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFD,
+0xFFFFFFFD,
+0xFFFEFFFF,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFEFFFD,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFEFFFD,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFD,
+0xFFFCFFFD,
+0xFFFBFFFF,
+0xFFFCFFFF,
+0xFFFFFEFF,
+0xFFFFFEFD,
+0xFFFFFEFA,
+0xFFFFFEFB,
+0xFFFEFFFF,
+0xFFFCFFFF,
+0xFFFBFFFF,
+0xFFFBFFFF,
+0xFFFEFFFF,
+0xFFFFFEFF,
+0xFFFFFDFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFEFFFD,
+0xFFFCFFFB,
+0xFFFCFFFB,
+0xFFFCFFFD,
+0xFFFEFFFF,
+0xFFFEFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFB,
+0xFFFFFFF8,
+0xFFFFFFFA,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFB,
+0xFFFFFFFB,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFD,
+0xFFFEFFFF,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFEFFFD,
+0xFFFFFFFF,
+0xFFFFFDFF,
+0xFFFFFDFF,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFFFFFA,
+0xFFFFFFFA,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFCFFFF,
+0xFFFEFFFF,
+0xFFFFFEFD,
+0xFFFFFEFB,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFBFF,
+0xFFFFFBFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFDFF,
+0xFFFFFDFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFEFFFD,
+0xFFFCFFFB,
+0xFFFBFFFB,
+0xFFFEFFFB,
+0xFFFFFFF8,
+0xFFFFFEFA,
+0xFFFFFEFD,
+0xFFFFFEFF,
+0xFFFFFDFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFD,
+0xFFFFFFFB,
+0xFFFFFFFA,
+0xFFFFFFFB,
+0xFFFFFEFF,
+0xFFFFFDFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFEFB,
+0xFFFFFFFA,
+0xFFFEFFFF,
+0xFFFCFFFF,
+0xFFFFFDFF,
+0xFFFFFDFF,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFFFFFA,
+0xFFFFFFFB,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFDFF,
+0xFFFFFDFF,
+0xFFFFFEFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFEFFFD,
+0xFFFEFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFEFFFF,
+0xFFFFFDFF,
+0xFFFFFDFF,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFEFFFB,
+0xFFFEFFFB,
+0xFFFEFFFB,
+0xFFFFFFFB,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFEFFF8,
+0xFFFEFFF8,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFEFFFB,
+0xFFFEFFFF,
+0xFFFEFEFF,
+0xFFFCFFFF,
+0xFFFEFFFF,
+0xFFFEFFFB,
+0xFFFEFFFD,
+0xFFFEFFFD,
+0xFFFFFFFB,
+0xFFFFFFFB,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFBFEFF,
+0xFFFAFDFF,
+0xFFFCFFFF,
+0xFFFEFFFF,
+0xFFFCFEFD,
+0xFFFEFFFF,
+0xFFFEFDFF,
+0xFFFFFFFF,
+0xFFFFFFFA,
+0xFFFDFEF8,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFCFBF9,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFDFBFC,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFEFEFC,
+0xFFFEFFFB,
+0xFFFBFFFC,
+0xFFFCFFFB,
+0xFFFEFFFB,
+0xFFFEFFFB,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFEFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFB,
+0xFFFFFFFD,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFB,
+0xFFFEFFFA,
+0xFFFEFFFA,
+0xFFFEFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFFFFFB,
+0xFFFFFFFA,
+0xFFFFFFFB,
+0xFFFEFFFD,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFB,
+0xFFFFFFFB,
+0xFFFEFFFD,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFEFFFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFEFFFD,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFD,
+0xFFFEFFFD,
+0xFFFCFFFF,
+0xFFFCFFFF,
+0xFFFFFFFF,
+0xFFFFFEFB,
+0xFFFFFFFA,
+0xFFFFFFFA,
+0xFFFEFFFF,
+0xFFFCFFFF,
+0xFFFBFFFF,
+0xFFFCFFFF,
+0xFFFEFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFD,
+0xFFFEFFFD,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFEFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFB,
+0xFFFFFFF8,
+0xFFFFFFFA,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFEFFFB,
+0xFFFEFFFB,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFDFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFEFFFD,
+0xFFFCFFFD,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFD,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFDFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFA,
+0xFFFFFFFB,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFD,
+0xFFFEFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFEFFFF,
+0xFFFEFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFEFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFEFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFD,
+0xFFFFFFFD,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF,
+0xFFFFFFFF};
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __LIFE_AUGMENTED_ARGB8888_H */
diff --git a/Core/Inc/ltdc.h b/Core/Inc/ltdc.h
new file mode 100644
index 0000000..8647c27
--- /dev/null
+++ b/Core/Inc/ltdc.h
@@ -0,0 +1,52 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    ltdc.h
+  * @brief   This file contains all the function prototypes for
+  *          the ltdc.c file
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2022 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __LTDC_H__
+#define __LTDC_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+extern LTDC_HandleTypeDef hltdc;
+
+/* USER CODE BEGIN Private defines */
+
+/* USER CODE END Private defines */
+
+void MX_LTDC_Init(void);
+
+/* USER CODE BEGIN Prototypes */
+
+/* USER CODE END Prototypes */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __LTDC_H__ */
+
diff --git a/Core/Inc/main.h b/Core/Inc/main.h
new file mode 100644
index 0000000..ff2ca41
--- /dev/null
+++ b/Core/Inc/main.h
@@ -0,0 +1,268 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file           : main.h
+  * @brief          : Header for main.c file.
+  *                   This file contains the common defines of the application.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2022 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __MAIN_H
+#define __MAIN_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void Error_Handler(void);
+
+/* USER CODE BEGIN EFP */
+
+/* USER CODE END EFP */
+
+/* Private defines -----------------------------------------------------------*/
+#define SAI1_FSA_Pin GPIO_PIN_4
+#define SAI1_FSA_GPIO_Port GPIOE
+#define SPKR_HP_Pin GPIO_PIN_3
+#define SPKR_HP_GPIO_Port GPIOE
+#define AUDIO_RST_Pin GPIO_PIN_2
+#define AUDIO_RST_GPIO_Port GPIOE
+#define ARDUINO_USART6_TX_Pin GPIO_PIN_14
+#define ARDUINO_USART6_TX_GPIO_Port GPIOG
+#define FMC_NBL1_Pin GPIO_PIN_1
+#define FMC_NBL1_GPIO_Port GPIOE
+#define FMC_NBL0_Pin GPIO_PIN_0
+#define FMC_NBL0_GPIO_Port GPIOE
+#define I2C1_SCL_Pin GPIO_PIN_8
+#define I2C1_SCL_GPIO_Port GPIOB
+#define I2S3_CK_Pin GPIO_PIN_3
+#define I2S3_CK_GPIO_Port GPIOB
+#define uSD_CLK_Pin GPIO_PIN_12
+#define uSD_CLK_GPIO_Port GPIOC
+#define SWCLK_Pin GPIO_PIN_14
+#define SWCLK_GPIO_Port GPIOA
+#define SWDIO_Pin GPIO_PIN_13
+#define SWDIO_GPIO_Port GPIOA
+#define SAI1_SCKA_Pin GPIO_PIN_5
+#define SAI1_SCKA_GPIO_Port GPIOE
+#define I2C1_SDA_Pin GPIO_PIN_9
+#define I2C1_SDA_GPIO_Port GPIOB
+#define OTG_FS1_OverCurrent_Pin GPIO_PIN_7
+#define OTG_FS1_OverCurrent_GPIO_Port GPIOB
+#define QSPI_BK1_NCS_Pin GPIO_PIN_6
+#define QSPI_BK1_NCS_GPIO_Port GPIOB
+#define SDNCAS_Pin GPIO_PIN_15
+#define SDNCAS_GPIO_Port GPIOG
+#define MIC_DATA_Pin GPIO_PIN_6
+#define MIC_DATA_GPIO_Port GPIOD
+#define D2_Pin GPIO_PIN_0
+#define D2_GPIO_Port GPIOD
+#define uSD_D3_Pin GPIO_PIN_11
+#define uSD_D3_GPIO_Port GPIOC
+#define uSD_D2_Pin GPIO_PIN_10
+#define uSD_D2_GPIO_Port GPIOC
+#define USB_FS1_P_Pin GPIO_PIN_12
+#define USB_FS1_P_GPIO_Port GPIOA
+#define FMC_NBL2_Pin GPIO_PIN_4
+#define FMC_NBL2_GPIO_Port GPIOI
+#define LED3_Pin GPIO_PIN_5
+#define LED3_GPIO_Port GPIOD
+#define D3_Pin GPIO_PIN_1
+#define D3_GPIO_Port GPIOD
+#define D27_Pin GPIO_PIN_3
+#define D27_GPIO_Port GPIOI
+#define D26_Pin GPIO_PIN_2
+#define D26_GPIO_Port GPIOI
+#define USB_FS1_N_Pin GPIO_PIN_11
+#define USB_FS1_N_GPIO_Port GPIOA
+#define A0_Pin GPIO_PIN_0
+#define A0_GPIO_Port GPIOF
+#define FMC_NBL3_Pin GPIO_PIN_5
+#define FMC_NBL3_GPIO_Port GPIOI
+#define D29_Pin GPIO_PIN_7
+#define D29_GPIO_Port GPIOI
+#define D31_Pin GPIO_PIN_10
+#define D31_GPIO_Port GPIOI
+#define D28_Pin GPIO_PIN_6
+#define D28_GPIO_Port GPIOI
+#define LED4_Pin GPIO_PIN_3
+#define LED4_GPIO_Port GPIOK
+#define USART6_RX_Pin GPIO_PIN_9
+#define USART6_RX_GPIO_Port GPIOG
+#define LED2_Pin GPIO_PIN_4
+#define LED2_GPIO_Port GPIOD
+#define uSD_CMD_Pin GPIO_PIN_2
+#define uSD_CMD_GPIO_Port GPIOD
+#define D23_Pin GPIO_PIN_15
+#define D23_GPIO_Port GPIOH
+#define D25_Pin GPIO_PIN_1
+#define D25_GPIO_Port GPIOI
+#define USB_FS1_ID_Pin GPIO_PIN_10
+#define USB_FS1_ID_GPIO_Port GPIOA
+#define A1_Pin GPIO_PIN_1
+#define A1_GPIO_Port GPIOF
+#define D30_Pin GPIO_PIN_9
+#define D30_GPIO_Port GPIOI
+#define D21_Pin GPIO_PIN_13
+#define D21_GPIO_Port GPIOH
+#define D22_Pin GPIO_PIN_14
+#define D22_GPIO_Port GPIOH
+#define D24_Pin GPIO_PIN_0
+#define D24_GPIO_Port GPIOI
+#define VBUS_FS1_Pin GPIO_PIN_9
+#define VBUS_FS1_GPIO_Port GPIOA
+#define uSD_D1_Pin GPIO_PIN_9
+#define uSD_D1_GPIO_Port GPIOC
+#define A2_Pin GPIO_PIN_2
+#define A2_GPIO_Port GPIOF
+#define uSD_D0_Pin GPIO_PIN_8
+#define uSD_D0_GPIO_Port GPIOC
+#define A3_Pin GPIO_PIN_3
+#define A3_GPIO_Port GPIOF
+#define I2C2_SCL_Pin GPIO_PIN_4
+#define I2C2_SCL_GPIO_Port GPIOH
+#define SDCLK_Pin GPIO_PIN_8
+#define SDCLK_GPIO_Port GPIOG
+#define A4_Pin GPIO_PIN_4
+#define A4_GPIO_Port GPIOF
+#define I2C2_SDA_Pin GPIO_PIN_5
+#define I2C2_SDA_GPIO_Port GPIOH
+#define SDNE0_Pin GPIO_PIN_3
+#define SDNE0_GPIO_Port GPIOH
+#define SAI1_MCLKA_Pin GPIO_PIN_7
+#define SAI1_MCLKA_GPIO_Port GPIOG
+#define LED1_Pin GPIO_PIN_6
+#define LED1_GPIO_Port GPIOG
+#define QSPI_BK1_IO2_Pin GPIO_PIN_7
+#define QSPI_BK1_IO2_GPIO_Port GPIOF
+#define QSPI_BK1_IO3_Pin GPIO_PIN_6
+#define QSPI_BK1_IO3_GPIO_Port GPIOF
+#define A5_Pin GPIO_PIN_5
+#define A5_GPIO_Port GPIOF
+#define SDCKE0_Pin GPIO_PIN_2
+#define SDCKE0_GPIO_Port GPIOH
+#define D1_Pin GPIO_PIN_15
+#define D1_GPIO_Port GPIOD
+#define D15_Pin GPIO_PIN_10
+#define D15_GPIO_Port GPIOD
+#define QSPI_CLK_Pin GPIO_PIN_10
+#define QSPI_CLK_GPIO_Port GPIOF
+#define QSPI_BK1_IO1_Pin GPIO_PIN_9
+#define QSPI_BK1_IO1_GPIO_Port GPIOF
+#define QSPI_BK1_IO0_Pin GPIO_PIN_8
+#define QSPI_BK1_IO0_GPIO_Port GPIOF
+#define D0_Pin GPIO_PIN_14
+#define D0_GPIO_Port GPIOD
+#define D14_Pin GPIO_PIN_9
+#define D14_GPIO_Port GPIOD
+#define D13_Pin GPIO_PIN_8
+#define D13_GPIO_Port GPIOD
+#define SDNWE_Pin GPIO_PIN_0
+#define SDNWE_GPIO_Port GPIOC
+#define OTG_FS1_PowerSwitchOn_Pin GPIO_PIN_2
+#define OTG_FS1_PowerSwitchOn_GPIO_Port GPIOB
+#define A6_Pin GPIO_PIN_12
+#define A6_GPIO_Port GPIOF
+#define A11_Pin GPIO_PIN_1
+#define A11_GPIO_Port GPIOG
+#define A9_Pin GPIO_PIN_15
+#define A9_GPIO_Port GPIOF
+#define MIC_CK_Pin GPIO_PIN_13
+#define MIC_CK_GPIO_Port GPIOD
+#define uSD_Detect_Pin GPIO_PIN_2
+#define uSD_Detect_GPIO_Port GPIOG
+#define LCD_INT_Pin GPIO_PIN_5
+#define LCD_INT_GPIO_Port GPIOJ
+#define D20_Pin GPIO_PIN_12
+#define D20_GPIO_Port GPIOH
+#define WAKEUP_Pin GPIO_PIN_0
+#define WAKEUP_GPIO_Port GPIOA
+#define A7_Pin GPIO_PIN_13
+#define A7_GPIO_Port GPIOF
+#define A10_Pin GPIO_PIN_0
+#define A10_GPIO_Port GPIOG
+#define D5_Pin GPIO_PIN_8
+#define D5_GPIO_Port GPIOE
+#define D17_Pin GPIO_PIN_9
+#define D17_GPIO_Port GPIOH
+#define D19_Pin GPIO_PIN_11
+#define D19_GPIO_Port GPIOH
+#define A8_Pin GPIO_PIN_14
+#define A8_GPIO_Port GPIOF
+#define DSI_TE_Pin GPIO_PIN_2
+#define DSI_TE_GPIO_Port GPIOJ
+#define SDNMT48LC4M32B2B5_6A_RAS_RAS___Pin GPIO_PIN_11
+#define SDNMT48LC4M32B2B5_6A_RAS_RAS___GPIO_Port GPIOF
+#define D6_Pin GPIO_PIN_9
+#define D6_GPIO_Port GPIOE
+#define D8_Pin GPIO_PIN_11
+#define D8_GPIO_Port GPIOE
+#define D11_Pin GPIO_PIN_14
+#define D11_GPIO_Port GPIOE
+#define STLK_RX_Pin GPIO_PIN_10
+#define STLK_RX_GPIO_Port GPIOB
+#define D16_Pin GPIO_PIN_8
+#define D16_GPIO_Port GPIOH
+#define D18_Pin GPIO_PIN_10
+#define D18_GPIO_Port GPIOH
+#define LCD_BL_CTRL_Pin GPIO_PIN_3
+#define LCD_BL_CTRL_GPIO_Port GPIOA
+#define EXT_RESET_Pin GPIO_PIN_0
+#define EXT_RESET_GPIO_Port GPIOB
+#define D4_Pin GPIO_PIN_7
+#define D4_GPIO_Port GPIOE
+#define D7_Pin GPIO_PIN_10
+#define D7_GPIO_Port GPIOE
+#define D9_Pin GPIO_PIN_12
+#define D9_GPIO_Port GPIOE
+#define D12_Pin GPIO_PIN_15
+#define D12_GPIO_Port GPIOE
+#define D10_Pin GPIO_PIN_13
+#define D10_GPIO_Port GPIOE
+#define STLK_TX_Pin GPIO_PIN_11
+#define STLK_TX_GPIO_Port GPIOB
+/* USER CODE BEGIN Private defines */
+
+/* USER CODE END Private defines */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __MAIN_H */
diff --git a/Core/Inc/my_lcd.h b/Core/Inc/my_lcd.h
new file mode 100644
index 0000000..567ba73
--- /dev/null
+++ b/Core/Inc/my_lcd.h
@@ -0,0 +1,4 @@
+void My_SystemClock_Config(void);
+
+void MY_LCD_Init();
+void MY_LCD_Tick();
diff --git a/Core/Inc/quadspi.h b/Core/Inc/quadspi.h
new file mode 100644
index 0000000..1aade85
--- /dev/null
+++ b/Core/Inc/quadspi.h
@@ -0,0 +1,52 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    quadspi.h
+  * @brief   This file contains all the function prototypes for
+  *          the quadspi.c file
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2022 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __QUADSPI_H__
+#define __QUADSPI_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+extern QSPI_HandleTypeDef hqspi;
+
+/* USER CODE BEGIN Private defines */
+
+/* USER CODE END Private defines */
+
+void MX_QUADSPI_Init(void);
+
+/* USER CODE BEGIN Prototypes */
+
+/* USER CODE END Prototypes */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __QUADSPI_H__ */
+
diff --git a/Core/Inc/sai.h b/Core/Inc/sai.h
new file mode 100644
index 0000000..a579631
--- /dev/null
+++ b/Core/Inc/sai.h
@@ -0,0 +1,52 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    sai.h
+  * @brief   This file contains all the function prototypes for
+  *          the sai.c file
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2022 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __SAI_H__
+#define __SAI_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+extern SAI_HandleTypeDef hsai_BlockA1;
+
+/* USER CODE BEGIN Private defines */
+
+/* USER CODE END Private defines */
+
+void MX_SAI1_Init(void);
+
+/* USER CODE BEGIN Prototypes */
+
+/* USER CODE END Prototypes */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __SAI_H__ */
+
diff --git a/Core/Inc/sdio.h b/Core/Inc/sdio.h
new file mode 100644
index 0000000..648b317
--- /dev/null
+++ b/Core/Inc/sdio.h
@@ -0,0 +1,52 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    sdio.h
+  * @brief   This file contains all the function prototypes for
+  *          the sdio.c file
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2022 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __SDIO_H__
+#define __SDIO_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+extern SD_HandleTypeDef hsd;
+
+/* USER CODE BEGIN Private defines */
+
+/* USER CODE END Private defines */
+
+void MX_SDIO_SD_Init(void);
+
+/* USER CODE BEGIN Prototypes */
+
+/* USER CODE END Prototypes */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __SDIO_H__ */
+
diff --git a/Core/Inc/stm32f4xx_hal_conf.h b/Core/Inc/stm32f4xx_hal_conf.h
new file mode 100644
index 0000000..444c911
--- /dev/null
+++ b/Core/Inc/stm32f4xx_hal_conf.h
@@ -0,0 +1,491 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hal_conf_template.h
+  * @author  MCD Application Team
+  * @brief   HAL configuration template file.
+  *          This file should be copied to the application folder and renamed
+  *          to stm32f4xx_hal_conf.h.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_CONF_H
+#define __STM32F4xx_HAL_CONF_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/* ########################## Module Selection ############################## */
+/**
+  * @brief This is the list of modules to be used in the HAL driver
+  */
+#define HAL_MODULE_ENABLED
+
+  /* #define HAL_ADC_MODULE_ENABLED   */
+/* #define HAL_CRYP_MODULE_ENABLED   */
+/* #define HAL_CAN_MODULE_ENABLED   */
+#define HAL_CRC_MODULE_ENABLED
+/* #define HAL_CAN_LEGACY_MODULE_ENABLED   */
+/* #define HAL_CRYP_MODULE_ENABLED   */
+/* #define HAL_DAC_MODULE_ENABLED   */
+/* #define HAL_DCMI_MODULE_ENABLED   */
+#define HAL_DMA2D_MODULE_ENABLED
+/* #define HAL_ETH_MODULE_ENABLED   */
+/* #define HAL_NAND_MODULE_ENABLED   */
+/* #define HAL_NOR_MODULE_ENABLED   */
+/* #define HAL_PCCARD_MODULE_ENABLED   */
+/* #define HAL_SRAM_MODULE_ENABLED   */
+#define HAL_SDRAM_MODULE_ENABLED
+/* #define HAL_HASH_MODULE_ENABLED   */
+#define HAL_I2C_MODULE_ENABLED
+/* #define HAL_I2S_MODULE_ENABLED   */
+/* #define HAL_IWDG_MODULE_ENABLED   */
+#define HAL_LTDC_MODULE_ENABLED
+/* #define HAL_RNG_MODULE_ENABLED   */
+/* #define HAL_RTC_MODULE_ENABLED   */
+#define HAL_SAI_MODULE_ENABLED
+#define HAL_SD_MODULE_ENABLED
+/* #define HAL_MMC_MODULE_ENABLED   */
+/* #define HAL_SPI_MODULE_ENABLED   */
+#define HAL_TIM_MODULE_ENABLED
+#define HAL_UART_MODULE_ENABLED
+/* #define HAL_USART_MODULE_ENABLED   */
+/* #define HAL_IRDA_MODULE_ENABLED   */
+/* #define HAL_SMARTCARD_MODULE_ENABLED   */
+/* #define HAL_SMBUS_MODULE_ENABLED   */
+/* #define HAL_WWDG_MODULE_ENABLED   */
+/* #define HAL_PCD_MODULE_ENABLED   */
+#define HAL_HCD_MODULE_ENABLED
+#define HAL_DSI_MODULE_ENABLED
+/* #define HAL_QSPI_MODULE_ENABLED   */
+#define HAL_QSPI_MODULE_ENABLED
+/* #define HAL_CEC_MODULE_ENABLED   */
+/* #define HAL_FMPI2C_MODULE_ENABLED   */
+/* #define HAL_FMPSMBUS_MODULE_ENABLED   */
+/* #define HAL_SPDIFRX_MODULE_ENABLED   */
+/* #define HAL_DFSDM_MODULE_ENABLED   */
+/* #define HAL_LPTIM_MODULE_ENABLED   */
+#define HAL_GPIO_MODULE_ENABLED
+#define HAL_EXTI_MODULE_ENABLED
+#define HAL_DMA_MODULE_ENABLED
+#define HAL_RCC_MODULE_ENABLED
+#define HAL_FLASH_MODULE_ENABLED
+#define HAL_PWR_MODULE_ENABLED
+#define HAL_CORTEX_MODULE_ENABLED
+
+/* ########################## HSE/HSI Values adaptation ##################### */
+/**
+  * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSE is used as system clock source, directly or through the PLL).
+  */
+#if !defined  (HSE_VALUE)
+  #define HSE_VALUE    8000000U /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (HSE_STARTUP_TIMEOUT)
+  #define HSE_STARTUP_TIMEOUT    100U   /*!< Time out for HSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief Internal High Speed oscillator (HSI) value.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSI is used as system clock source, directly or through the PLL).
+  */
+#if !defined  (HSI_VALUE)
+  #define HSI_VALUE    ((uint32_t)16000000U) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+/**
+  * @brief Internal Low Speed oscillator (LSI) value.
+  */
+#if !defined  (LSI_VALUE)
+ #define LSI_VALUE  32000U       /*!< LSI Typical Value in Hz*/
+#endif /* LSI_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
+                                             The real value may vary depending on the variations
+                                             in voltage and temperature.*/
+/**
+  * @brief External Low Speed oscillator (LSE) value.
+  */
+#if !defined  (LSE_VALUE)
+ #define LSE_VALUE  32768U    /*!< Value of the External Low Speed oscillator in Hz */
+#endif /* LSE_VALUE */
+
+#if !defined  (LSE_STARTUP_TIMEOUT)
+  #define LSE_STARTUP_TIMEOUT    5000U   /*!< Time out for LSE start up, in ms */
+#endif /* LSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief External clock source for I2S peripheral
+  *        This value is used by the I2S HAL module to compute the I2S clock source
+  *        frequency, this source is inserted directly through I2S_CKIN pad.
+  */
+#if !defined  (EXTERNAL_CLOCK_VALUE)
+  #define EXTERNAL_CLOCK_VALUE    12288000U /*!< Value of the External audio frequency in Hz*/
+#endif /* EXTERNAL_CLOCK_VALUE */
+
+/* Tip: To avoid modifying this file each time you need to use different HSE,
+   ===  you can define the HSE value in your toolchain compiler preprocessor. */
+
+/* ########################### System Configuration ######################### */
+/**
+  * @brief This is the HAL system configuration section
+  */
+#define  VDD_VALUE		      3300U /*!< Value of VDD in mv */
+#define  TICK_INT_PRIORITY            0U   /*!< tick interrupt priority */
+#define  USE_RTOS                     0U
+#define  PREFETCH_ENABLE              1U
+#define  INSTRUCTION_CACHE_ENABLE     1U
+#define  DATA_CACHE_ENABLE            1U
+
+#define  USE_HAL_ADC_REGISTER_CALLBACKS         0U /* ADC register callback disabled       */
+#define  USE_HAL_CAN_REGISTER_CALLBACKS         0U /* CAN register callback disabled       */
+#define  USE_HAL_CEC_REGISTER_CALLBACKS         0U /* CEC register callback disabled       */
+#define  USE_HAL_CRYP_REGISTER_CALLBACKS        0U /* CRYP register callback disabled      */
+#define  USE_HAL_DAC_REGISTER_CALLBACKS         0U /* DAC register callback disabled       */
+#define  USE_HAL_DCMI_REGISTER_CALLBACKS        0U /* DCMI register callback disabled      */
+#define  USE_HAL_DFSDM_REGISTER_CALLBACKS       0U /* DFSDM register callback disabled     */
+#define  USE_HAL_DMA2D_REGISTER_CALLBACKS       0U /* DMA2D register callback disabled     */
+#define  USE_HAL_DSI_REGISTER_CALLBACKS         0U /* DSI register callback disabled       */
+#define  USE_HAL_ETH_REGISTER_CALLBACKS         0U /* ETH register callback disabled       */
+#define  USE_HAL_HASH_REGISTER_CALLBACKS        0U /* HASH register callback disabled      */
+#define  USE_HAL_HCD_REGISTER_CALLBACKS         0U /* HCD register callback disabled       */
+#define  USE_HAL_I2C_REGISTER_CALLBACKS         0U /* I2C register callback disabled       */
+#define  USE_HAL_FMPI2C_REGISTER_CALLBACKS      0U /* FMPI2C register callback disabled    */
+#define  USE_HAL_FMPSMBUS_REGISTER_CALLBACKS    0U /* FMPSMBUS register callback disabled  */
+#define  USE_HAL_I2S_REGISTER_CALLBACKS         0U /* I2S register callback disabled       */
+#define  USE_HAL_IRDA_REGISTER_CALLBACKS        0U /* IRDA register callback disabled      */
+#define  USE_HAL_LPTIM_REGISTER_CALLBACKS       0U /* LPTIM register callback disabled     */
+#define  USE_HAL_LTDC_REGISTER_CALLBACKS        0U /* LTDC register callback disabled      */
+#define  USE_HAL_MMC_REGISTER_CALLBACKS         0U /* MMC register callback disabled       */
+#define  USE_HAL_NAND_REGISTER_CALLBACKS        0U /* NAND register callback disabled      */
+#define  USE_HAL_NOR_REGISTER_CALLBACKS         0U /* NOR register callback disabled       */
+#define  USE_HAL_PCCARD_REGISTER_CALLBACKS      0U /* PCCARD register callback disabled    */
+#define  USE_HAL_PCD_REGISTER_CALLBACKS         0U /* PCD register callback disabled       */
+#define  USE_HAL_QSPI_REGISTER_CALLBACKS        0U /* QSPI register callback disabled      */
+#define  USE_HAL_RNG_REGISTER_CALLBACKS         0U /* RNG register callback disabled       */
+#define  USE_HAL_RTC_REGISTER_CALLBACKS         0U /* RTC register callback disabled       */
+#define  USE_HAL_SAI_REGISTER_CALLBACKS         0U /* SAI register callback disabled       */
+#define  USE_HAL_SD_REGISTER_CALLBACKS          0U /* SD register callback disabled        */
+#define  USE_HAL_SMARTCARD_REGISTER_CALLBACKS   0U /* SMARTCARD register callback disabled */
+#define  USE_HAL_SDRAM_REGISTER_CALLBACKS       0U /* SDRAM register callback disabled     */
+#define  USE_HAL_SRAM_REGISTER_CALLBACKS        0U /* SRAM register callback disabled      */
+#define  USE_HAL_SPDIFRX_REGISTER_CALLBACKS     0U /* SPDIFRX register callback disabled   */
+#define  USE_HAL_SMBUS_REGISTER_CALLBACKS       0U /* SMBUS register callback disabled     */
+#define  USE_HAL_SPI_REGISTER_CALLBACKS         0U /* SPI register callback disabled       */
+#define  USE_HAL_TIM_REGISTER_CALLBACKS         0U /* TIM register callback disabled       */
+#define  USE_HAL_UART_REGISTER_CALLBACKS        0U /* UART register callback disabled      */
+#define  USE_HAL_USART_REGISTER_CALLBACKS       0U /* USART register callback disabled     */
+#define  USE_HAL_WWDG_REGISTER_CALLBACKS        0U /* WWDG register callback disabled      */
+
+/* ########################## Assert Selection ############################## */
+/**
+  * @brief Uncomment the line below to expanse the "assert_param" macro in the
+  *        HAL drivers code
+  */
+/* #define USE_FULL_ASSERT    1U */
+
+/* ################## Ethernet peripheral configuration ##################### */
+
+/* Section 1 : Ethernet peripheral configuration */
+
+/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */
+#define MAC_ADDR0   2U
+#define MAC_ADDR1   0U
+#define MAC_ADDR2   0U
+#define MAC_ADDR3   0U
+#define MAC_ADDR4   0U
+#define MAC_ADDR5   0U
+
+/* Definition of the Ethernet driver buffers size and count */
+#define ETH_RX_BUF_SIZE                ETH_MAX_PACKET_SIZE /* buffer size for receive               */
+#define ETH_TX_BUF_SIZE                ETH_MAX_PACKET_SIZE /* buffer size for transmit              */
+#define ETH_RXBUFNB                    4U       /* 4 Rx buffers of size ETH_RX_BUF_SIZE  */
+#define ETH_TXBUFNB                    4U       /* 4 Tx buffers of size ETH_TX_BUF_SIZE  */
+
+/* Section 2: PHY configuration section */
+
+/* DP83848_PHY_ADDRESS Address*/
+#define DP83848_PHY_ADDRESS           0x01U
+/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/
+#define PHY_RESET_DELAY                 0x000000FFU
+/* PHY Configuration delay */
+#define PHY_CONFIG_DELAY                0x00000FFFU
+
+#define PHY_READ_TO                     0x0000FFFFU
+#define PHY_WRITE_TO                    0x0000FFFFU
+
+/* Section 3: Common PHY Registers */
+
+#define PHY_BCR                         ((uint16_t)0x0000U)    /*!< Transceiver Basic Control Register   */
+#define PHY_BSR                         ((uint16_t)0x0001U)    /*!< Transceiver Basic Status Register    */
+
+#define PHY_RESET                       ((uint16_t)0x8000U)  /*!< PHY Reset */
+#define PHY_LOOPBACK                    ((uint16_t)0x4000U)  /*!< Select loop-back mode */
+#define PHY_FULLDUPLEX_100M             ((uint16_t)0x2100U)  /*!< Set the full-duplex mode at 100 Mb/s */
+#define PHY_HALFDUPLEX_100M             ((uint16_t)0x2000U)  /*!< Set the half-duplex mode at 100 Mb/s */
+#define PHY_FULLDUPLEX_10M              ((uint16_t)0x0100U)  /*!< Set the full-duplex mode at 10 Mb/s  */
+#define PHY_HALFDUPLEX_10M              ((uint16_t)0x0000U)  /*!< Set the half-duplex mode at 10 Mb/s  */
+#define PHY_AUTONEGOTIATION             ((uint16_t)0x1000U)  /*!< Enable auto-negotiation function     */
+#define PHY_RESTART_AUTONEGOTIATION     ((uint16_t)0x0200U)  /*!< Restart auto-negotiation function    */
+#define PHY_POWERDOWN                   ((uint16_t)0x0800U)  /*!< Select the power down mode           */
+#define PHY_ISOLATE                     ((uint16_t)0x0400U)  /*!< Isolate PHY from MII                 */
+
+#define PHY_AUTONEGO_COMPLETE           ((uint16_t)0x0020U)  /*!< Auto-Negotiation process completed   */
+#define PHY_LINKED_STATUS               ((uint16_t)0x0004U)  /*!< Valid link established               */
+#define PHY_JABBER_DETECTION            ((uint16_t)0x0002U)  /*!< Jabber condition detected            */
+
+/* Section 4: Extended PHY Registers */
+#define PHY_SR                          ((uint16_t)0x10U)    /*!< PHY status register Offset                      */
+
+#define PHY_SPEED_STATUS                ((uint16_t)0x0002U)  /*!< PHY Speed mask                                  */
+#define PHY_DUPLEX_STATUS               ((uint16_t)0x0004U)  /*!< PHY Duplex mask                                 */
+
+/* ################## SPI peripheral configuration ########################## */
+
+/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
+* Activated: CRC code is present inside driver
+* Deactivated: CRC code cleaned from driver
+*/
+
+#define USE_SPI_CRC                     0U
+
+/* Includes ------------------------------------------------------------------*/
+/**
+  * @brief Include module's header file
+  */
+
+#ifdef HAL_RCC_MODULE_ENABLED
+  #include "stm32f4xx_hal_rcc.h"
+#endif /* HAL_RCC_MODULE_ENABLED */
+
+#ifdef HAL_GPIO_MODULE_ENABLED
+  #include "stm32f4xx_hal_gpio.h"
+#endif /* HAL_GPIO_MODULE_ENABLED */
+
+#ifdef HAL_EXTI_MODULE_ENABLED
+  #include "stm32f4xx_hal_exti.h"
+#endif /* HAL_EXTI_MODULE_ENABLED */
+
+#ifdef HAL_DMA_MODULE_ENABLED
+  #include "stm32f4xx_hal_dma.h"
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+#ifdef HAL_CORTEX_MODULE_ENABLED
+  #include "stm32f4xx_hal_cortex.h"
+#endif /* HAL_CORTEX_MODULE_ENABLED */
+
+#ifdef HAL_ADC_MODULE_ENABLED
+  #include "stm32f4xx_hal_adc.h"
+#endif /* HAL_ADC_MODULE_ENABLED */
+
+#ifdef HAL_CAN_MODULE_ENABLED
+  #include "stm32f4xx_hal_can.h"
+#endif /* HAL_CAN_MODULE_ENABLED */
+
+#ifdef HAL_CAN_LEGACY_MODULE_ENABLED
+  #include "stm32f4xx_hal_can_legacy.h"
+#endif /* HAL_CAN_LEGACY_MODULE_ENABLED */
+
+#ifdef HAL_CRC_MODULE_ENABLED
+  #include "stm32f4xx_hal_crc.h"
+#endif /* HAL_CRC_MODULE_ENABLED */
+
+#ifdef HAL_CRYP_MODULE_ENABLED
+  #include "stm32f4xx_hal_cryp.h"
+#endif /* HAL_CRYP_MODULE_ENABLED */
+
+#ifdef HAL_DMA2D_MODULE_ENABLED
+  #include "stm32f4xx_hal_dma2d.h"
+#endif /* HAL_DMA2D_MODULE_ENABLED */
+
+#ifdef HAL_DAC_MODULE_ENABLED
+  #include "stm32f4xx_hal_dac.h"
+#endif /* HAL_DAC_MODULE_ENABLED */
+
+#ifdef HAL_DCMI_MODULE_ENABLED
+  #include "stm32f4xx_hal_dcmi.h"
+#endif /* HAL_DCMI_MODULE_ENABLED */
+
+#ifdef HAL_ETH_MODULE_ENABLED
+  #include "stm32f4xx_hal_eth.h"
+#endif /* HAL_ETH_MODULE_ENABLED */
+
+#ifdef HAL_FLASH_MODULE_ENABLED
+  #include "stm32f4xx_hal_flash.h"
+#endif /* HAL_FLASH_MODULE_ENABLED */
+
+#ifdef HAL_SRAM_MODULE_ENABLED
+  #include "stm32f4xx_hal_sram.h"
+#endif /* HAL_SRAM_MODULE_ENABLED */
+
+#ifdef HAL_NOR_MODULE_ENABLED
+  #include "stm32f4xx_hal_nor.h"
+#endif /* HAL_NOR_MODULE_ENABLED */
+
+#ifdef HAL_NAND_MODULE_ENABLED
+  #include "stm32f4xx_hal_nand.h"
+#endif /* HAL_NAND_MODULE_ENABLED */
+
+#ifdef HAL_PCCARD_MODULE_ENABLED
+  #include "stm32f4xx_hal_pccard.h"
+#endif /* HAL_PCCARD_MODULE_ENABLED */
+
+#ifdef HAL_SDRAM_MODULE_ENABLED
+  #include "stm32f4xx_hal_sdram.h"
+#endif /* HAL_SDRAM_MODULE_ENABLED */
+
+#ifdef HAL_HASH_MODULE_ENABLED
+ #include "stm32f4xx_hal_hash.h"
+#endif /* HAL_HASH_MODULE_ENABLED */
+
+#ifdef HAL_I2C_MODULE_ENABLED
+ #include "stm32f4xx_hal_i2c.h"
+#endif /* HAL_I2C_MODULE_ENABLED */
+
+#ifdef HAL_SMBUS_MODULE_ENABLED
+ #include "stm32f4xx_hal_smbus.h"
+#endif /* HAL_SMBUS_MODULE_ENABLED */
+
+#ifdef HAL_I2S_MODULE_ENABLED
+ #include "stm32f4xx_hal_i2s.h"
+#endif /* HAL_I2S_MODULE_ENABLED */
+
+#ifdef HAL_IWDG_MODULE_ENABLED
+ #include "stm32f4xx_hal_iwdg.h"
+#endif /* HAL_IWDG_MODULE_ENABLED */
+
+#ifdef HAL_LTDC_MODULE_ENABLED
+ #include "stm32f4xx_hal_ltdc.h"
+#endif /* HAL_LTDC_MODULE_ENABLED */
+
+#ifdef HAL_PWR_MODULE_ENABLED
+ #include "stm32f4xx_hal_pwr.h"
+#endif /* HAL_PWR_MODULE_ENABLED */
+
+#ifdef HAL_RNG_MODULE_ENABLED
+ #include "stm32f4xx_hal_rng.h"
+#endif /* HAL_RNG_MODULE_ENABLED */
+
+#ifdef HAL_RTC_MODULE_ENABLED
+ #include "stm32f4xx_hal_rtc.h"
+#endif /* HAL_RTC_MODULE_ENABLED */
+
+#ifdef HAL_SAI_MODULE_ENABLED
+ #include "stm32f4xx_hal_sai.h"
+#endif /* HAL_SAI_MODULE_ENABLED */
+
+#ifdef HAL_SD_MODULE_ENABLED
+ #include "stm32f4xx_hal_sd.h"
+#endif /* HAL_SD_MODULE_ENABLED */
+
+#ifdef HAL_SPI_MODULE_ENABLED
+ #include "stm32f4xx_hal_spi.h"
+#endif /* HAL_SPI_MODULE_ENABLED */
+
+#ifdef HAL_TIM_MODULE_ENABLED
+ #include "stm32f4xx_hal_tim.h"
+#endif /* HAL_TIM_MODULE_ENABLED */
+
+#ifdef HAL_UART_MODULE_ENABLED
+ #include "stm32f4xx_hal_uart.h"
+#endif /* HAL_UART_MODULE_ENABLED */
+
+#ifdef HAL_USART_MODULE_ENABLED
+ #include "stm32f4xx_hal_usart.h"
+#endif /* HAL_USART_MODULE_ENABLED */
+
+#ifdef HAL_IRDA_MODULE_ENABLED
+ #include "stm32f4xx_hal_irda.h"
+#endif /* HAL_IRDA_MODULE_ENABLED */
+
+#ifdef HAL_SMARTCARD_MODULE_ENABLED
+ #include "stm32f4xx_hal_smartcard.h"
+#endif /* HAL_SMARTCARD_MODULE_ENABLED */
+
+#ifdef HAL_WWDG_MODULE_ENABLED
+ #include "stm32f4xx_hal_wwdg.h"
+#endif /* HAL_WWDG_MODULE_ENABLED */
+
+#ifdef HAL_PCD_MODULE_ENABLED
+ #include "stm32f4xx_hal_pcd.h"
+#endif /* HAL_PCD_MODULE_ENABLED */
+
+#ifdef HAL_HCD_MODULE_ENABLED
+ #include "stm32f4xx_hal_hcd.h"
+#endif /* HAL_HCD_MODULE_ENABLED */
+
+#ifdef HAL_DSI_MODULE_ENABLED
+ #include "stm32f4xx_hal_dsi.h"
+#endif /* HAL_DSI_MODULE_ENABLED */
+
+#ifdef HAL_QSPI_MODULE_ENABLED
+ #include "stm32f4xx_hal_qspi.h"
+#endif /* HAL_QSPI_MODULE_ENABLED */
+
+#ifdef HAL_CEC_MODULE_ENABLED
+ #include "stm32f4xx_hal_cec.h"
+#endif /* HAL_CEC_MODULE_ENABLED */
+
+#ifdef HAL_FMPI2C_MODULE_ENABLED
+ #include "stm32f4xx_hal_fmpi2c.h"
+#endif /* HAL_FMPI2C_MODULE_ENABLED */
+
+#ifdef HAL_FMPSMBUS_MODULE_ENABLED
+ #include "stm32f4xx_hal_fmpsmbus.h"
+#endif /* HAL_FMPSMBUS_MODULE_ENABLED */
+
+#ifdef HAL_SPDIFRX_MODULE_ENABLED
+ #include "stm32f4xx_hal_spdifrx.h"
+#endif /* HAL_SPDIFRX_MODULE_ENABLED */
+
+#ifdef HAL_DFSDM_MODULE_ENABLED
+ #include "stm32f4xx_hal_dfsdm.h"
+#endif /* HAL_DFSDM_MODULE_ENABLED */
+
+#ifdef HAL_LPTIM_MODULE_ENABLED
+ #include "stm32f4xx_hal_lptim.h"
+#endif /* HAL_LPTIM_MODULE_ENABLED */
+
+#ifdef HAL_MMC_MODULE_ENABLED
+ #include "stm32f4xx_hal_mmc.h"
+#endif /* HAL_MMC_MODULE_ENABLED */
+
+/* Exported macro ------------------------------------------------------------*/
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  The assert_param macro is used for function's parameters check.
+  * @param  expr If expr is false, it calls assert_failed function
+  *         which reports the name of the source file and the source
+  *         line number of the call that failed.
+  *         If expr is true, it returns no value.
+  * @retval None
+  */
+  #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+  void assert_failed(uint8_t* file, uint32_t line);
+#else
+  #define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_CONF_H */
diff --git a/Core/Inc/stm32f4xx_it.h b/Core/Inc/stm32f4xx_it.h
new file mode 100644
index 0000000..8640da9
--- /dev/null
+++ b/Core/Inc/stm32f4xx_it.h
@@ -0,0 +1,68 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_it.h
+  * @brief   This file contains the headers of the interrupt handlers.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2022 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+ ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_IT_H
+#define __STM32F4xx_IT_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void NMI_Handler(void);
+void HardFault_Handler(void);
+void MemManage_Handler(void);
+void BusFault_Handler(void);
+void UsageFault_Handler(void);
+void DebugMon_Handler(void);
+void TIM6_DAC_IRQHandler(void);
+void OTG_FS_IRQHandler(void);
+void LTDC_IRQHandler(void);
+void DMA2D_IRQHandler(void);
+void DSI_IRQHandler(void);
+/* USER CODE BEGIN EFP */
+
+/* USER CODE END EFP */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_IT_H */
diff --git a/Core/Inc/tim.h b/Core/Inc/tim.h
new file mode 100644
index 0000000..9e5f239
--- /dev/null
+++ b/Core/Inc/tim.h
@@ -0,0 +1,52 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    tim.h
+  * @brief   This file contains all the function prototypes for
+  *          the tim.c file
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2022 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __TIM_H__
+#define __TIM_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+extern TIM_HandleTypeDef htim1;
+
+/* USER CODE BEGIN Private defines */
+
+/* USER CODE END Private defines */
+
+void MX_TIM1_Init(void);
+
+/* USER CODE BEGIN Prototypes */
+
+/* USER CODE END Prototypes */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __TIM_H__ */
+
diff --git a/Core/Inc/usart.h b/Core/Inc/usart.h
new file mode 100644
index 0000000..9d32d76
--- /dev/null
+++ b/Core/Inc/usart.h
@@ -0,0 +1,55 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    usart.h
+  * @brief   This file contains all the function prototypes for
+  *          the usart.c file
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2022 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __USART_H__
+#define __USART_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+extern UART_HandleTypeDef huart3;
+
+extern UART_HandleTypeDef huart6;
+
+/* USER CODE BEGIN Private defines */
+
+/* USER CODE END Private defines */
+
+void MX_USART3_UART_Init(void);
+void MX_USART6_UART_Init(void);
+
+/* USER CODE BEGIN Prototypes */
+
+/* USER CODE END Prototypes */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __USART_H__ */
+
diff --git a/Core/Src/crc.c b/Core/Src/crc.c
new file mode 100644
index 0000000..03e762c
--- /dev/null
+++ b/Core/Src/crc.c
@@ -0,0 +1,85 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    crc.c
+  * @brief   This file provides code for the configuration
+  *          of the CRC instances.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2022 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+/* Includes ------------------------------------------------------------------*/
+#include "crc.h"
+
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+CRC_HandleTypeDef hcrc;
+
+/* CRC init function */
+void MX_CRC_Init(void)
+{
+
+  /* USER CODE BEGIN CRC_Init 0 */
+
+  /* USER CODE END CRC_Init 0 */
+
+  /* USER CODE BEGIN CRC_Init 1 */
+
+  /* USER CODE END CRC_Init 1 */
+  hcrc.Instance = CRC;
+  if (HAL_CRC_Init(&hcrc) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /* USER CODE BEGIN CRC_Init 2 */
+
+  /* USER CODE END CRC_Init 2 */
+
+}
+
+void HAL_CRC_MspInit(CRC_HandleTypeDef* crcHandle)
+{
+
+  if(crcHandle->Instance==CRC)
+  {
+  /* USER CODE BEGIN CRC_MspInit 0 */
+
+  /* USER CODE END CRC_MspInit 0 */
+    /* CRC clock enable */
+    __HAL_RCC_CRC_CLK_ENABLE();
+  /* USER CODE BEGIN CRC_MspInit 1 */
+
+  /* USER CODE END CRC_MspInit 1 */
+  }
+}
+
+void HAL_CRC_MspDeInit(CRC_HandleTypeDef* crcHandle)
+{
+
+  if(crcHandle->Instance==CRC)
+  {
+  /* USER CODE BEGIN CRC_MspDeInit 0 */
+
+  /* USER CODE END CRC_MspDeInit 0 */
+    /* Peripheral clock disable */
+    __HAL_RCC_CRC_CLK_DISABLE();
+  /* USER CODE BEGIN CRC_MspDeInit 1 */
+
+  /* USER CODE END CRC_MspDeInit 1 */
+  }
+}
+
+/* USER CODE BEGIN 1 */
+
+/* USER CODE END 1 */
diff --git a/Core/Src/dma2d.c b/Core/Src/dma2d.c
new file mode 100644
index 0000000..ca4743a
--- /dev/null
+++ b/Core/Src/dma2d.c
@@ -0,0 +1,103 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    dma2d.c
+  * @brief   This file provides code for the configuration
+  *          of the DMA2D instances.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2022 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+/* Includes ------------------------------------------------------------------*/
+#include "dma2d.h"
+
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+DMA2D_HandleTypeDef hdma2d;
+
+/* DMA2D init function */
+void MX_DMA2D_Init(void)
+{
+
+  /* USER CODE BEGIN DMA2D_Init 0 */
+
+  /* USER CODE END DMA2D_Init 0 */
+
+  /* USER CODE BEGIN DMA2D_Init 1 */
+
+  /* USER CODE END DMA2D_Init 1 */
+  hdma2d.Instance = DMA2D;
+  hdma2d.Init.Mode = DMA2D_M2M;
+  hdma2d.Init.ColorMode = DMA2D_OUTPUT_ARGB8888;
+  hdma2d.Init.OutputOffset = 0;
+  hdma2d.LayerCfg[1].InputOffset = 0;
+  hdma2d.LayerCfg[1].InputColorMode = DMA2D_INPUT_ARGB8888;
+  hdma2d.LayerCfg[1].AlphaMode = DMA2D_NO_MODIF_ALPHA;
+  hdma2d.LayerCfg[1].InputAlpha = 0;
+  if (HAL_DMA2D_Init(&hdma2d) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  if (HAL_DMA2D_ConfigLayer(&hdma2d, 1) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /* USER CODE BEGIN DMA2D_Init 2 */
+
+  /* USER CODE END DMA2D_Init 2 */
+
+}
+
+void HAL_DMA2D_MspInit(DMA2D_HandleTypeDef* dma2dHandle)
+{
+
+  if(dma2dHandle->Instance==DMA2D)
+  {
+  /* USER CODE BEGIN DMA2D_MspInit 0 */
+
+  /* USER CODE END DMA2D_MspInit 0 */
+    /* DMA2D clock enable */
+    __HAL_RCC_DMA2D_CLK_ENABLE();
+
+    /* DMA2D interrupt Init */
+    HAL_NVIC_SetPriority(DMA2D_IRQn, 5, 0);
+    HAL_NVIC_EnableIRQ(DMA2D_IRQn);
+  /* USER CODE BEGIN DMA2D_MspInit 1 */
+
+  /* USER CODE END DMA2D_MspInit 1 */
+  }
+}
+
+void HAL_DMA2D_MspDeInit(DMA2D_HandleTypeDef* dma2dHandle)
+{
+
+  if(dma2dHandle->Instance==DMA2D)
+  {
+  /* USER CODE BEGIN DMA2D_MspDeInit 0 */
+
+  /* USER CODE END DMA2D_MspDeInit 0 */
+    /* Peripheral clock disable */
+    __HAL_RCC_DMA2D_CLK_DISABLE();
+
+    /* DMA2D interrupt Deinit */
+    HAL_NVIC_DisableIRQ(DMA2D_IRQn);
+  /* USER CODE BEGIN DMA2D_MspDeInit 1 */
+
+  /* USER CODE END DMA2D_MspDeInit 1 */
+  }
+}
+
+/* USER CODE BEGIN 1 */
+
+/* USER CODE END 1 */
diff --git a/Core/Src/dsihost.c b/Core/Src/dsihost.c
new file mode 100644
index 0000000..5992f7e
--- /dev/null
+++ b/Core/Src/dsihost.c
@@ -0,0 +1,193 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    dsihost.c
+  * @brief   This file provides code for the configuration
+  *          of the DSIHOST instances.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2022 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+/* Includes ------------------------------------------------------------------*/
+#include "dsihost.h"
+
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+DSI_HandleTypeDef hdsi;
+
+/* DSIHOST init function */
+
+void MX_DSIHOST_DSI_Init(void)
+{
+
+  /* USER CODE BEGIN DSIHOST_Init 0 */
+
+  /* USER CODE END DSIHOST_Init 0 */
+
+  DSI_PLLInitTypeDef PLLInit = {0};
+  DSI_HOST_TimeoutTypeDef HostTimeouts = {0};
+  DSI_PHY_TimerTypeDef PhyTimings = {0};
+  DSI_LPCmdTypeDef LPCmd = {0};
+  DSI_CmdCfgTypeDef CmdCfg = {0};
+
+  /* USER CODE BEGIN DSIHOST_Init 1 */
+
+  /* USER CODE END DSIHOST_Init 1 */
+  hdsi.Instance = DSI;
+  hdsi.Init.AutomaticClockLaneControl = DSI_AUTO_CLK_LANE_CTRL_DISABLE;
+  hdsi.Init.TXEscapeCkdiv = 4;
+  hdsi.Init.NumberOfLanes = DSI_TWO_DATA_LANES;
+  PLLInit.PLLNDIV = 125;
+  PLLInit.PLLIDF = DSI_PLL_IN_DIV2;
+  PLLInit.PLLODF = DSI_PLL_OUT_DIV1;
+  if (HAL_DSI_Init(&hdsi, &PLLInit) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  HostTimeouts.TimeoutCkdiv = 1;
+  HostTimeouts.HighSpeedTransmissionTimeout = 0;
+  HostTimeouts.LowPowerReceptionTimeout = 0;
+  HostTimeouts.HighSpeedReadTimeout = 0;
+  HostTimeouts.LowPowerReadTimeout = 0;
+  HostTimeouts.HighSpeedWriteTimeout = 0;
+  HostTimeouts.HighSpeedWritePrespMode = DSI_HS_PM_DISABLE;
+  HostTimeouts.LowPowerWriteTimeout = 0;
+  HostTimeouts.BTATimeout = 0;
+  if (HAL_DSI_ConfigHostTimeouts(&hdsi, &HostTimeouts) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  PhyTimings.ClockLaneHS2LPTime = 28;
+  PhyTimings.ClockLaneLP2HSTime = 33;
+  PhyTimings.DataLaneHS2LPTime = 15;
+  PhyTimings.DataLaneLP2HSTime = 25;
+  PhyTimings.DataLaneMaxReadTime = 0;
+  PhyTimings.StopWaitTime = 10;
+  if (HAL_DSI_ConfigPhyTimer(&hdsi, &PhyTimings) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  if (HAL_DSI_ConfigFlowControl(&hdsi, DSI_FLOW_CONTROL_BTA) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  if (HAL_DSI_SetLowPowerRXFilter(&hdsi, 10000) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  if (HAL_DSI_ConfigErrorMonitor(&hdsi, HAL_DSI_ERROR_NONE) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  LPCmd.LPGenShortWriteNoP = DSI_LP_GSW0P_ENABLE;
+  LPCmd.LPGenShortWriteOneP = DSI_LP_GSW1P_ENABLE;
+  LPCmd.LPGenShortWriteTwoP = DSI_LP_GSW2P_ENABLE;
+  LPCmd.LPGenShortReadNoP = DSI_LP_GSR0P_ENABLE;
+  LPCmd.LPGenShortReadOneP = DSI_LP_GSR1P_ENABLE;
+  LPCmd.LPGenShortReadTwoP = DSI_LP_GSR2P_ENABLE;
+  LPCmd.LPGenLongWrite = DSI_LP_GLW_ENABLE;
+  LPCmd.LPDcsShortWriteNoP = DSI_LP_DSW0P_ENABLE;
+  LPCmd.LPDcsShortWriteOneP = DSI_LP_DSW1P_ENABLE;
+  LPCmd.LPDcsShortReadNoP = DSI_LP_DSR0P_ENABLE;
+  LPCmd.LPDcsLongWrite = DSI_LP_DLW_ENABLE;
+  LPCmd.LPMaxReadPacket = DSI_LP_MRDP_ENABLE;
+  LPCmd.AcknowledgeRequest = DSI_ACKNOWLEDGE_DISABLE;
+  if (HAL_DSI_ConfigCommand(&hdsi, &LPCmd) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  CmdCfg.VirtualChannelID = 0;
+  CmdCfg.ColorCoding = DSI_RGB888;
+  CmdCfg.CommandSize = 200;
+  CmdCfg.TearingEffectSource = DSI_TE_EXTERNAL;
+  CmdCfg.TearingEffectPolarity = DSI_TE_RISING_EDGE;
+  CmdCfg.HSPolarity = DSI_HSYNC_ACTIVE_LOW;
+  CmdCfg.VSPolarity = DSI_VSYNC_ACTIVE_LOW;
+  CmdCfg.DEPolarity = DSI_DATA_ENABLE_ACTIVE_HIGH;
+  CmdCfg.VSyncPol = DSI_VSYNC_FALLING;
+  CmdCfg.AutomaticRefresh = DSI_AR_ENABLE;
+  CmdCfg.TEAcknowledgeRequest = DSI_TE_ACKNOWLEDGE_ENABLE;
+  if (HAL_DSI_ConfigAdaptedCommandMode(&hdsi, &CmdCfg) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  if (HAL_DSI_SetGenericVCID(&hdsi, 0) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /* USER CODE BEGIN DSIHOST_Init 2 */
+
+  /* USER CODE END DSIHOST_Init 2 */
+
+}
+
+void HAL_DSI_MspInit(DSI_HandleTypeDef* dsiHandle)
+{
+
+  GPIO_InitTypeDef GPIO_InitStruct = {0};
+  if(dsiHandle->Instance==DSI)
+  {
+  /* USER CODE BEGIN DSI_MspInit 0 */
+
+  /* USER CODE END DSI_MspInit 0 */
+    /* DSI clock enable */
+    __HAL_RCC_DSI_CLK_ENABLE();
+
+    __HAL_RCC_GPIOJ_CLK_ENABLE();
+    /**DSIHOST GPIO Configuration
+    PJ2     ------> DSIHOST_TE
+    */
+    GPIO_InitStruct.Pin = DSI_TE_Pin;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+    GPIO_InitStruct.Alternate = GPIO_AF13_DSI;
+    HAL_GPIO_Init(DSI_TE_GPIO_Port, &GPIO_InitStruct);
+
+    /* DSI interrupt Init */
+    HAL_NVIC_SetPriority(DSI_IRQn, 5, 0);
+    HAL_NVIC_EnableIRQ(DSI_IRQn);
+  /* USER CODE BEGIN DSI_MspInit 1 */
+
+  /* USER CODE END DSI_MspInit 1 */
+  }
+}
+
+void HAL_DSI_MspDeInit(DSI_HandleTypeDef* dsiHandle)
+{
+
+  if(dsiHandle->Instance==DSI)
+  {
+  /* USER CODE BEGIN DSI_MspDeInit 0 */
+
+  /* USER CODE END DSI_MspDeInit 0 */
+    /* Peripheral clock disable */
+    __HAL_RCC_DSI_CLK_DISABLE();
+
+    /**DSIHOST GPIO Configuration
+    PJ2     ------> DSIHOST_TE
+    */
+    HAL_GPIO_DeInit(DSI_TE_GPIO_Port, DSI_TE_Pin);
+
+    /* DSI interrupt Deinit */
+    HAL_NVIC_DisableIRQ(DSI_IRQn);
+  /* USER CODE BEGIN DSI_MspDeInit 1 */
+
+  /* USER CODE END DSI_MspDeInit 1 */
+  }
+}
+
+/* USER CODE BEGIN 1 */
+
+/* USER CODE END 1 */
diff --git a/Core/Src/fmc.c b/Core/Src/fmc.c
new file mode 100644
index 0000000..04acbde
--- /dev/null
+++ b/Core/Src/fmc.c
@@ -0,0 +1,353 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * File Name          : FMC.c
+  * Description        : This file provides code for the configuration
+  *                      of the FMC peripheral.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2022 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "fmc.h"
+
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+SDRAM_HandleTypeDef hsdram1;
+
+/* FMC initialization function */
+void MX_FMC_Init(void)
+{
+  /* USER CODE BEGIN FMC_Init 0 */
+
+  /* USER CODE END FMC_Init 0 */
+
+  FMC_SDRAM_TimingTypeDef SdramTiming = {0};
+
+  /* USER CODE BEGIN FMC_Init 1 */
+
+  /* USER CODE END FMC_Init 1 */
+
+  /** Perform the SDRAM1 memory initialization sequence
+  */
+  hsdram1.Instance = FMC_SDRAM_DEVICE;
+  /* hsdram1.Init */
+  hsdram1.Init.SDBank = FMC_SDRAM_BANK1;
+  hsdram1.Init.ColumnBitsNumber = FMC_SDRAM_COLUMN_BITS_NUM_8;
+  hsdram1.Init.RowBitsNumber = FMC_SDRAM_ROW_BITS_NUM_12;
+  hsdram1.Init.MemoryDataWidth = FMC_SDRAM_MEM_BUS_WIDTH_32;
+  hsdram1.Init.InternalBankNumber = FMC_SDRAM_INTERN_BANKS_NUM_4;
+  hsdram1.Init.CASLatency = FMC_SDRAM_CAS_LATENCY_3;
+  hsdram1.Init.WriteProtection = FMC_SDRAM_WRITE_PROTECTION_DISABLE;
+  hsdram1.Init.SDClockPeriod = FMC_SDRAM_CLOCK_PERIOD_2;
+  hsdram1.Init.ReadBurst = FMC_SDRAM_RBURST_ENABLE;
+  hsdram1.Init.ReadPipeDelay = FMC_SDRAM_RPIPE_DELAY_0;
+  /* SdramTiming */
+  SdramTiming.LoadToActiveDelay = 2;
+  SdramTiming.ExitSelfRefreshDelay = 7;
+  SdramTiming.SelfRefreshTime = 4;
+  SdramTiming.RowCycleDelay = 7;
+  SdramTiming.WriteRecoveryTime = 3;
+  SdramTiming.RPDelay = 2;
+  SdramTiming.RCDDelay = 2;
+
+  if (HAL_SDRAM_Init(&hsdram1, &SdramTiming) != HAL_OK)
+  {
+    Error_Handler( );
+  }
+
+  /* USER CODE BEGIN FMC_Init 2 */
+
+  /* USER CODE END FMC_Init 2 */
+}
+
+static uint32_t FMC_Initialized = 0;
+
+static void HAL_FMC_MspInit(void){
+  /* USER CODE BEGIN FMC_MspInit 0 */
+
+  /* USER CODE END FMC_MspInit 0 */
+  GPIO_InitTypeDef GPIO_InitStruct = {0};
+  if (FMC_Initialized) {
+    return;
+  }
+  FMC_Initialized = 1;
+
+  /* Peripheral clock enable */
+  __HAL_RCC_FMC_CLK_ENABLE();
+
+  /** FMC GPIO Configuration
+  PE1   ------> FMC_NBL1
+  PE0   ------> FMC_NBL0
+  PG15   ------> FMC_SDNCAS
+  PD0   ------> FMC_D2
+  PI4   ------> FMC_NBL2
+  PD1   ------> FMC_D3
+  PI3   ------> FMC_D27
+  PI2   ------> FMC_D26
+  PF0   ------> FMC_A0
+  PI5   ------> FMC_NBL3
+  PI7   ------> FMC_D29
+  PI10   ------> FMC_D31
+  PI6   ------> FMC_D28
+  PH15   ------> FMC_D23
+  PI1   ------> FMC_D25
+  PF1   ------> FMC_A1
+  PI9   ------> FMC_D30
+  PH13   ------> FMC_D21
+  PH14   ------> FMC_D22
+  PI0   ------> FMC_D24
+  PF2   ------> FMC_A2
+  PF3   ------> FMC_A3
+  PG8   ------> FMC_SDCLK
+  PF4   ------> FMC_A4
+  PH3   ------> FMC_SDNE0
+  PF5   ------> FMC_A5
+  PH2   ------> FMC_SDCKE0
+  PD15   ------> FMC_D1
+  PD10   ------> FMC_D15
+  PD14   ------> FMC_D0
+  PD9   ------> FMC_D14
+  PD8   ------> FMC_D13
+  PC0   ------> FMC_SDNWE
+  PF12   ------> FMC_A6
+  PG1   ------> FMC_A11
+  PF15   ------> FMC_A9
+  PH12   ------> FMC_D20
+  PF13   ------> FMC_A7
+  PG0   ------> FMC_A10
+  PE8   ------> FMC_D5
+  PG5   ------> FMC_BA1
+  PG4   ------> FMC_BA0
+  PH9   ------> FMC_D17
+  PH11   ------> FMC_D19
+  PF14   ------> FMC_A8
+  PF11   ------> FMC_SDNRAS
+  PE9   ------> FMC_D6
+  PE11   ------> FMC_D8
+  PE14   ------> FMC_D11
+  PH8   ------> FMC_D16
+  PH10   ------> FMC_D18
+  PE7   ------> FMC_D4
+  PE10   ------> FMC_D7
+  PE12   ------> FMC_D9
+  PE15   ------> FMC_D12
+  PE13   ------> FMC_D10
+  */
+  /* GPIO_InitStruct */
+  GPIO_InitStruct.Pin = FMC_NBL1_Pin|FMC_NBL0_Pin|D5_Pin|D6_Pin
+                          |D8_Pin|D11_Pin|D4_Pin|D7_Pin
+                          |D9_Pin|D12_Pin|D10_Pin;
+  GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+  GPIO_InitStruct.Alternate = GPIO_AF12_FMC;
+
+  HAL_GPIO_Init(GPIOE, &GPIO_InitStruct);
+
+  /* GPIO_InitStruct */
+  GPIO_InitStruct.Pin = SDNCAS_Pin|SDCLK_Pin|A11_Pin|A10_Pin
+                          |GPIO_PIN_5|GPIO_PIN_4;
+  GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+  GPIO_InitStruct.Alternate = GPIO_AF12_FMC;
+
+  HAL_GPIO_Init(GPIOG, &GPIO_InitStruct);
+
+  /* GPIO_InitStruct */
+  GPIO_InitStruct.Pin = D2_Pin|D3_Pin|D1_Pin|D15_Pin
+                          |D0_Pin|D14_Pin|D13_Pin;
+  GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+  GPIO_InitStruct.Alternate = GPIO_AF12_FMC;
+
+  HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
+
+  /* GPIO_InitStruct */
+  GPIO_InitStruct.Pin = FMC_NBL2_Pin|D27_Pin|D26_Pin|FMC_NBL3_Pin
+                          |D29_Pin|D31_Pin|D28_Pin|D25_Pin
+                          |D30_Pin|D24_Pin;
+  GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+  GPIO_InitStruct.Alternate = GPIO_AF12_FMC;
+
+  HAL_GPIO_Init(GPIOI, &GPIO_InitStruct);
+
+  /* GPIO_InitStruct */
+  GPIO_InitStruct.Pin = A0_Pin|A1_Pin|A2_Pin|A3_Pin
+                          |A4_Pin|A5_Pin|A6_Pin|A9_Pin
+                          |A7_Pin|A8_Pin|SDNMT48LC4M32B2B5_6A_RAS_RAS___Pin;
+  GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+  GPIO_InitStruct.Alternate = GPIO_AF12_FMC;
+
+  HAL_GPIO_Init(GPIOF, &GPIO_InitStruct);
+
+  /* GPIO_InitStruct */
+  GPIO_InitStruct.Pin = D23_Pin|D21_Pin|D22_Pin|SDNE0_Pin
+                          |SDCKE0_Pin|D20_Pin|D17_Pin|D19_Pin
+                          |D16_Pin|D18_Pin;
+  GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+  GPIO_InitStruct.Alternate = GPIO_AF12_FMC;
+
+  HAL_GPIO_Init(GPIOH, &GPIO_InitStruct);
+
+  /* GPIO_InitStruct */
+  GPIO_InitStruct.Pin = SDNWE_Pin;
+  GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+  GPIO_InitStruct.Alternate = GPIO_AF12_FMC;
+
+  HAL_GPIO_Init(SDNWE_GPIO_Port, &GPIO_InitStruct);
+
+  /* USER CODE BEGIN FMC_MspInit 1 */
+
+  /* USER CODE END FMC_MspInit 1 */
+}
+
+void HAL_SDRAM_MspInit(SDRAM_HandleTypeDef* sdramHandle){
+  /* USER CODE BEGIN SDRAM_MspInit 0 */
+
+  /* USER CODE END SDRAM_MspInit 0 */
+  HAL_FMC_MspInit();
+  /* USER CODE BEGIN SDRAM_MspInit 1 */
+
+  /* USER CODE END SDRAM_MspInit 1 */
+}
+
+static uint32_t FMC_DeInitialized = 0;
+
+static void HAL_FMC_MspDeInit(void){
+  /* USER CODE BEGIN FMC_MspDeInit 0 */
+
+  /* USER CODE END FMC_MspDeInit 0 */
+  if (FMC_DeInitialized) {
+    return;
+  }
+  FMC_DeInitialized = 1;
+  /* Peripheral clock enable */
+  __HAL_RCC_FMC_CLK_DISABLE();
+
+  /** FMC GPIO Configuration
+  PE1   ------> FMC_NBL1
+  PE0   ------> FMC_NBL0
+  PG15   ------> FMC_SDNCAS
+  PD0   ------> FMC_D2
+  PI4   ------> FMC_NBL2
+  PD1   ------> FMC_D3
+  PI3   ------> FMC_D27
+  PI2   ------> FMC_D26
+  PF0   ------> FMC_A0
+  PI5   ------> FMC_NBL3
+  PI7   ------> FMC_D29
+  PI10   ------> FMC_D31
+  PI6   ------> FMC_D28
+  PH15   ------> FMC_D23
+  PI1   ------> FMC_D25
+  PF1   ------> FMC_A1
+  PI9   ------> FMC_D30
+  PH13   ------> FMC_D21
+  PH14   ------> FMC_D22
+  PI0   ------> FMC_D24
+  PF2   ------> FMC_A2
+  PF3   ------> FMC_A3
+  PG8   ------> FMC_SDCLK
+  PF4   ------> FMC_A4
+  PH3   ------> FMC_SDNE0
+  PF5   ------> FMC_A5
+  PH2   ------> FMC_SDCKE0
+  PD15   ------> FMC_D1
+  PD10   ------> FMC_D15
+  PD14   ------> FMC_D0
+  PD9   ------> FMC_D14
+  PD8   ------> FMC_D13
+  PC0   ------> FMC_SDNWE
+  PF12   ------> FMC_A6
+  PG1   ------> FMC_A11
+  PF15   ------> FMC_A9
+  PH12   ------> FMC_D20
+  PF13   ------> FMC_A7
+  PG0   ------> FMC_A10
+  PE8   ------> FMC_D5
+  PG5   ------> FMC_BA1
+  PG4   ------> FMC_BA0
+  PH9   ------> FMC_D17
+  PH11   ------> FMC_D19
+  PF14   ------> FMC_A8
+  PF11   ------> FMC_SDNRAS
+  PE9   ------> FMC_D6
+  PE11   ------> FMC_D8
+  PE14   ------> FMC_D11
+  PH8   ------> FMC_D16
+  PH10   ------> FMC_D18
+  PE7   ------> FMC_D4
+  PE10   ------> FMC_D7
+  PE12   ------> FMC_D9
+  PE15   ------> FMC_D12
+  PE13   ------> FMC_D10
+  */
+
+  HAL_GPIO_DeInit(GPIOE, FMC_NBL1_Pin|FMC_NBL0_Pin|D5_Pin|D6_Pin
+                          |D8_Pin|D11_Pin|D4_Pin|D7_Pin
+                          |D9_Pin|D12_Pin|D10_Pin);
+
+  HAL_GPIO_DeInit(GPIOG, SDNCAS_Pin|SDCLK_Pin|A11_Pin|A10_Pin
+                          |GPIO_PIN_5|GPIO_PIN_4);
+
+  HAL_GPIO_DeInit(GPIOD, D2_Pin|D3_Pin|D1_Pin|D15_Pin
+                          |D0_Pin|D14_Pin|D13_Pin);
+
+  HAL_GPIO_DeInit(GPIOI, FMC_NBL2_Pin|D27_Pin|D26_Pin|FMC_NBL3_Pin
+                          |D29_Pin|D31_Pin|D28_Pin|D25_Pin
+                          |D30_Pin|D24_Pin);
+
+  HAL_GPIO_DeInit(GPIOF, A0_Pin|A1_Pin|A2_Pin|A3_Pin
+                          |A4_Pin|A5_Pin|A6_Pin|A9_Pin
+                          |A7_Pin|A8_Pin|SDNMT48LC4M32B2B5_6A_RAS_RAS___Pin);
+
+  HAL_GPIO_DeInit(GPIOH, D23_Pin|D21_Pin|D22_Pin|SDNE0_Pin
+                          |SDCKE0_Pin|D20_Pin|D17_Pin|D19_Pin
+                          |D16_Pin|D18_Pin);
+
+  HAL_GPIO_DeInit(SDNWE_GPIO_Port, SDNWE_Pin);
+
+  /* USER CODE BEGIN FMC_MspDeInit 1 */
+
+  /* USER CODE END FMC_MspDeInit 1 */
+}
+
+void HAL_SDRAM_MspDeInit(SDRAM_HandleTypeDef* sdramHandle){
+  /* USER CODE BEGIN SDRAM_MspDeInit 0 */
+
+  /* USER CODE END SDRAM_MspDeInit 0 */
+  HAL_FMC_MspDeInit();
+  /* USER CODE BEGIN SDRAM_MspDeInit 1 */
+
+  /* USER CODE END SDRAM_MspDeInit 1 */
+}
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
diff --git a/Core/Src/freertos.c b/Core/Src/freertos.c
new file mode 100644
index 0000000..7d5273a
--- /dev/null
+++ b/Core/Src/freertos.c
@@ -0,0 +1,176 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * File Name          : freertos.c
+  * Description        : Code for freertos applications
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2022 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "FreeRTOS.h"
+#include "task.h"
+#include "main.h"
+#include "cmsis_os.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+#include "my_lcd.h"
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN PTD */
+
+/* USER CODE END PTD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN Variables */
+
+/* USER CODE END Variables */
+/* Definitions for defaultTask */
+osThreadId_t defaultTaskHandle;
+const osThreadAttr_t defaultTask_attributes = {
+  .name = "defaultTask",
+  .stack_size = 4096 * 4,
+  .priority = (osPriority_t) osPriorityNormal,
+};
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN FunctionPrototypes */
+
+/* USER CODE END FunctionPrototypes */
+
+void StartDefaultTask(void *argument);
+
+extern void MX_USB_HOST_Init(void);
+void MX_FREERTOS_Init(void); /* (MISRA C 2004 rule 8.1) */
+
+/* Hook prototypes */
+void vApplicationIdleHook(void);
+void vApplicationStackOverflowHook(xTaskHandle xTask, signed char *pcTaskName);
+void vApplicationMallocFailedHook(void);
+
+/* USER CODE BEGIN 2 */
+__weak void vApplicationIdleHook( void )
+{
+   /* vApplicationIdleHook() will only be called if configUSE_IDLE_HOOK is set
+   to 1 in FreeRTOSConfig.h. It will be called on each iteration of the idle
+   task. It is essential that code added to this hook function never attempts
+   to block in any way (for example, call xQueueReceive() with a block time
+   specified, or call vTaskDelay()). If the application makes use of the
+   vTaskDelete() API function (as this demo application does) then it is also
+   important that vApplicationIdleHook() is permitted to return to its calling
+   function, because it is the responsibility of the idle task to clean up
+   memory allocated by the kernel to any task that has since been deleted. */
+}
+/* USER CODE END 2 */
+
+/* USER CODE BEGIN 4 */
+__weak void vApplicationStackOverflowHook(xTaskHandle xTask, signed char *pcTaskName)
+{
+   /* Run time stack overflow checking is performed if
+   configCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2. This hook function is
+   called if a stack overflow is detected. */
+}
+/* USER CODE END 4 */
+
+/* USER CODE BEGIN 5 */
+__weak void vApplicationMallocFailedHook(void)
+{
+   /* vApplicationMallocFailedHook() will only be called if
+   configUSE_MALLOC_FAILED_HOOK is set to 1 in FreeRTOSConfig.h. It is a hook
+   function that will get called if a call to pvPortMalloc() fails.
+   pvPortMalloc() is called internally by the kernel whenever a task, queue,
+   timer or semaphore is created. It is also called by various parts of the
+   demo application. If heap_1.c or heap_2.c are used, then the size of the
+   heap available to pvPortMalloc() is defined by configTOTAL_HEAP_SIZE in
+   FreeRTOSConfig.h, and the xPortGetFreeHeapSize() API function can be used
+   to query the size of free heap space that remains (although it does not
+   provide information on how the remaining heap might be fragmented). */
+}
+/* USER CODE END 5 */
+
+/**
+  * @brief  FreeRTOS initialization
+  * @param  None
+  * @retval None
+  */
+void MX_FREERTOS_Init(void) {
+  /* USER CODE BEGIN Init */
+
+  /* USER CODE END Init */
+
+  /* USER CODE BEGIN RTOS_MUTEX */
+  /* add mutexes, ... */
+  /* USER CODE END RTOS_MUTEX */
+
+  /* USER CODE BEGIN RTOS_SEMAPHORES */
+  /* add semaphores, ... */
+  /* USER CODE END RTOS_SEMAPHORES */
+
+  /* USER CODE BEGIN RTOS_TIMERS */
+  /* start timers, add new ones, ... */
+  /* USER CODE END RTOS_TIMERS */
+
+  /* USER CODE BEGIN RTOS_QUEUES */
+  /* add queues, ... */
+  /* USER CODE END RTOS_QUEUES */
+
+  /* Create the thread(s) */
+  /* creation of defaultTask */
+  defaultTaskHandle = osThreadNew(StartDefaultTask, NULL, &defaultTask_attributes);
+
+  /* USER CODE BEGIN RTOS_THREADS */
+  /* add threads, ... */
+  /* USER CODE END RTOS_THREADS */
+
+  /* USER CODE BEGIN RTOS_EVENTS */
+  /* add events, ... */
+  /* USER CODE END RTOS_EVENTS */
+
+}
+
+/* USER CODE BEGIN Header_StartDefaultTask */
+/**
+  * @brief  Function implementing the defaultTask thread.
+  * @param  argument: Not used
+  * @retval None
+  */
+/* USER CODE END Header_StartDefaultTask */
+void StartDefaultTask(void *argument)
+{
+  /* init code for USB_HOST */
+  MX_USB_HOST_Init();
+  /* USER CODE BEGIN StartDefaultTask */
+  /* Infinite loop */
+  for(;;)
+  {
+	  MY_LCD_Tick();
+  }
+  /* USER CODE END StartDefaultTask */
+}
+
+/* Private application code --------------------------------------------------*/
+/* USER CODE BEGIN Application */
+
+/* USER CODE END Application */
+
diff --git a/Core/Src/gpio.c b/Core/Src/gpio.c
new file mode 100644
index 0000000..7a50a7b
--- /dev/null
+++ b/Core/Src/gpio.c
@@ -0,0 +1,165 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    gpio.c
+  * @brief   This file provides code for the configuration
+  *          of all used GPIO pins.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2022 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "gpio.h"
+
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/*----------------------------------------------------------------------------*/
+/* Configure GPIO                                                             */
+/*----------------------------------------------------------------------------*/
+/* USER CODE BEGIN 1 */
+
+/* USER CODE END 1 */
+
+/** Configure pins
+     PB3   ------> I2S3_CK
+     PD13   ------> S_TIM4_CH2
+*/
+void MX_GPIO_Init(void)
+{
+
+  GPIO_InitTypeDef GPIO_InitStruct = {0};
+
+  /* GPIO Ports Clock Enable */
+  __HAL_RCC_GPIOE_CLK_ENABLE();
+  __HAL_RCC_GPIOG_CLK_ENABLE();
+  __HAL_RCC_GPIOB_CLK_ENABLE();
+  __HAL_RCC_GPIOC_CLK_ENABLE();
+  __HAL_RCC_GPIOA_CLK_ENABLE();
+  __HAL_RCC_GPIOD_CLK_ENABLE();
+  __HAL_RCC_GPIOI_CLK_ENABLE();
+  __HAL_RCC_GPIOF_CLK_ENABLE();
+  __HAL_RCC_GPIOK_CLK_ENABLE();
+  __HAL_RCC_GPIOH_CLK_ENABLE();
+  __HAL_RCC_GPIOJ_CLK_ENABLE();
+
+  /*Configure GPIO pin Output Level */
+  HAL_GPIO_WritePin(GPIOE, SPKR_HP_Pin|AUDIO_RST_Pin, GPIO_PIN_RESET);
+
+  /*Configure GPIO pin Output Level */
+  HAL_GPIO_WritePin(GPIOD, LED3_Pin|LED2_Pin, GPIO_PIN_RESET);
+
+  /*Configure GPIO pin Output Level */
+  HAL_GPIO_WritePin(LED4_GPIO_Port, LED4_Pin, GPIO_PIN_RESET);
+
+  /*Configure GPIO pin Output Level */
+  HAL_GPIO_WritePin(LED1_GPIO_Port, LED1_Pin, GPIO_PIN_RESET);
+
+  /*Configure GPIO pin Output Level */
+  HAL_GPIO_WritePin(GPIOB, OTG_FS1_PowerSwitchOn_Pin|EXT_RESET_Pin, GPIO_PIN_RESET);
+
+  /*Configure GPIO pin Output Level */
+  HAL_GPIO_WritePin(GPIOH, GPIO_PIN_7, GPIO_PIN_RESET);
+
+  /*Configure GPIO pin Output Level */
+  HAL_GPIO_WritePin(LCD_BL_CTRL_GPIO_Port, LCD_BL_CTRL_Pin, GPIO_PIN_RESET);
+
+  /*Configure GPIO pins : PEPin PEPin */
+  GPIO_InitStruct.Pin = SPKR_HP_Pin|AUDIO_RST_Pin;
+  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+  HAL_GPIO_Init(GPIOE, &GPIO_InitStruct);
+
+  /*Configure GPIO pin : PtPin */
+  GPIO_InitStruct.Pin = I2S3_CK_Pin;
+  GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+  GPIO_InitStruct.Alternate = GPIO_AF6_SPI3;
+  HAL_GPIO_Init(I2S3_CK_GPIO_Port, &GPIO_InitStruct);
+
+  /*Configure GPIO pin : PtPin */
+  GPIO_InitStruct.Pin = OTG_FS1_OverCurrent_Pin;
+  GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING;
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+  HAL_GPIO_Init(OTG_FS1_OverCurrent_GPIO_Port, &GPIO_InitStruct);
+
+  /*Configure GPIO pins : PDPin PDPin */
+  GPIO_InitStruct.Pin = LED3_Pin|LED2_Pin;
+  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_OD;
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+  HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
+
+  /*Configure GPIO pin : PtPin */
+  GPIO_InitStruct.Pin = LED4_Pin;
+  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_OD;
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+  HAL_GPIO_Init(LED4_GPIO_Port, &GPIO_InitStruct);
+
+  /*Configure GPIO pin : PtPin */
+  GPIO_InitStruct.Pin = LED1_Pin;
+  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_OD;
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+  HAL_GPIO_Init(LED1_GPIO_Port, &GPIO_InitStruct);
+
+  /*Configure GPIO pins : PBPin PBPin */
+  GPIO_InitStruct.Pin = OTG_FS1_PowerSwitchOn_Pin|EXT_RESET_Pin;
+  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+  HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
+
+  /*Configure GPIO pin : PtPin */
+  GPIO_InitStruct.Pin = MIC_CK_Pin;
+  GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+  GPIO_InitStruct.Alternate = GPIO_AF2_TIM4;
+  HAL_GPIO_Init(MIC_CK_GPIO_Port, &GPIO_InitStruct);
+
+  /*Configure GPIO pin : PtPin */
+  GPIO_InitStruct.Pin = uSD_Detect_Pin;
+  GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+  HAL_GPIO_Init(uSD_Detect_GPIO_Port, &GPIO_InitStruct);
+
+  /*Configure GPIO pin : PtPin */
+  GPIO_InitStruct.Pin = LCD_INT_Pin;
+  GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING;
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+  HAL_GPIO_Init(LCD_INT_GPIO_Port, &GPIO_InitStruct);
+
+  /*Configure GPIO pin : PH7 */
+  GPIO_InitStruct.Pin = GPIO_PIN_7;
+  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+  HAL_GPIO_Init(GPIOH, &GPIO_InitStruct);
+
+  /*Configure GPIO pin : PtPin */
+  GPIO_InitStruct.Pin = LCD_BL_CTRL_Pin;
+  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+  HAL_GPIO_Init(LCD_BL_CTRL_GPIO_Port, &GPIO_InitStruct);
+
+}
+
+/* USER CODE BEGIN 2 */
+
+/* USER CODE END 2 */
diff --git a/Core/Src/i2c.c b/Core/Src/i2c.c
new file mode 100644
index 0000000..27ed41f
--- /dev/null
+++ b/Core/Src/i2c.c
@@ -0,0 +1,190 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    i2c.c
+  * @brief   This file provides code for the configuration
+  *          of the I2C instances.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2022 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+/* Includes ------------------------------------------------------------------*/
+#include "i2c.h"
+
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+I2C_HandleTypeDef hi2c1;
+I2C_HandleTypeDef hi2c2;
+
+/* I2C1 init function */
+void MX_I2C1_Init(void)
+{
+
+  /* USER CODE BEGIN I2C1_Init 0 */
+
+  /* USER CODE END I2C1_Init 0 */
+
+  /* USER CODE BEGIN I2C1_Init 1 */
+
+  /* USER CODE END I2C1_Init 1 */
+  hi2c1.Instance = I2C1;
+  hi2c1.Init.ClockSpeed = 100000;
+  hi2c1.Init.DutyCycle = I2C_DUTYCYCLE_2;
+  hi2c1.Init.OwnAddress1 = 0;
+  hi2c1.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT;
+  hi2c1.Init.DualAddressMode = I2C_DUALADDRESS_DISABLE;
+  hi2c1.Init.OwnAddress2 = 0;
+  hi2c1.Init.GeneralCallMode = I2C_GENERALCALL_DISABLE;
+  hi2c1.Init.NoStretchMode = I2C_NOSTRETCH_DISABLE;
+  if (HAL_I2C_Init(&hi2c1) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /* USER CODE BEGIN I2C1_Init 2 */
+
+  /* USER CODE END I2C1_Init 2 */
+
+}
+/* I2C2 init function */
+void MX_I2C2_Init(void)
+{
+
+  /* USER CODE BEGIN I2C2_Init 0 */
+
+  /* USER CODE END I2C2_Init 0 */
+
+  /* USER CODE BEGIN I2C2_Init 1 */
+
+  /* USER CODE END I2C2_Init 1 */
+  hi2c2.Instance = I2C2;
+  hi2c2.Init.ClockSpeed = 100000;
+  hi2c2.Init.DutyCycle = I2C_DUTYCYCLE_2;
+  hi2c2.Init.OwnAddress1 = 0;
+  hi2c2.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT;
+  hi2c2.Init.DualAddressMode = I2C_DUALADDRESS_DISABLE;
+  hi2c2.Init.OwnAddress2 = 0;
+  hi2c2.Init.GeneralCallMode = I2C_GENERALCALL_DISABLE;
+  hi2c2.Init.NoStretchMode = I2C_NOSTRETCH_DISABLE;
+  if (HAL_I2C_Init(&hi2c2) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /* USER CODE BEGIN I2C2_Init 2 */
+
+  /* USER CODE END I2C2_Init 2 */
+
+}
+
+void HAL_I2C_MspInit(I2C_HandleTypeDef* i2cHandle)
+{
+
+  GPIO_InitTypeDef GPIO_InitStruct = {0};
+  if(i2cHandle->Instance==I2C1)
+  {
+  /* USER CODE BEGIN I2C1_MspInit 0 */
+
+  /* USER CODE END I2C1_MspInit 0 */
+
+    __HAL_RCC_GPIOB_CLK_ENABLE();
+    /**I2C1 GPIO Configuration
+    PB8     ------> I2C1_SCL
+    PB9     ------> I2C1_SDA
+    */
+    GPIO_InitStruct.Pin = I2C1_SCL_Pin|I2C1_SDA_Pin;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_OD;
+    GPIO_InitStruct.Pull = GPIO_PULLUP;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+    GPIO_InitStruct.Alternate = GPIO_AF4_I2C1;
+    HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
+
+    /* I2C1 clock enable */
+    __HAL_RCC_I2C1_CLK_ENABLE();
+  /* USER CODE BEGIN I2C1_MspInit 1 */
+
+  /* USER CODE END I2C1_MspInit 1 */
+  }
+  else if(i2cHandle->Instance==I2C2)
+  {
+  /* USER CODE BEGIN I2C2_MspInit 0 */
+
+  /* USER CODE END I2C2_MspInit 0 */
+
+    __HAL_RCC_GPIOH_CLK_ENABLE();
+    /**I2C2 GPIO Configuration
+    PH4     ------> I2C2_SCL
+    PH5     ------> I2C2_SDA
+    */
+    GPIO_InitStruct.Pin = I2C2_SCL_Pin|I2C2_SDA_Pin;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_OD;
+    GPIO_InitStruct.Pull = GPIO_PULLUP;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+    GPIO_InitStruct.Alternate = GPIO_AF4_I2C2;
+    HAL_GPIO_Init(GPIOH, &GPIO_InitStruct);
+
+    /* I2C2 clock enable */
+    __HAL_RCC_I2C2_CLK_ENABLE();
+  /* USER CODE BEGIN I2C2_MspInit 1 */
+
+  /* USER CODE END I2C2_MspInit 1 */
+  }
+}
+
+void HAL_I2C_MspDeInit(I2C_HandleTypeDef* i2cHandle)
+{
+
+  if(i2cHandle->Instance==I2C1)
+  {
+  /* USER CODE BEGIN I2C1_MspDeInit 0 */
+
+  /* USER CODE END I2C1_MspDeInit 0 */
+    /* Peripheral clock disable */
+    __HAL_RCC_I2C1_CLK_DISABLE();
+
+    /**I2C1 GPIO Configuration
+    PB8     ------> I2C1_SCL
+    PB9     ------> I2C1_SDA
+    */
+    HAL_GPIO_DeInit(I2C1_SCL_GPIO_Port, I2C1_SCL_Pin);
+
+    HAL_GPIO_DeInit(I2C1_SDA_GPIO_Port, I2C1_SDA_Pin);
+
+  /* USER CODE BEGIN I2C1_MspDeInit 1 */
+
+  /* USER CODE END I2C1_MspDeInit 1 */
+  }
+  else if(i2cHandle->Instance==I2C2)
+  {
+  /* USER CODE BEGIN I2C2_MspDeInit 0 */
+
+  /* USER CODE END I2C2_MspDeInit 0 */
+    /* Peripheral clock disable */
+    __HAL_RCC_I2C2_CLK_DISABLE();
+
+    /**I2C2 GPIO Configuration
+    PH4     ------> I2C2_SCL
+    PH5     ------> I2C2_SDA
+    */
+    HAL_GPIO_DeInit(I2C2_SCL_GPIO_Port, I2C2_SCL_Pin);
+
+    HAL_GPIO_DeInit(I2C2_SDA_GPIO_Port, I2C2_SDA_Pin);
+
+  /* USER CODE BEGIN I2C2_MspDeInit 1 */
+
+  /* USER CODE END I2C2_MspDeInit 1 */
+  }
+}
+
+/* USER CODE BEGIN 1 */
+
+/* USER CODE END 1 */
diff --git a/Core/Src/ltdc.c b/Core/Src/ltdc.c
new file mode 100644
index 0000000..71e998f
--- /dev/null
+++ b/Core/Src/ltdc.c
@@ -0,0 +1,128 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    ltdc.c
+  * @brief   This file provides code for the configuration
+  *          of the LTDC instances.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2022 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+/* Includes ------------------------------------------------------------------*/
+#include "ltdc.h"
+
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+LTDC_HandleTypeDef hltdc;
+
+/* LTDC init function */
+void MX_LTDC_Init(void)
+{
+
+  /* USER CODE BEGIN LTDC_Init 0 */
+
+  /* USER CODE END LTDC_Init 0 */
+
+  LTDC_LayerCfgTypeDef pLayerCfg = {0};
+
+  /* USER CODE BEGIN LTDC_Init 1 */
+
+  /* USER CODE END LTDC_Init 1 */
+  hltdc.Instance = LTDC;
+  hltdc.Init.HSPolarity = LTDC_HSPOLARITY_AL;
+  hltdc.Init.VSPolarity = LTDC_VSPOLARITY_AL;
+  hltdc.Init.DEPolarity = LTDC_DEPOLARITY_AL;
+  hltdc.Init.PCPolarity = LTDC_PCPOLARITY_IPC;
+  hltdc.Init.HorizontalSync = 0;
+  hltdc.Init.VerticalSync = 0;
+  hltdc.Init.AccumulatedHBP = 1;
+  hltdc.Init.AccumulatedVBP = 1;
+  hltdc.Init.AccumulatedActiveW = 201;
+  hltdc.Init.AccumulatedActiveH = 481;
+  hltdc.Init.TotalWidth = 202;
+  hltdc.Init.TotalHeigh = 482;
+  hltdc.Init.Backcolor.Blue = 0;
+  hltdc.Init.Backcolor.Green = 0;
+  hltdc.Init.Backcolor.Red = 0;
+  if (HAL_LTDC_Init(&hltdc) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  pLayerCfg.WindowX0 = 0;
+  pLayerCfg.WindowX1 = 200;
+  pLayerCfg.WindowY0 = 0;
+  pLayerCfg.WindowY1 = 480;
+  pLayerCfg.PixelFormat = LTDC_PIXEL_FORMAT_RGB565;
+  pLayerCfg.Alpha = 255;
+  pLayerCfg.Alpha0 = 0;
+  pLayerCfg.BlendingFactor1 = LTDC_BLENDING_FACTOR1_PAxCA;
+  pLayerCfg.BlendingFactor2 = LTDC_BLENDING_FACTOR2_PAxCA;
+  pLayerCfg.FBStartAdress = 0xC0000000;
+  pLayerCfg.ImageWidth = 200;
+  pLayerCfg.ImageHeight = 480;
+  pLayerCfg.Backcolor.Blue = 0;
+  pLayerCfg.Backcolor.Green = 0;
+  pLayerCfg.Backcolor.Red = 0;
+  if (HAL_LTDC_ConfigLayer(&hltdc, &pLayerCfg, 0) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /* USER CODE BEGIN LTDC_Init 2 */
+
+  /* USER CODE END LTDC_Init 2 */
+
+}
+
+void HAL_LTDC_MspInit(LTDC_HandleTypeDef* ltdcHandle)
+{
+
+  if(ltdcHandle->Instance==LTDC)
+  {
+  /* USER CODE BEGIN LTDC_MspInit 0 */
+
+  /* USER CODE END LTDC_MspInit 0 */
+    /* LTDC clock enable */
+    __HAL_RCC_LTDC_CLK_ENABLE();
+
+    /* LTDC interrupt Init */
+    HAL_NVIC_SetPriority(LTDC_IRQn, 5, 0);
+    HAL_NVIC_EnableIRQ(LTDC_IRQn);
+  /* USER CODE BEGIN LTDC_MspInit 1 */
+
+  /* USER CODE END LTDC_MspInit 1 */
+  }
+}
+
+void HAL_LTDC_MspDeInit(LTDC_HandleTypeDef* ltdcHandle)
+{
+
+  if(ltdcHandle->Instance==LTDC)
+  {
+  /* USER CODE BEGIN LTDC_MspDeInit 0 */
+
+  /* USER CODE END LTDC_MspDeInit 0 */
+    /* Peripheral clock disable */
+    __HAL_RCC_LTDC_CLK_DISABLE();
+
+    /* LTDC interrupt Deinit */
+    HAL_NVIC_DisableIRQ(LTDC_IRQn);
+  /* USER CODE BEGIN LTDC_MspDeInit 1 */
+
+  /* USER CODE END LTDC_MspDeInit 1 */
+  }
+}
+
+/* USER CODE BEGIN 1 */
+
+/* USER CODE END 1 */
diff --git a/Core/Src/main.c b/Core/Src/main.c
new file mode 100644
index 0000000..dedebee
--- /dev/null
+++ b/Core/Src/main.c
@@ -0,0 +1,276 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file           : main.c
+  * @brief          : Main program body
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2022 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+#include "cmsis_os.h"
+#include "crc.h"
+#include "dma2d.h"
+#include "dsihost.h"
+#include "fatfs.h"
+#include "i2c.h"
+#include "ltdc.h"
+#include "quadspi.h"
+#include "sai.h"
+#include "sdio.h"
+#include "tim.h"
+#include "usart.h"
+#include "usb_host.h"
+#include "gpio.h"
+#include "fmc.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+#include "my_lcd.h"
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN PTD */
+/* USER CODE END PTD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+
+/* USER CODE BEGIN PV */
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+void SystemClock_Config(void);
+void PeriphCommonClock_Config(void);
+void MX_FREERTOS_Init(void);
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+/* USER CODE END 0 */
+
+/**
+  * @brief  The application entry point.
+  * @retval int
+  */
+int main(void)
+{
+  /* USER CODE BEGIN 1 */
+#if 1
+  HAL_Init();
+  SystemClock_Config();
+  MY_LCD_Init();
+#else
+  /* USER CODE END 1 */
+
+  /* MCU Configuration--------------------------------------------------------*/
+
+  /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
+  HAL_Init();
+
+  /* USER CODE BEGIN Init */
+
+  /* USER CODE END Init */
+
+  /* Configure the system clock */
+  SystemClock_Config();
+
+/* Configure the peripherals common clocks */
+  PeriphCommonClock_Config();
+
+  /* USER CODE BEGIN SysInit */
+  /* USER CODE END SysInit */
+
+  /* Initialize all configured peripherals */
+  MX_GPIO_Init();
+  MX_CRC_Init();
+  MX_DMA2D_Init();
+  MX_DSIHOST_DSI_Init();
+  MX_FMC_Init();
+  MX_I2C1_Init();
+  MX_I2C2_Init();
+  MX_LTDC_Init();
+  MX_QUADSPI_Init();
+  MX_SAI1_Init();
+  MX_SDIO_SD_Init();
+  MX_TIM1_Init();
+  MX_USART3_UART_Init();
+  MX_USART6_UART_Init();
+  MX_FATFS_Init();
+  /* USER CODE BEGIN 2 */
+#endif
+  /* USER CODE END 2 */
+
+  /* Init scheduler */
+  osKernelInitialize();  /* Call init function for freertos objects (in freertos.c) */
+  MX_FREERTOS_Init();
+
+  /* Start scheduler */
+  osKernelStart();
+
+  /* We should never get here as control is now taken by the scheduler */
+  /* Infinite loop */
+  /* USER CODE BEGIN WHILE */
+  while (1)
+  {
+    /* USER CODE END WHILE */
+
+    /* USER CODE BEGIN 3 */
+  }
+  /* USER CODE END 3 */
+}
+
+/**
+  * @brief System Clock Configuration
+  * @retval None
+  */
+void SystemClock_Config(void)
+{
+  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+
+  /** Configure the main internal regulator output voltage
+  */
+  __HAL_RCC_PWR_CLK_ENABLE();
+  __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
+
+  /** Initializes the RCC Oscillators according to the specified parameters
+  * in the RCC_OscInitTypeDef structure.
+  */
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
+  RCC_OscInitStruct.HSEState = RCC_HSE_ON;
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
+  RCC_OscInitStruct.PLL.PLLM = 8;
+  RCC_OscInitStruct.PLL.PLLN = 360;
+  RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
+  RCC_OscInitStruct.PLL.PLLQ = 7;
+  RCC_OscInitStruct.PLL.PLLR = 6;
+  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
+  {
+    Error_Handler();
+  }
+
+  /** Activate the Over-Drive mode
+  */
+  if (HAL_PWREx_EnableOverDrive() != HAL_OK)
+  {
+    Error_Handler();
+  }
+
+  /** Initializes the CPU, AHB and APB buses clocks
+  */
+  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
+                              |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
+  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4;
+  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;
+
+  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK)
+  {
+    Error_Handler();
+  }
+}
+
+/**
+  * @brief Peripherals Common Clock Configuration
+  * @retval None
+  */
+void PeriphCommonClock_Config(void)
+{
+  RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
+
+  /** Initializes the peripherals clock
+  */
+  PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_SAI_PLLSAI|RCC_PERIPHCLK_SDIO
+                              |RCC_PERIPHCLK_CLK48|RCC_PERIPHCLK_LTDC;
+  PeriphClkInitStruct.PLLSAI.PLLSAIN = 192;
+  PeriphClkInitStruct.PLLSAI.PLLSAIR = 2;
+  PeriphClkInitStruct.PLLSAI.PLLSAIQ = 2;
+  PeriphClkInitStruct.PLLSAI.PLLSAIP = RCC_PLLSAIP_DIV4;
+  PeriphClkInitStruct.PLLSAIDivQ = 1;
+  PeriphClkInitStruct.PLLSAIDivR = RCC_PLLSAIDIVR_4;
+  PeriphClkInitStruct.Clk48ClockSelection = RCC_CLK48CLKSOURCE_PLLSAIP;
+  PeriphClkInitStruct.SdioClockSelection = RCC_SDIOCLKSOURCE_CLK48;
+  if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
+  {
+    Error_Handler();
+  }
+}
+
+/* USER CODE BEGIN 4 */
+
+/* USER CODE END 4 */
+
+/**
+  * @brief  Period elapsed callback in non blocking mode
+  * @note   This function is called  when TIM6 interrupt took place, inside
+  * HAL_TIM_IRQHandler(). It makes a direct call to HAL_IncTick() to increment
+  * a global variable "uwTick" used as application time base.
+  * @param  htim : TIM handle
+  * @retval None
+  */
+void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
+{
+  /* USER CODE BEGIN Callback 0 */
+
+  /* USER CODE END Callback 0 */
+  if (htim->Instance == TIM6) {
+    HAL_IncTick();
+  }
+  /* USER CODE BEGIN Callback 1 */
+
+  /* USER CODE END Callback 1 */
+}
+
+/**
+  * @brief  This function is executed in case of error occurrence.
+  * @retval None
+  */
+void Error_Handler(void)
+{
+  /* USER CODE BEGIN Error_Handler_Debug */
+  /* User can add his own implementation to report the HAL error return state */
+  __disable_irq();
+  while (1)
+  {
+  }
+  /* USER CODE END Error_Handler_Debug */
+}
+
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  Reports the name of the source file and the source line number
+  *         where the assert_param error has occurred.
+  * @param  file: pointer to the source file name
+  * @param  line: assert_param error line source number
+  * @retval None
+  */
+void assert_failed(uint8_t *file, uint32_t line)
+{
+  /* USER CODE BEGIN 6 */
+  /* User can add his own implementation to report the file name and line number,
+     ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
+  /* USER CODE END 6 */
+}
+#endif /* USE_FULL_ASSERT */
diff --git a/Core/Src/my_lcd.c b/Core/Src/my_lcd.c
new file mode 100644
index 0000000..60aaf6c
--- /dev/null
+++ b/Core/Src/my_lcd.c
@@ -0,0 +1,222 @@
+#include "my_lcd.h"
+
+#include "stm32469i_discovery_lcd.h"
+#include "stm32469i_discovery_sdram.h"
+
+#include "image_320x240_argb8888.h"
+#include "life_augmented_argb8888.h"
+
+extern LTDC_HandleTypeDef hltdc_eval;
+extern DMA2D_HandleTypeDef hdma2d_eval;
+
+#define LAYER0_ADDRESS               (LCD_FB_START_ADDRESS)
+
+static int32_t  front_buffer   = 0;
+static int32_t  pend_buffer   = -1;
+static uint32_t ImageIndex    = 0;
+
+static const uint32_t * Images[] =
+{
+  image_320x240_argb8888,
+  life_augmented_argb8888,
+};
+
+static const uint32_t Buffers[] =
+{
+  LAYER0_ADDRESS,
+  LAYER0_ADDRESS + (800*480*4),
+};
+
+static void OnError_Handler(uint32_t condition);
+static void LCD_BriefDisplay(void);
+static void CopyBuffer(uint32_t *pSrc, uint32_t *pDst, uint16_t x, uint16_t y, uint16_t xsize, uint16_t ysize);
+
+void MY_LCD_Init() {
+  uint8_t  lcd_status = LCD_OK;
+
+  lcd_status = BSP_LCD_Init();
+  OnError_Handler(lcd_status != LCD_OK);
+
+  BSP_LCD_LayerDefaultInit(0, LAYER0_ADDRESS);
+  BSP_LCD_SelectLayer(0);
+
+  /* Set LTDC Line Event  */
+  HAL_LTDC_ProgramLineEvent(&hltdc_eval, 0);
+
+  /* Display example brief   */
+  LCD_BriefDisplay();
+
+  /* Copy Buffer 0 into buffer 1, so only image area to be redrawn later */
+  CopyBuffer((uint32_t *)Buffers[0], (uint32_t *)Buffers[1], 0, 0, 800, 480);
+}
+
+void MY_LCD_Tick() {
+	if(pend_buffer < 0)
+	{
+	  /* Prepare back buffer */
+	  CopyBuffer((uint32_t *)Images[ImageIndex++], (uint32_t *)Buffers[1- front_buffer], 240, 160, 320, 240);
+	  pend_buffer = 1- front_buffer;
+
+	  if(ImageIndex >= 2)
+	  {
+		ImageIndex = 0;
+	  }
+
+	  /* Wait some time before switching to next stage */
+	  HAL_Delay(2000);
+	}
+}
+
+void My_SystemClock_Config(void)
+{
+  RCC_ClkInitTypeDef RCC_ClkInitStruct;
+  RCC_OscInitTypeDef RCC_OscInitStruct;
+  HAL_StatusTypeDef ret = HAL_OK;
+
+  /* Enable Power Control clock */
+  __HAL_RCC_PWR_CLK_ENABLE();
+
+  /* The voltage scaling allows optimizing the power consumption when the device is
+     clocked below the maximum system frequency, to update the voltage scaling value
+     regarding system frequency refer to product datasheet.  */
+  __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
+
+  /* Enable HSE Oscillator and activate PLL with HSE as source */
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
+  RCC_OscInitStruct.HSEState = RCC_HSE_ON;
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
+#if defined(USE_STM32469I_DISCO_REVA)
+  RCC_OscInitStruct.PLL.PLLM = 25;
+#else
+  RCC_OscInitStruct.PLL.PLLM = 8;
+#endif /* USE_STM32469I_DISCO_REVA */
+  RCC_OscInitStruct.PLL.PLLN = 360;
+  RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
+  RCC_OscInitStruct.PLL.PLLQ = 7;
+  RCC_OscInitStruct.PLL.PLLR = 6;
+
+  ret = HAL_RCC_OscConfig(&RCC_OscInitStruct);
+  if(ret != HAL_OK)
+  {
+    while(1) { ; }
+  }
+
+  /* Activate the OverDrive to reach the 180 MHz Frequency */
+  ret = HAL_PWREx_EnableOverDrive();
+  if(ret != HAL_OK)
+  {
+    while(1) { ; }
+  }
+
+  /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
+  RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
+  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4;
+  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;
+
+  ret = HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5);
+  if(ret != HAL_OK)
+  {
+    while(1) { ; }
+  }
+}
+
+
+/**
+  * @brief  On Error Handler on condition TRUE.
+  * @param  condition : Can be TRUE or FALSE
+  * @retval None
+  */
+static void OnError_Handler(uint32_t condition)
+{
+  if(condition)
+  {
+    BSP_LED_On(LED3);
+    while(1) { ; } /* Blocking on error */
+  }
+}
+
+/**
+  * @brief  Line Event callback.
+  * @param  hltdc: pointer to a LTDC_HandleTypeDef structure that contains
+  *                the configuration information for the LTDC.
+  * @retval None
+  */
+void HAL_LTDC_LineEventCallback(LTDC_HandleTypeDef *hltdc)
+{
+  if(pend_buffer >= 0)
+  {
+    LTDC_LAYER(hltdc, 0)->CFBAR = ((uint32_t)Buffers[pend_buffer]);
+    __HAL_LTDC_RELOAD_IMMEDIATE_CONFIG(hltdc);
+
+    front_buffer = pend_buffer;
+    pend_buffer = -1;
+  }
+
+  HAL_LTDC_ProgramLineEvent(hltdc, 0);
+}
+
+/**
+  * @brief  Display Example description.
+  * @param  None
+  * @retval None
+  */
+static void LCD_BriefDisplay(void)
+{
+  BSP_LCD_Clear(LCD_COLOR_WHITE);
+  BSP_LCD_SetBackColor(LCD_COLOR_BLUE);
+  BSP_LCD_SetTextColor(LCD_COLOR_BLUE);
+  BSP_LCD_FillRect(0, 0, 800, 112);
+  BSP_LCD_SetTextColor(LCD_COLOR_WHITE);
+  BSP_LCD_DisplayStringAtLine(1, (uint8_t *)"        LCD_DSI_VideoMode_DoubleBuffering");
+  BSP_LCD_SetFont(&Font16);
+  BSP_LCD_DisplayStringAtLine(4, (uint8_t *)"This example shows how to display images on LCD DSI using two buffers");
+  BSP_LCD_DisplayStringAtLine(5, (uint8_t *)"one for display and the other for draw     ");
+
+}
+
+/**
+  * @brief  Converts a line to an ARGB8888 pixel format.
+  * @param  pSrc: Pointer to source buffer
+  * @param  pDst: Output color
+  * @param  xSize: Buffer width
+  * @param  ColorMode: Input color mode
+  * @retval None
+  */
+static void CopyBuffer(uint32_t *pSrc, uint32_t *pDst, uint16_t x, uint16_t y, uint16_t xsize, uint16_t ysize)
+{
+
+  uint32_t destination = (uint32_t)pDst + (y * 800 + x) * 4;
+  uint32_t source      = (uint32_t)pSrc;
+
+  /*##-1- Configure the DMA2D Mode, Color Mode and output offset #############*/
+  hdma2d_eval.Init.Mode         = DMA2D_M2M;
+  hdma2d_eval.Init.ColorMode    = DMA2D_ARGB8888;
+  hdma2d_eval.Init.OutputOffset = 800 - xsize;
+
+  /*##-2- DMA2D Callbacks Configuration ######################################*/
+  hdma2d_eval.XferCpltCallback  = NULL;
+
+  /*##-3- Foreground Configuration ###########################################*/
+  hdma2d_eval.LayerCfg[1].AlphaMode = DMA2D_NO_MODIF_ALPHA;
+  hdma2d_eval.LayerCfg[1].InputAlpha = 0xFF;
+  hdma2d_eval.LayerCfg[1].InputColorMode = DMA2D_INPUT_ARGB8888;
+  hdma2d_eval.LayerCfg[1].InputOffset = 0;
+
+  hdma2d_eval.Instance          = DMA2D;
+
+  /* DMA2D Initialization */
+  if(HAL_DMA2D_Init(&hdma2d_eval) == HAL_OK)
+  {
+    if(HAL_DMA2D_ConfigLayer(&hdma2d_eval, 1) == HAL_OK)
+    {
+      if (HAL_DMA2D_Start(&hdma2d_eval, source, destination, xsize, ysize) == HAL_OK)
+      {
+        /* Polling For DMA transfer */
+        HAL_DMA2D_PollForTransfer(&hdma2d_eval, 100);
+      }
+    }
+  }
+}
diff --git a/Core/Src/my_stm32f4xx_hal_msp.c b/Core/Src/my_stm32f4xx_hal_msp.c
new file mode 100644
index 0000000..2deb592
--- /dev/null
+++ b/Core/Src/my_stm32f4xx_hal_msp.c
@@ -0,0 +1,53 @@
+/**
+  ******************************************************************************
+  * @file    LCD_DSI/LCD_DSI_VideoMode_DoubleBuffering/Src/stm32f4xx_hal_msp.c
+  * @author  MCD Application Team
+  * @brief   HAL MSP module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+
+/** @addtogroup STM32F4xx_HAL_Examples
+  * @{
+  */
+
+/** @defgroup HAL_MSP
+  * @brief HAL MSP module.
+  * @{
+  */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup HAL_MSP_Private_Functions
+  * @{
+  */
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
diff --git a/Core/Src/my_stm32f4xx_it.c b/Core/Src/my_stm32f4xx_it.c
new file mode 100644
index 0000000..c5b6ea0
--- /dev/null
+++ b/Core/Src/my_stm32f4xx_it.c
@@ -0,0 +1,166 @@
+/**
+  ******************************************************************************
+  * @file    LCD_DSI/LCD_DSI_VideoMode_DoubleBuffering/Src/stm32f4xx_it.c 
+  * @author  MCD Application Team
+  * @brief   Main Interrupt Service Routines.
+  *          This file provides template for all exceptions handler and
+  *          peripherals interrupt service routine.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+#include "stm32f4xx_it.h"
+
+/** @addtogroup STM32F4xx_HAL_Examples
+  * @{
+  */
+
+/** @addtogroup LCD_DSI_Video_OneLayer
+  * @{
+  */
+
+/* Private typedef -----------------------------------------------------------*/
+extern LTDC_HandleTypeDef hltdc_eval;    
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/******************************************************************************/
+/*            Cortex-M4 Processor Exceptions Handlers                         */
+/******************************************************************************/
+
+/**
+  * @brief   This function handles NMI exception.
+  * @param  None
+  * @retval None
+  */
+void NMI_Handler(void)
+{
+}
+
+/**
+  * @brief  This function handles Hard Fault exception.
+  * @param  None
+  * @retval None
+  */
+void HardFault_Handler(void)
+{
+  /* Go to infinite loop when Hard Fault exception occurs */
+  while (1)
+  {
+  }
+}
+
+/**
+  * @brief  This function handles Memory Manage exception.
+  * @param  None
+  * @retval None
+  */
+void MemManage_Handler(void)
+{
+  /* Go to infinite loop when Memory Manage exception occurs */
+  while (1)
+  {
+  }
+}
+
+/**
+  * @brief  This function handles Bus Fault exception.
+  * @param  None
+  * @retval None
+  */
+void BusFault_Handler(void)
+{
+  /* Go to infinite loop when Bus Fault exception occurs */
+  while (1)
+  {
+  }
+}
+
+/**
+  * @brief  This function handles Usage Fault exception.
+  * @param  None
+  * @retval None
+  */
+void UsageFault_Handler(void)
+{
+  /* Go to infinite loop when Usage Fault exception occurs */
+  while (1)
+  {
+  }
+}
+
+/**
+  * @brief  This function handles SVCall exception.
+  * @param  None
+  * @retval None
+  */
+void SVC_Handler(void)
+{
+}
+
+/**
+  * @brief  This function handles Debug Monitor exception.
+  * @param  None
+  * @retval None
+  */
+void DebugMon_Handler(void)
+{
+}
+
+/**
+  * @brief  This function handles PendSVC exception.
+  * @param  None
+  * @retval None
+  */
+void PendSV_Handler(void)
+{
+}
+
+/**
+  * @brief  This function handles SysTick Handler.
+  * @param  None
+  * @retval None
+  */
+void SysTick_Handler(void)
+{
+  HAL_IncTick();
+}
+
+/******************************************************************************/
+/*                 STM32F4xx Peripherals Interrupt Handlers                   */
+/*  Add here the Interrupt Handler for the used peripheral(s) (PPP), for the  */
+/*  available peripheral interrupt handler's name please refer to the startup */
+/*  file (startup_stm32f4xx.s).                                               */
+/******************************************************************************/
+
+/**
+  * @brief  This function handles LTDC interrupt request.
+  * @param  None
+  * @retval None
+  */
+void LTDC_IRQHandler(void)
+{
+  HAL_LTDC_IRQHandler(&hltdc_eval);
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
diff --git a/Core/Src/my_system_stm32f4xx.c b/Core/Src/my_system_stm32f4xx.c
new file mode 100644
index 0000000..cf8ea07
--- /dev/null
+++ b/Core/Src/my_system_stm32f4xx.c
@@ -0,0 +1,433 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32f4xx.c
+  * @author  MCD Application Team
+  * @brief   CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
+  *
+  *   This file provides two functions and one global variable to be called from 
+  *   user application:
+  *      - SystemInit(): This function is called at startup just after reset and 
+  *                      before branch to main program. This call is made inside
+  *                      the "startup_stm32f4xx.s" file.
+  *
+  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+  *                                  by the user application to setup the SysTick 
+  *                                  timer or configure other parameters.
+  *                                     
+  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+  *                                 be called whenever the core clock is changed
+  *                                 during program execution.
+  *
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32f4xx_system
+  * @{
+  */  
+  
+/** @addtogroup STM32F4xx_System_Private_Includes
+  * @{
+  */
+
+
+#include "stm32f4xx.h"
+
+#if !defined  (HSE_VALUE) 
+#if defined(USE_STM32469I_DISCO_REVA) 
+  #define HSE_VALUE    ((uint32_t)25000000)  /*!< Default value of the External oscillator in Hz */
+#else
+  #define HSE_VALUE    ((uint32_t)8000000)   /*!< Default value of the External oscillator in Hz */
+#endif /* USE_STM32469I_DISCO_REVA */
+#endif /* HSE_VALUE */
+
+#if !defined  (HSI_VALUE)
+  #define HSI_VALUE    ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F4xx_System_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F4xx_System_Private_Defines
+  * @{
+  */
+
+/************************* Miscellaneous Configuration ************************/
+/*!< Uncomment the following line if you need to use external SDRAM mounted
+     on DK as data memory  */
+/* #define DATA_IN_ExtSDRAM */
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET  0x00 /*!< Vector Table base offset field. 
+                                   This value must be a multiple of 0x200. */
+/******************************************************************************/
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F4xx_System_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F4xx_System_Private_Variables
+  * @{
+  */
+  /* This variable is updated in three ways:
+      1) by calling CMSIS function SystemCoreClockUpdate()
+      2) by calling HAL API function HAL_RCC_GetHCLKFreq()
+      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency 
+         Note: If you use this function to configure the system clock; then there
+               is no need to call the 2 first functions listed above, since SystemCoreClock
+               variable is updated automatically.
+  */
+uint32_t SystemCoreClock = 16000000;
+const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
+const uint8_t APBPrescTable[8]  = {0, 0, 0, 0, 1, 2, 3, 4};
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F4xx_System_Private_FunctionPrototypes
+  * @{
+  */
+
+#if defined (DATA_IN_ExtSDRAM)
+  static void SystemInit_ExtMemCtl(void); 
+#endif /* DATA_IN_ExtSDRAM */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F4xx_System_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Setup the microcontroller system
+  *         Initialize the FPU setting, vector table location and External memory 
+  *         configuration.
+  * @param  None
+  * @retval None
+  */
+void SystemInit(void)
+{
+  /* FPU settings ------------------------------------------------------------*/
+  #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+    SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2));  /* set CP10 and CP11 Full Access */
+  #endif
+  /* Reset the RCC clock configuration to the default reset state ------------*/
+  /* Set HSION bit */
+  RCC->CR |= (uint32_t)0x00000001;
+
+  /* Reset CFGR register */
+  RCC->CFGR = 0x00000000;
+
+  /* Reset HSEON, CSSON and PLLON bits */
+  RCC->CR &= (uint32_t)0xFEF6FFFF;
+
+  /* Reset PLLCFGR register */
+  RCC->PLLCFGR = 0x24003010;
+
+  /* Reset HSEBYP bit */
+  RCC->CR &= (uint32_t)0xFFFBFFFF;
+
+  /* Disable all interrupts */
+  RCC->CIR = 0x00000000;
+
+#if defined (DATA_IN_ExtSDRAM)
+  SystemInit_ExtMemCtl(); 
+#endif /* DATA_IN_ExtSDRAM */
+
+  /* Configure the Vector Table location add offset address ------------------*/
+#ifdef VECT_TAB_SRAM
+  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
+#else
+  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
+#endif
+}
+
+/**
+   * @brief  Update SystemCoreClock variable according to Clock Register Values.
+  *         The SystemCoreClock variable contains the core clock (HCLK), it can
+  *         be used by the user application to setup the SysTick timer or configure
+  *         other parameters.
+  *           
+  * @note   Each time the core clock (HCLK) changes, this function must be called
+  *         to update SystemCoreClock variable value. Otherwise, any configuration
+  *         based on this variable will be incorrect.         
+  *     
+  * @note   - The system frequency computed by this function is not the real 
+  *           frequency in the chip. It is calculated based on the predefined 
+  *           constant and the selected clock source:
+  *             
+  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
+  *                                              
+  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
+  *                          
+  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) 
+  *             or HSI_VALUE(*) multiplied/divided by the PLL factors.
+  *         
+  *         (*) HSI_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value
+  *             16 MHz) but the real value may vary depending on the variations
+  *             in voltage and temperature.   
+  *    
+  *         (**) HSE_VALUE is a constant defined in stm32f4xx_hal_conf.h file (its value
+  *              depends on the application requirements), user has to ensure that HSE_VALUE
+  *              is same as the real frequency of the crystal used. Otherwise, this function
+  *              may have wrong result.
+  *                
+  *         - The result of this function could be not correct when using fractional
+  *           value for HSE crystal.
+  *     
+  * @param  None
+  * @retval None
+  */
+void SystemCoreClockUpdate(void)
+{
+  uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;
+  
+  /* Get SYSCLK source -------------------------------------------------------*/
+  tmp = RCC->CFGR & RCC_CFGR_SWS;
+
+  switch (tmp)
+  {
+    case 0x00:  /* HSI used as system clock source */
+      SystemCoreClock = HSI_VALUE;
+      break;
+    case 0x04:  /* HSE used as system clock source */
+      SystemCoreClock = HSE_VALUE;
+      break;
+    case 0x08:  /* PLL used as system clock source */
+
+      /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N
+         SYSCLK = PLL_VCO / PLL_P
+         */    
+      pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;
+      pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
+      
+      if (pllsource != 0)
+      {
+        /* HSE used as PLL clock source */
+        pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
+      }
+      else
+      {
+        /* HSI used as PLL clock source */
+        pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
+      }
+
+      pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2;
+      SystemCoreClock = pllvco/pllp;
+      break;
+    default:
+      SystemCoreClock = HSI_VALUE;
+      break;
+  }
+  /* Compute HCLK frequency --------------------------------------------------*/
+  /* Get HCLK prescaler */
+  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
+  /* HCLK frequency */
+  SystemCoreClock >>= tmp;
+}
+
+#if defined (DATA_IN_ExtSDRAM)
+/**
+  * @brief  Setup the external memory controller.
+  *         Called in startup_stm32f4xx.s before jump to main.
+  *         This function configures the external memories (SRAM/SDRAM)
+  *         This SRAM/SDRAM will be used as program data memory (including heap and stack).
+  * @param  None
+  * @retval None
+  */
+void SystemInit_ExtMemCtl(void)
+{
+  register uint32_t tmpreg = 0, timeout = 0xFFFF;
+  register __IO uint32_t index;
+
+  /* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH, and GPIOI interface
+  clock */
+  RCC->AHB1ENR |= 0x000001FC;
+
+  /* Connect PCx pins to FMC Alternate function */
+  GPIOC->AFR[0]  = 0x0000000C;
+  GPIOC->AFR[1]  = 0x00000000;
+  /* Configure PCx pins in Alternate function mode */ 
+  GPIOC->MODER   = 0x00000002;
+  /* Configure PCx pins speed to 100 MHz */
+  GPIOC->OSPEEDR = 0x00000003;
+  /* Configure PCx pins Output type to push-pull */
+  GPIOC->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PCx pins */ 
+  GPIOC->PUPDR   = 0x00000000;
+
+  /* Connect PDx pins to FMC Alternate function */
+  GPIOD->AFR[0]  = 0x000000CC;
+  GPIOD->AFR[1]  = 0xCC000CCC;
+  /* Configure PDx pins in Alternate function mode */ 
+  GPIOD->MODER   = 0xA02A000A;
+  /* Configure PDx pins speed to 100 MHz */
+  GPIOD->OSPEEDR = 0xF03F000F;
+  /* Configure PDx pins Output type to push-pull */
+  GPIOD->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PDx pins */ 
+  GPIOD->PUPDR   = 0x00000000;
+  
+  /* Connect PEx pins to FMC Alternate function */
+  GPIOE->AFR[0]  = 0xC00000CC;
+  GPIOE->AFR[1]  = 0xCCCCCCCC;
+  /* Configure PEx pins in Alternate function mode */ 
+  GPIOE->MODER   = 0xAAAA800A;
+  /* Configure PEx pins speed to 100 MHz */
+  GPIOE->OSPEEDR = 0xFFFFC00F;
+  /* Configure PEx pins Output type to push-pull */
+  GPIOE->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PEx pins */ 
+  GPIOE->PUPDR   = 0x00000000;
+  
+  /* Connect PFx pins to FMC Alternate function */
+  GPIOF->AFR[0]  = 0x00CCCCCC;
+  GPIOF->AFR[1]  = 0xCCCCC000;
+  /* Configure PFx pins in Alternate function mode */ 
+  GPIOF->MODER   = 0xAA800AAA;
+  /* Configure PFx pins speed to 100 MHz */
+  GPIOF->OSPEEDR = 0xFFC00FFF;
+  /* Configure PFx pins Output type to push-pull */
+  GPIOF->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PFx pins */ 
+  GPIOF->PUPDR   = 0x00000000;
+  
+  /* Connect PGx pins to FMC Alternate function */
+  GPIOG->AFR[0]  = 0x00CC00CC;
+  GPIOG->AFR[1]  = 0xC000000C;
+  /* Configure PGx pins in Alternate function mode */ 
+  GPIOG->MODER   = 0x80020A0A;
+  /* Configure PGx pins speed to 100 MHz */
+  GPIOG->OSPEEDR = 0xC0030F0F;
+  /* Configure PGx pins Output type to push-pull */
+  GPIOG->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PGx pins */ 
+  GPIOG->PUPDR   = 0x00000000;
+  
+  /* Connect PHx pins to FMC Alternate function */
+  GPIOH->AFR[0]  = 0x0000CC00;
+  GPIOH->AFR[1]  = 0xCCCCCCCC;
+  /* Configure PHx pins in Alternate function mode */ 
+  GPIOH->MODER   = 0xAAAA00A0;
+  /* Configure PHx pins speed to 100 MHz */
+  GPIOH->OSPEEDR = 0xFFFF00F0;
+  /* Configure PHx pins Output type to push-pull */
+  GPIOH->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PHx pins */ 
+  GPIOH->PUPDR   = 0x00000000;
+  
+  /* Connect PIx pins to FMC Alternate function */
+  GPIOI->AFR[0]  = 0xCCCCCCCC;
+  GPIOI->AFR[1]  = 0x00000CC0;
+  /* Configure PIx pins in Alternate function mode */ 
+  GPIOI->MODER   = 0x0028AAAA;
+  /* Configure PIx pins speed to 100 MHz */
+  GPIOI->OSPEEDR = 0x003CFFFF;
+  /* Configure PIx pins Output type to push-pull */
+  GPIOI->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PIx pins */ 
+  GPIOI->PUPDR   = 0x00000000;
+
+  /* FMC Configuration */
+  /* Enable the FMC interface clock */
+  RCC->AHB3ENR |= 0x00000001;
+  
+  /* Configure and enable SDRAM bank2 */
+  FMC_Bank5_6->SDCR[0] = 0x000019E4;
+  FMC_Bank5_6->SDTR[0] = 0x01115351;
+  
+  /* SDRAM initialization sequence */
+  /* Clock enable command */
+  FMC_Bank5_6->SDCMR = 0x00000011; 
+  tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 
+  while((tmpreg != 0) && (timeout-- > 0))
+  {
+    tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 
+  }
+
+  /* Delay */
+  for (index = 0; index<1000; index++);
+  
+  /* PALL command */
+  FMC_Bank5_6->SDCMR = 0x00000012;     
+  tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
+  timeout = 0xFFFF;
+  while((tmpreg != 0) && (timeout-- > 0))
+  {
+    tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 
+  }
+  
+  /* Auto refresh command */
+  FMC_Bank5_6->SDCMR = 0x000000F3;
+  tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
+  timeout = 0xFFFF;
+  while((tmpreg != 0) && (timeout-- > 0))
+  {
+    tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 
+  }
+ 
+  /* MRD register program */
+  FMC_Bank5_6->SDCMR = 0x00046014;
+  tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
+  timeout = 0xFFFF;
+  while((tmpreg != 0) && (timeout-- > 0))
+  {
+    tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 
+  } 
+  
+  /* Set refresh count */
+  tmpreg = FMC_Bank5_6->SDRTR;
+  FMC_Bank5_6->SDRTR = (tmpreg | (0x0000056A<<1));
+  
+  /* Disable write protection */
+  tmpreg = FMC_Bank5_6->SDCR[0]; 
+  FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF);
+}
+#endif /* DATA_IN_ExtSDRAM */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
diff --git a/Core/Src/quadspi.c b/Core/Src/quadspi.c
new file mode 100644
index 0000000..b04511a
--- /dev/null
+++ b/Core/Src/quadspi.c
@@ -0,0 +1,140 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    quadspi.c
+  * @brief   This file provides code for the configuration
+  *          of the QUADSPI instances.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2022 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+/* Includes ------------------------------------------------------------------*/
+#include "quadspi.h"
+
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+QSPI_HandleTypeDef hqspi;
+
+/* QUADSPI init function */
+void MX_QUADSPI_Init(void)
+{
+
+  /* USER CODE BEGIN QUADSPI_Init 0 */
+
+  /* USER CODE END QUADSPI_Init 0 */
+
+  /* USER CODE BEGIN QUADSPI_Init 1 */
+
+  /* USER CODE END QUADSPI_Init 1 */
+  hqspi.Instance = QUADSPI;
+  hqspi.Init.ClockPrescaler = 1;
+  hqspi.Init.FifoThreshold = 1;
+  hqspi.Init.SampleShifting = QSPI_SAMPLE_SHIFTING_HALFCYCLE;
+  hqspi.Init.FlashSize = 24;
+  hqspi.Init.ChipSelectHighTime = QSPI_CS_HIGH_TIME_5_CYCLE;
+  hqspi.Init.ClockMode = QSPI_CLOCK_MODE_0;
+  hqspi.Init.FlashID = QSPI_FLASH_ID_1;
+  hqspi.Init.DualFlash = QSPI_DUALFLASH_DISABLE;
+  if (HAL_QSPI_Init(&hqspi) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /* USER CODE BEGIN QUADSPI_Init 2 */
+
+  /* USER CODE END QUADSPI_Init 2 */
+
+}
+
+void HAL_QSPI_MspInit(QSPI_HandleTypeDef* qspiHandle)
+{
+
+  GPIO_InitTypeDef GPIO_InitStruct = {0};
+  if(qspiHandle->Instance==QUADSPI)
+  {
+  /* USER CODE BEGIN QUADSPI_MspInit 0 */
+
+  /* USER CODE END QUADSPI_MspInit 0 */
+    /* QUADSPI clock enable */
+    __HAL_RCC_QSPI_CLK_ENABLE();
+
+    __HAL_RCC_GPIOB_CLK_ENABLE();
+    __HAL_RCC_GPIOF_CLK_ENABLE();
+    /**QUADSPI GPIO Configuration
+    PB6     ------> QUADSPI_BK1_NCS
+    PF7     ------> QUADSPI_BK1_IO2
+    PF6     ------> QUADSPI_BK1_IO3
+    PF10     ------> QUADSPI_CLK
+    PF9     ------> QUADSPI_BK1_IO1
+    PF8     ------> QUADSPI_BK1_IO0
+    */
+    GPIO_InitStruct.Pin = QSPI_BK1_NCS_Pin;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+    GPIO_InitStruct.Alternate = GPIO_AF10_QSPI;
+    HAL_GPIO_Init(QSPI_BK1_NCS_GPIO_Port, &GPIO_InitStruct);
+
+    GPIO_InitStruct.Pin = QSPI_BK1_IO2_Pin|QSPI_BK1_IO3_Pin|QSPI_CLK_Pin;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+    GPIO_InitStruct.Alternate = GPIO_AF9_QSPI;
+    HAL_GPIO_Init(GPIOF, &GPIO_InitStruct);
+
+    GPIO_InitStruct.Pin = QSPI_BK1_IO1_Pin|QSPI_BK1_IO0_Pin;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+    GPIO_InitStruct.Alternate = GPIO_AF10_QSPI;
+    HAL_GPIO_Init(GPIOF, &GPIO_InitStruct);
+
+  /* USER CODE BEGIN QUADSPI_MspInit 1 */
+
+  /* USER CODE END QUADSPI_MspInit 1 */
+  }
+}
+
+void HAL_QSPI_MspDeInit(QSPI_HandleTypeDef* qspiHandle)
+{
+
+  if(qspiHandle->Instance==QUADSPI)
+  {
+  /* USER CODE BEGIN QUADSPI_MspDeInit 0 */
+
+  /* USER CODE END QUADSPI_MspDeInit 0 */
+    /* Peripheral clock disable */
+    __HAL_RCC_QSPI_CLK_DISABLE();
+
+    /**QUADSPI GPIO Configuration
+    PB6     ------> QUADSPI_BK1_NCS
+    PF7     ------> QUADSPI_BK1_IO2
+    PF6     ------> QUADSPI_BK1_IO3
+    PF10     ------> QUADSPI_CLK
+    PF9     ------> QUADSPI_BK1_IO1
+    PF8     ------> QUADSPI_BK1_IO0
+    */
+    HAL_GPIO_DeInit(QSPI_BK1_NCS_GPIO_Port, QSPI_BK1_NCS_Pin);
+
+    HAL_GPIO_DeInit(GPIOF, QSPI_BK1_IO2_Pin|QSPI_BK1_IO3_Pin|QSPI_CLK_Pin|QSPI_BK1_IO1_Pin
+                          |QSPI_BK1_IO0_Pin);
+
+  /* USER CODE BEGIN QUADSPI_MspDeInit 1 */
+
+  /* USER CODE END QUADSPI_MspDeInit 1 */
+  }
+}
+
+/* USER CODE BEGIN 1 */
+
+/* USER CODE END 1 */
diff --git a/Core/Src/sai.c b/Core/Src/sai.c
new file mode 100644
index 0000000..6af3b05
--- /dev/null
+++ b/Core/Src/sai.c
@@ -0,0 +1,157 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * File Name          : SAI.c
+  * Description        : This file provides code for the configuration
+  *                      of the SAI instances.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2022 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "sai.h"
+
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+SAI_HandleTypeDef hsai_BlockA1;
+
+/* SAI1 init function */
+void MX_SAI1_Init(void)
+{
+
+  /* USER CODE BEGIN SAI1_Init 0 */
+
+  /* USER CODE END SAI1_Init 0 */
+
+  /* USER CODE BEGIN SAI1_Init 1 */
+
+  /* USER CODE END SAI1_Init 1 */
+
+  hsai_BlockA1.Instance = SAI1_Block_A;
+  hsai_BlockA1.Init.Protocol = SAI_FREE_PROTOCOL;
+  hsai_BlockA1.Init.AudioMode = SAI_MODEMASTER_TX;
+  hsai_BlockA1.Init.DataSize = SAI_DATASIZE_8;
+  hsai_BlockA1.Init.FirstBit = SAI_FIRSTBIT_MSB;
+  hsai_BlockA1.Init.ClockStrobing = SAI_CLOCKSTROBING_FALLINGEDGE;
+  hsai_BlockA1.Init.Synchro = SAI_ASYNCHRONOUS;
+  hsai_BlockA1.Init.OutputDrive = SAI_OUTPUTDRIVE_DISABLE;
+  hsai_BlockA1.Init.NoDivider = SAI_MASTERDIVIDER_ENABLE;
+  hsai_BlockA1.Init.FIFOThreshold = SAI_FIFOTHRESHOLD_EMPTY;
+  hsai_BlockA1.Init.ClockSource = SAI_CLKSOURCE_PLLSAI;
+  hsai_BlockA1.Init.AudioFrequency = SAI_AUDIO_FREQUENCY_192K;
+  hsai_BlockA1.Init.SynchroExt = SAI_SYNCEXT_DISABLE;
+  hsai_BlockA1.Init.MonoStereoMode = SAI_STEREOMODE;
+  hsai_BlockA1.Init.CompandingMode = SAI_NOCOMPANDING;
+  hsai_BlockA1.Init.TriState = SAI_OUTPUT_NOTRELEASED;
+  hsai_BlockA1.FrameInit.FrameLength = 8;
+  hsai_BlockA1.FrameInit.ActiveFrameLength = 1;
+  hsai_BlockA1.FrameInit.FSDefinition = SAI_FS_STARTFRAME;
+  hsai_BlockA1.FrameInit.FSPolarity = SAI_FS_ACTIVE_LOW;
+  hsai_BlockA1.FrameInit.FSOffset = SAI_FS_FIRSTBIT;
+  hsai_BlockA1.SlotInit.FirstBitOffset = 0;
+  hsai_BlockA1.SlotInit.SlotSize = SAI_SLOTSIZE_DATASIZE;
+  hsai_BlockA1.SlotInit.SlotNumber = 1;
+  hsai_BlockA1.SlotInit.SlotActive = 0x00000000;
+  if (HAL_SAI_Init(&hsai_BlockA1) != HAL_OK)
+  {
+    Error_Handler();
+  }
+
+  /* USER CODE BEGIN SAI1_Init 2 */
+
+  /* USER CODE END SAI1_Init 2 */
+
+}
+static uint32_t SAI1_client =0;
+
+void HAL_SAI_MspInit(SAI_HandleTypeDef* saiHandle)
+{
+
+  GPIO_InitTypeDef GPIO_InitStruct;
+/* SAI1 */
+    if(saiHandle->Instance==SAI1_Block_A)
+    {
+    /* SAI1 clock enable */
+    if (SAI1_client == 0)
+    {
+       __HAL_RCC_SAI1_CLK_ENABLE();
+    }
+    SAI1_client ++;
+
+    /**SAI1_A_Block_A GPIO Configuration
+    PE4     ------> SAI1_FS_A
+    PE5     ------> SAI1_SCK_A
+    PD6     ------> SAI1_SD_A
+    PG7     ------> SAI1_MCLK_A
+    */
+    GPIO_InitStruct.Pin = SAI1_FSA_Pin|SAI1_SCKA_Pin;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+    GPIO_InitStruct.Alternate = GPIO_AF6_SAI1;
+    HAL_GPIO_Init(GPIOE, &GPIO_InitStruct);
+
+    GPIO_InitStruct.Pin = MIC_DATA_Pin;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+    GPIO_InitStruct.Alternate = GPIO_AF6_SAI1;
+    HAL_GPIO_Init(MIC_DATA_GPIO_Port, &GPIO_InitStruct);
+
+    GPIO_InitStruct.Pin = SAI1_MCLKA_Pin;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+    GPIO_InitStruct.Alternate = GPIO_AF6_SAI1;
+    HAL_GPIO_Init(SAI1_MCLKA_GPIO_Port, &GPIO_InitStruct);
+
+    }
+}
+
+void HAL_SAI_MspDeInit(SAI_HandleTypeDef* saiHandle)
+{
+
+/* SAI1 */
+    if(saiHandle->Instance==SAI1_Block_A)
+    {
+    SAI1_client --;
+    if (SAI1_client == 0)
+      {
+      /* Peripheral clock disable */
+       __HAL_RCC_SAI1_CLK_DISABLE();
+      }
+
+    /**SAI1_A_Block_A GPIO Configuration
+    PE4     ------> SAI1_FS_A
+    PE5     ------> SAI1_SCK_A
+    PD6     ------> SAI1_SD_A
+    PG7     ------> SAI1_MCLK_A
+    */
+    HAL_GPIO_DeInit(GPIOE, SAI1_FSA_Pin|SAI1_SCKA_Pin);
+
+    HAL_GPIO_DeInit(MIC_DATA_GPIO_Port, MIC_DATA_Pin);
+
+    HAL_GPIO_DeInit(SAI1_MCLKA_GPIO_Port, SAI1_MCLKA_Pin);
+
+    }
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
diff --git a/Core/Src/sdio.c b/Core/Src/sdio.c
new file mode 100644
index 0000000..790ba9b
--- /dev/null
+++ b/Core/Src/sdio.c
@@ -0,0 +1,129 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    sdio.c
+  * @brief   This file provides code for the configuration
+  *          of the SDIO instances.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2022 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+/* Includes ------------------------------------------------------------------*/
+#include "sdio.h"
+
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+SD_HandleTypeDef hsd;
+
+/* SDIO init function */
+
+void MX_SDIO_SD_Init(void)
+{
+
+  /* USER CODE BEGIN SDIO_Init 0 */
+
+  /* USER CODE END SDIO_Init 0 */
+
+  /* USER CODE BEGIN SDIO_Init 1 */
+
+  /* USER CODE END SDIO_Init 1 */
+  hsd.Instance = SDIO;
+  hsd.Init.ClockEdge = SDIO_CLOCK_EDGE_RISING;
+  hsd.Init.ClockBypass = SDIO_CLOCK_BYPASS_DISABLE;
+  hsd.Init.ClockPowerSave = SDIO_CLOCK_POWER_SAVE_DISABLE;
+  hsd.Init.BusWide = SDIO_BUS_WIDE_1B;
+  hsd.Init.HardwareFlowControl = SDIO_HARDWARE_FLOW_CONTROL_DISABLE;
+  hsd.Init.ClockDiv = 0;
+  /* USER CODE BEGIN SDIO_Init 2 */
+
+  /* USER CODE END SDIO_Init 2 */
+
+}
+
+void HAL_SD_MspInit(SD_HandleTypeDef* sdHandle)
+{
+
+  GPIO_InitTypeDef GPIO_InitStruct = {0};
+  if(sdHandle->Instance==SDIO)
+  {
+  /* USER CODE BEGIN SDIO_MspInit 0 */
+
+  /* USER CODE END SDIO_MspInit 0 */
+    /* SDIO clock enable */
+    __HAL_RCC_SDIO_CLK_ENABLE();
+
+    __HAL_RCC_GPIOC_CLK_ENABLE();
+    __HAL_RCC_GPIOD_CLK_ENABLE();
+    /**SDIO GPIO Configuration
+    PC12     ------> SDIO_CK
+    PC11     ------> SDIO_D3
+    PC10     ------> SDIO_D2
+    PD2     ------> SDIO_CMD
+    PC9     ------> SDIO_D1
+    PC8     ------> SDIO_D0
+    */
+    GPIO_InitStruct.Pin = uSD_CLK_Pin|uSD_D3_Pin|uSD_D2_Pin|uSD_D1_Pin
+                          |uSD_D0_Pin;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+    GPIO_InitStruct.Alternate = GPIO_AF12_SDIO;
+    HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
+
+    GPIO_InitStruct.Pin = uSD_CMD_Pin;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+    GPIO_InitStruct.Alternate = GPIO_AF12_SDIO;
+    HAL_GPIO_Init(uSD_CMD_GPIO_Port, &GPIO_InitStruct);
+
+  /* USER CODE BEGIN SDIO_MspInit 1 */
+
+  /* USER CODE END SDIO_MspInit 1 */
+  }
+}
+
+void HAL_SD_MspDeInit(SD_HandleTypeDef* sdHandle)
+{
+
+  if(sdHandle->Instance==SDIO)
+  {
+  /* USER CODE BEGIN SDIO_MspDeInit 0 */
+
+  /* USER CODE END SDIO_MspDeInit 0 */
+    /* Peripheral clock disable */
+    __HAL_RCC_SDIO_CLK_DISABLE();
+
+    /**SDIO GPIO Configuration
+    PC12     ------> SDIO_CK
+    PC11     ------> SDIO_D3
+    PC10     ------> SDIO_D2
+    PD2     ------> SDIO_CMD
+    PC9     ------> SDIO_D1
+    PC8     ------> SDIO_D0
+    */
+    HAL_GPIO_DeInit(GPIOC, uSD_CLK_Pin|uSD_D3_Pin|uSD_D2_Pin|uSD_D1_Pin
+                          |uSD_D0_Pin);
+
+    HAL_GPIO_DeInit(uSD_CMD_GPIO_Port, uSD_CMD_Pin);
+
+  /* USER CODE BEGIN SDIO_MspDeInit 1 */
+
+  /* USER CODE END SDIO_MspDeInit 1 */
+  }
+}
+
+/* USER CODE BEGIN 1 */
+
+/* USER CODE END 1 */
diff --git a/Core/Src/stm32f4xx_hal_msp.c b/Core/Src/stm32f4xx_hal_msp.c
new file mode 100644
index 0000000..d71b4af
--- /dev/null
+++ b/Core/Src/stm32f4xx_hal_msp.c
@@ -0,0 +1,83 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file         stm32f4xx_hal_msp.c
+  * @brief        This file provides code for the MSP Initialization
+  *               and de-Initialization codes.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2022 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN Define */
+
+/* USER CODE END Define */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN Macro */
+
+/* USER CODE END Macro */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* External functions --------------------------------------------------------*/
+/* USER CODE BEGIN ExternalFunctions */
+
+/* USER CODE END ExternalFunctions */
+
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+/**
+  * Initializes the Global MSP.
+  */
+void HAL_MspInit(void)
+{
+  /* USER CODE BEGIN MspInit 0 */
+
+  /* USER CODE END MspInit 0 */
+
+  __HAL_RCC_SYSCFG_CLK_ENABLE();
+  __HAL_RCC_PWR_CLK_ENABLE();
+
+  /* System interrupt init*/
+  /* PendSV_IRQn interrupt configuration */
+  HAL_NVIC_SetPriority(PendSV_IRQn, 15, 0);
+
+  /* USER CODE BEGIN MspInit 1 */
+
+  /* USER CODE END MspInit 1 */
+}
+
+/* USER CODE BEGIN 1 */
+
+/* USER CODE END 1 */
diff --git a/Core/Src/stm32f4xx_hal_timebase_tim.c b/Core/Src/stm32f4xx_hal_timebase_tim.c
new file mode 100644
index 0000000..4e8ddec
--- /dev/null
+++ b/Core/Src/stm32f4xx_hal_timebase_tim.c
@@ -0,0 +1,136 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hal_timebase_TIM.c
+  * @brief   HAL time base based on the hardware TIM.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2022 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal.h"
+#include "stm32f4xx_hal_tim.h"
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+TIM_HandleTypeDef        htim6;
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/**
+  * @brief  This function configures the TIM6 as a time base source.
+  *         The time source is configured  to have 1ms time base with a dedicated
+  *         Tick interrupt priority.
+  * @note   This function is called  automatically at the beginning of program after
+  *         reset by HAL_Init() or at any time when clock is configured, by HAL_RCC_ClockConfig().
+  * @param  TickPriority: Tick interrupt priority.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
+{
+  RCC_ClkInitTypeDef    clkconfig;
+  uint32_t              uwTimclock, uwAPB1Prescaler = 0U;
+
+  uint32_t              uwPrescalerValue = 0U;
+  uint32_t              pFLatency;
+  HAL_StatusTypeDef     status;
+
+  /* Enable TIM6 clock */
+  __HAL_RCC_TIM6_CLK_ENABLE();
+
+  /* Get clock configuration */
+  HAL_RCC_GetClockConfig(&clkconfig, &pFLatency);
+
+  /* Get APB1 prescaler */
+  uwAPB1Prescaler = clkconfig.APB1CLKDivider;
+  /* Compute TIM6 clock */
+  if (uwAPB1Prescaler == RCC_HCLK_DIV1)
+  {
+    uwTimclock = HAL_RCC_GetPCLK1Freq();
+  }
+  else
+  {
+    uwTimclock = 2UL * HAL_RCC_GetPCLK1Freq();
+  }
+
+  /* Compute the prescaler value to have TIM6 counter clock equal to 1MHz */
+  uwPrescalerValue = (uint32_t) ((uwTimclock / 1000000U) - 1U);
+
+  /* Initialize TIM6 */
+  htim6.Instance = TIM6;
+
+  /* Initialize TIMx peripheral as follow:
+  + Period = [(TIM6CLK/1000) - 1]. to have a (1/1000) s time base.
+  + Prescaler = (uwTimclock/1000000 - 1) to have a 1MHz counter clock.
+  + ClockDivision = 0
+  + Counter direction = Up
+  */
+  htim6.Init.Period = (1000000U / 1000U) - 1U;
+  htim6.Init.Prescaler = uwPrescalerValue;
+  htim6.Init.ClockDivision = 0;
+  htim6.Init.CounterMode = TIM_COUNTERMODE_UP;
+  htim6.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
+
+  status = HAL_TIM_Base_Init(&htim6);
+  if (status == HAL_OK)
+  {
+    /* Start the TIM time Base generation in interrupt mode */
+    status = HAL_TIM_Base_Start_IT(&htim6);
+    if (status == HAL_OK)
+    {
+    /* Enable the TIM6 global Interrupt */
+        HAL_NVIC_EnableIRQ(TIM6_DAC_IRQn);
+      /* Configure the SysTick IRQ priority */
+      if (TickPriority < (1UL << __NVIC_PRIO_BITS))
+      {
+        /* Configure the TIM IRQ priority */
+        HAL_NVIC_SetPriority(TIM6_DAC_IRQn, TickPriority, 0U);
+        uwTickPrio = TickPriority;
+      }
+      else
+      {
+        status = HAL_ERROR;
+      }
+    }
+  }
+
+ /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  Suspend Tick increment.
+  * @note   Disable the tick increment by disabling TIM6 update interrupt.
+  * @param  None
+  * @retval None
+  */
+void HAL_SuspendTick(void)
+{
+  /* Disable TIM6 update Interrupt */
+  __HAL_TIM_DISABLE_IT(&htim6, TIM_IT_UPDATE);
+}
+
+/**
+  * @brief  Resume Tick increment.
+  * @note   Enable the tick increment by Enabling TIM6 update interrupt.
+  * @param  None
+  * @retval None
+  */
+void HAL_ResumeTick(void)
+{
+  /* Enable TIM6 Update interrupt */
+  __HAL_TIM_ENABLE_IT(&htim6, TIM_IT_UPDATE);
+}
+
diff --git a/Core/Src/stm32f4xx_it.c b/Core/Src/stm32f4xx_it.c
new file mode 100644
index 0000000..3031af8
--- /dev/null
+++ b/Core/Src/stm32f4xx_it.c
@@ -0,0 +1,242 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_it.c
+  * @brief   Interrupt Service Routines.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2022 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+#include "stm32f4xx_it.h"
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+extern LTDC_HandleTypeDef hltdc_eval;
+extern DMA2D_HandleTypeDef hdma2d_eval;
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/* External variables --------------------------------------------------------*/
+extern HCD_HandleTypeDef hhcd_USB_OTG_FS;
+extern DMA2D_HandleTypeDef hdma2d;
+extern DSI_HandleTypeDef hdsi;
+extern LTDC_HandleTypeDef hltdc;
+extern TIM_HandleTypeDef htim6;
+
+/* USER CODE BEGIN EV */
+
+/* USER CODE END EV */
+
+/******************************************************************************/
+/*           Cortex-M4 Processor Interruption and Exception Handlers          */
+/******************************************************************************/
+/**
+  * @brief This function handles Non maskable interrupt.
+  */
+void NMI_Handler(void)
+{
+  /* USER CODE BEGIN NonMaskableInt_IRQn 0 */
+
+  /* USER CODE END NonMaskableInt_IRQn 0 */
+  /* USER CODE BEGIN NonMaskableInt_IRQn 1 */
+  while (1)
+  {
+  }
+  /* USER CODE END NonMaskableInt_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Hard fault interrupt.
+  */
+void HardFault_Handler(void)
+{
+  /* USER CODE BEGIN HardFault_IRQn 0 */
+
+  /* USER CODE END HardFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_HardFault_IRQn 0 */
+    /* USER CODE END W1_HardFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Memory management fault.
+  */
+void MemManage_Handler(void)
+{
+  /* USER CODE BEGIN MemoryManagement_IRQn 0 */
+
+  /* USER CODE END MemoryManagement_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */
+    /* USER CODE END W1_MemoryManagement_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Pre-fetch fault, memory access fault.
+  */
+void BusFault_Handler(void)
+{
+  /* USER CODE BEGIN BusFault_IRQn 0 */
+
+  /* USER CODE END BusFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_BusFault_IRQn 0 */
+    /* USER CODE END W1_BusFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Undefined instruction or illegal state.
+  */
+void UsageFault_Handler(void)
+{
+  /* USER CODE BEGIN UsageFault_IRQn 0 */
+
+  /* USER CODE END UsageFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_UsageFault_IRQn 0 */
+    /* USER CODE END W1_UsageFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Debug monitor.
+  */
+void DebugMon_Handler(void)
+{
+  /* USER CODE BEGIN DebugMonitor_IRQn 0 */
+
+  /* USER CODE END DebugMonitor_IRQn 0 */
+  /* USER CODE BEGIN DebugMonitor_IRQn 1 */
+
+  /* USER CODE END DebugMonitor_IRQn 1 */
+}
+
+/******************************************************************************/
+/* STM32F4xx Peripheral Interrupt Handlers                                    */
+/* Add here the Interrupt Handlers for the used peripherals.                  */
+/* For the available peripheral interrupt handler names,                      */
+/* please refer to the startup file (startup_stm32f4xx.s).                    */
+/******************************************************************************/
+
+/**
+  * @brief This function handles TIM6 global interrupt, DAC1 and DAC2 underrun error interrupts.
+  */
+void TIM6_DAC_IRQHandler(void)
+{
+  /* USER CODE BEGIN TIM6_DAC_IRQn 0 */
+
+  /* USER CODE END TIM6_DAC_IRQn 0 */
+  /* USER CODE BEGIN TIM6_DAC_IRQn 1 */
+
+  /* USER CODE END TIM6_DAC_IRQn 1 */
+}
+
+/**
+  * @brief This function handles USB On The Go FS global interrupt.
+  */
+void OTG_FS_IRQHandler(void)
+{
+  /* USER CODE BEGIN OTG_FS_IRQn 0 */
+
+  /* USER CODE END OTG_FS_IRQn 0 */
+  HAL_HCD_IRQHandler(&hhcd_USB_OTG_FS);
+  /* USER CODE BEGIN OTG_FS_IRQn 1 */
+
+  /* USER CODE END OTG_FS_IRQn 1 */
+}
+
+/**
+  * @brief This function handles LTDC global interrupt.
+  */
+void LTDC_IRQHandler(void)
+{
+  /* USER CODE BEGIN LTDC_IRQn 0 */
+#if 1
+  HAL_LTDC_IRQHandler(&hltdc_eval);
+#else
+  /* USER CODE END LTDC_IRQn 0 */
+  HAL_LTDC_IRQHandler(&hltdc);
+  /* USER CODE BEGIN LTDC_IRQn 1 */
+#endif
+  /* USER CODE END LTDC_IRQn 1 */
+}
+
+/**
+  * @brief This function handles DMA2D global interrupt.
+  */
+void DMA2D_IRQHandler(void)
+{
+  /* USER CODE BEGIN DMA2D_IRQn 0 */
+#if 1
+  HAL_DMA2D_IRQHandler(&hdma2d_eval);
+#else
+  /* USER CODE END DMA2D_IRQn 0 */
+  HAL_DMA2D_IRQHandler(&hdma2d);
+  /* USER CODE BEGIN DMA2D_IRQn 1 */
+#endif
+  /* USER CODE END DMA2D_IRQn 1 */
+}
+
+/**
+  * @brief This function handles DSI global interrupt.
+  */
+void DSI_IRQHandler(void)
+{
+  /* USER CODE BEGIN DSI_IRQn 0 */
+
+  /* USER CODE END DSI_IRQn 0 */
+  HAL_DSI_IRQHandler(&hdsi);
+  /* USER CODE BEGIN DSI_IRQn 1 */
+
+  /* USER CODE END DSI_IRQn 1 */
+}
+
+/* USER CODE BEGIN 1 */
+
+/* USER CODE END 1 */
diff --git a/Core/Src/syscalls.c b/Core/Src/syscalls.c
new file mode 100644
index 0000000..fadb992
--- /dev/null
+++ b/Core/Src/syscalls.c
@@ -0,0 +1,155 @@
+/**
+ ******************************************************************************
+ * @file      syscalls.c
+ * @author    Auto-generated by STM32CubeIDE
+ * @brief     STM32CubeIDE Minimal System calls file
+ *
+ *            For more information about which c-functions
+ *            need which of these lowlevel functions
+ *            please consult the Newlib libc-manual
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2022 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Includes */
+#include <sys/stat.h>
+#include <stdlib.h>
+#include <errno.h>
+#include <stdio.h>
+#include <signal.h>
+#include <time.h>
+#include <sys/time.h>
+#include <sys/times.h>
+
+
+/* Variables */
+extern int __io_putchar(int ch) __attribute__((weak));
+extern int __io_getchar(void) __attribute__((weak));
+
+
+char *__env[1] = { 0 };
+char **environ = __env;
+
+
+/* Functions */
+void initialise_monitor_handles()
+{
+}
+
+int _getpid(void)
+{
+	return 1;
+}
+
+int _kill(int pid, int sig)
+{
+	errno = EINVAL;
+	return -1;
+}
+
+void _exit (int status)
+{
+	_kill(status, -1);
+	while (1) {}		/* Make sure we hang here */
+}
+
+__attribute__((weak)) int _read(int file, char *ptr, int len)
+{
+	int DataIdx;
+
+	for (DataIdx = 0; DataIdx < len; DataIdx++)
+	{
+		*ptr++ = __io_getchar();
+	}
+
+return len;
+}
+
+__attribute__((weak)) int _write(int file, char *ptr, int len)
+{
+	int DataIdx;
+
+	for (DataIdx = 0; DataIdx < len; DataIdx++)
+	{
+		__io_putchar(*ptr++);
+	}
+	return len;
+}
+
+int _close(int file)
+{
+	return -1;
+}
+
+
+int _fstat(int file, struct stat *st)
+{
+	st->st_mode = S_IFCHR;
+	return 0;
+}
+
+int _isatty(int file)
+{
+	return 1;
+}
+
+int _lseek(int file, int ptr, int dir)
+{
+	return 0;
+}
+
+int _open(char *path, int flags, ...)
+{
+	/* Pretend like we always fail */
+	return -1;
+}
+
+int _wait(int *status)
+{
+	errno = ECHILD;
+	return -1;
+}
+
+int _unlink(char *name)
+{
+	errno = ENOENT;
+	return -1;
+}
+
+int _times(struct tms *buf)
+{
+	return -1;
+}
+
+int _stat(char *file, struct stat *st)
+{
+	st->st_mode = S_IFCHR;
+	return 0;
+}
+
+int _link(char *old, char *new)
+{
+	errno = EMLINK;
+	return -1;
+}
+
+int _fork(void)
+{
+	errno = EAGAIN;
+	return -1;
+}
+
+int _execve(char *name, char **argv, char **env)
+{
+	errno = ENOMEM;
+	return -1;
+}
diff --git a/Core/Src/sysmem.c b/Core/Src/sysmem.c
new file mode 100644
index 0000000..54081ac
--- /dev/null
+++ b/Core/Src/sysmem.c
@@ -0,0 +1,79 @@
+/**
+ ******************************************************************************
+ * @file      sysmem.c
+ * @author    Generated by STM32CubeIDE
+ * @brief     STM32CubeIDE System Memory calls file
+ *
+ *            For more information about which C functions
+ *            need which of these lowlevel functions
+ *            please consult the newlib libc manual
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2022 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Includes */
+#include <errno.h>
+#include <stdint.h>
+
+/**
+ * Pointer to the current high watermark of the heap usage
+ */
+static uint8_t *__sbrk_heap_end = NULL;
+
+/**
+ * @brief _sbrk() allocates memory to the newlib heap and is used by malloc
+ *        and others from the C library
+ *
+ * @verbatim
+ * ############################################################################
+ * #  .data  #  .bss  #       newlib heap       #          MSP stack          #
+ * #         #        #                         # Reserved by _Min_Stack_Size #
+ * ############################################################################
+ * ^-- RAM start      ^-- _end                             _estack, RAM end --^
+ * @endverbatim
+ *
+ * This implementation starts allocating at the '_end' linker symbol
+ * The '_Min_Stack_Size' linker symbol reserves a memory for the MSP stack
+ * The implementation considers '_estack' linker symbol to be RAM end
+ * NOTE: If the MSP stack, at any point during execution, grows larger than the
+ * reserved size, please increase the '_Min_Stack_Size'.
+ *
+ * @param incr Memory size
+ * @return Pointer to allocated memory
+ */
+void *_sbrk(ptrdiff_t incr)
+{
+  extern uint8_t _end; /* Symbol defined in the linker script */
+  extern uint8_t _estack; /* Symbol defined in the linker script */
+  extern uint32_t _Min_Stack_Size; /* Symbol defined in the linker script */
+  const uint32_t stack_limit = (uint32_t)&_estack - (uint32_t)&_Min_Stack_Size;
+  const uint8_t *max_heap = (uint8_t *)stack_limit;
+  uint8_t *prev_heap_end;
+
+  /* Initialize heap end at first call */
+  if (NULL == __sbrk_heap_end)
+  {
+    __sbrk_heap_end = &_end;
+  }
+
+  /* Protect heap from growing into the reserved MSP stack */
+  if (__sbrk_heap_end + incr > max_heap)
+  {
+    errno = ENOMEM;
+    return (void *)-1;
+  }
+
+  prev_heap_end = __sbrk_heap_end;
+  __sbrk_heap_end += incr;
+
+  return (void *)prev_heap_end;
+}
diff --git a/Core/Src/system_stm32f4xx.c b/Core/Src/system_stm32f4xx.c
new file mode 100644
index 0000000..bd17010
--- /dev/null
+++ b/Core/Src/system_stm32f4xx.c
@@ -0,0 +1,747 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32f4xx.c
+  * @author  MCD Application Team
+  * @brief   CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
+  *
+  *   This file provides two functions and one global variable to be called from 
+  *   user application:
+  *      - SystemInit(): This function is called at startup just after reset and 
+  *                      before branch to main program. This call is made inside
+  *                      the "startup_stm32f4xx.s" file.
+  *
+  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+  *                                  by the user application to setup the SysTick 
+  *                                  timer or configure other parameters.
+  *                                     
+  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+  *                                 be called whenever the core clock is changed
+  *                                 during program execution.
+  *
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32f4xx_system
+  * @{
+  */  
+  
+/** @addtogroup STM32F4xx_System_Private_Includes
+  * @{
+  */
+
+
+#include "stm32f4xx.h"
+
+#if !defined  (HSE_VALUE) 
+  #define HSE_VALUE    ((uint32_t)25000000) /*!< Default value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (HSI_VALUE)
+  #define HSI_VALUE    ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F4xx_System_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F4xx_System_Private_Defines
+  * @{
+  */
+
+/************************* Miscellaneous Configuration ************************/
+/*!< Uncomment the following line if you need to use external SRAM or SDRAM as data memory  */
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)\
+ || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
+ || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx)
+/* #define DATA_IN_ExtSRAM */
+#endif /* STM32F40xxx || STM32F41xxx || STM32F42xxx || STM32F43xxx || STM32F469xx || STM32F479xx ||\
+          STM32F412Zx || STM32F412Vx */
+ 
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
+ || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
+/* #define DATA_IN_ExtSDRAM */
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx ||\
+          STM32F479xx */
+
+/* Note: Following vector table addresses must be defined in line with linker
+         configuration. */
+/*!< Uncomment the following line if you need to relocate the vector table
+     anywhere in Flash or Sram, else the vector table is kept at the automatic
+     remap of boot address selected */
+/* #define USER_VECT_TAB_ADDRESS */
+
+#if defined(USER_VECT_TAB_ADDRESS)
+/*!< Uncomment the following line if you need to relocate your vector Table
+     in Sram else user remap will be done in Flash. */
+/* #define VECT_TAB_SRAM */
+#if defined(VECT_TAB_SRAM)
+#define VECT_TAB_BASE_ADDRESS   SRAM_BASE       /*!< Vector Table base address field.
+                                                     This value must be a multiple of 0x200. */
+#define VECT_TAB_OFFSET         0x00000000U     /*!< Vector Table base offset field.
+                                                     This value must be a multiple of 0x200. */
+#else
+#define VECT_TAB_BASE_ADDRESS   FLASH_BASE      /*!< Vector Table base address field.
+                                                     This value must be a multiple of 0x200. */
+#define VECT_TAB_OFFSET         0x00000000U     /*!< Vector Table base offset field.
+                                                     This value must be a multiple of 0x200. */
+#endif /* VECT_TAB_SRAM */
+#endif /* USER_VECT_TAB_ADDRESS */
+/******************************************************************************/
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F4xx_System_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F4xx_System_Private_Variables
+  * @{
+  */
+  /* This variable is updated in three ways:
+      1) by calling CMSIS function SystemCoreClockUpdate()
+      2) by calling HAL API function HAL_RCC_GetHCLKFreq()
+      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency 
+         Note: If you use this function to configure the system clock; then there
+               is no need to call the 2 first functions listed above, since SystemCoreClock
+               variable is updated automatically.
+  */
+uint32_t SystemCoreClock = 16000000;
+const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
+const uint8_t APBPrescTable[8]  = {0, 0, 0, 0, 1, 2, 3, 4};
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F4xx_System_Private_FunctionPrototypes
+  * @{
+  */
+
+#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
+  static void SystemInit_ExtMemCtl(void); 
+#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F4xx_System_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Setup the microcontroller system
+  *         Initialize the FPU setting, vector table location and External memory 
+  *         configuration.
+  * @param  None
+  * @retval None
+  */
+void SystemInit(void)
+{
+  /* FPU settings ------------------------------------------------------------*/
+  #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+    SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2));  /* set CP10 and CP11 Full Access */
+  #endif
+
+#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
+  SystemInit_ExtMemCtl(); 
+#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
+
+  /* Configure the Vector Table location -------------------------------------*/
+#if defined(USER_VECT_TAB_ADDRESS)
+  SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
+#endif /* USER_VECT_TAB_ADDRESS */
+}
+
+/**
+   * @brief  Update SystemCoreClock variable according to Clock Register Values.
+  *         The SystemCoreClock variable contains the core clock (HCLK), it can
+  *         be used by the user application to setup the SysTick timer or configure
+  *         other parameters.
+  *           
+  * @note   Each time the core clock (HCLK) changes, this function must be called
+  *         to update SystemCoreClock variable value. Otherwise, any configuration
+  *         based on this variable will be incorrect.         
+  *     
+  * @note   - The system frequency computed by this function is not the real 
+  *           frequency in the chip. It is calculated based on the predefined 
+  *           constant and the selected clock source:
+  *             
+  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
+  *                                              
+  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
+  *                          
+  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) 
+  *             or HSI_VALUE(*) multiplied/divided by the PLL factors.
+  *         
+  *         (*) HSI_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value
+  *             16 MHz) but the real value may vary depending on the variations
+  *             in voltage and temperature.   
+  *    
+  *         (**) HSE_VALUE is a constant defined in stm32f4xx_hal_conf.h file (its value
+  *              depends on the application requirements), user has to ensure that HSE_VALUE
+  *              is same as the real frequency of the crystal used. Otherwise, this function
+  *              may have wrong result.
+  *                
+  *         - The result of this function could be not correct when using fractional
+  *           value for HSE crystal.
+  *     
+  * @param  None
+  * @retval None
+  */
+void SystemCoreClockUpdate(void)
+{
+  uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;
+  
+  /* Get SYSCLK source -------------------------------------------------------*/
+  tmp = RCC->CFGR & RCC_CFGR_SWS;
+
+  switch (tmp)
+  {
+    case 0x00:  /* HSI used as system clock source */
+      SystemCoreClock = HSI_VALUE;
+      break;
+    case 0x04:  /* HSE used as system clock source */
+      SystemCoreClock = HSE_VALUE;
+      break;
+    case 0x08:  /* PLL used as system clock source */
+
+      /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N
+         SYSCLK = PLL_VCO / PLL_P
+         */    
+      pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;
+      pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
+      
+      if (pllsource != 0)
+      {
+        /* HSE used as PLL clock source */
+        pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
+      }
+      else
+      {
+        /* HSI used as PLL clock source */
+        pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
+      }
+
+      pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2;
+      SystemCoreClock = pllvco/pllp;
+      break;
+    default:
+      SystemCoreClock = HSI_VALUE;
+      break;
+  }
+  /* Compute HCLK frequency --------------------------------------------------*/
+  /* Get HCLK prescaler */
+  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
+  /* HCLK frequency */
+  SystemCoreClock >>= tmp;
+}
+
+#if defined (DATA_IN_ExtSRAM) && defined (DATA_IN_ExtSDRAM)
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
+ || defined(STM32F469xx) || defined(STM32F479xx)
+/**
+  * @brief  Setup the external memory controller.
+  *         Called in startup_stm32f4xx.s before jump to main.
+  *         This function configures the external memories (SRAM/SDRAM)
+  *         This SRAM/SDRAM will be used as program data memory (including heap and stack).
+  * @param  None
+  * @retval None
+  */
+void SystemInit_ExtMemCtl(void)
+{
+  __IO uint32_t tmp = 0x00;
+
+  register uint32_t tmpreg = 0, timeout = 0xFFFF;
+  register __IO uint32_t index;
+
+  /* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface clock */
+  RCC->AHB1ENR |= 0x000001F8;
+
+  /* Delay after an RCC peripheral clock enabling */
+  tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);
+  
+  /* Connect PDx pins to FMC Alternate function */
+  GPIOD->AFR[0]  = 0x00CCC0CC;
+  GPIOD->AFR[1]  = 0xCCCCCCCC;
+  /* Configure PDx pins in Alternate function mode */  
+  GPIOD->MODER   = 0xAAAA0A8A;
+  /* Configure PDx pins speed to 100 MHz */  
+  GPIOD->OSPEEDR = 0xFFFF0FCF;
+  /* Configure PDx pins Output type to push-pull */  
+  GPIOD->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PDx pins */ 
+  GPIOD->PUPDR   = 0x00000000;
+
+  /* Connect PEx pins to FMC Alternate function */
+  GPIOE->AFR[0]  = 0xC00CC0CC;
+  GPIOE->AFR[1]  = 0xCCCCCCCC;
+  /* Configure PEx pins in Alternate function mode */ 
+  GPIOE->MODER   = 0xAAAA828A;
+  /* Configure PEx pins speed to 100 MHz */ 
+  GPIOE->OSPEEDR = 0xFFFFC3CF;
+  /* Configure PEx pins Output type to push-pull */  
+  GPIOE->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PEx pins */ 
+  GPIOE->PUPDR   = 0x00000000;
+  
+  /* Connect PFx pins to FMC Alternate function */
+  GPIOF->AFR[0]  = 0xCCCCCCCC;
+  GPIOF->AFR[1]  = 0xCCCCCCCC;
+  /* Configure PFx pins in Alternate function mode */   
+  GPIOF->MODER   = 0xAA800AAA;
+  /* Configure PFx pins speed to 50 MHz */ 
+  GPIOF->OSPEEDR = 0xAA800AAA;
+  /* Configure PFx pins Output type to push-pull */  
+  GPIOF->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PFx pins */ 
+  GPIOF->PUPDR   = 0x00000000;
+
+  /* Connect PGx pins to FMC Alternate function */
+  GPIOG->AFR[0]  = 0xCCCCCCCC;
+  GPIOG->AFR[1]  = 0xCCCCCCCC;
+  /* Configure PGx pins in Alternate function mode */ 
+  GPIOG->MODER   = 0xAAAAAAAA;
+  /* Configure PGx pins speed to 50 MHz */ 
+  GPIOG->OSPEEDR = 0xAAAAAAAA;
+  /* Configure PGx pins Output type to push-pull */  
+  GPIOG->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PGx pins */ 
+  GPIOG->PUPDR   = 0x00000000;
+  
+  /* Connect PHx pins to FMC Alternate function */
+  GPIOH->AFR[0]  = 0x00C0CC00;
+  GPIOH->AFR[1]  = 0xCCCCCCCC;
+  /* Configure PHx pins in Alternate function mode */ 
+  GPIOH->MODER   = 0xAAAA08A0;
+  /* Configure PHx pins speed to 50 MHz */ 
+  GPIOH->OSPEEDR = 0xAAAA08A0;
+  /* Configure PHx pins Output type to push-pull */  
+  GPIOH->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PHx pins */ 
+  GPIOH->PUPDR   = 0x00000000;
+  
+  /* Connect PIx pins to FMC Alternate function */
+  GPIOI->AFR[0]  = 0xCCCCCCCC;
+  GPIOI->AFR[1]  = 0x00000CC0;
+  /* Configure PIx pins in Alternate function mode */ 
+  GPIOI->MODER   = 0x0028AAAA;
+  /* Configure PIx pins speed to 50 MHz */ 
+  GPIOI->OSPEEDR = 0x0028AAAA;
+  /* Configure PIx pins Output type to push-pull */  
+  GPIOI->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PIx pins */ 
+  GPIOI->PUPDR   = 0x00000000;
+  
+/*-- FMC Configuration -------------------------------------------------------*/
+  /* Enable the FMC interface clock */
+  RCC->AHB3ENR |= 0x00000001;
+  /* Delay after an RCC peripheral clock enabling */
+  tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);
+
+  FMC_Bank5_6->SDCR[0] = 0x000019E4;
+  FMC_Bank5_6->SDTR[0] = 0x01115351;      
+  
+  /* SDRAM initialization sequence */
+  /* Clock enable command */
+  FMC_Bank5_6->SDCMR = 0x00000011; 
+  tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 
+  while((tmpreg != 0) && (timeout-- > 0))
+  {
+    tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 
+  }
+
+  /* Delay */
+  for (index = 0; index<1000; index++);
+  
+  /* PALL command */
+  FMC_Bank5_6->SDCMR = 0x00000012;           
+  tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
+  timeout = 0xFFFF;
+  while((tmpreg != 0) && (timeout-- > 0))
+  {
+    tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 
+  }
+  
+  /* Auto refresh command */
+  FMC_Bank5_6->SDCMR = 0x00000073;
+  tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
+  timeout = 0xFFFF;
+  while((tmpreg != 0) && (timeout-- > 0))
+  {
+    tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 
+  }
+ 
+  /* MRD register program */
+  FMC_Bank5_6->SDCMR = 0x00046014;
+  tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
+  timeout = 0xFFFF;
+  while((tmpreg != 0) && (timeout-- > 0))
+  {
+    tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 
+  } 
+  
+  /* Set refresh count */
+  tmpreg = FMC_Bank5_6->SDRTR;
+  FMC_Bank5_6->SDRTR = (tmpreg | (0x0000027C<<1));
+  
+  /* Disable write protection */
+  tmpreg = FMC_Bank5_6->SDCR[0]; 
+  FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF);
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
+  /* Configure and enable Bank1_SRAM2 */
+  FMC_Bank1->BTCR[2]  = 0x00001011;
+  FMC_Bank1->BTCR[3]  = 0x00000201;
+  FMC_Bank1E->BWTR[2] = 0x0fffffff;
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ 
+#if defined(STM32F469xx) || defined(STM32F479xx)
+  /* Configure and enable Bank1_SRAM2 */
+  FMC_Bank1->BTCR[2]  = 0x00001091;
+  FMC_Bank1->BTCR[3]  = 0x00110212;
+  FMC_Bank1E->BWTR[2] = 0x0fffffff;
+#endif /* STM32F469xx || STM32F479xx */
+
+  (void)(tmp); 
+}
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
+#elif defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
+/**
+  * @brief  Setup the external memory controller.
+  *         Called in startup_stm32f4xx.s before jump to main.
+  *         This function configures the external memories (SRAM/SDRAM)
+  *         This SRAM/SDRAM will be used as program data memory (including heap and stack).
+  * @param  None
+  * @retval None
+  */
+void SystemInit_ExtMemCtl(void)
+{
+  __IO uint32_t tmp = 0x00;
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
+ || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
+#if defined (DATA_IN_ExtSDRAM)
+  register uint32_t tmpreg = 0, timeout = 0xFFFF;
+  register __IO uint32_t index;
+
+#if defined(STM32F446xx)
+  /* Enable GPIOA, GPIOC, GPIOD, GPIOE, GPIOF, GPIOG interface
+      clock */
+  RCC->AHB1ENR |= 0x0000007D;
+#else
+  /* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface 
+      clock */
+  RCC->AHB1ENR |= 0x000001F8;
+#endif /* STM32F446xx */  
+  /* Delay after an RCC peripheral clock enabling */
+  tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);
+  
+#if defined(STM32F446xx)
+  /* Connect PAx pins to FMC Alternate function */
+  GPIOA->AFR[0]  |= 0xC0000000;
+  GPIOA->AFR[1]  |= 0x00000000;
+  /* Configure PDx pins in Alternate function mode */
+  GPIOA->MODER   |= 0x00008000;
+  /* Configure PDx pins speed to 50 MHz */
+  GPIOA->OSPEEDR |= 0x00008000;
+  /* Configure PDx pins Output type to push-pull */
+  GPIOA->OTYPER  |= 0x00000000;
+  /* No pull-up, pull-down for PDx pins */
+  GPIOA->PUPDR   |= 0x00000000;
+
+  /* Connect PCx pins to FMC Alternate function */
+  GPIOC->AFR[0]  |= 0x00CC0000;
+  GPIOC->AFR[1]  |= 0x00000000;
+  /* Configure PDx pins in Alternate function mode */
+  GPIOC->MODER   |= 0x00000A00;
+  /* Configure PDx pins speed to 50 MHz */
+  GPIOC->OSPEEDR |= 0x00000A00;
+  /* Configure PDx pins Output type to push-pull */
+  GPIOC->OTYPER  |= 0x00000000;
+  /* No pull-up, pull-down for PDx pins */
+  GPIOC->PUPDR   |= 0x00000000;
+#endif /* STM32F446xx */
+
+  /* Connect PDx pins to FMC Alternate function */
+  GPIOD->AFR[0]  = 0x000000CC;
+  GPIOD->AFR[1]  = 0xCC000CCC;
+  /* Configure PDx pins in Alternate function mode */  
+  GPIOD->MODER   = 0xA02A000A;
+  /* Configure PDx pins speed to 50 MHz */  
+  GPIOD->OSPEEDR = 0xA02A000A;
+  /* Configure PDx pins Output type to push-pull */  
+  GPIOD->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PDx pins */ 
+  GPIOD->PUPDR   = 0x00000000;
+
+  /* Connect PEx pins to FMC Alternate function */
+  GPIOE->AFR[0]  = 0xC00000CC;
+  GPIOE->AFR[1]  = 0xCCCCCCCC;
+  /* Configure PEx pins in Alternate function mode */ 
+  GPIOE->MODER   = 0xAAAA800A;
+  /* Configure PEx pins speed to 50 MHz */ 
+  GPIOE->OSPEEDR = 0xAAAA800A;
+  /* Configure PEx pins Output type to push-pull */  
+  GPIOE->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PEx pins */ 
+  GPIOE->PUPDR   = 0x00000000;
+
+  /* Connect PFx pins to FMC Alternate function */
+  GPIOF->AFR[0]  = 0xCCCCCCCC;
+  GPIOF->AFR[1]  = 0xCCCCCCCC;
+  /* Configure PFx pins in Alternate function mode */   
+  GPIOF->MODER   = 0xAA800AAA;
+  /* Configure PFx pins speed to 50 MHz */ 
+  GPIOF->OSPEEDR = 0xAA800AAA;
+  /* Configure PFx pins Output type to push-pull */  
+  GPIOF->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PFx pins */ 
+  GPIOF->PUPDR   = 0x00000000;
+
+  /* Connect PGx pins to FMC Alternate function */
+  GPIOG->AFR[0]  = 0xCCCCCCCC;
+  GPIOG->AFR[1]  = 0xCCCCCCCC;
+  /* Configure PGx pins in Alternate function mode */ 
+  GPIOG->MODER   = 0xAAAAAAAA;
+  /* Configure PGx pins speed to 50 MHz */ 
+  GPIOG->OSPEEDR = 0xAAAAAAAA;
+  /* Configure PGx pins Output type to push-pull */  
+  GPIOG->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PGx pins */ 
+  GPIOG->PUPDR   = 0x00000000;
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
+ || defined(STM32F469xx) || defined(STM32F479xx)  
+  /* Connect PHx pins to FMC Alternate function */
+  GPIOH->AFR[0]  = 0x00C0CC00;
+  GPIOH->AFR[1]  = 0xCCCCCCCC;
+  /* Configure PHx pins in Alternate function mode */ 
+  GPIOH->MODER   = 0xAAAA08A0;
+  /* Configure PHx pins speed to 50 MHz */ 
+  GPIOH->OSPEEDR = 0xAAAA08A0;
+  /* Configure PHx pins Output type to push-pull */  
+  GPIOH->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PHx pins */ 
+  GPIOH->PUPDR   = 0x00000000;
+  
+  /* Connect PIx pins to FMC Alternate function */
+  GPIOI->AFR[0]  = 0xCCCCCCCC;
+  GPIOI->AFR[1]  = 0x00000CC0;
+  /* Configure PIx pins in Alternate function mode */ 
+  GPIOI->MODER   = 0x0028AAAA;
+  /* Configure PIx pins speed to 50 MHz */ 
+  GPIOI->OSPEEDR = 0x0028AAAA;
+  /* Configure PIx pins Output type to push-pull */  
+  GPIOI->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PIx pins */ 
+  GPIOI->PUPDR   = 0x00000000;
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
+  
+/*-- FMC Configuration -------------------------------------------------------*/
+  /* Enable the FMC interface clock */
+  RCC->AHB3ENR |= 0x00000001;
+  /* Delay after an RCC peripheral clock enabling */
+  tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);
+
+  /* Configure and enable SDRAM bank1 */
+#if defined(STM32F446xx)
+  FMC_Bank5_6->SDCR[0] = 0x00001954;
+#else  
+  FMC_Bank5_6->SDCR[0] = 0x000019E4;
+#endif /* STM32F446xx */
+  FMC_Bank5_6->SDTR[0] = 0x01115351;      
+  
+  /* SDRAM initialization sequence */
+  /* Clock enable command */
+  FMC_Bank5_6->SDCMR = 0x00000011; 
+  tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 
+  while((tmpreg != 0) && (timeout-- > 0))
+  {
+    tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 
+  }
+
+  /* Delay */
+  for (index = 0; index<1000; index++);
+  
+  /* PALL command */
+  FMC_Bank5_6->SDCMR = 0x00000012;           
+  tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
+  timeout = 0xFFFF;
+  while((tmpreg != 0) && (timeout-- > 0))
+  {
+    tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 
+  }
+  
+  /* Auto refresh command */
+#if defined(STM32F446xx)
+  FMC_Bank5_6->SDCMR = 0x000000F3;
+#else  
+  FMC_Bank5_6->SDCMR = 0x00000073;
+#endif /* STM32F446xx */
+  tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
+  timeout = 0xFFFF;
+  while((tmpreg != 0) && (timeout-- > 0))
+  {
+    tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 
+  }
+ 
+  /* MRD register program */
+#if defined(STM32F446xx)
+  FMC_Bank5_6->SDCMR = 0x00044014;
+#else  
+  FMC_Bank5_6->SDCMR = 0x00046014;
+#endif /* STM32F446xx */
+  tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
+  timeout = 0xFFFF;
+  while((tmpreg != 0) && (timeout-- > 0))
+  {
+    tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 
+  } 
+  
+  /* Set refresh count */
+  tmpreg = FMC_Bank5_6->SDRTR;
+#if defined(STM32F446xx)
+  FMC_Bank5_6->SDRTR = (tmpreg | (0x0000050C<<1));
+#else    
+  FMC_Bank5_6->SDRTR = (tmpreg | (0x0000027C<<1));
+#endif /* STM32F446xx */
+  
+  /* Disable write protection */
+  tmpreg = FMC_Bank5_6->SDCR[0]; 
+  FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF);
+#endif /* DATA_IN_ExtSDRAM */
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
+
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)\
+ || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
+ || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx)
+
+#if defined(DATA_IN_ExtSRAM)
+/*-- GPIOs Configuration -----------------------------------------------------*/
+   /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */
+  RCC->AHB1ENR   |= 0x00000078;
+  /* Delay after an RCC peripheral clock enabling */
+  tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);
+  
+  /* Connect PDx pins to FMC Alternate function */
+  GPIOD->AFR[0]  = 0x00CCC0CC;
+  GPIOD->AFR[1]  = 0xCCCCCCCC;
+  /* Configure PDx pins in Alternate function mode */  
+  GPIOD->MODER   = 0xAAAA0A8A;
+  /* Configure PDx pins speed to 100 MHz */  
+  GPIOD->OSPEEDR = 0xFFFF0FCF;
+  /* Configure PDx pins Output type to push-pull */  
+  GPIOD->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PDx pins */ 
+  GPIOD->PUPDR   = 0x00000000;
+
+  /* Connect PEx pins to FMC Alternate function */
+  GPIOE->AFR[0]  = 0xC00CC0CC;
+  GPIOE->AFR[1]  = 0xCCCCCCCC;
+  /* Configure PEx pins in Alternate function mode */ 
+  GPIOE->MODER   = 0xAAAA828A;
+  /* Configure PEx pins speed to 100 MHz */ 
+  GPIOE->OSPEEDR = 0xFFFFC3CF;
+  /* Configure PEx pins Output type to push-pull */  
+  GPIOE->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PEx pins */ 
+  GPIOE->PUPDR   = 0x00000000;
+
+  /* Connect PFx pins to FMC Alternate function */
+  GPIOF->AFR[0]  = 0x00CCCCCC;
+  GPIOF->AFR[1]  = 0xCCCC0000;
+  /* Configure PFx pins in Alternate function mode */   
+  GPIOF->MODER   = 0xAA000AAA;
+  /* Configure PFx pins speed to 100 MHz */ 
+  GPIOF->OSPEEDR = 0xFF000FFF;
+  /* Configure PFx pins Output type to push-pull */  
+  GPIOF->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PFx pins */ 
+  GPIOF->PUPDR   = 0x00000000;
+
+  /* Connect PGx pins to FMC Alternate function */
+  GPIOG->AFR[0]  = 0x00CCCCCC;
+  GPIOG->AFR[1]  = 0x000000C0;
+  /* Configure PGx pins in Alternate function mode */ 
+  GPIOG->MODER   = 0x00085AAA;
+  /* Configure PGx pins speed to 100 MHz */ 
+  GPIOG->OSPEEDR = 0x000CAFFF;
+  /* Configure PGx pins Output type to push-pull */  
+  GPIOG->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PGx pins */ 
+  GPIOG->PUPDR   = 0x00000000;
+  
+/*-- FMC/FSMC Configuration --------------------------------------------------*/
+  /* Enable the FMC/FSMC interface clock */
+  RCC->AHB3ENR         |= 0x00000001;
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
+  /* Delay after an RCC peripheral clock enabling */
+  tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);
+  /* Configure and enable Bank1_SRAM2 */
+  FMC_Bank1->BTCR[2]  = 0x00001011;
+  FMC_Bank1->BTCR[3]  = 0x00000201;
+  FMC_Bank1E->BWTR[2] = 0x0fffffff;
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ 
+#if defined(STM32F469xx) || defined(STM32F479xx)
+  /* Delay after an RCC peripheral clock enabling */
+  tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);
+  /* Configure and enable Bank1_SRAM2 */
+  FMC_Bank1->BTCR[2]  = 0x00001091;
+  FMC_Bank1->BTCR[3]  = 0x00110212;
+  FMC_Bank1E->BWTR[2] = 0x0fffffff;
+#endif /* STM32F469xx || STM32F479xx */
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx)\
+   || defined(STM32F412Zx) || defined(STM32F412Vx)
+  /* Delay after an RCC peripheral clock enabling */
+  tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN);
+  /* Configure and enable Bank1_SRAM2 */
+  FSMC_Bank1->BTCR[2]  = 0x00001011;
+  FSMC_Bank1->BTCR[3]  = 0x00000201;
+  FSMC_Bank1E->BWTR[2] = 0x0FFFFFFF;
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F412Zx || STM32F412Vx */
+
+#endif /* DATA_IN_ExtSRAM */
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx ||\
+          STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx  */ 
+  (void)(tmp); 
+}
+#endif /* DATA_IN_ExtSRAM && DATA_IN_ExtSDRAM */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
diff --git a/Core/Src/tim.c b/Core/Src/tim.c
new file mode 100644
index 0000000..6216a8c
--- /dev/null
+++ b/Core/Src/tim.c
@@ -0,0 +1,105 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    tim.c
+  * @brief   This file provides code for the configuration
+  *          of the TIM instances.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2022 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+/* Includes ------------------------------------------------------------------*/
+#include "tim.h"
+
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+TIM_HandleTypeDef htim1;
+
+/* TIM1 init function */
+void MX_TIM1_Init(void)
+{
+
+  /* USER CODE BEGIN TIM1_Init 0 */
+
+  /* USER CODE END TIM1_Init 0 */
+
+  TIM_ClockConfigTypeDef sClockSourceConfig = {0};
+  TIM_MasterConfigTypeDef sMasterConfig = {0};
+
+  /* USER CODE BEGIN TIM1_Init 1 */
+
+  /* USER CODE END TIM1_Init 1 */
+  htim1.Instance = TIM1;
+  htim1.Init.Prescaler = 0;
+  htim1.Init.CounterMode = TIM_COUNTERMODE_UP;
+  htim1.Init.Period = 65535;
+  htim1.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
+  htim1.Init.RepetitionCounter = 0;
+  htim1.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
+  if (HAL_TIM_Base_Init(&htim1) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL;
+  if (HAL_TIM_ConfigClockSource(&htim1, &sClockSourceConfig) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
+  sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
+  if (HAL_TIMEx_MasterConfigSynchronization(&htim1, &sMasterConfig) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /* USER CODE BEGIN TIM1_Init 2 */
+
+  /* USER CODE END TIM1_Init 2 */
+
+}
+
+void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* tim_baseHandle)
+{
+
+  if(tim_baseHandle->Instance==TIM1)
+  {
+  /* USER CODE BEGIN TIM1_MspInit 0 */
+
+  /* USER CODE END TIM1_MspInit 0 */
+    /* TIM1 clock enable */
+    __HAL_RCC_TIM1_CLK_ENABLE();
+  /* USER CODE BEGIN TIM1_MspInit 1 */
+
+  /* USER CODE END TIM1_MspInit 1 */
+  }
+}
+
+void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef* tim_baseHandle)
+{
+
+  if(tim_baseHandle->Instance==TIM1)
+  {
+  /* USER CODE BEGIN TIM1_MspDeInit 0 */
+
+  /* USER CODE END TIM1_MspDeInit 0 */
+    /* Peripheral clock disable */
+    __HAL_RCC_TIM1_CLK_DISABLE();
+  /* USER CODE BEGIN TIM1_MspDeInit 1 */
+
+  /* USER CODE END TIM1_MspDeInit 1 */
+  }
+}
+
+/* USER CODE BEGIN 1 */
+
+/* USER CODE END 1 */
diff --git a/Core/Src/usart.c b/Core/Src/usart.c
new file mode 100644
index 0000000..be593bd
--- /dev/null
+++ b/Core/Src/usart.c
@@ -0,0 +1,186 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    usart.c
+  * @brief   This file provides code for the configuration
+  *          of the USART instances.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2022 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+/* Includes ------------------------------------------------------------------*/
+#include "usart.h"
+
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+UART_HandleTypeDef huart3;
+UART_HandleTypeDef huart6;
+
+/* USART3 init function */
+
+void MX_USART3_UART_Init(void)
+{
+
+  /* USER CODE BEGIN USART3_Init 0 */
+
+  /* USER CODE END USART3_Init 0 */
+
+  /* USER CODE BEGIN USART3_Init 1 */
+
+  /* USER CODE END USART3_Init 1 */
+  huart3.Instance = USART3;
+  huart3.Init.BaudRate = 115200;
+  huart3.Init.WordLength = UART_WORDLENGTH_8B;
+  huart3.Init.StopBits = UART_STOPBITS_1;
+  huart3.Init.Parity = UART_PARITY_NONE;
+  huart3.Init.Mode = UART_MODE_TX_RX;
+  huart3.Init.HwFlowCtl = UART_HWCONTROL_NONE;
+  huart3.Init.OverSampling = UART_OVERSAMPLING_16;
+  if (HAL_UART_Init(&huart3) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /* USER CODE BEGIN USART3_Init 2 */
+
+  /* USER CODE END USART3_Init 2 */
+
+}
+/* USART6 init function */
+
+void MX_USART6_UART_Init(void)
+{
+
+  /* USER CODE BEGIN USART6_Init 0 */
+
+  /* USER CODE END USART6_Init 0 */
+
+  /* USER CODE BEGIN USART6_Init 1 */
+
+  /* USER CODE END USART6_Init 1 */
+  huart6.Instance = USART6;
+  huart6.Init.BaudRate = 115200;
+  huart6.Init.WordLength = UART_WORDLENGTH_8B;
+  huart6.Init.StopBits = UART_STOPBITS_1;
+  huart6.Init.Parity = UART_PARITY_NONE;
+  huart6.Init.Mode = UART_MODE_TX_RX;
+  huart6.Init.HwFlowCtl = UART_HWCONTROL_NONE;
+  huart6.Init.OverSampling = UART_OVERSAMPLING_16;
+  if (HAL_UART_Init(&huart6) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /* USER CODE BEGIN USART6_Init 2 */
+
+  /* USER CODE END USART6_Init 2 */
+
+}
+
+void HAL_UART_MspInit(UART_HandleTypeDef* uartHandle)
+{
+
+  GPIO_InitTypeDef GPIO_InitStruct = {0};
+  if(uartHandle->Instance==USART3)
+  {
+  /* USER CODE BEGIN USART3_MspInit 0 */
+
+  /* USER CODE END USART3_MspInit 0 */
+    /* USART3 clock enable */
+    __HAL_RCC_USART3_CLK_ENABLE();
+
+    __HAL_RCC_GPIOB_CLK_ENABLE();
+    /**USART3 GPIO Configuration
+    PB10     ------> USART3_TX
+    PB11     ------> USART3_RX
+    */
+    GPIO_InitStruct.Pin = STLK_RX_Pin|STLK_TX_Pin;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+    GPIO_InitStruct.Pull = GPIO_PULLUP;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+    GPIO_InitStruct.Alternate = GPIO_AF7_USART3;
+    HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
+
+  /* USER CODE BEGIN USART3_MspInit 1 */
+
+  /* USER CODE END USART3_MspInit 1 */
+  }
+  else if(uartHandle->Instance==USART6)
+  {
+  /* USER CODE BEGIN USART6_MspInit 0 */
+
+  /* USER CODE END USART6_MspInit 0 */
+    /* USART6 clock enable */
+    __HAL_RCC_USART6_CLK_ENABLE();
+
+    __HAL_RCC_GPIOG_CLK_ENABLE();
+    /**USART6 GPIO Configuration
+    PG14     ------> USART6_TX
+    PG9     ------> USART6_RX
+    */
+    GPIO_InitStruct.Pin = ARDUINO_USART6_TX_Pin|USART6_RX_Pin;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+    GPIO_InitStruct.Alternate = GPIO_AF8_USART6;
+    HAL_GPIO_Init(GPIOG, &GPIO_InitStruct);
+
+  /* USER CODE BEGIN USART6_MspInit 1 */
+
+  /* USER CODE END USART6_MspInit 1 */
+  }
+}
+
+void HAL_UART_MspDeInit(UART_HandleTypeDef* uartHandle)
+{
+
+  if(uartHandle->Instance==USART3)
+  {
+  /* USER CODE BEGIN USART3_MspDeInit 0 */
+
+  /* USER CODE END USART3_MspDeInit 0 */
+    /* Peripheral clock disable */
+    __HAL_RCC_USART3_CLK_DISABLE();
+
+    /**USART3 GPIO Configuration
+    PB10     ------> USART3_TX
+    PB11     ------> USART3_RX
+    */
+    HAL_GPIO_DeInit(GPIOB, STLK_RX_Pin|STLK_TX_Pin);
+
+  /* USER CODE BEGIN USART3_MspDeInit 1 */
+
+  /* USER CODE END USART3_MspDeInit 1 */
+  }
+  else if(uartHandle->Instance==USART6)
+  {
+  /* USER CODE BEGIN USART6_MspDeInit 0 */
+
+  /* USER CODE END USART6_MspDeInit 0 */
+    /* Peripheral clock disable */
+    __HAL_RCC_USART6_CLK_DISABLE();
+
+    /**USART6 GPIO Configuration
+    PG14     ------> USART6_TX
+    PG9     ------> USART6_RX
+    */
+    HAL_GPIO_DeInit(GPIOG, ARDUINO_USART6_TX_Pin|USART6_RX_Pin);
+
+  /* USER CODE BEGIN USART6_MspDeInit 1 */
+
+  /* USER CODE END USART6_MspDeInit 1 */
+  }
+}
+
+/* USER CODE BEGIN 1 */
+
+/* USER CODE END 1 */
diff --git a/Core/Startup/startup_stm32f469nihx.s b/Core/Startup/startup_stm32f469nihx.s
new file mode 100644
index 0000000..0221a14
--- /dev/null
+++ b/Core/Startup/startup_stm32f469nihx.s
@@ -0,0 +1,549 @@
+/**
+  ******************************************************************************
+  * @file      startup_stm32f469xx.s
+  * @author    MCD Application Team
+  * @brief     STM32F469xx Devices vector table for GCC based toolchains. 
+  *            This module performs:
+  *                - Set the initial SP
+  *                - Set the initial PC == Reset_Handler,
+  *                - Set the vector table entries with the exceptions ISR address
+  *                - Branches to main in the C library (which eventually
+  *                  calls main()).
+  *            After Reset the Cortex-M4 processor is in Thread mode,
+  *            priority is Privileged, and the Stack is set to Main.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+    
+  .syntax unified
+  .cpu cortex-m4
+  .fpu softvfp
+  .thumb
+
+.global  g_pfnVectors
+.global  Default_Handler
+
+/* start address for the initialization values of the .data section. 
+defined in linker script */
+.word  _sidata
+/* start address for the .data section. defined in linker script */  
+.word  _sdata
+/* end address for the .data section. defined in linker script */
+.word  _edata
+/* start address for the .bss section. defined in linker script */
+.word  _sbss
+/* end address for the .bss section. defined in linker script */
+.word  _ebss
+/* stack used for SystemInit_ExtMemCtl; always internal RAM used */
+
+/**
+ * @brief  This is the code that gets called when the processor first
+ *          starts execution following a reset event. Only the absolutely
+ *          necessary set is performed, after which the application
+ *          supplied main() routine is called. 
+ * @param  None
+ * @retval : None
+*/
+
+    .section  .text.Reset_Handler
+  .weak  Reset_Handler
+  .type  Reset_Handler, %function
+Reset_Handler:  
+  ldr   sp, =_estack     /* set stack pointer */
+
+/* Copy the data segment initializers from flash to SRAM */  
+  ldr r0, =_sdata
+  ldr r1, =_edata
+  ldr r2, =_sidata
+  movs r3, #0
+  b LoopCopyDataInit
+
+CopyDataInit:
+  ldr r4, [r2, r3]
+  str r4, [r0, r3]
+  adds r3, r3, #4
+
+LoopCopyDataInit:
+  adds r4, r0, r3
+  cmp r4, r1
+  bcc CopyDataInit
+  
+/* Zero fill the bss segment. */
+  ldr r2, =_sbss
+  ldr r4, =_ebss
+  movs r3, #0
+  b LoopFillZerobss
+
+FillZerobss:
+  str  r3, [r2]
+  adds r2, r2, #4
+
+LoopFillZerobss:
+  cmp r2, r4
+  bcc FillZerobss
+
+/* Call the clock system initialization function.*/
+  bl  SystemInit   
+/* Call static constructors */
+    bl __libc_init_array
+/* Call the application's entry point.*/
+  bl  main
+  bx  lr    
+.size  Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief  This is the code that gets called when the processor receives an 
+ *         unexpected interrupt.  This simply enters an infinite loop, preserving
+ *         the system state for examination by a debugger.
+ * @param  None     
+ * @retval None       
+*/
+    .section  .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+  b  Infinite_Loop
+  .size  Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex M3. Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+* 
+*******************************************************************************/
+   .section  .isr_vector,"a",%progbits
+  .type  g_pfnVectors, %object
+  .size  g_pfnVectors, .-g_pfnVectors 
+  
+  g_pfnVectors:
+  .word  _estack
+  .word  Reset_Handler
+
+  .word  NMI_Handler
+  .word  HardFault_Handler
+  .word  MemManage_Handler
+  .word  BusFault_Handler
+  .word  UsageFault_Handler
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  SVC_Handler
+  .word  DebugMon_Handler
+  .word  0
+  .word  PendSV_Handler
+  .word  SysTick_Handler
+  
+  /* External Interrupts */
+  .word     WWDG_IRQHandler                   /* Window WatchDog              */                                        
+  .word     PVD_IRQHandler                    /* PVD through EXTI Line detection */                        
+  .word     TAMP_STAMP_IRQHandler             /* Tamper and TimeStamps through the EXTI line */            
+  .word     RTC_WKUP_IRQHandler               /* RTC Wakeup through the EXTI line */                      
+  .word     FLASH_IRQHandler                  /* FLASH                        */                                          
+  .word     RCC_IRQHandler                    /* RCC                          */                                            
+  .word     EXTI0_IRQHandler                  /* EXTI Line0                   */                        
+  .word     EXTI1_IRQHandler                  /* EXTI Line1                   */                          
+  .word     EXTI2_IRQHandler                  /* EXTI Line2                   */                          
+  .word     EXTI3_IRQHandler                  /* EXTI Line3                   */                          
+  .word     EXTI4_IRQHandler                  /* EXTI Line4                   */                          
+  .word     DMA1_Stream0_IRQHandler           /* DMA1 Stream 0                */                  
+  .word     DMA1_Stream1_IRQHandler           /* DMA1 Stream 1                */                   
+  .word     DMA1_Stream2_IRQHandler           /* DMA1 Stream 2                */                   
+  .word     DMA1_Stream3_IRQHandler           /* DMA1 Stream 3                */                   
+  .word     DMA1_Stream4_IRQHandler           /* DMA1 Stream 4                */                   
+  .word     DMA1_Stream5_IRQHandler           /* DMA1 Stream 5                */                   
+  .word     DMA1_Stream6_IRQHandler           /* DMA1 Stream 6                */                   
+  .word     ADC_IRQHandler                    /* ADC1, ADC2 and ADC3s         */                   
+  .word     CAN1_TX_IRQHandler                /* CAN1 TX                      */                         
+  .word     CAN1_RX0_IRQHandler               /* CAN1 RX0                     */                          
+  .word     CAN1_RX1_IRQHandler               /* CAN1 RX1                     */                          
+  .word     CAN1_SCE_IRQHandler               /* CAN1 SCE                     */                          
+  .word     EXTI9_5_IRQHandler                /* External Line[9:5]s          */                          
+  .word     TIM1_BRK_TIM9_IRQHandler          /* TIM1 Break and TIM9          */         
+  .word     TIM1_UP_TIM10_IRQHandler          /* TIM1 Update and TIM10        */         
+  .word     TIM1_TRG_COM_TIM11_IRQHandler     /* TIM1 Trigger and Commutation and TIM11 */
+  .word     TIM1_CC_IRQHandler                /* TIM1 Capture Compare         */                          
+  .word     TIM2_IRQHandler                   /* TIM2                         */                   
+  .word     TIM3_IRQHandler                   /* TIM3                         */                   
+  .word     TIM4_IRQHandler                   /* TIM4                         */                   
+  .word     I2C1_EV_IRQHandler                /* I2C1 Event                   */                          
+  .word     I2C1_ER_IRQHandler                /* I2C1 Error                   */                          
+  .word     I2C2_EV_IRQHandler                /* I2C2 Event                   */                          
+  .word     I2C2_ER_IRQHandler                /* I2C2 Error                   */                            
+  .word     SPI1_IRQHandler                   /* SPI1                         */                   
+  .word     SPI2_IRQHandler                   /* SPI2                         */                   
+  .word     USART1_IRQHandler                 /* USART1                       */                   
+  .word     USART2_IRQHandler                 /* USART2                       */                   
+  .word     USART3_IRQHandler                 /* USART3                       */                   
+  .word     EXTI15_10_IRQHandler              /* External Line[15:10]s        */                          
+  .word     RTC_Alarm_IRQHandler              /* RTC Alarm (A and B) through EXTI Line */                 
+  .word     OTG_FS_WKUP_IRQHandler            /* USB OTG FS Wakeup through EXTI line */                       
+  .word     TIM8_BRK_TIM12_IRQHandler         /* TIM8 Break and TIM12         */         
+  .word     TIM8_UP_TIM13_IRQHandler          /* TIM8 Update and TIM13        */         
+  .word     TIM8_TRG_COM_TIM14_IRQHandler     /* TIM8 Trigger and Commutation and TIM14 */
+  .word     TIM8_CC_IRQHandler                /* TIM8 Capture Compare         */                          
+  .word     DMA1_Stream7_IRQHandler           /* DMA1 Stream7                 */                          
+  .word     FMC_IRQHandler                    /* FMC                          */                   
+  .word     SDIO_IRQHandler                   /* SDIO                         */                   
+  .word     TIM5_IRQHandler                   /* TIM5                         */                   
+  .word     SPI3_IRQHandler                   /* SPI3                         */                   
+  .word     UART4_IRQHandler                  /* UART4                        */                   
+  .word     UART5_IRQHandler                  /* UART5                        */                   
+  .word     TIM6_DAC_IRQHandler               /* TIM6 and DAC1&2 underrun errors */                   
+  .word     TIM7_IRQHandler                   /* TIM7                         */
+  .word     DMA2_Stream0_IRQHandler           /* DMA2 Stream 0                */                   
+  .word     DMA2_Stream1_IRQHandler           /* DMA2 Stream 1                */                   
+  .word     DMA2_Stream2_IRQHandler           /* DMA2 Stream 2                */                   
+  .word     DMA2_Stream3_IRQHandler           /* DMA2 Stream 3                */                   
+  .word     DMA2_Stream4_IRQHandler           /* DMA2 Stream 4                */                   
+  .word     ETH_IRQHandler                    /* Ethernet                     */                   
+  .word     ETH_WKUP_IRQHandler               /* Ethernet Wakeup through EXTI line */                     
+  .word     CAN2_TX_IRQHandler                /* CAN2 TX                      */                          
+  .word     CAN2_RX0_IRQHandler               /* CAN2 RX0                     */                          
+  .word     CAN2_RX1_IRQHandler               /* CAN2 RX1                     */                          
+  .word     CAN2_SCE_IRQHandler               /* CAN2 SCE                     */                          
+  .word     OTG_FS_IRQHandler                 /* USB OTG FS                   */                   
+  .word     DMA2_Stream5_IRQHandler           /* DMA2 Stream 5                */                   
+  .word     DMA2_Stream6_IRQHandler           /* DMA2 Stream 6                */                   
+  .word     DMA2_Stream7_IRQHandler           /* DMA2 Stream 7                */                   
+  .word     USART6_IRQHandler                 /* USART6                       */                    
+  .word     I2C3_EV_IRQHandler                /* I2C3 event                   */                          
+  .word     I2C3_ER_IRQHandler                /* I2C3 error                   */                          
+  .word     OTG_HS_EP1_OUT_IRQHandler         /* USB OTG HS End Point 1 Out   */                   
+  .word     OTG_HS_EP1_IN_IRQHandler          /* USB OTG HS End Point 1 In    */                   
+  .word     OTG_HS_WKUP_IRQHandler            /* USB OTG HS Wakeup through EXTI */                         
+  .word     OTG_HS_IRQHandler                 /* USB OTG HS                   */                   
+  .word     DCMI_IRQHandler                   /* DCMI                         */                   
+  .word     0                                 /* Reserved                     */                   
+  .word     HASH_RNG_IRQHandler               /* Hash and Rng                 */
+  .word     FPU_IRQHandler                    /* FPU                          */
+  .word     UART7_IRQHandler                  /* UART7                        */      
+  .word     UART8_IRQHandler                  /* UART8                        */
+  .word     SPI4_IRQHandler                   /* SPI4                         */
+  .word     SPI5_IRQHandler                   /* SPI5 						  */
+  .word     SPI6_IRQHandler                   /* SPI6						  */
+  .word     SAI1_IRQHandler                   /* SAI1						  */
+  .word     LTDC_IRQHandler                   /* LTDC           		      */
+  .word     LTDC_ER_IRQHandler                /* LTDC error          	      */
+  .word     DMA2D_IRQHandler                  /* DMA2D                        */
+  .word     QUADSPI_IRQHandler                /* QUADSPI             	      */
+  .word     DSI_IRQHandler                    /* DSI                          */  
+  
+ 
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler. 
+* As they are weak aliases, any function with the same name will override 
+* this definition.
+* 
+*******************************************************************************/
+   .weak      NMI_Handler
+   .thumb_set NMI_Handler,Default_Handler
+  
+   .weak      HardFault_Handler
+   .thumb_set HardFault_Handler,Default_Handler
+  
+   .weak      MemManage_Handler
+   .thumb_set MemManage_Handler,Default_Handler
+  
+   .weak      BusFault_Handler
+   .thumb_set BusFault_Handler,Default_Handler
+
+   .weak      UsageFault_Handler
+   .thumb_set UsageFault_Handler,Default_Handler
+
+   .weak      SVC_Handler
+   .thumb_set SVC_Handler,Default_Handler
+
+   .weak      DebugMon_Handler
+   .thumb_set DebugMon_Handler,Default_Handler
+
+   .weak      PendSV_Handler
+   .thumb_set PendSV_Handler,Default_Handler
+
+   .weak      SysTick_Handler
+   .thumb_set SysTick_Handler,Default_Handler              
+  
+   .weak      WWDG_IRQHandler                   
+   .thumb_set WWDG_IRQHandler,Default_Handler      
+                  
+   .weak      PVD_IRQHandler      
+   .thumb_set PVD_IRQHandler,Default_Handler
+               
+   .weak      TAMP_STAMP_IRQHandler            
+   .thumb_set TAMP_STAMP_IRQHandler,Default_Handler
+            
+   .weak      RTC_WKUP_IRQHandler                  
+   .thumb_set RTC_WKUP_IRQHandler,Default_Handler
+            
+   .weak      FLASH_IRQHandler         
+   .thumb_set FLASH_IRQHandler,Default_Handler
+                  
+   .weak      RCC_IRQHandler      
+   .thumb_set RCC_IRQHandler,Default_Handler
+                  
+   .weak      EXTI0_IRQHandler         
+   .thumb_set EXTI0_IRQHandler,Default_Handler
+                  
+   .weak      EXTI1_IRQHandler         
+   .thumb_set EXTI1_IRQHandler,Default_Handler
+                     
+   .weak      EXTI2_IRQHandler         
+   .thumb_set EXTI2_IRQHandler,Default_Handler 
+                 
+   .weak      EXTI3_IRQHandler         
+   .thumb_set EXTI3_IRQHandler,Default_Handler
+                        
+   .weak      EXTI4_IRQHandler         
+   .thumb_set EXTI4_IRQHandler,Default_Handler
+                  
+   .weak      DMA1_Stream0_IRQHandler               
+   .thumb_set DMA1_Stream0_IRQHandler,Default_Handler
+         
+   .weak      DMA1_Stream1_IRQHandler               
+   .thumb_set DMA1_Stream1_IRQHandler,Default_Handler
+                  
+   .weak      DMA1_Stream2_IRQHandler               
+   .thumb_set DMA1_Stream2_IRQHandler,Default_Handler
+                  
+   .weak      DMA1_Stream3_IRQHandler               
+   .thumb_set DMA1_Stream3_IRQHandler,Default_Handler 
+                 
+   .weak      DMA1_Stream4_IRQHandler              
+   .thumb_set DMA1_Stream4_IRQHandler,Default_Handler
+                  
+   .weak      DMA1_Stream5_IRQHandler               
+   .thumb_set DMA1_Stream5_IRQHandler,Default_Handler
+                  
+   .weak      DMA1_Stream6_IRQHandler               
+   .thumb_set DMA1_Stream6_IRQHandler,Default_Handler
+                  
+   .weak      ADC_IRQHandler      
+   .thumb_set ADC_IRQHandler,Default_Handler
+               
+   .weak      CAN1_TX_IRQHandler   
+   .thumb_set CAN1_TX_IRQHandler,Default_Handler
+            
+   .weak      CAN1_RX0_IRQHandler                  
+   .thumb_set CAN1_RX0_IRQHandler,Default_Handler
+                           
+   .weak      CAN1_RX1_IRQHandler                  
+   .thumb_set CAN1_RX1_IRQHandler,Default_Handler
+            
+   .weak      CAN1_SCE_IRQHandler                  
+   .thumb_set CAN1_SCE_IRQHandler,Default_Handler
+            
+   .weak      EXTI9_5_IRQHandler   
+   .thumb_set EXTI9_5_IRQHandler,Default_Handler
+            
+   .weak      TIM1_BRK_TIM9_IRQHandler            
+   .thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler
+            
+   .weak      TIM1_UP_TIM10_IRQHandler            
+   .thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler
+
+   .weak      TIM1_TRG_COM_TIM11_IRQHandler      
+   .thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler
+      
+   .weak      TIM1_CC_IRQHandler   
+   .thumb_set TIM1_CC_IRQHandler,Default_Handler
+                  
+   .weak      TIM2_IRQHandler            
+   .thumb_set TIM2_IRQHandler,Default_Handler
+                  
+   .weak      TIM3_IRQHandler            
+   .thumb_set TIM3_IRQHandler,Default_Handler
+                  
+   .weak      TIM4_IRQHandler            
+   .thumb_set TIM4_IRQHandler,Default_Handler
+                  
+   .weak      I2C1_EV_IRQHandler   
+   .thumb_set I2C1_EV_IRQHandler,Default_Handler
+                     
+   .weak      I2C1_ER_IRQHandler   
+   .thumb_set I2C1_ER_IRQHandler,Default_Handler
+                     
+   .weak      I2C2_EV_IRQHandler   
+   .thumb_set I2C2_EV_IRQHandler,Default_Handler
+                  
+   .weak      I2C2_ER_IRQHandler   
+   .thumb_set I2C2_ER_IRQHandler,Default_Handler
+                           
+   .weak      SPI1_IRQHandler            
+   .thumb_set SPI1_IRQHandler,Default_Handler
+                        
+   .weak      SPI2_IRQHandler            
+   .thumb_set SPI2_IRQHandler,Default_Handler
+                  
+   .weak      USART1_IRQHandler      
+   .thumb_set USART1_IRQHandler,Default_Handler
+                     
+   .weak      USART2_IRQHandler      
+   .thumb_set USART2_IRQHandler,Default_Handler
+                     
+   .weak      USART3_IRQHandler      
+   .thumb_set USART3_IRQHandler,Default_Handler
+                  
+   .weak      EXTI15_10_IRQHandler               
+   .thumb_set EXTI15_10_IRQHandler,Default_Handler
+               
+   .weak      RTC_Alarm_IRQHandler               
+   .thumb_set RTC_Alarm_IRQHandler,Default_Handler
+            
+   .weak      OTG_FS_WKUP_IRQHandler         
+   .thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler
+            
+   .weak      TIM8_BRK_TIM12_IRQHandler         
+   .thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler
+         
+   .weak      TIM8_UP_TIM13_IRQHandler            
+   .thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler
+         
+   .weak      TIM8_TRG_COM_TIM14_IRQHandler      
+   .thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler
+      
+   .weak      TIM8_CC_IRQHandler   
+   .thumb_set TIM8_CC_IRQHandler,Default_Handler
+                  
+   .weak      DMA1_Stream7_IRQHandler               
+   .thumb_set DMA1_Stream7_IRQHandler,Default_Handler
+                     
+   .weak      FMC_IRQHandler            
+   .thumb_set FMC_IRQHandler,Default_Handler
+                     
+   .weak      SDIO_IRQHandler            
+   .thumb_set SDIO_IRQHandler,Default_Handler
+                     
+   .weak      TIM5_IRQHandler            
+   .thumb_set TIM5_IRQHandler,Default_Handler
+                     
+   .weak      SPI3_IRQHandler            
+   .thumb_set SPI3_IRQHandler,Default_Handler
+                     
+   .weak      UART4_IRQHandler         
+   .thumb_set UART4_IRQHandler,Default_Handler
+                  
+   .weak      UART5_IRQHandler         
+   .thumb_set UART5_IRQHandler,Default_Handler
+                  
+   .weak      TIM6_DAC_IRQHandler                  
+   .thumb_set TIM6_DAC_IRQHandler,Default_Handler
+               
+   .weak      TIM7_IRQHandler            
+   .thumb_set TIM7_IRQHandler,Default_Handler
+         
+   .weak      DMA2_Stream0_IRQHandler               
+   .thumb_set DMA2_Stream0_IRQHandler,Default_Handler
+               
+   .weak      DMA2_Stream1_IRQHandler               
+   .thumb_set DMA2_Stream1_IRQHandler,Default_Handler
+                  
+   .weak      DMA2_Stream2_IRQHandler               
+   .thumb_set DMA2_Stream2_IRQHandler,Default_Handler
+            
+   .weak      DMA2_Stream3_IRQHandler               
+   .thumb_set DMA2_Stream3_IRQHandler,Default_Handler
+            
+   .weak      DMA2_Stream4_IRQHandler               
+   .thumb_set DMA2_Stream4_IRQHandler,Default_Handler
+   
+   .weak      ETH_IRQHandler               
+   .thumb_set ETH_IRQHandler,Default_Handler
+
+   .weak      ETH_WKUP_IRQHandler               
+   .thumb_set ETH_WKUP_IRQHandler,Default_Handler
+
+   .weak      CAN2_TX_IRQHandler   
+   .thumb_set CAN2_TX_IRQHandler,Default_Handler
+                           
+   .weak      CAN2_RX0_IRQHandler                  
+   .thumb_set CAN2_RX0_IRQHandler,Default_Handler
+                           
+   .weak      CAN2_RX1_IRQHandler                  
+   .thumb_set CAN2_RX1_IRQHandler,Default_Handler
+                           
+   .weak      CAN2_SCE_IRQHandler                  
+   .thumb_set CAN2_SCE_IRQHandler,Default_Handler
+                           
+   .weak      OTG_FS_IRQHandler      
+   .thumb_set OTG_FS_IRQHandler,Default_Handler
+                     
+   .weak      DMA2_Stream5_IRQHandler               
+   .thumb_set DMA2_Stream5_IRQHandler,Default_Handler
+                  
+   .weak      DMA2_Stream6_IRQHandler               
+   .thumb_set DMA2_Stream6_IRQHandler,Default_Handler
+                  
+   .weak      DMA2_Stream7_IRQHandler               
+   .thumb_set DMA2_Stream7_IRQHandler,Default_Handler
+                  
+   .weak      USART6_IRQHandler      
+   .thumb_set USART6_IRQHandler,Default_Handler
+                        
+   .weak      I2C3_EV_IRQHandler   
+   .thumb_set I2C3_EV_IRQHandler,Default_Handler
+                        
+   .weak      I2C3_ER_IRQHandler   
+   .thumb_set I2C3_ER_IRQHandler,Default_Handler
+                        
+   .weak      OTG_HS_EP1_OUT_IRQHandler         
+   .thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler
+               
+   .weak      OTG_HS_EP1_IN_IRQHandler            
+   .thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler
+               
+   .weak      OTG_HS_WKUP_IRQHandler         
+   .thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler
+            
+   .weak      OTG_HS_IRQHandler      
+   .thumb_set OTG_HS_IRQHandler,Default_Handler
+                  
+   .weak      DCMI_IRQHandler            
+   .thumb_set DCMI_IRQHandler,Default_Handler
+                                
+   .weak      HASH_RNG_IRQHandler                  
+   .thumb_set HASH_RNG_IRQHandler,Default_Handler   
+
+   .weak      FPU_IRQHandler                  
+   .thumb_set FPU_IRQHandler,Default_Handler  
+
+   .weak      UART7_IRQHandler            
+   .thumb_set UART7_IRQHandler,Default_Handler
+
+   .weak      UART8_IRQHandler            
+   .thumb_set UART8_IRQHandler,Default_Handler
+
+   .weak      SPI4_IRQHandler            
+   .thumb_set SPI4_IRQHandler,Default_Handler
+
+   .weak      SPI5_IRQHandler            
+   .thumb_set SPI5_IRQHandler,Default_Handler
+
+   .weak      SPI6_IRQHandler            
+   .thumb_set SPI6_IRQHandler,Default_Handler
+
+   .weak      SAI1_IRQHandler            
+   .thumb_set SAI1_IRQHandler,Default_Handler
+
+   .weak      LTDC_IRQHandler            
+   .thumb_set LTDC_IRQHandler,Default_Handler
+
+   .weak      LTDC_ER_IRQHandler            
+   .thumb_set LTDC_ER_IRQHandler,Default_Handler
+
+   .weak      DMA2D_IRQHandler            
+   .thumb_set DMA2D_IRQHandler,Default_Handler
+   
+   .weak      QUADSPI_IRQHandler            
+   .thumb_set QUADSPI_IRQHandler,Default_Handler
+
+   .weak      DSI_IRQHandler            
+   .thumb_set DSI_IRQHandler,Default_Handler
diff --git a/Drivers/BSP/Components/Common/Release_Notes.html b/Drivers/BSP/Components/Common/Release_Notes.html
new file mode 100644
index 0000000..d419c70
--- /dev/null
+++ b/Drivers/BSP/Components/Common/Release_Notes.html
@@ -0,0 +1,759 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html xmlns:v="urn:schemas-microsoft-com:vml" xmlns:o="urn:schemas-microsoft-com:office:office" xmlns:w="urn:schemas-microsoft-com:office:word" xmlns="http://www.w3.org/TR/REC-html40"><head>
+
+
+
+
+
+
+
+
+
+
+
+  
+  <meta http-equiv="Content-Type" content="text/html; charset=ISO-8859-1">
+
+  
+  <link rel="File-List" href="Library_files/filelist.xml">
+
+  
+  <link rel="Edit-Time-Data" href="Library_files/editdata.mso"><!--[if !mso]> <style> v\:* {behavior:url(#default#VML);} o\:* {behavior:url(#default#VML);} w\:* {behavior:url(#default#VML);} .shape {behavior:url(#default#VML);} </style> <![endif]--><title>Release Notes for BSP Components Common Drivers</title><!--[if gte mso 9]><xml> <o:DocumentProperties> <o:Author>STMicroelectronics</o:Author> <o:LastAuthor>STMicroelectronics</o:LastAuthor> <o:Revision>37</o:Revision> <o:TotalTime>136</o:TotalTime> <o:Created>2009-02-27T19:26:00Z</o:Created> <o:LastSaved>2009-03-01T17:56:00Z</o:LastSaved> <o:Pages>1</o:Pages> <o:Words>522</o:Words> <o:Characters>2977</o:Characters> <o:Company>STMicroelectronics</o:Company> <o:Lines>24</o:Lines> <o:Paragraphs>6</o:Paragraphs> <o:CharactersWithSpaces>3493</o:CharactersWithSpaces> <o:Version>11.6568</o:Version> </o:DocumentProperties> </xml><![endif]--><!--[if gte mso 9]><xml> <w:WordDocument> <w:Zoom>110</w:Zoom> <w:ValidateAgainstSchemas/> <w:SaveIfXMLInvalid>false</w:SaveIfXMLInvalid> <w:IgnoreMixedContent>false</w:IgnoreMixedContent> <w:AlwaysShowPlaceholderText>false</w:AlwaysShowPlaceholderText> <w:BrowserLevel>MicrosoftInternetExplorer4</w:BrowserLevel> </w:WordDocument> </xml><![endif]--><!--[if gte mso 9]><xml> <w:LatentStyles DefLockedState="false" LatentStyleCount="156"> </w:LatentStyles> </xml><![endif]-->
+
+
+  
+
+  
+
+  
+  <style>
+<!--
+/* Style Definitions */
+p.MsoNormal, li.MsoNormal, div.MsoNormal
+{mso-style-parent:"";
+margin:0in;
+margin-bottom:.0001pt;
+mso-pagination:widow-orphan;
+font-size:12.0pt;
+font-family:"Times New Roman";
+mso-fareast-font-family:"Times New Roman";}
+h2
+{mso-style-next:Normal;
+margin-top:12.0pt;
+margin-right:0in;
+margin-bottom:3.0pt;
+margin-left:0in;
+mso-pagination:widow-orphan;
+page-break-after:avoid;
+mso-outline-level:2;
+font-size:14.0pt;
+font-family:Arial;
+font-weight:bold;
+font-style:italic;}
+a:link, span.MsoHyperlink
+{color:blue;
+text-decoration:underline;
+text-underline:single;}
+a:visited, span.MsoHyperlinkFollowed
+{color:blue;
+text-decoration:underline;
+text-underline:single;}
+p
+{mso-margin-top-alt:auto;
+margin-right:0in;
+mso-margin-bottom-alt:auto;
+margin-left:0in;
+mso-pagination:widow-orphan;
+font-size:12.0pt;
+font-family:"Times New Roman";
+mso-fareast-font-family:"Times New Roman";}
+@page Section1
+{size:8.5in 11.0in;
+margin:1.0in 1.25in 1.0in 1.25in;
+mso-header-margin:.5in;
+mso-footer-margin:.5in;
+mso-paper-source:0;}
+div.Section1
+{page:Section1;}
+-->
+  </style><!--[if gte mso 10]> <style> /* Style Definitions */ table.MsoNormalTable {mso-style-name:"Table Normal"; mso-tstyle-rowband-size:0; mso-tstyle-colband-size:0; mso-style-noshow:yes; mso-style-parent:""; mso-padding-alt:0in 5.4pt 0in 5.4pt; mso-para-margin:0in; mso-para-margin-bottom:.0001pt; mso-pagination:widow-orphan; font-size:10.0pt; font-family:"Times New Roman"; mso-ansi-language:#0400; mso-fareast-language:#0400; mso-bidi-language:#0400;} </style> <![endif]--><!--[if gte mso 9]><xml> <o:shapedefaults v:ext="edit" spidmax="5122"/> </xml><![endif]--><!--[if gte mso 9]><xml> <o:shapelayout v:ext="edit"> <o:idmap v:ext="edit" data="1"/> </o:shapelayout></xml><![endif]-->
+  <meta content="MCD Application Team" name="author"></head>
+<body link="blue" vlink="blue">
+<div class="Section1">
+<p class="MsoNormal"><span style="font-family: Arial;"><o:p><br>
+</o:p></span></p>
+<div align="center">
+<table class="MsoNormalTable" style="width: 675pt;" border="0" cellpadding="0" cellspacing="0" width="900">
+  <tbody>
+    <tr>
+      <td style="padding: 0cm;" valign="top">
+      <table class="MsoNormalTable" style="width: 675pt;" border="0" cellpadding="0" cellspacing="0" width="900">
+        <tbody>
+          <tr>
+            <td style="vertical-align: top;">
+            <p class="MsoNormal"><span style="font-size: 8pt; font-family: Arial; color: blue;"><a href="../../../../Release_Notes.html">Back to Release page</a><o:p></o:p></span></p>
+            </td>
+          </tr>
+          <tr style="">
+            <td style="padding: 1.5pt;">
+            
+            <h1 style="margin-bottom: 18pt; text-align: center;" align="center"><span style="font-size: 20pt; font-family: Verdana; color: rgb(51, 102, 255);">Release
+Notes for BSP Components Common&nbsp; Drivers</span><span style="font-size: 20pt; font-family: Verdana;"><o:p></o:p></span></h1>
+
+            <p class="MsoNormal" style="text-align: center;" align="center"><span style="font-size: 10pt; font-family: Arial; color: black;">Copyright
+2015 STMicroelectronics</span><span style="color: black;"><u1:p></u1:p><o:p></o:p></span></p>
+            <p class="MsoNormal" style="text-align: center;" align="center"><span style="font-size: 10pt; font-family: Arial; color: black;"><img alt="" id="_x0000_i1025" src="../../../../_htmresc/st_logo.png" style="border: 0px solid ; width: 86px; height: 65px;"></span><span style="font-size: 10pt;"><o:p></o:p></span></p>
+            </td>
+          </tr>
+        </tbody>
+      </table>
+      <p class="MsoNormal"><span style="font-family: Arial; display: none;"><o:p>&nbsp;</o:p></span></p>
+      <table class="MsoNormalTable" style="width: 675pt;" border="0" cellpadding="0" width="900">
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+            </span>
+            <h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial;"><a name="History"></a><span style="font-size: 12pt; color: white;">Update History</span></h2>
+            <h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 210px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V4.0.1 / 21-July-2015 <o:p></o:p></span></h3><p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
+Changes<o:p></o:p></span></u></b></p>
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+            <span style="font-size: 10pt; font-family: Verdana;"></span><ul style="list-style-type: square;"><li><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;">tsensor.h: Fix compilation issue on TSENSOR_InitTypeDef</span></li></ul><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 210px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V4.0.0 / 22-June-2015 <o:p></o:p></span></h3><p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
+Changes<o:p></o:p></span></u></b></p>
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+
+            <span style="font-size: 10pt; font-family: Verdana;"></span><ul style="list-style-type: square;"><li><span style="font-size: 10pt; font-family: Verdana;">accelero.h: add <span style="font-style: italic;">*DeInit</span> field in <span style="font-style: italic;">ACCELERO_DrvTypeDef</span> structure</span></li><li><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;">audio.h: add <span style="font-style: italic;">*DeInit</span> field in <span style="font-style: italic;">AUDIO_DrvTypeDef</span> structure</span></li><li><span style="font-size: 10pt; font-family: Verdana;">idd.h:&nbsp;</span></li><ul><li><span style="font-size: 10pt; font-family: Verdana;">add <span style="font-style: italic;">Shunt0StabDelay, Shunt1StabDelay, Shunt2StabDelay, Shunt3StabDelay, Shunt4StabDelay and ShuntNbOnBoard </span></span><span style="font-size: 10pt; font-family: Verdana;">fields in <span style="font-style: italic;">IDD_ConfigTypeDef</span>&nbsp;</span><span style="font-size: 10pt; font-family: Verdana;">structure</span></li><li><span style="font-size: 10pt; font-family: Verdana;">rename <span style="font-style: italic;">ShuntNumber</span> field to <span style="font-style: italic;">ShuntNbUsed</span> in </span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">IDD_ConfigTypeDef</span> structure</span></li></ul><li><span style="font-size: 10pt; font-family: Verdana;">magneto.h: add <span style="font-style: italic;">*DeInit</span> field in <span style="font-style: italic;">MAGNETO_DrvTypeDef</span> structure</span></li><li><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">Important Note:</span>&nbsp; this release V4.0.0 is not backward compatible with V3.0.0</span></li></ul><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 210px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V3.0.0 / 28-April-2015 <o:p></o:p></span></h3><p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
+Changes<o:p></o:p></span></u></b></p>
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+            <span style="font-size: 10pt; font-family: Verdana;"></span><ul style="list-style-type: square;"><li><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;">accelero.h:&nbsp;</span><span style="font-size: 10pt; font-family: Verdana;">add <span style="font-style: italic;">*LowPower</span> field in <span style="font-style: italic;">ACCELERO_DrvTypeDef</span> structure</span><span style="font-size: 10pt; font-family: Verdana;"></span></li><li><span style="font-size: 10pt; font-family: Verdana;">magneto.h:&nbsp;</span><span style="font-size: 10pt; font-family: Verdana;">add <span style="font-style: italic;">*LowPower</span> field in <span style="font-style: italic;">MAGNETO_DrvTypeDef</span> structure</span></li><li><span style="font-size: 10pt; font-family: Verdana;">gyro.h: add <span style="font-style: italic;">*DeInit</span> and <span style="font-style: italic;">*LowPower</span> fields in <span style="font-style: italic;">GYRO_DrvTypeDef</span> structure<br></span></li><li><span style="font-size: 10pt; font-family: Verdana;">camera.h: add <span style="font-style: italic;">CAMERA_COLOR_EFFECT_NONE</span> define</span></li><li><span style="font-size: 10pt; font-family: Verdana;">idd.h:&nbsp;</span></li><ul><li><span style="font-size: 10pt; font-family: Verdana;">add <span style="font-style: italic;">MeasureNb</span>, <span style="font-style: italic;">DeltaDelayUnit</span> and <span style="font-style: italic;">DeltaDelayValue</span> fields in <span style="font-style: italic;">IDD_ConfigTypeDef</span> structure</span></li><li><span style="font-size: 10pt; font-family: Verdana;">rename <span style="font-style: italic;">PreDelay</span> field to <span style="font-style: italic;">PreDelayUnit</span> in </span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">IDD_ConfigTypeDef</span> structure</span></li></ul>
+              <li><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">Important Note:</span>&nbsp; this release V3.0.0 is not backward compatible with V2.2.0<br>
+</span></li>
+</ul><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 210px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V2.2.0 / 09-February-2015 <o:p></o:p></span></h3><p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
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+            <span style="font-size: 10pt; font-family: Verdana;"></span><ul style="list-style-type: square;"><li><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;">Magnetometer </span><span style="font-size: 10pt; font-family: Verdana;">driver function prototypes added (magneto.h file)</span></li><li><span style="font-size: 10pt; font-family: Verdana;">Update "idd.h" file to provide DeInit() and WakeUp() services in IDD current measurement driver</span></li></ul><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 210px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V2.1.0 / 06-February-2015 <o:p></o:p></span></h3><p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
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+            <span style="font-size: 10pt; font-family: Verdana;"></span><ul style="list-style-type: square;"><li><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;">IDD current measurement </span><span style="font-size: 10pt; font-family: Verdana;">driver function prototypes added (idd.h file)</span></li><li><span style="font-size: 10pt; font-family: Verdana;">io.h: add new typedef enum IO_PinState with IO_PIN_RESET and IO_PIN_SET values<br></span></li></ul><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 210px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V2.0.0 / 15-December-2014 <o:p></o:p></span></h3><p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
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+            <span style="font-size: 10pt; font-family: Verdana;"></span><ul style="list-style-type: square;"><li><span style="font-size: 10pt; font-family: Verdana;">Update "io.h" file to support MFX (Multi Function eXpander) device available on some STM32 boards</span></li><ul><li><span style="font-size: 10pt; font-family: Verdana;">add new entries for IO_ModeTypedef enumeration structure</span><span style="font-size: 10pt; font-family: Verdana;"></span></li><li><span style="font-size: 10pt; font-family: Verdana;">update the IO_DrvTypeDef structure</span></li><ul><li><span style="font-size: 10pt; font-family: Verdana;">Update all return values and function parameters to uint32_t</span></li><li><span style="font-size: 10pt; font-family: Verdana;">Add a return value for Config field</span></li></ul></ul><li style="font-family: Verdana;"><small><span style="font-weight: bold;">Important Note</span>: &nbsp;this version V2.0.0 is not backward compatible with V1.2.1</small></li></ul><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 180px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.2.1 / 02-December-2014 <o:p></o:p></span></h3>
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+
+
+
+            
+            
+            
+
+
+
+
+            
+            
+            
+
+            
+            
+
+
+            
+            <ul style="list-style-type: square;"><li><span style="font-size: 10pt; font-family: Verdana;">gyro.h: change &#8220;__GIRO_H&#8221; by &#8220;__GYRO_H&#8221; to fix compilation issue under Mac OS</span><span style="font-size: 10pt; font-family: Verdana;"></span></li></ul><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 180px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.2.0 / 18-June-2014 <o:p></o:p></span></h3><p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
+Changes<o:p></o:p></span></u></b></p>
+
+
+
+
+
+
+
+
+
+            <span style="font-size: 10pt; font-family: Verdana;"></span>
+
+
+            
+            <span style="font-size: 10pt; font-family: Verdana;"></span>
+
+
+            
+            <span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;"></span>
+
+
+
+
+
+
+            
+            
+            <span style="font-size: 10pt; font-family: Verdana;"></span>
+
+
+
+
+
+
+            
+            
+            <span style="font-size: 10pt; font-family: Verdana;"></span>
+
+
+
+
+
+            
+            
+            <span style="font-size: 10pt; font-family: Verdana;"></span>
+
+
+
+
+            
+            
+            <span style="font-size: 10pt; font-family: Verdana;"></span>
+
+            <span style="font-size: 10pt; font-family: Verdana;"></span>
+            
+
+
+            <span style="font-size: 10pt; font-family: Verdana;"></span><ul style="list-style-type: square;"><li><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;">EPD (</span><span style="font-size: 10pt; font-family: Verdana;">E Paper Display)&nbsp; driver function prototype added (epd.h file)<br>
+                </span></li></ul><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 180px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.1.0 / 21-March-2014 <o:p></o:p></span></h3><p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
+Changes<o:p></o:p></span></u></b></p>
+
+
+
+
+
+
+
+
+
+            <span style="font-size: 10pt; font-family: Verdana;"></span>
+
+
+            
+            <span style="font-size: 10pt; font-family: Verdana;"></span>
+
+
+            
+            <span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;"></span>
+
+
+
+
+
+
+            
+            
+            <span style="font-size: 10pt; font-family: Verdana;"></span>
+
+
+
+
+
+
+            
+            
+            <span style="font-size: 10pt; font-family: Verdana;"></span>
+
+
+
+
+
+            
+            
+            <span style="font-size: 10pt; font-family: Verdana;"></span>
+
+
+
+
+            
+            
+            <span style="font-size: 10pt; font-family: Verdana;"></span>
+
+            <span style="font-size: 10pt; font-family: Verdana;"></span>
+            
+
+
+            <span style="font-size: 10pt; font-family: Verdana;"></span><ul style="list-style-type: square;"><li><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;">Temperature Sensor driver function prototype added</span></li></ul><span style="font-size: 10pt; font-family: Verdana;"></span><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 180px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.0.0 / 18-February-2014 <o:p></o:p></span></h3>
+
+
+
+
+
+
+
+
+
+
+
+            
+            
+            
+            
+            
+            <p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
+Changes<o:p></o:p></span></u></b></p>
+
+
+
+
+
+
+
+
+
+            <span style="font-size: 10pt; font-family: Verdana;"></span>
+
+
+            
+            <span style="font-size: 10pt; font-family: Verdana;"></span>
+
+
+            
+            <span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;"></span>
+
+
+
+
+
+
+            
+            
+            <span style="font-size: 10pt; font-family: Verdana;"></span>
+
+
+
+
+
+
+            
+            
+            <span style="font-size: 10pt; font-family: Verdana;"></span>
+
+
+
+
+
+            
+            
+            <span style="font-size: 10pt; font-family: Verdana;"></span>
+
+
+
+
+            
+            
+            <span style="font-size: 10pt; font-family: Verdana;"></span>
+
+            <span style="font-size: 10pt; font-family: Verdana;"></span>
+            
+
+
+            <span style="font-size: 10pt; font-family: Verdana;"></span><ul style="list-style-type: square;"><li><span style="font-size: 10pt; font-family: Verdana;">First official release with &nbsp;</span><span style="font-size: 10pt; font-family: Verdana;">Accelerometer, </span><span style="font-size: 10pt; font-family: Verdana;">Audio, Camera, Gyroscope, IO, LCD and Touch Screen drivers function prototypes </span><span style="font-size: 10pt; font-family: Verdana;"></span></li></ul><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic; font-weight: bold;"></span></span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic; font-weight: bold;"></span></span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic; font-weight: bold;"></span></span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic; font-weight: bold;"></span></span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic; font-weight: bold;"></span></span><span style="font-size: 10pt; font-family: Verdana;"></span><h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial;"><a name="License"></a><span style="font-size: 12pt; color: white;">License<o:p></o:p></span><br></h2>
+            <div style="text-align: justify;"><font size="-1"><span style="font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are
+met:</span><br>
+            </font>
+            <ol><li><font size="-1"><span style="font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.</span><span style="font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"></span></font></li><li><font size="-1"><span style="font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Redistributions
+in binary form must reproduce the above copyright notice, this list of
+conditions and the following disclaimer in </span><span style="font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">the documentation and/or other materials provided with the distribution.</span><span style="font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"></span></font></li><li><font size="-1"><span style="font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived </span><br>
+                </font>
+              </li></ol>
+            <font size="-1"><span style="font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; from this software without specific prior written permission.</span><br>
+            <span style="font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"></span><br>
+            <span style="font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED</span><span style="font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"> WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A </span><span style="font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY </span><span style="font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, </span><span style="font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER</span><span style="font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"> CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR </span><span style="font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.</span></font>
+            
+            </div>
+<p class="MsoNormal"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;; color: black;"><font size="-1"></font><o:p></o:p></span></p>
+<b><span style="font-size: 10pt; font-family: Verdana; color: black;"></span></b>
+            
+            <div class="MsoNormal" style="text-align: center;" align="center"><span style="color: black;">
+            <hr align="center" size="2" width="100%"></span></div>
+            <p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt; text-align: center;" align="center"><span style="font-size: 10pt; font-family: Verdana; color: black;">For
+complete documentation on </span><span style="font-size: 10pt; font-family: Verdana;">STM32<span style="color: black;">&nbsp;Microcontrollers
+visit </span><u><span style="color: blue;"><a href="http://www.st.com/internet/mcu/class/1734.jsp" target="_blank">www.st.com/STM32</a></span></u></span><span style="font-size: 10pt; font-family: Verdana;"><a target="_blank" href="http://www.st.com/internet/mcu/family/141.jsp"><u><span style="color: blue;"></span></u></a></span><span style="font-size: 10pt; font-family: Verdana;"><u><span style="color: blue;"></span></u></span><span style="color: black;"><o:p></o:p></span></p>
+            </td>
+          </tr>
+        </tbody>
+      </table>
+      <p class="MsoNormal"><span style="font-size: 10pt;"><o:p></o:p></span></p>
+      </td>
+    </tr>
+  </tbody>
+</table>
+</div>
+<p class="MsoNormal"><o:p>&nbsp;</o:p></p>
+</div>
+
+</body></html>
\ No newline at end of file
diff --git a/Drivers/BSP/Components/Common/accelero.h b/Drivers/BSP/Components/Common/accelero.h
new file mode 100644
index 0000000..dad8d8d
--- /dev/null
+++ b/Drivers/BSP/Components/Common/accelero.h
@@ -0,0 +1,143 @@
+/**
+  ******************************************************************************
+  * @file    accelero.h
+  * @author  MCD Application Team
+  * @version V4.0.1
+  * @date    21-July-2015
+  * @brief   This header file contains the functions prototypes for the Accelerometer driver.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __ACCELERO_H
+#define __ACCELERO_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include <stdint.h>
+
+/** @addtogroup BSP
+  * @{
+  */
+
+/** @addtogroup Components
+  * @{
+  */
+    
+/** @addtogroup ACCELERO
+  * @{
+  */
+
+/** @defgroup ACCELERO_Exported_Types
+  * @{
+  */ 
+
+/** @defgroup ACCELERO_Driver_structure  Accelerometer Driver structure
+  * @{
+  */
+typedef struct
+{  
+  void      (*Init)(uint16_t);
+  void      (*DeInit)(void); 
+  uint8_t   (*ReadID)(void);
+  void      (*Reset)(void);
+  void      (*LowPower)(void);
+  void      (*ConfigIT)(void);
+  void      (*EnableIT)(uint8_t);
+  void      (*DisableIT)(uint8_t);
+  uint8_t   (*ITStatus)(uint16_t);
+  void      (*ClearIT)(void);
+  void      (*FilterConfig)(uint8_t);
+  void      (*FilterCmd)(uint8_t);
+  void      (*GetXYZ)(int16_t *);
+}ACCELERO_DrvTypeDef;
+/**
+  * @}
+  */
+
+/** @defgroup ACCELERO_Configuration_structure  Accelerometer Configuration structure
+  * @{
+  */
+
+/* ACCELERO struct */
+typedef struct
+{
+  uint8_t Power_Mode;                         /* Power-down/Normal Mode */
+  uint8_t AccOutput_DataRate;                 /* OUT data rate */
+  uint8_t Axes_Enable;                        /* Axes enable */
+  uint8_t High_Resolution;                    /* High Resolution enabling/disabling */
+  uint8_t BlockData_Update;                   /* Block Data Update */
+  uint8_t Endianness;                         /* Endian Data selection */
+  uint8_t AccFull_Scale;                      /* Full Scale selection */
+  uint8_t Communication_Mode;
+}ACCELERO_InitTypeDef;
+
+/* ACCELERO High Pass Filter struct */
+typedef struct
+{
+  uint8_t HighPassFilter_Mode_Selection;      /* Internal filter mode */
+  uint8_t HighPassFilter_CutOff_Frequency;    /* High pass filter cut-off frequency */
+  uint8_t HighPassFilter_AOI1;                /* HPF_enabling/disabling for AOI function on interrupt 1 */
+  uint8_t HighPassFilter_AOI2;                /* HPF_enabling/disabling for AOI function on interrupt 2 */
+  uint8_t HighPassFilter_Data_Sel;
+  uint8_t HighPassFilter_Stat;
+}ACCELERO_FilterConfigTypeDef;
+
+/**
+  * @}
+  */
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __ACCELERO_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Drivers/BSP/Components/Common/audio.h b/Drivers/BSP/Components/Common/audio.h
new file mode 100644
index 0000000..6a04b69
--- /dev/null
+++ b/Drivers/BSP/Components/Common/audio.h
@@ -0,0 +1,122 @@
+/**
+  ******************************************************************************
+  * @file    audio.h
+  * @author  MCD Application Team
+  * @version V4.0.1
+  * @date    21-July-2015
+  * @brief   This header file contains the common defines and functions prototypes
+  *          for the Audio driver.  
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __AUDIO_H
+#define __AUDIO_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include <stdint.h>
+
+/** @addtogroup BSP
+  * @{
+  */
+
+/** @addtogroup Components
+  * @{
+  */
+    
+/** @addtogroup AUDIO
+  * @{
+  */
+
+/** @defgroup AUDIO_Exported_Constants
+  * @{
+  */
+
+/* Codec audio Standards */
+#define CODEC_STANDARD                0x04
+#define I2S_STANDARD                  I2S_STANDARD_PHILIPS
+
+/**
+  * @}
+  */
+
+/** @defgroup AUDIO_Exported_Types
+  * @{
+  */
+
+/** @defgroup AUDIO_Driver_structure  Audio Driver structure
+  * @{
+  */
+typedef struct
+{
+  uint32_t  (*Init)(uint16_t, uint16_t, uint8_t, uint32_t);
+  void      (*DeInit)(void);
+  uint32_t  (*ReadID)(uint16_t);
+  uint32_t  (*Play)(uint16_t, uint16_t*, uint16_t);
+  uint32_t  (*Pause)(uint16_t);
+  uint32_t  (*Resume)(uint16_t);
+  uint32_t  (*Stop)(uint16_t, uint32_t);
+  uint32_t  (*SetFrequency)(uint16_t, uint32_t);
+  uint32_t  (*SetVolume)(uint16_t, uint8_t);
+  uint32_t  (*SetMute)(uint16_t, uint32_t);
+  uint32_t  (*SetOutputMode)(uint16_t, uint8_t);
+  uint32_t  (*Reset)(uint16_t);
+}AUDIO_DrvTypeDef;
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __AUDIO_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Drivers/BSP/Components/Common/camera.h b/Drivers/BSP/Components/Common/camera.h
new file mode 100644
index 0000000..7709084
--- /dev/null
+++ b/Drivers/BSP/Components/Common/camera.h
@@ -0,0 +1,141 @@
+/**
+  ******************************************************************************
+  * @file    camera.h
+  * @author  MCD Application Team
+  * @version V4.0.1
+  * @date    21-July-2015
+  * @brief   This header file contains the common defines and functions prototypes
+  *          for the camera driver.   
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */ 
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __CAMERA_H
+#define __CAMERA_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+
+/* Includes ------------------------------------------------------------------*/
+#include <stdint.h>
+
+/** @addtogroup BSP
+  * @{
+  */
+
+/** @addtogroup Components
+  * @{
+  */
+    
+/** @addtogroup CAMERA
+  * @{
+  */
+
+
+/** @defgroup CAMERA_Exported_Types
+  * @{
+  */ 
+
+/** @defgroup CAMERA_Driver_structure  Camera Driver structure
+  * @{
+  */
+typedef struct
+{
+  void     (*Init)(uint16_t, uint32_t);
+  uint16_t (*ReadID)(uint16_t);  
+  void     (*Config)(uint16_t, uint32_t, uint32_t, uint32_t);
+}CAMERA_DrvTypeDef;
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup CAMERA_Exported_Constants
+  * @{
+  */
+#define CAMERA_R160x120                 0x00   /* QQVGA Resolution                     */
+#define CAMERA_R320x240                 0x01   /* QVGA Resolution                      */
+#define CAMERA_R480x272                 0x02   /* 480x272 Resolution                   */
+#define CAMERA_R640x480                 0x03   /* VGA Resolution                       */  
+
+#define CAMERA_CONTRAST_BRIGHTNESS      0x00   /* Camera contrast brightness features  */
+#define CAMERA_BLACK_WHITE              0x01   /* Camera black white feature           */
+#define CAMERA_COLOR_EFFECT             0x03   /* Camera color effect feature          */
+
+#define CAMERA_BRIGHTNESS_LEVEL0        0x00   /* Brightness level -2         */
+#define CAMERA_BRIGHTNESS_LEVEL1        0x01   /* Brightness level -1         */
+#define CAMERA_BRIGHTNESS_LEVEL2        0x02   /* Brightness level 0          */
+#define CAMERA_BRIGHTNESS_LEVEL3        0x03   /* Brightness level +1         */
+#define CAMERA_BRIGHTNESS_LEVEL4        0x04   /* Brightness level +2         */
+
+#define CAMERA_CONTRAST_LEVEL0          0x05   /* Contrast level -2           */
+#define CAMERA_CONTRAST_LEVEL1          0x06   /* Contrast level -1           */
+#define CAMERA_CONTRAST_LEVEL2          0x07   /* Contrast level  0           */
+#define CAMERA_CONTRAST_LEVEL3          0x08   /* Contrast level +1           */
+#define CAMERA_CONTRAST_LEVEL4          0x09   /* Contrast level +2           */    
+    
+#define CAMERA_BLACK_WHITE_BW           0x00   /* Black and white effect      */
+#define CAMERA_BLACK_WHITE_NEGATIVE     0x01   /* Negative effect             */
+#define CAMERA_BLACK_WHITE_BW_NEGATIVE  0x02   /* BW and Negative effect      */
+#define CAMERA_BLACK_WHITE_NORMAL       0x03   /* Normal effect               */
+                                        
+#define CAMERA_COLOR_EFFECT_NONE        0x00   /* No effects                  */
+#define CAMERA_COLOR_EFFECT_BLUE        0x01   /* Blue effect                 */
+#define CAMERA_COLOR_EFFECT_GREEN       0x02   /* Green effect                */
+#define CAMERA_COLOR_EFFECT_RED         0x03   /* Red effect                  */
+#define CAMERA_COLOR_EFFECT_ANTIQUE     0x04   /* Antique effect              */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CAMERA_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Drivers/BSP/Components/Common/epd.h b/Drivers/BSP/Components/Common/epd.h
new file mode 100644
index 0000000..9c91347
--- /dev/null
+++ b/Drivers/BSP/Components/Common/epd.h
@@ -0,0 +1,115 @@
+/**
+  ******************************************************************************
+  * @file    epd.h
+  * @author  MCD Application Team
+  * @version V4.0.1
+  * @date    21-July-2015
+  * @brief   This file contains all the functions prototypes for the 
+  *          EPD (E Paper Display) driver.   
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */ 
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __EPD_H
+#define __EPD_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include <stdint.h>
+
+/** @addtogroup BSP
+  * @{
+  */
+
+/** @addtogroup Components
+  * @{
+  */
+  
+/** @addtogroup Common
+  * @{
+  */
+
+/** @addtogroup EPD
+  * @{
+  */
+
+/** @defgroup EPD_Exported_Types
+  * @{
+  */
+
+/** @defgroup EPD_Driver_structure  E Paper Display Driver structure
+  * @{
+  */
+typedef struct
+{
+  void     (*Init)(void);
+  void     (*WritePixel)(uint8_t);
+
+  /* Optimized operation */
+  void     (*SetDisplayWindow)(uint16_t, uint16_t, uint16_t, uint16_t);
+  void     (*RefreshDisplay)(void);
+  void     (*CloseChargePump)(void);
+
+  uint16_t (*GetEpdPixelWidth)(void);
+  uint16_t (*GetEpdPixelHeight)(void);
+  void     (*DrawImage)(uint16_t, uint16_t, uint16_t, uint16_t, uint8_t*);
+}
+EPD_DrvTypeDef;
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* EPD_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Drivers/BSP/Components/Common/gyro.h b/Drivers/BSP/Components/Common/gyro.h
new file mode 100644
index 0000000..424033b
--- /dev/null
+++ b/Drivers/BSP/Components/Common/gyro.h
@@ -0,0 +1,145 @@
+/**
+  ******************************************************************************
+  * @file    gyro.h
+  * @author  MCD Application Team
+  * @version V4.0.1
+  * @date    21-July-2015
+  * @brief   This header file contains the functions prototypes for the gyroscope driver.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+  
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __GYRO_H
+#define __GYRO_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include <stdint.h>
+
+/** @addtogroup BSP
+  * @{
+  */
+
+/** @addtogroup Components
+  * @{
+  */
+    
+/** @addtogroup GYRO
+  * @{
+  */
+
+/** @defgroup GYRO_Exported_Types
+  * @{
+  */
+
+/** @defgroup GYRO_Driver_structure  Gyroscope Driver structure
+  * @{
+  */
+typedef struct
+{  
+  void       (*Init)(uint16_t);
+  void       (*DeInit)(void); 
+  uint8_t    (*ReadID)(void);
+  void       (*Reset)(void);
+  void       (*LowPower)(uint16_t);   
+  void       (*ConfigIT)(uint16_t); 
+  void       (*EnableIT)(uint8_t);
+  void       (*DisableIT)(uint8_t);  
+  uint8_t    (*ITStatus)(uint16_t, uint16_t);   
+  void       (*ClearIT)(uint16_t, uint16_t); 
+  void       (*FilterConfig)(uint8_t);  
+  void       (*FilterCmd)(uint8_t);  
+  void       (*GetXYZ)(float *);
+}GYRO_DrvTypeDef;
+/**
+  * @}
+  */
+
+/** @defgroup GYRO_Config_structure  Gyroscope Configuration structure
+  * @{
+  */
+
+typedef struct
+{
+  uint8_t Power_Mode;                         /* Power-down/Sleep/Normal Mode */
+  uint8_t Output_DataRate;                    /* OUT data rate */
+  uint8_t Axes_Enable;                        /* Axes enable */
+  uint8_t Band_Width;                         /* Bandwidth selection */
+  uint8_t BlockData_Update;                   /* Block Data Update */
+  uint8_t Endianness;                         /* Endian Data selection */
+  uint8_t Full_Scale;                         /* Full Scale selection */
+}GYRO_InitTypeDef;
+
+/* GYRO High Pass Filter struct */
+typedef struct
+{
+  uint8_t HighPassFilter_Mode_Selection;      /* Internal filter mode */
+  uint8_t HighPassFilter_CutOff_Frequency;    /* High pass filter cut-off frequency */
+}GYRO_FilterConfigTypeDef;
+
+/*GYRO Interrupt struct */
+typedef struct
+{
+  uint8_t Latch_Request;                      /* Latch interrupt request into CLICK_SRC register */
+  uint8_t Interrupt_Axes;                     /* X, Y, Z Axes Interrupts */ 
+  uint8_t Interrupt_ActiveEdge;               /* Interrupt Active edge */
+}GYRO_InterruptConfigTypeDef;  
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __GYRO_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Drivers/BSP/Components/Common/idd.h b/Drivers/BSP/Components/Common/idd.h
new file mode 100644
index 0000000..410f8c9
--- /dev/null
+++ b/Drivers/BSP/Components/Common/idd.h
@@ -0,0 +1,168 @@
+/**
+  ******************************************************************************
+  * @file    idd.h
+  * @author  MCD Application Team
+  * @version V4.0.1
+  * @date    21-July-2015
+  * @brief   This file contains all the functions prototypes for the IDD driver.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */ 
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __IDD_H
+#define __IDD_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include <stdint.h>
+
+/** @addtogroup BSP
+  * @{
+  */
+
+/** @addtogroup Components
+  * @{
+  */
+    
+/** @addtogroup IDD
+  * @{
+  */
+
+/** @defgroup IDD_Exported_Types IDD Exported Types
+  * @{
+  */
+
+/** @defgroup IDD_Config_structure  IDD Configuration structure
+  * @{
+  */
+typedef struct
+{
+  uint16_t AmpliGain;       /*!< Specifies ampli gain value
+                                 */
+  uint16_t VddMin;          /*!< Specifies minimum MCU VDD can reach to protect MCU from reset
+                                  */
+  uint16_t Shunt0Value;     /*!< Specifies value of Shunt 0 if existing
+                                 */
+  uint16_t Shunt1Value;     /*!< Specifies value of Shunt 1 if existing
+                                 */
+  uint16_t Shunt2Value;     /*!< Specifies value of Shunt 2 if existing
+                                 */
+  uint16_t Shunt3Value;     /*!< Specifies value of Shunt 3 if existing
+                                 */
+  uint16_t Shunt4Value;     /*!< Specifies value of Shunt 4 if existing
+                                  */
+  uint16_t Shunt0StabDelay; /*!< Specifies delay of Shunt 0 stabilization if existing
+                                  */
+  uint16_t Shunt1StabDelay; /*!< Specifies delay of Shunt 1 stabilization if existing
+                                  */
+  uint16_t Shunt2StabDelay; /*!< Specifies delay of Shunt 2 stabilization if existing
+                                  */
+  uint16_t Shunt3StabDelay; /*!< Specifies delay of Shunt 3 stabilization if existing
+                                  */
+  uint16_t Shunt4StabDelay; /*!< Specifies delay of Shunt 4 stabilization if existing
+                                  */
+  uint8_t ShuntNbOnBoard;   /*!< Specifies number of shunts that are present on board
+                                 This parameter can be a value of @ref IDD_shunt_number */
+  uint8_t ShuntNbUsed;      /*!< Specifies number of shunts used for measurement
+                                 This parameter can be a value of @ref IDD_shunt_number */
+  uint8_t VrefMeasurement;  /*!< Specifies if Vref is automatically measured before each Idd measurement
+                                 This parameter can be a value of @ref IDD_Vref_Measurement */
+  uint8_t Calibration;      /*!< Specifies if calibration is done before each Idd measurement
+                                  */
+  uint8_t PreDelayUnit;     /*!< Specifies Pre delay unit 
+                                 This parameter can be a value of @ref IDD_PreDelay */
+  uint8_t PreDelayValue;    /*!< Specifies Pre delay value in selected unit
+                                  */
+  uint8_t MeasureNb;        /*!< Specifies number of Measure to be performed 
+                                 This parameter can be a value between 1 and 256 */
+  uint8_t DeltaDelayUnit;   /*!< Specifies Delta delay unit
+                                  This parameter can be a value of @ref IDD_DeltaDelay */
+  uint8_t DeltaDelayValue;  /*!< Specifies Delta delay between 2 measures
+                                  value can be between 1 and 128 */
+}IDD_ConfigTypeDef;
+/**
+  * @}
+  */
+
+/** @defgroup IDD_Driver_structure  IDD Driver structure
+  * @{
+  */
+typedef struct
+{
+  void       (*Init)(uint16_t);
+  void       (*DeInit)(uint16_t);
+  uint16_t   (*ReadID)(uint16_t);
+  void       (*Reset)(uint16_t);
+  void       (*LowPower)(uint16_t);
+  void       (*WakeUp)(uint16_t);
+  void       (*Start)(uint16_t);
+  void       (*Config)(uint16_t,IDD_ConfigTypeDef);
+  void       (*GetValue)(uint16_t, uint32_t *);
+  void       (*EnableIT)(uint16_t);
+  void       (*ClearIT)(uint16_t);
+  uint8_t    (*GetITStatus)(uint16_t);
+  void       (*DisableIT)(uint16_t);
+  void       (*ErrorEnableIT)(uint16_t);
+  void       (*ErrorClearIT)(uint16_t);
+  uint8_t    (*ErrorGetITStatus)(uint16_t);
+  void       (*ErrorDisableIT)(uint16_t);
+  uint8_t    (*ErrorGetSrc)(uint16_t);
+  uint8_t    (*ErrorGetCode)(uint16_t);
+}IDD_DrvTypeDef;
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __IDD_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Drivers/BSP/Components/Common/io.h b/Drivers/BSP/Components/Common/io.h
new file mode 100644
index 0000000..da6826c
--- /dev/null
+++ b/Drivers/BSP/Components/Common/io.h
@@ -0,0 +1,150 @@
+/**
+  ******************************************************************************
+  * @file    io.h
+  * @author  MCD Application Team
+  * @version V4.0.1
+  * @date    21-July-2015
+  * @brief   This file contains all the functions prototypes for the IO driver.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */ 
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __IO_H
+#define __IO_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include <stdint.h>
+
+/** @addtogroup BSP
+  * @{
+  */
+
+/** @addtogroup Components
+  * @{
+  */
+    
+/** @addtogroup IO
+  * @{
+  */
+
+/** @defgroup IO_Exported_Types
+  * @{
+  */
+
+/**
+  * @brief  IO Bit SET and Bit RESET enumeration
+  */
+typedef enum
+{
+  IO_PIN_RESET = 0,
+  IO_PIN_SET
+}IO_PinState;
+
+typedef enum
+{
+   IO_MODE_INPUT = 0,   /* input floating */
+   IO_MODE_OUTPUT,      /* output Push Pull */
+   IO_MODE_IT_RISING_EDGE,   /* float input - irq detect on rising edge */
+   IO_MODE_IT_FALLING_EDGE,  /* float input - irq detect on falling edge */
+   IO_MODE_IT_LOW_LEVEL,     /* float input - irq detect on low level */
+   IO_MODE_IT_HIGH_LEVEL,    /* float input - irq detect on high level */
+   /* following modes only available on MFX*/
+   IO_MODE_ANALOG,           /* analog mode */
+   IO_MODE_OFF,              /* when pin isn't used*/
+   IO_MODE_INPUT_PU,         /* input with internal pull up resistor */
+   IO_MODE_INPUT_PD,         /* input with internal pull down resistor */
+   IO_MODE_OUTPUT_OD,          /* Open Drain output without internal resistor */
+   IO_MODE_OUTPUT_OD_PU,       /* Open Drain output with  internal pullup resistor */
+   IO_MODE_OUTPUT_OD_PD,       /* Open Drain output with  internal pulldown resistor */
+   IO_MODE_OUTPUT_PP,          /* PushPull output without internal resistor */
+   IO_MODE_OUTPUT_PP_PU,       /* PushPull output with  internal pullup resistor */
+   IO_MODE_OUTPUT_PP_PD,       /* PushPull output with  internal pulldown resistor */
+   IO_MODE_IT_RISING_EDGE_PU,   /* push up resistor input - irq on rising edge  */
+   IO_MODE_IT_RISING_EDGE_PD,   /* push dw resistor input - irq on rising edge  */
+   IO_MODE_IT_FALLING_EDGE_PU,  /* push up resistor input - irq on falling edge */
+   IO_MODE_IT_FALLING_EDGE_PD,  /* push dw resistor input - irq on falling edge */
+   IO_MODE_IT_LOW_LEVEL_PU,     /* push up resistor input - irq detect on low level */
+   IO_MODE_IT_LOW_LEVEL_PD,     /* push dw resistor input - irq detect on low level */
+   IO_MODE_IT_HIGH_LEVEL_PU,    /* push up resistor input - irq detect on high level */
+   IO_MODE_IT_HIGH_LEVEL_PD,    /* push dw resistor input - irq detect on high level */
+
+}IO_ModeTypedef;
+
+/** @defgroup IO_Driver_structure  IO Driver structure
+  * @{
+  */
+typedef struct
+{  
+  void       (*Init)(uint16_t);
+  uint16_t   (*ReadID)(uint16_t);
+  void       (*Reset)(uint16_t);
+  
+  void       (*Start)(uint16_t, uint32_t);
+  uint8_t    (*Config)(uint16_t, uint32_t, IO_ModeTypedef);
+  void       (*WritePin)(uint16_t, uint32_t, uint8_t);
+  uint32_t   (*ReadPin)(uint16_t, uint32_t);
+  
+  void       (*EnableIT)(uint16_t);
+  void       (*DisableIT)(uint16_t);
+  uint32_t    (*ITStatus)(uint16_t, uint32_t);
+  void       (*ClearIT)(uint16_t, uint32_t);
+    
+}IO_DrvTypeDef;
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __IO_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Drivers/BSP/Components/Common/lcd.h b/Drivers/BSP/Components/Common/lcd.h
new file mode 100644
index 0000000..12a7fa5
--- /dev/null
+++ b/Drivers/BSP/Components/Common/lcd.h
@@ -0,0 +1,114 @@
+/**
+  ******************************************************************************
+  * @file    lcd.h
+  * @author  MCD Application Team
+  * @version V4.0.1
+  * @date    21-July-2015
+  * @brief   This file contains all the functions prototypes for the LCD driver.   
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */ 
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __LCD_H
+#define __LCD_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+
+/* Includes ------------------------------------------------------------------*/
+#include <stdint.h>
+   
+/** @addtogroup BSP
+  * @{
+  */
+
+/** @addtogroup Components
+  * @{
+  */
+
+/** @addtogroup LCD
+  * @{
+  */
+ 
+/** @defgroup LCD_Exported_Types
+  * @{
+  */
+
+/** @defgroup LCD_Driver_structure  LCD Driver structure
+  * @{
+  */
+typedef struct
+{
+  void     (*Init)(void);
+  uint16_t (*ReadID)(void);
+  void     (*DisplayOn)(void);
+  void     (*DisplayOff)(void);
+  void     (*SetCursor)(uint16_t, uint16_t);
+  void     (*WritePixel)(uint16_t, uint16_t, uint16_t);
+  uint16_t (*ReadPixel)(uint16_t, uint16_t);
+  
+   /* Optimized operation */
+  void     (*SetDisplayWindow)(uint16_t, uint16_t, uint16_t, uint16_t);
+  void     (*DrawHLine)(uint16_t, uint16_t, uint16_t, uint16_t);
+  void     (*DrawVLine)(uint16_t, uint16_t, uint16_t, uint16_t);
+  
+  uint16_t (*GetLcdPixelWidth)(void);
+  uint16_t (*GetLcdPixelHeight)(void);
+  void     (*DrawBitmap)(uint16_t, uint16_t, uint8_t*);
+  void     (*DrawRGBImage)(uint16_t, uint16_t, uint16_t, uint16_t, uint8_t*);
+}LCD_DrvTypeDef;    
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __LCD_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Drivers/BSP/Components/Common/magneto.h b/Drivers/BSP/Components/Common/magneto.h
new file mode 100644
index 0000000..799fc87
--- /dev/null
+++ b/Drivers/BSP/Components/Common/magneto.h
@@ -0,0 +1,125 @@
+/**
+  ******************************************************************************
+  * @file    magneto.h
+  * @author  MCD Application Team
+  * @version V4.0.1
+  * @date    21-July-2015
+  * @brief   This header file contains the functions prototypes for the MAGNETO driver.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __MAGNETO_H
+#define __MAGNETO_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include <stdint.h>
+
+/** @addtogroup BSP
+  * @{
+  */
+
+/** @addtogroup Components
+  * @{
+  */
+    
+/** @addtogroup MAGNETO
+  * @{
+  */
+
+/** @defgroup MAGNETO_Exported_Types
+  * @{
+  */ 
+
+/** @defgroup MAGNETO_Config_structure  Magnetometer Configuration structure
+  * @{
+  */
+typedef struct
+{
+  uint8_t Register1;
+  uint8_t Register2;
+  uint8_t Register3;
+  uint8_t Register4;
+  uint8_t Register5;
+}MAGNETO_InitTypeDef;
+/**
+  * @}
+  */
+
+/** @defgroup MAGNETO_Driver_structure  Magnetometer Driver structure
+  * @{
+  */
+typedef struct
+{  
+  void      (*Init)(MAGNETO_InitTypeDef);
+  void      (*DeInit)(void); 
+  uint8_t   (*ReadID)(void);
+  void      (*Reset)(void);
+  void      (*LowPower)(void);
+  void      (*ConfigIT)(void);
+  void      (*EnableIT)(uint8_t);
+  void      (*DisableIT)(uint8_t);
+  uint8_t   (*ITStatus)(uint16_t);
+  void      (*ClearIT)(void);
+  void      (*FilterConfig)(uint8_t);
+  void      (*FilterCmd)(uint8_t);
+  void      (*GetXYZ)(int16_t *);
+}MAGNETO_DrvTypeDef;
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __MAGNETO_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Drivers/BSP/Components/Common/ts.h b/Drivers/BSP/Components/Common/ts.h
new file mode 100644
index 0000000..bef7119
--- /dev/null
+++ b/Drivers/BSP/Components/Common/ts.h
@@ -0,0 +1,107 @@
+/**
+  ******************************************************************************
+  * @file    ts.h
+  * @author  MCD Application Team
+  * @version V4.0.1
+  * @date    21-July-2015
+  * @brief   This file contains all the functions prototypes for the Touch Screen driver.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __TS_H
+#define __TS_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include <stdint.h> 
+
+/** @addtogroup BSP
+  * @{
+  */
+
+/** @addtogroup Components
+  * @{
+  */
+    
+/** @addtogroup TS
+  * @{
+  */
+
+/** @defgroup TS_Exported_Types
+  * @{
+  */
+
+/** @defgroup TS_Driver_structure  Touch Sensor Driver structure
+  * @{
+  */
+typedef struct
+{  
+  void       (*Init)(uint16_t);
+  uint16_t   (*ReadID)(uint16_t);
+  void       (*Reset)(uint16_t);
+  void       (*Start)(uint16_t);
+  uint8_t    (*DetectTouch)(uint16_t);
+  void       (*GetXY)(uint16_t, uint16_t*, uint16_t*);
+  void       (*EnableIT)(uint16_t);
+  void       (*ClearIT)(uint16_t);
+  uint8_t    (*GetITStatus)(uint16_t);
+  void       (*DisableIT)(uint16_t);
+}TS_DrvTypeDef;
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __TS_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Drivers/BSP/Components/Common/tsensor.h b/Drivers/BSP/Components/Common/tsensor.h
new file mode 100644
index 0000000..ca0e544
--- /dev/null
+++ b/Drivers/BSP/Components/Common/tsensor.h
@@ -0,0 +1,118 @@
+/**
+  ******************************************************************************
+  * @file    tsensor.h
+  * @author  MCD Application Team
+  * @version V4.0.1
+  * @date    21-July-2015
+  * @brief   This header file contains the functions prototypes for the
+  *          Temperature Sensor driver. 
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __TSENSOR_H
+#define __TSENSOR_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include <stdint.h>
+
+/** @addtogroup BSP
+  * @{
+  */
+
+/** @addtogroup Components
+  * @{
+  */
+    
+/** @addtogroup TSENSOR
+  * @{
+  */
+
+/** @defgroup TSENSOR_Exported_Types
+  * @{
+  */ 
+
+/** @defgroup TSENSOR_Config_structure  Temperature Sensor Configuration structure
+  * @{
+  */
+typedef struct
+{
+  uint8_t AlertMode;            /* Alert Mode Temperature out of range*/
+  uint8_t ConversionMode;       /* Continuous/One Shot Mode */
+  uint8_t ConversionResolution; /* Temperature Resolution */
+  uint8_t ConversionRate;       /* Number of measure per second */
+  uint8_t TemperatureLimitHigh; /* High Temperature Limit Range */
+  uint8_t TemperatureLimitLow;  /* Low Temperature Limit Range */
+}TSENSOR_InitTypeDef;
+/**
+  * @}
+  */
+
+/** @defgroup TSENSOR_Driver_structure  Temperature Sensor Driver structure
+  * @{
+  */
+typedef struct
+{  
+  void       (*Init)(uint16_t, TSENSOR_InitTypeDef *);
+  uint8_t    (*IsReady)(uint16_t, uint32_t);
+  uint8_t    (*ReadStatus)(uint16_t);
+  uint16_t   (*ReadTemp)(uint16_t); 
+}TSENSOR_DrvTypeDef;
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __TSENSOR_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Drivers/BSP/Components/cs43l22/Release_Notes.html b/Drivers/BSP/Components/cs43l22/Release_Notes.html
new file mode 100644
index 0000000..559e8f1
--- /dev/null
+++ b/Drivers/BSP/Components/cs43l22/Release_Notes.html
@@ -0,0 +1,743 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html xmlns:v="urn:schemas-microsoft-com:vml" xmlns:o="urn:schemas-microsoft-com:office:office" xmlns:w="urn:schemas-microsoft-com:office:word" xmlns="http://www.w3.org/TR/REC-html40"><head>
+
+
+
+
+
+
+
+
+
+
+  
+  <meta http-equiv="Content-Type" content="text/html; charset=ISO-8859-1">
+
+  
+  <link rel="File-List" href="Library_files/filelist.xml">
+
+  
+  <link rel="Edit-Time-Data" href="Library_files/editdata.mso"><!--[if !mso]> <style> v\:* {behavior:url(#default#VML);} o\:* {behavior:url(#default#VML);} w\:* {behavior:url(#default#VML);} .shape {behavior:url(#default#VML);} </style> <![endif]--><title>Release Notes for CS43L22 Component Driver</title><!--[if gte mso 9]><xml> <o:DocumentProperties> <o:Author>STMicroelectronics</o:Author> <o:LastAuthor>STMicroelectronics</o:LastAuthor> <o:Revision>37</o:Revision> <o:TotalTime>136</o:TotalTime> <o:Created>2009-02-27T19:26:00Z</o:Created> <o:LastSaved>2009-03-01T17:56:00Z</o:LastSaved> <o:Pages>1</o:Pages> <o:Words>522</o:Words> <o:Characters>2977</o:Characters> <o:Company>STMicroelectronics</o:Company> <o:Lines>24</o:Lines> <o:Paragraphs>6</o:Paragraphs> <o:CharactersWithSpaces>3493</o:CharactersWithSpaces> <o:Version>11.6568</o:Version> </o:DocumentProperties> </xml><![endif]--><!--[if gte mso 9]><xml> <w:WordDocument> <w:Zoom>110</w:Zoom> <w:ValidateAgainstSchemas/> <w:SaveIfXMLInvalid>false</w:SaveIfXMLInvalid> <w:IgnoreMixedContent>false</w:IgnoreMixedContent> <w:AlwaysShowPlaceholderText>false</w:AlwaysShowPlaceholderText> <w:BrowserLevel>MicrosoftInternetExplorer4</w:BrowserLevel> </w:WordDocument> </xml><![endif]--><!--[if gte mso 9]><xml> <w:LatentStyles DefLockedState="false" LatentStyleCount="156"> </w:LatentStyles> </xml><![endif]-->
+
+
+  
+
+  
+
+  
+  <style>
+<!--
+/* Style Definitions */
+p.MsoNormal, li.MsoNormal, div.MsoNormal
+{mso-style-parent:"";
+margin:0in;
+margin-bottom:.0001pt;
+mso-pagination:widow-orphan;
+font-size:12.0pt;
+font-family:"Times New Roman";
+mso-fareast-font-family:"Times New Roman";}
+h2
+{mso-style-next:Normal;
+margin-top:12.0pt;
+margin-right:0in;
+margin-bottom:3.0pt;
+margin-left:0in;
+mso-pagination:widow-orphan;
+page-break-after:avoid;
+mso-outline-level:2;
+font-size:14.0pt;
+font-family:Arial;
+font-weight:bold;
+font-style:italic;}
+a:link, span.MsoHyperlink
+{color:blue;
+text-decoration:underline;
+text-underline:single;}
+a:visited, span.MsoHyperlinkFollowed
+{color:blue;
+text-decoration:underline;
+text-underline:single;}
+p
+{mso-margin-top-alt:auto;
+margin-right:0in;
+mso-margin-bottom-alt:auto;
+margin-left:0in;
+mso-pagination:widow-orphan;
+font-size:12.0pt;
+font-family:"Times New Roman";
+mso-fareast-font-family:"Times New Roman";}
+@page Section1
+{size:8.5in 11.0in;
+margin:1.0in 1.25in 1.0in 1.25in;
+mso-header-margin:.5in;
+mso-footer-margin:.5in;
+mso-paper-source:0;}
+div.Section1
+{page:Section1;}
+-->
+  </style><!--[if gte mso 10]> <style> /* Style Definitions */ table.MsoNormalTable {mso-style-name:"Table Normal"; mso-tstyle-rowband-size:0; mso-tstyle-colband-size:0; mso-style-noshow:yes; mso-style-parent:""; mso-padding-alt:0in 5.4pt 0in 5.4pt; mso-para-margin:0in; mso-para-margin-bottom:.0001pt; mso-pagination:widow-orphan; font-size:10.0pt; font-family:"Times New Roman"; mso-ansi-language:#0400; mso-fareast-language:#0400; mso-bidi-language:#0400;} </style> <![endif]--><!--[if gte mso 9]><xml> <o:shapedefaults v:ext="edit" spidmax="5122"/> </xml><![endif]--><!--[if gte mso 9]><xml> <o:shapelayout v:ext="edit"> <o:idmap v:ext="edit" data="1"/> </o:shapelayout></xml><![endif]-->
+  <meta content="MCD Application Team" name="author"></head>
+<body link="blue" vlink="blue">
+<div class="Section1">
+<p class="MsoNormal"><span style="font-family: Arial;"><o:p><br>
+</o:p></span></p>
+<div align="center">
+<table class="MsoNormalTable" style="width: 675pt;" border="0" cellpadding="0" cellspacing="0" width="900">
+  <tbody>
+    <tr>
+      <td style="padding: 0cm;" valign="top">
+      <table class="MsoNormalTable" style="width: 675pt;" border="0" cellpadding="0" cellspacing="0" width="900">
+        <tbody>
+          <tr>
+            <td style="vertical-align: top;">
+            <p class="MsoNormal"><span style="font-size: 8pt; font-family: Arial; color: blue;"><a href="../../../../Release_Notes.html">Back to Release page</a><o:p></o:p></span></p>
+            </td>
+          </tr>
+          <tr style="">
+            <td style="padding: 1.5pt;">
+            <h1 style="margin-bottom: 18pt; text-align: center;" align="center"><span style="font-size: 20pt; font-family: Verdana; color: rgb(51, 102, 255);">Release
+Notes for CS43L22 Component Driver</span><span style="font-size: 20pt; font-family: Verdana;"><o:p></o:p></span></h1>
+            <p class="MsoNormal" style="text-align: center;" align="center"><span style="font-size: 10pt; font-family: Arial; color: black;">Copyright
+2014 STMicroelectronics</span><span style="color: black;"><u1:p></u1:p><o:p></o:p></span></p>
+            <p class="MsoNormal" style="text-align: center;" align="center"><span style="font-size: 10pt; font-family: Arial; color: black;"><img alt="" id="_x0000_i1025" src="../../../../_htmresc/st_logo.png" style="border: 0px solid ; width: 86px; height: 65px;"></span><span style="font-size: 10pt;"><o:p></o:p></span></p>
+            </td>
+          </tr>
+        </tbody>
+      </table>
+      <p class="MsoNormal"><span style="font-family: Arial; display: none;"><o:p>&nbsp;</o:p></span></p>
+      <table class="MsoNormalTable" style="width: 675pt;" border="0" cellpadding="0" width="900">
+        <tbody>
+          <tr style="">
+            <td style="padding: 0cm;" valign="top">
+            <span style="font-family: &quot;Times New Roman&quot;;">
+            </span>
+            <h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial;"><a name="History"></a><span style="font-size: 12pt; color: white;">Update History</span></h2>
+            <h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 206px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V2.0.3 / 05-October-2017 <o:p></o:p></span></h3>
+
+
+
+
+
+
+
+
+
+
+
+
+            
+            
+            
+            
+            
+            
+            
+            <p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
+Changes<o:p></o:p></span></u></b></p>
+
+
+
+
+
+
+
+
+
+
+            <span style="font-size: 10pt; font-family: Verdana;"></span>
+
+
+            
+            <span style="font-size: 10pt; font-family: Verdana;"></span>
+
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+            
+            <span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;"></span>
+
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+
+
+
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+            
+            
+            <span style="font-size: 10pt; font-family: Verdana;"></span>
+
+
+
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+
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+            
+            
+            <span style="font-size: 10pt; font-family: Verdana;"></span>
+
+
+
+
+
+            
+            
+            <span style="font-size: 10pt; font-family: Verdana;"></span>
+
+
+
+
+            
+            
+            <span style="font-size: 10pt; font-family: Verdana;"></span>
+            
+            
+            
+
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+            
+            
+            
+            <ul style="list-style-type: square;"><li><span style="font-size: 10pt; font-family: Verdana;">cs43l22.c/.h:&nbsp;</span></li><ul><li><span style="font-size: 10pt; font-family: Verdana;">Update VOLUME_CONVERT macro to return 255 if the input volume is greater than 100.</span></li><li><span style="font-size: 10pt; font-family: Verdana;">Update cs43l22_SetVolume API to check on convertedvol instead of Volume</span></li></ul></ul><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 206px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V2.0.2 / 02-October-2015 <o:p></o:p></span></h3>
+
+
+
+
+
+
+
+
+
+
+
+
+            
+            
+            
+            
+            
+            
+            
+            <p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
+Changes<o:p></o:p></span></u></b></p>
+
+
+
+
+
+
+
+
+
+
+            <span style="font-size: 10pt; font-family: Verdana;"></span>
+
+
+            
+            <span style="font-size: 10pt; font-family: Verdana;"></span>
+
+
+            
+            <span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;"></span>
+
+
+
+
+
+
+            
+            
+            <span style="font-size: 10pt; font-family: Verdana;"></span>
+
+
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+
+
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+            
+            
+            <span style="font-size: 10pt; font-family: Verdana;"></span>
+
+
+
+
+
+            
+            
+            <span style="font-size: 10pt; font-family: Verdana;"></span>
+
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+            
+            
+            <span style="font-size: 10pt; font-family: Verdana;"></span>
+            
+            
+            
+
+
+
+
+            
+            
+            
+            <ul style="list-style-type: square;"><li><span style="font-size: 10pt; font-family: Verdana;">cs43l22.c/.h:&nbsp;</span></li><ul><li><span style="font-size: 10pt; font-family: Verdana;">Move VOLUME_CONVERT macro from cs43l22.h to cs43l22.c as internally used to convert volume.</span></li><li><span style="font-size: 10pt; font-family: Verdana;">Add literals instead of magic number for cs34l22 registers.</span></li></ul></ul><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 220px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V2.0.1 / 16-September-2015 <o:p></o:p></span></h3>
+
+
+
+
+
+
+
+
+
+
+
+
+            
+            
+            
+            
+            
+            
+            
+            <p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
+Changes<o:p></o:p></span></u></b></p>
+
+
+
+
+
+
+
+
+
+
+            <span style="font-size: 10pt; font-family: Verdana;"></span>
+
+
+            
+            <span style="font-size: 10pt; font-family: Verdana;"></span>
+
+
+            
+            <span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;"></span>
+
+
+
+
+
+
+            
+            
+            <span style="font-size: 10pt; font-family: Verdana;"></span>
+
+
+
+
+
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+            
+            
+            <span style="font-size: 10pt; font-family: Verdana;"></span>
+
+
+
+
+
+            
+            
+            <span style="font-size: 10pt; font-family: Verdana;"></span>
+
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+            
+            
+            <span style="font-size: 10pt; font-family: Verdana;"></span>
+            
+            
+            
+
+
+
+
+            
+            
+            
+            <ul style="list-style-type: square;"><li><span style="font-size: 10pt; font-family: Verdana;">cs43l22.c:&nbsp;</span></li><ul><li><span style="font-size: 10pt; font-family: Verdana;">Enable the digital soft ramp to avoid clac noise.</span></li><li><span style="font-size: 10pt; font-family: Verdana;">Improve mute/unmute by muting/unmuting also the DAC inputs.&nbsp;</span></li></ul></ul><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 210px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V2.0.0 / 24-June-2015 <o:p></o:p></span></h3>
+
+
+
+
+
+
+
+
+
+
+
+
+            
+            
+            
+            
+            
+            
+            
+            <p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
+Changes<o:p></o:p></span></u></b></p>
+
+
+
+
+
+
+
+
+
+
+            <span style="font-size: 10pt; font-family: Verdana;"></span>
+
+
+            
+            <span style="font-size: 10pt; font-family: Verdana;"></span>
+
+
+            
+            <span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;"></span>
+
+
+
+
+
+
+            
+            
+            <span style="font-size: 10pt; font-family: Verdana;"></span>
+
+
+
+
+
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+            
+            
+            <span style="font-size: 10pt; font-family: Verdana;"></span>
+
+
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+
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+            
+            
+            <span style="font-size: 10pt; font-family: Verdana;"></span>
+
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+            
+            
+            <span style="font-size: 10pt; font-family: Verdana;"></span>
+            
+            
+            
+
+
+
+
+            
+            
+            
+            <ul style="list-style-type: square;"><li><span style="font-size: 10pt; font-family: Verdana;">cs43l22.h/.c:&nbsp;</span></li><ul><li><span style="font-size: 10pt; font-family: Verdana;">Add codec de-initialization function: cs43l22_DeInit()</span></li><li><span style="font-size: 10pt; font-family: Verdana;">Add Audio IO </span><span style="font-size: 10pt; font-family: Verdana;">de-initialization function prototype: AUDIO_IO_DeInit()</span></li><li><span style="font-family: Verdana; font-size: 10pt;"><span style="font-weight: bold;">NOTE:</span> This release must be used with BSP Common 
+driver V4.0.0 or later</span></li></ul></ul><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 210px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.1.0 / 10-February-2015 <o:p></o:p></span></h3>
+
+
+
+
+
+
+
+
+
+
+
+
+            
+            
+            
+            
+            
+            
+            
+            <p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
+Changes<o:p></o:p></span></u></b></p>
+
+
+
+
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+
+
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+
+            <span style="font-size: 10pt; font-family: Verdana;"></span>
+
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+            
+            <span style="font-size: 10pt; font-family: Verdana;"></span>
+
+
+            
+            <span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;"></span>
+
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+            
+            
+            <span style="font-size: 10pt; font-family: Verdana;"></span>
+
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+            <span style="font-size: 10pt; font-family: Verdana;"></span>
+
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+            
+            <span style="font-size: 10pt; font-family: Verdana;"></span>
+
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+            <span style="font-size: 10pt; font-family: Verdana;"></span>
+            
+            
+            
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+
+
+            
+            
+            
+            <ul style="list-style-type: square;"><li><span style="font-size: 10pt; font-family: Verdana;">cs43l22.h/.c:&nbsp;</span></li><ul><li><span style="font-size: 10pt; font-family: Verdana;">Add AUDIO_FREQUENCY_xxx defines for frequencies capabilities (8K to 192K)</span></li><li><span style="font-size: 10pt; font-family: Verdana;">Add codec reset function: cs43l22_Reset()<br></span></li></ul></ul><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 210px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.0.1 / 02-December-2014 <o:p></o:p></span></h3>
+
+
+
+
+
+
+
+
+
+
+
+
+            
+            
+            
+            
+            
+            
+            
+            <p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
+Changes<o:p></o:p></span></u></b></p>
+
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+
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+
+            <span style="font-size: 10pt; font-family: Verdana;"></span>
+
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+            <span style="font-size: 10pt; font-family: Verdana;"></span>
+
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+            <span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;"></span>
+
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+            
+            <span style="font-size: 10pt; font-family: Verdana;"></span>
+
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+            <span style="font-size: 10pt; font-family: Verdana;"></span>
+
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+            <span style="font-size: 10pt; font-family: Verdana;"></span>
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+            
+            
+            
+
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+
+
+            
+            
+            
+            <ul style="list-style-type: square;">
+              <li><span style="font-size: 10pt; font-family: Verdana;">cs43l22.h: change "\" by "/" in the include path to fix compilation issue under Linux</span></li>
+            </ul>
+
+            <h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 210px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.0.0 / 18-February-2014 <o:p></o:p></span></h3>
+
+
+
+
+
+
+
+
+
+
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+            
+            
+            
+            
+            
+            <p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
+Changes<o:p></o:p></span></u></b></p>
+
+
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+            <span style="font-size: 10pt; font-family: Verdana;"></span>
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+            <span style="font-size: 10pt; font-family: Verdana;"></span>
+
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+            <span style="font-size: 10pt; font-family: Verdana;"></span>
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+            <span style="font-size: 10pt; font-family: Verdana;"></span>
+
+            <span style="font-size: 10pt; font-family: Verdana;"></span>
+
+            <span style="font-size: 10pt; font-family: Verdana;"></span>
+
+
+
+
+            
+            
+            <ul style="list-style-type: square;">
+<li><span style="font-size: 10pt; font-family: Verdana;">First official release of CS43L22 audio codec &nbsp;</span><span style="font-size: 10pt; font-family: Verdana;"></span></li>
+            </ul><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic; font-weight: bold;"></span></span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic; font-weight: bold;"></span></span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic; font-weight: bold;"></span></span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic; font-weight: bold;"></span></span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic; font-weight: bold;"></span></span><span style="font-size: 10pt; font-family: Verdana;"></span><h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial;"><a name="License"></a><span style="font-size: 12pt; color: white;">License<o:p></o:p></span><br></h2>
+            <div style="text-align: justify;"><font size="-1"><span style="font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are
+met:</span><br>
+            </font>
+            <ol><li><font size="-1"><span style="font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.</span><span style="font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"></span></font></li><li><font size="-1"><span style="font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Redistributions
+in binary form must reproduce the above copyright notice, this list of
+conditions and the following disclaimer in </span><span style="font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">the documentation and/or other materials provided with the distribution.</span><span style="font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"></span></font></li><li><font size="-1"><span style="font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived </span><br>
+                </font>
+              </li></ol>
+            <font size="-1"><span style="font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; from this software without specific prior written permission.</span><br>
+            <span style="font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"></span><br>
+            <span style="font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED</span><span style="font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"> WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A </span><span style="font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY </span><span style="font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, </span><span style="font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER</span><span style="font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"> CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR </span><span style="font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.</span></font>
+            
+            </div>
+<p class="MsoNormal"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;; color: black;"><font size="-1"></font><o:p></o:p></span></p>
+<b><span style="font-size: 10pt; font-family: Verdana; color: black;"></span></b>
+            
+            <div class="MsoNormal" style="text-align: center;" align="center"><span style="color: black;">
+            <hr align="center" size="2" width="100%"></span></div>
+            <p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt; text-align: center;" align="center"><span style="font-size: 10pt; font-family: Verdana; color: black;">For
+complete documentation on </span><span style="font-size: 10pt; font-family: Verdana;">STM32<span style="color: black;">&nbsp;Microcontrollers
+visit </span><u><span style="color: blue;"><a href="http://www.st.com/internet/mcu/class/1734.jsp" target="_blank">www.st.com/STM32</a></span></u></span><span style="font-size: 10pt; font-family: Verdana;"><a target="_blank" href="http://www.st.com/internet/mcu/family/141.jsp"><u><span style="color: blue;"></span></u></a></span><span style="font-size: 10pt; font-family: Verdana;"><u><span style="color: blue;"></span></u></span><span style="color: black;"><o:p></o:p></span></p>
+            </td>
+          </tr>
+        </tbody>
+      </table>
+      <p class="MsoNormal"><span style="font-size: 10pt;"><o:p></o:p></span></p>
+      </td>
+    </tr>
+  </tbody>
+</table>
+</div>
+<p class="MsoNormal"><o:p>&nbsp;</o:p></p>
+</div>
+
+</body></html>
\ No newline at end of file
diff --git a/Drivers/BSP/Components/cs43l22/cs43l22.c b/Drivers/BSP/Components/cs43l22/cs43l22.c
new file mode 100644
index 0000000..3949418
--- /dev/null
+++ b/Drivers/BSP/Components/cs43l22/cs43l22.c
@@ -0,0 +1,493 @@
+/**
+  ******************************************************************************
+  * @file    cs43l22.c
+  * @author  MCD Application Team
+  * @brief   This file provides the CS43L22 Audio Codec driver.   
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "cs43l22.h"
+
+/** @addtogroup BSP
+  * @{
+  */
+  
+/** @addtogroup Components
+  * @{
+  */ 
+
+/** @addtogroup CS43L22
+  * @brief     This file provides a set of functions needed to drive the 
+  *            CS43L22 audio codec.
+  * @{
+  */
+
+/** @defgroup CS43L22_Private_Types
+  * @{
+  */
+
+/**
+  * @}
+  */ 
+  
+/** @defgroup CS43L22_Private_Defines
+  * @{
+  */
+#define VOLUME_CONVERT(Volume)    (((Volume) > 100)? 255:((uint8_t)(((Volume) * 255) / 100)))  
+/* Uncomment this line to enable verifying data sent to codec after each write 
+   operation (for debug purpose) */
+#if !defined (VERIFY_WRITTENDATA)  
+/* #define VERIFY_WRITTENDATA */
+#endif /* VERIFY_WRITTENDATA */
+/**
+  * @}
+  */ 
+
+/** @defgroup CS43L22_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */ 
+  
+/** @defgroup CS43L22_Private_Variables
+  * @{
+  */
+
+/* Audio codec driver structure initialization */  
+AUDIO_DrvTypeDef cs43l22_drv = 
+{
+  cs43l22_Init,
+  cs43l22_DeInit,
+  cs43l22_ReadID,
+
+  cs43l22_Play,
+  cs43l22_Pause,
+  cs43l22_Resume,
+  cs43l22_Stop,  
+  
+  cs43l22_SetFrequency,  
+  cs43l22_SetVolume,
+  cs43l22_SetMute,  
+  cs43l22_SetOutputMode,
+  cs43l22_Reset,
+};
+
+static uint8_t Is_cs43l22_Stop = 1;
+
+volatile uint8_t OutputDev = 0;
+
+/**
+  * @}
+  */ 
+
+/** @defgroup CS43L22_Function_Prototypes
+  * @{
+  */
+static uint8_t CODEC_IO_Write(uint8_t Addr, uint8_t Reg, uint8_t Value);
+/**
+  * @}
+  */ 
+
+/** @defgroup CS43L22_Private_Functions
+  * @{
+  */ 
+
+/**
+  * @brief Initializes the audio codec and the control interface.
+  * @param DeviceAddr: Device address on communication Bus.   
+  * @param OutputDevice: can be OUTPUT_DEVICE_SPEAKER, OUTPUT_DEVICE_HEADPHONE,
+  *                       OUTPUT_DEVICE_BOTH or OUTPUT_DEVICE_AUTO .
+  * @param Volume: Initial volume level (from 0 (Mute) to 100 (Max))
+  * @retval 0 if correct communication, else wrong communication
+  */
+uint32_t cs43l22_Init(uint16_t DeviceAddr, uint16_t OutputDevice, uint8_t Volume, uint32_t AudioFreq)
+{
+  uint32_t counter = 0;
+  
+  /* Initialize the Control interface of the Audio Codec */
+  AUDIO_IO_Init();     
+    
+  /* Keep Codec powered OFF */
+  counter += CODEC_IO_Write(DeviceAddr, CS43L22_REG_POWER_CTL1, 0x01);  
+  
+  /*Save Output device for mute ON/OFF procedure*/
+  switch (OutputDevice)
+  {
+  case OUTPUT_DEVICE_SPEAKER:
+    OutputDev = 0xFA;
+    break;
+    
+  case OUTPUT_DEVICE_HEADPHONE:
+    OutputDev = 0xAF;
+    break;
+    
+  case OUTPUT_DEVICE_BOTH:
+    OutputDev = 0xAA;
+    break;
+    
+  case OUTPUT_DEVICE_AUTO:
+    OutputDev = 0x05;
+    break;    
+    
+  default:
+    OutputDev = 0x05;
+    break;    
+  }
+  
+  counter += CODEC_IO_Write(DeviceAddr, CS43L22_REG_POWER_CTL2, OutputDev);
+  
+  /* Clock configuration: Auto detection */  
+  counter += CODEC_IO_Write(DeviceAddr, CS43L22_REG_CLOCKING_CTL, 0x81);
+  
+  /* Set the Slave Mode and the audio Standard */  
+  counter += CODEC_IO_Write(DeviceAddr, CS43L22_REG_INTERFACE_CTL1, CODEC_STANDARD);
+  
+  /* Set the Master volume */
+  counter += cs43l22_SetVolume(DeviceAddr, Volume);
+  
+  /* If the Speaker is enabled, set the Mono mode and volume attenuation level */
+  if(OutputDevice != OUTPUT_DEVICE_HEADPHONE)
+  {
+    /* Set the Speaker Mono mode */  
+    counter += CODEC_IO_Write(DeviceAddr, CS43L22_REG_PLAYBACK_CTL2, 0x06);
+    
+    /* Set the Speaker attenuation level */  
+    counter += CODEC_IO_Write(DeviceAddr, CS43L22_REG_SPEAKER_A_VOL, 0x00);
+    counter += CODEC_IO_Write(DeviceAddr, CS43L22_REG_SPEAKER_B_VOL, 0x00);
+  }
+  
+  /* Additional configuration for the CODEC. These configurations are done to reduce
+  the time needed for the Codec to power off. If these configurations are removed, 
+  then a long delay should be added between powering off the Codec and switching 
+  off the I2S peripheral MCLK clock (which is the operating clock for Codec).
+  If this delay is not inserted, then the codec will not shut down properly and
+  it results in high noise after shut down. */
+  
+  /* Disable the analog soft ramp */
+  counter += CODEC_IO_Write(DeviceAddr, CS43L22_REG_ANALOG_ZC_SR_SETT, 0x00);
+  /* Disable the digital soft ramp */
+  counter += CODEC_IO_Write(DeviceAddr, CS43L22_REG_MISC_CTL, 0x04);
+  /* Disable the limiter attack level */
+  counter += CODEC_IO_Write(DeviceAddr, CS43L22_REG_LIMIT_CTL1, 0x00);
+  /* Adjust Bass and Treble levels */
+  counter += CODEC_IO_Write(DeviceAddr, CS43L22_REG_TONE_CTL, 0x0F);
+  /* Adjust PCM volume level */
+  counter += CODEC_IO_Write(DeviceAddr, CS43L22_REG_PCMA_VOL, 0x0A);
+  counter += CODEC_IO_Write(DeviceAddr, CS43L22_REG_PCMB_VOL, 0x0A);
+  
+  /* Return communication control value */
+  return counter;  
+}
+
+/**
+  * @brief  Deinitializes the audio codec.
+  * @param  None
+  * @retval  None
+  */
+void cs43l22_DeInit(void)
+{
+  /* Deinitialize Audio Codec interface */
+  AUDIO_IO_DeInit();
+}
+
+/**
+  * @brief  Get the CS43L22 ID.
+  * @param DeviceAddr: Device address on communication Bus.   
+  * @retval The CS43L22 ID 
+  */
+uint32_t cs43l22_ReadID(uint16_t DeviceAddr)
+{
+  uint8_t Value;
+  /* Initialize the Control interface of the Audio Codec */
+  AUDIO_IO_Init(); 
+  
+  Value = AUDIO_IO_Read(DeviceAddr, CS43L22_CHIPID_ADDR);
+  Value = (Value & CS43L22_ID_MASK);
+  
+  return((uint32_t) Value);
+}
+
+/**
+  * @brief Start the audio Codec play feature.
+  * @note For this codec no Play options are required.
+  * @param DeviceAddr: Device address on communication Bus.   
+  * @retval 0 if correct communication, else wrong communication
+  */
+uint32_t cs43l22_Play(uint16_t DeviceAddr, uint16_t* pBuffer, uint16_t Size)
+{
+  uint32_t counter = 0;
+  
+  if(Is_cs43l22_Stop == 1)
+  {
+    /* Enable the digital soft ramp */
+    counter += CODEC_IO_Write(DeviceAddr, CS43L22_REG_MISC_CTL, 0x06);
+  
+    /* Enable Output device */  
+    counter += cs43l22_SetMute(DeviceAddr, AUDIO_MUTE_OFF);
+    
+    /* Power on the Codec */
+    counter += CODEC_IO_Write(DeviceAddr, CS43L22_REG_POWER_CTL1, 0x9E);  
+    Is_cs43l22_Stop = 0;
+  }
+  
+  /* Return communication control value */
+  return counter;  
+}
+
+/**
+  * @brief Pauses playing on the audio codec.
+  * @param DeviceAddr: Device address on communication Bus. 
+  * @retval 0 if correct communication, else wrong communication
+  */
+uint32_t cs43l22_Pause(uint16_t DeviceAddr)
+{  
+  uint32_t counter = 0;
+ 
+  /* Pause the audio file playing */
+  /* Mute the output first */
+  counter += cs43l22_SetMute(DeviceAddr, AUDIO_MUTE_ON);
+  
+  /* Put the Codec in Power save mode */    
+  counter += CODEC_IO_Write(DeviceAddr, CS43L22_REG_POWER_CTL1, 0x01);
+ 
+  return counter;
+}
+
+/**
+  * @brief Resumes playing on the audio codec.
+  * @param DeviceAddr: Device address on communication Bus. 
+  * @retval 0 if correct communication, else wrong communication
+  */
+uint32_t cs43l22_Resume(uint16_t DeviceAddr)
+{
+  uint32_t counter = 0;
+  volatile uint32_t index = 0x00;
+  /* Resumes the audio file playing */  
+  /* Unmute the output first */
+  counter += cs43l22_SetMute(DeviceAddr, AUDIO_MUTE_OFF);
+
+  for(index = 0x00; index < 0xFF; index++);
+  
+  counter += CODEC_IO_Write(DeviceAddr, CS43L22_REG_POWER_CTL2, OutputDev);
+
+  /* Exit the Power save mode */
+  counter += CODEC_IO_Write(DeviceAddr, CS43L22_REG_POWER_CTL1, 0x9E); 
+  
+  return counter;
+}
+
+/**
+  * @brief Stops audio Codec playing. It powers down the codec.
+  * @param DeviceAddr: Device address on communication Bus. 
+  * @param CodecPdwnMode: selects the  power down mode.
+  *          - CODEC_PDWN_HW: Physically power down the codec. When resuming from this
+  *                           mode, the codec is set to default configuration 
+  *                           (user should re-Initialize the codec in order to 
+  *                            play again the audio stream).
+  * @retval 0 if correct communication, else wrong communication
+  */
+uint32_t cs43l22_Stop(uint16_t DeviceAddr, uint32_t CodecPdwnMode)
+{
+  uint32_t counter = 0;
+  
+  /* Mute the output first */
+  counter += cs43l22_SetMute(DeviceAddr, AUDIO_MUTE_ON);
+
+  /* Disable the digital soft ramp */
+  counter += CODEC_IO_Write(DeviceAddr, CS43L22_REG_MISC_CTL, 0x04);
+  
+  /* Power down the DAC and the speaker (PMDAC and PMSPK bits)*/
+  counter += CODEC_IO_Write(DeviceAddr, CS43L22_REG_POWER_CTL1, 0x9F);
+  
+  Is_cs43l22_Stop = 1;
+  return counter;    
+}
+
+/**
+  * @brief Sets higher or lower the codec volume level.
+  * @param DeviceAddr: Device address on communication Bus.   
+  * @param Volume: a byte value from 0 to 255 (refer to codec registers 
+  *                description for more details).
+  *         
+  * @retval 0 if correct communication, else wrong communication
+  */
+uint32_t cs43l22_SetVolume(uint16_t DeviceAddr, uint8_t Volume)
+{
+  uint32_t counter = 0;
+  uint8_t convertedvol = VOLUME_CONVERT(Volume);
+
+  if(convertedvol > 0xE6)
+  {
+    /* Set the Master volume */
+    counter += CODEC_IO_Write(DeviceAddr, CS43L22_REG_MASTER_A_VOL, convertedvol - 0xE7); 
+    counter += CODEC_IO_Write(DeviceAddr, CS43L22_REG_MASTER_B_VOL, convertedvol - 0xE7);     
+  }
+  else
+  {
+    /* Set the Master volume */
+    counter += CODEC_IO_Write(DeviceAddr, CS43L22_REG_MASTER_A_VOL, convertedvol + 0x19); 
+    counter += CODEC_IO_Write(DeviceAddr, CS43L22_REG_MASTER_B_VOL, convertedvol + 0x19); 
+  }
+
+  return counter;
+}
+
+/**
+  * @brief Sets new frequency.
+  * @param DeviceAddr: Device address on communication Bus.   
+  * @param AudioFreq: Audio frequency used to play the audio stream.
+  * @retval 0 if correct communication, else wrong communication
+  */
+uint32_t cs43l22_SetFrequency(uint16_t DeviceAddr, uint32_t AudioFreq)
+{
+  return 0;
+}
+
+/**
+  * @brief Enables or disables the mute feature on the audio codec.
+  * @param DeviceAddr: Device address on communication Bus.   
+  * @param Cmd: AUDIO_MUTE_ON to enable the mute or AUDIO_MUTE_OFF to disable the
+  *             mute mode.
+  * @retval 0 if correct communication, else wrong communication
+  */
+uint32_t cs43l22_SetMute(uint16_t DeviceAddr, uint32_t Cmd)
+{
+  uint32_t counter = 0;
+  
+  /* Set the Mute mode */
+  if(Cmd == AUDIO_MUTE_ON)
+  {
+    counter += CODEC_IO_Write(DeviceAddr, CS43L22_REG_POWER_CTL2, 0xFF);
+    counter += CODEC_IO_Write(DeviceAddr, CS43L22_REG_HEADPHONE_A_VOL, 0x01);
+    counter += CODEC_IO_Write(DeviceAddr, CS43L22_REG_HEADPHONE_B_VOL, 0x01);
+  }
+  else /* AUDIO_MUTE_OFF Disable the Mute */
+  {
+    counter += CODEC_IO_Write(DeviceAddr, CS43L22_REG_HEADPHONE_A_VOL, 0x00);
+    counter += CODEC_IO_Write(DeviceAddr, CS43L22_REG_HEADPHONE_B_VOL, 0x00);
+    counter += CODEC_IO_Write(DeviceAddr, CS43L22_REG_POWER_CTL2, OutputDev);
+  }
+  return counter;
+}
+
+/**
+  * @brief Switch dynamically (while audio file is played) the output target 
+  *         (speaker or headphone).
+  * @note This function modifies a global variable of the audio codec driver: OutputDev.
+  * @param DeviceAddr: Device address on communication Bus.
+  * @param Output: specifies the audio output target: OUTPUT_DEVICE_SPEAKER,
+  *         OUTPUT_DEVICE_HEADPHONE, OUTPUT_DEVICE_BOTH or OUTPUT_DEVICE_AUTO 
+  * @retval 0 if correct communication, else wrong communication
+  */
+uint32_t cs43l22_SetOutputMode(uint16_t DeviceAddr, uint8_t Output)
+{
+  uint32_t counter = 0; 
+  
+  switch (Output) 
+  {
+    case OUTPUT_DEVICE_SPEAKER:
+      counter += CODEC_IO_Write(DeviceAddr, CS43L22_REG_POWER_CTL2, 0xFA); /* SPK always ON & HP always OFF */
+      OutputDev = 0xFA;
+      break;
+      
+    case OUTPUT_DEVICE_HEADPHONE:
+      counter += CODEC_IO_Write(DeviceAddr, CS43L22_REG_POWER_CTL2, 0xAF); /* SPK always OFF & HP always ON */
+      OutputDev = 0xAF;
+      break;
+      
+    case OUTPUT_DEVICE_BOTH:
+      counter += CODEC_IO_Write(DeviceAddr, CS43L22_REG_POWER_CTL2, 0xAA); /* SPK always ON & HP always ON */
+      OutputDev = 0xAA;
+      break;
+      
+    case OUTPUT_DEVICE_AUTO:
+      counter += CODEC_IO_Write(DeviceAddr, CS43L22_REG_POWER_CTL2, 0x05); /* Detect the HP or the SPK automatically */
+      OutputDev = 0x05;
+      break;    
+      
+    default:
+      counter += CODEC_IO_Write(DeviceAddr, CS43L22_REG_POWER_CTL2, 0x05); /* Detect the HP or the SPK automatically */
+      OutputDev = 0x05;
+      break;
+  }  
+  return counter;
+}
+
+/**
+  * @brief Resets cs43l22 registers.
+  * @param DeviceAddr: Device address on communication Bus. 
+  * @retval 0 if correct communication, else wrong communication
+  */
+uint32_t cs43l22_Reset(uint16_t DeviceAddr)
+{
+  return 0;
+}
+
+/**
+  * @brief  Writes/Read a single data.
+  * @param  Addr: I2C address
+  * @param  Reg: Reg address 
+  * @param  Value: Data to be written
+  * @retval None
+  */
+static uint8_t CODEC_IO_Write(uint8_t Addr, uint8_t Reg, uint8_t Value)
+{
+  uint32_t result = 0;
+  
+  AUDIO_IO_Write(Addr, Reg, Value);
+  
+#ifdef VERIFY_WRITTENDATA
+  /* Verify that the data has been correctly written */  
+  result = (AUDIO_IO_Read(Addr, Reg) == Value)? 0:1;
+#endif /* VERIFY_WRITTENDATA */
+  
+  return result;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Drivers/BSP/Components/cs43l22/cs43l22.h b/Drivers/BSP/Components/cs43l22/cs43l22.h
new file mode 100644
index 0000000..14ab36d
--- /dev/null
+++ b/Drivers/BSP/Components/cs43l22/cs43l22.h
@@ -0,0 +1,226 @@
+/**
+  ******************************************************************************
+  * @file    cs43l22.h
+  * @author  MCD Application Team
+  * @brief   This file contains all the functions prototypes for the cs43l22.c driver.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __CS43L22_H
+#define __CS43L22_H
+
+/* Includes ------------------------------------------------------------------*/
+#include "../Common/audio.h"
+
+/** @addtogroup BSP
+  * @{
+  */ 
+
+/** @addtogroup Component
+  * @{
+  */ 
+  
+/** @addtogroup CS43L22
+  * @{
+  */
+
+/** @defgroup CS43L22_Exported_Types
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup CS43L22_Exported_Constants
+  * @{
+  */ 
+
+/******************************************************************************/
+/***************************  Codec User defines ******************************/
+/******************************************************************************/
+/* Codec output DEVICE */
+#define OUTPUT_DEVICE_SPEAKER         1
+#define OUTPUT_DEVICE_HEADPHONE       2
+#define OUTPUT_DEVICE_BOTH            3
+#define OUTPUT_DEVICE_AUTO            4
+
+/* Volume Levels values */
+#define DEFAULT_VOLMIN                0x00
+#define DEFAULT_VOLMAX                0xFF
+#define DEFAULT_VOLSTEP               0x04
+
+#define AUDIO_PAUSE                   0
+#define AUDIO_RESUME                  1
+
+/* Codec POWER DOWN modes */
+#define CODEC_PDWN_HW                 1
+#define CODEC_PDWN_SW                 2
+
+/* MUTE commands */
+#define AUDIO_MUTE_ON                 1
+#define AUDIO_MUTE_OFF                0
+
+/* AUDIO FREQUENCY */
+#define AUDIO_FREQUENCY_192K          ((uint32_t)192000)
+#define AUDIO_FREQUENCY_96K           ((uint32_t)96000)
+#define AUDIO_FREQUENCY_48K           ((uint32_t)48000)
+#define AUDIO_FREQUENCY_44K           ((uint32_t)44100)
+#define AUDIO_FREQUENCY_32K           ((uint32_t)32000)
+#define AUDIO_FREQUENCY_22K           ((uint32_t)22050)
+#define AUDIO_FREQUENCY_16K           ((uint32_t)16000)
+#define AUDIO_FREQUENCY_11K           ((uint32_t)11025)
+#define AUDIO_FREQUENCY_8K            ((uint32_t)8000)  
+
+/** CS43l22 Registers  ***/
+#define   CS43L22_REG_ID                  0x01
+#define   CS43L22_REG_POWER_CTL1          0x02
+#define   CS43L22_REG_POWER_CTL2          0x04
+#define   CS43L22_REG_CLOCKING_CTL        0x05
+#define   CS43L22_REG_INTERFACE_CTL1      0x06
+#define   CS43L22_REG_INTERFACE_CTL2      0x07
+#define   CS43L22_REG_PASSTHR_A_SELECT    0x08
+#define   CS43L22_REG_PASSTHR_B_SELECT    0x09
+#define   CS43L22_REG_ANALOG_ZC_SR_SETT   0x0A
+#define   CS43L22_REG_PASSTHR_GANG_CTL    0x0C
+#define   CS43L22_REG_PLAYBACK_CTL1       0x0D
+#define   CS43L22_REG_MISC_CTL            0x0E
+#define   CS43L22_REG_PLAYBACK_CTL2       0x0F
+#define   CS43L22_REG_PASSTHR_A_VOL       0x14
+#define   CS43L22_REG_PASSTHR_B_VOL       0x15
+#define   CS43L22_REG_PCMA_VOL            0x1A
+#define   CS43L22_REG_PCMB_VOL            0x1B
+#define   CS43L22_REG_BEEP_FREQ_ON_TIME   0x1C
+#define   CS43L22_REG_BEEP_VOL_OFF_TIME   0x1D
+#define   CS43L22_REG_BEEP_TONE_CFG       0x1E
+#define   CS43L22_REG_TONE_CTL            0x1F
+#define   CS43L22_REG_MASTER_A_VOL        0x20
+#define   CS43L22_REG_MASTER_B_VOL        0x21
+#define   CS43L22_REG_HEADPHONE_A_VOL     0x22
+#define   CS43L22_REG_HEADPHONE_B_VOL     0x23
+#define   CS43L22_REG_SPEAKER_A_VOL       0x24
+#define   CS43L22_REG_SPEAKER_B_VOL       0x25
+#define   CS43L22_REG_CH_MIXER_SWAP       0x26
+#define   CS43L22_REG_LIMIT_CTL1          0x27
+#define   CS43L22_REG_LIMIT_CTL2          0x28
+#define   CS43L22_REG_LIMIT_ATTACK_RATE   0x29
+#define   CS43L22_REG_OVF_CLK_STATUS      0x2E
+#define   CS43L22_REG_BATT_COMPENSATION   0x2F
+#define   CS43L22_REG_VP_BATTERY_LEVEL    0x30
+#define   CS43L22_REG_SPEAKER_STATUS      0x31
+#define   CS43L22_REG_TEMPMONITOR_CTL     0x32
+#define   CS43L22_REG_THERMAL_FOLDBACK    0x33
+#define   CS43L22_REG_CHARGE_PUMP_FREQ    0x34
+
+/******************************************************************************/
+/****************************** REGISTER MAPPING ******************************/
+/******************************************************************************/
+/** 
+  * @brief  CS43L22 ID  
+  */  
+#define  CS43L22_ID            0xE0
+#define  CS43L22_ID_MASK       0xF8
+/**
+  * @brief Chip ID Register: Chip I.D. and Revision Register
+  *  Read only register
+  *  Default value: 0x01
+  *  [7:3] CHIPID[4:0]: I.D. code for the CS43L22.
+  *        Default value: 11100b
+  *  [2:0] REVID[2:0]: CS43L22 revision level.
+  *        Default value: 
+  *        000 - Rev A0
+  *        001 - Rev A1
+  *        010 - Rev B0
+  *        011 - Rev B1
+  */
+#define CS43L22_CHIPID_ADDR    0x01
+
+/**
+  * @}
+  */ 
+
+/** @defgroup CS43L22_Exported_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */ 
+
+/** @defgroup CS43L22_Exported_Functions
+  * @{
+  */
+    
+/*------------------------------------------------------------------------------
+                           Audio Codec functions 
+------------------------------------------------------------------------------*/
+/* High Layer codec functions */
+uint32_t cs43l22_Init(uint16_t DeviceAddr, uint16_t OutputDevice, uint8_t Volume, uint32_t AudioFreq);
+void     cs43l22_DeInit(void);
+uint32_t cs43l22_ReadID(uint16_t DeviceAddr);
+uint32_t cs43l22_Play(uint16_t DeviceAddr, uint16_t* pBuffer, uint16_t Size);
+uint32_t cs43l22_Pause(uint16_t DeviceAddr);
+uint32_t cs43l22_Resume(uint16_t DeviceAddr);
+uint32_t cs43l22_Stop(uint16_t DeviceAddr, uint32_t Cmd);
+uint32_t cs43l22_SetVolume(uint16_t DeviceAddr, uint8_t Volume);
+uint32_t cs43l22_SetFrequency(uint16_t DeviceAddr, uint32_t AudioFreq);
+uint32_t cs43l22_SetMute(uint16_t DeviceAddr, uint32_t Cmd);
+uint32_t cs43l22_SetOutputMode(uint16_t DeviceAddr, uint8_t Output);
+uint32_t cs43l22_Reset(uint16_t DeviceAddr);
+
+/* AUDIO IO functions */
+void      AUDIO_IO_Init(void);
+void      AUDIO_IO_DeInit(void);
+void      AUDIO_IO_Write(uint8_t Addr, uint8_t Reg, uint8_t Value);
+uint8_t   AUDIO_IO_Read(uint8_t Addr, uint8_t Reg);
+
+/* Audio driver structure */
+extern AUDIO_DrvTypeDef   cs43l22_drv;
+
+#endif /* __CS43L22_H */
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */ 
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Drivers/BSP/Components/ft6x06/Release_Notes.html b/Drivers/BSP/Components/ft6x06/Release_Notes.html
new file mode 100644
index 0000000..81ec955
--- /dev/null
+++ b/Drivers/BSP/Components/ft6x06/Release_Notes.html
@@ -0,0 +1,91 @@
+<!DOCTYPE html>
+<html xmlns="http://www.w3.org/1999/xhtml" lang="en" xml:lang="en">
+<head>
+  <meta charset="utf-8" />
+  <meta name="generator" content="pandoc" />
+  <meta name="viewport" content="width=device-width, initial-scale=1.0, user-scalable=yes" />
+  <title>Release Notes for FT6X06 Component Drivers</title>
+  <style>
+      code{white-space: pre-wrap;}
+      span.smallcaps{font-variant: small-caps;}
+      span.underline{text-decoration: underline;}
+      div.column{display: inline-block; vertical-align: top; width: 50%;}
+  </style>
+  <link rel="stylesheet" href="_htmresc/mini-st.css" />
+  <!--[if lt IE 9]>
+    <script src="//cdnjs.cloudflare.com/ajax/libs/html5shiv/3.7.3/html5shiv-printshiv.min.js"></script>
+  <![endif]-->
+</head>
+<body>
+<div class="row">
+<div class="col-sm-12 col-lg-4">
+<div class="card fluid">
+<div class="sectione dark">
+<center>
+<h1 id="release-notes-for-ft6x06-component-drivers"><small>Release Notes for</small> <mark>FT6X06 Component Drivers</mark></h1>
+<p>Copyright © 2016 STMicroelectronics<br />
+</p>
+<a href="https://www.st.com" class="logo"><img src="_htmresc/st_logo.png" alt="ST logo" /></a>
+</center>
+</div>
+</div>
+<h1 id="license">License</h1>
+<p>Licensed by ST under BSD 3-Clause license (the "License"). You may not use this package except in compliance with the License. You may obtain a copy of the License at:</p>
+<p><a href="https://opensource.org/licenses/BSD-3-Clause">https://opensource.org/licenses/BSD-3-Clause</a></p>
+<h1 id="purpose">Purpose</h1>
+<p>This directory contains the FT6X06 component drivers.</p>
+</div>
+<div class="col-sm-12 col-lg-8">
+<h1 id="update-history">Update History</h1>
+<div class="collapse">
+<input type="checkbox" id="collapse-section23" checked aria-hidden="true"> <label for="collapse-section23" aria-hidden="true">V1.1.0 / 11-December-2020</label>
+<div>
+<h2 id="main-changes">Main Changes</h2>
+<ul>
+<li>Add new FT6xx6 chip ID.</li>
+</ul>
+</div>
+</div>
+<div class="collapse">
+<input type="checkbox" id="collapse-section22" aria-hidden="true"> <label for="collapse-section22" aria-hidden="true">V1.0.3 / 03-April-2019</label>
+<div>
+<h2 id="main-changes-1">Main Changes</h2>
+<ul>
+<li>Update release notes format</li>
+</ul>
+</div>
+</div>
+<div class="collapse">
+<input type="checkbox" id="collapse-section20" aria-hidden="true"> <label for="collapse-section20" aria-hidden="true">V1.0.2 / 31-August-2018</label>
+<div>
+<h2 id="main-changes-2">Main Changes</h2>
+<ul>
+<li>Reformat the BSD 3-Clause license declaration in the files header (replace license terms by a web reference to OSI website where those terms lie)</li>
+</ul>
+</div>
+</div>
+<div class="collapse">
+<input type="checkbox" id="collapse-section19" aria-hidden="true"> <label for="collapse-section19" aria-hidden="true">V1.0.1 / 03-May-2016</label>
+<div>
+<h2 id="main-changes-3">Main Changes</h2>
+<ul>
+<li>Add support of FT6x36 Touch controller</li>
+</ul>
+</div>
+</div>
+<div class="collapse">
+<input type="checkbox" id="collapse-section18" aria-hidden="true"> <label for="collapse-section18" aria-hidden="true">V1.0.0 / 03-August-2015</label>
+<div>
+<h2 id="main-changes-4">Main Changes</h2>
+<ul>
+<li>First official release</li>
+</ul>
+</div>
+</div>
+</div>
+</div>
+<footer class="sticky">
+For complete documentation on <mark>STM32 Microcontrollers</mark> , visit: <a href="http://www.st.com/STM32">http://www.st.com/STM32</a>
+</footer>
+</body>
+</html>
diff --git a/Drivers/BSP/Components/ft6x06/_htmresc/mini-st.css b/Drivers/BSP/Components/ft6x06/_htmresc/mini-st.css
new file mode 100644
index 0000000..9b2d0a9
--- /dev/null
+++ b/Drivers/BSP/Components/ft6x06/_htmresc/mini-st.css
@@ -0,0 +1,1700 @@
+@charset "UTF-8";
+/*
+  Flavor name: Default (mini-default)
+  Author: Angelos Chalaris (chalarangelo@gmail.com)
+  Maintainers: Angelos Chalaris
+  mini.css version: v3.0.0-alpha.3
+*/
+/*
+  Browsers resets and base typography.
+*/
+/* Core module CSS variable definitions */
+:root {
+  --fore-color: #111;
+  --secondary-fore-color: #444;
+  --back-color: #f8f8f8;
+  --secondary-back-color: #f0f0f0;
+  --blockquote-color: #f57c00;
+  --pre-color: #1565c0;
+  --border-color: #aaa;
+  --secondary-border-color: #ddd;
+  --heading-ratio: 1.19;
+  --universal-margin: 0.5rem;
+  --universal-padding: 0.125rem;
+  --universal-border-radius: 0.125rem;
+  --a-link-color: #0277bd;
+  --a-visited-color: #01579b; }
+
+html {
+  font-size: 14px; }
+
+a, b, del, em, i, ins, q, span, strong, u {
+  font-size: 1em; }
+
+html, * {
+  font-family: -apple-system, BlinkMacSystemFont, "Segoe UI", Roboto, Ubuntu, "Helvetica Neue", Helvetica, sans-serif;
+  line-height: 1.4;
+  -webkit-text-size-adjust: 100%; }
+
+* {
+  font-size: 1rem; }
+
+body {
+  margin: 0;
+  color: var(--fore-color);
+  background: var(--back-color); }
+
+details {
+  display: block; }
+
+summary {
+  display: list-item; }
+
+abbr[title] {
+  border-bottom: none;
+  text-decoration: underline dotted; }
+
+input {
+  overflow: visible; }
+
+img {
+  max-width: 100%;
+  height: auto; }
+
+h1, h2, h3, h4, h5, h6 {
+  line-height: 1.2;
+  margin: calc(1.5 * var(--universal-margin)) var(--universal-margin);
+  font-weight: 500; }
+  h1 small, h2 small, h3 small, h4 small, h5 small, h6 small {
+    color: var(--secondary-fore-color);
+    display: block;
+    margin-top: -0.25rem; }
+
+h1 {
+  font-size: calc(1rem * var(--heading-ratio) * var(--heading-ratio) * var(--heading-ratio)); }
+
+h2 {
+  font-size: calc(1rem * var(--heading-ratio) * var(--heading-ratio); );
+  background: var(--mark-back-color);
+  font-weight: 600;
+  padding: 0.1em 0.5em 0.2em 0.5em;
+  color: var(--mark-fore-color); }
+
+h3 {
+  font-size: calc(1rem * var(--heading-ratio));
+  padding-left: calc(2 * var(--universal-margin)); 
+  /* background: var(--border-color); */
+    }
+
+h4 {
+  font-size: 1rem;);
+  padding-left: calc(4 * var(--universal-margin));  }
+
+h5 {
+  font-size: 1rem; }
+
+h6 {
+  font-size: calc(1rem / var(--heading-ratio)); }
+
+p {
+  margin: var(--universal-margin); }
+
+ol, ul {
+  margin: var(--universal-margin);
+  padding-left: calc(6 * var(--universal-margin)); }
+
+b, strong {
+  font-weight: 700; }
+
+hr {
+  box-sizing: content-box;
+  border: 0;
+  line-height: 1.25em;
+  margin: var(--universal-margin);
+  height: 0.0625rem;
+  background: linear-gradient(to right, transparent, var(--border-color) 20%, var(--border-color) 80%, transparent); }
+
+blockquote {
+  display: block;
+  position: relative;
+  font-style: italic;
+  color: var(--secondary-fore-color);
+  margin: var(--universal-margin);
+  padding: calc(3 * var(--universal-padding));
+  border: 0.0625rem solid var(--secondary-border-color);
+  border-left: 0.375rem solid var(--blockquote-color);
+  border-radius: 0 var(--universal-border-radius) var(--universal-border-radius) 0; }
+  blockquote:before {
+    position: absolute;
+    top: calc(0rem - var(--universal-padding));
+    left: 0;
+    font-family: sans-serif;
+    font-size: 3rem;
+    font-weight: 700;
+    content: "\201c";
+    color: var(--blockquote-color); }
+  blockquote[cite]:after {
+    font-style: normal;
+    font-size: 0.75em;
+    font-weight: 700;
+    content: "\a—  " attr(cite);
+    white-space: pre; }
+
+code, kbd, pre, samp {
+  font-family: Menlo, Consolas, monospace;
+  font-size: 0.85em; }
+
+code {
+  background: var(--secondary-back-color);
+  border-radius: var(--universal-border-radius);
+  padding: calc(var(--universal-padding) / 4) calc(var(--universal-padding) / 2); }
+
+kbd {
+  background: var(--fore-color);
+  color: var(--back-color);
+  border-radius: var(--universal-border-radius);
+  padding: calc(var(--universal-padding) / 4) calc(var(--universal-padding) / 2); }
+
+pre {
+  overflow: auto;
+  background: var(--secondary-back-color);
+  padding: calc(1.5 * var(--universal-padding));
+  margin: var(--universal-margin);
+  border: 0.0625rem solid var(--secondary-border-color);
+  border-left: 0.25rem solid var(--pre-color);
+  border-radius: 0 var(--universal-border-radius) var(--universal-border-radius) 0; }
+
+sup, sub, code, kbd {
+  line-height: 0;
+  position: relative;
+  vertical-align: baseline; }
+
+small, sup, sub, figcaption {
+  font-size: 0.75em; }
+
+sup {
+  top: -0.5em; }
+
+sub {
+  bottom: -0.25em; }
+
+figure {
+  margin: var(--universal-margin); }
+
+figcaption {
+  color: var(--secondary-fore-color); }
+
+a {
+  text-decoration: none; }
+  a:link {
+    color: var(--a-link-color); }
+  a:visited {
+    color: var(--a-visited-color); }
+  a:hover, a:focus {
+    text-decoration: underline; }
+
+/*
+  Definitions for the grid system, cards and containers.
+*/
+.container {
+  margin: 0 auto;
+  padding: 0 calc(1.5 * var(--universal-padding)); }
+
+.row {
+  box-sizing: border-box;
+  display: flex;
+  flex: 0 1 auto;
+  flex-flow: row wrap; }
+
+.col-sm,
+[class^='col-sm-'],
+[class^='col-sm-offset-'],
+.row[class*='cols-sm-'] > * {
+  box-sizing: border-box;
+  flex: 0 0 auto;
+  padding: 0 calc(var(--universal-padding) / 2); }
+
+.col-sm,
+.row.cols-sm > * {
+  max-width: 100%;
+  flex-grow: 1;
+  flex-basis: 0; }
+
+.col-sm-1,
+.row.cols-sm-1 > * {
+  max-width: 8.3333333333%;
+  flex-basis: 8.3333333333%; }
+
+.col-sm-offset-0 {
+  margin-left: 0; }
+
+.col-sm-2,
+.row.cols-sm-2 > * {
+  max-width: 16.6666666667%;
+  flex-basis: 16.6666666667%; }
+
+.col-sm-offset-1 {
+  margin-left: 8.3333333333%; }
+
+.col-sm-3,
+.row.cols-sm-3 > * {
+  max-width: 25%;
+  flex-basis: 25%; }
+
+.col-sm-offset-2 {
+  margin-left: 16.6666666667%; }
+
+.col-sm-4,
+.row.cols-sm-4 > * {
+  max-width: 33.3333333333%;
+  flex-basis: 33.3333333333%; }
+
+.col-sm-offset-3 {
+  margin-left: 25%; }
+
+.col-sm-5,
+.row.cols-sm-5 > * {
+  max-width: 41.6666666667%;
+  flex-basis: 41.6666666667%; }
+
+.col-sm-offset-4 {
+  margin-left: 33.3333333333%; }
+
+.col-sm-6,
+.row.cols-sm-6 > * {
+  max-width: 50%;
+  flex-basis: 50%; }
+
+.col-sm-offset-5 {
+  margin-left: 41.6666666667%; }
+
+.col-sm-7,
+.row.cols-sm-7 > * {
+  max-width: 58.3333333333%;
+  flex-basis: 58.3333333333%; }
+
+.col-sm-offset-6 {
+  margin-left: 50%; }
+
+.col-sm-8,
+.row.cols-sm-8 > * {
+  max-width: 66.6666666667%;
+  flex-basis: 66.6666666667%; }
+
+.col-sm-offset-7 {
+  margin-left: 58.3333333333%; }
+
+.col-sm-9,
+.row.cols-sm-9 > * {
+  max-width: 75%;
+  flex-basis: 75%; }
+
+.col-sm-offset-8 {
+  margin-left: 66.6666666667%; }
+
+.col-sm-10,
+.row.cols-sm-10 > * {
+  max-width: 83.3333333333%;
+  flex-basis: 83.3333333333%; }
+
+.col-sm-offset-9 {
+  margin-left: 75%; }
+
+.col-sm-11,
+.row.cols-sm-11 > * {
+  max-width: 91.6666666667%;
+  flex-basis: 91.6666666667%; }
+
+.col-sm-offset-10 {
+  margin-left: 83.3333333333%; }
+
+.col-sm-12,
+.row.cols-sm-12 > * {
+  max-width: 100%;
+  flex-basis: 100%; }
+
+.col-sm-offset-11 {
+  margin-left: 91.6666666667%; }
+
+.col-sm-normal {
+  order: initial; }
+
+.col-sm-first {
+  order: -999; }
+
+.col-sm-last {
+  order: 999; }
+
+@media screen and (min-width: 500px) {
+  .col-md,
+  [class^='col-md-'],
+  [class^='col-md-offset-'],
+  .row[class*='cols-md-'] > * {
+    box-sizing: border-box;
+    flex: 0 0 auto;
+    padding: 0 calc(var(--universal-padding) / 2); }
+
+  .col-md,
+  .row.cols-md > * {
+    max-width: 100%;
+    flex-grow: 1;
+    flex-basis: 0; }
+
+  .col-md-1,
+  .row.cols-md-1 > * {
+    max-width: 8.3333333333%;
+    flex-basis: 8.3333333333%; }
+
+  .col-md-offset-0 {
+    margin-left: 0; }
+
+  .col-md-2,
+  .row.cols-md-2 > * {
+    max-width: 16.6666666667%;
+    flex-basis: 16.6666666667%; }
+
+  .col-md-offset-1 {
+    margin-left: 8.3333333333%; }
+
+  .col-md-3,
+  .row.cols-md-3 > * {
+    max-width: 25%;
+    flex-basis: 25%; }
+
+  .col-md-offset-2 {
+    margin-left: 16.6666666667%; }
+
+  .col-md-4,
+  .row.cols-md-4 > * {
+    max-width: 33.3333333333%;
+    flex-basis: 33.3333333333%; }
+
+  .col-md-offset-3 {
+    margin-left: 25%; }
+
+  .col-md-5,
+  .row.cols-md-5 > * {
+    max-width: 41.6666666667%;
+    flex-basis: 41.6666666667%; }
+
+  .col-md-offset-4 {
+    margin-left: 33.3333333333%; }
+
+  .col-md-6,
+  .row.cols-md-6 > * {
+    max-width: 50%;
+    flex-basis: 50%; }
+
+  .col-md-offset-5 {
+    margin-left: 41.6666666667%; }
+
+  .col-md-7,
+  .row.cols-md-7 > * {
+    max-width: 58.3333333333%;
+    flex-basis: 58.3333333333%; }
+
+  .col-md-offset-6 {
+    margin-left: 50%; }
+
+  .col-md-8,
+  .row.cols-md-8 > * {
+    max-width: 66.6666666667%;
+    flex-basis: 66.6666666667%; }
+
+  .col-md-offset-7 {
+    margin-left: 58.3333333333%; }
+
+  .col-md-9,
+  .row.cols-md-9 > * {
+    max-width: 75%;
+    flex-basis: 75%; }
+
+  .col-md-offset-8 {
+    margin-left: 66.6666666667%; }
+
+  .col-md-10,
+  .row.cols-md-10 > * {
+    max-width: 83.3333333333%;
+    flex-basis: 83.3333333333%; }
+
+  .col-md-offset-9 {
+    margin-left: 75%; }
+
+  .col-md-11,
+  .row.cols-md-11 > * {
+    max-width: 91.6666666667%;
+    flex-basis: 91.6666666667%; }
+
+  .col-md-offset-10 {
+    margin-left: 83.3333333333%; }
+
+  .col-md-12,
+  .row.cols-md-12 > * {
+    max-width: 100%;
+    flex-basis: 100%; }
+
+  .col-md-offset-11 {
+    margin-left: 91.6666666667%; }
+
+  .col-md-normal {
+    order: initial; }
+
+  .col-md-first {
+    order: -999; }
+
+  .col-md-last {
+    order: 999; } }
+@media screen and (min-width: 1280px) {
+  .col-lg,
+  [class^='col-lg-'],
+  [class^='col-lg-offset-'],
+  .row[class*='cols-lg-'] > * {
+    box-sizing: border-box;
+    flex: 0 0 auto;
+    padding: 0 calc(var(--universal-padding) / 2); }
+
+  .col-lg,
+  .row.cols-lg > * {
+    max-width: 100%;
+    flex-grow: 1;
+    flex-basis: 0; }
+
+  .col-lg-1,
+  .row.cols-lg-1 > * {
+    max-width: 8.3333333333%;
+    flex-basis: 8.3333333333%; }
+
+  .col-lg-offset-0 {
+    margin-left: 0; }
+
+  .col-lg-2,
+  .row.cols-lg-2 > * {
+    max-width: 16.6666666667%;
+    flex-basis: 16.6666666667%; }
+
+  .col-lg-offset-1 {
+    margin-left: 8.3333333333%; }
+
+  .col-lg-3,
+  .row.cols-lg-3 > * {
+    max-width: 25%;
+    flex-basis: 25%; }
+
+  .col-lg-offset-2 {
+    margin-left: 16.6666666667%; }
+
+  .col-lg-4,
+  .row.cols-lg-4 > * {
+    max-width: 33.3333333333%;
+    flex-basis: 33.3333333333%; }
+
+  .col-lg-offset-3 {
+    margin-left: 25%; }
+
+  .col-lg-5,
+  .row.cols-lg-5 > * {
+    max-width: 41.6666666667%;
+    flex-basis: 41.6666666667%; }
+
+  .col-lg-offset-4 {
+    margin-left: 33.3333333333%; }
+
+  .col-lg-6,
+  .row.cols-lg-6 > * {
+    max-width: 50%;
+    flex-basis: 50%; }
+
+  .col-lg-offset-5 {
+    margin-left: 41.6666666667%; }
+
+  .col-lg-7,
+  .row.cols-lg-7 > * {
+    max-width: 58.3333333333%;
+    flex-basis: 58.3333333333%; }
+
+  .col-lg-offset-6 {
+    margin-left: 50%; }
+
+  .col-lg-8,
+  .row.cols-lg-8 > * {
+    max-width: 66.6666666667%;
+    flex-basis: 66.6666666667%; }
+
+  .col-lg-offset-7 {
+    margin-left: 58.3333333333%; }
+
+  .col-lg-9,
+  .row.cols-lg-9 > * {
+    max-width: 75%;
+    flex-basis: 75%; }
+
+  .col-lg-offset-8 {
+    margin-left: 66.6666666667%; }
+
+  .col-lg-10,
+  .row.cols-lg-10 > * {
+    max-width: 83.3333333333%;
+    flex-basis: 83.3333333333%; }
+
+  .col-lg-offset-9 {
+    margin-left: 75%; }
+
+  .col-lg-11,
+  .row.cols-lg-11 > * {
+    max-width: 91.6666666667%;
+    flex-basis: 91.6666666667%; }
+
+  .col-lg-offset-10 {
+    margin-left: 83.3333333333%; }
+
+  .col-lg-12,
+  .row.cols-lg-12 > * {
+    max-width: 100%;
+    flex-basis: 100%; }
+
+  .col-lg-offset-11 {
+    margin-left: 91.6666666667%; }
+
+  .col-lg-normal {
+    order: initial; }
+
+  .col-lg-first {
+    order: -999; }
+
+  .col-lg-last {
+    order: 999; } }
+/* Card component CSS variable definitions */
+:root {
+  --card-back-color: #f8f8f8;
+  --card-fore-color: #111;
+  --card-border-color: #ddd; }
+
+.card {
+  display: flex;
+  flex-direction: column;
+  justify-content: space-between;
+  align-self: center;
+  position: relative;
+  width: 100%;
+  background: var(--card-back-color);
+  color: var(--card-fore-color);
+  border: 0.0625rem solid var(--card-border-color);
+  border-radius: var(--universal-border-radius);
+  margin: var(--universal-margin);
+  overflow: hidden; }
+  @media screen and (min-width: 320px) {
+    .card {
+      max-width: 320px; } }
+  .card > .sectione {
+    background: var(--card-back-color);
+    color: var(--card-fore-color);
+    box-sizing: border-box;
+    margin: 0;
+    border: 0;
+    border-radius: 0;
+    border-bottom: 0.0625rem solid var(--card-border-color);
+    padding: var(--universal-padding);
+    width: 100%; }
+    .card > .sectione.media {
+      height: 200px;
+      padding: 0;
+      -o-object-fit: cover;
+      object-fit: cover; }
+  .card > .sectione:last-child {
+    border-bottom: 0; }
+
+/*
+  Custom elements for card elements.
+*/
+@media screen and (min-width: 240px) {
+  .card.small {
+    max-width: 240px; } }
+@media screen and (min-width: 480px) {
+  .card.large {
+    max-width: 480px; } }
+.card.fluid {
+  max-width: 100%;
+  width: auto; }
+
+.card.warning {
+/*  --card-back-color: #ffca28; */
+  --card-back-color: #e5b8b7;
+  --card-border-color: #e8b825; }
+
+.card.error {
+  --card-back-color: #b71c1c;
+  --card-fore-color: #f8f8f8;
+  --card-border-color: #a71a1a; }
+
+.card > .sectione.dark {
+  --card-back-color: #e0e0e0; }
+
+.card > .sectione.double-padded {
+  padding: calc(1.5 * var(--universal-padding)); }
+
+/*
+  Definitions for forms and input elements.
+*/
+/* Input_control module CSS variable definitions */
+:root {
+  --form-back-color: #f0f0f0;
+  --form-fore-color: #111;
+  --form-border-color: #ddd;
+  --input-back-color: #f8f8f8;
+  --input-fore-color: #111;
+  --input-border-color: #ddd;
+  --input-focus-color: #0288d1;
+  --input-invalid-color: #d32f2f;
+  --button-back-color: #e2e2e2;
+  --button-hover-back-color: #dcdcdc;
+  --button-fore-color: #212121;
+  --button-border-color: transparent;
+  --button-hover-border-color: transparent;
+  --button-group-border-color: rgba(124, 124, 124, 0.54); }
+
+form {
+  background: var(--form-back-color);
+  color: var(--form-fore-color);
+  border: 0.0625rem solid var(--form-border-color);
+  border-radius: var(--universal-border-radius);
+  margin: var(--universal-margin);
+  padding: calc(2 * var(--universal-padding)) var(--universal-padding); }
+
+fieldset {
+  border: 0.0625rem solid var(--form-border-color);
+  border-radius: var(--universal-border-radius);
+  margin: calc(var(--universal-margin) / 4);
+  padding: var(--universal-padding); }
+
+legend {
+  box-sizing: border-box;
+  display: table;
+  max-width: 100%;
+  white-space: normal;
+  font-weight: 700;
+  padding: calc(var(--universal-padding) / 2); }
+
+label {
+  padding: calc(var(--universal-padding) / 2) var(--universal-padding); }
+
+.input-group {
+  display: inline-block; }
+  .input-group.fluid {
+    display: flex;
+    align-items: center;
+    justify-content: center; }
+    .input-group.fluid > input {
+      max-width: 100%;
+      flex-grow: 1;
+      flex-basis: 0px; }
+    @media screen and (max-width: 499px) {
+      .input-group.fluid {
+        align-items: stretch;
+        flex-direction: column; } }
+  .input-group.vertical {
+    display: flex;
+    align-items: stretch;
+    flex-direction: column; }
+    .input-group.vertical > input {
+      max-width: 100%;
+      flex-grow: 1;
+      flex-basis: 0px; }
+
+[type="number"]::-webkit-inner-spin-button, [type="number"]::-webkit-outer-spin-button {
+  height: auto; }
+
+[type="search"] {
+  -webkit-appearance: textfield;
+  outline-offset: -2px; }
+
+[type="search"]::-webkit-search-cancel-button,
+[type="search"]::-webkit-search-decoration {
+  -webkit-appearance: none; }
+
+input:not([type]), [type="text"], [type="email"], [type="number"], [type="search"],
+[type="password"], [type="url"], [type="tel"], [type="checkbox"], [type="radio"], textarea, select {
+  box-sizing: border-box;
+  background: var(--input-back-color);
+  color: var(--input-fore-color);
+  border: 0.0625rem solid var(--input-border-color);
+  border-radius: var(--universal-border-radius);
+  margin: calc(var(--universal-margin) / 2);
+  padding: var(--universal-padding) calc(1.5 * var(--universal-padding)); }
+
+input:not([type="button"]):not([type="submit"]):not([type="reset"]):hover, input:not([type="button"]):not([type="submit"]):not([type="reset"]):focus, textarea:hover, textarea:focus, select:hover, select:focus {
+  border-color: var(--input-focus-color);
+  box-shadow: none; }
+input:not([type="button"]):not([type="submit"]):not([type="reset"]):invalid, input:not([type="button"]):not([type="submit"]):not([type="reset"]):focus:invalid, textarea:invalid, textarea:focus:invalid, select:invalid, select:focus:invalid {
+  border-color: var(--input-invalid-color);
+  box-shadow: none; }
+input:not([type="button"]):not([type="submit"]):not([type="reset"])[readonly], textarea[readonly], select[readonly] {
+  background: var(--secondary-back-color); }
+
+select {
+  max-width: 100%; }
+
+option {
+  overflow: hidden;
+  text-overflow: ellipsis; }
+
+[type="checkbox"], [type="radio"] {
+  -webkit-appearance: none;
+  -moz-appearance: none;
+  appearance: none;
+  position: relative;
+  height: calc(1rem + var(--universal-padding) / 2);
+  width: calc(1rem + var(--universal-padding) / 2);
+  vertical-align: text-bottom;
+  padding: 0;
+  flex-basis: calc(1rem + var(--universal-padding) / 2) !important;
+  flex-grow: 0 !important; }
+  [type="checkbox"]:checked:before, [type="radio"]:checked:before {
+    position: absolute; }
+
+[type="checkbox"]:checked:before {
+  content: '\2713';
+  font-family: sans-serif;
+  font-size: calc(1rem + var(--universal-padding) / 2);
+  top: calc(0rem - var(--universal-padding));
+  left: calc(var(--universal-padding) / 4); }
+
+[type="radio"] {
+  border-radius: 100%; }
+  [type="radio"]:checked:before {
+    border-radius: 100%;
+    content: '';
+    top: calc(0.0625rem + var(--universal-padding) / 2);
+    left: calc(0.0625rem + var(--universal-padding) / 2);
+    background: var(--input-fore-color);
+    width: 0.5rem;
+    height: 0.5rem; }
+
+:placeholder-shown {
+  color: var(--input-fore-color); }
+
+::-ms-placeholder {
+  color: var(--input-fore-color);
+  opacity: 0.54; }
+
+button::-moz-focus-inner, [type="button"]::-moz-focus-inner, [type="reset"]::-moz-focus-inner, [type="submit"]::-moz-focus-inner {
+  border-style: none;
+  padding: 0; }
+
+button, html [type="button"], [type="reset"], [type="submit"] {
+  -webkit-appearance: button; }
+
+button {
+  overflow: visible;
+  text-transform: none; }
+
+button, [type="button"], [type="submit"], [type="reset"],
+a.button, label.button, .button,
+a[role="button"], label[role="button"], [role="button"] {
+  display: inline-block;
+  background: var(--button-back-color);
+  color: var(--button-fore-color);
+  border: 0.0625rem solid var(--button-border-color);
+  border-radius: var(--universal-border-radius);
+  padding: var(--universal-padding) calc(1.5 * var(--universal-padding));
+  margin: var(--universal-margin);
+  text-decoration: none;
+  cursor: pointer;
+  transition: background 0.3s; }
+  button:hover, button:focus, [type="button"]:hover, [type="button"]:focus, [type="submit"]:hover, [type="submit"]:focus, [type="reset"]:hover, [type="reset"]:focus,
+  a.button:hover,
+  a.button:focus, label.button:hover, label.button:focus, .button:hover, .button:focus,
+  a[role="button"]:hover,
+  a[role="button"]:focus, label[role="button"]:hover, label[role="button"]:focus, [role="button"]:hover, [role="button"]:focus {
+    background: var(--button-hover-back-color);
+    border-color: var(--button-hover-border-color); }
+
+input:disabled, input[disabled], textarea:disabled, textarea[disabled], select:disabled, select[disabled], button:disabled, button[disabled], .button:disabled, .button[disabled], [role="button"]:disabled, [role="button"][disabled] {
+  cursor: not-allowed;
+  opacity: 0.75; }
+
+.button-group {
+  display: flex;
+  border: 0.0625rem solid var(--button-group-border-color);
+  border-radius: var(--universal-border-radius);
+  margin: var(--universal-margin); }
+  .button-group > button, .button-group [type="button"], .button-group > [type="submit"], .button-group > [type="reset"], .button-group > .button, .button-group > [role="button"] {
+    margin: 0;
+    max-width: 100%;
+    flex: 1 1 auto;
+    text-align: center;
+    border: 0;
+    border-radius: 0;
+    box-shadow: none; }
+  .button-group > :not(:first-child) {
+    border-left: 0.0625rem solid var(--button-group-border-color); }
+  @media screen and (max-width: 499px) {
+    .button-group {
+      flex-direction: column; }
+      .button-group > :not(:first-child) {
+        border: 0;
+        border-top: 0.0625rem solid var(--button-group-border-color); } }
+
+/*
+  Custom elements for forms and input elements.
+*/
+button.primary, [type="button"].primary, [type="submit"].primary, [type="reset"].primary, .button.primary, [role="button"].primary {
+  --button-back-color: #1976d2;
+  --button-fore-color: #f8f8f8; }
+  button.primary:hover, button.primary:focus, [type="button"].primary:hover, [type="button"].primary:focus, [type="submit"].primary:hover, [type="submit"].primary:focus, [type="reset"].primary:hover, [type="reset"].primary:focus, .button.primary:hover, .button.primary:focus, [role="button"].primary:hover, [role="button"].primary:focus {
+    --button-hover-back-color: #1565c0; }
+
+button.secondary, [type="button"].secondary, [type="submit"].secondary, [type="reset"].secondary, .button.secondary, [role="button"].secondary {
+  --button-back-color: #d32f2f;
+  --button-fore-color: #f8f8f8; }
+  button.secondary:hover, button.secondary:focus, [type="button"].secondary:hover, [type="button"].secondary:focus, [type="submit"].secondary:hover, [type="submit"].secondary:focus, [type="reset"].secondary:hover, [type="reset"].secondary:focus, .button.secondary:hover, .button.secondary:focus, [role="button"].secondary:hover, [role="button"].secondary:focus {
+    --button-hover-back-color: #c62828; }
+
+button.tertiary, [type="button"].tertiary, [type="submit"].tertiary, [type="reset"].tertiary, .button.tertiary, [role="button"].tertiary {
+  --button-back-color: #308732;
+  --button-fore-color: #f8f8f8; }
+  button.tertiary:hover, button.tertiary:focus, [type="button"].tertiary:hover, [type="button"].tertiary:focus, [type="submit"].tertiary:hover, [type="submit"].tertiary:focus, [type="reset"].tertiary:hover, [type="reset"].tertiary:focus, .button.tertiary:hover, .button.tertiary:focus, [role="button"].tertiary:hover, [role="button"].tertiary:focus {
+    --button-hover-back-color: #277529; }
+
+button.inverse, [type="button"].inverse, [type="submit"].inverse, [type="reset"].inverse, .button.inverse, [role="button"].inverse {
+  --button-back-color: #212121;
+  --button-fore-color: #f8f8f8; }
+  button.inverse:hover, button.inverse:focus, [type="button"].inverse:hover, [type="button"].inverse:focus, [type="submit"].inverse:hover, [type="submit"].inverse:focus, [type="reset"].inverse:hover, [type="reset"].inverse:focus, .button.inverse:hover, .button.inverse:focus, [role="button"].inverse:hover, [role="button"].inverse:focus {
+    --button-hover-back-color: #111; }
+
+button.small, [type="button"].small, [type="submit"].small, [type="reset"].small, .button.small, [role="button"].small {
+  padding: calc(0.5 * var(--universal-padding)) calc(0.75 * var(--universal-padding));
+  margin: var(--universal-margin); }
+
+button.large, [type="button"].large, [type="submit"].large, [type="reset"].large, .button.large, [role="button"].large {
+  padding: calc(1.5 * var(--universal-padding)) calc(2 * var(--universal-padding));
+  margin: var(--universal-margin); }
+
+/*
+  Definitions for navigation elements.
+*/
+/* Navigation module CSS variable definitions */
+:root {
+  --header-back-color: #f8f8f8;
+  --header-hover-back-color: #f0f0f0;
+  --header-fore-color: #444;
+  --header-border-color: #ddd;
+  --nav-back-color: #f8f8f8;
+  --nav-hover-back-color: #f0f0f0;
+  --nav-fore-color: #444;
+  --nav-border-color: #ddd;
+  --nav-link-color: #0277bd;
+  --footer-fore-color: #444;
+  --footer-back-color: #f8f8f8;
+  --footer-border-color: #ddd;
+  --footer-link-color: #0277bd;
+  --drawer-back-color: #f8f8f8;
+  --drawer-hover-back-color: #f0f0f0;
+  --drawer-border-color: #ddd;
+  --drawer-close-color: #444; }
+
+header {
+  height: 3.1875rem;
+  background: var(--header-back-color);
+  color: var(--header-fore-color);
+  border-bottom: 0.0625rem solid var(--header-border-color);
+  padding: calc(var(--universal-padding) / 4) 0;
+  white-space: nowrap;
+  overflow-x: auto;
+  overflow-y: hidden; }
+  header.row {
+    box-sizing: content-box; }
+  header .logo {
+    color: var(--header-fore-color);
+    font-size: 1.75rem;
+    padding: var(--universal-padding) calc(2 * var(--universal-padding));
+    text-decoration: none; }
+  header button, header [type="button"], header .button, header [role="button"] {
+    box-sizing: border-box;
+    position: relative;
+    top: calc(0rem - var(--universal-padding) / 4);
+    height: calc(3.1875rem + var(--universal-padding) / 2);
+    background: var(--header-back-color);
+    line-height: calc(3.1875rem - var(--universal-padding) * 1.5);
+    text-align: center;
+    color: var(--header-fore-color);
+    border: 0;
+    border-radius: 0;
+    margin: 0;
+    text-transform: uppercase; }
+    header button:hover, header button:focus, header [type="button"]:hover, header [type="button"]:focus, header .button:hover, header .button:focus, header [role="button"]:hover, header [role="button"]:focus {
+      background: var(--header-hover-back-color); }
+
+nav {
+  background: var(--nav-back-color);
+  color: var(--nav-fore-color);
+  border: 0.0625rem solid var(--nav-border-color);
+  border-radius: var(--universal-border-radius);
+  margin: var(--universal-margin); }
+  nav * {
+    padding: var(--universal-padding) calc(1.5 * var(--universal-padding)); }
+  nav a, nav a:visited {
+    display: block;
+    color: var(--nav-link-color);
+    border-radius: var(--universal-border-radius);
+    transition: background 0.3s; }
+    nav a:hover, nav a:focus, nav a:visited:hover, nav a:visited:focus {
+      text-decoration: none;
+      background: var(--nav-hover-back-color); }
+  nav .sublink-1 {
+    position: relative;
+    margin-left: calc(2 * var(--universal-padding)); }
+    nav .sublink-1:before {
+      position: absolute;
+      left: calc(var(--universal-padding) - 1 * var(--universal-padding));
+      top: -0.0625rem;
+      content: '';
+      height: 100%;
+      border: 0.0625rem solid var(--nav-border-color);
+      border-left: 0; }
+  nav .sublink-2 {
+    position: relative;
+    margin-left: calc(4 * var(--universal-padding)); }
+    nav .sublink-2:before {
+      position: absolute;
+      left: calc(var(--universal-padding) - 3 * var(--universal-padding));
+      top: -0.0625rem;
+      content: '';
+      height: 100%;
+      border: 0.0625rem solid var(--nav-border-color);
+      border-left: 0; }
+
+footer {
+  background: var(--footer-back-color);
+  color: var(--footer-fore-color);
+  border-top: 0.0625rem solid var(--footer-border-color);
+  padding: calc(2 * var(--universal-padding)) var(--universal-padding);
+  font-size: 0.875rem; }
+  footer a, footer a:visited {
+    color: var(--footer-link-color); }
+
+header.sticky {
+  position: -webkit-sticky;
+  position: sticky;
+  z-index: 1101;
+  top: 0; }
+
+footer.sticky {
+  position: -webkit-sticky;
+  position: sticky;
+  z-index: 1101;
+  bottom: 0; }
+
+.drawer-toggle:before {
+  display: inline-block;
+  position: relative;
+  vertical-align: bottom;
+  content: '\00a0\2261\00a0';
+  font-family: sans-serif;
+  font-size: 1.5em; }
+@media screen and (min-width: 500px) {
+  .drawer-toggle:not(.persistent) {
+    display: none; } }
+
+[type="checkbox"].drawer {
+  height: 1px;
+  width: 1px;
+  margin: -1px;
+  overflow: hidden;
+  position: absolute;
+  clip: rect(0 0 0 0);
+  -webkit-clip-path: inset(100%);
+  clip-path: inset(100%); }
+  [type="checkbox"].drawer + * {
+    display: block;
+    box-sizing: border-box;
+    position: fixed;
+    top: 0;
+    width: 320px;
+    height: 100vh;
+    overflow-y: auto;
+    background: var(--drawer-back-color);
+    border: 0.0625rem solid var(--drawer-border-color);
+    border-radius: 0;
+    margin: 0;
+    z-index: 1110;
+    right: -320px;
+    transition: right 0.3s; }
+    [type="checkbox"].drawer + * .drawer-close {
+      position: absolute;
+      top: var(--universal-margin);
+      right: var(--universal-margin);
+      z-index: 1111;
+      width: 2rem;
+      height: 2rem;
+      border-radius: var(--universal-border-radius);
+      padding: var(--universal-padding);
+      margin: 0;
+      cursor: pointer;
+      transition: background 0.3s; }
+      [type="checkbox"].drawer + * .drawer-close:before {
+        display: block;
+        content: '\00D7';
+        color: var(--drawer-close-color);
+        position: relative;
+        font-family: sans-serif;
+        font-size: 2rem;
+        line-height: 1;
+        text-align: center; }
+      [type="checkbox"].drawer + * .drawer-close:hover, [type="checkbox"].drawer + * .drawer-close:focus {
+        background: var(--drawer-hover-back-color); }
+    @media screen and (max-width: 320px) {
+      [type="checkbox"].drawer + * {
+        width: 100%; } }
+  [type="checkbox"].drawer:checked + * {
+    right: 0; }
+  @media screen and (min-width: 500px) {
+    [type="checkbox"].drawer:not(.persistent) + * {
+      position: static;
+      height: 100%;
+      z-index: 1100; }
+      [type="checkbox"].drawer:not(.persistent) + * .drawer-close {
+        display: none; } }
+
+/*
+  Definitions for the responsive table component.
+*/
+/* Table module CSS variable definitions. */
+:root {
+  --table-border-color: #aaa;
+  --table-border-separator-color: #666;
+  --table-head-back-color: #e6e6e6;
+  --table-head-fore-color: #111;
+  --table-body-back-color: #f8f8f8;
+  --table-body-fore-color: #111;
+  --table-body-alt-back-color: #eee; }
+
+table {
+  border-collapse: separate;
+  border-spacing: 0;
+  : margin: calc(1.5 * var(--universal-margin)) var(--universal-margin);
+  display: flex;
+  flex: 0 1 auto;
+  flex-flow: row wrap;
+  padding: var(--universal-padding);
+  padding-top: 0;
+	margin: calc(1.5 * var(--universal-margin)) var(--universal-margin);	}
+  table caption {
+    font-size: 1.25 * rem;
+    margin: calc(2 * var(--universal-margin)) 0;
+    max-width: 100%;
+    flex: 0 0 100%;
+		text-align: left;}
+  table thead, table tbody {
+    display: flex;
+    flex-flow: row wrap;
+    border: 0.0625rem solid var(--table-border-color); }
+  table thead {
+    z-index: 999;
+    border-radius: var(--universal-border-radius) var(--universal-border-radius) 0 0;
+    border-bottom: 0.0625rem solid var(--table-border-separator-color); }
+  table tbody {
+    border-top: 0;
+    margin-top: calc(0 - var(--universal-margin));
+    border-radius: 0 0 var(--universal-border-radius) var(--universal-border-radius); }
+  table tr {
+    display: flex;
+    padding: 0; }
+  table th, table td {
+    padding: calc(0.5 * var(--universal-padding));
+		font-size: 0.9rem; }
+  table th {
+    text-align: left;
+    background: var(--table-head-back-color);
+    color: var(--table-head-fore-color); }
+  table td {
+    background: var(--table-body-back-color);
+    color: var(--table-body-fore-color);
+    border-top: 0.0625rem solid var(--table-border-color); }
+
+table:not(.horizontal) {
+  overflow: auto;
+  max-height: 850px; }
+  table:not(.horizontal) thead, table:not(.horizontal) tbody {
+    max-width: 100%;
+    flex: 0 0 100%; }
+  table:not(.horizontal) tr {
+    flex-flow: row wrap;
+    flex: 0 0 100%; }
+  table:not(.horizontal) th, table:not(.horizontal) td {
+    flex: 1 0 0%;
+    overflow: hidden;
+    text-overflow: ellipsis; }
+  table:not(.horizontal) thead {
+    position: sticky;
+    top: 0; }
+  table:not(.horizontal) tbody tr:first-child td {
+    border-top: 0; }
+
+table.horizontal {
+  border: 0; }
+  table.horizontal thead, table.horizontal tbody {
+    border: 0;
+    flex-flow: row nowrap; }
+  table.horizontal tbody {
+    overflow: auto;
+    justify-content: space-between;
+    flex: 1 0 0;
+    margin-left: calc( 4 * var(--universal-margin));
+    padding-bottom: calc(var(--universal-padding) / 4); }
+  table.horizontal tr {
+    flex-direction: column;
+    flex: 1 0 auto; }
+  table.horizontal th, table.horizontal td {
+    width: 100%;
+    border: 0;
+    border-bottom: 0.0625rem solid var(--table-border-color); }
+    table.horizontal th:not(:first-child), table.horizontal td:not(:first-child) {
+      border-top: 0; }
+  table.horizontal th {
+    text-align: right;
+    border-left: 0.0625rem solid var(--table-border-color);
+    border-right: 0.0625rem solid var(--table-border-separator-color); }
+  table.horizontal thead tr:first-child {
+    padding-left: 0; }
+  table.horizontal th:first-child, table.horizontal td:first-child {
+    border-top: 0.0625rem solid var(--table-border-color); }
+  table.horizontal tbody tr:last-child td {
+    border-right: 0.0625rem solid var(--table-border-color); }
+    table.horizontal tbody tr:last-child td:first-child {
+      border-top-right-radius: 0.25rem; }
+    table.horizontal tbody tr:last-child td:last-child {
+      border-bottom-right-radius: 0.25rem; }
+  table.horizontal thead tr:first-child th:first-child {
+    border-top-left-radius: 0.25rem; }
+  table.horizontal thead tr:first-child th:last-child {
+    border-bottom-left-radius: 0.25rem; }
+
+@media screen and (max-width: 499px) {
+  table, table.horizontal {
+    border-collapse: collapse;
+    border: 0;
+    width: 100%;
+    display: table; }
+    table thead, table th, table.horizontal thead, table.horizontal th {
+      border: 0;
+      height: 1px;
+      width: 1px;
+      margin: -1px;
+      overflow: hidden;
+      padding: 0;
+      position: absolute;
+      clip: rect(0 0 0 0);
+      -webkit-clip-path: inset(100%);
+      clip-path: inset(100%); }
+    table tbody, table.horizontal tbody {
+      border: 0;
+      display: table-row-group; }
+    table tr, table.horizontal tr {
+      display: block;
+      border: 0.0625rem solid var(--table-border-color);
+      border-radius: var(--universal-border-radius);
+      background: #fafafa;
+      padding: var(--universal-padding);
+      margin: var(--universal-margin);
+      margin-bottom: calc(2 * var(--universal-margin)); }
+    table th, table td, table.horizontal th, table.horizontal td {
+      width: auto; }
+    table td, table.horizontal td {
+      display: block;
+      border: 0;
+      text-align: right; }
+    table td:before, table.horizontal td:before {
+      content: attr(data-label);
+      float: left;
+      font-weight: 600; }
+    table th:first-child, table td:first-child, table.horizontal th:first-child, table.horizontal td:first-child {
+      border-top: 0; }
+    table tbody tr:last-child td, table.horizontal tbody tr:last-child td {
+      border-right: 0; } }
+:root {
+  --table-body-alt-back-color: #eee; }
+
+table tr:nth-of-type(2n) > td {
+  background: var(--table-body-alt-back-color); }
+
+@media screen and (max-width: 500px) {
+  table tr:nth-of-type(2n) {
+    background: var(--table-body-alt-back-color); } }
+:root {
+  --table-body-hover-back-color: #90caf9; }
+
+table.hoverable tr:hover, table.hoverable tr:hover > td, table.hoverable tr:focus, table.hoverable tr:focus > td {
+  background: var(--table-body-hover-back-color); }
+
+@media screen and (max-width: 500px) {
+  table.hoverable tr:hover, table.hoverable tr:hover > td, table.hoverable tr:focus, table.hoverable tr:focus > td {
+    background: var(--table-body-hover-back-color); } }
+/*
+  Definitions for contextual background elements, toasts and tooltips.
+*/
+/* Contextual module CSS variable definitions */
+:root {
+  --mark-back-color: #0277bd;
+  --mark-fore-color: #fafafa; }
+
+mark {
+  background: var(--mark-back-color);
+  color: var(--mark-fore-color);
+  font-size: 0.95em;
+  line-height: 1em;
+  border-radius: var(--universal-border-radius);
+  padding: calc(var(--universal-padding) / 4) calc(var(--universal-padding) / 2); }
+  mark.inline-block {
+    display: inline-block;
+    font-size: 1em;
+    line-height: 1.5;
+    padding: calc(var(--universal-padding) / 2) var(--universal-padding); }
+
+:root {
+  --toast-back-color: #424242;
+  --toast-fore-color: #fafafa; }
+
+.toast {
+  position: fixed;
+  bottom: calc(var(--universal-margin) * 3);
+  left: 50%;
+  transform: translate(-50%, -50%);
+  z-index: 1111;
+  color: var(--toast-fore-color);
+  background: var(--toast-back-color);
+  border-radius: calc(var(--universal-border-radius) * 16);
+  padding: var(--universal-padding) calc(var(--universal-padding) * 3); }
+
+:root {
+  --tooltip-back-color: #212121;
+  --tooltip-fore-color: #fafafa; }
+
+.tooltip {
+  position: relative;
+  display: inline-block; }
+  .tooltip:before, .tooltip:after {
+    position: absolute;
+    opacity: 0;
+    clip: rect(0 0 0 0);
+    -webkit-clip-path: inset(100%);
+    clip-path: inset(100%);
+    transition: all 0.3s;
+    z-index: 1010;
+    left: 50%; }
+  .tooltip:not(.bottom):before, .tooltip:not(.bottom):after {
+    bottom: 75%; }
+  .tooltip.bottom:before, .tooltip.bottom:after {
+    top: 75%; }
+  .tooltip:hover:before, .tooltip:hover:after, .tooltip:focus:before, .tooltip:focus:after {
+    opacity: 1;
+    clip: auto;
+    -webkit-clip-path: inset(0%);
+    clip-path: inset(0%); }
+  .tooltip:before {
+    content: '';
+    background: transparent;
+    border: var(--universal-margin) solid transparent;
+    left: calc(50% - var(--universal-margin)); }
+  .tooltip:not(.bottom):before {
+    border-top-color: #212121; }
+  .tooltip.bottom:before {
+    border-bottom-color: #212121; }
+  .tooltip:after {
+    content: attr(aria-label);
+    color: var(--tooltip-fore-color);
+    background: var(--tooltip-back-color);
+    border-radius: var(--universal-border-radius);
+    padding: var(--universal-padding);
+    white-space: nowrap;
+    transform: translateX(-50%); }
+  .tooltip:not(.bottom):after {
+    margin-bottom: calc(2 * var(--universal-margin)); }
+  .tooltip.bottom:after {
+    margin-top: calc(2 * var(--universal-margin)); }
+
+:root {
+  --modal-overlay-color: rgba(0, 0, 0, 0.45);
+  --modal-close-color: #444;
+  --modal-close-hover-color: #f0f0f0; }
+
+[type="checkbox"].modal {
+  height: 1px;
+  width: 1px;
+  margin: -1px;
+  overflow: hidden;
+  position: absolute;
+  clip: rect(0 0 0 0);
+  -webkit-clip-path: inset(100%);
+  clip-path: inset(100%); }
+  [type="checkbox"].modal + div {
+    position: fixed;
+    top: 0;
+    left: 0;
+    display: none;
+    width: 100vw;
+    height: 100vh;
+    background: var(--modal-overlay-color); }
+    [type="checkbox"].modal + div .card {
+      margin: 0 auto;
+      max-height: 50vh;
+      overflow: auto; }
+      [type="checkbox"].modal + div .card .modal-close {
+        position: absolute;
+        top: 0;
+        right: 0;
+        width: 1.75rem;
+        height: 1.75rem;
+        border-radius: var(--universal-border-radius);
+        padding: var(--universal-padding);
+        margin: 0;
+        cursor: pointer;
+        transition: background 0.3s; }
+        [type="checkbox"].modal + div .card .modal-close:before {
+          display: block;
+          content: '\00D7';
+          color: var(--modal-close-color);
+          position: relative;
+          font-family: sans-serif;
+          font-size: 1.75rem;
+          line-height: 1;
+          text-align: center; }
+        [type="checkbox"].modal + div .card .modal-close:hover, [type="checkbox"].modal + div .card .modal-close:focus {
+          background: var(--modal-close-hover-color); }
+  [type="checkbox"].modal:checked + div {
+    display: flex;
+    flex: 0 1 auto;
+    z-index: 1200; }
+    [type="checkbox"].modal:checked + div .card .modal-close {
+      z-index: 1211; }
+
+:root {
+  --collapse-label-back-color: #e8e8e8;
+  --collapse-label-fore-color: #212121;
+  --collapse-label-hover-back-color: #f0f0f0;
+  --collapse-selected-label-back-color: #ececec;
+  --collapse-border-color: #ddd;
+  --collapse-content-back-color: #fafafa;
+  --collapse-selected-label-border-color: #0277bd; }
+
+.collapse {
+  width: calc(100% - 2 * var(--universal-margin));
+  opacity: 1;
+  display: flex;
+  flex-direction: column;
+  margin: var(--universal-margin);
+  border-radius: var(--universal-border-radius); }
+  .collapse > [type="radio"], .collapse > [type="checkbox"] {
+    height: 1px;
+    width: 1px;
+    margin: -1px;
+    overflow: hidden;
+    position: absolute;
+    clip: rect(0 0 0 0);
+    -webkit-clip-path: inset(100%);
+    clip-path: inset(100%); }
+  .collapse > label {
+    flex-grow: 1;
+    display: inline-block;
+    height: 1.5rem;
+    cursor: pointer;
+    transition: background 0.3s;
+    color: var(--collapse-label-fore-color);
+    background: var(--collapse-label-back-color);
+    border: 0.0625rem solid var(--collapse-border-color);
+    padding: calc(1.5 * var(--universal-padding)); }
+    .collapse > label:hover, .collapse > label:focus {
+      background: var(--collapse-label-hover-back-color); }
+    .collapse > label + div {
+      flex-basis: auto;
+      height: 1px;
+      width: 1px;
+      margin: -1px;
+      overflow: hidden;
+      position: absolute;
+      clip: rect(0 0 0 0);
+      -webkit-clip-path: inset(100%);
+      clip-path: inset(100%);
+      transition: max-height 0.3s;
+      max-height: 1px; }
+  .collapse > :checked + label {
+    background: var(--collapse-selected-label-back-color);
+    border-bottom-color: var(--collapse-selected-label-border-color); }
+    .collapse > :checked + label + div {
+      box-sizing: border-box;
+      position: relative;
+      width: 100%;
+      height: auto;
+      overflow: auto;
+      margin: 0;
+      background: var(--collapse-content-back-color);
+      border: 0.0625rem solid var(--collapse-border-color);
+      border-top: 0;
+      padding: var(--universal-padding);
+      clip: auto;
+      -webkit-clip-path: inset(0%);
+      clip-path: inset(0%);
+      max-height: 850px; }
+  .collapse > label:not(:first-of-type) {
+    border-top: 0; }
+  .collapse > label:first-of-type {
+    border-radius: var(--universal-border-radius) var(--universal-border-radius) 0 0; }
+  .collapse > label:last-of-type:not(:first-of-type) {
+    border-radius: 0 0 var(--universal-border-radius) var(--universal-border-radius); }
+  .collapse > label:last-of-type:first-of-type {
+    border-radius: var(--universal-border-radius); }
+  .collapse > :checked:last-of-type:not(:first-of-type) + label {
+    border-radius: 0; }
+  .collapse > :checked:last-of-type + label + div {
+    border-radius: 0 0 var(--universal-border-radius) var(--universal-border-radius); }
+
+/*
+  Custom elements for contextual background elements, toasts and tooltips.
+*/
+mark.secondary {
+  --mark-back-color: #d32f2f; }
+
+mark.tertiary {
+  --mark-back-color: #308732; }
+
+mark.tag {
+  padding: calc(var(--universal-padding)/2) var(--universal-padding);
+  border-radius: 1em; }
+
+/*
+  Definitions for progress elements and spinners.
+*/
+/* Progess module CSS variable definitions */
+:root {
+  --progress-back-color: #ddd;
+  --progress-fore-color: #555; }
+
+progress {
+  display: block;
+  vertical-align: baseline;
+  -webkit-appearance: none;
+  -moz-appearance: none;
+  appearance: none;
+  height: 0.75rem;
+  width: calc(100% - 2 * var(--universal-margin));
+  margin: var(--universal-margin);
+  border: 0;
+  border-radius: calc(2 * var(--universal-border-radius));
+  background: var(--progress-back-color);
+  color: var(--progress-fore-color); }
+  progress::-webkit-progress-value {
+    background: var(--progress-fore-color);
+    border-top-left-radius: calc(2 * var(--universal-border-radius));
+    border-bottom-left-radius: calc(2 * var(--universal-border-radius)); }
+  progress::-webkit-progress-bar {
+    background: var(--progress-back-color); }
+  progress::-moz-progress-bar {
+    background: var(--progress-fore-color);
+    border-top-left-radius: calc(2 * var(--universal-border-radius));
+    border-bottom-left-radius: calc(2 * var(--universal-border-radius)); }
+  progress[value="1000"]::-webkit-progress-value {
+    border-radius: calc(2 * var(--universal-border-radius)); }
+  progress[value="1000"]::-moz-progress-bar {
+    border-radius: calc(2 * var(--universal-border-radius)); }
+  progress.inline {
+    display: inline-block;
+    vertical-align: middle;
+    width: 60%; }
+
+:root {
+  --spinner-back-color: #ddd;
+  --spinner-fore-color: #555; }
+
+@keyframes spinner-donut-anim {
+  0% {
+    transform: rotate(0deg); }
+  100% {
+    transform: rotate(360deg); } }
+.spinner {
+  display: inline-block;
+  margin: var(--universal-margin);
+  border: 0.25rem solid var(--spinner-back-color);
+  border-left: 0.25rem solid var(--spinner-fore-color);
+  border-radius: 50%;
+  width: 1.25rem;
+  height: 1.25rem;
+  animation: spinner-donut-anim 1.2s linear infinite; }
+
+/*
+  Custom elements for progress bars and spinners.
+*/
+progress.primary {
+  --progress-fore-color: #1976d2; }
+
+progress.secondary {
+  --progress-fore-color: #d32f2f; }
+
+progress.tertiary {
+  --progress-fore-color: #308732; }
+
+.spinner.primary {
+  --spinner-fore-color: #1976d2; }
+
+.spinner.secondary {
+  --spinner-fore-color: #d32f2f; }
+
+.spinner.tertiary {
+  --spinner-fore-color: #308732; }
+
+/*
+  Definitions for icons - powered by Feather (https://feathericons.com/).
+*/
+span[class^='icon-'] {
+  display: inline-block;
+  height: 1em;
+  width: 1em;
+  vertical-align: -0.125em;
+  background-size: contain;
+  margin: 0 calc(var(--universal-margin) / 4); }
+  span[class^='icon-'].secondary {
+    -webkit-filter: invert(25%);
+    filter: invert(25%); }
+  span[class^='icon-'].inverse {
+    -webkit-filter: invert(100%);
+    filter: invert(100%); }
+
+span.icon-alert {
+  background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='12' cy='12' r='10'%3E%3C/circle%3E%3Cline x1='12' y1='8' x2='12' y2='12'%3E%3C/line%3E%3Cline x1='12' y1='16' x2='12' y2='16'%3E%3C/line%3E%3C/svg%3E"); }
+span.icon-bookmark {
+  background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M19 21l-7-5-7 5V5a2 2 0 0 1 2-2h10a2 2 0 0 1 2 2z'%3E%3C/path%3E%3C/svg%3E"); }
+span.icon-calendar {
+  background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Crect x='3' y='4' width='18' height='18' rx='2' ry='2'%3E%3C/rect%3E%3Cline x1='16' y1='2' x2='16' y2='6'%3E%3C/line%3E%3Cline x1='8' y1='2' x2='8' y2='6'%3E%3C/line%3E%3Cline x1='3' y1='10' x2='21' y2='10'%3E%3C/line%3E%3C/svg%3E"); }
+span.icon-credit {
+  background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Crect x='1' y='4' width='22' height='16' rx='2' ry='2'%3E%3C/rect%3E%3Cline x1='1' y1='10' x2='23' y2='10'%3E%3C/line%3E%3C/svg%3E"); }
+span.icon-edit {
+  background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M20 14.66V20a2 2 0 0 1-2 2H4a2 2 0 0 1-2-2V6a2 2 0 0 1 2-2h5.34'%3E%3C/path%3E%3Cpolygon points='18 2 22 6 12 16 8 16 8 12 18 2'%3E%3C/polygon%3E%3C/svg%3E"); }
+span.icon-link {
+  background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M18 13v6a2 2 0 0 1-2 2H5a2 2 0 0 1-2-2V8a2 2 0 0 1 2-2h6'%3E%3C/path%3E%3Cpolyline points='15 3 21 3 21 9'%3E%3C/polyline%3E%3Cline x1='10' y1='14' x2='21' y2='3'%3E%3C/line%3E%3C/svg%3E"); }
+span.icon-help {
+  background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M9.09 9a3 3 0 0 1 5.83 1c0 2-3 3-3 3'%3E%3C/path%3E%3Ccircle cx='12' cy='12' r='10'%3E%3C/circle%3E%3Cline x1='12' y1='17' x2='12' y2='17'%3E%3C/line%3E%3C/svg%3E"); }
+span.icon-home {
+  background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M3 9l9-7 9 7v11a2 2 0 0 1-2 2H5a2 2 0 0 1-2-2z'%3E%3C/path%3E%3Cpolyline points='9 22 9 12 15 12 15 22'%3E%3C/polyline%3E%3C/svg%3E"); }
+span.icon-info {
+  background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='12' cy='12' r='10'%3E%3C/circle%3E%3Cline x1='12' y1='16' x2='12' y2='12'%3E%3C/line%3E%3Cline x1='12' y1='8' x2='12' y2='8'%3E%3C/line%3E%3C/svg%3E"); }
+span.icon-lock {
+  background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Crect x='3' y='11' width='18' height='11' rx='2' ry='2'%3E%3C/rect%3E%3Cpath d='M7 11V7a5 5 0 0 1 10 0v4'%3E%3C/path%3E%3C/svg%3E"); }
+span.icon-mail {
+  background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M4 4h16c1.1 0 2 .9 2 2v12c0 1.1-.9 2-2 2H4c-1.1 0-2-.9-2-2V6c0-1.1.9-2 2-2z'%3E%3C/path%3E%3Cpolyline points='22,6 12,13 2,6'%3E%3C/polyline%3E%3C/svg%3E"); }
+span.icon-location {
+  background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M21 10c0 7-9 13-9 13s-9-6-9-13a9 9 0 0 1 18 0z'%3E%3C/path%3E%3Ccircle cx='12' cy='10' r='3'%3E%3C/circle%3E%3C/svg%3E"); }
+span.icon-phone {
+  background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M22 16.92v3a2 2 0 0 1-2.18 2 19.79 19.79 0 0 1-8.63-3.07 19.5 19.5 0 0 1-6-6 19.79 19.79 0 0 1-3.07-8.67A2 2 0 0 1 4.11 2h3a2 2 0 0 1 2 1.72 12.84 12.84 0 0 0 .7 2.81 2 2 0 0 1-.45 2.11L8.09 9.91a16 16 0 0 0 6 6l1.27-1.27a2 2 0 0 1 2.11-.45 12.84 12.84 0 0 0 2.81.7A2 2 0 0 1 22 16.92z'%3E%3C/path%3E%3C/svg%3E"); }
+span.icon-rss {
+  background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M4 11a9 9 0 0 1 9 9'%3E%3C/path%3E%3Cpath d='M4 4a16 16 0 0 1 16 16'%3E%3C/path%3E%3Ccircle cx='5' cy='19' r='1'%3E%3C/circle%3E%3C/svg%3E"); }
+span.icon-search {
+  background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='11' cy='11' r='8'%3E%3C/circle%3E%3Cline x1='21' y1='21' x2='16.65' y2='16.65'%3E%3C/line%3E%3C/svg%3E"); }
+span.icon-settings {
+  background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='12' cy='12' r='3'%3E%3C/circle%3E%3Cpath d='M19.4 15a1.65 1.65 0 0 0 .33 1.82l.06.06a2 2 0 0 1 0 2.83 2 2 0 0 1-2.83 0l-.06-.06a1.65 1.65 0 0 0-1.82-.33 1.65 1.65 0 0 0-1 1.51V21a2 2 0 0 1-2 2 2 2 0 0 1-2-2v-.09A1.65 1.65 0 0 0 9 19.4a1.65 1.65 0 0 0-1.82.33l-.06.06a2 2 0 0 1-2.83 0 2 2 0 0 1 0-2.83l.06-.06a1.65 1.65 0 0 0 .33-1.82 1.65 1.65 0 0 0-1.51-1H3a2 2 0 0 1-2-2 2 2 0 0 1 2-2h.09A1.65 1.65 0 0 0 4.6 9a1.65 1.65 0 0 0-.33-1.82l-.06-.06a2 2 0 0 1 0-2.83 2 2 0 0 1 2.83 0l.06.06a1.65 1.65 0 0 0 1.82.33H9a1.65 1.65 0 0 0 1-1.51V3a2 2 0 0 1 2-2 2 2 0 0 1 2 2v.09a1.65 1.65 0 0 0 1 1.51 1.65 1.65 0 0 0 1.82-.33l.06-.06a2 2 0 0 1 2.83 0 2 2 0 0 1 0 2.83l-.06.06a1.65 1.65 0 0 0-.33 1.82V9a1.65 1.65 0 0 0 1.51 1H21a2 2 0 0 1 2 2 2 2 0 0 1-2 2h-.09a1.65 1.65 0 0 0-1.51 1z'%3E%3C/path%3E%3C/svg%3E"); }
+span.icon-share {
+  background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='18' cy='5' r='3'%3E%3C/circle%3E%3Ccircle cx='6' cy='12' r='3'%3E%3C/circle%3E%3Ccircle cx='18' cy='19' r='3'%3E%3C/circle%3E%3Cline x1='8.59' y1='13.51' x2='15.42' y2='17.49'%3E%3C/line%3E%3Cline x1='15.41' y1='6.51' x2='8.59' y2='10.49'%3E%3C/line%3E%3C/svg%3E"); }
+span.icon-cart {
+  background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='9' cy='21' r='1'%3E%3C/circle%3E%3Ccircle cx='20' cy='21' r='1'%3E%3C/circle%3E%3Cpath d='M1 1h4l2.68 13.39a2 2 0 0 0 2 1.61h9.72a2 2 0 0 0 2-1.61L23 6H6'%3E%3C/path%3E%3C/svg%3E"); }
+span.icon-upload {
+  background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M21 15v4a2 2 0 0 1-2 2H5a2 2 0 0 1-2-2v-4'%3E%3C/path%3E%3Cpolyline points='17 8 12 3 7 8'%3E%3C/polyline%3E%3Cline x1='12' y1='3' x2='12' y2='15'%3E%3C/line%3E%3C/svg%3E"); }
+span.icon-user {
+  background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M20 21v-2a4 4 0 0 0-4-4H8a4 4 0 0 0-4 4v2'%3E%3C/path%3E%3Ccircle cx='12' cy='7' r='4'%3E%3C/circle%3E%3C/svg%3E"); }
+
+/*
+  Definitions for utilities and helper classes.
+*/
+/* Utility module CSS variable definitions */
+:root {
+  --generic-border-color: rgba(0, 0, 0, 0.3);
+  --generic-box-shadow: 0 0.25rem 0.25rem 0 rgba(0, 0, 0, 0.125), 0 0.125rem 0.125rem -0.125rem rgba(0, 0, 0, 0.25); }
+
+.hidden {
+  display: none !important; }
+
+.visually-hidden {
+  position: absolute !important;
+  width: 1px !important;
+  height: 1px !important;
+  margin: -1px !important;
+  border: 0 !important;
+  padding: 0 !important;
+  clip: rect(0 0 0 0) !important;
+  -webkit-clip-path: inset(100%) !important;
+  clip-path: inset(100%) !important;
+  overflow: hidden !important; }
+
+.bordered {
+  border: 0.0625rem solid var(--generic-border-color) !important; }
+
+.rounded {
+  border-radius: var(--universal-border-radius) !important; }
+
+.circular {
+  border-radius: 50% !important; }
+
+.shadowed {
+  box-shadow: var(--generic-box-shadow) !important; }
+
+.responsive-margin {
+  margin: calc(var(--universal-margin) / 4) !important; }
+  @media screen and (min-width: 500px) {
+    .responsive-margin {
+      margin: calc(var(--universal-margin) / 2) !important; } }
+  @media screen and (min-width: 1280px) {
+    .responsive-margin {
+      margin: var(--universal-margin) !important; } }
+
+.responsive-padding {
+  padding: calc(var(--universal-padding) / 4) !important; }
+  @media screen and (min-width: 500px) {
+    .responsive-padding {
+      padding: calc(var(--universal-padding) / 2) !important; } }
+  @media screen and (min-width: 1280px) {
+    .responsive-padding {
+      padding: var(--universal-padding) !important; } }
+
+@media screen and (max-width: 499px) {
+  .hidden-sm {
+    display: none !important; } }
+@media screen and (min-width: 500px) and (max-width: 1279px) {
+  .hidden-md {
+    display: none !important; } }
+@media screen and (min-width: 1280px) {
+  .hidden-lg {
+    display: none !important; } }
+@media screen and (max-width: 499px) {
+  .visually-hidden-sm {
+    position: absolute !important;
+    width: 1px !important;
+    height: 1px !important;
+    margin: -1px !important;
+    border: 0 !important;
+    padding: 0 !important;
+    clip: rect(0 0 0 0) !important;
+    -webkit-clip-path: inset(100%) !important;
+    clip-path: inset(100%) !important;
+    overflow: hidden !important; } }
+@media screen and (min-width: 500px) and (max-width: 1279px) {
+  .visually-hidden-md {
+    position: absolute !important;
+    width: 1px !important;
+    height: 1px !important;
+    margin: -1px !important;
+    border: 0 !important;
+    padding: 0 !important;
+    clip: rect(0 0 0 0) !important;
+    -webkit-clip-path: inset(100%) !important;
+    clip-path: inset(100%) !important;
+    overflow: hidden !important; } }
+@media screen and (min-width: 1280px) {
+  .visually-hidden-lg {
+    position: absolute !important;
+    width: 1px !important;
+    height: 1px !important;
+    margin: -1px !important;
+    border: 0 !important;
+    padding: 0 !important;
+    clip: rect(0 0 0 0) !important;
+    -webkit-clip-path: inset(100%) !important;
+    clip-path: inset(100%) !important;
+    overflow: hidden !important; } }
+
+/*# sourceMappingURL=mini-default.css.map */
diff --git a/Drivers/BSP/Components/ft6x06/_htmresc/st_logo.png b/Drivers/BSP/Components/ft6x06/_htmresc/st_logo.png
new file mode 100644
index 0000000..8b80057
Binary files /dev/null and b/Drivers/BSP/Components/ft6x06/_htmresc/st_logo.png differ
diff --git a/Drivers/BSP/Components/ft6x06/ft6x06.c b/Drivers/BSP/Components/ft6x06/ft6x06.c
new file mode 100644
index 0000000..9321cd6
--- /dev/null
+++ b/Drivers/BSP/Components/ft6x06/ft6x06.c
@@ -0,0 +1,496 @@
+/**
+  ******************************************************************************
+  * @file    ft6x06.c
+  * @author  MCD Application Team
+  * @brief   This file provides a set of functions needed to manage the FT6X06
+  *          IO Expander devices.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "ft6x06.h"
+
+/** @addtogroup BSP
+  * @{
+  */
+
+/** @addtogroup Component
+  * @{
+  */
+
+/** @defgroup FT6XX6
+  * @{
+  */
+
+/* Private typedef -----------------------------------------------------------*/
+
+/** @defgroup FT6XX6_Private_Defines FT6XX6 Private Defines
+  * @{
+  */
+#define FT6x06_MAX_INSTANCE  2
+/**
+  * @}
+  */
+
+/* Private macro -------------------------------------------------------------*/
+
+/** @defgroup FT6XX6_Private_Variables FT6XX6 Private Variables
+  * @{
+  */
+
+/* Touch screen driver structure initialization */
+TS_DrvTypeDef ft6x06_ts_drv =
+{
+  ft6x06_Init,
+  ft6x06_ReadID,
+  ft6x06_Reset,
+
+  ft6x06_TS_Start,
+  ft6x06_TS_DetectTouch,
+  ft6x06_TS_GetXY,
+
+  ft6x06_TS_EnableIT,
+  ft6x06_TS_ClearIT,
+  ft6x06_TS_ITStatus,
+  ft6x06_TS_DisableIT
+};
+
+/* ft6xx6 instances by address */
+uint8_t ft6x06[FT6x06_MAX_INSTANCE] = {0};
+
+/* Global ft6xx6 handle */
+static ft6x06_handle_TypeDef ft6x06_handle = { FT6206_I2C_NOT_INITIALIZED, 0, 0};
+
+/**
+  * @}
+  */
+
+/** @defgroup ft6xx6_Private_Function_Prototypes ft6xx6 Private Function Prototypes
+  * @{
+  */
+static uint8_t ft6x06_GetInstance(uint16_t DeviceAddr);
+/* Private functions prototypes-----------------------------------------------*/
+#if (TS_AUTO_CALIBRATION_SUPPORTED == 1)
+/**
+  * @brief  Start TouchScreen calibration phase
+  * @param  DeviceAddr: FT6xx6 Device address for communication on I2C Bus.
+  * @retval Status FT6206_STATUS_OK or FT6206_STATUS_NOT_OK.
+  */
+static uint32_t ft6x06_TS_Calibration(uint16_t DeviceAddr);
+#endif /* TS_AUTO_CALIBRATION_SUPPORTED == 1 */
+
+/**
+  * @brief  Basic static configuration of TouchScreen
+  * @param  DeviceAddr: FT6xx6 Device address for communication on I2C Bus.
+  * @retval Status FT6206_STATUS_OK or FT6206_STATUS_NOT_OK.
+  */
+static uint32_t ft6x06_TS_Configure(uint16_t DeviceAddr);
+
+/**
+  * @}
+  */
+
+/** @defgroup ft6xx6_Private_Functions ft6xx6 Private Functions
+  * @{
+  */
+
+/**
+  * @brief  Initialize the ft6xx6 communication bus
+  *         from MCU to FT6xx6 : ie I2C channel initialization (if required).
+  * @param  DeviceAddr: Device address on communication Bus (I2C slave address of FT6xx6).
+  * @retval None
+  */
+void ft6x06_Init(uint16_t DeviceAddr)
+{  
+  uint8_t instance;
+  uint8_t empty;
+  
+  /* Check if device instance already exists */
+  instance = ft6x06_GetInstance(DeviceAddr);
+  
+  /* To prevent double initialization */
+  if(instance == 0xFF)
+  {
+    /* Look for empty instance */
+    empty = ft6x06_GetInstance(0);
+    
+    if(empty < FT6x06_MAX_INSTANCE)
+    {
+      /* Register the current device instance */
+      ft6x06[empty] = DeviceAddr;
+      
+      /* Initialize IO BUS layer */
+      TS_IO_Init(); 
+    }
+  }
+}
+
+/**
+  * @brief  Software Reset the ft6xx6.
+  *         @note : Not applicable to FT6xx6.
+  * @param  DeviceAddr: Device address on communication Bus (I2C slave address of FT6xx6).
+  * @retval None
+  */
+void ft6x06_Reset(uint16_t DeviceAddr)
+{
+  /* Do nothing */
+  /* No software reset sequence available in FT6xx6 IC */
+}
+
+/**
+  * @brief  Read the ft6xx6 device ID, pre initialize I2C in case of need to be
+  *         able to read the FT6xx6 device ID, and verify this is a FT6xx6.
+  * @param  DeviceAddr: I2C FT6xx6 Slave address.
+  * @retval The Device ID (two bytes).
+  */
+uint16_t ft6x06_ReadID(uint16_t DeviceAddr)
+{
+  /* Initialize I2C link if needed */
+  TS_IO_Init();
+  
+  /* Return the device ID value */
+  return (TS_IO_Read(DeviceAddr, FT6206_CHIP_ID_REG));
+}
+
+/**
+  * @brief  Configures the touch Screen IC device to start detecting touches
+  *         It goes through an internal calibration process (Hw calibration sequence of
+  *         the touch screen).
+  * @param  DeviceAddr: Device address on communication Bus (I2C slave address).
+  * @retval None.
+  */
+void ft6x06_TS_Start(uint16_t DeviceAddr)
+{
+#if (TS_AUTO_CALIBRATION_SUPPORTED == 1)
+  /* Hw Calibration sequence start : should be done once after each power up */
+  /* This is called internal calibration of the touch screen                 */
+  ft6x06_TS_Calibration(DeviceAddr);
+#endif
+  /* Minimum static configuration of FT6xx6 */
+  ft6x06_TS_Configure(DeviceAddr);
+
+  /* By default set FT6xx6 IC in Polling mode : no INT generation on FT6xx6 for new touch available */
+  /* Note TS_INT is active low                                                                      */
+  ft6x06_TS_DisableIT(DeviceAddr);
+}
+
+/**
+  * @brief  Return if there is touches detected or not.
+  *         Try to detect new touches and forget the old ones (reset internal global
+  *         variables).
+  * @param  DeviceAddr: Device address on communication Bus.
+  * @retval : Number of active touches detected (can be 0, 1 or 2).
+  */
+uint8_t ft6x06_TS_DetectTouch(uint16_t DeviceAddr)
+{
+  volatile uint8_t nbTouch = 0;
+
+  /* Read register FT6206_TD_STAT_REG to check number of touches detection */
+  nbTouch = TS_IO_Read(DeviceAddr, FT6206_TD_STAT_REG);
+  nbTouch &= FT6206_TD_STAT_MASK;
+
+  if(nbTouch > FT6206_MAX_DETECTABLE_TOUCH)
+  {
+    /* If invalid number of touch detected, set it to zero */
+    nbTouch = 0;
+  }
+
+  /* Update ft6xx6 driver internal global : current number of active touches */
+  ft6x06_handle.currActiveTouchNb = nbTouch;
+
+  /* Reset current active touch index on which to work on */
+  ft6x06_handle.currActiveTouchIdx = 0;
+
+  return(nbTouch);
+}
+
+/**
+  * @brief  Get the touch screen X and Y positions values
+  *         Manage multi touch thanks to touch Index global
+  *         variable 'ft6x06_handle.currActiveTouchIdx'.
+  * @param  DeviceAddr: Device address on communication Bus.
+  * @param  X: Pointer to X position value
+  * @param  Y: Pointer to Y position value
+  * @retval None.
+  */
+void ft6x06_TS_GetXY(uint16_t DeviceAddr, uint16_t *X, uint16_t *Y)
+{
+  uint8_t regAddress = 0;
+  uint8_t  dataxy[4];
+  
+  if(ft6x06_handle.currActiveTouchIdx < ft6x06_handle.currActiveTouchNb)
+  {
+    switch(ft6x06_handle.currActiveTouchIdx)
+    {
+    case 0 :    
+      regAddress = FT6206_P1_XH_REG; 
+      break;
+    case 1 :
+      regAddress = FT6206_P2_XH_REG; 
+      break;
+
+    default :
+      break;
+    }
+    
+    /* Read X and Y positions */
+    TS_IO_ReadMultiple(DeviceAddr, regAddress, dataxy, sizeof(dataxy)); 
+
+    /* Send back ready X position to caller */
+    *X = ((dataxy[0] & FT6206_MSB_MASK) << 8) | (dataxy[1] & FT6206_LSB_MASK);
+    
+    /* Send back ready Y position to caller */
+    *Y = ((dataxy[2] & FT6206_MSB_MASK) << 8) | (dataxy[3] & FT6206_LSB_MASK);
+    
+    ft6x06_handle.currActiveTouchIdx++;
+  }
+}
+
+/**
+  * @brief  Configure the FT6xx6 device to generate IT on given INT pin
+  *         connected to MCU as EXTI.
+  * @param  DeviceAddr: Device address on communication Bus (Slave I2C address of FT6xx6).
+  * @retval None
+  */
+void ft6x06_TS_EnableIT(uint16_t DeviceAddr)
+{
+  uint8_t regValue = 0;
+  regValue = (FT6206_G_MODE_INTERRUPT_TRIGGER & (FT6206_G_MODE_INTERRUPT_MASK >> FT6206_G_MODE_INTERRUPT_SHIFT)) << FT6206_G_MODE_INTERRUPT_SHIFT;
+  
+  /* Set interrupt trigger mode in FT6206_GMODE_REG */
+  TS_IO_Write(DeviceAddr, FT6206_GMODE_REG, regValue);
+}
+
+/**
+  * @brief  Configure the FT6xx6 device to stop generating IT on the given INT pin
+  *         connected to MCU as EXTI.
+  * @param  DeviceAddr: Device address on communication Bus (Slave I2C address of FT6xx6).
+  * @retval None
+  */
+void ft6x06_TS_DisableIT(uint16_t DeviceAddr)
+{
+  uint8_t regValue = 0;
+  regValue = (FT6206_G_MODE_INTERRUPT_POLLING & (FT6206_G_MODE_INTERRUPT_MASK >> FT6206_G_MODE_INTERRUPT_SHIFT)) << FT6206_G_MODE_INTERRUPT_SHIFT;
+
+  /* Set interrupt polling mode in FT6206_GMODE_REG */
+  TS_IO_Write(DeviceAddr, FT6206_GMODE_REG, regValue);
+}
+
+/**
+  * @brief  Get IT status from FT6xx6 interrupt status registers
+  *         Should be called Following an EXTI coming to the MCU to know the detailed
+  *         reason of the interrupt.
+  *         @note : This feature is not applicable to FT6xx6.
+  * @param  DeviceAddr: Device address on communication Bus (I2C slave address of FT6xx6).
+  * @retval TS interrupts status : always return 0 here
+  */
+uint8_t ft6x06_TS_ITStatus(uint16_t DeviceAddr)
+{
+  /* Always return 0 as feature not applicable to FT6xx6 */
+  return 0;
+}
+
+/**
+  * @brief  Clear IT status in FT6xx6 interrupt status clear registers
+  *         Should be called Following an EXTI coming to the MCU.
+  *         @note : This feature is not applicable to FT6xx6.
+  * @param  DeviceAddr: Device address on communication Bus (I2C slave address of FT6xx6).
+  * @retval None
+  */
+void ft6x06_TS_ClearIT(uint16_t DeviceAddr)
+{
+  /* Nothing to be done here for FT6xx6 */
+}
+
+/**** NEW FEATURES enabled when Multi-touch support is enabled ****/
+
+#if (TS_MULTI_TOUCH_SUPPORTED == 1)
+/**
+  * @brief  Get the last touch gesture identification (zoom, move up/down...).
+  * @param  DeviceAddr: Device address on communication Bus (I2C slave address of FT6xx6).
+  * @param  pGestureId : Pointer to get last touch gesture Identification.
+  * @retval None.
+  */
+void ft6x06_TS_GetGestureID(uint16_t DeviceAddr, uint32_t * pGestureId)
+{
+  volatile uint8_t ucReadData = 0;
+
+  ucReadData = TS_IO_Read(DeviceAddr, FT6206_GEST_ID_REG);
+
+  * pGestureId = ucReadData;
+}
+
+/**
+  * @brief  Get the touch detailed informations on touch number 'touchIdx' (0..1)
+  *         This touch detailed information contains :
+  *         - weight that was applied to this touch
+  *         - sub-area of the touch in the touch panel
+  *         - event of linked to the touch (press down, lift up, ...)
+  * @param  DeviceAddr: Device address on communication Bus (I2C slave address of FT6xx6).
+  * @param  touchIdx : Passed index of the touch (0..1) on which we want to get the
+  *                    detailed information.
+  * @param  pWeight : Pointer to to get the weight information of 'touchIdx'.
+  * @param  pArea   : Pointer to to get the sub-area information of 'touchIdx'.
+  * @param  pEvent  : Pointer to to get the event information of 'touchIdx'.
+
+  * @retval None.
+  */
+void ft6x06_TS_GetTouchInfo(uint16_t   DeviceAddr,
+                            uint32_t   touchIdx,
+                            uint32_t * pWeight,
+                            uint32_t * pArea,
+                            uint32_t * pEvent)
+{
+  uint8_t regAddress = 0;
+  uint8_t dataxy[3];
+  
+  if(touchIdx < ft6x06_handle.currActiveTouchNb)
+  {
+    switch(touchIdx)
+    {
+    case 0 : 
+      regAddress = FT6206_P1_WEIGHT_REG;
+      break;
+      
+    case 1 :
+      regAddress = FT6206_P2_WEIGHT_REG;
+      break;
+      
+    default :
+      break;
+      
+    } /* end switch(touchIdx) */
+    
+    /* Read weight, area and Event Id of touch index */
+    TS_IO_ReadMultiple(DeviceAddr, regAddress, dataxy, sizeof(dataxy)); 
+    
+    /* Return weight of touch index */
+    * pWeight = (dataxy[0] & FT6206_TOUCH_WEIGHT_MASK) >> FT6206_TOUCH_WEIGHT_SHIFT;
+    /* Return area of touch index */
+    * pArea = (dataxy[1] & FT6206_TOUCH_AREA_MASK) >> FT6206_TOUCH_AREA_SHIFT;
+    /* Return Event Id  of touch index */
+    * pEvent = (dataxy[2] & FT6206_TOUCH_EVT_FLAG_MASK) >> FT6206_TOUCH_EVT_FLAG_SHIFT;
+    
+  } /* of if(touchIdx < ft6x06_handle.currActiveTouchNb) */
+}
+
+#endif /* TS_MULTI_TOUCH_SUPPORTED == 1 */
+
+#if (TS_AUTO_CALIBRATION_SUPPORTED == 1)
+/**
+  * @brief  Start TouchScreen calibration phase
+  * @param  DeviceAddr: FT6xx6 Device address for communication on I2C Bus.
+  * @retval Status FT6206_STATUS_OK or FT6206_STATUS_NOT_OK.
+  */
+static uint32_t ft6x06_TS_Calibration(uint16_t DeviceAddr)
+{
+  uint32_t nbAttempt = 0;
+  volatile uint8_t ucReadData;
+  volatile uint8_t regValue;
+  uint32_t status = FT6206_STATUS_OK;
+  uint8_t bEndCalibration = 0;
+
+  /* >> Calibration sequence start */
+
+  /* Switch FT6xx6 back to factory mode to calibrate */
+  regValue = (FT6206_DEV_MODE_FACTORY & FT6206_DEV_MODE_MASK) << FT6206_DEV_MODE_SHIFT;
+  TS_IO_Write(DeviceAddr, FT6206_DEV_MODE_REG, regValue); /* 0x40 */
+
+  /* Read back the same register FT6206_DEV_MODE_REG */
+  ucReadData = TS_IO_Read(DeviceAddr, FT6206_DEV_MODE_REG);
+  TS_IO_Delay(300); /* Wait 300 ms */
+
+  if(((ucReadData & (FT6206_DEV_MODE_MASK << FT6206_DEV_MODE_SHIFT)) >> FT6206_DEV_MODE_SHIFT) != FT6206_DEV_MODE_FACTORY )
+  {
+    /* Return error to caller */
+    return(FT6206_STATUS_NOT_OK);
+  }
+
+  /* Start calibration command */
+  TS_IO_Write(DeviceAddr, FT6206_TD_STAT_REG, 0x04);
+  TS_IO_Delay(300); /* Wait 300 ms */
+
+  /* 100 attempts to wait switch from factory mode (calibration) to working mode */
+  for (nbAttempt=0; ((nbAttempt < 100) && (!bEndCalibration)) ; nbAttempt++)
+  {
+    ucReadData = TS_IO_Read(DeviceAddr, FT6206_DEV_MODE_REG);
+    ucReadData = (ucReadData & (FT6206_DEV_MODE_MASK << FT6206_DEV_MODE_SHIFT)) >> FT6206_DEV_MODE_SHIFT;
+    if(ucReadData == FT6206_DEV_MODE_WORKING)
+    {
+      /* Auto Switch to FT6206_DEV_MODE_WORKING : means calibration have ended */
+      bEndCalibration = 1; /* exit for loop */
+    }
+    
+    TS_IO_Delay(200); /* Wait 200 ms */
+  }
+
+  /* Calibration sequence end << */
+
+  return(status);
+}
+#endif /* TS_AUTO_CALIBRATION_SUPPORTED == 1 */
+
+/**
+  * @brief  Basic static configuration of TouchScreen
+  * @param  DeviceAddr: FT6xx6 Device address for communication on I2C Bus.
+  * @retval Status FT6206_STATUS_OK or FT6206_STATUS_NOT_OK.
+  */
+static uint32_t ft6x06_TS_Configure(uint16_t DeviceAddr)
+{
+  uint32_t status = FT6206_STATUS_OK;
+
+  /* Nothing special to be done for FT6xx6 */
+
+  return(status);
+}
+
+/**
+  * @brief  Check if the device instance of the selected address is already registered
+  *         and return its index  
+  * @param  DeviceAddr: Device address on communication Bus.
+  * @retval Index of the device instance if registered, 0xFF if not.
+  */
+static uint8_t ft6x06_GetInstance(uint16_t DeviceAddr)
+{
+  uint8_t idx = 0;
+  
+  /* Check all the registered instances */
+  for(idx = 0; idx < FT6x06_MAX_INSTANCE ; idx ++)
+  {
+    if(ft6x06[idx] == DeviceAddr)
+    {
+      return idx; 
+    }
+  }
+  
+  return 0xFF;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Drivers/BSP/Components/ft6x06/ft6x06.h b/Drivers/BSP/Components/ft6x06/ft6x06.h
new file mode 100644
index 0000000..937dcd9
--- /dev/null
+++ b/Drivers/BSP/Components/ft6x06/ft6x06.h
@@ -0,0 +1,454 @@
+/**
+  ******************************************************************************
+  * @file    ft6x06.h
+  * @author  MCD Application Team
+  * @brief   This file contains all the functions prototypes for the
+  *          ft6x06.c IO expander driver.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __FT6XX6_H
+#define __FT6XX6_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Set Multi-touch as non supported */
+#ifndef TS_MULTI_TOUCH_SUPPORTED
+  #define TS_MULTI_TOUCH_SUPPORTED 0
+#endif
+
+/* Set Auto-calibration as non supported */  
+#ifndef TS_AUTO_CALIBRATION_SUPPORTED
+  #define TS_AUTO_CALIBRATION_SUPPORTED 0
+#endif
+  
+/* Includes ------------------------------------------------------------------*/
+#include "../Common/ts.h"
+
+/* Macros --------------------------------------------------------------------*/
+
+/** @typedef ft6x06_handle_TypeDef
+ *  ft6x06 Handle definition.
+ */
+typedef struct
+{
+  uint8_t i2cInitialized;
+
+  /* field holding the current number of simultaneous active touches */
+  uint8_t currActiveTouchNb;
+
+  /* field holding the touch index currently managed */
+  uint8_t currActiveTouchIdx;
+
+} ft6x06_handle_TypeDef;
+
+  /** @addtogroup BSP
+   * @{
+   */
+
+  /** @addtogroup Component
+   * @{
+   */
+
+  /** @defgroup FT6XX6
+   * @{
+   */
+
+  /* Exported types ------------------------------------------------------------*/
+
+  /** @defgroup FT6XX6_Exported_Types
+   * @{
+   */
+
+  /* Exported constants --------------------------------------------------------*/
+
+  /** @defgroup FT6XX6_Exported_Constants
+   * @{
+   */
+
+  /* Maximum border values of the touchscreen pad */
+#define  FT_6206_MAX_WIDTH              ((uint16_t)800)     /* Touchscreen pad max width   */
+#define  FT_6206_MAX_HEIGHT             ((uint16_t)480)     /* Touchscreen pad max height  */
+
+  /* Touchscreen pad max width and height values for FT6xx6 Touch*/
+#define  FT_6206_MAX_WIDTH_HEIGHT       ((uint16_t)240)     
+
+  /* Possible values of driver functions return status */
+#define FT6206_STATUS_OK                0
+#define FT6206_STATUS_NOT_OK            1
+
+  /* Possible values of global variable 'TS_I2C_Initialized' */
+#define FT6206_I2C_NOT_INITIALIZED      0
+#define FT6206_I2C_INITIALIZED          1
+
+  /* Max detectable simultaneous touches */
+#define FT6206_MAX_DETECTABLE_TOUCH     2
+
+  /**
+   * @brief : Definitions for FT6xx6 I2C register addresses on 8 bit
+   **/
+
+  /* Current mode register of the FT6xx6 (R/W) */
+#define FT6206_DEV_MODE_REG             0x00
+
+  /* Possible values of FT6206_DEV_MODE_REG */
+#define FT6206_DEV_MODE_WORKING         0x00
+#define FT6206_DEV_MODE_FACTORY         0x04
+
+#define FT6206_DEV_MODE_MASK            0x7
+#define FT6206_DEV_MODE_SHIFT           4
+
+  /* Gesture ID register */
+#define FT6206_GEST_ID_REG              0x01
+
+  /* Possible values of FT6206_GEST_ID_REG */
+#define FT6206_GEST_ID_NO_GESTURE       0x00
+#define FT6206_GEST_ID_MOVE_UP          0x10
+#define FT6206_GEST_ID_MOVE_RIGHT       0x14
+#define FT6206_GEST_ID_MOVE_DOWN        0x18
+#define FT6206_GEST_ID_MOVE_LEFT        0x1C
+#define FT6206_GEST_ID_ZOOM_IN          0x48
+#define FT6206_GEST_ID_ZOOM_OUT         0x49
+
+  /* Touch Data Status register : gives number of active touch points (0..2) */
+#define FT6206_TD_STAT_REG              0x02
+
+  /* Values related to FT6206_TD_STAT_REG */
+#define FT6206_TD_STAT_MASK             0x0F
+#define FT6206_TD_STAT_SHIFT            0x00
+
+  /* Values Pn_XH and Pn_YH related */
+#define FT6206_TOUCH_EVT_FLAG_PRESS_DOWN 0x00
+#define FT6206_TOUCH_EVT_FLAG_LIFT_UP    0x01
+#define FT6206_TOUCH_EVT_FLAG_CONTACT    0x02
+#define FT6206_TOUCH_EVT_FLAG_NO_EVENT   0x03
+
+#define FT6206_TOUCH_EVT_FLAG_SHIFT     6
+#define FT6206_TOUCH_EVT_FLAG_MASK      (3 << FT6206_TOUCH_EVT_FLAG_SHIFT)
+
+#define FT6206_MSB_MASK                 0x0F
+#define FT6206_MSB_SHIFT                0
+
+  /* Values Pn_XL and Pn_YL related */
+#define FT6206_LSB_MASK                 0xFF
+#define FT6206_LSB_SHIFT                0
+
+#define FT6206_P1_XH_REG                0x03
+#define FT6206_P1_XL_REG                0x04
+#define FT6206_P1_YH_REG                0x05
+#define FT6206_P1_YL_REG                0x06
+
+  /* Touch Pressure register value (R) */
+#define FT6206_P1_WEIGHT_REG            0x07
+
+  /* Values Pn_WEIGHT related  */
+#define FT6206_TOUCH_WEIGHT_MASK        0xFF
+#define FT6206_TOUCH_WEIGHT_SHIFT       0
+
+  /* Touch area register */
+#define FT6206_P1_MISC_REG              0x08
+
+  /* Values related to FT6206_Pn_MISC_REG */
+#define FT6206_TOUCH_AREA_MASK         (0x04 << 4)
+#define FT6206_TOUCH_AREA_SHIFT        0x04
+
+#define FT6206_P2_XH_REG               0x09
+#define FT6206_P2_XL_REG               0x0A
+#define FT6206_P2_YH_REG               0x0B
+#define FT6206_P2_YL_REG               0x0C
+#define FT6206_P2_WEIGHT_REG           0x0D
+#define FT6206_P2_MISC_REG             0x0E
+
+  /* Threshold for touch detection */
+#define FT6206_TH_GROUP_REG            0x80
+
+  /* Values FT6206_TH_GROUP_REG : threshold related  */
+#define FT6206_THRESHOLD_MASK          0xFF
+#define FT6206_THRESHOLD_SHIFT         0
+
+  /* Filter function coefficients */
+#define FT6206_TH_DIFF_REG             0x85
+
+  /* Control register */
+#define FT6206_CTRL_REG                0x86
+
+  /* Values related to FT6206_CTRL_REG */
+
+  /* Will keep the Active mode when there is no touching */
+#define FT6206_CTRL_KEEP_ACTIVE_MODE    0x00
+
+  /* Switching from Active mode to Monitor mode automatically when there is no touching */
+#define FT6206_CTRL_KEEP_AUTO_SWITCH_MONITOR_MODE  0x01
+
+  /* The time period of switching from Active mode to Monitor mode when there is no touching */
+#define FT6206_TIMEENTERMONITOR_REG     0x87
+
+  /* Report rate in Active mode */
+#define FT6206_PERIODACTIVE_REG         0x88
+
+  /* Report rate in Monitor mode */
+#define FT6206_PERIODMONITOR_REG        0x89
+
+  /* The value of the minimum allowed angle while Rotating gesture mode */
+#define FT6206_RADIAN_VALUE_REG         0x91
+
+  /* Maximum offset while Moving Left and Moving Right gesture */
+#define FT6206_OFFSET_LEFT_RIGHT_REG    0x92
+
+  /* Maximum offset while Moving Up and Moving Down gesture */
+#define FT6206_OFFSET_UP_DOWN_REG       0x93
+
+  /* Minimum distance while Moving Left and Moving Right gesture */
+#define FT6206_DISTANCE_LEFT_RIGHT_REG  0x94
+
+  /* Minimum distance while Moving Up and Moving Down gesture */
+#define FT6206_DISTANCE_UP_DOWN_REG     0x95
+
+  /* Maximum distance while Zoom In and Zoom Out gesture */
+#define FT6206_DISTANCE_ZOOM_REG        0x96
+
+  /* High 8-bit of LIB Version info */
+#define FT6206_LIB_VER_H_REG            0xA1
+
+  /* Low 8-bit of LIB Version info */
+#define FT6206_LIB_VER_L_REG            0xA2
+
+  /* Chip Selecting */
+#define FT6206_CIPHER_REG               0xA3
+
+  /* Interrupt mode register (used when in interrupt mode) */
+#define FT6206_GMODE_REG                0xA4
+
+#define FT6206_G_MODE_INTERRUPT_MASK    0x03
+#define FT6206_G_MODE_INTERRUPT_SHIFT   0x00
+
+  /* Possible values of FT6206_GMODE_REG */
+#define FT6206_G_MODE_INTERRUPT_POLLING 0x00
+#define FT6206_G_MODE_INTERRUPT_TRIGGER 0x01
+
+  /* Current power mode the FT6xx6 system is in (R) */
+#define FT6206_PWR_MODE_REG             0xA5
+
+  /* FT6xx6 firmware version */
+#define FT6206_FIRMID_REG               0xA6
+
+  /* FT6xx6 Chip identification register */
+#define FT6206_CHIP_ID_REG              0xA8
+
+  /*  Possible values of touchscreen controller ID */
+#define FT6206_ID_VALUE                 0x11
+#define FT6x36_ID_VALUE                 0xCD
+#define FT6X36_ID2_VALUE                0xD8
+
+  /* Release code version */
+#define FT6206_RELEASE_CODE_ID_REG      0xAF
+
+  /* Current operating mode the FT6xx6 system is in (R) */
+#define FT6206_STATE_REG                0xBC
+
+  /**
+   * @}
+   */
+
+  /* Exported macro ------------------------------------------------------------*/
+
+  /** @defgroup ft6xx6_Exported_Macros
+   * @{
+   */
+
+  /* Exported functions --------------------------------------------------------*/
+
+  /** @defgroup ft6xx6_Exported_Functions
+   * @{
+   */
+
+  /**
+   * @brief ft6xx6 Control functions
+   */
+
+
+/**
+ * @brief  Initialize the ft6xx6 communication bus
+ *         from MCU to FT6xx6 : ie I2C channel initialization (if required).
+ * @param  DeviceAddr: Device address on communication Bus (I2C slave address of FT6xx6).
+ * @retval None
+ */
+void ft6x06_Init(uint16_t DeviceAddr);
+
+/**
+ * @brief  Software Reset the ft6xx6.
+ * @param  DeviceAddr: Device address on communication Bus (I2C slave address of FT6xx6).
+ * @retval None
+ */
+void ft6x06_Reset(uint16_t DeviceAddr);
+
+/**
+ * @brief  Read the ft6xx6 device ID, pre intitalize I2C in case of need to be
+ *         able to read the FT6xx6 device ID, and verify this is a FT6xx6.
+ * @param  DeviceAddr: I2C FT6xx6 Slave address.
+ * @retval The Device ID (two bytes).
+ */
+uint16_t ft6x06_ReadID(uint16_t DeviceAddr);
+
+/**
+ * @brief  Configures the touch Screen IC device to start detecting touches
+ * @param  DeviceAddr: Device address on communication Bus (I2C slave address).
+ * @retval None.
+ */
+void ft6x06_TS_Start(uint16_t DeviceAddr);
+
+/**
+ * @brief  Return if there is touches detected or not.
+ *         Try to detect new touches and forget the old ones (reset internal global
+ *         variables).
+ * @param  DeviceAddr: Device address on communication Bus.
+ * @retval : Number of active touches detected (can be 0, 1 or 2).
+ */
+uint8_t ft6x06_TS_DetectTouch(uint16_t DeviceAddr);
+
+/**
+ * @brief  Get the touch screen X and Y positions values
+ *         Manage multi touch thanks to touch Index global
+ *         variable 'ft6x06_handle.currActiveTouchIdx'.
+ * @param  DeviceAddr: Device address on communication Bus.
+ * @param  X: Pointer to X position value
+ * @param  Y: Pointer to Y position value
+ * @retval None.
+ */
+void ft6x06_TS_GetXY(uint16_t DeviceAddr, uint16_t *X, uint16_t *Y);
+
+/**
+ * @brief  Configure the FT6xx6 device to generate IT on given INT pin
+ *         connected to MCU as EXTI.
+ * @param  DeviceAddr: Device address on communication Bus (Slave I2C address of FT6xx6).
+ * @retval None
+ */
+void ft6x06_TS_EnableIT(uint16_t DeviceAddr);
+
+/**
+ * @brief  Configure the FT6xx6 device to stop generating IT on the given INT pin
+ *         connected to MCU as EXTI.
+ * @param  DeviceAddr: Device address on communication Bus (Slave I2C address of FT6xx6).
+ * @retval None
+ */
+void ft6x06_TS_DisableIT(uint16_t DeviceAddr);
+
+/**
+ * @brief  Get IT status from FT6xx6 interrupt status registers
+ *         Should be called Following an EXTI coming to the MCU to know the detailed
+ *         reason of the interrupt.
+ * @param  DeviceAddr: Device address on communication Bus (I2C slave address of FT6xx6).
+ * @retval TS interrupts status
+ */
+uint8_t ft6x06_TS_ITStatus (uint16_t DeviceAddr);
+
+/**
+ * @brief  Clear IT status in FT6xx6 interrupt status clear registers
+ *         Should be called Following an EXTI coming to the MCU.
+ * @param  DeviceAddr: Device address on communication Bus (I2C slave address of FT6xx6).
+ * @retval TS interrupts status
+ */
+void ft6x06_TS_ClearIT (uint16_t DeviceAddr);
+
+/**** NEW FEATURES enabled when Multi-touch support is enabled ****/
+
+#if (TS_MULTI_TOUCH_SUPPORTED == 1)
+
+/**
+ * @brief  Get the last touch gesture identification (zoom, move up/down...).
+ * @param  DeviceAddr: Device address on communication Bus (I2C slave address of FT6xx6).
+ * @param  pGestureId : Pointer to get last touch gesture Identification.
+ * @retval None.
+ */
+void ft6x06_TS_GetGestureID(uint16_t DeviceAddr, uint32_t * pGestureId);
+
+/**
+ * @brief  Get the touch detailed informations on touch number 'touchIdx' (0..1)
+ *         This touch detailed information contains :
+ *         - weight that was applied to this touch
+ *         - sub-area of the touch in the touch panel
+ *         - event of linked to the touch (press down, lift up, ...)
+ * @param  DeviceAddr: Device address on communication Bus (I2C slave address of FT6xx6).
+ * @param  touchIdx : Passed index of the touch (0..1) on which we want to get the
+ *                    detailed information.
+ * @param  pWeight : Pointer to to get the weight information of 'touchIdx'.
+ * @param  pArea   : Pointer to to get the sub-area information of 'touchIdx'.
+ * @param  pEvent  : Pointer to to get the event information of 'touchIdx'.
+
+ * @retval None.
+ */
+void ft6x06_TS_GetTouchInfo(uint16_t   DeviceAddr,
+                            uint32_t   touchIdx,
+                            uint32_t * pWeight,
+                            uint32_t * pArea,
+                            uint32_t * pEvent);
+
+#endif /* TS_MULTI_TOUCH_SUPPORTED == 1 */
+
+/* Imported TS IO functions --------------------------------------------------------*/
+
+/** @defgroup ft6xx6_Imported_Functions
+ * @{
+ */
+
+/* TouchScreen (TS) external IO functions */
+extern void     TS_IO_Init(void);
+extern void     TS_IO_Write(uint8_t Addr, uint8_t Reg, uint8_t Value);
+extern uint8_t  TS_IO_Read(uint8_t Addr, uint8_t Reg);
+extern uint16_t TS_IO_ReadMultiple(uint8_t Addr, uint8_t Reg, uint8_t *Buffer, uint16_t Length);
+extern void     TS_IO_Delay(uint32_t Delay);
+
+  /**
+   * @}
+   */
+
+  /* Imported global variables --------------------------------------------------------*/
+
+  /** @defgroup ft6xx6_Imported_Globals
+   * @{
+   */
+
+
+/* Touch screen driver structure */
+extern TS_DrvTypeDef ft6x06_ts_drv;
+
+  /**
+   * @}
+   */
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* __FT6XX6_H */
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Drivers/BSP/Components/n25q128a/Release_Notes.html b/Drivers/BSP/Components/n25q128a/Release_Notes.html
new file mode 100644
index 0000000..f0b58f0
--- /dev/null
+++ b/Drivers/BSP/Components/n25q128a/Release_Notes.html
@@ -0,0 +1,157 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html xmlns:v="urn:schemas-microsoft-com:vml" xmlns:o="urn:schemas-microsoft-com:office:office" xmlns:w="urn:schemas-microsoft-com:office:word" xmlns="http://www.w3.org/TR/REC-html40"><head>
+
+
+
+
+
+
+  
+  <meta http-equiv="Content-Type" content="text/html; charset=ISO-8859-1">
+
+  
+  <link rel="File-List" href="Library_files/filelist.xml">
+
+  
+  <link rel="Edit-Time-Data" href="Library_files/editdata.mso"><!--[if !mso]> <style> v\:* {behavior:url(#default#VML);} o\:* {behavior:url(#default#VML);} w\:* {behavior:url(#default#VML);} .shape {behavior:url(#default#VML);} </style> <![endif]--><title>Release Notes for STM32 BSP Components Drivers</title><!--[if gte mso 9]><xml> <o:DocumentProperties> <o:Author>STMicroelectronics</o:Author> <o:LastAuthor>STMicroelectronics</o:LastAuthor> <o:Revision>37</o:Revision> <o:TotalTime>136</o:TotalTime> <o:Created>2009-02-27T19:26:00Z</o:Created> <o:LastSaved>2009-03-01T17:56:00Z</o:LastSaved> <o:Pages>1</o:Pages> <o:Words>522</o:Words> <o:Characters>2977</o:Characters> <o:Company>STMicroelectronics</o:Company> <o:Lines>24</o:Lines> <o:Paragraphs>6</o:Paragraphs> <o:CharactersWithSpaces>3493</o:CharactersWithSpaces> <o:Version>11.6568</o:Version> </o:DocumentProperties> </xml><![endif]--><!--[if gte mso 9]><xml> <w:WordDocument> <w:Zoom>110</w:Zoom> <w:ValidateAgainstSchemas/> <w:SaveIfXMLInvalid>false</w:SaveIfXMLInvalid> <w:IgnoreMixedContent>false</w:IgnoreMixedContent> <w:AlwaysShowPlaceholderText>false</w:AlwaysShowPlaceholderText> <w:BrowserLevel>MicrosoftInternetExplorer4</w:BrowserLevel> </w:WordDocument> </xml><![endif]--><!--[if gte mso 9]><xml> <w:LatentStyles DefLockedState="false" LatentStyleCount="156"> </w:LatentStyles> </xml><![endif]-->
+
+
+  
+
+  
+
+  
+  <style>
+<!--
+/* Style Definitions */
+p.MsoNormal, li.MsoNormal, div.MsoNormal
+{mso-style-parent:"";
+margin:0in;
+margin-bottom:.0001pt;
+mso-pagination:widow-orphan;
+font-size:12.0pt;
+font-family:"Times New Roman";
+mso-fareast-font-family:"Times New Roman";}
+h2
+{mso-style-next:Normal;
+margin-top:12.0pt;
+margin-right:0in;
+margin-bottom:3.0pt;
+margin-left:0in;
+mso-pagination:widow-orphan;
+page-break-after:avoid;
+mso-outline-level:2;
+font-size:14.0pt;
+font-family:Arial;
+font-weight:bold;
+font-style:italic;}
+a:link, span.MsoHyperlink
+{color:blue;
+text-decoration:underline;
+text-underline:single;}
+a:visited, span.MsoHyperlinkFollowed
+{color:blue;
+text-decoration:underline;
+text-underline:single;}
+p
+{mso-margin-top-alt:auto;
+margin-right:0in;
+mso-margin-bottom-alt:auto;
+margin-left:0in;
+mso-pagination:widow-orphan;
+font-size:12.0pt;
+font-family:"Times New Roman";
+mso-fareast-font-family:"Times New Roman";}
+@page Section1
+{size:8.5in 11.0in;
+margin:1.0in 1.25in 1.0in 1.25in;
+mso-header-margin:.5in;
+mso-footer-margin:.5in;
+mso-paper-source:0;}
+div.Section1
+{page:Section1;}
+-->
+  </style><!--[if gte mso 10]> <style> /* Style Definitions */ table.MsoNormalTable {mso-style-name:"Table Normal"; mso-tstyle-rowband-size:0; mso-tstyle-colband-size:0; mso-style-noshow:yes; mso-style-parent:""; mso-padding-alt:0in 5.4pt 0in 5.4pt; mso-para-margin:0in; mso-para-margin-bottom:.0001pt; mso-pagination:widow-orphan; font-size:10.0pt; font-family:"Times New Roman"; mso-ansi-language:#0400; mso-fareast-language:#0400; mso-bidi-language:#0400;} </style> <![endif]--><!--[if gte mso 9]><xml> <o:shapedefaults v:ext="edit" spidmax="5122"/> </xml><![endif]--><!--[if gte mso 9]><xml> <o:shapelayout v:ext="edit"> <o:idmap v:ext="edit" data="1"/> </o:shapelayout></xml><![endif]-->
+  <meta content="MCD Application Team" name="author"></head>
+<body link="blue" vlink="blue">
+<div class="Section1">
+<p class="MsoNormal"><span style="font-family: Arial;"><o:p><br>
+</o:p></span></p>
+<div align="center">
+<table class="MsoNormalTable" style="width: 675pt;" border="0" cellpadding="0" cellspacing="0" width="900">
+  <tbody>
+    <tr>
+      <td style="padding: 0cm;" valign="top">
+      <table class="MsoNormalTable" style="width: 675pt;" border="0" cellpadding="0" cellspacing="0" width="900">
+        <tbody>
+          <tr>
+            <td style="vertical-align: top;">
+            <p class="MsoNormal"><span style="font-size: 8pt; font-family: Arial; color: blue;"><a href="../../../../Release_Notes.html">Back to Release page</a><o:p></o:p></span></p>
+            </td>
+          </tr>
+          <tr style="">
+            <td style="padding: 1.5pt;">
+            <h1 style="margin-bottom: 18pt; text-align: center;" align="center"><span style="font-size: 20pt; font-family: Verdana; color: rgb(51, 102, 255);">Release
+Notes for N25Q128A Component Driver</span><span style="font-size: 20pt; font-family: Verdana;"><o:p></o:p></span></h1>
+            <p class="MsoNormal" style="text-align: center;" align="center"><span style="font-size: 10pt; font-family: Arial; color: black;">Copyright
+2015 STMicroelectronics</span><span style="color: black;"><u1:p></u1:p><o:p></o:p></span></p>
+            <p class="MsoNormal" style="text-align: center;" align="center"><span style="font-size: 10pt; font-family: Arial; color: black;"><img alt="" id="_x0000_i1025" src="../../../../_htmresc/st_logo.png" style="border: 0px solid ; width: 86px; height: 65px;"></span><span style="font-size: 10pt;"><o:p></o:p></span></p>
+            </td>
+          </tr>
+        </tbody>
+      </table>
+      <p class="MsoNormal"><span style="font-family: Arial; display: none;"><o:p>&nbsp;</o:p></span></p>
+      <table style="width: 675pt;" class="MsoNormalTable" border="0" cellpadding="0" width="900">
+        <tbody>
+          <tr style="">
+            <td style="padding: 0cm;" valign="top"><span style="font-size: 10pt; font-family: Verdana;"></span><h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial;"><a name="History"></a><span style="font-size: 12pt; color: white;">Update History</span></h2><br><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 180px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.0.0
+/ 29-May-2015 <o:p></o:p></span></h3>
+<p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
+Changes<o:p></o:p></span></u></b></p>
+<span style="font-size: 10pt; font-family: Verdana;"></span>
+<span style="font-size: 10pt; font-family: Verdana;"></span>
+<span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;"></span>
+<span style="font-size: 10pt; font-family: Verdana;"></span>
+<span style="font-size: 10pt; font-family: Verdana;"></span>
+<span style="font-size: 10pt; font-family: Verdana;"></span>
+<span style="font-size: 10pt; font-family: Verdana;"></span>
+<span style="font-size: 10pt; font-family: Verdana;"></span>
+<span style="font-size: 10pt; font-family: Verdana;"></span>
+<ul style="list-style-type: square;"><li><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-family: Verdana;"></span><span style="font-family: Verdana; font-size: 10pt;">First official 
+release</span><span style="font-size: 10pt; font-family: Verdana;"> of </span><span style="font-size: 10pt; font-family: Verdana;">N25Q128A QuadSPI Flash&nbsp;Component</span><span style="font-size: 10pt; font-family: Verdana;"> driver</span></li></ul><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic; font-weight: bold;"></span></span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic; font-weight: bold;"></span></span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic; font-weight: bold;"></span></span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic; font-weight: bold;"></span></span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic; font-weight: bold;"></span></span><span style="font-size: 10pt; font-family: Verdana;"></span><h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial;"><a name="License"></a><span style="font-size: 12pt; color: white;">License<o:p></o:p></span><br></h2><div style="text-align: justify;"><font size="-1"><span style="font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are
+met:</span><br>
+            </font>
+            <ol><li><font size="-1"><span style="font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.</span><span style="font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"></span></font></li><li><font size="-1"><span style="font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Redistributions
+in binary form must reproduce the above copyright notice, this list of
+conditions and the following disclaimer in </span><span style="font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">the documentation and/or other materials provided with the distribution.</span><span style="font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"></span></font></li><li><font size="-1"><span style="font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived </span><br>
+                </font>
+              </li></ol>
+            <font size="-1"><span style="font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; from this software without specific prior written permission.</span><br>
+            <span style="font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"></span><br>
+            <span style="font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED</span><span style="font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"> WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A </span><span style="font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY </span><span style="font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, </span><span style="font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER</span><span style="font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"> CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR </span><span style="font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.</span></font>
+            
+            </div>
+<p class="MsoNormal"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;; color: black;"><o:p></o:p></span></p>
+<b><span style="font-size: 10pt; font-family: Verdana; color: black;"></span></b>
+            
+            <div class="MsoNormal" style="text-align: center;" align="center"><span style="color: black;">
+            <hr align="center" size="2" width="100%"></span></div>
+            <div style="margin-left: 120px;"><span style="font-size: 10pt; font-family: Verdana; color: black;">For
+complete documentation on </span><span style="font-size: 10pt; font-family: Verdana;">STM32<span style="color: black;">&nbsp;Microcontrollers
+visit </span><u><span style="color: blue;"><a href="http://www.st.com/internet/mcu/class/1734.jsp" target="_blank">www.st.com/STM32</a></span></u></span></div>
+            </td>
+          </tr>
+        <tr><td style="padding: 0cm;" valign="top"></td></tr></tbody>
+      </table>
+      <p class="MsoNormal"><span style="font-size: 10pt;"><o:p></o:p></span></p>
+      </td>
+    </tr>
+  </tbody>
+</table>
+</div>
+<p class="MsoNormal"><o:p>&nbsp;</o:p></p>
+</div>
+
+</body></html>
\ No newline at end of file
diff --git a/Drivers/BSP/Components/n25q128a/n25q128a.h b/Drivers/BSP/Components/n25q128a/n25q128a.h
new file mode 100644
index 0000000..2669ee2
--- /dev/null
+++ b/Drivers/BSP/Components/n25q128a/n25q128a.h
@@ -0,0 +1,219 @@
+/**
+  ******************************************************************************
+  * @file    n25q128a.h
+  * @author  MCD Application Team
+  * @version V1.0.0
+  * @date    29-May-2015
+  * @brief   This file contains all the description of the N25Q128A QSPI memory.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */ 
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __N25Q128A_H
+#define __N25Q128A_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+
+/* Includes ------------------------------------------------------------------*/
+
+/** @addtogroup BSP
+  * @{
+  */ 
+
+/** @addtogroup Components
+  * @{
+  */ 
+  
+/** @addtogroup n25q128a
+  * @{
+  */
+
+/** @defgroup N25Q128A_Exported_Types
+  * @{
+  */
+   
+/**
+  * @}
+  */ 
+
+/** @defgroup N25Q128A_Exported_Constants
+  * @{
+  */
+   
+/** 
+  * @brief  N25Q128A Configuration  
+  */  
+#define N25Q128A_FLASH_SIZE                  0x1000000 /* 128 MBits => 16MBytes */
+#define N25Q128A_SECTOR_SIZE                 0x10000   /* 256 sectors of 64KBytes */
+#define N25Q128A_SUBSECTOR_SIZE              0x1000    /* 4096 subsectors of 4kBytes */
+#define N25Q128A_PAGE_SIZE                   0x100     /* 65536 pages of 256 bytes */
+
+#define N25Q128A_DUMMY_CYCLES_READ           8
+#define N25Q128A_DUMMY_CYCLES_READ_QUAD      10
+
+#define N25Q128A_BULK_ERASE_MAX_TIME         250000
+#define N25Q128A_SECTOR_ERASE_MAX_TIME       3000
+#define N25Q128A_SUBSECTOR_ERASE_MAX_TIME    800
+
+/** 
+  * @brief  N25Q128A Commands  
+  */  
+/* Reset Operations */
+#define RESET_ENABLE_CMD                     0x66
+#define RESET_MEMORY_CMD                     0x99
+
+/* Identification Operations */
+#define READ_ID_CMD                          0x9E
+#define READ_ID_CMD2                         0x9F
+#define MULTIPLE_IO_READ_ID_CMD              0xAF
+#define READ_SERIAL_FLASH_DISCO_PARAM_CMD    0x5A
+
+/* Read Operations */
+#define READ_CMD                             0x03
+#define FAST_READ_CMD                        0x0B
+#define DUAL_OUT_FAST_READ_CMD               0x3B
+#define DUAL_INOUT_FAST_READ_CMD             0xBB
+#define QUAD_OUT_FAST_READ_CMD               0x6B
+#define QUAD_INOUT_FAST_READ_CMD             0xEB
+
+/* Write Operations */
+#define WRITE_ENABLE_CMD                     0x06
+#define WRITE_DISABLE_CMD                    0x04
+
+/* Register Operations */
+#define READ_STATUS_REG_CMD                  0x05
+#define WRITE_STATUS_REG_CMD                 0x01
+
+#define READ_LOCK_REG_CMD                    0xE8
+#define WRITE_LOCK_REG_CMD                   0xE5
+
+#define READ_FLAG_STATUS_REG_CMD             0x70
+#define CLEAR_FLAG_STATUS_REG_CMD            0x50
+
+#define READ_NONVOL_CFG_REG_CMD              0xB5
+#define WRITE_NONVOL_CFG_REG_CMD             0xB1
+
+#define READ_VOL_CFG_REG_CMD                 0x85
+#define WRITE_VOL_CFG_REG_CMD                0x81
+
+#define READ_ENHANCED_VOL_CFG_REG_CMD        0x65
+#define WRITE_ENHANCED_VOL_CFG_REG_CMD       0x61
+
+/* Program Operations */
+#define PAGE_PROG_CMD                        0x02
+#define DUAL_IN_FAST_PROG_CMD                0xA2
+#define EXT_DUAL_IN_FAST_PROG_CMD            0xD2
+#define QUAD_IN_FAST_PROG_CMD                0x32
+#define EXT_QUAD_IN_FAST_PROG_CMD            0x12
+
+/* Erase Operations */
+#define SUBSECTOR_ERASE_CMD                  0x20
+#define SECTOR_ERASE_CMD                     0xD8
+#define BULK_ERASE_CMD                       0xC7
+
+#define PROG_ERASE_RESUME_CMD                0x7A
+#define PROG_ERASE_SUSPEND_CMD               0x75
+
+/* One-Time Programmable Operations */
+#define READ_OTP_ARRAY_CMD                   0x4B
+#define PROG_OTP_ARRAY_CMD                   0x42
+
+/** 
+  * @brief  N25Q128A Registers  
+  */ 
+/* Status Register */
+#define N25Q128A_SR_WIP                      ((uint8_t)0x01)    /*!< Write in progress */
+#define N25Q128A_SR_WREN                     ((uint8_t)0x02)    /*!< Write enable latch */
+#define N25Q128A_SR_BLOCKPR                  ((uint8_t)0x5C)    /*!< Block protected against program and erase operations */
+#define N25Q128A_SR_PRBOTTOM                 ((uint8_t)0x20)    /*!< Protected memory area defined by BLOCKPR starts from top or bottom */
+#define N25Q128A_SR_SRWREN                   ((uint8_t)0x80)    /*!< Status register write enable/disable */
+
+/* Nonvolatile Configuration Register */
+#define N25Q128A_NVCR_LOCK                   ((uint16_t)0x0001) /*!< Lock nonvolatile configuration register */
+#define N25Q128A_NVCR_DUAL                   ((uint16_t)0x0004) /*!< Dual I/O protocol */
+#define N25Q128A_NVCR_QUAB                   ((uint16_t)0x0008) /*!< Quad I/O protocol */
+#define N25Q128A_NVCR_RH                     ((uint16_t)0x0010) /*!< Reset/hold */
+#define N25Q128A_NVCR_ODS                    ((uint16_t)0x01C0) /*!< Output driver strength */
+#define N25Q128A_NVCR_XIP                    ((uint16_t)0x0E00) /*!< XIP mode at power-on reset */
+#define N25Q128A_NVCR_NB_DUMMY               ((uint16_t)0xF000) /*!< Number of dummy clock cycles */
+
+/* Volatile Configuration Register */
+#define N25Q128A_VCR_WRAP                    ((uint8_t)0x03)    /*!< Wrap */
+#define N25Q128A_VCR_XIP                     ((uint8_t)0x08)    /*!< XIP */
+#define N25Q128A_VCR_NB_DUMMY                ((uint8_t)0xF0)    /*!< Number of dummy clock cycles */
+
+/* Enhanced Volatile Configuration Register */
+#define N25Q128A_EVCR_ODS                    ((uint8_t)0x07)    /*!< Output driver strength */
+#define N25Q128A_EVCR_VPPA                   ((uint8_t)0x08)    /*!< Vpp accelerator */
+#define N25Q128A_EVCR_RH                     ((uint8_t)0x10)    /*!< Reset/hold */
+#define N25Q128A_EVCR_DUAL                   ((uint8_t)0x40)    /*!< Dual I/O protocol */
+#define N25Q128A_EVCR_QUAD                   ((uint8_t)0x80)    /*!< Quad I/O protocol */
+
+/* Flag Status Register */
+#define N25Q128A_FSR_PRERR                   ((uint8_t)0x02)    /*!< Protection error */
+#define N25Q128A_FSR_PGSUS                   ((uint8_t)0x04)    /*!< Program operation suspended */
+#define N25Q128A_FSR_VPPERR                  ((uint8_t)0x08)    /*!< Invalid voltage during program or erase */
+#define N25Q128A_FSR_PGERR                   ((uint8_t)0x10)    /*!< Program error */
+#define N25Q128A_FSR_ERERR                   ((uint8_t)0x20)    /*!< Erase error */
+#define N25Q128A_FSR_ERSUS                   ((uint8_t)0x40)    /*!< Erase operation suspended */
+#define N25Q128A_FSR_READY                   ((uint8_t)0x80)    /*!< Ready or command in progress */
+
+/**
+  * @}
+  */
+  
+/** @defgroup N25Q128A_Exported_Functions
+  * @{
+  */ 
+/**
+  * @}
+  */ 
+      
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */
+  
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __N25Q128A_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Drivers/BSP/Components/nt35510/Release_Notes.html b/Drivers/BSP/Components/nt35510/Release_Notes.html
new file mode 100644
index 0000000..b36db70
--- /dev/null
+++ b/Drivers/BSP/Components/nt35510/Release_Notes.html
@@ -0,0 +1,55 @@
+<!DOCTYPE html>
+<html xmlns="http://www.w3.org/1999/xhtml" lang="en" xml:lang="en">
+<head>
+  <meta charset="utf-8" />
+  <meta name="generator" content="pandoc" />
+  <meta name="viewport" content="width=device-width, initial-scale=1.0, user-scalable=yes" />
+  <title>Release Notes for NT35510 Component Drivers</title>
+  <style>
+      code{white-space: pre-wrap;}
+      span.smallcaps{font-variant: small-caps;}
+      span.underline{text-decoration: underline;}
+      div.column{display: inline-block; vertical-align: top; width: 50%;}
+  </style>
+  <link rel="stylesheet" href="_htmresc/mini-st.css" />
+  <!--[if lt IE 9]>
+    <script src="//cdnjs.cloudflare.com/ajax/libs/html5shiv/3.7.3/html5shiv-printshiv.min.js"></script>
+  <![endif]-->
+</head>
+<body>
+<div class="row">
+<div class="col-sm-12 col-lg-4">
+<div class="card fluid">
+<div class="sectione dark">
+<center>
+<h1 id="release-notes-for-nt35510-component-drivers"><small>Release Notes for</small> <mark>NT35510 Component Drivers</mark></h1>
+<p>Copyright © 2020 STMicroelectronics<br />
+</p>
+<a href="https://www.st.com" class="logo"><img src="_htmresc/st_logo.png" alt="ST logo" /></a>
+</center>
+</div>
+</div>
+<h1 id="license">License</h1>
+<p>Licensed by ST under BSD 3-Clause license (the "License"). You may not use this package except in compliance with the License. You may obtain a copy of the License at:</p>
+<p><a href="https://opensource.org/licenses/BSD-3-Clause">https://opensource.org/licenses/BSD-3-Clause</a></p>
+<h1 id="purpose">Purpose</h1>
+<p>This directory contains the NT35510 LCD DSI component drivers.</p>
+</div>
+<div class="col-sm-12 col-lg-8">
+<h1 id="update-history">Update History</h1>
+<div class="collapse">
+<input type="checkbox" id="collapse-section1_0_0" checked aria-hidden="true"> <label for="collapse-section1_0_0" aria-hidden="true">V1.0.0 / 11-December-2020</label>
+<div>
+<h2 id="main-changes">Main Changes</h2>
+<ul>
+<li>First official release</li>
+</ul>
+</div>
+</div>
+</div>
+</div>
+<footer class="sticky">
+For complete documentation on <mark>STM32 Microcontrollers</mark> , visit: <a href="http://www.st.com/STM32">http://www.st.com/STM32</a>
+</footer>
+</body>
+</html>
diff --git a/Drivers/BSP/Components/nt35510/_htmresc/mini-st.css b/Drivers/BSP/Components/nt35510/_htmresc/mini-st.css
new file mode 100644
index 0000000..9b2d0a9
--- /dev/null
+++ b/Drivers/BSP/Components/nt35510/_htmresc/mini-st.css
@@ -0,0 +1,1700 @@
+@charset "UTF-8";
+/*
+  Flavor name: Default (mini-default)
+  Author: Angelos Chalaris (chalarangelo@gmail.com)
+  Maintainers: Angelos Chalaris
+  mini.css version: v3.0.0-alpha.3
+*/
+/*
+  Browsers resets and base typography.
+*/
+/* Core module CSS variable definitions */
+:root {
+  --fore-color: #111;
+  --secondary-fore-color: #444;
+  --back-color: #f8f8f8;
+  --secondary-back-color: #f0f0f0;
+  --blockquote-color: #f57c00;
+  --pre-color: #1565c0;
+  --border-color: #aaa;
+  --secondary-border-color: #ddd;
+  --heading-ratio: 1.19;
+  --universal-margin: 0.5rem;
+  --universal-padding: 0.125rem;
+  --universal-border-radius: 0.125rem;
+  --a-link-color: #0277bd;
+  --a-visited-color: #01579b; }
+
+html {
+  font-size: 14px; }
+
+a, b, del, em, i, ins, q, span, strong, u {
+  font-size: 1em; }
+
+html, * {
+  font-family: -apple-system, BlinkMacSystemFont, "Segoe UI", Roboto, Ubuntu, "Helvetica Neue", Helvetica, sans-serif;
+  line-height: 1.4;
+  -webkit-text-size-adjust: 100%; }
+
+* {
+  font-size: 1rem; }
+
+body {
+  margin: 0;
+  color: var(--fore-color);
+  background: var(--back-color); }
+
+details {
+  display: block; }
+
+summary {
+  display: list-item; }
+
+abbr[title] {
+  border-bottom: none;
+  text-decoration: underline dotted; }
+
+input {
+  overflow: visible; }
+
+img {
+  max-width: 100%;
+  height: auto; }
+
+h1, h2, h3, h4, h5, h6 {
+  line-height: 1.2;
+  margin: calc(1.5 * var(--universal-margin)) var(--universal-margin);
+  font-weight: 500; }
+  h1 small, h2 small, h3 small, h4 small, h5 small, h6 small {
+    color: var(--secondary-fore-color);
+    display: block;
+    margin-top: -0.25rem; }
+
+h1 {
+  font-size: calc(1rem * var(--heading-ratio) * var(--heading-ratio) * var(--heading-ratio)); }
+
+h2 {
+  font-size: calc(1rem * var(--heading-ratio) * var(--heading-ratio); );
+  background: var(--mark-back-color);
+  font-weight: 600;
+  padding: 0.1em 0.5em 0.2em 0.5em;
+  color: var(--mark-fore-color); }
+
+h3 {
+  font-size: calc(1rem * var(--heading-ratio));
+  padding-left: calc(2 * var(--universal-margin)); 
+  /* background: var(--border-color); */
+    }
+
+h4 {
+  font-size: 1rem;);
+  padding-left: calc(4 * var(--universal-margin));  }
+
+h5 {
+  font-size: 1rem; }
+
+h6 {
+  font-size: calc(1rem / var(--heading-ratio)); }
+
+p {
+  margin: var(--universal-margin); }
+
+ol, ul {
+  margin: var(--universal-margin);
+  padding-left: calc(6 * var(--universal-margin)); }
+
+b, strong {
+  font-weight: 700; }
+
+hr {
+  box-sizing: content-box;
+  border: 0;
+  line-height: 1.25em;
+  margin: var(--universal-margin);
+  height: 0.0625rem;
+  background: linear-gradient(to right, transparent, var(--border-color) 20%, var(--border-color) 80%, transparent); }
+
+blockquote {
+  display: block;
+  position: relative;
+  font-style: italic;
+  color: var(--secondary-fore-color);
+  margin: var(--universal-margin);
+  padding: calc(3 * var(--universal-padding));
+  border: 0.0625rem solid var(--secondary-border-color);
+  border-left: 0.375rem solid var(--blockquote-color);
+  border-radius: 0 var(--universal-border-radius) var(--universal-border-radius) 0; }
+  blockquote:before {
+    position: absolute;
+    top: calc(0rem - var(--universal-padding));
+    left: 0;
+    font-family: sans-serif;
+    font-size: 3rem;
+    font-weight: 700;
+    content: "\201c";
+    color: var(--blockquote-color); }
+  blockquote[cite]:after {
+    font-style: normal;
+    font-size: 0.75em;
+    font-weight: 700;
+    content: "\a—  " attr(cite);
+    white-space: pre; }
+
+code, kbd, pre, samp {
+  font-family: Menlo, Consolas, monospace;
+  font-size: 0.85em; }
+
+code {
+  background: var(--secondary-back-color);
+  border-radius: var(--universal-border-radius);
+  padding: calc(var(--universal-padding) / 4) calc(var(--universal-padding) / 2); }
+
+kbd {
+  background: var(--fore-color);
+  color: var(--back-color);
+  border-radius: var(--universal-border-radius);
+  padding: calc(var(--universal-padding) / 4) calc(var(--universal-padding) / 2); }
+
+pre {
+  overflow: auto;
+  background: var(--secondary-back-color);
+  padding: calc(1.5 * var(--universal-padding));
+  margin: var(--universal-margin);
+  border: 0.0625rem solid var(--secondary-border-color);
+  border-left: 0.25rem solid var(--pre-color);
+  border-radius: 0 var(--universal-border-radius) var(--universal-border-radius) 0; }
+
+sup, sub, code, kbd {
+  line-height: 0;
+  position: relative;
+  vertical-align: baseline; }
+
+small, sup, sub, figcaption {
+  font-size: 0.75em; }
+
+sup {
+  top: -0.5em; }
+
+sub {
+  bottom: -0.25em; }
+
+figure {
+  margin: var(--universal-margin); }
+
+figcaption {
+  color: var(--secondary-fore-color); }
+
+a {
+  text-decoration: none; }
+  a:link {
+    color: var(--a-link-color); }
+  a:visited {
+    color: var(--a-visited-color); }
+  a:hover, a:focus {
+    text-decoration: underline; }
+
+/*
+  Definitions for the grid system, cards and containers.
+*/
+.container {
+  margin: 0 auto;
+  padding: 0 calc(1.5 * var(--universal-padding)); }
+
+.row {
+  box-sizing: border-box;
+  display: flex;
+  flex: 0 1 auto;
+  flex-flow: row wrap; }
+
+.col-sm,
+[class^='col-sm-'],
+[class^='col-sm-offset-'],
+.row[class*='cols-sm-'] > * {
+  box-sizing: border-box;
+  flex: 0 0 auto;
+  padding: 0 calc(var(--universal-padding) / 2); }
+
+.col-sm,
+.row.cols-sm > * {
+  max-width: 100%;
+  flex-grow: 1;
+  flex-basis: 0; }
+
+.col-sm-1,
+.row.cols-sm-1 > * {
+  max-width: 8.3333333333%;
+  flex-basis: 8.3333333333%; }
+
+.col-sm-offset-0 {
+  margin-left: 0; }
+
+.col-sm-2,
+.row.cols-sm-2 > * {
+  max-width: 16.6666666667%;
+  flex-basis: 16.6666666667%; }
+
+.col-sm-offset-1 {
+  margin-left: 8.3333333333%; }
+
+.col-sm-3,
+.row.cols-sm-3 > * {
+  max-width: 25%;
+  flex-basis: 25%; }
+
+.col-sm-offset-2 {
+  margin-left: 16.6666666667%; }
+
+.col-sm-4,
+.row.cols-sm-4 > * {
+  max-width: 33.3333333333%;
+  flex-basis: 33.3333333333%; }
+
+.col-sm-offset-3 {
+  margin-left: 25%; }
+
+.col-sm-5,
+.row.cols-sm-5 > * {
+  max-width: 41.6666666667%;
+  flex-basis: 41.6666666667%; }
+
+.col-sm-offset-4 {
+  margin-left: 33.3333333333%; }
+
+.col-sm-6,
+.row.cols-sm-6 > * {
+  max-width: 50%;
+  flex-basis: 50%; }
+
+.col-sm-offset-5 {
+  margin-left: 41.6666666667%; }
+
+.col-sm-7,
+.row.cols-sm-7 > * {
+  max-width: 58.3333333333%;
+  flex-basis: 58.3333333333%; }
+
+.col-sm-offset-6 {
+  margin-left: 50%; }
+
+.col-sm-8,
+.row.cols-sm-8 > * {
+  max-width: 66.6666666667%;
+  flex-basis: 66.6666666667%; }
+
+.col-sm-offset-7 {
+  margin-left: 58.3333333333%; }
+
+.col-sm-9,
+.row.cols-sm-9 > * {
+  max-width: 75%;
+  flex-basis: 75%; }
+
+.col-sm-offset-8 {
+  margin-left: 66.6666666667%; }
+
+.col-sm-10,
+.row.cols-sm-10 > * {
+  max-width: 83.3333333333%;
+  flex-basis: 83.3333333333%; }
+
+.col-sm-offset-9 {
+  margin-left: 75%; }
+
+.col-sm-11,
+.row.cols-sm-11 > * {
+  max-width: 91.6666666667%;
+  flex-basis: 91.6666666667%; }
+
+.col-sm-offset-10 {
+  margin-left: 83.3333333333%; }
+
+.col-sm-12,
+.row.cols-sm-12 > * {
+  max-width: 100%;
+  flex-basis: 100%; }
+
+.col-sm-offset-11 {
+  margin-left: 91.6666666667%; }
+
+.col-sm-normal {
+  order: initial; }
+
+.col-sm-first {
+  order: -999; }
+
+.col-sm-last {
+  order: 999; }
+
+@media screen and (min-width: 500px) {
+  .col-md,
+  [class^='col-md-'],
+  [class^='col-md-offset-'],
+  .row[class*='cols-md-'] > * {
+    box-sizing: border-box;
+    flex: 0 0 auto;
+    padding: 0 calc(var(--universal-padding) / 2); }
+
+  .col-md,
+  .row.cols-md > * {
+    max-width: 100%;
+    flex-grow: 1;
+    flex-basis: 0; }
+
+  .col-md-1,
+  .row.cols-md-1 > * {
+    max-width: 8.3333333333%;
+    flex-basis: 8.3333333333%; }
+
+  .col-md-offset-0 {
+    margin-left: 0; }
+
+  .col-md-2,
+  .row.cols-md-2 > * {
+    max-width: 16.6666666667%;
+    flex-basis: 16.6666666667%; }
+
+  .col-md-offset-1 {
+    margin-left: 8.3333333333%; }
+
+  .col-md-3,
+  .row.cols-md-3 > * {
+    max-width: 25%;
+    flex-basis: 25%; }
+
+  .col-md-offset-2 {
+    margin-left: 16.6666666667%; }
+
+  .col-md-4,
+  .row.cols-md-4 > * {
+    max-width: 33.3333333333%;
+    flex-basis: 33.3333333333%; }
+
+  .col-md-offset-3 {
+    margin-left: 25%; }
+
+  .col-md-5,
+  .row.cols-md-5 > * {
+    max-width: 41.6666666667%;
+    flex-basis: 41.6666666667%; }
+
+  .col-md-offset-4 {
+    margin-left: 33.3333333333%; }
+
+  .col-md-6,
+  .row.cols-md-6 > * {
+    max-width: 50%;
+    flex-basis: 50%; }
+
+  .col-md-offset-5 {
+    margin-left: 41.6666666667%; }
+
+  .col-md-7,
+  .row.cols-md-7 > * {
+    max-width: 58.3333333333%;
+    flex-basis: 58.3333333333%; }
+
+  .col-md-offset-6 {
+    margin-left: 50%; }
+
+  .col-md-8,
+  .row.cols-md-8 > * {
+    max-width: 66.6666666667%;
+    flex-basis: 66.6666666667%; }
+
+  .col-md-offset-7 {
+    margin-left: 58.3333333333%; }
+
+  .col-md-9,
+  .row.cols-md-9 > * {
+    max-width: 75%;
+    flex-basis: 75%; }
+
+  .col-md-offset-8 {
+    margin-left: 66.6666666667%; }
+
+  .col-md-10,
+  .row.cols-md-10 > * {
+    max-width: 83.3333333333%;
+    flex-basis: 83.3333333333%; }
+
+  .col-md-offset-9 {
+    margin-left: 75%; }
+
+  .col-md-11,
+  .row.cols-md-11 > * {
+    max-width: 91.6666666667%;
+    flex-basis: 91.6666666667%; }
+
+  .col-md-offset-10 {
+    margin-left: 83.3333333333%; }
+
+  .col-md-12,
+  .row.cols-md-12 > * {
+    max-width: 100%;
+    flex-basis: 100%; }
+
+  .col-md-offset-11 {
+    margin-left: 91.6666666667%; }
+
+  .col-md-normal {
+    order: initial; }
+
+  .col-md-first {
+    order: -999; }
+
+  .col-md-last {
+    order: 999; } }
+@media screen and (min-width: 1280px) {
+  .col-lg,
+  [class^='col-lg-'],
+  [class^='col-lg-offset-'],
+  .row[class*='cols-lg-'] > * {
+    box-sizing: border-box;
+    flex: 0 0 auto;
+    padding: 0 calc(var(--universal-padding) / 2); }
+
+  .col-lg,
+  .row.cols-lg > * {
+    max-width: 100%;
+    flex-grow: 1;
+    flex-basis: 0; }
+
+  .col-lg-1,
+  .row.cols-lg-1 > * {
+    max-width: 8.3333333333%;
+    flex-basis: 8.3333333333%; }
+
+  .col-lg-offset-0 {
+    margin-left: 0; }
+
+  .col-lg-2,
+  .row.cols-lg-2 > * {
+    max-width: 16.6666666667%;
+    flex-basis: 16.6666666667%; }
+
+  .col-lg-offset-1 {
+    margin-left: 8.3333333333%; }
+
+  .col-lg-3,
+  .row.cols-lg-3 > * {
+    max-width: 25%;
+    flex-basis: 25%; }
+
+  .col-lg-offset-2 {
+    margin-left: 16.6666666667%; }
+
+  .col-lg-4,
+  .row.cols-lg-4 > * {
+    max-width: 33.3333333333%;
+    flex-basis: 33.3333333333%; }
+
+  .col-lg-offset-3 {
+    margin-left: 25%; }
+
+  .col-lg-5,
+  .row.cols-lg-5 > * {
+    max-width: 41.6666666667%;
+    flex-basis: 41.6666666667%; }
+
+  .col-lg-offset-4 {
+    margin-left: 33.3333333333%; }
+
+  .col-lg-6,
+  .row.cols-lg-6 > * {
+    max-width: 50%;
+    flex-basis: 50%; }
+
+  .col-lg-offset-5 {
+    margin-left: 41.6666666667%; }
+
+  .col-lg-7,
+  .row.cols-lg-7 > * {
+    max-width: 58.3333333333%;
+    flex-basis: 58.3333333333%; }
+
+  .col-lg-offset-6 {
+    margin-left: 50%; }
+
+  .col-lg-8,
+  .row.cols-lg-8 > * {
+    max-width: 66.6666666667%;
+    flex-basis: 66.6666666667%; }
+
+  .col-lg-offset-7 {
+    margin-left: 58.3333333333%; }
+
+  .col-lg-9,
+  .row.cols-lg-9 > * {
+    max-width: 75%;
+    flex-basis: 75%; }
+
+  .col-lg-offset-8 {
+    margin-left: 66.6666666667%; }
+
+  .col-lg-10,
+  .row.cols-lg-10 > * {
+    max-width: 83.3333333333%;
+    flex-basis: 83.3333333333%; }
+
+  .col-lg-offset-9 {
+    margin-left: 75%; }
+
+  .col-lg-11,
+  .row.cols-lg-11 > * {
+    max-width: 91.6666666667%;
+    flex-basis: 91.6666666667%; }
+
+  .col-lg-offset-10 {
+    margin-left: 83.3333333333%; }
+
+  .col-lg-12,
+  .row.cols-lg-12 > * {
+    max-width: 100%;
+    flex-basis: 100%; }
+
+  .col-lg-offset-11 {
+    margin-left: 91.6666666667%; }
+
+  .col-lg-normal {
+    order: initial; }
+
+  .col-lg-first {
+    order: -999; }
+
+  .col-lg-last {
+    order: 999; } }
+/* Card component CSS variable definitions */
+:root {
+  --card-back-color: #f8f8f8;
+  --card-fore-color: #111;
+  --card-border-color: #ddd; }
+
+.card {
+  display: flex;
+  flex-direction: column;
+  justify-content: space-between;
+  align-self: center;
+  position: relative;
+  width: 100%;
+  background: var(--card-back-color);
+  color: var(--card-fore-color);
+  border: 0.0625rem solid var(--card-border-color);
+  border-radius: var(--universal-border-radius);
+  margin: var(--universal-margin);
+  overflow: hidden; }
+  @media screen and (min-width: 320px) {
+    .card {
+      max-width: 320px; } }
+  .card > .sectione {
+    background: var(--card-back-color);
+    color: var(--card-fore-color);
+    box-sizing: border-box;
+    margin: 0;
+    border: 0;
+    border-radius: 0;
+    border-bottom: 0.0625rem solid var(--card-border-color);
+    padding: var(--universal-padding);
+    width: 100%; }
+    .card > .sectione.media {
+      height: 200px;
+      padding: 0;
+      -o-object-fit: cover;
+      object-fit: cover; }
+  .card > .sectione:last-child {
+    border-bottom: 0; }
+
+/*
+  Custom elements for card elements.
+*/
+@media screen and (min-width: 240px) {
+  .card.small {
+    max-width: 240px; } }
+@media screen and (min-width: 480px) {
+  .card.large {
+    max-width: 480px; } }
+.card.fluid {
+  max-width: 100%;
+  width: auto; }
+
+.card.warning {
+/*  --card-back-color: #ffca28; */
+  --card-back-color: #e5b8b7;
+  --card-border-color: #e8b825; }
+
+.card.error {
+  --card-back-color: #b71c1c;
+  --card-fore-color: #f8f8f8;
+  --card-border-color: #a71a1a; }
+
+.card > .sectione.dark {
+  --card-back-color: #e0e0e0; }
+
+.card > .sectione.double-padded {
+  padding: calc(1.5 * var(--universal-padding)); }
+
+/*
+  Definitions for forms and input elements.
+*/
+/* Input_control module CSS variable definitions */
+:root {
+  --form-back-color: #f0f0f0;
+  --form-fore-color: #111;
+  --form-border-color: #ddd;
+  --input-back-color: #f8f8f8;
+  --input-fore-color: #111;
+  --input-border-color: #ddd;
+  --input-focus-color: #0288d1;
+  --input-invalid-color: #d32f2f;
+  --button-back-color: #e2e2e2;
+  --button-hover-back-color: #dcdcdc;
+  --button-fore-color: #212121;
+  --button-border-color: transparent;
+  --button-hover-border-color: transparent;
+  --button-group-border-color: rgba(124, 124, 124, 0.54); }
+
+form {
+  background: var(--form-back-color);
+  color: var(--form-fore-color);
+  border: 0.0625rem solid var(--form-border-color);
+  border-radius: var(--universal-border-radius);
+  margin: var(--universal-margin);
+  padding: calc(2 * var(--universal-padding)) var(--universal-padding); }
+
+fieldset {
+  border: 0.0625rem solid var(--form-border-color);
+  border-radius: var(--universal-border-radius);
+  margin: calc(var(--universal-margin) / 4);
+  padding: var(--universal-padding); }
+
+legend {
+  box-sizing: border-box;
+  display: table;
+  max-width: 100%;
+  white-space: normal;
+  font-weight: 700;
+  padding: calc(var(--universal-padding) / 2); }
+
+label {
+  padding: calc(var(--universal-padding) / 2) var(--universal-padding); }
+
+.input-group {
+  display: inline-block; }
+  .input-group.fluid {
+    display: flex;
+    align-items: center;
+    justify-content: center; }
+    .input-group.fluid > input {
+      max-width: 100%;
+      flex-grow: 1;
+      flex-basis: 0px; }
+    @media screen and (max-width: 499px) {
+      .input-group.fluid {
+        align-items: stretch;
+        flex-direction: column; } }
+  .input-group.vertical {
+    display: flex;
+    align-items: stretch;
+    flex-direction: column; }
+    .input-group.vertical > input {
+      max-width: 100%;
+      flex-grow: 1;
+      flex-basis: 0px; }
+
+[type="number"]::-webkit-inner-spin-button, [type="number"]::-webkit-outer-spin-button {
+  height: auto; }
+
+[type="search"] {
+  -webkit-appearance: textfield;
+  outline-offset: -2px; }
+
+[type="search"]::-webkit-search-cancel-button,
+[type="search"]::-webkit-search-decoration {
+  -webkit-appearance: none; }
+
+input:not([type]), [type="text"], [type="email"], [type="number"], [type="search"],
+[type="password"], [type="url"], [type="tel"], [type="checkbox"], [type="radio"], textarea, select {
+  box-sizing: border-box;
+  background: var(--input-back-color);
+  color: var(--input-fore-color);
+  border: 0.0625rem solid var(--input-border-color);
+  border-radius: var(--universal-border-radius);
+  margin: calc(var(--universal-margin) / 2);
+  padding: var(--universal-padding) calc(1.5 * var(--universal-padding)); }
+
+input:not([type="button"]):not([type="submit"]):not([type="reset"]):hover, input:not([type="button"]):not([type="submit"]):not([type="reset"]):focus, textarea:hover, textarea:focus, select:hover, select:focus {
+  border-color: var(--input-focus-color);
+  box-shadow: none; }
+input:not([type="button"]):not([type="submit"]):not([type="reset"]):invalid, input:not([type="button"]):not([type="submit"]):not([type="reset"]):focus:invalid, textarea:invalid, textarea:focus:invalid, select:invalid, select:focus:invalid {
+  border-color: var(--input-invalid-color);
+  box-shadow: none; }
+input:not([type="button"]):not([type="submit"]):not([type="reset"])[readonly], textarea[readonly], select[readonly] {
+  background: var(--secondary-back-color); }
+
+select {
+  max-width: 100%; }
+
+option {
+  overflow: hidden;
+  text-overflow: ellipsis; }
+
+[type="checkbox"], [type="radio"] {
+  -webkit-appearance: none;
+  -moz-appearance: none;
+  appearance: none;
+  position: relative;
+  height: calc(1rem + var(--universal-padding) / 2);
+  width: calc(1rem + var(--universal-padding) / 2);
+  vertical-align: text-bottom;
+  padding: 0;
+  flex-basis: calc(1rem + var(--universal-padding) / 2) !important;
+  flex-grow: 0 !important; }
+  [type="checkbox"]:checked:before, [type="radio"]:checked:before {
+    position: absolute; }
+
+[type="checkbox"]:checked:before {
+  content: '\2713';
+  font-family: sans-serif;
+  font-size: calc(1rem + var(--universal-padding) / 2);
+  top: calc(0rem - var(--universal-padding));
+  left: calc(var(--universal-padding) / 4); }
+
+[type="radio"] {
+  border-radius: 100%; }
+  [type="radio"]:checked:before {
+    border-radius: 100%;
+    content: '';
+    top: calc(0.0625rem + var(--universal-padding) / 2);
+    left: calc(0.0625rem + var(--universal-padding) / 2);
+    background: var(--input-fore-color);
+    width: 0.5rem;
+    height: 0.5rem; }
+
+:placeholder-shown {
+  color: var(--input-fore-color); }
+
+::-ms-placeholder {
+  color: var(--input-fore-color);
+  opacity: 0.54; }
+
+button::-moz-focus-inner, [type="button"]::-moz-focus-inner, [type="reset"]::-moz-focus-inner, [type="submit"]::-moz-focus-inner {
+  border-style: none;
+  padding: 0; }
+
+button, html [type="button"], [type="reset"], [type="submit"] {
+  -webkit-appearance: button; }
+
+button {
+  overflow: visible;
+  text-transform: none; }
+
+button, [type="button"], [type="submit"], [type="reset"],
+a.button, label.button, .button,
+a[role="button"], label[role="button"], [role="button"] {
+  display: inline-block;
+  background: var(--button-back-color);
+  color: var(--button-fore-color);
+  border: 0.0625rem solid var(--button-border-color);
+  border-radius: var(--universal-border-radius);
+  padding: var(--universal-padding) calc(1.5 * var(--universal-padding));
+  margin: var(--universal-margin);
+  text-decoration: none;
+  cursor: pointer;
+  transition: background 0.3s; }
+  button:hover, button:focus, [type="button"]:hover, [type="button"]:focus, [type="submit"]:hover, [type="submit"]:focus, [type="reset"]:hover, [type="reset"]:focus,
+  a.button:hover,
+  a.button:focus, label.button:hover, label.button:focus, .button:hover, .button:focus,
+  a[role="button"]:hover,
+  a[role="button"]:focus, label[role="button"]:hover, label[role="button"]:focus, [role="button"]:hover, [role="button"]:focus {
+    background: var(--button-hover-back-color);
+    border-color: var(--button-hover-border-color); }
+
+input:disabled, input[disabled], textarea:disabled, textarea[disabled], select:disabled, select[disabled], button:disabled, button[disabled], .button:disabled, .button[disabled], [role="button"]:disabled, [role="button"][disabled] {
+  cursor: not-allowed;
+  opacity: 0.75; }
+
+.button-group {
+  display: flex;
+  border: 0.0625rem solid var(--button-group-border-color);
+  border-radius: var(--universal-border-radius);
+  margin: var(--universal-margin); }
+  .button-group > button, .button-group [type="button"], .button-group > [type="submit"], .button-group > [type="reset"], .button-group > .button, .button-group > [role="button"] {
+    margin: 0;
+    max-width: 100%;
+    flex: 1 1 auto;
+    text-align: center;
+    border: 0;
+    border-radius: 0;
+    box-shadow: none; }
+  .button-group > :not(:first-child) {
+    border-left: 0.0625rem solid var(--button-group-border-color); }
+  @media screen and (max-width: 499px) {
+    .button-group {
+      flex-direction: column; }
+      .button-group > :not(:first-child) {
+        border: 0;
+        border-top: 0.0625rem solid var(--button-group-border-color); } }
+
+/*
+  Custom elements for forms and input elements.
+*/
+button.primary, [type="button"].primary, [type="submit"].primary, [type="reset"].primary, .button.primary, [role="button"].primary {
+  --button-back-color: #1976d2;
+  --button-fore-color: #f8f8f8; }
+  button.primary:hover, button.primary:focus, [type="button"].primary:hover, [type="button"].primary:focus, [type="submit"].primary:hover, [type="submit"].primary:focus, [type="reset"].primary:hover, [type="reset"].primary:focus, .button.primary:hover, .button.primary:focus, [role="button"].primary:hover, [role="button"].primary:focus {
+    --button-hover-back-color: #1565c0; }
+
+button.secondary, [type="button"].secondary, [type="submit"].secondary, [type="reset"].secondary, .button.secondary, [role="button"].secondary {
+  --button-back-color: #d32f2f;
+  --button-fore-color: #f8f8f8; }
+  button.secondary:hover, button.secondary:focus, [type="button"].secondary:hover, [type="button"].secondary:focus, [type="submit"].secondary:hover, [type="submit"].secondary:focus, [type="reset"].secondary:hover, [type="reset"].secondary:focus, .button.secondary:hover, .button.secondary:focus, [role="button"].secondary:hover, [role="button"].secondary:focus {
+    --button-hover-back-color: #c62828; }
+
+button.tertiary, [type="button"].tertiary, [type="submit"].tertiary, [type="reset"].tertiary, .button.tertiary, [role="button"].tertiary {
+  --button-back-color: #308732;
+  --button-fore-color: #f8f8f8; }
+  button.tertiary:hover, button.tertiary:focus, [type="button"].tertiary:hover, [type="button"].tertiary:focus, [type="submit"].tertiary:hover, [type="submit"].tertiary:focus, [type="reset"].tertiary:hover, [type="reset"].tertiary:focus, .button.tertiary:hover, .button.tertiary:focus, [role="button"].tertiary:hover, [role="button"].tertiary:focus {
+    --button-hover-back-color: #277529; }
+
+button.inverse, [type="button"].inverse, [type="submit"].inverse, [type="reset"].inverse, .button.inverse, [role="button"].inverse {
+  --button-back-color: #212121;
+  --button-fore-color: #f8f8f8; }
+  button.inverse:hover, button.inverse:focus, [type="button"].inverse:hover, [type="button"].inverse:focus, [type="submit"].inverse:hover, [type="submit"].inverse:focus, [type="reset"].inverse:hover, [type="reset"].inverse:focus, .button.inverse:hover, .button.inverse:focus, [role="button"].inverse:hover, [role="button"].inverse:focus {
+    --button-hover-back-color: #111; }
+
+button.small, [type="button"].small, [type="submit"].small, [type="reset"].small, .button.small, [role="button"].small {
+  padding: calc(0.5 * var(--universal-padding)) calc(0.75 * var(--universal-padding));
+  margin: var(--universal-margin); }
+
+button.large, [type="button"].large, [type="submit"].large, [type="reset"].large, .button.large, [role="button"].large {
+  padding: calc(1.5 * var(--universal-padding)) calc(2 * var(--universal-padding));
+  margin: var(--universal-margin); }
+
+/*
+  Definitions for navigation elements.
+*/
+/* Navigation module CSS variable definitions */
+:root {
+  --header-back-color: #f8f8f8;
+  --header-hover-back-color: #f0f0f0;
+  --header-fore-color: #444;
+  --header-border-color: #ddd;
+  --nav-back-color: #f8f8f8;
+  --nav-hover-back-color: #f0f0f0;
+  --nav-fore-color: #444;
+  --nav-border-color: #ddd;
+  --nav-link-color: #0277bd;
+  --footer-fore-color: #444;
+  --footer-back-color: #f8f8f8;
+  --footer-border-color: #ddd;
+  --footer-link-color: #0277bd;
+  --drawer-back-color: #f8f8f8;
+  --drawer-hover-back-color: #f0f0f0;
+  --drawer-border-color: #ddd;
+  --drawer-close-color: #444; }
+
+header {
+  height: 3.1875rem;
+  background: var(--header-back-color);
+  color: var(--header-fore-color);
+  border-bottom: 0.0625rem solid var(--header-border-color);
+  padding: calc(var(--universal-padding) / 4) 0;
+  white-space: nowrap;
+  overflow-x: auto;
+  overflow-y: hidden; }
+  header.row {
+    box-sizing: content-box; }
+  header .logo {
+    color: var(--header-fore-color);
+    font-size: 1.75rem;
+    padding: var(--universal-padding) calc(2 * var(--universal-padding));
+    text-decoration: none; }
+  header button, header [type="button"], header .button, header [role="button"] {
+    box-sizing: border-box;
+    position: relative;
+    top: calc(0rem - var(--universal-padding) / 4);
+    height: calc(3.1875rem + var(--universal-padding) / 2);
+    background: var(--header-back-color);
+    line-height: calc(3.1875rem - var(--universal-padding) * 1.5);
+    text-align: center;
+    color: var(--header-fore-color);
+    border: 0;
+    border-radius: 0;
+    margin: 0;
+    text-transform: uppercase; }
+    header button:hover, header button:focus, header [type="button"]:hover, header [type="button"]:focus, header .button:hover, header .button:focus, header [role="button"]:hover, header [role="button"]:focus {
+      background: var(--header-hover-back-color); }
+
+nav {
+  background: var(--nav-back-color);
+  color: var(--nav-fore-color);
+  border: 0.0625rem solid var(--nav-border-color);
+  border-radius: var(--universal-border-radius);
+  margin: var(--universal-margin); }
+  nav * {
+    padding: var(--universal-padding) calc(1.5 * var(--universal-padding)); }
+  nav a, nav a:visited {
+    display: block;
+    color: var(--nav-link-color);
+    border-radius: var(--universal-border-radius);
+    transition: background 0.3s; }
+    nav a:hover, nav a:focus, nav a:visited:hover, nav a:visited:focus {
+      text-decoration: none;
+      background: var(--nav-hover-back-color); }
+  nav .sublink-1 {
+    position: relative;
+    margin-left: calc(2 * var(--universal-padding)); }
+    nav .sublink-1:before {
+      position: absolute;
+      left: calc(var(--universal-padding) - 1 * var(--universal-padding));
+      top: -0.0625rem;
+      content: '';
+      height: 100%;
+      border: 0.0625rem solid var(--nav-border-color);
+      border-left: 0; }
+  nav .sublink-2 {
+    position: relative;
+    margin-left: calc(4 * var(--universal-padding)); }
+    nav .sublink-2:before {
+      position: absolute;
+      left: calc(var(--universal-padding) - 3 * var(--universal-padding));
+      top: -0.0625rem;
+      content: '';
+      height: 100%;
+      border: 0.0625rem solid var(--nav-border-color);
+      border-left: 0; }
+
+footer {
+  background: var(--footer-back-color);
+  color: var(--footer-fore-color);
+  border-top: 0.0625rem solid var(--footer-border-color);
+  padding: calc(2 * var(--universal-padding)) var(--universal-padding);
+  font-size: 0.875rem; }
+  footer a, footer a:visited {
+    color: var(--footer-link-color); }
+
+header.sticky {
+  position: -webkit-sticky;
+  position: sticky;
+  z-index: 1101;
+  top: 0; }
+
+footer.sticky {
+  position: -webkit-sticky;
+  position: sticky;
+  z-index: 1101;
+  bottom: 0; }
+
+.drawer-toggle:before {
+  display: inline-block;
+  position: relative;
+  vertical-align: bottom;
+  content: '\00a0\2261\00a0';
+  font-family: sans-serif;
+  font-size: 1.5em; }
+@media screen and (min-width: 500px) {
+  .drawer-toggle:not(.persistent) {
+    display: none; } }
+
+[type="checkbox"].drawer {
+  height: 1px;
+  width: 1px;
+  margin: -1px;
+  overflow: hidden;
+  position: absolute;
+  clip: rect(0 0 0 0);
+  -webkit-clip-path: inset(100%);
+  clip-path: inset(100%); }
+  [type="checkbox"].drawer + * {
+    display: block;
+    box-sizing: border-box;
+    position: fixed;
+    top: 0;
+    width: 320px;
+    height: 100vh;
+    overflow-y: auto;
+    background: var(--drawer-back-color);
+    border: 0.0625rem solid var(--drawer-border-color);
+    border-radius: 0;
+    margin: 0;
+    z-index: 1110;
+    right: -320px;
+    transition: right 0.3s; }
+    [type="checkbox"].drawer + * .drawer-close {
+      position: absolute;
+      top: var(--universal-margin);
+      right: var(--universal-margin);
+      z-index: 1111;
+      width: 2rem;
+      height: 2rem;
+      border-radius: var(--universal-border-radius);
+      padding: var(--universal-padding);
+      margin: 0;
+      cursor: pointer;
+      transition: background 0.3s; }
+      [type="checkbox"].drawer + * .drawer-close:before {
+        display: block;
+        content: '\00D7';
+        color: var(--drawer-close-color);
+        position: relative;
+        font-family: sans-serif;
+        font-size: 2rem;
+        line-height: 1;
+        text-align: center; }
+      [type="checkbox"].drawer + * .drawer-close:hover, [type="checkbox"].drawer + * .drawer-close:focus {
+        background: var(--drawer-hover-back-color); }
+    @media screen and (max-width: 320px) {
+      [type="checkbox"].drawer + * {
+        width: 100%; } }
+  [type="checkbox"].drawer:checked + * {
+    right: 0; }
+  @media screen and (min-width: 500px) {
+    [type="checkbox"].drawer:not(.persistent) + * {
+      position: static;
+      height: 100%;
+      z-index: 1100; }
+      [type="checkbox"].drawer:not(.persistent) + * .drawer-close {
+        display: none; } }
+
+/*
+  Definitions for the responsive table component.
+*/
+/* Table module CSS variable definitions. */
+:root {
+  --table-border-color: #aaa;
+  --table-border-separator-color: #666;
+  --table-head-back-color: #e6e6e6;
+  --table-head-fore-color: #111;
+  --table-body-back-color: #f8f8f8;
+  --table-body-fore-color: #111;
+  --table-body-alt-back-color: #eee; }
+
+table {
+  border-collapse: separate;
+  border-spacing: 0;
+  : margin: calc(1.5 * var(--universal-margin)) var(--universal-margin);
+  display: flex;
+  flex: 0 1 auto;
+  flex-flow: row wrap;
+  padding: var(--universal-padding);
+  padding-top: 0;
+	margin: calc(1.5 * var(--universal-margin)) var(--universal-margin);	}
+  table caption {
+    font-size: 1.25 * rem;
+    margin: calc(2 * var(--universal-margin)) 0;
+    max-width: 100%;
+    flex: 0 0 100%;
+		text-align: left;}
+  table thead, table tbody {
+    display: flex;
+    flex-flow: row wrap;
+    border: 0.0625rem solid var(--table-border-color); }
+  table thead {
+    z-index: 999;
+    border-radius: var(--universal-border-radius) var(--universal-border-radius) 0 0;
+    border-bottom: 0.0625rem solid var(--table-border-separator-color); }
+  table tbody {
+    border-top: 0;
+    margin-top: calc(0 - var(--universal-margin));
+    border-radius: 0 0 var(--universal-border-radius) var(--universal-border-radius); }
+  table tr {
+    display: flex;
+    padding: 0; }
+  table th, table td {
+    padding: calc(0.5 * var(--universal-padding));
+		font-size: 0.9rem; }
+  table th {
+    text-align: left;
+    background: var(--table-head-back-color);
+    color: var(--table-head-fore-color); }
+  table td {
+    background: var(--table-body-back-color);
+    color: var(--table-body-fore-color);
+    border-top: 0.0625rem solid var(--table-border-color); }
+
+table:not(.horizontal) {
+  overflow: auto;
+  max-height: 850px; }
+  table:not(.horizontal) thead, table:not(.horizontal) tbody {
+    max-width: 100%;
+    flex: 0 0 100%; }
+  table:not(.horizontal) tr {
+    flex-flow: row wrap;
+    flex: 0 0 100%; }
+  table:not(.horizontal) th, table:not(.horizontal) td {
+    flex: 1 0 0%;
+    overflow: hidden;
+    text-overflow: ellipsis; }
+  table:not(.horizontal) thead {
+    position: sticky;
+    top: 0; }
+  table:not(.horizontal) tbody tr:first-child td {
+    border-top: 0; }
+
+table.horizontal {
+  border: 0; }
+  table.horizontal thead, table.horizontal tbody {
+    border: 0;
+    flex-flow: row nowrap; }
+  table.horizontal tbody {
+    overflow: auto;
+    justify-content: space-between;
+    flex: 1 0 0;
+    margin-left: calc( 4 * var(--universal-margin));
+    padding-bottom: calc(var(--universal-padding) / 4); }
+  table.horizontal tr {
+    flex-direction: column;
+    flex: 1 0 auto; }
+  table.horizontal th, table.horizontal td {
+    width: 100%;
+    border: 0;
+    border-bottom: 0.0625rem solid var(--table-border-color); }
+    table.horizontal th:not(:first-child), table.horizontal td:not(:first-child) {
+      border-top: 0; }
+  table.horizontal th {
+    text-align: right;
+    border-left: 0.0625rem solid var(--table-border-color);
+    border-right: 0.0625rem solid var(--table-border-separator-color); }
+  table.horizontal thead tr:first-child {
+    padding-left: 0; }
+  table.horizontal th:first-child, table.horizontal td:first-child {
+    border-top: 0.0625rem solid var(--table-border-color); }
+  table.horizontal tbody tr:last-child td {
+    border-right: 0.0625rem solid var(--table-border-color); }
+    table.horizontal tbody tr:last-child td:first-child {
+      border-top-right-radius: 0.25rem; }
+    table.horizontal tbody tr:last-child td:last-child {
+      border-bottom-right-radius: 0.25rem; }
+  table.horizontal thead tr:first-child th:first-child {
+    border-top-left-radius: 0.25rem; }
+  table.horizontal thead tr:first-child th:last-child {
+    border-bottom-left-radius: 0.25rem; }
+
+@media screen and (max-width: 499px) {
+  table, table.horizontal {
+    border-collapse: collapse;
+    border: 0;
+    width: 100%;
+    display: table; }
+    table thead, table th, table.horizontal thead, table.horizontal th {
+      border: 0;
+      height: 1px;
+      width: 1px;
+      margin: -1px;
+      overflow: hidden;
+      padding: 0;
+      position: absolute;
+      clip: rect(0 0 0 0);
+      -webkit-clip-path: inset(100%);
+      clip-path: inset(100%); }
+    table tbody, table.horizontal tbody {
+      border: 0;
+      display: table-row-group; }
+    table tr, table.horizontal tr {
+      display: block;
+      border: 0.0625rem solid var(--table-border-color);
+      border-radius: var(--universal-border-radius);
+      background: #fafafa;
+      padding: var(--universal-padding);
+      margin: var(--universal-margin);
+      margin-bottom: calc(2 * var(--universal-margin)); }
+    table th, table td, table.horizontal th, table.horizontal td {
+      width: auto; }
+    table td, table.horizontal td {
+      display: block;
+      border: 0;
+      text-align: right; }
+    table td:before, table.horizontal td:before {
+      content: attr(data-label);
+      float: left;
+      font-weight: 600; }
+    table th:first-child, table td:first-child, table.horizontal th:first-child, table.horizontal td:first-child {
+      border-top: 0; }
+    table tbody tr:last-child td, table.horizontal tbody tr:last-child td {
+      border-right: 0; } }
+:root {
+  --table-body-alt-back-color: #eee; }
+
+table tr:nth-of-type(2n) > td {
+  background: var(--table-body-alt-back-color); }
+
+@media screen and (max-width: 500px) {
+  table tr:nth-of-type(2n) {
+    background: var(--table-body-alt-back-color); } }
+:root {
+  --table-body-hover-back-color: #90caf9; }
+
+table.hoverable tr:hover, table.hoverable tr:hover > td, table.hoverable tr:focus, table.hoverable tr:focus > td {
+  background: var(--table-body-hover-back-color); }
+
+@media screen and (max-width: 500px) {
+  table.hoverable tr:hover, table.hoverable tr:hover > td, table.hoverable tr:focus, table.hoverable tr:focus > td {
+    background: var(--table-body-hover-back-color); } }
+/*
+  Definitions for contextual background elements, toasts and tooltips.
+*/
+/* Contextual module CSS variable definitions */
+:root {
+  --mark-back-color: #0277bd;
+  --mark-fore-color: #fafafa; }
+
+mark {
+  background: var(--mark-back-color);
+  color: var(--mark-fore-color);
+  font-size: 0.95em;
+  line-height: 1em;
+  border-radius: var(--universal-border-radius);
+  padding: calc(var(--universal-padding) / 4) calc(var(--universal-padding) / 2); }
+  mark.inline-block {
+    display: inline-block;
+    font-size: 1em;
+    line-height: 1.5;
+    padding: calc(var(--universal-padding) / 2) var(--universal-padding); }
+
+:root {
+  --toast-back-color: #424242;
+  --toast-fore-color: #fafafa; }
+
+.toast {
+  position: fixed;
+  bottom: calc(var(--universal-margin) * 3);
+  left: 50%;
+  transform: translate(-50%, -50%);
+  z-index: 1111;
+  color: var(--toast-fore-color);
+  background: var(--toast-back-color);
+  border-radius: calc(var(--universal-border-radius) * 16);
+  padding: var(--universal-padding) calc(var(--universal-padding) * 3); }
+
+:root {
+  --tooltip-back-color: #212121;
+  --tooltip-fore-color: #fafafa; }
+
+.tooltip {
+  position: relative;
+  display: inline-block; }
+  .tooltip:before, .tooltip:after {
+    position: absolute;
+    opacity: 0;
+    clip: rect(0 0 0 0);
+    -webkit-clip-path: inset(100%);
+    clip-path: inset(100%);
+    transition: all 0.3s;
+    z-index: 1010;
+    left: 50%; }
+  .tooltip:not(.bottom):before, .tooltip:not(.bottom):after {
+    bottom: 75%; }
+  .tooltip.bottom:before, .tooltip.bottom:after {
+    top: 75%; }
+  .tooltip:hover:before, .tooltip:hover:after, .tooltip:focus:before, .tooltip:focus:after {
+    opacity: 1;
+    clip: auto;
+    -webkit-clip-path: inset(0%);
+    clip-path: inset(0%); }
+  .tooltip:before {
+    content: '';
+    background: transparent;
+    border: var(--universal-margin) solid transparent;
+    left: calc(50% - var(--universal-margin)); }
+  .tooltip:not(.bottom):before {
+    border-top-color: #212121; }
+  .tooltip.bottom:before {
+    border-bottom-color: #212121; }
+  .tooltip:after {
+    content: attr(aria-label);
+    color: var(--tooltip-fore-color);
+    background: var(--tooltip-back-color);
+    border-radius: var(--universal-border-radius);
+    padding: var(--universal-padding);
+    white-space: nowrap;
+    transform: translateX(-50%); }
+  .tooltip:not(.bottom):after {
+    margin-bottom: calc(2 * var(--universal-margin)); }
+  .tooltip.bottom:after {
+    margin-top: calc(2 * var(--universal-margin)); }
+
+:root {
+  --modal-overlay-color: rgba(0, 0, 0, 0.45);
+  --modal-close-color: #444;
+  --modal-close-hover-color: #f0f0f0; }
+
+[type="checkbox"].modal {
+  height: 1px;
+  width: 1px;
+  margin: -1px;
+  overflow: hidden;
+  position: absolute;
+  clip: rect(0 0 0 0);
+  -webkit-clip-path: inset(100%);
+  clip-path: inset(100%); }
+  [type="checkbox"].modal + div {
+    position: fixed;
+    top: 0;
+    left: 0;
+    display: none;
+    width: 100vw;
+    height: 100vh;
+    background: var(--modal-overlay-color); }
+    [type="checkbox"].modal + div .card {
+      margin: 0 auto;
+      max-height: 50vh;
+      overflow: auto; }
+      [type="checkbox"].modal + div .card .modal-close {
+        position: absolute;
+        top: 0;
+        right: 0;
+        width: 1.75rem;
+        height: 1.75rem;
+        border-radius: var(--universal-border-radius);
+        padding: var(--universal-padding);
+        margin: 0;
+        cursor: pointer;
+        transition: background 0.3s; }
+        [type="checkbox"].modal + div .card .modal-close:before {
+          display: block;
+          content: '\00D7';
+          color: var(--modal-close-color);
+          position: relative;
+          font-family: sans-serif;
+          font-size: 1.75rem;
+          line-height: 1;
+          text-align: center; }
+        [type="checkbox"].modal + div .card .modal-close:hover, [type="checkbox"].modal + div .card .modal-close:focus {
+          background: var(--modal-close-hover-color); }
+  [type="checkbox"].modal:checked + div {
+    display: flex;
+    flex: 0 1 auto;
+    z-index: 1200; }
+    [type="checkbox"].modal:checked + div .card .modal-close {
+      z-index: 1211; }
+
+:root {
+  --collapse-label-back-color: #e8e8e8;
+  --collapse-label-fore-color: #212121;
+  --collapse-label-hover-back-color: #f0f0f0;
+  --collapse-selected-label-back-color: #ececec;
+  --collapse-border-color: #ddd;
+  --collapse-content-back-color: #fafafa;
+  --collapse-selected-label-border-color: #0277bd; }
+
+.collapse {
+  width: calc(100% - 2 * var(--universal-margin));
+  opacity: 1;
+  display: flex;
+  flex-direction: column;
+  margin: var(--universal-margin);
+  border-radius: var(--universal-border-radius); }
+  .collapse > [type="radio"], .collapse > [type="checkbox"] {
+    height: 1px;
+    width: 1px;
+    margin: -1px;
+    overflow: hidden;
+    position: absolute;
+    clip: rect(0 0 0 0);
+    -webkit-clip-path: inset(100%);
+    clip-path: inset(100%); }
+  .collapse > label {
+    flex-grow: 1;
+    display: inline-block;
+    height: 1.5rem;
+    cursor: pointer;
+    transition: background 0.3s;
+    color: var(--collapse-label-fore-color);
+    background: var(--collapse-label-back-color);
+    border: 0.0625rem solid var(--collapse-border-color);
+    padding: calc(1.5 * var(--universal-padding)); }
+    .collapse > label:hover, .collapse > label:focus {
+      background: var(--collapse-label-hover-back-color); }
+    .collapse > label + div {
+      flex-basis: auto;
+      height: 1px;
+      width: 1px;
+      margin: -1px;
+      overflow: hidden;
+      position: absolute;
+      clip: rect(0 0 0 0);
+      -webkit-clip-path: inset(100%);
+      clip-path: inset(100%);
+      transition: max-height 0.3s;
+      max-height: 1px; }
+  .collapse > :checked + label {
+    background: var(--collapse-selected-label-back-color);
+    border-bottom-color: var(--collapse-selected-label-border-color); }
+    .collapse > :checked + label + div {
+      box-sizing: border-box;
+      position: relative;
+      width: 100%;
+      height: auto;
+      overflow: auto;
+      margin: 0;
+      background: var(--collapse-content-back-color);
+      border: 0.0625rem solid var(--collapse-border-color);
+      border-top: 0;
+      padding: var(--universal-padding);
+      clip: auto;
+      -webkit-clip-path: inset(0%);
+      clip-path: inset(0%);
+      max-height: 850px; }
+  .collapse > label:not(:first-of-type) {
+    border-top: 0; }
+  .collapse > label:first-of-type {
+    border-radius: var(--universal-border-radius) var(--universal-border-radius) 0 0; }
+  .collapse > label:last-of-type:not(:first-of-type) {
+    border-radius: 0 0 var(--universal-border-radius) var(--universal-border-radius); }
+  .collapse > label:last-of-type:first-of-type {
+    border-radius: var(--universal-border-radius); }
+  .collapse > :checked:last-of-type:not(:first-of-type) + label {
+    border-radius: 0; }
+  .collapse > :checked:last-of-type + label + div {
+    border-radius: 0 0 var(--universal-border-radius) var(--universal-border-radius); }
+
+/*
+  Custom elements for contextual background elements, toasts and tooltips.
+*/
+mark.secondary {
+  --mark-back-color: #d32f2f; }
+
+mark.tertiary {
+  --mark-back-color: #308732; }
+
+mark.tag {
+  padding: calc(var(--universal-padding)/2) var(--universal-padding);
+  border-radius: 1em; }
+
+/*
+  Definitions for progress elements and spinners.
+*/
+/* Progess module CSS variable definitions */
+:root {
+  --progress-back-color: #ddd;
+  --progress-fore-color: #555; }
+
+progress {
+  display: block;
+  vertical-align: baseline;
+  -webkit-appearance: none;
+  -moz-appearance: none;
+  appearance: none;
+  height: 0.75rem;
+  width: calc(100% - 2 * var(--universal-margin));
+  margin: var(--universal-margin);
+  border: 0;
+  border-radius: calc(2 * var(--universal-border-radius));
+  background: var(--progress-back-color);
+  color: var(--progress-fore-color); }
+  progress::-webkit-progress-value {
+    background: var(--progress-fore-color);
+    border-top-left-radius: calc(2 * var(--universal-border-radius));
+    border-bottom-left-radius: calc(2 * var(--universal-border-radius)); }
+  progress::-webkit-progress-bar {
+    background: var(--progress-back-color); }
+  progress::-moz-progress-bar {
+    background: var(--progress-fore-color);
+    border-top-left-radius: calc(2 * var(--universal-border-radius));
+    border-bottom-left-radius: calc(2 * var(--universal-border-radius)); }
+  progress[value="1000"]::-webkit-progress-value {
+    border-radius: calc(2 * var(--universal-border-radius)); }
+  progress[value="1000"]::-moz-progress-bar {
+    border-radius: calc(2 * var(--universal-border-radius)); }
+  progress.inline {
+    display: inline-block;
+    vertical-align: middle;
+    width: 60%; }
+
+:root {
+  --spinner-back-color: #ddd;
+  --spinner-fore-color: #555; }
+
+@keyframes spinner-donut-anim {
+  0% {
+    transform: rotate(0deg); }
+  100% {
+    transform: rotate(360deg); } }
+.spinner {
+  display: inline-block;
+  margin: var(--universal-margin);
+  border: 0.25rem solid var(--spinner-back-color);
+  border-left: 0.25rem solid var(--spinner-fore-color);
+  border-radius: 50%;
+  width: 1.25rem;
+  height: 1.25rem;
+  animation: spinner-donut-anim 1.2s linear infinite; }
+
+/*
+  Custom elements for progress bars and spinners.
+*/
+progress.primary {
+  --progress-fore-color: #1976d2; }
+
+progress.secondary {
+  --progress-fore-color: #d32f2f; }
+
+progress.tertiary {
+  --progress-fore-color: #308732; }
+
+.spinner.primary {
+  --spinner-fore-color: #1976d2; }
+
+.spinner.secondary {
+  --spinner-fore-color: #d32f2f; }
+
+.spinner.tertiary {
+  --spinner-fore-color: #308732; }
+
+/*
+  Definitions for icons - powered by Feather (https://feathericons.com/).
+*/
+span[class^='icon-'] {
+  display: inline-block;
+  height: 1em;
+  width: 1em;
+  vertical-align: -0.125em;
+  background-size: contain;
+  margin: 0 calc(var(--universal-margin) / 4); }
+  span[class^='icon-'].secondary {
+    -webkit-filter: invert(25%);
+    filter: invert(25%); }
+  span[class^='icon-'].inverse {
+    -webkit-filter: invert(100%);
+    filter: invert(100%); }
+
+span.icon-alert {
+  background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='12' cy='12' r='10'%3E%3C/circle%3E%3Cline x1='12' y1='8' x2='12' y2='12'%3E%3C/line%3E%3Cline x1='12' y1='16' x2='12' y2='16'%3E%3C/line%3E%3C/svg%3E"); }
+span.icon-bookmark {
+  background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M19 21l-7-5-7 5V5a2 2 0 0 1 2-2h10a2 2 0 0 1 2 2z'%3E%3C/path%3E%3C/svg%3E"); }
+span.icon-calendar {
+  background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Crect x='3' y='4' width='18' height='18' rx='2' ry='2'%3E%3C/rect%3E%3Cline x1='16' y1='2' x2='16' y2='6'%3E%3C/line%3E%3Cline x1='8' y1='2' x2='8' y2='6'%3E%3C/line%3E%3Cline x1='3' y1='10' x2='21' y2='10'%3E%3C/line%3E%3C/svg%3E"); }
+span.icon-credit {
+  background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Crect x='1' y='4' width='22' height='16' rx='2' ry='2'%3E%3C/rect%3E%3Cline x1='1' y1='10' x2='23' y2='10'%3E%3C/line%3E%3C/svg%3E"); }
+span.icon-edit {
+  background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M20 14.66V20a2 2 0 0 1-2 2H4a2 2 0 0 1-2-2V6a2 2 0 0 1 2-2h5.34'%3E%3C/path%3E%3Cpolygon points='18 2 22 6 12 16 8 16 8 12 18 2'%3E%3C/polygon%3E%3C/svg%3E"); }
+span.icon-link {
+  background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M18 13v6a2 2 0 0 1-2 2H5a2 2 0 0 1-2-2V8a2 2 0 0 1 2-2h6'%3E%3C/path%3E%3Cpolyline points='15 3 21 3 21 9'%3E%3C/polyline%3E%3Cline x1='10' y1='14' x2='21' y2='3'%3E%3C/line%3E%3C/svg%3E"); }
+span.icon-help {
+  background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M9.09 9a3 3 0 0 1 5.83 1c0 2-3 3-3 3'%3E%3C/path%3E%3Ccircle cx='12' cy='12' r='10'%3E%3C/circle%3E%3Cline x1='12' y1='17' x2='12' y2='17'%3E%3C/line%3E%3C/svg%3E"); }
+span.icon-home {
+  background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M3 9l9-7 9 7v11a2 2 0 0 1-2 2H5a2 2 0 0 1-2-2z'%3E%3C/path%3E%3Cpolyline points='9 22 9 12 15 12 15 22'%3E%3C/polyline%3E%3C/svg%3E"); }
+span.icon-info {
+  background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='12' cy='12' r='10'%3E%3C/circle%3E%3Cline x1='12' y1='16' x2='12' y2='12'%3E%3C/line%3E%3Cline x1='12' y1='8' x2='12' y2='8'%3E%3C/line%3E%3C/svg%3E"); }
+span.icon-lock {
+  background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Crect x='3' y='11' width='18' height='11' rx='2' ry='2'%3E%3C/rect%3E%3Cpath d='M7 11V7a5 5 0 0 1 10 0v4'%3E%3C/path%3E%3C/svg%3E"); }
+span.icon-mail {
+  background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M4 4h16c1.1 0 2 .9 2 2v12c0 1.1-.9 2-2 2H4c-1.1 0-2-.9-2-2V6c0-1.1.9-2 2-2z'%3E%3C/path%3E%3Cpolyline points='22,6 12,13 2,6'%3E%3C/polyline%3E%3C/svg%3E"); }
+span.icon-location {
+  background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M21 10c0 7-9 13-9 13s-9-6-9-13a9 9 0 0 1 18 0z'%3E%3C/path%3E%3Ccircle cx='12' cy='10' r='3'%3E%3C/circle%3E%3C/svg%3E"); }
+span.icon-phone {
+  background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M22 16.92v3a2 2 0 0 1-2.18 2 19.79 19.79 0 0 1-8.63-3.07 19.5 19.5 0 0 1-6-6 19.79 19.79 0 0 1-3.07-8.67A2 2 0 0 1 4.11 2h3a2 2 0 0 1 2 1.72 12.84 12.84 0 0 0 .7 2.81 2 2 0 0 1-.45 2.11L8.09 9.91a16 16 0 0 0 6 6l1.27-1.27a2 2 0 0 1 2.11-.45 12.84 12.84 0 0 0 2.81.7A2 2 0 0 1 22 16.92z'%3E%3C/path%3E%3C/svg%3E"); }
+span.icon-rss {
+  background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M4 11a9 9 0 0 1 9 9'%3E%3C/path%3E%3Cpath d='M4 4a16 16 0 0 1 16 16'%3E%3C/path%3E%3Ccircle cx='5' cy='19' r='1'%3E%3C/circle%3E%3C/svg%3E"); }
+span.icon-search {
+  background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='11' cy='11' r='8'%3E%3C/circle%3E%3Cline x1='21' y1='21' x2='16.65' y2='16.65'%3E%3C/line%3E%3C/svg%3E"); }
+span.icon-settings {
+  background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='12' cy='12' r='3'%3E%3C/circle%3E%3Cpath d='M19.4 15a1.65 1.65 0 0 0 .33 1.82l.06.06a2 2 0 0 1 0 2.83 2 2 0 0 1-2.83 0l-.06-.06a1.65 1.65 0 0 0-1.82-.33 1.65 1.65 0 0 0-1 1.51V21a2 2 0 0 1-2 2 2 2 0 0 1-2-2v-.09A1.65 1.65 0 0 0 9 19.4a1.65 1.65 0 0 0-1.82.33l-.06.06a2 2 0 0 1-2.83 0 2 2 0 0 1 0-2.83l.06-.06a1.65 1.65 0 0 0 .33-1.82 1.65 1.65 0 0 0-1.51-1H3a2 2 0 0 1-2-2 2 2 0 0 1 2-2h.09A1.65 1.65 0 0 0 4.6 9a1.65 1.65 0 0 0-.33-1.82l-.06-.06a2 2 0 0 1 0-2.83 2 2 0 0 1 2.83 0l.06.06a1.65 1.65 0 0 0 1.82.33H9a1.65 1.65 0 0 0 1-1.51V3a2 2 0 0 1 2-2 2 2 0 0 1 2 2v.09a1.65 1.65 0 0 0 1 1.51 1.65 1.65 0 0 0 1.82-.33l.06-.06a2 2 0 0 1 2.83 0 2 2 0 0 1 0 2.83l-.06.06a1.65 1.65 0 0 0-.33 1.82V9a1.65 1.65 0 0 0 1.51 1H21a2 2 0 0 1 2 2 2 2 0 0 1-2 2h-.09a1.65 1.65 0 0 0-1.51 1z'%3E%3C/path%3E%3C/svg%3E"); }
+span.icon-share {
+  background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='18' cy='5' r='3'%3E%3C/circle%3E%3Ccircle cx='6' cy='12' r='3'%3E%3C/circle%3E%3Ccircle cx='18' cy='19' r='3'%3E%3C/circle%3E%3Cline x1='8.59' y1='13.51' x2='15.42' y2='17.49'%3E%3C/line%3E%3Cline x1='15.41' y1='6.51' x2='8.59' y2='10.49'%3E%3C/line%3E%3C/svg%3E"); }
+span.icon-cart {
+  background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='9' cy='21' r='1'%3E%3C/circle%3E%3Ccircle cx='20' cy='21' r='1'%3E%3C/circle%3E%3Cpath d='M1 1h4l2.68 13.39a2 2 0 0 0 2 1.61h9.72a2 2 0 0 0 2-1.61L23 6H6'%3E%3C/path%3E%3C/svg%3E"); }
+span.icon-upload {
+  background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M21 15v4a2 2 0 0 1-2 2H5a2 2 0 0 1-2-2v-4'%3E%3C/path%3E%3Cpolyline points='17 8 12 3 7 8'%3E%3C/polyline%3E%3Cline x1='12' y1='3' x2='12' y2='15'%3E%3C/line%3E%3C/svg%3E"); }
+span.icon-user {
+  background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M20 21v-2a4 4 0 0 0-4-4H8a4 4 0 0 0-4 4v2'%3E%3C/path%3E%3Ccircle cx='12' cy='7' r='4'%3E%3C/circle%3E%3C/svg%3E"); }
+
+/*
+  Definitions for utilities and helper classes.
+*/
+/* Utility module CSS variable definitions */
+:root {
+  --generic-border-color: rgba(0, 0, 0, 0.3);
+  --generic-box-shadow: 0 0.25rem 0.25rem 0 rgba(0, 0, 0, 0.125), 0 0.125rem 0.125rem -0.125rem rgba(0, 0, 0, 0.25); }
+
+.hidden {
+  display: none !important; }
+
+.visually-hidden {
+  position: absolute !important;
+  width: 1px !important;
+  height: 1px !important;
+  margin: -1px !important;
+  border: 0 !important;
+  padding: 0 !important;
+  clip: rect(0 0 0 0) !important;
+  -webkit-clip-path: inset(100%) !important;
+  clip-path: inset(100%) !important;
+  overflow: hidden !important; }
+
+.bordered {
+  border: 0.0625rem solid var(--generic-border-color) !important; }
+
+.rounded {
+  border-radius: var(--universal-border-radius) !important; }
+
+.circular {
+  border-radius: 50% !important; }
+
+.shadowed {
+  box-shadow: var(--generic-box-shadow) !important; }
+
+.responsive-margin {
+  margin: calc(var(--universal-margin) / 4) !important; }
+  @media screen and (min-width: 500px) {
+    .responsive-margin {
+      margin: calc(var(--universal-margin) / 2) !important; } }
+  @media screen and (min-width: 1280px) {
+    .responsive-margin {
+      margin: var(--universal-margin) !important; } }
+
+.responsive-padding {
+  padding: calc(var(--universal-padding) / 4) !important; }
+  @media screen and (min-width: 500px) {
+    .responsive-padding {
+      padding: calc(var(--universal-padding) / 2) !important; } }
+  @media screen and (min-width: 1280px) {
+    .responsive-padding {
+      padding: var(--universal-padding) !important; } }
+
+@media screen and (max-width: 499px) {
+  .hidden-sm {
+    display: none !important; } }
+@media screen and (min-width: 500px) and (max-width: 1279px) {
+  .hidden-md {
+    display: none !important; } }
+@media screen and (min-width: 1280px) {
+  .hidden-lg {
+    display: none !important; } }
+@media screen and (max-width: 499px) {
+  .visually-hidden-sm {
+    position: absolute !important;
+    width: 1px !important;
+    height: 1px !important;
+    margin: -1px !important;
+    border: 0 !important;
+    padding: 0 !important;
+    clip: rect(0 0 0 0) !important;
+    -webkit-clip-path: inset(100%) !important;
+    clip-path: inset(100%) !important;
+    overflow: hidden !important; } }
+@media screen and (min-width: 500px) and (max-width: 1279px) {
+  .visually-hidden-md {
+    position: absolute !important;
+    width: 1px !important;
+    height: 1px !important;
+    margin: -1px !important;
+    border: 0 !important;
+    padding: 0 !important;
+    clip: rect(0 0 0 0) !important;
+    -webkit-clip-path: inset(100%) !important;
+    clip-path: inset(100%) !important;
+    overflow: hidden !important; } }
+@media screen and (min-width: 1280px) {
+  .visually-hidden-lg {
+    position: absolute !important;
+    width: 1px !important;
+    height: 1px !important;
+    margin: -1px !important;
+    border: 0 !important;
+    padding: 0 !important;
+    clip: rect(0 0 0 0) !important;
+    -webkit-clip-path: inset(100%) !important;
+    clip-path: inset(100%) !important;
+    overflow: hidden !important; } }
+
+/*# sourceMappingURL=mini-default.css.map */
diff --git a/Drivers/BSP/Components/nt35510/_htmresc/st_logo.png b/Drivers/BSP/Components/nt35510/_htmresc/st_logo.png
new file mode 100644
index 0000000..8b80057
Binary files /dev/null and b/Drivers/BSP/Components/nt35510/_htmresc/st_logo.png differ
diff --git a/Drivers/BSP/Components/nt35510/nt35510.c b/Drivers/BSP/Components/nt35510/nt35510.c
new file mode 100644
index 0000000..566d924
--- /dev/null
+++ b/Drivers/BSP/Components/nt35510/nt35510.c
@@ -0,0 +1,252 @@
+/**
+  ******************************************************************************
+  * @file    nt35510.c
+  * @author  MCD Application Team
+  * @brief   This file provides the LCD Driver for Frida Techshine 3K138 (WVGA)
+  *          DSI LCD Display NT35510.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "nt35510.h"
+#include <stdio.h>
+#include <stdarg.h>
+
+
+/** @addtogroup BSP
+  * @{
+  */
+
+/** @addtogroup Components
+  * @{
+  */
+
+/** @defgroup NT35510 NT35510
+  * @brief     This file provides a set of functions needed to drive the
+  *            NT35510 IC display driver.
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup NT35510_Private_Constants NT35510 Private Constants
+  * @{
+  */
+
+/*
+ * @brief Constant tables of register settings used to transmit DSI
+ * command packets as power up initialization sequence of the Frida 3K138
+ */
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup NT35510_Exported_Variables
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Exported functions ---------------------------------------------------------*/
+/** @defgroup NT35510_Exported_Functions OTM8009A Exported Functions
+  * @{
+  */
+
+/**
+  * @brief  Initializes the LCD Frida display part by communication in DSI mode in Video Mode
+  *         with IC Display Driver NT35510 (see IC Driver specification for more information).
+  * @param  hdsi_eval : pointer on DSI configuration structure
+  * @param  hdsivideo_handle : pointer on DSI video mode configuration structure
+  * @retval Status
+  */
+uint8_t NT35510_Init(uint32_t ColorCoding, uint32_t orientation)
+{
+  NT35510_IO_Delay(120);
+
+/* ************************************************************************** */
+/* Proprietary Initialization                                                 */
+/* ************************************************************************** */
+  const uint8_t nt35510_reg[]   = {0x55, 0xAA, 0x52, 0x08, 0x01, 0xF0};
+  const uint8_t nt35510_reg1[]  = {0x03, 0x03, 0x03, 0xB0};
+  const uint8_t nt35510_reg2[]  = {0x46, 0x46, 0x46, 0xB6};
+  const uint8_t nt35510_reg3[]  = {0x03, 0x03, 0x03, 0xB1};
+  const uint8_t nt35510_reg4[]  = {0x36, 0x36, 0x36, 0xB7};
+  const uint8_t nt35510_reg5[]  = {0x00, 0x00, 0x02, 0xB2};
+  const uint8_t nt35510_reg6[]  = {0x26, 0x26, 0x26, 0xB8};
+  const uint8_t nt35510_reg7[]  = {0xBF, 0x01};
+  const uint8_t nt35510_reg8[]  = {0x09, 0x09, 0x09, 0xB3};
+  const uint8_t nt35510_reg9[]  = {0x36, 0x36, 0x36, 0xB9};
+  const uint8_t nt35510_reg10[] = {0x08, 0x08, 0x08, 0xB5};
+  const uint8_t nt35510_reg12[] = {0x26, 0x26, 0x26, 0xBA};
+  const uint8_t nt35510_reg13[] = {0x00, 0x80, 0x00, 0xBC};
+  const uint8_t nt35510_reg14[] = {0x00, 0x80, 0x00, 0xBD};
+  const uint8_t nt35510_reg15[] = {0x00, 0x50, 0xBE};
+  const uint8_t nt35510_reg16[] = {0x55, 0xAA, 0x52, 0x08, 0x00, 0xF0};
+  const uint8_t nt35510_reg17[] = {0xFC, 0x00, 0xB1};
+  const uint8_t nt35510_reg18[] = {0xB6, 0x03};
+  const uint8_t nt35510_reg19[] = {0xB5, 0x51};
+  const uint8_t nt35510_reg20[] = {0x00, 0x00, 0xB7};
+  const uint8_t nt35510_reg21[] = {0x01, 0x02, 0x02, 0x02, 0xB8};
+  const uint8_t nt35510_reg22[] = {0x00, 0x00, 0x00, 0xBC};
+  const uint8_t nt35510_reg23[] = {0x03, 0x00, 0x00, 0xCC};
+  const uint8_t nt35510_reg24[] = {0xBA, 0x01};
+  const uint8_t nt35510_madctl_portrait[] = {NT35510_CMD_MADCTL ,0x00};
+  const uint8_t nt35510_caset_portrait[] = {0x00, 0x00, 0x01, 0xDF ,NT35510_CMD_CASET};
+  const uint8_t nt35510_raset_portrait[] = {0x00, 0x00, 0x03, 0x1F ,NT35510_CMD_RASET};
+  const uint8_t nt35510_madctl_landscape[] = {NT35510_CMD_MADCTL, 0x60};
+  const uint8_t nt35510_caset_landscape[] = {0x00, 0x00, 0x03, 0x1F ,NT35510_CMD_CASET};
+  const uint8_t nt35510_raset_landscape[] = {0x00, 0x00, 0x01, 0xDF ,NT35510_CMD_RASET};
+  const uint8_t nt35510_reg26[] = {NT35510_CMD_TEEON, 0x00};  /* Tear on */
+  const uint8_t nt35510_reg27[] = {NT35510_CMD_SLPOUT, 0x00}; /* Sleep out */
+  const uint8_t nt35510_reg30[] = {NT35510_CMD_DISPON, 0x00};
+
+  const uint8_t nt35510_reg31[] = {NT35510_CMD_WRDISBV, 0x7F};
+  const uint8_t nt35510_reg32[] = {NT35510_CMD_WRCTRLD, 0x2C};
+  const uint8_t nt35510_reg33[] = {NT35510_CMD_WRCABC, 0x02};
+  const uint8_t nt35510_reg34[] = {NT35510_CMD_WRCABCMB, 0xFF};
+  const uint8_t nt35510_reg35[] = {NT35510_CMD_RAMWR, 0x00};
+  const uint8_t nt35510_reg36[] = {NT35510_CMD_COLMOD, NT35510_COLMOD_RGB565};
+  const uint8_t nt35510_reg37[] = {NT35510_CMD_COLMOD, NT35510_COLMOD_RGB888};
+
+  DSI_IO_WriteCmd(5, (uint8_t *)nt35510_reg); /* LV2:  Page 1 enable */
+  DSI_IO_WriteCmd(3, (uint8_t *)nt35510_reg1);/* AVDD: 5.2V */
+  DSI_IO_WriteCmd(3, (uint8_t *)nt35510_reg2);/* AVDD: Ratio */
+  DSI_IO_WriteCmd(3, (uint8_t *)nt35510_reg3);/* AVEE: -5.2V */
+  DSI_IO_WriteCmd(3, (uint8_t *)nt35510_reg4);/* AVEE: Ratio */
+  DSI_IO_WriteCmd(3, (uint8_t *)nt35510_reg5);/* VCL: -2.5V */
+  DSI_IO_WriteCmd(3, (uint8_t *)nt35510_reg6);/* VCL: Ratio */
+  DSI_IO_WriteCmd(1, (uint8_t *)nt35510_reg7);/* VGH: 15V (Free Pump) */
+  DSI_IO_WriteCmd(3, (uint8_t *)nt35510_reg8);
+  DSI_IO_WriteCmd(3, (uint8_t *)nt35510_reg9);/* VGH: Ratio */
+  DSI_IO_WriteCmd(3, (uint8_t *)nt35510_reg10);/* VGL_REG: -10V */
+  DSI_IO_WriteCmd(3, (uint8_t *)nt35510_reg12);/* VGLX: Ratio */
+  DSI_IO_WriteCmd(3, (uint8_t *)nt35510_reg13);/* VGMP/VGSP: 4.5V/0V */
+  DSI_IO_WriteCmd(3, (uint8_t *)nt35510_reg14);/* VGMN/VGSN:-4.5V/0V */
+  DSI_IO_WriteCmd(2, (uint8_t *)nt35510_reg15);/* VCOM: -1.325V */
+
+/* ************************************************************************** */
+/* Proprietary DCS Initialization                                             */
+/* ************************************************************************** */
+  DSI_IO_WriteCmd(5, (uint8_t *)nt35510_reg16);/* LV2: Page 0 enable */
+  DSI_IO_WriteCmd(2, (uint8_t *)nt35510_reg17);/* Display control */
+  DSI_IO_WriteCmd(1, (uint8_t *)nt35510_reg18);/* Src hold time */
+  DSI_IO_WriteCmd(1, (uint8_t *)nt35510_reg19);
+  DSI_IO_WriteCmd(2, (uint8_t *)nt35510_reg20);/* Gate EQ control */
+  DSI_IO_WriteCmd(4, (uint8_t *)nt35510_reg21);/* Src EQ control(Mode2) */
+  DSI_IO_WriteCmd(3, (uint8_t *)nt35510_reg22);/* Inv. mode(2-dot) */
+  DSI_IO_WriteCmd(3, (uint8_t *)nt35510_reg23);
+  DSI_IO_WriteCmd(1, (uint8_t *)nt35510_reg24);
+  /* Tear on */
+  DSI_IO_WriteCmd(0, (uint8_t *)nt35510_reg26);
+  /* Set Pixel color format to RGB888 */
+  DSI_IO_WriteCmd(0, (uint8_t *)nt35510_reg37);
+
+/* ************************************************************************** */
+/* Standard DCS Initialization                                                */
+/* ************************************************************************** */
+
+  /* Add a delay, otherwise MADCTL not taken */
+  NT35510_IO_Delay(200);
+
+  /* Configure orientation */
+  if(orientation == NT35510_ORIENTATION_PORTRAIT)
+  {
+    DSI_IO_WriteCmd(1, (uint8_t *)nt35510_madctl_portrait);
+    DSI_IO_WriteCmd(4, (uint8_t *)nt35510_caset_portrait);
+    DSI_IO_WriteCmd(4, (uint8_t *)nt35510_raset_portrait);
+  }
+  else
+  {
+    DSI_IO_WriteCmd(1, (uint8_t *)nt35510_madctl_landscape);
+    DSI_IO_WriteCmd(4, (uint8_t *)nt35510_caset_landscape);
+    DSI_IO_WriteCmd(4, (uint8_t *)nt35510_raset_landscape);
+  }
+
+  DSI_IO_WriteCmd(0, (uint8_t *)nt35510_reg27);
+  /* Wait for sleep out exit */
+  NT35510_IO_Delay(120);
+
+  switch(ColorCoding)
+  {
+    case NT35510_FORMAT_RBG565 :
+      /* Set Pixel color format to RGB565 */
+      DSI_IO_WriteCmd(1, (uint8_t *)nt35510_reg36);
+      break;
+    case NT35510_FORMAT_RGB888 :
+      /* Set Pixel color format to RGB888 */
+      DSI_IO_WriteCmd(1, (uint8_t *)nt35510_reg37);
+      break;
+    default :
+      /* Set Pixel color format to RGB888 */
+      DSI_IO_WriteCmd(1, (uint8_t *)nt35510_reg37);
+      break;
+  }
+
+  /** CABC : Content Adaptive Backlight Control section start >> */
+  /* Note : defaut is 0 (lowest Brightness), 0xFF is highest Brightness, try 0x7F : intermediate value */
+  DSI_IO_WriteCmd(1, (uint8_t *)nt35510_reg31);
+  /* defaut is 0, try 0x2C - Brightness Control Block, Display Dimming & BackLight on */
+  DSI_IO_WriteCmd(1, (uint8_t *)nt35510_reg32);
+  /* defaut is 0, try 0x02 - image Content based Adaptive Brightness [Still Picture] */
+  DSI_IO_WriteCmd(1, (uint8_t *)nt35510_reg33);
+  /* defaut is 0 (lowest Brightness), 0xFF is highest Brightness */
+  DSI_IO_WriteCmd(1, (uint8_t *)nt35510_reg34);
+  /** CABC : Content Adaptive Backlight Control section end << */
+
+  /* Display on */
+  DSI_IO_WriteCmd(0, (uint8_t *)nt35510_reg30);
+
+  /* Send Command GRAM memory write (no parameters) : this initiates frame write via other DSI commands sent by */
+  /* DSI host from LTDC incoming pixels in video mode */
+  DSI_IO_WriteCmd(0, (uint8_t *)nt35510_reg35);
+
+  return 0;
+}
+
+
+/**
+  * @}
+  */
+
+uint8_t NT35510_DeInit(void)
+{
+  const uint8_t nt35510_reg30b[] = {NT35510_CMD_DISPOFF, 0x00};
+  const uint8_t nt35510_reg27b[] = {NT35510_CMD_SLPIN, 0x00};
+  /* Display off */
+  DSI_IO_WriteCmd(0, (uint8_t *)nt35510_reg30b);
+  NT35510_IO_Delay(120);
+  /* Sleep in */
+  DSI_IO_WriteCmd(0, (uint8_t *)nt35510_reg27b);
+  return 0;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Drivers/BSP/Components/nt35510/nt35510.h b/Drivers/BSP/Components/nt35510/nt35510.h
new file mode 100644
index 0000000..0e74206
--- /dev/null
+++ b/Drivers/BSP/Components/nt35510/nt35510.h
@@ -0,0 +1,249 @@
+/**
+  ******************************************************************************
+  * @file    nt35510.h
+  * @author  MCD Application Team
+  * @brief   This file contains all the constants parameters for the NT35510
+  *          which is the LCD Driver for Frida Techshine 3K138 (WVGA)
+  *          DSI LCD Display.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __NT35510_H
+#define __NT35510_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include <stdint.h>
+/** @addtogroup BSP
+  * @{
+  */
+
+/** @addtogroup Components
+  * @{
+  */
+
+/** @addtogroup nt35510
+  * @{
+  */
+
+/** @addtogroup NT35510_Exported_Variables
+  * @{
+  */
+
+#if defined ( __GNUC__ )
+#ifndef __weak
+#define __weak __attribute__((weak))
+#endif /* __weak */
+#endif /* __GNUC__ */
+
+/**
+ *  @brief LCD_OrientationTypeDef
+ *  Possible values of Display Orientation
+ */
+#define NT35510_ORIENTATION_PORTRAIT    ((uint32_t)0x00) /* Portrait orientation choice of LCD screen  */
+#define NT35510_ORIENTATION_LANDSCAPE   ((uint32_t)0x01) /* Landscape orientation choice of LCD screen */
+
+/**
+ *  @brief  Possible values of
+ *  pixel data format (ie color coding) transmitted on DSI Data lane in DSI packets
+ */
+#define NT35510_FORMAT_RGB888    ((uint32_t)0x00) /* Pixel format chosen is RGB888 : 24 bpp */
+#define NT35510_FORMAT_RBG565    ((uint32_t)0x02) /* Pixel format chosen is RGB565 : 16 bpp */
+
+/**
+  * @brief  nt35510_480x800 Size
+  */
+
+/* Width and Height in Portrait mode */
+#define  NT35510_480X800_WIDTH             ((uint16_t)480)     /* LCD PIXEL WIDTH   */
+#define  NT35510_480X800_HEIGHT            ((uint16_t)800)     /* LCD PIXEL HEIGHT  */
+
+/* Width and Height in Landscape mode */
+#define  NT35510_800X480_WIDTH             ((uint16_t)800)     /* LCD PIXEL WIDTH   */
+#define  NT35510_800X480_HEIGHT            ((uint16_t)480)     /* LCD PIXEL HEIGHT  */
+
+/**
+  * @brief  NT35510_480X800 Timing parameters for Portrait orientation mode
+  */
+#define  NT35510_480X800_HSYNC             ((uint16_t)2)      /* Horizontal synchronization */
+#define  NT35510_480X800_HBP               ((uint16_t)34)     /* Horizontal back porch      */
+#define  NT35510_480X800_HFP               ((uint16_t)34)     /* Horizontal front porch     */
+
+#define  NT35510_480X800_VSYNC             ((uint16_t)120)      /* Vertical synchronization   */
+#define  NT35510_480X800_VBP               ((uint16_t)150)     /* Vertical back porch        */
+#define  NT35510_480X800_VFP               ((uint16_t)150)     /* Vertical front porch       */
+
+/**
+  * @brief  NT35510_800X480 Timing parameters for Landscape orientation mode
+  *         Same values as for Portrait mode in fact.
+  */
+#define  NT35510_800X480_HSYNC             NT35510_480X800_VSYNC  /* Horizontal synchronization */
+#define  NT35510_800X480_HBP               NT35510_480X800_VBP    /* Horizontal back porch      */
+#define  NT35510_800X480_HFP               NT35510_480X800_VFP    /* Horizontal front porch     */
+#define  NT35510_800X480_VSYNC             NT35510_480X800_HSYNC  /* Vertical synchronization   */
+#define  NT35510_800X480_VBP               NT35510_480X800_HBP    /* Vertical back porch        */
+#define  NT35510_800X480_VFP               NT35510_480X800_HFP    /* Vertical front porch       */
+
+
+/* List of NT35510 used commands                                  */
+/* Detailed in NT35510 Data Sheet v0.80                           */
+/* Version of 10/28/2011                                          */
+/* Command, NumberOfArguments                                     */
+
+#define  NT35510_CMD_NOP                   0x00  /* NOP */
+#define  NT35510_CMD_SWRESET               0x01  /* SW reset */
+#define  NT35510_CMD_RDDID                 0x04  /* Read display ID */
+#define  NT35510_CMD_RDNUMED               0x05  /* Read number of errors on DSI */
+#define  NT35510_CMD_RDDPM                 0x0A  /* Read display power mode */
+#define  NT35510_CMD_RDDMADCTL             0x0B  /* Read display MADCTL */
+#define  NT35510_CMD_RDDCOLMOD             0x0C  /* Read display pixel format */
+#define  NT35510_CMD_RDDIM                 0x0D  /* Read display image mode */
+#define  NT35510_CMD_RDDSM                 0x0E  /* Read display signal mode */
+#define  NT35510_CMD_RDDSDR                0x0F  /* Read display self-diagnostics result */
+#define  NT35510_CMD_SLPIN                 0x10  /* Sleep in */
+#define  NT35510_CMD_SLPOUT                0x11  /* Sleep out */
+#define  NT35510_CMD_PTLON                 0x12  /* Partial mode on  */
+#define  NT35510_CMD_NORON                 0x13  /* Normal display mode on */
+#define  NT35510_CMD_INVOFF                0x20  /* Display inversion off */
+#define  NT35510_CMD_INVON                 0x21  /* Display inversion on */
+#define  NT35510_CMD_ALLPOFF               0x22  /* All pixel off */
+#define  NT35510_CMD_ALLPON                0x23  /* All pixel on */
+#define  NT35510_CMD_GAMSET                0x26  /* Gamma set */
+#define  NT35510_CMD_DISPOFF               0x28  /* Display off */
+#define  NT35510_CMD_DISPON                0x29  /* Display on */
+#define  NT35510_CMD_CASET                 0x2A  /* Column address set */
+#define  NT35510_CMD_RASET                 0x2B  /* Row address set */
+#define  NT35510_CMD_RAMWR                 0x2C  /* Memory write */
+#define  NT35510_CMD_RAMRD                 0x2E  /* Memory read  */
+#define  NT35510_CMD_PLTAR                 0x30  /* Partial area */
+#define  NT35510_CMD_TOPC                  0x32  /* Turn On Peripheral Command */
+#define  NT35510_CMD_TEOFF                 0x34  /* Tearing effect line off */
+#define  NT35510_CMD_TEEON                 0x35  /* Tearing effect line on */
+#define  NT35510_CMD_MADCTL                0x36  /* Memory data access control */
+#define  NT35510_CMD_IDMOFF                0x38  /* Idle mode off */
+#define  NT35510_CMD_IDMON                 0x39  /* Idle mode on */
+#define  NT35510_CMD_COLMOD                0x3A  /* Interface pixel format */
+#define  NT35510_CMD_RAMWRC                0x3C  /* Memory write continue */
+#define  NT35510_CMD_RAMRDC                0x3E  /* Memory read continue */
+#define  NT35510_CMD_STESL                 0x44  /* Set tearing effect scan line */
+#define  NT35510_CMD_GSL                   0x45  /* Get scan line */
+
+#define  NT35510_CMD_DSTBON                0x4F  /* Deep standby mode on */
+#define  NT35510_CMD_WRPFD                 0x50  /* Write profile value for display */
+#define  NT35510_CMD_WRDISBV               0x51  /* Write display brightness */
+#define  NT35510_CMD_RDDISBV               0x52  /* Read display brightness */
+#define  NT35510_CMD_WRCTRLD               0x53  /* Write CTRL display */
+#define  NT35510_CMD_RDCTRLD               0x54  /* Read CTRL display value */
+#define  NT35510_CMD_WRCABC                0x55  /* Write content adaptative brightness control */
+#define  NT35510_CMD_RDCABC                0x56  /* Read content adaptive brightness control */
+#define  NT35510_CMD_WRHYSTE               0x57  /* Write hysteresis */
+#define  NT35510_CMD_WRGAMMSET             0x58  /* Write gamme setting */
+#define  NT35510_CMD_RDFSVM                0x5A  /* Read FS value MSBs */
+#define  NT35510_CMD_RDFSVL                0x5B  /* Read FS value LSBs */
+#define  NT35510_CMD_RDMFFSVM              0x5C  /* Read median filter FS value MSBs */
+#define  NT35510_CMD_RDMFFSVL              0x5D  /* Read median filter FS value LSBs */
+#define  NT35510_CMD_WRCABCMB              0x5E  /* Write CABC minimum brightness */
+#define  NT35510_CMD_RDCABCMB              0x5F  /* Read CABC minimum brightness */
+#define  NT35510_CMD_WRLSCC                0x65  /* Write light sensor compensation coefficient value */
+#define  NT35510_CMD_RDLSCCM               0x66  /* Read light sensor compensation coefficient value MSBs */
+#define  NT35510_CMD_RDLSCCL               0x67  /* Read light sensor compensation coefficient value LSBs */
+#define  NT35510_CMD_RDBWLB                0x70  /* Read black/white low bits */
+#define  NT35510_CMD_RDBKX                 0x71  /* Read Bkx */
+#define  NT35510_CMD_RDBKY                 0x72  /* Read Bky */
+#define  NT35510_CMD_RDWX                  0x73  /* Read Wx */
+#define  NT35510_CMD_RDWY                  0x74  /* Read Wy */
+#define  NT35510_CMD_RDRGLB                0x75  /* Read red/green low bits */
+#define  NT35510_CMD_RDRX                  0x76  /* Read Rx */
+#define  NT35510_CMD_RDRY                  0x77  /* Read Ry */
+#define  NT35510_CMD_RDGX                  0x78  /* Read Gx */
+#define  NT35510_CMD_RDGY                  0x79  /* Read Gy */
+#define  NT35510_CMD_RDBALB                0x7A  /* Read blue/acolor low bits */
+#define  NT35510_CMD_RDBX                  0x7B  /* Read Bx */
+#define  NT35510_CMD_RDBY                  0x7C  /* Read By */
+#define  NT35510_CMD_RDAX                  0x7D  /* Read Ax */
+#define  NT35510_CMD_RDAY                  0x7E  /* Read Ay */
+#define  NT35510_CMD_RDDDBS                0xA1  /* Read DDB start */
+#define  NT35510_CMD_RDDDBC                0xA8  /* Read DDB continue */
+#define  NT35510_CMD_RDDCS                 0xAA  /* Read first checksum */
+#define  NT35510_CMD_RDCCS                 0xAF  /* Read continue checksum */
+#define  NT35510_CMD_RDID1                 0xDA  /* Read ID1 value */
+#define  NT35510_CMD_RDID2                 0xDB  /* Read ID2 value */
+#define  NT35510_CMD_RDID3                 0xDC  /* Read ID3 value */
+
+/* Parameter TELOM : Tearing Effect Line Output Mode : possible values */
+#define NT35510_TEEON_TELOM_VBLANKING_INFO_ONLY            0x00
+#define NT35510_TEEON_TELOM_VBLANKING_AND_HBLANKING_INFO   0x01
+
+/* Possible used values of MADCTR */
+#define NT35510_MADCTR_MODE_PORTRAIT       0x00
+#define NT35510_MADCTR_MODE_LANDSCAPE      0x60  /* MY = 0, MX = 1, MV = 1, ML = 0, RGB = 0 */
+
+/* Possible values of COLMOD parameter corresponding to used pixel formats */
+#define  NT35510_COLMOD_RGB565             0x55
+#define  NT35510_COLMOD_RGB888             0x77
+
+/**
+  * @brief  NT35510_480X800 frequency divider
+  */
+#define NT35510_480X800_FREQUENCY_DIVIDER  2   /* LCD Frequency divider      */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/** @defgroup NT35510_Exported_Macros NT35510 Exported Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @addtogroup NT35510_Exported_Functions
+  * @{
+  */
+void DSI_IO_WriteCmd(uint32_t NbrParams, uint8_t *pParams);
+uint8_t NT35510_Init(uint32_t ColorCoding, uint32_t orientation);
+uint8_t NT35510_DeInit(void);
+void NT35510_IO_Delay(uint32_t Delay);
+
+/**
+  * @}
+  */
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __NT35510_H */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Drivers/BSP/Components/otm8009a/Release_Notes.html b/Drivers/BSP/Components/otm8009a/Release_Notes.html
new file mode 100644
index 0000000..052fc75
--- /dev/null
+++ b/Drivers/BSP/Components/otm8009a/Release_Notes.html
@@ -0,0 +1,245 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html xmlns:v="urn:schemas-microsoft-com:vml" xmlns:o="urn:schemas-microsoft-com:office:office" xmlns:w="urn:schemas-microsoft-com:office:word" xmlns="http://www.w3.org/TR/REC-html40"><head>
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+
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+
+
+  
+
+  
+
+  
+  <style>
+<!--
+/* Style Definitions */
+p.MsoNormal, li.MsoNormal, div.MsoNormal
+{mso-style-parent:"";
+margin:0in;
+margin-bottom:.0001pt;
+mso-pagination:widow-orphan;
+font-size:12.0pt;
+font-family:"Times New Roman";
+mso-fareast-font-family:"Times New Roman";}
+h2
+{mso-style-next:Normal;
+margin-top:12.0pt;
+margin-right:0in;
+margin-bottom:3.0pt;
+margin-left:0in;
+mso-pagination:widow-orphan;
+page-break-after:avoid;
+mso-outline-level:2;
+font-size:14.0pt;
+font-family:Arial;
+font-weight:bold;
+font-style:italic;}
+a:link, span.MsoHyperlink
+{color:blue;
+text-decoration:underline;
+text-underline:single;}
+a:visited, span.MsoHyperlinkFollowed
+{color:blue;
+text-decoration:underline;
+text-underline:single;}
+p
+{mso-margin-top-alt:auto;
+margin-right:0in;
+mso-margin-bottom-alt:auto;
+margin-left:0in;
+mso-pagination:widow-orphan;
+font-size:12.0pt;
+font-family:"Times New Roman";
+mso-fareast-font-family:"Times New Roman";}
+@page Section1
+{size:8.5in 11.0in;
+margin:1.0in 1.25in 1.0in 1.25in;
+mso-header-margin:.5in;
+mso-footer-margin:.5in;
+mso-paper-source:0;}
+div.Section1
+{page:Section1;}
+-->
+  </style><!--[if gte mso 10]> <style> /* Style Definitions */ table.MsoNormalTable {mso-style-name:"Table Normal"; mso-tstyle-rowband-size:0; mso-tstyle-colband-size:0; mso-style-noshow:yes; mso-style-parent:""; mso-padding-alt:0in 5.4pt 0in 5.4pt; mso-para-margin:0in; mso-para-margin-bottom:.0001pt; mso-pagination:widow-orphan; font-size:10.0pt; font-family:"Times New Roman"; mso-ansi-language:#0400; mso-fareast-language:#0400; mso-bidi-language:#0400;} </style> <![endif]--><!--[if gte mso 9]><xml> <o:shapedefaults v:ext="edit" spidmax="5122"/> </xml><![endif]--><!--[if gte mso 9]><xml> <o:shapelayout v:ext="edit"> <o:idmap v:ext="edit" data="1"/> </o:shapelayout></xml><![endif]-->
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+<p class="MsoNormal"><span style="font-family: Arial;"><o:p><br>
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+<div align="center">
+<table class="MsoNormalTable" style="width: 675pt;" border="0" cellpadding="0" cellspacing="0" width="900">
+  <tbody>
+    <tr>
+      <td style="padding: 0cm;" valign="top">
+      <table class="MsoNormalTable" style="width: 675pt;" border="0" cellpadding="0" cellspacing="0" width="900">
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+          <tr>
+            <td style="vertical-align: top;">
+            <p class="MsoNormal"><span style="font-size: 8pt; font-family: Arial; color: blue;"><a href="../../../../Release_Notes.html">Back to Release page</a><o:p></o:p></span></p>
+            </td>
+          </tr>
+          <tr style="">
+            <td style="padding: 1.5pt;">
+            <h1 style="margin-bottom: 18pt; text-align: center;" align="center"><span style="font-size: 20pt; font-family: Verdana; color: rgb(51, 102, 255);">Release
+Notes for OTM8009A Component Driver</span><span style="font-size: 20pt; font-family: Verdana;"><o:p></o:p></span></h1>
+            <p class="MsoNormal" style="text-align: center;" align="center"><span style="font-size: 10pt; font-family: Arial; color: black;">Copyright
+2017 STMicroelectronics</span><span style="color: black;"><u1:p></u1:p><o:p></o:p></span></p>
+            <p class="MsoNormal" style="text-align: center;" align="center"><span style="font-size: 10pt; font-family: Arial; color: black;"><img alt="" id="_x0000_i1025" src="../../../../_htmresc/st_logo.png" style="border: 0px solid ; width: 86px; height: 65px;"></span><span style="font-size: 10pt;"><o:p></o:p></span></p>
+            </td>
+          </tr>
+        </tbody>
+      </table>
+      <p class="MsoNormal"><span style="font-family: Arial; display: none;"><o:p>&nbsp;</o:p></span></p>
+      <table style="width: 675pt;" class="MsoNormalTable" border="0" cellpadding="0" width="900">
+        <tbody>
+          <tr style="">
+            <td style="padding: 0cm;" valign="top"><span style="font-size: 10pt; font-family: Verdana;"></span><h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial;"><a name="History"></a><span style="font-size: 12pt; color: white;">Update History</span></h2><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 180px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.0.4
+/ 23-November-2020 <o:p></o:p></span></h3>
+
+            
+            <p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
+Changes<o:p></o:p></span></u></b></p>
+
+
+
+            <span style="font-size: 10pt; font-family: Verdana;"></span>
+            <span style="font-size: 10pt; font-family: Verdana;"></span>
+            <span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;"></span>
+            <span style="font-size: 10pt; font-family: Verdana;"></span>
+            <span style="font-size: 10pt; font-family: Verdana;"></span>
+            <span style="font-size: 10pt; font-family: Verdana;"></span>
+            <span style="font-size: 10pt; font-family: Verdana;"></span>
+            <span style="font-size: 10pt; font-family: Verdana;"></span>
+            <span style="font-size: 10pt; font-family: Verdana;"></span>
+            
+            
+            <ul style="list-style-type: square;"><li><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;">Update otm8009a.h to support ARM compiler Keil V6</span></li></ul><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 180px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.0.3
+/ 07-April-2017 <o:p></o:p></span></h3>
+
+            
+            <p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
+Changes<o:p></o:p></span></u></b></p>
+
+
+
+            <span style="font-size: 10pt; font-family: Verdana;"></span>
+            <span style="font-size: 10pt; font-family: Verdana;"></span>
+            <span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;"></span>
+            <span style="font-size: 10pt; font-family: Verdana;"></span>
+            <span style="font-size: 10pt; font-family: Verdana;"></span>
+            <span style="font-size: 10pt; font-family: Verdana;"></span>
+            <span style="font-size: 10pt; font-family: Verdana;"></span>
+            <span style="font-size: 10pt; font-family: Verdana;"></span>
+            <span style="font-size: 10pt; font-family: Verdana;"></span>
+            
+            
+            <ul style="list-style-type: square;"><li><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;">Update comments to be used for PDSC generation</span></li></ul><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 180px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.0.2
+/ 27-January-2017 <o:p></o:p></span></h3>
+
+            <p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
+Changes<o:p></o:p></span></u></b></p>
+
+
+            <span style="font-size: 10pt; font-family: Verdana;"></span>
+            <span style="font-size: 10pt; font-family: Verdana;"></span>
+            <span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;"></span>
+            <span style="font-size: 10pt; font-family: Verdana;"></span>
+            <span style="font-size: 10pt; font-family: Verdana;"></span>
+            <span style="font-size: 10pt; font-family: Verdana;"></span>
+            <span style="font-size: 10pt; font-family: Verdana;"></span>
+            <span style="font-size: 10pt; font-family: Verdana;"></span>
+            <span style="font-size: 10pt; font-family: Verdana;"></span>
+            
+            <ul style="list-style-type: square;">
+<li><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;">Update DSI controller timings</span></li>
+              <li><span style="font-size: 10pt; font-family: Verdana;">CABC LEDPWM frequency adjusted to 19,5kHz<br>
+</span></li>
+            </ul>
+            <span style="font-size: 10pt; font-family: Verdana;"></span>
+            <h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 180px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.0.1
+/ 04-August-2016 <o:p></o:p></span></h3>
+
+
+            <p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
+Changes<o:p></o:p></span></u></b></p>
+
+            <span style="font-size: 10pt; font-family: Verdana;"></span>
+            <span style="font-size: 10pt; font-family: Verdana;"></span>
+            <span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;"></span>
+            <span style="font-size: 10pt; font-family: Verdana;"></span>
+            <span style="font-size: 10pt; font-family: Verdana;"></span>
+            <span style="font-size: 10pt; font-family: Verdana;"></span>
+            <span style="font-size: 10pt; font-family: Verdana;"></span>
+            <span style="font-size: 10pt; font-family: Verdana;"></span>
+            <span style="font-size: 10pt; font-family: Verdana;"></span>
+            <ul style="list-style-type: square;">
+<li><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;">Update DSI controller timings</span></li>
+            </ul>
+            <h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 180px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.0.0
+/ 03-August-2015 <o:p></o:p></span></h3>
+
+<p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
+Changes<o:p></o:p></span></u></b></p>
+<span style="font-size: 10pt; font-family: Verdana;"></span>
+<span style="font-size: 10pt; font-family: Verdana;"></span>
+<span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;"></span>
+<span style="font-size: 10pt; font-family: Verdana;"></span>
+<span style="font-size: 10pt; font-family: Verdana;"></span>
+<span style="font-size: 10pt; font-family: Verdana;"></span>
+<span style="font-size: 10pt; font-family: Verdana;"></span>
+<span style="font-size: 10pt; font-family: Verdana;"></span>
+<span style="font-size: 10pt; font-family: Verdana;"></span>
+<ul style="list-style-type: square;"><li><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;">First official release of OTM8009A LCD component driver<br>
+</span></li></ul><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic; font-weight: bold;"></span></span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic; font-weight: bold;"></span></span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic; font-weight: bold;"></span></span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic; font-weight: bold;"></span></span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic; font-weight: bold;"></span></span><span style="font-size: 10pt; font-family: Verdana;"></span><h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial;"><a name="License"></a><span style="font-size: 12pt; color: white;">License<o:p></o:p></span><br></h2><div style="text-align: justify;"><font size="-1"><span style="font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are
+met:</span><br>
+            </font>
+            <ol><li><font size="-1"><span style="font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.</span><span style="font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"></span></font></li><li><font size="-1"><span style="font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Redistributions
+in binary form must reproduce the above copyright notice, this list of
+conditions and the following disclaimer in </span><span style="font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">the documentation and/or other materials provided with the distribution.</span><span style="font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"></span></font></li><li><font size="-1"><span style="font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived </span><br>
+                </font>
+              </li></ol>
+            <font size="-1"><span style="font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; from this software without specific prior written permission.</span><br>
+            <span style="font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"></span><br>
+            <span style="font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED</span><span style="font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"> WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A </span><span style="font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY </span><span style="font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, </span><span style="font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER</span><span style="font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"> CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR </span><span style="font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.</span></font>
+            
+            </div>
+<p class="MsoNormal"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;; color: black;"><o:p></o:p></span></p>
+<b><span style="font-size: 10pt; font-family: Verdana; color: black;"></span></b>
+            
+            <div class="MsoNormal" style="text-align: center;" align="center"><span style="color: black;">
+            <hr align="center" size="2" width="100%"></span></div>
+            <div style="margin-left: 120px;"><span style="font-size: 10pt; font-family: Verdana; color: black;">For
+complete documentation on </span><span style="font-size: 10pt; font-family: Verdana;">STM32<span style="color: black;">&nbsp;Microcontrollers
+visit </span><u><span style="color: blue;"><a href="http://www.st.com/internet/mcu/class/1734.jsp" target="_blank">www.st.com/STM32</a></span></u></span></div>
+            </td>
+          </tr>
+        <tr><td style="padding: 0cm;" valign="top"><br>
+</td></tr></tbody>
+      </table>
+      <p class="MsoNormal"><span style="font-size: 10pt;"><o:p></o:p></span></p>
+      </td>
+    </tr>
+  </tbody>
+</table>
+</div>
+<p class="MsoNormal"><o:p>&nbsp;</o:p></p>
+</div>
+
+</body></html>
\ No newline at end of file
diff --git a/Drivers/BSP/Components/otm8009a/otm8009a.c b/Drivers/BSP/Components/otm8009a/otm8009a.c
new file mode 100644
index 0000000..604c864
--- /dev/null
+++ b/Drivers/BSP/Components/otm8009a/otm8009a.c
@@ -0,0 +1,452 @@
+/**
+  ******************************************************************************
+  * @file    otm8009a.c
+  * @author  MCD Application Team
+  * @brief   This file provides the LCD Driver for KoD KM-040TMP-02-0621 (WVGA)
+  *          DSI LCD Display OTM8009A.   
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "otm8009a.h"
+
+/** @addtogroup BSP
+  * @{
+  */
+  
+/** @addtogroup Components
+  * @{
+  */ 
+
+/** @defgroup OTM8009A OTM8009A
+  * @brief     This file provides a set of functions needed to drive the 
+  *            otm8009a IC display driver.
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup OTM8009A_Private_Constants OTM8009A Private Constants
+  * @{
+  */
+
+/*
+ * @brief Constant tables of register settings used to transmit DSI
+ * command packets as power up initialization sequence of the KoD LCD (OTM8009A LCD Driver)
+ */
+const uint8_t lcdRegData1[]  = {0x80,0x09,0x01,0xFF};
+const uint8_t lcdRegData2[]  = {0x80,0x09,0xFF};
+const uint8_t lcdRegData3[]  = {0x00,0x09,0x0F,0x0E,0x07,0x10,0x0B,0x0A,0x04,0x07,0x0B,0x08,0x0F,0x10,0x0A,0x01,0xE1};
+const uint8_t lcdRegData4[]  = {0x00,0x09,0x0F,0x0E,0x07,0x10,0x0B,0x0A,0x04,0x07,0x0B,0x08,0x0F,0x10,0x0A,0x01,0xE2};
+const uint8_t lcdRegData5[]  = {0x79,0x79,0xD8};
+const uint8_t lcdRegData6[]  = {0x00,0x01,0xB3};
+const uint8_t lcdRegData7[]  = {0x85,0x01,0x00,0x84,0x01,0x00,0xCE};
+const uint8_t lcdRegData8[]  = {0x18,0x04,0x03,0x39,0x00,0x00,0x00,0x18,0x03,0x03,0x3A,0x00,0x00,0x00,0xCE};
+const uint8_t lcdRegData9[]  = {0x18,0x02,0x03,0x3B,0x00,0x00,0x00,0x18,0x01,0x03,0x3C,0x00,0x00,0x00,0xCE};
+const uint8_t lcdRegData10[] = {0x01,0x01,0x20,0x20,0x00,0x00,0x01,0x02,0x00,0x00,0xCF};
+const uint8_t lcdRegData11[] = {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xCB};
+const uint8_t lcdRegData12[] = {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xCB};
+const uint8_t lcdRegData13[] = {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xCB};
+const uint8_t lcdRegData14[] = {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xCB};
+const uint8_t lcdRegData15[] = {0x00,0x04,0x04,0x04,0x04,0x04,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xCB};
+const uint8_t lcdRegData16[] = {0x00,0x00,0x00,0x00,0x00,0x00,0x04,0x04,0x04,0x04,0x04,0x00,0x00,0x00,0x00,0xCB};
+const uint8_t lcdRegData17[] = {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xCB};
+const uint8_t lcdRegData18[] = {0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xCB};
+const uint8_t lcdRegData19[] = {0x00,0x26,0x09,0x0B,0x01,0x25,0x00,0x00,0x00,0x00,0xCC};
+const uint8_t lcdRegData20[] = {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x26,0x0A,0x0C,0x02,0xCC};
+const uint8_t lcdRegData21[] = {0x25,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xCC};
+const uint8_t lcdRegData22[] = {0x00,0x25,0x0C,0x0A,0x02,0x26,0x00,0x00,0x00,0x00,0xCC};
+const uint8_t lcdRegData23[] = {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x25,0x0B,0x09,0x01,0xCC};
+const uint8_t lcdRegData24[] = {0x26,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xCC};
+const uint8_t lcdRegData25[] = {0xFF,0xFF,0xFF,0xFF};    
+/*
+  * CASET value (Column Address Set) : X direction LCD GRAM boundaries
+  * depending on LCD orientation mode and PASET value (Page Address Set) : Y direction
+  * LCD GRAM boundaries depending on LCD orientation mode
+  * XS[15:0] = 0x000 = 0, XE[15:0] = 0x31F = 799 for landscape mode : apply to CASET
+  * YS[15:0] = 0x000 = 0, YE[15:0] = 0x31F = 799 for portrait mode : : apply to PASET
+  */
+const uint8_t lcdRegData27[] = {0x00, 0x00, 0x03, 0x1F, OTM8009A_CMD_CASET};
+/*
+  * XS[15:0] = 0x000 = 0, XE[15:0] = 0x1DF = 479 for portrait mode : apply to CASET
+  * YS[15:0] = 0x000 = 0, YE[15:0] = 0x1DF = 479 for landscape mode : apply to PASET
+ */
+const uint8_t lcdRegData28[] = {0x00, 0x00, 0x01, 0xDF, OTM8009A_CMD_PASET};
+
+
+const uint8_t ShortRegData1[]  = {OTM8009A_CMD_NOP, 0x00};
+const uint8_t ShortRegData2[]  = {OTM8009A_CMD_NOP, 0x80};
+const uint8_t ShortRegData3[]  = {0xC4, 0x30};
+const uint8_t ShortRegData4[]  = {OTM8009A_CMD_NOP, 0x8A};
+const uint8_t ShortRegData5[]  = {0xC4, 0x40};
+const uint8_t ShortRegData6[]  = {OTM8009A_CMD_NOP, 0xB1};
+const uint8_t ShortRegData7[]  = {0xC5, 0xA9};
+const uint8_t ShortRegData8[]  = {OTM8009A_CMD_NOP, 0x91};
+const uint8_t ShortRegData9[]  = {0xC5, 0x34};
+const uint8_t ShortRegData10[] = {OTM8009A_CMD_NOP, 0xB4};
+const uint8_t ShortRegData11[] = {0xC0, 0x50};
+const uint8_t ShortRegData12[] = {0xD9, 0x4E};
+const uint8_t ShortRegData13[] = {OTM8009A_CMD_NOP, 0x81};
+const uint8_t ShortRegData14[] = {0xC1, 0x66};
+const uint8_t ShortRegData15[] = {OTM8009A_CMD_NOP, 0xA1};
+const uint8_t ShortRegData16[] = {0xC1, 0x08};
+const uint8_t ShortRegData17[] = {OTM8009A_CMD_NOP, 0x92};
+const uint8_t ShortRegData18[] = {0xC5, 0x01};
+const uint8_t ShortRegData19[] = {OTM8009A_CMD_NOP, 0x95};
+const uint8_t ShortRegData20[] = {OTM8009A_CMD_NOP, 0x94};
+const uint8_t ShortRegData21[] = {0xC5, 0x33};
+const uint8_t ShortRegData22[] = {OTM8009A_CMD_NOP, 0xA3};
+const uint8_t ShortRegData23[] = {0xC0, 0x1B};
+const uint8_t ShortRegData24[] = {OTM8009A_CMD_NOP, 0x82};
+const uint8_t ShortRegData25[] = {0xC5, 0x83};
+const uint8_t ShortRegData26[] = {0xC4, 0x83};
+const uint8_t ShortRegData27[] = {0xC1, 0x0E};
+const uint8_t ShortRegData28[] = {OTM8009A_CMD_NOP, 0xA6};
+const uint8_t ShortRegData29[] = {OTM8009A_CMD_NOP, 0xA0};
+const uint8_t ShortRegData30[] = {OTM8009A_CMD_NOP, 0xB0};
+const uint8_t ShortRegData31[] = {OTM8009A_CMD_NOP, 0xC0};
+const uint8_t ShortRegData32[] = {OTM8009A_CMD_NOP, 0xD0};
+const uint8_t ShortRegData33[] = {OTM8009A_CMD_NOP, 0x90};
+const uint8_t ShortRegData34[] = {OTM8009A_CMD_NOP, 0xE0};
+const uint8_t ShortRegData35[] = {OTM8009A_CMD_NOP, 0xF0};
+const uint8_t ShortRegData36[] = {OTM8009A_CMD_SLPOUT, 0x00};
+const uint8_t ShortRegData37[] = {OTM8009A_CMD_COLMOD, OTM8009A_COLMOD_RGB565};
+const uint8_t ShortRegData38[] = {OTM8009A_CMD_COLMOD, OTM8009A_COLMOD_RGB888};
+const uint8_t ShortRegData39[] = {OTM8009A_CMD_MADCTR, OTM8009A_MADCTR_MODE_LANDSCAPE};
+const uint8_t ShortRegData40[] = {OTM8009A_CMD_WRDISBV, 0x7F};
+const uint8_t ShortRegData41[] = {OTM8009A_CMD_WRCTRLD, 0x2C};
+const uint8_t ShortRegData42[] = {OTM8009A_CMD_WRCABC, 0x02};
+const uint8_t ShortRegData43[] = {OTM8009A_CMD_WRCABCMB, 0xFF};
+const uint8_t ShortRegData44[] = {OTM8009A_CMD_DISPON, 0x00};
+const uint8_t ShortRegData45[] = {OTM8009A_CMD_RAMWR, 0x00};
+const uint8_t ShortRegData46[] = {0xCF, 0x00};
+const uint8_t ShortRegData47[] = {0xC5, 0x66};
+const uint8_t ShortRegData48[] = {OTM8009A_CMD_NOP, 0xB6};
+const uint8_t ShortRegData49[] = {0xF5, 0x06};
+const uint8_t ShortRegData50[] = {OTM8009A_CMD_NOP, 0xB1};
+const uint8_t ShortRegData51[] = {0xC6, 0x06};
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup OTM8009A_Exported_Variables
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Exported functions ---------------------------------------------------------*/
+/** @defgroup OTM8009A_Exported_Functions OTM8009A Exported Functions
+  * @{
+  */
+
+/**
+  * @brief  DSI IO write short/long command.
+  * @note : Can be surcharged by application code implementation of the function.
+  */
+__weak void DSI_IO_WriteCmd(uint32_t NbrParams, uint8_t *pParams)
+{
+  /* NOTE : This function Should not be modified, when it is needed,
+            the DSI_IO_WriteCmd could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Initializes the LCD KoD display part by communication in DSI mode in Video Mode
+  *         with IC Display Driver OTM8009A (see IC Driver specification for more information).
+  * @param  hdsi_eval : pointer on DSI configuration structure
+  * @param  hdsivideo_handle : pointer on DSI video mode configuration structure
+  * @retval Status
+  */
+uint8_t OTM8009A_Init(uint32_t ColorCoding, uint32_t orientation)
+{
+  /* Enable CMD2 to access vendor specific commands                               */
+  /* Enter in command 2 mode and set EXTC to enable address shift function (0x00) */
+  DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData1);
+  DSI_IO_WriteCmd( 3, (uint8_t *)lcdRegData1);
+
+  /* Enter ORISE Command 2 */
+  DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData2); /* Shift address to 0x80 */
+  DSI_IO_WriteCmd( 2, (uint8_t *)lcdRegData2);
+
+  /////////////////////////////////////////////////////////////////////
+  /* SD_PCH_CTRL - 0xC480h - 129th parameter - Default 0x00          */
+  /* Set SD_PT                                                       */
+  /* -> Source output level during porch and non-display area to GND */
+  DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData2);
+  DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData3);
+  OTM8009A_IO_Delay(10);
+  /* Not documented */
+  DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData4);
+  DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData5);
+  OTM8009A_IO_Delay(10);
+  /////////////////////////////////////////////////////////////////////
+
+  /* PWR_CTRL4 - 0xC4B0h - 178th parameter - Default 0xA8 */
+  /* Set gvdd_en_test                                     */
+  /* -> enable GVDD test mode !!!                         */
+  DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData6);
+  DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData7);
+
+  /* PWR_CTRL2 - 0xC590h - 146th parameter - Default 0x79      */
+  /* Set pump 4 vgh voltage                                    */
+  /* -> from 15.0v down to 13.0v                               */
+  /* Set pump 5 vgh voltage                                    */
+  /* -> from -12.0v downto -9.0v                               */
+  DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData8);
+  DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData9);
+
+  /* P_DRV_M - 0xC0B4h - 181th parameter - Default 0x00 */
+  /* -> Column inversion                                */
+  DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData10);
+  DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData11);
+
+  /* VCOMDC - 0xD900h - 1st parameter - Default 0x39h */
+  /* VCOM Voltage settings                            */
+  /* -> from -1.0000v downto -1.2625v                 */
+  DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData1);
+  DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData12);
+
+  /* Oscillator adjustment for Idle/Normal mode (LPDT only) set to 65Hz (default is 60Hz) */
+  DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData13);
+  DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData14);
+
+  /* Video mode internal */
+  DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData15);
+  DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData16);
+
+  /* PWR_CTRL2 - 0xC590h - 147h parameter - Default 0x00 */
+  /* Set pump 4&5 x6                                     */
+  /* -> ONLY VALID when PUMP4_EN_ASDM_HV = "0"           */
+  DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData17);
+  DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData18);
+
+  /* PWR_CTRL2 - 0xC590h - 150th parameter - Default 0x33h */
+  /* Change pump4 clock ratio                              */
+  /* -> from 1 line to 1/2 line                            */
+  DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData19);
+  DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData9);
+
+  /* GVDD/NGVDD settings */
+  DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData1);
+  DSI_IO_WriteCmd( 2, (uint8_t *)lcdRegData5);
+
+  /* PWR_CTRL2 - 0xC590h - 149th parameter - Default 0x33h */
+  /* Rewrite the default value !                           */
+  DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData20);
+  DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData21);
+
+  /* Panel display timing Setting 3 */
+  DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData22);
+  DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData23);
+
+  /* Power control 1 */
+  DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData24);
+  DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData25);
+
+  /* Source driver precharge */
+  DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData13);
+  DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData26);
+
+  DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData15);
+  DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData27);
+
+  DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData28);
+  DSI_IO_WriteCmd( 2, (uint8_t *)lcdRegData6);
+
+  /* GOAVST */
+  DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData2);
+  DSI_IO_WriteCmd( 6, (uint8_t *)lcdRegData7);
+
+  DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData29);
+  DSI_IO_WriteCmd( 14, (uint8_t *)lcdRegData8);
+
+  DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData30);
+  DSI_IO_WriteCmd( 14, (uint8_t *)lcdRegData9);
+
+  DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData31);
+  DSI_IO_WriteCmd( 10, (uint8_t *)lcdRegData10);
+
+  DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData32);
+  DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData46);
+
+  DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData2);
+  DSI_IO_WriteCmd( 10, (uint8_t *)lcdRegData11);
+
+  DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData33);
+  DSI_IO_WriteCmd( 15, (uint8_t *)lcdRegData12);
+
+  DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData29);
+  DSI_IO_WriteCmd( 15, (uint8_t *)lcdRegData13);
+
+  DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData30);
+  DSI_IO_WriteCmd( 10, (uint8_t *)lcdRegData14);
+
+  DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData31);
+  DSI_IO_WriteCmd( 15, (uint8_t *)lcdRegData15);
+
+  DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData32);
+  DSI_IO_WriteCmd( 15, (uint8_t *)lcdRegData16);
+
+  DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData34);
+  DSI_IO_WriteCmd( 10, (uint8_t *)lcdRegData17);
+
+  DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData35);
+  DSI_IO_WriteCmd( 10, (uint8_t *)lcdRegData18);
+
+  DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData2);
+  DSI_IO_WriteCmd( 10, (uint8_t *)lcdRegData19);
+
+  DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData33);
+  DSI_IO_WriteCmd( 15, (uint8_t *)lcdRegData20);
+
+  DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData29);
+  DSI_IO_WriteCmd( 15, (uint8_t *)lcdRegData21);
+
+  DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData30);
+  DSI_IO_WriteCmd( 10, (uint8_t *)lcdRegData22);
+
+  DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData31);
+  DSI_IO_WriteCmd( 15, (uint8_t *)lcdRegData23);
+
+  DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData32);
+  DSI_IO_WriteCmd( 15, (uint8_t *)lcdRegData24);
+
+  /////////////////////////////////////////////////////////////////////////////
+  /* PWR_CTRL1 - 0xc580h - 130th parameter - default 0x00 */
+  /* Pump 1 min and max DM                                */
+  DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData13);
+  DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData47);
+  DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData48);
+  DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData49);
+  /////////////////////////////////////////////////////////////////////////////
+
+  /* CABC LEDPWM frequency adjusted to 19,5kHz */
+  DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData50);
+  DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData51);
+  
+  /* Exit CMD2 mode */
+  DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData1);
+  DSI_IO_WriteCmd( 3, (uint8_t *)lcdRegData25);
+
+  /*************************************************************************** */
+  /* Standard DCS Initialization TO KEEP CAN BE DONE IN HSDT                   */
+  /*************************************************************************** */
+
+  /* NOP - goes back to DCS std command ? */
+  DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData1);
+          
+  /* Gamma correction 2.2+ table (HSDT possible) */
+  DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData1);
+  DSI_IO_WriteCmd( 16, (uint8_t *)lcdRegData3);
+  
+  /* Gamma correction 2.2- table (HSDT possible) */
+  DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData1);
+  DSI_IO_WriteCmd( 16, (uint8_t *)lcdRegData4);
+          
+  /* Send Sleep Out command to display : no parameter */
+  DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData36);
+  
+  /* Wait for sleep out exit */
+  OTM8009A_IO_Delay(120);
+
+  switch(ColorCoding)
+  {
+  case OTM8009A_FORMAT_RBG565 :
+    /* Set Pixel color format to RGB565 */
+    DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData37);
+    break;
+  case OTM8009A_FORMAT_RGB888 :
+    /* Set Pixel color format to RGB888 */
+    DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData38);
+    break;
+  default :
+    break;
+  }
+
+  /* Send command to configure display in landscape orientation mode. By default
+      the orientation mode is portrait  */
+  if(orientation == OTM8009A_ORIENTATION_LANDSCAPE)
+  {
+    DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData39);
+    DSI_IO_WriteCmd( 4, (uint8_t *)lcdRegData27);
+    DSI_IO_WriteCmd( 4, (uint8_t *)lcdRegData28);
+  }
+
+  /** CABC : Content Adaptive Backlight Control section start >> */
+  /* Note : defaut is 0 (lowest Brightness), 0xFF is highest Brightness, try 0x7F : intermediate value */
+  DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData40);
+
+  /* defaut is 0, try 0x2C - Brightness Control Block, Display Dimming & BackLight on */
+  DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData41);
+
+  /* defaut is 0, try 0x02 - image Content based Adaptive Brightness [Still Picture] */
+  DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData42);
+
+  /* defaut is 0 (lowest Brightness), 0xFF is highest Brightness */
+  DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData43);
+
+  /** CABC : Content Adaptive Backlight Control section end << */
+
+  /* Send Command Display On */
+  DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData44);
+
+  /* NOP command */
+  DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData1);
+
+  /* Send Command GRAM memory write (no parameters) : this initiates frame write via other DSI commands sent by */
+  /* DSI host from LTDC incoming pixels in video mode */
+  DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData45);
+
+  return 0;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Drivers/BSP/Components/otm8009a/otm8009a.h b/Drivers/BSP/Components/otm8009a/otm8009a.h
new file mode 100644
index 0000000..d5b1fc5
--- /dev/null
+++ b/Drivers/BSP/Components/otm8009a/otm8009a.h
@@ -0,0 +1,222 @@
+/**
+  ******************************************************************************
+  * @file    otm8009a.h
+  * @author  MCD Application Team
+  * @brief   This file contains all the constants parameters for the OTM8009A
+  *          which is the LCD Driver for KoD KM-040TMP-02-0621 (WVGA)
+  *          DSI LCD Display.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __OTM8009A_H
+#define __OTM8009A_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include <stdint.h>
+/** @addtogroup BSP
+  * @{
+  */
+
+/** @addtogroup Components
+  * @{
+  */
+
+/** @addtogroup otm8009a
+  * @{
+  */
+
+/** @addtogroup OTM8009A_Exported_Variables
+  * @{
+  */
+
+#if defined ( __GNUC__ ) || (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) /* GNU and ARM Compiler 6 compilers */
+#ifndef __weak
+#define __weak __attribute__((weak))
+#endif /* __weak */
+#endif /* __GNUC__ || (__ARMCC_VERSION && (__ARMCC_VERSION >= 6010050)) */
+
+/**
+ *  @brief LCD_OrientationTypeDef
+ *  Possible values of Display Orientation
+ */
+#define OTM8009A_ORIENTATION_PORTRAIT    ((uint32_t)0x00) /* Portrait orientation choice of LCD screen  */
+#define OTM8009A_ORIENTATION_LANDSCAPE   ((uint32_t)0x01) /* Landscape orientation choice of LCD screen */
+
+/**
+ *  @brief  Possible values of
+ *  pixel data format (ie color coding) transmitted on DSI Data lane in DSI packets
+ */
+#define OTM8009A_FORMAT_RGB888    ((uint32_t)0x00) /* Pixel format chosen is RGB888 : 24 bpp */
+#define OTM8009A_FORMAT_RBG565    ((uint32_t)0x02) /* Pixel format chosen is RGB565 : 16 bpp */
+
+/**
+  * @brief  otm8009a_480x800 Size
+  */
+
+/* Width and Height in Portrait mode */
+#define  OTM8009A_480X800_WIDTH             ((uint16_t)480)     /* LCD PIXEL WIDTH   */
+#define  OTM8009A_480X800_HEIGHT            ((uint16_t)800)     /* LCD PIXEL HEIGHT  */
+
+/* Width and Height in Landscape mode */
+#define  OTM8009A_800X480_WIDTH             ((uint16_t)800)     /* LCD PIXEL WIDTH   */
+#define  OTM8009A_800X480_HEIGHT            ((uint16_t)480)     /* LCD PIXEL HEIGHT  */
+
+/**
+  * @brief  OTM8009A_480X800 Timing parameters for Portrait orientation mode
+  */
+#define  OTM8009A_480X800_HSYNC             ((uint16_t)2)      /* Horizontal synchronization */
+#define  OTM8009A_480X800_HBP               ((uint16_t)34)     /* Horizontal back porch      */
+#define  OTM8009A_480X800_HFP               ((uint16_t)34)     /* Horizontal front porch     */
+#define  OTM8009A_480X800_VSYNC             ((uint16_t)1)      /* Vertical synchronization   */
+#define  OTM8009A_480X800_VBP               ((uint16_t)15)      /* Vertical back porch        */
+#define  OTM8009A_480X800_VFP               ((uint16_t)16)      /* Vertical front porch       */
+
+/**
+  * @brief  OTM8009A_800X480 Timing parameters for Landscape orientation mode
+  *         Same values as for Portrait mode in fact.
+  */
+#define  OTM8009A_800X480_HSYNC             OTM8009A_480X800_VSYNC  /* Horizontal synchronization */
+#define  OTM8009A_800X480_HBP               OTM8009A_480X800_VBP    /* Horizontal back porch      */
+#define  OTM8009A_800X480_HFP               OTM8009A_480X800_VFP    /* Horizontal front porch     */
+#define  OTM8009A_800X480_VSYNC             OTM8009A_480X800_HSYNC  /* Vertical synchronization   */
+#define  OTM8009A_800X480_VBP               OTM8009A_480X800_HBP    /* Vertical back porch        */
+#define  OTM8009A_800X480_VFP               OTM8009A_480X800_HFP    /* Vertical front porch       */
+
+
+/* List of OTM8009A used commands                                  */
+/* Detailed in OTM8009A Data Sheet 'DATA_SHEET_OTM8009A_V0 92.pdf' */
+/* Version of 14 June 2012                                         */
+#define  OTM8009A_CMD_NOP                   0x00  /* NOP command      */
+#define  OTM8009A_CMD_SWRESET               0x01  /* Sw reset command */
+#define  OTM8009A_CMD_RDDMADCTL             0x0B  /* Read Display MADCTR command : read memory display access ctrl */
+#define  OTM8009A_CMD_RDDCOLMOD             0x0C  /* Read Display pixel format */
+#define  OTM8009A_CMD_SLPIN                 0x10  /* Sleep In command */
+#define  OTM8009A_CMD_SLPOUT                0x11  /* Sleep Out command */
+#define  OTM8009A_CMD_PTLON                 0x12  /* Partial mode On command */
+
+#define  OTM8009A_CMD_DISPOFF               0x28  /* Display Off command */
+#define  OTM8009A_CMD_DISPON                0x29  /* Display On command */
+
+#define  OTM8009A_CMD_CASET                 0x2A  /* Column address set command */
+#define  OTM8009A_CMD_PASET                 0x2B  /* Page address set command */
+
+#define  OTM8009A_CMD_RAMWR                 0x2C  /* Memory (GRAM) write command */
+#define  OTM8009A_CMD_RAMRD                 0x2E  /* Memory (GRAM) read command  */
+
+#define  OTM8009A_CMD_PLTAR                 0x30  /* Partial area command (4 parameters) */
+
+#define  OTM8009A_CMD_TEOFF                 0x34  /* Tearing Effect Line Off command : command with no parameter */
+
+#define  OTM8009A_CMD_TEEON                 0x35  /* Tearing Effect Line On command : command with 1 parameter 'TELOM' */
+
+/* Parameter TELOM : Tearing Effect Line Output Mode : possible values */
+#define OTM8009A_TEEON_TELOM_VBLANKING_INFO_ONLY            0x00
+#define OTM8009A_TEEON_TELOM_VBLANKING_AND_HBLANKING_INFO   0x01
+
+#define  OTM8009A_CMD_MADCTR                0x36  /* Memory Access write control command  */
+
+/* Possible used values of MADCTR */
+#define OTM8009A_MADCTR_MODE_PORTRAIT       0x00
+#define OTM8009A_MADCTR_MODE_LANDSCAPE      0x60  /* MY = 0, MX = 1, MV = 1, ML = 0, RGB = 0 */
+
+#define  OTM8009A_CMD_IDMOFF                0x38  /* Idle mode Off command */
+#define  OTM8009A_CMD_IDMON                 0x39  /* Idle mode On command  */
+
+#define  OTM8009A_CMD_COLMOD                0x3A  /* Interface Pixel format command */
+
+/* Possible values of COLMOD parameter corresponding to used pixel formats */
+#define  OTM8009A_COLMOD_RGB565             0x55
+#define  OTM8009A_COLMOD_RGB888             0x77
+
+#define  OTM8009A_CMD_RAMWRC                0x3C  /* Memory write continue command */
+#define  OTM8009A_CMD_RAMRDC                0x3E  /* Memory read continue command  */
+
+#define  OTM8009A_CMD_WRTESCN               0x44  /* Write Tearing Effect Scan line command */
+#define  OTM8009A_CMD_RDSCNL                0x45  /* Read  Tearing Effect Scan line command */
+
+/* CABC Management : ie : Content Adaptive Back light Control in IC OTM8009a */
+#define  OTM8009A_CMD_WRDISBV               0x51  /* Write Display Brightness command          */
+#define  OTM8009A_CMD_WRCTRLD               0x53  /* Write CTRL Display command                */
+#define  OTM8009A_CMD_WRCABC                0x55  /* Write Content Adaptive Brightness command */
+#define  OTM8009A_CMD_WRCABCMB              0x5E  /* Write CABC Minimum Brightness command     */
+
+/**
+  * @brief  OTM8009A_480X800 frequency divider
+  */
+#define OTM8009A_480X800_FREQUENCY_DIVIDER  2   /* LCD Frequency divider      */
+
+/**
+  * @}
+  */
+   
+/* Exported macro ------------------------------------------------------------*/
+   
+/** @defgroup OTM8009A_Exported_Macros OTM8009A Exported Macros
+  * @{
+  */ 
+
+/**
+  * @}
+  */ 
+
+/* Exported functions --------------------------------------------------------*/
+  
+/** @addtogroup OTM8009A_Exported_Functions
+  * @{
+  */
+void DSI_IO_WriteCmd(uint32_t NbrParams, uint8_t *pParams);
+uint8_t OTM8009A_Init(uint32_t ColorCoding, uint32_t orientation);
+void OTM8009A_IO_Delay(uint32_t Delay);
+/**
+  * @}
+  */
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __OTM8009A_480X800_H */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Drivers/BSP/STM32469I-Discovery/LICENSE.txt b/Drivers/BSP/STM32469I-Discovery/LICENSE.txt
new file mode 100644
index 0000000..b40364c
--- /dev/null
+++ b/Drivers/BSP/STM32469I-Discovery/LICENSE.txt
@@ -0,0 +1,6 @@
+This software component is provided to you as part of a software package and
+applicable license terms are in the  Package_license file. If you received this
+software component outside of a package or without applicable license terms,
+the terms of the BSD-3-Clause license shall apply. 
+You may obtain a copy of the BSD-3-Clause at:
+https://opensource.org/licenses/BSD-3-Clause
diff --git a/Drivers/BSP/STM32469I-Discovery/Release_Notes.html b/Drivers/BSP/STM32469I-Discovery/Release_Notes.html
new file mode 100644
index 0000000..eab5ca5
--- /dev/null
+++ b/Drivers/BSP/STM32469I-Discovery/Release_Notes.html
@@ -0,0 +1,369 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html xmlns:v="urn:schemas-microsoft-com:vml" xmlns:o="urn:schemas-microsoft-com:office:office" xmlns:w="urn:schemas-microsoft-com:office:word" xmlns="http://www.w3.org/TR/REC-html40"><head>
+
+
+
+
+
+  
+  <meta http-equiv="Content-Type" content="text/html; charset=ISO-8859-1">
+
+  
+  <link rel="File-List" href="Library_files/filelist.xml">
+
+  
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+
+
+  
+
+  
+
+  
+  <style>
+<!--
+/* Style Definitions */
+p.MsoNormal, li.MsoNormal, div.MsoNormal
+{mso-style-parent:"";
+margin:0in;
+margin-bottom:.0001pt;
+mso-pagination:widow-orphan;
+font-size:12.0pt;
+font-family:"Times New Roman";
+mso-fareast-font-family:"Times New Roman";}
+h2
+{mso-style-next:Normal;
+margin-top:12.0pt;
+margin-right:0in;
+margin-bottom:3.0pt;
+margin-left:0in;
+mso-pagination:widow-orphan;
+page-break-after:avoid;
+mso-outline-level:2;
+font-size:14.0pt;
+font-family:Arial;
+font-weight:bold;
+font-style:italic;}
+a:link, span.MsoHyperlink
+{color:blue;
+text-decoration:underline;
+text-underline:single;}
+a:visited, span.MsoHyperlinkFollowed
+{color:blue;
+text-decoration:underline;
+text-underline:single;}
+p
+{mso-margin-top-alt:auto;
+margin-right:0in;
+mso-margin-bottom-alt:auto;
+margin-left:0in;
+mso-pagination:widow-orphan;
+font-size:12.0pt;
+font-family:"Times New Roman";
+mso-fareast-font-family:"Times New Roman";}
+@page Section1
+{size:8.5in 11.0in;
+margin:1.0in 1.25in 1.0in 1.25in;
+mso-header-margin:.5in;
+mso-footer-margin:.5in;
+mso-paper-source:0;}
+div.Section1
+{page:Section1;}
+-->
+  </style><!--[if gte mso 10]> <style> /* Style Definitions */ table.MsoNormalTable {mso-style-name:"Table Normal"; mso-tstyle-rowband-size:0; mso-tstyle-colband-size:0; mso-style-noshow:yes; mso-style-parent:""; mso-padding-alt:0in 5.4pt 0in 5.4pt; mso-para-margin:0in; mso-para-margin-bottom:.0001pt; mso-pagination:widow-orphan; font-size:10.0pt; font-family:"Times New Roman"; mso-ansi-language:#0400; mso-fareast-language:#0400; mso-bidi-language:#0400;} </style> <![endif]--><!--[if gte mso 9]><xml> <o:shapedefaults v:ext="edit" spidmax="5122"/> </xml><![endif]--><!--[if gte mso 9]><xml> <o:shapelayout v:ext="edit"> <o:idmap v:ext="edit" data="1"/> </o:shapelayout></xml><![endif]-->
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+<table class="MsoNormalTable" style="width: 675pt;" border="0" cellpadding="0" cellspacing="0" width="900">
+  <tbody>
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+        <tbody>
+          <tr>
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+            <p class="MsoNormal"><span style="font-size: 8pt; font-family: Arial; color: blue;"><a href="../../../Release_Notes.html">Back to Release page</a><o:p></o:p></span></p>
+            </td>
+          </tr>
+          <tr style="">
+            <td style="padding: 1.5pt;">
+            <h1 style="margin-bottom: 18pt; text-align: center;" align="center"><span style="font-size: 20pt; font-family: Verdana; color: rgb(51, 102, 255);">Release
+Notes for STM32469I_Discovery Board Drivers</span><span style="font-size: 20pt; font-family: Verdana;"><o:p></o:p></span></h1>
+            <p class="MsoNormal" style="text-align: center;" align="center"><span style="font-size: 10pt; font-family: Arial; color: black;">Copyright
+2017 STMicroelectronics</span><span style="color: black;"><u1:p></u1:p><o:p></o:p></span></p>
+            <p class="MsoNormal" style="text-align: center;" align="center"><span style="font-size: 10pt; font-family: Arial; color: black;"><img alt="" id="_x0000_i1025" src="_htmresc/st_logo.png" style="border: 0px solid ; width: 86px; height: 65px;"></span><span style="font-size: 10pt;"><o:p></o:p></span></p>
+            </td>
+          </tr>
+        </tbody>
+      </table>
+      <p class="MsoNormal"><span style="font-family: Arial; display: none;"><o:p>&nbsp;</o:p></span></p>
+      <table class="MsoNormalTable" style="width: 675pt;" border="0" cellpadding="0" width="900">
+        <tbody>
+          <tr style="">
+            <td style="padding: 0cm;" valign="top"><span style="font-family: &quot;Times New Roman&quot;;"></span><p class="MsoListParagraph" style="text-align: left;"><span style="font-family: &quot;Arial&quot;,sans-serif; font-size: 11pt;">The
+BSP (Board Specific Package) drivers are parts of the STM32Cube package
+based on the HAL drivers and provide a set of high level APIs relative
+to the hardware components and features in the evaluation boards,
+discovery kits and nucleo boards coming with the STM32Cube package for
+a given STM32 serie.</span></p><p class="MsoListParagraph" style="text-align: left;"><span style="font-family: &quot;Arial&quot;,sans-serif; font-size: 11pt;">The
+BSP drivers allow a quick access to the boards&#8217; services using high
+level APIs and without any specific configuration as the link with the
+HAL and the external components is done in intrinsic within the
+drivers. <br></span></p><p class="MsoListParagraph" style="text-align: left;"><span style="font-family: &quot;Arial&quot;,sans-serif; font-size: 11pt;">From
+project settings points of view, user has only to add the necessary
+driver&#8217;s files in the workspace and call the needed functions from
+examples. However some low level configuration functions are weak and
+can be overridden by the applications if user wants to change some BSP
+drivers default behavior.</span></p><h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial;"><span style="font-size: 12pt; color: white;">Update
+History</span></h2>
+            
+            <h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; margin-right: 500pt; width: 215px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V2.1.1 / 11-February-2022 <o:p></o:p></span></h3>
+
+            <b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
+Changes<br></span></u></b>
+            <ul style="list-style-type: square;">
+<li><span style="font-size: 10pt; font-family: Verdana;">All source files: update disclaimer to add reference to the new license agreement</span></li>
+            </ul>
+<h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; margin-right: 500pt; width: 215px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V2.1.0 / 11-December-2020 <o:p></o:p></span></h3>
+            <b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
+Changes<br></span></u></b><ul style="list-style-type: square;"><li><span style="font-size: 10pt; font-family: Verdana;">Update Drivers to support new LCD controller <span style="font-weight: bold;">NT35510</span>.</span></li></ul><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; margin-right: 500pt; width: 215px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V2.0.1 / 21-September-2017 <o:p></o:p></span></h3>
+            <p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
+Changes<o:p></o:p></span></u></b></p>
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+            <span style="font-size: 10pt; font-family: Verdana;"></span>
+
+
+            
+            <span style="font-size: 10pt; font-family: Verdana;"></span>
+
+
+            
+            <span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;"></span>
+
+
+
+
+
+
+            
+            
+            <span style="font-size: 10pt; font-family: Verdana;"></span>
+
+
+
+
+
+
+            
+            
+            <span style="font-size: 10pt; font-family: Verdana;"></span>
+
+
+
+
+
+            
+            
+            <span style="font-size: 10pt; font-family: Verdana;"></span>
+
+
+
+
+            
+            
+            <span style="font-size: 10pt; font-family: Verdana;"></span>
+
+            <span style="font-size: 10pt; font-family: Verdana;"></span>
+            
+            
+            <ul style="list-style-type: square;"><li><span style="font-size: 10pt; font-family: Verdana;">Remove date &amp; version</span></li><li><span style="font-family: Verdana; font-size: 10pt;">Add general description of BSP drivers</span></li><li><span style="font-size: 10pt; font-family: Verdana;">stm32469i_discovery_audio.c/.h:</span></li><ul><li><span style="font-size: 10pt; font-family: Verdana;">Aligned with PDM&nbsp;library v3.0.0&nbsp;</span></li></ul><li><span style="font-size: 10pt; font-family: Verdana;">stm32469i_discovery_lcd.c:</span></li><ul><li><span style="font-size: 10pt; font-family: Verdana;">Update &nbsp;BSP_LCD_DrawBitmap() API to fix functional misbehaviour with SW4STM32 Toolchain</span></li></ul><li><span style="font-family: Verdana; font-size: 10pt;"><span style="font-style: italic; font-weight: bold; text-decoration: underline;">Notes:</span> <br>
+  </span></li><ul><li><span style="font-family: Verdana; font-size: 10pt;">This version must be used with v3.0.0 of PDM library</span></li></ul></ul><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; margin-right: 500pt; width: 205px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V2.0.0 / 27-January-2017 <o:p></o:p></span></h3>
+
+
+            <p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
+Changes<o:p></o:p></span></u></b></p>
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+            <span style="font-size: 10pt; font-family: Verdana;"></span>
+
+
+            
+            <span style="font-size: 10pt; font-family: Verdana;"></span>
+
+
+            
+            <span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;"></span>
+
+
+
+
+
+
+            
+            
+            <span style="font-size: 10pt; font-family: Verdana;"></span>
+
+
+
+
+
+
+            
+            
+            <span style="font-size: 10pt; font-family: Verdana;"></span>
+
+
+
+
+
+            
+            
+            <span style="font-size: 10pt; font-family: Verdana;"></span>
+
+
+
+
+            
+            
+            <span style="font-size: 10pt; font-family: Verdana;"></span>
+
+            <span style="font-size: 10pt; font-family: Verdana;"></span>
+            
+            
+            <ul style="list-style-type: square;">
+<li><span style="font-size: 10pt; font-family: Verdana;">stm32469i_discovery_sd.c/.h:</span></li><ul><li><span style="font-size: 10pt; font-family: Verdana;">Update BSP SD APIs </span><span style="font-family: Verdana; font-size: 10pt;">following new HAL SD drivers implementation</span></li><li><span style="font-size: 10pt; font-family: Verdana;">Fix BlockSize to 512 bytes<br>
+</span></li></ul><li><span style="font-size: 10pt; font-family: Verdana;">stm32469i_</span><span style="font-size: 10pt; font-family: Verdana;">discovery</span><span style="font-size: 10pt; font-family: Verdana;">_ts.c/.h:</span></li><ul><li><span style="font-size: 10pt; font-family: Verdana;">Support of FT6336G Touch Screen</span></li></ul><li><span style="font-size: 10pt; font-family: Verdana;">stm32469i_</span><span style="font-size: 10pt; font-family: Verdana;">discovery</span><span style="font-size: 10pt; font-family: Verdana;">_qspi.c/.h:</span></li><ul><li><span style="font-size: 10pt; font-family: Verdana;">QSPI write operation improvement</span></li><li><span style="font-size: 10pt; font-family: Verdana;">Update CS High Time</span></li></ul><li><span style="font-size: 10pt; font-family: Verdana;">stm32469i_</span><span style="font-size: 10pt; font-family: Verdana;">discovery</span><span style="font-size: 10pt; font-family: Verdana;">_sdram.c:</span></li><ul><li><span style="font-size: 10pt; font-family: Verdana;">Update SDRAM RowBitsNumbers and ColumnBitsNumber values to address all 16MB memory size</span><span style="font-size: 10.5pt; font-family: &quot;Helvetica&quot;,sans-serif; color: rgb(51, 51, 51);">.</span></li></ul>
+              <li><span style="font-size: 10pt; font-family: Verdana;">stm32469i_</span><span style="font-size: 10pt; font-family: Verdana;">discovery</span><span style="font-size: 10pt; font-family: Verdana;">_lcd.c:</span></li>
+              <ul>
+<li><span style="font-size: 10pt; font-family: Verdana;">Update BSP_LCD_ReadPixel for ARGB8888 and RGB888 formats</span></li>
+              </ul>
+              <li><span style="font-size: 10pt; font-family: Verdana;">stm32469i_</span><span style="font-size: 10pt; font-family: Verdana;">discovery</span><span style="font-size: 10pt; font-family: Verdana;">_audio.c:</span></li>
+              <ul>
+<li><span style="font-size: 10pt; font-family: Verdana;">Remove static CODEC_Reset API<br>
+</span></li>
+              </ul>
+
+<li><span style="font-family: Verdana; font-size: 10pt;"><span style="font-style: italic; font-weight: bold; text-decoration: underline;">Notes:</span> <br>
+  </span></li><ul><li><span style="font-family: Verdana; font-size: 10pt;">These</span><span style="font-family: Verdana; font-size: 10pt;"> BSP drivers</span><span style="font-family: Verdana; font-size: 10pt;"> break the compatibility with previous versions.</span></li></ul><ul><li><span style="font-family: Verdana; font-size: 10pt;">If FatFs is required, </span><span style="font-family: Verdana; font-size: 10pt; font-style: italic;">"FatFS R0.11<span class="Apple-converted-space"> </span> </span><span style="font-family: Verdana; font-size: 10pt;"><span style="font-style: italic;">ST modified 20161223"</span><span style="color: red;"><span style="color: black;"></span></span></span><span style="font-family: Verdana; font-size: 10pt;"> must be used with </span><span style="font-family: Verdana; font-size: 10pt;">this version of BSP drivers.</span></li></ul>
+            </ul>
+
+            <h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; margin-right: 500pt; width: 205px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.0.3 / 04-August-2016 <o:p></o:p></span></h3>
+
+
+
+            
+            <p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
+Changes</span></u></b><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;"><o:p></o:p></span></u></b></p>
+
+            
+            <ul style="margin-top: 0cm;" type="square">
+              <li><span style="font-size: 10pt; font-family: Verdana;">stm32469i_discovery_lcd.c/.h:<br></span></li>
+              <ul>
+<li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman'; color: black;"><span style="font-size: 10pt; font-family: Verdana;">Update DSI initialization<br>
+</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman'; color: black;"><span style="font-size: 10pt; font-family: Verdana;">Update LTDC clock value</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman'; color: black;"><span style="font-size: 10pt; font-family: Verdana;">Update LCD_DSI_PIXEL_DATA_FMT_RBG888 and LCD_DSI_PIXEL_DATA_FMT_RBG565 values</span></li>
+              </ul>
+            </ul><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; margin-right: 500pt; width: 205px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.0.2 /
+13-January-2016 <o:p></o:p></span></h3>
+
+            <p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
+Changes</span></u></b><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;"><o:p></o:p></span></u></b></p>
+            <ul style="margin-top: 0cm;" type="square">
+              <li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman'; color: black;"><span style="color: rgb(0, 0, 0); font-family: Verdana,sans-serif; font-size: 13.3333px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 1; word-spacing: 0px; display: inline ! important; float: none;">General&nbsp;updates
+to fix&nbsp;doxygen errors</span><span style="font-size: 10pt; font-family: Verdana;"></span></li>
+              <li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman'; color: black;"><span style="font-size: 10pt; font-family: Verdana;">Add
+STM32F469I-Discovery_BSP_User_Manual.chm file</span></li>
+              <li><span style="font-size: 10pt; font-family: Verdana;">stm32469i_discovery_audio.c</span></li>
+              <ul>
+                <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Alignement with
+STM32F4xx_HAL_Driver V1.4.4</span><span style="font-size: 10pt; font-family: Verdana;">&nbsp;</span></li>
+              </ul>
+              <li><span style="font-size: 10pt; font-family: Verdana;">stm32469i_discovery_qspi.c</span></li>
+              <ul>
+                <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Desactivate Timeout in
+memory mapped mode</span></li>
+                <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Rename
+BSP_QSPI_MemoryMappedMode() API to BSP_QSPI_EnableMemoryMappedMode()
+API&nbsp;</span></li>
+              </ul>
+              <li><span style="font-size: 10pt; font-family: Verdana;">stm32469i_discovery_lcd.c</span></li>
+              <ul>
+                <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">BSP_LCD_InitEx() API
+updated to remove use of intermediate variable Clockratio and improve
+calculation granularity</span><br>
+                  <span style="font-size: 10pt; font-family: Arial; color: white;"></span></li>
+              </ul>
+            </ul>
+            <h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; margin-right: 500pt; width: 220px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.0.1 /
+29-September-2015</span></h3>
+            <p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
+Changes<o:p></o:p></span></u></b></p>
+            <ul style="margin-top: 0cm;" type="square">
+              <li class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">stm32469i_discovery_lcd.c
+update:</span></li>
+              <ul>
+                <li class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">Add delay
+within&nbsp;BSP_LCD_Reset() function </span></li>
+              </ul>
+            </ul>
+            <h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; margin-right: 500pt; width: 200px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.0.0 /
+14-Augusty-2015</span></h3><p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
+Changes<o:p></o:p></span></u></b></p>
+            <ul style="margin-top: 0cm;" type="square">
+              <li class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">First official Release </span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold; font-style: italic;"></span></span><span style="font-size: 10pt; font-family: Verdana;">for&nbsp;<span style="font-weight: bold; font-style: italic;">STM32469I_Discovery</span>
+board drivers.</span></li>
+            </ul><div style="text-align: justify;"><span style="font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"></span></div>
+            <span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;; color: black;"></span>
+            <b><span style="font-size: 10pt; font-family: Verdana; color: black;"></span></b>
+            <div class="MsoNormal" style="text-align: center;" align="center"><span style="color: black;">
+            <hr align="center" size="2" width="100%"></span></div>
+            <p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt; text-align: center;" align="center"><span style="font-size: 10pt; font-family: Verdana; color: black;">For
+complete documentation on </span><span style="font-size: 10pt; font-family: Verdana;">STM32<span style="color: black;">&nbsp;Microcontrollers
+visit </span><u><span style="color: blue;"><a href="http://www.st.com/internet/mcu/class/1734.jsp" target="_blank">www.st.com/STM32</a></span></u></span><span style="font-size: 10pt; font-family: Verdana;"><a target="_blank" href="http://www.st.com/internet/mcu/family/141.jsp"><u><span style="color: blue;"></span></u></a></span><span style="font-size: 10pt; font-family: Verdana;"><u><span style="color: blue;"></span></u></span><span style="color: black;"><o:p></o:p></span></p>
+            </td>
+          </tr>
+        </tbody>
+      </table>
+      <p class="MsoNormal"><span style="font-size: 10pt;"><o:p></o:p></span></p>
+      </td>
+    </tr>
+  </tbody>
+</table>
+</div>
+<p class="MsoNormal"><o:p>&nbsp;</o:p></p>
+</div>
+
+</body></html>
\ No newline at end of file
diff --git a/Drivers/BSP/STM32469I-Discovery/STM32469I-Discovery_BSP_User_Manual.chm b/Drivers/BSP/STM32469I-Discovery/STM32469I-Discovery_BSP_User_Manual.chm
new file mode 100644
index 0000000..1805894
Binary files /dev/null and b/Drivers/BSP/STM32469I-Discovery/STM32469I-Discovery_BSP_User_Manual.chm differ
diff --git a/Drivers/BSP/STM32469I-Discovery/_htmresc/mini-st.css b/Drivers/BSP/STM32469I-Discovery/_htmresc/mini-st.css
new file mode 100644
index 0000000..9b2d0a9
--- /dev/null
+++ b/Drivers/BSP/STM32469I-Discovery/_htmresc/mini-st.css
@@ -0,0 +1,1700 @@
+@charset "UTF-8";
+/*
+  Flavor name: Default (mini-default)
+  Author: Angelos Chalaris (chalarangelo@gmail.com)
+  Maintainers: Angelos Chalaris
+  mini.css version: v3.0.0-alpha.3
+*/
+/*
+  Browsers resets and base typography.
+*/
+/* Core module CSS variable definitions */
+:root {
+  --fore-color: #111;
+  --secondary-fore-color: #444;
+  --back-color: #f8f8f8;
+  --secondary-back-color: #f0f0f0;
+  --blockquote-color: #f57c00;
+  --pre-color: #1565c0;
+  --border-color: #aaa;
+  --secondary-border-color: #ddd;
+  --heading-ratio: 1.19;
+  --universal-margin: 0.5rem;
+  --universal-padding: 0.125rem;
+  --universal-border-radius: 0.125rem;
+  --a-link-color: #0277bd;
+  --a-visited-color: #01579b; }
+
+html {
+  font-size: 14px; }
+
+a, b, del, em, i, ins, q, span, strong, u {
+  font-size: 1em; }
+
+html, * {
+  font-family: -apple-system, BlinkMacSystemFont, "Segoe UI", Roboto, Ubuntu, "Helvetica Neue", Helvetica, sans-serif;
+  line-height: 1.4;
+  -webkit-text-size-adjust: 100%; }
+
+* {
+  font-size: 1rem; }
+
+body {
+  margin: 0;
+  color: var(--fore-color);
+  background: var(--back-color); }
+
+details {
+  display: block; }
+
+summary {
+  display: list-item; }
+
+abbr[title] {
+  border-bottom: none;
+  text-decoration: underline dotted; }
+
+input {
+  overflow: visible; }
+
+img {
+  max-width: 100%;
+  height: auto; }
+
+h1, h2, h3, h4, h5, h6 {
+  line-height: 1.2;
+  margin: calc(1.5 * var(--universal-margin)) var(--universal-margin);
+  font-weight: 500; }
+  h1 small, h2 small, h3 small, h4 small, h5 small, h6 small {
+    color: var(--secondary-fore-color);
+    display: block;
+    margin-top: -0.25rem; }
+
+h1 {
+  font-size: calc(1rem * var(--heading-ratio) * var(--heading-ratio) * var(--heading-ratio)); }
+
+h2 {
+  font-size: calc(1rem * var(--heading-ratio) * var(--heading-ratio); );
+  background: var(--mark-back-color);
+  font-weight: 600;
+  padding: 0.1em 0.5em 0.2em 0.5em;
+  color: var(--mark-fore-color); }
+
+h3 {
+  font-size: calc(1rem * var(--heading-ratio));
+  padding-left: calc(2 * var(--universal-margin)); 
+  /* background: var(--border-color); */
+    }
+
+h4 {
+  font-size: 1rem;);
+  padding-left: calc(4 * var(--universal-margin));  }
+
+h5 {
+  font-size: 1rem; }
+
+h6 {
+  font-size: calc(1rem / var(--heading-ratio)); }
+
+p {
+  margin: var(--universal-margin); }
+
+ol, ul {
+  margin: var(--universal-margin);
+  padding-left: calc(6 * var(--universal-margin)); }
+
+b, strong {
+  font-weight: 700; }
+
+hr {
+  box-sizing: content-box;
+  border: 0;
+  line-height: 1.25em;
+  margin: var(--universal-margin);
+  height: 0.0625rem;
+  background: linear-gradient(to right, transparent, var(--border-color) 20%, var(--border-color) 80%, transparent); }
+
+blockquote {
+  display: block;
+  position: relative;
+  font-style: italic;
+  color: var(--secondary-fore-color);
+  margin: var(--universal-margin);
+  padding: calc(3 * var(--universal-padding));
+  border: 0.0625rem solid var(--secondary-border-color);
+  border-left: 0.375rem solid var(--blockquote-color);
+  border-radius: 0 var(--universal-border-radius) var(--universal-border-radius) 0; }
+  blockquote:before {
+    position: absolute;
+    top: calc(0rem - var(--universal-padding));
+    left: 0;
+    font-family: sans-serif;
+    font-size: 3rem;
+    font-weight: 700;
+    content: "\201c";
+    color: var(--blockquote-color); }
+  blockquote[cite]:after {
+    font-style: normal;
+    font-size: 0.75em;
+    font-weight: 700;
+    content: "\a—  " attr(cite);
+    white-space: pre; }
+
+code, kbd, pre, samp {
+  font-family: Menlo, Consolas, monospace;
+  font-size: 0.85em; }
+
+code {
+  background: var(--secondary-back-color);
+  border-radius: var(--universal-border-radius);
+  padding: calc(var(--universal-padding) / 4) calc(var(--universal-padding) / 2); }
+
+kbd {
+  background: var(--fore-color);
+  color: var(--back-color);
+  border-radius: var(--universal-border-radius);
+  padding: calc(var(--universal-padding) / 4) calc(var(--universal-padding) / 2); }
+
+pre {
+  overflow: auto;
+  background: var(--secondary-back-color);
+  padding: calc(1.5 * var(--universal-padding));
+  margin: var(--universal-margin);
+  border: 0.0625rem solid var(--secondary-border-color);
+  border-left: 0.25rem solid var(--pre-color);
+  border-radius: 0 var(--universal-border-radius) var(--universal-border-radius) 0; }
+
+sup, sub, code, kbd {
+  line-height: 0;
+  position: relative;
+  vertical-align: baseline; }
+
+small, sup, sub, figcaption {
+  font-size: 0.75em; }
+
+sup {
+  top: -0.5em; }
+
+sub {
+  bottom: -0.25em; }
+
+figure {
+  margin: var(--universal-margin); }
+
+figcaption {
+  color: var(--secondary-fore-color); }
+
+a {
+  text-decoration: none; }
+  a:link {
+    color: var(--a-link-color); }
+  a:visited {
+    color: var(--a-visited-color); }
+  a:hover, a:focus {
+    text-decoration: underline; }
+
+/*
+  Definitions for the grid system, cards and containers.
+*/
+.container {
+  margin: 0 auto;
+  padding: 0 calc(1.5 * var(--universal-padding)); }
+
+.row {
+  box-sizing: border-box;
+  display: flex;
+  flex: 0 1 auto;
+  flex-flow: row wrap; }
+
+.col-sm,
+[class^='col-sm-'],
+[class^='col-sm-offset-'],
+.row[class*='cols-sm-'] > * {
+  box-sizing: border-box;
+  flex: 0 0 auto;
+  padding: 0 calc(var(--universal-padding) / 2); }
+
+.col-sm,
+.row.cols-sm > * {
+  max-width: 100%;
+  flex-grow: 1;
+  flex-basis: 0; }
+
+.col-sm-1,
+.row.cols-sm-1 > * {
+  max-width: 8.3333333333%;
+  flex-basis: 8.3333333333%; }
+
+.col-sm-offset-0 {
+  margin-left: 0; }
+
+.col-sm-2,
+.row.cols-sm-2 > * {
+  max-width: 16.6666666667%;
+  flex-basis: 16.6666666667%; }
+
+.col-sm-offset-1 {
+  margin-left: 8.3333333333%; }
+
+.col-sm-3,
+.row.cols-sm-3 > * {
+  max-width: 25%;
+  flex-basis: 25%; }
+
+.col-sm-offset-2 {
+  margin-left: 16.6666666667%; }
+
+.col-sm-4,
+.row.cols-sm-4 > * {
+  max-width: 33.3333333333%;
+  flex-basis: 33.3333333333%; }
+
+.col-sm-offset-3 {
+  margin-left: 25%; }
+
+.col-sm-5,
+.row.cols-sm-5 > * {
+  max-width: 41.6666666667%;
+  flex-basis: 41.6666666667%; }
+
+.col-sm-offset-4 {
+  margin-left: 33.3333333333%; }
+
+.col-sm-6,
+.row.cols-sm-6 > * {
+  max-width: 50%;
+  flex-basis: 50%; }
+
+.col-sm-offset-5 {
+  margin-left: 41.6666666667%; }
+
+.col-sm-7,
+.row.cols-sm-7 > * {
+  max-width: 58.3333333333%;
+  flex-basis: 58.3333333333%; }
+
+.col-sm-offset-6 {
+  margin-left: 50%; }
+
+.col-sm-8,
+.row.cols-sm-8 > * {
+  max-width: 66.6666666667%;
+  flex-basis: 66.6666666667%; }
+
+.col-sm-offset-7 {
+  margin-left: 58.3333333333%; }
+
+.col-sm-9,
+.row.cols-sm-9 > * {
+  max-width: 75%;
+  flex-basis: 75%; }
+
+.col-sm-offset-8 {
+  margin-left: 66.6666666667%; }
+
+.col-sm-10,
+.row.cols-sm-10 > * {
+  max-width: 83.3333333333%;
+  flex-basis: 83.3333333333%; }
+
+.col-sm-offset-9 {
+  margin-left: 75%; }
+
+.col-sm-11,
+.row.cols-sm-11 > * {
+  max-width: 91.6666666667%;
+  flex-basis: 91.6666666667%; }
+
+.col-sm-offset-10 {
+  margin-left: 83.3333333333%; }
+
+.col-sm-12,
+.row.cols-sm-12 > * {
+  max-width: 100%;
+  flex-basis: 100%; }
+
+.col-sm-offset-11 {
+  margin-left: 91.6666666667%; }
+
+.col-sm-normal {
+  order: initial; }
+
+.col-sm-first {
+  order: -999; }
+
+.col-sm-last {
+  order: 999; }
+
+@media screen and (min-width: 500px) {
+  .col-md,
+  [class^='col-md-'],
+  [class^='col-md-offset-'],
+  .row[class*='cols-md-'] > * {
+    box-sizing: border-box;
+    flex: 0 0 auto;
+    padding: 0 calc(var(--universal-padding) / 2); }
+
+  .col-md,
+  .row.cols-md > * {
+    max-width: 100%;
+    flex-grow: 1;
+    flex-basis: 0; }
+
+  .col-md-1,
+  .row.cols-md-1 > * {
+    max-width: 8.3333333333%;
+    flex-basis: 8.3333333333%; }
+
+  .col-md-offset-0 {
+    margin-left: 0; }
+
+  .col-md-2,
+  .row.cols-md-2 > * {
+    max-width: 16.6666666667%;
+    flex-basis: 16.6666666667%; }
+
+  .col-md-offset-1 {
+    margin-left: 8.3333333333%; }
+
+  .col-md-3,
+  .row.cols-md-3 > * {
+    max-width: 25%;
+    flex-basis: 25%; }
+
+  .col-md-offset-2 {
+    margin-left: 16.6666666667%; }
+
+  .col-md-4,
+  .row.cols-md-4 > * {
+    max-width: 33.3333333333%;
+    flex-basis: 33.3333333333%; }
+
+  .col-md-offset-3 {
+    margin-left: 25%; }
+
+  .col-md-5,
+  .row.cols-md-5 > * {
+    max-width: 41.6666666667%;
+    flex-basis: 41.6666666667%; }
+
+  .col-md-offset-4 {
+    margin-left: 33.3333333333%; }
+
+  .col-md-6,
+  .row.cols-md-6 > * {
+    max-width: 50%;
+    flex-basis: 50%; }
+
+  .col-md-offset-5 {
+    margin-left: 41.6666666667%; }
+
+  .col-md-7,
+  .row.cols-md-7 > * {
+    max-width: 58.3333333333%;
+    flex-basis: 58.3333333333%; }
+
+  .col-md-offset-6 {
+    margin-left: 50%; }
+
+  .col-md-8,
+  .row.cols-md-8 > * {
+    max-width: 66.6666666667%;
+    flex-basis: 66.6666666667%; }
+
+  .col-md-offset-7 {
+    margin-left: 58.3333333333%; }
+
+  .col-md-9,
+  .row.cols-md-9 > * {
+    max-width: 75%;
+    flex-basis: 75%; }
+
+  .col-md-offset-8 {
+    margin-left: 66.6666666667%; }
+
+  .col-md-10,
+  .row.cols-md-10 > * {
+    max-width: 83.3333333333%;
+    flex-basis: 83.3333333333%; }
+
+  .col-md-offset-9 {
+    margin-left: 75%; }
+
+  .col-md-11,
+  .row.cols-md-11 > * {
+    max-width: 91.6666666667%;
+    flex-basis: 91.6666666667%; }
+
+  .col-md-offset-10 {
+    margin-left: 83.3333333333%; }
+
+  .col-md-12,
+  .row.cols-md-12 > * {
+    max-width: 100%;
+    flex-basis: 100%; }
+
+  .col-md-offset-11 {
+    margin-left: 91.6666666667%; }
+
+  .col-md-normal {
+    order: initial; }
+
+  .col-md-first {
+    order: -999; }
+
+  .col-md-last {
+    order: 999; } }
+@media screen and (min-width: 1280px) {
+  .col-lg,
+  [class^='col-lg-'],
+  [class^='col-lg-offset-'],
+  .row[class*='cols-lg-'] > * {
+    box-sizing: border-box;
+    flex: 0 0 auto;
+    padding: 0 calc(var(--universal-padding) / 2); }
+
+  .col-lg,
+  .row.cols-lg > * {
+    max-width: 100%;
+    flex-grow: 1;
+    flex-basis: 0; }
+
+  .col-lg-1,
+  .row.cols-lg-1 > * {
+    max-width: 8.3333333333%;
+    flex-basis: 8.3333333333%; }
+
+  .col-lg-offset-0 {
+    margin-left: 0; }
+
+  .col-lg-2,
+  .row.cols-lg-2 > * {
+    max-width: 16.6666666667%;
+    flex-basis: 16.6666666667%; }
+
+  .col-lg-offset-1 {
+    margin-left: 8.3333333333%; }
+
+  .col-lg-3,
+  .row.cols-lg-3 > * {
+    max-width: 25%;
+    flex-basis: 25%; }
+
+  .col-lg-offset-2 {
+    margin-left: 16.6666666667%; }
+
+  .col-lg-4,
+  .row.cols-lg-4 > * {
+    max-width: 33.3333333333%;
+    flex-basis: 33.3333333333%; }
+
+  .col-lg-offset-3 {
+    margin-left: 25%; }
+
+  .col-lg-5,
+  .row.cols-lg-5 > * {
+    max-width: 41.6666666667%;
+    flex-basis: 41.6666666667%; }
+
+  .col-lg-offset-4 {
+    margin-left: 33.3333333333%; }
+
+  .col-lg-6,
+  .row.cols-lg-6 > * {
+    max-width: 50%;
+    flex-basis: 50%; }
+
+  .col-lg-offset-5 {
+    margin-left: 41.6666666667%; }
+
+  .col-lg-7,
+  .row.cols-lg-7 > * {
+    max-width: 58.3333333333%;
+    flex-basis: 58.3333333333%; }
+
+  .col-lg-offset-6 {
+    margin-left: 50%; }
+
+  .col-lg-8,
+  .row.cols-lg-8 > * {
+    max-width: 66.6666666667%;
+    flex-basis: 66.6666666667%; }
+
+  .col-lg-offset-7 {
+    margin-left: 58.3333333333%; }
+
+  .col-lg-9,
+  .row.cols-lg-9 > * {
+    max-width: 75%;
+    flex-basis: 75%; }
+
+  .col-lg-offset-8 {
+    margin-left: 66.6666666667%; }
+
+  .col-lg-10,
+  .row.cols-lg-10 > * {
+    max-width: 83.3333333333%;
+    flex-basis: 83.3333333333%; }
+
+  .col-lg-offset-9 {
+    margin-left: 75%; }
+
+  .col-lg-11,
+  .row.cols-lg-11 > * {
+    max-width: 91.6666666667%;
+    flex-basis: 91.6666666667%; }
+
+  .col-lg-offset-10 {
+    margin-left: 83.3333333333%; }
+
+  .col-lg-12,
+  .row.cols-lg-12 > * {
+    max-width: 100%;
+    flex-basis: 100%; }
+
+  .col-lg-offset-11 {
+    margin-left: 91.6666666667%; }
+
+  .col-lg-normal {
+    order: initial; }
+
+  .col-lg-first {
+    order: -999; }
+
+  .col-lg-last {
+    order: 999; } }
+/* Card component CSS variable definitions */
+:root {
+  --card-back-color: #f8f8f8;
+  --card-fore-color: #111;
+  --card-border-color: #ddd; }
+
+.card {
+  display: flex;
+  flex-direction: column;
+  justify-content: space-between;
+  align-self: center;
+  position: relative;
+  width: 100%;
+  background: var(--card-back-color);
+  color: var(--card-fore-color);
+  border: 0.0625rem solid var(--card-border-color);
+  border-radius: var(--universal-border-radius);
+  margin: var(--universal-margin);
+  overflow: hidden; }
+  @media screen and (min-width: 320px) {
+    .card {
+      max-width: 320px; } }
+  .card > .sectione {
+    background: var(--card-back-color);
+    color: var(--card-fore-color);
+    box-sizing: border-box;
+    margin: 0;
+    border: 0;
+    border-radius: 0;
+    border-bottom: 0.0625rem solid var(--card-border-color);
+    padding: var(--universal-padding);
+    width: 100%; }
+    .card > .sectione.media {
+      height: 200px;
+      padding: 0;
+      -o-object-fit: cover;
+      object-fit: cover; }
+  .card > .sectione:last-child {
+    border-bottom: 0; }
+
+/*
+  Custom elements for card elements.
+*/
+@media screen and (min-width: 240px) {
+  .card.small {
+    max-width: 240px; } }
+@media screen and (min-width: 480px) {
+  .card.large {
+    max-width: 480px; } }
+.card.fluid {
+  max-width: 100%;
+  width: auto; }
+
+.card.warning {
+/*  --card-back-color: #ffca28; */
+  --card-back-color: #e5b8b7;
+  --card-border-color: #e8b825; }
+
+.card.error {
+  --card-back-color: #b71c1c;
+  --card-fore-color: #f8f8f8;
+  --card-border-color: #a71a1a; }
+
+.card > .sectione.dark {
+  --card-back-color: #e0e0e0; }
+
+.card > .sectione.double-padded {
+  padding: calc(1.5 * var(--universal-padding)); }
+
+/*
+  Definitions for forms and input elements.
+*/
+/* Input_control module CSS variable definitions */
+:root {
+  --form-back-color: #f0f0f0;
+  --form-fore-color: #111;
+  --form-border-color: #ddd;
+  --input-back-color: #f8f8f8;
+  --input-fore-color: #111;
+  --input-border-color: #ddd;
+  --input-focus-color: #0288d1;
+  --input-invalid-color: #d32f2f;
+  --button-back-color: #e2e2e2;
+  --button-hover-back-color: #dcdcdc;
+  --button-fore-color: #212121;
+  --button-border-color: transparent;
+  --button-hover-border-color: transparent;
+  --button-group-border-color: rgba(124, 124, 124, 0.54); }
+
+form {
+  background: var(--form-back-color);
+  color: var(--form-fore-color);
+  border: 0.0625rem solid var(--form-border-color);
+  border-radius: var(--universal-border-radius);
+  margin: var(--universal-margin);
+  padding: calc(2 * var(--universal-padding)) var(--universal-padding); }
+
+fieldset {
+  border: 0.0625rem solid var(--form-border-color);
+  border-radius: var(--universal-border-radius);
+  margin: calc(var(--universal-margin) / 4);
+  padding: var(--universal-padding); }
+
+legend {
+  box-sizing: border-box;
+  display: table;
+  max-width: 100%;
+  white-space: normal;
+  font-weight: 700;
+  padding: calc(var(--universal-padding) / 2); }
+
+label {
+  padding: calc(var(--universal-padding) / 2) var(--universal-padding); }
+
+.input-group {
+  display: inline-block; }
+  .input-group.fluid {
+    display: flex;
+    align-items: center;
+    justify-content: center; }
+    .input-group.fluid > input {
+      max-width: 100%;
+      flex-grow: 1;
+      flex-basis: 0px; }
+    @media screen and (max-width: 499px) {
+      .input-group.fluid {
+        align-items: stretch;
+        flex-direction: column; } }
+  .input-group.vertical {
+    display: flex;
+    align-items: stretch;
+    flex-direction: column; }
+    .input-group.vertical > input {
+      max-width: 100%;
+      flex-grow: 1;
+      flex-basis: 0px; }
+
+[type="number"]::-webkit-inner-spin-button, [type="number"]::-webkit-outer-spin-button {
+  height: auto; }
+
+[type="search"] {
+  -webkit-appearance: textfield;
+  outline-offset: -2px; }
+
+[type="search"]::-webkit-search-cancel-button,
+[type="search"]::-webkit-search-decoration {
+  -webkit-appearance: none; }
+
+input:not([type]), [type="text"], [type="email"], [type="number"], [type="search"],
+[type="password"], [type="url"], [type="tel"], [type="checkbox"], [type="radio"], textarea, select {
+  box-sizing: border-box;
+  background: var(--input-back-color);
+  color: var(--input-fore-color);
+  border: 0.0625rem solid var(--input-border-color);
+  border-radius: var(--universal-border-radius);
+  margin: calc(var(--universal-margin) / 2);
+  padding: var(--universal-padding) calc(1.5 * var(--universal-padding)); }
+
+input:not([type="button"]):not([type="submit"]):not([type="reset"]):hover, input:not([type="button"]):not([type="submit"]):not([type="reset"]):focus, textarea:hover, textarea:focus, select:hover, select:focus {
+  border-color: var(--input-focus-color);
+  box-shadow: none; }
+input:not([type="button"]):not([type="submit"]):not([type="reset"]):invalid, input:not([type="button"]):not([type="submit"]):not([type="reset"]):focus:invalid, textarea:invalid, textarea:focus:invalid, select:invalid, select:focus:invalid {
+  border-color: var(--input-invalid-color);
+  box-shadow: none; }
+input:not([type="button"]):not([type="submit"]):not([type="reset"])[readonly], textarea[readonly], select[readonly] {
+  background: var(--secondary-back-color); }
+
+select {
+  max-width: 100%; }
+
+option {
+  overflow: hidden;
+  text-overflow: ellipsis; }
+
+[type="checkbox"], [type="radio"] {
+  -webkit-appearance: none;
+  -moz-appearance: none;
+  appearance: none;
+  position: relative;
+  height: calc(1rem + var(--universal-padding) / 2);
+  width: calc(1rem + var(--universal-padding) / 2);
+  vertical-align: text-bottom;
+  padding: 0;
+  flex-basis: calc(1rem + var(--universal-padding) / 2) !important;
+  flex-grow: 0 !important; }
+  [type="checkbox"]:checked:before, [type="radio"]:checked:before {
+    position: absolute; }
+
+[type="checkbox"]:checked:before {
+  content: '\2713';
+  font-family: sans-serif;
+  font-size: calc(1rem + var(--universal-padding) / 2);
+  top: calc(0rem - var(--universal-padding));
+  left: calc(var(--universal-padding) / 4); }
+
+[type="radio"] {
+  border-radius: 100%; }
+  [type="radio"]:checked:before {
+    border-radius: 100%;
+    content: '';
+    top: calc(0.0625rem + var(--universal-padding) / 2);
+    left: calc(0.0625rem + var(--universal-padding) / 2);
+    background: var(--input-fore-color);
+    width: 0.5rem;
+    height: 0.5rem; }
+
+:placeholder-shown {
+  color: var(--input-fore-color); }
+
+::-ms-placeholder {
+  color: var(--input-fore-color);
+  opacity: 0.54; }
+
+button::-moz-focus-inner, [type="button"]::-moz-focus-inner, [type="reset"]::-moz-focus-inner, [type="submit"]::-moz-focus-inner {
+  border-style: none;
+  padding: 0; }
+
+button, html [type="button"], [type="reset"], [type="submit"] {
+  -webkit-appearance: button; }
+
+button {
+  overflow: visible;
+  text-transform: none; }
+
+button, [type="button"], [type="submit"], [type="reset"],
+a.button, label.button, .button,
+a[role="button"], label[role="button"], [role="button"] {
+  display: inline-block;
+  background: var(--button-back-color);
+  color: var(--button-fore-color);
+  border: 0.0625rem solid var(--button-border-color);
+  border-radius: var(--universal-border-radius);
+  padding: var(--universal-padding) calc(1.5 * var(--universal-padding));
+  margin: var(--universal-margin);
+  text-decoration: none;
+  cursor: pointer;
+  transition: background 0.3s; }
+  button:hover, button:focus, [type="button"]:hover, [type="button"]:focus, [type="submit"]:hover, [type="submit"]:focus, [type="reset"]:hover, [type="reset"]:focus,
+  a.button:hover,
+  a.button:focus, label.button:hover, label.button:focus, .button:hover, .button:focus,
+  a[role="button"]:hover,
+  a[role="button"]:focus, label[role="button"]:hover, label[role="button"]:focus, [role="button"]:hover, [role="button"]:focus {
+    background: var(--button-hover-back-color);
+    border-color: var(--button-hover-border-color); }
+
+input:disabled, input[disabled], textarea:disabled, textarea[disabled], select:disabled, select[disabled], button:disabled, button[disabled], .button:disabled, .button[disabled], [role="button"]:disabled, [role="button"][disabled] {
+  cursor: not-allowed;
+  opacity: 0.75; }
+
+.button-group {
+  display: flex;
+  border: 0.0625rem solid var(--button-group-border-color);
+  border-radius: var(--universal-border-radius);
+  margin: var(--universal-margin); }
+  .button-group > button, .button-group [type="button"], .button-group > [type="submit"], .button-group > [type="reset"], .button-group > .button, .button-group > [role="button"] {
+    margin: 0;
+    max-width: 100%;
+    flex: 1 1 auto;
+    text-align: center;
+    border: 0;
+    border-radius: 0;
+    box-shadow: none; }
+  .button-group > :not(:first-child) {
+    border-left: 0.0625rem solid var(--button-group-border-color); }
+  @media screen and (max-width: 499px) {
+    .button-group {
+      flex-direction: column; }
+      .button-group > :not(:first-child) {
+        border: 0;
+        border-top: 0.0625rem solid var(--button-group-border-color); } }
+
+/*
+  Custom elements for forms and input elements.
+*/
+button.primary, [type="button"].primary, [type="submit"].primary, [type="reset"].primary, .button.primary, [role="button"].primary {
+  --button-back-color: #1976d2;
+  --button-fore-color: #f8f8f8; }
+  button.primary:hover, button.primary:focus, [type="button"].primary:hover, [type="button"].primary:focus, [type="submit"].primary:hover, [type="submit"].primary:focus, [type="reset"].primary:hover, [type="reset"].primary:focus, .button.primary:hover, .button.primary:focus, [role="button"].primary:hover, [role="button"].primary:focus {
+    --button-hover-back-color: #1565c0; }
+
+button.secondary, [type="button"].secondary, [type="submit"].secondary, [type="reset"].secondary, .button.secondary, [role="button"].secondary {
+  --button-back-color: #d32f2f;
+  --button-fore-color: #f8f8f8; }
+  button.secondary:hover, button.secondary:focus, [type="button"].secondary:hover, [type="button"].secondary:focus, [type="submit"].secondary:hover, [type="submit"].secondary:focus, [type="reset"].secondary:hover, [type="reset"].secondary:focus, .button.secondary:hover, .button.secondary:focus, [role="button"].secondary:hover, [role="button"].secondary:focus {
+    --button-hover-back-color: #c62828; }
+
+button.tertiary, [type="button"].tertiary, [type="submit"].tertiary, [type="reset"].tertiary, .button.tertiary, [role="button"].tertiary {
+  --button-back-color: #308732;
+  --button-fore-color: #f8f8f8; }
+  button.tertiary:hover, button.tertiary:focus, [type="button"].tertiary:hover, [type="button"].tertiary:focus, [type="submit"].tertiary:hover, [type="submit"].tertiary:focus, [type="reset"].tertiary:hover, [type="reset"].tertiary:focus, .button.tertiary:hover, .button.tertiary:focus, [role="button"].tertiary:hover, [role="button"].tertiary:focus {
+    --button-hover-back-color: #277529; }
+
+button.inverse, [type="button"].inverse, [type="submit"].inverse, [type="reset"].inverse, .button.inverse, [role="button"].inverse {
+  --button-back-color: #212121;
+  --button-fore-color: #f8f8f8; }
+  button.inverse:hover, button.inverse:focus, [type="button"].inverse:hover, [type="button"].inverse:focus, [type="submit"].inverse:hover, [type="submit"].inverse:focus, [type="reset"].inverse:hover, [type="reset"].inverse:focus, .button.inverse:hover, .button.inverse:focus, [role="button"].inverse:hover, [role="button"].inverse:focus {
+    --button-hover-back-color: #111; }
+
+button.small, [type="button"].small, [type="submit"].small, [type="reset"].small, .button.small, [role="button"].small {
+  padding: calc(0.5 * var(--universal-padding)) calc(0.75 * var(--universal-padding));
+  margin: var(--universal-margin); }
+
+button.large, [type="button"].large, [type="submit"].large, [type="reset"].large, .button.large, [role="button"].large {
+  padding: calc(1.5 * var(--universal-padding)) calc(2 * var(--universal-padding));
+  margin: var(--universal-margin); }
+
+/*
+  Definitions for navigation elements.
+*/
+/* Navigation module CSS variable definitions */
+:root {
+  --header-back-color: #f8f8f8;
+  --header-hover-back-color: #f0f0f0;
+  --header-fore-color: #444;
+  --header-border-color: #ddd;
+  --nav-back-color: #f8f8f8;
+  --nav-hover-back-color: #f0f0f0;
+  --nav-fore-color: #444;
+  --nav-border-color: #ddd;
+  --nav-link-color: #0277bd;
+  --footer-fore-color: #444;
+  --footer-back-color: #f8f8f8;
+  --footer-border-color: #ddd;
+  --footer-link-color: #0277bd;
+  --drawer-back-color: #f8f8f8;
+  --drawer-hover-back-color: #f0f0f0;
+  --drawer-border-color: #ddd;
+  --drawer-close-color: #444; }
+
+header {
+  height: 3.1875rem;
+  background: var(--header-back-color);
+  color: var(--header-fore-color);
+  border-bottom: 0.0625rem solid var(--header-border-color);
+  padding: calc(var(--universal-padding) / 4) 0;
+  white-space: nowrap;
+  overflow-x: auto;
+  overflow-y: hidden; }
+  header.row {
+    box-sizing: content-box; }
+  header .logo {
+    color: var(--header-fore-color);
+    font-size: 1.75rem;
+    padding: var(--universal-padding) calc(2 * var(--universal-padding));
+    text-decoration: none; }
+  header button, header [type="button"], header .button, header [role="button"] {
+    box-sizing: border-box;
+    position: relative;
+    top: calc(0rem - var(--universal-padding) / 4);
+    height: calc(3.1875rem + var(--universal-padding) / 2);
+    background: var(--header-back-color);
+    line-height: calc(3.1875rem - var(--universal-padding) * 1.5);
+    text-align: center;
+    color: var(--header-fore-color);
+    border: 0;
+    border-radius: 0;
+    margin: 0;
+    text-transform: uppercase; }
+    header button:hover, header button:focus, header [type="button"]:hover, header [type="button"]:focus, header .button:hover, header .button:focus, header [role="button"]:hover, header [role="button"]:focus {
+      background: var(--header-hover-back-color); }
+
+nav {
+  background: var(--nav-back-color);
+  color: var(--nav-fore-color);
+  border: 0.0625rem solid var(--nav-border-color);
+  border-radius: var(--universal-border-radius);
+  margin: var(--universal-margin); }
+  nav * {
+    padding: var(--universal-padding) calc(1.5 * var(--universal-padding)); }
+  nav a, nav a:visited {
+    display: block;
+    color: var(--nav-link-color);
+    border-radius: var(--universal-border-radius);
+    transition: background 0.3s; }
+    nav a:hover, nav a:focus, nav a:visited:hover, nav a:visited:focus {
+      text-decoration: none;
+      background: var(--nav-hover-back-color); }
+  nav .sublink-1 {
+    position: relative;
+    margin-left: calc(2 * var(--universal-padding)); }
+    nav .sublink-1:before {
+      position: absolute;
+      left: calc(var(--universal-padding) - 1 * var(--universal-padding));
+      top: -0.0625rem;
+      content: '';
+      height: 100%;
+      border: 0.0625rem solid var(--nav-border-color);
+      border-left: 0; }
+  nav .sublink-2 {
+    position: relative;
+    margin-left: calc(4 * var(--universal-padding)); }
+    nav .sublink-2:before {
+      position: absolute;
+      left: calc(var(--universal-padding) - 3 * var(--universal-padding));
+      top: -0.0625rem;
+      content: '';
+      height: 100%;
+      border: 0.0625rem solid var(--nav-border-color);
+      border-left: 0; }
+
+footer {
+  background: var(--footer-back-color);
+  color: var(--footer-fore-color);
+  border-top: 0.0625rem solid var(--footer-border-color);
+  padding: calc(2 * var(--universal-padding)) var(--universal-padding);
+  font-size: 0.875rem; }
+  footer a, footer a:visited {
+    color: var(--footer-link-color); }
+
+header.sticky {
+  position: -webkit-sticky;
+  position: sticky;
+  z-index: 1101;
+  top: 0; }
+
+footer.sticky {
+  position: -webkit-sticky;
+  position: sticky;
+  z-index: 1101;
+  bottom: 0; }
+
+.drawer-toggle:before {
+  display: inline-block;
+  position: relative;
+  vertical-align: bottom;
+  content: '\00a0\2261\00a0';
+  font-family: sans-serif;
+  font-size: 1.5em; }
+@media screen and (min-width: 500px) {
+  .drawer-toggle:not(.persistent) {
+    display: none; } }
+
+[type="checkbox"].drawer {
+  height: 1px;
+  width: 1px;
+  margin: -1px;
+  overflow: hidden;
+  position: absolute;
+  clip: rect(0 0 0 0);
+  -webkit-clip-path: inset(100%);
+  clip-path: inset(100%); }
+  [type="checkbox"].drawer + * {
+    display: block;
+    box-sizing: border-box;
+    position: fixed;
+    top: 0;
+    width: 320px;
+    height: 100vh;
+    overflow-y: auto;
+    background: var(--drawer-back-color);
+    border: 0.0625rem solid var(--drawer-border-color);
+    border-radius: 0;
+    margin: 0;
+    z-index: 1110;
+    right: -320px;
+    transition: right 0.3s; }
+    [type="checkbox"].drawer + * .drawer-close {
+      position: absolute;
+      top: var(--universal-margin);
+      right: var(--universal-margin);
+      z-index: 1111;
+      width: 2rem;
+      height: 2rem;
+      border-radius: var(--universal-border-radius);
+      padding: var(--universal-padding);
+      margin: 0;
+      cursor: pointer;
+      transition: background 0.3s; }
+      [type="checkbox"].drawer + * .drawer-close:before {
+        display: block;
+        content: '\00D7';
+        color: var(--drawer-close-color);
+        position: relative;
+        font-family: sans-serif;
+        font-size: 2rem;
+        line-height: 1;
+        text-align: center; }
+      [type="checkbox"].drawer + * .drawer-close:hover, [type="checkbox"].drawer + * .drawer-close:focus {
+        background: var(--drawer-hover-back-color); }
+    @media screen and (max-width: 320px) {
+      [type="checkbox"].drawer + * {
+        width: 100%; } }
+  [type="checkbox"].drawer:checked + * {
+    right: 0; }
+  @media screen and (min-width: 500px) {
+    [type="checkbox"].drawer:not(.persistent) + * {
+      position: static;
+      height: 100%;
+      z-index: 1100; }
+      [type="checkbox"].drawer:not(.persistent) + * .drawer-close {
+        display: none; } }
+
+/*
+  Definitions for the responsive table component.
+*/
+/* Table module CSS variable definitions. */
+:root {
+  --table-border-color: #aaa;
+  --table-border-separator-color: #666;
+  --table-head-back-color: #e6e6e6;
+  --table-head-fore-color: #111;
+  --table-body-back-color: #f8f8f8;
+  --table-body-fore-color: #111;
+  --table-body-alt-back-color: #eee; }
+
+table {
+  border-collapse: separate;
+  border-spacing: 0;
+  : margin: calc(1.5 * var(--universal-margin)) var(--universal-margin);
+  display: flex;
+  flex: 0 1 auto;
+  flex-flow: row wrap;
+  padding: var(--universal-padding);
+  padding-top: 0;
+	margin: calc(1.5 * var(--universal-margin)) var(--universal-margin);	}
+  table caption {
+    font-size: 1.25 * rem;
+    margin: calc(2 * var(--universal-margin)) 0;
+    max-width: 100%;
+    flex: 0 0 100%;
+		text-align: left;}
+  table thead, table tbody {
+    display: flex;
+    flex-flow: row wrap;
+    border: 0.0625rem solid var(--table-border-color); }
+  table thead {
+    z-index: 999;
+    border-radius: var(--universal-border-radius) var(--universal-border-radius) 0 0;
+    border-bottom: 0.0625rem solid var(--table-border-separator-color); }
+  table tbody {
+    border-top: 0;
+    margin-top: calc(0 - var(--universal-margin));
+    border-radius: 0 0 var(--universal-border-radius) var(--universal-border-radius); }
+  table tr {
+    display: flex;
+    padding: 0; }
+  table th, table td {
+    padding: calc(0.5 * var(--universal-padding));
+		font-size: 0.9rem; }
+  table th {
+    text-align: left;
+    background: var(--table-head-back-color);
+    color: var(--table-head-fore-color); }
+  table td {
+    background: var(--table-body-back-color);
+    color: var(--table-body-fore-color);
+    border-top: 0.0625rem solid var(--table-border-color); }
+
+table:not(.horizontal) {
+  overflow: auto;
+  max-height: 850px; }
+  table:not(.horizontal) thead, table:not(.horizontal) tbody {
+    max-width: 100%;
+    flex: 0 0 100%; }
+  table:not(.horizontal) tr {
+    flex-flow: row wrap;
+    flex: 0 0 100%; }
+  table:not(.horizontal) th, table:not(.horizontal) td {
+    flex: 1 0 0%;
+    overflow: hidden;
+    text-overflow: ellipsis; }
+  table:not(.horizontal) thead {
+    position: sticky;
+    top: 0; }
+  table:not(.horizontal) tbody tr:first-child td {
+    border-top: 0; }
+
+table.horizontal {
+  border: 0; }
+  table.horizontal thead, table.horizontal tbody {
+    border: 0;
+    flex-flow: row nowrap; }
+  table.horizontal tbody {
+    overflow: auto;
+    justify-content: space-between;
+    flex: 1 0 0;
+    margin-left: calc( 4 * var(--universal-margin));
+    padding-bottom: calc(var(--universal-padding) / 4); }
+  table.horizontal tr {
+    flex-direction: column;
+    flex: 1 0 auto; }
+  table.horizontal th, table.horizontal td {
+    width: 100%;
+    border: 0;
+    border-bottom: 0.0625rem solid var(--table-border-color); }
+    table.horizontal th:not(:first-child), table.horizontal td:not(:first-child) {
+      border-top: 0; }
+  table.horizontal th {
+    text-align: right;
+    border-left: 0.0625rem solid var(--table-border-color);
+    border-right: 0.0625rem solid var(--table-border-separator-color); }
+  table.horizontal thead tr:first-child {
+    padding-left: 0; }
+  table.horizontal th:first-child, table.horizontal td:first-child {
+    border-top: 0.0625rem solid var(--table-border-color); }
+  table.horizontal tbody tr:last-child td {
+    border-right: 0.0625rem solid var(--table-border-color); }
+    table.horizontal tbody tr:last-child td:first-child {
+      border-top-right-radius: 0.25rem; }
+    table.horizontal tbody tr:last-child td:last-child {
+      border-bottom-right-radius: 0.25rem; }
+  table.horizontal thead tr:first-child th:first-child {
+    border-top-left-radius: 0.25rem; }
+  table.horizontal thead tr:first-child th:last-child {
+    border-bottom-left-radius: 0.25rem; }
+
+@media screen and (max-width: 499px) {
+  table, table.horizontal {
+    border-collapse: collapse;
+    border: 0;
+    width: 100%;
+    display: table; }
+    table thead, table th, table.horizontal thead, table.horizontal th {
+      border: 0;
+      height: 1px;
+      width: 1px;
+      margin: -1px;
+      overflow: hidden;
+      padding: 0;
+      position: absolute;
+      clip: rect(0 0 0 0);
+      -webkit-clip-path: inset(100%);
+      clip-path: inset(100%); }
+    table tbody, table.horizontal tbody {
+      border: 0;
+      display: table-row-group; }
+    table tr, table.horizontal tr {
+      display: block;
+      border: 0.0625rem solid var(--table-border-color);
+      border-radius: var(--universal-border-radius);
+      background: #fafafa;
+      padding: var(--universal-padding);
+      margin: var(--universal-margin);
+      margin-bottom: calc(2 * var(--universal-margin)); }
+    table th, table td, table.horizontal th, table.horizontal td {
+      width: auto; }
+    table td, table.horizontal td {
+      display: block;
+      border: 0;
+      text-align: right; }
+    table td:before, table.horizontal td:before {
+      content: attr(data-label);
+      float: left;
+      font-weight: 600; }
+    table th:first-child, table td:first-child, table.horizontal th:first-child, table.horizontal td:first-child {
+      border-top: 0; }
+    table tbody tr:last-child td, table.horizontal tbody tr:last-child td {
+      border-right: 0; } }
+:root {
+  --table-body-alt-back-color: #eee; }
+
+table tr:nth-of-type(2n) > td {
+  background: var(--table-body-alt-back-color); }
+
+@media screen and (max-width: 500px) {
+  table tr:nth-of-type(2n) {
+    background: var(--table-body-alt-back-color); } }
+:root {
+  --table-body-hover-back-color: #90caf9; }
+
+table.hoverable tr:hover, table.hoverable tr:hover > td, table.hoverable tr:focus, table.hoverable tr:focus > td {
+  background: var(--table-body-hover-back-color); }
+
+@media screen and (max-width: 500px) {
+  table.hoverable tr:hover, table.hoverable tr:hover > td, table.hoverable tr:focus, table.hoverable tr:focus > td {
+    background: var(--table-body-hover-back-color); } }
+/*
+  Definitions for contextual background elements, toasts and tooltips.
+*/
+/* Contextual module CSS variable definitions */
+:root {
+  --mark-back-color: #0277bd;
+  --mark-fore-color: #fafafa; }
+
+mark {
+  background: var(--mark-back-color);
+  color: var(--mark-fore-color);
+  font-size: 0.95em;
+  line-height: 1em;
+  border-radius: var(--universal-border-radius);
+  padding: calc(var(--universal-padding) / 4) calc(var(--universal-padding) / 2); }
+  mark.inline-block {
+    display: inline-block;
+    font-size: 1em;
+    line-height: 1.5;
+    padding: calc(var(--universal-padding) / 2) var(--universal-padding); }
+
+:root {
+  --toast-back-color: #424242;
+  --toast-fore-color: #fafafa; }
+
+.toast {
+  position: fixed;
+  bottom: calc(var(--universal-margin) * 3);
+  left: 50%;
+  transform: translate(-50%, -50%);
+  z-index: 1111;
+  color: var(--toast-fore-color);
+  background: var(--toast-back-color);
+  border-radius: calc(var(--universal-border-radius) * 16);
+  padding: var(--universal-padding) calc(var(--universal-padding) * 3); }
+
+:root {
+  --tooltip-back-color: #212121;
+  --tooltip-fore-color: #fafafa; }
+
+.tooltip {
+  position: relative;
+  display: inline-block; }
+  .tooltip:before, .tooltip:after {
+    position: absolute;
+    opacity: 0;
+    clip: rect(0 0 0 0);
+    -webkit-clip-path: inset(100%);
+    clip-path: inset(100%);
+    transition: all 0.3s;
+    z-index: 1010;
+    left: 50%; }
+  .tooltip:not(.bottom):before, .tooltip:not(.bottom):after {
+    bottom: 75%; }
+  .tooltip.bottom:before, .tooltip.bottom:after {
+    top: 75%; }
+  .tooltip:hover:before, .tooltip:hover:after, .tooltip:focus:before, .tooltip:focus:after {
+    opacity: 1;
+    clip: auto;
+    -webkit-clip-path: inset(0%);
+    clip-path: inset(0%); }
+  .tooltip:before {
+    content: '';
+    background: transparent;
+    border: var(--universal-margin) solid transparent;
+    left: calc(50% - var(--universal-margin)); }
+  .tooltip:not(.bottom):before {
+    border-top-color: #212121; }
+  .tooltip.bottom:before {
+    border-bottom-color: #212121; }
+  .tooltip:after {
+    content: attr(aria-label);
+    color: var(--tooltip-fore-color);
+    background: var(--tooltip-back-color);
+    border-radius: var(--universal-border-radius);
+    padding: var(--universal-padding);
+    white-space: nowrap;
+    transform: translateX(-50%); }
+  .tooltip:not(.bottom):after {
+    margin-bottom: calc(2 * var(--universal-margin)); }
+  .tooltip.bottom:after {
+    margin-top: calc(2 * var(--universal-margin)); }
+
+:root {
+  --modal-overlay-color: rgba(0, 0, 0, 0.45);
+  --modal-close-color: #444;
+  --modal-close-hover-color: #f0f0f0; }
+
+[type="checkbox"].modal {
+  height: 1px;
+  width: 1px;
+  margin: -1px;
+  overflow: hidden;
+  position: absolute;
+  clip: rect(0 0 0 0);
+  -webkit-clip-path: inset(100%);
+  clip-path: inset(100%); }
+  [type="checkbox"].modal + div {
+    position: fixed;
+    top: 0;
+    left: 0;
+    display: none;
+    width: 100vw;
+    height: 100vh;
+    background: var(--modal-overlay-color); }
+    [type="checkbox"].modal + div .card {
+      margin: 0 auto;
+      max-height: 50vh;
+      overflow: auto; }
+      [type="checkbox"].modal + div .card .modal-close {
+        position: absolute;
+        top: 0;
+        right: 0;
+        width: 1.75rem;
+        height: 1.75rem;
+        border-radius: var(--universal-border-radius);
+        padding: var(--universal-padding);
+        margin: 0;
+        cursor: pointer;
+        transition: background 0.3s; }
+        [type="checkbox"].modal + div .card .modal-close:before {
+          display: block;
+          content: '\00D7';
+          color: var(--modal-close-color);
+          position: relative;
+          font-family: sans-serif;
+          font-size: 1.75rem;
+          line-height: 1;
+          text-align: center; }
+        [type="checkbox"].modal + div .card .modal-close:hover, [type="checkbox"].modal + div .card .modal-close:focus {
+          background: var(--modal-close-hover-color); }
+  [type="checkbox"].modal:checked + div {
+    display: flex;
+    flex: 0 1 auto;
+    z-index: 1200; }
+    [type="checkbox"].modal:checked + div .card .modal-close {
+      z-index: 1211; }
+
+:root {
+  --collapse-label-back-color: #e8e8e8;
+  --collapse-label-fore-color: #212121;
+  --collapse-label-hover-back-color: #f0f0f0;
+  --collapse-selected-label-back-color: #ececec;
+  --collapse-border-color: #ddd;
+  --collapse-content-back-color: #fafafa;
+  --collapse-selected-label-border-color: #0277bd; }
+
+.collapse {
+  width: calc(100% - 2 * var(--universal-margin));
+  opacity: 1;
+  display: flex;
+  flex-direction: column;
+  margin: var(--universal-margin);
+  border-radius: var(--universal-border-radius); }
+  .collapse > [type="radio"], .collapse > [type="checkbox"] {
+    height: 1px;
+    width: 1px;
+    margin: -1px;
+    overflow: hidden;
+    position: absolute;
+    clip: rect(0 0 0 0);
+    -webkit-clip-path: inset(100%);
+    clip-path: inset(100%); }
+  .collapse > label {
+    flex-grow: 1;
+    display: inline-block;
+    height: 1.5rem;
+    cursor: pointer;
+    transition: background 0.3s;
+    color: var(--collapse-label-fore-color);
+    background: var(--collapse-label-back-color);
+    border: 0.0625rem solid var(--collapse-border-color);
+    padding: calc(1.5 * var(--universal-padding)); }
+    .collapse > label:hover, .collapse > label:focus {
+      background: var(--collapse-label-hover-back-color); }
+    .collapse > label + div {
+      flex-basis: auto;
+      height: 1px;
+      width: 1px;
+      margin: -1px;
+      overflow: hidden;
+      position: absolute;
+      clip: rect(0 0 0 0);
+      -webkit-clip-path: inset(100%);
+      clip-path: inset(100%);
+      transition: max-height 0.3s;
+      max-height: 1px; }
+  .collapse > :checked + label {
+    background: var(--collapse-selected-label-back-color);
+    border-bottom-color: var(--collapse-selected-label-border-color); }
+    .collapse > :checked + label + div {
+      box-sizing: border-box;
+      position: relative;
+      width: 100%;
+      height: auto;
+      overflow: auto;
+      margin: 0;
+      background: var(--collapse-content-back-color);
+      border: 0.0625rem solid var(--collapse-border-color);
+      border-top: 0;
+      padding: var(--universal-padding);
+      clip: auto;
+      -webkit-clip-path: inset(0%);
+      clip-path: inset(0%);
+      max-height: 850px; }
+  .collapse > label:not(:first-of-type) {
+    border-top: 0; }
+  .collapse > label:first-of-type {
+    border-radius: var(--universal-border-radius) var(--universal-border-radius) 0 0; }
+  .collapse > label:last-of-type:not(:first-of-type) {
+    border-radius: 0 0 var(--universal-border-radius) var(--universal-border-radius); }
+  .collapse > label:last-of-type:first-of-type {
+    border-radius: var(--universal-border-radius); }
+  .collapse > :checked:last-of-type:not(:first-of-type) + label {
+    border-radius: 0; }
+  .collapse > :checked:last-of-type + label + div {
+    border-radius: 0 0 var(--universal-border-radius) var(--universal-border-radius); }
+
+/*
+  Custom elements for contextual background elements, toasts and tooltips.
+*/
+mark.secondary {
+  --mark-back-color: #d32f2f; }
+
+mark.tertiary {
+  --mark-back-color: #308732; }
+
+mark.tag {
+  padding: calc(var(--universal-padding)/2) var(--universal-padding);
+  border-radius: 1em; }
+
+/*
+  Definitions for progress elements and spinners.
+*/
+/* Progess module CSS variable definitions */
+:root {
+  --progress-back-color: #ddd;
+  --progress-fore-color: #555; }
+
+progress {
+  display: block;
+  vertical-align: baseline;
+  -webkit-appearance: none;
+  -moz-appearance: none;
+  appearance: none;
+  height: 0.75rem;
+  width: calc(100% - 2 * var(--universal-margin));
+  margin: var(--universal-margin);
+  border: 0;
+  border-radius: calc(2 * var(--universal-border-radius));
+  background: var(--progress-back-color);
+  color: var(--progress-fore-color); }
+  progress::-webkit-progress-value {
+    background: var(--progress-fore-color);
+    border-top-left-radius: calc(2 * var(--universal-border-radius));
+    border-bottom-left-radius: calc(2 * var(--universal-border-radius)); }
+  progress::-webkit-progress-bar {
+    background: var(--progress-back-color); }
+  progress::-moz-progress-bar {
+    background: var(--progress-fore-color);
+    border-top-left-radius: calc(2 * var(--universal-border-radius));
+    border-bottom-left-radius: calc(2 * var(--universal-border-radius)); }
+  progress[value="1000"]::-webkit-progress-value {
+    border-radius: calc(2 * var(--universal-border-radius)); }
+  progress[value="1000"]::-moz-progress-bar {
+    border-radius: calc(2 * var(--universal-border-radius)); }
+  progress.inline {
+    display: inline-block;
+    vertical-align: middle;
+    width: 60%; }
+
+:root {
+  --spinner-back-color: #ddd;
+  --spinner-fore-color: #555; }
+
+@keyframes spinner-donut-anim {
+  0% {
+    transform: rotate(0deg); }
+  100% {
+    transform: rotate(360deg); } }
+.spinner {
+  display: inline-block;
+  margin: var(--universal-margin);
+  border: 0.25rem solid var(--spinner-back-color);
+  border-left: 0.25rem solid var(--spinner-fore-color);
+  border-radius: 50%;
+  width: 1.25rem;
+  height: 1.25rem;
+  animation: spinner-donut-anim 1.2s linear infinite; }
+
+/*
+  Custom elements for progress bars and spinners.
+*/
+progress.primary {
+  --progress-fore-color: #1976d2; }
+
+progress.secondary {
+  --progress-fore-color: #d32f2f; }
+
+progress.tertiary {
+  --progress-fore-color: #308732; }
+
+.spinner.primary {
+  --spinner-fore-color: #1976d2; }
+
+.spinner.secondary {
+  --spinner-fore-color: #d32f2f; }
+
+.spinner.tertiary {
+  --spinner-fore-color: #308732; }
+
+/*
+  Definitions for icons - powered by Feather (https://feathericons.com/).
+*/
+span[class^='icon-'] {
+  display: inline-block;
+  height: 1em;
+  width: 1em;
+  vertical-align: -0.125em;
+  background-size: contain;
+  margin: 0 calc(var(--universal-margin) / 4); }
+  span[class^='icon-'].secondary {
+    -webkit-filter: invert(25%);
+    filter: invert(25%); }
+  span[class^='icon-'].inverse {
+    -webkit-filter: invert(100%);
+    filter: invert(100%); }
+
+span.icon-alert {
+  background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='12' cy='12' r='10'%3E%3C/circle%3E%3Cline x1='12' y1='8' x2='12' y2='12'%3E%3C/line%3E%3Cline x1='12' y1='16' x2='12' y2='16'%3E%3C/line%3E%3C/svg%3E"); }
+span.icon-bookmark {
+  background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M19 21l-7-5-7 5V5a2 2 0 0 1 2-2h10a2 2 0 0 1 2 2z'%3E%3C/path%3E%3C/svg%3E"); }
+span.icon-calendar {
+  background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Crect x='3' y='4' width='18' height='18' rx='2' ry='2'%3E%3C/rect%3E%3Cline x1='16' y1='2' x2='16' y2='6'%3E%3C/line%3E%3Cline x1='8' y1='2' x2='8' y2='6'%3E%3C/line%3E%3Cline x1='3' y1='10' x2='21' y2='10'%3E%3C/line%3E%3C/svg%3E"); }
+span.icon-credit {
+  background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Crect x='1' y='4' width='22' height='16' rx='2' ry='2'%3E%3C/rect%3E%3Cline x1='1' y1='10' x2='23' y2='10'%3E%3C/line%3E%3C/svg%3E"); }
+span.icon-edit {
+  background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M20 14.66V20a2 2 0 0 1-2 2H4a2 2 0 0 1-2-2V6a2 2 0 0 1 2-2h5.34'%3E%3C/path%3E%3Cpolygon points='18 2 22 6 12 16 8 16 8 12 18 2'%3E%3C/polygon%3E%3C/svg%3E"); }
+span.icon-link {
+  background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M18 13v6a2 2 0 0 1-2 2H5a2 2 0 0 1-2-2V8a2 2 0 0 1 2-2h6'%3E%3C/path%3E%3Cpolyline points='15 3 21 3 21 9'%3E%3C/polyline%3E%3Cline x1='10' y1='14' x2='21' y2='3'%3E%3C/line%3E%3C/svg%3E"); }
+span.icon-help {
+  background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M9.09 9a3 3 0 0 1 5.83 1c0 2-3 3-3 3'%3E%3C/path%3E%3Ccircle cx='12' cy='12' r='10'%3E%3C/circle%3E%3Cline x1='12' y1='17' x2='12' y2='17'%3E%3C/line%3E%3C/svg%3E"); }
+span.icon-home {
+  background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M3 9l9-7 9 7v11a2 2 0 0 1-2 2H5a2 2 0 0 1-2-2z'%3E%3C/path%3E%3Cpolyline points='9 22 9 12 15 12 15 22'%3E%3C/polyline%3E%3C/svg%3E"); }
+span.icon-info {
+  background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='12' cy='12' r='10'%3E%3C/circle%3E%3Cline x1='12' y1='16' x2='12' y2='12'%3E%3C/line%3E%3Cline x1='12' y1='8' x2='12' y2='8'%3E%3C/line%3E%3C/svg%3E"); }
+span.icon-lock {
+  background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Crect x='3' y='11' width='18' height='11' rx='2' ry='2'%3E%3C/rect%3E%3Cpath d='M7 11V7a5 5 0 0 1 10 0v4'%3E%3C/path%3E%3C/svg%3E"); }
+span.icon-mail {
+  background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M4 4h16c1.1 0 2 .9 2 2v12c0 1.1-.9 2-2 2H4c-1.1 0-2-.9-2-2V6c0-1.1.9-2 2-2z'%3E%3C/path%3E%3Cpolyline points='22,6 12,13 2,6'%3E%3C/polyline%3E%3C/svg%3E"); }
+span.icon-location {
+  background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M21 10c0 7-9 13-9 13s-9-6-9-13a9 9 0 0 1 18 0z'%3E%3C/path%3E%3Ccircle cx='12' cy='10' r='3'%3E%3C/circle%3E%3C/svg%3E"); }
+span.icon-phone {
+  background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M22 16.92v3a2 2 0 0 1-2.18 2 19.79 19.79 0 0 1-8.63-3.07 19.5 19.5 0 0 1-6-6 19.79 19.79 0 0 1-3.07-8.67A2 2 0 0 1 4.11 2h3a2 2 0 0 1 2 1.72 12.84 12.84 0 0 0 .7 2.81 2 2 0 0 1-.45 2.11L8.09 9.91a16 16 0 0 0 6 6l1.27-1.27a2 2 0 0 1 2.11-.45 12.84 12.84 0 0 0 2.81.7A2 2 0 0 1 22 16.92z'%3E%3C/path%3E%3C/svg%3E"); }
+span.icon-rss {
+  background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M4 11a9 9 0 0 1 9 9'%3E%3C/path%3E%3Cpath d='M4 4a16 16 0 0 1 16 16'%3E%3C/path%3E%3Ccircle cx='5' cy='19' r='1'%3E%3C/circle%3E%3C/svg%3E"); }
+span.icon-search {
+  background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='11' cy='11' r='8'%3E%3C/circle%3E%3Cline x1='21' y1='21' x2='16.65' y2='16.65'%3E%3C/line%3E%3C/svg%3E"); }
+span.icon-settings {
+  background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='12' cy='12' r='3'%3E%3C/circle%3E%3Cpath d='M19.4 15a1.65 1.65 0 0 0 .33 1.82l.06.06a2 2 0 0 1 0 2.83 2 2 0 0 1-2.83 0l-.06-.06a1.65 1.65 0 0 0-1.82-.33 1.65 1.65 0 0 0-1 1.51V21a2 2 0 0 1-2 2 2 2 0 0 1-2-2v-.09A1.65 1.65 0 0 0 9 19.4a1.65 1.65 0 0 0-1.82.33l-.06.06a2 2 0 0 1-2.83 0 2 2 0 0 1 0-2.83l.06-.06a1.65 1.65 0 0 0 .33-1.82 1.65 1.65 0 0 0-1.51-1H3a2 2 0 0 1-2-2 2 2 0 0 1 2-2h.09A1.65 1.65 0 0 0 4.6 9a1.65 1.65 0 0 0-.33-1.82l-.06-.06a2 2 0 0 1 0-2.83 2 2 0 0 1 2.83 0l.06.06a1.65 1.65 0 0 0 1.82.33H9a1.65 1.65 0 0 0 1-1.51V3a2 2 0 0 1 2-2 2 2 0 0 1 2 2v.09a1.65 1.65 0 0 0 1 1.51 1.65 1.65 0 0 0 1.82-.33l.06-.06a2 2 0 0 1 2.83 0 2 2 0 0 1 0 2.83l-.06.06a1.65 1.65 0 0 0-.33 1.82V9a1.65 1.65 0 0 0 1.51 1H21a2 2 0 0 1 2 2 2 2 0 0 1-2 2h-.09a1.65 1.65 0 0 0-1.51 1z'%3E%3C/path%3E%3C/svg%3E"); }
+span.icon-share {
+  background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='18' cy='5' r='3'%3E%3C/circle%3E%3Ccircle cx='6' cy='12' r='3'%3E%3C/circle%3E%3Ccircle cx='18' cy='19' r='3'%3E%3C/circle%3E%3Cline x1='8.59' y1='13.51' x2='15.42' y2='17.49'%3E%3C/line%3E%3Cline x1='15.41' y1='6.51' x2='8.59' y2='10.49'%3E%3C/line%3E%3C/svg%3E"); }
+span.icon-cart {
+  background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='9' cy='21' r='1'%3E%3C/circle%3E%3Ccircle cx='20' cy='21' r='1'%3E%3C/circle%3E%3Cpath d='M1 1h4l2.68 13.39a2 2 0 0 0 2 1.61h9.72a2 2 0 0 0 2-1.61L23 6H6'%3E%3C/path%3E%3C/svg%3E"); }
+span.icon-upload {
+  background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M21 15v4a2 2 0 0 1-2 2H5a2 2 0 0 1-2-2v-4'%3E%3C/path%3E%3Cpolyline points='17 8 12 3 7 8'%3E%3C/polyline%3E%3Cline x1='12' y1='3' x2='12' y2='15'%3E%3C/line%3E%3C/svg%3E"); }
+span.icon-user {
+  background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M20 21v-2a4 4 0 0 0-4-4H8a4 4 0 0 0-4 4v2'%3E%3C/path%3E%3Ccircle cx='12' cy='7' r='4'%3E%3C/circle%3E%3C/svg%3E"); }
+
+/*
+  Definitions for utilities and helper classes.
+*/
+/* Utility module CSS variable definitions */
+:root {
+  --generic-border-color: rgba(0, 0, 0, 0.3);
+  --generic-box-shadow: 0 0.25rem 0.25rem 0 rgba(0, 0, 0, 0.125), 0 0.125rem 0.125rem -0.125rem rgba(0, 0, 0, 0.25); }
+
+.hidden {
+  display: none !important; }
+
+.visually-hidden {
+  position: absolute !important;
+  width: 1px !important;
+  height: 1px !important;
+  margin: -1px !important;
+  border: 0 !important;
+  padding: 0 !important;
+  clip: rect(0 0 0 0) !important;
+  -webkit-clip-path: inset(100%) !important;
+  clip-path: inset(100%) !important;
+  overflow: hidden !important; }
+
+.bordered {
+  border: 0.0625rem solid var(--generic-border-color) !important; }
+
+.rounded {
+  border-radius: var(--universal-border-radius) !important; }
+
+.circular {
+  border-radius: 50% !important; }
+
+.shadowed {
+  box-shadow: var(--generic-box-shadow) !important; }
+
+.responsive-margin {
+  margin: calc(var(--universal-margin) / 4) !important; }
+  @media screen and (min-width: 500px) {
+    .responsive-margin {
+      margin: calc(var(--universal-margin) / 2) !important; } }
+  @media screen and (min-width: 1280px) {
+    .responsive-margin {
+      margin: var(--universal-margin) !important; } }
+
+.responsive-padding {
+  padding: calc(var(--universal-padding) / 4) !important; }
+  @media screen and (min-width: 500px) {
+    .responsive-padding {
+      padding: calc(var(--universal-padding) / 2) !important; } }
+  @media screen and (min-width: 1280px) {
+    .responsive-padding {
+      padding: var(--universal-padding) !important; } }
+
+@media screen and (max-width: 499px) {
+  .hidden-sm {
+    display: none !important; } }
+@media screen and (min-width: 500px) and (max-width: 1279px) {
+  .hidden-md {
+    display: none !important; } }
+@media screen and (min-width: 1280px) {
+  .hidden-lg {
+    display: none !important; } }
+@media screen and (max-width: 499px) {
+  .visually-hidden-sm {
+    position: absolute !important;
+    width: 1px !important;
+    height: 1px !important;
+    margin: -1px !important;
+    border: 0 !important;
+    padding: 0 !important;
+    clip: rect(0 0 0 0) !important;
+    -webkit-clip-path: inset(100%) !important;
+    clip-path: inset(100%) !important;
+    overflow: hidden !important; } }
+@media screen and (min-width: 500px) and (max-width: 1279px) {
+  .visually-hidden-md {
+    position: absolute !important;
+    width: 1px !important;
+    height: 1px !important;
+    margin: -1px !important;
+    border: 0 !important;
+    padding: 0 !important;
+    clip: rect(0 0 0 0) !important;
+    -webkit-clip-path: inset(100%) !important;
+    clip-path: inset(100%) !important;
+    overflow: hidden !important; } }
+@media screen and (min-width: 1280px) {
+  .visually-hidden-lg {
+    position: absolute !important;
+    width: 1px !important;
+    height: 1px !important;
+    margin: -1px !important;
+    border: 0 !important;
+    padding: 0 !important;
+    clip: rect(0 0 0 0) !important;
+    -webkit-clip-path: inset(100%) !important;
+    clip-path: inset(100%) !important;
+    overflow: hidden !important; } }
+
+/*# sourceMappingURL=mini-default.css.map */
diff --git a/Drivers/BSP/STM32469I-Discovery/_htmresc/st_logo.png b/Drivers/BSP/STM32469I-Discovery/_htmresc/st_logo.png
new file mode 100644
index 0000000..8b80057
Binary files /dev/null and b/Drivers/BSP/STM32469I-Discovery/_htmresc/st_logo.png differ
diff --git a/Drivers/BSP/STM32469I-Discovery/stm32469i_discovery.c b/Drivers/BSP/STM32469I-Discovery/stm32469i_discovery.c
new file mode 100644
index 0000000..efe6bab
--- /dev/null
+++ b/Drivers/BSP/STM32469I-Discovery/stm32469i_discovery.c
@@ -0,0 +1,943 @@
+/**
+  ******************************************************************************
+  * @file    stm32469i_discovery.c
+  * @author  MCD Application Team
+  * @brief   This file provides a set of firmware functions to manage LEDs,
+  *          push-buttons, external SDRAM, external QSPI Flash, RF EEPROM,
+  *          available on STM32469I-Discovery
+  *          board (MB1189) RevA/B/C from STMicroelectronics.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32469i_discovery.h"
+
+/** @defgroup BSP BSP
+  * @{
+  */
+
+/** @defgroup STM32469I_Discovery STM32469I Discovery
+  * @{
+  */
+
+/** @defgroup STM32469I_Discovery_LOW_LEVEL STM32469I Discovery LOW LEVEL
+  * @{
+  */
+
+/** @defgroup STM32469I_Discovery_LOW_LEVEL_Private_TypesDefinitions STM32469I Discovery LOW LEVEL Private TypesDefinitions
+  * @{
+  */
+/**
+  * @}
+  */
+
+/** @defgroup STM32469I_Discovery_LOW_LEVEL_Private_Defines STM32469I Discovery LOW LEVEL Private Defines
+  * @{
+  */
+/**
+ * @brief STM32469I Discovery BSP Driver version number V2.1.1
+   */
+#define __STM32469I_DISCOVERY_BSP_VERSION_MAIN   (0x02) /*!< [31:24] main version */
+#define __STM32469I_DISCOVERY_BSP_VERSION_SUB1   (0x01) /*!< [23:16] sub1 version */
+#define __STM32469I_DISCOVERY_BSP_VERSION_SUB2   (0x01) /*!< [15:8]  sub2 version */
+#define __STM32469I_DISCOVERY_BSP_VERSION_RC     (0x00) /*!< [7:0]  release candidate */
+#define __STM32469I_DISCOVERY_BSP_VERSION        ((__STM32469I_DISCOVERY_BSP_VERSION_MAIN << 24)\
+                                                 |(__STM32469I_DISCOVERY_BSP_VERSION_SUB1 << 16)\
+                                                 |(__STM32469I_DISCOVERY_BSP_VERSION_SUB2 << 8 )\
+                                                 |(__STM32469I_DISCOVERY_BSP_VERSION_RC))
+/**
+  * @}
+  */
+
+/** @defgroup STM32469I_Discovery_LOW_LEVEL_Private_Macros  STM32469I Discovery LOW LEVEL Private Macros
+  * @{
+  */
+/**
+  * @}
+  */
+
+/** @defgroup STM32469I_Discovery_LOW_LEVEL_Private_Variables STM32469I Discovery LOW LEVEL Private Variables
+  * @{
+  */
+uint32_t GPIO_PIN[LEDn] = {LED1_PIN,
+                           LED2_PIN,
+                           LED3_PIN,
+                           LED4_PIN};
+
+GPIO_TypeDef* GPIO_PORT[LEDn] = {LED1_GPIO_PORT,
+                                 LED2_GPIO_PORT,
+                                 LED3_GPIO_PORT,
+                                 LED4_GPIO_PORT};
+
+GPIO_TypeDef* BUTTON_PORT[BUTTONn] = {WAKEUP_BUTTON_GPIO_PORT };
+
+const uint16_t BUTTON_PIN[BUTTONn] = {WAKEUP_BUTTON_PIN };
+
+const uint16_t BUTTON_IRQn[BUTTONn] = {WAKEUP_BUTTON_EXTI_IRQn };
+
+
+static I2C_HandleTypeDef heval_I2c1;
+static I2C_HandleTypeDef heval_I2c2;
+
+/**
+  * @}
+  */
+
+/** @defgroup STM32469I_Discovery_LOW_LEVEL_Private_FunctionPrototypes STM32469I Discovery LOW LEVEL Private FunctionPrototypes
+  * @{
+  */
+static void            I2C1_MspInit(void);
+static void            I2C2_MspInit(void);
+static void            I2C1_Init(void);
+static void            I2C2_Init(void);
+
+#if defined(USE_IOEXPANDER)
+static void            I2C1_Write(uint8_t Addr, uint8_t Reg, uint8_t Value);
+static uint8_t       I2C1_Read(uint8_t Addr, uint8_t Reg);
+#endif /* USE_IOEXPANDER */
+static HAL_StatusTypeDef I2C1_ReadMultiple(uint8_t Addr, uint16_t Reg, uint16_t MemAddSize, uint8_t *Buffer, uint16_t Length);
+static HAL_StatusTypeDef I2C2_ReadMultiple(uint8_t Addr, uint16_t Reg, uint16_t MemAddSize, uint8_t *Buffer, uint16_t Length);
+static HAL_StatusTypeDef I2C1_WriteMultiple(uint8_t Addr, uint16_t Reg, uint16_t MemAddSize, uint8_t *Buffer, uint16_t Length);
+static HAL_StatusTypeDef I2C2_WriteMultiple(uint8_t Addr, uint16_t Reg, uint16_t MemAddSize, uint8_t *Buffer, uint16_t Length);
+static HAL_StatusTypeDef I2C1_IsDeviceReady(uint16_t DevAddress, uint32_t Trials);
+static void              I2C1_Error(uint8_t Addr);
+static void              I2C2_Error(uint8_t Addr);
+
+/* AUDIO IO functions */
+void              AUDIO_IO_Init(void);
+void              AUDIO_IO_DeInit(void);
+void              AUDIO_IO_Write(uint8_t Addr, uint8_t Reg, uint8_t Value);
+uint8_t           AUDIO_IO_Read(uint8_t Addr, uint8_t Reg);
+void              AUDIO_IO_Delay(uint32_t Delay);
+
+
+/* I2C EEPROM IO function */
+void                EEPROM_IO_Init(void);
+HAL_StatusTypeDef   EEPROM_IO_WriteData(uint16_t DevAddress, uint16_t MemAddress, uint8_t* pBuffer, uint32_t BufferSize);
+HAL_StatusTypeDef   EEPROM_IO_ReadData(uint16_t DevAddress, uint16_t MemAddress, uint8_t* pBuffer, uint32_t BufferSize);
+HAL_StatusTypeDef   EEPROM_IO_IsDeviceReady(uint16_t DevAddress, uint32_t Trials);
+
+/* TouchScreen (TS) IO functions */
+void    TS_IO_Init(void);
+void    TS_IO_Write(uint8_t Addr, uint8_t Reg, uint8_t Value);
+uint8_t  TS_IO_Read(uint8_t Addr, uint8_t Reg);
+uint16_t TS_IO_ReadMultiple(uint8_t Addr, uint8_t Reg, uint8_t *Buffer, uint16_t Length);
+void    TS_IO_WriteMultiple(uint8_t Addr, uint8_t Reg, uint8_t *Buffer, uint16_t Length);
+void    TS_IO_Delay(uint32_t Delay);
+void     OTM8009A_IO_Delay(uint32_t Delay);
+void     NT35510_IO_Delay(uint32_t Delay);
+/**
+  * @}
+  */
+
+/** @defgroup STM32469I_Discovery_BSP_Public_Functions STM32469I Discovery BSP Public Functions
+  * @{
+  */
+
+  /**
+  * @brief  This method returns the STM32469I Discovery BSP Driver revision
+  * @retval version: 0xXYZR (8bits for each decimal, R for RC)
+  */
+uint32_t BSP_GetVersion(void)
+{
+  return __STM32469I_DISCOVERY_BSP_VERSION;
+}
+
+/**
+  * @brief  Configures LED GPIO.
+  * @param  Led: LED to be configured.
+  *          This parameter can be one of the following values:
+  *            @arg  LED1
+  *            @arg  LED2
+  *            @arg  LED3
+  *            @arg  LED4
+  */
+void BSP_LED_Init(Led_TypeDef Led)
+{
+  GPIO_InitTypeDef  gpio_init_structure;
+
+  if (Led <= LED4)
+  {
+    /* Configure the GPIO_LED pin */
+    gpio_init_structure.Pin   = GPIO_PIN[Led];
+    gpio_init_structure.Mode  = GPIO_MODE_OUTPUT_PP;
+    gpio_init_structure.Pull  = GPIO_PULLUP;
+    gpio_init_structure.Speed = GPIO_SPEED_HIGH;
+
+    switch(Led)
+    {
+    case LED1 :
+      LED1_GPIO_CLK_ENABLE();
+      break;
+    case LED2 :
+      LED2_GPIO_CLK_ENABLE();
+      break;
+    case LED3 :
+      LED3_GPIO_CLK_ENABLE();
+      break;
+    case LED4 :
+      LED4_GPIO_CLK_ENABLE();
+      break;
+    default :
+      break;
+
+    } /* end switch */
+
+    HAL_GPIO_Init(GPIO_PORT[Led], &gpio_init_structure);
+
+    /* By default, turn off LED by setting a high level on corresponding GPIO */
+    HAL_GPIO_WritePin(GPIO_PORT[Led], GPIO_PIN[Led], GPIO_PIN_SET);
+
+  } /* of if (Led <= LED4) */
+
+}
+
+
+/**
+  * @brief  DeInit LEDs.
+  * @param  Led: LED to be configured.
+  *          This parameter can be one of the following values:
+  *            @arg  LED1
+  *            @arg  LED2
+  *            @arg  LED3
+  *            @arg  LED4
+  * @note Led DeInit does not disable the GPIO clock nor disable the Mfx
+  */
+void BSP_LED_DeInit(Led_TypeDef Led)
+{
+  GPIO_InitTypeDef  gpio_init_structure;
+
+  if (Led <= LED4)
+  {
+    /* DeInit the GPIO_LED pin */
+    gpio_init_structure.Pin = GPIO_PIN[Led];
+
+    /* Turn off LED */
+    HAL_GPIO_WritePin(GPIO_PORT[Led], GPIO_PIN[Led], GPIO_PIN_SET);
+    HAL_GPIO_DeInit(GPIO_PORT[Led], gpio_init_structure.Pin);
+  }
+
+}
+
+/**
+  * @brief  Turns selected LED On.
+  * @param  Led: LED to be set on
+  *          This parameter can be one of the following values:
+  *            @arg  LED1
+  *            @arg  LED2
+  *            @arg  LED3
+  *            @arg  LED4
+  */
+void BSP_LED_On(Led_TypeDef Led)
+{
+  if (Led <= LED4)
+  {
+     HAL_GPIO_WritePin(GPIO_PORT[Led], GPIO_PIN[Led], GPIO_PIN_RESET);
+  }
+
+}
+
+/**
+  * @brief  Turns selected LED Off.
+  * @param  Led: LED to be set off
+  *          This parameter can be one of the following values:
+  *            @arg  LED1
+  *            @arg  LED2
+  *            @arg  LED3
+  *            @arg  LED4
+  */
+void BSP_LED_Off(Led_TypeDef Led)
+{
+  if (Led <= LED4)
+  {
+    HAL_GPIO_WritePin(GPIO_PORT[Led], GPIO_PIN[Led], GPIO_PIN_SET);
+  }
+}
+
+/**
+  * @brief  Toggles the selected LED.
+  * @param  Led: LED to be toggled
+  *          This parameter can be one of the following values:
+  *            @arg  LED1
+  *            @arg  LED2
+  *            @arg  LED3
+  *            @arg  LED4
+  */
+void BSP_LED_Toggle(Led_TypeDef Led)
+{
+  if (Led <= LED4)
+  {
+     HAL_GPIO_TogglePin(GPIO_PORT[Led], GPIO_PIN[Led]);
+  }
+}
+
+/**
+  * @brief  Configures button GPIO and EXTI Line.
+  * @param  Button: Button to be configured
+  *          This parameter can be one of the following values:
+  *            @arg  BUTTON_WAKEUP: Wakeup Push Button
+  *            @arg  BUTTON_USER: User Push Button
+  * @param  Button_Mode: Button mode
+  *          This parameter can be one of the following values:
+  *            @arg  BUTTON_MODE_GPIO: Button will be used as simple IO
+  *            @arg  BUTTON_MODE_EXTI: Button will be connected to EXTI line
+  *                                    with interrupt generation capability
+  */
+void BSP_PB_Init(Button_TypeDef Button, ButtonMode_TypeDef Button_Mode)
+{
+  GPIO_InitTypeDef gpio_init_structure;
+
+  /* Enable the BUTTON clock */
+  BUTTON_GPIO_CLK_ENABLE();
+
+  if(Button_Mode == BUTTON_MODE_GPIO)
+  {
+    /* Configure Button pin as input */
+    gpio_init_structure.Pin = BUTTON_PIN[Button];
+    gpio_init_structure.Mode = GPIO_MODE_INPUT;
+    gpio_init_structure.Pull = GPIO_NOPULL;
+    gpio_init_structure.Speed = GPIO_SPEED_FAST;
+    HAL_GPIO_Init(BUTTON_PORT[Button], &gpio_init_structure);
+  }
+
+  if(Button_Mode == BUTTON_MODE_EXTI)
+  {
+    /* Configure Button pin as input with External interrupt */
+    gpio_init_structure.Pin = BUTTON_PIN[Button];
+    gpio_init_structure.Pull = GPIO_NOPULL;
+    gpio_init_structure.Speed = GPIO_SPEED_FAST;
+
+    gpio_init_structure.Mode = GPIO_MODE_IT_RISING;
+
+    HAL_GPIO_Init(BUTTON_PORT[Button], &gpio_init_structure);
+
+    /* Enable and set Button EXTI Interrupt to the lowest priority */
+    HAL_NVIC_SetPriority((IRQn_Type)(BUTTON_IRQn[Button]), 0x0F, 0x00);
+    HAL_NVIC_EnableIRQ((IRQn_Type)(BUTTON_IRQn[Button]));
+  }
+}
+
+/**
+  * @brief  Push Button DeInit.
+  * @param  Button: Button to be configured
+  *          This parameter can be one of the following values:
+  *            @arg  BUTTON_WAKEUP: Wakeup Push Button
+  *            @arg  BUTTON_USER: User Push Button
+  * @note PB DeInit does not disable the GPIO clock
+  */
+void BSP_PB_DeInit(Button_TypeDef Button)
+{
+    GPIO_InitTypeDef gpio_init_structure;
+
+    gpio_init_structure.Pin = BUTTON_PIN[Button];
+    HAL_NVIC_DisableIRQ((IRQn_Type)(BUTTON_IRQn[Button]));
+    HAL_GPIO_DeInit(BUTTON_PORT[Button], gpio_init_structure.Pin);
+}
+
+
+/**
+  * @brief  Returns the selected button state.
+  * @param  Button: Button to be checked
+  *          This parameter can be one of the following values:
+  *            @arg  BUTTON_WAKEUP: Wakeup Push Button
+  *            @arg  BUTTON_USER: User Push Button
+  * @retval The Button GPIO pin value
+  */
+uint32_t BSP_PB_GetState(Button_TypeDef Button)
+{
+  return HAL_GPIO_ReadPin(BUTTON_PORT[Button], BUTTON_PIN[Button]);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup STM32469I_Discovery_LOW_LEVEL_Private_Functions STM32469I Discovery LOW LEVEL Private Functions
+  * @{
+  */
+
+
+/*******************************************************************************
+                            BUS OPERATIONS
+*******************************************************************************/
+
+/******************************* I2C Routines *********************************/
+/**
+  * @brief  Initializes I2C MSP.
+  */
+static void I2C1_MspInit(void)
+{
+  GPIO_InitTypeDef  gpio_init_structure;
+
+  /*** Configure the GPIOs ***/
+  /* Enable GPIO clock */
+  DISCO_I2C1_SCL_SDA_GPIO_CLK_ENABLE();
+
+#if defined(USE_STM32469I_DISCO_REVC)
+  /* Perform 10 pulses on SCL to unlock I2C devices if previous I2C transaction aborted.*/
+  /* This configuration is needed with STM32F469i Disco RevC when using touch screen controller FT6336U */
+  gpio_init_structure.Pin = DISCO_I2C1_SCL_PIN;
+  gpio_init_structure.Mode = GPIO_MODE_OUTPUT_OD;
+  gpio_init_structure.Pull = GPIO_NOPULL;
+  gpio_init_structure.Speed = GPIO_SPEED_FAST;
+  gpio_init_structure.Alternate = 0;
+  HAL_GPIO_Init( DISCO_I2C1_SCL_SDA_GPIO_PORT, &gpio_init_structure );
+  for(uint8_t count = 10; count > 0; count-- )
+  {
+    HAL_GPIO_WritePin( DISCO_I2C1_SCL_SDA_GPIO_PORT, DISCO_I2C1_SCL_PIN, GPIO_PIN_SET );
+    HAL_Delay(1);
+    HAL_GPIO_WritePin( DISCO_I2C1_SCL_SDA_GPIO_PORT, DISCO_I2C1_SCL_PIN, GPIO_PIN_RESET );
+    HAL_Delay(1);
+  }
+#endif /* USE_STM32469I_DISCO_REVC */
+
+  /* Configure I2C Tx as alternate function */
+  gpio_init_structure.Pin = DISCO_I2C1_SCL_PIN;
+  gpio_init_structure.Mode = GPIO_MODE_AF_OD;
+  gpio_init_structure.Pull = GPIO_NOPULL;
+  gpio_init_structure.Speed = GPIO_SPEED_FAST;
+  gpio_init_structure.Alternate = DISCO_I2C1_SCL_SDA_AF;
+  HAL_GPIO_Init(DISCO_I2C1_SCL_SDA_GPIO_PORT, &gpio_init_structure);
+
+  /* Configure I2C Rx as alternate function */
+  gpio_init_structure.Pin = DISCO_I2C1_SDA_PIN;
+  HAL_GPIO_Init(DISCO_I2C1_SCL_SDA_GPIO_PORT, &gpio_init_structure);
+
+  /*** Configure the I2C peripheral ***/
+  /* Enable I2C clock */
+  DISCO_I2C1_CLK_ENABLE();
+
+  /* Force the I2C peripheral clock reset */
+  DISCO_I2C1_FORCE_RESET();
+
+  /* Release the I2C peripheral clock reset */
+  DISCO_I2C1_RELEASE_RESET();
+
+  /* Enable and set I2C1 Interrupt to a lower priority */
+  HAL_NVIC_SetPriority(DISCO_I2C1_EV_IRQn, 0x05, 0);
+  HAL_NVIC_EnableIRQ(DISCO_I2C1_EV_IRQn);
+
+  /* Enable and set I2C1 Interrupt to a lower priority */
+  HAL_NVIC_SetPriority(DISCO_I2C1_ER_IRQn, 0x05, 0);
+  HAL_NVIC_EnableIRQ(DISCO_I2C1_ER_IRQn);
+}
+
+/**
+  * @brief  Initializes I2C MSP.
+  */
+static void I2C2_MspInit(void)
+{
+  GPIO_InitTypeDef  gpio_init_structure;
+
+  /*** Configure the GPIOs ***/
+  /* Enable GPIO clock */
+  DISCO_I2C2_SCL_SDA_GPIO_CLK_ENABLE();
+
+  /* Configure I2C Tx as alternate function */
+  gpio_init_structure.Pin = DISCO_I2C2_SCL_PIN;
+  gpio_init_structure.Mode = GPIO_MODE_AF_OD;
+  gpio_init_structure.Pull = GPIO_NOPULL;
+  gpio_init_structure.Speed = GPIO_SPEED_FAST;
+  gpio_init_structure.Alternate = DISCO_I2C2_SCL_SDA_AF;
+  HAL_GPIO_Init(DISCO_I2C2_SCL_SDA_GPIO_PORT, &gpio_init_structure);
+
+  /* Configure I2C Rx as alternate function */
+  gpio_init_structure.Pin = DISCO_I2C2_SDA_PIN;
+  HAL_GPIO_Init(DISCO_I2C2_SCL_SDA_GPIO_PORT, &gpio_init_structure);
+
+  /*** Configure the I2C peripheral ***/
+  /* Enable I2C clock */
+  DISCO_I2C2_CLK_ENABLE();
+
+  /* Force the I2C peripheral clock reset */
+  DISCO_I2C2_FORCE_RESET();
+
+  /* Release the I2C peripheral clock reset */
+  DISCO_I2C2_RELEASE_RESET();
+
+  /* Enable and set I2C1 Interrupt to a lower priority */
+  HAL_NVIC_SetPriority(DISCO_I2C2_EV_IRQn, 0x05, 0);
+  HAL_NVIC_EnableIRQ(DISCO_I2C2_EV_IRQn);
+
+  /* Enable and set I2C1 Interrupt to a lower priority */
+  HAL_NVIC_SetPriority(DISCO_I2C2_ER_IRQn, 0x05, 0);
+  HAL_NVIC_EnableIRQ(DISCO_I2C2_ER_IRQn);
+}
+
+/**
+  * @brief  Initializes I2C HAL.
+  */
+static void I2C1_Init(void)
+{
+  if(HAL_I2C_GetState(&heval_I2c1) == HAL_I2C_STATE_RESET)
+  {
+    heval_I2c1.Instance = I2C1;
+    heval_I2c1.Init.ClockSpeed      = I2C1_SCL_FREQ_KHZ;
+    heval_I2c1.Init.DutyCycle       = I2C_DUTYCYCLE_2;
+    heval_I2c1.Init.OwnAddress1     = 0;
+    heval_I2c1.Init.AddressingMode  = I2C_ADDRESSINGMODE_7BIT;
+    heval_I2c1.Init.DualAddressMode = I2C_DUALADDRESS_DISABLE;
+    heval_I2c1.Init.OwnAddress2     = 0;
+    heval_I2c1.Init.GeneralCallMode = I2C_GENERALCALL_DISABLE;
+    heval_I2c1.Init.NoStretchMode   = I2C_NOSTRETCH_DISABLE;
+
+    /* Init the I2C */
+    I2C1_MspInit();
+    HAL_I2C_Init(&heval_I2c1);
+  }
+}
+
+/**
+  * @brief  Initializes I2C HAL.
+  */
+static void I2C2_Init(void)
+{
+  if(HAL_I2C_GetState(&heval_I2c2) == HAL_I2C_STATE_RESET)
+  {
+    heval_I2c2.Instance = I2C2;
+    heval_I2c2.Init.ClockSpeed      = I2C2_SCL_FREQ_KHZ;
+    heval_I2c2.Init.DutyCycle       = I2C_DUTYCYCLE_2;
+    heval_I2c2.Init.OwnAddress1     = 0;
+    heval_I2c2.Init.AddressingMode  = I2C_ADDRESSINGMODE_7BIT;
+    heval_I2c2.Init.DualAddressMode = I2C_DUALADDRESS_DISABLE;
+    heval_I2c2.Init.OwnAddress2     = 0;
+    heval_I2c2.Init.GeneralCallMode = I2C_GENERALCALL_DISABLE;
+    heval_I2c2.Init.NoStretchMode   = I2C_NOSTRETCH_DISABLE;
+
+    /* Init the I2C */
+    I2C2_MspInit();
+    HAL_I2C_Init(&heval_I2c2);
+  }
+}
+
+/**
+  * @brief  Writes a single data.
+  * @param  Addr: I2C address
+  * @param  Reg: Register address
+  * @param  Value: Data to be written
+  */
+static void I2C1_Write(uint8_t Addr, uint8_t Reg, uint8_t Value)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  status = HAL_I2C_Mem_Write(&heval_I2c1,
+                         Addr,
+                         (uint16_t)Reg,
+                         I2C_MEMADD_SIZE_8BIT,
+                         &Value,
+                         1,
+                         100);
+
+  /* Check the communication status */
+  if(status != HAL_OK)
+  {
+    /* Execute user timeout callback */
+    I2C1_Error(Addr);
+  }
+}
+
+/**
+  * @brief  Reads a single data.
+  * @param  Addr: I2C address
+  * @param  Reg: Register address
+  * @retval Read data
+  */
+static uint8_t I2C1_Read(uint8_t Addr, uint8_t Reg)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  uint8_t Value = 0;
+
+  status = HAL_I2C_Mem_Read(&heval_I2c1,
+                        Addr,
+                        Reg,
+                        I2C_MEMADD_SIZE_8BIT,
+                        &Value,
+                        1,
+                        1000);
+
+  /* Check the communication status */
+  if(status != HAL_OK)
+  {
+    /* Execute user timeout callback */
+    I2C1_Error(Addr);
+  }
+  return Value;
+}
+
+/**
+  * @brief  Reads multiple data.
+  * @param  Addr: I2C address
+  * @param  Reg: Reg address
+  * @param  MemAddress: memory address
+  * @param  Buffer: Pointer to data buffer
+  * @param  Length: Length of the data
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef I2C1_ReadMultiple(uint8_t Addr,
+                                       uint16_t Reg,
+                                       uint16_t MemAddress,
+                                       uint8_t *Buffer,
+                                       uint16_t Length)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  status = HAL_I2C_Mem_Read(&heval_I2c1,
+                        Addr,
+                        (uint16_t)Reg,
+                        MemAddress,
+                        Buffer,
+                        Length,
+                        1000);
+
+  /* Check the communication status */
+  if(status != HAL_OK)
+  {
+    /* I2C error occured */
+    I2C1_Error(Addr);
+  }
+  return status;
+}
+
+static HAL_StatusTypeDef I2C2_ReadMultiple(uint8_t Addr,
+                                       uint16_t Reg,
+                                       uint16_t MemAddress,
+                                       uint8_t *Buffer,
+                                       uint16_t Length)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  status = HAL_I2C_Mem_Read(&heval_I2c2,
+                        Addr,
+                        (uint16_t)Reg,
+                        MemAddress,
+                        Buffer,
+                        Length,
+                        1000);
+
+  /* Check the communication status */
+  if(status != HAL_OK)
+  {
+    /* I2C2 error occured */
+    I2C2_Error(Addr);
+  }
+  return status;
+}
+
+/**
+  * @brief  Writes a value in a register of the device through BUS in using DMA mode.
+  * @param  Addr: Device address on BUS Bus.
+  * @param  Reg: The target register address to write
+  * @param  MemAddress: memory address
+  * @param  Buffer: The target register value to be written
+  * @param  Length: buffer size to be written
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef I2C1_WriteMultiple(uint8_t Addr,
+                                        uint16_t Reg,
+                                        uint16_t MemAddress,
+                                        uint8_t *Buffer,
+                                        uint16_t Length)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  status = HAL_I2C_Mem_Write(&heval_I2c1,
+                         Addr,
+                         (uint16_t)Reg,
+                         MemAddress,
+                         Buffer,
+                         Length,
+                         1000);
+
+  /* Check the communication status */
+  if(status != HAL_OK)
+  {
+    /* Re-Initiaize the I2C Bus */
+    I2C1_Error(Addr);
+  }
+  return status;
+}
+
+static HAL_StatusTypeDef I2C2_WriteMultiple(uint8_t Addr,
+                                        uint16_t Reg,
+                                        uint16_t MemAddress,
+                                        uint8_t *Buffer,
+                                        uint16_t Length)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  status = HAL_I2C_Mem_Write(&heval_I2c2,
+                         Addr,
+                         (uint16_t)Reg,
+                         MemAddress,
+                         Buffer,
+                         Length,
+                         1000);
+
+  /* Check the communication status */
+  if(status != HAL_OK)
+  {
+    /* Re-Initiaize the I2C2 Bus */
+    I2C2_Error(Addr);
+  }
+  return status;
+}
+
+/**
+  * @brief  Checks if target device is ready for communication.
+  * @note   This function is used with Memory devices
+  * @param  DevAddress: Target device address
+  * @param  Trials: Number of trials
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef I2C1_IsDeviceReady(uint16_t DevAddress, uint32_t Trials)
+{
+  return (HAL_I2C_IsDeviceReady(&heval_I2c1, DevAddress, Trials, 1000));
+}
+
+/**
+  * @brief  Manages error callback by re-initializing I2C.
+  * @param  Addr: I2C Address
+  */
+static void I2C1_Error(uint8_t Addr)
+{
+  /* De-initialize the I2C comunication bus */
+  HAL_I2C_DeInit(&heval_I2c1);
+
+  /* Re-Initiaize the I2C comunication bus */
+  I2C1_Init();
+}
+
+static void I2C2_Error(uint8_t Addr)
+{
+  /* De-initialize the I2C2 comunication bus */
+  HAL_I2C_DeInit(&heval_I2c2);
+
+  /* Re-Initiaize the I2C2 comunication bus */
+  I2C2_Init();
+}
+
+/**
+  * @}
+  */
+
+/*******************************************************************************
+                            LINK OPERATIONS
+*******************************************************************************/
+
+/********************************* LINK AUDIO *********************************/
+
+/**
+  * @brief  Initializes Audio low level.
+  */
+void AUDIO_IO_Init(void)
+{
+  I2C2_Init();
+}
+
+/**
+  * @brief  DeInitializes Audio low level.
+  */
+void AUDIO_IO_DeInit(void)
+{
+
+}
+
+/**
+  * @brief  Writes a single data.
+  * @param  Addr: I2C address
+  * @param  Reg: Reg address
+  * @param  Value: Data to be written
+  */
+void AUDIO_IO_Write(uint8_t Addr, uint8_t Reg, uint8_t Value)
+{
+  I2C2_WriteMultiple(Addr, (uint16_t) Reg, I2C_MEMADD_SIZE_8BIT, (uint8_t*)&Value, 1);
+}
+
+/**
+  * @brief  Reads a single data.
+  * @param  Addr: I2C address
+  * @param  Reg: Reg address
+  * @retval Data to be read
+  */
+uint8_t AUDIO_IO_Read(uint8_t Addr, uint8_t Reg)
+{
+  uint8_t read_value = 0;
+
+  I2C2_ReadMultiple(Addr, (uint16_t) Reg, I2C_MEMADD_SIZE_8BIT, (uint8_t*)&read_value, 1);
+
+  return read_value;
+}
+
+/**
+  * @brief  AUDIO Codec delay
+  * @param  Delay: Delay in ms
+  */
+void AUDIO_IO_Delay(uint32_t Delay)
+{
+  HAL_Delay(Delay);
+}
+
+/******************************** LINK I2C EEPROM *****************************/
+
+/**
+  * @brief  Initializes peripherals used by the I2C EEPROM driver.
+  */
+void EEPROM_IO_Init(void)
+{
+  I2C1_Init();
+}
+
+/**
+  * @brief  Write data to I2C EEPROM driver in using DMA channel.
+  * @param  DevAddress: Target device address
+  * @param  MemAddress: Internal memory address
+  * @param  pBuffer: Pointer to data buffer
+  * @param  BufferSize: Amount of data to be sent
+  * @retval HAL status
+  */
+HAL_StatusTypeDef EEPROM_IO_WriteData(uint16_t DevAddress, uint16_t MemAddress, uint8_t* pBuffer, uint32_t BufferSize)
+{
+  return (I2C1_WriteMultiple(DevAddress, MemAddress, I2C_MEMADD_SIZE_16BIT, pBuffer, BufferSize));
+}
+
+/**
+  * @brief  Read data from I2C EEPROM driver in using DMA channel.
+  * @param  DevAddress: Target device address
+  * @param  MemAddress: Internal memory address
+  * @param  pBuffer: Pointer to data buffer
+  * @param  BufferSize: Amount of data to be read
+  * @retval HAL status
+  */
+HAL_StatusTypeDef EEPROM_IO_ReadData(uint16_t DevAddress, uint16_t MemAddress, uint8_t* pBuffer, uint32_t BufferSize)
+{
+  return (I2C1_ReadMultiple(DevAddress, MemAddress, I2C_MEMADD_SIZE_16BIT, pBuffer, BufferSize));
+}
+
+/**
+  * @brief  Checks if target device is ready for communication.
+  * @note   This function is used with Memory devices
+  * @param  DevAddress: Target device address
+  * @param  Trials: Number of trials
+  * @retval HAL status
+  */
+HAL_StatusTypeDef EEPROM_IO_IsDeviceReady(uint16_t DevAddress, uint32_t Trials)
+{
+  return (I2C1_IsDeviceReady(DevAddress, Trials));
+}
+
+/******************************** LINK TS (TouchScreen) ***********************/
+
+/**
+  * @brief  Initialize I2C communication
+  *         channel from MCU to TouchScreen (TS).
+  */
+void TS_IO_Init(void)
+{
+  I2C1_Init();
+}
+
+/**
+  * @brief  Writes single data with I2C communication
+  *         channel from MCU to TouchScreen.
+  * @param  Addr: I2C address
+  * @param  Reg: Register address
+  * @param  Value: Data to be written
+  */
+void TS_IO_Write(uint8_t Addr, uint8_t Reg, uint8_t Value)
+{
+  I2C1_Write(Addr, Reg, Value);
+}
+
+/**
+  * @brief  Reads single data with I2C communication
+  *         channel from TouchScreen.
+  * @param  Addr: I2C address
+  * @param  Reg: Register address
+  * @retval Read data
+  */
+uint8_t TS_IO_Read(uint8_t Addr, uint8_t Reg)
+{
+  return I2C1_Read(Addr, Reg);
+}
+
+/**
+  * @brief  Reads multiple data with I2C communication
+  *         channel from TouchScreen.
+  * @param  Addr: I2C address
+  * @param  Reg: Register address
+  * @param  Buffer: Pointer to data buffer
+  * @param  Length: Length of the data
+  * @retval Number of read data
+  */
+uint16_t TS_IO_ReadMultiple(uint8_t Addr, uint8_t Reg, uint8_t *Buffer, uint16_t Length)
+{
+ return I2C1_ReadMultiple(Addr, (uint16_t)Reg, I2C_MEMADD_SIZE_8BIT, Buffer, Length);
+}
+
+/**
+  * @brief  Writes multiple data with I2C communication
+  *         channel from MCU to TouchScreen.
+  * @param  Addr: I2C address
+  * @param  Reg: Register address
+  * @param  Buffer: Pointer to data buffer
+  * @param  Length: Length of the data
+  */
+void TS_IO_WriteMultiple(uint8_t Addr, uint8_t Reg, uint8_t *Buffer, uint16_t Length)
+{
+  I2C1_WriteMultiple(Addr, (uint16_t)Reg, I2C_MEMADD_SIZE_8BIT, Buffer, Length);
+}
+
+/**
+  * @brief  Delay function used in TouchScreen low level driver.
+  * @param  Delay: Delay in ms
+  */
+void TS_IO_Delay(uint32_t Delay)
+{
+  HAL_Delay(Delay);
+}
+
+/**************************** LINK OTM8009A (Display driver) ******************/
+/**
+  * @brief  OTM8009A delay
+  * @param  Delay: Delay in ms
+  */
+void OTM8009A_IO_Delay(uint32_t Delay)
+{
+  HAL_Delay(Delay);
+}
+
+/**************************** LINK NT35510 (Display driver) ******************/
+/**
+  * @brief  NT35510 delay
+  * @param  Delay: Delay in ms
+  */
+void NT35510_IO_Delay(uint32_t Delay)
+{
+  HAL_Delay(Delay);
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
diff --git a/Drivers/BSP/STM32469I-Discovery/stm32469i_discovery.h b/Drivers/BSP/STM32469I-Discovery/stm32469i_discovery.h
new file mode 100644
index 0000000..6fa79ca
--- /dev/null
+++ b/Drivers/BSP/STM32469I-Discovery/stm32469i_discovery.h
@@ -0,0 +1,362 @@
+/**
+  ******************************************************************************
+  * @file    stm32469i_discovery.h
+  * @author  MCD Application Team
+  * @brief   This file contains definitions for STM32469I-Discovery LEDs,
+  *          push-buttons hardware resources.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* IMPORTANT: One of the following flags must be defined in the preprocessor */
+/* options in order to select the target board revision: !!!!!!!!!! */
+/* USE_STM32469I_DISCO_REVA */
+/* USE_STM32469I_DISCO_REVB */
+/* USE_STM32469I_DISCO_REVC */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32469I_DISCOVERY_H
+#define __STM32469I_DISCOVERY_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+
+ /* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal.h"
+
+/** @addtogroup BSP
+  * @{
+  */
+
+/** @addtogroup STM32469I_Discovery
+  * @{
+  */
+
+/** @addtogroup STM32469I_Discovery_LOW_LEVEL 
+  * @{
+  */
+
+/** @defgroup STM32469I_Discovery_LOW_LEVEL_Exported_Types STM32469I Discovery LOW LEVEL Exported Types
+ * @{
+ */
+
+/** @brief Led_TypeDef
+  *  STM32469I_Discovery board leds definitions.
+  */
+typedef enum
+{
+ LED1 = 0,
+ LED_GREEN = LED1,
+ LED2 = 1,
+ LED_ORANGE = LED2,
+ LED3 = 2,
+ LED_RED = LED3,
+ LED4 = 3,
+ LED_BLUE = LED4
+
+} Led_TypeDef;
+
+/** @brief Button_TypeDef
+  *  STM32469I_Discovery board Buttons definitions.
+  */
+typedef enum
+{
+  BUTTON_WAKEUP = 0
+} Button_TypeDef;
+
+#define BUTTON_USER BUTTON_WAKEUP
+
+/** @brief ButtonMode_TypeDef
+  *  STM32469I_Discovery board Buttons Modes definitions.
+  */
+typedef enum
+{
+ BUTTON_MODE_GPIO = 0,
+ BUTTON_MODE_EXTI = 1
+
+} ButtonMode_TypeDef;
+
+/** @addtogroup Exported_types
+  * @{
+  */ 
+typedef enum 
+{
+  PB_SET = 0, 
+  PB_RESET = !PB_SET
+} ButtonValue_TypeDef;
+
+
+/** @brief DISCO_Status_TypeDef
+  *  STM32469I_DISCO board Status return possible values.
+  */
+typedef enum
+{
+ DISCO_OK    = 0,
+ DISCO_ERROR = 1
+
+} DISCO_Status_TypeDef;
+
+/**
+  * @}
+  */
+  
+/**
+  * @}
+  */
+
+/** @defgroup STM32469I_Discovery_LOW_LEVEL_Exported_Constants STM32469I Discovery LOW LEVEL Exported Constants
+  * @{
+  */
+
+
+/** @defgroup STM32469I_Discovery_LOW_LEVEL_LED STM32469I Discovery LOW LEVEL LED
+  * @{
+  */
+/* Always four leds for all revisions of Discovery boards */
+#define LEDn                             ((uint8_t)4)
+
+
+/* 4 Leds are connected to MCU directly on PG6, PD4, PD5, PK3 */
+#define LED1_GPIO_PORT                   ((GPIO_TypeDef*)GPIOG)
+#define LED2_GPIO_PORT                   ((GPIO_TypeDef*)GPIOD)
+#define LED3_GPIO_PORT                   ((GPIO_TypeDef*)GPIOD)
+#define LED4_GPIO_PORT                   ((GPIO_TypeDef*)GPIOK)
+
+#define LED1_GPIO_CLK_ENABLE()           __HAL_RCC_GPIOG_CLK_ENABLE()
+#define LED1_GPIO_CLK_DISABLE()          __HAL_RCC_GPIOG_CLK_DISABLE()
+#define LED2_GPIO_CLK_ENABLE()           __HAL_RCC_GPIOD_CLK_ENABLE()
+#define LED2_GPIO_CLK_DISABLE()          __HAL_RCC_GPIOD_CLK_DISABLE()
+#define LED3_GPIO_CLK_ENABLE()           __HAL_RCC_GPIOD_CLK_ENABLE()
+#define LED3_GPIO_CLK_DISABLE()          __HAL_RCC_GPIOD_CLK_DISABLE()
+#define LED4_GPIO_CLK_ENABLE()           __HAL_RCC_GPIOK_CLK_ENABLE()
+#define LED4_GPIO_CLK_DISABLE()          __HAL_RCC_GPIOK_CLK_DISABLE()
+
+#define LED1_PIN                         ((uint32_t)GPIO_PIN_6)
+#define LED2_PIN                         ((uint32_t)GPIO_PIN_4)
+#define LED3_PIN                         ((uint32_t)GPIO_PIN_5)
+#define LED4_PIN                         ((uint32_t)GPIO_PIN_3)
+/**
+  * @}
+  */
+
+/** @addtogroup STM32469I_Discovery_LOW_LEVEL_BUTTON STM32469I Discovery LOW LEVEL BUTTON
+  * @{
+  */
+/* Only one User/Wakeup button */
+#define BUTTONn                             ((uint8_t)1)
+
+/**
+  * @brief Wakeup push-button
+  */
+#define WAKEUP_BUTTON_PIN                   GPIO_PIN_0
+#define WAKEUP_BUTTON_GPIO_PORT             GPIOA
+#define WAKEUP_BUTTON_GPIO_CLK_ENABLE()     __HAL_RCC_GPIOA_CLK_ENABLE()
+#define WAKEUP_BUTTON_GPIO_CLK_DISABLE()    __HAL_RCC_GPIOA_CLK_DISABLE()
+#define WAKEUP_BUTTON_EXTI_IRQn             EXTI0_IRQn
+
+/* Define the USER button as an alias of the Wakeup button */
+#define USER_BUTTON_PIN                   WAKEUP_BUTTON_PIN
+#define USER_BUTTON_GPIO_PORT             WAKEUP_BUTTON_GPIO_PORT
+#define USER_BUTTON_GPIO_CLK_ENABLE()     WAKEUP_BUTTON_GPIO_CLK_ENABLE()
+#define USER_BUTTON_GPIO_CLK_DISABLE()    WAKEUP_BUTTON_GPIO_CLK_DISABLE()
+#define USER_BUTTON_EXTI_IRQn             WAKEUP_BUTTON_EXTI_IRQn
+
+#define BUTTON_GPIO_CLK_ENABLE()            __HAL_RCC_GPIOA_CLK_ENABLE()
+
+/**
+  * @}
+  */
+
+/**
+  * @brief OTG_FS1 OVER_CURRENT and POWER_SWITCH Pins definition
+  */
+#define AUDIO_INT_PIN                  GPIO_PIN_7
+#define AUDIO_INT_PORT                 GPIOB
+#define AUDIO_INT_PORT_CLK_ENABLE()     __HAL_RCC_GPIOB_CLK_ENABLE()
+
+#define OTG_FS1_OVER_CURRENT_PIN                  GPIO_PIN_7
+#define OTG_FS1_OVER_CURRENT_PORT                 GPIOB
+#define OTG_FS1_OVER_CURRENT_PORT_CLK_ENABLE()     __HAL_RCC_GPIOB_CLK_ENABLE()
+
+#define OTG_FS1_POWER_SWITCH_PIN                  GPIO_PIN_2
+#define OTG_FS1_POWER_SWITCH_PORT                 GPIOB
+#define OTG_FS1_POWER_SWITCH_PORT_CLK_ENABLE()     __HAL_RCC_GPIOB_CLK_ENABLE()
+
+/**
+  * @brief SD-detect signal
+  */
+#define SD_DETECT_PIN                        ((uint32_t)GPIO_PIN_2)
+#define SD_DETECT_GPIO_PORT                  ((GPIO_TypeDef*)GPIOG)
+#define SD_DETECT_GPIO_CLK_ENABLE()          __HAL_RCC_GPIOG_CLK_ENABLE()
+#define SD_DETECT_GPIO_CLK_DISABLE()         __HAL_RCC_GPIOG_CLK_DISABLE()
+#define SD_DETECT_EXTI_IRQn                  EXTI2_IRQn
+
+/**
+  * @brief TS_INT signal from TouchScreen when it is configured in interrupt mode
+  */
+#define TS_INT_PIN                        ((uint32_t)GPIO_PIN_5)
+#define TS_INT_GPIO_PORT                  ((GPIO_TypeDef*)GPIOJ)
+#define TS_INT_GPIO_CLK_ENABLE()          __HAL_RCC_GPIOJ_CLK_ENABLE()
+#define TS_INT_GPIO_CLK_DISABLE()         __HAL_RCC_GPIOJ_CLK_DISABLE()
+#define TS_INT_EXTI_IRQn                  EXTI9_5_IRQn
+
+/**
+  * @brief TouchScreen FT6206 Slave I2C address 1
+  */
+#define TS_I2C_ADDRESS                   ((uint16_t)0x54)
+
+/**
+  * @brief TouchScreen FT6336G Slave I2C address 2
+  */
+#define TS_I2C_ADDRESS_A02               ((uint16_t)0x70)
+
+
+/**
+  * @brief Audio I2C Slave address
+  */
+#define AUDIO_I2C_ADDRESS                ((uint16_t)0x94)
+
+/**
+  * @brief EEPROM I2C Slave address 1
+  */
+#define EEPROM_I2C_ADDRESS_A01           ((uint16_t)0xA0)
+
+/**
+  * @brief EEPROM I2C Slave address 2
+  */
+#define EEPROM_I2C_ADDRESS_A02           ((uint16_t)0xA6)
+
+/**
+  * @brief I2C clock speed configuration (in Hz)
+  * WARNING:
+  * Make sure that this define is not already declared in other files
+  * It can be used in parallel by other modules.
+  */
+#ifndef I2C1_SCL_FREQ_KHZ
+#define I2C1_SCL_FREQ_KHZ                  400000 /*!< f(I2C_SCL) = 400 kHz */
+#endif /* I2C1_SCL_FREQ_KHZ */
+
+/**
+  * @brief User can use this section to tailor I2C1/I2C1 instance used and associated
+  * resources.
+  * Definition for I2C1 clock resources
+  */
+#define DISCO_I2C1                             I2C1
+#define DISCO_I2C1_CLK_ENABLE()                __HAL_RCC_I2C1_CLK_ENABLE()
+#define DISCO_DMAx_CLK_ENABLE()                __HAL_RCC_DMA1_CLK_ENABLE()
+#define DISCO_I2C1_SCL_SDA_GPIO_CLK_ENABLE()   __HAL_RCC_GPIOB_CLK_ENABLE()
+
+#define DISCO_I2C1_FORCE_RESET()               __HAL_RCC_I2C1_FORCE_RESET()
+#define DISCO_I2C1_RELEASE_RESET()             __HAL_RCC_I2C1_RELEASE_RESET()
+
+/** @brief Definition for I2C1 Pins
+  */
+#define DISCO_I2C1_SCL_PIN                     GPIO_PIN_8 /*!< PB8 */
+#define DISCO_I2C1_SCL_SDA_GPIO_PORT           GPIOB
+#define DISCO_I2C1_SCL_SDA_AF                  GPIO_AF4_I2C1
+#define DISCO_I2C1_SDA_PIN                     GPIO_PIN_9 /*!< PB9 */
+
+/** @brief Definition of I2C interrupt requests
+  */
+#define DISCO_I2C1_EV_IRQn                     I2C1_EV_IRQn
+#define DISCO_I2C1_ER_IRQn                     I2C1_ER_IRQn
+
+
+
+/**
+  * @brief I2C2 clock speed configuration (in Hz)
+  * WARNING:
+  * Make sure that this define is not already declared in other files
+  * It can be used in parallel by other modules.
+  */
+#ifndef I2C2_SCL_FREQ_KHZ
+#define I2C2_SCL_FREQ_KHZ                  100000 /*!< f(I2C2_SCL) < 100 kHz */
+#endif /* I2C2_SCL_FREQ_KHZ */
+
+/**
+  * @brief User can use this section to tailor I2C2/I2C2 instance used and associated
+  * resources (audio codec).
+  * Definition for I2C2 clock resources
+  */
+#define DISCO_I2C2                             I2C2
+#define DISCO_I2C2_CLK_ENABLE()                __HAL_RCC_I2C2_CLK_ENABLE()
+#define DISCO_I2C2_SCL_SDA_GPIO_CLK_ENABLE()   __HAL_RCC_GPIOH_CLK_ENABLE()
+
+#define DISCO_I2C2_FORCE_RESET()               __HAL_RCC_I2C2_FORCE_RESET()
+#define DISCO_I2C2_RELEASE_RESET()             __HAL_RCC_I2C2_RELEASE_RESET()
+
+/** @brief Definition for I2C2 Pins
+  */
+#define DISCO_I2C2_SCL_PIN                     GPIO_PIN_4 /*!< PH4 */
+#define DISCO_I2C2_SCL_SDA_GPIO_PORT           GPIOH
+#define DISCO_I2C2_SCL_SDA_AF                  GPIO_AF4_I2C2
+#define DISCO_I2C2_SDA_PIN                     GPIO_PIN_5 /*!< PH5 */
+
+/** @brief Definition of I2C2 interrupt requests
+  */
+#define DISCO_I2C2_EV_IRQn                     I2C2_EV_IRQn
+#define DISCO_I2C2_ER_IRQn                     I2C2_ER_IRQn
+
+#if !defined(USE_STM32469I_DISCO_REVA) && \
+    !defined(USE_STM32469I_DISCO_REVB) && \
+    !defined(USE_STM32469I_DISCO_REVC)
+#define USE_STM32469I_DISCO_REVC
+#endif
+
+/**
+  * @}
+  */
+
+/** @defgroup STM32469I_Discovery_LOW_LEVEL_Exported_Macros STM32469I Discovery LOW LEVEL Exported Macros
+  * @{
+  */
+/**
+  * @}
+  */
+
+/** @defgroup STM32469I_Discovery_LOW_LEVEL_Exported_Functions STM32469I Discovery LOW LEVEL Exported Functions
+  * @{
+  */
+uint32_t         BSP_GetVersion(void);
+void             BSP_LED_Init(Led_TypeDef Led);
+void             BSP_LED_DeInit(Led_TypeDef Led);
+void             BSP_LED_On(Led_TypeDef Led);
+void             BSP_LED_Off(Led_TypeDef Led);
+void             BSP_LED_Toggle(Led_TypeDef Led);
+void             BSP_PB_Init(Button_TypeDef Button, ButtonMode_TypeDef Button_Mode);
+void             BSP_PB_DeInit(Button_TypeDef Button);
+uint32_t         BSP_PB_GetState(Button_TypeDef Button);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32469I_DISCOVERY_H */
diff --git a/Drivers/BSP/STM32469I-Discovery/stm32469i_discovery_audio.c b/Drivers/BSP/STM32469I-Discovery/stm32469i_discovery_audio.c
new file mode 100644
index 0000000..4522295
--- /dev/null
+++ b/Drivers/BSP/STM32469I-Discovery/stm32469i_discovery_audio.c
@@ -0,0 +1,1482 @@
+/**
+  ******************************************************************************
+  * @file    stm32469i_discovery_audio.c
+  * @author  MCD Application Team
+  * @version V2.0.0
+  * @date    27-January-2017
+  * @brief   This file provides the Audio driver for the STM32469I-Discovery board.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/*==============================================================================
+                                 User NOTES
+
+How To use this driver:
+-----------------------
+   + This driver supports STM32F4xx devices on STM32469I-Discovery (MB1189) Discovery boards.
+   + Call the function BSP_AUDIO_OUT_Init(
+                                    OutputDevice: physical output mode (OUTPUT_DEVICE_HEADPHONE1,
+                                                  OUTPUT_DEVICE_HEADPHONE2 or OUTPUT_DEVICE_BOTH)
+                                    Volume      : Initial volume to be set (0 is min (mute), 100 is max (100%)
+                                    AudioFreq   : Audio frequency in Hz (8000, 16000, 22500, 32000...)
+                                                  this parameter is relative to the audio file/stream type.
+                                   )
+      This function configures all the hardware required for the audio application (codec, I2C, SAI,
+      GPIOs, DMA and interrupt if needed). This function returns AUDIO_OK if configuration is OK.
+      If the returned value is different from AUDIO_OK or the function is stuck then the communication with
+      the codec or the MFX has failed (try to un-plug the power or reset device in this case).
+      - OUTPUT_DEVICE_HEADPHONE1 : only headphones 1 will be set as output for the audio stream.
+      - OUTPUT_DEVICE_HEADPHONE2 : only headphones 2 will be set as output for the audio stream.
+      - OUTPUT_DEVICE_BOTH       : both Headphones are used as outputs for the audio stream
+                                 at the same time.
+      Note. On STM32469I-Discovery SAI_DMA is configured in CIRCULAR mode. Due to this the application
+        does NOT need to call BSP_AUDIO_OUT_ChangeBuffer() to assure straming.
+   + Call the function BSP_Discovery_AUDIO_OUT_Play(
+                                  pBuffer: pointer to the audio data file address
+                                  Size   : size of the buffer to be sent in Bytes
+                                 )
+      to start playing (for the first time) from the audio file/stream.
+   + Call the function BSP_AUDIO_OUT_Pause() to pause playing
+   + Call the function BSP_AUDIO_OUT_Resume() to resume playing.
+       Note. After calling BSP_AUDIO_OUT_Pause() function for pause, only BSP_AUDIO_OUT_Resume() should be called
+          for resume (it is not allowed to call BSP_AUDIO_OUT_Play() in this case).
+       Note. This function should be called only when the audio file is played or paused (not stopped).
+   + For each mode, you may need to implement the relative callback functions into your code.
+      The Callback functions are named AUDIO_OUT_XXX_CallBack() and only their prototypes are declared in
+      the stm32469i_discovery_audio.h file. (refer to the example for more details on the callbacks implementations)
+   + To Stop playing, to modify the volume level, the frequency, the audio frame slot,
+      the device output mode the mute or the stop, use the functions: BSP_AUDIO_OUT_SetVolume(),
+      AUDIO_OUT_SetFrequency(), BSP_AUDIO_OUT_SetAudioFrameSlot(), BSP_AUDIO_OUT_SetOutputMode(),
+      BSP_AUDIO_OUT_SetMute() and BSP_AUDIO_OUT_Stop().
+   + The driver API and the callback functions are at the end of the stm32469i_discovery_audio.h file.
+
+Driver architecture:
+--------------------
+   + This driver provide the High Audio Layer: consists of the function API exported in the stm32469i_discovery_audio.h file
+     (BSP_AUDIO_OUT_Init(), BSP_AUDIO_OUT_Play() ...)
+   + This driver provide also the Media Access Layer (MAL): which consists of functions allowing to access the media containing/
+     providing the audio file/stream. These functions are also included as local functions into
+     the stm32469i_discovery_audio_codec.c file (I2Sx_Init(), I2Sx_DeInit(), SAIx_Init() and SAIx_DeInit())
+
+Known Limitations:
+------------------
+   1- If the TDM Format used to paly in parallel 2 audio Stream (the first Stream is configured in codec SLOT0 and second
+      Stream in SLOT1) the Pause/Resume, volume and mute feature will control the both streams.
+   2- Parsing of audio file is not implemented (in order to determine audio file properties: Mono/Stereo, Data size,
+      File size, Audio Frequency, Audio Data header size ...). The configuration is fixed for the given audio file.
+   3- Supports only Stereo audio streaming.
+   4- Supports only 16-bits audio data size.
+==============================================================================*/
+
+/* Includes ------------------------------------------------------------------*/
+#include <string.h>
+#include "stm32469i_discovery_audio.h"
+
+/** @addtogroup BSP
+  * @{
+  */
+
+/** @addtogroup STM32469I_Discovery
+  * @{
+  */
+
+/** @defgroup STM32469I-Discovery_AUDIO STM32469I Discovery AUDIO
+  * @brief This file includes the low layer driver for CS43L22 Audio Codec
+  *        available on STM32469I-Discovery board(MB1189).
+  * @{
+  */
+
+/** @defgroup STM32469I-Discovery_AUDIO_Private_Types STM32469I Discovery AUDIO Private Types
+  * @{
+  */
+/**
+  * @}
+  */
+
+/** @defgroup STM32469I-Discovery_AUDIO_Private_Defines STM32469I Discovery AUDIO Private Defines
+ *  @brief Headphone1 (CN27 of STM32469I-Discovery board) is connected to the
+ *         HEADPHONE output of CS43L22 Audio Codec.
+ *         Headphone2 (CN26 of STM32469I-Discovery board) is connected to the
+ *         SPEAKER output of CS43L22 Audio Codec.
+  * @{
+  */
+#define OUTPUT_DEVICE_HEADPHONE1 OUTPUT_DEVICE_HEADPHONE
+
+/* Headphone2 is connected to Speaker output of the CS43L22 codec */
+#define OUTPUT_DEVICE_HEADPHONE2 OUTPUT_DEVICE_SPEAKER
+/**
+  * @}
+  */
+
+/** @defgroup STM32469I-Discovery_AUDIO_Private_Macros STM32469I Discovery AUDIO Private macros
+  * @{
+  */
+
+/*### PLAY ###*/
+/* SCK(kHz) = SAI_CK_x/(SAIClockDivider*2*256) */
+#define SAIClockDivider(__FREQUENCY__) \
+        (__FREQUENCY__ == AUDIO_FREQUENCY_8K)  ? 12 \
+      : (__FREQUENCY__ == AUDIO_FREQUENCY_11K) ? 2 \
+      : (__FREQUENCY__ == AUDIO_FREQUENCY_16K) ? 6 \
+      : (__FREQUENCY__ == AUDIO_FREQUENCY_22K) ? 1 \
+      : (__FREQUENCY__ == AUDIO_FREQUENCY_32K) ? 3 \
+      : (__FREQUENCY__ == AUDIO_FREQUENCY_44K) ? 0 \
+      : (__FREQUENCY__ == AUDIO_FREQUENCY_48K) ? 2 : 1  \
+
+/**
+  * @}
+  */
+
+/** @defgroup STM32469I-Discovery_AUDIO_Private_Variables STM32469I Discovery AUDIO Private Variables
+  * @{
+  */
+  
+/*
+Note: 
+  these global variables are not compliant to naming rules (upper case without "_" ), 
+  but we keep this naming for compatibility, in fact these variables (not static)
+  could have been used by the application, example the stm32f4xx_it.c:
+    void DMA2_Stream6_IRQHandler(void)
+     {  HAL_DMA_IRQHandler(haudio_out_sai.hdmatx);  }
+*/
+AUDIO_DrvTypeDef          *audio_drv;
+SAI_HandleTypeDef         haudio_out_sai;
+I2S_HandleTypeDef         haudio_in_i2s;
+TIM_HandleTypeDef         haudio_tim;
+
+/* PDM filters params */
+PDM_Filter_Handler_t  PDM_FilterHandler[2];
+PDM_Filter_Config_t   PDM_FilterConfig[2];
+
+uint8_t Channel_Demux[128] = {
+    0x00, 0x01, 0x00, 0x01, 0x02, 0x03, 0x02, 0x03,
+    0x00, 0x01, 0x00, 0x01, 0x02, 0x03, 0x02, 0x03,
+    0x04, 0x05, 0x04, 0x05, 0x06, 0x07, 0x06, 0x07,
+    0x04, 0x05, 0x04, 0x05, 0x06, 0x07, 0x06, 0x07,
+    0x00, 0x01, 0x00, 0x01, 0x02, 0x03, 0x02, 0x03,
+    0x00, 0x01, 0x00, 0x01, 0x02, 0x03, 0x02, 0x03,
+    0x04, 0x05, 0x04, 0x05, 0x06, 0x07, 0x06, 0x07,
+    0x04, 0x05, 0x04, 0x05, 0x06, 0x07, 0x06, 0x07,
+    0x08, 0x09, 0x08, 0x09, 0x0a, 0x0b, 0x0a, 0x0b,
+    0x08, 0x09, 0x08, 0x09, 0x0a, 0x0b, 0x0a, 0x0b,
+    0x0c, 0x0d, 0x0c, 0x0d, 0x0e, 0x0f, 0x0e, 0x0f,
+    0x0c, 0x0d, 0x0c, 0x0d, 0x0e, 0x0f, 0x0e, 0x0f,
+    0x08, 0x09, 0x08, 0x09, 0x0a, 0x0b, 0x0a, 0x0b,
+    0x08, 0x09, 0x08, 0x09, 0x0a, 0x0b, 0x0a, 0x0b,
+    0x0c, 0x0d, 0x0c, 0x0d, 0x0e, 0x0f, 0x0e, 0x0f,
+    0x0c, 0x0d, 0x0c, 0x0d, 0x0e, 0x0f, 0x0e, 0x0f
+};
+
+uint16_t __IO AudioInVolume = DEFAULT_AUDIO_IN_VOLUME;
+
+/**
+  * @}
+  */
+
+/** @defgroup STM32469I-Discovery_AUDIO_Private_Function_Prototypes STM32469I Discovery AUDIO Private Prototypes
+  * @{
+  */
+static uint8_t SAIx_Init(uint32_t AudioFreq);
+static void SAIx_DeInit(void);
+static void I2Sx_Init(uint32_t AudioFreq);
+static void I2Sx_DeInit(void);
+static void TIMx_IC_MspInit(TIM_HandleTypeDef *htim);
+static void TIMx_IC_MspDeInit(TIM_HandleTypeDef *htim);
+static void TIMx_Init(void);
+static void TIMx_DeInit(void);
+static void PDMDecoder_Init(uint32_t AudioFreq, uint32_t ChnlNbrIn, uint32_t ChnlNbrOut);
+
+void BSP_AUDIO_OUT_ChangeAudioConfig(uint32_t AudioOutOption);
+
+/**
+  * @}
+  */
+
+/** @defgroup STM32469I-Discovery_AUDIO_out_Private_Functions STM32469I Discovery AUDIO OUT Private Functions
+  * @{
+  */
+
+/**
+  * @brief  Configures the audio peripherals.
+  * @param  OutputDevice: OUTPUT_DEVICE_SPEAKER, OUTPUT_DEVICE_HEADPHONE,
+  *                       or OUTPUT_DEVICE_BOTH.
+  * @param  Volume: Initial volume level (from 0 (Mute) to 100 (Max))
+  * @param  AudioFreq: Audio frequency used to play the audio stream.
+  * @note   The SAI PLL input clock must be done in the user application.  
+  * @retval AUDIO_OK if correct communication, else wrong communication
+  */
+uint8_t BSP_AUDIO_OUT_Init(uint16_t OutputDevice, 
+                           uint8_t Volume, 
+                           uint32_t AudioFreq)
+{
+  uint8_t ret = AUDIO_OK;
+
+  SAIx_DeInit();
+  
+  /* PLL clock is set depending by the AudioFreq (44.1khz vs 48khz groups) */ 
+  BSP_AUDIO_OUT_ClockConfig(&haudio_out_sai, AudioFreq, NULL);
+
+  /* SAI data transfer preparation:
+  Prepare the Media to be used for the audio transfer from memory to SAI peripheral */
+  haudio_out_sai.Instance = AUDIO_SAIx;
+  if(HAL_SAI_GetState(&haudio_out_sai) == HAL_SAI_STATE_RESET)
+  {
+    /* Init the SAI MSP: this __weak function can be redefined by the application*/
+    BSP_AUDIO_OUT_MspInit(&haudio_out_sai, NULL);
+  }
+
+  if (SAIx_Init(AudioFreq) != AUDIO_OK)
+  {
+    ret = AUDIO_ERROR;
+  }
+
+  if(ret == AUDIO_OK)
+  {
+    /* Retieve audio codec identifier */
+    if (cs43l22_drv.ReadID(AUDIO_I2C_ADDRESS) == CS43L22_ID)
+    {  
+      /* Initialize the audio driver structure */
+      audio_drv = &cs43l22_drv;
+    }
+    else
+    {
+      ret = AUDIO_ERROR;
+    }
+  }
+
+  if(ret == AUDIO_OK)
+  {
+    /* Initialize the audio codec internal registers */
+    if (audio_drv->Init(AUDIO_I2C_ADDRESS,
+                        OutputDevice, 
+                        Volume, 
+                        AudioFreq) != AUDIO_OK)
+    {
+      ret = AUDIO_ERROR;
+    }
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  Starts playing audio stream from a data buffer for a determined size.
+  * @param  pBuffer: Pointer to the buffer
+  * @param  Size: Number of audio data BYTES.
+  * @retval AUDIO_OK if correct communication, else wrong communication
+  */
+uint8_t BSP_AUDIO_OUT_Play(uint16_t* pBuffer, uint32_t Size)
+{
+  uint8_t ret = AUDIO_OK;
+
+  /* Call the audio Codec Play function */
+  if(audio_drv->Play(AUDIO_I2C_ADDRESS, pBuffer, Size) != 0)
+  {  
+    ret = AUDIO_ERROR;
+  }
+
+  /* Initiate a DMA transfer of PCM samples towards the serial audio interface */  
+  if(ret == AUDIO_OK)
+  {
+    if (HAL_SAI_Transmit_DMA(&haudio_out_sai, (uint8_t*) pBuffer, DMA_MAX(Size / AUDIODATA_SIZE))!= HAL_OK)
+    {
+      ret = AUDIO_ERROR;
+    }
+  }
+        
+  return ret;
+}
+
+/**
+  * @brief  Sends n-Bytes on the SAI interface.
+  * @param  pData: pointer on PCM samples buffer 
+  * @param  Size: number of data to be written
+  */
+void BSP_AUDIO_OUT_ChangeBuffer(uint16_t *pData, uint16_t Size)
+{
+   HAL_SAI_Transmit_DMA(&haudio_out_sai, (uint8_t*) pData, Size);
+}
+
+/**
+  * @brief   This function Pauses the audio file stream. In case
+  *          of using DMA, the DMA Pause feature is used.
+  * @warning When calling BSP_AUDIO_OUT_Pause() function for pause, only
+  *          BSP_AUDIO_OUT_Resume() function should be called for resume (use of BSP_AUDIO_OUT_Play()
+  *          function for resume could lead to unexpected behavior).
+  * @retval  AUDIO_OK if correct communication, else wrong communication
+  */
+uint8_t BSP_AUDIO_OUT_Pause(void)
+{
+  uint8_t ret = AUDIO_OK;
+
+  /* Call the Audio Codec Pause/Resume function */
+  if(audio_drv->Pause(AUDIO_I2C_ADDRESS) != 0)
+  {
+    ret =  AUDIO_ERROR;
+  }
+ 
+  /* Pause DMA transfer of PCM samples towards the serial audio interface */  
+  if(ret == AUDIO_OK)
+  {
+    if (HAL_SAI_DMAPause(&haudio_out_sai)!= HAL_OK)
+    {
+      ret =  AUDIO_ERROR;
+    }
+  }
+
+  /* Return AUDIO_OK when all operations are correctly done */
+  return ret;
+}
+
+/**
+  * @brief  This function  Resumes the audio file stream.
+  * WARNING: When calling BSP_AUDIO_OUT_Pause() function for pause, only
+  *          BSP_AUDIO_OUT_Resume() function should be called for resume
+  *          (use of BSP_AUDIO_OUT_Play() function for resume could lead to 
+  *           unexpected behavior).
+  * @retval AUDIO_OK if correct communication, else wrong communication
+  */
+uint8_t BSP_AUDIO_OUT_Resume(void)
+{
+  uint8_t ret = AUDIO_OK;
+
+  /* Call the Audio Codec Pause/Resume function */
+  if(audio_drv->Resume(AUDIO_I2C_ADDRESS) != 0)
+  {
+    ret =  AUDIO_ERROR;
+  }
+
+  /* Resume DMA transfer of PCM samples towards the serial audio interface */  
+  if(ret == AUDIO_OK)
+  {
+    if (HAL_SAI_DMAResume(&haudio_out_sai)!= HAL_OK)
+    {
+      ret =  AUDIO_ERROR;
+    }
+  }
+
+  /* Return AUDIO_OK when all operations are correctly done */
+  return ret;
+}
+
+/**
+  * @brief  Stops audio playing and Power down the Audio Codec.
+  * @param  Option: could be one of the following parameters
+  *           - CODEC_PDWN_SW: for software power off (by writing registers).
+  *                            Then no need to reconfigure the Codec after power on.
+  *           - CODEC_PDWN_HW: completely shut down the codec (physically).
+  *                            Then need to reconfigure the Codec after power on.
+  * @retval AUDIO_OK if correct communication, else wrong communication
+  */
+uint8_t BSP_AUDIO_OUT_Stop(uint32_t Option)
+{
+  uint8_t ret = AUDIO_OK;
+
+ /* Call Audio Codec Stop function */
+  if(audio_drv->Stop(AUDIO_I2C_ADDRESS, Option) != 0)
+  {
+    ret = AUDIO_ERROR;
+  }
+
+  if(ret == AUDIO_OK)
+  {
+    if(Option == CODEC_PDWN_HW)
+    {
+      /* Wait at least 100us */
+      HAL_Delay(2);
+    }
+
+    /* Stop DMA transfer of PCM samples towards the serial audio interface */  
+    if (HAL_SAI_DMAStop(&haudio_out_sai)!= HAL_OK)
+    {
+      ret = AUDIO_ERROR;
+    }
+  }
+  /* Return AUDIO_OK when all operations are correctly done */
+  return ret;
+}
+
+/**
+  * @brief  Controls the current audio volume level.
+  * @param  Volume: Volume level to be set in percentage from 0% to 100% (0 for
+  *         Mute and 100 for Max volume level).
+  * @retval AUDIO_OK if correct communication, else wrong communication
+  */
+uint8_t BSP_AUDIO_OUT_SetVolume(uint8_t Volume)
+{
+  uint8_t ret = AUDIO_OK;
+
+  /* Call the codec volume control function with converted volume value */
+  if(audio_drv->SetVolume(AUDIO_I2C_ADDRESS, Volume) != 0)
+  {
+    ret =  AUDIO_ERROR;
+  }
+
+  /* Return AUDIO_OK when all operations are correctly done */
+  return ret;
+}
+
+/**
+  * @brief  Enables or disables the MUTE mode by software
+  * @param  Cmd: Could be AUDIO_MUTE_ON to mute sound or AUDIO_MUTE_OFF to
+  *         unmute the codec and restore previous volume level.
+  * @retval AUDIO_OK if correct communication, else wrong communication
+  */
+uint8_t BSP_AUDIO_OUT_SetMute(uint32_t Cmd)
+{
+  uint8_t ret = AUDIO_OK;
+
+  /* Call the Codec Mute function */
+  if(audio_drv->SetMute(AUDIO_I2C_ADDRESS, Cmd) != 0)
+  {
+    ret = AUDIO_ERROR;
+  }
+
+  /* Return AUDIO_OK when all operations are correctly done */
+  return ret;
+}
+
+/**
+  * @brief  Switch dynamically (while audio file is being played) the output 
+  *          target (speaker or headphone).
+  * @param  Output: The audio output target: OUTPUT_DEVICE_SPEAKER,
+  *         OUTPUT_DEVICE_HEADPHONE or OUTPUT_DEVICE_BOTH
+  * @retval AUDIO_OK if correct communication, else wrong communication
+  */
+uint8_t BSP_AUDIO_OUT_SetOutputMode(uint8_t Output)
+{
+  uint8_t ret = AUDIO_OK;
+
+  /* Call the Codec output device function */
+  if(audio_drv->SetOutputMode(AUDIO_I2C_ADDRESS, Output) != 0)
+  {
+    ret = AUDIO_ERROR;
+  }
+
+  /* Return AUDIO_OK when all operations are correctly done */
+  return ret;
+}
+
+/**
+  * @brief  Updates the audio frequency.
+  * @param  AudioFreq: Audio frequency used to play the audio stream.
+  * @note   This API should be called after the BSP_AUDIO_OUT_Init() to adjust the
+  *         audio frequency.
+  */
+void BSP_AUDIO_OUT_SetFrequency(uint32_t AudioFreq)
+{ 
+  /* PLL clock is set depending by the AudioFreq (44.1khz vs 48khz groups) */ 
+  BSP_AUDIO_OUT_ClockConfig(&haudio_out_sai, AudioFreq, NULL);
+
+  /* Disable SAI peripheral to allow access to SAI internal registers */
+  __HAL_SAI_DISABLE(&haudio_out_sai);
+
+  /* Update the SAI audio frequency configuration */
+  haudio_out_sai.Init.AudioFrequency = AudioFreq;
+  HAL_SAI_Init(&haudio_out_sai);
+
+  /* Enable SAI peripheral to generate MCLK */
+  __HAL_SAI_ENABLE(&haudio_out_sai);
+}
+
+/**
+  * @brief  Changes the Audio Out Configuration.
+  * @param  AudioOutOption: specifies the audio out new configuration
+  *         This parameter can be any value of @ref BSP_Audio_Out_Option
+  * @note   This API should be called after the BSP_AUDIO_OUT_Init() to adjust the
+  *         audio out configuration.
+  */
+void BSP_AUDIO_OUT_ChangeAudioConfig(uint32_t AudioOutOption)
+{ 
+  /********** Playback Buffer circular/normal mode **********/
+  if(AudioOutOption & BSP_AUDIO_OUT_CIRCULARMODE)
+  {
+    /* Deinitialize the Stream to update DMA mode */
+    HAL_DMA_DeInit(haudio_out_sai.hdmatx);
+    
+    /* Update the SAI audio Transfer DMA mode */
+    haudio_out_sai.hdmatx->Init.Mode = DMA_CIRCULAR;
+    
+    /* Configure the DMA Stream with new Transfer DMA mode */
+    HAL_DMA_Init(haudio_out_sai.hdmatx);      
+  }
+  else /* BSP_AUDIO_OUT_NORMALMODE */
+  {
+    /* Deinitialize the Stream to update DMA mode */
+    HAL_DMA_DeInit(haudio_out_sai.hdmatx);
+    
+    /* Update the SAI audio Transfer DMA mode */
+    haudio_out_sai.hdmatx->Init.Mode = DMA_NORMAL;
+    
+    /* Configure the DMA Stream with new Transfer DMA mode */
+    HAL_DMA_Init(haudio_out_sai.hdmatx);      
+  }
+  
+  /********** Playback Buffer stereo/mono mode **********/
+  if(AudioOutOption & BSP_AUDIO_OUT_STEREOMODE)
+  {
+    /* Disable SAI peripheral to allow access to SAI internal registers */
+    __HAL_SAI_DISABLE(&haudio_out_sai);
+    
+    /* Update the SAI audio frame slot configuration */
+    haudio_out_sai.Init.MonoStereoMode = SAI_STEREOMODE;
+    HAL_SAI_Init(&haudio_out_sai);
+    
+    /* Enable SAI peripheral to generate MCLK */
+    __HAL_SAI_ENABLE(&haudio_out_sai);
+  }
+  else /* BSP_AUDIO_OUT_MONOMODE */
+  {
+    /* Disable SAI peripheral to allow access to SAI internal registers */
+    __HAL_SAI_DISABLE(&haudio_out_sai);
+    
+    /* Update the SAI audio frame slot configuration */
+    haudio_out_sai.Init.MonoStereoMode = SAI_MONOMODE;
+    HAL_SAI_Init(&haudio_out_sai);
+    
+    /* Enable SAI peripheral to generate MCLK */
+    __HAL_SAI_ENABLE(&haudio_out_sai);
+  }
+}
+
+/**
+  * @brief  Updates the Audio frame slot configuration.
+  * @param  AudioFrameSlot: specifies the audio Frame slot
+  *         This parameter can be any value of @ref CODEC_AudioFrame_SLOT_TDMMode
+  * @note   This API should be called after the BSP_AUDIO_OUT_Init() to adjust the
+  *         audio frame slot.
+  */
+void BSP_AUDIO_OUT_SetAudioFrameSlot(uint32_t AudioFrameSlot)
+{
+  /* Disable SAI peripheral to allow access to SAI internal registers */
+  __HAL_SAI_DISABLE(&haudio_out_sai);
+
+  /* Update the SAI audio frame slot configuration */
+  haudio_out_sai.SlotInit.SlotActive = AudioFrameSlot;
+  HAL_SAI_Init(&haudio_out_sai);
+
+  /* Enable SAI peripheral to generate MCLK */
+  __HAL_SAI_ENABLE(&haudio_out_sai);
+}
+
+/**
+  * @brief  Deinit the audio peripherals.
+  */
+void BSP_AUDIO_OUT_DeInit(void)
+{
+  SAIx_DeInit();
+  /* DeInit the SAI MSP : this __weak function can be rewritten by the applic */
+  BSP_AUDIO_OUT_MspDeInit(&haudio_out_sai, NULL);
+ 
+  /* Reset the audio output context */
+  memset(&audio_drv, 0, sizeof(audio_drv));
+}
+
+/**
+  * @brief  Tx Transfer completed callbacks.
+  * @param  hsai: SAI handle
+  */
+void HAL_SAI_TxCpltCallback(SAI_HandleTypeDef *hsai)
+{
+  /* Manage the remaining file size and new address offset: This function
+     should be coded by user (its prototype is already declared in stm32469i_discovery_audio.h) */
+  BSP_AUDIO_OUT_TransferComplete_CallBack();
+}
+
+/**
+  * @brief  Tx Half Transfer completed callbacks.
+  * @param  hsai: SAI handle
+  */
+void HAL_SAI_TxHalfCpltCallback(SAI_HandleTypeDef *hsai)
+{
+  /* Manage the remaining file size and new address offset: This function
+     should be coded by user (its prototype is already declared in stm32469i_discovery_audio.h) */
+  BSP_AUDIO_OUT_HalfTransfer_CallBack();
+}
+
+/**
+  * @brief  SAI error callbacks.
+  * @param  hsai: SAI handle
+  */
+void HAL_SAI_ErrorCallback(SAI_HandleTypeDef *hsai)
+{
+  BSP_AUDIO_OUT_Error_CallBack();
+}
+
+/**
+  * @brief  Manages the DMA full Transfer complete event.
+  */
+__weak void BSP_AUDIO_OUT_TransferComplete_CallBack(void)
+{
+}
+
+/**
+  * @brief  Manages the DMA Half Transfer complete event.
+  */
+__weak void BSP_AUDIO_OUT_HalfTransfer_CallBack(void)
+{
+}
+
+/**
+  * @brief  Manages the DMA FIFO error event.
+  */
+__weak void BSP_AUDIO_OUT_Error_CallBack(void)
+{
+}
+
+/**
+  * @brief  Initializes BSP_AUDIO_OUT MSP.
+  * @param  hsai: SAI handle
+  * @param  Params : pointer on additional configuration parameters, can be NULL.
+  */
+__weak void BSP_AUDIO_OUT_MspInit(SAI_HandleTypeDef *hsai, void *Params)
+{
+  static DMA_HandleTypeDef hdma_sai_tx;
+  GPIO_InitTypeDef  gpio_init_structure;
+
+  /* Put CS43L2 codec reset high -----------------------------------*/
+  AUDIO_RESET_ENABLE();
+  gpio_init_structure.Pin =  AUDIO_RESET_PIN;
+  gpio_init_structure.Mode = GPIO_MODE_OUTPUT_PP;
+  gpio_init_structure.Pull = GPIO_NOPULL;
+  gpio_init_structure.Speed = GPIO_SPEED_HIGH;
+  HAL_GPIO_Init(AUDIO_RESET_GPIO_PORT, &gpio_init_structure);
+  HAL_GPIO_WritePin(AUDIO_RESET_GPIO_PORT, AUDIO_RESET_PIN, GPIO_PIN_SET);
+
+  /* Enable SAI clock */
+  AUDIO_SAIx_CLK_ENABLE();
+
+  /* Enable GPIO clock */
+  AUDIO_SAIx_MCLK_ENABLE();
+  AUDIO_SAIx_SCK_SD_FS_ENABLE();
+
+  /* CODEC_SAI pins configuration: MCK pin -----------------------------------*/
+  gpio_init_structure.Pin =  AUDIO_SAIx_MCK_PIN;
+  gpio_init_structure.Mode = GPIO_MODE_AF_PP;
+  gpio_init_structure.Pull = GPIO_NOPULL;
+  gpio_init_structure.Speed = GPIO_SPEED_HIGH;
+  gpio_init_structure.Alternate = AUDIO_SAIx_MCLK_SCK_SD_FS_AF;
+  HAL_GPIO_Init(AUDIO_SAIx_MCLK_GPIO_PORT, &gpio_init_structure);
+
+  /* CODEC_SAI pins configuration: FS, SCK, MCK and SD pins ------------------*/
+  gpio_init_structure.Pin = AUDIO_SAIx_FS_PIN | AUDIO_SAIx_SCK_PIN | AUDIO_SAIx_SD_PIN;
+  gpio_init_structure.Mode = GPIO_MODE_AF_PP;
+  gpio_init_structure.Pull = GPIO_NOPULL;
+  gpio_init_structure.Speed = GPIO_SPEED_HIGH;
+  gpio_init_structure.Alternate = AUDIO_SAIx_MCLK_SCK_SD_FS_AF;
+  HAL_GPIO_Init(AUDIO_SAIx_SCK_SD_FS_GPIO_PORT, &gpio_init_structure);
+
+  /* Enable the DMA clock */
+  AUDIO_SAIx_DMAx_CLK_ENABLE();
+
+  if(hsai->Instance == AUDIO_SAIx)
+  {
+    /* Configure the hdma_saiTx handle parameters */
+    hdma_sai_tx.Init.Channel             = AUDIO_SAIx_DMAx_CHANNEL;
+    hdma_sai_tx.Init.Direction           = DMA_MEMORY_TO_PERIPH;
+    hdma_sai_tx.Init.PeriphInc           = DMA_PINC_DISABLE;
+    hdma_sai_tx.Init.MemInc              = DMA_MINC_ENABLE;
+    hdma_sai_tx.Init.PeriphDataAlignment = AUDIO_SAIx_DMAx_PERIPH_DATA_SIZE;
+    hdma_sai_tx.Init.MemDataAlignment    = AUDIO_SAIx_DMAx_MEM_DATA_SIZE;
+    hdma_sai_tx.Init.Mode                = DMA_CIRCULAR;
+    hdma_sai_tx.Init.Priority            = DMA_PRIORITY_HIGH;
+    hdma_sai_tx.Init.FIFOMode            = DMA_FIFOMODE_ENABLE;
+    hdma_sai_tx.Init.FIFOThreshold       = DMA_FIFO_THRESHOLD_FULL;
+    hdma_sai_tx.Init.MemBurst            = DMA_MBURST_SINGLE;
+    hdma_sai_tx.Init.PeriphBurst         = DMA_PBURST_SINGLE;
+
+    hdma_sai_tx.Instance = AUDIO_SAIx_DMAx_STREAM;
+
+    /* Associate the DMA handle */
+    __HAL_LINKDMA(hsai, hdmatx, hdma_sai_tx);
+
+    /* Deinitialize the Stream for new transfer */
+    HAL_DMA_DeInit(&hdma_sai_tx);
+
+    /* Configure the DMA Stream */
+    HAL_DMA_Init(&hdma_sai_tx);
+  }
+
+  /* SAI DMA IRQ Channel configuration */
+  HAL_NVIC_SetPriority(AUDIO_SAIx_DMAx_IRQ, AUDIO_OUT_IRQ_PREPRIO, 0);
+  HAL_NVIC_EnableIRQ(AUDIO_SAIx_DMAx_IRQ);
+
+}
+/**
+  * @brief  Deinitializes BSP_AUDIO_OUT MSP.
+  * @param  hsai: SAI handle
+  * @param  Params : pointer on additional configuration parameters, can be NULL.
+  */
+__weak void BSP_AUDIO_OUT_MspDeInit(SAI_HandleTypeDef *hsai, void *Params)
+{
+  GPIO_InitTypeDef  gpio_init_structure;
+
+  /* SAI DMA IRQ Channel deactivation */
+  HAL_NVIC_DisableIRQ(AUDIO_SAIx_DMAx_IRQ);
+
+  if(hsai->Instance == AUDIO_SAIx)
+  {
+    /* Deinitialize the DMA stream */
+    HAL_DMA_DeInit(hsai->hdmatx);
+  }
+
+  /* Disable SAI peripheral */
+  __HAL_SAI_DISABLE(hsai);  
+
+  /* Put CS43L2 codec reset low -----------------------------------*/
+  HAL_GPIO_WritePin(AUDIO_RESET_GPIO_PORT, AUDIO_RESET_PIN, GPIO_PIN_RESET);
+
+  /* Deactives CODEC_SAI pins FS, SCK, MCK and SD by putting them in input mode */
+  gpio_init_structure.Pin = AUDIO_SAIx_MCK_PIN;
+  HAL_GPIO_DeInit(AUDIO_SAIx_MCLK_GPIO_PORT, gpio_init_structure.Pin);
+
+  gpio_init_structure.Pin = AUDIO_SAIx_FS_PIN | AUDIO_SAIx_SCK_PIN | AUDIO_SAIx_SD_PIN;
+  HAL_GPIO_DeInit(AUDIO_SAIx_SCK_SD_FS_GPIO_PORT, gpio_init_structure.Pin);
+ 
+  gpio_init_structure.Pin = AUDIO_RESET_PIN;
+  HAL_GPIO_DeInit(AUDIO_RESET_GPIO_PORT, gpio_init_structure.Pin);
+
+
+  /* Disable SAI clock */
+  AUDIO_SAIx_CLK_DISABLE();
+
+  
+  /* GPIO pins clock and DMA clock can be shut down in the applic 
+     by surcgarging this __weak function */ 
+}
+
+/**
+  * @brief  Clock Config.
+  * @param  hsai: might be required to set audio peripheral predivider if any.
+  * @param  AudioFreq: Audio frequency used to play the audio stream.
+  * @note   This API is called by BSP_AUDIO_OUT_Init() and BSP_AUDIO_OUT_SetFrequency()
+  *         Being __weak it can be overwritten by the application     
+  * @param  Params : pointer on additional configuration parameters, can be NULL.
+  */
+__weak void BSP_AUDIO_OUT_ClockConfig(SAI_HandleTypeDef *hsai, uint32_t AudioFreq, void *Params)
+{ 
+  RCC_PeriphCLKInitTypeDef rcc_ex_clk_init_struct;
+
+  HAL_RCCEx_GetPeriphCLKConfig(&rcc_ex_clk_init_struct);
+  
+  /* Set the PLL configuration according to the audio frequency */
+  if((AudioFreq == AUDIO_FREQUENCY_11K) || (AudioFreq == AUDIO_FREQUENCY_22K) || (AudioFreq == AUDIO_FREQUENCY_44K))
+  {
+    /* Configure PLLI2S prescalers */
+    /* PLLI2S_VCO: VCO_429M
+    I2S_CLK(first level) = PLLI2S_VCO/PLLI2SQ = 429/2 = 214.5 Mhz
+    I2S_CLK_x = I2S_CLK(first level)/PLLI2SDIVQ = 214.5/19 = 11.289 Mhz */
+    rcc_ex_clk_init_struct.PeriphClockSelection = RCC_PERIPHCLK_SAI_PLLI2S;
+    rcc_ex_clk_init_struct.PLLI2S.PLLI2SN = 429;
+    rcc_ex_clk_init_struct.PLLI2S.PLLI2SQ = 2;
+    rcc_ex_clk_init_struct.PLLI2SDivQ = 19;
+    
+    HAL_RCCEx_PeriphCLKConfig(&rcc_ex_clk_init_struct);
+    
+  }
+  else /* AUDIO_FREQUENCY_8K, AUDIO_FREQUENCY_16K, AUDIO_FREQUENCY_48K), AUDIO_FREQUENCY_96K */
+  {
+    /* SAI clock config 
+    PLLSAI_VCO: VCO_344M 
+    I2S_CLK(first level) = PLLI2S_VCO/PLLI2SQ = 344/7 = 49.142 Mhz 
+    I2S_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ = 49.142/1 = 49.142 Mhz */  
+    rcc_ex_clk_init_struct.PeriphClockSelection = RCC_PERIPHCLK_SAI_PLLI2S;
+    rcc_ex_clk_init_struct.PLLI2S.PLLI2SN = 344; 
+    rcc_ex_clk_init_struct.PLLI2S.PLLI2SQ = 7; 
+    rcc_ex_clk_init_struct.PLLI2SDivQ = 1;       
+    
+    HAL_RCCEx_PeriphCLKConfig(&rcc_ex_clk_init_struct);
+  }
+}
+
+/*******************************************************************************
+                            Static Functions
+*******************************************************************************/
+/**
+  * @brief  Initializes the Audio Codec audio interface (SAI).
+  * @param  AudioFreq: Audio frequency to be configured for the SAI peripheral.
+  * @note   The default SlotActive configuration is set to CODEC_AUDIOFRAME_SLOT_0123
+  *         and user can update this configuration using
+  */
+static uint8_t SAIx_Init(uint32_t AudioFreq)
+{
+  uint8_t ret = AUDIO_OK;
+
+  /* Initialize the haudio_out_sai Instance parameter */
+  haudio_out_sai.Instance = AUDIO_SAIx;
+
+  /* Disable SAI peripheral to allow access to SAI internal registers */
+  __HAL_SAI_DISABLE(&haudio_out_sai);
+
+  /* Configure SAI_Block_x
+  LSBFirst: Disabled
+  DataSize: 16 */
+  haudio_out_sai.Init.AudioFrequency = AudioFreq;
+  haudio_out_sai.Init.ClockSource = SAI_CLKSOURCE_PLLI2S;
+  haudio_out_sai.Init.AudioMode = SAI_MODEMASTER_TX;
+  haudio_out_sai.Init.NoDivider = SAI_MASTERDIVIDER_ENABLE;
+  haudio_out_sai.Init.Protocol = SAI_FREE_PROTOCOL;
+  haudio_out_sai.Init.DataSize = SAI_DATASIZE_16;
+  haudio_out_sai.Init.FirstBit = SAI_FIRSTBIT_MSB;
+  haudio_out_sai.Init.ClockStrobing = SAI_CLOCKSTROBING_FALLINGEDGE;
+  haudio_out_sai.Init.Synchro = SAI_ASYNCHRONOUS;
+  haudio_out_sai.Init.OutputDrive = SAI_OUTPUTDRIVE_ENABLE;
+  haudio_out_sai.Init.FIFOThreshold = SAI_FIFOTHRESHOLD_1QF;
+/*
+  haudio_out_sai.Init.AudioFrequency = SAI_AUDIO_FREQUENCY_MCKDIV;
+  haudio_out_sai.Init.SynchroExt     = SAI_SYNCEXT_DISABLE;
+  haudio_out_sai.Init.Mckdiv         = SAIClockDivider(AudioFreq);
+  haudio_out_sai.Init.MonoStereoMode = SAI_STEREOMODE;
+  haudio_out_sai.Init.CompandingMode = SAI_NOCOMPANDING;
+  haudio_out_sai.Init.TriState       = SAI_OUTPUT_NOTRELEASED;
+*/
+
+  /* Configure SAI_Block_x Frame
+  Frame Length: 64
+  Frame active Length: 32
+  FS Definition: Start frame + Channel Side identification
+  FS Polarity: FS active Low
+  FS Offset: FS asserted one bit before the first bit of slot 0 */
+  haudio_out_sai.FrameInit.FrameLength = 64;
+  haudio_out_sai.FrameInit.ActiveFrameLength = 32;
+  haudio_out_sai.FrameInit.FSDefinition = SAI_FS_CHANNEL_IDENTIFICATION;
+  haudio_out_sai.FrameInit.FSPolarity = SAI_FS_ACTIVE_LOW;
+  haudio_out_sai.FrameInit.FSOffset = SAI_FS_BEFOREFIRSTBIT;
+
+  /* Configure SAI Block_x Slot
+  Slot First Bit Offset: 0
+  Slot Size  : 16
+  Slot Number: 4
+  Slot Active: All slot actives */
+  haudio_out_sai.SlotInit.FirstBitOffset = 0;
+  haudio_out_sai.SlotInit.SlotSize = SAI_SLOTSIZE_DATASIZE;
+  haudio_out_sai.SlotInit.SlotNumber = 4;
+  haudio_out_sai.SlotInit.SlotActive = CODEC_AUDIOFRAME_SLOT_0123;
+
+  /* Initializes the SAI peripheral*/
+  if (HAL_SAI_Init(&haudio_out_sai) != HAL_OK)
+  {
+    ret = AUDIO_ERROR;
+  }
+
+  /* Enable SAI peripheral to generate MCLK */
+  __HAL_SAI_ENABLE(&haudio_out_sai);
+
+  return ret;
+
+}
+
+/**
+  * @brief  Deinitializes the Audio Codec audio interface (SAI).
+  */
+static void SAIx_DeInit(void)
+{
+  /* Initialize the hAudioOutSai Instance parameter */
+  haudio_out_sai.Instance = AUDIO_SAIx;
+
+  /* Disable SAI peripheral */
+  __HAL_SAI_DISABLE(&haudio_out_sai);
+
+  HAL_SAI_DeInit(&haudio_out_sai);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup STM32469I-Discovery_AUDIO_in_Private_Functions STM32469I Discovery AUDIO IN Private functions
+  * @{
+  */
+
+/**
+  * @brief  Initializes wave recording.
+  * @note   This function assumes that the I2S input clock (through PLL_R in
+  *         Devices RevA/Z and through dedicated PLLI2S_R in Devices RevB/Y)
+  *         is already configured and ready to be used.
+  * @param  AudioFreq: Audio frequency to be configured for the I2S peripheral.
+  * @param  BitRes: Audio frequency to be configured for the I2S peripheral.
+  * @param  ChnlNbr: Audio frequency to be configured for the I2S peripheral.
+  * @retval AUDIO_OK if correct communication, else wrong communication
+  */
+uint8_t BSP_AUDIO_IN_Init(uint32_t AudioFreq, uint32_t BitRes, uint32_t ChnlNbr)
+{
+  /* DeInit the I2S */
+  I2Sx_DeInit();
+
+  /* Configure PLL clock */ 
+  BSP_AUDIO_IN_ClockConfig(&haudio_in_i2s, NULL);
+
+  /* Configure the PDM library */
+  PDMDecoder_Init(AudioFreq, ChnlNbr, ChnlNbr);
+ 
+  /* Configure the I2S peripheral */
+  haudio_in_i2s.Instance = AUDIO_I2Sx;
+  if(HAL_I2S_GetState(&haudio_in_i2s) == HAL_I2S_STATE_RESET)
+  { 
+    /* Initialize the I2S Msp: this __weak function can be rewritten by the application */
+    BSP_AUDIO_IN_MspInit(&haudio_in_i2s, NULL);
+  }
+
+  I2Sx_Init(AudioFreq);
+
+  /* Return AUDIO_OK when all operations are correctly done */
+  return AUDIO_OK;
+}
+
+/**
+  * @brief  Starts audio recording.
+  * @param  pbuf: Main buffer pointer for the recorded data storing
+  * @param  size: Current size of the recorded buffer
+  * @retval AUDIO_OK if correct communication, else wrong communication
+  */
+uint8_t BSP_AUDIO_IN_Record(uint16_t* pbuf, uint32_t size)
+{
+  uint32_t ret = AUDIO_ERROR;
+
+  /* Start the process receive DMA */
+  HAL_I2S_Receive_DMA(&haudio_in_i2s, pbuf, size);
+
+  /* Return AUDIO_OK when all operations are correctly done */
+  ret = AUDIO_OK;
+
+  return ret;
+}
+
+/**
+  * @brief  Stops audio recording.
+  * @retval AUDIO_OK if correct communication, else wrong communication
+  */
+uint8_t BSP_AUDIO_IN_Stop(void)
+{
+  uint32_t ret = AUDIO_ERROR;
+
+  /* Call the Media layer pause function */
+  HAL_I2S_DMAPause(&haudio_in_i2s);
+
+  /* TIMx Peripheral clock disable */
+  AUDIO_TIMx_CLK_DISABLE();
+
+  /* Return AUDIO_OK when all operations are correctly done */
+  ret = AUDIO_OK;
+
+  return ret;
+}
+
+/**
+  * @brief  Pauses the audio file stream.
+  * @retval AUDIO_OK if correct communication, else wrong communication
+  */
+uint8_t BSP_AUDIO_IN_Pause(void)
+{
+  /* Call the Media layer pause function */
+  HAL_I2S_DMAPause(&haudio_in_i2s);
+
+  /* Return AUDIO_OK when all operations are correctly done */
+  return AUDIO_OK;
+}
+
+/**
+  * @brief  Resumes the audio file stream.
+  * @retval AUDIO_OK if correct communication, else wrong communication
+  */
+uint8_t BSP_AUDIO_IN_Resume(void)
+{
+  /* Call the Media layer pause/resume function */
+  HAL_I2S_DMAResume(&haudio_in_i2s);
+
+  /* Return AUDIO_OK when all operations are correctly done */
+  return AUDIO_OK;
+}
+
+/**
+  * @brief  Controls the audio in volume level.
+  * @param  Volume: Volume level to be set in percentage from 0% to 100% (0 for
+  *         Mute and 100 for Max volume level).
+  * @retval AUDIO_OK if correct communication, else wrong communication
+  */
+uint8_t BSP_AUDIO_IN_SetVolume(uint8_t Volume)
+{
+  /* Set the Global variable AudioInVolume  */
+  AudioInVolume = Volume;
+
+  /* Return AUDIO_OK when all operations are correctly done */
+  return AUDIO_OK;
+}
+
+/**
+  * @brief  Deinit the audio IN peripherals.
+  */
+void BSP_AUDIO_IN_DeInit(void)
+{
+  I2Sx_DeInit();
+    /* DeInit the I2S MSP : this __weak function can be rewritten by the applic */
+  BSP_AUDIO_IN_MspDeInit(&haudio_in_i2s, NULL);
+  TIMx_DeInit();
+}
+
+/**
+  * @brief  Converts audio format from PDM to PCM.
+  * @param  PDMBuf: Pointer to data PDM buffer
+  * @param  PCMBuf: Pointer to data PCM buffer
+  * @retval AUDIO_OK if correct communication, else wrong communication
+  */
+uint8_t BSP_AUDIO_IN_PDMToPCM(uint16_t* PDMBuf, uint16_t* PCMBuf)
+{
+  uint8_t app_pdm[INTERNAL_BUFF_SIZE*2];
+  uint8_t byte1 = 0, byte2 = 0;
+  uint32_t index = 0;
+
+  /* PDM Demux */
+  for(index = 0; index<INTERNAL_BUFF_SIZE/2; index++)
+  {
+    byte2 = (PDMBuf[index] >> 8)& 0xFF;
+    byte1 = (PDMBuf[index] & 0xFF);
+    app_pdm[(index*2)+1] = Channel_Demux[byte1 & CHANNEL_DEMUX_MASK] | Channel_Demux[byte2 & CHANNEL_DEMUX_MASK] << 4;
+    app_pdm[(index*2)] = Channel_Demux[(byte1 >> 1) & CHANNEL_DEMUX_MASK] | Channel_Demux[(byte2 >> 1) & CHANNEL_DEMUX_MASK] << 4;
+  }
+
+  for(index = 0; index < DEFAULT_AUDIO_IN_CHANNEL_NBR; index++)
+  {
+    /* PDM to PCM filter */
+    PDM_Filter((uint8_t*)&app_pdm[index], (uint16_t*)&(PCMBuf[index]), &PDM_FilterHandler[index]);
+  }
+
+  /* Return AUDIO_OK when all operations are correctly done */
+  return AUDIO_OK;
+}
+
+ /**
+  * @brief  Rx Transfer completed callbacks.
+  * @param  hi2s: I2S handle
+  */
+void HAL_I2S_RxCpltCallback(I2S_HandleTypeDef *hi2s)
+{
+  /* Call the record update function to get the next buffer to fill and its size (size is ignored) */
+  BSP_AUDIO_IN_TransferComplete_CallBack();
+}
+
+/**
+  * @brief  Rx Half Transfer completed callbacks.
+  * @param  hi2s: I2S handle
+  */
+void HAL_I2S_RxHalfCpltCallback(I2S_HandleTypeDef *hi2s)
+{
+  /* Manage the remaining file size and new address offset: This function
+     should be coded by user (its prototype is already declared in stm32469i_discovery_audio.h) */
+  BSP_AUDIO_IN_HalfTransfer_CallBack();
+}
+
+/**
+  * @brief  I2S error callbacks.
+  * @param  hi2s: I2S handle
+  */
+void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s)
+{
+  /* Manage the error generated on DMA FIFO: This function
+     should be coded by user (its prototype is already declared in stm32469i_discovery_audio.h) */
+  BSP_AUDIO_IN_Error_Callback();
+}
+
+/**
+  * @brief  Clock Config.
+  * @param  hi2s: I2S handle
+  * @param  Params : pointer on additional configuration parameters, can be NULL.   
+  * @note   This API is called by BSP_AUDIO_IN_Init()
+  *         Being __weak it can be overwritten by the application
+  */
+__weak void BSP_AUDIO_IN_ClockConfig(I2S_HandleTypeDef *hi2s, void *Params)
+{
+  RCC_PeriphCLKInitTypeDef RCC_ExCLKInitStruct;
+  
+  HAL_RCCEx_GetPeriphCLKConfig(&RCC_ExCLKInitStruct);
+  RCC_ExCLKInitStruct.PeriphClockSelection = RCC_PERIPHCLK_I2S;
+  RCC_ExCLKInitStruct.PLLI2S.PLLI2SN = 384;
+  RCC_ExCLKInitStruct.PLLI2S.PLLI2SR = 2;
+  HAL_RCCEx_PeriphCLKConfig(&RCC_ExCLKInitStruct); 
+}
+
+/**
+  * @brief  User callback when record buffer is filled.
+  */
+__weak void BSP_AUDIO_IN_TransferComplete_CallBack(void)
+{
+  /* This function should be implemented by the user application.
+     It is called into this driver when the current buffer is filled
+     to prepare the next buffer pointer and its size. */
+}
+
+/**
+  * @brief  Manages the DMA Half Transfer complete event.
+  */
+__weak void BSP_AUDIO_IN_HalfTransfer_CallBack(void)
+{
+  /* This function should be implemented by the user application.
+     It is called into this driver when the current buffer is filled
+     to prepare the next buffer pointer and its size. */
+}
+
+/**
+  * @brief  Audio IN Error callback function.
+  */
+__weak void BSP_AUDIO_IN_Error_Callback(void)
+{
+  /* This function is called when an Interrupt due to transfer error on or peripheral
+     error occurs. */
+}
+
+/**
+  * @brief  BSP AUDIO IN MSP Init.
+  * @param  hi2s: I2S handle
+  * @param  Params : pointer on additional configuration parameters, can be NULL.
+  */
+__weak void BSP_AUDIO_IN_MspInit(I2S_HandleTypeDef *hi2s, void *Params)
+{
+  static DMA_HandleTypeDef hdma_i2s_rx;
+  GPIO_InitTypeDef  gpio_init_structure;
+
+  /* Configure the Timer which clocks the MEMS */
+  /* Moved inside MSP to allow applic to redefine the TIMx_MspInit */
+  TIMx_Init();
+  
+  /* Enable I2S clock */
+  AUDIO_I2Sx_CLK_ENABLE();
+
+  /* Enable SCK and SD GPIO clock */
+  AUDIO_I2Sx_SD_GPIO_CLK_ENABLE();
+  AUDIO_I2Sx_SCK_GPIO_CLK_ENABLE();
+  /* CODEC_I2S pins configuration: SCK and SD pins */
+  gpio_init_structure.Pin = AUDIO_I2Sx_SCK_PIN;
+  gpio_init_structure.Mode = GPIO_MODE_AF_PP;
+  gpio_init_structure.Pull = GPIO_NOPULL;
+  gpio_init_structure.Speed = GPIO_SPEED_FAST;
+  gpio_init_structure.Alternate = AUDIO_I2Sx_SCK_AF;
+  HAL_GPIO_Init(AUDIO_I2Sx_SCK_GPIO_PORT, &gpio_init_structure);
+
+  gpio_init_structure.Pin = AUDIO_I2Sx_SD_PIN;
+  gpio_init_structure.Alternate = AUDIO_I2Sx_SD_AF;
+  HAL_GPIO_Init(AUDIO_I2Sx_SD_GPIO_PORT, &gpio_init_structure);
+
+  /* Enable PD12 (I2S3_CLK) connected to PB3 via jamper JP4 */
+  /* on Eval this was provided by PC6 (initialized in TIMx section) */
+/*
+  gpio_init_structure.Pin = GPIO_PIN_12;
+  gpio_init_structure.Mode = GPIO_MODE_AF_PP;
+  gpio_init_structure.Pull = GPIO_NOPULL;
+  gpio_init_structure.Speed = GPIO_SPEED_FAST;
+  gpio_init_structure.Alternate = AUDIO_I2Sx_SCK_AF;
+  HAL_GPIO_Init(GPIOD, &gpio_init_structure); */
+  
+
+  /* Enable the DMA clock */
+  AUDIO_I2Sx_DMAx_CLK_ENABLE();
+
+  if(hi2s->Instance == AUDIO_I2Sx)
+  {
+    /* Configure the hdma_i2sRx handle parameters */
+    hdma_i2s_rx.Init.Channel             = AUDIO_I2Sx_DMAx_CHANNEL;
+    hdma_i2s_rx.Init.Direction           = DMA_PERIPH_TO_MEMORY;
+    hdma_i2s_rx.Init.PeriphInc           = DMA_PINC_DISABLE;
+    hdma_i2s_rx.Init.MemInc              = DMA_MINC_ENABLE;
+    hdma_i2s_rx.Init.PeriphDataAlignment = AUDIO_I2Sx_DMAx_PERIPH_DATA_SIZE;
+    hdma_i2s_rx.Init.MemDataAlignment    = AUDIO_I2Sx_DMAx_MEM_DATA_SIZE;
+    hdma_i2s_rx.Init.Mode                = DMA_CIRCULAR;
+    hdma_i2s_rx.Init.Priority            = DMA_PRIORITY_HIGH;
+    hdma_i2s_rx.Init.FIFOMode            = DMA_FIFOMODE_DISABLE;
+    hdma_i2s_rx.Init.FIFOThreshold       = DMA_FIFO_THRESHOLD_FULL;
+    hdma_i2s_rx.Init.MemBurst            = DMA_MBURST_SINGLE;
+    hdma_i2s_rx.Init.PeriphBurst         = DMA_MBURST_SINGLE;
+
+    hdma_i2s_rx.Instance = AUDIO_I2Sx_DMAx_STREAM;
+
+    /* Associate the DMA handle */
+    __HAL_LINKDMA(hi2s, hdmarx, hdma_i2s_rx);
+
+    /* Deinitialize the Stream for new transfer */
+    HAL_DMA_DeInit(&hdma_i2s_rx);
+
+    /* Configure the DMA Stream */
+    HAL_DMA_Init(&hdma_i2s_rx);
+  }
+
+  /* I2S DMA IRQ Channel configuration */
+  HAL_NVIC_SetPriority(AUDIO_I2Sx_DMAx_IRQ, AUDIO_IN_IRQ_PREPRIO, 0);
+  HAL_NVIC_EnableIRQ(AUDIO_I2Sx_DMAx_IRQ);
+}
+
+/**
+  * @brief  DeInitializes BSP_AUDIO_IN MSP.
+  * @param  hi2s: I2S handle
+  * @param  Params : pointer on additional configuration parameters, can be NULL.
+  */
+__weak void BSP_AUDIO_IN_MspDeInit(I2S_HandleTypeDef *hi2s, void *Params)
+{
+  GPIO_InitTypeDef  gpio_init_structure;
+
+  /* I2S DMA IRQ Channel deactivation */
+  HAL_NVIC_DisableIRQ(AUDIO_I2Sx_DMAx_IRQ); 
+  
+  if(hi2s->Instance == AUDIO_I2Sx)
+  {
+    /* Deinitialize the Stream for new transfer */
+    HAL_DMA_DeInit(hi2s->hdmarx);
+  }
+
+ /* Disable I2S block */
+  __HAL_I2S_DISABLE(hi2s);
+
+  /* Disable pins: SCK and SD pins */
+  gpio_init_structure.Pin = AUDIO_I2Sx_SCK_PIN;
+  HAL_GPIO_DeInit(AUDIO_I2Sx_SCK_GPIO_PORT, gpio_init_structure.Pin);
+  gpio_init_structure.Pin = AUDIO_I2Sx_SD_PIN;
+  HAL_GPIO_DeInit(AUDIO_I2Sx_SD_GPIO_PORT, gpio_init_structure.Pin); 
+
+  /* Disable I2S clock */
+  AUDIO_I2Sx_CLK_DISABLE();
+
+  /* GPIO pins clock and DMA clock can be shut down in the applic 
+     by surcgarging this __weak function */ 
+}
+
+/*******************************************************************************
+                            Static Functions
+*******************************************************************************/
+
+/**
+  * @brief  Initializes the PDM library.
+  * @param  AudioFreq: Audio sampling frequency
+  * @param  ChnlNbrIn: Number of input audio channels in the PDM buffer
+  * @param  ChnlNbrOut: Number of desired output audio channels in the  resulting PCM buffer
+  *         Number of audio channels (1: mono; 2: stereo)
+  */
+static void PDMDecoder_Init(uint32_t AudioFreq, uint32_t ChnlNbrIn, uint32_t ChnlNbrOut)
+{
+  uint32_t index = 0;
+
+  /* Enable CRC peripheral to unlock the PDM library */
+  __HAL_RCC_CRC_CLK_ENABLE();
+
+  for(index = 0; index < ChnlNbrIn; index++)
+  {
+    /* Init PDM filters */
+    PDM_FilterHandler[index].bit_order  = PDM_FILTER_BIT_ORDER_LSB;
+    PDM_FilterHandler[index].endianness = PDM_FILTER_ENDIANNESS_LE;
+    PDM_FilterHandler[index].high_pass_tap = 2122358088;
+    PDM_FilterHandler[index].out_ptr_channels = ChnlNbrOut;
+    PDM_FilterHandler[index].in_ptr_channels  = ChnlNbrIn;
+    PDM_Filter_Init((PDM_Filter_Handler_t *)(&PDM_FilterHandler[index]));
+
+    /* PDM lib config phase */
+    PDM_FilterConfig[index].output_samples_number = AudioFreq/1000;
+    PDM_FilterConfig[index].mic_gain = 24;
+    PDM_FilterConfig[index].decimation_factor = PDM_FILTER_DEC_FACTOR_64;
+    PDM_Filter_setConfig((PDM_Filter_Handler_t *)&PDM_FilterHandler[index], &PDM_FilterConfig[index]);
+  }
+}
+
+/**
+  * @brief  Initializes the Audio Codec audio interface (I2S)
+  * @note   This function assumes that the I2S input clock (through dedicated PLLI2S_R)
+  *         is already configured and ready to be used.
+  * @param  AudioFreq: Audio frequency to be configured for the I2S peripheral.
+  */
+static void I2Sx_Init(uint32_t AudioFreq)
+{
+  /* Initialize the haudio_in_i2s Instance parameter */
+  haudio_in_i2s.Instance = AUDIO_I2Sx;
+
+ /* Disable I2S block */
+  __HAL_I2S_DISABLE(&haudio_in_i2s);
+
+  /* I2S2 peripheral configuration */
+  haudio_in_i2s.Init.AudioFreq = 4 * AudioFreq;
+  haudio_in_i2s.Init.ClockSource = I2S_CLOCK_PLL;
+  haudio_in_i2s.Init.CPOL = I2S_CPOL_LOW;
+  haudio_in_i2s.Init.DataFormat = I2S_DATAFORMAT_16B;
+  haudio_in_i2s.Init.MCLKOutput = I2S_MCLKOUTPUT_DISABLE;
+  haudio_in_i2s.Init.Mode = I2S_MODE_MASTER_RX;
+  haudio_in_i2s.Init.Standard = I2S_STANDARD_LSB;
+  
+  /* Init the I2S */
+  HAL_I2S_Init(&haudio_in_i2s); 
+
+ /* Disable I2S block */
+  __HAL_I2S_ENABLE(&haudio_in_i2s);
+
+}
+
+/**
+  * @brief  Deinitializes the Audio Codec audio interface (I2S).
+  */
+static void I2Sx_DeInit(void)
+{
+  /* Initialize the hAudioInI2s Instance parameter */
+  haudio_in_i2s.Instance = AUDIO_I2Sx;
+
+ /* Disable I2S block */
+  __HAL_I2S_DISABLE(&haudio_in_i2s);
+
+  /* DeInit the I2S */
+  HAL_I2S_DeInit(&haudio_in_i2s); 
+}
+
+
+/**
+  * @brief  Initializes the TIM INput Capture MSP.
+  * @param  htim: TIM handle
+  */
+static void TIMx_IC_MspInit(TIM_HandleTypeDef *htim)
+{
+  GPIO_InitTypeDef   gpio_init_structure;
+
+  /* Enable peripherals and GPIO Clocks --------------------------------------*/
+  /* TIMx Peripheral clock enable */
+  AUDIO_TIMx_CLK_ENABLE();
+
+  /* Enable GPIO Channels Clock */
+  AUDIO_TIMx_GPIO_CLK_ENABLE();
+
+  /* Configure I/Os ----------------------------------------------------------*/
+  /* Common configuration for all channels */
+  gpio_init_structure.Mode = GPIO_MODE_AF_PP;
+  gpio_init_structure.Pull = GPIO_NOPULL;
+  gpio_init_structure.Speed = GPIO_SPEED_HIGH;
+  gpio_init_structure.Alternate = AUDIO_TIMx_AF;
+
+  /* Configure TIM input channel */
+  gpio_init_structure.Pin = AUDIO_TIMx_IN_GPIO_PIN;
+  HAL_GPIO_Init(AUDIO_TIMx_GPIO_PORT, &gpio_init_structure);
+
+  /* Configure TIM output channel */
+  gpio_init_structure.Pin = AUDIO_TIMx_OUT_GPIO_PIN;
+  HAL_GPIO_Init(AUDIO_TIMx_GPIO_PORT, &gpio_init_structure);
+}
+
+/**
+  * @brief  Initializes the TIM INput Capture MSP.
+  * @param  htim: TIM handle
+  */
+static void TIMx_IC_MspDeInit(TIM_HandleTypeDef *htim)
+{
+    /* Disable TIMx Peripheral clock  */
+    AUDIO_TIMx_CLK_DISABLE();
+
+    /* GPIO pins clock and DMA clock can be shut down in the applic 
+       by surcgarging this __weak function */ 
+}
+
+/**
+  * @brief  Configure TIM as a clock divider by 2.
+  *         I2S_SCK is externally connected to TIMx input channel
+  */
+static void TIMx_Init(void)
+{
+  TIM_IC_InitTypeDef     s_ic_config;
+  TIM_OC_InitTypeDef     s_oc_config;
+  TIM_ClockConfigTypeDef s_clk_source_config;
+  TIM_SlaveConfigTypeDef s_slave_config;
+  
+  /* Configure the TIM peripheral --------------------------------------------*/
+  /* Set TIMx instance */
+  haudio_tim.Instance = AUDIO_TIMx;
+  /* Timer Input Capture Configuration Structure declaration */
+   /* Initialize TIMx peripheral as follow:
+       + Period = 0xFFFF
+       + Prescaler = 0
+       + ClockDivision = 0
+       + Counter direction = Up
+  */
+  haudio_tim.Init.Period        = 1;
+  haudio_tim.Init.Prescaler     = 0;
+  haudio_tim.Init.ClockDivision = 0;
+  haudio_tim.Init.CounterMode   = TIM_COUNTERMODE_UP;
+
+  /* Initialize the TIMx peripheral with the structure above */
+  TIMx_IC_MspInit(&haudio_tim);
+  HAL_TIM_IC_Init(&haudio_tim);
+
+  /* Configure the Input Capture channel -------------------------------------*/
+  /* Configure the Input Capture of channel 2 */
+  s_ic_config.ICPolarity  = TIM_ICPOLARITY_FALLING;
+  s_ic_config.ICSelection = TIM_ICSELECTION_DIRECTTI;
+  s_ic_config.ICPrescaler = TIM_ICPSC_DIV1;
+  s_ic_config.ICFilter    = 0;
+  HAL_TIM_IC_ConfigChannel(&haudio_tim, &s_ic_config, AUDIO_TIMx_IN_CHANNEL);
+  
+  /* Select external clock mode 1 */
+  s_clk_source_config.ClockSource = TIM_CLOCKSOURCE_ETRMODE1;
+  s_clk_source_config.ClockPolarity = TIM_CLOCKPOLARITY_NONINVERTED;
+  s_clk_source_config.ClockPrescaler = TIM_CLOCKPRESCALER_DIV1;
+  s_clk_source_config.ClockFilter = 0;   
+  HAL_TIM_ConfigClockSource(&haudio_tim, &s_clk_source_config);
+  
+  /* Select Input Channel as input trigger */
+  s_slave_config.InputTrigger = TIM_TS_TI1FP1;
+  s_slave_config.SlaveMode = TIM_SLAVEMODE_EXTERNAL1;
+  s_slave_config.TriggerPolarity = TIM_TRIGGERPOLARITY_NONINVERTED;
+  s_slave_config.TriggerPrescaler = TIM_CLOCKPRESCALER_DIV1;
+  s_slave_config.TriggerFilter = 0;
+  HAL_TIM_SlaveConfigSynchronization(&haudio_tim, &s_slave_config);
+  
+  /* Output Compare PWM Mode configuration: Channel2 */
+  s_oc_config.OCMode = TIM_OCMODE_PWM1;
+  s_oc_config.OCIdleState = TIM_OCIDLESTATE_SET;
+  s_oc_config.Pulse = 1;
+  s_oc_config.OCPolarity = TIM_OCPOLARITY_HIGH;
+  s_oc_config.OCNPolarity = TIM_OCNPOLARITY_HIGH;
+  s_oc_config.OCFastMode = TIM_OCFAST_DISABLE;
+  s_oc_config.OCNIdleState = TIM_OCNIDLESTATE_SET;
+  
+  /* Initialize the TIM3 Channel2 with the structure above */
+  HAL_TIM_PWM_ConfigChannel(&haudio_tim, &s_oc_config, AUDIO_TIMx_OUT_CHANNEL);
+
+  /* Start the TIM3 Channel2 */
+  HAL_TIM_PWM_Start(&haudio_tim, AUDIO_TIMx_OUT_CHANNEL);
+
+  /* Start the TIM3 Channel1 */
+  HAL_TIM_IC_Start(&haudio_tim, AUDIO_TIMx_IN_CHANNEL);
+}
+
+/**
+  * @brief  Configure TIM as a clock divider by 2.
+  *         I2S_SCK is externally connected to TIMx input channel
+  */
+static void TIMx_DeInit(void)
+{
+  haudio_tim.Instance = AUDIO_TIMx;
+  
+  /* Stop the TIM3 Channel2 */
+  HAL_TIM_PWM_Stop(&haudio_tim, AUDIO_TIMx_OUT_CHANNEL);
+  /* Stop the TIM3 Channel1 */
+  HAL_TIM_IC_Stop(&haudio_tim, AUDIO_TIMx_IN_CHANNEL);
+
+  HAL_TIM_IC_DeInit(&haudio_tim);
+  
+  /* Initialize the TIMx peripheral with the structure above */
+  TIMx_IC_MspDeInit(&haudio_tim);
+}
+
+/**
+  * @}
+  */ 
+  
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
diff --git a/Drivers/BSP/STM32469I-Discovery/stm32469i_discovery_audio.h b/Drivers/BSP/STM32469I-Discovery/stm32469i_discovery_audio.h
new file mode 100644
index 0000000..ca5e7da
--- /dev/null
+++ b/Drivers/BSP/STM32469I-Discovery/stm32469i_discovery_audio.h
@@ -0,0 +1,328 @@
+/**
+  ******************************************************************************
+  * @file    stm32469i_discovery_audio.h
+  * @author  MCD Application Team
+  * @version V2.0.0
+  * @date    27-January-2017
+  * @brief   This file contains the common defines and functions prototypes for
+  *          the stm32469i_discovery_audio.c driver.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32469I_DISCOVERY_AUDIO_H
+#define __STM32469I_DISCOVERY_AUDIO_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#if defined(BSP_AUDIO_USE_RTOS)
+#include "k_mem.h"
+#else
+#include <stdlib.h>
+#endif
+
+/* Include audio component Driver */
+#include "../Components/cs43l22/cs43l22.h"
+#include "stm32469i_discovery.h"
+#include "../../../Middlewares/ST/STM32_Audio/Addons/PDM/Inc/pdm2pcm_glo.h"
+
+/** @addtogroup BSP
+  * @{
+  */
+
+/** @addtogroup STM32469I_Discovery
+  * @{
+  */
+
+/** @addtogroup STM32469I-Discovery_AUDIO
+  * @{
+  */
+
+/** @defgroup STM32469I-Discovery_AUDIO_Exported_Types STM32469I Discovery AUDIO Exported Types
+  * @{
+  */
+/**
+  * @}
+  */
+
+/** @defgroup STM32469I-Discovery_AUDIO_Exported_Constants  STM32469I Discovery AUDIO Exported Constants
+  * @{
+  */
+
+/** @defgroup BSP_Audio_Out_Option BSP AUDIO OUT Option
+  * @{
+  */
+#define BSP_AUDIO_OUT_CIRCULARMODE      ((uint32_t)0x00000001) /* BUFFER CIRCULAR MODE */
+#define BSP_AUDIO_OUT_NORMALMODE        ((uint32_t)0x00000002) /* BUFFER NORMAL MODE   */
+#define BSP_AUDIO_OUT_STEREOMODE        ((uint32_t)0x00000004) /* STEREO MODE          */
+#define BSP_AUDIO_OUT_MONOMODE          ((uint32_t)0x00000008) /* MONO MODE            */
+/**
+  * @}
+  */
+
+/*------------------------------------------------------------------------------
+                          USER SAI defines parameters
+ -----------------------------------------------------------------------------*/
+/** @defgroup CODEC_AudioFrame_SLOT_TDMMode  STM32469I Discovery Audio Slot TDM mode
+  * @brief In W8994 codec the Audio frame contains 4 slots : TDM Mode
+  * TDM format :
+  * +------------------|------------------|--------------------|-------------------+
+  * | CODEC_SLOT0 Left | CODEC_SLOT1 Left | CODEC_SLOT0 Right  | CODEC_SLOT1 Right |
+  * +------------------------------------------------------------------------------+
+  * @{
+  */
+/* To have 2 separate audio stream in Both headphone and speaker the 4 slot must be activated */
+#define CODEC_AUDIOFRAME_SLOT_0123                   SAI_SLOTACTIVE_0 | SAI_SLOTACTIVE_1 | SAI_SLOTACTIVE_2 | SAI_SLOTACTIVE_3
+/* To have an audio stream in headphone only SAI Slot 0 and Slot 2 must be activated */
+#define CODEC_AUDIOFRAME_SLOT_02                     SAI_SLOTACTIVE_0 | SAI_SLOTACTIVE_2
+/* To have an audio stream in speaker only SAI Slot 1 and Slot 3 must be activated */
+#define CODEC_AUDIOFRAME_SLOT_13                     SAI_SLOTACTIVE_1 | SAI_SLOTACTIVE_3
+/**
+  * @}
+  */
+
+/* SAI peripheral configuration defines */
+#define AUDIO_SAIx                           SAI1_Block_A
+#define AUDIO_SAIx_CLK_ENABLE()              __HAL_RCC_SAI1_CLK_ENABLE()
+#define AUDIO_SAIx_CLK_DISABLE()             __HAL_RCC_SAI1_CLK_DISABLE()
+#define AUDIO_SAIx_MCLK_SCK_SD_FS_AF         GPIO_AF6_SAI1
+
+#define AUDIO_SAIx_MCLK_ENABLE()             __HAL_RCC_GPIOG_CLK_ENABLE()
+#define AUDIO_SAIx_MCLK_DISABLE()            __HAL_RCC_GPIOG_CLK_DISABLE()
+
+#define AUDIO_SAIx_MCK_PIN                   GPIO_PIN_7
+#define AUDIO_SAIx_MCLK_GPIO_PORT            GPIOG
+
+#define AUDIO_SAIx_SCK_SD_FS_ENABLE()        __HAL_RCC_GPIOE_CLK_ENABLE()
+#define AUDIO_SAIx_SCK_SD_FS_DISABLE()       __HAL_RCC_GPIOE_CLK_DISABLE()
+#define AUDIO_SAIx_FS_PIN                    GPIO_PIN_4
+#define AUDIO_SAIx_SCK_PIN                   GPIO_PIN_5
+#define AUDIO_SAIx_SD_PIN                    GPIO_PIN_6
+#define AUDIO_SAIx_SCK_SD_FS_GPIO_PORT       GPIOE
+
+#define AUDIO_RESET_ENABLE()                 __HAL_RCC_GPIOE_CLK_ENABLE()
+#define AUDIO_RESET_DISABLE()                __HAL_RCC_GPIOE_CLK_DISABLE()
+#define AUDIO_RESET_PIN                      GPIO_PIN_2
+#define AUDIO_RESET_GPIO_PORT                GPIOE
+
+/* SAI DMA Stream definitions */
+#define AUDIO_SAIx_DMAx_CLK_ENABLE()         __HAL_RCC_DMA2_CLK_ENABLE()
+#define AUDIO_SAIx_DMAx_CLK_DISABLE()        __HAL_RCC_DMA2_CLK_DISABLE()
+#define AUDIO_SAIx_DMAx_STREAM               DMA2_Stream3
+#define AUDIO_SAIx_DMAx_CHANNEL              DMA_CHANNEL_0
+#define AUDIO_SAIx_DMAx_IRQ                  DMA2_Stream3_IRQn
+#define AUDIO_SAIx_DMAx_PERIPH_DATA_SIZE     DMA_PDATAALIGN_HALFWORD
+#define AUDIO_SAIx_DMAx_MEM_DATA_SIZE        DMA_MDATAALIGN_HALFWORD
+#define DMA_MAX_SZE                          0xFFFF
+
+#define AUDIO_SAIx_DMAx_IRQHandler           DMA2_Stream3_IRQHandler
+
+/* Select the interrupt preemption priority for the DMA interrupt */
+#define AUDIO_OUT_IRQ_PREPRIO           5   /* Select the preemption priority level(0 is the highest) */
+
+/* Disable SAIx PLL */
+#define AUDIO_SAIx_PLL_DISABLE()             HAL_RCCEx_DisablePLLSAI1()
+/*------------------------------------------------------------------------------
+                        AUDIO IN CONFIGURATION
+------------------------------------------------------------------------------*/
+/* SPI Configuration defines */
+#define AUDIO_I2Sx                           SPI3
+#define AUDIO_I2Sx_CLK_ENABLE()              __HAL_RCC_SPI3_CLK_ENABLE()
+#define AUDIO_I2Sx_CLK_DISABLE()             __HAL_RCC_SPI3_CLK_DISABLE()
+#define AUDIO_I2Sx_SCK_PIN                   GPIO_PIN_3
+#define AUDIO_I2Sx_SCK_GPIO_PORT             GPIOB
+#define AUDIO_I2Sx_SCK_GPIO_CLK_ENABLE()     __HAL_RCC_GPIOB_CLK_ENABLE()
+#define AUDIO_I2Sx_SCK_GPIO_CLK_DISABLE()    __HAL_RCC_GPIOB_CLK_DISABLE()
+#define AUDIO_I2Sx_SCK_AF                    GPIO_AF6_SPI3
+
+#define AUDIO_I2Sx_SD_PIN                    GPIO_PIN_6
+#define AUDIO_I2Sx_SD_GPIO_PORT              GPIOD
+#define AUDIO_I2Sx_SD_GPIO_CLK_ENABLE()      __HAL_RCC_GPIOD_CLK_ENABLE()
+#define AUDIO_I2Sx_SD_GPIO_CLK_DISABLE()     __HAL_RCC_GPIOD_CLK_DISABLE()
+#define AUDIO_I2Sx_SD_AF                     GPIO_AF5_I2S3ext
+
+/* I2S DMA Stream Rx definitions */
+#define AUDIO_I2Sx_DMAx_CLK_ENABLE()        __HAL_RCC_DMA1_CLK_ENABLE()
+#define AUDIO_I2Sx_DMAx_CLK_DISABLE()       __HAL_RCC_DMA1_CLK_DISABLE()
+#define AUDIO_I2Sx_DMAx_STREAM              DMA1_Stream2
+#define AUDIO_I2Sx_DMAx_CHANNEL             DMA_CHANNEL_0
+#define AUDIO_I2Sx_DMAx_IRQ                 DMA1_Stream2_IRQn
+#define AUDIO_I2Sx_DMAx_PERIPH_DATA_SIZE    DMA_PDATAALIGN_HALFWORD
+#define AUDIO_I2Sx_DMAx_MEM_DATA_SIZE       DMA_MDATAALIGN_HALFWORD
+
+#define AUDIO_I2Sx_DMAx_IRQHandler          DMA1_Stream2_IRQHandler
+
+/* Select the interrupt preemption priority and subpriority for the IT/DMA interrupt */
+#define AUDIO_IN_IRQ_PREPRIO                ((uint32_t)6)   /* Select the preemption priority level(0 is the highest) */
+
+
+/* Two channels are used:
+   - one channel as input which is connected to I2S SCK in stereo mode
+   - one channel as outupt which divides the frequency on the input
+*/
+
+#define AUDIO_TIMx_CLK_ENABLE()             __HAL_RCC_TIM4_CLK_ENABLE()
+#define AUDIO_TIMx_CLK_DISABLE()            __HAL_RCC_TIM4_CLK_DISABLE()
+#define AUDIO_TIMx                          TIM4
+#define AUDIO_TIMx_IN_CHANNEL               TIM_CHANNEL_1
+#define AUDIO_TIMx_OUT_CHANNEL              TIM_CHANNEL_2 /* Select channel 2 as output */
+#define AUDIO_TIMx_GPIO_CLK_ENABLE()        __HAL_RCC_GPIOD_CLK_ENABLE()
+#define AUDIO_TIMx_GPIO_CLK_DISABLE()       __HAL_RCC_GPIOD_CLK_DISABLE()
+#define AUDIO_TIMx_GPIO_PORT                GPIOD
+#define AUDIO_TIMx_IN_GPIO_PIN              GPIO_PIN_12
+#define AUDIO_TIMx_OUT_GPIO_PIN             GPIO_PIN_13
+#define AUDIO_TIMx_AF                       GPIO_AF2_TIM4
+
+/*------------------------------------------------------------------------------
+             CONFIGURATION: Audio Driver Configuration parameters
+------------------------------------------------------------------------------*/
+
+#define AUDIODATA_SIZE                      2   /* 16-bits audio data size */
+
+/* Audio status definition */
+#define AUDIO_OK                            ((uint8_t)0)
+#define AUDIO_ERROR                         ((uint8_t)1)
+#define AUDIO_TIMEOUT                       ((uint8_t)2)
+
+/* AudioFreq * DataSize (2 bytes) * NumChannels (Stereo: 2) */
+#define DEFAULT_AUDIO_IN_FREQ               I2S_AUDIOFREQ_16K
+#define DEFAULT_AUDIO_IN_BIT_RESOLUTION     ((uint8_t)16)
+#define DEFAULT_AUDIO_IN_CHANNEL_NBR        ((uint8_t)2) /* Mono = 1, Stereo = 2 */
+#define DEFAULT_AUDIO_IN_VOLUME             ((uint16_t)64)
+
+/* PDM buffer input size */
+#define INTERNAL_BUFF_SIZE                  (128*DEFAULT_AUDIO_IN_FREQ/16000*DEFAULT_AUDIO_IN_CHANNEL_NBR)
+/* PCM buffer output size */
+#define PCM_OUT_SIZE                        (DEFAULT_AUDIO_IN_FREQ/1000*DEFAULT_AUDIO_IN_CHANNEL_NBR)
+#define CHANNEL_DEMUX_MASK                  ((uint8_t)0x55)
+
+/*------------------------------------------------------------------------------
+                    OPTIONAL Configuration defines parameters
+------------------------------------------------------------------------------*/
+
+/* Delay for the Codec to be correctly reset */
+#define CODEC_RESET_DELAY           ((uint8_t)5)
+
+/*------------------------------------------------------------------------------
+                            OUTPUT DEVICES definition
+------------------------------------------------------------------------------*/
+
+/**
+  * @}
+  */
+
+/** @defgroup STM32469I-Discovery_AUDIO_Exported_Variables  STM32469I-Discovery AUDIO Exported Variables
+  * @{
+  */
+extern __IO uint16_t AudioInVolume;
+ /**
+  * @}
+  */
+
+/** @defgroup STM32469I-Discovery_AUDIO_Exported_Macros STM32469I-Discovery AUDIO Exported Macros
+  * @{
+  */
+#define DMA_MAX(x)           (((x) <= DMA_MAX_SZE)? (x):DMA_MAX_SZE)
+/**
+  * @}
+  */
+
+/** @defgroup STM32469I-Discovery_AUDIO_OUT_Exported_Functions  STM32469I Discovery AUDIO OUT Exported Functions
+  * @{
+  */
+uint8_t BSP_AUDIO_OUT_Init(uint16_t OutputDevice, uint8_t Volume, uint32_t AudioFreq);
+uint8_t BSP_AUDIO_OUT_Play(uint16_t* pBuffer, uint32_t Size);
+void    BSP_AUDIO_OUT_ChangeBuffer(uint16_t *pData, uint16_t Size);
+uint8_t BSP_AUDIO_OUT_Pause(void);
+uint8_t BSP_AUDIO_OUT_Resume(void);
+uint8_t BSP_AUDIO_OUT_Stop(uint32_t Option);
+uint8_t BSP_AUDIO_OUT_SetVolume(uint8_t Volume);
+void    BSP_AUDIO_OUT_SetFrequency(uint32_t AudioFreq);
+void    BSP_AUDIO_OUT_SetAudioFrameSlot(uint32_t AudioFrameSlot);
+uint8_t BSP_AUDIO_OUT_SetMute(uint32_t Cmd);
+uint8_t BSP_AUDIO_OUT_SetOutputMode(uint8_t Output);
+void    BSP_AUDIO_OUT_DeInit(void);
+
+/* User Callbacks: user has to implement these functions in his code if they are needed. */
+/* This function is called when the requested data has been completely transferred.*/
+void    BSP_AUDIO_OUT_TransferComplete_CallBack(void);
+
+/* This function is called when half of the requested buffer has been transferred. */
+void    BSP_AUDIO_OUT_HalfTransfer_CallBack(void);
+
+/* This function is called when an Interrupt due to transfer error on or peripheral
+   error occurs. */
+void    BSP_AUDIO_OUT_Error_CallBack(void);
+
+/* These function can be modified in case the current settings (e.g. DMA stream)
+   need to be changed for specific application needs */
+void  BSP_AUDIO_OUT_ClockConfig(SAI_HandleTypeDef *hsai, uint32_t AudioFreq, void *Params);
+void  BSP_AUDIO_OUT_MspInit(SAI_HandleTypeDef *hsai, void *Params);
+void  BSP_AUDIO_OUT_MspDeInit(SAI_HandleTypeDef *hsai, void *Params);
+
+/**
+  * @}
+  */
+
+/** @defgroup STM32469I-Discovery_AUDIO_IN_Exported_Functions  STM32469I Discovery AUDIO IN Exported Functions
+  * @{
+  */
+uint8_t BSP_AUDIO_IN_Init(uint32_t AudioFreq, uint32_t BitRes, uint32_t ChnlNbr);
+uint8_t BSP_AUDIO_IN_Record(uint16_t *pData, uint32_t Size);
+uint8_t BSP_AUDIO_IN_Stop(void);
+uint8_t BSP_AUDIO_IN_Pause(void);
+uint8_t BSP_AUDIO_IN_Resume(void);
+uint8_t BSP_AUDIO_IN_SetVolume(uint8_t Volume);
+void    BSP_AUDIO_IN_DeInit(void);
+uint8_t BSP_AUDIO_IN_PDMToPCM(uint16_t* PDMBuf, uint16_t* PCMBuf);
+/* User Callbacks: user has to implement these functions in his code if they are needed. */
+/* This function should be implemented by the user application.
+   It is called into this driver when the current buffer is filled to prepare the next
+   buffer pointer and its size. */
+void    BSP_AUDIO_IN_TransferComplete_CallBack(void);
+void    BSP_AUDIO_IN_HalfTransfer_CallBack(void);
+
+/* This function is called when an Interrupt due to transfer error on or peripheral
+   error occurs. */
+void    BSP_AUDIO_IN_Error_Callback(void);
+
+/* These function can be modified in case the current settings (e.g. DMA stream)
+   need to be changed for specific application needs */
+void  BSP_AUDIO_IN_ClockConfig(I2S_HandleTypeDef *hi2s, void *Params);   
+void  BSP_AUDIO_IN_MspInit(I2S_HandleTypeDef *hi2s, void *Params);
+void  BSP_AUDIO_IN_MspDeInit(I2S_HandleTypeDef *hi2s, void *Params);
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32469I_DISCOVERY_AUDIO_H */
diff --git a/Drivers/BSP/STM32469I-Discovery/stm32469i_discovery_eeprom.c b/Drivers/BSP/STM32469I-Discovery/stm32469i_discovery_eeprom.c
new file mode 100644
index 0000000..27eac6d
--- /dev/null
+++ b/Drivers/BSP/STM32469I-Discovery/stm32469i_discovery_eeprom.c
@@ -0,0 +1,453 @@
+/**
+  ******************************************************************************
+  * @file    stm32469i_discovery_eeprom.c
+  * @author  MCD Application Team
+  * @brief   This file provides a set of functions needed to manage an I2C M24LR64 
+  *          EEPROM memory.
+  *          To be able to use this driver, the switch EE_M24LR64 must be defined
+  *          in your toolchain compiler preprocessor
+  *          
+  *          =================================================================== 
+  *          Notes:
+  *           - This driver is intended for STM32F4xx families devices only. 
+  *           - The I2C EEPROM memory (M24LR64) is available on separate daughter 
+  *             board ANT7-M24LR-A, which is not provided with the STM32469I-Discovery
+  *             board.
+  *             To use this driver you have to connect the ANT7-M24LR-A to CN11
+  *             connector of STM32469I-Discovery board.
+  *          ===================================================================
+  *              
+  *          It implements a high level communication layer for read and write 
+  *          from/to this memory. The needed STM32F4xx hardware resources (I2C and 
+  *          GPIO) are defined in stm32469i_discovery.h file, and the initialization is
+  *          performed in EEPROM_IO_Init() function declared in stm32469i_discovery.c
+  *          file.
+  *          You can easily tailor this driver to any other development board, 
+  *          by just adapting the defines for hardware resources and 
+  *          EEPROM_IO_Init() function. 
+  *        
+  *          @note In this driver, basic read and write functions (BSP_EEPROM_ReadBuffer() 
+  *                and BSP_EEPROM_WritePage()) use DMA mode to perform the data 
+  *                transfer to/from EEPROM memory.
+  *
+  *         @note   Regarding BSP_EEPROM_WritePage(), it is a optimized function to perform
+  *                small write (less than 1 page) BUT The number of bytes (combined to write start address) must not 
+  *                cross the EEPROM page boundary. This function can only write into
+  *                the boundaries of an EEPROM page.
+  *                This function doesn't check on boundaries condition (in this driver 
+  *                the function BSP_EEPROM_WriteBuffer() which calls BSP_EEPROM_WritePage() is 
+  *                responsible of checking on Page boundaries).
+  * 
+  *             
+  *     +-----------------------------------------------------------------+
+  *     |               Pin assignment for M24LR64 EEPROM                 |
+  *     +---------------------------------------+-----------+-------------+
+  *     |  STM32F4xx I2C Pins                   |   EEPROM  |   Pin       |
+  *     +---------------------------------------+-----------+-------------+
+  *     | .                                     |   E0(GND) |    1  (0V)  |
+  *     | .                                     |   AC0     |    2        |
+  *     | .                                     |   AC1     |    3        |
+  *     | .                                     |   VSS     |    4  (0V)  |
+  *     | SDA                                   |   SDA     |    5        |
+  *     | SCL                                   |   SCL     |    6        |
+  *     | .                                     |   E1(GND) |    7  (0V)  |
+  *     | .                                     |   VDD     |    8 (3.3V) |
+  *     +---------------------------------------+-----------+-------------+
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+/* Includes ------------------------------------------------------------------*/
+#include "stm32469i_discovery_eeprom.h"
+
+/** @addtogroup BSP
+  * @{
+  */
+  
+/** @addtogroup STM32469I_Discovery
+  * @{
+  */ 
+  
+/** @defgroup STM32469I-Discovery_EEPROM STM32469I Discovery EEPROM
+  * @brief This file includes the I2C EEPROM driver of STM32469I-Discovery board.
+  * @{
+  */ 
+
+/** @defgroup STM32469I-Discovery_EEPROM_Private_Types STM32469I Discovery EEPROM Private Types
+  * @{
+  */ 
+/**
+  * @}
+  */ 
+
+/** @defgroup STM32469I-Discovery_EEPROM_Private_Defines STM32469I Discovery EEPROM Private Defines
+  * @{
+  */  
+/**
+  * @}
+  */ 
+
+/** @defgroup STM32469I-Discovery_EEPROM_Private_Macros STM32469I Discovery EEPROM Private Macros
+  * @{
+  */
+/**
+  * @}
+  */ 
+  
+/** @defgroup STM32469I-Discovery_EEPROM_Private_Variables STM32469I Discovery EEPROM Private Variables
+  * @{
+  */
+__IO uint16_t EEPROMAddress = 0;
+__IO uint32_t EEPROMTimeout = EEPROM_READ_TIMEOUT;
+__IO uint16_t EEPROMDataRead;
+__IO uint8_t  EEPROMDataWrite;
+/**
+  * @}
+  */ 
+
+/** @defgroup STM32469I-Discovery_EEPROM_Private_Function_Prototypes STM32469I Discovery EEPROM Private Prototypes
+  * @{
+  */ 
+/**
+  * @}
+  */ 
+
+/** @defgroup STM32469I-Discovery_EEPROM_Private_Functions STM32469I Discovery EEPROM Private Functions
+  * @{
+  */ 
+
+/**
+  * @brief  Initializes peripherals used by the I2C EEPROM driver.
+  * 
+  * @note   There are 2 different versions of M24LR64 (A01 & A02).
+  *             Then try to connect on 1st one (EEPROM_I2C_ADDRESS_A01) 
+  *             and if problem, check the 2nd one (EEPROM_I2C_ADDRESS_A02)
+  * @retval EEPROM_OK (0) if operation is correctly performed, else return value 
+  *         different from EEPROM_OK (0)
+  */
+uint32_t BSP_EEPROM_Init(void)
+{ 
+  /* I2C Initialization */
+  EEPROM_IO_Init();
+  
+  /* Select the EEPROM address for A01 and check if OK */
+  EEPROMAddress = EEPROM_I2C_ADDRESS_A01;
+  if(EEPROM_IO_IsDeviceReady(EEPROMAddress, EEPROM_MAX_TRIALS) != HAL_OK) 
+  {
+    /* Select the EEPROM address for A02 and check if OK */
+    EEPROMAddress = EEPROM_I2C_ADDRESS_A02;
+    if(EEPROM_IO_IsDeviceReady(EEPROMAddress, EEPROM_MAX_TRIALS) != HAL_OK)
+    {
+      return EEPROM_FAIL;
+    }
+  }
+  return EEPROM_OK;
+}
+
+/**
+  * @brief  DeInitializes the EEPROM.
+  * @retval EEPROM state
+  */
+uint8_t BSP_EEPROM_DeInit(void)
+{ 
+  /* I2C won't be disabled because common to other functionalities */
+  return EEPROM_OK;
+}
+
+/**
+  * @brief  Reads a block of data from the EEPROM.
+  * @param  pBuffer: pointer to the buffer that receives the data read from 
+  *         the EEPROM.
+  * @param  ReadAddr: EEPROM's internal address to start reading from.
+  * @param  NumByteToRead: pointer to the variable holding number of bytes to 
+  *         be read from the EEPROM.
+  * 
+  *        @note The variable pointed by NumByteToRead is reset to 0 when all the 
+  *              data are read from the EEPROM. Application should monitor this 
+  *              variable in order know when the transfer is complete.
+  * 
+  * @retval EEPROM_OK (0) if operation is correctly performed, else return value 
+  *         different from EEPROM_OK (0) or the timeout user callback.
+  */
+uint32_t BSP_EEPROM_ReadBuffer(uint8_t* pBuffer, uint16_t ReadAddr, uint16_t* NumByteToRead)
+{  
+  uint32_t buffersize = *NumByteToRead;
+  
+  /* Set the pointer to the Number of data to be read. This pointer will be used 
+     by the DMA Transfer Completer interrupt Handler in order to reset the 
+     variable to 0. User should check on this variable in order to know if the 
+     DMA transfer has been complete or not. */
+  EEPROMDataRead = *NumByteToRead;
+  
+  if(EEPROM_IO_ReadData(EEPROMAddress, ReadAddr, pBuffer, buffersize) != HAL_OK)
+  {
+    BSP_EEPROM_TIMEOUT_UserCallback();
+    return EEPROM_FAIL;
+  }
+
+  /* If all operations OK, return EEPROM_OK (0) */
+  return EEPROM_OK;
+}
+
+/**
+  * @brief  Writes more than one byte to the EEPROM with a single WRITE cycle.
+  *
+  * @note   The number of bytes (combined to write start address) must not 
+  *         cross the EEPROM page boundary. This function can only write into
+  *         the boundaries of an EEPROM page.
+  *         This function doesn't check on boundaries condition (in this driver 
+  *         the function BSP_EEPROM_WriteBuffer() which calls BSP_EEPROM_WritePage() is 
+  *         responsible of checking on Page boundaries).
+  * 
+  * @param  pBuffer: pointer to the buffer containing the data to be written to 
+  *         the EEPROM.
+  * @param  WriteAddr: EEPROM's internal address to write to.
+  * @param  NumByteToWrite: pointer to the variable holding number of bytes to 
+  *         be written into the EEPROM. 
+  * 
+  *        @note The variable pointed by NumByteToWrite is reset to 0 when all the 
+  *              data are written to the EEPROM. Application should monitor this 
+  *              variable in order know when the transfer is complete.
+  * 
+  *        @note This function just configure the communication and enable the DMA 
+  *              channel to transfer data. Meanwhile, the user application may perform 
+  *              other tasks in parallel.
+  * 
+  * @retval EEPROM_OK (0) if operation is correctly performed, else return value 
+  *         different from EEPROM_OK (0) or the timeout user callback.
+  */
+uint32_t BSP_EEPROM_WritePage(uint8_t* pBuffer, uint16_t WriteAddr, uint8_t* NumByteToWrite)
+{ 
+  uint32_t buffersize = *NumByteToWrite;
+  uint32_t status = EEPROM_OK;
+  
+  /* Set the pointer to the Number of data to be written. This pointer will be used 
+      by the DMA Transfer Completer interrupt Handler in order to reset the 
+      variable to 0. User should check on this variable in order to know if the 
+      DMA transfer has been complete or not. */
+  EEPROMDataWrite = *NumByteToWrite;  
+  
+  if(EEPROM_IO_WriteData(EEPROMAddress, WriteAddr, pBuffer, buffersize) != HAL_OK)
+  {
+    BSP_EEPROM_TIMEOUT_UserCallback();
+    status = EEPROM_FAIL;
+  }
+  
+  if(BSP_EEPROM_WaitEepromStandbyState() != EEPROM_OK) 
+  {
+    return EEPROM_FAIL;
+  }
+  
+  /* If all operations OK, return EEPROM_OK (0) */
+  return status;
+}
+
+/**
+  * @brief  Writes buffer of data to the I2C EEPROM.
+  * @param  pBuffer: pointer to the buffer  containing the data to be written 
+  *         to the EEPROM.
+  * @param  WriteAddr: EEPROM's internal address to write to.
+  * @param  NumByteToWrite: number of bytes to write to the EEPROM.
+  * @retval EEPROM_OK (0) if operation is correctly performed, else return value 
+  *         different from EEPROM_OK (0) or the timeout user callback.
+  */
+uint32_t BSP_EEPROM_WriteBuffer(uint8_t *pBuffer, uint16_t WriteAddr, uint16_t NumByteToWrite)
+{
+  uint16_t numofpage = 0, numofsingle = 0, count = 0;
+  uint16_t addr = 0;
+  uint8_t  dataindex = 0;
+  uint32_t status = EEPROM_OK;
+
+  addr = WriteAddr % EEPROM_PAGESIZE;
+  count = EEPROM_PAGESIZE - addr;
+  numofpage =  NumByteToWrite / EEPROM_PAGESIZE;
+  numofsingle = NumByteToWrite % EEPROM_PAGESIZE;
+ 
+  /* If WriteAddr is EEPROM_PAGESIZE aligned */
+  if(addr == 0) 
+  {
+    /* If NumByteToWrite < EEPROM_PAGESIZE */
+    if(numofpage == 0) 
+    {
+      /* Store the number of data to be written */
+      dataindex = numofsingle;
+      /* Start writing data */
+      status = BSP_EEPROM_WritePage(pBuffer, WriteAddr, (uint8_t*)(&dataindex));
+      if(status != EEPROM_OK)
+      {
+        return status;
+      }
+    }
+    /* If NumByteToWrite > EEPROM_PAGESIZE */
+    else  
+    {
+      while(numofpage--)
+      {
+        /* Store the number of data to be written */
+        dataindex = EEPROM_PAGESIZE;        
+        status = BSP_EEPROM_WritePage(pBuffer, WriteAddr, (uint8_t*)(&dataindex));
+        if(status != EEPROM_OK)
+        {
+          return status;
+        }
+        
+        WriteAddr +=  EEPROM_PAGESIZE;
+        pBuffer += EEPROM_PAGESIZE;
+      }
+      
+      if(numofsingle!=0)
+      {
+        /* Store the number of data to be written */
+        dataindex = numofsingle;          
+        status = BSP_EEPROM_WritePage(pBuffer, WriteAddr, (uint8_t*)(&dataindex));
+        if(status != EEPROM_OK)
+        {
+          return status;
+        }
+      }
+    }
+  }
+  /* If WriteAddr is not EEPROM_PAGESIZE aligned */
+  else 
+  {
+    /* If NumByteToWrite < EEPROM_PAGESIZE */
+    if(numofpage== 0) 
+    {
+      /* If the number of data to be written is more than the remaining space 
+      in the current page: */
+      if(NumByteToWrite > count)
+      {
+        /* Store the number of data to be written */
+        dataindex = count;        
+        /* Write the data contained in same page */
+        status = BSP_EEPROM_WritePage(pBuffer, WriteAddr, (uint8_t*)(&dataindex));
+        if(status != EEPROM_OK)
+        {
+          return status;
+        }
+        
+        /* Store the number of data to be written */
+        dataindex = (NumByteToWrite - count);          
+        /* Write the remaining data in the following page */
+        status = BSP_EEPROM_WritePage((uint8_t*)(pBuffer + count), (WriteAddr + count), (uint8_t*)(&dataindex));
+        if(status != EEPROM_OK)
+        {
+          return status;
+        }
+      }      
+      else      
+      {
+        /* Store the number of data to be written */
+        dataindex = numofsingle;         
+        status = BSP_EEPROM_WritePage(pBuffer, WriteAddr, (uint8_t*)(&dataindex));
+        if(status != EEPROM_OK)
+        {
+          return status;
+        }
+      }     
+    }
+    /* If NumByteToWrite > EEPROM_PAGESIZE */
+    else
+    {
+      NumByteToWrite -= count;
+      numofpage =  NumByteToWrite / EEPROM_PAGESIZE;
+      numofsingle = NumByteToWrite % EEPROM_PAGESIZE;
+      
+      if(count != 0)
+      {  
+        /* Store the number of data to be written */
+        dataindex = count;         
+        status = BSP_EEPROM_WritePage(pBuffer, WriteAddr, (uint8_t*)(&dataindex));
+        if(status != EEPROM_OK)
+        {
+          return status;
+        }
+        WriteAddr += count;
+        pBuffer += count;
+      } 
+      
+      while(numofpage--)
+      {
+        /* Store the number of data to be written */
+        dataindex = EEPROM_PAGESIZE;          
+        status = BSP_EEPROM_WritePage(pBuffer, WriteAddr, (uint8_t*)(&dataindex));
+        if(status != EEPROM_OK)
+        {
+          return status;
+        }
+        WriteAddr +=  EEPROM_PAGESIZE;
+        pBuffer += EEPROM_PAGESIZE;  
+      }
+      if(numofsingle != 0)
+      {
+        /* Store the number of data to be written */
+        dataindex = numofsingle;           
+        status = BSP_EEPROM_WritePage(pBuffer, WriteAddr, (uint8_t*)(&dataindex));
+        if(status != EEPROM_OK)
+        {
+          return status;
+        }
+      }
+    }
+  }  
+                                   
+  /* If all operations OK, return EEPROM_OK (0) */
+  return EEPROM_OK;
+}
+
+/**
+  * @brief  Wait for EEPROM Standby state.
+  * 
+  * @note  This function allows to wait and check that EEPROM has finished the 
+  *        last operation. It is mostly used after Write operation: after receiving
+  *        the buffer to be written, the EEPROM may need additional time to actually
+  *        perform the write operation. During this time, it doesn't answer to
+  *        I2C packets addressed to it. Once the write operation is complete
+  *        the EEPROM responds to its address.
+  * 
+  * @retval EEPROM_OK (0) if operation is correctly performed, else return value 
+  *         different from EEPROM_OK (0) or the timeout user callback.
+  */
+uint32_t BSP_EEPROM_WaitEepromStandbyState(void)      
+{
+  /* Check if the maximum allowed number of trials has bee reached */
+  if(EEPROM_IO_IsDeviceReady(EEPROMAddress, EEPROM_MAX_TRIALS) != HAL_OK)
+  {
+    /* If the maximum number of trials has been reached, exit the function */
+    BSP_EEPROM_TIMEOUT_UserCallback();
+    return EEPROM_TIMEOUT;
+  }
+  return EEPROM_OK;
+}
+
+/**
+  * @brief  Basic management of the timeout situation.
+  */
+__weak void BSP_EEPROM_TIMEOUT_UserCallback(void)
+{
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
diff --git a/Drivers/BSP/STM32469I-Discovery/stm32469i_discovery_eeprom.h b/Drivers/BSP/STM32469I-Discovery/stm32469i_discovery_eeprom.h
new file mode 100644
index 0000000..baf8195
--- /dev/null
+++ b/Drivers/BSP/STM32469I-Discovery/stm32469i_discovery_eeprom.h
@@ -0,0 +1,125 @@
+/**
+  ******************************************************************************
+  * @file    stm32469i_discovery_eeprom.h
+  * @author  MCD Application Team
+  * @brief   This file contains all the functions prototypes for
+  *          the stm32469i_discovery_eeprom.c firmware driver.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F469I_DISCOVERY_EEPROM_H
+#define __STM32F469I_DISCOVERY_EEPROM_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32469i_discovery.h"
+
+/** @addtogroup BSP
+  * @{
+  */
+
+/** @addtogroup STM32469I_Discovery
+  * @{
+  */
+
+/** @addtogroup STM32469I-Discovery_EEPROM
+  * @brief This file includes the I2C EEPROM driver of STM32469I-Discovery board.
+  * @{
+  */
+
+/** @defgroup STM32469I-Discovery_EEPROM_Exported_Types STM32469I Discovery EEPROM Exported Types
+  * @{
+  */
+/**
+  * @}
+  */
+
+/** @defgroup STM32469I-Discovery_EEPROM_Exported_Constants STM32469I Discovery EEPROM Exported Constants
+  * @{
+  */
+/* EEPROM hardware address and page size */
+#define EEPROM_PAGESIZE             ((uint8_t)4)
+#define EEPROM_MAX_SIZE             ((uint16_t)0x2000) /* 64Kbit */
+
+/* Maximum Timeout values for flags and events waiting loops.
+This timeout is based on systick set to 1ms*/
+/* Timeout for read based if read all the EEPROM : EEPROM_MAX_SIZE * I2C_SPEED (640ms) */
+#define EEPROM_READ_TIMEOUT         ((uint32_t)(1000))
+/* Timeout for write based on max write which is EEPROM_PAGESIZE bytes: EEPROM_PAGESIZE * I2C_SPEED (320us) */
+#define EEPROM_WRITE_TIMEOUT         ((uint32_t)(10))
+
+/* Maximum number of trials for EEPROM_WaitEepromStandbyState() function */
+#define EEPROM_MAX_TRIALS           3000
+
+#define EEPROM_OK                   0
+#define EEPROM_FAIL                 1
+#define EEPROM_TIMEOUT              2
+/**
+  * @}
+  */
+
+/** @defgroup STM32469I-Discovery_EEPROM_Exported_Macros STM32469I Discovery EEPROM Exported Macros
+  * @{
+  */
+/**
+  * @}
+  */
+
+/** @defgroup STM32469I-Discovery_EEPROM_Exported_Functions STM32469I Discovery EEPROM Exported Functions
+  * @{
+  */
+uint32_t BSP_EEPROM_Init(void);
+uint8_t  BSP_EEPROM_DeInit(void);
+uint32_t BSP_EEPROM_ReadBuffer(uint8_t* pBuffer, uint16_t ReadAddr, uint16_t* NumByteToRead);
+uint32_t BSP_EEPROM_WritePage(uint8_t* pBuffer, uint16_t WriteAddr, uint8_t* NumByteToWrite);
+uint32_t BSP_EEPROM_WriteBuffer(uint8_t* pBuffer, uint16_t WriteAddr, uint16_t NumByteToWrite);
+uint32_t BSP_EEPROM_WaitEepromStandbyState(void);
+
+/* USER Callbacks: This function is declared as __weak in EEPROM driver and
+   should be implemented into user application.
+   BSP_EEPROM_TIMEOUT_UserCallback() function is called whenever a timeout condition
+   occure during communication (waiting on an event that doesn't occur, bus
+   errors, busy devices ...). */
+void     BSP_EEPROM_TIMEOUT_UserCallback(void);
+
+/* Link function for I2C EEPROM peripheral */
+void              EEPROM_IO_Init(void);
+HAL_StatusTypeDef EEPROM_IO_WriteData(uint16_t DevAddress, uint16_t MemAddress, uint8_t *pBuffer, uint32_t BufferSize);
+HAL_StatusTypeDef EEPROM_IO_ReadData(uint16_t DevAddress, uint16_t MemAddress, uint8_t *pBuffer, uint32_t BufferSize);
+HAL_StatusTypeDef EEPROM_IO_IsDeviceReady(uint16_t DevAddress, uint32_t Trials);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F469I_DISCOVERY_EEPROM_H */
diff --git a/Drivers/BSP/STM32469I-Discovery/stm32469i_discovery_lcd.c b/Drivers/BSP/STM32469I-Discovery/stm32469i_discovery_lcd.c
new file mode 100644
index 0000000..6a4515b
--- /dev/null
+++ b/Drivers/BSP/STM32469I-Discovery/stm32469i_discovery_lcd.c
@@ -0,0 +1,1649 @@
+/**
+  ******************************************************************************
+  * @file    stm32469i_discovery_lcd.c
+  * @author  MCD Application Team
+  * @brief   This file includes the driver for Liquid Crystal Display (LCD) module
+  *          mounted on STM32469I-Discovery evaluation board.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* File Info: ------------------------------------------------------------------
+                                   User NOTES
+1. How To use this driver:
+--------------------------
+   - This driver is used to drive directly in video mode a LCD TFT using the DSI interface.
+     The following IPs are implied : DSI Host IP block working
+     in conjunction to the LTDC controller.
+   - This driver is linked by construction to LCD KoD mounted on board MB1166.
+
+2. Driver description:
+---------------------
+  + Initialization steps:
+     o Initialize the LCD using the BSP_LCD_Init() function.
+     o Select the LCD layer to be used using the BSP_LCD_SelectLayer() function.
+     o Enable the LCD display using the BSP_LCD_DisplayOn() function.
+
+  + Options
+     o Configure and enable the color keying functionality using the
+       BSP_LCD_SetColorKeying() function.
+     o Modify in the fly the transparency and/or the frame buffer address
+       using the following functions:
+       - BSP_LCD_SetTransparency()
+       - BSP_LCD_SetLayerAddress()
+
+  + Display on LCD
+     o Clear the whole LCD using BSP_LCD_Clear() function or only one specified string
+       line using the BSP_LCD_ClearStringLine() function.
+     o Display a character on the specified line and column using the BSP_LCD_DisplayChar()
+       function or a complete string line using the BSP_LCD_DisplayStringAtLine() function.
+     o Display a string line on the specified position (x,y in pixel) and align mode
+       using the BSP_LCD_DisplayStringAtLine() function.
+     o Draw and fill a basic shapes (dot, line, rectangle, circle, ellipse, .. bitmap)
+       on LCD using the available set of functions.
+
+------------------------------------------------------------------------------*/
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32469i_discovery_lcd.h"
+#include "../../../Utilities/Fonts/fonts.h"
+#include "../../../Utilities/Fonts/font24.c"
+#include "../../../Utilities/Fonts/font20.c"
+#include "../../../Utilities/Fonts/font16.c"
+#include "../../../Utilities/Fonts/font12.c"
+#include "../../../Utilities/Fonts/font8.c"
+
+/** @addtogroup BSP
+  * @{
+  */
+
+/** @addtogroup STM32469I_Discovery
+  * @{
+  */
+
+/** @defgroup STM32469I-Discovery_LCD STM32469I Discovery LCD
+  * @{
+  */
+
+/** @defgroup STM32469I-Discovery_LCD_Private_TypesDefinitions STM32469I Discovery LCD Private TypesDefinitions
+  * @{
+  */
+static DSI_VidCfgTypeDef hdsivideo_handle;
+
+/**
+  * @}
+  */
+
+/** @defgroup STM32469I-Discovery_LCD_Private_Defines STM32469I Discovery LCD Private Defines
+  * @{
+  */
+/**
+  * @}
+  */
+
+/** @defgroup STM32469I-Discovery_LCD_Private_Macros STM32469I Discovery LCD Private Macros
+  * @{
+  */
+#define ABS(X)                 ((X) > 0 ? (X) : -(X))
+
+#define POLY_X(Z)              ((int32_t)((Points + (Z))->X))
+#define POLY_Y(Z)              ((int32_t)((Points + (Z))->Y))
+/**
+  * @}
+  */
+
+/** @defgroup STM32469I-Discovery_LCD_Exported_Variables STM32469I Discovery LCD Exported Variables
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+
+/** @defgroup STM32469I-Discovery_LCD_Private_Variables STM32469I Discovery LCD Private Variables
+  * @{
+  */
+
+DMA2D_HandleTypeDef hdma2d_eval;
+LTDC_HandleTypeDef  hltdc_eval;
+DSI_HandleTypeDef hdsi_eval;
+uint32_t lcd_x_size = OTM8009A_800X480_WIDTH;
+uint32_t lcd_y_size = OTM8009A_800X480_HEIGHT;
+
+/**
+  * @}
+  */
+
+
+/** @defgroup STM32469I-Discovery_LCD_Private_Variables STM32469I Discovery LCD Private Variables
+  * @{
+  */
+
+/**
+  * @brief  Default Active LTDC Layer in which drawing is made is LTDC Layer Background
+  */
+static uint32_t  ActiveLayer = LTDC_ACTIVE_LAYER_BACKGROUND;
+
+/**
+  * @brief  Current Drawing Layer properties variable
+  */
+static LCD_DrawPropTypeDef DrawProp[LTDC_MAX_LAYER_NUMBER];
+/**
+  * @}
+  */
+
+/** @defgroup STM32469I-Discovery_LCD_Private_FunctionPrototypes STM32469I Discovery LCD Private FunctionPrototypes
+  * @{
+  */
+static void DrawChar(uint16_t Xpos, uint16_t Ypos, const uint8_t *c);
+static void FillTriangle(uint16_t x1, uint16_t x2, uint16_t x3, uint16_t y1, uint16_t y2, uint16_t y3);
+static void LL_FillBuffer(uint32_t LayerIndex, void *pDst, uint32_t xSize, uint32_t ySize, uint32_t OffLine, uint32_t ColorIndex);
+static void LL_ConvertLineToARGB8888(void * pSrc, void *pDst, uint32_t xSize, uint32_t ColorMode);
+/**
+  * @}
+  */
+
+/** @defgroup STM32469I-Discovery_LCD_Exported_Functions STM32469I Discovery LCD Exported Functions
+  * @{
+  */
+
+/**
+  * @brief  Initializes the DSI LCD.
+  * @retval LCD state
+  */
+uint8_t BSP_LCD_Init(void)
+{
+  return (BSP_LCD_InitEx(LCD_ORIENTATION_LANDSCAPE));
+}
+
+/**
+  * @brief  Initializes the DSI LCD. 
+  * The ititialization is done as below:
+  *     - DSI PLL ititialization
+  *     - DSI ititialization
+  *     - LTDC ititialization
+  *     - OTM8009A LCD Display IC Driver ititialization
+  * @retval LCD state
+  */
+uint8_t BSP_LCD_InitEx(LCD_OrientationTypeDef orientation)
+{
+  DSI_PLLInitTypeDef dsiPllInit;
+  DSI_PHY_TimerTypeDef  PhyTimings;
+  static RCC_PeriphCLKInitTypeDef  PeriphClkInitStruct;
+  uint32_t LcdClock  = 27429; /*!< LcdClk = 27429 kHz */
+  
+  uint32_t laneByteClk_kHz = 0;
+  uint32_t                   VSA; /*!< Vertical start active time in units of lines */
+  uint32_t                   VBP; /*!< Vertical Back Porch time in units of lines */
+  uint32_t                   VFP; /*!< Vertical Front Porch time in units of lines */
+  uint32_t                   VACT; /*!< Vertical Active time in units of lines = imageSize Y in pixels to display */
+  uint32_t                   HSA; /*!< Horizontal start active time in units of lcdClk */
+  uint32_t                   HBP; /*!< Horizontal Back Porch time in units of lcdClk */
+  uint32_t                   HFP; /*!< Horizontal Front Porch time in units of lcdClk */
+  uint32_t                   HACT; /*!< Horizontal Active time in units of lcdClk = imageSize X in pixels to display */
+  
+  
+  /* Toggle Hardware Reset of the DSI LCD using
+  * its XRES signal (active low) */
+  BSP_LCD_Reset();
+  
+  /* Call first MSP Initialize only in case of first initialization
+  * This will set IP blocks LTDC, DSI and DMA2D
+  * - out of reset
+  * - clocked
+  * - NVIC IRQ related to IP blocks enabled
+  */
+  BSP_LCD_MspInit();
+  
+/*************************DSI Initialization***********************************/  
+  
+  /* Base address of DSI Host/Wrapper registers to be set before calling De-Init */
+  hdsi_eval.Instance = DSI;
+  
+  HAL_DSI_DeInit(&(hdsi_eval));
+  
+#if !defined(USE_STM32469I_DISCO_REVA)
+  dsiPllInit.PLLNDIV  = 125;
+  dsiPllInit.PLLIDF   = DSI_PLL_IN_DIV2;
+  dsiPllInit.PLLODF   = DSI_PLL_OUT_DIV1;
+#else  
+  dsiPllInit.PLLNDIV  = 100;
+  dsiPllInit.PLLIDF   = DSI_PLL_IN_DIV5;
+  dsiPllInit.PLLODF   = DSI_PLL_OUT_DIV1;
+#endif
+  laneByteClk_kHz = 62500; /* 500 MHz / 8 = 62.5 MHz = 62500 kHz */
+  
+  /* Set number of Lanes */
+  hdsi_eval.Init.NumberOfLanes = DSI_TWO_DATA_LANES;
+  
+  /* TXEscapeCkdiv = f(LaneByteClk)/15.62 = 4 */
+  hdsi_eval.Init.TXEscapeCkdiv = laneByteClk_kHz/15620; 
+  
+  HAL_DSI_Init(&(hdsi_eval), &(dsiPllInit));
+  
+  /* Timing parameters for all Video modes
+  * Set Timing parameters of LTDC depending on its chosen orientation
+  */
+  if(orientation == LCD_ORIENTATION_PORTRAIT)
+  {
+    lcd_x_size = OTM8009A_480X800_WIDTH;  /* 480 */
+    lcd_y_size = OTM8009A_480X800_HEIGHT; /* 800 */                                
+  }
+  else
+  {
+    /* lcd_orientation == LCD_ORIENTATION_LANDSCAPE */
+    lcd_x_size = OTM8009A_800X480_WIDTH;  /* 800 */
+    lcd_y_size = OTM8009A_800X480_HEIGHT; /* 480 */                                
+  }
+  
+  HACT = lcd_x_size;
+  VACT = lcd_y_size;
+  
+  /* The following values are same for portrait and landscape orientations */
+#if defined (USE_STM32469I_DISCO_REVC)
+  VSA  = NT35510_480X800_VSYNC;
+  VBP  = NT35510_480X800_VBP;
+  VFP  = NT35510_480X800_VFP;
+  HSA  = NT35510_480X800_HSYNC;
+  HBP  = NT35510_480X800_HBP;
+  HFP  = NT35510_480X800_HFP;
+#else
+  VSA  = OTM8009A_480X800_VSYNC;
+  VBP  = OTM8009A_480X800_VBP;
+  VFP  = OTM8009A_480X800_VFP;
+  HSA  = OTM8009A_480X800_HSYNC;
+  HBP  = OTM8009A_480X800_HBP;
+  HFP  = OTM8009A_480X800_HFP;
+#endif /* USE_STM32469I_DISCO_REVC */
+  
+  
+  hdsivideo_handle.VirtualChannelID = LCD_OTM8009A_ID;
+  hdsivideo_handle.ColorCoding = LCD_DSI_PIXEL_DATA_FMT_RBG888;
+  hdsivideo_handle.VSPolarity = DSI_VSYNC_ACTIVE_HIGH;
+  hdsivideo_handle.HSPolarity = DSI_HSYNC_ACTIVE_HIGH;
+  hdsivideo_handle.DEPolarity = DSI_DATA_ENABLE_ACTIVE_HIGH;  
+  hdsivideo_handle.Mode = DSI_VID_MODE_BURST; /* Mode Video burst ie : one LgP per line */
+  hdsivideo_handle.NullPacketSize = 0xFFF;
+  hdsivideo_handle.NumberOfChunks = 0;
+  hdsivideo_handle.PacketSize                = HACT; /* Value depending on display orientation choice portrait/landscape */ 
+  hdsivideo_handle.HorizontalSyncActive      = (HSA * laneByteClk_kHz) / LcdClock;
+  hdsivideo_handle.HorizontalBackPorch       = (HBP * laneByteClk_kHz) / LcdClock;
+  hdsivideo_handle.HorizontalLine            = ((HACT + HSA + HBP + HFP) * laneByteClk_kHz) / LcdClock; /* Value depending on display orientation choice portrait/landscape */
+  hdsivideo_handle.VerticalSyncActive        = VSA;
+  hdsivideo_handle.VerticalBackPorch         = VBP;
+  hdsivideo_handle.VerticalFrontPorch        = VFP;
+  hdsivideo_handle.VerticalActive            = VACT; /* Value depending on display orientation choice portrait/landscape */
+  
+  /* Enable or disable sending LP command while streaming is active in video mode */
+  hdsivideo_handle.LPCommandEnable = DSI_LP_COMMAND_ENABLE; /* Enable sending commands in mode LP (Low Power) */
+  
+  /* Largest packet size possible to transmit in LP mode in VSA, VBP, VFP regions */
+  /* Only useful when sending LP packets is allowed while streaming is active in video mode */
+  hdsivideo_handle.LPLargestPacketSize = 16;
+  
+  /* Largest packet size possible to transmit in LP mode in HFP region during VACT period */
+  /* Only useful when sending LP packets is allowed while streaming is active in video mode */
+  hdsivideo_handle.LPVACTLargestPacketSize = 0;
+  
+  
+  /* Specify for each region of the video frame, if the transmission of command in LP mode is allowed in this region */
+  /* while streaming is active in video mode                                                                         */
+  hdsivideo_handle.LPHorizontalFrontPorchEnable = DSI_LP_HFP_ENABLE;   /* Allow sending LP commands during HFP period */
+  hdsivideo_handle.LPHorizontalBackPorchEnable  = DSI_LP_HBP_ENABLE;   /* Allow sending LP commands during HBP period */
+  hdsivideo_handle.LPVerticalActiveEnable = DSI_LP_VACT_ENABLE;  /* Allow sending LP commands during VACT period */
+  hdsivideo_handle.LPVerticalFrontPorchEnable = DSI_LP_VFP_ENABLE;   /* Allow sending LP commands during VFP period */
+  hdsivideo_handle.LPVerticalBackPorchEnable = DSI_LP_VBP_ENABLE;   /* Allow sending LP commands during VBP period */
+  hdsivideo_handle.LPVerticalSyncActiveEnable = DSI_LP_VSYNC_ENABLE; /* Allow sending LP commands during VSync = VSA period */
+  
+  /* Configure DSI Video mode timings with settings set above */
+  HAL_DSI_ConfigVideoMode(&(hdsi_eval), &(hdsivideo_handle));
+
+  /* Configure DSI PHY HS2LP and LP2HS timings */
+  PhyTimings.ClockLaneHS2LPTime = 35;
+  PhyTimings.ClockLaneLP2HSTime = 35;
+  PhyTimings.DataLaneHS2LPTime = 35;
+  PhyTimings.DataLaneLP2HSTime = 35;
+  PhyTimings.DataLaneMaxReadTime = 0;
+  PhyTimings.StopWaitTime = 10;
+  HAL_DSI_ConfigPhyTimer(&hdsi_eval, &PhyTimings);
+
+/*************************End DSI Initialization*******************************/ 
+  
+  
+/************************LTDC Initialization***********************************/  
+  
+  /* Timing Configuration */    
+  hltdc_eval.Init.HorizontalSync = (HSA - 1);
+  hltdc_eval.Init.AccumulatedHBP = (HSA + HBP - 1);
+  hltdc_eval.Init.AccumulatedActiveW = (lcd_x_size + HSA + HBP - 1);
+  hltdc_eval.Init.TotalWidth = (lcd_x_size + HSA + HBP + HFP - 1);
+  
+  /* Initialize the LCD pixel width and pixel height */
+  hltdc_eval.LayerCfg->ImageWidth  = lcd_x_size;
+  hltdc_eval.LayerCfg->ImageHeight = lcd_y_size;   
+  
+  
+  /* LCD clock configuration */
+  /* PLLSAI_VCO Input = HSE_VALUE/PLL_M = 1 Mhz */
+  /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN = 384 Mhz */
+  /* PLLLCDCLK = PLLSAI_VCO Output/PLLSAIR = 384 MHz / 7 = 54.857 MHz */
+  /* LTDC clock frequency = PLLLCDCLK / LTDC_PLLSAI_DIVR_2 = 54.857 MHz / 2 = 27.429 MHz */
+  PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_LTDC;
+  PeriphClkInitStruct.PLLSAI.PLLSAIN = 384;
+  PeriphClkInitStruct.PLLSAI.PLLSAIR = 7;
+  PeriphClkInitStruct.PLLSAIDivR = RCC_PLLSAIDIVR_2;
+  HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct); 
+  
+  /* Background value */
+  hltdc_eval.Init.Backcolor.Blue = 0;
+  hltdc_eval.Init.Backcolor.Green = 0;
+  hltdc_eval.Init.Backcolor.Red = 0;
+  hltdc_eval.Init.PCPolarity = LTDC_PCPOLARITY_IPC;
+  hltdc_eval.Instance = LTDC;
+  
+  /* Get LTDC Configuration from DSI Configuration */
+  HAL_LTDCEx_StructInitFromVideoConfig(&(hltdc_eval), &(hdsivideo_handle));
+  
+  /* Initialize the LTDC */  
+  HAL_LTDC_Init(&hltdc_eval);
+
+  /* Enable the DSI host and wrapper after the LTDC initialization
+     To avoid any synchronization issue, the DSI shall be started after enabling the LTDC */
+  HAL_DSI_Start(&(hdsi_eval));
+  
+#if !defined(DATA_IN_ExtSDRAM)
+  /* Initialize the SDRAM */
+  BSP_SDRAM_Init();
+#endif /* DATA_IN_ExtSDRAM */
+  
+  /* Initialize the font */
+  BSP_LCD_SetFont(&LCD_DEFAULT_FONT);
+  
+/************************End LTDC Initialization*******************************/
+  
+#if defined(USE_STM32469I_DISCO_REVC)
+/***********************NT35510 Initialization********************************/  
+  
+  /* Initialize the NT35510 LCD Display IC Driver (TechShine LCD IC Driver)
+   * depending on configuration set in 'hdsivideo_handle'.
+   */
+  NT35510_Init(NT35510_FORMAT_RGB888, orientation);
+/***********************End NT35510 Initialization****************************/
+#else
+/***********************OTM8009A Initialization********************************/  
+  
+  /* Initialize the OTM8009A LCD Display IC Driver (KoD LCD IC Driver)
+  *  depending on configuration set in 'hdsivideo_handle'.
+  */
+  OTM8009A_Init(OTM8009A_FORMAT_RGB888, orientation);
+/***********************End OTM8009A Initialization****************************/ 
+#endif /* USE_STM32469I_DISCO_REVC */
+
+  return LCD_OK;
+}
+
+/**
+  * @brief  BSP LCD Reset
+  *         Hw reset the LCD DSI activating its XRES signal (active low for some time)
+  *         and desactivating it later.
+  *         This signal is only cabled on Discovery Rev B and beyond.
+  */
+void BSP_LCD_Reset(void)
+{
+#if !defined(USE_STM32469I_DISCO_REVA)
+  /* Disco Rev B and beyond : reset the LCD by activation of XRES (active low) connected to PH7 */
+  GPIO_InitTypeDef  gpio_init_structure;
+
+  __HAL_RCC_GPIOH_CLK_ENABLE();
+
+    /* Configure the GPIO on PH7 */
+    gpio_init_structure.Pin   = GPIO_PIN_7;
+#if defined(USE_STM32469I_DISCO_REVC)
+    /* Push Pull Mode is required for TechShine LCD (NT35510) */
+    gpio_init_structure.Mode  = GPIO_MODE_OUTPUT_PP;
+#else
+    gpio_init_structure.Mode  = GPIO_MODE_OUTPUT_OD;
+#endif
+    gpio_init_structure.Pull  = GPIO_NOPULL;
+    gpio_init_structure.Speed = GPIO_SPEED_HIGH;
+
+    HAL_GPIO_Init(GPIOH, &gpio_init_structure);
+
+    /* Activate XRES active low */
+    HAL_GPIO_WritePin(GPIOH, GPIO_PIN_7, GPIO_PIN_RESET);
+
+    HAL_Delay(20); /* wait 20 ms */
+
+    /* Desactivate XRES */
+    HAL_GPIO_WritePin(GPIOH, GPIO_PIN_7, GPIO_PIN_SET);
+    
+    /* Wait for 20ms after releasing XRES before sending commands */
+    HAL_Delay(20);    
+#else
+  /* Nothing to do in case of Disco Rev A */
+#endif /* USE_STM32469I_DISCO_REVA == 0 */
+}
+
+/**
+  * @brief  Gets the LCD X size.
+  * @retval Used LCD X size
+  */
+uint32_t BSP_LCD_GetXSize(void)
+{
+  return (lcd_x_size);
+}
+
+/**
+  * @brief  Gets the LCD Y size.
+  * @retval Used LCD Y size
+  */
+uint32_t BSP_LCD_GetYSize(void)
+{
+  return (lcd_y_size);
+}
+
+/**
+  * @brief  Set the LCD X size.
+  * @param  imageWidthPixels : uint32_t image width in pixels unit
+  */
+void BSP_LCD_SetXSize(uint32_t imageWidthPixels)
+{
+  hltdc_eval.LayerCfg[ActiveLayer].ImageWidth = imageWidthPixels;
+}
+
+/**
+  * @brief  Set the LCD Y size.
+  * @param  imageHeightPixels : uint32_t image height in lines unit
+  */
+void BSP_LCD_SetYSize(uint32_t imageHeightPixels)
+{
+  hltdc_eval.LayerCfg[ActiveLayer].ImageHeight = imageHeightPixels;
+}
+
+
+/**
+  * @brief  Initializes the LCD layers.
+  * @param  LayerIndex: Layer foreground or background
+  * @param  FB_Address: Layer frame buffer
+  */
+void BSP_LCD_LayerDefaultInit(uint16_t LayerIndex, uint32_t FB_Address)
+{
+    LCD_LayerCfgTypeDef  Layercfg;
+
+  /* Layer Init */
+  Layercfg.WindowX0 = 0;
+  Layercfg.WindowX1 = BSP_LCD_GetXSize();
+  Layercfg.WindowY0 = 0;
+  Layercfg.WindowY1 = BSP_LCD_GetYSize(); 
+  Layercfg.PixelFormat = LTDC_PIXEL_FORMAT_ARGB8888;
+  Layercfg.FBStartAdress = FB_Address;
+  Layercfg.Alpha = 255;
+  Layercfg.Alpha0 = 0;
+  Layercfg.Backcolor.Blue = 0;
+  Layercfg.Backcolor.Green = 0;
+  Layercfg.Backcolor.Red = 0;
+  Layercfg.BlendingFactor1 = LTDC_BLENDING_FACTOR1_PAxCA;
+  Layercfg.BlendingFactor2 = LTDC_BLENDING_FACTOR2_PAxCA;
+  Layercfg.ImageWidth = BSP_LCD_GetXSize();
+  Layercfg.ImageHeight = BSP_LCD_GetYSize();
+  
+  HAL_LTDC_ConfigLayer(&hltdc_eval, &Layercfg, LayerIndex); 
+  
+  DrawProp[LayerIndex].BackColor = LCD_COLOR_WHITE;
+  DrawProp[LayerIndex].pFont     = &Font24;
+  DrawProp[LayerIndex].TextColor = LCD_COLOR_BLACK;
+}
+
+
+/**
+  * @brief  Selects the LCD Layer.
+  * @param  LayerIndex: Layer foreground or background
+  */
+void BSP_LCD_SelectLayer(uint32_t LayerIndex)
+{
+  ActiveLayer = LayerIndex;
+}
+
+/**
+  * @brief  Sets an LCD Layer visible
+  * @param  LayerIndex: Visible Layer
+  * @param  State: New state of the specified layer
+  *          This parameter can be one of the following values:
+  *            @arg  ENABLE
+  *            @arg  DISABLE
+  */
+void BSP_LCD_SetLayerVisible(uint32_t LayerIndex, FunctionalState State)
+{
+  if(State == ENABLE)
+  {
+    __HAL_LTDC_LAYER_ENABLE(&(hltdc_eval), LayerIndex);
+  }
+  else
+  {
+    __HAL_LTDC_LAYER_DISABLE(&(hltdc_eval), LayerIndex);
+  }
+  __HAL_LTDC_RELOAD_IMMEDIATE_CONFIG(&(hltdc_eval));
+  
+}
+
+/**
+  * @brief  Configures the transparency.
+  * @param  LayerIndex: Layer foreground or background.
+  * @param  Transparency: Transparency
+  *           This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF
+  */
+void BSP_LCD_SetTransparency(uint32_t LayerIndex, uint8_t Transparency)
+{
+  
+  HAL_LTDC_SetAlpha(&(hltdc_eval), Transparency, LayerIndex);
+  
+}
+
+/**
+  * @brief  Sets an LCD layer frame buffer address.
+  * @param  LayerIndex: Layer foreground or background
+  * @param  Address: New LCD frame buffer value
+  */
+void BSP_LCD_SetLayerAddress(uint32_t LayerIndex, uint32_t Address)
+{
+  
+  HAL_LTDC_SetAddress(&(hltdc_eval), Address, LayerIndex);
+  
+}
+
+/**
+  * @brief  Sets display window.
+  * @param  LayerIndex: Layer index
+  * @param  Xpos: LCD X position
+  * @param  Ypos: LCD Y position
+  * @param  Width: LCD window width
+  * @param  Height: LCD window height
+  */
+void BSP_LCD_SetLayerWindow(uint16_t LayerIndex, uint16_t Xpos, uint16_t Ypos, uint16_t Width, uint16_t Height)
+{
+  /* Reconfigure the layer size */
+  HAL_LTDC_SetWindowSize(&(hltdc_eval), Width, Height, LayerIndex);
+  
+  /* Reconfigure the layer position */
+  HAL_LTDC_SetWindowPosition(&(hltdc_eval), Xpos, Ypos, LayerIndex);
+  
+}
+
+/**
+  * @brief  Configures and sets the color keying.
+  * @param  LayerIndex: Layer foreground or background
+  * @param  RGBValue: Color reference
+  */
+void BSP_LCD_SetColorKeying(uint32_t LayerIndex, uint32_t RGBValue)
+{
+  /* Configure and Enable the color Keying for LCD Layer */
+  HAL_LTDC_ConfigColorKeying(&(hltdc_eval), RGBValue, LayerIndex);
+  HAL_LTDC_EnableColorKeying(&(hltdc_eval), LayerIndex);
+}
+
+/**
+  * @brief  Disables the color keying.
+  * @param  LayerIndex: Layer foreground or background
+  */
+void BSP_LCD_ResetColorKeying(uint32_t LayerIndex)
+{
+  /* Disable the color Keying for LCD Layer */
+  HAL_LTDC_DisableColorKeying(&(hltdc_eval), LayerIndex);
+}
+
+/**
+  * @brief  Sets the LCD text color.
+  * @param  Color: Text color code ARGB(8-8-8-8)
+  */
+void BSP_LCD_SetTextColor(uint32_t Color)
+{
+  DrawProp[ActiveLayer].TextColor = Color;
+}
+
+/**
+  * @brief  Gets the LCD text color.
+  * @retval Used text color.
+  */
+uint32_t BSP_LCD_GetTextColor(void)
+{
+  return DrawProp[ActiveLayer].TextColor;
+}
+
+/**
+  * @brief  Sets the LCD background color.
+  * @param  Color: Layer background color code ARGB(8-8-8-8)
+  */
+void BSP_LCD_SetBackColor(uint32_t Color)
+{
+  DrawProp[ActiveLayer].BackColor = Color;
+}
+
+/**
+  * @brief  Gets the LCD background color.
+  * @retval Used background color
+  */
+uint32_t BSP_LCD_GetBackColor(void)
+{
+  return DrawProp[ActiveLayer].BackColor;
+}
+
+/**
+  * @brief  Sets the LCD text font.
+  * @param  fonts: Layer font to be used
+  */
+void BSP_LCD_SetFont(sFONT *fonts)
+{
+  DrawProp[ActiveLayer].pFont = fonts;
+}
+
+/**
+  * @brief  Gets the LCD text font.
+  * @retval Used layer font
+  */
+sFONT *BSP_LCD_GetFont(void)
+{
+  return DrawProp[ActiveLayer].pFont;
+}
+
+/**
+  * @brief  Reads an LCD pixel.
+  * @param  Xpos: X position
+  * @param  Ypos: Y position
+  * @retval RGB pixel color
+  */
+uint32_t BSP_LCD_ReadPixel(uint16_t Xpos, uint16_t Ypos)
+{
+  uint32_t ret = 0;
+
+  if(hltdc_eval.LayerCfg[ActiveLayer].PixelFormat == LTDC_PIXEL_FORMAT_ARGB8888)
+  {
+    /* Read data value from SDRAM memory */
+    ret = *(__IO uint32_t*) (hltdc_eval.LayerCfg[ActiveLayer].FBStartAdress + (4*(Ypos*BSP_LCD_GetXSize() + Xpos)));
+  }
+  else if(hltdc_eval.LayerCfg[ActiveLayer].PixelFormat == LTDC_PIXEL_FORMAT_RGB888)
+  {
+    /* Read data value from SDRAM memory */
+    ret = (*(__IO uint32_t*) (hltdc_eval.LayerCfg[ActiveLayer].FBStartAdress + (4*(Ypos*BSP_LCD_GetXSize() + Xpos))) & 0x00FFFFFF);
+  }
+  else if((hltdc_eval.LayerCfg[ActiveLayer].PixelFormat == LTDC_PIXEL_FORMAT_RGB565) || \
+          (hltdc_eval.LayerCfg[ActiveLayer].PixelFormat == LTDC_PIXEL_FORMAT_ARGB4444) || \
+          (hltdc_eval.LayerCfg[ActiveLayer].PixelFormat == LTDC_PIXEL_FORMAT_AL88))
+  {
+    /* Read data value from SDRAM memory */
+    ret = *(__IO uint16_t*) (hltdc_eval.LayerCfg[ActiveLayer].FBStartAdress + (2*(Ypos*BSP_LCD_GetXSize() + Xpos)));
+  }
+  else
+  {
+    /* Read data value from SDRAM memory */
+    ret = *(__IO uint8_t*) (hltdc_eval.LayerCfg[ActiveLayer].FBStartAdress + (2*(Ypos*BSP_LCD_GetXSize() + Xpos)));
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  Clears the whole currently active layer of LTDC.
+  * @param  Color: Color of the background
+  */
+void BSP_LCD_Clear(uint32_t Color)
+{
+  /* Clear the LCD */
+  LL_FillBuffer(ActiveLayer, (uint32_t *)(hltdc_eval.LayerCfg[ActiveLayer].FBStartAdress), BSP_LCD_GetXSize(), BSP_LCD_GetYSize(), 0, Color);
+}
+
+/**
+  * @brief  Clears the selected line in currently active layer.
+  * @param  Line: Line to be cleared
+  */
+void BSP_LCD_ClearStringLine(uint32_t Line)
+{
+  uint32_t color_backup = DrawProp[ActiveLayer].TextColor;
+  DrawProp[ActiveLayer].TextColor = DrawProp[ActiveLayer].BackColor;
+
+  /* Draw rectangle with background color */
+  BSP_LCD_FillRect(0, (Line * DrawProp[ActiveLayer].pFont->Height), BSP_LCD_GetXSize(), DrawProp[ActiveLayer].pFont->Height);
+
+  DrawProp[ActiveLayer].TextColor = color_backup;
+  BSP_LCD_SetTextColor(DrawProp[ActiveLayer].TextColor);
+}
+
+/**
+  * @brief  Displays one character in currently active layer.
+  * @param  Xpos: Start column address
+  * @param  Ypos: Line where to display the character shape.
+  * @param  Ascii: Character ascii code
+  *           This parameter must be a number between Min_Data = 0x20 and Max_Data = 0x7E
+  */
+void BSP_LCD_DisplayChar(uint16_t Xpos, uint16_t Ypos, uint8_t Ascii)
+{
+  DrawChar(Xpos, Ypos, &DrawProp[ActiveLayer].pFont->table[(Ascii-' ') *\
+    DrawProp[ActiveLayer].pFont->Height * ((DrawProp[ActiveLayer].pFont->Width + 7) / 8)]);
+}
+
+/**
+  * @brief  Displays characters in currently active layer.
+  * @param  Xpos: X position (in pixel)
+  * @param  Ypos: Y position (in pixel)
+  * @param  Text: Pointer to string to display on LCD
+  * @param  Mode: Display mode
+  *          This parameter can be one of the following values:
+  *            @arg  CENTER_MODE
+  *            @arg  RIGHT_MODE
+  *            @arg  LEFT_MODE
+  */
+void BSP_LCD_DisplayStringAt(uint16_t Xpos, uint16_t Ypos, uint8_t *Text, Text_AlignModeTypdef Mode)
+{
+  uint16_t refcolumn = 1, i = 0;
+  uint32_t size = 0, xsize = 0;
+  uint8_t  *ptr = Text;
+
+  /* Get the text size */
+  while (*ptr++) size ++ ;
+
+  /* Characters number per line */
+  xsize = (BSP_LCD_GetXSize()/DrawProp[ActiveLayer].pFont->Width);
+
+  switch (Mode)
+  {
+  case CENTER_MODE:
+    {
+      refcolumn = Xpos + ((xsize - size)* DrawProp[ActiveLayer].pFont->Width) / 2;
+      break;
+    }
+  case LEFT_MODE:
+    {
+      refcolumn = Xpos;
+      break;
+    }
+  case RIGHT_MODE:
+    {
+      refcolumn = - Xpos + ((xsize - size)*DrawProp[ActiveLayer].pFont->Width);
+      break;
+    }
+  default:
+    {
+      refcolumn = Xpos;
+      break;
+    }
+  }
+
+  /* Check that the Start column is located in the screen */
+  if ((refcolumn < 1) || (refcolumn >= 0x8000))
+  {
+    refcolumn = 1;
+  }
+
+  /* Send the string character by character on LCD */
+  while ((*Text != 0) & (((BSP_LCD_GetXSize() - (i*DrawProp[ActiveLayer].pFont->Width)) & 0xFFFF) >= DrawProp[ActiveLayer].pFont->Width))
+  {
+    /* Display one character on LCD */
+    BSP_LCD_DisplayChar(refcolumn, Ypos, *Text);
+    /* Decrement the column position by 16 */
+    refcolumn += DrawProp[ActiveLayer].pFont->Width;
+
+    /* Point on the next character */
+    Text++;
+    i++;
+  }
+
+}
+
+/**
+  * @brief  Displays a maximum of 60 characters on the LCD.
+  * @param  Line: Line where to display the character shape
+  * @param  ptr: Pointer to string to display on LCD
+  */
+void BSP_LCD_DisplayStringAtLine(uint16_t Line, uint8_t *ptr)
+{
+  BSP_LCD_DisplayStringAt(0, LINE(Line), ptr, LEFT_MODE);
+}
+
+/**
+  * @brief  Draws an horizontal line in currently active layer.
+  * @param  Xpos: X position
+  * @param  Ypos: Y position
+  * @param  Length: Line length
+  */
+void BSP_LCD_DrawHLine(uint16_t Xpos, uint16_t Ypos, uint16_t Length)
+{
+  uint32_t  Xaddress = 0;
+
+  /* Get the line address */
+  Xaddress = (hltdc_eval.LayerCfg[ActiveLayer].FBStartAdress) + 4*(BSP_LCD_GetXSize()*Ypos + Xpos);
+
+  /* Write line */
+  LL_FillBuffer(ActiveLayer, (uint32_t *)Xaddress, Length, 1, 0, DrawProp[ActiveLayer].TextColor);
+}
+
+/**
+  * @brief  Draws a vertical line in currently active layer.
+  * @param  Xpos: X position
+  * @param  Ypos: Y position
+  * @param  Length: Line length
+  */
+void BSP_LCD_DrawVLine(uint16_t Xpos, uint16_t Ypos, uint16_t Length)
+{
+  uint32_t  Xaddress = 0;
+
+  /* Get the line address */
+  Xaddress = (hltdc_eval.LayerCfg[ActiveLayer].FBStartAdress) + 4*(BSP_LCD_GetXSize()*Ypos + Xpos);
+
+  /* Write line */
+  LL_FillBuffer(ActiveLayer, (uint32_t *)Xaddress, 1, Length, (BSP_LCD_GetXSize() - 1), DrawProp[ActiveLayer].TextColor);
+}
+
+/**
+  * @brief  Draws an uni-line (between two points) in currently active layer.
+  * @param  x1: Point 1 X position
+  * @param  y1: Point 1 Y position
+  * @param  x2: Point 2 X position
+  * @param  y2: Point 2 Y position
+  */
+void BSP_LCD_DrawLine(uint16_t x1, uint16_t y1, uint16_t x2, uint16_t y2)
+{
+  int16_t deltax = 0, deltay = 0, x = 0, y = 0, xinc1 = 0, xinc2 = 0,
+  yinc1 = 0, yinc2 = 0, den = 0, num = 0, numadd = 0, numpixels = 0,
+  curpixel = 0;
+
+  deltax = ABS(x2 - x1);        /* The difference between the x's */
+  deltay = ABS(y2 - y1);        /* The difference between the y's */
+  x = x1;                       /* Start x off at the first pixel */
+  y = y1;                       /* Start y off at the first pixel */
+
+  if (x2 >= x1)                 /* The x-values are increasing */
+  {
+    xinc1 = 1;
+    xinc2 = 1;
+  }
+  else                          /* The x-values are decreasing */
+  {
+    xinc1 = -1;
+    xinc2 = -1;
+  }
+
+  if (y2 >= y1)                 /* The y-values are increasing */
+  {
+    yinc1 = 1;
+    yinc2 = 1;
+  }
+  else                          /* The y-values are decreasing */
+  {
+    yinc1 = -1;
+    yinc2 = -1;
+  }
+
+  if (deltax >= deltay)         /* There is at least one x-value for every y-value */
+  {
+    xinc1 = 0;                  /* Don't change the x when numerator >= denominator */
+    yinc2 = 0;                  /* Don't change the y for every iteration */
+    den = deltax;
+    num = deltax / 2;
+    numadd = deltay;
+    numpixels = deltax;         /* There are more x-values than y-values */
+  }
+  else                          /* There is at least one y-value for every x-value */
+  {
+    xinc2 = 0;                  /* Don't change the x for every iteration */
+    yinc1 = 0;                  /* Don't change the y when numerator >= denominator */
+    den = deltay;
+    num = deltay / 2;
+    numadd = deltax;
+    numpixels = deltay;         /* There are more y-values than x-values */
+  }
+
+  for (curpixel = 0; curpixel <= numpixels; curpixel++)
+  {
+    BSP_LCD_DrawPixel(x, y, DrawProp[ActiveLayer].TextColor);   /* Draw the current pixel */
+    num += numadd;                            /* Increase the numerator by the top of the fraction */
+    if (num >= den)                           /* Check if numerator >= denominator */
+    {
+      num -= den;                             /* Calculate the new numerator value */
+      x += xinc1;                             /* Change the x as appropriate */
+      y += yinc1;                             /* Change the y as appropriate */
+    }
+    x += xinc2;                               /* Change the x as appropriate */
+    y += yinc2;                               /* Change the y as appropriate */
+  }
+}
+
+/**
+  * @brief  Draws a rectangle in currently active layer.
+  * @param  Xpos: X position
+  * @param  Ypos: Y position
+  * @param  Width: Rectangle width
+  * @param  Height: Rectangle height
+  */
+void BSP_LCD_DrawRect(uint16_t Xpos, uint16_t Ypos, uint16_t Width, uint16_t Height)
+{
+  /* Draw horizontal lines */
+  BSP_LCD_DrawHLine(Xpos, Ypos, Width);
+  BSP_LCD_DrawHLine(Xpos, (Ypos+ Height), Width);
+
+  /* Draw vertical lines */
+  BSP_LCD_DrawVLine(Xpos, Ypos, Height);
+  BSP_LCD_DrawVLine((Xpos + Width), Ypos, Height);
+}
+
+/**
+  * @brief  Draws a circle in currently active layer.
+  * @param  Xpos: X position
+  * @param  Ypos: Y position
+  * @param  Radius: Circle radius
+  */
+void BSP_LCD_DrawCircle(uint16_t Xpos, uint16_t Ypos, uint16_t Radius)
+{
+  int32_t   D;    /* Decision Variable */
+  uint32_t  CurX; /* Current X Value */
+  uint32_t  CurY; /* Current Y Value */
+
+  D = 3 - (Radius << 1);
+  CurX = 0;
+  CurY = Radius;
+
+  while (CurX <= CurY)
+  {
+    BSP_LCD_DrawPixel((Xpos + CurX), (Ypos - CurY), DrawProp[ActiveLayer].TextColor);
+
+    BSP_LCD_DrawPixel((Xpos - CurX), (Ypos - CurY), DrawProp[ActiveLayer].TextColor);
+
+    BSP_LCD_DrawPixel((Xpos + CurY), (Ypos - CurX), DrawProp[ActiveLayer].TextColor);
+
+    BSP_LCD_DrawPixel((Xpos - CurY), (Ypos - CurX), DrawProp[ActiveLayer].TextColor);
+
+    BSP_LCD_DrawPixel((Xpos + CurX), (Ypos + CurY), DrawProp[ActiveLayer].TextColor);
+
+    BSP_LCD_DrawPixel((Xpos - CurX), (Ypos + CurY), DrawProp[ActiveLayer].TextColor);
+
+    BSP_LCD_DrawPixel((Xpos + CurY), (Ypos + CurX), DrawProp[ActiveLayer].TextColor);
+
+    BSP_LCD_DrawPixel((Xpos - CurY), (Ypos + CurX), DrawProp[ActiveLayer].TextColor);
+
+    if (D < 0)
+    {
+      D += (CurX << 2) + 6;
+    }
+    else
+    {
+      D += ((CurX - CurY) << 2) + 10;
+      CurY--;
+    }
+    CurX++;
+  }
+}
+
+/**
+  * @brief  Draws an poly-line (between many points) in currently active layer.
+  * @param  Points: Pointer to the points array
+  * @param  PointCount: Number of points
+  */
+void BSP_LCD_DrawPolygon(pPoint Points, uint16_t PointCount)
+{
+  int16_t X = 0, Y = 0;
+
+  if(PointCount < 2)
+  {
+    return;
+  }
+
+  BSP_LCD_DrawLine(Points->X, Points->Y, (Points+PointCount-1)->X, (Points+PointCount-1)->Y);
+
+  while(--PointCount)
+  {
+    X = Points->X;
+    Y = Points->Y;
+    Points++;
+    BSP_LCD_DrawLine(X, Y, Points->X, Points->Y);
+  }
+}
+
+/**
+  * @brief  Draws an ellipse on LCD in currently active layer.
+  * @param  Xpos: X position
+  * @param  Ypos: Y position
+  * @param  XRadius: Ellipse X radius
+  * @param  YRadius: Ellipse Y radius
+  */
+void BSP_LCD_DrawEllipse(int Xpos, int Ypos, int XRadius, int YRadius)
+{
+  int x = 0, y = -YRadius, err = 2-2*XRadius, e2;
+  float K = 0, rad1 = 0, rad2 = 0;
+
+  rad1 = XRadius;
+  rad2 = YRadius;
+
+  K = (float)(rad2/rad1);
+
+  do {
+    BSP_LCD_DrawPixel((Xpos-(uint16_t)(x/K)), (Ypos+y), DrawProp[ActiveLayer].TextColor);
+    BSP_LCD_DrawPixel((Xpos+(uint16_t)(x/K)), (Ypos+y), DrawProp[ActiveLayer].TextColor);
+    BSP_LCD_DrawPixel((Xpos+(uint16_t)(x/K)), (Ypos-y), DrawProp[ActiveLayer].TextColor);
+    BSP_LCD_DrawPixel((Xpos-(uint16_t)(x/K)), (Ypos-y), DrawProp[ActiveLayer].TextColor);
+
+    e2 = err;
+    if (e2 <= x) {
+      err += ++x*2+1;
+      if (-y == x && e2 <= y) e2 = 0;
+    }
+    if (e2 > y) err += ++y*2+1;
+  }
+  while (y <= 0);
+}
+
+/**
+  * @brief  Draws a bitmap picture loaded in the internal Flash (32 bpp) in currently active layer.
+  * @param  Xpos: Bmp X position in the LCD
+  * @param  Ypos: Bmp Y position in the LCD
+  * @param  pbmp: Pointer to Bmp picture address in the internal Flash
+  */
+void BSP_LCD_DrawBitmap(uint32_t Xpos, uint32_t Ypos, uint8_t *pbmp)
+{
+  uint32_t index = 0, width = 0, height = 0, bit_pixel = 0;
+  uint32_t Address;
+  uint32_t InputColorMode = 0;
+
+  /* Get bitmap data address offset */
+  index = pbmp[10] + (pbmp[11] << 8) + (pbmp[12] << 16)  + (pbmp[13] << 24);
+
+  /* Read bitmap width */
+  width = pbmp[18] + (pbmp[19] << 8) + (pbmp[20] << 16)  + (pbmp[21] << 24);
+
+  /* Read bitmap height */
+  height = pbmp[22] + (pbmp[23] << 8) + (pbmp[24] << 16)  + (pbmp[25] << 24);
+
+  /* Read bit/pixel */
+  bit_pixel = pbmp[28] + (pbmp[29] << 8);
+
+  /* Set the address */
+  Address = hltdc_eval.LayerCfg[ActiveLayer].FBStartAdress + (((BSP_LCD_GetXSize()*Ypos) + Xpos)*(4));
+
+  /* Get the layer pixel format */
+  if ((bit_pixel/8) == 4)
+  {
+    InputColorMode = CM_ARGB8888;
+  }
+  else if ((bit_pixel/8) == 2)
+  {
+    InputColorMode = CM_RGB565;
+  }
+  else
+  {
+    InputColorMode = CM_RGB888;
+  }
+
+  /* Bypass the bitmap header */
+  pbmp += (index + (width * (height - 1) * (bit_pixel/8)));
+
+  /* Convert picture to ARGB8888 pixel format */
+  for(index=0; index < height; index++)
+  {
+    /* Pixel format conversion */
+    LL_ConvertLineToARGB8888((uint32_t *)pbmp, (uint32_t *)Address, width, InputColorMode);
+
+    /* Increment the source and destination buffers */
+    Address+=  (BSP_LCD_GetXSize()*4);
+    pbmp -= width*(bit_pixel/8);
+  }
+}
+
+/**
+  * @brief  Draws a full rectangle in currently active layer.
+  * @param  Xpos: X position
+  * @param  Ypos: Y position
+  * @param  Width: Rectangle width
+  * @param  Height: Rectangle height
+  */
+void BSP_LCD_FillRect(uint16_t Xpos, uint16_t Ypos, uint16_t Width, uint16_t Height)
+{
+  uint32_t  Xaddress = 0;
+
+  /* Set the text color */
+  BSP_LCD_SetTextColor(DrawProp[ActiveLayer].TextColor);
+
+  /* Get the rectangle start address */
+  Xaddress = (hltdc_eval.LayerCfg[ActiveLayer].FBStartAdress) + 4*(BSP_LCD_GetXSize()*Ypos + Xpos);
+
+  /* Fill the rectangle */
+  LL_FillBuffer(ActiveLayer, (uint32_t *)Xaddress, Width, Height, (BSP_LCD_GetXSize() - Width), DrawProp[ActiveLayer].TextColor);
+}
+
+/**
+  * @brief  Draws a full circle in currently active layer.
+  * @param  Xpos: X position
+  * @param  Ypos: Y position
+  * @param  Radius: Circle radius
+  */
+void BSP_LCD_FillCircle(uint16_t Xpos, uint16_t Ypos, uint16_t Radius)
+{
+  int32_t  D;     /* Decision Variable */
+  uint32_t  CurX; /* Current X Value */
+  uint32_t  CurY; /* Current Y Value */
+
+  D = 3 - (Radius << 1);
+
+  CurX = 0;
+  CurY = Radius;
+
+  BSP_LCD_SetTextColor(DrawProp[ActiveLayer].TextColor);
+
+  while (CurX <= CurY)
+  {
+    if(CurY > 0)
+    {
+      BSP_LCD_DrawHLine(Xpos - CurY, Ypos + CurX, 2*CurY);
+      BSP_LCD_DrawHLine(Xpos - CurY, Ypos - CurX, 2*CurY);
+    }
+
+    if(CurX > 0)
+    {
+      BSP_LCD_DrawHLine(Xpos - CurX, Ypos - CurY, 2*CurX);
+      BSP_LCD_DrawHLine(Xpos - CurX, Ypos + CurY, 2*CurX);
+    }
+    if (D < 0)
+    {
+      D += (CurX << 2) + 6;
+    }
+    else
+    {
+      D += ((CurX - CurY) << 2) + 10;
+      CurY--;
+    }
+    CurX++;
+  }
+
+  BSP_LCD_SetTextColor(DrawProp[ActiveLayer].TextColor);
+  BSP_LCD_DrawCircle(Xpos, Ypos, Radius);
+}
+
+/**
+  * @brief  Draws a full poly-line (between many points) in currently active layer.
+  * @param  Points: Pointer to the points array
+  * @param  PointCount: Number of points
+  */
+void BSP_LCD_FillPolygon(pPoint Points, uint16_t PointCount)
+{
+  int16_t X = 0, Y = 0, X2 = 0, Y2 = 0, X_center = 0, Y_center = 0, X_first = 0, Y_first = 0, pixelX = 0, pixelY = 0, counter = 0;
+  uint16_t  IMAGE_LEFT = 0, IMAGE_RIGHT = 0, IMAGE_TOP = 0, IMAGE_BOTTOM = 0;
+
+  IMAGE_LEFT = IMAGE_RIGHT = Points->X;
+  IMAGE_TOP= IMAGE_BOTTOM = Points->Y;
+
+  for(counter = 1; counter < PointCount; counter++)
+  {
+    pixelX = POLY_X(counter);
+    if(pixelX < IMAGE_LEFT)
+    {
+      IMAGE_LEFT = pixelX;
+    }
+    if(pixelX > IMAGE_RIGHT)
+    {
+      IMAGE_RIGHT = pixelX;
+    }
+
+    pixelY = POLY_Y(counter);
+    if(pixelY < IMAGE_TOP)
+    {
+      IMAGE_TOP = pixelY;
+    }
+    if(pixelY > IMAGE_BOTTOM)
+    {
+      IMAGE_BOTTOM = pixelY;
+    }
+  }
+
+  if(PointCount < 2)
+  {
+    return;
+  }
+
+  X_center = (IMAGE_LEFT + IMAGE_RIGHT)/2;
+  Y_center = (IMAGE_BOTTOM + IMAGE_TOP)/2;
+
+  X_first = Points->X;
+  Y_first = Points->Y;
+
+  while(--PointCount)
+  {
+    X = Points->X;
+    Y = Points->Y;
+    Points++;
+    X2 = Points->X;
+    Y2 = Points->Y;
+
+    FillTriangle(X, X2, X_center, Y, Y2, Y_center);
+    FillTriangle(X, X_center, X2, Y, Y_center, Y2);
+    FillTriangle(X_center, X2, X, Y_center, Y2, Y);
+  }
+
+  FillTriangle(X_first, X2, X_center, Y_first, Y2, Y_center);
+  FillTriangle(X_first, X_center, X2, Y_first, Y_center, Y2);
+  FillTriangle(X_center, X2, X_first, Y_center, Y2, Y_first);
+}
+
+/**
+  * @brief  Draws a full ellipse in currently active layer.
+  * @param  Xpos: X position
+  * @param  Ypos: Y position
+  * @param  XRadius: Ellipse X radius
+  * @param  YRadius: Ellipse Y radius
+  */
+void BSP_LCD_FillEllipse(int Xpos, int Ypos, int XRadius, int YRadius)
+{
+  int x = 0, y = -YRadius, err = 2-2*XRadius, e2;
+  float K = 0, rad1 = 0, rad2 = 0;
+
+  rad1 = XRadius;
+  rad2 = YRadius;
+
+  K = (float)(rad2/rad1);
+
+  do
+  {
+    BSP_LCD_DrawHLine((Xpos-(uint16_t)(x/K)), (Ypos+y), (2*(uint16_t)(x/K) + 1));
+    BSP_LCD_DrawHLine((Xpos-(uint16_t)(x/K)), (Ypos-y), (2*(uint16_t)(x/K) + 1));
+
+    e2 = err;
+    if (e2 <= x)
+    {
+      err += ++x*2+1;
+      if (-y == x && e2 <= y) e2 = 0;
+    }
+    if (e2 > y) err += ++y*2+1;
+  }
+  while (y <= 0);
+}
+
+/**
+  * @brief  Switch back on the display if was switched off by previous call of BSP_LCD_DisplayOff().
+  *         Exit DSI ULPM mode if was allowed and configured in Dsi Configuration.
+  */
+void BSP_LCD_DisplayOn(void)
+{
+  /* Send Display on DCS command to display */
+  HAL_DSI_ShortWrite(&(hdsi_eval),
+                     hdsivideo_handle.VirtualChannelID,
+                     DSI_DCS_SHORT_PKT_WRITE_P1,
+                     OTM8009A_CMD_DISPON,
+                     0x00);
+  
+}
+
+/**
+  * @brief  Switch Off the display.
+  *         Enter DSI ULPM mode if was allowed and configured in Dsi Configuration.
+  */
+void BSP_LCD_DisplayOff(void)
+{
+  /* Send Display off DCS Command to display */
+  HAL_DSI_ShortWrite(&(hdsi_eval),
+                     hdsivideo_handle.VirtualChannelID,
+                     DSI_DCS_SHORT_PKT_WRITE_P1,
+                     OTM8009A_CMD_DISPOFF,
+                     0x00);
+  
+}
+
+/**
+  * @brief  DCS or Generic short/long write command
+  * @param  NbrParams: Number of parameters. It indicates the write command mode:
+  *                 If inferior to 2, a long write command is performed else short.
+  * @param  pParams: Pointer to parameter values table.
+  * @retval HAL status
+  */
+void DSI_IO_WriteCmd(uint32_t NbrParams, uint8_t *pParams)
+{
+  if(NbrParams <= 1)
+  {
+   HAL_DSI_ShortWrite(&hdsi_eval, LCD_OTM8009A_ID, DSI_DCS_SHORT_PKT_WRITE_P1, pParams[0], pParams[1]); 
+  }
+  else
+  {
+   HAL_DSI_LongWrite(&hdsi_eval,  LCD_OTM8009A_ID, DSI_DCS_LONG_PKT_WRITE, NbrParams, pParams[NbrParams], pParams); 
+  }
+}
+
+/*******************************************************************************
+                       LTDC, DMA2D and DSI BSP Routines
+*******************************************************************************/
+/**
+  * @brief  Handles DMA2D interrupt request.
+  * @note : Can be surcharged by application code implementation of the function.
+  */
+__weak void BSP_LCD_DMA2D_IRQHandler(void)
+{
+  HAL_DMA2D_IRQHandler(&hdma2d_eval);
+}
+
+/**
+  * @brief  Handles DSI interrupt request.
+  * @note : Can be surcharged by application code implementation of the function.
+  */
+__weak void BSP_LCD_DSI_IRQHandler(void)
+{
+  HAL_DSI_IRQHandler(&(hdsi_eval));
+}
+
+
+/**
+  * @brief  Handles LTDC interrupt request.
+  * @note : Can be surcharged by application code implementation of the function.
+  */
+__weak void BSP_LCD_LTDC_IRQHandler(void)
+{
+  HAL_LTDC_IRQHandler(&(hltdc_eval));
+}
+
+/**
+  * @brief  De-Initializes the BSP LCD Msp
+  * Application can surcharge if needed this function implementation.
+  */
+__weak void BSP_LCD_MspDeInit(void)
+{
+  /** @brief Disable IRQ of LTDC IP */
+  HAL_NVIC_DisableIRQ(LTDC_IRQn);
+
+  /** @brief Disable IRQ of DMA2D IP */
+  HAL_NVIC_DisableIRQ(DMA2D_IRQn);
+
+  /** @brief Disable IRQ of DSI IP */
+  HAL_NVIC_DisableIRQ(DSI_IRQn);
+
+  /** @brief Force and let in reset state LTDC, DMA2D and DSI Host + Wrapper IPs */
+  __HAL_RCC_LTDC_FORCE_RESET();
+  __HAL_RCC_DMA2D_FORCE_RESET();
+  __HAL_RCC_DSI_FORCE_RESET();
+
+  /** @brief Disable the LTDC, DMA2D and DSI Host and Wrapper clocks */
+  __HAL_RCC_LTDC_CLK_DISABLE();
+  __HAL_RCC_DMA2D_CLK_DISABLE();
+  __HAL_RCC_DSI_CLK_DISABLE();
+}
+
+/**
+  * @brief  Initialize the BSP LCD Msp.
+  * Application can surcharge if needed this function implementation
+  */
+__weak void BSP_LCD_MspInit(void)
+{
+  /** @brief Enable the LTDC clock */
+  __HAL_RCC_LTDC_CLK_ENABLE();
+
+  /** @brief Toggle Sw reset of LTDC IP */
+  __HAL_RCC_LTDC_FORCE_RESET();
+  __HAL_RCC_LTDC_RELEASE_RESET();
+
+  /** @brief Enable the DMA2D clock */
+  __HAL_RCC_DMA2D_CLK_ENABLE();
+
+  /** @brief Toggle Sw reset of DMA2D IP */
+  __HAL_RCC_DMA2D_FORCE_RESET();
+  __HAL_RCC_DMA2D_RELEASE_RESET();
+
+  /** @brief Enable DSI Host and wrapper clocks */
+  __HAL_RCC_DSI_CLK_ENABLE();
+
+  /** @brief Soft Reset the DSI Host and wrapper */
+  __HAL_RCC_DSI_FORCE_RESET();
+  __HAL_RCC_DSI_RELEASE_RESET();
+
+  /** @brief NVIC configuration for LTDC interrupt that is now enabled */
+  HAL_NVIC_SetPriority(LTDC_IRQn, 3, 0);
+  HAL_NVIC_EnableIRQ(LTDC_IRQn);
+
+  /** @brief NVIC configuration for DMA2D interrupt that is now enabled */
+  HAL_NVIC_SetPriority(DMA2D_IRQn, 3, 0);
+  HAL_NVIC_EnableIRQ(DMA2D_IRQn);
+
+  /** @brief NVIC configuration for DSI interrupt that is now enabled */
+  HAL_NVIC_SetPriority(DSI_IRQn, 3, 0);
+  HAL_NVIC_EnableIRQ(DSI_IRQn);
+}
+
+/**
+  * @brief  This function handles LTDC Error interrupt Handler.
+  * @note : Can be surcharged by application code implementation of the function.
+  */
+
+__weak void BSP_LCD_LTDC_ER_IRQHandler(void)
+{
+  HAL_LTDC_IRQHandler(&(hltdc_eval));
+}
+
+
+/**
+  * @brief  Draws a pixel on LCD.
+  * @param  Xpos: X position
+  * @param  Ypos: Y position
+  * @param  RGB_Code: Pixel color in ARGB mode (8-8-8-8)
+  */
+void BSP_LCD_DrawPixel(uint16_t Xpos, uint16_t Ypos, uint32_t RGB_Code)
+{
+  /* Write data value to all SDRAM memory */
+  *(__IO uint32_t*) (hltdc_eval.LayerCfg[ActiveLayer].FBStartAdress + (4*(Ypos*BSP_LCD_GetXSize() + Xpos))) = RGB_Code;
+}
+
+
+/**
+  * @brief  Draws a character on LCD.
+  * @param  Xpos: Line where to display the character shape
+  * @param  Ypos: Start column address
+  * @param  c: Pointer to the character data
+  */
+static void DrawChar(uint16_t Xpos, uint16_t Ypos, const uint8_t *c)
+{
+  uint32_t i = 0, j = 0;
+  uint16_t height, width;
+  uint8_t  offset;
+  uint8_t  *pchar;
+  uint32_t line;
+
+  height = DrawProp[ActiveLayer].pFont->Height;
+  width  = DrawProp[ActiveLayer].pFont->Width;
+
+  offset =  8 *((width + 7)/8) -  width ;
+
+  for(i = 0; i < height; i++)
+  {
+    pchar = ((uint8_t *)c + (width + 7)/8 * i);
+
+    switch(((width + 7)/8))
+    {
+
+    case 1:
+      line =  pchar[0];
+      break;
+
+    case 2:
+      line =  (pchar[0]<< 8) | pchar[1];
+      break;
+
+    case 3:
+    default:
+      line =  (pchar[0]<< 16) | (pchar[1]<< 8) | pchar[2];
+      break;
+    }
+
+    for (j = 0; j < width; j++)
+    {
+      if(line & (1 << (width- j + offset- 1)))
+      {
+        BSP_LCD_DrawPixel((Xpos + j), Ypos, DrawProp[ActiveLayer].TextColor);
+      }
+      else
+      {
+        BSP_LCD_DrawPixel((Xpos + j), Ypos, DrawProp[ActiveLayer].BackColor);
+      }
+    }
+    Ypos++;
+  }
+}
+
+/**
+  * @brief  Fills a triangle (between 3 points).
+  * @param  x1: Point 1 X position
+  * @param  y1: Point 1 Y position
+  * @param  x2: Point 2 X position
+  * @param  y2: Point 2 Y position
+  * @param  x3: Point 3 X position
+  * @param  y3: Point 3 Y position
+  */
+static void FillTriangle(uint16_t x1, uint16_t x2, uint16_t x3, uint16_t y1, uint16_t y2, uint16_t y3)
+{
+  int16_t deltax = 0, deltay = 0, x = 0, y = 0, xinc1 = 0, xinc2 = 0,
+  yinc1 = 0, yinc2 = 0, den = 0, num = 0, numadd = 0, numpixels = 0,
+  curpixel = 0;
+
+  deltax = ABS(x2 - x1);        /* The difference between the x's */
+  deltay = ABS(y2 - y1);        /* The difference between the y's */
+  x = x1;                       /* Start x off at the first pixel */
+  y = y1;                       /* Start y off at the first pixel */
+
+  if (x2 >= x1)                 /* The x-values are increasing */
+  {
+    xinc1 = 1;
+    xinc2 = 1;
+  }
+  else                          /* The x-values are decreasing */
+  {
+    xinc1 = -1;
+    xinc2 = -1;
+  }
+
+  if (y2 >= y1)                 /* The y-values are increasing */
+  {
+    yinc1 = 1;
+    yinc2 = 1;
+  }
+  else                          /* The y-values are decreasing */
+  {
+    yinc1 = -1;
+    yinc2 = -1;
+  }
+
+  if (deltax >= deltay)         /* There is at least one x-value for every y-value */
+  {
+    xinc1 = 0;                  /* Don't change the x when numerator >= denominator */
+    yinc2 = 0;                  /* Don't change the y for every iteration */
+    den = deltax;
+    num = deltax / 2;
+    numadd = deltay;
+    numpixels = deltax;         /* There are more x-values than y-values */
+  }
+  else                          /* There is at least one y-value for every x-value */
+  {
+    xinc2 = 0;                  /* Don't change the x for every iteration */
+    yinc1 = 0;                  /* Don't change the y when numerator >= denominator */
+    den = deltay;
+    num = deltay / 2;
+    numadd = deltax;
+    numpixels = deltay;         /* There are more y-values than x-values */
+  }
+
+  for (curpixel = 0; curpixel <= numpixels; curpixel++)
+  {
+    BSP_LCD_DrawLine(x, y, x3, y3);
+
+    num += numadd;              /* Increase the numerator by the top of the fraction */
+    if (num >= den)             /* Check if numerator >= denominator */
+    {
+      num -= den;               /* Calculate the new numerator value */
+      x += xinc1;               /* Change the x as appropriate */
+      y += yinc1;               /* Change the y as appropriate */
+    }
+    x += xinc2;                 /* Change the x as appropriate */
+    y += yinc2;                 /* Change the y as appropriate */
+  }
+}
+
+/**
+  * @brief  Fills a buffer.
+  * @param  LayerIndex: Layer index
+  * @param  pDst: Pointer to destination buffer
+  * @param  xSize: Buffer width
+  * @param  ySize: Buffer height
+  * @param  OffLine: Offset
+  * @param  ColorIndex: Color index
+  */
+static void LL_FillBuffer(uint32_t LayerIndex, void *pDst, uint32_t xSize, uint32_t ySize, uint32_t OffLine, uint32_t ColorIndex)
+{
+  /* Register to memory mode with ARGB8888 as color Mode */
+  hdma2d_eval.Init.Mode         = DMA2D_R2M;
+  hdma2d_eval.Init.ColorMode    = DMA2D_ARGB8888;
+  hdma2d_eval.Init.OutputOffset = OffLine;
+
+  hdma2d_eval.Instance = DMA2D;
+
+  /* DMA2D Initialization */
+  if(HAL_DMA2D_Init(&hdma2d_eval) == HAL_OK)
+  {
+    if(HAL_DMA2D_ConfigLayer(&hdma2d_eval, LayerIndex) == HAL_OK)
+    {
+      if (HAL_DMA2D_Start(&hdma2d_eval, ColorIndex, (uint32_t)pDst, xSize, ySize) == HAL_OK)
+      {
+        /* Polling For DMA transfer */
+        HAL_DMA2D_PollForTransfer(&hdma2d_eval, 10);
+      }
+    }
+  }
+}
+
+/**
+  * @brief  Converts a line to an ARGB8888 pixel format.
+  * @param  pSrc: Pointer to source buffer
+  * @param  pDst: Output color
+  * @param  xSize: Buffer width
+  * @param  ColorMode: Input color mode
+  */
+static void LL_ConvertLineToARGB8888(void *pSrc, void *pDst, uint32_t xSize, uint32_t ColorMode)
+{
+  /* Configure the DMA2D Mode, Color Mode and output offset */
+  hdma2d_eval.Init.Mode         = DMA2D_M2M_PFC;
+  hdma2d_eval.Init.ColorMode    = DMA2D_ARGB8888;
+  hdma2d_eval.Init.OutputOffset = 0;
+
+  /* Foreground Configuration */
+  hdma2d_eval.LayerCfg[1].AlphaMode = DMA2D_NO_MODIF_ALPHA;
+  hdma2d_eval.LayerCfg[1].InputAlpha = 0xFF;
+  hdma2d_eval.LayerCfg[1].InputColorMode = ColorMode;
+  hdma2d_eval.LayerCfg[1].InputOffset = 0;
+
+  hdma2d_eval.Instance = DMA2D;
+
+  /* DMA2D Initialization */
+  if(HAL_DMA2D_Init(&hdma2d_eval) == HAL_OK)
+  {
+    if(HAL_DMA2D_ConfigLayer(&hdma2d_eval, 1) == HAL_OK)
+    {
+      if (HAL_DMA2D_Start(&hdma2d_eval, (uint32_t)pSrc, (uint32_t)pDst, xSize, 1) == HAL_OK)
+      {
+        /* Polling For DMA transfer */
+        HAL_DMA2D_PollForTransfer(&hdma2d_eval, 10);
+      }
+    }
+  }
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
diff --git a/Drivers/BSP/STM32469I-Discovery/stm32469i_discovery_lcd.h b/Drivers/BSP/STM32469I-Discovery/stm32469i_discovery_lcd.h
new file mode 100644
index 0000000..e105cf8
--- /dev/null
+++ b/Drivers/BSP/STM32469I-Discovery/stm32469i_discovery_lcd.h
@@ -0,0 +1,389 @@
+/**
+  ******************************************************************************
+  * @file    stm32469i_discovery_lcd.h
+  * @author  MCD Application Team
+  * @brief   This file contains the common defines and functions prototypes for
+  *          the stm32469i_discovery_lcd.c driver.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32469I_DISCOVERY_LCD_H
+#define __STM32469I_DISCOVERY_LCD_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+/* Include LCD component Driver */
+
+/* Include OTM8009A LCD Driver IC driver code */
+#include "../Components/otm8009a/otm8009a.h"
+/* Include NT35510 LCD Driver IC driver code */
+#include "../Components/nt35510/nt35510.h"
+
+/* Include SDRAM Driver */
+#include "stm32469i_discovery_sdram.h"
+#include "stm32469i_discovery.h"
+#include "../../../Utilities/Fonts/fonts.h"
+
+#include <string.h> /* use of memset() */
+
+/** @addtogroup BSP
+  * @{
+  */
+
+/** @addtogroup STM32469I_Discovery
+  * @{
+  */
+
+/** @addtogroup STM32469I-Discovery_LCD 
+  * @{
+  */
+
+/** @defgroup STM32469I-Discovery_LCD_Exported_Constants STM32469I Discovery LCD Exported Constants
+  * @{
+  */
+
+#define LCD_LayerCfgTypeDef    LTDC_LayerCfgTypeDef
+/** 
+  * @brief  LCD FB_StartAddress  
+  */
+#define LCD_FB_START_ADDRESS       ((uint32_t)0xC0000000)
+   
+/** @brief Maximum number of LTDC layers
+ */
+#define LTDC_MAX_LAYER_NUMBER             ((uint32_t) 2)
+
+/** @brief LTDC Background layer index
+ */
+#define LTDC_ACTIVE_LAYER_BACKGROUND      ((uint32_t) 0)
+
+/** @brief LTDC Foreground layer index
+ */
+#define LTDC_ACTIVE_LAYER_FOREGROUND      ((uint32_t) 1)
+
+/** @brief Number of LTDC layers
+ */
+#define LTDC_NB_OF_LAYERS                 ((uint32_t) 2)
+
+/** @brief LTDC Default used layer index
+ */
+#define LTDC_DEFAULT_ACTIVE_LAYER         LTDC_ACTIVE_LAYER_FOREGROUND
+
+/** 
+  * @brief  LCD status structure definition  
+  */     
+#define   LCD_OK         0x00
+#define   LCD_ERROR      0x01
+#define   LCD_TIMEOUT    0x02
+
+/** 
+  * @brief  LCD Display OTM8009A ID  
+  */ 
+#define LCD_OTM8009A_ID  ((uint32_t) 0)
+   
+/**
+  * @brief  LCD color definitions values
+  * in ARGB8888 format.
+  */
+
+/** @brief Blue value in ARGB8888 format
+ */
+#define LCD_COLOR_BLUE          ((uint32_t) 0xFF0000FF)
+
+/** @brief Green value in ARGB8888 format
+ */
+#define LCD_COLOR_GREEN         ((uint32_t) 0xFF00FF00)
+
+/** @brief Red value in ARGB8888 format
+ */
+#define LCD_COLOR_RED           ((uint32_t) 0xFFFF0000)
+
+/** @brief Cyan value in ARGB8888 format
+ */
+#define LCD_COLOR_CYAN          ((uint32_t) 0xFF00FFFF)
+
+/** @brief Magenta value in ARGB8888 format
+ */
+#define LCD_COLOR_MAGENTA       ((uint32_t) 0xFFFF00FF)
+
+/** @brief Yellow value in ARGB8888 format
+ */
+#define LCD_COLOR_YELLOW        ((uint32_t) 0xFFFFFF00)
+
+/** @brief Light Blue value in ARGB8888 format
+ */
+#define LCD_COLOR_LIGHTBLUE     ((uint32_t) 0xFF8080FF)
+
+/** @brief Light Green value in ARGB8888 format
+ */
+#define LCD_COLOR_LIGHTGREEN    ((uint32_t) 0xFF80FF80)
+
+/** @brief Light Red value in ARGB8888 format
+ */
+#define LCD_COLOR_LIGHTRED      ((uint32_t) 0xFFFF8080)
+
+/** @brief Light Cyan value in ARGB8888 format
+ */
+#define LCD_COLOR_LIGHTCYAN     ((uint32_t) 0xFF80FFFF)
+
+/** @brief Light Magenta value in ARGB8888 format
+ */
+#define LCD_COLOR_LIGHTMAGENTA  ((uint32_t) 0xFFFF80FF)
+
+/** @brief Light Yellow value in ARGB8888 format
+ */
+#define LCD_COLOR_LIGHTYELLOW   ((uint32_t) 0xFFFFFF80)
+
+/** @brief Dark Blue value in ARGB8888 format
+ */
+#define LCD_COLOR_DARKBLUE      ((uint32_t) 0xFF000080)
+
+/** @brief Light Dark Green value in ARGB8888 format
+ */
+#define LCD_COLOR_DARKGREEN     ((uint32_t) 0xFF008000)
+
+/** @brief Light Dark Red value in ARGB8888 format
+ */
+#define LCD_COLOR_DARKRED       ((uint32_t) 0xFF800000)
+
+/** @brief Dark Cyan value in ARGB8888 format
+ */
+#define LCD_COLOR_DARKCYAN      ((uint32_t) 0xFF008080)
+
+/** @brief Dark Magenta value in ARGB8888 format
+ */
+#define LCD_COLOR_DARKMAGENTA   ((uint32_t) 0xFF800080)
+
+/** @brief Dark Yellow value in ARGB8888 format
+ */
+#define LCD_COLOR_DARKYELLOW    ((uint32_t) 0xFF808000)
+
+/** @brief White value in ARGB8888 format
+ */
+#define LCD_COLOR_WHITE         ((uint32_t) 0xFFFFFFFF)
+
+/** @brief Light Gray value in ARGB8888 format
+ */
+#define LCD_COLOR_LIGHTGRAY     ((uint32_t) 0xFFD3D3D3)
+
+/** @brief Gray value in ARGB8888 format
+ */
+#define LCD_COLOR_GRAY          ((uint32_t) 0xFF808080)
+
+/** @brief Dark Gray value in ARGB8888 format
+ */
+#define LCD_COLOR_DARKGRAY      ((uint32_t) 0xFF404040)
+
+/** @brief Black value in ARGB8888 format
+ */
+#define LCD_COLOR_BLACK         ((uint32_t) 0xFF000000)
+
+/** @brief Brown value in ARGB8888 format
+ */
+#define LCD_COLOR_BROWN         ((uint32_t) 0xFFA52A2A)
+
+/** @brief Orange value in ARGB8888 format
+ */
+#define LCD_COLOR_ORANGE        ((uint32_t) 0xFFFFA500)
+
+/** @brief Transparent value in ARGB8888 format
+ */
+#define LCD_COLOR_TRANSPARENT   ((uint32_t) 0xFF000000)
+
+/**
+  * @brief LCD default font
+  */
+#define LCD_DEFAULT_FONT        Font24
+
+/**
+ *  @brief  Possible values of
+ *  pixel data format (ie color coding) transmitted on DSI Data lane in DSI packets
+ */
+
+#define   LCD_DSI_PIXEL_DATA_FMT_RBG888  DSI_RGB888 /*!< DSI packet pixel format chosen is RGB888 : 24 bpp */
+#define   LCD_DSI_PIXEL_DATA_FMT_RBG565  DSI_RGB565 /*!< DSI packet pixel format chosen is RGB565 : 16 bpp */
+
+/**
+  * @}
+  */
+   
+/** @defgroup STM32469I-Discovery_LCD_Exported_Types STM32469I Discovery LCD Exported Types
+  * @{
+  */
+
+/**
+* @brief  LCD Drawing main properties
+*/
+typedef struct
+{
+  uint32_t TextColor; /*!< Specifies the color of text */
+  uint32_t BackColor; /*!< Specifies the background color below the text */
+  sFONT    *pFont;    /*!< Specifies the font used for the text */
+
+} LCD_DrawPropTypeDef;
+
+/**
+  * @brief  LCD Drawing point (pixel) geometric definition
+  */
+typedef struct
+{
+  int16_t X; /*!< geometric X position of drawing */
+  int16_t Y; /*!< geometric Y position of drawing */
+
+} Point;
+
+/**
+  * @brief  Pointer on LCD Drawing point (pixel) geometric definition
+  */
+typedef Point * pPoint;
+
+/**
+  * @brief  LCD drawing Line alignment mode definitions
+  */
+typedef enum
+{
+  CENTER_MODE             = 0x01,    /*!< Center mode */
+  RIGHT_MODE              = 0x02,    /*!< Right mode  */
+  LEFT_MODE               = 0x03     /*!< Left mode   */
+
+} Text_AlignModeTypdef;
+
+
+/**
+ *  @brief LCD_OrientationTypeDef
+ *  Possible values of Display Orientation
+ */
+typedef enum
+{
+  LCD_ORIENTATION_PORTRAIT  = 0x00, /*!< Portrait orientation choice of LCD screen  */
+  LCD_ORIENTATION_LANDSCAPE = 0x01, /*!< Landscape orientation choice of LCD screen */
+  LCD_ORIENTATION_INVALID   = 0x02  /*!< Invalid orientation choice of LCD screen   */
+} LCD_OrientationTypeDef;
+
+/**
+  * @}
+  */
+
+/** @defgroup STM32469I-Discovery_LCD_Exported_Macro STM32469I Discovery LCD Exported Macro
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup STM32469I-Discovery_LCD_Exported_Functions STM32469I Discovery LCD Exported Functions
+  * @{
+  */
+void     BSP_LCD_DMA2D_IRQHandler(void);
+void     BSP_LCD_DSI_IRQHandler(void);
+void     BSP_LCD_LTDC_IRQHandler(void);
+void     BSP_LCD_LTDC_ER_IRQHandler(void);
+
+uint8_t  BSP_LCD_Init(void);
+uint8_t  BSP_LCD_InitEx(LCD_OrientationTypeDef orientation);
+
+void     BSP_LCD_MspDeInit(void);
+void     BSP_LCD_MspInit(void);
+void     BSP_LCD_Reset(void);
+
+uint32_t BSP_LCD_GetXSize(void);
+uint32_t BSP_LCD_GetYSize(void);
+void     BSP_LCD_SetXSize(uint32_t imageWidthPixels);
+void     BSP_LCD_SetYSize(uint32_t imageHeightPixels);
+
+void     BSP_LCD_LayerDefaultInit(uint16_t LayerIndex, uint32_t FB_Address);
+void     BSP_LCD_SetTransparency(uint32_t LayerIndex, uint8_t Transparency);
+void     BSP_LCD_SetLayerAddress(uint32_t LayerIndex, uint32_t Address);
+void     BSP_LCD_SetColorKeying(uint32_t LayerIndex, uint32_t RGBValue);
+void     BSP_LCD_ResetColorKeying(uint32_t LayerIndex);
+void     BSP_LCD_SetLayerWindow(uint16_t LayerIndex, uint16_t Xpos, uint16_t Ypos, uint16_t Width, uint16_t Height);
+
+void     BSP_LCD_SelectLayer(uint32_t LayerIndex);
+void     BSP_LCD_SetLayerVisible(uint32_t LayerIndex, FunctionalState State);
+
+void     BSP_LCD_SetTextColor(uint32_t Color);
+uint32_t BSP_LCD_GetTextColor(void);
+void     BSP_LCD_SetBackColor(uint32_t Color);
+uint32_t BSP_LCD_GetBackColor(void);
+void     BSP_LCD_SetFont(sFONT *fonts);
+sFONT    *BSP_LCD_GetFont(void);
+
+uint32_t BSP_LCD_ReadPixel(uint16_t Xpos, uint16_t Ypos);
+void     BSP_LCD_DrawPixel(uint16_t Xpos, uint16_t Ypos, uint32_t pixel);
+void     BSP_LCD_Clear(uint32_t Color);
+void     BSP_LCD_ClearStringLine(uint32_t Line);
+void     BSP_LCD_DisplayStringAtLine(uint16_t Line, uint8_t *ptr);
+void     BSP_LCD_DisplayStringAt(uint16_t Xpos, uint16_t Ypos, uint8_t *Text, Text_AlignModeTypdef Mode);
+void     BSP_LCD_DisplayChar(uint16_t Xpos, uint16_t Ypos, uint8_t Ascii);
+
+void     BSP_LCD_DrawHLine(uint16_t Xpos, uint16_t Ypos, uint16_t Length);
+void     BSP_LCD_DrawVLine(uint16_t Xpos, uint16_t Ypos, uint16_t Length);
+void     BSP_LCD_DrawLine(uint16_t x1, uint16_t y1, uint16_t x2, uint16_t y2);
+void     BSP_LCD_DrawRect(uint16_t Xpos, uint16_t Ypos, uint16_t Width, uint16_t Height);
+void     BSP_LCD_DrawCircle(uint16_t Xpos, uint16_t Ypos, uint16_t Radius);
+void     BSP_LCD_DrawPolygon(pPoint Points, uint16_t PointCount);
+void     BSP_LCD_DrawEllipse(int Xpos, int Ypos, int XRadius, int YRadius);
+void     BSP_LCD_DrawBitmap(uint32_t Xpos, uint32_t Ypos, uint8_t *pbmp);
+
+void     BSP_LCD_FillRect(uint16_t Xpos, uint16_t Ypos, uint16_t Width, uint16_t Height);
+void     BSP_LCD_FillCircle(uint16_t Xpos, uint16_t Ypos, uint16_t Radius);
+void     BSP_LCD_FillPolygon(pPoint Points, uint16_t PointCount);
+void     BSP_LCD_FillEllipse(int Xpos, int Ypos, int XRadius, int YRadius);
+
+void     BSP_LCD_DisplayOff(void);
+void     BSP_LCD_DisplayOn(void);
+
+/**
+  * @}
+  */
+
+/** @defgroup STM32469I-EVAL_LCD_Exported_Variables STM32469I EVAL LCD Exported Variables
+  * @{
+  */
+
+/* @brief DMA2D handle variable */
+extern DMA2D_HandleTypeDef hdma2d_eval;
+
+/**
+  * @}
+  */
+
+/** @defgroup STM32469I-Discovery_LCD_Exported_Variables STM32469I Discovery LCD Exported Variables
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32469I_DISCOVERY_LCD_H */
diff --git a/Drivers/BSP/STM32469I-Discovery/stm32469i_discovery_qspi.c b/Drivers/BSP/STM32469I-Discovery/stm32469i_discovery_qspi.c
new file mode 100644
index 0000000..72e69aa
--- /dev/null
+++ b/Drivers/BSP/STM32469I-Discovery/stm32469i_discovery_qspi.c
@@ -0,0 +1,755 @@
+/**
+  ******************************************************************************
+  * @file    stm32469i_discovery_qspi.c
+  * @author  MCD Application Team
+  * @brief   This file includes a standard driver for the N25Q128A QSPI
+  *          memory mounted on STM32469I-Discovery board.
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  @verbatim
+  ==============================================================================
+                     ##### How to use this driver #####
+  ==============================================================================
+  [..]
+   (#) This driver is used to drive the N25Q128A QSPI external
+       memory mounted on STM32469I-Discovery board.
+
+   (#) This driver need a specific component driver N25Q128A to be included with.
+
+   (#) Initialization steps:
+       (++) Initialize the QPSI external memory using the BSP_QSPI_Init() function. This
+            function includes the MSP layer hardware resources initialization and the
+            QSPI interface with the external memory.
+
+   (#) QSPI memory operations
+       (++) QSPI memory can be accessed with read/write operations once it is
+            initialized.
+            Read/write operation can be performed with AHB access using the functions
+            BSP_QSPI_Read()/BSP_QSPI_Write().
+       (++) The function BSP_QSPI_GetInfo() returns the configuration of the QSPI memory.
+            (see the QSPI memory data sheet)
+       (++) Perform erase block operation using the function BSP_QSPI_Erase_Block() and by
+            specifying the block address. You can perform an erase operation of the whole
+            chip by calling the function BSP_QSPI_Erase_Chip().
+       (++) The function BSP_QSPI_GetStatus() returns the current status of the QSPI memory.
+            (see the QSPI memory data sheet)
+  @endverbatim
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32469i_discovery_qspi.h"
+
+/** @addtogroup BSP
+  * @{
+  */
+
+/** @addtogroup STM32469I_Discovery
+  * @{
+  */
+
+/** @defgroup STM32469I_Discovery_QSPI STM32469I Discovery QSPI
+  * @{
+  */
+
+
+/* Private variables ---------------------------------------------------------*/
+
+
+/** @defgroup STM32469I_Discovery_QSPI_Private_Variables STM32469I Discovery QSPI Private Variables
+  * @{
+  */
+QSPI_HandleTypeDef QSPIHandle;
+
+/**
+  * @}
+  */
+
+
+
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup STM32469I_Discovery_QSPI_Private_Functions STM32469I Discovery QSPI Private Functions
+  * @{
+  */
+static uint8_t QSPI_ResetMemory          (QSPI_HandleTypeDef *hqspi);
+static uint8_t QSPI_DummyCyclesCfg       (QSPI_HandleTypeDef *hqspi);
+static uint8_t QSPI_WriteEnable          (QSPI_HandleTypeDef *hqspi);
+static uint8_t QSPI_AutoPollingMemReady  (QSPI_HandleTypeDef *hqspi, uint32_t Timeout);
+
+
+/**
+  * @}
+  */
+
+/** @defgroup STM32469I_Discovery_QSPI_Exported_Functions STM32469I Discovery QSPI Exported Functions
+  * @{
+  */
+
+/**
+  * @brief  Initializes the QSPI interface.
+  * @retval QSPI memory status
+  */
+uint8_t BSP_QSPI_Init(void)
+{
+  QSPIHandle.Instance = QUADSPI;
+
+  /* Call the DeInit function to reset the driver */
+  if (HAL_QSPI_DeInit(&QSPIHandle) != HAL_OK)
+  {
+    return QSPI_ERROR;
+  }
+
+  /* System level initialization */
+  BSP_QSPI_MspInit(&QSPIHandle, NULL);
+
+  /* QSPI initialization */
+  QSPIHandle.Init.ClockPrescaler     = 1; /* QSPI Freq= 180 MHz / (1+1) = 90 MHz */
+  QSPIHandle.Init.FifoThreshold      = 1;
+  QSPIHandle.Init.SampleShifting     = QSPI_SAMPLE_SHIFTING_HALFCYCLE;
+  QSPIHandle.Init.FlashSize          = POSITION_VAL(N25Q128A_FLASH_SIZE) - 1;
+  QSPIHandle.Init.ChipSelectHighTime = QSPI_CS_HIGH_TIME_5_CYCLE;
+  QSPIHandle.Init.ClockMode          = QSPI_CLOCK_MODE_0;
+  QSPIHandle.Init.FlashID            = QSPI_FLASH_ID_1;
+  QSPIHandle.Init.DualFlash          = QSPI_DUALFLASH_DISABLE;
+
+  if (HAL_QSPI_Init(&QSPIHandle) != HAL_OK)
+  {
+    return QSPI_ERROR;
+  }
+
+  /* QSPI memory reset */
+  if (QSPI_ResetMemory(&QSPIHandle) != QSPI_OK)
+  {
+    return QSPI_NOT_SUPPORTED;
+  }
+
+
+  /* Configuration of the dummy cucles on QSPI memory side */
+  if (QSPI_DummyCyclesCfg(&QSPIHandle) != QSPI_OK)
+  {
+    return QSPI_NOT_SUPPORTED;
+  }
+
+  return QSPI_OK;
+}
+
+/**
+  * @brief  De-Initializes the QSPI interface.
+  * @retval QSPI memory status
+  */
+uint8_t BSP_QSPI_DeInit(void)
+{
+  QSPIHandle.Instance = QUADSPI;
+
+  /* Call the DeInit function to reset the driver */
+  if (HAL_QSPI_DeInit(&QSPIHandle) != HAL_OK)
+  {
+    return QSPI_ERROR;
+  }
+
+  /* System level De-initialization */
+  BSP_QSPI_MspDeInit(&QSPIHandle, NULL);
+
+  return QSPI_OK;
+}
+
+/**
+  * @brief  Reads an amount of data from the QSPI memory.
+  * @param  pData: Pointer to data to be read
+  * @param  ReadAddr: Read start address
+  * @param  Size: Size of data to read
+  * @retval QSPI memory status
+  */
+uint8_t BSP_QSPI_Read(uint8_t* pData, uint32_t ReadAddr, uint32_t Size)
+{
+  QSPI_CommandTypeDef s_command;
+
+  /* Initialize the read command */
+  s_command.InstructionMode   = QSPI_INSTRUCTION_1_LINE;
+  s_command.Instruction       = QUAD_INOUT_FAST_READ_CMD;
+  s_command.AddressMode       = QSPI_ADDRESS_4_LINES;
+  s_command.AddressSize       = QSPI_ADDRESS_24_BITS;
+  s_command.Address           = ReadAddr;
+  s_command.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE;
+  s_command.DataMode          = QSPI_DATA_4_LINES;
+  s_command.DummyCycles       = N25Q128A_DUMMY_CYCLES_READ_QUAD;
+  s_command.NbData            = Size;
+  s_command.DdrMode           = QSPI_DDR_MODE_DISABLE;
+  s_command.DdrHoldHalfCycle  = QSPI_DDR_HHC_ANALOG_DELAY;
+  s_command.SIOOMode          = QSPI_SIOO_INST_EVERY_CMD;
+
+  /* Configure the command */
+  if (HAL_QSPI_Command(&QSPIHandle, &s_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
+  {
+    return QSPI_ERROR;
+  }
+
+  /* Set S# timing for Read command: Min 20ns for N25Q128A memory */
+  MODIFY_REG(QSPIHandle.Instance->DCR, QUADSPI_DCR_CSHT, QSPI_CS_HIGH_TIME_2_CYCLE);
+  
+  /* Reception of the data */
+  if (HAL_QSPI_Receive(&QSPIHandle, pData, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
+  {
+    return QSPI_ERROR;
+  }
+
+  /* Restore S# timing for nonRead commands */
+  MODIFY_REG(QSPIHandle.Instance->DCR, QUADSPI_DCR_CSHT, QSPI_CS_HIGH_TIME_5_CYCLE);
+  
+  return QSPI_OK;
+}
+
+/**
+  * @brief  Writes an amount of data to the QSPI memory.
+  * @param  pData: Pointer to data to be written
+  * @param  WriteAddr: Write start address
+  * @param  Size: Size of data to write
+  * @retval QSPI memory status
+  */
+uint8_t BSP_QSPI_Write(uint8_t* pData, uint32_t WriteAddr, uint32_t Size)
+{
+  QSPI_CommandTypeDef s_command;
+  uint32_t end_addr, current_size, current_addr;
+
+  /* Calculation of the size between the write address and the end of the page */
+  current_size = N25Q128A_PAGE_SIZE - (WriteAddr % N25Q128A_PAGE_SIZE);
+  
+  /* Check if the size of the data is less than the remaining place in the page */
+  if (current_size > Size)
+  {
+    current_size = Size;
+  }
+
+  /* Initialize the address variables */
+  current_addr = WriteAddr;
+  end_addr = WriteAddr + Size;
+
+  /* Initialize the program command */
+  s_command.InstructionMode   = QSPI_INSTRUCTION_1_LINE;
+  s_command.Instruction       = EXT_QUAD_IN_FAST_PROG_CMD;
+  s_command.AddressMode       = QSPI_ADDRESS_4_LINES;
+  s_command.AddressSize       = QSPI_ADDRESS_24_BITS;
+  s_command.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE;
+  s_command.DataMode          = QSPI_DATA_4_LINES;
+  s_command.DummyCycles       = 0;
+  s_command.DdrMode           = QSPI_DDR_MODE_DISABLE;
+  s_command.DdrHoldHalfCycle  = QSPI_DDR_HHC_ANALOG_DELAY;
+  s_command.SIOOMode          = QSPI_SIOO_INST_EVERY_CMD;
+
+  /* Perform the write page by page */
+  do
+  {
+    s_command.Address = current_addr;
+    s_command.NbData  = current_size;
+
+    /* Enable write operations */
+    if (QSPI_WriteEnable(&QSPIHandle) != QSPI_OK)
+    {
+      return QSPI_ERROR;
+    }
+
+    /* Configure the command */
+    if (HAL_QSPI_Command(&QSPIHandle, &s_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
+    {
+      return QSPI_ERROR;
+    }
+
+    /* Transmission of the data */
+    if (HAL_QSPI_Transmit(&QSPIHandle, pData, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
+    {
+      return QSPI_ERROR;
+    }
+
+    /* Configure automatic polling mode to wait for end of program */
+    if (QSPI_AutoPollingMemReady(&QSPIHandle, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != QSPI_OK)
+    {
+      return QSPI_ERROR;
+    }
+
+    /* Update the address and size variables for next page programming */
+    current_addr += current_size;
+    pData += current_size;
+    current_size = ((current_addr + N25Q128A_PAGE_SIZE) > end_addr) ? (end_addr - current_addr) : N25Q128A_PAGE_SIZE;
+  } while (current_addr < end_addr);
+
+  return QSPI_OK;
+}
+
+/**
+  * @brief  Erases the specified block of the QSPI memory.
+  * @param  BlockAddress: Block address to erase
+  * @retval QSPI memory status
+  */
+uint8_t BSP_QSPI_Erase_Block(uint32_t BlockAddress)
+{
+  QSPI_CommandTypeDef s_command;
+
+  /* Initialize the erase command */
+  s_command.InstructionMode   = QSPI_INSTRUCTION_1_LINE;
+  s_command.Instruction       = SUBSECTOR_ERASE_CMD;
+  s_command.AddressMode       = QSPI_ADDRESS_1_LINE;
+  s_command.AddressSize       = QSPI_ADDRESS_24_BITS;
+  s_command.Address           = BlockAddress;
+  s_command.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE;
+  s_command.DataMode          = QSPI_DATA_NONE;
+  s_command.DummyCycles       = 0;
+  s_command.DdrMode           = QSPI_DDR_MODE_DISABLE;
+  s_command.DdrHoldHalfCycle  = QSPI_DDR_HHC_ANALOG_DELAY;
+  s_command.SIOOMode          = QSPI_SIOO_INST_EVERY_CMD;
+
+  /* Enable write operations */
+  if (QSPI_WriteEnable(&QSPIHandle) != QSPI_OK)
+  {
+    return QSPI_ERROR;
+  }
+
+  /* Send the command */
+  if (HAL_QSPI_Command(&QSPIHandle, &s_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
+  {
+    return QSPI_ERROR;
+  }
+  
+  /* Configure automatic polling mode to wait for end of erase */  
+  if (QSPI_AutoPollingMemReady(&QSPIHandle, N25Q128A_SUBSECTOR_ERASE_MAX_TIME) != QSPI_OK)
+  {
+    return QSPI_ERROR;
+  }
+
+  return QSPI_OK;
+}
+
+/**
+  * @brief  Erases the entire QSPI memory.
+  * @retval QSPI memory status
+  */
+uint8_t BSP_QSPI_Erase_Chip(void)
+{
+  QSPI_CommandTypeDef s_command;
+
+  /* Initialize the erase command */
+  s_command.InstructionMode   = QSPI_INSTRUCTION_1_LINE;
+  s_command.Instruction       = BULK_ERASE_CMD;
+  s_command.AddressMode       = QSPI_ADDRESS_NONE;
+  s_command.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE;
+  s_command.DataMode          = QSPI_DATA_NONE;
+  s_command.DummyCycles       = 0;
+  s_command.DdrMode           = QSPI_DDR_MODE_DISABLE;
+  s_command.DdrHoldHalfCycle  = QSPI_DDR_HHC_ANALOG_DELAY;
+  s_command.SIOOMode          = QSPI_SIOO_INST_EVERY_CMD;
+
+  /* Enable write operations */
+  if (QSPI_WriteEnable(&QSPIHandle) != QSPI_OK)
+  {
+    return QSPI_ERROR;
+  }
+
+  /* Send the command */
+  if (HAL_QSPI_Command(&QSPIHandle, &s_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
+  {
+    return QSPI_ERROR;
+  }
+  
+  /* Configure automatic polling mode to wait for end of erase */  
+  if (QSPI_AutoPollingMemReady(&QSPIHandle, N25Q128A_BULK_ERASE_MAX_TIME) != QSPI_OK)
+  {
+    return QSPI_ERROR;
+  }
+
+  return QSPI_OK;
+}
+
+/**
+  * @brief  Reads current status of the QSPI memory.
+  * @retval QSPI memory status
+  */
+uint8_t BSP_QSPI_GetStatus(void)
+{
+  QSPI_CommandTypeDef s_command;
+  uint8_t reg;
+
+  /* Initialize the read flag status register command */
+  s_command.InstructionMode   = QSPI_INSTRUCTION_1_LINE;
+  s_command.Instruction       = READ_FLAG_STATUS_REG_CMD;
+  s_command.AddressMode       = QSPI_ADDRESS_NONE;
+  s_command.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE;
+  s_command.DataMode          = QSPI_DATA_1_LINE;
+  s_command.DummyCycles       = 0;
+  s_command.NbData            = 1;
+  s_command.DdrMode           = QSPI_DDR_MODE_DISABLE;
+  s_command.DdrHoldHalfCycle  = QSPI_DDR_HHC_ANALOG_DELAY;
+  s_command.SIOOMode          = QSPI_SIOO_INST_EVERY_CMD;
+
+  /* Configure the command */
+  if (HAL_QSPI_Command(&QSPIHandle, &s_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
+  {
+    return QSPI_ERROR;
+  }
+
+  /* Reception of the data */
+  if (HAL_QSPI_Receive(&QSPIHandle, &reg, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
+  {
+    return QSPI_ERROR;
+  }
+  
+  /* Check the value of the register */
+  if ((reg & (N25Q128A_FSR_PRERR | N25Q128A_FSR_VPPERR | N25Q128A_FSR_PGERR | N25Q128A_FSR_ERERR)) != 0)
+  {
+    return QSPI_ERROR;
+  }
+  else if ((reg & (N25Q128A_FSR_PGSUS | N25Q128A_FSR_ERSUS)) != 0)
+  {
+    return QSPI_SUSPENDED;
+  }
+  else if ((reg & N25Q128A_FSR_READY) != 0)
+  {
+    return QSPI_OK;
+  }
+  else
+  {
+    return QSPI_BUSY;
+  }
+}
+
+/**
+  * @brief  Reads the configuration of the memory and fills QspiInfo struct
+  * @param  pInfo pointer to Info structure
+  * @retval QSPI memory status
+  */
+uint8_t BSP_QSPI_GetInfo(QSPI_InfoTypeDef* pInfo)
+{
+  /* Configure the structure with the memory configuration */
+  pInfo->FlashSize          = N25Q128A_FLASH_SIZE;
+  pInfo->EraseSectorSize    = N25Q128A_SUBSECTOR_SIZE;
+  pInfo->EraseSectorsNumber = (N25Q128A_FLASH_SIZE/N25Q128A_SUBSECTOR_SIZE);
+  pInfo->ProgPageSize       = N25Q128A_PAGE_SIZE;
+  pInfo->ProgPagesNumber    = (N25Q128A_FLASH_SIZE/N25Q128A_PAGE_SIZE);
+
+  return QSPI_OK;
+}
+
+/**
+  * @brief  Configure the QSPI in memory-mapped mode 
+  * @retval QSPI memory status
+  */
+uint8_t BSP_QSPI_EnableMemoryMappedMode(void)
+{
+  QSPI_CommandTypeDef      s_command;
+  QSPI_MemoryMappedTypeDef s_mem_mapped_cfg;
+
+  /* Configure the command for the read instruction */
+  s_command.InstructionMode   = QSPI_INSTRUCTION_1_LINE;
+  s_command.Instruction       = QUAD_INOUT_FAST_READ_CMD;
+  s_command.AddressMode       = QSPI_ADDRESS_4_LINES;
+  s_command.AddressSize       = QSPI_ADDRESS_24_BITS;
+  s_command.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE;
+  s_command.DataMode          = QSPI_DATA_4_LINES;
+  s_command.DummyCycles       = N25Q128A_DUMMY_CYCLES_READ_QUAD;
+  s_command.DdrMode           = QSPI_DDR_MODE_DISABLE;
+  s_command.DdrHoldHalfCycle  = QSPI_DDR_HHC_ANALOG_DELAY;
+  s_command.SIOOMode          = QSPI_SIOO_INST_EVERY_CMD;
+  
+  /* Configure the memory mapped mode */
+  s_mem_mapped_cfg.TimeOutActivation = QSPI_TIMEOUT_COUNTER_DISABLE;
+  
+  if (HAL_QSPI_MemoryMapped(&QSPIHandle, &s_command, &s_mem_mapped_cfg) != HAL_OK)
+  {
+    return QSPI_ERROR;
+  }
+
+  return QSPI_OK;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup STM32469I_Discovery_QSPI_Private_Functions STM32469I Discovery QSPI Private Functions
+  * @{
+  */
+
+/**
+  * @brief QSPI MSP Initialization
+  *        This function configures the hardware resources used in this example:
+  *           - Peripheral's clock enable
+  *           - Peripheral's GPIO Configuration
+  *           - NVIC configuration for QSPI interrupt
+  */
+__weak void BSP_QSPI_MspInit(QSPI_HandleTypeDef *hqspi, void *Params)
+{
+  GPIO_InitTypeDef gpio_init_structure;
+
+  /*##-1- Enable peripherals and GPIO Clocks #################################*/
+  /* Enable the QuadSPI memory interface clock */
+  QSPI_CLK_ENABLE();
+  /* Reset the QuadSPI memory interface */
+  QSPI_FORCE_RESET();
+  QSPI_RELEASE_RESET();
+  /* Enable GPIO clocks */
+  QSPI_CS_GPIO_CLK_ENABLE();
+  QSPI_DX_CLK_GPIO_CLK_ENABLE();
+
+  /*##-2- Configure peripheral GPIO ##########################################*/
+  /* QSPI CS GPIO pin configuration  */
+  gpio_init_structure.Pin       = QSPI_CS_PIN;
+  gpio_init_structure.Mode      = GPIO_MODE_AF_PP;
+  gpio_init_structure.Pull      = GPIO_PULLUP;
+  gpio_init_structure.Speed     = GPIO_SPEED_HIGH;
+  gpio_init_structure.Alternate = GPIO_AF10_QSPI;
+  HAL_GPIO_Init(QSPI_CS_GPIO_PORT, &gpio_init_structure);
+
+  /* QSPI CLK GPIO pin configuration  */
+  gpio_init_structure.Pin       = QSPI_CLK_PIN;
+  gpio_init_structure.Pull      = GPIO_NOPULL;
+  gpio_init_structure.Alternate = GPIO_AF9_QSPI;
+  HAL_GPIO_Init(QSPI_CLK_GPIO_PORT, &gpio_init_structure);
+
+  /* QSPI D0 and D1 GPIO pin configuration  */
+  gpio_init_structure.Pin       = (QSPI_D0_PIN | QSPI_D1_PIN);
+  gpio_init_structure.Alternate = GPIO_AF10_QSPI;
+  HAL_GPIO_Init(QSPI_DX_GPIO_PORT, &gpio_init_structure);
+
+  /* QSPI D2 and D3 GPIO pin configuration  */
+  gpio_init_structure.Pin       = (QSPI_D2_PIN | QSPI_D3_PIN) ;
+  gpio_init_structure.Alternate = GPIO_AF9_QSPI;
+  HAL_GPIO_Init(QSPI_DX_GPIO_PORT, &gpio_init_structure);
+
+  /*##-3- Configure the NVIC for QSPI #########################################*/
+  /* NVIC configuration for QSPI interrupt */
+  HAL_NVIC_SetPriority(QUADSPI_IRQn, 0x0F, 0);
+  HAL_NVIC_EnableIRQ(QUADSPI_IRQn);
+
+}
+
+/**
+  * @brief QSPI MSP De-Initialization
+  *        This function frees the hardware resources used in this example:
+  *          - Disable the Peripheral's clock
+  *          - Revert GPIO and NVIC configuration to their default state
+  */
+__weak void BSP_QSPI_MspDeInit(QSPI_HandleTypeDef *hqspi, void *Params)
+{
+  /*##-1- Disable the NVIC for QSPI ###########################################*/
+  HAL_NVIC_DisableIRQ(QUADSPI_IRQn);
+
+  /*##-2- Disable peripherals and GPIO Clocks ################################*/
+  /* De-Configure QSPI pins */
+  HAL_GPIO_DeInit(QSPI_CS_GPIO_PORT, QSPI_CS_PIN);
+  HAL_GPIO_DeInit(QSPI_CLK_GPIO_PORT, QSPI_CLK_PIN);
+  HAL_GPIO_DeInit(QSPI_DX_GPIO_PORT, QSPI_D0_PIN);
+  HAL_GPIO_DeInit(QSPI_DX_GPIO_PORT, QSPI_D1_PIN);
+  HAL_GPIO_DeInit(QSPI_DX_GPIO_PORT, QSPI_D2_PIN);
+  HAL_GPIO_DeInit(QSPI_DX_GPIO_PORT, QSPI_D3_PIN);
+
+  /*##-3- Reset peripherals ##################################################*/
+  /* Reset the QuadSPI memory interface */
+  QSPI_FORCE_RESET();
+  QSPI_RELEASE_RESET();
+
+  /* Disable the QuadSPI memory interface clock */
+  QSPI_CLK_DISABLE();
+}
+
+/**
+  * @brief  This function reset the QSPI memory.
+  * @param  hqspi: QSPI handle
+  */
+static uint8_t QSPI_ResetMemory(QSPI_HandleTypeDef *hqspi)
+{
+  QSPI_CommandTypeDef s_command;
+
+  /* Initialize the reset enable command */
+  s_command.InstructionMode   = QSPI_INSTRUCTION_1_LINE;
+  s_command.Instruction       = RESET_ENABLE_CMD;
+  s_command.AddressMode       = QSPI_ADDRESS_NONE;
+  s_command.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE;
+  s_command.DataMode          = QSPI_DATA_NONE;
+  s_command.DummyCycles       = 0;
+  s_command.DdrMode           = QSPI_DDR_MODE_DISABLE;
+  s_command.DdrHoldHalfCycle  = QSPI_DDR_HHC_ANALOG_DELAY;
+  s_command.SIOOMode          = QSPI_SIOO_INST_EVERY_CMD;
+
+  /* Send the command */
+  if (HAL_QSPI_Command(hqspi, &s_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
+  {
+    return QSPI_ERROR;
+  }
+
+  /* Send the reset memory command */
+  s_command.Instruction = RESET_MEMORY_CMD;
+  if (HAL_QSPI_Command(hqspi, &s_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
+  {
+    return QSPI_ERROR;
+  }
+
+  /* Configure automatic polling mode to wait the memory is ready */  
+  if (QSPI_AutoPollingMemReady(hqspi, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != QSPI_OK)
+  {
+    return QSPI_ERROR;
+  }
+
+  return QSPI_OK;
+}
+
+/**
+  * @brief  This function configure the dummy cycles on memory side.
+  * @param  hqspi: QSPI handle
+  */
+static uint8_t QSPI_DummyCyclesCfg(QSPI_HandleTypeDef *hqspi)
+{
+  QSPI_CommandTypeDef s_command;
+  uint8_t reg;
+
+  /* Initialize the read volatile configuration register command */
+  s_command.InstructionMode   = QSPI_INSTRUCTION_1_LINE;
+  s_command.Instruction       = READ_VOL_CFG_REG_CMD;
+  s_command.AddressMode       = QSPI_ADDRESS_NONE;
+  s_command.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE;
+  s_command.DataMode          = QSPI_DATA_1_LINE;
+  s_command.DummyCycles       = 0;
+  s_command.NbData            = 1;
+  s_command.DdrMode           = QSPI_DDR_MODE_DISABLE;
+  s_command.DdrHoldHalfCycle  = QSPI_DDR_HHC_ANALOG_DELAY;
+  s_command.SIOOMode          = QSPI_SIOO_INST_EVERY_CMD;
+
+  /* Configure the command */
+  if (HAL_QSPI_Command(hqspi, &s_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
+  {
+    return QSPI_ERROR;
+  }
+
+  /* Reception of the data */
+  if (HAL_QSPI_Receive(hqspi, &reg, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
+  {
+    return QSPI_ERROR;
+  }
+
+  /* Enable write operations */
+  if (QSPI_WriteEnable(hqspi) != QSPI_OK)
+  {
+    return QSPI_ERROR;
+  }
+
+  /* Update volatile configuration register (with new dummy cycles) */  
+  s_command.Instruction = WRITE_VOL_CFG_REG_CMD;
+  MODIFY_REG(reg, N25Q128A_VCR_NB_DUMMY, (N25Q128A_DUMMY_CYCLES_READ_QUAD << POSITION_VAL(N25Q128A_VCR_NB_DUMMY)));
+      
+  /* Configure the write volatile configuration register command */
+  if (HAL_QSPI_Command(hqspi, &s_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
+  {
+    return QSPI_ERROR;
+  }
+
+  /* Transmission of the data */
+  if (HAL_QSPI_Transmit(hqspi, &reg, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
+  {
+    return QSPI_ERROR;
+  }
+  
+  return QSPI_OK;
+}
+
+/**
+  * @brief  This function send a Write Enable and wait it is effective.
+  * @param  hqspi: QSPI handle
+  */
+static uint8_t QSPI_WriteEnable(QSPI_HandleTypeDef *hqspi)
+{
+  QSPI_CommandTypeDef     s_command;
+  QSPI_AutoPollingTypeDef s_config;
+
+  /* Enable write operations */
+  s_command.InstructionMode   = QSPI_INSTRUCTION_1_LINE;
+  s_command.Instruction       = WRITE_ENABLE_CMD;
+  s_command.AddressMode       = QSPI_ADDRESS_NONE;
+  s_command.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE;
+  s_command.DataMode          = QSPI_DATA_NONE;
+  s_command.DummyCycles       = 0;
+  s_command.DdrMode           = QSPI_DDR_MODE_DISABLE;
+  s_command.DdrHoldHalfCycle  = QSPI_DDR_HHC_ANALOG_DELAY;
+  s_command.SIOOMode          = QSPI_SIOO_INST_EVERY_CMD;
+
+  if (HAL_QSPI_Command(hqspi, &s_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
+  {
+    return QSPI_ERROR;
+  }
+  
+  /* Configure automatic polling mode to wait for write enabling */  
+  s_config.Match           = N25Q128A_SR_WREN;
+  s_config.Mask            = N25Q128A_SR_WREN;
+  s_config.MatchMode       = QSPI_MATCH_MODE_AND;
+  s_config.StatusBytesSize = 1;
+  s_config.Interval        = 0x10;
+  s_config.AutomaticStop   = QSPI_AUTOMATIC_STOP_ENABLE;
+
+  s_command.Instruction    = READ_STATUS_REG_CMD;
+  s_command.DataMode       = QSPI_DATA_1_LINE;
+
+  if (HAL_QSPI_AutoPolling(hqspi, &s_command, &s_config, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
+  {
+    return QSPI_ERROR;
+  }
+
+  return QSPI_OK;
+}
+
+/**
+  * @brief  This function read the SR of the memory and wait the EOP.
+  * @param  hqspi: QSPI handle
+  * @param  Timeout: timeout value before returning an error
+  */
+static uint8_t QSPI_AutoPollingMemReady(QSPI_HandleTypeDef *hqspi, uint32_t Timeout)
+{
+  QSPI_CommandTypeDef     s_command;
+  QSPI_AutoPollingTypeDef s_config;
+
+  /* Configure automatic polling mode to wait for memory ready */  
+  s_command.InstructionMode   = QSPI_INSTRUCTION_1_LINE;
+  s_command.Instruction       = READ_STATUS_REG_CMD;
+  s_command.AddressMode       = QSPI_ADDRESS_NONE;
+  s_command.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE;
+  s_command.DataMode          = QSPI_DATA_1_LINE;
+  s_command.DummyCycles       = 0;
+  s_command.DdrMode           = QSPI_DDR_MODE_DISABLE;
+  s_command.DdrHoldHalfCycle  = QSPI_DDR_HHC_ANALOG_DELAY;
+  s_command.SIOOMode          = QSPI_SIOO_INST_EVERY_CMD;
+
+  s_config.Match           = 0;
+  s_config.Mask            = N25Q128A_SR_WIP;
+  s_config.MatchMode       = QSPI_MATCH_MODE_AND;
+  s_config.StatusBytesSize = 1;
+  s_config.Interval        = 0x10;
+  s_config.AutomaticStop   = QSPI_AUTOMATIC_STOP_ENABLE;
+
+  if (HAL_QSPI_AutoPolling(hqspi, &s_command, &s_config, Timeout) != HAL_OK)
+  {
+    return QSPI_ERROR;
+  }
+
+  return QSPI_OK;
+}
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
diff --git a/Drivers/BSP/STM32469I-Discovery/stm32469i_discovery_qspi.h b/Drivers/BSP/STM32469I-Discovery/stm32469i_discovery_qspi.h
new file mode 100644
index 0000000..2abf9ad
--- /dev/null
+++ b/Drivers/BSP/STM32469I-Discovery/stm32469i_discovery_qspi.h
@@ -0,0 +1,145 @@
+/**
+  ******************************************************************************
+  * @file    stm32469i_discovery_qspi.h
+  * @author  MCD Application Team
+  * @brief   This file contains the common defines and functions prototypes for
+  *          the stm32469i_discovery_qspi.c driver.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup BSP
+  * @{
+  */
+
+/** @addtogroup STM32469I_Discovery
+  * @{
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32469I_DISCOVERY_QSPI_H
+#define __STM32469I_DISCOVERY_QSPI_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal.h"
+#include "../Components/n25q128a/n25q128a.h"
+
+
+/** @addtogroup STM32469I_Discovery_QSPI
+  * @{
+  */
+
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup STM32469I_Discovery_QSPI_Exported_Constants STM32469I Discovery QSPI Exported Constants
+  * @{
+  */
+/* QSPI Error codes */
+#define QSPI_OK            ((uint8_t)0x00)
+#define QSPI_ERROR         ((uint8_t)0x01)
+#define QSPI_BUSY          ((uint8_t)0x02)
+#define QSPI_NOT_SUPPORTED ((uint8_t)0x04)
+#define QSPI_SUSPENDED     ((uint8_t)0x08)
+
+
+/* Definition for QSPI clock resources */
+#define QSPI_CLK_ENABLE()             __HAL_RCC_QSPI_CLK_ENABLE()
+#define QSPI_CLK_DISABLE()            __HAL_RCC_QSPI_CLK_DISABLE()
+#define QSPI_CS_GPIO_CLK_ENABLE()     __HAL_RCC_GPIOB_CLK_ENABLE()
+#define QSPI_CS_GPIO_CLK_DISABLE()  __HAL_RCC_GPIOB_CLK_DISABLE()
+#define QSPI_DX_CLK_GPIO_CLK_ENABLE() __HAL_RCC_GPIOF_CLK_ENABLE()
+#define QSPI_DX_CLK_GPIO_CLK_DISABLE()  __HAL_RCC_GPIOF_CLK_DISABLE()
+
+#define QSPI_FORCE_RESET()            __HAL_RCC_QSPI_FORCE_RESET()
+#define QSPI_RELEASE_RESET()          __HAL_RCC_QSPI_RELEASE_RESET()
+
+/* Definition for QSPI Pins */
+#define QSPI_CS_PIN                GPIO_PIN_6
+#define QSPI_CS_GPIO_PORT          GPIOB
+#define QSPI_CLK_PIN               GPIO_PIN_10
+#define QSPI_CLK_GPIO_PORT         GPIOF
+#define QSPI_D0_PIN                GPIO_PIN_8
+#define QSPI_D1_PIN                GPIO_PIN_9
+#define QSPI_D2_PIN                GPIO_PIN_7
+#define QSPI_D3_PIN                GPIO_PIN_6
+#define QSPI_DX_GPIO_PORT          GPIOF
+
+
+/**
+  * @}
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup STM32469I_Discovery_QSPI_Exported_Types STM32469I Discovery QSPI Exported Types
+  * @{
+  */
+/**
+ * @brief QSPI Info
+ * */
+typedef struct {
+  uint32_t FlashSize;          /*!< Size of the flash                         */
+  uint32_t EraseSectorSize;    /*!< Size of sectors for the erase operation   */
+  uint32_t EraseSectorsNumber; /*!< Number of sectors for the erase operation */
+  uint32_t ProgPageSize;       /*!< Size of pages for the program operation   */
+  uint32_t ProgPagesNumber;    /*!< Number of pages for the program operation */
+} QSPI_InfoTypeDef;
+
+/**
+  * @}
+  */
+
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup STM32469I_Discovery_QSPI_Exported_Functions STM32469I Discovery QSPI Exported Functions
+  * @{
+  */
+uint8_t BSP_QSPI_Init       (void);
+uint8_t BSP_QSPI_DeInit     (void);
+uint8_t BSP_QSPI_Read       (uint8_t* pData, uint32_t ReadAddr, uint32_t Size);
+uint8_t BSP_QSPI_Write      (uint8_t* pData, uint32_t WriteAddr, uint32_t Size);
+uint8_t BSP_QSPI_Erase_Block(uint32_t BlockAddress);
+uint8_t BSP_QSPI_Erase_Chip (void);
+uint8_t BSP_QSPI_GetStatus  (void);
+uint8_t BSP_QSPI_GetInfo    (QSPI_InfoTypeDef* pInfo);
+uint8_t BSP_QSPI_EnableMemoryMappedMode(void);
+/* BSP Aliased function maintained for legacy purpose */
+#define BSP_QSPI_MemoryMappedMode      BSP_QSPI_EnableMemoryMappedMode
+
+/* These function can be modified in case the current settings (e.g. DMA stream)
+   need to be changed for specific application needs */
+void BSP_QSPI_MspInit(QSPI_HandleTypeDef *hqspi, void *Params);
+void BSP_QSPI_MspDeInit(QSPI_HandleTypeDef *hqspi, void *Params);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32469I_DISCOVERY_QSPI_H */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
diff --git a/Drivers/BSP/STM32469I-Discovery/stm32469i_discovery_sd.c b/Drivers/BSP/STM32469I-Discovery/stm32469i_discovery_sd.c
new file mode 100644
index 0000000..63f40b9
--- /dev/null
+++ b/Drivers/BSP/STM32469I-Discovery/stm32469i_discovery_sd.c
@@ -0,0 +1,578 @@
+/**
+  ******************************************************************************
+  * @file    stm32469i_discovery_sd.c
+  * @author  MCD Application Team
+  * @brief   This file includes the uSD card driver mounted on STM32469I-Discovery
+  *          board.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* File Info : -----------------------------------------------------------------
+                                   User NOTES
+1. How To use this driver:
+--------------------------
+   - This driver is used to drive the micro SD external card mounted on STM32469I-Discovery
+     board.
+   - This driver does not need a specific component driver for the micro SD device
+     to be included with.
+
+2. Driver description:
+---------------------
+  + Initialization steps:
+     o Initialize the micro SD card using the BSP_SD_Init() function. This
+       function includes the MSP layer hardware resources initialization and the
+       SDIO interface configuration to interface with the external micro SD. It
+       also includes the micro SD initialization sequence.
+     o To check the SD card presence you can use the function BSP_SD_IsDetected() which
+       returns the detection status
+     o If SD presence detection interrupt mode is desired, you must configure the 
+       SD detection interrupt mode by calling the function BSP_SD_ITConfig(). The interrupt 
+       is generated as an external interrupt whenever the micro SD card is 
+       plugged/unplugged in/from the board.
+     o The function BSP_SD_GetCardInfo() is used to get the micro SD card information
+       which is stored in the structure "HAL_SD_CardInfoTypeDef".
+
+     + Micro SD card operations
+        o The micro SD card can be accessed with read/write block(s) operations once 
+          it is ready for access. The access can be performed whether using the polling
+          mode by calling the functions BSP_SD_ReadBlocks()/BSP_SD_WriteBlocks(), or by DMA 
+          transfer using the functions BSP_SD_ReadBlocks_DMA()/BSP_SD_WriteBlocks_DMA()
+        o The DMA transfer complete is used with interrupt mode. Once the SD transfer
+          is complete, the SD interrupt is handled using the function BSP_SD_IRQHandler(),
+          the DMA Tx/Rx transfer complete are handled using the functions
+          BSP_SD_DMA_Tx_IRQHandler()/BSP_SD_DMA_Rx_IRQHandler(). The corresponding user callbacks 
+          are implemented by the user at application level. 
+        o The SD erase block(s) is performed using the function BSP_SD_Erase() with specifying
+          the number of blocks to erase.
+        o The SD runtime status is returned when calling the function BSP_SD_GetCardState().
+
+------------------------------------------------------------------------------*/
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32469i_discovery_sd.h"
+
+/** @addtogroup BSP
+  * @{
+  */
+
+/** @addtogroup STM32469I_Discovery
+  * @{
+  */
+
+/** @defgroup STM32469I-Discovery_SD STM32469I Discovery SD
+  * @{
+  */
+
+
+/** @defgroup STM32469I-Discovery_SD_Private_TypesDefinitions STM32469I Discovery SD Private TypesDef
+  * @{
+  */
+/**
+  * @}
+  */
+
+/** @defgroup STM32469I-Discovery_SD_Private_Defines STM32469I Discovery SD Private Defines
+  * @{
+  */
+/**
+  * @}
+  */
+
+/** @defgroup STM32469I-Discovery_SD_Private_Macros STM32469I Discovery SD Private Macro
+  * @{
+  */
+/**
+  * @}
+  */
+
+/** @defgroup STM32469I-Discovery_SD_Private_Variables STM32469I Discovery SD Private Variables
+  * @{
+  */
+SD_HandleTypeDef uSdHandle;
+
+/**
+  * @}
+  */
+
+/** @defgroup STM32469I-Discovery_SD_Private_FunctionPrototypes STM32469I Discovery SD Private Prototypes
+  * @{
+  */
+/**
+  * @}
+  */
+
+/** @defgroup STM32469I-Discovery_SD_Private_Functions STM32469I Discovery SD Private Functions
+  * @{
+  */
+
+/**
+  * @brief  Initializes the SD card device.
+  * @retval SD status
+  */
+uint8_t BSP_SD_Init(void)
+{
+  uint8_t sd_state = MSD_OK;
+
+  /* PLLSAI is dedicated to LCD periph. Do not use it to get 48MHz*/
+
+  /* uSD device interface configuration */
+  uSdHandle.Instance = SDIO;
+
+  uSdHandle.Init.ClockEdge           = SDIO_CLOCK_EDGE_RISING;
+  uSdHandle.Init.ClockBypass         = SDIO_CLOCK_BYPASS_DISABLE;
+  uSdHandle.Init.ClockPowerSave      = SDIO_CLOCK_POWER_SAVE_DISABLE;
+  uSdHandle.Init.BusWide             = SDIO_BUS_WIDE_1B;
+  uSdHandle.Init.HardwareFlowControl = SDIO_HARDWARE_FLOW_CONTROL_ENABLE;
+  uSdHandle.Init.ClockDiv            = SDIO_TRANSFER_CLK_DIV;
+
+  /* Msp SD Detect pin initialization */
+  BSP_SD_Detect_MspInit(&uSdHandle, NULL);
+  if(BSP_SD_IsDetected() != SD_PRESENT)   /* Check if SD card is present */
+  {
+    return MSD_ERROR_SD_NOT_PRESENT;
+  }
+
+  /* Msp SD initialization */
+  BSP_SD_MspInit(&uSdHandle, NULL);
+
+  /* HAL SD initialization */
+  if(HAL_SD_Init(&uSdHandle) != HAL_OK)
+  {
+    sd_state = MSD_ERROR;
+  }
+
+  /* Configure SD Bus width */
+  if(sd_state == MSD_OK)
+  {
+    /* Enable wide operation */
+    if(HAL_SD_ConfigWideBusOperation(&uSdHandle, SDIO_BUS_WIDE_4B) != HAL_OK)
+    {
+      sd_state = MSD_ERROR;
+    }
+    else
+    {
+      sd_state = MSD_OK;
+    }
+  }
+  return  sd_state;
+}
+
+/**
+  * @brief  DeInitializes the SD card device.
+  * @retval SD status
+  */
+uint8_t BSP_SD_DeInit(void)
+{
+  uint8_t sd_state = MSD_OK;
+
+  uSdHandle.Instance = SDIO;
+
+  /* HAL SD deinitialization */
+  if(HAL_SD_DeInit(&uSdHandle) != HAL_OK)
+  {
+    sd_state = MSD_ERROR;
+  }
+
+  /* Msp SD deinitialization */
+  uSdHandle.Instance = SDIO;
+  BSP_SD_MspDeInit(&uSdHandle, NULL);
+
+  return  sd_state;
+}
+
+/**
+  * @brief  Configures Interrupt mode for SD detection pin.
+  * @retval Returns 0
+  */
+uint8_t BSP_SD_ITConfig(void)
+{
+  GPIO_InitTypeDef gpio_init_structure;
+
+  /* Configure Interrupt mode for SD detection pin */
+  gpio_init_structure.Pin = SD_DETECT_PIN;
+  gpio_init_structure.Pull = GPIO_PULLUP;
+  gpio_init_structure.Speed = GPIO_SPEED_FAST;
+  gpio_init_structure.Mode = GPIO_MODE_IT_RISING_FALLING;
+  HAL_GPIO_Init(SD_DETECT_GPIO_PORT, &gpio_init_structure);
+
+  /* Enable and set SD detect EXTI Interrupt to the lowest priority */
+  HAL_NVIC_SetPriority((IRQn_Type)(SD_DETECT_EXTI_IRQn), 0x0F, 0x00);
+  HAL_NVIC_EnableIRQ((IRQn_Type)(SD_DETECT_EXTI_IRQn));
+
+  return MSD_OK;
+}
+
+/**
+ * @brief  Detects if SD card is correctly plugged in the memory slot or not.
+ * @retval Returns if SD is detected or not
+ */
+uint8_t BSP_SD_IsDetected(void)
+{
+  __IO uint8_t  status = SD_PRESENT;
+
+  /* Check SD card detect pin */
+  if (HAL_GPIO_ReadPin(SD_DETECT_GPIO_PORT, SD_DETECT_PIN) == GPIO_PIN_SET)
+  {
+    status = SD_NOT_PRESENT;
+  }
+
+    return status;
+}
+
+/**
+  * @brief  Reads block(s) from a specified address in an SD card, in polling mode.
+  * @param  pData: Pointer to the buffer that will contain the data to transmit
+  * @param  ReadAddr: Address from where data is to be read
+  * @param  NumOfBlocks: Number of SD blocks to read
+  * @param  Timeout: Timeout for read operation
+  * @retval SD status
+  */
+uint8_t BSP_SD_ReadBlocks(uint32_t *pData, uint32_t ReadAddr, uint32_t NumOfBlocks, uint32_t Timeout)
+{
+  if(HAL_SD_ReadBlocks(&uSdHandle, (uint8_t *)pData, ReadAddr, NumOfBlocks, Timeout) != HAL_OK)
+  {
+    return MSD_ERROR;
+  }
+  else
+  {
+    return MSD_OK;
+  }
+}
+
+/**
+  * @brief  Writes block(s) to a specified address in an SD card, in polling mode. 
+  * @param  pData: Pointer to the buffer that will contain the data to transmit
+  * @param  WriteAddr: Address from where data is to be written
+  * @param  NumOfBlocks: Number of SD blocks to write
+  * @param  Timeout: Timeout for write operation
+  * @retval SD status
+  */
+uint8_t BSP_SD_WriteBlocks(uint32_t *pData, uint32_t WriteAddr, uint32_t NumOfBlocks, uint32_t Timeout)
+{
+  if(HAL_SD_WriteBlocks(&uSdHandle, (uint8_t *)pData, WriteAddr, NumOfBlocks, Timeout) != HAL_OK)
+  {
+    return MSD_ERROR;
+  }
+  else
+  {
+    return MSD_OK;
+  }
+}
+
+/**
+  * @brief  Reads block(s) from a specified address in an SD card, in DMA mode.
+  * @param  pData: Pointer to the buffer that will contain the data to transmit
+  * @param  ReadAddr: Address from where data is to be read
+  * @param  NumOfBlocks: Number of SD blocks to read 
+  * @retval SD status
+  */
+uint8_t BSP_SD_ReadBlocks_DMA(uint32_t *pData, uint32_t ReadAddr, uint32_t NumOfBlocks)
+{  
+  /* Read block(s) in DMA transfer mode */
+  if(HAL_SD_ReadBlocks_DMA(&uSdHandle, (uint8_t *)pData, ReadAddr, NumOfBlocks) != HAL_OK)
+  {
+    return MSD_ERROR;
+  }
+  else
+  {
+    return MSD_OK;
+  }
+}
+
+/**
+  * @brief  Writes block(s) to a specified address in an SD card, in DMA mode.
+  * @param  pData: Pointer to the buffer that will contain the data to transmit
+  * @param  WriteAddr: Address from where data is to be written
+  * @param  NumOfBlocks: Number of SD blocks to write 
+  * @retval SD status
+  */
+uint8_t BSP_SD_WriteBlocks_DMA(uint32_t *pData, uint32_t WriteAddr, uint32_t NumOfBlocks)
+{ 
+  /* Write block(s) in DMA transfer mode */
+  if(HAL_SD_WriteBlocks_DMA(&uSdHandle, (uint8_t *)pData, WriteAddr, NumOfBlocks) != HAL_OK)
+  {
+    return MSD_ERROR;
+  }
+  else
+  {
+    return MSD_OK;
+  }
+}
+
+/**
+  * @brief  Erases the specified memory area of the given SD card. 
+  * @param  StartAddr: Start byte address
+  * @param  EndAddr: End byte address
+  * @retval SD status
+  */
+uint8_t BSP_SD_Erase(uint32_t StartAddr, uint32_t EndAddr)
+{
+  if(HAL_SD_Erase(&uSdHandle, StartAddr, EndAddr) != HAL_OK)
+  {
+    return MSD_ERROR;
+  }
+  else
+  {
+    return MSD_OK;
+  }
+}
+
+/**
+  * @brief  Initializes the SD MSP.
+  * @param  hsd: SD handle
+  * @param  Params : pointer on additional configuration parameters, can be NULL.
+  */
+__weak void BSP_SD_MspInit(SD_HandleTypeDef *hsd, void *Params)
+{
+  static DMA_HandleTypeDef dma_rx_handle;
+  static DMA_HandleTypeDef dma_tx_handle;
+  GPIO_InitTypeDef gpio_init_structure;
+
+  /* Enable SDIO clock */
+  __HAL_RCC_SDIO_CLK_ENABLE();
+
+  /* Enable DMA2 clocks */
+  __DMAx_TxRx_CLK_ENABLE();
+
+  /* Enable GPIOs clock */
+  __HAL_RCC_GPIOC_CLK_ENABLE();
+  __HAL_RCC_GPIOD_CLK_ENABLE();
+
+  /* Common GPIO configuration */
+  gpio_init_structure.Mode      = GPIO_MODE_AF_PP;
+  gpio_init_structure.Pull      = GPIO_PULLUP;
+  gpio_init_structure.Speed     = GPIO_SPEED_HIGH;
+  gpio_init_structure.Alternate = GPIO_AF12_SDIO;
+
+  /* GPIOC configuration */
+  gpio_init_structure.Pin = GPIO_PIN_8 | GPIO_PIN_9 | GPIO_PIN_10 | GPIO_PIN_11 | GPIO_PIN_12;
+
+  HAL_GPIO_Init(GPIOC, &gpio_init_structure);
+
+  /* GPIOD configuration */
+  gpio_init_structure.Pin = GPIO_PIN_2;
+  HAL_GPIO_Init(GPIOD, &gpio_init_structure);
+
+  /* NVIC configuration for SDIO interrupts */
+  HAL_NVIC_SetPriority(SDIO_IRQn, 0x0E, 0);
+  HAL_NVIC_EnableIRQ(SDIO_IRQn);
+
+  /* Configure DMA Rx parameters */
+  dma_rx_handle.Init.Channel             = SD_DMAx_Rx_CHANNEL;
+  dma_rx_handle.Init.Direction           = DMA_PERIPH_TO_MEMORY;
+  dma_rx_handle.Init.PeriphInc           = DMA_PINC_DISABLE;
+  dma_rx_handle.Init.MemInc              = DMA_MINC_ENABLE;
+  dma_rx_handle.Init.PeriphDataAlignment = DMA_PDATAALIGN_WORD;
+  dma_rx_handle.Init.MemDataAlignment    = DMA_MDATAALIGN_WORD;
+  dma_rx_handle.Init.Mode                = DMA_PFCTRL;
+  dma_rx_handle.Init.Priority            = DMA_PRIORITY_VERY_HIGH;
+  dma_rx_handle.Init.FIFOMode            = DMA_FIFOMODE_ENABLE;
+  dma_rx_handle.Init.FIFOThreshold       = DMA_FIFO_THRESHOLD_FULL;
+  dma_rx_handle.Init.MemBurst            = DMA_MBURST_INC4;
+  dma_rx_handle.Init.PeriphBurst         = DMA_PBURST_INC4;
+
+  dma_rx_handle.Instance = SD_DMAx_Rx_STREAM;
+
+  /* Associate the DMA handle */
+  __HAL_LINKDMA(hsd, hdmarx, dma_rx_handle);
+
+  /* Deinitialize the stream for new transfer */
+  HAL_DMA_DeInit(&dma_rx_handle);
+
+  /* Configure the DMA stream */
+  HAL_DMA_Init(&dma_rx_handle);
+
+  /* Configure DMA Tx parameters */
+  dma_tx_handle.Init.Channel             = SD_DMAx_Tx_CHANNEL;
+  dma_tx_handle.Init.Direction           = DMA_MEMORY_TO_PERIPH;
+  dma_tx_handle.Init.PeriphInc           = DMA_PINC_DISABLE;
+  dma_tx_handle.Init.MemInc              = DMA_MINC_ENABLE;
+  dma_tx_handle.Init.PeriphDataAlignment = DMA_PDATAALIGN_WORD;
+  dma_tx_handle.Init.MemDataAlignment    = DMA_MDATAALIGN_WORD;
+  dma_tx_handle.Init.Mode                = DMA_PFCTRL;
+  dma_tx_handle.Init.Priority            = DMA_PRIORITY_VERY_HIGH;
+  dma_tx_handle.Init.FIFOMode            = DMA_FIFOMODE_ENABLE;
+  dma_tx_handle.Init.FIFOThreshold       = DMA_FIFO_THRESHOLD_FULL;
+  dma_tx_handle.Init.MemBurst            = DMA_MBURST_INC4;
+  dma_tx_handle.Init.PeriphBurst         = DMA_PBURST_INC4;
+
+  dma_tx_handle.Instance = SD_DMAx_Tx_STREAM;
+
+  /* Associate the DMA handle */
+  __HAL_LINKDMA(hsd, hdmatx, dma_tx_handle);
+
+  /* Deinitialize the stream for new transfer */
+  HAL_DMA_DeInit(&dma_tx_handle);
+
+  /* Configure the DMA stream */
+  HAL_DMA_Init(&dma_tx_handle);
+
+  /* NVIC configuration for DMA transfer complete interrupt */
+  HAL_NVIC_SetPriority(SD_DMAx_Rx_IRQn, 0x0F, 0);
+  HAL_NVIC_EnableIRQ(SD_DMAx_Rx_IRQn);
+
+  /* NVIC configuration for DMA transfer complete interrupt */
+  HAL_NVIC_SetPriority(SD_DMAx_Tx_IRQn, 0x0F, 0);
+  HAL_NVIC_EnableIRQ(SD_DMAx_Tx_IRQn);
+}
+
+/**
+  * @brief  Initializes the SD Detect pin MSP.
+  * @param  hsd: SD handle
+  * @param  Params : pointer on additional configuration parameters, can be NULL.
+  */
+__weak void BSP_SD_Detect_MspInit(SD_HandleTypeDef *hsd, void *Params)
+{
+  GPIO_InitTypeDef  gpio_init_structure;
+
+  SD_DETECT_GPIO_CLK_ENABLE();
+
+  /* GPIO configuration in input for uSD_Detect signal */
+  gpio_init_structure.Pin       = SD_DETECT_PIN;
+  gpio_init_structure.Mode      = GPIO_MODE_INPUT;
+  gpio_init_structure.Pull      = GPIO_PULLUP;
+  gpio_init_structure.Speed     = GPIO_SPEED_HIGH;
+  HAL_GPIO_Init(SD_DETECT_GPIO_PORT, &gpio_init_structure);
+}
+
+/**
+  * @brief  DeInitializes the SD MSP.
+  * @param  hsd: SD handle
+  * @param  Params : pointer on additional configuration parameters, can be NULL.
+  */
+__weak void BSP_SD_MspDeInit(SD_HandleTypeDef *hsd, void *Params)
+{
+    static DMA_HandleTypeDef dma_rx_handle;
+    static DMA_HandleTypeDef dma_tx_handle;
+
+    /* Disable NVIC for DMA transfer complete interrupts */
+    HAL_NVIC_DisableIRQ(SD_DMAx_Rx_IRQn);
+    HAL_NVIC_DisableIRQ(SD_DMAx_Tx_IRQn);
+
+    /* Deinitialize the stream for new transfer */
+    dma_rx_handle.Instance = SD_DMAx_Rx_STREAM;
+    HAL_DMA_DeInit(&dma_rx_handle);
+
+    /* Deinitialize the stream for new transfer */
+    dma_tx_handle.Instance = SD_DMAx_Tx_STREAM;
+    HAL_DMA_DeInit(&dma_tx_handle);
+
+    /* Disable NVIC for SDIO interrupts */
+    HAL_NVIC_DisableIRQ(SDIO_IRQn);
+
+    /* DeInit GPIO pins can be done in the application
+       (by surcharging this __weak function) */
+
+    /* Disable SDIO clock */
+    __HAL_RCC_SDIO_CLK_DISABLE();
+
+    /* GPOI pins clock and DMA cloks can be shut down in the applic
+       by surcgarging this __weak function */
+}
+
+/**
+  * @brief  Gets the current SD card data status.
+  * @retval Data transfer state.
+  *          This value can be one of the following values:
+  *            @arg  SD_TRANSFER_OK: No data transfer is acting
+  *            @arg  SD_TRANSFER_BUSY: Data transfer is acting
+  */
+uint8_t BSP_SD_GetCardState(void)
+{
+  return((HAL_SD_GetCardState(&uSdHandle) == HAL_SD_CARD_TRANSFER ) ? SD_TRANSFER_OK : SD_TRANSFER_BUSY);
+}
+  
+
+/**
+  * @brief  Get SD information about specific SD card.
+  * @param  CardInfo: Pointer to HAL_SD_CardInfoTypedef structure
+  * @retval None 
+  */
+void BSP_SD_GetCardInfo(HAL_SD_CardInfoTypeDef *CardInfo)
+{
+  /* Get SD card Information */
+  HAL_SD_GetCardInfo(&uSdHandle, CardInfo);
+}
+
+/**
+  * @brief SD Abort callbacks
+  * @param hsd: SD handle
+  * @retval None
+  */
+void HAL_SD_AbortCallback(SD_HandleTypeDef *hsd)
+{
+  BSP_SD_AbortCallback();
+}
+
+/**
+  * @brief Tx Transfer completed callbacks
+  * @param hsd: SD handle
+  * @retval None
+  */
+void HAL_SD_TxCpltCallback(SD_HandleTypeDef *hsd)
+{
+  BSP_SD_WriteCpltCallback();
+}
+
+/**
+  * @brief Rx Transfer completed callbacks
+  * @param hsd: SD handle
+  * @retval None
+  */
+void HAL_SD_RxCpltCallback(SD_HandleTypeDef *hsd)
+{
+  BSP_SD_ReadCpltCallback();
+}
+
+/**
+  * @brief BSP SD Abort callbacks
+  * @retval None
+  */
+__weak void BSP_SD_AbortCallback(void)
+{
+
+}
+
+/**
+  * @brief BSP Tx Transfer completed callbacks
+  * @retval None
+  */
+__weak void BSP_SD_WriteCpltCallback(void)
+{
+
+}
+
+/**
+  * @brief BSP Rx Transfer completed callbacks
+  * @retval None
+  */
+__weak void BSP_SD_ReadCpltCallback(void)
+{
+
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
diff --git a/Drivers/BSP/STM32469I-Discovery/stm32469i_discovery_sd.h b/Drivers/BSP/STM32469I-Discovery/stm32469i_discovery_sd.h
new file mode 100644
index 0000000..2b86e78
--- /dev/null
+++ b/Drivers/BSP/STM32469I-Discovery/stm32469i_discovery_sd.h
@@ -0,0 +1,143 @@
+/**
+  ******************************************************************************
+  * @file    stm32469i_discovery_sd.h
+  * @author  MCD Application Team
+  * @brief   This file contains the common defines and functions prototypes for
+  *          the stm32469i_discovery_sd.c driver.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32469I_DISCOVERY_SD_H
+#define __STM32469I_DISCOVERY_SD_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32469i_discovery.h"
+
+/** @addtogroup BSP
+  * @{
+  */
+
+/** @addtogroup STM32469I_Discovery
+  * @{
+  */
+
+/** @addtogroup STM32469I-Discovery_SD 
+  * @{
+  */
+
+/** @defgroup STM32469I-Discovery_SD_Exported_Types STM32469I Discovery SD Exported Types
+  * @{
+  */
+
+/**
+  * @brief SD Card information structure
+  */
+#define BSP_SD_CardInfo HAL_SD_CardInfoTypeDef
+/**
+  * @}
+  */
+
+/**
+  * @brief  SD status structure definition
+  */
+#define   MSD_OK                        ((uint8_t)0x00)
+#define   MSD_ERROR                     ((uint8_t)0x01)
+#define   MSD_ERROR_SD_NOT_PRESENT      ((uint8_t)0x02)
+
+/** 
+  * @brief  SD transfer state definition  
+  */     
+#define   SD_TRANSFER_OK                ((uint8_t)0x00)
+#define   SD_TRANSFER_BUSY              ((uint8_t)0x01)
+
+/** @defgroup STM32469I-Discovery_SD_Exported_Constants STM32469I Discovery SD Exported Constants
+  * @{
+  */
+#define SD_PRESENT               ((uint8_t)0x01)
+#define SD_NOT_PRESENT           ((uint8_t)0x00)
+
+#define SD_DATATIMEOUT           ((uint32_t)100000000)
+
+/* DMA definitions for SD DMA transfer */
+#define __DMAx_TxRx_CLK_ENABLE            __HAL_RCC_DMA2_CLK_ENABLE
+#define SD_DMAx_Tx_CHANNEL                DMA_CHANNEL_4
+#define SD_DMAx_Rx_CHANNEL                DMA_CHANNEL_4
+#define SD_DMAx_Tx_STREAM                 DMA2_Stream6
+#define SD_DMAx_Rx_STREAM                 DMA2_Stream3
+#define SD_DMAx_Tx_IRQn                   DMA2_Stream6_IRQn
+#define SD_DMAx_Rx_IRQn                   DMA2_Stream3_IRQn
+#define BSP_SD_IRQHandler                 SDIO_IRQHandler
+#define BSP_SD_DMA_Tx_IRQHandler          DMA2_Stream6_IRQHandler
+#define BSP_SD_DMA_Rx_IRQHandler          DMA2_Stream3_IRQHandler
+#define SD_DetectIRQHandler()             HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_8)
+/**
+  * @}
+  */
+
+/** @defgroup STM32469I-Discovery_SD_Exported_Macro STM32469I Discovery SD Exported Macro
+  * @{
+  */
+/**
+  * @}
+  */
+
+/** @defgroup STM32469I-Discovery_SD_Exported_Functions STM32469I Discovery SD Exported Functions
+  * @{
+  */
+uint8_t BSP_SD_Init(void);
+uint8_t BSP_SD_DeInit(void);
+uint8_t BSP_SD_ITConfig(void);
+uint8_t BSP_SD_ReadBlocks(uint32_t *pData, uint32_t ReadAddr, uint32_t NumOfBlocks, uint32_t Timeout);
+uint8_t BSP_SD_WriteBlocks(uint32_t *pData, uint32_t WriteAddr, uint32_t NumOfBlocks, uint32_t Timeout);
+uint8_t BSP_SD_ReadBlocks_DMA(uint32_t *pData, uint32_t ReadAddr, uint32_t NumOfBlocks);
+uint8_t BSP_SD_WriteBlocks_DMA(uint32_t *pData, uint32_t WriteAddr, uint32_t NumOfBlocks);
+uint8_t BSP_SD_Erase(uint32_t StartAddr, uint32_t EndAddr);
+uint8_t BSP_SD_GetCardState(void);
+void    BSP_SD_GetCardInfo(HAL_SD_CardInfoTypeDef *CardInfo);
+uint8_t BSP_SD_IsDetected(void);
+
+/* These functions can be modified in case the current settings (e.g. DMA stream)
+   need to be changed for specific application needs */
+void    BSP_SD_MspInit(SD_HandleTypeDef *hsd, void *Params);
+void    BSP_SD_Detect_MspInit(SD_HandleTypeDef *hsd, void *Params);
+void    BSP_SD_MspDeInit(SD_HandleTypeDef *hsd, void *Params);
+void    BSP_SD_AbortCallback(void);
+void    BSP_SD_WriteCpltCallback(void);
+void    BSP_SD_ReadCpltCallback(void);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32469I_DISCOVERY_SD_H */
diff --git a/Drivers/BSP/STM32469I-Discovery/stm32469i_discovery_sdram.c b/Drivers/BSP/STM32469I-Discovery/stm32469i_discovery_sdram.c
new file mode 100644
index 0000000..ff9bfd8
--- /dev/null
+++ b/Drivers/BSP/STM32469I-Discovery/stm32469i_discovery_sdram.c
@@ -0,0 +1,508 @@
+/**
+  ******************************************************************************
+  * @file    stm32469i_discovery_sdram.c
+  * @author  MCD Application Team
+  * @brief   This file includes the SDRAM driver for the MT48LC4M32B2B5-7 memory
+  *          device mounted on STM32469I-Discovery board.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* File Info : -----------------------------------------------------------------
+                                   User NOTES
+1. How To use this driver:
+--------------------------
+   - This driver is used to drive the MT48LC4M32B2B5-7 SDRAM external memory mounted
+     on STM32469I-Discovery board.
+   - This driver does not need a specific component driver for the SDRAM device
+     to be included with.
+
+2. Driver description:
+---------------------
+  + Initialization steps:
+     o Initialize the SDRAM external memory using the BSP_SDRAM_Init() function. This
+       function includes the MSP layer hardware resources initialization and the
+       FMC controller configuration to interface with the external SDRAM memory.
+     o It contains the SDRAM initialization sequence to program the SDRAM external
+       device using the function BSP_SDRAM_Initialization_sequence(). Note that this
+       sequence is standard for all SDRAM devices, but can include some differences
+       from a device to another. If it is the case, the right sequence should be
+       implemented separately.
+
+  + SDRAM read/write operations
+     o SDRAM external memory can be accessed with read/write operations once it is
+       initialized.
+       Read/write operation can be performed with AHB access using the functions
+       BSP_SDRAM_ReadData()/BSP_SDRAM_WriteData(), or by DMA transfer using the functions
+       BSP_SDRAM_ReadData_DMA()/BSP_SDRAM_WriteData_DMA().
+     o The AHB access is performed with 32-bit width transaction, the DMA transfer
+       configuration is fixed at single (no burst) word transfer (see the
+       BSP_SDRAM_MspInit() weak function).
+     o User can implement his own functions for read/write access with his desired
+       configurations.
+     o If interrupt mode is used for DMA transfer, the function BSP_SDRAM_DMA_IRQHandler()
+       is called in IRQ handler file, to serve the generated interrupt once the DMA
+       transfer is complete.
+     o You can send a command to the SDRAM device in runtime using the function
+       BSP_SDRAM_Sendcmd(), and giving the desired command as parameter chosen between
+       the predefined commands of the "FMC_SDRAM_CommandTypeDef" structure.
+
+------------------------------------------------------------------------------*/
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32469i_discovery_sdram.h"
+
+/** @addtogroup BSP
+  * @{
+  */
+
+/** @addtogroup STM32469I_Discovery
+  * @{
+  */
+
+/** @defgroup STM32469I-Discovery_SDRAM STM32469I Discovery SDRAM
+  * @{
+  */
+
+/** @defgroup STM32469I-Discovery_SDRAM_Private_Types_Definitions STM32469I Discovery SDRAM Private TypesDef
+  * @{
+  */
+/**
+  * @}
+  */
+
+/** @defgroup STM32469I-Discovery_SDRAM_Private_Defines STM32469I Discovery SDRAM Private Defines
+  * @{
+  */
+/**
+  * @}
+  */
+
+/** @defgroup STM32469I-Discovery_SDRAM_Private_Macros STM32469I Discovery SDRAM Private Macros
+  * @{
+  */
+/**
+  * @}
+  */
+
+/** @defgroup STM32469I-Discovery_SDRAM_Private_Variables STM32469I Discovery SDRAM Private Variables
+  * @{
+  */
+static SDRAM_HandleTypeDef sdramHandle;
+static FMC_SDRAM_TimingTypeDef Timing;
+static FMC_SDRAM_CommandTypeDef Command;
+/**
+  * @}
+  */
+
+/** @defgroup STM32469I-Discovery_SDRAM_Private_Function_Prototypes STM32469I Discovery SDRAM Private Prototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup STM32469I-Discovery_SDRAM_Private_Functions STM32469I Discovery SDRAM Private Functions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup STM32469I_Discovery_SDRAM_Exported_Functions STM32469I Discovery SDRAM Exported Functions
+  * @{
+  */
+
+/**
+  * @brief  Initializes the SDRAM device.
+  * @retval SDRAM status
+  */
+uint8_t BSP_SDRAM_Init(void)
+{
+  static uint8_t sdramstatus = SDRAM_ERROR;
+
+  /* SDRAM device configuration */
+  sdramHandle.Instance = FMC_SDRAM_DEVICE;
+
+  /* Timing configuration for 90 MHz as SD clock frequency (System clock is up to 180 MHz) */
+  Timing.LoadToActiveDelay    = 2;
+  Timing.ExitSelfRefreshDelay = 7;
+  Timing.SelfRefreshTime      = 4;
+  Timing.RowCycleDelay        = 7;
+  Timing.WriteRecoveryTime    = 2;
+  Timing.RPDelay              = 2;
+  Timing.RCDDelay             = 2;
+
+  sdramHandle.Init.SDBank             = FMC_SDRAM_BANK1;
+  sdramHandle.Init.ColumnBitsNumber   = FMC_SDRAM_COLUMN_BITS_NUM_8;
+  sdramHandle.Init.RowBitsNumber      = FMC_SDRAM_ROW_BITS_NUM_12;
+  sdramHandle.Init.MemoryDataWidth    = SDRAM_MEMORY_WIDTH;
+  sdramHandle.Init.InternalBankNumber = FMC_SDRAM_INTERN_BANKS_NUM_4;
+  sdramHandle.Init.CASLatency         = FMC_SDRAM_CAS_LATENCY_3;
+  sdramHandle.Init.WriteProtection    = FMC_SDRAM_WRITE_PROTECTION_DISABLE;
+  sdramHandle.Init.SDClockPeriod      = SDCLOCK_PERIOD;
+  sdramHandle.Init.ReadBurst          = FMC_SDRAM_RBURST_ENABLE;
+  sdramHandle.Init.ReadPipeDelay      = FMC_SDRAM_RPIPE_DELAY_0;
+
+  /* SDRAM controller initialization */
+  /* __weak function can be surcharged by the application code */
+  BSP_SDRAM_MspInit(&sdramHandle, (void *)NULL);
+  if(HAL_SDRAM_Init(&sdramHandle, &Timing) != HAL_OK)
+  {
+    sdramstatus = SDRAM_ERROR;
+  }
+  else
+  {
+    sdramstatus = SDRAM_OK;
+  }
+
+  /* SDRAM initialization sequence */
+  BSP_SDRAM_Initialization_sequence(REFRESH_COUNT);
+
+  return sdramstatus;
+}
+
+/**
+  * @brief  DeInitializes the SDRAM device.
+  * @retval SDRAM status : SDRAM_OK or SDRAM_ERROR.
+  */
+uint8_t BSP_SDRAM_DeInit(void)
+{
+  static uint8_t sdramstatus = SDRAM_ERROR;
+
+  /* SDRAM device configuration */
+  sdramHandle.Instance = FMC_SDRAM_DEVICE;
+
+  if(HAL_SDRAM_DeInit(&sdramHandle) == HAL_OK)
+  {
+    sdramstatus = SDRAM_OK;
+
+  /* SDRAM controller De-initialization */
+   BSP_SDRAM_MspDeInit(&sdramHandle, (void *)NULL);
+  }
+
+  return sdramstatus;
+}
+
+
+/**
+  * @brief  Programs the SDRAM device.
+  * @param  RefreshCount: SDRAM refresh counter value
+  */
+void BSP_SDRAM_Initialization_sequence(uint32_t RefreshCount)
+{
+  __IO uint32_t tmpmrd = 0;
+
+  /* Step 1: Configure a clock configuration enable command */
+  Command.CommandMode            = FMC_SDRAM_CMD_CLK_ENABLE;
+  Command.CommandTarget          = FMC_SDRAM_CMD_TARGET_BANK1;
+  Command.AutoRefreshNumber      = 1;
+  Command.ModeRegisterDefinition = 0;
+
+  /* Send the command */
+  HAL_SDRAM_SendCommand(&sdramHandle, &Command, SDRAM_TIMEOUT);
+
+  /* Step 2: Insert 100 us minimum delay */
+  /* Inserted delay is equal to 1 ms due to systick time base unit (ms) */
+  HAL_Delay(1);
+
+  /* Step 3: Configure a PALL (precharge all) command */
+  Command.CommandMode            = FMC_SDRAM_CMD_PALL;
+  Command.CommandTarget          = FMC_SDRAM_CMD_TARGET_BANK1;
+  Command.AutoRefreshNumber      = 1;
+  Command.ModeRegisterDefinition = 0;
+
+  /* Send the command */
+  HAL_SDRAM_SendCommand(&sdramHandle, &Command, SDRAM_TIMEOUT);
+
+  /* Step 4: Configure an Auto Refresh command */
+  Command.CommandMode            = FMC_SDRAM_CMD_AUTOREFRESH_MODE;
+  Command.CommandTarget          = FMC_SDRAM_CMD_TARGET_BANK1;
+  Command.AutoRefreshNumber      = 8;
+  Command.ModeRegisterDefinition = 0;
+
+  /* Send the command */
+  HAL_SDRAM_SendCommand(&sdramHandle, &Command, SDRAM_TIMEOUT);
+
+  /* Step 5: Program the external memory mode register */
+  tmpmrd = (uint32_t)SDRAM_MODEREG_BURST_LENGTH_1          |\
+                     SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL   |\
+                     SDRAM_MODEREG_CAS_LATENCY_3           |\
+                     SDRAM_MODEREG_OPERATING_MODE_STANDARD |\
+                     SDRAM_MODEREG_WRITEBURST_MODE_SINGLE;
+
+  Command.CommandMode            = FMC_SDRAM_CMD_LOAD_MODE;
+  Command.CommandTarget          = FMC_SDRAM_CMD_TARGET_BANK1;
+  Command.AutoRefreshNumber      = 1;
+  Command.ModeRegisterDefinition = tmpmrd;
+
+  /* Send the command */
+  HAL_SDRAM_SendCommand(&sdramHandle, &Command, SDRAM_TIMEOUT);
+
+  /* Step 6: Set the refresh rate counter */
+  /* Set the device refresh rate */
+  HAL_SDRAM_ProgramRefreshRate(&sdramHandle, RefreshCount);
+}
+
+/**
+  * @brief  Reads an mount of data from the SDRAM memory in polling mode.
+  * @param  uwStartAddress: Read start address
+  * @param  pData: Pointer to data to be read
+  * @param  uwDataSize: Size of read data from the memory
+  * @retval SDRAM status : SDRAM_OK or SDRAM_ERROR.
+  */
+uint8_t BSP_SDRAM_ReadData(uint32_t uwStartAddress, uint32_t *pData, uint32_t uwDataSize)
+{
+  if(HAL_SDRAM_Read_32b(&sdramHandle, (uint32_t *)uwStartAddress, pData, uwDataSize) != HAL_OK)
+  {
+    return SDRAM_ERROR;
+  }
+  else
+  {
+    return SDRAM_OK;
+  }
+}
+
+/**
+  * @brief  Reads an mount of data from the SDRAM memory in DMA mode.
+  * @param  uwStartAddress: Read start address
+  * @param  pData: Pointer to data to be read
+  * @param  uwDataSize: Size of read data from the memory
+  * @retval SDRAM status : SDRAM_OK or SDRAM_ERROR.
+  */
+uint8_t BSP_SDRAM_ReadData_DMA(uint32_t uwStartAddress, uint32_t *pData, uint32_t uwDataSize)
+{
+  if(HAL_SDRAM_Read_DMA(&sdramHandle, (uint32_t *)uwStartAddress, pData, uwDataSize) != HAL_OK)
+  {
+    return SDRAM_ERROR;
+  }
+  else
+  {
+    return SDRAM_OK;
+  }
+}
+
+/**
+  * @brief  Writes an mount of data to the SDRAM memory in polling mode.
+  * @param  uwStartAddress: Write start address
+  * @param  pData: Pointer to data to be written
+  * @param  uwDataSize: Size of written data from the memory
+  * @retval SDRAM status : SDRAM_OK or SDRAM_ERROR.
+  */
+uint8_t BSP_SDRAM_WriteData(uint32_t uwStartAddress, uint32_t *pData, uint32_t uwDataSize)
+{
+  if(HAL_SDRAM_Write_32b(&sdramHandle, (uint32_t *)uwStartAddress, pData, uwDataSize) != HAL_OK)
+  {
+    return SDRAM_ERROR;
+  }
+  else
+  {
+    return SDRAM_OK;
+  }
+}
+
+/**
+  * @brief  Writes an mount of data to the SDRAM memory in DMA mode.
+  * @param  uwStartAddress: Write start address
+  * @param  pData: Pointer to data to be written
+  * @param  uwDataSize: Size of written data from the memory
+  * @retval SDRAM status : SDRAM_OK or SDRAM_ERROR.
+  */
+uint8_t BSP_SDRAM_WriteData_DMA(uint32_t uwStartAddress, uint32_t *pData, uint32_t uwDataSize)
+{
+  if(HAL_SDRAM_Write_DMA(&sdramHandle, (uint32_t *)uwStartAddress, pData, uwDataSize) != HAL_OK)
+  {
+    return SDRAM_ERROR;
+  }
+  else
+  {
+    return SDRAM_OK;
+  }
+}
+
+/**
+  * @brief  Sends command to the SDRAM bank.
+  * @param  SdramCmd: Pointer to SDRAM command structure
+  * @retval HAL status : SDRAM_OK or SDRAM_ERROR.
+  */
+uint8_t BSP_SDRAM_Sendcmd(FMC_SDRAM_CommandTypeDef *SdramCmd)
+{
+  if(HAL_SDRAM_SendCommand(&sdramHandle, SdramCmd, SDRAM_TIMEOUT) != HAL_OK)
+  {
+    return SDRAM_ERROR;
+  }
+  else
+  {
+    return SDRAM_OK;
+  }
+}
+
+/**
+  * @brief  Handles SDRAM DMA transfer interrupt request.
+  */
+void BSP_SDRAM_DMA_IRQHandler(void)
+{
+  HAL_DMA_IRQHandler(sdramHandle.hdma);
+}
+
+/**
+  * @brief  Initializes SDRAM MSP.
+  * @note   This function can be surcharged by application code.
+  * @param  hsdram: pointer on SDRAM handle
+  * @param  Params: pointer on additional configuration parameters, can be NULL.
+  */
+__weak void BSP_SDRAM_MspInit(SDRAM_HandleTypeDef  *hsdram, void *Params)
+{
+  static DMA_HandleTypeDef dma_handle;
+  GPIO_InitTypeDef gpio_init_structure;
+
+  if(hsdram != (SDRAM_HandleTypeDef  *)NULL)
+  {
+    /* Enable FMC clock */
+    __HAL_RCC_FMC_CLK_ENABLE();
+
+    /* Enable chosen DMAx clock */
+    __DMAx_CLK_ENABLE();
+
+    /* Enable GPIOs clock */
+    __HAL_RCC_GPIOC_CLK_ENABLE();
+    __HAL_RCC_GPIOD_CLK_ENABLE();
+    __HAL_RCC_GPIOE_CLK_ENABLE();
+    __HAL_RCC_GPIOF_CLK_ENABLE();
+    __HAL_RCC_GPIOG_CLK_ENABLE();
+    __HAL_RCC_GPIOH_CLK_ENABLE();
+    __HAL_RCC_GPIOI_CLK_ENABLE();
+
+    /* Common GPIO configuration */
+    gpio_init_structure.Mode      = GPIO_MODE_AF_PP;
+    gpio_init_structure.Pull      = GPIO_PULLUP;
+    gpio_init_structure.Speed     = GPIO_SPEED_FAST;
+    gpio_init_structure.Alternate = GPIO_AF12_FMC;
+
+    /* GPIOC configuration : PC0 is SDNWE */
+    gpio_init_structure.Pin   = GPIO_PIN_0;
+    HAL_GPIO_Init(GPIOC, &gpio_init_structure);
+
+    /* GPIOD configuration */
+    gpio_init_structure.Pin   = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_8| GPIO_PIN_9 | GPIO_PIN_10 |\
+                                GPIO_PIN_14 | GPIO_PIN_15;
+
+
+    HAL_GPIO_Init(GPIOD, &gpio_init_structure);
+
+    /* GPIOE configuration */
+    gpio_init_structure.Pin   = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_7| GPIO_PIN_8 | GPIO_PIN_9 |\
+                                GPIO_PIN_10 | GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_13 | GPIO_PIN_14 |\
+                                GPIO_PIN_15;
+
+    HAL_GPIO_Init(GPIOE, &gpio_init_structure);
+
+    /* GPIOF configuration */
+    gpio_init_structure.Pin   = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2| GPIO_PIN_3 | GPIO_PIN_4 |\
+                                GPIO_PIN_5 | GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_13 | GPIO_PIN_14 |\
+                                GPIO_PIN_15;
+
+    HAL_GPIO_Init(GPIOF, &gpio_init_structure);
+
+    /* GPIOG configuration */
+    gpio_init_structure.Pin   = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_4| GPIO_PIN_5 | GPIO_PIN_8 |\
+                                GPIO_PIN_15;
+    HAL_GPIO_Init(GPIOG, &gpio_init_structure);
+
+    /* GPIOH configuration */
+    gpio_init_structure.Pin   = GPIO_PIN_2 | GPIO_PIN_3 | GPIO_PIN_8 | GPIO_PIN_9 |\
+                                GPIO_PIN_10 | GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_13 | GPIO_PIN_14 |\
+                                GPIO_PIN_15;
+    HAL_GPIO_Init(GPIOH, &gpio_init_structure);
+
+    /* GPIOI configuration */
+    gpio_init_structure.Pin   = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_3 | GPIO_PIN_4 |\
+                                GPIO_PIN_5 | GPIO_PIN_6 | GPIO_PIN_7 | GPIO_PIN_9 | GPIO_PIN_10;
+    HAL_GPIO_Init(GPIOI, &gpio_init_structure);
+
+    /* Configure common DMA parameters */
+    dma_handle.Init.Channel             = SDRAM_DMAx_CHANNEL;
+    dma_handle.Init.Direction           = DMA_MEMORY_TO_MEMORY;
+    dma_handle.Init.PeriphInc           = DMA_PINC_ENABLE;
+    dma_handle.Init.MemInc              = DMA_MINC_ENABLE;
+    dma_handle.Init.PeriphDataAlignment = DMA_PDATAALIGN_WORD;
+    dma_handle.Init.MemDataAlignment    = DMA_MDATAALIGN_WORD;
+    dma_handle.Init.Mode                = DMA_NORMAL;
+    dma_handle.Init.Priority            = DMA_PRIORITY_HIGH;
+    dma_handle.Init.FIFOMode            = DMA_FIFOMODE_DISABLE;
+    dma_handle.Init.FIFOThreshold       = DMA_FIFO_THRESHOLD_FULL;
+    dma_handle.Init.MemBurst            = DMA_MBURST_SINGLE;
+    dma_handle.Init.PeriphBurst         = DMA_PBURST_SINGLE;
+
+    dma_handle.Instance = SDRAM_DMAx_STREAM;
+
+    /* Associate the DMA handle */
+    __HAL_LINKDMA(hsdram, hdma, dma_handle);
+
+    /* Deinitialize the stream for new transfer */
+    HAL_DMA_DeInit(&dma_handle);
+
+    /* Configure the DMA stream */
+    HAL_DMA_Init(&dma_handle);
+
+    /* NVIC configuration for DMA transfer complete interrupt */
+    HAL_NVIC_SetPriority(SDRAM_DMAx_IRQn, 5, 0);
+    HAL_NVIC_EnableIRQ(SDRAM_DMAx_IRQn);
+
+  } /* of if(hsdram != (SDRAM_HandleTypeDef  *)NULL) */
+}
+
+/**
+  * @brief  DeInitializes SDRAM MSP.
+  * @note   This function can be surcharged by application code.
+  * @param  hsdram: pointer on SDRAM handle
+  * @param  Params: pointer on additional configuration parameters, can be NULL.
+  */
+__weak void BSP_SDRAM_MspDeInit(SDRAM_HandleTypeDef  *hsdram, void *Params)
+{
+    static DMA_HandleTypeDef dma_handle;
+
+    if(hsdram != (SDRAM_HandleTypeDef  *)NULL)
+    {
+      /* Disable NVIC configuration for DMA interrupt */
+      HAL_NVIC_DisableIRQ(SDRAM_DMAx_IRQn);
+
+      /* Deinitialize the stream for new transfer */
+      dma_handle.Instance = SDRAM_DMAx_STREAM;
+      HAL_DMA_DeInit(&dma_handle);
+
+      /* DeInit GPIO pins can be done in the application
+       (by surcharging this __weak function) */
+
+      /* GPIO pins clock, FMC clock and DMA clock can be shut down in the application
+       by surcharging this __weak function */
+
+    } /* of if(hsdram != (SDRAM_HandleTypeDef  *)NULL) */
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
diff --git a/Drivers/BSP/STM32469I-Discovery/stm32469i_discovery_sdram.h b/Drivers/BSP/STM32469I-Discovery/stm32469i_discovery_sdram.h
new file mode 100644
index 0000000..958256b
--- /dev/null
+++ b/Drivers/BSP/STM32469I-Discovery/stm32469i_discovery_sdram.h
@@ -0,0 +1,148 @@
+/**
+  ******************************************************************************
+  * @file    stm32469i_discovery_sdram.h
+  * @author  MCD Application Team
+  * @brief   This file contains the common defines and functions prototypes for
+  *          the stm32469i_discovery_sdram.c driver.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32469I_DISCOVERY_SDRAM_H
+#define __STM32469I_DISCOVERY_SDRAM_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal.h"
+
+/** @addtogroup BSP
+  * @{
+  */
+
+/** @addtogroup STM32469I_Discovery
+  * @{
+  */
+
+/** @addtogroup STM32469I-Discovery_SDRAM
+  * @{
+  */
+
+/** @defgroup STM32469I-Discovery_SDRAM_Exported_Types STM32469I Discovery SDRAM Exported Types
+  * @{
+  */
+
+/**
+  * @brief  SDRAM status structure definition
+  */
+#define   SDRAM_OK         ((uint8_t)0x00)
+#define   SDRAM_ERROR      ((uint8_t)0x01)
+
+/**
+  * @}
+  */
+
+/** @defgroup STM32469I-Discovery_SDRAM_Exported_Constants STM32469I Discovery SDRAM Exported Constants
+  * @{
+  */
+#define SDRAM_DEVICE_ADDR  ((uint32_t)0xC0000000)
+
+ /* SDRAM device size in Bytes */
+ #define SDRAM_DEVICE_SIZE  ((uint32_t)0x1000000)
+
+#define SDRAM_MEMORY_WIDTH FMC_SDRAM_MEM_BUS_WIDTH_32
+#define SDCLOCK_PERIOD     FMC_SDRAM_CLOCK_PERIOD_2
+
+/* SDRAM refresh counter (90 MHz SD clock) */
+#define REFRESH_COUNT       ((uint32_t)0x0569)
+#define  SDRAM_TIMEOUT      ((uint32_t)0xFFFF)
+
+/* DMA definitions for SDRAM DMA transfer */
+#define __DMAx_CLK_ENABLE     __HAL_RCC_DMA2_CLK_ENABLE
+#define __DMAx_CLK_DISABLE    __HAL_RCC_DMA2_CLK_DISABLE
+#define SDRAM_DMAx_CHANNEL    DMA_CHANNEL_0
+#define SDRAM_DMAx_STREAM     DMA2_Stream0
+#define SDRAM_DMAx_IRQn       DMA2_Stream0_IRQn
+#define SDRAM_DMAx_IRQHandler DMA2_Stream0_IRQHandler
+
+
+/**
+  * @brief  FMC SDRAM Mode definition register defines
+  */
+#define SDRAM_MODEREG_BURST_LENGTH_1             ((uint16_t)0x0000)
+#define SDRAM_MODEREG_BURST_LENGTH_2             ((uint16_t)0x0001)
+#define SDRAM_MODEREG_BURST_LENGTH_4             ((uint16_t)0x0002)
+#define SDRAM_MODEREG_BURST_LENGTH_8             ((uint16_t)0x0004)
+#define SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL      ((uint16_t)0x0000)
+#define SDRAM_MODEREG_BURST_TYPE_INTERLEAVED     ((uint16_t)0x0008)
+#define SDRAM_MODEREG_CAS_LATENCY_2              ((uint16_t)0x0020)
+#define SDRAM_MODEREG_CAS_LATENCY_3              ((uint16_t)0x0030)
+#define SDRAM_MODEREG_OPERATING_MODE_STANDARD    ((uint16_t)0x0000)
+#define SDRAM_MODEREG_WRITEBURST_MODE_PROGRAMMED ((uint16_t)0x0000)
+#define SDRAM_MODEREG_WRITEBURST_MODE_SINGLE     ((uint16_t)0x0200)
+/**
+  * @}
+  */
+
+/** @defgroup STM32469I-Discovery_SDRAM_Exported_Macro STM32469I Discovery SDRAM Exported Macro
+  * @{
+  */
+/**
+  * @}
+  */
+
+/** @addtogroup STM32469I_Discovery_SDRAM_Exported_Functions 
+  * @{
+  */
+uint8_t BSP_SDRAM_Init(void);
+uint8_t BSP_SDRAM_DeInit(void);
+void    BSP_SDRAM_Initialization_sequence(uint32_t RefreshCount);
+uint8_t BSP_SDRAM_ReadData(uint32_t uwStartAddress, uint32_t *pData, uint32_t uwDataSize);
+uint8_t BSP_SDRAM_ReadData_DMA(uint32_t uwStartAddress, uint32_t *pData, uint32_t uwDataSize);
+uint8_t BSP_SDRAM_WriteData(uint32_t uwStartAddress, uint32_t *pData, uint32_t uwDataSize);
+uint8_t BSP_SDRAM_WriteData_DMA(uint32_t uwStartAddress, uint32_t *pData, uint32_t uwDataSize);
+uint8_t BSP_SDRAM_Sendcmd(FMC_SDRAM_CommandTypeDef *SdramCmd);
+void    BSP_SDRAM_DMA_IRQHandler(void);
+
+/* These function can be modified in case the current settings (e.g. DMA stream)
+   need to be changed for specific application needs */
+void    BSP_SDRAM_MspInit(SDRAM_HandleTypeDef  *hsdram, void *Params);
+void    BSP_SDRAM_MspDeInit(SDRAM_HandleTypeDef  *hsdram, void *Params);
+
+/**
+  * @}
+  */
+  
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32469I_DISCOVERY_SDRAM_H */
diff --git a/Drivers/BSP/STM32469I-Discovery/stm32469i_discovery_ts.c b/Drivers/BSP/STM32469I-Discovery/stm32469i_discovery_ts.c
new file mode 100644
index 0000000..12bbbdc
--- /dev/null
+++ b/Drivers/BSP/STM32469I-Discovery/stm32469i_discovery_ts.c
@@ -0,0 +1,461 @@
+/**
+  ******************************************************************************
+  * @file    stm32469i_discovery_ts.c
+  * @author  MCD Application Team
+  * @brief   This file provides a set of functions needed to manage the Touch
+  *          Screen on STM32469I-Discovery board.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* File Info : -----------------------------------------------------------------
+                                   User NOTES
+1. How To use this driver:
+--------------------------
+   - This driver is used to drive the touch screen module of the STM32469I-Discovery
+     board on the K.O.D Optica Technology 480x800 TFT-LCD mounted on
+     MB1189 board. The touch screen driver IC inside the K.O.D module KM-040TMP-02
+   is a FT6206 by Focal Tech.
+
+2. Driver description:
+---------------------
+  + Initialization steps:
+     o Initialize the TS module using the BSP_TS_Init() function. This
+       function includes the MSP layer hardware resources initialization and the
+       communication layer configuration to start the TS use. The LCD size properties
+       (x and y) are passed as parameters.
+     o If TS interrupt mode is desired, you must configure the TS interrupt mode
+       by calling the function BSP_TS_ITConfig(). The TS interrupt mode is generated
+       as an external interrupt whenever a touch is detected.
+       The interrupt mode internally uses the IO functionalities driver driven by
+       the IO expander, to configure the IT line.
+
+  + Touch screen use
+     o The touch screen state is captured whenever the function BSP_TS_GetState() is
+       used. This function returns information about the last LCD touch occurred
+       in the TS_StateTypeDef structure.
+     o If TS interrupt mode is used, the function BSP_TS_ITGetStatus() is needed to get
+       the interrupt status. To clear the IT pending bits, you should call the
+       function BSP_TS_ITClear().
+     o The IT is handled using the corresponding external interrupt IRQ handler,
+       the user IT callback treatment is implemented on the same external interrupt
+       callback.
+
+------------------------------------------------------------------------------*/
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32469i_discovery_ts.h"
+
+/** @addtogroup BSP
+  * @{
+  */
+
+/** @addtogroup STM32469I_Discovery
+  * @{
+  */
+
+/** @defgroup STM32469I-Discovery_TS STM32469I Discovery TS
+  * @{
+  */
+
+/** @defgroup STM32469I-Discovery_TS_Private_Types_Definitions STM32469I Discovery TS Private Types Definitions
+  * @{
+  */
+/**
+  * @}
+  */
+
+/** @defgroup STM32469I-Discovery_TS_Private_Defines STM32469I Discovery TS Private Types Defines
+  * @{
+  */
+/**
+  * @}
+  */
+
+/** @defgroup STM32469I-Discovery_TS_Private_Macros STM32469I Discovery TS Private Macros
+  * @{
+  */
+/**
+  * @}
+  */
+
+/** @defgroup STM32469I-Discovery_TS_Imported_Variables STM32469I Discovery TS Imported Variables
+  * @{
+  */
+  /**
+    * @}
+    */
+
+/** @defgroup STM32469I-Discovery_TS_Private_Variables STM32469I Discovery TS Private Variables
+  * @{
+  */
+static TS_DrvTypeDef *ts_driver;
+static uint8_t  ts_orientation;
+uint8_t  I2C_Address = 0;
+
+/* Table for touchscreen event information display on LCD : table indexed on enum @ref TS_TouchEventTypeDef information */
+char * ts_event_string_tab[TOUCH_EVENT_NB_MAX] = { "None",
+                                                   "Press down",
+                                                   "Lift up",
+                                                   "Contact"
+                                                  };
+
+/* Table for touchscreen gesture Id information display on LCD : table indexed on enum @ref TS_GestureIdTypeDef information */
+char * ts_gesture_id_string_tab[GEST_ID_NB_MAX] = { "None",
+                                                    "Move Up",
+                                                    "Move Right",
+                                                    "Move Down",
+                                                    "Move Left",
+                                                    "Zoom In",
+                                                    "Zoom Out"
+                                                  };
+
+/**
+  * @}
+  */
+
+/** @defgroup STM32469I-Discovery_TS_Private_Function_Prototypes STM32469I Discovery TS Private Function Prototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup STM32469I-Discovery_TS_Public_Functions STM32469I Discovery TS Public Functions
+  * @{
+  */
+
+/**
+  * @brief  Initializes and configures the touch screen functionalities and
+  *         configures all necessary hardware resources (GPIOs, I2C, clocks..).
+  * @param  ts_SizeX : Maximum X size of the TS area on LCD
+  * @param  ts_SizeY : Maximum Y size of the TS area on LCD
+  * @retval TS_OK if all initializations are OK. Other value if error.
+  */
+uint8_t BSP_TS_Init(uint16_t ts_SizeX, uint16_t ts_SizeY)
+{
+  uint8_t ts_status = TS_OK;
+  uint8_t ts_id1, ts_id2 = 0;
+  /* Note : I2C_Address is un-initialized here, but is not used at all in init function */
+  /* but the prototype of Init() is like that in template and should be respected       */
+
+  /* Initialize the communication channel to sensor (I2C) if necessary */
+  /* that is initialization is done only once after a power up         */
+  ft6x06_ts_drv.Init(I2C_Address);
+
+  ts_id1 = ft6x06_ts_drv.ReadID(TS_I2C_ADDRESS);
+  if(ts_id1 != FT6206_ID_VALUE)
+  {
+    ts_id2 = ft6x06_ts_drv.ReadID(TS_I2C_ADDRESS_A02);
+    I2C_Address    = TS_I2C_ADDRESS_A02;    
+  }
+  else
+  {
+    I2C_Address    = TS_I2C_ADDRESS;    
+  }
+  
+  /* Scan FT6xx6 TouchScreen IC controller ID register by I2C Read       */
+  /* Verify this is a FT6206 or FT6336G, otherwise this is an error case */
+  if((ts_id1 == FT6206_ID_VALUE) || (ts_id2 == FT6206_ID_VALUE) || (ts_id2 == FT6X36_ID2_VALUE))
+  {
+    /* Found FT6206 : Initialize the TS driver structure */
+    ts_driver = &ft6x06_ts_drv;
+
+    /* Get LCD chosen orientation */
+    if(ts_SizeX < ts_SizeY)
+    {
+      ts_orientation = TS_SWAP_NONE;                
+    }
+    else
+    {
+      ts_orientation = TS_SWAP_XY | TS_SWAP_Y;                 
+    }
+
+    if(ts_status == TS_OK)
+    {
+      /* Software reset the TouchScreen */
+      ts_driver->Reset(I2C_Address);
+
+      /* Calibrate, Configure and Start the TouchScreen driver */
+      ts_driver->Start(I2C_Address);
+
+    } /* of if(ts_status == TS_OK) */
+  }
+  else
+  {
+    ts_status = TS_DEVICE_NOT_FOUND;
+  }
+
+  return (ts_status);
+}
+
+/**
+  * @brief  Configures and enables the touch screen interrupts both at GPIO level and
+  * in TouchScreen IC driver configuration.
+  * @retval TS_OK if all initializations are OK.
+  */
+uint8_t BSP_TS_ITConfig(void)
+{
+  uint8_t ts_status = TS_OK;
+  GPIO_InitTypeDef gpio_init_structure;
+
+  /* Msp Init of GPIO used for TS_INT pin coming from TouchScreen driver IC FT6x06 */
+  /* When touchscreen is operated in interrupt mode */
+  BSP_TS_INT_MspInit();
+
+  /* Configure Interrupt mode for TS_INT pin falling edge : when a new touch is available */
+  /* TS_INT pin is active on low level on new touch available */
+  gpio_init_structure.Pin = TS_INT_PIN;
+  gpio_init_structure.Pull = GPIO_PULLUP;
+  gpio_init_structure.Speed = GPIO_SPEED_FAST;
+  gpio_init_structure.Mode = GPIO_MODE_IT_FALLING;
+  HAL_GPIO_Init(TS_INT_GPIO_PORT, &gpio_init_structure);
+
+  /* Enable and set the TS_INT EXTI Interrupt to an intermediate priority */
+  HAL_NVIC_SetPriority((IRQn_Type)(TS_INT_EXTI_IRQn), 0x05, 0x00);
+  HAL_NVIC_EnableIRQ((IRQn_Type)(TS_INT_EXTI_IRQn));
+
+  /* Enable the TS in interrupt mode */
+  /* In that case the INT output of FT6206 when new touch is available */
+  /* is active on low level and directed on EXTI */
+  ts_driver->EnableIT(I2C_Address);
+
+  return (ts_status);
+}
+
+/**
+  * @brief  Returns status and positions of the touch screen.
+  * @param  TS_State: Pointer to touch screen current state structure
+  * @retval TS_OK if all initializations are OK. Other value if error.
+  */
+uint8_t BSP_TS_GetState(TS_StateTypeDef *TS_State)
+{
+  static uint32_t _x[TS_MAX_NB_TOUCH] = {0, 0};
+  static uint32_t _y[TS_MAX_NB_TOUCH] = {0, 0};
+  uint8_t ts_status = TS_OK;
+  uint16_t tmp;
+  uint16_t Raw_x[TS_MAX_NB_TOUCH];
+  uint16_t Raw_y[TS_MAX_NB_TOUCH];
+  uint16_t xDiff;
+  uint16_t yDiff;
+  uint32_t index;
+#if (TS_MULTI_TOUCH_SUPPORTED == 1)
+  uint32_t weight = 0;
+  uint32_t area = 0;
+  uint32_t event = 0;
+#endif /* TS_MULTI_TOUCH_SUPPORTED == 1 */
+
+  /* Check and update the number of touches active detected */
+  TS_State->touchDetected = ts_driver->DetectTouch(I2C_Address);
+  if(TS_State->touchDetected)
+  {
+    for(index=0; index < TS_State->touchDetected; index++)
+    {
+      /* Get each touch coordinates */
+      ts_driver->GetXY(I2C_Address, &(Raw_x[index]), &(Raw_y[index]));
+
+      if(ts_orientation & TS_SWAP_XY)
+      {
+        tmp = Raw_x[index];
+        Raw_x[index] = Raw_y[index]; 
+        Raw_y[index] = tmp;
+      }
+      
+      if(ts_orientation & TS_SWAP_X)
+      {
+        Raw_x[index] = FT_6206_MAX_WIDTH - 1 - Raw_x[index];
+      }
+
+      if(ts_orientation & TS_SWAP_Y)
+      {
+        Raw_y[index] = FT_6206_MAX_HEIGHT - 1 - Raw_y[index];
+      }
+            
+      xDiff = Raw_x[index] > _x[index]? (Raw_x[index] - _x[index]): (_x[index] - Raw_x[index]);
+      yDiff = Raw_y[index] > _y[index]? (Raw_y[index] - _y[index]): (_y[index] - Raw_y[index]);
+
+      if ((xDiff + yDiff) > 5)
+      {
+        _x[index] = Raw_x[index];
+        _y[index] = Raw_y[index];
+      }
+
+
+      TS_State->touchX[index] = _x[index];
+      TS_State->touchY[index] = _y[index];
+
+#if (TS_MULTI_TOUCH_SUPPORTED == 1)
+
+      /* Get touch info related to the current touch */
+      ft6x06_TS_GetTouchInfo(I2C_Address, index, &weight, &area, &event);
+
+      /* Update TS_State structure */
+      TS_State->touchWeight[index] = weight;
+      TS_State->touchArea[index]   = area;
+
+      /* Remap touch event */
+      switch(event)
+      {
+        case FT6206_TOUCH_EVT_FLAG_PRESS_DOWN  :
+          TS_State->touchEventId[index] = TOUCH_EVENT_PRESS_DOWN;
+          break;
+        case FT6206_TOUCH_EVT_FLAG_LIFT_UP :
+          TS_State->touchEventId[index] = TOUCH_EVENT_LIFT_UP;
+          break;
+        case FT6206_TOUCH_EVT_FLAG_CONTACT :
+          TS_State->touchEventId[index] = TOUCH_EVENT_CONTACT;
+          break;
+        case FT6206_TOUCH_EVT_FLAG_NO_EVENT :
+          TS_State->touchEventId[index] = TOUCH_EVENT_NO_EVT;
+          break;
+        default :
+          ts_status = TS_ERROR;
+          break;
+      } /* of switch(event) */
+
+#endif /* TS_MULTI_TOUCH_SUPPORTED == 1 */
+
+    } /* of for(index=0; index < TS_State->touchDetected; index++) */
+
+#if (TS_MULTI_TOUCH_SUPPORTED == 1)
+    /* Get gesture Id */
+    ts_status = BSP_TS_Get_GestureId(TS_State);
+#endif /* TS_MULTI_TOUCH_SUPPORTED == 1 */
+
+  } /* end of if(TS_State->touchDetected != 0) */
+
+  return (ts_status);
+}
+
+#if (TS_MULTI_TOUCH_SUPPORTED == 1)
+/**
+  * @brief  Update gesture Id following a touch detected.
+  * @param  TS_State: Pointer to touch screen current state structure
+  * @retval TS_OK if all initializations are OK. Other value if error.
+  */
+uint8_t BSP_TS_Get_GestureId(TS_StateTypeDef *TS_State)
+{
+  uint32_t gestureId = 0;
+  uint8_t  ts_status = TS_OK;
+
+  /* Get gesture Id */
+  ft6x06_TS_GetGestureID(I2C_Address, &gestureId);
+
+  /* Remap gesture Id to a TS_GestureIdTypeDef value */
+  switch(gestureId)
+  {
+    case FT6206_GEST_ID_NO_GESTURE :
+      TS_State->gestureId = GEST_ID_NO_GESTURE;
+      break;
+    case FT6206_GEST_ID_MOVE_UP :
+      TS_State->gestureId = GEST_ID_MOVE_UP;
+      break;
+    case FT6206_GEST_ID_MOVE_RIGHT :
+      TS_State->gestureId = GEST_ID_MOVE_RIGHT;
+      break;
+    case FT6206_GEST_ID_MOVE_DOWN :
+      TS_State->gestureId = GEST_ID_MOVE_DOWN;
+      break;
+    case FT6206_GEST_ID_MOVE_LEFT :
+      TS_State->gestureId = GEST_ID_MOVE_LEFT;
+      break;
+    case FT6206_GEST_ID_ZOOM_IN :
+      TS_State->gestureId = GEST_ID_ZOOM_IN;
+      break;
+    case FT6206_GEST_ID_ZOOM_OUT :
+      TS_State->gestureId = GEST_ID_ZOOM_OUT;
+      break;
+    default :
+      ts_status = TS_ERROR;
+      break;
+  } /* of switch(gestureId) */
+
+  return(ts_status);
+}
+
+
+/** @defgroup STM32469I-Discovery_TS_Private_Functions STM32469I Discovery TS Private Functions
+  * @{
+  */
+
+
+/**
+  * @brief  Function used to reset all touch data before a new acquisition
+  *         of touch information.
+  * @param  TS_State: Pointer to touch screen current state structure
+  * @retval TS_OK if OK, TE_ERROR if problem found.
+  */
+uint8_t BSP_TS_ResetTouchData(TS_StateTypeDef *TS_State)
+{
+  uint8_t ts_status = TS_ERROR;
+  uint32_t index;
+
+  if (TS_State != (TS_StateTypeDef *)NULL)
+  {
+    TS_State->gestureId = GEST_ID_NO_GESTURE;
+    TS_State->touchDetected = 0;
+
+    for(index = 0; index < TS_MAX_NB_TOUCH; index++)
+    {
+      TS_State->touchX[index]       = 0;
+      TS_State->touchY[index]       = 0;
+      TS_State->touchArea[index]    = 0;
+      TS_State->touchEventId[index] = TOUCH_EVENT_NO_EVT;
+      TS_State->touchWeight[index]  = 0;
+    }
+
+    ts_status = TS_OK;
+
+  } /* of if (TS_State != (TS_StateTypeDef *)NULL) */
+
+  return (ts_status);
+}
+#endif /* TS_MULTI_TOUCH_SUPPORTED == 1 */
+/**
+  * @brief  Initializes the TS_INT pin MSP.
+  */
+__weak void BSP_TS_INT_MspInit(void)
+{
+  GPIO_InitTypeDef  gpio_init_structure;
+
+  TS_INT_GPIO_CLK_ENABLE();
+
+  /* GPIO configuration in input for TouchScreen interrupt signal on TS_INT pin */
+  gpio_init_structure.Pin       = TS_INT_PIN;
+
+  gpio_init_structure.Mode      = GPIO_MODE_INPUT;
+  gpio_init_structure.Pull      = GPIO_PULLUP;
+  gpio_init_structure.Speed     = GPIO_SPEED_HIGH;
+  HAL_GPIO_Init(TS_INT_GPIO_PORT, &gpio_init_structure);
+}
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
diff --git a/Drivers/BSP/STM32469I-Discovery/stm32469i_discovery_ts.h b/Drivers/BSP/STM32469I-Discovery/stm32469i_discovery_ts.h
new file mode 100644
index 0000000..f9c80ff
--- /dev/null
+++ b/Drivers/BSP/STM32469I-Discovery/stm32469i_discovery_ts.h
@@ -0,0 +1,192 @@
+/**
+  ******************************************************************************
+  * @file    stm32469i_discovery_ts.h
+  * @author  MCD Application Team
+  * @brief   This file contains the common defines and functions prototypes for
+  *          the stm32469i_discovery_ts.c driver.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32469I_DISCOVERY_TS_H
+#define __STM32469I_DISCOVERY_TS_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32469i_discovery.h"
+#include "stm32469i_discovery_lcd.h"
+
+/* Include TouchScreen component driver */
+#include "../Components/ft6x06/ft6x06.h"
+
+/** @addtogroup BSP
+  * @{
+  */
+
+/** @addtogroup STM32469I_Discovery
+  * @{
+  */
+
+/** @addtogroup STM32469I-Discovery_TS 
+  * @{
+  */
+
+ /** @defgroup STM32469I-Discovery_TS_Exported_Constants STM32469I Discovery TS Exported Constants
+   * @{
+   */
+/** @brief With FT6206 : maximum 2 touches detected simultaneously
+  */
+#define TS_MAX_NB_TOUCH                 ((uint32_t) FT6206_MAX_DETECTABLE_TOUCH)
+#define TS_NO_IRQ_PENDING               ((uint8_t) 0)
+#define TS_IRQ_PENDING                  ((uint8_t) 1)
+
+#define TS_SWAP_NONE                    ((uint8_t) 0x01)
+#define TS_SWAP_X                       ((uint8_t) 0x02)
+#define TS_SWAP_Y                       ((uint8_t) 0x04)
+#define TS_SWAP_XY                      ((uint8_t) 0x08)
+
+ /**
+   * @}
+   */
+
+/** @defgroup STM32469I-Discovery_TS_Exported_Types  STM32469I Discovery TS Exported Types
+  * @{
+  */
+/**
+*  @brief TS_StateTypeDef
+*  Define TS State structure
+*/
+typedef struct
+{
+  uint8_t  touchDetected;                /*!< Total number of active touches detected at last scan */
+  uint16_t touchX[TS_MAX_NB_TOUCH];      /*!< Touch X[0], X[1] coordinates on 12 bits */
+  uint16_t touchY[TS_MAX_NB_TOUCH];      /*!< Touch Y[0], Y[1] coordinates on 12 bits */
+
+#if (TS_MULTI_TOUCH_SUPPORTED == 1)
+  uint8_t  touchWeight[TS_MAX_NB_TOUCH]; /*!< Touch_Weight[0], Touch_Weight[1] : weight property of touches */
+  uint8_t  touchEventId[TS_MAX_NB_TOUCH];     /*!< Touch_EventId[0], Touch_EventId[1] : take value of type @ref TS_TouchEventTypeDef */
+  uint8_t  touchArea[TS_MAX_NB_TOUCH];   /*!< Touch_Area[0], Touch_Area[1] : touch area of each touch */
+  uint32_t gestureId; /*!< type of gesture detected : take value of type @ref TS_GestureIdTypeDef */
+#endif  /* TS_MULTI_TOUCH_SUPPORTED == 1 */
+
+} TS_StateTypeDef;
+
+/**
+ *  @brief TS_StatusTypeDef
+ *  Define BSP_TS_xxx() functions possible return value,
+ *  when status is returned by those functions.
+ */
+typedef enum
+{
+  TS_OK                = 0x00, /*!< Touch Ok */
+  TS_ERROR             = 0x01, /*!< Touch Error */
+  TS_TIMEOUT           = 0x02, /*!< Touch Timeout */
+  TS_DEVICE_NOT_FOUND  = 0x03  /*!< Touchscreen device not found */
+} TS_StatusTypeDef;
+
+/**
+ *  @brief TS_GestureIdTypeDef
+ *  Define Possible managed gesture identification values returned by touch screen
+ *  driver.
+ */
+typedef enum
+{
+  GEST_ID_NO_GESTURE = 0x00, /*!< Gesture not defined / recognized */
+  GEST_ID_MOVE_UP    = 0x01, /*!< Gesture Move Up */
+  GEST_ID_MOVE_RIGHT = 0x02, /*!< Gesture Move Right */
+  GEST_ID_MOVE_DOWN  = 0x03, /*!< Gesture Move Down */
+  GEST_ID_MOVE_LEFT  = 0x04, /*!< Gesture Move Left */
+  GEST_ID_ZOOM_IN    = 0x05, /*!< Gesture Zoom In */
+  GEST_ID_ZOOM_OUT   = 0x06, /*!< Gesture Zoom Out */
+  GEST_ID_NB_MAX     = 0x07 /*!< max number of gesture id */
+} TS_GestureIdTypeDef;
+
+/**
+ *  @brief TS_TouchEventTypeDef
+ *  Define Possible touch events kind as returned values
+ *  by touch screen IC Driver.
+ */
+typedef enum
+{
+  TOUCH_EVENT_NO_EVT        = 0x00, /*!< Touch Event : undetermined */
+  TOUCH_EVENT_PRESS_DOWN    = 0x01, /*!< Touch Event Press Down */
+  TOUCH_EVENT_LIFT_UP       = 0x02, /*!< Touch Event Lift Up */
+  TOUCH_EVENT_CONTACT       = 0x03, /*!< Touch Event Contact */
+  TOUCH_EVENT_NB_MAX        = 0x04  /*!< max number of touch events kind */
+} TS_TouchEventTypeDef;
+
+/**
+  * @}
+  */
+
+/** @defgroup STM32469I-Discovery_TS_Imported_Variables STM32469I Discovery TS Imported Variables
+  * @{
+  */
+/**
+ *  @brief Table for touchscreen event information display on LCD :
+ *  table indexed on enum @ref TS_TouchEventTypeDef information
+ */
+extern char * ts_event_string_tab[TOUCH_EVENT_NB_MAX];
+
+/**
+ *  @brief Table for touchscreen gesture Id information display on LCD : table indexed
+ *  on enum @ref TS_GestureIdTypeDef information
+ */
+extern char * ts_gesture_id_string_tab[GEST_ID_NB_MAX];
+/**
+  * @}
+  */
+
+/** @defgroup STM32469I-Discovery_TS_Exported_Functions STM32469I Discovery TS Exported Functions
+  * @{
+  */
+uint8_t BSP_TS_Init(uint16_t ts_SizeX, uint16_t ts_SizeY);
+uint8_t BSP_TS_GetState(TS_StateTypeDef *TS_State);
+
+#if (TS_MULTI_TOUCH_SUPPORTED == 1)
+uint8_t BSP_TS_Get_GestureId(TS_StateTypeDef *TS_State);
+uint8_t BSP_TS_ResetTouchData(TS_StateTypeDef *TS_State);
+#endif /* TS_MULTI_TOUCH_SUPPORTED == 1 */
+
+uint8_t BSP_TS_ITConfig(void);
+
+
+/* These __weak function can be surcharged by application code in case the current settings
+   need to be changed for specific (example GPIO allocation) */
+void BSP_TS_INT_MspInit(void);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32469I_DISCOVERY_TS_H */
diff --git a/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f469xx.h b/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f469xx.h
new file mode 100644
index 0000000..0a812b4
--- /dev/null
+++ b/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f469xx.h
@@ -0,0 +1,20278 @@
+/**
+  ******************************************************************************
+  * @file    stm32f469xx.h
+  * @author  MCD Application Team
+  * @brief   CMSIS STM32F469xx Device Peripheral Access Layer Header File.
+  *
+  *          This file contains:
+  *           - Data structures and the address mapping for all peripherals
+  *           - peripherals registers declarations and bits definition
+  *           - Macros to access peripheral’s registers hardware
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS_Device
+  * @{
+  */
+
+/** @addtogroup stm32f469xx
+  * @{
+  */
+    
+#ifndef __STM32F469xx_H
+#define __STM32F469xx_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif /* __cplusplus */
+
+/** @addtogroup Configuration_section_for_CMSIS
+  * @{
+  */
+
+/**
+  * @brief Configuration of the Cortex-M4 Processor and Core Peripherals 
+  */
+#define __CM4_REV                 0x0001U  /*!< Core revision r0p1                            */
+#define __MPU_PRESENT             1U       /*!< STM32F4XX provides an MPU                     */
+#define __NVIC_PRIO_BITS          4U       /*!< STM32F4XX uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig    0U       /*!< Set to 1 if different SysTick Config is used  */
+#define __FPU_PRESENT             1U       /*!< FPU present                                   */
+
+/**
+  * @}
+  */
+  
+/** @addtogroup Peripheral_interrupt_number_definition
+  * @{
+  */
+
+/**
+ * @brief STM32F4XX Interrupt Number Definition, according to the selected device 
+ *        in @ref Library_configuration_section 
+ */
+typedef enum
+{
+/******  Cortex-M4 Processor Exceptions Numbers ****************************************************************/
+  NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                                          */
+  MemoryManagement_IRQn       = -12,    /*!< 4 Cortex-M4 Memory Management Interrupt                           */
+  BusFault_IRQn               = -11,    /*!< 5 Cortex-M4 Bus Fault Interrupt                                   */
+  UsageFault_IRQn             = -10,    /*!< 6 Cortex-M4 Usage Fault Interrupt                                 */
+  SVCall_IRQn                 = -5,     /*!< 11 Cortex-M4 SV Call Interrupt                                    */
+  DebugMonitor_IRQn           = -4,     /*!< 12 Cortex-M4 Debug Monitor Interrupt                              */
+  PendSV_IRQn                 = -2,     /*!< 14 Cortex-M4 Pend SV Interrupt                                    */
+  SysTick_IRQn                = -1,     /*!< 15 Cortex-M4 System Tick Interrupt                                */
+/******  STM32 specific Interrupt Numbers **********************************************************************/
+  WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt                                         */
+  PVD_IRQn                    = 1,      /*!< PVD through EXTI Line detection Interrupt                         */
+  TAMP_STAMP_IRQn             = 2,      /*!< Tamper and TimeStamp interrupts through the EXTI line             */
+  RTC_WKUP_IRQn               = 3,      /*!< RTC Wakeup interrupt through the EXTI line                        */
+  FLASH_IRQn                  = 4,      /*!< FLASH global Interrupt                                            */
+  RCC_IRQn                    = 5,      /*!< RCC global Interrupt                                              */
+  EXTI0_IRQn                  = 6,      /*!< EXTI Line0 Interrupt                                              */
+  EXTI1_IRQn                  = 7,      /*!< EXTI Line1 Interrupt                                              */
+  EXTI2_IRQn                  = 8,      /*!< EXTI Line2 Interrupt                                              */
+  EXTI3_IRQn                  = 9,      /*!< EXTI Line3 Interrupt                                              */
+  EXTI4_IRQn                  = 10,     /*!< EXTI Line4 Interrupt                                              */
+  DMA1_Stream0_IRQn           = 11,     /*!< DMA1 Stream 0 global Interrupt                                    */
+  DMA1_Stream1_IRQn           = 12,     /*!< DMA1 Stream 1 global Interrupt                                    */
+  DMA1_Stream2_IRQn           = 13,     /*!< DMA1 Stream 2 global Interrupt                                    */
+  DMA1_Stream3_IRQn           = 14,     /*!< DMA1 Stream 3 global Interrupt                                    */
+  DMA1_Stream4_IRQn           = 15,     /*!< DMA1 Stream 4 global Interrupt                                    */
+  DMA1_Stream5_IRQn           = 16,     /*!< DMA1 Stream 5 global Interrupt                                    */
+  DMA1_Stream6_IRQn           = 17,     /*!< DMA1 Stream 6 global Interrupt                                    */
+  ADC_IRQn                    = 18,     /*!< ADC1, ADC2 and ADC3 global Interrupts                             */
+  CAN1_TX_IRQn                = 19,     /*!< CAN1 TX Interrupt                                                 */
+  CAN1_RX0_IRQn               = 20,     /*!< CAN1 RX0 Interrupt                                                */
+  CAN1_RX1_IRQn               = 21,     /*!< CAN1 RX1 Interrupt                                                */
+  CAN1_SCE_IRQn               = 22,     /*!< CAN1 SCE Interrupt                                                */
+  EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                                     */
+  TIM1_BRK_TIM9_IRQn          = 24,     /*!< TIM1 Break interrupt and TIM9 global interrupt                    */
+  TIM1_UP_TIM10_IRQn          = 25,     /*!< TIM1 Update Interrupt and TIM10 global interrupt                  */
+  TIM1_TRG_COM_TIM11_IRQn     = 26,     /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
+  TIM1_CC_IRQn                = 27,     /*!< TIM1 Capture Compare Interrupt                                    */
+  TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                             */
+  TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                             */
+  TIM4_IRQn                   = 30,     /*!< TIM4 global Interrupt                                             */
+  I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                              */
+  I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                              */
+  I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                              */
+  I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                              */
+  SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                             */
+  SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                             */
+  USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                                           */
+  USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                                           */
+  USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                                           */
+  EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                                   */
+  RTC_Alarm_IRQn              = 41,     /*!< RTC Alarm (A and B) through EXTI Line Interrupt                   */
+  OTG_FS_WKUP_IRQn            = 42,     /*!< USB OTG FS Wakeup through EXTI line interrupt                     */
+  TIM8_BRK_TIM12_IRQn         = 43,     /*!< TIM8 Break Interrupt and TIM12 global interrupt                   */
+  TIM8_UP_TIM13_IRQn          = 44,     /*!< TIM8 Update Interrupt and TIM13 global interrupt                  */
+  TIM8_TRG_COM_TIM14_IRQn     = 45,     /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
+  TIM8_CC_IRQn                = 46,     /*!< TIM8 Capture Compare global interrupt                             */
+  DMA1_Stream7_IRQn           = 47,     /*!< DMA1 Stream7 Interrupt                                            */
+  FMC_IRQn                    = 48,     /*!< FMC global Interrupt                                              */
+  SDIO_IRQn                   = 49,     /*!< SDIO global Interrupt                                             */
+  TIM5_IRQn                   = 50,     /*!< TIM5 global Interrupt                                             */
+  SPI3_IRQn                   = 51,     /*!< SPI3 global Interrupt                                             */
+  UART4_IRQn                  = 52,     /*!< UART4 global Interrupt                                            */
+  UART5_IRQn                  = 53,     /*!< UART5 global Interrupt                                            */
+  TIM6_DAC_IRQn               = 54,     /*!< TIM6 global and DAC1&2 underrun error  interrupts                 */
+  TIM7_IRQn                   = 55,     /*!< TIM7 global interrupt                                             */
+  DMA2_Stream0_IRQn           = 56,     /*!< DMA2 Stream 0 global Interrupt                                    */
+  DMA2_Stream1_IRQn           = 57,     /*!< DMA2 Stream 1 global Interrupt                                    */
+  DMA2_Stream2_IRQn           = 58,     /*!< DMA2 Stream 2 global Interrupt                                    */
+  DMA2_Stream3_IRQn           = 59,     /*!< DMA2 Stream 3 global Interrupt                                    */
+  DMA2_Stream4_IRQn           = 60,     /*!< DMA2 Stream 4 global Interrupt                                    */
+  ETH_IRQn                    = 61,     /*!< Ethernet global Interrupt                                         */
+  ETH_WKUP_IRQn               = 62,     /*!< Ethernet Wakeup through EXTI line Interrupt                       */
+  CAN2_TX_IRQn                = 63,     /*!< CAN2 TX Interrupt                                                 */
+  CAN2_RX0_IRQn               = 64,     /*!< CAN2 RX0 Interrupt                                                */
+  CAN2_RX1_IRQn               = 65,     /*!< CAN2 RX1 Interrupt                                                */
+  CAN2_SCE_IRQn               = 66,     /*!< CAN2 SCE Interrupt                                                */
+  OTG_FS_IRQn                 = 67,     /*!< USB OTG FS global Interrupt                                       */
+  DMA2_Stream5_IRQn           = 68,     /*!< DMA2 Stream 5 global interrupt                                    */
+  DMA2_Stream6_IRQn           = 69,     /*!< DMA2 Stream 6 global interrupt                                    */
+  DMA2_Stream7_IRQn           = 70,     /*!< DMA2 Stream 7 global interrupt                                    */
+  USART6_IRQn                 = 71,     /*!< USART6 global interrupt                                           */
+  I2C3_EV_IRQn                = 72,     /*!< I2C3 event interrupt                                              */
+  I2C3_ER_IRQn                = 73,     /*!< I2C3 error interrupt                                              */
+  OTG_HS_EP1_OUT_IRQn         = 74,     /*!< USB OTG HS End Point 1 Out global interrupt                       */
+  OTG_HS_EP1_IN_IRQn          = 75,     /*!< USB OTG HS End Point 1 In global interrupt                        */
+  OTG_HS_WKUP_IRQn            = 76,     /*!< USB OTG HS Wakeup through EXTI interrupt                          */
+  OTG_HS_IRQn                 = 77,     /*!< USB OTG HS global interrupt                                       */
+  DCMI_IRQn                   = 78,     /*!< DCMI global interrupt                                             */
+  HASH_RNG_IRQn               = 80,     /*!< Hash and Rng global interrupt                                     */
+  FPU_IRQn                    = 81,     /*!< FPU global interrupt                                              */
+  UART7_IRQn                  = 82,     /*!< UART7 global interrupt                                            */
+  UART8_IRQn                  = 83,     /*!< UART8 global interrupt                                            */
+  SPI4_IRQn                   = 84,     /*!< SPI4 global Interrupt                                             */
+  SPI5_IRQn                   = 85,     /*!< SPI5 global Interrupt                                             */
+  SPI6_IRQn                   = 86,     /*!< SPI6 global Interrupt                                             */
+  SAI1_IRQn                   = 87,     /*!< SAI1 global Interrupt                                             */
+  LTDC_IRQn                   = 88,     /*!< LTDC global Interrupt                                              */
+  LTDC_ER_IRQn                = 89,     /*!< LTDC Error global Interrupt                                        */
+  DMA2D_IRQn                  = 90,     /*!< DMA2D global Interrupt                                            */
+  QUADSPI_IRQn                = 91,     /*!< QUADSPI global Interrupt                                          */
+  DSI_IRQn                    = 92      /*!< DSI global Interrupt                                              */
+} IRQn_Type;
+
+/**
+  * @}
+  */
+
+#include "core_cm4.h"             /* Cortex-M4 processor and core peripherals */
+#include "system_stm32f4xx.h"
+#include <stdint.h>
+
+/** @addtogroup Peripheral_registers_structures
+  * @{
+  */   
+
+/** 
+  * @brief Analog to Digital Converter  
+  */
+
+typedef struct
+{
+  __IO uint32_t SR;     /*!< ADC status register,                         Address offset: 0x00 */
+  __IO uint32_t CR1;    /*!< ADC control register 1,                      Address offset: 0x04 */
+  __IO uint32_t CR2;    /*!< ADC control register 2,                      Address offset: 0x08 */
+  __IO uint32_t SMPR1;  /*!< ADC sample time register 1,                  Address offset: 0x0C */
+  __IO uint32_t SMPR2;  /*!< ADC sample time register 2,                  Address offset: 0x10 */
+  __IO uint32_t JOFR1;  /*!< ADC injected channel data offset register 1, Address offset: 0x14 */
+  __IO uint32_t JOFR2;  /*!< ADC injected channel data offset register 2, Address offset: 0x18 */
+  __IO uint32_t JOFR3;  /*!< ADC injected channel data offset register 3, Address offset: 0x1C */
+  __IO uint32_t JOFR4;  /*!< ADC injected channel data offset register 4, Address offset: 0x20 */
+  __IO uint32_t HTR;    /*!< ADC watchdog higher threshold register,      Address offset: 0x24 */
+  __IO uint32_t LTR;    /*!< ADC watchdog lower threshold register,       Address offset: 0x28 */
+  __IO uint32_t SQR1;   /*!< ADC regular sequence register 1,             Address offset: 0x2C */
+  __IO uint32_t SQR2;   /*!< ADC regular sequence register 2,             Address offset: 0x30 */
+  __IO uint32_t SQR3;   /*!< ADC regular sequence register 3,             Address offset: 0x34 */
+  __IO uint32_t JSQR;   /*!< ADC injected sequence register,              Address offset: 0x38*/
+  __IO uint32_t JDR1;   /*!< ADC injected data register 1,                Address offset: 0x3C */
+  __IO uint32_t JDR2;   /*!< ADC injected data register 2,                Address offset: 0x40 */
+  __IO uint32_t JDR3;   /*!< ADC injected data register 3,                Address offset: 0x44 */
+  __IO uint32_t JDR4;   /*!< ADC injected data register 4,                Address offset: 0x48 */
+  __IO uint32_t DR;     /*!< ADC regular data register,                   Address offset: 0x4C */
+} ADC_TypeDef;
+
+typedef struct
+{
+  __IO uint32_t CSR;    /*!< ADC Common status register,                  Address offset: ADC1 base address + 0x300 */
+  __IO uint32_t CCR;    /*!< ADC common control register,                 Address offset: ADC1 base address + 0x304 */
+  __IO uint32_t CDR;    /*!< ADC common regular data register for dual
+                             AND triple modes,                            Address offset: ADC1 base address + 0x308 */
+} ADC_Common_TypeDef;
+
+
+/** 
+  * @brief Controller Area Network TxMailBox 
+  */
+
+typedef struct
+{
+  __IO uint32_t TIR;  /*!< CAN TX mailbox identifier register */
+  __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
+  __IO uint32_t TDLR; /*!< CAN mailbox data low register */
+  __IO uint32_t TDHR; /*!< CAN mailbox data high register */
+} CAN_TxMailBox_TypeDef;
+
+/** 
+  * @brief Controller Area Network FIFOMailBox 
+  */
+  
+typedef struct
+{
+  __IO uint32_t RIR;  /*!< CAN receive FIFO mailbox identifier register */
+  __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
+  __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
+  __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
+} CAN_FIFOMailBox_TypeDef;
+
+/** 
+  * @brief Controller Area Network FilterRegister 
+  */
+  
+typedef struct
+{
+  __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
+  __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
+} CAN_FilterRegister_TypeDef;
+
+/** 
+  * @brief Controller Area Network 
+  */
+  
+typedef struct
+{
+  __IO uint32_t              MCR;                 /*!< CAN master control register,         Address offset: 0x00          */
+  __IO uint32_t              MSR;                 /*!< CAN master status register,          Address offset: 0x04          */
+  __IO uint32_t              TSR;                 /*!< CAN transmit status register,        Address offset: 0x08          */
+  __IO uint32_t              RF0R;                /*!< CAN receive FIFO 0 register,         Address offset: 0x0C          */
+  __IO uint32_t              RF1R;                /*!< CAN receive FIFO 1 register,         Address offset: 0x10          */
+  __IO uint32_t              IER;                 /*!< CAN interrupt enable register,       Address offset: 0x14          */
+  __IO uint32_t              ESR;                 /*!< CAN error status register,           Address offset: 0x18          */
+  __IO uint32_t              BTR;                 /*!< CAN bit timing register,             Address offset: 0x1C          */
+  uint32_t                   RESERVED0[88];       /*!< Reserved, 0x020 - 0x17F                                            */
+  CAN_TxMailBox_TypeDef      sTxMailBox[3];       /*!< CAN Tx MailBox,                      Address offset: 0x180 - 0x1AC */
+  CAN_FIFOMailBox_TypeDef    sFIFOMailBox[2];     /*!< CAN FIFO MailBox,                    Address offset: 0x1B0 - 0x1CC */
+  uint32_t                   RESERVED1[12];       /*!< Reserved, 0x1D0 - 0x1FF                                            */
+  __IO uint32_t              FMR;                 /*!< CAN filter master register,          Address offset: 0x200         */
+  __IO uint32_t              FM1R;                /*!< CAN filter mode register,            Address offset: 0x204         */
+  uint32_t                   RESERVED2;           /*!< Reserved, 0x208                                                    */
+  __IO uint32_t              FS1R;                /*!< CAN filter scale register,           Address offset: 0x20C         */
+  uint32_t                   RESERVED3;           /*!< Reserved, 0x210                                                    */
+  __IO uint32_t              FFA1R;               /*!< CAN filter FIFO assignment register, Address offset: 0x214         */
+  uint32_t                   RESERVED4;           /*!< Reserved, 0x218                                                    */
+  __IO uint32_t              FA1R;                /*!< CAN filter activation register,      Address offset: 0x21C         */
+  uint32_t                   RESERVED5[8];        /*!< Reserved, 0x220-0x23F                                              */ 
+  CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register,                 Address offset: 0x240-0x31C   */
+} CAN_TypeDef;
+
+/** 
+  * @brief CRC calculation unit 
+  */
+
+typedef struct
+{
+  __IO uint32_t DR;         /*!< CRC Data register,             Address offset: 0x00 */
+  __IO uint8_t  IDR;        /*!< CRC Independent data register, Address offset: 0x04 */
+  uint8_t       RESERVED0;  /*!< Reserved, 0x05                                      */
+  uint16_t      RESERVED1;  /*!< Reserved, 0x06                                      */
+  __IO uint32_t CR;         /*!< CRC Control register,          Address offset: 0x08 */
+} CRC_TypeDef;
+
+/** 
+  * @brief Digital to Analog Converter
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;       /*!< DAC control register,                                    Address offset: 0x00 */
+  __IO uint32_t SWTRIGR;  /*!< DAC software trigger register,                           Address offset: 0x04 */
+  __IO uint32_t DHR12R1;  /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
+  __IO uint32_t DHR12L1;  /*!< DAC channel1 12-bit left aligned data holding register,  Address offset: 0x0C */
+  __IO uint32_t DHR8R1;   /*!< DAC channel1 8-bit right aligned data holding register,  Address offset: 0x10 */
+  __IO uint32_t DHR12R2;  /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
+  __IO uint32_t DHR12L2;  /*!< DAC channel2 12-bit left aligned data holding register,  Address offset: 0x18 */
+  __IO uint32_t DHR8R2;   /*!< DAC channel2 8-bit right-aligned data holding register,  Address offset: 0x1C */
+  __IO uint32_t DHR12RD;  /*!< Dual DAC 12-bit right-aligned data holding register,     Address offset: 0x20 */
+  __IO uint32_t DHR12LD;  /*!< DUAL DAC 12-bit left aligned data holding register,      Address offset: 0x24 */
+  __IO uint32_t DHR8RD;   /*!< DUAL DAC 8-bit right aligned data holding register,      Address offset: 0x28 */
+  __IO uint32_t DOR1;     /*!< DAC channel1 data output register,                       Address offset: 0x2C */
+  __IO uint32_t DOR2;     /*!< DAC channel2 data output register,                       Address offset: 0x30 */
+  __IO uint32_t SR;       /*!< DAC status register,                                     Address offset: 0x34 */
+} DAC_TypeDef;
+
+/** 
+  * @brief Debug MCU
+  */
+
+typedef struct
+{
+  __IO uint32_t IDCODE;  /*!< MCU device ID code,               Address offset: 0x00 */
+  __IO uint32_t CR;      /*!< Debug MCU configuration register, Address offset: 0x04 */
+  __IO uint32_t APB1FZ;  /*!< Debug MCU APB1 freeze register,   Address offset: 0x08 */
+  __IO uint32_t APB2FZ;  /*!< Debug MCU APB2 freeze register,   Address offset: 0x0C */
+}DBGMCU_TypeDef;
+
+/** 
+  * @brief DCMI
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;       /*!< DCMI control register 1,                       Address offset: 0x00 */
+  __IO uint32_t SR;       /*!< DCMI status register,                          Address offset: 0x04 */
+  __IO uint32_t RISR;     /*!< DCMI raw interrupt status register,            Address offset: 0x08 */
+  __IO uint32_t IER;      /*!< DCMI interrupt enable register,                Address offset: 0x0C */
+  __IO uint32_t MISR;     /*!< DCMI masked interrupt status register,         Address offset: 0x10 */
+  __IO uint32_t ICR;      /*!< DCMI interrupt clear register,                 Address offset: 0x14 */
+  __IO uint32_t ESCR;     /*!< DCMI embedded synchronization code register,   Address offset: 0x18 */
+  __IO uint32_t ESUR;     /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */
+  __IO uint32_t CWSTRTR;  /*!< DCMI crop window start,                        Address offset: 0x20 */
+  __IO uint32_t CWSIZER;  /*!< DCMI crop window size,                         Address offset: 0x24 */
+  __IO uint32_t DR;       /*!< DCMI data register,                            Address offset: 0x28 */
+} DCMI_TypeDef;
+
+/** 
+  * @brief DMA Controller
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;     /*!< DMA stream x configuration register      */
+  __IO uint32_t NDTR;   /*!< DMA stream x number of data register     */
+  __IO uint32_t PAR;    /*!< DMA stream x peripheral address register */
+  __IO uint32_t M0AR;   /*!< DMA stream x memory 0 address register   */
+  __IO uint32_t M1AR;   /*!< DMA stream x memory 1 address register   */
+  __IO uint32_t FCR;    /*!< DMA stream x FIFO control register       */
+} DMA_Stream_TypeDef;
+
+typedef struct
+{
+  __IO uint32_t LISR;   /*!< DMA low interrupt status register,      Address offset: 0x00 */
+  __IO uint32_t HISR;   /*!< DMA high interrupt status register,     Address offset: 0x04 */
+  __IO uint32_t LIFCR;  /*!< DMA low interrupt flag clear register,  Address offset: 0x08 */
+  __IO uint32_t HIFCR;  /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
+} DMA_TypeDef;
+
+/** 
+  * @brief DMA2D Controller
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;            /*!< DMA2D Control Register,                         Address offset: 0x00 */
+  __IO uint32_t ISR;           /*!< DMA2D Interrupt Status Register,                Address offset: 0x04 */
+  __IO uint32_t IFCR;          /*!< DMA2D Interrupt Flag Clear Register,            Address offset: 0x08 */
+  __IO uint32_t FGMAR;         /*!< DMA2D Foreground Memory Address Register,       Address offset: 0x0C */
+  __IO uint32_t FGOR;          /*!< DMA2D Foreground Offset Register,               Address offset: 0x10 */
+  __IO uint32_t BGMAR;         /*!< DMA2D Background Memory Address Register,       Address offset: 0x14 */
+  __IO uint32_t BGOR;          /*!< DMA2D Background Offset Register,               Address offset: 0x18 */
+  __IO uint32_t FGPFCCR;       /*!< DMA2D Foreground PFC Control Register,          Address offset: 0x1C */
+  __IO uint32_t FGCOLR;        /*!< DMA2D Foreground Color Register,                Address offset: 0x20 */
+  __IO uint32_t BGPFCCR;       /*!< DMA2D Background PFC Control Register,          Address offset: 0x24 */
+  __IO uint32_t BGCOLR;        /*!< DMA2D Background Color Register,                Address offset: 0x28 */
+  __IO uint32_t FGCMAR;        /*!< DMA2D Foreground CLUT Memory Address Register,  Address offset: 0x2C */
+  __IO uint32_t BGCMAR;        /*!< DMA2D Background CLUT Memory Address Register,  Address offset: 0x30 */
+  __IO uint32_t OPFCCR;        /*!< DMA2D Output PFC Control Register,              Address offset: 0x34 */
+  __IO uint32_t OCOLR;         /*!< DMA2D Output Color Register,                    Address offset: 0x38 */
+  __IO uint32_t OMAR;          /*!< DMA2D Output Memory Address Register,           Address offset: 0x3C */
+  __IO uint32_t OOR;           /*!< DMA2D Output Offset Register,                   Address offset: 0x40 */
+  __IO uint32_t NLR;           /*!< DMA2D Number of Line Register,                  Address offset: 0x44 */
+  __IO uint32_t LWR;           /*!< DMA2D Line Watermark Register,                  Address offset: 0x48 */
+  __IO uint32_t AMTCR;         /*!< DMA2D AHB Master Timer Configuration Register,  Address offset: 0x4C */
+  uint32_t      RESERVED[236]; /*!< Reserved, 0x50-0x3FF */
+  __IO uint32_t FGCLUT[256];   /*!< DMA2D Foreground CLUT,                          Address offset:400-7FF */
+  __IO uint32_t BGCLUT[256];   /*!< DMA2D Background CLUT,                          Address offset:800-BFF */
+} DMA2D_TypeDef;
+
+/** 
+  * @brief DSI Controller
+  */
+
+typedef struct
+{
+  __IO uint32_t VR;            /*!< DSI Host Version Register,                                 Address offset: 0x00        */
+  __IO uint32_t CR;            /*!< DSI Host Control Register,                                 Address offset: 0x04        */
+  __IO uint32_t CCR;           /*!< DSI HOST Clock Control Register,                           Address offset: 0x08        */
+  __IO uint32_t LVCIDR;        /*!< DSI Host LTDC VCID Register,                               Address offset: 0x0C        */
+  __IO uint32_t LCOLCR;        /*!< DSI Host LTDC Color Coding Register,                       Address offset: 0x10        */
+  __IO uint32_t LPCR;          /*!< DSI Host LTDC Polarity Configuration Register,             Address offset: 0x14        */
+  __IO uint32_t LPMCR;         /*!< DSI Host Low-Power Mode Configuration Register,            Address offset: 0x18        */
+  uint32_t      RESERVED0[4];  /*!< Reserved, 0x1C - 0x2B                                                                  */
+  __IO uint32_t PCR;           /*!< DSI Host Protocol Configuration Register,                  Address offset: 0x2C        */
+  __IO uint32_t GVCIDR;        /*!< DSI Host Generic VCID Register,                            Address offset: 0x30        */
+  __IO uint32_t MCR;           /*!< DSI Host Mode Configuration Register,                      Address offset: 0x34        */
+  __IO uint32_t VMCR;          /*!< DSI Host Video Mode Configuration Register,                Address offset: 0x38        */
+  __IO uint32_t VPCR;          /*!< DSI Host Video Packet Configuration Register,              Address offset: 0x3C        */
+  __IO uint32_t VCCR;          /*!< DSI Host Video Chunks Configuration Register,              Address offset: 0x40        */
+  __IO uint32_t VNPCR;         /*!< DSI Host Video Null Packet Configuration Register,         Address offset: 0x44        */
+  __IO uint32_t VHSACR;        /*!< DSI Host Video HSA Configuration Register,                 Address offset: 0x48        */
+  __IO uint32_t VHBPCR;        /*!< DSI Host Video HBP Configuration Register,                 Address offset: 0x4C        */
+  __IO uint32_t VLCR;          /*!< DSI Host Video Line Configuration Register,                Address offset: 0x50        */
+  __IO uint32_t VVSACR;        /*!< DSI Host Video VSA Configuration Register,                 Address offset: 0x54        */
+  __IO uint32_t VVBPCR;        /*!< DSI Host Video VBP Configuration Register,                 Address offset: 0x58        */
+  __IO uint32_t VVFPCR;        /*!< DSI Host Video VFP Configuration Register,                 Address offset: 0x5C        */
+  __IO uint32_t VVACR;         /*!< DSI Host Video VA Configuration Register,                  Address offset: 0x60        */
+  __IO uint32_t LCCR;          /*!< DSI Host LTDC Command Configuration Register,              Address offset: 0x64        */
+  __IO uint32_t CMCR;          /*!< DSI Host Command Mode Configuration Register,              Address offset: 0x68        */
+  __IO uint32_t GHCR;          /*!< DSI Host Generic Header Configuration Register,            Address offset: 0x6C        */
+  __IO uint32_t GPDR;          /*!< DSI Host Generic Payload Data Register,                    Address offset: 0x70        */
+  __IO uint32_t GPSR;          /*!< DSI Host Generic Packet Status Register,                   Address offset: 0x74        */
+  __IO uint32_t TCCR[6];       /*!< DSI Host Timeout Counter Configuration Register,           Address offset: 0x78-0x8F   */
+  __IO uint32_t TDCR;          /*!< DSI Host 3D Configuration Register,                        Address offset: 0x90        */
+  __IO uint32_t CLCR;          /*!< DSI Host Clock Lane Configuration Register,                Address offset: 0x94        */
+  __IO uint32_t CLTCR;         /*!< DSI Host Clock Lane Timer Configuration Register,          Address offset: 0x98        */
+  __IO uint32_t DLTCR;         /*!< DSI Host Data Lane Timer Configuration Register,           Address offset: 0x9C        */
+  __IO uint32_t PCTLR;         /*!< DSI Host PHY Control Register,                             Address offset: 0xA0        */
+  __IO uint32_t PCONFR;        /*!< DSI Host PHY Configuration Register,                       Address offset: 0xA4        */
+  __IO uint32_t PUCR;          /*!< DSI Host PHY ULPS Control Register,                        Address offset: 0xA8        */
+  __IO uint32_t PTTCR;         /*!< DSI Host PHY TX Triggers Configuration Register,           Address offset: 0xAC        */
+  __IO uint32_t PSR;           /*!< DSI Host PHY Status Register,                              Address offset: 0xB0        */
+  uint32_t      RESERVED1[2];  /*!< Reserved, 0xB4 - 0xBB                                                                  */
+  __IO uint32_t ISR[2];        /*!< DSI Host Interrupt & Status Register,                      Address offset: 0xBC-0xC3   */
+  __IO uint32_t IER[2];        /*!< DSI Host Interrupt Enable Register,                        Address offset: 0xC4-0xCB   */
+  uint32_t      RESERVED2[3];  /*!< Reserved, 0xD0 - 0xD7                                                                  */
+  __IO uint32_t FIR[2];        /*!< DSI Host Force Interrupt Register,                         Address offset: 0xD8-0xDF   */
+  uint32_t      RESERVED3[8];  /*!< Reserved, 0xE0 - 0xFF                                                                  */
+  __IO uint32_t VSCR;          /*!< DSI Host Video Shadow Control Register,                    Address offset: 0x100       */
+  uint32_t      RESERVED4[2];  /*!< Reserved, 0x104 - 0x10B                                                                */
+  __IO uint32_t LCVCIDR;       /*!< DSI Host LTDC Current VCID Register,                       Address offset: 0x10C       */
+  __IO uint32_t LCCCR;         /*!< DSI Host LTDC Current Color Coding Register,               Address offset: 0x110       */
+  uint32_t      RESERVED5;     /*!< Reserved, 0x114                                                                        */
+  __IO uint32_t LPMCCR;        /*!< DSI Host Low-power Mode Current Configuration Register,    Address offset: 0x118       */
+  uint32_t      RESERVED6[7];  /*!< Reserved, 0x11C - 0x137                                                                */
+  __IO uint32_t VMCCR;         /*!< DSI Host Video Mode Current Configuration Register,        Address offset: 0x138       */
+  __IO uint32_t VPCCR;         /*!< DSI Host Video Packet Current Configuration Register,      Address offset: 0x13C       */
+  __IO uint32_t VCCCR;         /*!< DSI Host Video Chunks Current Configuration Register,     Address offset: 0x140       */
+  __IO uint32_t VNPCCR;        /*!< DSI Host Video Null Packet Current Configuration Register, Address offset: 0x144       */
+  __IO uint32_t VHSACCR;       /*!< DSI Host Video HSA Current Configuration Register,         Address offset: 0x148       */
+  __IO uint32_t VHBPCCR;       /*!< DSI Host Video HBP Current Configuration Register,         Address offset: 0x14C       */
+  __IO uint32_t VLCCR;         /*!< DSI Host Video Line Current Configuration Register,        Address offset: 0x150       */
+  __IO uint32_t VVSACCR;       /*!< DSI Host Video VSA Current Configuration Register,         Address offset: 0x154       */
+  __IO uint32_t VVBPCCR;       /*!< DSI Host Video VBP Current Configuration Register,         Address offset: 0x158       */
+  __IO uint32_t VVFPCCR;       /*!< DSI Host Video VFP Current Configuration Register,         Address offset: 0x15C       */
+  __IO uint32_t VVACCR;        /*!< DSI Host Video VA Current Configuration Register,          Address offset: 0x160       */
+  uint32_t      RESERVED7[11]; /*!< Reserved, 0x164 - 0x18F                                                                */
+  __IO uint32_t TDCCR;         /*!< DSI Host 3D Current Configuration Register,                Address offset: 0x190       */
+  uint32_t      RESERVED8[155]; /*!< Reserved, 0x194 - 0x3FF                                                               */
+  __IO uint32_t WCFGR;          /*!< DSI Wrapper Configuration Register,                       Address offset: 0x400       */
+  __IO uint32_t WCR;            /*!< DSI Wrapper Control Register,                             Address offset: 0x404       */
+  __IO uint32_t WIER;           /*!< DSI Wrapper Interrupt Enable Register,                    Address offset: 0x408       */
+  __IO uint32_t WISR;           /*!< DSI Wrapper Interrupt and Status Register,                Address offset: 0x40C       */
+  __IO uint32_t WIFCR;          /*!< DSI Wrapper Interrupt Flag Clear Register,                Address offset: 0x410       */
+  uint32_t      RESERVED9;      /*!< Reserved, 0x414                                                                       */
+  __IO uint32_t WPCR[5];        /*!< DSI Wrapper PHY Configuration Register,                   Address offset: 0x418-0x42B */
+  uint32_t      RESERVED10;     /*!< Reserved, 0x42C                                                                       */
+  __IO uint32_t WRPCR;          /*!< DSI Wrapper Regulator and PLL Control Register, Address offset: 0x430                 */
+} DSI_TypeDef;
+
+/** 
+  * @brief Ethernet MAC
+  */
+
+typedef struct
+{
+  __IO uint32_t MACCR;
+  __IO uint32_t MACFFR;
+  __IO uint32_t MACHTHR;
+  __IO uint32_t MACHTLR;
+  __IO uint32_t MACMIIAR;
+  __IO uint32_t MACMIIDR;
+  __IO uint32_t MACFCR;
+  __IO uint32_t MACVLANTR;             /*    8 */
+  uint32_t      RESERVED0[2];
+  __IO uint32_t MACRWUFFR;             /*   11 */
+  __IO uint32_t MACPMTCSR;
+  uint32_t      RESERVED1;
+  __IO uint32_t MACDBGR;
+  __IO uint32_t MACSR;                 /*   15 */
+  __IO uint32_t MACIMR;
+  __IO uint32_t MACA0HR;
+  __IO uint32_t MACA0LR;
+  __IO uint32_t MACA1HR;
+  __IO uint32_t MACA1LR;
+  __IO uint32_t MACA2HR;
+  __IO uint32_t MACA2LR;
+  __IO uint32_t MACA3HR;
+  __IO uint32_t MACA3LR;               /*   24 */
+  uint32_t      RESERVED2[40];
+  __IO uint32_t MMCCR;                 /*   65 */
+  __IO uint32_t MMCRIR;
+  __IO uint32_t MMCTIR;
+  __IO uint32_t MMCRIMR;
+  __IO uint32_t MMCTIMR;               /*   69 */
+  uint32_t      RESERVED3[14];
+  __IO uint32_t MMCTGFSCCR;            /*   84 */
+  __IO uint32_t MMCTGFMSCCR;
+  uint32_t      RESERVED4[5];
+  __IO uint32_t MMCTGFCR;
+  uint32_t      RESERVED5[10];
+  __IO uint32_t MMCRFCECR;
+  __IO uint32_t MMCRFAECR;
+  uint32_t      RESERVED6[10];
+  __IO uint32_t MMCRGUFCR;
+  uint32_t      RESERVED7[334];
+  __IO uint32_t PTPTSCR;
+  __IO uint32_t PTPSSIR;
+  __IO uint32_t PTPTSHR;
+  __IO uint32_t PTPTSLR;
+  __IO uint32_t PTPTSHUR;
+  __IO uint32_t PTPTSLUR;
+  __IO uint32_t PTPTSAR;
+  __IO uint32_t PTPTTHR;
+  __IO uint32_t PTPTTLR;
+  __IO uint32_t RESERVED8;
+  __IO uint32_t PTPTSSR;
+  uint32_t      RESERVED9[565];
+  __IO uint32_t DMABMR;
+  __IO uint32_t DMATPDR;
+  __IO uint32_t DMARPDR;
+  __IO uint32_t DMARDLAR;
+  __IO uint32_t DMATDLAR;
+  __IO uint32_t DMASR;
+  __IO uint32_t DMAOMR;
+  __IO uint32_t DMAIER;
+  __IO uint32_t DMAMFBOCR;
+  __IO uint32_t DMARSWTR;
+  uint32_t      RESERVED10[8];
+  __IO uint32_t DMACHTDR;
+  __IO uint32_t DMACHRDR;
+  __IO uint32_t DMACHTBAR;
+  __IO uint32_t DMACHRBAR;
+} ETH_TypeDef;
+
+/** 
+  * @brief External Interrupt/Event Controller
+  */
+
+typedef struct
+{
+  __IO uint32_t IMR;    /*!< EXTI Interrupt mask register,            Address offset: 0x00 */
+  __IO uint32_t EMR;    /*!< EXTI Event mask register,                Address offset: 0x04 */
+  __IO uint32_t RTSR;   /*!< EXTI Rising trigger selection register,  Address offset: 0x08 */
+  __IO uint32_t FTSR;   /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
+  __IO uint32_t SWIER;  /*!< EXTI Software interrupt event register,  Address offset: 0x10 */
+  __IO uint32_t PR;     /*!< EXTI Pending register,                   Address offset: 0x14 */
+} EXTI_TypeDef;
+
+/** 
+  * @brief FLASH Registers
+  */
+
+typedef struct
+{
+  __IO uint32_t ACR;      /*!< FLASH access control register,   Address offset: 0x00 */
+  __IO uint32_t KEYR;     /*!< FLASH key register,              Address offset: 0x04 */
+  __IO uint32_t OPTKEYR;  /*!< FLASH option key register,       Address offset: 0x08 */
+  __IO uint32_t SR;       /*!< FLASH status register,           Address offset: 0x0C */
+  __IO uint32_t CR;       /*!< FLASH control register,          Address offset: 0x10 */
+  __IO uint32_t OPTCR;    /*!< FLASH option control register ,  Address offset: 0x14 */
+  __IO uint32_t OPTCR1;   /*!< FLASH option control register 1, Address offset: 0x18 */
+} FLASH_TypeDef;
+
+/** 
+  * @brief Flexible Memory Controller
+  */
+
+typedef struct
+{
+  __IO uint32_t BTCR[8];    /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */
+} FMC_Bank1_TypeDef; 
+
+/** 
+  * @brief Flexible Memory Controller Bank1E
+  */
+  
+typedef struct
+{
+  __IO uint32_t BWTR[7];    /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
+} FMC_Bank1E_TypeDef;
+
+/** 
+  * @brief Flexible Memory Controller Bank3
+  */
+ 
+typedef struct
+{
+  __IO uint32_t PCR;       /*!< NAND Flash control register,                       Address offset: 0x80 */
+  __IO uint32_t SR;        /*!< NAND Flash FIFO status and interrupt register,     Address offset: 0x84 */
+  __IO uint32_t PMEM;      /*!< NAND Flash Common memory space timing register,    Address offset: 0x88 */
+  __IO uint32_t PATT;      /*!< NAND Flash Attribute memory space timing register, Address offset: 0x8C */
+  uint32_t      RESERVED;  /*!< Reserved, 0x90                                                          */
+  __IO uint32_t ECCR;      /*!< NAND Flash ECC result registers,                   Address offset: 0x94 */
+} FMC_Bank3_TypeDef;
+
+/** 
+  * @brief Flexible Memory Controller Bank5_6
+  */
+  
+typedef struct
+{
+  __IO uint32_t SDCR[2];        /*!< SDRAM Control registers ,      Address offset: 0x140-0x144  */
+  __IO uint32_t SDTR[2];        /*!< SDRAM Timing registers ,       Address offset: 0x148-0x14C  */
+  __IO uint32_t SDCMR;          /*!< SDRAM Command Mode register,   Address offset: 0x150        */
+  __IO uint32_t SDRTR;          /*!< SDRAM Refresh Timer register,  Address offset: 0x154        */
+  __IO uint32_t SDSR;           /*!< SDRAM Status register,         Address offset: 0x158        */
+} FMC_Bank5_6_TypeDef;
+
+/** 
+  * @brief General Purpose I/O
+  */
+
+typedef struct
+{
+  __IO uint32_t MODER;    /*!< GPIO port mode register,               Address offset: 0x00      */
+  __IO uint32_t OTYPER;   /*!< GPIO port output type register,        Address offset: 0x04      */
+  __IO uint32_t OSPEEDR;  /*!< GPIO port output speed register,       Address offset: 0x08      */
+  __IO uint32_t PUPDR;    /*!< GPIO port pull-up/pull-down register,  Address offset: 0x0C      */
+  __IO uint32_t IDR;      /*!< GPIO port input data register,         Address offset: 0x10      */
+  __IO uint32_t ODR;      /*!< GPIO port output data register,        Address offset: 0x14      */
+  __IO uint32_t BSRR;     /*!< GPIO port bit set/reset register,      Address offset: 0x18      */
+  __IO uint32_t LCKR;     /*!< GPIO port configuration lock register, Address offset: 0x1C      */
+  __IO uint32_t AFR[2];   /*!< GPIO alternate function registers,     Address offset: 0x20-0x24 */
+} GPIO_TypeDef;
+
+/** 
+  * @brief System configuration controller
+  */
+
+typedef struct
+{
+  __IO uint32_t MEMRMP;       /*!< SYSCFG memory remap register,                      Address offset: 0x00      */
+  __IO uint32_t PMC;          /*!< SYSCFG peripheral mode configuration register,     Address offset: 0x04      */
+  __IO uint32_t EXTICR[4];    /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
+  uint32_t      RESERVED[2];  /*!< Reserved, 0x18-0x1C                                                          */
+  __IO uint32_t CMPCR;        /*!< SYSCFG Compensation cell control register,         Address offset: 0x20      */
+} SYSCFG_TypeDef;
+
+/** 
+  * @brief Inter-integrated Circuit Interface
+  */
+
+typedef struct
+{
+  __IO uint32_t CR1;        /*!< I2C Control register 1,     Address offset: 0x00 */
+  __IO uint32_t CR2;        /*!< I2C Control register 2,     Address offset: 0x04 */
+  __IO uint32_t OAR1;       /*!< I2C Own address register 1, Address offset: 0x08 */
+  __IO uint32_t OAR2;       /*!< I2C Own address register 2, Address offset: 0x0C */
+  __IO uint32_t DR;         /*!< I2C Data register,          Address offset: 0x10 */
+  __IO uint32_t SR1;        /*!< I2C Status register 1,      Address offset: 0x14 */
+  __IO uint32_t SR2;        /*!< I2C Status register 2,      Address offset: 0x18 */
+  __IO uint32_t CCR;        /*!< I2C Clock control register, Address offset: 0x1C */
+  __IO uint32_t TRISE;      /*!< I2C TRISE register,         Address offset: 0x20 */
+  __IO uint32_t FLTR;       /*!< I2C FLTR register,          Address offset: 0x24 */
+} I2C_TypeDef;
+
+/** 
+  * @brief Independent WATCHDOG
+  */
+
+typedef struct
+{
+  __IO uint32_t KR;   /*!< IWDG Key register,       Address offset: 0x00 */
+  __IO uint32_t PR;   /*!< IWDG Prescaler register, Address offset: 0x04 */
+  __IO uint32_t RLR;  /*!< IWDG Reload register,    Address offset: 0x08 */
+  __IO uint32_t SR;   /*!< IWDG Status register,    Address offset: 0x0C */
+} IWDG_TypeDef;
+
+/** 
+  * @brief LCD-TFT Display Controller
+  */
+  
+typedef struct
+{
+  uint32_t      RESERVED0[2];  /*!< Reserved, 0x00-0x04                                                       */
+  __IO uint32_t SSCR;          /*!< LTDC Synchronization Size Configuration Register,    Address offset: 0x08 */
+  __IO uint32_t BPCR;          /*!< LTDC Back Porch Configuration Register,              Address offset: 0x0C */
+  __IO uint32_t AWCR;          /*!< LTDC Active Width Configuration Register,            Address offset: 0x10 */
+  __IO uint32_t TWCR;          /*!< LTDC Total Width Configuration Register,             Address offset: 0x14 */
+  __IO uint32_t GCR;           /*!< LTDC Global Control Register,                        Address offset: 0x18 */
+  uint32_t      RESERVED1[2];  /*!< Reserved, 0x1C-0x20                                                       */
+  __IO uint32_t SRCR;          /*!< LTDC Shadow Reload Configuration Register,           Address offset: 0x24 */
+  uint32_t      RESERVED2[1];  /*!< Reserved, 0x28                                                            */
+  __IO uint32_t BCCR;          /*!< LTDC Background Color Configuration Register,        Address offset: 0x2C */
+  uint32_t      RESERVED3[1];  /*!< Reserved, 0x30                                                            */
+  __IO uint32_t IER;           /*!< LTDC Interrupt Enable Register,                      Address offset: 0x34 */
+  __IO uint32_t ISR;           /*!< LTDC Interrupt Status Register,                      Address offset: 0x38 */
+  __IO uint32_t ICR;           /*!< LTDC Interrupt Clear Register,                       Address offset: 0x3C */
+  __IO uint32_t LIPCR;         /*!< LTDC Line Interrupt Position Configuration Register, Address offset: 0x40 */
+  __IO uint32_t CPSR;          /*!< LTDC Current Position Status Register,               Address offset: 0x44 */
+  __IO uint32_t CDSR;          /*!< LTDC Current Display Status Register,                Address offset: 0x48 */
+} LTDC_TypeDef;
+
+/** 
+  * @brief LCD-TFT Display layer x Controller
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;            /*!< LTDC Layerx Control Register                                  Address offset: 0x84 */
+  __IO uint32_t WHPCR;         /*!< LTDC Layerx Window Horizontal Position Configuration Register Address offset: 0x88 */
+  __IO uint32_t WVPCR;         /*!< LTDC Layerx Window Vertical Position Configuration Register   Address offset: 0x8C */
+  __IO uint32_t CKCR;          /*!< LTDC Layerx Color Keying Configuration Register               Address offset: 0x90 */
+  __IO uint32_t PFCR;          /*!< LTDC Layerx Pixel Format Configuration Register               Address offset: 0x94 */
+  __IO uint32_t CACR;          /*!< LTDC Layerx Constant Alpha Configuration Register             Address offset: 0x98 */
+  __IO uint32_t DCCR;          /*!< LTDC Layerx Default Color Configuration Register              Address offset: 0x9C */
+  __IO uint32_t BFCR;          /*!< LTDC Layerx Blending Factors Configuration Register           Address offset: 0xA0 */
+  uint32_t      RESERVED0[2];  /*!< Reserved                                                                           */
+  __IO uint32_t CFBAR;         /*!< LTDC Layerx Color Frame Buffer Address Register               Address offset: 0xAC */
+  __IO uint32_t CFBLR;         /*!< LTDC Layerx Color Frame Buffer Length Register                Address offset: 0xB0 */
+  __IO uint32_t CFBLNR;        /*!< LTDC Layerx ColorFrame Buffer Line Number Register            Address offset: 0xB4 */
+  uint32_t      RESERVED1[3];  /*!< Reserved                                                                           */
+  __IO uint32_t CLUTWR;        /*!< LTDC Layerx CLUT Write Register                               Address offset: 0x144*/
+} LTDC_Layer_TypeDef;
+
+/** 
+  * @brief Power Control
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;   /*!< PWR power control register,        Address offset: 0x00 */
+  __IO uint32_t CSR;  /*!< PWR power control/status register, Address offset: 0x04 */
+} PWR_TypeDef;
+
+/** 
+  * @brief Reset and Clock Control
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;            /*!< RCC clock control register,                                  Address offset: 0x00 */
+  __IO uint32_t PLLCFGR;       /*!< RCC PLL configuration register,                              Address offset: 0x04 */
+  __IO uint32_t CFGR;          /*!< RCC clock configuration register,                            Address offset: 0x08 */
+  __IO uint32_t CIR;           /*!< RCC clock interrupt register,                                Address offset: 0x0C */
+  __IO uint32_t AHB1RSTR;      /*!< RCC AHB1 peripheral reset register,                          Address offset: 0x10 */
+  __IO uint32_t AHB2RSTR;      /*!< RCC AHB2 peripheral reset register,                          Address offset: 0x14 */
+  __IO uint32_t AHB3RSTR;      /*!< RCC AHB3 peripheral reset register,                          Address offset: 0x18 */
+  uint32_t      RESERVED0;     /*!< Reserved, 0x1C                                                                    */
+  __IO uint32_t APB1RSTR;      /*!< RCC APB1 peripheral reset register,                          Address offset: 0x20 */
+  __IO uint32_t APB2RSTR;      /*!< RCC APB2 peripheral reset register,                          Address offset: 0x24 */
+  uint32_t      RESERVED1[2];  /*!< Reserved, 0x28-0x2C                                                               */
+  __IO uint32_t AHB1ENR;       /*!< RCC AHB1 peripheral clock register,                          Address offset: 0x30 */
+  __IO uint32_t AHB2ENR;       /*!< RCC AHB2 peripheral clock register,                          Address offset: 0x34 */
+  __IO uint32_t AHB3ENR;       /*!< RCC AHB3 peripheral clock register,                          Address offset: 0x38 */
+  uint32_t      RESERVED2;     /*!< Reserved, 0x3C                                                                    */
+  __IO uint32_t APB1ENR;       /*!< RCC APB1 peripheral clock enable register,                   Address offset: 0x40 */
+  __IO uint32_t APB2ENR;       /*!< RCC APB2 peripheral clock enable register,                   Address offset: 0x44 */
+  uint32_t      RESERVED3[2];  /*!< Reserved, 0x48-0x4C                                                               */
+  __IO uint32_t AHB1LPENR;     /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */
+  __IO uint32_t AHB2LPENR;     /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */
+  __IO uint32_t AHB3LPENR;     /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */
+  uint32_t      RESERVED4;     /*!< Reserved, 0x5C                                                                    */
+  __IO uint32_t APB1LPENR;     /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */
+  __IO uint32_t APB2LPENR;     /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */
+  uint32_t      RESERVED5[2];  /*!< Reserved, 0x68-0x6C                                                               */
+  __IO uint32_t BDCR;          /*!< RCC Backup domain control register,                          Address offset: 0x70 */
+  __IO uint32_t CSR;           /*!< RCC clock control & status register,                         Address offset: 0x74 */
+  uint32_t      RESERVED6[2];  /*!< Reserved, 0x78-0x7C                                                               */
+  __IO uint32_t SSCGR;         /*!< RCC spread spectrum clock generation register,               Address offset: 0x80 */
+  __IO uint32_t PLLI2SCFGR;    /*!< RCC PLLI2S configuration register,                           Address offset: 0x84 */
+  __IO uint32_t PLLSAICFGR;    /*!< RCC PLLSAI configuration register,                           Address offset: 0x88 */
+  __IO uint32_t DCKCFGR;       /*!< RCC Dedicated Clocks configuration register,                 Address offset: 0x8C */
+} RCC_TypeDef;
+
+/** 
+  * @brief Real-Time Clock
+  */
+
+typedef struct
+{
+  __IO uint32_t TR;      /*!< RTC time register,                                        Address offset: 0x00 */
+  __IO uint32_t DR;      /*!< RTC date register,                                        Address offset: 0x04 */
+  __IO uint32_t CR;      /*!< RTC control register,                                     Address offset: 0x08 */
+  __IO uint32_t ISR;     /*!< RTC initialization and status register,                   Address offset: 0x0C */
+  __IO uint32_t PRER;    /*!< RTC prescaler register,                                   Address offset: 0x10 */
+  __IO uint32_t WUTR;    /*!< RTC wakeup timer register,                                Address offset: 0x14 */
+  __IO uint32_t CALIBR;  /*!< RTC calibration register,                                 Address offset: 0x18 */
+  __IO uint32_t ALRMAR;  /*!< RTC alarm A register,                                     Address offset: 0x1C */
+  __IO uint32_t ALRMBR;  /*!< RTC alarm B register,                                     Address offset: 0x20 */
+  __IO uint32_t WPR;     /*!< RTC write protection register,                            Address offset: 0x24 */
+  __IO uint32_t SSR;     /*!< RTC sub second register,                                  Address offset: 0x28 */
+  __IO uint32_t SHIFTR;  /*!< RTC shift control register,                               Address offset: 0x2C */
+  __IO uint32_t TSTR;    /*!< RTC time stamp time register,                             Address offset: 0x30 */
+  __IO uint32_t TSDR;    /*!< RTC time stamp date register,                             Address offset: 0x34 */
+  __IO uint32_t TSSSR;   /*!< RTC time-stamp sub second register,                       Address offset: 0x38 */
+  __IO uint32_t CALR;    /*!< RTC calibration register,                                 Address offset: 0x3C */
+  __IO uint32_t TAFCR;   /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
+  __IO uint32_t ALRMASSR;/*!< RTC alarm A sub second register,                          Address offset: 0x44 */
+  __IO uint32_t ALRMBSSR;/*!< RTC alarm B sub second register,                          Address offset: 0x48 */
+  uint32_t RESERVED7;    /*!< Reserved, 0x4C                                                                 */
+  __IO uint32_t BKP0R;   /*!< RTC backup register 1,                                    Address offset: 0x50 */
+  __IO uint32_t BKP1R;   /*!< RTC backup register 1,                                    Address offset: 0x54 */
+  __IO uint32_t BKP2R;   /*!< RTC backup register 2,                                    Address offset: 0x58 */
+  __IO uint32_t BKP3R;   /*!< RTC backup register 3,                                    Address offset: 0x5C */
+  __IO uint32_t BKP4R;   /*!< RTC backup register 4,                                    Address offset: 0x60 */
+  __IO uint32_t BKP5R;   /*!< RTC backup register 5,                                    Address offset: 0x64 */
+  __IO uint32_t BKP6R;   /*!< RTC backup register 6,                                    Address offset: 0x68 */
+  __IO uint32_t BKP7R;   /*!< RTC backup register 7,                                    Address offset: 0x6C */
+  __IO uint32_t BKP8R;   /*!< RTC backup register 8,                                    Address offset: 0x70 */
+  __IO uint32_t BKP9R;   /*!< RTC backup register 9,                                    Address offset: 0x74 */
+  __IO uint32_t BKP10R;  /*!< RTC backup register 10,                                   Address offset: 0x78 */
+  __IO uint32_t BKP11R;  /*!< RTC backup register 11,                                   Address offset: 0x7C */
+  __IO uint32_t BKP12R;  /*!< RTC backup register 12,                                   Address offset: 0x80 */
+  __IO uint32_t BKP13R;  /*!< RTC backup register 13,                                   Address offset: 0x84 */
+  __IO uint32_t BKP14R;  /*!< RTC backup register 14,                                   Address offset: 0x88 */
+  __IO uint32_t BKP15R;  /*!< RTC backup register 15,                                   Address offset: 0x8C */
+  __IO uint32_t BKP16R;  /*!< RTC backup register 16,                                   Address offset: 0x90 */
+  __IO uint32_t BKP17R;  /*!< RTC backup register 17,                                   Address offset: 0x94 */
+  __IO uint32_t BKP18R;  /*!< RTC backup register 18,                                   Address offset: 0x98 */
+  __IO uint32_t BKP19R;  /*!< RTC backup register 19,                                   Address offset: 0x9C */
+} RTC_TypeDef;
+
+/** 
+  * @brief Serial Audio Interface
+  */
+  
+typedef struct
+{
+  __IO uint32_t GCR;      /*!< SAI global configuration register,        Address offset: 0x00 */
+} SAI_TypeDef;
+
+typedef struct
+{
+  __IO uint32_t CR1;      /*!< SAI block x configuration register 1,     Address offset: 0x04 */
+  __IO uint32_t CR2;      /*!< SAI block x configuration register 2,     Address offset: 0x08 */
+  __IO uint32_t FRCR;     /*!< SAI block x frame configuration register, Address offset: 0x0C */
+  __IO uint32_t SLOTR;    /*!< SAI block x slot register,                Address offset: 0x10 */
+  __IO uint32_t IMR;      /*!< SAI block x interrupt mask register,      Address offset: 0x14 */
+  __IO uint32_t SR;       /*!< SAI block x status register,              Address offset: 0x18 */
+  __IO uint32_t CLRFR;    /*!< SAI block x clear flag register,          Address offset: 0x1C */
+  __IO uint32_t DR;       /*!< SAI block x data register,                Address offset: 0x20 */
+} SAI_Block_TypeDef;
+
+/** 
+  * @brief SD host Interface
+  */
+
+typedef struct
+{
+  __IO uint32_t POWER;                 /*!< SDIO power control register,    Address offset: 0x00 */
+  __IO uint32_t CLKCR;                 /*!< SDI clock control register,     Address offset: 0x04 */
+  __IO uint32_t ARG;                   /*!< SDIO argument register,         Address offset: 0x08 */
+  __IO uint32_t CMD;                   /*!< SDIO command register,          Address offset: 0x0C */
+  __IO const uint32_t  RESPCMD;        /*!< SDIO command response register, Address offset: 0x10 */
+  __IO const uint32_t  RESP1;          /*!< SDIO response 1 register,       Address offset: 0x14 */
+  __IO const uint32_t  RESP2;          /*!< SDIO response 2 register,       Address offset: 0x18 */
+  __IO const uint32_t  RESP3;          /*!< SDIO response 3 register,       Address offset: 0x1C */
+  __IO const uint32_t  RESP4;          /*!< SDIO response 4 register,       Address offset: 0x20 */
+  __IO uint32_t DTIMER;                /*!< SDIO data timer register,       Address offset: 0x24 */
+  __IO uint32_t DLEN;                  /*!< SDIO data length register,      Address offset: 0x28 */
+  __IO uint32_t DCTRL;                 /*!< SDIO data control register,     Address offset: 0x2C */
+  __IO const uint32_t  DCOUNT;         /*!< SDIO data counter register,     Address offset: 0x30 */
+  __IO const uint32_t  STA;            /*!< SDIO status register,           Address offset: 0x34 */
+  __IO uint32_t ICR;                   /*!< SDIO interrupt clear register,  Address offset: 0x38 */
+  __IO uint32_t MASK;                  /*!< SDIO mask register,             Address offset: 0x3C */
+  uint32_t      RESERVED0[2];          /*!< Reserved, 0x40-0x44                                  */
+  __IO const uint32_t  FIFOCNT;        /*!< SDIO FIFO counter register,     Address offset: 0x48 */
+  uint32_t      RESERVED1[13];         /*!< Reserved, 0x4C-0x7C                                  */
+  __IO uint32_t FIFO;                  /*!< SDIO data FIFO register,        Address offset: 0x80 */
+} SDIO_TypeDef;
+
+/** 
+  * @brief Serial Peripheral Interface
+  */
+
+typedef struct
+{
+  __IO uint32_t CR1;        /*!< SPI control register 1 (not used in I2S mode),      Address offset: 0x00 */
+  __IO uint32_t CR2;        /*!< SPI control register 2,                             Address offset: 0x04 */
+  __IO uint32_t SR;         /*!< SPI status register,                                Address offset: 0x08 */
+  __IO uint32_t DR;         /*!< SPI data register,                                  Address offset: 0x0C */
+  __IO uint32_t CRCPR;      /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
+  __IO uint32_t RXCRCR;     /*!< SPI RX CRC register (not used in I2S mode),         Address offset: 0x14 */
+  __IO uint32_t TXCRCR;     /*!< SPI TX CRC register (not used in I2S mode),         Address offset: 0x18 */
+  __IO uint32_t I2SCFGR;    /*!< SPI_I2S configuration register,                     Address offset: 0x1C */
+  __IO uint32_t I2SPR;      /*!< SPI_I2S prescaler register,                         Address offset: 0x20 */
+} SPI_TypeDef;
+
+/** 
+  * @brief QUAD Serial Peripheral Interface
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;       /*!< QUADSPI Control register,                           Address offset: 0x00 */
+  __IO uint32_t DCR;      /*!< QUADSPI Device Configuration register,              Address offset: 0x04 */
+  __IO uint32_t SR;       /*!< QUADSPI Status register,                            Address offset: 0x08 */
+  __IO uint32_t FCR;      /*!< QUADSPI Flag Clear register,                        Address offset: 0x0C */
+  __IO uint32_t DLR;      /*!< QUADSPI Data Length register,                       Address offset: 0x10 */
+  __IO uint32_t CCR;      /*!< QUADSPI Communication Configuration register,       Address offset: 0x14 */
+  __IO uint32_t AR;       /*!< QUADSPI Address register,                           Address offset: 0x18 */
+  __IO uint32_t ABR;      /*!< QUADSPI Alternate Bytes register,                   Address offset: 0x1C */
+  __IO uint32_t DR;       /*!< QUADSPI Data register,                              Address offset: 0x20 */
+  __IO uint32_t PSMKR;    /*!< QUADSPI Polling Status Mask register,               Address offset: 0x24 */
+  __IO uint32_t PSMAR;    /*!< QUADSPI Polling Status Match register,              Address offset: 0x28 */
+  __IO uint32_t PIR;      /*!< QUADSPI Polling Interval register,                  Address offset: 0x2C */
+  __IO uint32_t LPTR;     /*!< QUADSPI Low Power Timeout register,                 Address offset: 0x30 */
+} QUADSPI_TypeDef;
+
+/** 
+  * @brief TIM
+  */
+
+typedef struct
+{
+  __IO uint32_t CR1;         /*!< TIM control register 1,              Address offset: 0x00 */
+  __IO uint32_t CR2;         /*!< TIM control register 2,              Address offset: 0x04 */
+  __IO uint32_t SMCR;        /*!< TIM slave mode control register,     Address offset: 0x08 */
+  __IO uint32_t DIER;        /*!< TIM DMA/interrupt enable register,   Address offset: 0x0C */
+  __IO uint32_t SR;          /*!< TIM status register,                 Address offset: 0x10 */
+  __IO uint32_t EGR;         /*!< TIM event generation register,       Address offset: 0x14 */
+  __IO uint32_t CCMR1;       /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
+  __IO uint32_t CCMR2;       /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
+  __IO uint32_t CCER;        /*!< TIM capture/compare enable register, Address offset: 0x20 */
+  __IO uint32_t CNT;         /*!< TIM counter register,                Address offset: 0x24 */
+  __IO uint32_t PSC;         /*!< TIM prescaler,                       Address offset: 0x28 */
+  __IO uint32_t ARR;         /*!< TIM auto-reload register,            Address offset: 0x2C */
+  __IO uint32_t RCR;         /*!< TIM repetition counter register,     Address offset: 0x30 */
+  __IO uint32_t CCR1;        /*!< TIM capture/compare register 1,      Address offset: 0x34 */
+  __IO uint32_t CCR2;        /*!< TIM capture/compare register 2,      Address offset: 0x38 */
+  __IO uint32_t CCR3;        /*!< TIM capture/compare register 3,      Address offset: 0x3C */
+  __IO uint32_t CCR4;        /*!< TIM capture/compare register 4,      Address offset: 0x40 */
+  __IO uint32_t BDTR;        /*!< TIM break and dead-time register,    Address offset: 0x44 */
+  __IO uint32_t DCR;         /*!< TIM DMA control register,            Address offset: 0x48 */
+  __IO uint32_t DMAR;        /*!< TIM DMA address for full transfer,   Address offset: 0x4C */
+  __IO uint32_t OR;          /*!< TIM option register,                 Address offset: 0x50 */
+} TIM_TypeDef;
+
+/** 
+  * @brief Universal Synchronous Asynchronous Receiver Transmitter
+  */
+ 
+typedef struct
+{
+  __IO uint32_t SR;         /*!< USART Status register,                   Address offset: 0x00 */
+  __IO uint32_t DR;         /*!< USART Data register,                     Address offset: 0x04 */
+  __IO uint32_t BRR;        /*!< USART Baud rate register,                Address offset: 0x08 */
+  __IO uint32_t CR1;        /*!< USART Control register 1,                Address offset: 0x0C */
+  __IO uint32_t CR2;        /*!< USART Control register 2,                Address offset: 0x10 */
+  __IO uint32_t CR3;        /*!< USART Control register 3,                Address offset: 0x14 */
+  __IO uint32_t GTPR;       /*!< USART Guard time and prescaler register, Address offset: 0x18 */
+} USART_TypeDef;
+
+/** 
+  * @brief Window WATCHDOG
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;   /*!< WWDG Control register,       Address offset: 0x00 */
+  __IO uint32_t CFR;  /*!< WWDG Configuration register, Address offset: 0x04 */
+  __IO uint32_t SR;   /*!< WWDG Status register,        Address offset: 0x08 */
+} WWDG_TypeDef;
+
+/** 
+  * @brief RNG
+  */
+  
+typedef struct 
+{
+  __IO uint32_t CR;  /*!< RNG control register, Address offset: 0x00 */
+  __IO uint32_t SR;  /*!< RNG status register,  Address offset: 0x04 */
+  __IO uint32_t DR;  /*!< RNG data register,    Address offset: 0x08 */
+} RNG_TypeDef;
+
+/** 
+  * @brief USB_OTG_Core_Registers
+  */
+typedef struct
+{
+  __IO uint32_t GOTGCTL;              /*!< USB_OTG Control and Status Register          000h */
+  __IO uint32_t GOTGINT;              /*!< USB_OTG Interrupt Register                   004h */
+  __IO uint32_t GAHBCFG;              /*!< Core AHB Configuration Register              008h */
+  __IO uint32_t GUSBCFG;              /*!< Core USB Configuration Register              00Ch */
+  __IO uint32_t GRSTCTL;              /*!< Core Reset Register                          010h */
+  __IO uint32_t GINTSTS;              /*!< Core Interrupt Register                      014h */
+  __IO uint32_t GINTMSK;              /*!< Core Interrupt Mask Register                 018h */
+  __IO uint32_t GRXSTSR;              /*!< Receive Sts Q Read Register                  01Ch */
+  __IO uint32_t GRXSTSP;              /*!< Receive Sts Q Read & POP Register            020h */
+  __IO uint32_t GRXFSIZ;              /*!< Receive FIFO Size Register                   024h */
+  __IO uint32_t DIEPTXF0_HNPTXFSIZ;   /*!< EP0 / Non Periodic Tx FIFO Size Register     028h */
+  __IO uint32_t HNPTXSTS;             /*!< Non Periodic Tx FIFO/Queue Sts reg           02Ch */
+  uint32_t Reserved30[2];             /*!< Reserved                                     030h */
+  __IO uint32_t GCCFG;                /*!< General Purpose IO Register                  038h */
+  __IO uint32_t CID;                  /*!< User ID Register                             03Ch */
+  uint32_t  Reserved5[3];             /*!< Reserved                                040h-048h */
+  __IO uint32_t GHWCFG3;              /*!< User HW config3                              04Ch */
+  uint32_t  Reserved6;                /*!< Reserved                                     050h */
+  __IO uint32_t GLPMCFG;              /*!< LPM Register                                 054h */
+  uint32_t  Reserved;                 /*!< Reserved                                     058h */
+  __IO uint32_t GDFIFOCFG;            /*!< DFIFO Software Config Register               05Ch */
+  uint32_t  Reserved43[40];           /*!< Reserved                                058h-0FFh */
+  __IO uint32_t HPTXFSIZ;             /*!< Host Periodic Tx FIFO Size Reg               100h */
+  __IO uint32_t DIEPTXF[0x0F];        /*!< dev Periodic Transmit FIFO                        */
+} USB_OTG_GlobalTypeDef;
+
+/** 
+  * @brief USB_OTG_device_Registers
+  */
+typedef struct 
+{
+  __IO uint32_t DCFG;            /*!< dev Configuration Register   800h */
+  __IO uint32_t DCTL;            /*!< dev Control Register         804h */
+  __IO uint32_t DSTS;            /*!< dev Status Register (RO)     808h */
+  uint32_t Reserved0C;           /*!< Reserved                     80Ch */
+  __IO uint32_t DIEPMSK;         /*!< dev IN Endpoint Mask         810h */
+  __IO uint32_t DOEPMSK;         /*!< dev OUT Endpoint Mask        814h */
+  __IO uint32_t DAINT;           /*!< dev All Endpoints Itr Reg    818h */
+  __IO uint32_t DAINTMSK;        /*!< dev All Endpoints Itr Mask   81Ch */
+  uint32_t  Reserved20;          /*!< Reserved                     820h */
+  uint32_t Reserved9;            /*!< Reserved                     824h */
+  __IO uint32_t DVBUSDIS;        /*!< dev VBUS discharge Register  828h */
+  __IO uint32_t DVBUSPULSE;      /*!< dev VBUS Pulse Register      82Ch */
+  __IO uint32_t DTHRCTL;         /*!< dev threshold                830h */
+  __IO uint32_t DIEPEMPMSK;      /*!< dev empty msk                834h */
+  __IO uint32_t DEACHINT;        /*!< dedicated EP interrupt       838h */
+  __IO uint32_t DEACHMSK;        /*!< dedicated EP msk             83Ch */
+  uint32_t Reserved40;           /*!< dedicated EP mask            840h */
+  __IO uint32_t DINEP1MSK;       /*!< dedicated EP mask            844h */
+  uint32_t  Reserved44[15];      /*!< Reserved                 844-87Ch */
+  __IO uint32_t DOUTEP1MSK;      /*!< dedicated EP msk             884h */
+} USB_OTG_DeviceTypeDef;
+
+/** 
+  * @brief USB_OTG_IN_Endpoint-Specific_Register
+  */
+typedef struct 
+{
+  __IO uint32_t DIEPCTL;           /*!< dev IN Endpoint Control Reg    900h + (ep_num * 20h) + 00h */
+  uint32_t Reserved04;             /*!< Reserved                       900h + (ep_num * 20h) + 04h */
+  __IO uint32_t DIEPINT;           /*!< dev IN Endpoint Itr Reg        900h + (ep_num * 20h) + 08h */
+  uint32_t Reserved0C;             /*!< Reserved                       900h + (ep_num * 20h) + 0Ch */
+  __IO uint32_t DIEPTSIZ;          /*!< IN Endpoint Txfer Size         900h + (ep_num * 20h) + 10h */
+  __IO uint32_t DIEPDMA;           /*!< IN Endpoint DMA Address Reg    900h + (ep_num * 20h) + 14h */
+  __IO uint32_t DTXFSTS;           /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */
+  uint32_t Reserved18;             /*!< Reserved  900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */
+} USB_OTG_INEndpointTypeDef;
+
+/** 
+  * @brief USB_OTG_OUT_Endpoint-Specific_Registers
+  */
+typedef struct 
+{
+  __IO uint32_t DOEPCTL;       /*!< dev OUT Endpoint Control Reg           B00h + (ep_num * 20h) + 00h */
+  uint32_t Reserved04;         /*!< Reserved                               B00h + (ep_num * 20h) + 04h */
+  __IO uint32_t DOEPINT;       /*!< dev OUT Endpoint Itr Reg               B00h + (ep_num * 20h) + 08h */
+  uint32_t Reserved0C;         /*!< Reserved                               B00h + (ep_num * 20h) + 0Ch */
+  __IO uint32_t DOEPTSIZ;      /*!< dev OUT Endpoint Txfer Size            B00h + (ep_num * 20h) + 10h */
+  __IO uint32_t DOEPDMA;       /*!< dev OUT Endpoint DMA Address           B00h + (ep_num * 20h) + 14h */
+  uint32_t Reserved18[2];      /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */
+} USB_OTG_OUTEndpointTypeDef;
+
+/** 
+  * @brief USB_OTG_Host_Mode_Register_Structures
+  */
+typedef struct 
+{
+  __IO uint32_t HCFG;             /*!< Host Configuration Register          400h */
+  __IO uint32_t HFIR;             /*!< Host Frame Interval Register         404h */
+  __IO uint32_t HFNUM;            /*!< Host Frame Nbr/Frame Remaining       408h */
+  uint32_t Reserved40C;           /*!< Reserved                             40Ch */
+  __IO uint32_t HPTXSTS;          /*!< Host Periodic Tx FIFO/ Queue Status  410h */
+  __IO uint32_t HAINT;            /*!< Host All Channels Interrupt Register 414h */
+  __IO uint32_t HAINTMSK;         /*!< Host All Channels Interrupt Mask     418h */
+} USB_OTG_HostTypeDef;
+
+/** 
+  * @brief USB_OTG_Host_Channel_Specific_Registers
+  */
+typedef struct
+{
+  __IO uint32_t HCCHAR;           /*!< Host Channel Characteristics Register    500h */
+  __IO uint32_t HCSPLT;           /*!< Host Channel Split Control Register      504h */
+  __IO uint32_t HCINT;            /*!< Host Channel Interrupt Register          508h */
+  __IO uint32_t HCINTMSK;         /*!< Host Channel Interrupt Mask Register     50Ch */
+  __IO uint32_t HCTSIZ;           /*!< Host Channel Transfer Size Register      510h */
+  __IO uint32_t HCDMA;            /*!< Host Channel DMA Address Register        514h */
+  uint32_t Reserved[2];           /*!< Reserved                                      */
+} USB_OTG_HostChannelTypeDef;
+
+/**
+  * @}
+  */
+
+/** @addtogroup Peripheral_memory_map
+  * @{
+  */
+#define FLASH_BASE            0x08000000UL /*!< FLASH(up to 1 MB) base address in the alias region                         */
+#define CCMDATARAM_BASE       0x10000000UL /*!< CCM(core coupled memory) data RAM(64 KB) base address in the alias region  */
+#define SRAM1_BASE            0x20000000UL /*!< SRAM1(160 KB) base address in the alias region                             */
+#define SRAM2_BASE            0x20028000UL /*!< SRAM2(32 KB) base address in the alias region                              */
+#define SRAM3_BASE            0x20030000UL /*!< SRAM3(128 KB) base address in the alias region                              */
+#define PERIPH_BASE           0x40000000UL /*!< Peripheral base address in the alias region                                */
+#define BKPSRAM_BASE          0x40024000UL /*!< Backup SRAM(4 KB) base address in the alias region                         */
+#define FMC_R_BASE            0xA0000000UL /*!< FMC registers base address                                                 */
+#define QSPI_R_BASE           0xA0001000UL /*!< QuadSPI registers base address                                             */
+#define SRAM1_BB_BASE         0x22000000UL /*!< SRAM1(112 KB) base address in the bit-band region                          */
+#define SRAM2_BB_BASE         0x22500000UL /*!< SRAM2(16 KB) base address in the bit-band region                           */
+#define SRAM3_BB_BASE         0x22600000UL /*!< SRAM3(64 KB) base address in the bit-band region                           */
+#define PERIPH_BB_BASE        0x42000000UL /*!< Peripheral base address in the bit-band region                             */
+#define BKPSRAM_BB_BASE       0x42480000UL /*!< Backup SRAM(4 KB) base address in the bit-band region                      */
+#define FLASH_END             0x081FFFFFUL /*!< FLASH end address                                                          */
+#define FLASH_OTP_BASE        0x1FFF7800UL /*!< Base address of : (up to 528 Bytes) embedded FLASH OTP Area                */
+#define FLASH_OTP_END         0x1FFF7A0FUL /*!< End address of : (up to 528 Bytes) embedded FLASH OTP Area                 */
+#define CCMDATARAM_END        0x1000FFFFUL /*!< CCM data RAM end address                                                   */
+
+/* Legacy defines */
+#define SRAM_BASE             SRAM1_BASE
+#define SRAM_BB_BASE          SRAM1_BB_BASE
+
+/*!< Peripheral memory map */
+#define APB1PERIPH_BASE       PERIPH_BASE
+#define APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000UL)
+#define AHB1PERIPH_BASE       (PERIPH_BASE + 0x00020000UL)
+#define AHB2PERIPH_BASE       (PERIPH_BASE + 0x10000000UL)
+
+/*!< APB1 peripherals */
+#define TIM2_BASE             (APB1PERIPH_BASE + 0x0000UL)
+#define TIM3_BASE             (APB1PERIPH_BASE + 0x0400UL)
+#define TIM4_BASE             (APB1PERIPH_BASE + 0x0800UL)
+#define TIM5_BASE             (APB1PERIPH_BASE + 0x0C00UL)
+#define TIM6_BASE             (APB1PERIPH_BASE + 0x1000UL)
+#define TIM7_BASE             (APB1PERIPH_BASE + 0x1400UL)
+#define TIM12_BASE            (APB1PERIPH_BASE + 0x1800UL)
+#define TIM13_BASE            (APB1PERIPH_BASE + 0x1C00UL)
+#define TIM14_BASE            (APB1PERIPH_BASE + 0x2000UL)
+#define RTC_BASE              (APB1PERIPH_BASE + 0x2800UL)
+#define WWDG_BASE             (APB1PERIPH_BASE + 0x2C00UL)
+#define IWDG_BASE             (APB1PERIPH_BASE + 0x3000UL)
+#define I2S2ext_BASE          (APB1PERIPH_BASE + 0x3400UL)
+#define SPI2_BASE             (APB1PERIPH_BASE + 0x3800UL)
+#define SPI3_BASE             (APB1PERIPH_BASE + 0x3C00UL)
+#define I2S3ext_BASE          (APB1PERIPH_BASE + 0x4000UL)
+#define USART2_BASE           (APB1PERIPH_BASE + 0x4400UL)
+#define USART3_BASE           (APB1PERIPH_BASE + 0x4800UL)
+#define UART4_BASE            (APB1PERIPH_BASE + 0x4C00UL)
+#define UART5_BASE            (APB1PERIPH_BASE + 0x5000UL)
+#define I2C1_BASE             (APB1PERIPH_BASE + 0x5400UL)
+#define I2C2_BASE             (APB1PERIPH_BASE + 0x5800UL)
+#define I2C3_BASE             (APB1PERIPH_BASE + 0x5C00UL)
+#define CAN1_BASE             (APB1PERIPH_BASE + 0x6400UL)
+#define CAN2_BASE             (APB1PERIPH_BASE + 0x6800UL)
+#define PWR_BASE              (APB1PERIPH_BASE + 0x7000UL)
+#define DAC_BASE              (APB1PERIPH_BASE + 0x7400UL)
+#define UART7_BASE            (APB1PERIPH_BASE + 0x7800UL)
+#define UART8_BASE            (APB1PERIPH_BASE + 0x7C00UL)
+
+/*!< APB2 peripherals */
+#define TIM1_BASE             (APB2PERIPH_BASE + 0x0000UL)
+#define TIM8_BASE             (APB2PERIPH_BASE + 0x0400UL)
+#define USART1_BASE           (APB2PERIPH_BASE + 0x1000UL)
+#define USART6_BASE           (APB2PERIPH_BASE + 0x1400UL)
+#define ADC1_BASE             (APB2PERIPH_BASE + 0x2000UL)
+#define ADC2_BASE             (APB2PERIPH_BASE + 0x2100UL)
+#define ADC3_BASE             (APB2PERIPH_BASE + 0x2200UL)
+#define ADC123_COMMON_BASE    (APB2PERIPH_BASE + 0x2300UL)
+/* Legacy define */
+#define ADC_BASE               ADC123_COMMON_BASE
+#define SDIO_BASE             (APB2PERIPH_BASE + 0x2C00UL)
+#define SPI1_BASE             (APB2PERIPH_BASE + 0x3000UL)
+#define SPI4_BASE             (APB2PERIPH_BASE + 0x3400UL)
+#define SYSCFG_BASE           (APB2PERIPH_BASE + 0x3800UL)
+#define EXTI_BASE             (APB2PERIPH_BASE + 0x3C00UL)
+#define TIM9_BASE             (APB2PERIPH_BASE + 0x4000UL)
+#define TIM10_BASE            (APB2PERIPH_BASE + 0x4400UL)
+#define TIM11_BASE            (APB2PERIPH_BASE + 0x4800UL)
+#define SPI5_BASE             (APB2PERIPH_BASE + 0x5000UL)
+#define SPI6_BASE             (APB2PERIPH_BASE + 0x5400UL)
+#define SAI1_BASE             (APB2PERIPH_BASE + 0x5800UL)
+#define SAI1_Block_A_BASE     (SAI1_BASE + 0x004UL)
+#define SAI1_Block_B_BASE     (SAI1_BASE + 0x024UL)
+#define LTDC_BASE             (APB2PERIPH_BASE + 0x6800UL)
+#define LTDC_Layer1_BASE      (LTDC_BASE + 0x84UL)
+#define LTDC_Layer2_BASE      (LTDC_BASE + 0x104UL)
+#define DSI_BASE              (APB2PERIPH_BASE + 0x6C00UL)
+
+/*!< AHB1 peripherals */
+#define GPIOA_BASE            (AHB1PERIPH_BASE + 0x0000UL)
+#define GPIOB_BASE            (AHB1PERIPH_BASE + 0x0400UL)
+#define GPIOC_BASE            (AHB1PERIPH_BASE + 0x0800UL)
+#define GPIOD_BASE            (AHB1PERIPH_BASE + 0x0C00UL)
+#define GPIOE_BASE            (AHB1PERIPH_BASE + 0x1000UL)
+#define GPIOF_BASE            (AHB1PERIPH_BASE + 0x1400UL)
+#define GPIOG_BASE            (AHB1PERIPH_BASE + 0x1800UL)
+#define GPIOH_BASE            (AHB1PERIPH_BASE + 0x1C00UL)
+#define GPIOI_BASE            (AHB1PERIPH_BASE + 0x2000UL)
+#define GPIOJ_BASE            (AHB1PERIPH_BASE + 0x2400UL)
+#define GPIOK_BASE            (AHB1PERIPH_BASE + 0x2800UL)
+#define CRC_BASE              (AHB1PERIPH_BASE + 0x3000UL)
+#define RCC_BASE              (AHB1PERIPH_BASE + 0x3800UL)
+#define FLASH_R_BASE          (AHB1PERIPH_BASE + 0x3C00UL)
+#define DMA1_BASE             (AHB1PERIPH_BASE + 0x6000UL)
+#define DMA1_Stream0_BASE     (DMA1_BASE + 0x010UL)
+#define DMA1_Stream1_BASE     (DMA1_BASE + 0x028UL)
+#define DMA1_Stream2_BASE     (DMA1_BASE + 0x040UL)
+#define DMA1_Stream3_BASE     (DMA1_BASE + 0x058UL)
+#define DMA1_Stream4_BASE     (DMA1_BASE + 0x070UL)
+#define DMA1_Stream5_BASE     (DMA1_BASE + 0x088UL)
+#define DMA1_Stream6_BASE     (DMA1_BASE + 0x0A0UL)
+#define DMA1_Stream7_BASE     (DMA1_BASE + 0x0B8UL)
+#define DMA2_BASE             (AHB1PERIPH_BASE + 0x6400UL)
+#define DMA2_Stream0_BASE     (DMA2_BASE + 0x010UL)
+#define DMA2_Stream1_BASE     (DMA2_BASE + 0x028UL)
+#define DMA2_Stream2_BASE     (DMA2_BASE + 0x040UL)
+#define DMA2_Stream3_BASE     (DMA2_BASE + 0x058UL)
+#define DMA2_Stream4_BASE     (DMA2_BASE + 0x070UL)
+#define DMA2_Stream5_BASE     (DMA2_BASE + 0x088UL)
+#define DMA2_Stream6_BASE     (DMA2_BASE + 0x0A0UL)
+#define DMA2_Stream7_BASE     (DMA2_BASE + 0x0B8UL)
+#define ETH_BASE              (AHB1PERIPH_BASE + 0x8000UL)
+#define ETH_MAC_BASE          (ETH_BASE)
+#define ETH_MMC_BASE          (ETH_BASE + 0x0100UL)
+#define ETH_PTP_BASE          (ETH_BASE + 0x0700UL)
+#define ETH_DMA_BASE          (ETH_BASE + 0x1000UL)
+#define DMA2D_BASE            (AHB1PERIPH_BASE + 0xB000UL)
+
+/*!< AHB2 peripherals */
+#define DCMI_BASE             (AHB2PERIPH_BASE + 0x50000UL)
+#define RNG_BASE              (AHB2PERIPH_BASE + 0x60800UL)
+
+/*!< FMC Bankx registers base address */
+#define FMC_Bank1_R_BASE      (FMC_R_BASE + 0x0000UL)
+#define FMC_Bank1E_R_BASE     (FMC_R_BASE + 0x0104UL)
+#define FMC_Bank3_R_BASE      (FMC_R_BASE + 0x0080UL)
+#define FMC_Bank5_6_R_BASE    (FMC_R_BASE + 0x0140UL)
+
+
+/*!< Debug MCU registers base address */
+#define DBGMCU_BASE           0xE0042000UL
+/*!< USB registers base address */
+#define USB_OTG_HS_PERIPH_BASE               0x40040000UL
+#define USB_OTG_FS_PERIPH_BASE               0x50000000UL
+
+#define USB_OTG_GLOBAL_BASE                  0x000UL
+#define USB_OTG_DEVICE_BASE                  0x800UL
+#define USB_OTG_IN_ENDPOINT_BASE             0x900UL
+#define USB_OTG_OUT_ENDPOINT_BASE            0xB00UL
+#define USB_OTG_EP_REG_SIZE                  0x20UL
+#define USB_OTG_HOST_BASE                    0x400UL
+#define USB_OTG_HOST_PORT_BASE               0x440UL
+#define USB_OTG_HOST_CHANNEL_BASE            0x500UL
+#define USB_OTG_HOST_CHANNEL_SIZE            0x20UL
+#define USB_OTG_PCGCCTL_BASE                 0xE00UL
+#define USB_OTG_FIFO_BASE                    0x1000UL
+#define USB_OTG_FIFO_SIZE                    0x1000UL
+
+#define UID_BASE                     0x1FFF7A10UL           /*!< Unique device ID register base address */
+#define FLASHSIZE_BASE               0x1FFF7A22UL           /*!< FLASH Size register base address       */
+#define PACKAGE_BASE                 0x1FFF7BF0UL           /*!< Package size register base address     */
+/**
+  * @}
+  */
+
+/** @addtogroup Peripheral_declaration
+  * @{
+  */  
+#define TIM2                ((TIM_TypeDef *) TIM2_BASE)
+#define TIM3                ((TIM_TypeDef *) TIM3_BASE)
+#define TIM4                ((TIM_TypeDef *) TIM4_BASE)
+#define TIM5                ((TIM_TypeDef *) TIM5_BASE)
+#define TIM6                ((TIM_TypeDef *) TIM6_BASE)
+#define TIM7                ((TIM_TypeDef *) TIM7_BASE)
+#define TIM12               ((TIM_TypeDef *) TIM12_BASE)
+#define TIM13               ((TIM_TypeDef *) TIM13_BASE)
+#define TIM14               ((TIM_TypeDef *) TIM14_BASE)
+#define RTC                 ((RTC_TypeDef *) RTC_BASE)
+#define WWDG                ((WWDG_TypeDef *) WWDG_BASE)
+#define IWDG                ((IWDG_TypeDef *) IWDG_BASE)
+#define I2S2ext             ((SPI_TypeDef *) I2S2ext_BASE)
+#define SPI2                ((SPI_TypeDef *) SPI2_BASE)
+#define SPI3                ((SPI_TypeDef *) SPI3_BASE)
+#define I2S3ext             ((SPI_TypeDef *) I2S3ext_BASE)
+#define USART2              ((USART_TypeDef *) USART2_BASE)
+#define USART3              ((USART_TypeDef *) USART3_BASE)
+#define UART4               ((USART_TypeDef *) UART4_BASE)
+#define UART5               ((USART_TypeDef *) UART5_BASE)
+#define I2C1                ((I2C_TypeDef *) I2C1_BASE)
+#define I2C2                ((I2C_TypeDef *) I2C2_BASE)
+#define I2C3                ((I2C_TypeDef *) I2C3_BASE)
+#define CAN1                ((CAN_TypeDef *) CAN1_BASE)
+#define CAN2                ((CAN_TypeDef *) CAN2_BASE)
+#define PWR                 ((PWR_TypeDef *) PWR_BASE)
+#define DAC1                ((DAC_TypeDef *) DAC_BASE)
+#define DAC                 ((DAC_TypeDef *) DAC_BASE) /* Kept for legacy purpose */
+#define UART7               ((USART_TypeDef *) UART7_BASE)
+#define UART8               ((USART_TypeDef *) UART8_BASE)
+#define TIM1                ((TIM_TypeDef *) TIM1_BASE)
+#define TIM8                ((TIM_TypeDef *) TIM8_BASE)
+#define USART1              ((USART_TypeDef *) USART1_BASE)
+#define USART6              ((USART_TypeDef *) USART6_BASE)
+#define ADC1                ((ADC_TypeDef *) ADC1_BASE)
+#define ADC2                ((ADC_TypeDef *) ADC2_BASE)
+#define ADC3                ((ADC_TypeDef *) ADC3_BASE)
+#define ADC123_COMMON       ((ADC_Common_TypeDef *) ADC123_COMMON_BASE)
+/* Legacy define */
+#define ADC                  ADC123_COMMON
+#define SDIO                ((SDIO_TypeDef *) SDIO_BASE)
+#define SPI1                ((SPI_TypeDef *) SPI1_BASE)
+#define SPI4                ((SPI_TypeDef *) SPI4_BASE)
+#define SYSCFG              ((SYSCFG_TypeDef *) SYSCFG_BASE)
+#define EXTI                ((EXTI_TypeDef *) EXTI_BASE)
+#define TIM9                ((TIM_TypeDef *) TIM9_BASE)
+#define TIM10               ((TIM_TypeDef *) TIM10_BASE)
+#define TIM11               ((TIM_TypeDef *) TIM11_BASE)
+#define SPI5                ((SPI_TypeDef *) SPI5_BASE)
+#define SPI6                ((SPI_TypeDef *) SPI6_BASE)
+#define SAI1                ((SAI_TypeDef *) SAI1_BASE)
+#define SAI1_Block_A        ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)
+#define SAI1_Block_B        ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)
+#define LTDC                ((LTDC_TypeDef *)LTDC_BASE)
+#define LTDC_Layer1         ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE)
+#define LTDC_Layer2         ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE)
+#define DSI                 ((DSI_TypeDef *)DSI_BASE)
+#define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)
+#define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)
+#define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)
+#define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)
+#define GPIOE               ((GPIO_TypeDef *) GPIOE_BASE)
+#define GPIOF               ((GPIO_TypeDef *) GPIOF_BASE)
+#define GPIOG               ((GPIO_TypeDef *) GPIOG_BASE)
+#define GPIOH               ((GPIO_TypeDef *) GPIOH_BASE)
+#define GPIOI               ((GPIO_TypeDef *) GPIOI_BASE)
+#define GPIOJ               ((GPIO_TypeDef *) GPIOJ_BASE)
+#define GPIOK               ((GPIO_TypeDef *) GPIOK_BASE)
+#define CRC                 ((CRC_TypeDef *) CRC_BASE)
+#define RCC                 ((RCC_TypeDef *) RCC_BASE)
+#define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)
+#define DMA1                ((DMA_TypeDef *) DMA1_BASE)
+#define DMA1_Stream0        ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
+#define DMA1_Stream1        ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
+#define DMA1_Stream2        ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
+#define DMA1_Stream3        ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
+#define DMA1_Stream4        ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
+#define DMA1_Stream5        ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
+#define DMA1_Stream6        ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
+#define DMA1_Stream7        ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
+#define DMA2                ((DMA_TypeDef *) DMA2_BASE)
+#define DMA2_Stream0        ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
+#define DMA2_Stream1        ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
+#define DMA2_Stream2        ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
+#define DMA2_Stream3        ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
+#define DMA2_Stream4        ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
+#define DMA2_Stream5        ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
+#define DMA2_Stream6        ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
+#define DMA2_Stream7        ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
+#define ETH                 ((ETH_TypeDef *) ETH_BASE)  
+#define DMA2D               ((DMA2D_TypeDef *)DMA2D_BASE)
+#define DCMI                ((DCMI_TypeDef *) DCMI_BASE)
+#define RNG                 ((RNG_TypeDef *) RNG_BASE)
+#define FMC_Bank1           ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)
+#define FMC_Bank1E          ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)
+#define FMC_Bank3           ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE)
+#define FMC_Bank5_6         ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE)
+#define QUADSPI             ((QUADSPI_TypeDef *) QSPI_R_BASE)
+#define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)
+#define USB_OTG_FS          ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
+#define USB_OTG_HS          ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_PERIPH_BASE)
+
+/**
+  * @}
+  */
+
+/** @addtogroup Exported_constants
+  * @{
+  */
+
+/** @addtogroup Hardware_Constant_Definition
+  * @{
+  */
+#define LSI_STARTUP_TIME                40U /*!< LSI Maximum startup time in us */
+/**
+  * @}
+  */
+
+  /** @addtogroup Peripheral_Registers_Bits_Definition
+  * @{
+  */
+    
+/******************************************************************************/
+/*                         Peripheral Registers_Bits_Definition               */
+/******************************************************************************/
+
+/******************************************************************************/
+/*                                                                            */
+/*                        Analog to Digital Converter                         */
+/*                                                                            */
+/******************************************************************************/
+/*
+ * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
+ */
+#define ADC_MULTIMODE_SUPPORT                                                  /*!<ADC Multimode feature available on specific devices */
+
+/********************  Bit definition for ADC_SR register  ********************/
+#define ADC_SR_AWD_Pos            (0U)                                         
+#define ADC_SR_AWD_Msk            (0x1UL << ADC_SR_AWD_Pos)                     /*!< 0x00000001 */
+#define ADC_SR_AWD                ADC_SR_AWD_Msk                               /*!<Analog watchdog flag */
+#define ADC_SR_EOC_Pos            (1U)                                         
+#define ADC_SR_EOC_Msk            (0x1UL << ADC_SR_EOC_Pos)                     /*!< 0x00000002 */
+#define ADC_SR_EOC                ADC_SR_EOC_Msk                               /*!<End of conversion */
+#define ADC_SR_JEOC_Pos           (2U)                                         
+#define ADC_SR_JEOC_Msk           (0x1UL << ADC_SR_JEOC_Pos)                    /*!< 0x00000004 */
+#define ADC_SR_JEOC               ADC_SR_JEOC_Msk                              /*!<Injected channel end of conversion */
+#define ADC_SR_JSTRT_Pos          (3U)                                         
+#define ADC_SR_JSTRT_Msk          (0x1UL << ADC_SR_JSTRT_Pos)                   /*!< 0x00000008 */
+#define ADC_SR_JSTRT              ADC_SR_JSTRT_Msk                             /*!<Injected channel Start flag */
+#define ADC_SR_STRT_Pos           (4U)                                         
+#define ADC_SR_STRT_Msk           (0x1UL << ADC_SR_STRT_Pos)                    /*!< 0x00000010 */
+#define ADC_SR_STRT               ADC_SR_STRT_Msk                              /*!<Regular channel Start flag */
+#define ADC_SR_OVR_Pos            (5U)                                         
+#define ADC_SR_OVR_Msk            (0x1UL << ADC_SR_OVR_Pos)                     /*!< 0x00000020 */
+#define ADC_SR_OVR                ADC_SR_OVR_Msk                               /*!<Overrun flag */
+
+/*******************  Bit definition for ADC_CR1 register  ********************/
+#define ADC_CR1_AWDCH_Pos         (0U)                                         
+#define ADC_CR1_AWDCH_Msk         (0x1FUL << ADC_CR1_AWDCH_Pos)                 /*!< 0x0000001F */
+#define ADC_CR1_AWDCH             ADC_CR1_AWDCH_Msk                            /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
+#define ADC_CR1_AWDCH_0           (0x01UL << ADC_CR1_AWDCH_Pos)                 /*!< 0x00000001 */
+#define ADC_CR1_AWDCH_1           (0x02UL << ADC_CR1_AWDCH_Pos)                 /*!< 0x00000002 */
+#define ADC_CR1_AWDCH_2           (0x04UL << ADC_CR1_AWDCH_Pos)                 /*!< 0x00000004 */
+#define ADC_CR1_AWDCH_3           (0x08UL << ADC_CR1_AWDCH_Pos)                 /*!< 0x00000008 */
+#define ADC_CR1_AWDCH_4           (0x10UL << ADC_CR1_AWDCH_Pos)                 /*!< 0x00000010 */
+#define ADC_CR1_EOCIE_Pos         (5U)                                         
+#define ADC_CR1_EOCIE_Msk         (0x1UL << ADC_CR1_EOCIE_Pos)                  /*!< 0x00000020 */
+#define ADC_CR1_EOCIE             ADC_CR1_EOCIE_Msk                            /*!<Interrupt enable for EOC */
+#define ADC_CR1_AWDIE_Pos         (6U)                                         
+#define ADC_CR1_AWDIE_Msk         (0x1UL << ADC_CR1_AWDIE_Pos)                  /*!< 0x00000040 */
+#define ADC_CR1_AWDIE             ADC_CR1_AWDIE_Msk                            /*!<AAnalog Watchdog interrupt enable */
+#define ADC_CR1_JEOCIE_Pos        (7U)                                         
+#define ADC_CR1_JEOCIE_Msk        (0x1UL << ADC_CR1_JEOCIE_Pos)                 /*!< 0x00000080 */
+#define ADC_CR1_JEOCIE            ADC_CR1_JEOCIE_Msk                           /*!<Interrupt enable for injected channels */
+#define ADC_CR1_SCAN_Pos          (8U)                                         
+#define ADC_CR1_SCAN_Msk          (0x1UL << ADC_CR1_SCAN_Pos)                   /*!< 0x00000100 */
+#define ADC_CR1_SCAN              ADC_CR1_SCAN_Msk                             /*!<Scan mode */
+#define ADC_CR1_AWDSGL_Pos        (9U)                                         
+#define ADC_CR1_AWDSGL_Msk        (0x1UL << ADC_CR1_AWDSGL_Pos)                 /*!< 0x00000200 */
+#define ADC_CR1_AWDSGL            ADC_CR1_AWDSGL_Msk                           /*!<Enable the watchdog on a single channel in scan mode */
+#define ADC_CR1_JAUTO_Pos         (10U)                                        
+#define ADC_CR1_JAUTO_Msk         (0x1UL << ADC_CR1_JAUTO_Pos)                  /*!< 0x00000400 */
+#define ADC_CR1_JAUTO             ADC_CR1_JAUTO_Msk                            /*!<Automatic injected group conversion */
+#define ADC_CR1_DISCEN_Pos        (11U)                                        
+#define ADC_CR1_DISCEN_Msk        (0x1UL << ADC_CR1_DISCEN_Pos)                 /*!< 0x00000800 */
+#define ADC_CR1_DISCEN            ADC_CR1_DISCEN_Msk                           /*!<Discontinuous mode on regular channels */
+#define ADC_CR1_JDISCEN_Pos       (12U)                                        
+#define ADC_CR1_JDISCEN_Msk       (0x1UL << ADC_CR1_JDISCEN_Pos)                /*!< 0x00001000 */
+#define ADC_CR1_JDISCEN           ADC_CR1_JDISCEN_Msk                          /*!<Discontinuous mode on injected channels */
+#define ADC_CR1_DISCNUM_Pos       (13U)                                        
+#define ADC_CR1_DISCNUM_Msk       (0x7UL << ADC_CR1_DISCNUM_Pos)                /*!< 0x0000E000 */
+#define ADC_CR1_DISCNUM           ADC_CR1_DISCNUM_Msk                          /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */
+#define ADC_CR1_DISCNUM_0         (0x1UL << ADC_CR1_DISCNUM_Pos)                /*!< 0x00002000 */
+#define ADC_CR1_DISCNUM_1         (0x2UL << ADC_CR1_DISCNUM_Pos)                /*!< 0x00004000 */
+#define ADC_CR1_DISCNUM_2         (0x4UL << ADC_CR1_DISCNUM_Pos)                /*!< 0x00008000 */
+#define ADC_CR1_JAWDEN_Pos        (22U)                                        
+#define ADC_CR1_JAWDEN_Msk        (0x1UL << ADC_CR1_JAWDEN_Pos)                 /*!< 0x00400000 */
+#define ADC_CR1_JAWDEN            ADC_CR1_JAWDEN_Msk                           /*!<Analog watchdog enable on injected channels */
+#define ADC_CR1_AWDEN_Pos         (23U)                                        
+#define ADC_CR1_AWDEN_Msk         (0x1UL << ADC_CR1_AWDEN_Pos)                  /*!< 0x00800000 */
+#define ADC_CR1_AWDEN             ADC_CR1_AWDEN_Msk                            /*!<Analog watchdog enable on regular channels */
+#define ADC_CR1_RES_Pos           (24U)                                        
+#define ADC_CR1_RES_Msk           (0x3UL << ADC_CR1_RES_Pos)                    /*!< 0x03000000 */
+#define ADC_CR1_RES               ADC_CR1_RES_Msk                              /*!<RES[2:0] bits (Resolution) */
+#define ADC_CR1_RES_0             (0x1UL << ADC_CR1_RES_Pos)                    /*!< 0x01000000 */
+#define ADC_CR1_RES_1             (0x2UL << ADC_CR1_RES_Pos)                    /*!< 0x02000000 */
+#define ADC_CR1_OVRIE_Pos         (26U)                                        
+#define ADC_CR1_OVRIE_Msk         (0x1UL << ADC_CR1_OVRIE_Pos)                  /*!< 0x04000000 */
+#define ADC_CR1_OVRIE             ADC_CR1_OVRIE_Msk                            /*!<overrun interrupt enable */
+  
+/*******************  Bit definition for ADC_CR2 register  ********************/
+#define ADC_CR2_ADON_Pos          (0U)                                         
+#define ADC_CR2_ADON_Msk          (0x1UL << ADC_CR2_ADON_Pos)                   /*!< 0x00000001 */
+#define ADC_CR2_ADON              ADC_CR2_ADON_Msk                             /*!<A/D Converter ON / OFF */
+#define ADC_CR2_CONT_Pos          (1U)                                         
+#define ADC_CR2_CONT_Msk          (0x1UL << ADC_CR2_CONT_Pos)                   /*!< 0x00000002 */
+#define ADC_CR2_CONT              ADC_CR2_CONT_Msk                             /*!<Continuous Conversion */
+#define ADC_CR2_DMA_Pos           (8U)                                         
+#define ADC_CR2_DMA_Msk           (0x1UL << ADC_CR2_DMA_Pos)                    /*!< 0x00000100 */
+#define ADC_CR2_DMA               ADC_CR2_DMA_Msk                              /*!<Direct Memory access mode */
+#define ADC_CR2_DDS_Pos           (9U)                                         
+#define ADC_CR2_DDS_Msk           (0x1UL << ADC_CR2_DDS_Pos)                    /*!< 0x00000200 */
+#define ADC_CR2_DDS               ADC_CR2_DDS_Msk                              /*!<DMA disable selection (Single ADC) */
+#define ADC_CR2_EOCS_Pos          (10U)                                        
+#define ADC_CR2_EOCS_Msk          (0x1UL << ADC_CR2_EOCS_Pos)                   /*!< 0x00000400 */
+#define ADC_CR2_EOCS              ADC_CR2_EOCS_Msk                             /*!<End of conversion selection */
+#define ADC_CR2_ALIGN_Pos         (11U)                                        
+#define ADC_CR2_ALIGN_Msk         (0x1UL << ADC_CR2_ALIGN_Pos)                  /*!< 0x00000800 */
+#define ADC_CR2_ALIGN             ADC_CR2_ALIGN_Msk                            /*!<Data Alignment */
+#define ADC_CR2_JEXTSEL_Pos       (16U)                                        
+#define ADC_CR2_JEXTSEL_Msk       (0xFUL << ADC_CR2_JEXTSEL_Pos)                /*!< 0x000F0000 */
+#define ADC_CR2_JEXTSEL           ADC_CR2_JEXTSEL_Msk                          /*!<JEXTSEL[3:0] bits (External event select for injected group) */
+#define ADC_CR2_JEXTSEL_0         (0x1UL << ADC_CR2_JEXTSEL_Pos)                /*!< 0x00010000 */
+#define ADC_CR2_JEXTSEL_1         (0x2UL << ADC_CR2_JEXTSEL_Pos)                /*!< 0x00020000 */
+#define ADC_CR2_JEXTSEL_2         (0x4UL << ADC_CR2_JEXTSEL_Pos)                /*!< 0x00040000 */
+#define ADC_CR2_JEXTSEL_3         (0x8UL << ADC_CR2_JEXTSEL_Pos)                /*!< 0x00080000 */
+#define ADC_CR2_JEXTEN_Pos        (20U)                                        
+#define ADC_CR2_JEXTEN_Msk        (0x3UL << ADC_CR2_JEXTEN_Pos)                 /*!< 0x00300000 */
+#define ADC_CR2_JEXTEN            ADC_CR2_JEXTEN_Msk                           /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */
+#define ADC_CR2_JEXTEN_0          (0x1UL << ADC_CR2_JEXTEN_Pos)                 /*!< 0x00100000 */
+#define ADC_CR2_JEXTEN_1          (0x2UL << ADC_CR2_JEXTEN_Pos)                 /*!< 0x00200000 */
+#define ADC_CR2_JSWSTART_Pos      (22U)                                        
+#define ADC_CR2_JSWSTART_Msk      (0x1UL << ADC_CR2_JSWSTART_Pos)               /*!< 0x00400000 */
+#define ADC_CR2_JSWSTART          ADC_CR2_JSWSTART_Msk                         /*!<Start Conversion of injected channels */
+#define ADC_CR2_EXTSEL_Pos        (24U)                                        
+#define ADC_CR2_EXTSEL_Msk        (0xFUL << ADC_CR2_EXTSEL_Pos)                 /*!< 0x0F000000 */
+#define ADC_CR2_EXTSEL            ADC_CR2_EXTSEL_Msk                           /*!<EXTSEL[3:0] bits (External Event Select for regular group) */
+#define ADC_CR2_EXTSEL_0          (0x1UL << ADC_CR2_EXTSEL_Pos)                 /*!< 0x01000000 */
+#define ADC_CR2_EXTSEL_1          (0x2UL << ADC_CR2_EXTSEL_Pos)                 /*!< 0x02000000 */
+#define ADC_CR2_EXTSEL_2          (0x4UL << ADC_CR2_EXTSEL_Pos)                 /*!< 0x04000000 */
+#define ADC_CR2_EXTSEL_3          (0x8UL << ADC_CR2_EXTSEL_Pos)                 /*!< 0x08000000 */
+#define ADC_CR2_EXTEN_Pos         (28U)                                        
+#define ADC_CR2_EXTEN_Msk         (0x3UL << ADC_CR2_EXTEN_Pos)                  /*!< 0x30000000 */
+#define ADC_CR2_EXTEN             ADC_CR2_EXTEN_Msk                            /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */
+#define ADC_CR2_EXTEN_0           (0x1UL << ADC_CR2_EXTEN_Pos)                  /*!< 0x10000000 */
+#define ADC_CR2_EXTEN_1           (0x2UL << ADC_CR2_EXTEN_Pos)                  /*!< 0x20000000 */
+#define ADC_CR2_SWSTART_Pos       (30U)                                        
+#define ADC_CR2_SWSTART_Msk       (0x1UL << ADC_CR2_SWSTART_Pos)                /*!< 0x40000000 */
+#define ADC_CR2_SWSTART           ADC_CR2_SWSTART_Msk                          /*!<Start Conversion of regular channels */
+
+/******************  Bit definition for ADC_SMPR1 register  *******************/
+#define ADC_SMPR1_SMP10_Pos       (0U)                                         
+#define ADC_SMPR1_SMP10_Msk       (0x7UL << ADC_SMPR1_SMP10_Pos)                /*!< 0x00000007 */
+#define ADC_SMPR1_SMP10           ADC_SMPR1_SMP10_Msk                          /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
+#define ADC_SMPR1_SMP10_0         (0x1UL << ADC_SMPR1_SMP10_Pos)                /*!< 0x00000001 */
+#define ADC_SMPR1_SMP10_1         (0x2UL << ADC_SMPR1_SMP10_Pos)                /*!< 0x00000002 */
+#define ADC_SMPR1_SMP10_2         (0x4UL << ADC_SMPR1_SMP10_Pos)                /*!< 0x00000004 */
+#define ADC_SMPR1_SMP11_Pos       (3U)                                         
+#define ADC_SMPR1_SMP11_Msk       (0x7UL << ADC_SMPR1_SMP11_Pos)                /*!< 0x00000038 */
+#define ADC_SMPR1_SMP11           ADC_SMPR1_SMP11_Msk                          /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
+#define ADC_SMPR1_SMP11_0         (0x1UL << ADC_SMPR1_SMP11_Pos)                /*!< 0x00000008 */
+#define ADC_SMPR1_SMP11_1         (0x2UL << ADC_SMPR1_SMP11_Pos)                /*!< 0x00000010 */
+#define ADC_SMPR1_SMP11_2         (0x4UL << ADC_SMPR1_SMP11_Pos)                /*!< 0x00000020 */
+#define ADC_SMPR1_SMP12_Pos       (6U)                                         
+#define ADC_SMPR1_SMP12_Msk       (0x7UL << ADC_SMPR1_SMP12_Pos)                /*!< 0x000001C0 */
+#define ADC_SMPR1_SMP12           ADC_SMPR1_SMP12_Msk                          /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
+#define ADC_SMPR1_SMP12_0         (0x1UL << ADC_SMPR1_SMP12_Pos)                /*!< 0x00000040 */
+#define ADC_SMPR1_SMP12_1         (0x2UL << ADC_SMPR1_SMP12_Pos)                /*!< 0x00000080 */
+#define ADC_SMPR1_SMP12_2         (0x4UL << ADC_SMPR1_SMP12_Pos)                /*!< 0x00000100 */
+#define ADC_SMPR1_SMP13_Pos       (9U)                                         
+#define ADC_SMPR1_SMP13_Msk       (0x7UL << ADC_SMPR1_SMP13_Pos)                /*!< 0x00000E00 */
+#define ADC_SMPR1_SMP13           ADC_SMPR1_SMP13_Msk                          /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
+#define ADC_SMPR1_SMP13_0         (0x1UL << ADC_SMPR1_SMP13_Pos)                /*!< 0x00000200 */
+#define ADC_SMPR1_SMP13_1         (0x2UL << ADC_SMPR1_SMP13_Pos)                /*!< 0x00000400 */
+#define ADC_SMPR1_SMP13_2         (0x4UL << ADC_SMPR1_SMP13_Pos)                /*!< 0x00000800 */
+#define ADC_SMPR1_SMP14_Pos       (12U)                                        
+#define ADC_SMPR1_SMP14_Msk       (0x7UL << ADC_SMPR1_SMP14_Pos)                /*!< 0x00007000 */
+#define ADC_SMPR1_SMP14           ADC_SMPR1_SMP14_Msk                          /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
+#define ADC_SMPR1_SMP14_0         (0x1UL << ADC_SMPR1_SMP14_Pos)                /*!< 0x00001000 */
+#define ADC_SMPR1_SMP14_1         (0x2UL << ADC_SMPR1_SMP14_Pos)                /*!< 0x00002000 */
+#define ADC_SMPR1_SMP14_2         (0x4UL << ADC_SMPR1_SMP14_Pos)                /*!< 0x00004000 */
+#define ADC_SMPR1_SMP15_Pos       (15U)                                        
+#define ADC_SMPR1_SMP15_Msk       (0x7UL << ADC_SMPR1_SMP15_Pos)                /*!< 0x00038000 */
+#define ADC_SMPR1_SMP15           ADC_SMPR1_SMP15_Msk                          /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
+#define ADC_SMPR1_SMP15_0         (0x1UL << ADC_SMPR1_SMP15_Pos)                /*!< 0x00008000 */
+#define ADC_SMPR1_SMP15_1         (0x2UL << ADC_SMPR1_SMP15_Pos)                /*!< 0x00010000 */
+#define ADC_SMPR1_SMP15_2         (0x4UL << ADC_SMPR1_SMP15_Pos)                /*!< 0x00020000 */
+#define ADC_SMPR1_SMP16_Pos       (18U)                                        
+#define ADC_SMPR1_SMP16_Msk       (0x7UL << ADC_SMPR1_SMP16_Pos)                /*!< 0x001C0000 */
+#define ADC_SMPR1_SMP16           ADC_SMPR1_SMP16_Msk                          /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
+#define ADC_SMPR1_SMP16_0         (0x1UL << ADC_SMPR1_SMP16_Pos)                /*!< 0x00040000 */
+#define ADC_SMPR1_SMP16_1         (0x2UL << ADC_SMPR1_SMP16_Pos)                /*!< 0x00080000 */
+#define ADC_SMPR1_SMP16_2         (0x4UL << ADC_SMPR1_SMP16_Pos)                /*!< 0x00100000 */
+#define ADC_SMPR1_SMP17_Pos       (21U)                                        
+#define ADC_SMPR1_SMP17_Msk       (0x7UL << ADC_SMPR1_SMP17_Pos)                /*!< 0x00E00000 */
+#define ADC_SMPR1_SMP17           ADC_SMPR1_SMP17_Msk                          /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
+#define ADC_SMPR1_SMP17_0         (0x1UL << ADC_SMPR1_SMP17_Pos)                /*!< 0x00200000 */
+#define ADC_SMPR1_SMP17_1         (0x2UL << ADC_SMPR1_SMP17_Pos)                /*!< 0x00400000 */
+#define ADC_SMPR1_SMP17_2         (0x4UL << ADC_SMPR1_SMP17_Pos)                /*!< 0x00800000 */
+#define ADC_SMPR1_SMP18_Pos       (24U)                                        
+#define ADC_SMPR1_SMP18_Msk       (0x7UL << ADC_SMPR1_SMP18_Pos)                /*!< 0x07000000 */
+#define ADC_SMPR1_SMP18           ADC_SMPR1_SMP18_Msk                          /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */
+#define ADC_SMPR1_SMP18_0         (0x1UL << ADC_SMPR1_SMP18_Pos)                /*!< 0x01000000 */
+#define ADC_SMPR1_SMP18_1         (0x2UL << ADC_SMPR1_SMP18_Pos)                /*!< 0x02000000 */
+#define ADC_SMPR1_SMP18_2         (0x4UL << ADC_SMPR1_SMP18_Pos)                /*!< 0x04000000 */
+
+/******************  Bit definition for ADC_SMPR2 register  *******************/
+#define ADC_SMPR2_SMP0_Pos        (0U)                                         
+#define ADC_SMPR2_SMP0_Msk        (0x7UL << ADC_SMPR2_SMP0_Pos)                 /*!< 0x00000007 */
+#define ADC_SMPR2_SMP0            ADC_SMPR2_SMP0_Msk                           /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
+#define ADC_SMPR2_SMP0_0          (0x1UL << ADC_SMPR2_SMP0_Pos)                 /*!< 0x00000001 */
+#define ADC_SMPR2_SMP0_1          (0x2UL << ADC_SMPR2_SMP0_Pos)                 /*!< 0x00000002 */
+#define ADC_SMPR2_SMP0_2          (0x4UL << ADC_SMPR2_SMP0_Pos)                 /*!< 0x00000004 */
+#define ADC_SMPR2_SMP1_Pos        (3U)                                         
+#define ADC_SMPR2_SMP1_Msk        (0x7UL << ADC_SMPR2_SMP1_Pos)                 /*!< 0x00000038 */
+#define ADC_SMPR2_SMP1            ADC_SMPR2_SMP1_Msk                           /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
+#define ADC_SMPR2_SMP1_0          (0x1UL << ADC_SMPR2_SMP1_Pos)                 /*!< 0x00000008 */
+#define ADC_SMPR2_SMP1_1          (0x2UL << ADC_SMPR2_SMP1_Pos)                 /*!< 0x00000010 */
+#define ADC_SMPR2_SMP1_2          (0x4UL << ADC_SMPR2_SMP1_Pos)                 /*!< 0x00000020 */
+#define ADC_SMPR2_SMP2_Pos        (6U)                                         
+#define ADC_SMPR2_SMP2_Msk        (0x7UL << ADC_SMPR2_SMP2_Pos)                 /*!< 0x000001C0 */
+#define ADC_SMPR2_SMP2            ADC_SMPR2_SMP2_Msk                           /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
+#define ADC_SMPR2_SMP2_0          (0x1UL << ADC_SMPR2_SMP2_Pos)                 /*!< 0x00000040 */
+#define ADC_SMPR2_SMP2_1          (0x2UL << ADC_SMPR2_SMP2_Pos)                 /*!< 0x00000080 */
+#define ADC_SMPR2_SMP2_2          (0x4UL << ADC_SMPR2_SMP2_Pos)                 /*!< 0x00000100 */
+#define ADC_SMPR2_SMP3_Pos        (9U)                                         
+#define ADC_SMPR2_SMP3_Msk        (0x7UL << ADC_SMPR2_SMP3_Pos)                 /*!< 0x00000E00 */
+#define ADC_SMPR2_SMP3            ADC_SMPR2_SMP3_Msk                           /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
+#define ADC_SMPR2_SMP3_0          (0x1UL << ADC_SMPR2_SMP3_Pos)                 /*!< 0x00000200 */
+#define ADC_SMPR2_SMP3_1          (0x2UL << ADC_SMPR2_SMP3_Pos)                 /*!< 0x00000400 */
+#define ADC_SMPR2_SMP3_2          (0x4UL << ADC_SMPR2_SMP3_Pos)                 /*!< 0x00000800 */
+#define ADC_SMPR2_SMP4_Pos        (12U)                                        
+#define ADC_SMPR2_SMP4_Msk        (0x7UL << ADC_SMPR2_SMP4_Pos)                 /*!< 0x00007000 */
+#define ADC_SMPR2_SMP4            ADC_SMPR2_SMP4_Msk                           /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
+#define ADC_SMPR2_SMP4_0          (0x1UL << ADC_SMPR2_SMP4_Pos)                 /*!< 0x00001000 */
+#define ADC_SMPR2_SMP4_1          (0x2UL << ADC_SMPR2_SMP4_Pos)                 /*!< 0x00002000 */
+#define ADC_SMPR2_SMP4_2          (0x4UL << ADC_SMPR2_SMP4_Pos)                 /*!< 0x00004000 */
+#define ADC_SMPR2_SMP5_Pos        (15U)                                        
+#define ADC_SMPR2_SMP5_Msk        (0x7UL << ADC_SMPR2_SMP5_Pos)                 /*!< 0x00038000 */
+#define ADC_SMPR2_SMP5            ADC_SMPR2_SMP5_Msk                           /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
+#define ADC_SMPR2_SMP5_0          (0x1UL << ADC_SMPR2_SMP5_Pos)                 /*!< 0x00008000 */
+#define ADC_SMPR2_SMP5_1          (0x2UL << ADC_SMPR2_SMP5_Pos)                 /*!< 0x00010000 */
+#define ADC_SMPR2_SMP5_2          (0x4UL << ADC_SMPR2_SMP5_Pos)                 /*!< 0x00020000 */
+#define ADC_SMPR2_SMP6_Pos        (18U)                                        
+#define ADC_SMPR2_SMP6_Msk        (0x7UL << ADC_SMPR2_SMP6_Pos)                 /*!< 0x001C0000 */
+#define ADC_SMPR2_SMP6            ADC_SMPR2_SMP6_Msk                           /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
+#define ADC_SMPR2_SMP6_0          (0x1UL << ADC_SMPR2_SMP6_Pos)                 /*!< 0x00040000 */
+#define ADC_SMPR2_SMP6_1          (0x2UL << ADC_SMPR2_SMP6_Pos)                 /*!< 0x00080000 */
+#define ADC_SMPR2_SMP6_2          (0x4UL << ADC_SMPR2_SMP6_Pos)                 /*!< 0x00100000 */
+#define ADC_SMPR2_SMP7_Pos        (21U)                                        
+#define ADC_SMPR2_SMP7_Msk        (0x7UL << ADC_SMPR2_SMP7_Pos)                 /*!< 0x00E00000 */
+#define ADC_SMPR2_SMP7            ADC_SMPR2_SMP7_Msk                           /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
+#define ADC_SMPR2_SMP7_0          (0x1UL << ADC_SMPR2_SMP7_Pos)                 /*!< 0x00200000 */
+#define ADC_SMPR2_SMP7_1          (0x2UL << ADC_SMPR2_SMP7_Pos)                 /*!< 0x00400000 */
+#define ADC_SMPR2_SMP7_2          (0x4UL << ADC_SMPR2_SMP7_Pos)                 /*!< 0x00800000 */
+#define ADC_SMPR2_SMP8_Pos        (24U)                                        
+#define ADC_SMPR2_SMP8_Msk        (0x7UL << ADC_SMPR2_SMP8_Pos)                 /*!< 0x07000000 */
+#define ADC_SMPR2_SMP8            ADC_SMPR2_SMP8_Msk                           /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
+#define ADC_SMPR2_SMP8_0          (0x1UL << ADC_SMPR2_SMP8_Pos)                 /*!< 0x01000000 */
+#define ADC_SMPR2_SMP8_1          (0x2UL << ADC_SMPR2_SMP8_Pos)                 /*!< 0x02000000 */
+#define ADC_SMPR2_SMP8_2          (0x4UL << ADC_SMPR2_SMP8_Pos)                 /*!< 0x04000000 */
+#define ADC_SMPR2_SMP9_Pos        (27U)                                        
+#define ADC_SMPR2_SMP9_Msk        (0x7UL << ADC_SMPR2_SMP9_Pos)                 /*!< 0x38000000 */
+#define ADC_SMPR2_SMP9            ADC_SMPR2_SMP9_Msk                           /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
+#define ADC_SMPR2_SMP9_0          (0x1UL << ADC_SMPR2_SMP9_Pos)                 /*!< 0x08000000 */
+#define ADC_SMPR2_SMP9_1          (0x2UL << ADC_SMPR2_SMP9_Pos)                 /*!< 0x10000000 */
+#define ADC_SMPR2_SMP9_2          (0x4UL << ADC_SMPR2_SMP9_Pos)                 /*!< 0x20000000 */
+
+/******************  Bit definition for ADC_JOFR1 register  *******************/
+#define ADC_JOFR1_JOFFSET1_Pos    (0U)                                         
+#define ADC_JOFR1_JOFFSET1_Msk    (0xFFFUL << ADC_JOFR1_JOFFSET1_Pos)           /*!< 0x00000FFF */
+#define ADC_JOFR1_JOFFSET1        ADC_JOFR1_JOFFSET1_Msk                       /*!<Data offset for injected channel 1 */
+
+/******************  Bit definition for ADC_JOFR2 register  *******************/
+#define ADC_JOFR2_JOFFSET2_Pos    (0U)                                         
+#define ADC_JOFR2_JOFFSET2_Msk    (0xFFFUL << ADC_JOFR2_JOFFSET2_Pos)           /*!< 0x00000FFF */
+#define ADC_JOFR2_JOFFSET2        ADC_JOFR2_JOFFSET2_Msk                       /*!<Data offset for injected channel 2 */
+
+/******************  Bit definition for ADC_JOFR3 register  *******************/
+#define ADC_JOFR3_JOFFSET3_Pos    (0U)                                         
+#define ADC_JOFR3_JOFFSET3_Msk    (0xFFFUL << ADC_JOFR3_JOFFSET3_Pos)           /*!< 0x00000FFF */
+#define ADC_JOFR3_JOFFSET3        ADC_JOFR3_JOFFSET3_Msk                       /*!<Data offset for injected channel 3 */
+
+/******************  Bit definition for ADC_JOFR4 register  *******************/
+#define ADC_JOFR4_JOFFSET4_Pos    (0U)                                         
+#define ADC_JOFR4_JOFFSET4_Msk    (0xFFFUL << ADC_JOFR4_JOFFSET4_Pos)           /*!< 0x00000FFF */
+#define ADC_JOFR4_JOFFSET4        ADC_JOFR4_JOFFSET4_Msk                       /*!<Data offset for injected channel 4 */
+
+/*******************  Bit definition for ADC_HTR register  ********************/
+#define ADC_HTR_HT_Pos            (0U)                                         
+#define ADC_HTR_HT_Msk            (0xFFFUL << ADC_HTR_HT_Pos)                   /*!< 0x00000FFF */
+#define ADC_HTR_HT                ADC_HTR_HT_Msk                               /*!<Analog watchdog high threshold */
+
+/*******************  Bit definition for ADC_LTR register  ********************/
+#define ADC_LTR_LT_Pos            (0U)                                         
+#define ADC_LTR_LT_Msk            (0xFFFUL << ADC_LTR_LT_Pos)                   /*!< 0x00000FFF */
+#define ADC_LTR_LT                ADC_LTR_LT_Msk                               /*!<Analog watchdog low threshold */
+
+/*******************  Bit definition for ADC_SQR1 register  *******************/
+#define ADC_SQR1_SQ13_Pos         (0U)                                         
+#define ADC_SQR1_SQ13_Msk         (0x1FUL << ADC_SQR1_SQ13_Pos)                 /*!< 0x0000001F */
+#define ADC_SQR1_SQ13             ADC_SQR1_SQ13_Msk                            /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
+#define ADC_SQR1_SQ13_0           (0x01UL << ADC_SQR1_SQ13_Pos)                 /*!< 0x00000001 */
+#define ADC_SQR1_SQ13_1           (0x02UL << ADC_SQR1_SQ13_Pos)                 /*!< 0x00000002 */
+#define ADC_SQR1_SQ13_2           (0x04UL << ADC_SQR1_SQ13_Pos)                 /*!< 0x00000004 */
+#define ADC_SQR1_SQ13_3           (0x08UL << ADC_SQR1_SQ13_Pos)                 /*!< 0x00000008 */
+#define ADC_SQR1_SQ13_4           (0x10UL << ADC_SQR1_SQ13_Pos)                 /*!< 0x00000010 */
+#define ADC_SQR1_SQ14_Pos         (5U)                                         
+#define ADC_SQR1_SQ14_Msk         (0x1FUL << ADC_SQR1_SQ14_Pos)                 /*!< 0x000003E0 */
+#define ADC_SQR1_SQ14             ADC_SQR1_SQ14_Msk                            /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
+#define ADC_SQR1_SQ14_0           (0x01UL << ADC_SQR1_SQ14_Pos)                 /*!< 0x00000020 */
+#define ADC_SQR1_SQ14_1           (0x02UL << ADC_SQR1_SQ14_Pos)                 /*!< 0x00000040 */
+#define ADC_SQR1_SQ14_2           (0x04UL << ADC_SQR1_SQ14_Pos)                 /*!< 0x00000080 */
+#define ADC_SQR1_SQ14_3           (0x08UL << ADC_SQR1_SQ14_Pos)                 /*!< 0x00000100 */
+#define ADC_SQR1_SQ14_4           (0x10UL << ADC_SQR1_SQ14_Pos)                 /*!< 0x00000200 */
+#define ADC_SQR1_SQ15_Pos         (10U)                                        
+#define ADC_SQR1_SQ15_Msk         (0x1FUL << ADC_SQR1_SQ15_Pos)                 /*!< 0x00007C00 */
+#define ADC_SQR1_SQ15             ADC_SQR1_SQ15_Msk                            /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
+#define ADC_SQR1_SQ15_0           (0x01UL << ADC_SQR1_SQ15_Pos)                 /*!< 0x00000400 */
+#define ADC_SQR1_SQ15_1           (0x02UL << ADC_SQR1_SQ15_Pos)                 /*!< 0x00000800 */
+#define ADC_SQR1_SQ15_2           (0x04UL << ADC_SQR1_SQ15_Pos)                 /*!< 0x00001000 */
+#define ADC_SQR1_SQ15_3           (0x08UL << ADC_SQR1_SQ15_Pos)                 /*!< 0x00002000 */
+#define ADC_SQR1_SQ15_4           (0x10UL << ADC_SQR1_SQ15_Pos)                 /*!< 0x00004000 */
+#define ADC_SQR1_SQ16_Pos         (15U)                                        
+#define ADC_SQR1_SQ16_Msk         (0x1FUL << ADC_SQR1_SQ16_Pos)                 /*!< 0x000F8000 */
+#define ADC_SQR1_SQ16             ADC_SQR1_SQ16_Msk                            /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
+#define ADC_SQR1_SQ16_0           (0x01UL << ADC_SQR1_SQ16_Pos)                 /*!< 0x00008000 */
+#define ADC_SQR1_SQ16_1           (0x02UL << ADC_SQR1_SQ16_Pos)                 /*!< 0x00010000 */
+#define ADC_SQR1_SQ16_2           (0x04UL << ADC_SQR1_SQ16_Pos)                 /*!< 0x00020000 */
+#define ADC_SQR1_SQ16_3           (0x08UL << ADC_SQR1_SQ16_Pos)                 /*!< 0x00040000 */
+#define ADC_SQR1_SQ16_4           (0x10UL << ADC_SQR1_SQ16_Pos)                 /*!< 0x00080000 */
+#define ADC_SQR1_L_Pos            (20U)                                        
+#define ADC_SQR1_L_Msk            (0xFUL << ADC_SQR1_L_Pos)                     /*!< 0x00F00000 */
+#define ADC_SQR1_L                ADC_SQR1_L_Msk                               /*!<L[3:0] bits (Regular channel sequence length) */
+#define ADC_SQR1_L_0              (0x1UL << ADC_SQR1_L_Pos)                     /*!< 0x00100000 */
+#define ADC_SQR1_L_1              (0x2UL << ADC_SQR1_L_Pos)                     /*!< 0x00200000 */
+#define ADC_SQR1_L_2              (0x4UL << ADC_SQR1_L_Pos)                     /*!< 0x00400000 */
+#define ADC_SQR1_L_3              (0x8UL << ADC_SQR1_L_Pos)                     /*!< 0x00800000 */
+
+/*******************  Bit definition for ADC_SQR2 register  *******************/
+#define ADC_SQR2_SQ7_Pos          (0U)                                         
+#define ADC_SQR2_SQ7_Msk          (0x1FUL << ADC_SQR2_SQ7_Pos)                  /*!< 0x0000001F */
+#define ADC_SQR2_SQ7              ADC_SQR2_SQ7_Msk                             /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
+#define ADC_SQR2_SQ7_0            (0x01UL << ADC_SQR2_SQ7_Pos)                  /*!< 0x00000001 */
+#define ADC_SQR2_SQ7_1            (0x02UL << ADC_SQR2_SQ7_Pos)                  /*!< 0x00000002 */
+#define ADC_SQR2_SQ7_2            (0x04UL << ADC_SQR2_SQ7_Pos)                  /*!< 0x00000004 */
+#define ADC_SQR2_SQ7_3            (0x08UL << ADC_SQR2_SQ7_Pos)                  /*!< 0x00000008 */
+#define ADC_SQR2_SQ7_4            (0x10UL << ADC_SQR2_SQ7_Pos)                  /*!< 0x00000010 */
+#define ADC_SQR2_SQ8_Pos          (5U)                                         
+#define ADC_SQR2_SQ8_Msk          (0x1FUL << ADC_SQR2_SQ8_Pos)                  /*!< 0x000003E0 */
+#define ADC_SQR2_SQ8              ADC_SQR2_SQ8_Msk                             /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
+#define ADC_SQR2_SQ8_0            (0x01UL << ADC_SQR2_SQ8_Pos)                  /*!< 0x00000020 */
+#define ADC_SQR2_SQ8_1            (0x02UL << ADC_SQR2_SQ8_Pos)                  /*!< 0x00000040 */
+#define ADC_SQR2_SQ8_2            (0x04UL << ADC_SQR2_SQ8_Pos)                  /*!< 0x00000080 */
+#define ADC_SQR2_SQ8_3            (0x08UL << ADC_SQR2_SQ8_Pos)                  /*!< 0x00000100 */
+#define ADC_SQR2_SQ8_4            (0x10UL << ADC_SQR2_SQ8_Pos)                  /*!< 0x00000200 */
+#define ADC_SQR2_SQ9_Pos          (10U)                                        
+#define ADC_SQR2_SQ9_Msk          (0x1FUL << ADC_SQR2_SQ9_Pos)                  /*!< 0x00007C00 */
+#define ADC_SQR2_SQ9              ADC_SQR2_SQ9_Msk                             /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
+#define ADC_SQR2_SQ9_0            (0x01UL << ADC_SQR2_SQ9_Pos)                  /*!< 0x00000400 */
+#define ADC_SQR2_SQ9_1            (0x02UL << ADC_SQR2_SQ9_Pos)                  /*!< 0x00000800 */
+#define ADC_SQR2_SQ9_2            (0x04UL << ADC_SQR2_SQ9_Pos)                  /*!< 0x00001000 */
+#define ADC_SQR2_SQ9_3            (0x08UL << ADC_SQR2_SQ9_Pos)                  /*!< 0x00002000 */
+#define ADC_SQR2_SQ9_4            (0x10UL << ADC_SQR2_SQ9_Pos)                  /*!< 0x00004000 */
+#define ADC_SQR2_SQ10_Pos         (15U)                                        
+#define ADC_SQR2_SQ10_Msk         (0x1FUL << ADC_SQR2_SQ10_Pos)                 /*!< 0x000F8000 */
+#define ADC_SQR2_SQ10             ADC_SQR2_SQ10_Msk                            /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
+#define ADC_SQR2_SQ10_0           (0x01UL << ADC_SQR2_SQ10_Pos)                 /*!< 0x00008000 */
+#define ADC_SQR2_SQ10_1           (0x02UL << ADC_SQR2_SQ10_Pos)                 /*!< 0x00010000 */
+#define ADC_SQR2_SQ10_2           (0x04UL << ADC_SQR2_SQ10_Pos)                 /*!< 0x00020000 */
+#define ADC_SQR2_SQ10_3           (0x08UL << ADC_SQR2_SQ10_Pos)                 /*!< 0x00040000 */
+#define ADC_SQR2_SQ10_4           (0x10UL << ADC_SQR2_SQ10_Pos)                 /*!< 0x00080000 */
+#define ADC_SQR2_SQ11_Pos         (20U)                                        
+#define ADC_SQR2_SQ11_Msk         (0x1FUL << ADC_SQR2_SQ11_Pos)                 /*!< 0x01F00000 */
+#define ADC_SQR2_SQ11             ADC_SQR2_SQ11_Msk                            /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
+#define ADC_SQR2_SQ11_0           (0x01UL << ADC_SQR2_SQ11_Pos)                 /*!< 0x00100000 */
+#define ADC_SQR2_SQ11_1           (0x02UL << ADC_SQR2_SQ11_Pos)                 /*!< 0x00200000 */
+#define ADC_SQR2_SQ11_2           (0x04UL << ADC_SQR2_SQ11_Pos)                 /*!< 0x00400000 */
+#define ADC_SQR2_SQ11_3           (0x08UL << ADC_SQR2_SQ11_Pos)                 /*!< 0x00800000 */
+#define ADC_SQR2_SQ11_4           (0x10UL << ADC_SQR2_SQ11_Pos)                 /*!< 0x01000000 */
+#define ADC_SQR2_SQ12_Pos         (25U)                                        
+#define ADC_SQR2_SQ12_Msk         (0x1FUL << ADC_SQR2_SQ12_Pos)                 /*!< 0x3E000000 */
+#define ADC_SQR2_SQ12             ADC_SQR2_SQ12_Msk                            /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
+#define ADC_SQR2_SQ12_0           (0x01UL << ADC_SQR2_SQ12_Pos)                 /*!< 0x02000000 */
+#define ADC_SQR2_SQ12_1           (0x02UL << ADC_SQR2_SQ12_Pos)                 /*!< 0x04000000 */
+#define ADC_SQR2_SQ12_2           (0x04UL << ADC_SQR2_SQ12_Pos)                 /*!< 0x08000000 */
+#define ADC_SQR2_SQ12_3           (0x08UL << ADC_SQR2_SQ12_Pos)                 /*!< 0x10000000 */
+#define ADC_SQR2_SQ12_4           (0x10UL << ADC_SQR2_SQ12_Pos)                 /*!< 0x20000000 */
+
+/*******************  Bit definition for ADC_SQR3 register  *******************/
+#define ADC_SQR3_SQ1_Pos          (0U)                                         
+#define ADC_SQR3_SQ1_Msk          (0x1FUL << ADC_SQR3_SQ1_Pos)                  /*!< 0x0000001F */
+#define ADC_SQR3_SQ1              ADC_SQR3_SQ1_Msk                             /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
+#define ADC_SQR3_SQ1_0            (0x01UL << ADC_SQR3_SQ1_Pos)                  /*!< 0x00000001 */
+#define ADC_SQR3_SQ1_1            (0x02UL << ADC_SQR3_SQ1_Pos)                  /*!< 0x00000002 */
+#define ADC_SQR3_SQ1_2            (0x04UL << ADC_SQR3_SQ1_Pos)                  /*!< 0x00000004 */
+#define ADC_SQR3_SQ1_3            (0x08UL << ADC_SQR3_SQ1_Pos)                  /*!< 0x00000008 */
+#define ADC_SQR3_SQ1_4            (0x10UL << ADC_SQR3_SQ1_Pos)                  /*!< 0x00000010 */
+#define ADC_SQR3_SQ2_Pos          (5U)                                         
+#define ADC_SQR3_SQ2_Msk          (0x1FUL << ADC_SQR3_SQ2_Pos)                  /*!< 0x000003E0 */
+#define ADC_SQR3_SQ2              ADC_SQR3_SQ2_Msk                             /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
+#define ADC_SQR3_SQ2_0            (0x01UL << ADC_SQR3_SQ2_Pos)                  /*!< 0x00000020 */
+#define ADC_SQR3_SQ2_1            (0x02UL << ADC_SQR3_SQ2_Pos)                  /*!< 0x00000040 */
+#define ADC_SQR3_SQ2_2            (0x04UL << ADC_SQR3_SQ2_Pos)                  /*!< 0x00000080 */
+#define ADC_SQR3_SQ2_3            (0x08UL << ADC_SQR3_SQ2_Pos)                  /*!< 0x00000100 */
+#define ADC_SQR3_SQ2_4            (0x10UL << ADC_SQR3_SQ2_Pos)                  /*!< 0x00000200 */
+#define ADC_SQR3_SQ3_Pos          (10U)                                        
+#define ADC_SQR3_SQ3_Msk          (0x1FUL << ADC_SQR3_SQ3_Pos)                  /*!< 0x00007C00 */
+#define ADC_SQR3_SQ3              ADC_SQR3_SQ3_Msk                             /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
+#define ADC_SQR3_SQ3_0            (0x01UL << ADC_SQR3_SQ3_Pos)                  /*!< 0x00000400 */
+#define ADC_SQR3_SQ3_1            (0x02UL << ADC_SQR3_SQ3_Pos)                  /*!< 0x00000800 */
+#define ADC_SQR3_SQ3_2            (0x04UL << ADC_SQR3_SQ3_Pos)                  /*!< 0x00001000 */
+#define ADC_SQR3_SQ3_3            (0x08UL << ADC_SQR3_SQ3_Pos)                  /*!< 0x00002000 */
+#define ADC_SQR3_SQ3_4            (0x10UL << ADC_SQR3_SQ3_Pos)                  /*!< 0x00004000 */
+#define ADC_SQR3_SQ4_Pos          (15U)                                        
+#define ADC_SQR3_SQ4_Msk          (0x1FUL << ADC_SQR3_SQ4_Pos)                  /*!< 0x000F8000 */
+#define ADC_SQR3_SQ4              ADC_SQR3_SQ4_Msk                             /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
+#define ADC_SQR3_SQ4_0            (0x01UL << ADC_SQR3_SQ4_Pos)                  /*!< 0x00008000 */
+#define ADC_SQR3_SQ4_1            (0x02UL << ADC_SQR3_SQ4_Pos)                  /*!< 0x00010000 */
+#define ADC_SQR3_SQ4_2            (0x04UL << ADC_SQR3_SQ4_Pos)                  /*!< 0x00020000 */
+#define ADC_SQR3_SQ4_3            (0x08UL << ADC_SQR3_SQ4_Pos)                  /*!< 0x00040000 */
+#define ADC_SQR3_SQ4_4            (0x10UL << ADC_SQR3_SQ4_Pos)                  /*!< 0x00080000 */
+#define ADC_SQR3_SQ5_Pos          (20U)                                        
+#define ADC_SQR3_SQ5_Msk          (0x1FUL << ADC_SQR3_SQ5_Pos)                  /*!< 0x01F00000 */
+#define ADC_SQR3_SQ5              ADC_SQR3_SQ5_Msk                             /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
+#define ADC_SQR3_SQ5_0            (0x01UL << ADC_SQR3_SQ5_Pos)                  /*!< 0x00100000 */
+#define ADC_SQR3_SQ5_1            (0x02UL << ADC_SQR3_SQ5_Pos)                  /*!< 0x00200000 */
+#define ADC_SQR3_SQ5_2            (0x04UL << ADC_SQR3_SQ5_Pos)                  /*!< 0x00400000 */
+#define ADC_SQR3_SQ5_3            (0x08UL << ADC_SQR3_SQ5_Pos)                  /*!< 0x00800000 */
+#define ADC_SQR3_SQ5_4            (0x10UL << ADC_SQR3_SQ5_Pos)                  /*!< 0x01000000 */
+#define ADC_SQR3_SQ6_Pos          (25U)                                        
+#define ADC_SQR3_SQ6_Msk          (0x1FUL << ADC_SQR3_SQ6_Pos)                  /*!< 0x3E000000 */
+#define ADC_SQR3_SQ6              ADC_SQR3_SQ6_Msk                             /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
+#define ADC_SQR3_SQ6_0            (0x01UL << ADC_SQR3_SQ6_Pos)                  /*!< 0x02000000 */
+#define ADC_SQR3_SQ6_1            (0x02UL << ADC_SQR3_SQ6_Pos)                  /*!< 0x04000000 */
+#define ADC_SQR3_SQ6_2            (0x04UL << ADC_SQR3_SQ6_Pos)                  /*!< 0x08000000 */
+#define ADC_SQR3_SQ6_3            (0x08UL << ADC_SQR3_SQ6_Pos)                  /*!< 0x10000000 */
+#define ADC_SQR3_SQ6_4            (0x10UL << ADC_SQR3_SQ6_Pos)                  /*!< 0x20000000 */
+
+/*******************  Bit definition for ADC_JSQR register  *******************/
+#define ADC_JSQR_JSQ1_Pos         (0U)                                         
+#define ADC_JSQR_JSQ1_Msk         (0x1FUL << ADC_JSQR_JSQ1_Pos)                 /*!< 0x0000001F */
+#define ADC_JSQR_JSQ1             ADC_JSQR_JSQ1_Msk                            /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */  
+#define ADC_JSQR_JSQ1_0           (0x01UL << ADC_JSQR_JSQ1_Pos)                 /*!< 0x00000001 */
+#define ADC_JSQR_JSQ1_1           (0x02UL << ADC_JSQR_JSQ1_Pos)                 /*!< 0x00000002 */
+#define ADC_JSQR_JSQ1_2           (0x04UL << ADC_JSQR_JSQ1_Pos)                 /*!< 0x00000004 */
+#define ADC_JSQR_JSQ1_3           (0x08UL << ADC_JSQR_JSQ1_Pos)                 /*!< 0x00000008 */
+#define ADC_JSQR_JSQ1_4           (0x10UL << ADC_JSQR_JSQ1_Pos)                 /*!< 0x00000010 */
+#define ADC_JSQR_JSQ2_Pos         (5U)                                         
+#define ADC_JSQR_JSQ2_Msk         (0x1FUL << ADC_JSQR_JSQ2_Pos)                 /*!< 0x000003E0 */
+#define ADC_JSQR_JSQ2             ADC_JSQR_JSQ2_Msk                            /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
+#define ADC_JSQR_JSQ2_0           (0x01UL << ADC_JSQR_JSQ2_Pos)                 /*!< 0x00000020 */
+#define ADC_JSQR_JSQ2_1           (0x02UL << ADC_JSQR_JSQ2_Pos)                 /*!< 0x00000040 */
+#define ADC_JSQR_JSQ2_2           (0x04UL << ADC_JSQR_JSQ2_Pos)                 /*!< 0x00000080 */
+#define ADC_JSQR_JSQ2_3           (0x08UL << ADC_JSQR_JSQ2_Pos)                 /*!< 0x00000100 */
+#define ADC_JSQR_JSQ2_4           (0x10UL << ADC_JSQR_JSQ2_Pos)                 /*!< 0x00000200 */
+#define ADC_JSQR_JSQ3_Pos         (10U)                                        
+#define ADC_JSQR_JSQ3_Msk         (0x1FUL << ADC_JSQR_JSQ3_Pos)                 /*!< 0x00007C00 */
+#define ADC_JSQR_JSQ3             ADC_JSQR_JSQ3_Msk                            /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
+#define ADC_JSQR_JSQ3_0           (0x01UL << ADC_JSQR_JSQ3_Pos)                 /*!< 0x00000400 */
+#define ADC_JSQR_JSQ3_1           (0x02UL << ADC_JSQR_JSQ3_Pos)                 /*!< 0x00000800 */
+#define ADC_JSQR_JSQ3_2           (0x04UL << ADC_JSQR_JSQ3_Pos)                 /*!< 0x00001000 */
+#define ADC_JSQR_JSQ3_3           (0x08UL << ADC_JSQR_JSQ3_Pos)                 /*!< 0x00002000 */
+#define ADC_JSQR_JSQ3_4           (0x10UL << ADC_JSQR_JSQ3_Pos)                 /*!< 0x00004000 */
+#define ADC_JSQR_JSQ4_Pos         (15U)                                        
+#define ADC_JSQR_JSQ4_Msk         (0x1FUL << ADC_JSQR_JSQ4_Pos)                 /*!< 0x000F8000 */
+#define ADC_JSQR_JSQ4             ADC_JSQR_JSQ4_Msk                            /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
+#define ADC_JSQR_JSQ4_0           (0x01UL << ADC_JSQR_JSQ4_Pos)                 /*!< 0x00008000 */
+#define ADC_JSQR_JSQ4_1           (0x02UL << ADC_JSQR_JSQ4_Pos)                 /*!< 0x00010000 */
+#define ADC_JSQR_JSQ4_2           (0x04UL << ADC_JSQR_JSQ4_Pos)                 /*!< 0x00020000 */
+#define ADC_JSQR_JSQ4_3           (0x08UL << ADC_JSQR_JSQ4_Pos)                 /*!< 0x00040000 */
+#define ADC_JSQR_JSQ4_4           (0x10UL << ADC_JSQR_JSQ4_Pos)                 /*!< 0x00080000 */
+#define ADC_JSQR_JL_Pos           (20U)                                        
+#define ADC_JSQR_JL_Msk           (0x3UL << ADC_JSQR_JL_Pos)                    /*!< 0x00300000 */
+#define ADC_JSQR_JL               ADC_JSQR_JL_Msk                              /*!<JL[1:0] bits (Injected Sequence length) */
+#define ADC_JSQR_JL_0             (0x1UL << ADC_JSQR_JL_Pos)                    /*!< 0x00100000 */
+#define ADC_JSQR_JL_1             (0x2UL << ADC_JSQR_JL_Pos)                    /*!< 0x00200000 */
+
+/*******************  Bit definition for ADC_JDR1 register  *******************/
+#define ADC_JDR1_JDATA_Pos        (0U)                                         
+#define ADC_JDR1_JDATA_Msk        (0xFFFFUL << ADC_JDR1_JDATA_Pos)              /*!< 0x0000FFFF */
+#define ADC_JDR1_JDATA            ADC_JDR1_JDATA_Msk                           /*!<Injected data */
+
+/*******************  Bit definition for ADC_JDR2 register  *******************/
+#define ADC_JDR2_JDATA_Pos        (0U)                                         
+#define ADC_JDR2_JDATA_Msk        (0xFFFFUL << ADC_JDR2_JDATA_Pos)              /*!< 0x0000FFFF */
+#define ADC_JDR2_JDATA            ADC_JDR2_JDATA_Msk                           /*!<Injected data */
+
+/*******************  Bit definition for ADC_JDR3 register  *******************/
+#define ADC_JDR3_JDATA_Pos        (0U)                                         
+#define ADC_JDR3_JDATA_Msk        (0xFFFFUL << ADC_JDR3_JDATA_Pos)              /*!< 0x0000FFFF */
+#define ADC_JDR3_JDATA            ADC_JDR3_JDATA_Msk                           /*!<Injected data */
+
+/*******************  Bit definition for ADC_JDR4 register  *******************/
+#define ADC_JDR4_JDATA_Pos        (0U)                                         
+#define ADC_JDR4_JDATA_Msk        (0xFFFFUL << ADC_JDR4_JDATA_Pos)              /*!< 0x0000FFFF */
+#define ADC_JDR4_JDATA            ADC_JDR4_JDATA_Msk                           /*!<Injected data */
+
+/********************  Bit definition for ADC_DR register  ********************/
+#define ADC_DR_DATA_Pos           (0U)                                         
+#define ADC_DR_DATA_Msk           (0xFFFFUL << ADC_DR_DATA_Pos)                 /*!< 0x0000FFFF */
+#define ADC_DR_DATA               ADC_DR_DATA_Msk                              /*!<Regular data */
+#define ADC_DR_ADC2DATA_Pos       (16U)                                        
+#define ADC_DR_ADC2DATA_Msk       (0xFFFFUL << ADC_DR_ADC2DATA_Pos)             /*!< 0xFFFF0000 */
+#define ADC_DR_ADC2DATA           ADC_DR_ADC2DATA_Msk                          /*!<ADC2 data */
+
+/*******************  Bit definition for ADC_CSR register  ********************/
+#define ADC_CSR_AWD1_Pos          (0U)                                         
+#define ADC_CSR_AWD1_Msk          (0x1UL << ADC_CSR_AWD1_Pos)                   /*!< 0x00000001 */
+#define ADC_CSR_AWD1              ADC_CSR_AWD1_Msk                             /*!<ADC1 Analog watchdog flag */
+#define ADC_CSR_EOC1_Pos          (1U)                                         
+#define ADC_CSR_EOC1_Msk          (0x1UL << ADC_CSR_EOC1_Pos)                   /*!< 0x00000002 */
+#define ADC_CSR_EOC1              ADC_CSR_EOC1_Msk                             /*!<ADC1 End of conversion */
+#define ADC_CSR_JEOC1_Pos         (2U)                                         
+#define ADC_CSR_JEOC1_Msk         (0x1UL << ADC_CSR_JEOC1_Pos)                  /*!< 0x00000004 */
+#define ADC_CSR_JEOC1             ADC_CSR_JEOC1_Msk                            /*!<ADC1 Injected channel end of conversion */
+#define ADC_CSR_JSTRT1_Pos        (3U)                                         
+#define ADC_CSR_JSTRT1_Msk        (0x1UL << ADC_CSR_JSTRT1_Pos)                 /*!< 0x00000008 */
+#define ADC_CSR_JSTRT1            ADC_CSR_JSTRT1_Msk                           /*!<ADC1 Injected channel Start flag */
+#define ADC_CSR_STRT1_Pos         (4U)                                         
+#define ADC_CSR_STRT1_Msk         (0x1UL << ADC_CSR_STRT1_Pos)                  /*!< 0x00000010 */
+#define ADC_CSR_STRT1             ADC_CSR_STRT1_Msk                            /*!<ADC1 Regular channel Start flag */
+#define ADC_CSR_OVR1_Pos          (5U)                                         
+#define ADC_CSR_OVR1_Msk          (0x1UL << ADC_CSR_OVR1_Pos)                   /*!< 0x00000020 */
+#define ADC_CSR_OVR1              ADC_CSR_OVR1_Msk                             /*!<ADC1 DMA overrun  flag */
+#define ADC_CSR_AWD2_Pos          (8U)                                         
+#define ADC_CSR_AWD2_Msk          (0x1UL << ADC_CSR_AWD2_Pos)                   /*!< 0x00000100 */
+#define ADC_CSR_AWD2              ADC_CSR_AWD2_Msk                             /*!<ADC2 Analog watchdog flag */
+#define ADC_CSR_EOC2_Pos          (9U)                                         
+#define ADC_CSR_EOC2_Msk          (0x1UL << ADC_CSR_EOC2_Pos)                   /*!< 0x00000200 */
+#define ADC_CSR_EOC2              ADC_CSR_EOC2_Msk                             /*!<ADC2 End of conversion */
+#define ADC_CSR_JEOC2_Pos         (10U)                                        
+#define ADC_CSR_JEOC2_Msk         (0x1UL << ADC_CSR_JEOC2_Pos)                  /*!< 0x00000400 */
+#define ADC_CSR_JEOC2             ADC_CSR_JEOC2_Msk                            /*!<ADC2 Injected channel end of conversion */
+#define ADC_CSR_JSTRT2_Pos        (11U)                                        
+#define ADC_CSR_JSTRT2_Msk        (0x1UL << ADC_CSR_JSTRT2_Pos)                 /*!< 0x00000800 */
+#define ADC_CSR_JSTRT2            ADC_CSR_JSTRT2_Msk                           /*!<ADC2 Injected channel Start flag */
+#define ADC_CSR_STRT2_Pos         (12U)                                        
+#define ADC_CSR_STRT2_Msk         (0x1UL << ADC_CSR_STRT2_Pos)                  /*!< 0x00001000 */
+#define ADC_CSR_STRT2             ADC_CSR_STRT2_Msk                            /*!<ADC2 Regular channel Start flag */
+#define ADC_CSR_OVR2_Pos          (13U)                                        
+#define ADC_CSR_OVR2_Msk          (0x1UL << ADC_CSR_OVR2_Pos)                   /*!< 0x00002000 */
+#define ADC_CSR_OVR2              ADC_CSR_OVR2_Msk                             /*!<ADC2 DMA overrun  flag */
+#define ADC_CSR_AWD3_Pos          (16U)                                        
+#define ADC_CSR_AWD3_Msk          (0x1UL << ADC_CSR_AWD3_Pos)                   /*!< 0x00010000 */
+#define ADC_CSR_AWD3              ADC_CSR_AWD3_Msk                             /*!<ADC3 Analog watchdog flag */
+#define ADC_CSR_EOC3_Pos          (17U)                                        
+#define ADC_CSR_EOC3_Msk          (0x1UL << ADC_CSR_EOC3_Pos)                   /*!< 0x00020000 */
+#define ADC_CSR_EOC3              ADC_CSR_EOC3_Msk                             /*!<ADC3 End of conversion */
+#define ADC_CSR_JEOC3_Pos         (18U)                                        
+#define ADC_CSR_JEOC3_Msk         (0x1UL << ADC_CSR_JEOC3_Pos)                  /*!< 0x00040000 */
+#define ADC_CSR_JEOC3             ADC_CSR_JEOC3_Msk                            /*!<ADC3 Injected channel end of conversion */
+#define ADC_CSR_JSTRT3_Pos        (19U)                                        
+#define ADC_CSR_JSTRT3_Msk        (0x1UL << ADC_CSR_JSTRT3_Pos)                 /*!< 0x00080000 */
+#define ADC_CSR_JSTRT3            ADC_CSR_JSTRT3_Msk                           /*!<ADC3 Injected channel Start flag */
+#define ADC_CSR_STRT3_Pos         (20U)                                        
+#define ADC_CSR_STRT3_Msk         (0x1UL << ADC_CSR_STRT3_Pos)                  /*!< 0x00100000 */
+#define ADC_CSR_STRT3             ADC_CSR_STRT3_Msk                            /*!<ADC3 Regular channel Start flag */
+#define ADC_CSR_OVR3_Pos          (21U)                                        
+#define ADC_CSR_OVR3_Msk          (0x1UL << ADC_CSR_OVR3_Pos)                   /*!< 0x00200000 */
+#define ADC_CSR_OVR3              ADC_CSR_OVR3_Msk                             /*!<ADC3 DMA overrun  flag */
+
+/* Legacy defines */
+#define  ADC_CSR_DOVR1                        ADC_CSR_OVR1
+#define  ADC_CSR_DOVR2                        ADC_CSR_OVR2
+#define  ADC_CSR_DOVR3                        ADC_CSR_OVR3
+
+/*******************  Bit definition for ADC_CCR register  ********************/
+#define ADC_CCR_MULTI_Pos         (0U)                                         
+#define ADC_CCR_MULTI_Msk         (0x1FUL << ADC_CCR_MULTI_Pos)                 /*!< 0x0000001F */
+#define ADC_CCR_MULTI             ADC_CCR_MULTI_Msk                            /*!<MULTI[4:0] bits (Multi-ADC mode selection) */  
+#define ADC_CCR_MULTI_0           (0x01UL << ADC_CCR_MULTI_Pos)                 /*!< 0x00000001 */
+#define ADC_CCR_MULTI_1           (0x02UL << ADC_CCR_MULTI_Pos)                 /*!< 0x00000002 */
+#define ADC_CCR_MULTI_2           (0x04UL << ADC_CCR_MULTI_Pos)                 /*!< 0x00000004 */
+#define ADC_CCR_MULTI_3           (0x08UL << ADC_CCR_MULTI_Pos)                 /*!< 0x00000008 */
+#define ADC_CCR_MULTI_4           (0x10UL << ADC_CCR_MULTI_Pos)                 /*!< 0x00000010 */
+#define ADC_CCR_DELAY_Pos         (8U)                                         
+#define ADC_CCR_DELAY_Msk         (0xFUL << ADC_CCR_DELAY_Pos)                  /*!< 0x00000F00 */
+#define ADC_CCR_DELAY             ADC_CCR_DELAY_Msk                            /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */  
+#define ADC_CCR_DELAY_0           (0x1UL << ADC_CCR_DELAY_Pos)                  /*!< 0x00000100 */
+#define ADC_CCR_DELAY_1           (0x2UL << ADC_CCR_DELAY_Pos)                  /*!< 0x00000200 */
+#define ADC_CCR_DELAY_2           (0x4UL << ADC_CCR_DELAY_Pos)                  /*!< 0x00000400 */
+#define ADC_CCR_DELAY_3           (0x8UL << ADC_CCR_DELAY_Pos)                  /*!< 0x00000800 */
+#define ADC_CCR_DDS_Pos           (13U)                                        
+#define ADC_CCR_DDS_Msk           (0x1UL << ADC_CCR_DDS_Pos)                    /*!< 0x00002000 */
+#define ADC_CCR_DDS               ADC_CCR_DDS_Msk                              /*!<DMA disable selection (Multi-ADC mode) */
+#define ADC_CCR_DMA_Pos           (14U)                                        
+#define ADC_CCR_DMA_Msk           (0x3UL << ADC_CCR_DMA_Pos)                    /*!< 0x0000C000 */
+#define ADC_CCR_DMA               ADC_CCR_DMA_Msk                              /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */  
+#define ADC_CCR_DMA_0             (0x1UL << ADC_CCR_DMA_Pos)                    /*!< 0x00004000 */
+#define ADC_CCR_DMA_1             (0x2UL << ADC_CCR_DMA_Pos)                    /*!< 0x00008000 */
+#define ADC_CCR_ADCPRE_Pos        (16U)                                        
+#define ADC_CCR_ADCPRE_Msk        (0x3UL << ADC_CCR_ADCPRE_Pos)                 /*!< 0x00030000 */
+#define ADC_CCR_ADCPRE            ADC_CCR_ADCPRE_Msk                           /*!<ADCPRE[1:0] bits (ADC prescaler) */  
+#define ADC_CCR_ADCPRE_0          (0x1UL << ADC_CCR_ADCPRE_Pos)                 /*!< 0x00010000 */
+#define ADC_CCR_ADCPRE_1          (0x2UL << ADC_CCR_ADCPRE_Pos)                 /*!< 0x00020000 */
+#define ADC_CCR_VBATE_Pos         (22U)                                        
+#define ADC_CCR_VBATE_Msk         (0x1UL << ADC_CCR_VBATE_Pos)                  /*!< 0x00400000 */
+#define ADC_CCR_VBATE             ADC_CCR_VBATE_Msk                            /*!<VBAT Enable */
+#define ADC_CCR_TSVREFE_Pos       (23U)                                        
+#define ADC_CCR_TSVREFE_Msk       (0x1UL << ADC_CCR_TSVREFE_Pos)                /*!< 0x00800000 */
+#define ADC_CCR_TSVREFE           ADC_CCR_TSVREFE_Msk                          /*!<Temperature Sensor and VREFINT Enable */
+
+/*******************  Bit definition for ADC_CDR register  ********************/
+#define ADC_CDR_DATA1_Pos         (0U)                                         
+#define ADC_CDR_DATA1_Msk         (0xFFFFUL << ADC_CDR_DATA1_Pos)               /*!< 0x0000FFFF */
+#define ADC_CDR_DATA1             ADC_CDR_DATA1_Msk                            /*!<1st data of a pair of regular conversions */
+#define ADC_CDR_DATA2_Pos         (16U)                                        
+#define ADC_CDR_DATA2_Msk         (0xFFFFUL << ADC_CDR_DATA2_Pos)               /*!< 0xFFFF0000 */
+#define ADC_CDR_DATA2             ADC_CDR_DATA2_Msk                            /*!<2nd data of a pair of regular conversions */
+
+/* Legacy defines */
+#define ADC_CDR_RDATA_MST         ADC_CDR_DATA1
+#define ADC_CDR_RDATA_SLV         ADC_CDR_DATA2
+
+/******************************************************************************/
+/*                                                                            */
+/*                         Controller Area Network                            */
+/*                                                                            */
+/******************************************************************************/
+/*!<CAN control and status registers */
+/*******************  Bit definition for CAN_MCR register  ********************/
+#define CAN_MCR_INRQ_Pos       (0U)                                            
+#define CAN_MCR_INRQ_Msk       (0x1UL << CAN_MCR_INRQ_Pos)                      /*!< 0x00000001 */
+#define CAN_MCR_INRQ           CAN_MCR_INRQ_Msk                                /*!<Initialization Request */
+#define CAN_MCR_SLEEP_Pos      (1U)                                            
+#define CAN_MCR_SLEEP_Msk      (0x1UL << CAN_MCR_SLEEP_Pos)                     /*!< 0x00000002 */
+#define CAN_MCR_SLEEP          CAN_MCR_SLEEP_Msk                               /*!<Sleep Mode Request */
+#define CAN_MCR_TXFP_Pos       (2U)                                            
+#define CAN_MCR_TXFP_Msk       (0x1UL << CAN_MCR_TXFP_Pos)                      /*!< 0x00000004 */
+#define CAN_MCR_TXFP           CAN_MCR_TXFP_Msk                                /*!<Transmit FIFO Priority */
+#define CAN_MCR_RFLM_Pos       (3U)                                            
+#define CAN_MCR_RFLM_Msk       (0x1UL << CAN_MCR_RFLM_Pos)                      /*!< 0x00000008 */
+#define CAN_MCR_RFLM           CAN_MCR_RFLM_Msk                                /*!<Receive FIFO Locked Mode */
+#define CAN_MCR_NART_Pos       (4U)                                            
+#define CAN_MCR_NART_Msk       (0x1UL << CAN_MCR_NART_Pos)                      /*!< 0x00000010 */
+#define CAN_MCR_NART           CAN_MCR_NART_Msk                                /*!<No Automatic Retransmission */
+#define CAN_MCR_AWUM_Pos       (5U)                                            
+#define CAN_MCR_AWUM_Msk       (0x1UL << CAN_MCR_AWUM_Pos)                      /*!< 0x00000020 */
+#define CAN_MCR_AWUM           CAN_MCR_AWUM_Msk                                /*!<Automatic Wakeup Mode */
+#define CAN_MCR_ABOM_Pos       (6U)                                            
+#define CAN_MCR_ABOM_Msk       (0x1UL << CAN_MCR_ABOM_Pos)                      /*!< 0x00000040 */
+#define CAN_MCR_ABOM           CAN_MCR_ABOM_Msk                                /*!<Automatic Bus-Off Management */
+#define CAN_MCR_TTCM_Pos       (7U)                                            
+#define CAN_MCR_TTCM_Msk       (0x1UL << CAN_MCR_TTCM_Pos)                      /*!< 0x00000080 */
+#define CAN_MCR_TTCM           CAN_MCR_TTCM_Msk                                /*!<Time Triggered Communication Mode */
+#define CAN_MCR_RESET_Pos      (15U)                                           
+#define CAN_MCR_RESET_Msk      (0x1UL << CAN_MCR_RESET_Pos)                     /*!< 0x00008000 */
+#define CAN_MCR_RESET          CAN_MCR_RESET_Msk                               /*!<bxCAN software master reset */
+#define CAN_MCR_DBF_Pos        (16U)                                           
+#define CAN_MCR_DBF_Msk        (0x1UL << CAN_MCR_DBF_Pos)                       /*!< 0x00010000 */
+#define CAN_MCR_DBF            CAN_MCR_DBF_Msk                                 /*!<bxCAN Debug freeze */
+/*******************  Bit definition for CAN_MSR register  ********************/
+#define CAN_MSR_INAK_Pos       (0U)                                            
+#define CAN_MSR_INAK_Msk       (0x1UL << CAN_MSR_INAK_Pos)                      /*!< 0x00000001 */
+#define CAN_MSR_INAK           CAN_MSR_INAK_Msk                                /*!<Initialization Acknowledge */
+#define CAN_MSR_SLAK_Pos       (1U)                                            
+#define CAN_MSR_SLAK_Msk       (0x1UL << CAN_MSR_SLAK_Pos)                      /*!< 0x00000002 */
+#define CAN_MSR_SLAK           CAN_MSR_SLAK_Msk                                /*!<Sleep Acknowledge */
+#define CAN_MSR_ERRI_Pos       (2U)                                            
+#define CAN_MSR_ERRI_Msk       (0x1UL << CAN_MSR_ERRI_Pos)                      /*!< 0x00000004 */
+#define CAN_MSR_ERRI           CAN_MSR_ERRI_Msk                                /*!<Error Interrupt */
+#define CAN_MSR_WKUI_Pos       (3U)                                            
+#define CAN_MSR_WKUI_Msk       (0x1UL << CAN_MSR_WKUI_Pos)                      /*!< 0x00000008 */
+#define CAN_MSR_WKUI           CAN_MSR_WKUI_Msk                                /*!<Wakeup Interrupt */
+#define CAN_MSR_SLAKI_Pos      (4U)                                            
+#define CAN_MSR_SLAKI_Msk      (0x1UL << CAN_MSR_SLAKI_Pos)                     /*!< 0x00000010 */
+#define CAN_MSR_SLAKI          CAN_MSR_SLAKI_Msk                               /*!<Sleep Acknowledge Interrupt */
+#define CAN_MSR_TXM_Pos        (8U)                                            
+#define CAN_MSR_TXM_Msk        (0x1UL << CAN_MSR_TXM_Pos)                       /*!< 0x00000100 */
+#define CAN_MSR_TXM            CAN_MSR_TXM_Msk                                 /*!<Transmit Mode */
+#define CAN_MSR_RXM_Pos        (9U)                                            
+#define CAN_MSR_RXM_Msk        (0x1UL << CAN_MSR_RXM_Pos)                       /*!< 0x00000200 */
+#define CAN_MSR_RXM            CAN_MSR_RXM_Msk                                 /*!<Receive Mode */
+#define CAN_MSR_SAMP_Pos       (10U)                                           
+#define CAN_MSR_SAMP_Msk       (0x1UL << CAN_MSR_SAMP_Pos)                      /*!< 0x00000400 */
+#define CAN_MSR_SAMP           CAN_MSR_SAMP_Msk                                /*!<Last Sample Point */
+#define CAN_MSR_RX_Pos         (11U)                                           
+#define CAN_MSR_RX_Msk         (0x1UL << CAN_MSR_RX_Pos)                        /*!< 0x00000800 */
+#define CAN_MSR_RX             CAN_MSR_RX_Msk                                  /*!<CAN Rx Signal */
+
+/*******************  Bit definition for CAN_TSR register  ********************/
+#define CAN_TSR_RQCP0_Pos      (0U)                                            
+#define CAN_TSR_RQCP0_Msk      (0x1UL << CAN_TSR_RQCP0_Pos)                     /*!< 0x00000001 */
+#define CAN_TSR_RQCP0          CAN_TSR_RQCP0_Msk                               /*!<Request Completed Mailbox0 */
+#define CAN_TSR_TXOK0_Pos      (1U)                                            
+#define CAN_TSR_TXOK0_Msk      (0x1UL << CAN_TSR_TXOK0_Pos)                     /*!< 0x00000002 */
+#define CAN_TSR_TXOK0          CAN_TSR_TXOK0_Msk                               /*!<Transmission OK of Mailbox0 */
+#define CAN_TSR_ALST0_Pos      (2U)                                            
+#define CAN_TSR_ALST0_Msk      (0x1UL << CAN_TSR_ALST0_Pos)                     /*!< 0x00000004 */
+#define CAN_TSR_ALST0          CAN_TSR_ALST0_Msk                               /*!<Arbitration Lost for Mailbox0 */
+#define CAN_TSR_TERR0_Pos      (3U)                                            
+#define CAN_TSR_TERR0_Msk      (0x1UL << CAN_TSR_TERR0_Pos)                     /*!< 0x00000008 */
+#define CAN_TSR_TERR0          CAN_TSR_TERR0_Msk                               /*!<Transmission Error of Mailbox0 */
+#define CAN_TSR_ABRQ0_Pos      (7U)                                            
+#define CAN_TSR_ABRQ0_Msk      (0x1UL << CAN_TSR_ABRQ0_Pos)                     /*!< 0x00000080 */
+#define CAN_TSR_ABRQ0          CAN_TSR_ABRQ0_Msk                               /*!<Abort Request for Mailbox0 */
+#define CAN_TSR_RQCP1_Pos      (8U)                                            
+#define CAN_TSR_RQCP1_Msk      (0x1UL << CAN_TSR_RQCP1_Pos)                     /*!< 0x00000100 */
+#define CAN_TSR_RQCP1          CAN_TSR_RQCP1_Msk                               /*!<Request Completed Mailbox1 */
+#define CAN_TSR_TXOK1_Pos      (9U)                                            
+#define CAN_TSR_TXOK1_Msk      (0x1UL << CAN_TSR_TXOK1_Pos)                     /*!< 0x00000200 */
+#define CAN_TSR_TXOK1          CAN_TSR_TXOK1_Msk                               /*!<Transmission OK of Mailbox1 */
+#define CAN_TSR_ALST1_Pos      (10U)                                           
+#define CAN_TSR_ALST1_Msk      (0x1UL << CAN_TSR_ALST1_Pos)                     /*!< 0x00000400 */
+#define CAN_TSR_ALST1          CAN_TSR_ALST1_Msk                               /*!<Arbitration Lost for Mailbox1 */
+#define CAN_TSR_TERR1_Pos      (11U)                                           
+#define CAN_TSR_TERR1_Msk      (0x1UL << CAN_TSR_TERR1_Pos)                     /*!< 0x00000800 */
+#define CAN_TSR_TERR1          CAN_TSR_TERR1_Msk                               /*!<Transmission Error of Mailbox1 */
+#define CAN_TSR_ABRQ1_Pos      (15U)                                           
+#define CAN_TSR_ABRQ1_Msk      (0x1UL << CAN_TSR_ABRQ1_Pos)                     /*!< 0x00008000 */
+#define CAN_TSR_ABRQ1          CAN_TSR_ABRQ1_Msk                               /*!<Abort Request for Mailbox 1 */
+#define CAN_TSR_RQCP2_Pos      (16U)                                           
+#define CAN_TSR_RQCP2_Msk      (0x1UL << CAN_TSR_RQCP2_Pos)                     /*!< 0x00010000 */
+#define CAN_TSR_RQCP2          CAN_TSR_RQCP2_Msk                               /*!<Request Completed Mailbox2 */
+#define CAN_TSR_TXOK2_Pos      (17U)                                           
+#define CAN_TSR_TXOK2_Msk      (0x1UL << CAN_TSR_TXOK2_Pos)                     /*!< 0x00020000 */
+#define CAN_TSR_TXOK2          CAN_TSR_TXOK2_Msk                               /*!<Transmission OK of Mailbox 2 */
+#define CAN_TSR_ALST2_Pos      (18U)                                           
+#define CAN_TSR_ALST2_Msk      (0x1UL << CAN_TSR_ALST2_Pos)                     /*!< 0x00040000 */
+#define CAN_TSR_ALST2          CAN_TSR_ALST2_Msk                               /*!<Arbitration Lost for mailbox 2 */
+#define CAN_TSR_TERR2_Pos      (19U)                                           
+#define CAN_TSR_TERR2_Msk      (0x1UL << CAN_TSR_TERR2_Pos)                     /*!< 0x00080000 */
+#define CAN_TSR_TERR2          CAN_TSR_TERR2_Msk                               /*!<Transmission Error of Mailbox 2 */
+#define CAN_TSR_ABRQ2_Pos      (23U)                                           
+#define CAN_TSR_ABRQ2_Msk      (0x1UL << CAN_TSR_ABRQ2_Pos)                     /*!< 0x00800000 */
+#define CAN_TSR_ABRQ2          CAN_TSR_ABRQ2_Msk                               /*!<Abort Request for Mailbox 2 */
+#define CAN_TSR_CODE_Pos       (24U)                                           
+#define CAN_TSR_CODE_Msk       (0x3UL << CAN_TSR_CODE_Pos)                      /*!< 0x03000000 */
+#define CAN_TSR_CODE           CAN_TSR_CODE_Msk                                /*!<Mailbox Code */
+
+#define CAN_TSR_TME_Pos        (26U)                                           
+#define CAN_TSR_TME_Msk        (0x7UL << CAN_TSR_TME_Pos)                       /*!< 0x1C000000 */
+#define CAN_TSR_TME            CAN_TSR_TME_Msk                                 /*!<TME[2:0] bits */
+#define CAN_TSR_TME0_Pos       (26U)                                           
+#define CAN_TSR_TME0_Msk       (0x1UL << CAN_TSR_TME0_Pos)                      /*!< 0x04000000 */
+#define CAN_TSR_TME0           CAN_TSR_TME0_Msk                                /*!<Transmit Mailbox 0 Empty */
+#define CAN_TSR_TME1_Pos       (27U)                                           
+#define CAN_TSR_TME1_Msk       (0x1UL << CAN_TSR_TME1_Pos)                      /*!< 0x08000000 */
+#define CAN_TSR_TME1           CAN_TSR_TME1_Msk                                /*!<Transmit Mailbox 1 Empty */
+#define CAN_TSR_TME2_Pos       (28U)                                           
+#define CAN_TSR_TME2_Msk       (0x1UL << CAN_TSR_TME2_Pos)                      /*!< 0x10000000 */
+#define CAN_TSR_TME2           CAN_TSR_TME2_Msk                                /*!<Transmit Mailbox 2 Empty */
+
+#define CAN_TSR_LOW_Pos        (29U)                                           
+#define CAN_TSR_LOW_Msk        (0x7UL << CAN_TSR_LOW_Pos)                       /*!< 0xE0000000 */
+#define CAN_TSR_LOW            CAN_TSR_LOW_Msk                                 /*!<LOW[2:0] bits */
+#define CAN_TSR_LOW0_Pos       (29U)                                           
+#define CAN_TSR_LOW0_Msk       (0x1UL << CAN_TSR_LOW0_Pos)                      /*!< 0x20000000 */
+#define CAN_TSR_LOW0           CAN_TSR_LOW0_Msk                                /*!<Lowest Priority Flag for Mailbox 0 */
+#define CAN_TSR_LOW1_Pos       (30U)                                           
+#define CAN_TSR_LOW1_Msk       (0x1UL << CAN_TSR_LOW1_Pos)                      /*!< 0x40000000 */
+#define CAN_TSR_LOW1           CAN_TSR_LOW1_Msk                                /*!<Lowest Priority Flag for Mailbox 1 */
+#define CAN_TSR_LOW2_Pos       (31U)                                           
+#define CAN_TSR_LOW2_Msk       (0x1UL << CAN_TSR_LOW2_Pos)                      /*!< 0x80000000 */
+#define CAN_TSR_LOW2           CAN_TSR_LOW2_Msk                                /*!<Lowest Priority Flag for Mailbox 2 */
+
+/*******************  Bit definition for CAN_RF0R register  *******************/
+#define CAN_RF0R_FMP0_Pos      (0U)                                            
+#define CAN_RF0R_FMP0_Msk      (0x3UL << CAN_RF0R_FMP0_Pos)                     /*!< 0x00000003 */
+#define CAN_RF0R_FMP0          CAN_RF0R_FMP0_Msk                               /*!<FIFO 0 Message Pending */
+#define CAN_RF0R_FULL0_Pos     (3U)                                            
+#define CAN_RF0R_FULL0_Msk     (0x1UL << CAN_RF0R_FULL0_Pos)                    /*!< 0x00000008 */
+#define CAN_RF0R_FULL0         CAN_RF0R_FULL0_Msk                              /*!<FIFO 0 Full */
+#define CAN_RF0R_FOVR0_Pos     (4U)                                            
+#define CAN_RF0R_FOVR0_Msk     (0x1UL << CAN_RF0R_FOVR0_Pos)                    /*!< 0x00000010 */
+#define CAN_RF0R_FOVR0         CAN_RF0R_FOVR0_Msk                              /*!<FIFO 0 Overrun */
+#define CAN_RF0R_RFOM0_Pos     (5U)                                            
+#define CAN_RF0R_RFOM0_Msk     (0x1UL << CAN_RF0R_RFOM0_Pos)                    /*!< 0x00000020 */
+#define CAN_RF0R_RFOM0         CAN_RF0R_RFOM0_Msk                              /*!<Release FIFO 0 Output Mailbox */
+
+/*******************  Bit definition for CAN_RF1R register  *******************/
+#define CAN_RF1R_FMP1_Pos      (0U)                                            
+#define CAN_RF1R_FMP1_Msk      (0x3UL << CAN_RF1R_FMP1_Pos)                     /*!< 0x00000003 */
+#define CAN_RF1R_FMP1          CAN_RF1R_FMP1_Msk                               /*!<FIFO 1 Message Pending */
+#define CAN_RF1R_FULL1_Pos     (3U)                                            
+#define CAN_RF1R_FULL1_Msk     (0x1UL << CAN_RF1R_FULL1_Pos)                    /*!< 0x00000008 */
+#define CAN_RF1R_FULL1         CAN_RF1R_FULL1_Msk                              /*!<FIFO 1 Full */
+#define CAN_RF1R_FOVR1_Pos     (4U)                                            
+#define CAN_RF1R_FOVR1_Msk     (0x1UL << CAN_RF1R_FOVR1_Pos)                    /*!< 0x00000010 */
+#define CAN_RF1R_FOVR1         CAN_RF1R_FOVR1_Msk                              /*!<FIFO 1 Overrun */
+#define CAN_RF1R_RFOM1_Pos     (5U)                                            
+#define CAN_RF1R_RFOM1_Msk     (0x1UL << CAN_RF1R_RFOM1_Pos)                    /*!< 0x00000020 */
+#define CAN_RF1R_RFOM1         CAN_RF1R_RFOM1_Msk                              /*!<Release FIFO 1 Output Mailbox */
+
+/********************  Bit definition for CAN_IER register  *******************/
+#define CAN_IER_TMEIE_Pos      (0U)                                            
+#define CAN_IER_TMEIE_Msk      (0x1UL << CAN_IER_TMEIE_Pos)                     /*!< 0x00000001 */
+#define CAN_IER_TMEIE          CAN_IER_TMEIE_Msk                               /*!<Transmit Mailbox Empty Interrupt Enable */
+#define CAN_IER_FMPIE0_Pos     (1U)                                            
+#define CAN_IER_FMPIE0_Msk     (0x1UL << CAN_IER_FMPIE0_Pos)                    /*!< 0x00000002 */
+#define CAN_IER_FMPIE0         CAN_IER_FMPIE0_Msk                              /*!<FIFO Message Pending Interrupt Enable */
+#define CAN_IER_FFIE0_Pos      (2U)                                            
+#define CAN_IER_FFIE0_Msk      (0x1UL << CAN_IER_FFIE0_Pos)                     /*!< 0x00000004 */
+#define CAN_IER_FFIE0          CAN_IER_FFIE0_Msk                               /*!<FIFO Full Interrupt Enable */
+#define CAN_IER_FOVIE0_Pos     (3U)                                            
+#define CAN_IER_FOVIE0_Msk     (0x1UL << CAN_IER_FOVIE0_Pos)                    /*!< 0x00000008 */
+#define CAN_IER_FOVIE0         CAN_IER_FOVIE0_Msk                              /*!<FIFO Overrun Interrupt Enable */
+#define CAN_IER_FMPIE1_Pos     (4U)                                            
+#define CAN_IER_FMPIE1_Msk     (0x1UL << CAN_IER_FMPIE1_Pos)                    /*!< 0x00000010 */
+#define CAN_IER_FMPIE1         CAN_IER_FMPIE1_Msk                              /*!<FIFO Message Pending Interrupt Enable */
+#define CAN_IER_FFIE1_Pos      (5U)                                            
+#define CAN_IER_FFIE1_Msk      (0x1UL << CAN_IER_FFIE1_Pos)                     /*!< 0x00000020 */
+#define CAN_IER_FFIE1          CAN_IER_FFIE1_Msk                               /*!<FIFO Full Interrupt Enable */
+#define CAN_IER_FOVIE1_Pos     (6U)                                            
+#define CAN_IER_FOVIE1_Msk     (0x1UL << CAN_IER_FOVIE1_Pos)                    /*!< 0x00000040 */
+#define CAN_IER_FOVIE1         CAN_IER_FOVIE1_Msk                              /*!<FIFO Overrun Interrupt Enable */
+#define CAN_IER_EWGIE_Pos      (8U)                                            
+#define CAN_IER_EWGIE_Msk      (0x1UL << CAN_IER_EWGIE_Pos)                     /*!< 0x00000100 */
+#define CAN_IER_EWGIE          CAN_IER_EWGIE_Msk                               /*!<Error Warning Interrupt Enable */
+#define CAN_IER_EPVIE_Pos      (9U)                                            
+#define CAN_IER_EPVIE_Msk      (0x1UL << CAN_IER_EPVIE_Pos)                     /*!< 0x00000200 */
+#define CAN_IER_EPVIE          CAN_IER_EPVIE_Msk                               /*!<Error Passive Interrupt Enable */
+#define CAN_IER_BOFIE_Pos      (10U)                                           
+#define CAN_IER_BOFIE_Msk      (0x1UL << CAN_IER_BOFIE_Pos)                     /*!< 0x00000400 */
+#define CAN_IER_BOFIE          CAN_IER_BOFIE_Msk                               /*!<Bus-Off Interrupt Enable */
+#define CAN_IER_LECIE_Pos      (11U)                                           
+#define CAN_IER_LECIE_Msk      (0x1UL << CAN_IER_LECIE_Pos)                     /*!< 0x00000800 */
+#define CAN_IER_LECIE          CAN_IER_LECIE_Msk                               /*!<Last Error Code Interrupt Enable */
+#define CAN_IER_ERRIE_Pos      (15U)                                           
+#define CAN_IER_ERRIE_Msk      (0x1UL << CAN_IER_ERRIE_Pos)                     /*!< 0x00008000 */
+#define CAN_IER_ERRIE          CAN_IER_ERRIE_Msk                               /*!<Error Interrupt Enable */
+#define CAN_IER_WKUIE_Pos      (16U)                                           
+#define CAN_IER_WKUIE_Msk      (0x1UL << CAN_IER_WKUIE_Pos)                     /*!< 0x00010000 */
+#define CAN_IER_WKUIE          CAN_IER_WKUIE_Msk                               /*!<Wakeup Interrupt Enable */
+#define CAN_IER_SLKIE_Pos      (17U)                                           
+#define CAN_IER_SLKIE_Msk      (0x1UL << CAN_IER_SLKIE_Pos)                     /*!< 0x00020000 */
+#define CAN_IER_SLKIE          CAN_IER_SLKIE_Msk                               /*!<Sleep Interrupt Enable */
+#define CAN_IER_EWGIE_Pos      (8U)                                            
+
+/********************  Bit definition for CAN_ESR register  *******************/
+#define CAN_ESR_EWGF_Pos       (0U)                                            
+#define CAN_ESR_EWGF_Msk       (0x1UL << CAN_ESR_EWGF_Pos)                      /*!< 0x00000001 */
+#define CAN_ESR_EWGF           CAN_ESR_EWGF_Msk                                /*!<Error Warning Flag */
+#define CAN_ESR_EPVF_Pos       (1U)                                            
+#define CAN_ESR_EPVF_Msk       (0x1UL << CAN_ESR_EPVF_Pos)                      /*!< 0x00000002 */
+#define CAN_ESR_EPVF           CAN_ESR_EPVF_Msk                                /*!<Error Passive Flag */
+#define CAN_ESR_BOFF_Pos       (2U)                                            
+#define CAN_ESR_BOFF_Msk       (0x1UL << CAN_ESR_BOFF_Pos)                      /*!< 0x00000004 */
+#define CAN_ESR_BOFF           CAN_ESR_BOFF_Msk                                /*!<Bus-Off Flag */
+
+#define CAN_ESR_LEC_Pos        (4U)                                            
+#define CAN_ESR_LEC_Msk        (0x7UL << CAN_ESR_LEC_Pos)                       /*!< 0x00000070 */
+#define CAN_ESR_LEC            CAN_ESR_LEC_Msk                                 /*!<LEC[2:0] bits (Last Error Code) */
+#define CAN_ESR_LEC_0          (0x1UL << CAN_ESR_LEC_Pos)                       /*!< 0x00000010 */
+#define CAN_ESR_LEC_1          (0x2UL << CAN_ESR_LEC_Pos)                       /*!< 0x00000020 */
+#define CAN_ESR_LEC_2          (0x4UL << CAN_ESR_LEC_Pos)                       /*!< 0x00000040 */
+
+#define CAN_ESR_TEC_Pos        (16U)                                           
+#define CAN_ESR_TEC_Msk        (0xFFUL << CAN_ESR_TEC_Pos)                      /*!< 0x00FF0000 */
+#define CAN_ESR_TEC            CAN_ESR_TEC_Msk                                 /*!<Least significant byte of the 9-bit Transmit Error Counter */
+#define CAN_ESR_REC_Pos        (24U)                                           
+#define CAN_ESR_REC_Msk        (0xFFUL << CAN_ESR_REC_Pos)                      /*!< 0xFF000000 */
+#define CAN_ESR_REC            CAN_ESR_REC_Msk                                 /*!<Receive Error Counter */
+
+/*******************  Bit definition for CAN_BTR register  ********************/
+#define CAN_BTR_BRP_Pos        (0U)                                            
+#define CAN_BTR_BRP_Msk        (0x3FFUL << CAN_BTR_BRP_Pos)                     /*!< 0x000003FF */
+#define CAN_BTR_BRP            CAN_BTR_BRP_Msk                                 /*!<Baud Rate Prescaler */
+#define CAN_BTR_TS1_Pos        (16U)                                           
+#define CAN_BTR_TS1_Msk        (0xFUL << CAN_BTR_TS1_Pos)                       /*!< 0x000F0000 */
+#define CAN_BTR_TS1            CAN_BTR_TS1_Msk                                 /*!<Time Segment 1 */
+#define CAN_BTR_TS1_0          (0x1UL << CAN_BTR_TS1_Pos)                       /*!< 0x00010000 */
+#define CAN_BTR_TS1_1          (0x2UL << CAN_BTR_TS1_Pos)                       /*!< 0x00020000 */
+#define CAN_BTR_TS1_2          (0x4UL << CAN_BTR_TS1_Pos)                       /*!< 0x00040000 */
+#define CAN_BTR_TS1_3          (0x8UL << CAN_BTR_TS1_Pos)                       /*!< 0x00080000 */
+#define CAN_BTR_TS2_Pos        (20U)                                           
+#define CAN_BTR_TS2_Msk        (0x7UL << CAN_BTR_TS2_Pos)                       /*!< 0x00700000 */
+#define CAN_BTR_TS2            CAN_BTR_TS2_Msk                                 /*!<Time Segment 2 */
+#define CAN_BTR_TS2_0          (0x1UL << CAN_BTR_TS2_Pos)                       /*!< 0x00100000 */
+#define CAN_BTR_TS2_1          (0x2UL << CAN_BTR_TS2_Pos)                       /*!< 0x00200000 */
+#define CAN_BTR_TS2_2          (0x4UL << CAN_BTR_TS2_Pos)                       /*!< 0x00400000 */
+#define CAN_BTR_SJW_Pos        (24U)                                           
+#define CAN_BTR_SJW_Msk        (0x3UL << CAN_BTR_SJW_Pos)                       /*!< 0x03000000 */
+#define CAN_BTR_SJW            CAN_BTR_SJW_Msk                                 /*!<Resynchronization Jump Width */
+#define CAN_BTR_SJW_0          (0x1UL << CAN_BTR_SJW_Pos)                       /*!< 0x01000000 */
+#define CAN_BTR_SJW_1          (0x2UL << CAN_BTR_SJW_Pos)                       /*!< 0x02000000 */
+#define CAN_BTR_LBKM_Pos       (30U)                                           
+#define CAN_BTR_LBKM_Msk       (0x1UL << CAN_BTR_LBKM_Pos)                      /*!< 0x40000000 */
+#define CAN_BTR_LBKM           CAN_BTR_LBKM_Msk                                /*!<Loop Back Mode (Debug) */
+#define CAN_BTR_SILM_Pos       (31U)                                           
+#define CAN_BTR_SILM_Msk       (0x1UL << CAN_BTR_SILM_Pos)                      /*!< 0x80000000 */
+#define CAN_BTR_SILM           CAN_BTR_SILM_Msk                                /*!<Silent Mode */
+
+
+/*!<Mailbox registers */
+/******************  Bit definition for CAN_TI0R register  ********************/
+#define CAN_TI0R_TXRQ_Pos      (0U)                                            
+#define CAN_TI0R_TXRQ_Msk      (0x1UL << CAN_TI0R_TXRQ_Pos)                     /*!< 0x00000001 */
+#define CAN_TI0R_TXRQ          CAN_TI0R_TXRQ_Msk                               /*!<Transmit Mailbox Request */
+#define CAN_TI0R_RTR_Pos       (1U)                                            
+#define CAN_TI0R_RTR_Msk       (0x1UL << CAN_TI0R_RTR_Pos)                      /*!< 0x00000002 */
+#define CAN_TI0R_RTR           CAN_TI0R_RTR_Msk                                /*!<Remote Transmission Request */
+#define CAN_TI0R_IDE_Pos       (2U)                                            
+#define CAN_TI0R_IDE_Msk       (0x1UL << CAN_TI0R_IDE_Pos)                      /*!< 0x00000004 */
+#define CAN_TI0R_IDE           CAN_TI0R_IDE_Msk                                /*!<Identifier Extension */
+#define CAN_TI0R_EXID_Pos      (3U)                                            
+#define CAN_TI0R_EXID_Msk      (0x3FFFFUL << CAN_TI0R_EXID_Pos)                 /*!< 0x001FFFF8 */
+#define CAN_TI0R_EXID          CAN_TI0R_EXID_Msk                               /*!<Extended Identifier */
+#define CAN_TI0R_STID_Pos      (21U)                                           
+#define CAN_TI0R_STID_Msk      (0x7FFUL << CAN_TI0R_STID_Pos)                   /*!< 0xFFE00000 */
+#define CAN_TI0R_STID          CAN_TI0R_STID_Msk                               /*!<Standard Identifier or Extended Identifier */
+
+/******************  Bit definition for CAN_TDT0R register  *******************/
+#define CAN_TDT0R_DLC_Pos      (0U)                                            
+#define CAN_TDT0R_DLC_Msk      (0xFUL << CAN_TDT0R_DLC_Pos)                     /*!< 0x0000000F */
+#define CAN_TDT0R_DLC          CAN_TDT0R_DLC_Msk                               /*!<Data Length Code */
+#define CAN_TDT0R_TGT_Pos      (8U)                                            
+#define CAN_TDT0R_TGT_Msk      (0x1UL << CAN_TDT0R_TGT_Pos)                     /*!< 0x00000100 */
+#define CAN_TDT0R_TGT          CAN_TDT0R_TGT_Msk                               /*!<Transmit Global Time */
+#define CAN_TDT0R_TIME_Pos     (16U)                                           
+#define CAN_TDT0R_TIME_Msk     (0xFFFFUL << CAN_TDT0R_TIME_Pos)                 /*!< 0xFFFF0000 */
+#define CAN_TDT0R_TIME         CAN_TDT0R_TIME_Msk                              /*!<Message Time Stamp */
+
+/******************  Bit definition for CAN_TDL0R register  *******************/
+#define CAN_TDL0R_DATA0_Pos    (0U)                                            
+#define CAN_TDL0R_DATA0_Msk    (0xFFUL << CAN_TDL0R_DATA0_Pos)                  /*!< 0x000000FF */
+#define CAN_TDL0R_DATA0        CAN_TDL0R_DATA0_Msk                             /*!<Data byte 0 */
+#define CAN_TDL0R_DATA1_Pos    (8U)                                            
+#define CAN_TDL0R_DATA1_Msk    (0xFFUL << CAN_TDL0R_DATA1_Pos)                  /*!< 0x0000FF00 */
+#define CAN_TDL0R_DATA1        CAN_TDL0R_DATA1_Msk                             /*!<Data byte 1 */
+#define CAN_TDL0R_DATA2_Pos    (16U)                                           
+#define CAN_TDL0R_DATA2_Msk    (0xFFUL << CAN_TDL0R_DATA2_Pos)                  /*!< 0x00FF0000 */
+#define CAN_TDL0R_DATA2        CAN_TDL0R_DATA2_Msk                             /*!<Data byte 2 */
+#define CAN_TDL0R_DATA3_Pos    (24U)                                           
+#define CAN_TDL0R_DATA3_Msk    (0xFFUL << CAN_TDL0R_DATA3_Pos)                  /*!< 0xFF000000 */
+#define CAN_TDL0R_DATA3        CAN_TDL0R_DATA3_Msk                             /*!<Data byte 3 */
+
+/******************  Bit definition for CAN_TDH0R register  *******************/
+#define CAN_TDH0R_DATA4_Pos    (0U)                                            
+#define CAN_TDH0R_DATA4_Msk    (0xFFUL << CAN_TDH0R_DATA4_Pos)                  /*!< 0x000000FF */
+#define CAN_TDH0R_DATA4        CAN_TDH0R_DATA4_Msk                             /*!<Data byte 4 */
+#define CAN_TDH0R_DATA5_Pos    (8U)                                            
+#define CAN_TDH0R_DATA5_Msk    (0xFFUL << CAN_TDH0R_DATA5_Pos)                  /*!< 0x0000FF00 */
+#define CAN_TDH0R_DATA5        CAN_TDH0R_DATA5_Msk                             /*!<Data byte 5 */
+#define CAN_TDH0R_DATA6_Pos    (16U)                                           
+#define CAN_TDH0R_DATA6_Msk    (0xFFUL << CAN_TDH0R_DATA6_Pos)                  /*!< 0x00FF0000 */
+#define CAN_TDH0R_DATA6        CAN_TDH0R_DATA6_Msk                             /*!<Data byte 6 */
+#define CAN_TDH0R_DATA7_Pos    (24U)                                           
+#define CAN_TDH0R_DATA7_Msk    (0xFFUL << CAN_TDH0R_DATA7_Pos)                  /*!< 0xFF000000 */
+#define CAN_TDH0R_DATA7        CAN_TDH0R_DATA7_Msk                             /*!<Data byte 7 */
+
+/*******************  Bit definition for CAN_TI1R register  *******************/
+#define CAN_TI1R_TXRQ_Pos      (0U)                                            
+#define CAN_TI1R_TXRQ_Msk      (0x1UL << CAN_TI1R_TXRQ_Pos)                     /*!< 0x00000001 */
+#define CAN_TI1R_TXRQ          CAN_TI1R_TXRQ_Msk                               /*!<Transmit Mailbox Request */
+#define CAN_TI1R_RTR_Pos       (1U)                                            
+#define CAN_TI1R_RTR_Msk       (0x1UL << CAN_TI1R_RTR_Pos)                      /*!< 0x00000002 */
+#define CAN_TI1R_RTR           CAN_TI1R_RTR_Msk                                /*!<Remote Transmission Request */
+#define CAN_TI1R_IDE_Pos       (2U)                                            
+#define CAN_TI1R_IDE_Msk       (0x1UL << CAN_TI1R_IDE_Pos)                      /*!< 0x00000004 */
+#define CAN_TI1R_IDE           CAN_TI1R_IDE_Msk                                /*!<Identifier Extension */
+#define CAN_TI1R_EXID_Pos      (3U)                                            
+#define CAN_TI1R_EXID_Msk      (0x3FFFFUL << CAN_TI1R_EXID_Pos)                 /*!< 0x001FFFF8 */
+#define CAN_TI1R_EXID          CAN_TI1R_EXID_Msk                               /*!<Extended Identifier */
+#define CAN_TI1R_STID_Pos      (21U)                                           
+#define CAN_TI1R_STID_Msk      (0x7FFUL << CAN_TI1R_STID_Pos)                   /*!< 0xFFE00000 */
+#define CAN_TI1R_STID          CAN_TI1R_STID_Msk                               /*!<Standard Identifier or Extended Identifier */
+
+/*******************  Bit definition for CAN_TDT1R register  ******************/
+#define CAN_TDT1R_DLC_Pos      (0U)                                            
+#define CAN_TDT1R_DLC_Msk      (0xFUL << CAN_TDT1R_DLC_Pos)                     /*!< 0x0000000F */
+#define CAN_TDT1R_DLC          CAN_TDT1R_DLC_Msk                               /*!<Data Length Code */
+#define CAN_TDT1R_TGT_Pos      (8U)                                            
+#define CAN_TDT1R_TGT_Msk      (0x1UL << CAN_TDT1R_TGT_Pos)                     /*!< 0x00000100 */
+#define CAN_TDT1R_TGT          CAN_TDT1R_TGT_Msk                               /*!<Transmit Global Time */
+#define CAN_TDT1R_TIME_Pos     (16U)                                           
+#define CAN_TDT1R_TIME_Msk     (0xFFFFUL << CAN_TDT1R_TIME_Pos)                 /*!< 0xFFFF0000 */
+#define CAN_TDT1R_TIME         CAN_TDT1R_TIME_Msk                              /*!<Message Time Stamp */
+
+/*******************  Bit definition for CAN_TDL1R register  ******************/
+#define CAN_TDL1R_DATA0_Pos    (0U)                                            
+#define CAN_TDL1R_DATA0_Msk    (0xFFUL << CAN_TDL1R_DATA0_Pos)                  /*!< 0x000000FF */
+#define CAN_TDL1R_DATA0        CAN_TDL1R_DATA0_Msk                             /*!<Data byte 0 */
+#define CAN_TDL1R_DATA1_Pos    (8U)                                            
+#define CAN_TDL1R_DATA1_Msk    (0xFFUL << CAN_TDL1R_DATA1_Pos)                  /*!< 0x0000FF00 */
+#define CAN_TDL1R_DATA1        CAN_TDL1R_DATA1_Msk                             /*!<Data byte 1 */
+#define CAN_TDL1R_DATA2_Pos    (16U)                                           
+#define CAN_TDL1R_DATA2_Msk    (0xFFUL << CAN_TDL1R_DATA2_Pos)                  /*!< 0x00FF0000 */
+#define CAN_TDL1R_DATA2        CAN_TDL1R_DATA2_Msk                             /*!<Data byte 2 */
+#define CAN_TDL1R_DATA3_Pos    (24U)                                           
+#define CAN_TDL1R_DATA3_Msk    (0xFFUL << CAN_TDL1R_DATA3_Pos)                  /*!< 0xFF000000 */
+#define CAN_TDL1R_DATA3        CAN_TDL1R_DATA3_Msk                             /*!<Data byte 3 */
+
+/*******************  Bit definition for CAN_TDH1R register  ******************/
+#define CAN_TDH1R_DATA4_Pos    (0U)                                            
+#define CAN_TDH1R_DATA4_Msk    (0xFFUL << CAN_TDH1R_DATA4_Pos)                  /*!< 0x000000FF */
+#define CAN_TDH1R_DATA4        CAN_TDH1R_DATA4_Msk                             /*!<Data byte 4 */
+#define CAN_TDH1R_DATA5_Pos    (8U)                                            
+#define CAN_TDH1R_DATA5_Msk    (0xFFUL << CAN_TDH1R_DATA5_Pos)                  /*!< 0x0000FF00 */
+#define CAN_TDH1R_DATA5        CAN_TDH1R_DATA5_Msk                             /*!<Data byte 5 */
+#define CAN_TDH1R_DATA6_Pos    (16U)                                           
+#define CAN_TDH1R_DATA6_Msk    (0xFFUL << CAN_TDH1R_DATA6_Pos)                  /*!< 0x00FF0000 */
+#define CAN_TDH1R_DATA6        CAN_TDH1R_DATA6_Msk                             /*!<Data byte 6 */
+#define CAN_TDH1R_DATA7_Pos    (24U)                                           
+#define CAN_TDH1R_DATA7_Msk    (0xFFUL << CAN_TDH1R_DATA7_Pos)                  /*!< 0xFF000000 */
+#define CAN_TDH1R_DATA7        CAN_TDH1R_DATA7_Msk                             /*!<Data byte 7 */
+
+/*******************  Bit definition for CAN_TI2R register  *******************/
+#define CAN_TI2R_TXRQ_Pos      (0U)                                            
+#define CAN_TI2R_TXRQ_Msk      (0x1UL << CAN_TI2R_TXRQ_Pos)                     /*!< 0x00000001 */
+#define CAN_TI2R_TXRQ          CAN_TI2R_TXRQ_Msk                               /*!<Transmit Mailbox Request */
+#define CAN_TI2R_RTR_Pos       (1U)                                            
+#define CAN_TI2R_RTR_Msk       (0x1UL << CAN_TI2R_RTR_Pos)                      /*!< 0x00000002 */
+#define CAN_TI2R_RTR           CAN_TI2R_RTR_Msk                                /*!<Remote Transmission Request */
+#define CAN_TI2R_IDE_Pos       (2U)                                            
+#define CAN_TI2R_IDE_Msk       (0x1UL << CAN_TI2R_IDE_Pos)                      /*!< 0x00000004 */
+#define CAN_TI2R_IDE           CAN_TI2R_IDE_Msk                                /*!<Identifier Extension */
+#define CAN_TI2R_EXID_Pos      (3U)                                            
+#define CAN_TI2R_EXID_Msk      (0x3FFFFUL << CAN_TI2R_EXID_Pos)                 /*!< 0x001FFFF8 */
+#define CAN_TI2R_EXID          CAN_TI2R_EXID_Msk                               /*!<Extended identifier */
+#define CAN_TI2R_STID_Pos      (21U)                                           
+#define CAN_TI2R_STID_Msk      (0x7FFUL << CAN_TI2R_STID_Pos)                   /*!< 0xFFE00000 */
+#define CAN_TI2R_STID          CAN_TI2R_STID_Msk                               /*!<Standard Identifier or Extended Identifier */
+
+/*******************  Bit definition for CAN_TDT2R register  ******************/  
+#define CAN_TDT2R_DLC_Pos      (0U)                                            
+#define CAN_TDT2R_DLC_Msk      (0xFUL << CAN_TDT2R_DLC_Pos)                     /*!< 0x0000000F */
+#define CAN_TDT2R_DLC          CAN_TDT2R_DLC_Msk                               /*!<Data Length Code */
+#define CAN_TDT2R_TGT_Pos      (8U)                                            
+#define CAN_TDT2R_TGT_Msk      (0x1UL << CAN_TDT2R_TGT_Pos)                     /*!< 0x00000100 */
+#define CAN_TDT2R_TGT          CAN_TDT2R_TGT_Msk                               /*!<Transmit Global Time */
+#define CAN_TDT2R_TIME_Pos     (16U)                                           
+#define CAN_TDT2R_TIME_Msk     (0xFFFFUL << CAN_TDT2R_TIME_Pos)                 /*!< 0xFFFF0000 */
+#define CAN_TDT2R_TIME         CAN_TDT2R_TIME_Msk                              /*!<Message Time Stamp */
+
+/*******************  Bit definition for CAN_TDL2R register  ******************/
+#define CAN_TDL2R_DATA0_Pos    (0U)                                            
+#define CAN_TDL2R_DATA0_Msk    (0xFFUL << CAN_TDL2R_DATA0_Pos)                  /*!< 0x000000FF */
+#define CAN_TDL2R_DATA0        CAN_TDL2R_DATA0_Msk                             /*!<Data byte 0 */
+#define CAN_TDL2R_DATA1_Pos    (8U)                                            
+#define CAN_TDL2R_DATA1_Msk    (0xFFUL << CAN_TDL2R_DATA1_Pos)                  /*!< 0x0000FF00 */
+#define CAN_TDL2R_DATA1        CAN_TDL2R_DATA1_Msk                             /*!<Data byte 1 */
+#define CAN_TDL2R_DATA2_Pos    (16U)                                           
+#define CAN_TDL2R_DATA2_Msk    (0xFFUL << CAN_TDL2R_DATA2_Pos)                  /*!< 0x00FF0000 */
+#define CAN_TDL2R_DATA2        CAN_TDL2R_DATA2_Msk                             /*!<Data byte 2 */
+#define CAN_TDL2R_DATA3_Pos    (24U)                                           
+#define CAN_TDL2R_DATA3_Msk    (0xFFUL << CAN_TDL2R_DATA3_Pos)                  /*!< 0xFF000000 */
+#define CAN_TDL2R_DATA3        CAN_TDL2R_DATA3_Msk                             /*!<Data byte 3 */
+
+/*******************  Bit definition for CAN_TDH2R register  ******************/
+#define CAN_TDH2R_DATA4_Pos    (0U)                                            
+#define CAN_TDH2R_DATA4_Msk    (0xFFUL << CAN_TDH2R_DATA4_Pos)                  /*!< 0x000000FF */
+#define CAN_TDH2R_DATA4        CAN_TDH2R_DATA4_Msk                             /*!<Data byte 4 */
+#define CAN_TDH2R_DATA5_Pos    (8U)                                            
+#define CAN_TDH2R_DATA5_Msk    (0xFFUL << CAN_TDH2R_DATA5_Pos)                  /*!< 0x0000FF00 */
+#define CAN_TDH2R_DATA5        CAN_TDH2R_DATA5_Msk                             /*!<Data byte 5 */
+#define CAN_TDH2R_DATA6_Pos    (16U)                                           
+#define CAN_TDH2R_DATA6_Msk    (0xFFUL << CAN_TDH2R_DATA6_Pos)                  /*!< 0x00FF0000 */
+#define CAN_TDH2R_DATA6        CAN_TDH2R_DATA6_Msk                             /*!<Data byte 6 */
+#define CAN_TDH2R_DATA7_Pos    (24U)                                           
+#define CAN_TDH2R_DATA7_Msk    (0xFFUL << CAN_TDH2R_DATA7_Pos)                  /*!< 0xFF000000 */
+#define CAN_TDH2R_DATA7        CAN_TDH2R_DATA7_Msk                             /*!<Data byte 7 */
+
+/*******************  Bit definition for CAN_RI0R register  *******************/
+#define CAN_RI0R_RTR_Pos       (1U)                                            
+#define CAN_RI0R_RTR_Msk       (0x1UL << CAN_RI0R_RTR_Pos)                      /*!< 0x00000002 */
+#define CAN_RI0R_RTR           CAN_RI0R_RTR_Msk                                /*!<Remote Transmission Request */
+#define CAN_RI0R_IDE_Pos       (2U)                                            
+#define CAN_RI0R_IDE_Msk       (0x1UL << CAN_RI0R_IDE_Pos)                      /*!< 0x00000004 */
+#define CAN_RI0R_IDE           CAN_RI0R_IDE_Msk                                /*!<Identifier Extension */
+#define CAN_RI0R_EXID_Pos      (3U)                                            
+#define CAN_RI0R_EXID_Msk      (0x3FFFFUL << CAN_RI0R_EXID_Pos)                 /*!< 0x001FFFF8 */
+#define CAN_RI0R_EXID          CAN_RI0R_EXID_Msk                               /*!<Extended Identifier */
+#define CAN_RI0R_STID_Pos      (21U)                                           
+#define CAN_RI0R_STID_Msk      (0x7FFUL << CAN_RI0R_STID_Pos)                   /*!< 0xFFE00000 */
+#define CAN_RI0R_STID          CAN_RI0R_STID_Msk                               /*!<Standard Identifier or Extended Identifier */
+
+/*******************  Bit definition for CAN_RDT0R register  ******************/
+#define CAN_RDT0R_DLC_Pos      (0U)                                            
+#define CAN_RDT0R_DLC_Msk      (0xFUL << CAN_RDT0R_DLC_Pos)                     /*!< 0x0000000F */
+#define CAN_RDT0R_DLC          CAN_RDT0R_DLC_Msk                               /*!<Data Length Code */
+#define CAN_RDT0R_FMI_Pos      (8U)                                            
+#define CAN_RDT0R_FMI_Msk      (0xFFUL << CAN_RDT0R_FMI_Pos)                    /*!< 0x0000FF00 */
+#define CAN_RDT0R_FMI          CAN_RDT0R_FMI_Msk                               /*!<Filter Match Index */
+#define CAN_RDT0R_TIME_Pos     (16U)                                           
+#define CAN_RDT0R_TIME_Msk     (0xFFFFUL << CAN_RDT0R_TIME_Pos)                 /*!< 0xFFFF0000 */
+#define CAN_RDT0R_TIME         CAN_RDT0R_TIME_Msk                              /*!<Message Time Stamp */
+
+/*******************  Bit definition for CAN_RDL0R register  ******************/
+#define CAN_RDL0R_DATA0_Pos    (0U)                                            
+#define CAN_RDL0R_DATA0_Msk    (0xFFUL << CAN_RDL0R_DATA0_Pos)                  /*!< 0x000000FF */
+#define CAN_RDL0R_DATA0        CAN_RDL0R_DATA0_Msk                             /*!<Data byte 0 */
+#define CAN_RDL0R_DATA1_Pos    (8U)                                            
+#define CAN_RDL0R_DATA1_Msk    (0xFFUL << CAN_RDL0R_DATA1_Pos)                  /*!< 0x0000FF00 */
+#define CAN_RDL0R_DATA1        CAN_RDL0R_DATA1_Msk                             /*!<Data byte 1 */
+#define CAN_RDL0R_DATA2_Pos    (16U)                                           
+#define CAN_RDL0R_DATA2_Msk    (0xFFUL << CAN_RDL0R_DATA2_Pos)                  /*!< 0x00FF0000 */
+#define CAN_RDL0R_DATA2        CAN_RDL0R_DATA2_Msk                             /*!<Data byte 2 */
+#define CAN_RDL0R_DATA3_Pos    (24U)                                           
+#define CAN_RDL0R_DATA3_Msk    (0xFFUL << CAN_RDL0R_DATA3_Pos)                  /*!< 0xFF000000 */
+#define CAN_RDL0R_DATA3        CAN_RDL0R_DATA3_Msk                             /*!<Data byte 3 */
+
+/*******************  Bit definition for CAN_RDH0R register  ******************/
+#define CAN_RDH0R_DATA4_Pos    (0U)                                            
+#define CAN_RDH0R_DATA4_Msk    (0xFFUL << CAN_RDH0R_DATA4_Pos)                  /*!< 0x000000FF */
+#define CAN_RDH0R_DATA4        CAN_RDH0R_DATA4_Msk                             /*!<Data byte 4 */
+#define CAN_RDH0R_DATA5_Pos    (8U)                                            
+#define CAN_RDH0R_DATA5_Msk    (0xFFUL << CAN_RDH0R_DATA5_Pos)                  /*!< 0x0000FF00 */
+#define CAN_RDH0R_DATA5        CAN_RDH0R_DATA5_Msk                             /*!<Data byte 5 */
+#define CAN_RDH0R_DATA6_Pos    (16U)                                           
+#define CAN_RDH0R_DATA6_Msk    (0xFFUL << CAN_RDH0R_DATA6_Pos)                  /*!< 0x00FF0000 */
+#define CAN_RDH0R_DATA6        CAN_RDH0R_DATA6_Msk                             /*!<Data byte 6 */
+#define CAN_RDH0R_DATA7_Pos    (24U)                                           
+#define CAN_RDH0R_DATA7_Msk    (0xFFUL << CAN_RDH0R_DATA7_Pos)                  /*!< 0xFF000000 */
+#define CAN_RDH0R_DATA7        CAN_RDH0R_DATA7_Msk                             /*!<Data byte 7 */
+
+/*******************  Bit definition for CAN_RI1R register  *******************/
+#define CAN_RI1R_RTR_Pos       (1U)                                            
+#define CAN_RI1R_RTR_Msk       (0x1UL << CAN_RI1R_RTR_Pos)                      /*!< 0x00000002 */
+#define CAN_RI1R_RTR           CAN_RI1R_RTR_Msk                                /*!<Remote Transmission Request */
+#define CAN_RI1R_IDE_Pos       (2U)                                            
+#define CAN_RI1R_IDE_Msk       (0x1UL << CAN_RI1R_IDE_Pos)                      /*!< 0x00000004 */
+#define CAN_RI1R_IDE           CAN_RI1R_IDE_Msk                                /*!<Identifier Extension */
+#define CAN_RI1R_EXID_Pos      (3U)                                            
+#define CAN_RI1R_EXID_Msk      (0x3FFFFUL << CAN_RI1R_EXID_Pos)                 /*!< 0x001FFFF8 */
+#define CAN_RI1R_EXID          CAN_RI1R_EXID_Msk                               /*!<Extended identifier */
+#define CAN_RI1R_STID_Pos      (21U)                                           
+#define CAN_RI1R_STID_Msk      (0x7FFUL << CAN_RI1R_STID_Pos)                   /*!< 0xFFE00000 */
+#define CAN_RI1R_STID          CAN_RI1R_STID_Msk                               /*!<Standard Identifier or Extended Identifier */
+
+/*******************  Bit definition for CAN_RDT1R register  ******************/
+#define CAN_RDT1R_DLC_Pos      (0U)                                            
+#define CAN_RDT1R_DLC_Msk      (0xFUL << CAN_RDT1R_DLC_Pos)                     /*!< 0x0000000F */
+#define CAN_RDT1R_DLC          CAN_RDT1R_DLC_Msk                               /*!<Data Length Code */
+#define CAN_RDT1R_FMI_Pos      (8U)                                            
+#define CAN_RDT1R_FMI_Msk      (0xFFUL << CAN_RDT1R_FMI_Pos)                    /*!< 0x0000FF00 */
+#define CAN_RDT1R_FMI          CAN_RDT1R_FMI_Msk                               /*!<Filter Match Index */
+#define CAN_RDT1R_TIME_Pos     (16U)                                           
+#define CAN_RDT1R_TIME_Msk     (0xFFFFUL << CAN_RDT1R_TIME_Pos)                 /*!< 0xFFFF0000 */
+#define CAN_RDT1R_TIME         CAN_RDT1R_TIME_Msk                              /*!<Message Time Stamp */
+
+/*******************  Bit definition for CAN_RDL1R register  ******************/
+#define CAN_RDL1R_DATA0_Pos    (0U)                                            
+#define CAN_RDL1R_DATA0_Msk    (0xFFUL << CAN_RDL1R_DATA0_Pos)                  /*!< 0x000000FF */
+#define CAN_RDL1R_DATA0        CAN_RDL1R_DATA0_Msk                             /*!<Data byte 0 */
+#define CAN_RDL1R_DATA1_Pos    (8U)                                            
+#define CAN_RDL1R_DATA1_Msk    (0xFFUL << CAN_RDL1R_DATA1_Pos)                  /*!< 0x0000FF00 */
+#define CAN_RDL1R_DATA1        CAN_RDL1R_DATA1_Msk                             /*!<Data byte 1 */
+#define CAN_RDL1R_DATA2_Pos    (16U)                                           
+#define CAN_RDL1R_DATA2_Msk    (0xFFUL << CAN_RDL1R_DATA2_Pos)                  /*!< 0x00FF0000 */
+#define CAN_RDL1R_DATA2        CAN_RDL1R_DATA2_Msk                             /*!<Data byte 2 */
+#define CAN_RDL1R_DATA3_Pos    (24U)                                           
+#define CAN_RDL1R_DATA3_Msk    (0xFFUL << CAN_RDL1R_DATA3_Pos)                  /*!< 0xFF000000 */
+#define CAN_RDL1R_DATA3        CAN_RDL1R_DATA3_Msk                             /*!<Data byte 3 */
+
+/*******************  Bit definition for CAN_RDH1R register  ******************/
+#define CAN_RDH1R_DATA4_Pos    (0U)                                            
+#define CAN_RDH1R_DATA4_Msk    (0xFFUL << CAN_RDH1R_DATA4_Pos)                  /*!< 0x000000FF */
+#define CAN_RDH1R_DATA4        CAN_RDH1R_DATA4_Msk                             /*!<Data byte 4 */
+#define CAN_RDH1R_DATA5_Pos    (8U)                                            
+#define CAN_RDH1R_DATA5_Msk    (0xFFUL << CAN_RDH1R_DATA5_Pos)                  /*!< 0x0000FF00 */
+#define CAN_RDH1R_DATA5        CAN_RDH1R_DATA5_Msk                             /*!<Data byte 5 */
+#define CAN_RDH1R_DATA6_Pos    (16U)                                           
+#define CAN_RDH1R_DATA6_Msk    (0xFFUL << CAN_RDH1R_DATA6_Pos)                  /*!< 0x00FF0000 */
+#define CAN_RDH1R_DATA6        CAN_RDH1R_DATA6_Msk                             /*!<Data byte 6 */
+#define CAN_RDH1R_DATA7_Pos    (24U)                                           
+#define CAN_RDH1R_DATA7_Msk    (0xFFUL << CAN_RDH1R_DATA7_Pos)                  /*!< 0xFF000000 */
+#define CAN_RDH1R_DATA7        CAN_RDH1R_DATA7_Msk                             /*!<Data byte 7 */
+
+/*!<CAN filter registers */
+/*******************  Bit definition for CAN_FMR register  ********************/
+#define CAN_FMR_FINIT_Pos      (0U)                                            
+#define CAN_FMR_FINIT_Msk      (0x1UL << CAN_FMR_FINIT_Pos)                     /*!< 0x00000001 */
+#define CAN_FMR_FINIT          CAN_FMR_FINIT_Msk                               /*!<Filter Init Mode */
+#define CAN_FMR_CAN2SB_Pos     (8U)                                            
+#define CAN_FMR_CAN2SB_Msk     (0x3FUL << CAN_FMR_CAN2SB_Pos)                   /*!< 0x00003F00 */
+#define CAN_FMR_CAN2SB         CAN_FMR_CAN2SB_Msk                              /*!<CAN2 start bank */
+
+/*******************  Bit definition for CAN_FM1R register  *******************/
+#define CAN_FM1R_FBM_Pos       (0U)                                            
+#define CAN_FM1R_FBM_Msk       (0xFFFFFFFUL << CAN_FM1R_FBM_Pos)                /*!< 0x0FFFFFFF */
+#define CAN_FM1R_FBM           CAN_FM1R_FBM_Msk                                /*!<Filter Mode */
+#define CAN_FM1R_FBM0_Pos      (0U)                                            
+#define CAN_FM1R_FBM0_Msk      (0x1UL << CAN_FM1R_FBM0_Pos)                     /*!< 0x00000001 */
+#define CAN_FM1R_FBM0          CAN_FM1R_FBM0_Msk                               /*!<Filter Init Mode bit 0 */
+#define CAN_FM1R_FBM1_Pos      (1U)                                            
+#define CAN_FM1R_FBM1_Msk      (0x1UL << CAN_FM1R_FBM1_Pos)                     /*!< 0x00000002 */
+#define CAN_FM1R_FBM1          CAN_FM1R_FBM1_Msk                               /*!<Filter Init Mode bit 1 */
+#define CAN_FM1R_FBM2_Pos      (2U)                                            
+#define CAN_FM1R_FBM2_Msk      (0x1UL << CAN_FM1R_FBM2_Pos)                     /*!< 0x00000004 */
+#define CAN_FM1R_FBM2          CAN_FM1R_FBM2_Msk                               /*!<Filter Init Mode bit 2 */
+#define CAN_FM1R_FBM3_Pos      (3U)                                            
+#define CAN_FM1R_FBM3_Msk      (0x1UL << CAN_FM1R_FBM3_Pos)                     /*!< 0x00000008 */
+#define CAN_FM1R_FBM3          CAN_FM1R_FBM3_Msk                               /*!<Filter Init Mode bit 3 */
+#define CAN_FM1R_FBM4_Pos      (4U)                                            
+#define CAN_FM1R_FBM4_Msk      (0x1UL << CAN_FM1R_FBM4_Pos)                     /*!< 0x00000010 */
+#define CAN_FM1R_FBM4          CAN_FM1R_FBM4_Msk                               /*!<Filter Init Mode bit 4 */
+#define CAN_FM1R_FBM5_Pos      (5U)                                            
+#define CAN_FM1R_FBM5_Msk      (0x1UL << CAN_FM1R_FBM5_Pos)                     /*!< 0x00000020 */
+#define CAN_FM1R_FBM5          CAN_FM1R_FBM5_Msk                               /*!<Filter Init Mode bit 5 */
+#define CAN_FM1R_FBM6_Pos      (6U)                                            
+#define CAN_FM1R_FBM6_Msk      (0x1UL << CAN_FM1R_FBM6_Pos)                     /*!< 0x00000040 */
+#define CAN_FM1R_FBM6          CAN_FM1R_FBM6_Msk                               /*!<Filter Init Mode bit 6 */
+#define CAN_FM1R_FBM7_Pos      (7U)                                            
+#define CAN_FM1R_FBM7_Msk      (0x1UL << CAN_FM1R_FBM7_Pos)                     /*!< 0x00000080 */
+#define CAN_FM1R_FBM7          CAN_FM1R_FBM7_Msk                               /*!<Filter Init Mode bit 7 */
+#define CAN_FM1R_FBM8_Pos      (8U)                                            
+#define CAN_FM1R_FBM8_Msk      (0x1UL << CAN_FM1R_FBM8_Pos)                     /*!< 0x00000100 */
+#define CAN_FM1R_FBM8          CAN_FM1R_FBM8_Msk                               /*!<Filter Init Mode bit 8 */
+#define CAN_FM1R_FBM9_Pos      (9U)                                            
+#define CAN_FM1R_FBM9_Msk      (0x1UL << CAN_FM1R_FBM9_Pos)                     /*!< 0x00000200 */
+#define CAN_FM1R_FBM9          CAN_FM1R_FBM9_Msk                               /*!<Filter Init Mode bit 9 */
+#define CAN_FM1R_FBM10_Pos     (10U)                                           
+#define CAN_FM1R_FBM10_Msk     (0x1UL << CAN_FM1R_FBM10_Pos)                    /*!< 0x00000400 */
+#define CAN_FM1R_FBM10         CAN_FM1R_FBM10_Msk                              /*!<Filter Init Mode bit 10 */
+#define CAN_FM1R_FBM11_Pos     (11U)                                           
+#define CAN_FM1R_FBM11_Msk     (0x1UL << CAN_FM1R_FBM11_Pos)                    /*!< 0x00000800 */
+#define CAN_FM1R_FBM11         CAN_FM1R_FBM11_Msk                              /*!<Filter Init Mode bit 11 */
+#define CAN_FM1R_FBM12_Pos     (12U)                                           
+#define CAN_FM1R_FBM12_Msk     (0x1UL << CAN_FM1R_FBM12_Pos)                    /*!< 0x00001000 */
+#define CAN_FM1R_FBM12         CAN_FM1R_FBM12_Msk                              /*!<Filter Init Mode bit 12 */
+#define CAN_FM1R_FBM13_Pos     (13U)                                           
+#define CAN_FM1R_FBM13_Msk     (0x1UL << CAN_FM1R_FBM13_Pos)                    /*!< 0x00002000 */
+#define CAN_FM1R_FBM13         CAN_FM1R_FBM13_Msk                              /*!<Filter Init Mode bit 13 */
+#define CAN_FM1R_FBM14_Pos     (14U)                                           
+#define CAN_FM1R_FBM14_Msk     (0x1UL << CAN_FM1R_FBM14_Pos)                    /*!< 0x00004000 */
+#define CAN_FM1R_FBM14         CAN_FM1R_FBM14_Msk                              /*!<Filter Init Mode bit 14 */
+#define CAN_FM1R_FBM15_Pos     (15U)                                           
+#define CAN_FM1R_FBM15_Msk     (0x1UL << CAN_FM1R_FBM15_Pos)                    /*!< 0x00008000 */
+#define CAN_FM1R_FBM15         CAN_FM1R_FBM15_Msk                              /*!<Filter Init Mode bit 15 */
+#define CAN_FM1R_FBM16_Pos     (16U)                                           
+#define CAN_FM1R_FBM16_Msk     (0x1UL << CAN_FM1R_FBM16_Pos)                    /*!< 0x00010000 */
+#define CAN_FM1R_FBM16         CAN_FM1R_FBM16_Msk                              /*!<Filter Init Mode bit 16 */
+#define CAN_FM1R_FBM17_Pos     (17U)                                           
+#define CAN_FM1R_FBM17_Msk     (0x1UL << CAN_FM1R_FBM17_Pos)                    /*!< 0x00020000 */
+#define CAN_FM1R_FBM17         CAN_FM1R_FBM17_Msk                              /*!<Filter Init Mode bit 17 */
+#define CAN_FM1R_FBM18_Pos     (18U)                                           
+#define CAN_FM1R_FBM18_Msk     (0x1UL << CAN_FM1R_FBM18_Pos)                    /*!< 0x00040000 */
+#define CAN_FM1R_FBM18         CAN_FM1R_FBM18_Msk                              /*!<Filter Init Mode bit 18 */
+#define CAN_FM1R_FBM19_Pos     (19U)                                           
+#define CAN_FM1R_FBM19_Msk     (0x1UL << CAN_FM1R_FBM19_Pos)                    /*!< 0x00080000 */
+#define CAN_FM1R_FBM19         CAN_FM1R_FBM19_Msk                              /*!<Filter Init Mode bit 19 */
+#define CAN_FM1R_FBM20_Pos     (20U)                                           
+#define CAN_FM1R_FBM20_Msk     (0x1UL << CAN_FM1R_FBM20_Pos)                    /*!< 0x00100000 */
+#define CAN_FM1R_FBM20         CAN_FM1R_FBM20_Msk                              /*!<Filter Init Mode bit 20 */
+#define CAN_FM1R_FBM21_Pos     (21U)                                           
+#define CAN_FM1R_FBM21_Msk     (0x1UL << CAN_FM1R_FBM21_Pos)                    /*!< 0x00200000 */
+#define CAN_FM1R_FBM21         CAN_FM1R_FBM21_Msk                              /*!<Filter Init Mode bit 21 */
+#define CAN_FM1R_FBM22_Pos     (22U)                                           
+#define CAN_FM1R_FBM22_Msk     (0x1UL << CAN_FM1R_FBM22_Pos)                    /*!< 0x00400000 */
+#define CAN_FM1R_FBM22         CAN_FM1R_FBM22_Msk                              /*!<Filter Init Mode bit 22 */
+#define CAN_FM1R_FBM23_Pos     (23U)                                           
+#define CAN_FM1R_FBM23_Msk     (0x1UL << CAN_FM1R_FBM23_Pos)                    /*!< 0x00800000 */
+#define CAN_FM1R_FBM23         CAN_FM1R_FBM23_Msk                              /*!<Filter Init Mode bit 23 */
+#define CAN_FM1R_FBM24_Pos     (24U)                                           
+#define CAN_FM1R_FBM24_Msk     (0x1UL << CAN_FM1R_FBM24_Pos)                    /*!< 0x01000000 */
+#define CAN_FM1R_FBM24         CAN_FM1R_FBM24_Msk                              /*!<Filter Init Mode bit 24 */
+#define CAN_FM1R_FBM25_Pos     (25U)                                           
+#define CAN_FM1R_FBM25_Msk     (0x1UL << CAN_FM1R_FBM25_Pos)                    /*!< 0x02000000 */
+#define CAN_FM1R_FBM25         CAN_FM1R_FBM25_Msk                              /*!<Filter Init Mode bit 25 */
+#define CAN_FM1R_FBM26_Pos     (26U)                                           
+#define CAN_FM1R_FBM26_Msk     (0x1UL << CAN_FM1R_FBM26_Pos)                    /*!< 0x04000000 */
+#define CAN_FM1R_FBM26         CAN_FM1R_FBM26_Msk                              /*!<Filter Init Mode bit 26 */
+#define CAN_FM1R_FBM27_Pos     (27U)                                           
+#define CAN_FM1R_FBM27_Msk     (0x1UL << CAN_FM1R_FBM27_Pos)                    /*!< 0x08000000 */
+#define CAN_FM1R_FBM27         CAN_FM1R_FBM27_Msk                              /*!<Filter Init Mode bit 27 */
+
+/*******************  Bit definition for CAN_FS1R register  *******************/
+#define CAN_FS1R_FSC_Pos       (0U)                                            
+#define CAN_FS1R_FSC_Msk       (0xFFFFFFFUL << CAN_FS1R_FSC_Pos)                /*!< 0x0FFFFFFF */
+#define CAN_FS1R_FSC           CAN_FS1R_FSC_Msk                                /*!<Filter Scale Configuration */
+#define CAN_FS1R_FSC0_Pos      (0U)                                            
+#define CAN_FS1R_FSC0_Msk      (0x1UL << CAN_FS1R_FSC0_Pos)                     /*!< 0x00000001 */
+#define CAN_FS1R_FSC0          CAN_FS1R_FSC0_Msk                               /*!<Filter Scale Configuration bit 0 */
+#define CAN_FS1R_FSC1_Pos      (1U)                                            
+#define CAN_FS1R_FSC1_Msk      (0x1UL << CAN_FS1R_FSC1_Pos)                     /*!< 0x00000002 */
+#define CAN_FS1R_FSC1          CAN_FS1R_FSC1_Msk                               /*!<Filter Scale Configuration bit 1 */
+#define CAN_FS1R_FSC2_Pos      (2U)                                            
+#define CAN_FS1R_FSC2_Msk      (0x1UL << CAN_FS1R_FSC2_Pos)                     /*!< 0x00000004 */
+#define CAN_FS1R_FSC2          CAN_FS1R_FSC2_Msk                               /*!<Filter Scale Configuration bit 2 */
+#define CAN_FS1R_FSC3_Pos      (3U)                                            
+#define CAN_FS1R_FSC3_Msk      (0x1UL << CAN_FS1R_FSC3_Pos)                     /*!< 0x00000008 */
+#define CAN_FS1R_FSC3          CAN_FS1R_FSC3_Msk                               /*!<Filter Scale Configuration bit 3 */
+#define CAN_FS1R_FSC4_Pos      (4U)                                            
+#define CAN_FS1R_FSC4_Msk      (0x1UL << CAN_FS1R_FSC4_Pos)                     /*!< 0x00000010 */
+#define CAN_FS1R_FSC4          CAN_FS1R_FSC4_Msk                               /*!<Filter Scale Configuration bit 4 */
+#define CAN_FS1R_FSC5_Pos      (5U)                                            
+#define CAN_FS1R_FSC5_Msk      (0x1UL << CAN_FS1R_FSC5_Pos)                     /*!< 0x00000020 */
+#define CAN_FS1R_FSC5          CAN_FS1R_FSC5_Msk                               /*!<Filter Scale Configuration bit 5 */
+#define CAN_FS1R_FSC6_Pos      (6U)                                            
+#define CAN_FS1R_FSC6_Msk      (0x1UL << CAN_FS1R_FSC6_Pos)                     /*!< 0x00000040 */
+#define CAN_FS1R_FSC6          CAN_FS1R_FSC6_Msk                               /*!<Filter Scale Configuration bit 6 */
+#define CAN_FS1R_FSC7_Pos      (7U)                                            
+#define CAN_FS1R_FSC7_Msk      (0x1UL << CAN_FS1R_FSC7_Pos)                     /*!< 0x00000080 */
+#define CAN_FS1R_FSC7          CAN_FS1R_FSC7_Msk                               /*!<Filter Scale Configuration bit 7 */
+#define CAN_FS1R_FSC8_Pos      (8U)                                            
+#define CAN_FS1R_FSC8_Msk      (0x1UL << CAN_FS1R_FSC8_Pos)                     /*!< 0x00000100 */
+#define CAN_FS1R_FSC8          CAN_FS1R_FSC8_Msk                               /*!<Filter Scale Configuration bit 8 */
+#define CAN_FS1R_FSC9_Pos      (9U)                                            
+#define CAN_FS1R_FSC9_Msk      (0x1UL << CAN_FS1R_FSC9_Pos)                     /*!< 0x00000200 */
+#define CAN_FS1R_FSC9          CAN_FS1R_FSC9_Msk                               /*!<Filter Scale Configuration bit 9 */
+#define CAN_FS1R_FSC10_Pos     (10U)                                           
+#define CAN_FS1R_FSC10_Msk     (0x1UL << CAN_FS1R_FSC10_Pos)                    /*!< 0x00000400 */
+#define CAN_FS1R_FSC10         CAN_FS1R_FSC10_Msk                              /*!<Filter Scale Configuration bit 10 */
+#define CAN_FS1R_FSC11_Pos     (11U)                                           
+#define CAN_FS1R_FSC11_Msk     (0x1UL << CAN_FS1R_FSC11_Pos)                    /*!< 0x00000800 */
+#define CAN_FS1R_FSC11         CAN_FS1R_FSC11_Msk                              /*!<Filter Scale Configuration bit 11 */
+#define CAN_FS1R_FSC12_Pos     (12U)                                           
+#define CAN_FS1R_FSC12_Msk     (0x1UL << CAN_FS1R_FSC12_Pos)                    /*!< 0x00001000 */
+#define CAN_FS1R_FSC12         CAN_FS1R_FSC12_Msk                              /*!<Filter Scale Configuration bit 12 */
+#define CAN_FS1R_FSC13_Pos     (13U)                                           
+#define CAN_FS1R_FSC13_Msk     (0x1UL << CAN_FS1R_FSC13_Pos)                    /*!< 0x00002000 */
+#define CAN_FS1R_FSC13         CAN_FS1R_FSC13_Msk                              /*!<Filter Scale Configuration bit 13 */
+#define CAN_FS1R_FSC14_Pos     (14U)                                           
+#define CAN_FS1R_FSC14_Msk     (0x1UL << CAN_FS1R_FSC14_Pos)                    /*!< 0x00004000 */
+#define CAN_FS1R_FSC14         CAN_FS1R_FSC14_Msk                              /*!<Filter Scale Configuration bit 14 */
+#define CAN_FS1R_FSC15_Pos     (15U)                                           
+#define CAN_FS1R_FSC15_Msk     (0x1UL << CAN_FS1R_FSC15_Pos)                    /*!< 0x00008000 */
+#define CAN_FS1R_FSC15         CAN_FS1R_FSC15_Msk                              /*!<Filter Scale Configuration bit 15 */
+#define CAN_FS1R_FSC16_Pos     (16U)                                           
+#define CAN_FS1R_FSC16_Msk     (0x1UL << CAN_FS1R_FSC16_Pos)                    /*!< 0x00010000 */
+#define CAN_FS1R_FSC16         CAN_FS1R_FSC16_Msk                              /*!<Filter Scale Configuration bit 16 */
+#define CAN_FS1R_FSC17_Pos     (17U)                                           
+#define CAN_FS1R_FSC17_Msk     (0x1UL << CAN_FS1R_FSC17_Pos)                    /*!< 0x00020000 */
+#define CAN_FS1R_FSC17         CAN_FS1R_FSC17_Msk                              /*!<Filter Scale Configuration bit 17 */
+#define CAN_FS1R_FSC18_Pos     (18U)                                           
+#define CAN_FS1R_FSC18_Msk     (0x1UL << CAN_FS1R_FSC18_Pos)                    /*!< 0x00040000 */
+#define CAN_FS1R_FSC18         CAN_FS1R_FSC18_Msk                              /*!<Filter Scale Configuration bit 18 */
+#define CAN_FS1R_FSC19_Pos     (19U)                                           
+#define CAN_FS1R_FSC19_Msk     (0x1UL << CAN_FS1R_FSC19_Pos)                    /*!< 0x00080000 */
+#define CAN_FS1R_FSC19         CAN_FS1R_FSC19_Msk                              /*!<Filter Scale Configuration bit 19 */
+#define CAN_FS1R_FSC20_Pos     (20U)                                           
+#define CAN_FS1R_FSC20_Msk     (0x1UL << CAN_FS1R_FSC20_Pos)                    /*!< 0x00100000 */
+#define CAN_FS1R_FSC20         CAN_FS1R_FSC20_Msk                              /*!<Filter Scale Configuration bit 20 */
+#define CAN_FS1R_FSC21_Pos     (21U)                                           
+#define CAN_FS1R_FSC21_Msk     (0x1UL << CAN_FS1R_FSC21_Pos)                    /*!< 0x00200000 */
+#define CAN_FS1R_FSC21         CAN_FS1R_FSC21_Msk                              /*!<Filter Scale Configuration bit 21 */
+#define CAN_FS1R_FSC22_Pos     (22U)                                           
+#define CAN_FS1R_FSC22_Msk     (0x1UL << CAN_FS1R_FSC22_Pos)                    /*!< 0x00400000 */
+#define CAN_FS1R_FSC22         CAN_FS1R_FSC22_Msk                              /*!<Filter Scale Configuration bit 22 */
+#define CAN_FS1R_FSC23_Pos     (23U)                                           
+#define CAN_FS1R_FSC23_Msk     (0x1UL << CAN_FS1R_FSC23_Pos)                    /*!< 0x00800000 */
+#define CAN_FS1R_FSC23         CAN_FS1R_FSC23_Msk                              /*!<Filter Scale Configuration bit 23 */
+#define CAN_FS1R_FSC24_Pos     (24U)                                           
+#define CAN_FS1R_FSC24_Msk     (0x1UL << CAN_FS1R_FSC24_Pos)                    /*!< 0x01000000 */
+#define CAN_FS1R_FSC24         CAN_FS1R_FSC24_Msk                              /*!<Filter Scale Configuration bit 24 */
+#define CAN_FS1R_FSC25_Pos     (25U)                                           
+#define CAN_FS1R_FSC25_Msk     (0x1UL << CAN_FS1R_FSC25_Pos)                    /*!< 0x02000000 */
+#define CAN_FS1R_FSC25         CAN_FS1R_FSC25_Msk                              /*!<Filter Scale Configuration bit 25 */
+#define CAN_FS1R_FSC26_Pos     (26U)                                           
+#define CAN_FS1R_FSC26_Msk     (0x1UL << CAN_FS1R_FSC26_Pos)                    /*!< 0x04000000 */
+#define CAN_FS1R_FSC26         CAN_FS1R_FSC26_Msk                              /*!<Filter Scale Configuration bit 26 */
+#define CAN_FS1R_FSC27_Pos     (27U)                                           
+#define CAN_FS1R_FSC27_Msk     (0x1UL << CAN_FS1R_FSC27_Pos)                    /*!< 0x08000000 */
+#define CAN_FS1R_FSC27         CAN_FS1R_FSC27_Msk                              /*!<Filter Scale Configuration bit 27 */
+
+/******************  Bit definition for CAN_FFA1R register  *******************/
+#define CAN_FFA1R_FFA_Pos      (0U)                                            
+#define CAN_FFA1R_FFA_Msk      (0xFFFFFFFUL << CAN_FFA1R_FFA_Pos)               /*!< 0x0FFFFFFF */
+#define CAN_FFA1R_FFA          CAN_FFA1R_FFA_Msk                               /*!<Filter FIFO Assignment */
+#define CAN_FFA1R_FFA0_Pos     (0U)                                            
+#define CAN_FFA1R_FFA0_Msk     (0x1UL << CAN_FFA1R_FFA0_Pos)                    /*!< 0x00000001 */
+#define CAN_FFA1R_FFA0         CAN_FFA1R_FFA0_Msk                              /*!<Filter FIFO Assignment bit 0 */
+#define CAN_FFA1R_FFA1_Pos     (1U)                                            
+#define CAN_FFA1R_FFA1_Msk     (0x1UL << CAN_FFA1R_FFA1_Pos)                    /*!< 0x00000002 */
+#define CAN_FFA1R_FFA1         CAN_FFA1R_FFA1_Msk                              /*!<Filter FIFO Assignment bit 1 */
+#define CAN_FFA1R_FFA2_Pos     (2U)                                            
+#define CAN_FFA1R_FFA2_Msk     (0x1UL << CAN_FFA1R_FFA2_Pos)                    /*!< 0x00000004 */
+#define CAN_FFA1R_FFA2         CAN_FFA1R_FFA2_Msk                              /*!<Filter FIFO Assignment bit 2 */
+#define CAN_FFA1R_FFA3_Pos     (3U)                                            
+#define CAN_FFA1R_FFA3_Msk     (0x1UL << CAN_FFA1R_FFA3_Pos)                    /*!< 0x00000008 */
+#define CAN_FFA1R_FFA3         CAN_FFA1R_FFA3_Msk                              /*!<Filter FIFO Assignment bit 3 */
+#define CAN_FFA1R_FFA4_Pos     (4U)                                            
+#define CAN_FFA1R_FFA4_Msk     (0x1UL << CAN_FFA1R_FFA4_Pos)                    /*!< 0x00000010 */
+#define CAN_FFA1R_FFA4         CAN_FFA1R_FFA4_Msk                              /*!<Filter FIFO Assignment bit 4 */
+#define CAN_FFA1R_FFA5_Pos     (5U)                                            
+#define CAN_FFA1R_FFA5_Msk     (0x1UL << CAN_FFA1R_FFA5_Pos)                    /*!< 0x00000020 */
+#define CAN_FFA1R_FFA5         CAN_FFA1R_FFA5_Msk                              /*!<Filter FIFO Assignment bit 5 */
+#define CAN_FFA1R_FFA6_Pos     (6U)                                            
+#define CAN_FFA1R_FFA6_Msk     (0x1UL << CAN_FFA1R_FFA6_Pos)                    /*!< 0x00000040 */
+#define CAN_FFA1R_FFA6         CAN_FFA1R_FFA6_Msk                              /*!<Filter FIFO Assignment bit 6 */
+#define CAN_FFA1R_FFA7_Pos     (7U)                                            
+#define CAN_FFA1R_FFA7_Msk     (0x1UL << CAN_FFA1R_FFA7_Pos)                    /*!< 0x00000080 */
+#define CAN_FFA1R_FFA7         CAN_FFA1R_FFA7_Msk                              /*!<Filter FIFO Assignment bit 7 */
+#define CAN_FFA1R_FFA8_Pos     (8U)                                            
+#define CAN_FFA1R_FFA8_Msk     (0x1UL << CAN_FFA1R_FFA8_Pos)                    /*!< 0x00000100 */
+#define CAN_FFA1R_FFA8         CAN_FFA1R_FFA8_Msk                              /*!<Filter FIFO Assignment bit 8 */
+#define CAN_FFA1R_FFA9_Pos     (9U)                                            
+#define CAN_FFA1R_FFA9_Msk     (0x1UL << CAN_FFA1R_FFA9_Pos)                    /*!< 0x00000200 */
+#define CAN_FFA1R_FFA9         CAN_FFA1R_FFA9_Msk                              /*!<Filter FIFO Assignment bit 9 */
+#define CAN_FFA1R_FFA10_Pos    (10U)                                           
+#define CAN_FFA1R_FFA10_Msk    (0x1UL << CAN_FFA1R_FFA10_Pos)                   /*!< 0x00000400 */
+#define CAN_FFA1R_FFA10        CAN_FFA1R_FFA10_Msk                             /*!<Filter FIFO Assignment bit 10 */
+#define CAN_FFA1R_FFA11_Pos    (11U)                                           
+#define CAN_FFA1R_FFA11_Msk    (0x1UL << CAN_FFA1R_FFA11_Pos)                   /*!< 0x00000800 */
+#define CAN_FFA1R_FFA11        CAN_FFA1R_FFA11_Msk                             /*!<Filter FIFO Assignment bit 11 */
+#define CAN_FFA1R_FFA12_Pos    (12U)                                           
+#define CAN_FFA1R_FFA12_Msk    (0x1UL << CAN_FFA1R_FFA12_Pos)                   /*!< 0x00001000 */
+#define CAN_FFA1R_FFA12        CAN_FFA1R_FFA12_Msk                             /*!<Filter FIFO Assignment bit 12 */
+#define CAN_FFA1R_FFA13_Pos    (13U)                                           
+#define CAN_FFA1R_FFA13_Msk    (0x1UL << CAN_FFA1R_FFA13_Pos)                   /*!< 0x00002000 */
+#define CAN_FFA1R_FFA13        CAN_FFA1R_FFA13_Msk                             /*!<Filter FIFO Assignment bit 13 */
+#define CAN_FFA1R_FFA14_Pos    (14U)                                           
+#define CAN_FFA1R_FFA14_Msk    (0x1UL << CAN_FFA1R_FFA14_Pos)                   /*!< 0x00004000 */
+#define CAN_FFA1R_FFA14        CAN_FFA1R_FFA14_Msk                             /*!<Filter FIFO Assignment bit 14 */
+#define CAN_FFA1R_FFA15_Pos    (15U)                                           
+#define CAN_FFA1R_FFA15_Msk    (0x1UL << CAN_FFA1R_FFA15_Pos)                   /*!< 0x00008000 */
+#define CAN_FFA1R_FFA15        CAN_FFA1R_FFA15_Msk                             /*!<Filter FIFO Assignment bit 15 */
+#define CAN_FFA1R_FFA16_Pos    (16U)                                           
+#define CAN_FFA1R_FFA16_Msk    (0x1UL << CAN_FFA1R_FFA16_Pos)                   /*!< 0x00010000 */
+#define CAN_FFA1R_FFA16        CAN_FFA1R_FFA16_Msk                             /*!<Filter FIFO Assignment bit 16 */
+#define CAN_FFA1R_FFA17_Pos    (17U)                                           
+#define CAN_FFA1R_FFA17_Msk    (0x1UL << CAN_FFA1R_FFA17_Pos)                   /*!< 0x00020000 */
+#define CAN_FFA1R_FFA17        CAN_FFA1R_FFA17_Msk                             /*!<Filter FIFO Assignment bit 17 */
+#define CAN_FFA1R_FFA18_Pos    (18U)                                           
+#define CAN_FFA1R_FFA18_Msk    (0x1UL << CAN_FFA1R_FFA18_Pos)                   /*!< 0x00040000 */
+#define CAN_FFA1R_FFA18        CAN_FFA1R_FFA18_Msk                             /*!<Filter FIFO Assignment bit 18 */
+#define CAN_FFA1R_FFA19_Pos    (19U)                                           
+#define CAN_FFA1R_FFA19_Msk    (0x1UL << CAN_FFA1R_FFA19_Pos)                   /*!< 0x00080000 */
+#define CAN_FFA1R_FFA19        CAN_FFA1R_FFA19_Msk                             /*!<Filter FIFO Assignment bit 19 */
+#define CAN_FFA1R_FFA20_Pos    (20U)                                           
+#define CAN_FFA1R_FFA20_Msk    (0x1UL << CAN_FFA1R_FFA20_Pos)                   /*!< 0x00100000 */
+#define CAN_FFA1R_FFA20        CAN_FFA1R_FFA20_Msk                             /*!<Filter FIFO Assignment bit 20 */
+#define CAN_FFA1R_FFA21_Pos    (21U)                                           
+#define CAN_FFA1R_FFA21_Msk    (0x1UL << CAN_FFA1R_FFA21_Pos)                   /*!< 0x00200000 */
+#define CAN_FFA1R_FFA21        CAN_FFA1R_FFA21_Msk                             /*!<Filter FIFO Assignment bit 21 */
+#define CAN_FFA1R_FFA22_Pos    (22U)                                           
+#define CAN_FFA1R_FFA22_Msk    (0x1UL << CAN_FFA1R_FFA22_Pos)                   /*!< 0x00400000 */
+#define CAN_FFA1R_FFA22        CAN_FFA1R_FFA22_Msk                             /*!<Filter FIFO Assignment bit 22 */
+#define CAN_FFA1R_FFA23_Pos    (23U)                                           
+#define CAN_FFA1R_FFA23_Msk    (0x1UL << CAN_FFA1R_FFA23_Pos)                   /*!< 0x00800000 */
+#define CAN_FFA1R_FFA23        CAN_FFA1R_FFA23_Msk                             /*!<Filter FIFO Assignment bit 23 */
+#define CAN_FFA1R_FFA24_Pos    (24U)                                           
+#define CAN_FFA1R_FFA24_Msk    (0x1UL << CAN_FFA1R_FFA24_Pos)                   /*!< 0x01000000 */
+#define CAN_FFA1R_FFA24        CAN_FFA1R_FFA24_Msk                             /*!<Filter FIFO Assignment bit 24 */
+#define CAN_FFA1R_FFA25_Pos    (25U)                                           
+#define CAN_FFA1R_FFA25_Msk    (0x1UL << CAN_FFA1R_FFA25_Pos)                   /*!< 0x02000000 */
+#define CAN_FFA1R_FFA25        CAN_FFA1R_FFA25_Msk                             /*!<Filter FIFO Assignment bit 25 */
+#define CAN_FFA1R_FFA26_Pos    (26U)                                           
+#define CAN_FFA1R_FFA26_Msk    (0x1UL << CAN_FFA1R_FFA26_Pos)                   /*!< 0x04000000 */
+#define CAN_FFA1R_FFA26        CAN_FFA1R_FFA26_Msk                             /*!<Filter FIFO Assignment bit 26 */
+#define CAN_FFA1R_FFA27_Pos    (27U)                                           
+#define CAN_FFA1R_FFA27_Msk    (0x1UL << CAN_FFA1R_FFA27_Pos)                   /*!< 0x08000000 */
+#define CAN_FFA1R_FFA27        CAN_FFA1R_FFA27_Msk                             /*!<Filter FIFO Assignment bit 27 */
+
+/*******************  Bit definition for CAN_FA1R register  *******************/
+#define CAN_FA1R_FACT_Pos      (0U)                                            
+#define CAN_FA1R_FACT_Msk      (0xFFFFFFFUL << CAN_FA1R_FACT_Pos)               /*!< 0x0FFFFFFF */
+#define CAN_FA1R_FACT          CAN_FA1R_FACT_Msk                               /*!<Filter Active */
+#define CAN_FA1R_FACT0_Pos     (0U)                                            
+#define CAN_FA1R_FACT0_Msk     (0x1UL << CAN_FA1R_FACT0_Pos)                    /*!< 0x00000001 */
+#define CAN_FA1R_FACT0         CAN_FA1R_FACT0_Msk                              /*!<Filter Active bit 0 */
+#define CAN_FA1R_FACT1_Pos     (1U)                                            
+#define CAN_FA1R_FACT1_Msk     (0x1UL << CAN_FA1R_FACT1_Pos)                    /*!< 0x00000002 */
+#define CAN_FA1R_FACT1         CAN_FA1R_FACT1_Msk                              /*!<Filter Active bit 1 */
+#define CAN_FA1R_FACT2_Pos     (2U)                                            
+#define CAN_FA1R_FACT2_Msk     (0x1UL << CAN_FA1R_FACT2_Pos)                    /*!< 0x00000004 */
+#define CAN_FA1R_FACT2         CAN_FA1R_FACT2_Msk                              /*!<Filter Active bit 2 */
+#define CAN_FA1R_FACT3_Pos     (3U)                                            
+#define CAN_FA1R_FACT3_Msk     (0x1UL << CAN_FA1R_FACT3_Pos)                    /*!< 0x00000008 */
+#define CAN_FA1R_FACT3         CAN_FA1R_FACT3_Msk                              /*!<Filter Active bit 3 */
+#define CAN_FA1R_FACT4_Pos     (4U)                                            
+#define CAN_FA1R_FACT4_Msk     (0x1UL << CAN_FA1R_FACT4_Pos)                    /*!< 0x00000010 */
+#define CAN_FA1R_FACT4         CAN_FA1R_FACT4_Msk                              /*!<Filter Active bit 4 */
+#define CAN_FA1R_FACT5_Pos     (5U)                                            
+#define CAN_FA1R_FACT5_Msk     (0x1UL << CAN_FA1R_FACT5_Pos)                    /*!< 0x00000020 */
+#define CAN_FA1R_FACT5         CAN_FA1R_FACT5_Msk                              /*!<Filter Active bit 5 */
+#define CAN_FA1R_FACT6_Pos     (6U)                                            
+#define CAN_FA1R_FACT6_Msk     (0x1UL << CAN_FA1R_FACT6_Pos)                    /*!< 0x00000040 */
+#define CAN_FA1R_FACT6         CAN_FA1R_FACT6_Msk                              /*!<Filter Active bit 6 */
+#define CAN_FA1R_FACT7_Pos     (7U)                                            
+#define CAN_FA1R_FACT7_Msk     (0x1UL << CAN_FA1R_FACT7_Pos)                    /*!< 0x00000080 */
+#define CAN_FA1R_FACT7         CAN_FA1R_FACT7_Msk                              /*!<Filter Active bit 7 */
+#define CAN_FA1R_FACT8_Pos     (8U)                                            
+#define CAN_FA1R_FACT8_Msk     (0x1UL << CAN_FA1R_FACT8_Pos)                    /*!< 0x00000100 */
+#define CAN_FA1R_FACT8         CAN_FA1R_FACT8_Msk                              /*!<Filter Active bit 8 */
+#define CAN_FA1R_FACT9_Pos     (9U)                                            
+#define CAN_FA1R_FACT9_Msk     (0x1UL << CAN_FA1R_FACT9_Pos)                    /*!< 0x00000200 */
+#define CAN_FA1R_FACT9         CAN_FA1R_FACT9_Msk                              /*!<Filter Active bit 9 */
+#define CAN_FA1R_FACT10_Pos    (10U)                                           
+#define CAN_FA1R_FACT10_Msk    (0x1UL << CAN_FA1R_FACT10_Pos)                   /*!< 0x00000400 */
+#define CAN_FA1R_FACT10        CAN_FA1R_FACT10_Msk                             /*!<Filter Active bit 10 */
+#define CAN_FA1R_FACT11_Pos    (11U)                                           
+#define CAN_FA1R_FACT11_Msk    (0x1UL << CAN_FA1R_FACT11_Pos)                   /*!< 0x00000800 */
+#define CAN_FA1R_FACT11        CAN_FA1R_FACT11_Msk                             /*!<Filter Active bit 11 */
+#define CAN_FA1R_FACT12_Pos    (12U)                                           
+#define CAN_FA1R_FACT12_Msk    (0x1UL << CAN_FA1R_FACT12_Pos)                   /*!< 0x00001000 */
+#define CAN_FA1R_FACT12        CAN_FA1R_FACT12_Msk                             /*!<Filter Active bit 12 */
+#define CAN_FA1R_FACT13_Pos    (13U)                                           
+#define CAN_FA1R_FACT13_Msk    (0x1UL << CAN_FA1R_FACT13_Pos)                   /*!< 0x00002000 */
+#define CAN_FA1R_FACT13        CAN_FA1R_FACT13_Msk                             /*!<Filter Active bit 13 */
+#define CAN_FA1R_FACT14_Pos    (14U)                                           
+#define CAN_FA1R_FACT14_Msk    (0x1UL << CAN_FA1R_FACT14_Pos)                   /*!< 0x00004000 */
+#define CAN_FA1R_FACT14        CAN_FA1R_FACT14_Msk                             /*!<Filter Active bit 14 */
+#define CAN_FA1R_FACT15_Pos    (15U)                                           
+#define CAN_FA1R_FACT15_Msk    (0x1UL << CAN_FA1R_FACT15_Pos)                   /*!< 0x00008000 */
+#define CAN_FA1R_FACT15        CAN_FA1R_FACT15_Msk                             /*!<Filter Active bit 15 */
+#define CAN_FA1R_FACT16_Pos    (16U)                                           
+#define CAN_FA1R_FACT16_Msk    (0x1UL << CAN_FA1R_FACT16_Pos)                   /*!< 0x00010000 */
+#define CAN_FA1R_FACT16        CAN_FA1R_FACT16_Msk                             /*!<Filter Active bit 16 */
+#define CAN_FA1R_FACT17_Pos    (17U)                                           
+#define CAN_FA1R_FACT17_Msk    (0x1UL << CAN_FA1R_FACT17_Pos)                   /*!< 0x00020000 */
+#define CAN_FA1R_FACT17        CAN_FA1R_FACT17_Msk                             /*!<Filter Active bit 17 */
+#define CAN_FA1R_FACT18_Pos    (18U)                                           
+#define CAN_FA1R_FACT18_Msk    (0x1UL << CAN_FA1R_FACT18_Pos)                   /*!< 0x00040000 */
+#define CAN_FA1R_FACT18        CAN_FA1R_FACT18_Msk                             /*!<Filter Active bit 18 */
+#define CAN_FA1R_FACT19_Pos    (19U)                                           
+#define CAN_FA1R_FACT19_Msk    (0x1UL << CAN_FA1R_FACT19_Pos)                   /*!< 0x00080000 */
+#define CAN_FA1R_FACT19        CAN_FA1R_FACT19_Msk                             /*!<Filter Active bit 19 */
+#define CAN_FA1R_FACT20_Pos    (20U)                                           
+#define CAN_FA1R_FACT20_Msk    (0x1UL << CAN_FA1R_FACT20_Pos)                   /*!< 0x00100000 */
+#define CAN_FA1R_FACT20        CAN_FA1R_FACT20_Msk                             /*!<Filter Active bit 20 */
+#define CAN_FA1R_FACT21_Pos    (21U)                                           
+#define CAN_FA1R_FACT21_Msk    (0x1UL << CAN_FA1R_FACT21_Pos)                   /*!< 0x00200000 */
+#define CAN_FA1R_FACT21        CAN_FA1R_FACT21_Msk                             /*!<Filter Active bit 21 */
+#define CAN_FA1R_FACT22_Pos    (22U)                                           
+#define CAN_FA1R_FACT22_Msk    (0x1UL << CAN_FA1R_FACT22_Pos)                   /*!< 0x00400000 */
+#define CAN_FA1R_FACT22        CAN_FA1R_FACT22_Msk                             /*!<Filter Active bit 22 */
+#define CAN_FA1R_FACT23_Pos    (23U)                                           
+#define CAN_FA1R_FACT23_Msk    (0x1UL << CAN_FA1R_FACT23_Pos)                   /*!< 0x00800000 */
+#define CAN_FA1R_FACT23        CAN_FA1R_FACT23_Msk                             /*!<Filter Active bit 23 */
+#define CAN_FA1R_FACT24_Pos    (24U)                                           
+#define CAN_FA1R_FACT24_Msk    (0x1UL << CAN_FA1R_FACT24_Pos)                   /*!< 0x01000000 */
+#define CAN_FA1R_FACT24        CAN_FA1R_FACT24_Msk                             /*!<Filter Active bit 24 */
+#define CAN_FA1R_FACT25_Pos    (25U)                                           
+#define CAN_FA1R_FACT25_Msk    (0x1UL << CAN_FA1R_FACT25_Pos)                   /*!< 0x02000000 */
+#define CAN_FA1R_FACT25        CAN_FA1R_FACT25_Msk                             /*!<Filter Active bit 25 */
+#define CAN_FA1R_FACT26_Pos    (26U)                                           
+#define CAN_FA1R_FACT26_Msk    (0x1UL << CAN_FA1R_FACT26_Pos)                   /*!< 0x04000000 */
+#define CAN_FA1R_FACT26        CAN_FA1R_FACT26_Msk                             /*!<Filter Active bit 26 */
+#define CAN_FA1R_FACT27_Pos    (27U)                                           
+#define CAN_FA1R_FACT27_Msk    (0x1UL << CAN_FA1R_FACT27_Pos)                   /*!< 0x08000000 */
+#define CAN_FA1R_FACT27        CAN_FA1R_FACT27_Msk                             /*!<Filter Active bit 27 */
+
+
+/*******************  Bit definition for CAN_F0R1 register  *******************/
+#define CAN_F0R1_FB0_Pos       (0U)                                            
+#define CAN_F0R1_FB0_Msk       (0x1UL << CAN_F0R1_FB0_Pos)                      /*!< 0x00000001 */
+#define CAN_F0R1_FB0           CAN_F0R1_FB0_Msk                                /*!<Filter bit 0 */
+#define CAN_F0R1_FB1_Pos       (1U)                                            
+#define CAN_F0R1_FB1_Msk       (0x1UL << CAN_F0R1_FB1_Pos)                      /*!< 0x00000002 */
+#define CAN_F0R1_FB1           CAN_F0R1_FB1_Msk                                /*!<Filter bit 1 */
+#define CAN_F0R1_FB2_Pos       (2U)                                            
+#define CAN_F0R1_FB2_Msk       (0x1UL << CAN_F0R1_FB2_Pos)                      /*!< 0x00000004 */
+#define CAN_F0R1_FB2           CAN_F0R1_FB2_Msk                                /*!<Filter bit 2 */
+#define CAN_F0R1_FB3_Pos       (3U)                                            
+#define CAN_F0R1_FB3_Msk       (0x1UL << CAN_F0R1_FB3_Pos)                      /*!< 0x00000008 */
+#define CAN_F0R1_FB3           CAN_F0R1_FB3_Msk                                /*!<Filter bit 3 */
+#define CAN_F0R1_FB4_Pos       (4U)                                            
+#define CAN_F0R1_FB4_Msk       (0x1UL << CAN_F0R1_FB4_Pos)                      /*!< 0x00000010 */
+#define CAN_F0R1_FB4           CAN_F0R1_FB4_Msk                                /*!<Filter bit 4 */
+#define CAN_F0R1_FB5_Pos       (5U)                                            
+#define CAN_F0R1_FB5_Msk       (0x1UL << CAN_F0R1_FB5_Pos)                      /*!< 0x00000020 */
+#define CAN_F0R1_FB5           CAN_F0R1_FB5_Msk                                /*!<Filter bit 5 */
+#define CAN_F0R1_FB6_Pos       (6U)                                            
+#define CAN_F0R1_FB6_Msk       (0x1UL << CAN_F0R1_FB6_Pos)                      /*!< 0x00000040 */
+#define CAN_F0R1_FB6           CAN_F0R1_FB6_Msk                                /*!<Filter bit 6 */
+#define CAN_F0R1_FB7_Pos       (7U)                                            
+#define CAN_F0R1_FB7_Msk       (0x1UL << CAN_F0R1_FB7_Pos)                      /*!< 0x00000080 */
+#define CAN_F0R1_FB7           CAN_F0R1_FB7_Msk                                /*!<Filter bit 7 */
+#define CAN_F0R1_FB8_Pos       (8U)                                            
+#define CAN_F0R1_FB8_Msk       (0x1UL << CAN_F0R1_FB8_Pos)                      /*!< 0x00000100 */
+#define CAN_F0R1_FB8           CAN_F0R1_FB8_Msk                                /*!<Filter bit 8 */
+#define CAN_F0R1_FB9_Pos       (9U)                                            
+#define CAN_F0R1_FB9_Msk       (0x1UL << CAN_F0R1_FB9_Pos)                      /*!< 0x00000200 */
+#define CAN_F0R1_FB9           CAN_F0R1_FB9_Msk                                /*!<Filter bit 9 */
+#define CAN_F0R1_FB10_Pos      (10U)                                           
+#define CAN_F0R1_FB10_Msk      (0x1UL << CAN_F0R1_FB10_Pos)                     /*!< 0x00000400 */
+#define CAN_F0R1_FB10          CAN_F0R1_FB10_Msk                               /*!<Filter bit 10 */
+#define CAN_F0R1_FB11_Pos      (11U)                                           
+#define CAN_F0R1_FB11_Msk      (0x1UL << CAN_F0R1_FB11_Pos)                     /*!< 0x00000800 */
+#define CAN_F0R1_FB11          CAN_F0R1_FB11_Msk                               /*!<Filter bit 11 */
+#define CAN_F0R1_FB12_Pos      (12U)                                           
+#define CAN_F0R1_FB12_Msk      (0x1UL << CAN_F0R1_FB12_Pos)                     /*!< 0x00001000 */
+#define CAN_F0R1_FB12          CAN_F0R1_FB12_Msk                               /*!<Filter bit 12 */
+#define CAN_F0R1_FB13_Pos      (13U)                                           
+#define CAN_F0R1_FB13_Msk      (0x1UL << CAN_F0R1_FB13_Pos)                     /*!< 0x00002000 */
+#define CAN_F0R1_FB13          CAN_F0R1_FB13_Msk                               /*!<Filter bit 13 */
+#define CAN_F0R1_FB14_Pos      (14U)                                           
+#define CAN_F0R1_FB14_Msk      (0x1UL << CAN_F0R1_FB14_Pos)                     /*!< 0x00004000 */
+#define CAN_F0R1_FB14          CAN_F0R1_FB14_Msk                               /*!<Filter bit 14 */
+#define CAN_F0R1_FB15_Pos      (15U)                                           
+#define CAN_F0R1_FB15_Msk      (0x1UL << CAN_F0R1_FB15_Pos)                     /*!< 0x00008000 */
+#define CAN_F0R1_FB15          CAN_F0R1_FB15_Msk                               /*!<Filter bit 15 */
+#define CAN_F0R1_FB16_Pos      (16U)                                           
+#define CAN_F0R1_FB16_Msk      (0x1UL << CAN_F0R1_FB16_Pos)                     /*!< 0x00010000 */
+#define CAN_F0R1_FB16          CAN_F0R1_FB16_Msk                               /*!<Filter bit 16 */
+#define CAN_F0R1_FB17_Pos      (17U)                                           
+#define CAN_F0R1_FB17_Msk      (0x1UL << CAN_F0R1_FB17_Pos)                     /*!< 0x00020000 */
+#define CAN_F0R1_FB17          CAN_F0R1_FB17_Msk                               /*!<Filter bit 17 */
+#define CAN_F0R1_FB18_Pos      (18U)                                           
+#define CAN_F0R1_FB18_Msk      (0x1UL << CAN_F0R1_FB18_Pos)                     /*!< 0x00040000 */
+#define CAN_F0R1_FB18          CAN_F0R1_FB18_Msk                               /*!<Filter bit 18 */
+#define CAN_F0R1_FB19_Pos      (19U)                                           
+#define CAN_F0R1_FB19_Msk      (0x1UL << CAN_F0R1_FB19_Pos)                     /*!< 0x00080000 */
+#define CAN_F0R1_FB19          CAN_F0R1_FB19_Msk                               /*!<Filter bit 19 */
+#define CAN_F0R1_FB20_Pos      (20U)                                           
+#define CAN_F0R1_FB20_Msk      (0x1UL << CAN_F0R1_FB20_Pos)                     /*!< 0x00100000 */
+#define CAN_F0R1_FB20          CAN_F0R1_FB20_Msk                               /*!<Filter bit 20 */
+#define CAN_F0R1_FB21_Pos      (21U)                                           
+#define CAN_F0R1_FB21_Msk      (0x1UL << CAN_F0R1_FB21_Pos)                     /*!< 0x00200000 */
+#define CAN_F0R1_FB21          CAN_F0R1_FB21_Msk                               /*!<Filter bit 21 */
+#define CAN_F0R1_FB22_Pos      (22U)                                           
+#define CAN_F0R1_FB22_Msk      (0x1UL << CAN_F0R1_FB22_Pos)                     /*!< 0x00400000 */
+#define CAN_F0R1_FB22          CAN_F0R1_FB22_Msk                               /*!<Filter bit 22 */
+#define CAN_F0R1_FB23_Pos      (23U)                                           
+#define CAN_F0R1_FB23_Msk      (0x1UL << CAN_F0R1_FB23_Pos)                     /*!< 0x00800000 */
+#define CAN_F0R1_FB23          CAN_F0R1_FB23_Msk                               /*!<Filter bit 23 */
+#define CAN_F0R1_FB24_Pos      (24U)                                           
+#define CAN_F0R1_FB24_Msk      (0x1UL << CAN_F0R1_FB24_Pos)                     /*!< 0x01000000 */
+#define CAN_F0R1_FB24          CAN_F0R1_FB24_Msk                               /*!<Filter bit 24 */
+#define CAN_F0R1_FB25_Pos      (25U)                                           
+#define CAN_F0R1_FB25_Msk      (0x1UL << CAN_F0R1_FB25_Pos)                     /*!< 0x02000000 */
+#define CAN_F0R1_FB25          CAN_F0R1_FB25_Msk                               /*!<Filter bit 25 */
+#define CAN_F0R1_FB26_Pos      (26U)                                           
+#define CAN_F0R1_FB26_Msk      (0x1UL << CAN_F0R1_FB26_Pos)                     /*!< 0x04000000 */
+#define CAN_F0R1_FB26          CAN_F0R1_FB26_Msk                               /*!<Filter bit 26 */
+#define CAN_F0R1_FB27_Pos      (27U)                                           
+#define CAN_F0R1_FB27_Msk      (0x1UL << CAN_F0R1_FB27_Pos)                     /*!< 0x08000000 */
+#define CAN_F0R1_FB27          CAN_F0R1_FB27_Msk                               /*!<Filter bit 27 */
+#define CAN_F0R1_FB28_Pos      (28U)                                           
+#define CAN_F0R1_FB28_Msk      (0x1UL << CAN_F0R1_FB28_Pos)                     /*!< 0x10000000 */
+#define CAN_F0R1_FB28          CAN_F0R1_FB28_Msk                               /*!<Filter bit 28 */
+#define CAN_F0R1_FB29_Pos      (29U)                                           
+#define CAN_F0R1_FB29_Msk      (0x1UL << CAN_F0R1_FB29_Pos)                     /*!< 0x20000000 */
+#define CAN_F0R1_FB29          CAN_F0R1_FB29_Msk                               /*!<Filter bit 29 */
+#define CAN_F0R1_FB30_Pos      (30U)                                           
+#define CAN_F0R1_FB30_Msk      (0x1UL << CAN_F0R1_FB30_Pos)                     /*!< 0x40000000 */
+#define CAN_F0R1_FB30          CAN_F0R1_FB30_Msk                               /*!<Filter bit 30 */
+#define CAN_F0R1_FB31_Pos      (31U)                                           
+#define CAN_F0R1_FB31_Msk      (0x1UL << CAN_F0R1_FB31_Pos)                     /*!< 0x80000000 */
+#define CAN_F0R1_FB31          CAN_F0R1_FB31_Msk                               /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F1R1 register  *******************/
+#define CAN_F1R1_FB0_Pos       (0U)                                            
+#define CAN_F1R1_FB0_Msk       (0x1UL << CAN_F1R1_FB0_Pos)                      /*!< 0x00000001 */
+#define CAN_F1R1_FB0           CAN_F1R1_FB0_Msk                                /*!<Filter bit 0 */
+#define CAN_F1R1_FB1_Pos       (1U)                                            
+#define CAN_F1R1_FB1_Msk       (0x1UL << CAN_F1R1_FB1_Pos)                      /*!< 0x00000002 */
+#define CAN_F1R1_FB1           CAN_F1R1_FB1_Msk                                /*!<Filter bit 1 */
+#define CAN_F1R1_FB2_Pos       (2U)                                            
+#define CAN_F1R1_FB2_Msk       (0x1UL << CAN_F1R1_FB2_Pos)                      /*!< 0x00000004 */
+#define CAN_F1R1_FB2           CAN_F1R1_FB2_Msk                                /*!<Filter bit 2 */
+#define CAN_F1R1_FB3_Pos       (3U)                                            
+#define CAN_F1R1_FB3_Msk       (0x1UL << CAN_F1R1_FB3_Pos)                      /*!< 0x00000008 */
+#define CAN_F1R1_FB3           CAN_F1R1_FB3_Msk                                /*!<Filter bit 3 */
+#define CAN_F1R1_FB4_Pos       (4U)                                            
+#define CAN_F1R1_FB4_Msk       (0x1UL << CAN_F1R1_FB4_Pos)                      /*!< 0x00000010 */
+#define CAN_F1R1_FB4           CAN_F1R1_FB4_Msk                                /*!<Filter bit 4 */
+#define CAN_F1R1_FB5_Pos       (5U)                                            
+#define CAN_F1R1_FB5_Msk       (0x1UL << CAN_F1R1_FB5_Pos)                      /*!< 0x00000020 */
+#define CAN_F1R1_FB5           CAN_F1R1_FB5_Msk                                /*!<Filter bit 5 */
+#define CAN_F1R1_FB6_Pos       (6U)                                            
+#define CAN_F1R1_FB6_Msk       (0x1UL << CAN_F1R1_FB6_Pos)                      /*!< 0x00000040 */
+#define CAN_F1R1_FB6           CAN_F1R1_FB6_Msk                                /*!<Filter bit 6 */
+#define CAN_F1R1_FB7_Pos       (7U)                                            
+#define CAN_F1R1_FB7_Msk       (0x1UL << CAN_F1R1_FB7_Pos)                      /*!< 0x00000080 */
+#define CAN_F1R1_FB7           CAN_F1R1_FB7_Msk                                /*!<Filter bit 7 */
+#define CAN_F1R1_FB8_Pos       (8U)                                            
+#define CAN_F1R1_FB8_Msk       (0x1UL << CAN_F1R1_FB8_Pos)                      /*!< 0x00000100 */
+#define CAN_F1R1_FB8           CAN_F1R1_FB8_Msk                                /*!<Filter bit 8 */
+#define CAN_F1R1_FB9_Pos       (9U)                                            
+#define CAN_F1R1_FB9_Msk       (0x1UL << CAN_F1R1_FB9_Pos)                      /*!< 0x00000200 */
+#define CAN_F1R1_FB9           CAN_F1R1_FB9_Msk                                /*!<Filter bit 9 */
+#define CAN_F1R1_FB10_Pos      (10U)                                           
+#define CAN_F1R1_FB10_Msk      (0x1UL << CAN_F1R1_FB10_Pos)                     /*!< 0x00000400 */
+#define CAN_F1R1_FB10          CAN_F1R1_FB10_Msk                               /*!<Filter bit 10 */
+#define CAN_F1R1_FB11_Pos      (11U)                                           
+#define CAN_F1R1_FB11_Msk      (0x1UL << CAN_F1R1_FB11_Pos)                     /*!< 0x00000800 */
+#define CAN_F1R1_FB11          CAN_F1R1_FB11_Msk                               /*!<Filter bit 11 */
+#define CAN_F1R1_FB12_Pos      (12U)                                           
+#define CAN_F1R1_FB12_Msk      (0x1UL << CAN_F1R1_FB12_Pos)                     /*!< 0x00001000 */
+#define CAN_F1R1_FB12          CAN_F1R1_FB12_Msk                               /*!<Filter bit 12 */
+#define CAN_F1R1_FB13_Pos      (13U)                                           
+#define CAN_F1R1_FB13_Msk      (0x1UL << CAN_F1R1_FB13_Pos)                     /*!< 0x00002000 */
+#define CAN_F1R1_FB13          CAN_F1R1_FB13_Msk                               /*!<Filter bit 13 */
+#define CAN_F1R1_FB14_Pos      (14U)                                           
+#define CAN_F1R1_FB14_Msk      (0x1UL << CAN_F1R1_FB14_Pos)                     /*!< 0x00004000 */
+#define CAN_F1R1_FB14          CAN_F1R1_FB14_Msk                               /*!<Filter bit 14 */
+#define CAN_F1R1_FB15_Pos      (15U)                                           
+#define CAN_F1R1_FB15_Msk      (0x1UL << CAN_F1R1_FB15_Pos)                     /*!< 0x00008000 */
+#define CAN_F1R1_FB15          CAN_F1R1_FB15_Msk                               /*!<Filter bit 15 */
+#define CAN_F1R1_FB16_Pos      (16U)                                           
+#define CAN_F1R1_FB16_Msk      (0x1UL << CAN_F1R1_FB16_Pos)                     /*!< 0x00010000 */
+#define CAN_F1R1_FB16          CAN_F1R1_FB16_Msk                               /*!<Filter bit 16 */
+#define CAN_F1R1_FB17_Pos      (17U)                                           
+#define CAN_F1R1_FB17_Msk      (0x1UL << CAN_F1R1_FB17_Pos)                     /*!< 0x00020000 */
+#define CAN_F1R1_FB17          CAN_F1R1_FB17_Msk                               /*!<Filter bit 17 */
+#define CAN_F1R1_FB18_Pos      (18U)                                           
+#define CAN_F1R1_FB18_Msk      (0x1UL << CAN_F1R1_FB18_Pos)                     /*!< 0x00040000 */
+#define CAN_F1R1_FB18          CAN_F1R1_FB18_Msk                               /*!<Filter bit 18 */
+#define CAN_F1R1_FB19_Pos      (19U)                                           
+#define CAN_F1R1_FB19_Msk      (0x1UL << CAN_F1R1_FB19_Pos)                     /*!< 0x00080000 */
+#define CAN_F1R1_FB19          CAN_F1R1_FB19_Msk                               /*!<Filter bit 19 */
+#define CAN_F1R1_FB20_Pos      (20U)                                           
+#define CAN_F1R1_FB20_Msk      (0x1UL << CAN_F1R1_FB20_Pos)                     /*!< 0x00100000 */
+#define CAN_F1R1_FB20          CAN_F1R1_FB20_Msk                               /*!<Filter bit 20 */
+#define CAN_F1R1_FB21_Pos      (21U)                                           
+#define CAN_F1R1_FB21_Msk      (0x1UL << CAN_F1R1_FB21_Pos)                     /*!< 0x00200000 */
+#define CAN_F1R1_FB21          CAN_F1R1_FB21_Msk                               /*!<Filter bit 21 */
+#define CAN_F1R1_FB22_Pos      (22U)                                           
+#define CAN_F1R1_FB22_Msk      (0x1UL << CAN_F1R1_FB22_Pos)                     /*!< 0x00400000 */
+#define CAN_F1R1_FB22          CAN_F1R1_FB22_Msk                               /*!<Filter bit 22 */
+#define CAN_F1R1_FB23_Pos      (23U)                                           
+#define CAN_F1R1_FB23_Msk      (0x1UL << CAN_F1R1_FB23_Pos)                     /*!< 0x00800000 */
+#define CAN_F1R1_FB23          CAN_F1R1_FB23_Msk                               /*!<Filter bit 23 */
+#define CAN_F1R1_FB24_Pos      (24U)                                           
+#define CAN_F1R1_FB24_Msk      (0x1UL << CAN_F1R1_FB24_Pos)                     /*!< 0x01000000 */
+#define CAN_F1R1_FB24          CAN_F1R1_FB24_Msk                               /*!<Filter bit 24 */
+#define CAN_F1R1_FB25_Pos      (25U)                                           
+#define CAN_F1R1_FB25_Msk      (0x1UL << CAN_F1R1_FB25_Pos)                     /*!< 0x02000000 */
+#define CAN_F1R1_FB25          CAN_F1R1_FB25_Msk                               /*!<Filter bit 25 */
+#define CAN_F1R1_FB26_Pos      (26U)                                           
+#define CAN_F1R1_FB26_Msk      (0x1UL << CAN_F1R1_FB26_Pos)                     /*!< 0x04000000 */
+#define CAN_F1R1_FB26          CAN_F1R1_FB26_Msk                               /*!<Filter bit 26 */
+#define CAN_F1R1_FB27_Pos      (27U)                                           
+#define CAN_F1R1_FB27_Msk      (0x1UL << CAN_F1R1_FB27_Pos)                     /*!< 0x08000000 */
+#define CAN_F1R1_FB27          CAN_F1R1_FB27_Msk                               /*!<Filter bit 27 */
+#define CAN_F1R1_FB28_Pos      (28U)                                           
+#define CAN_F1R1_FB28_Msk      (0x1UL << CAN_F1R1_FB28_Pos)                     /*!< 0x10000000 */
+#define CAN_F1R1_FB28          CAN_F1R1_FB28_Msk                               /*!<Filter bit 28 */
+#define CAN_F1R1_FB29_Pos      (29U)                                           
+#define CAN_F1R1_FB29_Msk      (0x1UL << CAN_F1R1_FB29_Pos)                     /*!< 0x20000000 */
+#define CAN_F1R1_FB29          CAN_F1R1_FB29_Msk                               /*!<Filter bit 29 */
+#define CAN_F1R1_FB30_Pos      (30U)                                           
+#define CAN_F1R1_FB30_Msk      (0x1UL << CAN_F1R1_FB30_Pos)                     /*!< 0x40000000 */
+#define CAN_F1R1_FB30          CAN_F1R1_FB30_Msk                               /*!<Filter bit 30 */
+#define CAN_F1R1_FB31_Pos      (31U)                                           
+#define CAN_F1R1_FB31_Msk      (0x1UL << CAN_F1R1_FB31_Pos)                     /*!< 0x80000000 */
+#define CAN_F1R1_FB31          CAN_F1R1_FB31_Msk                               /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F2R1 register  *******************/
+#define CAN_F2R1_FB0_Pos       (0U)                                            
+#define CAN_F2R1_FB0_Msk       (0x1UL << CAN_F2R1_FB0_Pos)                      /*!< 0x00000001 */
+#define CAN_F2R1_FB0           CAN_F2R1_FB0_Msk                                /*!<Filter bit 0 */
+#define CAN_F2R1_FB1_Pos       (1U)                                            
+#define CAN_F2R1_FB1_Msk       (0x1UL << CAN_F2R1_FB1_Pos)                      /*!< 0x00000002 */
+#define CAN_F2R1_FB1           CAN_F2R1_FB1_Msk                                /*!<Filter bit 1 */
+#define CAN_F2R1_FB2_Pos       (2U)                                            
+#define CAN_F2R1_FB2_Msk       (0x1UL << CAN_F2R1_FB2_Pos)                      /*!< 0x00000004 */
+#define CAN_F2R1_FB2           CAN_F2R1_FB2_Msk                                /*!<Filter bit 2 */
+#define CAN_F2R1_FB3_Pos       (3U)                                            
+#define CAN_F2R1_FB3_Msk       (0x1UL << CAN_F2R1_FB3_Pos)                      /*!< 0x00000008 */
+#define CAN_F2R1_FB3           CAN_F2R1_FB3_Msk                                /*!<Filter bit 3 */
+#define CAN_F2R1_FB4_Pos       (4U)                                            
+#define CAN_F2R1_FB4_Msk       (0x1UL << CAN_F2R1_FB4_Pos)                      /*!< 0x00000010 */
+#define CAN_F2R1_FB4           CAN_F2R1_FB4_Msk                                /*!<Filter bit 4 */
+#define CAN_F2R1_FB5_Pos       (5U)                                            
+#define CAN_F2R1_FB5_Msk       (0x1UL << CAN_F2R1_FB5_Pos)                      /*!< 0x00000020 */
+#define CAN_F2R1_FB5           CAN_F2R1_FB5_Msk                                /*!<Filter bit 5 */
+#define CAN_F2R1_FB6_Pos       (6U)                                            
+#define CAN_F2R1_FB6_Msk       (0x1UL << CAN_F2R1_FB6_Pos)                      /*!< 0x00000040 */
+#define CAN_F2R1_FB6           CAN_F2R1_FB6_Msk                                /*!<Filter bit 6 */
+#define CAN_F2R1_FB7_Pos       (7U)                                            
+#define CAN_F2R1_FB7_Msk       (0x1UL << CAN_F2R1_FB7_Pos)                      /*!< 0x00000080 */
+#define CAN_F2R1_FB7           CAN_F2R1_FB7_Msk                                /*!<Filter bit 7 */
+#define CAN_F2R1_FB8_Pos       (8U)                                            
+#define CAN_F2R1_FB8_Msk       (0x1UL << CAN_F2R1_FB8_Pos)                      /*!< 0x00000100 */
+#define CAN_F2R1_FB8           CAN_F2R1_FB8_Msk                                /*!<Filter bit 8 */
+#define CAN_F2R1_FB9_Pos       (9U)                                            
+#define CAN_F2R1_FB9_Msk       (0x1UL << CAN_F2R1_FB9_Pos)                      /*!< 0x00000200 */
+#define CAN_F2R1_FB9           CAN_F2R1_FB9_Msk                                /*!<Filter bit 9 */
+#define CAN_F2R1_FB10_Pos      (10U)                                           
+#define CAN_F2R1_FB10_Msk      (0x1UL << CAN_F2R1_FB10_Pos)                     /*!< 0x00000400 */
+#define CAN_F2R1_FB10          CAN_F2R1_FB10_Msk                               /*!<Filter bit 10 */
+#define CAN_F2R1_FB11_Pos      (11U)                                           
+#define CAN_F2R1_FB11_Msk      (0x1UL << CAN_F2R1_FB11_Pos)                     /*!< 0x00000800 */
+#define CAN_F2R1_FB11          CAN_F2R1_FB11_Msk                               /*!<Filter bit 11 */
+#define CAN_F2R1_FB12_Pos      (12U)                                           
+#define CAN_F2R1_FB12_Msk      (0x1UL << CAN_F2R1_FB12_Pos)                     /*!< 0x00001000 */
+#define CAN_F2R1_FB12          CAN_F2R1_FB12_Msk                               /*!<Filter bit 12 */
+#define CAN_F2R1_FB13_Pos      (13U)                                           
+#define CAN_F2R1_FB13_Msk      (0x1UL << CAN_F2R1_FB13_Pos)                     /*!< 0x00002000 */
+#define CAN_F2R1_FB13          CAN_F2R1_FB13_Msk                               /*!<Filter bit 13 */
+#define CAN_F2R1_FB14_Pos      (14U)                                           
+#define CAN_F2R1_FB14_Msk      (0x1UL << CAN_F2R1_FB14_Pos)                     /*!< 0x00004000 */
+#define CAN_F2R1_FB14          CAN_F2R1_FB14_Msk                               /*!<Filter bit 14 */
+#define CAN_F2R1_FB15_Pos      (15U)                                           
+#define CAN_F2R1_FB15_Msk      (0x1UL << CAN_F2R1_FB15_Pos)                     /*!< 0x00008000 */
+#define CAN_F2R1_FB15          CAN_F2R1_FB15_Msk                               /*!<Filter bit 15 */
+#define CAN_F2R1_FB16_Pos      (16U)                                           
+#define CAN_F2R1_FB16_Msk      (0x1UL << CAN_F2R1_FB16_Pos)                     /*!< 0x00010000 */
+#define CAN_F2R1_FB16          CAN_F2R1_FB16_Msk                               /*!<Filter bit 16 */
+#define CAN_F2R1_FB17_Pos      (17U)                                           
+#define CAN_F2R1_FB17_Msk      (0x1UL << CAN_F2R1_FB17_Pos)                     /*!< 0x00020000 */
+#define CAN_F2R1_FB17          CAN_F2R1_FB17_Msk                               /*!<Filter bit 17 */
+#define CAN_F2R1_FB18_Pos      (18U)                                           
+#define CAN_F2R1_FB18_Msk      (0x1UL << CAN_F2R1_FB18_Pos)                     /*!< 0x00040000 */
+#define CAN_F2R1_FB18          CAN_F2R1_FB18_Msk                               /*!<Filter bit 18 */
+#define CAN_F2R1_FB19_Pos      (19U)                                           
+#define CAN_F2R1_FB19_Msk      (0x1UL << CAN_F2R1_FB19_Pos)                     /*!< 0x00080000 */
+#define CAN_F2R1_FB19          CAN_F2R1_FB19_Msk                               /*!<Filter bit 19 */
+#define CAN_F2R1_FB20_Pos      (20U)                                           
+#define CAN_F2R1_FB20_Msk      (0x1UL << CAN_F2R1_FB20_Pos)                     /*!< 0x00100000 */
+#define CAN_F2R1_FB20          CAN_F2R1_FB20_Msk                               /*!<Filter bit 20 */
+#define CAN_F2R1_FB21_Pos      (21U)                                           
+#define CAN_F2R1_FB21_Msk      (0x1UL << CAN_F2R1_FB21_Pos)                     /*!< 0x00200000 */
+#define CAN_F2R1_FB21          CAN_F2R1_FB21_Msk                               /*!<Filter bit 21 */
+#define CAN_F2R1_FB22_Pos      (22U)                                           
+#define CAN_F2R1_FB22_Msk      (0x1UL << CAN_F2R1_FB22_Pos)                     /*!< 0x00400000 */
+#define CAN_F2R1_FB22          CAN_F2R1_FB22_Msk                               /*!<Filter bit 22 */
+#define CAN_F2R1_FB23_Pos      (23U)                                           
+#define CAN_F2R1_FB23_Msk      (0x1UL << CAN_F2R1_FB23_Pos)                     /*!< 0x00800000 */
+#define CAN_F2R1_FB23          CAN_F2R1_FB23_Msk                               /*!<Filter bit 23 */
+#define CAN_F2R1_FB24_Pos      (24U)                                           
+#define CAN_F2R1_FB24_Msk      (0x1UL << CAN_F2R1_FB24_Pos)                     /*!< 0x01000000 */
+#define CAN_F2R1_FB24          CAN_F2R1_FB24_Msk                               /*!<Filter bit 24 */
+#define CAN_F2R1_FB25_Pos      (25U)                                           
+#define CAN_F2R1_FB25_Msk      (0x1UL << CAN_F2R1_FB25_Pos)                     /*!< 0x02000000 */
+#define CAN_F2R1_FB25          CAN_F2R1_FB25_Msk                               /*!<Filter bit 25 */
+#define CAN_F2R1_FB26_Pos      (26U)                                           
+#define CAN_F2R1_FB26_Msk      (0x1UL << CAN_F2R1_FB26_Pos)                     /*!< 0x04000000 */
+#define CAN_F2R1_FB26          CAN_F2R1_FB26_Msk                               /*!<Filter bit 26 */
+#define CAN_F2R1_FB27_Pos      (27U)                                           
+#define CAN_F2R1_FB27_Msk      (0x1UL << CAN_F2R1_FB27_Pos)                     /*!< 0x08000000 */
+#define CAN_F2R1_FB27          CAN_F2R1_FB27_Msk                               /*!<Filter bit 27 */
+#define CAN_F2R1_FB28_Pos      (28U)                                           
+#define CAN_F2R1_FB28_Msk      (0x1UL << CAN_F2R1_FB28_Pos)                     /*!< 0x10000000 */
+#define CAN_F2R1_FB28          CAN_F2R1_FB28_Msk                               /*!<Filter bit 28 */
+#define CAN_F2R1_FB29_Pos      (29U)                                           
+#define CAN_F2R1_FB29_Msk      (0x1UL << CAN_F2R1_FB29_Pos)                     /*!< 0x20000000 */
+#define CAN_F2R1_FB29          CAN_F2R1_FB29_Msk                               /*!<Filter bit 29 */
+#define CAN_F2R1_FB30_Pos      (30U)                                           
+#define CAN_F2R1_FB30_Msk      (0x1UL << CAN_F2R1_FB30_Pos)                     /*!< 0x40000000 */
+#define CAN_F2R1_FB30          CAN_F2R1_FB30_Msk                               /*!<Filter bit 30 */
+#define CAN_F2R1_FB31_Pos      (31U)                                           
+#define CAN_F2R1_FB31_Msk      (0x1UL << CAN_F2R1_FB31_Pos)                     /*!< 0x80000000 */
+#define CAN_F2R1_FB31          CAN_F2R1_FB31_Msk                               /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F3R1 register  *******************/
+#define CAN_F3R1_FB0_Pos       (0U)                                            
+#define CAN_F3R1_FB0_Msk       (0x1UL << CAN_F3R1_FB0_Pos)                      /*!< 0x00000001 */
+#define CAN_F3R1_FB0           CAN_F3R1_FB0_Msk                                /*!<Filter bit 0 */
+#define CAN_F3R1_FB1_Pos       (1U)                                            
+#define CAN_F3R1_FB1_Msk       (0x1UL << CAN_F3R1_FB1_Pos)                      /*!< 0x00000002 */
+#define CAN_F3R1_FB1           CAN_F3R1_FB1_Msk                                /*!<Filter bit 1 */
+#define CAN_F3R1_FB2_Pos       (2U)                                            
+#define CAN_F3R1_FB2_Msk       (0x1UL << CAN_F3R1_FB2_Pos)                      /*!< 0x00000004 */
+#define CAN_F3R1_FB2           CAN_F3R1_FB2_Msk                                /*!<Filter bit 2 */
+#define CAN_F3R1_FB3_Pos       (3U)                                            
+#define CAN_F3R1_FB3_Msk       (0x1UL << CAN_F3R1_FB3_Pos)                      /*!< 0x00000008 */
+#define CAN_F3R1_FB3           CAN_F3R1_FB3_Msk                                /*!<Filter bit 3 */
+#define CAN_F3R1_FB4_Pos       (4U)                                            
+#define CAN_F3R1_FB4_Msk       (0x1UL << CAN_F3R1_FB4_Pos)                      /*!< 0x00000010 */
+#define CAN_F3R1_FB4           CAN_F3R1_FB4_Msk                                /*!<Filter bit 4 */
+#define CAN_F3R1_FB5_Pos       (5U)                                            
+#define CAN_F3R1_FB5_Msk       (0x1UL << CAN_F3R1_FB5_Pos)                      /*!< 0x00000020 */
+#define CAN_F3R1_FB5           CAN_F3R1_FB5_Msk                                /*!<Filter bit 5 */
+#define CAN_F3R1_FB6_Pos       (6U)                                            
+#define CAN_F3R1_FB6_Msk       (0x1UL << CAN_F3R1_FB6_Pos)                      /*!< 0x00000040 */
+#define CAN_F3R1_FB6           CAN_F3R1_FB6_Msk                                /*!<Filter bit 6 */
+#define CAN_F3R1_FB7_Pos       (7U)                                            
+#define CAN_F3R1_FB7_Msk       (0x1UL << CAN_F3R1_FB7_Pos)                      /*!< 0x00000080 */
+#define CAN_F3R1_FB7           CAN_F3R1_FB7_Msk                                /*!<Filter bit 7 */
+#define CAN_F3R1_FB8_Pos       (8U)                                            
+#define CAN_F3R1_FB8_Msk       (0x1UL << CAN_F3R1_FB8_Pos)                      /*!< 0x00000100 */
+#define CAN_F3R1_FB8           CAN_F3R1_FB8_Msk                                /*!<Filter bit 8 */
+#define CAN_F3R1_FB9_Pos       (9U)                                            
+#define CAN_F3R1_FB9_Msk       (0x1UL << CAN_F3R1_FB9_Pos)                      /*!< 0x00000200 */
+#define CAN_F3R1_FB9           CAN_F3R1_FB9_Msk                                /*!<Filter bit 9 */
+#define CAN_F3R1_FB10_Pos      (10U)                                           
+#define CAN_F3R1_FB10_Msk      (0x1UL << CAN_F3R1_FB10_Pos)                     /*!< 0x00000400 */
+#define CAN_F3R1_FB10          CAN_F3R1_FB10_Msk                               /*!<Filter bit 10 */
+#define CAN_F3R1_FB11_Pos      (11U)                                           
+#define CAN_F3R1_FB11_Msk      (0x1UL << CAN_F3R1_FB11_Pos)                     /*!< 0x00000800 */
+#define CAN_F3R1_FB11          CAN_F3R1_FB11_Msk                               /*!<Filter bit 11 */
+#define CAN_F3R1_FB12_Pos      (12U)                                           
+#define CAN_F3R1_FB12_Msk      (0x1UL << CAN_F3R1_FB12_Pos)                     /*!< 0x00001000 */
+#define CAN_F3R1_FB12          CAN_F3R1_FB12_Msk                               /*!<Filter bit 12 */
+#define CAN_F3R1_FB13_Pos      (13U)                                           
+#define CAN_F3R1_FB13_Msk      (0x1UL << CAN_F3R1_FB13_Pos)                     /*!< 0x00002000 */
+#define CAN_F3R1_FB13          CAN_F3R1_FB13_Msk                               /*!<Filter bit 13 */
+#define CAN_F3R1_FB14_Pos      (14U)                                           
+#define CAN_F3R1_FB14_Msk      (0x1UL << CAN_F3R1_FB14_Pos)                     /*!< 0x00004000 */
+#define CAN_F3R1_FB14          CAN_F3R1_FB14_Msk                               /*!<Filter bit 14 */
+#define CAN_F3R1_FB15_Pos      (15U)                                           
+#define CAN_F3R1_FB15_Msk      (0x1UL << CAN_F3R1_FB15_Pos)                     /*!< 0x00008000 */
+#define CAN_F3R1_FB15          CAN_F3R1_FB15_Msk                               /*!<Filter bit 15 */
+#define CAN_F3R1_FB16_Pos      (16U)                                           
+#define CAN_F3R1_FB16_Msk      (0x1UL << CAN_F3R1_FB16_Pos)                     /*!< 0x00010000 */
+#define CAN_F3R1_FB16          CAN_F3R1_FB16_Msk                               /*!<Filter bit 16 */
+#define CAN_F3R1_FB17_Pos      (17U)                                           
+#define CAN_F3R1_FB17_Msk      (0x1UL << CAN_F3R1_FB17_Pos)                     /*!< 0x00020000 */
+#define CAN_F3R1_FB17          CAN_F3R1_FB17_Msk                               /*!<Filter bit 17 */
+#define CAN_F3R1_FB18_Pos      (18U)                                           
+#define CAN_F3R1_FB18_Msk      (0x1UL << CAN_F3R1_FB18_Pos)                     /*!< 0x00040000 */
+#define CAN_F3R1_FB18          CAN_F3R1_FB18_Msk                               /*!<Filter bit 18 */
+#define CAN_F3R1_FB19_Pos      (19U)                                           
+#define CAN_F3R1_FB19_Msk      (0x1UL << CAN_F3R1_FB19_Pos)                     /*!< 0x00080000 */
+#define CAN_F3R1_FB19          CAN_F3R1_FB19_Msk                               /*!<Filter bit 19 */
+#define CAN_F3R1_FB20_Pos      (20U)                                           
+#define CAN_F3R1_FB20_Msk      (0x1UL << CAN_F3R1_FB20_Pos)                     /*!< 0x00100000 */
+#define CAN_F3R1_FB20          CAN_F3R1_FB20_Msk                               /*!<Filter bit 20 */
+#define CAN_F3R1_FB21_Pos      (21U)                                           
+#define CAN_F3R1_FB21_Msk      (0x1UL << CAN_F3R1_FB21_Pos)                     /*!< 0x00200000 */
+#define CAN_F3R1_FB21          CAN_F3R1_FB21_Msk                               /*!<Filter bit 21 */
+#define CAN_F3R1_FB22_Pos      (22U)                                           
+#define CAN_F3R1_FB22_Msk      (0x1UL << CAN_F3R1_FB22_Pos)                     /*!< 0x00400000 */
+#define CAN_F3R1_FB22          CAN_F3R1_FB22_Msk                               /*!<Filter bit 22 */
+#define CAN_F3R1_FB23_Pos      (23U)                                           
+#define CAN_F3R1_FB23_Msk      (0x1UL << CAN_F3R1_FB23_Pos)                     /*!< 0x00800000 */
+#define CAN_F3R1_FB23          CAN_F3R1_FB23_Msk                               /*!<Filter bit 23 */
+#define CAN_F3R1_FB24_Pos      (24U)                                           
+#define CAN_F3R1_FB24_Msk      (0x1UL << CAN_F3R1_FB24_Pos)                     /*!< 0x01000000 */
+#define CAN_F3R1_FB24          CAN_F3R1_FB24_Msk                               /*!<Filter bit 24 */
+#define CAN_F3R1_FB25_Pos      (25U)                                           
+#define CAN_F3R1_FB25_Msk      (0x1UL << CAN_F3R1_FB25_Pos)                     /*!< 0x02000000 */
+#define CAN_F3R1_FB25          CAN_F3R1_FB25_Msk                               /*!<Filter bit 25 */
+#define CAN_F3R1_FB26_Pos      (26U)                                           
+#define CAN_F3R1_FB26_Msk      (0x1UL << CAN_F3R1_FB26_Pos)                     /*!< 0x04000000 */
+#define CAN_F3R1_FB26          CAN_F3R1_FB26_Msk                               /*!<Filter bit 26 */
+#define CAN_F3R1_FB27_Pos      (27U)                                           
+#define CAN_F3R1_FB27_Msk      (0x1UL << CAN_F3R1_FB27_Pos)                     /*!< 0x08000000 */
+#define CAN_F3R1_FB27          CAN_F3R1_FB27_Msk                               /*!<Filter bit 27 */
+#define CAN_F3R1_FB28_Pos      (28U)                                           
+#define CAN_F3R1_FB28_Msk      (0x1UL << CAN_F3R1_FB28_Pos)                     /*!< 0x10000000 */
+#define CAN_F3R1_FB28          CAN_F3R1_FB28_Msk                               /*!<Filter bit 28 */
+#define CAN_F3R1_FB29_Pos      (29U)                                           
+#define CAN_F3R1_FB29_Msk      (0x1UL << CAN_F3R1_FB29_Pos)                     /*!< 0x20000000 */
+#define CAN_F3R1_FB29          CAN_F3R1_FB29_Msk                               /*!<Filter bit 29 */
+#define CAN_F3R1_FB30_Pos      (30U)                                           
+#define CAN_F3R1_FB30_Msk      (0x1UL << CAN_F3R1_FB30_Pos)                     /*!< 0x40000000 */
+#define CAN_F3R1_FB30          CAN_F3R1_FB30_Msk                               /*!<Filter bit 30 */
+#define CAN_F3R1_FB31_Pos      (31U)                                           
+#define CAN_F3R1_FB31_Msk      (0x1UL << CAN_F3R1_FB31_Pos)                     /*!< 0x80000000 */
+#define CAN_F3R1_FB31          CAN_F3R1_FB31_Msk                               /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F4R1 register  *******************/
+#define CAN_F4R1_FB0_Pos       (0U)                                            
+#define CAN_F4R1_FB0_Msk       (0x1UL << CAN_F4R1_FB0_Pos)                      /*!< 0x00000001 */
+#define CAN_F4R1_FB0           CAN_F4R1_FB0_Msk                                /*!<Filter bit 0 */
+#define CAN_F4R1_FB1_Pos       (1U)                                            
+#define CAN_F4R1_FB1_Msk       (0x1UL << CAN_F4R1_FB1_Pos)                      /*!< 0x00000002 */
+#define CAN_F4R1_FB1           CAN_F4R1_FB1_Msk                                /*!<Filter bit 1 */
+#define CAN_F4R1_FB2_Pos       (2U)                                            
+#define CAN_F4R1_FB2_Msk       (0x1UL << CAN_F4R1_FB2_Pos)                      /*!< 0x00000004 */
+#define CAN_F4R1_FB2           CAN_F4R1_FB2_Msk                                /*!<Filter bit 2 */
+#define CAN_F4R1_FB3_Pos       (3U)                                            
+#define CAN_F4R1_FB3_Msk       (0x1UL << CAN_F4R1_FB3_Pos)                      /*!< 0x00000008 */
+#define CAN_F4R1_FB3           CAN_F4R1_FB3_Msk                                /*!<Filter bit 3 */
+#define CAN_F4R1_FB4_Pos       (4U)                                            
+#define CAN_F4R1_FB4_Msk       (0x1UL << CAN_F4R1_FB4_Pos)                      /*!< 0x00000010 */
+#define CAN_F4R1_FB4           CAN_F4R1_FB4_Msk                                /*!<Filter bit 4 */
+#define CAN_F4R1_FB5_Pos       (5U)                                            
+#define CAN_F4R1_FB5_Msk       (0x1UL << CAN_F4R1_FB5_Pos)                      /*!< 0x00000020 */
+#define CAN_F4R1_FB5           CAN_F4R1_FB5_Msk                                /*!<Filter bit 5 */
+#define CAN_F4R1_FB6_Pos       (6U)                                            
+#define CAN_F4R1_FB6_Msk       (0x1UL << CAN_F4R1_FB6_Pos)                      /*!< 0x00000040 */
+#define CAN_F4R1_FB6           CAN_F4R1_FB6_Msk                                /*!<Filter bit 6 */
+#define CAN_F4R1_FB7_Pos       (7U)                                            
+#define CAN_F4R1_FB7_Msk       (0x1UL << CAN_F4R1_FB7_Pos)                      /*!< 0x00000080 */
+#define CAN_F4R1_FB7           CAN_F4R1_FB7_Msk                                /*!<Filter bit 7 */
+#define CAN_F4R1_FB8_Pos       (8U)                                            
+#define CAN_F4R1_FB8_Msk       (0x1UL << CAN_F4R1_FB8_Pos)                      /*!< 0x00000100 */
+#define CAN_F4R1_FB8           CAN_F4R1_FB8_Msk                                /*!<Filter bit 8 */
+#define CAN_F4R1_FB9_Pos       (9U)                                            
+#define CAN_F4R1_FB9_Msk       (0x1UL << CAN_F4R1_FB9_Pos)                      /*!< 0x00000200 */
+#define CAN_F4R1_FB9           CAN_F4R1_FB9_Msk                                /*!<Filter bit 9 */
+#define CAN_F4R1_FB10_Pos      (10U)                                           
+#define CAN_F4R1_FB10_Msk      (0x1UL << CAN_F4R1_FB10_Pos)                     /*!< 0x00000400 */
+#define CAN_F4R1_FB10          CAN_F4R1_FB10_Msk                               /*!<Filter bit 10 */
+#define CAN_F4R1_FB11_Pos      (11U)                                           
+#define CAN_F4R1_FB11_Msk      (0x1UL << CAN_F4R1_FB11_Pos)                     /*!< 0x00000800 */
+#define CAN_F4R1_FB11          CAN_F4R1_FB11_Msk                               /*!<Filter bit 11 */
+#define CAN_F4R1_FB12_Pos      (12U)                                           
+#define CAN_F4R1_FB12_Msk      (0x1UL << CAN_F4R1_FB12_Pos)                     /*!< 0x00001000 */
+#define CAN_F4R1_FB12          CAN_F4R1_FB12_Msk                               /*!<Filter bit 12 */
+#define CAN_F4R1_FB13_Pos      (13U)                                           
+#define CAN_F4R1_FB13_Msk      (0x1UL << CAN_F4R1_FB13_Pos)                     /*!< 0x00002000 */
+#define CAN_F4R1_FB13          CAN_F4R1_FB13_Msk                               /*!<Filter bit 13 */
+#define CAN_F4R1_FB14_Pos      (14U)                                           
+#define CAN_F4R1_FB14_Msk      (0x1UL << CAN_F4R1_FB14_Pos)                     /*!< 0x00004000 */
+#define CAN_F4R1_FB14          CAN_F4R1_FB14_Msk                               /*!<Filter bit 14 */
+#define CAN_F4R1_FB15_Pos      (15U)                                           
+#define CAN_F4R1_FB15_Msk      (0x1UL << CAN_F4R1_FB15_Pos)                     /*!< 0x00008000 */
+#define CAN_F4R1_FB15          CAN_F4R1_FB15_Msk                               /*!<Filter bit 15 */
+#define CAN_F4R1_FB16_Pos      (16U)                                           
+#define CAN_F4R1_FB16_Msk      (0x1UL << CAN_F4R1_FB16_Pos)                     /*!< 0x00010000 */
+#define CAN_F4R1_FB16          CAN_F4R1_FB16_Msk                               /*!<Filter bit 16 */
+#define CAN_F4R1_FB17_Pos      (17U)                                           
+#define CAN_F4R1_FB17_Msk      (0x1UL << CAN_F4R1_FB17_Pos)                     /*!< 0x00020000 */
+#define CAN_F4R1_FB17          CAN_F4R1_FB17_Msk                               /*!<Filter bit 17 */
+#define CAN_F4R1_FB18_Pos      (18U)                                           
+#define CAN_F4R1_FB18_Msk      (0x1UL << CAN_F4R1_FB18_Pos)                     /*!< 0x00040000 */
+#define CAN_F4R1_FB18          CAN_F4R1_FB18_Msk                               /*!<Filter bit 18 */
+#define CAN_F4R1_FB19_Pos      (19U)                                           
+#define CAN_F4R1_FB19_Msk      (0x1UL << CAN_F4R1_FB19_Pos)                     /*!< 0x00080000 */
+#define CAN_F4R1_FB19          CAN_F4R1_FB19_Msk                               /*!<Filter bit 19 */
+#define CAN_F4R1_FB20_Pos      (20U)                                           
+#define CAN_F4R1_FB20_Msk      (0x1UL << CAN_F4R1_FB20_Pos)                     /*!< 0x00100000 */
+#define CAN_F4R1_FB20          CAN_F4R1_FB20_Msk                               /*!<Filter bit 20 */
+#define CAN_F4R1_FB21_Pos      (21U)                                           
+#define CAN_F4R1_FB21_Msk      (0x1UL << CAN_F4R1_FB21_Pos)                     /*!< 0x00200000 */
+#define CAN_F4R1_FB21          CAN_F4R1_FB21_Msk                               /*!<Filter bit 21 */
+#define CAN_F4R1_FB22_Pos      (22U)                                           
+#define CAN_F4R1_FB22_Msk      (0x1UL << CAN_F4R1_FB22_Pos)                     /*!< 0x00400000 */
+#define CAN_F4R1_FB22          CAN_F4R1_FB22_Msk                               /*!<Filter bit 22 */
+#define CAN_F4R1_FB23_Pos      (23U)                                           
+#define CAN_F4R1_FB23_Msk      (0x1UL << CAN_F4R1_FB23_Pos)                     /*!< 0x00800000 */
+#define CAN_F4R1_FB23          CAN_F4R1_FB23_Msk                               /*!<Filter bit 23 */
+#define CAN_F4R1_FB24_Pos      (24U)                                           
+#define CAN_F4R1_FB24_Msk      (0x1UL << CAN_F4R1_FB24_Pos)                     /*!< 0x01000000 */
+#define CAN_F4R1_FB24          CAN_F4R1_FB24_Msk                               /*!<Filter bit 24 */
+#define CAN_F4R1_FB25_Pos      (25U)                                           
+#define CAN_F4R1_FB25_Msk      (0x1UL << CAN_F4R1_FB25_Pos)                     /*!< 0x02000000 */
+#define CAN_F4R1_FB25          CAN_F4R1_FB25_Msk                               /*!<Filter bit 25 */
+#define CAN_F4R1_FB26_Pos      (26U)                                           
+#define CAN_F4R1_FB26_Msk      (0x1UL << CAN_F4R1_FB26_Pos)                     /*!< 0x04000000 */
+#define CAN_F4R1_FB26          CAN_F4R1_FB26_Msk                               /*!<Filter bit 26 */
+#define CAN_F4R1_FB27_Pos      (27U)                                           
+#define CAN_F4R1_FB27_Msk      (0x1UL << CAN_F4R1_FB27_Pos)                     /*!< 0x08000000 */
+#define CAN_F4R1_FB27          CAN_F4R1_FB27_Msk                               /*!<Filter bit 27 */
+#define CAN_F4R1_FB28_Pos      (28U)                                           
+#define CAN_F4R1_FB28_Msk      (0x1UL << CAN_F4R1_FB28_Pos)                     /*!< 0x10000000 */
+#define CAN_F4R1_FB28          CAN_F4R1_FB28_Msk                               /*!<Filter bit 28 */
+#define CAN_F4R1_FB29_Pos      (29U)                                           
+#define CAN_F4R1_FB29_Msk      (0x1UL << CAN_F4R1_FB29_Pos)                     /*!< 0x20000000 */
+#define CAN_F4R1_FB29          CAN_F4R1_FB29_Msk                               /*!<Filter bit 29 */
+#define CAN_F4R1_FB30_Pos      (30U)                                           
+#define CAN_F4R1_FB30_Msk      (0x1UL << CAN_F4R1_FB30_Pos)                     /*!< 0x40000000 */
+#define CAN_F4R1_FB30          CAN_F4R1_FB30_Msk                               /*!<Filter bit 30 */
+#define CAN_F4R1_FB31_Pos      (31U)                                           
+#define CAN_F4R1_FB31_Msk      (0x1UL << CAN_F4R1_FB31_Pos)                     /*!< 0x80000000 */
+#define CAN_F4R1_FB31          CAN_F4R1_FB31_Msk                               /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F5R1 register  *******************/
+#define CAN_F5R1_FB0_Pos       (0U)                                            
+#define CAN_F5R1_FB0_Msk       (0x1UL << CAN_F5R1_FB0_Pos)                      /*!< 0x00000001 */
+#define CAN_F5R1_FB0           CAN_F5R1_FB0_Msk                                /*!<Filter bit 0 */
+#define CAN_F5R1_FB1_Pos       (1U)                                            
+#define CAN_F5R1_FB1_Msk       (0x1UL << CAN_F5R1_FB1_Pos)                      /*!< 0x00000002 */
+#define CAN_F5R1_FB1           CAN_F5R1_FB1_Msk                                /*!<Filter bit 1 */
+#define CAN_F5R1_FB2_Pos       (2U)                                            
+#define CAN_F5R1_FB2_Msk       (0x1UL << CAN_F5R1_FB2_Pos)                      /*!< 0x00000004 */
+#define CAN_F5R1_FB2           CAN_F5R1_FB2_Msk                                /*!<Filter bit 2 */
+#define CAN_F5R1_FB3_Pos       (3U)                                            
+#define CAN_F5R1_FB3_Msk       (0x1UL << CAN_F5R1_FB3_Pos)                      /*!< 0x00000008 */
+#define CAN_F5R1_FB3           CAN_F5R1_FB3_Msk                                /*!<Filter bit 3 */
+#define CAN_F5R1_FB4_Pos       (4U)                                            
+#define CAN_F5R1_FB4_Msk       (0x1UL << CAN_F5R1_FB4_Pos)                      /*!< 0x00000010 */
+#define CAN_F5R1_FB4           CAN_F5R1_FB4_Msk                                /*!<Filter bit 4 */
+#define CAN_F5R1_FB5_Pos       (5U)                                            
+#define CAN_F5R1_FB5_Msk       (0x1UL << CAN_F5R1_FB5_Pos)                      /*!< 0x00000020 */
+#define CAN_F5R1_FB5           CAN_F5R1_FB5_Msk                                /*!<Filter bit 5 */
+#define CAN_F5R1_FB6_Pos       (6U)                                            
+#define CAN_F5R1_FB6_Msk       (0x1UL << CAN_F5R1_FB6_Pos)                      /*!< 0x00000040 */
+#define CAN_F5R1_FB6           CAN_F5R1_FB6_Msk                                /*!<Filter bit 6 */
+#define CAN_F5R1_FB7_Pos       (7U)                                            
+#define CAN_F5R1_FB7_Msk       (0x1UL << CAN_F5R1_FB7_Pos)                      /*!< 0x00000080 */
+#define CAN_F5R1_FB7           CAN_F5R1_FB7_Msk                                /*!<Filter bit 7 */
+#define CAN_F5R1_FB8_Pos       (8U)                                            
+#define CAN_F5R1_FB8_Msk       (0x1UL << CAN_F5R1_FB8_Pos)                      /*!< 0x00000100 */
+#define CAN_F5R1_FB8           CAN_F5R1_FB8_Msk                                /*!<Filter bit 8 */
+#define CAN_F5R1_FB9_Pos       (9U)                                            
+#define CAN_F5R1_FB9_Msk       (0x1UL << CAN_F5R1_FB9_Pos)                      /*!< 0x00000200 */
+#define CAN_F5R1_FB9           CAN_F5R1_FB9_Msk                                /*!<Filter bit 9 */
+#define CAN_F5R1_FB10_Pos      (10U)                                           
+#define CAN_F5R1_FB10_Msk      (0x1UL << CAN_F5R1_FB10_Pos)                     /*!< 0x00000400 */
+#define CAN_F5R1_FB10          CAN_F5R1_FB10_Msk                               /*!<Filter bit 10 */
+#define CAN_F5R1_FB11_Pos      (11U)                                           
+#define CAN_F5R1_FB11_Msk      (0x1UL << CAN_F5R1_FB11_Pos)                     /*!< 0x00000800 */
+#define CAN_F5R1_FB11          CAN_F5R1_FB11_Msk                               /*!<Filter bit 11 */
+#define CAN_F5R1_FB12_Pos      (12U)                                           
+#define CAN_F5R1_FB12_Msk      (0x1UL << CAN_F5R1_FB12_Pos)                     /*!< 0x00001000 */
+#define CAN_F5R1_FB12          CAN_F5R1_FB12_Msk                               /*!<Filter bit 12 */
+#define CAN_F5R1_FB13_Pos      (13U)                                           
+#define CAN_F5R1_FB13_Msk      (0x1UL << CAN_F5R1_FB13_Pos)                     /*!< 0x00002000 */
+#define CAN_F5R1_FB13          CAN_F5R1_FB13_Msk                               /*!<Filter bit 13 */
+#define CAN_F5R1_FB14_Pos      (14U)                                           
+#define CAN_F5R1_FB14_Msk      (0x1UL << CAN_F5R1_FB14_Pos)                     /*!< 0x00004000 */
+#define CAN_F5R1_FB14          CAN_F5R1_FB14_Msk                               /*!<Filter bit 14 */
+#define CAN_F5R1_FB15_Pos      (15U)                                           
+#define CAN_F5R1_FB15_Msk      (0x1UL << CAN_F5R1_FB15_Pos)                     /*!< 0x00008000 */
+#define CAN_F5R1_FB15          CAN_F5R1_FB15_Msk                               /*!<Filter bit 15 */
+#define CAN_F5R1_FB16_Pos      (16U)                                           
+#define CAN_F5R1_FB16_Msk      (0x1UL << CAN_F5R1_FB16_Pos)                     /*!< 0x00010000 */
+#define CAN_F5R1_FB16          CAN_F5R1_FB16_Msk                               /*!<Filter bit 16 */
+#define CAN_F5R1_FB17_Pos      (17U)                                           
+#define CAN_F5R1_FB17_Msk      (0x1UL << CAN_F5R1_FB17_Pos)                     /*!< 0x00020000 */
+#define CAN_F5R1_FB17          CAN_F5R1_FB17_Msk                               /*!<Filter bit 17 */
+#define CAN_F5R1_FB18_Pos      (18U)                                           
+#define CAN_F5R1_FB18_Msk      (0x1UL << CAN_F5R1_FB18_Pos)                     /*!< 0x00040000 */
+#define CAN_F5R1_FB18          CAN_F5R1_FB18_Msk                               /*!<Filter bit 18 */
+#define CAN_F5R1_FB19_Pos      (19U)                                           
+#define CAN_F5R1_FB19_Msk      (0x1UL << CAN_F5R1_FB19_Pos)                     /*!< 0x00080000 */
+#define CAN_F5R1_FB19          CAN_F5R1_FB19_Msk                               /*!<Filter bit 19 */
+#define CAN_F5R1_FB20_Pos      (20U)                                           
+#define CAN_F5R1_FB20_Msk      (0x1UL << CAN_F5R1_FB20_Pos)                     /*!< 0x00100000 */
+#define CAN_F5R1_FB20          CAN_F5R1_FB20_Msk                               /*!<Filter bit 20 */
+#define CAN_F5R1_FB21_Pos      (21U)                                           
+#define CAN_F5R1_FB21_Msk      (0x1UL << CAN_F5R1_FB21_Pos)                     /*!< 0x00200000 */
+#define CAN_F5R1_FB21          CAN_F5R1_FB21_Msk                               /*!<Filter bit 21 */
+#define CAN_F5R1_FB22_Pos      (22U)                                           
+#define CAN_F5R1_FB22_Msk      (0x1UL << CAN_F5R1_FB22_Pos)                     /*!< 0x00400000 */
+#define CAN_F5R1_FB22          CAN_F5R1_FB22_Msk                               /*!<Filter bit 22 */
+#define CAN_F5R1_FB23_Pos      (23U)                                           
+#define CAN_F5R1_FB23_Msk      (0x1UL << CAN_F5R1_FB23_Pos)                     /*!< 0x00800000 */
+#define CAN_F5R1_FB23          CAN_F5R1_FB23_Msk                               /*!<Filter bit 23 */
+#define CAN_F5R1_FB24_Pos      (24U)                                           
+#define CAN_F5R1_FB24_Msk      (0x1UL << CAN_F5R1_FB24_Pos)                     /*!< 0x01000000 */
+#define CAN_F5R1_FB24          CAN_F5R1_FB24_Msk                               /*!<Filter bit 24 */
+#define CAN_F5R1_FB25_Pos      (25U)                                           
+#define CAN_F5R1_FB25_Msk      (0x1UL << CAN_F5R1_FB25_Pos)                     /*!< 0x02000000 */
+#define CAN_F5R1_FB25          CAN_F5R1_FB25_Msk                               /*!<Filter bit 25 */
+#define CAN_F5R1_FB26_Pos      (26U)                                           
+#define CAN_F5R1_FB26_Msk      (0x1UL << CAN_F5R1_FB26_Pos)                     /*!< 0x04000000 */
+#define CAN_F5R1_FB26          CAN_F5R1_FB26_Msk                               /*!<Filter bit 26 */
+#define CAN_F5R1_FB27_Pos      (27U)                                           
+#define CAN_F5R1_FB27_Msk      (0x1UL << CAN_F5R1_FB27_Pos)                     /*!< 0x08000000 */
+#define CAN_F5R1_FB27          CAN_F5R1_FB27_Msk                               /*!<Filter bit 27 */
+#define CAN_F5R1_FB28_Pos      (28U)                                           
+#define CAN_F5R1_FB28_Msk      (0x1UL << CAN_F5R1_FB28_Pos)                     /*!< 0x10000000 */
+#define CAN_F5R1_FB28          CAN_F5R1_FB28_Msk                               /*!<Filter bit 28 */
+#define CAN_F5R1_FB29_Pos      (29U)                                           
+#define CAN_F5R1_FB29_Msk      (0x1UL << CAN_F5R1_FB29_Pos)                     /*!< 0x20000000 */
+#define CAN_F5R1_FB29          CAN_F5R1_FB29_Msk                               /*!<Filter bit 29 */
+#define CAN_F5R1_FB30_Pos      (30U)                                           
+#define CAN_F5R1_FB30_Msk      (0x1UL << CAN_F5R1_FB30_Pos)                     /*!< 0x40000000 */
+#define CAN_F5R1_FB30          CAN_F5R1_FB30_Msk                               /*!<Filter bit 30 */
+#define CAN_F5R1_FB31_Pos      (31U)                                           
+#define CAN_F5R1_FB31_Msk      (0x1UL << CAN_F5R1_FB31_Pos)                     /*!< 0x80000000 */
+#define CAN_F5R1_FB31          CAN_F5R1_FB31_Msk                               /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F6R1 register  *******************/
+#define CAN_F6R1_FB0_Pos       (0U)                                            
+#define CAN_F6R1_FB0_Msk       (0x1UL << CAN_F6R1_FB0_Pos)                      /*!< 0x00000001 */
+#define CAN_F6R1_FB0           CAN_F6R1_FB0_Msk                                /*!<Filter bit 0 */
+#define CAN_F6R1_FB1_Pos       (1U)                                            
+#define CAN_F6R1_FB1_Msk       (0x1UL << CAN_F6R1_FB1_Pos)                      /*!< 0x00000002 */
+#define CAN_F6R1_FB1           CAN_F6R1_FB1_Msk                                /*!<Filter bit 1 */
+#define CAN_F6R1_FB2_Pos       (2U)                                            
+#define CAN_F6R1_FB2_Msk       (0x1UL << CAN_F6R1_FB2_Pos)                      /*!< 0x00000004 */
+#define CAN_F6R1_FB2           CAN_F6R1_FB2_Msk                                /*!<Filter bit 2 */
+#define CAN_F6R1_FB3_Pos       (3U)                                            
+#define CAN_F6R1_FB3_Msk       (0x1UL << CAN_F6R1_FB3_Pos)                      /*!< 0x00000008 */
+#define CAN_F6R1_FB3           CAN_F6R1_FB3_Msk                                /*!<Filter bit 3 */
+#define CAN_F6R1_FB4_Pos       (4U)                                            
+#define CAN_F6R1_FB4_Msk       (0x1UL << CAN_F6R1_FB4_Pos)                      /*!< 0x00000010 */
+#define CAN_F6R1_FB4           CAN_F6R1_FB4_Msk                                /*!<Filter bit 4 */
+#define CAN_F6R1_FB5_Pos       (5U)                                            
+#define CAN_F6R1_FB5_Msk       (0x1UL << CAN_F6R1_FB5_Pos)                      /*!< 0x00000020 */
+#define CAN_F6R1_FB5           CAN_F6R1_FB5_Msk                                /*!<Filter bit 5 */
+#define CAN_F6R1_FB6_Pos       (6U)                                            
+#define CAN_F6R1_FB6_Msk       (0x1UL << CAN_F6R1_FB6_Pos)                      /*!< 0x00000040 */
+#define CAN_F6R1_FB6           CAN_F6R1_FB6_Msk                                /*!<Filter bit 6 */
+#define CAN_F6R1_FB7_Pos       (7U)                                            
+#define CAN_F6R1_FB7_Msk       (0x1UL << CAN_F6R1_FB7_Pos)                      /*!< 0x00000080 */
+#define CAN_F6R1_FB7           CAN_F6R1_FB7_Msk                                /*!<Filter bit 7 */
+#define CAN_F6R1_FB8_Pos       (8U)                                            
+#define CAN_F6R1_FB8_Msk       (0x1UL << CAN_F6R1_FB8_Pos)                      /*!< 0x00000100 */
+#define CAN_F6R1_FB8           CAN_F6R1_FB8_Msk                                /*!<Filter bit 8 */
+#define CAN_F6R1_FB9_Pos       (9U)                                            
+#define CAN_F6R1_FB9_Msk       (0x1UL << CAN_F6R1_FB9_Pos)                      /*!< 0x00000200 */
+#define CAN_F6R1_FB9           CAN_F6R1_FB9_Msk                                /*!<Filter bit 9 */
+#define CAN_F6R1_FB10_Pos      (10U)                                           
+#define CAN_F6R1_FB10_Msk      (0x1UL << CAN_F6R1_FB10_Pos)                     /*!< 0x00000400 */
+#define CAN_F6R1_FB10          CAN_F6R1_FB10_Msk                               /*!<Filter bit 10 */
+#define CAN_F6R1_FB11_Pos      (11U)                                           
+#define CAN_F6R1_FB11_Msk      (0x1UL << CAN_F6R1_FB11_Pos)                     /*!< 0x00000800 */
+#define CAN_F6R1_FB11          CAN_F6R1_FB11_Msk                               /*!<Filter bit 11 */
+#define CAN_F6R1_FB12_Pos      (12U)                                           
+#define CAN_F6R1_FB12_Msk      (0x1UL << CAN_F6R1_FB12_Pos)                     /*!< 0x00001000 */
+#define CAN_F6R1_FB12          CAN_F6R1_FB12_Msk                               /*!<Filter bit 12 */
+#define CAN_F6R1_FB13_Pos      (13U)                                           
+#define CAN_F6R1_FB13_Msk      (0x1UL << CAN_F6R1_FB13_Pos)                     /*!< 0x00002000 */
+#define CAN_F6R1_FB13          CAN_F6R1_FB13_Msk                               /*!<Filter bit 13 */
+#define CAN_F6R1_FB14_Pos      (14U)                                           
+#define CAN_F6R1_FB14_Msk      (0x1UL << CAN_F6R1_FB14_Pos)                     /*!< 0x00004000 */
+#define CAN_F6R1_FB14          CAN_F6R1_FB14_Msk                               /*!<Filter bit 14 */
+#define CAN_F6R1_FB15_Pos      (15U)                                           
+#define CAN_F6R1_FB15_Msk      (0x1UL << CAN_F6R1_FB15_Pos)                     /*!< 0x00008000 */
+#define CAN_F6R1_FB15          CAN_F6R1_FB15_Msk                               /*!<Filter bit 15 */
+#define CAN_F6R1_FB16_Pos      (16U)                                           
+#define CAN_F6R1_FB16_Msk      (0x1UL << CAN_F6R1_FB16_Pos)                     /*!< 0x00010000 */
+#define CAN_F6R1_FB16          CAN_F6R1_FB16_Msk                               /*!<Filter bit 16 */
+#define CAN_F6R1_FB17_Pos      (17U)                                           
+#define CAN_F6R1_FB17_Msk      (0x1UL << CAN_F6R1_FB17_Pos)                     /*!< 0x00020000 */
+#define CAN_F6R1_FB17          CAN_F6R1_FB17_Msk                               /*!<Filter bit 17 */
+#define CAN_F6R1_FB18_Pos      (18U)                                           
+#define CAN_F6R1_FB18_Msk      (0x1UL << CAN_F6R1_FB18_Pos)                     /*!< 0x00040000 */
+#define CAN_F6R1_FB18          CAN_F6R1_FB18_Msk                               /*!<Filter bit 18 */
+#define CAN_F6R1_FB19_Pos      (19U)                                           
+#define CAN_F6R1_FB19_Msk      (0x1UL << CAN_F6R1_FB19_Pos)                     /*!< 0x00080000 */
+#define CAN_F6R1_FB19          CAN_F6R1_FB19_Msk                               /*!<Filter bit 19 */
+#define CAN_F6R1_FB20_Pos      (20U)                                           
+#define CAN_F6R1_FB20_Msk      (0x1UL << CAN_F6R1_FB20_Pos)                     /*!< 0x00100000 */
+#define CAN_F6R1_FB20          CAN_F6R1_FB20_Msk                               /*!<Filter bit 20 */
+#define CAN_F6R1_FB21_Pos      (21U)                                           
+#define CAN_F6R1_FB21_Msk      (0x1UL << CAN_F6R1_FB21_Pos)                     /*!< 0x00200000 */
+#define CAN_F6R1_FB21          CAN_F6R1_FB21_Msk                               /*!<Filter bit 21 */
+#define CAN_F6R1_FB22_Pos      (22U)                                           
+#define CAN_F6R1_FB22_Msk      (0x1UL << CAN_F6R1_FB22_Pos)                     /*!< 0x00400000 */
+#define CAN_F6R1_FB22          CAN_F6R1_FB22_Msk                               /*!<Filter bit 22 */
+#define CAN_F6R1_FB23_Pos      (23U)                                           
+#define CAN_F6R1_FB23_Msk      (0x1UL << CAN_F6R1_FB23_Pos)                     /*!< 0x00800000 */
+#define CAN_F6R1_FB23          CAN_F6R1_FB23_Msk                               /*!<Filter bit 23 */
+#define CAN_F6R1_FB24_Pos      (24U)                                           
+#define CAN_F6R1_FB24_Msk      (0x1UL << CAN_F6R1_FB24_Pos)                     /*!< 0x01000000 */
+#define CAN_F6R1_FB24          CAN_F6R1_FB24_Msk                               /*!<Filter bit 24 */
+#define CAN_F6R1_FB25_Pos      (25U)                                           
+#define CAN_F6R1_FB25_Msk      (0x1UL << CAN_F6R1_FB25_Pos)                     /*!< 0x02000000 */
+#define CAN_F6R1_FB25          CAN_F6R1_FB25_Msk                               /*!<Filter bit 25 */
+#define CAN_F6R1_FB26_Pos      (26U)                                           
+#define CAN_F6R1_FB26_Msk      (0x1UL << CAN_F6R1_FB26_Pos)                     /*!< 0x04000000 */
+#define CAN_F6R1_FB26          CAN_F6R1_FB26_Msk                               /*!<Filter bit 26 */
+#define CAN_F6R1_FB27_Pos      (27U)                                           
+#define CAN_F6R1_FB27_Msk      (0x1UL << CAN_F6R1_FB27_Pos)                     /*!< 0x08000000 */
+#define CAN_F6R1_FB27          CAN_F6R1_FB27_Msk                               /*!<Filter bit 27 */
+#define CAN_F6R1_FB28_Pos      (28U)                                           
+#define CAN_F6R1_FB28_Msk      (0x1UL << CAN_F6R1_FB28_Pos)                     /*!< 0x10000000 */
+#define CAN_F6R1_FB28          CAN_F6R1_FB28_Msk                               /*!<Filter bit 28 */
+#define CAN_F6R1_FB29_Pos      (29U)                                           
+#define CAN_F6R1_FB29_Msk      (0x1UL << CAN_F6R1_FB29_Pos)                     /*!< 0x20000000 */
+#define CAN_F6R1_FB29          CAN_F6R1_FB29_Msk                               /*!<Filter bit 29 */
+#define CAN_F6R1_FB30_Pos      (30U)                                           
+#define CAN_F6R1_FB30_Msk      (0x1UL << CAN_F6R1_FB30_Pos)                     /*!< 0x40000000 */
+#define CAN_F6R1_FB30          CAN_F6R1_FB30_Msk                               /*!<Filter bit 30 */
+#define CAN_F6R1_FB31_Pos      (31U)                                           
+#define CAN_F6R1_FB31_Msk      (0x1UL << CAN_F6R1_FB31_Pos)                     /*!< 0x80000000 */
+#define CAN_F6R1_FB31          CAN_F6R1_FB31_Msk                               /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F7R1 register  *******************/
+#define CAN_F7R1_FB0_Pos       (0U)                                            
+#define CAN_F7R1_FB0_Msk       (0x1UL << CAN_F7R1_FB0_Pos)                      /*!< 0x00000001 */
+#define CAN_F7R1_FB0           CAN_F7R1_FB0_Msk                                /*!<Filter bit 0 */
+#define CAN_F7R1_FB1_Pos       (1U)                                            
+#define CAN_F7R1_FB1_Msk       (0x1UL << CAN_F7R1_FB1_Pos)                      /*!< 0x00000002 */
+#define CAN_F7R1_FB1           CAN_F7R1_FB1_Msk                                /*!<Filter bit 1 */
+#define CAN_F7R1_FB2_Pos       (2U)                                            
+#define CAN_F7R1_FB2_Msk       (0x1UL << CAN_F7R1_FB2_Pos)                      /*!< 0x00000004 */
+#define CAN_F7R1_FB2           CAN_F7R1_FB2_Msk                                /*!<Filter bit 2 */
+#define CAN_F7R1_FB3_Pos       (3U)                                            
+#define CAN_F7R1_FB3_Msk       (0x1UL << CAN_F7R1_FB3_Pos)                      /*!< 0x00000008 */
+#define CAN_F7R1_FB3           CAN_F7R1_FB3_Msk                                /*!<Filter bit 3 */
+#define CAN_F7R1_FB4_Pos       (4U)                                            
+#define CAN_F7R1_FB4_Msk       (0x1UL << CAN_F7R1_FB4_Pos)                      /*!< 0x00000010 */
+#define CAN_F7R1_FB4           CAN_F7R1_FB4_Msk                                /*!<Filter bit 4 */
+#define CAN_F7R1_FB5_Pos       (5U)                                            
+#define CAN_F7R1_FB5_Msk       (0x1UL << CAN_F7R1_FB5_Pos)                      /*!< 0x00000020 */
+#define CAN_F7R1_FB5           CAN_F7R1_FB5_Msk                                /*!<Filter bit 5 */
+#define CAN_F7R1_FB6_Pos       (6U)                                            
+#define CAN_F7R1_FB6_Msk       (0x1UL << CAN_F7R1_FB6_Pos)                      /*!< 0x00000040 */
+#define CAN_F7R1_FB6           CAN_F7R1_FB6_Msk                                /*!<Filter bit 6 */
+#define CAN_F7R1_FB7_Pos       (7U)                                            
+#define CAN_F7R1_FB7_Msk       (0x1UL << CAN_F7R1_FB7_Pos)                      /*!< 0x00000080 */
+#define CAN_F7R1_FB7           CAN_F7R1_FB7_Msk                                /*!<Filter bit 7 */
+#define CAN_F7R1_FB8_Pos       (8U)                                            
+#define CAN_F7R1_FB8_Msk       (0x1UL << CAN_F7R1_FB8_Pos)                      /*!< 0x00000100 */
+#define CAN_F7R1_FB8           CAN_F7R1_FB8_Msk                                /*!<Filter bit 8 */
+#define CAN_F7R1_FB9_Pos       (9U)                                            
+#define CAN_F7R1_FB9_Msk       (0x1UL << CAN_F7R1_FB9_Pos)                      /*!< 0x00000200 */
+#define CAN_F7R1_FB9           CAN_F7R1_FB9_Msk                                /*!<Filter bit 9 */
+#define CAN_F7R1_FB10_Pos      (10U)                                           
+#define CAN_F7R1_FB10_Msk      (0x1UL << CAN_F7R1_FB10_Pos)                     /*!< 0x00000400 */
+#define CAN_F7R1_FB10          CAN_F7R1_FB10_Msk                               /*!<Filter bit 10 */
+#define CAN_F7R1_FB11_Pos      (11U)                                           
+#define CAN_F7R1_FB11_Msk      (0x1UL << CAN_F7R1_FB11_Pos)                     /*!< 0x00000800 */
+#define CAN_F7R1_FB11          CAN_F7R1_FB11_Msk                               /*!<Filter bit 11 */
+#define CAN_F7R1_FB12_Pos      (12U)                                           
+#define CAN_F7R1_FB12_Msk      (0x1UL << CAN_F7R1_FB12_Pos)                     /*!< 0x00001000 */
+#define CAN_F7R1_FB12          CAN_F7R1_FB12_Msk                               /*!<Filter bit 12 */
+#define CAN_F7R1_FB13_Pos      (13U)                                           
+#define CAN_F7R1_FB13_Msk      (0x1UL << CAN_F7R1_FB13_Pos)                     /*!< 0x00002000 */
+#define CAN_F7R1_FB13          CAN_F7R1_FB13_Msk                               /*!<Filter bit 13 */
+#define CAN_F7R1_FB14_Pos      (14U)                                           
+#define CAN_F7R1_FB14_Msk      (0x1UL << CAN_F7R1_FB14_Pos)                     /*!< 0x00004000 */
+#define CAN_F7R1_FB14          CAN_F7R1_FB14_Msk                               /*!<Filter bit 14 */
+#define CAN_F7R1_FB15_Pos      (15U)                                           
+#define CAN_F7R1_FB15_Msk      (0x1UL << CAN_F7R1_FB15_Pos)                     /*!< 0x00008000 */
+#define CAN_F7R1_FB15          CAN_F7R1_FB15_Msk                               /*!<Filter bit 15 */
+#define CAN_F7R1_FB16_Pos      (16U)                                           
+#define CAN_F7R1_FB16_Msk      (0x1UL << CAN_F7R1_FB16_Pos)                     /*!< 0x00010000 */
+#define CAN_F7R1_FB16          CAN_F7R1_FB16_Msk                               /*!<Filter bit 16 */
+#define CAN_F7R1_FB17_Pos      (17U)                                           
+#define CAN_F7R1_FB17_Msk      (0x1UL << CAN_F7R1_FB17_Pos)                     /*!< 0x00020000 */
+#define CAN_F7R1_FB17          CAN_F7R1_FB17_Msk                               /*!<Filter bit 17 */
+#define CAN_F7R1_FB18_Pos      (18U)                                           
+#define CAN_F7R1_FB18_Msk      (0x1UL << CAN_F7R1_FB18_Pos)                     /*!< 0x00040000 */
+#define CAN_F7R1_FB18          CAN_F7R1_FB18_Msk                               /*!<Filter bit 18 */
+#define CAN_F7R1_FB19_Pos      (19U)                                           
+#define CAN_F7R1_FB19_Msk      (0x1UL << CAN_F7R1_FB19_Pos)                     /*!< 0x00080000 */
+#define CAN_F7R1_FB19          CAN_F7R1_FB19_Msk                               /*!<Filter bit 19 */
+#define CAN_F7R1_FB20_Pos      (20U)                                           
+#define CAN_F7R1_FB20_Msk      (0x1UL << CAN_F7R1_FB20_Pos)                     /*!< 0x00100000 */
+#define CAN_F7R1_FB20          CAN_F7R1_FB20_Msk                               /*!<Filter bit 20 */
+#define CAN_F7R1_FB21_Pos      (21U)                                           
+#define CAN_F7R1_FB21_Msk      (0x1UL << CAN_F7R1_FB21_Pos)                     /*!< 0x00200000 */
+#define CAN_F7R1_FB21          CAN_F7R1_FB21_Msk                               /*!<Filter bit 21 */
+#define CAN_F7R1_FB22_Pos      (22U)                                           
+#define CAN_F7R1_FB22_Msk      (0x1UL << CAN_F7R1_FB22_Pos)                     /*!< 0x00400000 */
+#define CAN_F7R1_FB22          CAN_F7R1_FB22_Msk                               /*!<Filter bit 22 */
+#define CAN_F7R1_FB23_Pos      (23U)                                           
+#define CAN_F7R1_FB23_Msk      (0x1UL << CAN_F7R1_FB23_Pos)                     /*!< 0x00800000 */
+#define CAN_F7R1_FB23          CAN_F7R1_FB23_Msk                               /*!<Filter bit 23 */
+#define CAN_F7R1_FB24_Pos      (24U)                                           
+#define CAN_F7R1_FB24_Msk      (0x1UL << CAN_F7R1_FB24_Pos)                     /*!< 0x01000000 */
+#define CAN_F7R1_FB24          CAN_F7R1_FB24_Msk                               /*!<Filter bit 24 */
+#define CAN_F7R1_FB25_Pos      (25U)                                           
+#define CAN_F7R1_FB25_Msk      (0x1UL << CAN_F7R1_FB25_Pos)                     /*!< 0x02000000 */
+#define CAN_F7R1_FB25          CAN_F7R1_FB25_Msk                               /*!<Filter bit 25 */
+#define CAN_F7R1_FB26_Pos      (26U)                                           
+#define CAN_F7R1_FB26_Msk      (0x1UL << CAN_F7R1_FB26_Pos)                     /*!< 0x04000000 */
+#define CAN_F7R1_FB26          CAN_F7R1_FB26_Msk                               /*!<Filter bit 26 */
+#define CAN_F7R1_FB27_Pos      (27U)                                           
+#define CAN_F7R1_FB27_Msk      (0x1UL << CAN_F7R1_FB27_Pos)                     /*!< 0x08000000 */
+#define CAN_F7R1_FB27          CAN_F7R1_FB27_Msk                               /*!<Filter bit 27 */
+#define CAN_F7R1_FB28_Pos      (28U)                                           
+#define CAN_F7R1_FB28_Msk      (0x1UL << CAN_F7R1_FB28_Pos)                     /*!< 0x10000000 */
+#define CAN_F7R1_FB28          CAN_F7R1_FB28_Msk                               /*!<Filter bit 28 */
+#define CAN_F7R1_FB29_Pos      (29U)                                           
+#define CAN_F7R1_FB29_Msk      (0x1UL << CAN_F7R1_FB29_Pos)                     /*!< 0x20000000 */
+#define CAN_F7R1_FB29          CAN_F7R1_FB29_Msk                               /*!<Filter bit 29 */
+#define CAN_F7R1_FB30_Pos      (30U)                                           
+#define CAN_F7R1_FB30_Msk      (0x1UL << CAN_F7R1_FB30_Pos)                     /*!< 0x40000000 */
+#define CAN_F7R1_FB30          CAN_F7R1_FB30_Msk                               /*!<Filter bit 30 */
+#define CAN_F7R1_FB31_Pos      (31U)                                           
+#define CAN_F7R1_FB31_Msk      (0x1UL << CAN_F7R1_FB31_Pos)                     /*!< 0x80000000 */
+#define CAN_F7R1_FB31          CAN_F7R1_FB31_Msk                               /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F8R1 register  *******************/
+#define CAN_F8R1_FB0_Pos       (0U)                                            
+#define CAN_F8R1_FB0_Msk       (0x1UL << CAN_F8R1_FB0_Pos)                      /*!< 0x00000001 */
+#define CAN_F8R1_FB0           CAN_F8R1_FB0_Msk                                /*!<Filter bit 0 */
+#define CAN_F8R1_FB1_Pos       (1U)                                            
+#define CAN_F8R1_FB1_Msk       (0x1UL << CAN_F8R1_FB1_Pos)                      /*!< 0x00000002 */
+#define CAN_F8R1_FB1           CAN_F8R1_FB1_Msk                                /*!<Filter bit 1 */
+#define CAN_F8R1_FB2_Pos       (2U)                                            
+#define CAN_F8R1_FB2_Msk       (0x1UL << CAN_F8R1_FB2_Pos)                      /*!< 0x00000004 */
+#define CAN_F8R1_FB2           CAN_F8R1_FB2_Msk                                /*!<Filter bit 2 */
+#define CAN_F8R1_FB3_Pos       (3U)                                            
+#define CAN_F8R1_FB3_Msk       (0x1UL << CAN_F8R1_FB3_Pos)                      /*!< 0x00000008 */
+#define CAN_F8R1_FB3           CAN_F8R1_FB3_Msk                                /*!<Filter bit 3 */
+#define CAN_F8R1_FB4_Pos       (4U)                                            
+#define CAN_F8R1_FB4_Msk       (0x1UL << CAN_F8R1_FB4_Pos)                      /*!< 0x00000010 */
+#define CAN_F8R1_FB4           CAN_F8R1_FB4_Msk                                /*!<Filter bit 4 */
+#define CAN_F8R1_FB5_Pos       (5U)                                            
+#define CAN_F8R1_FB5_Msk       (0x1UL << CAN_F8R1_FB5_Pos)                      /*!< 0x00000020 */
+#define CAN_F8R1_FB5           CAN_F8R1_FB5_Msk                                /*!<Filter bit 5 */
+#define CAN_F8R1_FB6_Pos       (6U)                                            
+#define CAN_F8R1_FB6_Msk       (0x1UL << CAN_F8R1_FB6_Pos)                      /*!< 0x00000040 */
+#define CAN_F8R1_FB6           CAN_F8R1_FB6_Msk                                /*!<Filter bit 6 */
+#define CAN_F8R1_FB7_Pos       (7U)                                            
+#define CAN_F8R1_FB7_Msk       (0x1UL << CAN_F8R1_FB7_Pos)                      /*!< 0x00000080 */
+#define CAN_F8R1_FB7           CAN_F8R1_FB7_Msk                                /*!<Filter bit 7 */
+#define CAN_F8R1_FB8_Pos       (8U)                                            
+#define CAN_F8R1_FB8_Msk       (0x1UL << CAN_F8R1_FB8_Pos)                      /*!< 0x00000100 */
+#define CAN_F8R1_FB8           CAN_F8R1_FB8_Msk                                /*!<Filter bit 8 */
+#define CAN_F8R1_FB9_Pos       (9U)                                            
+#define CAN_F8R1_FB9_Msk       (0x1UL << CAN_F8R1_FB9_Pos)                      /*!< 0x00000200 */
+#define CAN_F8R1_FB9           CAN_F8R1_FB9_Msk                                /*!<Filter bit 9 */
+#define CAN_F8R1_FB10_Pos      (10U)                                           
+#define CAN_F8R1_FB10_Msk      (0x1UL << CAN_F8R1_FB10_Pos)                     /*!< 0x00000400 */
+#define CAN_F8R1_FB10          CAN_F8R1_FB10_Msk                               /*!<Filter bit 10 */
+#define CAN_F8R1_FB11_Pos      (11U)                                           
+#define CAN_F8R1_FB11_Msk      (0x1UL << CAN_F8R1_FB11_Pos)                     /*!< 0x00000800 */
+#define CAN_F8R1_FB11          CAN_F8R1_FB11_Msk                               /*!<Filter bit 11 */
+#define CAN_F8R1_FB12_Pos      (12U)                                           
+#define CAN_F8R1_FB12_Msk      (0x1UL << CAN_F8R1_FB12_Pos)                     /*!< 0x00001000 */
+#define CAN_F8R1_FB12          CAN_F8R1_FB12_Msk                               /*!<Filter bit 12 */
+#define CAN_F8R1_FB13_Pos      (13U)                                           
+#define CAN_F8R1_FB13_Msk      (0x1UL << CAN_F8R1_FB13_Pos)                     /*!< 0x00002000 */
+#define CAN_F8R1_FB13          CAN_F8R1_FB13_Msk                               /*!<Filter bit 13 */
+#define CAN_F8R1_FB14_Pos      (14U)                                           
+#define CAN_F8R1_FB14_Msk      (0x1UL << CAN_F8R1_FB14_Pos)                     /*!< 0x00004000 */
+#define CAN_F8R1_FB14          CAN_F8R1_FB14_Msk                               /*!<Filter bit 14 */
+#define CAN_F8R1_FB15_Pos      (15U)                                           
+#define CAN_F8R1_FB15_Msk      (0x1UL << CAN_F8R1_FB15_Pos)                     /*!< 0x00008000 */
+#define CAN_F8R1_FB15          CAN_F8R1_FB15_Msk                               /*!<Filter bit 15 */
+#define CAN_F8R1_FB16_Pos      (16U)                                           
+#define CAN_F8R1_FB16_Msk      (0x1UL << CAN_F8R1_FB16_Pos)                     /*!< 0x00010000 */
+#define CAN_F8R1_FB16          CAN_F8R1_FB16_Msk                               /*!<Filter bit 16 */
+#define CAN_F8R1_FB17_Pos      (17U)                                           
+#define CAN_F8R1_FB17_Msk      (0x1UL << CAN_F8R1_FB17_Pos)                     /*!< 0x00020000 */
+#define CAN_F8R1_FB17          CAN_F8R1_FB17_Msk                               /*!<Filter bit 17 */
+#define CAN_F8R1_FB18_Pos      (18U)                                           
+#define CAN_F8R1_FB18_Msk      (0x1UL << CAN_F8R1_FB18_Pos)                     /*!< 0x00040000 */
+#define CAN_F8R1_FB18          CAN_F8R1_FB18_Msk                               /*!<Filter bit 18 */
+#define CAN_F8R1_FB19_Pos      (19U)                                           
+#define CAN_F8R1_FB19_Msk      (0x1UL << CAN_F8R1_FB19_Pos)                     /*!< 0x00080000 */
+#define CAN_F8R1_FB19          CAN_F8R1_FB19_Msk                               /*!<Filter bit 19 */
+#define CAN_F8R1_FB20_Pos      (20U)                                           
+#define CAN_F8R1_FB20_Msk      (0x1UL << CAN_F8R1_FB20_Pos)                     /*!< 0x00100000 */
+#define CAN_F8R1_FB20          CAN_F8R1_FB20_Msk                               /*!<Filter bit 20 */
+#define CAN_F8R1_FB21_Pos      (21U)                                           
+#define CAN_F8R1_FB21_Msk      (0x1UL << CAN_F8R1_FB21_Pos)                     /*!< 0x00200000 */
+#define CAN_F8R1_FB21          CAN_F8R1_FB21_Msk                               /*!<Filter bit 21 */
+#define CAN_F8R1_FB22_Pos      (22U)                                           
+#define CAN_F8R1_FB22_Msk      (0x1UL << CAN_F8R1_FB22_Pos)                     /*!< 0x00400000 */
+#define CAN_F8R1_FB22          CAN_F8R1_FB22_Msk                               /*!<Filter bit 22 */
+#define CAN_F8R1_FB23_Pos      (23U)                                           
+#define CAN_F8R1_FB23_Msk      (0x1UL << CAN_F8R1_FB23_Pos)                     /*!< 0x00800000 */
+#define CAN_F8R1_FB23          CAN_F8R1_FB23_Msk                               /*!<Filter bit 23 */
+#define CAN_F8R1_FB24_Pos      (24U)                                           
+#define CAN_F8R1_FB24_Msk      (0x1UL << CAN_F8R1_FB24_Pos)                     /*!< 0x01000000 */
+#define CAN_F8R1_FB24          CAN_F8R1_FB24_Msk                               /*!<Filter bit 24 */
+#define CAN_F8R1_FB25_Pos      (25U)                                           
+#define CAN_F8R1_FB25_Msk      (0x1UL << CAN_F8R1_FB25_Pos)                     /*!< 0x02000000 */
+#define CAN_F8R1_FB25          CAN_F8R1_FB25_Msk                               /*!<Filter bit 25 */
+#define CAN_F8R1_FB26_Pos      (26U)                                           
+#define CAN_F8R1_FB26_Msk      (0x1UL << CAN_F8R1_FB26_Pos)                     /*!< 0x04000000 */
+#define CAN_F8R1_FB26          CAN_F8R1_FB26_Msk                               /*!<Filter bit 26 */
+#define CAN_F8R1_FB27_Pos      (27U)                                           
+#define CAN_F8R1_FB27_Msk      (0x1UL << CAN_F8R1_FB27_Pos)                     /*!< 0x08000000 */
+#define CAN_F8R1_FB27          CAN_F8R1_FB27_Msk                               /*!<Filter bit 27 */
+#define CAN_F8R1_FB28_Pos      (28U)                                           
+#define CAN_F8R1_FB28_Msk      (0x1UL << CAN_F8R1_FB28_Pos)                     /*!< 0x10000000 */
+#define CAN_F8R1_FB28          CAN_F8R1_FB28_Msk                               /*!<Filter bit 28 */
+#define CAN_F8R1_FB29_Pos      (29U)                                           
+#define CAN_F8R1_FB29_Msk      (0x1UL << CAN_F8R1_FB29_Pos)                     /*!< 0x20000000 */
+#define CAN_F8R1_FB29          CAN_F8R1_FB29_Msk                               /*!<Filter bit 29 */
+#define CAN_F8R1_FB30_Pos      (30U)                                           
+#define CAN_F8R1_FB30_Msk      (0x1UL << CAN_F8R1_FB30_Pos)                     /*!< 0x40000000 */
+#define CAN_F8R1_FB30          CAN_F8R1_FB30_Msk                               /*!<Filter bit 30 */
+#define CAN_F8R1_FB31_Pos      (31U)                                           
+#define CAN_F8R1_FB31_Msk      (0x1UL << CAN_F8R1_FB31_Pos)                     /*!< 0x80000000 */
+#define CAN_F8R1_FB31          CAN_F8R1_FB31_Msk                               /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F9R1 register  *******************/
+#define CAN_F9R1_FB0_Pos       (0U)                                            
+#define CAN_F9R1_FB0_Msk       (0x1UL << CAN_F9R1_FB0_Pos)                      /*!< 0x00000001 */
+#define CAN_F9R1_FB0           CAN_F9R1_FB0_Msk                                /*!<Filter bit 0 */
+#define CAN_F9R1_FB1_Pos       (1U)                                            
+#define CAN_F9R1_FB1_Msk       (0x1UL << CAN_F9R1_FB1_Pos)                      /*!< 0x00000002 */
+#define CAN_F9R1_FB1           CAN_F9R1_FB1_Msk                                /*!<Filter bit 1 */
+#define CAN_F9R1_FB2_Pos       (2U)                                            
+#define CAN_F9R1_FB2_Msk       (0x1UL << CAN_F9R1_FB2_Pos)                      /*!< 0x00000004 */
+#define CAN_F9R1_FB2           CAN_F9R1_FB2_Msk                                /*!<Filter bit 2 */
+#define CAN_F9R1_FB3_Pos       (3U)                                            
+#define CAN_F9R1_FB3_Msk       (0x1UL << CAN_F9R1_FB3_Pos)                      /*!< 0x00000008 */
+#define CAN_F9R1_FB3           CAN_F9R1_FB3_Msk                                /*!<Filter bit 3 */
+#define CAN_F9R1_FB4_Pos       (4U)                                            
+#define CAN_F9R1_FB4_Msk       (0x1UL << CAN_F9R1_FB4_Pos)                      /*!< 0x00000010 */
+#define CAN_F9R1_FB4           CAN_F9R1_FB4_Msk                                /*!<Filter bit 4 */
+#define CAN_F9R1_FB5_Pos       (5U)                                            
+#define CAN_F9R1_FB5_Msk       (0x1UL << CAN_F9R1_FB5_Pos)                      /*!< 0x00000020 */
+#define CAN_F9R1_FB5           CAN_F9R1_FB5_Msk                                /*!<Filter bit 5 */
+#define CAN_F9R1_FB6_Pos       (6U)                                            
+#define CAN_F9R1_FB6_Msk       (0x1UL << CAN_F9R1_FB6_Pos)                      /*!< 0x00000040 */
+#define CAN_F9R1_FB6           CAN_F9R1_FB6_Msk                                /*!<Filter bit 6 */
+#define CAN_F9R1_FB7_Pos       (7U)                                            
+#define CAN_F9R1_FB7_Msk       (0x1UL << CAN_F9R1_FB7_Pos)                      /*!< 0x00000080 */
+#define CAN_F9R1_FB7           CAN_F9R1_FB7_Msk                                /*!<Filter bit 7 */
+#define CAN_F9R1_FB8_Pos       (8U)                                            
+#define CAN_F9R1_FB8_Msk       (0x1UL << CAN_F9R1_FB8_Pos)                      /*!< 0x00000100 */
+#define CAN_F9R1_FB8           CAN_F9R1_FB8_Msk                                /*!<Filter bit 8 */
+#define CAN_F9R1_FB9_Pos       (9U)                                            
+#define CAN_F9R1_FB9_Msk       (0x1UL << CAN_F9R1_FB9_Pos)                      /*!< 0x00000200 */
+#define CAN_F9R1_FB9           CAN_F9R1_FB9_Msk                                /*!<Filter bit 9 */
+#define CAN_F9R1_FB10_Pos      (10U)                                           
+#define CAN_F9R1_FB10_Msk      (0x1UL << CAN_F9R1_FB10_Pos)                     /*!< 0x00000400 */
+#define CAN_F9R1_FB10          CAN_F9R1_FB10_Msk                               /*!<Filter bit 10 */
+#define CAN_F9R1_FB11_Pos      (11U)                                           
+#define CAN_F9R1_FB11_Msk      (0x1UL << CAN_F9R1_FB11_Pos)                     /*!< 0x00000800 */
+#define CAN_F9R1_FB11          CAN_F9R1_FB11_Msk                               /*!<Filter bit 11 */
+#define CAN_F9R1_FB12_Pos      (12U)                                           
+#define CAN_F9R1_FB12_Msk      (0x1UL << CAN_F9R1_FB12_Pos)                     /*!< 0x00001000 */
+#define CAN_F9R1_FB12          CAN_F9R1_FB12_Msk                               /*!<Filter bit 12 */
+#define CAN_F9R1_FB13_Pos      (13U)                                           
+#define CAN_F9R1_FB13_Msk      (0x1UL << CAN_F9R1_FB13_Pos)                     /*!< 0x00002000 */
+#define CAN_F9R1_FB13          CAN_F9R1_FB13_Msk                               /*!<Filter bit 13 */
+#define CAN_F9R1_FB14_Pos      (14U)                                           
+#define CAN_F9R1_FB14_Msk      (0x1UL << CAN_F9R1_FB14_Pos)                     /*!< 0x00004000 */
+#define CAN_F9R1_FB14          CAN_F9R1_FB14_Msk                               /*!<Filter bit 14 */
+#define CAN_F9R1_FB15_Pos      (15U)                                           
+#define CAN_F9R1_FB15_Msk      (0x1UL << CAN_F9R1_FB15_Pos)                     /*!< 0x00008000 */
+#define CAN_F9R1_FB15          CAN_F9R1_FB15_Msk                               /*!<Filter bit 15 */
+#define CAN_F9R1_FB16_Pos      (16U)                                           
+#define CAN_F9R1_FB16_Msk      (0x1UL << CAN_F9R1_FB16_Pos)                     /*!< 0x00010000 */
+#define CAN_F9R1_FB16          CAN_F9R1_FB16_Msk                               /*!<Filter bit 16 */
+#define CAN_F9R1_FB17_Pos      (17U)                                           
+#define CAN_F9R1_FB17_Msk      (0x1UL << CAN_F9R1_FB17_Pos)                     /*!< 0x00020000 */
+#define CAN_F9R1_FB17          CAN_F9R1_FB17_Msk                               /*!<Filter bit 17 */
+#define CAN_F9R1_FB18_Pos      (18U)                                           
+#define CAN_F9R1_FB18_Msk      (0x1UL << CAN_F9R1_FB18_Pos)                     /*!< 0x00040000 */
+#define CAN_F9R1_FB18          CAN_F9R1_FB18_Msk                               /*!<Filter bit 18 */
+#define CAN_F9R1_FB19_Pos      (19U)                                           
+#define CAN_F9R1_FB19_Msk      (0x1UL << CAN_F9R1_FB19_Pos)                     /*!< 0x00080000 */
+#define CAN_F9R1_FB19          CAN_F9R1_FB19_Msk                               /*!<Filter bit 19 */
+#define CAN_F9R1_FB20_Pos      (20U)                                           
+#define CAN_F9R1_FB20_Msk      (0x1UL << CAN_F9R1_FB20_Pos)                     /*!< 0x00100000 */
+#define CAN_F9R1_FB20          CAN_F9R1_FB20_Msk                               /*!<Filter bit 20 */
+#define CAN_F9R1_FB21_Pos      (21U)                                           
+#define CAN_F9R1_FB21_Msk      (0x1UL << CAN_F9R1_FB21_Pos)                     /*!< 0x00200000 */
+#define CAN_F9R1_FB21          CAN_F9R1_FB21_Msk                               /*!<Filter bit 21 */
+#define CAN_F9R1_FB22_Pos      (22U)                                           
+#define CAN_F9R1_FB22_Msk      (0x1UL << CAN_F9R1_FB22_Pos)                     /*!< 0x00400000 */
+#define CAN_F9R1_FB22          CAN_F9R1_FB22_Msk                               /*!<Filter bit 22 */
+#define CAN_F9R1_FB23_Pos      (23U)                                           
+#define CAN_F9R1_FB23_Msk      (0x1UL << CAN_F9R1_FB23_Pos)                     /*!< 0x00800000 */
+#define CAN_F9R1_FB23          CAN_F9R1_FB23_Msk                               /*!<Filter bit 23 */
+#define CAN_F9R1_FB24_Pos      (24U)                                           
+#define CAN_F9R1_FB24_Msk      (0x1UL << CAN_F9R1_FB24_Pos)                     /*!< 0x01000000 */
+#define CAN_F9R1_FB24          CAN_F9R1_FB24_Msk                               /*!<Filter bit 24 */
+#define CAN_F9R1_FB25_Pos      (25U)                                           
+#define CAN_F9R1_FB25_Msk      (0x1UL << CAN_F9R1_FB25_Pos)                     /*!< 0x02000000 */
+#define CAN_F9R1_FB25          CAN_F9R1_FB25_Msk                               /*!<Filter bit 25 */
+#define CAN_F9R1_FB26_Pos      (26U)                                           
+#define CAN_F9R1_FB26_Msk      (0x1UL << CAN_F9R1_FB26_Pos)                     /*!< 0x04000000 */
+#define CAN_F9R1_FB26          CAN_F9R1_FB26_Msk                               /*!<Filter bit 26 */
+#define CAN_F9R1_FB27_Pos      (27U)                                           
+#define CAN_F9R1_FB27_Msk      (0x1UL << CAN_F9R1_FB27_Pos)                     /*!< 0x08000000 */
+#define CAN_F9R1_FB27          CAN_F9R1_FB27_Msk                               /*!<Filter bit 27 */
+#define CAN_F9R1_FB28_Pos      (28U)                                           
+#define CAN_F9R1_FB28_Msk      (0x1UL << CAN_F9R1_FB28_Pos)                     /*!< 0x10000000 */
+#define CAN_F9R1_FB28          CAN_F9R1_FB28_Msk                               /*!<Filter bit 28 */
+#define CAN_F9R1_FB29_Pos      (29U)                                           
+#define CAN_F9R1_FB29_Msk      (0x1UL << CAN_F9R1_FB29_Pos)                     /*!< 0x20000000 */
+#define CAN_F9R1_FB29          CAN_F9R1_FB29_Msk                               /*!<Filter bit 29 */
+#define CAN_F9R1_FB30_Pos      (30U)                                           
+#define CAN_F9R1_FB30_Msk      (0x1UL << CAN_F9R1_FB30_Pos)                     /*!< 0x40000000 */
+#define CAN_F9R1_FB30          CAN_F9R1_FB30_Msk                               /*!<Filter bit 30 */
+#define CAN_F9R1_FB31_Pos      (31U)                                           
+#define CAN_F9R1_FB31_Msk      (0x1UL << CAN_F9R1_FB31_Pos)                     /*!< 0x80000000 */
+#define CAN_F9R1_FB31          CAN_F9R1_FB31_Msk                               /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F10R1 register  ******************/
+#define CAN_F10R1_FB0_Pos      (0U)                                            
+#define CAN_F10R1_FB0_Msk      (0x1UL << CAN_F10R1_FB0_Pos)                     /*!< 0x00000001 */
+#define CAN_F10R1_FB0          CAN_F10R1_FB0_Msk                               /*!<Filter bit 0 */
+#define CAN_F10R1_FB1_Pos      (1U)                                            
+#define CAN_F10R1_FB1_Msk      (0x1UL << CAN_F10R1_FB1_Pos)                     /*!< 0x00000002 */
+#define CAN_F10R1_FB1          CAN_F10R1_FB1_Msk                               /*!<Filter bit 1 */
+#define CAN_F10R1_FB2_Pos      (2U)                                            
+#define CAN_F10R1_FB2_Msk      (0x1UL << CAN_F10R1_FB2_Pos)                     /*!< 0x00000004 */
+#define CAN_F10R1_FB2          CAN_F10R1_FB2_Msk                               /*!<Filter bit 2 */
+#define CAN_F10R1_FB3_Pos      (3U)                                            
+#define CAN_F10R1_FB3_Msk      (0x1UL << CAN_F10R1_FB3_Pos)                     /*!< 0x00000008 */
+#define CAN_F10R1_FB3          CAN_F10R1_FB3_Msk                               /*!<Filter bit 3 */
+#define CAN_F10R1_FB4_Pos      (4U)                                            
+#define CAN_F10R1_FB4_Msk      (0x1UL << CAN_F10R1_FB4_Pos)                     /*!< 0x00000010 */
+#define CAN_F10R1_FB4          CAN_F10R1_FB4_Msk                               /*!<Filter bit 4 */
+#define CAN_F10R1_FB5_Pos      (5U)                                            
+#define CAN_F10R1_FB5_Msk      (0x1UL << CAN_F10R1_FB5_Pos)                     /*!< 0x00000020 */
+#define CAN_F10R1_FB5          CAN_F10R1_FB5_Msk                               /*!<Filter bit 5 */
+#define CAN_F10R1_FB6_Pos      (6U)                                            
+#define CAN_F10R1_FB6_Msk      (0x1UL << CAN_F10R1_FB6_Pos)                     /*!< 0x00000040 */
+#define CAN_F10R1_FB6          CAN_F10R1_FB6_Msk                               /*!<Filter bit 6 */
+#define CAN_F10R1_FB7_Pos      (7U)                                            
+#define CAN_F10R1_FB7_Msk      (0x1UL << CAN_F10R1_FB7_Pos)                     /*!< 0x00000080 */
+#define CAN_F10R1_FB7          CAN_F10R1_FB7_Msk                               /*!<Filter bit 7 */
+#define CAN_F10R1_FB8_Pos      (8U)                                            
+#define CAN_F10R1_FB8_Msk      (0x1UL << CAN_F10R1_FB8_Pos)                     /*!< 0x00000100 */
+#define CAN_F10R1_FB8          CAN_F10R1_FB8_Msk                               /*!<Filter bit 8 */
+#define CAN_F10R1_FB9_Pos      (9U)                                            
+#define CAN_F10R1_FB9_Msk      (0x1UL << CAN_F10R1_FB9_Pos)                     /*!< 0x00000200 */
+#define CAN_F10R1_FB9          CAN_F10R1_FB9_Msk                               /*!<Filter bit 9 */
+#define CAN_F10R1_FB10_Pos     (10U)                                           
+#define CAN_F10R1_FB10_Msk     (0x1UL << CAN_F10R1_FB10_Pos)                    /*!< 0x00000400 */
+#define CAN_F10R1_FB10         CAN_F10R1_FB10_Msk                              /*!<Filter bit 10 */
+#define CAN_F10R1_FB11_Pos     (11U)                                           
+#define CAN_F10R1_FB11_Msk     (0x1UL << CAN_F10R1_FB11_Pos)                    /*!< 0x00000800 */
+#define CAN_F10R1_FB11         CAN_F10R1_FB11_Msk                              /*!<Filter bit 11 */
+#define CAN_F10R1_FB12_Pos     (12U)                                           
+#define CAN_F10R1_FB12_Msk     (0x1UL << CAN_F10R1_FB12_Pos)                    /*!< 0x00001000 */
+#define CAN_F10R1_FB12         CAN_F10R1_FB12_Msk                              /*!<Filter bit 12 */
+#define CAN_F10R1_FB13_Pos     (13U)                                           
+#define CAN_F10R1_FB13_Msk     (0x1UL << CAN_F10R1_FB13_Pos)                    /*!< 0x00002000 */
+#define CAN_F10R1_FB13         CAN_F10R1_FB13_Msk                              /*!<Filter bit 13 */
+#define CAN_F10R1_FB14_Pos     (14U)                                           
+#define CAN_F10R1_FB14_Msk     (0x1UL << CAN_F10R1_FB14_Pos)                    /*!< 0x00004000 */
+#define CAN_F10R1_FB14         CAN_F10R1_FB14_Msk                              /*!<Filter bit 14 */
+#define CAN_F10R1_FB15_Pos     (15U)                                           
+#define CAN_F10R1_FB15_Msk     (0x1UL << CAN_F10R1_FB15_Pos)                    /*!< 0x00008000 */
+#define CAN_F10R1_FB15         CAN_F10R1_FB15_Msk                              /*!<Filter bit 15 */
+#define CAN_F10R1_FB16_Pos     (16U)                                           
+#define CAN_F10R1_FB16_Msk     (0x1UL << CAN_F10R1_FB16_Pos)                    /*!< 0x00010000 */
+#define CAN_F10R1_FB16         CAN_F10R1_FB16_Msk                              /*!<Filter bit 16 */
+#define CAN_F10R1_FB17_Pos     (17U)                                           
+#define CAN_F10R1_FB17_Msk     (0x1UL << CAN_F10R1_FB17_Pos)                    /*!< 0x00020000 */
+#define CAN_F10R1_FB17         CAN_F10R1_FB17_Msk                              /*!<Filter bit 17 */
+#define CAN_F10R1_FB18_Pos     (18U)                                           
+#define CAN_F10R1_FB18_Msk     (0x1UL << CAN_F10R1_FB18_Pos)                    /*!< 0x00040000 */
+#define CAN_F10R1_FB18         CAN_F10R1_FB18_Msk                              /*!<Filter bit 18 */
+#define CAN_F10R1_FB19_Pos     (19U)                                           
+#define CAN_F10R1_FB19_Msk     (0x1UL << CAN_F10R1_FB19_Pos)                    /*!< 0x00080000 */
+#define CAN_F10R1_FB19         CAN_F10R1_FB19_Msk                              /*!<Filter bit 19 */
+#define CAN_F10R1_FB20_Pos     (20U)                                           
+#define CAN_F10R1_FB20_Msk     (0x1UL << CAN_F10R1_FB20_Pos)                    /*!< 0x00100000 */
+#define CAN_F10R1_FB20         CAN_F10R1_FB20_Msk                              /*!<Filter bit 20 */
+#define CAN_F10R1_FB21_Pos     (21U)                                           
+#define CAN_F10R1_FB21_Msk     (0x1UL << CAN_F10R1_FB21_Pos)                    /*!< 0x00200000 */
+#define CAN_F10R1_FB21         CAN_F10R1_FB21_Msk                              /*!<Filter bit 21 */
+#define CAN_F10R1_FB22_Pos     (22U)                                           
+#define CAN_F10R1_FB22_Msk     (0x1UL << CAN_F10R1_FB22_Pos)                    /*!< 0x00400000 */
+#define CAN_F10R1_FB22         CAN_F10R1_FB22_Msk                              /*!<Filter bit 22 */
+#define CAN_F10R1_FB23_Pos     (23U)                                           
+#define CAN_F10R1_FB23_Msk     (0x1UL << CAN_F10R1_FB23_Pos)                    /*!< 0x00800000 */
+#define CAN_F10R1_FB23         CAN_F10R1_FB23_Msk                              /*!<Filter bit 23 */
+#define CAN_F10R1_FB24_Pos     (24U)                                           
+#define CAN_F10R1_FB24_Msk     (0x1UL << CAN_F10R1_FB24_Pos)                    /*!< 0x01000000 */
+#define CAN_F10R1_FB24         CAN_F10R1_FB24_Msk                              /*!<Filter bit 24 */
+#define CAN_F10R1_FB25_Pos     (25U)                                           
+#define CAN_F10R1_FB25_Msk     (0x1UL << CAN_F10R1_FB25_Pos)                    /*!< 0x02000000 */
+#define CAN_F10R1_FB25         CAN_F10R1_FB25_Msk                              /*!<Filter bit 25 */
+#define CAN_F10R1_FB26_Pos     (26U)                                           
+#define CAN_F10R1_FB26_Msk     (0x1UL << CAN_F10R1_FB26_Pos)                    /*!< 0x04000000 */
+#define CAN_F10R1_FB26         CAN_F10R1_FB26_Msk                              /*!<Filter bit 26 */
+#define CAN_F10R1_FB27_Pos     (27U)                                           
+#define CAN_F10R1_FB27_Msk     (0x1UL << CAN_F10R1_FB27_Pos)                    /*!< 0x08000000 */
+#define CAN_F10R1_FB27         CAN_F10R1_FB27_Msk                              /*!<Filter bit 27 */
+#define CAN_F10R1_FB28_Pos     (28U)                                           
+#define CAN_F10R1_FB28_Msk     (0x1UL << CAN_F10R1_FB28_Pos)                    /*!< 0x10000000 */
+#define CAN_F10R1_FB28         CAN_F10R1_FB28_Msk                              /*!<Filter bit 28 */
+#define CAN_F10R1_FB29_Pos     (29U)                                           
+#define CAN_F10R1_FB29_Msk     (0x1UL << CAN_F10R1_FB29_Pos)                    /*!< 0x20000000 */
+#define CAN_F10R1_FB29         CAN_F10R1_FB29_Msk                              /*!<Filter bit 29 */
+#define CAN_F10R1_FB30_Pos     (30U)                                           
+#define CAN_F10R1_FB30_Msk     (0x1UL << CAN_F10R1_FB30_Pos)                    /*!< 0x40000000 */
+#define CAN_F10R1_FB30         CAN_F10R1_FB30_Msk                              /*!<Filter bit 30 */
+#define CAN_F10R1_FB31_Pos     (31U)                                           
+#define CAN_F10R1_FB31_Msk     (0x1UL << CAN_F10R1_FB31_Pos)                    /*!< 0x80000000 */
+#define CAN_F10R1_FB31         CAN_F10R1_FB31_Msk                              /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F11R1 register  ******************/
+#define CAN_F11R1_FB0_Pos      (0U)                                            
+#define CAN_F11R1_FB0_Msk      (0x1UL << CAN_F11R1_FB0_Pos)                     /*!< 0x00000001 */
+#define CAN_F11R1_FB0          CAN_F11R1_FB0_Msk                               /*!<Filter bit 0 */
+#define CAN_F11R1_FB1_Pos      (1U)                                            
+#define CAN_F11R1_FB1_Msk      (0x1UL << CAN_F11R1_FB1_Pos)                     /*!< 0x00000002 */
+#define CAN_F11R1_FB1          CAN_F11R1_FB1_Msk                               /*!<Filter bit 1 */
+#define CAN_F11R1_FB2_Pos      (2U)                                            
+#define CAN_F11R1_FB2_Msk      (0x1UL << CAN_F11R1_FB2_Pos)                     /*!< 0x00000004 */
+#define CAN_F11R1_FB2          CAN_F11R1_FB2_Msk                               /*!<Filter bit 2 */
+#define CAN_F11R1_FB3_Pos      (3U)                                            
+#define CAN_F11R1_FB3_Msk      (0x1UL << CAN_F11R1_FB3_Pos)                     /*!< 0x00000008 */
+#define CAN_F11R1_FB3          CAN_F11R1_FB3_Msk                               /*!<Filter bit 3 */
+#define CAN_F11R1_FB4_Pos      (4U)                                            
+#define CAN_F11R1_FB4_Msk      (0x1UL << CAN_F11R1_FB4_Pos)                     /*!< 0x00000010 */
+#define CAN_F11R1_FB4          CAN_F11R1_FB4_Msk                               /*!<Filter bit 4 */
+#define CAN_F11R1_FB5_Pos      (5U)                                            
+#define CAN_F11R1_FB5_Msk      (0x1UL << CAN_F11R1_FB5_Pos)                     /*!< 0x00000020 */
+#define CAN_F11R1_FB5          CAN_F11R1_FB5_Msk                               /*!<Filter bit 5 */
+#define CAN_F11R1_FB6_Pos      (6U)                                            
+#define CAN_F11R1_FB6_Msk      (0x1UL << CAN_F11R1_FB6_Pos)                     /*!< 0x00000040 */
+#define CAN_F11R1_FB6          CAN_F11R1_FB6_Msk                               /*!<Filter bit 6 */
+#define CAN_F11R1_FB7_Pos      (7U)                                            
+#define CAN_F11R1_FB7_Msk      (0x1UL << CAN_F11R1_FB7_Pos)                     /*!< 0x00000080 */
+#define CAN_F11R1_FB7          CAN_F11R1_FB7_Msk                               /*!<Filter bit 7 */
+#define CAN_F11R1_FB8_Pos      (8U)                                            
+#define CAN_F11R1_FB8_Msk      (0x1UL << CAN_F11R1_FB8_Pos)                     /*!< 0x00000100 */
+#define CAN_F11R1_FB8          CAN_F11R1_FB8_Msk                               /*!<Filter bit 8 */
+#define CAN_F11R1_FB9_Pos      (9U)                                            
+#define CAN_F11R1_FB9_Msk      (0x1UL << CAN_F11R1_FB9_Pos)                     /*!< 0x00000200 */
+#define CAN_F11R1_FB9          CAN_F11R1_FB9_Msk                               /*!<Filter bit 9 */
+#define CAN_F11R1_FB10_Pos     (10U)                                           
+#define CAN_F11R1_FB10_Msk     (0x1UL << CAN_F11R1_FB10_Pos)                    /*!< 0x00000400 */
+#define CAN_F11R1_FB10         CAN_F11R1_FB10_Msk                              /*!<Filter bit 10 */
+#define CAN_F11R1_FB11_Pos     (11U)                                           
+#define CAN_F11R1_FB11_Msk     (0x1UL << CAN_F11R1_FB11_Pos)                    /*!< 0x00000800 */
+#define CAN_F11R1_FB11         CAN_F11R1_FB11_Msk                              /*!<Filter bit 11 */
+#define CAN_F11R1_FB12_Pos     (12U)                                           
+#define CAN_F11R1_FB12_Msk     (0x1UL << CAN_F11R1_FB12_Pos)                    /*!< 0x00001000 */
+#define CAN_F11R1_FB12         CAN_F11R1_FB12_Msk                              /*!<Filter bit 12 */
+#define CAN_F11R1_FB13_Pos     (13U)                                           
+#define CAN_F11R1_FB13_Msk     (0x1UL << CAN_F11R1_FB13_Pos)                    /*!< 0x00002000 */
+#define CAN_F11R1_FB13         CAN_F11R1_FB13_Msk                              /*!<Filter bit 13 */
+#define CAN_F11R1_FB14_Pos     (14U)                                           
+#define CAN_F11R1_FB14_Msk     (0x1UL << CAN_F11R1_FB14_Pos)                    /*!< 0x00004000 */
+#define CAN_F11R1_FB14         CAN_F11R1_FB14_Msk                              /*!<Filter bit 14 */
+#define CAN_F11R1_FB15_Pos     (15U)                                           
+#define CAN_F11R1_FB15_Msk     (0x1UL << CAN_F11R1_FB15_Pos)                    /*!< 0x00008000 */
+#define CAN_F11R1_FB15         CAN_F11R1_FB15_Msk                              /*!<Filter bit 15 */
+#define CAN_F11R1_FB16_Pos     (16U)                                           
+#define CAN_F11R1_FB16_Msk     (0x1UL << CAN_F11R1_FB16_Pos)                    /*!< 0x00010000 */
+#define CAN_F11R1_FB16         CAN_F11R1_FB16_Msk                              /*!<Filter bit 16 */
+#define CAN_F11R1_FB17_Pos     (17U)                                           
+#define CAN_F11R1_FB17_Msk     (0x1UL << CAN_F11R1_FB17_Pos)                    /*!< 0x00020000 */
+#define CAN_F11R1_FB17         CAN_F11R1_FB17_Msk                              /*!<Filter bit 17 */
+#define CAN_F11R1_FB18_Pos     (18U)                                           
+#define CAN_F11R1_FB18_Msk     (0x1UL << CAN_F11R1_FB18_Pos)                    /*!< 0x00040000 */
+#define CAN_F11R1_FB18         CAN_F11R1_FB18_Msk                              /*!<Filter bit 18 */
+#define CAN_F11R1_FB19_Pos     (19U)                                           
+#define CAN_F11R1_FB19_Msk     (0x1UL << CAN_F11R1_FB19_Pos)                    /*!< 0x00080000 */
+#define CAN_F11R1_FB19         CAN_F11R1_FB19_Msk                              /*!<Filter bit 19 */
+#define CAN_F11R1_FB20_Pos     (20U)                                           
+#define CAN_F11R1_FB20_Msk     (0x1UL << CAN_F11R1_FB20_Pos)                    /*!< 0x00100000 */
+#define CAN_F11R1_FB20         CAN_F11R1_FB20_Msk                              /*!<Filter bit 20 */
+#define CAN_F11R1_FB21_Pos     (21U)                                           
+#define CAN_F11R1_FB21_Msk     (0x1UL << CAN_F11R1_FB21_Pos)                    /*!< 0x00200000 */
+#define CAN_F11R1_FB21         CAN_F11R1_FB21_Msk                              /*!<Filter bit 21 */
+#define CAN_F11R1_FB22_Pos     (22U)                                           
+#define CAN_F11R1_FB22_Msk     (0x1UL << CAN_F11R1_FB22_Pos)                    /*!< 0x00400000 */
+#define CAN_F11R1_FB22         CAN_F11R1_FB22_Msk                              /*!<Filter bit 22 */
+#define CAN_F11R1_FB23_Pos     (23U)                                           
+#define CAN_F11R1_FB23_Msk     (0x1UL << CAN_F11R1_FB23_Pos)                    /*!< 0x00800000 */
+#define CAN_F11R1_FB23         CAN_F11R1_FB23_Msk                              /*!<Filter bit 23 */
+#define CAN_F11R1_FB24_Pos     (24U)                                           
+#define CAN_F11R1_FB24_Msk     (0x1UL << CAN_F11R1_FB24_Pos)                    /*!< 0x01000000 */
+#define CAN_F11R1_FB24         CAN_F11R1_FB24_Msk                              /*!<Filter bit 24 */
+#define CAN_F11R1_FB25_Pos     (25U)                                           
+#define CAN_F11R1_FB25_Msk     (0x1UL << CAN_F11R1_FB25_Pos)                    /*!< 0x02000000 */
+#define CAN_F11R1_FB25         CAN_F11R1_FB25_Msk                              /*!<Filter bit 25 */
+#define CAN_F11R1_FB26_Pos     (26U)                                           
+#define CAN_F11R1_FB26_Msk     (0x1UL << CAN_F11R1_FB26_Pos)                    /*!< 0x04000000 */
+#define CAN_F11R1_FB26         CAN_F11R1_FB26_Msk                              /*!<Filter bit 26 */
+#define CAN_F11R1_FB27_Pos     (27U)                                           
+#define CAN_F11R1_FB27_Msk     (0x1UL << CAN_F11R1_FB27_Pos)                    /*!< 0x08000000 */
+#define CAN_F11R1_FB27         CAN_F11R1_FB27_Msk                              /*!<Filter bit 27 */
+#define CAN_F11R1_FB28_Pos     (28U)                                           
+#define CAN_F11R1_FB28_Msk     (0x1UL << CAN_F11R1_FB28_Pos)                    /*!< 0x10000000 */
+#define CAN_F11R1_FB28         CAN_F11R1_FB28_Msk                              /*!<Filter bit 28 */
+#define CAN_F11R1_FB29_Pos     (29U)                                           
+#define CAN_F11R1_FB29_Msk     (0x1UL << CAN_F11R1_FB29_Pos)                    /*!< 0x20000000 */
+#define CAN_F11R1_FB29         CAN_F11R1_FB29_Msk                              /*!<Filter bit 29 */
+#define CAN_F11R1_FB30_Pos     (30U)                                           
+#define CAN_F11R1_FB30_Msk     (0x1UL << CAN_F11R1_FB30_Pos)                    /*!< 0x40000000 */
+#define CAN_F11R1_FB30         CAN_F11R1_FB30_Msk                              /*!<Filter bit 30 */
+#define CAN_F11R1_FB31_Pos     (31U)                                           
+#define CAN_F11R1_FB31_Msk     (0x1UL << CAN_F11R1_FB31_Pos)                    /*!< 0x80000000 */
+#define CAN_F11R1_FB31         CAN_F11R1_FB31_Msk                              /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F12R1 register  ******************/
+#define CAN_F12R1_FB0_Pos      (0U)                                            
+#define CAN_F12R1_FB0_Msk      (0x1UL << CAN_F12R1_FB0_Pos)                     /*!< 0x00000001 */
+#define CAN_F12R1_FB0          CAN_F12R1_FB0_Msk                               /*!<Filter bit 0 */
+#define CAN_F12R1_FB1_Pos      (1U)                                            
+#define CAN_F12R1_FB1_Msk      (0x1UL << CAN_F12R1_FB1_Pos)                     /*!< 0x00000002 */
+#define CAN_F12R1_FB1          CAN_F12R1_FB1_Msk                               /*!<Filter bit 1 */
+#define CAN_F12R1_FB2_Pos      (2U)                                            
+#define CAN_F12R1_FB2_Msk      (0x1UL << CAN_F12R1_FB2_Pos)                     /*!< 0x00000004 */
+#define CAN_F12R1_FB2          CAN_F12R1_FB2_Msk                               /*!<Filter bit 2 */
+#define CAN_F12R1_FB3_Pos      (3U)                                            
+#define CAN_F12R1_FB3_Msk      (0x1UL << CAN_F12R1_FB3_Pos)                     /*!< 0x00000008 */
+#define CAN_F12R1_FB3          CAN_F12R1_FB3_Msk                               /*!<Filter bit 3 */
+#define CAN_F12R1_FB4_Pos      (4U)                                            
+#define CAN_F12R1_FB4_Msk      (0x1UL << CAN_F12R1_FB4_Pos)                     /*!< 0x00000010 */
+#define CAN_F12R1_FB4          CAN_F12R1_FB4_Msk                               /*!<Filter bit 4 */
+#define CAN_F12R1_FB5_Pos      (5U)                                            
+#define CAN_F12R1_FB5_Msk      (0x1UL << CAN_F12R1_FB5_Pos)                     /*!< 0x00000020 */
+#define CAN_F12R1_FB5          CAN_F12R1_FB5_Msk                               /*!<Filter bit 5 */
+#define CAN_F12R1_FB6_Pos      (6U)                                            
+#define CAN_F12R1_FB6_Msk      (0x1UL << CAN_F12R1_FB6_Pos)                     /*!< 0x00000040 */
+#define CAN_F12R1_FB6          CAN_F12R1_FB6_Msk                               /*!<Filter bit 6 */
+#define CAN_F12R1_FB7_Pos      (7U)                                            
+#define CAN_F12R1_FB7_Msk      (0x1UL << CAN_F12R1_FB7_Pos)                     /*!< 0x00000080 */
+#define CAN_F12R1_FB7          CAN_F12R1_FB7_Msk                               /*!<Filter bit 7 */
+#define CAN_F12R1_FB8_Pos      (8U)                                            
+#define CAN_F12R1_FB8_Msk      (0x1UL << CAN_F12R1_FB8_Pos)                     /*!< 0x00000100 */
+#define CAN_F12R1_FB8          CAN_F12R1_FB8_Msk                               /*!<Filter bit 8 */
+#define CAN_F12R1_FB9_Pos      (9U)                                            
+#define CAN_F12R1_FB9_Msk      (0x1UL << CAN_F12R1_FB9_Pos)                     /*!< 0x00000200 */
+#define CAN_F12R1_FB9          CAN_F12R1_FB9_Msk                               /*!<Filter bit 9 */
+#define CAN_F12R1_FB10_Pos     (10U)                                           
+#define CAN_F12R1_FB10_Msk     (0x1UL << CAN_F12R1_FB10_Pos)                    /*!< 0x00000400 */
+#define CAN_F12R1_FB10         CAN_F12R1_FB10_Msk                              /*!<Filter bit 10 */
+#define CAN_F12R1_FB11_Pos     (11U)                                           
+#define CAN_F12R1_FB11_Msk     (0x1UL << CAN_F12R1_FB11_Pos)                    /*!< 0x00000800 */
+#define CAN_F12R1_FB11         CAN_F12R1_FB11_Msk                              /*!<Filter bit 11 */
+#define CAN_F12R1_FB12_Pos     (12U)                                           
+#define CAN_F12R1_FB12_Msk     (0x1UL << CAN_F12R1_FB12_Pos)                    /*!< 0x00001000 */
+#define CAN_F12R1_FB12         CAN_F12R1_FB12_Msk                              /*!<Filter bit 12 */
+#define CAN_F12R1_FB13_Pos     (13U)                                           
+#define CAN_F12R1_FB13_Msk     (0x1UL << CAN_F12R1_FB13_Pos)                    /*!< 0x00002000 */
+#define CAN_F12R1_FB13         CAN_F12R1_FB13_Msk                              /*!<Filter bit 13 */
+#define CAN_F12R1_FB14_Pos     (14U)                                           
+#define CAN_F12R1_FB14_Msk     (0x1UL << CAN_F12R1_FB14_Pos)                    /*!< 0x00004000 */
+#define CAN_F12R1_FB14         CAN_F12R1_FB14_Msk                              /*!<Filter bit 14 */
+#define CAN_F12R1_FB15_Pos     (15U)                                           
+#define CAN_F12R1_FB15_Msk     (0x1UL << CAN_F12R1_FB15_Pos)                    /*!< 0x00008000 */
+#define CAN_F12R1_FB15         CAN_F12R1_FB15_Msk                              /*!<Filter bit 15 */
+#define CAN_F12R1_FB16_Pos     (16U)                                           
+#define CAN_F12R1_FB16_Msk     (0x1UL << CAN_F12R1_FB16_Pos)                    /*!< 0x00010000 */
+#define CAN_F12R1_FB16         CAN_F12R1_FB16_Msk                              /*!<Filter bit 16 */
+#define CAN_F12R1_FB17_Pos     (17U)                                           
+#define CAN_F12R1_FB17_Msk     (0x1UL << CAN_F12R1_FB17_Pos)                    /*!< 0x00020000 */
+#define CAN_F12R1_FB17         CAN_F12R1_FB17_Msk                              /*!<Filter bit 17 */
+#define CAN_F12R1_FB18_Pos     (18U)                                           
+#define CAN_F12R1_FB18_Msk     (0x1UL << CAN_F12R1_FB18_Pos)                    /*!< 0x00040000 */
+#define CAN_F12R1_FB18         CAN_F12R1_FB18_Msk                              /*!<Filter bit 18 */
+#define CAN_F12R1_FB19_Pos     (19U)                                           
+#define CAN_F12R1_FB19_Msk     (0x1UL << CAN_F12R1_FB19_Pos)                    /*!< 0x00080000 */
+#define CAN_F12R1_FB19         CAN_F12R1_FB19_Msk                              /*!<Filter bit 19 */
+#define CAN_F12R1_FB20_Pos     (20U)                                           
+#define CAN_F12R1_FB20_Msk     (0x1UL << CAN_F12R1_FB20_Pos)                    /*!< 0x00100000 */
+#define CAN_F12R1_FB20         CAN_F12R1_FB20_Msk                              /*!<Filter bit 20 */
+#define CAN_F12R1_FB21_Pos     (21U)                                           
+#define CAN_F12R1_FB21_Msk     (0x1UL << CAN_F12R1_FB21_Pos)                    /*!< 0x00200000 */
+#define CAN_F12R1_FB21         CAN_F12R1_FB21_Msk                              /*!<Filter bit 21 */
+#define CAN_F12R1_FB22_Pos     (22U)                                           
+#define CAN_F12R1_FB22_Msk     (0x1UL << CAN_F12R1_FB22_Pos)                    /*!< 0x00400000 */
+#define CAN_F12R1_FB22         CAN_F12R1_FB22_Msk                              /*!<Filter bit 22 */
+#define CAN_F12R1_FB23_Pos     (23U)                                           
+#define CAN_F12R1_FB23_Msk     (0x1UL << CAN_F12R1_FB23_Pos)                    /*!< 0x00800000 */
+#define CAN_F12R1_FB23         CAN_F12R1_FB23_Msk                              /*!<Filter bit 23 */
+#define CAN_F12R1_FB24_Pos     (24U)                                           
+#define CAN_F12R1_FB24_Msk     (0x1UL << CAN_F12R1_FB24_Pos)                    /*!< 0x01000000 */
+#define CAN_F12R1_FB24         CAN_F12R1_FB24_Msk                              /*!<Filter bit 24 */
+#define CAN_F12R1_FB25_Pos     (25U)                                           
+#define CAN_F12R1_FB25_Msk     (0x1UL << CAN_F12R1_FB25_Pos)                    /*!< 0x02000000 */
+#define CAN_F12R1_FB25         CAN_F12R1_FB25_Msk                              /*!<Filter bit 25 */
+#define CAN_F12R1_FB26_Pos     (26U)                                           
+#define CAN_F12R1_FB26_Msk     (0x1UL << CAN_F12R1_FB26_Pos)                    /*!< 0x04000000 */
+#define CAN_F12R1_FB26         CAN_F12R1_FB26_Msk                              /*!<Filter bit 26 */
+#define CAN_F12R1_FB27_Pos     (27U)                                           
+#define CAN_F12R1_FB27_Msk     (0x1UL << CAN_F12R1_FB27_Pos)                    /*!< 0x08000000 */
+#define CAN_F12R1_FB27         CAN_F12R1_FB27_Msk                              /*!<Filter bit 27 */
+#define CAN_F12R1_FB28_Pos     (28U)                                           
+#define CAN_F12R1_FB28_Msk     (0x1UL << CAN_F12R1_FB28_Pos)                    /*!< 0x10000000 */
+#define CAN_F12R1_FB28         CAN_F12R1_FB28_Msk                              /*!<Filter bit 28 */
+#define CAN_F12R1_FB29_Pos     (29U)                                           
+#define CAN_F12R1_FB29_Msk     (0x1UL << CAN_F12R1_FB29_Pos)                    /*!< 0x20000000 */
+#define CAN_F12R1_FB29         CAN_F12R1_FB29_Msk                              /*!<Filter bit 29 */
+#define CAN_F12R1_FB30_Pos     (30U)                                           
+#define CAN_F12R1_FB30_Msk     (0x1UL << CAN_F12R1_FB30_Pos)                    /*!< 0x40000000 */
+#define CAN_F12R1_FB30         CAN_F12R1_FB30_Msk                              /*!<Filter bit 30 */
+#define CAN_F12R1_FB31_Pos     (31U)                                           
+#define CAN_F12R1_FB31_Msk     (0x1UL << CAN_F12R1_FB31_Pos)                    /*!< 0x80000000 */
+#define CAN_F12R1_FB31         CAN_F12R1_FB31_Msk                              /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F13R1 register  ******************/
+#define CAN_F13R1_FB0_Pos      (0U)                                            
+#define CAN_F13R1_FB0_Msk      (0x1UL << CAN_F13R1_FB0_Pos)                     /*!< 0x00000001 */
+#define CAN_F13R1_FB0          CAN_F13R1_FB0_Msk                               /*!<Filter bit 0 */
+#define CAN_F13R1_FB1_Pos      (1U)                                            
+#define CAN_F13R1_FB1_Msk      (0x1UL << CAN_F13R1_FB1_Pos)                     /*!< 0x00000002 */
+#define CAN_F13R1_FB1          CAN_F13R1_FB1_Msk                               /*!<Filter bit 1 */
+#define CAN_F13R1_FB2_Pos      (2U)                                            
+#define CAN_F13R1_FB2_Msk      (0x1UL << CAN_F13R1_FB2_Pos)                     /*!< 0x00000004 */
+#define CAN_F13R1_FB2          CAN_F13R1_FB2_Msk                               /*!<Filter bit 2 */
+#define CAN_F13R1_FB3_Pos      (3U)                                            
+#define CAN_F13R1_FB3_Msk      (0x1UL << CAN_F13R1_FB3_Pos)                     /*!< 0x00000008 */
+#define CAN_F13R1_FB3          CAN_F13R1_FB3_Msk                               /*!<Filter bit 3 */
+#define CAN_F13R1_FB4_Pos      (4U)                                            
+#define CAN_F13R1_FB4_Msk      (0x1UL << CAN_F13R1_FB4_Pos)                     /*!< 0x00000010 */
+#define CAN_F13R1_FB4          CAN_F13R1_FB4_Msk                               /*!<Filter bit 4 */
+#define CAN_F13R1_FB5_Pos      (5U)                                            
+#define CAN_F13R1_FB5_Msk      (0x1UL << CAN_F13R1_FB5_Pos)                     /*!< 0x00000020 */
+#define CAN_F13R1_FB5          CAN_F13R1_FB5_Msk                               /*!<Filter bit 5 */
+#define CAN_F13R1_FB6_Pos      (6U)                                            
+#define CAN_F13R1_FB6_Msk      (0x1UL << CAN_F13R1_FB6_Pos)                     /*!< 0x00000040 */
+#define CAN_F13R1_FB6          CAN_F13R1_FB6_Msk                               /*!<Filter bit 6 */
+#define CAN_F13R1_FB7_Pos      (7U)                                            
+#define CAN_F13R1_FB7_Msk      (0x1UL << CAN_F13R1_FB7_Pos)                     /*!< 0x00000080 */
+#define CAN_F13R1_FB7          CAN_F13R1_FB7_Msk                               /*!<Filter bit 7 */
+#define CAN_F13R1_FB8_Pos      (8U)                                            
+#define CAN_F13R1_FB8_Msk      (0x1UL << CAN_F13R1_FB8_Pos)                     /*!< 0x00000100 */
+#define CAN_F13R1_FB8          CAN_F13R1_FB8_Msk                               /*!<Filter bit 8 */
+#define CAN_F13R1_FB9_Pos      (9U)                                            
+#define CAN_F13R1_FB9_Msk      (0x1UL << CAN_F13R1_FB9_Pos)                     /*!< 0x00000200 */
+#define CAN_F13R1_FB9          CAN_F13R1_FB9_Msk                               /*!<Filter bit 9 */
+#define CAN_F13R1_FB10_Pos     (10U)                                           
+#define CAN_F13R1_FB10_Msk     (0x1UL << CAN_F13R1_FB10_Pos)                    /*!< 0x00000400 */
+#define CAN_F13R1_FB10         CAN_F13R1_FB10_Msk                              /*!<Filter bit 10 */
+#define CAN_F13R1_FB11_Pos     (11U)                                           
+#define CAN_F13R1_FB11_Msk     (0x1UL << CAN_F13R1_FB11_Pos)                    /*!< 0x00000800 */
+#define CAN_F13R1_FB11         CAN_F13R1_FB11_Msk                              /*!<Filter bit 11 */
+#define CAN_F13R1_FB12_Pos     (12U)                                           
+#define CAN_F13R1_FB12_Msk     (0x1UL << CAN_F13R1_FB12_Pos)                    /*!< 0x00001000 */
+#define CAN_F13R1_FB12         CAN_F13R1_FB12_Msk                              /*!<Filter bit 12 */
+#define CAN_F13R1_FB13_Pos     (13U)                                           
+#define CAN_F13R1_FB13_Msk     (0x1UL << CAN_F13R1_FB13_Pos)                    /*!< 0x00002000 */
+#define CAN_F13R1_FB13         CAN_F13R1_FB13_Msk                              /*!<Filter bit 13 */
+#define CAN_F13R1_FB14_Pos     (14U)                                           
+#define CAN_F13R1_FB14_Msk     (0x1UL << CAN_F13R1_FB14_Pos)                    /*!< 0x00004000 */
+#define CAN_F13R1_FB14         CAN_F13R1_FB14_Msk                              /*!<Filter bit 14 */
+#define CAN_F13R1_FB15_Pos     (15U)                                           
+#define CAN_F13R1_FB15_Msk     (0x1UL << CAN_F13R1_FB15_Pos)                    /*!< 0x00008000 */
+#define CAN_F13R1_FB15         CAN_F13R1_FB15_Msk                              /*!<Filter bit 15 */
+#define CAN_F13R1_FB16_Pos     (16U)                                           
+#define CAN_F13R1_FB16_Msk     (0x1UL << CAN_F13R1_FB16_Pos)                    /*!< 0x00010000 */
+#define CAN_F13R1_FB16         CAN_F13R1_FB16_Msk                              /*!<Filter bit 16 */
+#define CAN_F13R1_FB17_Pos     (17U)                                           
+#define CAN_F13R1_FB17_Msk     (0x1UL << CAN_F13R1_FB17_Pos)                    /*!< 0x00020000 */
+#define CAN_F13R1_FB17         CAN_F13R1_FB17_Msk                              /*!<Filter bit 17 */
+#define CAN_F13R1_FB18_Pos     (18U)                                           
+#define CAN_F13R1_FB18_Msk     (0x1UL << CAN_F13R1_FB18_Pos)                    /*!< 0x00040000 */
+#define CAN_F13R1_FB18         CAN_F13R1_FB18_Msk                              /*!<Filter bit 18 */
+#define CAN_F13R1_FB19_Pos     (19U)                                           
+#define CAN_F13R1_FB19_Msk     (0x1UL << CAN_F13R1_FB19_Pos)                    /*!< 0x00080000 */
+#define CAN_F13R1_FB19         CAN_F13R1_FB19_Msk                              /*!<Filter bit 19 */
+#define CAN_F13R1_FB20_Pos     (20U)                                           
+#define CAN_F13R1_FB20_Msk     (0x1UL << CAN_F13R1_FB20_Pos)                    /*!< 0x00100000 */
+#define CAN_F13R1_FB20         CAN_F13R1_FB20_Msk                              /*!<Filter bit 20 */
+#define CAN_F13R1_FB21_Pos     (21U)                                           
+#define CAN_F13R1_FB21_Msk     (0x1UL << CAN_F13R1_FB21_Pos)                    /*!< 0x00200000 */
+#define CAN_F13R1_FB21         CAN_F13R1_FB21_Msk                              /*!<Filter bit 21 */
+#define CAN_F13R1_FB22_Pos     (22U)                                           
+#define CAN_F13R1_FB22_Msk     (0x1UL << CAN_F13R1_FB22_Pos)                    /*!< 0x00400000 */
+#define CAN_F13R1_FB22         CAN_F13R1_FB22_Msk                              /*!<Filter bit 22 */
+#define CAN_F13R1_FB23_Pos     (23U)                                           
+#define CAN_F13R1_FB23_Msk     (0x1UL << CAN_F13R1_FB23_Pos)                    /*!< 0x00800000 */
+#define CAN_F13R1_FB23         CAN_F13R1_FB23_Msk                              /*!<Filter bit 23 */
+#define CAN_F13R1_FB24_Pos     (24U)                                           
+#define CAN_F13R1_FB24_Msk     (0x1UL << CAN_F13R1_FB24_Pos)                    /*!< 0x01000000 */
+#define CAN_F13R1_FB24         CAN_F13R1_FB24_Msk                              /*!<Filter bit 24 */
+#define CAN_F13R1_FB25_Pos     (25U)                                           
+#define CAN_F13R1_FB25_Msk     (0x1UL << CAN_F13R1_FB25_Pos)                    /*!< 0x02000000 */
+#define CAN_F13R1_FB25         CAN_F13R1_FB25_Msk                              /*!<Filter bit 25 */
+#define CAN_F13R1_FB26_Pos     (26U)                                           
+#define CAN_F13R1_FB26_Msk     (0x1UL << CAN_F13R1_FB26_Pos)                    /*!< 0x04000000 */
+#define CAN_F13R1_FB26         CAN_F13R1_FB26_Msk                              /*!<Filter bit 26 */
+#define CAN_F13R1_FB27_Pos     (27U)                                           
+#define CAN_F13R1_FB27_Msk     (0x1UL << CAN_F13R1_FB27_Pos)                    /*!< 0x08000000 */
+#define CAN_F13R1_FB27         CAN_F13R1_FB27_Msk                              /*!<Filter bit 27 */
+#define CAN_F13R1_FB28_Pos     (28U)                                           
+#define CAN_F13R1_FB28_Msk     (0x1UL << CAN_F13R1_FB28_Pos)                    /*!< 0x10000000 */
+#define CAN_F13R1_FB28         CAN_F13R1_FB28_Msk                              /*!<Filter bit 28 */
+#define CAN_F13R1_FB29_Pos     (29U)                                           
+#define CAN_F13R1_FB29_Msk     (0x1UL << CAN_F13R1_FB29_Pos)                    /*!< 0x20000000 */
+#define CAN_F13R1_FB29         CAN_F13R1_FB29_Msk                              /*!<Filter bit 29 */
+#define CAN_F13R1_FB30_Pos     (30U)                                           
+#define CAN_F13R1_FB30_Msk     (0x1UL << CAN_F13R1_FB30_Pos)                    /*!< 0x40000000 */
+#define CAN_F13R1_FB30         CAN_F13R1_FB30_Msk                              /*!<Filter bit 30 */
+#define CAN_F13R1_FB31_Pos     (31U)                                           
+#define CAN_F13R1_FB31_Msk     (0x1UL << CAN_F13R1_FB31_Pos)                    /*!< 0x80000000 */
+#define CAN_F13R1_FB31         CAN_F13R1_FB31_Msk                              /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F0R2 register  *******************/
+#define CAN_F0R2_FB0_Pos       (0U)                                            
+#define CAN_F0R2_FB0_Msk       (0x1UL << CAN_F0R2_FB0_Pos)                      /*!< 0x00000001 */
+#define CAN_F0R2_FB0           CAN_F0R2_FB0_Msk                                /*!<Filter bit 0 */
+#define CAN_F0R2_FB1_Pos       (1U)                                            
+#define CAN_F0R2_FB1_Msk       (0x1UL << CAN_F0R2_FB1_Pos)                      /*!< 0x00000002 */
+#define CAN_F0R2_FB1           CAN_F0R2_FB1_Msk                                /*!<Filter bit 1 */
+#define CAN_F0R2_FB2_Pos       (2U)                                            
+#define CAN_F0R2_FB2_Msk       (0x1UL << CAN_F0R2_FB2_Pos)                      /*!< 0x00000004 */
+#define CAN_F0R2_FB2           CAN_F0R2_FB2_Msk                                /*!<Filter bit 2 */
+#define CAN_F0R2_FB3_Pos       (3U)                                            
+#define CAN_F0R2_FB3_Msk       (0x1UL << CAN_F0R2_FB3_Pos)                      /*!< 0x00000008 */
+#define CAN_F0R2_FB3           CAN_F0R2_FB3_Msk                                /*!<Filter bit 3 */
+#define CAN_F0R2_FB4_Pos       (4U)                                            
+#define CAN_F0R2_FB4_Msk       (0x1UL << CAN_F0R2_FB4_Pos)                      /*!< 0x00000010 */
+#define CAN_F0R2_FB4           CAN_F0R2_FB4_Msk                                /*!<Filter bit 4 */
+#define CAN_F0R2_FB5_Pos       (5U)                                            
+#define CAN_F0R2_FB5_Msk       (0x1UL << CAN_F0R2_FB5_Pos)                      /*!< 0x00000020 */
+#define CAN_F0R2_FB5           CAN_F0R2_FB5_Msk                                /*!<Filter bit 5 */
+#define CAN_F0R2_FB6_Pos       (6U)                                            
+#define CAN_F0R2_FB6_Msk       (0x1UL << CAN_F0R2_FB6_Pos)                      /*!< 0x00000040 */
+#define CAN_F0R2_FB6           CAN_F0R2_FB6_Msk                                /*!<Filter bit 6 */
+#define CAN_F0R2_FB7_Pos       (7U)                                            
+#define CAN_F0R2_FB7_Msk       (0x1UL << CAN_F0R2_FB7_Pos)                      /*!< 0x00000080 */
+#define CAN_F0R2_FB7           CAN_F0R2_FB7_Msk                                /*!<Filter bit 7 */
+#define CAN_F0R2_FB8_Pos       (8U)                                            
+#define CAN_F0R2_FB8_Msk       (0x1UL << CAN_F0R2_FB8_Pos)                      /*!< 0x00000100 */
+#define CAN_F0R2_FB8           CAN_F0R2_FB8_Msk                                /*!<Filter bit 8 */
+#define CAN_F0R2_FB9_Pos       (9U)                                            
+#define CAN_F0R2_FB9_Msk       (0x1UL << CAN_F0R2_FB9_Pos)                      /*!< 0x00000200 */
+#define CAN_F0R2_FB9           CAN_F0R2_FB9_Msk                                /*!<Filter bit 9 */
+#define CAN_F0R2_FB10_Pos      (10U)                                           
+#define CAN_F0R2_FB10_Msk      (0x1UL << CAN_F0R2_FB10_Pos)                     /*!< 0x00000400 */
+#define CAN_F0R2_FB10          CAN_F0R2_FB10_Msk                               /*!<Filter bit 10 */
+#define CAN_F0R2_FB11_Pos      (11U)                                           
+#define CAN_F0R2_FB11_Msk      (0x1UL << CAN_F0R2_FB11_Pos)                     /*!< 0x00000800 */
+#define CAN_F0R2_FB11          CAN_F0R2_FB11_Msk                               /*!<Filter bit 11 */
+#define CAN_F0R2_FB12_Pos      (12U)                                           
+#define CAN_F0R2_FB12_Msk      (0x1UL << CAN_F0R2_FB12_Pos)                     /*!< 0x00001000 */
+#define CAN_F0R2_FB12          CAN_F0R2_FB12_Msk                               /*!<Filter bit 12 */
+#define CAN_F0R2_FB13_Pos      (13U)                                           
+#define CAN_F0R2_FB13_Msk      (0x1UL << CAN_F0R2_FB13_Pos)                     /*!< 0x00002000 */
+#define CAN_F0R2_FB13          CAN_F0R2_FB13_Msk                               /*!<Filter bit 13 */
+#define CAN_F0R2_FB14_Pos      (14U)                                           
+#define CAN_F0R2_FB14_Msk      (0x1UL << CAN_F0R2_FB14_Pos)                     /*!< 0x00004000 */
+#define CAN_F0R2_FB14          CAN_F0R2_FB14_Msk                               /*!<Filter bit 14 */
+#define CAN_F0R2_FB15_Pos      (15U)                                           
+#define CAN_F0R2_FB15_Msk      (0x1UL << CAN_F0R2_FB15_Pos)                     /*!< 0x00008000 */
+#define CAN_F0R2_FB15          CAN_F0R2_FB15_Msk                               /*!<Filter bit 15 */
+#define CAN_F0R2_FB16_Pos      (16U)                                           
+#define CAN_F0R2_FB16_Msk      (0x1UL << CAN_F0R2_FB16_Pos)                     /*!< 0x00010000 */
+#define CAN_F0R2_FB16          CAN_F0R2_FB16_Msk                               /*!<Filter bit 16 */
+#define CAN_F0R2_FB17_Pos      (17U)                                           
+#define CAN_F0R2_FB17_Msk      (0x1UL << CAN_F0R2_FB17_Pos)                     /*!< 0x00020000 */
+#define CAN_F0R2_FB17          CAN_F0R2_FB17_Msk                               /*!<Filter bit 17 */
+#define CAN_F0R2_FB18_Pos      (18U)                                           
+#define CAN_F0R2_FB18_Msk      (0x1UL << CAN_F0R2_FB18_Pos)                     /*!< 0x00040000 */
+#define CAN_F0R2_FB18          CAN_F0R2_FB18_Msk                               /*!<Filter bit 18 */
+#define CAN_F0R2_FB19_Pos      (19U)                                           
+#define CAN_F0R2_FB19_Msk      (0x1UL << CAN_F0R2_FB19_Pos)                     /*!< 0x00080000 */
+#define CAN_F0R2_FB19          CAN_F0R2_FB19_Msk                               /*!<Filter bit 19 */
+#define CAN_F0R2_FB20_Pos      (20U)                                           
+#define CAN_F0R2_FB20_Msk      (0x1UL << CAN_F0R2_FB20_Pos)                     /*!< 0x00100000 */
+#define CAN_F0R2_FB20          CAN_F0R2_FB20_Msk                               /*!<Filter bit 20 */
+#define CAN_F0R2_FB21_Pos      (21U)                                           
+#define CAN_F0R2_FB21_Msk      (0x1UL << CAN_F0R2_FB21_Pos)                     /*!< 0x00200000 */
+#define CAN_F0R2_FB21          CAN_F0R2_FB21_Msk                               /*!<Filter bit 21 */
+#define CAN_F0R2_FB22_Pos      (22U)                                           
+#define CAN_F0R2_FB22_Msk      (0x1UL << CAN_F0R2_FB22_Pos)                     /*!< 0x00400000 */
+#define CAN_F0R2_FB22          CAN_F0R2_FB22_Msk                               /*!<Filter bit 22 */
+#define CAN_F0R2_FB23_Pos      (23U)                                           
+#define CAN_F0R2_FB23_Msk      (0x1UL << CAN_F0R2_FB23_Pos)                     /*!< 0x00800000 */
+#define CAN_F0R2_FB23          CAN_F0R2_FB23_Msk                               /*!<Filter bit 23 */
+#define CAN_F0R2_FB24_Pos      (24U)                                           
+#define CAN_F0R2_FB24_Msk      (0x1UL << CAN_F0R2_FB24_Pos)                     /*!< 0x01000000 */
+#define CAN_F0R2_FB24          CAN_F0R2_FB24_Msk                               /*!<Filter bit 24 */
+#define CAN_F0R2_FB25_Pos      (25U)                                           
+#define CAN_F0R2_FB25_Msk      (0x1UL << CAN_F0R2_FB25_Pos)                     /*!< 0x02000000 */
+#define CAN_F0R2_FB25          CAN_F0R2_FB25_Msk                               /*!<Filter bit 25 */
+#define CAN_F0R2_FB26_Pos      (26U)                                           
+#define CAN_F0R2_FB26_Msk      (0x1UL << CAN_F0R2_FB26_Pos)                     /*!< 0x04000000 */
+#define CAN_F0R2_FB26          CAN_F0R2_FB26_Msk                               /*!<Filter bit 26 */
+#define CAN_F0R2_FB27_Pos      (27U)                                           
+#define CAN_F0R2_FB27_Msk      (0x1UL << CAN_F0R2_FB27_Pos)                     /*!< 0x08000000 */
+#define CAN_F0R2_FB27          CAN_F0R2_FB27_Msk                               /*!<Filter bit 27 */
+#define CAN_F0R2_FB28_Pos      (28U)                                           
+#define CAN_F0R2_FB28_Msk      (0x1UL << CAN_F0R2_FB28_Pos)                     /*!< 0x10000000 */
+#define CAN_F0R2_FB28          CAN_F0R2_FB28_Msk                               /*!<Filter bit 28 */
+#define CAN_F0R2_FB29_Pos      (29U)                                           
+#define CAN_F0R2_FB29_Msk      (0x1UL << CAN_F0R2_FB29_Pos)                     /*!< 0x20000000 */
+#define CAN_F0R2_FB29          CAN_F0R2_FB29_Msk                               /*!<Filter bit 29 */
+#define CAN_F0R2_FB30_Pos      (30U)                                           
+#define CAN_F0R2_FB30_Msk      (0x1UL << CAN_F0R2_FB30_Pos)                     /*!< 0x40000000 */
+#define CAN_F0R2_FB30          CAN_F0R2_FB30_Msk                               /*!<Filter bit 30 */
+#define CAN_F0R2_FB31_Pos      (31U)                                           
+#define CAN_F0R2_FB31_Msk      (0x1UL << CAN_F0R2_FB31_Pos)                     /*!< 0x80000000 */
+#define CAN_F0R2_FB31          CAN_F0R2_FB31_Msk                               /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F1R2 register  *******************/
+#define CAN_F1R2_FB0_Pos       (0U)                                            
+#define CAN_F1R2_FB0_Msk       (0x1UL << CAN_F1R2_FB0_Pos)                      /*!< 0x00000001 */
+#define CAN_F1R2_FB0           CAN_F1R2_FB0_Msk                                /*!<Filter bit 0 */
+#define CAN_F1R2_FB1_Pos       (1U)                                            
+#define CAN_F1R2_FB1_Msk       (0x1UL << CAN_F1R2_FB1_Pos)                      /*!< 0x00000002 */
+#define CAN_F1R2_FB1           CAN_F1R2_FB1_Msk                                /*!<Filter bit 1 */
+#define CAN_F1R2_FB2_Pos       (2U)                                            
+#define CAN_F1R2_FB2_Msk       (0x1UL << CAN_F1R2_FB2_Pos)                      /*!< 0x00000004 */
+#define CAN_F1R2_FB2           CAN_F1R2_FB2_Msk                                /*!<Filter bit 2 */
+#define CAN_F1R2_FB3_Pos       (3U)                                            
+#define CAN_F1R2_FB3_Msk       (0x1UL << CAN_F1R2_FB3_Pos)                      /*!< 0x00000008 */
+#define CAN_F1R2_FB3           CAN_F1R2_FB3_Msk                                /*!<Filter bit 3 */
+#define CAN_F1R2_FB4_Pos       (4U)                                            
+#define CAN_F1R2_FB4_Msk       (0x1UL << CAN_F1R2_FB4_Pos)                      /*!< 0x00000010 */
+#define CAN_F1R2_FB4           CAN_F1R2_FB4_Msk                                /*!<Filter bit 4 */
+#define CAN_F1R2_FB5_Pos       (5U)                                            
+#define CAN_F1R2_FB5_Msk       (0x1UL << CAN_F1R2_FB5_Pos)                      /*!< 0x00000020 */
+#define CAN_F1R2_FB5           CAN_F1R2_FB5_Msk                                /*!<Filter bit 5 */
+#define CAN_F1R2_FB6_Pos       (6U)                                            
+#define CAN_F1R2_FB6_Msk       (0x1UL << CAN_F1R2_FB6_Pos)                      /*!< 0x00000040 */
+#define CAN_F1R2_FB6           CAN_F1R2_FB6_Msk                                /*!<Filter bit 6 */
+#define CAN_F1R2_FB7_Pos       (7U)                                            
+#define CAN_F1R2_FB7_Msk       (0x1UL << CAN_F1R2_FB7_Pos)                      /*!< 0x00000080 */
+#define CAN_F1R2_FB7           CAN_F1R2_FB7_Msk                                /*!<Filter bit 7 */
+#define CAN_F1R2_FB8_Pos       (8U)                                            
+#define CAN_F1R2_FB8_Msk       (0x1UL << CAN_F1R2_FB8_Pos)                      /*!< 0x00000100 */
+#define CAN_F1R2_FB8           CAN_F1R2_FB8_Msk                                /*!<Filter bit 8 */
+#define CAN_F1R2_FB9_Pos       (9U)                                            
+#define CAN_F1R2_FB9_Msk       (0x1UL << CAN_F1R2_FB9_Pos)                      /*!< 0x00000200 */
+#define CAN_F1R2_FB9           CAN_F1R2_FB9_Msk                                /*!<Filter bit 9 */
+#define CAN_F1R2_FB10_Pos      (10U)                                           
+#define CAN_F1R2_FB10_Msk      (0x1UL << CAN_F1R2_FB10_Pos)                     /*!< 0x00000400 */
+#define CAN_F1R2_FB10          CAN_F1R2_FB10_Msk                               /*!<Filter bit 10 */
+#define CAN_F1R2_FB11_Pos      (11U)                                           
+#define CAN_F1R2_FB11_Msk      (0x1UL << CAN_F1R2_FB11_Pos)                     /*!< 0x00000800 */
+#define CAN_F1R2_FB11          CAN_F1R2_FB11_Msk                               /*!<Filter bit 11 */
+#define CAN_F1R2_FB12_Pos      (12U)                                           
+#define CAN_F1R2_FB12_Msk      (0x1UL << CAN_F1R2_FB12_Pos)                     /*!< 0x00001000 */
+#define CAN_F1R2_FB12          CAN_F1R2_FB12_Msk                               /*!<Filter bit 12 */
+#define CAN_F1R2_FB13_Pos      (13U)                                           
+#define CAN_F1R2_FB13_Msk      (0x1UL << CAN_F1R2_FB13_Pos)                     /*!< 0x00002000 */
+#define CAN_F1R2_FB13          CAN_F1R2_FB13_Msk                               /*!<Filter bit 13 */
+#define CAN_F1R2_FB14_Pos      (14U)                                           
+#define CAN_F1R2_FB14_Msk      (0x1UL << CAN_F1R2_FB14_Pos)                     /*!< 0x00004000 */
+#define CAN_F1R2_FB14          CAN_F1R2_FB14_Msk                               /*!<Filter bit 14 */
+#define CAN_F1R2_FB15_Pos      (15U)                                           
+#define CAN_F1R2_FB15_Msk      (0x1UL << CAN_F1R2_FB15_Pos)                     /*!< 0x00008000 */
+#define CAN_F1R2_FB15          CAN_F1R2_FB15_Msk                               /*!<Filter bit 15 */
+#define CAN_F1R2_FB16_Pos      (16U)                                           
+#define CAN_F1R2_FB16_Msk      (0x1UL << CAN_F1R2_FB16_Pos)                     /*!< 0x00010000 */
+#define CAN_F1R2_FB16          CAN_F1R2_FB16_Msk                               /*!<Filter bit 16 */
+#define CAN_F1R2_FB17_Pos      (17U)                                           
+#define CAN_F1R2_FB17_Msk      (0x1UL << CAN_F1R2_FB17_Pos)                     /*!< 0x00020000 */
+#define CAN_F1R2_FB17          CAN_F1R2_FB17_Msk                               /*!<Filter bit 17 */
+#define CAN_F1R2_FB18_Pos      (18U)                                           
+#define CAN_F1R2_FB18_Msk      (0x1UL << CAN_F1R2_FB18_Pos)                     /*!< 0x00040000 */
+#define CAN_F1R2_FB18          CAN_F1R2_FB18_Msk                               /*!<Filter bit 18 */
+#define CAN_F1R2_FB19_Pos      (19U)                                           
+#define CAN_F1R2_FB19_Msk      (0x1UL << CAN_F1R2_FB19_Pos)                     /*!< 0x00080000 */
+#define CAN_F1R2_FB19          CAN_F1R2_FB19_Msk                               /*!<Filter bit 19 */
+#define CAN_F1R2_FB20_Pos      (20U)                                           
+#define CAN_F1R2_FB20_Msk      (0x1UL << CAN_F1R2_FB20_Pos)                     /*!< 0x00100000 */
+#define CAN_F1R2_FB20          CAN_F1R2_FB20_Msk                               /*!<Filter bit 20 */
+#define CAN_F1R2_FB21_Pos      (21U)                                           
+#define CAN_F1R2_FB21_Msk      (0x1UL << CAN_F1R2_FB21_Pos)                     /*!< 0x00200000 */
+#define CAN_F1R2_FB21          CAN_F1R2_FB21_Msk                               /*!<Filter bit 21 */
+#define CAN_F1R2_FB22_Pos      (22U)                                           
+#define CAN_F1R2_FB22_Msk      (0x1UL << CAN_F1R2_FB22_Pos)                     /*!< 0x00400000 */
+#define CAN_F1R2_FB22          CAN_F1R2_FB22_Msk                               /*!<Filter bit 22 */
+#define CAN_F1R2_FB23_Pos      (23U)                                           
+#define CAN_F1R2_FB23_Msk      (0x1UL << CAN_F1R2_FB23_Pos)                     /*!< 0x00800000 */
+#define CAN_F1R2_FB23          CAN_F1R2_FB23_Msk                               /*!<Filter bit 23 */
+#define CAN_F1R2_FB24_Pos      (24U)                                           
+#define CAN_F1R2_FB24_Msk      (0x1UL << CAN_F1R2_FB24_Pos)                     /*!< 0x01000000 */
+#define CAN_F1R2_FB24          CAN_F1R2_FB24_Msk                               /*!<Filter bit 24 */
+#define CAN_F1R2_FB25_Pos      (25U)                                           
+#define CAN_F1R2_FB25_Msk      (0x1UL << CAN_F1R2_FB25_Pos)                     /*!< 0x02000000 */
+#define CAN_F1R2_FB25          CAN_F1R2_FB25_Msk                               /*!<Filter bit 25 */
+#define CAN_F1R2_FB26_Pos      (26U)                                           
+#define CAN_F1R2_FB26_Msk      (0x1UL << CAN_F1R2_FB26_Pos)                     /*!< 0x04000000 */
+#define CAN_F1R2_FB26          CAN_F1R2_FB26_Msk                               /*!<Filter bit 26 */
+#define CAN_F1R2_FB27_Pos      (27U)                                           
+#define CAN_F1R2_FB27_Msk      (0x1UL << CAN_F1R2_FB27_Pos)                     /*!< 0x08000000 */
+#define CAN_F1R2_FB27          CAN_F1R2_FB27_Msk                               /*!<Filter bit 27 */
+#define CAN_F1R2_FB28_Pos      (28U)                                           
+#define CAN_F1R2_FB28_Msk      (0x1UL << CAN_F1R2_FB28_Pos)                     /*!< 0x10000000 */
+#define CAN_F1R2_FB28          CAN_F1R2_FB28_Msk                               /*!<Filter bit 28 */
+#define CAN_F1R2_FB29_Pos      (29U)                                           
+#define CAN_F1R2_FB29_Msk      (0x1UL << CAN_F1R2_FB29_Pos)                     /*!< 0x20000000 */
+#define CAN_F1R2_FB29          CAN_F1R2_FB29_Msk                               /*!<Filter bit 29 */
+#define CAN_F1R2_FB30_Pos      (30U)                                           
+#define CAN_F1R2_FB30_Msk      (0x1UL << CAN_F1R2_FB30_Pos)                     /*!< 0x40000000 */
+#define CAN_F1R2_FB30          CAN_F1R2_FB30_Msk                               /*!<Filter bit 30 */
+#define CAN_F1R2_FB31_Pos      (31U)                                           
+#define CAN_F1R2_FB31_Msk      (0x1UL << CAN_F1R2_FB31_Pos)                     /*!< 0x80000000 */
+#define CAN_F1R2_FB31          CAN_F1R2_FB31_Msk                               /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F2R2 register  *******************/
+#define CAN_F2R2_FB0_Pos       (0U)                                            
+#define CAN_F2R2_FB0_Msk       (0x1UL << CAN_F2R2_FB0_Pos)                      /*!< 0x00000001 */
+#define CAN_F2R2_FB0           CAN_F2R2_FB0_Msk                                /*!<Filter bit 0 */
+#define CAN_F2R2_FB1_Pos       (1U)                                            
+#define CAN_F2R2_FB1_Msk       (0x1UL << CAN_F2R2_FB1_Pos)                      /*!< 0x00000002 */
+#define CAN_F2R2_FB1           CAN_F2R2_FB1_Msk                                /*!<Filter bit 1 */
+#define CAN_F2R2_FB2_Pos       (2U)                                            
+#define CAN_F2R2_FB2_Msk       (0x1UL << CAN_F2R2_FB2_Pos)                      /*!< 0x00000004 */
+#define CAN_F2R2_FB2           CAN_F2R2_FB2_Msk                                /*!<Filter bit 2 */
+#define CAN_F2R2_FB3_Pos       (3U)                                            
+#define CAN_F2R2_FB3_Msk       (0x1UL << CAN_F2R2_FB3_Pos)                      /*!< 0x00000008 */
+#define CAN_F2R2_FB3           CAN_F2R2_FB3_Msk                                /*!<Filter bit 3 */
+#define CAN_F2R2_FB4_Pos       (4U)                                            
+#define CAN_F2R2_FB4_Msk       (0x1UL << CAN_F2R2_FB4_Pos)                      /*!< 0x00000010 */
+#define CAN_F2R2_FB4           CAN_F2R2_FB4_Msk                                /*!<Filter bit 4 */
+#define CAN_F2R2_FB5_Pos       (5U)                                            
+#define CAN_F2R2_FB5_Msk       (0x1UL << CAN_F2R2_FB5_Pos)                      /*!< 0x00000020 */
+#define CAN_F2R2_FB5           CAN_F2R2_FB5_Msk                                /*!<Filter bit 5 */
+#define CAN_F2R2_FB6_Pos       (6U)                                            
+#define CAN_F2R2_FB6_Msk       (0x1UL << CAN_F2R2_FB6_Pos)                      /*!< 0x00000040 */
+#define CAN_F2R2_FB6           CAN_F2R2_FB6_Msk                                /*!<Filter bit 6 */
+#define CAN_F2R2_FB7_Pos       (7U)                                            
+#define CAN_F2R2_FB7_Msk       (0x1UL << CAN_F2R2_FB7_Pos)                      /*!< 0x00000080 */
+#define CAN_F2R2_FB7           CAN_F2R2_FB7_Msk                                /*!<Filter bit 7 */
+#define CAN_F2R2_FB8_Pos       (8U)                                            
+#define CAN_F2R2_FB8_Msk       (0x1UL << CAN_F2R2_FB8_Pos)                      /*!< 0x00000100 */
+#define CAN_F2R2_FB8           CAN_F2R2_FB8_Msk                                /*!<Filter bit 8 */
+#define CAN_F2R2_FB9_Pos       (9U)                                            
+#define CAN_F2R2_FB9_Msk       (0x1UL << CAN_F2R2_FB9_Pos)                      /*!< 0x00000200 */
+#define CAN_F2R2_FB9           CAN_F2R2_FB9_Msk                                /*!<Filter bit 9 */
+#define CAN_F2R2_FB10_Pos      (10U)                                           
+#define CAN_F2R2_FB10_Msk      (0x1UL << CAN_F2R2_FB10_Pos)                     /*!< 0x00000400 */
+#define CAN_F2R2_FB10          CAN_F2R2_FB10_Msk                               /*!<Filter bit 10 */
+#define CAN_F2R2_FB11_Pos      (11U)                                           
+#define CAN_F2R2_FB11_Msk      (0x1UL << CAN_F2R2_FB11_Pos)                     /*!< 0x00000800 */
+#define CAN_F2R2_FB11          CAN_F2R2_FB11_Msk                               /*!<Filter bit 11 */
+#define CAN_F2R2_FB12_Pos      (12U)                                           
+#define CAN_F2R2_FB12_Msk      (0x1UL << CAN_F2R2_FB12_Pos)                     /*!< 0x00001000 */
+#define CAN_F2R2_FB12          CAN_F2R2_FB12_Msk                               /*!<Filter bit 12 */
+#define CAN_F2R2_FB13_Pos      (13U)                                           
+#define CAN_F2R2_FB13_Msk      (0x1UL << CAN_F2R2_FB13_Pos)                     /*!< 0x00002000 */
+#define CAN_F2R2_FB13          CAN_F2R2_FB13_Msk                               /*!<Filter bit 13 */
+#define CAN_F2R2_FB14_Pos      (14U)                                           
+#define CAN_F2R2_FB14_Msk      (0x1UL << CAN_F2R2_FB14_Pos)                     /*!< 0x00004000 */
+#define CAN_F2R2_FB14          CAN_F2R2_FB14_Msk                               /*!<Filter bit 14 */
+#define CAN_F2R2_FB15_Pos      (15U)                                           
+#define CAN_F2R2_FB15_Msk      (0x1UL << CAN_F2R2_FB15_Pos)                     /*!< 0x00008000 */
+#define CAN_F2R2_FB15          CAN_F2R2_FB15_Msk                               /*!<Filter bit 15 */
+#define CAN_F2R2_FB16_Pos      (16U)                                           
+#define CAN_F2R2_FB16_Msk      (0x1UL << CAN_F2R2_FB16_Pos)                     /*!< 0x00010000 */
+#define CAN_F2R2_FB16          CAN_F2R2_FB16_Msk                               /*!<Filter bit 16 */
+#define CAN_F2R2_FB17_Pos      (17U)                                           
+#define CAN_F2R2_FB17_Msk      (0x1UL << CAN_F2R2_FB17_Pos)                     /*!< 0x00020000 */
+#define CAN_F2R2_FB17          CAN_F2R2_FB17_Msk                               /*!<Filter bit 17 */
+#define CAN_F2R2_FB18_Pos      (18U)                                           
+#define CAN_F2R2_FB18_Msk      (0x1UL << CAN_F2R2_FB18_Pos)                     /*!< 0x00040000 */
+#define CAN_F2R2_FB18          CAN_F2R2_FB18_Msk                               /*!<Filter bit 18 */
+#define CAN_F2R2_FB19_Pos      (19U)                                           
+#define CAN_F2R2_FB19_Msk      (0x1UL << CAN_F2R2_FB19_Pos)                     /*!< 0x00080000 */
+#define CAN_F2R2_FB19          CAN_F2R2_FB19_Msk                               /*!<Filter bit 19 */
+#define CAN_F2R2_FB20_Pos      (20U)                                           
+#define CAN_F2R2_FB20_Msk      (0x1UL << CAN_F2R2_FB20_Pos)                     /*!< 0x00100000 */
+#define CAN_F2R2_FB20          CAN_F2R2_FB20_Msk                               /*!<Filter bit 20 */
+#define CAN_F2R2_FB21_Pos      (21U)                                           
+#define CAN_F2R2_FB21_Msk      (0x1UL << CAN_F2R2_FB21_Pos)                     /*!< 0x00200000 */
+#define CAN_F2R2_FB21          CAN_F2R2_FB21_Msk                               /*!<Filter bit 21 */
+#define CAN_F2R2_FB22_Pos      (22U)                                           
+#define CAN_F2R2_FB22_Msk      (0x1UL << CAN_F2R2_FB22_Pos)                     /*!< 0x00400000 */
+#define CAN_F2R2_FB22          CAN_F2R2_FB22_Msk                               /*!<Filter bit 22 */
+#define CAN_F2R2_FB23_Pos      (23U)                                           
+#define CAN_F2R2_FB23_Msk      (0x1UL << CAN_F2R2_FB23_Pos)                     /*!< 0x00800000 */
+#define CAN_F2R2_FB23          CAN_F2R2_FB23_Msk                               /*!<Filter bit 23 */
+#define CAN_F2R2_FB24_Pos      (24U)                                           
+#define CAN_F2R2_FB24_Msk      (0x1UL << CAN_F2R2_FB24_Pos)                     /*!< 0x01000000 */
+#define CAN_F2R2_FB24          CAN_F2R2_FB24_Msk                               /*!<Filter bit 24 */
+#define CAN_F2R2_FB25_Pos      (25U)                                           
+#define CAN_F2R2_FB25_Msk      (0x1UL << CAN_F2R2_FB25_Pos)                     /*!< 0x02000000 */
+#define CAN_F2R2_FB25          CAN_F2R2_FB25_Msk                               /*!<Filter bit 25 */
+#define CAN_F2R2_FB26_Pos      (26U)                                           
+#define CAN_F2R2_FB26_Msk      (0x1UL << CAN_F2R2_FB26_Pos)                     /*!< 0x04000000 */
+#define CAN_F2R2_FB26          CAN_F2R2_FB26_Msk                               /*!<Filter bit 26 */
+#define CAN_F2R2_FB27_Pos      (27U)                                           
+#define CAN_F2R2_FB27_Msk      (0x1UL << CAN_F2R2_FB27_Pos)                     /*!< 0x08000000 */
+#define CAN_F2R2_FB27          CAN_F2R2_FB27_Msk                               /*!<Filter bit 27 */
+#define CAN_F2R2_FB28_Pos      (28U)                                           
+#define CAN_F2R2_FB28_Msk      (0x1UL << CAN_F2R2_FB28_Pos)                     /*!< 0x10000000 */
+#define CAN_F2R2_FB28          CAN_F2R2_FB28_Msk                               /*!<Filter bit 28 */
+#define CAN_F2R2_FB29_Pos      (29U)                                           
+#define CAN_F2R2_FB29_Msk      (0x1UL << CAN_F2R2_FB29_Pos)                     /*!< 0x20000000 */
+#define CAN_F2R2_FB29          CAN_F2R2_FB29_Msk                               /*!<Filter bit 29 */
+#define CAN_F2R2_FB30_Pos      (30U)                                           
+#define CAN_F2R2_FB30_Msk      (0x1UL << CAN_F2R2_FB30_Pos)                     /*!< 0x40000000 */
+#define CAN_F2R2_FB30          CAN_F2R2_FB30_Msk                               /*!<Filter bit 30 */
+#define CAN_F2R2_FB31_Pos      (31U)                                           
+#define CAN_F2R2_FB31_Msk      (0x1UL << CAN_F2R2_FB31_Pos)                     /*!< 0x80000000 */
+#define CAN_F2R2_FB31          CAN_F2R2_FB31_Msk                               /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F3R2 register  *******************/
+#define CAN_F3R2_FB0_Pos       (0U)                                            
+#define CAN_F3R2_FB0_Msk       (0x1UL << CAN_F3R2_FB0_Pos)                      /*!< 0x00000001 */
+#define CAN_F3R2_FB0           CAN_F3R2_FB0_Msk                                /*!<Filter bit 0 */
+#define CAN_F3R2_FB1_Pos       (1U)                                            
+#define CAN_F3R2_FB1_Msk       (0x1UL << CAN_F3R2_FB1_Pos)                      /*!< 0x00000002 */
+#define CAN_F3R2_FB1           CAN_F3R2_FB1_Msk                                /*!<Filter bit 1 */
+#define CAN_F3R2_FB2_Pos       (2U)                                            
+#define CAN_F3R2_FB2_Msk       (0x1UL << CAN_F3R2_FB2_Pos)                      /*!< 0x00000004 */
+#define CAN_F3R2_FB2           CAN_F3R2_FB2_Msk                                /*!<Filter bit 2 */
+#define CAN_F3R2_FB3_Pos       (3U)                                            
+#define CAN_F3R2_FB3_Msk       (0x1UL << CAN_F3R2_FB3_Pos)                      /*!< 0x00000008 */
+#define CAN_F3R2_FB3           CAN_F3R2_FB3_Msk                                /*!<Filter bit 3 */
+#define CAN_F3R2_FB4_Pos       (4U)                                            
+#define CAN_F3R2_FB4_Msk       (0x1UL << CAN_F3R2_FB4_Pos)                      /*!< 0x00000010 */
+#define CAN_F3R2_FB4           CAN_F3R2_FB4_Msk                                /*!<Filter bit 4 */
+#define CAN_F3R2_FB5_Pos       (5U)                                            
+#define CAN_F3R2_FB5_Msk       (0x1UL << CAN_F3R2_FB5_Pos)                      /*!< 0x00000020 */
+#define CAN_F3R2_FB5           CAN_F3R2_FB5_Msk                                /*!<Filter bit 5 */
+#define CAN_F3R2_FB6_Pos       (6U)                                            
+#define CAN_F3R2_FB6_Msk       (0x1UL << CAN_F3R2_FB6_Pos)                      /*!< 0x00000040 */
+#define CAN_F3R2_FB6           CAN_F3R2_FB6_Msk                                /*!<Filter bit 6 */
+#define CAN_F3R2_FB7_Pos       (7U)                                            
+#define CAN_F3R2_FB7_Msk       (0x1UL << CAN_F3R2_FB7_Pos)                      /*!< 0x00000080 */
+#define CAN_F3R2_FB7           CAN_F3R2_FB7_Msk                                /*!<Filter bit 7 */
+#define CAN_F3R2_FB8_Pos       (8U)                                            
+#define CAN_F3R2_FB8_Msk       (0x1UL << CAN_F3R2_FB8_Pos)                      /*!< 0x00000100 */
+#define CAN_F3R2_FB8           CAN_F3R2_FB8_Msk                                /*!<Filter bit 8 */
+#define CAN_F3R2_FB9_Pos       (9U)                                            
+#define CAN_F3R2_FB9_Msk       (0x1UL << CAN_F3R2_FB9_Pos)                      /*!< 0x00000200 */
+#define CAN_F3R2_FB9           CAN_F3R2_FB9_Msk                                /*!<Filter bit 9 */
+#define CAN_F3R2_FB10_Pos      (10U)                                           
+#define CAN_F3R2_FB10_Msk      (0x1UL << CAN_F3R2_FB10_Pos)                     /*!< 0x00000400 */
+#define CAN_F3R2_FB10          CAN_F3R2_FB10_Msk                               /*!<Filter bit 10 */
+#define CAN_F3R2_FB11_Pos      (11U)                                           
+#define CAN_F3R2_FB11_Msk      (0x1UL << CAN_F3R2_FB11_Pos)                     /*!< 0x00000800 */
+#define CAN_F3R2_FB11          CAN_F3R2_FB11_Msk                               /*!<Filter bit 11 */
+#define CAN_F3R2_FB12_Pos      (12U)                                           
+#define CAN_F3R2_FB12_Msk      (0x1UL << CAN_F3R2_FB12_Pos)                     /*!< 0x00001000 */
+#define CAN_F3R2_FB12          CAN_F3R2_FB12_Msk                               /*!<Filter bit 12 */
+#define CAN_F3R2_FB13_Pos      (13U)                                           
+#define CAN_F3R2_FB13_Msk      (0x1UL << CAN_F3R2_FB13_Pos)                     /*!< 0x00002000 */
+#define CAN_F3R2_FB13          CAN_F3R2_FB13_Msk                               /*!<Filter bit 13 */
+#define CAN_F3R2_FB14_Pos      (14U)                                           
+#define CAN_F3R2_FB14_Msk      (0x1UL << CAN_F3R2_FB14_Pos)                     /*!< 0x00004000 */
+#define CAN_F3R2_FB14          CAN_F3R2_FB14_Msk                               /*!<Filter bit 14 */
+#define CAN_F3R2_FB15_Pos      (15U)                                           
+#define CAN_F3R2_FB15_Msk      (0x1UL << CAN_F3R2_FB15_Pos)                     /*!< 0x00008000 */
+#define CAN_F3R2_FB15          CAN_F3R2_FB15_Msk                               /*!<Filter bit 15 */
+#define CAN_F3R2_FB16_Pos      (16U)                                           
+#define CAN_F3R2_FB16_Msk      (0x1UL << CAN_F3R2_FB16_Pos)                     /*!< 0x00010000 */
+#define CAN_F3R2_FB16          CAN_F3R2_FB16_Msk                               /*!<Filter bit 16 */
+#define CAN_F3R2_FB17_Pos      (17U)                                           
+#define CAN_F3R2_FB17_Msk      (0x1UL << CAN_F3R2_FB17_Pos)                     /*!< 0x00020000 */
+#define CAN_F3R2_FB17          CAN_F3R2_FB17_Msk                               /*!<Filter bit 17 */
+#define CAN_F3R2_FB18_Pos      (18U)                                           
+#define CAN_F3R2_FB18_Msk      (0x1UL << CAN_F3R2_FB18_Pos)                     /*!< 0x00040000 */
+#define CAN_F3R2_FB18          CAN_F3R2_FB18_Msk                               /*!<Filter bit 18 */
+#define CAN_F3R2_FB19_Pos      (19U)                                           
+#define CAN_F3R2_FB19_Msk      (0x1UL << CAN_F3R2_FB19_Pos)                     /*!< 0x00080000 */
+#define CAN_F3R2_FB19          CAN_F3R2_FB19_Msk                               /*!<Filter bit 19 */
+#define CAN_F3R2_FB20_Pos      (20U)                                           
+#define CAN_F3R2_FB20_Msk      (0x1UL << CAN_F3R2_FB20_Pos)                     /*!< 0x00100000 */
+#define CAN_F3R2_FB20          CAN_F3R2_FB20_Msk                               /*!<Filter bit 20 */
+#define CAN_F3R2_FB21_Pos      (21U)                                           
+#define CAN_F3R2_FB21_Msk      (0x1UL << CAN_F3R2_FB21_Pos)                     /*!< 0x00200000 */
+#define CAN_F3R2_FB21          CAN_F3R2_FB21_Msk                               /*!<Filter bit 21 */
+#define CAN_F3R2_FB22_Pos      (22U)                                           
+#define CAN_F3R2_FB22_Msk      (0x1UL << CAN_F3R2_FB22_Pos)                     /*!< 0x00400000 */
+#define CAN_F3R2_FB22          CAN_F3R2_FB22_Msk                               /*!<Filter bit 22 */
+#define CAN_F3R2_FB23_Pos      (23U)                                           
+#define CAN_F3R2_FB23_Msk      (0x1UL << CAN_F3R2_FB23_Pos)                     /*!< 0x00800000 */
+#define CAN_F3R2_FB23          CAN_F3R2_FB23_Msk                               /*!<Filter bit 23 */
+#define CAN_F3R2_FB24_Pos      (24U)                                           
+#define CAN_F3R2_FB24_Msk      (0x1UL << CAN_F3R2_FB24_Pos)                     /*!< 0x01000000 */
+#define CAN_F3R2_FB24          CAN_F3R2_FB24_Msk                               /*!<Filter bit 24 */
+#define CAN_F3R2_FB25_Pos      (25U)                                           
+#define CAN_F3R2_FB25_Msk      (0x1UL << CAN_F3R2_FB25_Pos)                     /*!< 0x02000000 */
+#define CAN_F3R2_FB25          CAN_F3R2_FB25_Msk                               /*!<Filter bit 25 */
+#define CAN_F3R2_FB26_Pos      (26U)                                           
+#define CAN_F3R2_FB26_Msk      (0x1UL << CAN_F3R2_FB26_Pos)                     /*!< 0x04000000 */
+#define CAN_F3R2_FB26          CAN_F3R2_FB26_Msk                               /*!<Filter bit 26 */
+#define CAN_F3R2_FB27_Pos      (27U)                                           
+#define CAN_F3R2_FB27_Msk      (0x1UL << CAN_F3R2_FB27_Pos)                     /*!< 0x08000000 */
+#define CAN_F3R2_FB27          CAN_F3R2_FB27_Msk                               /*!<Filter bit 27 */
+#define CAN_F3R2_FB28_Pos      (28U)                                           
+#define CAN_F3R2_FB28_Msk      (0x1UL << CAN_F3R2_FB28_Pos)                     /*!< 0x10000000 */
+#define CAN_F3R2_FB28          CAN_F3R2_FB28_Msk                               /*!<Filter bit 28 */
+#define CAN_F3R2_FB29_Pos      (29U)                                           
+#define CAN_F3R2_FB29_Msk      (0x1UL << CAN_F3R2_FB29_Pos)                     /*!< 0x20000000 */
+#define CAN_F3R2_FB29          CAN_F3R2_FB29_Msk                               /*!<Filter bit 29 */
+#define CAN_F3R2_FB30_Pos      (30U)                                           
+#define CAN_F3R2_FB30_Msk      (0x1UL << CAN_F3R2_FB30_Pos)                     /*!< 0x40000000 */
+#define CAN_F3R2_FB30          CAN_F3R2_FB30_Msk                               /*!<Filter bit 30 */
+#define CAN_F3R2_FB31_Pos      (31U)                                           
+#define CAN_F3R2_FB31_Msk      (0x1UL << CAN_F3R2_FB31_Pos)                     /*!< 0x80000000 */
+#define CAN_F3R2_FB31          CAN_F3R2_FB31_Msk                               /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F4R2 register  *******************/
+#define CAN_F4R2_FB0_Pos       (0U)                                            
+#define CAN_F4R2_FB0_Msk       (0x1UL << CAN_F4R2_FB0_Pos)                      /*!< 0x00000001 */
+#define CAN_F4R2_FB0           CAN_F4R2_FB0_Msk                                /*!<Filter bit 0 */
+#define CAN_F4R2_FB1_Pos       (1U)                                            
+#define CAN_F4R2_FB1_Msk       (0x1UL << CAN_F4R2_FB1_Pos)                      /*!< 0x00000002 */
+#define CAN_F4R2_FB1           CAN_F4R2_FB1_Msk                                /*!<Filter bit 1 */
+#define CAN_F4R2_FB2_Pos       (2U)                                            
+#define CAN_F4R2_FB2_Msk       (0x1UL << CAN_F4R2_FB2_Pos)                      /*!< 0x00000004 */
+#define CAN_F4R2_FB2           CAN_F4R2_FB2_Msk                                /*!<Filter bit 2 */
+#define CAN_F4R2_FB3_Pos       (3U)                                            
+#define CAN_F4R2_FB3_Msk       (0x1UL << CAN_F4R2_FB3_Pos)                      /*!< 0x00000008 */
+#define CAN_F4R2_FB3           CAN_F4R2_FB3_Msk                                /*!<Filter bit 3 */
+#define CAN_F4R2_FB4_Pos       (4U)                                            
+#define CAN_F4R2_FB4_Msk       (0x1UL << CAN_F4R2_FB4_Pos)                      /*!< 0x00000010 */
+#define CAN_F4R2_FB4           CAN_F4R2_FB4_Msk                                /*!<Filter bit 4 */
+#define CAN_F4R2_FB5_Pos       (5U)                                            
+#define CAN_F4R2_FB5_Msk       (0x1UL << CAN_F4R2_FB5_Pos)                      /*!< 0x00000020 */
+#define CAN_F4R2_FB5           CAN_F4R2_FB5_Msk                                /*!<Filter bit 5 */
+#define CAN_F4R2_FB6_Pos       (6U)                                            
+#define CAN_F4R2_FB6_Msk       (0x1UL << CAN_F4R2_FB6_Pos)                      /*!< 0x00000040 */
+#define CAN_F4R2_FB6           CAN_F4R2_FB6_Msk                                /*!<Filter bit 6 */
+#define CAN_F4R2_FB7_Pos       (7U)                                            
+#define CAN_F4R2_FB7_Msk       (0x1UL << CAN_F4R2_FB7_Pos)                      /*!< 0x00000080 */
+#define CAN_F4R2_FB7           CAN_F4R2_FB7_Msk                                /*!<Filter bit 7 */
+#define CAN_F4R2_FB8_Pos       (8U)                                            
+#define CAN_F4R2_FB8_Msk       (0x1UL << CAN_F4R2_FB8_Pos)                      /*!< 0x00000100 */
+#define CAN_F4R2_FB8           CAN_F4R2_FB8_Msk                                /*!<Filter bit 8 */
+#define CAN_F4R2_FB9_Pos       (9U)                                            
+#define CAN_F4R2_FB9_Msk       (0x1UL << CAN_F4R2_FB9_Pos)                      /*!< 0x00000200 */
+#define CAN_F4R2_FB9           CAN_F4R2_FB9_Msk                                /*!<Filter bit 9 */
+#define CAN_F4R2_FB10_Pos      (10U)                                           
+#define CAN_F4R2_FB10_Msk      (0x1UL << CAN_F4R2_FB10_Pos)                     /*!< 0x00000400 */
+#define CAN_F4R2_FB10          CAN_F4R2_FB10_Msk                               /*!<Filter bit 10 */
+#define CAN_F4R2_FB11_Pos      (11U)                                           
+#define CAN_F4R2_FB11_Msk      (0x1UL << CAN_F4R2_FB11_Pos)                     /*!< 0x00000800 */
+#define CAN_F4R2_FB11          CAN_F4R2_FB11_Msk                               /*!<Filter bit 11 */
+#define CAN_F4R2_FB12_Pos      (12U)                                           
+#define CAN_F4R2_FB12_Msk      (0x1UL << CAN_F4R2_FB12_Pos)                     /*!< 0x00001000 */
+#define CAN_F4R2_FB12          CAN_F4R2_FB12_Msk                               /*!<Filter bit 12 */
+#define CAN_F4R2_FB13_Pos      (13U)                                           
+#define CAN_F4R2_FB13_Msk      (0x1UL << CAN_F4R2_FB13_Pos)                     /*!< 0x00002000 */
+#define CAN_F4R2_FB13          CAN_F4R2_FB13_Msk                               /*!<Filter bit 13 */
+#define CAN_F4R2_FB14_Pos      (14U)                                           
+#define CAN_F4R2_FB14_Msk      (0x1UL << CAN_F4R2_FB14_Pos)                     /*!< 0x00004000 */
+#define CAN_F4R2_FB14          CAN_F4R2_FB14_Msk                               /*!<Filter bit 14 */
+#define CAN_F4R2_FB15_Pos      (15U)                                           
+#define CAN_F4R2_FB15_Msk      (0x1UL << CAN_F4R2_FB15_Pos)                     /*!< 0x00008000 */
+#define CAN_F4R2_FB15          CAN_F4R2_FB15_Msk                               /*!<Filter bit 15 */
+#define CAN_F4R2_FB16_Pos      (16U)                                           
+#define CAN_F4R2_FB16_Msk      (0x1UL << CAN_F4R2_FB16_Pos)                     /*!< 0x00010000 */
+#define CAN_F4R2_FB16          CAN_F4R2_FB16_Msk                               /*!<Filter bit 16 */
+#define CAN_F4R2_FB17_Pos      (17U)                                           
+#define CAN_F4R2_FB17_Msk      (0x1UL << CAN_F4R2_FB17_Pos)                     /*!< 0x00020000 */
+#define CAN_F4R2_FB17          CAN_F4R2_FB17_Msk                               /*!<Filter bit 17 */
+#define CAN_F4R2_FB18_Pos      (18U)                                           
+#define CAN_F4R2_FB18_Msk      (0x1UL << CAN_F4R2_FB18_Pos)                     /*!< 0x00040000 */
+#define CAN_F4R2_FB18          CAN_F4R2_FB18_Msk                               /*!<Filter bit 18 */
+#define CAN_F4R2_FB19_Pos      (19U)                                           
+#define CAN_F4R2_FB19_Msk      (0x1UL << CAN_F4R2_FB19_Pos)                     /*!< 0x00080000 */
+#define CAN_F4R2_FB19          CAN_F4R2_FB19_Msk                               /*!<Filter bit 19 */
+#define CAN_F4R2_FB20_Pos      (20U)                                           
+#define CAN_F4R2_FB20_Msk      (0x1UL << CAN_F4R2_FB20_Pos)                     /*!< 0x00100000 */
+#define CAN_F4R2_FB20          CAN_F4R2_FB20_Msk                               /*!<Filter bit 20 */
+#define CAN_F4R2_FB21_Pos      (21U)                                           
+#define CAN_F4R2_FB21_Msk      (0x1UL << CAN_F4R2_FB21_Pos)                     /*!< 0x00200000 */
+#define CAN_F4R2_FB21          CAN_F4R2_FB21_Msk                               /*!<Filter bit 21 */
+#define CAN_F4R2_FB22_Pos      (22U)                                           
+#define CAN_F4R2_FB22_Msk      (0x1UL << CAN_F4R2_FB22_Pos)                     /*!< 0x00400000 */
+#define CAN_F4R2_FB22          CAN_F4R2_FB22_Msk                               /*!<Filter bit 22 */
+#define CAN_F4R2_FB23_Pos      (23U)                                           
+#define CAN_F4R2_FB23_Msk      (0x1UL << CAN_F4R2_FB23_Pos)                     /*!< 0x00800000 */
+#define CAN_F4R2_FB23          CAN_F4R2_FB23_Msk                               /*!<Filter bit 23 */
+#define CAN_F4R2_FB24_Pos      (24U)                                           
+#define CAN_F4R2_FB24_Msk      (0x1UL << CAN_F4R2_FB24_Pos)                     /*!< 0x01000000 */
+#define CAN_F4R2_FB24          CAN_F4R2_FB24_Msk                               /*!<Filter bit 24 */
+#define CAN_F4R2_FB25_Pos      (25U)                                           
+#define CAN_F4R2_FB25_Msk      (0x1UL << CAN_F4R2_FB25_Pos)                     /*!< 0x02000000 */
+#define CAN_F4R2_FB25          CAN_F4R2_FB25_Msk                               /*!<Filter bit 25 */
+#define CAN_F4R2_FB26_Pos      (26U)                                           
+#define CAN_F4R2_FB26_Msk      (0x1UL << CAN_F4R2_FB26_Pos)                     /*!< 0x04000000 */
+#define CAN_F4R2_FB26          CAN_F4R2_FB26_Msk                               /*!<Filter bit 26 */
+#define CAN_F4R2_FB27_Pos      (27U)                                           
+#define CAN_F4R2_FB27_Msk      (0x1UL << CAN_F4R2_FB27_Pos)                     /*!< 0x08000000 */
+#define CAN_F4R2_FB27          CAN_F4R2_FB27_Msk                               /*!<Filter bit 27 */
+#define CAN_F4R2_FB28_Pos      (28U)                                           
+#define CAN_F4R2_FB28_Msk      (0x1UL << CAN_F4R2_FB28_Pos)                     /*!< 0x10000000 */
+#define CAN_F4R2_FB28          CAN_F4R2_FB28_Msk                               /*!<Filter bit 28 */
+#define CAN_F4R2_FB29_Pos      (29U)                                           
+#define CAN_F4R2_FB29_Msk      (0x1UL << CAN_F4R2_FB29_Pos)                     /*!< 0x20000000 */
+#define CAN_F4R2_FB29          CAN_F4R2_FB29_Msk                               /*!<Filter bit 29 */
+#define CAN_F4R2_FB30_Pos      (30U)                                           
+#define CAN_F4R2_FB30_Msk      (0x1UL << CAN_F4R2_FB30_Pos)                     /*!< 0x40000000 */
+#define CAN_F4R2_FB30          CAN_F4R2_FB30_Msk                               /*!<Filter bit 30 */
+#define CAN_F4R2_FB31_Pos      (31U)                                           
+#define CAN_F4R2_FB31_Msk      (0x1UL << CAN_F4R2_FB31_Pos)                     /*!< 0x80000000 */
+#define CAN_F4R2_FB31          CAN_F4R2_FB31_Msk                               /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F5R2 register  *******************/
+#define CAN_F5R2_FB0_Pos       (0U)                                            
+#define CAN_F5R2_FB0_Msk       (0x1UL << CAN_F5R2_FB0_Pos)                      /*!< 0x00000001 */
+#define CAN_F5R2_FB0           CAN_F5R2_FB0_Msk                                /*!<Filter bit 0 */
+#define CAN_F5R2_FB1_Pos       (1U)                                            
+#define CAN_F5R2_FB1_Msk       (0x1UL << CAN_F5R2_FB1_Pos)                      /*!< 0x00000002 */
+#define CAN_F5R2_FB1           CAN_F5R2_FB1_Msk                                /*!<Filter bit 1 */
+#define CAN_F5R2_FB2_Pos       (2U)                                            
+#define CAN_F5R2_FB2_Msk       (0x1UL << CAN_F5R2_FB2_Pos)                      /*!< 0x00000004 */
+#define CAN_F5R2_FB2           CAN_F5R2_FB2_Msk                                /*!<Filter bit 2 */
+#define CAN_F5R2_FB3_Pos       (3U)                                            
+#define CAN_F5R2_FB3_Msk       (0x1UL << CAN_F5R2_FB3_Pos)                      /*!< 0x00000008 */
+#define CAN_F5R2_FB3           CAN_F5R2_FB3_Msk                                /*!<Filter bit 3 */
+#define CAN_F5R2_FB4_Pos       (4U)                                            
+#define CAN_F5R2_FB4_Msk       (0x1UL << CAN_F5R2_FB4_Pos)                      /*!< 0x00000010 */
+#define CAN_F5R2_FB4           CAN_F5R2_FB4_Msk                                /*!<Filter bit 4 */
+#define CAN_F5R2_FB5_Pos       (5U)                                            
+#define CAN_F5R2_FB5_Msk       (0x1UL << CAN_F5R2_FB5_Pos)                      /*!< 0x00000020 */
+#define CAN_F5R2_FB5           CAN_F5R2_FB5_Msk                                /*!<Filter bit 5 */
+#define CAN_F5R2_FB6_Pos       (6U)                                            
+#define CAN_F5R2_FB6_Msk       (0x1UL << CAN_F5R2_FB6_Pos)                      /*!< 0x00000040 */
+#define CAN_F5R2_FB6           CAN_F5R2_FB6_Msk                                /*!<Filter bit 6 */
+#define CAN_F5R2_FB7_Pos       (7U)                                            
+#define CAN_F5R2_FB7_Msk       (0x1UL << CAN_F5R2_FB7_Pos)                      /*!< 0x00000080 */
+#define CAN_F5R2_FB7           CAN_F5R2_FB7_Msk                                /*!<Filter bit 7 */
+#define CAN_F5R2_FB8_Pos       (8U)                                            
+#define CAN_F5R2_FB8_Msk       (0x1UL << CAN_F5R2_FB8_Pos)                      /*!< 0x00000100 */
+#define CAN_F5R2_FB8           CAN_F5R2_FB8_Msk                                /*!<Filter bit 8 */
+#define CAN_F5R2_FB9_Pos       (9U)                                            
+#define CAN_F5R2_FB9_Msk       (0x1UL << CAN_F5R2_FB9_Pos)                      /*!< 0x00000200 */
+#define CAN_F5R2_FB9           CAN_F5R2_FB9_Msk                                /*!<Filter bit 9 */
+#define CAN_F5R2_FB10_Pos      (10U)                                           
+#define CAN_F5R2_FB10_Msk      (0x1UL << CAN_F5R2_FB10_Pos)                     /*!< 0x00000400 */
+#define CAN_F5R2_FB10          CAN_F5R2_FB10_Msk                               /*!<Filter bit 10 */
+#define CAN_F5R2_FB11_Pos      (11U)                                           
+#define CAN_F5R2_FB11_Msk      (0x1UL << CAN_F5R2_FB11_Pos)                     /*!< 0x00000800 */
+#define CAN_F5R2_FB11          CAN_F5R2_FB11_Msk                               /*!<Filter bit 11 */
+#define CAN_F5R2_FB12_Pos      (12U)                                           
+#define CAN_F5R2_FB12_Msk      (0x1UL << CAN_F5R2_FB12_Pos)                     /*!< 0x00001000 */
+#define CAN_F5R2_FB12          CAN_F5R2_FB12_Msk                               /*!<Filter bit 12 */
+#define CAN_F5R2_FB13_Pos      (13U)                                           
+#define CAN_F5R2_FB13_Msk      (0x1UL << CAN_F5R2_FB13_Pos)                     /*!< 0x00002000 */
+#define CAN_F5R2_FB13          CAN_F5R2_FB13_Msk                               /*!<Filter bit 13 */
+#define CAN_F5R2_FB14_Pos      (14U)                                           
+#define CAN_F5R2_FB14_Msk      (0x1UL << CAN_F5R2_FB14_Pos)                     /*!< 0x00004000 */
+#define CAN_F5R2_FB14          CAN_F5R2_FB14_Msk                               /*!<Filter bit 14 */
+#define CAN_F5R2_FB15_Pos      (15U)                                           
+#define CAN_F5R2_FB15_Msk      (0x1UL << CAN_F5R2_FB15_Pos)                     /*!< 0x00008000 */
+#define CAN_F5R2_FB15          CAN_F5R2_FB15_Msk                               /*!<Filter bit 15 */
+#define CAN_F5R2_FB16_Pos      (16U)                                           
+#define CAN_F5R2_FB16_Msk      (0x1UL << CAN_F5R2_FB16_Pos)                     /*!< 0x00010000 */
+#define CAN_F5R2_FB16          CAN_F5R2_FB16_Msk                               /*!<Filter bit 16 */
+#define CAN_F5R2_FB17_Pos      (17U)                                           
+#define CAN_F5R2_FB17_Msk      (0x1UL << CAN_F5R2_FB17_Pos)                     /*!< 0x00020000 */
+#define CAN_F5R2_FB17          CAN_F5R2_FB17_Msk                               /*!<Filter bit 17 */
+#define CAN_F5R2_FB18_Pos      (18U)                                           
+#define CAN_F5R2_FB18_Msk      (0x1UL << CAN_F5R2_FB18_Pos)                     /*!< 0x00040000 */
+#define CAN_F5R2_FB18          CAN_F5R2_FB18_Msk                               /*!<Filter bit 18 */
+#define CAN_F5R2_FB19_Pos      (19U)                                           
+#define CAN_F5R2_FB19_Msk      (0x1UL << CAN_F5R2_FB19_Pos)                     /*!< 0x00080000 */
+#define CAN_F5R2_FB19          CAN_F5R2_FB19_Msk                               /*!<Filter bit 19 */
+#define CAN_F5R2_FB20_Pos      (20U)                                           
+#define CAN_F5R2_FB20_Msk      (0x1UL << CAN_F5R2_FB20_Pos)                     /*!< 0x00100000 */
+#define CAN_F5R2_FB20          CAN_F5R2_FB20_Msk                               /*!<Filter bit 20 */
+#define CAN_F5R2_FB21_Pos      (21U)                                           
+#define CAN_F5R2_FB21_Msk      (0x1UL << CAN_F5R2_FB21_Pos)                     /*!< 0x00200000 */
+#define CAN_F5R2_FB21          CAN_F5R2_FB21_Msk                               /*!<Filter bit 21 */
+#define CAN_F5R2_FB22_Pos      (22U)                                           
+#define CAN_F5R2_FB22_Msk      (0x1UL << CAN_F5R2_FB22_Pos)                     /*!< 0x00400000 */
+#define CAN_F5R2_FB22          CAN_F5R2_FB22_Msk                               /*!<Filter bit 22 */
+#define CAN_F5R2_FB23_Pos      (23U)                                           
+#define CAN_F5R2_FB23_Msk      (0x1UL << CAN_F5R2_FB23_Pos)                     /*!< 0x00800000 */
+#define CAN_F5R2_FB23          CAN_F5R2_FB23_Msk                               /*!<Filter bit 23 */
+#define CAN_F5R2_FB24_Pos      (24U)                                           
+#define CAN_F5R2_FB24_Msk      (0x1UL << CAN_F5R2_FB24_Pos)                     /*!< 0x01000000 */
+#define CAN_F5R2_FB24          CAN_F5R2_FB24_Msk                               /*!<Filter bit 24 */
+#define CAN_F5R2_FB25_Pos      (25U)                                           
+#define CAN_F5R2_FB25_Msk      (0x1UL << CAN_F5R2_FB25_Pos)                     /*!< 0x02000000 */
+#define CAN_F5R2_FB25          CAN_F5R2_FB25_Msk                               /*!<Filter bit 25 */
+#define CAN_F5R2_FB26_Pos      (26U)                                           
+#define CAN_F5R2_FB26_Msk      (0x1UL << CAN_F5R2_FB26_Pos)                     /*!< 0x04000000 */
+#define CAN_F5R2_FB26          CAN_F5R2_FB26_Msk                               /*!<Filter bit 26 */
+#define CAN_F5R2_FB27_Pos      (27U)                                           
+#define CAN_F5R2_FB27_Msk      (0x1UL << CAN_F5R2_FB27_Pos)                     /*!< 0x08000000 */
+#define CAN_F5R2_FB27          CAN_F5R2_FB27_Msk                               /*!<Filter bit 27 */
+#define CAN_F5R2_FB28_Pos      (28U)                                           
+#define CAN_F5R2_FB28_Msk      (0x1UL << CAN_F5R2_FB28_Pos)                     /*!< 0x10000000 */
+#define CAN_F5R2_FB28          CAN_F5R2_FB28_Msk                               /*!<Filter bit 28 */
+#define CAN_F5R2_FB29_Pos      (29U)                                           
+#define CAN_F5R2_FB29_Msk      (0x1UL << CAN_F5R2_FB29_Pos)                     /*!< 0x20000000 */
+#define CAN_F5R2_FB29          CAN_F5R2_FB29_Msk                               /*!<Filter bit 29 */
+#define CAN_F5R2_FB30_Pos      (30U)                                           
+#define CAN_F5R2_FB30_Msk      (0x1UL << CAN_F5R2_FB30_Pos)                     /*!< 0x40000000 */
+#define CAN_F5R2_FB30          CAN_F5R2_FB30_Msk                               /*!<Filter bit 30 */
+#define CAN_F5R2_FB31_Pos      (31U)                                           
+#define CAN_F5R2_FB31_Msk      (0x1UL << CAN_F5R2_FB31_Pos)                     /*!< 0x80000000 */
+#define CAN_F5R2_FB31          CAN_F5R2_FB31_Msk                               /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F6R2 register  *******************/
+#define CAN_F6R2_FB0_Pos       (0U)                                            
+#define CAN_F6R2_FB0_Msk       (0x1UL << CAN_F6R2_FB0_Pos)                      /*!< 0x00000001 */
+#define CAN_F6R2_FB0           CAN_F6R2_FB0_Msk                                /*!<Filter bit 0 */
+#define CAN_F6R2_FB1_Pos       (1U)                                            
+#define CAN_F6R2_FB1_Msk       (0x1UL << CAN_F6R2_FB1_Pos)                      /*!< 0x00000002 */
+#define CAN_F6R2_FB1           CAN_F6R2_FB1_Msk                                /*!<Filter bit 1 */
+#define CAN_F6R2_FB2_Pos       (2U)                                            
+#define CAN_F6R2_FB2_Msk       (0x1UL << CAN_F6R2_FB2_Pos)                      /*!< 0x00000004 */
+#define CAN_F6R2_FB2           CAN_F6R2_FB2_Msk                                /*!<Filter bit 2 */
+#define CAN_F6R2_FB3_Pos       (3U)                                            
+#define CAN_F6R2_FB3_Msk       (0x1UL << CAN_F6R2_FB3_Pos)                      /*!< 0x00000008 */
+#define CAN_F6R2_FB3           CAN_F6R2_FB3_Msk                                /*!<Filter bit 3 */
+#define CAN_F6R2_FB4_Pos       (4U)                                            
+#define CAN_F6R2_FB4_Msk       (0x1UL << CAN_F6R2_FB4_Pos)                      /*!< 0x00000010 */
+#define CAN_F6R2_FB4           CAN_F6R2_FB4_Msk                                /*!<Filter bit 4 */
+#define CAN_F6R2_FB5_Pos       (5U)                                            
+#define CAN_F6R2_FB5_Msk       (0x1UL << CAN_F6R2_FB5_Pos)                      /*!< 0x00000020 */
+#define CAN_F6R2_FB5           CAN_F6R2_FB5_Msk                                /*!<Filter bit 5 */
+#define CAN_F6R2_FB6_Pos       (6U)                                            
+#define CAN_F6R2_FB6_Msk       (0x1UL << CAN_F6R2_FB6_Pos)                      /*!< 0x00000040 */
+#define CAN_F6R2_FB6           CAN_F6R2_FB6_Msk                                /*!<Filter bit 6 */
+#define CAN_F6R2_FB7_Pos       (7U)                                            
+#define CAN_F6R2_FB7_Msk       (0x1UL << CAN_F6R2_FB7_Pos)                      /*!< 0x00000080 */
+#define CAN_F6R2_FB7           CAN_F6R2_FB7_Msk                                /*!<Filter bit 7 */
+#define CAN_F6R2_FB8_Pos       (8U)                                            
+#define CAN_F6R2_FB8_Msk       (0x1UL << CAN_F6R2_FB8_Pos)                      /*!< 0x00000100 */
+#define CAN_F6R2_FB8           CAN_F6R2_FB8_Msk                                /*!<Filter bit 8 */
+#define CAN_F6R2_FB9_Pos       (9U)                                            
+#define CAN_F6R2_FB9_Msk       (0x1UL << CAN_F6R2_FB9_Pos)                      /*!< 0x00000200 */
+#define CAN_F6R2_FB9           CAN_F6R2_FB9_Msk                                /*!<Filter bit 9 */
+#define CAN_F6R2_FB10_Pos      (10U)                                           
+#define CAN_F6R2_FB10_Msk      (0x1UL << CAN_F6R2_FB10_Pos)                     /*!< 0x00000400 */
+#define CAN_F6R2_FB10          CAN_F6R2_FB10_Msk                               /*!<Filter bit 10 */
+#define CAN_F6R2_FB11_Pos      (11U)                                           
+#define CAN_F6R2_FB11_Msk      (0x1UL << CAN_F6R2_FB11_Pos)                     /*!< 0x00000800 */
+#define CAN_F6R2_FB11          CAN_F6R2_FB11_Msk                               /*!<Filter bit 11 */
+#define CAN_F6R2_FB12_Pos      (12U)                                           
+#define CAN_F6R2_FB12_Msk      (0x1UL << CAN_F6R2_FB12_Pos)                     /*!< 0x00001000 */
+#define CAN_F6R2_FB12          CAN_F6R2_FB12_Msk                               /*!<Filter bit 12 */
+#define CAN_F6R2_FB13_Pos      (13U)                                           
+#define CAN_F6R2_FB13_Msk      (0x1UL << CAN_F6R2_FB13_Pos)                     /*!< 0x00002000 */
+#define CAN_F6R2_FB13          CAN_F6R2_FB13_Msk                               /*!<Filter bit 13 */
+#define CAN_F6R2_FB14_Pos      (14U)                                           
+#define CAN_F6R2_FB14_Msk      (0x1UL << CAN_F6R2_FB14_Pos)                     /*!< 0x00004000 */
+#define CAN_F6R2_FB14          CAN_F6R2_FB14_Msk                               /*!<Filter bit 14 */
+#define CAN_F6R2_FB15_Pos      (15U)                                           
+#define CAN_F6R2_FB15_Msk      (0x1UL << CAN_F6R2_FB15_Pos)                     /*!< 0x00008000 */
+#define CAN_F6R2_FB15          CAN_F6R2_FB15_Msk                               /*!<Filter bit 15 */
+#define CAN_F6R2_FB16_Pos      (16U)                                           
+#define CAN_F6R2_FB16_Msk      (0x1UL << CAN_F6R2_FB16_Pos)                     /*!< 0x00010000 */
+#define CAN_F6R2_FB16          CAN_F6R2_FB16_Msk                               /*!<Filter bit 16 */
+#define CAN_F6R2_FB17_Pos      (17U)                                           
+#define CAN_F6R2_FB17_Msk      (0x1UL << CAN_F6R2_FB17_Pos)                     /*!< 0x00020000 */
+#define CAN_F6R2_FB17          CAN_F6R2_FB17_Msk                               /*!<Filter bit 17 */
+#define CAN_F6R2_FB18_Pos      (18U)                                           
+#define CAN_F6R2_FB18_Msk      (0x1UL << CAN_F6R2_FB18_Pos)                     /*!< 0x00040000 */
+#define CAN_F6R2_FB18          CAN_F6R2_FB18_Msk                               /*!<Filter bit 18 */
+#define CAN_F6R2_FB19_Pos      (19U)                                           
+#define CAN_F6R2_FB19_Msk      (0x1UL << CAN_F6R2_FB19_Pos)                     /*!< 0x00080000 */
+#define CAN_F6R2_FB19          CAN_F6R2_FB19_Msk                               /*!<Filter bit 19 */
+#define CAN_F6R2_FB20_Pos      (20U)                                           
+#define CAN_F6R2_FB20_Msk      (0x1UL << CAN_F6R2_FB20_Pos)                     /*!< 0x00100000 */
+#define CAN_F6R2_FB20          CAN_F6R2_FB20_Msk                               /*!<Filter bit 20 */
+#define CAN_F6R2_FB21_Pos      (21U)                                           
+#define CAN_F6R2_FB21_Msk      (0x1UL << CAN_F6R2_FB21_Pos)                     /*!< 0x00200000 */
+#define CAN_F6R2_FB21          CAN_F6R2_FB21_Msk                               /*!<Filter bit 21 */
+#define CAN_F6R2_FB22_Pos      (22U)                                           
+#define CAN_F6R2_FB22_Msk      (0x1UL << CAN_F6R2_FB22_Pos)                     /*!< 0x00400000 */
+#define CAN_F6R2_FB22          CAN_F6R2_FB22_Msk                               /*!<Filter bit 22 */
+#define CAN_F6R2_FB23_Pos      (23U)                                           
+#define CAN_F6R2_FB23_Msk      (0x1UL << CAN_F6R2_FB23_Pos)                     /*!< 0x00800000 */
+#define CAN_F6R2_FB23          CAN_F6R2_FB23_Msk                               /*!<Filter bit 23 */
+#define CAN_F6R2_FB24_Pos      (24U)                                           
+#define CAN_F6R2_FB24_Msk      (0x1UL << CAN_F6R2_FB24_Pos)                     /*!< 0x01000000 */
+#define CAN_F6R2_FB24          CAN_F6R2_FB24_Msk                               /*!<Filter bit 24 */
+#define CAN_F6R2_FB25_Pos      (25U)                                           
+#define CAN_F6R2_FB25_Msk      (0x1UL << CAN_F6R2_FB25_Pos)                     /*!< 0x02000000 */
+#define CAN_F6R2_FB25          CAN_F6R2_FB25_Msk                               /*!<Filter bit 25 */
+#define CAN_F6R2_FB26_Pos      (26U)                                           
+#define CAN_F6R2_FB26_Msk      (0x1UL << CAN_F6R2_FB26_Pos)                     /*!< 0x04000000 */
+#define CAN_F6R2_FB26          CAN_F6R2_FB26_Msk                               /*!<Filter bit 26 */
+#define CAN_F6R2_FB27_Pos      (27U)                                           
+#define CAN_F6R2_FB27_Msk      (0x1UL << CAN_F6R2_FB27_Pos)                     /*!< 0x08000000 */
+#define CAN_F6R2_FB27          CAN_F6R2_FB27_Msk                               /*!<Filter bit 27 */
+#define CAN_F6R2_FB28_Pos      (28U)                                           
+#define CAN_F6R2_FB28_Msk      (0x1UL << CAN_F6R2_FB28_Pos)                     /*!< 0x10000000 */
+#define CAN_F6R2_FB28          CAN_F6R2_FB28_Msk                               /*!<Filter bit 28 */
+#define CAN_F6R2_FB29_Pos      (29U)                                           
+#define CAN_F6R2_FB29_Msk      (0x1UL << CAN_F6R2_FB29_Pos)                     /*!< 0x20000000 */
+#define CAN_F6R2_FB29          CAN_F6R2_FB29_Msk                               /*!<Filter bit 29 */
+#define CAN_F6R2_FB30_Pos      (30U)                                           
+#define CAN_F6R2_FB30_Msk      (0x1UL << CAN_F6R2_FB30_Pos)                     /*!< 0x40000000 */
+#define CAN_F6R2_FB30          CAN_F6R2_FB30_Msk                               /*!<Filter bit 30 */
+#define CAN_F6R2_FB31_Pos      (31U)                                           
+#define CAN_F6R2_FB31_Msk      (0x1UL << CAN_F6R2_FB31_Pos)                     /*!< 0x80000000 */
+#define CAN_F6R2_FB31          CAN_F6R2_FB31_Msk                               /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F7R2 register  *******************/
+#define CAN_F7R2_FB0_Pos       (0U)                                            
+#define CAN_F7R2_FB0_Msk       (0x1UL << CAN_F7R2_FB0_Pos)                      /*!< 0x00000001 */
+#define CAN_F7R2_FB0           CAN_F7R2_FB0_Msk                                /*!<Filter bit 0 */
+#define CAN_F7R2_FB1_Pos       (1U)                                            
+#define CAN_F7R2_FB1_Msk       (0x1UL << CAN_F7R2_FB1_Pos)                      /*!< 0x00000002 */
+#define CAN_F7R2_FB1           CAN_F7R2_FB1_Msk                                /*!<Filter bit 1 */
+#define CAN_F7R2_FB2_Pos       (2U)                                            
+#define CAN_F7R2_FB2_Msk       (0x1UL << CAN_F7R2_FB2_Pos)                      /*!< 0x00000004 */
+#define CAN_F7R2_FB2           CAN_F7R2_FB2_Msk                                /*!<Filter bit 2 */
+#define CAN_F7R2_FB3_Pos       (3U)                                            
+#define CAN_F7R2_FB3_Msk       (0x1UL << CAN_F7R2_FB3_Pos)                      /*!< 0x00000008 */
+#define CAN_F7R2_FB3           CAN_F7R2_FB3_Msk                                /*!<Filter bit 3 */
+#define CAN_F7R2_FB4_Pos       (4U)                                            
+#define CAN_F7R2_FB4_Msk       (0x1UL << CAN_F7R2_FB4_Pos)                      /*!< 0x00000010 */
+#define CAN_F7R2_FB4           CAN_F7R2_FB4_Msk                                /*!<Filter bit 4 */
+#define CAN_F7R2_FB5_Pos       (5U)                                            
+#define CAN_F7R2_FB5_Msk       (0x1UL << CAN_F7R2_FB5_Pos)                      /*!< 0x00000020 */
+#define CAN_F7R2_FB5           CAN_F7R2_FB5_Msk                                /*!<Filter bit 5 */
+#define CAN_F7R2_FB6_Pos       (6U)                                            
+#define CAN_F7R2_FB6_Msk       (0x1UL << CAN_F7R2_FB6_Pos)                      /*!< 0x00000040 */
+#define CAN_F7R2_FB6           CAN_F7R2_FB6_Msk                                /*!<Filter bit 6 */
+#define CAN_F7R2_FB7_Pos       (7U)                                            
+#define CAN_F7R2_FB7_Msk       (0x1UL << CAN_F7R2_FB7_Pos)                      /*!< 0x00000080 */
+#define CAN_F7R2_FB7           CAN_F7R2_FB7_Msk                                /*!<Filter bit 7 */
+#define CAN_F7R2_FB8_Pos       (8U)                                            
+#define CAN_F7R2_FB8_Msk       (0x1UL << CAN_F7R2_FB8_Pos)                      /*!< 0x00000100 */
+#define CAN_F7R2_FB8           CAN_F7R2_FB8_Msk                                /*!<Filter bit 8 */
+#define CAN_F7R2_FB9_Pos       (9U)                                            
+#define CAN_F7R2_FB9_Msk       (0x1UL << CAN_F7R2_FB9_Pos)                      /*!< 0x00000200 */
+#define CAN_F7R2_FB9           CAN_F7R2_FB9_Msk                                /*!<Filter bit 9 */
+#define CAN_F7R2_FB10_Pos      (10U)                                           
+#define CAN_F7R2_FB10_Msk      (0x1UL << CAN_F7R2_FB10_Pos)                     /*!< 0x00000400 */
+#define CAN_F7R2_FB10          CAN_F7R2_FB10_Msk                               /*!<Filter bit 10 */
+#define CAN_F7R2_FB11_Pos      (11U)                                           
+#define CAN_F7R2_FB11_Msk      (0x1UL << CAN_F7R2_FB11_Pos)                     /*!< 0x00000800 */
+#define CAN_F7R2_FB11          CAN_F7R2_FB11_Msk                               /*!<Filter bit 11 */
+#define CAN_F7R2_FB12_Pos      (12U)                                           
+#define CAN_F7R2_FB12_Msk      (0x1UL << CAN_F7R2_FB12_Pos)                     /*!< 0x00001000 */
+#define CAN_F7R2_FB12          CAN_F7R2_FB12_Msk                               /*!<Filter bit 12 */
+#define CAN_F7R2_FB13_Pos      (13U)                                           
+#define CAN_F7R2_FB13_Msk      (0x1UL << CAN_F7R2_FB13_Pos)                     /*!< 0x00002000 */
+#define CAN_F7R2_FB13          CAN_F7R2_FB13_Msk                               /*!<Filter bit 13 */
+#define CAN_F7R2_FB14_Pos      (14U)                                           
+#define CAN_F7R2_FB14_Msk      (0x1UL << CAN_F7R2_FB14_Pos)                     /*!< 0x00004000 */
+#define CAN_F7R2_FB14          CAN_F7R2_FB14_Msk                               /*!<Filter bit 14 */
+#define CAN_F7R2_FB15_Pos      (15U)                                           
+#define CAN_F7R2_FB15_Msk      (0x1UL << CAN_F7R2_FB15_Pos)                     /*!< 0x00008000 */
+#define CAN_F7R2_FB15          CAN_F7R2_FB15_Msk                               /*!<Filter bit 15 */
+#define CAN_F7R2_FB16_Pos      (16U)                                           
+#define CAN_F7R2_FB16_Msk      (0x1UL << CAN_F7R2_FB16_Pos)                     /*!< 0x00010000 */
+#define CAN_F7R2_FB16          CAN_F7R2_FB16_Msk                               /*!<Filter bit 16 */
+#define CAN_F7R2_FB17_Pos      (17U)                                           
+#define CAN_F7R2_FB17_Msk      (0x1UL << CAN_F7R2_FB17_Pos)                     /*!< 0x00020000 */
+#define CAN_F7R2_FB17          CAN_F7R2_FB17_Msk                               /*!<Filter bit 17 */
+#define CAN_F7R2_FB18_Pos      (18U)                                           
+#define CAN_F7R2_FB18_Msk      (0x1UL << CAN_F7R2_FB18_Pos)                     /*!< 0x00040000 */
+#define CAN_F7R2_FB18          CAN_F7R2_FB18_Msk                               /*!<Filter bit 18 */
+#define CAN_F7R2_FB19_Pos      (19U)                                           
+#define CAN_F7R2_FB19_Msk      (0x1UL << CAN_F7R2_FB19_Pos)                     /*!< 0x00080000 */
+#define CAN_F7R2_FB19          CAN_F7R2_FB19_Msk                               /*!<Filter bit 19 */
+#define CAN_F7R2_FB20_Pos      (20U)                                           
+#define CAN_F7R2_FB20_Msk      (0x1UL << CAN_F7R2_FB20_Pos)                     /*!< 0x00100000 */
+#define CAN_F7R2_FB20          CAN_F7R2_FB20_Msk                               /*!<Filter bit 20 */
+#define CAN_F7R2_FB21_Pos      (21U)                                           
+#define CAN_F7R2_FB21_Msk      (0x1UL << CAN_F7R2_FB21_Pos)                     /*!< 0x00200000 */
+#define CAN_F7R2_FB21          CAN_F7R2_FB21_Msk                               /*!<Filter bit 21 */
+#define CAN_F7R2_FB22_Pos      (22U)                                           
+#define CAN_F7R2_FB22_Msk      (0x1UL << CAN_F7R2_FB22_Pos)                     /*!< 0x00400000 */
+#define CAN_F7R2_FB22          CAN_F7R2_FB22_Msk                               /*!<Filter bit 22 */
+#define CAN_F7R2_FB23_Pos      (23U)                                           
+#define CAN_F7R2_FB23_Msk      (0x1UL << CAN_F7R2_FB23_Pos)                     /*!< 0x00800000 */
+#define CAN_F7R2_FB23          CAN_F7R2_FB23_Msk                               /*!<Filter bit 23 */
+#define CAN_F7R2_FB24_Pos      (24U)                                           
+#define CAN_F7R2_FB24_Msk      (0x1UL << CAN_F7R2_FB24_Pos)                     /*!< 0x01000000 */
+#define CAN_F7R2_FB24          CAN_F7R2_FB24_Msk                               /*!<Filter bit 24 */
+#define CAN_F7R2_FB25_Pos      (25U)                                           
+#define CAN_F7R2_FB25_Msk      (0x1UL << CAN_F7R2_FB25_Pos)                     /*!< 0x02000000 */
+#define CAN_F7R2_FB25          CAN_F7R2_FB25_Msk                               /*!<Filter bit 25 */
+#define CAN_F7R2_FB26_Pos      (26U)                                           
+#define CAN_F7R2_FB26_Msk      (0x1UL << CAN_F7R2_FB26_Pos)                     /*!< 0x04000000 */
+#define CAN_F7R2_FB26          CAN_F7R2_FB26_Msk                               /*!<Filter bit 26 */
+#define CAN_F7R2_FB27_Pos      (27U)                                           
+#define CAN_F7R2_FB27_Msk      (0x1UL << CAN_F7R2_FB27_Pos)                     /*!< 0x08000000 */
+#define CAN_F7R2_FB27          CAN_F7R2_FB27_Msk                               /*!<Filter bit 27 */
+#define CAN_F7R2_FB28_Pos      (28U)                                           
+#define CAN_F7R2_FB28_Msk      (0x1UL << CAN_F7R2_FB28_Pos)                     /*!< 0x10000000 */
+#define CAN_F7R2_FB28          CAN_F7R2_FB28_Msk                               /*!<Filter bit 28 */
+#define CAN_F7R2_FB29_Pos      (29U)                                           
+#define CAN_F7R2_FB29_Msk      (0x1UL << CAN_F7R2_FB29_Pos)                     /*!< 0x20000000 */
+#define CAN_F7R2_FB29          CAN_F7R2_FB29_Msk                               /*!<Filter bit 29 */
+#define CAN_F7R2_FB30_Pos      (30U)                                           
+#define CAN_F7R2_FB30_Msk      (0x1UL << CAN_F7R2_FB30_Pos)                     /*!< 0x40000000 */
+#define CAN_F7R2_FB30          CAN_F7R2_FB30_Msk                               /*!<Filter bit 30 */
+#define CAN_F7R2_FB31_Pos      (31U)                                           
+#define CAN_F7R2_FB31_Msk      (0x1UL << CAN_F7R2_FB31_Pos)                     /*!< 0x80000000 */
+#define CAN_F7R2_FB31          CAN_F7R2_FB31_Msk                               /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F8R2 register  *******************/
+#define CAN_F8R2_FB0_Pos       (0U)                                            
+#define CAN_F8R2_FB0_Msk       (0x1UL << CAN_F8R2_FB0_Pos)                      /*!< 0x00000001 */
+#define CAN_F8R2_FB0           CAN_F8R2_FB0_Msk                                /*!<Filter bit 0 */
+#define CAN_F8R2_FB1_Pos       (1U)                                            
+#define CAN_F8R2_FB1_Msk       (0x1UL << CAN_F8R2_FB1_Pos)                      /*!< 0x00000002 */
+#define CAN_F8R2_FB1           CAN_F8R2_FB1_Msk                                /*!<Filter bit 1 */
+#define CAN_F8R2_FB2_Pos       (2U)                                            
+#define CAN_F8R2_FB2_Msk       (0x1UL << CAN_F8R2_FB2_Pos)                      /*!< 0x00000004 */
+#define CAN_F8R2_FB2           CAN_F8R2_FB2_Msk                                /*!<Filter bit 2 */
+#define CAN_F8R2_FB3_Pos       (3U)                                            
+#define CAN_F8R2_FB3_Msk       (0x1UL << CAN_F8R2_FB3_Pos)                      /*!< 0x00000008 */
+#define CAN_F8R2_FB3           CAN_F8R2_FB3_Msk                                /*!<Filter bit 3 */
+#define CAN_F8R2_FB4_Pos       (4U)                                            
+#define CAN_F8R2_FB4_Msk       (0x1UL << CAN_F8R2_FB4_Pos)                      /*!< 0x00000010 */
+#define CAN_F8R2_FB4           CAN_F8R2_FB4_Msk                                /*!<Filter bit 4 */
+#define CAN_F8R2_FB5_Pos       (5U)                                            
+#define CAN_F8R2_FB5_Msk       (0x1UL << CAN_F8R2_FB5_Pos)                      /*!< 0x00000020 */
+#define CAN_F8R2_FB5           CAN_F8R2_FB5_Msk                                /*!<Filter bit 5 */
+#define CAN_F8R2_FB6_Pos       (6U)                                            
+#define CAN_F8R2_FB6_Msk       (0x1UL << CAN_F8R2_FB6_Pos)                      /*!< 0x00000040 */
+#define CAN_F8R2_FB6           CAN_F8R2_FB6_Msk                                /*!<Filter bit 6 */
+#define CAN_F8R2_FB7_Pos       (7U)                                            
+#define CAN_F8R2_FB7_Msk       (0x1UL << CAN_F8R2_FB7_Pos)                      /*!< 0x00000080 */
+#define CAN_F8R2_FB7           CAN_F8R2_FB7_Msk                                /*!<Filter bit 7 */
+#define CAN_F8R2_FB8_Pos       (8U)                                            
+#define CAN_F8R2_FB8_Msk       (0x1UL << CAN_F8R2_FB8_Pos)                      /*!< 0x00000100 */
+#define CAN_F8R2_FB8           CAN_F8R2_FB8_Msk                                /*!<Filter bit 8 */
+#define CAN_F8R2_FB9_Pos       (9U)                                            
+#define CAN_F8R2_FB9_Msk       (0x1UL << CAN_F8R2_FB9_Pos)                      /*!< 0x00000200 */
+#define CAN_F8R2_FB9           CAN_F8R2_FB9_Msk                                /*!<Filter bit 9 */
+#define CAN_F8R2_FB10_Pos      (10U)                                           
+#define CAN_F8R2_FB10_Msk      (0x1UL << CAN_F8R2_FB10_Pos)                     /*!< 0x00000400 */
+#define CAN_F8R2_FB10          CAN_F8R2_FB10_Msk                               /*!<Filter bit 10 */
+#define CAN_F8R2_FB11_Pos      (11U)                                           
+#define CAN_F8R2_FB11_Msk      (0x1UL << CAN_F8R2_FB11_Pos)                     /*!< 0x00000800 */
+#define CAN_F8R2_FB11          CAN_F8R2_FB11_Msk                               /*!<Filter bit 11 */
+#define CAN_F8R2_FB12_Pos      (12U)                                           
+#define CAN_F8R2_FB12_Msk      (0x1UL << CAN_F8R2_FB12_Pos)                     /*!< 0x00001000 */
+#define CAN_F8R2_FB12          CAN_F8R2_FB12_Msk                               /*!<Filter bit 12 */
+#define CAN_F8R2_FB13_Pos      (13U)                                           
+#define CAN_F8R2_FB13_Msk      (0x1UL << CAN_F8R2_FB13_Pos)                     /*!< 0x00002000 */
+#define CAN_F8R2_FB13          CAN_F8R2_FB13_Msk                               /*!<Filter bit 13 */
+#define CAN_F8R2_FB14_Pos      (14U)                                           
+#define CAN_F8R2_FB14_Msk      (0x1UL << CAN_F8R2_FB14_Pos)                     /*!< 0x00004000 */
+#define CAN_F8R2_FB14          CAN_F8R2_FB14_Msk                               /*!<Filter bit 14 */
+#define CAN_F8R2_FB15_Pos      (15U)                                           
+#define CAN_F8R2_FB15_Msk      (0x1UL << CAN_F8R2_FB15_Pos)                     /*!< 0x00008000 */
+#define CAN_F8R2_FB15          CAN_F8R2_FB15_Msk                               /*!<Filter bit 15 */
+#define CAN_F8R2_FB16_Pos      (16U)                                           
+#define CAN_F8R2_FB16_Msk      (0x1UL << CAN_F8R2_FB16_Pos)                     /*!< 0x00010000 */
+#define CAN_F8R2_FB16          CAN_F8R2_FB16_Msk                               /*!<Filter bit 16 */
+#define CAN_F8R2_FB17_Pos      (17U)                                           
+#define CAN_F8R2_FB17_Msk      (0x1UL << CAN_F8R2_FB17_Pos)                     /*!< 0x00020000 */
+#define CAN_F8R2_FB17          CAN_F8R2_FB17_Msk                               /*!<Filter bit 17 */
+#define CAN_F8R2_FB18_Pos      (18U)                                           
+#define CAN_F8R2_FB18_Msk      (0x1UL << CAN_F8R2_FB18_Pos)                     /*!< 0x00040000 */
+#define CAN_F8R2_FB18          CAN_F8R2_FB18_Msk                               /*!<Filter bit 18 */
+#define CAN_F8R2_FB19_Pos      (19U)                                           
+#define CAN_F8R2_FB19_Msk      (0x1UL << CAN_F8R2_FB19_Pos)                     /*!< 0x00080000 */
+#define CAN_F8R2_FB19          CAN_F8R2_FB19_Msk                               /*!<Filter bit 19 */
+#define CAN_F8R2_FB20_Pos      (20U)                                           
+#define CAN_F8R2_FB20_Msk      (0x1UL << CAN_F8R2_FB20_Pos)                     /*!< 0x00100000 */
+#define CAN_F8R2_FB20          CAN_F8R2_FB20_Msk                               /*!<Filter bit 20 */
+#define CAN_F8R2_FB21_Pos      (21U)                                           
+#define CAN_F8R2_FB21_Msk      (0x1UL << CAN_F8R2_FB21_Pos)                     /*!< 0x00200000 */
+#define CAN_F8R2_FB21          CAN_F8R2_FB21_Msk                               /*!<Filter bit 21 */
+#define CAN_F8R2_FB22_Pos      (22U)                                           
+#define CAN_F8R2_FB22_Msk      (0x1UL << CAN_F8R2_FB22_Pos)                     /*!< 0x00400000 */
+#define CAN_F8R2_FB22          CAN_F8R2_FB22_Msk                               /*!<Filter bit 22 */
+#define CAN_F8R2_FB23_Pos      (23U)                                           
+#define CAN_F8R2_FB23_Msk      (0x1UL << CAN_F8R2_FB23_Pos)                     /*!< 0x00800000 */
+#define CAN_F8R2_FB23          CAN_F8R2_FB23_Msk                               /*!<Filter bit 23 */
+#define CAN_F8R2_FB24_Pos      (24U)                                           
+#define CAN_F8R2_FB24_Msk      (0x1UL << CAN_F8R2_FB24_Pos)                     /*!< 0x01000000 */
+#define CAN_F8R2_FB24          CAN_F8R2_FB24_Msk                               /*!<Filter bit 24 */
+#define CAN_F8R2_FB25_Pos      (25U)                                           
+#define CAN_F8R2_FB25_Msk      (0x1UL << CAN_F8R2_FB25_Pos)                     /*!< 0x02000000 */
+#define CAN_F8R2_FB25          CAN_F8R2_FB25_Msk                               /*!<Filter bit 25 */
+#define CAN_F8R2_FB26_Pos      (26U)                                           
+#define CAN_F8R2_FB26_Msk      (0x1UL << CAN_F8R2_FB26_Pos)                     /*!< 0x04000000 */
+#define CAN_F8R2_FB26          CAN_F8R2_FB26_Msk                               /*!<Filter bit 26 */
+#define CAN_F8R2_FB27_Pos      (27U)                                           
+#define CAN_F8R2_FB27_Msk      (0x1UL << CAN_F8R2_FB27_Pos)                     /*!< 0x08000000 */
+#define CAN_F8R2_FB27          CAN_F8R2_FB27_Msk                               /*!<Filter bit 27 */
+#define CAN_F8R2_FB28_Pos      (28U)                                           
+#define CAN_F8R2_FB28_Msk      (0x1UL << CAN_F8R2_FB28_Pos)                     /*!< 0x10000000 */
+#define CAN_F8R2_FB28          CAN_F8R2_FB28_Msk                               /*!<Filter bit 28 */
+#define CAN_F8R2_FB29_Pos      (29U)                                           
+#define CAN_F8R2_FB29_Msk      (0x1UL << CAN_F8R2_FB29_Pos)                     /*!< 0x20000000 */
+#define CAN_F8R2_FB29          CAN_F8R2_FB29_Msk                               /*!<Filter bit 29 */
+#define CAN_F8R2_FB30_Pos      (30U)                                           
+#define CAN_F8R2_FB30_Msk      (0x1UL << CAN_F8R2_FB30_Pos)                     /*!< 0x40000000 */
+#define CAN_F8R2_FB30          CAN_F8R2_FB30_Msk                               /*!<Filter bit 30 */
+#define CAN_F8R2_FB31_Pos      (31U)                                           
+#define CAN_F8R2_FB31_Msk      (0x1UL << CAN_F8R2_FB31_Pos)                     /*!< 0x80000000 */
+#define CAN_F8R2_FB31          CAN_F8R2_FB31_Msk                               /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F9R2 register  *******************/
+#define CAN_F9R2_FB0_Pos       (0U)                                            
+#define CAN_F9R2_FB0_Msk       (0x1UL << CAN_F9R2_FB0_Pos)                      /*!< 0x00000001 */
+#define CAN_F9R2_FB0           CAN_F9R2_FB0_Msk                                /*!<Filter bit 0 */
+#define CAN_F9R2_FB1_Pos       (1U)                                            
+#define CAN_F9R2_FB1_Msk       (0x1UL << CAN_F9R2_FB1_Pos)                      /*!< 0x00000002 */
+#define CAN_F9R2_FB1           CAN_F9R2_FB1_Msk                                /*!<Filter bit 1 */
+#define CAN_F9R2_FB2_Pos       (2U)                                            
+#define CAN_F9R2_FB2_Msk       (0x1UL << CAN_F9R2_FB2_Pos)                      /*!< 0x00000004 */
+#define CAN_F9R2_FB2           CAN_F9R2_FB2_Msk                                /*!<Filter bit 2 */
+#define CAN_F9R2_FB3_Pos       (3U)                                            
+#define CAN_F9R2_FB3_Msk       (0x1UL << CAN_F9R2_FB3_Pos)                      /*!< 0x00000008 */
+#define CAN_F9R2_FB3           CAN_F9R2_FB3_Msk                                /*!<Filter bit 3 */
+#define CAN_F9R2_FB4_Pos       (4U)                                            
+#define CAN_F9R2_FB4_Msk       (0x1UL << CAN_F9R2_FB4_Pos)                      /*!< 0x00000010 */
+#define CAN_F9R2_FB4           CAN_F9R2_FB4_Msk                                /*!<Filter bit 4 */
+#define CAN_F9R2_FB5_Pos       (5U)                                            
+#define CAN_F9R2_FB5_Msk       (0x1UL << CAN_F9R2_FB5_Pos)                      /*!< 0x00000020 */
+#define CAN_F9R2_FB5           CAN_F9R2_FB5_Msk                                /*!<Filter bit 5 */
+#define CAN_F9R2_FB6_Pos       (6U)                                            
+#define CAN_F9R2_FB6_Msk       (0x1UL << CAN_F9R2_FB6_Pos)                      /*!< 0x00000040 */
+#define CAN_F9R2_FB6           CAN_F9R2_FB6_Msk                                /*!<Filter bit 6 */
+#define CAN_F9R2_FB7_Pos       (7U)                                            
+#define CAN_F9R2_FB7_Msk       (0x1UL << CAN_F9R2_FB7_Pos)                      /*!< 0x00000080 */
+#define CAN_F9R2_FB7           CAN_F9R2_FB7_Msk                                /*!<Filter bit 7 */
+#define CAN_F9R2_FB8_Pos       (8U)                                            
+#define CAN_F9R2_FB8_Msk       (0x1UL << CAN_F9R2_FB8_Pos)                      /*!< 0x00000100 */
+#define CAN_F9R2_FB8           CAN_F9R2_FB8_Msk                                /*!<Filter bit 8 */
+#define CAN_F9R2_FB9_Pos       (9U)                                            
+#define CAN_F9R2_FB9_Msk       (0x1UL << CAN_F9R2_FB9_Pos)                      /*!< 0x00000200 */
+#define CAN_F9R2_FB9           CAN_F9R2_FB9_Msk                                /*!<Filter bit 9 */
+#define CAN_F9R2_FB10_Pos      (10U)                                           
+#define CAN_F9R2_FB10_Msk      (0x1UL << CAN_F9R2_FB10_Pos)                     /*!< 0x00000400 */
+#define CAN_F9R2_FB10          CAN_F9R2_FB10_Msk                               /*!<Filter bit 10 */
+#define CAN_F9R2_FB11_Pos      (11U)                                           
+#define CAN_F9R2_FB11_Msk      (0x1UL << CAN_F9R2_FB11_Pos)                     /*!< 0x00000800 */
+#define CAN_F9R2_FB11          CAN_F9R2_FB11_Msk                               /*!<Filter bit 11 */
+#define CAN_F9R2_FB12_Pos      (12U)                                           
+#define CAN_F9R2_FB12_Msk      (0x1UL << CAN_F9R2_FB12_Pos)                     /*!< 0x00001000 */
+#define CAN_F9R2_FB12          CAN_F9R2_FB12_Msk                               /*!<Filter bit 12 */
+#define CAN_F9R2_FB13_Pos      (13U)                                           
+#define CAN_F9R2_FB13_Msk      (0x1UL << CAN_F9R2_FB13_Pos)                     /*!< 0x00002000 */
+#define CAN_F9R2_FB13          CAN_F9R2_FB13_Msk                               /*!<Filter bit 13 */
+#define CAN_F9R2_FB14_Pos      (14U)                                           
+#define CAN_F9R2_FB14_Msk      (0x1UL << CAN_F9R2_FB14_Pos)                     /*!< 0x00004000 */
+#define CAN_F9R2_FB14          CAN_F9R2_FB14_Msk                               /*!<Filter bit 14 */
+#define CAN_F9R2_FB15_Pos      (15U)                                           
+#define CAN_F9R2_FB15_Msk      (0x1UL << CAN_F9R2_FB15_Pos)                     /*!< 0x00008000 */
+#define CAN_F9R2_FB15          CAN_F9R2_FB15_Msk                               /*!<Filter bit 15 */
+#define CAN_F9R2_FB16_Pos      (16U)                                           
+#define CAN_F9R2_FB16_Msk      (0x1UL << CAN_F9R2_FB16_Pos)                     /*!< 0x00010000 */
+#define CAN_F9R2_FB16          CAN_F9R2_FB16_Msk                               /*!<Filter bit 16 */
+#define CAN_F9R2_FB17_Pos      (17U)                                           
+#define CAN_F9R2_FB17_Msk      (0x1UL << CAN_F9R2_FB17_Pos)                     /*!< 0x00020000 */
+#define CAN_F9R2_FB17          CAN_F9R2_FB17_Msk                               /*!<Filter bit 17 */
+#define CAN_F9R2_FB18_Pos      (18U)                                           
+#define CAN_F9R2_FB18_Msk      (0x1UL << CAN_F9R2_FB18_Pos)                     /*!< 0x00040000 */
+#define CAN_F9R2_FB18          CAN_F9R2_FB18_Msk                               /*!<Filter bit 18 */
+#define CAN_F9R2_FB19_Pos      (19U)                                           
+#define CAN_F9R2_FB19_Msk      (0x1UL << CAN_F9R2_FB19_Pos)                     /*!< 0x00080000 */
+#define CAN_F9R2_FB19          CAN_F9R2_FB19_Msk                               /*!<Filter bit 19 */
+#define CAN_F9R2_FB20_Pos      (20U)                                           
+#define CAN_F9R2_FB20_Msk      (0x1UL << CAN_F9R2_FB20_Pos)                     /*!< 0x00100000 */
+#define CAN_F9R2_FB20          CAN_F9R2_FB20_Msk                               /*!<Filter bit 20 */
+#define CAN_F9R2_FB21_Pos      (21U)                                           
+#define CAN_F9R2_FB21_Msk      (0x1UL << CAN_F9R2_FB21_Pos)                     /*!< 0x00200000 */
+#define CAN_F9R2_FB21          CAN_F9R2_FB21_Msk                               /*!<Filter bit 21 */
+#define CAN_F9R2_FB22_Pos      (22U)                                           
+#define CAN_F9R2_FB22_Msk      (0x1UL << CAN_F9R2_FB22_Pos)                     /*!< 0x00400000 */
+#define CAN_F9R2_FB22          CAN_F9R2_FB22_Msk                               /*!<Filter bit 22 */
+#define CAN_F9R2_FB23_Pos      (23U)                                           
+#define CAN_F9R2_FB23_Msk      (0x1UL << CAN_F9R2_FB23_Pos)                     /*!< 0x00800000 */
+#define CAN_F9R2_FB23          CAN_F9R2_FB23_Msk                               /*!<Filter bit 23 */
+#define CAN_F9R2_FB24_Pos      (24U)                                           
+#define CAN_F9R2_FB24_Msk      (0x1UL << CAN_F9R2_FB24_Pos)                     /*!< 0x01000000 */
+#define CAN_F9R2_FB24          CAN_F9R2_FB24_Msk                               /*!<Filter bit 24 */
+#define CAN_F9R2_FB25_Pos      (25U)                                           
+#define CAN_F9R2_FB25_Msk      (0x1UL << CAN_F9R2_FB25_Pos)                     /*!< 0x02000000 */
+#define CAN_F9R2_FB25          CAN_F9R2_FB25_Msk                               /*!<Filter bit 25 */
+#define CAN_F9R2_FB26_Pos      (26U)                                           
+#define CAN_F9R2_FB26_Msk      (0x1UL << CAN_F9R2_FB26_Pos)                     /*!< 0x04000000 */
+#define CAN_F9R2_FB26          CAN_F9R2_FB26_Msk                               /*!<Filter bit 26 */
+#define CAN_F9R2_FB27_Pos      (27U)                                           
+#define CAN_F9R2_FB27_Msk      (0x1UL << CAN_F9R2_FB27_Pos)                     /*!< 0x08000000 */
+#define CAN_F9R2_FB27          CAN_F9R2_FB27_Msk                               /*!<Filter bit 27 */
+#define CAN_F9R2_FB28_Pos      (28U)                                           
+#define CAN_F9R2_FB28_Msk      (0x1UL << CAN_F9R2_FB28_Pos)                     /*!< 0x10000000 */
+#define CAN_F9R2_FB28          CAN_F9R2_FB28_Msk                               /*!<Filter bit 28 */
+#define CAN_F9R2_FB29_Pos      (29U)                                           
+#define CAN_F9R2_FB29_Msk      (0x1UL << CAN_F9R2_FB29_Pos)                     /*!< 0x20000000 */
+#define CAN_F9R2_FB29          CAN_F9R2_FB29_Msk                               /*!<Filter bit 29 */
+#define CAN_F9R2_FB30_Pos      (30U)                                           
+#define CAN_F9R2_FB30_Msk      (0x1UL << CAN_F9R2_FB30_Pos)                     /*!< 0x40000000 */
+#define CAN_F9R2_FB30          CAN_F9R2_FB30_Msk                               /*!<Filter bit 30 */
+#define CAN_F9R2_FB31_Pos      (31U)                                           
+#define CAN_F9R2_FB31_Msk      (0x1UL << CAN_F9R2_FB31_Pos)                     /*!< 0x80000000 */
+#define CAN_F9R2_FB31          CAN_F9R2_FB31_Msk                               /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F10R2 register  ******************/
+#define CAN_F10R2_FB0_Pos      (0U)                                            
+#define CAN_F10R2_FB0_Msk      (0x1UL << CAN_F10R2_FB0_Pos)                     /*!< 0x00000001 */
+#define CAN_F10R2_FB0          CAN_F10R2_FB0_Msk                               /*!<Filter bit 0 */
+#define CAN_F10R2_FB1_Pos      (1U)                                            
+#define CAN_F10R2_FB1_Msk      (0x1UL << CAN_F10R2_FB1_Pos)                     /*!< 0x00000002 */
+#define CAN_F10R2_FB1          CAN_F10R2_FB1_Msk                               /*!<Filter bit 1 */
+#define CAN_F10R2_FB2_Pos      (2U)                                            
+#define CAN_F10R2_FB2_Msk      (0x1UL << CAN_F10R2_FB2_Pos)                     /*!< 0x00000004 */
+#define CAN_F10R2_FB2          CAN_F10R2_FB2_Msk                               /*!<Filter bit 2 */
+#define CAN_F10R2_FB3_Pos      (3U)                                            
+#define CAN_F10R2_FB3_Msk      (0x1UL << CAN_F10R2_FB3_Pos)                     /*!< 0x00000008 */
+#define CAN_F10R2_FB3          CAN_F10R2_FB3_Msk                               /*!<Filter bit 3 */
+#define CAN_F10R2_FB4_Pos      (4U)                                            
+#define CAN_F10R2_FB4_Msk      (0x1UL << CAN_F10R2_FB4_Pos)                     /*!< 0x00000010 */
+#define CAN_F10R2_FB4          CAN_F10R2_FB4_Msk                               /*!<Filter bit 4 */
+#define CAN_F10R2_FB5_Pos      (5U)                                            
+#define CAN_F10R2_FB5_Msk      (0x1UL << CAN_F10R2_FB5_Pos)                     /*!< 0x00000020 */
+#define CAN_F10R2_FB5          CAN_F10R2_FB5_Msk                               /*!<Filter bit 5 */
+#define CAN_F10R2_FB6_Pos      (6U)                                            
+#define CAN_F10R2_FB6_Msk      (0x1UL << CAN_F10R2_FB6_Pos)                     /*!< 0x00000040 */
+#define CAN_F10R2_FB6          CAN_F10R2_FB6_Msk                               /*!<Filter bit 6 */
+#define CAN_F10R2_FB7_Pos      (7U)                                            
+#define CAN_F10R2_FB7_Msk      (0x1UL << CAN_F10R2_FB7_Pos)                     /*!< 0x00000080 */
+#define CAN_F10R2_FB7          CAN_F10R2_FB7_Msk                               /*!<Filter bit 7 */
+#define CAN_F10R2_FB8_Pos      (8U)                                            
+#define CAN_F10R2_FB8_Msk      (0x1UL << CAN_F10R2_FB8_Pos)                     /*!< 0x00000100 */
+#define CAN_F10R2_FB8          CAN_F10R2_FB8_Msk                               /*!<Filter bit 8 */
+#define CAN_F10R2_FB9_Pos      (9U)                                            
+#define CAN_F10R2_FB9_Msk      (0x1UL << CAN_F10R2_FB9_Pos)                     /*!< 0x00000200 */
+#define CAN_F10R2_FB9          CAN_F10R2_FB9_Msk                               /*!<Filter bit 9 */
+#define CAN_F10R2_FB10_Pos     (10U)                                           
+#define CAN_F10R2_FB10_Msk     (0x1UL << CAN_F10R2_FB10_Pos)                    /*!< 0x00000400 */
+#define CAN_F10R2_FB10         CAN_F10R2_FB10_Msk                              /*!<Filter bit 10 */
+#define CAN_F10R2_FB11_Pos     (11U)                                           
+#define CAN_F10R2_FB11_Msk     (0x1UL << CAN_F10R2_FB11_Pos)                    /*!< 0x00000800 */
+#define CAN_F10R2_FB11         CAN_F10R2_FB11_Msk                              /*!<Filter bit 11 */
+#define CAN_F10R2_FB12_Pos     (12U)                                           
+#define CAN_F10R2_FB12_Msk     (0x1UL << CAN_F10R2_FB12_Pos)                    /*!< 0x00001000 */
+#define CAN_F10R2_FB12         CAN_F10R2_FB12_Msk                              /*!<Filter bit 12 */
+#define CAN_F10R2_FB13_Pos     (13U)                                           
+#define CAN_F10R2_FB13_Msk     (0x1UL << CAN_F10R2_FB13_Pos)                    /*!< 0x00002000 */
+#define CAN_F10R2_FB13         CAN_F10R2_FB13_Msk                              /*!<Filter bit 13 */
+#define CAN_F10R2_FB14_Pos     (14U)                                           
+#define CAN_F10R2_FB14_Msk     (0x1UL << CAN_F10R2_FB14_Pos)                    /*!< 0x00004000 */
+#define CAN_F10R2_FB14         CAN_F10R2_FB14_Msk                              /*!<Filter bit 14 */
+#define CAN_F10R2_FB15_Pos     (15U)                                           
+#define CAN_F10R2_FB15_Msk     (0x1UL << CAN_F10R2_FB15_Pos)                    /*!< 0x00008000 */
+#define CAN_F10R2_FB15         CAN_F10R2_FB15_Msk                              /*!<Filter bit 15 */
+#define CAN_F10R2_FB16_Pos     (16U)                                           
+#define CAN_F10R2_FB16_Msk     (0x1UL << CAN_F10R2_FB16_Pos)                    /*!< 0x00010000 */
+#define CAN_F10R2_FB16         CAN_F10R2_FB16_Msk                              /*!<Filter bit 16 */
+#define CAN_F10R2_FB17_Pos     (17U)                                           
+#define CAN_F10R2_FB17_Msk     (0x1UL << CAN_F10R2_FB17_Pos)                    /*!< 0x00020000 */
+#define CAN_F10R2_FB17         CAN_F10R2_FB17_Msk                              /*!<Filter bit 17 */
+#define CAN_F10R2_FB18_Pos     (18U)                                           
+#define CAN_F10R2_FB18_Msk     (0x1UL << CAN_F10R2_FB18_Pos)                    /*!< 0x00040000 */
+#define CAN_F10R2_FB18         CAN_F10R2_FB18_Msk                              /*!<Filter bit 18 */
+#define CAN_F10R2_FB19_Pos     (19U)                                           
+#define CAN_F10R2_FB19_Msk     (0x1UL << CAN_F10R2_FB19_Pos)                    /*!< 0x00080000 */
+#define CAN_F10R2_FB19         CAN_F10R2_FB19_Msk                              /*!<Filter bit 19 */
+#define CAN_F10R2_FB20_Pos     (20U)                                           
+#define CAN_F10R2_FB20_Msk     (0x1UL << CAN_F10R2_FB20_Pos)                    /*!< 0x00100000 */
+#define CAN_F10R2_FB20         CAN_F10R2_FB20_Msk                              /*!<Filter bit 20 */
+#define CAN_F10R2_FB21_Pos     (21U)                                           
+#define CAN_F10R2_FB21_Msk     (0x1UL << CAN_F10R2_FB21_Pos)                    /*!< 0x00200000 */
+#define CAN_F10R2_FB21         CAN_F10R2_FB21_Msk                              /*!<Filter bit 21 */
+#define CAN_F10R2_FB22_Pos     (22U)                                           
+#define CAN_F10R2_FB22_Msk     (0x1UL << CAN_F10R2_FB22_Pos)                    /*!< 0x00400000 */
+#define CAN_F10R2_FB22         CAN_F10R2_FB22_Msk                              /*!<Filter bit 22 */
+#define CAN_F10R2_FB23_Pos     (23U)                                           
+#define CAN_F10R2_FB23_Msk     (0x1UL << CAN_F10R2_FB23_Pos)                    /*!< 0x00800000 */
+#define CAN_F10R2_FB23         CAN_F10R2_FB23_Msk                              /*!<Filter bit 23 */
+#define CAN_F10R2_FB24_Pos     (24U)                                           
+#define CAN_F10R2_FB24_Msk     (0x1UL << CAN_F10R2_FB24_Pos)                    /*!< 0x01000000 */
+#define CAN_F10R2_FB24         CAN_F10R2_FB24_Msk                              /*!<Filter bit 24 */
+#define CAN_F10R2_FB25_Pos     (25U)                                           
+#define CAN_F10R2_FB25_Msk     (0x1UL << CAN_F10R2_FB25_Pos)                    /*!< 0x02000000 */
+#define CAN_F10R2_FB25         CAN_F10R2_FB25_Msk                              /*!<Filter bit 25 */
+#define CAN_F10R2_FB26_Pos     (26U)                                           
+#define CAN_F10R2_FB26_Msk     (0x1UL << CAN_F10R2_FB26_Pos)                    /*!< 0x04000000 */
+#define CAN_F10R2_FB26         CAN_F10R2_FB26_Msk                              /*!<Filter bit 26 */
+#define CAN_F10R2_FB27_Pos     (27U)                                           
+#define CAN_F10R2_FB27_Msk     (0x1UL << CAN_F10R2_FB27_Pos)                    /*!< 0x08000000 */
+#define CAN_F10R2_FB27         CAN_F10R2_FB27_Msk                              /*!<Filter bit 27 */
+#define CAN_F10R2_FB28_Pos     (28U)                                           
+#define CAN_F10R2_FB28_Msk     (0x1UL << CAN_F10R2_FB28_Pos)                    /*!< 0x10000000 */
+#define CAN_F10R2_FB28         CAN_F10R2_FB28_Msk                              /*!<Filter bit 28 */
+#define CAN_F10R2_FB29_Pos     (29U)                                           
+#define CAN_F10R2_FB29_Msk     (0x1UL << CAN_F10R2_FB29_Pos)                    /*!< 0x20000000 */
+#define CAN_F10R2_FB29         CAN_F10R2_FB29_Msk                              /*!<Filter bit 29 */
+#define CAN_F10R2_FB30_Pos     (30U)                                           
+#define CAN_F10R2_FB30_Msk     (0x1UL << CAN_F10R2_FB30_Pos)                    /*!< 0x40000000 */
+#define CAN_F10R2_FB30         CAN_F10R2_FB30_Msk                              /*!<Filter bit 30 */
+#define CAN_F10R2_FB31_Pos     (31U)                                           
+#define CAN_F10R2_FB31_Msk     (0x1UL << CAN_F10R2_FB31_Pos)                    /*!< 0x80000000 */
+#define CAN_F10R2_FB31         CAN_F10R2_FB31_Msk                              /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F11R2 register  ******************/
+#define CAN_F11R2_FB0_Pos      (0U)                                            
+#define CAN_F11R2_FB0_Msk      (0x1UL << CAN_F11R2_FB0_Pos)                     /*!< 0x00000001 */
+#define CAN_F11R2_FB0          CAN_F11R2_FB0_Msk                               /*!<Filter bit 0 */
+#define CAN_F11R2_FB1_Pos      (1U)                                            
+#define CAN_F11R2_FB1_Msk      (0x1UL << CAN_F11R2_FB1_Pos)                     /*!< 0x00000002 */
+#define CAN_F11R2_FB1          CAN_F11R2_FB1_Msk                               /*!<Filter bit 1 */
+#define CAN_F11R2_FB2_Pos      (2U)                                            
+#define CAN_F11R2_FB2_Msk      (0x1UL << CAN_F11R2_FB2_Pos)                     /*!< 0x00000004 */
+#define CAN_F11R2_FB2          CAN_F11R2_FB2_Msk                               /*!<Filter bit 2 */
+#define CAN_F11R2_FB3_Pos      (3U)                                            
+#define CAN_F11R2_FB3_Msk      (0x1UL << CAN_F11R2_FB3_Pos)                     /*!< 0x00000008 */
+#define CAN_F11R2_FB3          CAN_F11R2_FB3_Msk                               /*!<Filter bit 3 */
+#define CAN_F11R2_FB4_Pos      (4U)                                            
+#define CAN_F11R2_FB4_Msk      (0x1UL << CAN_F11R2_FB4_Pos)                     /*!< 0x00000010 */
+#define CAN_F11R2_FB4          CAN_F11R2_FB4_Msk                               /*!<Filter bit 4 */
+#define CAN_F11R2_FB5_Pos      (5U)                                            
+#define CAN_F11R2_FB5_Msk      (0x1UL << CAN_F11R2_FB5_Pos)                     /*!< 0x00000020 */
+#define CAN_F11R2_FB5          CAN_F11R2_FB5_Msk                               /*!<Filter bit 5 */
+#define CAN_F11R2_FB6_Pos      (6U)                                            
+#define CAN_F11R2_FB6_Msk      (0x1UL << CAN_F11R2_FB6_Pos)                     /*!< 0x00000040 */
+#define CAN_F11R2_FB6          CAN_F11R2_FB6_Msk                               /*!<Filter bit 6 */
+#define CAN_F11R2_FB7_Pos      (7U)                                            
+#define CAN_F11R2_FB7_Msk      (0x1UL << CAN_F11R2_FB7_Pos)                     /*!< 0x00000080 */
+#define CAN_F11R2_FB7          CAN_F11R2_FB7_Msk                               /*!<Filter bit 7 */
+#define CAN_F11R2_FB8_Pos      (8U)                                            
+#define CAN_F11R2_FB8_Msk      (0x1UL << CAN_F11R2_FB8_Pos)                     /*!< 0x00000100 */
+#define CAN_F11R2_FB8          CAN_F11R2_FB8_Msk                               /*!<Filter bit 8 */
+#define CAN_F11R2_FB9_Pos      (9U)                                            
+#define CAN_F11R2_FB9_Msk      (0x1UL << CAN_F11R2_FB9_Pos)                     /*!< 0x00000200 */
+#define CAN_F11R2_FB9          CAN_F11R2_FB9_Msk                               /*!<Filter bit 9 */
+#define CAN_F11R2_FB10_Pos     (10U)                                           
+#define CAN_F11R2_FB10_Msk     (0x1UL << CAN_F11R2_FB10_Pos)                    /*!< 0x00000400 */
+#define CAN_F11R2_FB10         CAN_F11R2_FB10_Msk                              /*!<Filter bit 10 */
+#define CAN_F11R2_FB11_Pos     (11U)                                           
+#define CAN_F11R2_FB11_Msk     (0x1UL << CAN_F11R2_FB11_Pos)                    /*!< 0x00000800 */
+#define CAN_F11R2_FB11         CAN_F11R2_FB11_Msk                              /*!<Filter bit 11 */
+#define CAN_F11R2_FB12_Pos     (12U)                                           
+#define CAN_F11R2_FB12_Msk     (0x1UL << CAN_F11R2_FB12_Pos)                    /*!< 0x00001000 */
+#define CAN_F11R2_FB12         CAN_F11R2_FB12_Msk                              /*!<Filter bit 12 */
+#define CAN_F11R2_FB13_Pos     (13U)                                           
+#define CAN_F11R2_FB13_Msk     (0x1UL << CAN_F11R2_FB13_Pos)                    /*!< 0x00002000 */
+#define CAN_F11R2_FB13         CAN_F11R2_FB13_Msk                              /*!<Filter bit 13 */
+#define CAN_F11R2_FB14_Pos     (14U)                                           
+#define CAN_F11R2_FB14_Msk     (0x1UL << CAN_F11R2_FB14_Pos)                    /*!< 0x00004000 */
+#define CAN_F11R2_FB14         CAN_F11R2_FB14_Msk                              /*!<Filter bit 14 */
+#define CAN_F11R2_FB15_Pos     (15U)                                           
+#define CAN_F11R2_FB15_Msk     (0x1UL << CAN_F11R2_FB15_Pos)                    /*!< 0x00008000 */
+#define CAN_F11R2_FB15         CAN_F11R2_FB15_Msk                              /*!<Filter bit 15 */
+#define CAN_F11R2_FB16_Pos     (16U)                                           
+#define CAN_F11R2_FB16_Msk     (0x1UL << CAN_F11R2_FB16_Pos)                    /*!< 0x00010000 */
+#define CAN_F11R2_FB16         CAN_F11R2_FB16_Msk                              /*!<Filter bit 16 */
+#define CAN_F11R2_FB17_Pos     (17U)                                           
+#define CAN_F11R2_FB17_Msk     (0x1UL << CAN_F11R2_FB17_Pos)                    /*!< 0x00020000 */
+#define CAN_F11R2_FB17         CAN_F11R2_FB17_Msk                              /*!<Filter bit 17 */
+#define CAN_F11R2_FB18_Pos     (18U)                                           
+#define CAN_F11R2_FB18_Msk     (0x1UL << CAN_F11R2_FB18_Pos)                    /*!< 0x00040000 */
+#define CAN_F11R2_FB18         CAN_F11R2_FB18_Msk                              /*!<Filter bit 18 */
+#define CAN_F11R2_FB19_Pos     (19U)                                           
+#define CAN_F11R2_FB19_Msk     (0x1UL << CAN_F11R2_FB19_Pos)                    /*!< 0x00080000 */
+#define CAN_F11R2_FB19         CAN_F11R2_FB19_Msk                              /*!<Filter bit 19 */
+#define CAN_F11R2_FB20_Pos     (20U)                                           
+#define CAN_F11R2_FB20_Msk     (0x1UL << CAN_F11R2_FB20_Pos)                    /*!< 0x00100000 */
+#define CAN_F11R2_FB20         CAN_F11R2_FB20_Msk                              /*!<Filter bit 20 */
+#define CAN_F11R2_FB21_Pos     (21U)                                           
+#define CAN_F11R2_FB21_Msk     (0x1UL << CAN_F11R2_FB21_Pos)                    /*!< 0x00200000 */
+#define CAN_F11R2_FB21         CAN_F11R2_FB21_Msk                              /*!<Filter bit 21 */
+#define CAN_F11R2_FB22_Pos     (22U)                                           
+#define CAN_F11R2_FB22_Msk     (0x1UL << CAN_F11R2_FB22_Pos)                    /*!< 0x00400000 */
+#define CAN_F11R2_FB22         CAN_F11R2_FB22_Msk                              /*!<Filter bit 22 */
+#define CAN_F11R2_FB23_Pos     (23U)                                           
+#define CAN_F11R2_FB23_Msk     (0x1UL << CAN_F11R2_FB23_Pos)                    /*!< 0x00800000 */
+#define CAN_F11R2_FB23         CAN_F11R2_FB23_Msk                              /*!<Filter bit 23 */
+#define CAN_F11R2_FB24_Pos     (24U)                                           
+#define CAN_F11R2_FB24_Msk     (0x1UL << CAN_F11R2_FB24_Pos)                    /*!< 0x01000000 */
+#define CAN_F11R2_FB24         CAN_F11R2_FB24_Msk                              /*!<Filter bit 24 */
+#define CAN_F11R2_FB25_Pos     (25U)                                           
+#define CAN_F11R2_FB25_Msk     (0x1UL << CAN_F11R2_FB25_Pos)                    /*!< 0x02000000 */
+#define CAN_F11R2_FB25         CAN_F11R2_FB25_Msk                              /*!<Filter bit 25 */
+#define CAN_F11R2_FB26_Pos     (26U)                                           
+#define CAN_F11R2_FB26_Msk     (0x1UL << CAN_F11R2_FB26_Pos)                    /*!< 0x04000000 */
+#define CAN_F11R2_FB26         CAN_F11R2_FB26_Msk                              /*!<Filter bit 26 */
+#define CAN_F11R2_FB27_Pos     (27U)                                           
+#define CAN_F11R2_FB27_Msk     (0x1UL << CAN_F11R2_FB27_Pos)                    /*!< 0x08000000 */
+#define CAN_F11R2_FB27         CAN_F11R2_FB27_Msk                              /*!<Filter bit 27 */
+#define CAN_F11R2_FB28_Pos     (28U)                                           
+#define CAN_F11R2_FB28_Msk     (0x1UL << CAN_F11R2_FB28_Pos)                    /*!< 0x10000000 */
+#define CAN_F11R2_FB28         CAN_F11R2_FB28_Msk                              /*!<Filter bit 28 */
+#define CAN_F11R2_FB29_Pos     (29U)                                           
+#define CAN_F11R2_FB29_Msk     (0x1UL << CAN_F11R2_FB29_Pos)                    /*!< 0x20000000 */
+#define CAN_F11R2_FB29         CAN_F11R2_FB29_Msk                              /*!<Filter bit 29 */
+#define CAN_F11R2_FB30_Pos     (30U)                                           
+#define CAN_F11R2_FB30_Msk     (0x1UL << CAN_F11R2_FB30_Pos)                    /*!< 0x40000000 */
+#define CAN_F11R2_FB30         CAN_F11R2_FB30_Msk                              /*!<Filter bit 30 */
+#define CAN_F11R2_FB31_Pos     (31U)                                           
+#define CAN_F11R2_FB31_Msk     (0x1UL << CAN_F11R2_FB31_Pos)                    /*!< 0x80000000 */
+#define CAN_F11R2_FB31         CAN_F11R2_FB31_Msk                              /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F12R2 register  ******************/
+#define CAN_F12R2_FB0_Pos      (0U)                                            
+#define CAN_F12R2_FB0_Msk      (0x1UL << CAN_F12R2_FB0_Pos)                     /*!< 0x00000001 */
+#define CAN_F12R2_FB0          CAN_F12R2_FB0_Msk                               /*!<Filter bit 0 */
+#define CAN_F12R2_FB1_Pos      (1U)                                            
+#define CAN_F12R2_FB1_Msk      (0x1UL << CAN_F12R2_FB1_Pos)                     /*!< 0x00000002 */
+#define CAN_F12R2_FB1          CAN_F12R2_FB1_Msk                               /*!<Filter bit 1 */
+#define CAN_F12R2_FB2_Pos      (2U)                                            
+#define CAN_F12R2_FB2_Msk      (0x1UL << CAN_F12R2_FB2_Pos)                     /*!< 0x00000004 */
+#define CAN_F12R2_FB2          CAN_F12R2_FB2_Msk                               /*!<Filter bit 2 */
+#define CAN_F12R2_FB3_Pos      (3U)                                            
+#define CAN_F12R2_FB3_Msk      (0x1UL << CAN_F12R2_FB3_Pos)                     /*!< 0x00000008 */
+#define CAN_F12R2_FB3          CAN_F12R2_FB3_Msk                               /*!<Filter bit 3 */
+#define CAN_F12R2_FB4_Pos      (4U)                                            
+#define CAN_F12R2_FB4_Msk      (0x1UL << CAN_F12R2_FB4_Pos)                     /*!< 0x00000010 */
+#define CAN_F12R2_FB4          CAN_F12R2_FB4_Msk                               /*!<Filter bit 4 */
+#define CAN_F12R2_FB5_Pos      (5U)                                            
+#define CAN_F12R2_FB5_Msk      (0x1UL << CAN_F12R2_FB5_Pos)                     /*!< 0x00000020 */
+#define CAN_F12R2_FB5          CAN_F12R2_FB5_Msk                               /*!<Filter bit 5 */
+#define CAN_F12R2_FB6_Pos      (6U)                                            
+#define CAN_F12R2_FB6_Msk      (0x1UL << CAN_F12R2_FB6_Pos)                     /*!< 0x00000040 */
+#define CAN_F12R2_FB6          CAN_F12R2_FB6_Msk                               /*!<Filter bit 6 */
+#define CAN_F12R2_FB7_Pos      (7U)                                            
+#define CAN_F12R2_FB7_Msk      (0x1UL << CAN_F12R2_FB7_Pos)                     /*!< 0x00000080 */
+#define CAN_F12R2_FB7          CAN_F12R2_FB7_Msk                               /*!<Filter bit 7 */
+#define CAN_F12R2_FB8_Pos      (8U)                                            
+#define CAN_F12R2_FB8_Msk      (0x1UL << CAN_F12R2_FB8_Pos)                     /*!< 0x00000100 */
+#define CAN_F12R2_FB8          CAN_F12R2_FB8_Msk                               /*!<Filter bit 8 */
+#define CAN_F12R2_FB9_Pos      (9U)                                            
+#define CAN_F12R2_FB9_Msk      (0x1UL << CAN_F12R2_FB9_Pos)                     /*!< 0x00000200 */
+#define CAN_F12R2_FB9          CAN_F12R2_FB9_Msk                               /*!<Filter bit 9 */
+#define CAN_F12R2_FB10_Pos     (10U)                                           
+#define CAN_F12R2_FB10_Msk     (0x1UL << CAN_F12R2_FB10_Pos)                    /*!< 0x00000400 */
+#define CAN_F12R2_FB10         CAN_F12R2_FB10_Msk                              /*!<Filter bit 10 */
+#define CAN_F12R2_FB11_Pos     (11U)                                           
+#define CAN_F12R2_FB11_Msk     (0x1UL << CAN_F12R2_FB11_Pos)                    /*!< 0x00000800 */
+#define CAN_F12R2_FB11         CAN_F12R2_FB11_Msk                              /*!<Filter bit 11 */
+#define CAN_F12R2_FB12_Pos     (12U)                                           
+#define CAN_F12R2_FB12_Msk     (0x1UL << CAN_F12R2_FB12_Pos)                    /*!< 0x00001000 */
+#define CAN_F12R2_FB12         CAN_F12R2_FB12_Msk                              /*!<Filter bit 12 */
+#define CAN_F12R2_FB13_Pos     (13U)                                           
+#define CAN_F12R2_FB13_Msk     (0x1UL << CAN_F12R2_FB13_Pos)                    /*!< 0x00002000 */
+#define CAN_F12R2_FB13         CAN_F12R2_FB13_Msk                              /*!<Filter bit 13 */
+#define CAN_F12R2_FB14_Pos     (14U)                                           
+#define CAN_F12R2_FB14_Msk     (0x1UL << CAN_F12R2_FB14_Pos)                    /*!< 0x00004000 */
+#define CAN_F12R2_FB14         CAN_F12R2_FB14_Msk                              /*!<Filter bit 14 */
+#define CAN_F12R2_FB15_Pos     (15U)                                           
+#define CAN_F12R2_FB15_Msk     (0x1UL << CAN_F12R2_FB15_Pos)                    /*!< 0x00008000 */
+#define CAN_F12R2_FB15         CAN_F12R2_FB15_Msk                              /*!<Filter bit 15 */
+#define CAN_F12R2_FB16_Pos     (16U)                                           
+#define CAN_F12R2_FB16_Msk     (0x1UL << CAN_F12R2_FB16_Pos)                    /*!< 0x00010000 */
+#define CAN_F12R2_FB16         CAN_F12R2_FB16_Msk                              /*!<Filter bit 16 */
+#define CAN_F12R2_FB17_Pos     (17U)                                           
+#define CAN_F12R2_FB17_Msk     (0x1UL << CAN_F12R2_FB17_Pos)                    /*!< 0x00020000 */
+#define CAN_F12R2_FB17         CAN_F12R2_FB17_Msk                              /*!<Filter bit 17 */
+#define CAN_F12R2_FB18_Pos     (18U)                                           
+#define CAN_F12R2_FB18_Msk     (0x1UL << CAN_F12R2_FB18_Pos)                    /*!< 0x00040000 */
+#define CAN_F12R2_FB18         CAN_F12R2_FB18_Msk                              /*!<Filter bit 18 */
+#define CAN_F12R2_FB19_Pos     (19U)                                           
+#define CAN_F12R2_FB19_Msk     (0x1UL << CAN_F12R2_FB19_Pos)                    /*!< 0x00080000 */
+#define CAN_F12R2_FB19         CAN_F12R2_FB19_Msk                              /*!<Filter bit 19 */
+#define CAN_F12R2_FB20_Pos     (20U)                                           
+#define CAN_F12R2_FB20_Msk     (0x1UL << CAN_F12R2_FB20_Pos)                    /*!< 0x00100000 */
+#define CAN_F12R2_FB20         CAN_F12R2_FB20_Msk                              /*!<Filter bit 20 */
+#define CAN_F12R2_FB21_Pos     (21U)                                           
+#define CAN_F12R2_FB21_Msk     (0x1UL << CAN_F12R2_FB21_Pos)                    /*!< 0x00200000 */
+#define CAN_F12R2_FB21         CAN_F12R2_FB21_Msk                              /*!<Filter bit 21 */
+#define CAN_F12R2_FB22_Pos     (22U)                                           
+#define CAN_F12R2_FB22_Msk     (0x1UL << CAN_F12R2_FB22_Pos)                    /*!< 0x00400000 */
+#define CAN_F12R2_FB22         CAN_F12R2_FB22_Msk                              /*!<Filter bit 22 */
+#define CAN_F12R2_FB23_Pos     (23U)                                           
+#define CAN_F12R2_FB23_Msk     (0x1UL << CAN_F12R2_FB23_Pos)                    /*!< 0x00800000 */
+#define CAN_F12R2_FB23         CAN_F12R2_FB23_Msk                              /*!<Filter bit 23 */
+#define CAN_F12R2_FB24_Pos     (24U)                                           
+#define CAN_F12R2_FB24_Msk     (0x1UL << CAN_F12R2_FB24_Pos)                    /*!< 0x01000000 */
+#define CAN_F12R2_FB24         CAN_F12R2_FB24_Msk                              /*!<Filter bit 24 */
+#define CAN_F12R2_FB25_Pos     (25U)                                           
+#define CAN_F12R2_FB25_Msk     (0x1UL << CAN_F12R2_FB25_Pos)                    /*!< 0x02000000 */
+#define CAN_F12R2_FB25         CAN_F12R2_FB25_Msk                              /*!<Filter bit 25 */
+#define CAN_F12R2_FB26_Pos     (26U)                                           
+#define CAN_F12R2_FB26_Msk     (0x1UL << CAN_F12R2_FB26_Pos)                    /*!< 0x04000000 */
+#define CAN_F12R2_FB26         CAN_F12R2_FB26_Msk                              /*!<Filter bit 26 */
+#define CAN_F12R2_FB27_Pos     (27U)                                           
+#define CAN_F12R2_FB27_Msk     (0x1UL << CAN_F12R2_FB27_Pos)                    /*!< 0x08000000 */
+#define CAN_F12R2_FB27         CAN_F12R2_FB27_Msk                              /*!<Filter bit 27 */
+#define CAN_F12R2_FB28_Pos     (28U)                                           
+#define CAN_F12R2_FB28_Msk     (0x1UL << CAN_F12R2_FB28_Pos)                    /*!< 0x10000000 */
+#define CAN_F12R2_FB28         CAN_F12R2_FB28_Msk                              /*!<Filter bit 28 */
+#define CAN_F12R2_FB29_Pos     (29U)                                           
+#define CAN_F12R2_FB29_Msk     (0x1UL << CAN_F12R2_FB29_Pos)                    /*!< 0x20000000 */
+#define CAN_F12R2_FB29         CAN_F12R2_FB29_Msk                              /*!<Filter bit 29 */
+#define CAN_F12R2_FB30_Pos     (30U)                                           
+#define CAN_F12R2_FB30_Msk     (0x1UL << CAN_F12R2_FB30_Pos)                    /*!< 0x40000000 */
+#define CAN_F12R2_FB30         CAN_F12R2_FB30_Msk                              /*!<Filter bit 30 */
+#define CAN_F12R2_FB31_Pos     (31U)                                           
+#define CAN_F12R2_FB31_Msk     (0x1UL << CAN_F12R2_FB31_Pos)                    /*!< 0x80000000 */
+#define CAN_F12R2_FB31         CAN_F12R2_FB31_Msk                              /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F13R2 register  ******************/
+#define CAN_F13R2_FB0_Pos      (0U)                                            
+#define CAN_F13R2_FB0_Msk      (0x1UL << CAN_F13R2_FB0_Pos)                     /*!< 0x00000001 */
+#define CAN_F13R2_FB0          CAN_F13R2_FB0_Msk                               /*!<Filter bit 0 */
+#define CAN_F13R2_FB1_Pos      (1U)                                            
+#define CAN_F13R2_FB1_Msk      (0x1UL << CAN_F13R2_FB1_Pos)                     /*!< 0x00000002 */
+#define CAN_F13R2_FB1          CAN_F13R2_FB1_Msk                               /*!<Filter bit 1 */
+#define CAN_F13R2_FB2_Pos      (2U)                                            
+#define CAN_F13R2_FB2_Msk      (0x1UL << CAN_F13R2_FB2_Pos)                     /*!< 0x00000004 */
+#define CAN_F13R2_FB2          CAN_F13R2_FB2_Msk                               /*!<Filter bit 2 */
+#define CAN_F13R2_FB3_Pos      (3U)                                            
+#define CAN_F13R2_FB3_Msk      (0x1UL << CAN_F13R2_FB3_Pos)                     /*!< 0x00000008 */
+#define CAN_F13R2_FB3          CAN_F13R2_FB3_Msk                               /*!<Filter bit 3 */
+#define CAN_F13R2_FB4_Pos      (4U)                                            
+#define CAN_F13R2_FB4_Msk      (0x1UL << CAN_F13R2_FB4_Pos)                     /*!< 0x00000010 */
+#define CAN_F13R2_FB4          CAN_F13R2_FB4_Msk                               /*!<Filter bit 4 */
+#define CAN_F13R2_FB5_Pos      (5U)                                            
+#define CAN_F13R2_FB5_Msk      (0x1UL << CAN_F13R2_FB5_Pos)                     /*!< 0x00000020 */
+#define CAN_F13R2_FB5          CAN_F13R2_FB5_Msk                               /*!<Filter bit 5 */
+#define CAN_F13R2_FB6_Pos      (6U)                                            
+#define CAN_F13R2_FB6_Msk      (0x1UL << CAN_F13R2_FB6_Pos)                     /*!< 0x00000040 */
+#define CAN_F13R2_FB6          CAN_F13R2_FB6_Msk                               /*!<Filter bit 6 */
+#define CAN_F13R2_FB7_Pos      (7U)                                            
+#define CAN_F13R2_FB7_Msk      (0x1UL << CAN_F13R2_FB7_Pos)                     /*!< 0x00000080 */
+#define CAN_F13R2_FB7          CAN_F13R2_FB7_Msk                               /*!<Filter bit 7 */
+#define CAN_F13R2_FB8_Pos      (8U)                                            
+#define CAN_F13R2_FB8_Msk      (0x1UL << CAN_F13R2_FB8_Pos)                     /*!< 0x00000100 */
+#define CAN_F13R2_FB8          CAN_F13R2_FB8_Msk                               /*!<Filter bit 8 */
+#define CAN_F13R2_FB9_Pos      (9U)                                            
+#define CAN_F13R2_FB9_Msk      (0x1UL << CAN_F13R2_FB9_Pos)                     /*!< 0x00000200 */
+#define CAN_F13R2_FB9          CAN_F13R2_FB9_Msk                               /*!<Filter bit 9 */
+#define CAN_F13R2_FB10_Pos     (10U)                                           
+#define CAN_F13R2_FB10_Msk     (0x1UL << CAN_F13R2_FB10_Pos)                    /*!< 0x00000400 */
+#define CAN_F13R2_FB10         CAN_F13R2_FB10_Msk                              /*!<Filter bit 10 */
+#define CAN_F13R2_FB11_Pos     (11U)                                           
+#define CAN_F13R2_FB11_Msk     (0x1UL << CAN_F13R2_FB11_Pos)                    /*!< 0x00000800 */
+#define CAN_F13R2_FB11         CAN_F13R2_FB11_Msk                              /*!<Filter bit 11 */
+#define CAN_F13R2_FB12_Pos     (12U)                                           
+#define CAN_F13R2_FB12_Msk     (0x1UL << CAN_F13R2_FB12_Pos)                    /*!< 0x00001000 */
+#define CAN_F13R2_FB12         CAN_F13R2_FB12_Msk                              /*!<Filter bit 12 */
+#define CAN_F13R2_FB13_Pos     (13U)                                           
+#define CAN_F13R2_FB13_Msk     (0x1UL << CAN_F13R2_FB13_Pos)                    /*!< 0x00002000 */
+#define CAN_F13R2_FB13         CAN_F13R2_FB13_Msk                              /*!<Filter bit 13 */
+#define CAN_F13R2_FB14_Pos     (14U)                                           
+#define CAN_F13R2_FB14_Msk     (0x1UL << CAN_F13R2_FB14_Pos)                    /*!< 0x00004000 */
+#define CAN_F13R2_FB14         CAN_F13R2_FB14_Msk                              /*!<Filter bit 14 */
+#define CAN_F13R2_FB15_Pos     (15U)                                           
+#define CAN_F13R2_FB15_Msk     (0x1UL << CAN_F13R2_FB15_Pos)                    /*!< 0x00008000 */
+#define CAN_F13R2_FB15         CAN_F13R2_FB15_Msk                              /*!<Filter bit 15 */
+#define CAN_F13R2_FB16_Pos     (16U)                                           
+#define CAN_F13R2_FB16_Msk     (0x1UL << CAN_F13R2_FB16_Pos)                    /*!< 0x00010000 */
+#define CAN_F13R2_FB16         CAN_F13R2_FB16_Msk                              /*!<Filter bit 16 */
+#define CAN_F13R2_FB17_Pos     (17U)                                           
+#define CAN_F13R2_FB17_Msk     (0x1UL << CAN_F13R2_FB17_Pos)                    /*!< 0x00020000 */
+#define CAN_F13R2_FB17         CAN_F13R2_FB17_Msk                              /*!<Filter bit 17 */
+#define CAN_F13R2_FB18_Pos     (18U)                                           
+#define CAN_F13R2_FB18_Msk     (0x1UL << CAN_F13R2_FB18_Pos)                    /*!< 0x00040000 */
+#define CAN_F13R2_FB18         CAN_F13R2_FB18_Msk                              /*!<Filter bit 18 */
+#define CAN_F13R2_FB19_Pos     (19U)                                           
+#define CAN_F13R2_FB19_Msk     (0x1UL << CAN_F13R2_FB19_Pos)                    /*!< 0x00080000 */
+#define CAN_F13R2_FB19         CAN_F13R2_FB19_Msk                              /*!<Filter bit 19 */
+#define CAN_F13R2_FB20_Pos     (20U)                                           
+#define CAN_F13R2_FB20_Msk     (0x1UL << CAN_F13R2_FB20_Pos)                    /*!< 0x00100000 */
+#define CAN_F13R2_FB20         CAN_F13R2_FB20_Msk                              /*!<Filter bit 20 */
+#define CAN_F13R2_FB21_Pos     (21U)                                           
+#define CAN_F13R2_FB21_Msk     (0x1UL << CAN_F13R2_FB21_Pos)                    /*!< 0x00200000 */
+#define CAN_F13R2_FB21         CAN_F13R2_FB21_Msk                              /*!<Filter bit 21 */
+#define CAN_F13R2_FB22_Pos     (22U)                                           
+#define CAN_F13R2_FB22_Msk     (0x1UL << CAN_F13R2_FB22_Pos)                    /*!< 0x00400000 */
+#define CAN_F13R2_FB22         CAN_F13R2_FB22_Msk                              /*!<Filter bit 22 */
+#define CAN_F13R2_FB23_Pos     (23U)                                           
+#define CAN_F13R2_FB23_Msk     (0x1UL << CAN_F13R2_FB23_Pos)                    /*!< 0x00800000 */
+#define CAN_F13R2_FB23         CAN_F13R2_FB23_Msk                              /*!<Filter bit 23 */
+#define CAN_F13R2_FB24_Pos     (24U)                                           
+#define CAN_F13R2_FB24_Msk     (0x1UL << CAN_F13R2_FB24_Pos)                    /*!< 0x01000000 */
+#define CAN_F13R2_FB24         CAN_F13R2_FB24_Msk                              /*!<Filter bit 24 */
+#define CAN_F13R2_FB25_Pos     (25U)                                           
+#define CAN_F13R2_FB25_Msk     (0x1UL << CAN_F13R2_FB25_Pos)                    /*!< 0x02000000 */
+#define CAN_F13R2_FB25         CAN_F13R2_FB25_Msk                              /*!<Filter bit 25 */
+#define CAN_F13R2_FB26_Pos     (26U)                                           
+#define CAN_F13R2_FB26_Msk     (0x1UL << CAN_F13R2_FB26_Pos)                    /*!< 0x04000000 */
+#define CAN_F13R2_FB26         CAN_F13R2_FB26_Msk                              /*!<Filter bit 26 */
+#define CAN_F13R2_FB27_Pos     (27U)                                           
+#define CAN_F13R2_FB27_Msk     (0x1UL << CAN_F13R2_FB27_Pos)                    /*!< 0x08000000 */
+#define CAN_F13R2_FB27         CAN_F13R2_FB27_Msk                              /*!<Filter bit 27 */
+#define CAN_F13R2_FB28_Pos     (28U)                                           
+#define CAN_F13R2_FB28_Msk     (0x1UL << CAN_F13R2_FB28_Pos)                    /*!< 0x10000000 */
+#define CAN_F13R2_FB28         CAN_F13R2_FB28_Msk                              /*!<Filter bit 28 */
+#define CAN_F13R2_FB29_Pos     (29U)                                           
+#define CAN_F13R2_FB29_Msk     (0x1UL << CAN_F13R2_FB29_Pos)                    /*!< 0x20000000 */
+#define CAN_F13R2_FB29         CAN_F13R2_FB29_Msk                              /*!<Filter bit 29 */
+#define CAN_F13R2_FB30_Pos     (30U)                                           
+#define CAN_F13R2_FB30_Msk     (0x1UL << CAN_F13R2_FB30_Pos)                    /*!< 0x40000000 */
+#define CAN_F13R2_FB30         CAN_F13R2_FB30_Msk                              /*!<Filter bit 30 */
+#define CAN_F13R2_FB31_Pos     (31U)                                           
+#define CAN_F13R2_FB31_Msk     (0x1UL << CAN_F13R2_FB31_Pos)                    /*!< 0x80000000 */
+#define CAN_F13R2_FB31         CAN_F13R2_FB31_Msk                              /*!<Filter bit 31 */
+
+/******************************************************************************/
+/*                                                                            */
+/*                          CRC calculation unit                              */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for CRC_DR register  *********************/
+#define CRC_DR_DR_Pos       (0U)                                               
+#define CRC_DR_DR_Msk       (0xFFFFFFFFUL << CRC_DR_DR_Pos)                     /*!< 0xFFFFFFFF */
+#define CRC_DR_DR           CRC_DR_DR_Msk                                      /*!< Data register bits */
+
+
+/*******************  Bit definition for CRC_IDR register  ********************/
+#define CRC_IDR_IDR_Pos     (0U)                                               
+#define CRC_IDR_IDR_Msk     (0xFFUL << CRC_IDR_IDR_Pos)                         /*!< 0x000000FF */
+#define CRC_IDR_IDR         CRC_IDR_IDR_Msk                                    /*!< General-purpose 8-bit data register bits */
+
+
+/********************  Bit definition for CRC_CR register  ********************/
+#define CRC_CR_RESET_Pos    (0U)                                               
+#define CRC_CR_RESET_Msk    (0x1UL << CRC_CR_RESET_Pos)                         /*!< 0x00000001 */
+#define CRC_CR_RESET        CRC_CR_RESET_Msk                                   /*!< RESET bit */
+
+/******************************************************************************/
+/*                                                                            */
+/*                      Digital to Analog Converter                           */
+/*                                                                            */
+/******************************************************************************/
+/*
+ * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
+ */
+#define DAC_CHANNEL2_SUPPORT                                    /*!< DAC feature available only on specific devices: availability of DAC channel 2 */
+/********************  Bit definition for DAC_CR register  ********************/
+#define DAC_CR_EN1_Pos              (0U)                                       
+#define DAC_CR_EN1_Msk              (0x1UL << DAC_CR_EN1_Pos)                   /*!< 0x00000001 */
+#define DAC_CR_EN1                  DAC_CR_EN1_Msk                             /*!<DAC channel1 enable */
+#define DAC_CR_BOFF1_Pos            (1U)                                       
+#define DAC_CR_BOFF1_Msk            (0x1UL << DAC_CR_BOFF1_Pos)                 /*!< 0x00000002 */
+#define DAC_CR_BOFF1                DAC_CR_BOFF1_Msk                           /*!<DAC channel1 output buffer disable */
+#define DAC_CR_TEN1_Pos             (2U)                                       
+#define DAC_CR_TEN1_Msk             (0x1UL << DAC_CR_TEN1_Pos)                  /*!< 0x00000004 */
+#define DAC_CR_TEN1                 DAC_CR_TEN1_Msk                            /*!<DAC channel1 Trigger enable */
+
+#define DAC_CR_TSEL1_Pos            (3U)                                       
+#define DAC_CR_TSEL1_Msk            (0x7UL << DAC_CR_TSEL1_Pos)                 /*!< 0x00000038 */
+#define DAC_CR_TSEL1                DAC_CR_TSEL1_Msk                           /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
+#define DAC_CR_TSEL1_0              (0x1UL << DAC_CR_TSEL1_Pos)                 /*!< 0x00000008 */
+#define DAC_CR_TSEL1_1              (0x2UL << DAC_CR_TSEL1_Pos)                 /*!< 0x00000010 */
+#define DAC_CR_TSEL1_2              (0x4UL << DAC_CR_TSEL1_Pos)                 /*!< 0x00000020 */
+
+#define DAC_CR_WAVE1_Pos            (6U)                                       
+#define DAC_CR_WAVE1_Msk            (0x3UL << DAC_CR_WAVE1_Pos)                 /*!< 0x000000C0 */
+#define DAC_CR_WAVE1                DAC_CR_WAVE1_Msk                           /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
+#define DAC_CR_WAVE1_0              (0x1UL << DAC_CR_WAVE1_Pos)                 /*!< 0x00000040 */
+#define DAC_CR_WAVE1_1              (0x2UL << DAC_CR_WAVE1_Pos)                 /*!< 0x00000080 */
+
+#define DAC_CR_MAMP1_Pos            (8U)                                       
+#define DAC_CR_MAMP1_Msk            (0xFUL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000F00 */
+#define DAC_CR_MAMP1                DAC_CR_MAMP1_Msk                           /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
+#define DAC_CR_MAMP1_0              (0x1UL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000100 */
+#define DAC_CR_MAMP1_1              (0x2UL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000200 */
+#define DAC_CR_MAMP1_2              (0x4UL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000400 */
+#define DAC_CR_MAMP1_3              (0x8UL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000800 */
+
+#define DAC_CR_DMAEN1_Pos           (12U)                                      
+#define DAC_CR_DMAEN1_Msk           (0x1UL << DAC_CR_DMAEN1_Pos)                /*!< 0x00001000 */
+#define DAC_CR_DMAEN1               DAC_CR_DMAEN1_Msk                          /*!<DAC channel1 DMA enable */
+#define DAC_CR_DMAUDRIE1_Pos        (13U)                                      
+#define DAC_CR_DMAUDRIE1_Msk        (0x1UL << DAC_CR_DMAUDRIE1_Pos)             /*!< 0x00002000 */
+#define DAC_CR_DMAUDRIE1            DAC_CR_DMAUDRIE1_Msk                       /*!<DAC channel1 DMA underrun interrupt enable*/
+#define DAC_CR_EN2_Pos              (16U)                                      
+#define DAC_CR_EN2_Msk              (0x1UL << DAC_CR_EN2_Pos)                   /*!< 0x00010000 */
+#define DAC_CR_EN2                  DAC_CR_EN2_Msk                             /*!<DAC channel2 enable */
+#define DAC_CR_BOFF2_Pos            (17U)                                      
+#define DAC_CR_BOFF2_Msk            (0x1UL << DAC_CR_BOFF2_Pos)                 /*!< 0x00020000 */
+#define DAC_CR_BOFF2                DAC_CR_BOFF2_Msk                           /*!<DAC channel2 output buffer disable */
+#define DAC_CR_TEN2_Pos             (18U)                                      
+#define DAC_CR_TEN2_Msk             (0x1UL << DAC_CR_TEN2_Pos)                  /*!< 0x00040000 */
+#define DAC_CR_TEN2                 DAC_CR_TEN2_Msk                            /*!<DAC channel2 Trigger enable */
+
+#define DAC_CR_TSEL2_Pos            (19U)                                      
+#define DAC_CR_TSEL2_Msk            (0x7UL << DAC_CR_TSEL2_Pos)                 /*!< 0x00380000 */
+#define DAC_CR_TSEL2                DAC_CR_TSEL2_Msk                           /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
+#define DAC_CR_TSEL2_0              (0x1UL << DAC_CR_TSEL2_Pos)                 /*!< 0x00080000 */
+#define DAC_CR_TSEL2_1              (0x2UL << DAC_CR_TSEL2_Pos)                 /*!< 0x00100000 */
+#define DAC_CR_TSEL2_2              (0x4UL << DAC_CR_TSEL2_Pos)                 /*!< 0x00200000 */
+
+#define DAC_CR_WAVE2_Pos            (22U)                                      
+#define DAC_CR_WAVE2_Msk            (0x3UL << DAC_CR_WAVE2_Pos)                 /*!< 0x00C00000 */
+#define DAC_CR_WAVE2                DAC_CR_WAVE2_Msk                           /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
+#define DAC_CR_WAVE2_0              (0x1UL << DAC_CR_WAVE2_Pos)                 /*!< 0x00400000 */
+#define DAC_CR_WAVE2_1              (0x2UL << DAC_CR_WAVE2_Pos)                 /*!< 0x00800000 */
+
+#define DAC_CR_MAMP2_Pos            (24U)                                      
+#define DAC_CR_MAMP2_Msk            (0xFUL << DAC_CR_MAMP2_Pos)                 /*!< 0x0F000000 */
+#define DAC_CR_MAMP2                DAC_CR_MAMP2_Msk                           /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
+#define DAC_CR_MAMP2_0              (0x1UL << DAC_CR_MAMP2_Pos)                 /*!< 0x01000000 */
+#define DAC_CR_MAMP2_1              (0x2UL << DAC_CR_MAMP2_Pos)                 /*!< 0x02000000 */
+#define DAC_CR_MAMP2_2              (0x4UL << DAC_CR_MAMP2_Pos)                 /*!< 0x04000000 */
+#define DAC_CR_MAMP2_3              (0x8UL << DAC_CR_MAMP2_Pos)                 /*!< 0x08000000 */
+
+#define DAC_CR_DMAEN2_Pos           (28U)                                      
+#define DAC_CR_DMAEN2_Msk           (0x1UL << DAC_CR_DMAEN2_Pos)                /*!< 0x10000000 */
+#define DAC_CR_DMAEN2               DAC_CR_DMAEN2_Msk                          /*!<DAC channel2 DMA enabled */
+#define DAC_CR_DMAUDRIE2_Pos        (29U)                                      
+#define DAC_CR_DMAUDRIE2_Msk        (0x1UL << DAC_CR_DMAUDRIE2_Pos)             /*!< 0x20000000 */
+#define DAC_CR_DMAUDRIE2            DAC_CR_DMAUDRIE2_Msk                       /*!<DAC channel2 DMA underrun interrupt enable*/
+
+/*****************  Bit definition for DAC_SWTRIGR register  ******************/
+#define DAC_SWTRIGR_SWTRIG1_Pos     (0U)                                       
+#define DAC_SWTRIGR_SWTRIG1_Msk     (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos)          /*!< 0x00000001 */
+#define DAC_SWTRIGR_SWTRIG1         DAC_SWTRIGR_SWTRIG1_Msk                    /*!<DAC channel1 software trigger */
+#define DAC_SWTRIGR_SWTRIG2_Pos     (1U)                                       
+#define DAC_SWTRIGR_SWTRIG2_Msk     (0x1UL << DAC_SWTRIGR_SWTRIG2_Pos)          /*!< 0x00000002 */
+#define DAC_SWTRIGR_SWTRIG2         DAC_SWTRIGR_SWTRIG2_Msk                    /*!<DAC channel2 software trigger */
+
+/*****************  Bit definition for DAC_DHR12R1 register  ******************/
+#define DAC_DHR12R1_DACC1DHR_Pos    (0U)                                       
+#define DAC_DHR12R1_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12R1_DACC1DHR_Pos)       /*!< 0x00000FFF */
+#define DAC_DHR12R1_DACC1DHR        DAC_DHR12R1_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Right aligned data */
+
+/*****************  Bit definition for DAC_DHR12L1 register  ******************/
+#define DAC_DHR12L1_DACC1DHR_Pos    (4U)                                       
+#define DAC_DHR12L1_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12L1_DACC1DHR_Pos)       /*!< 0x0000FFF0 */
+#define DAC_DHR12L1_DACC1DHR        DAC_DHR12L1_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Left aligned data */
+
+/******************  Bit definition for DAC_DHR8R1 register  ******************/
+#define DAC_DHR8R1_DACC1DHR_Pos     (0U)                                       
+#define DAC_DHR8R1_DACC1DHR_Msk     (0xFFUL << DAC_DHR8R1_DACC1DHR_Pos)         /*!< 0x000000FF */
+#define DAC_DHR8R1_DACC1DHR         DAC_DHR8R1_DACC1DHR_Msk                    /*!<DAC channel1 8-bit Right aligned data */
+
+/*****************  Bit definition for DAC_DHR12R2 register  ******************/
+#define DAC_DHR12R2_DACC2DHR_Pos    (0U)                                       
+#define DAC_DHR12R2_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12R2_DACC2DHR_Pos)       /*!< 0x00000FFF */
+#define DAC_DHR12R2_DACC2DHR        DAC_DHR12R2_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Right aligned data */
+
+/*****************  Bit definition for DAC_DHR12L2 register  ******************/
+#define DAC_DHR12L2_DACC2DHR_Pos    (4U)                                       
+#define DAC_DHR12L2_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12L2_DACC2DHR_Pos)       /*!< 0x0000FFF0 */
+#define DAC_DHR12L2_DACC2DHR        DAC_DHR12L2_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Left aligned data */
+
+/******************  Bit definition for DAC_DHR8R2 register  ******************/
+#define DAC_DHR8R2_DACC2DHR_Pos     (0U)                                       
+#define DAC_DHR8R2_DACC2DHR_Msk     (0xFFUL << DAC_DHR8R2_DACC2DHR_Pos)         /*!< 0x000000FF */
+#define DAC_DHR8R2_DACC2DHR         DAC_DHR8R2_DACC2DHR_Msk                    /*!<DAC channel2 8-bit Right aligned data */
+
+/*****************  Bit definition for DAC_DHR12RD register  ******************/
+#define DAC_DHR12RD_DACC1DHR_Pos    (0U)                                       
+#define DAC_DHR12RD_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12RD_DACC1DHR_Pos)       /*!< 0x00000FFF */
+#define DAC_DHR12RD_DACC1DHR        DAC_DHR12RD_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Right aligned data */
+#define DAC_DHR12RD_DACC2DHR_Pos    (16U)                                      
+#define DAC_DHR12RD_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12RD_DACC2DHR_Pos)       /*!< 0x0FFF0000 */
+#define DAC_DHR12RD_DACC2DHR        DAC_DHR12RD_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Right aligned data */
+
+/*****************  Bit definition for DAC_DHR12LD register  ******************/
+#define DAC_DHR12LD_DACC1DHR_Pos    (4U)                                       
+#define DAC_DHR12LD_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12LD_DACC1DHR_Pos)       /*!< 0x0000FFF0 */
+#define DAC_DHR12LD_DACC1DHR        DAC_DHR12LD_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Left aligned data */
+#define DAC_DHR12LD_DACC2DHR_Pos    (20U)                                      
+#define DAC_DHR12LD_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12LD_DACC2DHR_Pos)       /*!< 0xFFF00000 */
+#define DAC_DHR12LD_DACC2DHR        DAC_DHR12LD_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Left aligned data */
+
+/******************  Bit definition for DAC_DHR8RD register  ******************/
+#define DAC_DHR8RD_DACC1DHR_Pos     (0U)                                       
+#define DAC_DHR8RD_DACC1DHR_Msk     (0xFFUL << DAC_DHR8RD_DACC1DHR_Pos)         /*!< 0x000000FF */
+#define DAC_DHR8RD_DACC1DHR         DAC_DHR8RD_DACC1DHR_Msk                    /*!<DAC channel1 8-bit Right aligned data */
+#define DAC_DHR8RD_DACC2DHR_Pos     (8U)                                       
+#define DAC_DHR8RD_DACC2DHR_Msk     (0xFFUL << DAC_DHR8RD_DACC2DHR_Pos)         /*!< 0x0000FF00 */
+#define DAC_DHR8RD_DACC2DHR         DAC_DHR8RD_DACC2DHR_Msk                    /*!<DAC channel2 8-bit Right aligned data */
+
+/*******************  Bit definition for DAC_DOR1 register  *******************/
+#define DAC_DOR1_DACC1DOR_Pos       (0U)                                       
+#define DAC_DOR1_DACC1DOR_Msk       (0xFFFUL << DAC_DOR1_DACC1DOR_Pos)          /*!< 0x00000FFF */
+#define DAC_DOR1_DACC1DOR           DAC_DOR1_DACC1DOR_Msk                      /*!<DAC channel1 data output */
+
+/*******************  Bit definition for DAC_DOR2 register  *******************/
+#define DAC_DOR2_DACC2DOR_Pos       (0U)                                       
+#define DAC_DOR2_DACC2DOR_Msk       (0xFFFUL << DAC_DOR2_DACC2DOR_Pos)          /*!< 0x00000FFF */
+#define DAC_DOR2_DACC2DOR           DAC_DOR2_DACC2DOR_Msk                      /*!<DAC channel2 data output */
+
+/********************  Bit definition for DAC_SR register  ********************/
+#define DAC_SR_DMAUDR1_Pos          (13U)                                      
+#define DAC_SR_DMAUDR1_Msk          (0x1UL << DAC_SR_DMAUDR1_Pos)               /*!< 0x00002000 */
+#define DAC_SR_DMAUDR1              DAC_SR_DMAUDR1_Msk                         /*!<DAC channel1 DMA underrun flag */
+#define DAC_SR_DMAUDR2_Pos          (29U)                                      
+#define DAC_SR_DMAUDR2_Msk          (0x1UL << DAC_SR_DMAUDR2_Pos)               /*!< 0x20000000 */
+#define DAC_SR_DMAUDR2              DAC_SR_DMAUDR2_Msk                         /*!<DAC channel2 DMA underrun flag */
+
+/******************************************************************************/
+/*                                                                            */
+/*                                    DCMI                                    */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bits definition for DCMI_CR register  ******************/
+#define DCMI_CR_CAPTURE_Pos        (0U)                                        
+#define DCMI_CR_CAPTURE_Msk        (0x1UL << DCMI_CR_CAPTURE_Pos)               /*!< 0x00000001 */
+#define DCMI_CR_CAPTURE            DCMI_CR_CAPTURE_Msk                         
+#define DCMI_CR_CM_Pos             (1U)                                        
+#define DCMI_CR_CM_Msk             (0x1UL << DCMI_CR_CM_Pos)                    /*!< 0x00000002 */
+#define DCMI_CR_CM                 DCMI_CR_CM_Msk                              
+#define DCMI_CR_CROP_Pos           (2U)                                        
+#define DCMI_CR_CROP_Msk           (0x1UL << DCMI_CR_CROP_Pos)                  /*!< 0x00000004 */
+#define DCMI_CR_CROP               DCMI_CR_CROP_Msk                            
+#define DCMI_CR_JPEG_Pos           (3U)                                        
+#define DCMI_CR_JPEG_Msk           (0x1UL << DCMI_CR_JPEG_Pos)                  /*!< 0x00000008 */
+#define DCMI_CR_JPEG               DCMI_CR_JPEG_Msk                            
+#define DCMI_CR_ESS_Pos            (4U)                                        
+#define DCMI_CR_ESS_Msk            (0x1UL << DCMI_CR_ESS_Pos)                   /*!< 0x00000010 */
+#define DCMI_CR_ESS                DCMI_CR_ESS_Msk                             
+#define DCMI_CR_PCKPOL_Pos         (5U)                                        
+#define DCMI_CR_PCKPOL_Msk         (0x1UL << DCMI_CR_PCKPOL_Pos)                /*!< 0x00000020 */
+#define DCMI_CR_PCKPOL             DCMI_CR_PCKPOL_Msk                          
+#define DCMI_CR_HSPOL_Pos          (6U)                                        
+#define DCMI_CR_HSPOL_Msk          (0x1UL << DCMI_CR_HSPOL_Pos)                 /*!< 0x00000040 */
+#define DCMI_CR_HSPOL              DCMI_CR_HSPOL_Msk                           
+#define DCMI_CR_VSPOL_Pos          (7U)                                        
+#define DCMI_CR_VSPOL_Msk          (0x1UL << DCMI_CR_VSPOL_Pos)                 /*!< 0x00000080 */
+#define DCMI_CR_VSPOL              DCMI_CR_VSPOL_Msk                           
+#define DCMI_CR_FCRC_0             0x00000100U                                 
+#define DCMI_CR_FCRC_1             0x00000200U                                 
+#define DCMI_CR_EDM_0              0x00000400U                                 
+#define DCMI_CR_EDM_1              0x00000800U                                 
+#define DCMI_CR_OUTEN_Pos          (13U)                                       
+#define DCMI_CR_OUTEN_Msk          (0x1UL << DCMI_CR_OUTEN_Pos)                 /*!< 0x00002000 */
+#define DCMI_CR_OUTEN              DCMI_CR_OUTEN_Msk                           
+#define DCMI_CR_ENABLE_Pos         (14U)                                       
+#define DCMI_CR_ENABLE_Msk         (0x1UL << DCMI_CR_ENABLE_Pos)                /*!< 0x00004000 */
+#define DCMI_CR_ENABLE             DCMI_CR_ENABLE_Msk                          
+#define DCMI_CR_BSM_0              0x00010000U                                 
+#define DCMI_CR_BSM_1              0x00020000U                                 
+#define DCMI_CR_OEBS_Pos           (18U)                                       
+#define DCMI_CR_OEBS_Msk           (0x1UL << DCMI_CR_OEBS_Pos)                  /*!< 0x00040000 */
+#define DCMI_CR_OEBS               DCMI_CR_OEBS_Msk                            
+#define DCMI_CR_LSM_Pos            (19U)                                       
+#define DCMI_CR_LSM_Msk            (0x1UL << DCMI_CR_LSM_Pos)                   /*!< 0x00080000 */
+#define DCMI_CR_LSM                DCMI_CR_LSM_Msk                             
+#define DCMI_CR_OELS_Pos           (20U)                                       
+#define DCMI_CR_OELS_Msk           (0x1UL << DCMI_CR_OELS_Pos)                  /*!< 0x00100000 */
+#define DCMI_CR_OELS               DCMI_CR_OELS_Msk                            
+
+/********************  Bits definition for DCMI_SR register  ******************/
+#define DCMI_SR_HSYNC_Pos          (0U)                                        
+#define DCMI_SR_HSYNC_Msk          (0x1UL << DCMI_SR_HSYNC_Pos)                 /*!< 0x00000001 */
+#define DCMI_SR_HSYNC              DCMI_SR_HSYNC_Msk                           
+#define DCMI_SR_VSYNC_Pos          (1U)                                        
+#define DCMI_SR_VSYNC_Msk          (0x1UL << DCMI_SR_VSYNC_Pos)                 /*!< 0x00000002 */
+#define DCMI_SR_VSYNC              DCMI_SR_VSYNC_Msk                           
+#define DCMI_SR_FNE_Pos            (2U)                                        
+#define DCMI_SR_FNE_Msk            (0x1UL << DCMI_SR_FNE_Pos)                   /*!< 0x00000004 */
+#define DCMI_SR_FNE                DCMI_SR_FNE_Msk                             
+
+/********************  Bits definition for DCMI_RIS register  *****************/
+#define DCMI_RIS_FRAME_RIS_Pos     (0U)                                        
+#define DCMI_RIS_FRAME_RIS_Msk     (0x1UL << DCMI_RIS_FRAME_RIS_Pos)            /*!< 0x00000001 */
+#define DCMI_RIS_FRAME_RIS         DCMI_RIS_FRAME_RIS_Msk                      
+#define DCMI_RIS_OVR_RIS_Pos       (1U)                                        
+#define DCMI_RIS_OVR_RIS_Msk       (0x1UL << DCMI_RIS_OVR_RIS_Pos)              /*!< 0x00000002 */
+#define DCMI_RIS_OVR_RIS           DCMI_RIS_OVR_RIS_Msk                        
+#define DCMI_RIS_ERR_RIS_Pos       (2U)                                        
+#define DCMI_RIS_ERR_RIS_Msk       (0x1UL << DCMI_RIS_ERR_RIS_Pos)              /*!< 0x00000004 */
+#define DCMI_RIS_ERR_RIS           DCMI_RIS_ERR_RIS_Msk                        
+#define DCMI_RIS_VSYNC_RIS_Pos     (3U)                                        
+#define DCMI_RIS_VSYNC_RIS_Msk     (0x1UL << DCMI_RIS_VSYNC_RIS_Pos)            /*!< 0x00000008 */
+#define DCMI_RIS_VSYNC_RIS         DCMI_RIS_VSYNC_RIS_Msk                      
+#define DCMI_RIS_LINE_RIS_Pos      (4U)                                        
+#define DCMI_RIS_LINE_RIS_Msk      (0x1UL << DCMI_RIS_LINE_RIS_Pos)             /*!< 0x00000010 */
+#define DCMI_RIS_LINE_RIS          DCMI_RIS_LINE_RIS_Msk                       
+/* Legacy defines */
+#define DCMI_RISR_FRAME_RIS                  DCMI_RIS_FRAME_RIS
+#define DCMI_RISR_OVR_RIS                    DCMI_RIS_OVR_RIS
+#define DCMI_RISR_ERR_RIS                    DCMI_RIS_ERR_RIS
+#define DCMI_RISR_VSYNC_RIS                  DCMI_RIS_VSYNC_RIS
+#define DCMI_RISR_LINE_RIS                   DCMI_RIS_LINE_RIS
+#define DCMI_RISR_OVF_RIS                    DCMI_RIS_OVR_RIS
+
+/********************  Bits definition for DCMI_IER register  *****************/
+#define DCMI_IER_FRAME_IE_Pos      (0U)                                        
+#define DCMI_IER_FRAME_IE_Msk      (0x1UL << DCMI_IER_FRAME_IE_Pos)             /*!< 0x00000001 */
+#define DCMI_IER_FRAME_IE          DCMI_IER_FRAME_IE_Msk                       
+#define DCMI_IER_OVR_IE_Pos        (1U)                                        
+#define DCMI_IER_OVR_IE_Msk        (0x1UL << DCMI_IER_OVR_IE_Pos)               /*!< 0x00000002 */
+#define DCMI_IER_OVR_IE            DCMI_IER_OVR_IE_Msk                         
+#define DCMI_IER_ERR_IE_Pos        (2U)                                        
+#define DCMI_IER_ERR_IE_Msk        (0x1UL << DCMI_IER_ERR_IE_Pos)               /*!< 0x00000004 */
+#define DCMI_IER_ERR_IE            DCMI_IER_ERR_IE_Msk                         
+#define DCMI_IER_VSYNC_IE_Pos      (3U)                                        
+#define DCMI_IER_VSYNC_IE_Msk      (0x1UL << DCMI_IER_VSYNC_IE_Pos)             /*!< 0x00000008 */
+#define DCMI_IER_VSYNC_IE          DCMI_IER_VSYNC_IE_Msk                       
+#define DCMI_IER_LINE_IE_Pos       (4U)                                        
+#define DCMI_IER_LINE_IE_Msk       (0x1UL << DCMI_IER_LINE_IE_Pos)              /*!< 0x00000010 */
+#define DCMI_IER_LINE_IE           DCMI_IER_LINE_IE_Msk                        
+/* Legacy defines */
+#define DCMI_IER_OVF_IE                      DCMI_IER_OVR_IE
+
+/********************  Bits definition for DCMI_MIS register  *****************/
+#define DCMI_MIS_FRAME_MIS_Pos     (0U)                                        
+#define DCMI_MIS_FRAME_MIS_Msk     (0x1UL << DCMI_MIS_FRAME_MIS_Pos)            /*!< 0x00000001 */
+#define DCMI_MIS_FRAME_MIS         DCMI_MIS_FRAME_MIS_Msk                      
+#define DCMI_MIS_OVR_MIS_Pos       (1U)                                        
+#define DCMI_MIS_OVR_MIS_Msk       (0x1UL << DCMI_MIS_OVR_MIS_Pos)              /*!< 0x00000002 */
+#define DCMI_MIS_OVR_MIS           DCMI_MIS_OVR_MIS_Msk                        
+#define DCMI_MIS_ERR_MIS_Pos       (2U)                                        
+#define DCMI_MIS_ERR_MIS_Msk       (0x1UL << DCMI_MIS_ERR_MIS_Pos)              /*!< 0x00000004 */
+#define DCMI_MIS_ERR_MIS           DCMI_MIS_ERR_MIS_Msk                        
+#define DCMI_MIS_VSYNC_MIS_Pos     (3U)                                        
+#define DCMI_MIS_VSYNC_MIS_Msk     (0x1UL << DCMI_MIS_VSYNC_MIS_Pos)            /*!< 0x00000008 */
+#define DCMI_MIS_VSYNC_MIS         DCMI_MIS_VSYNC_MIS_Msk                      
+#define DCMI_MIS_LINE_MIS_Pos      (4U)                                        
+#define DCMI_MIS_LINE_MIS_Msk      (0x1UL << DCMI_MIS_LINE_MIS_Pos)             /*!< 0x00000010 */
+#define DCMI_MIS_LINE_MIS          DCMI_MIS_LINE_MIS_Msk                       
+
+/* Legacy defines */
+#define DCMI_MISR_FRAME_MIS                  DCMI_MIS_FRAME_MIS
+#define DCMI_MISR_OVF_MIS                    DCMI_MIS_OVR_MIS
+#define DCMI_MISR_ERR_MIS                    DCMI_MIS_ERR_MIS
+#define DCMI_MISR_VSYNC_MIS                  DCMI_MIS_VSYNC_MIS
+#define DCMI_MISR_LINE_MIS                   DCMI_MIS_LINE_MIS
+
+/********************  Bits definition for DCMI_ICR register  *****************/
+#define DCMI_ICR_FRAME_ISC_Pos     (0U)                                        
+#define DCMI_ICR_FRAME_ISC_Msk     (0x1UL << DCMI_ICR_FRAME_ISC_Pos)            /*!< 0x00000001 */
+#define DCMI_ICR_FRAME_ISC         DCMI_ICR_FRAME_ISC_Msk                      
+#define DCMI_ICR_OVR_ISC_Pos       (1U)                                        
+#define DCMI_ICR_OVR_ISC_Msk       (0x1UL << DCMI_ICR_OVR_ISC_Pos)              /*!< 0x00000002 */
+#define DCMI_ICR_OVR_ISC           DCMI_ICR_OVR_ISC_Msk                        
+#define DCMI_ICR_ERR_ISC_Pos       (2U)                                        
+#define DCMI_ICR_ERR_ISC_Msk       (0x1UL << DCMI_ICR_ERR_ISC_Pos)              /*!< 0x00000004 */
+#define DCMI_ICR_ERR_ISC           DCMI_ICR_ERR_ISC_Msk                        
+#define DCMI_ICR_VSYNC_ISC_Pos     (3U)                                        
+#define DCMI_ICR_VSYNC_ISC_Msk     (0x1UL << DCMI_ICR_VSYNC_ISC_Pos)            /*!< 0x00000008 */
+#define DCMI_ICR_VSYNC_ISC         DCMI_ICR_VSYNC_ISC_Msk                      
+#define DCMI_ICR_LINE_ISC_Pos      (4U)                                        
+#define DCMI_ICR_LINE_ISC_Msk      (0x1UL << DCMI_ICR_LINE_ISC_Pos)             /*!< 0x00000010 */
+#define DCMI_ICR_LINE_ISC          DCMI_ICR_LINE_ISC_Msk                       
+
+/* Legacy defines */
+#define DCMI_ICR_OVF_ISC                     DCMI_ICR_OVR_ISC
+
+/********************  Bits definition for DCMI_ESCR register  ******************/
+#define DCMI_ESCR_FSC_Pos          (0U)                                        
+#define DCMI_ESCR_FSC_Msk          (0xFFUL << DCMI_ESCR_FSC_Pos)                /*!< 0x000000FF */
+#define DCMI_ESCR_FSC              DCMI_ESCR_FSC_Msk                           
+#define DCMI_ESCR_LSC_Pos          (8U)                                        
+#define DCMI_ESCR_LSC_Msk          (0xFFUL << DCMI_ESCR_LSC_Pos)                /*!< 0x0000FF00 */
+#define DCMI_ESCR_LSC              DCMI_ESCR_LSC_Msk                           
+#define DCMI_ESCR_LEC_Pos          (16U)                                       
+#define DCMI_ESCR_LEC_Msk          (0xFFUL << DCMI_ESCR_LEC_Pos)                /*!< 0x00FF0000 */
+#define DCMI_ESCR_LEC              DCMI_ESCR_LEC_Msk                           
+#define DCMI_ESCR_FEC_Pos          (24U)                                       
+#define DCMI_ESCR_FEC_Msk          (0xFFUL << DCMI_ESCR_FEC_Pos)                /*!< 0xFF000000 */
+#define DCMI_ESCR_FEC              DCMI_ESCR_FEC_Msk                           
+
+/********************  Bits definition for DCMI_ESUR register  ******************/
+#define DCMI_ESUR_FSU_Pos          (0U)                                        
+#define DCMI_ESUR_FSU_Msk          (0xFFUL << DCMI_ESUR_FSU_Pos)                /*!< 0x000000FF */
+#define DCMI_ESUR_FSU              DCMI_ESUR_FSU_Msk                           
+#define DCMI_ESUR_LSU_Pos          (8U)                                        
+#define DCMI_ESUR_LSU_Msk          (0xFFUL << DCMI_ESUR_LSU_Pos)                /*!< 0x0000FF00 */
+#define DCMI_ESUR_LSU              DCMI_ESUR_LSU_Msk                           
+#define DCMI_ESUR_LEU_Pos          (16U)                                       
+#define DCMI_ESUR_LEU_Msk          (0xFFUL << DCMI_ESUR_LEU_Pos)                /*!< 0x00FF0000 */
+#define DCMI_ESUR_LEU              DCMI_ESUR_LEU_Msk                           
+#define DCMI_ESUR_FEU_Pos          (24U)                                       
+#define DCMI_ESUR_FEU_Msk          (0xFFUL << DCMI_ESUR_FEU_Pos)                /*!< 0xFF000000 */
+#define DCMI_ESUR_FEU              DCMI_ESUR_FEU_Msk                           
+
+/********************  Bits definition for DCMI_CWSTRT register  ******************/
+#define DCMI_CWSTRT_HOFFCNT_Pos    (0U)                                        
+#define DCMI_CWSTRT_HOFFCNT_Msk    (0x3FFFUL << DCMI_CWSTRT_HOFFCNT_Pos)        /*!< 0x00003FFF */
+#define DCMI_CWSTRT_HOFFCNT        DCMI_CWSTRT_HOFFCNT_Msk                     
+#define DCMI_CWSTRT_VST_Pos        (16U)                                       
+#define DCMI_CWSTRT_VST_Msk        (0x1FFFUL << DCMI_CWSTRT_VST_Pos)            /*!< 0x1FFF0000 */
+#define DCMI_CWSTRT_VST            DCMI_CWSTRT_VST_Msk                         
+
+/********************  Bits definition for DCMI_CWSIZE register  ******************/
+#define DCMI_CWSIZE_CAPCNT_Pos     (0U)                                        
+#define DCMI_CWSIZE_CAPCNT_Msk     (0x3FFFUL << DCMI_CWSIZE_CAPCNT_Pos)         /*!< 0x00003FFF */
+#define DCMI_CWSIZE_CAPCNT         DCMI_CWSIZE_CAPCNT_Msk                      
+#define DCMI_CWSIZE_VLINE_Pos      (16U)                                       
+#define DCMI_CWSIZE_VLINE_Msk      (0x3FFFUL << DCMI_CWSIZE_VLINE_Pos)          /*!< 0x3FFF0000 */
+#define DCMI_CWSIZE_VLINE          DCMI_CWSIZE_VLINE_Msk                       
+
+/********************  Bits definition for DCMI_DR register  *********************/
+#define DCMI_DR_BYTE0_Pos          (0U)                                        
+#define DCMI_DR_BYTE0_Msk          (0xFFUL << DCMI_DR_BYTE0_Pos)                /*!< 0x000000FF */
+#define DCMI_DR_BYTE0              DCMI_DR_BYTE0_Msk                           
+#define DCMI_DR_BYTE1_Pos          (8U)                                        
+#define DCMI_DR_BYTE1_Msk          (0xFFUL << DCMI_DR_BYTE1_Pos)                /*!< 0x0000FF00 */
+#define DCMI_DR_BYTE1              DCMI_DR_BYTE1_Msk                           
+#define DCMI_DR_BYTE2_Pos          (16U)                                       
+#define DCMI_DR_BYTE2_Msk          (0xFFUL << DCMI_DR_BYTE2_Pos)                /*!< 0x00FF0000 */
+#define DCMI_DR_BYTE2              DCMI_DR_BYTE2_Msk                           
+#define DCMI_DR_BYTE3_Pos          (24U)                                       
+#define DCMI_DR_BYTE3_Msk          (0xFFUL << DCMI_DR_BYTE3_Pos)                /*!< 0xFF000000 */
+#define DCMI_DR_BYTE3              DCMI_DR_BYTE3_Msk                           
+
+/******************************************************************************/
+/*                                                                            */
+/*                             DMA Controller                                 */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bits definition for DMA_SxCR register  *****************/
+#define DMA_SxCR_CHSEL_Pos       (25U)                                         
+#define DMA_SxCR_CHSEL_Msk       (0x7UL << DMA_SxCR_CHSEL_Pos)                  /*!< 0x0E000000 */
+#define DMA_SxCR_CHSEL           DMA_SxCR_CHSEL_Msk                            
+#define DMA_SxCR_CHSEL_0         0x02000000U                                   
+#define DMA_SxCR_CHSEL_1         0x04000000U                                   
+#define DMA_SxCR_CHSEL_2         0x08000000U                                   
+#define DMA_SxCR_MBURST_Pos      (23U)                                         
+#define DMA_SxCR_MBURST_Msk      (0x3UL << DMA_SxCR_MBURST_Pos)                 /*!< 0x01800000 */
+#define DMA_SxCR_MBURST          DMA_SxCR_MBURST_Msk                           
+#define DMA_SxCR_MBURST_0        (0x1UL << DMA_SxCR_MBURST_Pos)                 /*!< 0x00800000 */
+#define DMA_SxCR_MBURST_1        (0x2UL << DMA_SxCR_MBURST_Pos)                 /*!< 0x01000000 */
+#define DMA_SxCR_PBURST_Pos      (21U)                                         
+#define DMA_SxCR_PBURST_Msk      (0x3UL << DMA_SxCR_PBURST_Pos)                 /*!< 0x00600000 */
+#define DMA_SxCR_PBURST          DMA_SxCR_PBURST_Msk                           
+#define DMA_SxCR_PBURST_0        (0x1UL << DMA_SxCR_PBURST_Pos)                 /*!< 0x00200000 */
+#define DMA_SxCR_PBURST_1        (0x2UL << DMA_SxCR_PBURST_Pos)                 /*!< 0x00400000 */
+#define DMA_SxCR_CT_Pos          (19U)                                         
+#define DMA_SxCR_CT_Msk          (0x1UL << DMA_SxCR_CT_Pos)                     /*!< 0x00080000 */
+#define DMA_SxCR_CT              DMA_SxCR_CT_Msk                               
+#define DMA_SxCR_DBM_Pos         (18U)                                         
+#define DMA_SxCR_DBM_Msk         (0x1UL << DMA_SxCR_DBM_Pos)                    /*!< 0x00040000 */
+#define DMA_SxCR_DBM             DMA_SxCR_DBM_Msk                              
+#define DMA_SxCR_PL_Pos          (16U)                                         
+#define DMA_SxCR_PL_Msk          (0x3UL << DMA_SxCR_PL_Pos)                     /*!< 0x00030000 */
+#define DMA_SxCR_PL              DMA_SxCR_PL_Msk                               
+#define DMA_SxCR_PL_0            (0x1UL << DMA_SxCR_PL_Pos)                     /*!< 0x00010000 */
+#define DMA_SxCR_PL_1            (0x2UL << DMA_SxCR_PL_Pos)                     /*!< 0x00020000 */
+#define DMA_SxCR_PINCOS_Pos      (15U)                                         
+#define DMA_SxCR_PINCOS_Msk      (0x1UL << DMA_SxCR_PINCOS_Pos)                 /*!< 0x00008000 */
+#define DMA_SxCR_PINCOS          DMA_SxCR_PINCOS_Msk                           
+#define DMA_SxCR_MSIZE_Pos       (13U)                                         
+#define DMA_SxCR_MSIZE_Msk       (0x3UL << DMA_SxCR_MSIZE_Pos)                  /*!< 0x00006000 */
+#define DMA_SxCR_MSIZE           DMA_SxCR_MSIZE_Msk                            
+#define DMA_SxCR_MSIZE_0         (0x1UL << DMA_SxCR_MSIZE_Pos)                  /*!< 0x00002000 */
+#define DMA_SxCR_MSIZE_1         (0x2UL << DMA_SxCR_MSIZE_Pos)                  /*!< 0x00004000 */
+#define DMA_SxCR_PSIZE_Pos       (11U)                                         
+#define DMA_SxCR_PSIZE_Msk       (0x3UL << DMA_SxCR_PSIZE_Pos)                  /*!< 0x00001800 */
+#define DMA_SxCR_PSIZE           DMA_SxCR_PSIZE_Msk                            
+#define DMA_SxCR_PSIZE_0         (0x1UL << DMA_SxCR_PSIZE_Pos)                  /*!< 0x00000800 */
+#define DMA_SxCR_PSIZE_1         (0x2UL << DMA_SxCR_PSIZE_Pos)                  /*!< 0x00001000 */
+#define DMA_SxCR_MINC_Pos        (10U)                                         
+#define DMA_SxCR_MINC_Msk        (0x1UL << DMA_SxCR_MINC_Pos)                   /*!< 0x00000400 */
+#define DMA_SxCR_MINC            DMA_SxCR_MINC_Msk                             
+#define DMA_SxCR_PINC_Pos        (9U)                                          
+#define DMA_SxCR_PINC_Msk        (0x1UL << DMA_SxCR_PINC_Pos)                   /*!< 0x00000200 */
+#define DMA_SxCR_PINC            DMA_SxCR_PINC_Msk                             
+#define DMA_SxCR_CIRC_Pos        (8U)                                          
+#define DMA_SxCR_CIRC_Msk        (0x1UL << DMA_SxCR_CIRC_Pos)                   /*!< 0x00000100 */
+#define DMA_SxCR_CIRC            DMA_SxCR_CIRC_Msk                             
+#define DMA_SxCR_DIR_Pos         (6U)                                          
+#define DMA_SxCR_DIR_Msk         (0x3UL << DMA_SxCR_DIR_Pos)                    /*!< 0x000000C0 */
+#define DMA_SxCR_DIR             DMA_SxCR_DIR_Msk                              
+#define DMA_SxCR_DIR_0           (0x1UL << DMA_SxCR_DIR_Pos)                    /*!< 0x00000040 */
+#define DMA_SxCR_DIR_1           (0x2UL << DMA_SxCR_DIR_Pos)                    /*!< 0x00000080 */
+#define DMA_SxCR_PFCTRL_Pos      (5U)                                          
+#define DMA_SxCR_PFCTRL_Msk      (0x1UL << DMA_SxCR_PFCTRL_Pos)                 /*!< 0x00000020 */
+#define DMA_SxCR_PFCTRL          DMA_SxCR_PFCTRL_Msk                           
+#define DMA_SxCR_TCIE_Pos        (4U)                                          
+#define DMA_SxCR_TCIE_Msk        (0x1UL << DMA_SxCR_TCIE_Pos)                   /*!< 0x00000010 */
+#define DMA_SxCR_TCIE            DMA_SxCR_TCIE_Msk                             
+#define DMA_SxCR_HTIE_Pos        (3U)                                          
+#define DMA_SxCR_HTIE_Msk        (0x1UL << DMA_SxCR_HTIE_Pos)                   /*!< 0x00000008 */
+#define DMA_SxCR_HTIE            DMA_SxCR_HTIE_Msk                             
+#define DMA_SxCR_TEIE_Pos        (2U)                                          
+#define DMA_SxCR_TEIE_Msk        (0x1UL << DMA_SxCR_TEIE_Pos)                   /*!< 0x00000004 */
+#define DMA_SxCR_TEIE            DMA_SxCR_TEIE_Msk                             
+#define DMA_SxCR_DMEIE_Pos       (1U)                                          
+#define DMA_SxCR_DMEIE_Msk       (0x1UL << DMA_SxCR_DMEIE_Pos)                  /*!< 0x00000002 */
+#define DMA_SxCR_DMEIE           DMA_SxCR_DMEIE_Msk                            
+#define DMA_SxCR_EN_Pos          (0U)                                          
+#define DMA_SxCR_EN_Msk          (0x1UL << DMA_SxCR_EN_Pos)                     /*!< 0x00000001 */
+#define DMA_SxCR_EN              DMA_SxCR_EN_Msk                               
+
+/* Legacy defines */
+#define DMA_SxCR_ACK_Pos         (20U)                                         
+#define DMA_SxCR_ACK_Msk         (0x1UL << DMA_SxCR_ACK_Pos)                    /*!< 0x00100000 */
+#define DMA_SxCR_ACK             DMA_SxCR_ACK_Msk                              
+
+/********************  Bits definition for DMA_SxCNDTR register  **************/
+#define DMA_SxNDT_Pos            (0U)                                          
+#define DMA_SxNDT_Msk            (0xFFFFUL << DMA_SxNDT_Pos)                    /*!< 0x0000FFFF */
+#define DMA_SxNDT                DMA_SxNDT_Msk                                 
+#define DMA_SxNDT_0              (0x0001UL << DMA_SxNDT_Pos)                    /*!< 0x00000001 */
+#define DMA_SxNDT_1              (0x0002UL << DMA_SxNDT_Pos)                    /*!< 0x00000002 */
+#define DMA_SxNDT_2              (0x0004UL << DMA_SxNDT_Pos)                    /*!< 0x00000004 */
+#define DMA_SxNDT_3              (0x0008UL << DMA_SxNDT_Pos)                    /*!< 0x00000008 */
+#define DMA_SxNDT_4              (0x0010UL << DMA_SxNDT_Pos)                    /*!< 0x00000010 */
+#define DMA_SxNDT_5              (0x0020UL << DMA_SxNDT_Pos)                    /*!< 0x00000020 */
+#define DMA_SxNDT_6              (0x0040UL << DMA_SxNDT_Pos)                    /*!< 0x00000040 */
+#define DMA_SxNDT_7              (0x0080UL << DMA_SxNDT_Pos)                    /*!< 0x00000080 */
+#define DMA_SxNDT_8              (0x0100UL << DMA_SxNDT_Pos)                    /*!< 0x00000100 */
+#define DMA_SxNDT_9              (0x0200UL << DMA_SxNDT_Pos)                    /*!< 0x00000200 */
+#define DMA_SxNDT_10             (0x0400UL << DMA_SxNDT_Pos)                    /*!< 0x00000400 */
+#define DMA_SxNDT_11             (0x0800UL << DMA_SxNDT_Pos)                    /*!< 0x00000800 */
+#define DMA_SxNDT_12             (0x1000UL << DMA_SxNDT_Pos)                    /*!< 0x00001000 */
+#define DMA_SxNDT_13             (0x2000UL << DMA_SxNDT_Pos)                    /*!< 0x00002000 */
+#define DMA_SxNDT_14             (0x4000UL << DMA_SxNDT_Pos)                    /*!< 0x00004000 */
+#define DMA_SxNDT_15             (0x8000UL << DMA_SxNDT_Pos)                    /*!< 0x00008000 */
+
+/********************  Bits definition for DMA_SxFCR register  ****************/ 
+#define DMA_SxFCR_FEIE_Pos       (7U)                                          
+#define DMA_SxFCR_FEIE_Msk       (0x1UL << DMA_SxFCR_FEIE_Pos)                  /*!< 0x00000080 */
+#define DMA_SxFCR_FEIE           DMA_SxFCR_FEIE_Msk                            
+#define DMA_SxFCR_FS_Pos         (3U)                                          
+#define DMA_SxFCR_FS_Msk         (0x7UL << DMA_SxFCR_FS_Pos)                    /*!< 0x00000038 */
+#define DMA_SxFCR_FS             DMA_SxFCR_FS_Msk                              
+#define DMA_SxFCR_FS_0           (0x1UL << DMA_SxFCR_FS_Pos)                    /*!< 0x00000008 */
+#define DMA_SxFCR_FS_1           (0x2UL << DMA_SxFCR_FS_Pos)                    /*!< 0x00000010 */
+#define DMA_SxFCR_FS_2           (0x4UL << DMA_SxFCR_FS_Pos)                    /*!< 0x00000020 */
+#define DMA_SxFCR_DMDIS_Pos      (2U)                                          
+#define DMA_SxFCR_DMDIS_Msk      (0x1UL << DMA_SxFCR_DMDIS_Pos)                 /*!< 0x00000004 */
+#define DMA_SxFCR_DMDIS          DMA_SxFCR_DMDIS_Msk                           
+#define DMA_SxFCR_FTH_Pos        (0U)                                          
+#define DMA_SxFCR_FTH_Msk        (0x3UL << DMA_SxFCR_FTH_Pos)                   /*!< 0x00000003 */
+#define DMA_SxFCR_FTH            DMA_SxFCR_FTH_Msk                             
+#define DMA_SxFCR_FTH_0          (0x1UL << DMA_SxFCR_FTH_Pos)                   /*!< 0x00000001 */
+#define DMA_SxFCR_FTH_1          (0x2UL << DMA_SxFCR_FTH_Pos)                   /*!< 0x00000002 */
+
+/********************  Bits definition for DMA_LISR register  *****************/ 
+#define DMA_LISR_TCIF3_Pos       (27U)                                         
+#define DMA_LISR_TCIF3_Msk       (0x1UL << DMA_LISR_TCIF3_Pos)                  /*!< 0x08000000 */
+#define DMA_LISR_TCIF3           DMA_LISR_TCIF3_Msk                            
+#define DMA_LISR_HTIF3_Pos       (26U)                                         
+#define DMA_LISR_HTIF3_Msk       (0x1UL << DMA_LISR_HTIF3_Pos)                  /*!< 0x04000000 */
+#define DMA_LISR_HTIF3           DMA_LISR_HTIF3_Msk                            
+#define DMA_LISR_TEIF3_Pos       (25U)                                         
+#define DMA_LISR_TEIF3_Msk       (0x1UL << DMA_LISR_TEIF3_Pos)                  /*!< 0x02000000 */
+#define DMA_LISR_TEIF3           DMA_LISR_TEIF3_Msk                            
+#define DMA_LISR_DMEIF3_Pos      (24U)                                         
+#define DMA_LISR_DMEIF3_Msk      (0x1UL << DMA_LISR_DMEIF3_Pos)                 /*!< 0x01000000 */
+#define DMA_LISR_DMEIF3          DMA_LISR_DMEIF3_Msk                           
+#define DMA_LISR_FEIF3_Pos       (22U)                                         
+#define DMA_LISR_FEIF3_Msk       (0x1UL << DMA_LISR_FEIF3_Pos)                  /*!< 0x00400000 */
+#define DMA_LISR_FEIF3           DMA_LISR_FEIF3_Msk                            
+#define DMA_LISR_TCIF2_Pos       (21U)                                         
+#define DMA_LISR_TCIF2_Msk       (0x1UL << DMA_LISR_TCIF2_Pos)                  /*!< 0x00200000 */
+#define DMA_LISR_TCIF2           DMA_LISR_TCIF2_Msk                            
+#define DMA_LISR_HTIF2_Pos       (20U)                                         
+#define DMA_LISR_HTIF2_Msk       (0x1UL << DMA_LISR_HTIF2_Pos)                  /*!< 0x00100000 */
+#define DMA_LISR_HTIF2           DMA_LISR_HTIF2_Msk                            
+#define DMA_LISR_TEIF2_Pos       (19U)                                         
+#define DMA_LISR_TEIF2_Msk       (0x1UL << DMA_LISR_TEIF2_Pos)                  /*!< 0x00080000 */
+#define DMA_LISR_TEIF2           DMA_LISR_TEIF2_Msk                            
+#define DMA_LISR_DMEIF2_Pos      (18U)                                         
+#define DMA_LISR_DMEIF2_Msk      (0x1UL << DMA_LISR_DMEIF2_Pos)                 /*!< 0x00040000 */
+#define DMA_LISR_DMEIF2          DMA_LISR_DMEIF2_Msk                           
+#define DMA_LISR_FEIF2_Pos       (16U)                                         
+#define DMA_LISR_FEIF2_Msk       (0x1UL << DMA_LISR_FEIF2_Pos)                  /*!< 0x00010000 */
+#define DMA_LISR_FEIF2           DMA_LISR_FEIF2_Msk                            
+#define DMA_LISR_TCIF1_Pos       (11U)                                         
+#define DMA_LISR_TCIF1_Msk       (0x1UL << DMA_LISR_TCIF1_Pos)                  /*!< 0x00000800 */
+#define DMA_LISR_TCIF1           DMA_LISR_TCIF1_Msk                            
+#define DMA_LISR_HTIF1_Pos       (10U)                                         
+#define DMA_LISR_HTIF1_Msk       (0x1UL << DMA_LISR_HTIF1_Pos)                  /*!< 0x00000400 */
+#define DMA_LISR_HTIF1           DMA_LISR_HTIF1_Msk                            
+#define DMA_LISR_TEIF1_Pos       (9U)                                          
+#define DMA_LISR_TEIF1_Msk       (0x1UL << DMA_LISR_TEIF1_Pos)                  /*!< 0x00000200 */
+#define DMA_LISR_TEIF1           DMA_LISR_TEIF1_Msk                            
+#define DMA_LISR_DMEIF1_Pos      (8U)                                          
+#define DMA_LISR_DMEIF1_Msk      (0x1UL << DMA_LISR_DMEIF1_Pos)                 /*!< 0x00000100 */
+#define DMA_LISR_DMEIF1          DMA_LISR_DMEIF1_Msk                           
+#define DMA_LISR_FEIF1_Pos       (6U)                                          
+#define DMA_LISR_FEIF1_Msk       (0x1UL << DMA_LISR_FEIF1_Pos)                  /*!< 0x00000040 */
+#define DMA_LISR_FEIF1           DMA_LISR_FEIF1_Msk                            
+#define DMA_LISR_TCIF0_Pos       (5U)                                          
+#define DMA_LISR_TCIF0_Msk       (0x1UL << DMA_LISR_TCIF0_Pos)                  /*!< 0x00000020 */
+#define DMA_LISR_TCIF0           DMA_LISR_TCIF0_Msk                            
+#define DMA_LISR_HTIF0_Pos       (4U)                                          
+#define DMA_LISR_HTIF0_Msk       (0x1UL << DMA_LISR_HTIF0_Pos)                  /*!< 0x00000010 */
+#define DMA_LISR_HTIF0           DMA_LISR_HTIF0_Msk                            
+#define DMA_LISR_TEIF0_Pos       (3U)                                          
+#define DMA_LISR_TEIF0_Msk       (0x1UL << DMA_LISR_TEIF0_Pos)                  /*!< 0x00000008 */
+#define DMA_LISR_TEIF0           DMA_LISR_TEIF0_Msk                            
+#define DMA_LISR_DMEIF0_Pos      (2U)                                          
+#define DMA_LISR_DMEIF0_Msk      (0x1UL << DMA_LISR_DMEIF0_Pos)                 /*!< 0x00000004 */
+#define DMA_LISR_DMEIF0          DMA_LISR_DMEIF0_Msk                           
+#define DMA_LISR_FEIF0_Pos       (0U)                                          
+#define DMA_LISR_FEIF0_Msk       (0x1UL << DMA_LISR_FEIF0_Pos)                  /*!< 0x00000001 */
+#define DMA_LISR_FEIF0           DMA_LISR_FEIF0_Msk                            
+
+/********************  Bits definition for DMA_HISR register  *****************/ 
+#define DMA_HISR_TCIF7_Pos       (27U)                                         
+#define DMA_HISR_TCIF7_Msk       (0x1UL << DMA_HISR_TCIF7_Pos)                  /*!< 0x08000000 */
+#define DMA_HISR_TCIF7           DMA_HISR_TCIF7_Msk                            
+#define DMA_HISR_HTIF7_Pos       (26U)                                         
+#define DMA_HISR_HTIF7_Msk       (0x1UL << DMA_HISR_HTIF7_Pos)                  /*!< 0x04000000 */
+#define DMA_HISR_HTIF7           DMA_HISR_HTIF7_Msk                            
+#define DMA_HISR_TEIF7_Pos       (25U)                                         
+#define DMA_HISR_TEIF7_Msk       (0x1UL << DMA_HISR_TEIF7_Pos)                  /*!< 0x02000000 */
+#define DMA_HISR_TEIF7           DMA_HISR_TEIF7_Msk                            
+#define DMA_HISR_DMEIF7_Pos      (24U)                                         
+#define DMA_HISR_DMEIF7_Msk      (0x1UL << DMA_HISR_DMEIF7_Pos)                 /*!< 0x01000000 */
+#define DMA_HISR_DMEIF7          DMA_HISR_DMEIF7_Msk                           
+#define DMA_HISR_FEIF7_Pos       (22U)                                         
+#define DMA_HISR_FEIF7_Msk       (0x1UL << DMA_HISR_FEIF7_Pos)                  /*!< 0x00400000 */
+#define DMA_HISR_FEIF7           DMA_HISR_FEIF7_Msk                            
+#define DMA_HISR_TCIF6_Pos       (21U)                                         
+#define DMA_HISR_TCIF6_Msk       (0x1UL << DMA_HISR_TCIF6_Pos)                  /*!< 0x00200000 */
+#define DMA_HISR_TCIF6           DMA_HISR_TCIF6_Msk                            
+#define DMA_HISR_HTIF6_Pos       (20U)                                         
+#define DMA_HISR_HTIF6_Msk       (0x1UL << DMA_HISR_HTIF6_Pos)                  /*!< 0x00100000 */
+#define DMA_HISR_HTIF6           DMA_HISR_HTIF6_Msk                            
+#define DMA_HISR_TEIF6_Pos       (19U)                                         
+#define DMA_HISR_TEIF6_Msk       (0x1UL << DMA_HISR_TEIF6_Pos)                  /*!< 0x00080000 */
+#define DMA_HISR_TEIF6           DMA_HISR_TEIF6_Msk                            
+#define DMA_HISR_DMEIF6_Pos      (18U)                                         
+#define DMA_HISR_DMEIF6_Msk      (0x1UL << DMA_HISR_DMEIF6_Pos)                 /*!< 0x00040000 */
+#define DMA_HISR_DMEIF6          DMA_HISR_DMEIF6_Msk                           
+#define DMA_HISR_FEIF6_Pos       (16U)                                         
+#define DMA_HISR_FEIF6_Msk       (0x1UL << DMA_HISR_FEIF6_Pos)                  /*!< 0x00010000 */
+#define DMA_HISR_FEIF6           DMA_HISR_FEIF6_Msk                            
+#define DMA_HISR_TCIF5_Pos       (11U)                                         
+#define DMA_HISR_TCIF5_Msk       (0x1UL << DMA_HISR_TCIF5_Pos)                  /*!< 0x00000800 */
+#define DMA_HISR_TCIF5           DMA_HISR_TCIF5_Msk                            
+#define DMA_HISR_HTIF5_Pos       (10U)                                         
+#define DMA_HISR_HTIF5_Msk       (0x1UL << DMA_HISR_HTIF5_Pos)                  /*!< 0x00000400 */
+#define DMA_HISR_HTIF5           DMA_HISR_HTIF5_Msk                            
+#define DMA_HISR_TEIF5_Pos       (9U)                                          
+#define DMA_HISR_TEIF5_Msk       (0x1UL << DMA_HISR_TEIF5_Pos)                  /*!< 0x00000200 */
+#define DMA_HISR_TEIF5           DMA_HISR_TEIF5_Msk                            
+#define DMA_HISR_DMEIF5_Pos      (8U)                                          
+#define DMA_HISR_DMEIF5_Msk      (0x1UL << DMA_HISR_DMEIF5_Pos)                 /*!< 0x00000100 */
+#define DMA_HISR_DMEIF5          DMA_HISR_DMEIF5_Msk                           
+#define DMA_HISR_FEIF5_Pos       (6U)                                          
+#define DMA_HISR_FEIF5_Msk       (0x1UL << DMA_HISR_FEIF5_Pos)                  /*!< 0x00000040 */
+#define DMA_HISR_FEIF5           DMA_HISR_FEIF5_Msk                            
+#define DMA_HISR_TCIF4_Pos       (5U)                                          
+#define DMA_HISR_TCIF4_Msk       (0x1UL << DMA_HISR_TCIF4_Pos)                  /*!< 0x00000020 */
+#define DMA_HISR_TCIF4           DMA_HISR_TCIF4_Msk                            
+#define DMA_HISR_HTIF4_Pos       (4U)                                          
+#define DMA_HISR_HTIF4_Msk       (0x1UL << DMA_HISR_HTIF4_Pos)                  /*!< 0x00000010 */
+#define DMA_HISR_HTIF4           DMA_HISR_HTIF4_Msk                            
+#define DMA_HISR_TEIF4_Pos       (3U)                                          
+#define DMA_HISR_TEIF4_Msk       (0x1UL << DMA_HISR_TEIF4_Pos)                  /*!< 0x00000008 */
+#define DMA_HISR_TEIF4           DMA_HISR_TEIF4_Msk                            
+#define DMA_HISR_DMEIF4_Pos      (2U)                                          
+#define DMA_HISR_DMEIF4_Msk      (0x1UL << DMA_HISR_DMEIF4_Pos)                 /*!< 0x00000004 */
+#define DMA_HISR_DMEIF4          DMA_HISR_DMEIF4_Msk                           
+#define DMA_HISR_FEIF4_Pos       (0U)                                          
+#define DMA_HISR_FEIF4_Msk       (0x1UL << DMA_HISR_FEIF4_Pos)                  /*!< 0x00000001 */
+#define DMA_HISR_FEIF4           DMA_HISR_FEIF4_Msk                            
+
+/********************  Bits definition for DMA_LIFCR register  ****************/ 
+#define DMA_LIFCR_CTCIF3_Pos     (27U)                                         
+#define DMA_LIFCR_CTCIF3_Msk     (0x1UL << DMA_LIFCR_CTCIF3_Pos)                /*!< 0x08000000 */
+#define DMA_LIFCR_CTCIF3         DMA_LIFCR_CTCIF3_Msk                          
+#define DMA_LIFCR_CHTIF3_Pos     (26U)                                         
+#define DMA_LIFCR_CHTIF3_Msk     (0x1UL << DMA_LIFCR_CHTIF3_Pos)                /*!< 0x04000000 */
+#define DMA_LIFCR_CHTIF3         DMA_LIFCR_CHTIF3_Msk                          
+#define DMA_LIFCR_CTEIF3_Pos     (25U)                                         
+#define DMA_LIFCR_CTEIF3_Msk     (0x1UL << DMA_LIFCR_CTEIF3_Pos)                /*!< 0x02000000 */
+#define DMA_LIFCR_CTEIF3         DMA_LIFCR_CTEIF3_Msk                          
+#define DMA_LIFCR_CDMEIF3_Pos    (24U)                                         
+#define DMA_LIFCR_CDMEIF3_Msk    (0x1UL << DMA_LIFCR_CDMEIF3_Pos)               /*!< 0x01000000 */
+#define DMA_LIFCR_CDMEIF3        DMA_LIFCR_CDMEIF3_Msk                         
+#define DMA_LIFCR_CFEIF3_Pos     (22U)                                         
+#define DMA_LIFCR_CFEIF3_Msk     (0x1UL << DMA_LIFCR_CFEIF3_Pos)                /*!< 0x00400000 */
+#define DMA_LIFCR_CFEIF3         DMA_LIFCR_CFEIF3_Msk                          
+#define DMA_LIFCR_CTCIF2_Pos     (21U)                                         
+#define DMA_LIFCR_CTCIF2_Msk     (0x1UL << DMA_LIFCR_CTCIF2_Pos)                /*!< 0x00200000 */
+#define DMA_LIFCR_CTCIF2         DMA_LIFCR_CTCIF2_Msk                          
+#define DMA_LIFCR_CHTIF2_Pos     (20U)                                         
+#define DMA_LIFCR_CHTIF2_Msk     (0x1UL << DMA_LIFCR_CHTIF2_Pos)                /*!< 0x00100000 */
+#define DMA_LIFCR_CHTIF2         DMA_LIFCR_CHTIF2_Msk                          
+#define DMA_LIFCR_CTEIF2_Pos     (19U)                                         
+#define DMA_LIFCR_CTEIF2_Msk     (0x1UL << DMA_LIFCR_CTEIF2_Pos)                /*!< 0x00080000 */
+#define DMA_LIFCR_CTEIF2         DMA_LIFCR_CTEIF2_Msk                          
+#define DMA_LIFCR_CDMEIF2_Pos    (18U)                                         
+#define DMA_LIFCR_CDMEIF2_Msk    (0x1UL << DMA_LIFCR_CDMEIF2_Pos)               /*!< 0x00040000 */
+#define DMA_LIFCR_CDMEIF2        DMA_LIFCR_CDMEIF2_Msk                         
+#define DMA_LIFCR_CFEIF2_Pos     (16U)                                         
+#define DMA_LIFCR_CFEIF2_Msk     (0x1UL << DMA_LIFCR_CFEIF2_Pos)                /*!< 0x00010000 */
+#define DMA_LIFCR_CFEIF2         DMA_LIFCR_CFEIF2_Msk                          
+#define DMA_LIFCR_CTCIF1_Pos     (11U)                                         
+#define DMA_LIFCR_CTCIF1_Msk     (0x1UL << DMA_LIFCR_CTCIF1_Pos)                /*!< 0x00000800 */
+#define DMA_LIFCR_CTCIF1         DMA_LIFCR_CTCIF1_Msk                          
+#define DMA_LIFCR_CHTIF1_Pos     (10U)                                         
+#define DMA_LIFCR_CHTIF1_Msk     (0x1UL << DMA_LIFCR_CHTIF1_Pos)                /*!< 0x00000400 */
+#define DMA_LIFCR_CHTIF1         DMA_LIFCR_CHTIF1_Msk                          
+#define DMA_LIFCR_CTEIF1_Pos     (9U)                                          
+#define DMA_LIFCR_CTEIF1_Msk     (0x1UL << DMA_LIFCR_CTEIF1_Pos)                /*!< 0x00000200 */
+#define DMA_LIFCR_CTEIF1         DMA_LIFCR_CTEIF1_Msk                          
+#define DMA_LIFCR_CDMEIF1_Pos    (8U)                                          
+#define DMA_LIFCR_CDMEIF1_Msk    (0x1UL << DMA_LIFCR_CDMEIF1_Pos)               /*!< 0x00000100 */
+#define DMA_LIFCR_CDMEIF1        DMA_LIFCR_CDMEIF1_Msk                         
+#define DMA_LIFCR_CFEIF1_Pos     (6U)                                          
+#define DMA_LIFCR_CFEIF1_Msk     (0x1UL << DMA_LIFCR_CFEIF1_Pos)                /*!< 0x00000040 */
+#define DMA_LIFCR_CFEIF1         DMA_LIFCR_CFEIF1_Msk                          
+#define DMA_LIFCR_CTCIF0_Pos     (5U)                                          
+#define DMA_LIFCR_CTCIF0_Msk     (0x1UL << DMA_LIFCR_CTCIF0_Pos)                /*!< 0x00000020 */
+#define DMA_LIFCR_CTCIF0         DMA_LIFCR_CTCIF0_Msk                          
+#define DMA_LIFCR_CHTIF0_Pos     (4U)                                          
+#define DMA_LIFCR_CHTIF0_Msk     (0x1UL << DMA_LIFCR_CHTIF0_Pos)                /*!< 0x00000010 */
+#define DMA_LIFCR_CHTIF0         DMA_LIFCR_CHTIF0_Msk                          
+#define DMA_LIFCR_CTEIF0_Pos     (3U)                                          
+#define DMA_LIFCR_CTEIF0_Msk     (0x1UL << DMA_LIFCR_CTEIF0_Pos)                /*!< 0x00000008 */
+#define DMA_LIFCR_CTEIF0         DMA_LIFCR_CTEIF0_Msk                          
+#define DMA_LIFCR_CDMEIF0_Pos    (2U)                                          
+#define DMA_LIFCR_CDMEIF0_Msk    (0x1UL << DMA_LIFCR_CDMEIF0_Pos)               /*!< 0x00000004 */
+#define DMA_LIFCR_CDMEIF0        DMA_LIFCR_CDMEIF0_Msk                         
+#define DMA_LIFCR_CFEIF0_Pos     (0U)                                          
+#define DMA_LIFCR_CFEIF0_Msk     (0x1UL << DMA_LIFCR_CFEIF0_Pos)                /*!< 0x00000001 */
+#define DMA_LIFCR_CFEIF0         DMA_LIFCR_CFEIF0_Msk                          
+
+/********************  Bits definition for DMA_HIFCR  register  ****************/ 
+#define DMA_HIFCR_CTCIF7_Pos     (27U)                                         
+#define DMA_HIFCR_CTCIF7_Msk     (0x1UL << DMA_HIFCR_CTCIF7_Pos)                /*!< 0x08000000 */
+#define DMA_HIFCR_CTCIF7         DMA_HIFCR_CTCIF7_Msk                          
+#define DMA_HIFCR_CHTIF7_Pos     (26U)                                         
+#define DMA_HIFCR_CHTIF7_Msk     (0x1UL << DMA_HIFCR_CHTIF7_Pos)                /*!< 0x04000000 */
+#define DMA_HIFCR_CHTIF7         DMA_HIFCR_CHTIF7_Msk                          
+#define DMA_HIFCR_CTEIF7_Pos     (25U)                                         
+#define DMA_HIFCR_CTEIF7_Msk     (0x1UL << DMA_HIFCR_CTEIF7_Pos)                /*!< 0x02000000 */
+#define DMA_HIFCR_CTEIF7         DMA_HIFCR_CTEIF7_Msk                          
+#define DMA_HIFCR_CDMEIF7_Pos    (24U)                                         
+#define DMA_HIFCR_CDMEIF7_Msk    (0x1UL << DMA_HIFCR_CDMEIF7_Pos)               /*!< 0x01000000 */
+#define DMA_HIFCR_CDMEIF7        DMA_HIFCR_CDMEIF7_Msk                         
+#define DMA_HIFCR_CFEIF7_Pos     (22U)                                         
+#define DMA_HIFCR_CFEIF7_Msk     (0x1UL << DMA_HIFCR_CFEIF7_Pos)                /*!< 0x00400000 */
+#define DMA_HIFCR_CFEIF7         DMA_HIFCR_CFEIF7_Msk                          
+#define DMA_HIFCR_CTCIF6_Pos     (21U)                                         
+#define DMA_HIFCR_CTCIF6_Msk     (0x1UL << DMA_HIFCR_CTCIF6_Pos)                /*!< 0x00200000 */
+#define DMA_HIFCR_CTCIF6         DMA_HIFCR_CTCIF6_Msk                          
+#define DMA_HIFCR_CHTIF6_Pos     (20U)                                         
+#define DMA_HIFCR_CHTIF6_Msk     (0x1UL << DMA_HIFCR_CHTIF6_Pos)                /*!< 0x00100000 */
+#define DMA_HIFCR_CHTIF6         DMA_HIFCR_CHTIF6_Msk                          
+#define DMA_HIFCR_CTEIF6_Pos     (19U)                                         
+#define DMA_HIFCR_CTEIF6_Msk     (0x1UL << DMA_HIFCR_CTEIF6_Pos)                /*!< 0x00080000 */
+#define DMA_HIFCR_CTEIF6         DMA_HIFCR_CTEIF6_Msk                          
+#define DMA_HIFCR_CDMEIF6_Pos    (18U)                                         
+#define DMA_HIFCR_CDMEIF6_Msk    (0x1UL << DMA_HIFCR_CDMEIF6_Pos)               /*!< 0x00040000 */
+#define DMA_HIFCR_CDMEIF6        DMA_HIFCR_CDMEIF6_Msk                         
+#define DMA_HIFCR_CFEIF6_Pos     (16U)                                         
+#define DMA_HIFCR_CFEIF6_Msk     (0x1UL << DMA_HIFCR_CFEIF6_Pos)                /*!< 0x00010000 */
+#define DMA_HIFCR_CFEIF6         DMA_HIFCR_CFEIF6_Msk                          
+#define DMA_HIFCR_CTCIF5_Pos     (11U)                                         
+#define DMA_HIFCR_CTCIF5_Msk     (0x1UL << DMA_HIFCR_CTCIF5_Pos)                /*!< 0x00000800 */
+#define DMA_HIFCR_CTCIF5         DMA_HIFCR_CTCIF5_Msk                          
+#define DMA_HIFCR_CHTIF5_Pos     (10U)                                         
+#define DMA_HIFCR_CHTIF5_Msk     (0x1UL << DMA_HIFCR_CHTIF5_Pos)                /*!< 0x00000400 */
+#define DMA_HIFCR_CHTIF5         DMA_HIFCR_CHTIF5_Msk                          
+#define DMA_HIFCR_CTEIF5_Pos     (9U)                                          
+#define DMA_HIFCR_CTEIF5_Msk     (0x1UL << DMA_HIFCR_CTEIF5_Pos)                /*!< 0x00000200 */
+#define DMA_HIFCR_CTEIF5         DMA_HIFCR_CTEIF5_Msk                          
+#define DMA_HIFCR_CDMEIF5_Pos    (8U)                                          
+#define DMA_HIFCR_CDMEIF5_Msk    (0x1UL << DMA_HIFCR_CDMEIF5_Pos)               /*!< 0x00000100 */
+#define DMA_HIFCR_CDMEIF5        DMA_HIFCR_CDMEIF5_Msk                         
+#define DMA_HIFCR_CFEIF5_Pos     (6U)                                          
+#define DMA_HIFCR_CFEIF5_Msk     (0x1UL << DMA_HIFCR_CFEIF5_Pos)                /*!< 0x00000040 */
+#define DMA_HIFCR_CFEIF5         DMA_HIFCR_CFEIF5_Msk                          
+#define DMA_HIFCR_CTCIF4_Pos     (5U)                                          
+#define DMA_HIFCR_CTCIF4_Msk     (0x1UL << DMA_HIFCR_CTCIF4_Pos)                /*!< 0x00000020 */
+#define DMA_HIFCR_CTCIF4         DMA_HIFCR_CTCIF4_Msk                          
+#define DMA_HIFCR_CHTIF4_Pos     (4U)                                          
+#define DMA_HIFCR_CHTIF4_Msk     (0x1UL << DMA_HIFCR_CHTIF4_Pos)                /*!< 0x00000010 */
+#define DMA_HIFCR_CHTIF4         DMA_HIFCR_CHTIF4_Msk                          
+#define DMA_HIFCR_CTEIF4_Pos     (3U)                                          
+#define DMA_HIFCR_CTEIF4_Msk     (0x1UL << DMA_HIFCR_CTEIF4_Pos)                /*!< 0x00000008 */
+#define DMA_HIFCR_CTEIF4         DMA_HIFCR_CTEIF4_Msk                          
+#define DMA_HIFCR_CDMEIF4_Pos    (2U)                                          
+#define DMA_HIFCR_CDMEIF4_Msk    (0x1UL << DMA_HIFCR_CDMEIF4_Pos)               /*!< 0x00000004 */
+#define DMA_HIFCR_CDMEIF4        DMA_HIFCR_CDMEIF4_Msk                         
+#define DMA_HIFCR_CFEIF4_Pos     (0U)                                          
+#define DMA_HIFCR_CFEIF4_Msk     (0x1UL << DMA_HIFCR_CFEIF4_Pos)                /*!< 0x00000001 */
+#define DMA_HIFCR_CFEIF4         DMA_HIFCR_CFEIF4_Msk                          
+
+/******************  Bit definition for DMA_SxPAR register  ********************/
+#define DMA_SxPAR_PA_Pos         (0U)                                          
+#define DMA_SxPAR_PA_Msk         (0xFFFFFFFFUL << DMA_SxPAR_PA_Pos)             /*!< 0xFFFFFFFF */
+#define DMA_SxPAR_PA             DMA_SxPAR_PA_Msk                              /*!< Peripheral Address */
+
+/******************  Bit definition for DMA_SxM0AR register  ********************/
+#define DMA_SxM0AR_M0A_Pos       (0U)                                          
+#define DMA_SxM0AR_M0A_Msk       (0xFFFFFFFFUL << DMA_SxM0AR_M0A_Pos)           /*!< 0xFFFFFFFF */
+#define DMA_SxM0AR_M0A           DMA_SxM0AR_M0A_Msk                            /*!< Memory Address */
+
+/******************  Bit definition for DMA_SxM1AR register  ********************/
+#define DMA_SxM1AR_M1A_Pos       (0U)                                          
+#define DMA_SxM1AR_M1A_Msk       (0xFFFFFFFFUL << DMA_SxM1AR_M1A_Pos)           /*!< 0xFFFFFFFF */
+#define DMA_SxM1AR_M1A           DMA_SxM1AR_M1A_Msk                            /*!< Memory Address */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                         AHB Master DMA2D Controller (DMA2D)                */
+/*                                                                            */
+/******************************************************************************/
+
+/********************  Bit definition for DMA2D_CR register  ******************/
+
+#define DMA2D_CR_START_Pos         (0U)                                        
+#define DMA2D_CR_START_Msk         (0x1UL << DMA2D_CR_START_Pos)                /*!< 0x00000001 */
+#define DMA2D_CR_START             DMA2D_CR_START_Msk                          /*!< Start transfer */
+#define DMA2D_CR_SUSP_Pos          (1U)                                        
+#define DMA2D_CR_SUSP_Msk          (0x1UL << DMA2D_CR_SUSP_Pos)                 /*!< 0x00000002 */
+#define DMA2D_CR_SUSP              DMA2D_CR_SUSP_Msk                           /*!< Suspend transfer */
+#define DMA2D_CR_ABORT_Pos         (2U)                                        
+#define DMA2D_CR_ABORT_Msk         (0x1UL << DMA2D_CR_ABORT_Pos)                /*!< 0x00000004 */
+#define DMA2D_CR_ABORT             DMA2D_CR_ABORT_Msk                          /*!< Abort transfer */
+#define DMA2D_CR_TEIE_Pos          (8U)                                        
+#define DMA2D_CR_TEIE_Msk          (0x1UL << DMA2D_CR_TEIE_Pos)                 /*!< 0x00000100 */
+#define DMA2D_CR_TEIE              DMA2D_CR_TEIE_Msk                           /*!< Transfer Error Interrupt Enable */
+#define DMA2D_CR_TCIE_Pos          (9U)                                        
+#define DMA2D_CR_TCIE_Msk          (0x1UL << DMA2D_CR_TCIE_Pos)                 /*!< 0x00000200 */
+#define DMA2D_CR_TCIE              DMA2D_CR_TCIE_Msk                           /*!< Transfer Complete Interrupt Enable */
+#define DMA2D_CR_TWIE_Pos          (10U)                                       
+#define DMA2D_CR_TWIE_Msk          (0x1UL << DMA2D_CR_TWIE_Pos)                 /*!< 0x00000400 */
+#define DMA2D_CR_TWIE              DMA2D_CR_TWIE_Msk                           /*!< Transfer Watermark Interrupt Enable */
+#define DMA2D_CR_CAEIE_Pos         (11U)                                       
+#define DMA2D_CR_CAEIE_Msk         (0x1UL << DMA2D_CR_CAEIE_Pos)                /*!< 0x00000800 */
+#define DMA2D_CR_CAEIE             DMA2D_CR_CAEIE_Msk                          /*!< CLUT Access Error Interrupt Enable */
+#define DMA2D_CR_CTCIE_Pos         (12U)                                       
+#define DMA2D_CR_CTCIE_Msk         (0x1UL << DMA2D_CR_CTCIE_Pos)                /*!< 0x00001000 */
+#define DMA2D_CR_CTCIE             DMA2D_CR_CTCIE_Msk                          /*!< CLUT Transfer Complete Interrupt Enable */
+#define DMA2D_CR_CEIE_Pos          (13U)                                       
+#define DMA2D_CR_CEIE_Msk          (0x1UL << DMA2D_CR_CEIE_Pos)                 /*!< 0x00002000 */
+#define DMA2D_CR_CEIE              DMA2D_CR_CEIE_Msk                           /*!< Configuration Error Interrupt Enable */
+#define DMA2D_CR_MODE_Pos          (16U)                                       
+#define DMA2D_CR_MODE_Msk          (0x3UL << DMA2D_CR_MODE_Pos)                 /*!< 0x00030000 */
+#define DMA2D_CR_MODE              DMA2D_CR_MODE_Msk                           /*!< DMA2D Mode[1:0] */
+#define DMA2D_CR_MODE_0            (0x1UL << DMA2D_CR_MODE_Pos)                 /*!< 0x00010000 */
+#define DMA2D_CR_MODE_1            (0x2UL << DMA2D_CR_MODE_Pos)                 /*!< 0x00020000 */
+
+/********************  Bit definition for DMA2D_ISR register  *****************/
+
+#define DMA2D_ISR_TEIF_Pos         (0U)                                        
+#define DMA2D_ISR_TEIF_Msk         (0x1UL << DMA2D_ISR_TEIF_Pos)                /*!< 0x00000001 */
+#define DMA2D_ISR_TEIF             DMA2D_ISR_TEIF_Msk                          /*!< Transfer Error Interrupt Flag */
+#define DMA2D_ISR_TCIF_Pos         (1U)                                        
+#define DMA2D_ISR_TCIF_Msk         (0x1UL << DMA2D_ISR_TCIF_Pos)                /*!< 0x00000002 */
+#define DMA2D_ISR_TCIF             DMA2D_ISR_TCIF_Msk                          /*!< Transfer Complete Interrupt Flag */
+#define DMA2D_ISR_TWIF_Pos         (2U)                                        
+#define DMA2D_ISR_TWIF_Msk         (0x1UL << DMA2D_ISR_TWIF_Pos)                /*!< 0x00000004 */
+#define DMA2D_ISR_TWIF             DMA2D_ISR_TWIF_Msk                          /*!< Transfer Watermark Interrupt Flag */
+#define DMA2D_ISR_CAEIF_Pos        (3U)                                        
+#define DMA2D_ISR_CAEIF_Msk        (0x1UL << DMA2D_ISR_CAEIF_Pos)               /*!< 0x00000008 */
+#define DMA2D_ISR_CAEIF            DMA2D_ISR_CAEIF_Msk                         /*!< CLUT Access Error Interrupt Flag */
+#define DMA2D_ISR_CTCIF_Pos        (4U)                                        
+#define DMA2D_ISR_CTCIF_Msk        (0x1UL << DMA2D_ISR_CTCIF_Pos)               /*!< 0x00000010 */
+#define DMA2D_ISR_CTCIF            DMA2D_ISR_CTCIF_Msk                         /*!< CLUT Transfer Complete Interrupt Flag */
+#define DMA2D_ISR_CEIF_Pos         (5U)                                        
+#define DMA2D_ISR_CEIF_Msk         (0x1UL << DMA2D_ISR_CEIF_Pos)                /*!< 0x00000020 */
+#define DMA2D_ISR_CEIF             DMA2D_ISR_CEIF_Msk                          /*!< Configuration Error Interrupt Flag */
+
+/********************  Bit definition for DMA2D_IFCR register  ****************/
+
+#define DMA2D_IFCR_CTEIF_Pos       (0U)                                        
+#define DMA2D_IFCR_CTEIF_Msk       (0x1UL << DMA2D_IFCR_CTEIF_Pos)              /*!< 0x00000001 */
+#define DMA2D_IFCR_CTEIF           DMA2D_IFCR_CTEIF_Msk                        /*!< Clears Transfer Error Interrupt Flag         */
+#define DMA2D_IFCR_CTCIF_Pos       (1U)                                        
+#define DMA2D_IFCR_CTCIF_Msk       (0x1UL << DMA2D_IFCR_CTCIF_Pos)              /*!< 0x00000002 */
+#define DMA2D_IFCR_CTCIF           DMA2D_IFCR_CTCIF_Msk                        /*!< Clears Transfer Complete Interrupt Flag      */
+#define DMA2D_IFCR_CTWIF_Pos       (2U)                                        
+#define DMA2D_IFCR_CTWIF_Msk       (0x1UL << DMA2D_IFCR_CTWIF_Pos)              /*!< 0x00000004 */
+#define DMA2D_IFCR_CTWIF           DMA2D_IFCR_CTWIF_Msk                        /*!< Clears Transfer Watermark Interrupt Flag     */
+#define DMA2D_IFCR_CAECIF_Pos      (3U)                                        
+#define DMA2D_IFCR_CAECIF_Msk      (0x1UL << DMA2D_IFCR_CAECIF_Pos)             /*!< 0x00000008 */
+#define DMA2D_IFCR_CAECIF          DMA2D_IFCR_CAECIF_Msk                       /*!< Clears CLUT Access Error Interrupt Flag      */
+#define DMA2D_IFCR_CCTCIF_Pos      (4U)                                        
+#define DMA2D_IFCR_CCTCIF_Msk      (0x1UL << DMA2D_IFCR_CCTCIF_Pos)             /*!< 0x00000010 */
+#define DMA2D_IFCR_CCTCIF          DMA2D_IFCR_CCTCIF_Msk                       /*!< Clears CLUT Transfer Complete Interrupt Flag */
+#define DMA2D_IFCR_CCEIF_Pos       (5U)                                        
+#define DMA2D_IFCR_CCEIF_Msk       (0x1UL << DMA2D_IFCR_CCEIF_Pos)              /*!< 0x00000020 */
+#define DMA2D_IFCR_CCEIF           DMA2D_IFCR_CCEIF_Msk                        /*!< Clears Configuration Error Interrupt Flag    */
+
+/* Legacy defines */
+#define DMA2D_IFSR_CTEIF                   DMA2D_IFCR_CTEIF                     /*!< Clears Transfer Error Interrupt Flag         */
+#define DMA2D_IFSR_CTCIF                   DMA2D_IFCR_CTCIF                     /*!< Clears Transfer Complete Interrupt Flag      */
+#define DMA2D_IFSR_CTWIF                   DMA2D_IFCR_CTWIF                     /*!< Clears Transfer Watermark Interrupt Flag     */
+#define DMA2D_IFSR_CCAEIF                  DMA2D_IFCR_CAECIF                    /*!< Clears CLUT Access Error Interrupt Flag      */
+#define DMA2D_IFSR_CCTCIF                  DMA2D_IFCR_CCTCIF                    /*!< Clears CLUT Transfer Complete Interrupt Flag */
+#define DMA2D_IFSR_CCEIF                   DMA2D_IFCR_CCEIF                     /*!< Clears Configuration Error Interrupt Flag    */
+
+/********************  Bit definition for DMA2D_FGMAR register  ***************/
+
+#define DMA2D_FGMAR_MA_Pos         (0U)                                        
+#define DMA2D_FGMAR_MA_Msk         (0xFFFFFFFFUL << DMA2D_FGMAR_MA_Pos)         /*!< 0xFFFFFFFF */
+#define DMA2D_FGMAR_MA             DMA2D_FGMAR_MA_Msk                          /*!< Memory Address */
+
+/********************  Bit definition for DMA2D_FGOR register  ****************/
+
+#define DMA2D_FGOR_LO_Pos          (0U)                                        
+#define DMA2D_FGOR_LO_Msk          (0x3FFFUL << DMA2D_FGOR_LO_Pos)              /*!< 0x00003FFF */
+#define DMA2D_FGOR_LO              DMA2D_FGOR_LO_Msk                           /*!< Line Offset */
+
+/********************  Bit definition for DMA2D_BGMAR register  ***************/
+
+#define DMA2D_BGMAR_MA_Pos         (0U)                                        
+#define DMA2D_BGMAR_MA_Msk         (0xFFFFFFFFUL << DMA2D_BGMAR_MA_Pos)         /*!< 0xFFFFFFFF */
+#define DMA2D_BGMAR_MA             DMA2D_BGMAR_MA_Msk                          /*!< Memory Address */
+
+/********************  Bit definition for DMA2D_BGOR register  ****************/
+
+#define DMA2D_BGOR_LO_Pos          (0U)                                        
+#define DMA2D_BGOR_LO_Msk          (0x3FFFUL << DMA2D_BGOR_LO_Pos)              /*!< 0x00003FFF */
+#define DMA2D_BGOR_LO              DMA2D_BGOR_LO_Msk                           /*!< Line Offset */
+
+/********************  Bit definition for DMA2D_FGPFCCR register  *************/
+
+#define DMA2D_FGPFCCR_CM_Pos       (0U)                                        
+#define DMA2D_FGPFCCR_CM_Msk       (0xFUL << DMA2D_FGPFCCR_CM_Pos)              /*!< 0x0000000F */
+#define DMA2D_FGPFCCR_CM           DMA2D_FGPFCCR_CM_Msk                        /*!< Input color mode CM[3:0] */
+#define DMA2D_FGPFCCR_CM_0         (0x1UL << DMA2D_FGPFCCR_CM_Pos)              /*!< 0x00000001 */
+#define DMA2D_FGPFCCR_CM_1         (0x2UL << DMA2D_FGPFCCR_CM_Pos)              /*!< 0x00000002 */
+#define DMA2D_FGPFCCR_CM_2         (0x4UL << DMA2D_FGPFCCR_CM_Pos)              /*!< 0x00000004 */
+#define DMA2D_FGPFCCR_CM_3         (0x8UL << DMA2D_FGPFCCR_CM_Pos)              /*!< 0x00000008 */
+#define DMA2D_FGPFCCR_CCM_Pos      (4U)                                        
+#define DMA2D_FGPFCCR_CCM_Msk      (0x1UL << DMA2D_FGPFCCR_CCM_Pos)             /*!< 0x00000010 */
+#define DMA2D_FGPFCCR_CCM          DMA2D_FGPFCCR_CCM_Msk                       /*!< CLUT Color mode */
+#define DMA2D_FGPFCCR_START_Pos    (5U)                                        
+#define DMA2D_FGPFCCR_START_Msk    (0x1UL << DMA2D_FGPFCCR_START_Pos)           /*!< 0x00000020 */
+#define DMA2D_FGPFCCR_START        DMA2D_FGPFCCR_START_Msk                     /*!< Start */
+#define DMA2D_FGPFCCR_CS_Pos       (8U)                                        
+#define DMA2D_FGPFCCR_CS_Msk       (0xFFUL << DMA2D_FGPFCCR_CS_Pos)             /*!< 0x0000FF00 */
+#define DMA2D_FGPFCCR_CS           DMA2D_FGPFCCR_CS_Msk                        /*!< CLUT size */
+#define DMA2D_FGPFCCR_AM_Pos       (16U)                                       
+#define DMA2D_FGPFCCR_AM_Msk       (0x3UL << DMA2D_FGPFCCR_AM_Pos)              /*!< 0x00030000 */
+#define DMA2D_FGPFCCR_AM           DMA2D_FGPFCCR_AM_Msk                        /*!< Alpha mode AM[1:0] */
+#define DMA2D_FGPFCCR_AM_0         (0x1UL << DMA2D_FGPFCCR_AM_Pos)              /*!< 0x00010000 */
+#define DMA2D_FGPFCCR_AM_1         (0x2UL << DMA2D_FGPFCCR_AM_Pos)              /*!< 0x00020000 */
+#define DMA2D_FGPFCCR_ALPHA_Pos    (24U)                                       
+#define DMA2D_FGPFCCR_ALPHA_Msk    (0xFFUL << DMA2D_FGPFCCR_ALPHA_Pos)          /*!< 0xFF000000 */
+#define DMA2D_FGPFCCR_ALPHA        DMA2D_FGPFCCR_ALPHA_Msk                     /*!< Alpha value */
+
+/********************  Bit definition for DMA2D_FGCOLR register  **************/
+
+#define DMA2D_FGCOLR_BLUE_Pos      (0U)                                        
+#define DMA2D_FGCOLR_BLUE_Msk      (0xFFUL << DMA2D_FGCOLR_BLUE_Pos)            /*!< 0x000000FF */
+#define DMA2D_FGCOLR_BLUE          DMA2D_FGCOLR_BLUE_Msk                       /*!< Blue Value */
+#define DMA2D_FGCOLR_GREEN_Pos     (8U)                                        
+#define DMA2D_FGCOLR_GREEN_Msk     (0xFFUL << DMA2D_FGCOLR_GREEN_Pos)           /*!< 0x0000FF00 */
+#define DMA2D_FGCOLR_GREEN         DMA2D_FGCOLR_GREEN_Msk                      /*!< Green Value */
+#define DMA2D_FGCOLR_RED_Pos       (16U)                                       
+#define DMA2D_FGCOLR_RED_Msk       (0xFFUL << DMA2D_FGCOLR_RED_Pos)             /*!< 0x00FF0000 */
+#define DMA2D_FGCOLR_RED           DMA2D_FGCOLR_RED_Msk                        /*!< Red Value */   
+
+/********************  Bit definition for DMA2D_BGPFCCR register  *************/
+
+#define DMA2D_BGPFCCR_CM_Pos       (0U)                                        
+#define DMA2D_BGPFCCR_CM_Msk       (0xFUL << DMA2D_BGPFCCR_CM_Pos)              /*!< 0x0000000F */
+#define DMA2D_BGPFCCR_CM           DMA2D_BGPFCCR_CM_Msk                        /*!< Input color mode CM[3:0] */
+#define DMA2D_BGPFCCR_CM_0         (0x1UL << DMA2D_BGPFCCR_CM_Pos)              /*!< 0x00000001 */
+#define DMA2D_BGPFCCR_CM_1         (0x2UL << DMA2D_BGPFCCR_CM_Pos)              /*!< 0x00000002 */
+#define DMA2D_BGPFCCR_CM_2         (0x4UL << DMA2D_BGPFCCR_CM_Pos)              /*!< 0x00000004 */
+#define DMA2D_BGPFCCR_CM_3         0x00000008U                                 /*!< Input color mode CM bit 3 */
+#define DMA2D_BGPFCCR_CCM_Pos      (4U)                                        
+#define DMA2D_BGPFCCR_CCM_Msk      (0x1UL << DMA2D_BGPFCCR_CCM_Pos)             /*!< 0x00000010 */
+#define DMA2D_BGPFCCR_CCM          DMA2D_BGPFCCR_CCM_Msk                       /*!< CLUT Color mode */
+#define DMA2D_BGPFCCR_START_Pos    (5U)                                        
+#define DMA2D_BGPFCCR_START_Msk    (0x1UL << DMA2D_BGPFCCR_START_Pos)           /*!< 0x00000020 */
+#define DMA2D_BGPFCCR_START        DMA2D_BGPFCCR_START_Msk                     /*!< Start */
+#define DMA2D_BGPFCCR_CS_Pos       (8U)                                        
+#define DMA2D_BGPFCCR_CS_Msk       (0xFFUL << DMA2D_BGPFCCR_CS_Pos)             /*!< 0x0000FF00 */
+#define DMA2D_BGPFCCR_CS           DMA2D_BGPFCCR_CS_Msk                        /*!< CLUT size */
+#define DMA2D_BGPFCCR_AM_Pos       (16U)                                       
+#define DMA2D_BGPFCCR_AM_Msk       (0x3UL << DMA2D_BGPFCCR_AM_Pos)              /*!< 0x00030000 */
+#define DMA2D_BGPFCCR_AM           DMA2D_BGPFCCR_AM_Msk                        /*!< Alpha mode AM[1:0] */
+#define DMA2D_BGPFCCR_AM_0         (0x1UL << DMA2D_BGPFCCR_AM_Pos)              /*!< 0x00010000 */
+#define DMA2D_BGPFCCR_AM_1         (0x2UL << DMA2D_BGPFCCR_AM_Pos)              /*!< 0x00020000 */
+#define DMA2D_BGPFCCR_ALPHA_Pos    (24U)                                       
+#define DMA2D_BGPFCCR_ALPHA_Msk    (0xFFUL << DMA2D_BGPFCCR_ALPHA_Pos)          /*!< 0xFF000000 */
+#define DMA2D_BGPFCCR_ALPHA        DMA2D_BGPFCCR_ALPHA_Msk                     /*!< background Input Alpha value */
+
+/********************  Bit definition for DMA2D_BGCOLR register  **************/
+
+#define DMA2D_BGCOLR_BLUE_Pos      (0U)                                        
+#define DMA2D_BGCOLR_BLUE_Msk      (0xFFUL << DMA2D_BGCOLR_BLUE_Pos)            /*!< 0x000000FF */
+#define DMA2D_BGCOLR_BLUE          DMA2D_BGCOLR_BLUE_Msk                       /*!< Blue Value */
+#define DMA2D_BGCOLR_GREEN_Pos     (8U)                                        
+#define DMA2D_BGCOLR_GREEN_Msk     (0xFFUL << DMA2D_BGCOLR_GREEN_Pos)           /*!< 0x0000FF00 */
+#define DMA2D_BGCOLR_GREEN         DMA2D_BGCOLR_GREEN_Msk                      /*!< Green Value */
+#define DMA2D_BGCOLR_RED_Pos       (16U)                                       
+#define DMA2D_BGCOLR_RED_Msk       (0xFFUL << DMA2D_BGCOLR_RED_Pos)             /*!< 0x00FF0000 */
+#define DMA2D_BGCOLR_RED           DMA2D_BGCOLR_RED_Msk                        /*!< Red Value */
+
+/********************  Bit definition for DMA2D_FGCMAR register  **************/
+
+#define DMA2D_FGCMAR_MA_Pos        (0U)                                        
+#define DMA2D_FGCMAR_MA_Msk        (0xFFFFFFFFUL << DMA2D_FGCMAR_MA_Pos)        /*!< 0xFFFFFFFF */
+#define DMA2D_FGCMAR_MA            DMA2D_FGCMAR_MA_Msk                         /*!< Memory Address */
+
+/********************  Bit definition for DMA2D_BGCMAR register  **************/
+
+#define DMA2D_BGCMAR_MA_Pos        (0U)                                        
+#define DMA2D_BGCMAR_MA_Msk        (0xFFFFFFFFUL << DMA2D_BGCMAR_MA_Pos)        /*!< 0xFFFFFFFF */
+#define DMA2D_BGCMAR_MA            DMA2D_BGCMAR_MA_Msk                         /*!< Memory Address */
+
+/********************  Bit definition for DMA2D_OPFCCR register  **************/
+
+#define DMA2D_OPFCCR_CM_Pos        (0U)                                        
+#define DMA2D_OPFCCR_CM_Msk        (0x7UL << DMA2D_OPFCCR_CM_Pos)               /*!< 0x00000007 */
+#define DMA2D_OPFCCR_CM            DMA2D_OPFCCR_CM_Msk                         /*!< Color mode CM[2:0] */
+#define DMA2D_OPFCCR_CM_0          (0x1UL << DMA2D_OPFCCR_CM_Pos)               /*!< 0x00000001 */
+#define DMA2D_OPFCCR_CM_1          (0x2UL << DMA2D_OPFCCR_CM_Pos)               /*!< 0x00000002 */
+#define DMA2D_OPFCCR_CM_2          (0x4UL << DMA2D_OPFCCR_CM_Pos)               /*!< 0x00000004 */
+
+/********************  Bit definition for DMA2D_OCOLR register  ***************/
+
+/*!<Mode_ARGB8888/RGB888 */
+
+#define DMA2D_OCOLR_BLUE_1         0x000000FFU                                 /*!< BLUE Value */
+#define DMA2D_OCOLR_GREEN_1        0x0000FF00U                                 /*!< GREEN Value  */
+#define DMA2D_OCOLR_RED_1          0x00FF0000U                                 /*!< Red Value */
+#define DMA2D_OCOLR_ALPHA_1        0xFF000000U                                 /*!< Alpha Channel Value */
+
+/*!<Mode_RGB565 */
+#define DMA2D_OCOLR_BLUE_2         0x0000001FU                                 /*!< BLUE Value */
+#define DMA2D_OCOLR_GREEN_2        0x000007E0U                                 /*!< GREEN Value  */
+#define DMA2D_OCOLR_RED_2          0x0000F800U                                 /*!< Red Value */
+
+/*!<Mode_ARGB1555 */
+#define DMA2D_OCOLR_BLUE_3         0x0000001FU                                 /*!< BLUE Value */
+#define DMA2D_OCOLR_GREEN_3        0x000003E0U                                 /*!< GREEN Value  */
+#define DMA2D_OCOLR_RED_3          0x00007C00U                                 /*!< Red Value */
+#define DMA2D_OCOLR_ALPHA_3        0x00008000U                                 /*!< Alpha Channel Value */
+
+/*!<Mode_ARGB4444 */
+#define DMA2D_OCOLR_BLUE_4         0x0000000FU                                 /*!< BLUE Value */
+#define DMA2D_OCOLR_GREEN_4        0x000000F0U                                 /*!< GREEN Value  */
+#define DMA2D_OCOLR_RED_4          0x00000F00U                                 /*!< Red Value */
+#define DMA2D_OCOLR_ALPHA_4        0x0000F000U                                 /*!< Alpha Channel Value */
+
+/********************  Bit definition for DMA2D_OMAR register  ****************/
+
+#define DMA2D_OMAR_MA_Pos          (0U)                                        
+#define DMA2D_OMAR_MA_Msk          (0xFFFFFFFFUL << DMA2D_OMAR_MA_Pos)          /*!< 0xFFFFFFFF */
+#define DMA2D_OMAR_MA              DMA2D_OMAR_MA_Msk                           /*!< Memory Address */
+
+/********************  Bit definition for DMA2D_OOR register  *****************/
+
+#define DMA2D_OOR_LO_Pos           (0U)                                        
+#define DMA2D_OOR_LO_Msk           (0x3FFFUL << DMA2D_OOR_LO_Pos)               /*!< 0x00003FFF */
+#define DMA2D_OOR_LO               DMA2D_OOR_LO_Msk                            /*!< Line Offset */
+
+/********************  Bit definition for DMA2D_NLR register  *****************/
+
+#define DMA2D_NLR_NL_Pos           (0U)                                        
+#define DMA2D_NLR_NL_Msk           (0xFFFFUL << DMA2D_NLR_NL_Pos)               /*!< 0x0000FFFF */
+#define DMA2D_NLR_NL               DMA2D_NLR_NL_Msk                            /*!< Number of Lines */
+#define DMA2D_NLR_PL_Pos           (16U)                                       
+#define DMA2D_NLR_PL_Msk           (0x3FFFUL << DMA2D_NLR_PL_Pos)               /*!< 0x3FFF0000 */
+#define DMA2D_NLR_PL               DMA2D_NLR_PL_Msk                            /*!< Pixel per Lines */
+
+/********************  Bit definition for DMA2D_LWR register  *****************/
+
+#define DMA2D_LWR_LW_Pos           (0U)                                        
+#define DMA2D_LWR_LW_Msk           (0xFFFFUL << DMA2D_LWR_LW_Pos)               /*!< 0x0000FFFF */
+#define DMA2D_LWR_LW               DMA2D_LWR_LW_Msk                            /*!< Line Watermark */
+
+/********************  Bit definition for DMA2D_AMTCR register  ***************/
+
+#define DMA2D_AMTCR_EN_Pos         (0U)                                        
+#define DMA2D_AMTCR_EN_Msk         (0x1UL << DMA2D_AMTCR_EN_Pos)                /*!< 0x00000001 */
+#define DMA2D_AMTCR_EN             DMA2D_AMTCR_EN_Msk                          /*!< Enable */
+#define DMA2D_AMTCR_DT_Pos         (8U)                                        
+#define DMA2D_AMTCR_DT_Msk         (0xFFUL << DMA2D_AMTCR_DT_Pos)               /*!< 0x0000FF00 */
+#define DMA2D_AMTCR_DT             DMA2D_AMTCR_DT_Msk                          /*!< Dead Time */
+
+/********************  Bit definition for DMA2D_FGCLUT register  **************/
+                                                                     
+/********************  Bit definition for DMA2D_BGCLUT register  **************/
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                     Display Serial Interface (DSI)                         */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for DSI_VR register  *****************/
+#define DSI_VR_Pos                    (1U)                                     
+#define DSI_VR_Msk                    (0x18999815UL << DSI_VR_Pos)              /*!< 0x3133302A */
+#define DSI_VR                        DSI_VR_Msk                               /*!< DSI Host Version */
+
+/*******************  Bit definition for DSI_CR register  *****************/
+#define DSI_CR_EN_Pos                 (0U)                                     
+#define DSI_CR_EN_Msk                 (0x1UL << DSI_CR_EN_Pos)                  /*!< 0x00000001 */
+#define DSI_CR_EN                     DSI_CR_EN_Msk                            /*!< DSI Host power up and reset */
+
+/*******************  Bit definition for DSI_CCR register  ****************/
+#define DSI_CCR_TXECKDIV_Pos          (0U)                                     
+#define DSI_CCR_TXECKDIV_Msk          (0xFFUL << DSI_CCR_TXECKDIV_Pos)          /*!< 0x000000FF */
+#define DSI_CCR_TXECKDIV              DSI_CCR_TXECKDIV_Msk                     /*!< TX Escape Clock Division */
+#define DSI_CCR_TXECKDIV0_Pos         (0U)                                     
+#define DSI_CCR_TXECKDIV0_Msk         (0x1UL << DSI_CCR_TXECKDIV0_Pos)          /*!< 0x00000001 */
+#define DSI_CCR_TXECKDIV0             DSI_CCR_TXECKDIV0_Msk                    
+#define DSI_CCR_TXECKDIV1_Pos         (1U)                                     
+#define DSI_CCR_TXECKDIV1_Msk         (0x1UL << DSI_CCR_TXECKDIV1_Pos)          /*!< 0x00000002 */
+#define DSI_CCR_TXECKDIV1             DSI_CCR_TXECKDIV1_Msk                    
+#define DSI_CCR_TXECKDIV2_Pos         (2U)                                     
+#define DSI_CCR_TXECKDIV2_Msk         (0x1UL << DSI_CCR_TXECKDIV2_Pos)          /*!< 0x00000004 */
+#define DSI_CCR_TXECKDIV2             DSI_CCR_TXECKDIV2_Msk                    
+#define DSI_CCR_TXECKDIV3_Pos         (3U)                                     
+#define DSI_CCR_TXECKDIV3_Msk         (0x1UL << DSI_CCR_TXECKDIV3_Pos)          /*!< 0x00000008 */
+#define DSI_CCR_TXECKDIV3             DSI_CCR_TXECKDIV3_Msk                    
+#define DSI_CCR_TXECKDIV4_Pos         (4U)                                     
+#define DSI_CCR_TXECKDIV4_Msk         (0x1UL << DSI_CCR_TXECKDIV4_Pos)          /*!< 0x00000010 */
+#define DSI_CCR_TXECKDIV4             DSI_CCR_TXECKDIV4_Msk                    
+#define DSI_CCR_TXECKDIV5_Pos         (5U)                                     
+#define DSI_CCR_TXECKDIV5_Msk         (0x1UL << DSI_CCR_TXECKDIV5_Pos)          /*!< 0x00000020 */
+#define DSI_CCR_TXECKDIV5             DSI_CCR_TXECKDIV5_Msk                    
+#define DSI_CCR_TXECKDIV6_Pos         (6U)                                     
+#define DSI_CCR_TXECKDIV6_Msk         (0x1UL << DSI_CCR_TXECKDIV6_Pos)          /*!< 0x00000040 */
+#define DSI_CCR_TXECKDIV6             DSI_CCR_TXECKDIV6_Msk                    
+#define DSI_CCR_TXECKDIV7_Pos         (7U)                                     
+#define DSI_CCR_TXECKDIV7_Msk         (0x1UL << DSI_CCR_TXECKDIV7_Pos)          /*!< 0x00000080 */
+#define DSI_CCR_TXECKDIV7             DSI_CCR_TXECKDIV7_Msk                    
+
+#define DSI_CCR_TOCKDIV_Pos           (8U)                                     
+#define DSI_CCR_TOCKDIV_Msk           (0xFFUL << DSI_CCR_TOCKDIV_Pos)           /*!< 0x0000FF00 */
+#define DSI_CCR_TOCKDIV               DSI_CCR_TOCKDIV_Msk                      /*!< Timeout Clock Division */
+#define DSI_CCR_TOCKDIV0_Pos          (8U)                                     
+#define DSI_CCR_TOCKDIV0_Msk          (0x1UL << DSI_CCR_TOCKDIV0_Pos)           /*!< 0x00000100 */
+#define DSI_CCR_TOCKDIV0              DSI_CCR_TOCKDIV0_Msk                     
+#define DSI_CCR_TOCKDIV1_Pos          (9U)                                     
+#define DSI_CCR_TOCKDIV1_Msk          (0x1UL << DSI_CCR_TOCKDIV1_Pos)           /*!< 0x00000200 */
+#define DSI_CCR_TOCKDIV1              DSI_CCR_TOCKDIV1_Msk                     
+#define DSI_CCR_TOCKDIV2_Pos          (10U)                                    
+#define DSI_CCR_TOCKDIV2_Msk          (0x1UL << DSI_CCR_TOCKDIV2_Pos)           /*!< 0x00000400 */
+#define DSI_CCR_TOCKDIV2              DSI_CCR_TOCKDIV2_Msk                     
+#define DSI_CCR_TOCKDIV3_Pos          (11U)                                    
+#define DSI_CCR_TOCKDIV3_Msk          (0x1UL << DSI_CCR_TOCKDIV3_Pos)           /*!< 0x00000800 */
+#define DSI_CCR_TOCKDIV3              DSI_CCR_TOCKDIV3_Msk                     
+#define DSI_CCR_TOCKDIV4_Pos          (12U)                                    
+#define DSI_CCR_TOCKDIV4_Msk          (0x1UL << DSI_CCR_TOCKDIV4_Pos)           /*!< 0x00001000 */
+#define DSI_CCR_TOCKDIV4              DSI_CCR_TOCKDIV4_Msk                     
+#define DSI_CCR_TOCKDIV5_Pos          (13U)                                    
+#define DSI_CCR_TOCKDIV5_Msk          (0x1UL << DSI_CCR_TOCKDIV5_Pos)           /*!< 0x00002000 */
+#define DSI_CCR_TOCKDIV5              DSI_CCR_TOCKDIV5_Msk                     
+#define DSI_CCR_TOCKDIV6_Pos          (14U)                                    
+#define DSI_CCR_TOCKDIV6_Msk          (0x1UL << DSI_CCR_TOCKDIV6_Pos)           /*!< 0x00004000 */
+#define DSI_CCR_TOCKDIV6              DSI_CCR_TOCKDIV6_Msk                     
+#define DSI_CCR_TOCKDIV7_Pos          (15U)                                    
+#define DSI_CCR_TOCKDIV7_Msk          (0x1UL << DSI_CCR_TOCKDIV7_Pos)           /*!< 0x00008000 */
+#define DSI_CCR_TOCKDIV7              DSI_CCR_TOCKDIV7_Msk                     
+
+/*******************  Bit definition for DSI_LVCIDR register  *************/
+#define DSI_LVCIDR_VCID_Pos           (0U)                                     
+#define DSI_LVCIDR_VCID_Msk           (0x3UL << DSI_LVCIDR_VCID_Pos)            /*!< 0x00000003 */
+#define DSI_LVCIDR_VCID               DSI_LVCIDR_VCID_Msk                      /*!< Virtual Channel ID */
+#define DSI_LVCIDR_VCID0_Pos          (0U)                                     
+#define DSI_LVCIDR_VCID0_Msk          (0x1UL << DSI_LVCIDR_VCID0_Pos)           /*!< 0x00000001 */
+#define DSI_LVCIDR_VCID0              DSI_LVCIDR_VCID0_Msk                     
+#define DSI_LVCIDR_VCID1_Pos          (1U)                                     
+#define DSI_LVCIDR_VCID1_Msk          (0x1UL << DSI_LVCIDR_VCID1_Pos)           /*!< 0x00000002 */
+#define DSI_LVCIDR_VCID1              DSI_LVCIDR_VCID1_Msk                     
+
+/*******************  Bit definition for DSI_LCOLCR register  *************/
+#define DSI_LCOLCR_COLC_Pos           (0U)                                     
+#define DSI_LCOLCR_COLC_Msk           (0xFUL << DSI_LCOLCR_COLC_Pos)            /*!< 0x0000000F */
+#define DSI_LCOLCR_COLC               DSI_LCOLCR_COLC_Msk                      /*!< Color Coding */
+#define DSI_LCOLCR_COLC0_Pos          (0U)                                     
+#define DSI_LCOLCR_COLC0_Msk          (0x1UL << DSI_LCOLCR_COLC0_Pos)           /*!< 0x00000001 */
+#define DSI_LCOLCR_COLC0              DSI_LCOLCR_COLC0_Msk                     
+#define DSI_LCOLCR_COLC1_Pos          (5U)                                     
+#define DSI_LCOLCR_COLC1_Msk          (0x1UL << DSI_LCOLCR_COLC1_Pos)           /*!< 0x00000020 */
+#define DSI_LCOLCR_COLC1              DSI_LCOLCR_COLC1_Msk                     
+#define DSI_LCOLCR_COLC2_Pos          (6U)                                     
+#define DSI_LCOLCR_COLC2_Msk          (0x1UL << DSI_LCOLCR_COLC2_Pos)           /*!< 0x00000040 */
+#define DSI_LCOLCR_COLC2              DSI_LCOLCR_COLC2_Msk                     
+#define DSI_LCOLCR_COLC3_Pos          (7U)                                     
+#define DSI_LCOLCR_COLC3_Msk          (0x1UL << DSI_LCOLCR_COLC3_Pos)           /*!< 0x00000080 */
+#define DSI_LCOLCR_COLC3              DSI_LCOLCR_COLC3_Msk                     
+
+#define DSI_LCOLCR_LPE_Pos            (8U)                                     
+#define DSI_LCOLCR_LPE_Msk            (0x1UL << DSI_LCOLCR_LPE_Pos)             /*!< 0x00000100 */
+#define DSI_LCOLCR_LPE                DSI_LCOLCR_LPE_Msk                       /*!< Loosely Packet Enable */
+
+/*******************  Bit definition for DSI_LPCR register  ***************/
+#define DSI_LPCR_DEP_Pos              (0U)                                     
+#define DSI_LPCR_DEP_Msk              (0x1UL << DSI_LPCR_DEP_Pos)               /*!< 0x00000001 */
+#define DSI_LPCR_DEP                  DSI_LPCR_DEP_Msk                         /*!< Data Enable Polarity */
+#define DSI_LPCR_VSP_Pos              (1U)                                     
+#define DSI_LPCR_VSP_Msk              (0x1UL << DSI_LPCR_VSP_Pos)               /*!< 0x00000002 */
+#define DSI_LPCR_VSP                  DSI_LPCR_VSP_Msk                         /*!< VSYNC Polarity */
+#define DSI_LPCR_HSP_Pos              (2U)                                     
+#define DSI_LPCR_HSP_Msk              (0x1UL << DSI_LPCR_HSP_Pos)               /*!< 0x00000004 */
+#define DSI_LPCR_HSP                  DSI_LPCR_HSP_Msk                         /*!< HSYNC Polarity */
+
+/*******************  Bit definition for DSI_LPMCR register  **************/
+#define DSI_LPMCR_VLPSIZE_Pos         (0U)                                     
+#define DSI_LPMCR_VLPSIZE_Msk         (0xFFUL << DSI_LPMCR_VLPSIZE_Pos)         /*!< 0x000000FF */
+#define DSI_LPMCR_VLPSIZE             DSI_LPMCR_VLPSIZE_Msk                    /*!< VACT Largest Packet Size */
+#define DSI_LPMCR_VLPSIZE0_Pos        (0U)                                     
+#define DSI_LPMCR_VLPSIZE0_Msk        (0x1UL << DSI_LPMCR_VLPSIZE0_Pos)         /*!< 0x00000001 */
+#define DSI_LPMCR_VLPSIZE0            DSI_LPMCR_VLPSIZE0_Msk                   
+#define DSI_LPMCR_VLPSIZE1_Pos        (1U)                                     
+#define DSI_LPMCR_VLPSIZE1_Msk        (0x1UL << DSI_LPMCR_VLPSIZE1_Pos)         /*!< 0x00000002 */
+#define DSI_LPMCR_VLPSIZE1            DSI_LPMCR_VLPSIZE1_Msk                   
+#define DSI_LPMCR_VLPSIZE2_Pos        (2U)                                     
+#define DSI_LPMCR_VLPSIZE2_Msk        (0x1UL << DSI_LPMCR_VLPSIZE2_Pos)         /*!< 0x00000004 */
+#define DSI_LPMCR_VLPSIZE2            DSI_LPMCR_VLPSIZE2_Msk                   
+#define DSI_LPMCR_VLPSIZE3_Pos        (3U)                                     
+#define DSI_LPMCR_VLPSIZE3_Msk        (0x1UL << DSI_LPMCR_VLPSIZE3_Pos)         /*!< 0x00000008 */
+#define DSI_LPMCR_VLPSIZE3            DSI_LPMCR_VLPSIZE3_Msk                   
+#define DSI_LPMCR_VLPSIZE4_Pos        (4U)                                     
+#define DSI_LPMCR_VLPSIZE4_Msk        (0x1UL << DSI_LPMCR_VLPSIZE4_Pos)         /*!< 0x00000010 */
+#define DSI_LPMCR_VLPSIZE4            DSI_LPMCR_VLPSIZE4_Msk                   
+#define DSI_LPMCR_VLPSIZE5_Pos        (5U)                                     
+#define DSI_LPMCR_VLPSIZE5_Msk        (0x1UL << DSI_LPMCR_VLPSIZE5_Pos)         /*!< 0x00000020 */
+#define DSI_LPMCR_VLPSIZE5            DSI_LPMCR_VLPSIZE5_Msk                   
+#define DSI_LPMCR_VLPSIZE6_Pos        (6U)                                     
+#define DSI_LPMCR_VLPSIZE6_Msk        (0x1UL << DSI_LPMCR_VLPSIZE6_Pos)         /*!< 0x00000040 */
+#define DSI_LPMCR_VLPSIZE6            DSI_LPMCR_VLPSIZE6_Msk                   
+#define DSI_LPMCR_VLPSIZE7_Pos        (7U)                                     
+#define DSI_LPMCR_VLPSIZE7_Msk        (0x1UL << DSI_LPMCR_VLPSIZE7_Pos)         /*!< 0x00000080 */
+#define DSI_LPMCR_VLPSIZE7            DSI_LPMCR_VLPSIZE7_Msk                   
+
+#define DSI_LPMCR_LPSIZE_Pos          (16U)                                    
+#define DSI_LPMCR_LPSIZE_Msk          (0xFFUL << DSI_LPMCR_LPSIZE_Pos)          /*!< 0x00FF0000 */
+#define DSI_LPMCR_LPSIZE              DSI_LPMCR_LPSIZE_Msk                     /*!< Largest Packet Size */
+#define DSI_LPMCR_LPSIZE0_Pos         (16U)                                    
+#define DSI_LPMCR_LPSIZE0_Msk         (0x1UL << DSI_LPMCR_LPSIZE0_Pos)          /*!< 0x00010000 */
+#define DSI_LPMCR_LPSIZE0             DSI_LPMCR_LPSIZE0_Msk                    
+#define DSI_LPMCR_LPSIZE1_Pos         (17U)                                    
+#define DSI_LPMCR_LPSIZE1_Msk         (0x1UL << DSI_LPMCR_LPSIZE1_Pos)          /*!< 0x00020000 */
+#define DSI_LPMCR_LPSIZE1             DSI_LPMCR_LPSIZE1_Msk                    
+#define DSI_LPMCR_LPSIZE2_Pos         (18U)                                    
+#define DSI_LPMCR_LPSIZE2_Msk         (0x1UL << DSI_LPMCR_LPSIZE2_Pos)          /*!< 0x00040000 */
+#define DSI_LPMCR_LPSIZE2             DSI_LPMCR_LPSIZE2_Msk                    
+#define DSI_LPMCR_LPSIZE3_Pos         (19U)                                    
+#define DSI_LPMCR_LPSIZE3_Msk         (0x1UL << DSI_LPMCR_LPSIZE3_Pos)          /*!< 0x00080000 */
+#define DSI_LPMCR_LPSIZE3             DSI_LPMCR_LPSIZE3_Msk                    
+#define DSI_LPMCR_LPSIZE4_Pos         (20U)                                    
+#define DSI_LPMCR_LPSIZE4_Msk         (0x1UL << DSI_LPMCR_LPSIZE4_Pos)          /*!< 0x00100000 */
+#define DSI_LPMCR_LPSIZE4             DSI_LPMCR_LPSIZE4_Msk                    
+#define DSI_LPMCR_LPSIZE5_Pos         (21U)                                    
+#define DSI_LPMCR_LPSIZE5_Msk         (0x1UL << DSI_LPMCR_LPSIZE5_Pos)          /*!< 0x00200000 */
+#define DSI_LPMCR_LPSIZE5             DSI_LPMCR_LPSIZE5_Msk                    
+#define DSI_LPMCR_LPSIZE6_Pos         (22U)                                    
+#define DSI_LPMCR_LPSIZE6_Msk         (0x1UL << DSI_LPMCR_LPSIZE6_Pos)          /*!< 0x00400000 */
+#define DSI_LPMCR_LPSIZE6             DSI_LPMCR_LPSIZE6_Msk                    
+#define DSI_LPMCR_LPSIZE7_Pos         (23U)                                    
+#define DSI_LPMCR_LPSIZE7_Msk         (0x1UL << DSI_LPMCR_LPSIZE7_Pos)          /*!< 0x00800000 */
+#define DSI_LPMCR_LPSIZE7             DSI_LPMCR_LPSIZE7_Msk                    
+
+/*******************  Bit definition for DSI_PCR register  ****************/
+#define DSI_PCR_ETTXE_Pos             (0U)                                     
+#define DSI_PCR_ETTXE_Msk             (0x1UL << DSI_PCR_ETTXE_Pos)              /*!< 0x00000001 */
+#define DSI_PCR_ETTXE                 DSI_PCR_ETTXE_Msk                        /*!< EoTp Transmission Enable */
+#define DSI_PCR_ETRXE_Pos             (1U)                                     
+#define DSI_PCR_ETRXE_Msk             (0x1UL << DSI_PCR_ETRXE_Pos)              /*!< 0x00000002 */
+#define DSI_PCR_ETRXE                 DSI_PCR_ETRXE_Msk                        /*!< EoTp Reception Enable */
+#define DSI_PCR_BTAE_Pos              (2U)                                     
+#define DSI_PCR_BTAE_Msk              (0x1UL << DSI_PCR_BTAE_Pos)               /*!< 0x00000004 */
+#define DSI_PCR_BTAE                  DSI_PCR_BTAE_Msk                         /*!< Bus Turn Around Enable */
+#define DSI_PCR_ECCRXE_Pos            (3U)                                     
+#define DSI_PCR_ECCRXE_Msk            (0x1UL << DSI_PCR_ECCRXE_Pos)             /*!< 0x00000008 */
+#define DSI_PCR_ECCRXE                DSI_PCR_ECCRXE_Msk                       /*!< ECC Reception Enable */
+#define DSI_PCR_CRCRXE_Pos            (4U)                                     
+#define DSI_PCR_CRCRXE_Msk            (0x1UL << DSI_PCR_CRCRXE_Pos)             /*!< 0x00000010 */
+#define DSI_PCR_CRCRXE                DSI_PCR_CRCRXE_Msk                       /*!< CRC Reception Enable */
+
+/*******************  Bit definition for DSI_GVCIDR register  *************/
+#define DSI_GVCIDR_VCID_Pos           (0U)                                     
+#define DSI_GVCIDR_VCID_Msk           (0x3UL << DSI_GVCIDR_VCID_Pos)            /*!< 0x00000003 */
+#define DSI_GVCIDR_VCID               DSI_GVCIDR_VCID_Msk                      /*!< Virtual Channel ID */
+#define DSI_GVCIDR_VCID0_Pos          (0U)                                     
+#define DSI_GVCIDR_VCID0_Msk          (0x1UL << DSI_GVCIDR_VCID0_Pos)           /*!< 0x00000001 */
+#define DSI_GVCIDR_VCID0              DSI_GVCIDR_VCID0_Msk                     
+#define DSI_GVCIDR_VCID1_Pos          (1U)                                     
+#define DSI_GVCIDR_VCID1_Msk          (0x1UL << DSI_GVCIDR_VCID1_Pos)           /*!< 0x00000002 */
+#define DSI_GVCIDR_VCID1              DSI_GVCIDR_VCID1_Msk                     
+
+/*******************  Bit definition for DSI_MCR register  ****************/
+#define DSI_MCR_CMDM_Pos              (0U)                                     
+#define DSI_MCR_CMDM_Msk              (0x1UL << DSI_MCR_CMDM_Pos)               /*!< 0x00000001 */
+#define DSI_MCR_CMDM                  DSI_MCR_CMDM_Msk                         /*!< Command Mode */
+
+/*******************  Bit definition for DSI_VMCR register  ***************/
+#define DSI_VMCR_VMT_Pos              (0U)                                     
+#define DSI_VMCR_VMT_Msk              (0x3UL << DSI_VMCR_VMT_Pos)               /*!< 0x00000003 */
+#define DSI_VMCR_VMT                  DSI_VMCR_VMT_Msk                         /*!< Video Mode Type */
+#define DSI_VMCR_VMT0_Pos             (0U)                                     
+#define DSI_VMCR_VMT0_Msk             (0x1UL << DSI_VMCR_VMT0_Pos)              /*!< 0x00000001 */
+#define DSI_VMCR_VMT0                 DSI_VMCR_VMT0_Msk                        
+#define DSI_VMCR_VMT1_Pos             (1U)                                     
+#define DSI_VMCR_VMT1_Msk             (0x1UL << DSI_VMCR_VMT1_Pos)              /*!< 0x00000002 */
+#define DSI_VMCR_VMT1                 DSI_VMCR_VMT1_Msk                        
+
+#define DSI_VMCR_LPVSAE_Pos           (8U)                                     
+#define DSI_VMCR_LPVSAE_Msk           (0x1UL << DSI_VMCR_LPVSAE_Pos)            /*!< 0x00000100 */
+#define DSI_VMCR_LPVSAE               DSI_VMCR_LPVSAE_Msk                      /*!< Low-Power Vertical Sync Active Enable */
+#define DSI_VMCR_LPVBPE_Pos           (9U)                                     
+#define DSI_VMCR_LPVBPE_Msk           (0x1UL << DSI_VMCR_LPVBPE_Pos)            /*!< 0x00000200 */
+#define DSI_VMCR_LPVBPE               DSI_VMCR_LPVBPE_Msk                      /*!< Low-power Vertical Back-Porch Enable */
+#define DSI_VMCR_LPVFPE_Pos           (10U)                                    
+#define DSI_VMCR_LPVFPE_Msk           (0x1UL << DSI_VMCR_LPVFPE_Pos)            /*!< 0x00000400 */
+#define DSI_VMCR_LPVFPE               DSI_VMCR_LPVFPE_Msk                      /*!< Low-power Vertical Front-porch Enable */
+#define DSI_VMCR_LPVAE_Pos            (11U)                                    
+#define DSI_VMCR_LPVAE_Msk            (0x1UL << DSI_VMCR_LPVAE_Pos)             /*!< 0x00000800 */
+#define DSI_VMCR_LPVAE                DSI_VMCR_LPVAE_Msk                       /*!< Low-Power Vertical Active Enable */
+#define DSI_VMCR_LPHBPE_Pos           (12U)                                    
+#define DSI_VMCR_LPHBPE_Msk           (0x1UL << DSI_VMCR_LPHBPE_Pos)            /*!< 0x00001000 */
+#define DSI_VMCR_LPHBPE               DSI_VMCR_LPHBPE_Msk                      /*!< Low-Power Horizontal Back-Porch Enable */
+#define DSI_VMCR_LPHFPE_Pos           (13U)                                    
+#define DSI_VMCR_LPHFPE_Msk           (0x1UL << DSI_VMCR_LPHFPE_Pos)            /*!< 0x00002000 */
+#define DSI_VMCR_LPHFPE               DSI_VMCR_LPHFPE_Msk                      /*!< Low-Power Horizontal Front-Porch Enable */
+#define DSI_VMCR_FBTAAE_Pos           (14U)                                    
+#define DSI_VMCR_FBTAAE_Msk           (0x1UL << DSI_VMCR_FBTAAE_Pos)            /*!< 0x00004000 */
+#define DSI_VMCR_FBTAAE               DSI_VMCR_FBTAAE_Msk                      /*!< Frame Bus-Turn-Around Acknowledge Enable */
+#define DSI_VMCR_LPCE_Pos             (15U)                                    
+#define DSI_VMCR_LPCE_Msk             (0x1UL << DSI_VMCR_LPCE_Pos)              /*!< 0x00008000 */
+#define DSI_VMCR_LPCE                 DSI_VMCR_LPCE_Msk                        /*!< Low-Power Command Enable */
+#define DSI_VMCR_PGE_Pos              (16U)                                    
+#define DSI_VMCR_PGE_Msk              (0x1UL << DSI_VMCR_PGE_Pos)               /*!< 0x00010000 */
+#define DSI_VMCR_PGE                  DSI_VMCR_PGE_Msk                         /*!< Pattern Generator Enable */
+#define DSI_VMCR_PGM_Pos              (20U)                                    
+#define DSI_VMCR_PGM_Msk              (0x1UL << DSI_VMCR_PGM_Pos)               /*!< 0x00100000 */
+#define DSI_VMCR_PGM                  DSI_VMCR_PGM_Msk                         /*!< Pattern Generator Mode */
+#define DSI_VMCR_PGO_Pos              (24U)                                    
+#define DSI_VMCR_PGO_Msk              (0x1UL << DSI_VMCR_PGO_Pos)               /*!< 0x01000000 */
+#define DSI_VMCR_PGO                  DSI_VMCR_PGO_Msk                         /*!< Pattern Generator Orientation */
+
+/*******************  Bit definition for DSI_VPCR register  ***************/
+#define DSI_VPCR_VPSIZE_Pos           (0U)                                     
+#define DSI_VPCR_VPSIZE_Msk           (0x3FFFUL << DSI_VPCR_VPSIZE_Pos)         /*!< 0x00003FFF */
+#define DSI_VPCR_VPSIZE               DSI_VPCR_VPSIZE_Msk                      /*!< Video Packet Size */
+#define DSI_VPCR_VPSIZE0_Pos          (0U)                                     
+#define DSI_VPCR_VPSIZE0_Msk          (0x1UL << DSI_VPCR_VPSIZE0_Pos)           /*!< 0x00000001 */
+#define DSI_VPCR_VPSIZE0              DSI_VPCR_VPSIZE0_Msk                     
+#define DSI_VPCR_VPSIZE1_Pos          (1U)                                     
+#define DSI_VPCR_VPSIZE1_Msk          (0x1UL << DSI_VPCR_VPSIZE1_Pos)           /*!< 0x00000002 */
+#define DSI_VPCR_VPSIZE1              DSI_VPCR_VPSIZE1_Msk                     
+#define DSI_VPCR_VPSIZE2_Pos          (2U)                                     
+#define DSI_VPCR_VPSIZE2_Msk          (0x1UL << DSI_VPCR_VPSIZE2_Pos)           /*!< 0x00000004 */
+#define DSI_VPCR_VPSIZE2              DSI_VPCR_VPSIZE2_Msk                     
+#define DSI_VPCR_VPSIZE3_Pos          (3U)                                     
+#define DSI_VPCR_VPSIZE3_Msk          (0x1UL << DSI_VPCR_VPSIZE3_Pos)           /*!< 0x00000008 */
+#define DSI_VPCR_VPSIZE3              DSI_VPCR_VPSIZE3_Msk                     
+#define DSI_VPCR_VPSIZE4_Pos          (4U)                                     
+#define DSI_VPCR_VPSIZE4_Msk          (0x1UL << DSI_VPCR_VPSIZE4_Pos)           /*!< 0x00000010 */
+#define DSI_VPCR_VPSIZE4              DSI_VPCR_VPSIZE4_Msk                     
+#define DSI_VPCR_VPSIZE5_Pos          (5U)                                     
+#define DSI_VPCR_VPSIZE5_Msk          (0x1UL << DSI_VPCR_VPSIZE5_Pos)           /*!< 0x00000020 */
+#define DSI_VPCR_VPSIZE5              DSI_VPCR_VPSIZE5_Msk                     
+#define DSI_VPCR_VPSIZE6_Pos          (6U)                                     
+#define DSI_VPCR_VPSIZE6_Msk          (0x1UL << DSI_VPCR_VPSIZE6_Pos)           /*!< 0x00000040 */
+#define DSI_VPCR_VPSIZE6              DSI_VPCR_VPSIZE6_Msk                     
+#define DSI_VPCR_VPSIZE7_Pos          (7U)                                     
+#define DSI_VPCR_VPSIZE7_Msk          (0x1UL << DSI_VPCR_VPSIZE7_Pos)           /*!< 0x00000080 */
+#define DSI_VPCR_VPSIZE7              DSI_VPCR_VPSIZE7_Msk                     
+#define DSI_VPCR_VPSIZE8_Pos          (8U)                                     
+#define DSI_VPCR_VPSIZE8_Msk          (0x1UL << DSI_VPCR_VPSIZE8_Pos)           /*!< 0x00000100 */
+#define DSI_VPCR_VPSIZE8              DSI_VPCR_VPSIZE8_Msk                     
+#define DSI_VPCR_VPSIZE9_Pos          (9U)                                     
+#define DSI_VPCR_VPSIZE9_Msk          (0x1UL << DSI_VPCR_VPSIZE9_Pos)           /*!< 0x00000200 */
+#define DSI_VPCR_VPSIZE9              DSI_VPCR_VPSIZE9_Msk                     
+#define DSI_VPCR_VPSIZE10_Pos         (10U)                                    
+#define DSI_VPCR_VPSIZE10_Msk         (0x1UL << DSI_VPCR_VPSIZE10_Pos)          /*!< 0x00000400 */
+#define DSI_VPCR_VPSIZE10             DSI_VPCR_VPSIZE10_Msk                    
+#define DSI_VPCR_VPSIZE11_Pos         (11U)                                    
+#define DSI_VPCR_VPSIZE11_Msk         (0x1UL << DSI_VPCR_VPSIZE11_Pos)          /*!< 0x00000800 */
+#define DSI_VPCR_VPSIZE11             DSI_VPCR_VPSIZE11_Msk                    
+#define DSI_VPCR_VPSIZE12_Pos         (12U)                                    
+#define DSI_VPCR_VPSIZE12_Msk         (0x1UL << DSI_VPCR_VPSIZE12_Pos)          /*!< 0x00001000 */
+#define DSI_VPCR_VPSIZE12             DSI_VPCR_VPSIZE12_Msk                    
+#define DSI_VPCR_VPSIZE13_Pos         (13U)                                    
+#define DSI_VPCR_VPSIZE13_Msk         (0x1UL << DSI_VPCR_VPSIZE13_Pos)          /*!< 0x00002000 */
+#define DSI_VPCR_VPSIZE13             DSI_VPCR_VPSIZE13_Msk                    
+
+/*******************  Bit definition for DSI_VCCR register  ***************/
+#define DSI_VCCR_NUMC_Pos             (0U)                                     
+#define DSI_VCCR_NUMC_Msk             (0x1FFFUL << DSI_VCCR_NUMC_Pos)           /*!< 0x00001FFF */
+#define DSI_VCCR_NUMC                 DSI_VCCR_NUMC_Msk                        /*!< Number of Chunks */
+#define DSI_VCCR_NUMC0_Pos            (0U)                                     
+#define DSI_VCCR_NUMC0_Msk            (0x1UL << DSI_VCCR_NUMC0_Pos)             /*!< 0x00000001 */
+#define DSI_VCCR_NUMC0                DSI_VCCR_NUMC0_Msk                       
+#define DSI_VCCR_NUMC1_Pos            (1U)                                     
+#define DSI_VCCR_NUMC1_Msk            (0x1UL << DSI_VCCR_NUMC1_Pos)             /*!< 0x00000002 */
+#define DSI_VCCR_NUMC1                DSI_VCCR_NUMC1_Msk                       
+#define DSI_VCCR_NUMC2_Pos            (2U)                                     
+#define DSI_VCCR_NUMC2_Msk            (0x1UL << DSI_VCCR_NUMC2_Pos)             /*!< 0x00000004 */
+#define DSI_VCCR_NUMC2                DSI_VCCR_NUMC2_Msk                       
+#define DSI_VCCR_NUMC3_Pos            (3U)                                     
+#define DSI_VCCR_NUMC3_Msk            (0x1UL << DSI_VCCR_NUMC3_Pos)             /*!< 0x00000008 */
+#define DSI_VCCR_NUMC3                DSI_VCCR_NUMC3_Msk                       
+#define DSI_VCCR_NUMC4_Pos            (4U)                                     
+#define DSI_VCCR_NUMC4_Msk            (0x1UL << DSI_VCCR_NUMC4_Pos)             /*!< 0x00000010 */
+#define DSI_VCCR_NUMC4                DSI_VCCR_NUMC4_Msk                       
+#define DSI_VCCR_NUMC5_Pos            (5U)                                     
+#define DSI_VCCR_NUMC5_Msk            (0x1UL << DSI_VCCR_NUMC5_Pos)             /*!< 0x00000020 */
+#define DSI_VCCR_NUMC5                DSI_VCCR_NUMC5_Msk                       
+#define DSI_VCCR_NUMC6_Pos            (6U)                                     
+#define DSI_VCCR_NUMC6_Msk            (0x1UL << DSI_VCCR_NUMC6_Pos)             /*!< 0x00000040 */
+#define DSI_VCCR_NUMC6                DSI_VCCR_NUMC6_Msk                       
+#define DSI_VCCR_NUMC7_Pos            (7U)                                     
+#define DSI_VCCR_NUMC7_Msk            (0x1UL << DSI_VCCR_NUMC7_Pos)             /*!< 0x00000080 */
+#define DSI_VCCR_NUMC7                DSI_VCCR_NUMC7_Msk                       
+#define DSI_VCCR_NUMC8_Pos            (8U)                                     
+#define DSI_VCCR_NUMC8_Msk            (0x1UL << DSI_VCCR_NUMC8_Pos)             /*!< 0x00000100 */
+#define DSI_VCCR_NUMC8                DSI_VCCR_NUMC8_Msk                       
+#define DSI_VCCR_NUMC9_Pos            (9U)                                     
+#define DSI_VCCR_NUMC9_Msk            (0x1UL << DSI_VCCR_NUMC9_Pos)             /*!< 0x00000200 */
+#define DSI_VCCR_NUMC9                DSI_VCCR_NUMC9_Msk                       
+#define DSI_VCCR_NUMC10_Pos           (10U)                                    
+#define DSI_VCCR_NUMC10_Msk           (0x1UL << DSI_VCCR_NUMC10_Pos)            /*!< 0x00000400 */
+#define DSI_VCCR_NUMC10               DSI_VCCR_NUMC10_Msk                      
+#define DSI_VCCR_NUMC11_Pos           (11U)                                    
+#define DSI_VCCR_NUMC11_Msk           (0x1UL << DSI_VCCR_NUMC11_Pos)            /*!< 0x00000800 */
+#define DSI_VCCR_NUMC11               DSI_VCCR_NUMC11_Msk                      
+#define DSI_VCCR_NUMC12_Pos           (12U)                                    
+#define DSI_VCCR_NUMC12_Msk           (0x1UL << DSI_VCCR_NUMC12_Pos)            /*!< 0x00001000 */
+#define DSI_VCCR_NUMC12               DSI_VCCR_NUMC12_Msk                      
+
+/*******************  Bit definition for DSI_VNPCR register  **************/
+#define DSI_VNPCR_NPSIZE_Pos          (0U)                                     
+#define DSI_VNPCR_NPSIZE_Msk          (0x1FFFUL << DSI_VNPCR_NPSIZE_Pos)        /*!< 0x00001FFF */
+#define DSI_VNPCR_NPSIZE              DSI_VNPCR_NPSIZE_Msk                     /*!< Null Packet Size */
+#define DSI_VNPCR_NPSIZE0_Pos         (0U)                                     
+#define DSI_VNPCR_NPSIZE0_Msk         (0x1UL << DSI_VNPCR_NPSIZE0_Pos)          /*!< 0x00000001 */
+#define DSI_VNPCR_NPSIZE0             DSI_VNPCR_NPSIZE0_Msk                    
+#define DSI_VNPCR_NPSIZE1_Pos         (1U)                                     
+#define DSI_VNPCR_NPSIZE1_Msk         (0x1UL << DSI_VNPCR_NPSIZE1_Pos)          /*!< 0x00000002 */
+#define DSI_VNPCR_NPSIZE1             DSI_VNPCR_NPSIZE1_Msk                    
+#define DSI_VNPCR_NPSIZE2_Pos         (2U)                                     
+#define DSI_VNPCR_NPSIZE2_Msk         (0x1UL << DSI_VNPCR_NPSIZE2_Pos)          /*!< 0x00000004 */
+#define DSI_VNPCR_NPSIZE2             DSI_VNPCR_NPSIZE2_Msk                    
+#define DSI_VNPCR_NPSIZE3_Pos         (3U)                                     
+#define DSI_VNPCR_NPSIZE3_Msk         (0x1UL << DSI_VNPCR_NPSIZE3_Pos)          /*!< 0x00000008 */
+#define DSI_VNPCR_NPSIZE3             DSI_VNPCR_NPSIZE3_Msk                    
+#define DSI_VNPCR_NPSIZE4_Pos         (4U)                                     
+#define DSI_VNPCR_NPSIZE4_Msk         (0x1UL << DSI_VNPCR_NPSIZE4_Pos)          /*!< 0x00000010 */
+#define DSI_VNPCR_NPSIZE4             DSI_VNPCR_NPSIZE4_Msk                    
+#define DSI_VNPCR_NPSIZE5_Pos         (5U)                                     
+#define DSI_VNPCR_NPSIZE5_Msk         (0x1UL << DSI_VNPCR_NPSIZE5_Pos)          /*!< 0x00000020 */
+#define DSI_VNPCR_NPSIZE5             DSI_VNPCR_NPSIZE5_Msk                    
+#define DSI_VNPCR_NPSIZE6_Pos         (6U)                                     
+#define DSI_VNPCR_NPSIZE6_Msk         (0x1UL << DSI_VNPCR_NPSIZE6_Pos)          /*!< 0x00000040 */
+#define DSI_VNPCR_NPSIZE6             DSI_VNPCR_NPSIZE6_Msk                    
+#define DSI_VNPCR_NPSIZE7_Pos         (7U)                                     
+#define DSI_VNPCR_NPSIZE7_Msk         (0x1UL << DSI_VNPCR_NPSIZE7_Pos)          /*!< 0x00000080 */
+#define DSI_VNPCR_NPSIZE7             DSI_VNPCR_NPSIZE7_Msk                    
+#define DSI_VNPCR_NPSIZE8_Pos         (8U)                                     
+#define DSI_VNPCR_NPSIZE8_Msk         (0x1UL << DSI_VNPCR_NPSIZE8_Pos)          /*!< 0x00000100 */
+#define DSI_VNPCR_NPSIZE8             DSI_VNPCR_NPSIZE8_Msk                    
+#define DSI_VNPCR_NPSIZE9_Pos         (9U)                                     
+#define DSI_VNPCR_NPSIZE9_Msk         (0x1UL << DSI_VNPCR_NPSIZE9_Pos)          /*!< 0x00000200 */
+#define DSI_VNPCR_NPSIZE9             DSI_VNPCR_NPSIZE9_Msk                    
+#define DSI_VNPCR_NPSIZE10_Pos        (10U)                                    
+#define DSI_VNPCR_NPSIZE10_Msk        (0x1UL << DSI_VNPCR_NPSIZE10_Pos)         /*!< 0x00000400 */
+#define DSI_VNPCR_NPSIZE10            DSI_VNPCR_NPSIZE10_Msk                   
+#define DSI_VNPCR_NPSIZE11_Pos        (11U)                                    
+#define DSI_VNPCR_NPSIZE11_Msk        (0x1UL << DSI_VNPCR_NPSIZE11_Pos)         /*!< 0x00000800 */
+#define DSI_VNPCR_NPSIZE11            DSI_VNPCR_NPSIZE11_Msk                   
+#define DSI_VNPCR_NPSIZE12_Pos        (12U)                                    
+#define DSI_VNPCR_NPSIZE12_Msk        (0x1UL << DSI_VNPCR_NPSIZE12_Pos)         /*!< 0x00001000 */
+#define DSI_VNPCR_NPSIZE12            DSI_VNPCR_NPSIZE12_Msk                   
+
+/*******************  Bit definition for DSI_VHSACR register  *************/
+#define DSI_VHSACR_HSA_Pos            (0U)                                     
+#define DSI_VHSACR_HSA_Msk            (0xFFFUL << DSI_VHSACR_HSA_Pos)           /*!< 0x00000FFF */
+#define DSI_VHSACR_HSA                DSI_VHSACR_HSA_Msk                       /*!< Horizontal Synchronism Active duration */
+#define DSI_VHSACR_HSA0_Pos           (0U)                                     
+#define DSI_VHSACR_HSA0_Msk           (0x1UL << DSI_VHSACR_HSA0_Pos)            /*!< 0x00000001 */
+#define DSI_VHSACR_HSA0               DSI_VHSACR_HSA0_Msk                      
+#define DSI_VHSACR_HSA1_Pos           (1U)                                     
+#define DSI_VHSACR_HSA1_Msk           (0x1UL << DSI_VHSACR_HSA1_Pos)            /*!< 0x00000002 */
+#define DSI_VHSACR_HSA1               DSI_VHSACR_HSA1_Msk                      
+#define DSI_VHSACR_HSA2_Pos           (2U)                                     
+#define DSI_VHSACR_HSA2_Msk           (0x1UL << DSI_VHSACR_HSA2_Pos)            /*!< 0x00000004 */
+#define DSI_VHSACR_HSA2               DSI_VHSACR_HSA2_Msk                      
+#define DSI_VHSACR_HSA3_Pos           (3U)                                     
+#define DSI_VHSACR_HSA3_Msk           (0x1UL << DSI_VHSACR_HSA3_Pos)            /*!< 0x00000008 */
+#define DSI_VHSACR_HSA3               DSI_VHSACR_HSA3_Msk                      
+#define DSI_VHSACR_HSA4_Pos           (4U)                                     
+#define DSI_VHSACR_HSA4_Msk           (0x1UL << DSI_VHSACR_HSA4_Pos)            /*!< 0x00000010 */
+#define DSI_VHSACR_HSA4               DSI_VHSACR_HSA4_Msk                      
+#define DSI_VHSACR_HSA5_Pos           (5U)                                     
+#define DSI_VHSACR_HSA5_Msk           (0x1UL << DSI_VHSACR_HSA5_Pos)            /*!< 0x00000020 */
+#define DSI_VHSACR_HSA5               DSI_VHSACR_HSA5_Msk                      
+#define DSI_VHSACR_HSA6_Pos           (6U)                                     
+#define DSI_VHSACR_HSA6_Msk           (0x1UL << DSI_VHSACR_HSA6_Pos)            /*!< 0x00000040 */
+#define DSI_VHSACR_HSA6               DSI_VHSACR_HSA6_Msk                      
+#define DSI_VHSACR_HSA7_Pos           (7U)                                     
+#define DSI_VHSACR_HSA7_Msk           (0x1UL << DSI_VHSACR_HSA7_Pos)            /*!< 0x00000080 */
+#define DSI_VHSACR_HSA7               DSI_VHSACR_HSA7_Msk                      
+#define DSI_VHSACR_HSA8_Pos           (8U)                                     
+#define DSI_VHSACR_HSA8_Msk           (0x1UL << DSI_VHSACR_HSA8_Pos)            /*!< 0x00000100 */
+#define DSI_VHSACR_HSA8               DSI_VHSACR_HSA8_Msk                      
+#define DSI_VHSACR_HSA9_Pos           (9U)                                     
+#define DSI_VHSACR_HSA9_Msk           (0x1UL << DSI_VHSACR_HSA9_Pos)            /*!< 0x00000200 */
+#define DSI_VHSACR_HSA9               DSI_VHSACR_HSA9_Msk                      
+#define DSI_VHSACR_HSA10_Pos          (10U)                                    
+#define DSI_VHSACR_HSA10_Msk          (0x1UL << DSI_VHSACR_HSA10_Pos)           /*!< 0x00000400 */
+#define DSI_VHSACR_HSA10              DSI_VHSACR_HSA10_Msk                     
+#define DSI_VHSACR_HSA11_Pos          (11U)                                    
+#define DSI_VHSACR_HSA11_Msk          (0x1UL << DSI_VHSACR_HSA11_Pos)           /*!< 0x00000800 */
+#define DSI_VHSACR_HSA11              DSI_VHSACR_HSA11_Msk                     
+
+/*******************  Bit definition for DSI_VHBPCR register  *************/
+#define DSI_VHBPCR_HBP_Pos            (0U)                                     
+#define DSI_VHBPCR_HBP_Msk            (0xFFFUL << DSI_VHBPCR_HBP_Pos)           /*!< 0x00000FFF */
+#define DSI_VHBPCR_HBP                DSI_VHBPCR_HBP_Msk                       /*!< Horizontal Back-Porch duration */
+#define DSI_VHBPCR_HBP0_Pos           (0U)                                     
+#define DSI_VHBPCR_HBP0_Msk           (0x1UL << DSI_VHBPCR_HBP0_Pos)            /*!< 0x00000001 */
+#define DSI_VHBPCR_HBP0               DSI_VHBPCR_HBP0_Msk                      
+#define DSI_VHBPCR_HBP1_Pos           (1U)                                     
+#define DSI_VHBPCR_HBP1_Msk           (0x1UL << DSI_VHBPCR_HBP1_Pos)            /*!< 0x00000002 */
+#define DSI_VHBPCR_HBP1               DSI_VHBPCR_HBP1_Msk                      
+#define DSI_VHBPCR_HBP2_Pos           (2U)                                     
+#define DSI_VHBPCR_HBP2_Msk           (0x1UL << DSI_VHBPCR_HBP2_Pos)            /*!< 0x00000004 */
+#define DSI_VHBPCR_HBP2               DSI_VHBPCR_HBP2_Msk                      
+#define DSI_VHBPCR_HBP3_Pos           (3U)                                     
+#define DSI_VHBPCR_HBP3_Msk           (0x1UL << DSI_VHBPCR_HBP3_Pos)            /*!< 0x00000008 */
+#define DSI_VHBPCR_HBP3               DSI_VHBPCR_HBP3_Msk                      
+#define DSI_VHBPCR_HBP4_Pos           (4U)                                     
+#define DSI_VHBPCR_HBP4_Msk           (0x1UL << DSI_VHBPCR_HBP4_Pos)            /*!< 0x00000010 */
+#define DSI_VHBPCR_HBP4               DSI_VHBPCR_HBP4_Msk                      
+#define DSI_VHBPCR_HBP5_Pos           (5U)                                     
+#define DSI_VHBPCR_HBP5_Msk           (0x1UL << DSI_VHBPCR_HBP5_Pos)            /*!< 0x00000020 */
+#define DSI_VHBPCR_HBP5               DSI_VHBPCR_HBP5_Msk                      
+#define DSI_VHBPCR_HBP6_Pos           (6U)                                     
+#define DSI_VHBPCR_HBP6_Msk           (0x1UL << DSI_VHBPCR_HBP6_Pos)            /*!< 0x00000040 */
+#define DSI_VHBPCR_HBP6               DSI_VHBPCR_HBP6_Msk                      
+#define DSI_VHBPCR_HBP7_Pos           (7U)                                     
+#define DSI_VHBPCR_HBP7_Msk           (0x1UL << DSI_VHBPCR_HBP7_Pos)            /*!< 0x00000080 */
+#define DSI_VHBPCR_HBP7               DSI_VHBPCR_HBP7_Msk                      
+#define DSI_VHBPCR_HBP8_Pos           (8U)                                     
+#define DSI_VHBPCR_HBP8_Msk           (0x1UL << DSI_VHBPCR_HBP8_Pos)            /*!< 0x00000100 */
+#define DSI_VHBPCR_HBP8               DSI_VHBPCR_HBP8_Msk                      
+#define DSI_VHBPCR_HBP9_Pos           (9U)                                     
+#define DSI_VHBPCR_HBP9_Msk           (0x1UL << DSI_VHBPCR_HBP9_Pos)            /*!< 0x00000200 */
+#define DSI_VHBPCR_HBP9               DSI_VHBPCR_HBP9_Msk                      
+#define DSI_VHBPCR_HBP10_Pos          (10U)                                    
+#define DSI_VHBPCR_HBP10_Msk          (0x1UL << DSI_VHBPCR_HBP10_Pos)           /*!< 0x00000400 */
+#define DSI_VHBPCR_HBP10              DSI_VHBPCR_HBP10_Msk                     
+#define DSI_VHBPCR_HBP11_Pos          (11U)                                    
+#define DSI_VHBPCR_HBP11_Msk          (0x1UL << DSI_VHBPCR_HBP11_Pos)           /*!< 0x00000800 */
+#define DSI_VHBPCR_HBP11              DSI_VHBPCR_HBP11_Msk                     
+
+/*******************  Bit definition for DSI_VLCR register  ***************/
+#define DSI_VLCR_HLINE_Pos            (0U)                                     
+#define DSI_VLCR_HLINE_Msk            (0x7FFFUL << DSI_VLCR_HLINE_Pos)          /*!< 0x00007FFF */
+#define DSI_VLCR_HLINE                DSI_VLCR_HLINE_Msk                       /*!< Horizontal Line duration */
+#define DSI_VLCR_HLINE0_Pos           (0U)                                     
+#define DSI_VLCR_HLINE0_Msk           (0x1UL << DSI_VLCR_HLINE0_Pos)            /*!< 0x00000001 */
+#define DSI_VLCR_HLINE0               DSI_VLCR_HLINE0_Msk                      
+#define DSI_VLCR_HLINE1_Pos           (1U)                                     
+#define DSI_VLCR_HLINE1_Msk           (0x1UL << DSI_VLCR_HLINE1_Pos)            /*!< 0x00000002 */
+#define DSI_VLCR_HLINE1               DSI_VLCR_HLINE1_Msk                      
+#define DSI_VLCR_HLINE2_Pos           (2U)                                     
+#define DSI_VLCR_HLINE2_Msk           (0x1UL << DSI_VLCR_HLINE2_Pos)            /*!< 0x00000004 */
+#define DSI_VLCR_HLINE2               DSI_VLCR_HLINE2_Msk                      
+#define DSI_VLCR_HLINE3_Pos           (3U)                                     
+#define DSI_VLCR_HLINE3_Msk           (0x1UL << DSI_VLCR_HLINE3_Pos)            /*!< 0x00000008 */
+#define DSI_VLCR_HLINE3               DSI_VLCR_HLINE3_Msk                      
+#define DSI_VLCR_HLINE4_Pos           (4U)                                     
+#define DSI_VLCR_HLINE4_Msk           (0x1UL << DSI_VLCR_HLINE4_Pos)            /*!< 0x00000010 */
+#define DSI_VLCR_HLINE4               DSI_VLCR_HLINE4_Msk                      
+#define DSI_VLCR_HLINE5_Pos           (5U)                                     
+#define DSI_VLCR_HLINE5_Msk           (0x1UL << DSI_VLCR_HLINE5_Pos)            /*!< 0x00000020 */
+#define DSI_VLCR_HLINE5               DSI_VLCR_HLINE5_Msk                      
+#define DSI_VLCR_HLINE6_Pos           (6U)                                     
+#define DSI_VLCR_HLINE6_Msk           (0x1UL << DSI_VLCR_HLINE6_Pos)            /*!< 0x00000040 */
+#define DSI_VLCR_HLINE6               DSI_VLCR_HLINE6_Msk                      
+#define DSI_VLCR_HLINE7_Pos           (7U)                                     
+#define DSI_VLCR_HLINE7_Msk           (0x1UL << DSI_VLCR_HLINE7_Pos)            /*!< 0x00000080 */
+#define DSI_VLCR_HLINE7               DSI_VLCR_HLINE7_Msk                      
+#define DSI_VLCR_HLINE8_Pos           (8U)                                     
+#define DSI_VLCR_HLINE8_Msk           (0x1UL << DSI_VLCR_HLINE8_Pos)            /*!< 0x00000100 */
+#define DSI_VLCR_HLINE8               DSI_VLCR_HLINE8_Msk                      
+#define DSI_VLCR_HLINE9_Pos           (9U)                                     
+#define DSI_VLCR_HLINE9_Msk           (0x1UL << DSI_VLCR_HLINE9_Pos)            /*!< 0x00000200 */
+#define DSI_VLCR_HLINE9               DSI_VLCR_HLINE9_Msk                      
+#define DSI_VLCR_HLINE10_Pos          (10U)                                    
+#define DSI_VLCR_HLINE10_Msk          (0x1UL << DSI_VLCR_HLINE10_Pos)           /*!< 0x00000400 */
+#define DSI_VLCR_HLINE10              DSI_VLCR_HLINE10_Msk                     
+#define DSI_VLCR_HLINE11_Pos          (11U)                                    
+#define DSI_VLCR_HLINE11_Msk          (0x1UL << DSI_VLCR_HLINE11_Pos)           /*!< 0x00000800 */
+#define DSI_VLCR_HLINE11              DSI_VLCR_HLINE11_Msk                     
+#define DSI_VLCR_HLINE12_Pos          (12U)                                    
+#define DSI_VLCR_HLINE12_Msk          (0x1UL << DSI_VLCR_HLINE12_Pos)           /*!< 0x00001000 */
+#define DSI_VLCR_HLINE12              DSI_VLCR_HLINE12_Msk                     
+#define DSI_VLCR_HLINE13_Pos          (13U)                                    
+#define DSI_VLCR_HLINE13_Msk          (0x1UL << DSI_VLCR_HLINE13_Pos)           /*!< 0x00002000 */
+#define DSI_VLCR_HLINE13              DSI_VLCR_HLINE13_Msk                     
+#define DSI_VLCR_HLINE14_Pos          (14U)                                    
+#define DSI_VLCR_HLINE14_Msk          (0x1UL << DSI_VLCR_HLINE14_Pos)           /*!< 0x00004000 */
+#define DSI_VLCR_HLINE14              DSI_VLCR_HLINE14_Msk                     
+
+/*******************  Bit definition for DSI_VVSACR register  *************/
+#define DSI_VVSACR_VSA_Pos            (0U)                                     
+#define DSI_VVSACR_VSA_Msk            (0x3FFUL << DSI_VVSACR_VSA_Pos)           /*!< 0x000003FF */
+#define DSI_VVSACR_VSA                DSI_VVSACR_VSA_Msk                       /*!< Vertical Synchronism Active duration */
+#define DSI_VVSACR_VSA0_Pos           (0U)                                     
+#define DSI_VVSACR_VSA0_Msk           (0x1UL << DSI_VVSACR_VSA0_Pos)            /*!< 0x00000001 */
+#define DSI_VVSACR_VSA0               DSI_VVSACR_VSA0_Msk                      
+#define DSI_VVSACR_VSA1_Pos           (1U)                                     
+#define DSI_VVSACR_VSA1_Msk           (0x1UL << DSI_VVSACR_VSA1_Pos)            /*!< 0x00000002 */
+#define DSI_VVSACR_VSA1               DSI_VVSACR_VSA1_Msk                      
+#define DSI_VVSACR_VSA2_Pos           (2U)                                     
+#define DSI_VVSACR_VSA2_Msk           (0x1UL << DSI_VVSACR_VSA2_Pos)            /*!< 0x00000004 */
+#define DSI_VVSACR_VSA2               DSI_VVSACR_VSA2_Msk                      
+#define DSI_VVSACR_VSA3_Pos           (3U)                                     
+#define DSI_VVSACR_VSA3_Msk           (0x1UL << DSI_VVSACR_VSA3_Pos)            /*!< 0x00000008 */
+#define DSI_VVSACR_VSA3               DSI_VVSACR_VSA3_Msk                      
+#define DSI_VVSACR_VSA4_Pos           (4U)                                     
+#define DSI_VVSACR_VSA4_Msk           (0x1UL << DSI_VVSACR_VSA4_Pos)            /*!< 0x00000010 */
+#define DSI_VVSACR_VSA4               DSI_VVSACR_VSA4_Msk                      
+#define DSI_VVSACR_VSA5_Pos           (5U)                                     
+#define DSI_VVSACR_VSA5_Msk           (0x1UL << DSI_VVSACR_VSA5_Pos)            /*!< 0x00000020 */
+#define DSI_VVSACR_VSA5               DSI_VVSACR_VSA5_Msk                      
+#define DSI_VVSACR_VSA6_Pos           (6U)                                     
+#define DSI_VVSACR_VSA6_Msk           (0x1UL << DSI_VVSACR_VSA6_Pos)            /*!< 0x00000040 */
+#define DSI_VVSACR_VSA6               DSI_VVSACR_VSA6_Msk                      
+#define DSI_VVSACR_VSA7_Pos           (7U)                                     
+#define DSI_VVSACR_VSA7_Msk           (0x1UL << DSI_VVSACR_VSA7_Pos)            /*!< 0x00000080 */
+#define DSI_VVSACR_VSA7               DSI_VVSACR_VSA7_Msk                      
+#define DSI_VVSACR_VSA8_Pos           (8U)                                     
+#define DSI_VVSACR_VSA8_Msk           (0x1UL << DSI_VVSACR_VSA8_Pos)            /*!< 0x00000100 */
+#define DSI_VVSACR_VSA8               DSI_VVSACR_VSA8_Msk                      
+#define DSI_VVSACR_VSA9_Pos           (9U)                                     
+#define DSI_VVSACR_VSA9_Msk           (0x1UL << DSI_VVSACR_VSA9_Pos)            /*!< 0x00000200 */
+#define DSI_VVSACR_VSA9               DSI_VVSACR_VSA9_Msk                      
+
+/*******************  Bit definition for DSI_VVBPCR register  *************/
+#define DSI_VVBPCR_VBP_Pos            (0U)                                     
+#define DSI_VVBPCR_VBP_Msk            (0x3FFUL << DSI_VVBPCR_VBP_Pos)           /*!< 0x000003FF */
+#define DSI_VVBPCR_VBP                DSI_VVBPCR_VBP_Msk                       /*!< Vertical Back-Porch duration */
+#define DSI_VVBPCR_VBP0_Pos           (0U)                                     
+#define DSI_VVBPCR_VBP0_Msk           (0x1UL << DSI_VVBPCR_VBP0_Pos)            /*!< 0x00000001 */
+#define DSI_VVBPCR_VBP0               DSI_VVBPCR_VBP0_Msk                      
+#define DSI_VVBPCR_VBP1_Pos           (1U)                                     
+#define DSI_VVBPCR_VBP1_Msk           (0x1UL << DSI_VVBPCR_VBP1_Pos)            /*!< 0x00000002 */
+#define DSI_VVBPCR_VBP1               DSI_VVBPCR_VBP1_Msk                      
+#define DSI_VVBPCR_VBP2_Pos           (2U)                                     
+#define DSI_VVBPCR_VBP2_Msk           (0x1UL << DSI_VVBPCR_VBP2_Pos)            /*!< 0x00000004 */
+#define DSI_VVBPCR_VBP2               DSI_VVBPCR_VBP2_Msk                      
+#define DSI_VVBPCR_VBP3_Pos           (3U)                                     
+#define DSI_VVBPCR_VBP3_Msk           (0x1UL << DSI_VVBPCR_VBP3_Pos)            /*!< 0x00000008 */
+#define DSI_VVBPCR_VBP3               DSI_VVBPCR_VBP3_Msk                      
+#define DSI_VVBPCR_VBP4_Pos           (4U)                                     
+#define DSI_VVBPCR_VBP4_Msk           (0x1UL << DSI_VVBPCR_VBP4_Pos)            /*!< 0x00000010 */
+#define DSI_VVBPCR_VBP4               DSI_VVBPCR_VBP4_Msk                      
+#define DSI_VVBPCR_VBP5_Pos           (5U)                                     
+#define DSI_VVBPCR_VBP5_Msk           (0x1UL << DSI_VVBPCR_VBP5_Pos)            /*!< 0x00000020 */
+#define DSI_VVBPCR_VBP5               DSI_VVBPCR_VBP5_Msk                      
+#define DSI_VVBPCR_VBP6_Pos           (6U)                                     
+#define DSI_VVBPCR_VBP6_Msk           (0x1UL << DSI_VVBPCR_VBP6_Pos)            /*!< 0x00000040 */
+#define DSI_VVBPCR_VBP6               DSI_VVBPCR_VBP6_Msk                      
+#define DSI_VVBPCR_VBP7_Pos           (7U)                                     
+#define DSI_VVBPCR_VBP7_Msk           (0x1UL << DSI_VVBPCR_VBP7_Pos)            /*!< 0x00000080 */
+#define DSI_VVBPCR_VBP7               DSI_VVBPCR_VBP7_Msk                      
+#define DSI_VVBPCR_VBP8_Pos           (8U)                                     
+#define DSI_VVBPCR_VBP8_Msk           (0x1UL << DSI_VVBPCR_VBP8_Pos)            /*!< 0x00000100 */
+#define DSI_VVBPCR_VBP8               DSI_VVBPCR_VBP8_Msk                      
+#define DSI_VVBPCR_VBP9_Pos           (9U)                                     
+#define DSI_VVBPCR_VBP9_Msk           (0x1UL << DSI_VVBPCR_VBP9_Pos)            /*!< 0x00000200 */
+#define DSI_VVBPCR_VBP9               DSI_VVBPCR_VBP9_Msk                      
+
+/*******************  Bit definition for DSI_VVFPCR register  *************/
+#define DSI_VVFPCR_VFP_Pos            (0U)                                     
+#define DSI_VVFPCR_VFP_Msk            (0x3FFUL << DSI_VVFPCR_VFP_Pos)           /*!< 0x000003FF */
+#define DSI_VVFPCR_VFP                DSI_VVFPCR_VFP_Msk                       /*!< Vertical Front-Porch duration */
+#define DSI_VVFPCR_VFP0_Pos           (0U)                                     
+#define DSI_VVFPCR_VFP0_Msk           (0x1UL << DSI_VVFPCR_VFP0_Pos)            /*!< 0x00000001 */
+#define DSI_VVFPCR_VFP0               DSI_VVFPCR_VFP0_Msk                      
+#define DSI_VVFPCR_VFP1_Pos           (1U)                                     
+#define DSI_VVFPCR_VFP1_Msk           (0x1UL << DSI_VVFPCR_VFP1_Pos)            /*!< 0x00000002 */
+#define DSI_VVFPCR_VFP1               DSI_VVFPCR_VFP1_Msk                      
+#define DSI_VVFPCR_VFP2_Pos           (2U)                                     
+#define DSI_VVFPCR_VFP2_Msk           (0x1UL << DSI_VVFPCR_VFP2_Pos)            /*!< 0x00000004 */
+#define DSI_VVFPCR_VFP2               DSI_VVFPCR_VFP2_Msk                      
+#define DSI_VVFPCR_VFP3_Pos           (3U)                                     
+#define DSI_VVFPCR_VFP3_Msk           (0x1UL << DSI_VVFPCR_VFP3_Pos)            /*!< 0x00000008 */
+#define DSI_VVFPCR_VFP3               DSI_VVFPCR_VFP3_Msk                      
+#define DSI_VVFPCR_VFP4_Pos           (4U)                                     
+#define DSI_VVFPCR_VFP4_Msk           (0x1UL << DSI_VVFPCR_VFP4_Pos)            /*!< 0x00000010 */
+#define DSI_VVFPCR_VFP4               DSI_VVFPCR_VFP4_Msk                      
+#define DSI_VVFPCR_VFP5_Pos           (5U)                                     
+#define DSI_VVFPCR_VFP5_Msk           (0x1UL << DSI_VVFPCR_VFP5_Pos)            /*!< 0x00000020 */
+#define DSI_VVFPCR_VFP5               DSI_VVFPCR_VFP5_Msk                      
+#define DSI_VVFPCR_VFP6_Pos           (6U)                                     
+#define DSI_VVFPCR_VFP6_Msk           (0x1UL << DSI_VVFPCR_VFP6_Pos)            /*!< 0x00000040 */
+#define DSI_VVFPCR_VFP6               DSI_VVFPCR_VFP6_Msk                      
+#define DSI_VVFPCR_VFP7_Pos           (7U)                                     
+#define DSI_VVFPCR_VFP7_Msk           (0x1UL << DSI_VVFPCR_VFP7_Pos)            /*!< 0x00000080 */
+#define DSI_VVFPCR_VFP7               DSI_VVFPCR_VFP7_Msk                      
+#define DSI_VVFPCR_VFP8_Pos           (8U)                                     
+#define DSI_VVFPCR_VFP8_Msk           (0x1UL << DSI_VVFPCR_VFP8_Pos)            /*!< 0x00000100 */
+#define DSI_VVFPCR_VFP8               DSI_VVFPCR_VFP8_Msk                      
+#define DSI_VVFPCR_VFP9_Pos           (9U)                                     
+#define DSI_VVFPCR_VFP9_Msk           (0x1UL << DSI_VVFPCR_VFP9_Pos)            /*!< 0x00000200 */
+#define DSI_VVFPCR_VFP9               DSI_VVFPCR_VFP9_Msk                      
+
+/*******************  Bit definition for DSI_VVACR register  **************/
+#define DSI_VVACR_VA_Pos              (0U)                                     
+#define DSI_VVACR_VA_Msk              (0x3FFFUL << DSI_VVACR_VA_Pos)            /*!< 0x00003FFF */
+#define DSI_VVACR_VA                  DSI_VVACR_VA_Msk                         /*!< Vertical Active duration */
+#define DSI_VVACR_VA0_Pos             (0U)                                     
+#define DSI_VVACR_VA0_Msk             (0x1UL << DSI_VVACR_VA0_Pos)              /*!< 0x00000001 */
+#define DSI_VVACR_VA0                 DSI_VVACR_VA0_Msk                        
+#define DSI_VVACR_VA1_Pos             (1U)                                     
+#define DSI_VVACR_VA1_Msk             (0x1UL << DSI_VVACR_VA1_Pos)              /*!< 0x00000002 */
+#define DSI_VVACR_VA1                 DSI_VVACR_VA1_Msk                        
+#define DSI_VVACR_VA2_Pos             (2U)                                     
+#define DSI_VVACR_VA2_Msk             (0x1UL << DSI_VVACR_VA2_Pos)              /*!< 0x00000004 */
+#define DSI_VVACR_VA2                 DSI_VVACR_VA2_Msk                        
+#define DSI_VVACR_VA3_Pos             (3U)                                     
+#define DSI_VVACR_VA3_Msk             (0x1UL << DSI_VVACR_VA3_Pos)              /*!< 0x00000008 */
+#define DSI_VVACR_VA3                 DSI_VVACR_VA3_Msk                        
+#define DSI_VVACR_VA4_Pos             (4U)                                     
+#define DSI_VVACR_VA4_Msk             (0x1UL << DSI_VVACR_VA4_Pos)              /*!< 0x00000010 */
+#define DSI_VVACR_VA4                 DSI_VVACR_VA4_Msk                        
+#define DSI_VVACR_VA5_Pos             (5U)                                     
+#define DSI_VVACR_VA5_Msk             (0x1UL << DSI_VVACR_VA5_Pos)              /*!< 0x00000020 */
+#define DSI_VVACR_VA5                 DSI_VVACR_VA5_Msk                        
+#define DSI_VVACR_VA6_Pos             (6U)                                     
+#define DSI_VVACR_VA6_Msk             (0x1UL << DSI_VVACR_VA6_Pos)              /*!< 0x00000040 */
+#define DSI_VVACR_VA6                 DSI_VVACR_VA6_Msk                        
+#define DSI_VVACR_VA7_Pos             (7U)                                     
+#define DSI_VVACR_VA7_Msk             (0x1UL << DSI_VVACR_VA7_Pos)              /*!< 0x00000080 */
+#define DSI_VVACR_VA7                 DSI_VVACR_VA7_Msk                        
+#define DSI_VVACR_VA8_Pos             (8U)                                     
+#define DSI_VVACR_VA8_Msk             (0x1UL << DSI_VVACR_VA8_Pos)              /*!< 0x00000100 */
+#define DSI_VVACR_VA8                 DSI_VVACR_VA8_Msk                        
+#define DSI_VVACR_VA9_Pos             (9U)                                     
+#define DSI_VVACR_VA9_Msk             (0x1UL << DSI_VVACR_VA9_Pos)              /*!< 0x00000200 */
+#define DSI_VVACR_VA9                 DSI_VVACR_VA9_Msk                        
+#define DSI_VVACR_VA10_Pos            (10U)                                    
+#define DSI_VVACR_VA10_Msk            (0x1UL << DSI_VVACR_VA10_Pos)             /*!< 0x00000400 */
+#define DSI_VVACR_VA10                DSI_VVACR_VA10_Msk                       
+#define DSI_VVACR_VA11_Pos            (11U)                                    
+#define DSI_VVACR_VA11_Msk            (0x1UL << DSI_VVACR_VA11_Pos)             /*!< 0x00000800 */
+#define DSI_VVACR_VA11                DSI_VVACR_VA11_Msk                       
+#define DSI_VVACR_VA12_Pos            (12U)                                    
+#define DSI_VVACR_VA12_Msk            (0x1UL << DSI_VVACR_VA12_Pos)             /*!< 0x00001000 */
+#define DSI_VVACR_VA12                DSI_VVACR_VA12_Msk                       
+#define DSI_VVACR_VA13_Pos            (13U)                                    
+#define DSI_VVACR_VA13_Msk            (0x1UL << DSI_VVACR_VA13_Pos)             /*!< 0x00002000 */
+#define DSI_VVACR_VA13                DSI_VVACR_VA13_Msk                       
+
+/*******************  Bit definition for DSI_LCCR register  ***************/
+#define DSI_LCCR_CMDSIZE_Pos          (0U)                                     
+#define DSI_LCCR_CMDSIZE_Msk          (0xFFFFUL << DSI_LCCR_CMDSIZE_Pos)        /*!< 0x0000FFFF */
+#define DSI_LCCR_CMDSIZE              DSI_LCCR_CMDSIZE_Msk                     /*!< Command Size */
+#define DSI_LCCR_CMDSIZE0_Pos         (0U)                                     
+#define DSI_LCCR_CMDSIZE0_Msk         (0x1UL << DSI_LCCR_CMDSIZE0_Pos)          /*!< 0x00000001 */
+#define DSI_LCCR_CMDSIZE0             DSI_LCCR_CMDSIZE0_Msk                    
+#define DSI_LCCR_CMDSIZE1_Pos         (1U)                                     
+#define DSI_LCCR_CMDSIZE1_Msk         (0x1UL << DSI_LCCR_CMDSIZE1_Pos)          /*!< 0x00000002 */
+#define DSI_LCCR_CMDSIZE1             DSI_LCCR_CMDSIZE1_Msk                    
+#define DSI_LCCR_CMDSIZE2_Pos         (2U)                                     
+#define DSI_LCCR_CMDSIZE2_Msk         (0x1UL << DSI_LCCR_CMDSIZE2_Pos)          /*!< 0x00000004 */
+#define DSI_LCCR_CMDSIZE2             DSI_LCCR_CMDSIZE2_Msk                    
+#define DSI_LCCR_CMDSIZE3_Pos         (3U)                                     
+#define DSI_LCCR_CMDSIZE3_Msk         (0x1UL << DSI_LCCR_CMDSIZE3_Pos)          /*!< 0x00000008 */
+#define DSI_LCCR_CMDSIZE3             DSI_LCCR_CMDSIZE3_Msk                    
+#define DSI_LCCR_CMDSIZE4_Pos         (4U)                                     
+#define DSI_LCCR_CMDSIZE4_Msk         (0x1UL << DSI_LCCR_CMDSIZE4_Pos)          /*!< 0x00000010 */
+#define DSI_LCCR_CMDSIZE4             DSI_LCCR_CMDSIZE4_Msk                    
+#define DSI_LCCR_CMDSIZE5_Pos         (5U)                                     
+#define DSI_LCCR_CMDSIZE5_Msk         (0x1UL << DSI_LCCR_CMDSIZE5_Pos)          /*!< 0x00000020 */
+#define DSI_LCCR_CMDSIZE5             DSI_LCCR_CMDSIZE5_Msk                    
+#define DSI_LCCR_CMDSIZE6_Pos         (6U)                                     
+#define DSI_LCCR_CMDSIZE6_Msk         (0x1UL << DSI_LCCR_CMDSIZE6_Pos)          /*!< 0x00000040 */
+#define DSI_LCCR_CMDSIZE6             DSI_LCCR_CMDSIZE6_Msk                    
+#define DSI_LCCR_CMDSIZE7_Pos         (7U)                                     
+#define DSI_LCCR_CMDSIZE7_Msk         (0x1UL << DSI_LCCR_CMDSIZE7_Pos)          /*!< 0x00000080 */
+#define DSI_LCCR_CMDSIZE7             DSI_LCCR_CMDSIZE7_Msk                    
+#define DSI_LCCR_CMDSIZE8_Pos         (8U)                                     
+#define DSI_LCCR_CMDSIZE8_Msk         (0x1UL << DSI_LCCR_CMDSIZE8_Pos)          /*!< 0x00000100 */
+#define DSI_LCCR_CMDSIZE8             DSI_LCCR_CMDSIZE8_Msk                    
+#define DSI_LCCR_CMDSIZE9_Pos         (9U)                                     
+#define DSI_LCCR_CMDSIZE9_Msk         (0x1UL << DSI_LCCR_CMDSIZE9_Pos)          /*!< 0x00000200 */
+#define DSI_LCCR_CMDSIZE9             DSI_LCCR_CMDSIZE9_Msk                    
+#define DSI_LCCR_CMDSIZE10_Pos        (10U)                                    
+#define DSI_LCCR_CMDSIZE10_Msk        (0x1UL << DSI_LCCR_CMDSIZE10_Pos)         /*!< 0x00000400 */
+#define DSI_LCCR_CMDSIZE10            DSI_LCCR_CMDSIZE10_Msk                   
+#define DSI_LCCR_CMDSIZE11_Pos        (11U)                                    
+#define DSI_LCCR_CMDSIZE11_Msk        (0x1UL << DSI_LCCR_CMDSIZE11_Pos)         /*!< 0x00000800 */
+#define DSI_LCCR_CMDSIZE11            DSI_LCCR_CMDSIZE11_Msk                   
+#define DSI_LCCR_CMDSIZE12_Pos        (12U)                                    
+#define DSI_LCCR_CMDSIZE12_Msk        (0x1UL << DSI_LCCR_CMDSIZE12_Pos)         /*!< 0x00001000 */
+#define DSI_LCCR_CMDSIZE12            DSI_LCCR_CMDSIZE12_Msk                   
+#define DSI_LCCR_CMDSIZE13_Pos        (13U)                                    
+#define DSI_LCCR_CMDSIZE13_Msk        (0x1UL << DSI_LCCR_CMDSIZE13_Pos)         /*!< 0x00002000 */
+#define DSI_LCCR_CMDSIZE13            DSI_LCCR_CMDSIZE13_Msk                   
+#define DSI_LCCR_CMDSIZE14_Pos        (14U)                                    
+#define DSI_LCCR_CMDSIZE14_Msk        (0x1UL << DSI_LCCR_CMDSIZE14_Pos)         /*!< 0x00004000 */
+#define DSI_LCCR_CMDSIZE14            DSI_LCCR_CMDSIZE14_Msk                   
+#define DSI_LCCR_CMDSIZE15_Pos        (15U)                                    
+#define DSI_LCCR_CMDSIZE15_Msk        (0x1UL << DSI_LCCR_CMDSIZE15_Pos)         /*!< 0x00008000 */
+#define DSI_LCCR_CMDSIZE15            DSI_LCCR_CMDSIZE15_Msk                   
+
+/*******************  Bit definition for DSI_CMCR register  ***************/
+#define DSI_CMCR_TEARE_Pos            (0U)                                     
+#define DSI_CMCR_TEARE_Msk            (0x1UL << DSI_CMCR_TEARE_Pos)             /*!< 0x00000001 */
+#define DSI_CMCR_TEARE                DSI_CMCR_TEARE_Msk                       /*!< Tearing Effect Acknowledge Request Enable */
+#define DSI_CMCR_ARE_Pos              (1U)                                     
+#define DSI_CMCR_ARE_Msk              (0x1UL << DSI_CMCR_ARE_Pos)               /*!< 0x00000002 */
+#define DSI_CMCR_ARE                  DSI_CMCR_ARE_Msk                         /*!< Acknowledge Request Enable */
+#define DSI_CMCR_GSW0TX_Pos           (8U)                                     
+#define DSI_CMCR_GSW0TX_Msk           (0x1UL << DSI_CMCR_GSW0TX_Pos)            /*!< 0x00000100 */
+#define DSI_CMCR_GSW0TX               DSI_CMCR_GSW0TX_Msk                      /*!< Generic Short Write Zero parameters Transmission */
+#define DSI_CMCR_GSW1TX_Pos           (9U)                                     
+#define DSI_CMCR_GSW1TX_Msk           (0x1UL << DSI_CMCR_GSW1TX_Pos)            /*!< 0x00000200 */
+#define DSI_CMCR_GSW1TX               DSI_CMCR_GSW1TX_Msk                      /*!< Generic Short Write One parameters Transmission */
+#define DSI_CMCR_GSW2TX_Pos           (10U)                                    
+#define DSI_CMCR_GSW2TX_Msk           (0x1UL << DSI_CMCR_GSW2TX_Pos)            /*!< 0x00000400 */
+#define DSI_CMCR_GSW2TX               DSI_CMCR_GSW2TX_Msk                      /*!< Generic Short Write Two parameters Transmission */
+#define DSI_CMCR_GSR0TX_Pos           (11U)                                    
+#define DSI_CMCR_GSR0TX_Msk           (0x1UL << DSI_CMCR_GSR0TX_Pos)            /*!< 0x00000800 */
+#define DSI_CMCR_GSR0TX               DSI_CMCR_GSR0TX_Msk                      /*!< Generic Short Read Zero parameters Transmission */
+#define DSI_CMCR_GSR1TX_Pos           (12U)                                    
+#define DSI_CMCR_GSR1TX_Msk           (0x1UL << DSI_CMCR_GSR1TX_Pos)            /*!< 0x00001000 */
+#define DSI_CMCR_GSR1TX               DSI_CMCR_GSR1TX_Msk                      /*!< Generic Short Read One parameters Transmission */
+#define DSI_CMCR_GSR2TX_Pos           (13U)                                    
+#define DSI_CMCR_GSR2TX_Msk           (0x1UL << DSI_CMCR_GSR2TX_Pos)            /*!< 0x00002000 */
+#define DSI_CMCR_GSR2TX               DSI_CMCR_GSR2TX_Msk                      /*!< Generic Short Read Two parameters Transmission */
+#define DSI_CMCR_GLWTX_Pos            (14U)                                    
+#define DSI_CMCR_GLWTX_Msk            (0x1UL << DSI_CMCR_GLWTX_Pos)             /*!< 0x00004000 */
+#define DSI_CMCR_GLWTX                DSI_CMCR_GLWTX_Msk                       /*!< Generic Long Write Transmission */
+#define DSI_CMCR_DSW0TX_Pos           (16U)                                    
+#define DSI_CMCR_DSW0TX_Msk           (0x1UL << DSI_CMCR_DSW0TX_Pos)            /*!< 0x00010000 */
+#define DSI_CMCR_DSW0TX               DSI_CMCR_DSW0TX_Msk                      /*!< DCS Short Write Zero parameter Transmission */
+#define DSI_CMCR_DSW1TX_Pos           (17U)                                    
+#define DSI_CMCR_DSW1TX_Msk           (0x1UL << DSI_CMCR_DSW1TX_Pos)            /*!< 0x00020000 */
+#define DSI_CMCR_DSW1TX               DSI_CMCR_DSW1TX_Msk                      /*!< DCS Short Read One parameter Transmission */
+#define DSI_CMCR_DSR0TX_Pos           (18U)                                    
+#define DSI_CMCR_DSR0TX_Msk           (0x1UL << DSI_CMCR_DSR0TX_Pos)            /*!< 0x00040000 */
+#define DSI_CMCR_DSR0TX               DSI_CMCR_DSR0TX_Msk                      /*!< DCS Short Read Zero parameter Transmission */
+#define DSI_CMCR_DLWTX_Pos            (19U)                                    
+#define DSI_CMCR_DLWTX_Msk            (0x1UL << DSI_CMCR_DLWTX_Pos)             /*!< 0x00080000 */
+#define DSI_CMCR_DLWTX                DSI_CMCR_DLWTX_Msk                       /*!< DCS Long Write Transmission */
+#define DSI_CMCR_MRDPS_Pos            (24U)                                    
+#define DSI_CMCR_MRDPS_Msk            (0x1UL << DSI_CMCR_MRDPS_Pos)             /*!< 0x01000000 */
+#define DSI_CMCR_MRDPS                DSI_CMCR_MRDPS_Msk                       /*!< Maximum Read Packet Size */
+
+/*******************  Bit definition for DSI_GHCR register  ***************/
+#define DSI_GHCR_DT_Pos               (0U)                                     
+#define DSI_GHCR_DT_Msk               (0x3FUL << DSI_GHCR_DT_Pos)               /*!< 0x0000003F */
+#define DSI_GHCR_DT                   DSI_GHCR_DT_Msk                          /*!< Type */
+#define DSI_GHCR_DT0_Pos              (0U)                                     
+#define DSI_GHCR_DT0_Msk              (0x1UL << DSI_GHCR_DT0_Pos)               /*!< 0x00000001 */
+#define DSI_GHCR_DT0                  DSI_GHCR_DT0_Msk                         
+#define DSI_GHCR_DT1_Pos              (1U)                                     
+#define DSI_GHCR_DT1_Msk              (0x1UL << DSI_GHCR_DT1_Pos)               /*!< 0x00000002 */
+#define DSI_GHCR_DT1                  DSI_GHCR_DT1_Msk                         
+#define DSI_GHCR_DT2_Pos              (2U)                                     
+#define DSI_GHCR_DT2_Msk              (0x1UL << DSI_GHCR_DT2_Pos)               /*!< 0x00000004 */
+#define DSI_GHCR_DT2                  DSI_GHCR_DT2_Msk                         
+#define DSI_GHCR_DT3_Pos              (3U)                                     
+#define DSI_GHCR_DT3_Msk              (0x1UL << DSI_GHCR_DT3_Pos)               /*!< 0x00000008 */
+#define DSI_GHCR_DT3                  DSI_GHCR_DT3_Msk                         
+#define DSI_GHCR_DT4_Pos              (4U)                                     
+#define DSI_GHCR_DT4_Msk              (0x1UL << DSI_GHCR_DT4_Pos)               /*!< 0x00000010 */
+#define DSI_GHCR_DT4                  DSI_GHCR_DT4_Msk                         
+#define DSI_GHCR_DT5_Pos              (5U)                                     
+#define DSI_GHCR_DT5_Msk              (0x1UL << DSI_GHCR_DT5_Pos)               /*!< 0x00000020 */
+#define DSI_GHCR_DT5                  DSI_GHCR_DT5_Msk                         
+
+#define DSI_GHCR_VCID_Pos             (6U)                                     
+#define DSI_GHCR_VCID_Msk             (0x3UL << DSI_GHCR_VCID_Pos)              /*!< 0x000000C0 */
+#define DSI_GHCR_VCID                 DSI_GHCR_VCID_Msk                        /*!< Channel */
+#define DSI_GHCR_VCID0_Pos            (6U)                                     
+#define DSI_GHCR_VCID0_Msk            (0x1UL << DSI_GHCR_VCID0_Pos)             /*!< 0x00000040 */
+#define DSI_GHCR_VCID0                DSI_GHCR_VCID0_Msk                       
+#define DSI_GHCR_VCID1_Pos            (7U)                                     
+#define DSI_GHCR_VCID1_Msk            (0x1UL << DSI_GHCR_VCID1_Pos)             /*!< 0x00000080 */
+#define DSI_GHCR_VCID1                DSI_GHCR_VCID1_Msk                       
+
+#define DSI_GHCR_WCLSB_Pos            (8U)                                     
+#define DSI_GHCR_WCLSB_Msk            (0xFFUL << DSI_GHCR_WCLSB_Pos)            /*!< 0x0000FF00 */
+#define DSI_GHCR_WCLSB                DSI_GHCR_WCLSB_Msk                       /*!< WordCount LSB */
+#define DSI_GHCR_WCLSB0_Pos           (8U)                                     
+#define DSI_GHCR_WCLSB0_Msk           (0x1UL << DSI_GHCR_WCLSB0_Pos)            /*!< 0x00000100 */
+#define DSI_GHCR_WCLSB0               DSI_GHCR_WCLSB0_Msk                      
+#define DSI_GHCR_WCLSB1_Pos           (9U)                                     
+#define DSI_GHCR_WCLSB1_Msk           (0x1UL << DSI_GHCR_WCLSB1_Pos)            /*!< 0x00000200 */
+#define DSI_GHCR_WCLSB1               DSI_GHCR_WCLSB1_Msk                      
+#define DSI_GHCR_WCLSB2_Pos           (10U)                                    
+#define DSI_GHCR_WCLSB2_Msk           (0x1UL << DSI_GHCR_WCLSB2_Pos)            /*!< 0x00000400 */
+#define DSI_GHCR_WCLSB2               DSI_GHCR_WCLSB2_Msk                      
+#define DSI_GHCR_WCLSB3_Pos           (11U)                                    
+#define DSI_GHCR_WCLSB3_Msk           (0x1UL << DSI_GHCR_WCLSB3_Pos)            /*!< 0x00000800 */
+#define DSI_GHCR_WCLSB3               DSI_GHCR_WCLSB3_Msk                      
+#define DSI_GHCR_WCLSB4_Pos           (12U)                                    
+#define DSI_GHCR_WCLSB4_Msk           (0x1UL << DSI_GHCR_WCLSB4_Pos)            /*!< 0x00001000 */
+#define DSI_GHCR_WCLSB4               DSI_GHCR_WCLSB4_Msk                      
+#define DSI_GHCR_WCLSB5_Pos           (13U)                                    
+#define DSI_GHCR_WCLSB5_Msk           (0x1UL << DSI_GHCR_WCLSB5_Pos)            /*!< 0x00002000 */
+#define DSI_GHCR_WCLSB5               DSI_GHCR_WCLSB5_Msk                      
+#define DSI_GHCR_WCLSB6_Pos           (14U)                                    
+#define DSI_GHCR_WCLSB6_Msk           (0x1UL << DSI_GHCR_WCLSB6_Pos)            /*!< 0x00004000 */
+#define DSI_GHCR_WCLSB6               DSI_GHCR_WCLSB6_Msk                      
+#define DSI_GHCR_WCLSB7_Pos           (15U)                                    
+#define DSI_GHCR_WCLSB7_Msk           (0x1UL << DSI_GHCR_WCLSB7_Pos)            /*!< 0x00008000 */
+#define DSI_GHCR_WCLSB7               DSI_GHCR_WCLSB7_Msk                      
+
+#define DSI_GHCR_WCMSB_Pos            (16U)                                    
+#define DSI_GHCR_WCMSB_Msk            (0xFFUL << DSI_GHCR_WCMSB_Pos)            /*!< 0x00FF0000 */
+#define DSI_GHCR_WCMSB                DSI_GHCR_WCMSB_Msk                       /*!< WordCount MSB */
+#define DSI_GHCR_WCMSB0_Pos           (16U)                                    
+#define DSI_GHCR_WCMSB0_Msk           (0x1UL << DSI_GHCR_WCMSB0_Pos)            /*!< 0x00010000 */
+#define DSI_GHCR_WCMSB0               DSI_GHCR_WCMSB0_Msk                      
+#define DSI_GHCR_WCMSB1_Pos           (17U)                                    
+#define DSI_GHCR_WCMSB1_Msk           (0x1UL << DSI_GHCR_WCMSB1_Pos)            /*!< 0x00020000 */
+#define DSI_GHCR_WCMSB1               DSI_GHCR_WCMSB1_Msk                      
+#define DSI_GHCR_WCMSB2_Pos           (18U)                                    
+#define DSI_GHCR_WCMSB2_Msk           (0x1UL << DSI_GHCR_WCMSB2_Pos)            /*!< 0x00040000 */
+#define DSI_GHCR_WCMSB2               DSI_GHCR_WCMSB2_Msk                      
+#define DSI_GHCR_WCMSB3_Pos           (19U)                                    
+#define DSI_GHCR_WCMSB3_Msk           (0x1UL << DSI_GHCR_WCMSB3_Pos)            /*!< 0x00080000 */
+#define DSI_GHCR_WCMSB3               DSI_GHCR_WCMSB3_Msk                      
+#define DSI_GHCR_WCMSB4_Pos           (20U)                                    
+#define DSI_GHCR_WCMSB4_Msk           (0x1UL << DSI_GHCR_WCMSB4_Pos)            /*!< 0x00100000 */
+#define DSI_GHCR_WCMSB4               DSI_GHCR_WCMSB4_Msk                      
+#define DSI_GHCR_WCMSB5_Pos           (21U)                                    
+#define DSI_GHCR_WCMSB5_Msk           (0x1UL << DSI_GHCR_WCMSB5_Pos)            /*!< 0x00200000 */
+#define DSI_GHCR_WCMSB5               DSI_GHCR_WCMSB5_Msk                      
+#define DSI_GHCR_WCMSB6_Pos           (22U)                                    
+#define DSI_GHCR_WCMSB6_Msk           (0x1UL << DSI_GHCR_WCMSB6_Pos)            /*!< 0x00400000 */
+#define DSI_GHCR_WCMSB6               DSI_GHCR_WCMSB6_Msk                      
+#define DSI_GHCR_WCMSB7_Pos           (23U)                                    
+#define DSI_GHCR_WCMSB7_Msk           (0x1UL << DSI_GHCR_WCMSB7_Pos)            /*!< 0x00800000 */
+#define DSI_GHCR_WCMSB7               DSI_GHCR_WCMSB7_Msk                      
+
+/*******************  Bit definition for DSI_GPDR register  ***************/
+#define DSI_GPDR_DATA1_Pos            (0U)                                     
+#define DSI_GPDR_DATA1_Msk            (0xFFUL << DSI_GPDR_DATA1_Pos)            /*!< 0x000000FF */
+#define DSI_GPDR_DATA1                DSI_GPDR_DATA1_Msk                       /*!< Payload Byte 1 */
+#define DSI_GPDR_DATA1_0              (0x01UL << DSI_GPDR_DATA1_Pos)            /*!< 0x00000001 */
+#define DSI_GPDR_DATA1_1              (0x02UL << DSI_GPDR_DATA1_Pos)            /*!< 0x00000002 */
+#define DSI_GPDR_DATA1_2              (0x04UL << DSI_GPDR_DATA1_Pos)            /*!< 0x00000004 */
+#define DSI_GPDR_DATA1_3              (0x08UL << DSI_GPDR_DATA1_Pos)            /*!< 0x00000008 */
+#define DSI_GPDR_DATA1_4              (0x10UL << DSI_GPDR_DATA1_Pos)            /*!< 0x00000010 */
+#define DSI_GPDR_DATA1_5              (0x20UL << DSI_GPDR_DATA1_Pos)            /*!< 0x00000020 */
+#define DSI_GPDR_DATA1_6              (0x40UL << DSI_GPDR_DATA1_Pos)            /*!< 0x00000040 */
+#define DSI_GPDR_DATA1_7              (0x80UL << DSI_GPDR_DATA1_Pos)            /*!< 0x00000080 */
+
+#define DSI_GPDR_DATA2_Pos            (8U)                                     
+#define DSI_GPDR_DATA2_Msk            (0xFFUL << DSI_GPDR_DATA2_Pos)            /*!< 0x0000FF00 */
+#define DSI_GPDR_DATA2                DSI_GPDR_DATA2_Msk                       /*!< Payload Byte 2 */
+#define DSI_GPDR_DATA2_0              (0x01UL << DSI_GPDR_DATA2_Pos)            /*!< 0x00000100 */
+#define DSI_GPDR_DATA2_1              (0x02UL << DSI_GPDR_DATA2_Pos)            /*!< 0x00000200 */
+#define DSI_GPDR_DATA2_2              (0x04UL << DSI_GPDR_DATA2_Pos)            /*!< 0x00000400 */
+#define DSI_GPDR_DATA2_3              (0x08UL << DSI_GPDR_DATA2_Pos)            /*!< 0x00000800 */
+#define DSI_GPDR_DATA2_4              (0x10UL << DSI_GPDR_DATA2_Pos)            /*!< 0x00001000 */
+#define DSI_GPDR_DATA2_5              (0x20UL << DSI_GPDR_DATA2_Pos)            /*!< 0x00002000 */
+#define DSI_GPDR_DATA2_6              (0x40UL << DSI_GPDR_DATA2_Pos)            /*!< 0x00004000 */
+#define DSI_GPDR_DATA2_7              (0x80UL << DSI_GPDR_DATA2_Pos)            /*!< 0x00008000 */
+
+#define DSI_GPDR_DATA3_Pos            (16U)                                    
+#define DSI_GPDR_DATA3_Msk            (0xFFUL << DSI_GPDR_DATA3_Pos)            /*!< 0x00FF0000 */
+#define DSI_GPDR_DATA3                DSI_GPDR_DATA3_Msk                       /*!< Payload Byte 3 */
+#define DSI_GPDR_DATA3_0              (0x01UL << DSI_GPDR_DATA3_Pos)            /*!< 0x00010000 */
+#define DSI_GPDR_DATA3_1              (0x02UL << DSI_GPDR_DATA3_Pos)            /*!< 0x00020000 */
+#define DSI_GPDR_DATA3_2              (0x04UL << DSI_GPDR_DATA3_Pos)            /*!< 0x00040000 */
+#define DSI_GPDR_DATA3_3              (0x08UL << DSI_GPDR_DATA3_Pos)            /*!< 0x00080000 */
+#define DSI_GPDR_DATA3_4              (0x10UL << DSI_GPDR_DATA3_Pos)            /*!< 0x00100000 */
+#define DSI_GPDR_DATA3_5              (0x20UL << DSI_GPDR_DATA3_Pos)            /*!< 0x00200000 */
+#define DSI_GPDR_DATA3_6              (0x40UL << DSI_GPDR_DATA3_Pos)            /*!< 0x00400000 */
+#define DSI_GPDR_DATA3_7              (0x80UL << DSI_GPDR_DATA3_Pos)            /*!< 0x00800000 */
+
+#define DSI_GPDR_DATA4_Pos            (24U)                                    
+#define DSI_GPDR_DATA4_Msk            (0xFFUL << DSI_GPDR_DATA4_Pos)            /*!< 0xFF000000 */
+#define DSI_GPDR_DATA4                DSI_GPDR_DATA4_Msk                       /*!< Payload Byte 4 */
+#define DSI_GPDR_DATA4_0              (0x01UL << DSI_GPDR_DATA4_Pos)            /*!< 0x01000000 */
+#define DSI_GPDR_DATA4_1              (0x02UL << DSI_GPDR_DATA4_Pos)            /*!< 0x02000000 */
+#define DSI_GPDR_DATA4_2              (0x04UL << DSI_GPDR_DATA4_Pos)            /*!< 0x04000000 */
+#define DSI_GPDR_DATA4_3              (0x08UL << DSI_GPDR_DATA4_Pos)            /*!< 0x08000000 */
+#define DSI_GPDR_DATA4_4              (0x10UL << DSI_GPDR_DATA4_Pos)            /*!< 0x10000000 */
+#define DSI_GPDR_DATA4_5              (0x20UL << DSI_GPDR_DATA4_Pos)            /*!< 0x20000000 */
+#define DSI_GPDR_DATA4_6              (0x40UL << DSI_GPDR_DATA4_Pos)            /*!< 0x40000000 */
+#define DSI_GPDR_DATA4_7              (0x80UL << DSI_GPDR_DATA4_Pos)            /*!< 0x80000000 */
+
+/*******************  Bit definition for DSI_GPSR register  ***************/
+#define DSI_GPSR_CMDFE_Pos            (0U)                                     
+#define DSI_GPSR_CMDFE_Msk            (0x1UL << DSI_GPSR_CMDFE_Pos)             /*!< 0x00000001 */
+#define DSI_GPSR_CMDFE                DSI_GPSR_CMDFE_Msk                       /*!< Command FIFO Empty */
+#define DSI_GPSR_CMDFF_Pos            (1U)                                     
+#define DSI_GPSR_CMDFF_Msk            (0x1UL << DSI_GPSR_CMDFF_Pos)             /*!< 0x00000002 */
+#define DSI_GPSR_CMDFF                DSI_GPSR_CMDFF_Msk                       /*!< Command FIFO Full */
+#define DSI_GPSR_PWRFE_Pos            (2U)                                     
+#define DSI_GPSR_PWRFE_Msk            (0x1UL << DSI_GPSR_PWRFE_Pos)             /*!< 0x00000004 */
+#define DSI_GPSR_PWRFE                DSI_GPSR_PWRFE_Msk                       /*!< Payload Write FIFO Empty */
+#define DSI_GPSR_PWRFF_Pos            (3U)                                     
+#define DSI_GPSR_PWRFF_Msk            (0x1UL << DSI_GPSR_PWRFF_Pos)             /*!< 0x00000008 */
+#define DSI_GPSR_PWRFF                DSI_GPSR_PWRFF_Msk                       /*!< Payload Write FIFO Full */
+#define DSI_GPSR_PRDFE_Pos            (4U)                                     
+#define DSI_GPSR_PRDFE_Msk            (0x1UL << DSI_GPSR_PRDFE_Pos)             /*!< 0x00000010 */
+#define DSI_GPSR_PRDFE                DSI_GPSR_PRDFE_Msk                       /*!< Payload Read FIFO Empty */
+#define DSI_GPSR_PRDFF_Pos            (5U)                                     
+#define DSI_GPSR_PRDFF_Msk            (0x1UL << DSI_GPSR_PRDFF_Pos)             /*!< 0x00000020 */
+#define DSI_GPSR_PRDFF                DSI_GPSR_PRDFF_Msk                       /*!< Payload Read FIFO Full */
+#define DSI_GPSR_RCB_Pos              (6U)                                     
+#define DSI_GPSR_RCB_Msk              (0x1UL << DSI_GPSR_RCB_Pos)               /*!< 0x00000040 */
+#define DSI_GPSR_RCB                  DSI_GPSR_RCB_Msk                         /*!< Read Command Busy */
+
+/*******************  Bit definition for DSI_TCCR0 register  **************/
+#define DSI_TCCR0_LPRX_TOCNT_Pos      (0U)                                     
+#define DSI_TCCR0_LPRX_TOCNT_Msk      (0xFFFFUL << DSI_TCCR0_LPRX_TOCNT_Pos)    /*!< 0x0000FFFF */
+#define DSI_TCCR0_LPRX_TOCNT          DSI_TCCR0_LPRX_TOCNT_Msk                 /*!< Low-power Reception Timeout Counter */
+#define DSI_TCCR0_LPRX_TOCNT0_Pos     (0U)                                     
+#define DSI_TCCR0_LPRX_TOCNT0_Msk     (0x1UL << DSI_TCCR0_LPRX_TOCNT0_Pos)      /*!< 0x00000001 */
+#define DSI_TCCR0_LPRX_TOCNT0         DSI_TCCR0_LPRX_TOCNT0_Msk                
+#define DSI_TCCR0_LPRX_TOCNT1_Pos     (1U)                                     
+#define DSI_TCCR0_LPRX_TOCNT1_Msk     (0x1UL << DSI_TCCR0_LPRX_TOCNT1_Pos)      /*!< 0x00000002 */
+#define DSI_TCCR0_LPRX_TOCNT1         DSI_TCCR0_LPRX_TOCNT1_Msk                
+#define DSI_TCCR0_LPRX_TOCNT2_Pos     (2U)                                     
+#define DSI_TCCR0_LPRX_TOCNT2_Msk     (0x1UL << DSI_TCCR0_LPRX_TOCNT2_Pos)      /*!< 0x00000004 */
+#define DSI_TCCR0_LPRX_TOCNT2         DSI_TCCR0_LPRX_TOCNT2_Msk                
+#define DSI_TCCR0_LPRX_TOCNT3_Pos     (3U)                                     
+#define DSI_TCCR0_LPRX_TOCNT3_Msk     (0x1UL << DSI_TCCR0_LPRX_TOCNT3_Pos)      /*!< 0x00000008 */
+#define DSI_TCCR0_LPRX_TOCNT3         DSI_TCCR0_LPRX_TOCNT3_Msk                
+#define DSI_TCCR0_LPRX_TOCNT4_Pos     (4U)                                     
+#define DSI_TCCR0_LPRX_TOCNT4_Msk     (0x1UL << DSI_TCCR0_LPRX_TOCNT4_Pos)      /*!< 0x00000010 */
+#define DSI_TCCR0_LPRX_TOCNT4         DSI_TCCR0_LPRX_TOCNT4_Msk                
+#define DSI_TCCR0_LPRX_TOCNT5_Pos     (5U)                                     
+#define DSI_TCCR0_LPRX_TOCNT5_Msk     (0x1UL << DSI_TCCR0_LPRX_TOCNT5_Pos)      /*!< 0x00000020 */
+#define DSI_TCCR0_LPRX_TOCNT5         DSI_TCCR0_LPRX_TOCNT5_Msk                
+#define DSI_TCCR0_LPRX_TOCNT6_Pos     (6U)                                     
+#define DSI_TCCR0_LPRX_TOCNT6_Msk     (0x1UL << DSI_TCCR0_LPRX_TOCNT6_Pos)      /*!< 0x00000040 */
+#define DSI_TCCR0_LPRX_TOCNT6         DSI_TCCR0_LPRX_TOCNT6_Msk                
+#define DSI_TCCR0_LPRX_TOCNT7_Pos     (7U)                                     
+#define DSI_TCCR0_LPRX_TOCNT7_Msk     (0x1UL << DSI_TCCR0_LPRX_TOCNT7_Pos)      /*!< 0x00000080 */
+#define DSI_TCCR0_LPRX_TOCNT7         DSI_TCCR0_LPRX_TOCNT7_Msk                
+#define DSI_TCCR0_LPRX_TOCNT8_Pos     (8U)                                     
+#define DSI_TCCR0_LPRX_TOCNT8_Msk     (0x1UL << DSI_TCCR0_LPRX_TOCNT8_Pos)      /*!< 0x00000100 */
+#define DSI_TCCR0_LPRX_TOCNT8         DSI_TCCR0_LPRX_TOCNT8_Msk                
+#define DSI_TCCR0_LPRX_TOCNT9_Pos     (9U)                                     
+#define DSI_TCCR0_LPRX_TOCNT9_Msk     (0x1UL << DSI_TCCR0_LPRX_TOCNT9_Pos)      /*!< 0x00000200 */
+#define DSI_TCCR0_LPRX_TOCNT9         DSI_TCCR0_LPRX_TOCNT9_Msk                
+#define DSI_TCCR0_LPRX_TOCNT10_Pos    (10U)                                    
+#define DSI_TCCR0_LPRX_TOCNT10_Msk    (0x1UL << DSI_TCCR0_LPRX_TOCNT10_Pos)     /*!< 0x00000400 */
+#define DSI_TCCR0_LPRX_TOCNT10        DSI_TCCR0_LPRX_TOCNT10_Msk               
+#define DSI_TCCR0_LPRX_TOCNT11_Pos    (11U)                                    
+#define DSI_TCCR0_LPRX_TOCNT11_Msk    (0x1UL << DSI_TCCR0_LPRX_TOCNT11_Pos)     /*!< 0x00000800 */
+#define DSI_TCCR0_LPRX_TOCNT11        DSI_TCCR0_LPRX_TOCNT11_Msk               
+#define DSI_TCCR0_LPRX_TOCNT12_Pos    (12U)                                    
+#define DSI_TCCR0_LPRX_TOCNT12_Msk    (0x1UL << DSI_TCCR0_LPRX_TOCNT12_Pos)     /*!< 0x00001000 */
+#define DSI_TCCR0_LPRX_TOCNT12        DSI_TCCR0_LPRX_TOCNT12_Msk               
+#define DSI_TCCR0_LPRX_TOCNT13_Pos    (13U)                                    
+#define DSI_TCCR0_LPRX_TOCNT13_Msk    (0x1UL << DSI_TCCR0_LPRX_TOCNT13_Pos)     /*!< 0x00002000 */
+#define DSI_TCCR0_LPRX_TOCNT13        DSI_TCCR0_LPRX_TOCNT13_Msk               
+#define DSI_TCCR0_LPRX_TOCNT14_Pos    (14U)                                    
+#define DSI_TCCR0_LPRX_TOCNT14_Msk    (0x1UL << DSI_TCCR0_LPRX_TOCNT14_Pos)     /*!< 0x00004000 */
+#define DSI_TCCR0_LPRX_TOCNT14        DSI_TCCR0_LPRX_TOCNT14_Msk               
+#define DSI_TCCR0_LPRX_TOCNT15_Pos    (15U)                                    
+#define DSI_TCCR0_LPRX_TOCNT15_Msk    (0x1UL << DSI_TCCR0_LPRX_TOCNT15_Pos)     /*!< 0x00008000 */
+#define DSI_TCCR0_LPRX_TOCNT15        DSI_TCCR0_LPRX_TOCNT15_Msk               
+
+#define DSI_TCCR0_HSTX_TOCNT_Pos      (16U)                                    
+#define DSI_TCCR0_HSTX_TOCNT_Msk      (0xFFFFUL << DSI_TCCR0_HSTX_TOCNT_Pos)    /*!< 0xFFFF0000 */
+#define DSI_TCCR0_HSTX_TOCNT          DSI_TCCR0_HSTX_TOCNT_Msk                 /*!< High-Speed Transmission Timeout Counter */
+#define DSI_TCCR0_HSTX_TOCNT0_Pos     (16U)                                    
+#define DSI_TCCR0_HSTX_TOCNT0_Msk     (0x1UL << DSI_TCCR0_HSTX_TOCNT0_Pos)      /*!< 0x00010000 */
+#define DSI_TCCR0_HSTX_TOCNT0         DSI_TCCR0_HSTX_TOCNT0_Msk                
+#define DSI_TCCR0_HSTX_TOCNT1_Pos     (17U)                                    
+#define DSI_TCCR0_HSTX_TOCNT1_Msk     (0x1UL << DSI_TCCR0_HSTX_TOCNT1_Pos)      /*!< 0x00020000 */
+#define DSI_TCCR0_HSTX_TOCNT1         DSI_TCCR0_HSTX_TOCNT1_Msk                
+#define DSI_TCCR0_HSTX_TOCNT2_Pos     (18U)                                    
+#define DSI_TCCR0_HSTX_TOCNT2_Msk     (0x1UL << DSI_TCCR0_HSTX_TOCNT2_Pos)      /*!< 0x00040000 */
+#define DSI_TCCR0_HSTX_TOCNT2         DSI_TCCR0_HSTX_TOCNT2_Msk                
+#define DSI_TCCR0_HSTX_TOCNT3_Pos     (19U)                                    
+#define DSI_TCCR0_HSTX_TOCNT3_Msk     (0x1UL << DSI_TCCR0_HSTX_TOCNT3_Pos)      /*!< 0x00080000 */
+#define DSI_TCCR0_HSTX_TOCNT3         DSI_TCCR0_HSTX_TOCNT3_Msk                
+#define DSI_TCCR0_HSTX_TOCNT4_Pos     (20U)                                    
+#define DSI_TCCR0_HSTX_TOCNT4_Msk     (0x1UL << DSI_TCCR0_HSTX_TOCNT4_Pos)      /*!< 0x00100000 */
+#define DSI_TCCR0_HSTX_TOCNT4         DSI_TCCR0_HSTX_TOCNT4_Msk                
+#define DSI_TCCR0_HSTX_TOCNT5_Pos     (21U)                                    
+#define DSI_TCCR0_HSTX_TOCNT5_Msk     (0x1UL << DSI_TCCR0_HSTX_TOCNT5_Pos)      /*!< 0x00200000 */
+#define DSI_TCCR0_HSTX_TOCNT5         DSI_TCCR0_HSTX_TOCNT5_Msk                
+#define DSI_TCCR0_HSTX_TOCNT6_Pos     (22U)                                    
+#define DSI_TCCR0_HSTX_TOCNT6_Msk     (0x1UL << DSI_TCCR0_HSTX_TOCNT6_Pos)      /*!< 0x00400000 */
+#define DSI_TCCR0_HSTX_TOCNT6         DSI_TCCR0_HSTX_TOCNT6_Msk                
+#define DSI_TCCR0_HSTX_TOCNT7_Pos     (23U)                                    
+#define DSI_TCCR0_HSTX_TOCNT7_Msk     (0x1UL << DSI_TCCR0_HSTX_TOCNT7_Pos)      /*!< 0x00800000 */
+#define DSI_TCCR0_HSTX_TOCNT7         DSI_TCCR0_HSTX_TOCNT7_Msk                
+#define DSI_TCCR0_HSTX_TOCNT8_Pos     (24U)                                    
+#define DSI_TCCR0_HSTX_TOCNT8_Msk     (0x1UL << DSI_TCCR0_HSTX_TOCNT8_Pos)      /*!< 0x01000000 */
+#define DSI_TCCR0_HSTX_TOCNT8         DSI_TCCR0_HSTX_TOCNT8_Msk                
+#define DSI_TCCR0_HSTX_TOCNT9_Pos     (25U)                                    
+#define DSI_TCCR0_HSTX_TOCNT9_Msk     (0x1UL << DSI_TCCR0_HSTX_TOCNT9_Pos)      /*!< 0x02000000 */
+#define DSI_TCCR0_HSTX_TOCNT9         DSI_TCCR0_HSTX_TOCNT9_Msk                
+#define DSI_TCCR0_HSTX_TOCNT10_Pos    (26U)                                    
+#define DSI_TCCR0_HSTX_TOCNT10_Msk    (0x1UL << DSI_TCCR0_HSTX_TOCNT10_Pos)     /*!< 0x04000000 */
+#define DSI_TCCR0_HSTX_TOCNT10        DSI_TCCR0_HSTX_TOCNT10_Msk               
+#define DSI_TCCR0_HSTX_TOCNT11_Pos    (27U)                                    
+#define DSI_TCCR0_HSTX_TOCNT11_Msk    (0x1UL << DSI_TCCR0_HSTX_TOCNT11_Pos)     /*!< 0x08000000 */
+#define DSI_TCCR0_HSTX_TOCNT11        DSI_TCCR0_HSTX_TOCNT11_Msk               
+#define DSI_TCCR0_HSTX_TOCNT12_Pos    (28U)                                    
+#define DSI_TCCR0_HSTX_TOCNT12_Msk    (0x1UL << DSI_TCCR0_HSTX_TOCNT12_Pos)     /*!< 0x10000000 */
+#define DSI_TCCR0_HSTX_TOCNT12        DSI_TCCR0_HSTX_TOCNT12_Msk               
+#define DSI_TCCR0_HSTX_TOCNT13_Pos    (29U)                                    
+#define DSI_TCCR0_HSTX_TOCNT13_Msk    (0x1UL << DSI_TCCR0_HSTX_TOCNT13_Pos)     /*!< 0x20000000 */
+#define DSI_TCCR0_HSTX_TOCNT13        DSI_TCCR0_HSTX_TOCNT13_Msk               
+#define DSI_TCCR0_HSTX_TOCNT14_Pos    (30U)                                    
+#define DSI_TCCR0_HSTX_TOCNT14_Msk    (0x1UL << DSI_TCCR0_HSTX_TOCNT14_Pos)     /*!< 0x40000000 */
+#define DSI_TCCR0_HSTX_TOCNT14        DSI_TCCR0_HSTX_TOCNT14_Msk               
+#define DSI_TCCR0_HSTX_TOCNT15_Pos    (31U)                                    
+#define DSI_TCCR0_HSTX_TOCNT15_Msk    (0x1UL << DSI_TCCR0_HSTX_TOCNT15_Pos)     /*!< 0x80000000 */
+#define DSI_TCCR0_HSTX_TOCNT15        DSI_TCCR0_HSTX_TOCNT15_Msk               
+
+/*******************  Bit definition for DSI_TCCR1 register  **************/
+#define DSI_TCCR1_HSRD_TOCNT_Pos      (0U)                                     
+#define DSI_TCCR1_HSRD_TOCNT_Msk      (0xFFFFUL << DSI_TCCR1_HSRD_TOCNT_Pos)    /*!< 0x0000FFFF */
+#define DSI_TCCR1_HSRD_TOCNT          DSI_TCCR1_HSRD_TOCNT_Msk                 /*!< High-Speed Read Timeout Counter */
+#define DSI_TCCR1_HSRD_TOCNT0_Pos     (0U)                                     
+#define DSI_TCCR1_HSRD_TOCNT0_Msk     (0x1UL << DSI_TCCR1_HSRD_TOCNT0_Pos)      /*!< 0x00000001 */
+#define DSI_TCCR1_HSRD_TOCNT0         DSI_TCCR1_HSRD_TOCNT0_Msk                
+#define DSI_TCCR1_HSRD_TOCNT1_Pos     (1U)                                     
+#define DSI_TCCR1_HSRD_TOCNT1_Msk     (0x1UL << DSI_TCCR1_HSRD_TOCNT1_Pos)      /*!< 0x00000002 */
+#define DSI_TCCR1_HSRD_TOCNT1         DSI_TCCR1_HSRD_TOCNT1_Msk                
+#define DSI_TCCR1_HSRD_TOCNT2_Pos     (2U)                                     
+#define DSI_TCCR1_HSRD_TOCNT2_Msk     (0x1UL << DSI_TCCR1_HSRD_TOCNT2_Pos)      /*!< 0x00000004 */
+#define DSI_TCCR1_HSRD_TOCNT2         DSI_TCCR1_HSRD_TOCNT2_Msk                
+#define DSI_TCCR1_HSRD_TOCNT3_Pos     (3U)                                     
+#define DSI_TCCR1_HSRD_TOCNT3_Msk     (0x1UL << DSI_TCCR1_HSRD_TOCNT3_Pos)      /*!< 0x00000008 */
+#define DSI_TCCR1_HSRD_TOCNT3         DSI_TCCR1_HSRD_TOCNT3_Msk                
+#define DSI_TCCR1_HSRD_TOCNT4_Pos     (4U)                                     
+#define DSI_TCCR1_HSRD_TOCNT4_Msk     (0x1UL << DSI_TCCR1_HSRD_TOCNT4_Pos)      /*!< 0x00000010 */
+#define DSI_TCCR1_HSRD_TOCNT4         DSI_TCCR1_HSRD_TOCNT4_Msk                
+#define DSI_TCCR1_HSRD_TOCNT5_Pos     (5U)                                     
+#define DSI_TCCR1_HSRD_TOCNT5_Msk     (0x1UL << DSI_TCCR1_HSRD_TOCNT5_Pos)      /*!< 0x00000020 */
+#define DSI_TCCR1_HSRD_TOCNT5         DSI_TCCR1_HSRD_TOCNT5_Msk                
+#define DSI_TCCR1_HSRD_TOCNT6_Pos     (6U)                                     
+#define DSI_TCCR1_HSRD_TOCNT6_Msk     (0x1UL << DSI_TCCR1_HSRD_TOCNT6_Pos)      /*!< 0x00000040 */
+#define DSI_TCCR1_HSRD_TOCNT6         DSI_TCCR1_HSRD_TOCNT6_Msk                
+#define DSI_TCCR1_HSRD_TOCNT7_Pos     (7U)                                     
+#define DSI_TCCR1_HSRD_TOCNT7_Msk     (0x1UL << DSI_TCCR1_HSRD_TOCNT7_Pos)      /*!< 0x00000080 */
+#define DSI_TCCR1_HSRD_TOCNT7         DSI_TCCR1_HSRD_TOCNT7_Msk                
+#define DSI_TCCR1_HSRD_TOCNT8_Pos     (8U)                                     
+#define DSI_TCCR1_HSRD_TOCNT8_Msk     (0x1UL << DSI_TCCR1_HSRD_TOCNT8_Pos)      /*!< 0x00000100 */
+#define DSI_TCCR1_HSRD_TOCNT8         DSI_TCCR1_HSRD_TOCNT8_Msk                
+#define DSI_TCCR1_HSRD_TOCNT9_Pos     (9U)                                     
+#define DSI_TCCR1_HSRD_TOCNT9_Msk     (0x1UL << DSI_TCCR1_HSRD_TOCNT9_Pos)      /*!< 0x00000200 */
+#define DSI_TCCR1_HSRD_TOCNT9         DSI_TCCR1_HSRD_TOCNT9_Msk                
+#define DSI_TCCR1_HSRD_TOCNT10_Pos    (10U)                                    
+#define DSI_TCCR1_HSRD_TOCNT10_Msk    (0x1UL << DSI_TCCR1_HSRD_TOCNT10_Pos)     /*!< 0x00000400 */
+#define DSI_TCCR1_HSRD_TOCNT10        DSI_TCCR1_HSRD_TOCNT10_Msk               
+#define DSI_TCCR1_HSRD_TOCNT11_Pos    (11U)                                    
+#define DSI_TCCR1_HSRD_TOCNT11_Msk    (0x1UL << DSI_TCCR1_HSRD_TOCNT11_Pos)     /*!< 0x00000800 */
+#define DSI_TCCR1_HSRD_TOCNT11        DSI_TCCR1_HSRD_TOCNT11_Msk               
+#define DSI_TCCR1_HSRD_TOCNT12_Pos    (12U)                                    
+#define DSI_TCCR1_HSRD_TOCNT12_Msk    (0x1UL << DSI_TCCR1_HSRD_TOCNT12_Pos)     /*!< 0x00001000 */
+#define DSI_TCCR1_HSRD_TOCNT12        DSI_TCCR1_HSRD_TOCNT12_Msk               
+#define DSI_TCCR1_HSRD_TOCNT13_Pos    (13U)                                    
+#define DSI_TCCR1_HSRD_TOCNT13_Msk    (0x1UL << DSI_TCCR1_HSRD_TOCNT13_Pos)     /*!< 0x00002000 */
+#define DSI_TCCR1_HSRD_TOCNT13        DSI_TCCR1_HSRD_TOCNT13_Msk               
+#define DSI_TCCR1_HSRD_TOCNT14_Pos    (14U)                                    
+#define DSI_TCCR1_HSRD_TOCNT14_Msk    (0x1UL << DSI_TCCR1_HSRD_TOCNT14_Pos)     /*!< 0x00004000 */
+#define DSI_TCCR1_HSRD_TOCNT14        DSI_TCCR1_HSRD_TOCNT14_Msk               
+#define DSI_TCCR1_HSRD_TOCNT15_Pos    (15U)                                    
+#define DSI_TCCR1_HSRD_TOCNT15_Msk    (0x1UL << DSI_TCCR1_HSRD_TOCNT15_Pos)     /*!< 0x00008000 */
+#define DSI_TCCR1_HSRD_TOCNT15        DSI_TCCR1_HSRD_TOCNT15_Msk               
+
+/*******************  Bit definition for DSI_TCCR2 register  **************/
+#define DSI_TCCR2_LPRD_TOCNT_Pos      (0U)                                     
+#define DSI_TCCR2_LPRD_TOCNT_Msk      (0xFFFFUL << DSI_TCCR2_LPRD_TOCNT_Pos)    /*!< 0x0000FFFF */
+#define DSI_TCCR2_LPRD_TOCNT          DSI_TCCR2_LPRD_TOCNT_Msk                 /*!< Low-Power Read Timeout Counter */
+#define DSI_TCCR2_LPRD_TOCNT0_Pos     (0U)                                     
+#define DSI_TCCR2_LPRD_TOCNT0_Msk     (0x1UL << DSI_TCCR2_LPRD_TOCNT0_Pos)      /*!< 0x00000001 */
+#define DSI_TCCR2_LPRD_TOCNT0         DSI_TCCR2_LPRD_TOCNT0_Msk                
+#define DSI_TCCR2_LPRD_TOCNT1_Pos     (1U)                                     
+#define DSI_TCCR2_LPRD_TOCNT1_Msk     (0x1UL << DSI_TCCR2_LPRD_TOCNT1_Pos)      /*!< 0x00000002 */
+#define DSI_TCCR2_LPRD_TOCNT1         DSI_TCCR2_LPRD_TOCNT1_Msk                
+#define DSI_TCCR2_LPRD_TOCNT2_Pos     (2U)                                     
+#define DSI_TCCR2_LPRD_TOCNT2_Msk     (0x1UL << DSI_TCCR2_LPRD_TOCNT2_Pos)      /*!< 0x00000004 */
+#define DSI_TCCR2_LPRD_TOCNT2         DSI_TCCR2_LPRD_TOCNT2_Msk                
+#define DSI_TCCR2_LPRD_TOCNT3_Pos     (3U)                                     
+#define DSI_TCCR2_LPRD_TOCNT3_Msk     (0x1UL << DSI_TCCR2_LPRD_TOCNT3_Pos)      /*!< 0x00000008 */
+#define DSI_TCCR2_LPRD_TOCNT3         DSI_TCCR2_LPRD_TOCNT3_Msk                
+#define DSI_TCCR2_LPRD_TOCNT4_Pos     (4U)                                     
+#define DSI_TCCR2_LPRD_TOCNT4_Msk     (0x1UL << DSI_TCCR2_LPRD_TOCNT4_Pos)      /*!< 0x00000010 */
+#define DSI_TCCR2_LPRD_TOCNT4         DSI_TCCR2_LPRD_TOCNT4_Msk                
+#define DSI_TCCR2_LPRD_TOCNT5_Pos     (5U)                                     
+#define DSI_TCCR2_LPRD_TOCNT5_Msk     (0x1UL << DSI_TCCR2_LPRD_TOCNT5_Pos)      /*!< 0x00000020 */
+#define DSI_TCCR2_LPRD_TOCNT5         DSI_TCCR2_LPRD_TOCNT5_Msk                
+#define DSI_TCCR2_LPRD_TOCNT6_Pos     (6U)                                     
+#define DSI_TCCR2_LPRD_TOCNT6_Msk     (0x1UL << DSI_TCCR2_LPRD_TOCNT6_Pos)      /*!< 0x00000040 */
+#define DSI_TCCR2_LPRD_TOCNT6         DSI_TCCR2_LPRD_TOCNT6_Msk                
+#define DSI_TCCR2_LPRD_TOCNT7_Pos     (7U)                                     
+#define DSI_TCCR2_LPRD_TOCNT7_Msk     (0x1UL << DSI_TCCR2_LPRD_TOCNT7_Pos)      /*!< 0x00000080 */
+#define DSI_TCCR2_LPRD_TOCNT7         DSI_TCCR2_LPRD_TOCNT7_Msk                
+#define DSI_TCCR2_LPRD_TOCNT8_Pos     (8U)                                     
+#define DSI_TCCR2_LPRD_TOCNT8_Msk     (0x1UL << DSI_TCCR2_LPRD_TOCNT8_Pos)      /*!< 0x00000100 */
+#define DSI_TCCR2_LPRD_TOCNT8         DSI_TCCR2_LPRD_TOCNT8_Msk                
+#define DSI_TCCR2_LPRD_TOCNT9_Pos     (9U)                                     
+#define DSI_TCCR2_LPRD_TOCNT9_Msk     (0x1UL << DSI_TCCR2_LPRD_TOCNT9_Pos)      /*!< 0x00000200 */
+#define DSI_TCCR2_LPRD_TOCNT9         DSI_TCCR2_LPRD_TOCNT9_Msk                
+#define DSI_TCCR2_LPRD_TOCNT10_Pos    (10U)                                    
+#define DSI_TCCR2_LPRD_TOCNT10_Msk    (0x1UL << DSI_TCCR2_LPRD_TOCNT10_Pos)     /*!< 0x00000400 */
+#define DSI_TCCR2_LPRD_TOCNT10        DSI_TCCR2_LPRD_TOCNT10_Msk               
+#define DSI_TCCR2_LPRD_TOCNT11_Pos    (11U)                                    
+#define DSI_TCCR2_LPRD_TOCNT11_Msk    (0x1UL << DSI_TCCR2_LPRD_TOCNT11_Pos)     /*!< 0x00000800 */
+#define DSI_TCCR2_LPRD_TOCNT11        DSI_TCCR2_LPRD_TOCNT11_Msk               
+#define DSI_TCCR2_LPRD_TOCNT12_Pos    (12U)                                    
+#define DSI_TCCR2_LPRD_TOCNT12_Msk    (0x1UL << DSI_TCCR2_LPRD_TOCNT12_Pos)     /*!< 0x00001000 */
+#define DSI_TCCR2_LPRD_TOCNT12        DSI_TCCR2_LPRD_TOCNT12_Msk               
+#define DSI_TCCR2_LPRD_TOCNT13_Pos    (13U)                                    
+#define DSI_TCCR2_LPRD_TOCNT13_Msk    (0x1UL << DSI_TCCR2_LPRD_TOCNT13_Pos)     /*!< 0x00002000 */
+#define DSI_TCCR2_LPRD_TOCNT13        DSI_TCCR2_LPRD_TOCNT13_Msk               
+#define DSI_TCCR2_LPRD_TOCNT14_Pos    (14U)                                    
+#define DSI_TCCR2_LPRD_TOCNT14_Msk    (0x1UL << DSI_TCCR2_LPRD_TOCNT14_Pos)     /*!< 0x00004000 */
+#define DSI_TCCR2_LPRD_TOCNT14        DSI_TCCR2_LPRD_TOCNT14_Msk               
+#define DSI_TCCR2_LPRD_TOCNT15_Pos    (15U)                                    
+#define DSI_TCCR2_LPRD_TOCNT15_Msk    (0x1UL << DSI_TCCR2_LPRD_TOCNT15_Pos)     /*!< 0x00008000 */
+#define DSI_TCCR2_LPRD_TOCNT15        DSI_TCCR2_LPRD_TOCNT15_Msk               
+
+/*******************  Bit definition for DSI_TCCR3 register  **************/
+#define DSI_TCCR3_HSWR_TOCNT_Pos      (0U)                                     
+#define DSI_TCCR3_HSWR_TOCNT_Msk      (0xFFFFUL << DSI_TCCR3_HSWR_TOCNT_Pos)    /*!< 0x0000FFFF */
+#define DSI_TCCR3_HSWR_TOCNT          DSI_TCCR3_HSWR_TOCNT_Msk                 /*!< High-Speed Write Timeout Counter */
+#define DSI_TCCR3_HSWR_TOCNT0_Pos     (0U)                                     
+#define DSI_TCCR3_HSWR_TOCNT0_Msk     (0x1UL << DSI_TCCR3_HSWR_TOCNT0_Pos)      /*!< 0x00000001 */
+#define DSI_TCCR3_HSWR_TOCNT0         DSI_TCCR3_HSWR_TOCNT0_Msk                
+#define DSI_TCCR3_HSWR_TOCNT1_Pos     (1U)                                     
+#define DSI_TCCR3_HSWR_TOCNT1_Msk     (0x1UL << DSI_TCCR3_HSWR_TOCNT1_Pos)      /*!< 0x00000002 */
+#define DSI_TCCR3_HSWR_TOCNT1         DSI_TCCR3_HSWR_TOCNT1_Msk                
+#define DSI_TCCR3_HSWR_TOCNT2_Pos     (2U)                                     
+#define DSI_TCCR3_HSWR_TOCNT2_Msk     (0x1UL << DSI_TCCR3_HSWR_TOCNT2_Pos)      /*!< 0x00000004 */
+#define DSI_TCCR3_HSWR_TOCNT2         DSI_TCCR3_HSWR_TOCNT2_Msk                
+#define DSI_TCCR3_HSWR_TOCNT3_Pos     (3U)                                     
+#define DSI_TCCR3_HSWR_TOCNT3_Msk     (0x1UL << DSI_TCCR3_HSWR_TOCNT3_Pos)      /*!< 0x00000008 */
+#define DSI_TCCR3_HSWR_TOCNT3         DSI_TCCR3_HSWR_TOCNT3_Msk                
+#define DSI_TCCR3_HSWR_TOCNT4_Pos     (4U)                                     
+#define DSI_TCCR3_HSWR_TOCNT4_Msk     (0x1UL << DSI_TCCR3_HSWR_TOCNT4_Pos)      /*!< 0x00000010 */
+#define DSI_TCCR3_HSWR_TOCNT4         DSI_TCCR3_HSWR_TOCNT4_Msk                
+#define DSI_TCCR3_HSWR_TOCNT5_Pos     (5U)                                     
+#define DSI_TCCR3_HSWR_TOCNT5_Msk     (0x1UL << DSI_TCCR3_HSWR_TOCNT5_Pos)      /*!< 0x00000020 */
+#define DSI_TCCR3_HSWR_TOCNT5         DSI_TCCR3_HSWR_TOCNT5_Msk                
+#define DSI_TCCR3_HSWR_TOCNT6_Pos     (6U)                                     
+#define DSI_TCCR3_HSWR_TOCNT6_Msk     (0x1UL << DSI_TCCR3_HSWR_TOCNT6_Pos)      /*!< 0x00000040 */
+#define DSI_TCCR3_HSWR_TOCNT6         DSI_TCCR3_HSWR_TOCNT6_Msk                
+#define DSI_TCCR3_HSWR_TOCNT7_Pos     (7U)                                     
+#define DSI_TCCR3_HSWR_TOCNT7_Msk     (0x1UL << DSI_TCCR3_HSWR_TOCNT7_Pos)      /*!< 0x00000080 */
+#define DSI_TCCR3_HSWR_TOCNT7         DSI_TCCR3_HSWR_TOCNT7_Msk                
+#define DSI_TCCR3_HSWR_TOCNT8_Pos     (8U)                                     
+#define DSI_TCCR3_HSWR_TOCNT8_Msk     (0x1UL << DSI_TCCR3_HSWR_TOCNT8_Pos)      /*!< 0x00000100 */
+#define DSI_TCCR3_HSWR_TOCNT8         DSI_TCCR3_HSWR_TOCNT8_Msk                
+#define DSI_TCCR3_HSWR_TOCNT9_Pos     (9U)                                     
+#define DSI_TCCR3_HSWR_TOCNT9_Msk     (0x1UL << DSI_TCCR3_HSWR_TOCNT9_Pos)      /*!< 0x00000200 */
+#define DSI_TCCR3_HSWR_TOCNT9         DSI_TCCR3_HSWR_TOCNT9_Msk                
+#define DSI_TCCR3_HSWR_TOCNT10_Pos    (10U)                                    
+#define DSI_TCCR3_HSWR_TOCNT10_Msk    (0x1UL << DSI_TCCR3_HSWR_TOCNT10_Pos)     /*!< 0x00000400 */
+#define DSI_TCCR3_HSWR_TOCNT10        DSI_TCCR3_HSWR_TOCNT10_Msk               
+#define DSI_TCCR3_HSWR_TOCNT11_Pos    (11U)                                    
+#define DSI_TCCR3_HSWR_TOCNT11_Msk    (0x1UL << DSI_TCCR3_HSWR_TOCNT11_Pos)     /*!< 0x00000800 */
+#define DSI_TCCR3_HSWR_TOCNT11        DSI_TCCR3_HSWR_TOCNT11_Msk               
+#define DSI_TCCR3_HSWR_TOCNT12_Pos    (12U)                                    
+#define DSI_TCCR3_HSWR_TOCNT12_Msk    (0x1UL << DSI_TCCR3_HSWR_TOCNT12_Pos)     /*!< 0x00001000 */
+#define DSI_TCCR3_HSWR_TOCNT12        DSI_TCCR3_HSWR_TOCNT12_Msk               
+#define DSI_TCCR3_HSWR_TOCNT13_Pos    (13U)                                    
+#define DSI_TCCR3_HSWR_TOCNT13_Msk    (0x1UL << DSI_TCCR3_HSWR_TOCNT13_Pos)     /*!< 0x00002000 */
+#define DSI_TCCR3_HSWR_TOCNT13        DSI_TCCR3_HSWR_TOCNT13_Msk               
+#define DSI_TCCR3_HSWR_TOCNT14_Pos    (14U)                                    
+#define DSI_TCCR3_HSWR_TOCNT14_Msk    (0x1UL << DSI_TCCR3_HSWR_TOCNT14_Pos)     /*!< 0x00004000 */
+#define DSI_TCCR3_HSWR_TOCNT14        DSI_TCCR3_HSWR_TOCNT14_Msk               
+#define DSI_TCCR3_HSWR_TOCNT15_Pos    (15U)                                    
+#define DSI_TCCR3_HSWR_TOCNT15_Msk    (0x1UL << DSI_TCCR3_HSWR_TOCNT15_Pos)     /*!< 0x00008000 */
+#define DSI_TCCR3_HSWR_TOCNT15        DSI_TCCR3_HSWR_TOCNT15_Msk               
+
+#define DSI_TCCR3_PM_Pos              (24U)                                    
+#define DSI_TCCR3_PM_Msk              (0x1UL << DSI_TCCR3_PM_Pos)               /*!< 0x01000000 */
+#define DSI_TCCR3_PM                  DSI_TCCR3_PM_Msk                         /*!< Presp Mode */
+
+/*******************  Bit definition for DSI_TCCR4 register  **************/
+#define DSI_TCCR4_LPWR_TOCNT_Pos      (0U)                                     
+#define DSI_TCCR4_LPWR_TOCNT_Msk      (0xFFFFUL << DSI_TCCR4_LPWR_TOCNT_Pos)    /*!< 0x0000FFFF */
+#define DSI_TCCR4_LPWR_TOCNT          DSI_TCCR4_LPWR_TOCNT_Msk                 /*!< Low-Power Write Timeout Counter */
+#define DSI_TCCR4_LPWR_TOCNT0_Pos     (0U)                                     
+#define DSI_TCCR4_LPWR_TOCNT0_Msk     (0x1UL << DSI_TCCR4_LPWR_TOCNT0_Pos)      /*!< 0x00000001 */
+#define DSI_TCCR4_LPWR_TOCNT0         DSI_TCCR4_LPWR_TOCNT0_Msk                
+#define DSI_TCCR4_LPWR_TOCNT1_Pos     (1U)                                     
+#define DSI_TCCR4_LPWR_TOCNT1_Msk     (0x1UL << DSI_TCCR4_LPWR_TOCNT1_Pos)      /*!< 0x00000002 */
+#define DSI_TCCR4_LPWR_TOCNT1         DSI_TCCR4_LPWR_TOCNT1_Msk                
+#define DSI_TCCR4_LPWR_TOCNT2_Pos     (2U)                                     
+#define DSI_TCCR4_LPWR_TOCNT2_Msk     (0x1UL << DSI_TCCR4_LPWR_TOCNT2_Pos)      /*!< 0x00000004 */
+#define DSI_TCCR4_LPWR_TOCNT2         DSI_TCCR4_LPWR_TOCNT2_Msk                
+#define DSI_TCCR4_LPWR_TOCNT3_Pos     (3U)                                     
+#define DSI_TCCR4_LPWR_TOCNT3_Msk     (0x1UL << DSI_TCCR4_LPWR_TOCNT3_Pos)      /*!< 0x00000008 */
+#define DSI_TCCR4_LPWR_TOCNT3         DSI_TCCR4_LPWR_TOCNT3_Msk                
+#define DSI_TCCR4_LPWR_TOCNT4_Pos     (4U)                                     
+#define DSI_TCCR4_LPWR_TOCNT4_Msk     (0x1UL << DSI_TCCR4_LPWR_TOCNT4_Pos)      /*!< 0x00000010 */
+#define DSI_TCCR4_LPWR_TOCNT4         DSI_TCCR4_LPWR_TOCNT4_Msk                
+#define DSI_TCCR4_LPWR_TOCNT5_Pos     (5U)                                     
+#define DSI_TCCR4_LPWR_TOCNT5_Msk     (0x1UL << DSI_TCCR4_LPWR_TOCNT5_Pos)      /*!< 0x00000020 */
+#define DSI_TCCR4_LPWR_TOCNT5         DSI_TCCR4_LPWR_TOCNT5_Msk                
+#define DSI_TCCR4_LPWR_TOCNT6_Pos     (6U)                                     
+#define DSI_TCCR4_LPWR_TOCNT6_Msk     (0x1UL << DSI_TCCR4_LPWR_TOCNT6_Pos)      /*!< 0x00000040 */
+#define DSI_TCCR4_LPWR_TOCNT6         DSI_TCCR4_LPWR_TOCNT6_Msk                
+#define DSI_TCCR4_LPWR_TOCNT7_Pos     (7U)                                     
+#define DSI_TCCR4_LPWR_TOCNT7_Msk     (0x1UL << DSI_TCCR4_LPWR_TOCNT7_Pos)      /*!< 0x00000080 */
+#define DSI_TCCR4_LPWR_TOCNT7         DSI_TCCR4_LPWR_TOCNT7_Msk                
+#define DSI_TCCR4_LPWR_TOCNT8_Pos     (8U)                                     
+#define DSI_TCCR4_LPWR_TOCNT8_Msk     (0x1UL << DSI_TCCR4_LPWR_TOCNT8_Pos)      /*!< 0x00000100 */
+#define DSI_TCCR4_LPWR_TOCNT8         DSI_TCCR4_LPWR_TOCNT8_Msk                
+#define DSI_TCCR4_LPWR_TOCNT9_Pos     (9U)                                     
+#define DSI_TCCR4_LPWR_TOCNT9_Msk     (0x1UL << DSI_TCCR4_LPWR_TOCNT9_Pos)      /*!< 0x00000200 */
+#define DSI_TCCR4_LPWR_TOCNT9         DSI_TCCR4_LPWR_TOCNT9_Msk                
+#define DSI_TCCR4_LPWR_TOCNT10_Pos    (10U)                                    
+#define DSI_TCCR4_LPWR_TOCNT10_Msk    (0x1UL << DSI_TCCR4_LPWR_TOCNT10_Pos)     /*!< 0x00000400 */
+#define DSI_TCCR4_LPWR_TOCNT10        DSI_TCCR4_LPWR_TOCNT10_Msk               
+#define DSI_TCCR4_LPWR_TOCNT11_Pos    (11U)                                    
+#define DSI_TCCR4_LPWR_TOCNT11_Msk    (0x1UL << DSI_TCCR4_LPWR_TOCNT11_Pos)     /*!< 0x00000800 */
+#define DSI_TCCR4_LPWR_TOCNT11        DSI_TCCR4_LPWR_TOCNT11_Msk               
+#define DSI_TCCR4_LPWR_TOCNT12_Pos    (12U)                                    
+#define DSI_TCCR4_LPWR_TOCNT12_Msk    (0x1UL << DSI_TCCR4_LPWR_TOCNT12_Pos)     /*!< 0x00001000 */
+#define DSI_TCCR4_LPWR_TOCNT12        DSI_TCCR4_LPWR_TOCNT12_Msk               
+#define DSI_TCCR4_LPWR_TOCNT13_Pos    (13U)                                    
+#define DSI_TCCR4_LPWR_TOCNT13_Msk    (0x1UL << DSI_TCCR4_LPWR_TOCNT13_Pos)     /*!< 0x00002000 */
+#define DSI_TCCR4_LPWR_TOCNT13        DSI_TCCR4_LPWR_TOCNT13_Msk               
+#define DSI_TCCR4_LPWR_TOCNT14_Pos    (14U)                                    
+#define DSI_TCCR4_LPWR_TOCNT14_Msk    (0x1UL << DSI_TCCR4_LPWR_TOCNT14_Pos)     /*!< 0x00004000 */
+#define DSI_TCCR4_LPWR_TOCNT14        DSI_TCCR4_LPWR_TOCNT14_Msk               
+#define DSI_TCCR4_LPWR_TOCNT15_Pos    (15U)                                    
+#define DSI_TCCR4_LPWR_TOCNT15_Msk    (0x1UL << DSI_TCCR4_LPWR_TOCNT15_Pos)     /*!< 0x00008000 */
+#define DSI_TCCR4_LPWR_TOCNT15        DSI_TCCR4_LPWR_TOCNT15_Msk               
+
+/*******************  Bit definition for DSI_TCCR5 register  **************/
+#define DSI_TCCR5_BTA_TOCNT_Pos       (0U)                                     
+#define DSI_TCCR5_BTA_TOCNT_Msk       (0xFFFFUL << DSI_TCCR5_BTA_TOCNT_Pos)     /*!< 0x0000FFFF */
+#define DSI_TCCR5_BTA_TOCNT           DSI_TCCR5_BTA_TOCNT_Msk                  /*!< Bus-Turn-Around Timeout Counter */
+#define DSI_TCCR5_BTA_TOCNT0_Pos      (0U)                                     
+#define DSI_TCCR5_BTA_TOCNT0_Msk      (0x1UL << DSI_TCCR5_BTA_TOCNT0_Pos)       /*!< 0x00000001 */
+#define DSI_TCCR5_BTA_TOCNT0          DSI_TCCR5_BTA_TOCNT0_Msk                 
+#define DSI_TCCR5_BTA_TOCNT1_Pos      (1U)                                     
+#define DSI_TCCR5_BTA_TOCNT1_Msk      (0x1UL << DSI_TCCR5_BTA_TOCNT1_Pos)       /*!< 0x00000002 */
+#define DSI_TCCR5_BTA_TOCNT1          DSI_TCCR5_BTA_TOCNT1_Msk                 
+#define DSI_TCCR5_BTA_TOCNT2_Pos      (2U)                                     
+#define DSI_TCCR5_BTA_TOCNT2_Msk      (0x1UL << DSI_TCCR5_BTA_TOCNT2_Pos)       /*!< 0x00000004 */
+#define DSI_TCCR5_BTA_TOCNT2          DSI_TCCR5_BTA_TOCNT2_Msk                 
+#define DSI_TCCR5_BTA_TOCNT3_Pos      (3U)                                     
+#define DSI_TCCR5_BTA_TOCNT3_Msk      (0x1UL << DSI_TCCR5_BTA_TOCNT3_Pos)       /*!< 0x00000008 */
+#define DSI_TCCR5_BTA_TOCNT3          DSI_TCCR5_BTA_TOCNT3_Msk                 
+#define DSI_TCCR5_BTA_TOCNT4_Pos      (4U)                                     
+#define DSI_TCCR5_BTA_TOCNT4_Msk      (0x1UL << DSI_TCCR5_BTA_TOCNT4_Pos)       /*!< 0x00000010 */
+#define DSI_TCCR5_BTA_TOCNT4          DSI_TCCR5_BTA_TOCNT4_Msk                 
+#define DSI_TCCR5_BTA_TOCNT5_Pos      (5U)                                     
+#define DSI_TCCR5_BTA_TOCNT5_Msk      (0x1UL << DSI_TCCR5_BTA_TOCNT5_Pos)       /*!< 0x00000020 */
+#define DSI_TCCR5_BTA_TOCNT5          DSI_TCCR5_BTA_TOCNT5_Msk                 
+#define DSI_TCCR5_BTA_TOCNT6_Pos      (6U)                                     
+#define DSI_TCCR5_BTA_TOCNT6_Msk      (0x1UL << DSI_TCCR5_BTA_TOCNT6_Pos)       /*!< 0x00000040 */
+#define DSI_TCCR5_BTA_TOCNT6          DSI_TCCR5_BTA_TOCNT6_Msk                 
+#define DSI_TCCR5_BTA_TOCNT7_Pos      (7U)                                     
+#define DSI_TCCR5_BTA_TOCNT7_Msk      (0x1UL << DSI_TCCR5_BTA_TOCNT7_Pos)       /*!< 0x00000080 */
+#define DSI_TCCR5_BTA_TOCNT7          DSI_TCCR5_BTA_TOCNT7_Msk                 
+#define DSI_TCCR5_BTA_TOCNT8_Pos      (8U)                                     
+#define DSI_TCCR5_BTA_TOCNT8_Msk      (0x1UL << DSI_TCCR5_BTA_TOCNT8_Pos)       /*!< 0x00000100 */
+#define DSI_TCCR5_BTA_TOCNT8          DSI_TCCR5_BTA_TOCNT8_Msk                 
+#define DSI_TCCR5_BTA_TOCNT9_Pos      (9U)                                     
+#define DSI_TCCR5_BTA_TOCNT9_Msk      (0x1UL << DSI_TCCR5_BTA_TOCNT9_Pos)       /*!< 0x00000200 */
+#define DSI_TCCR5_BTA_TOCNT9          DSI_TCCR5_BTA_TOCNT9_Msk                 
+#define DSI_TCCR5_BTA_TOCNT10_Pos     (10U)                                    
+#define DSI_TCCR5_BTA_TOCNT10_Msk     (0x1UL << DSI_TCCR5_BTA_TOCNT10_Pos)      /*!< 0x00000400 */
+#define DSI_TCCR5_BTA_TOCNT10         DSI_TCCR5_BTA_TOCNT10_Msk                
+#define DSI_TCCR5_BTA_TOCNT11_Pos     (11U)                                    
+#define DSI_TCCR5_BTA_TOCNT11_Msk     (0x1UL << DSI_TCCR5_BTA_TOCNT11_Pos)      /*!< 0x00000800 */
+#define DSI_TCCR5_BTA_TOCNT11         DSI_TCCR5_BTA_TOCNT11_Msk                
+#define DSI_TCCR5_BTA_TOCNT12_Pos     (12U)                                    
+#define DSI_TCCR5_BTA_TOCNT12_Msk     (0x1UL << DSI_TCCR5_BTA_TOCNT12_Pos)      /*!< 0x00001000 */
+#define DSI_TCCR5_BTA_TOCNT12         DSI_TCCR5_BTA_TOCNT12_Msk                
+#define DSI_TCCR5_BTA_TOCNT13_Pos     (13U)                                    
+#define DSI_TCCR5_BTA_TOCNT13_Msk     (0x1UL << DSI_TCCR5_BTA_TOCNT13_Pos)      /*!< 0x00002000 */
+#define DSI_TCCR5_BTA_TOCNT13         DSI_TCCR5_BTA_TOCNT13_Msk                
+#define DSI_TCCR5_BTA_TOCNT14_Pos     (14U)                                    
+#define DSI_TCCR5_BTA_TOCNT14_Msk     (0x1UL << DSI_TCCR5_BTA_TOCNT14_Pos)      /*!< 0x00004000 */
+#define DSI_TCCR5_BTA_TOCNT14         DSI_TCCR5_BTA_TOCNT14_Msk                
+#define DSI_TCCR5_BTA_TOCNT15_Pos     (15U)                                    
+#define DSI_TCCR5_BTA_TOCNT15_Msk     (0x1UL << DSI_TCCR5_BTA_TOCNT15_Pos)      /*!< 0x00008000 */
+#define DSI_TCCR5_BTA_TOCNT15         DSI_TCCR5_BTA_TOCNT15_Msk                
+
+/*******************  Bit definition for DSI_TDCR register  ***************/
+#define DSI_TDCR_3DM                  0x00000003U                              /*!< 3D Mode */
+#define DSI_TDCR_3DM0                 0x00000001U                              
+#define DSI_TDCR_3DM1                 0x00000002U                              
+
+#define DSI_TDCR_3DF                  0x0000000CU                              /*!< 3D Format */
+#define DSI_TDCR_3DF0                 0x00000004U                              
+#define DSI_TDCR_3DF1                 0x00000008U                              
+
+#define DSI_TDCR_SVS_Pos              (4U)                                     
+#define DSI_TDCR_SVS_Msk              (0x1UL << DSI_TDCR_SVS_Pos)               /*!< 0x00000010 */
+#define DSI_TDCR_SVS                  DSI_TDCR_SVS_Msk                         /*!< Second VSYNC */
+#define DSI_TDCR_RF_Pos               (5U)                                     
+#define DSI_TDCR_RF_Msk               (0x1UL << DSI_TDCR_RF_Pos)                /*!< 0x00000020 */
+#define DSI_TDCR_RF                   DSI_TDCR_RF_Msk                          /*!< Right First */
+#define DSI_TDCR_S3DC_Pos             (16U)                                    
+#define DSI_TDCR_S3DC_Msk             (0x1UL << DSI_TDCR_S3DC_Pos)              /*!< 0x00010000 */
+#define DSI_TDCR_S3DC                 DSI_TDCR_S3DC_Msk                        /*!< Send 3D Control */
+
+/*******************  Bit definition for DSI_CLCR register  ***************/
+#define DSI_CLCR_DPCC_Pos             (0U)                                     
+#define DSI_CLCR_DPCC_Msk             (0x1UL << DSI_CLCR_DPCC_Pos)              /*!< 0x00000001 */
+#define DSI_CLCR_DPCC                 DSI_CLCR_DPCC_Msk                        /*!< D-PHY Clock Control */
+#define DSI_CLCR_ACR_Pos              (1U)                                     
+#define DSI_CLCR_ACR_Msk              (0x1UL << DSI_CLCR_ACR_Pos)               /*!< 0x00000002 */
+#define DSI_CLCR_ACR                  DSI_CLCR_ACR_Msk                         /*!< Automatic Clocklane Control */
+
+/*******************  Bit definition for DSI_CLTCR register  **************/
+#define DSI_CLTCR_LP2HS_TIME_Pos      (0U)                                     
+#define DSI_CLTCR_LP2HS_TIME_Msk      (0x3FFUL << DSI_CLTCR_LP2HS_TIME_Pos)     /*!< 0x000003FF */
+#define DSI_CLTCR_LP2HS_TIME          DSI_CLTCR_LP2HS_TIME_Msk                 /*!< Low-Power to High-Speed Time */
+#define DSI_CLTCR_LP2HS_TIME0_Pos     (0U)                                     
+#define DSI_CLTCR_LP2HS_TIME0_Msk     (0x1UL << DSI_CLTCR_LP2HS_TIME0_Pos)      /*!< 0x00000001 */
+#define DSI_CLTCR_LP2HS_TIME0         DSI_CLTCR_LP2HS_TIME0_Msk                
+#define DSI_CLTCR_LP2HS_TIME1_Pos     (1U)                                     
+#define DSI_CLTCR_LP2HS_TIME1_Msk     (0x1UL << DSI_CLTCR_LP2HS_TIME1_Pos)      /*!< 0x00000002 */
+#define DSI_CLTCR_LP2HS_TIME1         DSI_CLTCR_LP2HS_TIME1_Msk                
+#define DSI_CLTCR_LP2HS_TIME2_Pos     (2U)                                     
+#define DSI_CLTCR_LP2HS_TIME2_Msk     (0x1UL << DSI_CLTCR_LP2HS_TIME2_Pos)      /*!< 0x00000004 */
+#define DSI_CLTCR_LP2HS_TIME2         DSI_CLTCR_LP2HS_TIME2_Msk                
+#define DSI_CLTCR_LP2HS_TIME3_Pos     (3U)                                     
+#define DSI_CLTCR_LP2HS_TIME3_Msk     (0x1UL << DSI_CLTCR_LP2HS_TIME3_Pos)      /*!< 0x00000008 */
+#define DSI_CLTCR_LP2HS_TIME3         DSI_CLTCR_LP2HS_TIME3_Msk                
+#define DSI_CLTCR_LP2HS_TIME4_Pos     (4U)                                     
+#define DSI_CLTCR_LP2HS_TIME4_Msk     (0x1UL << DSI_CLTCR_LP2HS_TIME4_Pos)      /*!< 0x00000010 */
+#define DSI_CLTCR_LP2HS_TIME4         DSI_CLTCR_LP2HS_TIME4_Msk                
+#define DSI_CLTCR_LP2HS_TIME5_Pos     (5U)                                     
+#define DSI_CLTCR_LP2HS_TIME5_Msk     (0x1UL << DSI_CLTCR_LP2HS_TIME5_Pos)      /*!< 0x00000020 */
+#define DSI_CLTCR_LP2HS_TIME5         DSI_CLTCR_LP2HS_TIME5_Msk                
+#define DSI_CLTCR_LP2HS_TIME6_Pos     (6U)                                     
+#define DSI_CLTCR_LP2HS_TIME6_Msk     (0x1UL << DSI_CLTCR_LP2HS_TIME6_Pos)      /*!< 0x00000040 */
+#define DSI_CLTCR_LP2HS_TIME6         DSI_CLTCR_LP2HS_TIME6_Msk                
+#define DSI_CLTCR_LP2HS_TIME7_Pos     (7U)                                     
+#define DSI_CLTCR_LP2HS_TIME7_Msk     (0x1UL << DSI_CLTCR_LP2HS_TIME7_Pos)      /*!< 0x00000080 */
+#define DSI_CLTCR_LP2HS_TIME7         DSI_CLTCR_LP2HS_TIME7_Msk                
+#define DSI_CLTCR_LP2HS_TIME8_Pos     (8U)                                     
+#define DSI_CLTCR_LP2HS_TIME8_Msk     (0x1UL << DSI_CLTCR_LP2HS_TIME8_Pos)      /*!< 0x00000100 */
+#define DSI_CLTCR_LP2HS_TIME8         DSI_CLTCR_LP2HS_TIME8_Msk                
+#define DSI_CLTCR_LP2HS_TIME9_Pos     (9U)                                     
+#define DSI_CLTCR_LP2HS_TIME9_Msk     (0x1UL << DSI_CLTCR_LP2HS_TIME9_Pos)      /*!< 0x00000200 */
+#define DSI_CLTCR_LP2HS_TIME9         DSI_CLTCR_LP2HS_TIME9_Msk                
+
+#define DSI_CLTCR_HS2LP_TIME_Pos      (16U)                                    
+#define DSI_CLTCR_HS2LP_TIME_Msk      (0x3FFUL << DSI_CLTCR_HS2LP_TIME_Pos)     /*!< 0x03FF0000 */
+#define DSI_CLTCR_HS2LP_TIME          DSI_CLTCR_HS2LP_TIME_Msk                 /*!< High-Speed to Low-Power Time */
+#define DSI_CLTCR_HS2LP_TIME0_Pos     (16U)                                    
+#define DSI_CLTCR_HS2LP_TIME0_Msk     (0x1UL << DSI_CLTCR_HS2LP_TIME0_Pos)      /*!< 0x00010000 */
+#define DSI_CLTCR_HS2LP_TIME0         DSI_CLTCR_HS2LP_TIME0_Msk                
+#define DSI_CLTCR_HS2LP_TIME1_Pos     (17U)                                    
+#define DSI_CLTCR_HS2LP_TIME1_Msk     (0x1UL << DSI_CLTCR_HS2LP_TIME1_Pos)      /*!< 0x00020000 */
+#define DSI_CLTCR_HS2LP_TIME1         DSI_CLTCR_HS2LP_TIME1_Msk                
+#define DSI_CLTCR_HS2LP_TIME2_Pos     (18U)                                    
+#define DSI_CLTCR_HS2LP_TIME2_Msk     (0x1UL << DSI_CLTCR_HS2LP_TIME2_Pos)      /*!< 0x00040000 */
+#define DSI_CLTCR_HS2LP_TIME2         DSI_CLTCR_HS2LP_TIME2_Msk                
+#define DSI_CLTCR_HS2LP_TIME3_Pos     (19U)                                    
+#define DSI_CLTCR_HS2LP_TIME3_Msk     (0x1UL << DSI_CLTCR_HS2LP_TIME3_Pos)      /*!< 0x00080000 */
+#define DSI_CLTCR_HS2LP_TIME3         DSI_CLTCR_HS2LP_TIME3_Msk                
+#define DSI_CLTCR_HS2LP_TIME4_Pos     (20U)                                    
+#define DSI_CLTCR_HS2LP_TIME4_Msk     (0x1UL << DSI_CLTCR_HS2LP_TIME4_Pos)      /*!< 0x00100000 */
+#define DSI_CLTCR_HS2LP_TIME4         DSI_CLTCR_HS2LP_TIME4_Msk                
+#define DSI_CLTCR_HS2LP_TIME5_Pos     (21U)                                    
+#define DSI_CLTCR_HS2LP_TIME5_Msk     (0x1UL << DSI_CLTCR_HS2LP_TIME5_Pos)      /*!< 0x00200000 */
+#define DSI_CLTCR_HS2LP_TIME5         DSI_CLTCR_HS2LP_TIME5_Msk                
+#define DSI_CLTCR_HS2LP_TIME6_Pos     (22U)                                    
+#define DSI_CLTCR_HS2LP_TIME6_Msk     (0x1UL << DSI_CLTCR_HS2LP_TIME6_Pos)      /*!< 0x00400000 */
+#define DSI_CLTCR_HS2LP_TIME6         DSI_CLTCR_HS2LP_TIME6_Msk                
+#define DSI_CLTCR_HS2LP_TIME7_Pos     (23U)                                    
+#define DSI_CLTCR_HS2LP_TIME7_Msk     (0x1UL << DSI_CLTCR_HS2LP_TIME7_Pos)      /*!< 0x00800000 */
+#define DSI_CLTCR_HS2LP_TIME7         DSI_CLTCR_HS2LP_TIME7_Msk                
+#define DSI_CLTCR_HS2LP_TIME8_Pos     (24U)                                    
+#define DSI_CLTCR_HS2LP_TIME8_Msk     (0x1UL << DSI_CLTCR_HS2LP_TIME8_Pos)      /*!< 0x01000000 */
+#define DSI_CLTCR_HS2LP_TIME8         DSI_CLTCR_HS2LP_TIME8_Msk                
+#define DSI_CLTCR_HS2LP_TIME9_Pos     (25U)                                    
+#define DSI_CLTCR_HS2LP_TIME9_Msk     (0x1UL << DSI_CLTCR_HS2LP_TIME9_Pos)      /*!< 0x02000000 */
+#define DSI_CLTCR_HS2LP_TIME9         DSI_CLTCR_HS2LP_TIME9_Msk                
+
+/*******************  Bit definition for DSI_DLTCR register  **************/
+#define DSI_DLTCR_MRD_TIME_Pos        (0U)                                     
+#define DSI_DLTCR_MRD_TIME_Msk        (0x7FFFUL << DSI_DLTCR_MRD_TIME_Pos)      /*!< 0x00007FFF */
+#define DSI_DLTCR_MRD_TIME            DSI_DLTCR_MRD_TIME_Msk                   /*!< Maximum Read Time */
+#define DSI_DLTCR_MRD_TIME0_Pos       (0U)                                     
+#define DSI_DLTCR_MRD_TIME0_Msk       (0x1UL << DSI_DLTCR_MRD_TIME0_Pos)        /*!< 0x00000001 */
+#define DSI_DLTCR_MRD_TIME0           DSI_DLTCR_MRD_TIME0_Msk                  
+#define DSI_DLTCR_MRD_TIME1_Pos       (1U)                                     
+#define DSI_DLTCR_MRD_TIME1_Msk       (0x1UL << DSI_DLTCR_MRD_TIME1_Pos)        /*!< 0x00000002 */
+#define DSI_DLTCR_MRD_TIME1           DSI_DLTCR_MRD_TIME1_Msk                  
+#define DSI_DLTCR_MRD_TIME2_Pos       (2U)                                     
+#define DSI_DLTCR_MRD_TIME2_Msk       (0x1UL << DSI_DLTCR_MRD_TIME2_Pos)        /*!< 0x00000004 */
+#define DSI_DLTCR_MRD_TIME2           DSI_DLTCR_MRD_TIME2_Msk                  
+#define DSI_DLTCR_MRD_TIME3_Pos       (3U)                                     
+#define DSI_DLTCR_MRD_TIME3_Msk       (0x1UL << DSI_DLTCR_MRD_TIME3_Pos)        /*!< 0x00000008 */
+#define DSI_DLTCR_MRD_TIME3           DSI_DLTCR_MRD_TIME3_Msk                  
+#define DSI_DLTCR_MRD_TIME4_Pos       (4U)                                     
+#define DSI_DLTCR_MRD_TIME4_Msk       (0x1UL << DSI_DLTCR_MRD_TIME4_Pos)        /*!< 0x00000010 */
+#define DSI_DLTCR_MRD_TIME4           DSI_DLTCR_MRD_TIME4_Msk                  
+#define DSI_DLTCR_MRD_TIME5_Pos       (5U)                                     
+#define DSI_DLTCR_MRD_TIME5_Msk       (0x1UL << DSI_DLTCR_MRD_TIME5_Pos)        /*!< 0x00000020 */
+#define DSI_DLTCR_MRD_TIME5           DSI_DLTCR_MRD_TIME5_Msk                  
+#define DSI_DLTCR_MRD_TIME6_Pos       (6U)                                     
+#define DSI_DLTCR_MRD_TIME6_Msk       (0x1UL << DSI_DLTCR_MRD_TIME6_Pos)        /*!< 0x00000040 */
+#define DSI_DLTCR_MRD_TIME6           DSI_DLTCR_MRD_TIME6_Msk                  
+#define DSI_DLTCR_MRD_TIME7_Pos       (7U)                                     
+#define DSI_DLTCR_MRD_TIME7_Msk       (0x1UL << DSI_DLTCR_MRD_TIME7_Pos)        /*!< 0x00000080 */
+#define DSI_DLTCR_MRD_TIME7           DSI_DLTCR_MRD_TIME7_Msk                  
+#define DSI_DLTCR_MRD_TIME8_Pos       (8U)                                     
+#define DSI_DLTCR_MRD_TIME8_Msk       (0x1UL << DSI_DLTCR_MRD_TIME8_Pos)        /*!< 0x00000100 */
+#define DSI_DLTCR_MRD_TIME8           DSI_DLTCR_MRD_TIME8_Msk                  
+#define DSI_DLTCR_MRD_TIME9_Pos       (9U)                                     
+#define DSI_DLTCR_MRD_TIME9_Msk       (0x1UL << DSI_DLTCR_MRD_TIME9_Pos)        /*!< 0x00000200 */
+#define DSI_DLTCR_MRD_TIME9           DSI_DLTCR_MRD_TIME9_Msk                  
+#define DSI_DLTCR_MRD_TIME10_Pos      (10U)                                    
+#define DSI_DLTCR_MRD_TIME10_Msk      (0x1UL << DSI_DLTCR_MRD_TIME10_Pos)       /*!< 0x00000400 */
+#define DSI_DLTCR_MRD_TIME10          DSI_DLTCR_MRD_TIME10_Msk                 
+#define DSI_DLTCR_MRD_TIME11_Pos      (11U)                                    
+#define DSI_DLTCR_MRD_TIME11_Msk      (0x1UL << DSI_DLTCR_MRD_TIME11_Pos)       /*!< 0x00000800 */
+#define DSI_DLTCR_MRD_TIME11          DSI_DLTCR_MRD_TIME11_Msk                 
+#define DSI_DLTCR_MRD_TIME12_Pos      (12U)                                    
+#define DSI_DLTCR_MRD_TIME12_Msk      (0x1UL << DSI_DLTCR_MRD_TIME12_Pos)       /*!< 0x00001000 */
+#define DSI_DLTCR_MRD_TIME12          DSI_DLTCR_MRD_TIME12_Msk                 
+#define DSI_DLTCR_MRD_TIME13_Pos      (13U)                                    
+#define DSI_DLTCR_MRD_TIME13_Msk      (0x1UL << DSI_DLTCR_MRD_TIME13_Pos)       /*!< 0x00002000 */
+#define DSI_DLTCR_MRD_TIME13          DSI_DLTCR_MRD_TIME13_Msk                 
+#define DSI_DLTCR_MRD_TIME14_Pos      (14U)                                    
+#define DSI_DLTCR_MRD_TIME14_Msk      (0x1UL << DSI_DLTCR_MRD_TIME14_Pos)       /*!< 0x00004000 */
+#define DSI_DLTCR_MRD_TIME14          DSI_DLTCR_MRD_TIME14_Msk                 
+
+#define DSI_DLTCR_LP2HS_TIME_Pos      (16U)                                    
+#define DSI_DLTCR_LP2HS_TIME_Msk      (0xFFUL << DSI_DLTCR_LP2HS_TIME_Pos)      /*!< 0x00FF0000 */
+#define DSI_DLTCR_LP2HS_TIME          DSI_DLTCR_LP2HS_TIME_Msk                 /*!< Low-Power To High-Speed Time */
+#define DSI_DLTCR_LP2HS_TIME0_Pos     (16U)                                    
+#define DSI_DLTCR_LP2HS_TIME0_Msk     (0x1UL << DSI_DLTCR_LP2HS_TIME0_Pos)      /*!< 0x00010000 */
+#define DSI_DLTCR_LP2HS_TIME0         DSI_DLTCR_LP2HS_TIME0_Msk                
+#define DSI_DLTCR_LP2HS_TIME1_Pos     (17U)                                    
+#define DSI_DLTCR_LP2HS_TIME1_Msk     (0x1UL << DSI_DLTCR_LP2HS_TIME1_Pos)      /*!< 0x00020000 */
+#define DSI_DLTCR_LP2HS_TIME1         DSI_DLTCR_LP2HS_TIME1_Msk                
+#define DSI_DLTCR_LP2HS_TIME2_Pos     (18U)                                    
+#define DSI_DLTCR_LP2HS_TIME2_Msk     (0x1UL << DSI_DLTCR_LP2HS_TIME2_Pos)      /*!< 0x00040000 */
+#define DSI_DLTCR_LP2HS_TIME2         DSI_DLTCR_LP2HS_TIME2_Msk                
+#define DSI_DLTCR_LP2HS_TIME3_Pos     (19U)                                    
+#define DSI_DLTCR_LP2HS_TIME3_Msk     (0x1UL << DSI_DLTCR_LP2HS_TIME3_Pos)      /*!< 0x00080000 */
+#define DSI_DLTCR_LP2HS_TIME3         DSI_DLTCR_LP2HS_TIME3_Msk                
+#define DSI_DLTCR_LP2HS_TIME4_Pos     (20U)                                    
+#define DSI_DLTCR_LP2HS_TIME4_Msk     (0x1UL << DSI_DLTCR_LP2HS_TIME4_Pos)      /*!< 0x00100000 */
+#define DSI_DLTCR_LP2HS_TIME4         DSI_DLTCR_LP2HS_TIME4_Msk                
+#define DSI_DLTCR_LP2HS_TIME5_Pos     (21U)                                    
+#define DSI_DLTCR_LP2HS_TIME5_Msk     (0x1UL << DSI_DLTCR_LP2HS_TIME5_Pos)      /*!< 0x00200000 */
+#define DSI_DLTCR_LP2HS_TIME5         DSI_DLTCR_LP2HS_TIME5_Msk                
+#define DSI_DLTCR_LP2HS_TIME6_Pos     (22U)                                    
+#define DSI_DLTCR_LP2HS_TIME6_Msk     (0x1UL << DSI_DLTCR_LP2HS_TIME6_Pos)      /*!< 0x00400000 */
+#define DSI_DLTCR_LP2HS_TIME6         DSI_DLTCR_LP2HS_TIME6_Msk                
+#define DSI_DLTCR_LP2HS_TIME7_Pos     (23U)                                    
+#define DSI_DLTCR_LP2HS_TIME7_Msk     (0x1UL << DSI_DLTCR_LP2HS_TIME7_Pos)      /*!< 0x00800000 */
+#define DSI_DLTCR_LP2HS_TIME7         DSI_DLTCR_LP2HS_TIME7_Msk                
+
+#define DSI_DLTCR_HS2LP_TIME_Pos      (24U)                                    
+#define DSI_DLTCR_HS2LP_TIME_Msk      (0xFFUL << DSI_DLTCR_HS2LP_TIME_Pos)      /*!< 0xFF000000 */
+#define DSI_DLTCR_HS2LP_TIME          DSI_DLTCR_HS2LP_TIME_Msk                 /*!< High-Speed To Low-Power Time */
+#define DSI_DLTCR_HS2LP_TIME0_Pos     (24U)                                    
+#define DSI_DLTCR_HS2LP_TIME0_Msk     (0x1UL << DSI_DLTCR_HS2LP_TIME0_Pos)      /*!< 0x01000000 */
+#define DSI_DLTCR_HS2LP_TIME0         DSI_DLTCR_HS2LP_TIME0_Msk                
+#define DSI_DLTCR_HS2LP_TIME1_Pos     (25U)                                    
+#define DSI_DLTCR_HS2LP_TIME1_Msk     (0x1UL << DSI_DLTCR_HS2LP_TIME1_Pos)      /*!< 0x02000000 */
+#define DSI_DLTCR_HS2LP_TIME1         DSI_DLTCR_HS2LP_TIME1_Msk                
+#define DSI_DLTCR_HS2LP_TIME2_Pos     (26U)                                    
+#define DSI_DLTCR_HS2LP_TIME2_Msk     (0x1UL << DSI_DLTCR_HS2LP_TIME2_Pos)      /*!< 0x04000000 */
+#define DSI_DLTCR_HS2LP_TIME2         DSI_DLTCR_HS2LP_TIME2_Msk                
+#define DSI_DLTCR_HS2LP_TIME3_Pos     (27U)                                    
+#define DSI_DLTCR_HS2LP_TIME3_Msk     (0x1UL << DSI_DLTCR_HS2LP_TIME3_Pos)      /*!< 0x08000000 */
+#define DSI_DLTCR_HS2LP_TIME3         DSI_DLTCR_HS2LP_TIME3_Msk                
+#define DSI_DLTCR_HS2LP_TIME4_Pos     (28U)                                    
+#define DSI_DLTCR_HS2LP_TIME4_Msk     (0x1UL << DSI_DLTCR_HS2LP_TIME4_Pos)      /*!< 0x10000000 */
+#define DSI_DLTCR_HS2LP_TIME4         DSI_DLTCR_HS2LP_TIME4_Msk                
+#define DSI_DLTCR_HS2LP_TIME5_Pos     (29U)                                    
+#define DSI_DLTCR_HS2LP_TIME5_Msk     (0x1UL << DSI_DLTCR_HS2LP_TIME5_Pos)      /*!< 0x20000000 */
+#define DSI_DLTCR_HS2LP_TIME5         DSI_DLTCR_HS2LP_TIME5_Msk                
+#define DSI_DLTCR_HS2LP_TIME6_Pos     (30U)                                    
+#define DSI_DLTCR_HS2LP_TIME6_Msk     (0x1UL << DSI_DLTCR_HS2LP_TIME6_Pos)      /*!< 0x40000000 */
+#define DSI_DLTCR_HS2LP_TIME6         DSI_DLTCR_HS2LP_TIME6_Msk                
+#define DSI_DLTCR_HS2LP_TIME7_Pos     (31U)                                    
+#define DSI_DLTCR_HS2LP_TIME7_Msk     (0x1UL << DSI_DLTCR_HS2LP_TIME7_Pos)      /*!< 0x80000000 */
+#define DSI_DLTCR_HS2LP_TIME7         DSI_DLTCR_HS2LP_TIME7_Msk                
+
+/*******************  Bit definition for DSI_PCTLR register  **************/
+#define DSI_PCTLR_DEN_Pos             (1U)                                     
+#define DSI_PCTLR_DEN_Msk             (0x1UL << DSI_PCTLR_DEN_Pos)              /*!< 0x00000002 */
+#define DSI_PCTLR_DEN                 DSI_PCTLR_DEN_Msk                        /*!< Digital Enable */
+#define DSI_PCTLR_CKE_Pos             (2U)                                     
+#define DSI_PCTLR_CKE_Msk             (0x1UL << DSI_PCTLR_CKE_Pos)              /*!< 0x00000004 */
+#define DSI_PCTLR_CKE                 DSI_PCTLR_CKE_Msk                        /*!< Clock Enable */
+
+/*******************  Bit definition for DSI_PCONFR register  *************/
+#define DSI_PCONFR_NL_Pos             (0U)                                     
+#define DSI_PCONFR_NL_Msk             (0x3UL << DSI_PCONFR_NL_Pos)              /*!< 0x00000003 */
+#define DSI_PCONFR_NL                 DSI_PCONFR_NL_Msk                        /*!< Number of Lanes */
+#define DSI_PCONFR_NL0_Pos            (0U)                                     
+#define DSI_PCONFR_NL0_Msk            (0x1UL << DSI_PCONFR_NL0_Pos)             /*!< 0x00000001 */
+#define DSI_PCONFR_NL0                DSI_PCONFR_NL0_Msk                       
+#define DSI_PCONFR_NL1_Pos            (1U)                                     
+#define DSI_PCONFR_NL1_Msk            (0x1UL << DSI_PCONFR_NL1_Pos)             /*!< 0x00000002 */
+#define DSI_PCONFR_NL1                DSI_PCONFR_NL1_Msk                       
+
+#define DSI_PCONFR_SW_TIME_Pos        (8U)                                     
+#define DSI_PCONFR_SW_TIME_Msk        (0xFFUL << DSI_PCONFR_SW_TIME_Pos)        /*!< 0x0000FF00 */
+#define DSI_PCONFR_SW_TIME            DSI_PCONFR_SW_TIME_Msk                   /*!< Stop Wait Time */
+#define DSI_PCONFR_SW_TIME0_Pos       (8U)                                     
+#define DSI_PCONFR_SW_TIME0_Msk       (0x1UL << DSI_PCONFR_SW_TIME0_Pos)        /*!< 0x00000100 */
+#define DSI_PCONFR_SW_TIME0           DSI_PCONFR_SW_TIME0_Msk                  
+#define DSI_PCONFR_SW_TIME1_Pos       (9U)                                     
+#define DSI_PCONFR_SW_TIME1_Msk       (0x1UL << DSI_PCONFR_SW_TIME1_Pos)        /*!< 0x00000200 */
+#define DSI_PCONFR_SW_TIME1           DSI_PCONFR_SW_TIME1_Msk                  
+#define DSI_PCONFR_SW_TIME2_Pos       (10U)                                    
+#define DSI_PCONFR_SW_TIME2_Msk       (0x1UL << DSI_PCONFR_SW_TIME2_Pos)        /*!< 0x00000400 */
+#define DSI_PCONFR_SW_TIME2           DSI_PCONFR_SW_TIME2_Msk                  
+#define DSI_PCONFR_SW_TIME3_Pos       (11U)                                    
+#define DSI_PCONFR_SW_TIME3_Msk       (0x1UL << DSI_PCONFR_SW_TIME3_Pos)        /*!< 0x00000800 */
+#define DSI_PCONFR_SW_TIME3           DSI_PCONFR_SW_TIME3_Msk                  
+#define DSI_PCONFR_SW_TIME4_Pos       (12U)                                    
+#define DSI_PCONFR_SW_TIME4_Msk       (0x1UL << DSI_PCONFR_SW_TIME4_Pos)        /*!< 0x00001000 */
+#define DSI_PCONFR_SW_TIME4           DSI_PCONFR_SW_TIME4_Msk                  
+#define DSI_PCONFR_SW_TIME5_Pos       (13U)                                    
+#define DSI_PCONFR_SW_TIME5_Msk       (0x1UL << DSI_PCONFR_SW_TIME5_Pos)        /*!< 0x00002000 */
+#define DSI_PCONFR_SW_TIME5           DSI_PCONFR_SW_TIME5_Msk                  
+#define DSI_PCONFR_SW_TIME6_Pos       (14U)                                    
+#define DSI_PCONFR_SW_TIME6_Msk       (0x1UL << DSI_PCONFR_SW_TIME6_Pos)        /*!< 0x00004000 */
+#define DSI_PCONFR_SW_TIME6           DSI_PCONFR_SW_TIME6_Msk                  
+#define DSI_PCONFR_SW_TIME7_Pos       (15U)                                    
+#define DSI_PCONFR_SW_TIME7_Msk       (0x1UL << DSI_PCONFR_SW_TIME7_Pos)        /*!< 0x00008000 */
+#define DSI_PCONFR_SW_TIME7           DSI_PCONFR_SW_TIME7_Msk                  
+
+/*******************  Bit definition for DSI_PUCR register  ***************/
+#define DSI_PUCR_URCL_Pos             (0U)                                     
+#define DSI_PUCR_URCL_Msk             (0x1UL << DSI_PUCR_URCL_Pos)              /*!< 0x00000001 */
+#define DSI_PUCR_URCL                 DSI_PUCR_URCL_Msk                        /*!< ULPS Request on Clock Lane */
+#define DSI_PUCR_UECL_Pos             (1U)                                     
+#define DSI_PUCR_UECL_Msk             (0x1UL << DSI_PUCR_UECL_Pos)              /*!< 0x00000002 */
+#define DSI_PUCR_UECL                 DSI_PUCR_UECL_Msk                        /*!< ULPS Exit on Clock Lane */
+#define DSI_PUCR_URDL_Pos             (2U)                                     
+#define DSI_PUCR_URDL_Msk             (0x1UL << DSI_PUCR_URDL_Pos)              /*!< 0x00000004 */
+#define DSI_PUCR_URDL                 DSI_PUCR_URDL_Msk                        /*!< ULPS Request on Data Lane */
+#define DSI_PUCR_UEDL_Pos             (3U)                                     
+#define DSI_PUCR_UEDL_Msk             (0x1UL << DSI_PUCR_UEDL_Pos)              /*!< 0x00000008 */
+#define DSI_PUCR_UEDL                 DSI_PUCR_UEDL_Msk                        /*!< ULPS Exit on Data Lane */
+
+/*******************  Bit definition for DSI_PTTCR register  **************/
+#define DSI_PTTCR_TX_TRIG_Pos         (0U)                                     
+#define DSI_PTTCR_TX_TRIG_Msk         (0xFUL << DSI_PTTCR_TX_TRIG_Pos)          /*!< 0x0000000F */
+#define DSI_PTTCR_TX_TRIG             DSI_PTTCR_TX_TRIG_Msk                    /*!< Transmission Trigger */
+#define DSI_PTTCR_TX_TRIG0_Pos        (0U)                                     
+#define DSI_PTTCR_TX_TRIG0_Msk        (0x1UL << DSI_PTTCR_TX_TRIG0_Pos)         /*!< 0x00000001 */
+#define DSI_PTTCR_TX_TRIG0            DSI_PTTCR_TX_TRIG0_Msk                   
+#define DSI_PTTCR_TX_TRIG1_Pos        (1U)                                     
+#define DSI_PTTCR_TX_TRIG1_Msk        (0x1UL << DSI_PTTCR_TX_TRIG1_Pos)         /*!< 0x00000002 */
+#define DSI_PTTCR_TX_TRIG1            DSI_PTTCR_TX_TRIG1_Msk                   
+#define DSI_PTTCR_TX_TRIG2_Pos        (2U)                                     
+#define DSI_PTTCR_TX_TRIG2_Msk        (0x1UL << DSI_PTTCR_TX_TRIG2_Pos)         /*!< 0x00000004 */
+#define DSI_PTTCR_TX_TRIG2            DSI_PTTCR_TX_TRIG2_Msk                   
+#define DSI_PTTCR_TX_TRIG3_Pos        (3U)                                     
+#define DSI_PTTCR_TX_TRIG3_Msk        (0x1UL << DSI_PTTCR_TX_TRIG3_Pos)         /*!< 0x00000008 */
+#define DSI_PTTCR_TX_TRIG3            DSI_PTTCR_TX_TRIG3_Msk                   
+
+/*******************  Bit definition for DSI_PSR register  ****************/
+#define DSI_PSR_PD_Pos                (1U)                                     
+#define DSI_PSR_PD_Msk                (0x1UL << DSI_PSR_PD_Pos)                 /*!< 0x00000002 */
+#define DSI_PSR_PD                    DSI_PSR_PD_Msk                           /*!< PHY Direction */
+#define DSI_PSR_PSSC_Pos              (2U)                                     
+#define DSI_PSR_PSSC_Msk              (0x1UL << DSI_PSR_PSSC_Pos)               /*!< 0x00000004 */
+#define DSI_PSR_PSSC                  DSI_PSR_PSSC_Msk                         /*!< PHY Stop State Clock lane */
+#define DSI_PSR_UANC_Pos              (3U)                                     
+#define DSI_PSR_UANC_Msk              (0x1UL << DSI_PSR_UANC_Pos)               /*!< 0x00000008 */
+#define DSI_PSR_UANC                  DSI_PSR_UANC_Msk                         /*!< ULPS Active Not Clock lane */
+#define DSI_PSR_PSS0_Pos              (4U)                                     
+#define DSI_PSR_PSS0_Msk              (0x1UL << DSI_PSR_PSS0_Pos)               /*!< 0x00000010 */
+#define DSI_PSR_PSS0                  DSI_PSR_PSS0_Msk                         /*!< PHY Stop State lane 0 */
+#define DSI_PSR_UAN0_Pos              (5U)                                     
+#define DSI_PSR_UAN0_Msk              (0x1UL << DSI_PSR_UAN0_Pos)               /*!< 0x00000020 */
+#define DSI_PSR_UAN0                  DSI_PSR_UAN0_Msk                         /*!< ULPS Active Not lane 0 */
+#define DSI_PSR_RUE0_Pos              (6U)                                     
+#define DSI_PSR_RUE0_Msk              (0x1UL << DSI_PSR_RUE0_Pos)               /*!< 0x00000040 */
+#define DSI_PSR_RUE0                  DSI_PSR_RUE0_Msk                         /*!< RX ULPS Escape lane 0 */
+#define DSI_PSR_PSS1_Pos              (7U)                                     
+#define DSI_PSR_PSS1_Msk              (0x1UL << DSI_PSR_PSS1_Pos)               /*!< 0x00000080 */
+#define DSI_PSR_PSS1                  DSI_PSR_PSS1_Msk                         /*!< PHY Stop State lane 1 */
+#define DSI_PSR_UAN1_Pos              (8U)                                     
+#define DSI_PSR_UAN1_Msk              (0x1UL << DSI_PSR_UAN1_Pos)               /*!< 0x00000100 */
+#define DSI_PSR_UAN1                  DSI_PSR_UAN1_Msk                         /*!< ULPS Active Not lane 1 */
+
+/*******************  Bit definition for DSI_ISR0 register  ***************/
+#define DSI_ISR0_AE0_Pos              (0U)                                     
+#define DSI_ISR0_AE0_Msk              (0x1UL << DSI_ISR0_AE0_Pos)               /*!< 0x00000001 */
+#define DSI_ISR0_AE0                  DSI_ISR0_AE0_Msk                         /*!< Acknowledge Error 0 */
+#define DSI_ISR0_AE1_Pos              (1U)                                     
+#define DSI_ISR0_AE1_Msk              (0x1UL << DSI_ISR0_AE1_Pos)               /*!< 0x00000002 */
+#define DSI_ISR0_AE1                  DSI_ISR0_AE1_Msk                         /*!< Acknowledge Error 1 */
+#define DSI_ISR0_AE2_Pos              (2U)                                     
+#define DSI_ISR0_AE2_Msk              (0x1UL << DSI_ISR0_AE2_Pos)               /*!< 0x00000004 */
+#define DSI_ISR0_AE2                  DSI_ISR0_AE2_Msk                         /*!< Acknowledge Error 2 */
+#define DSI_ISR0_AE3_Pos              (3U)                                     
+#define DSI_ISR0_AE3_Msk              (0x1UL << DSI_ISR0_AE3_Pos)               /*!< 0x00000008 */
+#define DSI_ISR0_AE3                  DSI_ISR0_AE3_Msk                         /*!< Acknowledge Error 3 */
+#define DSI_ISR0_AE4_Pos              (4U)                                     
+#define DSI_ISR0_AE4_Msk              (0x1UL << DSI_ISR0_AE4_Pos)               /*!< 0x00000010 */
+#define DSI_ISR0_AE4                  DSI_ISR0_AE4_Msk                         /*!< Acknowledge Error 4 */
+#define DSI_ISR0_AE5_Pos              (5U)                                     
+#define DSI_ISR0_AE5_Msk              (0x1UL << DSI_ISR0_AE5_Pos)               /*!< 0x00000020 */
+#define DSI_ISR0_AE5                  DSI_ISR0_AE5_Msk                         /*!< Acknowledge Error 5 */
+#define DSI_ISR0_AE6_Pos              (6U)                                     
+#define DSI_ISR0_AE6_Msk              (0x1UL << DSI_ISR0_AE6_Pos)               /*!< 0x00000040 */
+#define DSI_ISR0_AE6                  DSI_ISR0_AE6_Msk                         /*!< Acknowledge Error 6 */
+#define DSI_ISR0_AE7_Pos              (7U)                                     
+#define DSI_ISR0_AE7_Msk              (0x1UL << DSI_ISR0_AE7_Pos)               /*!< 0x00000080 */
+#define DSI_ISR0_AE7                  DSI_ISR0_AE7_Msk                         /*!< Acknowledge Error 7 */
+#define DSI_ISR0_AE8_Pos              (8U)                                     
+#define DSI_ISR0_AE8_Msk              (0x1UL << DSI_ISR0_AE8_Pos)               /*!< 0x00000100 */
+#define DSI_ISR0_AE8                  DSI_ISR0_AE8_Msk                         /*!< Acknowledge Error 8 */
+#define DSI_ISR0_AE9_Pos              (9U)                                     
+#define DSI_ISR0_AE9_Msk              (0x1UL << DSI_ISR0_AE9_Pos)               /*!< 0x00000200 */
+#define DSI_ISR0_AE9                  DSI_ISR0_AE9_Msk                         /*!< Acknowledge Error 9 */
+#define DSI_ISR0_AE10_Pos             (10U)                                    
+#define DSI_ISR0_AE10_Msk             (0x1UL << DSI_ISR0_AE10_Pos)              /*!< 0x00000400 */
+#define DSI_ISR0_AE10                 DSI_ISR0_AE10_Msk                        /*!< Acknowledge Error 10 */
+#define DSI_ISR0_AE11_Pos             (11U)                                    
+#define DSI_ISR0_AE11_Msk             (0x1UL << DSI_ISR0_AE11_Pos)              /*!< 0x00000800 */
+#define DSI_ISR0_AE11                 DSI_ISR0_AE11_Msk                        /*!< Acknowledge Error 11 */
+#define DSI_ISR0_AE12_Pos             (12U)                                    
+#define DSI_ISR0_AE12_Msk             (0x1UL << DSI_ISR0_AE12_Pos)              /*!< 0x00001000 */
+#define DSI_ISR0_AE12                 DSI_ISR0_AE12_Msk                        /*!< Acknowledge Error 12 */
+#define DSI_ISR0_AE13_Pos             (13U)                                    
+#define DSI_ISR0_AE13_Msk             (0x1UL << DSI_ISR0_AE13_Pos)              /*!< 0x00002000 */
+#define DSI_ISR0_AE13                 DSI_ISR0_AE13_Msk                        /*!< Acknowledge Error 13 */
+#define DSI_ISR0_AE14_Pos             (14U)                                    
+#define DSI_ISR0_AE14_Msk             (0x1UL << DSI_ISR0_AE14_Pos)              /*!< 0x00004000 */
+#define DSI_ISR0_AE14                 DSI_ISR0_AE14_Msk                        /*!< Acknowledge Error 14 */
+#define DSI_ISR0_AE15_Pos             (15U)                                    
+#define DSI_ISR0_AE15_Msk             (0x1UL << DSI_ISR0_AE15_Pos)              /*!< 0x00008000 */
+#define DSI_ISR0_AE15                 DSI_ISR0_AE15_Msk                        /*!< Acknowledge Error 15 */
+#define DSI_ISR0_PE0_Pos              (16U)                                    
+#define DSI_ISR0_PE0_Msk              (0x1UL << DSI_ISR0_PE0_Pos)               /*!< 0x00010000 */
+#define DSI_ISR0_PE0                  DSI_ISR0_PE0_Msk                         /*!< PHY Error 0 */
+#define DSI_ISR0_PE1_Pos              (17U)                                    
+#define DSI_ISR0_PE1_Msk              (0x1UL << DSI_ISR0_PE1_Pos)               /*!< 0x00020000 */
+#define DSI_ISR0_PE1                  DSI_ISR0_PE1_Msk                         /*!< PHY Error 1 */
+#define DSI_ISR0_PE2_Pos              (18U)                                    
+#define DSI_ISR0_PE2_Msk              (0x1UL << DSI_ISR0_PE2_Pos)               /*!< 0x00040000 */
+#define DSI_ISR0_PE2                  DSI_ISR0_PE2_Msk                         /*!< PHY Error 2 */
+#define DSI_ISR0_PE3_Pos              (19U)                                    
+#define DSI_ISR0_PE3_Msk              (0x1UL << DSI_ISR0_PE3_Pos)               /*!< 0x00080000 */
+#define DSI_ISR0_PE3                  DSI_ISR0_PE3_Msk                         /*!< PHY Error 3 */
+#define DSI_ISR0_PE4_Pos              (20U)                                    
+#define DSI_ISR0_PE4_Msk              (0x1UL << DSI_ISR0_PE4_Pos)               /*!< 0x00100000 */
+#define DSI_ISR0_PE4                  DSI_ISR0_PE4_Msk                         /*!< PHY Error 4 */
+
+/*******************  Bit definition for DSI_ISR1 register  ***************/
+#define DSI_ISR1_TOHSTX_Pos           (0U)                                     
+#define DSI_ISR1_TOHSTX_Msk           (0x1UL << DSI_ISR1_TOHSTX_Pos)            /*!< 0x00000001 */
+#define DSI_ISR1_TOHSTX               DSI_ISR1_TOHSTX_Msk                      /*!< Timeout High-Speed Transmission */
+#define DSI_ISR1_TOLPRX_Pos           (1U)                                     
+#define DSI_ISR1_TOLPRX_Msk           (0x1UL << DSI_ISR1_TOLPRX_Pos)            /*!< 0x00000002 */
+#define DSI_ISR1_TOLPRX               DSI_ISR1_TOLPRX_Msk                      /*!< Timeout Low-Power Reception */
+#define DSI_ISR1_ECCSE_Pos            (2U)                                     
+#define DSI_ISR1_ECCSE_Msk            (0x1UL << DSI_ISR1_ECCSE_Pos)             /*!< 0x00000004 */
+#define DSI_ISR1_ECCSE                DSI_ISR1_ECCSE_Msk                       /*!< ECC Single-bit Error */
+#define DSI_ISR1_ECCME_Pos            (3U)                                     
+#define DSI_ISR1_ECCME_Msk            (0x1UL << DSI_ISR1_ECCME_Pos)             /*!< 0x00000008 */
+#define DSI_ISR1_ECCME                DSI_ISR1_ECCME_Msk                       /*!< ECC Multi-bit Error */
+#define DSI_ISR1_CRCE_Pos             (4U)                                     
+#define DSI_ISR1_CRCE_Msk             (0x1UL << DSI_ISR1_CRCE_Pos)              /*!< 0x00000010 */
+#define DSI_ISR1_CRCE                 DSI_ISR1_CRCE_Msk                        /*!< CRC Error */
+#define DSI_ISR1_PSE_Pos              (5U)                                     
+#define DSI_ISR1_PSE_Msk              (0x1UL << DSI_ISR1_PSE_Pos)               /*!< 0x00000020 */
+#define DSI_ISR1_PSE                  DSI_ISR1_PSE_Msk                         /*!< Packet Size Error */
+#define DSI_ISR1_EOTPE_Pos            (6U)                                     
+#define DSI_ISR1_EOTPE_Msk            (0x1UL << DSI_ISR1_EOTPE_Pos)             /*!< 0x00000040 */
+#define DSI_ISR1_EOTPE                DSI_ISR1_EOTPE_Msk                       /*!< EoTp Error */
+#define DSI_ISR1_LPWRE_Pos            (7U)                                     
+#define DSI_ISR1_LPWRE_Msk            (0x1UL << DSI_ISR1_LPWRE_Pos)             /*!< 0x00000080 */
+#define DSI_ISR1_LPWRE                DSI_ISR1_LPWRE_Msk                       /*!< LTDC Payload Write Error */
+#define DSI_ISR1_GCWRE_Pos            (8U)                                     
+#define DSI_ISR1_GCWRE_Msk            (0x1UL << DSI_ISR1_GCWRE_Pos)             /*!< 0x00000100 */
+#define DSI_ISR1_GCWRE                DSI_ISR1_GCWRE_Msk                       /*!< Generic Command Write Error */
+#define DSI_ISR1_GPWRE_Pos            (9U)                                     
+#define DSI_ISR1_GPWRE_Msk            (0x1UL << DSI_ISR1_GPWRE_Pos)             /*!< 0x00000200 */
+#define DSI_ISR1_GPWRE                DSI_ISR1_GPWRE_Msk                       /*!< Generic Payload Write Error */
+#define DSI_ISR1_GPTXE_Pos            (10U)                                    
+#define DSI_ISR1_GPTXE_Msk            (0x1UL << DSI_ISR1_GPTXE_Pos)             /*!< 0x00000400 */
+#define DSI_ISR1_GPTXE                DSI_ISR1_GPTXE_Msk                       /*!< Generic Payload Transmit Error */
+#define DSI_ISR1_GPRDE_Pos            (11U)                                    
+#define DSI_ISR1_GPRDE_Msk            (0x1UL << DSI_ISR1_GPRDE_Pos)             /*!< 0x00000800 */
+#define DSI_ISR1_GPRDE                DSI_ISR1_GPRDE_Msk                       /*!< Generic Payload Read Error */
+#define DSI_ISR1_GPRXE_Pos            (12U)                                    
+#define DSI_ISR1_GPRXE_Msk            (0x1UL << DSI_ISR1_GPRXE_Pos)             /*!< 0x00001000 */
+#define DSI_ISR1_GPRXE                DSI_ISR1_GPRXE_Msk                       /*!< Generic Payload Receive Error */
+
+/*******************  Bit definition for DSI_IER0 register  ***************/
+#define DSI_IER0_AE0IE_Pos            (0U)                                     
+#define DSI_IER0_AE0IE_Msk            (0x1UL << DSI_IER0_AE0IE_Pos)             /*!< 0x00000001 */
+#define DSI_IER0_AE0IE                DSI_IER0_AE0IE_Msk                       /*!< Acknowledge Error 0 Interrupt Enable */
+#define DSI_IER0_AE1IE_Pos            (1U)                                     
+#define DSI_IER0_AE1IE_Msk            (0x1UL << DSI_IER0_AE1IE_Pos)             /*!< 0x00000002 */
+#define DSI_IER0_AE1IE                DSI_IER0_AE1IE_Msk                       /*!< Acknowledge Error 1 Interrupt Enable */
+#define DSI_IER0_AE2IE_Pos            (2U)                                     
+#define DSI_IER0_AE2IE_Msk            (0x1UL << DSI_IER0_AE2IE_Pos)             /*!< 0x00000004 */
+#define DSI_IER0_AE2IE                DSI_IER0_AE2IE_Msk                       /*!< Acknowledge Error 2 Interrupt Enable */
+#define DSI_IER0_AE3IE_Pos            (3U)                                     
+#define DSI_IER0_AE3IE_Msk            (0x1UL << DSI_IER0_AE3IE_Pos)             /*!< 0x00000008 */
+#define DSI_IER0_AE3IE                DSI_IER0_AE3IE_Msk                       /*!< Acknowledge Error 3 Interrupt Enable */
+#define DSI_IER0_AE4IE_Pos            (4U)                                     
+#define DSI_IER0_AE4IE_Msk            (0x1UL << DSI_IER0_AE4IE_Pos)             /*!< 0x00000010 */
+#define DSI_IER0_AE4IE                DSI_IER0_AE4IE_Msk                       /*!< Acknowledge Error 4 Interrupt Enable */
+#define DSI_IER0_AE5IE_Pos            (5U)                                     
+#define DSI_IER0_AE5IE_Msk            (0x1UL << DSI_IER0_AE5IE_Pos)             /*!< 0x00000020 */
+#define DSI_IER0_AE5IE                DSI_IER0_AE5IE_Msk                       /*!< Acknowledge Error 5 Interrupt Enable */
+#define DSI_IER0_AE6IE_Pos            (6U)                                     
+#define DSI_IER0_AE6IE_Msk            (0x1UL << DSI_IER0_AE6IE_Pos)             /*!< 0x00000040 */
+#define DSI_IER0_AE6IE                DSI_IER0_AE6IE_Msk                       /*!< Acknowledge Error 6 Interrupt Enable */
+#define DSI_IER0_AE7IE_Pos            (7U)                                     
+#define DSI_IER0_AE7IE_Msk            (0x1UL << DSI_IER0_AE7IE_Pos)             /*!< 0x00000080 */
+#define DSI_IER0_AE7IE                DSI_IER0_AE7IE_Msk                       /*!< Acknowledge Error 7 Interrupt Enable */
+#define DSI_IER0_AE8IE_Pos            (8U)                                     
+#define DSI_IER0_AE8IE_Msk            (0x1UL << DSI_IER0_AE8IE_Pos)             /*!< 0x00000100 */
+#define DSI_IER0_AE8IE                DSI_IER0_AE8IE_Msk                       /*!< Acknowledge Error 8 Interrupt Enable */
+#define DSI_IER0_AE9IE_Pos            (9U)                                     
+#define DSI_IER0_AE9IE_Msk            (0x1UL << DSI_IER0_AE9IE_Pos)             /*!< 0x00000200 */
+#define DSI_IER0_AE9IE                DSI_IER0_AE9IE_Msk                       /*!< Acknowledge Error 9 Interrupt Enable */
+#define DSI_IER0_AE10IE_Pos           (10U)                                    
+#define DSI_IER0_AE10IE_Msk           (0x1UL << DSI_IER0_AE10IE_Pos)            /*!< 0x00000400 */
+#define DSI_IER0_AE10IE               DSI_IER0_AE10IE_Msk                      /*!< Acknowledge Error 10 Interrupt Enable */
+#define DSI_IER0_AE11IE_Pos           (11U)                                    
+#define DSI_IER0_AE11IE_Msk           (0x1UL << DSI_IER0_AE11IE_Pos)            /*!< 0x00000800 */
+#define DSI_IER0_AE11IE               DSI_IER0_AE11IE_Msk                      /*!< Acknowledge Error 11 Interrupt Enable */
+#define DSI_IER0_AE12IE_Pos           (12U)                                    
+#define DSI_IER0_AE12IE_Msk           (0x1UL << DSI_IER0_AE12IE_Pos)            /*!< 0x00001000 */
+#define DSI_IER0_AE12IE               DSI_IER0_AE12IE_Msk                      /*!< Acknowledge Error 12 Interrupt Enable */
+#define DSI_IER0_AE13IE_Pos           (13U)                                    
+#define DSI_IER0_AE13IE_Msk           (0x1UL << DSI_IER0_AE13IE_Pos)            /*!< 0x00002000 */
+#define DSI_IER0_AE13IE               DSI_IER0_AE13IE_Msk                      /*!< Acknowledge Error 13 Interrupt Enable */
+#define DSI_IER0_AE14IE_Pos           (14U)                                    
+#define DSI_IER0_AE14IE_Msk           (0x1UL << DSI_IER0_AE14IE_Pos)            /*!< 0x00004000 */
+#define DSI_IER0_AE14IE               DSI_IER0_AE14IE_Msk                      /*!< Acknowledge Error 14 Interrupt Enable */
+#define DSI_IER0_AE15IE_Pos           (15U)                                    
+#define DSI_IER0_AE15IE_Msk           (0x1UL << DSI_IER0_AE15IE_Pos)            /*!< 0x00008000 */
+#define DSI_IER0_AE15IE               DSI_IER0_AE15IE_Msk                      /*!< Acknowledge Error 15 Interrupt Enable */
+#define DSI_IER0_PE0IE_Pos            (16U)                                    
+#define DSI_IER0_PE0IE_Msk            (0x1UL << DSI_IER0_PE0IE_Pos)             /*!< 0x00010000 */
+#define DSI_IER0_PE0IE                DSI_IER0_PE0IE_Msk                       /*!< PHY Error 0 Interrupt Enable */
+#define DSI_IER0_PE1IE_Pos            (17U)                                    
+#define DSI_IER0_PE1IE_Msk            (0x1UL << DSI_IER0_PE1IE_Pos)             /*!< 0x00020000 */
+#define DSI_IER0_PE1IE                DSI_IER0_PE1IE_Msk                       /*!< PHY Error 1 Interrupt Enable */
+#define DSI_IER0_PE2IE_Pos            (18U)                                    
+#define DSI_IER0_PE2IE_Msk            (0x1UL << DSI_IER0_PE2IE_Pos)             /*!< 0x00040000 */
+#define DSI_IER0_PE2IE                DSI_IER0_PE2IE_Msk                       /*!< PHY Error 2 Interrupt Enable */
+#define DSI_IER0_PE3IE_Pos            (19U)                                    
+#define DSI_IER0_PE3IE_Msk            (0x1UL << DSI_IER0_PE3IE_Pos)             /*!< 0x00080000 */
+#define DSI_IER0_PE3IE                DSI_IER0_PE3IE_Msk                       /*!< PHY Error 3 Interrupt Enable */
+#define DSI_IER0_PE4IE_Pos            (20U)                                    
+#define DSI_IER0_PE4IE_Msk            (0x1UL << DSI_IER0_PE4IE_Pos)             /*!< 0x00100000 */
+#define DSI_IER0_PE4IE                DSI_IER0_PE4IE_Msk                       /*!< PHY Error 4 Interrupt Enable */
+
+/*******************  Bit definition for DSI_IER1 register  ***************/
+#define DSI_IER1_TOHSTXIE_Pos         (0U)                                     
+#define DSI_IER1_TOHSTXIE_Msk         (0x1UL << DSI_IER1_TOHSTXIE_Pos)          /*!< 0x00000001 */
+#define DSI_IER1_TOHSTXIE             DSI_IER1_TOHSTXIE_Msk                    /*!< Timeout High-Speed Transmission Interrupt Enable */
+#define DSI_IER1_TOLPRXIE_Pos         (1U)                                     
+#define DSI_IER1_TOLPRXIE_Msk         (0x1UL << DSI_IER1_TOLPRXIE_Pos)          /*!< 0x00000002 */
+#define DSI_IER1_TOLPRXIE             DSI_IER1_TOLPRXIE_Msk                    /*!< Timeout Low-Power Reception Interrupt Enable */
+#define DSI_IER1_ECCSEIE_Pos          (2U)                                     
+#define DSI_IER1_ECCSEIE_Msk          (0x1UL << DSI_IER1_ECCSEIE_Pos)           /*!< 0x00000004 */
+#define DSI_IER1_ECCSEIE              DSI_IER1_ECCSEIE_Msk                     /*!< ECC Single-bit Error Interrupt Enable */
+#define DSI_IER1_ECCMEIE_Pos          (3U)                                     
+#define DSI_IER1_ECCMEIE_Msk          (0x1UL << DSI_IER1_ECCMEIE_Pos)           /*!< 0x00000008 */
+#define DSI_IER1_ECCMEIE              DSI_IER1_ECCMEIE_Msk                     /*!< ECC Multi-bit Error Interrupt Enable */
+#define DSI_IER1_CRCEIE_Pos           (4U)                                     
+#define DSI_IER1_CRCEIE_Msk           (0x1UL << DSI_IER1_CRCEIE_Pos)            /*!< 0x00000010 */
+#define DSI_IER1_CRCEIE               DSI_IER1_CRCEIE_Msk                      /*!< CRC Error Interrupt Enable */
+#define DSI_IER1_PSEIE_Pos            (5U)                                     
+#define DSI_IER1_PSEIE_Msk            (0x1UL << DSI_IER1_PSEIE_Pos)             /*!< 0x00000020 */
+#define DSI_IER1_PSEIE                DSI_IER1_PSEIE_Msk                       /*!< Packet Size Error Interrupt Enable */
+#define DSI_IER1_EOTPEIE_Pos          (6U)                                     
+#define DSI_IER1_EOTPEIE_Msk          (0x1UL << DSI_IER1_EOTPEIE_Pos)           /*!< 0x00000040 */
+#define DSI_IER1_EOTPEIE              DSI_IER1_EOTPEIE_Msk                     /*!< EoTp Error Interrupt Enable */
+#define DSI_IER1_LPWREIE_Pos          (7U)                                     
+#define DSI_IER1_LPWREIE_Msk          (0x1UL << DSI_IER1_LPWREIE_Pos)           /*!< 0x00000080 */
+#define DSI_IER1_LPWREIE              DSI_IER1_LPWREIE_Msk                     /*!< LTDC Payload Write Error Interrupt Enable */
+#define DSI_IER1_GCWREIE_Pos          (8U)                                     
+#define DSI_IER1_GCWREIE_Msk          (0x1UL << DSI_IER1_GCWREIE_Pos)           /*!< 0x00000100 */
+#define DSI_IER1_GCWREIE              DSI_IER1_GCWREIE_Msk                     /*!< Generic Command Write Error Interrupt Enable */
+#define DSI_IER1_GPWREIE_Pos          (9U)                                     
+#define DSI_IER1_GPWREIE_Msk          (0x1UL << DSI_IER1_GPWREIE_Pos)           /*!< 0x00000200 */
+#define DSI_IER1_GPWREIE              DSI_IER1_GPWREIE_Msk                     /*!< Generic Payload Write Error Interrupt Enable */
+#define DSI_IER1_GPTXEIE_Pos          (10U)                                    
+#define DSI_IER1_GPTXEIE_Msk          (0x1UL << DSI_IER1_GPTXEIE_Pos)           /*!< 0x00000400 */
+#define DSI_IER1_GPTXEIE              DSI_IER1_GPTXEIE_Msk                     /*!< Generic Payload Transmit Error Interrupt Enable */
+#define DSI_IER1_GPRDEIE_Pos          (11U)                                    
+#define DSI_IER1_GPRDEIE_Msk          (0x1UL << DSI_IER1_GPRDEIE_Pos)           /*!< 0x00000800 */
+#define DSI_IER1_GPRDEIE              DSI_IER1_GPRDEIE_Msk                     /*!< Generic Payload Read Error Interrupt Enable */
+#define DSI_IER1_GPRXEIE_Pos          (12U)                                    
+#define DSI_IER1_GPRXEIE_Msk          (0x1UL << DSI_IER1_GPRXEIE_Pos)           /*!< 0x00001000 */
+#define DSI_IER1_GPRXEIE              DSI_IER1_GPRXEIE_Msk                     /*!< Generic Payload Receive Error Interrupt Enable */
+
+/*******************  Bit definition for DSI_FIR0 register  ***************/
+#define DSI_FIR0_FAE0_Pos             (0U)                                     
+#define DSI_FIR0_FAE0_Msk             (0x1UL << DSI_FIR0_FAE0_Pos)              /*!< 0x00000001 */
+#define DSI_FIR0_FAE0                 DSI_FIR0_FAE0_Msk                        /*!< Force Acknowledge Error 0 */
+#define DSI_FIR0_FAE1_Pos             (1U)                                     
+#define DSI_FIR0_FAE1_Msk             (0x1UL << DSI_FIR0_FAE1_Pos)              /*!< 0x00000002 */
+#define DSI_FIR0_FAE1                 DSI_FIR0_FAE1_Msk                        /*!< Force Acknowledge Error 1 */
+#define DSI_FIR0_FAE2_Pos             (2U)                                     
+#define DSI_FIR0_FAE2_Msk             (0x1UL << DSI_FIR0_FAE2_Pos)              /*!< 0x00000004 */
+#define DSI_FIR0_FAE2                 DSI_FIR0_FAE2_Msk                        /*!< Force Acknowledge Error 2 */
+#define DSI_FIR0_FAE3_Pos             (3U)                                     
+#define DSI_FIR0_FAE3_Msk             (0x1UL << DSI_FIR0_FAE3_Pos)              /*!< 0x00000008 */
+#define DSI_FIR0_FAE3                 DSI_FIR0_FAE3_Msk                        /*!< Force Acknowledge Error 3 */
+#define DSI_FIR0_FAE4_Pos             (4U)                                     
+#define DSI_FIR0_FAE4_Msk             (0x1UL << DSI_FIR0_FAE4_Pos)              /*!< 0x00000010 */
+#define DSI_FIR0_FAE4                 DSI_FIR0_FAE4_Msk                        /*!< Force Acknowledge Error 4 */
+#define DSI_FIR0_FAE5_Pos             (5U)                                     
+#define DSI_FIR0_FAE5_Msk             (0x1UL << DSI_FIR0_FAE5_Pos)              /*!< 0x00000020 */
+#define DSI_FIR0_FAE5                 DSI_FIR0_FAE5_Msk                        /*!< Force Acknowledge Error 5 */
+#define DSI_FIR0_FAE6_Pos             (6U)                                     
+#define DSI_FIR0_FAE6_Msk             (0x1UL << DSI_FIR0_FAE6_Pos)              /*!< 0x00000040 */
+#define DSI_FIR0_FAE6                 DSI_FIR0_FAE6_Msk                        /*!< Force Acknowledge Error 6 */
+#define DSI_FIR0_FAE7_Pos             (7U)                                     
+#define DSI_FIR0_FAE7_Msk             (0x1UL << DSI_FIR0_FAE7_Pos)              /*!< 0x00000080 */
+#define DSI_FIR0_FAE7                 DSI_FIR0_FAE7_Msk                        /*!< Force Acknowledge Error 7 */
+#define DSI_FIR0_FAE8_Pos             (8U)                                     
+#define DSI_FIR0_FAE8_Msk             (0x1UL << DSI_FIR0_FAE8_Pos)              /*!< 0x00000100 */
+#define DSI_FIR0_FAE8                 DSI_FIR0_FAE8_Msk                        /*!< Force Acknowledge Error 8 */
+#define DSI_FIR0_FAE9_Pos             (9U)                                     
+#define DSI_FIR0_FAE9_Msk             (0x1UL << DSI_FIR0_FAE9_Pos)              /*!< 0x00000200 */
+#define DSI_FIR0_FAE9                 DSI_FIR0_FAE9_Msk                        /*!< Force Acknowledge Error 9 */
+#define DSI_FIR0_FAE10_Pos            (10U)                                    
+#define DSI_FIR0_FAE10_Msk            (0x1UL << DSI_FIR0_FAE10_Pos)             /*!< 0x00000400 */
+#define DSI_FIR0_FAE10                DSI_FIR0_FAE10_Msk                       /*!< Force Acknowledge Error 10 */
+#define DSI_FIR0_FAE11_Pos            (11U)                                    
+#define DSI_FIR0_FAE11_Msk            (0x1UL << DSI_FIR0_FAE11_Pos)             /*!< 0x00000800 */
+#define DSI_FIR0_FAE11                DSI_FIR0_FAE11_Msk                       /*!< Force Acknowledge Error 11 */
+#define DSI_FIR0_FAE12_Pos            (12U)                                    
+#define DSI_FIR0_FAE12_Msk            (0x1UL << DSI_FIR0_FAE12_Pos)             /*!< 0x00001000 */
+#define DSI_FIR0_FAE12                DSI_FIR0_FAE12_Msk                       /*!< Force Acknowledge Error 12 */
+#define DSI_FIR0_FAE13_Pos            (13U)                                    
+#define DSI_FIR0_FAE13_Msk            (0x1UL << DSI_FIR0_FAE13_Pos)             /*!< 0x00002000 */
+#define DSI_FIR0_FAE13                DSI_FIR0_FAE13_Msk                       /*!< Force Acknowledge Error 13 */
+#define DSI_FIR0_FAE14_Pos            (14U)                                    
+#define DSI_FIR0_FAE14_Msk            (0x1UL << DSI_FIR0_FAE14_Pos)             /*!< 0x00004000 */
+#define DSI_FIR0_FAE14                DSI_FIR0_FAE14_Msk                       /*!< Force Acknowledge Error 14 */
+#define DSI_FIR0_FAE15_Pos            (15U)                                    
+#define DSI_FIR0_FAE15_Msk            (0x1UL << DSI_FIR0_FAE15_Pos)             /*!< 0x00008000 */
+#define DSI_FIR0_FAE15                DSI_FIR0_FAE15_Msk                       /*!< Force Acknowledge Error 15 */
+#define DSI_FIR0_FPE0_Pos             (16U)                                    
+#define DSI_FIR0_FPE0_Msk             (0x1UL << DSI_FIR0_FPE0_Pos)              /*!< 0x00010000 */
+#define DSI_FIR0_FPE0                 DSI_FIR0_FPE0_Msk                        /*!< Force PHY Error 0 */
+#define DSI_FIR0_FPE1_Pos             (17U)                                    
+#define DSI_FIR0_FPE1_Msk             (0x1UL << DSI_FIR0_FPE1_Pos)              /*!< 0x00020000 */
+#define DSI_FIR0_FPE1                 DSI_FIR0_FPE1_Msk                        /*!< Force PHY Error 1 */
+#define DSI_FIR0_FPE2_Pos             (18U)                                    
+#define DSI_FIR0_FPE2_Msk             (0x1UL << DSI_FIR0_FPE2_Pos)              /*!< 0x00040000 */
+#define DSI_FIR0_FPE2                 DSI_FIR0_FPE2_Msk                        /*!< Force PHY Error 2 */
+#define DSI_FIR0_FPE3_Pos             (19U)                                    
+#define DSI_FIR0_FPE3_Msk             (0x1UL << DSI_FIR0_FPE3_Pos)              /*!< 0x00080000 */
+#define DSI_FIR0_FPE3                 DSI_FIR0_FPE3_Msk                        /*!< Force PHY Error 3 */
+#define DSI_FIR0_FPE4_Pos             (20U)                                    
+#define DSI_FIR0_FPE4_Msk             (0x1UL << DSI_FIR0_FPE4_Pos)              /*!< 0x00100000 */
+#define DSI_FIR0_FPE4                 DSI_FIR0_FPE4_Msk                        /*!< Force PHY Error 4 */
+
+/*******************  Bit definition for DSI_FIR1 register  ***************/
+#define DSI_FIR1_FTOHSTX_Pos          (0U)                                     
+#define DSI_FIR1_FTOHSTX_Msk          (0x1UL << DSI_FIR1_FTOHSTX_Pos)           /*!< 0x00000001 */
+#define DSI_FIR1_FTOHSTX              DSI_FIR1_FTOHSTX_Msk                     /*!< Force Timeout High-Speed Transmission */
+#define DSI_FIR1_FTOLPRX_Pos          (1U)                                     
+#define DSI_FIR1_FTOLPRX_Msk          (0x1UL << DSI_FIR1_FTOLPRX_Pos)           /*!< 0x00000002 */
+#define DSI_FIR1_FTOLPRX              DSI_FIR1_FTOLPRX_Msk                     /*!< Force Timeout Low-Power Reception */
+#define DSI_FIR1_FECCSE_Pos           (2U)                                     
+#define DSI_FIR1_FECCSE_Msk           (0x1UL << DSI_FIR1_FECCSE_Pos)            /*!< 0x00000004 */
+#define DSI_FIR1_FECCSE               DSI_FIR1_FECCSE_Msk                      /*!< Force ECC Single-bit Error */
+#define DSI_FIR1_FECCME_Pos           (3U)                                     
+#define DSI_FIR1_FECCME_Msk           (0x1UL << DSI_FIR1_FECCME_Pos)            /*!< 0x00000008 */
+#define DSI_FIR1_FECCME               DSI_FIR1_FECCME_Msk                      /*!< Force ECC Multi-bit Error */
+#define DSI_FIR1_FCRCE_Pos            (4U)                                     
+#define DSI_FIR1_FCRCE_Msk            (0x1UL << DSI_FIR1_FCRCE_Pos)             /*!< 0x00000010 */
+#define DSI_FIR1_FCRCE                DSI_FIR1_FCRCE_Msk                       /*!< Force CRC Error */
+#define DSI_FIR1_FPSE_Pos             (5U)                                     
+#define DSI_FIR1_FPSE_Msk             (0x1UL << DSI_FIR1_FPSE_Pos)              /*!< 0x00000020 */
+#define DSI_FIR1_FPSE                 DSI_FIR1_FPSE_Msk                        /*!< Force Packet Size Error */
+#define DSI_FIR1_FEOTPE_Pos           (6U)                                     
+#define DSI_FIR1_FEOTPE_Msk           (0x1UL << DSI_FIR1_FEOTPE_Pos)            /*!< 0x00000040 */
+#define DSI_FIR1_FEOTPE               DSI_FIR1_FEOTPE_Msk                      /*!< Force EoTp Error */
+#define DSI_FIR1_FLPWRE_Pos           (7U)                                     
+#define DSI_FIR1_FLPWRE_Msk           (0x1UL << DSI_FIR1_FLPWRE_Pos)            /*!< 0x00000080 */
+#define DSI_FIR1_FLPWRE               DSI_FIR1_FLPWRE_Msk                      /*!< Force LTDC Payload Write Error */
+#define DSI_FIR1_FGCWRE_Pos           (8U)                                     
+#define DSI_FIR1_FGCWRE_Msk           (0x1UL << DSI_FIR1_FGCWRE_Pos)            /*!< 0x00000100 */
+#define DSI_FIR1_FGCWRE               DSI_FIR1_FGCWRE_Msk                      /*!< Force Generic Command Write Error */
+#define DSI_FIR1_FGPWRE_Pos           (9U)                                     
+#define DSI_FIR1_FGPWRE_Msk           (0x1UL << DSI_FIR1_FGPWRE_Pos)            /*!< 0x00000200 */
+#define DSI_FIR1_FGPWRE               DSI_FIR1_FGPWRE_Msk                      /*!< Force Generic Payload Write Error */
+#define DSI_FIR1_FGPTXE_Pos           (10U)                                    
+#define DSI_FIR1_FGPTXE_Msk           (0x1UL << DSI_FIR1_FGPTXE_Pos)            /*!< 0x00000400 */
+#define DSI_FIR1_FGPTXE               DSI_FIR1_FGPTXE_Msk                      /*!< Force Generic Payload Transmit Error */
+#define DSI_FIR1_FGPRDE_Pos           (11U)                                    
+#define DSI_FIR1_FGPRDE_Msk           (0x1UL << DSI_FIR1_FGPRDE_Pos)            /*!< 0x00000800 */
+#define DSI_FIR1_FGPRDE               DSI_FIR1_FGPRDE_Msk                      /*!< Force Generic Payload Read Error */
+#define DSI_FIR1_FGPRXE_Pos           (12U)                                    
+#define DSI_FIR1_FGPRXE_Msk           (0x1UL << DSI_FIR1_FGPRXE_Pos)            /*!< 0x00001000 */
+#define DSI_FIR1_FGPRXE               DSI_FIR1_FGPRXE_Msk                      /*!< Force Generic Payload Receive Error */
+
+/*******************  Bit definition for DSI_VSCR register  ***************/
+#define DSI_VSCR_EN_Pos               (0U)                                     
+#define DSI_VSCR_EN_Msk               (0x1UL << DSI_VSCR_EN_Pos)                /*!< 0x00000001 */
+#define DSI_VSCR_EN                   DSI_VSCR_EN_Msk                          /*!< Enable */
+#define DSI_VSCR_UR_Pos               (8U)                                     
+#define DSI_VSCR_UR_Msk               (0x1UL << DSI_VSCR_UR_Pos)                /*!< 0x00000100 */
+#define DSI_VSCR_UR                   DSI_VSCR_UR_Msk                          /*!< Update Register */
+
+/*******************  Bit definition for DSI_LCVCIDR register  ************/
+#define DSI_LCVCIDR_VCID_Pos          (0U)                                     
+#define DSI_LCVCIDR_VCID_Msk          (0x3UL << DSI_LCVCIDR_VCID_Pos)           /*!< 0x00000003 */
+#define DSI_LCVCIDR_VCID              DSI_LCVCIDR_VCID_Msk                     /*!< Virtual Channel ID */
+#define DSI_LCVCIDR_VCID0_Pos         (0U)                                     
+#define DSI_LCVCIDR_VCID0_Msk         (0x1UL << DSI_LCVCIDR_VCID0_Pos)          /*!< 0x00000001 */
+#define DSI_LCVCIDR_VCID0             DSI_LCVCIDR_VCID0_Msk                    
+#define DSI_LCVCIDR_VCID1_Pos         (1U)                                     
+#define DSI_LCVCIDR_VCID1_Msk         (0x1UL << DSI_LCVCIDR_VCID1_Pos)          /*!< 0x00000002 */
+#define DSI_LCVCIDR_VCID1             DSI_LCVCIDR_VCID1_Msk                    
+
+/*******************  Bit definition for DSI_LCCCR register  **************/
+#define DSI_LCCCR_COLC_Pos            (0U)                                     
+#define DSI_LCCCR_COLC_Msk            (0xFUL << DSI_LCCCR_COLC_Pos)             /*!< 0x0000000F */
+#define DSI_LCCCR_COLC                DSI_LCCCR_COLC_Msk                       /*!< Color Coding */
+#define DSI_LCCCR_COLC0_Pos           (0U)                                     
+#define DSI_LCCCR_COLC0_Msk           (0x1UL << DSI_LCCCR_COLC0_Pos)            /*!< 0x00000001 */
+#define DSI_LCCCR_COLC0               DSI_LCCCR_COLC0_Msk                      
+#define DSI_LCCCR_COLC1_Pos           (1U)                                     
+#define DSI_LCCCR_COLC1_Msk           (0x1UL << DSI_LCCCR_COLC1_Pos)            /*!< 0x00000002 */
+#define DSI_LCCCR_COLC1               DSI_LCCCR_COLC1_Msk                      
+#define DSI_LCCCR_COLC2_Pos           (2U)                                     
+#define DSI_LCCCR_COLC2_Msk           (0x1UL << DSI_LCCCR_COLC2_Pos)            /*!< 0x00000004 */
+#define DSI_LCCCR_COLC2               DSI_LCCCR_COLC2_Msk                      
+#define DSI_LCCCR_COLC3_Pos           (3U)                                     
+#define DSI_LCCCR_COLC3_Msk           (0x1UL << DSI_LCCCR_COLC3_Pos)            /*!< 0x00000008 */
+#define DSI_LCCCR_COLC3               DSI_LCCCR_COLC3_Msk                      
+
+#define DSI_LCCCR_LPE_Pos             (8U)                                     
+#define DSI_LCCCR_LPE_Msk             (0x1UL << DSI_LCCCR_LPE_Pos)              /*!< 0x00000100 */
+#define DSI_LCCCR_LPE                 DSI_LCCCR_LPE_Msk                        /*!< Loosely Packed Enable */
+
+/*******************  Bit definition for DSI_LPMCCR register  *************/
+#define DSI_LPMCCR_VLPSIZE_Pos        (0U)                                     
+#define DSI_LPMCCR_VLPSIZE_Msk        (0xFFUL << DSI_LPMCCR_VLPSIZE_Pos)        /*!< 0x000000FF */
+#define DSI_LPMCCR_VLPSIZE            DSI_LPMCCR_VLPSIZE_Msk                   /*!< VACT Largest Packet Size */
+#define DSI_LPMCCR_VLPSIZE0_Pos       (0U)                                     
+#define DSI_LPMCCR_VLPSIZE0_Msk       (0x1UL << DSI_LPMCCR_VLPSIZE0_Pos)        /*!< 0x00000001 */
+#define DSI_LPMCCR_VLPSIZE0           DSI_LPMCCR_VLPSIZE0_Msk                  
+#define DSI_LPMCCR_VLPSIZE1_Pos       (1U)                                     
+#define DSI_LPMCCR_VLPSIZE1_Msk       (0x1UL << DSI_LPMCCR_VLPSIZE1_Pos)        /*!< 0x00000002 */
+#define DSI_LPMCCR_VLPSIZE1           DSI_LPMCCR_VLPSIZE1_Msk                  
+#define DSI_LPMCCR_VLPSIZE2_Pos       (2U)                                     
+#define DSI_LPMCCR_VLPSIZE2_Msk       (0x1UL << DSI_LPMCCR_VLPSIZE2_Pos)        /*!< 0x00000004 */
+#define DSI_LPMCCR_VLPSIZE2           DSI_LPMCCR_VLPSIZE2_Msk                  
+#define DSI_LPMCCR_VLPSIZE3_Pos       (3U)                                     
+#define DSI_LPMCCR_VLPSIZE3_Msk       (0x1UL << DSI_LPMCCR_VLPSIZE3_Pos)        /*!< 0x00000008 */
+#define DSI_LPMCCR_VLPSIZE3           DSI_LPMCCR_VLPSIZE3_Msk                  
+#define DSI_LPMCCR_VLPSIZE4_Pos       (4U)                                     
+#define DSI_LPMCCR_VLPSIZE4_Msk       (0x1UL << DSI_LPMCCR_VLPSIZE4_Pos)        /*!< 0x00000010 */
+#define DSI_LPMCCR_VLPSIZE4           DSI_LPMCCR_VLPSIZE4_Msk                  
+#define DSI_LPMCCR_VLPSIZE5_Pos       (5U)                                     
+#define DSI_LPMCCR_VLPSIZE5_Msk       (0x1UL << DSI_LPMCCR_VLPSIZE5_Pos)        /*!< 0x00000020 */
+#define DSI_LPMCCR_VLPSIZE5           DSI_LPMCCR_VLPSIZE5_Msk                  
+#define DSI_LPMCCR_VLPSIZE6_Pos       (6U)                                     
+#define DSI_LPMCCR_VLPSIZE6_Msk       (0x1UL << DSI_LPMCCR_VLPSIZE6_Pos)        /*!< 0x00000040 */
+#define DSI_LPMCCR_VLPSIZE6           DSI_LPMCCR_VLPSIZE6_Msk                  
+#define DSI_LPMCCR_VLPSIZE7_Pos       (7U)                                     
+#define DSI_LPMCCR_VLPSIZE7_Msk       (0x1UL << DSI_LPMCCR_VLPSIZE7_Pos)        /*!< 0x00000080 */
+#define DSI_LPMCCR_VLPSIZE7           DSI_LPMCCR_VLPSIZE7_Msk                  
+
+#define DSI_LPMCCR_LPSIZE_Pos         (16U)                                    
+#define DSI_LPMCCR_LPSIZE_Msk         (0xFFUL << DSI_LPMCCR_LPSIZE_Pos)         /*!< 0x00FF0000 */
+#define DSI_LPMCCR_LPSIZE             DSI_LPMCCR_LPSIZE_Msk                    /*!< Largest Packet Size */
+#define DSI_LPMCCR_LPSIZE0_Pos        (16U)                                    
+#define DSI_LPMCCR_LPSIZE0_Msk        (0x1UL << DSI_LPMCCR_LPSIZE0_Pos)         /*!< 0x00010000 */
+#define DSI_LPMCCR_LPSIZE0            DSI_LPMCCR_LPSIZE0_Msk                   
+#define DSI_LPMCCR_LPSIZE1_Pos        (17U)                                    
+#define DSI_LPMCCR_LPSIZE1_Msk        (0x1UL << DSI_LPMCCR_LPSIZE1_Pos)         /*!< 0x00020000 */
+#define DSI_LPMCCR_LPSIZE1            DSI_LPMCCR_LPSIZE1_Msk                   
+#define DSI_LPMCCR_LPSIZE2_Pos        (18U)                                    
+#define DSI_LPMCCR_LPSIZE2_Msk        (0x1UL << DSI_LPMCCR_LPSIZE2_Pos)         /*!< 0x00040000 */
+#define DSI_LPMCCR_LPSIZE2            DSI_LPMCCR_LPSIZE2_Msk                   
+#define DSI_LPMCCR_LPSIZE3_Pos        (19U)                                    
+#define DSI_LPMCCR_LPSIZE3_Msk        (0x1UL << DSI_LPMCCR_LPSIZE3_Pos)         /*!< 0x00080000 */
+#define DSI_LPMCCR_LPSIZE3            DSI_LPMCCR_LPSIZE3_Msk                   
+#define DSI_LPMCCR_LPSIZE4_Pos        (20U)                                    
+#define DSI_LPMCCR_LPSIZE4_Msk        (0x1UL << DSI_LPMCCR_LPSIZE4_Pos)         /*!< 0x00100000 */
+#define DSI_LPMCCR_LPSIZE4            DSI_LPMCCR_LPSIZE4_Msk                   
+#define DSI_LPMCCR_LPSIZE5_Pos        (21U)                                    
+#define DSI_LPMCCR_LPSIZE5_Msk        (0x1UL << DSI_LPMCCR_LPSIZE5_Pos)         /*!< 0x00200000 */
+#define DSI_LPMCCR_LPSIZE5            DSI_LPMCCR_LPSIZE5_Msk                   
+#define DSI_LPMCCR_LPSIZE6_Pos        (22U)                                    
+#define DSI_LPMCCR_LPSIZE6_Msk        (0x1UL << DSI_LPMCCR_LPSIZE6_Pos)         /*!< 0x00400000 */
+#define DSI_LPMCCR_LPSIZE6            DSI_LPMCCR_LPSIZE6_Msk                   
+#define DSI_LPMCCR_LPSIZE7_Pos        (23U)                                    
+#define DSI_LPMCCR_LPSIZE7_Msk        (0x1UL << DSI_LPMCCR_LPSIZE7_Pos)         /*!< 0x00800000 */
+#define DSI_LPMCCR_LPSIZE7            DSI_LPMCCR_LPSIZE7_Msk                   
+
+/*******************  Bit definition for DSI_VMCCR register  **************/
+#define DSI_VMCCR_VMT_Pos             (0U)                                     
+#define DSI_VMCCR_VMT_Msk             (0x3UL << DSI_VMCCR_VMT_Pos)              /*!< 0x00000003 */
+#define DSI_VMCCR_VMT                 DSI_VMCCR_VMT_Msk                        /*!< Video Mode Type */
+#define DSI_VMCCR_VMT0_Pos            (0U)                                     
+#define DSI_VMCCR_VMT0_Msk            (0x1UL << DSI_VMCCR_VMT0_Pos)             /*!< 0x00000001 */
+#define DSI_VMCCR_VMT0                DSI_VMCCR_VMT0_Msk                       
+#define DSI_VMCCR_VMT1_Pos            (1U)                                     
+#define DSI_VMCCR_VMT1_Msk            (0x1UL << DSI_VMCCR_VMT1_Pos)             /*!< 0x00000002 */
+#define DSI_VMCCR_VMT1                DSI_VMCCR_VMT1_Msk                       
+
+#define DSI_VMCCR_LPVSAE_Pos          (8U)                                     
+#define DSI_VMCCR_LPVSAE_Msk          (0x1UL << DSI_VMCCR_LPVSAE_Pos)           /*!< 0x00000100 */
+#define DSI_VMCCR_LPVSAE              DSI_VMCCR_LPVSAE_Msk                     /*!< Low-power Vertical Sync time Enable */
+#define DSI_VMCCR_LPVBPE_Pos          (9U)                                     
+#define DSI_VMCCR_LPVBPE_Msk          (0x1UL << DSI_VMCCR_LPVBPE_Pos)           /*!< 0x00000200 */
+#define DSI_VMCCR_LPVBPE              DSI_VMCCR_LPVBPE_Msk                     /*!< Low-power Vertical Back-porch Enable */
+#define DSI_VMCCR_LPVFPE_Pos          (10U)                                    
+#define DSI_VMCCR_LPVFPE_Msk          (0x1UL << DSI_VMCCR_LPVFPE_Pos)           /*!< 0x00000400 */
+#define DSI_VMCCR_LPVFPE              DSI_VMCCR_LPVFPE_Msk                     /*!< Low-power Vertical Front-porch Enable */
+#define DSI_VMCCR_LPVAE_Pos           (11U)                                    
+#define DSI_VMCCR_LPVAE_Msk           (0x1UL << DSI_VMCCR_LPVAE_Pos)            /*!< 0x00000800 */
+#define DSI_VMCCR_LPVAE               DSI_VMCCR_LPVAE_Msk                      /*!< Low-power Vertical Active Enable */
+#define DSI_VMCCR_LPHBPE_Pos          (12U)                                    
+#define DSI_VMCCR_LPHBPE_Msk          (0x1UL << DSI_VMCCR_LPHBPE_Pos)           /*!< 0x00001000 */
+#define DSI_VMCCR_LPHBPE              DSI_VMCCR_LPHBPE_Msk                     /*!< Low-power Horizontal Back-porch Enable */
+#define DSI_VMCCR_LPHFE_Pos           (13U)                                    
+#define DSI_VMCCR_LPHFE_Msk           (0x1UL << DSI_VMCCR_LPHFE_Pos)            /*!< 0x00002000 */
+#define DSI_VMCCR_LPHFE               DSI_VMCCR_LPHFE_Msk                      /*!< Low-power Horizontal Front-porch Enable */
+#define DSI_VMCCR_FBTAAE_Pos          (14U)                                    
+#define DSI_VMCCR_FBTAAE_Msk          (0x1UL << DSI_VMCCR_FBTAAE_Pos)           /*!< 0x00004000 */
+#define DSI_VMCCR_FBTAAE              DSI_VMCCR_FBTAAE_Msk                     /*!< Frame BTA Acknowledge Enable */
+#define DSI_VMCCR_LPCE_Pos            (15U)                                    
+#define DSI_VMCCR_LPCE_Msk            (0x1UL << DSI_VMCCR_LPCE_Pos)             /*!< 0x00008000 */
+#define DSI_VMCCR_LPCE                DSI_VMCCR_LPCE_Msk                       /*!< Low-power Command Enable */
+
+/*******************  Bit definition for DSI_VPCCR register  **************/
+#define DSI_VPCCR_VPSIZE_Pos          (0U)                                     
+#define DSI_VPCCR_VPSIZE_Msk          (0x3FFFUL << DSI_VPCCR_VPSIZE_Pos)        /*!< 0x00003FFF */
+#define DSI_VPCCR_VPSIZE              DSI_VPCCR_VPSIZE_Msk                     /*!< Video Packet Size */
+#define DSI_VPCCR_VPSIZE0_Pos         (0U)                                     
+#define DSI_VPCCR_VPSIZE0_Msk         (0x1UL << DSI_VPCCR_VPSIZE0_Pos)          /*!< 0x00000001 */
+#define DSI_VPCCR_VPSIZE0             DSI_VPCCR_VPSIZE0_Msk                    
+#define DSI_VPCCR_VPSIZE1_Pos         (1U)                                     
+#define DSI_VPCCR_VPSIZE1_Msk         (0x1UL << DSI_VPCCR_VPSIZE1_Pos)          /*!< 0x00000002 */
+#define DSI_VPCCR_VPSIZE1             DSI_VPCCR_VPSIZE1_Msk                    
+#define DSI_VPCCR_VPSIZE2_Pos         (2U)                                     
+#define DSI_VPCCR_VPSIZE2_Msk         (0x1UL << DSI_VPCCR_VPSIZE2_Pos)          /*!< 0x00000004 */
+#define DSI_VPCCR_VPSIZE2             DSI_VPCCR_VPSIZE2_Msk                    
+#define DSI_VPCCR_VPSIZE3_Pos         (3U)                                     
+#define DSI_VPCCR_VPSIZE3_Msk         (0x1UL << DSI_VPCCR_VPSIZE3_Pos)          /*!< 0x00000008 */
+#define DSI_VPCCR_VPSIZE3             DSI_VPCCR_VPSIZE3_Msk                    
+#define DSI_VPCCR_VPSIZE4_Pos         (4U)                                     
+#define DSI_VPCCR_VPSIZE4_Msk         (0x1UL << DSI_VPCCR_VPSIZE4_Pos)          /*!< 0x00000010 */
+#define DSI_VPCCR_VPSIZE4             DSI_VPCCR_VPSIZE4_Msk                    
+#define DSI_VPCCR_VPSIZE5_Pos         (5U)                                     
+#define DSI_VPCCR_VPSIZE5_Msk         (0x1UL << DSI_VPCCR_VPSIZE5_Pos)          /*!< 0x00000020 */
+#define DSI_VPCCR_VPSIZE5             DSI_VPCCR_VPSIZE5_Msk                    
+#define DSI_VPCCR_VPSIZE6_Pos         (6U)                                     
+#define DSI_VPCCR_VPSIZE6_Msk         (0x1UL << DSI_VPCCR_VPSIZE6_Pos)          /*!< 0x00000040 */
+#define DSI_VPCCR_VPSIZE6             DSI_VPCCR_VPSIZE6_Msk                    
+#define DSI_VPCCR_VPSIZE7_Pos         (7U)                                     
+#define DSI_VPCCR_VPSIZE7_Msk         (0x1UL << DSI_VPCCR_VPSIZE7_Pos)          /*!< 0x00000080 */
+#define DSI_VPCCR_VPSIZE7             DSI_VPCCR_VPSIZE7_Msk                    
+#define DSI_VPCCR_VPSIZE8_Pos         (8U)                                     
+#define DSI_VPCCR_VPSIZE8_Msk         (0x1UL << DSI_VPCCR_VPSIZE8_Pos)          /*!< 0x00000100 */
+#define DSI_VPCCR_VPSIZE8             DSI_VPCCR_VPSIZE8_Msk                    
+#define DSI_VPCCR_VPSIZE9_Pos         (9U)                                     
+#define DSI_VPCCR_VPSIZE9_Msk         (0x1UL << DSI_VPCCR_VPSIZE9_Pos)          /*!< 0x00000200 */
+#define DSI_VPCCR_VPSIZE9             DSI_VPCCR_VPSIZE9_Msk                    
+#define DSI_VPCCR_VPSIZE10_Pos        (10U)                                    
+#define DSI_VPCCR_VPSIZE10_Msk        (0x1UL << DSI_VPCCR_VPSIZE10_Pos)         /*!< 0x00000400 */
+#define DSI_VPCCR_VPSIZE10            DSI_VPCCR_VPSIZE10_Msk                   
+#define DSI_VPCCR_VPSIZE11_Pos        (11U)                                    
+#define DSI_VPCCR_VPSIZE11_Msk        (0x1UL << DSI_VPCCR_VPSIZE11_Pos)         /*!< 0x00000800 */
+#define DSI_VPCCR_VPSIZE11            DSI_VPCCR_VPSIZE11_Msk                   
+#define DSI_VPCCR_VPSIZE12_Pos        (12U)                                    
+#define DSI_VPCCR_VPSIZE12_Msk        (0x1UL << DSI_VPCCR_VPSIZE12_Pos)         /*!< 0x00001000 */
+#define DSI_VPCCR_VPSIZE12            DSI_VPCCR_VPSIZE12_Msk                   
+#define DSI_VPCCR_VPSIZE13_Pos        (13U)                                    
+#define DSI_VPCCR_VPSIZE13_Msk        (0x1UL << DSI_VPCCR_VPSIZE13_Pos)         /*!< 0x00002000 */
+#define DSI_VPCCR_VPSIZE13            DSI_VPCCR_VPSIZE13_Msk                   
+
+/*******************  Bit definition for DSI_VCCCR register  **************/
+#define DSI_VCCCR_NUMC_Pos            (0U)                                     
+#define DSI_VCCCR_NUMC_Msk            (0x1FFFUL << DSI_VCCCR_NUMC_Pos)          /*!< 0x00001FFF */
+#define DSI_VCCCR_NUMC                DSI_VCCCR_NUMC_Msk                       /*!< Number of Chunks */
+#define DSI_VCCCR_NUMC0_Pos           (0U)                                     
+#define DSI_VCCCR_NUMC0_Msk           (0x1UL << DSI_VCCCR_NUMC0_Pos)            /*!< 0x00000001 */
+#define DSI_VCCCR_NUMC0               DSI_VCCCR_NUMC0_Msk                      
+#define DSI_VCCCR_NUMC1_Pos           (1U)                                     
+#define DSI_VCCCR_NUMC1_Msk           (0x1UL << DSI_VCCCR_NUMC1_Pos)            /*!< 0x00000002 */
+#define DSI_VCCCR_NUMC1               DSI_VCCCR_NUMC1_Msk                      
+#define DSI_VCCCR_NUMC2_Pos           (2U)                                     
+#define DSI_VCCCR_NUMC2_Msk           (0x1UL << DSI_VCCCR_NUMC2_Pos)            /*!< 0x00000004 */
+#define DSI_VCCCR_NUMC2               DSI_VCCCR_NUMC2_Msk                      
+#define DSI_VCCCR_NUMC3_Pos           (3U)                                     
+#define DSI_VCCCR_NUMC3_Msk           (0x1UL << DSI_VCCCR_NUMC3_Pos)            /*!< 0x00000008 */
+#define DSI_VCCCR_NUMC3               DSI_VCCCR_NUMC3_Msk                      
+#define DSI_VCCCR_NUMC4_Pos           (4U)                                     
+#define DSI_VCCCR_NUMC4_Msk           (0x1UL << DSI_VCCCR_NUMC4_Pos)            /*!< 0x00000010 */
+#define DSI_VCCCR_NUMC4               DSI_VCCCR_NUMC4_Msk                      
+#define DSI_VCCCR_NUMC5_Pos           (5U)                                     
+#define DSI_VCCCR_NUMC5_Msk           (0x1UL << DSI_VCCCR_NUMC5_Pos)            /*!< 0x00000020 */
+#define DSI_VCCCR_NUMC5               DSI_VCCCR_NUMC5_Msk                      
+#define DSI_VCCCR_NUMC6_Pos           (6U)                                     
+#define DSI_VCCCR_NUMC6_Msk           (0x1UL << DSI_VCCCR_NUMC6_Pos)            /*!< 0x00000040 */
+#define DSI_VCCCR_NUMC6               DSI_VCCCR_NUMC6_Msk                      
+#define DSI_VCCCR_NUMC7_Pos           (7U)                                     
+#define DSI_VCCCR_NUMC7_Msk           (0x1UL << DSI_VCCCR_NUMC7_Pos)            /*!< 0x00000080 */
+#define DSI_VCCCR_NUMC7               DSI_VCCCR_NUMC7_Msk                      
+#define DSI_VCCCR_NUMC8_Pos           (8U)                                     
+#define DSI_VCCCR_NUMC8_Msk           (0x1UL << DSI_VCCCR_NUMC8_Pos)            /*!< 0x00000100 */
+#define DSI_VCCCR_NUMC8               DSI_VCCCR_NUMC8_Msk                      
+#define DSI_VCCCR_NUMC9_Pos           (9U)                                     
+#define DSI_VCCCR_NUMC9_Msk           (0x1UL << DSI_VCCCR_NUMC9_Pos)            /*!< 0x00000200 */
+#define DSI_VCCCR_NUMC9               DSI_VCCCR_NUMC9_Msk                      
+#define DSI_VCCCR_NUMC10_Pos          (10U)                                    
+#define DSI_VCCCR_NUMC10_Msk          (0x1UL << DSI_VCCCR_NUMC10_Pos)           /*!< 0x00000400 */
+#define DSI_VCCCR_NUMC10              DSI_VCCCR_NUMC10_Msk                     
+#define DSI_VCCCR_NUMC11_Pos          (11U)                                    
+#define DSI_VCCCR_NUMC11_Msk          (0x1UL << DSI_VCCCR_NUMC11_Pos)           /*!< 0x00000800 */
+#define DSI_VCCCR_NUMC11              DSI_VCCCR_NUMC11_Msk                     
+#define DSI_VCCCR_NUMC12_Pos          (12U)                                    
+#define DSI_VCCCR_NUMC12_Msk          (0x1UL << DSI_VCCCR_NUMC12_Pos)           /*!< 0x00001000 */
+#define DSI_VCCCR_NUMC12              DSI_VCCCR_NUMC12_Msk                     
+
+/*******************  Bit definition for DSI_VNPCCR register  *************/
+#define DSI_VNPCCR_NPSIZE_Pos         (0U)                                     
+#define DSI_VNPCCR_NPSIZE_Msk         (0x1FFFUL << DSI_VNPCCR_NPSIZE_Pos)       /*!< 0x00001FFF */
+#define DSI_VNPCCR_NPSIZE             DSI_VNPCCR_NPSIZE_Msk                    /*!< Number of Chunks */
+#define DSI_VNPCCR_NPSIZE0_Pos        (0U)                                     
+#define DSI_VNPCCR_NPSIZE0_Msk        (0x1UL << DSI_VNPCCR_NPSIZE0_Pos)         /*!< 0x00000001 */
+#define DSI_VNPCCR_NPSIZE0            DSI_VNPCCR_NPSIZE0_Msk                   
+#define DSI_VNPCCR_NPSIZE1_Pos        (1U)                                     
+#define DSI_VNPCCR_NPSIZE1_Msk        (0x1UL << DSI_VNPCCR_NPSIZE1_Pos)         /*!< 0x00000002 */
+#define DSI_VNPCCR_NPSIZE1            DSI_VNPCCR_NPSIZE1_Msk                   
+#define DSI_VNPCCR_NPSIZE2_Pos        (2U)                                     
+#define DSI_VNPCCR_NPSIZE2_Msk        (0x1UL << DSI_VNPCCR_NPSIZE2_Pos)         /*!< 0x00000004 */
+#define DSI_VNPCCR_NPSIZE2            DSI_VNPCCR_NPSIZE2_Msk                   
+#define DSI_VNPCCR_NPSIZE3_Pos        (3U)                                     
+#define DSI_VNPCCR_NPSIZE3_Msk        (0x1UL << DSI_VNPCCR_NPSIZE3_Pos)         /*!< 0x00000008 */
+#define DSI_VNPCCR_NPSIZE3            DSI_VNPCCR_NPSIZE3_Msk                   
+#define DSI_VNPCCR_NPSIZE4_Pos        (4U)                                     
+#define DSI_VNPCCR_NPSIZE4_Msk        (0x1UL << DSI_VNPCCR_NPSIZE4_Pos)         /*!< 0x00000010 */
+#define DSI_VNPCCR_NPSIZE4            DSI_VNPCCR_NPSIZE4_Msk                   
+#define DSI_VNPCCR_NPSIZE5_Pos        (5U)                                     
+#define DSI_VNPCCR_NPSIZE5_Msk        (0x1UL << DSI_VNPCCR_NPSIZE5_Pos)         /*!< 0x00000020 */
+#define DSI_VNPCCR_NPSIZE5            DSI_VNPCCR_NPSIZE5_Msk                   
+#define DSI_VNPCCR_NPSIZE6_Pos        (6U)                                     
+#define DSI_VNPCCR_NPSIZE6_Msk        (0x1UL << DSI_VNPCCR_NPSIZE6_Pos)         /*!< 0x00000040 */
+#define DSI_VNPCCR_NPSIZE6            DSI_VNPCCR_NPSIZE6_Msk                   
+#define DSI_VNPCCR_NPSIZE7_Pos        (7U)                                     
+#define DSI_VNPCCR_NPSIZE7_Msk        (0x1UL << DSI_VNPCCR_NPSIZE7_Pos)         /*!< 0x00000080 */
+#define DSI_VNPCCR_NPSIZE7            DSI_VNPCCR_NPSIZE7_Msk                   
+#define DSI_VNPCCR_NPSIZE8_Pos        (8U)                                     
+#define DSI_VNPCCR_NPSIZE8_Msk        (0x1UL << DSI_VNPCCR_NPSIZE8_Pos)         /*!< 0x00000100 */
+#define DSI_VNPCCR_NPSIZE8            DSI_VNPCCR_NPSIZE8_Msk                   
+#define DSI_VNPCCR_NPSIZE9_Pos        (9U)                                     
+#define DSI_VNPCCR_NPSIZE9_Msk        (0x1UL << DSI_VNPCCR_NPSIZE9_Pos)         /*!< 0x00000200 */
+#define DSI_VNPCCR_NPSIZE9            DSI_VNPCCR_NPSIZE9_Msk                   
+#define DSI_VNPCCR_NPSIZE10_Pos       (10U)                                    
+#define DSI_VNPCCR_NPSIZE10_Msk       (0x1UL << DSI_VNPCCR_NPSIZE10_Pos)        /*!< 0x00000400 */
+#define DSI_VNPCCR_NPSIZE10           DSI_VNPCCR_NPSIZE10_Msk                  
+#define DSI_VNPCCR_NPSIZE11_Pos       (11U)                                    
+#define DSI_VNPCCR_NPSIZE11_Msk       (0x1UL << DSI_VNPCCR_NPSIZE11_Pos)        /*!< 0x00000800 */
+#define DSI_VNPCCR_NPSIZE11           DSI_VNPCCR_NPSIZE11_Msk                  
+#define DSI_VNPCCR_NPSIZE12_Pos       (12U)                                    
+#define DSI_VNPCCR_NPSIZE12_Msk       (0x1UL << DSI_VNPCCR_NPSIZE12_Pos)        /*!< 0x00001000 */
+#define DSI_VNPCCR_NPSIZE12           DSI_VNPCCR_NPSIZE12_Msk                  
+
+/*******************  Bit definition for DSI_VHSACCR register  ************/
+#define DSI_VHSACCR_HSA_Pos           (0U)                                     
+#define DSI_VHSACCR_HSA_Msk           (0xFFFUL << DSI_VHSACCR_HSA_Pos)          /*!< 0x00000FFF */
+#define DSI_VHSACCR_HSA               DSI_VHSACCR_HSA_Msk                      /*!< Horizontal Synchronism Active duration */
+#define DSI_VHSACCR_HSA0_Pos          (0U)                                     
+#define DSI_VHSACCR_HSA0_Msk          (0x1UL << DSI_VHSACCR_HSA0_Pos)           /*!< 0x00000001 */
+#define DSI_VHSACCR_HSA0              DSI_VHSACCR_HSA0_Msk                     
+#define DSI_VHSACCR_HSA1_Pos          (1U)                                     
+#define DSI_VHSACCR_HSA1_Msk          (0x1UL << DSI_VHSACCR_HSA1_Pos)           /*!< 0x00000002 */
+#define DSI_VHSACCR_HSA1              DSI_VHSACCR_HSA1_Msk                     
+#define DSI_VHSACCR_HSA2_Pos          (2U)                                     
+#define DSI_VHSACCR_HSA2_Msk          (0x1UL << DSI_VHSACCR_HSA2_Pos)           /*!< 0x00000004 */
+#define DSI_VHSACCR_HSA2              DSI_VHSACCR_HSA2_Msk                     
+#define DSI_VHSACCR_HSA3_Pos          (3U)                                     
+#define DSI_VHSACCR_HSA3_Msk          (0x1UL << DSI_VHSACCR_HSA3_Pos)           /*!< 0x00000008 */
+#define DSI_VHSACCR_HSA3              DSI_VHSACCR_HSA3_Msk                     
+#define DSI_VHSACCR_HSA4_Pos          (4U)                                     
+#define DSI_VHSACCR_HSA4_Msk          (0x1UL << DSI_VHSACCR_HSA4_Pos)           /*!< 0x00000010 */
+#define DSI_VHSACCR_HSA4              DSI_VHSACCR_HSA4_Msk                     
+#define DSI_VHSACCR_HSA5_Pos          (5U)                                     
+#define DSI_VHSACCR_HSA5_Msk          (0x1UL << DSI_VHSACCR_HSA5_Pos)           /*!< 0x00000020 */
+#define DSI_VHSACCR_HSA5              DSI_VHSACCR_HSA5_Msk                     
+#define DSI_VHSACCR_HSA6_Pos          (6U)                                     
+#define DSI_VHSACCR_HSA6_Msk          (0x1UL << DSI_VHSACCR_HSA6_Pos)           /*!< 0x00000040 */
+#define DSI_VHSACCR_HSA6              DSI_VHSACCR_HSA6_Msk                     
+#define DSI_VHSACCR_HSA7_Pos          (7U)                                     
+#define DSI_VHSACCR_HSA7_Msk          (0x1UL << DSI_VHSACCR_HSA7_Pos)           /*!< 0x00000080 */
+#define DSI_VHSACCR_HSA7              DSI_VHSACCR_HSA7_Msk                     
+#define DSI_VHSACCR_HSA8_Pos          (8U)                                     
+#define DSI_VHSACCR_HSA8_Msk          (0x1UL << DSI_VHSACCR_HSA8_Pos)           /*!< 0x00000100 */
+#define DSI_VHSACCR_HSA8              DSI_VHSACCR_HSA8_Msk                     
+#define DSI_VHSACCR_HSA9_Pos          (9U)                                     
+#define DSI_VHSACCR_HSA9_Msk          (0x1UL << DSI_VHSACCR_HSA9_Pos)           /*!< 0x00000200 */
+#define DSI_VHSACCR_HSA9              DSI_VHSACCR_HSA9_Msk                     
+#define DSI_VHSACCR_HSA10_Pos         (10U)                                    
+#define DSI_VHSACCR_HSA10_Msk         (0x1UL << DSI_VHSACCR_HSA10_Pos)          /*!< 0x00000400 */
+#define DSI_VHSACCR_HSA10             DSI_VHSACCR_HSA10_Msk                    
+#define DSI_VHSACCR_HSA11_Pos         (11U)                                    
+#define DSI_VHSACCR_HSA11_Msk         (0x1UL << DSI_VHSACCR_HSA11_Pos)          /*!< 0x00000800 */
+#define DSI_VHSACCR_HSA11             DSI_VHSACCR_HSA11_Msk                    
+
+/*******************  Bit definition for DSI_VHBPCCR register  ************/
+#define DSI_VHBPCCR_HBP_Pos           (0U)                                     
+#define DSI_VHBPCCR_HBP_Msk           (0xFFFUL << DSI_VHBPCCR_HBP_Pos)          /*!< 0x00000FFF */
+#define DSI_VHBPCCR_HBP               DSI_VHBPCCR_HBP_Msk                      /*!< Horizontal Back-Porch duration */
+#define DSI_VHBPCCR_HBP0_Pos          (0U)                                     
+#define DSI_VHBPCCR_HBP0_Msk          (0x1UL << DSI_VHBPCCR_HBP0_Pos)           /*!< 0x00000001 */
+#define DSI_VHBPCCR_HBP0              DSI_VHBPCCR_HBP0_Msk                     
+#define DSI_VHBPCCR_HBP1_Pos          (1U)                                     
+#define DSI_VHBPCCR_HBP1_Msk          (0x1UL << DSI_VHBPCCR_HBP1_Pos)           /*!< 0x00000002 */
+#define DSI_VHBPCCR_HBP1              DSI_VHBPCCR_HBP1_Msk                     
+#define DSI_VHBPCCR_HBP2_Pos          (2U)                                     
+#define DSI_VHBPCCR_HBP2_Msk          (0x1UL << DSI_VHBPCCR_HBP2_Pos)           /*!< 0x00000004 */
+#define DSI_VHBPCCR_HBP2              DSI_VHBPCCR_HBP2_Msk                     
+#define DSI_VHBPCCR_HBP3_Pos          (3U)                                     
+#define DSI_VHBPCCR_HBP3_Msk          (0x1UL << DSI_VHBPCCR_HBP3_Pos)           /*!< 0x00000008 */
+#define DSI_VHBPCCR_HBP3              DSI_VHBPCCR_HBP3_Msk                     
+#define DSI_VHBPCCR_HBP4_Pos          (4U)                                     
+#define DSI_VHBPCCR_HBP4_Msk          (0x1UL << DSI_VHBPCCR_HBP4_Pos)           /*!< 0x00000010 */
+#define DSI_VHBPCCR_HBP4              DSI_VHBPCCR_HBP4_Msk                     
+#define DSI_VHBPCCR_HBP5_Pos          (5U)                                     
+#define DSI_VHBPCCR_HBP5_Msk          (0x1UL << DSI_VHBPCCR_HBP5_Pos)           /*!< 0x00000020 */
+#define DSI_VHBPCCR_HBP5              DSI_VHBPCCR_HBP5_Msk                     
+#define DSI_VHBPCCR_HBP6_Pos          (6U)                                     
+#define DSI_VHBPCCR_HBP6_Msk          (0x1UL << DSI_VHBPCCR_HBP6_Pos)           /*!< 0x00000040 */
+#define DSI_VHBPCCR_HBP6              DSI_VHBPCCR_HBP6_Msk                     
+#define DSI_VHBPCCR_HBP7_Pos          (7U)                                     
+#define DSI_VHBPCCR_HBP7_Msk          (0x1UL << DSI_VHBPCCR_HBP7_Pos)           /*!< 0x00000080 */
+#define DSI_VHBPCCR_HBP7              DSI_VHBPCCR_HBP7_Msk                     
+#define DSI_VHBPCCR_HBP8_Pos          (8U)                                     
+#define DSI_VHBPCCR_HBP8_Msk          (0x1UL << DSI_VHBPCCR_HBP8_Pos)           /*!< 0x00000100 */
+#define DSI_VHBPCCR_HBP8              DSI_VHBPCCR_HBP8_Msk                     
+#define DSI_VHBPCCR_HBP9_Pos          (9U)                                     
+#define DSI_VHBPCCR_HBP9_Msk          (0x1UL << DSI_VHBPCCR_HBP9_Pos)           /*!< 0x00000200 */
+#define DSI_VHBPCCR_HBP9              DSI_VHBPCCR_HBP9_Msk                     
+#define DSI_VHBPCCR_HBP10_Pos         (10U)                                    
+#define DSI_VHBPCCR_HBP10_Msk         (0x1UL << DSI_VHBPCCR_HBP10_Pos)          /*!< 0x00000400 */
+#define DSI_VHBPCCR_HBP10             DSI_VHBPCCR_HBP10_Msk                    
+#define DSI_VHBPCCR_HBP11_Pos         (11U)                                    
+#define DSI_VHBPCCR_HBP11_Msk         (0x1UL << DSI_VHBPCCR_HBP11_Pos)          /*!< 0x00000800 */
+#define DSI_VHBPCCR_HBP11             DSI_VHBPCCR_HBP11_Msk                    
+
+/*******************  Bit definition for DSI_VLCCR register  **************/
+#define DSI_VLCCR_HLINE_Pos           (0U)                                     
+#define DSI_VLCCR_HLINE_Msk           (0x7FFFUL << DSI_VLCCR_HLINE_Pos)         /*!< 0x00007FFF */
+#define DSI_VLCCR_HLINE               DSI_VLCCR_HLINE_Msk                      /*!< Horizontal Line duration */
+#define DSI_VLCCR_HLINE0_Pos          (0U)                                     
+#define DSI_VLCCR_HLINE0_Msk          (0x1UL << DSI_VLCCR_HLINE0_Pos)           /*!< 0x00000001 */
+#define DSI_VLCCR_HLINE0              DSI_VLCCR_HLINE0_Msk                     
+#define DSI_VLCCR_HLINE1_Pos          (1U)                                     
+#define DSI_VLCCR_HLINE1_Msk          (0x1UL << DSI_VLCCR_HLINE1_Pos)           /*!< 0x00000002 */
+#define DSI_VLCCR_HLINE1              DSI_VLCCR_HLINE1_Msk                     
+#define DSI_VLCCR_HLINE2_Pos          (2U)                                     
+#define DSI_VLCCR_HLINE2_Msk          (0x1UL << DSI_VLCCR_HLINE2_Pos)           /*!< 0x00000004 */
+#define DSI_VLCCR_HLINE2              DSI_VLCCR_HLINE2_Msk                     
+#define DSI_VLCCR_HLINE3_Pos          (3U)                                     
+#define DSI_VLCCR_HLINE3_Msk          (0x1UL << DSI_VLCCR_HLINE3_Pos)           /*!< 0x00000008 */
+#define DSI_VLCCR_HLINE3              DSI_VLCCR_HLINE3_Msk                     
+#define DSI_VLCCR_HLINE4_Pos          (4U)                                     
+#define DSI_VLCCR_HLINE4_Msk          (0x1UL << DSI_VLCCR_HLINE4_Pos)           /*!< 0x00000010 */
+#define DSI_VLCCR_HLINE4              DSI_VLCCR_HLINE4_Msk                     
+#define DSI_VLCCR_HLINE5_Pos          (5U)                                     
+#define DSI_VLCCR_HLINE5_Msk          (0x1UL << DSI_VLCCR_HLINE5_Pos)           /*!< 0x00000020 */
+#define DSI_VLCCR_HLINE5              DSI_VLCCR_HLINE5_Msk                     
+#define DSI_VLCCR_HLINE6_Pos          (6U)                                     
+#define DSI_VLCCR_HLINE6_Msk          (0x1UL << DSI_VLCCR_HLINE6_Pos)           /*!< 0x00000040 */
+#define DSI_VLCCR_HLINE6              DSI_VLCCR_HLINE6_Msk                     
+#define DSI_VLCCR_HLINE7_Pos          (7U)                                     
+#define DSI_VLCCR_HLINE7_Msk          (0x1UL << DSI_VLCCR_HLINE7_Pos)           /*!< 0x00000080 */
+#define DSI_VLCCR_HLINE7              DSI_VLCCR_HLINE7_Msk                     
+#define DSI_VLCCR_HLINE8_Pos          (8U)                                     
+#define DSI_VLCCR_HLINE8_Msk          (0x1UL << DSI_VLCCR_HLINE8_Pos)           /*!< 0x00000100 */
+#define DSI_VLCCR_HLINE8              DSI_VLCCR_HLINE8_Msk                     
+#define DSI_VLCCR_HLINE9_Pos          (9U)                                     
+#define DSI_VLCCR_HLINE9_Msk          (0x1UL << DSI_VLCCR_HLINE9_Pos)           /*!< 0x00000200 */
+#define DSI_VLCCR_HLINE9              DSI_VLCCR_HLINE9_Msk                     
+#define DSI_VLCCR_HLINE10_Pos         (10U)                                    
+#define DSI_VLCCR_HLINE10_Msk         (0x1UL << DSI_VLCCR_HLINE10_Pos)          /*!< 0x00000400 */
+#define DSI_VLCCR_HLINE10             DSI_VLCCR_HLINE10_Msk                    
+#define DSI_VLCCR_HLINE11_Pos         (11U)                                    
+#define DSI_VLCCR_HLINE11_Msk         (0x1UL << DSI_VLCCR_HLINE11_Pos)          /*!< 0x00000800 */
+#define DSI_VLCCR_HLINE11             DSI_VLCCR_HLINE11_Msk                    
+#define DSI_VLCCR_HLINE12_Pos         (12U)                                    
+#define DSI_VLCCR_HLINE12_Msk         (0x1UL << DSI_VLCCR_HLINE12_Pos)          /*!< 0x00001000 */
+#define DSI_VLCCR_HLINE12             DSI_VLCCR_HLINE12_Msk                    
+#define DSI_VLCCR_HLINE13_Pos         (13U)                                    
+#define DSI_VLCCR_HLINE13_Msk         (0x1UL << DSI_VLCCR_HLINE13_Pos)          /*!< 0x00002000 */
+#define DSI_VLCCR_HLINE13             DSI_VLCCR_HLINE13_Msk                    
+#define DSI_VLCCR_HLINE14_Pos         (14U)                                    
+#define DSI_VLCCR_HLINE14_Msk         (0x1UL << DSI_VLCCR_HLINE14_Pos)          /*!< 0x00004000 */
+#define DSI_VLCCR_HLINE14             DSI_VLCCR_HLINE14_Msk                    
+
+/*******************  Bit definition for DSI_VVSACCR register  ***************/
+#define DSI_VVSACCR_VSA_Pos           (0U)                                     
+#define DSI_VVSACCR_VSA_Msk           (0x3FFUL << DSI_VVSACCR_VSA_Pos)          /*!< 0x000003FF */
+#define DSI_VVSACCR_VSA               DSI_VVSACCR_VSA_Msk                      /*!< Vertical Synchronism Active duration */
+#define DSI_VVSACCR_VSA0_Pos          (0U)                                     
+#define DSI_VVSACCR_VSA0_Msk          (0x1UL << DSI_VVSACCR_VSA0_Pos)           /*!< 0x00000001 */
+#define DSI_VVSACCR_VSA0              DSI_VVSACCR_VSA0_Msk                     
+#define DSI_VVSACCR_VSA1_Pos          (1U)                                     
+#define DSI_VVSACCR_VSA1_Msk          (0x1UL << DSI_VVSACCR_VSA1_Pos)           /*!< 0x00000002 */
+#define DSI_VVSACCR_VSA1              DSI_VVSACCR_VSA1_Msk                     
+#define DSI_VVSACCR_VSA2_Pos          (2U)                                     
+#define DSI_VVSACCR_VSA2_Msk          (0x1UL << DSI_VVSACCR_VSA2_Pos)           /*!< 0x00000004 */
+#define DSI_VVSACCR_VSA2              DSI_VVSACCR_VSA2_Msk                     
+#define DSI_VVSACCR_VSA3_Pos          (3U)                                     
+#define DSI_VVSACCR_VSA3_Msk          (0x1UL << DSI_VVSACCR_VSA3_Pos)           /*!< 0x00000008 */
+#define DSI_VVSACCR_VSA3              DSI_VVSACCR_VSA3_Msk                     
+#define DSI_VVSACCR_VSA4_Pos          (4U)                                     
+#define DSI_VVSACCR_VSA4_Msk          (0x1UL << DSI_VVSACCR_VSA4_Pos)           /*!< 0x00000010 */
+#define DSI_VVSACCR_VSA4              DSI_VVSACCR_VSA4_Msk                     
+#define DSI_VVSACCR_VSA5_Pos          (5U)                                     
+#define DSI_VVSACCR_VSA5_Msk          (0x1UL << DSI_VVSACCR_VSA5_Pos)           /*!< 0x00000020 */
+#define DSI_VVSACCR_VSA5              DSI_VVSACCR_VSA5_Msk                     
+#define DSI_VVSACCR_VSA6_Pos          (6U)                                     
+#define DSI_VVSACCR_VSA6_Msk          (0x1UL << DSI_VVSACCR_VSA6_Pos)           /*!< 0x00000040 */
+#define DSI_VVSACCR_VSA6              DSI_VVSACCR_VSA6_Msk                     
+#define DSI_VVSACCR_VSA7_Pos          (7U)                                     
+#define DSI_VVSACCR_VSA7_Msk          (0x1UL << DSI_VVSACCR_VSA7_Pos)           /*!< 0x00000080 */
+#define DSI_VVSACCR_VSA7              DSI_VVSACCR_VSA7_Msk                     
+#define DSI_VVSACCR_VSA8_Pos          (8U)                                     
+#define DSI_VVSACCR_VSA8_Msk          (0x1UL << DSI_VVSACCR_VSA8_Pos)           /*!< 0x00000100 */
+#define DSI_VVSACCR_VSA8              DSI_VVSACCR_VSA8_Msk                     
+#define DSI_VVSACCR_VSA9_Pos          (9U)                                     
+#define DSI_VVSACCR_VSA9_Msk          (0x1UL << DSI_VVSACCR_VSA9_Pos)           /*!< 0x00000200 */
+#define DSI_VVSACCR_VSA9              DSI_VVSACCR_VSA9_Msk                     
+
+/*******************  Bit definition for DSI_VVBPCCR register  ************/
+#define DSI_VVBPCCR_VBP_Pos           (0U)                                     
+#define DSI_VVBPCCR_VBP_Msk           (0x3FFUL << DSI_VVBPCCR_VBP_Pos)          /*!< 0x000003FF */
+#define DSI_VVBPCCR_VBP               DSI_VVBPCCR_VBP_Msk                      /*!< Vertical Back-Porch duration */
+#define DSI_VVBPCCR_VBP0_Pos          (0U)                                     
+#define DSI_VVBPCCR_VBP0_Msk          (0x1UL << DSI_VVBPCCR_VBP0_Pos)           /*!< 0x00000001 */
+#define DSI_VVBPCCR_VBP0              DSI_VVBPCCR_VBP0_Msk                     
+#define DSI_VVBPCCR_VBP1_Pos          (1U)                                     
+#define DSI_VVBPCCR_VBP1_Msk          (0x1UL << DSI_VVBPCCR_VBP1_Pos)           /*!< 0x00000002 */
+#define DSI_VVBPCCR_VBP1              DSI_VVBPCCR_VBP1_Msk                     
+#define DSI_VVBPCCR_VBP2_Pos          (2U)                                     
+#define DSI_VVBPCCR_VBP2_Msk          (0x1UL << DSI_VVBPCCR_VBP2_Pos)           /*!< 0x00000004 */
+#define DSI_VVBPCCR_VBP2              DSI_VVBPCCR_VBP2_Msk                     
+#define DSI_VVBPCCR_VBP3_Pos          (3U)                                     
+#define DSI_VVBPCCR_VBP3_Msk          (0x1UL << DSI_VVBPCCR_VBP3_Pos)           /*!< 0x00000008 */
+#define DSI_VVBPCCR_VBP3              DSI_VVBPCCR_VBP3_Msk                     
+#define DSI_VVBPCCR_VBP4_Pos          (4U)                                     
+#define DSI_VVBPCCR_VBP4_Msk          (0x1UL << DSI_VVBPCCR_VBP4_Pos)           /*!< 0x00000010 */
+#define DSI_VVBPCCR_VBP4              DSI_VVBPCCR_VBP4_Msk                     
+#define DSI_VVBPCCR_VBP5_Pos          (5U)                                     
+#define DSI_VVBPCCR_VBP5_Msk          (0x1UL << DSI_VVBPCCR_VBP5_Pos)           /*!< 0x00000020 */
+#define DSI_VVBPCCR_VBP5              DSI_VVBPCCR_VBP5_Msk                     
+#define DSI_VVBPCCR_VBP6_Pos          (6U)                                     
+#define DSI_VVBPCCR_VBP6_Msk          (0x1UL << DSI_VVBPCCR_VBP6_Pos)           /*!< 0x00000040 */
+#define DSI_VVBPCCR_VBP6              DSI_VVBPCCR_VBP6_Msk                     
+#define DSI_VVBPCCR_VBP7_Pos          (7U)                                     
+#define DSI_VVBPCCR_VBP7_Msk          (0x1UL << DSI_VVBPCCR_VBP7_Pos)           /*!< 0x00000080 */
+#define DSI_VVBPCCR_VBP7              DSI_VVBPCCR_VBP7_Msk                     
+#define DSI_VVBPCCR_VBP8_Pos          (8U)                                     
+#define DSI_VVBPCCR_VBP8_Msk          (0x1UL << DSI_VVBPCCR_VBP8_Pos)           /*!< 0x00000100 */
+#define DSI_VVBPCCR_VBP8              DSI_VVBPCCR_VBP8_Msk                     
+#define DSI_VVBPCCR_VBP9_Pos          (9U)                                     
+#define DSI_VVBPCCR_VBP9_Msk          (0x1UL << DSI_VVBPCCR_VBP9_Pos)           /*!< 0x00000200 */
+#define DSI_VVBPCCR_VBP9              DSI_VVBPCCR_VBP9_Msk                     
+
+/*******************  Bit definition for DSI_VVFPCCR register  ************/
+#define DSI_VVFPCCR_VFP_Pos           (0U)                                     
+#define DSI_VVFPCCR_VFP_Msk           (0x3FFUL << DSI_VVFPCCR_VFP_Pos)          /*!< 0x000003FF */
+#define DSI_VVFPCCR_VFP               DSI_VVFPCCR_VFP_Msk                      /*!< Vertical Front-Porch duration */
+#define DSI_VVFPCCR_VFP0_Pos          (0U)                                     
+#define DSI_VVFPCCR_VFP0_Msk          (0x1UL << DSI_VVFPCCR_VFP0_Pos)           /*!< 0x00000001 */
+#define DSI_VVFPCCR_VFP0              DSI_VVFPCCR_VFP0_Msk                     
+#define DSI_VVFPCCR_VFP1_Pos          (1U)                                     
+#define DSI_VVFPCCR_VFP1_Msk          (0x1UL << DSI_VVFPCCR_VFP1_Pos)           /*!< 0x00000002 */
+#define DSI_VVFPCCR_VFP1              DSI_VVFPCCR_VFP1_Msk                     
+#define DSI_VVFPCCR_VFP2_Pos          (2U)                                     
+#define DSI_VVFPCCR_VFP2_Msk          (0x1UL << DSI_VVFPCCR_VFP2_Pos)           /*!< 0x00000004 */
+#define DSI_VVFPCCR_VFP2              DSI_VVFPCCR_VFP2_Msk                     
+#define DSI_VVFPCCR_VFP3_Pos          (3U)                                     
+#define DSI_VVFPCCR_VFP3_Msk          (0x1UL << DSI_VVFPCCR_VFP3_Pos)           /*!< 0x00000008 */
+#define DSI_VVFPCCR_VFP3              DSI_VVFPCCR_VFP3_Msk                     
+#define DSI_VVFPCCR_VFP4_Pos          (4U)                                     
+#define DSI_VVFPCCR_VFP4_Msk          (0x1UL << DSI_VVFPCCR_VFP4_Pos)           /*!< 0x00000010 */
+#define DSI_VVFPCCR_VFP4              DSI_VVFPCCR_VFP4_Msk                     
+#define DSI_VVFPCCR_VFP5_Pos          (5U)                                     
+#define DSI_VVFPCCR_VFP5_Msk          (0x1UL << DSI_VVFPCCR_VFP5_Pos)           /*!< 0x00000020 */
+#define DSI_VVFPCCR_VFP5              DSI_VVFPCCR_VFP5_Msk                     
+#define DSI_VVFPCCR_VFP6_Pos          (6U)                                     
+#define DSI_VVFPCCR_VFP6_Msk          (0x1UL << DSI_VVFPCCR_VFP6_Pos)           /*!< 0x00000040 */
+#define DSI_VVFPCCR_VFP6              DSI_VVFPCCR_VFP6_Msk                     
+#define DSI_VVFPCCR_VFP7_Pos          (7U)                                     
+#define DSI_VVFPCCR_VFP7_Msk          (0x1UL << DSI_VVFPCCR_VFP7_Pos)           /*!< 0x00000080 */
+#define DSI_VVFPCCR_VFP7              DSI_VVFPCCR_VFP7_Msk                     
+#define DSI_VVFPCCR_VFP8_Pos          (8U)                                     
+#define DSI_VVFPCCR_VFP8_Msk          (0x1UL << DSI_VVFPCCR_VFP8_Pos)           /*!< 0x00000100 */
+#define DSI_VVFPCCR_VFP8              DSI_VVFPCCR_VFP8_Msk                     
+#define DSI_VVFPCCR_VFP9_Pos          (9U)                                     
+#define DSI_VVFPCCR_VFP9_Msk          (0x1UL << DSI_VVFPCCR_VFP9_Pos)           /*!< 0x00000200 */
+#define DSI_VVFPCCR_VFP9              DSI_VVFPCCR_VFP9_Msk                     
+
+/*******************  Bit definition for DSI_VVACCR register  *************/
+#define DSI_VVACCR_VA_Pos             (0U)                                     
+#define DSI_VVACCR_VA_Msk             (0x3FFFUL << DSI_VVACCR_VA_Pos)           /*!< 0x00003FFF */
+#define DSI_VVACCR_VA                 DSI_VVACCR_VA_Msk                        /*!< Vertical Active duration */
+#define DSI_VVACCR_VA0_Pos            (0U)                                     
+#define DSI_VVACCR_VA0_Msk            (0x1UL << DSI_VVACCR_VA0_Pos)             /*!< 0x00000001 */
+#define DSI_VVACCR_VA0                DSI_VVACCR_VA0_Msk                       
+#define DSI_VVACCR_VA1_Pos            (1U)                                     
+#define DSI_VVACCR_VA1_Msk            (0x1UL << DSI_VVACCR_VA1_Pos)             /*!< 0x00000002 */
+#define DSI_VVACCR_VA1                DSI_VVACCR_VA1_Msk                       
+#define DSI_VVACCR_VA2_Pos            (2U)                                     
+#define DSI_VVACCR_VA2_Msk            (0x1UL << DSI_VVACCR_VA2_Pos)             /*!< 0x00000004 */
+#define DSI_VVACCR_VA2                DSI_VVACCR_VA2_Msk                       
+#define DSI_VVACCR_VA3_Pos            (3U)                                     
+#define DSI_VVACCR_VA3_Msk            (0x1UL << DSI_VVACCR_VA3_Pos)             /*!< 0x00000008 */
+#define DSI_VVACCR_VA3                DSI_VVACCR_VA3_Msk                       
+#define DSI_VVACCR_VA4_Pos            (4U)                                     
+#define DSI_VVACCR_VA4_Msk            (0x1UL << DSI_VVACCR_VA4_Pos)             /*!< 0x00000010 */
+#define DSI_VVACCR_VA4                DSI_VVACCR_VA4_Msk                       
+#define DSI_VVACCR_VA5_Pos            (5U)                                     
+#define DSI_VVACCR_VA5_Msk            (0x1UL << DSI_VVACCR_VA5_Pos)             /*!< 0x00000020 */
+#define DSI_VVACCR_VA5                DSI_VVACCR_VA5_Msk                       
+#define DSI_VVACCR_VA6_Pos            (6U)                                     
+#define DSI_VVACCR_VA6_Msk            (0x1UL << DSI_VVACCR_VA6_Pos)             /*!< 0x00000040 */
+#define DSI_VVACCR_VA6                DSI_VVACCR_VA6_Msk                       
+#define DSI_VVACCR_VA7_Pos            (7U)                                     
+#define DSI_VVACCR_VA7_Msk            (0x1UL << DSI_VVACCR_VA7_Pos)             /*!< 0x00000080 */
+#define DSI_VVACCR_VA7                DSI_VVACCR_VA7_Msk                       
+#define DSI_VVACCR_VA8_Pos            (8U)                                     
+#define DSI_VVACCR_VA8_Msk            (0x1UL << DSI_VVACCR_VA8_Pos)             /*!< 0x00000100 */
+#define DSI_VVACCR_VA8                DSI_VVACCR_VA8_Msk                       
+#define DSI_VVACCR_VA9_Pos            (9U)                                     
+#define DSI_VVACCR_VA9_Msk            (0x1UL << DSI_VVACCR_VA9_Pos)             /*!< 0x00000200 */
+#define DSI_VVACCR_VA9                DSI_VVACCR_VA9_Msk                       
+#define DSI_VVACCR_VA10_Pos           (10U)                                    
+#define DSI_VVACCR_VA10_Msk           (0x1UL << DSI_VVACCR_VA10_Pos)            /*!< 0x00000400 */
+#define DSI_VVACCR_VA10               DSI_VVACCR_VA10_Msk                      
+#define DSI_VVACCR_VA11_Pos           (11U)                                    
+#define DSI_VVACCR_VA11_Msk           (0x1UL << DSI_VVACCR_VA11_Pos)            /*!< 0x00000800 */
+#define DSI_VVACCR_VA11               DSI_VVACCR_VA11_Msk                      
+#define DSI_VVACCR_VA12_Pos           (12U)                                    
+#define DSI_VVACCR_VA12_Msk           (0x1UL << DSI_VVACCR_VA12_Pos)            /*!< 0x00001000 */
+#define DSI_VVACCR_VA12               DSI_VVACCR_VA12_Msk                      
+#define DSI_VVACCR_VA13_Pos           (13U)                                    
+#define DSI_VVACCR_VA13_Msk           (0x1UL << DSI_VVACCR_VA13_Pos)            /*!< 0x00002000 */
+#define DSI_VVACCR_VA13               DSI_VVACCR_VA13_Msk                      
+
+/*******************  Bit definition for DSI_TDCCR register  **************/
+#define DSI_TDCCR_3DM                 0x00000003U                              /*!< 3D Mode */
+#define DSI_TDCCR_3DM0                0x00000001U                              
+#define DSI_TDCCR_3DM1                0x00000002U                              
+
+#define DSI_TDCCR_3DF                 0x0000000CU                              /*!< 3D Format */
+#define DSI_TDCCR_3DF0                0x00000004U                              
+#define DSI_TDCCR_3DF1                0x00000008U                              
+
+#define DSI_TDCCR_SVS_Pos             (4U)                                     
+#define DSI_TDCCR_SVS_Msk             (0x1UL << DSI_TDCCR_SVS_Pos)              /*!< 0x00000010 */
+#define DSI_TDCCR_SVS                 DSI_TDCCR_SVS_Msk                        /*!< Second VSYNC */
+#define DSI_TDCCR_RF_Pos              (5U)                                     
+#define DSI_TDCCR_RF_Msk              (0x1UL << DSI_TDCCR_RF_Pos)               /*!< 0x00000020 */
+#define DSI_TDCCR_RF                  DSI_TDCCR_RF_Msk                         /*!< Right First */
+#define DSI_TDCCR_S3DC_Pos            (16U)                                    
+#define DSI_TDCCR_S3DC_Msk            (0x1UL << DSI_TDCCR_S3DC_Pos)             /*!< 0x00010000 */
+#define DSI_TDCCR_S3DC                DSI_TDCCR_S3DC_Msk                       /*!< Send 3D Control */
+
+/*******************  Bit definition for DSI_WCFGR register  ***************/
+#define DSI_WCFGR_DSIM_Pos            (0U)                                     
+#define DSI_WCFGR_DSIM_Msk            (0x1UL << DSI_WCFGR_DSIM_Pos)             /*!< 0x00000001 */
+#define DSI_WCFGR_DSIM                DSI_WCFGR_DSIM_Msk                       /*!< DSI Mode */
+#define DSI_WCFGR_COLMUX_Pos          (1U)                                     
+#define DSI_WCFGR_COLMUX_Msk          (0x7UL << DSI_WCFGR_COLMUX_Pos)           /*!< 0x0000000E */
+#define DSI_WCFGR_COLMUX              DSI_WCFGR_COLMUX_Msk                     /*!< Color Multiplexing */
+#define DSI_WCFGR_COLMUX0_Pos         (1U)                                     
+#define DSI_WCFGR_COLMUX0_Msk         (0x1UL << DSI_WCFGR_COLMUX0_Pos)          /*!< 0x00000002 */
+#define DSI_WCFGR_COLMUX0             DSI_WCFGR_COLMUX0_Msk                    
+#define DSI_WCFGR_COLMUX1_Pos         (2U)                                     
+#define DSI_WCFGR_COLMUX1_Msk         (0x1UL << DSI_WCFGR_COLMUX1_Pos)          /*!< 0x00000004 */
+#define DSI_WCFGR_COLMUX1             DSI_WCFGR_COLMUX1_Msk                    
+#define DSI_WCFGR_COLMUX2_Pos         (3U)                                     
+#define DSI_WCFGR_COLMUX2_Msk         (0x1UL << DSI_WCFGR_COLMUX2_Pos)          /*!< 0x00000008 */
+#define DSI_WCFGR_COLMUX2             DSI_WCFGR_COLMUX2_Msk                    
+
+#define DSI_WCFGR_TESRC_Pos           (4U)                                     
+#define DSI_WCFGR_TESRC_Msk           (0x1UL << DSI_WCFGR_TESRC_Pos)            /*!< 0x00000010 */
+#define DSI_WCFGR_TESRC               DSI_WCFGR_TESRC_Msk                      /*!< Tearing Effect Source */
+#define DSI_WCFGR_TEPOL_Pos           (5U)                                     
+#define DSI_WCFGR_TEPOL_Msk           (0x1UL << DSI_WCFGR_TEPOL_Pos)            /*!< 0x00000020 */
+#define DSI_WCFGR_TEPOL               DSI_WCFGR_TEPOL_Msk                      /*!< Tearing Effect Polarity */
+#define DSI_WCFGR_AR_Pos              (6U)                                     
+#define DSI_WCFGR_AR_Msk              (0x1UL << DSI_WCFGR_AR_Pos)               /*!< 0x00000040 */
+#define DSI_WCFGR_AR                  DSI_WCFGR_AR_Msk                         /*!< Automatic Refresh */
+#define DSI_WCFGR_VSPOL_Pos           (7U)                                     
+#define DSI_WCFGR_VSPOL_Msk           (0x1UL << DSI_WCFGR_VSPOL_Pos)            /*!< 0x00000080 */
+#define DSI_WCFGR_VSPOL               DSI_WCFGR_VSPOL_Msk                      /*!< VSync Polarity */
+
+/*******************  Bit definition for DSI_WCR register  *****************/
+#define DSI_WCR_COLM_Pos              (0U)                                     
+#define DSI_WCR_COLM_Msk              (0x1UL << DSI_WCR_COLM_Pos)               /*!< 0x00000001 */
+#define DSI_WCR_COLM                  DSI_WCR_COLM_Msk                         /*!< Color Mode */
+#define DSI_WCR_SHTDN_Pos             (1U)                                     
+#define DSI_WCR_SHTDN_Msk             (0x1UL << DSI_WCR_SHTDN_Pos)              /*!< 0x00000002 */
+#define DSI_WCR_SHTDN                 DSI_WCR_SHTDN_Msk                        /*!< Shutdown */
+#define DSI_WCR_LTDCEN_Pos            (2U)                                     
+#define DSI_WCR_LTDCEN_Msk            (0x1UL << DSI_WCR_LTDCEN_Pos)             /*!< 0x00000004 */
+#define DSI_WCR_LTDCEN                DSI_WCR_LTDCEN_Msk                       /*!< LTDC Enable */
+#define DSI_WCR_DSIEN_Pos             (3U)                                     
+#define DSI_WCR_DSIEN_Msk             (0x1UL << DSI_WCR_DSIEN_Pos)              /*!< 0x00000008 */
+#define DSI_WCR_DSIEN                 DSI_WCR_DSIEN_Msk                        /*!< DSI Enable */
+
+/*******************  Bit definition for DSI_WIER register  ****************/
+#define DSI_WIER_TEIE_Pos             (0U)                                     
+#define DSI_WIER_TEIE_Msk             (0x1UL << DSI_WIER_TEIE_Pos)              /*!< 0x00000001 */
+#define DSI_WIER_TEIE                 DSI_WIER_TEIE_Msk                        /*!< Tearing Effect Interrupt Enable */
+#define DSI_WIER_ERIE_Pos             (1U)                                     
+#define DSI_WIER_ERIE_Msk             (0x1UL << DSI_WIER_ERIE_Pos)              /*!< 0x00000002 */
+#define DSI_WIER_ERIE                 DSI_WIER_ERIE_Msk                        /*!< End of Refresh Interrupt Enable */
+#define DSI_WIER_PLLLIE_Pos           (9U)                                     
+#define DSI_WIER_PLLLIE_Msk           (0x1UL << DSI_WIER_PLLLIE_Pos)            /*!< 0x00000200 */
+#define DSI_WIER_PLLLIE               DSI_WIER_PLLLIE_Msk                      /*!< PLL Lock Interrupt Enable */
+#define DSI_WIER_PLLUIE_Pos           (10U)                                    
+#define DSI_WIER_PLLUIE_Msk           (0x1UL << DSI_WIER_PLLUIE_Pos)            /*!< 0x00000400 */
+#define DSI_WIER_PLLUIE               DSI_WIER_PLLUIE_Msk                      /*!< PLL Unlock Interrupt Enable */
+#define DSI_WIER_RRIE_Pos             (13U)                                    
+#define DSI_WIER_RRIE_Msk             (0x1UL << DSI_WIER_RRIE_Pos)              /*!< 0x00002000 */
+#define DSI_WIER_RRIE                 DSI_WIER_RRIE_Msk                        /*!< Regulator Ready Interrupt Enable */
+
+/*******************  Bit definition for DSI_WISR register  ****************/
+#define DSI_WISR_TEIF_Pos             (0U)                                     
+#define DSI_WISR_TEIF_Msk             (0x1UL << DSI_WISR_TEIF_Pos)              /*!< 0x00000001 */
+#define DSI_WISR_TEIF                 DSI_WISR_TEIF_Msk                        /*!< Tearing Effect Interrupt Flag */
+#define DSI_WISR_ERIF_Pos             (1U)                                     
+#define DSI_WISR_ERIF_Msk             (0x1UL << DSI_WISR_ERIF_Pos)              /*!< 0x00000002 */
+#define DSI_WISR_ERIF                 DSI_WISR_ERIF_Msk                        /*!< End of Refresh Interrupt Flag */
+#define DSI_WISR_BUSY_Pos             (2U)                                     
+#define DSI_WISR_BUSY_Msk             (0x1UL << DSI_WISR_BUSY_Pos)              /*!< 0x00000004 */
+#define DSI_WISR_BUSY                 DSI_WISR_BUSY_Msk                        /*!< Busy Flag */
+#define DSI_WISR_PLLLS_Pos            (8U)                                     
+#define DSI_WISR_PLLLS_Msk            (0x1UL << DSI_WISR_PLLLS_Pos)             /*!< 0x00000100 */
+#define DSI_WISR_PLLLS                DSI_WISR_PLLLS_Msk                       /*!< PLL Lock Status */
+#define DSI_WISR_PLLLIF_Pos           (9U)                                     
+#define DSI_WISR_PLLLIF_Msk           (0x1UL << DSI_WISR_PLLLIF_Pos)            /*!< 0x00000200 */
+#define DSI_WISR_PLLLIF               DSI_WISR_PLLLIF_Msk                      /*!< PLL Lock Interrupt Flag */
+#define DSI_WISR_PLLUIF_Pos           (10U)                                    
+#define DSI_WISR_PLLUIF_Msk           (0x1UL << DSI_WISR_PLLUIF_Pos)            /*!< 0x00000400 */
+#define DSI_WISR_PLLUIF               DSI_WISR_PLLUIF_Msk                      /*!< PLL Unlock Interrupt Flag */
+#define DSI_WISR_RRS_Pos              (12U)                                    
+#define DSI_WISR_RRS_Msk              (0x1UL << DSI_WISR_RRS_Pos)               /*!< 0x00001000 */
+#define DSI_WISR_RRS                  DSI_WISR_RRS_Msk                         /*!< Regulator Ready Flag */
+#define DSI_WISR_RRIF_Pos             (13U)                                    
+#define DSI_WISR_RRIF_Msk             (0x1UL << DSI_WISR_RRIF_Pos)              /*!< 0x00002000 */
+#define DSI_WISR_RRIF                 DSI_WISR_RRIF_Msk                        /*!< Regulator Ready Interrupt Flag */
+
+/*******************  Bit definition for DSI_WIFCR register  ***************/
+#define DSI_WIFCR_CTEIF_Pos           (0U)                                     
+#define DSI_WIFCR_CTEIF_Msk           (0x1UL << DSI_WIFCR_CTEIF_Pos)            /*!< 0x00000001 */
+#define DSI_WIFCR_CTEIF               DSI_WIFCR_CTEIF_Msk                      /*!< Clear Tearing Effect Interrupt Flag */
+#define DSI_WIFCR_CERIF_Pos           (1U)                                     
+#define DSI_WIFCR_CERIF_Msk           (0x1UL << DSI_WIFCR_CERIF_Pos)            /*!< 0x00000002 */
+#define DSI_WIFCR_CERIF               DSI_WIFCR_CERIF_Msk                      /*!< Clear End of Refresh Interrupt Flag */
+#define DSI_WIFCR_CPLLLIF_Pos         (9U)                                     
+#define DSI_WIFCR_CPLLLIF_Msk         (0x1UL << DSI_WIFCR_CPLLLIF_Pos)          /*!< 0x00000200 */
+#define DSI_WIFCR_CPLLLIF             DSI_WIFCR_CPLLLIF_Msk                    /*!< Clear PLL Lock Interrupt Flag */
+#define DSI_WIFCR_CPLLUIF_Pos         (10U)                                    
+#define DSI_WIFCR_CPLLUIF_Msk         (0x1UL << DSI_WIFCR_CPLLUIF_Pos)          /*!< 0x00000400 */
+#define DSI_WIFCR_CPLLUIF             DSI_WIFCR_CPLLUIF_Msk                    /*!< Clear PLL Unlock Interrupt Flag */
+#define DSI_WIFCR_CRRIF_Pos           (13U)                                    
+#define DSI_WIFCR_CRRIF_Msk           (0x1UL << DSI_WIFCR_CRRIF_Pos)            /*!< 0x00002000 */
+#define DSI_WIFCR_CRRIF               DSI_WIFCR_CRRIF_Msk                      /*!< Clear Regulator Ready Interrupt Flag */
+
+/*******************  Bit definition for DSI_WPCR0 register  ***************/
+#define DSI_WPCR0_UIX4_Pos            (0U)                                     
+#define DSI_WPCR0_UIX4_Msk            (0x3FUL << DSI_WPCR0_UIX4_Pos)            /*!< 0x0000003F */
+#define DSI_WPCR0_UIX4                DSI_WPCR0_UIX4_Msk                       /*!< Unit Interval multiplied by 4 */
+#define DSI_WPCR0_UIX4_0              (0x01UL << DSI_WPCR0_UIX4_Pos)            /*!< 0x00000001 */
+#define DSI_WPCR0_UIX4_1              (0x02UL << DSI_WPCR0_UIX4_Pos)            /*!< 0x00000002 */
+#define DSI_WPCR0_UIX4_2              (0x04UL << DSI_WPCR0_UIX4_Pos)            /*!< 0x00000004 */
+#define DSI_WPCR0_UIX4_3              (0x08UL << DSI_WPCR0_UIX4_Pos)            /*!< 0x00000008 */
+#define DSI_WPCR0_UIX4_4              (0x10UL << DSI_WPCR0_UIX4_Pos)            /*!< 0x00000010 */
+#define DSI_WPCR0_UIX4_5              (0x20UL << DSI_WPCR0_UIX4_Pos)            /*!< 0x00000020 */
+
+#define DSI_WPCR0_SWCL_Pos            (6U)                                     
+#define DSI_WPCR0_SWCL_Msk            (0x1UL << DSI_WPCR0_SWCL_Pos)             /*!< 0x00000040 */
+#define DSI_WPCR0_SWCL                DSI_WPCR0_SWCL_Msk                       /*!< Swap pins on clock lane */
+#define DSI_WPCR0_SWDL0_Pos           (7U)                                     
+#define DSI_WPCR0_SWDL0_Msk           (0x1UL << DSI_WPCR0_SWDL0_Pos)            /*!< 0x00000080 */
+#define DSI_WPCR0_SWDL0               DSI_WPCR0_SWDL0_Msk                      /*!< Swap pins on data lane 1 */
+#define DSI_WPCR0_SWDL1_Pos           (8U)                                     
+#define DSI_WPCR0_SWDL1_Msk           (0x1UL << DSI_WPCR0_SWDL1_Pos)            /*!< 0x00000100 */
+#define DSI_WPCR0_SWDL1               DSI_WPCR0_SWDL1_Msk                      /*!< Swap pins on data lane 2 */
+#define DSI_WPCR0_HSICL_Pos           (9U)                                     
+#define DSI_WPCR0_HSICL_Msk           (0x1UL << DSI_WPCR0_HSICL_Pos)            /*!< 0x00000200 */
+#define DSI_WPCR0_HSICL               DSI_WPCR0_HSICL_Msk                      /*!< Invert the high-speed data signal on clock lane */
+#define DSI_WPCR0_HSIDL0_Pos          (10U)                                    
+#define DSI_WPCR0_HSIDL0_Msk          (0x1UL << DSI_WPCR0_HSIDL0_Pos)           /*!< 0x00000400 */
+#define DSI_WPCR0_HSIDL0              DSI_WPCR0_HSIDL0_Msk                     /*!< Invert the high-speed data signal on lane 1 */
+#define DSI_WPCR0_HSIDL1_Pos          (11U)                                    
+#define DSI_WPCR0_HSIDL1_Msk          (0x1UL << DSI_WPCR0_HSIDL1_Pos)           /*!< 0x00000800 */
+#define DSI_WPCR0_HSIDL1              DSI_WPCR0_HSIDL1_Msk                     /*!< Invert the high-speed data signal on lane 2 */
+#define DSI_WPCR0_FTXSMCL_Pos         (12U)                                    
+#define DSI_WPCR0_FTXSMCL_Msk         (0x1UL << DSI_WPCR0_FTXSMCL_Pos)          /*!< 0x00001000 */
+#define DSI_WPCR0_FTXSMCL             DSI_WPCR0_FTXSMCL_Msk                    /*!< Force clock lane in TX stop mode */
+#define DSI_WPCR0_FTXSMDL_Pos         (13U)                                    
+#define DSI_WPCR0_FTXSMDL_Msk         (0x1UL << DSI_WPCR0_FTXSMDL_Pos)          /*!< 0x00002000 */
+#define DSI_WPCR0_FTXSMDL             DSI_WPCR0_FTXSMDL_Msk                    /*!< Force data lanes in TX stop mode */
+#define DSI_WPCR0_CDOFFDL_Pos         (14U)                                    
+#define DSI_WPCR0_CDOFFDL_Msk         (0x1UL << DSI_WPCR0_CDOFFDL_Pos)          /*!< 0x00004000 */
+#define DSI_WPCR0_CDOFFDL             DSI_WPCR0_CDOFFDL_Msk                    /*!< Contention detection OFF */
+#define DSI_WPCR0_TDDL_Pos            (16U)                                    
+#define DSI_WPCR0_TDDL_Msk            (0x1UL << DSI_WPCR0_TDDL_Pos)             /*!< 0x00010000 */
+#define DSI_WPCR0_TDDL                DSI_WPCR0_TDDL_Msk                       /*!< Turn Disable Data Lanes */
+#define DSI_WPCR0_PDEN_Pos            (18U)                                    
+#define DSI_WPCR0_PDEN_Msk            (0x1UL << DSI_WPCR0_PDEN_Pos)             /*!< 0x00040000 */
+#define DSI_WPCR0_PDEN                DSI_WPCR0_PDEN_Msk                       /*!< Pull-Down Enable */
+#define DSI_WPCR0_TCLKPREPEN_Pos      (19U)                                    
+#define DSI_WPCR0_TCLKPREPEN_Msk      (0x1UL << DSI_WPCR0_TCLKPREPEN_Pos)       /*!< 0x00080000 */
+#define DSI_WPCR0_TCLKPREPEN          DSI_WPCR0_TCLKPREPEN_Msk                 /*!< Timer for t-CLKPREP Enable */
+#define DSI_WPCR0_TCLKZEROEN_Pos      (20U)                                    
+#define DSI_WPCR0_TCLKZEROEN_Msk      (0x1UL << DSI_WPCR0_TCLKZEROEN_Pos)       /*!< 0x00100000 */
+#define DSI_WPCR0_TCLKZEROEN          DSI_WPCR0_TCLKZEROEN_Msk                 /*!< Timer for t-CLKZERO Enable */
+#define DSI_WPCR0_THSPREPEN_Pos       (21U)                                    
+#define DSI_WPCR0_THSPREPEN_Msk       (0x1UL << DSI_WPCR0_THSPREPEN_Pos)        /*!< 0x00200000 */
+#define DSI_WPCR0_THSPREPEN           DSI_WPCR0_THSPREPEN_Msk                  /*!< Timer for t-HSPREP Enable */
+#define DSI_WPCR0_THSTRAILEN_Pos      (22U)                                    
+#define DSI_WPCR0_THSTRAILEN_Msk      (0x1UL << DSI_WPCR0_THSTRAILEN_Pos)       /*!< 0x00400000 */
+#define DSI_WPCR0_THSTRAILEN          DSI_WPCR0_THSTRAILEN_Msk                 /*!< Timer for t-HSTRAIL Enable */
+#define DSI_WPCR0_THSZEROEN_Pos       (23U)                                    
+#define DSI_WPCR0_THSZEROEN_Msk       (0x1UL << DSI_WPCR0_THSZEROEN_Pos)        /*!< 0x00800000 */
+#define DSI_WPCR0_THSZEROEN           DSI_WPCR0_THSZEROEN_Msk                  /*!< Timer for t-HSZERO Enable */
+#define DSI_WPCR0_TLPXDEN_Pos         (24U)                                    
+#define DSI_WPCR0_TLPXDEN_Msk         (0x1UL << DSI_WPCR0_TLPXDEN_Pos)          /*!< 0x01000000 */
+#define DSI_WPCR0_TLPXDEN             DSI_WPCR0_TLPXDEN_Msk                    /*!< Timer for t-LPXD Enable */
+#define DSI_WPCR0_THSEXITEN_Pos       (25U)                                    
+#define DSI_WPCR0_THSEXITEN_Msk       (0x1UL << DSI_WPCR0_THSEXITEN_Pos)        /*!< 0x02000000 */
+#define DSI_WPCR0_THSEXITEN           DSI_WPCR0_THSEXITEN_Msk                  /*!< Timer for t-HSEXIT Enable */
+#define DSI_WPCR0_TLPXCEN_Pos         (26U)                                    
+#define DSI_WPCR0_TLPXCEN_Msk         (0x1UL << DSI_WPCR0_TLPXCEN_Pos)          /*!< 0x04000000 */
+#define DSI_WPCR0_TLPXCEN             DSI_WPCR0_TLPXCEN_Msk                    /*!< Timer for t-LPXC Enable */
+#define DSI_WPCR0_TCLKPOSTEN_Pos      (27U)                                    
+#define DSI_WPCR0_TCLKPOSTEN_Msk      (0x1UL << DSI_WPCR0_TCLKPOSTEN_Pos)       /*!< 0x08000000 */
+#define DSI_WPCR0_TCLKPOSTEN          DSI_WPCR0_TCLKPOSTEN_Msk                 /*!< Timer for t-CLKPOST Enable */
+
+/*******************  Bit definition for DSI_WPCR1 register  ***************/
+#define DSI_WPCR1_HSTXDCL_Pos         (0U)                                     
+#define DSI_WPCR1_HSTXDCL_Msk         (0x3UL << DSI_WPCR1_HSTXDCL_Pos)          /*!< 0x00000003 */
+#define DSI_WPCR1_HSTXDCL             DSI_WPCR1_HSTXDCL_Msk                    /*!< High-Speed Transmission Delay on Clock Lane */
+#define DSI_WPCR1_HSTXDCL0_Pos        (0U)                                     
+#define DSI_WPCR1_HSTXDCL0_Msk        (0x1UL << DSI_WPCR1_HSTXDCL0_Pos)         /*!< 0x00000001 */
+#define DSI_WPCR1_HSTXDCL0            DSI_WPCR1_HSTXDCL0_Msk                   
+#define DSI_WPCR1_HSTXDCL1_Pos        (1U)                                     
+#define DSI_WPCR1_HSTXDCL1_Msk        (0x1UL << DSI_WPCR1_HSTXDCL1_Pos)         /*!< 0x00000002 */
+#define DSI_WPCR1_HSTXDCL1            DSI_WPCR1_HSTXDCL1_Msk                   
+
+#define DSI_WPCR1_HSTXDDL_Pos         (2U)                                     
+#define DSI_WPCR1_HSTXDDL_Msk         (0x3UL << DSI_WPCR1_HSTXDDL_Pos)          /*!< 0x0000000C */
+#define DSI_WPCR1_HSTXDDL             DSI_WPCR1_HSTXDDL_Msk                    /*!< High-Speed Transmission Delay on Data Lane */
+#define DSI_WPCR1_HSTXDDL0_Pos        (2U)                                     
+#define DSI_WPCR1_HSTXDDL0_Msk        (0x1UL << DSI_WPCR1_HSTXDDL0_Pos)         /*!< 0x00000004 */
+#define DSI_WPCR1_HSTXDDL0            DSI_WPCR1_HSTXDDL0_Msk                   
+#define DSI_WPCR1_HSTXDDL1_Pos        (3U)                                     
+#define DSI_WPCR1_HSTXDDL1_Msk        (0x1UL << DSI_WPCR1_HSTXDDL1_Pos)         /*!< 0x00000008 */
+#define DSI_WPCR1_HSTXDDL1            DSI_WPCR1_HSTXDDL1_Msk                   
+
+#define DSI_WPCR1_LPSRCCL_Pos         (6U)                                     
+#define DSI_WPCR1_LPSRCCL_Msk         (0x3UL << DSI_WPCR1_LPSRCCL_Pos)          /*!< 0x000000C0 */
+#define DSI_WPCR1_LPSRCCL             DSI_WPCR1_LPSRCCL_Msk                    /*!< Low-Power transmission Slew Rate Compensation on Clock Lane */
+#define DSI_WPCR1_LPSRCCL0_Pos        (6U)                                     
+#define DSI_WPCR1_LPSRCCL0_Msk        (0x1UL << DSI_WPCR1_LPSRCCL0_Pos)         /*!< 0x00000040 */
+#define DSI_WPCR1_LPSRCCL0            DSI_WPCR1_LPSRCCL0_Msk                   
+#define DSI_WPCR1_LPSRCCL1_Pos        (7U)                                     
+#define DSI_WPCR1_LPSRCCL1_Msk        (0x1UL << DSI_WPCR1_LPSRCCL1_Pos)         /*!< 0x00000080 */
+#define DSI_WPCR1_LPSRCCL1            DSI_WPCR1_LPSRCCL1_Msk                   
+
+#define DSI_WPCR1_LPSRCDL_Pos         (8U)                                     
+#define DSI_WPCR1_LPSRCDL_Msk         (0x3UL << DSI_WPCR1_LPSRCDL_Pos)          /*!< 0x00000300 */
+#define DSI_WPCR1_LPSRCDL             DSI_WPCR1_LPSRCDL_Msk                    /*!< Low-Power transmission Slew Rate Compensation on Data Lane */
+#define DSI_WPCR1_LPSRCDL0_Pos        (8U)                                     
+#define DSI_WPCR1_LPSRCDL0_Msk        (0x1UL << DSI_WPCR1_LPSRCDL0_Pos)         /*!< 0x00000100 */
+#define DSI_WPCR1_LPSRCDL0            DSI_WPCR1_LPSRCDL0_Msk                   
+#define DSI_WPCR1_LPSRCDL1_Pos        (9U)                                     
+#define DSI_WPCR1_LPSRCDL1_Msk        (0x1UL << DSI_WPCR1_LPSRCDL1_Pos)         /*!< 0x00000200 */
+#define DSI_WPCR1_LPSRCDL1            DSI_WPCR1_LPSRCDL1_Msk                   
+
+#define DSI_WPCR1_SDDC_Pos            (12U)                                    
+#define DSI_WPCR1_SDDC_Msk            (0x1UL << DSI_WPCR1_SDDC_Pos)             /*!< 0x00001000 */
+#define DSI_WPCR1_SDDC                DSI_WPCR1_SDDC_Msk                       /*!< SDD Control */
+
+#define DSI_WPCR1_LPRXVCDL_Pos        (14U)                                    
+#define DSI_WPCR1_LPRXVCDL_Msk        (0x3UL << DSI_WPCR1_LPRXVCDL_Pos)         /*!< 0x0000C000 */
+#define DSI_WPCR1_LPRXVCDL            DSI_WPCR1_LPRXVCDL_Msk                   /*!< Low-Power Reception V-IL Compensation on Data Lanes */
+#define DSI_WPCR1_LPRXVCDL0_Pos       (14U)                                    
+#define DSI_WPCR1_LPRXVCDL0_Msk       (0x1UL << DSI_WPCR1_LPRXVCDL0_Pos)        /*!< 0x00004000 */
+#define DSI_WPCR1_LPRXVCDL0           DSI_WPCR1_LPRXVCDL0_Msk                  
+#define DSI_WPCR1_LPRXVCDL1_Pos       (15U)                                    
+#define DSI_WPCR1_LPRXVCDL1_Msk       (0x1UL << DSI_WPCR1_LPRXVCDL1_Pos)        /*!< 0x00008000 */
+#define DSI_WPCR1_LPRXVCDL1           DSI_WPCR1_LPRXVCDL1_Msk                  
+
+#define DSI_WPCR1_HSTXSRCCL_Pos       (16U)                                    
+#define DSI_WPCR1_HSTXSRCCL_Msk       (0x3UL << DSI_WPCR1_HSTXSRCCL_Pos)        /*!< 0x00030000 */
+#define DSI_WPCR1_HSTXSRCCL           DSI_WPCR1_HSTXSRCCL_Msk                  /*!< High-Speed Transmission Delay on Clock Lane */
+#define DSI_WPCR1_HSTXSRCCL0_Pos      (16U)                                    
+#define DSI_WPCR1_HSTXSRCCL0_Msk      (0x1UL << DSI_WPCR1_HSTXSRCCL0_Pos)       /*!< 0x00010000 */
+#define DSI_WPCR1_HSTXSRCCL0          DSI_WPCR1_HSTXSRCCL0_Msk                 
+#define DSI_WPCR1_HSTXSRCCL1_Pos      (17U)                                    
+#define DSI_WPCR1_HSTXSRCCL1_Msk      (0x1UL << DSI_WPCR1_HSTXSRCCL1_Pos)       /*!< 0x00020000 */
+#define DSI_WPCR1_HSTXSRCCL1          DSI_WPCR1_HSTXSRCCL1_Msk                 
+
+#define DSI_WPCR1_HSTXSRCDL_Pos       (18U)                                    
+#define DSI_WPCR1_HSTXSRCDL_Msk       (0x3UL << DSI_WPCR1_HSTXSRCDL_Pos)        /*!< 0x000C0000 */
+#define DSI_WPCR1_HSTXSRCDL           DSI_WPCR1_HSTXSRCDL_Msk                  /*!< High-Speed Transmission Delay on Data Lane */
+#define DSI_WPCR1_HSTXSRCDL0_Pos      (18U)                                    
+#define DSI_WPCR1_HSTXSRCDL0_Msk      (0x1UL << DSI_WPCR1_HSTXSRCDL0_Pos)       /*!< 0x00040000 */
+#define DSI_WPCR1_HSTXSRCDL0          DSI_WPCR1_HSTXSRCDL0_Msk                 
+#define DSI_WPCR1_HSTXSRCDL1_Pos      (19U)                                    
+#define DSI_WPCR1_HSTXSRCDL1_Msk      (0x1UL << DSI_WPCR1_HSTXSRCDL1_Pos)       /*!< 0x00080000 */
+#define DSI_WPCR1_HSTXSRCDL1          DSI_WPCR1_HSTXSRCDL1_Msk                 
+
+#define DSI_WPCR1_FLPRXLPM_Pos        (22U)                                    
+#define DSI_WPCR1_FLPRXLPM_Msk        (0x1UL << DSI_WPCR1_FLPRXLPM_Pos)         /*!< 0x00400000 */
+#define DSI_WPCR1_FLPRXLPM            DSI_WPCR1_FLPRXLPM_Msk                   /*!< Forces LP Receiver in Low-Power Mode */
+
+#define DSI_WPCR1_LPRXFT_Pos          (25U)                                    
+#define DSI_WPCR1_LPRXFT_Msk          (0x3UL << DSI_WPCR1_LPRXFT_Pos)           /*!< 0x06000000 */
+#define DSI_WPCR1_LPRXFT              DSI_WPCR1_LPRXFT_Msk                     /*!< Low-Power RX low-pass Filtering Tuning */
+#define DSI_WPCR1_LPRXFT0_Pos         (25U)                                    
+#define DSI_WPCR1_LPRXFT0_Msk         (0x1UL << DSI_WPCR1_LPRXFT0_Pos)          /*!< 0x02000000 */
+#define DSI_WPCR1_LPRXFT0             DSI_WPCR1_LPRXFT0_Msk                    
+#define DSI_WPCR1_LPRXFT1_Pos         (26U)                                    
+#define DSI_WPCR1_LPRXFT1_Msk         (0x1UL << DSI_WPCR1_LPRXFT1_Pos)          /*!< 0x04000000 */
+#define DSI_WPCR1_LPRXFT1             DSI_WPCR1_LPRXFT1_Msk                    
+
+/*******************  Bit definition for DSI_WPCR2 register  ***************/
+#define DSI_WPCR2_TCLKPREP_Pos        (0U)                                     
+#define DSI_WPCR2_TCLKPREP_Msk        (0xFFUL << DSI_WPCR2_TCLKPREP_Pos)        /*!< 0x000000FF */
+#define DSI_WPCR2_TCLKPREP            DSI_WPCR2_TCLKPREP_Msk                   /*!< t-CLKPREP */
+#define DSI_WPCR2_TCLKPREP0_Pos       (0U)                                     
+#define DSI_WPCR2_TCLKPREP0_Msk       (0x1UL << DSI_WPCR2_TCLKPREP0_Pos)        /*!< 0x00000001 */
+#define DSI_WPCR2_TCLKPREP0           DSI_WPCR2_TCLKPREP0_Msk                  
+#define DSI_WPCR2_TCLKPREP1_Pos       (1U)                                     
+#define DSI_WPCR2_TCLKPREP1_Msk       (0x1UL << DSI_WPCR2_TCLKPREP1_Pos)        /*!< 0x00000002 */
+#define DSI_WPCR2_TCLKPREP1           DSI_WPCR2_TCLKPREP1_Msk                  
+#define DSI_WPCR2_TCLKPREP2_Pos       (2U)                                     
+#define DSI_WPCR2_TCLKPREP2_Msk       (0x1UL << DSI_WPCR2_TCLKPREP2_Pos)        /*!< 0x00000004 */
+#define DSI_WPCR2_TCLKPREP2           DSI_WPCR2_TCLKPREP2_Msk                  
+#define DSI_WPCR2_TCLKPREP3_Pos       (3U)                                     
+#define DSI_WPCR2_TCLKPREP3_Msk       (0x1UL << DSI_WPCR2_TCLKPREP3_Pos)        /*!< 0x00000008 */
+#define DSI_WPCR2_TCLKPREP3           DSI_WPCR2_TCLKPREP3_Msk                  
+#define DSI_WPCR2_TCLKPREP4_Pos       (4U)                                     
+#define DSI_WPCR2_TCLKPREP4_Msk       (0x1UL << DSI_WPCR2_TCLKPREP4_Pos)        /*!< 0x00000010 */
+#define DSI_WPCR2_TCLKPREP4           DSI_WPCR2_TCLKPREP4_Msk                  
+#define DSI_WPCR2_TCLKPREP5_Pos       (5U)                                     
+#define DSI_WPCR2_TCLKPREP5_Msk       (0x1UL << DSI_WPCR2_TCLKPREP5_Pos)        /*!< 0x00000020 */
+#define DSI_WPCR2_TCLKPREP5           DSI_WPCR2_TCLKPREP5_Msk                  
+#define DSI_WPCR2_TCLKPREP6_Pos       (6U)                                     
+#define DSI_WPCR2_TCLKPREP6_Msk       (0x1UL << DSI_WPCR2_TCLKPREP6_Pos)        /*!< 0x00000040 */
+#define DSI_WPCR2_TCLKPREP6           DSI_WPCR2_TCLKPREP6_Msk                  
+#define DSI_WPCR2_TCLKPREP7_Pos       (7U)                                     
+#define DSI_WPCR2_TCLKPREP7_Msk       (0x1UL << DSI_WPCR2_TCLKPREP7_Pos)        /*!< 0x00000080 */
+#define DSI_WPCR2_TCLKPREP7           DSI_WPCR2_TCLKPREP7_Msk                  
+
+#define DSI_WPCR2_TCLKZERO_Pos        (8U)                                     
+#define DSI_WPCR2_TCLKZERO_Msk        (0xFFUL << DSI_WPCR2_TCLKZERO_Pos)        /*!< 0x0000FF00 */
+#define DSI_WPCR2_TCLKZERO            DSI_WPCR2_TCLKZERO_Msk                   /*!< t-CLKZERO */
+#define DSI_WPCR2_TCLKZERO0_Pos       (8U)                                     
+#define DSI_WPCR2_TCLKZERO0_Msk       (0x1UL << DSI_WPCR2_TCLKZERO0_Pos)        /*!< 0x00000100 */
+#define DSI_WPCR2_TCLKZERO0           DSI_WPCR2_TCLKZERO0_Msk                  
+#define DSI_WPCR2_TCLKZERO1_Pos       (9U)                                     
+#define DSI_WPCR2_TCLKZERO1_Msk       (0x1UL << DSI_WPCR2_TCLKZERO1_Pos)        /*!< 0x00000200 */
+#define DSI_WPCR2_TCLKZERO1           DSI_WPCR2_TCLKZERO1_Msk                  
+#define DSI_WPCR2_TCLKZERO2_Pos       (10U)                                    
+#define DSI_WPCR2_TCLKZERO2_Msk       (0x1UL << DSI_WPCR2_TCLKZERO2_Pos)        /*!< 0x00000400 */
+#define DSI_WPCR2_TCLKZERO2           DSI_WPCR2_TCLKZERO2_Msk                  
+#define DSI_WPCR2_TCLKZERO3_Pos       (11U)                                    
+#define DSI_WPCR2_TCLKZERO3_Msk       (0x1UL << DSI_WPCR2_TCLKZERO3_Pos)        /*!< 0x00000800 */
+#define DSI_WPCR2_TCLKZERO3           DSI_WPCR2_TCLKZERO3_Msk                  
+#define DSI_WPCR2_TCLKZERO4_Pos       (12U)                                    
+#define DSI_WPCR2_TCLKZERO4_Msk       (0x1UL << DSI_WPCR2_TCLKZERO4_Pos)        /*!< 0x00001000 */
+#define DSI_WPCR2_TCLKZERO4           DSI_WPCR2_TCLKZERO4_Msk                  
+#define DSI_WPCR2_TCLKZERO5_Pos       (13U)                                    
+#define DSI_WPCR2_TCLKZERO5_Msk       (0x1UL << DSI_WPCR2_TCLKZERO5_Pos)        /*!< 0x00002000 */
+#define DSI_WPCR2_TCLKZERO5           DSI_WPCR2_TCLKZERO5_Msk                  
+#define DSI_WPCR2_TCLKZERO6_Pos       (14U)                                    
+#define DSI_WPCR2_TCLKZERO6_Msk       (0x1UL << DSI_WPCR2_TCLKZERO6_Pos)        /*!< 0x00004000 */
+#define DSI_WPCR2_TCLKZERO6           DSI_WPCR2_TCLKZERO6_Msk                  
+#define DSI_WPCR2_TCLKZERO7_Pos       (15U)                                    
+#define DSI_WPCR2_TCLKZERO7_Msk       (0x1UL << DSI_WPCR2_TCLKZERO7_Pos)        /*!< 0x00008000 */
+#define DSI_WPCR2_TCLKZERO7           DSI_WPCR2_TCLKZERO7_Msk                  
+
+#define DSI_WPCR2_THSPREP_Pos         (16U)                                    
+#define DSI_WPCR2_THSPREP_Msk         (0xFFUL << DSI_WPCR2_THSPREP_Pos)         /*!< 0x00FF0000 */
+#define DSI_WPCR2_THSPREP             DSI_WPCR2_THSPREP_Msk                    /*!< t-HSPREP */
+#define DSI_WPCR2_THSPREP0_Pos        (16U)                                    
+#define DSI_WPCR2_THSPREP0_Msk        (0x1UL << DSI_WPCR2_THSPREP0_Pos)         /*!< 0x00010000 */
+#define DSI_WPCR2_THSPREP0            DSI_WPCR2_THSPREP0_Msk                   
+#define DSI_WPCR2_THSPREP1_Pos        (17U)                                    
+#define DSI_WPCR2_THSPREP1_Msk        (0x1UL << DSI_WPCR2_THSPREP1_Pos)         /*!< 0x00020000 */
+#define DSI_WPCR2_THSPREP1            DSI_WPCR2_THSPREP1_Msk                   
+#define DSI_WPCR2_THSPREP2_Pos        (18U)                                    
+#define DSI_WPCR2_THSPREP2_Msk        (0x1UL << DSI_WPCR2_THSPREP2_Pos)         /*!< 0x00040000 */
+#define DSI_WPCR2_THSPREP2            DSI_WPCR2_THSPREP2_Msk                   
+#define DSI_WPCR2_THSPREP3_Pos        (19U)                                    
+#define DSI_WPCR2_THSPREP3_Msk        (0x1UL << DSI_WPCR2_THSPREP3_Pos)         /*!< 0x00080000 */
+#define DSI_WPCR2_THSPREP3            DSI_WPCR2_THSPREP3_Msk                   
+#define DSI_WPCR2_THSPREP4_Pos        (20U)                                    
+#define DSI_WPCR2_THSPREP4_Msk        (0x1UL << DSI_WPCR2_THSPREP4_Pos)         /*!< 0x00100000 */
+#define DSI_WPCR2_THSPREP4            DSI_WPCR2_THSPREP4_Msk                   
+#define DSI_WPCR2_THSPREP5_Pos        (21U)                                    
+#define DSI_WPCR2_THSPREP5_Msk        (0x1UL << DSI_WPCR2_THSPREP5_Pos)         /*!< 0x00200000 */
+#define DSI_WPCR2_THSPREP5            DSI_WPCR2_THSPREP5_Msk                   
+#define DSI_WPCR2_THSPREP6_Pos        (22U)                                    
+#define DSI_WPCR2_THSPREP6_Msk        (0x1UL << DSI_WPCR2_THSPREP6_Pos)         /*!< 0x00400000 */
+#define DSI_WPCR2_THSPREP6            DSI_WPCR2_THSPREP6_Msk                   
+#define DSI_WPCR2_THSPREP7_Pos        (23U)                                    
+#define DSI_WPCR2_THSPREP7_Msk        (0x1UL << DSI_WPCR2_THSPREP7_Pos)         /*!< 0x00800000 */
+#define DSI_WPCR2_THSPREP7            DSI_WPCR2_THSPREP7_Msk                   
+
+#define DSI_WPCR2_THSTRAIL_Pos        (24U)                                    
+#define DSI_WPCR2_THSTRAIL_Msk        (0xFFUL << DSI_WPCR2_THSTRAIL_Pos)        /*!< 0xFF000000 */
+#define DSI_WPCR2_THSTRAIL            DSI_WPCR2_THSTRAIL_Msk                   /*!< t-HSTRAIL */
+#define DSI_WPCR2_THSTRAIL0_Pos       (24U)                                    
+#define DSI_WPCR2_THSTRAIL0_Msk       (0x1UL << DSI_WPCR2_THSTRAIL0_Pos)        /*!< 0x01000000 */
+#define DSI_WPCR2_THSTRAIL0           DSI_WPCR2_THSTRAIL0_Msk                  
+#define DSI_WPCR2_THSTRAIL1_Pos       (25U)                                    
+#define DSI_WPCR2_THSTRAIL1_Msk       (0x1UL << DSI_WPCR2_THSTRAIL1_Pos)        /*!< 0x02000000 */
+#define DSI_WPCR2_THSTRAIL1           DSI_WPCR2_THSTRAIL1_Msk                  
+#define DSI_WPCR2_THSTRAIL2_Pos       (26U)                                    
+#define DSI_WPCR2_THSTRAIL2_Msk       (0x1UL << DSI_WPCR2_THSTRAIL2_Pos)        /*!< 0x04000000 */
+#define DSI_WPCR2_THSTRAIL2           DSI_WPCR2_THSTRAIL2_Msk                  
+#define DSI_WPCR2_THSTRAIL3_Pos       (27U)                                    
+#define DSI_WPCR2_THSTRAIL3_Msk       (0x1UL << DSI_WPCR2_THSTRAIL3_Pos)        /*!< 0x08000000 */
+#define DSI_WPCR2_THSTRAIL3           DSI_WPCR2_THSTRAIL3_Msk                  
+#define DSI_WPCR2_THSTRAIL4_Pos       (28U)                                    
+#define DSI_WPCR2_THSTRAIL4_Msk       (0x1UL << DSI_WPCR2_THSTRAIL4_Pos)        /*!< 0x10000000 */
+#define DSI_WPCR2_THSTRAIL4           DSI_WPCR2_THSTRAIL4_Msk                  
+#define DSI_WPCR2_THSTRAIL5_Pos       (29U)                                    
+#define DSI_WPCR2_THSTRAIL5_Msk       (0x1UL << DSI_WPCR2_THSTRAIL5_Pos)        /*!< 0x20000000 */
+#define DSI_WPCR2_THSTRAIL5           DSI_WPCR2_THSTRAIL5_Msk                  
+#define DSI_WPCR2_THSTRAIL6_Pos       (30U)                                    
+#define DSI_WPCR2_THSTRAIL6_Msk       (0x1UL << DSI_WPCR2_THSTRAIL6_Pos)        /*!< 0x40000000 */
+#define DSI_WPCR2_THSTRAIL6           DSI_WPCR2_THSTRAIL6_Msk                  
+#define DSI_WPCR2_THSTRAIL7_Pos       (31U)                                    
+#define DSI_WPCR2_THSTRAIL7_Msk       (0x1UL << DSI_WPCR2_THSTRAIL7_Pos)        /*!< 0x80000000 */
+#define DSI_WPCR2_THSTRAIL7           DSI_WPCR2_THSTRAIL7_Msk                  
+
+/*******************  Bit definition for DSI_WPCR3 register  ***************/
+#define DSI_WPCR3_THSZERO_Pos         (0U)                                     
+#define DSI_WPCR3_THSZERO_Msk         (0xFFUL << DSI_WPCR3_THSZERO_Pos)         /*!< 0x000000FF */
+#define DSI_WPCR3_THSZERO             DSI_WPCR3_THSZERO_Msk                    /*!< t-HSZERO */
+#define DSI_WPCR3_THSZERO0_Pos        (0U)                                     
+#define DSI_WPCR3_THSZERO0_Msk        (0x1UL << DSI_WPCR3_THSZERO0_Pos)         /*!< 0x00000001 */
+#define DSI_WPCR3_THSZERO0            DSI_WPCR3_THSZERO0_Msk                   
+#define DSI_WPCR3_THSZERO1_Pos        (1U)                                     
+#define DSI_WPCR3_THSZERO1_Msk        (0x1UL << DSI_WPCR3_THSZERO1_Pos)         /*!< 0x00000002 */
+#define DSI_WPCR3_THSZERO1            DSI_WPCR3_THSZERO1_Msk                   
+#define DSI_WPCR3_THSZERO2_Pos        (2U)                                     
+#define DSI_WPCR3_THSZERO2_Msk        (0x1UL << DSI_WPCR3_THSZERO2_Pos)         /*!< 0x00000004 */
+#define DSI_WPCR3_THSZERO2            DSI_WPCR3_THSZERO2_Msk                   
+#define DSI_WPCR3_THSZERO3_Pos        (3U)                                     
+#define DSI_WPCR3_THSZERO3_Msk        (0x1UL << DSI_WPCR3_THSZERO3_Pos)         /*!< 0x00000008 */
+#define DSI_WPCR3_THSZERO3            DSI_WPCR3_THSZERO3_Msk                   
+#define DSI_WPCR3_THSZERO4_Pos        (4U)                                     
+#define DSI_WPCR3_THSZERO4_Msk        (0x1UL << DSI_WPCR3_THSZERO4_Pos)         /*!< 0x00000010 */
+#define DSI_WPCR3_THSZERO4            DSI_WPCR3_THSZERO4_Msk                   
+#define DSI_WPCR3_THSZERO5_Pos        (5U)                                     
+#define DSI_WPCR3_THSZERO5_Msk        (0x1UL << DSI_WPCR3_THSZERO5_Pos)         /*!< 0x00000020 */
+#define DSI_WPCR3_THSZERO5            DSI_WPCR3_THSZERO5_Msk                   
+#define DSI_WPCR3_THSZERO6_Pos        (6U)                                     
+#define DSI_WPCR3_THSZERO6_Msk        (0x1UL << DSI_WPCR3_THSZERO6_Pos)         /*!< 0x00000040 */
+#define DSI_WPCR3_THSZERO6            DSI_WPCR3_THSZERO6_Msk                   
+#define DSI_WPCR3_THSZERO7_Pos        (7U)                                     
+#define DSI_WPCR3_THSZERO7_Msk        (0x1UL << DSI_WPCR3_THSZERO7_Pos)         /*!< 0x00000080 */
+#define DSI_WPCR3_THSZERO7            DSI_WPCR3_THSZERO7_Msk                   
+
+#define DSI_WPCR3_TLPXD_Pos           (8U)                                     
+#define DSI_WPCR3_TLPXD_Msk           (0xFFUL << DSI_WPCR3_TLPXD_Pos)           /*!< 0x0000FF00 */
+#define DSI_WPCR3_TLPXD               DSI_WPCR3_TLPXD_Msk                      /*!< t-LPXD */
+#define DSI_WPCR3_TLPXD0_Pos          (8U)                                     
+#define DSI_WPCR3_TLPXD0_Msk          (0x1UL << DSI_WPCR3_TLPXD0_Pos)           /*!< 0x00000100 */
+#define DSI_WPCR3_TLPXD0              DSI_WPCR3_TLPXD0_Msk                     
+#define DSI_WPCR3_TLPXD1_Pos          (9U)                                     
+#define DSI_WPCR3_TLPXD1_Msk          (0x1UL << DSI_WPCR3_TLPXD1_Pos)           /*!< 0x00000200 */
+#define DSI_WPCR3_TLPXD1              DSI_WPCR3_TLPXD1_Msk                     
+#define DSI_WPCR3_TLPXD2_Pos          (10U)                                    
+#define DSI_WPCR3_TLPXD2_Msk          (0x1UL << DSI_WPCR3_TLPXD2_Pos)           /*!< 0x00000400 */
+#define DSI_WPCR3_TLPXD2              DSI_WPCR3_TLPXD2_Msk                     
+#define DSI_WPCR3_TLPXD3_Pos          (11U)                                    
+#define DSI_WPCR3_TLPXD3_Msk          (0x1UL << DSI_WPCR3_TLPXD3_Pos)           /*!< 0x00000800 */
+#define DSI_WPCR3_TLPXD3              DSI_WPCR3_TLPXD3_Msk                     
+#define DSI_WPCR3_TLPXD4_Pos          (12U)                                    
+#define DSI_WPCR3_TLPXD4_Msk          (0x1UL << DSI_WPCR3_TLPXD4_Pos)           /*!< 0x00001000 */
+#define DSI_WPCR3_TLPXD4              DSI_WPCR3_TLPXD4_Msk                     
+#define DSI_WPCR3_TLPXD5_Pos          (13U)                                    
+#define DSI_WPCR3_TLPXD5_Msk          (0x1UL << DSI_WPCR3_TLPXD5_Pos)           /*!< 0x00002000 */
+#define DSI_WPCR3_TLPXD5              DSI_WPCR3_TLPXD5_Msk                     
+#define DSI_WPCR3_TLPXD6_Pos          (14U)                                    
+#define DSI_WPCR3_TLPXD6_Msk          (0x1UL << DSI_WPCR3_TLPXD6_Pos)           /*!< 0x00004000 */
+#define DSI_WPCR3_TLPXD6              DSI_WPCR3_TLPXD6_Msk                     
+#define DSI_WPCR3_TLPXD7_Pos          (15U)                                    
+#define DSI_WPCR3_TLPXD7_Msk          (0x1UL << DSI_WPCR3_TLPXD7_Pos)           /*!< 0x00008000 */
+#define DSI_WPCR3_TLPXD7              DSI_WPCR3_TLPXD7_Msk                     
+
+#define DSI_WPCR3_THSEXIT_Pos         (16U)                                    
+#define DSI_WPCR3_THSEXIT_Msk         (0xFFUL << DSI_WPCR3_THSEXIT_Pos)         /*!< 0x00FF0000 */
+#define DSI_WPCR3_THSEXIT             DSI_WPCR3_THSEXIT_Msk                    /*!< t-HSEXIT */
+#define DSI_WPCR3_THSEXIT0_Pos        (16U)                                    
+#define DSI_WPCR3_THSEXIT0_Msk        (0x1UL << DSI_WPCR3_THSEXIT0_Pos)         /*!< 0x00010000 */
+#define DSI_WPCR3_THSEXIT0            DSI_WPCR3_THSEXIT0_Msk                   
+#define DSI_WPCR3_THSEXIT1_Pos        (17U)                                    
+#define DSI_WPCR3_THSEXIT1_Msk        (0x1UL << DSI_WPCR3_THSEXIT1_Pos)         /*!< 0x00020000 */
+#define DSI_WPCR3_THSEXIT1            DSI_WPCR3_THSEXIT1_Msk                   
+#define DSI_WPCR3_THSEXIT2_Pos        (18U)                                    
+#define DSI_WPCR3_THSEXIT2_Msk        (0x1UL << DSI_WPCR3_THSEXIT2_Pos)         /*!< 0x00040000 */
+#define DSI_WPCR3_THSEXIT2            DSI_WPCR3_THSEXIT2_Msk                   
+#define DSI_WPCR3_THSEXIT3_Pos        (19U)                                    
+#define DSI_WPCR3_THSEXIT3_Msk        (0x1UL << DSI_WPCR3_THSEXIT3_Pos)         /*!< 0x00080000 */
+#define DSI_WPCR3_THSEXIT3            DSI_WPCR3_THSEXIT3_Msk                   
+#define DSI_WPCR3_THSEXIT4_Pos        (20U)                                    
+#define DSI_WPCR3_THSEXIT4_Msk        (0x1UL << DSI_WPCR3_THSEXIT4_Pos)         /*!< 0x00100000 */
+#define DSI_WPCR3_THSEXIT4            DSI_WPCR3_THSEXIT4_Msk                   
+#define DSI_WPCR3_THSEXIT5_Pos        (21U)                                    
+#define DSI_WPCR3_THSEXIT5_Msk        (0x1UL << DSI_WPCR3_THSEXIT5_Pos)         /*!< 0x00200000 */
+#define DSI_WPCR3_THSEXIT5            DSI_WPCR3_THSEXIT5_Msk                   
+#define DSI_WPCR3_THSEXIT6_Pos        (22U)                                    
+#define DSI_WPCR3_THSEXIT6_Msk        (0x1UL << DSI_WPCR3_THSEXIT6_Pos)         /*!< 0x00400000 */
+#define DSI_WPCR3_THSEXIT6            DSI_WPCR3_THSEXIT6_Msk                   
+#define DSI_WPCR3_THSEXIT7_Pos        (23U)                                    
+#define DSI_WPCR3_THSEXIT7_Msk        (0x1UL << DSI_WPCR3_THSEXIT7_Pos)         /*!< 0x00800000 */
+#define DSI_WPCR3_THSEXIT7            DSI_WPCR3_THSEXIT7_Msk                   
+
+#define DSI_WPCR3_TLPXC_Pos           (24U)                                    
+#define DSI_WPCR3_TLPXC_Msk           (0xFFUL << DSI_WPCR3_TLPXC_Pos)           /*!< 0xFF000000 */
+#define DSI_WPCR3_TLPXC               DSI_WPCR3_TLPXC_Msk                      /*!< t-LPXC */
+#define DSI_WPCR3_TLPXC0_Pos          (24U)                                    
+#define DSI_WPCR3_TLPXC0_Msk          (0x1UL << DSI_WPCR3_TLPXC0_Pos)           /*!< 0x01000000 */
+#define DSI_WPCR3_TLPXC0              DSI_WPCR3_TLPXC0_Msk                     
+#define DSI_WPCR3_TLPXC1_Pos          (25U)                                    
+#define DSI_WPCR3_TLPXC1_Msk          (0x1UL << DSI_WPCR3_TLPXC1_Pos)           /*!< 0x02000000 */
+#define DSI_WPCR3_TLPXC1              DSI_WPCR3_TLPXC1_Msk                     
+#define DSI_WPCR3_TLPXC2_Pos          (26U)                                    
+#define DSI_WPCR3_TLPXC2_Msk          (0x1UL << DSI_WPCR3_TLPXC2_Pos)           /*!< 0x04000000 */
+#define DSI_WPCR3_TLPXC2              DSI_WPCR3_TLPXC2_Msk                     
+#define DSI_WPCR3_TLPXC3_Pos          (27U)                                    
+#define DSI_WPCR3_TLPXC3_Msk          (0x1UL << DSI_WPCR3_TLPXC3_Pos)           /*!< 0x08000000 */
+#define DSI_WPCR3_TLPXC3              DSI_WPCR3_TLPXC3_Msk                     
+#define DSI_WPCR3_TLPXC4_Pos          (28U)                                    
+#define DSI_WPCR3_TLPXC4_Msk          (0x1UL << DSI_WPCR3_TLPXC4_Pos)           /*!< 0x10000000 */
+#define DSI_WPCR3_TLPXC4              DSI_WPCR3_TLPXC4_Msk                     
+#define DSI_WPCR3_TLPXC5_Pos          (29U)                                    
+#define DSI_WPCR3_TLPXC5_Msk          (0x1UL << DSI_WPCR3_TLPXC5_Pos)           /*!< 0x20000000 */
+#define DSI_WPCR3_TLPXC5              DSI_WPCR3_TLPXC5_Msk                     
+#define DSI_WPCR3_TLPXC6_Pos          (30U)                                    
+#define DSI_WPCR3_TLPXC6_Msk          (0x1UL << DSI_WPCR3_TLPXC6_Pos)           /*!< 0x40000000 */
+#define DSI_WPCR3_TLPXC6              DSI_WPCR3_TLPXC6_Msk                     
+#define DSI_WPCR3_TLPXC7_Pos          (31U)                                    
+#define DSI_WPCR3_TLPXC7_Msk          (0x1UL << DSI_WPCR3_TLPXC7_Pos)           /*!< 0x80000000 */
+#define DSI_WPCR3_TLPXC7              DSI_WPCR3_TLPXC7_Msk                     
+
+/*******************  Bit definition for DSI_WPCR4 register  ***************/
+#define DSI_WPCR4_TCLKPOST_Pos        (0U)                                     
+#define DSI_WPCR4_TCLKPOST_Msk        (0xFFUL << DSI_WPCR4_TCLKPOST_Pos)        /*!< 0x000000FF */
+#define DSI_WPCR4_TCLKPOST            DSI_WPCR4_TCLKPOST_Msk                   /*!< t-CLKPOST */
+#define DSI_WPCR4_TCLKPOST0_Pos       (0U)                                     
+#define DSI_WPCR4_TCLKPOST0_Msk       (0x1UL << DSI_WPCR4_TCLKPOST0_Pos)        /*!< 0x00000001 */
+#define DSI_WPCR4_TCLKPOST0           DSI_WPCR4_TCLKPOST0_Msk                  
+#define DSI_WPCR4_TCLKPOST1_Pos       (1U)                                     
+#define DSI_WPCR4_TCLKPOST1_Msk       (0x1UL << DSI_WPCR4_TCLKPOST1_Pos)        /*!< 0x00000002 */
+#define DSI_WPCR4_TCLKPOST1           DSI_WPCR4_TCLKPOST1_Msk                  
+#define DSI_WPCR4_TCLKPOST2_Pos       (2U)                                     
+#define DSI_WPCR4_TCLKPOST2_Msk       (0x1UL << DSI_WPCR4_TCLKPOST2_Pos)        /*!< 0x00000004 */
+#define DSI_WPCR4_TCLKPOST2           DSI_WPCR4_TCLKPOST2_Msk                  
+#define DSI_WPCR4_TCLKPOST3_Pos       (3U)                                     
+#define DSI_WPCR4_TCLKPOST3_Msk       (0x1UL << DSI_WPCR4_TCLKPOST3_Pos)        /*!< 0x00000008 */
+#define DSI_WPCR4_TCLKPOST3           DSI_WPCR4_TCLKPOST3_Msk                  
+#define DSI_WPCR4_TCLKPOST4_Pos       (4U)                                     
+#define DSI_WPCR4_TCLKPOST4_Msk       (0x1UL << DSI_WPCR4_TCLKPOST4_Pos)        /*!< 0x00000010 */
+#define DSI_WPCR4_TCLKPOST4           DSI_WPCR4_TCLKPOST4_Msk                  
+#define DSI_WPCR4_TCLKPOST5_Pos       (5U)                                     
+#define DSI_WPCR4_TCLKPOST5_Msk       (0x1UL << DSI_WPCR4_TCLKPOST5_Pos)        /*!< 0x00000020 */
+#define DSI_WPCR4_TCLKPOST5           DSI_WPCR4_TCLKPOST5_Msk                  
+#define DSI_WPCR4_TCLKPOST6_Pos       (6U)                                     
+#define DSI_WPCR4_TCLKPOST6_Msk       (0x1UL << DSI_WPCR4_TCLKPOST6_Pos)        /*!< 0x00000040 */
+#define DSI_WPCR4_TCLKPOST6           DSI_WPCR4_TCLKPOST6_Msk                  
+#define DSI_WPCR4_TCLKPOST7_Pos       (7U)                                     
+#define DSI_WPCR4_TCLKPOST7_Msk       (0x1UL << DSI_WPCR4_TCLKPOST7_Pos)        /*!< 0x00000080 */
+#define DSI_WPCR4_TCLKPOST7           DSI_WPCR4_TCLKPOST7_Msk                  
+
+/*******************  Bit definition for DSI_WRPCR register  ***************/
+#define DSI_WRPCR_PLLEN_Pos           (0U)                                     
+#define DSI_WRPCR_PLLEN_Msk           (0x1UL << DSI_WRPCR_PLLEN_Pos)            /*!< 0x00000001 */
+#define DSI_WRPCR_PLLEN               DSI_WRPCR_PLLEN_Msk                      /*!< PLL Enable */
+#define DSI_WRPCR_PLL_NDIV_Pos        (2U)                                     
+#define DSI_WRPCR_PLL_NDIV_Msk        (0x7FUL << DSI_WRPCR_PLL_NDIV_Pos)        /*!< 0x000001FC */
+#define DSI_WRPCR_PLL_NDIV            DSI_WRPCR_PLL_NDIV_Msk                   /*!< PLL Loop Division Factor */
+#define DSI_WRPCR_PLL_NDIV0_Pos       (2U)                                     
+#define DSI_WRPCR_PLL_NDIV0_Msk       (0x1UL << DSI_WRPCR_PLL_NDIV0_Pos)        /*!< 0x00000004 */
+#define DSI_WRPCR_PLL_NDIV0           DSI_WRPCR_PLL_NDIV0_Msk                  
+#define DSI_WRPCR_PLL_NDIV1_Pos       (3U)                                     
+#define DSI_WRPCR_PLL_NDIV1_Msk       (0x1UL << DSI_WRPCR_PLL_NDIV1_Pos)        /*!< 0x00000008 */
+#define DSI_WRPCR_PLL_NDIV1           DSI_WRPCR_PLL_NDIV1_Msk                  
+#define DSI_WRPCR_PLL_NDIV2_Pos       (4U)                                     
+#define DSI_WRPCR_PLL_NDIV2_Msk       (0x1UL << DSI_WRPCR_PLL_NDIV2_Pos)        /*!< 0x00000010 */
+#define DSI_WRPCR_PLL_NDIV2           DSI_WRPCR_PLL_NDIV2_Msk                  
+#define DSI_WRPCR_PLL_NDIV3_Pos       (5U)                                     
+#define DSI_WRPCR_PLL_NDIV3_Msk       (0x1UL << DSI_WRPCR_PLL_NDIV3_Pos)        /*!< 0x00000020 */
+#define DSI_WRPCR_PLL_NDIV3           DSI_WRPCR_PLL_NDIV3_Msk                  
+#define DSI_WRPCR_PLL_NDIV4_Pos       (6U)                                     
+#define DSI_WRPCR_PLL_NDIV4_Msk       (0x1UL << DSI_WRPCR_PLL_NDIV4_Pos)        /*!< 0x00000040 */
+#define DSI_WRPCR_PLL_NDIV4           DSI_WRPCR_PLL_NDIV4_Msk                  
+#define DSI_WRPCR_PLL_NDIV5_Pos       (7U)                                     
+#define DSI_WRPCR_PLL_NDIV5_Msk       (0x1UL << DSI_WRPCR_PLL_NDIV5_Pos)        /*!< 0x00000080 */
+#define DSI_WRPCR_PLL_NDIV5           DSI_WRPCR_PLL_NDIV5_Msk                  
+#define DSI_WRPCR_PLL_NDIV6_Pos       (8U)                                     
+#define DSI_WRPCR_PLL_NDIV6_Msk       (0x1UL << DSI_WRPCR_PLL_NDIV6_Pos)        /*!< 0x00000100 */
+#define DSI_WRPCR_PLL_NDIV6           DSI_WRPCR_PLL_NDIV6_Msk                  
+
+#define DSI_WRPCR_PLL_IDF_Pos         (11U)                                    
+#define DSI_WRPCR_PLL_IDF_Msk         (0xFUL << DSI_WRPCR_PLL_IDF_Pos)          /*!< 0x00007800 */
+#define DSI_WRPCR_PLL_IDF             DSI_WRPCR_PLL_IDF_Msk                    /*!< PLL Input Division Factor */
+#define DSI_WRPCR_PLL_IDF0_Pos        (11U)                                    
+#define DSI_WRPCR_PLL_IDF0_Msk        (0x1UL << DSI_WRPCR_PLL_IDF0_Pos)         /*!< 0x00000800 */
+#define DSI_WRPCR_PLL_IDF0            DSI_WRPCR_PLL_IDF0_Msk                   
+#define DSI_WRPCR_PLL_IDF1_Pos        (12U)                                    
+#define DSI_WRPCR_PLL_IDF1_Msk        (0x1UL << DSI_WRPCR_PLL_IDF1_Pos)         /*!< 0x00001000 */
+#define DSI_WRPCR_PLL_IDF1            DSI_WRPCR_PLL_IDF1_Msk                   
+#define DSI_WRPCR_PLL_IDF2_Pos        (13U)                                    
+#define DSI_WRPCR_PLL_IDF2_Msk        (0x1UL << DSI_WRPCR_PLL_IDF2_Pos)         /*!< 0x00002000 */
+#define DSI_WRPCR_PLL_IDF2            DSI_WRPCR_PLL_IDF2_Msk                   
+#define DSI_WRPCR_PLL_IDF3_Pos        (14U)                                    
+#define DSI_WRPCR_PLL_IDF3_Msk        (0x1UL << DSI_WRPCR_PLL_IDF3_Pos)         /*!< 0x00004000 */
+#define DSI_WRPCR_PLL_IDF3            DSI_WRPCR_PLL_IDF3_Msk                   
+
+#define DSI_WRPCR_PLL_ODF_Pos         (16U)                                    
+#define DSI_WRPCR_PLL_ODF_Msk         (0x3UL << DSI_WRPCR_PLL_ODF_Pos)          /*!< 0x00030000 */
+#define DSI_WRPCR_PLL_ODF             DSI_WRPCR_PLL_ODF_Msk                    /*!< PLL Output Division Factor */
+#define DSI_WRPCR_PLL_ODF0_Pos        (16U)                                    
+#define DSI_WRPCR_PLL_ODF0_Msk        (0x1UL << DSI_WRPCR_PLL_ODF0_Pos)         /*!< 0x00010000 */
+#define DSI_WRPCR_PLL_ODF0            DSI_WRPCR_PLL_ODF0_Msk                   
+#define DSI_WRPCR_PLL_ODF1_Pos        (17U)                                    
+#define DSI_WRPCR_PLL_ODF1_Msk        (0x1UL << DSI_WRPCR_PLL_ODF1_Pos)         /*!< 0x00020000 */
+#define DSI_WRPCR_PLL_ODF1            DSI_WRPCR_PLL_ODF1_Msk                   
+
+#define DSI_WRPCR_REGEN_Pos           (24U)                                    
+#define DSI_WRPCR_REGEN_Msk           (0x1UL << DSI_WRPCR_REGEN_Pos)            /*!< 0x01000000 */
+#define DSI_WRPCR_REGEN               DSI_WRPCR_REGEN_Msk                      /*!< Regulator Enable */
+
+/******************************************************************************/
+/*                                                                            */
+/*                    External Interrupt/Event Controller                     */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for EXTI_IMR register  *******************/
+#define EXTI_IMR_MR0_Pos          (0U)                                         
+#define EXTI_IMR_MR0_Msk          (0x1UL << EXTI_IMR_MR0_Pos)                   /*!< 0x00000001 */
+#define EXTI_IMR_MR0              EXTI_IMR_MR0_Msk                             /*!< Interrupt Mask on line 0 */
+#define EXTI_IMR_MR1_Pos          (1U)                                         
+#define EXTI_IMR_MR1_Msk          (0x1UL << EXTI_IMR_MR1_Pos)                   /*!< 0x00000002 */
+#define EXTI_IMR_MR1              EXTI_IMR_MR1_Msk                             /*!< Interrupt Mask on line 1 */
+#define EXTI_IMR_MR2_Pos          (2U)                                         
+#define EXTI_IMR_MR2_Msk          (0x1UL << EXTI_IMR_MR2_Pos)                   /*!< 0x00000004 */
+#define EXTI_IMR_MR2              EXTI_IMR_MR2_Msk                             /*!< Interrupt Mask on line 2 */
+#define EXTI_IMR_MR3_Pos          (3U)                                         
+#define EXTI_IMR_MR3_Msk          (0x1UL << EXTI_IMR_MR3_Pos)                   /*!< 0x00000008 */
+#define EXTI_IMR_MR3              EXTI_IMR_MR3_Msk                             /*!< Interrupt Mask on line 3 */
+#define EXTI_IMR_MR4_Pos          (4U)                                         
+#define EXTI_IMR_MR4_Msk          (0x1UL << EXTI_IMR_MR4_Pos)                   /*!< 0x00000010 */
+#define EXTI_IMR_MR4              EXTI_IMR_MR4_Msk                             /*!< Interrupt Mask on line 4 */
+#define EXTI_IMR_MR5_Pos          (5U)                                         
+#define EXTI_IMR_MR5_Msk          (0x1UL << EXTI_IMR_MR5_Pos)                   /*!< 0x00000020 */
+#define EXTI_IMR_MR5              EXTI_IMR_MR5_Msk                             /*!< Interrupt Mask on line 5 */
+#define EXTI_IMR_MR6_Pos          (6U)                                         
+#define EXTI_IMR_MR6_Msk          (0x1UL << EXTI_IMR_MR6_Pos)                   /*!< 0x00000040 */
+#define EXTI_IMR_MR6              EXTI_IMR_MR6_Msk                             /*!< Interrupt Mask on line 6 */
+#define EXTI_IMR_MR7_Pos          (7U)                                         
+#define EXTI_IMR_MR7_Msk          (0x1UL << EXTI_IMR_MR7_Pos)                   /*!< 0x00000080 */
+#define EXTI_IMR_MR7              EXTI_IMR_MR7_Msk                             /*!< Interrupt Mask on line 7 */
+#define EXTI_IMR_MR8_Pos          (8U)                                         
+#define EXTI_IMR_MR8_Msk          (0x1UL << EXTI_IMR_MR8_Pos)                   /*!< 0x00000100 */
+#define EXTI_IMR_MR8              EXTI_IMR_MR8_Msk                             /*!< Interrupt Mask on line 8 */
+#define EXTI_IMR_MR9_Pos          (9U)                                         
+#define EXTI_IMR_MR9_Msk          (0x1UL << EXTI_IMR_MR9_Pos)                   /*!< 0x00000200 */
+#define EXTI_IMR_MR9              EXTI_IMR_MR9_Msk                             /*!< Interrupt Mask on line 9 */
+#define EXTI_IMR_MR10_Pos         (10U)                                        
+#define EXTI_IMR_MR10_Msk         (0x1UL << EXTI_IMR_MR10_Pos)                  /*!< 0x00000400 */
+#define EXTI_IMR_MR10             EXTI_IMR_MR10_Msk                            /*!< Interrupt Mask on line 10 */
+#define EXTI_IMR_MR11_Pos         (11U)                                        
+#define EXTI_IMR_MR11_Msk         (0x1UL << EXTI_IMR_MR11_Pos)                  /*!< 0x00000800 */
+#define EXTI_IMR_MR11             EXTI_IMR_MR11_Msk                            /*!< Interrupt Mask on line 11 */
+#define EXTI_IMR_MR12_Pos         (12U)                                        
+#define EXTI_IMR_MR12_Msk         (0x1UL << EXTI_IMR_MR12_Pos)                  /*!< 0x00001000 */
+#define EXTI_IMR_MR12             EXTI_IMR_MR12_Msk                            /*!< Interrupt Mask on line 12 */
+#define EXTI_IMR_MR13_Pos         (13U)                                        
+#define EXTI_IMR_MR13_Msk         (0x1UL << EXTI_IMR_MR13_Pos)                  /*!< 0x00002000 */
+#define EXTI_IMR_MR13             EXTI_IMR_MR13_Msk                            /*!< Interrupt Mask on line 13 */
+#define EXTI_IMR_MR14_Pos         (14U)                                        
+#define EXTI_IMR_MR14_Msk         (0x1UL << EXTI_IMR_MR14_Pos)                  /*!< 0x00004000 */
+#define EXTI_IMR_MR14             EXTI_IMR_MR14_Msk                            /*!< Interrupt Mask on line 14 */
+#define EXTI_IMR_MR15_Pos         (15U)                                        
+#define EXTI_IMR_MR15_Msk         (0x1UL << EXTI_IMR_MR15_Pos)                  /*!< 0x00008000 */
+#define EXTI_IMR_MR15             EXTI_IMR_MR15_Msk                            /*!< Interrupt Mask on line 15 */
+#define EXTI_IMR_MR16_Pos         (16U)                                        
+#define EXTI_IMR_MR16_Msk         (0x1UL << EXTI_IMR_MR16_Pos)                  /*!< 0x00010000 */
+#define EXTI_IMR_MR16             EXTI_IMR_MR16_Msk                            /*!< Interrupt Mask on line 16 */
+#define EXTI_IMR_MR17_Pos         (17U)                                        
+#define EXTI_IMR_MR17_Msk         (0x1UL << EXTI_IMR_MR17_Pos)                  /*!< 0x00020000 */
+#define EXTI_IMR_MR17             EXTI_IMR_MR17_Msk                            /*!< Interrupt Mask on line 17 */
+#define EXTI_IMR_MR18_Pos         (18U)                                        
+#define EXTI_IMR_MR18_Msk         (0x1UL << EXTI_IMR_MR18_Pos)                  /*!< 0x00040000 */
+#define EXTI_IMR_MR18             EXTI_IMR_MR18_Msk                            /*!< Interrupt Mask on line 18 */
+#define EXTI_IMR_MR19_Pos         (19U)                                        
+#define EXTI_IMR_MR19_Msk         (0x1UL << EXTI_IMR_MR19_Pos)                  /*!< 0x00080000 */
+#define EXTI_IMR_MR19             EXTI_IMR_MR19_Msk                            /*!< Interrupt Mask on line 19 */
+#define EXTI_IMR_MR20_Pos         (20U)                                        
+#define EXTI_IMR_MR20_Msk         (0x1UL << EXTI_IMR_MR20_Pos)                  /*!< 0x00100000 */
+#define EXTI_IMR_MR20             EXTI_IMR_MR20_Msk                            /*!< Interrupt Mask on line 20 */
+#define EXTI_IMR_MR21_Pos         (21U)                                        
+#define EXTI_IMR_MR21_Msk         (0x1UL << EXTI_IMR_MR21_Pos)                  /*!< 0x00200000 */
+#define EXTI_IMR_MR21             EXTI_IMR_MR21_Msk                            /*!< Interrupt Mask on line 21 */
+#define EXTI_IMR_MR22_Pos         (22U)                                        
+#define EXTI_IMR_MR22_Msk         (0x1UL << EXTI_IMR_MR22_Pos)                  /*!< 0x00400000 */
+#define EXTI_IMR_MR22             EXTI_IMR_MR22_Msk                            /*!< Interrupt Mask on line 22 */
+
+/* Reference Defines */
+#define  EXTI_IMR_IM0                        EXTI_IMR_MR0
+#define  EXTI_IMR_IM1                        EXTI_IMR_MR1
+#define  EXTI_IMR_IM2                        EXTI_IMR_MR2
+#define  EXTI_IMR_IM3                        EXTI_IMR_MR3
+#define  EXTI_IMR_IM4                        EXTI_IMR_MR4
+#define  EXTI_IMR_IM5                        EXTI_IMR_MR5
+#define  EXTI_IMR_IM6                        EXTI_IMR_MR6
+#define  EXTI_IMR_IM7                        EXTI_IMR_MR7
+#define  EXTI_IMR_IM8                        EXTI_IMR_MR8
+#define  EXTI_IMR_IM9                        EXTI_IMR_MR9
+#define  EXTI_IMR_IM10                       EXTI_IMR_MR10
+#define  EXTI_IMR_IM11                       EXTI_IMR_MR11
+#define  EXTI_IMR_IM12                       EXTI_IMR_MR12
+#define  EXTI_IMR_IM13                       EXTI_IMR_MR13
+#define  EXTI_IMR_IM14                       EXTI_IMR_MR14
+#define  EXTI_IMR_IM15                       EXTI_IMR_MR15
+#define  EXTI_IMR_IM16                       EXTI_IMR_MR16
+#define  EXTI_IMR_IM17                       EXTI_IMR_MR17
+#define  EXTI_IMR_IM18                       EXTI_IMR_MR18
+#define  EXTI_IMR_IM19                       EXTI_IMR_MR19
+#define  EXTI_IMR_IM20                       EXTI_IMR_MR20
+#define  EXTI_IMR_IM21                       EXTI_IMR_MR21
+#define  EXTI_IMR_IM22                       EXTI_IMR_MR22
+#define EXTI_IMR_IM_Pos           (0U)                                         
+#define EXTI_IMR_IM_Msk           (0x7FFFFFUL << EXTI_IMR_IM_Pos)               /*!< 0x007FFFFF */
+#define EXTI_IMR_IM               EXTI_IMR_IM_Msk                              /*!< Interrupt Mask All */
+
+/*******************  Bit definition for EXTI_EMR register  *******************/
+#define EXTI_EMR_MR0_Pos          (0U)                                         
+#define EXTI_EMR_MR0_Msk          (0x1UL << EXTI_EMR_MR0_Pos)                   /*!< 0x00000001 */
+#define EXTI_EMR_MR0              EXTI_EMR_MR0_Msk                             /*!< Event Mask on line 0 */
+#define EXTI_EMR_MR1_Pos          (1U)                                         
+#define EXTI_EMR_MR1_Msk          (0x1UL << EXTI_EMR_MR1_Pos)                   /*!< 0x00000002 */
+#define EXTI_EMR_MR1              EXTI_EMR_MR1_Msk                             /*!< Event Mask on line 1 */
+#define EXTI_EMR_MR2_Pos          (2U)                                         
+#define EXTI_EMR_MR2_Msk          (0x1UL << EXTI_EMR_MR2_Pos)                   /*!< 0x00000004 */
+#define EXTI_EMR_MR2              EXTI_EMR_MR2_Msk                             /*!< Event Mask on line 2 */
+#define EXTI_EMR_MR3_Pos          (3U)                                         
+#define EXTI_EMR_MR3_Msk          (0x1UL << EXTI_EMR_MR3_Pos)                   /*!< 0x00000008 */
+#define EXTI_EMR_MR3              EXTI_EMR_MR3_Msk                             /*!< Event Mask on line 3 */
+#define EXTI_EMR_MR4_Pos          (4U)                                         
+#define EXTI_EMR_MR4_Msk          (0x1UL << EXTI_EMR_MR4_Pos)                   /*!< 0x00000010 */
+#define EXTI_EMR_MR4              EXTI_EMR_MR4_Msk                             /*!< Event Mask on line 4 */
+#define EXTI_EMR_MR5_Pos          (5U)                                         
+#define EXTI_EMR_MR5_Msk          (0x1UL << EXTI_EMR_MR5_Pos)                   /*!< 0x00000020 */
+#define EXTI_EMR_MR5              EXTI_EMR_MR5_Msk                             /*!< Event Mask on line 5 */
+#define EXTI_EMR_MR6_Pos          (6U)                                         
+#define EXTI_EMR_MR6_Msk          (0x1UL << EXTI_EMR_MR6_Pos)                   /*!< 0x00000040 */
+#define EXTI_EMR_MR6              EXTI_EMR_MR6_Msk                             /*!< Event Mask on line 6 */
+#define EXTI_EMR_MR7_Pos          (7U)                                         
+#define EXTI_EMR_MR7_Msk          (0x1UL << EXTI_EMR_MR7_Pos)                   /*!< 0x00000080 */
+#define EXTI_EMR_MR7              EXTI_EMR_MR7_Msk                             /*!< Event Mask on line 7 */
+#define EXTI_EMR_MR8_Pos          (8U)                                         
+#define EXTI_EMR_MR8_Msk          (0x1UL << EXTI_EMR_MR8_Pos)                   /*!< 0x00000100 */
+#define EXTI_EMR_MR8              EXTI_EMR_MR8_Msk                             /*!< Event Mask on line 8 */
+#define EXTI_EMR_MR9_Pos          (9U)                                         
+#define EXTI_EMR_MR9_Msk          (0x1UL << EXTI_EMR_MR9_Pos)                   /*!< 0x00000200 */
+#define EXTI_EMR_MR9              EXTI_EMR_MR9_Msk                             /*!< Event Mask on line 9 */
+#define EXTI_EMR_MR10_Pos         (10U)                                        
+#define EXTI_EMR_MR10_Msk         (0x1UL << EXTI_EMR_MR10_Pos)                  /*!< 0x00000400 */
+#define EXTI_EMR_MR10             EXTI_EMR_MR10_Msk                            /*!< Event Mask on line 10 */
+#define EXTI_EMR_MR11_Pos         (11U)                                        
+#define EXTI_EMR_MR11_Msk         (0x1UL << EXTI_EMR_MR11_Pos)                  /*!< 0x00000800 */
+#define EXTI_EMR_MR11             EXTI_EMR_MR11_Msk                            /*!< Event Mask on line 11 */
+#define EXTI_EMR_MR12_Pos         (12U)                                        
+#define EXTI_EMR_MR12_Msk         (0x1UL << EXTI_EMR_MR12_Pos)                  /*!< 0x00001000 */
+#define EXTI_EMR_MR12             EXTI_EMR_MR12_Msk                            /*!< Event Mask on line 12 */
+#define EXTI_EMR_MR13_Pos         (13U)                                        
+#define EXTI_EMR_MR13_Msk         (0x1UL << EXTI_EMR_MR13_Pos)                  /*!< 0x00002000 */
+#define EXTI_EMR_MR13             EXTI_EMR_MR13_Msk                            /*!< Event Mask on line 13 */
+#define EXTI_EMR_MR14_Pos         (14U)                                        
+#define EXTI_EMR_MR14_Msk         (0x1UL << EXTI_EMR_MR14_Pos)                  /*!< 0x00004000 */
+#define EXTI_EMR_MR14             EXTI_EMR_MR14_Msk                            /*!< Event Mask on line 14 */
+#define EXTI_EMR_MR15_Pos         (15U)                                        
+#define EXTI_EMR_MR15_Msk         (0x1UL << EXTI_EMR_MR15_Pos)                  /*!< 0x00008000 */
+#define EXTI_EMR_MR15             EXTI_EMR_MR15_Msk                            /*!< Event Mask on line 15 */
+#define EXTI_EMR_MR16_Pos         (16U)                                        
+#define EXTI_EMR_MR16_Msk         (0x1UL << EXTI_EMR_MR16_Pos)                  /*!< 0x00010000 */
+#define EXTI_EMR_MR16             EXTI_EMR_MR16_Msk                            /*!< Event Mask on line 16 */
+#define EXTI_EMR_MR17_Pos         (17U)                                        
+#define EXTI_EMR_MR17_Msk         (0x1UL << EXTI_EMR_MR17_Pos)                  /*!< 0x00020000 */
+#define EXTI_EMR_MR17             EXTI_EMR_MR17_Msk                            /*!< Event Mask on line 17 */
+#define EXTI_EMR_MR18_Pos         (18U)                                        
+#define EXTI_EMR_MR18_Msk         (0x1UL << EXTI_EMR_MR18_Pos)                  /*!< 0x00040000 */
+#define EXTI_EMR_MR18             EXTI_EMR_MR18_Msk                            /*!< Event Mask on line 18 */
+#define EXTI_EMR_MR19_Pos         (19U)                                        
+#define EXTI_EMR_MR19_Msk         (0x1UL << EXTI_EMR_MR19_Pos)                  /*!< 0x00080000 */
+#define EXTI_EMR_MR19             EXTI_EMR_MR19_Msk                            /*!< Event Mask on line 19 */
+#define EXTI_EMR_MR20_Pos         (20U)                                        
+#define EXTI_EMR_MR20_Msk         (0x1UL << EXTI_EMR_MR20_Pos)                  /*!< 0x00100000 */
+#define EXTI_EMR_MR20             EXTI_EMR_MR20_Msk                            /*!< Event Mask on line 20 */
+#define EXTI_EMR_MR21_Pos         (21U)                                        
+#define EXTI_EMR_MR21_Msk         (0x1UL << EXTI_EMR_MR21_Pos)                  /*!< 0x00200000 */
+#define EXTI_EMR_MR21             EXTI_EMR_MR21_Msk                            /*!< Event Mask on line 21 */
+#define EXTI_EMR_MR22_Pos         (22U)                                        
+#define EXTI_EMR_MR22_Msk         (0x1UL << EXTI_EMR_MR22_Pos)                  /*!< 0x00400000 */
+#define EXTI_EMR_MR22             EXTI_EMR_MR22_Msk                            /*!< Event Mask on line 22 */
+
+/* Reference Defines */
+#define  EXTI_EMR_EM0                        EXTI_EMR_MR0
+#define  EXTI_EMR_EM1                        EXTI_EMR_MR1
+#define  EXTI_EMR_EM2                        EXTI_EMR_MR2
+#define  EXTI_EMR_EM3                        EXTI_EMR_MR3
+#define  EXTI_EMR_EM4                        EXTI_EMR_MR4
+#define  EXTI_EMR_EM5                        EXTI_EMR_MR5
+#define  EXTI_EMR_EM6                        EXTI_EMR_MR6
+#define  EXTI_EMR_EM7                        EXTI_EMR_MR7
+#define  EXTI_EMR_EM8                        EXTI_EMR_MR8
+#define  EXTI_EMR_EM9                        EXTI_EMR_MR9
+#define  EXTI_EMR_EM10                       EXTI_EMR_MR10
+#define  EXTI_EMR_EM11                       EXTI_EMR_MR11
+#define  EXTI_EMR_EM12                       EXTI_EMR_MR12
+#define  EXTI_EMR_EM13                       EXTI_EMR_MR13
+#define  EXTI_EMR_EM14                       EXTI_EMR_MR14
+#define  EXTI_EMR_EM15                       EXTI_EMR_MR15
+#define  EXTI_EMR_EM16                       EXTI_EMR_MR16
+#define  EXTI_EMR_EM17                       EXTI_EMR_MR17
+#define  EXTI_EMR_EM18                       EXTI_EMR_MR18
+#define  EXTI_EMR_EM19                       EXTI_EMR_MR19
+#define  EXTI_EMR_EM20                       EXTI_EMR_MR20
+#define  EXTI_EMR_EM21                       EXTI_EMR_MR21
+#define  EXTI_EMR_EM22                       EXTI_EMR_MR22
+
+/******************  Bit definition for EXTI_RTSR register  *******************/
+#define EXTI_RTSR_TR0_Pos         (0U)                                         
+#define EXTI_RTSR_TR0_Msk         (0x1UL << EXTI_RTSR_TR0_Pos)                  /*!< 0x00000001 */
+#define EXTI_RTSR_TR0             EXTI_RTSR_TR0_Msk                            /*!< Rising trigger event configuration bit of line 0 */
+#define EXTI_RTSR_TR1_Pos         (1U)                                         
+#define EXTI_RTSR_TR1_Msk         (0x1UL << EXTI_RTSR_TR1_Pos)                  /*!< 0x00000002 */
+#define EXTI_RTSR_TR1             EXTI_RTSR_TR1_Msk                            /*!< Rising trigger event configuration bit of line 1 */
+#define EXTI_RTSR_TR2_Pos         (2U)                                         
+#define EXTI_RTSR_TR2_Msk         (0x1UL << EXTI_RTSR_TR2_Pos)                  /*!< 0x00000004 */
+#define EXTI_RTSR_TR2             EXTI_RTSR_TR2_Msk                            /*!< Rising trigger event configuration bit of line 2 */
+#define EXTI_RTSR_TR3_Pos         (3U)                                         
+#define EXTI_RTSR_TR3_Msk         (0x1UL << EXTI_RTSR_TR3_Pos)                  /*!< 0x00000008 */
+#define EXTI_RTSR_TR3             EXTI_RTSR_TR3_Msk                            /*!< Rising trigger event configuration bit of line 3 */
+#define EXTI_RTSR_TR4_Pos         (4U)                                         
+#define EXTI_RTSR_TR4_Msk         (0x1UL << EXTI_RTSR_TR4_Pos)                  /*!< 0x00000010 */
+#define EXTI_RTSR_TR4             EXTI_RTSR_TR4_Msk                            /*!< Rising trigger event configuration bit of line 4 */
+#define EXTI_RTSR_TR5_Pos         (5U)                                         
+#define EXTI_RTSR_TR5_Msk         (0x1UL << EXTI_RTSR_TR5_Pos)                  /*!< 0x00000020 */
+#define EXTI_RTSR_TR5             EXTI_RTSR_TR5_Msk                            /*!< Rising trigger event configuration bit of line 5 */
+#define EXTI_RTSR_TR6_Pos         (6U)                                         
+#define EXTI_RTSR_TR6_Msk         (0x1UL << EXTI_RTSR_TR6_Pos)                  /*!< 0x00000040 */
+#define EXTI_RTSR_TR6             EXTI_RTSR_TR6_Msk                            /*!< Rising trigger event configuration bit of line 6 */
+#define EXTI_RTSR_TR7_Pos         (7U)                                         
+#define EXTI_RTSR_TR7_Msk         (0x1UL << EXTI_RTSR_TR7_Pos)                  /*!< 0x00000080 */
+#define EXTI_RTSR_TR7             EXTI_RTSR_TR7_Msk                            /*!< Rising trigger event configuration bit of line 7 */
+#define EXTI_RTSR_TR8_Pos         (8U)                                         
+#define EXTI_RTSR_TR8_Msk         (0x1UL << EXTI_RTSR_TR8_Pos)                  /*!< 0x00000100 */
+#define EXTI_RTSR_TR8             EXTI_RTSR_TR8_Msk                            /*!< Rising trigger event configuration bit of line 8 */
+#define EXTI_RTSR_TR9_Pos         (9U)                                         
+#define EXTI_RTSR_TR9_Msk         (0x1UL << EXTI_RTSR_TR9_Pos)                  /*!< 0x00000200 */
+#define EXTI_RTSR_TR9             EXTI_RTSR_TR9_Msk                            /*!< Rising trigger event configuration bit of line 9 */
+#define EXTI_RTSR_TR10_Pos        (10U)                                        
+#define EXTI_RTSR_TR10_Msk        (0x1UL << EXTI_RTSR_TR10_Pos)                 /*!< 0x00000400 */
+#define EXTI_RTSR_TR10            EXTI_RTSR_TR10_Msk                           /*!< Rising trigger event configuration bit of line 10 */
+#define EXTI_RTSR_TR11_Pos        (11U)                                        
+#define EXTI_RTSR_TR11_Msk        (0x1UL << EXTI_RTSR_TR11_Pos)                 /*!< 0x00000800 */
+#define EXTI_RTSR_TR11            EXTI_RTSR_TR11_Msk                           /*!< Rising trigger event configuration bit of line 11 */
+#define EXTI_RTSR_TR12_Pos        (12U)                                        
+#define EXTI_RTSR_TR12_Msk        (0x1UL << EXTI_RTSR_TR12_Pos)                 /*!< 0x00001000 */
+#define EXTI_RTSR_TR12            EXTI_RTSR_TR12_Msk                           /*!< Rising trigger event configuration bit of line 12 */
+#define EXTI_RTSR_TR13_Pos        (13U)                                        
+#define EXTI_RTSR_TR13_Msk        (0x1UL << EXTI_RTSR_TR13_Pos)                 /*!< 0x00002000 */
+#define EXTI_RTSR_TR13            EXTI_RTSR_TR13_Msk                           /*!< Rising trigger event configuration bit of line 13 */
+#define EXTI_RTSR_TR14_Pos        (14U)                                        
+#define EXTI_RTSR_TR14_Msk        (0x1UL << EXTI_RTSR_TR14_Pos)                 /*!< 0x00004000 */
+#define EXTI_RTSR_TR14            EXTI_RTSR_TR14_Msk                           /*!< Rising trigger event configuration bit of line 14 */
+#define EXTI_RTSR_TR15_Pos        (15U)                                        
+#define EXTI_RTSR_TR15_Msk        (0x1UL << EXTI_RTSR_TR15_Pos)                 /*!< 0x00008000 */
+#define EXTI_RTSR_TR15            EXTI_RTSR_TR15_Msk                           /*!< Rising trigger event configuration bit of line 15 */
+#define EXTI_RTSR_TR16_Pos        (16U)                                        
+#define EXTI_RTSR_TR16_Msk        (0x1UL << EXTI_RTSR_TR16_Pos)                 /*!< 0x00010000 */
+#define EXTI_RTSR_TR16            EXTI_RTSR_TR16_Msk                           /*!< Rising trigger event configuration bit of line 16 */
+#define EXTI_RTSR_TR17_Pos        (17U)                                        
+#define EXTI_RTSR_TR17_Msk        (0x1UL << EXTI_RTSR_TR17_Pos)                 /*!< 0x00020000 */
+#define EXTI_RTSR_TR17            EXTI_RTSR_TR17_Msk                           /*!< Rising trigger event configuration bit of line 17 */
+#define EXTI_RTSR_TR18_Pos        (18U)                                        
+#define EXTI_RTSR_TR18_Msk        (0x1UL << EXTI_RTSR_TR18_Pos)                 /*!< 0x00040000 */
+#define EXTI_RTSR_TR18            EXTI_RTSR_TR18_Msk                           /*!< Rising trigger event configuration bit of line 18 */
+#define EXTI_RTSR_TR19_Pos        (19U)                                        
+#define EXTI_RTSR_TR19_Msk        (0x1UL << EXTI_RTSR_TR19_Pos)                 /*!< 0x00080000 */
+#define EXTI_RTSR_TR19            EXTI_RTSR_TR19_Msk                           /*!< Rising trigger event configuration bit of line 19 */
+#define EXTI_RTSR_TR20_Pos        (20U)                                        
+#define EXTI_RTSR_TR20_Msk        (0x1UL << EXTI_RTSR_TR20_Pos)                 /*!< 0x00100000 */
+#define EXTI_RTSR_TR20            EXTI_RTSR_TR20_Msk                           /*!< Rising trigger event configuration bit of line 20 */
+#define EXTI_RTSR_TR21_Pos        (21U)                                        
+#define EXTI_RTSR_TR21_Msk        (0x1UL << EXTI_RTSR_TR21_Pos)                 /*!< 0x00200000 */
+#define EXTI_RTSR_TR21            EXTI_RTSR_TR21_Msk                           /*!< Rising trigger event configuration bit of line 21 */
+#define EXTI_RTSR_TR22_Pos        (22U)                                        
+#define EXTI_RTSR_TR22_Msk        (0x1UL << EXTI_RTSR_TR22_Pos)                 /*!< 0x00400000 */
+#define EXTI_RTSR_TR22            EXTI_RTSR_TR22_Msk                           /*!< Rising trigger event configuration bit of line 22 */
+
+/******************  Bit definition for EXTI_FTSR register  *******************/
+#define EXTI_FTSR_TR0_Pos         (0U)                                         
+#define EXTI_FTSR_TR0_Msk         (0x1UL << EXTI_FTSR_TR0_Pos)                  /*!< 0x00000001 */
+#define EXTI_FTSR_TR0             EXTI_FTSR_TR0_Msk                            /*!< Falling trigger event configuration bit of line 0 */
+#define EXTI_FTSR_TR1_Pos         (1U)                                         
+#define EXTI_FTSR_TR1_Msk         (0x1UL << EXTI_FTSR_TR1_Pos)                  /*!< 0x00000002 */
+#define EXTI_FTSR_TR1             EXTI_FTSR_TR1_Msk                            /*!< Falling trigger event configuration bit of line 1 */
+#define EXTI_FTSR_TR2_Pos         (2U)                                         
+#define EXTI_FTSR_TR2_Msk         (0x1UL << EXTI_FTSR_TR2_Pos)                  /*!< 0x00000004 */
+#define EXTI_FTSR_TR2             EXTI_FTSR_TR2_Msk                            /*!< Falling trigger event configuration bit of line 2 */
+#define EXTI_FTSR_TR3_Pos         (3U)                                         
+#define EXTI_FTSR_TR3_Msk         (0x1UL << EXTI_FTSR_TR3_Pos)                  /*!< 0x00000008 */
+#define EXTI_FTSR_TR3             EXTI_FTSR_TR3_Msk                            /*!< Falling trigger event configuration bit of line 3 */
+#define EXTI_FTSR_TR4_Pos         (4U)                                         
+#define EXTI_FTSR_TR4_Msk         (0x1UL << EXTI_FTSR_TR4_Pos)                  /*!< 0x00000010 */
+#define EXTI_FTSR_TR4             EXTI_FTSR_TR4_Msk                            /*!< Falling trigger event configuration bit of line 4 */
+#define EXTI_FTSR_TR5_Pos         (5U)                                         
+#define EXTI_FTSR_TR5_Msk         (0x1UL << EXTI_FTSR_TR5_Pos)                  /*!< 0x00000020 */
+#define EXTI_FTSR_TR5             EXTI_FTSR_TR5_Msk                            /*!< Falling trigger event configuration bit of line 5 */
+#define EXTI_FTSR_TR6_Pos         (6U)                                         
+#define EXTI_FTSR_TR6_Msk         (0x1UL << EXTI_FTSR_TR6_Pos)                  /*!< 0x00000040 */
+#define EXTI_FTSR_TR6             EXTI_FTSR_TR6_Msk                            /*!< Falling trigger event configuration bit of line 6 */
+#define EXTI_FTSR_TR7_Pos         (7U)                                         
+#define EXTI_FTSR_TR7_Msk         (0x1UL << EXTI_FTSR_TR7_Pos)                  /*!< 0x00000080 */
+#define EXTI_FTSR_TR7             EXTI_FTSR_TR7_Msk                            /*!< Falling trigger event configuration bit of line 7 */
+#define EXTI_FTSR_TR8_Pos         (8U)                                         
+#define EXTI_FTSR_TR8_Msk         (0x1UL << EXTI_FTSR_TR8_Pos)                  /*!< 0x00000100 */
+#define EXTI_FTSR_TR8             EXTI_FTSR_TR8_Msk                            /*!< Falling trigger event configuration bit of line 8 */
+#define EXTI_FTSR_TR9_Pos         (9U)                                         
+#define EXTI_FTSR_TR9_Msk         (0x1UL << EXTI_FTSR_TR9_Pos)                  /*!< 0x00000200 */
+#define EXTI_FTSR_TR9             EXTI_FTSR_TR9_Msk                            /*!< Falling trigger event configuration bit of line 9 */
+#define EXTI_FTSR_TR10_Pos        (10U)                                        
+#define EXTI_FTSR_TR10_Msk        (0x1UL << EXTI_FTSR_TR10_Pos)                 /*!< 0x00000400 */
+#define EXTI_FTSR_TR10            EXTI_FTSR_TR10_Msk                           /*!< Falling trigger event configuration bit of line 10 */
+#define EXTI_FTSR_TR11_Pos        (11U)                                        
+#define EXTI_FTSR_TR11_Msk        (0x1UL << EXTI_FTSR_TR11_Pos)                 /*!< 0x00000800 */
+#define EXTI_FTSR_TR11            EXTI_FTSR_TR11_Msk                           /*!< Falling trigger event configuration bit of line 11 */
+#define EXTI_FTSR_TR12_Pos        (12U)                                        
+#define EXTI_FTSR_TR12_Msk        (0x1UL << EXTI_FTSR_TR12_Pos)                 /*!< 0x00001000 */
+#define EXTI_FTSR_TR12            EXTI_FTSR_TR12_Msk                           /*!< Falling trigger event configuration bit of line 12 */
+#define EXTI_FTSR_TR13_Pos        (13U)                                        
+#define EXTI_FTSR_TR13_Msk        (0x1UL << EXTI_FTSR_TR13_Pos)                 /*!< 0x00002000 */
+#define EXTI_FTSR_TR13            EXTI_FTSR_TR13_Msk                           /*!< Falling trigger event configuration bit of line 13 */
+#define EXTI_FTSR_TR14_Pos        (14U)                                        
+#define EXTI_FTSR_TR14_Msk        (0x1UL << EXTI_FTSR_TR14_Pos)                 /*!< 0x00004000 */
+#define EXTI_FTSR_TR14            EXTI_FTSR_TR14_Msk                           /*!< Falling trigger event configuration bit of line 14 */
+#define EXTI_FTSR_TR15_Pos        (15U)                                        
+#define EXTI_FTSR_TR15_Msk        (0x1UL << EXTI_FTSR_TR15_Pos)                 /*!< 0x00008000 */
+#define EXTI_FTSR_TR15            EXTI_FTSR_TR15_Msk                           /*!< Falling trigger event configuration bit of line 15 */
+#define EXTI_FTSR_TR16_Pos        (16U)                                        
+#define EXTI_FTSR_TR16_Msk        (0x1UL << EXTI_FTSR_TR16_Pos)                 /*!< 0x00010000 */
+#define EXTI_FTSR_TR16            EXTI_FTSR_TR16_Msk                           /*!< Falling trigger event configuration bit of line 16 */
+#define EXTI_FTSR_TR17_Pos        (17U)                                        
+#define EXTI_FTSR_TR17_Msk        (0x1UL << EXTI_FTSR_TR17_Pos)                 /*!< 0x00020000 */
+#define EXTI_FTSR_TR17            EXTI_FTSR_TR17_Msk                           /*!< Falling trigger event configuration bit of line 17 */
+#define EXTI_FTSR_TR18_Pos        (18U)                                        
+#define EXTI_FTSR_TR18_Msk        (0x1UL << EXTI_FTSR_TR18_Pos)                 /*!< 0x00040000 */
+#define EXTI_FTSR_TR18            EXTI_FTSR_TR18_Msk                           /*!< Falling trigger event configuration bit of line 18 */
+#define EXTI_FTSR_TR19_Pos        (19U)                                        
+#define EXTI_FTSR_TR19_Msk        (0x1UL << EXTI_FTSR_TR19_Pos)                 /*!< 0x00080000 */
+#define EXTI_FTSR_TR19            EXTI_FTSR_TR19_Msk                           /*!< Falling trigger event configuration bit of line 19 */
+#define EXTI_FTSR_TR20_Pos        (20U)                                        
+#define EXTI_FTSR_TR20_Msk        (0x1UL << EXTI_FTSR_TR20_Pos)                 /*!< 0x00100000 */
+#define EXTI_FTSR_TR20            EXTI_FTSR_TR20_Msk                           /*!< Falling trigger event configuration bit of line 20 */
+#define EXTI_FTSR_TR21_Pos        (21U)                                        
+#define EXTI_FTSR_TR21_Msk        (0x1UL << EXTI_FTSR_TR21_Pos)                 /*!< 0x00200000 */
+#define EXTI_FTSR_TR21            EXTI_FTSR_TR21_Msk                           /*!< Falling trigger event configuration bit of line 21 */
+#define EXTI_FTSR_TR22_Pos        (22U)                                        
+#define EXTI_FTSR_TR22_Msk        (0x1UL << EXTI_FTSR_TR22_Pos)                 /*!< 0x00400000 */
+#define EXTI_FTSR_TR22            EXTI_FTSR_TR22_Msk                           /*!< Falling trigger event configuration bit of line 22 */
+
+/******************  Bit definition for EXTI_SWIER register  ******************/
+#define EXTI_SWIER_SWIER0_Pos     (0U)                                         
+#define EXTI_SWIER_SWIER0_Msk     (0x1UL << EXTI_SWIER_SWIER0_Pos)              /*!< 0x00000001 */
+#define EXTI_SWIER_SWIER0         EXTI_SWIER_SWIER0_Msk                        /*!< Software Interrupt on line 0 */
+#define EXTI_SWIER_SWIER1_Pos     (1U)                                         
+#define EXTI_SWIER_SWIER1_Msk     (0x1UL << EXTI_SWIER_SWIER1_Pos)              /*!< 0x00000002 */
+#define EXTI_SWIER_SWIER1         EXTI_SWIER_SWIER1_Msk                        /*!< Software Interrupt on line 1 */
+#define EXTI_SWIER_SWIER2_Pos     (2U)                                         
+#define EXTI_SWIER_SWIER2_Msk     (0x1UL << EXTI_SWIER_SWIER2_Pos)              /*!< 0x00000004 */
+#define EXTI_SWIER_SWIER2         EXTI_SWIER_SWIER2_Msk                        /*!< Software Interrupt on line 2 */
+#define EXTI_SWIER_SWIER3_Pos     (3U)                                         
+#define EXTI_SWIER_SWIER3_Msk     (0x1UL << EXTI_SWIER_SWIER3_Pos)              /*!< 0x00000008 */
+#define EXTI_SWIER_SWIER3         EXTI_SWIER_SWIER3_Msk                        /*!< Software Interrupt on line 3 */
+#define EXTI_SWIER_SWIER4_Pos     (4U)                                         
+#define EXTI_SWIER_SWIER4_Msk     (0x1UL << EXTI_SWIER_SWIER4_Pos)              /*!< 0x00000010 */
+#define EXTI_SWIER_SWIER4         EXTI_SWIER_SWIER4_Msk                        /*!< Software Interrupt on line 4 */
+#define EXTI_SWIER_SWIER5_Pos     (5U)                                         
+#define EXTI_SWIER_SWIER5_Msk     (0x1UL << EXTI_SWIER_SWIER5_Pos)              /*!< 0x00000020 */
+#define EXTI_SWIER_SWIER5         EXTI_SWIER_SWIER5_Msk                        /*!< Software Interrupt on line 5 */
+#define EXTI_SWIER_SWIER6_Pos     (6U)                                         
+#define EXTI_SWIER_SWIER6_Msk     (0x1UL << EXTI_SWIER_SWIER6_Pos)              /*!< 0x00000040 */
+#define EXTI_SWIER_SWIER6         EXTI_SWIER_SWIER6_Msk                        /*!< Software Interrupt on line 6 */
+#define EXTI_SWIER_SWIER7_Pos     (7U)                                         
+#define EXTI_SWIER_SWIER7_Msk     (0x1UL << EXTI_SWIER_SWIER7_Pos)              /*!< 0x00000080 */
+#define EXTI_SWIER_SWIER7         EXTI_SWIER_SWIER7_Msk                        /*!< Software Interrupt on line 7 */
+#define EXTI_SWIER_SWIER8_Pos     (8U)                                         
+#define EXTI_SWIER_SWIER8_Msk     (0x1UL << EXTI_SWIER_SWIER8_Pos)              /*!< 0x00000100 */
+#define EXTI_SWIER_SWIER8         EXTI_SWIER_SWIER8_Msk                        /*!< Software Interrupt on line 8 */
+#define EXTI_SWIER_SWIER9_Pos     (9U)                                         
+#define EXTI_SWIER_SWIER9_Msk     (0x1UL << EXTI_SWIER_SWIER9_Pos)              /*!< 0x00000200 */
+#define EXTI_SWIER_SWIER9         EXTI_SWIER_SWIER9_Msk                        /*!< Software Interrupt on line 9 */
+#define EXTI_SWIER_SWIER10_Pos    (10U)                                        
+#define EXTI_SWIER_SWIER10_Msk    (0x1UL << EXTI_SWIER_SWIER10_Pos)             /*!< 0x00000400 */
+#define EXTI_SWIER_SWIER10        EXTI_SWIER_SWIER10_Msk                       /*!< Software Interrupt on line 10 */
+#define EXTI_SWIER_SWIER11_Pos    (11U)                                        
+#define EXTI_SWIER_SWIER11_Msk    (0x1UL << EXTI_SWIER_SWIER11_Pos)             /*!< 0x00000800 */
+#define EXTI_SWIER_SWIER11        EXTI_SWIER_SWIER11_Msk                       /*!< Software Interrupt on line 11 */
+#define EXTI_SWIER_SWIER12_Pos    (12U)                                        
+#define EXTI_SWIER_SWIER12_Msk    (0x1UL << EXTI_SWIER_SWIER12_Pos)             /*!< 0x00001000 */
+#define EXTI_SWIER_SWIER12        EXTI_SWIER_SWIER12_Msk                       /*!< Software Interrupt on line 12 */
+#define EXTI_SWIER_SWIER13_Pos    (13U)                                        
+#define EXTI_SWIER_SWIER13_Msk    (0x1UL << EXTI_SWIER_SWIER13_Pos)             /*!< 0x00002000 */
+#define EXTI_SWIER_SWIER13        EXTI_SWIER_SWIER13_Msk                       /*!< Software Interrupt on line 13 */
+#define EXTI_SWIER_SWIER14_Pos    (14U)                                        
+#define EXTI_SWIER_SWIER14_Msk    (0x1UL << EXTI_SWIER_SWIER14_Pos)             /*!< 0x00004000 */
+#define EXTI_SWIER_SWIER14        EXTI_SWIER_SWIER14_Msk                       /*!< Software Interrupt on line 14 */
+#define EXTI_SWIER_SWIER15_Pos    (15U)                                        
+#define EXTI_SWIER_SWIER15_Msk    (0x1UL << EXTI_SWIER_SWIER15_Pos)             /*!< 0x00008000 */
+#define EXTI_SWIER_SWIER15        EXTI_SWIER_SWIER15_Msk                       /*!< Software Interrupt on line 15 */
+#define EXTI_SWIER_SWIER16_Pos    (16U)                                        
+#define EXTI_SWIER_SWIER16_Msk    (0x1UL << EXTI_SWIER_SWIER16_Pos)             /*!< 0x00010000 */
+#define EXTI_SWIER_SWIER16        EXTI_SWIER_SWIER16_Msk                       /*!< Software Interrupt on line 16 */
+#define EXTI_SWIER_SWIER17_Pos    (17U)                                        
+#define EXTI_SWIER_SWIER17_Msk    (0x1UL << EXTI_SWIER_SWIER17_Pos)             /*!< 0x00020000 */
+#define EXTI_SWIER_SWIER17        EXTI_SWIER_SWIER17_Msk                       /*!< Software Interrupt on line 17 */
+#define EXTI_SWIER_SWIER18_Pos    (18U)                                        
+#define EXTI_SWIER_SWIER18_Msk    (0x1UL << EXTI_SWIER_SWIER18_Pos)             /*!< 0x00040000 */
+#define EXTI_SWIER_SWIER18        EXTI_SWIER_SWIER18_Msk                       /*!< Software Interrupt on line 18 */
+#define EXTI_SWIER_SWIER19_Pos    (19U)                                        
+#define EXTI_SWIER_SWIER19_Msk    (0x1UL << EXTI_SWIER_SWIER19_Pos)             /*!< 0x00080000 */
+#define EXTI_SWIER_SWIER19        EXTI_SWIER_SWIER19_Msk                       /*!< Software Interrupt on line 19 */
+#define EXTI_SWIER_SWIER20_Pos    (20U)                                        
+#define EXTI_SWIER_SWIER20_Msk    (0x1UL << EXTI_SWIER_SWIER20_Pos)             /*!< 0x00100000 */
+#define EXTI_SWIER_SWIER20        EXTI_SWIER_SWIER20_Msk                       /*!< Software Interrupt on line 20 */
+#define EXTI_SWIER_SWIER21_Pos    (21U)                                        
+#define EXTI_SWIER_SWIER21_Msk    (0x1UL << EXTI_SWIER_SWIER21_Pos)             /*!< 0x00200000 */
+#define EXTI_SWIER_SWIER21        EXTI_SWIER_SWIER21_Msk                       /*!< Software Interrupt on line 21 */
+#define EXTI_SWIER_SWIER22_Pos    (22U)                                        
+#define EXTI_SWIER_SWIER22_Msk    (0x1UL << EXTI_SWIER_SWIER22_Pos)             /*!< 0x00400000 */
+#define EXTI_SWIER_SWIER22        EXTI_SWIER_SWIER22_Msk                       /*!< Software Interrupt on line 22 */
+
+/*******************  Bit definition for EXTI_PR register  ********************/
+#define EXTI_PR_PR0_Pos           (0U)                                         
+#define EXTI_PR_PR0_Msk           (0x1UL << EXTI_PR_PR0_Pos)                    /*!< 0x00000001 */
+#define EXTI_PR_PR0               EXTI_PR_PR0_Msk                              /*!< Pending bit for line 0 */
+#define EXTI_PR_PR1_Pos           (1U)                                         
+#define EXTI_PR_PR1_Msk           (0x1UL << EXTI_PR_PR1_Pos)                    /*!< 0x00000002 */
+#define EXTI_PR_PR1               EXTI_PR_PR1_Msk                              /*!< Pending bit for line 1 */
+#define EXTI_PR_PR2_Pos           (2U)                                         
+#define EXTI_PR_PR2_Msk           (0x1UL << EXTI_PR_PR2_Pos)                    /*!< 0x00000004 */
+#define EXTI_PR_PR2               EXTI_PR_PR2_Msk                              /*!< Pending bit for line 2 */
+#define EXTI_PR_PR3_Pos           (3U)                                         
+#define EXTI_PR_PR3_Msk           (0x1UL << EXTI_PR_PR3_Pos)                    /*!< 0x00000008 */
+#define EXTI_PR_PR3               EXTI_PR_PR3_Msk                              /*!< Pending bit for line 3 */
+#define EXTI_PR_PR4_Pos           (4U)                                         
+#define EXTI_PR_PR4_Msk           (0x1UL << EXTI_PR_PR4_Pos)                    /*!< 0x00000010 */
+#define EXTI_PR_PR4               EXTI_PR_PR4_Msk                              /*!< Pending bit for line 4 */
+#define EXTI_PR_PR5_Pos           (5U)                                         
+#define EXTI_PR_PR5_Msk           (0x1UL << EXTI_PR_PR5_Pos)                    /*!< 0x00000020 */
+#define EXTI_PR_PR5               EXTI_PR_PR5_Msk                              /*!< Pending bit for line 5 */
+#define EXTI_PR_PR6_Pos           (6U)                                         
+#define EXTI_PR_PR6_Msk           (0x1UL << EXTI_PR_PR6_Pos)                    /*!< 0x00000040 */
+#define EXTI_PR_PR6               EXTI_PR_PR6_Msk                              /*!< Pending bit for line 6 */
+#define EXTI_PR_PR7_Pos           (7U)                                         
+#define EXTI_PR_PR7_Msk           (0x1UL << EXTI_PR_PR7_Pos)                    /*!< 0x00000080 */
+#define EXTI_PR_PR7               EXTI_PR_PR7_Msk                              /*!< Pending bit for line 7 */
+#define EXTI_PR_PR8_Pos           (8U)                                         
+#define EXTI_PR_PR8_Msk           (0x1UL << EXTI_PR_PR8_Pos)                    /*!< 0x00000100 */
+#define EXTI_PR_PR8               EXTI_PR_PR8_Msk                              /*!< Pending bit for line 8 */
+#define EXTI_PR_PR9_Pos           (9U)                                         
+#define EXTI_PR_PR9_Msk           (0x1UL << EXTI_PR_PR9_Pos)                    /*!< 0x00000200 */
+#define EXTI_PR_PR9               EXTI_PR_PR9_Msk                              /*!< Pending bit for line 9 */
+#define EXTI_PR_PR10_Pos          (10U)                                        
+#define EXTI_PR_PR10_Msk          (0x1UL << EXTI_PR_PR10_Pos)                   /*!< 0x00000400 */
+#define EXTI_PR_PR10              EXTI_PR_PR10_Msk                             /*!< Pending bit for line 10 */
+#define EXTI_PR_PR11_Pos          (11U)                                        
+#define EXTI_PR_PR11_Msk          (0x1UL << EXTI_PR_PR11_Pos)                   /*!< 0x00000800 */
+#define EXTI_PR_PR11              EXTI_PR_PR11_Msk                             /*!< Pending bit for line 11 */
+#define EXTI_PR_PR12_Pos          (12U)                                        
+#define EXTI_PR_PR12_Msk          (0x1UL << EXTI_PR_PR12_Pos)                   /*!< 0x00001000 */
+#define EXTI_PR_PR12              EXTI_PR_PR12_Msk                             /*!< Pending bit for line 12 */
+#define EXTI_PR_PR13_Pos          (13U)                                        
+#define EXTI_PR_PR13_Msk          (0x1UL << EXTI_PR_PR13_Pos)                   /*!< 0x00002000 */
+#define EXTI_PR_PR13              EXTI_PR_PR13_Msk                             /*!< Pending bit for line 13 */
+#define EXTI_PR_PR14_Pos          (14U)                                        
+#define EXTI_PR_PR14_Msk          (0x1UL << EXTI_PR_PR14_Pos)                   /*!< 0x00004000 */
+#define EXTI_PR_PR14              EXTI_PR_PR14_Msk                             /*!< Pending bit for line 14 */
+#define EXTI_PR_PR15_Pos          (15U)                                        
+#define EXTI_PR_PR15_Msk          (0x1UL << EXTI_PR_PR15_Pos)                   /*!< 0x00008000 */
+#define EXTI_PR_PR15              EXTI_PR_PR15_Msk                             /*!< Pending bit for line 15 */
+#define EXTI_PR_PR16_Pos          (16U)                                        
+#define EXTI_PR_PR16_Msk          (0x1UL << EXTI_PR_PR16_Pos)                   /*!< 0x00010000 */
+#define EXTI_PR_PR16              EXTI_PR_PR16_Msk                             /*!< Pending bit for line 16 */
+#define EXTI_PR_PR17_Pos          (17U)                                        
+#define EXTI_PR_PR17_Msk          (0x1UL << EXTI_PR_PR17_Pos)                   /*!< 0x00020000 */
+#define EXTI_PR_PR17              EXTI_PR_PR17_Msk                             /*!< Pending bit for line 17 */
+#define EXTI_PR_PR18_Pos          (18U)                                        
+#define EXTI_PR_PR18_Msk          (0x1UL << EXTI_PR_PR18_Pos)                   /*!< 0x00040000 */
+#define EXTI_PR_PR18              EXTI_PR_PR18_Msk                             /*!< Pending bit for line 18 */
+#define EXTI_PR_PR19_Pos          (19U)                                        
+#define EXTI_PR_PR19_Msk          (0x1UL << EXTI_PR_PR19_Pos)                   /*!< 0x00080000 */
+#define EXTI_PR_PR19              EXTI_PR_PR19_Msk                             /*!< Pending bit for line 19 */
+#define EXTI_PR_PR20_Pos          (20U)                                        
+#define EXTI_PR_PR20_Msk          (0x1UL << EXTI_PR_PR20_Pos)                   /*!< 0x00100000 */
+#define EXTI_PR_PR20              EXTI_PR_PR20_Msk                             /*!< Pending bit for line 20 */
+#define EXTI_PR_PR21_Pos          (21U)                                        
+#define EXTI_PR_PR21_Msk          (0x1UL << EXTI_PR_PR21_Pos)                   /*!< 0x00200000 */
+#define EXTI_PR_PR21              EXTI_PR_PR21_Msk                             /*!< Pending bit for line 21 */
+#define EXTI_PR_PR22_Pos          (22U)                                        
+#define EXTI_PR_PR22_Msk          (0x1UL << EXTI_PR_PR22_Pos)                   /*!< 0x00400000 */
+#define EXTI_PR_PR22              EXTI_PR_PR22_Msk                             /*!< Pending bit for line 22 */
+
+/******************************************************************************/
+/*                                                                            */
+/*                                    FLASH                                   */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bits definition for FLASH_ACR register  *****************/
+#define FLASH_ACR_LATENCY_Pos          (0U)
+#define FLASH_ACR_LATENCY_Msk          (0xFUL << FLASH_ACR_LATENCY_Pos)         /*!< 0x0000000F */
+#define FLASH_ACR_LATENCY              FLASH_ACR_LATENCY_Msk
+#define FLASH_ACR_LATENCY_0WS          0x00000000U
+#define FLASH_ACR_LATENCY_1WS          0x00000001U
+#define FLASH_ACR_LATENCY_2WS          0x00000002U
+#define FLASH_ACR_LATENCY_3WS          0x00000003U
+#define FLASH_ACR_LATENCY_4WS          0x00000004U
+#define FLASH_ACR_LATENCY_5WS          0x00000005U
+#define FLASH_ACR_LATENCY_6WS          0x00000006U
+#define FLASH_ACR_LATENCY_7WS          0x00000007U
+
+#define FLASH_ACR_LATENCY_8WS          0x00000008U
+#define FLASH_ACR_LATENCY_9WS          0x00000009U
+#define FLASH_ACR_LATENCY_10WS         0x0000000AU
+#define FLASH_ACR_LATENCY_11WS         0x0000000BU
+#define FLASH_ACR_LATENCY_12WS         0x0000000CU
+#define FLASH_ACR_LATENCY_13WS         0x0000000DU
+#define FLASH_ACR_LATENCY_14WS         0x0000000EU
+#define FLASH_ACR_LATENCY_15WS         0x0000000FU
+
+#define FLASH_ACR_PRFTEN_Pos           (8U)                                    
+#define FLASH_ACR_PRFTEN_Msk           (0x1UL << FLASH_ACR_PRFTEN_Pos)          /*!< 0x00000100 */
+#define FLASH_ACR_PRFTEN               FLASH_ACR_PRFTEN_Msk                    
+#define FLASH_ACR_ICEN_Pos             (9U)                                    
+#define FLASH_ACR_ICEN_Msk             (0x1UL << FLASH_ACR_ICEN_Pos)            /*!< 0x00000200 */
+#define FLASH_ACR_ICEN                 FLASH_ACR_ICEN_Msk                      
+#define FLASH_ACR_DCEN_Pos             (10U)                                   
+#define FLASH_ACR_DCEN_Msk             (0x1UL << FLASH_ACR_DCEN_Pos)            /*!< 0x00000400 */
+#define FLASH_ACR_DCEN                 FLASH_ACR_DCEN_Msk                      
+#define FLASH_ACR_ICRST_Pos            (11U)                                   
+#define FLASH_ACR_ICRST_Msk            (0x1UL << FLASH_ACR_ICRST_Pos)           /*!< 0x00000800 */
+#define FLASH_ACR_ICRST                FLASH_ACR_ICRST_Msk                     
+#define FLASH_ACR_DCRST_Pos            (12U)                                   
+#define FLASH_ACR_DCRST_Msk            (0x1UL << FLASH_ACR_DCRST_Pos)           /*!< 0x00001000 */
+#define FLASH_ACR_DCRST                FLASH_ACR_DCRST_Msk                     
+#define FLASH_ACR_BYTE0_ADDRESS_Pos    (10U)                                   
+#define FLASH_ACR_BYTE0_ADDRESS_Msk    (0x10008FUL << FLASH_ACR_BYTE0_ADDRESS_Pos) /*!< 0x40023C00 */
+#define FLASH_ACR_BYTE0_ADDRESS        FLASH_ACR_BYTE0_ADDRESS_Msk             
+#define FLASH_ACR_BYTE2_ADDRESS_Pos    (0U)                                    
+#define FLASH_ACR_BYTE2_ADDRESS_Msk    (0x40023C03UL << FLASH_ACR_BYTE2_ADDRESS_Pos) /*!< 0x40023C03 */
+#define FLASH_ACR_BYTE2_ADDRESS        FLASH_ACR_BYTE2_ADDRESS_Msk             
+
+/*******************  Bits definition for FLASH_SR register  ******************/
+#define FLASH_SR_EOP_Pos               (0U)                                    
+#define FLASH_SR_EOP_Msk               (0x1UL << FLASH_SR_EOP_Pos)              /*!< 0x00000001 */
+#define FLASH_SR_EOP                   FLASH_SR_EOP_Msk                        
+#define FLASH_SR_SOP_Pos               (1U)                                    
+#define FLASH_SR_SOP_Msk               (0x1UL << FLASH_SR_SOP_Pos)              /*!< 0x00000002 */
+#define FLASH_SR_SOP                   FLASH_SR_SOP_Msk                        
+#define FLASH_SR_WRPERR_Pos            (4U)                                    
+#define FLASH_SR_WRPERR_Msk            (0x1UL << FLASH_SR_WRPERR_Pos)           /*!< 0x00000010 */
+#define FLASH_SR_WRPERR                FLASH_SR_WRPERR_Msk                     
+#define FLASH_SR_PGAERR_Pos            (5U)                                    
+#define FLASH_SR_PGAERR_Msk            (0x1UL << FLASH_SR_PGAERR_Pos)           /*!< 0x00000020 */
+#define FLASH_SR_PGAERR                FLASH_SR_PGAERR_Msk                     
+#define FLASH_SR_PGPERR_Pos            (6U)                                    
+#define FLASH_SR_PGPERR_Msk            (0x1UL << FLASH_SR_PGPERR_Pos)           /*!< 0x00000040 */
+#define FLASH_SR_PGPERR                FLASH_SR_PGPERR_Msk                     
+#define FLASH_SR_PGSERR_Pos            (7U)                                    
+#define FLASH_SR_PGSERR_Msk            (0x1UL << FLASH_SR_PGSERR_Pos)           /*!< 0x00000080 */
+#define FLASH_SR_PGSERR                FLASH_SR_PGSERR_Msk                     
+#define FLASH_SR_RDERR_Pos            (8U)                                    
+#define FLASH_SR_RDERR_Msk            (0x1UL << FLASH_SR_RDERR_Pos)             /*!< 0x00000100 */
+#define FLASH_SR_RDERR                FLASH_SR_RDERR_Msk                     
+#define FLASH_SR_BSY_Pos               (16U)                                   
+#define FLASH_SR_BSY_Msk               (0x1UL << FLASH_SR_BSY_Pos)              /*!< 0x00010000 */
+#define FLASH_SR_BSY                   FLASH_SR_BSY_Msk                        
+
+/*******************  Bits definition for FLASH_CR register  ******************/
+#define FLASH_CR_PG_Pos                (0U)                                    
+#define FLASH_CR_PG_Msk                (0x1UL << FLASH_CR_PG_Pos)               /*!< 0x00000001 */
+#define FLASH_CR_PG                    FLASH_CR_PG_Msk                         
+#define FLASH_CR_SER_Pos               (1U)                                    
+#define FLASH_CR_SER_Msk               (0x1UL << FLASH_CR_SER_Pos)              /*!< 0x00000002 */
+#define FLASH_CR_SER                   FLASH_CR_SER_Msk                        
+#define FLASH_CR_MER_Pos               (2U)                                    
+#define FLASH_CR_MER_Msk               (0x1UL << FLASH_CR_MER_Pos)              /*!< 0x00000004 */
+#define FLASH_CR_MER                   FLASH_CR_MER_Msk                        
+#define FLASH_CR_MER1                        FLASH_CR_MER
+#define FLASH_CR_SNB_Pos               (3U)                                    
+#define FLASH_CR_SNB_Msk               (0x1FUL << FLASH_CR_SNB_Pos)             /*!< 0x000000F8 */
+#define FLASH_CR_SNB                   FLASH_CR_SNB_Msk                        
+#define FLASH_CR_SNB_0                 (0x01UL << FLASH_CR_SNB_Pos)             /*!< 0x00000008 */
+#define FLASH_CR_SNB_1                 (0x02UL << FLASH_CR_SNB_Pos)             /*!< 0x00000010 */
+#define FLASH_CR_SNB_2                 (0x04UL << FLASH_CR_SNB_Pos)             /*!< 0x00000020 */
+#define FLASH_CR_SNB_3                 (0x08UL << FLASH_CR_SNB_Pos)             /*!< 0x00000040 */
+#define FLASH_CR_SNB_4                 (0x10UL << FLASH_CR_SNB_Pos)             /*!< 0x00000080 */
+#define FLASH_CR_PSIZE_Pos             (8U)                                    
+#define FLASH_CR_PSIZE_Msk             (0x3UL << FLASH_CR_PSIZE_Pos)            /*!< 0x00000300 */
+#define FLASH_CR_PSIZE                 FLASH_CR_PSIZE_Msk                      
+#define FLASH_CR_PSIZE_0               (0x1UL << FLASH_CR_PSIZE_Pos)            /*!< 0x00000100 */
+#define FLASH_CR_PSIZE_1               (0x2UL << FLASH_CR_PSIZE_Pos)            /*!< 0x00000200 */
+#define FLASH_CR_MER2_Pos              (15U)                                   
+#define FLASH_CR_MER2_Msk              (0x1UL << FLASH_CR_MER2_Pos)             /*!< 0x00008000 */
+#define FLASH_CR_MER2                  FLASH_CR_MER2_Msk                       
+#define FLASH_CR_STRT_Pos              (16U)                                   
+#define FLASH_CR_STRT_Msk              (0x1UL << FLASH_CR_STRT_Pos)             /*!< 0x00010000 */
+#define FLASH_CR_STRT                  FLASH_CR_STRT_Msk                       
+#define FLASH_CR_EOPIE_Pos             (24U)                                   
+#define FLASH_CR_EOPIE_Msk             (0x1UL << FLASH_CR_EOPIE_Pos)            /*!< 0x01000000 */
+#define FLASH_CR_EOPIE                 FLASH_CR_EOPIE_Msk                      
+#define FLASH_CR_ERRIE_Pos             (25U)
+#define FLASH_CR_ERRIE_Msk             (0x1UL << FLASH_CR_ERRIE_Pos)
+#define FLASH_CR_ERRIE                 FLASH_CR_ERRIE_Msk
+#define FLASH_CR_LOCK_Pos              (31U)                                   
+#define FLASH_CR_LOCK_Msk              (0x1UL << FLASH_CR_LOCK_Pos)             /*!< 0x80000000 */
+#define FLASH_CR_LOCK                  FLASH_CR_LOCK_Msk                       
+
+/*******************  Bits definition for FLASH_OPTCR register  ***************/
+#define FLASH_OPTCR_OPTLOCK_Pos        (0U)                                    
+#define FLASH_OPTCR_OPTLOCK_Msk        (0x1UL << FLASH_OPTCR_OPTLOCK_Pos)       /*!< 0x00000001 */
+#define FLASH_OPTCR_OPTLOCK            FLASH_OPTCR_OPTLOCK_Msk                 
+#define FLASH_OPTCR_OPTSTRT_Pos        (1U)                                    
+#define FLASH_OPTCR_OPTSTRT_Msk        (0x1UL << FLASH_OPTCR_OPTSTRT_Pos)       /*!< 0x00000002 */
+#define FLASH_OPTCR_OPTSTRT            FLASH_OPTCR_OPTSTRT_Msk                 
+
+#define FLASH_OPTCR_BOR_LEV_0          0x00000004U                             
+#define FLASH_OPTCR_BOR_LEV_1          0x00000008U                             
+#define FLASH_OPTCR_BOR_LEV_Pos        (2U)                                    
+#define FLASH_OPTCR_BOR_LEV_Msk        (0x3UL << FLASH_OPTCR_BOR_LEV_Pos)       /*!< 0x0000000C */
+#define FLASH_OPTCR_BOR_LEV            FLASH_OPTCR_BOR_LEV_Msk                 
+#define FLASH_OPTCR_BFB2_Pos           (4U)                                    
+#define FLASH_OPTCR_BFB2_Msk           (0x1UL << FLASH_OPTCR_BFB2_Pos)          /*!< 0x00000010 */
+#define FLASH_OPTCR_BFB2               FLASH_OPTCR_BFB2_Msk                    
+#define FLASH_OPTCR_WDG_SW_Pos         (5U)                                    
+#define FLASH_OPTCR_WDG_SW_Msk         (0x1UL << FLASH_OPTCR_WDG_SW_Pos)        /*!< 0x00000020 */
+#define FLASH_OPTCR_WDG_SW             FLASH_OPTCR_WDG_SW_Msk                  
+#define FLASH_OPTCR_nRST_STOP_Pos      (6U)                                    
+#define FLASH_OPTCR_nRST_STOP_Msk      (0x1UL << FLASH_OPTCR_nRST_STOP_Pos)     /*!< 0x00000040 */
+#define FLASH_OPTCR_nRST_STOP          FLASH_OPTCR_nRST_STOP_Msk               
+#define FLASH_OPTCR_nRST_STDBY_Pos     (7U)                                    
+#define FLASH_OPTCR_nRST_STDBY_Msk     (0x1UL << FLASH_OPTCR_nRST_STDBY_Pos)    /*!< 0x00000080 */
+#define FLASH_OPTCR_nRST_STDBY         FLASH_OPTCR_nRST_STDBY_Msk              
+#define FLASH_OPTCR_RDP_Pos            (8U)                                    
+#define FLASH_OPTCR_RDP_Msk            (0xFFUL << FLASH_OPTCR_RDP_Pos)          /*!< 0x0000FF00 */
+#define FLASH_OPTCR_RDP                FLASH_OPTCR_RDP_Msk                     
+#define FLASH_OPTCR_RDP_0              (0x01UL << FLASH_OPTCR_RDP_Pos)          /*!< 0x00000100 */
+#define FLASH_OPTCR_RDP_1              (0x02UL << FLASH_OPTCR_RDP_Pos)          /*!< 0x00000200 */
+#define FLASH_OPTCR_RDP_2              (0x04UL << FLASH_OPTCR_RDP_Pos)          /*!< 0x00000400 */
+#define FLASH_OPTCR_RDP_3              (0x08UL << FLASH_OPTCR_RDP_Pos)          /*!< 0x00000800 */
+#define FLASH_OPTCR_RDP_4              (0x10UL << FLASH_OPTCR_RDP_Pos)          /*!< 0x00001000 */
+#define FLASH_OPTCR_RDP_5              (0x20UL << FLASH_OPTCR_RDP_Pos)          /*!< 0x00002000 */
+#define FLASH_OPTCR_RDP_6              (0x40UL << FLASH_OPTCR_RDP_Pos)          /*!< 0x00004000 */
+#define FLASH_OPTCR_RDP_7              (0x80UL << FLASH_OPTCR_RDP_Pos)          /*!< 0x00008000 */
+#define FLASH_OPTCR_nWRP_Pos           (16U)                                   
+#define FLASH_OPTCR_nWRP_Msk           (0xFFFUL << FLASH_OPTCR_nWRP_Pos)        /*!< 0x0FFF0000 */
+#define FLASH_OPTCR_nWRP               FLASH_OPTCR_nWRP_Msk                    
+#define FLASH_OPTCR_nWRP_0             0x00010000U                             
+#define FLASH_OPTCR_nWRP_1             0x00020000U                             
+#define FLASH_OPTCR_nWRP_2             0x00040000U                             
+#define FLASH_OPTCR_nWRP_3             0x00080000U                             
+#define FLASH_OPTCR_nWRP_4             0x00100000U                             
+#define FLASH_OPTCR_nWRP_5             0x00200000U                             
+#define FLASH_OPTCR_nWRP_6             0x00400000U                             
+#define FLASH_OPTCR_nWRP_7             0x00800000U                             
+#define FLASH_OPTCR_nWRP_8             0x01000000U                             
+#define FLASH_OPTCR_nWRP_9             0x02000000U                             
+#define FLASH_OPTCR_nWRP_10            0x04000000U                             
+#define FLASH_OPTCR_nWRP_11            0x08000000U                             
+#define FLASH_OPTCR_DB1M_Pos           (30U)                                   
+#define FLASH_OPTCR_DB1M_Msk           (0x1UL << FLASH_OPTCR_DB1M_Pos)          /*!< 0x40000000 */
+#define FLASH_OPTCR_DB1M               FLASH_OPTCR_DB1M_Msk                    
+#define FLASH_OPTCR_SPRMOD_Pos         (31U)                                   
+#define FLASH_OPTCR_SPRMOD_Msk         (0x1UL << FLASH_OPTCR_SPRMOD_Pos)        /*!< 0x80000000 */
+#define FLASH_OPTCR_SPRMOD             FLASH_OPTCR_SPRMOD_Msk                  
+                                             
+/******************  Bits definition for FLASH_OPTCR1 register  ***************/
+#define FLASH_OPTCR1_nWRP_Pos          (16U)                                   
+#define FLASH_OPTCR1_nWRP_Msk          (0xFFFUL << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x0FFF0000 */
+#define FLASH_OPTCR1_nWRP              FLASH_OPTCR1_nWRP_Msk                   
+#define FLASH_OPTCR1_nWRP_0            (0x001UL << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x00010000 */
+#define FLASH_OPTCR1_nWRP_1            (0x002UL << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x00020000 */
+#define FLASH_OPTCR1_nWRP_2            (0x004UL << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x00040000 */
+#define FLASH_OPTCR1_nWRP_3            (0x008UL << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x00080000 */
+#define FLASH_OPTCR1_nWRP_4            (0x010UL << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x00100000 */
+#define FLASH_OPTCR1_nWRP_5            (0x020UL << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x00200000 */
+#define FLASH_OPTCR1_nWRP_6            (0x040UL << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x00400000 */
+#define FLASH_OPTCR1_nWRP_7            (0x080UL << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x00800000 */
+#define FLASH_OPTCR1_nWRP_8            (0x100UL << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x01000000 */
+#define FLASH_OPTCR1_nWRP_9            (0x200UL << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x02000000 */
+#define FLASH_OPTCR1_nWRP_10           (0x400UL << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x04000000 */
+#define FLASH_OPTCR1_nWRP_11           (0x800UL << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x08000000 */
+
+/******************************************************************************/
+/*                                                                            */
+/*                          Flexible Memory Controller                        */
+/*                                                                            */
+/******************************************************************************/
+/******************  Bit definition for FMC_BCR1 register  *******************/
+#define FMC_BCR1_MBKEN_Pos          (0U)                                       
+#define FMC_BCR1_MBKEN_Msk          (0x1UL << FMC_BCR1_MBKEN_Pos)               /*!< 0x00000001 */
+#define FMC_BCR1_MBKEN              FMC_BCR1_MBKEN_Msk                         /*!<Memory bank enable bit                 */
+#define FMC_BCR1_MUXEN_Pos          (1U)                                       
+#define FMC_BCR1_MUXEN_Msk          (0x1UL << FMC_BCR1_MUXEN_Pos)               /*!< 0x00000002 */
+#define FMC_BCR1_MUXEN              FMC_BCR1_MUXEN_Msk                         /*!<Address/data multiplexing enable bit   */
+
+#define FMC_BCR1_MTYP_Pos           (2U)                                       
+#define FMC_BCR1_MTYP_Msk           (0x3UL << FMC_BCR1_MTYP_Pos)                /*!< 0x0000000C */
+#define FMC_BCR1_MTYP               FMC_BCR1_MTYP_Msk                          /*!<MTYP[1:0] bits (Memory type)           */
+#define FMC_BCR1_MTYP_0             (0x1UL << FMC_BCR1_MTYP_Pos)                /*!< 0x00000004 */
+#define FMC_BCR1_MTYP_1             (0x2UL << FMC_BCR1_MTYP_Pos)                /*!< 0x00000008 */
+
+#define FMC_BCR1_MWID_Pos           (4U)                                       
+#define FMC_BCR1_MWID_Msk           (0x3UL << FMC_BCR1_MWID_Pos)                /*!< 0x00000030 */
+#define FMC_BCR1_MWID               FMC_BCR1_MWID_Msk                          /*!<MWID[1:0] bits (Memory data bus width) */
+#define FMC_BCR1_MWID_0             (0x1UL << FMC_BCR1_MWID_Pos)                /*!< 0x00000010 */
+#define FMC_BCR1_MWID_1             (0x2UL << FMC_BCR1_MWID_Pos)                /*!< 0x00000020 */
+
+#define FMC_BCR1_FACCEN_Pos         (6U)                                       
+#define FMC_BCR1_FACCEN_Msk         (0x1UL << FMC_BCR1_FACCEN_Pos)              /*!< 0x00000040 */
+#define FMC_BCR1_FACCEN             FMC_BCR1_FACCEN_Msk                        /*!<Flash access enable        */
+#define FMC_BCR1_BURSTEN_Pos        (8U)                                       
+#define FMC_BCR1_BURSTEN_Msk        (0x1UL << FMC_BCR1_BURSTEN_Pos)             /*!< 0x00000100 */
+#define FMC_BCR1_BURSTEN            FMC_BCR1_BURSTEN_Msk                       /*!<Burst enable bit           */
+#define FMC_BCR1_WAITPOL_Pos        (9U)                                       
+#define FMC_BCR1_WAITPOL_Msk        (0x1UL << FMC_BCR1_WAITPOL_Pos)             /*!< 0x00000200 */
+#define FMC_BCR1_WAITPOL            FMC_BCR1_WAITPOL_Msk                       /*!<Wait signal polarity bit   */
+#define FMC_BCR1_WAITCFG_Pos        (11U)                                      
+#define FMC_BCR1_WAITCFG_Msk        (0x1UL << FMC_BCR1_WAITCFG_Pos)             /*!< 0x00000800 */
+#define FMC_BCR1_WAITCFG            FMC_BCR1_WAITCFG_Msk                       /*!<Wait timing configuration  */
+#define FMC_BCR1_WREN_Pos           (12U)                                      
+#define FMC_BCR1_WREN_Msk           (0x1UL << FMC_BCR1_WREN_Pos)                /*!< 0x00001000 */
+#define FMC_BCR1_WREN               FMC_BCR1_WREN_Msk                          /*!<Write enable bit           */
+#define FMC_BCR1_WAITEN_Pos         (13U)                                      
+#define FMC_BCR1_WAITEN_Msk         (0x1UL << FMC_BCR1_WAITEN_Pos)              /*!< 0x00002000 */
+#define FMC_BCR1_WAITEN             FMC_BCR1_WAITEN_Msk                        /*!<Wait enable bit            */
+#define FMC_BCR1_EXTMOD_Pos         (14U)                                      
+#define FMC_BCR1_EXTMOD_Msk         (0x1UL << FMC_BCR1_EXTMOD_Pos)              /*!< 0x00004000 */
+#define FMC_BCR1_EXTMOD             FMC_BCR1_EXTMOD_Msk                        /*!<Extended mode enable       */
+#define FMC_BCR1_ASYNCWAIT_Pos      (15U)                                      
+#define FMC_BCR1_ASYNCWAIT_Msk      (0x1UL << FMC_BCR1_ASYNCWAIT_Pos)           /*!< 0x00008000 */
+#define FMC_BCR1_ASYNCWAIT          FMC_BCR1_ASYNCWAIT_Msk                     /*!<Asynchronous wait          */
+#define FMC_BCR1_CPSIZE_Pos         (16U)                                      
+#define FMC_BCR1_CPSIZE_Msk         (0x7UL << FMC_BCR1_CPSIZE_Pos)              /*!< 0x00070000 */
+#define FMC_BCR1_CPSIZE             FMC_BCR1_CPSIZE_Msk                        /*!<CRAM page size             */
+#define FMC_BCR1_CPSIZE_0           (0x1UL << FMC_BCR1_CPSIZE_Pos)              /*!< 0x00010000 */
+#define FMC_BCR1_CPSIZE_1           (0x2UL << FMC_BCR1_CPSIZE_Pos)              /*!< 0x00020000 */
+#define FMC_BCR1_CPSIZE_2           (0x4UL << FMC_BCR1_CPSIZE_Pos)              /*!< 0x00040000 */
+#define FMC_BCR1_CBURSTRW_Pos       (19U)                                      
+#define FMC_BCR1_CBURSTRW_Msk       (0x1UL << FMC_BCR1_CBURSTRW_Pos)            /*!< 0x00080000 */
+#define FMC_BCR1_CBURSTRW           FMC_BCR1_CBURSTRW_Msk                      /*!<Write burst enable         */
+#define FMC_BCR1_CCLKEN_Pos         (20U)                                      
+#define FMC_BCR1_CCLKEN_Msk         (0x1UL << FMC_BCR1_CCLKEN_Pos)              /*!< 0x00100000 */
+#define FMC_BCR1_CCLKEN             FMC_BCR1_CCLKEN_Msk                        /*!<Continuous clock enable     */
+#define FMC_BCR1_WFDIS_Pos          (21U)                                      
+#define FMC_BCR1_WFDIS_Msk          (0x1UL << FMC_BCR1_WFDIS_Pos)               /*!< 0x00200000 */
+#define FMC_BCR1_WFDIS              FMC_BCR1_WFDIS_Msk                         /*!<Write FIFO Disable         */
+
+/******************  Bit definition for FMC_BCR2 register  *******************/
+#define FMC_BCR2_MBKEN_Pos          (0U)                                       
+#define FMC_BCR2_MBKEN_Msk          (0x1UL << FMC_BCR2_MBKEN_Pos)               /*!< 0x00000001 */
+#define FMC_BCR2_MBKEN              FMC_BCR2_MBKEN_Msk                         /*!<Memory bank enable bit                 */
+#define FMC_BCR2_MUXEN_Pos          (1U)                                       
+#define FMC_BCR2_MUXEN_Msk          (0x1UL << FMC_BCR2_MUXEN_Pos)               /*!< 0x00000002 */
+#define FMC_BCR2_MUXEN              FMC_BCR2_MUXEN_Msk                         /*!<Address/data multiplexing enable bit   */
+
+#define FMC_BCR2_MTYP_Pos           (2U)                                       
+#define FMC_BCR2_MTYP_Msk           (0x3UL << FMC_BCR2_MTYP_Pos)                /*!< 0x0000000C */
+#define FMC_BCR2_MTYP               FMC_BCR2_MTYP_Msk                          /*!<MTYP[1:0] bits (Memory type)           */
+#define FMC_BCR2_MTYP_0             (0x1UL << FMC_BCR2_MTYP_Pos)                /*!< 0x00000004 */
+#define FMC_BCR2_MTYP_1             (0x2UL << FMC_BCR2_MTYP_Pos)                /*!< 0x00000008 */
+
+#define FMC_BCR2_MWID_Pos           (4U)                                       
+#define FMC_BCR2_MWID_Msk           (0x3UL << FMC_BCR2_MWID_Pos)                /*!< 0x00000030 */
+#define FMC_BCR2_MWID               FMC_BCR2_MWID_Msk                          /*!<MWID[1:0] bits (Memory data bus width) */
+#define FMC_BCR2_MWID_0             (0x1UL << FMC_BCR2_MWID_Pos)                /*!< 0x00000010 */
+#define FMC_BCR2_MWID_1             (0x2UL << FMC_BCR2_MWID_Pos)                /*!< 0x00000020 */
+
+#define FMC_BCR2_FACCEN_Pos         (6U)                                       
+#define FMC_BCR2_FACCEN_Msk         (0x1UL << FMC_BCR2_FACCEN_Pos)              /*!< 0x00000040 */
+#define FMC_BCR2_FACCEN             FMC_BCR2_FACCEN_Msk                        /*!<Flash access enable        */
+#define FMC_BCR2_BURSTEN_Pos        (8U)                                       
+#define FMC_BCR2_BURSTEN_Msk        (0x1UL << FMC_BCR2_BURSTEN_Pos)             /*!< 0x00000100 */
+#define FMC_BCR2_BURSTEN            FMC_BCR2_BURSTEN_Msk                       /*!<Burst enable bit           */
+#define FMC_BCR2_WAITPOL_Pos        (9U)                                       
+#define FMC_BCR2_WAITPOL_Msk        (0x1UL << FMC_BCR2_WAITPOL_Pos)             /*!< 0x00000200 */
+#define FMC_BCR2_WAITPOL            FMC_BCR2_WAITPOL_Msk                       /*!<Wait signal polarity bit   */
+#define FMC_BCR2_WAITCFG_Pos        (11U)                                      
+#define FMC_BCR2_WAITCFG_Msk        (0x1UL << FMC_BCR2_WAITCFG_Pos)             /*!< 0x00000800 */
+#define FMC_BCR2_WAITCFG            FMC_BCR2_WAITCFG_Msk                       /*!<Wait timing configuration  */
+#define FMC_BCR2_WREN_Pos           (12U)                                      
+#define FMC_BCR2_WREN_Msk           (0x1UL << FMC_BCR2_WREN_Pos)                /*!< 0x00001000 */
+#define FMC_BCR2_WREN               FMC_BCR2_WREN_Msk                          /*!<Write enable bit           */
+#define FMC_BCR2_WAITEN_Pos         (13U)                                      
+#define FMC_BCR2_WAITEN_Msk         (0x1UL << FMC_BCR2_WAITEN_Pos)              /*!< 0x00002000 */
+#define FMC_BCR2_WAITEN             FMC_BCR2_WAITEN_Msk                        /*!<Wait enable bit            */
+#define FMC_BCR2_EXTMOD_Pos         (14U)                                      
+#define FMC_BCR2_EXTMOD_Msk         (0x1UL << FMC_BCR2_EXTMOD_Pos)              /*!< 0x00004000 */
+#define FMC_BCR2_EXTMOD             FMC_BCR2_EXTMOD_Msk                        /*!<Extended mode enable       */
+#define FMC_BCR2_ASYNCWAIT_Pos      (15U)                                      
+#define FMC_BCR2_ASYNCWAIT_Msk      (0x1UL << FMC_BCR2_ASYNCWAIT_Pos)           /*!< 0x00008000 */
+#define FMC_BCR2_ASYNCWAIT          FMC_BCR2_ASYNCWAIT_Msk                     /*!<Asynchronous wait          */
+#define FMC_BCR2_CBURSTRW_Pos       (19U)                                      
+#define FMC_BCR2_CBURSTRW_Msk       (0x1UL << FMC_BCR2_CBURSTRW_Pos)            /*!< 0x00080000 */
+#define FMC_BCR2_CBURSTRW           FMC_BCR2_CBURSTRW_Msk                      /*!<Write burst enable         */
+
+/******************  Bit definition for FMC_BCR3 register  *******************/
+#define FMC_BCR3_MBKEN_Pos          (0U)                                       
+#define FMC_BCR3_MBKEN_Msk          (0x1UL << FMC_BCR3_MBKEN_Pos)               /*!< 0x00000001 */
+#define FMC_BCR3_MBKEN              FMC_BCR3_MBKEN_Msk                         /*!<Memory bank enable bit                 */
+#define FMC_BCR3_MUXEN_Pos          (1U)                                       
+#define FMC_BCR3_MUXEN_Msk          (0x1UL << FMC_BCR3_MUXEN_Pos)               /*!< 0x00000002 */
+#define FMC_BCR3_MUXEN              FMC_BCR3_MUXEN_Msk                         /*!<Address/data multiplexing enable bit   */
+
+#define FMC_BCR3_MTYP_Pos           (2U)                                       
+#define FMC_BCR3_MTYP_Msk           (0x3UL << FMC_BCR3_MTYP_Pos)                /*!< 0x0000000C */
+#define FMC_BCR3_MTYP               FMC_BCR3_MTYP_Msk                          /*!<MTYP[1:0] bits (Memory type)           */
+#define FMC_BCR3_MTYP_0             (0x1UL << FMC_BCR3_MTYP_Pos)                /*!< 0x00000004 */
+#define FMC_BCR3_MTYP_1             (0x2UL << FMC_BCR3_MTYP_Pos)                /*!< 0x00000008 */
+
+#define FMC_BCR3_MWID_Pos           (4U)                                       
+#define FMC_BCR3_MWID_Msk           (0x3UL << FMC_BCR3_MWID_Pos)                /*!< 0x00000030 */
+#define FMC_BCR3_MWID               FMC_BCR3_MWID_Msk                          /*!<MWID[1:0] bits (Memory data bus width) */
+#define FMC_BCR3_MWID_0             (0x1UL << FMC_BCR3_MWID_Pos)                /*!< 0x00000010 */
+#define FMC_BCR3_MWID_1             (0x2UL << FMC_BCR3_MWID_Pos)                /*!< 0x00000020 */
+
+#define FMC_BCR3_FACCEN_Pos         (6U)                                       
+#define FMC_BCR3_FACCEN_Msk         (0x1UL << FMC_BCR3_FACCEN_Pos)              /*!< 0x00000040 */
+#define FMC_BCR3_FACCEN             FMC_BCR3_FACCEN_Msk                        /*!<Flash access enable        */
+#define FMC_BCR3_BURSTEN_Pos        (8U)                                       
+#define FMC_BCR3_BURSTEN_Msk        (0x1UL << FMC_BCR3_BURSTEN_Pos)             /*!< 0x00000100 */
+#define FMC_BCR3_BURSTEN            FMC_BCR3_BURSTEN_Msk                       /*!<Burst enable bit           */
+#define FMC_BCR3_WAITPOL_Pos        (9U)                                       
+#define FMC_BCR3_WAITPOL_Msk        (0x1UL << FMC_BCR3_WAITPOL_Pos)             /*!< 0x00000200 */
+#define FMC_BCR3_WAITPOL            FMC_BCR3_WAITPOL_Msk                       /*!<Wait signal polarity bit   */
+#define FMC_BCR3_WAITCFG_Pos        (11U)                                      
+#define FMC_BCR3_WAITCFG_Msk        (0x1UL << FMC_BCR3_WAITCFG_Pos)             /*!< 0x00000800 */
+#define FMC_BCR3_WAITCFG            FMC_BCR3_WAITCFG_Msk                       /*!<Wait timing configuration  */
+#define FMC_BCR3_WREN_Pos           (12U)                                      
+#define FMC_BCR3_WREN_Msk           (0x1UL << FMC_BCR3_WREN_Pos)                /*!< 0x00001000 */
+#define FMC_BCR3_WREN               FMC_BCR3_WREN_Msk                          /*!<Write enable bit           */
+#define FMC_BCR3_WAITEN_Pos         (13U)                                      
+#define FMC_BCR3_WAITEN_Msk         (0x1UL << FMC_BCR3_WAITEN_Pos)              /*!< 0x00002000 */
+#define FMC_BCR3_WAITEN             FMC_BCR3_WAITEN_Msk                        /*!<Wait enable bit            */
+#define FMC_BCR3_EXTMOD_Pos         (14U)                                      
+#define FMC_BCR3_EXTMOD_Msk         (0x1UL << FMC_BCR3_EXTMOD_Pos)              /*!< 0x00004000 */
+#define FMC_BCR3_EXTMOD             FMC_BCR3_EXTMOD_Msk                        /*!<Extended mode enable       */
+#define FMC_BCR3_ASYNCWAIT_Pos      (15U)                                      
+#define FMC_BCR3_ASYNCWAIT_Msk      (0x1UL << FMC_BCR3_ASYNCWAIT_Pos)           /*!< 0x00008000 */
+#define FMC_BCR3_ASYNCWAIT          FMC_BCR3_ASYNCWAIT_Msk                     /*!<Asynchronous wait          */
+#define FMC_BCR3_CBURSTRW_Pos       (19U)                                      
+#define FMC_BCR3_CBURSTRW_Msk       (0x1UL << FMC_BCR3_CBURSTRW_Pos)            /*!< 0x00080000 */
+#define FMC_BCR3_CBURSTRW           FMC_BCR3_CBURSTRW_Msk                      /*!<Write burst enable         */
+
+/******************  Bit definition for FMC_BCR4 register  *******************/
+#define FMC_BCR4_MBKEN_Pos          (0U)                                       
+#define FMC_BCR4_MBKEN_Msk          (0x1UL << FMC_BCR4_MBKEN_Pos)               /*!< 0x00000001 */
+#define FMC_BCR4_MBKEN              FMC_BCR4_MBKEN_Msk                         /*!<Memory bank enable bit                 */
+#define FMC_BCR4_MUXEN_Pos          (1U)                                       
+#define FMC_BCR4_MUXEN_Msk          (0x1UL << FMC_BCR4_MUXEN_Pos)               /*!< 0x00000002 */
+#define FMC_BCR4_MUXEN              FMC_BCR4_MUXEN_Msk                         /*!<Address/data multiplexing enable bit   */
+
+#define FMC_BCR4_MTYP_Pos           (2U)                                       
+#define FMC_BCR4_MTYP_Msk           (0x3UL << FMC_BCR4_MTYP_Pos)                /*!< 0x0000000C */
+#define FMC_BCR4_MTYP               FMC_BCR4_MTYP_Msk                          /*!<MTYP[1:0] bits (Memory type)           */
+#define FMC_BCR4_MTYP_0             (0x1UL << FMC_BCR4_MTYP_Pos)                /*!< 0x00000004 */
+#define FMC_BCR4_MTYP_1             (0x2UL << FMC_BCR4_MTYP_Pos)                /*!< 0x00000008 */
+
+#define FMC_BCR4_MWID_Pos           (4U)                                       
+#define FMC_BCR4_MWID_Msk           (0x3UL << FMC_BCR4_MWID_Pos)                /*!< 0x00000030 */
+#define FMC_BCR4_MWID               FMC_BCR4_MWID_Msk                          /*!<MWID[1:0] bits (Memory data bus width) */
+#define FMC_BCR4_MWID_0             (0x1UL << FMC_BCR4_MWID_Pos)                /*!< 0x00000010 */
+#define FMC_BCR4_MWID_1             (0x2UL << FMC_BCR4_MWID_Pos)                /*!< 0x00000020 */
+
+#define FMC_BCR4_FACCEN_Pos         (6U)                                       
+#define FMC_BCR4_FACCEN_Msk         (0x1UL << FMC_BCR4_FACCEN_Pos)              /*!< 0x00000040 */
+#define FMC_BCR4_FACCEN             FMC_BCR4_FACCEN_Msk                        /*!<Flash access enable        */
+#define FMC_BCR4_BURSTEN_Pos        (8U)                                       
+#define FMC_BCR4_BURSTEN_Msk        (0x1UL << FMC_BCR4_BURSTEN_Pos)             /*!< 0x00000100 */
+#define FMC_BCR4_BURSTEN            FMC_BCR4_BURSTEN_Msk                       /*!<Burst enable bit           */
+#define FMC_BCR4_WAITPOL_Pos        (9U)                                       
+#define FMC_BCR4_WAITPOL_Msk        (0x1UL << FMC_BCR4_WAITPOL_Pos)             /*!< 0x00000200 */
+#define FMC_BCR4_WAITPOL            FMC_BCR4_WAITPOL_Msk                       /*!<Wait signal polarity bit   */
+#define FMC_BCR4_WAITCFG_Pos        (11U)                                      
+#define FMC_BCR4_WAITCFG_Msk        (0x1UL << FMC_BCR4_WAITCFG_Pos)             /*!< 0x00000800 */
+#define FMC_BCR4_WAITCFG            FMC_BCR4_WAITCFG_Msk                       /*!<Wait timing configuration  */
+#define FMC_BCR4_WREN_Pos           (12U)                                      
+#define FMC_BCR4_WREN_Msk           (0x1UL << FMC_BCR4_WREN_Pos)                /*!< 0x00001000 */
+#define FMC_BCR4_WREN               FMC_BCR4_WREN_Msk                          /*!<Write enable bit           */
+#define FMC_BCR4_WAITEN_Pos         (13U)                                      
+#define FMC_BCR4_WAITEN_Msk         (0x1UL << FMC_BCR4_WAITEN_Pos)              /*!< 0x00002000 */
+#define FMC_BCR4_WAITEN             FMC_BCR4_WAITEN_Msk                        /*!<Wait enable bit            */
+#define FMC_BCR4_EXTMOD_Pos         (14U)                                      
+#define FMC_BCR4_EXTMOD_Msk         (0x1UL << FMC_BCR4_EXTMOD_Pos)              /*!< 0x00004000 */
+#define FMC_BCR4_EXTMOD             FMC_BCR4_EXTMOD_Msk                        /*!<Extended mode enable       */
+#define FMC_BCR4_ASYNCWAIT_Pos      (15U)                                      
+#define FMC_BCR4_ASYNCWAIT_Msk      (0x1UL << FMC_BCR4_ASYNCWAIT_Pos)           /*!< 0x00008000 */
+#define FMC_BCR4_ASYNCWAIT          FMC_BCR4_ASYNCWAIT_Msk                     /*!<Asynchronous wait          */
+#define FMC_BCR4_CBURSTRW_Pos       (19U)                                      
+#define FMC_BCR4_CBURSTRW_Msk       (0x1UL << FMC_BCR4_CBURSTRW_Pos)            /*!< 0x00080000 */
+#define FMC_BCR4_CBURSTRW           FMC_BCR4_CBURSTRW_Msk                      /*!<Write burst enable         */
+
+/******************  Bit definition for FMC_BTR1 register  ******************/
+#define FMC_BTR1_ADDSET_Pos         (0U)                                       
+#define FMC_BTR1_ADDSET_Msk         (0xFUL << FMC_BTR1_ADDSET_Pos)              /*!< 0x0000000F */
+#define FMC_BTR1_ADDSET             FMC_BTR1_ADDSET_Msk                        /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FMC_BTR1_ADDSET_0           (0x1UL << FMC_BTR1_ADDSET_Pos)              /*!< 0x00000001 */
+#define FMC_BTR1_ADDSET_1           (0x2UL << FMC_BTR1_ADDSET_Pos)              /*!< 0x00000002 */
+#define FMC_BTR1_ADDSET_2           (0x4UL << FMC_BTR1_ADDSET_Pos)              /*!< 0x00000004 */
+#define FMC_BTR1_ADDSET_3           (0x8UL << FMC_BTR1_ADDSET_Pos)              /*!< 0x00000008 */
+
+#define FMC_BTR1_ADDHLD_Pos         (4U)                                       
+#define FMC_BTR1_ADDHLD_Msk         (0xFUL << FMC_BTR1_ADDHLD_Pos)              /*!< 0x000000F0 */
+#define FMC_BTR1_ADDHLD             FMC_BTR1_ADDHLD_Msk                        /*!<ADDHLD[3:0] bits (Address-hold phase duration)  */
+#define FMC_BTR1_ADDHLD_0           (0x1UL << FMC_BTR1_ADDHLD_Pos)              /*!< 0x00000010 */
+#define FMC_BTR1_ADDHLD_1           (0x2UL << FMC_BTR1_ADDHLD_Pos)              /*!< 0x00000020 */
+#define FMC_BTR1_ADDHLD_2           (0x4UL << FMC_BTR1_ADDHLD_Pos)              /*!< 0x00000040 */
+#define FMC_BTR1_ADDHLD_3           (0x8UL << FMC_BTR1_ADDHLD_Pos)              /*!< 0x00000080 */
+
+#define FMC_BTR1_DATAST_Pos         (8U)                                       
+#define FMC_BTR1_DATAST_Msk         (0xFFUL << FMC_BTR1_DATAST_Pos)             /*!< 0x0000FF00 */
+#define FMC_BTR1_DATAST             FMC_BTR1_DATAST_Msk                        /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FMC_BTR1_DATAST_0           (0x01UL << FMC_BTR1_DATAST_Pos)             /*!< 0x00000100 */
+#define FMC_BTR1_DATAST_1           (0x02UL << FMC_BTR1_DATAST_Pos)             /*!< 0x00000200 */
+#define FMC_BTR1_DATAST_2           (0x04UL << FMC_BTR1_DATAST_Pos)             /*!< 0x00000400 */
+#define FMC_BTR1_DATAST_3           (0x08UL << FMC_BTR1_DATAST_Pos)             /*!< 0x00000800 */
+#define FMC_BTR1_DATAST_4           (0x10UL << FMC_BTR1_DATAST_Pos)             /*!< 0x00001000 */
+#define FMC_BTR1_DATAST_5           (0x20UL << FMC_BTR1_DATAST_Pos)             /*!< 0x00002000 */
+#define FMC_BTR1_DATAST_6           (0x40UL << FMC_BTR1_DATAST_Pos)             /*!< 0x00004000 */
+#define FMC_BTR1_DATAST_7           (0x80UL << FMC_BTR1_DATAST_Pos)             /*!< 0x00008000 */
+
+#define FMC_BTR1_BUSTURN_Pos        (16U)                                      
+#define FMC_BTR1_BUSTURN_Msk        (0xFUL << FMC_BTR1_BUSTURN_Pos)             /*!< 0x000F0000 */
+#define FMC_BTR1_BUSTURN            FMC_BTR1_BUSTURN_Msk                       /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define FMC_BTR1_BUSTURN_0          (0x1UL << FMC_BTR1_BUSTURN_Pos)             /*!< 0x00010000 */
+#define FMC_BTR1_BUSTURN_1          (0x2UL << FMC_BTR1_BUSTURN_Pos)             /*!< 0x00020000 */
+#define FMC_BTR1_BUSTURN_2          (0x4UL << FMC_BTR1_BUSTURN_Pos)             /*!< 0x00040000 */
+#define FMC_BTR1_BUSTURN_3          (0x8UL << FMC_BTR1_BUSTURN_Pos)             /*!< 0x00080000 */
+
+#define FMC_BTR1_CLKDIV_Pos         (20U)                                      
+#define FMC_BTR1_CLKDIV_Msk         (0xFUL << FMC_BTR1_CLKDIV_Pos)              /*!< 0x00F00000 */
+#define FMC_BTR1_CLKDIV             FMC_BTR1_CLKDIV_Msk                        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define FMC_BTR1_CLKDIV_0           (0x1UL << FMC_BTR1_CLKDIV_Pos)              /*!< 0x00100000 */
+#define FMC_BTR1_CLKDIV_1           (0x2UL << FMC_BTR1_CLKDIV_Pos)              /*!< 0x00200000 */
+#define FMC_BTR1_CLKDIV_2           (0x4UL << FMC_BTR1_CLKDIV_Pos)              /*!< 0x00400000 */
+#define FMC_BTR1_CLKDIV_3           (0x8UL << FMC_BTR1_CLKDIV_Pos)              /*!< 0x00800000 */
+
+#define FMC_BTR1_DATLAT_Pos         (24U)                                      
+#define FMC_BTR1_DATLAT_Msk         (0xFUL << FMC_BTR1_DATLAT_Pos)              /*!< 0x0F000000 */
+#define FMC_BTR1_DATLAT             FMC_BTR1_DATLAT_Msk                        /*!<DATLA[3:0] bits (Data latency) */
+#define FMC_BTR1_DATLAT_0           (0x1UL << FMC_BTR1_DATLAT_Pos)              /*!< 0x01000000 */
+#define FMC_BTR1_DATLAT_1           (0x2UL << FMC_BTR1_DATLAT_Pos)              /*!< 0x02000000 */
+#define FMC_BTR1_DATLAT_2           (0x4UL << FMC_BTR1_DATLAT_Pos)              /*!< 0x04000000 */
+#define FMC_BTR1_DATLAT_3           (0x8UL << FMC_BTR1_DATLAT_Pos)              /*!< 0x08000000 */
+
+#define FMC_BTR1_ACCMOD_Pos         (28U)                                      
+#define FMC_BTR1_ACCMOD_Msk         (0x3UL << FMC_BTR1_ACCMOD_Pos)              /*!< 0x30000000 */
+#define FMC_BTR1_ACCMOD             FMC_BTR1_ACCMOD_Msk                        /*!<ACCMOD[1:0] bits (Access mode) */
+#define FMC_BTR1_ACCMOD_0           (0x1UL << FMC_BTR1_ACCMOD_Pos)              /*!< 0x10000000 */
+#define FMC_BTR1_ACCMOD_1           (0x2UL << FMC_BTR1_ACCMOD_Pos)              /*!< 0x20000000 */
+
+/******************  Bit definition for FMC_BTR2 register  *******************/
+#define FMC_BTR2_ADDSET_Pos         (0U)                                       
+#define FMC_BTR2_ADDSET_Msk         (0xFUL << FMC_BTR2_ADDSET_Pos)              /*!< 0x0000000F */
+#define FMC_BTR2_ADDSET             FMC_BTR2_ADDSET_Msk                        /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FMC_BTR2_ADDSET_0           (0x1UL << FMC_BTR2_ADDSET_Pos)              /*!< 0x00000001 */
+#define FMC_BTR2_ADDSET_1           (0x2UL << FMC_BTR2_ADDSET_Pos)              /*!< 0x00000002 */
+#define FMC_BTR2_ADDSET_2           (0x4UL << FMC_BTR2_ADDSET_Pos)              /*!< 0x00000004 */
+#define FMC_BTR2_ADDSET_3           (0x8UL << FMC_BTR2_ADDSET_Pos)              /*!< 0x00000008 */
+
+#define FMC_BTR2_ADDHLD_Pos         (4U)                                       
+#define FMC_BTR2_ADDHLD_Msk         (0xFUL << FMC_BTR2_ADDHLD_Pos)              /*!< 0x000000F0 */
+#define FMC_BTR2_ADDHLD             FMC_BTR2_ADDHLD_Msk                        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FMC_BTR2_ADDHLD_0           (0x1UL << FMC_BTR2_ADDHLD_Pos)              /*!< 0x00000010 */
+#define FMC_BTR2_ADDHLD_1           (0x2UL << FMC_BTR2_ADDHLD_Pos)              /*!< 0x00000020 */
+#define FMC_BTR2_ADDHLD_2           (0x4UL << FMC_BTR2_ADDHLD_Pos)              /*!< 0x00000040 */
+#define FMC_BTR2_ADDHLD_3           (0x8UL << FMC_BTR2_ADDHLD_Pos)              /*!< 0x00000080 */
+
+#define FMC_BTR2_DATAST_Pos         (8U)                                       
+#define FMC_BTR2_DATAST_Msk         (0xFFUL << FMC_BTR2_DATAST_Pos)             /*!< 0x0000FF00 */
+#define FMC_BTR2_DATAST             FMC_BTR2_DATAST_Msk                        /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FMC_BTR2_DATAST_0           (0x01UL << FMC_BTR2_DATAST_Pos)             /*!< 0x00000100 */
+#define FMC_BTR2_DATAST_1           (0x02UL << FMC_BTR2_DATAST_Pos)             /*!< 0x00000200 */
+#define FMC_BTR2_DATAST_2           (0x04UL << FMC_BTR2_DATAST_Pos)             /*!< 0x00000400 */
+#define FMC_BTR2_DATAST_3           (0x08UL << FMC_BTR2_DATAST_Pos)             /*!< 0x00000800 */
+#define FMC_BTR2_DATAST_4           (0x10UL << FMC_BTR2_DATAST_Pos)             /*!< 0x00001000 */
+#define FMC_BTR2_DATAST_5           (0x20UL << FMC_BTR2_DATAST_Pos)             /*!< 0x00002000 */
+#define FMC_BTR2_DATAST_6           (0x40UL << FMC_BTR2_DATAST_Pos)             /*!< 0x00004000 */
+#define FMC_BTR2_DATAST_7           (0x80UL << FMC_BTR2_DATAST_Pos)             /*!< 0x00008000 */
+
+#define FMC_BTR2_BUSTURN_Pos        (16U)                                      
+#define FMC_BTR2_BUSTURN_Msk        (0xFUL << FMC_BTR2_BUSTURN_Pos)             /*!< 0x000F0000 */
+#define FMC_BTR2_BUSTURN            FMC_BTR2_BUSTURN_Msk                       /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define FMC_BTR2_BUSTURN_0          (0x1UL << FMC_BTR2_BUSTURN_Pos)             /*!< 0x00010000 */
+#define FMC_BTR2_BUSTURN_1          (0x2UL << FMC_BTR2_BUSTURN_Pos)             /*!< 0x00020000 */
+#define FMC_BTR2_BUSTURN_2          (0x4UL << FMC_BTR2_BUSTURN_Pos)             /*!< 0x00040000 */
+#define FMC_BTR2_BUSTURN_3          (0x8UL << FMC_BTR2_BUSTURN_Pos)             /*!< 0x00080000 */
+
+#define FMC_BTR2_CLKDIV_Pos         (20U)                                      
+#define FMC_BTR2_CLKDIV_Msk         (0xFUL << FMC_BTR2_CLKDIV_Pos)              /*!< 0x00F00000 */
+#define FMC_BTR2_CLKDIV             FMC_BTR2_CLKDIV_Msk                        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define FMC_BTR2_CLKDIV_0           (0x1UL << FMC_BTR2_CLKDIV_Pos)              /*!< 0x00100000 */
+#define FMC_BTR2_CLKDIV_1           (0x2UL << FMC_BTR2_CLKDIV_Pos)              /*!< 0x00200000 */
+#define FMC_BTR2_CLKDIV_2           (0x4UL << FMC_BTR2_CLKDIV_Pos)              /*!< 0x00400000 */
+#define FMC_BTR2_CLKDIV_3           (0x8UL << FMC_BTR2_CLKDIV_Pos)              /*!< 0x00800000 */
+
+#define FMC_BTR2_DATLAT_Pos         (24U)                                      
+#define FMC_BTR2_DATLAT_Msk         (0xFUL << FMC_BTR2_DATLAT_Pos)              /*!< 0x0F000000 */
+#define FMC_BTR2_DATLAT             FMC_BTR2_DATLAT_Msk                        /*!<DATLA[3:0] bits (Data latency) */
+#define FMC_BTR2_DATLAT_0           (0x1UL << FMC_BTR2_DATLAT_Pos)              /*!< 0x01000000 */
+#define FMC_BTR2_DATLAT_1           (0x2UL << FMC_BTR2_DATLAT_Pos)              /*!< 0x02000000 */
+#define FMC_BTR2_DATLAT_2           (0x4UL << FMC_BTR2_DATLAT_Pos)              /*!< 0x04000000 */
+#define FMC_BTR2_DATLAT_3           (0x8UL << FMC_BTR2_DATLAT_Pos)              /*!< 0x08000000 */
+
+#define FMC_BTR2_ACCMOD_Pos         (28U)                                      
+#define FMC_BTR2_ACCMOD_Msk         (0x3UL << FMC_BTR2_ACCMOD_Pos)              /*!< 0x30000000 */
+#define FMC_BTR2_ACCMOD             FMC_BTR2_ACCMOD_Msk                        /*!<ACCMOD[1:0] bits (Access mode) */
+#define FMC_BTR2_ACCMOD_0           (0x1UL << FMC_BTR2_ACCMOD_Pos)              /*!< 0x10000000 */
+#define FMC_BTR2_ACCMOD_1           (0x2UL << FMC_BTR2_ACCMOD_Pos)              /*!< 0x20000000 */
+
+/*******************  Bit definition for FMC_BTR3 register  *******************/
+#define FMC_BTR3_ADDSET_Pos         (0U)                                       
+#define FMC_BTR3_ADDSET_Msk         (0xFUL << FMC_BTR3_ADDSET_Pos)              /*!< 0x0000000F */
+#define FMC_BTR3_ADDSET             FMC_BTR3_ADDSET_Msk                        /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FMC_BTR3_ADDSET_0           (0x1UL << FMC_BTR3_ADDSET_Pos)              /*!< 0x00000001 */
+#define FMC_BTR3_ADDSET_1           (0x2UL << FMC_BTR3_ADDSET_Pos)              /*!< 0x00000002 */
+#define FMC_BTR3_ADDSET_2           (0x4UL << FMC_BTR3_ADDSET_Pos)              /*!< 0x00000004 */
+#define FMC_BTR3_ADDSET_3           (0x8UL << FMC_BTR3_ADDSET_Pos)              /*!< 0x00000008 */
+
+#define FMC_BTR3_ADDHLD_Pos         (4U)                                       
+#define FMC_BTR3_ADDHLD_Msk         (0xFUL << FMC_BTR3_ADDHLD_Pos)              /*!< 0x000000F0 */
+#define FMC_BTR3_ADDHLD             FMC_BTR3_ADDHLD_Msk                        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FMC_BTR3_ADDHLD_0           (0x1UL << FMC_BTR3_ADDHLD_Pos)              /*!< 0x00000010 */
+#define FMC_BTR3_ADDHLD_1           (0x2UL << FMC_BTR3_ADDHLD_Pos)              /*!< 0x00000020 */
+#define FMC_BTR3_ADDHLD_2           (0x4UL << FMC_BTR3_ADDHLD_Pos)              /*!< 0x00000040 */
+#define FMC_BTR3_ADDHLD_3           (0x8UL << FMC_BTR3_ADDHLD_Pos)              /*!< 0x00000080 */
+
+#define FMC_BTR3_DATAST_Pos         (8U)                                       
+#define FMC_BTR3_DATAST_Msk         (0xFFUL << FMC_BTR3_DATAST_Pos)             /*!< 0x0000FF00 */
+#define FMC_BTR3_DATAST             FMC_BTR3_DATAST_Msk                        /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FMC_BTR3_DATAST_0           (0x01UL << FMC_BTR3_DATAST_Pos)             /*!< 0x00000100 */
+#define FMC_BTR3_DATAST_1           (0x02UL << FMC_BTR3_DATAST_Pos)             /*!< 0x00000200 */
+#define FMC_BTR3_DATAST_2           (0x04UL << FMC_BTR3_DATAST_Pos)             /*!< 0x00000400 */
+#define FMC_BTR3_DATAST_3           (0x08UL << FMC_BTR3_DATAST_Pos)             /*!< 0x00000800 */
+#define FMC_BTR3_DATAST_4           (0x10UL << FMC_BTR3_DATAST_Pos)             /*!< 0x00001000 */
+#define FMC_BTR3_DATAST_5           (0x20UL << FMC_BTR3_DATAST_Pos)             /*!< 0x00002000 */
+#define FMC_BTR3_DATAST_6           (0x40UL << FMC_BTR3_DATAST_Pos)             /*!< 0x00004000 */
+#define FMC_BTR3_DATAST_7           (0x80UL << FMC_BTR3_DATAST_Pos)             /*!< 0x00008000 */
+
+#define FMC_BTR3_BUSTURN_Pos        (16U)                                      
+#define FMC_BTR3_BUSTURN_Msk        (0xFUL << FMC_BTR3_BUSTURN_Pos)             /*!< 0x000F0000 */
+#define FMC_BTR3_BUSTURN            FMC_BTR3_BUSTURN_Msk                       /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define FMC_BTR3_BUSTURN_0          (0x1UL << FMC_BTR3_BUSTURN_Pos)             /*!< 0x00010000 */
+#define FMC_BTR3_BUSTURN_1          (0x2UL << FMC_BTR3_BUSTURN_Pos)             /*!< 0x00020000 */
+#define FMC_BTR3_BUSTURN_2          (0x4UL << FMC_BTR3_BUSTURN_Pos)             /*!< 0x00040000 */
+#define FMC_BTR3_BUSTURN_3          (0x8UL << FMC_BTR3_BUSTURN_Pos)             /*!< 0x00080000 */
+
+#define FMC_BTR3_CLKDIV_Pos         (20U)                                      
+#define FMC_BTR3_CLKDIV_Msk         (0xFUL << FMC_BTR3_CLKDIV_Pos)              /*!< 0x00F00000 */
+#define FMC_BTR3_CLKDIV             FMC_BTR3_CLKDIV_Msk                        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define FMC_BTR3_CLKDIV_0           (0x1UL << FMC_BTR3_CLKDIV_Pos)              /*!< 0x00100000 */
+#define FMC_BTR3_CLKDIV_1           (0x2UL << FMC_BTR3_CLKDIV_Pos)              /*!< 0x00200000 */
+#define FMC_BTR3_CLKDIV_2           (0x4UL << FMC_BTR3_CLKDIV_Pos)              /*!< 0x00400000 */
+#define FMC_BTR3_CLKDIV_3           (0x8UL << FMC_BTR3_CLKDIV_Pos)              /*!< 0x00800000 */
+
+#define FMC_BTR3_DATLAT_Pos         (24U)                                      
+#define FMC_BTR3_DATLAT_Msk         (0xFUL << FMC_BTR3_DATLAT_Pos)              /*!< 0x0F000000 */
+#define FMC_BTR3_DATLAT             FMC_BTR3_DATLAT_Msk                        /*!<DATLA[3:0] bits (Data latency) */
+#define FMC_BTR3_DATLAT_0           (0x1UL << FMC_BTR3_DATLAT_Pos)              /*!< 0x01000000 */
+#define FMC_BTR3_DATLAT_1           (0x2UL << FMC_BTR3_DATLAT_Pos)              /*!< 0x02000000 */
+#define FMC_BTR3_DATLAT_2           (0x4UL << FMC_BTR3_DATLAT_Pos)              /*!< 0x04000000 */
+#define FMC_BTR3_DATLAT_3           (0x8UL << FMC_BTR3_DATLAT_Pos)              /*!< 0x08000000 */
+
+#define FMC_BTR3_ACCMOD_Pos         (28U)                                      
+#define FMC_BTR3_ACCMOD_Msk         (0x3UL << FMC_BTR3_ACCMOD_Pos)              /*!< 0x30000000 */
+#define FMC_BTR3_ACCMOD             FMC_BTR3_ACCMOD_Msk                        /*!<ACCMOD[1:0] bits (Access mode) */
+#define FMC_BTR3_ACCMOD_0           (0x1UL << FMC_BTR3_ACCMOD_Pos)              /*!< 0x10000000 */
+#define FMC_BTR3_ACCMOD_1           (0x2UL << FMC_BTR3_ACCMOD_Pos)              /*!< 0x20000000 */
+
+/******************  Bit definition for FMC_BTR4 register  *******************/
+#define FMC_BTR4_ADDSET_Pos         (0U)                                       
+#define FMC_BTR4_ADDSET_Msk         (0xFUL << FMC_BTR4_ADDSET_Pos)              /*!< 0x0000000F */
+#define FMC_BTR4_ADDSET             FMC_BTR4_ADDSET_Msk                        /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FMC_BTR4_ADDSET_0           (0x1UL << FMC_BTR4_ADDSET_Pos)              /*!< 0x00000001 */
+#define FMC_BTR4_ADDSET_1           (0x2UL << FMC_BTR4_ADDSET_Pos)              /*!< 0x00000002 */
+#define FMC_BTR4_ADDSET_2           (0x4UL << FMC_BTR4_ADDSET_Pos)              /*!< 0x00000004 */
+#define FMC_BTR4_ADDSET_3           (0x8UL << FMC_BTR4_ADDSET_Pos)              /*!< 0x00000008 */
+
+#define FMC_BTR4_ADDHLD_Pos         (4U)                                       
+#define FMC_BTR4_ADDHLD_Msk         (0xFUL << FMC_BTR4_ADDHLD_Pos)              /*!< 0x000000F0 */
+#define FMC_BTR4_ADDHLD             FMC_BTR4_ADDHLD_Msk                        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FMC_BTR4_ADDHLD_0           (0x1UL << FMC_BTR4_ADDHLD_Pos)              /*!< 0x00000010 */
+#define FMC_BTR4_ADDHLD_1           (0x2UL << FMC_BTR4_ADDHLD_Pos)              /*!< 0x00000020 */
+#define FMC_BTR4_ADDHLD_2           (0x4UL << FMC_BTR4_ADDHLD_Pos)              /*!< 0x00000040 */
+#define FMC_BTR4_ADDHLD_3           (0x8UL << FMC_BTR4_ADDHLD_Pos)              /*!< 0x00000080 */
+
+#define FMC_BTR4_DATAST_Pos         (8U)                                       
+#define FMC_BTR4_DATAST_Msk         (0xFFUL << FMC_BTR4_DATAST_Pos)             /*!< 0x0000FF00 */
+#define FMC_BTR4_DATAST             FMC_BTR4_DATAST_Msk                        /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FMC_BTR4_DATAST_0           (0x01UL << FMC_BTR4_DATAST_Pos)             /*!< 0x00000100 */
+#define FMC_BTR4_DATAST_1           (0x02UL << FMC_BTR4_DATAST_Pos)             /*!< 0x00000200 */
+#define FMC_BTR4_DATAST_2           (0x04UL << FMC_BTR4_DATAST_Pos)             /*!< 0x00000400 */
+#define FMC_BTR4_DATAST_3           (0x08UL << FMC_BTR4_DATAST_Pos)             /*!< 0x00000800 */
+#define FMC_BTR4_DATAST_4           (0x10UL << FMC_BTR4_DATAST_Pos)             /*!< 0x00001000 */
+#define FMC_BTR4_DATAST_5           (0x20UL << FMC_BTR4_DATAST_Pos)             /*!< 0x00002000 */
+#define FMC_BTR4_DATAST_6           (0x40UL << FMC_BTR4_DATAST_Pos)             /*!< 0x00004000 */
+#define FMC_BTR4_DATAST_7           (0x80UL << FMC_BTR4_DATAST_Pos)             /*!< 0x00008000 */
+
+#define FMC_BTR4_BUSTURN_Pos        (16U)                                      
+#define FMC_BTR4_BUSTURN_Msk        (0xFUL << FMC_BTR4_BUSTURN_Pos)             /*!< 0x000F0000 */
+#define FMC_BTR4_BUSTURN            FMC_BTR4_BUSTURN_Msk                       /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define FMC_BTR4_BUSTURN_0          (0x1UL << FMC_BTR4_BUSTURN_Pos)             /*!< 0x00010000 */
+#define FMC_BTR4_BUSTURN_1          (0x2UL << FMC_BTR4_BUSTURN_Pos)             /*!< 0x00020000 */
+#define FMC_BTR4_BUSTURN_2          (0x4UL << FMC_BTR4_BUSTURN_Pos)             /*!< 0x00040000 */
+#define FMC_BTR4_BUSTURN_3          (0x8UL << FMC_BTR4_BUSTURN_Pos)             /*!< 0x00080000 */
+
+#define FMC_BTR4_CLKDIV_Pos         (20U)                                      
+#define FMC_BTR4_CLKDIV_Msk         (0xFUL << FMC_BTR4_CLKDIV_Pos)              /*!< 0x00F00000 */
+#define FMC_BTR4_CLKDIV             FMC_BTR4_CLKDIV_Msk                        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define FMC_BTR4_CLKDIV_0           (0x1UL << FMC_BTR4_CLKDIV_Pos)              /*!< 0x00100000 */
+#define FMC_BTR4_CLKDIV_1           (0x2UL << FMC_BTR4_CLKDIV_Pos)              /*!< 0x00200000 */
+#define FMC_BTR4_CLKDIV_2           (0x4UL << FMC_BTR4_CLKDIV_Pos)              /*!< 0x00400000 */
+#define FMC_BTR4_CLKDIV_3           (0x8UL << FMC_BTR4_CLKDIV_Pos)              /*!< 0x00800000 */
+
+#define FMC_BTR4_DATLAT_Pos         (24U)                                      
+#define FMC_BTR4_DATLAT_Msk         (0xFUL << FMC_BTR4_DATLAT_Pos)              /*!< 0x0F000000 */
+#define FMC_BTR4_DATLAT             FMC_BTR4_DATLAT_Msk                        /*!<DATLA[3:0] bits (Data latency) */
+#define FMC_BTR4_DATLAT_0           (0x1UL << FMC_BTR4_DATLAT_Pos)              /*!< 0x01000000 */
+#define FMC_BTR4_DATLAT_1           (0x2UL << FMC_BTR4_DATLAT_Pos)              /*!< 0x02000000 */
+#define FMC_BTR4_DATLAT_2           (0x4UL << FMC_BTR4_DATLAT_Pos)              /*!< 0x04000000 */
+#define FMC_BTR4_DATLAT_3           (0x8UL << FMC_BTR4_DATLAT_Pos)              /*!< 0x08000000 */
+
+#define FMC_BTR4_ACCMOD_Pos         (28U)                                      
+#define FMC_BTR4_ACCMOD_Msk         (0x3UL << FMC_BTR4_ACCMOD_Pos)              /*!< 0x30000000 */
+#define FMC_BTR4_ACCMOD             FMC_BTR4_ACCMOD_Msk                        /*!<ACCMOD[1:0] bits (Access mode) */
+#define FMC_BTR4_ACCMOD_0           (0x1UL << FMC_BTR4_ACCMOD_Pos)              /*!< 0x10000000 */
+#define FMC_BTR4_ACCMOD_1           (0x2UL << FMC_BTR4_ACCMOD_Pos)              /*!< 0x20000000 */
+
+/******************  Bit definition for FMC_BWTR1 register  ******************/
+#define FMC_BWTR1_ADDSET_Pos        (0U)                                       
+#define FMC_BWTR1_ADDSET_Msk        (0xFUL << FMC_BWTR1_ADDSET_Pos)             /*!< 0x0000000F */
+#define FMC_BWTR1_ADDSET            FMC_BWTR1_ADDSET_Msk                       /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FMC_BWTR1_ADDSET_0          (0x1UL << FMC_BWTR1_ADDSET_Pos)             /*!< 0x00000001 */
+#define FMC_BWTR1_ADDSET_1          (0x2UL << FMC_BWTR1_ADDSET_Pos)             /*!< 0x00000002 */
+#define FMC_BWTR1_ADDSET_2          (0x4UL << FMC_BWTR1_ADDSET_Pos)             /*!< 0x00000004 */
+#define FMC_BWTR1_ADDSET_3          (0x8UL << FMC_BWTR1_ADDSET_Pos)             /*!< 0x00000008 */
+
+#define FMC_BWTR1_ADDHLD_Pos        (4U)                                       
+#define FMC_BWTR1_ADDHLD_Msk        (0xFUL << FMC_BWTR1_ADDHLD_Pos)             /*!< 0x000000F0 */
+#define FMC_BWTR1_ADDHLD            FMC_BWTR1_ADDHLD_Msk                       /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FMC_BWTR1_ADDHLD_0          (0x1UL << FMC_BWTR1_ADDHLD_Pos)             /*!< 0x00000010 */
+#define FMC_BWTR1_ADDHLD_1          (0x2UL << FMC_BWTR1_ADDHLD_Pos)             /*!< 0x00000020 */
+#define FMC_BWTR1_ADDHLD_2          (0x4UL << FMC_BWTR1_ADDHLD_Pos)             /*!< 0x00000040 */
+#define FMC_BWTR1_ADDHLD_3          (0x8UL << FMC_BWTR1_ADDHLD_Pos)             /*!< 0x00000080 */
+
+#define FMC_BWTR1_DATAST_Pos        (8U)                                       
+#define FMC_BWTR1_DATAST_Msk        (0xFFUL << FMC_BWTR1_DATAST_Pos)            /*!< 0x0000FF00 */
+#define FMC_BWTR1_DATAST            FMC_BWTR1_DATAST_Msk                       /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FMC_BWTR1_DATAST_0          (0x01UL << FMC_BWTR1_DATAST_Pos)            /*!< 0x00000100 */
+#define FMC_BWTR1_DATAST_1          (0x02UL << FMC_BWTR1_DATAST_Pos)            /*!< 0x00000200 */
+#define FMC_BWTR1_DATAST_2          (0x04UL << FMC_BWTR1_DATAST_Pos)            /*!< 0x00000400 */
+#define FMC_BWTR1_DATAST_3          (0x08UL << FMC_BWTR1_DATAST_Pos)            /*!< 0x00000800 */
+#define FMC_BWTR1_DATAST_4          (0x10UL << FMC_BWTR1_DATAST_Pos)            /*!< 0x00001000 */
+#define FMC_BWTR1_DATAST_5          (0x20UL << FMC_BWTR1_DATAST_Pos)            /*!< 0x00002000 */
+#define FMC_BWTR1_DATAST_6          (0x40UL << FMC_BWTR1_DATAST_Pos)            /*!< 0x00004000 */
+#define FMC_BWTR1_DATAST_7          (0x80UL << FMC_BWTR1_DATAST_Pos)            /*!< 0x00008000 */
+
+#define FMC_BWTR1_BUSTURN_Pos       (16U)                                      
+#define FMC_BWTR1_BUSTURN_Msk       (0xFUL << FMC_BWTR1_BUSTURN_Pos)            /*!< 0x000F0000 */
+#define FMC_BWTR1_BUSTURN           FMC_BWTR1_BUSTURN_Msk                      /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
+#define FMC_BWTR1_BUSTURN_0         (0x1UL << FMC_BWTR1_BUSTURN_Pos)            /*!< 0x00010000 */
+#define FMC_BWTR1_BUSTURN_1         (0x2UL << FMC_BWTR1_BUSTURN_Pos)            /*!< 0x00020000 */
+#define FMC_BWTR1_BUSTURN_2         (0x4UL << FMC_BWTR1_BUSTURN_Pos)            /*!< 0x00040000 */
+#define FMC_BWTR1_BUSTURN_3         (0x8UL << FMC_BWTR1_BUSTURN_Pos)            /*!< 0x00080000 */
+
+#define FMC_BWTR1_ACCMOD_Pos        (28U)                                      
+#define FMC_BWTR1_ACCMOD_Msk        (0x3UL << FMC_BWTR1_ACCMOD_Pos)             /*!< 0x30000000 */
+#define FMC_BWTR1_ACCMOD            FMC_BWTR1_ACCMOD_Msk                       /*!<ACCMOD[1:0] bits (Access mode) */
+#define FMC_BWTR1_ACCMOD_0          (0x1UL << FMC_BWTR1_ACCMOD_Pos)             /*!< 0x10000000 */
+#define FMC_BWTR1_ACCMOD_1          (0x2UL << FMC_BWTR1_ACCMOD_Pos)             /*!< 0x20000000 */
+
+/******************  Bit definition for FMC_BWTR2 register  ******************/
+#define FMC_BWTR2_ADDSET_Pos        (0U)                                       
+#define FMC_BWTR2_ADDSET_Msk        (0xFUL << FMC_BWTR2_ADDSET_Pos)             /*!< 0x0000000F */
+#define FMC_BWTR2_ADDSET            FMC_BWTR2_ADDSET_Msk                       /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FMC_BWTR2_ADDSET_0          (0x1UL << FMC_BWTR2_ADDSET_Pos)             /*!< 0x00000001 */
+#define FMC_BWTR2_ADDSET_1          (0x2UL << FMC_BWTR2_ADDSET_Pos)             /*!< 0x00000002 */
+#define FMC_BWTR2_ADDSET_2          (0x4UL << FMC_BWTR2_ADDSET_Pos)             /*!< 0x00000004 */
+#define FMC_BWTR2_ADDSET_3          (0x8UL << FMC_BWTR2_ADDSET_Pos)             /*!< 0x00000008 */
+
+#define FMC_BWTR2_ADDHLD_Pos        (4U)                                       
+#define FMC_BWTR2_ADDHLD_Msk        (0xFUL << FMC_BWTR2_ADDHLD_Pos)             /*!< 0x000000F0 */
+#define FMC_BWTR2_ADDHLD            FMC_BWTR2_ADDHLD_Msk                       /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FMC_BWTR2_ADDHLD_0          (0x1UL << FMC_BWTR2_ADDHLD_Pos)             /*!< 0x00000010 */
+#define FMC_BWTR2_ADDHLD_1          (0x2UL << FMC_BWTR2_ADDHLD_Pos)             /*!< 0x00000020 */
+#define FMC_BWTR2_ADDHLD_2          (0x4UL << FMC_BWTR2_ADDHLD_Pos)             /*!< 0x00000040 */
+#define FMC_BWTR2_ADDHLD_3          (0x8UL << FMC_BWTR2_ADDHLD_Pos)             /*!< 0x00000080 */
+
+#define FMC_BWTR2_DATAST_Pos        (8U)                                       
+#define FMC_BWTR2_DATAST_Msk        (0xFFUL << FMC_BWTR2_DATAST_Pos)            /*!< 0x0000FF00 */
+#define FMC_BWTR2_DATAST            FMC_BWTR2_DATAST_Msk                       /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FMC_BWTR2_DATAST_0          (0x01UL << FMC_BWTR2_DATAST_Pos)            /*!< 0x00000100 */
+#define FMC_BWTR2_DATAST_1          (0x02UL << FMC_BWTR2_DATAST_Pos)            /*!< 0x00000200 */
+#define FMC_BWTR2_DATAST_2          (0x04UL << FMC_BWTR2_DATAST_Pos)            /*!< 0x00000400 */
+#define FMC_BWTR2_DATAST_3          (0x08UL << FMC_BWTR2_DATAST_Pos)            /*!< 0x00000800 */
+#define FMC_BWTR2_DATAST_4          (0x10UL << FMC_BWTR2_DATAST_Pos)            /*!< 0x00001000 */
+#define FMC_BWTR2_DATAST_5          (0x20UL << FMC_BWTR2_DATAST_Pos)            /*!< 0x00002000 */
+#define FMC_BWTR2_DATAST_6          (0x40UL << FMC_BWTR2_DATAST_Pos)            /*!< 0x00004000 */
+#define FMC_BWTR2_DATAST_7          (0x80UL << FMC_BWTR2_DATAST_Pos)            /*!< 0x00008000 */
+
+#define FMC_BWTR2_BUSTURN_Pos       (16U)                                      
+#define FMC_BWTR2_BUSTURN_Msk       (0xFUL << FMC_BWTR2_BUSTURN_Pos)            /*!< 0x000F0000 */
+#define FMC_BWTR2_BUSTURN           FMC_BWTR2_BUSTURN_Msk                      /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
+#define FMC_BWTR2_BUSTURN_0         (0x1UL << FMC_BWTR2_BUSTURN_Pos)            /*!< 0x00010000 */
+#define FMC_BWTR2_BUSTURN_1         (0x2UL << FMC_BWTR2_BUSTURN_Pos)            /*!< 0x00020000 */
+#define FMC_BWTR2_BUSTURN_2         (0x4UL << FMC_BWTR2_BUSTURN_Pos)            /*!< 0x00040000 */
+#define FMC_BWTR2_BUSTURN_3         (0x8UL << FMC_BWTR2_BUSTURN_Pos)            /*!< 0x00080000 */
+
+#define FMC_BWTR2_ACCMOD_Pos        (28U)                                      
+#define FMC_BWTR2_ACCMOD_Msk        (0x3UL << FMC_BWTR2_ACCMOD_Pos)             /*!< 0x30000000 */
+#define FMC_BWTR2_ACCMOD            FMC_BWTR2_ACCMOD_Msk                       /*!<ACCMOD[1:0] bits (Access mode) */
+#define FMC_BWTR2_ACCMOD_0          (0x1UL << FMC_BWTR2_ACCMOD_Pos)             /*!< 0x10000000 */
+#define FMC_BWTR2_ACCMOD_1          (0x2UL << FMC_BWTR2_ACCMOD_Pos)             /*!< 0x20000000 */
+
+/******************  Bit definition for FMC_BWTR3 register  ******************/
+#define FMC_BWTR3_ADDSET_Pos        (0U)                                       
+#define FMC_BWTR3_ADDSET_Msk        (0xFUL << FMC_BWTR3_ADDSET_Pos)             /*!< 0x0000000F */
+#define FMC_BWTR3_ADDSET            FMC_BWTR3_ADDSET_Msk                       /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FMC_BWTR3_ADDSET_0          (0x1UL << FMC_BWTR3_ADDSET_Pos)             /*!< 0x00000001 */
+#define FMC_BWTR3_ADDSET_1          (0x2UL << FMC_BWTR3_ADDSET_Pos)             /*!< 0x00000002 */
+#define FMC_BWTR3_ADDSET_2          (0x4UL << FMC_BWTR3_ADDSET_Pos)             /*!< 0x00000004 */
+#define FMC_BWTR3_ADDSET_3          (0x8UL << FMC_BWTR3_ADDSET_Pos)             /*!< 0x00000008 */
+
+#define FMC_BWTR3_ADDHLD_Pos        (4U)                                       
+#define FMC_BWTR3_ADDHLD_Msk        (0xFUL << FMC_BWTR3_ADDHLD_Pos)             /*!< 0x000000F0 */
+#define FMC_BWTR3_ADDHLD            FMC_BWTR3_ADDHLD_Msk                       /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FMC_BWTR3_ADDHLD_0          (0x1UL << FMC_BWTR3_ADDHLD_Pos)             /*!< 0x00000010 */
+#define FMC_BWTR3_ADDHLD_1          (0x2UL << FMC_BWTR3_ADDHLD_Pos)             /*!< 0x00000020 */
+#define FMC_BWTR3_ADDHLD_2          (0x4UL << FMC_BWTR3_ADDHLD_Pos)             /*!< 0x00000040 */
+#define FMC_BWTR3_ADDHLD_3          (0x8UL << FMC_BWTR3_ADDHLD_Pos)             /*!< 0x00000080 */
+
+#define FMC_BWTR3_DATAST_Pos        (8U)                                       
+#define FMC_BWTR3_DATAST_Msk        (0xFFUL << FMC_BWTR3_DATAST_Pos)            /*!< 0x0000FF00 */
+#define FMC_BWTR3_DATAST            FMC_BWTR3_DATAST_Msk                       /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FMC_BWTR3_DATAST_0          (0x01UL << FMC_BWTR3_DATAST_Pos)            /*!< 0x00000100 */
+#define FMC_BWTR3_DATAST_1          (0x02UL << FMC_BWTR3_DATAST_Pos)            /*!< 0x00000200 */
+#define FMC_BWTR3_DATAST_2          (0x04UL << FMC_BWTR3_DATAST_Pos)            /*!< 0x00000400 */
+#define FMC_BWTR3_DATAST_3          (0x08UL << FMC_BWTR3_DATAST_Pos)            /*!< 0x00000800 */
+#define FMC_BWTR3_DATAST_4          (0x10UL << FMC_BWTR3_DATAST_Pos)            /*!< 0x00001000 */
+#define FMC_BWTR3_DATAST_5          (0x20UL << FMC_BWTR3_DATAST_Pos)            /*!< 0x00002000 */
+#define FMC_BWTR3_DATAST_6          (0x40UL << FMC_BWTR3_DATAST_Pos)            /*!< 0x00004000 */
+#define FMC_BWTR3_DATAST_7          (0x80UL << FMC_BWTR3_DATAST_Pos)            /*!< 0x00008000 */
+
+#define FMC_BWTR3_BUSTURN_Pos       (16U)                                      
+#define FMC_BWTR3_BUSTURN_Msk       (0xFUL << FMC_BWTR3_BUSTURN_Pos)            /*!< 0x000F0000 */
+#define FMC_BWTR3_BUSTURN           FMC_BWTR3_BUSTURN_Msk                      /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
+#define FMC_BWTR3_BUSTURN_0         (0x1UL << FMC_BWTR3_BUSTURN_Pos)            /*!< 0x00010000 */
+#define FMC_BWTR3_BUSTURN_1         (0x2UL << FMC_BWTR3_BUSTURN_Pos)            /*!< 0x00020000 */
+#define FMC_BWTR3_BUSTURN_2         (0x4UL << FMC_BWTR3_BUSTURN_Pos)            /*!< 0x00040000 */
+#define FMC_BWTR3_BUSTURN_3         (0x8UL << FMC_BWTR3_BUSTURN_Pos)            /*!< 0x00080000 */
+
+#define FMC_BWTR3_ACCMOD_Pos        (28U)                                      
+#define FMC_BWTR3_ACCMOD_Msk        (0x3UL << FMC_BWTR3_ACCMOD_Pos)             /*!< 0x30000000 */
+#define FMC_BWTR3_ACCMOD            FMC_BWTR3_ACCMOD_Msk                       /*!<ACCMOD[1:0] bits (Access mode) */
+#define FMC_BWTR3_ACCMOD_0          (0x1UL << FMC_BWTR3_ACCMOD_Pos)             /*!< 0x10000000 */
+#define FMC_BWTR3_ACCMOD_1          (0x2UL << FMC_BWTR3_ACCMOD_Pos)             /*!< 0x20000000 */
+
+/******************  Bit definition for FMC_BWTR4 register  ******************/
+#define FMC_BWTR4_ADDSET_Pos        (0U)                                       
+#define FMC_BWTR4_ADDSET_Msk        (0xFUL << FMC_BWTR4_ADDSET_Pos)             /*!< 0x0000000F */
+#define FMC_BWTR4_ADDSET            FMC_BWTR4_ADDSET_Msk                       /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FMC_BWTR4_ADDSET_0          (0x1UL << FMC_BWTR4_ADDSET_Pos)             /*!< 0x00000001 */
+#define FMC_BWTR4_ADDSET_1          (0x2UL << FMC_BWTR4_ADDSET_Pos)             /*!< 0x00000002 */
+#define FMC_BWTR4_ADDSET_2          (0x4UL << FMC_BWTR4_ADDSET_Pos)             /*!< 0x00000004 */
+#define FMC_BWTR4_ADDSET_3          (0x8UL << FMC_BWTR4_ADDSET_Pos)             /*!< 0x00000008 */
+
+#define FMC_BWTR4_ADDHLD_Pos        (4U)                                       
+#define FMC_BWTR4_ADDHLD_Msk        (0xFUL << FMC_BWTR4_ADDHLD_Pos)             /*!< 0x000000F0 */
+#define FMC_BWTR4_ADDHLD            FMC_BWTR4_ADDHLD_Msk                       /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FMC_BWTR4_ADDHLD_0          (0x1UL << FMC_BWTR4_ADDHLD_Pos)             /*!< 0x00000010 */
+#define FMC_BWTR4_ADDHLD_1          (0x2UL << FMC_BWTR4_ADDHLD_Pos)             /*!< 0x00000020 */
+#define FMC_BWTR4_ADDHLD_2          (0x4UL << FMC_BWTR4_ADDHLD_Pos)             /*!< 0x00000040 */
+#define FMC_BWTR4_ADDHLD_3          (0x8UL << FMC_BWTR4_ADDHLD_Pos)             /*!< 0x00000080 */
+
+#define FMC_BWTR4_DATAST_Pos        (8U)                                       
+#define FMC_BWTR4_DATAST_Msk        (0xFFUL << FMC_BWTR4_DATAST_Pos)            /*!< 0x0000FF00 */
+#define FMC_BWTR4_DATAST            FMC_BWTR4_DATAST_Msk                       /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FMC_BWTR4_DATAST_0          (0x01UL << FMC_BWTR4_DATAST_Pos)            /*!< 0x00000100 */
+#define FMC_BWTR4_DATAST_1          (0x02UL << FMC_BWTR4_DATAST_Pos)            /*!< 0x00000200 */
+#define FMC_BWTR4_DATAST_2          (0x04UL << FMC_BWTR4_DATAST_Pos)            /*!< 0x00000400 */
+#define FMC_BWTR4_DATAST_3          (0x08UL << FMC_BWTR4_DATAST_Pos)            /*!< 0x00000800 */
+#define FMC_BWTR4_DATAST_4          (0x10UL << FMC_BWTR4_DATAST_Pos)            /*!< 0x00001000 */
+#define FMC_BWTR4_DATAST_5          (0x20UL << FMC_BWTR4_DATAST_Pos)            /*!< 0x00002000 */
+#define FMC_BWTR4_DATAST_6          (0x40UL << FMC_BWTR4_DATAST_Pos)            /*!< 0x00004000 */
+#define FMC_BWTR4_DATAST_7          (0x80UL << FMC_BWTR4_DATAST_Pos)            /*!< 0x00008000 */
+
+#define FMC_BWTR4_BUSTURN_Pos       (16U)                                      
+#define FMC_BWTR4_BUSTURN_Msk       (0xFUL << FMC_BWTR4_BUSTURN_Pos)            /*!< 0x000F0000 */
+#define FMC_BWTR4_BUSTURN           FMC_BWTR4_BUSTURN_Msk                      /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
+#define FMC_BWTR4_BUSTURN_0         (0x1UL << FMC_BWTR4_BUSTURN_Pos)            /*!< 0x00010000 */
+#define FMC_BWTR4_BUSTURN_1         (0x2UL << FMC_BWTR4_BUSTURN_Pos)            /*!< 0x00020000 */
+#define FMC_BWTR4_BUSTURN_2         (0x4UL << FMC_BWTR4_BUSTURN_Pos)            /*!< 0x00040000 */
+#define FMC_BWTR4_BUSTURN_3         (0x8UL << FMC_BWTR4_BUSTURN_Pos)            /*!< 0x00080000 */
+
+#define FMC_BWTR4_ACCMOD_Pos        (28U)                                      
+#define FMC_BWTR4_ACCMOD_Msk        (0x3UL << FMC_BWTR4_ACCMOD_Pos)             /*!< 0x30000000 */
+#define FMC_BWTR4_ACCMOD            FMC_BWTR4_ACCMOD_Msk                       /*!<ACCMOD[1:0] bits (Access mode) */
+#define FMC_BWTR4_ACCMOD_0          (0x1UL << FMC_BWTR4_ACCMOD_Pos)             /*!< 0x10000000 */
+#define FMC_BWTR4_ACCMOD_1          (0x2UL << FMC_BWTR4_ACCMOD_Pos)             /*!< 0x20000000 */
+
+/******************  Bit definition for FMC_PCR register  *******************/
+#define FMC_PCR_PWAITEN_Pos         (1U)                                       
+#define FMC_PCR_PWAITEN_Msk         (0x1UL << FMC_PCR_PWAITEN_Pos)              /*!< 0x00000002 */
+#define FMC_PCR_PWAITEN             FMC_PCR_PWAITEN_Msk                        /*!<Wait feature enable bit                   */
+#define FMC_PCR_PBKEN_Pos           (2U)                                       
+#define FMC_PCR_PBKEN_Msk           (0x1UL << FMC_PCR_PBKEN_Pos)                /*!< 0x00000004 */
+#define FMC_PCR_PBKEN               FMC_PCR_PBKEN_Msk                          /*!<PC Card/NAND Flash memory bank enable bit */
+#define FMC_PCR_PTYP_Pos            (3U)                                       
+#define FMC_PCR_PTYP_Msk            (0x1UL << FMC_PCR_PTYP_Pos)                 /*!< 0x00000008 */
+#define FMC_PCR_PTYP                FMC_PCR_PTYP_Msk                           /*!<Memory type                               */
+
+#define FMC_PCR_PWID_Pos            (4U)                                       
+#define FMC_PCR_PWID_Msk            (0x3UL << FMC_PCR_PWID_Pos)                 /*!< 0x00000030 */
+#define FMC_PCR_PWID                FMC_PCR_PWID_Msk                           /*!<PWID[1:0] bits (NAND Flash databus width) */
+#define FMC_PCR_PWID_0              (0x1UL << FMC_PCR_PWID_Pos)                 /*!< 0x00000010 */
+#define FMC_PCR_PWID_1              (0x2UL << FMC_PCR_PWID_Pos)                 /*!< 0x00000020 */
+
+#define FMC_PCR_ECCEN_Pos           (6U)                                       
+#define FMC_PCR_ECCEN_Msk           (0x1UL << FMC_PCR_ECCEN_Pos)                /*!< 0x00000040 */
+#define FMC_PCR_ECCEN               FMC_PCR_ECCEN_Msk                          /*!<ECC computation logic enable bit          */
+
+#define FMC_PCR_TCLR_Pos            (9U)                                       
+#define FMC_PCR_TCLR_Msk            (0xFUL << FMC_PCR_TCLR_Pos)                 /*!< 0x00001E00 */
+#define FMC_PCR_TCLR                FMC_PCR_TCLR_Msk                           /*!<TCLR[3:0] bits (CLE to RE delay)          */
+#define FMC_PCR_TCLR_0              (0x1UL << FMC_PCR_TCLR_Pos)                 /*!< 0x00000200 */
+#define FMC_PCR_TCLR_1              (0x2UL << FMC_PCR_TCLR_Pos)                 /*!< 0x00000400 */
+#define FMC_PCR_TCLR_2              (0x4UL << FMC_PCR_TCLR_Pos)                 /*!< 0x00000800 */
+#define FMC_PCR_TCLR_3              (0x8UL << FMC_PCR_TCLR_Pos)                 /*!< 0x00001000 */
+
+#define FMC_PCR_TAR_Pos             (13U)                                      
+#define FMC_PCR_TAR_Msk             (0xFUL << FMC_PCR_TAR_Pos)                  /*!< 0x0001E000 */
+#define FMC_PCR_TAR                 FMC_PCR_TAR_Msk                            /*!<TAR[3:0] bits (ALE to RE delay)           */
+#define FMC_PCR_TAR_0               (0x1UL << FMC_PCR_TAR_Pos)                  /*!< 0x00002000 */
+#define FMC_PCR_TAR_1               (0x2UL << FMC_PCR_TAR_Pos)                  /*!< 0x00004000 */
+#define FMC_PCR_TAR_2               (0x4UL << FMC_PCR_TAR_Pos)                  /*!< 0x00008000 */
+#define FMC_PCR_TAR_3               (0x8UL << FMC_PCR_TAR_Pos)                  /*!< 0x00010000 */
+
+#define FMC_PCR_ECCPS_Pos           (17U)                                      
+#define FMC_PCR_ECCPS_Msk           (0x7UL << FMC_PCR_ECCPS_Pos)                /*!< 0x000E0000 */
+#define FMC_PCR_ECCPS               FMC_PCR_ECCPS_Msk                          /*!<ECCPS[1:0] bits (ECC page size)           */
+#define FMC_PCR_ECCPS_0             (0x1UL << FMC_PCR_ECCPS_Pos)                /*!< 0x00020000 */
+#define FMC_PCR_ECCPS_1             (0x2UL << FMC_PCR_ECCPS_Pos)                /*!< 0x00040000 */
+#define FMC_PCR_ECCPS_2             (0x4UL << FMC_PCR_ECCPS_Pos)                /*!< 0x00080000 */
+
+/*******************  Bit definition for FMC_SR register  *******************/
+#define FMC_SR_IRS_Pos              (0U)                                       
+#define FMC_SR_IRS_Msk              (0x1UL << FMC_SR_IRS_Pos)                   /*!< 0x00000001 */
+#define FMC_SR_IRS                  FMC_SR_IRS_Msk                             /*!<Interrupt Rising Edge status                */
+#define FMC_SR_ILS_Pos              (1U)                                       
+#define FMC_SR_ILS_Msk              (0x1UL << FMC_SR_ILS_Pos)                   /*!< 0x00000002 */
+#define FMC_SR_ILS                  FMC_SR_ILS_Msk                             /*!<Interrupt Level status                      */
+#define FMC_SR_IFS_Pos              (2U)                                       
+#define FMC_SR_IFS_Msk              (0x1UL << FMC_SR_IFS_Pos)                   /*!< 0x00000004 */
+#define FMC_SR_IFS                  FMC_SR_IFS_Msk                             /*!<Interrupt Falling Edge status               */
+#define FMC_SR_IREN_Pos             (3U)                                       
+#define FMC_SR_IREN_Msk             (0x1UL << FMC_SR_IREN_Pos)                  /*!< 0x00000008 */
+#define FMC_SR_IREN                 FMC_SR_IREN_Msk                            /*!<Interrupt Rising Edge detection Enable bit  */
+#define FMC_SR_ILEN_Pos             (4U)                                       
+#define FMC_SR_ILEN_Msk             (0x1UL << FMC_SR_ILEN_Pos)                  /*!< 0x00000010 */
+#define FMC_SR_ILEN                 FMC_SR_ILEN_Msk                            /*!<Interrupt Level detection Enable bit        */
+#define FMC_SR_IFEN_Pos             (5U)                                       
+#define FMC_SR_IFEN_Msk             (0x1UL << FMC_SR_IFEN_Pos)                  /*!< 0x00000020 */
+#define FMC_SR_IFEN                 FMC_SR_IFEN_Msk                            /*!<Interrupt Falling Edge detection Enable bit */
+#define FMC_SR_FEMPT_Pos            (6U)                                       
+#define FMC_SR_FEMPT_Msk            (0x1UL << FMC_SR_FEMPT_Pos)                 /*!< 0x00000040 */
+#define FMC_SR_FEMPT                FMC_SR_FEMPT_Msk                           /*!<FIFO empty                                  */
+
+/******************  Bit definition for FMC_PMEM register  ******************/
+#define FMC_PMEM_MEMSET2_Pos        (0U)                                       
+#define FMC_PMEM_MEMSET2_Msk        (0xFFUL << FMC_PMEM_MEMSET2_Pos)            /*!< 0x000000FF */
+#define FMC_PMEM_MEMSET2            FMC_PMEM_MEMSET2_Msk                       /*!<MEMSET2[7:0] bits (Common memory 2 setup time) */
+#define FMC_PMEM_MEMSET2_0          (0x01UL << FMC_PMEM_MEMSET2_Pos)            /*!< 0x00000001 */
+#define FMC_PMEM_MEMSET2_1          (0x02UL << FMC_PMEM_MEMSET2_Pos)            /*!< 0x00000002 */
+#define FMC_PMEM_MEMSET2_2          (0x04UL << FMC_PMEM_MEMSET2_Pos)            /*!< 0x00000004 */
+#define FMC_PMEM_MEMSET2_3          (0x08UL << FMC_PMEM_MEMSET2_Pos)            /*!< 0x00000008 */
+#define FMC_PMEM_MEMSET2_4          (0x10UL << FMC_PMEM_MEMSET2_Pos)            /*!< 0x00000010 */
+#define FMC_PMEM_MEMSET2_5          (0x20UL << FMC_PMEM_MEMSET2_Pos)            /*!< 0x00000020 */
+#define FMC_PMEM_MEMSET2_6          (0x40UL << FMC_PMEM_MEMSET2_Pos)            /*!< 0x00000040 */
+#define FMC_PMEM_MEMSET2_7          (0x80UL << FMC_PMEM_MEMSET2_Pos)            /*!< 0x00000080 */
+
+#define FMC_PMEM_MEMWAIT2_Pos       (8U)                                       
+#define FMC_PMEM_MEMWAIT2_Msk       (0xFFUL << FMC_PMEM_MEMWAIT2_Pos)           /*!< 0x0000FF00 */
+#define FMC_PMEM_MEMWAIT2           FMC_PMEM_MEMWAIT2_Msk                      /*!<MEMWAIT2[7:0] bits (Common memory 2 wait time) */
+#define FMC_PMEM_MEMWAIT2_0         (0x01UL << FMC_PMEM_MEMWAIT2_Pos)           /*!< 0x00000100 */
+#define FMC_PMEM_MEMWAIT2_1         (0x02UL << FMC_PMEM_MEMWAIT2_Pos)           /*!< 0x00000200 */
+#define FMC_PMEM_MEMWAIT2_2         (0x04UL << FMC_PMEM_MEMWAIT2_Pos)           /*!< 0x00000400 */
+#define FMC_PMEM_MEMWAIT2_3         (0x08UL << FMC_PMEM_MEMWAIT2_Pos)           /*!< 0x00000800 */
+#define FMC_PMEM_MEMWAIT2_4         (0x10UL << FMC_PMEM_MEMWAIT2_Pos)           /*!< 0x00001000 */
+#define FMC_PMEM_MEMWAIT2_5         (0x20UL << FMC_PMEM_MEMWAIT2_Pos)           /*!< 0x00002000 */
+#define FMC_PMEM_MEMWAIT2_6         (0x40UL << FMC_PMEM_MEMWAIT2_Pos)           /*!< 0x00004000 */
+#define FMC_PMEM_MEMWAIT2_7         (0x80UL << FMC_PMEM_MEMWAIT2_Pos)           /*!< 0x00008000 */
+
+#define FMC_PMEM_MEMHOLD2_Pos       (16U)                                      
+#define FMC_PMEM_MEMHOLD2_Msk       (0xFFUL << FMC_PMEM_MEMHOLD2_Pos)           /*!< 0x00FF0000 */
+#define FMC_PMEM_MEMHOLD2           FMC_PMEM_MEMHOLD2_Msk                      /*!<MEMHOLD2[7:0] bits (Common memory 2 hold time) */
+#define FMC_PMEM_MEMHOLD2_0         (0x01UL << FMC_PMEM_MEMHOLD2_Pos)           /*!< 0x00010000 */
+#define FMC_PMEM_MEMHOLD2_1         (0x02UL << FMC_PMEM_MEMHOLD2_Pos)           /*!< 0x00020000 */
+#define FMC_PMEM_MEMHOLD2_2         (0x04UL << FMC_PMEM_MEMHOLD2_Pos)           /*!< 0x00040000 */
+#define FMC_PMEM_MEMHOLD2_3         (0x08UL << FMC_PMEM_MEMHOLD2_Pos)           /*!< 0x00080000 */
+#define FMC_PMEM_MEMHOLD2_4         (0x10UL << FMC_PMEM_MEMHOLD2_Pos)           /*!< 0x00100000 */
+#define FMC_PMEM_MEMHOLD2_5         (0x20UL << FMC_PMEM_MEMHOLD2_Pos)           /*!< 0x00200000 */
+#define FMC_PMEM_MEMHOLD2_6         (0x40UL << FMC_PMEM_MEMHOLD2_Pos)           /*!< 0x00400000 */
+#define FMC_PMEM_MEMHOLD2_7         (0x80UL << FMC_PMEM_MEMHOLD2_Pos)           /*!< 0x00800000 */
+
+#define FMC_PMEM_MEMHIZ2_Pos        (24U)                                      
+#define FMC_PMEM_MEMHIZ2_Msk        (0xFFUL << FMC_PMEM_MEMHIZ2_Pos)            /*!< 0xFF000000 */
+#define FMC_PMEM_MEMHIZ2            FMC_PMEM_MEMHIZ2_Msk                       /*!<MEMHIZ2[7:0] bits (Common memory 2 databus HiZ time) */
+#define FMC_PMEM_MEMHIZ2_0          (0x01UL << FMC_PMEM_MEMHIZ2_Pos)            /*!< 0x01000000 */
+#define FMC_PMEM_MEMHIZ2_1          (0x02UL << FMC_PMEM_MEMHIZ2_Pos)            /*!< 0x02000000 */
+#define FMC_PMEM_MEMHIZ2_2          (0x04UL << FMC_PMEM_MEMHIZ2_Pos)            /*!< 0x04000000 */
+#define FMC_PMEM_MEMHIZ2_3          (0x08UL << FMC_PMEM_MEMHIZ2_Pos)            /*!< 0x08000000 */
+#define FMC_PMEM_MEMHIZ2_4          (0x10UL << FMC_PMEM_MEMHIZ2_Pos)            /*!< 0x10000000 */
+#define FMC_PMEM_MEMHIZ2_5          (0x20UL << FMC_PMEM_MEMHIZ2_Pos)            /*!< 0x20000000 */
+#define FMC_PMEM_MEMHIZ2_6          (0x40UL << FMC_PMEM_MEMHIZ2_Pos)            /*!< 0x40000000 */
+#define FMC_PMEM_MEMHIZ2_7          (0x80UL << FMC_PMEM_MEMHIZ2_Pos)            /*!< 0x80000000 */
+
+/******************  Bit definition for FMC_PATT register  ******************/
+#define FMC_PATT_ATTSET2_Pos        (0U)                                       
+#define FMC_PATT_ATTSET2_Msk        (0xFFUL << FMC_PATT_ATTSET2_Pos)            /*!< 0x000000FF */
+#define FMC_PATT_ATTSET2            FMC_PATT_ATTSET2_Msk                       /*!<ATTSET2[7:0] bits (Attribute memory 2 setup time) */
+#define FMC_PATT_ATTSET2_0          (0x01UL << FMC_PATT_ATTSET2_Pos)            /*!< 0x00000001 */
+#define FMC_PATT_ATTSET2_1          (0x02UL << FMC_PATT_ATTSET2_Pos)            /*!< 0x00000002 */
+#define FMC_PATT_ATTSET2_2          (0x04UL << FMC_PATT_ATTSET2_Pos)            /*!< 0x00000004 */
+#define FMC_PATT_ATTSET2_3          (0x08UL << FMC_PATT_ATTSET2_Pos)            /*!< 0x00000008 */
+#define FMC_PATT_ATTSET2_4          (0x10UL << FMC_PATT_ATTSET2_Pos)            /*!< 0x00000010 */
+#define FMC_PATT_ATTSET2_5          (0x20UL << FMC_PATT_ATTSET2_Pos)            /*!< 0x00000020 */
+#define FMC_PATT_ATTSET2_6          (0x40UL << FMC_PATT_ATTSET2_Pos)            /*!< 0x00000040 */
+#define FMC_PATT_ATTSET2_7          (0x80UL << FMC_PATT_ATTSET2_Pos)            /*!< 0x00000080 */
+
+#define FMC_PATT_ATTWAIT2_Pos       (8U)                                       
+#define FMC_PATT_ATTWAIT2_Msk       (0xFFUL << FMC_PATT_ATTWAIT2_Pos)           /*!< 0x0000FF00 */
+#define FMC_PATT_ATTWAIT2           FMC_PATT_ATTWAIT2_Msk                      /*!<ATTWAIT2[7:0] bits (Attribute memory 2 wait time) */
+#define FMC_PATT_ATTWAIT2_0         (0x01UL << FMC_PATT_ATTWAIT2_Pos)           /*!< 0x00000100 */
+#define FMC_PATT_ATTWAIT2_1         (0x02UL << FMC_PATT_ATTWAIT2_Pos)           /*!< 0x00000200 */
+#define FMC_PATT_ATTWAIT2_2         (0x04UL << FMC_PATT_ATTWAIT2_Pos)           /*!< 0x00000400 */
+#define FMC_PATT_ATTWAIT2_3         (0x08UL << FMC_PATT_ATTWAIT2_Pos)           /*!< 0x00000800 */
+#define FMC_PATT_ATTWAIT2_4         (0x10UL << FMC_PATT_ATTWAIT2_Pos)           /*!< 0x00001000 */
+#define FMC_PATT_ATTWAIT2_5         (0x20UL << FMC_PATT_ATTWAIT2_Pos)           /*!< 0x00002000 */
+#define FMC_PATT_ATTWAIT2_6         (0x40UL << FMC_PATT_ATTWAIT2_Pos)           /*!< 0x00004000 */
+#define FMC_PATT_ATTWAIT2_7         (0x80UL << FMC_PATT_ATTWAIT2_Pos)           /*!< 0x00008000 */
+
+#define FMC_PATT_ATTHOLD2_Pos       (16U)                                      
+#define FMC_PATT_ATTHOLD2_Msk       (0xFFUL << FMC_PATT_ATTHOLD2_Pos)           /*!< 0x00FF0000 */
+#define FMC_PATT_ATTHOLD2           FMC_PATT_ATTHOLD2_Msk                      /*!<ATTHOLD2[7:0] bits (Attribute memory 2 hold time) */
+#define FMC_PATT_ATTHOLD2_0         (0x01UL << FMC_PATT_ATTHOLD2_Pos)           /*!< 0x00010000 */
+#define FMC_PATT_ATTHOLD2_1         (0x02UL << FMC_PATT_ATTHOLD2_Pos)           /*!< 0x00020000 */
+#define FMC_PATT_ATTHOLD2_2         (0x04UL << FMC_PATT_ATTHOLD2_Pos)           /*!< 0x00040000 */
+#define FMC_PATT_ATTHOLD2_3         (0x08UL << FMC_PATT_ATTHOLD2_Pos)           /*!< 0x00080000 */
+#define FMC_PATT_ATTHOLD2_4         (0x10UL << FMC_PATT_ATTHOLD2_Pos)           /*!< 0x00100000 */
+#define FMC_PATT_ATTHOLD2_5         (0x20UL << FMC_PATT_ATTHOLD2_Pos)           /*!< 0x00200000 */
+#define FMC_PATT_ATTHOLD2_6         (0x40UL << FMC_PATT_ATTHOLD2_Pos)           /*!< 0x00400000 */
+#define FMC_PATT_ATTHOLD2_7         (0x80UL << FMC_PATT_ATTHOLD2_Pos)           /*!< 0x00800000 */
+
+#define FMC_PATT_ATTHIZ2_Pos        (24U)                                      
+#define FMC_PATT_ATTHIZ2_Msk        (0xFFUL << FMC_PATT_ATTHIZ2_Pos)            /*!< 0xFF000000 */
+#define FMC_PATT_ATTHIZ2            FMC_PATT_ATTHIZ2_Msk                       /*!<ATTHIZ2[7:0] bits (Attribute memory 2 databus HiZ time) */
+#define FMC_PATT_ATTHIZ2_0          (0x01UL << FMC_PATT_ATTHIZ2_Pos)            /*!< 0x01000000 */
+#define FMC_PATT_ATTHIZ2_1          (0x02UL << FMC_PATT_ATTHIZ2_Pos)            /*!< 0x02000000 */
+#define FMC_PATT_ATTHIZ2_2          (0x04UL << FMC_PATT_ATTHIZ2_Pos)            /*!< 0x04000000 */
+#define FMC_PATT_ATTHIZ2_3          (0x08UL << FMC_PATT_ATTHIZ2_Pos)            /*!< 0x08000000 */
+#define FMC_PATT_ATTHIZ2_4          (0x10UL << FMC_PATT_ATTHIZ2_Pos)            /*!< 0x10000000 */
+#define FMC_PATT_ATTHIZ2_5          (0x20UL << FMC_PATT_ATTHIZ2_Pos)            /*!< 0x20000000 */
+#define FMC_PATT_ATTHIZ2_6          (0x40UL << FMC_PATT_ATTHIZ2_Pos)            /*!< 0x40000000 */
+#define FMC_PATT_ATTHIZ2_7          (0x80UL << FMC_PATT_ATTHIZ2_Pos)            /*!< 0x80000000 */
+
+/******************  Bit definition for FMC_ECCR register  ******************/
+#define FMC_ECCR_ECC2_Pos           (0U)                                       
+#define FMC_ECCR_ECC2_Msk           (0xFFFFFFFFUL << FMC_ECCR_ECC2_Pos)         /*!< 0xFFFFFFFF */
+#define FMC_ECCR_ECC2               FMC_ECCR_ECC2_Msk                          /*!<ECC result */
+
+/******************  Bit definition for FMC_SDCR1 register  ******************/
+#define FMC_SDCR1_NC_Pos            (0U)                                       
+#define FMC_SDCR1_NC_Msk            (0x3UL << FMC_SDCR1_NC_Pos)                 /*!< 0x00000003 */
+#define FMC_SDCR1_NC                FMC_SDCR1_NC_Msk                           /*!<NC[1:0] bits (Number of column bits) */
+#define FMC_SDCR1_NC_0              (0x1UL << FMC_SDCR1_NC_Pos)                 /*!< 0x00000001 */
+#define FMC_SDCR1_NC_1              (0x2UL << FMC_SDCR1_NC_Pos)                 /*!< 0x00000002 */
+
+#define FMC_SDCR1_NR_Pos            (2U)                                       
+#define FMC_SDCR1_NR_Msk            (0x3UL << FMC_SDCR1_NR_Pos)                 /*!< 0x0000000C */
+#define FMC_SDCR1_NR                FMC_SDCR1_NR_Msk                           /*!<NR[1:0] bits (Number of row bits) */
+#define FMC_SDCR1_NR_0              (0x1UL << FMC_SDCR1_NR_Pos)                 /*!< 0x00000004 */
+#define FMC_SDCR1_NR_1              (0x2UL << FMC_SDCR1_NR_Pos)                 /*!< 0x00000008 */
+
+#define FMC_SDCR1_MWID_Pos          (4U)                                       
+#define FMC_SDCR1_MWID_Msk          (0x3UL << FMC_SDCR1_MWID_Pos)               /*!< 0x00000030 */
+#define FMC_SDCR1_MWID              FMC_SDCR1_MWID_Msk                         /*!<NR[1:0] bits (Number of row bits) */
+#define FMC_SDCR1_MWID_0            (0x1UL << FMC_SDCR1_MWID_Pos)               /*!< 0x00000010 */
+#define FMC_SDCR1_MWID_1            (0x2UL << FMC_SDCR1_MWID_Pos)               /*!< 0x00000020 */
+
+#define FMC_SDCR1_NB_Pos            (6U)                                       
+#define FMC_SDCR1_NB_Msk            (0x1UL << FMC_SDCR1_NB_Pos)                 /*!< 0x00000040 */
+#define FMC_SDCR1_NB                FMC_SDCR1_NB_Msk                           /*!<Number of internal bank */
+
+#define FMC_SDCR1_CAS_Pos           (7U)                                       
+#define FMC_SDCR1_CAS_Msk           (0x3UL << FMC_SDCR1_CAS_Pos)                /*!< 0x00000180 */
+#define FMC_SDCR1_CAS               FMC_SDCR1_CAS_Msk                          /*!<CAS[1:0] bits (CAS latency) */
+#define FMC_SDCR1_CAS_0             (0x1UL << FMC_SDCR1_CAS_Pos)                /*!< 0x00000080 */
+#define FMC_SDCR1_CAS_1             (0x2UL << FMC_SDCR1_CAS_Pos)                /*!< 0x00000100 */
+
+#define FMC_SDCR1_WP_Pos            (9U)                                       
+#define FMC_SDCR1_WP_Msk            (0x1UL << FMC_SDCR1_WP_Pos)                 /*!< 0x00000200 */
+#define FMC_SDCR1_WP                FMC_SDCR1_WP_Msk                           /*!<Write protection */
+
+#define FMC_SDCR1_SDCLK_Pos         (10U)                                      
+#define FMC_SDCR1_SDCLK_Msk         (0x3UL << FMC_SDCR1_SDCLK_Pos)              /*!< 0x00000C00 */
+#define FMC_SDCR1_SDCLK             FMC_SDCR1_SDCLK_Msk                        /*!<SDRAM clock configuration */
+#define FMC_SDCR1_SDCLK_0           (0x1UL << FMC_SDCR1_SDCLK_Pos)              /*!< 0x00000400 */
+#define FMC_SDCR1_SDCLK_1           (0x2UL << FMC_SDCR1_SDCLK_Pos)              /*!< 0x00000800 */
+
+#define FMC_SDCR1_RBURST_Pos        (12U)                                      
+#define FMC_SDCR1_RBURST_Msk        (0x1UL << FMC_SDCR1_RBURST_Pos)             /*!< 0x00001000 */
+#define FMC_SDCR1_RBURST            FMC_SDCR1_RBURST_Msk                       /*!<Read burst */
+
+#define FMC_SDCR1_RPIPE_Pos         (13U)                                      
+#define FMC_SDCR1_RPIPE_Msk         (0x3UL << FMC_SDCR1_RPIPE_Pos)              /*!< 0x00006000 */
+#define FMC_SDCR1_RPIPE             FMC_SDCR1_RPIPE_Msk                        /*!<Write protection */
+#define FMC_SDCR1_RPIPE_0           (0x1UL << FMC_SDCR1_RPIPE_Pos)              /*!< 0x00002000 */
+#define FMC_SDCR1_RPIPE_1           (0x2UL << FMC_SDCR1_RPIPE_Pos)              /*!< 0x00004000 */
+
+/******************  Bit definition for FMC_SDCR2 register  ******************/
+#define FMC_SDCR2_NC_Pos            (0U)                                       
+#define FMC_SDCR2_NC_Msk            (0x3UL << FMC_SDCR2_NC_Pos)                 /*!< 0x00000003 */
+#define FMC_SDCR2_NC                FMC_SDCR2_NC_Msk                           /*!<NC[1:0] bits (Number of column bits) */
+#define FMC_SDCR2_NC_0              (0x1UL << FMC_SDCR2_NC_Pos)                 /*!< 0x00000001 */
+#define FMC_SDCR2_NC_1              (0x2UL << FMC_SDCR2_NC_Pos)                 /*!< 0x00000002 */
+
+#define FMC_SDCR2_NR_Pos            (2U)                                       
+#define FMC_SDCR2_NR_Msk            (0x3UL << FMC_SDCR2_NR_Pos)                 /*!< 0x0000000C */
+#define FMC_SDCR2_NR                FMC_SDCR2_NR_Msk                           /*!<NR[1:0] bits (Number of row bits) */
+#define FMC_SDCR2_NR_0              (0x1UL << FMC_SDCR2_NR_Pos)                 /*!< 0x00000004 */
+#define FMC_SDCR2_NR_1              (0x2UL << FMC_SDCR2_NR_Pos)                 /*!< 0x00000008 */
+
+#define FMC_SDCR2_MWID_Pos          (4U)                                       
+#define FMC_SDCR2_MWID_Msk          (0x3UL << FMC_SDCR2_MWID_Pos)               /*!< 0x00000030 */
+#define FMC_SDCR2_MWID              FMC_SDCR2_MWID_Msk                         /*!<NR[1:0] bits (Number of row bits) */
+#define FMC_SDCR2_MWID_0            (0x1UL << FMC_SDCR2_MWID_Pos)               /*!< 0x00000010 */
+#define FMC_SDCR2_MWID_1            (0x2UL << FMC_SDCR2_MWID_Pos)               /*!< 0x00000020 */
+
+#define FMC_SDCR2_NB_Pos            (6U)                                       
+#define FMC_SDCR2_NB_Msk            (0x1UL << FMC_SDCR2_NB_Pos)                 /*!< 0x00000040 */
+#define FMC_SDCR2_NB                FMC_SDCR2_NB_Msk                           /*!<Number of internal bank */
+
+#define FMC_SDCR2_CAS_Pos           (7U)                                       
+#define FMC_SDCR2_CAS_Msk           (0x3UL << FMC_SDCR2_CAS_Pos)                /*!< 0x00000180 */
+#define FMC_SDCR2_CAS               FMC_SDCR2_CAS_Msk                          /*!<CAS[1:0] bits (CAS latency) */
+#define FMC_SDCR2_CAS_0             (0x1UL << FMC_SDCR2_CAS_Pos)                /*!< 0x00000080 */
+#define FMC_SDCR2_CAS_1             (0x2UL << FMC_SDCR2_CAS_Pos)                /*!< 0x00000100 */
+
+#define FMC_SDCR2_WP_Pos            (9U)                                       
+#define FMC_SDCR2_WP_Msk            (0x1UL << FMC_SDCR2_WP_Pos)                 /*!< 0x00000200 */
+#define FMC_SDCR2_WP                FMC_SDCR2_WP_Msk                           /*!<Write protection */
+
+#define FMC_SDCR2_SDCLK_Pos         (10U)                                      
+#define FMC_SDCR2_SDCLK_Msk         (0x3UL << FMC_SDCR2_SDCLK_Pos)              /*!< 0x00000C00 */
+#define FMC_SDCR2_SDCLK             FMC_SDCR2_SDCLK_Msk                        /*!<SDCLK[1:0] (SDRAM clock configuration) */
+#define FMC_SDCR2_SDCLK_0           (0x1UL << FMC_SDCR2_SDCLK_Pos)              /*!< 0x00000400 */
+#define FMC_SDCR2_SDCLK_1           (0x2UL << FMC_SDCR2_SDCLK_Pos)              /*!< 0x00000800 */
+
+#define FMC_SDCR2_RBURST_Pos        (12U)                                      
+#define FMC_SDCR2_RBURST_Msk        (0x1UL << FMC_SDCR2_RBURST_Pos)             /*!< 0x00001000 */
+#define FMC_SDCR2_RBURST            FMC_SDCR2_RBURST_Msk                       /*!<Read burst */
+
+#define FMC_SDCR2_RPIPE_Pos         (13U)                                      
+#define FMC_SDCR2_RPIPE_Msk         (0x3UL << FMC_SDCR2_RPIPE_Pos)              /*!< 0x00006000 */
+#define FMC_SDCR2_RPIPE             FMC_SDCR2_RPIPE_Msk                        /*!<RPIPE[1:0](Read pipe) */
+#define FMC_SDCR2_RPIPE_0           (0x1UL << FMC_SDCR2_RPIPE_Pos)              /*!< 0x00002000 */
+#define FMC_SDCR2_RPIPE_1           (0x2UL << FMC_SDCR2_RPIPE_Pos)              /*!< 0x00004000 */
+
+/******************  Bit definition for FMC_SDTR1 register  ******************/
+#define FMC_SDTR1_TMRD_Pos          (0U)                                       
+#define FMC_SDTR1_TMRD_Msk          (0xFUL << FMC_SDTR1_TMRD_Pos)               /*!< 0x0000000F */
+#define FMC_SDTR1_TMRD              FMC_SDTR1_TMRD_Msk                         /*!<TMRD[3:0] bits (Load mode register to active) */
+#define FMC_SDTR1_TMRD_0            (0x1UL << FMC_SDTR1_TMRD_Pos)               /*!< 0x00000001 */
+#define FMC_SDTR1_TMRD_1            (0x2UL << FMC_SDTR1_TMRD_Pos)               /*!< 0x00000002 */
+#define FMC_SDTR1_TMRD_2            (0x4UL << FMC_SDTR1_TMRD_Pos)               /*!< 0x00000004 */
+#define FMC_SDTR1_TMRD_3            (0x8UL << FMC_SDTR1_TMRD_Pos)               /*!< 0x00000008 */
+                                            
+#define FMC_SDTR1_TXSR_Pos          (4U)                                       
+#define FMC_SDTR1_TXSR_Msk          (0xFUL << FMC_SDTR1_TXSR_Pos)               /*!< 0x000000F0 */
+#define FMC_SDTR1_TXSR              FMC_SDTR1_TXSR_Msk                         /*!<TXSR[3:0] bits (Exit self refresh) */
+#define FMC_SDTR1_TXSR_0            (0x1UL << FMC_SDTR1_TXSR_Pos)               /*!< 0x00000010 */
+#define FMC_SDTR1_TXSR_1            (0x2UL << FMC_SDTR1_TXSR_Pos)               /*!< 0x00000020 */
+#define FMC_SDTR1_TXSR_2            (0x4UL << FMC_SDTR1_TXSR_Pos)               /*!< 0x00000040 */
+#define FMC_SDTR1_TXSR_3            (0x8UL << FMC_SDTR1_TXSR_Pos)               /*!< 0x00000080 */
+
+#define FMC_SDTR1_TRAS_Pos          (8U)                                       
+#define FMC_SDTR1_TRAS_Msk          (0xFUL << FMC_SDTR1_TRAS_Pos)               /*!< 0x00000F00 */
+#define FMC_SDTR1_TRAS              FMC_SDTR1_TRAS_Msk                         /*!<TRAS[3:0] bits (Self refresh time) */
+#define FMC_SDTR1_TRAS_0            (0x1UL << FMC_SDTR1_TRAS_Pos)               /*!< 0x00000100 */
+#define FMC_SDTR1_TRAS_1            (0x2UL << FMC_SDTR1_TRAS_Pos)               /*!< 0x00000200 */
+#define FMC_SDTR1_TRAS_2            (0x4UL << FMC_SDTR1_TRAS_Pos)               /*!< 0x00000400 */
+#define FMC_SDTR1_TRAS_3            (0x8UL << FMC_SDTR1_TRAS_Pos)               /*!< 0x00000800 */
+
+#define FMC_SDTR1_TRC_Pos           (12U)                                      
+#define FMC_SDTR1_TRC_Msk           (0xFUL << FMC_SDTR1_TRC_Pos)                /*!< 0x0000F000 */
+#define FMC_SDTR1_TRC               FMC_SDTR1_TRC_Msk                          /*!<TRC[2:0] bits (Row cycle delay) */
+#define FMC_SDTR1_TRC_0             (0x1UL << FMC_SDTR1_TRC_Pos)                /*!< 0x00001000 */
+#define FMC_SDTR1_TRC_1             (0x2UL << FMC_SDTR1_TRC_Pos)                /*!< 0x00002000 */
+#define FMC_SDTR1_TRC_2             (0x4UL << FMC_SDTR1_TRC_Pos)                /*!< 0x00004000 */
+
+#define FMC_SDTR1_TWR_Pos           (16U)                                      
+#define FMC_SDTR1_TWR_Msk           (0xFUL << FMC_SDTR1_TWR_Pos)                /*!< 0x000F0000 */
+#define FMC_SDTR1_TWR               FMC_SDTR1_TWR_Msk                          /*!<TRC[2:0] bits (Write recovery delay) */
+#define FMC_SDTR1_TWR_0             (0x1UL << FMC_SDTR1_TWR_Pos)                /*!< 0x00010000 */
+#define FMC_SDTR1_TWR_1             (0x2UL << FMC_SDTR1_TWR_Pos)                /*!< 0x00020000 */
+#define FMC_SDTR1_TWR_2             (0x4UL << FMC_SDTR1_TWR_Pos)                /*!< 0x00040000 */
+
+#define FMC_SDTR1_TRP_Pos           (20U)                                      
+#define FMC_SDTR1_TRP_Msk           (0xFUL << FMC_SDTR1_TRP_Pos)                /*!< 0x00F00000 */
+#define FMC_SDTR1_TRP               FMC_SDTR1_TRP_Msk                          /*!<TRP[2:0] bits (Row precharge delay) */
+#define FMC_SDTR1_TRP_0             (0x1UL << FMC_SDTR1_TRP_Pos)                /*!< 0x00100000 */
+#define FMC_SDTR1_TRP_1             (0x2UL << FMC_SDTR1_TRP_Pos)                /*!< 0x00200000 */
+#define FMC_SDTR1_TRP_2             (0x4UL << FMC_SDTR1_TRP_Pos)                /*!< 0x00400000 */
+
+#define FMC_SDTR1_TRCD_Pos          (24U)                                      
+#define FMC_SDTR1_TRCD_Msk          (0xFUL << FMC_SDTR1_TRCD_Pos)               /*!< 0x0F000000 */
+#define FMC_SDTR1_TRCD              FMC_SDTR1_TRCD_Msk                         /*!<TRP[2:0] bits (Row to column delay) */
+#define FMC_SDTR1_TRCD_0            (0x1UL << FMC_SDTR1_TRCD_Pos)               /*!< 0x01000000 */
+#define FMC_SDTR1_TRCD_1            (0x2UL << FMC_SDTR1_TRCD_Pos)               /*!< 0x02000000 */
+#define FMC_SDTR1_TRCD_2            (0x4UL << FMC_SDTR1_TRCD_Pos)               /*!< 0x04000000 */
+
+/******************  Bit definition for FMC_SDTR2 register  ******************/
+#define FMC_SDTR2_TMRD_Pos          (0U)                                       
+#define FMC_SDTR2_TMRD_Msk          (0xFUL << FMC_SDTR2_TMRD_Pos)               /*!< 0x0000000F */
+#define FMC_SDTR2_TMRD              FMC_SDTR2_TMRD_Msk                         /*!<TMRD[3:0] bits (Load mode register to active) */
+#define FMC_SDTR2_TMRD_0            (0x1UL << FMC_SDTR2_TMRD_Pos)               /*!< 0x00000001 */
+#define FMC_SDTR2_TMRD_1            (0x2UL << FMC_SDTR2_TMRD_Pos)               /*!< 0x00000002 */
+#define FMC_SDTR2_TMRD_2            (0x4UL << FMC_SDTR2_TMRD_Pos)               /*!< 0x00000004 */
+#define FMC_SDTR2_TMRD_3            (0x8UL << FMC_SDTR2_TMRD_Pos)               /*!< 0x00000008 */
+                                            
+#define FMC_SDTR2_TXSR_Pos          (4U)                                       
+#define FMC_SDTR2_TXSR_Msk          (0xFUL << FMC_SDTR2_TXSR_Pos)               /*!< 0x000000F0 */
+#define FMC_SDTR2_TXSR              FMC_SDTR2_TXSR_Msk                         /*!<TXSR[3:0] bits (Exit self refresh) */
+#define FMC_SDTR2_TXSR_0            (0x1UL << FMC_SDTR2_TXSR_Pos)               /*!< 0x00000010 */
+#define FMC_SDTR2_TXSR_1            (0x2UL << FMC_SDTR2_TXSR_Pos)               /*!< 0x00000020 */
+#define FMC_SDTR2_TXSR_2            (0x4UL << FMC_SDTR2_TXSR_Pos)               /*!< 0x00000040 */
+#define FMC_SDTR2_TXSR_3            (0x8UL << FMC_SDTR2_TXSR_Pos)               /*!< 0x00000080 */
+
+#define FMC_SDTR2_TRAS_Pos          (8U)                                       
+#define FMC_SDTR2_TRAS_Msk          (0xFUL << FMC_SDTR2_TRAS_Pos)               /*!< 0x00000F00 */
+#define FMC_SDTR2_TRAS              FMC_SDTR2_TRAS_Msk                         /*!<TRAS[3:0] bits (Self refresh time) */
+#define FMC_SDTR2_TRAS_0            (0x1UL << FMC_SDTR2_TRAS_Pos)               /*!< 0x00000100 */
+#define FMC_SDTR2_TRAS_1            (0x2UL << FMC_SDTR2_TRAS_Pos)               /*!< 0x00000200 */
+#define FMC_SDTR2_TRAS_2            (0x4UL << FMC_SDTR2_TRAS_Pos)               /*!< 0x00000400 */
+#define FMC_SDTR2_TRAS_3            (0x8UL << FMC_SDTR2_TRAS_Pos)               /*!< 0x00000800 */
+
+#define FMC_SDTR2_TRC_Pos           (12U)                                      
+#define FMC_SDTR2_TRC_Msk           (0xFUL << FMC_SDTR2_TRC_Pos)                /*!< 0x0000F000 */
+#define FMC_SDTR2_TRC               FMC_SDTR2_TRC_Msk                          /*!<TRC[2:0] bits (Row cycle delay) */
+#define FMC_SDTR2_TRC_0             (0x1UL << FMC_SDTR2_TRC_Pos)                /*!< 0x00001000 */
+#define FMC_SDTR2_TRC_1             (0x2UL << FMC_SDTR2_TRC_Pos)                /*!< 0x00002000 */
+#define FMC_SDTR2_TRC_2             (0x4UL << FMC_SDTR2_TRC_Pos)                /*!< 0x00004000 */
+
+#define FMC_SDTR2_TWR_Pos           (16U)                                      
+#define FMC_SDTR2_TWR_Msk           (0xFUL << FMC_SDTR2_TWR_Pos)                /*!< 0x000F0000 */
+#define FMC_SDTR2_TWR               FMC_SDTR2_TWR_Msk                          /*!<TRC[2:0] bits (Write recovery delay) */
+#define FMC_SDTR2_TWR_0             (0x1UL << FMC_SDTR2_TWR_Pos)                /*!< 0x00010000 */
+#define FMC_SDTR2_TWR_1             (0x2UL << FMC_SDTR2_TWR_Pos)                /*!< 0x00020000 */
+#define FMC_SDTR2_TWR_2             (0x4UL << FMC_SDTR2_TWR_Pos)                /*!< 0x00040000 */
+
+#define FMC_SDTR2_TRP_Pos           (20U)                                      
+#define FMC_SDTR2_TRP_Msk           (0xFUL << FMC_SDTR2_TRP_Pos)                /*!< 0x00F00000 */
+#define FMC_SDTR2_TRP               FMC_SDTR2_TRP_Msk                          /*!<TRP[2:0] bits (Row precharge delay) */
+#define FMC_SDTR2_TRP_0             (0x1UL << FMC_SDTR2_TRP_Pos)                /*!< 0x00100000 */
+#define FMC_SDTR2_TRP_1             (0x2UL << FMC_SDTR2_TRP_Pos)                /*!< 0x00200000 */
+#define FMC_SDTR2_TRP_2             (0x4UL << FMC_SDTR2_TRP_Pos)                /*!< 0x00400000 */
+
+#define FMC_SDTR2_TRCD_Pos          (24U)                                      
+#define FMC_SDTR2_TRCD_Msk          (0xFUL << FMC_SDTR2_TRCD_Pos)               /*!< 0x0F000000 */
+#define FMC_SDTR2_TRCD              FMC_SDTR2_TRCD_Msk                         /*!<TRP[2:0] bits (Row to column delay) */
+#define FMC_SDTR2_TRCD_0            (0x1UL << FMC_SDTR2_TRCD_Pos)               /*!< 0x01000000 */
+#define FMC_SDTR2_TRCD_1            (0x2UL << FMC_SDTR2_TRCD_Pos)               /*!< 0x02000000 */
+#define FMC_SDTR2_TRCD_2            (0x4UL << FMC_SDTR2_TRCD_Pos)               /*!< 0x04000000 */
+
+/******************  Bit definition for FMC_SDCMR register  ******************/
+#define FMC_SDCMR_MODE_Pos          (0U)                                       
+#define FMC_SDCMR_MODE_Msk          (0x7UL << FMC_SDCMR_MODE_Pos)               /*!< 0x00000007 */
+#define FMC_SDCMR_MODE              FMC_SDCMR_MODE_Msk                         /*!<MODE[2:0] bits (Command mode) */
+#define FMC_SDCMR_MODE_0            (0x1UL << FMC_SDCMR_MODE_Pos)               /*!< 0x00000001 */
+#define FMC_SDCMR_MODE_1            (0x2UL << FMC_SDCMR_MODE_Pos)               /*!< 0x00000002 */
+#define FMC_SDCMR_MODE_2            (0x4UL << FMC_SDCMR_MODE_Pos)               /*!< 0x00000004 */
+                                            
+#define FMC_SDCMR_CTB2_Pos          (3U)                                       
+#define FMC_SDCMR_CTB2_Msk          (0x1UL << FMC_SDCMR_CTB2_Pos)               /*!< 0x00000008 */
+#define FMC_SDCMR_CTB2              FMC_SDCMR_CTB2_Msk                         /*!<Command target 2 */
+
+#define FMC_SDCMR_CTB1_Pos          (4U)                                       
+#define FMC_SDCMR_CTB1_Msk          (0x1UL << FMC_SDCMR_CTB1_Pos)               /*!< 0x00000010 */
+#define FMC_SDCMR_CTB1              FMC_SDCMR_CTB1_Msk                         /*!<Command target 1 */
+
+#define FMC_SDCMR_NRFS_Pos          (5U)                                       
+#define FMC_SDCMR_NRFS_Msk          (0xFUL << FMC_SDCMR_NRFS_Pos)               /*!< 0x000001E0 */
+#define FMC_SDCMR_NRFS              FMC_SDCMR_NRFS_Msk                         /*!<NRFS[3:0] bits (Number of auto-refresh) */
+#define FMC_SDCMR_NRFS_0            (0x1UL << FMC_SDCMR_NRFS_Pos)               /*!< 0x00000020 */
+#define FMC_SDCMR_NRFS_1            (0x2UL << FMC_SDCMR_NRFS_Pos)               /*!< 0x00000040 */
+#define FMC_SDCMR_NRFS_2            (0x4UL << FMC_SDCMR_NRFS_Pos)               /*!< 0x00000080 */
+#define FMC_SDCMR_NRFS_3            (0x8UL << FMC_SDCMR_NRFS_Pos)               /*!< 0x00000100 */
+
+#define FMC_SDCMR_MRD_Pos           (9U)                                       
+#define FMC_SDCMR_MRD_Msk           (0x1FFFUL << FMC_SDCMR_MRD_Pos)             /*!< 0x003FFE00 */
+#define FMC_SDCMR_MRD               FMC_SDCMR_MRD_Msk                          /*!<MRD[12:0] bits (Mode register definition) */
+
+/******************  Bit definition for FMC_SDRTR register  ******************/
+#define FMC_SDRTR_CRE_Pos           (0U)                                       
+#define FMC_SDRTR_CRE_Msk           (0x1UL << FMC_SDRTR_CRE_Pos)                /*!< 0x00000001 */
+#define FMC_SDRTR_CRE               FMC_SDRTR_CRE_Msk                          /*!<Clear refresh error flag */
+
+#define FMC_SDRTR_COUNT_Pos         (1U)                                       
+#define FMC_SDRTR_COUNT_Msk         (0x1FFFUL << FMC_SDRTR_COUNT_Pos)           /*!< 0x00003FFE */
+#define FMC_SDRTR_COUNT             FMC_SDRTR_COUNT_Msk                        /*!<COUNT[12:0] bits (Refresh timer count) */
+
+#define FMC_SDRTR_REIE_Pos          (14U)                                      
+#define FMC_SDRTR_REIE_Msk          (0x1UL << FMC_SDRTR_REIE_Pos)               /*!< 0x00004000 */
+#define FMC_SDRTR_REIE              FMC_SDRTR_REIE_Msk                         /*!<RES interrupt enable */
+
+/******************  Bit definition for FMC_SDSR register  ******************/
+#define FMC_SDSR_RE_Pos             (0U)                                       
+#define FMC_SDSR_RE_Msk             (0x1UL << FMC_SDSR_RE_Pos)                  /*!< 0x00000001 */
+#define FMC_SDSR_RE                 FMC_SDSR_RE_Msk                            /*!<Refresh error flag */
+
+#define FMC_SDSR_MODES1_Pos         (1U)                                       
+#define FMC_SDSR_MODES1_Msk         (0x3UL << FMC_SDSR_MODES1_Pos)              /*!< 0x00000006 */
+#define FMC_SDSR_MODES1             FMC_SDSR_MODES1_Msk                        /*!<MODES1[1:0]bits (Status mode for bank 1) */
+#define FMC_SDSR_MODES1_0           (0x1UL << FMC_SDSR_MODES1_Pos)              /*!< 0x00000002 */
+#define FMC_SDSR_MODES1_1           (0x2UL << FMC_SDSR_MODES1_Pos)              /*!< 0x00000004 */
+
+#define FMC_SDSR_MODES2_Pos         (3U)                                       
+#define FMC_SDSR_MODES2_Msk         (0x3UL << FMC_SDSR_MODES2_Pos)              /*!< 0x00000018 */
+#define FMC_SDSR_MODES2             FMC_SDSR_MODES2_Msk                        /*!<MODES2[1:0]bits (Status mode for bank 2) */
+#define FMC_SDSR_MODES2_0           (0x1UL << FMC_SDSR_MODES2_Pos)              /*!< 0x00000008 */
+#define FMC_SDSR_MODES2_1           (0x2UL << FMC_SDSR_MODES2_Pos)              /*!< 0x00000010 */
+#define FMC_SDSR_BUSY_Pos           (5U)                                       
+#define FMC_SDSR_BUSY_Msk           (0x1UL << FMC_SDSR_BUSY_Pos)                /*!< 0x00000020 */
+#define FMC_SDSR_BUSY               FMC_SDSR_BUSY_Msk                          /*!<Busy status */
+
+/******************************************************************************/
+/*                                                                            */
+/*                            General Purpose I/O                             */
+/*                                                                            */
+/******************************************************************************/
+/******************  Bits definition for GPIO_MODER register  *****************/
+#define GPIO_MODER_MODER0_Pos            (0U)                                  
+#define GPIO_MODER_MODER0_Msk            (0x3UL << GPIO_MODER_MODER0_Pos)       /*!< 0x00000003 */
+#define GPIO_MODER_MODER0                GPIO_MODER_MODER0_Msk                 
+#define GPIO_MODER_MODER0_0              (0x1UL << GPIO_MODER_MODER0_Pos)       /*!< 0x00000001 */
+#define GPIO_MODER_MODER0_1              (0x2UL << GPIO_MODER_MODER0_Pos)       /*!< 0x00000002 */
+#define GPIO_MODER_MODER1_Pos            (2U)                                  
+#define GPIO_MODER_MODER1_Msk            (0x3UL << GPIO_MODER_MODER1_Pos)       /*!< 0x0000000C */
+#define GPIO_MODER_MODER1                GPIO_MODER_MODER1_Msk                 
+#define GPIO_MODER_MODER1_0              (0x1UL << GPIO_MODER_MODER1_Pos)       /*!< 0x00000004 */
+#define GPIO_MODER_MODER1_1              (0x2UL << GPIO_MODER_MODER1_Pos)       /*!< 0x00000008 */
+#define GPIO_MODER_MODER2_Pos            (4U)                                  
+#define GPIO_MODER_MODER2_Msk            (0x3UL << GPIO_MODER_MODER2_Pos)       /*!< 0x00000030 */
+#define GPIO_MODER_MODER2                GPIO_MODER_MODER2_Msk                 
+#define GPIO_MODER_MODER2_0              (0x1UL << GPIO_MODER_MODER2_Pos)       /*!< 0x00000010 */
+#define GPIO_MODER_MODER2_1              (0x2UL << GPIO_MODER_MODER2_Pos)       /*!< 0x00000020 */
+#define GPIO_MODER_MODER3_Pos            (6U)                                  
+#define GPIO_MODER_MODER3_Msk            (0x3UL << GPIO_MODER_MODER3_Pos)       /*!< 0x000000C0 */
+#define GPIO_MODER_MODER3                GPIO_MODER_MODER3_Msk                 
+#define GPIO_MODER_MODER3_0              (0x1UL << GPIO_MODER_MODER3_Pos)       /*!< 0x00000040 */
+#define GPIO_MODER_MODER3_1              (0x2UL << GPIO_MODER_MODER3_Pos)       /*!< 0x00000080 */
+#define GPIO_MODER_MODER4_Pos            (8U)                                  
+#define GPIO_MODER_MODER4_Msk            (0x3UL << GPIO_MODER_MODER4_Pos)       /*!< 0x00000300 */
+#define GPIO_MODER_MODER4                GPIO_MODER_MODER4_Msk                 
+#define GPIO_MODER_MODER4_0              (0x1UL << GPIO_MODER_MODER4_Pos)       /*!< 0x00000100 */
+#define GPIO_MODER_MODER4_1              (0x2UL << GPIO_MODER_MODER4_Pos)       /*!< 0x00000200 */
+#define GPIO_MODER_MODER5_Pos            (10U)                                 
+#define GPIO_MODER_MODER5_Msk            (0x3UL << GPIO_MODER_MODER5_Pos)       /*!< 0x00000C00 */
+#define GPIO_MODER_MODER5                GPIO_MODER_MODER5_Msk                 
+#define GPIO_MODER_MODER5_0              (0x1UL << GPIO_MODER_MODER5_Pos)       /*!< 0x00000400 */
+#define GPIO_MODER_MODER5_1              (0x2UL << GPIO_MODER_MODER5_Pos)       /*!< 0x00000800 */
+#define GPIO_MODER_MODER6_Pos            (12U)                                 
+#define GPIO_MODER_MODER6_Msk            (0x3UL << GPIO_MODER_MODER6_Pos)       /*!< 0x00003000 */
+#define GPIO_MODER_MODER6                GPIO_MODER_MODER6_Msk                 
+#define GPIO_MODER_MODER6_0              (0x1UL << GPIO_MODER_MODER6_Pos)       /*!< 0x00001000 */
+#define GPIO_MODER_MODER6_1              (0x2UL << GPIO_MODER_MODER6_Pos)       /*!< 0x00002000 */
+#define GPIO_MODER_MODER7_Pos            (14U)                                 
+#define GPIO_MODER_MODER7_Msk            (0x3UL << GPIO_MODER_MODER7_Pos)       /*!< 0x0000C000 */
+#define GPIO_MODER_MODER7                GPIO_MODER_MODER7_Msk                 
+#define GPIO_MODER_MODER7_0              (0x1UL << GPIO_MODER_MODER7_Pos)       /*!< 0x00004000 */
+#define GPIO_MODER_MODER7_1              (0x2UL << GPIO_MODER_MODER7_Pos)       /*!< 0x00008000 */
+#define GPIO_MODER_MODER8_Pos            (16U)                                 
+#define GPIO_MODER_MODER8_Msk            (0x3UL << GPIO_MODER_MODER8_Pos)       /*!< 0x00030000 */
+#define GPIO_MODER_MODER8                GPIO_MODER_MODER8_Msk                 
+#define GPIO_MODER_MODER8_0              (0x1UL << GPIO_MODER_MODER8_Pos)       /*!< 0x00010000 */
+#define GPIO_MODER_MODER8_1              (0x2UL << GPIO_MODER_MODER8_Pos)       /*!< 0x00020000 */
+#define GPIO_MODER_MODER9_Pos            (18U)                                 
+#define GPIO_MODER_MODER9_Msk            (0x3UL << GPIO_MODER_MODER9_Pos)       /*!< 0x000C0000 */
+#define GPIO_MODER_MODER9                GPIO_MODER_MODER9_Msk                 
+#define GPIO_MODER_MODER9_0              (0x1UL << GPIO_MODER_MODER9_Pos)       /*!< 0x00040000 */
+#define GPIO_MODER_MODER9_1              (0x2UL << GPIO_MODER_MODER9_Pos)       /*!< 0x00080000 */
+#define GPIO_MODER_MODER10_Pos           (20U)                                 
+#define GPIO_MODER_MODER10_Msk           (0x3UL << GPIO_MODER_MODER10_Pos)      /*!< 0x00300000 */
+#define GPIO_MODER_MODER10               GPIO_MODER_MODER10_Msk                
+#define GPIO_MODER_MODER10_0             (0x1UL << GPIO_MODER_MODER10_Pos)      /*!< 0x00100000 */
+#define GPIO_MODER_MODER10_1             (0x2UL << GPIO_MODER_MODER10_Pos)      /*!< 0x00200000 */
+#define GPIO_MODER_MODER11_Pos           (22U)                                 
+#define GPIO_MODER_MODER11_Msk           (0x3UL << GPIO_MODER_MODER11_Pos)      /*!< 0x00C00000 */
+#define GPIO_MODER_MODER11               GPIO_MODER_MODER11_Msk                
+#define GPIO_MODER_MODER11_0             (0x1UL << GPIO_MODER_MODER11_Pos)      /*!< 0x00400000 */
+#define GPIO_MODER_MODER11_1             (0x2UL << GPIO_MODER_MODER11_Pos)      /*!< 0x00800000 */
+#define GPIO_MODER_MODER12_Pos           (24U)                                 
+#define GPIO_MODER_MODER12_Msk           (0x3UL << GPIO_MODER_MODER12_Pos)      /*!< 0x03000000 */
+#define GPIO_MODER_MODER12               GPIO_MODER_MODER12_Msk                
+#define GPIO_MODER_MODER12_0             (0x1UL << GPIO_MODER_MODER12_Pos)      /*!< 0x01000000 */
+#define GPIO_MODER_MODER12_1             (0x2UL << GPIO_MODER_MODER12_Pos)      /*!< 0x02000000 */
+#define GPIO_MODER_MODER13_Pos           (26U)                                 
+#define GPIO_MODER_MODER13_Msk           (0x3UL << GPIO_MODER_MODER13_Pos)      /*!< 0x0C000000 */
+#define GPIO_MODER_MODER13               GPIO_MODER_MODER13_Msk                
+#define GPIO_MODER_MODER13_0             (0x1UL << GPIO_MODER_MODER13_Pos)      /*!< 0x04000000 */
+#define GPIO_MODER_MODER13_1             (0x2UL << GPIO_MODER_MODER13_Pos)      /*!< 0x08000000 */
+#define GPIO_MODER_MODER14_Pos           (28U)                                 
+#define GPIO_MODER_MODER14_Msk           (0x3UL << GPIO_MODER_MODER14_Pos)      /*!< 0x30000000 */
+#define GPIO_MODER_MODER14               GPIO_MODER_MODER14_Msk                
+#define GPIO_MODER_MODER14_0             (0x1UL << GPIO_MODER_MODER14_Pos)      /*!< 0x10000000 */
+#define GPIO_MODER_MODER14_1             (0x2UL << GPIO_MODER_MODER14_Pos)      /*!< 0x20000000 */
+#define GPIO_MODER_MODER15_Pos           (30U)                                 
+#define GPIO_MODER_MODER15_Msk           (0x3UL << GPIO_MODER_MODER15_Pos)      /*!< 0xC0000000 */
+#define GPIO_MODER_MODER15               GPIO_MODER_MODER15_Msk                
+#define GPIO_MODER_MODER15_0             (0x1UL << GPIO_MODER_MODER15_Pos)      /*!< 0x40000000 */
+#define GPIO_MODER_MODER15_1             (0x2UL << GPIO_MODER_MODER15_Pos)      /*!< 0x80000000 */
+
+/* Legacy defines */
+#define GPIO_MODER_MODE0_Pos             GPIO_MODER_MODER0_Pos                                  
+#define GPIO_MODER_MODE0_Msk             GPIO_MODER_MODER0_Msk
+#define GPIO_MODER_MODE0                 GPIO_MODER_MODER0                 
+#define GPIO_MODER_MODE0_0               GPIO_MODER_MODER0_0
+#define GPIO_MODER_MODE0_1               GPIO_MODER_MODER0_1
+#define GPIO_MODER_MODE1_Pos             GPIO_MODER_MODER1_Pos                                  
+#define GPIO_MODER_MODE1_Msk             GPIO_MODER_MODER1_Msk
+#define GPIO_MODER_MODE1                 GPIO_MODER_MODER1                  
+#define GPIO_MODER_MODE1_0               GPIO_MODER_MODER1_0
+#define GPIO_MODER_MODE1_1               GPIO_MODER_MODER1_1
+#define GPIO_MODER_MODE2_Pos             GPIO_MODER_MODER2_Pos
+#define GPIO_MODER_MODE2_Msk             GPIO_MODER_MODER2_Msk
+#define GPIO_MODER_MODE2                 GPIO_MODER_MODER2                 
+#define GPIO_MODER_MODE2_0               GPIO_MODER_MODER2_0
+#define GPIO_MODER_MODE2_1               GPIO_MODER_MODER2_1
+#define GPIO_MODER_MODE3_Pos             GPIO_MODER_MODER3_Pos                                
+#define GPIO_MODER_MODE3_Msk             GPIO_MODER_MODER3_Msk
+#define GPIO_MODER_MODE3                 GPIO_MODER_MODER3
+#define GPIO_MODER_MODE3_0               GPIO_MODER_MODER3_0
+#define GPIO_MODER_MODE3_1               GPIO_MODER_MODER3_1
+#define GPIO_MODER_MODE4_Pos             GPIO_MODER_MODER4_Pos
+#define GPIO_MODER_MODE4_Msk             GPIO_MODER_MODER4_Msk
+#define GPIO_MODER_MODE4                 GPIO_MODER_MODER4
+#define GPIO_MODER_MODE4_0               GPIO_MODER_MODER4_0
+#define GPIO_MODER_MODE4_1               GPIO_MODER_MODER4_1
+#define GPIO_MODER_MODE5_Pos             GPIO_MODER_MODER5_Pos
+#define GPIO_MODER_MODE5_Msk             GPIO_MODER_MODER5_Msk
+#define GPIO_MODER_MODE5                 GPIO_MODER_MODER5
+#define GPIO_MODER_MODE5_0               GPIO_MODER_MODER5_0
+#define GPIO_MODER_MODE5_1               GPIO_MODER_MODER5_1
+#define GPIO_MODER_MODE6_Pos             GPIO_MODER_MODER6_Pos
+#define GPIO_MODER_MODE6_Msk             GPIO_MODER_MODER6_Msk
+#define GPIO_MODER_MODE6                 GPIO_MODER_MODER6
+#define GPIO_MODER_MODE6_0               GPIO_MODER_MODER6_0
+#define GPIO_MODER_MODE6_1               GPIO_MODER_MODER6_1
+#define GPIO_MODER_MODE7_Pos             GPIO_MODER_MODER7_Pos
+#define GPIO_MODER_MODE7_Msk             GPIO_MODER_MODER7_Msk
+#define GPIO_MODER_MODE7                 GPIO_MODER_MODER7
+#define GPIO_MODER_MODE7_0               GPIO_MODER_MODER7_0
+#define GPIO_MODER_MODE7_1               GPIO_MODER_MODER7_1
+#define GPIO_MODER_MODE8_Pos             GPIO_MODER_MODER8_Pos
+#define GPIO_MODER_MODE8_Msk             GPIO_MODER_MODER8_Msk
+#define GPIO_MODER_MODE8                 GPIO_MODER_MODER8
+#define GPIO_MODER_MODE8_0               GPIO_MODER_MODER8_0
+#define GPIO_MODER_MODE8_1               GPIO_MODER_MODER8_1
+#define GPIO_MODER_MODE9_Pos             GPIO_MODER_MODER9_Pos
+#define GPIO_MODER_MODE9_Msk             GPIO_MODER_MODER9_Msk
+#define GPIO_MODER_MODE9                 GPIO_MODER_MODER9
+#define GPIO_MODER_MODE9_0               GPIO_MODER_MODER9_0
+#define GPIO_MODER_MODE9_1               GPIO_MODER_MODER9_1
+#define GPIO_MODER_MODE10_Pos            GPIO_MODER_MODER10_Pos
+#define GPIO_MODER_MODE10_Msk            GPIO_MODER_MODER10_Msk
+#define GPIO_MODER_MODE10                GPIO_MODER_MODER10
+#define GPIO_MODER_MODE10_0              GPIO_MODER_MODER10_0
+#define GPIO_MODER_MODE10_1              GPIO_MODER_MODER10_1
+#define GPIO_MODER_MODE11_Pos            GPIO_MODER_MODER11_Pos
+#define GPIO_MODER_MODE11_Msk            GPIO_MODER_MODER11_Msk
+#define GPIO_MODER_MODE11                GPIO_MODER_MODER11
+#define GPIO_MODER_MODE11_0              GPIO_MODER_MODER11_0
+#define GPIO_MODER_MODE11_1              GPIO_MODER_MODER11_1
+#define GPIO_MODER_MODE12_Pos            GPIO_MODER_MODER12_Pos
+#define GPIO_MODER_MODE12_Msk            GPIO_MODER_MODER12_Msk
+#define GPIO_MODER_MODE12                GPIO_MODER_MODER12
+#define GPIO_MODER_MODE12_0              GPIO_MODER_MODER12_0
+#define GPIO_MODER_MODE12_1              GPIO_MODER_MODER12_1
+#define GPIO_MODER_MODE13_Pos            GPIO_MODER_MODER13_Pos
+#define GPIO_MODER_MODE13_Msk            GPIO_MODER_MODER13_Msk
+#define GPIO_MODER_MODE13                GPIO_MODER_MODER13
+#define GPIO_MODER_MODE13_0              GPIO_MODER_MODER13_0
+#define GPIO_MODER_MODE13_1              GPIO_MODER_MODER13_1
+#define GPIO_MODER_MODE14_Pos            GPIO_MODER_MODER14_Pos
+#define GPIO_MODER_MODE14_Msk            GPIO_MODER_MODER14_Msk
+#define GPIO_MODER_MODE14                GPIO_MODER_MODER14
+#define GPIO_MODER_MODE14_0              GPIO_MODER_MODER14_0
+#define GPIO_MODER_MODE14_1              GPIO_MODER_MODER14_1
+#define GPIO_MODER_MODE15_Pos            GPIO_MODER_MODER15_Pos
+#define GPIO_MODER_MODE15_Msk            GPIO_MODER_MODER15_Msk
+#define GPIO_MODER_MODE15                GPIO_MODER_MODER15
+#define GPIO_MODER_MODE15_0              GPIO_MODER_MODER15_0
+#define GPIO_MODER_MODE15_1              GPIO_MODER_MODER15_1
+
+/******************  Bits definition for GPIO_OTYPER register  ****************/
+#define GPIO_OTYPER_OT0_Pos              (0U)                                  
+#define GPIO_OTYPER_OT0_Msk              (0x1UL << GPIO_OTYPER_OT0_Pos)         /*!< 0x00000001 */
+#define GPIO_OTYPER_OT0                  GPIO_OTYPER_OT0_Msk                   
+#define GPIO_OTYPER_OT1_Pos              (1U)                                  
+#define GPIO_OTYPER_OT1_Msk              (0x1UL << GPIO_OTYPER_OT1_Pos)         /*!< 0x00000002 */
+#define GPIO_OTYPER_OT1                  GPIO_OTYPER_OT1_Msk                   
+#define GPIO_OTYPER_OT2_Pos              (2U)                                  
+#define GPIO_OTYPER_OT2_Msk              (0x1UL << GPIO_OTYPER_OT2_Pos)         /*!< 0x00000004 */
+#define GPIO_OTYPER_OT2                  GPIO_OTYPER_OT2_Msk                   
+#define GPIO_OTYPER_OT3_Pos              (3U)                                  
+#define GPIO_OTYPER_OT3_Msk              (0x1UL << GPIO_OTYPER_OT3_Pos)         /*!< 0x00000008 */
+#define GPIO_OTYPER_OT3                  GPIO_OTYPER_OT3_Msk                   
+#define GPIO_OTYPER_OT4_Pos              (4U)                                  
+#define GPIO_OTYPER_OT4_Msk              (0x1UL << GPIO_OTYPER_OT4_Pos)         /*!< 0x00000010 */
+#define GPIO_OTYPER_OT4                  GPIO_OTYPER_OT4_Msk                   
+#define GPIO_OTYPER_OT5_Pos              (5U)                                  
+#define GPIO_OTYPER_OT5_Msk              (0x1UL << GPIO_OTYPER_OT5_Pos)         /*!< 0x00000020 */
+#define GPIO_OTYPER_OT5                  GPIO_OTYPER_OT5_Msk                   
+#define GPIO_OTYPER_OT6_Pos              (6U)                                  
+#define GPIO_OTYPER_OT6_Msk              (0x1UL << GPIO_OTYPER_OT6_Pos)         /*!< 0x00000040 */
+#define GPIO_OTYPER_OT6                  GPIO_OTYPER_OT6_Msk                   
+#define GPIO_OTYPER_OT7_Pos              (7U)                                  
+#define GPIO_OTYPER_OT7_Msk              (0x1UL << GPIO_OTYPER_OT7_Pos)         /*!< 0x00000080 */
+#define GPIO_OTYPER_OT7                  GPIO_OTYPER_OT7_Msk                   
+#define GPIO_OTYPER_OT8_Pos              (8U)                                  
+#define GPIO_OTYPER_OT8_Msk              (0x1UL << GPIO_OTYPER_OT8_Pos)         /*!< 0x00000100 */
+#define GPIO_OTYPER_OT8                  GPIO_OTYPER_OT8_Msk                   
+#define GPIO_OTYPER_OT9_Pos              (9U)                                  
+#define GPIO_OTYPER_OT9_Msk              (0x1UL << GPIO_OTYPER_OT9_Pos)         /*!< 0x00000200 */
+#define GPIO_OTYPER_OT9                  GPIO_OTYPER_OT9_Msk                   
+#define GPIO_OTYPER_OT10_Pos             (10U)                                 
+#define GPIO_OTYPER_OT10_Msk             (0x1UL << GPIO_OTYPER_OT10_Pos)        /*!< 0x00000400 */
+#define GPIO_OTYPER_OT10                 GPIO_OTYPER_OT10_Msk                  
+#define GPIO_OTYPER_OT11_Pos             (11U)                                 
+#define GPIO_OTYPER_OT11_Msk             (0x1UL << GPIO_OTYPER_OT11_Pos)        /*!< 0x00000800 */
+#define GPIO_OTYPER_OT11                 GPIO_OTYPER_OT11_Msk                  
+#define GPIO_OTYPER_OT12_Pos             (12U)                                 
+#define GPIO_OTYPER_OT12_Msk             (0x1UL << GPIO_OTYPER_OT12_Pos)        /*!< 0x00001000 */
+#define GPIO_OTYPER_OT12                 GPIO_OTYPER_OT12_Msk                  
+#define GPIO_OTYPER_OT13_Pos             (13U)                                 
+#define GPIO_OTYPER_OT13_Msk             (0x1UL << GPIO_OTYPER_OT13_Pos)        /*!< 0x00002000 */
+#define GPIO_OTYPER_OT13                 GPIO_OTYPER_OT13_Msk                  
+#define GPIO_OTYPER_OT14_Pos             (14U)                                 
+#define GPIO_OTYPER_OT14_Msk             (0x1UL << GPIO_OTYPER_OT14_Pos)        /*!< 0x00004000 */
+#define GPIO_OTYPER_OT14                 GPIO_OTYPER_OT14_Msk                  
+#define GPIO_OTYPER_OT15_Pos             (15U)                                 
+#define GPIO_OTYPER_OT15_Msk             (0x1UL << GPIO_OTYPER_OT15_Pos)        /*!< 0x00008000 */
+#define GPIO_OTYPER_OT15                 GPIO_OTYPER_OT15_Msk                  
+
+/* Legacy defines */
+#define GPIO_OTYPER_OT_0                 GPIO_OTYPER_OT0
+#define GPIO_OTYPER_OT_1                 GPIO_OTYPER_OT1
+#define GPIO_OTYPER_OT_2                 GPIO_OTYPER_OT2
+#define GPIO_OTYPER_OT_3                 GPIO_OTYPER_OT3
+#define GPIO_OTYPER_OT_4                 GPIO_OTYPER_OT4
+#define GPIO_OTYPER_OT_5                 GPIO_OTYPER_OT5
+#define GPIO_OTYPER_OT_6                 GPIO_OTYPER_OT6
+#define GPIO_OTYPER_OT_7                 GPIO_OTYPER_OT7
+#define GPIO_OTYPER_OT_8                 GPIO_OTYPER_OT8
+#define GPIO_OTYPER_OT_9                 GPIO_OTYPER_OT9
+#define GPIO_OTYPER_OT_10                GPIO_OTYPER_OT10
+#define GPIO_OTYPER_OT_11                GPIO_OTYPER_OT11
+#define GPIO_OTYPER_OT_12                GPIO_OTYPER_OT12
+#define GPIO_OTYPER_OT_13                GPIO_OTYPER_OT13
+#define GPIO_OTYPER_OT_14                GPIO_OTYPER_OT14
+#define GPIO_OTYPER_OT_15                GPIO_OTYPER_OT15
+
+/******************  Bits definition for GPIO_OSPEEDR register  ***************/
+#define GPIO_OSPEEDR_OSPEED0_Pos         (0U)                                  
+#define GPIO_OSPEEDR_OSPEED0_Msk         (0x3UL << GPIO_OSPEEDR_OSPEED0_Pos)    /*!< 0x00000003 */
+#define GPIO_OSPEEDR_OSPEED0             GPIO_OSPEEDR_OSPEED0_Msk              
+#define GPIO_OSPEEDR_OSPEED0_0           (0x1UL << GPIO_OSPEEDR_OSPEED0_Pos)    /*!< 0x00000001 */
+#define GPIO_OSPEEDR_OSPEED0_1           (0x2UL << GPIO_OSPEEDR_OSPEED0_Pos)    /*!< 0x00000002 */
+#define GPIO_OSPEEDR_OSPEED1_Pos         (2U)                                  
+#define GPIO_OSPEEDR_OSPEED1_Msk         (0x3UL << GPIO_OSPEEDR_OSPEED1_Pos)    /*!< 0x0000000C */
+#define GPIO_OSPEEDR_OSPEED1             GPIO_OSPEEDR_OSPEED1_Msk              
+#define GPIO_OSPEEDR_OSPEED1_0           (0x1UL << GPIO_OSPEEDR_OSPEED1_Pos)    /*!< 0x00000004 */
+#define GPIO_OSPEEDR_OSPEED1_1           (0x2UL << GPIO_OSPEEDR_OSPEED1_Pos)    /*!< 0x00000008 */
+#define GPIO_OSPEEDR_OSPEED2_Pos         (4U)                                  
+#define GPIO_OSPEEDR_OSPEED2_Msk         (0x3UL << GPIO_OSPEEDR_OSPEED2_Pos)    /*!< 0x00000030 */
+#define GPIO_OSPEEDR_OSPEED2             GPIO_OSPEEDR_OSPEED2_Msk              
+#define GPIO_OSPEEDR_OSPEED2_0           (0x1UL << GPIO_OSPEEDR_OSPEED2_Pos)    /*!< 0x00000010 */
+#define GPIO_OSPEEDR_OSPEED2_1           (0x2UL << GPIO_OSPEEDR_OSPEED2_Pos)    /*!< 0x00000020 */
+#define GPIO_OSPEEDR_OSPEED3_Pos         (6U)                                  
+#define GPIO_OSPEEDR_OSPEED3_Msk         (0x3UL << GPIO_OSPEEDR_OSPEED3_Pos)    /*!< 0x000000C0 */
+#define GPIO_OSPEEDR_OSPEED3             GPIO_OSPEEDR_OSPEED3_Msk              
+#define GPIO_OSPEEDR_OSPEED3_0           (0x1UL << GPIO_OSPEEDR_OSPEED3_Pos)    /*!< 0x00000040 */
+#define GPIO_OSPEEDR_OSPEED3_1           (0x2UL << GPIO_OSPEEDR_OSPEED3_Pos)    /*!< 0x00000080 */
+#define GPIO_OSPEEDR_OSPEED4_Pos         (8U)                                  
+#define GPIO_OSPEEDR_OSPEED4_Msk         (0x3UL << GPIO_OSPEEDR_OSPEED4_Pos)    /*!< 0x00000300 */
+#define GPIO_OSPEEDR_OSPEED4             GPIO_OSPEEDR_OSPEED4_Msk              
+#define GPIO_OSPEEDR_OSPEED4_0           (0x1UL << GPIO_OSPEEDR_OSPEED4_Pos)    /*!< 0x00000100 */
+#define GPIO_OSPEEDR_OSPEED4_1           (0x2UL << GPIO_OSPEEDR_OSPEED4_Pos)    /*!< 0x00000200 */
+#define GPIO_OSPEEDR_OSPEED5_Pos         (10U)                                 
+#define GPIO_OSPEEDR_OSPEED5_Msk         (0x3UL << GPIO_OSPEEDR_OSPEED5_Pos)    /*!< 0x00000C00 */
+#define GPIO_OSPEEDR_OSPEED5             GPIO_OSPEEDR_OSPEED5_Msk              
+#define GPIO_OSPEEDR_OSPEED5_0           (0x1UL << GPIO_OSPEEDR_OSPEED5_Pos)    /*!< 0x00000400 */
+#define GPIO_OSPEEDR_OSPEED5_1           (0x2UL << GPIO_OSPEEDR_OSPEED5_Pos)    /*!< 0x00000800 */
+#define GPIO_OSPEEDR_OSPEED6_Pos         (12U)                                 
+#define GPIO_OSPEEDR_OSPEED6_Msk         (0x3UL << GPIO_OSPEEDR_OSPEED6_Pos)    /*!< 0x00003000 */
+#define GPIO_OSPEEDR_OSPEED6             GPIO_OSPEEDR_OSPEED6_Msk              
+#define GPIO_OSPEEDR_OSPEED6_0           (0x1UL << GPIO_OSPEEDR_OSPEED6_Pos)    /*!< 0x00001000 */
+#define GPIO_OSPEEDR_OSPEED6_1           (0x2UL << GPIO_OSPEEDR_OSPEED6_Pos)    /*!< 0x00002000 */
+#define GPIO_OSPEEDR_OSPEED7_Pos         (14U)                                 
+#define GPIO_OSPEEDR_OSPEED7_Msk         (0x3UL << GPIO_OSPEEDR_OSPEED7_Pos)    /*!< 0x0000C000 */
+#define GPIO_OSPEEDR_OSPEED7             GPIO_OSPEEDR_OSPEED7_Msk              
+#define GPIO_OSPEEDR_OSPEED7_0           (0x1UL << GPIO_OSPEEDR_OSPEED7_Pos)    /*!< 0x00004000 */
+#define GPIO_OSPEEDR_OSPEED7_1           (0x2UL << GPIO_OSPEEDR_OSPEED7_Pos)    /*!< 0x00008000 */
+#define GPIO_OSPEEDR_OSPEED8_Pos         (16U)                                 
+#define GPIO_OSPEEDR_OSPEED8_Msk         (0x3UL << GPIO_OSPEEDR_OSPEED8_Pos)    /*!< 0x00030000 */
+#define GPIO_OSPEEDR_OSPEED8             GPIO_OSPEEDR_OSPEED8_Msk              
+#define GPIO_OSPEEDR_OSPEED8_0           (0x1UL << GPIO_OSPEEDR_OSPEED8_Pos)    /*!< 0x00010000 */
+#define GPIO_OSPEEDR_OSPEED8_1           (0x2UL << GPIO_OSPEEDR_OSPEED8_Pos)    /*!< 0x00020000 */
+#define GPIO_OSPEEDR_OSPEED9_Pos         (18U)                                 
+#define GPIO_OSPEEDR_OSPEED9_Msk         (0x3UL << GPIO_OSPEEDR_OSPEED9_Pos)    /*!< 0x000C0000 */
+#define GPIO_OSPEEDR_OSPEED9             GPIO_OSPEEDR_OSPEED9_Msk              
+#define GPIO_OSPEEDR_OSPEED9_0           (0x1UL << GPIO_OSPEEDR_OSPEED9_Pos)    /*!< 0x00040000 */
+#define GPIO_OSPEEDR_OSPEED9_1           (0x2UL << GPIO_OSPEEDR_OSPEED9_Pos)    /*!< 0x00080000 */
+#define GPIO_OSPEEDR_OSPEED10_Pos        (20U)                                 
+#define GPIO_OSPEEDR_OSPEED10_Msk        (0x3UL << GPIO_OSPEEDR_OSPEED10_Pos)   /*!< 0x00300000 */
+#define GPIO_OSPEEDR_OSPEED10            GPIO_OSPEEDR_OSPEED10_Msk             
+#define GPIO_OSPEEDR_OSPEED10_0          (0x1UL << GPIO_OSPEEDR_OSPEED10_Pos)   /*!< 0x00100000 */
+#define GPIO_OSPEEDR_OSPEED10_1          (0x2UL << GPIO_OSPEEDR_OSPEED10_Pos)   /*!< 0x00200000 */
+#define GPIO_OSPEEDR_OSPEED11_Pos        (22U)                                 
+#define GPIO_OSPEEDR_OSPEED11_Msk        (0x3UL << GPIO_OSPEEDR_OSPEED11_Pos)   /*!< 0x00C00000 */
+#define GPIO_OSPEEDR_OSPEED11            GPIO_OSPEEDR_OSPEED11_Msk             
+#define GPIO_OSPEEDR_OSPEED11_0          (0x1UL << GPIO_OSPEEDR_OSPEED11_Pos)   /*!< 0x00400000 */
+#define GPIO_OSPEEDR_OSPEED11_1          (0x2UL << GPIO_OSPEEDR_OSPEED11_Pos)   /*!< 0x00800000 */
+#define GPIO_OSPEEDR_OSPEED12_Pos        (24U)                                 
+#define GPIO_OSPEEDR_OSPEED12_Msk        (0x3UL << GPIO_OSPEEDR_OSPEED12_Pos)   /*!< 0x03000000 */
+#define GPIO_OSPEEDR_OSPEED12            GPIO_OSPEEDR_OSPEED12_Msk             
+#define GPIO_OSPEEDR_OSPEED12_0          (0x1UL << GPIO_OSPEEDR_OSPEED12_Pos)   /*!< 0x01000000 */
+#define GPIO_OSPEEDR_OSPEED12_1          (0x2UL << GPIO_OSPEEDR_OSPEED12_Pos)   /*!< 0x02000000 */
+#define GPIO_OSPEEDR_OSPEED13_Pos        (26U)                                 
+#define GPIO_OSPEEDR_OSPEED13_Msk        (0x3UL << GPIO_OSPEEDR_OSPEED13_Pos)   /*!< 0x0C000000 */
+#define GPIO_OSPEEDR_OSPEED13            GPIO_OSPEEDR_OSPEED13_Msk             
+#define GPIO_OSPEEDR_OSPEED13_0          (0x1UL << GPIO_OSPEEDR_OSPEED13_Pos)   /*!< 0x04000000 */
+#define GPIO_OSPEEDR_OSPEED13_1          (0x2UL << GPIO_OSPEEDR_OSPEED13_Pos)   /*!< 0x08000000 */
+#define GPIO_OSPEEDR_OSPEED14_Pos        (28U)                                 
+#define GPIO_OSPEEDR_OSPEED14_Msk        (0x3UL << GPIO_OSPEEDR_OSPEED14_Pos)   /*!< 0x30000000 */
+#define GPIO_OSPEEDR_OSPEED14            GPIO_OSPEEDR_OSPEED14_Msk             
+#define GPIO_OSPEEDR_OSPEED14_0          (0x1UL << GPIO_OSPEEDR_OSPEED14_Pos)   /*!< 0x10000000 */
+#define GPIO_OSPEEDR_OSPEED14_1          (0x2UL << GPIO_OSPEEDR_OSPEED14_Pos)   /*!< 0x20000000 */
+#define GPIO_OSPEEDR_OSPEED15_Pos        (30U)                                 
+#define GPIO_OSPEEDR_OSPEED15_Msk        (0x3UL << GPIO_OSPEEDR_OSPEED15_Pos)   /*!< 0xC0000000 */
+#define GPIO_OSPEEDR_OSPEED15            GPIO_OSPEEDR_OSPEED15_Msk             
+#define GPIO_OSPEEDR_OSPEED15_0          (0x1UL << GPIO_OSPEEDR_OSPEED15_Pos)   /*!< 0x40000000 */
+#define GPIO_OSPEEDR_OSPEED15_1          (0x2UL << GPIO_OSPEEDR_OSPEED15_Pos)   /*!< 0x80000000 */
+
+/* Legacy defines */
+#define GPIO_OSPEEDER_OSPEEDR0           GPIO_OSPEEDR_OSPEED0
+#define GPIO_OSPEEDER_OSPEEDR0_0         GPIO_OSPEEDR_OSPEED0_0
+#define GPIO_OSPEEDER_OSPEEDR0_1         GPIO_OSPEEDR_OSPEED0_1
+#define GPIO_OSPEEDER_OSPEEDR1           GPIO_OSPEEDR_OSPEED1
+#define GPIO_OSPEEDER_OSPEEDR1_0         GPIO_OSPEEDR_OSPEED1_0
+#define GPIO_OSPEEDER_OSPEEDR1_1         GPIO_OSPEEDR_OSPEED1_1
+#define GPIO_OSPEEDER_OSPEEDR2           GPIO_OSPEEDR_OSPEED2
+#define GPIO_OSPEEDER_OSPEEDR2_0         GPIO_OSPEEDR_OSPEED2_0
+#define GPIO_OSPEEDER_OSPEEDR2_1         GPIO_OSPEEDR_OSPEED2_1
+#define GPIO_OSPEEDER_OSPEEDR3           GPIO_OSPEEDR_OSPEED3
+#define GPIO_OSPEEDER_OSPEEDR3_0         GPIO_OSPEEDR_OSPEED3_0
+#define GPIO_OSPEEDER_OSPEEDR3_1         GPIO_OSPEEDR_OSPEED3_1
+#define GPIO_OSPEEDER_OSPEEDR4           GPIO_OSPEEDR_OSPEED4
+#define GPIO_OSPEEDER_OSPEEDR4_0         GPIO_OSPEEDR_OSPEED4_0
+#define GPIO_OSPEEDER_OSPEEDR4_1         GPIO_OSPEEDR_OSPEED4_1
+#define GPIO_OSPEEDER_OSPEEDR5           GPIO_OSPEEDR_OSPEED5
+#define GPIO_OSPEEDER_OSPEEDR5_0         GPIO_OSPEEDR_OSPEED5_0
+#define GPIO_OSPEEDER_OSPEEDR5_1         GPIO_OSPEEDR_OSPEED5_1
+#define GPIO_OSPEEDER_OSPEEDR6           GPIO_OSPEEDR_OSPEED6
+#define GPIO_OSPEEDER_OSPEEDR6_0         GPIO_OSPEEDR_OSPEED6_0
+#define GPIO_OSPEEDER_OSPEEDR6_1         GPIO_OSPEEDR_OSPEED6_1
+#define GPIO_OSPEEDER_OSPEEDR7           GPIO_OSPEEDR_OSPEED7
+#define GPIO_OSPEEDER_OSPEEDR7_0         GPIO_OSPEEDR_OSPEED7_0
+#define GPIO_OSPEEDER_OSPEEDR7_1         GPIO_OSPEEDR_OSPEED7_1
+#define GPIO_OSPEEDER_OSPEEDR8           GPIO_OSPEEDR_OSPEED8
+#define GPIO_OSPEEDER_OSPEEDR8_0         GPIO_OSPEEDR_OSPEED8_0
+#define GPIO_OSPEEDER_OSPEEDR8_1         GPIO_OSPEEDR_OSPEED8_1
+#define GPIO_OSPEEDER_OSPEEDR9           GPIO_OSPEEDR_OSPEED9
+#define GPIO_OSPEEDER_OSPEEDR9_0         GPIO_OSPEEDR_OSPEED9_0
+#define GPIO_OSPEEDER_OSPEEDR9_1         GPIO_OSPEEDR_OSPEED9_1
+#define GPIO_OSPEEDER_OSPEEDR10          GPIO_OSPEEDR_OSPEED10
+#define GPIO_OSPEEDER_OSPEEDR10_0        GPIO_OSPEEDR_OSPEED10_0
+#define GPIO_OSPEEDER_OSPEEDR10_1        GPIO_OSPEEDR_OSPEED10_1
+#define GPIO_OSPEEDER_OSPEEDR11          GPIO_OSPEEDR_OSPEED11
+#define GPIO_OSPEEDER_OSPEEDR11_0        GPIO_OSPEEDR_OSPEED11_0
+#define GPIO_OSPEEDER_OSPEEDR11_1        GPIO_OSPEEDR_OSPEED11_1
+#define GPIO_OSPEEDER_OSPEEDR12          GPIO_OSPEEDR_OSPEED12
+#define GPIO_OSPEEDER_OSPEEDR12_0        GPIO_OSPEEDR_OSPEED12_0
+#define GPIO_OSPEEDER_OSPEEDR12_1        GPIO_OSPEEDR_OSPEED12_1
+#define GPIO_OSPEEDER_OSPEEDR13          GPIO_OSPEEDR_OSPEED13
+#define GPIO_OSPEEDER_OSPEEDR13_0        GPIO_OSPEEDR_OSPEED13_0
+#define GPIO_OSPEEDER_OSPEEDR13_1        GPIO_OSPEEDR_OSPEED13_1
+#define GPIO_OSPEEDER_OSPEEDR14          GPIO_OSPEEDR_OSPEED14
+#define GPIO_OSPEEDER_OSPEEDR14_0        GPIO_OSPEEDR_OSPEED14_0
+#define GPIO_OSPEEDER_OSPEEDR14_1        GPIO_OSPEEDR_OSPEED14_1
+#define GPIO_OSPEEDER_OSPEEDR15          GPIO_OSPEEDR_OSPEED15
+#define GPIO_OSPEEDER_OSPEEDR15_0        GPIO_OSPEEDR_OSPEED15_0
+#define GPIO_OSPEEDER_OSPEEDR15_1        GPIO_OSPEEDR_OSPEED15_1
+
+/******************  Bits definition for GPIO_PUPDR register  *****************/
+#define GPIO_PUPDR_PUPD0_Pos             (0U)                                  
+#define GPIO_PUPDR_PUPD0_Msk             (0x3UL << GPIO_PUPDR_PUPD0_Pos)        /*!< 0x00000003 */
+#define GPIO_PUPDR_PUPD0                 GPIO_PUPDR_PUPD0_Msk                  
+#define GPIO_PUPDR_PUPD0_0               (0x1UL << GPIO_PUPDR_PUPD0_Pos)        /*!< 0x00000001 */
+#define GPIO_PUPDR_PUPD0_1               (0x2UL << GPIO_PUPDR_PUPD0_Pos)        /*!< 0x00000002 */
+#define GPIO_PUPDR_PUPD1_Pos             (2U)                                  
+#define GPIO_PUPDR_PUPD1_Msk             (0x3UL << GPIO_PUPDR_PUPD1_Pos)        /*!< 0x0000000C */
+#define GPIO_PUPDR_PUPD1                 GPIO_PUPDR_PUPD1_Msk                  
+#define GPIO_PUPDR_PUPD1_0               (0x1UL << GPIO_PUPDR_PUPD1_Pos)        /*!< 0x00000004 */
+#define GPIO_PUPDR_PUPD1_1               (0x2UL << GPIO_PUPDR_PUPD1_Pos)        /*!< 0x00000008 */
+#define GPIO_PUPDR_PUPD2_Pos             (4U)                                  
+#define GPIO_PUPDR_PUPD2_Msk             (0x3UL << GPIO_PUPDR_PUPD2_Pos)        /*!< 0x00000030 */
+#define GPIO_PUPDR_PUPD2                 GPIO_PUPDR_PUPD2_Msk                  
+#define GPIO_PUPDR_PUPD2_0               (0x1UL << GPIO_PUPDR_PUPD2_Pos)        /*!< 0x00000010 */
+#define GPIO_PUPDR_PUPD2_1               (0x2UL << GPIO_PUPDR_PUPD2_Pos)        /*!< 0x00000020 */
+#define GPIO_PUPDR_PUPD3_Pos             (6U)                                  
+#define GPIO_PUPDR_PUPD3_Msk             (0x3UL << GPIO_PUPDR_PUPD3_Pos)        /*!< 0x000000C0 */
+#define GPIO_PUPDR_PUPD3                 GPIO_PUPDR_PUPD3_Msk                  
+#define GPIO_PUPDR_PUPD3_0               (0x1UL << GPIO_PUPDR_PUPD3_Pos)        /*!< 0x00000040 */
+#define GPIO_PUPDR_PUPD3_1               (0x2UL << GPIO_PUPDR_PUPD3_Pos)        /*!< 0x00000080 */
+#define GPIO_PUPDR_PUPD4_Pos             (8U)                                  
+#define GPIO_PUPDR_PUPD4_Msk             (0x3UL << GPIO_PUPDR_PUPD4_Pos)        /*!< 0x00000300 */
+#define GPIO_PUPDR_PUPD4                 GPIO_PUPDR_PUPD4_Msk                  
+#define GPIO_PUPDR_PUPD4_0               (0x1UL << GPIO_PUPDR_PUPD4_Pos)        /*!< 0x00000100 */
+#define GPIO_PUPDR_PUPD4_1               (0x2UL << GPIO_PUPDR_PUPD4_Pos)        /*!< 0x00000200 */
+#define GPIO_PUPDR_PUPD5_Pos             (10U)                                 
+#define GPIO_PUPDR_PUPD5_Msk             (0x3UL << GPIO_PUPDR_PUPD5_Pos)        /*!< 0x00000C00 */
+#define GPIO_PUPDR_PUPD5                 GPIO_PUPDR_PUPD5_Msk                  
+#define GPIO_PUPDR_PUPD5_0               (0x1UL << GPIO_PUPDR_PUPD5_Pos)        /*!< 0x00000400 */
+#define GPIO_PUPDR_PUPD5_1               (0x2UL << GPIO_PUPDR_PUPD5_Pos)        /*!< 0x00000800 */
+#define GPIO_PUPDR_PUPD6_Pos             (12U)                                 
+#define GPIO_PUPDR_PUPD6_Msk             (0x3UL << GPIO_PUPDR_PUPD6_Pos)        /*!< 0x00003000 */
+#define GPIO_PUPDR_PUPD6                 GPIO_PUPDR_PUPD6_Msk                  
+#define GPIO_PUPDR_PUPD6_0               (0x1UL << GPIO_PUPDR_PUPD6_Pos)        /*!< 0x00001000 */
+#define GPIO_PUPDR_PUPD6_1               (0x2UL << GPIO_PUPDR_PUPD6_Pos)        /*!< 0x00002000 */
+#define GPIO_PUPDR_PUPD7_Pos             (14U)                                 
+#define GPIO_PUPDR_PUPD7_Msk             (0x3UL << GPIO_PUPDR_PUPD7_Pos)        /*!< 0x0000C000 */
+#define GPIO_PUPDR_PUPD7                 GPIO_PUPDR_PUPD7_Msk                  
+#define GPIO_PUPDR_PUPD7_0               (0x1UL << GPIO_PUPDR_PUPD7_Pos)        /*!< 0x00004000 */
+#define GPIO_PUPDR_PUPD7_1               (0x2UL << GPIO_PUPDR_PUPD7_Pos)        /*!< 0x00008000 */
+#define GPIO_PUPDR_PUPD8_Pos             (16U)                                 
+#define GPIO_PUPDR_PUPD8_Msk             (0x3UL << GPIO_PUPDR_PUPD8_Pos)        /*!< 0x00030000 */
+#define GPIO_PUPDR_PUPD8                 GPIO_PUPDR_PUPD8_Msk                  
+#define GPIO_PUPDR_PUPD8_0               (0x1UL << GPIO_PUPDR_PUPD8_Pos)        /*!< 0x00010000 */
+#define GPIO_PUPDR_PUPD8_1               (0x2UL << GPIO_PUPDR_PUPD8_Pos)        /*!< 0x00020000 */
+#define GPIO_PUPDR_PUPD9_Pos             (18U)                                 
+#define GPIO_PUPDR_PUPD9_Msk             (0x3UL << GPIO_PUPDR_PUPD9_Pos)        /*!< 0x000C0000 */
+#define GPIO_PUPDR_PUPD9                 GPIO_PUPDR_PUPD9_Msk                  
+#define GPIO_PUPDR_PUPD9_0               (0x1UL << GPIO_PUPDR_PUPD9_Pos)        /*!< 0x00040000 */
+#define GPIO_PUPDR_PUPD9_1               (0x2UL << GPIO_PUPDR_PUPD9_Pos)        /*!< 0x00080000 */
+#define GPIO_PUPDR_PUPD10_Pos            (20U)                                 
+#define GPIO_PUPDR_PUPD10_Msk            (0x3UL << GPIO_PUPDR_PUPD10_Pos)       /*!< 0x00300000 */
+#define GPIO_PUPDR_PUPD10                GPIO_PUPDR_PUPD10_Msk                 
+#define GPIO_PUPDR_PUPD10_0              (0x1UL << GPIO_PUPDR_PUPD10_Pos)       /*!< 0x00100000 */
+#define GPIO_PUPDR_PUPD10_1              (0x2UL << GPIO_PUPDR_PUPD10_Pos)       /*!< 0x00200000 */
+#define GPIO_PUPDR_PUPD11_Pos            (22U)                                 
+#define GPIO_PUPDR_PUPD11_Msk            (0x3UL << GPIO_PUPDR_PUPD11_Pos)       /*!< 0x00C00000 */
+#define GPIO_PUPDR_PUPD11                GPIO_PUPDR_PUPD11_Msk                 
+#define GPIO_PUPDR_PUPD11_0              (0x1UL << GPIO_PUPDR_PUPD11_Pos)       /*!< 0x00400000 */
+#define GPIO_PUPDR_PUPD11_1              (0x2UL << GPIO_PUPDR_PUPD11_Pos)       /*!< 0x00800000 */
+#define GPIO_PUPDR_PUPD12_Pos            (24U)                                 
+#define GPIO_PUPDR_PUPD12_Msk            (0x3UL << GPIO_PUPDR_PUPD12_Pos)       /*!< 0x03000000 */
+#define GPIO_PUPDR_PUPD12                GPIO_PUPDR_PUPD12_Msk                 
+#define GPIO_PUPDR_PUPD12_0              (0x1UL << GPIO_PUPDR_PUPD12_Pos)       /*!< 0x01000000 */
+#define GPIO_PUPDR_PUPD12_1              (0x2UL << GPIO_PUPDR_PUPD12_Pos)       /*!< 0x02000000 */
+#define GPIO_PUPDR_PUPD13_Pos            (26U)                                 
+#define GPIO_PUPDR_PUPD13_Msk            (0x3UL << GPIO_PUPDR_PUPD13_Pos)       /*!< 0x0C000000 */
+#define GPIO_PUPDR_PUPD13                GPIO_PUPDR_PUPD13_Msk                 
+#define GPIO_PUPDR_PUPD13_0              (0x1UL << GPIO_PUPDR_PUPD13_Pos)       /*!< 0x04000000 */
+#define GPIO_PUPDR_PUPD13_1              (0x2UL << GPIO_PUPDR_PUPD13_Pos)       /*!< 0x08000000 */
+#define GPIO_PUPDR_PUPD14_Pos            (28U)                                 
+#define GPIO_PUPDR_PUPD14_Msk            (0x3UL << GPIO_PUPDR_PUPD14_Pos)       /*!< 0x30000000 */
+#define GPIO_PUPDR_PUPD14                GPIO_PUPDR_PUPD14_Msk                 
+#define GPIO_PUPDR_PUPD14_0              (0x1UL << GPIO_PUPDR_PUPD14_Pos)       /*!< 0x10000000 */
+#define GPIO_PUPDR_PUPD14_1              (0x2UL << GPIO_PUPDR_PUPD14_Pos)       /*!< 0x20000000 */
+#define GPIO_PUPDR_PUPD15_Pos            (30U)                                 
+#define GPIO_PUPDR_PUPD15_Msk            (0x3UL << GPIO_PUPDR_PUPD15_Pos)       /*!< 0xC0000000 */
+#define GPIO_PUPDR_PUPD15                GPIO_PUPDR_PUPD15_Msk                 
+#define GPIO_PUPDR_PUPD15_0              (0x1UL << GPIO_PUPDR_PUPD15_Pos)       /*!< 0x40000000 */
+#define GPIO_PUPDR_PUPD15_1              (0x2UL << GPIO_PUPDR_PUPD15_Pos)       /*!< 0x80000000 */
+
+/* Legacy defines */
+#define GPIO_PUPDR_PUPDR0                GPIO_PUPDR_PUPD0
+#define GPIO_PUPDR_PUPDR0_0              GPIO_PUPDR_PUPD0_0
+#define GPIO_PUPDR_PUPDR0_1              GPIO_PUPDR_PUPD0_1
+#define GPIO_PUPDR_PUPDR1                GPIO_PUPDR_PUPD1
+#define GPIO_PUPDR_PUPDR1_0              GPIO_PUPDR_PUPD1_0
+#define GPIO_PUPDR_PUPDR1_1              GPIO_PUPDR_PUPD1_1
+#define GPIO_PUPDR_PUPDR2                GPIO_PUPDR_PUPD2
+#define GPIO_PUPDR_PUPDR2_0              GPIO_PUPDR_PUPD2_0
+#define GPIO_PUPDR_PUPDR2_1              GPIO_PUPDR_PUPD2_1
+#define GPIO_PUPDR_PUPDR3                GPIO_PUPDR_PUPD3
+#define GPIO_PUPDR_PUPDR3_0              GPIO_PUPDR_PUPD3_0
+#define GPIO_PUPDR_PUPDR3_1              GPIO_PUPDR_PUPD3_1
+#define GPIO_PUPDR_PUPDR4                GPIO_PUPDR_PUPD4
+#define GPIO_PUPDR_PUPDR4_0              GPIO_PUPDR_PUPD4_0
+#define GPIO_PUPDR_PUPDR4_1              GPIO_PUPDR_PUPD4_1
+#define GPIO_PUPDR_PUPDR5                GPIO_PUPDR_PUPD5
+#define GPIO_PUPDR_PUPDR5_0              GPIO_PUPDR_PUPD5_0
+#define GPIO_PUPDR_PUPDR5_1              GPIO_PUPDR_PUPD5_1
+#define GPIO_PUPDR_PUPDR6                GPIO_PUPDR_PUPD6
+#define GPIO_PUPDR_PUPDR6_0              GPIO_PUPDR_PUPD6_0
+#define GPIO_PUPDR_PUPDR6_1              GPIO_PUPDR_PUPD6_1
+#define GPIO_PUPDR_PUPDR7                GPIO_PUPDR_PUPD7
+#define GPIO_PUPDR_PUPDR7_0              GPIO_PUPDR_PUPD7_0
+#define GPIO_PUPDR_PUPDR7_1              GPIO_PUPDR_PUPD7_1
+#define GPIO_PUPDR_PUPDR8                GPIO_PUPDR_PUPD8
+#define GPIO_PUPDR_PUPDR8_0              GPIO_PUPDR_PUPD8_0
+#define GPIO_PUPDR_PUPDR8_1              GPIO_PUPDR_PUPD8_1
+#define GPIO_PUPDR_PUPDR9                GPIO_PUPDR_PUPD9
+#define GPIO_PUPDR_PUPDR9_0              GPIO_PUPDR_PUPD9_0
+#define GPIO_PUPDR_PUPDR9_1              GPIO_PUPDR_PUPD9_1
+#define GPIO_PUPDR_PUPDR10               GPIO_PUPDR_PUPD10
+#define GPIO_PUPDR_PUPDR10_0             GPIO_PUPDR_PUPD10_0
+#define GPIO_PUPDR_PUPDR10_1             GPIO_PUPDR_PUPD10_1
+#define GPIO_PUPDR_PUPDR11               GPIO_PUPDR_PUPD11
+#define GPIO_PUPDR_PUPDR11_0             GPIO_PUPDR_PUPD11_0
+#define GPIO_PUPDR_PUPDR11_1             GPIO_PUPDR_PUPD11_1
+#define GPIO_PUPDR_PUPDR12               GPIO_PUPDR_PUPD12
+#define GPIO_PUPDR_PUPDR12_0             GPIO_PUPDR_PUPD12_0
+#define GPIO_PUPDR_PUPDR12_1             GPIO_PUPDR_PUPD12_1
+#define GPIO_PUPDR_PUPDR13               GPIO_PUPDR_PUPD13
+#define GPIO_PUPDR_PUPDR13_0             GPIO_PUPDR_PUPD13_0
+#define GPIO_PUPDR_PUPDR13_1             GPIO_PUPDR_PUPD13_1
+#define GPIO_PUPDR_PUPDR14               GPIO_PUPDR_PUPD14
+#define GPIO_PUPDR_PUPDR14_0             GPIO_PUPDR_PUPD14_0
+#define GPIO_PUPDR_PUPDR14_1             GPIO_PUPDR_PUPD14_1
+#define GPIO_PUPDR_PUPDR15               GPIO_PUPDR_PUPD15
+#define GPIO_PUPDR_PUPDR15_0             GPIO_PUPDR_PUPD15_0
+#define GPIO_PUPDR_PUPDR15_1             GPIO_PUPDR_PUPD15_1
+
+/******************  Bits definition for GPIO_IDR register  *******************/
+#define GPIO_IDR_ID0_Pos                 (0U)                                  
+#define GPIO_IDR_ID0_Msk                 (0x1UL << GPIO_IDR_ID0_Pos)            /*!< 0x00000001 */
+#define GPIO_IDR_ID0                     GPIO_IDR_ID0_Msk                      
+#define GPIO_IDR_ID1_Pos                 (1U)                                  
+#define GPIO_IDR_ID1_Msk                 (0x1UL << GPIO_IDR_ID1_Pos)            /*!< 0x00000002 */
+#define GPIO_IDR_ID1                     GPIO_IDR_ID1_Msk                      
+#define GPIO_IDR_ID2_Pos                 (2U)                                  
+#define GPIO_IDR_ID2_Msk                 (0x1UL << GPIO_IDR_ID2_Pos)            /*!< 0x00000004 */
+#define GPIO_IDR_ID2                     GPIO_IDR_ID2_Msk                      
+#define GPIO_IDR_ID3_Pos                 (3U)                                  
+#define GPIO_IDR_ID3_Msk                 (0x1UL << GPIO_IDR_ID3_Pos)            /*!< 0x00000008 */
+#define GPIO_IDR_ID3                     GPIO_IDR_ID3_Msk                      
+#define GPIO_IDR_ID4_Pos                 (4U)                                  
+#define GPIO_IDR_ID4_Msk                 (0x1UL << GPIO_IDR_ID4_Pos)            /*!< 0x00000010 */
+#define GPIO_IDR_ID4                     GPIO_IDR_ID4_Msk                      
+#define GPIO_IDR_ID5_Pos                 (5U)                                  
+#define GPIO_IDR_ID5_Msk                 (0x1UL << GPIO_IDR_ID5_Pos)            /*!< 0x00000020 */
+#define GPIO_IDR_ID5                     GPIO_IDR_ID5_Msk                      
+#define GPIO_IDR_ID6_Pos                 (6U)                                  
+#define GPIO_IDR_ID6_Msk                 (0x1UL << GPIO_IDR_ID6_Pos)            /*!< 0x00000040 */
+#define GPIO_IDR_ID6                     GPIO_IDR_ID6_Msk                      
+#define GPIO_IDR_ID7_Pos                 (7U)                                  
+#define GPIO_IDR_ID7_Msk                 (0x1UL << GPIO_IDR_ID7_Pos)            /*!< 0x00000080 */
+#define GPIO_IDR_ID7                     GPIO_IDR_ID7_Msk                      
+#define GPIO_IDR_ID8_Pos                 (8U)                                  
+#define GPIO_IDR_ID8_Msk                 (0x1UL << GPIO_IDR_ID8_Pos)            /*!< 0x00000100 */
+#define GPIO_IDR_ID8                     GPIO_IDR_ID8_Msk                      
+#define GPIO_IDR_ID9_Pos                 (9U)                                  
+#define GPIO_IDR_ID9_Msk                 (0x1UL << GPIO_IDR_ID9_Pos)            /*!< 0x00000200 */
+#define GPIO_IDR_ID9                     GPIO_IDR_ID9_Msk                      
+#define GPIO_IDR_ID10_Pos                (10U)                                 
+#define GPIO_IDR_ID10_Msk                (0x1UL << GPIO_IDR_ID10_Pos)           /*!< 0x00000400 */
+#define GPIO_IDR_ID10                    GPIO_IDR_ID10_Msk                     
+#define GPIO_IDR_ID11_Pos                (11U)                                 
+#define GPIO_IDR_ID11_Msk                (0x1UL << GPIO_IDR_ID11_Pos)           /*!< 0x00000800 */
+#define GPIO_IDR_ID11                    GPIO_IDR_ID11_Msk                     
+#define GPIO_IDR_ID12_Pos                (12U)                                 
+#define GPIO_IDR_ID12_Msk                (0x1UL << GPIO_IDR_ID12_Pos)           /*!< 0x00001000 */
+#define GPIO_IDR_ID12                    GPIO_IDR_ID12_Msk                     
+#define GPIO_IDR_ID13_Pos                (13U)                                 
+#define GPIO_IDR_ID13_Msk                (0x1UL << GPIO_IDR_ID13_Pos)           /*!< 0x00002000 */
+#define GPIO_IDR_ID13                    GPIO_IDR_ID13_Msk                     
+#define GPIO_IDR_ID14_Pos                (14U)                                 
+#define GPIO_IDR_ID14_Msk                (0x1UL << GPIO_IDR_ID14_Pos)           /*!< 0x00004000 */
+#define GPIO_IDR_ID14                    GPIO_IDR_ID14_Msk                     
+#define GPIO_IDR_ID15_Pos                (15U)                                 
+#define GPIO_IDR_ID15_Msk                (0x1UL << GPIO_IDR_ID15_Pos)           /*!< 0x00008000 */
+#define GPIO_IDR_ID15                    GPIO_IDR_ID15_Msk                     
+
+/* Legacy defines */
+#define GPIO_IDR_IDR_0                   GPIO_IDR_ID0
+#define GPIO_IDR_IDR_1                   GPIO_IDR_ID1
+#define GPIO_IDR_IDR_2                   GPIO_IDR_ID2
+#define GPIO_IDR_IDR_3                   GPIO_IDR_ID3
+#define GPIO_IDR_IDR_4                   GPIO_IDR_ID4
+#define GPIO_IDR_IDR_5                   GPIO_IDR_ID5
+#define GPIO_IDR_IDR_6                   GPIO_IDR_ID6
+#define GPIO_IDR_IDR_7                   GPIO_IDR_ID7
+#define GPIO_IDR_IDR_8                   GPIO_IDR_ID8
+#define GPIO_IDR_IDR_9                   GPIO_IDR_ID9
+#define GPIO_IDR_IDR_10                  GPIO_IDR_ID10
+#define GPIO_IDR_IDR_11                  GPIO_IDR_ID11
+#define GPIO_IDR_IDR_12                  GPIO_IDR_ID12
+#define GPIO_IDR_IDR_13                  GPIO_IDR_ID13
+#define GPIO_IDR_IDR_14                  GPIO_IDR_ID14
+#define GPIO_IDR_IDR_15                  GPIO_IDR_ID15
+
+/******************  Bits definition for GPIO_ODR register  *******************/
+#define GPIO_ODR_OD0_Pos                 (0U)                                  
+#define GPIO_ODR_OD0_Msk                 (0x1UL << GPIO_ODR_OD0_Pos)            /*!< 0x00000001 */
+#define GPIO_ODR_OD0                     GPIO_ODR_OD0_Msk                      
+#define GPIO_ODR_OD1_Pos                 (1U)                                  
+#define GPIO_ODR_OD1_Msk                 (0x1UL << GPIO_ODR_OD1_Pos)            /*!< 0x00000002 */
+#define GPIO_ODR_OD1                     GPIO_ODR_OD1_Msk                      
+#define GPIO_ODR_OD2_Pos                 (2U)                                  
+#define GPIO_ODR_OD2_Msk                 (0x1UL << GPIO_ODR_OD2_Pos)            /*!< 0x00000004 */
+#define GPIO_ODR_OD2                     GPIO_ODR_OD2_Msk                      
+#define GPIO_ODR_OD3_Pos                 (3U)                                  
+#define GPIO_ODR_OD3_Msk                 (0x1UL << GPIO_ODR_OD3_Pos)            /*!< 0x00000008 */
+#define GPIO_ODR_OD3                     GPIO_ODR_OD3_Msk                      
+#define GPIO_ODR_OD4_Pos                 (4U)                                  
+#define GPIO_ODR_OD4_Msk                 (0x1UL << GPIO_ODR_OD4_Pos)            /*!< 0x00000010 */
+#define GPIO_ODR_OD4                     GPIO_ODR_OD4_Msk                      
+#define GPIO_ODR_OD5_Pos                 (5U)                                  
+#define GPIO_ODR_OD5_Msk                 (0x1UL << GPIO_ODR_OD5_Pos)            /*!< 0x00000020 */
+#define GPIO_ODR_OD5                     GPIO_ODR_OD5_Msk                      
+#define GPIO_ODR_OD6_Pos                 (6U)                                  
+#define GPIO_ODR_OD6_Msk                 (0x1UL << GPIO_ODR_OD6_Pos)            /*!< 0x00000040 */
+#define GPIO_ODR_OD6                     GPIO_ODR_OD6_Msk                      
+#define GPIO_ODR_OD7_Pos                 (7U)                                  
+#define GPIO_ODR_OD7_Msk                 (0x1UL << GPIO_ODR_OD7_Pos)            /*!< 0x00000080 */
+#define GPIO_ODR_OD7                     GPIO_ODR_OD7_Msk                      
+#define GPIO_ODR_OD8_Pos                 (8U)                                  
+#define GPIO_ODR_OD8_Msk                 (0x1UL << GPIO_ODR_OD8_Pos)            /*!< 0x00000100 */
+#define GPIO_ODR_OD8                     GPIO_ODR_OD8_Msk                      
+#define GPIO_ODR_OD9_Pos                 (9U)                                  
+#define GPIO_ODR_OD9_Msk                 (0x1UL << GPIO_ODR_OD9_Pos)            /*!< 0x00000200 */
+#define GPIO_ODR_OD9                     GPIO_ODR_OD9_Msk                      
+#define GPIO_ODR_OD10_Pos                (10U)                                 
+#define GPIO_ODR_OD10_Msk                (0x1UL << GPIO_ODR_OD10_Pos)           /*!< 0x00000400 */
+#define GPIO_ODR_OD10                    GPIO_ODR_OD10_Msk                     
+#define GPIO_ODR_OD11_Pos                (11U)                                 
+#define GPIO_ODR_OD11_Msk                (0x1UL << GPIO_ODR_OD11_Pos)           /*!< 0x00000800 */
+#define GPIO_ODR_OD11                    GPIO_ODR_OD11_Msk                     
+#define GPIO_ODR_OD12_Pos                (12U)                                 
+#define GPIO_ODR_OD12_Msk                (0x1UL << GPIO_ODR_OD12_Pos)           /*!< 0x00001000 */
+#define GPIO_ODR_OD12                    GPIO_ODR_OD12_Msk                     
+#define GPIO_ODR_OD13_Pos                (13U)                                 
+#define GPIO_ODR_OD13_Msk                (0x1UL << GPIO_ODR_OD13_Pos)           /*!< 0x00002000 */
+#define GPIO_ODR_OD13                    GPIO_ODR_OD13_Msk                     
+#define GPIO_ODR_OD14_Pos                (14U)                                 
+#define GPIO_ODR_OD14_Msk                (0x1UL << GPIO_ODR_OD14_Pos)           /*!< 0x00004000 */
+#define GPIO_ODR_OD14                    GPIO_ODR_OD14_Msk                     
+#define GPIO_ODR_OD15_Pos                (15U)                                 
+#define GPIO_ODR_OD15_Msk                (0x1UL << GPIO_ODR_OD15_Pos)           /*!< 0x00008000 */
+#define GPIO_ODR_OD15                    GPIO_ODR_OD15_Msk                     
+/* Legacy defines */
+#define GPIO_ODR_ODR_0                   GPIO_ODR_OD0
+#define GPIO_ODR_ODR_1                   GPIO_ODR_OD1
+#define GPIO_ODR_ODR_2                   GPIO_ODR_OD2
+#define GPIO_ODR_ODR_3                   GPIO_ODR_OD3
+#define GPIO_ODR_ODR_4                   GPIO_ODR_OD4
+#define GPIO_ODR_ODR_5                   GPIO_ODR_OD5
+#define GPIO_ODR_ODR_6                   GPIO_ODR_OD6
+#define GPIO_ODR_ODR_7                   GPIO_ODR_OD7
+#define GPIO_ODR_ODR_8                   GPIO_ODR_OD8
+#define GPIO_ODR_ODR_9                   GPIO_ODR_OD9
+#define GPIO_ODR_ODR_10                  GPIO_ODR_OD10
+#define GPIO_ODR_ODR_11                  GPIO_ODR_OD11
+#define GPIO_ODR_ODR_12                  GPIO_ODR_OD12
+#define GPIO_ODR_ODR_13                  GPIO_ODR_OD13
+#define GPIO_ODR_ODR_14                  GPIO_ODR_OD14
+#define GPIO_ODR_ODR_15                  GPIO_ODR_OD15
+
+/******************  Bits definition for GPIO_BSRR register  ******************/
+#define GPIO_BSRR_BS0_Pos                (0U)                                  
+#define GPIO_BSRR_BS0_Msk                (0x1UL << GPIO_BSRR_BS0_Pos)           /*!< 0x00000001 */
+#define GPIO_BSRR_BS0                    GPIO_BSRR_BS0_Msk                     
+#define GPIO_BSRR_BS1_Pos                (1U)                                  
+#define GPIO_BSRR_BS1_Msk                (0x1UL << GPIO_BSRR_BS1_Pos)           /*!< 0x00000002 */
+#define GPIO_BSRR_BS1                    GPIO_BSRR_BS1_Msk                     
+#define GPIO_BSRR_BS2_Pos                (2U)                                  
+#define GPIO_BSRR_BS2_Msk                (0x1UL << GPIO_BSRR_BS2_Pos)           /*!< 0x00000004 */
+#define GPIO_BSRR_BS2                    GPIO_BSRR_BS2_Msk                     
+#define GPIO_BSRR_BS3_Pos                (3U)                                  
+#define GPIO_BSRR_BS3_Msk                (0x1UL << GPIO_BSRR_BS3_Pos)           /*!< 0x00000008 */
+#define GPIO_BSRR_BS3                    GPIO_BSRR_BS3_Msk                     
+#define GPIO_BSRR_BS4_Pos                (4U)                                  
+#define GPIO_BSRR_BS4_Msk                (0x1UL << GPIO_BSRR_BS4_Pos)           /*!< 0x00000010 */
+#define GPIO_BSRR_BS4                    GPIO_BSRR_BS4_Msk                     
+#define GPIO_BSRR_BS5_Pos                (5U)                                  
+#define GPIO_BSRR_BS5_Msk                (0x1UL << GPIO_BSRR_BS5_Pos)           /*!< 0x00000020 */
+#define GPIO_BSRR_BS5                    GPIO_BSRR_BS5_Msk                     
+#define GPIO_BSRR_BS6_Pos                (6U)                                  
+#define GPIO_BSRR_BS6_Msk                (0x1UL << GPIO_BSRR_BS6_Pos)           /*!< 0x00000040 */
+#define GPIO_BSRR_BS6                    GPIO_BSRR_BS6_Msk                     
+#define GPIO_BSRR_BS7_Pos                (7U)                                  
+#define GPIO_BSRR_BS7_Msk                (0x1UL << GPIO_BSRR_BS7_Pos)           /*!< 0x00000080 */
+#define GPIO_BSRR_BS7                    GPIO_BSRR_BS7_Msk                     
+#define GPIO_BSRR_BS8_Pos                (8U)                                  
+#define GPIO_BSRR_BS8_Msk                (0x1UL << GPIO_BSRR_BS8_Pos)           /*!< 0x00000100 */
+#define GPIO_BSRR_BS8                    GPIO_BSRR_BS8_Msk                     
+#define GPIO_BSRR_BS9_Pos                (9U)                                  
+#define GPIO_BSRR_BS9_Msk                (0x1UL << GPIO_BSRR_BS9_Pos)           /*!< 0x00000200 */
+#define GPIO_BSRR_BS9                    GPIO_BSRR_BS9_Msk                     
+#define GPIO_BSRR_BS10_Pos               (10U)                                 
+#define GPIO_BSRR_BS10_Msk               (0x1UL << GPIO_BSRR_BS10_Pos)          /*!< 0x00000400 */
+#define GPIO_BSRR_BS10                   GPIO_BSRR_BS10_Msk                    
+#define GPIO_BSRR_BS11_Pos               (11U)                                 
+#define GPIO_BSRR_BS11_Msk               (0x1UL << GPIO_BSRR_BS11_Pos)          /*!< 0x00000800 */
+#define GPIO_BSRR_BS11                   GPIO_BSRR_BS11_Msk                    
+#define GPIO_BSRR_BS12_Pos               (12U)                                 
+#define GPIO_BSRR_BS12_Msk               (0x1UL << GPIO_BSRR_BS12_Pos)          /*!< 0x00001000 */
+#define GPIO_BSRR_BS12                   GPIO_BSRR_BS12_Msk                    
+#define GPIO_BSRR_BS13_Pos               (13U)                                 
+#define GPIO_BSRR_BS13_Msk               (0x1UL << GPIO_BSRR_BS13_Pos)          /*!< 0x00002000 */
+#define GPIO_BSRR_BS13                   GPIO_BSRR_BS13_Msk                    
+#define GPIO_BSRR_BS14_Pos               (14U)                                 
+#define GPIO_BSRR_BS14_Msk               (0x1UL << GPIO_BSRR_BS14_Pos)          /*!< 0x00004000 */
+#define GPIO_BSRR_BS14                   GPIO_BSRR_BS14_Msk                    
+#define GPIO_BSRR_BS15_Pos               (15U)                                 
+#define GPIO_BSRR_BS15_Msk               (0x1UL << GPIO_BSRR_BS15_Pos)          /*!< 0x00008000 */
+#define GPIO_BSRR_BS15                   GPIO_BSRR_BS15_Msk                    
+#define GPIO_BSRR_BR0_Pos                (16U)                                 
+#define GPIO_BSRR_BR0_Msk                (0x1UL << GPIO_BSRR_BR0_Pos)           /*!< 0x00010000 */
+#define GPIO_BSRR_BR0                    GPIO_BSRR_BR0_Msk                     
+#define GPIO_BSRR_BR1_Pos                (17U)                                 
+#define GPIO_BSRR_BR1_Msk                (0x1UL << GPIO_BSRR_BR1_Pos)           /*!< 0x00020000 */
+#define GPIO_BSRR_BR1                    GPIO_BSRR_BR1_Msk                     
+#define GPIO_BSRR_BR2_Pos                (18U)                                 
+#define GPIO_BSRR_BR2_Msk                (0x1UL << GPIO_BSRR_BR2_Pos)           /*!< 0x00040000 */
+#define GPIO_BSRR_BR2                    GPIO_BSRR_BR2_Msk                     
+#define GPIO_BSRR_BR3_Pos                (19U)                                 
+#define GPIO_BSRR_BR3_Msk                (0x1UL << GPIO_BSRR_BR3_Pos)           /*!< 0x00080000 */
+#define GPIO_BSRR_BR3                    GPIO_BSRR_BR3_Msk                     
+#define GPIO_BSRR_BR4_Pos                (20U)                                 
+#define GPIO_BSRR_BR4_Msk                (0x1UL << GPIO_BSRR_BR4_Pos)           /*!< 0x00100000 */
+#define GPIO_BSRR_BR4                    GPIO_BSRR_BR4_Msk                     
+#define GPIO_BSRR_BR5_Pos                (21U)                                 
+#define GPIO_BSRR_BR5_Msk                (0x1UL << GPIO_BSRR_BR5_Pos)           /*!< 0x00200000 */
+#define GPIO_BSRR_BR5                    GPIO_BSRR_BR5_Msk                     
+#define GPIO_BSRR_BR6_Pos                (22U)                                 
+#define GPIO_BSRR_BR6_Msk                (0x1UL << GPIO_BSRR_BR6_Pos)           /*!< 0x00400000 */
+#define GPIO_BSRR_BR6                    GPIO_BSRR_BR6_Msk                     
+#define GPIO_BSRR_BR7_Pos                (23U)                                 
+#define GPIO_BSRR_BR7_Msk                (0x1UL << GPIO_BSRR_BR7_Pos)           /*!< 0x00800000 */
+#define GPIO_BSRR_BR7                    GPIO_BSRR_BR7_Msk                     
+#define GPIO_BSRR_BR8_Pos                (24U)                                 
+#define GPIO_BSRR_BR8_Msk                (0x1UL << GPIO_BSRR_BR8_Pos)           /*!< 0x01000000 */
+#define GPIO_BSRR_BR8                    GPIO_BSRR_BR8_Msk                     
+#define GPIO_BSRR_BR9_Pos                (25U)                                 
+#define GPIO_BSRR_BR9_Msk                (0x1UL << GPIO_BSRR_BR9_Pos)           /*!< 0x02000000 */
+#define GPIO_BSRR_BR9                    GPIO_BSRR_BR9_Msk                     
+#define GPIO_BSRR_BR10_Pos               (26U)                                 
+#define GPIO_BSRR_BR10_Msk               (0x1UL << GPIO_BSRR_BR10_Pos)          /*!< 0x04000000 */
+#define GPIO_BSRR_BR10                   GPIO_BSRR_BR10_Msk                    
+#define GPIO_BSRR_BR11_Pos               (27U)                                 
+#define GPIO_BSRR_BR11_Msk               (0x1UL << GPIO_BSRR_BR11_Pos)          /*!< 0x08000000 */
+#define GPIO_BSRR_BR11                   GPIO_BSRR_BR11_Msk                    
+#define GPIO_BSRR_BR12_Pos               (28U)                                 
+#define GPIO_BSRR_BR12_Msk               (0x1UL << GPIO_BSRR_BR12_Pos)          /*!< 0x10000000 */
+#define GPIO_BSRR_BR12                   GPIO_BSRR_BR12_Msk                    
+#define GPIO_BSRR_BR13_Pos               (29U)                                 
+#define GPIO_BSRR_BR13_Msk               (0x1UL << GPIO_BSRR_BR13_Pos)          /*!< 0x20000000 */
+#define GPIO_BSRR_BR13                   GPIO_BSRR_BR13_Msk                    
+#define GPIO_BSRR_BR14_Pos               (30U)                                 
+#define GPIO_BSRR_BR14_Msk               (0x1UL << GPIO_BSRR_BR14_Pos)          /*!< 0x40000000 */
+#define GPIO_BSRR_BR14                   GPIO_BSRR_BR14_Msk                    
+#define GPIO_BSRR_BR15_Pos               (31U)                                 
+#define GPIO_BSRR_BR15_Msk               (0x1UL << GPIO_BSRR_BR15_Pos)          /*!< 0x80000000 */
+#define GPIO_BSRR_BR15                   GPIO_BSRR_BR15_Msk                    
+
+/* Legacy defines */
+#define GPIO_BSRR_BS_0                   GPIO_BSRR_BS0
+#define GPIO_BSRR_BS_1                   GPIO_BSRR_BS1
+#define GPIO_BSRR_BS_2                   GPIO_BSRR_BS2
+#define GPIO_BSRR_BS_3                   GPIO_BSRR_BS3
+#define GPIO_BSRR_BS_4                   GPIO_BSRR_BS4
+#define GPIO_BSRR_BS_5                   GPIO_BSRR_BS5
+#define GPIO_BSRR_BS_6                   GPIO_BSRR_BS6
+#define GPIO_BSRR_BS_7                   GPIO_BSRR_BS7
+#define GPIO_BSRR_BS_8                   GPIO_BSRR_BS8
+#define GPIO_BSRR_BS_9                   GPIO_BSRR_BS9
+#define GPIO_BSRR_BS_10                  GPIO_BSRR_BS10
+#define GPIO_BSRR_BS_11                  GPIO_BSRR_BS11
+#define GPIO_BSRR_BS_12                  GPIO_BSRR_BS12
+#define GPIO_BSRR_BS_13                  GPIO_BSRR_BS13
+#define GPIO_BSRR_BS_14                  GPIO_BSRR_BS14
+#define GPIO_BSRR_BS_15                  GPIO_BSRR_BS15
+#define GPIO_BSRR_BR_0                   GPIO_BSRR_BR0
+#define GPIO_BSRR_BR_1                   GPIO_BSRR_BR1
+#define GPIO_BSRR_BR_2                   GPIO_BSRR_BR2
+#define GPIO_BSRR_BR_3                   GPIO_BSRR_BR3
+#define GPIO_BSRR_BR_4                   GPIO_BSRR_BR4
+#define GPIO_BSRR_BR_5                   GPIO_BSRR_BR5
+#define GPIO_BSRR_BR_6                   GPIO_BSRR_BR6
+#define GPIO_BSRR_BR_7                   GPIO_BSRR_BR7
+#define GPIO_BSRR_BR_8                   GPIO_BSRR_BR8
+#define GPIO_BSRR_BR_9                   GPIO_BSRR_BR9
+#define GPIO_BSRR_BR_10                  GPIO_BSRR_BR10
+#define GPIO_BSRR_BR_11                  GPIO_BSRR_BR11
+#define GPIO_BSRR_BR_12                  GPIO_BSRR_BR12
+#define GPIO_BSRR_BR_13                  GPIO_BSRR_BR13
+#define GPIO_BSRR_BR_14                  GPIO_BSRR_BR14
+#define GPIO_BSRR_BR_15                  GPIO_BSRR_BR15
+#define GPIO_BRR_BR0                     GPIO_BSRR_BR0
+#define GPIO_BRR_BR0_Pos                 GPIO_BSRR_BR0_Pos
+#define GPIO_BRR_BR0_Msk                 GPIO_BSRR_BR0_Msk
+#define GPIO_BRR_BR1                     GPIO_BSRR_BR1
+#define GPIO_BRR_BR1_Pos                 GPIO_BSRR_BR1_Pos
+#define GPIO_BRR_BR1_Msk                 GPIO_BSRR_BR1_Msk
+#define GPIO_BRR_BR2                     GPIO_BSRR_BR2
+#define GPIO_BRR_BR2_Pos                 GPIO_BSRR_BR2_Pos
+#define GPIO_BRR_BR2_Msk                 GPIO_BSRR_BR2_Msk
+#define GPIO_BRR_BR3                     GPIO_BSRR_BR3
+#define GPIO_BRR_BR3_Pos                 GPIO_BSRR_BR3_Pos
+#define GPIO_BRR_BR3_Msk                 GPIO_BSRR_BR3_Msk
+#define GPIO_BRR_BR4                     GPIO_BSRR_BR4
+#define GPIO_BRR_BR4_Pos                 GPIO_BSRR_BR4_Pos
+#define GPIO_BRR_BR4_Msk                 GPIO_BSRR_BR4_Msk
+#define GPIO_BRR_BR5                     GPIO_BSRR_BR5
+#define GPIO_BRR_BR5_Pos                 GPIO_BSRR_BR5_Pos
+#define GPIO_BRR_BR5_Msk                 GPIO_BSRR_BR5_Msk
+#define GPIO_BRR_BR6                     GPIO_BSRR_BR6
+#define GPIO_BRR_BR6_Pos                 GPIO_BSRR_BR6_Pos
+#define GPIO_BRR_BR6_Msk                 GPIO_BSRR_BR6_Msk
+#define GPIO_BRR_BR7                     GPIO_BSRR_BR7
+#define GPIO_BRR_BR7_Pos                 GPIO_BSRR_BR7_Pos
+#define GPIO_BRR_BR7_Msk                 GPIO_BSRR_BR7_Msk
+#define GPIO_BRR_BR8                     GPIO_BSRR_BR8
+#define GPIO_BRR_BR8_Pos                 GPIO_BSRR_BR8_Pos
+#define GPIO_BRR_BR8_Msk                 GPIO_BSRR_BR8_Msk
+#define GPIO_BRR_BR9                     GPIO_BSRR_BR9
+#define GPIO_BRR_BR9_Pos                 GPIO_BSRR_BR9_Pos
+#define GPIO_BRR_BR9_Msk                 GPIO_BSRR_BR9_Msk
+#define GPIO_BRR_BR10                    GPIO_BSRR_BR10
+#define GPIO_BRR_BR10_Pos                GPIO_BSRR_BR10_Pos
+#define GPIO_BRR_BR10_Msk                GPIO_BSRR_BR10_Msk
+#define GPIO_BRR_BR11                    GPIO_BSRR_BR11
+#define GPIO_BRR_BR11_Pos                GPIO_BSRR_BR11_Pos
+#define GPIO_BRR_BR11_Msk                GPIO_BSRR_BR11_Msk
+#define GPIO_BRR_BR12                    GPIO_BSRR_BR12
+#define GPIO_BRR_BR12_Pos                GPIO_BSRR_BR12_Pos
+#define GPIO_BRR_BR12_Msk                GPIO_BSRR_BR12_Msk
+#define GPIO_BRR_BR13                    GPIO_BSRR_BR13
+#define GPIO_BRR_BR13_Pos                GPIO_BSRR_BR13_Pos
+#define GPIO_BRR_BR13_Msk                GPIO_BSRR_BR13_Msk
+#define GPIO_BRR_BR14                    GPIO_BSRR_BR14
+#define GPIO_BRR_BR14_Pos                GPIO_BSRR_BR14_Pos
+#define GPIO_BRR_BR14_Msk                GPIO_BSRR_BR14_Msk
+#define GPIO_BRR_BR15                    GPIO_BSRR_BR15
+#define GPIO_BRR_BR15_Pos                GPIO_BSRR_BR15_Pos
+#define GPIO_BRR_BR15_Msk                GPIO_BSRR_BR15_Msk 
+/****************** Bit definition for GPIO_LCKR register *********************/
+#define GPIO_LCKR_LCK0_Pos               (0U)                                  
+#define GPIO_LCKR_LCK0_Msk               (0x1UL << GPIO_LCKR_LCK0_Pos)          /*!< 0x00000001 */
+#define GPIO_LCKR_LCK0                   GPIO_LCKR_LCK0_Msk                    
+#define GPIO_LCKR_LCK1_Pos               (1U)                                  
+#define GPIO_LCKR_LCK1_Msk               (0x1UL << GPIO_LCKR_LCK1_Pos)          /*!< 0x00000002 */
+#define GPIO_LCKR_LCK1                   GPIO_LCKR_LCK1_Msk                    
+#define GPIO_LCKR_LCK2_Pos               (2U)                                  
+#define GPIO_LCKR_LCK2_Msk               (0x1UL << GPIO_LCKR_LCK2_Pos)          /*!< 0x00000004 */
+#define GPIO_LCKR_LCK2                   GPIO_LCKR_LCK2_Msk                    
+#define GPIO_LCKR_LCK3_Pos               (3U)                                  
+#define GPIO_LCKR_LCK3_Msk               (0x1UL << GPIO_LCKR_LCK3_Pos)          /*!< 0x00000008 */
+#define GPIO_LCKR_LCK3                   GPIO_LCKR_LCK3_Msk                    
+#define GPIO_LCKR_LCK4_Pos               (4U)                                  
+#define GPIO_LCKR_LCK4_Msk               (0x1UL << GPIO_LCKR_LCK4_Pos)          /*!< 0x00000010 */
+#define GPIO_LCKR_LCK4                   GPIO_LCKR_LCK4_Msk                    
+#define GPIO_LCKR_LCK5_Pos               (5U)                                  
+#define GPIO_LCKR_LCK5_Msk               (0x1UL << GPIO_LCKR_LCK5_Pos)          /*!< 0x00000020 */
+#define GPIO_LCKR_LCK5                   GPIO_LCKR_LCK5_Msk                    
+#define GPIO_LCKR_LCK6_Pos               (6U)                                  
+#define GPIO_LCKR_LCK6_Msk               (0x1UL << GPIO_LCKR_LCK6_Pos)          /*!< 0x00000040 */
+#define GPIO_LCKR_LCK6                   GPIO_LCKR_LCK6_Msk                    
+#define GPIO_LCKR_LCK7_Pos               (7U)                                  
+#define GPIO_LCKR_LCK7_Msk               (0x1UL << GPIO_LCKR_LCK7_Pos)          /*!< 0x00000080 */
+#define GPIO_LCKR_LCK7                   GPIO_LCKR_LCK7_Msk                    
+#define GPIO_LCKR_LCK8_Pos               (8U)                                  
+#define GPIO_LCKR_LCK8_Msk               (0x1UL << GPIO_LCKR_LCK8_Pos)          /*!< 0x00000100 */
+#define GPIO_LCKR_LCK8                   GPIO_LCKR_LCK8_Msk                    
+#define GPIO_LCKR_LCK9_Pos               (9U)                                  
+#define GPIO_LCKR_LCK9_Msk               (0x1UL << GPIO_LCKR_LCK9_Pos)          /*!< 0x00000200 */
+#define GPIO_LCKR_LCK9                   GPIO_LCKR_LCK9_Msk                    
+#define GPIO_LCKR_LCK10_Pos              (10U)                                 
+#define GPIO_LCKR_LCK10_Msk              (0x1UL << GPIO_LCKR_LCK10_Pos)         /*!< 0x00000400 */
+#define GPIO_LCKR_LCK10                  GPIO_LCKR_LCK10_Msk                   
+#define GPIO_LCKR_LCK11_Pos              (11U)                                 
+#define GPIO_LCKR_LCK11_Msk              (0x1UL << GPIO_LCKR_LCK11_Pos)         /*!< 0x00000800 */
+#define GPIO_LCKR_LCK11                  GPIO_LCKR_LCK11_Msk                   
+#define GPIO_LCKR_LCK12_Pos              (12U)                                 
+#define GPIO_LCKR_LCK12_Msk              (0x1UL << GPIO_LCKR_LCK12_Pos)         /*!< 0x00001000 */
+#define GPIO_LCKR_LCK12                  GPIO_LCKR_LCK12_Msk                   
+#define GPIO_LCKR_LCK13_Pos              (13U)                                 
+#define GPIO_LCKR_LCK13_Msk              (0x1UL << GPIO_LCKR_LCK13_Pos)         /*!< 0x00002000 */
+#define GPIO_LCKR_LCK13                  GPIO_LCKR_LCK13_Msk                   
+#define GPIO_LCKR_LCK14_Pos              (14U)                                 
+#define GPIO_LCKR_LCK14_Msk              (0x1UL << GPIO_LCKR_LCK14_Pos)         /*!< 0x00004000 */
+#define GPIO_LCKR_LCK14                  GPIO_LCKR_LCK14_Msk                   
+#define GPIO_LCKR_LCK15_Pos              (15U)                                 
+#define GPIO_LCKR_LCK15_Msk              (0x1UL << GPIO_LCKR_LCK15_Pos)         /*!< 0x00008000 */
+#define GPIO_LCKR_LCK15                  GPIO_LCKR_LCK15_Msk                   
+#define GPIO_LCKR_LCKK_Pos               (16U)                                 
+#define GPIO_LCKR_LCKK_Msk               (0x1UL << GPIO_LCKR_LCKK_Pos)          /*!< 0x00010000 */
+#define GPIO_LCKR_LCKK                   GPIO_LCKR_LCKK_Msk                    
+/****************** Bit definition for GPIO_AFRL register *********************/
+#define GPIO_AFRL_AFSEL0_Pos             (0U)                                  
+#define GPIO_AFRL_AFSEL0_Msk             (0xFUL << GPIO_AFRL_AFSEL0_Pos)        /*!< 0x0000000F */
+#define GPIO_AFRL_AFSEL0                 GPIO_AFRL_AFSEL0_Msk                  
+#define GPIO_AFRL_AFSEL0_0               (0x1UL << GPIO_AFRL_AFSEL0_Pos)        /*!< 0x00000001 */
+#define GPIO_AFRL_AFSEL0_1               (0x2UL << GPIO_AFRL_AFSEL0_Pos)        /*!< 0x00000002 */
+#define GPIO_AFRL_AFSEL0_2               (0x4UL << GPIO_AFRL_AFSEL0_Pos)        /*!< 0x00000004 */
+#define GPIO_AFRL_AFSEL0_3               (0x8UL << GPIO_AFRL_AFSEL0_Pos)        /*!< 0x00000008 */
+#define GPIO_AFRL_AFSEL1_Pos             (4U)                                  
+#define GPIO_AFRL_AFSEL1_Msk             (0xFUL << GPIO_AFRL_AFSEL1_Pos)        /*!< 0x000000F0 */
+#define GPIO_AFRL_AFSEL1                 GPIO_AFRL_AFSEL1_Msk                  
+#define GPIO_AFRL_AFSEL1_0               (0x1UL << GPIO_AFRL_AFSEL1_Pos)        /*!< 0x00000010 */
+#define GPIO_AFRL_AFSEL1_1               (0x2UL << GPIO_AFRL_AFSEL1_Pos)        /*!< 0x00000020 */
+#define GPIO_AFRL_AFSEL1_2               (0x4UL << GPIO_AFRL_AFSEL1_Pos)        /*!< 0x00000040 */
+#define GPIO_AFRL_AFSEL1_3               (0x8UL << GPIO_AFRL_AFSEL1_Pos)        /*!< 0x00000080 */
+#define GPIO_AFRL_AFSEL2_Pos             (8U)                                  
+#define GPIO_AFRL_AFSEL2_Msk             (0xFUL << GPIO_AFRL_AFSEL2_Pos)        /*!< 0x00000F00 */
+#define GPIO_AFRL_AFSEL2                 GPIO_AFRL_AFSEL2_Msk                  
+#define GPIO_AFRL_AFSEL2_0               (0x1UL << GPIO_AFRL_AFSEL2_Pos)        /*!< 0x00000100 */
+#define GPIO_AFRL_AFSEL2_1               (0x2UL << GPIO_AFRL_AFSEL2_Pos)        /*!< 0x00000200 */
+#define GPIO_AFRL_AFSEL2_2               (0x4UL << GPIO_AFRL_AFSEL2_Pos)        /*!< 0x00000400 */
+#define GPIO_AFRL_AFSEL2_3               (0x8UL << GPIO_AFRL_AFSEL2_Pos)        /*!< 0x00000800 */
+#define GPIO_AFRL_AFSEL3_Pos             (12U)                                 
+#define GPIO_AFRL_AFSEL3_Msk             (0xFUL << GPIO_AFRL_AFSEL3_Pos)        /*!< 0x0000F000 */
+#define GPIO_AFRL_AFSEL3                 GPIO_AFRL_AFSEL3_Msk                  
+#define GPIO_AFRL_AFSEL3_0               (0x1UL << GPIO_AFRL_AFSEL3_Pos)        /*!< 0x00001000 */
+#define GPIO_AFRL_AFSEL3_1               (0x2UL << GPIO_AFRL_AFSEL3_Pos)        /*!< 0x00002000 */
+#define GPIO_AFRL_AFSEL3_2               (0x4UL << GPIO_AFRL_AFSEL3_Pos)        /*!< 0x00004000 */
+#define GPIO_AFRL_AFSEL3_3               (0x8UL << GPIO_AFRL_AFSEL3_Pos)        /*!< 0x00008000 */
+#define GPIO_AFRL_AFSEL4_Pos             (16U)                                 
+#define GPIO_AFRL_AFSEL4_Msk             (0xFUL << GPIO_AFRL_AFSEL4_Pos)        /*!< 0x000F0000 */
+#define GPIO_AFRL_AFSEL4                 GPIO_AFRL_AFSEL4_Msk                  
+#define GPIO_AFRL_AFSEL4_0               (0x1UL << GPIO_AFRL_AFSEL4_Pos)        /*!< 0x00010000 */
+#define GPIO_AFRL_AFSEL4_1               (0x2UL << GPIO_AFRL_AFSEL4_Pos)        /*!< 0x00020000 */
+#define GPIO_AFRL_AFSEL4_2               (0x4UL << GPIO_AFRL_AFSEL4_Pos)        /*!< 0x00040000 */
+#define GPIO_AFRL_AFSEL4_3               (0x8UL << GPIO_AFRL_AFSEL4_Pos)        /*!< 0x00080000 */
+#define GPIO_AFRL_AFSEL5_Pos             (20U)                                 
+#define GPIO_AFRL_AFSEL5_Msk             (0xFUL << GPIO_AFRL_AFSEL5_Pos)        /*!< 0x00F00000 */
+#define GPIO_AFRL_AFSEL5                 GPIO_AFRL_AFSEL5_Msk                  
+#define GPIO_AFRL_AFSEL5_0               (0x1UL << GPIO_AFRL_AFSEL5_Pos)        /*!< 0x00100000 */
+#define GPIO_AFRL_AFSEL5_1               (0x2UL << GPIO_AFRL_AFSEL5_Pos)        /*!< 0x00200000 */
+#define GPIO_AFRL_AFSEL5_2               (0x4UL << GPIO_AFRL_AFSEL5_Pos)        /*!< 0x00400000 */
+#define GPIO_AFRL_AFSEL5_3               (0x8UL << GPIO_AFRL_AFSEL5_Pos)        /*!< 0x00800000 */
+#define GPIO_AFRL_AFSEL6_Pos             (24U)                                 
+#define GPIO_AFRL_AFSEL6_Msk             (0xFUL << GPIO_AFRL_AFSEL6_Pos)        /*!< 0x0F000000 */
+#define GPIO_AFRL_AFSEL6                 GPIO_AFRL_AFSEL6_Msk                  
+#define GPIO_AFRL_AFSEL6_0               (0x1UL << GPIO_AFRL_AFSEL6_Pos)        /*!< 0x01000000 */
+#define GPIO_AFRL_AFSEL6_1               (0x2UL << GPIO_AFRL_AFSEL6_Pos)        /*!< 0x02000000 */
+#define GPIO_AFRL_AFSEL6_2               (0x4UL << GPIO_AFRL_AFSEL6_Pos)        /*!< 0x04000000 */
+#define GPIO_AFRL_AFSEL6_3               (0x8UL << GPIO_AFRL_AFSEL6_Pos)        /*!< 0x08000000 */
+#define GPIO_AFRL_AFSEL7_Pos             (28U)                                 
+#define GPIO_AFRL_AFSEL7_Msk             (0xFUL << GPIO_AFRL_AFSEL7_Pos)        /*!< 0xF0000000 */
+#define GPIO_AFRL_AFSEL7                 GPIO_AFRL_AFSEL7_Msk                  
+#define GPIO_AFRL_AFSEL7_0               (0x1UL << GPIO_AFRL_AFSEL7_Pos)        /*!< 0x10000000 */
+#define GPIO_AFRL_AFSEL7_1               (0x2UL << GPIO_AFRL_AFSEL7_Pos)        /*!< 0x20000000 */
+#define GPIO_AFRL_AFSEL7_2               (0x4UL << GPIO_AFRL_AFSEL7_Pos)        /*!< 0x40000000 */
+#define GPIO_AFRL_AFSEL7_3               (0x8UL << GPIO_AFRL_AFSEL7_Pos)        /*!< 0x80000000 */
+
+/* Legacy defines */
+#define GPIO_AFRL_AFRL0                  GPIO_AFRL_AFSEL0
+#define GPIO_AFRL_AFRL0_0                GPIO_AFRL_AFSEL0_0
+#define GPIO_AFRL_AFRL0_1                GPIO_AFRL_AFSEL0_1
+#define GPIO_AFRL_AFRL0_2                GPIO_AFRL_AFSEL0_2
+#define GPIO_AFRL_AFRL0_3                GPIO_AFRL_AFSEL0_3
+#define GPIO_AFRL_AFRL1                  GPIO_AFRL_AFSEL1
+#define GPIO_AFRL_AFRL1_0                GPIO_AFRL_AFSEL1_0
+#define GPIO_AFRL_AFRL1_1                GPIO_AFRL_AFSEL1_1
+#define GPIO_AFRL_AFRL1_2                GPIO_AFRL_AFSEL1_2
+#define GPIO_AFRL_AFRL1_3                GPIO_AFRL_AFSEL1_3
+#define GPIO_AFRL_AFRL2                  GPIO_AFRL_AFSEL2
+#define GPIO_AFRL_AFRL2_0                GPIO_AFRL_AFSEL2_0
+#define GPIO_AFRL_AFRL2_1                GPIO_AFRL_AFSEL2_1
+#define GPIO_AFRL_AFRL2_2                GPIO_AFRL_AFSEL2_2
+#define GPIO_AFRL_AFRL2_3                GPIO_AFRL_AFSEL2_3
+#define GPIO_AFRL_AFRL3                  GPIO_AFRL_AFSEL3
+#define GPIO_AFRL_AFRL3_0                GPIO_AFRL_AFSEL3_0
+#define GPIO_AFRL_AFRL3_1                GPIO_AFRL_AFSEL3_1
+#define GPIO_AFRL_AFRL3_2                GPIO_AFRL_AFSEL3_2
+#define GPIO_AFRL_AFRL3_3                GPIO_AFRL_AFSEL3_3
+#define GPIO_AFRL_AFRL4                  GPIO_AFRL_AFSEL4
+#define GPIO_AFRL_AFRL4_0                GPIO_AFRL_AFSEL4_0
+#define GPIO_AFRL_AFRL4_1                GPIO_AFRL_AFSEL4_1
+#define GPIO_AFRL_AFRL4_2                GPIO_AFRL_AFSEL4_2
+#define GPIO_AFRL_AFRL4_3                GPIO_AFRL_AFSEL4_3
+#define GPIO_AFRL_AFRL5                  GPIO_AFRL_AFSEL5
+#define GPIO_AFRL_AFRL5_0                GPIO_AFRL_AFSEL5_0
+#define GPIO_AFRL_AFRL5_1                GPIO_AFRL_AFSEL5_1
+#define GPIO_AFRL_AFRL5_2                GPIO_AFRL_AFSEL5_2
+#define GPIO_AFRL_AFRL5_3                GPIO_AFRL_AFSEL5_3
+#define GPIO_AFRL_AFRL6                  GPIO_AFRL_AFSEL6
+#define GPIO_AFRL_AFRL6_0                GPIO_AFRL_AFSEL6_0
+#define GPIO_AFRL_AFRL6_1                GPIO_AFRL_AFSEL6_1
+#define GPIO_AFRL_AFRL6_2                GPIO_AFRL_AFSEL6_2
+#define GPIO_AFRL_AFRL6_3                GPIO_AFRL_AFSEL6_3
+#define GPIO_AFRL_AFRL7                  GPIO_AFRL_AFSEL7
+#define GPIO_AFRL_AFRL7_0                GPIO_AFRL_AFSEL7_0
+#define GPIO_AFRL_AFRL7_1                GPIO_AFRL_AFSEL7_1
+#define GPIO_AFRL_AFRL7_2                GPIO_AFRL_AFSEL7_2
+#define GPIO_AFRL_AFRL7_3                GPIO_AFRL_AFSEL7_3
+
+/****************** Bit definition for GPIO_AFRH register *********************/
+#define GPIO_AFRH_AFSEL8_Pos             (0U)                                  
+#define GPIO_AFRH_AFSEL8_Msk             (0xFUL << GPIO_AFRH_AFSEL8_Pos)        /*!< 0x0000000F */
+#define GPIO_AFRH_AFSEL8                 GPIO_AFRH_AFSEL8_Msk                  
+#define GPIO_AFRH_AFSEL8_0               (0x1UL << GPIO_AFRH_AFSEL8_Pos)        /*!< 0x00000001 */
+#define GPIO_AFRH_AFSEL8_1               (0x2UL << GPIO_AFRH_AFSEL8_Pos)        /*!< 0x00000002 */
+#define GPIO_AFRH_AFSEL8_2               (0x4UL << GPIO_AFRH_AFSEL8_Pos)        /*!< 0x00000004 */
+#define GPIO_AFRH_AFSEL8_3               (0x8UL << GPIO_AFRH_AFSEL8_Pos)        /*!< 0x00000008 */
+#define GPIO_AFRH_AFSEL9_Pos             (4U)                                  
+#define GPIO_AFRH_AFSEL9_Msk             (0xFUL << GPIO_AFRH_AFSEL9_Pos)        /*!< 0x000000F0 */
+#define GPIO_AFRH_AFSEL9                 GPIO_AFRH_AFSEL9_Msk                  
+#define GPIO_AFRH_AFSEL9_0               (0x1UL << GPIO_AFRH_AFSEL9_Pos)        /*!< 0x00000010 */
+#define GPIO_AFRH_AFSEL9_1               (0x2UL << GPIO_AFRH_AFSEL9_Pos)        /*!< 0x00000020 */
+#define GPIO_AFRH_AFSEL9_2               (0x4UL << GPIO_AFRH_AFSEL9_Pos)        /*!< 0x00000040 */
+#define GPIO_AFRH_AFSEL9_3               (0x8UL << GPIO_AFRH_AFSEL9_Pos)        /*!< 0x00000080 */
+#define GPIO_AFRH_AFSEL10_Pos            (8U)                                  
+#define GPIO_AFRH_AFSEL10_Msk            (0xFUL << GPIO_AFRH_AFSEL10_Pos)       /*!< 0x00000F00 */
+#define GPIO_AFRH_AFSEL10                GPIO_AFRH_AFSEL10_Msk                 
+#define GPIO_AFRH_AFSEL10_0              (0x1UL << GPIO_AFRH_AFSEL10_Pos)       /*!< 0x00000100 */
+#define GPIO_AFRH_AFSEL10_1              (0x2UL << GPIO_AFRH_AFSEL10_Pos)       /*!< 0x00000200 */
+#define GPIO_AFRH_AFSEL10_2              (0x4UL << GPIO_AFRH_AFSEL10_Pos)       /*!< 0x00000400 */
+#define GPIO_AFRH_AFSEL10_3              (0x8UL << GPIO_AFRH_AFSEL10_Pos)       /*!< 0x00000800 */
+#define GPIO_AFRH_AFSEL11_Pos            (12U)                                 
+#define GPIO_AFRH_AFSEL11_Msk            (0xFUL << GPIO_AFRH_AFSEL11_Pos)       /*!< 0x0000F000 */
+#define GPIO_AFRH_AFSEL11                GPIO_AFRH_AFSEL11_Msk                 
+#define GPIO_AFRH_AFSEL11_0              (0x1UL << GPIO_AFRH_AFSEL11_Pos)       /*!< 0x00001000 */
+#define GPIO_AFRH_AFSEL11_1              (0x2UL << GPIO_AFRH_AFSEL11_Pos)       /*!< 0x00002000 */
+#define GPIO_AFRH_AFSEL11_2              (0x4UL << GPIO_AFRH_AFSEL11_Pos)       /*!< 0x00004000 */
+#define GPIO_AFRH_AFSEL11_3              (0x8UL << GPIO_AFRH_AFSEL11_Pos)       /*!< 0x00008000 */
+#define GPIO_AFRH_AFSEL12_Pos            (16U)                                 
+#define GPIO_AFRH_AFSEL12_Msk            (0xFUL << GPIO_AFRH_AFSEL12_Pos)       /*!< 0x000F0000 */
+#define GPIO_AFRH_AFSEL12                GPIO_AFRH_AFSEL12_Msk                 
+#define GPIO_AFRH_AFSEL12_0              (0x1UL << GPIO_AFRH_AFSEL12_Pos)       /*!< 0x00010000 */
+#define GPIO_AFRH_AFSEL12_1              (0x2UL << GPIO_AFRH_AFSEL12_Pos)       /*!< 0x00020000 */
+#define GPIO_AFRH_AFSEL12_2              (0x4UL << GPIO_AFRH_AFSEL12_Pos)       /*!< 0x00040000 */
+#define GPIO_AFRH_AFSEL12_3              (0x8UL << GPIO_AFRH_AFSEL12_Pos)       /*!< 0x00080000 */
+#define GPIO_AFRH_AFSEL13_Pos            (20U)                                 
+#define GPIO_AFRH_AFSEL13_Msk            (0xFUL << GPIO_AFRH_AFSEL13_Pos)       /*!< 0x00F00000 */
+#define GPIO_AFRH_AFSEL13                GPIO_AFRH_AFSEL13_Msk                 
+#define GPIO_AFRH_AFSEL13_0              (0x1UL << GPIO_AFRH_AFSEL13_Pos)       /*!< 0x00100000 */
+#define GPIO_AFRH_AFSEL13_1              (0x2UL << GPIO_AFRH_AFSEL13_Pos)       /*!< 0x00200000 */
+#define GPIO_AFRH_AFSEL13_2              (0x4UL << GPIO_AFRH_AFSEL13_Pos)       /*!< 0x00400000 */
+#define GPIO_AFRH_AFSEL13_3              (0x8UL << GPIO_AFRH_AFSEL13_Pos)       /*!< 0x00800000 */
+#define GPIO_AFRH_AFSEL14_Pos            (24U)                                 
+#define GPIO_AFRH_AFSEL14_Msk            (0xFUL << GPIO_AFRH_AFSEL14_Pos)       /*!< 0x0F000000 */
+#define GPIO_AFRH_AFSEL14                GPIO_AFRH_AFSEL14_Msk                 
+#define GPIO_AFRH_AFSEL14_0              (0x1UL << GPIO_AFRH_AFSEL14_Pos)       /*!< 0x01000000 */
+#define GPIO_AFRH_AFSEL14_1              (0x2UL << GPIO_AFRH_AFSEL14_Pos)       /*!< 0x02000000 */
+#define GPIO_AFRH_AFSEL14_2              (0x4UL << GPIO_AFRH_AFSEL14_Pos)       /*!< 0x04000000 */
+#define GPIO_AFRH_AFSEL14_3              (0x8UL << GPIO_AFRH_AFSEL14_Pos)       /*!< 0x08000000 */
+#define GPIO_AFRH_AFSEL15_Pos            (28U)                                 
+#define GPIO_AFRH_AFSEL15_Msk            (0xFUL << GPIO_AFRH_AFSEL15_Pos)       /*!< 0xF0000000 */
+#define GPIO_AFRH_AFSEL15                GPIO_AFRH_AFSEL15_Msk                 
+#define GPIO_AFRH_AFSEL15_0              (0x1UL << GPIO_AFRH_AFSEL15_Pos)       /*!< 0x10000000 */
+#define GPIO_AFRH_AFSEL15_1              (0x2UL << GPIO_AFRH_AFSEL15_Pos)       /*!< 0x20000000 */
+#define GPIO_AFRH_AFSEL15_2              (0x4UL << GPIO_AFRH_AFSEL15_Pos)       /*!< 0x40000000 */
+#define GPIO_AFRH_AFSEL15_3              (0x8UL << GPIO_AFRH_AFSEL15_Pos)       /*!< 0x80000000 */
+
+/* Legacy defines */
+#define GPIO_AFRH_AFRH0                  GPIO_AFRH_AFSEL8
+#define GPIO_AFRH_AFRH0_0                GPIO_AFRH_AFSEL8_0
+#define GPIO_AFRH_AFRH0_1                GPIO_AFRH_AFSEL8_1
+#define GPIO_AFRH_AFRH0_2                GPIO_AFRH_AFSEL8_2
+#define GPIO_AFRH_AFRH0_3                GPIO_AFRH_AFSEL8_3
+#define GPIO_AFRH_AFRH1                  GPIO_AFRH_AFSEL9
+#define GPIO_AFRH_AFRH1_0                GPIO_AFRH_AFSEL9_0
+#define GPIO_AFRH_AFRH1_1                GPIO_AFRH_AFSEL9_1
+#define GPIO_AFRH_AFRH1_2                GPIO_AFRH_AFSEL9_2
+#define GPIO_AFRH_AFRH1_3                GPIO_AFRH_AFSEL9_3
+#define GPIO_AFRH_AFRH2                  GPIO_AFRH_AFSEL10
+#define GPIO_AFRH_AFRH2_0                GPIO_AFRH_AFSEL10_0
+#define GPIO_AFRH_AFRH2_1                GPIO_AFRH_AFSEL10_1
+#define GPIO_AFRH_AFRH2_2                GPIO_AFRH_AFSEL10_2
+#define GPIO_AFRH_AFRH2_3                GPIO_AFRH_AFSEL10_3
+#define GPIO_AFRH_AFRH3                  GPIO_AFRH_AFSEL11
+#define GPIO_AFRH_AFRH3_0                GPIO_AFRH_AFSEL11_0
+#define GPIO_AFRH_AFRH3_1                GPIO_AFRH_AFSEL11_1
+#define GPIO_AFRH_AFRH3_2                GPIO_AFRH_AFSEL11_2
+#define GPIO_AFRH_AFRH3_3                GPIO_AFRH_AFSEL11_3
+#define GPIO_AFRH_AFRH4                  GPIO_AFRH_AFSEL12
+#define GPIO_AFRH_AFRH4_0                GPIO_AFRH_AFSEL12_0
+#define GPIO_AFRH_AFRH4_1                GPIO_AFRH_AFSEL12_1
+#define GPIO_AFRH_AFRH4_2                GPIO_AFRH_AFSEL12_2
+#define GPIO_AFRH_AFRH4_3                GPIO_AFRH_AFSEL12_3
+#define GPIO_AFRH_AFRH5                  GPIO_AFRH_AFSEL13
+#define GPIO_AFRH_AFRH5_0                GPIO_AFRH_AFSEL13_0
+#define GPIO_AFRH_AFRH5_1                GPIO_AFRH_AFSEL13_1
+#define GPIO_AFRH_AFRH5_2                GPIO_AFRH_AFSEL13_2
+#define GPIO_AFRH_AFRH5_3                GPIO_AFRH_AFSEL13_3
+#define GPIO_AFRH_AFRH6                  GPIO_AFRH_AFSEL14
+#define GPIO_AFRH_AFRH6_0                GPIO_AFRH_AFSEL14_0
+#define GPIO_AFRH_AFRH6_1                GPIO_AFRH_AFSEL14_1
+#define GPIO_AFRH_AFRH6_2                GPIO_AFRH_AFSEL14_2
+#define GPIO_AFRH_AFRH6_3                GPIO_AFRH_AFSEL14_3
+#define GPIO_AFRH_AFRH7                  GPIO_AFRH_AFSEL15
+#define GPIO_AFRH_AFRH7_0                GPIO_AFRH_AFSEL15_0
+#define GPIO_AFRH_AFRH7_1                GPIO_AFRH_AFSEL15_1
+#define GPIO_AFRH_AFRH7_2                GPIO_AFRH_AFSEL15_2
+#define GPIO_AFRH_AFRH7_3                GPIO_AFRH_AFSEL15_3
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                      Inter-integrated Circuit Interface                    */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for I2C_CR1 register  ********************/
+#define I2C_CR1_PE_Pos            (0U)                                         
+#define I2C_CR1_PE_Msk            (0x1UL << I2C_CR1_PE_Pos)                     /*!< 0x00000001 */
+#define I2C_CR1_PE                I2C_CR1_PE_Msk                               /*!<Peripheral Enable                             */
+#define I2C_CR1_SMBUS_Pos         (1U)                                         
+#define I2C_CR1_SMBUS_Msk         (0x1UL << I2C_CR1_SMBUS_Pos)                  /*!< 0x00000002 */
+#define I2C_CR1_SMBUS             I2C_CR1_SMBUS_Msk                            /*!<SMBus Mode                                    */
+#define I2C_CR1_SMBTYPE_Pos       (3U)                                         
+#define I2C_CR1_SMBTYPE_Msk       (0x1UL << I2C_CR1_SMBTYPE_Pos)                /*!< 0x00000008 */
+#define I2C_CR1_SMBTYPE           I2C_CR1_SMBTYPE_Msk                          /*!<SMBus Type                                    */
+#define I2C_CR1_ENARP_Pos         (4U)                                         
+#define I2C_CR1_ENARP_Msk         (0x1UL << I2C_CR1_ENARP_Pos)                  /*!< 0x00000010 */
+#define I2C_CR1_ENARP             I2C_CR1_ENARP_Msk                            /*!<ARP Enable                                    */
+#define I2C_CR1_ENPEC_Pos         (5U)                                         
+#define I2C_CR1_ENPEC_Msk         (0x1UL << I2C_CR1_ENPEC_Pos)                  /*!< 0x00000020 */
+#define I2C_CR1_ENPEC             I2C_CR1_ENPEC_Msk                            /*!<PEC Enable                                    */
+#define I2C_CR1_ENGC_Pos          (6U)                                         
+#define I2C_CR1_ENGC_Msk          (0x1UL << I2C_CR1_ENGC_Pos)                   /*!< 0x00000040 */
+#define I2C_CR1_ENGC              I2C_CR1_ENGC_Msk                             /*!<General Call Enable                           */
+#define I2C_CR1_NOSTRETCH_Pos     (7U)                                         
+#define I2C_CR1_NOSTRETCH_Msk     (0x1UL << I2C_CR1_NOSTRETCH_Pos)              /*!< 0x00000080 */
+#define I2C_CR1_NOSTRETCH         I2C_CR1_NOSTRETCH_Msk                        /*!<Clock Stretching Disable (Slave mode)         */
+#define I2C_CR1_START_Pos         (8U)                                         
+#define I2C_CR1_START_Msk         (0x1UL << I2C_CR1_START_Pos)                  /*!< 0x00000100 */
+#define I2C_CR1_START             I2C_CR1_START_Msk                            /*!<Start Generation                              */
+#define I2C_CR1_STOP_Pos          (9U)                                         
+#define I2C_CR1_STOP_Msk          (0x1UL << I2C_CR1_STOP_Pos)                   /*!< 0x00000200 */
+#define I2C_CR1_STOP              I2C_CR1_STOP_Msk                             /*!<Stop Generation                               */
+#define I2C_CR1_ACK_Pos           (10U)                                        
+#define I2C_CR1_ACK_Msk           (0x1UL << I2C_CR1_ACK_Pos)                    /*!< 0x00000400 */
+#define I2C_CR1_ACK               I2C_CR1_ACK_Msk                              /*!<Acknowledge Enable                            */
+#define I2C_CR1_POS_Pos           (11U)                                        
+#define I2C_CR1_POS_Msk           (0x1UL << I2C_CR1_POS_Pos)                    /*!< 0x00000800 */
+#define I2C_CR1_POS               I2C_CR1_POS_Msk                              /*!<Acknowledge/PEC Position (for data reception) */
+#define I2C_CR1_PEC_Pos           (12U)                                        
+#define I2C_CR1_PEC_Msk           (0x1UL << I2C_CR1_PEC_Pos)                    /*!< 0x00001000 */
+#define I2C_CR1_PEC               I2C_CR1_PEC_Msk                              /*!<Packet Error Checking                         */
+#define I2C_CR1_ALERT_Pos         (13U)                                        
+#define I2C_CR1_ALERT_Msk         (0x1UL << I2C_CR1_ALERT_Pos)                  /*!< 0x00002000 */
+#define I2C_CR1_ALERT             I2C_CR1_ALERT_Msk                            /*!<SMBus Alert                                   */
+#define I2C_CR1_SWRST_Pos         (15U)                                        
+#define I2C_CR1_SWRST_Msk         (0x1UL << I2C_CR1_SWRST_Pos)                  /*!< 0x00008000 */
+#define I2C_CR1_SWRST             I2C_CR1_SWRST_Msk                            /*!<Software Reset                                */
+
+/*******************  Bit definition for I2C_CR2 register  ********************/
+#define I2C_CR2_FREQ_Pos          (0U)                                         
+#define I2C_CR2_FREQ_Msk          (0x3FUL << I2C_CR2_FREQ_Pos)                  /*!< 0x0000003F */
+#define I2C_CR2_FREQ              I2C_CR2_FREQ_Msk                             /*!<FREQ[5:0] bits (Peripheral Clock Frequency)   */
+#define I2C_CR2_FREQ_0            (0x01UL << I2C_CR2_FREQ_Pos)                  /*!< 0x00000001 */
+#define I2C_CR2_FREQ_1            (0x02UL << I2C_CR2_FREQ_Pos)                  /*!< 0x00000002 */
+#define I2C_CR2_FREQ_2            (0x04UL << I2C_CR2_FREQ_Pos)                  /*!< 0x00000004 */
+#define I2C_CR2_FREQ_3            (0x08UL << I2C_CR2_FREQ_Pos)                  /*!< 0x00000008 */
+#define I2C_CR2_FREQ_4            (0x10UL << I2C_CR2_FREQ_Pos)                  /*!< 0x00000010 */
+#define I2C_CR2_FREQ_5            (0x20UL << I2C_CR2_FREQ_Pos)                  /*!< 0x00000020 */
+
+#define I2C_CR2_ITERREN_Pos       (8U)                                         
+#define I2C_CR2_ITERREN_Msk       (0x1UL << I2C_CR2_ITERREN_Pos)                /*!< 0x00000100 */
+#define I2C_CR2_ITERREN           I2C_CR2_ITERREN_Msk                          /*!<Error Interrupt Enable  */
+#define I2C_CR2_ITEVTEN_Pos       (9U)                                         
+#define I2C_CR2_ITEVTEN_Msk       (0x1UL << I2C_CR2_ITEVTEN_Pos)                /*!< 0x00000200 */
+#define I2C_CR2_ITEVTEN           I2C_CR2_ITEVTEN_Msk                          /*!<Event Interrupt Enable  */
+#define I2C_CR2_ITBUFEN_Pos       (10U)                                        
+#define I2C_CR2_ITBUFEN_Msk       (0x1UL << I2C_CR2_ITBUFEN_Pos)                /*!< 0x00000400 */
+#define I2C_CR2_ITBUFEN           I2C_CR2_ITBUFEN_Msk                          /*!<Buffer Interrupt Enable */
+#define I2C_CR2_DMAEN_Pos         (11U)                                        
+#define I2C_CR2_DMAEN_Msk         (0x1UL << I2C_CR2_DMAEN_Pos)                  /*!< 0x00000800 */
+#define I2C_CR2_DMAEN             I2C_CR2_DMAEN_Msk                            /*!<DMA Requests Enable     */
+#define I2C_CR2_LAST_Pos          (12U)                                        
+#define I2C_CR2_LAST_Msk          (0x1UL << I2C_CR2_LAST_Pos)                   /*!< 0x00001000 */
+#define I2C_CR2_LAST              I2C_CR2_LAST_Msk                             /*!<DMA Last Transfer       */
+
+/*******************  Bit definition for I2C_OAR1 register  *******************/
+#define I2C_OAR1_ADD1_7           0x000000FEU                                  /*!<Interface Address */
+#define I2C_OAR1_ADD8_9           0x00000300U                                  /*!<Interface Address */
+
+#define I2C_OAR1_ADD0_Pos         (0U)                                         
+#define I2C_OAR1_ADD0_Msk         (0x1UL << I2C_OAR1_ADD0_Pos)                  /*!< 0x00000001 */
+#define I2C_OAR1_ADD0             I2C_OAR1_ADD0_Msk                            /*!<Bit 0 */
+#define I2C_OAR1_ADD1_Pos         (1U)                                         
+#define I2C_OAR1_ADD1_Msk         (0x1UL << I2C_OAR1_ADD1_Pos)                  /*!< 0x00000002 */
+#define I2C_OAR1_ADD1             I2C_OAR1_ADD1_Msk                            /*!<Bit 1 */
+#define I2C_OAR1_ADD2_Pos         (2U)                                         
+#define I2C_OAR1_ADD2_Msk         (0x1UL << I2C_OAR1_ADD2_Pos)                  /*!< 0x00000004 */
+#define I2C_OAR1_ADD2             I2C_OAR1_ADD2_Msk                            /*!<Bit 2 */
+#define I2C_OAR1_ADD3_Pos         (3U)                                         
+#define I2C_OAR1_ADD3_Msk         (0x1UL << I2C_OAR1_ADD3_Pos)                  /*!< 0x00000008 */
+#define I2C_OAR1_ADD3             I2C_OAR1_ADD3_Msk                            /*!<Bit 3 */
+#define I2C_OAR1_ADD4_Pos         (4U)                                         
+#define I2C_OAR1_ADD4_Msk         (0x1UL << I2C_OAR1_ADD4_Pos)                  /*!< 0x00000010 */
+#define I2C_OAR1_ADD4             I2C_OAR1_ADD4_Msk                            /*!<Bit 4 */
+#define I2C_OAR1_ADD5_Pos         (5U)                                         
+#define I2C_OAR1_ADD5_Msk         (0x1UL << I2C_OAR1_ADD5_Pos)                  /*!< 0x00000020 */
+#define I2C_OAR1_ADD5             I2C_OAR1_ADD5_Msk                            /*!<Bit 5 */
+#define I2C_OAR1_ADD6_Pos         (6U)                                         
+#define I2C_OAR1_ADD6_Msk         (0x1UL << I2C_OAR1_ADD6_Pos)                  /*!< 0x00000040 */
+#define I2C_OAR1_ADD6             I2C_OAR1_ADD6_Msk                            /*!<Bit 6 */
+#define I2C_OAR1_ADD7_Pos         (7U)                                         
+#define I2C_OAR1_ADD7_Msk         (0x1UL << I2C_OAR1_ADD7_Pos)                  /*!< 0x00000080 */
+#define I2C_OAR1_ADD7             I2C_OAR1_ADD7_Msk                            /*!<Bit 7 */
+#define I2C_OAR1_ADD8_Pos         (8U)                                         
+#define I2C_OAR1_ADD8_Msk         (0x1UL << I2C_OAR1_ADD8_Pos)                  /*!< 0x00000100 */
+#define I2C_OAR1_ADD8             I2C_OAR1_ADD8_Msk                            /*!<Bit 8 */
+#define I2C_OAR1_ADD9_Pos         (9U)                                         
+#define I2C_OAR1_ADD9_Msk         (0x1UL << I2C_OAR1_ADD9_Pos)                  /*!< 0x00000200 */
+#define I2C_OAR1_ADD9             I2C_OAR1_ADD9_Msk                            /*!<Bit 9 */
+
+#define I2C_OAR1_ADDMODE_Pos      (15U)                                        
+#define I2C_OAR1_ADDMODE_Msk      (0x1UL << I2C_OAR1_ADDMODE_Pos)               /*!< 0x00008000 */
+#define I2C_OAR1_ADDMODE          I2C_OAR1_ADDMODE_Msk                         /*!<Addressing Mode (Slave mode) */
+
+/*******************  Bit definition for I2C_OAR2 register  *******************/
+#define I2C_OAR2_ENDUAL_Pos       (0U)                                         
+#define I2C_OAR2_ENDUAL_Msk       (0x1UL << I2C_OAR2_ENDUAL_Pos)                /*!< 0x00000001 */
+#define I2C_OAR2_ENDUAL           I2C_OAR2_ENDUAL_Msk                          /*!<Dual addressing mode enable */
+#define I2C_OAR2_ADD2_Pos         (1U)                                         
+#define I2C_OAR2_ADD2_Msk         (0x7FUL << I2C_OAR2_ADD2_Pos)                 /*!< 0x000000FE */
+#define I2C_OAR2_ADD2             I2C_OAR2_ADD2_Msk                            /*!<Interface address           */
+
+/********************  Bit definition for I2C_DR register  ********************/
+#define I2C_DR_DR_Pos             (0U)                                         
+#define I2C_DR_DR_Msk             (0xFFUL << I2C_DR_DR_Pos)                     /*!< 0x000000FF */
+#define I2C_DR_DR                 I2C_DR_DR_Msk                                /*!<8-bit Data Register         */
+
+/*******************  Bit definition for I2C_SR1 register  ********************/
+#define I2C_SR1_SB_Pos            (0U)                                         
+#define I2C_SR1_SB_Msk            (0x1UL << I2C_SR1_SB_Pos)                     /*!< 0x00000001 */
+#define I2C_SR1_SB                I2C_SR1_SB_Msk                               /*!<Start Bit (Master mode)                         */
+#define I2C_SR1_ADDR_Pos          (1U)                                         
+#define I2C_SR1_ADDR_Msk          (0x1UL << I2C_SR1_ADDR_Pos)                   /*!< 0x00000002 */
+#define I2C_SR1_ADDR              I2C_SR1_ADDR_Msk                             /*!<Address sent (master mode)/matched (slave mode) */
+#define I2C_SR1_BTF_Pos           (2U)                                         
+#define I2C_SR1_BTF_Msk           (0x1UL << I2C_SR1_BTF_Pos)                    /*!< 0x00000004 */
+#define I2C_SR1_BTF               I2C_SR1_BTF_Msk                              /*!<Byte Transfer Finished                          */
+#define I2C_SR1_ADD10_Pos         (3U)                                         
+#define I2C_SR1_ADD10_Msk         (0x1UL << I2C_SR1_ADD10_Pos)                  /*!< 0x00000008 */
+#define I2C_SR1_ADD10             I2C_SR1_ADD10_Msk                            /*!<10-bit header sent (Master mode)                */
+#define I2C_SR1_STOPF_Pos         (4U)                                         
+#define I2C_SR1_STOPF_Msk         (0x1UL << I2C_SR1_STOPF_Pos)                  /*!< 0x00000010 */
+#define I2C_SR1_STOPF             I2C_SR1_STOPF_Msk                            /*!<Stop detection (Slave mode)                     */
+#define I2C_SR1_RXNE_Pos          (6U)                                         
+#define I2C_SR1_RXNE_Msk          (0x1UL << I2C_SR1_RXNE_Pos)                   /*!< 0x00000040 */
+#define I2C_SR1_RXNE              I2C_SR1_RXNE_Msk                             /*!<Data Register not Empty (receivers)             */
+#define I2C_SR1_TXE_Pos           (7U)                                         
+#define I2C_SR1_TXE_Msk           (0x1UL << I2C_SR1_TXE_Pos)                    /*!< 0x00000080 */
+#define I2C_SR1_TXE               I2C_SR1_TXE_Msk                              /*!<Data Register Empty (transmitters)              */
+#define I2C_SR1_BERR_Pos          (8U)                                         
+#define I2C_SR1_BERR_Msk          (0x1UL << I2C_SR1_BERR_Pos)                   /*!< 0x00000100 */
+#define I2C_SR1_BERR              I2C_SR1_BERR_Msk                             /*!<Bus Error                                       */
+#define I2C_SR1_ARLO_Pos          (9U)                                         
+#define I2C_SR1_ARLO_Msk          (0x1UL << I2C_SR1_ARLO_Pos)                   /*!< 0x00000200 */
+#define I2C_SR1_ARLO              I2C_SR1_ARLO_Msk                             /*!<Arbitration Lost (master mode)                  */
+#define I2C_SR1_AF_Pos            (10U)                                        
+#define I2C_SR1_AF_Msk            (0x1UL << I2C_SR1_AF_Pos)                     /*!< 0x00000400 */
+#define I2C_SR1_AF                I2C_SR1_AF_Msk                               /*!<Acknowledge Failure                             */
+#define I2C_SR1_OVR_Pos           (11U)                                        
+#define I2C_SR1_OVR_Msk           (0x1UL << I2C_SR1_OVR_Pos)                    /*!< 0x00000800 */
+#define I2C_SR1_OVR               I2C_SR1_OVR_Msk                              /*!<Overrun/Underrun                                */
+#define I2C_SR1_PECERR_Pos        (12U)                                        
+#define I2C_SR1_PECERR_Msk        (0x1UL << I2C_SR1_PECERR_Pos)                 /*!< 0x00001000 */
+#define I2C_SR1_PECERR            I2C_SR1_PECERR_Msk                           /*!<PEC Error in reception                          */
+#define I2C_SR1_TIMEOUT_Pos       (14U)                                        
+#define I2C_SR1_TIMEOUT_Msk       (0x1UL << I2C_SR1_TIMEOUT_Pos)                /*!< 0x00004000 */
+#define I2C_SR1_TIMEOUT           I2C_SR1_TIMEOUT_Msk                          /*!<Timeout or Tlow Error                           */
+#define I2C_SR1_SMBALERT_Pos      (15U)                                        
+#define I2C_SR1_SMBALERT_Msk      (0x1UL << I2C_SR1_SMBALERT_Pos)               /*!< 0x00008000 */
+#define I2C_SR1_SMBALERT          I2C_SR1_SMBALERT_Msk                         /*!<SMBus Alert                                     */
+
+/*******************  Bit definition for I2C_SR2 register  ********************/
+#define I2C_SR2_MSL_Pos           (0U)                                         
+#define I2C_SR2_MSL_Msk           (0x1UL << I2C_SR2_MSL_Pos)                    /*!< 0x00000001 */
+#define I2C_SR2_MSL               I2C_SR2_MSL_Msk                              /*!<Master/Slave                                    */
+#define I2C_SR2_BUSY_Pos          (1U)                                         
+#define I2C_SR2_BUSY_Msk          (0x1UL << I2C_SR2_BUSY_Pos)                   /*!< 0x00000002 */
+#define I2C_SR2_BUSY              I2C_SR2_BUSY_Msk                             /*!<Bus Busy                                        */
+#define I2C_SR2_TRA_Pos           (2U)                                         
+#define I2C_SR2_TRA_Msk           (0x1UL << I2C_SR2_TRA_Pos)                    /*!< 0x00000004 */
+#define I2C_SR2_TRA               I2C_SR2_TRA_Msk                              /*!<Transmitter/Receiver                            */
+#define I2C_SR2_GENCALL_Pos       (4U)                                         
+#define I2C_SR2_GENCALL_Msk       (0x1UL << I2C_SR2_GENCALL_Pos)                /*!< 0x00000010 */
+#define I2C_SR2_GENCALL           I2C_SR2_GENCALL_Msk                          /*!<General Call Address (Slave mode)               */
+#define I2C_SR2_SMBDEFAULT_Pos    (5U)                                         
+#define I2C_SR2_SMBDEFAULT_Msk    (0x1UL << I2C_SR2_SMBDEFAULT_Pos)             /*!< 0x00000020 */
+#define I2C_SR2_SMBDEFAULT        I2C_SR2_SMBDEFAULT_Msk                       /*!<SMBus Device Default Address (Slave mode)       */
+#define I2C_SR2_SMBHOST_Pos       (6U)                                         
+#define I2C_SR2_SMBHOST_Msk       (0x1UL << I2C_SR2_SMBHOST_Pos)                /*!< 0x00000040 */
+#define I2C_SR2_SMBHOST           I2C_SR2_SMBHOST_Msk                          /*!<SMBus Host Header (Slave mode)                  */
+#define I2C_SR2_DUALF_Pos         (7U)                                         
+#define I2C_SR2_DUALF_Msk         (0x1UL << I2C_SR2_DUALF_Pos)                  /*!< 0x00000080 */
+#define I2C_SR2_DUALF             I2C_SR2_DUALF_Msk                            /*!<Dual Flag (Slave mode)                          */
+#define I2C_SR2_PEC_Pos           (8U)                                         
+#define I2C_SR2_PEC_Msk           (0xFFUL << I2C_SR2_PEC_Pos)                   /*!< 0x0000FF00 */
+#define I2C_SR2_PEC               I2C_SR2_PEC_Msk                              /*!<Packet Error Checking Register                  */
+
+/*******************  Bit definition for I2C_CCR register  ********************/
+#define I2C_CCR_CCR_Pos           (0U)                                         
+#define I2C_CCR_CCR_Msk           (0xFFFUL << I2C_CCR_CCR_Pos)                  /*!< 0x00000FFF */
+#define I2C_CCR_CCR               I2C_CCR_CCR_Msk                              /*!<Clock Control Register in Fast/Standard mode (Master mode) */
+#define I2C_CCR_DUTY_Pos          (14U)                                        
+#define I2C_CCR_DUTY_Msk          (0x1UL << I2C_CCR_DUTY_Pos)                   /*!< 0x00004000 */
+#define I2C_CCR_DUTY              I2C_CCR_DUTY_Msk                             /*!<Fast Mode Duty Cycle                                       */
+#define I2C_CCR_FS_Pos            (15U)                                        
+#define I2C_CCR_FS_Msk            (0x1UL << I2C_CCR_FS_Pos)                     /*!< 0x00008000 */
+#define I2C_CCR_FS                I2C_CCR_FS_Msk                               /*!<I2C Master Mode Selection                                  */
+
+/******************  Bit definition for I2C_TRISE register  *******************/
+#define I2C_TRISE_TRISE_Pos       (0U)                                         
+#define I2C_TRISE_TRISE_Msk       (0x3FUL << I2C_TRISE_TRISE_Pos)               /*!< 0x0000003F */
+#define I2C_TRISE_TRISE           I2C_TRISE_TRISE_Msk                          /*!<Maximum Rise Time in Fast/Standard mode (Master mode) */
+
+/******************  Bit definition for I2C_FLTR register  *******************/
+#define I2C_FLTR_DNF_Pos          (0U)                                         
+#define I2C_FLTR_DNF_Msk          (0xFUL << I2C_FLTR_DNF_Pos)                   /*!< 0x0000000F */
+#define I2C_FLTR_DNF              I2C_FLTR_DNF_Msk                             /*!<Digital Noise Filter */
+#define I2C_FLTR_ANOFF_Pos        (4U)                                         
+#define I2C_FLTR_ANOFF_Msk        (0x1UL << I2C_FLTR_ANOFF_Pos)                 /*!< 0x00000010 */
+#define I2C_FLTR_ANOFF            I2C_FLTR_ANOFF_Msk                           /*!<Analog Noise Filter OFF */
+
+/******************************************************************************/
+/*                                                                            */
+/*                           Independent WATCHDOG                             */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for IWDG_KR register  ********************/
+#define IWDG_KR_KEY_Pos     (0U)                                               
+#define IWDG_KR_KEY_Msk     (0xFFFFUL << IWDG_KR_KEY_Pos)                       /*!< 0x0000FFFF */
+#define IWDG_KR_KEY         IWDG_KR_KEY_Msk                                    /*!<Key value (write only, read 0000h)  */
+
+/*******************  Bit definition for IWDG_PR register  ********************/
+#define IWDG_PR_PR_Pos      (0U)                                               
+#define IWDG_PR_PR_Msk      (0x7UL << IWDG_PR_PR_Pos)                           /*!< 0x00000007 */
+#define IWDG_PR_PR          IWDG_PR_PR_Msk                                     /*!<PR[2:0] (Prescaler divider)         */
+#define IWDG_PR_PR_0        (0x1UL << IWDG_PR_PR_Pos)                           /*!< 0x01 */
+#define IWDG_PR_PR_1        (0x2UL << IWDG_PR_PR_Pos)                           /*!< 0x02 */
+#define IWDG_PR_PR_2        (0x4UL << IWDG_PR_PR_Pos)                           /*!< 0x04 */
+
+/*******************  Bit definition for IWDG_RLR register  *******************/
+#define IWDG_RLR_RL_Pos     (0U)                                               
+#define IWDG_RLR_RL_Msk     (0xFFFUL << IWDG_RLR_RL_Pos)                        /*!< 0x00000FFF */
+#define IWDG_RLR_RL         IWDG_RLR_RL_Msk                                    /*!<Watchdog counter reload value        */
+
+/*******************  Bit definition for IWDG_SR register  ********************/
+#define IWDG_SR_PVU_Pos     (0U)                                               
+#define IWDG_SR_PVU_Msk     (0x1UL << IWDG_SR_PVU_Pos)                          /*!< 0x00000001 */
+#define IWDG_SR_PVU         IWDG_SR_PVU_Msk                                    /*!<Watchdog prescaler value update      */
+#define IWDG_SR_RVU_Pos     (1U)                                               
+#define IWDG_SR_RVU_Msk     (0x1UL << IWDG_SR_RVU_Pos)                          /*!< 0x00000002 */
+#define IWDG_SR_RVU         IWDG_SR_RVU_Msk                                    /*!<Watchdog counter reload value update */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                      LCD-TFT Display Controller (LTDC)                     */
+/*                                                                            */
+/******************************************************************************/
+
+/********************  Bit definition for LTDC_SSCR register  *****************/
+
+#define LTDC_SSCR_VSH_Pos            (0U)                                      
+#define LTDC_SSCR_VSH_Msk            (0x7FFUL << LTDC_SSCR_VSH_Pos)             /*!< 0x000007FF */
+#define LTDC_SSCR_VSH                LTDC_SSCR_VSH_Msk                         /*!< Vertical Synchronization Height */
+#define LTDC_SSCR_HSW_Pos            (16U)                                     
+#define LTDC_SSCR_HSW_Msk            (0xFFFUL << LTDC_SSCR_HSW_Pos)             /*!< 0x0FFF0000 */
+#define LTDC_SSCR_HSW                LTDC_SSCR_HSW_Msk                         /*!< Horizontal Synchronization Width */
+
+/********************  Bit definition for LTDC_BPCR register  *****************/
+
+#define LTDC_BPCR_AVBP_Pos           (0U)                                      
+#define LTDC_BPCR_AVBP_Msk           (0x7FFUL << LTDC_BPCR_AVBP_Pos)            /*!< 0x000007FF */
+#define LTDC_BPCR_AVBP               LTDC_BPCR_AVBP_Msk                        /*!< Accumulated Vertical Back Porch */
+#define LTDC_BPCR_AHBP_Pos           (16U)                                     
+#define LTDC_BPCR_AHBP_Msk           (0xFFFUL << LTDC_BPCR_AHBP_Pos)            /*!< 0x0FFF0000 */
+#define LTDC_BPCR_AHBP               LTDC_BPCR_AHBP_Msk                        /*!< Accumulated Horizontal Back Porch */
+
+/********************  Bit definition for LTDC_AWCR register  *****************/
+
+#define LTDC_AWCR_AAH_Pos            (0U)                                      
+#define LTDC_AWCR_AAH_Msk            (0x7FFUL << LTDC_AWCR_AAH_Pos)             /*!< 0x000007FF */
+#define LTDC_AWCR_AAH                LTDC_AWCR_AAH_Msk                         /*!< Accumulated Active Height */
+#define LTDC_AWCR_AAW_Pos            (16U)                                     
+#define LTDC_AWCR_AAW_Msk            (0xFFFUL << LTDC_AWCR_AAW_Pos)             /*!< 0x0FFF0000 */
+#define LTDC_AWCR_AAW                LTDC_AWCR_AAW_Msk                         /*!< Accumulated Active Width */
+
+/********************  Bit definition for LTDC_TWCR register  *****************/
+
+#define LTDC_TWCR_TOTALH_Pos         (0U)                                      
+#define LTDC_TWCR_TOTALH_Msk         (0x7FFUL << LTDC_TWCR_TOTALH_Pos)          /*!< 0x000007FF */
+#define LTDC_TWCR_TOTALH             LTDC_TWCR_TOTALH_Msk                      /*!< Total Height */
+#define LTDC_TWCR_TOTALW_Pos         (16U)                                     
+#define LTDC_TWCR_TOTALW_Msk         (0xFFFUL << LTDC_TWCR_TOTALW_Pos)          /*!< 0x0FFF0000 */
+#define LTDC_TWCR_TOTALW             LTDC_TWCR_TOTALW_Msk                      /*!< Total Width */
+
+/********************  Bit definition for LTDC_GCR register  ******************/
+
+#define LTDC_GCR_LTDCEN_Pos          (0U)                                      
+#define LTDC_GCR_LTDCEN_Msk          (0x1UL << LTDC_GCR_LTDCEN_Pos)             /*!< 0x00000001 */
+#define LTDC_GCR_LTDCEN              LTDC_GCR_LTDCEN_Msk                       /*!< LCD-TFT controller enable bit */
+#define LTDC_GCR_DBW_Pos             (4U)                                      
+#define LTDC_GCR_DBW_Msk             (0x7UL << LTDC_GCR_DBW_Pos)                /*!< 0x00000070 */
+#define LTDC_GCR_DBW                 LTDC_GCR_DBW_Msk                          /*!< Dither Blue Width */
+#define LTDC_GCR_DGW_Pos             (8U)                                      
+#define LTDC_GCR_DGW_Msk             (0x7UL << LTDC_GCR_DGW_Pos)                /*!< 0x00000700 */
+#define LTDC_GCR_DGW                 LTDC_GCR_DGW_Msk                          /*!< Dither Green Width */
+#define LTDC_GCR_DRW_Pos             (12U)                                     
+#define LTDC_GCR_DRW_Msk             (0x7UL << LTDC_GCR_DRW_Pos)                /*!< 0x00007000 */
+#define LTDC_GCR_DRW                 LTDC_GCR_DRW_Msk                          /*!< Dither Red Width */
+#define LTDC_GCR_DEN_Pos             (16U)                                     
+#define LTDC_GCR_DEN_Msk             (0x1UL << LTDC_GCR_DEN_Pos)                /*!< 0x00010000 */
+#define LTDC_GCR_DEN                 LTDC_GCR_DEN_Msk                          /*!< Dither Enable */
+#define LTDC_GCR_PCPOL_Pos           (28U)                                     
+#define LTDC_GCR_PCPOL_Msk           (0x1UL << LTDC_GCR_PCPOL_Pos)              /*!< 0x10000000 */
+#define LTDC_GCR_PCPOL               LTDC_GCR_PCPOL_Msk                        /*!< Pixel Clock Polarity */
+#define LTDC_GCR_DEPOL_Pos           (29U)                                     
+#define LTDC_GCR_DEPOL_Msk           (0x1UL << LTDC_GCR_DEPOL_Pos)              /*!< 0x20000000 */
+#define LTDC_GCR_DEPOL               LTDC_GCR_DEPOL_Msk                        /*!< Data Enable Polarity */
+#define LTDC_GCR_VSPOL_Pos           (30U)                                     
+#define LTDC_GCR_VSPOL_Msk           (0x1UL << LTDC_GCR_VSPOL_Pos)              /*!< 0x40000000 */
+#define LTDC_GCR_VSPOL               LTDC_GCR_VSPOL_Msk                        /*!< Vertical Synchronization Polarity */
+#define LTDC_GCR_HSPOL_Pos           (31U)                                     
+#define LTDC_GCR_HSPOL_Msk           (0x1UL << LTDC_GCR_HSPOL_Pos)              /*!< 0x80000000 */
+#define LTDC_GCR_HSPOL               LTDC_GCR_HSPOL_Msk                        /*!< Horizontal Synchronization Polarity */
+
+/* Legacy defines */
+#define LTDC_GCR_DTEN                       LTDC_GCR_DEN
+
+/********************  Bit definition for LTDC_SRCR register  *****************/
+
+#define LTDC_SRCR_IMR_Pos            (0U)                                      
+#define LTDC_SRCR_IMR_Msk            (0x1UL << LTDC_SRCR_IMR_Pos)               /*!< 0x00000001 */
+#define LTDC_SRCR_IMR                LTDC_SRCR_IMR_Msk                         /*!< Immediate Reload */
+#define LTDC_SRCR_VBR_Pos            (1U)                                      
+#define LTDC_SRCR_VBR_Msk            (0x1UL << LTDC_SRCR_VBR_Pos)               /*!< 0x00000002 */
+#define LTDC_SRCR_VBR                LTDC_SRCR_VBR_Msk                         /*!< Vertical Blanking Reload */
+
+/********************  Bit definition for LTDC_BCCR register  *****************/
+
+#define LTDC_BCCR_BCBLUE_Pos         (0U)                                      
+#define LTDC_BCCR_BCBLUE_Msk         (0xFFUL << LTDC_BCCR_BCBLUE_Pos)           /*!< 0x000000FF */
+#define LTDC_BCCR_BCBLUE             LTDC_BCCR_BCBLUE_Msk                      /*!< Background Blue value */
+#define LTDC_BCCR_BCGREEN_Pos        (8U)                                      
+#define LTDC_BCCR_BCGREEN_Msk        (0xFFUL << LTDC_BCCR_BCGREEN_Pos)          /*!< 0x0000FF00 */
+#define LTDC_BCCR_BCGREEN            LTDC_BCCR_BCGREEN_Msk                     /*!< Background Green value */
+#define LTDC_BCCR_BCRED_Pos          (16U)                                     
+#define LTDC_BCCR_BCRED_Msk          (0xFFUL << LTDC_BCCR_BCRED_Pos)            /*!< 0x00FF0000 */
+#define LTDC_BCCR_BCRED              LTDC_BCCR_BCRED_Msk                       /*!< Background Red value */
+
+/********************  Bit definition for LTDC_IER register  ******************/
+
+#define LTDC_IER_LIE_Pos             (0U)                                      
+#define LTDC_IER_LIE_Msk             (0x1UL << LTDC_IER_LIE_Pos)                /*!< 0x00000001 */
+#define LTDC_IER_LIE                 LTDC_IER_LIE_Msk                          /*!< Line Interrupt Enable */
+#define LTDC_IER_FUIE_Pos            (1U)                                      
+#define LTDC_IER_FUIE_Msk            (0x1UL << LTDC_IER_FUIE_Pos)               /*!< 0x00000002 */
+#define LTDC_IER_FUIE                LTDC_IER_FUIE_Msk                         /*!< FIFO Underrun Interrupt Enable */
+#define LTDC_IER_TERRIE_Pos          (2U)                                      
+#define LTDC_IER_TERRIE_Msk          (0x1UL << LTDC_IER_TERRIE_Pos)             /*!< 0x00000004 */
+#define LTDC_IER_TERRIE              LTDC_IER_TERRIE_Msk                       /*!< Transfer Error Interrupt Enable */
+#define LTDC_IER_RRIE_Pos            (3U)                                      
+#define LTDC_IER_RRIE_Msk            (0x1UL << LTDC_IER_RRIE_Pos)               /*!< 0x00000008 */
+#define LTDC_IER_RRIE                LTDC_IER_RRIE_Msk                         /*!< Register Reload interrupt enable */
+
+/********************  Bit definition for LTDC_ISR register  ******************/
+
+#define LTDC_ISR_LIF_Pos             (0U)                                      
+#define LTDC_ISR_LIF_Msk             (0x1UL << LTDC_ISR_LIF_Pos)                /*!< 0x00000001 */
+#define LTDC_ISR_LIF                 LTDC_ISR_LIF_Msk                          /*!< Line Interrupt Flag */
+#define LTDC_ISR_FUIF_Pos            (1U)                                      
+#define LTDC_ISR_FUIF_Msk            (0x1UL << LTDC_ISR_FUIF_Pos)               /*!< 0x00000002 */
+#define LTDC_ISR_FUIF                LTDC_ISR_FUIF_Msk                         /*!< FIFO Underrun Interrupt Flag */
+#define LTDC_ISR_TERRIF_Pos          (2U)                                      
+#define LTDC_ISR_TERRIF_Msk          (0x1UL << LTDC_ISR_TERRIF_Pos)             /*!< 0x00000004 */
+#define LTDC_ISR_TERRIF              LTDC_ISR_TERRIF_Msk                       /*!< Transfer Error Interrupt Flag */
+#define LTDC_ISR_RRIF_Pos            (3U)                                      
+#define LTDC_ISR_RRIF_Msk            (0x1UL << LTDC_ISR_RRIF_Pos)               /*!< 0x00000008 */
+#define LTDC_ISR_RRIF                LTDC_ISR_RRIF_Msk                         /*!< Register Reload interrupt Flag */
+
+/********************  Bit definition for LTDC_ICR register  ******************/
+
+#define LTDC_ICR_CLIF_Pos            (0U)                                      
+#define LTDC_ICR_CLIF_Msk            (0x1UL << LTDC_ICR_CLIF_Pos)               /*!< 0x00000001 */
+#define LTDC_ICR_CLIF                LTDC_ICR_CLIF_Msk                         /*!< Clears the Line Interrupt Flag */
+#define LTDC_ICR_CFUIF_Pos           (1U)                                      
+#define LTDC_ICR_CFUIF_Msk           (0x1UL << LTDC_ICR_CFUIF_Pos)              /*!< 0x00000002 */
+#define LTDC_ICR_CFUIF               LTDC_ICR_CFUIF_Msk                        /*!< Clears the FIFO Underrun Interrupt Flag */
+#define LTDC_ICR_CTERRIF_Pos         (2U)                                      
+#define LTDC_ICR_CTERRIF_Msk         (0x1UL << LTDC_ICR_CTERRIF_Pos)            /*!< 0x00000004 */
+#define LTDC_ICR_CTERRIF             LTDC_ICR_CTERRIF_Msk                      /*!< Clears the Transfer Error Interrupt Flag */
+#define LTDC_ICR_CRRIF_Pos           (3U)                                      
+#define LTDC_ICR_CRRIF_Msk           (0x1UL << LTDC_ICR_CRRIF_Pos)              /*!< 0x00000008 */
+#define LTDC_ICR_CRRIF               LTDC_ICR_CRRIF_Msk                        /*!< Clears Register Reload interrupt Flag */
+
+/********************  Bit definition for LTDC_LIPCR register  ****************/
+
+#define LTDC_LIPCR_LIPOS_Pos         (0U)                                      
+#define LTDC_LIPCR_LIPOS_Msk         (0x7FFUL << LTDC_LIPCR_LIPOS_Pos)          /*!< 0x000007FF */
+#define LTDC_LIPCR_LIPOS             LTDC_LIPCR_LIPOS_Msk                      /*!< Line Interrupt Position */
+
+/********************  Bit definition for LTDC_CPSR register  *****************/
+
+#define LTDC_CPSR_CYPOS_Pos          (0U)                                      
+#define LTDC_CPSR_CYPOS_Msk          (0xFFFFUL << LTDC_CPSR_CYPOS_Pos)          /*!< 0x0000FFFF */
+#define LTDC_CPSR_CYPOS              LTDC_CPSR_CYPOS_Msk                       /*!< Current Y Position */
+#define LTDC_CPSR_CXPOS_Pos          (16U)                                     
+#define LTDC_CPSR_CXPOS_Msk          (0xFFFFUL << LTDC_CPSR_CXPOS_Pos)          /*!< 0xFFFF0000 */
+#define LTDC_CPSR_CXPOS              LTDC_CPSR_CXPOS_Msk                       /*!< Current X Position */
+
+/********************  Bit definition for LTDC_CDSR register  *****************/
+
+#define LTDC_CDSR_VDES_Pos           (0U)                                      
+#define LTDC_CDSR_VDES_Msk           (0x1UL << LTDC_CDSR_VDES_Pos)              /*!< 0x00000001 */
+#define LTDC_CDSR_VDES               LTDC_CDSR_VDES_Msk                        /*!< Vertical Data Enable Status */
+#define LTDC_CDSR_HDES_Pos           (1U)                                      
+#define LTDC_CDSR_HDES_Msk           (0x1UL << LTDC_CDSR_HDES_Pos)              /*!< 0x00000002 */
+#define LTDC_CDSR_HDES               LTDC_CDSR_HDES_Msk                        /*!< Horizontal Data Enable Status */
+#define LTDC_CDSR_VSYNCS_Pos         (2U)                                      
+#define LTDC_CDSR_VSYNCS_Msk         (0x1UL << LTDC_CDSR_VSYNCS_Pos)            /*!< 0x00000004 */
+#define LTDC_CDSR_VSYNCS             LTDC_CDSR_VSYNCS_Msk                      /*!< Vertical Synchronization Status */
+#define LTDC_CDSR_HSYNCS_Pos         (3U)                                      
+#define LTDC_CDSR_HSYNCS_Msk         (0x1UL << LTDC_CDSR_HSYNCS_Pos)            /*!< 0x00000008 */
+#define LTDC_CDSR_HSYNCS             LTDC_CDSR_HSYNCS_Msk                      /*!< Horizontal Synchronization Status */
+
+/********************  Bit definition for LTDC_LxCR register  *****************/
+
+#define LTDC_LxCR_LEN_Pos            (0U)                                      
+#define LTDC_LxCR_LEN_Msk            (0x1UL << LTDC_LxCR_LEN_Pos)               /*!< 0x00000001 */
+#define LTDC_LxCR_LEN                LTDC_LxCR_LEN_Msk                         /*!< Layer Enable */
+#define LTDC_LxCR_COLKEN_Pos         (1U)                                      
+#define LTDC_LxCR_COLKEN_Msk         (0x1UL << LTDC_LxCR_COLKEN_Pos)            /*!< 0x00000002 */
+#define LTDC_LxCR_COLKEN             LTDC_LxCR_COLKEN_Msk                      /*!< Color Keying Enable */
+#define LTDC_LxCR_CLUTEN_Pos         (4U)                                      
+#define LTDC_LxCR_CLUTEN_Msk         (0x1UL << LTDC_LxCR_CLUTEN_Pos)            /*!< 0x00000010 */
+#define LTDC_LxCR_CLUTEN             LTDC_LxCR_CLUTEN_Msk                      /*!< Color Lockup Table Enable */
+
+/********************  Bit definition for LTDC_LxWHPCR register  **************/
+
+#define LTDC_LxWHPCR_WHSTPOS_Pos     (0U)                                      
+#define LTDC_LxWHPCR_WHSTPOS_Msk     (0xFFFUL << LTDC_LxWHPCR_WHSTPOS_Pos)      /*!< 0x00000FFF */
+#define LTDC_LxWHPCR_WHSTPOS         LTDC_LxWHPCR_WHSTPOS_Msk                  /*!< Window Horizontal Start Position */
+#define LTDC_LxWHPCR_WHSPPOS_Pos     (16U)                                     
+#define LTDC_LxWHPCR_WHSPPOS_Msk     (0xFFFFUL << LTDC_LxWHPCR_WHSPPOS_Pos)     /*!< 0xFFFF0000 */
+#define LTDC_LxWHPCR_WHSPPOS         LTDC_LxWHPCR_WHSPPOS_Msk                  /*!< Window Horizontal Stop Position */
+
+/********************  Bit definition for LTDC_LxWVPCR register  **************/
+
+#define LTDC_LxWVPCR_WVSTPOS_Pos     (0U)                                      
+#define LTDC_LxWVPCR_WVSTPOS_Msk     (0xFFFUL << LTDC_LxWVPCR_WVSTPOS_Pos)      /*!< 0x00000FFF */
+#define LTDC_LxWVPCR_WVSTPOS         LTDC_LxWVPCR_WVSTPOS_Msk                  /*!< Window Vertical Start Position */
+#define LTDC_LxWVPCR_WVSPPOS_Pos     (16U)                                     
+#define LTDC_LxWVPCR_WVSPPOS_Msk     (0xFFFFUL << LTDC_LxWVPCR_WVSPPOS_Pos)     /*!< 0xFFFF0000 */
+#define LTDC_LxWVPCR_WVSPPOS         LTDC_LxWVPCR_WVSPPOS_Msk                  /*!< Window Vertical Stop Position */
+
+/********************  Bit definition for LTDC_LxCKCR register  ***************/
+
+#define LTDC_LxCKCR_CKBLUE_Pos       (0U)                                      
+#define LTDC_LxCKCR_CKBLUE_Msk       (0xFFUL << LTDC_LxCKCR_CKBLUE_Pos)         /*!< 0x000000FF */
+#define LTDC_LxCKCR_CKBLUE           LTDC_LxCKCR_CKBLUE_Msk                    /*!< Color Key Blue value */
+#define LTDC_LxCKCR_CKGREEN_Pos      (8U)                                      
+#define LTDC_LxCKCR_CKGREEN_Msk      (0xFFUL << LTDC_LxCKCR_CKGREEN_Pos)        /*!< 0x0000FF00 */
+#define LTDC_LxCKCR_CKGREEN          LTDC_LxCKCR_CKGREEN_Msk                   /*!< Color Key Green value */
+#define LTDC_LxCKCR_CKRED_Pos        (16U)                                     
+#define LTDC_LxCKCR_CKRED_Msk        (0xFFUL << LTDC_LxCKCR_CKRED_Pos)          /*!< 0x00FF0000 */
+#define LTDC_LxCKCR_CKRED            LTDC_LxCKCR_CKRED_Msk                     /*!< Color Key Red value */
+
+/********************  Bit definition for LTDC_LxPFCR register  ***************/
+
+#define LTDC_LxPFCR_PF_Pos           (0U)                                      
+#define LTDC_LxPFCR_PF_Msk           (0x7UL << LTDC_LxPFCR_PF_Pos)              /*!< 0x00000007 */
+#define LTDC_LxPFCR_PF               LTDC_LxPFCR_PF_Msk                        /*!< Pixel Format */
+
+/********************  Bit definition for LTDC_LxCACR register  ***************/
+
+#define LTDC_LxCACR_CONSTA_Pos       (0U)                                      
+#define LTDC_LxCACR_CONSTA_Msk       (0xFFUL << LTDC_LxCACR_CONSTA_Pos)         /*!< 0x000000FF */
+#define LTDC_LxCACR_CONSTA           LTDC_LxCACR_CONSTA_Msk                    /*!< Constant Alpha */
+
+/********************  Bit definition for LTDC_LxDCCR register  ***************/
+
+#define LTDC_LxDCCR_DCBLUE_Pos       (0U)                                      
+#define LTDC_LxDCCR_DCBLUE_Msk       (0xFFUL << LTDC_LxDCCR_DCBLUE_Pos)         /*!< 0x000000FF */
+#define LTDC_LxDCCR_DCBLUE           LTDC_LxDCCR_DCBLUE_Msk                    /*!< Default Color Blue */
+#define LTDC_LxDCCR_DCGREEN_Pos      (8U)                                      
+#define LTDC_LxDCCR_DCGREEN_Msk      (0xFFUL << LTDC_LxDCCR_DCGREEN_Pos)        /*!< 0x0000FF00 */
+#define LTDC_LxDCCR_DCGREEN          LTDC_LxDCCR_DCGREEN_Msk                   /*!< Default Color Green */
+#define LTDC_LxDCCR_DCRED_Pos        (16U)                                     
+#define LTDC_LxDCCR_DCRED_Msk        (0xFFUL << LTDC_LxDCCR_DCRED_Pos)          /*!< 0x00FF0000 */
+#define LTDC_LxDCCR_DCRED            LTDC_LxDCCR_DCRED_Msk                     /*!< Default Color Red */
+#define LTDC_LxDCCR_DCALPHA_Pos      (24U)                                     
+#define LTDC_LxDCCR_DCALPHA_Msk      (0xFFUL << LTDC_LxDCCR_DCALPHA_Pos)        /*!< 0xFF000000 */
+#define LTDC_LxDCCR_DCALPHA          LTDC_LxDCCR_DCALPHA_Msk                   /*!< Default Color Alpha */
+                                
+/********************  Bit definition for LTDC_LxBFCR register  ***************/
+
+#define LTDC_LxBFCR_BF2_Pos          (0U)                                      
+#define LTDC_LxBFCR_BF2_Msk          (0x7UL << LTDC_LxBFCR_BF2_Pos)             /*!< 0x00000007 */
+#define LTDC_LxBFCR_BF2              LTDC_LxBFCR_BF2_Msk                       /*!< Blending Factor 2 */
+#define LTDC_LxBFCR_BF1_Pos          (8U)                                      
+#define LTDC_LxBFCR_BF1_Msk          (0x7UL << LTDC_LxBFCR_BF1_Pos)             /*!< 0x00000700 */
+#define LTDC_LxBFCR_BF1              LTDC_LxBFCR_BF1_Msk                       /*!< Blending Factor 1 */
+
+/********************  Bit definition for LTDC_LxCFBAR register  **************/
+
+#define LTDC_LxCFBAR_CFBADD_Pos      (0U)                                      
+#define LTDC_LxCFBAR_CFBADD_Msk      (0xFFFFFFFFUL << LTDC_LxCFBAR_CFBADD_Pos)  /*!< 0xFFFFFFFF */
+#define LTDC_LxCFBAR_CFBADD          LTDC_LxCFBAR_CFBADD_Msk                   /*!< Color Frame Buffer Start Address */
+
+/********************  Bit definition for LTDC_LxCFBLR register  **************/
+
+#define LTDC_LxCFBLR_CFBLL_Pos       (0U)                                      
+#define LTDC_LxCFBLR_CFBLL_Msk       (0x1FFFUL << LTDC_LxCFBLR_CFBLL_Pos)       /*!< 0x00001FFF */
+#define LTDC_LxCFBLR_CFBLL           LTDC_LxCFBLR_CFBLL_Msk                    /*!< Color Frame Buffer Line Length */
+#define LTDC_LxCFBLR_CFBP_Pos        (16U)                                     
+#define LTDC_LxCFBLR_CFBP_Msk        (0x1FFFUL << LTDC_LxCFBLR_CFBP_Pos)        /*!< 0x1FFF0000 */
+#define LTDC_LxCFBLR_CFBP            LTDC_LxCFBLR_CFBP_Msk                     /*!< Color Frame Buffer Pitch in bytes */
+
+/********************  Bit definition for LTDC_LxCFBLNR register  *************/
+
+#define LTDC_LxCFBLNR_CFBLNBR_Pos    (0U)                                      
+#define LTDC_LxCFBLNR_CFBLNBR_Msk    (0x7FFUL << LTDC_LxCFBLNR_CFBLNBR_Pos)     /*!< 0x000007FF */
+#define LTDC_LxCFBLNR_CFBLNBR        LTDC_LxCFBLNR_CFBLNBR_Msk                 /*!< Frame Buffer Line Number */
+
+/********************  Bit definition for LTDC_LxCLUTWR register  *************/
+
+#define LTDC_LxCLUTWR_BLUE_Pos       (0U)                                      
+#define LTDC_LxCLUTWR_BLUE_Msk       (0xFFUL << LTDC_LxCLUTWR_BLUE_Pos)         /*!< 0x000000FF */
+#define LTDC_LxCLUTWR_BLUE           LTDC_LxCLUTWR_BLUE_Msk                    /*!< Blue value */
+#define LTDC_LxCLUTWR_GREEN_Pos      (8U)                                      
+#define LTDC_LxCLUTWR_GREEN_Msk      (0xFFUL << LTDC_LxCLUTWR_GREEN_Pos)        /*!< 0x0000FF00 */
+#define LTDC_LxCLUTWR_GREEN          LTDC_LxCLUTWR_GREEN_Msk                   /*!< Green value */
+#define LTDC_LxCLUTWR_RED_Pos        (16U)                                     
+#define LTDC_LxCLUTWR_RED_Msk        (0xFFUL << LTDC_LxCLUTWR_RED_Pos)          /*!< 0x00FF0000 */
+#define LTDC_LxCLUTWR_RED            LTDC_LxCLUTWR_RED_Msk                     /*!< Red value */
+#define LTDC_LxCLUTWR_CLUTADD_Pos    (24U)                                     
+#define LTDC_LxCLUTWR_CLUTADD_Msk    (0xFFUL << LTDC_LxCLUTWR_CLUTADD_Pos)      /*!< 0xFF000000 */
+#define LTDC_LxCLUTWR_CLUTADD        LTDC_LxCLUTWR_CLUTADD_Msk                 /*!< CLUT address */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                             Power Control                                  */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bit definition for PWR_CR register  ********************/
+#define PWR_CR_LPDS_Pos        (0U)                                            
+#define PWR_CR_LPDS_Msk        (0x1UL << PWR_CR_LPDS_Pos)                       /*!< 0x00000001 */
+#define PWR_CR_LPDS            PWR_CR_LPDS_Msk                                 /*!< Low-Power Deepsleep                 */
+#define PWR_CR_PDDS_Pos        (1U)                                            
+#define PWR_CR_PDDS_Msk        (0x1UL << PWR_CR_PDDS_Pos)                       /*!< 0x00000002 */
+#define PWR_CR_PDDS            PWR_CR_PDDS_Msk                                 /*!< Power Down Deepsleep                */
+#define PWR_CR_CWUF_Pos        (2U)                                            
+#define PWR_CR_CWUF_Msk        (0x1UL << PWR_CR_CWUF_Pos)                       /*!< 0x00000004 */
+#define PWR_CR_CWUF            PWR_CR_CWUF_Msk                                 /*!< Clear Wakeup Flag                   */
+#define PWR_CR_CSBF_Pos        (3U)                                            
+#define PWR_CR_CSBF_Msk        (0x1UL << PWR_CR_CSBF_Pos)                       /*!< 0x00000008 */
+#define PWR_CR_CSBF            PWR_CR_CSBF_Msk                                 /*!< Clear Standby Flag                  */
+#define PWR_CR_PVDE_Pos        (4U)                                            
+#define PWR_CR_PVDE_Msk        (0x1UL << PWR_CR_PVDE_Pos)                       /*!< 0x00000010 */
+#define PWR_CR_PVDE            PWR_CR_PVDE_Msk                                 /*!< Power Voltage Detector Enable       */
+
+#define PWR_CR_PLS_Pos         (5U)                                            
+#define PWR_CR_PLS_Msk         (0x7UL << PWR_CR_PLS_Pos)                        /*!< 0x000000E0 */
+#define PWR_CR_PLS             PWR_CR_PLS_Msk                                  /*!< PLS[2:0] bits (PVD Level Selection) */
+#define PWR_CR_PLS_0           (0x1UL << PWR_CR_PLS_Pos)                        /*!< 0x00000020 */
+#define PWR_CR_PLS_1           (0x2UL << PWR_CR_PLS_Pos)                        /*!< 0x00000040 */
+#define PWR_CR_PLS_2           (0x4UL << PWR_CR_PLS_Pos)                        /*!< 0x00000080 */
+
+/*!< PVD level configuration */
+#define PWR_CR_PLS_LEV0        0x00000000U                                     /*!< PVD level 0 */
+#define PWR_CR_PLS_LEV1        0x00000020U                                     /*!< PVD level 1 */
+#define PWR_CR_PLS_LEV2        0x00000040U                                     /*!< PVD level 2 */
+#define PWR_CR_PLS_LEV3        0x00000060U                                     /*!< PVD level 3 */
+#define PWR_CR_PLS_LEV4        0x00000080U                                     /*!< PVD level 4 */
+#define PWR_CR_PLS_LEV5        0x000000A0U                                     /*!< PVD level 5 */
+#define PWR_CR_PLS_LEV6        0x000000C0U                                     /*!< PVD level 6 */
+#define PWR_CR_PLS_LEV7        0x000000E0U                                     /*!< PVD level 7 */
+#define PWR_CR_DBP_Pos         (8U)                                            
+#define PWR_CR_DBP_Msk         (0x1UL << PWR_CR_DBP_Pos)                        /*!< 0x00000100 */
+#define PWR_CR_DBP             PWR_CR_DBP_Msk                                  /*!< Disable Backup Domain write protection                     */
+#define PWR_CR_FPDS_Pos        (9U)                                            
+#define PWR_CR_FPDS_Msk        (0x1UL << PWR_CR_FPDS_Pos)                       /*!< 0x00000200 */
+#define PWR_CR_FPDS            PWR_CR_FPDS_Msk                                 /*!< Flash power down in Stop mode                              */
+#define PWR_CR_LPLVDS_Pos      (10U)                                           
+#define PWR_CR_LPLVDS_Msk      (0x1UL << PWR_CR_LPLVDS_Pos)                     /*!< 0x00000400 */
+#define PWR_CR_LPLVDS          PWR_CR_LPLVDS_Msk                               /*!< Low-Power Regulator Low Voltage Scaling in Stop mode       */
+#define PWR_CR_MRLVDS_Pos      (11U)                                           
+#define PWR_CR_MRLVDS_Msk      (0x1UL << PWR_CR_MRLVDS_Pos)                     /*!< 0x00000800 */
+#define PWR_CR_MRLVDS          PWR_CR_MRLVDS_Msk                               /*!< Main regulator Low Voltage Scaling in Stop mode            */
+#define PWR_CR_ADCDC1_Pos      (13U)                                           
+#define PWR_CR_ADCDC1_Msk      (0x1UL << PWR_CR_ADCDC1_Pos)                     /*!< 0x00002000 */
+#define PWR_CR_ADCDC1          PWR_CR_ADCDC1_Msk                               /*!< Refer to AN4073 on how to use this bit                     */ 
+#define PWR_CR_VOS_Pos         (14U)                                           
+#define PWR_CR_VOS_Msk         (0x3UL << PWR_CR_VOS_Pos)                        /*!< 0x0000C000 */
+#define PWR_CR_VOS             PWR_CR_VOS_Msk                                  /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
+#define PWR_CR_VOS_0           0x00004000U                                     /*!< Bit 0 */
+#define PWR_CR_VOS_1           0x00008000U                                     /*!< Bit 1 */
+#define PWR_CR_ODEN_Pos        (16U)                                           
+#define PWR_CR_ODEN_Msk        (0x1UL << PWR_CR_ODEN_Pos)                       /*!< 0x00010000 */
+#define PWR_CR_ODEN            PWR_CR_ODEN_Msk                                 /*!< Over Drive enable                   */
+#define PWR_CR_ODSWEN_Pos      (17U)                                           
+#define PWR_CR_ODSWEN_Msk      (0x1UL << PWR_CR_ODSWEN_Pos)                     /*!< 0x00020000 */
+#define PWR_CR_ODSWEN          PWR_CR_ODSWEN_Msk                               /*!< Over Drive switch enabled           */
+#define PWR_CR_UDEN_Pos        (18U)                                           
+#define PWR_CR_UDEN_Msk        (0x3UL << PWR_CR_UDEN_Pos)                       /*!< 0x000C0000 */
+#define PWR_CR_UDEN            PWR_CR_UDEN_Msk                                 /*!< Under Drive enable in stop mode     */
+#define PWR_CR_UDEN_0          (0x1UL << PWR_CR_UDEN_Pos)                       /*!< 0x00040000 */
+#define PWR_CR_UDEN_1          (0x2UL << PWR_CR_UDEN_Pos)                       /*!< 0x00080000 */
+
+/* Legacy define */
+#define  PWR_CR_PMODE                        PWR_CR_VOS
+#define  PWR_CR_LPUDS                        PWR_CR_LPLVDS     /*!< Low-Power Regulator in deepsleep under-drive mode        */
+#define  PWR_CR_MRUDS                        PWR_CR_MRLVDS     /*!< Main regulator in deepsleep under-drive mode             */
+
+/*******************  Bit definition for PWR_CSR register  ********************/
+#define PWR_CSR_WUF_Pos        (0U)                                            
+#define PWR_CSR_WUF_Msk        (0x1UL << PWR_CSR_WUF_Pos)                       /*!< 0x00000001 */
+#define PWR_CSR_WUF            PWR_CSR_WUF_Msk                                 /*!< Wakeup Flag                                      */
+#define PWR_CSR_SBF_Pos        (1U)                                            
+#define PWR_CSR_SBF_Msk        (0x1UL << PWR_CSR_SBF_Pos)                       /*!< 0x00000002 */
+#define PWR_CSR_SBF            PWR_CSR_SBF_Msk                                 /*!< Standby Flag                                     */
+#define PWR_CSR_PVDO_Pos       (2U)                                            
+#define PWR_CSR_PVDO_Msk       (0x1UL << PWR_CSR_PVDO_Pos)                      /*!< 0x00000004 */
+#define PWR_CSR_PVDO           PWR_CSR_PVDO_Msk                                /*!< PVD Output                                       */
+#define PWR_CSR_BRR_Pos        (3U)                                            
+#define PWR_CSR_BRR_Msk        (0x1UL << PWR_CSR_BRR_Pos)                       /*!< 0x00000008 */
+#define PWR_CSR_BRR            PWR_CSR_BRR_Msk                                 /*!< Backup regulator ready                           */
+#define PWR_CSR_EWUP_Pos       (8U)                                            
+#define PWR_CSR_EWUP_Msk       (0x1UL << PWR_CSR_EWUP_Pos)                      /*!< 0x00000100 */
+#define PWR_CSR_EWUP           PWR_CSR_EWUP_Msk                                /*!< Enable WKUP pin                                  */
+#define PWR_CSR_BRE_Pos        (9U)                                            
+#define PWR_CSR_BRE_Msk        (0x1UL << PWR_CSR_BRE_Pos)                       /*!< 0x00000200 */
+#define PWR_CSR_BRE            PWR_CSR_BRE_Msk                                 /*!< Backup regulator enable                          */
+#define PWR_CSR_VOSRDY_Pos     (14U)                                           
+#define PWR_CSR_VOSRDY_Msk     (0x1UL << PWR_CSR_VOSRDY_Pos)                    /*!< 0x00004000 */
+#define PWR_CSR_VOSRDY         PWR_CSR_VOSRDY_Msk                              /*!< Regulator voltage scaling output selection ready */
+#define PWR_CSR_ODRDY_Pos      (16U)                                           
+#define PWR_CSR_ODRDY_Msk      (0x1UL << PWR_CSR_ODRDY_Pos)                     /*!< 0x00010000 */
+#define PWR_CSR_ODRDY          PWR_CSR_ODRDY_Msk                               /*!< Over Drive generator ready                       */
+#define PWR_CSR_ODSWRDY_Pos    (17U)                                           
+#define PWR_CSR_ODSWRDY_Msk    (0x1UL << PWR_CSR_ODSWRDY_Pos)                   /*!< 0x00020000 */
+#define PWR_CSR_ODSWRDY        PWR_CSR_ODSWRDY_Msk                             /*!< Over Drive Switch ready                          */
+#define PWR_CSR_UDRDY_Pos      (18U)                                           
+#define PWR_CSR_UDRDY_Msk      (0x3UL << PWR_CSR_UDRDY_Pos)                     /*!< 0x000C0000 */
+#define PWR_CSR_UDRDY          PWR_CSR_UDRDY_Msk                               /*!< Under Drive ready                                */
+/* Legacy define */
+#define  PWR_CSR_UDSWRDY                     PWR_CSR_UDRDY
+
+/* Legacy define */
+#define  PWR_CSR_REGRDY                      PWR_CSR_VOSRDY
+
+/******************************************************************************/
+/*                                                                            */
+/*                                    QUADSPI                                 */
+/*                                                                            */
+/******************************************************************************/
+/*****************  Bit definition for QUADSPI_CR register  *******************/
+#define QUADSPI_CR_EN_Pos                (0U)                                  
+#define QUADSPI_CR_EN_Msk                (0x1UL << QUADSPI_CR_EN_Pos)           /*!< 0x00000001 */
+#define QUADSPI_CR_EN                    QUADSPI_CR_EN_Msk                     /*!< Enable                             */
+#define QUADSPI_CR_ABORT_Pos             (1U)                                  
+#define QUADSPI_CR_ABORT_Msk             (0x1UL << QUADSPI_CR_ABORT_Pos)        /*!< 0x00000002 */
+#define QUADSPI_CR_ABORT                 QUADSPI_CR_ABORT_Msk                  /*!< Abort request                      */
+#define QUADSPI_CR_DMAEN_Pos             (2U)                                  
+#define QUADSPI_CR_DMAEN_Msk             (0x1UL << QUADSPI_CR_DMAEN_Pos)        /*!< 0x00000004 */
+#define QUADSPI_CR_DMAEN                 QUADSPI_CR_DMAEN_Msk                  /*!< DMA Enable                         */
+#define QUADSPI_CR_TCEN_Pos              (3U)                                  
+#define QUADSPI_CR_TCEN_Msk              (0x1UL << QUADSPI_CR_TCEN_Pos)         /*!< 0x00000008 */
+#define QUADSPI_CR_TCEN                  QUADSPI_CR_TCEN_Msk                   /*!< Timeout Counter Enable             */
+#define QUADSPI_CR_SSHIFT_Pos            (4U)                                  
+#define QUADSPI_CR_SSHIFT_Msk            (0x1UL << QUADSPI_CR_SSHIFT_Pos)       /*!< 0x00000010 */
+#define QUADSPI_CR_SSHIFT                QUADSPI_CR_SSHIFT_Msk                 /*!< SSHIFT Sample Shift                */
+#define QUADSPI_CR_DFM_Pos               (6U)                                  
+#define QUADSPI_CR_DFM_Msk               (0x1UL << QUADSPI_CR_DFM_Pos)          /*!< 0x00000040 */
+#define QUADSPI_CR_DFM                   QUADSPI_CR_DFM_Msk                    /*!< Dual Flash Mode                    */
+#define QUADSPI_CR_FSEL_Pos              (7U)                                  
+#define QUADSPI_CR_FSEL_Msk              (0x1UL << QUADSPI_CR_FSEL_Pos)         /*!< 0x00000080 */
+#define QUADSPI_CR_FSEL                  QUADSPI_CR_FSEL_Msk                   /*!< Flash Select                       */
+#define QUADSPI_CR_FTHRES_Pos            (8U)                                  
+#define QUADSPI_CR_FTHRES_Msk            (0x1FUL << QUADSPI_CR_FTHRES_Pos)      /*!< 0x00001F00 */
+#define QUADSPI_CR_FTHRES                QUADSPI_CR_FTHRES_Msk                 /*!< FTHRES[3:0] FIFO Level             */
+#define QUADSPI_CR_FTHRES_0              (0x01UL << QUADSPI_CR_FTHRES_Pos)      /*!< 0x00000100 */
+#define QUADSPI_CR_FTHRES_1              (0x02UL << QUADSPI_CR_FTHRES_Pos)      /*!< 0x00000200 */
+#define QUADSPI_CR_FTHRES_2              (0x04UL << QUADSPI_CR_FTHRES_Pos)      /*!< 0x00000400 */
+#define QUADSPI_CR_FTHRES_3              (0x08UL << QUADSPI_CR_FTHRES_Pos)      /*!< 0x00000800 */
+#define QUADSPI_CR_FTHRES_4              (0x10UL << QUADSPI_CR_FTHRES_Pos)      /*!< 0x00001000 */
+#define QUADSPI_CR_TEIE_Pos              (16U)                                 
+#define QUADSPI_CR_TEIE_Msk              (0x1UL << QUADSPI_CR_TEIE_Pos)         /*!< 0x00010000 */
+#define QUADSPI_CR_TEIE                  QUADSPI_CR_TEIE_Msk                   /*!< Transfer Error Interrupt Enable    */
+#define QUADSPI_CR_TCIE_Pos              (17U)                                 
+#define QUADSPI_CR_TCIE_Msk              (0x1UL << QUADSPI_CR_TCIE_Pos)         /*!< 0x00020000 */
+#define QUADSPI_CR_TCIE                  QUADSPI_CR_TCIE_Msk                   /*!< Transfer Complete Interrupt Enable */
+#define QUADSPI_CR_FTIE_Pos              (18U)                                 
+#define QUADSPI_CR_FTIE_Msk              (0x1UL << QUADSPI_CR_FTIE_Pos)         /*!< 0x00040000 */
+#define QUADSPI_CR_FTIE                  QUADSPI_CR_FTIE_Msk                   /*!< FIFO Threshold Interrupt Enable    */
+#define QUADSPI_CR_SMIE_Pos              (19U)                                 
+#define QUADSPI_CR_SMIE_Msk              (0x1UL << QUADSPI_CR_SMIE_Pos)         /*!< 0x00080000 */
+#define QUADSPI_CR_SMIE                  QUADSPI_CR_SMIE_Msk                   /*!< Status Match Interrupt Enable      */
+#define QUADSPI_CR_TOIE_Pos              (20U)                                 
+#define QUADSPI_CR_TOIE_Msk              (0x1UL << QUADSPI_CR_TOIE_Pos)         /*!< 0x00100000 */
+#define QUADSPI_CR_TOIE                  QUADSPI_CR_TOIE_Msk                   /*!< TimeOut Interrupt Enable           */
+#define QUADSPI_CR_APMS_Pos              (22U)                                 
+#define QUADSPI_CR_APMS_Msk              (0x1UL << QUADSPI_CR_APMS_Pos)         /*!< 0x00400000 */
+#define QUADSPI_CR_APMS                  QUADSPI_CR_APMS_Msk                   /*!< Bit 1                              */
+#define QUADSPI_CR_PMM_Pos               (23U)                                 
+#define QUADSPI_CR_PMM_Msk               (0x1UL << QUADSPI_CR_PMM_Pos)          /*!< 0x00800000 */
+#define QUADSPI_CR_PMM                   QUADSPI_CR_PMM_Msk                    /*!< Polling Match Mode                 */
+#define QUADSPI_CR_PRESCALER_Pos         (24U)                                 
+#define QUADSPI_CR_PRESCALER_Msk         (0xFFUL << QUADSPI_CR_PRESCALER_Pos)   /*!< 0xFF000000 */
+#define QUADSPI_CR_PRESCALER             QUADSPI_CR_PRESCALER_Msk              /*!< PRESCALER[7:0] Clock prescaler     */
+#define QUADSPI_CR_PRESCALER_0           (0x01UL << QUADSPI_CR_PRESCALER_Pos)   /*!< 0x01000000 */
+#define QUADSPI_CR_PRESCALER_1           (0x02UL << QUADSPI_CR_PRESCALER_Pos)   /*!< 0x02000000 */
+#define QUADSPI_CR_PRESCALER_2           (0x04UL << QUADSPI_CR_PRESCALER_Pos)   /*!< 0x04000000 */
+#define QUADSPI_CR_PRESCALER_3           (0x08UL << QUADSPI_CR_PRESCALER_Pos)   /*!< 0x08000000 */
+#define QUADSPI_CR_PRESCALER_4           (0x10UL << QUADSPI_CR_PRESCALER_Pos)   /*!< 0x10000000 */
+#define QUADSPI_CR_PRESCALER_5           (0x20UL << QUADSPI_CR_PRESCALER_Pos)   /*!< 0x20000000 */
+#define QUADSPI_CR_PRESCALER_6           (0x40UL << QUADSPI_CR_PRESCALER_Pos)   /*!< 0x40000000 */
+#define QUADSPI_CR_PRESCALER_7           (0x80UL << QUADSPI_CR_PRESCALER_Pos)   /*!< 0x80000000 */
+
+/*****************  Bit definition for QUADSPI_DCR register  ******************/
+#define QUADSPI_DCR_CKMODE_Pos           (0U)                                  
+#define QUADSPI_DCR_CKMODE_Msk           (0x1UL << QUADSPI_DCR_CKMODE_Pos)      /*!< 0x00000001 */
+#define QUADSPI_DCR_CKMODE               QUADSPI_DCR_CKMODE_Msk                /*!< Mode 0 / Mode 3                 */
+#define QUADSPI_DCR_CSHT_Pos             (8U)                                  
+#define QUADSPI_DCR_CSHT_Msk             (0x7UL << QUADSPI_DCR_CSHT_Pos)        /*!< 0x00000700 */
+#define QUADSPI_DCR_CSHT                 QUADSPI_DCR_CSHT_Msk                  /*!< CSHT[2:0]: ChipSelect High Time */
+#define QUADSPI_DCR_CSHT_0               (0x1UL << QUADSPI_DCR_CSHT_Pos)        /*!< 0x00000100 */
+#define QUADSPI_DCR_CSHT_1               (0x2UL << QUADSPI_DCR_CSHT_Pos)        /*!< 0x00000200 */
+#define QUADSPI_DCR_CSHT_2               (0x4UL << QUADSPI_DCR_CSHT_Pos)        /*!< 0x00000400 */
+#define QUADSPI_DCR_FSIZE_Pos            (16U)                                 
+#define QUADSPI_DCR_FSIZE_Msk            (0x1FUL << QUADSPI_DCR_FSIZE_Pos)      /*!< 0x001F0000 */
+#define QUADSPI_DCR_FSIZE                QUADSPI_DCR_FSIZE_Msk                 /*!< FSIZE[4:0]: Flash Size          */
+#define QUADSPI_DCR_FSIZE_0              (0x01UL << QUADSPI_DCR_FSIZE_Pos)      /*!< 0x00010000 */
+#define QUADSPI_DCR_FSIZE_1              (0x02UL << QUADSPI_DCR_FSIZE_Pos)      /*!< 0x00020000 */
+#define QUADSPI_DCR_FSIZE_2              (0x04UL << QUADSPI_DCR_FSIZE_Pos)      /*!< 0x00040000 */
+#define QUADSPI_DCR_FSIZE_3              (0x08UL << QUADSPI_DCR_FSIZE_Pos)      /*!< 0x00080000 */
+#define QUADSPI_DCR_FSIZE_4              (0x10UL << QUADSPI_DCR_FSIZE_Pos)      /*!< 0x00100000 */
+
+/******************  Bit definition for QUADSPI_SR register  *******************/
+#define QUADSPI_SR_TEF_Pos               (0U)                                  
+#define QUADSPI_SR_TEF_Msk               (0x1UL << QUADSPI_SR_TEF_Pos)          /*!< 0x00000001 */
+#define QUADSPI_SR_TEF                   QUADSPI_SR_TEF_Msk                    /*!< Transfer Error Flag    */
+#define QUADSPI_SR_TCF_Pos               (1U)                                  
+#define QUADSPI_SR_TCF_Msk               (0x1UL << QUADSPI_SR_TCF_Pos)          /*!< 0x00000002 */
+#define QUADSPI_SR_TCF                   QUADSPI_SR_TCF_Msk                    /*!< Transfer Complete Flag */
+#define QUADSPI_SR_FTF_Pos               (2U)                                  
+#define QUADSPI_SR_FTF_Msk               (0x1UL << QUADSPI_SR_FTF_Pos)          /*!< 0x00000004 */
+#define QUADSPI_SR_FTF                   QUADSPI_SR_FTF_Msk                    /*!< FIFO Threshlod Flag    */
+#define QUADSPI_SR_SMF_Pos               (3U)                                  
+#define QUADSPI_SR_SMF_Msk               (0x1UL << QUADSPI_SR_SMF_Pos)          /*!< 0x00000008 */
+#define QUADSPI_SR_SMF                   QUADSPI_SR_SMF_Msk                    /*!< Status Match Flag      */
+#define QUADSPI_SR_TOF_Pos               (4U)                                  
+#define QUADSPI_SR_TOF_Msk               (0x1UL << QUADSPI_SR_TOF_Pos)          /*!< 0x00000010 */
+#define QUADSPI_SR_TOF                   QUADSPI_SR_TOF_Msk                    /*!< Timeout Flag           */
+#define QUADSPI_SR_BUSY_Pos              (5U)                                  
+#define QUADSPI_SR_BUSY_Msk              (0x1UL << QUADSPI_SR_BUSY_Pos)         /*!< 0x00000020 */
+#define QUADSPI_SR_BUSY                  QUADSPI_SR_BUSY_Msk                   /*!< Busy                   */
+#define QUADSPI_SR_FLEVEL_Pos            (8U)                                  
+#define QUADSPI_SR_FLEVEL_Msk            (0x3FUL << QUADSPI_SR_FLEVEL_Pos)      /*!< 0x00003F00 */
+#define QUADSPI_SR_FLEVEL                QUADSPI_SR_FLEVEL_Msk                 /*!< FIFO Threshlod Flag    */
+#define QUADSPI_SR_FLEVEL_0              (0x01UL << QUADSPI_SR_FLEVEL_Pos)      /*!< 0x00000100 */
+#define QUADSPI_SR_FLEVEL_1              (0x02UL << QUADSPI_SR_FLEVEL_Pos)      /*!< 0x00000200 */
+#define QUADSPI_SR_FLEVEL_2              (0x04UL << QUADSPI_SR_FLEVEL_Pos)      /*!< 0x00000400 */
+#define QUADSPI_SR_FLEVEL_3              (0x08UL << QUADSPI_SR_FLEVEL_Pos)      /*!< 0x00000800 */
+#define QUADSPI_SR_FLEVEL_4              (0x10UL << QUADSPI_SR_FLEVEL_Pos)      /*!< 0x00001000 */
+#define QUADSPI_SR_FLEVEL_5              (0x20UL << QUADSPI_SR_FLEVEL_Pos)      /*!< 0x00002000 */
+
+/******************  Bit definition for QUADSPI_FCR register  ******************/
+#define QUADSPI_FCR_CTEF_Pos             (0U)                                  
+#define QUADSPI_FCR_CTEF_Msk             (0x1UL << QUADSPI_FCR_CTEF_Pos)        /*!< 0x00000001 */
+#define QUADSPI_FCR_CTEF                 QUADSPI_FCR_CTEF_Msk                  /*!< Clear Transfer Error Flag    */
+#define QUADSPI_FCR_CTCF_Pos             (1U)                                  
+#define QUADSPI_FCR_CTCF_Msk             (0x1UL << QUADSPI_FCR_CTCF_Pos)        /*!< 0x00000002 */
+#define QUADSPI_FCR_CTCF                 QUADSPI_FCR_CTCF_Msk                  /*!< Clear Transfer Complete Flag */
+#define QUADSPI_FCR_CSMF_Pos             (3U)                                  
+#define QUADSPI_FCR_CSMF_Msk             (0x1UL << QUADSPI_FCR_CSMF_Pos)        /*!< 0x00000008 */
+#define QUADSPI_FCR_CSMF                 QUADSPI_FCR_CSMF_Msk                  /*!< Clear Status Match Flag      */
+#define QUADSPI_FCR_CTOF_Pos             (4U)                                  
+#define QUADSPI_FCR_CTOF_Msk             (0x1UL << QUADSPI_FCR_CTOF_Pos)        /*!< 0x00000010 */
+#define QUADSPI_FCR_CTOF                 QUADSPI_FCR_CTOF_Msk                  /*!< Clear Timeout Flag           */
+
+/******************  Bit definition for QUADSPI_DLR register  ******************/
+#define QUADSPI_DLR_DL_Pos               (0U)                                  
+#define QUADSPI_DLR_DL_Msk               (0xFFFFFFFFUL << QUADSPI_DLR_DL_Pos)   /*!< 0xFFFFFFFF */
+#define QUADSPI_DLR_DL                   QUADSPI_DLR_DL_Msk                    /*!< DL[31:0]: Data Length */
+
+/******************  Bit definition for QUADSPI_CCR register  ******************/
+#define QUADSPI_CCR_INSTRUCTION_Pos      (0U)                                  
+#define QUADSPI_CCR_INSTRUCTION_Msk      (0xFFUL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x000000FF */
+#define QUADSPI_CCR_INSTRUCTION          QUADSPI_CCR_INSTRUCTION_Msk           /*!< INSTRUCTION[7:0]: Instruction         */
+#define QUADSPI_CCR_INSTRUCTION_0        (0x01UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000001 */
+#define QUADSPI_CCR_INSTRUCTION_1        (0x02UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000002 */
+#define QUADSPI_CCR_INSTRUCTION_2        (0x04UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000004 */
+#define QUADSPI_CCR_INSTRUCTION_3        (0x08UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000008 */
+#define QUADSPI_CCR_INSTRUCTION_4        (0x10UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000010 */
+#define QUADSPI_CCR_INSTRUCTION_5        (0x20UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000020 */
+#define QUADSPI_CCR_INSTRUCTION_6        (0x40UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000040 */
+#define QUADSPI_CCR_INSTRUCTION_7        (0x80UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000080 */
+#define QUADSPI_CCR_IMODE_Pos            (8U)                                  
+#define QUADSPI_CCR_IMODE_Msk            (0x3UL << QUADSPI_CCR_IMODE_Pos)       /*!< 0x00000300 */
+#define QUADSPI_CCR_IMODE                QUADSPI_CCR_IMODE_Msk                 /*!< IMODE[1:0]: Instruction Mode          */
+#define QUADSPI_CCR_IMODE_0              (0x1UL << QUADSPI_CCR_IMODE_Pos)       /*!< 0x00000100 */
+#define QUADSPI_CCR_IMODE_1              (0x2UL << QUADSPI_CCR_IMODE_Pos)       /*!< 0x00000200 */
+#define QUADSPI_CCR_ADMODE_Pos           (10U)                                 
+#define QUADSPI_CCR_ADMODE_Msk           (0x3UL << QUADSPI_CCR_ADMODE_Pos)      /*!< 0x00000C00 */
+#define QUADSPI_CCR_ADMODE               QUADSPI_CCR_ADMODE_Msk                /*!< ADMODE[1:0]: Address Mode             */
+#define QUADSPI_CCR_ADMODE_0             (0x1UL << QUADSPI_CCR_ADMODE_Pos)      /*!< 0x00000400 */
+#define QUADSPI_CCR_ADMODE_1             (0x2UL << QUADSPI_CCR_ADMODE_Pos)      /*!< 0x00000800 */
+#define QUADSPI_CCR_ADSIZE_Pos           (12U)                                 
+#define QUADSPI_CCR_ADSIZE_Msk           (0x3UL << QUADSPI_CCR_ADSIZE_Pos)      /*!< 0x00003000 */
+#define QUADSPI_CCR_ADSIZE               QUADSPI_CCR_ADSIZE_Msk                /*!< ADSIZE[1:0]: Address Size             */
+#define QUADSPI_CCR_ADSIZE_0             (0x1UL << QUADSPI_CCR_ADSIZE_Pos)      /*!< 0x00001000 */
+#define QUADSPI_CCR_ADSIZE_1             (0x2UL << QUADSPI_CCR_ADSIZE_Pos)      /*!< 0x00002000 */
+#define QUADSPI_CCR_ABMODE_Pos           (14U)                                 
+#define QUADSPI_CCR_ABMODE_Msk           (0x3UL << QUADSPI_CCR_ABMODE_Pos)      /*!< 0x0000C000 */
+#define QUADSPI_CCR_ABMODE               QUADSPI_CCR_ABMODE_Msk                /*!< ABMODE[1:0]: Alternate Bytes Mode     */
+#define QUADSPI_CCR_ABMODE_0             (0x1UL << QUADSPI_CCR_ABMODE_Pos)      /*!< 0x00004000 */
+#define QUADSPI_CCR_ABMODE_1             (0x2UL << QUADSPI_CCR_ABMODE_Pos)      /*!< 0x00008000 */
+#define QUADSPI_CCR_ABSIZE_Pos           (16U)                                 
+#define QUADSPI_CCR_ABSIZE_Msk           (0x3UL << QUADSPI_CCR_ABSIZE_Pos)      /*!< 0x00030000 */
+#define QUADSPI_CCR_ABSIZE               QUADSPI_CCR_ABSIZE_Msk                /*!< ABSIZE[1:0]: Instruction Mode         */
+#define QUADSPI_CCR_ABSIZE_0             (0x1UL << QUADSPI_CCR_ABSIZE_Pos)      /*!< 0x00010000 */
+#define QUADSPI_CCR_ABSIZE_1             (0x2UL << QUADSPI_CCR_ABSIZE_Pos)      /*!< 0x00020000 */
+#define QUADSPI_CCR_DCYC_Pos             (18U)                                 
+#define QUADSPI_CCR_DCYC_Msk             (0x1FUL << QUADSPI_CCR_DCYC_Pos)       /*!< 0x007C0000 */
+#define QUADSPI_CCR_DCYC                 QUADSPI_CCR_DCYC_Msk                  /*!< DCYC[4:0]: Dummy Cycles               */
+#define QUADSPI_CCR_DCYC_0               (0x01UL << QUADSPI_CCR_DCYC_Pos)       /*!< 0x00040000 */
+#define QUADSPI_CCR_DCYC_1               (0x02UL << QUADSPI_CCR_DCYC_Pos)       /*!< 0x00080000 */
+#define QUADSPI_CCR_DCYC_2               (0x04UL << QUADSPI_CCR_DCYC_Pos)       /*!< 0x00100000 */
+#define QUADSPI_CCR_DCYC_3               (0x08UL << QUADSPI_CCR_DCYC_Pos)       /*!< 0x00200000 */
+#define QUADSPI_CCR_DCYC_4               (0x10UL << QUADSPI_CCR_DCYC_Pos)       /*!< 0x00400000 */
+#define QUADSPI_CCR_DMODE_Pos            (24U)                                 
+#define QUADSPI_CCR_DMODE_Msk            (0x3UL << QUADSPI_CCR_DMODE_Pos)       /*!< 0x03000000 */
+#define QUADSPI_CCR_DMODE                QUADSPI_CCR_DMODE_Msk                 /*!< DMODE[1:0]: Data Mode                 */
+#define QUADSPI_CCR_DMODE_0              (0x1UL << QUADSPI_CCR_DMODE_Pos)       /*!< 0x01000000 */
+#define QUADSPI_CCR_DMODE_1              (0x2UL << QUADSPI_CCR_DMODE_Pos)       /*!< 0x02000000 */
+#define QUADSPI_CCR_FMODE_Pos            (26U)                                 
+#define QUADSPI_CCR_FMODE_Msk            (0x3UL << QUADSPI_CCR_FMODE_Pos)       /*!< 0x0C000000 */
+#define QUADSPI_CCR_FMODE                QUADSPI_CCR_FMODE_Msk                 /*!< FMODE[1:0]: Functional Mode           */
+#define QUADSPI_CCR_FMODE_0              (0x1UL << QUADSPI_CCR_FMODE_Pos)       /*!< 0x04000000 */
+#define QUADSPI_CCR_FMODE_1              (0x2UL << QUADSPI_CCR_FMODE_Pos)       /*!< 0x08000000 */
+#define QUADSPI_CCR_SIOO_Pos             (28U)                                 
+#define QUADSPI_CCR_SIOO_Msk             (0x1UL << QUADSPI_CCR_SIOO_Pos)        /*!< 0x10000000 */
+#define QUADSPI_CCR_SIOO                 QUADSPI_CCR_SIOO_Msk                  /*!< SIOO: Send Instruction Only Once Mode */
+#define QUADSPI_CCR_DHHC_Pos             (30U)                                 
+#define QUADSPI_CCR_DHHC_Msk             (0x1UL << QUADSPI_CCR_DHHC_Pos)        /*!< 0x40000000 */
+#define QUADSPI_CCR_DHHC                 QUADSPI_CCR_DHHC_Msk                  /*!< DHHC: Delay Half Hclk Cycle           */
+#define QUADSPI_CCR_DDRM_Pos             (31U)                                 
+#define QUADSPI_CCR_DDRM_Msk             (0x1UL << QUADSPI_CCR_DDRM_Pos)        /*!< 0x80000000 */
+#define QUADSPI_CCR_DDRM                 QUADSPI_CCR_DDRM_Msk                  /*!< DDRM: Double Data Rate Mode           */
+/******************  Bit definition for QUADSPI_AR register  *******************/
+#define QUADSPI_AR_ADDRESS_Pos           (0U)                                  
+#define QUADSPI_AR_ADDRESS_Msk           (0xFFFFFFFFUL << QUADSPI_AR_ADDRESS_Pos) /*!< 0xFFFFFFFF */
+#define QUADSPI_AR_ADDRESS               QUADSPI_AR_ADDRESS_Msk                /*!< ADDRESS[31:0]: Address                */
+
+/******************  Bit definition for QUADSPI_ABR register  ******************/
+#define QUADSPI_ABR_ALTERNATE_Pos        (0U)                                  
+#define QUADSPI_ABR_ALTERNATE_Msk        (0xFFFFFFFFUL << QUADSPI_ABR_ALTERNATE_Pos) /*!< 0xFFFFFFFF */
+#define QUADSPI_ABR_ALTERNATE            QUADSPI_ABR_ALTERNATE_Msk             /*!< ALTERNATE[31:0]: Alternate Bytes      */
+
+/******************  Bit definition for QUADSPI_DR register  *******************/
+#define QUADSPI_DR_DATA_Pos              (0U)                                  
+#define QUADSPI_DR_DATA_Msk              (0xFFFFFFFFUL << QUADSPI_DR_DATA_Pos)  /*!< 0xFFFFFFFF */
+#define QUADSPI_DR_DATA                  QUADSPI_DR_DATA_Msk                   /*!< DATA[31:0]: Data                      */
+
+/******************  Bit definition for QUADSPI_PSMKR register  ****************/
+#define QUADSPI_PSMKR_MASK_Pos           (0U)                                  
+#define QUADSPI_PSMKR_MASK_Msk           (0xFFFFFFFFUL << QUADSPI_PSMKR_MASK_Pos) /*!< 0xFFFFFFFF */
+#define QUADSPI_PSMKR_MASK               QUADSPI_PSMKR_MASK_Msk                /*!< MASK[31:0]: Status Mask               */
+
+/******************  Bit definition for QUADSPI_PSMAR register  ****************/
+#define QUADSPI_PSMAR_MATCH_Pos          (0U)                                  
+#define QUADSPI_PSMAR_MATCH_Msk          (0xFFFFFFFFUL << QUADSPI_PSMAR_MATCH_Pos) /*!< 0xFFFFFFFF */
+#define QUADSPI_PSMAR_MATCH              QUADSPI_PSMAR_MATCH_Msk               /*!< MATCH[31:0]: Status Match             */
+
+/******************  Bit definition for QUADSPI_PIR register  *****************/
+#define QUADSPI_PIR_INTERVAL_Pos         (0U)                                  
+#define QUADSPI_PIR_INTERVAL_Msk         (0xFFFFUL << QUADSPI_PIR_INTERVAL_Pos) /*!< 0x0000FFFF */
+#define QUADSPI_PIR_INTERVAL             QUADSPI_PIR_INTERVAL_Msk              /*!< INTERVAL[15:0]: Polling Interval      */
+
+/******************  Bit definition for QUADSPI_LPTR register  *****************/
+#define QUADSPI_LPTR_TIMEOUT_Pos         (0U)                                  
+#define QUADSPI_LPTR_TIMEOUT_Msk         (0xFFFFUL << QUADSPI_LPTR_TIMEOUT_Pos) /*!< 0x0000FFFF */
+#define QUADSPI_LPTR_TIMEOUT             QUADSPI_LPTR_TIMEOUT_Msk              /*!< TIMEOUT[15:0]: Timeout period         */
+
+/******************************************************************************/
+/*                                                                            */
+/*                         Reset and Clock Control                            */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bit definition for RCC_CR register  ********************/
+#define RCC_CR_HSION_Pos                   (0U)                                
+#define RCC_CR_HSION_Msk                   (0x1UL << RCC_CR_HSION_Pos)          /*!< 0x00000001 */
+#define RCC_CR_HSION                       RCC_CR_HSION_Msk                    
+#define RCC_CR_HSIRDY_Pos                  (1U)                                
+#define RCC_CR_HSIRDY_Msk                  (0x1UL << RCC_CR_HSIRDY_Pos)         /*!< 0x00000002 */
+#define RCC_CR_HSIRDY                      RCC_CR_HSIRDY_Msk                   
+
+#define RCC_CR_HSITRIM_Pos                 (3U)                                
+#define RCC_CR_HSITRIM_Msk                 (0x1FUL << RCC_CR_HSITRIM_Pos)       /*!< 0x000000F8 */
+#define RCC_CR_HSITRIM                     RCC_CR_HSITRIM_Msk                  
+#define RCC_CR_HSITRIM_0                   (0x01UL << RCC_CR_HSITRIM_Pos)       /*!< 0x00000008 */
+#define RCC_CR_HSITRIM_1                   (0x02UL << RCC_CR_HSITRIM_Pos)       /*!< 0x00000010 */
+#define RCC_CR_HSITRIM_2                   (0x04UL << RCC_CR_HSITRIM_Pos)       /*!< 0x00000020 */
+#define RCC_CR_HSITRIM_3                   (0x08UL << RCC_CR_HSITRIM_Pos)       /*!< 0x00000040 */
+#define RCC_CR_HSITRIM_4                   (0x10UL << RCC_CR_HSITRIM_Pos)       /*!< 0x00000080 */
+
+#define RCC_CR_HSICAL_Pos                  (8U)                                
+#define RCC_CR_HSICAL_Msk                  (0xFFUL << RCC_CR_HSICAL_Pos)        /*!< 0x0000FF00 */
+#define RCC_CR_HSICAL                      RCC_CR_HSICAL_Msk                   
+#define RCC_CR_HSICAL_0                    (0x01UL << RCC_CR_HSICAL_Pos)        /*!< 0x00000100 */
+#define RCC_CR_HSICAL_1                    (0x02UL << RCC_CR_HSICAL_Pos)        /*!< 0x00000200 */
+#define RCC_CR_HSICAL_2                    (0x04UL << RCC_CR_HSICAL_Pos)        /*!< 0x00000400 */
+#define RCC_CR_HSICAL_3                    (0x08UL << RCC_CR_HSICAL_Pos)        /*!< 0x00000800 */
+#define RCC_CR_HSICAL_4                    (0x10UL << RCC_CR_HSICAL_Pos)        /*!< 0x00001000 */
+#define RCC_CR_HSICAL_5                    (0x20UL << RCC_CR_HSICAL_Pos)        /*!< 0x00002000 */
+#define RCC_CR_HSICAL_6                    (0x40UL << RCC_CR_HSICAL_Pos)        /*!< 0x00004000 */
+#define RCC_CR_HSICAL_7                    (0x80UL << RCC_CR_HSICAL_Pos)        /*!< 0x00008000 */
+
+#define RCC_CR_HSEON_Pos                   (16U)                               
+#define RCC_CR_HSEON_Msk                   (0x1UL << RCC_CR_HSEON_Pos)          /*!< 0x00010000 */
+#define RCC_CR_HSEON                       RCC_CR_HSEON_Msk                    
+#define RCC_CR_HSERDY_Pos                  (17U)                               
+#define RCC_CR_HSERDY_Msk                  (0x1UL << RCC_CR_HSERDY_Pos)         /*!< 0x00020000 */
+#define RCC_CR_HSERDY                      RCC_CR_HSERDY_Msk                   
+#define RCC_CR_HSEBYP_Pos                  (18U)                               
+#define RCC_CR_HSEBYP_Msk                  (0x1UL << RCC_CR_HSEBYP_Pos)         /*!< 0x00040000 */
+#define RCC_CR_HSEBYP                      RCC_CR_HSEBYP_Msk                   
+#define RCC_CR_CSSON_Pos                   (19U)                               
+#define RCC_CR_CSSON_Msk                   (0x1UL << RCC_CR_CSSON_Pos)          /*!< 0x00080000 */
+#define RCC_CR_CSSON                       RCC_CR_CSSON_Msk                    
+#define RCC_CR_PLLON_Pos                   (24U)                               
+#define RCC_CR_PLLON_Msk                   (0x1UL << RCC_CR_PLLON_Pos)          /*!< 0x01000000 */
+#define RCC_CR_PLLON                       RCC_CR_PLLON_Msk                    
+#define RCC_CR_PLLRDY_Pos                  (25U)                               
+#define RCC_CR_PLLRDY_Msk                  (0x1UL << RCC_CR_PLLRDY_Pos)         /*!< 0x02000000 */
+#define RCC_CR_PLLRDY                      RCC_CR_PLLRDY_Msk                   
+/*
+ * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
+ */
+#define RCC_PLLI2S_SUPPORT                                                     /*!< Support PLLI2S oscillator */
+
+#define RCC_CR_PLLI2SON_Pos                (26U)                               
+#define RCC_CR_PLLI2SON_Msk                (0x1UL << RCC_CR_PLLI2SON_Pos)       /*!< 0x04000000 */
+#define RCC_CR_PLLI2SON                    RCC_CR_PLLI2SON_Msk                 
+#define RCC_CR_PLLI2SRDY_Pos               (27U)                               
+#define RCC_CR_PLLI2SRDY_Msk               (0x1UL << RCC_CR_PLLI2SRDY_Pos)      /*!< 0x08000000 */
+#define RCC_CR_PLLI2SRDY                   RCC_CR_PLLI2SRDY_Msk                
+/*
+ * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
+ */
+#define RCC_PLLSAI_SUPPORT                                                     /*!< Support PLLSAI oscillator */
+
+#define RCC_CR_PLLSAION_Pos                (28U)                               
+#define RCC_CR_PLLSAION_Msk                (0x1UL << RCC_CR_PLLSAION_Pos)       /*!< 0x10000000 */
+#define RCC_CR_PLLSAION                    RCC_CR_PLLSAION_Msk                 
+#define RCC_CR_PLLSAIRDY_Pos               (29U)                               
+#define RCC_CR_PLLSAIRDY_Msk               (0x1UL << RCC_CR_PLLSAIRDY_Pos)      /*!< 0x20000000 */
+#define RCC_CR_PLLSAIRDY                   RCC_CR_PLLSAIRDY_Msk                
+
+/********************  Bit definition for RCC_PLLCFGR register  ***************/
+#define RCC_PLLCFGR_PLLM_Pos               (0U)                                
+#define RCC_PLLCFGR_PLLM_Msk               (0x3FUL << RCC_PLLCFGR_PLLM_Pos)     /*!< 0x0000003F */
+#define RCC_PLLCFGR_PLLM                   RCC_PLLCFGR_PLLM_Msk                
+#define RCC_PLLCFGR_PLLM_0                 (0x01UL << RCC_PLLCFGR_PLLM_Pos)     /*!< 0x00000001 */
+#define RCC_PLLCFGR_PLLM_1                 (0x02UL << RCC_PLLCFGR_PLLM_Pos)     /*!< 0x00000002 */
+#define RCC_PLLCFGR_PLLM_2                 (0x04UL << RCC_PLLCFGR_PLLM_Pos)     /*!< 0x00000004 */
+#define RCC_PLLCFGR_PLLM_3                 (0x08UL << RCC_PLLCFGR_PLLM_Pos)     /*!< 0x00000008 */
+#define RCC_PLLCFGR_PLLM_4                 (0x10UL << RCC_PLLCFGR_PLLM_Pos)     /*!< 0x00000010 */
+#define RCC_PLLCFGR_PLLM_5                 (0x20UL << RCC_PLLCFGR_PLLM_Pos)     /*!< 0x00000020 */
+
+#define RCC_PLLCFGR_PLLN_Pos               (6U)                                
+#define RCC_PLLCFGR_PLLN_Msk               (0x1FFUL << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00007FC0 */
+#define RCC_PLLCFGR_PLLN                   RCC_PLLCFGR_PLLN_Msk                
+#define RCC_PLLCFGR_PLLN_0                 (0x001UL << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00000040 */
+#define RCC_PLLCFGR_PLLN_1                 (0x002UL << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00000080 */
+#define RCC_PLLCFGR_PLLN_2                 (0x004UL << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00000100 */
+#define RCC_PLLCFGR_PLLN_3                 (0x008UL << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00000200 */
+#define RCC_PLLCFGR_PLLN_4                 (0x010UL << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00000400 */
+#define RCC_PLLCFGR_PLLN_5                 (0x020UL << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00000800 */
+#define RCC_PLLCFGR_PLLN_6                 (0x040UL << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00001000 */
+#define RCC_PLLCFGR_PLLN_7                 (0x080UL << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00002000 */
+#define RCC_PLLCFGR_PLLN_8                 (0x100UL << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00004000 */
+
+#define RCC_PLLCFGR_PLLP_Pos               (16U)                               
+#define RCC_PLLCFGR_PLLP_Msk               (0x3UL << RCC_PLLCFGR_PLLP_Pos)      /*!< 0x00030000 */
+#define RCC_PLLCFGR_PLLP                   RCC_PLLCFGR_PLLP_Msk                
+#define RCC_PLLCFGR_PLLP_0                 (0x1UL << RCC_PLLCFGR_PLLP_Pos)      /*!< 0x00010000 */
+#define RCC_PLLCFGR_PLLP_1                 (0x2UL << RCC_PLLCFGR_PLLP_Pos)      /*!< 0x00020000 */
+
+#define RCC_PLLCFGR_PLLSRC_Pos             (22U)                               
+#define RCC_PLLCFGR_PLLSRC_Msk             (0x1UL << RCC_PLLCFGR_PLLSRC_Pos)    /*!< 0x00400000 */
+#define RCC_PLLCFGR_PLLSRC                 RCC_PLLCFGR_PLLSRC_Msk              
+#define RCC_PLLCFGR_PLLSRC_HSE_Pos         (22U)                               
+#define RCC_PLLCFGR_PLLSRC_HSE_Msk         (0x1UL << RCC_PLLCFGR_PLLSRC_HSE_Pos) /*!< 0x00400000 */
+#define RCC_PLLCFGR_PLLSRC_HSE             RCC_PLLCFGR_PLLSRC_HSE_Msk          
+#define RCC_PLLCFGR_PLLSRC_HSI             0x00000000U                         
+
+#define RCC_PLLCFGR_PLLQ_Pos               (24U)                               
+#define RCC_PLLCFGR_PLLQ_Msk               (0xFUL << RCC_PLLCFGR_PLLQ_Pos)      /*!< 0x0F000000 */
+#define RCC_PLLCFGR_PLLQ                   RCC_PLLCFGR_PLLQ_Msk                
+#define RCC_PLLCFGR_PLLQ_0                 (0x1UL << RCC_PLLCFGR_PLLQ_Pos)      /*!< 0x01000000 */
+#define RCC_PLLCFGR_PLLQ_1                 (0x2UL << RCC_PLLCFGR_PLLQ_Pos)      /*!< 0x02000000 */
+#define RCC_PLLCFGR_PLLQ_2                 (0x4UL << RCC_PLLCFGR_PLLQ_Pos)      /*!< 0x04000000 */
+#define RCC_PLLCFGR_PLLQ_3                 (0x8UL << RCC_PLLCFGR_PLLQ_Pos)      /*!< 0x08000000 */
+
+#define RCC_PLLCFGR_PLLR_Pos               (28U)                               
+#define RCC_PLLCFGR_PLLR_Msk               (0x7UL << RCC_PLLCFGR_PLLR_Pos)      /*!< 0x70000000 */
+#define RCC_PLLCFGR_PLLR                   RCC_PLLCFGR_PLLR_Msk                
+#define RCC_PLLCFGR_PLLR_0                 (0x1UL << RCC_PLLCFGR_PLLR_Pos)      /*!< 0x10000000 */
+#define RCC_PLLCFGR_PLLR_1                 (0x2UL << RCC_PLLCFGR_PLLR_Pos)      /*!< 0x20000000 */
+#define RCC_PLLCFGR_PLLR_2                 (0x4UL << RCC_PLLCFGR_PLLR_Pos)      /*!< 0x40000000 */
+
+/********************  Bit definition for RCC_CFGR register  ******************/
+/*!< SW configuration */
+#define RCC_CFGR_SW_Pos                    (0U)                                
+#define RCC_CFGR_SW_Msk                    (0x3UL << RCC_CFGR_SW_Pos)           /*!< 0x00000003 */
+#define RCC_CFGR_SW                        RCC_CFGR_SW_Msk                     /*!< SW[1:0] bits (System clock Switch) */
+#define RCC_CFGR_SW_0                      (0x1UL << RCC_CFGR_SW_Pos)           /*!< 0x00000001 */
+#define RCC_CFGR_SW_1                      (0x2UL << RCC_CFGR_SW_Pos)           /*!< 0x00000002 */
+
+#define RCC_CFGR_SW_HSI                    0x00000000U                         /*!< HSI selected as system clock */
+#define RCC_CFGR_SW_HSE                    0x00000001U                         /*!< HSE selected as system clock */
+#define RCC_CFGR_SW_PLL                    0x00000002U                         /*!< PLL selected as system clock */
+
+/*!< SWS configuration */
+#define RCC_CFGR_SWS_Pos                   (2U)                                
+#define RCC_CFGR_SWS_Msk                   (0x3UL << RCC_CFGR_SWS_Pos)          /*!< 0x0000000C */
+#define RCC_CFGR_SWS                       RCC_CFGR_SWS_Msk                    /*!< SWS[1:0] bits (System Clock Switch Status) */
+#define RCC_CFGR_SWS_0                     (0x1UL << RCC_CFGR_SWS_Pos)          /*!< 0x00000004 */
+#define RCC_CFGR_SWS_1                     (0x2UL << RCC_CFGR_SWS_Pos)          /*!< 0x00000008 */
+
+#define RCC_CFGR_SWS_HSI                   0x00000000U                         /*!< HSI oscillator used as system clock        */
+#define RCC_CFGR_SWS_HSE                   0x00000004U                         /*!< HSE oscillator used as system clock        */
+#define RCC_CFGR_SWS_PLL                   0x00000008U                         /*!< PLL used as system clock                   */
+
+/*!< HPRE configuration */
+#define RCC_CFGR_HPRE_Pos                  (4U)                                
+#define RCC_CFGR_HPRE_Msk                  (0xFUL << RCC_CFGR_HPRE_Pos)         /*!< 0x000000F0 */
+#define RCC_CFGR_HPRE                      RCC_CFGR_HPRE_Msk                   /*!< HPRE[3:0] bits (AHB prescaler) */
+#define RCC_CFGR_HPRE_0                    (0x1UL << RCC_CFGR_HPRE_Pos)         /*!< 0x00000010 */
+#define RCC_CFGR_HPRE_1                    (0x2UL << RCC_CFGR_HPRE_Pos)         /*!< 0x00000020 */
+#define RCC_CFGR_HPRE_2                    (0x4UL << RCC_CFGR_HPRE_Pos)         /*!< 0x00000040 */
+#define RCC_CFGR_HPRE_3                    (0x8UL << RCC_CFGR_HPRE_Pos)         /*!< 0x00000080 */
+
+#define RCC_CFGR_HPRE_DIV1                 0x00000000U                         /*!< SYSCLK not divided    */
+#define RCC_CFGR_HPRE_DIV2                 0x00000080U                         /*!< SYSCLK divided by 2   */
+#define RCC_CFGR_HPRE_DIV4                 0x00000090U                         /*!< SYSCLK divided by 4   */
+#define RCC_CFGR_HPRE_DIV8                 0x000000A0U                         /*!< SYSCLK divided by 8   */
+#define RCC_CFGR_HPRE_DIV16                0x000000B0U                         /*!< SYSCLK divided by 16  */
+#define RCC_CFGR_HPRE_DIV64                0x000000C0U                         /*!< SYSCLK divided by 64  */
+#define RCC_CFGR_HPRE_DIV128               0x000000D0U                         /*!< SYSCLK divided by 128 */
+#define RCC_CFGR_HPRE_DIV256               0x000000E0U                         /*!< SYSCLK divided by 256 */
+#define RCC_CFGR_HPRE_DIV512               0x000000F0U                         /*!< SYSCLK divided by 512 */
+
+/*!< PPRE1 configuration */
+#define RCC_CFGR_PPRE1_Pos                 (10U)                               
+#define RCC_CFGR_PPRE1_Msk                 (0x7UL << RCC_CFGR_PPRE1_Pos)        /*!< 0x00001C00 */
+#define RCC_CFGR_PPRE1                     RCC_CFGR_PPRE1_Msk                  /*!< PRE1[2:0] bits (APB1 prescaler) */
+#define RCC_CFGR_PPRE1_0                   (0x1UL << RCC_CFGR_PPRE1_Pos)        /*!< 0x00000400 */
+#define RCC_CFGR_PPRE1_1                   (0x2UL << RCC_CFGR_PPRE1_Pos)        /*!< 0x00000800 */
+#define RCC_CFGR_PPRE1_2                   (0x4UL << RCC_CFGR_PPRE1_Pos)        /*!< 0x00001000 */
+
+#define RCC_CFGR_PPRE1_DIV1                0x00000000U                         /*!< HCLK not divided   */
+#define RCC_CFGR_PPRE1_DIV2                0x00001000U                         /*!< HCLK divided by 2  */
+#define RCC_CFGR_PPRE1_DIV4                0x00001400U                         /*!< HCLK divided by 4  */
+#define RCC_CFGR_PPRE1_DIV8                0x00001800U                         /*!< HCLK divided by 8  */
+#define RCC_CFGR_PPRE1_DIV16               0x00001C00U                         /*!< HCLK divided by 16 */
+
+/*!< PPRE2 configuration */
+#define RCC_CFGR_PPRE2_Pos                 (13U)                               
+#define RCC_CFGR_PPRE2_Msk                 (0x7UL << RCC_CFGR_PPRE2_Pos)        /*!< 0x0000E000 */
+#define RCC_CFGR_PPRE2                     RCC_CFGR_PPRE2_Msk                  /*!< PRE2[2:0] bits (APB2 prescaler) */
+#define RCC_CFGR_PPRE2_0                   (0x1UL << RCC_CFGR_PPRE2_Pos)        /*!< 0x00002000 */
+#define RCC_CFGR_PPRE2_1                   (0x2UL << RCC_CFGR_PPRE2_Pos)        /*!< 0x00004000 */
+#define RCC_CFGR_PPRE2_2                   (0x4UL << RCC_CFGR_PPRE2_Pos)        /*!< 0x00008000 */
+
+#define RCC_CFGR_PPRE2_DIV1                0x00000000U                         /*!< HCLK not divided   */
+#define RCC_CFGR_PPRE2_DIV2                0x00008000U                         /*!< HCLK divided by 2  */
+#define RCC_CFGR_PPRE2_DIV4                0x0000A000U                         /*!< HCLK divided by 4  */
+#define RCC_CFGR_PPRE2_DIV8                0x0000C000U                         /*!< HCLK divided by 8  */
+#define RCC_CFGR_PPRE2_DIV16               0x0000E000U                         /*!< HCLK divided by 16 */
+
+/*!< RTCPRE configuration */
+#define RCC_CFGR_RTCPRE_Pos                (16U)                               
+#define RCC_CFGR_RTCPRE_Msk                (0x1FUL << RCC_CFGR_RTCPRE_Pos)      /*!< 0x001F0000 */
+#define RCC_CFGR_RTCPRE                    RCC_CFGR_RTCPRE_Msk                 
+#define RCC_CFGR_RTCPRE_0                  (0x01UL << RCC_CFGR_RTCPRE_Pos)      /*!< 0x00010000 */
+#define RCC_CFGR_RTCPRE_1                  (0x02UL << RCC_CFGR_RTCPRE_Pos)      /*!< 0x00020000 */
+#define RCC_CFGR_RTCPRE_2                  (0x04UL << RCC_CFGR_RTCPRE_Pos)      /*!< 0x00040000 */
+#define RCC_CFGR_RTCPRE_3                  (0x08UL << RCC_CFGR_RTCPRE_Pos)      /*!< 0x00080000 */
+#define RCC_CFGR_RTCPRE_4                  (0x10UL << RCC_CFGR_RTCPRE_Pos)      /*!< 0x00100000 */
+
+/*!< MCO1 configuration */
+#define RCC_CFGR_MCO1_Pos                  (21U)                               
+#define RCC_CFGR_MCO1_Msk                  (0x3UL << RCC_CFGR_MCO1_Pos)         /*!< 0x00600000 */
+#define RCC_CFGR_MCO1                      RCC_CFGR_MCO1_Msk                   
+#define RCC_CFGR_MCO1_0                    (0x1UL << RCC_CFGR_MCO1_Pos)         /*!< 0x00200000 */
+#define RCC_CFGR_MCO1_1                    (0x2UL << RCC_CFGR_MCO1_Pos)         /*!< 0x00400000 */
+
+#define RCC_CFGR_I2SSRC_Pos                (23U)                               
+#define RCC_CFGR_I2SSRC_Msk                (0x1UL << RCC_CFGR_I2SSRC_Pos)       /*!< 0x00800000 */
+#define RCC_CFGR_I2SSRC                    RCC_CFGR_I2SSRC_Msk                 
+
+#define RCC_CFGR_MCO1PRE_Pos               (24U)                               
+#define RCC_CFGR_MCO1PRE_Msk               (0x7UL << RCC_CFGR_MCO1PRE_Pos)      /*!< 0x07000000 */
+#define RCC_CFGR_MCO1PRE                   RCC_CFGR_MCO1PRE_Msk                
+#define RCC_CFGR_MCO1PRE_0                 (0x1UL << RCC_CFGR_MCO1PRE_Pos)      /*!< 0x01000000 */
+#define RCC_CFGR_MCO1PRE_1                 (0x2UL << RCC_CFGR_MCO1PRE_Pos)      /*!< 0x02000000 */
+#define RCC_CFGR_MCO1PRE_2                 (0x4UL << RCC_CFGR_MCO1PRE_Pos)      /*!< 0x04000000 */
+
+#define RCC_CFGR_MCO2PRE_Pos               (27U)                               
+#define RCC_CFGR_MCO2PRE_Msk               (0x7UL << RCC_CFGR_MCO2PRE_Pos)      /*!< 0x38000000 */
+#define RCC_CFGR_MCO2PRE                   RCC_CFGR_MCO2PRE_Msk                
+#define RCC_CFGR_MCO2PRE_0                 (0x1UL << RCC_CFGR_MCO2PRE_Pos)      /*!< 0x08000000 */
+#define RCC_CFGR_MCO2PRE_1                 (0x2UL << RCC_CFGR_MCO2PRE_Pos)      /*!< 0x10000000 */
+#define RCC_CFGR_MCO2PRE_2                 (0x4UL << RCC_CFGR_MCO2PRE_Pos)      /*!< 0x20000000 */
+
+#define RCC_CFGR_MCO2_Pos                  (30U)                               
+#define RCC_CFGR_MCO2_Msk                  (0x3UL << RCC_CFGR_MCO2_Pos)         /*!< 0xC0000000 */
+#define RCC_CFGR_MCO2                      RCC_CFGR_MCO2_Msk                   
+#define RCC_CFGR_MCO2_0                    (0x1UL << RCC_CFGR_MCO2_Pos)         /*!< 0x40000000 */
+#define RCC_CFGR_MCO2_1                    (0x2UL << RCC_CFGR_MCO2_Pos)         /*!< 0x80000000 */
+
+/********************  Bit definition for RCC_CIR register  *******************/
+#define RCC_CIR_LSIRDYF_Pos                (0U)                                
+#define RCC_CIR_LSIRDYF_Msk                (0x1UL << RCC_CIR_LSIRDYF_Pos)       /*!< 0x00000001 */
+#define RCC_CIR_LSIRDYF                    RCC_CIR_LSIRDYF_Msk                 
+#define RCC_CIR_LSERDYF_Pos                (1U)                                
+#define RCC_CIR_LSERDYF_Msk                (0x1UL << RCC_CIR_LSERDYF_Pos)       /*!< 0x00000002 */
+#define RCC_CIR_LSERDYF                    RCC_CIR_LSERDYF_Msk                 
+#define RCC_CIR_HSIRDYF_Pos                (2U)                                
+#define RCC_CIR_HSIRDYF_Msk                (0x1UL << RCC_CIR_HSIRDYF_Pos)       /*!< 0x00000004 */
+#define RCC_CIR_HSIRDYF                    RCC_CIR_HSIRDYF_Msk                 
+#define RCC_CIR_HSERDYF_Pos                (3U)                                
+#define RCC_CIR_HSERDYF_Msk                (0x1UL << RCC_CIR_HSERDYF_Pos)       /*!< 0x00000008 */
+#define RCC_CIR_HSERDYF                    RCC_CIR_HSERDYF_Msk                 
+#define RCC_CIR_PLLRDYF_Pos                (4U)                                
+#define RCC_CIR_PLLRDYF_Msk                (0x1UL << RCC_CIR_PLLRDYF_Pos)       /*!< 0x00000010 */
+#define RCC_CIR_PLLRDYF                    RCC_CIR_PLLRDYF_Msk                 
+#define RCC_CIR_PLLI2SRDYF_Pos             (5U)                                
+#define RCC_CIR_PLLI2SRDYF_Msk             (0x1UL << RCC_CIR_PLLI2SRDYF_Pos)    /*!< 0x00000020 */
+#define RCC_CIR_PLLI2SRDYF                 RCC_CIR_PLLI2SRDYF_Msk              
+
+#define RCC_CIR_PLLSAIRDYF_Pos             (6U)                                
+#define RCC_CIR_PLLSAIRDYF_Msk             (0x1UL << RCC_CIR_PLLSAIRDYF_Pos)    /*!< 0x00000040 */
+#define RCC_CIR_PLLSAIRDYF                 RCC_CIR_PLLSAIRDYF_Msk              
+#define RCC_CIR_CSSF_Pos                   (7U)                                
+#define RCC_CIR_CSSF_Msk                   (0x1UL << RCC_CIR_CSSF_Pos)          /*!< 0x00000080 */
+#define RCC_CIR_CSSF                       RCC_CIR_CSSF_Msk                    
+#define RCC_CIR_LSIRDYIE_Pos               (8U)                                
+#define RCC_CIR_LSIRDYIE_Msk               (0x1UL << RCC_CIR_LSIRDYIE_Pos)      /*!< 0x00000100 */
+#define RCC_CIR_LSIRDYIE                   RCC_CIR_LSIRDYIE_Msk                
+#define RCC_CIR_LSERDYIE_Pos               (9U)                                
+#define RCC_CIR_LSERDYIE_Msk               (0x1UL << RCC_CIR_LSERDYIE_Pos)      /*!< 0x00000200 */
+#define RCC_CIR_LSERDYIE                   RCC_CIR_LSERDYIE_Msk                
+#define RCC_CIR_HSIRDYIE_Pos               (10U)                               
+#define RCC_CIR_HSIRDYIE_Msk               (0x1UL << RCC_CIR_HSIRDYIE_Pos)      /*!< 0x00000400 */
+#define RCC_CIR_HSIRDYIE                   RCC_CIR_HSIRDYIE_Msk                
+#define RCC_CIR_HSERDYIE_Pos               (11U)                               
+#define RCC_CIR_HSERDYIE_Msk               (0x1UL << RCC_CIR_HSERDYIE_Pos)      /*!< 0x00000800 */
+#define RCC_CIR_HSERDYIE                   RCC_CIR_HSERDYIE_Msk                
+#define RCC_CIR_PLLRDYIE_Pos               (12U)                               
+#define RCC_CIR_PLLRDYIE_Msk               (0x1UL << RCC_CIR_PLLRDYIE_Pos)      /*!< 0x00001000 */
+#define RCC_CIR_PLLRDYIE                   RCC_CIR_PLLRDYIE_Msk                
+#define RCC_CIR_PLLI2SRDYIE_Pos            (13U)                               
+#define RCC_CIR_PLLI2SRDYIE_Msk            (0x1UL << RCC_CIR_PLLI2SRDYIE_Pos)   /*!< 0x00002000 */
+#define RCC_CIR_PLLI2SRDYIE                RCC_CIR_PLLI2SRDYIE_Msk             
+
+#define RCC_CIR_PLLSAIRDYIE_Pos            (14U)                               
+#define RCC_CIR_PLLSAIRDYIE_Msk            (0x1UL << RCC_CIR_PLLSAIRDYIE_Pos)   /*!< 0x00004000 */
+#define RCC_CIR_PLLSAIRDYIE                RCC_CIR_PLLSAIRDYIE_Msk             
+#define RCC_CIR_LSIRDYC_Pos                (16U)                               
+#define RCC_CIR_LSIRDYC_Msk                (0x1UL << RCC_CIR_LSIRDYC_Pos)       /*!< 0x00010000 */
+#define RCC_CIR_LSIRDYC                    RCC_CIR_LSIRDYC_Msk                 
+#define RCC_CIR_LSERDYC_Pos                (17U)                               
+#define RCC_CIR_LSERDYC_Msk                (0x1UL << RCC_CIR_LSERDYC_Pos)       /*!< 0x00020000 */
+#define RCC_CIR_LSERDYC                    RCC_CIR_LSERDYC_Msk                 
+#define RCC_CIR_HSIRDYC_Pos                (18U)                               
+#define RCC_CIR_HSIRDYC_Msk                (0x1UL << RCC_CIR_HSIRDYC_Pos)       /*!< 0x00040000 */
+#define RCC_CIR_HSIRDYC                    RCC_CIR_HSIRDYC_Msk                 
+#define RCC_CIR_HSERDYC_Pos                (19U)                               
+#define RCC_CIR_HSERDYC_Msk                (0x1UL << RCC_CIR_HSERDYC_Pos)       /*!< 0x00080000 */
+#define RCC_CIR_HSERDYC                    RCC_CIR_HSERDYC_Msk                 
+#define RCC_CIR_PLLRDYC_Pos                (20U)                               
+#define RCC_CIR_PLLRDYC_Msk                (0x1UL << RCC_CIR_PLLRDYC_Pos)       /*!< 0x00100000 */
+#define RCC_CIR_PLLRDYC                    RCC_CIR_PLLRDYC_Msk                 
+#define RCC_CIR_PLLI2SRDYC_Pos             (21U)                               
+#define RCC_CIR_PLLI2SRDYC_Msk             (0x1UL << RCC_CIR_PLLI2SRDYC_Pos)    /*!< 0x00200000 */
+#define RCC_CIR_PLLI2SRDYC                 RCC_CIR_PLLI2SRDYC_Msk              
+#define RCC_CIR_PLLSAIRDYC_Pos             (22U)                               
+#define RCC_CIR_PLLSAIRDYC_Msk             (0x1UL << RCC_CIR_PLLSAIRDYC_Pos)    /*!< 0x00400000 */
+#define RCC_CIR_PLLSAIRDYC                 RCC_CIR_PLLSAIRDYC_Msk              
+
+#define RCC_CIR_CSSC_Pos                   (23U)                               
+#define RCC_CIR_CSSC_Msk                   (0x1UL << RCC_CIR_CSSC_Pos)          /*!< 0x00800000 */
+#define RCC_CIR_CSSC                       RCC_CIR_CSSC_Msk                    
+
+/********************  Bit definition for RCC_AHB1RSTR register  **************/
+#define RCC_AHB1RSTR_GPIOARST_Pos          (0U)                                
+#define RCC_AHB1RSTR_GPIOARST_Msk          (0x1UL << RCC_AHB1RSTR_GPIOARST_Pos) /*!< 0x00000001 */
+#define RCC_AHB1RSTR_GPIOARST              RCC_AHB1RSTR_GPIOARST_Msk           
+#define RCC_AHB1RSTR_GPIOBRST_Pos          (1U)                                
+#define RCC_AHB1RSTR_GPIOBRST_Msk          (0x1UL << RCC_AHB1RSTR_GPIOBRST_Pos) /*!< 0x00000002 */
+#define RCC_AHB1RSTR_GPIOBRST              RCC_AHB1RSTR_GPIOBRST_Msk           
+#define RCC_AHB1RSTR_GPIOCRST_Pos          (2U)                                
+#define RCC_AHB1RSTR_GPIOCRST_Msk          (0x1UL << RCC_AHB1RSTR_GPIOCRST_Pos) /*!< 0x00000004 */
+#define RCC_AHB1RSTR_GPIOCRST              RCC_AHB1RSTR_GPIOCRST_Msk           
+#define RCC_AHB1RSTR_GPIODRST_Pos          (3U)                                
+#define RCC_AHB1RSTR_GPIODRST_Msk          (0x1UL << RCC_AHB1RSTR_GPIODRST_Pos) /*!< 0x00000008 */
+#define RCC_AHB1RSTR_GPIODRST              RCC_AHB1RSTR_GPIODRST_Msk           
+#define RCC_AHB1RSTR_GPIOERST_Pos          (4U)                                
+#define RCC_AHB1RSTR_GPIOERST_Msk          (0x1UL << RCC_AHB1RSTR_GPIOERST_Pos) /*!< 0x00000010 */
+#define RCC_AHB1RSTR_GPIOERST              RCC_AHB1RSTR_GPIOERST_Msk           
+#define RCC_AHB1RSTR_GPIOFRST_Pos          (5U)                                
+#define RCC_AHB1RSTR_GPIOFRST_Msk          (0x1UL << RCC_AHB1RSTR_GPIOFRST_Pos) /*!< 0x00000020 */
+#define RCC_AHB1RSTR_GPIOFRST              RCC_AHB1RSTR_GPIOFRST_Msk           
+#define RCC_AHB1RSTR_GPIOGRST_Pos          (6U)                                
+#define RCC_AHB1RSTR_GPIOGRST_Msk          (0x1UL << RCC_AHB1RSTR_GPIOGRST_Pos) /*!< 0x00000040 */
+#define RCC_AHB1RSTR_GPIOGRST              RCC_AHB1RSTR_GPIOGRST_Msk           
+#define RCC_AHB1RSTR_GPIOHRST_Pos          (7U)                                
+#define RCC_AHB1RSTR_GPIOHRST_Msk          (0x1UL << RCC_AHB1RSTR_GPIOHRST_Pos) /*!< 0x00000080 */
+#define RCC_AHB1RSTR_GPIOHRST              RCC_AHB1RSTR_GPIOHRST_Msk           
+#define RCC_AHB1RSTR_GPIOIRST_Pos          (8U)                                
+#define RCC_AHB1RSTR_GPIOIRST_Msk          (0x1UL << RCC_AHB1RSTR_GPIOIRST_Pos) /*!< 0x00000100 */
+#define RCC_AHB1RSTR_GPIOIRST              RCC_AHB1RSTR_GPIOIRST_Msk           
+#define RCC_AHB1RSTR_GPIOJRST_Pos          (9U)                                
+#define RCC_AHB1RSTR_GPIOJRST_Msk          (0x1UL << RCC_AHB1RSTR_GPIOJRST_Pos) /*!< 0x00000200 */
+#define RCC_AHB1RSTR_GPIOJRST              RCC_AHB1RSTR_GPIOJRST_Msk           
+#define RCC_AHB1RSTR_GPIOKRST_Pos          (10U)                               
+#define RCC_AHB1RSTR_GPIOKRST_Msk          (0x1UL << RCC_AHB1RSTR_GPIOKRST_Pos) /*!< 0x00000400 */
+#define RCC_AHB1RSTR_GPIOKRST              RCC_AHB1RSTR_GPIOKRST_Msk           
+#define RCC_AHB1RSTR_CRCRST_Pos            (12U)                               
+#define RCC_AHB1RSTR_CRCRST_Msk            (0x1UL << RCC_AHB1RSTR_CRCRST_Pos)   /*!< 0x00001000 */
+#define RCC_AHB1RSTR_CRCRST                RCC_AHB1RSTR_CRCRST_Msk             
+#define RCC_AHB1RSTR_DMA1RST_Pos           (21U)                               
+#define RCC_AHB1RSTR_DMA1RST_Msk           (0x1UL << RCC_AHB1RSTR_DMA1RST_Pos)  /*!< 0x00200000 */
+#define RCC_AHB1RSTR_DMA1RST               RCC_AHB1RSTR_DMA1RST_Msk            
+#define RCC_AHB1RSTR_DMA2RST_Pos           (22U)                               
+#define RCC_AHB1RSTR_DMA2RST_Msk           (0x1UL << RCC_AHB1RSTR_DMA2RST_Pos)  /*!< 0x00400000 */
+#define RCC_AHB1RSTR_DMA2RST               RCC_AHB1RSTR_DMA2RST_Msk            
+#define RCC_AHB1RSTR_DMA2DRST_Pos          (23U)                               
+#define RCC_AHB1RSTR_DMA2DRST_Msk          (0x1UL << RCC_AHB1RSTR_DMA2DRST_Pos) /*!< 0x00800000 */
+#define RCC_AHB1RSTR_DMA2DRST              RCC_AHB1RSTR_DMA2DRST_Msk           
+#define RCC_AHB1RSTR_ETHMACRST_Pos         (25U)                               
+#define RCC_AHB1RSTR_ETHMACRST_Msk         (0x1UL << RCC_AHB1RSTR_ETHMACRST_Pos) /*!< 0x02000000 */
+#define RCC_AHB1RSTR_ETHMACRST             RCC_AHB1RSTR_ETHMACRST_Msk          
+#define RCC_AHB1RSTR_OTGHRST_Pos           (29U)                               
+#define RCC_AHB1RSTR_OTGHRST_Msk           (0x1UL << RCC_AHB1RSTR_OTGHRST_Pos)  /*!< 0x20000000 */
+#define RCC_AHB1RSTR_OTGHRST               RCC_AHB1RSTR_OTGHRST_Msk            
+
+/********************  Bit definition for RCC_AHB2RSTR register  **************/
+#define RCC_AHB2RSTR_DCMIRST_Pos           (0U)                                
+#define RCC_AHB2RSTR_DCMIRST_Msk           (0x1UL << RCC_AHB2RSTR_DCMIRST_Pos)  /*!< 0x00000001 */
+#define RCC_AHB2RSTR_DCMIRST               RCC_AHB2RSTR_DCMIRST_Msk            
+#define RCC_AHB2RSTR_RNGRST_Pos            (6U)                                
+#define RCC_AHB2RSTR_RNGRST_Msk            (0x1UL << RCC_AHB2RSTR_RNGRST_Pos)   /*!< 0x00000040 */
+#define RCC_AHB2RSTR_RNGRST                RCC_AHB2RSTR_RNGRST_Msk             
+#define RCC_AHB2RSTR_OTGFSRST_Pos          (7U)                                
+#define RCC_AHB2RSTR_OTGFSRST_Msk          (0x1UL << RCC_AHB2RSTR_OTGFSRST_Pos) /*!< 0x00000080 */
+#define RCC_AHB2RSTR_OTGFSRST              RCC_AHB2RSTR_OTGFSRST_Msk           
+/********************  Bit definition for RCC_AHB3RSTR register  **************/
+#define RCC_AHB3RSTR_FMCRST_Pos            (0U)                                
+#define RCC_AHB3RSTR_FMCRST_Msk            (0x1UL << RCC_AHB3RSTR_FMCRST_Pos)   /*!< 0x00000001 */
+#define RCC_AHB3RSTR_FMCRST                RCC_AHB3RSTR_FMCRST_Msk             
+#define RCC_AHB3RSTR_QSPIRST_Pos           (1U)                                
+#define RCC_AHB3RSTR_QSPIRST_Msk           (0x1UL << RCC_AHB3RSTR_QSPIRST_Pos)  /*!< 0x00000002 */
+#define RCC_AHB3RSTR_QSPIRST               RCC_AHB3RSTR_QSPIRST_Msk            
+
+
+/********************  Bit definition for RCC_APB1RSTR register  **************/
+#define RCC_APB1RSTR_TIM2RST_Pos           (0U)                                
+#define RCC_APB1RSTR_TIM2RST_Msk           (0x1UL << RCC_APB1RSTR_TIM2RST_Pos)  /*!< 0x00000001 */
+#define RCC_APB1RSTR_TIM2RST               RCC_APB1RSTR_TIM2RST_Msk            
+#define RCC_APB1RSTR_TIM3RST_Pos           (1U)                                
+#define RCC_APB1RSTR_TIM3RST_Msk           (0x1UL << RCC_APB1RSTR_TIM3RST_Pos)  /*!< 0x00000002 */
+#define RCC_APB1RSTR_TIM3RST               RCC_APB1RSTR_TIM3RST_Msk            
+#define RCC_APB1RSTR_TIM4RST_Pos           (2U)                                
+#define RCC_APB1RSTR_TIM4RST_Msk           (0x1UL << RCC_APB1RSTR_TIM4RST_Pos)  /*!< 0x00000004 */
+#define RCC_APB1RSTR_TIM4RST               RCC_APB1RSTR_TIM4RST_Msk            
+#define RCC_APB1RSTR_TIM5RST_Pos           (3U)                                
+#define RCC_APB1RSTR_TIM5RST_Msk           (0x1UL << RCC_APB1RSTR_TIM5RST_Pos)  /*!< 0x00000008 */
+#define RCC_APB1RSTR_TIM5RST               RCC_APB1RSTR_TIM5RST_Msk            
+#define RCC_APB1RSTR_TIM6RST_Pos           (4U)                                
+#define RCC_APB1RSTR_TIM6RST_Msk           (0x1UL << RCC_APB1RSTR_TIM6RST_Pos)  /*!< 0x00000010 */
+#define RCC_APB1RSTR_TIM6RST               RCC_APB1RSTR_TIM6RST_Msk            
+#define RCC_APB1RSTR_TIM7RST_Pos           (5U)                                
+#define RCC_APB1RSTR_TIM7RST_Msk           (0x1UL << RCC_APB1RSTR_TIM7RST_Pos)  /*!< 0x00000020 */
+#define RCC_APB1RSTR_TIM7RST               RCC_APB1RSTR_TIM7RST_Msk            
+#define RCC_APB1RSTR_TIM12RST_Pos          (6U)                                
+#define RCC_APB1RSTR_TIM12RST_Msk          (0x1UL << RCC_APB1RSTR_TIM12RST_Pos) /*!< 0x00000040 */
+#define RCC_APB1RSTR_TIM12RST              RCC_APB1RSTR_TIM12RST_Msk           
+#define RCC_APB1RSTR_TIM13RST_Pos          (7U)                                
+#define RCC_APB1RSTR_TIM13RST_Msk          (0x1UL << RCC_APB1RSTR_TIM13RST_Pos) /*!< 0x00000080 */
+#define RCC_APB1RSTR_TIM13RST              RCC_APB1RSTR_TIM13RST_Msk           
+#define RCC_APB1RSTR_TIM14RST_Pos          (8U)                                
+#define RCC_APB1RSTR_TIM14RST_Msk          (0x1UL << RCC_APB1RSTR_TIM14RST_Pos) /*!< 0x00000100 */
+#define RCC_APB1RSTR_TIM14RST              RCC_APB1RSTR_TIM14RST_Msk           
+#define RCC_APB1RSTR_WWDGRST_Pos           (11U)                               
+#define RCC_APB1RSTR_WWDGRST_Msk           (0x1UL << RCC_APB1RSTR_WWDGRST_Pos)  /*!< 0x00000800 */
+#define RCC_APB1RSTR_WWDGRST               RCC_APB1RSTR_WWDGRST_Msk            
+#define RCC_APB1RSTR_SPI2RST_Pos           (14U)                               
+#define RCC_APB1RSTR_SPI2RST_Msk           (0x1UL << RCC_APB1RSTR_SPI2RST_Pos)  /*!< 0x00004000 */
+#define RCC_APB1RSTR_SPI2RST               RCC_APB1RSTR_SPI2RST_Msk            
+#define RCC_APB1RSTR_SPI3RST_Pos           (15U)                               
+#define RCC_APB1RSTR_SPI3RST_Msk           (0x1UL << RCC_APB1RSTR_SPI3RST_Pos)  /*!< 0x00008000 */
+#define RCC_APB1RSTR_SPI3RST               RCC_APB1RSTR_SPI3RST_Msk            
+#define RCC_APB1RSTR_USART2RST_Pos         (17U)                               
+#define RCC_APB1RSTR_USART2RST_Msk         (0x1UL << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */
+#define RCC_APB1RSTR_USART2RST             RCC_APB1RSTR_USART2RST_Msk          
+#define RCC_APB1RSTR_USART3RST_Pos         (18U)                               
+#define RCC_APB1RSTR_USART3RST_Msk         (0x1UL << RCC_APB1RSTR_USART3RST_Pos) /*!< 0x00040000 */
+#define RCC_APB1RSTR_USART3RST             RCC_APB1RSTR_USART3RST_Msk          
+#define RCC_APB1RSTR_UART4RST_Pos          (19U)                               
+#define RCC_APB1RSTR_UART4RST_Msk          (0x1UL << RCC_APB1RSTR_UART4RST_Pos) /*!< 0x00080000 */
+#define RCC_APB1RSTR_UART4RST              RCC_APB1RSTR_UART4RST_Msk           
+#define RCC_APB1RSTR_UART5RST_Pos          (20U)                               
+#define RCC_APB1RSTR_UART5RST_Msk          (0x1UL << RCC_APB1RSTR_UART5RST_Pos) /*!< 0x00100000 */
+#define RCC_APB1RSTR_UART5RST              RCC_APB1RSTR_UART5RST_Msk           
+#define RCC_APB1RSTR_I2C1RST_Pos           (21U)                               
+#define RCC_APB1RSTR_I2C1RST_Msk           (0x1UL << RCC_APB1RSTR_I2C1RST_Pos)  /*!< 0x00200000 */
+#define RCC_APB1RSTR_I2C1RST               RCC_APB1RSTR_I2C1RST_Msk            
+#define RCC_APB1RSTR_I2C2RST_Pos           (22U)                               
+#define RCC_APB1RSTR_I2C2RST_Msk           (0x1UL << RCC_APB1RSTR_I2C2RST_Pos)  /*!< 0x00400000 */
+#define RCC_APB1RSTR_I2C2RST               RCC_APB1RSTR_I2C2RST_Msk            
+#define RCC_APB1RSTR_I2C3RST_Pos           (23U)                               
+#define RCC_APB1RSTR_I2C3RST_Msk           (0x1UL << RCC_APB1RSTR_I2C3RST_Pos)  /*!< 0x00800000 */
+#define RCC_APB1RSTR_I2C3RST               RCC_APB1RSTR_I2C3RST_Msk            
+#define RCC_APB1RSTR_CAN1RST_Pos           (25U)                               
+#define RCC_APB1RSTR_CAN1RST_Msk           (0x1UL << RCC_APB1RSTR_CAN1RST_Pos)  /*!< 0x02000000 */
+#define RCC_APB1RSTR_CAN1RST               RCC_APB1RSTR_CAN1RST_Msk            
+#define RCC_APB1RSTR_CAN2RST_Pos           (26U)                               
+#define RCC_APB1RSTR_CAN2RST_Msk           (0x1UL << RCC_APB1RSTR_CAN2RST_Pos)  /*!< 0x04000000 */
+#define RCC_APB1RSTR_CAN2RST               RCC_APB1RSTR_CAN2RST_Msk            
+#define RCC_APB1RSTR_PWRRST_Pos            (28U)                               
+#define RCC_APB1RSTR_PWRRST_Msk            (0x1UL << RCC_APB1RSTR_PWRRST_Pos)   /*!< 0x10000000 */
+#define RCC_APB1RSTR_PWRRST                RCC_APB1RSTR_PWRRST_Msk             
+#define RCC_APB1RSTR_DACRST_Pos            (29U)                               
+#define RCC_APB1RSTR_DACRST_Msk            (0x1UL << RCC_APB1RSTR_DACRST_Pos)   /*!< 0x20000000 */
+#define RCC_APB1RSTR_DACRST                RCC_APB1RSTR_DACRST_Msk             
+#define RCC_APB1RSTR_UART7RST_Pos          (30U)                               
+#define RCC_APB1RSTR_UART7RST_Msk          (0x1UL << RCC_APB1RSTR_UART7RST_Pos) /*!< 0x40000000 */
+#define RCC_APB1RSTR_UART7RST              RCC_APB1RSTR_UART7RST_Msk           
+#define RCC_APB1RSTR_UART8RST_Pos          (31U)                               
+#define RCC_APB1RSTR_UART8RST_Msk          (0x1UL << RCC_APB1RSTR_UART8RST_Pos) /*!< 0x80000000 */
+#define RCC_APB1RSTR_UART8RST              RCC_APB1RSTR_UART8RST_Msk           
+
+/********************  Bit definition for RCC_APB2RSTR register  **************/
+#define RCC_APB2RSTR_TIM1RST_Pos           (0U)                                
+#define RCC_APB2RSTR_TIM1RST_Msk           (0x1UL << RCC_APB2RSTR_TIM1RST_Pos)  /*!< 0x00000001 */
+#define RCC_APB2RSTR_TIM1RST               RCC_APB2RSTR_TIM1RST_Msk            
+#define RCC_APB2RSTR_TIM8RST_Pos           (1U)                                
+#define RCC_APB2RSTR_TIM8RST_Msk           (0x1UL << RCC_APB2RSTR_TIM8RST_Pos)  /*!< 0x00000002 */
+#define RCC_APB2RSTR_TIM8RST               RCC_APB2RSTR_TIM8RST_Msk            
+#define RCC_APB2RSTR_USART1RST_Pos         (4U)                                
+#define RCC_APB2RSTR_USART1RST_Msk         (0x1UL << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00000010 */
+#define RCC_APB2RSTR_USART1RST             RCC_APB2RSTR_USART1RST_Msk          
+#define RCC_APB2RSTR_USART6RST_Pos         (5U)                                
+#define RCC_APB2RSTR_USART6RST_Msk         (0x1UL << RCC_APB2RSTR_USART6RST_Pos) /*!< 0x00000020 */
+#define RCC_APB2RSTR_USART6RST             RCC_APB2RSTR_USART6RST_Msk          
+#define RCC_APB2RSTR_ADCRST_Pos            (8U)                                
+#define RCC_APB2RSTR_ADCRST_Msk            (0x1UL << RCC_APB2RSTR_ADCRST_Pos)   /*!< 0x00000100 */
+#define RCC_APB2RSTR_ADCRST                RCC_APB2RSTR_ADCRST_Msk             
+#define RCC_APB2RSTR_SDIORST_Pos           (11U)                               
+#define RCC_APB2RSTR_SDIORST_Msk           (0x1UL << RCC_APB2RSTR_SDIORST_Pos)  /*!< 0x00000800 */
+#define RCC_APB2RSTR_SDIORST               RCC_APB2RSTR_SDIORST_Msk            
+#define RCC_APB2RSTR_SPI1RST_Pos           (12U)                               
+#define RCC_APB2RSTR_SPI1RST_Msk           (0x1UL << RCC_APB2RSTR_SPI1RST_Pos)  /*!< 0x00001000 */
+#define RCC_APB2RSTR_SPI1RST               RCC_APB2RSTR_SPI1RST_Msk            
+#define RCC_APB2RSTR_SPI4RST_Pos           (13U)                               
+#define RCC_APB2RSTR_SPI4RST_Msk           (0x1UL << RCC_APB2RSTR_SPI4RST_Pos)  /*!< 0x00002000 */
+#define RCC_APB2RSTR_SPI4RST               RCC_APB2RSTR_SPI4RST_Msk            
+#define RCC_APB2RSTR_SYSCFGRST_Pos         (14U)                               
+#define RCC_APB2RSTR_SYSCFGRST_Msk         (0x1UL << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00004000 */
+#define RCC_APB2RSTR_SYSCFGRST             RCC_APB2RSTR_SYSCFGRST_Msk          
+#define RCC_APB2RSTR_TIM9RST_Pos           (16U)                               
+#define RCC_APB2RSTR_TIM9RST_Msk           (0x1UL << RCC_APB2RSTR_TIM9RST_Pos)  /*!< 0x00010000 */
+#define RCC_APB2RSTR_TIM9RST               RCC_APB2RSTR_TIM9RST_Msk            
+#define RCC_APB2RSTR_TIM10RST_Pos          (17U)                               
+#define RCC_APB2RSTR_TIM10RST_Msk          (0x1UL << RCC_APB2RSTR_TIM10RST_Pos) /*!< 0x00020000 */
+#define RCC_APB2RSTR_TIM10RST              RCC_APB2RSTR_TIM10RST_Msk           
+#define RCC_APB2RSTR_TIM11RST_Pos          (18U)                               
+#define RCC_APB2RSTR_TIM11RST_Msk          (0x1UL << RCC_APB2RSTR_TIM11RST_Pos) /*!< 0x00040000 */
+#define RCC_APB2RSTR_TIM11RST              RCC_APB2RSTR_TIM11RST_Msk           
+#define RCC_APB2RSTR_SPI5RST_Pos           (20U)                               
+#define RCC_APB2RSTR_SPI5RST_Msk           (0x1UL << RCC_APB2RSTR_SPI5RST_Pos)  /*!< 0x00100000 */
+#define RCC_APB2RSTR_SPI5RST               RCC_APB2RSTR_SPI5RST_Msk            
+#define RCC_APB2RSTR_SPI6RST_Pos           (21U)                               
+#define RCC_APB2RSTR_SPI6RST_Msk           (0x1UL << RCC_APB2RSTR_SPI6RST_Pos)  /*!< 0x00200000 */
+#define RCC_APB2RSTR_SPI6RST               RCC_APB2RSTR_SPI6RST_Msk            
+#define RCC_APB2RSTR_SAI1RST_Pos           (22U)                               
+#define RCC_APB2RSTR_SAI1RST_Msk           (0x1UL << RCC_APB2RSTR_SAI1RST_Pos)  /*!< 0x00400000 */
+#define RCC_APB2RSTR_SAI1RST               RCC_APB2RSTR_SAI1RST_Msk            
+#define RCC_APB2RSTR_LTDCRST_Pos           (26U)                               
+#define RCC_APB2RSTR_LTDCRST_Msk           (0x1UL << RCC_APB2RSTR_LTDCRST_Pos)  /*!< 0x04000000 */
+#define RCC_APB2RSTR_LTDCRST               RCC_APB2RSTR_LTDCRST_Msk            
+#define RCC_APB2RSTR_DSIRST_Pos            (27U)                               
+#define RCC_APB2RSTR_DSIRST_Msk            (0x1UL << RCC_APB2RSTR_DSIRST_Pos)   /*!< 0x08000000 */
+#define RCC_APB2RSTR_DSIRST                RCC_APB2RSTR_DSIRST_Msk             
+
+/* Old SPI1RST bit definition, maintained for legacy purpose */
+#define  RCC_APB2RSTR_SPI1                   RCC_APB2RSTR_SPI1RST
+
+/********************  Bit definition for RCC_AHB1ENR register  ***************/
+#define RCC_AHB1ENR_GPIOAEN_Pos            (0U)                                
+#define RCC_AHB1ENR_GPIOAEN_Msk            (0x1UL << RCC_AHB1ENR_GPIOAEN_Pos)   /*!< 0x00000001 */
+#define RCC_AHB1ENR_GPIOAEN                RCC_AHB1ENR_GPIOAEN_Msk             
+#define RCC_AHB1ENR_GPIOBEN_Pos            (1U)                                
+#define RCC_AHB1ENR_GPIOBEN_Msk            (0x1UL << RCC_AHB1ENR_GPIOBEN_Pos)   /*!< 0x00000002 */
+#define RCC_AHB1ENR_GPIOBEN                RCC_AHB1ENR_GPIOBEN_Msk             
+#define RCC_AHB1ENR_GPIOCEN_Pos            (2U)                                
+#define RCC_AHB1ENR_GPIOCEN_Msk            (0x1UL << RCC_AHB1ENR_GPIOCEN_Pos)   /*!< 0x00000004 */
+#define RCC_AHB1ENR_GPIOCEN                RCC_AHB1ENR_GPIOCEN_Msk             
+#define RCC_AHB1ENR_GPIODEN_Pos            (3U)                                
+#define RCC_AHB1ENR_GPIODEN_Msk            (0x1UL << RCC_AHB1ENR_GPIODEN_Pos)   /*!< 0x00000008 */
+#define RCC_AHB1ENR_GPIODEN                RCC_AHB1ENR_GPIODEN_Msk             
+#define RCC_AHB1ENR_GPIOEEN_Pos            (4U)                                
+#define RCC_AHB1ENR_GPIOEEN_Msk            (0x1UL << RCC_AHB1ENR_GPIOEEN_Pos)   /*!< 0x00000010 */
+#define RCC_AHB1ENR_GPIOEEN                RCC_AHB1ENR_GPIOEEN_Msk             
+#define RCC_AHB1ENR_GPIOFEN_Pos            (5U)                                
+#define RCC_AHB1ENR_GPIOFEN_Msk            (0x1UL << RCC_AHB1ENR_GPIOFEN_Pos)   /*!< 0x00000020 */
+#define RCC_AHB1ENR_GPIOFEN                RCC_AHB1ENR_GPIOFEN_Msk             
+#define RCC_AHB1ENR_GPIOGEN_Pos            (6U)                                
+#define RCC_AHB1ENR_GPIOGEN_Msk            (0x1UL << RCC_AHB1ENR_GPIOGEN_Pos)   /*!< 0x00000040 */
+#define RCC_AHB1ENR_GPIOGEN                RCC_AHB1ENR_GPIOGEN_Msk             
+#define RCC_AHB1ENR_GPIOHEN_Pos            (7U)                                
+#define RCC_AHB1ENR_GPIOHEN_Msk            (0x1UL << RCC_AHB1ENR_GPIOHEN_Pos)   /*!< 0x00000080 */
+#define RCC_AHB1ENR_GPIOHEN                RCC_AHB1ENR_GPIOHEN_Msk             
+#define RCC_AHB1ENR_GPIOIEN_Pos            (8U)                                
+#define RCC_AHB1ENR_GPIOIEN_Msk            (0x1UL << RCC_AHB1ENR_GPIOIEN_Pos)   /*!< 0x00000100 */
+#define RCC_AHB1ENR_GPIOIEN                RCC_AHB1ENR_GPIOIEN_Msk             
+#define RCC_AHB1ENR_GPIOJEN_Pos            (9U)                                
+#define RCC_AHB1ENR_GPIOJEN_Msk            (0x1UL << RCC_AHB1ENR_GPIOJEN_Pos)   /*!< 0x00000200 */
+#define RCC_AHB1ENR_GPIOJEN                RCC_AHB1ENR_GPIOJEN_Msk             
+#define RCC_AHB1ENR_GPIOKEN_Pos            (10U)                               
+#define RCC_AHB1ENR_GPIOKEN_Msk            (0x1UL << RCC_AHB1ENR_GPIOKEN_Pos)   /*!< 0x00000400 */
+#define RCC_AHB1ENR_GPIOKEN                RCC_AHB1ENR_GPIOKEN_Msk             
+#define RCC_AHB1ENR_CRCEN_Pos              (12U)                               
+#define RCC_AHB1ENR_CRCEN_Msk              (0x1UL << RCC_AHB1ENR_CRCEN_Pos)     /*!< 0x00001000 */
+#define RCC_AHB1ENR_CRCEN                  RCC_AHB1ENR_CRCEN_Msk               
+#define RCC_AHB1ENR_BKPSRAMEN_Pos          (18U)                               
+#define RCC_AHB1ENR_BKPSRAMEN_Msk          (0x1UL << RCC_AHB1ENR_BKPSRAMEN_Pos) /*!< 0x00040000 */
+#define RCC_AHB1ENR_BKPSRAMEN              RCC_AHB1ENR_BKPSRAMEN_Msk           
+#define RCC_AHB1ENR_CCMDATARAMEN_Pos       (20U)                               
+#define RCC_AHB1ENR_CCMDATARAMEN_Msk       (0x1UL << RCC_AHB1ENR_CCMDATARAMEN_Pos) /*!< 0x00100000 */
+#define RCC_AHB1ENR_CCMDATARAMEN           RCC_AHB1ENR_CCMDATARAMEN_Msk        
+#define RCC_AHB1ENR_DMA1EN_Pos             (21U)                               
+#define RCC_AHB1ENR_DMA1EN_Msk             (0x1UL << RCC_AHB1ENR_DMA1EN_Pos)    /*!< 0x00200000 */
+#define RCC_AHB1ENR_DMA1EN                 RCC_AHB1ENR_DMA1EN_Msk              
+#define RCC_AHB1ENR_DMA2EN_Pos             (22U)                               
+#define RCC_AHB1ENR_DMA2EN_Msk             (0x1UL << RCC_AHB1ENR_DMA2EN_Pos)    /*!< 0x00400000 */
+#define RCC_AHB1ENR_DMA2EN                 RCC_AHB1ENR_DMA2EN_Msk              
+#define RCC_AHB1ENR_DMA2DEN_Pos            (23U)                               
+#define RCC_AHB1ENR_DMA2DEN_Msk            (0x1UL << RCC_AHB1ENR_DMA2DEN_Pos)   /*!< 0x00800000 */
+#define RCC_AHB1ENR_DMA2DEN                RCC_AHB1ENR_DMA2DEN_Msk             
+#define RCC_AHB1ENR_ETHMACEN_Pos           (25U)                               
+#define RCC_AHB1ENR_ETHMACEN_Msk           (0x1UL << RCC_AHB1ENR_ETHMACEN_Pos)  /*!< 0x02000000 */
+#define RCC_AHB1ENR_ETHMACEN               RCC_AHB1ENR_ETHMACEN_Msk            
+#define RCC_AHB1ENR_ETHMACTXEN_Pos         (26U)                               
+#define RCC_AHB1ENR_ETHMACTXEN_Msk         (0x1UL << RCC_AHB1ENR_ETHMACTXEN_Pos) /*!< 0x04000000 */
+#define RCC_AHB1ENR_ETHMACTXEN             RCC_AHB1ENR_ETHMACTXEN_Msk          
+#define RCC_AHB1ENR_ETHMACRXEN_Pos         (27U)                               
+#define RCC_AHB1ENR_ETHMACRXEN_Msk         (0x1UL << RCC_AHB1ENR_ETHMACRXEN_Pos) /*!< 0x08000000 */
+#define RCC_AHB1ENR_ETHMACRXEN             RCC_AHB1ENR_ETHMACRXEN_Msk          
+#define RCC_AHB1ENR_ETHMACPTPEN_Pos        (28U)                               
+#define RCC_AHB1ENR_ETHMACPTPEN_Msk        (0x1UL << RCC_AHB1ENR_ETHMACPTPEN_Pos) /*!< 0x10000000 */
+#define RCC_AHB1ENR_ETHMACPTPEN            RCC_AHB1ENR_ETHMACPTPEN_Msk         
+#define RCC_AHB1ENR_OTGHSEN_Pos            (29U)                               
+#define RCC_AHB1ENR_OTGHSEN_Msk            (0x1UL << RCC_AHB1ENR_OTGHSEN_Pos)   /*!< 0x20000000 */
+#define RCC_AHB1ENR_OTGHSEN                RCC_AHB1ENR_OTGHSEN_Msk             
+#define RCC_AHB1ENR_OTGHSULPIEN_Pos        (30U)                               
+#define RCC_AHB1ENR_OTGHSULPIEN_Msk        (0x1UL << RCC_AHB1ENR_OTGHSULPIEN_Pos) /*!< 0x40000000 */
+#define RCC_AHB1ENR_OTGHSULPIEN            RCC_AHB1ENR_OTGHSULPIEN_Msk         
+/********************  Bit definition for RCC_AHB2ENR register  ***************/
+/*
+ * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
+ */
+#define RCC_AHB2_SUPPORT                   /*!< AHB2 Bus is supported */
+
+#define RCC_AHB2ENR_DCMIEN_Pos             (0U)                                
+#define RCC_AHB2ENR_DCMIEN_Msk             (0x1UL << RCC_AHB2ENR_DCMIEN_Pos)    /*!< 0x00000001 */
+#define RCC_AHB2ENR_DCMIEN                 RCC_AHB2ENR_DCMIEN_Msk              
+#define RCC_AHB2ENR_RNGEN_Pos              (6U)                                
+#define RCC_AHB2ENR_RNGEN_Msk              (0x1UL << RCC_AHB2ENR_RNGEN_Pos)     /*!< 0x00000040 */
+#define RCC_AHB2ENR_RNGEN                  RCC_AHB2ENR_RNGEN_Msk               
+#define RCC_AHB2ENR_OTGFSEN_Pos            (7U)                                
+#define RCC_AHB2ENR_OTGFSEN_Msk            (0x1UL << RCC_AHB2ENR_OTGFSEN_Pos)   /*!< 0x00000080 */
+#define RCC_AHB2ENR_OTGFSEN                RCC_AHB2ENR_OTGFSEN_Msk             
+
+/********************  Bit definition for RCC_AHB3ENR register  ***************/
+/*
+ * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
+ */
+#define RCC_AHB3_SUPPORT                   /*!< AHB3 Bus is supported */
+
+#define RCC_AHB3ENR_FMCEN_Pos              (0U)                                
+#define RCC_AHB3ENR_FMCEN_Msk              (0x1UL << RCC_AHB3ENR_FMCEN_Pos)     /*!< 0x00000001 */
+#define RCC_AHB3ENR_FMCEN                  RCC_AHB3ENR_FMCEN_Msk               
+#define RCC_AHB3ENR_QSPIEN_Pos             (1U)                                
+#define RCC_AHB3ENR_QSPIEN_Msk             (0x1UL << RCC_AHB3ENR_QSPIEN_Pos)    /*!< 0x00000002 */
+#define RCC_AHB3ENR_QSPIEN                 RCC_AHB3ENR_QSPIEN_Msk              
+
+/********************  Bit definition for RCC_APB1ENR register  ***************/
+#define RCC_APB1ENR_TIM2EN_Pos             (0U)                                
+#define RCC_APB1ENR_TIM2EN_Msk             (0x1UL << RCC_APB1ENR_TIM2EN_Pos)    /*!< 0x00000001 */
+#define RCC_APB1ENR_TIM2EN                 RCC_APB1ENR_TIM2EN_Msk              
+#define RCC_APB1ENR_TIM3EN_Pos             (1U)                                
+#define RCC_APB1ENR_TIM3EN_Msk             (0x1UL << RCC_APB1ENR_TIM3EN_Pos)    /*!< 0x00000002 */
+#define RCC_APB1ENR_TIM3EN                 RCC_APB1ENR_TIM3EN_Msk              
+#define RCC_APB1ENR_TIM4EN_Pos             (2U)                                
+#define RCC_APB1ENR_TIM4EN_Msk             (0x1UL << RCC_APB1ENR_TIM4EN_Pos)    /*!< 0x00000004 */
+#define RCC_APB1ENR_TIM4EN                 RCC_APB1ENR_TIM4EN_Msk              
+#define RCC_APB1ENR_TIM5EN_Pos             (3U)                                
+#define RCC_APB1ENR_TIM5EN_Msk             (0x1UL << RCC_APB1ENR_TIM5EN_Pos)    /*!< 0x00000008 */
+#define RCC_APB1ENR_TIM5EN                 RCC_APB1ENR_TIM5EN_Msk              
+#define RCC_APB1ENR_TIM6EN_Pos             (4U)                                
+#define RCC_APB1ENR_TIM6EN_Msk             (0x1UL << RCC_APB1ENR_TIM6EN_Pos)    /*!< 0x00000010 */
+#define RCC_APB1ENR_TIM6EN                 RCC_APB1ENR_TIM6EN_Msk              
+#define RCC_APB1ENR_TIM7EN_Pos             (5U)                                
+#define RCC_APB1ENR_TIM7EN_Msk             (0x1UL << RCC_APB1ENR_TIM7EN_Pos)    /*!< 0x00000020 */
+#define RCC_APB1ENR_TIM7EN                 RCC_APB1ENR_TIM7EN_Msk              
+#define RCC_APB1ENR_TIM12EN_Pos            (6U)                                
+#define RCC_APB1ENR_TIM12EN_Msk            (0x1UL << RCC_APB1ENR_TIM12EN_Pos)   /*!< 0x00000040 */
+#define RCC_APB1ENR_TIM12EN                RCC_APB1ENR_TIM12EN_Msk             
+#define RCC_APB1ENR_TIM13EN_Pos            (7U)                                
+#define RCC_APB1ENR_TIM13EN_Msk            (0x1UL << RCC_APB1ENR_TIM13EN_Pos)   /*!< 0x00000080 */
+#define RCC_APB1ENR_TIM13EN                RCC_APB1ENR_TIM13EN_Msk             
+#define RCC_APB1ENR_TIM14EN_Pos            (8U)                                
+#define RCC_APB1ENR_TIM14EN_Msk            (0x1UL << RCC_APB1ENR_TIM14EN_Pos)   /*!< 0x00000100 */
+#define RCC_APB1ENR_TIM14EN                RCC_APB1ENR_TIM14EN_Msk             
+#define RCC_APB1ENR_WWDGEN_Pos             (11U)                               
+#define RCC_APB1ENR_WWDGEN_Msk             (0x1UL << RCC_APB1ENR_WWDGEN_Pos)    /*!< 0x00000800 */
+#define RCC_APB1ENR_WWDGEN                 RCC_APB1ENR_WWDGEN_Msk              
+#define RCC_APB1ENR_SPI2EN_Pos             (14U)                               
+#define RCC_APB1ENR_SPI2EN_Msk             (0x1UL << RCC_APB1ENR_SPI2EN_Pos)    /*!< 0x00004000 */
+#define RCC_APB1ENR_SPI2EN                 RCC_APB1ENR_SPI2EN_Msk              
+#define RCC_APB1ENR_SPI3EN_Pos             (15U)                               
+#define RCC_APB1ENR_SPI3EN_Msk             (0x1UL << RCC_APB1ENR_SPI3EN_Pos)    /*!< 0x00008000 */
+#define RCC_APB1ENR_SPI3EN                 RCC_APB1ENR_SPI3EN_Msk              
+#define RCC_APB1ENR_USART2EN_Pos           (17U)                               
+#define RCC_APB1ENR_USART2EN_Msk           (0x1UL << RCC_APB1ENR_USART2EN_Pos)  /*!< 0x00020000 */
+#define RCC_APB1ENR_USART2EN               RCC_APB1ENR_USART2EN_Msk            
+#define RCC_APB1ENR_USART3EN_Pos           (18U)                               
+#define RCC_APB1ENR_USART3EN_Msk           (0x1UL << RCC_APB1ENR_USART3EN_Pos)  /*!< 0x00040000 */
+#define RCC_APB1ENR_USART3EN               RCC_APB1ENR_USART3EN_Msk            
+#define RCC_APB1ENR_UART4EN_Pos            (19U)                               
+#define RCC_APB1ENR_UART4EN_Msk            (0x1UL << RCC_APB1ENR_UART4EN_Pos)   /*!< 0x00080000 */
+#define RCC_APB1ENR_UART4EN                RCC_APB1ENR_UART4EN_Msk             
+#define RCC_APB1ENR_UART5EN_Pos            (20U)                               
+#define RCC_APB1ENR_UART5EN_Msk            (0x1UL << RCC_APB1ENR_UART5EN_Pos)   /*!< 0x00100000 */
+#define RCC_APB1ENR_UART5EN                RCC_APB1ENR_UART5EN_Msk             
+#define RCC_APB1ENR_I2C1EN_Pos             (21U)                               
+#define RCC_APB1ENR_I2C1EN_Msk             (0x1UL << RCC_APB1ENR_I2C1EN_Pos)    /*!< 0x00200000 */
+#define RCC_APB1ENR_I2C1EN                 RCC_APB1ENR_I2C1EN_Msk              
+#define RCC_APB1ENR_I2C2EN_Pos             (22U)                               
+#define RCC_APB1ENR_I2C2EN_Msk             (0x1UL << RCC_APB1ENR_I2C2EN_Pos)    /*!< 0x00400000 */
+#define RCC_APB1ENR_I2C2EN                 RCC_APB1ENR_I2C2EN_Msk              
+#define RCC_APB1ENR_I2C3EN_Pos             (23U)                               
+#define RCC_APB1ENR_I2C3EN_Msk             (0x1UL << RCC_APB1ENR_I2C3EN_Pos)    /*!< 0x00800000 */
+#define RCC_APB1ENR_I2C3EN                 RCC_APB1ENR_I2C3EN_Msk              
+#define RCC_APB1ENR_CAN1EN_Pos             (25U)                               
+#define RCC_APB1ENR_CAN1EN_Msk             (0x1UL << RCC_APB1ENR_CAN1EN_Pos)    /*!< 0x02000000 */
+#define RCC_APB1ENR_CAN1EN                 RCC_APB1ENR_CAN1EN_Msk              
+#define RCC_APB1ENR_CAN2EN_Pos             (26U)                               
+#define RCC_APB1ENR_CAN2EN_Msk             (0x1UL << RCC_APB1ENR_CAN2EN_Pos)    /*!< 0x04000000 */
+#define RCC_APB1ENR_CAN2EN                 RCC_APB1ENR_CAN2EN_Msk              
+#define RCC_APB1ENR_PWREN_Pos              (28U)                               
+#define RCC_APB1ENR_PWREN_Msk              (0x1UL << RCC_APB1ENR_PWREN_Pos)     /*!< 0x10000000 */
+#define RCC_APB1ENR_PWREN                  RCC_APB1ENR_PWREN_Msk               
+#define RCC_APB1ENR_DACEN_Pos              (29U)                               
+#define RCC_APB1ENR_DACEN_Msk              (0x1UL << RCC_APB1ENR_DACEN_Pos)     /*!< 0x20000000 */
+#define RCC_APB1ENR_DACEN                  RCC_APB1ENR_DACEN_Msk               
+#define RCC_APB1ENR_UART7EN_Pos            (30U)                               
+#define RCC_APB1ENR_UART7EN_Msk            (0x1UL << RCC_APB1ENR_UART7EN_Pos)   /*!< 0x40000000 */
+#define RCC_APB1ENR_UART7EN                RCC_APB1ENR_UART7EN_Msk             
+#define RCC_APB1ENR_UART8EN_Pos            (31U)                               
+#define RCC_APB1ENR_UART8EN_Msk            (0x1UL << RCC_APB1ENR_UART8EN_Pos)   /*!< 0x80000000 */
+#define RCC_APB1ENR_UART8EN                RCC_APB1ENR_UART8EN_Msk             
+
+/********************  Bit definition for RCC_APB2ENR register  ***************/
+#define RCC_APB2ENR_TIM1EN_Pos             (0U)                                
+#define RCC_APB2ENR_TIM1EN_Msk             (0x1UL << RCC_APB2ENR_TIM1EN_Pos)    /*!< 0x00000001 */
+#define RCC_APB2ENR_TIM1EN                 RCC_APB2ENR_TIM1EN_Msk              
+#define RCC_APB2ENR_TIM8EN_Pos             (1U)                                
+#define RCC_APB2ENR_TIM8EN_Msk             (0x1UL << RCC_APB2ENR_TIM8EN_Pos)    /*!< 0x00000002 */
+#define RCC_APB2ENR_TIM8EN                 RCC_APB2ENR_TIM8EN_Msk              
+#define RCC_APB2ENR_USART1EN_Pos           (4U)                                
+#define RCC_APB2ENR_USART1EN_Msk           (0x1UL << RCC_APB2ENR_USART1EN_Pos)  /*!< 0x00000010 */
+#define RCC_APB2ENR_USART1EN               RCC_APB2ENR_USART1EN_Msk            
+#define RCC_APB2ENR_USART6EN_Pos           (5U)                                
+#define RCC_APB2ENR_USART6EN_Msk           (0x1UL << RCC_APB2ENR_USART6EN_Pos)  /*!< 0x00000020 */
+#define RCC_APB2ENR_USART6EN               RCC_APB2ENR_USART6EN_Msk            
+#define RCC_APB2ENR_ADC1EN_Pos             (8U)                                
+#define RCC_APB2ENR_ADC1EN_Msk             (0x1UL << RCC_APB2ENR_ADC1EN_Pos)    /*!< 0x00000100 */
+#define RCC_APB2ENR_ADC1EN                 RCC_APB2ENR_ADC1EN_Msk              
+#define RCC_APB2ENR_ADC2EN_Pos             (9U)                                
+#define RCC_APB2ENR_ADC2EN_Msk             (0x1UL << RCC_APB2ENR_ADC2EN_Pos)    /*!< 0x00000200 */
+#define RCC_APB2ENR_ADC2EN                 RCC_APB2ENR_ADC2EN_Msk              
+#define RCC_APB2ENR_ADC3EN_Pos             (10U)                               
+#define RCC_APB2ENR_ADC3EN_Msk             (0x1UL << RCC_APB2ENR_ADC3EN_Pos)    /*!< 0x00000400 */
+#define RCC_APB2ENR_ADC3EN                 RCC_APB2ENR_ADC3EN_Msk              
+#define RCC_APB2ENR_SDIOEN_Pos             (11U)                               
+#define RCC_APB2ENR_SDIOEN_Msk             (0x1UL << RCC_APB2ENR_SDIOEN_Pos)    /*!< 0x00000800 */
+#define RCC_APB2ENR_SDIOEN                 RCC_APB2ENR_SDIOEN_Msk              
+#define RCC_APB2ENR_SPI1EN_Pos             (12U)                               
+#define RCC_APB2ENR_SPI1EN_Msk             (0x1UL << RCC_APB2ENR_SPI1EN_Pos)    /*!< 0x00001000 */
+#define RCC_APB2ENR_SPI1EN                 RCC_APB2ENR_SPI1EN_Msk              
+#define RCC_APB2ENR_SPI4EN_Pos             (13U)                               
+#define RCC_APB2ENR_SPI4EN_Msk             (0x1UL << RCC_APB2ENR_SPI4EN_Pos)    /*!< 0x00002000 */
+#define RCC_APB2ENR_SPI4EN                 RCC_APB2ENR_SPI4EN_Msk              
+#define RCC_APB2ENR_SYSCFGEN_Pos           (14U)                               
+#define RCC_APB2ENR_SYSCFGEN_Msk           (0x1UL << RCC_APB2ENR_SYSCFGEN_Pos)  /*!< 0x00004000 */
+#define RCC_APB2ENR_SYSCFGEN               RCC_APB2ENR_SYSCFGEN_Msk            
+#define RCC_APB2ENR_TIM9EN_Pos             (16U)                               
+#define RCC_APB2ENR_TIM9EN_Msk             (0x1UL << RCC_APB2ENR_TIM9EN_Pos)    /*!< 0x00010000 */
+#define RCC_APB2ENR_TIM9EN                 RCC_APB2ENR_TIM9EN_Msk              
+#define RCC_APB2ENR_TIM10EN_Pos            (17U)                               
+#define RCC_APB2ENR_TIM10EN_Msk            (0x1UL << RCC_APB2ENR_TIM10EN_Pos)   /*!< 0x00020000 */
+#define RCC_APB2ENR_TIM10EN                RCC_APB2ENR_TIM10EN_Msk             
+#define RCC_APB2ENR_TIM11EN_Pos            (18U)                               
+#define RCC_APB2ENR_TIM11EN_Msk            (0x1UL << RCC_APB2ENR_TIM11EN_Pos)   /*!< 0x00040000 */
+#define RCC_APB2ENR_TIM11EN                RCC_APB2ENR_TIM11EN_Msk             
+#define RCC_APB2ENR_SPI5EN_Pos             (20U)                               
+#define RCC_APB2ENR_SPI5EN_Msk             (0x1UL << RCC_APB2ENR_SPI5EN_Pos)    /*!< 0x00100000 */
+#define RCC_APB2ENR_SPI5EN                 RCC_APB2ENR_SPI5EN_Msk              
+#define RCC_APB2ENR_SPI6EN_Pos             (21U)                               
+#define RCC_APB2ENR_SPI6EN_Msk             (0x1UL << RCC_APB2ENR_SPI6EN_Pos)    /*!< 0x00200000 */
+#define RCC_APB2ENR_SPI6EN                 RCC_APB2ENR_SPI6EN_Msk              
+#define RCC_APB2ENR_SAI1EN_Pos             (22U)                               
+#define RCC_APB2ENR_SAI1EN_Msk             (0x1UL << RCC_APB2ENR_SAI1EN_Pos)    /*!< 0x00400000 */
+#define RCC_APB2ENR_SAI1EN                 RCC_APB2ENR_SAI1EN_Msk              
+#define RCC_APB2ENR_LTDCEN_Pos             (26U)                               
+#define RCC_APB2ENR_LTDCEN_Msk             (0x1UL << RCC_APB2ENR_LTDCEN_Pos)    /*!< 0x04000000 */
+#define RCC_APB2ENR_LTDCEN                 RCC_APB2ENR_LTDCEN_Msk              
+#define RCC_APB2ENR_DSIEN_Pos              (27U)                               
+#define RCC_APB2ENR_DSIEN_Msk              (0x1UL << RCC_APB2ENR_DSIEN_Pos)     /*!< 0x08000000 */
+#define RCC_APB2ENR_DSIEN                  RCC_APB2ENR_DSIEN_Msk               
+
+/********************  Bit definition for RCC_AHB1LPENR register  *************/
+#define RCC_AHB1LPENR_GPIOALPEN_Pos        (0U)                                
+#define RCC_AHB1LPENR_GPIOALPEN_Msk        (0x1UL << RCC_AHB1LPENR_GPIOALPEN_Pos) /*!< 0x00000001 */
+#define RCC_AHB1LPENR_GPIOALPEN            RCC_AHB1LPENR_GPIOALPEN_Msk         
+#define RCC_AHB1LPENR_GPIOBLPEN_Pos        (1U)                                
+#define RCC_AHB1LPENR_GPIOBLPEN_Msk        (0x1UL << RCC_AHB1LPENR_GPIOBLPEN_Pos) /*!< 0x00000002 */
+#define RCC_AHB1LPENR_GPIOBLPEN            RCC_AHB1LPENR_GPIOBLPEN_Msk         
+#define RCC_AHB1LPENR_GPIOCLPEN_Pos        (2U)                                
+#define RCC_AHB1LPENR_GPIOCLPEN_Msk        (0x1UL << RCC_AHB1LPENR_GPIOCLPEN_Pos) /*!< 0x00000004 */
+#define RCC_AHB1LPENR_GPIOCLPEN            RCC_AHB1LPENR_GPIOCLPEN_Msk         
+#define RCC_AHB1LPENR_GPIODLPEN_Pos        (3U)                                
+#define RCC_AHB1LPENR_GPIODLPEN_Msk        (0x1UL << RCC_AHB1LPENR_GPIODLPEN_Pos) /*!< 0x00000008 */
+#define RCC_AHB1LPENR_GPIODLPEN            RCC_AHB1LPENR_GPIODLPEN_Msk         
+#define RCC_AHB1LPENR_GPIOELPEN_Pos        (4U)                                
+#define RCC_AHB1LPENR_GPIOELPEN_Msk        (0x1UL << RCC_AHB1LPENR_GPIOELPEN_Pos) /*!< 0x00000010 */
+#define RCC_AHB1LPENR_GPIOELPEN            RCC_AHB1LPENR_GPIOELPEN_Msk         
+#define RCC_AHB1LPENR_GPIOFLPEN_Pos        (5U)                                
+#define RCC_AHB1LPENR_GPIOFLPEN_Msk        (0x1UL << RCC_AHB1LPENR_GPIOFLPEN_Pos) /*!< 0x00000020 */
+#define RCC_AHB1LPENR_GPIOFLPEN            RCC_AHB1LPENR_GPIOFLPEN_Msk         
+#define RCC_AHB1LPENR_GPIOGLPEN_Pos        (6U)                                
+#define RCC_AHB1LPENR_GPIOGLPEN_Msk        (0x1UL << RCC_AHB1LPENR_GPIOGLPEN_Pos) /*!< 0x00000040 */
+#define RCC_AHB1LPENR_GPIOGLPEN            RCC_AHB1LPENR_GPIOGLPEN_Msk         
+#define RCC_AHB1LPENR_GPIOHLPEN_Pos        (7U)                                
+#define RCC_AHB1LPENR_GPIOHLPEN_Msk        (0x1UL << RCC_AHB1LPENR_GPIOHLPEN_Pos) /*!< 0x00000080 */
+#define RCC_AHB1LPENR_GPIOHLPEN            RCC_AHB1LPENR_GPIOHLPEN_Msk         
+#define RCC_AHB1LPENR_GPIOILPEN_Pos        (8U)                                
+#define RCC_AHB1LPENR_GPIOILPEN_Msk        (0x1UL << RCC_AHB1LPENR_GPIOILPEN_Pos) /*!< 0x00000100 */
+#define RCC_AHB1LPENR_GPIOILPEN            RCC_AHB1LPENR_GPIOILPEN_Msk         
+#define RCC_AHB1LPENR_GPIOJLPEN_Pos        (9U)                                
+#define RCC_AHB1LPENR_GPIOJLPEN_Msk        (0x1UL << RCC_AHB1LPENR_GPIOJLPEN_Pos) /*!< 0x00000200 */
+#define RCC_AHB1LPENR_GPIOJLPEN            RCC_AHB1LPENR_GPIOJLPEN_Msk         
+#define RCC_AHB1LPENR_GPIOKLPEN_Pos        (10U)                               
+#define RCC_AHB1LPENR_GPIOKLPEN_Msk        (0x1UL << RCC_AHB1LPENR_GPIOKLPEN_Pos) /*!< 0x00000400 */
+#define RCC_AHB1LPENR_GPIOKLPEN            RCC_AHB1LPENR_GPIOKLPEN_Msk         
+#define RCC_AHB1LPENR_CRCLPEN_Pos          (12U)                               
+#define RCC_AHB1LPENR_CRCLPEN_Msk          (0x1UL << RCC_AHB1LPENR_CRCLPEN_Pos) /*!< 0x00001000 */
+#define RCC_AHB1LPENR_CRCLPEN              RCC_AHB1LPENR_CRCLPEN_Msk           
+#define RCC_AHB1LPENR_FLITFLPEN_Pos        (15U)                               
+#define RCC_AHB1LPENR_FLITFLPEN_Msk        (0x1UL << RCC_AHB1LPENR_FLITFLPEN_Pos) /*!< 0x00008000 */
+#define RCC_AHB1LPENR_FLITFLPEN            RCC_AHB1LPENR_FLITFLPEN_Msk         
+#define RCC_AHB1LPENR_SRAM1LPEN_Pos        (16U)                               
+#define RCC_AHB1LPENR_SRAM1LPEN_Msk        (0x1UL << RCC_AHB1LPENR_SRAM1LPEN_Pos) /*!< 0x00010000 */
+#define RCC_AHB1LPENR_SRAM1LPEN            RCC_AHB1LPENR_SRAM1LPEN_Msk         
+#define RCC_AHB1LPENR_SRAM2LPEN_Pos        (17U)                               
+#define RCC_AHB1LPENR_SRAM2LPEN_Msk        (0x1UL << RCC_AHB1LPENR_SRAM2LPEN_Pos) /*!< 0x00020000 */
+#define RCC_AHB1LPENR_SRAM2LPEN            RCC_AHB1LPENR_SRAM2LPEN_Msk         
+#define RCC_AHB1LPENR_BKPSRAMLPEN_Pos      (18U)                               
+#define RCC_AHB1LPENR_BKPSRAMLPEN_Msk      (0x1UL << RCC_AHB1LPENR_BKPSRAMLPEN_Pos) /*!< 0x00040000 */
+#define RCC_AHB1LPENR_BKPSRAMLPEN          RCC_AHB1LPENR_BKPSRAMLPEN_Msk       
+#define RCC_AHB1LPENR_SRAM3LPEN_Pos        (19U)                               
+#define RCC_AHB1LPENR_SRAM3LPEN_Msk        (0x1UL << RCC_AHB1LPENR_SRAM3LPEN_Pos) /*!< 0x00080000 */
+#define RCC_AHB1LPENR_SRAM3LPEN            RCC_AHB1LPENR_SRAM3LPEN_Msk         
+#define RCC_AHB1LPENR_DMA1LPEN_Pos         (21U)                               
+#define RCC_AHB1LPENR_DMA1LPEN_Msk         (0x1UL << RCC_AHB1LPENR_DMA1LPEN_Pos) /*!< 0x00200000 */
+#define RCC_AHB1LPENR_DMA1LPEN             RCC_AHB1LPENR_DMA1LPEN_Msk          
+#define RCC_AHB1LPENR_DMA2LPEN_Pos         (22U)                               
+#define RCC_AHB1LPENR_DMA2LPEN_Msk         (0x1UL << RCC_AHB1LPENR_DMA2LPEN_Pos) /*!< 0x00400000 */
+#define RCC_AHB1LPENR_DMA2LPEN             RCC_AHB1LPENR_DMA2LPEN_Msk          
+#define RCC_AHB1LPENR_DMA2DLPEN_Pos        (23U)                               
+#define RCC_AHB1LPENR_DMA2DLPEN_Msk        (0x1UL << RCC_AHB1LPENR_DMA2DLPEN_Pos) /*!< 0x00800000 */
+#define RCC_AHB1LPENR_DMA2DLPEN            RCC_AHB1LPENR_DMA2DLPEN_Msk         
+
+#define RCC_AHB1LPENR_ETHMACLPEN_Pos       (25U)                               
+#define RCC_AHB1LPENR_ETHMACLPEN_Msk       (0x1UL << RCC_AHB1LPENR_ETHMACLPEN_Pos) /*!< 0x02000000 */
+#define RCC_AHB1LPENR_ETHMACLPEN           RCC_AHB1LPENR_ETHMACLPEN_Msk        
+#define RCC_AHB1LPENR_ETHMACTXLPEN_Pos     (26U)                               
+#define RCC_AHB1LPENR_ETHMACTXLPEN_Msk     (0x1UL << RCC_AHB1LPENR_ETHMACTXLPEN_Pos) /*!< 0x04000000 */
+#define RCC_AHB1LPENR_ETHMACTXLPEN         RCC_AHB1LPENR_ETHMACTXLPEN_Msk      
+#define RCC_AHB1LPENR_ETHMACRXLPEN_Pos     (27U)                               
+#define RCC_AHB1LPENR_ETHMACRXLPEN_Msk     (0x1UL << RCC_AHB1LPENR_ETHMACRXLPEN_Pos) /*!< 0x08000000 */
+#define RCC_AHB1LPENR_ETHMACRXLPEN         RCC_AHB1LPENR_ETHMACRXLPEN_Msk      
+#define RCC_AHB1LPENR_ETHMACPTPLPEN_Pos    (28U)                               
+#define RCC_AHB1LPENR_ETHMACPTPLPEN_Msk    (0x1UL << RCC_AHB1LPENR_ETHMACPTPLPEN_Pos) /*!< 0x10000000 */
+#define RCC_AHB1LPENR_ETHMACPTPLPEN        RCC_AHB1LPENR_ETHMACPTPLPEN_Msk     
+#define RCC_AHB1LPENR_OTGHSLPEN_Pos        (29U)                               
+#define RCC_AHB1LPENR_OTGHSLPEN_Msk        (0x1UL << RCC_AHB1LPENR_OTGHSLPEN_Pos) /*!< 0x20000000 */
+#define RCC_AHB1LPENR_OTGHSLPEN            RCC_AHB1LPENR_OTGHSLPEN_Msk         
+#define RCC_AHB1LPENR_OTGHSULPILPEN_Pos    (30U)                               
+#define RCC_AHB1LPENR_OTGHSULPILPEN_Msk    (0x1UL << RCC_AHB1LPENR_OTGHSULPILPEN_Pos) /*!< 0x40000000 */
+#define RCC_AHB1LPENR_OTGHSULPILPEN        RCC_AHB1LPENR_OTGHSULPILPEN_Msk     
+
+/********************  Bit definition for RCC_AHB2LPENR register  *************/
+#define RCC_AHB2LPENR_DCMILPEN_Pos         (0U)                                
+#define RCC_AHB2LPENR_DCMILPEN_Msk         (0x1UL << RCC_AHB2LPENR_DCMILPEN_Pos) /*!< 0x00000001 */
+#define RCC_AHB2LPENR_DCMILPEN             RCC_AHB2LPENR_DCMILPEN_Msk          
+#define RCC_AHB2LPENR_RNGLPEN_Pos          (6U)                                
+#define RCC_AHB2LPENR_RNGLPEN_Msk          (0x1UL << RCC_AHB2LPENR_RNGLPEN_Pos) /*!< 0x00000040 */
+#define RCC_AHB2LPENR_RNGLPEN              RCC_AHB2LPENR_RNGLPEN_Msk           
+#define RCC_AHB2LPENR_OTGFSLPEN_Pos        (7U)                                
+#define RCC_AHB2LPENR_OTGFSLPEN_Msk        (0x1UL << RCC_AHB2LPENR_OTGFSLPEN_Pos) /*!< 0x00000080 */
+#define RCC_AHB2LPENR_OTGFSLPEN            RCC_AHB2LPENR_OTGFSLPEN_Msk         
+
+/********************  Bit definition for RCC_AHB3LPENR register  *************/
+#define RCC_AHB3LPENR_FMCLPEN_Pos          (0U)                                
+#define RCC_AHB3LPENR_FMCLPEN_Msk          (0x1UL << RCC_AHB3LPENR_FMCLPEN_Pos) /*!< 0x00000001 */
+#define RCC_AHB3LPENR_FMCLPEN              RCC_AHB3LPENR_FMCLPEN_Msk           
+#define RCC_AHB3LPENR_QSPILPEN_Pos         (1U)                                
+#define RCC_AHB3LPENR_QSPILPEN_Msk         (0x1UL << RCC_AHB3LPENR_QSPILPEN_Pos) /*!< 0x00000002 */
+#define RCC_AHB3LPENR_QSPILPEN             RCC_AHB3LPENR_QSPILPEN_Msk          
+
+/********************  Bit definition for RCC_APB1LPENR register  *************/
+#define RCC_APB1LPENR_TIM2LPEN_Pos         (0U)                                
+#define RCC_APB1LPENR_TIM2LPEN_Msk         (0x1UL << RCC_APB1LPENR_TIM2LPEN_Pos) /*!< 0x00000001 */
+#define RCC_APB1LPENR_TIM2LPEN             RCC_APB1LPENR_TIM2LPEN_Msk          
+#define RCC_APB1LPENR_TIM3LPEN_Pos         (1U)                                
+#define RCC_APB1LPENR_TIM3LPEN_Msk         (0x1UL << RCC_APB1LPENR_TIM3LPEN_Pos) /*!< 0x00000002 */
+#define RCC_APB1LPENR_TIM3LPEN             RCC_APB1LPENR_TIM3LPEN_Msk          
+#define RCC_APB1LPENR_TIM4LPEN_Pos         (2U)                                
+#define RCC_APB1LPENR_TIM4LPEN_Msk         (0x1UL << RCC_APB1LPENR_TIM4LPEN_Pos) /*!< 0x00000004 */
+#define RCC_APB1LPENR_TIM4LPEN             RCC_APB1LPENR_TIM4LPEN_Msk          
+#define RCC_APB1LPENR_TIM5LPEN_Pos         (3U)                                
+#define RCC_APB1LPENR_TIM5LPEN_Msk         (0x1UL << RCC_APB1LPENR_TIM5LPEN_Pos) /*!< 0x00000008 */
+#define RCC_APB1LPENR_TIM5LPEN             RCC_APB1LPENR_TIM5LPEN_Msk          
+#define RCC_APB1LPENR_TIM6LPEN_Pos         (4U)                                
+#define RCC_APB1LPENR_TIM6LPEN_Msk         (0x1UL << RCC_APB1LPENR_TIM6LPEN_Pos) /*!< 0x00000010 */
+#define RCC_APB1LPENR_TIM6LPEN             RCC_APB1LPENR_TIM6LPEN_Msk          
+#define RCC_APB1LPENR_TIM7LPEN_Pos         (5U)                                
+#define RCC_APB1LPENR_TIM7LPEN_Msk         (0x1UL << RCC_APB1LPENR_TIM7LPEN_Pos) /*!< 0x00000020 */
+#define RCC_APB1LPENR_TIM7LPEN             RCC_APB1LPENR_TIM7LPEN_Msk          
+#define RCC_APB1LPENR_TIM12LPEN_Pos        (6U)                                
+#define RCC_APB1LPENR_TIM12LPEN_Msk        (0x1UL << RCC_APB1LPENR_TIM12LPEN_Pos) /*!< 0x00000040 */
+#define RCC_APB1LPENR_TIM12LPEN            RCC_APB1LPENR_TIM12LPEN_Msk         
+#define RCC_APB1LPENR_TIM13LPEN_Pos        (7U)                                
+#define RCC_APB1LPENR_TIM13LPEN_Msk        (0x1UL << RCC_APB1LPENR_TIM13LPEN_Pos) /*!< 0x00000080 */
+#define RCC_APB1LPENR_TIM13LPEN            RCC_APB1LPENR_TIM13LPEN_Msk         
+#define RCC_APB1LPENR_TIM14LPEN_Pos        (8U)                                
+#define RCC_APB1LPENR_TIM14LPEN_Msk        (0x1UL << RCC_APB1LPENR_TIM14LPEN_Pos) /*!< 0x00000100 */
+#define RCC_APB1LPENR_TIM14LPEN            RCC_APB1LPENR_TIM14LPEN_Msk         
+#define RCC_APB1LPENR_WWDGLPEN_Pos         (11U)                               
+#define RCC_APB1LPENR_WWDGLPEN_Msk         (0x1UL << RCC_APB1LPENR_WWDGLPEN_Pos) /*!< 0x00000800 */
+#define RCC_APB1LPENR_WWDGLPEN             RCC_APB1LPENR_WWDGLPEN_Msk          
+#define RCC_APB1LPENR_SPI2LPEN_Pos         (14U)                               
+#define RCC_APB1LPENR_SPI2LPEN_Msk         (0x1UL << RCC_APB1LPENR_SPI2LPEN_Pos) /*!< 0x00004000 */
+#define RCC_APB1LPENR_SPI2LPEN             RCC_APB1LPENR_SPI2LPEN_Msk          
+#define RCC_APB1LPENR_SPI3LPEN_Pos         (15U)                               
+#define RCC_APB1LPENR_SPI3LPEN_Msk         (0x1UL << RCC_APB1LPENR_SPI3LPEN_Pos) /*!< 0x00008000 */
+#define RCC_APB1LPENR_SPI3LPEN             RCC_APB1LPENR_SPI3LPEN_Msk          
+#define RCC_APB1LPENR_USART2LPEN_Pos       (17U)                               
+#define RCC_APB1LPENR_USART2LPEN_Msk       (0x1UL << RCC_APB1LPENR_USART2LPEN_Pos) /*!< 0x00020000 */
+#define RCC_APB1LPENR_USART2LPEN           RCC_APB1LPENR_USART2LPEN_Msk        
+#define RCC_APB1LPENR_USART3LPEN_Pos       (18U)                               
+#define RCC_APB1LPENR_USART3LPEN_Msk       (0x1UL << RCC_APB1LPENR_USART3LPEN_Pos) /*!< 0x00040000 */
+#define RCC_APB1LPENR_USART3LPEN           RCC_APB1LPENR_USART3LPEN_Msk        
+#define RCC_APB1LPENR_UART4LPEN_Pos        (19U)                               
+#define RCC_APB1LPENR_UART4LPEN_Msk        (0x1UL << RCC_APB1LPENR_UART4LPEN_Pos) /*!< 0x00080000 */
+#define RCC_APB1LPENR_UART4LPEN            RCC_APB1LPENR_UART4LPEN_Msk         
+#define RCC_APB1LPENR_UART5LPEN_Pos        (20U)                               
+#define RCC_APB1LPENR_UART5LPEN_Msk        (0x1UL << RCC_APB1LPENR_UART5LPEN_Pos) /*!< 0x00100000 */
+#define RCC_APB1LPENR_UART5LPEN            RCC_APB1LPENR_UART5LPEN_Msk         
+#define RCC_APB1LPENR_I2C1LPEN_Pos         (21U)                               
+#define RCC_APB1LPENR_I2C1LPEN_Msk         (0x1UL << RCC_APB1LPENR_I2C1LPEN_Pos) /*!< 0x00200000 */
+#define RCC_APB1LPENR_I2C1LPEN             RCC_APB1LPENR_I2C1LPEN_Msk          
+#define RCC_APB1LPENR_I2C2LPEN_Pos         (22U)                               
+#define RCC_APB1LPENR_I2C2LPEN_Msk         (0x1UL << RCC_APB1LPENR_I2C2LPEN_Pos) /*!< 0x00400000 */
+#define RCC_APB1LPENR_I2C2LPEN             RCC_APB1LPENR_I2C2LPEN_Msk          
+#define RCC_APB1LPENR_I2C3LPEN_Pos         (23U)                               
+#define RCC_APB1LPENR_I2C3LPEN_Msk         (0x1UL << RCC_APB1LPENR_I2C3LPEN_Pos) /*!< 0x00800000 */
+#define RCC_APB1LPENR_I2C3LPEN             RCC_APB1LPENR_I2C3LPEN_Msk          
+#define RCC_APB1LPENR_CAN1LPEN_Pos         (25U)                               
+#define RCC_APB1LPENR_CAN1LPEN_Msk         (0x1UL << RCC_APB1LPENR_CAN1LPEN_Pos) /*!< 0x02000000 */
+#define RCC_APB1LPENR_CAN1LPEN             RCC_APB1LPENR_CAN1LPEN_Msk          
+#define RCC_APB1LPENR_CAN2LPEN_Pos         (26U)                               
+#define RCC_APB1LPENR_CAN2LPEN_Msk         (0x1UL << RCC_APB1LPENR_CAN2LPEN_Pos) /*!< 0x04000000 */
+#define RCC_APB1LPENR_CAN2LPEN             RCC_APB1LPENR_CAN2LPEN_Msk          
+#define RCC_APB1LPENR_PWRLPEN_Pos          (28U)                               
+#define RCC_APB1LPENR_PWRLPEN_Msk          (0x1UL << RCC_APB1LPENR_PWRLPEN_Pos) /*!< 0x10000000 */
+#define RCC_APB1LPENR_PWRLPEN              RCC_APB1LPENR_PWRLPEN_Msk           
+#define RCC_APB1LPENR_DACLPEN_Pos          (29U)                               
+#define RCC_APB1LPENR_DACLPEN_Msk          (0x1UL << RCC_APB1LPENR_DACLPEN_Pos) /*!< 0x20000000 */
+#define RCC_APB1LPENR_DACLPEN              RCC_APB1LPENR_DACLPEN_Msk           
+#define RCC_APB1LPENR_UART7LPEN_Pos        (30U)                               
+#define RCC_APB1LPENR_UART7LPEN_Msk        (0x1UL << RCC_APB1LPENR_UART7LPEN_Pos) /*!< 0x40000000 */
+#define RCC_APB1LPENR_UART7LPEN            RCC_APB1LPENR_UART7LPEN_Msk         
+#define RCC_APB1LPENR_UART8LPEN_Pos        (31U)                               
+#define RCC_APB1LPENR_UART8LPEN_Msk        (0x1UL << RCC_APB1LPENR_UART8LPEN_Pos) /*!< 0x80000000 */
+#define RCC_APB1LPENR_UART8LPEN            RCC_APB1LPENR_UART8LPEN_Msk         
+
+/********************  Bit definition for RCC_APB2LPENR register  *************/
+#define RCC_APB2LPENR_TIM1LPEN_Pos         (0U)                                
+#define RCC_APB2LPENR_TIM1LPEN_Msk         (0x1UL << RCC_APB2LPENR_TIM1LPEN_Pos) /*!< 0x00000001 */
+#define RCC_APB2LPENR_TIM1LPEN             RCC_APB2LPENR_TIM1LPEN_Msk          
+#define RCC_APB2LPENR_TIM8LPEN_Pos         (1U)                                
+#define RCC_APB2LPENR_TIM8LPEN_Msk         (0x1UL << RCC_APB2LPENR_TIM8LPEN_Pos) /*!< 0x00000002 */
+#define RCC_APB2LPENR_TIM8LPEN             RCC_APB2LPENR_TIM8LPEN_Msk          
+#define RCC_APB2LPENR_USART1LPEN_Pos       (4U)                                
+#define RCC_APB2LPENR_USART1LPEN_Msk       (0x1UL << RCC_APB2LPENR_USART1LPEN_Pos) /*!< 0x00000010 */
+#define RCC_APB2LPENR_USART1LPEN           RCC_APB2LPENR_USART1LPEN_Msk        
+#define RCC_APB2LPENR_USART6LPEN_Pos       (5U)                                
+#define RCC_APB2LPENR_USART6LPEN_Msk       (0x1UL << RCC_APB2LPENR_USART6LPEN_Pos) /*!< 0x00000020 */
+#define RCC_APB2LPENR_USART6LPEN           RCC_APB2LPENR_USART6LPEN_Msk        
+#define RCC_APB2LPENR_ADC1LPEN_Pos         (8U)                                
+#define RCC_APB2LPENR_ADC1LPEN_Msk         (0x1UL << RCC_APB2LPENR_ADC1LPEN_Pos) /*!< 0x00000100 */
+#define RCC_APB2LPENR_ADC1LPEN             RCC_APB2LPENR_ADC1LPEN_Msk          
+#define RCC_APB2LPENR_ADC2LPEN_Pos         (9U)                                
+#define RCC_APB2LPENR_ADC2LPEN_Msk         (0x1UL << RCC_APB2LPENR_ADC2LPEN_Pos) /*!< 0x00000200 */
+#define RCC_APB2LPENR_ADC2LPEN             RCC_APB2LPENR_ADC2LPEN_Msk          
+#define RCC_APB2LPENR_ADC3LPEN_Pos         (10U)                               
+#define RCC_APB2LPENR_ADC3LPEN_Msk         (0x1UL << RCC_APB2LPENR_ADC3LPEN_Pos) /*!< 0x00000400 */
+#define RCC_APB2LPENR_ADC3LPEN             RCC_APB2LPENR_ADC3LPEN_Msk          
+#define RCC_APB2LPENR_SDIOLPEN_Pos         (11U)                               
+#define RCC_APB2LPENR_SDIOLPEN_Msk         (0x1UL << RCC_APB2LPENR_SDIOLPEN_Pos) /*!< 0x00000800 */
+#define RCC_APB2LPENR_SDIOLPEN             RCC_APB2LPENR_SDIOLPEN_Msk          
+#define RCC_APB2LPENR_SPI1LPEN_Pos         (12U)                               
+#define RCC_APB2LPENR_SPI1LPEN_Msk         (0x1UL << RCC_APB2LPENR_SPI1LPEN_Pos) /*!< 0x00001000 */
+#define RCC_APB2LPENR_SPI1LPEN             RCC_APB2LPENR_SPI1LPEN_Msk          
+#define RCC_APB2LPENR_SPI4LPEN_Pos         (13U)                               
+#define RCC_APB2LPENR_SPI4LPEN_Msk         (0x1UL << RCC_APB2LPENR_SPI4LPEN_Pos) /*!< 0x00002000 */
+#define RCC_APB2LPENR_SPI4LPEN             RCC_APB2LPENR_SPI4LPEN_Msk          
+#define RCC_APB2LPENR_SYSCFGLPEN_Pos       (14U)                               
+#define RCC_APB2LPENR_SYSCFGLPEN_Msk       (0x1UL << RCC_APB2LPENR_SYSCFGLPEN_Pos) /*!< 0x00004000 */
+#define RCC_APB2LPENR_SYSCFGLPEN           RCC_APB2LPENR_SYSCFGLPEN_Msk        
+#define RCC_APB2LPENR_TIM9LPEN_Pos         (16U)                               
+#define RCC_APB2LPENR_TIM9LPEN_Msk         (0x1UL << RCC_APB2LPENR_TIM9LPEN_Pos) /*!< 0x00010000 */
+#define RCC_APB2LPENR_TIM9LPEN             RCC_APB2LPENR_TIM9LPEN_Msk          
+#define RCC_APB2LPENR_TIM10LPEN_Pos        (17U)                               
+#define RCC_APB2LPENR_TIM10LPEN_Msk        (0x1UL << RCC_APB2LPENR_TIM10LPEN_Pos) /*!< 0x00020000 */
+#define RCC_APB2LPENR_TIM10LPEN            RCC_APB2LPENR_TIM10LPEN_Msk         
+#define RCC_APB2LPENR_TIM11LPEN_Pos        (18U)                               
+#define RCC_APB2LPENR_TIM11LPEN_Msk        (0x1UL << RCC_APB2LPENR_TIM11LPEN_Pos) /*!< 0x00040000 */
+#define RCC_APB2LPENR_TIM11LPEN            RCC_APB2LPENR_TIM11LPEN_Msk         
+#define RCC_APB2LPENR_SPI5LPEN_Pos         (20U)                               
+#define RCC_APB2LPENR_SPI5LPEN_Msk         (0x1UL << RCC_APB2LPENR_SPI5LPEN_Pos) /*!< 0x00100000 */
+#define RCC_APB2LPENR_SPI5LPEN             RCC_APB2LPENR_SPI5LPEN_Msk          
+#define RCC_APB2LPENR_SPI6LPEN_Pos         (21U)                               
+#define RCC_APB2LPENR_SPI6LPEN_Msk         (0x1UL << RCC_APB2LPENR_SPI6LPEN_Pos) /*!< 0x00200000 */
+#define RCC_APB2LPENR_SPI6LPEN             RCC_APB2LPENR_SPI6LPEN_Msk          
+#define RCC_APB2LPENR_SAI1LPEN_Pos         (22U)                               
+#define RCC_APB2LPENR_SAI1LPEN_Msk         (0x1UL << RCC_APB2LPENR_SAI1LPEN_Pos) /*!< 0x00400000 */
+#define RCC_APB2LPENR_SAI1LPEN             RCC_APB2LPENR_SAI1LPEN_Msk          
+#define RCC_APB2LPENR_LTDCLPEN_Pos         (26U)                               
+#define RCC_APB2LPENR_LTDCLPEN_Msk         (0x1UL << RCC_APB2LPENR_LTDCLPEN_Pos) /*!< 0x04000000 */
+#define RCC_APB2LPENR_LTDCLPEN             RCC_APB2LPENR_LTDCLPEN_Msk          
+#define RCC_APB2LPENR_DSILPEN_Pos          (27U)                               
+#define RCC_APB2LPENR_DSILPEN_Msk          (0x1UL << RCC_APB2LPENR_DSILPEN_Pos) /*!< 0x08000000 */
+#define RCC_APB2LPENR_DSILPEN              RCC_APB2LPENR_DSILPEN_Msk           
+
+/********************  Bit definition for RCC_BDCR register  ******************/
+#define RCC_BDCR_LSEON_Pos                 (0U)                                
+#define RCC_BDCR_LSEON_Msk                 (0x1UL << RCC_BDCR_LSEON_Pos)        /*!< 0x00000001 */
+#define RCC_BDCR_LSEON                     RCC_BDCR_LSEON_Msk                  
+#define RCC_BDCR_LSERDY_Pos                (1U)                                
+#define RCC_BDCR_LSERDY_Msk                (0x1UL << RCC_BDCR_LSERDY_Pos)       /*!< 0x00000002 */
+#define RCC_BDCR_LSERDY                    RCC_BDCR_LSERDY_Msk                 
+#define RCC_BDCR_LSEBYP_Pos                (2U)                                
+#define RCC_BDCR_LSEBYP_Msk                (0x1UL << RCC_BDCR_LSEBYP_Pos)       /*!< 0x00000004 */
+#define RCC_BDCR_LSEBYP                    RCC_BDCR_LSEBYP_Msk                 
+#define RCC_BDCR_LSEMOD_Pos                (3U)                                
+#define RCC_BDCR_LSEMOD_Msk                (0x1UL << RCC_BDCR_LSEMOD_Pos)       /*!< 0x00000008 */
+#define RCC_BDCR_LSEMOD                    RCC_BDCR_LSEMOD_Msk                 
+
+#define RCC_BDCR_RTCSEL_Pos                (8U)                                
+#define RCC_BDCR_RTCSEL_Msk                (0x3UL << RCC_BDCR_RTCSEL_Pos)       /*!< 0x00000300 */
+#define RCC_BDCR_RTCSEL                    RCC_BDCR_RTCSEL_Msk                 
+#define RCC_BDCR_RTCSEL_0                  (0x1UL << RCC_BDCR_RTCSEL_Pos)       /*!< 0x00000100 */
+#define RCC_BDCR_RTCSEL_1                  (0x2UL << RCC_BDCR_RTCSEL_Pos)       /*!< 0x00000200 */
+
+#define RCC_BDCR_RTCEN_Pos                 (15U)                               
+#define RCC_BDCR_RTCEN_Msk                 (0x1UL << RCC_BDCR_RTCEN_Pos)        /*!< 0x00008000 */
+#define RCC_BDCR_RTCEN                     RCC_BDCR_RTCEN_Msk                  
+#define RCC_BDCR_BDRST_Pos                 (16U)                               
+#define RCC_BDCR_BDRST_Msk                 (0x1UL << RCC_BDCR_BDRST_Pos)        /*!< 0x00010000 */
+#define RCC_BDCR_BDRST                     RCC_BDCR_BDRST_Msk                  
+
+/********************  Bit definition for RCC_CSR register  *******************/
+#define RCC_CSR_LSION_Pos                  (0U)                                
+#define RCC_CSR_LSION_Msk                  (0x1UL << RCC_CSR_LSION_Pos)         /*!< 0x00000001 */
+#define RCC_CSR_LSION                      RCC_CSR_LSION_Msk                   
+#define RCC_CSR_LSIRDY_Pos                 (1U)                                
+#define RCC_CSR_LSIRDY_Msk                 (0x1UL << RCC_CSR_LSIRDY_Pos)        /*!< 0x00000002 */
+#define RCC_CSR_LSIRDY                     RCC_CSR_LSIRDY_Msk                  
+#define RCC_CSR_RMVF_Pos                   (24U)                               
+#define RCC_CSR_RMVF_Msk                   (0x1UL << RCC_CSR_RMVF_Pos)          /*!< 0x01000000 */
+#define RCC_CSR_RMVF                       RCC_CSR_RMVF_Msk                    
+#define RCC_CSR_BORRSTF_Pos                (25U)                               
+#define RCC_CSR_BORRSTF_Msk                (0x1UL << RCC_CSR_BORRSTF_Pos)       /*!< 0x02000000 */
+#define RCC_CSR_BORRSTF                    RCC_CSR_BORRSTF_Msk                 
+#define RCC_CSR_PINRSTF_Pos                (26U)
+#define RCC_CSR_PINRSTF_Msk                (0x1UL << RCC_CSR_PINRSTF_Pos)       /*!< 0x04000000 */
+#define RCC_CSR_PINRSTF                    RCC_CSR_PINRSTF_Msk
+#define RCC_CSR_PORRSTF_Pos                (27U)                               
+#define RCC_CSR_PORRSTF_Msk                (0x1UL << RCC_CSR_PORRSTF_Pos)       /*!< 0x08000000 */
+#define RCC_CSR_PORRSTF                    RCC_CSR_PORRSTF_Msk                 
+#define RCC_CSR_SFTRSTF_Pos                (28U)                               
+#define RCC_CSR_SFTRSTF_Msk                (0x1UL << RCC_CSR_SFTRSTF_Pos)       /*!< 0x10000000 */
+#define RCC_CSR_SFTRSTF                    RCC_CSR_SFTRSTF_Msk                 
+#define RCC_CSR_IWDGRSTF_Pos               (29U)
+#define RCC_CSR_IWDGRSTF_Msk               (0x1UL << RCC_CSR_IWDGRSTF_Pos)      /*!< 0x20000000 */
+#define RCC_CSR_IWDGRSTF                   RCC_CSR_IWDGRSTF_Msk
+#define RCC_CSR_WWDGRSTF_Pos               (30U)                               
+#define RCC_CSR_WWDGRSTF_Msk               (0x1UL << RCC_CSR_WWDGRSTF_Pos)      /*!< 0x40000000 */
+#define RCC_CSR_WWDGRSTF                   RCC_CSR_WWDGRSTF_Msk                
+#define RCC_CSR_LPWRRSTF_Pos               (31U)                               
+#define RCC_CSR_LPWRRSTF_Msk               (0x1UL << RCC_CSR_LPWRRSTF_Pos)      /*!< 0x80000000 */
+#define RCC_CSR_LPWRRSTF                   RCC_CSR_LPWRRSTF_Msk
+/* Legacy defines */
+#define RCC_CSR_PADRSTF                    RCC_CSR_PINRSTF
+#define RCC_CSR_WDGRSTF                    RCC_CSR_IWDGRSTF
+
+/********************  Bit definition for RCC_SSCGR register  *****************/
+#define RCC_SSCGR_MODPER_Pos               (0U)                                
+#define RCC_SSCGR_MODPER_Msk               (0x1FFFUL << RCC_SSCGR_MODPER_Pos)   /*!< 0x00001FFF */
+#define RCC_SSCGR_MODPER                   RCC_SSCGR_MODPER_Msk                
+#define RCC_SSCGR_INCSTEP_Pos              (13U)                               
+#define RCC_SSCGR_INCSTEP_Msk              (0x7FFFUL << RCC_SSCGR_INCSTEP_Pos)  /*!< 0x0FFFE000 */
+#define RCC_SSCGR_INCSTEP                  RCC_SSCGR_INCSTEP_Msk               
+#define RCC_SSCGR_SPREADSEL_Pos            (30U)                               
+#define RCC_SSCGR_SPREADSEL_Msk            (0x1UL << RCC_SSCGR_SPREADSEL_Pos)   /*!< 0x40000000 */
+#define RCC_SSCGR_SPREADSEL                RCC_SSCGR_SPREADSEL_Msk             
+#define RCC_SSCGR_SSCGEN_Pos               (31U)                               
+#define RCC_SSCGR_SSCGEN_Msk               (0x1UL << RCC_SSCGR_SSCGEN_Pos)      /*!< 0x80000000 */
+#define RCC_SSCGR_SSCGEN                   RCC_SSCGR_SSCGEN_Msk                
+
+/********************  Bit definition for RCC_PLLI2SCFGR register  ************/
+#define RCC_PLLI2SCFGR_PLLI2SN_Pos         (6U)                                
+#define RCC_PLLI2SCFGR_PLLI2SN_Msk         (0x1FFUL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00007FC0 */
+#define RCC_PLLI2SCFGR_PLLI2SN             RCC_PLLI2SCFGR_PLLI2SN_Msk          
+#define RCC_PLLI2SCFGR_PLLI2SN_0           (0x001UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000040 */
+#define RCC_PLLI2SCFGR_PLLI2SN_1           (0x002UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000080 */
+#define RCC_PLLI2SCFGR_PLLI2SN_2           (0x004UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000100 */
+#define RCC_PLLI2SCFGR_PLLI2SN_3           (0x008UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000200 */
+#define RCC_PLLI2SCFGR_PLLI2SN_4           (0x010UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000400 */
+#define RCC_PLLI2SCFGR_PLLI2SN_5           (0x020UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000800 */
+#define RCC_PLLI2SCFGR_PLLI2SN_6           (0x040UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00001000 */
+#define RCC_PLLI2SCFGR_PLLI2SN_7           (0x080UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00002000 */
+#define RCC_PLLI2SCFGR_PLLI2SN_8           (0x100UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00004000 */
+
+#define RCC_PLLI2SCFGR_PLLI2SQ_Pos         (24U)                               
+#define RCC_PLLI2SCFGR_PLLI2SQ_Msk         (0xFUL << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x0F000000 */
+#define RCC_PLLI2SCFGR_PLLI2SQ             RCC_PLLI2SCFGR_PLLI2SQ_Msk          
+#define RCC_PLLI2SCFGR_PLLI2SQ_0           (0x1UL << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x01000000 */
+#define RCC_PLLI2SCFGR_PLLI2SQ_1           (0x2UL << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x02000000 */
+#define RCC_PLLI2SCFGR_PLLI2SQ_2           (0x4UL << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x04000000 */
+#define RCC_PLLI2SCFGR_PLLI2SQ_3           (0x8UL << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x08000000 */
+#define RCC_PLLI2SCFGR_PLLI2SR_Pos         (28U)                               
+#define RCC_PLLI2SCFGR_PLLI2SR_Msk         (0x7UL << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x70000000 */
+#define RCC_PLLI2SCFGR_PLLI2SR             RCC_PLLI2SCFGR_PLLI2SR_Msk          
+#define RCC_PLLI2SCFGR_PLLI2SR_0           (0x1UL << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x10000000 */
+#define RCC_PLLI2SCFGR_PLLI2SR_1           (0x2UL << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x20000000 */
+#define RCC_PLLI2SCFGR_PLLI2SR_2           (0x4UL << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x40000000 */
+
+/********************  Bit definition for RCC_PLLSAICFGR register  ************/
+#define RCC_PLLSAICFGR_PLLSAIN_Pos         (6U)                                
+#define RCC_PLLSAICFGR_PLLSAIN_Msk         (0x1FFUL << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00007FC0 */
+#define RCC_PLLSAICFGR_PLLSAIN             RCC_PLLSAICFGR_PLLSAIN_Msk          
+#define RCC_PLLSAICFGR_PLLSAIN_0           (0x001UL << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000040 */
+#define RCC_PLLSAICFGR_PLLSAIN_1           (0x002UL << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000080 */
+#define RCC_PLLSAICFGR_PLLSAIN_2           (0x004UL << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000100 */
+#define RCC_PLLSAICFGR_PLLSAIN_3           (0x008UL << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000200 */
+#define RCC_PLLSAICFGR_PLLSAIN_4           (0x010UL << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000400 */
+#define RCC_PLLSAICFGR_PLLSAIN_5           (0x020UL << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000800 */
+#define RCC_PLLSAICFGR_PLLSAIN_6           (0x040UL << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00001000 */
+#define RCC_PLLSAICFGR_PLLSAIN_7           (0x080UL << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00002000 */
+#define RCC_PLLSAICFGR_PLLSAIN_8           (0x100UL << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00004000 */
+
+#define RCC_PLLSAICFGR_PLLSAIP_Pos         (16U)                               
+#define RCC_PLLSAICFGR_PLLSAIP_Msk         (0x3UL << RCC_PLLSAICFGR_PLLSAIP_Pos) /*!< 0x00030000 */
+#define RCC_PLLSAICFGR_PLLSAIP             RCC_PLLSAICFGR_PLLSAIP_Msk          
+#define RCC_PLLSAICFGR_PLLSAIP_0           (0x1UL << RCC_PLLSAICFGR_PLLSAIP_Pos) /*!< 0x00010000 */
+#define RCC_PLLSAICFGR_PLLSAIP_1           (0x2UL << RCC_PLLSAICFGR_PLLSAIP_Pos) /*!< 0x00020000 */
+
+#define RCC_PLLSAICFGR_PLLSAIQ_Pos         (24U)                               
+#define RCC_PLLSAICFGR_PLLSAIQ_Msk         (0xFUL << RCC_PLLSAICFGR_PLLSAIQ_Pos) /*!< 0x0F000000 */
+#define RCC_PLLSAICFGR_PLLSAIQ             RCC_PLLSAICFGR_PLLSAIQ_Msk          
+#define RCC_PLLSAICFGR_PLLSAIQ_0           (0x1UL << RCC_PLLSAICFGR_PLLSAIQ_Pos) /*!< 0x01000000 */
+#define RCC_PLLSAICFGR_PLLSAIQ_1           (0x2UL << RCC_PLLSAICFGR_PLLSAIQ_Pos) /*!< 0x02000000 */
+#define RCC_PLLSAICFGR_PLLSAIQ_2           (0x4UL << RCC_PLLSAICFGR_PLLSAIQ_Pos) /*!< 0x04000000 */
+#define RCC_PLLSAICFGR_PLLSAIQ_3           (0x8UL << RCC_PLLSAICFGR_PLLSAIQ_Pos) /*!< 0x08000000 */
+
+#define RCC_PLLSAICFGR_PLLSAIR_Pos         (28U)                               
+#define RCC_PLLSAICFGR_PLLSAIR_Msk         (0x7UL << RCC_PLLSAICFGR_PLLSAIR_Pos) /*!< 0x70000000 */
+#define RCC_PLLSAICFGR_PLLSAIR             RCC_PLLSAICFGR_PLLSAIR_Msk          
+#define RCC_PLLSAICFGR_PLLSAIR_0           (0x1UL << RCC_PLLSAICFGR_PLLSAIR_Pos) /*!< 0x10000000 */
+#define RCC_PLLSAICFGR_PLLSAIR_1           (0x2UL << RCC_PLLSAICFGR_PLLSAIR_Pos) /*!< 0x20000000 */
+#define RCC_PLLSAICFGR_PLLSAIR_2           (0x4UL << RCC_PLLSAICFGR_PLLSAIR_Pos) /*!< 0x40000000 */
+
+/********************  Bit definition for RCC_DCKCFGR register  ***************/
+#define RCC_DCKCFGR_PLLI2SDIVQ_Pos        (0U)                                
+#define RCC_DCKCFGR_PLLI2SDIVQ_Msk        (0x1FUL << RCC_DCKCFGR_PLLI2SDIVQ_Pos) /*!< 0x0000001F */
+#define RCC_DCKCFGR_PLLI2SDIVQ            RCC_DCKCFGR_PLLI2SDIVQ_Msk         
+#define RCC_DCKCFGR_PLLI2SDIVQ_0          (0x01UL << RCC_DCKCFGR_PLLI2SDIVQ_Pos) /*!< 0x00000001 */
+#define RCC_DCKCFGR_PLLI2SDIVQ_1          (0x02UL << RCC_DCKCFGR_PLLI2SDIVQ_Pos) /*!< 0x00000002 */
+#define RCC_DCKCFGR_PLLI2SDIVQ_2          (0x04UL << RCC_DCKCFGR_PLLI2SDIVQ_Pos) /*!< 0x00000004 */
+#define RCC_DCKCFGR_PLLI2SDIVQ_3          (0x08UL << RCC_DCKCFGR_PLLI2SDIVQ_Pos) /*!< 0x00000008 */
+#define RCC_DCKCFGR_PLLI2SDIVQ_4          (0x10UL << RCC_DCKCFGR_PLLI2SDIVQ_Pos) /*!< 0x00000010 */
+                   
+#define RCC_DCKCFGR_PLLSAIDIVQ_Pos        (8U)                                
+#define RCC_DCKCFGR_PLLSAIDIVQ_Msk        (0x1FUL << RCC_DCKCFGR_PLLSAIDIVQ_Pos) /*!< 0x00001F00 */
+#define RCC_DCKCFGR_PLLSAIDIVQ            RCC_DCKCFGR_PLLSAIDIVQ_Msk         
+#define RCC_DCKCFGR_PLLSAIDIVQ_0          (0x01UL << RCC_DCKCFGR_PLLSAIDIVQ_Pos) /*!< 0x00000100 */
+#define RCC_DCKCFGR_PLLSAIDIVQ_1          (0x02UL << RCC_DCKCFGR_PLLSAIDIVQ_Pos) /*!< 0x00000200 */
+#define RCC_DCKCFGR_PLLSAIDIVQ_2          (0x04UL << RCC_DCKCFGR_PLLSAIDIVQ_Pos) /*!< 0x00000400 */
+#define RCC_DCKCFGR_PLLSAIDIVQ_3          (0x08UL << RCC_DCKCFGR_PLLSAIDIVQ_Pos) /*!< 0x00000800 */
+#define RCC_DCKCFGR_PLLSAIDIVQ_4          (0x10UL << RCC_DCKCFGR_PLLSAIDIVQ_Pos) /*!< 0x00001000 */
+#define RCC_DCKCFGR_PLLSAIDIVR_Pos        (16U)                               
+#define RCC_DCKCFGR_PLLSAIDIVR_Msk        (0x3UL << RCC_DCKCFGR_PLLSAIDIVR_Pos) /*!< 0x00030000 */
+#define RCC_DCKCFGR_PLLSAIDIVR            RCC_DCKCFGR_PLLSAIDIVR_Msk         
+#define RCC_DCKCFGR_PLLSAIDIVR_0          (0x1UL << RCC_DCKCFGR_PLLSAIDIVR_Pos) /*!< 0x00010000 */
+#define RCC_DCKCFGR_PLLSAIDIVR_1          (0x2UL << RCC_DCKCFGR_PLLSAIDIVR_Pos) /*!< 0x00020000 */
+
+#define RCC_DCKCFGR_SAI1ASRC_Pos           (20U)                               
+#define RCC_DCKCFGR_SAI1ASRC_Msk           (0x3UL << RCC_DCKCFGR_SAI1ASRC_Pos)  /*!< 0x00300000 */
+#define RCC_DCKCFGR_SAI1ASRC               RCC_DCKCFGR_SAI1ASRC_Msk            
+#define RCC_DCKCFGR_SAI1ASRC_0             (0x1UL << RCC_DCKCFGR_SAI1ASRC_Pos)  /*!< 0x00100000 */
+#define RCC_DCKCFGR_SAI1ASRC_1             (0x2UL << RCC_DCKCFGR_SAI1ASRC_Pos)  /*!< 0x00200000 */
+#define RCC_DCKCFGR_SAI1BSRC_Pos           (22U)                               
+#define RCC_DCKCFGR_SAI1BSRC_Msk           (0x3UL << RCC_DCKCFGR_SAI1BSRC_Pos)  /*!< 0x00C00000 */
+#define RCC_DCKCFGR_SAI1BSRC               RCC_DCKCFGR_SAI1BSRC_Msk            
+#define RCC_DCKCFGR_SAI1BSRC_0             (0x1UL << RCC_DCKCFGR_SAI1BSRC_Pos)  /*!< 0x00400000 */
+#define RCC_DCKCFGR_SAI1BSRC_1             (0x2UL << RCC_DCKCFGR_SAI1BSRC_Pos)  /*!< 0x00800000 */
+#define RCC_DCKCFGR_TIMPRE_Pos             (24U)                               
+#define RCC_DCKCFGR_TIMPRE_Msk             (0x1UL << RCC_DCKCFGR_TIMPRE_Pos)    /*!< 0x01000000 */
+#define RCC_DCKCFGR_TIMPRE                 RCC_DCKCFGR_TIMPRE_Msk              
+#define RCC_DCKCFGR_CK48MSEL_Pos           (27U)                               
+#define RCC_DCKCFGR_CK48MSEL_Msk           (0x1UL << RCC_DCKCFGR_CK48MSEL_Pos)  /*!< 0x08000000 */
+#define RCC_DCKCFGR_CK48MSEL               RCC_DCKCFGR_CK48MSEL_Msk            
+#define RCC_DCKCFGR_SDIOSEL_Pos            (28U)                               
+#define RCC_DCKCFGR_SDIOSEL_Msk            (0x1UL << RCC_DCKCFGR_SDIOSEL_Pos)   /*!< 0x10000000 */
+#define RCC_DCKCFGR_SDIOSEL                RCC_DCKCFGR_SDIOSEL_Msk             
+#define RCC_DCKCFGR_DSISEL_Pos             (29U)                               
+#define RCC_DCKCFGR_DSISEL_Msk             (0x1UL << RCC_DCKCFGR_DSISEL_Pos)    /*!< 0x20000000 */
+#define RCC_DCKCFGR_DSISEL                 RCC_DCKCFGR_DSISEL_Msk              
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                                    RNG                                     */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bits definition for RNG_CR register  *******************/
+#define RNG_CR_RNGEN_Pos    (2U)                                               
+#define RNG_CR_RNGEN_Msk    (0x1UL << RNG_CR_RNGEN_Pos)                         /*!< 0x00000004 */
+#define RNG_CR_RNGEN        RNG_CR_RNGEN_Msk                                   
+#define RNG_CR_IE_Pos       (3U)                                               
+#define RNG_CR_IE_Msk       (0x1UL << RNG_CR_IE_Pos)                            /*!< 0x00000008 */
+#define RNG_CR_IE           RNG_CR_IE_Msk                                      
+
+/********************  Bits definition for RNG_SR register  *******************/
+#define RNG_SR_DRDY_Pos     (0U)                                               
+#define RNG_SR_DRDY_Msk     (0x1UL << RNG_SR_DRDY_Pos)                          /*!< 0x00000001 */
+#define RNG_SR_DRDY         RNG_SR_DRDY_Msk                                    
+#define RNG_SR_CECS_Pos     (1U)                                               
+#define RNG_SR_CECS_Msk     (0x1UL << RNG_SR_CECS_Pos)                          /*!< 0x00000002 */
+#define RNG_SR_CECS         RNG_SR_CECS_Msk                                    
+#define RNG_SR_SECS_Pos     (2U)                                               
+#define RNG_SR_SECS_Msk     (0x1UL << RNG_SR_SECS_Pos)                          /*!< 0x00000004 */
+#define RNG_SR_SECS         RNG_SR_SECS_Msk                                    
+#define RNG_SR_CEIS_Pos     (5U)                                               
+#define RNG_SR_CEIS_Msk     (0x1UL << RNG_SR_CEIS_Pos)                          /*!< 0x00000020 */
+#define RNG_SR_CEIS         RNG_SR_CEIS_Msk                                    
+#define RNG_SR_SEIS_Pos     (6U)                                               
+#define RNG_SR_SEIS_Msk     (0x1UL << RNG_SR_SEIS_Pos)                          /*!< 0x00000040 */
+#define RNG_SR_SEIS         RNG_SR_SEIS_Msk                                    
+
+/******************************************************************************/
+/*                                                                            */
+/*                           Real-Time Clock (RTC)                            */
+/*                                                                            */
+/******************************************************************************/
+/*
+ * @brief Specific device feature definitions  (not present on all devices in the STM32F4 serie)
+ */
+#define RTC_TAMPER2_SUPPORT  /*!< TAMPER 2 feature support */
+#define RTC_AF2_SUPPORT /*!< RTC Alternate Function 2 mapping support */
+/********************  Bits definition for RTC_TR register  *******************/
+#define RTC_TR_PM_Pos                 (22U)                                    
+#define RTC_TR_PM_Msk                 (0x1UL << RTC_TR_PM_Pos)                  /*!< 0x00400000 */
+#define RTC_TR_PM                     RTC_TR_PM_Msk                            
+#define RTC_TR_HT_Pos                 (20U)                                    
+#define RTC_TR_HT_Msk                 (0x3UL << RTC_TR_HT_Pos)                  /*!< 0x00300000 */
+#define RTC_TR_HT                     RTC_TR_HT_Msk                            
+#define RTC_TR_HT_0                   (0x1UL << RTC_TR_HT_Pos)                  /*!< 0x00100000 */
+#define RTC_TR_HT_1                   (0x2UL << RTC_TR_HT_Pos)                  /*!< 0x00200000 */
+#define RTC_TR_HU_Pos                 (16U)                                    
+#define RTC_TR_HU_Msk                 (0xFUL << RTC_TR_HU_Pos)                  /*!< 0x000F0000 */
+#define RTC_TR_HU                     RTC_TR_HU_Msk                            
+#define RTC_TR_HU_0                   (0x1UL << RTC_TR_HU_Pos)                  /*!< 0x00010000 */
+#define RTC_TR_HU_1                   (0x2UL << RTC_TR_HU_Pos)                  /*!< 0x00020000 */
+#define RTC_TR_HU_2                   (0x4UL << RTC_TR_HU_Pos)                  /*!< 0x00040000 */
+#define RTC_TR_HU_3                   (0x8UL << RTC_TR_HU_Pos)                  /*!< 0x00080000 */
+#define RTC_TR_MNT_Pos                (12U)                                    
+#define RTC_TR_MNT_Msk                (0x7UL << RTC_TR_MNT_Pos)                 /*!< 0x00007000 */
+#define RTC_TR_MNT                    RTC_TR_MNT_Msk                           
+#define RTC_TR_MNT_0                  (0x1UL << RTC_TR_MNT_Pos)                 /*!< 0x00001000 */
+#define RTC_TR_MNT_1                  (0x2UL << RTC_TR_MNT_Pos)                 /*!< 0x00002000 */
+#define RTC_TR_MNT_2                  (0x4UL << RTC_TR_MNT_Pos)                 /*!< 0x00004000 */
+#define RTC_TR_MNU_Pos                (8U)                                     
+#define RTC_TR_MNU_Msk                (0xFUL << RTC_TR_MNU_Pos)                 /*!< 0x00000F00 */
+#define RTC_TR_MNU                    RTC_TR_MNU_Msk                           
+#define RTC_TR_MNU_0                  (0x1UL << RTC_TR_MNU_Pos)                 /*!< 0x00000100 */
+#define RTC_TR_MNU_1                  (0x2UL << RTC_TR_MNU_Pos)                 /*!< 0x00000200 */
+#define RTC_TR_MNU_2                  (0x4UL << RTC_TR_MNU_Pos)                 /*!< 0x00000400 */
+#define RTC_TR_MNU_3                  (0x8UL << RTC_TR_MNU_Pos)                 /*!< 0x00000800 */
+#define RTC_TR_ST_Pos                 (4U)                                     
+#define RTC_TR_ST_Msk                 (0x7UL << RTC_TR_ST_Pos)                  /*!< 0x00000070 */
+#define RTC_TR_ST                     RTC_TR_ST_Msk                            
+#define RTC_TR_ST_0                   (0x1UL << RTC_TR_ST_Pos)                  /*!< 0x00000010 */
+#define RTC_TR_ST_1                   (0x2UL << RTC_TR_ST_Pos)                  /*!< 0x00000020 */
+#define RTC_TR_ST_2                   (0x4UL << RTC_TR_ST_Pos)                  /*!< 0x00000040 */
+#define RTC_TR_SU_Pos                 (0U)                                     
+#define RTC_TR_SU_Msk                 (0xFUL << RTC_TR_SU_Pos)                  /*!< 0x0000000F */
+#define RTC_TR_SU                     RTC_TR_SU_Msk                            
+#define RTC_TR_SU_0                   (0x1UL << RTC_TR_SU_Pos)                  /*!< 0x00000001 */
+#define RTC_TR_SU_1                   (0x2UL << RTC_TR_SU_Pos)                  /*!< 0x00000002 */
+#define RTC_TR_SU_2                   (0x4UL << RTC_TR_SU_Pos)                  /*!< 0x00000004 */
+#define RTC_TR_SU_3                   (0x8UL << RTC_TR_SU_Pos)                  /*!< 0x00000008 */
+
+/********************  Bits definition for RTC_DR register  *******************/
+#define RTC_DR_YT_Pos                 (20U)                                    
+#define RTC_DR_YT_Msk                 (0xFUL << RTC_DR_YT_Pos)                  /*!< 0x00F00000 */
+#define RTC_DR_YT                     RTC_DR_YT_Msk                            
+#define RTC_DR_YT_0                   (0x1UL << RTC_DR_YT_Pos)                  /*!< 0x00100000 */
+#define RTC_DR_YT_1                   (0x2UL << RTC_DR_YT_Pos)                  /*!< 0x00200000 */
+#define RTC_DR_YT_2                   (0x4UL << RTC_DR_YT_Pos)                  /*!< 0x00400000 */
+#define RTC_DR_YT_3                   (0x8UL << RTC_DR_YT_Pos)                  /*!< 0x00800000 */
+#define RTC_DR_YU_Pos                 (16U)                                    
+#define RTC_DR_YU_Msk                 (0xFUL << RTC_DR_YU_Pos)                  /*!< 0x000F0000 */
+#define RTC_DR_YU                     RTC_DR_YU_Msk                            
+#define RTC_DR_YU_0                   (0x1UL << RTC_DR_YU_Pos)                  /*!< 0x00010000 */
+#define RTC_DR_YU_1                   (0x2UL << RTC_DR_YU_Pos)                  /*!< 0x00020000 */
+#define RTC_DR_YU_2                   (0x4UL << RTC_DR_YU_Pos)                  /*!< 0x00040000 */
+#define RTC_DR_YU_3                   (0x8UL << RTC_DR_YU_Pos)                  /*!< 0x00080000 */
+#define RTC_DR_WDU_Pos                (13U)                                    
+#define RTC_DR_WDU_Msk                (0x7UL << RTC_DR_WDU_Pos)                 /*!< 0x0000E000 */
+#define RTC_DR_WDU                    RTC_DR_WDU_Msk                           
+#define RTC_DR_WDU_0                  (0x1UL << RTC_DR_WDU_Pos)                 /*!< 0x00002000 */
+#define RTC_DR_WDU_1                  (0x2UL << RTC_DR_WDU_Pos)                 /*!< 0x00004000 */
+#define RTC_DR_WDU_2                  (0x4UL << RTC_DR_WDU_Pos)                 /*!< 0x00008000 */
+#define RTC_DR_MT_Pos                 (12U)                                    
+#define RTC_DR_MT_Msk                 (0x1UL << RTC_DR_MT_Pos)                  /*!< 0x00001000 */
+#define RTC_DR_MT                     RTC_DR_MT_Msk                            
+#define RTC_DR_MU_Pos                 (8U)                                     
+#define RTC_DR_MU_Msk                 (0xFUL << RTC_DR_MU_Pos)                  /*!< 0x00000F00 */
+#define RTC_DR_MU                     RTC_DR_MU_Msk                            
+#define RTC_DR_MU_0                   (0x1UL << RTC_DR_MU_Pos)                  /*!< 0x00000100 */
+#define RTC_DR_MU_1                   (0x2UL << RTC_DR_MU_Pos)                  /*!< 0x00000200 */
+#define RTC_DR_MU_2                   (0x4UL << RTC_DR_MU_Pos)                  /*!< 0x00000400 */
+#define RTC_DR_MU_3                   (0x8UL << RTC_DR_MU_Pos)                  /*!< 0x00000800 */
+#define RTC_DR_DT_Pos                 (4U)                                     
+#define RTC_DR_DT_Msk                 (0x3UL << RTC_DR_DT_Pos)                  /*!< 0x00000030 */
+#define RTC_DR_DT                     RTC_DR_DT_Msk                            
+#define RTC_DR_DT_0                   (0x1UL << RTC_DR_DT_Pos)                  /*!< 0x00000010 */
+#define RTC_DR_DT_1                   (0x2UL << RTC_DR_DT_Pos)                  /*!< 0x00000020 */
+#define RTC_DR_DU_Pos                 (0U)                                     
+#define RTC_DR_DU_Msk                 (0xFUL << RTC_DR_DU_Pos)                  /*!< 0x0000000F */
+#define RTC_DR_DU                     RTC_DR_DU_Msk                            
+#define RTC_DR_DU_0                   (0x1UL << RTC_DR_DU_Pos)                  /*!< 0x00000001 */
+#define RTC_DR_DU_1                   (0x2UL << RTC_DR_DU_Pos)                  /*!< 0x00000002 */
+#define RTC_DR_DU_2                   (0x4UL << RTC_DR_DU_Pos)                  /*!< 0x00000004 */
+#define RTC_DR_DU_3                   (0x8UL << RTC_DR_DU_Pos)                  /*!< 0x00000008 */
+
+/********************  Bits definition for RTC_CR register  *******************/
+#define RTC_CR_COE_Pos                (23U)                                    
+#define RTC_CR_COE_Msk                (0x1UL << RTC_CR_COE_Pos)                 /*!< 0x00800000 */
+#define RTC_CR_COE                    RTC_CR_COE_Msk                           
+#define RTC_CR_OSEL_Pos               (21U)                                    
+#define RTC_CR_OSEL_Msk               (0x3UL << RTC_CR_OSEL_Pos)                /*!< 0x00600000 */
+#define RTC_CR_OSEL                   RTC_CR_OSEL_Msk                          
+#define RTC_CR_OSEL_0                 (0x1UL << RTC_CR_OSEL_Pos)                /*!< 0x00200000 */
+#define RTC_CR_OSEL_1                 (0x2UL << RTC_CR_OSEL_Pos)                /*!< 0x00400000 */
+#define RTC_CR_POL_Pos                (20U)                                    
+#define RTC_CR_POL_Msk                (0x1UL << RTC_CR_POL_Pos)                 /*!< 0x00100000 */
+#define RTC_CR_POL                    RTC_CR_POL_Msk                           
+#define RTC_CR_COSEL_Pos              (19U)                                    
+#define RTC_CR_COSEL_Msk              (0x1UL << RTC_CR_COSEL_Pos)               /*!< 0x00080000 */
+#define RTC_CR_COSEL                  RTC_CR_COSEL_Msk                         
+#define RTC_CR_BKP_Pos                 (18U)                                   
+#define RTC_CR_BKP_Msk                 (0x1UL << RTC_CR_BKP_Pos)                /*!< 0x00040000 */
+#define RTC_CR_BKP                     RTC_CR_BKP_Msk                          
+#define RTC_CR_SUB1H_Pos              (17U)                                    
+#define RTC_CR_SUB1H_Msk              (0x1UL << RTC_CR_SUB1H_Pos)               /*!< 0x00020000 */
+#define RTC_CR_SUB1H                  RTC_CR_SUB1H_Msk                         
+#define RTC_CR_ADD1H_Pos              (16U)                                    
+#define RTC_CR_ADD1H_Msk              (0x1UL << RTC_CR_ADD1H_Pos)               /*!< 0x00010000 */
+#define RTC_CR_ADD1H                  RTC_CR_ADD1H_Msk                         
+#define RTC_CR_TSIE_Pos               (15U)                                    
+#define RTC_CR_TSIE_Msk               (0x1UL << RTC_CR_TSIE_Pos)                /*!< 0x00008000 */
+#define RTC_CR_TSIE                   RTC_CR_TSIE_Msk                          
+#define RTC_CR_WUTIE_Pos              (14U)                                    
+#define RTC_CR_WUTIE_Msk              (0x1UL << RTC_CR_WUTIE_Pos)               /*!< 0x00004000 */
+#define RTC_CR_WUTIE                  RTC_CR_WUTIE_Msk                         
+#define RTC_CR_ALRBIE_Pos             (13U)                                    
+#define RTC_CR_ALRBIE_Msk             (0x1UL << RTC_CR_ALRBIE_Pos)              /*!< 0x00002000 */
+#define RTC_CR_ALRBIE                 RTC_CR_ALRBIE_Msk                        
+#define RTC_CR_ALRAIE_Pos             (12U)                                    
+#define RTC_CR_ALRAIE_Msk             (0x1UL << RTC_CR_ALRAIE_Pos)              /*!< 0x00001000 */
+#define RTC_CR_ALRAIE                 RTC_CR_ALRAIE_Msk                        
+#define RTC_CR_TSE_Pos                (11U)                                    
+#define RTC_CR_TSE_Msk                (0x1UL << RTC_CR_TSE_Pos)                 /*!< 0x00000800 */
+#define RTC_CR_TSE                    RTC_CR_TSE_Msk                           
+#define RTC_CR_WUTE_Pos               (10U)                                    
+#define RTC_CR_WUTE_Msk               (0x1UL << RTC_CR_WUTE_Pos)                /*!< 0x00000400 */
+#define RTC_CR_WUTE                   RTC_CR_WUTE_Msk                          
+#define RTC_CR_ALRBE_Pos              (9U)                                     
+#define RTC_CR_ALRBE_Msk              (0x1UL << RTC_CR_ALRBE_Pos)               /*!< 0x00000200 */
+#define RTC_CR_ALRBE                  RTC_CR_ALRBE_Msk                         
+#define RTC_CR_ALRAE_Pos              (8U)                                     
+#define RTC_CR_ALRAE_Msk              (0x1UL << RTC_CR_ALRAE_Pos)               /*!< 0x00000100 */
+#define RTC_CR_ALRAE                  RTC_CR_ALRAE_Msk                         
+#define RTC_CR_DCE_Pos                (7U)                                     
+#define RTC_CR_DCE_Msk                (0x1UL << RTC_CR_DCE_Pos)                 /*!< 0x00000080 */
+#define RTC_CR_DCE                    RTC_CR_DCE_Msk                           
+#define RTC_CR_FMT_Pos                (6U)                                     
+#define RTC_CR_FMT_Msk                (0x1UL << RTC_CR_FMT_Pos)                 /*!< 0x00000040 */
+#define RTC_CR_FMT                    RTC_CR_FMT_Msk                           
+#define RTC_CR_BYPSHAD_Pos            (5U)                                     
+#define RTC_CR_BYPSHAD_Msk            (0x1UL << RTC_CR_BYPSHAD_Pos)             /*!< 0x00000020 */
+#define RTC_CR_BYPSHAD                RTC_CR_BYPSHAD_Msk                       
+#define RTC_CR_REFCKON_Pos            (4U)                                     
+#define RTC_CR_REFCKON_Msk            (0x1UL << RTC_CR_REFCKON_Pos)             /*!< 0x00000010 */
+#define RTC_CR_REFCKON                RTC_CR_REFCKON_Msk                       
+#define RTC_CR_TSEDGE_Pos             (3U)                                     
+#define RTC_CR_TSEDGE_Msk             (0x1UL << RTC_CR_TSEDGE_Pos)              /*!< 0x00000008 */
+#define RTC_CR_TSEDGE                 RTC_CR_TSEDGE_Msk                        
+#define RTC_CR_WUCKSEL_Pos            (0U)                                     
+#define RTC_CR_WUCKSEL_Msk            (0x7UL << RTC_CR_WUCKSEL_Pos)             /*!< 0x00000007 */
+#define RTC_CR_WUCKSEL                RTC_CR_WUCKSEL_Msk                       
+#define RTC_CR_WUCKSEL_0              (0x1UL << RTC_CR_WUCKSEL_Pos)             /*!< 0x00000001 */
+#define RTC_CR_WUCKSEL_1              (0x2UL << RTC_CR_WUCKSEL_Pos)             /*!< 0x00000002 */
+#define RTC_CR_WUCKSEL_2              (0x4UL << RTC_CR_WUCKSEL_Pos)             /*!< 0x00000004 */
+
+/* Legacy defines */
+#define RTC_CR_BCK                     RTC_CR_BKP
+
+/********************  Bits definition for RTC_ISR register  ******************/
+#define RTC_ISR_RECALPF_Pos           (16U)                                    
+#define RTC_ISR_RECALPF_Msk           (0x1UL << RTC_ISR_RECALPF_Pos)            /*!< 0x00010000 */
+#define RTC_ISR_RECALPF               RTC_ISR_RECALPF_Msk                      
+#define RTC_ISR_TAMP1F_Pos            (13U)                                    
+#define RTC_ISR_TAMP1F_Msk            (0x1UL << RTC_ISR_TAMP1F_Pos)             /*!< 0x00002000 */
+#define RTC_ISR_TAMP1F                RTC_ISR_TAMP1F_Msk                       
+#define RTC_ISR_TAMP2F_Pos            (14U)                                    
+#define RTC_ISR_TAMP2F_Msk            (0x1UL << RTC_ISR_TAMP2F_Pos)             /*!< 0x00004000 */
+#define RTC_ISR_TAMP2F                RTC_ISR_TAMP2F_Msk                       
+#define RTC_ISR_TSOVF_Pos             (12U)                                    
+#define RTC_ISR_TSOVF_Msk             (0x1UL << RTC_ISR_TSOVF_Pos)              /*!< 0x00001000 */
+#define RTC_ISR_TSOVF                 RTC_ISR_TSOVF_Msk                        
+#define RTC_ISR_TSF_Pos               (11U)                                    
+#define RTC_ISR_TSF_Msk               (0x1UL << RTC_ISR_TSF_Pos)                /*!< 0x00000800 */
+#define RTC_ISR_TSF                   RTC_ISR_TSF_Msk                          
+#define RTC_ISR_WUTF_Pos              (10U)                                    
+#define RTC_ISR_WUTF_Msk              (0x1UL << RTC_ISR_WUTF_Pos)               /*!< 0x00000400 */
+#define RTC_ISR_WUTF                  RTC_ISR_WUTF_Msk                         
+#define RTC_ISR_ALRBF_Pos             (9U)                                     
+#define RTC_ISR_ALRBF_Msk             (0x1UL << RTC_ISR_ALRBF_Pos)              /*!< 0x00000200 */
+#define RTC_ISR_ALRBF                 RTC_ISR_ALRBF_Msk                        
+#define RTC_ISR_ALRAF_Pos             (8U)                                     
+#define RTC_ISR_ALRAF_Msk             (0x1UL << RTC_ISR_ALRAF_Pos)              /*!< 0x00000100 */
+#define RTC_ISR_ALRAF                 RTC_ISR_ALRAF_Msk                        
+#define RTC_ISR_INIT_Pos              (7U)                                     
+#define RTC_ISR_INIT_Msk              (0x1UL << RTC_ISR_INIT_Pos)               /*!< 0x00000080 */
+#define RTC_ISR_INIT                  RTC_ISR_INIT_Msk                         
+#define RTC_ISR_INITF_Pos             (6U)                                     
+#define RTC_ISR_INITF_Msk             (0x1UL << RTC_ISR_INITF_Pos)              /*!< 0x00000040 */
+#define RTC_ISR_INITF                 RTC_ISR_INITF_Msk                        
+#define RTC_ISR_RSF_Pos               (5U)                                     
+#define RTC_ISR_RSF_Msk               (0x1UL << RTC_ISR_RSF_Pos)                /*!< 0x00000020 */
+#define RTC_ISR_RSF                   RTC_ISR_RSF_Msk                          
+#define RTC_ISR_INITS_Pos             (4U)                                     
+#define RTC_ISR_INITS_Msk             (0x1UL << RTC_ISR_INITS_Pos)              /*!< 0x00000010 */
+#define RTC_ISR_INITS                 RTC_ISR_INITS_Msk                        
+#define RTC_ISR_SHPF_Pos              (3U)                                     
+#define RTC_ISR_SHPF_Msk              (0x1UL << RTC_ISR_SHPF_Pos)               /*!< 0x00000008 */
+#define RTC_ISR_SHPF                  RTC_ISR_SHPF_Msk                         
+#define RTC_ISR_WUTWF_Pos             (2U)                                     
+#define RTC_ISR_WUTWF_Msk             (0x1UL << RTC_ISR_WUTWF_Pos)              /*!< 0x00000004 */
+#define RTC_ISR_WUTWF                 RTC_ISR_WUTWF_Msk                        
+#define RTC_ISR_ALRBWF_Pos            (1U)                                     
+#define RTC_ISR_ALRBWF_Msk            (0x1UL << RTC_ISR_ALRBWF_Pos)             /*!< 0x00000002 */
+#define RTC_ISR_ALRBWF                RTC_ISR_ALRBWF_Msk                       
+#define RTC_ISR_ALRAWF_Pos            (0U)                                     
+#define RTC_ISR_ALRAWF_Msk            (0x1UL << RTC_ISR_ALRAWF_Pos)             /*!< 0x00000001 */
+#define RTC_ISR_ALRAWF                RTC_ISR_ALRAWF_Msk                       
+
+/********************  Bits definition for RTC_PRER register  *****************/
+#define RTC_PRER_PREDIV_A_Pos         (16U)                                    
+#define RTC_PRER_PREDIV_A_Msk         (0x7FUL << RTC_PRER_PREDIV_A_Pos)         /*!< 0x007F0000 */
+#define RTC_PRER_PREDIV_A             RTC_PRER_PREDIV_A_Msk                    
+#define RTC_PRER_PREDIV_S_Pos         (0U)                                     
+#define RTC_PRER_PREDIV_S_Msk         (0x7FFFUL << RTC_PRER_PREDIV_S_Pos)       /*!< 0x00007FFF */
+#define RTC_PRER_PREDIV_S             RTC_PRER_PREDIV_S_Msk                    
+
+/********************  Bits definition for RTC_WUTR register  *****************/
+#define RTC_WUTR_WUT_Pos              (0U)                                     
+#define RTC_WUTR_WUT_Msk              (0xFFFFUL << RTC_WUTR_WUT_Pos)            /*!< 0x0000FFFF */
+#define RTC_WUTR_WUT                  RTC_WUTR_WUT_Msk                         
+
+/********************  Bits definition for RTC_CALIBR register  ***************/
+#define RTC_CALIBR_DCS_Pos            (7U)                                     
+#define RTC_CALIBR_DCS_Msk            (0x1UL << RTC_CALIBR_DCS_Pos)             /*!< 0x00000080 */
+#define RTC_CALIBR_DCS                RTC_CALIBR_DCS_Msk                       
+#define RTC_CALIBR_DC_Pos             (0U)                                     
+#define RTC_CALIBR_DC_Msk             (0x1FUL << RTC_CALIBR_DC_Pos)             /*!< 0x0000001F */
+#define RTC_CALIBR_DC                 RTC_CALIBR_DC_Msk                        
+
+/********************  Bits definition for RTC_ALRMAR register  ***************/
+#define RTC_ALRMAR_MSK4_Pos           (31U)                                    
+#define RTC_ALRMAR_MSK4_Msk           (0x1UL << RTC_ALRMAR_MSK4_Pos)            /*!< 0x80000000 */
+#define RTC_ALRMAR_MSK4               RTC_ALRMAR_MSK4_Msk                      
+#define RTC_ALRMAR_WDSEL_Pos          (30U)                                    
+#define RTC_ALRMAR_WDSEL_Msk          (0x1UL << RTC_ALRMAR_WDSEL_Pos)           /*!< 0x40000000 */
+#define RTC_ALRMAR_WDSEL              RTC_ALRMAR_WDSEL_Msk                     
+#define RTC_ALRMAR_DT_Pos             (28U)                                    
+#define RTC_ALRMAR_DT_Msk             (0x3UL << RTC_ALRMAR_DT_Pos)              /*!< 0x30000000 */
+#define RTC_ALRMAR_DT                 RTC_ALRMAR_DT_Msk                        
+#define RTC_ALRMAR_DT_0               (0x1UL << RTC_ALRMAR_DT_Pos)              /*!< 0x10000000 */
+#define RTC_ALRMAR_DT_1               (0x2UL << RTC_ALRMAR_DT_Pos)              /*!< 0x20000000 */
+#define RTC_ALRMAR_DU_Pos             (24U)                                    
+#define RTC_ALRMAR_DU_Msk             (0xFUL << RTC_ALRMAR_DU_Pos)              /*!< 0x0F000000 */
+#define RTC_ALRMAR_DU                 RTC_ALRMAR_DU_Msk                        
+#define RTC_ALRMAR_DU_0               (0x1UL << RTC_ALRMAR_DU_Pos)              /*!< 0x01000000 */
+#define RTC_ALRMAR_DU_1               (0x2UL << RTC_ALRMAR_DU_Pos)              /*!< 0x02000000 */
+#define RTC_ALRMAR_DU_2               (0x4UL << RTC_ALRMAR_DU_Pos)              /*!< 0x04000000 */
+#define RTC_ALRMAR_DU_3               (0x8UL << RTC_ALRMAR_DU_Pos)              /*!< 0x08000000 */
+#define RTC_ALRMAR_MSK3_Pos           (23U)                                    
+#define RTC_ALRMAR_MSK3_Msk           (0x1UL << RTC_ALRMAR_MSK3_Pos)            /*!< 0x00800000 */
+#define RTC_ALRMAR_MSK3               RTC_ALRMAR_MSK3_Msk                      
+#define RTC_ALRMAR_PM_Pos             (22U)                                    
+#define RTC_ALRMAR_PM_Msk             (0x1UL << RTC_ALRMAR_PM_Pos)              /*!< 0x00400000 */
+#define RTC_ALRMAR_PM                 RTC_ALRMAR_PM_Msk                        
+#define RTC_ALRMAR_HT_Pos             (20U)                                    
+#define RTC_ALRMAR_HT_Msk             (0x3UL << RTC_ALRMAR_HT_Pos)              /*!< 0x00300000 */
+#define RTC_ALRMAR_HT                 RTC_ALRMAR_HT_Msk                        
+#define RTC_ALRMAR_HT_0               (0x1UL << RTC_ALRMAR_HT_Pos)              /*!< 0x00100000 */
+#define RTC_ALRMAR_HT_1               (0x2UL << RTC_ALRMAR_HT_Pos)              /*!< 0x00200000 */
+#define RTC_ALRMAR_HU_Pos             (16U)                                    
+#define RTC_ALRMAR_HU_Msk             (0xFUL << RTC_ALRMAR_HU_Pos)              /*!< 0x000F0000 */
+#define RTC_ALRMAR_HU                 RTC_ALRMAR_HU_Msk                        
+#define RTC_ALRMAR_HU_0               (0x1UL << RTC_ALRMAR_HU_Pos)              /*!< 0x00010000 */
+#define RTC_ALRMAR_HU_1               (0x2UL << RTC_ALRMAR_HU_Pos)              /*!< 0x00020000 */
+#define RTC_ALRMAR_HU_2               (0x4UL << RTC_ALRMAR_HU_Pos)              /*!< 0x00040000 */
+#define RTC_ALRMAR_HU_3               (0x8UL << RTC_ALRMAR_HU_Pos)              /*!< 0x00080000 */
+#define RTC_ALRMAR_MSK2_Pos           (15U)                                    
+#define RTC_ALRMAR_MSK2_Msk           (0x1UL << RTC_ALRMAR_MSK2_Pos)            /*!< 0x00008000 */
+#define RTC_ALRMAR_MSK2               RTC_ALRMAR_MSK2_Msk                      
+#define RTC_ALRMAR_MNT_Pos            (12U)                                    
+#define RTC_ALRMAR_MNT_Msk            (0x7UL << RTC_ALRMAR_MNT_Pos)             /*!< 0x00007000 */
+#define RTC_ALRMAR_MNT                RTC_ALRMAR_MNT_Msk                       
+#define RTC_ALRMAR_MNT_0              (0x1UL << RTC_ALRMAR_MNT_Pos)             /*!< 0x00001000 */
+#define RTC_ALRMAR_MNT_1              (0x2UL << RTC_ALRMAR_MNT_Pos)             /*!< 0x00002000 */
+#define RTC_ALRMAR_MNT_2              (0x4UL << RTC_ALRMAR_MNT_Pos)             /*!< 0x00004000 */
+#define RTC_ALRMAR_MNU_Pos            (8U)                                     
+#define RTC_ALRMAR_MNU_Msk            (0xFUL << RTC_ALRMAR_MNU_Pos)             /*!< 0x00000F00 */
+#define RTC_ALRMAR_MNU                RTC_ALRMAR_MNU_Msk                       
+#define RTC_ALRMAR_MNU_0              (0x1UL << RTC_ALRMAR_MNU_Pos)             /*!< 0x00000100 */
+#define RTC_ALRMAR_MNU_1              (0x2UL << RTC_ALRMAR_MNU_Pos)             /*!< 0x00000200 */
+#define RTC_ALRMAR_MNU_2              (0x4UL << RTC_ALRMAR_MNU_Pos)             /*!< 0x00000400 */
+#define RTC_ALRMAR_MNU_3              (0x8UL << RTC_ALRMAR_MNU_Pos)             /*!< 0x00000800 */
+#define RTC_ALRMAR_MSK1_Pos           (7U)                                     
+#define RTC_ALRMAR_MSK1_Msk           (0x1UL << RTC_ALRMAR_MSK1_Pos)            /*!< 0x00000080 */
+#define RTC_ALRMAR_MSK1               RTC_ALRMAR_MSK1_Msk                      
+#define RTC_ALRMAR_ST_Pos             (4U)                                     
+#define RTC_ALRMAR_ST_Msk             (0x7UL << RTC_ALRMAR_ST_Pos)              /*!< 0x00000070 */
+#define RTC_ALRMAR_ST                 RTC_ALRMAR_ST_Msk                        
+#define RTC_ALRMAR_ST_0               (0x1UL << RTC_ALRMAR_ST_Pos)              /*!< 0x00000010 */
+#define RTC_ALRMAR_ST_1               (0x2UL << RTC_ALRMAR_ST_Pos)              /*!< 0x00000020 */
+#define RTC_ALRMAR_ST_2               (0x4UL << RTC_ALRMAR_ST_Pos)              /*!< 0x00000040 */
+#define RTC_ALRMAR_SU_Pos             (0U)                                     
+#define RTC_ALRMAR_SU_Msk             (0xFUL << RTC_ALRMAR_SU_Pos)              /*!< 0x0000000F */
+#define RTC_ALRMAR_SU                 RTC_ALRMAR_SU_Msk                        
+#define RTC_ALRMAR_SU_0               (0x1UL << RTC_ALRMAR_SU_Pos)              /*!< 0x00000001 */
+#define RTC_ALRMAR_SU_1               (0x2UL << RTC_ALRMAR_SU_Pos)              /*!< 0x00000002 */
+#define RTC_ALRMAR_SU_2               (0x4UL << RTC_ALRMAR_SU_Pos)              /*!< 0x00000004 */
+#define RTC_ALRMAR_SU_3               (0x8UL << RTC_ALRMAR_SU_Pos)              /*!< 0x00000008 */
+
+/********************  Bits definition for RTC_ALRMBR register  ***************/
+#define RTC_ALRMBR_MSK4_Pos           (31U)                                    
+#define RTC_ALRMBR_MSK4_Msk           (0x1UL << RTC_ALRMBR_MSK4_Pos)            /*!< 0x80000000 */
+#define RTC_ALRMBR_MSK4               RTC_ALRMBR_MSK4_Msk                      
+#define RTC_ALRMBR_WDSEL_Pos          (30U)                                    
+#define RTC_ALRMBR_WDSEL_Msk          (0x1UL << RTC_ALRMBR_WDSEL_Pos)           /*!< 0x40000000 */
+#define RTC_ALRMBR_WDSEL              RTC_ALRMBR_WDSEL_Msk                     
+#define RTC_ALRMBR_DT_Pos             (28U)                                    
+#define RTC_ALRMBR_DT_Msk             (0x3UL << RTC_ALRMBR_DT_Pos)              /*!< 0x30000000 */
+#define RTC_ALRMBR_DT                 RTC_ALRMBR_DT_Msk                        
+#define RTC_ALRMBR_DT_0               (0x1UL << RTC_ALRMBR_DT_Pos)              /*!< 0x10000000 */
+#define RTC_ALRMBR_DT_1               (0x2UL << RTC_ALRMBR_DT_Pos)              /*!< 0x20000000 */
+#define RTC_ALRMBR_DU_Pos             (24U)                                    
+#define RTC_ALRMBR_DU_Msk             (0xFUL << RTC_ALRMBR_DU_Pos)              /*!< 0x0F000000 */
+#define RTC_ALRMBR_DU                 RTC_ALRMBR_DU_Msk                        
+#define RTC_ALRMBR_DU_0               (0x1UL << RTC_ALRMBR_DU_Pos)              /*!< 0x01000000 */
+#define RTC_ALRMBR_DU_1               (0x2UL << RTC_ALRMBR_DU_Pos)              /*!< 0x02000000 */
+#define RTC_ALRMBR_DU_2               (0x4UL << RTC_ALRMBR_DU_Pos)              /*!< 0x04000000 */
+#define RTC_ALRMBR_DU_3               (0x8UL << RTC_ALRMBR_DU_Pos)              /*!< 0x08000000 */
+#define RTC_ALRMBR_MSK3_Pos           (23U)                                    
+#define RTC_ALRMBR_MSK3_Msk           (0x1UL << RTC_ALRMBR_MSK3_Pos)            /*!< 0x00800000 */
+#define RTC_ALRMBR_MSK3               RTC_ALRMBR_MSK3_Msk                      
+#define RTC_ALRMBR_PM_Pos             (22U)                                    
+#define RTC_ALRMBR_PM_Msk             (0x1UL << RTC_ALRMBR_PM_Pos)              /*!< 0x00400000 */
+#define RTC_ALRMBR_PM                 RTC_ALRMBR_PM_Msk                        
+#define RTC_ALRMBR_HT_Pos             (20U)                                    
+#define RTC_ALRMBR_HT_Msk             (0x3UL << RTC_ALRMBR_HT_Pos)              /*!< 0x00300000 */
+#define RTC_ALRMBR_HT                 RTC_ALRMBR_HT_Msk                        
+#define RTC_ALRMBR_HT_0               (0x1UL << RTC_ALRMBR_HT_Pos)              /*!< 0x00100000 */
+#define RTC_ALRMBR_HT_1               (0x2UL << RTC_ALRMBR_HT_Pos)              /*!< 0x00200000 */
+#define RTC_ALRMBR_HU_Pos             (16U)                                    
+#define RTC_ALRMBR_HU_Msk             (0xFUL << RTC_ALRMBR_HU_Pos)              /*!< 0x000F0000 */
+#define RTC_ALRMBR_HU                 RTC_ALRMBR_HU_Msk                        
+#define RTC_ALRMBR_HU_0               (0x1UL << RTC_ALRMBR_HU_Pos)              /*!< 0x00010000 */
+#define RTC_ALRMBR_HU_1               (0x2UL << RTC_ALRMBR_HU_Pos)              /*!< 0x00020000 */
+#define RTC_ALRMBR_HU_2               (0x4UL << RTC_ALRMBR_HU_Pos)              /*!< 0x00040000 */
+#define RTC_ALRMBR_HU_3               (0x8UL << RTC_ALRMBR_HU_Pos)              /*!< 0x00080000 */
+#define RTC_ALRMBR_MSK2_Pos           (15U)                                    
+#define RTC_ALRMBR_MSK2_Msk           (0x1UL << RTC_ALRMBR_MSK2_Pos)            /*!< 0x00008000 */
+#define RTC_ALRMBR_MSK2               RTC_ALRMBR_MSK2_Msk                      
+#define RTC_ALRMBR_MNT_Pos            (12U)                                    
+#define RTC_ALRMBR_MNT_Msk            (0x7UL << RTC_ALRMBR_MNT_Pos)             /*!< 0x00007000 */
+#define RTC_ALRMBR_MNT                RTC_ALRMBR_MNT_Msk                       
+#define RTC_ALRMBR_MNT_0              (0x1UL << RTC_ALRMBR_MNT_Pos)             /*!< 0x00001000 */
+#define RTC_ALRMBR_MNT_1              (0x2UL << RTC_ALRMBR_MNT_Pos)             /*!< 0x00002000 */
+#define RTC_ALRMBR_MNT_2              (0x4UL << RTC_ALRMBR_MNT_Pos)             /*!< 0x00004000 */
+#define RTC_ALRMBR_MNU_Pos            (8U)                                     
+#define RTC_ALRMBR_MNU_Msk            (0xFUL << RTC_ALRMBR_MNU_Pos)             /*!< 0x00000F00 */
+#define RTC_ALRMBR_MNU                RTC_ALRMBR_MNU_Msk                       
+#define RTC_ALRMBR_MNU_0              (0x1UL << RTC_ALRMBR_MNU_Pos)             /*!< 0x00000100 */
+#define RTC_ALRMBR_MNU_1              (0x2UL << RTC_ALRMBR_MNU_Pos)             /*!< 0x00000200 */
+#define RTC_ALRMBR_MNU_2              (0x4UL << RTC_ALRMBR_MNU_Pos)             /*!< 0x00000400 */
+#define RTC_ALRMBR_MNU_3              (0x8UL << RTC_ALRMBR_MNU_Pos)             /*!< 0x00000800 */
+#define RTC_ALRMBR_MSK1_Pos           (7U)                                     
+#define RTC_ALRMBR_MSK1_Msk           (0x1UL << RTC_ALRMBR_MSK1_Pos)            /*!< 0x00000080 */
+#define RTC_ALRMBR_MSK1               RTC_ALRMBR_MSK1_Msk                      
+#define RTC_ALRMBR_ST_Pos             (4U)                                     
+#define RTC_ALRMBR_ST_Msk             (0x7UL << RTC_ALRMBR_ST_Pos)              /*!< 0x00000070 */
+#define RTC_ALRMBR_ST                 RTC_ALRMBR_ST_Msk                        
+#define RTC_ALRMBR_ST_0               (0x1UL << RTC_ALRMBR_ST_Pos)              /*!< 0x00000010 */
+#define RTC_ALRMBR_ST_1               (0x2UL << RTC_ALRMBR_ST_Pos)              /*!< 0x00000020 */
+#define RTC_ALRMBR_ST_2               (0x4UL << RTC_ALRMBR_ST_Pos)              /*!< 0x00000040 */
+#define RTC_ALRMBR_SU_Pos             (0U)                                     
+#define RTC_ALRMBR_SU_Msk             (0xFUL << RTC_ALRMBR_SU_Pos)              /*!< 0x0000000F */
+#define RTC_ALRMBR_SU                 RTC_ALRMBR_SU_Msk                        
+#define RTC_ALRMBR_SU_0               (0x1UL << RTC_ALRMBR_SU_Pos)              /*!< 0x00000001 */
+#define RTC_ALRMBR_SU_1               (0x2UL << RTC_ALRMBR_SU_Pos)              /*!< 0x00000002 */
+#define RTC_ALRMBR_SU_2               (0x4UL << RTC_ALRMBR_SU_Pos)              /*!< 0x00000004 */
+#define RTC_ALRMBR_SU_3               (0x8UL << RTC_ALRMBR_SU_Pos)              /*!< 0x00000008 */
+
+/********************  Bits definition for RTC_WPR register  ******************/
+#define RTC_WPR_KEY_Pos               (0U)                                     
+#define RTC_WPR_KEY_Msk               (0xFFUL << RTC_WPR_KEY_Pos)               /*!< 0x000000FF */
+#define RTC_WPR_KEY                   RTC_WPR_KEY_Msk                          
+
+/********************  Bits definition for RTC_SSR register  ******************/
+#define RTC_SSR_SS_Pos                (0U)                                     
+#define RTC_SSR_SS_Msk                (0xFFFFUL << RTC_SSR_SS_Pos)              /*!< 0x0000FFFF */
+#define RTC_SSR_SS                    RTC_SSR_SS_Msk                           
+
+/********************  Bits definition for RTC_SHIFTR register  ***************/
+#define RTC_SHIFTR_SUBFS_Pos          (0U)                                     
+#define RTC_SHIFTR_SUBFS_Msk          (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos)        /*!< 0x00007FFF */
+#define RTC_SHIFTR_SUBFS              RTC_SHIFTR_SUBFS_Msk                     
+#define RTC_SHIFTR_ADD1S_Pos          (31U)                                    
+#define RTC_SHIFTR_ADD1S_Msk          (0x1UL << RTC_SHIFTR_ADD1S_Pos)           /*!< 0x80000000 */
+#define RTC_SHIFTR_ADD1S              RTC_SHIFTR_ADD1S_Msk                     
+
+/********************  Bits definition for RTC_TSTR register  *****************/
+#define RTC_TSTR_PM_Pos               (22U)                                    
+#define RTC_TSTR_PM_Msk               (0x1UL << RTC_TSTR_PM_Pos)                /*!< 0x00400000 */
+#define RTC_TSTR_PM                   RTC_TSTR_PM_Msk                          
+#define RTC_TSTR_HT_Pos               (20U)                                    
+#define RTC_TSTR_HT_Msk               (0x3UL << RTC_TSTR_HT_Pos)                /*!< 0x00300000 */
+#define RTC_TSTR_HT                   RTC_TSTR_HT_Msk                          
+#define RTC_TSTR_HT_0                 (0x1UL << RTC_TSTR_HT_Pos)                /*!< 0x00100000 */
+#define RTC_TSTR_HT_1                 (0x2UL << RTC_TSTR_HT_Pos)                /*!< 0x00200000 */
+#define RTC_TSTR_HU_Pos               (16U)                                    
+#define RTC_TSTR_HU_Msk               (0xFUL << RTC_TSTR_HU_Pos)                /*!< 0x000F0000 */
+#define RTC_TSTR_HU                   RTC_TSTR_HU_Msk                          
+#define RTC_TSTR_HU_0                 (0x1UL << RTC_TSTR_HU_Pos)                /*!< 0x00010000 */
+#define RTC_TSTR_HU_1                 (0x2UL << RTC_TSTR_HU_Pos)                /*!< 0x00020000 */
+#define RTC_TSTR_HU_2                 (0x4UL << RTC_TSTR_HU_Pos)                /*!< 0x00040000 */
+#define RTC_TSTR_HU_3                 (0x8UL << RTC_TSTR_HU_Pos)                /*!< 0x00080000 */
+#define RTC_TSTR_MNT_Pos              (12U)                                    
+#define RTC_TSTR_MNT_Msk              (0x7UL << RTC_TSTR_MNT_Pos)               /*!< 0x00007000 */
+#define RTC_TSTR_MNT                  RTC_TSTR_MNT_Msk                         
+#define RTC_TSTR_MNT_0                (0x1UL << RTC_TSTR_MNT_Pos)               /*!< 0x00001000 */
+#define RTC_TSTR_MNT_1                (0x2UL << RTC_TSTR_MNT_Pos)               /*!< 0x00002000 */
+#define RTC_TSTR_MNT_2                (0x4UL << RTC_TSTR_MNT_Pos)               /*!< 0x00004000 */
+#define RTC_TSTR_MNU_Pos              (8U)                                     
+#define RTC_TSTR_MNU_Msk              (0xFUL << RTC_TSTR_MNU_Pos)               /*!< 0x00000F00 */
+#define RTC_TSTR_MNU                  RTC_TSTR_MNU_Msk                         
+#define RTC_TSTR_MNU_0                (0x1UL << RTC_TSTR_MNU_Pos)               /*!< 0x00000100 */
+#define RTC_TSTR_MNU_1                (0x2UL << RTC_TSTR_MNU_Pos)               /*!< 0x00000200 */
+#define RTC_TSTR_MNU_2                (0x4UL << RTC_TSTR_MNU_Pos)               /*!< 0x00000400 */
+#define RTC_TSTR_MNU_3                (0x8UL << RTC_TSTR_MNU_Pos)               /*!< 0x00000800 */
+#define RTC_TSTR_ST_Pos               (4U)                                     
+#define RTC_TSTR_ST_Msk               (0x7UL << RTC_TSTR_ST_Pos)                /*!< 0x00000070 */
+#define RTC_TSTR_ST                   RTC_TSTR_ST_Msk                          
+#define RTC_TSTR_ST_0                 (0x1UL << RTC_TSTR_ST_Pos)                /*!< 0x00000010 */
+#define RTC_TSTR_ST_1                 (0x2UL << RTC_TSTR_ST_Pos)                /*!< 0x00000020 */
+#define RTC_TSTR_ST_2                 (0x4UL << RTC_TSTR_ST_Pos)                /*!< 0x00000040 */
+#define RTC_TSTR_SU_Pos               (0U)                                     
+#define RTC_TSTR_SU_Msk               (0xFUL << RTC_TSTR_SU_Pos)                /*!< 0x0000000F */
+#define RTC_TSTR_SU                   RTC_TSTR_SU_Msk                          
+#define RTC_TSTR_SU_0                 (0x1UL << RTC_TSTR_SU_Pos)                /*!< 0x00000001 */
+#define RTC_TSTR_SU_1                 (0x2UL << RTC_TSTR_SU_Pos)                /*!< 0x00000002 */
+#define RTC_TSTR_SU_2                 (0x4UL << RTC_TSTR_SU_Pos)                /*!< 0x00000004 */
+#define RTC_TSTR_SU_3                 (0x8UL << RTC_TSTR_SU_Pos)                /*!< 0x00000008 */
+
+/********************  Bits definition for RTC_TSDR register  *****************/
+#define RTC_TSDR_WDU_Pos              (13U)                                    
+#define RTC_TSDR_WDU_Msk              (0x7UL << RTC_TSDR_WDU_Pos)               /*!< 0x0000E000 */
+#define RTC_TSDR_WDU                  RTC_TSDR_WDU_Msk                         
+#define RTC_TSDR_WDU_0                (0x1UL << RTC_TSDR_WDU_Pos)               /*!< 0x00002000 */
+#define RTC_TSDR_WDU_1                (0x2UL << RTC_TSDR_WDU_Pos)               /*!< 0x00004000 */
+#define RTC_TSDR_WDU_2                (0x4UL << RTC_TSDR_WDU_Pos)               /*!< 0x00008000 */
+#define RTC_TSDR_MT_Pos               (12U)                                    
+#define RTC_TSDR_MT_Msk               (0x1UL << RTC_TSDR_MT_Pos)                /*!< 0x00001000 */
+#define RTC_TSDR_MT                   RTC_TSDR_MT_Msk                          
+#define RTC_TSDR_MU_Pos               (8U)                                     
+#define RTC_TSDR_MU_Msk               (0xFUL << RTC_TSDR_MU_Pos)                /*!< 0x00000F00 */
+#define RTC_TSDR_MU                   RTC_TSDR_MU_Msk                          
+#define RTC_TSDR_MU_0                 (0x1UL << RTC_TSDR_MU_Pos)                /*!< 0x00000100 */
+#define RTC_TSDR_MU_1                 (0x2UL << RTC_TSDR_MU_Pos)                /*!< 0x00000200 */
+#define RTC_TSDR_MU_2                 (0x4UL << RTC_TSDR_MU_Pos)                /*!< 0x00000400 */
+#define RTC_TSDR_MU_3                 (0x8UL << RTC_TSDR_MU_Pos)                /*!< 0x00000800 */
+#define RTC_TSDR_DT_Pos               (4U)                                     
+#define RTC_TSDR_DT_Msk               (0x3UL << RTC_TSDR_DT_Pos)                /*!< 0x00000030 */
+#define RTC_TSDR_DT                   RTC_TSDR_DT_Msk                          
+#define RTC_TSDR_DT_0                 (0x1UL << RTC_TSDR_DT_Pos)                /*!< 0x00000010 */
+#define RTC_TSDR_DT_1                 (0x2UL << RTC_TSDR_DT_Pos)                /*!< 0x00000020 */
+#define RTC_TSDR_DU_Pos               (0U)                                     
+#define RTC_TSDR_DU_Msk               (0xFUL << RTC_TSDR_DU_Pos)                /*!< 0x0000000F */
+#define RTC_TSDR_DU                   RTC_TSDR_DU_Msk                          
+#define RTC_TSDR_DU_0                 (0x1UL << RTC_TSDR_DU_Pos)                /*!< 0x00000001 */
+#define RTC_TSDR_DU_1                 (0x2UL << RTC_TSDR_DU_Pos)                /*!< 0x00000002 */
+#define RTC_TSDR_DU_2                 (0x4UL << RTC_TSDR_DU_Pos)                /*!< 0x00000004 */
+#define RTC_TSDR_DU_3                 (0x8UL << RTC_TSDR_DU_Pos)                /*!< 0x00000008 */
+
+/********************  Bits definition for RTC_TSSSR register  ****************/
+#define RTC_TSSSR_SS_Pos              (0U)                                     
+#define RTC_TSSSR_SS_Msk              (0xFFFFUL << RTC_TSSSR_SS_Pos)            /*!< 0x0000FFFF */
+#define RTC_TSSSR_SS                  RTC_TSSSR_SS_Msk                         
+
+/********************  Bits definition for RTC_CAL register  *****************/
+#define RTC_CALR_CALP_Pos             (15U)                                    
+#define RTC_CALR_CALP_Msk             (0x1UL << RTC_CALR_CALP_Pos)              /*!< 0x00008000 */
+#define RTC_CALR_CALP                 RTC_CALR_CALP_Msk                        
+#define RTC_CALR_CALW8_Pos            (14U)                                    
+#define RTC_CALR_CALW8_Msk            (0x1UL << RTC_CALR_CALW8_Pos)             /*!< 0x00004000 */
+#define RTC_CALR_CALW8                RTC_CALR_CALW8_Msk                       
+#define RTC_CALR_CALW16_Pos           (13U)                                    
+#define RTC_CALR_CALW16_Msk           (0x1UL << RTC_CALR_CALW16_Pos)            /*!< 0x00002000 */
+#define RTC_CALR_CALW16               RTC_CALR_CALW16_Msk                      
+#define RTC_CALR_CALM_Pos             (0U)                                     
+#define RTC_CALR_CALM_Msk             (0x1FFUL << RTC_CALR_CALM_Pos)            /*!< 0x000001FF */
+#define RTC_CALR_CALM                 RTC_CALR_CALM_Msk                        
+#define RTC_CALR_CALM_0               (0x001UL << RTC_CALR_CALM_Pos)            /*!< 0x00000001 */
+#define RTC_CALR_CALM_1               (0x002UL << RTC_CALR_CALM_Pos)            /*!< 0x00000002 */
+#define RTC_CALR_CALM_2               (0x004UL << RTC_CALR_CALM_Pos)            /*!< 0x00000004 */
+#define RTC_CALR_CALM_3               (0x008UL << RTC_CALR_CALM_Pos)            /*!< 0x00000008 */
+#define RTC_CALR_CALM_4               (0x010UL << RTC_CALR_CALM_Pos)            /*!< 0x00000010 */
+#define RTC_CALR_CALM_5               (0x020UL << RTC_CALR_CALM_Pos)            /*!< 0x00000020 */
+#define RTC_CALR_CALM_6               (0x040UL << RTC_CALR_CALM_Pos)            /*!< 0x00000040 */
+#define RTC_CALR_CALM_7               (0x080UL << RTC_CALR_CALM_Pos)            /*!< 0x00000080 */
+#define RTC_CALR_CALM_8               (0x100UL << RTC_CALR_CALM_Pos)            /*!< 0x00000100 */
+
+/********************  Bits definition for RTC_TAFCR register  ****************/
+#define RTC_TAFCR_ALARMOUTTYPE_Pos    (18U)                                    
+#define RTC_TAFCR_ALARMOUTTYPE_Msk    (0x1UL << RTC_TAFCR_ALARMOUTTYPE_Pos)     /*!< 0x00040000 */
+#define RTC_TAFCR_ALARMOUTTYPE        RTC_TAFCR_ALARMOUTTYPE_Msk               
+#define RTC_TAFCR_TSINSEL_Pos         (17U)                                    
+#define RTC_TAFCR_TSINSEL_Msk         (0x1UL << RTC_TAFCR_TSINSEL_Pos)          /*!< 0x00020000 */
+#define RTC_TAFCR_TSINSEL             RTC_TAFCR_TSINSEL_Msk                    
+#define RTC_TAFCR_TAMP1INSEL_Pos      (16U)                                    
+#define RTC_TAFCR_TAMP1INSEL_Msk      (0x1UL << RTC_TAFCR_TAMP1INSEL_Pos)        /*!< 0x00010000 */
+#define RTC_TAFCR_TAMP1INSEL          RTC_TAFCR_TAMP1INSEL_Msk                  
+#define RTC_TAFCR_TAMPPUDIS_Pos       (15U)                                    
+#define RTC_TAFCR_TAMPPUDIS_Msk       (0x1UL << RTC_TAFCR_TAMPPUDIS_Pos)        /*!< 0x00008000 */
+#define RTC_TAFCR_TAMPPUDIS           RTC_TAFCR_TAMPPUDIS_Msk                  
+#define RTC_TAFCR_TAMPPRCH_Pos        (13U)                                    
+#define RTC_TAFCR_TAMPPRCH_Msk        (0x3UL << RTC_TAFCR_TAMPPRCH_Pos)         /*!< 0x00006000 */
+#define RTC_TAFCR_TAMPPRCH            RTC_TAFCR_TAMPPRCH_Msk                   
+#define RTC_TAFCR_TAMPPRCH_0          (0x1UL << RTC_TAFCR_TAMPPRCH_Pos)         /*!< 0x00002000 */
+#define RTC_TAFCR_TAMPPRCH_1          (0x2UL << RTC_TAFCR_TAMPPRCH_Pos)         /*!< 0x00004000 */
+#define RTC_TAFCR_TAMPFLT_Pos         (11U)                                    
+#define RTC_TAFCR_TAMPFLT_Msk         (0x3UL << RTC_TAFCR_TAMPFLT_Pos)          /*!< 0x00001800 */
+#define RTC_TAFCR_TAMPFLT             RTC_TAFCR_TAMPFLT_Msk                    
+#define RTC_TAFCR_TAMPFLT_0           (0x1UL << RTC_TAFCR_TAMPFLT_Pos)          /*!< 0x00000800 */
+#define RTC_TAFCR_TAMPFLT_1           (0x2UL << RTC_TAFCR_TAMPFLT_Pos)          /*!< 0x00001000 */
+#define RTC_TAFCR_TAMPFREQ_Pos        (8U)                                     
+#define RTC_TAFCR_TAMPFREQ_Msk        (0x7UL << RTC_TAFCR_TAMPFREQ_Pos)         /*!< 0x00000700 */
+#define RTC_TAFCR_TAMPFREQ            RTC_TAFCR_TAMPFREQ_Msk                   
+#define RTC_TAFCR_TAMPFREQ_0          (0x1UL << RTC_TAFCR_TAMPFREQ_Pos)         /*!< 0x00000100 */
+#define RTC_TAFCR_TAMPFREQ_1          (0x2UL << RTC_TAFCR_TAMPFREQ_Pos)         /*!< 0x00000200 */
+#define RTC_TAFCR_TAMPFREQ_2          (0x4UL << RTC_TAFCR_TAMPFREQ_Pos)         /*!< 0x00000400 */
+#define RTC_TAFCR_TAMPTS_Pos          (7U)                                     
+#define RTC_TAFCR_TAMPTS_Msk          (0x1UL << RTC_TAFCR_TAMPTS_Pos)           /*!< 0x00000080 */
+#define RTC_TAFCR_TAMPTS              RTC_TAFCR_TAMPTS_Msk                     
+#define RTC_TAFCR_TAMP2TRG_Pos        (4U)                                     
+#define RTC_TAFCR_TAMP2TRG_Msk        (0x1UL << RTC_TAFCR_TAMP2TRG_Pos)         /*!< 0x00000010 */
+#define RTC_TAFCR_TAMP2TRG            RTC_TAFCR_TAMP2TRG_Msk                   
+#define RTC_TAFCR_TAMP2E_Pos          (3U)                                     
+#define RTC_TAFCR_TAMP2E_Msk          (0x1UL << RTC_TAFCR_TAMP2E_Pos)           /*!< 0x00000008 */
+#define RTC_TAFCR_TAMP2E              RTC_TAFCR_TAMP2E_Msk                     
+#define RTC_TAFCR_TAMPIE_Pos          (2U)                                     
+#define RTC_TAFCR_TAMPIE_Msk          (0x1UL << RTC_TAFCR_TAMPIE_Pos)           /*!< 0x00000004 */
+#define RTC_TAFCR_TAMPIE              RTC_TAFCR_TAMPIE_Msk                     
+#define RTC_TAFCR_TAMP1TRG_Pos        (1U)                                     
+#define RTC_TAFCR_TAMP1TRG_Msk        (0x1UL << RTC_TAFCR_TAMP1TRG_Pos)         /*!< 0x00000002 */
+#define RTC_TAFCR_TAMP1TRG            RTC_TAFCR_TAMP1TRG_Msk                   
+#define RTC_TAFCR_TAMP1E_Pos          (0U)                                     
+#define RTC_TAFCR_TAMP1E_Msk          (0x1UL << RTC_TAFCR_TAMP1E_Pos)           /*!< 0x00000001 */
+#define RTC_TAFCR_TAMP1E              RTC_TAFCR_TAMP1E_Msk                     
+
+/* Legacy defines */
+#define RTC_TAFCR_TAMPINSEL           RTC_TAFCR_TAMP1INSEL
+
+/********************  Bits definition for RTC_ALRMASSR register  *************/
+#define RTC_ALRMASSR_MASKSS_Pos       (24U)                                    
+#define RTC_ALRMASSR_MASKSS_Msk       (0xFUL << RTC_ALRMASSR_MASKSS_Pos)        /*!< 0x0F000000 */
+#define RTC_ALRMASSR_MASKSS           RTC_ALRMASSR_MASKSS_Msk                  
+#define RTC_ALRMASSR_MASKSS_0         (0x1UL << RTC_ALRMASSR_MASKSS_Pos)        /*!< 0x01000000 */
+#define RTC_ALRMASSR_MASKSS_1         (0x2UL << RTC_ALRMASSR_MASKSS_Pos)        /*!< 0x02000000 */
+#define RTC_ALRMASSR_MASKSS_2         (0x4UL << RTC_ALRMASSR_MASKSS_Pos)        /*!< 0x04000000 */
+#define RTC_ALRMASSR_MASKSS_3         (0x8UL << RTC_ALRMASSR_MASKSS_Pos)        /*!< 0x08000000 */
+#define RTC_ALRMASSR_SS_Pos           (0U)                                     
+#define RTC_ALRMASSR_SS_Msk           (0x7FFFUL << RTC_ALRMASSR_SS_Pos)         /*!< 0x00007FFF */
+#define RTC_ALRMASSR_SS               RTC_ALRMASSR_SS_Msk                      
+
+/********************  Bits definition for RTC_ALRMBSSR register  *************/
+#define RTC_ALRMBSSR_MASKSS_Pos       (24U)                                    
+#define RTC_ALRMBSSR_MASKSS_Msk       (0xFUL << RTC_ALRMBSSR_MASKSS_Pos)        /*!< 0x0F000000 */
+#define RTC_ALRMBSSR_MASKSS           RTC_ALRMBSSR_MASKSS_Msk                  
+#define RTC_ALRMBSSR_MASKSS_0         (0x1UL << RTC_ALRMBSSR_MASKSS_Pos)        /*!< 0x01000000 */
+#define RTC_ALRMBSSR_MASKSS_1         (0x2UL << RTC_ALRMBSSR_MASKSS_Pos)        /*!< 0x02000000 */
+#define RTC_ALRMBSSR_MASKSS_2         (0x4UL << RTC_ALRMBSSR_MASKSS_Pos)        /*!< 0x04000000 */
+#define RTC_ALRMBSSR_MASKSS_3         (0x8UL << RTC_ALRMBSSR_MASKSS_Pos)        /*!< 0x08000000 */
+#define RTC_ALRMBSSR_SS_Pos           (0U)                                     
+#define RTC_ALRMBSSR_SS_Msk           (0x7FFFUL << RTC_ALRMBSSR_SS_Pos)         /*!< 0x00007FFF */
+#define RTC_ALRMBSSR_SS               RTC_ALRMBSSR_SS_Msk                      
+
+/********************  Bits definition for RTC_BKP0R register  ****************/
+#define RTC_BKP0R_Pos                 (0U)                                     
+#define RTC_BKP0R_Msk                 (0xFFFFFFFFUL << RTC_BKP0R_Pos)           /*!< 0xFFFFFFFF */
+#define RTC_BKP0R                     RTC_BKP0R_Msk                            
+
+/********************  Bits definition for RTC_BKP1R register  ****************/
+#define RTC_BKP1R_Pos                 (0U)                                     
+#define RTC_BKP1R_Msk                 (0xFFFFFFFFUL << RTC_BKP1R_Pos)           /*!< 0xFFFFFFFF */
+#define RTC_BKP1R                     RTC_BKP1R_Msk                            
+
+/********************  Bits definition for RTC_BKP2R register  ****************/
+#define RTC_BKP2R_Pos                 (0U)                                     
+#define RTC_BKP2R_Msk                 (0xFFFFFFFFUL << RTC_BKP2R_Pos)           /*!< 0xFFFFFFFF */
+#define RTC_BKP2R                     RTC_BKP2R_Msk                            
+
+/********************  Bits definition for RTC_BKP3R register  ****************/
+#define RTC_BKP3R_Pos                 (0U)                                     
+#define RTC_BKP3R_Msk                 (0xFFFFFFFFUL << RTC_BKP3R_Pos)           /*!< 0xFFFFFFFF */
+#define RTC_BKP3R                     RTC_BKP3R_Msk                            
+
+/********************  Bits definition for RTC_BKP4R register  ****************/
+#define RTC_BKP4R_Pos                 (0U)                                     
+#define RTC_BKP4R_Msk                 (0xFFFFFFFFUL << RTC_BKP4R_Pos)           /*!< 0xFFFFFFFF */
+#define RTC_BKP4R                     RTC_BKP4R_Msk                            
+
+/********************  Bits definition for RTC_BKP5R register  ****************/
+#define RTC_BKP5R_Pos                 (0U)                                     
+#define RTC_BKP5R_Msk                 (0xFFFFFFFFUL << RTC_BKP5R_Pos)           /*!< 0xFFFFFFFF */
+#define RTC_BKP5R                     RTC_BKP5R_Msk                            
+
+/********************  Bits definition for RTC_BKP6R register  ****************/
+#define RTC_BKP6R_Pos                 (0U)                                     
+#define RTC_BKP6R_Msk                 (0xFFFFFFFFUL << RTC_BKP6R_Pos)           /*!< 0xFFFFFFFF */
+#define RTC_BKP6R                     RTC_BKP6R_Msk                            
+
+/********************  Bits definition for RTC_BKP7R register  ****************/
+#define RTC_BKP7R_Pos                 (0U)                                     
+#define RTC_BKP7R_Msk                 (0xFFFFFFFFUL << RTC_BKP7R_Pos)           /*!< 0xFFFFFFFF */
+#define RTC_BKP7R                     RTC_BKP7R_Msk                            
+
+/********************  Bits definition for RTC_BKP8R register  ****************/
+#define RTC_BKP8R_Pos                 (0U)                                     
+#define RTC_BKP8R_Msk                 (0xFFFFFFFFUL << RTC_BKP8R_Pos)           /*!< 0xFFFFFFFF */
+#define RTC_BKP8R                     RTC_BKP8R_Msk                            
+
+/********************  Bits definition for RTC_BKP9R register  ****************/
+#define RTC_BKP9R_Pos                 (0U)                                     
+#define RTC_BKP9R_Msk                 (0xFFFFFFFFUL << RTC_BKP9R_Pos)           /*!< 0xFFFFFFFF */
+#define RTC_BKP9R                     RTC_BKP9R_Msk                            
+
+/********************  Bits definition for RTC_BKP10R register  ***************/
+#define RTC_BKP10R_Pos                (0U)                                     
+#define RTC_BKP10R_Msk                (0xFFFFFFFFUL << RTC_BKP10R_Pos)          /*!< 0xFFFFFFFF */
+#define RTC_BKP10R                    RTC_BKP10R_Msk                           
+
+/********************  Bits definition for RTC_BKP11R register  ***************/
+#define RTC_BKP11R_Pos                (0U)                                     
+#define RTC_BKP11R_Msk                (0xFFFFFFFFUL << RTC_BKP11R_Pos)          /*!< 0xFFFFFFFF */
+#define RTC_BKP11R                    RTC_BKP11R_Msk                           
+
+/********************  Bits definition for RTC_BKP12R register  ***************/
+#define RTC_BKP12R_Pos                (0U)                                     
+#define RTC_BKP12R_Msk                (0xFFFFFFFFUL << RTC_BKP12R_Pos)          /*!< 0xFFFFFFFF */
+#define RTC_BKP12R                    RTC_BKP12R_Msk                           
+
+/********************  Bits definition for RTC_BKP13R register  ***************/
+#define RTC_BKP13R_Pos                (0U)                                     
+#define RTC_BKP13R_Msk                (0xFFFFFFFFUL << RTC_BKP13R_Pos)          /*!< 0xFFFFFFFF */
+#define RTC_BKP13R                    RTC_BKP13R_Msk                           
+
+/********************  Bits definition for RTC_BKP14R register  ***************/
+#define RTC_BKP14R_Pos                (0U)                                     
+#define RTC_BKP14R_Msk                (0xFFFFFFFFUL << RTC_BKP14R_Pos)          /*!< 0xFFFFFFFF */
+#define RTC_BKP14R                    RTC_BKP14R_Msk                           
+
+/********************  Bits definition for RTC_BKP15R register  ***************/
+#define RTC_BKP15R_Pos                (0U)                                     
+#define RTC_BKP15R_Msk                (0xFFFFFFFFUL << RTC_BKP15R_Pos)          /*!< 0xFFFFFFFF */
+#define RTC_BKP15R                    RTC_BKP15R_Msk                           
+
+/********************  Bits definition for RTC_BKP16R register  ***************/
+#define RTC_BKP16R_Pos                (0U)                                     
+#define RTC_BKP16R_Msk                (0xFFFFFFFFUL << RTC_BKP16R_Pos)          /*!< 0xFFFFFFFF */
+#define RTC_BKP16R                    RTC_BKP16R_Msk                           
+
+/********************  Bits definition for RTC_BKP17R register  ***************/
+#define RTC_BKP17R_Pos                (0U)                                     
+#define RTC_BKP17R_Msk                (0xFFFFFFFFUL << RTC_BKP17R_Pos)          /*!< 0xFFFFFFFF */
+#define RTC_BKP17R                    RTC_BKP17R_Msk                           
+
+/********************  Bits definition for RTC_BKP18R register  ***************/
+#define RTC_BKP18R_Pos                (0U)                                     
+#define RTC_BKP18R_Msk                (0xFFFFFFFFUL << RTC_BKP18R_Pos)          /*!< 0xFFFFFFFF */
+#define RTC_BKP18R                    RTC_BKP18R_Msk                           
+
+/********************  Bits definition for RTC_BKP19R register  ***************/
+#define RTC_BKP19R_Pos                (0U)                                     
+#define RTC_BKP19R_Msk                (0xFFFFFFFFUL << RTC_BKP19R_Pos)          /*!< 0xFFFFFFFF */
+#define RTC_BKP19R                    RTC_BKP19R_Msk                           
+
+/******************** Number of backup registers ******************************/
+#define RTC_BKP_NUMBER                       0x000000014U
+    
+/******************************************************************************/
+/*                                                                            */
+/*                          Serial Audio Interface                            */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bit definition for SAI_GCR register  *******************/
+#define SAI_GCR_SYNCIN_Pos         (0U)                                        
+#define SAI_GCR_SYNCIN_Msk         (0x3UL << SAI_GCR_SYNCIN_Pos)                /*!< 0x00000003 */
+#define SAI_GCR_SYNCIN             SAI_GCR_SYNCIN_Msk                          /*!<SYNCIN[1:0] bits (Synchronization Inputs)   */
+#define SAI_GCR_SYNCIN_0           (0x1UL << SAI_GCR_SYNCIN_Pos)                /*!< 0x00000001 */
+#define SAI_GCR_SYNCIN_1           (0x2UL << SAI_GCR_SYNCIN_Pos)                /*!< 0x00000002 */
+
+#define SAI_GCR_SYNCOUT_Pos        (4U)                                        
+#define SAI_GCR_SYNCOUT_Msk        (0x3UL << SAI_GCR_SYNCOUT_Pos)               /*!< 0x00000030 */
+#define SAI_GCR_SYNCOUT            SAI_GCR_SYNCOUT_Msk                         /*!<SYNCOUT[1:0] bits (Synchronization Outputs) */
+#define SAI_GCR_SYNCOUT_0          (0x1UL << SAI_GCR_SYNCOUT_Pos)               /*!< 0x00000010 */
+#define SAI_GCR_SYNCOUT_1          (0x2UL << SAI_GCR_SYNCOUT_Pos)               /*!< 0x00000020 */
+
+/*******************  Bit definition for SAI_xCR1 register  *******************/
+#define SAI_xCR1_MODE_Pos          (0U)                                        
+#define SAI_xCR1_MODE_Msk          (0x3UL << SAI_xCR1_MODE_Pos)                 /*!< 0x00000003 */
+#define SAI_xCR1_MODE              SAI_xCR1_MODE_Msk                           /*!<MODE[1:0] bits (Audio Block Mode)           */
+#define SAI_xCR1_MODE_0            (0x1UL << SAI_xCR1_MODE_Pos)                 /*!< 0x00000001 */
+#define SAI_xCR1_MODE_1            (0x2UL << SAI_xCR1_MODE_Pos)                 /*!< 0x00000002 */
+
+#define SAI_xCR1_PRTCFG_Pos        (2U)                                        
+#define SAI_xCR1_PRTCFG_Msk        (0x3UL << SAI_xCR1_PRTCFG_Pos)               /*!< 0x0000000C */
+#define SAI_xCR1_PRTCFG            SAI_xCR1_PRTCFG_Msk                         /*!<PRTCFG[1:0] bits (Protocol Configuration)   */
+#define SAI_xCR1_PRTCFG_0          (0x1UL << SAI_xCR1_PRTCFG_Pos)               /*!< 0x00000004 */
+#define SAI_xCR1_PRTCFG_1          (0x2UL << SAI_xCR1_PRTCFG_Pos)               /*!< 0x00000008 */
+
+#define SAI_xCR1_DS_Pos            (5U)                                        
+#define SAI_xCR1_DS_Msk            (0x7UL << SAI_xCR1_DS_Pos)                   /*!< 0x000000E0 */
+#define SAI_xCR1_DS                SAI_xCR1_DS_Msk                             /*!<DS[1:0] bits (Data Size) */
+#define SAI_xCR1_DS_0              (0x1UL << SAI_xCR1_DS_Pos)                   /*!< 0x00000020 */
+#define SAI_xCR1_DS_1              (0x2UL << SAI_xCR1_DS_Pos)                   /*!< 0x00000040 */
+#define SAI_xCR1_DS_2              (0x4UL << SAI_xCR1_DS_Pos)                   /*!< 0x00000080 */
+
+#define SAI_xCR1_LSBFIRST_Pos      (8U)                                        
+#define SAI_xCR1_LSBFIRST_Msk      (0x1UL << SAI_xCR1_LSBFIRST_Pos)             /*!< 0x00000100 */
+#define SAI_xCR1_LSBFIRST          SAI_xCR1_LSBFIRST_Msk                       /*!<LSB First Configuration  */
+#define SAI_xCR1_CKSTR_Pos         (9U)                                        
+#define SAI_xCR1_CKSTR_Msk         (0x1UL << SAI_xCR1_CKSTR_Pos)                /*!< 0x00000200 */
+#define SAI_xCR1_CKSTR             SAI_xCR1_CKSTR_Msk                          /*!<ClocK STRobing edge      */
+
+#define SAI_xCR1_SYNCEN_Pos        (10U)                                       
+#define SAI_xCR1_SYNCEN_Msk        (0x3UL << SAI_xCR1_SYNCEN_Pos)               /*!< 0x00000C00 */
+#define SAI_xCR1_SYNCEN            SAI_xCR1_SYNCEN_Msk                         /*!<SYNCEN[1:0](SYNChronization ENable) */
+#define SAI_xCR1_SYNCEN_0          (0x1UL << SAI_xCR1_SYNCEN_Pos)               /*!< 0x00000400 */
+#define SAI_xCR1_SYNCEN_1          (0x2UL << SAI_xCR1_SYNCEN_Pos)               /*!< 0x00000800 */
+
+#define SAI_xCR1_MONO_Pos          (12U)                                       
+#define SAI_xCR1_MONO_Msk          (0x1UL << SAI_xCR1_MONO_Pos)                 /*!< 0x00001000 */
+#define SAI_xCR1_MONO              SAI_xCR1_MONO_Msk                           /*!<Mono mode                  */
+#define SAI_xCR1_OUTDRIV_Pos       (13U)                                       
+#define SAI_xCR1_OUTDRIV_Msk       (0x1UL << SAI_xCR1_OUTDRIV_Pos)              /*!< 0x00002000 */
+#define SAI_xCR1_OUTDRIV           SAI_xCR1_OUTDRIV_Msk                        /*!<Output Drive               */
+#define SAI_xCR1_SAIEN_Pos         (16U)                                       
+#define SAI_xCR1_SAIEN_Msk         (0x1UL << SAI_xCR1_SAIEN_Pos)                /*!< 0x00010000 */
+#define SAI_xCR1_SAIEN             SAI_xCR1_SAIEN_Msk                          /*!<Audio Block enable         */
+#define SAI_xCR1_DMAEN_Pos         (17U)                                       
+#define SAI_xCR1_DMAEN_Msk         (0x1UL << SAI_xCR1_DMAEN_Pos)                /*!< 0x00020000 */
+#define SAI_xCR1_DMAEN             SAI_xCR1_DMAEN_Msk                          /*!<DMA enable                 */
+#define SAI_xCR1_NODIV_Pos         (19U)                                       
+#define SAI_xCR1_NODIV_Msk         (0x1UL << SAI_xCR1_NODIV_Pos)                /*!< 0x00080000 */
+#define SAI_xCR1_NODIV             SAI_xCR1_NODIV_Msk                          /*!<No Divider Configuration   */
+
+#define SAI_xCR1_MCKDIV_Pos        (20U)                                       
+#define SAI_xCR1_MCKDIV_Msk        (0xFUL << SAI_xCR1_MCKDIV_Pos)               /*!< 0x00F00000 */
+#define SAI_xCR1_MCKDIV            SAI_xCR1_MCKDIV_Msk                         /*!<MCKDIV[3:0] (Master ClocK Divider)  */
+#define SAI_xCR1_MCKDIV_0          (0x1UL << SAI_xCR1_MCKDIV_Pos)               /*!< 0x00100000 */
+#define SAI_xCR1_MCKDIV_1          (0x2UL << SAI_xCR1_MCKDIV_Pos)               /*!< 0x00200000 */
+#define SAI_xCR1_MCKDIV_2          (0x4UL << SAI_xCR1_MCKDIV_Pos)               /*!< 0x00400000 */
+#define SAI_xCR1_MCKDIV_3          (0x8UL << SAI_xCR1_MCKDIV_Pos)               /*!< 0x00800000 */
+
+/*******************  Bit definition for SAI_xCR2 register  *******************/
+#define SAI_xCR2_FTH_Pos           (0U)                                        
+#define SAI_xCR2_FTH_Msk           (0x7UL << SAI_xCR2_FTH_Pos)                  /*!< 0x00000007 */
+#define SAI_xCR2_FTH               SAI_xCR2_FTH_Msk                            /*!<FTH[2:0](Fifo THreshold)  */
+#define SAI_xCR2_FTH_0             (0x1UL << SAI_xCR2_FTH_Pos)                  /*!< 0x00000001 */
+#define SAI_xCR2_FTH_1             (0x2UL << SAI_xCR2_FTH_Pos)                  /*!< 0x00000002 */
+#define SAI_xCR2_FTH_2             (0x4UL << SAI_xCR2_FTH_Pos)                  /*!< 0x00000004 */
+
+#define SAI_xCR2_FFLUSH_Pos        (3U)                                        
+#define SAI_xCR2_FFLUSH_Msk        (0x1UL << SAI_xCR2_FFLUSH_Pos)               /*!< 0x00000008 */
+#define SAI_xCR2_FFLUSH            SAI_xCR2_FFLUSH_Msk                         /*!<Fifo FLUSH                       */
+#define SAI_xCR2_TRIS_Pos          (4U)                                        
+#define SAI_xCR2_TRIS_Msk          (0x1UL << SAI_xCR2_TRIS_Pos)                 /*!< 0x00000010 */
+#define SAI_xCR2_TRIS              SAI_xCR2_TRIS_Msk                           /*!<TRIState Management on data line */
+#define SAI_xCR2_MUTE_Pos          (5U)                                        
+#define SAI_xCR2_MUTE_Msk          (0x1UL << SAI_xCR2_MUTE_Pos)                 /*!< 0x00000020 */
+#define SAI_xCR2_MUTE              SAI_xCR2_MUTE_Msk                           /*!<Mute mode                        */
+#define SAI_xCR2_MUTEVAL_Pos       (6U)                                        
+#define SAI_xCR2_MUTEVAL_Msk       (0x1UL << SAI_xCR2_MUTEVAL_Pos)              /*!< 0x00000040 */
+#define SAI_xCR2_MUTEVAL           SAI_xCR2_MUTEVAL_Msk                        /*!<Muate value                      */
+
+#define SAI_xCR2_MUTECNT_Pos       (7U)                                        
+#define SAI_xCR2_MUTECNT_Msk       (0x3FUL << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00001F80 */
+#define SAI_xCR2_MUTECNT           SAI_xCR2_MUTECNT_Msk                        /*!<MUTECNT[5:0] (MUTE counter) */
+#define SAI_xCR2_MUTECNT_0         (0x01UL << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000080 */
+#define SAI_xCR2_MUTECNT_1         (0x02UL << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000100 */
+#define SAI_xCR2_MUTECNT_2         (0x04UL << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000200 */
+#define SAI_xCR2_MUTECNT_3         (0x08UL << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000400 */
+#define SAI_xCR2_MUTECNT_4         (0x10UL << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000800 */
+#define SAI_xCR2_MUTECNT_5         (0x20UL << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00001000 */
+
+#define SAI_xCR2_CPL_Pos           (13U)                                       
+#define SAI_xCR2_CPL_Msk           (0x1UL << SAI_xCR2_CPL_Pos)                  /*!< 0x00002000 */
+#define SAI_xCR2_CPL               SAI_xCR2_CPL_Msk                            /*!< Complement Bit             */
+
+#define SAI_xCR2_COMP_Pos          (14U)                                       
+#define SAI_xCR2_COMP_Msk          (0x3UL << SAI_xCR2_COMP_Pos)                 /*!< 0x0000C000 */
+#define SAI_xCR2_COMP              SAI_xCR2_COMP_Msk                           /*!<COMP[1:0] (Companding mode) */
+#define SAI_xCR2_COMP_0            (0x1UL << SAI_xCR2_COMP_Pos)                 /*!< 0x00004000 */
+#define SAI_xCR2_COMP_1            (0x2UL << SAI_xCR2_COMP_Pos)                 /*!< 0x00008000 */
+
+/******************  Bit definition for SAI_xFRCR register  *******************/
+#define SAI_xFRCR_FRL_Pos          (0U)                                        
+#define SAI_xFRCR_FRL_Msk          (0xFFUL << SAI_xFRCR_FRL_Pos)                /*!< 0x000000FF */
+#define SAI_xFRCR_FRL              SAI_xFRCR_FRL_Msk                           /*!<FRL[7:0](Frame length)  */
+#define SAI_xFRCR_FRL_0            (0x01UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000001 */
+#define SAI_xFRCR_FRL_1            (0x02UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000002 */
+#define SAI_xFRCR_FRL_2            (0x04UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000004 */
+#define SAI_xFRCR_FRL_3            (0x08UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000008 */
+#define SAI_xFRCR_FRL_4            (0x10UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000010 */
+#define SAI_xFRCR_FRL_5            (0x20UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000020 */
+#define SAI_xFRCR_FRL_6            (0x40UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000040 */
+#define SAI_xFRCR_FRL_7            (0x80UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000080 */
+
+#define SAI_xFRCR_FSALL_Pos        (8U)                                        
+#define SAI_xFRCR_FSALL_Msk        (0x7FUL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00007F00 */
+#define SAI_xFRCR_FSALL            SAI_xFRCR_FSALL_Msk                         /*!<FRL[6:0] (Frame synchronization active level length)  */
+#define SAI_xFRCR_FSALL_0          (0x01UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00000100 */
+#define SAI_xFRCR_FSALL_1          (0x02UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00000200 */
+#define SAI_xFRCR_FSALL_2          (0x04UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00000400 */
+#define SAI_xFRCR_FSALL_3          (0x08UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00000800 */
+#define SAI_xFRCR_FSALL_4          (0x10UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00001000 */
+#define SAI_xFRCR_FSALL_5          (0x20UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00002000 */
+#define SAI_xFRCR_FSALL_6          (0x40UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00004000 */
+
+#define SAI_xFRCR_FSDEF_Pos        (16U)                                       
+#define SAI_xFRCR_FSDEF_Msk        (0x1UL << SAI_xFRCR_FSDEF_Pos)               /*!< 0x00010000 */
+#define SAI_xFRCR_FSDEF            SAI_xFRCR_FSDEF_Msk                         /*!< Frame Synchronization Definition */
+#define SAI_xFRCR_FSPOL_Pos        (17U)                                       
+#define SAI_xFRCR_FSPOL_Msk        (0x1UL << SAI_xFRCR_FSPOL_Pos)               /*!< 0x00020000 */
+#define SAI_xFRCR_FSPOL            SAI_xFRCR_FSPOL_Msk                         /*!<Frame Synchronization POLarity    */
+#define SAI_xFRCR_FSOFF_Pos        (18U)                                       
+#define SAI_xFRCR_FSOFF_Msk        (0x1UL << SAI_xFRCR_FSOFF_Pos)               /*!< 0x00040000 */
+#define SAI_xFRCR_FSOFF            SAI_xFRCR_FSOFF_Msk                         /*!<Frame Synchronization OFFset      */
+/* Legacy defines */
+#define  SAI_xFRCR_FSPO                   SAI_xFRCR_FSPOL
+
+/******************  Bit definition for SAI_xSLOTR register  *******************/
+#define SAI_xSLOTR_FBOFF_Pos       (0U)                                        
+#define SAI_xSLOTR_FBOFF_Msk       (0x1FUL << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x0000001F */
+#define SAI_xSLOTR_FBOFF           SAI_xSLOTR_FBOFF_Msk                        /*!<FRL[4:0](First Bit Offset)  */
+#define SAI_xSLOTR_FBOFF_0         (0x01UL << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000001 */
+#define SAI_xSLOTR_FBOFF_1         (0x02UL << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000002 */
+#define SAI_xSLOTR_FBOFF_2         (0x04UL << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000004 */
+#define SAI_xSLOTR_FBOFF_3         (0x08UL << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000008 */
+#define SAI_xSLOTR_FBOFF_4         (0x10UL << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000010 */
+
+#define SAI_xSLOTR_SLOTSZ_Pos      (6U)                                        
+#define SAI_xSLOTR_SLOTSZ_Msk      (0x3UL << SAI_xSLOTR_SLOTSZ_Pos)             /*!< 0x000000C0 */
+#define SAI_xSLOTR_SLOTSZ          SAI_xSLOTR_SLOTSZ_Msk                       /*!<SLOTSZ[1:0] (Slot size)  */
+#define SAI_xSLOTR_SLOTSZ_0        (0x1UL << SAI_xSLOTR_SLOTSZ_Pos)             /*!< 0x00000040 */
+#define SAI_xSLOTR_SLOTSZ_1        (0x2UL << SAI_xSLOTR_SLOTSZ_Pos)             /*!< 0x00000080 */
+
+#define SAI_xSLOTR_NBSLOT_Pos      (8U)                                        
+#define SAI_xSLOTR_NBSLOT_Msk      (0xFUL << SAI_xSLOTR_NBSLOT_Pos)             /*!< 0x00000F00 */
+#define SAI_xSLOTR_NBSLOT          SAI_xSLOTR_NBSLOT_Msk                       /*!<NBSLOT[3:0] (Number of Slot in audio Frame)  */
+#define SAI_xSLOTR_NBSLOT_0        (0x1UL << SAI_xSLOTR_NBSLOT_Pos)             /*!< 0x00000100 */
+#define SAI_xSLOTR_NBSLOT_1        (0x2UL << SAI_xSLOTR_NBSLOT_Pos)             /*!< 0x00000200 */
+#define SAI_xSLOTR_NBSLOT_2        (0x4UL << SAI_xSLOTR_NBSLOT_Pos)             /*!< 0x00000400 */
+#define SAI_xSLOTR_NBSLOT_3        (0x8UL << SAI_xSLOTR_NBSLOT_Pos)             /*!< 0x00000800 */
+
+#define SAI_xSLOTR_SLOTEN_Pos      (16U)                                       
+#define SAI_xSLOTR_SLOTEN_Msk      (0xFFFFUL << SAI_xSLOTR_SLOTEN_Pos)          /*!< 0xFFFF0000 */
+#define SAI_xSLOTR_SLOTEN          SAI_xSLOTR_SLOTEN_Msk                       /*!<SLOTEN[15:0] (Slot Enable)  */
+
+/*******************  Bit definition for SAI_xIMR register  *******************/
+#define SAI_xIMR_OVRUDRIE_Pos      (0U)                                        
+#define SAI_xIMR_OVRUDRIE_Msk      (0x1UL << SAI_xIMR_OVRUDRIE_Pos)             /*!< 0x00000001 */
+#define SAI_xIMR_OVRUDRIE          SAI_xIMR_OVRUDRIE_Msk                       /*!<Overrun underrun interrupt enable                              */
+#define SAI_xIMR_MUTEDETIE_Pos     (1U)                                        
+#define SAI_xIMR_MUTEDETIE_Msk     (0x1UL << SAI_xIMR_MUTEDETIE_Pos)            /*!< 0x00000002 */
+#define SAI_xIMR_MUTEDETIE         SAI_xIMR_MUTEDETIE_Msk                      /*!<Mute detection interrupt enable                                */
+#define SAI_xIMR_WCKCFGIE_Pos      (2U)                                        
+#define SAI_xIMR_WCKCFGIE_Msk      (0x1UL << SAI_xIMR_WCKCFGIE_Pos)             /*!< 0x00000004 */
+#define SAI_xIMR_WCKCFGIE          SAI_xIMR_WCKCFGIE_Msk                       /*!<Wrong Clock Configuration interrupt enable                     */
+#define SAI_xIMR_FREQIE_Pos        (3U)                                        
+#define SAI_xIMR_FREQIE_Msk        (0x1UL << SAI_xIMR_FREQIE_Pos)               /*!< 0x00000008 */
+#define SAI_xIMR_FREQIE            SAI_xIMR_FREQIE_Msk                         /*!<FIFO request interrupt enable                                  */
+#define SAI_xIMR_CNRDYIE_Pos       (4U)                                        
+#define SAI_xIMR_CNRDYIE_Msk       (0x1UL << SAI_xIMR_CNRDYIE_Pos)              /*!< 0x00000010 */
+#define SAI_xIMR_CNRDYIE           SAI_xIMR_CNRDYIE_Msk                        /*!<Codec not ready interrupt enable                               */
+#define SAI_xIMR_AFSDETIE_Pos      (5U)                                        
+#define SAI_xIMR_AFSDETIE_Msk      (0x1UL << SAI_xIMR_AFSDETIE_Pos)             /*!< 0x00000020 */
+#define SAI_xIMR_AFSDETIE          SAI_xIMR_AFSDETIE_Msk                       /*!<Anticipated frame synchronization detection interrupt enable   */
+#define SAI_xIMR_LFSDETIE_Pos      (6U)                                        
+#define SAI_xIMR_LFSDETIE_Msk      (0x1UL << SAI_xIMR_LFSDETIE_Pos)             /*!< 0x00000040 */
+#define SAI_xIMR_LFSDETIE          SAI_xIMR_LFSDETIE_Msk                       /*!<Late frame synchronization detection interrupt enable          */
+
+/********************  Bit definition for SAI_xSR register  *******************/
+#define SAI_xSR_OVRUDR_Pos         (0U)                                        
+#define SAI_xSR_OVRUDR_Msk         (0x1UL << SAI_xSR_OVRUDR_Pos)                /*!< 0x00000001 */
+#define SAI_xSR_OVRUDR             SAI_xSR_OVRUDR_Msk                          /*!<Overrun underrun                               */
+#define SAI_xSR_MUTEDET_Pos        (1U)                                        
+#define SAI_xSR_MUTEDET_Msk        (0x1UL << SAI_xSR_MUTEDET_Pos)               /*!< 0x00000002 */
+#define SAI_xSR_MUTEDET            SAI_xSR_MUTEDET_Msk                         /*!<Mute detection                                 */
+#define SAI_xSR_WCKCFG_Pos         (2U)                                        
+#define SAI_xSR_WCKCFG_Msk         (0x1UL << SAI_xSR_WCKCFG_Pos)                /*!< 0x00000004 */
+#define SAI_xSR_WCKCFG             SAI_xSR_WCKCFG_Msk                          /*!<Wrong Clock Configuration                      */
+#define SAI_xSR_FREQ_Pos           (3U)                                        
+#define SAI_xSR_FREQ_Msk           (0x1UL << SAI_xSR_FREQ_Pos)                  /*!< 0x00000008 */
+#define SAI_xSR_FREQ               SAI_xSR_FREQ_Msk                            /*!<FIFO request                                   */
+#define SAI_xSR_CNRDY_Pos          (4U)                                        
+#define SAI_xSR_CNRDY_Msk          (0x1UL << SAI_xSR_CNRDY_Pos)                 /*!< 0x00000010 */
+#define SAI_xSR_CNRDY              SAI_xSR_CNRDY_Msk                           /*!<Codec not ready                                */
+#define SAI_xSR_AFSDET_Pos         (5U)                                        
+#define SAI_xSR_AFSDET_Msk         (0x1UL << SAI_xSR_AFSDET_Pos)                /*!< 0x00000020 */
+#define SAI_xSR_AFSDET             SAI_xSR_AFSDET_Msk                          /*!<Anticipated frame synchronization detection    */
+#define SAI_xSR_LFSDET_Pos         (6U)                                        
+#define SAI_xSR_LFSDET_Msk         (0x1UL << SAI_xSR_LFSDET_Pos)                /*!< 0x00000040 */
+#define SAI_xSR_LFSDET             SAI_xSR_LFSDET_Msk                          /*!<Late frame synchronization detection           */
+
+#define SAI_xSR_FLVL_Pos           (16U)                                       
+#define SAI_xSR_FLVL_Msk           (0x7UL << SAI_xSR_FLVL_Pos)                  /*!< 0x00070000 */
+#define SAI_xSR_FLVL               SAI_xSR_FLVL_Msk                            /*!<FLVL[2:0] (FIFO Level Threshold)               */
+#define SAI_xSR_FLVL_0             (0x1UL << SAI_xSR_FLVL_Pos)                  /*!< 0x00010000 */
+#define SAI_xSR_FLVL_1             (0x2UL << SAI_xSR_FLVL_Pos)                  /*!< 0x00020000 */
+#define SAI_xSR_FLVL_2             (0x4UL << SAI_xSR_FLVL_Pos)                  /*!< 0x00040000 */
+
+/******************  Bit definition for SAI_xCLRFR register  ******************/
+#define SAI_xCLRFR_COVRUDR_Pos     (0U)                                        
+#define SAI_xCLRFR_COVRUDR_Msk     (0x1UL << SAI_xCLRFR_COVRUDR_Pos)            /*!< 0x00000001 */
+#define SAI_xCLRFR_COVRUDR         SAI_xCLRFR_COVRUDR_Msk                      /*!<Clear Overrun underrun                               */
+#define SAI_xCLRFR_CMUTEDET_Pos    (1U)                                        
+#define SAI_xCLRFR_CMUTEDET_Msk    (0x1UL << SAI_xCLRFR_CMUTEDET_Pos)           /*!< 0x00000002 */
+#define SAI_xCLRFR_CMUTEDET        SAI_xCLRFR_CMUTEDET_Msk                     /*!<Clear Mute detection                                 */
+#define SAI_xCLRFR_CWCKCFG_Pos     (2U)                                        
+#define SAI_xCLRFR_CWCKCFG_Msk     (0x1UL << SAI_xCLRFR_CWCKCFG_Pos)            /*!< 0x00000004 */
+#define SAI_xCLRFR_CWCKCFG         SAI_xCLRFR_CWCKCFG_Msk                      /*!<Clear Wrong Clock Configuration                      */
+#define SAI_xCLRFR_CFREQ_Pos       (3U)                                        
+#define SAI_xCLRFR_CFREQ_Msk       (0x1UL << SAI_xCLRFR_CFREQ_Pos)              /*!< 0x00000008 */
+#define SAI_xCLRFR_CFREQ           SAI_xCLRFR_CFREQ_Msk                        /*!<Clear FIFO request                                   */
+#define SAI_xCLRFR_CCNRDY_Pos      (4U)                                        
+#define SAI_xCLRFR_CCNRDY_Msk      (0x1UL << SAI_xCLRFR_CCNRDY_Pos)             /*!< 0x00000010 */
+#define SAI_xCLRFR_CCNRDY          SAI_xCLRFR_CCNRDY_Msk                       /*!<Clear Codec not ready                                */
+#define SAI_xCLRFR_CAFSDET_Pos     (5U)                                        
+#define SAI_xCLRFR_CAFSDET_Msk     (0x1UL << SAI_xCLRFR_CAFSDET_Pos)            /*!< 0x00000020 */
+#define SAI_xCLRFR_CAFSDET         SAI_xCLRFR_CAFSDET_Msk                      /*!<Clear Anticipated frame synchronization detection    */
+#define SAI_xCLRFR_CLFSDET_Pos     (6U)                                        
+#define SAI_xCLRFR_CLFSDET_Msk     (0x1UL << SAI_xCLRFR_CLFSDET_Pos)            /*!< 0x00000040 */
+#define SAI_xCLRFR_CLFSDET         SAI_xCLRFR_CLFSDET_Msk                      /*!<Clear Late frame synchronization detection           */
+
+/******************  Bit definition for SAI_xDR register  ******************/
+#define SAI_xDR_DATA_Pos           (0U)                                        
+#define SAI_xDR_DATA_Msk           (0xFFFFFFFFUL << SAI_xDR_DATA_Pos)           /*!< 0xFFFFFFFF */
+#define SAI_xDR_DATA               SAI_xDR_DATA_Msk                            
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                          SD host Interface                                 */
+/*                                                                            */
+/******************************************************************************/
+/******************  Bit definition for SDIO_POWER register  ******************/
+#define SDIO_POWER_PWRCTRL_Pos         (0U)                                    
+#define SDIO_POWER_PWRCTRL_Msk         (0x3UL << SDIO_POWER_PWRCTRL_Pos)        /*!< 0x00000003 */
+#define SDIO_POWER_PWRCTRL             SDIO_POWER_PWRCTRL_Msk                  /*!<PWRCTRL[1:0] bits (Power supply control bits) */
+#define SDIO_POWER_PWRCTRL_0           (0x1UL << SDIO_POWER_PWRCTRL_Pos)        /*!< 0x01 */
+#define SDIO_POWER_PWRCTRL_1           (0x2UL << SDIO_POWER_PWRCTRL_Pos)        /*!< 0x02 */
+
+/******************  Bit definition for SDIO_CLKCR register  ******************/
+#define SDIO_CLKCR_CLKDIV_Pos          (0U)                                    
+#define SDIO_CLKCR_CLKDIV_Msk          (0xFFUL << SDIO_CLKCR_CLKDIV_Pos)        /*!< 0x000000FF */
+#define SDIO_CLKCR_CLKDIV              SDIO_CLKCR_CLKDIV_Msk                   /*!<Clock divide factor             */
+#define SDIO_CLKCR_CLKEN_Pos           (8U)                                    
+#define SDIO_CLKCR_CLKEN_Msk           (0x1UL << SDIO_CLKCR_CLKEN_Pos)          /*!< 0x00000100 */
+#define SDIO_CLKCR_CLKEN               SDIO_CLKCR_CLKEN_Msk                    /*!<Clock enable bit                */
+#define SDIO_CLKCR_PWRSAV_Pos          (9U)                                    
+#define SDIO_CLKCR_PWRSAV_Msk          (0x1UL << SDIO_CLKCR_PWRSAV_Pos)         /*!< 0x00000200 */
+#define SDIO_CLKCR_PWRSAV              SDIO_CLKCR_PWRSAV_Msk                   /*!<Power saving configuration bit  */
+#define SDIO_CLKCR_BYPASS_Pos          (10U)                                   
+#define SDIO_CLKCR_BYPASS_Msk          (0x1UL << SDIO_CLKCR_BYPASS_Pos)         /*!< 0x00000400 */
+#define SDIO_CLKCR_BYPASS              SDIO_CLKCR_BYPASS_Msk                   /*!<Clock divider bypass enable bit */
+
+#define SDIO_CLKCR_WIDBUS_Pos          (11U)                                   
+#define SDIO_CLKCR_WIDBUS_Msk          (0x3UL << SDIO_CLKCR_WIDBUS_Pos)         /*!< 0x00001800 */
+#define SDIO_CLKCR_WIDBUS              SDIO_CLKCR_WIDBUS_Msk                   /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
+#define SDIO_CLKCR_WIDBUS_0            (0x1UL << SDIO_CLKCR_WIDBUS_Pos)         /*!< 0x0800 */
+#define SDIO_CLKCR_WIDBUS_1            (0x2UL << SDIO_CLKCR_WIDBUS_Pos)         /*!< 0x1000 */
+
+#define SDIO_CLKCR_NEGEDGE_Pos         (13U)                                   
+#define SDIO_CLKCR_NEGEDGE_Msk         (0x1UL << SDIO_CLKCR_NEGEDGE_Pos)        /*!< 0x00002000 */
+#define SDIO_CLKCR_NEGEDGE             SDIO_CLKCR_NEGEDGE_Msk                  /*!<SDIO_CK dephasing selection bit */
+#define SDIO_CLKCR_HWFC_EN_Pos         (14U)                                   
+#define SDIO_CLKCR_HWFC_EN_Msk         (0x1UL << SDIO_CLKCR_HWFC_EN_Pos)        /*!< 0x00004000 */
+#define SDIO_CLKCR_HWFC_EN             SDIO_CLKCR_HWFC_EN_Msk                  /*!<HW Flow Control enable          */
+
+/*******************  Bit definition for SDIO_ARG register  *******************/
+#define SDIO_ARG_CMDARG_Pos            (0U)                                    
+#define SDIO_ARG_CMDARG_Msk            (0xFFFFFFFFUL << SDIO_ARG_CMDARG_Pos)    /*!< 0xFFFFFFFF */
+#define SDIO_ARG_CMDARG                SDIO_ARG_CMDARG_Msk                     /*!<Command argument */
+
+/*******************  Bit definition for SDIO_CMD register  *******************/
+#define SDIO_CMD_CMDINDEX_Pos          (0U)                                    
+#define SDIO_CMD_CMDINDEX_Msk          (0x3FUL << SDIO_CMD_CMDINDEX_Pos)        /*!< 0x0000003F */
+#define SDIO_CMD_CMDINDEX              SDIO_CMD_CMDINDEX_Msk                   /*!<Command Index                               */
+
+#define SDIO_CMD_WAITRESP_Pos          (6U)                                    
+#define SDIO_CMD_WAITRESP_Msk          (0x3UL << SDIO_CMD_WAITRESP_Pos)         /*!< 0x000000C0 */
+#define SDIO_CMD_WAITRESP              SDIO_CMD_WAITRESP_Msk                   /*!<WAITRESP[1:0] bits (Wait for response bits) */
+#define SDIO_CMD_WAITRESP_0            (0x1UL << SDIO_CMD_WAITRESP_Pos)         /*!< 0x0040 */
+#define SDIO_CMD_WAITRESP_1            (0x2UL << SDIO_CMD_WAITRESP_Pos)         /*!< 0x0080 */
+
+#define SDIO_CMD_WAITINT_Pos           (8U)                                    
+#define SDIO_CMD_WAITINT_Msk           (0x1UL << SDIO_CMD_WAITINT_Pos)          /*!< 0x00000100 */
+#define SDIO_CMD_WAITINT               SDIO_CMD_WAITINT_Msk                    /*!<CPSM Waits for Interrupt Request                               */
+#define SDIO_CMD_WAITPEND_Pos          (9U)                                    
+#define SDIO_CMD_WAITPEND_Msk          (0x1UL << SDIO_CMD_WAITPEND_Pos)         /*!< 0x00000200 */
+#define SDIO_CMD_WAITPEND              SDIO_CMD_WAITPEND_Msk                   /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
+#define SDIO_CMD_CPSMEN_Pos            (10U)                                   
+#define SDIO_CMD_CPSMEN_Msk            (0x1UL << SDIO_CMD_CPSMEN_Pos)           /*!< 0x00000400 */
+#define SDIO_CMD_CPSMEN                SDIO_CMD_CPSMEN_Msk                     /*!<Command path state machine (CPSM) Enable bit                   */
+#define SDIO_CMD_SDIOSUSPEND_Pos       (11U)                                   
+#define SDIO_CMD_SDIOSUSPEND_Msk       (0x1UL << SDIO_CMD_SDIOSUSPEND_Pos)      /*!< 0x00000800 */
+#define SDIO_CMD_SDIOSUSPEND           SDIO_CMD_SDIOSUSPEND_Msk                /*!<SD I/O suspend command                                         */
+
+/*****************  Bit definition for SDIO_RESPCMD register  *****************/
+#define SDIO_RESPCMD_RESPCMD_Pos       (0U)                                    
+#define SDIO_RESPCMD_RESPCMD_Msk       (0x3FUL << SDIO_RESPCMD_RESPCMD_Pos)     /*!< 0x0000003F */
+#define SDIO_RESPCMD_RESPCMD           SDIO_RESPCMD_RESPCMD_Msk                /*!<Response command index */
+
+/******************  Bit definition for SDIO_RESP0 register  ******************/
+#define SDIO_RESP0_CARDSTATUS0_Pos     (0U)                                    
+#define SDIO_RESP0_CARDSTATUS0_Msk     (0xFFFFFFFFUL << SDIO_RESP0_CARDSTATUS0_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_RESP0_CARDSTATUS0         SDIO_RESP0_CARDSTATUS0_Msk              /*!<Card Status */
+
+/******************  Bit definition for SDIO_RESP1 register  ******************/
+#define SDIO_RESP1_CARDSTATUS1_Pos     (0U)                                    
+#define SDIO_RESP1_CARDSTATUS1_Msk     (0xFFFFFFFFUL << SDIO_RESP1_CARDSTATUS1_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_RESP1_CARDSTATUS1         SDIO_RESP1_CARDSTATUS1_Msk              /*!<Card Status */
+
+/******************  Bit definition for SDIO_RESP2 register  ******************/
+#define SDIO_RESP2_CARDSTATUS2_Pos     (0U)                                    
+#define SDIO_RESP2_CARDSTATUS2_Msk     (0xFFFFFFFFUL << SDIO_RESP2_CARDSTATUS2_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_RESP2_CARDSTATUS2         SDIO_RESP2_CARDSTATUS2_Msk              /*!<Card Status */
+
+/******************  Bit definition for SDIO_RESP3 register  ******************/
+#define SDIO_RESP3_CARDSTATUS3_Pos     (0U)                                    
+#define SDIO_RESP3_CARDSTATUS3_Msk     (0xFFFFFFFFUL << SDIO_RESP3_CARDSTATUS3_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_RESP3_CARDSTATUS3         SDIO_RESP3_CARDSTATUS3_Msk              /*!<Card Status */
+
+/******************  Bit definition for SDIO_RESP4 register  ******************/
+#define SDIO_RESP4_CARDSTATUS4_Pos     (0U)                                    
+#define SDIO_RESP4_CARDSTATUS4_Msk     (0xFFFFFFFFUL << SDIO_RESP4_CARDSTATUS4_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_RESP4_CARDSTATUS4         SDIO_RESP4_CARDSTATUS4_Msk              /*!<Card Status */
+
+/******************  Bit definition for SDIO_DTIMER register  *****************/
+#define SDIO_DTIMER_DATATIME_Pos       (0U)                                    
+#define SDIO_DTIMER_DATATIME_Msk       (0xFFFFFFFFUL << SDIO_DTIMER_DATATIME_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_DTIMER_DATATIME           SDIO_DTIMER_DATATIME_Msk                /*!<Data timeout period. */
+
+/******************  Bit definition for SDIO_DLEN register  *******************/
+#define SDIO_DLEN_DATALENGTH_Pos       (0U)                                    
+#define SDIO_DLEN_DATALENGTH_Msk       (0x1FFFFFFUL << SDIO_DLEN_DATALENGTH_Pos) /*!< 0x01FFFFFF */
+#define SDIO_DLEN_DATALENGTH           SDIO_DLEN_DATALENGTH_Msk                /*!<Data length value    */
+
+/******************  Bit definition for SDIO_DCTRL register  ******************/
+#define SDIO_DCTRL_DTEN_Pos            (0U)                                    
+#define SDIO_DCTRL_DTEN_Msk            (0x1UL << SDIO_DCTRL_DTEN_Pos)           /*!< 0x00000001 */
+#define SDIO_DCTRL_DTEN                SDIO_DCTRL_DTEN_Msk                     /*!<Data transfer enabled bit         */
+#define SDIO_DCTRL_DTDIR_Pos           (1U)                                    
+#define SDIO_DCTRL_DTDIR_Msk           (0x1UL << SDIO_DCTRL_DTDIR_Pos)          /*!< 0x00000002 */
+#define SDIO_DCTRL_DTDIR               SDIO_DCTRL_DTDIR_Msk                    /*!<Data transfer direction selection */
+#define SDIO_DCTRL_DTMODE_Pos          (2U)                                    
+#define SDIO_DCTRL_DTMODE_Msk          (0x1UL << SDIO_DCTRL_DTMODE_Pos)         /*!< 0x00000004 */
+#define SDIO_DCTRL_DTMODE              SDIO_DCTRL_DTMODE_Msk                   /*!<Data transfer mode selection      */
+#define SDIO_DCTRL_DMAEN_Pos           (3U)                                    
+#define SDIO_DCTRL_DMAEN_Msk           (0x1UL << SDIO_DCTRL_DMAEN_Pos)          /*!< 0x00000008 */
+#define SDIO_DCTRL_DMAEN               SDIO_DCTRL_DMAEN_Msk                    /*!<DMA enabled bit                   */
+
+#define SDIO_DCTRL_DBLOCKSIZE_Pos      (4U)                                    
+#define SDIO_DCTRL_DBLOCKSIZE_Msk      (0xFUL << SDIO_DCTRL_DBLOCKSIZE_Pos)     /*!< 0x000000F0 */
+#define SDIO_DCTRL_DBLOCKSIZE          SDIO_DCTRL_DBLOCKSIZE_Msk               /*!<DBLOCKSIZE[3:0] bits (Data block size) */
+#define SDIO_DCTRL_DBLOCKSIZE_0        (0x1UL << SDIO_DCTRL_DBLOCKSIZE_Pos)     /*!< 0x0010 */
+#define SDIO_DCTRL_DBLOCKSIZE_1        (0x2UL << SDIO_DCTRL_DBLOCKSIZE_Pos)     /*!< 0x0020 */
+#define SDIO_DCTRL_DBLOCKSIZE_2        (0x4UL << SDIO_DCTRL_DBLOCKSIZE_Pos)     /*!< 0x0040 */
+#define SDIO_DCTRL_DBLOCKSIZE_3        (0x8UL << SDIO_DCTRL_DBLOCKSIZE_Pos)     /*!< 0x0080 */
+
+#define SDIO_DCTRL_RWSTART_Pos         (8U)                                    
+#define SDIO_DCTRL_RWSTART_Msk         (0x1UL << SDIO_DCTRL_RWSTART_Pos)        /*!< 0x00000100 */
+#define SDIO_DCTRL_RWSTART             SDIO_DCTRL_RWSTART_Msk                  /*!<Read wait start         */
+#define SDIO_DCTRL_RWSTOP_Pos          (9U)                                    
+#define SDIO_DCTRL_RWSTOP_Msk          (0x1UL << SDIO_DCTRL_RWSTOP_Pos)         /*!< 0x00000200 */
+#define SDIO_DCTRL_RWSTOP              SDIO_DCTRL_RWSTOP_Msk                   /*!<Read wait stop          */
+#define SDIO_DCTRL_RWMOD_Pos           (10U)                                   
+#define SDIO_DCTRL_RWMOD_Msk           (0x1UL << SDIO_DCTRL_RWMOD_Pos)          /*!< 0x00000400 */
+#define SDIO_DCTRL_RWMOD               SDIO_DCTRL_RWMOD_Msk                    /*!<Read wait mode          */
+#define SDIO_DCTRL_SDIOEN_Pos          (11U)                                   
+#define SDIO_DCTRL_SDIOEN_Msk          (0x1UL << SDIO_DCTRL_SDIOEN_Pos)         /*!< 0x00000800 */
+#define SDIO_DCTRL_SDIOEN              SDIO_DCTRL_SDIOEN_Msk                   /*!<SD I/O enable functions */
+
+/******************  Bit definition for SDIO_DCOUNT register  *****************/
+#define SDIO_DCOUNT_DATACOUNT_Pos      (0U)                                    
+#define SDIO_DCOUNT_DATACOUNT_Msk      (0x1FFFFFFUL << SDIO_DCOUNT_DATACOUNT_Pos) /*!< 0x01FFFFFF */
+#define SDIO_DCOUNT_DATACOUNT          SDIO_DCOUNT_DATACOUNT_Msk               /*!<Data count value */
+
+/******************  Bit definition for SDIO_STA register  ********************/
+#define SDIO_STA_CCRCFAIL_Pos          (0U)                                    
+#define SDIO_STA_CCRCFAIL_Msk          (0x1UL << SDIO_STA_CCRCFAIL_Pos)         /*!< 0x00000001 */
+#define SDIO_STA_CCRCFAIL              SDIO_STA_CCRCFAIL_Msk                   /*!<Command response received (CRC check failed)  */
+#define SDIO_STA_DCRCFAIL_Pos          (1U)                                    
+#define SDIO_STA_DCRCFAIL_Msk          (0x1UL << SDIO_STA_DCRCFAIL_Pos)         /*!< 0x00000002 */
+#define SDIO_STA_DCRCFAIL              SDIO_STA_DCRCFAIL_Msk                   /*!<Data block sent/received (CRC check failed)   */
+#define SDIO_STA_CTIMEOUT_Pos          (2U)                                    
+#define SDIO_STA_CTIMEOUT_Msk          (0x1UL << SDIO_STA_CTIMEOUT_Pos)         /*!< 0x00000004 */
+#define SDIO_STA_CTIMEOUT              SDIO_STA_CTIMEOUT_Msk                   /*!<Command response timeout                      */
+#define SDIO_STA_DTIMEOUT_Pos          (3U)                                    
+#define SDIO_STA_DTIMEOUT_Msk          (0x1UL << SDIO_STA_DTIMEOUT_Pos)         /*!< 0x00000008 */
+#define SDIO_STA_DTIMEOUT              SDIO_STA_DTIMEOUT_Msk                   /*!<Data timeout                                  */
+#define SDIO_STA_TXUNDERR_Pos          (4U)                                    
+#define SDIO_STA_TXUNDERR_Msk          (0x1UL << SDIO_STA_TXUNDERR_Pos)         /*!< 0x00000010 */
+#define SDIO_STA_TXUNDERR              SDIO_STA_TXUNDERR_Msk                   /*!<Transmit FIFO underrun error                  */
+#define SDIO_STA_RXOVERR_Pos           (5U)                                    
+#define SDIO_STA_RXOVERR_Msk           (0x1UL << SDIO_STA_RXOVERR_Pos)          /*!< 0x00000020 */
+#define SDIO_STA_RXOVERR               SDIO_STA_RXOVERR_Msk                    /*!<Received FIFO overrun error                   */
+#define SDIO_STA_CMDREND_Pos           (6U)                                    
+#define SDIO_STA_CMDREND_Msk           (0x1UL << SDIO_STA_CMDREND_Pos)          /*!< 0x00000040 */
+#define SDIO_STA_CMDREND               SDIO_STA_CMDREND_Msk                    /*!<Command response received (CRC check passed)  */
+#define SDIO_STA_CMDSENT_Pos           (7U)                                    
+#define SDIO_STA_CMDSENT_Msk           (0x1UL << SDIO_STA_CMDSENT_Pos)          /*!< 0x00000080 */
+#define SDIO_STA_CMDSENT               SDIO_STA_CMDSENT_Msk                    /*!<Command sent (no response required)           */
+#define SDIO_STA_DATAEND_Pos           (8U)                                    
+#define SDIO_STA_DATAEND_Msk           (0x1UL << SDIO_STA_DATAEND_Pos)          /*!< 0x00000100 */
+#define SDIO_STA_DATAEND               SDIO_STA_DATAEND_Msk                    /*!<Data end (data counter, SDIDCOUNT, is zero)   */
+#define SDIO_STA_DBCKEND_Pos           (10U)                                   
+#define SDIO_STA_DBCKEND_Msk           (0x1UL << SDIO_STA_DBCKEND_Pos)          /*!< 0x00000400 */
+#define SDIO_STA_DBCKEND               SDIO_STA_DBCKEND_Msk                    /*!<Data block sent/received (CRC check passed)   */
+#define SDIO_STA_CMDACT_Pos            (11U)                                   
+#define SDIO_STA_CMDACT_Msk            (0x1UL << SDIO_STA_CMDACT_Pos)           /*!< 0x00000800 */
+#define SDIO_STA_CMDACT                SDIO_STA_CMDACT_Msk                     /*!<Command transfer in progress                  */
+#define SDIO_STA_TXACT_Pos             (12U)                                   
+#define SDIO_STA_TXACT_Msk             (0x1UL << SDIO_STA_TXACT_Pos)            /*!< 0x00001000 */
+#define SDIO_STA_TXACT                 SDIO_STA_TXACT_Msk                      /*!<Data transmit in progress                     */
+#define SDIO_STA_RXACT_Pos             (13U)                                   
+#define SDIO_STA_RXACT_Msk             (0x1UL << SDIO_STA_RXACT_Pos)            /*!< 0x00002000 */
+#define SDIO_STA_RXACT                 SDIO_STA_RXACT_Msk                      /*!<Data receive in progress                      */
+#define SDIO_STA_TXFIFOHE_Pos          (14U)                                   
+#define SDIO_STA_TXFIFOHE_Msk          (0x1UL << SDIO_STA_TXFIFOHE_Pos)         /*!< 0x00004000 */
+#define SDIO_STA_TXFIFOHE              SDIO_STA_TXFIFOHE_Msk                   /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
+#define SDIO_STA_RXFIFOHF_Pos          (15U)                                   
+#define SDIO_STA_RXFIFOHF_Msk          (0x1UL << SDIO_STA_RXFIFOHF_Pos)         /*!< 0x00008000 */
+#define SDIO_STA_RXFIFOHF              SDIO_STA_RXFIFOHF_Msk                   /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
+#define SDIO_STA_TXFIFOF_Pos           (16U)                                   
+#define SDIO_STA_TXFIFOF_Msk           (0x1UL << SDIO_STA_TXFIFOF_Pos)          /*!< 0x00010000 */
+#define SDIO_STA_TXFIFOF               SDIO_STA_TXFIFOF_Msk                    /*!<Transmit FIFO full                            */
+#define SDIO_STA_RXFIFOF_Pos           (17U)                                   
+#define SDIO_STA_RXFIFOF_Msk           (0x1UL << SDIO_STA_RXFIFOF_Pos)          /*!< 0x00020000 */
+#define SDIO_STA_RXFIFOF               SDIO_STA_RXFIFOF_Msk                    /*!<Receive FIFO full                             */
+#define SDIO_STA_TXFIFOE_Pos           (18U)                                   
+#define SDIO_STA_TXFIFOE_Msk           (0x1UL << SDIO_STA_TXFIFOE_Pos)          /*!< 0x00040000 */
+#define SDIO_STA_TXFIFOE               SDIO_STA_TXFIFOE_Msk                    /*!<Transmit FIFO empty                           */
+#define SDIO_STA_RXFIFOE_Pos           (19U)                                   
+#define SDIO_STA_RXFIFOE_Msk           (0x1UL << SDIO_STA_RXFIFOE_Pos)          /*!< 0x00080000 */
+#define SDIO_STA_RXFIFOE               SDIO_STA_RXFIFOE_Msk                    /*!<Receive FIFO empty                            */
+#define SDIO_STA_TXDAVL_Pos            (20U)                                   
+#define SDIO_STA_TXDAVL_Msk            (0x1UL << SDIO_STA_TXDAVL_Pos)           /*!< 0x00100000 */
+#define SDIO_STA_TXDAVL                SDIO_STA_TXDAVL_Msk                     /*!<Data available in transmit FIFO               */
+#define SDIO_STA_RXDAVL_Pos            (21U)                                   
+#define SDIO_STA_RXDAVL_Msk            (0x1UL << SDIO_STA_RXDAVL_Pos)           /*!< 0x00200000 */
+#define SDIO_STA_RXDAVL                SDIO_STA_RXDAVL_Msk                     /*!<Data available in receive FIFO                */
+#define SDIO_STA_SDIOIT_Pos            (22U)                                   
+#define SDIO_STA_SDIOIT_Msk            (0x1UL << SDIO_STA_SDIOIT_Pos)           /*!< 0x00400000 */
+#define SDIO_STA_SDIOIT                SDIO_STA_SDIOIT_Msk                     /*!<SDIO interrupt received                       */
+
+/*******************  Bit definition for SDIO_ICR register  *******************/
+#define SDIO_ICR_CCRCFAILC_Pos         (0U)                                    
+#define SDIO_ICR_CCRCFAILC_Msk         (0x1UL << SDIO_ICR_CCRCFAILC_Pos)        /*!< 0x00000001 */
+#define SDIO_ICR_CCRCFAILC             SDIO_ICR_CCRCFAILC_Msk                  /*!<CCRCFAIL flag clear bit */
+#define SDIO_ICR_DCRCFAILC_Pos         (1U)                                    
+#define SDIO_ICR_DCRCFAILC_Msk         (0x1UL << SDIO_ICR_DCRCFAILC_Pos)        /*!< 0x00000002 */
+#define SDIO_ICR_DCRCFAILC             SDIO_ICR_DCRCFAILC_Msk                  /*!<DCRCFAIL flag clear bit */
+#define SDIO_ICR_CTIMEOUTC_Pos         (2U)                                    
+#define SDIO_ICR_CTIMEOUTC_Msk         (0x1UL << SDIO_ICR_CTIMEOUTC_Pos)        /*!< 0x00000004 */
+#define SDIO_ICR_CTIMEOUTC             SDIO_ICR_CTIMEOUTC_Msk                  /*!<CTIMEOUT flag clear bit */
+#define SDIO_ICR_DTIMEOUTC_Pos         (3U)                                    
+#define SDIO_ICR_DTIMEOUTC_Msk         (0x1UL << SDIO_ICR_DTIMEOUTC_Pos)        /*!< 0x00000008 */
+#define SDIO_ICR_DTIMEOUTC             SDIO_ICR_DTIMEOUTC_Msk                  /*!<DTIMEOUT flag clear bit */
+#define SDIO_ICR_TXUNDERRC_Pos         (4U)                                    
+#define SDIO_ICR_TXUNDERRC_Msk         (0x1UL << SDIO_ICR_TXUNDERRC_Pos)        /*!< 0x00000010 */
+#define SDIO_ICR_TXUNDERRC             SDIO_ICR_TXUNDERRC_Msk                  /*!<TXUNDERR flag clear bit */
+#define SDIO_ICR_RXOVERRC_Pos          (5U)                                    
+#define SDIO_ICR_RXOVERRC_Msk          (0x1UL << SDIO_ICR_RXOVERRC_Pos)         /*!< 0x00000020 */
+#define SDIO_ICR_RXOVERRC              SDIO_ICR_RXOVERRC_Msk                   /*!<RXOVERR flag clear bit  */
+#define SDIO_ICR_CMDRENDC_Pos          (6U)                                    
+#define SDIO_ICR_CMDRENDC_Msk          (0x1UL << SDIO_ICR_CMDRENDC_Pos)         /*!< 0x00000040 */
+#define SDIO_ICR_CMDRENDC              SDIO_ICR_CMDRENDC_Msk                   /*!<CMDREND flag clear bit  */
+#define SDIO_ICR_CMDSENTC_Pos          (7U)                                    
+#define SDIO_ICR_CMDSENTC_Msk          (0x1UL << SDIO_ICR_CMDSENTC_Pos)         /*!< 0x00000080 */
+#define SDIO_ICR_CMDSENTC              SDIO_ICR_CMDSENTC_Msk                   /*!<CMDSENT flag clear bit  */
+#define SDIO_ICR_DATAENDC_Pos          (8U)                                    
+#define SDIO_ICR_DATAENDC_Msk          (0x1UL << SDIO_ICR_DATAENDC_Pos)         /*!< 0x00000100 */
+#define SDIO_ICR_DATAENDC              SDIO_ICR_DATAENDC_Msk                   /*!<DATAEND flag clear bit  */
+#define SDIO_ICR_DBCKENDC_Pos          (10U)                                   
+#define SDIO_ICR_DBCKENDC_Msk          (0x1UL << SDIO_ICR_DBCKENDC_Pos)         /*!< 0x00000400 */
+#define SDIO_ICR_DBCKENDC              SDIO_ICR_DBCKENDC_Msk                   /*!<DBCKEND flag clear bit  */
+#define SDIO_ICR_SDIOITC_Pos           (22U)                                   
+#define SDIO_ICR_SDIOITC_Msk           (0x1UL << SDIO_ICR_SDIOITC_Pos)          /*!< 0x00400000 */
+#define SDIO_ICR_SDIOITC               SDIO_ICR_SDIOITC_Msk                    /*!<SDIOIT flag clear bit   */
+
+/******************  Bit definition for SDIO_MASK register  *******************/
+#define SDIO_MASK_CCRCFAILIE_Pos       (0U)                                    
+#define SDIO_MASK_CCRCFAILIE_Msk       (0x1UL << SDIO_MASK_CCRCFAILIE_Pos)      /*!< 0x00000001 */
+#define SDIO_MASK_CCRCFAILIE           SDIO_MASK_CCRCFAILIE_Msk                /*!<Command CRC Fail Interrupt Enable          */
+#define SDIO_MASK_DCRCFAILIE_Pos       (1U)                                    
+#define SDIO_MASK_DCRCFAILIE_Msk       (0x1UL << SDIO_MASK_DCRCFAILIE_Pos)      /*!< 0x00000002 */
+#define SDIO_MASK_DCRCFAILIE           SDIO_MASK_DCRCFAILIE_Msk                /*!<Data CRC Fail Interrupt Enable             */
+#define SDIO_MASK_CTIMEOUTIE_Pos       (2U)                                    
+#define SDIO_MASK_CTIMEOUTIE_Msk       (0x1UL << SDIO_MASK_CTIMEOUTIE_Pos)      /*!< 0x00000004 */
+#define SDIO_MASK_CTIMEOUTIE           SDIO_MASK_CTIMEOUTIE_Msk                /*!<Command TimeOut Interrupt Enable           */
+#define SDIO_MASK_DTIMEOUTIE_Pos       (3U)                                    
+#define SDIO_MASK_DTIMEOUTIE_Msk       (0x1UL << SDIO_MASK_DTIMEOUTIE_Pos)      /*!< 0x00000008 */
+#define SDIO_MASK_DTIMEOUTIE           SDIO_MASK_DTIMEOUTIE_Msk                /*!<Data TimeOut Interrupt Enable              */
+#define SDIO_MASK_TXUNDERRIE_Pos       (4U)                                    
+#define SDIO_MASK_TXUNDERRIE_Msk       (0x1UL << SDIO_MASK_TXUNDERRIE_Pos)      /*!< 0x00000010 */
+#define SDIO_MASK_TXUNDERRIE           SDIO_MASK_TXUNDERRIE_Msk                /*!<Tx FIFO UnderRun Error Interrupt Enable    */
+#define SDIO_MASK_RXOVERRIE_Pos        (5U)                                    
+#define SDIO_MASK_RXOVERRIE_Msk        (0x1UL << SDIO_MASK_RXOVERRIE_Pos)       /*!< 0x00000020 */
+#define SDIO_MASK_RXOVERRIE            SDIO_MASK_RXOVERRIE_Msk                 /*!<Rx FIFO OverRun Error Interrupt Enable     */
+#define SDIO_MASK_CMDRENDIE_Pos        (6U)                                    
+#define SDIO_MASK_CMDRENDIE_Msk        (0x1UL << SDIO_MASK_CMDRENDIE_Pos)       /*!< 0x00000040 */
+#define SDIO_MASK_CMDRENDIE            SDIO_MASK_CMDRENDIE_Msk                 /*!<Command Response Received Interrupt Enable */
+#define SDIO_MASK_CMDSENTIE_Pos        (7U)                                    
+#define SDIO_MASK_CMDSENTIE_Msk        (0x1UL << SDIO_MASK_CMDSENTIE_Pos)       /*!< 0x00000080 */
+#define SDIO_MASK_CMDSENTIE            SDIO_MASK_CMDSENTIE_Msk                 /*!<Command Sent Interrupt Enable              */
+#define SDIO_MASK_DATAENDIE_Pos        (8U)                                    
+#define SDIO_MASK_DATAENDIE_Msk        (0x1UL << SDIO_MASK_DATAENDIE_Pos)       /*!< 0x00000100 */
+#define SDIO_MASK_DATAENDIE            SDIO_MASK_DATAENDIE_Msk                 /*!<Data End Interrupt Enable                  */
+#define SDIO_MASK_DBCKENDIE_Pos        (10U)                                   
+#define SDIO_MASK_DBCKENDIE_Msk        (0x1UL << SDIO_MASK_DBCKENDIE_Pos)       /*!< 0x00000400 */
+#define SDIO_MASK_DBCKENDIE            SDIO_MASK_DBCKENDIE_Msk                 /*!<Data Block End Interrupt Enable            */
+#define SDIO_MASK_CMDACTIE_Pos         (11U)                                   
+#define SDIO_MASK_CMDACTIE_Msk         (0x1UL << SDIO_MASK_CMDACTIE_Pos)        /*!< 0x00000800 */
+#define SDIO_MASK_CMDACTIE             SDIO_MASK_CMDACTIE_Msk                  /*!<CCommand Acting Interrupt Enable           */
+#define SDIO_MASK_TXACTIE_Pos          (12U)                                   
+#define SDIO_MASK_TXACTIE_Msk          (0x1UL << SDIO_MASK_TXACTIE_Pos)         /*!< 0x00001000 */
+#define SDIO_MASK_TXACTIE              SDIO_MASK_TXACTIE_Msk                   /*!<Data Transmit Acting Interrupt Enable      */
+#define SDIO_MASK_RXACTIE_Pos          (13U)                                   
+#define SDIO_MASK_RXACTIE_Msk          (0x1UL << SDIO_MASK_RXACTIE_Pos)         /*!< 0x00002000 */
+#define SDIO_MASK_RXACTIE              SDIO_MASK_RXACTIE_Msk                   /*!<Data receive acting interrupt enabled      */
+#define SDIO_MASK_TXFIFOHEIE_Pos       (14U)                                   
+#define SDIO_MASK_TXFIFOHEIE_Msk       (0x1UL << SDIO_MASK_TXFIFOHEIE_Pos)      /*!< 0x00004000 */
+#define SDIO_MASK_TXFIFOHEIE           SDIO_MASK_TXFIFOHEIE_Msk                /*!<Tx FIFO Half Empty interrupt Enable        */
+#define SDIO_MASK_RXFIFOHFIE_Pos       (15U)                                   
+#define SDIO_MASK_RXFIFOHFIE_Msk       (0x1UL << SDIO_MASK_RXFIFOHFIE_Pos)      /*!< 0x00008000 */
+#define SDIO_MASK_RXFIFOHFIE           SDIO_MASK_RXFIFOHFIE_Msk                /*!<Rx FIFO Half Full interrupt Enable         */
+#define SDIO_MASK_TXFIFOFIE_Pos        (16U)                                   
+#define SDIO_MASK_TXFIFOFIE_Msk        (0x1UL << SDIO_MASK_TXFIFOFIE_Pos)       /*!< 0x00010000 */
+#define SDIO_MASK_TXFIFOFIE            SDIO_MASK_TXFIFOFIE_Msk                 /*!<Tx FIFO Full interrupt Enable              */
+#define SDIO_MASK_RXFIFOFIE_Pos        (17U)                                   
+#define SDIO_MASK_RXFIFOFIE_Msk        (0x1UL << SDIO_MASK_RXFIFOFIE_Pos)       /*!< 0x00020000 */
+#define SDIO_MASK_RXFIFOFIE            SDIO_MASK_RXFIFOFIE_Msk                 /*!<Rx FIFO Full interrupt Enable              */
+#define SDIO_MASK_TXFIFOEIE_Pos        (18U)                                   
+#define SDIO_MASK_TXFIFOEIE_Msk        (0x1UL << SDIO_MASK_TXFIFOEIE_Pos)       /*!< 0x00040000 */
+#define SDIO_MASK_TXFIFOEIE            SDIO_MASK_TXFIFOEIE_Msk                 /*!<Tx FIFO Empty interrupt Enable             */
+#define SDIO_MASK_RXFIFOEIE_Pos        (19U)                                   
+#define SDIO_MASK_RXFIFOEIE_Msk        (0x1UL << SDIO_MASK_RXFIFOEIE_Pos)       /*!< 0x00080000 */
+#define SDIO_MASK_RXFIFOEIE            SDIO_MASK_RXFIFOEIE_Msk                 /*!<Rx FIFO Empty interrupt Enable             */
+#define SDIO_MASK_TXDAVLIE_Pos         (20U)                                   
+#define SDIO_MASK_TXDAVLIE_Msk         (0x1UL << SDIO_MASK_TXDAVLIE_Pos)        /*!< 0x00100000 */
+#define SDIO_MASK_TXDAVLIE             SDIO_MASK_TXDAVLIE_Msk                  /*!<Data available in Tx FIFO interrupt Enable */
+#define SDIO_MASK_RXDAVLIE_Pos         (21U)                                   
+#define SDIO_MASK_RXDAVLIE_Msk         (0x1UL << SDIO_MASK_RXDAVLIE_Pos)        /*!< 0x00200000 */
+#define SDIO_MASK_RXDAVLIE             SDIO_MASK_RXDAVLIE_Msk                  /*!<Data available in Rx FIFO interrupt Enable */
+#define SDIO_MASK_SDIOITIE_Pos         (22U)                                   
+#define SDIO_MASK_SDIOITIE_Msk         (0x1UL << SDIO_MASK_SDIOITIE_Pos)        /*!< 0x00400000 */
+#define SDIO_MASK_SDIOITIE             SDIO_MASK_SDIOITIE_Msk                  /*!<SDIO Mode Interrupt Received interrupt Enable */
+
+/*****************  Bit definition for SDIO_FIFOCNT register  *****************/
+#define SDIO_FIFOCNT_FIFOCOUNT_Pos     (0U)                                    
+#define SDIO_FIFOCNT_FIFOCOUNT_Msk     (0xFFFFFFUL << SDIO_FIFOCNT_FIFOCOUNT_Pos) /*!< 0x00FFFFFF */
+#define SDIO_FIFOCNT_FIFOCOUNT         SDIO_FIFOCNT_FIFOCOUNT_Msk              /*!<Remaining number of words to be written to or read from the FIFO */
+
+/******************  Bit definition for SDIO_FIFO register  *******************/
+#define SDIO_FIFO_FIFODATA_Pos         (0U)                                    
+#define SDIO_FIFO_FIFODATA_Msk         (0xFFFFFFFFUL << SDIO_FIFO_FIFODATA_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_FIFO_FIFODATA             SDIO_FIFO_FIFODATA_Msk                  /*!<Receive and transmit FIFO data */
+
+/******************************************************************************/
+/*                                                                            */
+/*                        Serial Peripheral Interface                         */
+/*                                                                            */
+/******************************************************************************/
+#define SPI_I2S_FULLDUPLEX_SUPPORT                                             /*!< I2S Full-Duplex support */
+
+/*******************  Bit definition for SPI_CR1 register  ********************/
+#define SPI_CR1_CPHA_Pos            (0U)                                       
+#define SPI_CR1_CPHA_Msk            (0x1UL << SPI_CR1_CPHA_Pos)                 /*!< 0x00000001 */
+#define SPI_CR1_CPHA                SPI_CR1_CPHA_Msk                           /*!<Clock Phase      */
+#define SPI_CR1_CPOL_Pos            (1U)                                       
+#define SPI_CR1_CPOL_Msk            (0x1UL << SPI_CR1_CPOL_Pos)                 /*!< 0x00000002 */
+#define SPI_CR1_CPOL                SPI_CR1_CPOL_Msk                           /*!<Clock Polarity   */
+#define SPI_CR1_MSTR_Pos            (2U)                                       
+#define SPI_CR1_MSTR_Msk            (0x1UL << SPI_CR1_MSTR_Pos)                 /*!< 0x00000004 */
+#define SPI_CR1_MSTR                SPI_CR1_MSTR_Msk                           /*!<Master Selection */
+
+#define SPI_CR1_BR_Pos              (3U)                                       
+#define SPI_CR1_BR_Msk              (0x7UL << SPI_CR1_BR_Pos)                   /*!< 0x00000038 */
+#define SPI_CR1_BR                  SPI_CR1_BR_Msk                             /*!<BR[2:0] bits (Baud Rate Control) */
+#define SPI_CR1_BR_0                (0x1UL << SPI_CR1_BR_Pos)                   /*!< 0x00000008 */
+#define SPI_CR1_BR_1                (0x2UL << SPI_CR1_BR_Pos)                   /*!< 0x00000010 */
+#define SPI_CR1_BR_2                (0x4UL << SPI_CR1_BR_Pos)                   /*!< 0x00000020 */
+
+#define SPI_CR1_SPE_Pos             (6U)                                       
+#define SPI_CR1_SPE_Msk             (0x1UL << SPI_CR1_SPE_Pos)                  /*!< 0x00000040 */
+#define SPI_CR1_SPE                 SPI_CR1_SPE_Msk                            /*!<SPI Enable                          */
+#define SPI_CR1_LSBFIRST_Pos        (7U)                                       
+#define SPI_CR1_LSBFIRST_Msk        (0x1UL << SPI_CR1_LSBFIRST_Pos)             /*!< 0x00000080 */
+#define SPI_CR1_LSBFIRST            SPI_CR1_LSBFIRST_Msk                       /*!<Frame Format                        */
+#define SPI_CR1_SSI_Pos             (8U)                                       
+#define SPI_CR1_SSI_Msk             (0x1UL << SPI_CR1_SSI_Pos)                  /*!< 0x00000100 */
+#define SPI_CR1_SSI                 SPI_CR1_SSI_Msk                            /*!<Internal slave select               */
+#define SPI_CR1_SSM_Pos             (9U)                                       
+#define SPI_CR1_SSM_Msk             (0x1UL << SPI_CR1_SSM_Pos)                  /*!< 0x00000200 */
+#define SPI_CR1_SSM                 SPI_CR1_SSM_Msk                            /*!<Software slave management           */
+#define SPI_CR1_RXONLY_Pos          (10U)                                      
+#define SPI_CR1_RXONLY_Msk          (0x1UL << SPI_CR1_RXONLY_Pos)               /*!< 0x00000400 */
+#define SPI_CR1_RXONLY              SPI_CR1_RXONLY_Msk                         /*!<Receive only                        */
+#define SPI_CR1_DFF_Pos             (11U)                                      
+#define SPI_CR1_DFF_Msk             (0x1UL << SPI_CR1_DFF_Pos)                  /*!< 0x00000800 */
+#define SPI_CR1_DFF                 SPI_CR1_DFF_Msk                            /*!<Data Frame Format                   */
+#define SPI_CR1_CRCNEXT_Pos         (12U)                                      
+#define SPI_CR1_CRCNEXT_Msk         (0x1UL << SPI_CR1_CRCNEXT_Pos)              /*!< 0x00001000 */
+#define SPI_CR1_CRCNEXT             SPI_CR1_CRCNEXT_Msk                        /*!<Transmit CRC next                   */
+#define SPI_CR1_CRCEN_Pos           (13U)                                      
+#define SPI_CR1_CRCEN_Msk           (0x1UL << SPI_CR1_CRCEN_Pos)                /*!< 0x00002000 */
+#define SPI_CR1_CRCEN               SPI_CR1_CRCEN_Msk                          /*!<Hardware CRC calculation enable     */
+#define SPI_CR1_BIDIOE_Pos          (14U)                                      
+#define SPI_CR1_BIDIOE_Msk          (0x1UL << SPI_CR1_BIDIOE_Pos)               /*!< 0x00004000 */
+#define SPI_CR1_BIDIOE              SPI_CR1_BIDIOE_Msk                         /*!<Output enable in bidirectional mode */
+#define SPI_CR1_BIDIMODE_Pos        (15U)                                      
+#define SPI_CR1_BIDIMODE_Msk        (0x1UL << SPI_CR1_BIDIMODE_Pos)             /*!< 0x00008000 */
+#define SPI_CR1_BIDIMODE            SPI_CR1_BIDIMODE_Msk                       /*!<Bidirectional data mode enable      */
+
+/*******************  Bit definition for SPI_CR2 register  ********************/
+#define SPI_CR2_RXDMAEN_Pos         (0U)                                       
+#define SPI_CR2_RXDMAEN_Msk         (0x1UL << SPI_CR2_RXDMAEN_Pos)              /*!< 0x00000001 */
+#define SPI_CR2_RXDMAEN             SPI_CR2_RXDMAEN_Msk                        /*!<Rx Buffer DMA Enable                 */
+#define SPI_CR2_TXDMAEN_Pos         (1U)                                       
+#define SPI_CR2_TXDMAEN_Msk         (0x1UL << SPI_CR2_TXDMAEN_Pos)              /*!< 0x00000002 */
+#define SPI_CR2_TXDMAEN             SPI_CR2_TXDMAEN_Msk                        /*!<Tx Buffer DMA Enable                 */
+#define SPI_CR2_SSOE_Pos            (2U)                                       
+#define SPI_CR2_SSOE_Msk            (0x1UL << SPI_CR2_SSOE_Pos)                 /*!< 0x00000004 */
+#define SPI_CR2_SSOE                SPI_CR2_SSOE_Msk                           /*!<SS Output Enable                     */
+#define SPI_CR2_FRF_Pos             (4U)                                       
+#define SPI_CR2_FRF_Msk             (0x1UL << SPI_CR2_FRF_Pos)                  /*!< 0x00000010 */
+#define SPI_CR2_FRF                 SPI_CR2_FRF_Msk                            /*!<Frame Format                         */
+#define SPI_CR2_ERRIE_Pos           (5U)                                       
+#define SPI_CR2_ERRIE_Msk           (0x1UL << SPI_CR2_ERRIE_Pos)                /*!< 0x00000020 */
+#define SPI_CR2_ERRIE               SPI_CR2_ERRIE_Msk                          /*!<Error Interrupt Enable               */
+#define SPI_CR2_RXNEIE_Pos          (6U)                                       
+#define SPI_CR2_RXNEIE_Msk          (0x1UL << SPI_CR2_RXNEIE_Pos)               /*!< 0x00000040 */
+#define SPI_CR2_RXNEIE              SPI_CR2_RXNEIE_Msk                         /*!<RX buffer Not Empty Interrupt Enable */
+#define SPI_CR2_TXEIE_Pos           (7U)                                       
+#define SPI_CR2_TXEIE_Msk           (0x1UL << SPI_CR2_TXEIE_Pos)                /*!< 0x00000080 */
+#define SPI_CR2_TXEIE               SPI_CR2_TXEIE_Msk                          /*!<Tx buffer Empty Interrupt Enable     */
+
+/********************  Bit definition for SPI_SR register  ********************/
+#define SPI_SR_RXNE_Pos             (0U)                                       
+#define SPI_SR_RXNE_Msk             (0x1UL << SPI_SR_RXNE_Pos)                  /*!< 0x00000001 */
+#define SPI_SR_RXNE                 SPI_SR_RXNE_Msk                            /*!<Receive buffer Not Empty */
+#define SPI_SR_TXE_Pos              (1U)                                       
+#define SPI_SR_TXE_Msk              (0x1UL << SPI_SR_TXE_Pos)                   /*!< 0x00000002 */
+#define SPI_SR_TXE                  SPI_SR_TXE_Msk                             /*!<Transmit buffer Empty    */
+#define SPI_SR_CHSIDE_Pos           (2U)                                       
+#define SPI_SR_CHSIDE_Msk           (0x1UL << SPI_SR_CHSIDE_Pos)                /*!< 0x00000004 */
+#define SPI_SR_CHSIDE               SPI_SR_CHSIDE_Msk                          /*!<Channel side             */
+#define SPI_SR_UDR_Pos              (3U)                                       
+#define SPI_SR_UDR_Msk              (0x1UL << SPI_SR_UDR_Pos)                   /*!< 0x00000008 */
+#define SPI_SR_UDR                  SPI_SR_UDR_Msk                             /*!<Underrun flag            */
+#define SPI_SR_CRCERR_Pos           (4U)                                       
+#define SPI_SR_CRCERR_Msk           (0x1UL << SPI_SR_CRCERR_Pos)                /*!< 0x00000010 */
+#define SPI_SR_CRCERR               SPI_SR_CRCERR_Msk                          /*!<CRC Error flag           */
+#define SPI_SR_MODF_Pos             (5U)                                       
+#define SPI_SR_MODF_Msk             (0x1UL << SPI_SR_MODF_Pos)                  /*!< 0x00000020 */
+#define SPI_SR_MODF                 SPI_SR_MODF_Msk                            /*!<Mode fault               */
+#define SPI_SR_OVR_Pos              (6U)                                       
+#define SPI_SR_OVR_Msk              (0x1UL << SPI_SR_OVR_Pos)                   /*!< 0x00000040 */
+#define SPI_SR_OVR                  SPI_SR_OVR_Msk                             /*!<Overrun flag             */
+#define SPI_SR_BSY_Pos              (7U)                                       
+#define SPI_SR_BSY_Msk              (0x1UL << SPI_SR_BSY_Pos)                   /*!< 0x00000080 */
+#define SPI_SR_BSY                  SPI_SR_BSY_Msk                             /*!<Busy flag                */
+#define SPI_SR_FRE_Pos              (8U)                                       
+#define SPI_SR_FRE_Msk              (0x1UL << SPI_SR_FRE_Pos)                   /*!< 0x00000100 */
+#define SPI_SR_FRE                  SPI_SR_FRE_Msk                             /*!<Frame format error flag  */
+
+/********************  Bit definition for SPI_DR register  ********************/
+#define SPI_DR_DR_Pos               (0U)                                       
+#define SPI_DR_DR_Msk               (0xFFFFUL << SPI_DR_DR_Pos)                 /*!< 0x0000FFFF */
+#define SPI_DR_DR                   SPI_DR_DR_Msk                              /*!<Data Register           */
+
+/*******************  Bit definition for SPI_CRCPR register  ******************/
+#define SPI_CRCPR_CRCPOLY_Pos       (0U)                                       
+#define SPI_CRCPR_CRCPOLY_Msk       (0xFFFFUL << SPI_CRCPR_CRCPOLY_Pos)         /*!< 0x0000FFFF */
+#define SPI_CRCPR_CRCPOLY           SPI_CRCPR_CRCPOLY_Msk                      /*!<CRC polynomial register */
+
+/******************  Bit definition for SPI_RXCRCR register  ******************/
+#define SPI_RXCRCR_RXCRC_Pos        (0U)                                       
+#define SPI_RXCRCR_RXCRC_Msk        (0xFFFFUL << SPI_RXCRCR_RXCRC_Pos)          /*!< 0x0000FFFF */
+#define SPI_RXCRCR_RXCRC            SPI_RXCRCR_RXCRC_Msk                       /*!<Rx CRC Register         */
+
+/******************  Bit definition for SPI_TXCRCR register  ******************/
+#define SPI_TXCRCR_TXCRC_Pos        (0U)                                       
+#define SPI_TXCRCR_TXCRC_Msk        (0xFFFFUL << SPI_TXCRCR_TXCRC_Pos)          /*!< 0x0000FFFF */
+#define SPI_TXCRCR_TXCRC            SPI_TXCRCR_TXCRC_Msk                       /*!<Tx CRC Register         */
+
+/******************  Bit definition for SPI_I2SCFGR register  *****************/
+#define SPI_I2SCFGR_CHLEN_Pos       (0U)                                       
+#define SPI_I2SCFGR_CHLEN_Msk       (0x1UL << SPI_I2SCFGR_CHLEN_Pos)            /*!< 0x00000001 */
+#define SPI_I2SCFGR_CHLEN           SPI_I2SCFGR_CHLEN_Msk                      /*!<Channel length (number of bits per audio channel) */
+
+#define SPI_I2SCFGR_DATLEN_Pos      (1U)                                       
+#define SPI_I2SCFGR_DATLEN_Msk      (0x3UL << SPI_I2SCFGR_DATLEN_Pos)           /*!< 0x00000006 */
+#define SPI_I2SCFGR_DATLEN          SPI_I2SCFGR_DATLEN_Msk                     /*!<DATLEN[1:0] bits (Data length to be transferred)  */
+#define SPI_I2SCFGR_DATLEN_0        (0x1UL << SPI_I2SCFGR_DATLEN_Pos)           /*!< 0x00000002 */
+#define SPI_I2SCFGR_DATLEN_1        (0x2UL << SPI_I2SCFGR_DATLEN_Pos)           /*!< 0x00000004 */
+
+#define SPI_I2SCFGR_CKPOL_Pos       (3U)                                       
+#define SPI_I2SCFGR_CKPOL_Msk       (0x1UL << SPI_I2SCFGR_CKPOL_Pos)            /*!< 0x00000008 */
+#define SPI_I2SCFGR_CKPOL           SPI_I2SCFGR_CKPOL_Msk                      /*!<steady state clock polarity               */
+
+#define SPI_I2SCFGR_I2SSTD_Pos      (4U)                                       
+#define SPI_I2SCFGR_I2SSTD_Msk      (0x3UL << SPI_I2SCFGR_I2SSTD_Pos)           /*!< 0x00000030 */
+#define SPI_I2SCFGR_I2SSTD          SPI_I2SCFGR_I2SSTD_Msk                     /*!<I2SSTD[1:0] bits (I2S standard selection) */
+#define SPI_I2SCFGR_I2SSTD_0        (0x1UL << SPI_I2SCFGR_I2SSTD_Pos)           /*!< 0x00000010 */
+#define SPI_I2SCFGR_I2SSTD_1        (0x2UL << SPI_I2SCFGR_I2SSTD_Pos)           /*!< 0x00000020 */
+
+#define SPI_I2SCFGR_PCMSYNC_Pos     (7U)                                       
+#define SPI_I2SCFGR_PCMSYNC_Msk     (0x1UL << SPI_I2SCFGR_PCMSYNC_Pos)          /*!< 0x00000080 */
+#define SPI_I2SCFGR_PCMSYNC         SPI_I2SCFGR_PCMSYNC_Msk                    /*!<PCM frame synchronization                 */
+
+#define SPI_I2SCFGR_I2SCFG_Pos      (8U)                                       
+#define SPI_I2SCFGR_I2SCFG_Msk      (0x3UL << SPI_I2SCFGR_I2SCFG_Pos)           /*!< 0x00000300 */
+#define SPI_I2SCFGR_I2SCFG          SPI_I2SCFGR_I2SCFG_Msk                     /*!<I2SCFG[1:0] bits (I2S configuration mode) */
+#define SPI_I2SCFGR_I2SCFG_0        (0x1UL << SPI_I2SCFGR_I2SCFG_Pos)           /*!< 0x00000100 */
+#define SPI_I2SCFGR_I2SCFG_1        (0x2UL << SPI_I2SCFGR_I2SCFG_Pos)           /*!< 0x00000200 */
+
+#define SPI_I2SCFGR_I2SE_Pos        (10U)                                      
+#define SPI_I2SCFGR_I2SE_Msk        (0x1UL << SPI_I2SCFGR_I2SE_Pos)             /*!< 0x00000400 */
+#define SPI_I2SCFGR_I2SE            SPI_I2SCFGR_I2SE_Msk                       /*!<I2S Enable         */
+#define SPI_I2SCFGR_I2SMOD_Pos      (11U)                                      
+#define SPI_I2SCFGR_I2SMOD_Msk      (0x1UL << SPI_I2SCFGR_I2SMOD_Pos)           /*!< 0x00000800 */
+#define SPI_I2SCFGR_I2SMOD          SPI_I2SCFGR_I2SMOD_Msk                     /*!<I2S mode selection */
+#define SPI_I2SCFGR_ASTRTEN_Pos     (12U)                                      
+#define SPI_I2SCFGR_ASTRTEN_Msk     (0x1UL << SPI_I2SCFGR_ASTRTEN_Pos)          /*!< 0x00001000 */
+#define SPI_I2SCFGR_ASTRTEN         SPI_I2SCFGR_ASTRTEN_Msk                    /*!<Asynchronous start enable */
+
+/******************  Bit definition for SPI_I2SPR register  *******************/
+#define SPI_I2SPR_I2SDIV_Pos        (0U)                                       
+#define SPI_I2SPR_I2SDIV_Msk        (0xFFUL << SPI_I2SPR_I2SDIV_Pos)            /*!< 0x000000FF */
+#define SPI_I2SPR_I2SDIV            SPI_I2SPR_I2SDIV_Msk                       /*!<I2S Linear prescaler         */
+#define SPI_I2SPR_ODD_Pos           (8U)                                       
+#define SPI_I2SPR_ODD_Msk           (0x1UL << SPI_I2SPR_ODD_Pos)                /*!< 0x00000100 */
+#define SPI_I2SPR_ODD               SPI_I2SPR_ODD_Msk                          /*!<Odd factor for the prescaler */
+#define SPI_I2SPR_MCKOE_Pos         (9U)                                       
+#define SPI_I2SPR_MCKOE_Msk         (0x1UL << SPI_I2SPR_MCKOE_Pos)              /*!< 0x00000200 */
+#define SPI_I2SPR_MCKOE             SPI_I2SPR_MCKOE_Msk                        /*!<Master Clock Output Enable   */
+
+/******************************************************************************/
+/*                                                                            */
+/*                                 SYSCFG                                     */
+/*                                                                            */
+/******************************************************************************/
+/******************  Bit definition for SYSCFG_MEMRMP register  ***************/
+#define SYSCFG_MEMRMP_MEM_MODE_Pos           (0U)                              
+#define SYSCFG_MEMRMP_MEM_MODE_Msk           (0x7UL << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000007 */
+#define SYSCFG_MEMRMP_MEM_MODE               SYSCFG_MEMRMP_MEM_MODE_Msk        /*!< SYSCFG_Memory Remap Config */
+#define SYSCFG_MEMRMP_MEM_MODE_0             (0x1UL << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000001 */
+#define SYSCFG_MEMRMP_MEM_MODE_1             (0x2UL << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000002 */
+#define SYSCFG_MEMRMP_MEM_MODE_2             (0x4UL << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000004 */
+#define SYSCFG_MEMRMP_UFB_MODE_Pos           (8U)                              
+#define SYSCFG_MEMRMP_UFB_MODE_Msk           (0x1UL << SYSCFG_MEMRMP_UFB_MODE_Pos) /*!< 0x00000100 */
+#define SYSCFG_MEMRMP_UFB_MODE               SYSCFG_MEMRMP_UFB_MODE_Msk        /*!< User Flash Bank mode    */
+#define SYSCFG_MEMRMP_SWP_FMC_Pos            (10U)                             
+#define SYSCFG_MEMRMP_SWP_FMC_Msk            (0x3UL << SYSCFG_MEMRMP_SWP_FMC_Pos) /*!< 0x00000C00 */
+#define SYSCFG_MEMRMP_SWP_FMC                SYSCFG_MEMRMP_SWP_FMC_Msk         /*!< FMC memory mapping swap */
+#define SYSCFG_MEMRMP_SWP_FMC_0              (0x1UL << SYSCFG_MEMRMP_SWP_FMC_Pos) /*!< 0x00000400 */
+/* Legacy Defines */
+#define SYSCFG_SWP_FMC                  SYSCFG_MEMRMP_SWP_FMC
+/******************  Bit definition for SYSCFG_PMC register  ******************/
+#define SYSCFG_PMC_ADCxDC2_Pos               (16U)                             
+#define SYSCFG_PMC_ADCxDC2_Msk               (0x7UL << SYSCFG_PMC_ADCxDC2_Pos)  /*!< 0x00070000 */
+#define SYSCFG_PMC_ADCxDC2                   SYSCFG_PMC_ADCxDC2_Msk            /*!< Refer to AN4073 on how to use this bit  */
+#define SYSCFG_PMC_ADC1DC2_Pos               (16U)                             
+#define SYSCFG_PMC_ADC1DC2_Msk               (0x1UL << SYSCFG_PMC_ADC1DC2_Pos)  /*!< 0x00010000 */
+#define SYSCFG_PMC_ADC1DC2                   SYSCFG_PMC_ADC1DC2_Msk            /*!< Refer to AN4073 on how to use this bit  */
+#define SYSCFG_PMC_ADC2DC2_Pos               (17U)                             
+#define SYSCFG_PMC_ADC2DC2_Msk               (0x1UL << SYSCFG_PMC_ADC2DC2_Pos)  /*!< 0x00020000 */
+#define SYSCFG_PMC_ADC2DC2                   SYSCFG_PMC_ADC2DC2_Msk            /*!< Refer to AN4073 on how to use this bit  */
+#define SYSCFG_PMC_ADC3DC2_Pos               (18U)                             
+#define SYSCFG_PMC_ADC3DC2_Msk               (0x1UL << SYSCFG_PMC_ADC3DC2_Pos)  /*!< 0x00040000 */
+#define SYSCFG_PMC_ADC3DC2                   SYSCFG_PMC_ADC3DC2_Msk            /*!< Refer to AN4073 on how to use this bit  */
+#define SYSCFG_PMC_MII_RMII_SEL_Pos          (23U)                             
+#define SYSCFG_PMC_MII_RMII_SEL_Msk          (0x1UL << SYSCFG_PMC_MII_RMII_SEL_Pos) /*!< 0x00800000 */
+#define SYSCFG_PMC_MII_RMII_SEL              SYSCFG_PMC_MII_RMII_SEL_Msk       /*!<Ethernet PHY interface selection */
+
+/*****************  Bit definition for SYSCFG_EXTICR1 register  ***************/
+#define SYSCFG_EXTICR1_EXTI0_Pos             (0U)                              
+#define SYSCFG_EXTICR1_EXTI0_Msk             (0xFUL << SYSCFG_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */
+#define SYSCFG_EXTICR1_EXTI0                 SYSCFG_EXTICR1_EXTI0_Msk          /*!<EXTI 0 configuration */
+#define SYSCFG_EXTICR1_EXTI1_Pos             (4U)                              
+#define SYSCFG_EXTICR1_EXTI1_Msk             (0xFUL << SYSCFG_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */
+#define SYSCFG_EXTICR1_EXTI1                 SYSCFG_EXTICR1_EXTI1_Msk          /*!<EXTI 1 configuration */
+#define SYSCFG_EXTICR1_EXTI2_Pos             (8U)                              
+#define SYSCFG_EXTICR1_EXTI2_Msk             (0xFUL << SYSCFG_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */
+#define SYSCFG_EXTICR1_EXTI2                 SYSCFG_EXTICR1_EXTI2_Msk          /*!<EXTI 2 configuration */
+#define SYSCFG_EXTICR1_EXTI3_Pos             (12U)                             
+#define SYSCFG_EXTICR1_EXTI3_Msk             (0xFUL << SYSCFG_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */
+#define SYSCFG_EXTICR1_EXTI3                 SYSCFG_EXTICR1_EXTI3_Msk          /*!<EXTI 3 configuration */
+/**
+  * @brief   EXTI0 configuration  
+  */
+#define SYSCFG_EXTICR1_EXTI0_PA              0x0000U                           /*!<PA[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PB              0x0001U                           /*!<PB[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PC              0x0002U                           /*!<PC[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PD              0x0003U                           /*!<PD[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PE              0x0004U                           /*!<PE[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PF              0x0005U                           /*!<PF[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PG              0x0006U                           /*!<PG[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PH              0x0007U                           /*!<PH[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PI              0x0008U                           /*!<PI[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PJ              0x0009U                           /*!<PJ[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PK              0x000AU                           /*!<PK[0] pin */
+
+/**
+  * @brief   EXTI1 configuration  
+  */
+#define SYSCFG_EXTICR1_EXTI1_PA              0x0000U                           /*!<PA[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PB              0x0010U                           /*!<PB[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PC              0x0020U                           /*!<PC[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PD              0x0030U                           /*!<PD[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PE              0x0040U                           /*!<PE[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PF              0x0050U                           /*!<PF[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PG              0x0060U                           /*!<PG[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PH              0x0070U                           /*!<PH[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PI              0x0080U                           /*!<PI[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PJ              0x0090U                           /*!<PJ[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PK              0x00A0U                           /*!<PK[1] pin */
+
+/**
+  * @brief   EXTI2 configuration  
+  */
+#define SYSCFG_EXTICR1_EXTI2_PA              0x0000U                           /*!<PA[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PB              0x0100U                           /*!<PB[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PC              0x0200U                           /*!<PC[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PD              0x0300U                           /*!<PD[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PE              0x0400U                           /*!<PE[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PF              0x0500U                           /*!<PF[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PG              0x0600U                           /*!<PG[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PH              0x0700U                           /*!<PH[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PI              0x0800U                           /*!<PI[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PJ              0x0900U                           /*!<PJ[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PK              0x0A00U                           /*!<PK[2] pin */
+
+/**
+  * @brief   EXTI3 configuration  
+  */
+#define SYSCFG_EXTICR1_EXTI3_PA              0x0000U                           /*!<PA[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PB              0x1000U                           /*!<PB[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PC              0x2000U                           /*!<PC[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PD              0x3000U                           /*!<PD[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PE              0x4000U                           /*!<PE[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PF              0x5000U                           /*!<PF[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PG              0x6000U                           /*!<PG[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PH              0x7000U                           /*!<PH[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PI              0x8000U                           /*!<PI[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PJ              0x9000U                           /*!<PJ[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PK              0xA000U                           /*!<PK[3] pin */
+
+/*****************  Bit definition for SYSCFG_EXTICR2 register  ***************/
+#define SYSCFG_EXTICR2_EXTI4_Pos             (0U)                              
+#define SYSCFG_EXTICR2_EXTI4_Msk             (0xFUL << SYSCFG_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */
+#define SYSCFG_EXTICR2_EXTI4                 SYSCFG_EXTICR2_EXTI4_Msk          /*!<EXTI 4 configuration */
+#define SYSCFG_EXTICR2_EXTI5_Pos             (4U)                              
+#define SYSCFG_EXTICR2_EXTI5_Msk             (0xFUL << SYSCFG_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */
+#define SYSCFG_EXTICR2_EXTI5                 SYSCFG_EXTICR2_EXTI5_Msk          /*!<EXTI 5 configuration */
+#define SYSCFG_EXTICR2_EXTI6_Pos             (8U)                              
+#define SYSCFG_EXTICR2_EXTI6_Msk             (0xFUL << SYSCFG_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */
+#define SYSCFG_EXTICR2_EXTI6                 SYSCFG_EXTICR2_EXTI6_Msk          /*!<EXTI 6 configuration */
+#define SYSCFG_EXTICR2_EXTI7_Pos             (12U)                             
+#define SYSCFG_EXTICR2_EXTI7_Msk             (0xFUL << SYSCFG_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */
+#define SYSCFG_EXTICR2_EXTI7                 SYSCFG_EXTICR2_EXTI7_Msk          /*!<EXTI 7 configuration */
+
+/**
+  * @brief   EXTI4 configuration  
+  */
+#define SYSCFG_EXTICR2_EXTI4_PA              0x0000U                           /*!<PA[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PB              0x0001U                           /*!<PB[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PC              0x0002U                           /*!<PC[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PD              0x0003U                           /*!<PD[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PE              0x0004U                           /*!<PE[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PF              0x0005U                           /*!<PF[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PG              0x0006U                           /*!<PG[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PH              0x0007U                           /*!<PH[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PI              0x0008U                           /*!<PI[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PJ              0x0009U                           /*!<PJ[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PK              0x000AU                           /*!<PK[4] pin */
+
+/**
+  * @brief   EXTI5 configuration  
+  */
+#define SYSCFG_EXTICR2_EXTI5_PA              0x0000U                           /*!<PA[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PB              0x0010U                           /*!<PB[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PC              0x0020U                           /*!<PC[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PD              0x0030U                           /*!<PD[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PE              0x0040U                           /*!<PE[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PF              0x0050U                           /*!<PF[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PG              0x0060U                           /*!<PG[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PH              0x0070U                           /*!<PH[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PI              0x0080U                           /*!<PI[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PJ              0x0090U                           /*!<PJ[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PK              0x00A0U                           /*!<PK[5] pin */
+
+/**
+  * @brief   EXTI6 configuration  
+  */
+#define SYSCFG_EXTICR2_EXTI6_PA              0x0000U                           /*!<PA[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PB              0x0100U                           /*!<PB[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PC              0x0200U                           /*!<PC[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PD              0x0300U                           /*!<PD[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PE              0x0400U                           /*!<PE[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PF              0x0500U                           /*!<PF[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PG              0x0600U                           /*!<PG[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PH              0x0700U                           /*!<PH[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PI              0x0800U                           /*!<PI[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PJ              0x0900U                           /*!<PJ[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PK              0x0A00U                           /*!<PK[6] pin */
+
+/**
+  * @brief   EXTI7 configuration  
+  */
+#define SYSCFG_EXTICR2_EXTI7_PA              0x0000U                           /*!<PA[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PB              0x1000U                           /*!<PB[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PC              0x2000U                           /*!<PC[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PD              0x3000U                           /*!<PD[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PE              0x4000U                           /*!<PE[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PF              0x5000U                           /*!<PF[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PG              0x6000U                           /*!<PG[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PH              0x7000U                           /*!<PH[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PI              0x8000U                           /*!<PI[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PJ              0x9000U                           /*!<PJ[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PK              0xA000U                           /*!<PK[7] pin */
+
+/*****************  Bit definition for SYSCFG_EXTICR3 register  ***************/
+#define SYSCFG_EXTICR3_EXTI8_Pos             (0U)                              
+#define SYSCFG_EXTICR3_EXTI8_Msk             (0xFUL << SYSCFG_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */
+#define SYSCFG_EXTICR3_EXTI8                 SYSCFG_EXTICR3_EXTI8_Msk          /*!<EXTI 8 configuration */
+#define SYSCFG_EXTICR3_EXTI9_Pos             (4U)                              
+#define SYSCFG_EXTICR3_EXTI9_Msk             (0xFUL << SYSCFG_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */
+#define SYSCFG_EXTICR3_EXTI9                 SYSCFG_EXTICR3_EXTI9_Msk          /*!<EXTI 9 configuration */
+#define SYSCFG_EXTICR3_EXTI10_Pos            (8U)                              
+#define SYSCFG_EXTICR3_EXTI10_Msk            (0xFUL << SYSCFG_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */
+#define SYSCFG_EXTICR3_EXTI10                SYSCFG_EXTICR3_EXTI10_Msk         /*!<EXTI 10 configuration */
+#define SYSCFG_EXTICR3_EXTI11_Pos            (12U)                             
+#define SYSCFG_EXTICR3_EXTI11_Msk            (0xFUL << SYSCFG_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */
+#define SYSCFG_EXTICR3_EXTI11                SYSCFG_EXTICR3_EXTI11_Msk         /*!<EXTI 11 configuration */
+
+/**
+  * @brief   EXTI8 configuration  
+  */
+#define SYSCFG_EXTICR3_EXTI8_PA              0x0000U                           /*!<PA[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PB              0x0001U                           /*!<PB[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PC              0x0002U                           /*!<PC[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PD              0x0003U                           /*!<PD[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PE              0x0004U                           /*!<PE[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PF              0x0005U                           /*!<PF[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PG              0x0006U                           /*!<PG[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PH              0x0007U                           /*!<PH[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PI              0x0008U                           /*!<PI[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PJ              0x0009U                           /*!<PJ[8] pin */
+
+/**
+  * @brief   EXTI9 configuration  
+  */
+#define SYSCFG_EXTICR3_EXTI9_PA              0x0000U                           /*!<PA[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PB              0x0010U                           /*!<PB[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PC              0x0020U                           /*!<PC[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PD              0x0030U                           /*!<PD[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PE              0x0040U                           /*!<PE[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PF              0x0050U                           /*!<PF[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PG              0x0060U                           /*!<PG[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PH              0x0070U                           /*!<PH[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PI              0x0080U                           /*!<PI[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PJ              0x0090U                           /*!<PJ[9] pin */
+
+/**
+  * @brief   EXTI10 configuration  
+  */
+#define SYSCFG_EXTICR3_EXTI10_PA             0x0000U                           /*!<PA[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PB             0x0100U                           /*!<PB[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PC             0x0200U                           /*!<PC[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PD             0x0300U                           /*!<PD[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PE             0x0400U                           /*!<PE[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PF             0x0500U                           /*!<PF[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PG             0x0600U                           /*!<PG[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PH             0x0700U                           /*!<PH[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PI             0x0800U                           /*!<PI[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PJ             0x0900U                           /*!<PJ[10] pin */
+
+/**
+  * @brief   EXTI11 configuration  
+  */
+#define SYSCFG_EXTICR3_EXTI11_PA             0x0000U                           /*!<PA[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PB             0x1000U                           /*!<PB[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PC             0x2000U                           /*!<PC[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PD             0x3000U                           /*!<PD[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PE             0x4000U                           /*!<PE[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PF             0x5000U                           /*!<PF[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PG             0x6000U                           /*!<PG[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PH             0x7000U                           /*!<PH[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PI             0x8000U                           /*!<PI[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PJ             0x9000U                           /*!<PJ[11] pin */
+
+
+/*****************  Bit definition for SYSCFG_EXTICR4 register  ***************/
+#define SYSCFG_EXTICR4_EXTI12_Pos            (0U)                              
+#define SYSCFG_EXTICR4_EXTI12_Msk            (0xFUL << SYSCFG_EXTICR4_EXTI12_Pos) /*!< 0x0000000F */
+#define SYSCFG_EXTICR4_EXTI12                SYSCFG_EXTICR4_EXTI12_Msk         /*!<EXTI 12 configuration */
+#define SYSCFG_EXTICR4_EXTI13_Pos            (4U)                              
+#define SYSCFG_EXTICR4_EXTI13_Msk            (0xFUL << SYSCFG_EXTICR4_EXTI13_Pos) /*!< 0x000000F0 */
+#define SYSCFG_EXTICR4_EXTI13                SYSCFG_EXTICR4_EXTI13_Msk         /*!<EXTI 13 configuration */
+#define SYSCFG_EXTICR4_EXTI14_Pos            (8U)                              
+#define SYSCFG_EXTICR4_EXTI14_Msk            (0xFUL << SYSCFG_EXTICR4_EXTI14_Pos) /*!< 0x00000F00 */
+#define SYSCFG_EXTICR4_EXTI14                SYSCFG_EXTICR4_EXTI14_Msk         /*!<EXTI 14 configuration */
+#define SYSCFG_EXTICR4_EXTI15_Pos            (12U)                             
+#define SYSCFG_EXTICR4_EXTI15_Msk            (0xFUL << SYSCFG_EXTICR4_EXTI15_Pos) /*!< 0x0000F000 */
+#define SYSCFG_EXTICR4_EXTI15                SYSCFG_EXTICR4_EXTI15_Msk         /*!<EXTI 15 configuration */
+
+/**
+  * @brief   EXTI12 configuration  
+  */
+#define SYSCFG_EXTICR4_EXTI12_PA             0x0000U                           /*!<PA[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PB             0x0001U                           /*!<PB[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PC             0x0002U                           /*!<PC[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PD             0x0003U                           /*!<PD[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PE             0x0004U                           /*!<PE[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PF             0x0005U                           /*!<PF[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PG             0x0006U                           /*!<PG[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PH             0x0007U                           /*!<PH[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PI             0x0008U                           /*!<PI[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PJ             0x0009U                           /*!<PJ[12] pin */
+
+/**
+  * @brief   EXTI13 configuration  
+  */
+#define SYSCFG_EXTICR4_EXTI13_PA             0x0000U                           /*!<PA[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PB             0x0010U                           /*!<PB[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PC             0x0020U                           /*!<PC[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PD             0x0030U                           /*!<PD[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PE             0x0040U                           /*!<PE[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PF             0x0050U                           /*!<PF[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PG             0x0060U                           /*!<PG[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PH             0x0070U                           /*!<PH[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PI             0x0008U                           /*!<PI[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PJ             0x0009U                           /*!<PJ[13] pin */
+
+/**
+  * @brief   EXTI14 configuration  
+  */
+#define SYSCFG_EXTICR4_EXTI14_PA             0x0000U                           /*!<PA[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PB             0x0100U                           /*!<PB[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PC             0x0200U                           /*!<PC[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PD             0x0300U                           /*!<PD[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PE             0x0400U                           /*!<PE[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PF             0x0500U                           /*!<PF[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PG             0x0600U                           /*!<PG[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PH             0x0700U                           /*!<PH[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PI             0x0800U                           /*!<PI[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PJ             0x0900U                           /*!<PJ[14] pin */
+
+/**
+  * @brief   EXTI15 configuration  
+  */
+#define SYSCFG_EXTICR4_EXTI15_PA             0x0000U                           /*!<PA[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PB             0x1000U                           /*!<PB[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PC             0x2000U                           /*!<PC[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PD             0x3000U                           /*!<PD[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PE             0x4000U                           /*!<PE[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PF             0x5000U                           /*!<PF[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PG             0x6000U                           /*!<PG[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PH             0x7000U                           /*!<PH[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PI             0x8000U                           /*!<PI[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PJ             0x9000U                           /*!<PJ[15] pin */
+
+/******************  Bit definition for SYSCFG_CMPCR register  ****************/
+#define SYSCFG_CMPCR_CMP_PD_Pos              (0U)                              
+#define SYSCFG_CMPCR_CMP_PD_Msk              (0x1UL << SYSCFG_CMPCR_CMP_PD_Pos) /*!< 0x00000001 */
+#define SYSCFG_CMPCR_CMP_PD                  SYSCFG_CMPCR_CMP_PD_Msk           /*!<Compensation cell ready flag */
+#define SYSCFG_CMPCR_READY_Pos               (8U)                              
+#define SYSCFG_CMPCR_READY_Msk               (0x1UL << SYSCFG_CMPCR_READY_Pos)  /*!< 0x00000100 */
+#define SYSCFG_CMPCR_READY                   SYSCFG_CMPCR_READY_Msk            /*!<Compensation cell power-down */
+
+/******************************************************************************/
+/*                                                                            */
+/*                                    TIM                                     */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for TIM_CR1 register  ********************/
+#define TIM_CR1_CEN_Pos           (0U)                                         
+#define TIM_CR1_CEN_Msk           (0x1UL << TIM_CR1_CEN_Pos)                    /*!< 0x00000001 */
+#define TIM_CR1_CEN               TIM_CR1_CEN_Msk                              /*!<Counter enable        */
+#define TIM_CR1_UDIS_Pos          (1U)                                         
+#define TIM_CR1_UDIS_Msk          (0x1UL << TIM_CR1_UDIS_Pos)                   /*!< 0x00000002 */
+#define TIM_CR1_UDIS              TIM_CR1_UDIS_Msk                             /*!<Update disable        */
+#define TIM_CR1_URS_Pos           (2U)                                         
+#define TIM_CR1_URS_Msk           (0x1UL << TIM_CR1_URS_Pos)                    /*!< 0x00000004 */
+#define TIM_CR1_URS               TIM_CR1_URS_Msk                              /*!<Update request source */
+#define TIM_CR1_OPM_Pos           (3U)                                         
+#define TIM_CR1_OPM_Msk           (0x1UL << TIM_CR1_OPM_Pos)                    /*!< 0x00000008 */
+#define TIM_CR1_OPM               TIM_CR1_OPM_Msk                              /*!<One pulse mode        */
+#define TIM_CR1_DIR_Pos           (4U)                                         
+#define TIM_CR1_DIR_Msk           (0x1UL << TIM_CR1_DIR_Pos)                    /*!< 0x00000010 */
+#define TIM_CR1_DIR               TIM_CR1_DIR_Msk                              /*!<Direction             */
+
+#define TIM_CR1_CMS_Pos           (5U)                                         
+#define TIM_CR1_CMS_Msk           (0x3UL << TIM_CR1_CMS_Pos)                    /*!< 0x00000060 */
+#define TIM_CR1_CMS               TIM_CR1_CMS_Msk                              /*!<CMS[1:0] bits (Center-aligned mode selection) */
+#define TIM_CR1_CMS_0             (0x1UL << TIM_CR1_CMS_Pos)                    /*!< 0x0020 */
+#define TIM_CR1_CMS_1             (0x2UL << TIM_CR1_CMS_Pos)                    /*!< 0x0040 */
+
+#define TIM_CR1_ARPE_Pos          (7U)                                         
+#define TIM_CR1_ARPE_Msk          (0x1UL << TIM_CR1_ARPE_Pos)                   /*!< 0x00000080 */
+#define TIM_CR1_ARPE              TIM_CR1_ARPE_Msk                             /*!<Auto-reload preload enable     */
+
+#define TIM_CR1_CKD_Pos           (8U)                                         
+#define TIM_CR1_CKD_Msk           (0x3UL << TIM_CR1_CKD_Pos)                    /*!< 0x00000300 */
+#define TIM_CR1_CKD               TIM_CR1_CKD_Msk                              /*!<CKD[1:0] bits (clock division) */
+#define TIM_CR1_CKD_0             (0x1UL << TIM_CR1_CKD_Pos)                    /*!< 0x0100 */
+#define TIM_CR1_CKD_1             (0x2UL << TIM_CR1_CKD_Pos)                    /*!< 0x0200 */
+
+/*******************  Bit definition for TIM_CR2 register  ********************/
+#define TIM_CR2_CCPC_Pos          (0U)                                         
+#define TIM_CR2_CCPC_Msk          (0x1UL << TIM_CR2_CCPC_Pos)                   /*!< 0x00000001 */
+#define TIM_CR2_CCPC              TIM_CR2_CCPC_Msk                             /*!<Capture/Compare Preloaded Control        */
+#define TIM_CR2_CCUS_Pos          (2U)                                         
+#define TIM_CR2_CCUS_Msk          (0x1UL << TIM_CR2_CCUS_Pos)                   /*!< 0x00000004 */
+#define TIM_CR2_CCUS              TIM_CR2_CCUS_Msk                             /*!<Capture/Compare Control Update Selection */
+#define TIM_CR2_CCDS_Pos          (3U)                                         
+#define TIM_CR2_CCDS_Msk          (0x1UL << TIM_CR2_CCDS_Pos)                   /*!< 0x00000008 */
+#define TIM_CR2_CCDS              TIM_CR2_CCDS_Msk                             /*!<Capture/Compare DMA Selection            */
+
+#define TIM_CR2_MMS_Pos           (4U)                                         
+#define TIM_CR2_MMS_Msk           (0x7UL << TIM_CR2_MMS_Pos)                    /*!< 0x00000070 */
+#define TIM_CR2_MMS               TIM_CR2_MMS_Msk                              /*!<MMS[2:0] bits (Master Mode Selection) */
+#define TIM_CR2_MMS_0             (0x1UL << TIM_CR2_MMS_Pos)                    /*!< 0x0010 */
+#define TIM_CR2_MMS_1             (0x2UL << TIM_CR2_MMS_Pos)                    /*!< 0x0020 */
+#define TIM_CR2_MMS_2             (0x4UL << TIM_CR2_MMS_Pos)                    /*!< 0x0040 */
+
+#define TIM_CR2_TI1S_Pos          (7U)                                         
+#define TIM_CR2_TI1S_Msk          (0x1UL << TIM_CR2_TI1S_Pos)                   /*!< 0x00000080 */
+#define TIM_CR2_TI1S              TIM_CR2_TI1S_Msk                             /*!<TI1 Selection */
+#define TIM_CR2_OIS1_Pos          (8U)                                         
+#define TIM_CR2_OIS1_Msk          (0x1UL << TIM_CR2_OIS1_Pos)                   /*!< 0x00000100 */
+#define TIM_CR2_OIS1              TIM_CR2_OIS1_Msk                             /*!<Output Idle state 1 (OC1 output)  */
+#define TIM_CR2_OIS1N_Pos         (9U)                                         
+#define TIM_CR2_OIS1N_Msk         (0x1UL << TIM_CR2_OIS1N_Pos)                  /*!< 0x00000200 */
+#define TIM_CR2_OIS1N             TIM_CR2_OIS1N_Msk                            /*!<Output Idle state 1 (OC1N output) */
+#define TIM_CR2_OIS2_Pos          (10U)                                        
+#define TIM_CR2_OIS2_Msk          (0x1UL << TIM_CR2_OIS2_Pos)                   /*!< 0x00000400 */
+#define TIM_CR2_OIS2              TIM_CR2_OIS2_Msk                             /*!<Output Idle state 2 (OC2 output)  */
+#define TIM_CR2_OIS2N_Pos         (11U)                                        
+#define TIM_CR2_OIS2N_Msk         (0x1UL << TIM_CR2_OIS2N_Pos)                  /*!< 0x00000800 */
+#define TIM_CR2_OIS2N             TIM_CR2_OIS2N_Msk                            /*!<Output Idle state 2 (OC2N output) */
+#define TIM_CR2_OIS3_Pos          (12U)                                        
+#define TIM_CR2_OIS3_Msk          (0x1UL << TIM_CR2_OIS3_Pos)                   /*!< 0x00001000 */
+#define TIM_CR2_OIS3              TIM_CR2_OIS3_Msk                             /*!<Output Idle state 3 (OC3 output)  */
+#define TIM_CR2_OIS3N_Pos         (13U)                                        
+#define TIM_CR2_OIS3N_Msk         (0x1UL << TIM_CR2_OIS3N_Pos)                  /*!< 0x00002000 */
+#define TIM_CR2_OIS3N             TIM_CR2_OIS3N_Msk                            /*!<Output Idle state 3 (OC3N output) */
+#define TIM_CR2_OIS4_Pos          (14U)                                        
+#define TIM_CR2_OIS4_Msk          (0x1UL << TIM_CR2_OIS4_Pos)                   /*!< 0x00004000 */
+#define TIM_CR2_OIS4              TIM_CR2_OIS4_Msk                             /*!<Output Idle state 4 (OC4 output)  */
+
+/*******************  Bit definition for TIM_SMCR register  *******************/
+#define TIM_SMCR_SMS_Pos          (0U)                                         
+#define TIM_SMCR_SMS_Msk          (0x7UL << TIM_SMCR_SMS_Pos)                   /*!< 0x00000007 */
+#define TIM_SMCR_SMS              TIM_SMCR_SMS_Msk                             /*!<SMS[2:0] bits (Slave mode selection)    */
+#define TIM_SMCR_SMS_0            (0x1UL << TIM_SMCR_SMS_Pos)                   /*!< 0x0001 */
+#define TIM_SMCR_SMS_1            (0x2UL << TIM_SMCR_SMS_Pos)                   /*!< 0x0002 */
+#define TIM_SMCR_SMS_2            (0x4UL << TIM_SMCR_SMS_Pos)                   /*!< 0x0004 */
+
+#define TIM_SMCR_TS_Pos           (4U)                                         
+#define TIM_SMCR_TS_Msk           (0x7UL << TIM_SMCR_TS_Pos)                    /*!< 0x00000070 */
+#define TIM_SMCR_TS               TIM_SMCR_TS_Msk                              /*!<TS[2:0] bits (Trigger selection)        */
+#define TIM_SMCR_TS_0             (0x1UL << TIM_SMCR_TS_Pos)                    /*!< 0x0010 */
+#define TIM_SMCR_TS_1             (0x2UL << TIM_SMCR_TS_Pos)                    /*!< 0x0020 */
+#define TIM_SMCR_TS_2             (0x4UL << TIM_SMCR_TS_Pos)                    /*!< 0x0040 */
+
+#define TIM_SMCR_MSM_Pos          (7U)                                         
+#define TIM_SMCR_MSM_Msk          (0x1UL << TIM_SMCR_MSM_Pos)                   /*!< 0x00000080 */
+#define TIM_SMCR_MSM              TIM_SMCR_MSM_Msk                             /*!<Master/slave mode                       */
+
+#define TIM_SMCR_ETF_Pos          (8U)                                         
+#define TIM_SMCR_ETF_Msk          (0xFUL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000F00 */
+#define TIM_SMCR_ETF              TIM_SMCR_ETF_Msk                             /*!<ETF[3:0] bits (External trigger filter) */
+#define TIM_SMCR_ETF_0            (0x1UL << TIM_SMCR_ETF_Pos)                   /*!< 0x0100 */
+#define TIM_SMCR_ETF_1            (0x2UL << TIM_SMCR_ETF_Pos)                   /*!< 0x0200 */
+#define TIM_SMCR_ETF_2            (0x4UL << TIM_SMCR_ETF_Pos)                   /*!< 0x0400 */
+#define TIM_SMCR_ETF_3            (0x8UL << TIM_SMCR_ETF_Pos)                   /*!< 0x0800 */
+
+#define TIM_SMCR_ETPS_Pos         (12U)                                        
+#define TIM_SMCR_ETPS_Msk         (0x3UL << TIM_SMCR_ETPS_Pos)                  /*!< 0x00003000 */
+#define TIM_SMCR_ETPS             TIM_SMCR_ETPS_Msk                            /*!<ETPS[1:0] bits (External trigger prescaler) */
+#define TIM_SMCR_ETPS_0           (0x1UL << TIM_SMCR_ETPS_Pos)                  /*!< 0x1000 */
+#define TIM_SMCR_ETPS_1           (0x2UL << TIM_SMCR_ETPS_Pos)                  /*!< 0x2000 */
+
+#define TIM_SMCR_ECE_Pos          (14U)                                        
+#define TIM_SMCR_ECE_Msk          (0x1UL << TIM_SMCR_ECE_Pos)                   /*!< 0x00004000 */
+#define TIM_SMCR_ECE              TIM_SMCR_ECE_Msk                             /*!<External clock enable     */
+#define TIM_SMCR_ETP_Pos          (15U)                                        
+#define TIM_SMCR_ETP_Msk          (0x1UL << TIM_SMCR_ETP_Pos)                   /*!< 0x00008000 */
+#define TIM_SMCR_ETP              TIM_SMCR_ETP_Msk                             /*!<External trigger polarity */
+
+/*******************  Bit definition for TIM_DIER register  *******************/
+#define TIM_DIER_UIE_Pos          (0U)                                         
+#define TIM_DIER_UIE_Msk          (0x1UL << TIM_DIER_UIE_Pos)                   /*!< 0x00000001 */
+#define TIM_DIER_UIE              TIM_DIER_UIE_Msk                             /*!<Update interrupt enable */
+#define TIM_DIER_CC1IE_Pos        (1U)                                         
+#define TIM_DIER_CC1IE_Msk        (0x1UL << TIM_DIER_CC1IE_Pos)                 /*!< 0x00000002 */
+#define TIM_DIER_CC1IE            TIM_DIER_CC1IE_Msk                           /*!<Capture/Compare 1 interrupt enable   */
+#define TIM_DIER_CC2IE_Pos        (2U)                                         
+#define TIM_DIER_CC2IE_Msk        (0x1UL << TIM_DIER_CC2IE_Pos)                 /*!< 0x00000004 */
+#define TIM_DIER_CC2IE            TIM_DIER_CC2IE_Msk                           /*!<Capture/Compare 2 interrupt enable   */
+#define TIM_DIER_CC3IE_Pos        (3U)                                         
+#define TIM_DIER_CC3IE_Msk        (0x1UL << TIM_DIER_CC3IE_Pos)                 /*!< 0x00000008 */
+#define TIM_DIER_CC3IE            TIM_DIER_CC3IE_Msk                           /*!<Capture/Compare 3 interrupt enable   */
+#define TIM_DIER_CC4IE_Pos        (4U)                                         
+#define TIM_DIER_CC4IE_Msk        (0x1UL << TIM_DIER_CC4IE_Pos)                 /*!< 0x00000010 */
+#define TIM_DIER_CC4IE            TIM_DIER_CC4IE_Msk                           /*!<Capture/Compare 4 interrupt enable   */
+#define TIM_DIER_COMIE_Pos        (5U)                                         
+#define TIM_DIER_COMIE_Msk        (0x1UL << TIM_DIER_COMIE_Pos)                 /*!< 0x00000020 */
+#define TIM_DIER_COMIE            TIM_DIER_COMIE_Msk                           /*!<COM interrupt enable                 */
+#define TIM_DIER_TIE_Pos          (6U)                                         
+#define TIM_DIER_TIE_Msk          (0x1UL << TIM_DIER_TIE_Pos)                   /*!< 0x00000040 */
+#define TIM_DIER_TIE              TIM_DIER_TIE_Msk                             /*!<Trigger interrupt enable             */
+#define TIM_DIER_BIE_Pos          (7U)                                         
+#define TIM_DIER_BIE_Msk          (0x1UL << TIM_DIER_BIE_Pos)                   /*!< 0x00000080 */
+#define TIM_DIER_BIE              TIM_DIER_BIE_Msk                             /*!<Break interrupt enable               */
+#define TIM_DIER_UDE_Pos          (8U)                                         
+#define TIM_DIER_UDE_Msk          (0x1UL << TIM_DIER_UDE_Pos)                   /*!< 0x00000100 */
+#define TIM_DIER_UDE              TIM_DIER_UDE_Msk                             /*!<Update DMA request enable            */
+#define TIM_DIER_CC1DE_Pos        (9U)                                         
+#define TIM_DIER_CC1DE_Msk        (0x1UL << TIM_DIER_CC1DE_Pos)                 /*!< 0x00000200 */
+#define TIM_DIER_CC1DE            TIM_DIER_CC1DE_Msk                           /*!<Capture/Compare 1 DMA request enable */
+#define TIM_DIER_CC2DE_Pos        (10U)                                        
+#define TIM_DIER_CC2DE_Msk        (0x1UL << TIM_DIER_CC2DE_Pos)                 /*!< 0x00000400 */
+#define TIM_DIER_CC2DE            TIM_DIER_CC2DE_Msk                           /*!<Capture/Compare 2 DMA request enable */
+#define TIM_DIER_CC3DE_Pos        (11U)                                        
+#define TIM_DIER_CC3DE_Msk        (0x1UL << TIM_DIER_CC3DE_Pos)                 /*!< 0x00000800 */
+#define TIM_DIER_CC3DE            TIM_DIER_CC3DE_Msk                           /*!<Capture/Compare 3 DMA request enable */
+#define TIM_DIER_CC4DE_Pos        (12U)                                        
+#define TIM_DIER_CC4DE_Msk        (0x1UL << TIM_DIER_CC4DE_Pos)                 /*!< 0x00001000 */
+#define TIM_DIER_CC4DE            TIM_DIER_CC4DE_Msk                           /*!<Capture/Compare 4 DMA request enable */
+#define TIM_DIER_COMDE_Pos        (13U)                                        
+#define TIM_DIER_COMDE_Msk        (0x1UL << TIM_DIER_COMDE_Pos)                 /*!< 0x00002000 */
+#define TIM_DIER_COMDE            TIM_DIER_COMDE_Msk                           /*!<COM DMA request enable               */
+#define TIM_DIER_TDE_Pos          (14U)                                        
+#define TIM_DIER_TDE_Msk          (0x1UL << TIM_DIER_TDE_Pos)                   /*!< 0x00004000 */
+#define TIM_DIER_TDE              TIM_DIER_TDE_Msk                             /*!<Trigger DMA request enable           */
+
+/********************  Bit definition for TIM_SR register  ********************/
+#define TIM_SR_UIF_Pos            (0U)                                         
+#define TIM_SR_UIF_Msk            (0x1UL << TIM_SR_UIF_Pos)                     /*!< 0x00000001 */
+#define TIM_SR_UIF                TIM_SR_UIF_Msk                               /*!<Update interrupt Flag              */
+#define TIM_SR_CC1IF_Pos          (1U)                                         
+#define TIM_SR_CC1IF_Msk          (0x1UL << TIM_SR_CC1IF_Pos)                   /*!< 0x00000002 */
+#define TIM_SR_CC1IF              TIM_SR_CC1IF_Msk                             /*!<Capture/Compare 1 interrupt Flag   */
+#define TIM_SR_CC2IF_Pos          (2U)                                         
+#define TIM_SR_CC2IF_Msk          (0x1UL << TIM_SR_CC2IF_Pos)                   /*!< 0x00000004 */
+#define TIM_SR_CC2IF              TIM_SR_CC2IF_Msk                             /*!<Capture/Compare 2 interrupt Flag   */
+#define TIM_SR_CC3IF_Pos          (3U)                                         
+#define TIM_SR_CC3IF_Msk          (0x1UL << TIM_SR_CC3IF_Pos)                   /*!< 0x00000008 */
+#define TIM_SR_CC3IF              TIM_SR_CC3IF_Msk                             /*!<Capture/Compare 3 interrupt Flag   */
+#define TIM_SR_CC4IF_Pos          (4U)                                         
+#define TIM_SR_CC4IF_Msk          (0x1UL << TIM_SR_CC4IF_Pos)                   /*!< 0x00000010 */
+#define TIM_SR_CC4IF              TIM_SR_CC4IF_Msk                             /*!<Capture/Compare 4 interrupt Flag   */
+#define TIM_SR_COMIF_Pos          (5U)                                         
+#define TIM_SR_COMIF_Msk          (0x1UL << TIM_SR_COMIF_Pos)                   /*!< 0x00000020 */
+#define TIM_SR_COMIF              TIM_SR_COMIF_Msk                             /*!<COM interrupt Flag                 */
+#define TIM_SR_TIF_Pos            (6U)                                         
+#define TIM_SR_TIF_Msk            (0x1UL << TIM_SR_TIF_Pos)                     /*!< 0x00000040 */
+#define TIM_SR_TIF                TIM_SR_TIF_Msk                               /*!<Trigger interrupt Flag             */
+#define TIM_SR_BIF_Pos            (7U)                                         
+#define TIM_SR_BIF_Msk            (0x1UL << TIM_SR_BIF_Pos)                     /*!< 0x00000080 */
+#define TIM_SR_BIF                TIM_SR_BIF_Msk                               /*!<Break interrupt Flag               */
+#define TIM_SR_CC1OF_Pos          (9U)                                         
+#define TIM_SR_CC1OF_Msk          (0x1UL << TIM_SR_CC1OF_Pos)                   /*!< 0x00000200 */
+#define TIM_SR_CC1OF              TIM_SR_CC1OF_Msk                             /*!<Capture/Compare 1 Overcapture Flag */
+#define TIM_SR_CC2OF_Pos          (10U)                                        
+#define TIM_SR_CC2OF_Msk          (0x1UL << TIM_SR_CC2OF_Pos)                   /*!< 0x00000400 */
+#define TIM_SR_CC2OF              TIM_SR_CC2OF_Msk                             /*!<Capture/Compare 2 Overcapture Flag */
+#define TIM_SR_CC3OF_Pos          (11U)                                        
+#define TIM_SR_CC3OF_Msk          (0x1UL << TIM_SR_CC3OF_Pos)                   /*!< 0x00000800 */
+#define TIM_SR_CC3OF              TIM_SR_CC3OF_Msk                             /*!<Capture/Compare 3 Overcapture Flag */
+#define TIM_SR_CC4OF_Pos          (12U)                                        
+#define TIM_SR_CC4OF_Msk          (0x1UL << TIM_SR_CC4OF_Pos)                   /*!< 0x00001000 */
+#define TIM_SR_CC4OF              TIM_SR_CC4OF_Msk                             /*!<Capture/Compare 4 Overcapture Flag */
+
+/*******************  Bit definition for TIM_EGR register  ********************/
+#define TIM_EGR_UG_Pos            (0U)                                         
+#define TIM_EGR_UG_Msk            (0x1UL << TIM_EGR_UG_Pos)                     /*!< 0x00000001 */
+#define TIM_EGR_UG                TIM_EGR_UG_Msk                               /*!<Update Generation                         */
+#define TIM_EGR_CC1G_Pos          (1U)                                         
+#define TIM_EGR_CC1G_Msk          (0x1UL << TIM_EGR_CC1G_Pos)                   /*!< 0x00000002 */
+#define TIM_EGR_CC1G              TIM_EGR_CC1G_Msk                             /*!<Capture/Compare 1 Generation              */
+#define TIM_EGR_CC2G_Pos          (2U)                                         
+#define TIM_EGR_CC2G_Msk          (0x1UL << TIM_EGR_CC2G_Pos)                   /*!< 0x00000004 */
+#define TIM_EGR_CC2G              TIM_EGR_CC2G_Msk                             /*!<Capture/Compare 2 Generation              */
+#define TIM_EGR_CC3G_Pos          (3U)                                         
+#define TIM_EGR_CC3G_Msk          (0x1UL << TIM_EGR_CC3G_Pos)                   /*!< 0x00000008 */
+#define TIM_EGR_CC3G              TIM_EGR_CC3G_Msk                             /*!<Capture/Compare 3 Generation              */
+#define TIM_EGR_CC4G_Pos          (4U)                                         
+#define TIM_EGR_CC4G_Msk          (0x1UL << TIM_EGR_CC4G_Pos)                   /*!< 0x00000010 */
+#define TIM_EGR_CC4G              TIM_EGR_CC4G_Msk                             /*!<Capture/Compare 4 Generation              */
+#define TIM_EGR_COMG_Pos          (5U)                                         
+#define TIM_EGR_COMG_Msk          (0x1UL << TIM_EGR_COMG_Pos)                   /*!< 0x00000020 */
+#define TIM_EGR_COMG              TIM_EGR_COMG_Msk                             /*!<Capture/Compare Control Update Generation */
+#define TIM_EGR_TG_Pos            (6U)                                         
+#define TIM_EGR_TG_Msk            (0x1UL << TIM_EGR_TG_Pos)                     /*!< 0x00000040 */
+#define TIM_EGR_TG                TIM_EGR_TG_Msk                               /*!<Trigger Generation                        */
+#define TIM_EGR_BG_Pos            (7U)                                         
+#define TIM_EGR_BG_Msk            (0x1UL << TIM_EGR_BG_Pos)                     /*!< 0x00000080 */
+#define TIM_EGR_BG                TIM_EGR_BG_Msk                               /*!<Break Generation                          */
+
+/******************  Bit definition for TIM_CCMR1 register  *******************/
+#define TIM_CCMR1_CC1S_Pos        (0U)                                         
+#define TIM_CCMR1_CC1S_Msk        (0x3UL << TIM_CCMR1_CC1S_Pos)                 /*!< 0x00000003 */
+#define TIM_CCMR1_CC1S            TIM_CCMR1_CC1S_Msk                           /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
+#define TIM_CCMR1_CC1S_0          (0x1UL << TIM_CCMR1_CC1S_Pos)                 /*!< 0x0001 */
+#define TIM_CCMR1_CC1S_1          (0x2UL << TIM_CCMR1_CC1S_Pos)                 /*!< 0x0002 */
+
+#define TIM_CCMR1_OC1FE_Pos       (2U)                                         
+#define TIM_CCMR1_OC1FE_Msk       (0x1UL << TIM_CCMR1_OC1FE_Pos)                /*!< 0x00000004 */
+#define TIM_CCMR1_OC1FE           TIM_CCMR1_OC1FE_Msk                          /*!<Output Compare 1 Fast enable                 */
+#define TIM_CCMR1_OC1PE_Pos       (3U)                                         
+#define TIM_CCMR1_OC1PE_Msk       (0x1UL << TIM_CCMR1_OC1PE_Pos)                /*!< 0x00000008 */
+#define TIM_CCMR1_OC1PE           TIM_CCMR1_OC1PE_Msk                          /*!<Output Compare 1 Preload enable              */
+
+#define TIM_CCMR1_OC1M_Pos        (4U)                                         
+#define TIM_CCMR1_OC1M_Msk        (0x7UL << TIM_CCMR1_OC1M_Pos)                 /*!< 0x00000070 */
+#define TIM_CCMR1_OC1M            TIM_CCMR1_OC1M_Msk                           /*!<OC1M[2:0] bits (Output Compare 1 Mode)       */
+#define TIM_CCMR1_OC1M_0          (0x1UL << TIM_CCMR1_OC1M_Pos)                 /*!< 0x0010 */
+#define TIM_CCMR1_OC1M_1          (0x2UL << TIM_CCMR1_OC1M_Pos)                 /*!< 0x0020 */
+#define TIM_CCMR1_OC1M_2          (0x4UL << TIM_CCMR1_OC1M_Pos)                 /*!< 0x0040 */
+
+#define TIM_CCMR1_OC1CE_Pos       (7U)                                         
+#define TIM_CCMR1_OC1CE_Msk       (0x1UL << TIM_CCMR1_OC1CE_Pos)                /*!< 0x00000080 */
+#define TIM_CCMR1_OC1CE           TIM_CCMR1_OC1CE_Msk                          /*!<Output Compare 1Clear Enable                 */
+
+#define TIM_CCMR1_CC2S_Pos        (8U)                                         
+#define TIM_CCMR1_CC2S_Msk        (0x3UL << TIM_CCMR1_CC2S_Pos)                 /*!< 0x00000300 */
+#define TIM_CCMR1_CC2S            TIM_CCMR1_CC2S_Msk                           /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
+#define TIM_CCMR1_CC2S_0          (0x1UL << TIM_CCMR1_CC2S_Pos)                 /*!< 0x0100 */
+#define TIM_CCMR1_CC2S_1          (0x2UL << TIM_CCMR1_CC2S_Pos)                 /*!< 0x0200 */
+
+#define TIM_CCMR1_OC2FE_Pos       (10U)                                        
+#define TIM_CCMR1_OC2FE_Msk       (0x1UL << TIM_CCMR1_OC2FE_Pos)                /*!< 0x00000400 */
+#define TIM_CCMR1_OC2FE           TIM_CCMR1_OC2FE_Msk                          /*!<Output Compare 2 Fast enable                 */
+#define TIM_CCMR1_OC2PE_Pos       (11U)                                        
+#define TIM_CCMR1_OC2PE_Msk       (0x1UL << TIM_CCMR1_OC2PE_Pos)                /*!< 0x00000800 */
+#define TIM_CCMR1_OC2PE           TIM_CCMR1_OC2PE_Msk                          /*!<Output Compare 2 Preload enable              */
+
+#define TIM_CCMR1_OC2M_Pos        (12U)                                        
+#define TIM_CCMR1_OC2M_Msk        (0x7UL << TIM_CCMR1_OC2M_Pos)                 /*!< 0x00007000 */
+#define TIM_CCMR1_OC2M            TIM_CCMR1_OC2M_Msk                           /*!<OC2M[2:0] bits (Output Compare 2 Mode)       */
+#define TIM_CCMR1_OC2M_0          (0x1UL << TIM_CCMR1_OC2M_Pos)                 /*!< 0x1000 */
+#define TIM_CCMR1_OC2M_1          (0x2UL << TIM_CCMR1_OC2M_Pos)                 /*!< 0x2000 */
+#define TIM_CCMR1_OC2M_2          (0x4UL << TIM_CCMR1_OC2M_Pos)                 /*!< 0x4000 */
+
+#define TIM_CCMR1_OC2CE_Pos       (15U)                                        
+#define TIM_CCMR1_OC2CE_Msk       (0x1UL << TIM_CCMR1_OC2CE_Pos)                /*!< 0x00008000 */
+#define TIM_CCMR1_OC2CE           TIM_CCMR1_OC2CE_Msk                          /*!<Output Compare 2 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define TIM_CCMR1_IC1PSC_Pos      (2U)                                         
+#define TIM_CCMR1_IC1PSC_Msk      (0x3UL << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x0000000C */
+#define TIM_CCMR1_IC1PSC          TIM_CCMR1_IC1PSC_Msk                         /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
+#define TIM_CCMR1_IC1PSC_0        (0x1UL << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x0004 */
+#define TIM_CCMR1_IC1PSC_1        (0x2UL << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x0008 */
+
+#define TIM_CCMR1_IC1F_Pos        (4U)                                         
+#define TIM_CCMR1_IC1F_Msk        (0xFUL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x000000F0 */
+#define TIM_CCMR1_IC1F            TIM_CCMR1_IC1F_Msk                           /*!<IC1F[3:0] bits (Input Capture 1 Filter)      */
+#define TIM_CCMR1_IC1F_0          (0x1UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x0010 */
+#define TIM_CCMR1_IC1F_1          (0x2UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x0020 */
+#define TIM_CCMR1_IC1F_2          (0x4UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x0040 */
+#define TIM_CCMR1_IC1F_3          (0x8UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x0080 */
+
+#define TIM_CCMR1_IC2PSC_Pos      (10U)                                        
+#define TIM_CCMR1_IC2PSC_Msk      (0x3UL << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x00000C00 */
+#define TIM_CCMR1_IC2PSC          TIM_CCMR1_IC2PSC_Msk                         /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler)  */
+#define TIM_CCMR1_IC2PSC_0        (0x1UL << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x0400 */
+#define TIM_CCMR1_IC2PSC_1        (0x2UL << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x0800 */
+
+#define TIM_CCMR1_IC2F_Pos        (12U)                                        
+#define TIM_CCMR1_IC2F_Msk        (0xFUL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x0000F000 */
+#define TIM_CCMR1_IC2F            TIM_CCMR1_IC2F_Msk                           /*!<IC2F[3:0] bits (Input Capture 2 Filter)       */
+#define TIM_CCMR1_IC2F_0          (0x1UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x1000 */
+#define TIM_CCMR1_IC2F_1          (0x2UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x2000 */
+#define TIM_CCMR1_IC2F_2          (0x4UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x4000 */
+#define TIM_CCMR1_IC2F_3          (0x8UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x8000 */
+
+/******************  Bit definition for TIM_CCMR2 register  *******************/
+#define TIM_CCMR2_CC3S_Pos        (0U)                                         
+#define TIM_CCMR2_CC3S_Msk        (0x3UL << TIM_CCMR2_CC3S_Pos)                 /*!< 0x00000003 */
+#define TIM_CCMR2_CC3S            TIM_CCMR2_CC3S_Msk                           /*!<CC3S[1:0] bits (Capture/Compare 3 Selection)  */
+#define TIM_CCMR2_CC3S_0          (0x1UL << TIM_CCMR2_CC3S_Pos)                 /*!< 0x0001 */
+#define TIM_CCMR2_CC3S_1          (0x2UL << TIM_CCMR2_CC3S_Pos)                 /*!< 0x0002 */
+
+#define TIM_CCMR2_OC3FE_Pos       (2U)                                         
+#define TIM_CCMR2_OC3FE_Msk       (0x1UL << TIM_CCMR2_OC3FE_Pos)                /*!< 0x00000004 */
+#define TIM_CCMR2_OC3FE           TIM_CCMR2_OC3FE_Msk                          /*!<Output Compare 3 Fast enable           */
+#define TIM_CCMR2_OC3PE_Pos       (3U)                                         
+#define TIM_CCMR2_OC3PE_Msk       (0x1UL << TIM_CCMR2_OC3PE_Pos)                /*!< 0x00000008 */
+#define TIM_CCMR2_OC3PE           TIM_CCMR2_OC3PE_Msk                          /*!<Output Compare 3 Preload enable        */
+
+#define TIM_CCMR2_OC3M_Pos        (4U)                                         
+#define TIM_CCMR2_OC3M_Msk        (0x7UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000070 */
+#define TIM_CCMR2_OC3M            TIM_CCMR2_OC3M_Msk                           /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
+#define TIM_CCMR2_OC3M_0          (0x1UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x0010 */
+#define TIM_CCMR2_OC3M_1          (0x2UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x0020 */
+#define TIM_CCMR2_OC3M_2          (0x4UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x0040 */
+
+#define TIM_CCMR2_OC3CE_Pos       (7U)                                         
+#define TIM_CCMR2_OC3CE_Msk       (0x1UL << TIM_CCMR2_OC3CE_Pos)                /*!< 0x00000080 */
+#define TIM_CCMR2_OC3CE           TIM_CCMR2_OC3CE_Msk                          /*!<Output Compare 3 Clear Enable */
+
+#define TIM_CCMR2_CC4S_Pos        (8U)                                         
+#define TIM_CCMR2_CC4S_Msk        (0x3UL << TIM_CCMR2_CC4S_Pos)                 /*!< 0x00000300 */
+#define TIM_CCMR2_CC4S            TIM_CCMR2_CC4S_Msk                           /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
+#define TIM_CCMR2_CC4S_0          (0x1UL << TIM_CCMR2_CC4S_Pos)                 /*!< 0x0100 */
+#define TIM_CCMR2_CC4S_1          (0x2UL << TIM_CCMR2_CC4S_Pos)                 /*!< 0x0200 */
+
+#define TIM_CCMR2_OC4FE_Pos       (10U)                                        
+#define TIM_CCMR2_OC4FE_Msk       (0x1UL << TIM_CCMR2_OC4FE_Pos)                /*!< 0x00000400 */
+#define TIM_CCMR2_OC4FE           TIM_CCMR2_OC4FE_Msk                          /*!<Output Compare 4 Fast enable    */
+#define TIM_CCMR2_OC4PE_Pos       (11U)                                        
+#define TIM_CCMR2_OC4PE_Msk       (0x1UL << TIM_CCMR2_OC4PE_Pos)                /*!< 0x00000800 */
+#define TIM_CCMR2_OC4PE           TIM_CCMR2_OC4PE_Msk                          /*!<Output Compare 4 Preload enable */
+
+#define TIM_CCMR2_OC4M_Pos        (12U)                                        
+#define TIM_CCMR2_OC4M_Msk        (0x7UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00007000 */
+#define TIM_CCMR2_OC4M            TIM_CCMR2_OC4M_Msk                           /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
+#define TIM_CCMR2_OC4M_0          (0x1UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x1000 */
+#define TIM_CCMR2_OC4M_1          (0x2UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x2000 */
+#define TIM_CCMR2_OC4M_2          (0x4UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x4000 */
+
+#define TIM_CCMR2_OC4CE_Pos       (15U)                                        
+#define TIM_CCMR2_OC4CE_Msk       (0x1UL << TIM_CCMR2_OC4CE_Pos)                /*!< 0x00008000 */
+#define TIM_CCMR2_OC4CE           TIM_CCMR2_OC4CE_Msk                          /*!<Output Compare 4 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define TIM_CCMR2_IC3PSC_Pos      (2U)                                         
+#define TIM_CCMR2_IC3PSC_Msk      (0x3UL << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x0000000C */
+#define TIM_CCMR2_IC3PSC          TIM_CCMR2_IC3PSC_Msk                         /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
+#define TIM_CCMR2_IC3PSC_0        (0x1UL << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x0004 */
+#define TIM_CCMR2_IC3PSC_1        (0x2UL << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x0008 */
+
+#define TIM_CCMR2_IC3F_Pos        (4U)                                         
+#define TIM_CCMR2_IC3F_Msk        (0xFUL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x000000F0 */
+#define TIM_CCMR2_IC3F            TIM_CCMR2_IC3F_Msk                           /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
+#define TIM_CCMR2_IC3F_0          (0x1UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x0010 */
+#define TIM_CCMR2_IC3F_1          (0x2UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x0020 */
+#define TIM_CCMR2_IC3F_2          (0x4UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x0040 */
+#define TIM_CCMR2_IC3F_3          (0x8UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x0080 */
+
+#define TIM_CCMR2_IC4PSC_Pos      (10U)                                        
+#define TIM_CCMR2_IC4PSC_Msk      (0x3UL << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x00000C00 */
+#define TIM_CCMR2_IC4PSC          TIM_CCMR2_IC4PSC_Msk                         /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
+#define TIM_CCMR2_IC4PSC_0        (0x1UL << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x0400 */
+#define TIM_CCMR2_IC4PSC_1        (0x2UL << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x0800 */
+
+#define TIM_CCMR2_IC4F_Pos        (12U)                                        
+#define TIM_CCMR2_IC4F_Msk        (0xFUL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x0000F000 */
+#define TIM_CCMR2_IC4F            TIM_CCMR2_IC4F_Msk                           /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
+#define TIM_CCMR2_IC4F_0          (0x1UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x1000 */
+#define TIM_CCMR2_IC4F_1          (0x2UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x2000 */
+#define TIM_CCMR2_IC4F_2          (0x4UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x4000 */
+#define TIM_CCMR2_IC4F_3          (0x8UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x8000 */
+
+/*******************  Bit definition for TIM_CCER register  *******************/
+#define TIM_CCER_CC1E_Pos         (0U)                                         
+#define TIM_CCER_CC1E_Msk         (0x1UL << TIM_CCER_CC1E_Pos)                  /*!< 0x00000001 */
+#define TIM_CCER_CC1E             TIM_CCER_CC1E_Msk                            /*!<Capture/Compare 1 output enable                 */
+#define TIM_CCER_CC1P_Pos         (1U)                                         
+#define TIM_CCER_CC1P_Msk         (0x1UL << TIM_CCER_CC1P_Pos)                  /*!< 0x00000002 */
+#define TIM_CCER_CC1P             TIM_CCER_CC1P_Msk                            /*!<Capture/Compare 1 output Polarity               */
+#define TIM_CCER_CC1NE_Pos        (2U)                                         
+#define TIM_CCER_CC1NE_Msk        (0x1UL << TIM_CCER_CC1NE_Pos)                 /*!< 0x00000004 */
+#define TIM_CCER_CC1NE            TIM_CCER_CC1NE_Msk                           /*!<Capture/Compare 1 Complementary output enable   */
+#define TIM_CCER_CC1NP_Pos        (3U)                                         
+#define TIM_CCER_CC1NP_Msk        (0x1UL << TIM_CCER_CC1NP_Pos)                 /*!< 0x00000008 */
+#define TIM_CCER_CC1NP            TIM_CCER_CC1NP_Msk                           /*!<Capture/Compare 1 Complementary output Polarity */
+#define TIM_CCER_CC2E_Pos         (4U)                                         
+#define TIM_CCER_CC2E_Msk         (0x1UL << TIM_CCER_CC2E_Pos)                  /*!< 0x00000010 */
+#define TIM_CCER_CC2E             TIM_CCER_CC2E_Msk                            /*!<Capture/Compare 2 output enable                 */
+#define TIM_CCER_CC2P_Pos         (5U)                                         
+#define TIM_CCER_CC2P_Msk         (0x1UL << TIM_CCER_CC2P_Pos)                  /*!< 0x00000020 */
+#define TIM_CCER_CC2P             TIM_CCER_CC2P_Msk                            /*!<Capture/Compare 2 output Polarity               */
+#define TIM_CCER_CC2NE_Pos        (6U)                                         
+#define TIM_CCER_CC2NE_Msk        (0x1UL << TIM_CCER_CC2NE_Pos)                 /*!< 0x00000040 */
+#define TIM_CCER_CC2NE            TIM_CCER_CC2NE_Msk                           /*!<Capture/Compare 2 Complementary output enable   */
+#define TIM_CCER_CC2NP_Pos        (7U)                                         
+#define TIM_CCER_CC2NP_Msk        (0x1UL << TIM_CCER_CC2NP_Pos)                 /*!< 0x00000080 */
+#define TIM_CCER_CC2NP            TIM_CCER_CC2NP_Msk                           /*!<Capture/Compare 2 Complementary output Polarity */
+#define TIM_CCER_CC3E_Pos         (8U)                                         
+#define TIM_CCER_CC3E_Msk         (0x1UL << TIM_CCER_CC3E_Pos)                  /*!< 0x00000100 */
+#define TIM_CCER_CC3E             TIM_CCER_CC3E_Msk                            /*!<Capture/Compare 3 output enable                 */
+#define TIM_CCER_CC3P_Pos         (9U)                                         
+#define TIM_CCER_CC3P_Msk         (0x1UL << TIM_CCER_CC3P_Pos)                  /*!< 0x00000200 */
+#define TIM_CCER_CC3P             TIM_CCER_CC3P_Msk                            /*!<Capture/Compare 3 output Polarity               */
+#define TIM_CCER_CC3NE_Pos        (10U)                                        
+#define TIM_CCER_CC3NE_Msk        (0x1UL << TIM_CCER_CC3NE_Pos)                 /*!< 0x00000400 */
+#define TIM_CCER_CC3NE            TIM_CCER_CC3NE_Msk                           /*!<Capture/Compare 3 Complementary output enable   */
+#define TIM_CCER_CC3NP_Pos        (11U)                                        
+#define TIM_CCER_CC3NP_Msk        (0x1UL << TIM_CCER_CC3NP_Pos)                 /*!< 0x00000800 */
+#define TIM_CCER_CC3NP            TIM_CCER_CC3NP_Msk                           /*!<Capture/Compare 3 Complementary output Polarity */
+#define TIM_CCER_CC4E_Pos         (12U)                                        
+#define TIM_CCER_CC4E_Msk         (0x1UL << TIM_CCER_CC4E_Pos)                  /*!< 0x00001000 */
+#define TIM_CCER_CC4E             TIM_CCER_CC4E_Msk                            /*!<Capture/Compare 4 output enable                 */
+#define TIM_CCER_CC4P_Pos         (13U)                                        
+#define TIM_CCER_CC4P_Msk         (0x1UL << TIM_CCER_CC4P_Pos)                  /*!< 0x00002000 */
+#define TIM_CCER_CC4P             TIM_CCER_CC4P_Msk                            /*!<Capture/Compare 4 output Polarity               */
+#define TIM_CCER_CC4NP_Pos        (15U)                                        
+#define TIM_CCER_CC4NP_Msk        (0x1UL << TIM_CCER_CC4NP_Pos)                 /*!< 0x00008000 */
+#define TIM_CCER_CC4NP            TIM_CCER_CC4NP_Msk                           /*!<Capture/Compare 4 Complementary output Polarity */
+
+/*******************  Bit definition for TIM_CNT register  ********************/
+#define TIM_CNT_CNT_Pos           (0U)                                             
+#define TIM_CNT_CNT_Msk           (0xFFFFFFFFUL << TIM_CNT_CNT_Pos)                 /*!< 0xFFFFFFFF */
+#define TIM_CNT_CNT               TIM_CNT_CNT_Msk                                  /*!<Counter Value            */
+
+/*******************  Bit definition for TIM_PSC register  ********************/
+#define TIM_PSC_PSC_Pos           (0U)                                         
+#define TIM_PSC_PSC_Msk           (0xFFFFUL << TIM_PSC_PSC_Pos)                 /*!< 0x0000FFFF */
+#define TIM_PSC_PSC               TIM_PSC_PSC_Msk                              /*!<Prescaler Value          */
+
+/*******************  Bit definition for TIM_ARR register  ********************/
+#define TIM_ARR_ARR_Pos           (0U)                                         
+#define TIM_ARR_ARR_Msk           (0xFFFFFFFFUL << TIM_ARR_ARR_Pos)             /*!< 0xFFFFFFFF */
+#define TIM_ARR_ARR               TIM_ARR_ARR_Msk                              /*!<actual auto-reload Value */
+
+/*******************  Bit definition for TIM_RCR register  ********************/
+#define TIM_RCR_REP_Pos           (0U)                                         
+#define TIM_RCR_REP_Msk           (0xFFUL << TIM_RCR_REP_Pos)                   /*!< 0x000000FF */
+#define TIM_RCR_REP               TIM_RCR_REP_Msk                              /*!<Repetition Counter Value */
+
+/*******************  Bit definition for TIM_CCR1 register  *******************/
+#define TIM_CCR1_CCR1_Pos         (0U)                                         
+#define TIM_CCR1_CCR1_Msk         (0xFFFFUL << TIM_CCR1_CCR1_Pos)               /*!< 0x0000FFFF */
+#define TIM_CCR1_CCR1             TIM_CCR1_CCR1_Msk                            /*!<Capture/Compare 1 Value  */
+
+/*******************  Bit definition for TIM_CCR2 register  *******************/
+#define TIM_CCR2_CCR2_Pos         (0U)                                         
+#define TIM_CCR2_CCR2_Msk         (0xFFFFUL << TIM_CCR2_CCR2_Pos)               /*!< 0x0000FFFF */
+#define TIM_CCR2_CCR2             TIM_CCR2_CCR2_Msk                            /*!<Capture/Compare 2 Value  */
+
+/*******************  Bit definition for TIM_CCR3 register  *******************/
+#define TIM_CCR3_CCR3_Pos         (0U)                                         
+#define TIM_CCR3_CCR3_Msk         (0xFFFFUL << TIM_CCR3_CCR3_Pos)               /*!< 0x0000FFFF */
+#define TIM_CCR3_CCR3             TIM_CCR3_CCR3_Msk                            /*!<Capture/Compare 3 Value  */
+
+/*******************  Bit definition for TIM_CCR4 register  *******************/
+#define TIM_CCR4_CCR4_Pos         (0U)                                         
+#define TIM_CCR4_CCR4_Msk         (0xFFFFUL << TIM_CCR4_CCR4_Pos)               /*!< 0x0000FFFF */
+#define TIM_CCR4_CCR4             TIM_CCR4_CCR4_Msk                            /*!<Capture/Compare 4 Value  */
+
+/*******************  Bit definition for TIM_BDTR register  *******************/
+#define TIM_BDTR_DTG_Pos          (0U)                                         
+#define TIM_BDTR_DTG_Msk          (0xFFUL << TIM_BDTR_DTG_Pos)                  /*!< 0x000000FF */
+#define TIM_BDTR_DTG              TIM_BDTR_DTG_Msk                             /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
+#define TIM_BDTR_DTG_0            (0x01UL << TIM_BDTR_DTG_Pos)                  /*!< 0x0001 */
+#define TIM_BDTR_DTG_1            (0x02UL << TIM_BDTR_DTG_Pos)                  /*!< 0x0002 */
+#define TIM_BDTR_DTG_2            (0x04UL << TIM_BDTR_DTG_Pos)                  /*!< 0x0004 */
+#define TIM_BDTR_DTG_3            (0x08UL << TIM_BDTR_DTG_Pos)                  /*!< 0x0008 */
+#define TIM_BDTR_DTG_4            (0x10UL << TIM_BDTR_DTG_Pos)                  /*!< 0x0010 */
+#define TIM_BDTR_DTG_5            (0x20UL << TIM_BDTR_DTG_Pos)                  /*!< 0x0020 */
+#define TIM_BDTR_DTG_6            (0x40UL << TIM_BDTR_DTG_Pos)                  /*!< 0x0040 */
+#define TIM_BDTR_DTG_7            (0x80UL << TIM_BDTR_DTG_Pos)                  /*!< 0x0080 */
+
+#define TIM_BDTR_LOCK_Pos         (8U)                                         
+#define TIM_BDTR_LOCK_Msk         (0x3UL << TIM_BDTR_LOCK_Pos)                  /*!< 0x00000300 */
+#define TIM_BDTR_LOCK             TIM_BDTR_LOCK_Msk                            /*!<LOCK[1:0] bits (Lock Configuration) */
+#define TIM_BDTR_LOCK_0           (0x1UL << TIM_BDTR_LOCK_Pos)                  /*!< 0x0100 */
+#define TIM_BDTR_LOCK_1           (0x2UL << TIM_BDTR_LOCK_Pos)                  /*!< 0x0200 */
+
+#define TIM_BDTR_OSSI_Pos         (10U)                                        
+#define TIM_BDTR_OSSI_Msk         (0x1UL << TIM_BDTR_OSSI_Pos)                  /*!< 0x00000400 */
+#define TIM_BDTR_OSSI             TIM_BDTR_OSSI_Msk                            /*!<Off-State Selection for Idle mode */
+#define TIM_BDTR_OSSR_Pos         (11U)                                        
+#define TIM_BDTR_OSSR_Msk         (0x1UL << TIM_BDTR_OSSR_Pos)                  /*!< 0x00000800 */
+#define TIM_BDTR_OSSR             TIM_BDTR_OSSR_Msk                            /*!<Off-State Selection for Run mode  */
+#define TIM_BDTR_BKE_Pos          (12U)                                        
+#define TIM_BDTR_BKE_Msk          (0x1UL << TIM_BDTR_BKE_Pos)                   /*!< 0x00001000 */
+#define TIM_BDTR_BKE              TIM_BDTR_BKE_Msk                             /*!<Break enable                      */
+#define TIM_BDTR_BKP_Pos          (13U)                                        
+#define TIM_BDTR_BKP_Msk          (0x1UL << TIM_BDTR_BKP_Pos)                   /*!< 0x00002000 */
+#define TIM_BDTR_BKP              TIM_BDTR_BKP_Msk                             /*!<Break Polarity                    */
+#define TIM_BDTR_AOE_Pos          (14U)                                        
+#define TIM_BDTR_AOE_Msk          (0x1UL << TIM_BDTR_AOE_Pos)                   /*!< 0x00004000 */
+#define TIM_BDTR_AOE              TIM_BDTR_AOE_Msk                             /*!<Automatic Output enable           */
+#define TIM_BDTR_MOE_Pos          (15U)                                        
+#define TIM_BDTR_MOE_Msk          (0x1UL << TIM_BDTR_MOE_Pos)                   /*!< 0x00008000 */
+#define TIM_BDTR_MOE              TIM_BDTR_MOE_Msk                             /*!<Main Output enable                */
+
+/*******************  Bit definition for TIM_DCR register  ********************/
+#define TIM_DCR_DBA_Pos           (0U)                                         
+#define TIM_DCR_DBA_Msk           (0x1FUL << TIM_DCR_DBA_Pos)                   /*!< 0x0000001F */
+#define TIM_DCR_DBA               TIM_DCR_DBA_Msk                              /*!<DBA[4:0] bits (DMA Base Address) */
+#define TIM_DCR_DBA_0             (0x01UL << TIM_DCR_DBA_Pos)                   /*!< 0x0001 */
+#define TIM_DCR_DBA_1             (0x02UL << TIM_DCR_DBA_Pos)                   /*!< 0x0002 */
+#define TIM_DCR_DBA_2             (0x04UL << TIM_DCR_DBA_Pos)                   /*!< 0x0004 */
+#define TIM_DCR_DBA_3             (0x08UL << TIM_DCR_DBA_Pos)                   /*!< 0x0008 */
+#define TIM_DCR_DBA_4             (0x10UL << TIM_DCR_DBA_Pos)                   /*!< 0x0010 */
+
+#define TIM_DCR_DBL_Pos           (8U)                                         
+#define TIM_DCR_DBL_Msk           (0x1FUL << TIM_DCR_DBL_Pos)                   /*!< 0x00001F00 */
+#define TIM_DCR_DBL               TIM_DCR_DBL_Msk                              /*!<DBL[4:0] bits (DMA Burst Length) */
+#define TIM_DCR_DBL_0             (0x01UL << TIM_DCR_DBL_Pos)                   /*!< 0x0100 */
+#define TIM_DCR_DBL_1             (0x02UL << TIM_DCR_DBL_Pos)                   /*!< 0x0200 */
+#define TIM_DCR_DBL_2             (0x04UL << TIM_DCR_DBL_Pos)                   /*!< 0x0400 */
+#define TIM_DCR_DBL_3             (0x08UL << TIM_DCR_DBL_Pos)                   /*!< 0x0800 */
+#define TIM_DCR_DBL_4             (0x10UL << TIM_DCR_DBL_Pos)                   /*!< 0x1000 */
+
+/*******************  Bit definition for TIM_DMAR register  *******************/
+#define TIM_DMAR_DMAB_Pos         (0U)                                         
+#define TIM_DMAR_DMAB_Msk         (0xFFFFUL << TIM_DMAR_DMAB_Pos)               /*!< 0x0000FFFF */
+#define TIM_DMAR_DMAB             TIM_DMAR_DMAB_Msk                            /*!<DMA register for burst accesses                    */
+
+/*******************  Bit definition for TIM_OR register  *********************/
+#define TIM_OR_TI1_RMP_Pos        (0U)                                          
+#define TIM_OR_TI1_RMP_Msk        (0x3UL << TIM_OR_TI1_RMP_Pos)                 /*!< 0x00000003 */
+#define TIM_OR_TI1_RMP            TIM_OR_TI1_RMP_Msk                           /*!< TI1_RMP[1:0] bits (TIM11 Input Capture 1 remap) */
+#define TIM_OR_TI1_RMP_0          (0x1UL << TIM_OR_TI1_RMP_Pos)                 /*!< 0x00000001 */
+#define TIM_OR_TI1_RMP_1          (0x2UL << TIM_OR_TI1_RMP_Pos)                 /*!< 0x00000002 */
+
+#define TIM_OR_TI4_RMP_Pos        (6U)                                         
+#define TIM_OR_TI4_RMP_Msk        (0x3UL << TIM_OR_TI4_RMP_Pos)                 /*!< 0x000000C0 */
+#define TIM_OR_TI4_RMP            TIM_OR_TI4_RMP_Msk                           /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap)             */
+#define TIM_OR_TI4_RMP_0          (0x1UL << TIM_OR_TI4_RMP_Pos)                 /*!< 0x0040 */
+#define TIM_OR_TI4_RMP_1          (0x2UL << TIM_OR_TI4_RMP_Pos)                 /*!< 0x0080 */
+#define TIM_OR_ITR1_RMP_Pos       (10U)                                        
+#define TIM_OR_ITR1_RMP_Msk       (0x3UL << TIM_OR_ITR1_RMP_Pos)                /*!< 0x00000C00 */
+#define TIM_OR_ITR1_RMP           TIM_OR_ITR1_RMP_Msk                          /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */
+#define TIM_OR_ITR1_RMP_0         (0x1UL << TIM_OR_ITR1_RMP_Pos)                /*!< 0x0400 */
+#define TIM_OR_ITR1_RMP_1         (0x2UL << TIM_OR_ITR1_RMP_Pos)                /*!< 0x0800 */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*         Universal Synchronous Asynchronous Receiver Transmitter            */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for USART_SR register  *******************/
+#define USART_SR_PE_Pos               (0U)                                     
+#define USART_SR_PE_Msk               (0x1UL << USART_SR_PE_Pos)                /*!< 0x00000001 */
+#define USART_SR_PE                   USART_SR_PE_Msk                          /*!<Parity Error                 */
+#define USART_SR_FE_Pos               (1U)                                     
+#define USART_SR_FE_Msk               (0x1UL << USART_SR_FE_Pos)                /*!< 0x00000002 */
+#define USART_SR_FE                   USART_SR_FE_Msk                          /*!<Framing Error                */
+#define USART_SR_NE_Pos               (2U)                                     
+#define USART_SR_NE_Msk               (0x1UL << USART_SR_NE_Pos)                /*!< 0x00000004 */
+#define USART_SR_NE                   USART_SR_NE_Msk                          /*!<Noise Error Flag             */
+#define USART_SR_ORE_Pos              (3U)                                     
+#define USART_SR_ORE_Msk              (0x1UL << USART_SR_ORE_Pos)               /*!< 0x00000008 */
+#define USART_SR_ORE                  USART_SR_ORE_Msk                         /*!<OverRun Error                */
+#define USART_SR_IDLE_Pos             (4U)                                     
+#define USART_SR_IDLE_Msk             (0x1UL << USART_SR_IDLE_Pos)              /*!< 0x00000010 */
+#define USART_SR_IDLE                 USART_SR_IDLE_Msk                        /*!<IDLE line detected           */
+#define USART_SR_RXNE_Pos             (5U)                                     
+#define USART_SR_RXNE_Msk             (0x1UL << USART_SR_RXNE_Pos)              /*!< 0x00000020 */
+#define USART_SR_RXNE                 USART_SR_RXNE_Msk                        /*!<Read Data Register Not Empty */
+#define USART_SR_TC_Pos               (6U)                                     
+#define USART_SR_TC_Msk               (0x1UL << USART_SR_TC_Pos)                /*!< 0x00000040 */
+#define USART_SR_TC                   USART_SR_TC_Msk                          /*!<Transmission Complete        */
+#define USART_SR_TXE_Pos              (7U)                                     
+#define USART_SR_TXE_Msk              (0x1UL << USART_SR_TXE_Pos)               /*!< 0x00000080 */
+#define USART_SR_TXE                  USART_SR_TXE_Msk                         /*!<Transmit Data Register Empty */
+#define USART_SR_LBD_Pos              (8U)                                     
+#define USART_SR_LBD_Msk              (0x1UL << USART_SR_LBD_Pos)               /*!< 0x00000100 */
+#define USART_SR_LBD                  USART_SR_LBD_Msk                         /*!<LIN Break Detection Flag     */
+#define USART_SR_CTS_Pos              (9U)                                     
+#define USART_SR_CTS_Msk              (0x1UL << USART_SR_CTS_Pos)               /*!< 0x00000200 */
+#define USART_SR_CTS                  USART_SR_CTS_Msk                         /*!<CTS Flag                     */
+
+/*******************  Bit definition for USART_DR register  *******************/
+#define USART_DR_DR_Pos               (0U)                                     
+#define USART_DR_DR_Msk               (0x1FFUL << USART_DR_DR_Pos)              /*!< 0x000001FF */
+#define USART_DR_DR                   USART_DR_DR_Msk                          /*!<Data value */
+
+/******************  Bit definition for USART_BRR register  *******************/
+#define USART_BRR_DIV_Fraction_Pos    (0U)                                     
+#define USART_BRR_DIV_Fraction_Msk    (0xFUL << USART_BRR_DIV_Fraction_Pos)     /*!< 0x0000000F */
+#define USART_BRR_DIV_Fraction        USART_BRR_DIV_Fraction_Msk               /*!<Fraction of USARTDIV */
+#define USART_BRR_DIV_Mantissa_Pos    (4U)                                     
+#define USART_BRR_DIV_Mantissa_Msk    (0xFFFUL << USART_BRR_DIV_Mantissa_Pos)   /*!< 0x0000FFF0 */
+#define USART_BRR_DIV_Mantissa        USART_BRR_DIV_Mantissa_Msk               /*!<Mantissa of USARTDIV */
+
+/******************  Bit definition for USART_CR1 register  *******************/
+#define USART_CR1_SBK_Pos             (0U)                                     
+#define USART_CR1_SBK_Msk             (0x1UL << USART_CR1_SBK_Pos)              /*!< 0x00000001 */
+#define USART_CR1_SBK                 USART_CR1_SBK_Msk                        /*!<Send Break                             */
+#define USART_CR1_RWU_Pos             (1U)                                     
+#define USART_CR1_RWU_Msk             (0x1UL << USART_CR1_RWU_Pos)              /*!< 0x00000002 */
+#define USART_CR1_RWU                 USART_CR1_RWU_Msk                        /*!<Receiver wakeup                        */
+#define USART_CR1_RE_Pos              (2U)                                     
+#define USART_CR1_RE_Msk              (0x1UL << USART_CR1_RE_Pos)               /*!< 0x00000004 */
+#define USART_CR1_RE                  USART_CR1_RE_Msk                         /*!<Receiver Enable                        */
+#define USART_CR1_TE_Pos              (3U)                                     
+#define USART_CR1_TE_Msk              (0x1UL << USART_CR1_TE_Pos)               /*!< 0x00000008 */
+#define USART_CR1_TE                  USART_CR1_TE_Msk                         /*!<Transmitter Enable                     */
+#define USART_CR1_IDLEIE_Pos          (4U)                                     
+#define USART_CR1_IDLEIE_Msk          (0x1UL << USART_CR1_IDLEIE_Pos)           /*!< 0x00000010 */
+#define USART_CR1_IDLEIE              USART_CR1_IDLEIE_Msk                     /*!<IDLE Interrupt Enable                  */
+#define USART_CR1_RXNEIE_Pos          (5U)                                     
+#define USART_CR1_RXNEIE_Msk          (0x1UL << USART_CR1_RXNEIE_Pos)           /*!< 0x00000020 */
+#define USART_CR1_RXNEIE              USART_CR1_RXNEIE_Msk                     /*!<RXNE Interrupt Enable                  */
+#define USART_CR1_TCIE_Pos            (6U)                                     
+#define USART_CR1_TCIE_Msk            (0x1UL << USART_CR1_TCIE_Pos)             /*!< 0x00000040 */
+#define USART_CR1_TCIE                USART_CR1_TCIE_Msk                       /*!<Transmission Complete Interrupt Enable */
+#define USART_CR1_TXEIE_Pos           (7U)                                     
+#define USART_CR1_TXEIE_Msk           (0x1UL << USART_CR1_TXEIE_Pos)            /*!< 0x00000080 */
+#define USART_CR1_TXEIE               USART_CR1_TXEIE_Msk                      /*!<TXE Interrupt Enable                   */
+#define USART_CR1_PEIE_Pos            (8U)                                     
+#define USART_CR1_PEIE_Msk            (0x1UL << USART_CR1_PEIE_Pos)             /*!< 0x00000100 */
+#define USART_CR1_PEIE                USART_CR1_PEIE_Msk                       /*!<PE Interrupt Enable                    */
+#define USART_CR1_PS_Pos              (9U)                                     
+#define USART_CR1_PS_Msk              (0x1UL << USART_CR1_PS_Pos)               /*!< 0x00000200 */
+#define USART_CR1_PS                  USART_CR1_PS_Msk                         /*!<Parity Selection                       */
+#define USART_CR1_PCE_Pos             (10U)                                    
+#define USART_CR1_PCE_Msk             (0x1UL << USART_CR1_PCE_Pos)              /*!< 0x00000400 */
+#define USART_CR1_PCE                 USART_CR1_PCE_Msk                        /*!<Parity Control Enable                  */
+#define USART_CR1_WAKE_Pos            (11U)                                    
+#define USART_CR1_WAKE_Msk            (0x1UL << USART_CR1_WAKE_Pos)             /*!< 0x00000800 */
+#define USART_CR1_WAKE                USART_CR1_WAKE_Msk                       /*!<Wakeup method                          */
+#define USART_CR1_M_Pos               (12U)                                    
+#define USART_CR1_M_Msk               (0x1UL << USART_CR1_M_Pos)                /*!< 0x00001000 */
+#define USART_CR1_M                   USART_CR1_M_Msk                          /*!<Word length                            */
+#define USART_CR1_UE_Pos              (13U)                                    
+#define USART_CR1_UE_Msk              (0x1UL << USART_CR1_UE_Pos)               /*!< 0x00002000 */
+#define USART_CR1_UE                  USART_CR1_UE_Msk                         /*!<USART Enable                           */
+#define USART_CR1_OVER8_Pos           (15U)                                    
+#define USART_CR1_OVER8_Msk           (0x1UL << USART_CR1_OVER8_Pos)            /*!< 0x00008000 */
+#define USART_CR1_OVER8               USART_CR1_OVER8_Msk                      /*!<USART Oversampling by 8 enable         */
+
+/******************  Bit definition for USART_CR2 register  *******************/
+#define USART_CR2_ADD_Pos             (0U)                                     
+#define USART_CR2_ADD_Msk             (0xFUL << USART_CR2_ADD_Pos)              /*!< 0x0000000F */
+#define USART_CR2_ADD                 USART_CR2_ADD_Msk                        /*!<Address of the USART node            */
+#define USART_CR2_LBDL_Pos            (5U)                                     
+#define USART_CR2_LBDL_Msk            (0x1UL << USART_CR2_LBDL_Pos)             /*!< 0x00000020 */
+#define USART_CR2_LBDL                USART_CR2_LBDL_Msk                       /*!<LIN Break Detection Length           */
+#define USART_CR2_LBDIE_Pos           (6U)                                     
+#define USART_CR2_LBDIE_Msk           (0x1UL << USART_CR2_LBDIE_Pos)            /*!< 0x00000040 */
+#define USART_CR2_LBDIE               USART_CR2_LBDIE_Msk                      /*!<LIN Break Detection Interrupt Enable */
+#define USART_CR2_LBCL_Pos            (8U)                                     
+#define USART_CR2_LBCL_Msk            (0x1UL << USART_CR2_LBCL_Pos)             /*!< 0x00000100 */
+#define USART_CR2_LBCL                USART_CR2_LBCL_Msk                       /*!<Last Bit Clock pulse                 */
+#define USART_CR2_CPHA_Pos            (9U)                                     
+#define USART_CR2_CPHA_Msk            (0x1UL << USART_CR2_CPHA_Pos)             /*!< 0x00000200 */
+#define USART_CR2_CPHA                USART_CR2_CPHA_Msk                       /*!<Clock Phase                          */
+#define USART_CR2_CPOL_Pos            (10U)                                    
+#define USART_CR2_CPOL_Msk            (0x1UL << USART_CR2_CPOL_Pos)             /*!< 0x00000400 */
+#define USART_CR2_CPOL                USART_CR2_CPOL_Msk                       /*!<Clock Polarity                       */
+#define USART_CR2_CLKEN_Pos           (11U)                                    
+#define USART_CR2_CLKEN_Msk           (0x1UL << USART_CR2_CLKEN_Pos)            /*!< 0x00000800 */
+#define USART_CR2_CLKEN               USART_CR2_CLKEN_Msk                      /*!<Clock Enable                         */
+
+#define USART_CR2_STOP_Pos            (12U)                                    
+#define USART_CR2_STOP_Msk            (0x3UL << USART_CR2_STOP_Pos)             /*!< 0x00003000 */
+#define USART_CR2_STOP                USART_CR2_STOP_Msk                       /*!<STOP[1:0] bits (STOP bits) */
+#define USART_CR2_STOP_0              (0x1UL << USART_CR2_STOP_Pos)             /*!< 0x1000 */
+#define USART_CR2_STOP_1              (0x2UL << USART_CR2_STOP_Pos)             /*!< 0x2000 */
+
+#define USART_CR2_LINEN_Pos           (14U)                                    
+#define USART_CR2_LINEN_Msk           (0x1UL << USART_CR2_LINEN_Pos)            /*!< 0x00004000 */
+#define USART_CR2_LINEN               USART_CR2_LINEN_Msk                      /*!<LIN mode enable */
+
+/******************  Bit definition for USART_CR3 register  *******************/
+#define USART_CR3_EIE_Pos             (0U)                                     
+#define USART_CR3_EIE_Msk             (0x1UL << USART_CR3_EIE_Pos)              /*!< 0x00000001 */
+#define USART_CR3_EIE                 USART_CR3_EIE_Msk                        /*!<Error Interrupt Enable      */
+#define USART_CR3_IREN_Pos            (1U)                                     
+#define USART_CR3_IREN_Msk            (0x1UL << USART_CR3_IREN_Pos)             /*!< 0x00000002 */
+#define USART_CR3_IREN                USART_CR3_IREN_Msk                       /*!<IrDA mode Enable            */
+#define USART_CR3_IRLP_Pos            (2U)                                     
+#define USART_CR3_IRLP_Msk            (0x1UL << USART_CR3_IRLP_Pos)             /*!< 0x00000004 */
+#define USART_CR3_IRLP                USART_CR3_IRLP_Msk                       /*!<IrDA Low-Power              */
+#define USART_CR3_HDSEL_Pos           (3U)                                     
+#define USART_CR3_HDSEL_Msk           (0x1UL << USART_CR3_HDSEL_Pos)            /*!< 0x00000008 */
+#define USART_CR3_HDSEL               USART_CR3_HDSEL_Msk                      /*!<Half-Duplex Selection       */
+#define USART_CR3_NACK_Pos            (4U)                                     
+#define USART_CR3_NACK_Msk            (0x1UL << USART_CR3_NACK_Pos)             /*!< 0x00000010 */
+#define USART_CR3_NACK                USART_CR3_NACK_Msk                       /*!<Smartcard NACK enable       */
+#define USART_CR3_SCEN_Pos            (5U)                                     
+#define USART_CR3_SCEN_Msk            (0x1UL << USART_CR3_SCEN_Pos)             /*!< 0x00000020 */
+#define USART_CR3_SCEN                USART_CR3_SCEN_Msk                       /*!<Smartcard mode enable       */
+#define USART_CR3_DMAR_Pos            (6U)                                     
+#define USART_CR3_DMAR_Msk            (0x1UL << USART_CR3_DMAR_Pos)             /*!< 0x00000040 */
+#define USART_CR3_DMAR                USART_CR3_DMAR_Msk                       /*!<DMA Enable Receiver         */
+#define USART_CR3_DMAT_Pos            (7U)                                     
+#define USART_CR3_DMAT_Msk            (0x1UL << USART_CR3_DMAT_Pos)             /*!< 0x00000080 */
+#define USART_CR3_DMAT                USART_CR3_DMAT_Msk                       /*!<DMA Enable Transmitter      */
+#define USART_CR3_RTSE_Pos            (8U)                                     
+#define USART_CR3_RTSE_Msk            (0x1UL << USART_CR3_RTSE_Pos)             /*!< 0x00000100 */
+#define USART_CR3_RTSE                USART_CR3_RTSE_Msk                       /*!<RTS Enable                  */
+#define USART_CR3_CTSE_Pos            (9U)                                     
+#define USART_CR3_CTSE_Msk            (0x1UL << USART_CR3_CTSE_Pos)             /*!< 0x00000200 */
+#define USART_CR3_CTSE                USART_CR3_CTSE_Msk                       /*!<CTS Enable                  */
+#define USART_CR3_CTSIE_Pos           (10U)                                    
+#define USART_CR3_CTSIE_Msk           (0x1UL << USART_CR3_CTSIE_Pos)            /*!< 0x00000400 */
+#define USART_CR3_CTSIE               USART_CR3_CTSIE_Msk                      /*!<CTS Interrupt Enable        */
+#define USART_CR3_ONEBIT_Pos          (11U)                                    
+#define USART_CR3_ONEBIT_Msk          (0x1UL << USART_CR3_ONEBIT_Pos)           /*!< 0x00000800 */
+#define USART_CR3_ONEBIT              USART_CR3_ONEBIT_Msk                     /*!<USART One bit method enable */
+
+/******************  Bit definition for USART_GTPR register  ******************/
+#define USART_GTPR_PSC_Pos            (0U)                                     
+#define USART_GTPR_PSC_Msk            (0xFFUL << USART_GTPR_PSC_Pos)            /*!< 0x000000FF */
+#define USART_GTPR_PSC                USART_GTPR_PSC_Msk                       /*!<PSC[7:0] bits (Prescaler value) */
+#define USART_GTPR_PSC_0              (0x01UL << USART_GTPR_PSC_Pos)            /*!< 0x0001 */
+#define USART_GTPR_PSC_1              (0x02UL << USART_GTPR_PSC_Pos)            /*!< 0x0002 */
+#define USART_GTPR_PSC_2              (0x04UL << USART_GTPR_PSC_Pos)            /*!< 0x0004 */
+#define USART_GTPR_PSC_3              (0x08UL << USART_GTPR_PSC_Pos)            /*!< 0x0008 */
+#define USART_GTPR_PSC_4              (0x10UL << USART_GTPR_PSC_Pos)            /*!< 0x0010 */
+#define USART_GTPR_PSC_5              (0x20UL << USART_GTPR_PSC_Pos)            /*!< 0x0020 */
+#define USART_GTPR_PSC_6              (0x40UL << USART_GTPR_PSC_Pos)            /*!< 0x0040 */
+#define USART_GTPR_PSC_7              (0x80UL << USART_GTPR_PSC_Pos)            /*!< 0x0080 */
+
+#define USART_GTPR_GT_Pos             (8U)                                     
+#define USART_GTPR_GT_Msk             (0xFFUL << USART_GTPR_GT_Pos)             /*!< 0x0000FF00 */
+#define USART_GTPR_GT                 USART_GTPR_GT_Msk                        /*!<Guard time value */
+
+/******************************************************************************/
+/*                                                                            */
+/*                            Window WATCHDOG                                 */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for WWDG_CR register  ********************/
+#define WWDG_CR_T_Pos           (0U)                                           
+#define WWDG_CR_T_Msk           (0x7FUL << WWDG_CR_T_Pos)                       /*!< 0x0000007F */
+#define WWDG_CR_T               WWDG_CR_T_Msk                                  /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
+#define WWDG_CR_T_0             (0x01UL << WWDG_CR_T_Pos)                       /*!< 0x01 */
+#define WWDG_CR_T_1             (0x02UL << WWDG_CR_T_Pos)                       /*!< 0x02 */
+#define WWDG_CR_T_2             (0x04UL << WWDG_CR_T_Pos)                       /*!< 0x04 */
+#define WWDG_CR_T_3             (0x08UL << WWDG_CR_T_Pos)                       /*!< 0x08 */
+#define WWDG_CR_T_4             (0x10UL << WWDG_CR_T_Pos)                       /*!< 0x10 */
+#define WWDG_CR_T_5             (0x20UL << WWDG_CR_T_Pos)                       /*!< 0x20 */
+#define WWDG_CR_T_6             (0x40UL << WWDG_CR_T_Pos)                       /*!< 0x40 */
+/* Legacy defines */
+#define  WWDG_CR_T0                          WWDG_CR_T_0
+#define  WWDG_CR_T1                          WWDG_CR_T_1
+#define  WWDG_CR_T2                          WWDG_CR_T_2
+#define  WWDG_CR_T3                          WWDG_CR_T_3
+#define  WWDG_CR_T4                          WWDG_CR_T_4
+#define  WWDG_CR_T5                          WWDG_CR_T_5
+#define  WWDG_CR_T6                          WWDG_CR_T_6
+
+#define WWDG_CR_WDGA_Pos        (7U)                                           
+#define WWDG_CR_WDGA_Msk        (0x1UL << WWDG_CR_WDGA_Pos)                     /*!< 0x00000080 */
+#define WWDG_CR_WDGA            WWDG_CR_WDGA_Msk                               /*!<Activation bit */
+
+/*******************  Bit definition for WWDG_CFR register  *******************/
+#define WWDG_CFR_W_Pos          (0U)                                           
+#define WWDG_CFR_W_Msk          (0x7FUL << WWDG_CFR_W_Pos)                      /*!< 0x0000007F */
+#define WWDG_CFR_W              WWDG_CFR_W_Msk                                 /*!<W[6:0] bits (7-bit window value) */
+#define WWDG_CFR_W_0            (0x01UL << WWDG_CFR_W_Pos)                      /*!< 0x0001 */
+#define WWDG_CFR_W_1            (0x02UL << WWDG_CFR_W_Pos)                      /*!< 0x0002 */
+#define WWDG_CFR_W_2            (0x04UL << WWDG_CFR_W_Pos)                      /*!< 0x0004 */
+#define WWDG_CFR_W_3            (0x08UL << WWDG_CFR_W_Pos)                      /*!< 0x0008 */
+#define WWDG_CFR_W_4            (0x10UL << WWDG_CFR_W_Pos)                      /*!< 0x0010 */
+#define WWDG_CFR_W_5            (0x20UL << WWDG_CFR_W_Pos)                      /*!< 0x0020 */
+#define WWDG_CFR_W_6            (0x40UL << WWDG_CFR_W_Pos)                      /*!< 0x0040 */
+/* Legacy defines */
+#define  WWDG_CFR_W0                         WWDG_CFR_W_0
+#define  WWDG_CFR_W1                         WWDG_CFR_W_1
+#define  WWDG_CFR_W2                         WWDG_CFR_W_2
+#define  WWDG_CFR_W3                         WWDG_CFR_W_3
+#define  WWDG_CFR_W4                         WWDG_CFR_W_4
+#define  WWDG_CFR_W5                         WWDG_CFR_W_5
+#define  WWDG_CFR_W6                         WWDG_CFR_W_6
+
+#define WWDG_CFR_WDGTB_Pos      (7U)                                           
+#define WWDG_CFR_WDGTB_Msk      (0x3UL << WWDG_CFR_WDGTB_Pos)                   /*!< 0x00000180 */
+#define WWDG_CFR_WDGTB          WWDG_CFR_WDGTB_Msk                             /*!<WDGTB[1:0] bits (Timer Base) */
+#define WWDG_CFR_WDGTB_0        (0x1UL << WWDG_CFR_WDGTB_Pos)                   /*!< 0x0080 */
+#define WWDG_CFR_WDGTB_1        (0x2UL << WWDG_CFR_WDGTB_Pos)                   /*!< 0x0100 */
+/* Legacy defines */
+#define  WWDG_CFR_WDGTB0                     WWDG_CFR_WDGTB_0
+#define  WWDG_CFR_WDGTB1                     WWDG_CFR_WDGTB_1
+
+#define WWDG_CFR_EWI_Pos        (9U)                                           
+#define WWDG_CFR_EWI_Msk        (0x1UL << WWDG_CFR_EWI_Pos)                     /*!< 0x00000200 */
+#define WWDG_CFR_EWI            WWDG_CFR_EWI_Msk                               /*!<Early Wakeup Interrupt */
+
+/*******************  Bit definition for WWDG_SR register  ********************/
+#define WWDG_SR_EWIF_Pos        (0U)                                           
+#define WWDG_SR_EWIF_Msk        (0x1UL << WWDG_SR_EWIF_Pos)                     /*!< 0x00000001 */
+#define WWDG_SR_EWIF            WWDG_SR_EWIF_Msk                               /*!<Early Wakeup Interrupt Flag */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                                DBG                                         */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bit definition for DBGMCU_IDCODE register  *************/
+#define DBGMCU_IDCODE_DEV_ID_Pos                     (0U)                      
+#define DBGMCU_IDCODE_DEV_ID_Msk                     (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
+#define DBGMCU_IDCODE_DEV_ID                         DBGMCU_IDCODE_DEV_ID_Msk  
+#define DBGMCU_IDCODE_REV_ID_Pos                     (16U)                     
+#define DBGMCU_IDCODE_REV_ID_Msk                     (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
+#define DBGMCU_IDCODE_REV_ID                         DBGMCU_IDCODE_REV_ID_Msk  
+
+/********************  Bit definition for DBGMCU_CR register  *****************/
+#define DBGMCU_CR_DBG_SLEEP_Pos                      (0U)                      
+#define DBGMCU_CR_DBG_SLEEP_Msk                      (0x1UL << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */
+#define DBGMCU_CR_DBG_SLEEP                          DBGMCU_CR_DBG_SLEEP_Msk   
+#define DBGMCU_CR_DBG_STOP_Pos                       (1U)                      
+#define DBGMCU_CR_DBG_STOP_Msk                       (0x1UL << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */
+#define DBGMCU_CR_DBG_STOP                           DBGMCU_CR_DBG_STOP_Msk    
+#define DBGMCU_CR_DBG_STANDBY_Pos                    (2U)                      
+#define DBGMCU_CR_DBG_STANDBY_Msk                    (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */
+#define DBGMCU_CR_DBG_STANDBY                        DBGMCU_CR_DBG_STANDBY_Msk 
+#define DBGMCU_CR_TRACE_IOEN_Pos                     (5U)                      
+#define DBGMCU_CR_TRACE_IOEN_Msk                     (0x1UL << DBGMCU_CR_TRACE_IOEN_Pos) /*!< 0x00000020 */
+#define DBGMCU_CR_TRACE_IOEN                         DBGMCU_CR_TRACE_IOEN_Msk  
+
+#define DBGMCU_CR_TRACE_MODE_Pos                     (6U)                      
+#define DBGMCU_CR_TRACE_MODE_Msk                     (0x3UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x000000C0 */
+#define DBGMCU_CR_TRACE_MODE                         DBGMCU_CR_TRACE_MODE_Msk  
+#define DBGMCU_CR_TRACE_MODE_0                       (0x1UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000040 */
+#define DBGMCU_CR_TRACE_MODE_1                       (0x2UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000080 */
+
+/********************  Bit definition for DBGMCU_APB1_FZ register  ************/
+#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos             (0U)                      
+#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk             (0x1UL << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */
+#define DBGMCU_APB1_FZ_DBG_TIM2_STOP                 DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk 
+#define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos             (1U)                      
+#define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk             (0x1UL << DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos) /*!< 0x00000002 */
+#define DBGMCU_APB1_FZ_DBG_TIM3_STOP                 DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk 
+#define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos             (2U)                      
+#define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk             (0x1UL << DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos) /*!< 0x00000004 */
+#define DBGMCU_APB1_FZ_DBG_TIM4_STOP                 DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk 
+#define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos             (3U)                      
+#define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk             (0x1UL << DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos) /*!< 0x00000008 */
+#define DBGMCU_APB1_FZ_DBG_TIM5_STOP                 DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk 
+#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos             (4U)                      
+#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk             (0x1UL << DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos) /*!< 0x00000010 */
+#define DBGMCU_APB1_FZ_DBG_TIM6_STOP                 DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk 
+#define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos             (5U)                      
+#define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk             (0x1UL << DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos) /*!< 0x00000020 */
+#define DBGMCU_APB1_FZ_DBG_TIM7_STOP                 DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk 
+#define DBGMCU_APB1_FZ_DBG_TIM12_STOP_Pos            (6U)                      
+#define DBGMCU_APB1_FZ_DBG_TIM12_STOP_Msk            (0x1UL << DBGMCU_APB1_FZ_DBG_TIM12_STOP_Pos) /*!< 0x00000040 */
+#define DBGMCU_APB1_FZ_DBG_TIM12_STOP                DBGMCU_APB1_FZ_DBG_TIM12_STOP_Msk 
+#define DBGMCU_APB1_FZ_DBG_TIM13_STOP_Pos            (7U)                      
+#define DBGMCU_APB1_FZ_DBG_TIM13_STOP_Msk            (0x1UL << DBGMCU_APB1_FZ_DBG_TIM13_STOP_Pos) /*!< 0x00000080 */
+#define DBGMCU_APB1_FZ_DBG_TIM13_STOP                DBGMCU_APB1_FZ_DBG_TIM13_STOP_Msk 
+#define DBGMCU_APB1_FZ_DBG_TIM14_STOP_Pos            (8U)                      
+#define DBGMCU_APB1_FZ_DBG_TIM14_STOP_Msk            (0x1UL << DBGMCU_APB1_FZ_DBG_TIM14_STOP_Pos) /*!< 0x00000100 */
+#define DBGMCU_APB1_FZ_DBG_TIM14_STOP                DBGMCU_APB1_FZ_DBG_TIM14_STOP_Msk 
+#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos              (10U)                     
+#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk              (0x1UL << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos) /*!< 0x00000400 */
+#define DBGMCU_APB1_FZ_DBG_RTC_STOP                  DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk 
+#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos             (11U)                     
+#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk             (0x1UL << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */
+#define DBGMCU_APB1_FZ_DBG_WWDG_STOP                 DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk 
+#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos             (12U)                     
+#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk             (0x1UL << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */
+#define DBGMCU_APB1_FZ_DBG_IWDG_STOP                 DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk 
+#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos    (21U)                     
+#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk    (0x1UL << DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos) /*!< 0x00200000 */
+#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT        DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk 
+#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos    (22U)                     
+#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk    (0x1UL << DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos) /*!< 0x00400000 */
+#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT        DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk 
+#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Pos    (23U)                     
+#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Msk    (0x1UL << DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Pos) /*!< 0x00800000 */
+#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT        DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Msk 
+#define DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT_Pos    (24U)                     
+#define DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT_Msk    (0x1UL << DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT_Pos) /*!< 0x01000000 */
+#define DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT        DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT_Msk 
+#define DBGMCU_APB1_FZ_DBG_CAN1_STOP_Pos             (25U)                     
+#define DBGMCU_APB1_FZ_DBG_CAN1_STOP_Msk             (0x1UL << DBGMCU_APB1_FZ_DBG_CAN1_STOP_Pos) /*!< 0x02000000 */
+#define DBGMCU_APB1_FZ_DBG_CAN1_STOP                 DBGMCU_APB1_FZ_DBG_CAN1_STOP_Msk 
+#define DBGMCU_APB1_FZ_DBG_CAN2_STOP_Pos             (26U)                     
+#define DBGMCU_APB1_FZ_DBG_CAN2_STOP_Msk             (0x1UL << DBGMCU_APB1_FZ_DBG_CAN2_STOP_Pos) /*!< 0x04000000 */
+#define DBGMCU_APB1_FZ_DBG_CAN2_STOP                 DBGMCU_APB1_FZ_DBG_CAN2_STOP_Msk 
+/* Old IWDGSTOP bit definition, maintained for legacy purpose */
+#define  DBGMCU_APB1_FZ_DBG_IWDEG_STOP           DBGMCU_APB1_FZ_DBG_IWDG_STOP
+
+/********************  Bit definition for DBGMCU_APB2_FZ register  ************/
+#define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos             (0U)                      
+#define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk             (0x1UL << DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos) /*!< 0x00000001 */
+#define DBGMCU_APB2_FZ_DBG_TIM1_STOP                 DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk 
+#define DBGMCU_APB2_FZ_DBG_TIM8_STOP_Pos             (1U)                      
+#define DBGMCU_APB2_FZ_DBG_TIM8_STOP_Msk             (0x1UL << DBGMCU_APB2_FZ_DBG_TIM8_STOP_Pos) /*!< 0x00000002 */
+#define DBGMCU_APB2_FZ_DBG_TIM8_STOP                 DBGMCU_APB2_FZ_DBG_TIM8_STOP_Msk 
+#define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos             (16U)                     
+#define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk             (0x1UL << DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos) /*!< 0x00010000 */
+#define DBGMCU_APB2_FZ_DBG_TIM9_STOP                 DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk 
+#define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos            (17U)                     
+#define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk            (0x1UL << DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos) /*!< 0x00020000 */
+#define DBGMCU_APB2_FZ_DBG_TIM10_STOP                DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk 
+#define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos            (18U)                     
+#define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk            (0x1UL << DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos) /*!< 0x00040000 */
+#define DBGMCU_APB2_FZ_DBG_TIM11_STOP                DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk 
+
+/******************************************************************************/
+/*                                                                            */
+/*                Ethernet MAC Registers bits definitions                     */
+/*                                                                            */
+/******************************************************************************/
+/* Bit definition for Ethernet MAC Control Register register */
+#define ETH_MACCR_WD_Pos                              (23U)                    
+#define ETH_MACCR_WD_Msk                              (0x1UL << ETH_MACCR_WD_Pos) /*!< 0x00800000 */
+#define ETH_MACCR_WD                                  ETH_MACCR_WD_Msk         /* Watchdog disable */
+#define ETH_MACCR_JD_Pos                              (22U)                    
+#define ETH_MACCR_JD_Msk                              (0x1UL << ETH_MACCR_JD_Pos) /*!< 0x00400000 */
+#define ETH_MACCR_JD                                  ETH_MACCR_JD_Msk         /* Jabber disable */
+#define ETH_MACCR_IFG_Pos                             (17U)                    
+#define ETH_MACCR_IFG_Msk                             (0x7UL << ETH_MACCR_IFG_Pos) /*!< 0x000E0000 */
+#define ETH_MACCR_IFG                                 ETH_MACCR_IFG_Msk        /* Inter-frame gap */
+#define ETH_MACCR_IFG_96Bit                           0x00000000U              /* Minimum IFG between frames during transmission is 96Bit */
+#define ETH_MACCR_IFG_88Bit                           0x00020000U              /* Minimum IFG between frames during transmission is 88Bit */
+#define ETH_MACCR_IFG_80Bit                           0x00040000U              /* Minimum IFG between frames during transmission is 80Bit */
+#define ETH_MACCR_IFG_72Bit                           0x00060000U              /* Minimum IFG between frames during transmission is 72Bit */
+#define ETH_MACCR_IFG_64Bit                           0x00080000U              /* Minimum IFG between frames during transmission is 64Bit */
+#define ETH_MACCR_IFG_56Bit                           0x000A0000U              /* Minimum IFG between frames during transmission is 56Bit */
+#define ETH_MACCR_IFG_48Bit                           0x000C0000U              /* Minimum IFG between frames during transmission is 48Bit */
+#define ETH_MACCR_IFG_40Bit                           0x000E0000U              /* Minimum IFG between frames during transmission is 40Bit */
+#define ETH_MACCR_CSD_Pos                             (16U)                    
+#define ETH_MACCR_CSD_Msk                             (0x1UL << ETH_MACCR_CSD_Pos) /*!< 0x00010000 */
+#define ETH_MACCR_CSD                                 ETH_MACCR_CSD_Msk        /* Carrier sense disable (during transmission) */
+#define ETH_MACCR_FES_Pos                             (14U)                    
+#define ETH_MACCR_FES_Msk                             (0x1UL << ETH_MACCR_FES_Pos) /*!< 0x00004000 */
+#define ETH_MACCR_FES                                 ETH_MACCR_FES_Msk        /* Fast ethernet speed */
+#define ETH_MACCR_ROD_Pos                             (13U)                    
+#define ETH_MACCR_ROD_Msk                             (0x1UL << ETH_MACCR_ROD_Pos) /*!< 0x00002000 */
+#define ETH_MACCR_ROD                                 ETH_MACCR_ROD_Msk        /* Receive own disable */
+#define ETH_MACCR_LM_Pos                              (12U)                    
+#define ETH_MACCR_LM_Msk                              (0x1UL << ETH_MACCR_LM_Pos) /*!< 0x00001000 */
+#define ETH_MACCR_LM                                  ETH_MACCR_LM_Msk         /* loopback mode */
+#define ETH_MACCR_DM_Pos                              (11U)                    
+#define ETH_MACCR_DM_Msk                              (0x1UL << ETH_MACCR_DM_Pos) /*!< 0x00000800 */
+#define ETH_MACCR_DM                                  ETH_MACCR_DM_Msk         /* Duplex mode */
+#define ETH_MACCR_IPCO_Pos                            (10U)                    
+#define ETH_MACCR_IPCO_Msk                            (0x1UL << ETH_MACCR_IPCO_Pos) /*!< 0x00000400 */
+#define ETH_MACCR_IPCO                                ETH_MACCR_IPCO_Msk       /* IP Checksum offload */
+#define ETH_MACCR_RD_Pos                              (9U)                     
+#define ETH_MACCR_RD_Msk                              (0x1UL << ETH_MACCR_RD_Pos) /*!< 0x00000200 */
+#define ETH_MACCR_RD                                  ETH_MACCR_RD_Msk         /* Retry disable */
+#define ETH_MACCR_APCS_Pos                            (7U)                     
+#define ETH_MACCR_APCS_Msk                            (0x1UL << ETH_MACCR_APCS_Pos) /*!< 0x00000080 */
+#define ETH_MACCR_APCS                                ETH_MACCR_APCS_Msk       /* Automatic Pad/CRC stripping */
+#define ETH_MACCR_BL_Pos                              (5U)                     
+#define ETH_MACCR_BL_Msk                              (0x3UL << ETH_MACCR_BL_Pos) /*!< 0x00000060 */
+#define ETH_MACCR_BL                                  ETH_MACCR_BL_Msk         /* Back-off limit: random integer number (r) of slot time delays before rescheduling
+                                                       a transmission attempt during retries after a collision: 0 =< r <2^k */
+#define ETH_MACCR_BL_10                               0x00000000U              /* k = min (n, 10) */
+#define ETH_MACCR_BL_8                                0x00000020U              /* k = min (n, 8) */
+#define ETH_MACCR_BL_4                                0x00000040U              /* k = min (n, 4) */
+#define ETH_MACCR_BL_1                                0x00000060U              /* k = min (n, 1) */ 
+#define ETH_MACCR_DC_Pos                              (4U)                     
+#define ETH_MACCR_DC_Msk                              (0x1UL << ETH_MACCR_DC_Pos) /*!< 0x00000010 */
+#define ETH_MACCR_DC                                  ETH_MACCR_DC_Msk         /* Defferal check */
+#define ETH_MACCR_TE_Pos                              (3U)                     
+#define ETH_MACCR_TE_Msk                              (0x1UL << ETH_MACCR_TE_Pos) /*!< 0x00000008 */
+#define ETH_MACCR_TE                                  ETH_MACCR_TE_Msk         /* Transmitter enable */
+#define ETH_MACCR_RE_Pos                              (2U)                     
+#define ETH_MACCR_RE_Msk                              (0x1UL << ETH_MACCR_RE_Pos) /*!< 0x00000004 */
+#define ETH_MACCR_RE                                  ETH_MACCR_RE_Msk         /* Receiver enable */
+
+/* Bit definition for Ethernet MAC Frame Filter Register */
+#define ETH_MACFFR_RA_Pos                             (31U)                    
+#define ETH_MACFFR_RA_Msk                             (0x1UL << ETH_MACFFR_RA_Pos) /*!< 0x80000000 */
+#define ETH_MACFFR_RA                                 ETH_MACFFR_RA_Msk        /* Receive all */
+#define ETH_MACFFR_HPF_Pos                            (10U)                    
+#define ETH_MACFFR_HPF_Msk                            (0x1UL << ETH_MACFFR_HPF_Pos) /*!< 0x00000400 */
+#define ETH_MACFFR_HPF                                ETH_MACFFR_HPF_Msk       /* Hash or perfect filter */
+#define ETH_MACFFR_SAF_Pos                            (9U)                     
+#define ETH_MACFFR_SAF_Msk                            (0x1UL << ETH_MACFFR_SAF_Pos) /*!< 0x00000200 */
+#define ETH_MACFFR_SAF                                ETH_MACFFR_SAF_Msk       /* Source address filter enable */
+#define ETH_MACFFR_SAIF_Pos                           (8U)                     
+#define ETH_MACFFR_SAIF_Msk                           (0x1UL << ETH_MACFFR_SAIF_Pos) /*!< 0x00000100 */
+#define ETH_MACFFR_SAIF                               ETH_MACFFR_SAIF_Msk      /* SA inverse filtering */ 
+#define ETH_MACFFR_PCF_Pos                            (6U)                     
+#define ETH_MACFFR_PCF_Msk                            (0x3UL << ETH_MACFFR_PCF_Pos) /*!< 0x000000C0 */
+#define ETH_MACFFR_PCF                                ETH_MACFFR_PCF_Msk       /* Pass control frames: 3 cases */
+#define ETH_MACFFR_PCF_BlockAll_Pos                   (6U)                     
+#define ETH_MACFFR_PCF_BlockAll_Msk                   (0x1UL << ETH_MACFFR_PCF_BlockAll_Pos) /*!< 0x00000040 */
+#define ETH_MACFFR_PCF_BlockAll                       ETH_MACFFR_PCF_BlockAll_Msk /* MAC filters all control frames from reaching the application */
+#define ETH_MACFFR_PCF_ForwardAll_Pos                 (7U)                     
+#define ETH_MACFFR_PCF_ForwardAll_Msk                 (0x1UL << ETH_MACFFR_PCF_ForwardAll_Pos) /*!< 0x00000080 */
+#define ETH_MACFFR_PCF_ForwardAll                     ETH_MACFFR_PCF_ForwardAll_Msk /* MAC forwards all control frames to application even if they fail the Address Filter */
+#define ETH_MACFFR_PCF_ForwardPassedAddrFilter_Pos    (6U)                     
+#define ETH_MACFFR_PCF_ForwardPassedAddrFilter_Msk    (0x3UL << ETH_MACFFR_PCF_ForwardPassedAddrFilter_Pos) /*!< 0x000000C0 */
+#define ETH_MACFFR_PCF_ForwardPassedAddrFilter        ETH_MACFFR_PCF_ForwardPassedAddrFilter_Msk /* MAC forwards control frames that pass the Address Filter. */ 
+#define ETH_MACFFR_BFD_Pos                            (5U)                     
+#define ETH_MACFFR_BFD_Msk                            (0x1UL << ETH_MACFFR_BFD_Pos) /*!< 0x00000020 */
+#define ETH_MACFFR_BFD                                ETH_MACFFR_BFD_Msk       /* Broadcast frame disable */ 
+#define ETH_MACFFR_PAM_Pos                            (4U)                     
+#define ETH_MACFFR_PAM_Msk                            (0x1UL << ETH_MACFFR_PAM_Pos) /*!< 0x00000010 */
+#define ETH_MACFFR_PAM                                ETH_MACFFR_PAM_Msk       /* Pass all mutlicast */
+#define ETH_MACFFR_DAIF_Pos                           (3U)                     
+#define ETH_MACFFR_DAIF_Msk                           (0x1UL << ETH_MACFFR_DAIF_Pos) /*!< 0x00000008 */
+#define ETH_MACFFR_DAIF                               ETH_MACFFR_DAIF_Msk      /* DA Inverse filtering */
+#define ETH_MACFFR_HM_Pos                             (2U)                     
+#define ETH_MACFFR_HM_Msk                             (0x1UL << ETH_MACFFR_HM_Pos) /*!< 0x00000004 */
+#define ETH_MACFFR_HM                                 ETH_MACFFR_HM_Msk        /* Hash multicast */ 
+#define ETH_MACFFR_HU_Pos                             (1U)                     
+#define ETH_MACFFR_HU_Msk                             (0x1UL << ETH_MACFFR_HU_Pos) /*!< 0x00000002 */
+#define ETH_MACFFR_HU                                 ETH_MACFFR_HU_Msk        /* Hash unicast */
+#define ETH_MACFFR_PM_Pos                             (0U)                     
+#define ETH_MACFFR_PM_Msk                             (0x1UL << ETH_MACFFR_PM_Pos) /*!< 0x00000001 */
+#define ETH_MACFFR_PM                                 ETH_MACFFR_PM_Msk        /* Promiscuous mode */
+
+/* Bit definition for Ethernet MAC Hash Table High Register */
+#define ETH_MACHTHR_HTH_Pos                           (0U)                     
+#define ETH_MACHTHR_HTH_Msk                           (0xFFFFFFFFUL << ETH_MACHTHR_HTH_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACHTHR_HTH                               ETH_MACHTHR_HTH_Msk      /* Hash table high */
+
+/* Bit definition for Ethernet MAC Hash Table Low Register */
+#define ETH_MACHTLR_HTL_Pos                           (0U)                     
+#define ETH_MACHTLR_HTL_Msk                           (0xFFFFFFFFUL << ETH_MACHTLR_HTL_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACHTLR_HTL                               ETH_MACHTLR_HTL_Msk      /* Hash table low */
+
+/* Bit definition for Ethernet MAC MII Address Register */
+#define ETH_MACMIIAR_PA_Pos                           (11U)                    
+#define ETH_MACMIIAR_PA_Msk                           (0x1FUL << ETH_MACMIIAR_PA_Pos) /*!< 0x0000F800 */
+#define ETH_MACMIIAR_PA                               ETH_MACMIIAR_PA_Msk      /* Physical layer address */
+#define ETH_MACMIIAR_MR_Pos                           (6U)                     
+#define ETH_MACMIIAR_MR_Msk                           (0x1FUL << ETH_MACMIIAR_MR_Pos) /*!< 0x000007C0 */
+#define ETH_MACMIIAR_MR                               ETH_MACMIIAR_MR_Msk      /* MII register in the selected PHY */
+#define ETH_MACMIIAR_CR_Pos                           (2U)                     
+#define ETH_MACMIIAR_CR_Msk                           (0x7UL << ETH_MACMIIAR_CR_Pos) /*!< 0x0000001C */
+#define ETH_MACMIIAR_CR                               ETH_MACMIIAR_CR_Msk      /* CR clock range: 6 cases */
+#define ETH_MACMIIAR_CR_Div42                         0x00000000U              /* HCLK:60-100 MHz; MDC clock= HCLK/42   */
+#define ETH_MACMIIAR_CR_Div62_Pos                     (2U)                     
+#define ETH_MACMIIAR_CR_Div62_Msk                     (0x1UL << ETH_MACMIIAR_CR_Div62_Pos) /*!< 0x00000004 */
+#define ETH_MACMIIAR_CR_Div62                         ETH_MACMIIAR_CR_Div62_Msk /* HCLK:100-150 MHz; MDC clock= HCLK/62  */
+#define ETH_MACMIIAR_CR_Div16_Pos                     (3U)                     
+#define ETH_MACMIIAR_CR_Div16_Msk                     (0x1UL << ETH_MACMIIAR_CR_Div16_Pos) /*!< 0x00000008 */
+#define ETH_MACMIIAR_CR_Div16                         ETH_MACMIIAR_CR_Div16_Msk /* HCLK:20-35 MHz; MDC clock= HCLK/16    */
+#define ETH_MACMIIAR_CR_Div26_Pos                     (2U)                     
+#define ETH_MACMIIAR_CR_Div26_Msk                     (0x3UL << ETH_MACMIIAR_CR_Div26_Pos) /*!< 0x0000000C */
+#define ETH_MACMIIAR_CR_Div26                         ETH_MACMIIAR_CR_Div26_Msk /* HCLK:35-60 MHz; MDC clock= HCLK/26    */
+#define ETH_MACMIIAR_CR_Div102_Pos                    (4U)                     
+#define ETH_MACMIIAR_CR_Div102_Msk                    (0x1UL << ETH_MACMIIAR_CR_Div102_Pos) /*!< 0x00000010 */
+#define ETH_MACMIIAR_CR_Div102                        ETH_MACMIIAR_CR_Div102_Msk /* HCLK:150-168 MHz; MDC clock= HCLK/102 */
+#define ETH_MACMIIAR_MW_Pos                           (1U)                     
+#define ETH_MACMIIAR_MW_Msk                           (0x1UL << ETH_MACMIIAR_MW_Pos) /*!< 0x00000002 */
+#define ETH_MACMIIAR_MW                               ETH_MACMIIAR_MW_Msk      /* MII write */
+#define ETH_MACMIIAR_MB_Pos                           (0U)                     
+#define ETH_MACMIIAR_MB_Msk                           (0x1UL << ETH_MACMIIAR_MB_Pos) /*!< 0x00000001 */
+#define ETH_MACMIIAR_MB                               ETH_MACMIIAR_MB_Msk      /* MII busy  */
+
+/* Bit definition for Ethernet MAC MII Data Register */
+#define ETH_MACMIIDR_MD_Pos                           (0U)                     
+#define ETH_MACMIIDR_MD_Msk                           (0xFFFFUL << ETH_MACMIIDR_MD_Pos) /*!< 0x0000FFFF */
+#define ETH_MACMIIDR_MD                               ETH_MACMIIDR_MD_Msk      /* MII data: read/write data from/to PHY */
+
+/* Bit definition for Ethernet MAC Flow Control Register */
+#define ETH_MACFCR_PT_Pos                             (16U)                    
+#define ETH_MACFCR_PT_Msk                             (0xFFFFUL << ETH_MACFCR_PT_Pos) /*!< 0xFFFF0000 */
+#define ETH_MACFCR_PT                                 ETH_MACFCR_PT_Msk        /* Pause time */
+#define ETH_MACFCR_ZQPD_Pos                           (7U)                     
+#define ETH_MACFCR_ZQPD_Msk                           (0x1UL << ETH_MACFCR_ZQPD_Pos) /*!< 0x00000080 */
+#define ETH_MACFCR_ZQPD                               ETH_MACFCR_ZQPD_Msk      /* Zero-quanta pause disable */
+#define ETH_MACFCR_PLT_Pos                            (4U)                     
+#define ETH_MACFCR_PLT_Msk                            (0x3UL << ETH_MACFCR_PLT_Pos) /*!< 0x00000030 */
+#define ETH_MACFCR_PLT                                ETH_MACFCR_PLT_Msk       /* Pause low threshold: 4 cases */
+#define ETH_MACFCR_PLT_Minus4                         0x00000000U              /* Pause time minus 4 slot times   */
+#define ETH_MACFCR_PLT_Minus28_Pos                    (4U)                     
+#define ETH_MACFCR_PLT_Minus28_Msk                    (0x1UL << ETH_MACFCR_PLT_Minus28_Pos) /*!< 0x00000010 */
+#define ETH_MACFCR_PLT_Minus28                        ETH_MACFCR_PLT_Minus28_Msk /* Pause time minus 28 slot times  */
+#define ETH_MACFCR_PLT_Minus144_Pos                   (5U)                     
+#define ETH_MACFCR_PLT_Minus144_Msk                   (0x1UL << ETH_MACFCR_PLT_Minus144_Pos) /*!< 0x00000020 */
+#define ETH_MACFCR_PLT_Minus144                       ETH_MACFCR_PLT_Minus144_Msk /* Pause time minus 144 slot times */
+#define ETH_MACFCR_PLT_Minus256_Pos                   (4U)                     
+#define ETH_MACFCR_PLT_Minus256_Msk                   (0x3UL << ETH_MACFCR_PLT_Minus256_Pos) /*!< 0x00000030 */
+#define ETH_MACFCR_PLT_Minus256                       ETH_MACFCR_PLT_Minus256_Msk /* Pause time minus 256 slot times */
+#define ETH_MACFCR_UPFD_Pos                           (3U)                     
+#define ETH_MACFCR_UPFD_Msk                           (0x1UL << ETH_MACFCR_UPFD_Pos) /*!< 0x00000008 */
+#define ETH_MACFCR_UPFD                               ETH_MACFCR_UPFD_Msk      /* Unicast pause frame detect */
+#define ETH_MACFCR_RFCE_Pos                           (2U)                     
+#define ETH_MACFCR_RFCE_Msk                           (0x1UL << ETH_MACFCR_RFCE_Pos) /*!< 0x00000004 */
+#define ETH_MACFCR_RFCE                               ETH_MACFCR_RFCE_Msk      /* Receive flow control enable */
+#define ETH_MACFCR_TFCE_Pos                           (1U)                     
+#define ETH_MACFCR_TFCE_Msk                           (0x1UL << ETH_MACFCR_TFCE_Pos) /*!< 0x00000002 */
+#define ETH_MACFCR_TFCE                               ETH_MACFCR_TFCE_Msk      /* Transmit flow control enable */
+#define ETH_MACFCR_FCBBPA_Pos                         (0U)                     
+#define ETH_MACFCR_FCBBPA_Msk                         (0x1UL << ETH_MACFCR_FCBBPA_Pos) /*!< 0x00000001 */
+#define ETH_MACFCR_FCBBPA                             ETH_MACFCR_FCBBPA_Msk    /* Flow control busy/backpressure activate */
+
+/* Bit definition for Ethernet MAC VLAN Tag Register */
+#define ETH_MACVLANTR_VLANTC_Pos                      (16U)                    
+#define ETH_MACVLANTR_VLANTC_Msk                      (0x1UL << ETH_MACVLANTR_VLANTC_Pos) /*!< 0x00010000 */
+#define ETH_MACVLANTR_VLANTC                          ETH_MACVLANTR_VLANTC_Msk /* 12-bit VLAN tag comparison */
+#define ETH_MACVLANTR_VLANTI_Pos                      (0U)                     
+#define ETH_MACVLANTR_VLANTI_Msk                      (0xFFFFUL << ETH_MACVLANTR_VLANTI_Pos) /*!< 0x0000FFFF */
+#define ETH_MACVLANTR_VLANTI                          ETH_MACVLANTR_VLANTI_Msk /* VLAN tag identifier (for receive frames) */
+
+/* Bit definition for Ethernet MAC Remote Wake-UpFrame Filter Register */ 
+#define ETH_MACRWUFFR_D_Pos                           (0U)                     
+#define ETH_MACRWUFFR_D_Msk                           (0xFFFFFFFFUL << ETH_MACRWUFFR_D_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACRWUFFR_D                               ETH_MACRWUFFR_D_Msk      /* Wake-up frame filter register data */
+/* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers.
+   Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */
+/* Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask
+   Wake-UpFrame Filter Reg1 : Filter 1 Byte Mask
+   Wake-UpFrame Filter Reg2 : Filter 2 Byte Mask
+   Wake-UpFrame Filter Reg3 : Filter 3 Byte Mask
+   Wake-UpFrame Filter Reg4 : RSVD - Filter3 Command - RSVD - Filter2 Command - 
+                              RSVD - Filter1 Command - RSVD - Filter0 Command
+   Wake-UpFrame Filter Re5 : Filter3 Offset - Filter2 Offset - Filter1 Offset - Filter0 Offset
+   Wake-UpFrame Filter Re6 : Filter1 CRC16 - Filter0 CRC16
+   Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */
+
+/* Bit definition for Ethernet MAC PMT Control and Status Register */ 
+#define ETH_MACPMTCSR_WFFRPR_Pos                      (31U)                    
+#define ETH_MACPMTCSR_WFFRPR_Msk                      (0x1UL << ETH_MACPMTCSR_WFFRPR_Pos) /*!< 0x80000000 */
+#define ETH_MACPMTCSR_WFFRPR                          ETH_MACPMTCSR_WFFRPR_Msk /* Wake-Up Frame Filter Register Pointer Reset */
+#define ETH_MACPMTCSR_GU_Pos                          (9U)                     
+#define ETH_MACPMTCSR_GU_Msk                          (0x1UL << ETH_MACPMTCSR_GU_Pos) /*!< 0x00000200 */
+#define ETH_MACPMTCSR_GU                              ETH_MACPMTCSR_GU_Msk     /* Global Unicast                              */
+#define ETH_MACPMTCSR_WFR_Pos                         (6U)                     
+#define ETH_MACPMTCSR_WFR_Msk                         (0x1UL << ETH_MACPMTCSR_WFR_Pos) /*!< 0x00000040 */
+#define ETH_MACPMTCSR_WFR                             ETH_MACPMTCSR_WFR_Msk    /* Wake-Up Frame Received                      */
+#define ETH_MACPMTCSR_MPR_Pos                         (5U)                     
+#define ETH_MACPMTCSR_MPR_Msk                         (0x1UL << ETH_MACPMTCSR_MPR_Pos) /*!< 0x00000020 */
+#define ETH_MACPMTCSR_MPR                             ETH_MACPMTCSR_MPR_Msk    /* Magic Packet Received                       */
+#define ETH_MACPMTCSR_WFE_Pos                         (2U)                     
+#define ETH_MACPMTCSR_WFE_Msk                         (0x1UL << ETH_MACPMTCSR_WFE_Pos) /*!< 0x00000004 */
+#define ETH_MACPMTCSR_WFE                             ETH_MACPMTCSR_WFE_Msk    /* Wake-Up Frame Enable                        */
+#define ETH_MACPMTCSR_MPE_Pos                         (1U)                     
+#define ETH_MACPMTCSR_MPE_Msk                         (0x1UL << ETH_MACPMTCSR_MPE_Pos) /*!< 0x00000002 */
+#define ETH_MACPMTCSR_MPE                             ETH_MACPMTCSR_MPE_Msk    /* Magic Packet Enable                         */
+#define ETH_MACPMTCSR_PD_Pos                          (0U)                     
+#define ETH_MACPMTCSR_PD_Msk                          (0x1UL << ETH_MACPMTCSR_PD_Pos) /*!< 0x00000001 */
+#define ETH_MACPMTCSR_PD                              ETH_MACPMTCSR_PD_Msk     /* Power Down                                  */
+
+/* Bit definition for Ethernet MAC debug Register */
+#define ETH_MACDBGR_TFF_Pos                           (25U)                    
+#define ETH_MACDBGR_TFF_Msk                           (0x1UL << ETH_MACDBGR_TFF_Pos) /*!< 0x02000000 */
+#define ETH_MACDBGR_TFF                               ETH_MACDBGR_TFF_Msk      /* Tx FIFO full                                                            */
+#define ETH_MACDBGR_TFNE_Pos                          (24U)                    
+#define ETH_MACDBGR_TFNE_Msk                          (0x1UL << ETH_MACDBGR_TFNE_Pos) /*!< 0x01000000 */
+#define ETH_MACDBGR_TFNE                              ETH_MACDBGR_TFNE_Msk     /* Tx FIFO not empty                                                       */
+#define ETH_MACDBGR_TFWA_Pos                          (22U)                    
+#define ETH_MACDBGR_TFWA_Msk                          (0x1UL << ETH_MACDBGR_TFWA_Pos) /*!< 0x00400000 */
+#define ETH_MACDBGR_TFWA                              ETH_MACDBGR_TFWA_Msk     /* Tx FIFO write active                                                    */
+#define ETH_MACDBGR_TFRS_Pos                          (20U)                    
+#define ETH_MACDBGR_TFRS_Msk                          (0x3UL << ETH_MACDBGR_TFRS_Pos) /*!< 0x00300000 */
+#define ETH_MACDBGR_TFRS                              ETH_MACDBGR_TFRS_Msk     /* Tx FIFO read status mask                                                */
+#define ETH_MACDBGR_TFRS_WRITING_Pos                  (20U)                    
+#define ETH_MACDBGR_TFRS_WRITING_Msk                  (0x3UL << ETH_MACDBGR_TFRS_WRITING_Pos) /*!< 0x00300000 */
+#define ETH_MACDBGR_TFRS_WRITING                      ETH_MACDBGR_TFRS_WRITING_Msk /* Writing the received TxStatus or flushing the TxFIFO                    */
+#define ETH_MACDBGR_TFRS_WAITING_Pos                  (21U)                    
+#define ETH_MACDBGR_TFRS_WAITING_Msk                  (0x1UL << ETH_MACDBGR_TFRS_WAITING_Pos) /*!< 0x00200000 */
+#define ETH_MACDBGR_TFRS_WAITING                      ETH_MACDBGR_TFRS_WAITING_Msk /* Waiting for TxStatus from MAC transmitter                               */
+#define ETH_MACDBGR_TFRS_READ_Pos                     (20U)                    
+#define ETH_MACDBGR_TFRS_READ_Msk                     (0x1UL << ETH_MACDBGR_TFRS_READ_Pos) /*!< 0x00100000 */
+#define ETH_MACDBGR_TFRS_READ                         ETH_MACDBGR_TFRS_READ_Msk /* Read state (transferring data to the MAC transmitter)                   */
+#define ETH_MACDBGR_TFRS_IDLE                         0x00000000U              /* Idle state                                                              */
+#define ETH_MACDBGR_MTP_Pos                           (19U)                    
+#define ETH_MACDBGR_MTP_Msk                           (0x1UL << ETH_MACDBGR_MTP_Pos) /*!< 0x00080000 */
+#define ETH_MACDBGR_MTP                               ETH_MACDBGR_MTP_Msk      /* MAC transmitter in pause                                                */
+#define ETH_MACDBGR_MTFCS_Pos                         (17U)                    
+#define ETH_MACDBGR_MTFCS_Msk                         (0x3UL << ETH_MACDBGR_MTFCS_Pos) /*!< 0x00060000 */
+#define ETH_MACDBGR_MTFCS                             ETH_MACDBGR_MTFCS_Msk    /* MAC transmit frame controller status mask                               */
+#define ETH_MACDBGR_MTFCS_TRANSFERRING_Pos            (17U)                    
+#define ETH_MACDBGR_MTFCS_TRANSFERRING_Msk            (0x3UL << ETH_MACDBGR_MTFCS_TRANSFERRING_Pos) /*!< 0x00060000 */
+#define ETH_MACDBGR_MTFCS_TRANSFERRING                ETH_MACDBGR_MTFCS_TRANSFERRING_Msk /* Transferring input frame for transmission                               */
+#define ETH_MACDBGR_MTFCS_GENERATINGPCF_Pos           (18U)                    
+#define ETH_MACDBGR_MTFCS_GENERATINGPCF_Msk           (0x1UL << ETH_MACDBGR_MTFCS_GENERATINGPCF_Pos) /*!< 0x00040000 */
+#define ETH_MACDBGR_MTFCS_GENERATINGPCF               ETH_MACDBGR_MTFCS_GENERATINGPCF_Msk /* Generating and transmitting a Pause control frame (in full duplex mode) */
+#define ETH_MACDBGR_MTFCS_WAITING_Pos                 (17U)                    
+#define ETH_MACDBGR_MTFCS_WAITING_Msk                 (0x1UL << ETH_MACDBGR_MTFCS_WAITING_Pos) /*!< 0x00020000 */
+#define ETH_MACDBGR_MTFCS_WAITING                     ETH_MACDBGR_MTFCS_WAITING_Msk /* Waiting for Status of previous frame or IFG/backoff period to be over   */
+#define ETH_MACDBGR_MTFCS_IDLE                        0x00000000U              /* Idle                                                                    */
+#define ETH_MACDBGR_MMTEA_Pos                         (16U)                    
+#define ETH_MACDBGR_MMTEA_Msk                         (0x1UL << ETH_MACDBGR_MMTEA_Pos) /*!< 0x00010000 */
+#define ETH_MACDBGR_MMTEA                             ETH_MACDBGR_MMTEA_Msk    /* MAC MII transmit engine active                                          */
+#define ETH_MACDBGR_RFFL_Pos                          (8U)                     
+#define ETH_MACDBGR_RFFL_Msk                          (0x3UL << ETH_MACDBGR_RFFL_Pos) /*!< 0x00000300 */
+#define ETH_MACDBGR_RFFL                              ETH_MACDBGR_RFFL_Msk     /* Rx FIFO fill level mask                                                 */
+#define ETH_MACDBGR_RFFL_FULL_Pos                     (8U)                     
+#define ETH_MACDBGR_RFFL_FULL_Msk                     (0x3UL << ETH_MACDBGR_RFFL_FULL_Pos) /*!< 0x00000300 */
+#define ETH_MACDBGR_RFFL_FULL                         ETH_MACDBGR_RFFL_FULL_Msk /* RxFIFO full                                                             */
+#define ETH_MACDBGR_RFFL_ABOVEFCT_Pos                 (9U)                     
+#define ETH_MACDBGR_RFFL_ABOVEFCT_Msk                 (0x1UL << ETH_MACDBGR_RFFL_ABOVEFCT_Pos) /*!< 0x00000200 */
+#define ETH_MACDBGR_RFFL_ABOVEFCT                     ETH_MACDBGR_RFFL_ABOVEFCT_Msk /* RxFIFO fill-level above flow-control activate threshold                 */
+#define ETH_MACDBGR_RFFL_BELOWFCT_Pos                 (8U)                     
+#define ETH_MACDBGR_RFFL_BELOWFCT_Msk                 (0x1UL << ETH_MACDBGR_RFFL_BELOWFCT_Pos) /*!< 0x00000100 */
+#define ETH_MACDBGR_RFFL_BELOWFCT                     ETH_MACDBGR_RFFL_BELOWFCT_Msk /* RxFIFO fill-level below flow-control de-activate threshold              */
+#define ETH_MACDBGR_RFFL_EMPTY                        0x00000000U              /* RxFIFO empty                                                            */
+#define ETH_MACDBGR_RFRCS_Pos                         (5U)                     
+#define ETH_MACDBGR_RFRCS_Msk                         (0x3UL << ETH_MACDBGR_RFRCS_Pos) /*!< 0x00000060 */
+#define ETH_MACDBGR_RFRCS                             ETH_MACDBGR_RFRCS_Msk    /* Rx FIFO read controller status mask                                     */
+#define ETH_MACDBGR_RFRCS_FLUSHING_Pos                (5U)                     
+#define ETH_MACDBGR_RFRCS_FLUSHING_Msk                (0x3UL << ETH_MACDBGR_RFRCS_FLUSHING_Pos) /*!< 0x00000060 */
+#define ETH_MACDBGR_RFRCS_FLUSHING                    ETH_MACDBGR_RFRCS_FLUSHING_Msk /* Flushing the frame data and status                                      */
+#define ETH_MACDBGR_RFRCS_STATUSREADING_Pos           (6U)                     
+#define ETH_MACDBGR_RFRCS_STATUSREADING_Msk           (0x1UL << ETH_MACDBGR_RFRCS_STATUSREADING_Pos) /*!< 0x00000040 */
+#define ETH_MACDBGR_RFRCS_STATUSREADING               ETH_MACDBGR_RFRCS_STATUSREADING_Msk /* Reading frame status (or time-stamp)                                    */
+#define ETH_MACDBGR_RFRCS_DATAREADING_Pos             (5U)                     
+#define ETH_MACDBGR_RFRCS_DATAREADING_Msk             (0x1UL << ETH_MACDBGR_RFRCS_DATAREADING_Pos) /*!< 0x00000020 */
+#define ETH_MACDBGR_RFRCS_DATAREADING                 ETH_MACDBGR_RFRCS_DATAREADING_Msk /* Reading frame data                                                      */
+#define ETH_MACDBGR_RFRCS_IDLE                        0x00000000U              /* IDLE state                                                              */
+#define ETH_MACDBGR_RFWRA_Pos                         (4U)                     
+#define ETH_MACDBGR_RFWRA_Msk                         (0x1UL << ETH_MACDBGR_RFWRA_Pos) /*!< 0x00000010 */
+#define ETH_MACDBGR_RFWRA                             ETH_MACDBGR_RFWRA_Msk    /* Rx FIFO write controller active                                         */
+#define ETH_MACDBGR_MSFRWCS_Pos                       (1U)                     
+#define ETH_MACDBGR_MSFRWCS_Msk                       (0x3UL << ETH_MACDBGR_MSFRWCS_Pos) /*!< 0x00000006 */
+#define ETH_MACDBGR_MSFRWCS                           ETH_MACDBGR_MSFRWCS_Msk  /* MAC small FIFO read / write controllers status  mask                    */
+#define ETH_MACDBGR_MSFRWCS_1                         (0x2UL << ETH_MACDBGR_MSFRWCS_Pos) /*!< 0x00000004 */
+#define ETH_MACDBGR_MSFRWCS_0                         (0x1UL << ETH_MACDBGR_MSFRWCS_Pos) /*!< 0x00000002 */
+#define ETH_MACDBGR_MMRPEA_Pos                        (0U)                     
+#define ETH_MACDBGR_MMRPEA_Msk                        (0x1UL << ETH_MACDBGR_MMRPEA_Pos) /*!< 0x00000001 */
+#define ETH_MACDBGR_MMRPEA                            ETH_MACDBGR_MMRPEA_Msk   /* MAC MII receive protocol engine active                                  */
+
+/* Bit definition for Ethernet MAC Status Register */
+#define ETH_MACSR_TSTS_Pos                            (9U)                     
+#define ETH_MACSR_TSTS_Msk                            (0x1UL << ETH_MACSR_TSTS_Pos) /*!< 0x00000200 */
+#define ETH_MACSR_TSTS                                ETH_MACSR_TSTS_Msk       /* Time stamp trigger status */
+#define ETH_MACSR_MMCTS_Pos                           (6U)                     
+#define ETH_MACSR_MMCTS_Msk                           (0x1UL << ETH_MACSR_MMCTS_Pos) /*!< 0x00000040 */
+#define ETH_MACSR_MMCTS                               ETH_MACSR_MMCTS_Msk      /* MMC transmit status       */
+#define ETH_MACSR_MMMCRS_Pos                          (5U)                     
+#define ETH_MACSR_MMMCRS_Msk                          (0x1UL << ETH_MACSR_MMMCRS_Pos) /*!< 0x00000020 */
+#define ETH_MACSR_MMMCRS                              ETH_MACSR_MMMCRS_Msk     /* MMC receive status        */
+#define ETH_MACSR_MMCS_Pos                            (4U)                     
+#define ETH_MACSR_MMCS_Msk                            (0x1UL << ETH_MACSR_MMCS_Pos) /*!< 0x00000010 */
+#define ETH_MACSR_MMCS                                ETH_MACSR_MMCS_Msk       /* MMC status                */
+#define ETH_MACSR_PMTS_Pos                            (3U)                     
+#define ETH_MACSR_PMTS_Msk                            (0x1UL << ETH_MACSR_PMTS_Pos) /*!< 0x00000008 */
+#define ETH_MACSR_PMTS                                ETH_MACSR_PMTS_Msk       /* PMT status                */
+
+/* Bit definition for Ethernet MAC Interrupt Mask Register */
+#define ETH_MACIMR_TSTIM_Pos                          (9U)                     
+#define ETH_MACIMR_TSTIM_Msk                          (0x1UL << ETH_MACIMR_TSTIM_Pos) /*!< 0x00000200 */
+#define ETH_MACIMR_TSTIM                              ETH_MACIMR_TSTIM_Msk     /* Time stamp trigger interrupt mask */
+#define ETH_MACIMR_PMTIM_Pos                          (3U)                     
+#define ETH_MACIMR_PMTIM_Msk                          (0x1UL << ETH_MACIMR_PMTIM_Pos) /*!< 0x00000008 */
+#define ETH_MACIMR_PMTIM                              ETH_MACIMR_PMTIM_Msk     /* PMT interrupt mask                */
+
+/* Bit definition for Ethernet MAC Address0 High Register */
+#define ETH_MACA0HR_MACA0H_Pos                        (0U)                     
+#define ETH_MACA0HR_MACA0H_Msk                        (0xFFFFUL << ETH_MACA0HR_MACA0H_Pos) /*!< 0x0000FFFF */
+#define ETH_MACA0HR_MACA0H                            ETH_MACA0HR_MACA0H_Msk   /* MAC address0 high */
+
+/* Bit definition for Ethernet MAC Address0 Low Register */
+#define ETH_MACA0LR_MACA0L_Pos                        (0U)                     
+#define ETH_MACA0LR_MACA0L_Msk                        (0xFFFFFFFFUL << ETH_MACA0LR_MACA0L_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACA0LR_MACA0L                            ETH_MACA0LR_MACA0L_Msk   /* MAC address0 low */
+
+/* Bit definition for Ethernet MAC Address1 High Register */
+#define ETH_MACA1HR_AE_Pos                            (31U)                    
+#define ETH_MACA1HR_AE_Msk                            (0x1UL << ETH_MACA1HR_AE_Pos) /*!< 0x80000000 */
+#define ETH_MACA1HR_AE                                ETH_MACA1HR_AE_Msk       /* Address enable */
+#define ETH_MACA1HR_SA_Pos                            (30U)                    
+#define ETH_MACA1HR_SA_Msk                            (0x1UL << ETH_MACA1HR_SA_Pos) /*!< 0x40000000 */
+#define ETH_MACA1HR_SA                                ETH_MACA1HR_SA_Msk       /* Source address */
+#define ETH_MACA1HR_MBC_Pos                           (24U)                    
+#define ETH_MACA1HR_MBC_Msk                           (0x3FUL << ETH_MACA1HR_MBC_Pos) /*!< 0x3F000000 */
+#define ETH_MACA1HR_MBC                               ETH_MACA1HR_MBC_Msk      /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
+#define ETH_MACA1HR_MBC_HBits15_8                     0x20000000U              /* Mask MAC Address high reg bits [15:8] */
+#define ETH_MACA1HR_MBC_HBits7_0                      0x10000000U              /* Mask MAC Address high reg bits [7:0]  */
+#define ETH_MACA1HR_MBC_LBits31_24                    0x08000000U              /* Mask MAC Address low reg bits [31:24] */
+#define ETH_MACA1HR_MBC_LBits23_16                    0x04000000U              /* Mask MAC Address low reg bits [23:16] */
+#define ETH_MACA1HR_MBC_LBits15_8                     0x02000000U              /* Mask MAC Address low reg bits [15:8]  */
+#define ETH_MACA1HR_MBC_LBits7_0                      0x01000000U              /* Mask MAC Address low reg bits [7:0]   */
+#define ETH_MACA1HR_MACA1H_Pos                        (0U)                     
+#define ETH_MACA1HR_MACA1H_Msk                        (0xFFFFUL << ETH_MACA1HR_MACA1H_Pos) /*!< 0x0000FFFF */
+#define ETH_MACA1HR_MACA1H                            ETH_MACA1HR_MACA1H_Msk   /* MAC address1 high */
+
+/* Bit definition for Ethernet MAC Address1 Low Register */
+#define ETH_MACA1LR_MACA1L_Pos                        (0U)                     
+#define ETH_MACA1LR_MACA1L_Msk                        (0xFFFFFFFFUL << ETH_MACA1LR_MACA1L_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACA1LR_MACA1L                            ETH_MACA1LR_MACA1L_Msk   /* MAC address1 low */
+
+/* Bit definition for Ethernet MAC Address2 High Register */
+#define ETH_MACA2HR_AE_Pos                            (31U)                    
+#define ETH_MACA2HR_AE_Msk                            (0x1UL << ETH_MACA2HR_AE_Pos) /*!< 0x80000000 */
+#define ETH_MACA2HR_AE                                ETH_MACA2HR_AE_Msk       /* Address enable */
+#define ETH_MACA2HR_SA_Pos                            (30U)                    
+#define ETH_MACA2HR_SA_Msk                            (0x1UL << ETH_MACA2HR_SA_Pos) /*!< 0x40000000 */
+#define ETH_MACA2HR_SA                                ETH_MACA2HR_SA_Msk       /* Source address */
+#define ETH_MACA2HR_MBC_Pos                           (24U)                    
+#define ETH_MACA2HR_MBC_Msk                           (0x3FUL << ETH_MACA2HR_MBC_Pos) /*!< 0x3F000000 */
+#define ETH_MACA2HR_MBC                               ETH_MACA2HR_MBC_Msk      /* Mask byte control */
+#define ETH_MACA2HR_MBC_HBits15_8                     0x20000000U              /* Mask MAC Address high reg bits [15:8] */
+#define ETH_MACA2HR_MBC_HBits7_0                      0x10000000U              /* Mask MAC Address high reg bits [7:0]  */
+#define ETH_MACA2HR_MBC_LBits31_24                    0x08000000U              /* Mask MAC Address low reg bits [31:24] */
+#define ETH_MACA2HR_MBC_LBits23_16                    0x04000000U              /* Mask MAC Address low reg bits [23:16] */
+#define ETH_MACA2HR_MBC_LBits15_8                     0x02000000U              /* Mask MAC Address low reg bits [15:8]  */
+#define ETH_MACA2HR_MBC_LBits7_0                      0x01000000U              /* Mask MAC Address low reg bits [70]    */
+#define ETH_MACA2HR_MACA2H_Pos                        (0U)                     
+#define ETH_MACA2HR_MACA2H_Msk                        (0xFFFFUL << ETH_MACA2HR_MACA2H_Pos) /*!< 0x0000FFFF */
+#define ETH_MACA2HR_MACA2H                            ETH_MACA2HR_MACA2H_Msk   /* MAC address1 high */
+
+/* Bit definition for Ethernet MAC Address2 Low Register */
+#define ETH_MACA2LR_MACA2L_Pos                        (0U)                     
+#define ETH_MACA2LR_MACA2L_Msk                        (0xFFFFFFFFUL << ETH_MACA2LR_MACA2L_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACA2LR_MACA2L                            ETH_MACA2LR_MACA2L_Msk   /* MAC address2 low */
+
+/* Bit definition for Ethernet MAC Address3 High Register */
+#define ETH_MACA3HR_AE_Pos                            (31U)                    
+#define ETH_MACA3HR_AE_Msk                            (0x1UL << ETH_MACA3HR_AE_Pos) /*!< 0x80000000 */
+#define ETH_MACA3HR_AE                                ETH_MACA3HR_AE_Msk       /* Address enable */
+#define ETH_MACA3HR_SA_Pos                            (30U)                    
+#define ETH_MACA3HR_SA_Msk                            (0x1UL << ETH_MACA3HR_SA_Pos) /*!< 0x40000000 */
+#define ETH_MACA3HR_SA                                ETH_MACA3HR_SA_Msk       /* Source address */
+#define ETH_MACA3HR_MBC_Pos                           (24U)                    
+#define ETH_MACA3HR_MBC_Msk                           (0x3FUL << ETH_MACA3HR_MBC_Pos) /*!< 0x3F000000 */
+#define ETH_MACA3HR_MBC                               ETH_MACA3HR_MBC_Msk      /* Mask byte control */
+#define ETH_MACA3HR_MBC_HBits15_8                     0x20000000U              /* Mask MAC Address high reg bits [15:8] */
+#define ETH_MACA3HR_MBC_HBits7_0                      0x10000000U              /* Mask MAC Address high reg bits [7:0]  */
+#define ETH_MACA3HR_MBC_LBits31_24                    0x08000000U              /* Mask MAC Address low reg bits [31:24] */
+#define ETH_MACA3HR_MBC_LBits23_16                    0x04000000U              /* Mask MAC Address low reg bits [23:16] */
+#define ETH_MACA3HR_MBC_LBits15_8                     0x02000000U              /* Mask MAC Address low reg bits [15:8]  */
+#define ETH_MACA3HR_MBC_LBits7_0                      0x01000000U              /* Mask MAC Address low reg bits [70]    */
+#define ETH_MACA3HR_MACA3H_Pos                        (0U)                     
+#define ETH_MACA3HR_MACA3H_Msk                        (0xFFFFUL << ETH_MACA3HR_MACA3H_Pos) /*!< 0x0000FFFF */
+#define ETH_MACA3HR_MACA3H                            ETH_MACA3HR_MACA3H_Msk   /* MAC address3 high */
+
+/* Bit definition for Ethernet MAC Address3 Low Register */
+#define ETH_MACA3LR_MACA3L_Pos                        (0U)                     
+#define ETH_MACA3LR_MACA3L_Msk                        (0xFFFFFFFFUL << ETH_MACA3LR_MACA3L_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACA3LR_MACA3L                            ETH_MACA3LR_MACA3L_Msk   /* MAC address3 low */
+
+/******************************************************************************/
+/*                Ethernet MMC Registers bits definition                      */
+/******************************************************************************/
+
+/* Bit definition for Ethernet MMC Control Register */
+#define ETH_MMCCR_MCFHP_Pos                           (5U)                     
+#define ETH_MMCCR_MCFHP_Msk                           (0x1UL << ETH_MMCCR_MCFHP_Pos) /*!< 0x00000020 */
+#define ETH_MMCCR_MCFHP                               ETH_MMCCR_MCFHP_Msk      /* MMC counter Full-Half preset */
+#define ETH_MMCCR_MCP_Pos                             (4U)                     
+#define ETH_MMCCR_MCP_Msk                             (0x1UL << ETH_MMCCR_MCP_Pos) /*!< 0x00000010 */
+#define ETH_MMCCR_MCP                                 ETH_MMCCR_MCP_Msk        /* MMC counter preset           */
+#define ETH_MMCCR_MCF_Pos                             (3U)                     
+#define ETH_MMCCR_MCF_Msk                             (0x1UL << ETH_MMCCR_MCF_Pos) /*!< 0x00000008 */
+#define ETH_MMCCR_MCF                                 ETH_MMCCR_MCF_Msk        /* MMC Counter Freeze           */
+#define ETH_MMCCR_ROR_Pos                             (2U)                     
+#define ETH_MMCCR_ROR_Msk                             (0x1UL << ETH_MMCCR_ROR_Pos) /*!< 0x00000004 */
+#define ETH_MMCCR_ROR                                 ETH_MMCCR_ROR_Msk        /* Reset on Read                */
+#define ETH_MMCCR_CSR_Pos                             (1U)                     
+#define ETH_MMCCR_CSR_Msk                             (0x1UL << ETH_MMCCR_CSR_Pos) /*!< 0x00000002 */
+#define ETH_MMCCR_CSR                                 ETH_MMCCR_CSR_Msk        /* Counter Stop Rollover        */
+#define ETH_MMCCR_CR_Pos                              (0U)                     
+#define ETH_MMCCR_CR_Msk                              (0x1UL << ETH_MMCCR_CR_Pos) /*!< 0x00000001 */
+#define ETH_MMCCR_CR                                  ETH_MMCCR_CR_Msk         /* Counters Reset               */
+
+/* Bit definition for Ethernet MMC Receive Interrupt Register */
+#define ETH_MMCRIR_RGUFS_Pos                          (17U)                    
+#define ETH_MMCRIR_RGUFS_Msk                          (0x1UL << ETH_MMCRIR_RGUFS_Pos) /*!< 0x00020000 */
+#define ETH_MMCRIR_RGUFS                              ETH_MMCRIR_RGUFS_Msk     /* Set when Rx good unicast frames counter reaches half the maximum value */
+#define ETH_MMCRIR_RFAES_Pos                          (6U)                     
+#define ETH_MMCRIR_RFAES_Msk                          (0x1UL << ETH_MMCRIR_RFAES_Pos) /*!< 0x00000040 */
+#define ETH_MMCRIR_RFAES                              ETH_MMCRIR_RFAES_Msk     /* Set when Rx alignment error counter reaches half the maximum value */
+#define ETH_MMCRIR_RFCES_Pos                          (5U)                     
+#define ETH_MMCRIR_RFCES_Msk                          (0x1UL << ETH_MMCRIR_RFCES_Pos) /*!< 0x00000020 */
+#define ETH_MMCRIR_RFCES                              ETH_MMCRIR_RFCES_Msk     /* Set when Rx crc error counter reaches half the maximum value */
+
+/* Bit definition for Ethernet MMC Transmit Interrupt Register */
+#define ETH_MMCTIR_TGFS_Pos                           (21U)                    
+#define ETH_MMCTIR_TGFS_Msk                           (0x1UL << ETH_MMCTIR_TGFS_Pos) /*!< 0x00200000 */
+#define ETH_MMCTIR_TGFS                               ETH_MMCTIR_TGFS_Msk      /* Set when Tx good frame count counter reaches half the maximum value */
+#define ETH_MMCTIR_TGFMSCS_Pos                        (15U)                    
+#define ETH_MMCTIR_TGFMSCS_Msk                        (0x1UL << ETH_MMCTIR_TGFMSCS_Pos) /*!< 0x00008000 */
+#define ETH_MMCTIR_TGFMSCS                            ETH_MMCTIR_TGFMSCS_Msk   /* Set when Tx good multi col counter reaches half the maximum value */
+#define ETH_MMCTIR_TGFSCS_Pos                         (14U)                    
+#define ETH_MMCTIR_TGFSCS_Msk                         (0x1UL << ETH_MMCTIR_TGFSCS_Pos) /*!< 0x00004000 */
+#define ETH_MMCTIR_TGFSCS                             ETH_MMCTIR_TGFSCS_Msk    /* Set when Tx good single col counter reaches half the maximum value */
+
+/* Bit definition for Ethernet MMC Receive Interrupt Mask Register */
+#define ETH_MMCRIMR_RGUFM_Pos                         (17U)                    
+#define ETH_MMCRIMR_RGUFM_Msk                         (0x1UL << ETH_MMCRIMR_RGUFM_Pos) /*!< 0x00020000 */
+#define ETH_MMCRIMR_RGUFM                             ETH_MMCRIMR_RGUFM_Msk    /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */
+#define ETH_MMCRIMR_RFAEM_Pos                         (6U)                     
+#define ETH_MMCRIMR_RFAEM_Msk                         (0x1UL << ETH_MMCRIMR_RFAEM_Pos) /*!< 0x00000040 */
+#define ETH_MMCRIMR_RFAEM                             ETH_MMCRIMR_RFAEM_Msk    /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */
+#define ETH_MMCRIMR_RFCEM_Pos                         (5U)                     
+#define ETH_MMCRIMR_RFCEM_Msk                         (0x1UL << ETH_MMCRIMR_RFCEM_Pos) /*!< 0x00000020 */
+#define ETH_MMCRIMR_RFCEM                             ETH_MMCRIMR_RFCEM_Msk    /* Mask the interrupt when Rx crc error counter reaches half the maximum value */
+
+/* Bit definition for Ethernet MMC Transmit Interrupt Mask Register */
+#define ETH_MMCTIMR_TGFM_Pos                          (21U)                    
+#define ETH_MMCTIMR_TGFM_Msk                          (0x1UL << ETH_MMCTIMR_TGFM_Pos) /*!< 0x00200000 */
+#define ETH_MMCTIMR_TGFM                              ETH_MMCTIMR_TGFM_Msk     /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */
+#define ETH_MMCTIMR_TGFMSCM_Pos                       (15U)                    
+#define ETH_MMCTIMR_TGFMSCM_Msk                       (0x1UL << ETH_MMCTIMR_TGFMSCM_Pos) /*!< 0x00008000 */
+#define ETH_MMCTIMR_TGFMSCM                           ETH_MMCTIMR_TGFMSCM_Msk  /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */
+#define ETH_MMCTIMR_TGFSCM_Pos                        (14U)                    
+#define ETH_MMCTIMR_TGFSCM_Msk                        (0x1UL << ETH_MMCTIMR_TGFSCM_Pos) /*!< 0x00004000 */
+#define ETH_MMCTIMR_TGFSCM                            ETH_MMCTIMR_TGFSCM_Msk   /* Mask the interrupt when Tx good single col counter reaches half the maximum value */
+
+/* Bit definition for Ethernet MMC Transmitted Good Frames after Single Collision Counter Register */
+#define ETH_MMCTGFSCCR_TGFSCC_Pos                     (0U)                     
+#define ETH_MMCTGFSCCR_TGFSCC_Msk                     (0xFFFFFFFFUL << ETH_MMCTGFSCCR_TGFSCC_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MMCTGFSCCR_TGFSCC                         ETH_MMCTGFSCCR_TGFSCC_Msk /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */
+
+/* Bit definition for Ethernet MMC Transmitted Good Frames after More than a Single Collision Counter Register */
+#define ETH_MMCTGFMSCCR_TGFMSCC_Pos                   (0U)                     
+#define ETH_MMCTGFMSCCR_TGFMSCC_Msk                   (0xFFFFFFFFUL << ETH_MMCTGFMSCCR_TGFMSCC_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MMCTGFMSCCR_TGFMSCC                       ETH_MMCTGFMSCCR_TGFMSCC_Msk /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */
+
+/* Bit definition for Ethernet MMC Transmitted Good Frames Counter Register */
+#define ETH_MMCTGFCR_TGFC_Pos                         (0U)                     
+#define ETH_MMCTGFCR_TGFC_Msk                         (0xFFFFFFFFUL << ETH_MMCTGFCR_TGFC_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MMCTGFCR_TGFC                             ETH_MMCTGFCR_TGFC_Msk    /* Number of good frames transmitted. */
+
+/* Bit definition for Ethernet MMC Received Frames with CRC Error Counter Register */
+#define ETH_MMCRFCECR_RFCEC_Pos                       (0U)                     
+#define ETH_MMCRFCECR_RFCEC_Msk                       (0xFFFFFFFFUL << ETH_MMCRFCECR_RFCEC_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MMCRFCECR_RFCEC                           ETH_MMCRFCECR_RFCEC_Msk  /* Number of frames received with CRC error. */
+
+/* Bit definition for Ethernet MMC Received Frames with Alignment Error Counter Register */
+#define ETH_MMCRFAECR_RFAEC_Pos                       (0U)                     
+#define ETH_MMCRFAECR_RFAEC_Msk                       (0xFFFFFFFFUL << ETH_MMCRFAECR_RFAEC_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MMCRFAECR_RFAEC                           ETH_MMCRFAECR_RFAEC_Msk  /* Number of frames received with alignment (dribble) error */
+
+/* Bit definition for Ethernet MMC Received Good Unicast Frames Counter Register */
+#define ETH_MMCRGUFCR_RGUFC_Pos                       (0U)                     
+#define ETH_MMCRGUFCR_RGUFC_Msk                       (0xFFFFFFFFUL << ETH_MMCRGUFCR_RGUFC_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MMCRGUFCR_RGUFC                           ETH_MMCRGUFCR_RGUFC_Msk  /* Number of good unicast frames received. */
+
+/******************************************************************************/
+/*               Ethernet PTP Registers bits definition                       */
+/******************************************************************************/
+
+/* Bit definition for Ethernet PTP Time Stamp Control Register */
+#define ETH_PTPTSCR_TSPFFMAE_Pos                      (18U)
+#define ETH_PTPTSCR_TSPFFMAE_Msk                      (0x1UL << ETH_PTPTSCR_TSPFFMAE_Pos) /*!< 0x00008000 */
+#define ETH_PTPTSCR_TSPFFMAE                          ETH_PTPTSCR_TSPFFMAE_Msk  /* Time stamp PTP frame filtering MAC address enable */
+#define ETH_PTPTSCR_TSCNT_Pos                         (16U)                    
+#define ETH_PTPTSCR_TSCNT_Msk                         (0x3UL << ETH_PTPTSCR_TSCNT_Pos) /*!< 0x00030000 */
+#define ETH_PTPTSCR_TSCNT                             ETH_PTPTSCR_TSCNT_Msk    /* Time stamp clock node type */
+#define ETH_PTPTSCR_TSSMRME_Pos                       (15U)                    
+#define ETH_PTPTSCR_TSSMRME_Msk                       (0x1UL << ETH_PTPTSCR_TSSMRME_Pos) /*!< 0x00008000 */
+#define ETH_PTPTSCR_TSSMRME                           ETH_PTPTSCR_TSSMRME_Msk  /* Time stamp snapshot for message relevant to master enable */
+#define ETH_PTPTSCR_TSSEME_Pos                        (14U)                    
+#define ETH_PTPTSCR_TSSEME_Msk                        (0x1UL << ETH_PTPTSCR_TSSEME_Pos) /*!< 0x00004000 */
+#define ETH_PTPTSCR_TSSEME                            ETH_PTPTSCR_TSSEME_Msk   /* Time stamp snapshot for event message enable */
+#define ETH_PTPTSCR_TSSIPV4FE_Pos                     (13U)                    
+#define ETH_PTPTSCR_TSSIPV4FE_Msk                     (0x1UL << ETH_PTPTSCR_TSSIPV4FE_Pos) /*!< 0x00002000 */
+#define ETH_PTPTSCR_TSSIPV4FE                         ETH_PTPTSCR_TSSIPV4FE_Msk /* Time stamp snapshot for IPv4 frames enable */
+#define ETH_PTPTSCR_TSSIPV6FE_Pos                     (12U)                    
+#define ETH_PTPTSCR_TSSIPV6FE_Msk                     (0x1UL << ETH_PTPTSCR_TSSIPV6FE_Pos) /*!< 0x00001000 */
+#define ETH_PTPTSCR_TSSIPV6FE                         ETH_PTPTSCR_TSSIPV6FE_Msk /* Time stamp snapshot for IPv6 frames enable */
+#define ETH_PTPTSCR_TSSPTPOEFE_Pos                    (11U)                    
+#define ETH_PTPTSCR_TSSPTPOEFE_Msk                    (0x1UL << ETH_PTPTSCR_TSSPTPOEFE_Pos) /*!< 0x00000800 */
+#define ETH_PTPTSCR_TSSPTPOEFE                        ETH_PTPTSCR_TSSPTPOEFE_Msk /* Time stamp snapshot for PTP over ethernet frames enable */
+#define ETH_PTPTSCR_TSPTPPSV2E_Pos                    (10U)                    
+#define ETH_PTPTSCR_TSPTPPSV2E_Msk                    (0x1UL << ETH_PTPTSCR_TSPTPPSV2E_Pos) /*!< 0x00000400 */
+#define ETH_PTPTSCR_TSPTPPSV2E                        ETH_PTPTSCR_TSPTPPSV2E_Msk /* Time stamp PTP packet snooping for version2 format enable */
+#define ETH_PTPTSCR_TSSSR_Pos                         (9U)                     
+#define ETH_PTPTSCR_TSSSR_Msk                         (0x1UL << ETH_PTPTSCR_TSSSR_Pos) /*!< 0x00000200 */
+#define ETH_PTPTSCR_TSSSR                             ETH_PTPTSCR_TSSSR_Msk    /* Time stamp Sub-seconds rollover */
+#define ETH_PTPTSCR_TSSARFE_Pos                       (8U)                     
+#define ETH_PTPTSCR_TSSARFE_Msk                       (0x1UL << ETH_PTPTSCR_TSSARFE_Pos) /*!< 0x00000100 */
+#define ETH_PTPTSCR_TSSARFE                           ETH_PTPTSCR_TSSARFE_Msk  /* Time stamp snapshot for all received frames enable */
+
+#define ETH_PTPTSCR_TSARU_Pos                         (5U)                     
+#define ETH_PTPTSCR_TSARU_Msk                         (0x1UL << ETH_PTPTSCR_TSARU_Pos) /*!< 0x00000020 */
+#define ETH_PTPTSCR_TSARU                             ETH_PTPTSCR_TSARU_Msk    /* Addend register update */
+#define ETH_PTPTSCR_TSITE_Pos                         (4U)                     
+#define ETH_PTPTSCR_TSITE_Msk                         (0x1UL << ETH_PTPTSCR_TSITE_Pos) /*!< 0x00000010 */
+#define ETH_PTPTSCR_TSITE                             ETH_PTPTSCR_TSITE_Msk    /* Time stamp interrupt trigger enable */
+#define ETH_PTPTSCR_TSSTU_Pos                         (3U)                     
+#define ETH_PTPTSCR_TSSTU_Msk                         (0x1UL << ETH_PTPTSCR_TSSTU_Pos) /*!< 0x00000008 */
+#define ETH_PTPTSCR_TSSTU                             ETH_PTPTSCR_TSSTU_Msk    /* Time stamp update */
+#define ETH_PTPTSCR_TSSTI_Pos                         (2U)                     
+#define ETH_PTPTSCR_TSSTI_Msk                         (0x1UL << ETH_PTPTSCR_TSSTI_Pos) /*!< 0x00000004 */
+#define ETH_PTPTSCR_TSSTI                             ETH_PTPTSCR_TSSTI_Msk    /* Time stamp initialize */
+#define ETH_PTPTSCR_TSFCU_Pos                         (1U)                     
+#define ETH_PTPTSCR_TSFCU_Msk                         (0x1UL << ETH_PTPTSCR_TSFCU_Pos) /*!< 0x00000002 */
+#define ETH_PTPTSCR_TSFCU                             ETH_PTPTSCR_TSFCU_Msk    /* Time stamp fine or coarse update */
+#define ETH_PTPTSCR_TSE_Pos                           (0U)                     
+#define ETH_PTPTSCR_TSE_Msk                           (0x1UL << ETH_PTPTSCR_TSE_Pos) /*!< 0x00000001 */
+#define ETH_PTPTSCR_TSE                               ETH_PTPTSCR_TSE_Msk      /* Time stamp enable */
+
+/* Bit definition for Ethernet PTP Sub-Second Increment Register */
+#define ETH_PTPSSIR_STSSI_Pos                         (0U)                     
+#define ETH_PTPSSIR_STSSI_Msk                         (0xFFUL << ETH_PTPSSIR_STSSI_Pos) /*!< 0x000000FF */
+#define ETH_PTPSSIR_STSSI                             ETH_PTPSSIR_STSSI_Msk    /* System time Sub-second increment value */
+
+/* Bit definition for Ethernet PTP Time Stamp High Register */
+#define ETH_PTPTSHR_STS_Pos                           (0U)                     
+#define ETH_PTPTSHR_STS_Msk                           (0xFFFFFFFFUL << ETH_PTPTSHR_STS_Pos) /*!< 0xFFFFFFFF */
+#define ETH_PTPTSHR_STS                               ETH_PTPTSHR_STS_Msk      /* System Time second */
+
+/* Bit definition for Ethernet PTP Time Stamp Low Register */
+#define ETH_PTPTSLR_STPNS_Pos                         (31U)                    
+#define ETH_PTPTSLR_STPNS_Msk                         (0x1UL << ETH_PTPTSLR_STPNS_Pos) /*!< 0x80000000 */
+#define ETH_PTPTSLR_STPNS                             ETH_PTPTSLR_STPNS_Msk    /* System Time Positive or negative time */
+#define ETH_PTPTSLR_STSS_Pos                          (0U)                     
+#define ETH_PTPTSLR_STSS_Msk                          (0x7FFFFFFFUL << ETH_PTPTSLR_STSS_Pos) /*!< 0x7FFFFFFF */
+#define ETH_PTPTSLR_STSS                              ETH_PTPTSLR_STSS_Msk     /* System Time sub-seconds */
+
+/* Bit definition for Ethernet PTP Time Stamp High Update Register */
+#define ETH_PTPTSHUR_TSUS_Pos                         (0U)                     
+#define ETH_PTPTSHUR_TSUS_Msk                         (0xFFFFFFFFUL << ETH_PTPTSHUR_TSUS_Pos) /*!< 0xFFFFFFFF */
+#define ETH_PTPTSHUR_TSUS                             ETH_PTPTSHUR_TSUS_Msk    /* Time stamp update seconds */
+
+/* Bit definition for Ethernet PTP Time Stamp Low Update Register */
+#define ETH_PTPTSLUR_TSUPNS_Pos                       (31U)                    
+#define ETH_PTPTSLUR_TSUPNS_Msk                       (0x1UL << ETH_PTPTSLUR_TSUPNS_Pos) /*!< 0x80000000 */
+#define ETH_PTPTSLUR_TSUPNS                           ETH_PTPTSLUR_TSUPNS_Msk  /* Time stamp update Positive or negative time */
+#define ETH_PTPTSLUR_TSUSS_Pos                        (0U)                     
+#define ETH_PTPTSLUR_TSUSS_Msk                        (0x7FFFFFFFUL << ETH_PTPTSLUR_TSUSS_Pos) /*!< 0x7FFFFFFF */
+#define ETH_PTPTSLUR_TSUSS                            ETH_PTPTSLUR_TSUSS_Msk   /* Time stamp update sub-seconds */
+
+/* Bit definition for Ethernet PTP Time Stamp Addend Register */
+#define ETH_PTPTSAR_TSA_Pos                           (0U)                     
+#define ETH_PTPTSAR_TSA_Msk                           (0xFFFFFFFFUL << ETH_PTPTSAR_TSA_Pos) /*!< 0xFFFFFFFF */
+#define ETH_PTPTSAR_TSA                               ETH_PTPTSAR_TSA_Msk      /* Time stamp addend */
+
+/* Bit definition for Ethernet PTP Target Time High Register */
+#define ETH_PTPTTHR_TTSH_Pos                          (0U)                     
+#define ETH_PTPTTHR_TTSH_Msk                          (0xFFFFFFFFUL << ETH_PTPTTHR_TTSH_Pos) /*!< 0xFFFFFFFF */
+#define ETH_PTPTTHR_TTSH                              ETH_PTPTTHR_TTSH_Msk     /* Target time stamp high */
+
+/* Bit definition for Ethernet PTP Target Time Low Register */
+#define ETH_PTPTTLR_TTSL_Pos                          (0U)                     
+#define ETH_PTPTTLR_TTSL_Msk                          (0xFFFFFFFFUL << ETH_PTPTTLR_TTSL_Pos) /*!< 0xFFFFFFFF */
+#define ETH_PTPTTLR_TTSL                              ETH_PTPTTLR_TTSL_Msk     /* Target time stamp low */
+
+/* Bit definition for Ethernet PTP Time Stamp Status Register */
+#define ETH_PTPTSSR_TSTTR_Pos                         (5U)                     
+#define ETH_PTPTSSR_TSTTR_Msk                         (0x1UL << ETH_PTPTSSR_TSTTR_Pos) /*!< 0x00000020 */
+#define ETH_PTPTSSR_TSTTR                             ETH_PTPTSSR_TSTTR_Msk    /* Time stamp target time reached */
+#define ETH_PTPTSSR_TSSO_Pos                          (4U)                     
+#define ETH_PTPTSSR_TSSO_Msk                          (0x1UL << ETH_PTPTSSR_TSSO_Pos) /*!< 0x00000010 */
+#define ETH_PTPTSSR_TSSO                              ETH_PTPTSSR_TSSO_Msk     /* Time stamp seconds overflow */
+
+/******************************************************************************/
+/*                 Ethernet DMA Registers bits definition                     */
+/******************************************************************************/
+
+/* Bit definition for Ethernet DMA Bus Mode Register */
+#define ETH_DMABMR_MB_Pos                             (26U)
+#define ETH_DMABMR_MB_Msk                             (0x1UL << ETH_DMABMR_MB_Pos) /*!< 0x04000000 */
+#define ETH_DMABMR_MB                                 ETH_DMABMR_MB_Msk       /* Mixed Burst */
+#define ETH_DMABMR_AAB_Pos                            (25U)                    
+#define ETH_DMABMR_AAB_Msk                            (0x1UL << ETH_DMABMR_AAB_Pos) /*!< 0x02000000 */
+#define ETH_DMABMR_AAB                                ETH_DMABMR_AAB_Msk       /* Address-Aligned beats */
+#define ETH_DMABMR_FPM_Pos                            (24U)                    
+#define ETH_DMABMR_FPM_Msk                            (0x1UL << ETH_DMABMR_FPM_Pos) /*!< 0x01000000 */
+#define ETH_DMABMR_FPM                                ETH_DMABMR_FPM_Msk       /* 4xPBL mode */
+#define ETH_DMABMR_USP_Pos                            (23U)                    
+#define ETH_DMABMR_USP_Msk                            (0x1UL << ETH_DMABMR_USP_Pos) /*!< 0x00800000 */
+#define ETH_DMABMR_USP                                ETH_DMABMR_USP_Msk       /* Use separate PBL */
+#define ETH_DMABMR_RDP_Pos                            (17U)                    
+#define ETH_DMABMR_RDP_Msk                            (0x3FUL << ETH_DMABMR_RDP_Pos) /*!< 0x007E0000 */
+#define ETH_DMABMR_RDP                                ETH_DMABMR_RDP_Msk       /* RxDMA PBL */
+#define ETH_DMABMR_RDP_1Beat                          0x00020000U              /* maximum number of beats to be transferred in one RxDMA transaction is 1 */
+#define ETH_DMABMR_RDP_2Beat                          0x00040000U              /* maximum number of beats to be transferred in one RxDMA transaction is 2 */
+#define ETH_DMABMR_RDP_4Beat                          0x00080000U              /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
+#define ETH_DMABMR_RDP_8Beat                          0x00100000U              /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
+#define ETH_DMABMR_RDP_16Beat                         0x00200000U              /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
+#define ETH_DMABMR_RDP_32Beat                         0x00400000U              /* maximum number of beats to be transferred in one RxDMA transaction is 32 */                
+#define ETH_DMABMR_RDP_4xPBL_4Beat                    0x01020000U              /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
+#define ETH_DMABMR_RDP_4xPBL_8Beat                    0x01040000U              /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
+#define ETH_DMABMR_RDP_4xPBL_16Beat                   0x01080000U              /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
+#define ETH_DMABMR_RDP_4xPBL_32Beat                   0x01100000U              /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
+#define ETH_DMABMR_RDP_4xPBL_64Beat                   0x01200000U              /* maximum number of beats to be transferred in one RxDMA transaction is 64 */
+#define ETH_DMABMR_RDP_4xPBL_128Beat                  0x01400000U              /* maximum number of beats to be transferred in one RxDMA transaction is 128 */  
+#define ETH_DMABMR_FB_Pos                             (16U)                    
+#define ETH_DMABMR_FB_Msk                             (0x1UL << ETH_DMABMR_FB_Pos) /*!< 0x00010000 */
+#define ETH_DMABMR_FB                                 ETH_DMABMR_FB_Msk        /* Fixed Burst */
+#define ETH_DMABMR_RTPR_Pos                           (14U)                    
+#define ETH_DMABMR_RTPR_Msk                           (0x3UL << ETH_DMABMR_RTPR_Pos) /*!< 0x0000C000 */
+#define ETH_DMABMR_RTPR                               ETH_DMABMR_RTPR_Msk      /* Rx Tx priority ratio */
+#define ETH_DMABMR_RTPR_1_1                           0x00000000U              /* Rx Tx priority ratio */
+#define ETH_DMABMR_RTPR_2_1                           0x00004000U              /* Rx Tx priority ratio */
+#define ETH_DMABMR_RTPR_3_1                           0x00008000U              /* Rx Tx priority ratio */
+#define ETH_DMABMR_RTPR_4_1                           0x0000C000U              /* Rx Tx priority ratio */  
+#define ETH_DMABMR_PBL_Pos                            (8U)                     
+#define ETH_DMABMR_PBL_Msk                            (0x3FUL << ETH_DMABMR_PBL_Pos) /*!< 0x00003F00 */
+#define ETH_DMABMR_PBL                                ETH_DMABMR_PBL_Msk       /* Programmable burst length */
+#define ETH_DMABMR_PBL_1Beat                          0x00000100U              /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
+#define ETH_DMABMR_PBL_2Beat                          0x00000200U              /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
+#define ETH_DMABMR_PBL_4Beat                          0x00000400U              /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
+#define ETH_DMABMR_PBL_8Beat                          0x00000800U              /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
+#define ETH_DMABMR_PBL_16Beat                         0x00001000U              /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
+#define ETH_DMABMR_PBL_32Beat                         0x00002000U              /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */                
+#define ETH_DMABMR_PBL_4xPBL_4Beat                    0x01000100U              /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
+#define ETH_DMABMR_PBL_4xPBL_8Beat                    0x01000200U              /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
+#define ETH_DMABMR_PBL_4xPBL_16Beat                   0x01000400U              /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
+#define ETH_DMABMR_PBL_4xPBL_32Beat                   0x01000800U              /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
+#define ETH_DMABMR_PBL_4xPBL_64Beat                   0x01001000U              /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
+#define ETH_DMABMR_PBL_4xPBL_128Beat                  0x01002000U              /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
+#define ETH_DMABMR_EDE_Pos                            (7U)                     
+#define ETH_DMABMR_EDE_Msk                            (0x1UL << ETH_DMABMR_EDE_Pos) /*!< 0x00000080 */
+#define ETH_DMABMR_EDE                                ETH_DMABMR_EDE_Msk       /* Enhanced Descriptor Enable */
+#define ETH_DMABMR_DSL_Pos                            (2U)                     
+#define ETH_DMABMR_DSL_Msk                            (0x1FUL << ETH_DMABMR_DSL_Pos) /*!< 0x0000007C */
+#define ETH_DMABMR_DSL                                ETH_DMABMR_DSL_Msk       /* Descriptor Skip Length */
+#define ETH_DMABMR_DA_Pos                             (1U)                     
+#define ETH_DMABMR_DA_Msk                             (0x1UL << ETH_DMABMR_DA_Pos) /*!< 0x00000002 */
+#define ETH_DMABMR_DA                                 ETH_DMABMR_DA_Msk        /* DMA arbitration scheme */
+#define ETH_DMABMR_SR_Pos                             (0U)                     
+#define ETH_DMABMR_SR_Msk                             (0x1UL << ETH_DMABMR_SR_Pos) /*!< 0x00000001 */
+#define ETH_DMABMR_SR                                 ETH_DMABMR_SR_Msk        /* Software reset */
+
+/* Bit definition for Ethernet DMA Transmit Poll Demand Register */
+#define ETH_DMATPDR_TPD_Pos                           (0U)                     
+#define ETH_DMATPDR_TPD_Msk                           (0xFFFFFFFFUL << ETH_DMATPDR_TPD_Pos) /*!< 0xFFFFFFFF */
+#define ETH_DMATPDR_TPD                               ETH_DMATPDR_TPD_Msk      /* Transmit poll demand */
+
+/* Bit definition for Ethernet DMA Receive Poll Demand Register */
+#define ETH_DMARPDR_RPD_Pos                           (0U)                     
+#define ETH_DMARPDR_RPD_Msk                           (0xFFFFFFFFUL << ETH_DMARPDR_RPD_Pos) /*!< 0xFFFFFFFF */
+#define ETH_DMARPDR_RPD                               ETH_DMARPDR_RPD_Msk      /* Receive poll demand  */
+
+/* Bit definition for Ethernet DMA Receive Descriptor List Address Register */
+#define ETH_DMARDLAR_SRL_Pos                          (0U)                     
+#define ETH_DMARDLAR_SRL_Msk                          (0xFFFFFFFFUL << ETH_DMARDLAR_SRL_Pos) /*!< 0xFFFFFFFF */
+#define ETH_DMARDLAR_SRL                              ETH_DMARDLAR_SRL_Msk     /* Start of receive list */
+
+/* Bit definition for Ethernet DMA Transmit Descriptor List Address Register */
+#define ETH_DMATDLAR_STL_Pos                          (0U)                     
+#define ETH_DMATDLAR_STL_Msk                          (0xFFFFFFFFUL << ETH_DMATDLAR_STL_Pos) /*!< 0xFFFFFFFF */
+#define ETH_DMATDLAR_STL                              ETH_DMATDLAR_STL_Msk     /* Start of transmit list */
+
+/* Bit definition for Ethernet DMA Status Register */
+#define ETH_DMASR_TSTS_Pos                            (29U)                    
+#define ETH_DMASR_TSTS_Msk                            (0x1UL << ETH_DMASR_TSTS_Pos) /*!< 0x20000000 */
+#define ETH_DMASR_TSTS                                ETH_DMASR_TSTS_Msk       /* Time-stamp trigger status */
+#define ETH_DMASR_PMTS_Pos                            (28U)                    
+#define ETH_DMASR_PMTS_Msk                            (0x1UL << ETH_DMASR_PMTS_Pos) /*!< 0x10000000 */
+#define ETH_DMASR_PMTS                                ETH_DMASR_PMTS_Msk       /* PMT status */
+#define ETH_DMASR_MMCS_Pos                            (27U)                    
+#define ETH_DMASR_MMCS_Msk                            (0x1UL << ETH_DMASR_MMCS_Pos) /*!< 0x08000000 */
+#define ETH_DMASR_MMCS                                ETH_DMASR_MMCS_Msk       /* MMC status */
+#define ETH_DMASR_EBS_Pos                             (23U)                    
+#define ETH_DMASR_EBS_Msk                             (0x7UL << ETH_DMASR_EBS_Pos) /*!< 0x03800000 */
+#define ETH_DMASR_EBS                                 ETH_DMASR_EBS_Msk        /* Error bits status */
+  /* combination with EBS[2:0] for GetFlagStatus function */
+#define ETH_DMASR_EBS_DescAccess_Pos                  (25U)                    
+#define ETH_DMASR_EBS_DescAccess_Msk                  (0x1UL << ETH_DMASR_EBS_DescAccess_Pos) /*!< 0x02000000 */
+#define ETH_DMASR_EBS_DescAccess                      ETH_DMASR_EBS_DescAccess_Msk /* Error bits 0-data buffer, 1-desc. access */
+#define ETH_DMASR_EBS_ReadTransf_Pos                  (24U)                    
+#define ETH_DMASR_EBS_ReadTransf_Msk                  (0x1UL << ETH_DMASR_EBS_ReadTransf_Pos) /*!< 0x01000000 */
+#define ETH_DMASR_EBS_ReadTransf                      ETH_DMASR_EBS_ReadTransf_Msk /* Error bits 0-write trnsf, 1-read transfr */
+#define ETH_DMASR_EBS_DataTransfTx_Pos                (23U)                    
+#define ETH_DMASR_EBS_DataTransfTx_Msk                (0x1UL << ETH_DMASR_EBS_DataTransfTx_Pos) /*!< 0x00800000 */
+#define ETH_DMASR_EBS_DataTransfTx                    ETH_DMASR_EBS_DataTransfTx_Msk /* Error bits 0-Rx DMA, 1-Tx DMA */
+#define ETH_DMASR_TPS_Pos                             (20U)                    
+#define ETH_DMASR_TPS_Msk                             (0x7UL << ETH_DMASR_TPS_Pos) /*!< 0x00700000 */
+#define ETH_DMASR_TPS                                 ETH_DMASR_TPS_Msk        /* Transmit process state */
+#define ETH_DMASR_TPS_Stopped                         0x00000000U              /* Stopped - Reset or Stop Tx Command issued  */
+#define ETH_DMASR_TPS_Fetching_Pos                    (20U)                    
+#define ETH_DMASR_TPS_Fetching_Msk                    (0x1UL << ETH_DMASR_TPS_Fetching_Pos) /*!< 0x00100000 */
+#define ETH_DMASR_TPS_Fetching                        ETH_DMASR_TPS_Fetching_Msk /* Running - fetching the Tx descriptor */
+#define ETH_DMASR_TPS_Waiting_Pos                     (21U)                    
+#define ETH_DMASR_TPS_Waiting_Msk                     (0x1UL << ETH_DMASR_TPS_Waiting_Pos) /*!< 0x00200000 */
+#define ETH_DMASR_TPS_Waiting                         ETH_DMASR_TPS_Waiting_Msk /* Running - waiting for status */
+#define ETH_DMASR_TPS_Reading_Pos                     (20U)                    
+#define ETH_DMASR_TPS_Reading_Msk                     (0x3UL << ETH_DMASR_TPS_Reading_Pos) /*!< 0x00300000 */
+#define ETH_DMASR_TPS_Reading                         ETH_DMASR_TPS_Reading_Msk /* Running - reading the data from host memory */
+#define ETH_DMASR_TPS_Suspended_Pos                   (21U)                    
+#define ETH_DMASR_TPS_Suspended_Msk                   (0x3UL << ETH_DMASR_TPS_Suspended_Pos) /*!< 0x00600000 */
+#define ETH_DMASR_TPS_Suspended                       ETH_DMASR_TPS_Suspended_Msk /* Suspended - Tx Descriptor unavailable */
+#define ETH_DMASR_TPS_Closing_Pos                     (20U)                    
+#define ETH_DMASR_TPS_Closing_Msk                     (0x7UL << ETH_DMASR_TPS_Closing_Pos) /*!< 0x00700000 */
+#define ETH_DMASR_TPS_Closing                         ETH_DMASR_TPS_Closing_Msk /* Running - closing Rx descriptor */
+#define ETH_DMASR_RPS_Pos                             (17U)                    
+#define ETH_DMASR_RPS_Msk                             (0x7UL << ETH_DMASR_RPS_Pos) /*!< 0x000E0000 */
+#define ETH_DMASR_RPS                                 ETH_DMASR_RPS_Msk        /* Receive process state */
+#define ETH_DMASR_RPS_Stopped                         0x00000000U              /* Stopped - Reset or Stop Rx Command issued */
+#define ETH_DMASR_RPS_Fetching_Pos                    (17U)                    
+#define ETH_DMASR_RPS_Fetching_Msk                    (0x1UL << ETH_DMASR_RPS_Fetching_Pos) /*!< 0x00020000 */
+#define ETH_DMASR_RPS_Fetching                        ETH_DMASR_RPS_Fetching_Msk /* Running - fetching the Rx descriptor */
+#define ETH_DMASR_RPS_Waiting_Pos                     (17U)                    
+#define ETH_DMASR_RPS_Waiting_Msk                     (0x3UL << ETH_DMASR_RPS_Waiting_Pos) /*!< 0x00060000 */
+#define ETH_DMASR_RPS_Waiting                         ETH_DMASR_RPS_Waiting_Msk /* Running - waiting for packet */
+#define ETH_DMASR_RPS_Suspended_Pos                   (19U)                    
+#define ETH_DMASR_RPS_Suspended_Msk                   (0x1UL << ETH_DMASR_RPS_Suspended_Pos) /*!< 0x00080000 */
+#define ETH_DMASR_RPS_Suspended                       ETH_DMASR_RPS_Suspended_Msk /* Suspended - Rx Descriptor unavailable */
+#define ETH_DMASR_RPS_Closing_Pos                     (17U)                    
+#define ETH_DMASR_RPS_Closing_Msk                     (0x5UL << ETH_DMASR_RPS_Closing_Pos) /*!< 0x000A0000 */
+#define ETH_DMASR_RPS_Closing                         ETH_DMASR_RPS_Closing_Msk /* Running - closing descriptor */
+#define ETH_DMASR_RPS_Queuing_Pos                     (17U)                    
+#define ETH_DMASR_RPS_Queuing_Msk                     (0x7UL << ETH_DMASR_RPS_Queuing_Pos) /*!< 0x000E0000 */
+#define ETH_DMASR_RPS_Queuing                         ETH_DMASR_RPS_Queuing_Msk /* Running - queuing the receive frame into host memory */
+#define ETH_DMASR_NIS_Pos                             (16U)                    
+#define ETH_DMASR_NIS_Msk                             (0x1UL << ETH_DMASR_NIS_Pos) /*!< 0x00010000 */
+#define ETH_DMASR_NIS                                 ETH_DMASR_NIS_Msk        /* Normal interrupt summary */
+#define ETH_DMASR_AIS_Pos                             (15U)                    
+#define ETH_DMASR_AIS_Msk                             (0x1UL << ETH_DMASR_AIS_Pos) /*!< 0x00008000 */
+#define ETH_DMASR_AIS                                 ETH_DMASR_AIS_Msk        /* Abnormal interrupt summary */
+#define ETH_DMASR_ERS_Pos                             (14U)                    
+#define ETH_DMASR_ERS_Msk                             (0x1UL << ETH_DMASR_ERS_Pos) /*!< 0x00004000 */
+#define ETH_DMASR_ERS                                 ETH_DMASR_ERS_Msk        /* Early receive status */
+#define ETH_DMASR_FBES_Pos                            (13U)                    
+#define ETH_DMASR_FBES_Msk                            (0x1UL << ETH_DMASR_FBES_Pos) /*!< 0x00002000 */
+#define ETH_DMASR_FBES                                ETH_DMASR_FBES_Msk       /* Fatal bus error status */
+#define ETH_DMASR_ETS_Pos                             (10U)                    
+#define ETH_DMASR_ETS_Msk                             (0x1UL << ETH_DMASR_ETS_Pos) /*!< 0x00000400 */
+#define ETH_DMASR_ETS                                 ETH_DMASR_ETS_Msk        /* Early transmit status */
+#define ETH_DMASR_RWTS_Pos                            (9U)                     
+#define ETH_DMASR_RWTS_Msk                            (0x1UL << ETH_DMASR_RWTS_Pos) /*!< 0x00000200 */
+#define ETH_DMASR_RWTS                                ETH_DMASR_RWTS_Msk       /* Receive watchdog timeout status */
+#define ETH_DMASR_RPSS_Pos                            (8U)                     
+#define ETH_DMASR_RPSS_Msk                            (0x1UL << ETH_DMASR_RPSS_Pos) /*!< 0x00000100 */
+#define ETH_DMASR_RPSS                                ETH_DMASR_RPSS_Msk       /* Receive process stopped status */
+#define ETH_DMASR_RBUS_Pos                            (7U)                     
+#define ETH_DMASR_RBUS_Msk                            (0x1UL << ETH_DMASR_RBUS_Pos) /*!< 0x00000080 */
+#define ETH_DMASR_RBUS                                ETH_DMASR_RBUS_Msk       /* Receive buffer unavailable status */
+#define ETH_DMASR_RS_Pos                              (6U)                     
+#define ETH_DMASR_RS_Msk                              (0x1UL << ETH_DMASR_RS_Pos) /*!< 0x00000040 */
+#define ETH_DMASR_RS                                  ETH_DMASR_RS_Msk         /* Receive status */
+#define ETH_DMASR_TUS_Pos                             (5U)                     
+#define ETH_DMASR_TUS_Msk                             (0x1UL << ETH_DMASR_TUS_Pos) /*!< 0x00000020 */
+#define ETH_DMASR_TUS                                 ETH_DMASR_TUS_Msk        /* Transmit underflow status */
+#define ETH_DMASR_ROS_Pos                             (4U)                     
+#define ETH_DMASR_ROS_Msk                             (0x1UL << ETH_DMASR_ROS_Pos) /*!< 0x00000010 */
+#define ETH_DMASR_ROS                                 ETH_DMASR_ROS_Msk        /* Receive overflow status */
+#define ETH_DMASR_TJTS_Pos                            (3U)                     
+#define ETH_DMASR_TJTS_Msk                            (0x1UL << ETH_DMASR_TJTS_Pos) /*!< 0x00000008 */
+#define ETH_DMASR_TJTS                                ETH_DMASR_TJTS_Msk       /* Transmit jabber timeout status */
+#define ETH_DMASR_TBUS_Pos                            (2U)                     
+#define ETH_DMASR_TBUS_Msk                            (0x1UL << ETH_DMASR_TBUS_Pos) /*!< 0x00000004 */
+#define ETH_DMASR_TBUS                                ETH_DMASR_TBUS_Msk       /* Transmit buffer unavailable status */
+#define ETH_DMASR_TPSS_Pos                            (1U)                     
+#define ETH_DMASR_TPSS_Msk                            (0x1UL << ETH_DMASR_TPSS_Pos) /*!< 0x00000002 */
+#define ETH_DMASR_TPSS                                ETH_DMASR_TPSS_Msk       /* Transmit process stopped status */
+#define ETH_DMASR_TS_Pos                              (0U)                     
+#define ETH_DMASR_TS_Msk                              (0x1UL << ETH_DMASR_TS_Pos) /*!< 0x00000001 */
+#define ETH_DMASR_TS                                  ETH_DMASR_TS_Msk         /* Transmit status */
+
+/* Bit definition for Ethernet DMA Operation Mode Register */
+#define ETH_DMAOMR_DTCEFD_Pos                         (26U)                    
+#define ETH_DMAOMR_DTCEFD_Msk                         (0x1UL << ETH_DMAOMR_DTCEFD_Pos) /*!< 0x04000000 */
+#define ETH_DMAOMR_DTCEFD                             ETH_DMAOMR_DTCEFD_Msk    /* Disable Dropping of TCP/IP checksum error frames */
+#define ETH_DMAOMR_RSF_Pos                            (25U)                    
+#define ETH_DMAOMR_RSF_Msk                            (0x1UL << ETH_DMAOMR_RSF_Pos) /*!< 0x02000000 */
+#define ETH_DMAOMR_RSF                                ETH_DMAOMR_RSF_Msk       /* Receive store and forward */
+#define ETH_DMAOMR_DFRF_Pos                           (24U)                    
+#define ETH_DMAOMR_DFRF_Msk                           (0x1UL << ETH_DMAOMR_DFRF_Pos) /*!< 0x01000000 */
+#define ETH_DMAOMR_DFRF                               ETH_DMAOMR_DFRF_Msk      /* Disable flushing of received frames */
+#define ETH_DMAOMR_TSF_Pos                            (21U)                    
+#define ETH_DMAOMR_TSF_Msk                            (0x1UL << ETH_DMAOMR_TSF_Pos) /*!< 0x00200000 */
+#define ETH_DMAOMR_TSF                                ETH_DMAOMR_TSF_Msk       /* Transmit store and forward */
+#define ETH_DMAOMR_FTF_Pos                            (20U)                    
+#define ETH_DMAOMR_FTF_Msk                            (0x1UL << ETH_DMAOMR_FTF_Pos) /*!< 0x00100000 */
+#define ETH_DMAOMR_FTF                                ETH_DMAOMR_FTF_Msk       /* Flush transmit FIFO */
+#define ETH_DMAOMR_TTC_Pos                            (14U)                    
+#define ETH_DMAOMR_TTC_Msk                            (0x7UL << ETH_DMAOMR_TTC_Pos) /*!< 0x0001C000 */
+#define ETH_DMAOMR_TTC                                ETH_DMAOMR_TTC_Msk       /* Transmit threshold control */
+#define ETH_DMAOMR_TTC_64Bytes                        0x00000000U              /* threshold level of the MTL Transmit FIFO is 64 Bytes */
+#define ETH_DMAOMR_TTC_128Bytes                       0x00004000U              /* threshold level of the MTL Transmit FIFO is 128 Bytes */
+#define ETH_DMAOMR_TTC_192Bytes                       0x00008000U              /* threshold level of the MTL Transmit FIFO is 192 Bytes */
+#define ETH_DMAOMR_TTC_256Bytes                       0x0000C000U              /* threshold level of the MTL Transmit FIFO is 256 Bytes */
+#define ETH_DMAOMR_TTC_40Bytes                        0x00010000U              /* threshold level of the MTL Transmit FIFO is 40 Bytes */
+#define ETH_DMAOMR_TTC_32Bytes                        0x00014000U              /* threshold level of the MTL Transmit FIFO is 32 Bytes */
+#define ETH_DMAOMR_TTC_24Bytes                        0x00018000U              /* threshold level of the MTL Transmit FIFO is 24 Bytes */
+#define ETH_DMAOMR_TTC_16Bytes                        0x0001C000U              /* threshold level of the MTL Transmit FIFO is 16 Bytes */
+#define ETH_DMAOMR_ST_Pos                             (13U)                    
+#define ETH_DMAOMR_ST_Msk                             (0x1UL << ETH_DMAOMR_ST_Pos) /*!< 0x00002000 */
+#define ETH_DMAOMR_ST                                 ETH_DMAOMR_ST_Msk        /* Start/stop transmission command */
+#define ETH_DMAOMR_FEF_Pos                            (7U)                     
+#define ETH_DMAOMR_FEF_Msk                            (0x1UL << ETH_DMAOMR_FEF_Pos) /*!< 0x00000080 */
+#define ETH_DMAOMR_FEF                                ETH_DMAOMR_FEF_Msk       /* Forward error frames */
+#define ETH_DMAOMR_FUGF_Pos                           (6U)                     
+#define ETH_DMAOMR_FUGF_Msk                           (0x1UL << ETH_DMAOMR_FUGF_Pos) /*!< 0x00000040 */
+#define ETH_DMAOMR_FUGF                               ETH_DMAOMR_FUGF_Msk      /* Forward undersized good frames */
+#define ETH_DMAOMR_RTC_Pos                            (3U)                     
+#define ETH_DMAOMR_RTC_Msk                            (0x3UL << ETH_DMAOMR_RTC_Pos) /*!< 0x00000018 */
+#define ETH_DMAOMR_RTC                                ETH_DMAOMR_RTC_Msk       /* receive threshold control */
+#define ETH_DMAOMR_RTC_64Bytes                        0x00000000U              /* threshold level of the MTL Receive FIFO is 64 Bytes */
+#define ETH_DMAOMR_RTC_32Bytes                        0x00000008U              /* threshold level of the MTL Receive FIFO is 32 Bytes */
+#define ETH_DMAOMR_RTC_96Bytes                        0x00000010U              /* threshold level of the MTL Receive FIFO is 96 Bytes */
+#define ETH_DMAOMR_RTC_128Bytes                       0x00000018U              /* threshold level of the MTL Receive FIFO is 128 Bytes */
+#define ETH_DMAOMR_OSF_Pos                            (2U)                     
+#define ETH_DMAOMR_OSF_Msk                            (0x1UL << ETH_DMAOMR_OSF_Pos) /*!< 0x00000004 */
+#define ETH_DMAOMR_OSF                                ETH_DMAOMR_OSF_Msk       /* operate on second frame */
+#define ETH_DMAOMR_SR_Pos                             (1U)                     
+#define ETH_DMAOMR_SR_Msk                             (0x1UL << ETH_DMAOMR_SR_Pos) /*!< 0x00000002 */
+#define ETH_DMAOMR_SR                                 ETH_DMAOMR_SR_Msk        /* Start/stop receive */
+
+/* Bit definition for Ethernet DMA Interrupt Enable Register */
+#define ETH_DMAIER_NISE_Pos                           (16U)                    
+#define ETH_DMAIER_NISE_Msk                           (0x1UL << ETH_DMAIER_NISE_Pos) /*!< 0x00010000 */
+#define ETH_DMAIER_NISE                               ETH_DMAIER_NISE_Msk      /* Normal interrupt summary enable */
+#define ETH_DMAIER_AISE_Pos                           (15U)                    
+#define ETH_DMAIER_AISE_Msk                           (0x1UL << ETH_DMAIER_AISE_Pos) /*!< 0x00008000 */
+#define ETH_DMAIER_AISE                               ETH_DMAIER_AISE_Msk      /* Abnormal interrupt summary enable */
+#define ETH_DMAIER_ERIE_Pos                           (14U)                    
+#define ETH_DMAIER_ERIE_Msk                           (0x1UL << ETH_DMAIER_ERIE_Pos) /*!< 0x00004000 */
+#define ETH_DMAIER_ERIE                               ETH_DMAIER_ERIE_Msk      /* Early receive interrupt enable */
+#define ETH_DMAIER_FBEIE_Pos                          (13U)                    
+#define ETH_DMAIER_FBEIE_Msk                          (0x1UL << ETH_DMAIER_FBEIE_Pos) /*!< 0x00002000 */
+#define ETH_DMAIER_FBEIE                              ETH_DMAIER_FBEIE_Msk     /* Fatal bus error interrupt enable */
+#define ETH_DMAIER_ETIE_Pos                           (10U)                    
+#define ETH_DMAIER_ETIE_Msk                           (0x1UL << ETH_DMAIER_ETIE_Pos) /*!< 0x00000400 */
+#define ETH_DMAIER_ETIE                               ETH_DMAIER_ETIE_Msk      /* Early transmit interrupt enable */
+#define ETH_DMAIER_RWTIE_Pos                          (9U)                     
+#define ETH_DMAIER_RWTIE_Msk                          (0x1UL << ETH_DMAIER_RWTIE_Pos) /*!< 0x00000200 */
+#define ETH_DMAIER_RWTIE                              ETH_DMAIER_RWTIE_Msk     /* Receive watchdog timeout interrupt enable */
+#define ETH_DMAIER_RPSIE_Pos                          (8U)                     
+#define ETH_DMAIER_RPSIE_Msk                          (0x1UL << ETH_DMAIER_RPSIE_Pos) /*!< 0x00000100 */
+#define ETH_DMAIER_RPSIE                              ETH_DMAIER_RPSIE_Msk     /* Receive process stopped interrupt enable */
+#define ETH_DMAIER_RBUIE_Pos                          (7U)                     
+#define ETH_DMAIER_RBUIE_Msk                          (0x1UL << ETH_DMAIER_RBUIE_Pos) /*!< 0x00000080 */
+#define ETH_DMAIER_RBUIE                              ETH_DMAIER_RBUIE_Msk     /* Receive buffer unavailable interrupt enable */
+#define ETH_DMAIER_RIE_Pos                            (6U)                     
+#define ETH_DMAIER_RIE_Msk                            (0x1UL << ETH_DMAIER_RIE_Pos) /*!< 0x00000040 */
+#define ETH_DMAIER_RIE                                ETH_DMAIER_RIE_Msk       /* Receive interrupt enable */
+#define ETH_DMAIER_TUIE_Pos                           (5U)                     
+#define ETH_DMAIER_TUIE_Msk                           (0x1UL << ETH_DMAIER_TUIE_Pos) /*!< 0x00000020 */
+#define ETH_DMAIER_TUIE                               ETH_DMAIER_TUIE_Msk      /* Transmit Underflow interrupt enable */
+#define ETH_DMAIER_ROIE_Pos                           (4U)                     
+#define ETH_DMAIER_ROIE_Msk                           (0x1UL << ETH_DMAIER_ROIE_Pos) /*!< 0x00000010 */
+#define ETH_DMAIER_ROIE                               ETH_DMAIER_ROIE_Msk      /* Receive Overflow interrupt enable */
+#define ETH_DMAIER_TJTIE_Pos                          (3U)                     
+#define ETH_DMAIER_TJTIE_Msk                          (0x1UL << ETH_DMAIER_TJTIE_Pos) /*!< 0x00000008 */
+#define ETH_DMAIER_TJTIE                              ETH_DMAIER_TJTIE_Msk     /* Transmit jabber timeout interrupt enable */
+#define ETH_DMAIER_TBUIE_Pos                          (2U)                     
+#define ETH_DMAIER_TBUIE_Msk                          (0x1UL << ETH_DMAIER_TBUIE_Pos) /*!< 0x00000004 */
+#define ETH_DMAIER_TBUIE                              ETH_DMAIER_TBUIE_Msk     /* Transmit buffer unavailable interrupt enable */
+#define ETH_DMAIER_TPSIE_Pos                          (1U)                     
+#define ETH_DMAIER_TPSIE_Msk                          (0x1UL << ETH_DMAIER_TPSIE_Pos) /*!< 0x00000002 */
+#define ETH_DMAIER_TPSIE                              ETH_DMAIER_TPSIE_Msk     /* Transmit process stopped interrupt enable */
+#define ETH_DMAIER_TIE_Pos                            (0U)                     
+#define ETH_DMAIER_TIE_Msk                            (0x1UL << ETH_DMAIER_TIE_Pos) /*!< 0x00000001 */
+#define ETH_DMAIER_TIE                                ETH_DMAIER_TIE_Msk       /* Transmit interrupt enable */
+
+/* Bit definition for Ethernet DMA Missed Frame and Buffer Overflow Counter Register */
+#define ETH_DMAMFBOCR_OFOC_Pos                        (28U)                    
+#define ETH_DMAMFBOCR_OFOC_Msk                        (0x1UL << ETH_DMAMFBOCR_OFOC_Pos) /*!< 0x10000000 */
+#define ETH_DMAMFBOCR_OFOC                            ETH_DMAMFBOCR_OFOC_Msk   /* Overflow bit for FIFO overflow counter */
+#define ETH_DMAMFBOCR_MFA_Pos                         (17U)                    
+#define ETH_DMAMFBOCR_MFA_Msk                         (0x7FFUL << ETH_DMAMFBOCR_MFA_Pos) /*!< 0x0FFE0000 */
+#define ETH_DMAMFBOCR_MFA                             ETH_DMAMFBOCR_MFA_Msk    /* Number of frames missed by the application */
+#define ETH_DMAMFBOCR_OMFC_Pos                        (16U)                    
+#define ETH_DMAMFBOCR_OMFC_Msk                        (0x1UL << ETH_DMAMFBOCR_OMFC_Pos) /*!< 0x00010000 */
+#define ETH_DMAMFBOCR_OMFC                            ETH_DMAMFBOCR_OMFC_Msk   /* Overflow bit for missed frame counter */
+#define ETH_DMAMFBOCR_MFC_Pos                         (0U)                     
+#define ETH_DMAMFBOCR_MFC_Msk                         (0xFFFFUL << ETH_DMAMFBOCR_MFC_Pos) /*!< 0x0000FFFF */
+#define ETH_DMAMFBOCR_MFC                             ETH_DMAMFBOCR_MFC_Msk    /* Number of frames missed by the controller */
+
+/* Bit definition for Ethernet DMA Current Host Transmit Descriptor Register */
+#define ETH_DMACHTDR_HTDAP_Pos                        (0U)                     
+#define ETH_DMACHTDR_HTDAP_Msk                        (0xFFFFFFFFUL << ETH_DMACHTDR_HTDAP_Pos) /*!< 0xFFFFFFFF */
+#define ETH_DMACHTDR_HTDAP                            ETH_DMACHTDR_HTDAP_Msk   /* Host transmit descriptor address pointer */
+
+/* Bit definition for Ethernet DMA Current Host Receive Descriptor Register */
+#define ETH_DMACHRDR_HRDAP_Pos                        (0U)                     
+#define ETH_DMACHRDR_HRDAP_Msk                        (0xFFFFFFFFUL << ETH_DMACHRDR_HRDAP_Pos) /*!< 0xFFFFFFFF */
+#define ETH_DMACHRDR_HRDAP                            ETH_DMACHRDR_HRDAP_Msk   /* Host receive descriptor address pointer */
+
+/* Bit definition for Ethernet DMA Current Host Transmit Buffer Address Register */
+#define ETH_DMACHTBAR_HTBAP_Pos                       (0U)                     
+#define ETH_DMACHTBAR_HTBAP_Msk                       (0xFFFFFFFFUL << ETH_DMACHTBAR_HTBAP_Pos) /*!< 0xFFFFFFFF */
+#define ETH_DMACHTBAR_HTBAP                           ETH_DMACHTBAR_HTBAP_Msk  /* Host transmit buffer address pointer */
+
+/* Bit definition for Ethernet DMA Current Host Receive Buffer Address Register */
+#define ETH_DMACHRBAR_HRBAP_Pos                       (0U)                     
+#define ETH_DMACHRBAR_HRBAP_Msk                       (0xFFFFFFFFUL << ETH_DMACHRBAR_HRBAP_Pos) /*!< 0xFFFFFFFF */
+#define ETH_DMACHRBAR_HRBAP                           ETH_DMACHRBAR_HRBAP_Msk  /* Host receive buffer address pointer */
+
+/******************************************************************************/
+/*                                                                            */
+/*                                       USB_OTG                              */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bit definition for USB_OTG_GOTGCTL register  ***********/
+#define USB_OTG_GOTGCTL_SRQSCS_Pos               (0U)                          
+#define USB_OTG_GOTGCTL_SRQSCS_Msk               (0x1UL << USB_OTG_GOTGCTL_SRQSCS_Pos) /*!< 0x00000001 */
+#define USB_OTG_GOTGCTL_SRQSCS                   USB_OTG_GOTGCTL_SRQSCS_Msk    /*!< Session request success */
+#define USB_OTG_GOTGCTL_SRQ_Pos                  (1U)                          
+#define USB_OTG_GOTGCTL_SRQ_Msk                  (0x1UL << USB_OTG_GOTGCTL_SRQ_Pos) /*!< 0x00000002 */
+#define USB_OTG_GOTGCTL_SRQ                      USB_OTG_GOTGCTL_SRQ_Msk       /*!< Session request */
+#define USB_OTG_GOTGCTL_VBVALOEN_Pos             (2U)                          
+#define USB_OTG_GOTGCTL_VBVALOEN_Msk             (0x1UL << USB_OTG_GOTGCTL_VBVALOEN_Pos) /*!< 0x00000004 */
+#define USB_OTG_GOTGCTL_VBVALOEN                 USB_OTG_GOTGCTL_VBVALOEN_Msk  /*!< VBUS valid override enable */
+#define USB_OTG_GOTGCTL_VBVALOVAL_Pos            (3U)                          
+#define USB_OTG_GOTGCTL_VBVALOVAL_Msk            (0x1UL << USB_OTG_GOTGCTL_VBVALOVAL_Pos) /*!< 0x00000008 */
+#define USB_OTG_GOTGCTL_VBVALOVAL                USB_OTG_GOTGCTL_VBVALOVAL_Msk /*!< VBUS valid override value */
+#define USB_OTG_GOTGCTL_AVALOEN_Pos              (4U)                          
+#define USB_OTG_GOTGCTL_AVALOEN_Msk              (0x1UL << USB_OTG_GOTGCTL_AVALOEN_Pos) /*!< 0x00000010 */
+#define USB_OTG_GOTGCTL_AVALOEN                  USB_OTG_GOTGCTL_AVALOEN_Msk   /*!< A-peripheral session valid override enable */
+#define USB_OTG_GOTGCTL_AVALOVAL_Pos             (5U)                          
+#define USB_OTG_GOTGCTL_AVALOVAL_Msk             (0x1UL << USB_OTG_GOTGCTL_AVALOVAL_Pos) /*!< 0x00000020 */
+#define USB_OTG_GOTGCTL_AVALOVAL                 USB_OTG_GOTGCTL_AVALOVAL_Msk  /*!< A-peripheral session valid override value */
+#define USB_OTG_GOTGCTL_BVALOEN_Pos              (6U)                          
+#define USB_OTG_GOTGCTL_BVALOEN_Msk              (0x1UL << USB_OTG_GOTGCTL_BVALOEN_Pos) /*!< 0x00000040 */
+#define USB_OTG_GOTGCTL_BVALOEN                  USB_OTG_GOTGCTL_BVALOEN_Msk   /*!< B-peripheral session valid override enable */
+#define USB_OTG_GOTGCTL_BVALOVAL_Pos             (7U)                          
+#define USB_OTG_GOTGCTL_BVALOVAL_Msk             (0x1UL << USB_OTG_GOTGCTL_BVALOVAL_Pos) /*!< 0x00000080 */
+#define USB_OTG_GOTGCTL_BVALOVAL                 USB_OTG_GOTGCTL_BVALOVAL_Msk  /*!< B-peripheral session valid override value  */
+#define USB_OTG_GOTGCTL_HNGSCS_Pos               (8U)                          
+#define USB_OTG_GOTGCTL_HNGSCS_Msk               (0x1UL << USB_OTG_GOTGCTL_HNGSCS_Pos) /*!< 0x00000100 */
+#define USB_OTG_GOTGCTL_HNGSCS                   USB_OTG_GOTGCTL_HNGSCS_Msk    /*!< Host set HNP enable */
+#define USB_OTG_GOTGCTL_HNPRQ_Pos                (9U)                          
+#define USB_OTG_GOTGCTL_HNPRQ_Msk                (0x1UL << USB_OTG_GOTGCTL_HNPRQ_Pos) /*!< 0x00000200 */
+#define USB_OTG_GOTGCTL_HNPRQ                    USB_OTG_GOTGCTL_HNPRQ_Msk     /*!< HNP request */
+#define USB_OTG_GOTGCTL_HSHNPEN_Pos              (10U)                         
+#define USB_OTG_GOTGCTL_HSHNPEN_Msk              (0x1UL << USB_OTG_GOTGCTL_HSHNPEN_Pos) /*!< 0x00000400 */
+#define USB_OTG_GOTGCTL_HSHNPEN                  USB_OTG_GOTGCTL_HSHNPEN_Msk   /*!< Host set HNP enable */
+#define USB_OTG_GOTGCTL_DHNPEN_Pos               (11U)                         
+#define USB_OTG_GOTGCTL_DHNPEN_Msk               (0x1UL << USB_OTG_GOTGCTL_DHNPEN_Pos) /*!< 0x00000800 */
+#define USB_OTG_GOTGCTL_DHNPEN                   USB_OTG_GOTGCTL_DHNPEN_Msk    /*!< Device HNP enabled */
+#define USB_OTG_GOTGCTL_EHEN_Pos                 (12U)                         
+#define USB_OTG_GOTGCTL_EHEN_Msk                 (0x1UL << USB_OTG_GOTGCTL_EHEN_Pos) /*!< 0x00001000 */
+#define USB_OTG_GOTGCTL_EHEN                     USB_OTG_GOTGCTL_EHEN_Msk      /*!< Embedded host enable */
+#define USB_OTG_GOTGCTL_CIDSTS_Pos               (16U)                         
+#define USB_OTG_GOTGCTL_CIDSTS_Msk               (0x1UL << USB_OTG_GOTGCTL_CIDSTS_Pos) /*!< 0x00010000 */
+#define USB_OTG_GOTGCTL_CIDSTS                   USB_OTG_GOTGCTL_CIDSTS_Msk    /*!< Connector ID status */
+#define USB_OTG_GOTGCTL_DBCT_Pos                 (17U)                         
+#define USB_OTG_GOTGCTL_DBCT_Msk                 (0x1UL << USB_OTG_GOTGCTL_DBCT_Pos) /*!< 0x00020000 */
+#define USB_OTG_GOTGCTL_DBCT                     USB_OTG_GOTGCTL_DBCT_Msk      /*!< Long/short debounce time */
+#define USB_OTG_GOTGCTL_ASVLD_Pos                (18U)                         
+#define USB_OTG_GOTGCTL_ASVLD_Msk                (0x1UL << USB_OTG_GOTGCTL_ASVLD_Pos) /*!< 0x00040000 */
+#define USB_OTG_GOTGCTL_ASVLD                    USB_OTG_GOTGCTL_ASVLD_Msk     /*!< A-session valid  */
+#define USB_OTG_GOTGCTL_BSESVLD_Pos              (19U)                         
+#define USB_OTG_GOTGCTL_BSESVLD_Msk              (0x1UL << USB_OTG_GOTGCTL_BSESVLD_Pos) /*!< 0x00080000 */
+#define USB_OTG_GOTGCTL_BSESVLD                  USB_OTG_GOTGCTL_BSESVLD_Msk   /*!< B-session valid */
+#define USB_OTG_GOTGCTL_OTGVER_Pos               (20U)                         
+#define USB_OTG_GOTGCTL_OTGVER_Msk               (0x1UL << USB_OTG_GOTGCTL_OTGVER_Pos) /*!< 0x00100000 */
+#define USB_OTG_GOTGCTL_OTGVER                   USB_OTG_GOTGCTL_OTGVER_Msk    /*!< OTG version  */
+
+/********************  Bit definition forUSB_OTG_HCFG register  ********************/
+
+#define USB_OTG_HCFG_FSLSPCS_Pos                 (0U)                          
+#define USB_OTG_HCFG_FSLSPCS_Msk                 (0x3UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000003 */
+#define USB_OTG_HCFG_FSLSPCS                     USB_OTG_HCFG_FSLSPCS_Msk      /*!< FS/LS PHY clock select  */
+#define USB_OTG_HCFG_FSLSPCS_0                   (0x1UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000001 */
+#define USB_OTG_HCFG_FSLSPCS_1                   (0x2UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000002 */
+#define USB_OTG_HCFG_FSLSS_Pos                   (2U)                          
+#define USB_OTG_HCFG_FSLSS_Msk                   (0x1UL << USB_OTG_HCFG_FSLSS_Pos) /*!< 0x00000004 */
+#define USB_OTG_HCFG_FSLSS                       USB_OTG_HCFG_FSLSS_Msk        /*!< FS- and LS-only support */
+
+/********************  Bit definition for USB_OTG_DCFG register  ********************/
+
+#define USB_OTG_DCFG_DSPD_Pos                    (0U)                          
+#define USB_OTG_DCFG_DSPD_Msk                    (0x3UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000003 */
+#define USB_OTG_DCFG_DSPD                        USB_OTG_DCFG_DSPD_Msk         /*!< Device speed */
+#define USB_OTG_DCFG_DSPD_0                      (0x1UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000001 */
+#define USB_OTG_DCFG_DSPD_1                      (0x2UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000002 */
+#define USB_OTG_DCFG_NZLSOHSK_Pos                (2U)                          
+#define USB_OTG_DCFG_NZLSOHSK_Msk                (0x1UL << USB_OTG_DCFG_NZLSOHSK_Pos) /*!< 0x00000004 */
+#define USB_OTG_DCFG_NZLSOHSK                    USB_OTG_DCFG_NZLSOHSK_Msk     /*!< Nonzero-length status OUT handshake */
+
+#define USB_OTG_DCFG_DAD_Pos                     (4U)                          
+#define USB_OTG_DCFG_DAD_Msk                     (0x7FUL << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */
+#define USB_OTG_DCFG_DAD                         USB_OTG_DCFG_DAD_Msk          /*!< Device address */
+#define USB_OTG_DCFG_DAD_0                       (0x01UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */
+#define USB_OTG_DCFG_DAD_1                       (0x02UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */
+#define USB_OTG_DCFG_DAD_2                       (0x04UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */
+#define USB_OTG_DCFG_DAD_3                       (0x08UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000080 */
+#define USB_OTG_DCFG_DAD_4                       (0x10UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000100 */
+#define USB_OTG_DCFG_DAD_5                       (0x20UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000200 */
+#define USB_OTG_DCFG_DAD_6                       (0x40UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000400 */
+
+#define USB_OTG_DCFG_PFIVL_Pos                   (11U)                         
+#define USB_OTG_DCFG_PFIVL_Msk                   (0x3UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */
+#define USB_OTG_DCFG_PFIVL                       USB_OTG_DCFG_PFIVL_Msk        /*!< Periodic (micro)frame interval */
+#define USB_OTG_DCFG_PFIVL_0                     (0x1UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */
+#define USB_OTG_DCFG_PFIVL_1                     (0x2UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */
+
+#define USB_OTG_DCFG_XCVRDLY_Pos                 (14U)                         
+#define USB_OTG_DCFG_XCVRDLY_Msk                 (0x1UL << USB_OTG_DCFG_XCVRDLY_Pos) /*!< 0x00004000 */
+#define USB_OTG_DCFG_XCVRDLY                     USB_OTG_DCFG_XCVRDLY_Msk        /*!< Transceiver delay */
+
+#define USB_OTG_DCFG_ERRATIM_Pos                 (15U)                         
+#define USB_OTG_DCFG_ERRATIM_Msk                 (0x1UL << USB_OTG_DCFG_ERRATIM_Pos) /*!< 0x00008000 */
+#define USB_OTG_DCFG_ERRATIM                     USB_OTG_DCFG_ERRATIM_Msk        /*!< Erratic error interrupt mask */
+
+#define USB_OTG_DCFG_PERSCHIVL_Pos               (24U)                         
+#define USB_OTG_DCFG_PERSCHIVL_Msk               (0x3UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */
+#define USB_OTG_DCFG_PERSCHIVL                   USB_OTG_DCFG_PERSCHIVL_Msk    /*!< Periodic scheduling interval */
+#define USB_OTG_DCFG_PERSCHIVL_0                 (0x1UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */
+#define USB_OTG_DCFG_PERSCHIVL_1                 (0x2UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */
+
+/********************  Bit definition for USB_OTG_PCGCR register  ********************/
+#define USB_OTG_PCGCR_STPPCLK_Pos                (0U)                          
+#define USB_OTG_PCGCR_STPPCLK_Msk                (0x1UL << USB_OTG_PCGCR_STPPCLK_Pos) /*!< 0x00000001 */
+#define USB_OTG_PCGCR_STPPCLK                    USB_OTG_PCGCR_STPPCLK_Msk     /*!< Stop PHY clock */
+#define USB_OTG_PCGCR_GATEHCLK_Pos               (1U)                          
+#define USB_OTG_PCGCR_GATEHCLK_Msk               (0x1UL << USB_OTG_PCGCR_GATEHCLK_Pos) /*!< 0x00000002 */
+#define USB_OTG_PCGCR_GATEHCLK                   USB_OTG_PCGCR_GATEHCLK_Msk    /*!< Gate HCLK */
+#define USB_OTG_PCGCR_PHYSUSP_Pos                (4U)                          
+#define USB_OTG_PCGCR_PHYSUSP_Msk                (0x1UL << USB_OTG_PCGCR_PHYSUSP_Pos) /*!< 0x00000010 */
+#define USB_OTG_PCGCR_PHYSUSP                    USB_OTG_PCGCR_PHYSUSP_Msk     /*!< PHY suspended */
+
+/********************  Bit definition for USB_OTG_GOTGINT register  ********************/
+#define USB_OTG_GOTGINT_SEDET_Pos                (2U)                          
+#define USB_OTG_GOTGINT_SEDET_Msk                (0x1UL << USB_OTG_GOTGINT_SEDET_Pos) /*!< 0x00000004 */
+#define USB_OTG_GOTGINT_SEDET                    USB_OTG_GOTGINT_SEDET_Msk     /*!< Session end detected                   */
+#define USB_OTG_GOTGINT_SRSSCHG_Pos              (8U)                          
+#define USB_OTG_GOTGINT_SRSSCHG_Msk              (0x1UL << USB_OTG_GOTGINT_SRSSCHG_Pos) /*!< 0x00000100 */
+#define USB_OTG_GOTGINT_SRSSCHG                  USB_OTG_GOTGINT_SRSSCHG_Msk   /*!< Session request success status change  */
+#define USB_OTG_GOTGINT_HNSSCHG_Pos              (9U)                          
+#define USB_OTG_GOTGINT_HNSSCHG_Msk              (0x1UL << USB_OTG_GOTGINT_HNSSCHG_Pos) /*!< 0x00000200 */
+#define USB_OTG_GOTGINT_HNSSCHG                  USB_OTG_GOTGINT_HNSSCHG_Msk   /*!< Host negotiation success status change */
+#define USB_OTG_GOTGINT_HNGDET_Pos               (17U)                         
+#define USB_OTG_GOTGINT_HNGDET_Msk               (0x1UL << USB_OTG_GOTGINT_HNGDET_Pos) /*!< 0x00020000 */
+#define USB_OTG_GOTGINT_HNGDET                   USB_OTG_GOTGINT_HNGDET_Msk    /*!< Host negotiation detected              */
+#define USB_OTG_GOTGINT_ADTOCHG_Pos              (18U)                         
+#define USB_OTG_GOTGINT_ADTOCHG_Msk              (0x1UL << USB_OTG_GOTGINT_ADTOCHG_Pos) /*!< 0x00040000 */
+#define USB_OTG_GOTGINT_ADTOCHG                  USB_OTG_GOTGINT_ADTOCHG_Msk   /*!< A-device timeout change                */
+#define USB_OTG_GOTGINT_DBCDNE_Pos               (19U)                         
+#define USB_OTG_GOTGINT_DBCDNE_Msk               (0x1UL << USB_OTG_GOTGINT_DBCDNE_Pos) /*!< 0x00080000 */
+#define USB_OTG_GOTGINT_DBCDNE                   USB_OTG_GOTGINT_DBCDNE_Msk    /*!< Debounce done                          */
+#define USB_OTG_GOTGINT_IDCHNG_Pos               (20U)                         
+#define USB_OTG_GOTGINT_IDCHNG_Msk               (0x1UL << USB_OTG_GOTGINT_IDCHNG_Pos) /*!< 0x00100000 */
+#define USB_OTG_GOTGINT_IDCHNG                   USB_OTG_GOTGINT_IDCHNG_Msk    /*!< Change in ID pin input value           */
+
+/********************  Bit definition for USB_OTG_DCTL register  ********************/
+#define USB_OTG_DCTL_RWUSIG_Pos                  (0U)                          
+#define USB_OTG_DCTL_RWUSIG_Msk                  (0x1UL << USB_OTG_DCTL_RWUSIG_Pos) /*!< 0x00000001 */
+#define USB_OTG_DCTL_RWUSIG                      USB_OTG_DCTL_RWUSIG_Msk       /*!< Remote wakeup signaling */
+#define USB_OTG_DCTL_SDIS_Pos                    (1U)                          
+#define USB_OTG_DCTL_SDIS_Msk                    (0x1UL << USB_OTG_DCTL_SDIS_Pos) /*!< 0x00000002 */
+#define USB_OTG_DCTL_SDIS                        USB_OTG_DCTL_SDIS_Msk         /*!< Soft disconnect         */
+#define USB_OTG_DCTL_GINSTS_Pos                  (2U)                          
+#define USB_OTG_DCTL_GINSTS_Msk                  (0x1UL << USB_OTG_DCTL_GINSTS_Pos) /*!< 0x00000004 */
+#define USB_OTG_DCTL_GINSTS                      USB_OTG_DCTL_GINSTS_Msk       /*!< Global IN NAK status    */
+#define USB_OTG_DCTL_GONSTS_Pos                  (3U)                          
+#define USB_OTG_DCTL_GONSTS_Msk                  (0x1UL << USB_OTG_DCTL_GONSTS_Pos) /*!< 0x00000008 */
+#define USB_OTG_DCTL_GONSTS                      USB_OTG_DCTL_GONSTS_Msk       /*!< Global OUT NAK status   */
+
+#define USB_OTG_DCTL_TCTL_Pos                    (4U)                          
+#define USB_OTG_DCTL_TCTL_Msk                    (0x7UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000070 */
+#define USB_OTG_DCTL_TCTL                        USB_OTG_DCTL_TCTL_Msk         /*!< Test control */
+#define USB_OTG_DCTL_TCTL_0                      (0x1UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000010 */
+#define USB_OTG_DCTL_TCTL_1                      (0x2UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000020 */
+#define USB_OTG_DCTL_TCTL_2                      (0x4UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000040 */
+#define USB_OTG_DCTL_SGINAK_Pos                  (7U)                          
+#define USB_OTG_DCTL_SGINAK_Msk                  (0x1UL << USB_OTG_DCTL_SGINAK_Pos) /*!< 0x00000080 */
+#define USB_OTG_DCTL_SGINAK                      USB_OTG_DCTL_SGINAK_Msk       /*!< Set global IN NAK         */
+#define USB_OTG_DCTL_CGINAK_Pos                  (8U)                          
+#define USB_OTG_DCTL_CGINAK_Msk                  (0x1UL << USB_OTG_DCTL_CGINAK_Pos) /*!< 0x00000100 */
+#define USB_OTG_DCTL_CGINAK                      USB_OTG_DCTL_CGINAK_Msk       /*!< Clear global IN NAK       */
+#define USB_OTG_DCTL_SGONAK_Pos                  (9U)                          
+#define USB_OTG_DCTL_SGONAK_Msk                  (0x1UL << USB_OTG_DCTL_SGONAK_Pos) /*!< 0x00000200 */
+#define USB_OTG_DCTL_SGONAK                      USB_OTG_DCTL_SGONAK_Msk       /*!< Set global OUT NAK        */
+#define USB_OTG_DCTL_CGONAK_Pos                  (10U)                         
+#define USB_OTG_DCTL_CGONAK_Msk                  (0x1UL << USB_OTG_DCTL_CGONAK_Pos) /*!< 0x00000400 */
+#define USB_OTG_DCTL_CGONAK                      USB_OTG_DCTL_CGONAK_Msk       /*!< Clear global OUT NAK      */
+#define USB_OTG_DCTL_POPRGDNE_Pos                (11U)                         
+#define USB_OTG_DCTL_POPRGDNE_Msk                (0x1UL << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */
+#define USB_OTG_DCTL_POPRGDNE                    USB_OTG_DCTL_POPRGDNE_Msk     /*!< Power-on programming done */
+
+/********************  Bit definition for USB_OTG_HFIR register  ********************/
+#define USB_OTG_HFIR_FRIVL_Pos                   (0U)                          
+#define USB_OTG_HFIR_FRIVL_Msk                   (0xFFFFUL << USB_OTG_HFIR_FRIVL_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HFIR_FRIVL                       USB_OTG_HFIR_FRIVL_Msk        /*!< Frame interval */
+
+/********************  Bit definition for USB_OTG_HFNUM register  ********************/
+#define USB_OTG_HFNUM_FRNUM_Pos                  (0U)                          
+#define USB_OTG_HFNUM_FRNUM_Msk                  (0xFFFFUL << USB_OTG_HFNUM_FRNUM_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HFNUM_FRNUM                      USB_OTG_HFNUM_FRNUM_Msk       /*!< Frame number         */
+#define USB_OTG_HFNUM_FTREM_Pos                  (16U)                         
+#define USB_OTG_HFNUM_FTREM_Msk                  (0xFFFFUL << USB_OTG_HFNUM_FTREM_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_HFNUM_FTREM                      USB_OTG_HFNUM_FTREM_Msk       /*!< Frame time remaining */
+
+/********************  Bit definition for USB_OTG_DSTS register  ********************/
+#define USB_OTG_DSTS_SUSPSTS_Pos                 (0U)                          
+#define USB_OTG_DSTS_SUSPSTS_Msk                 (0x1UL << USB_OTG_DSTS_SUSPSTS_Pos) /*!< 0x00000001 */
+#define USB_OTG_DSTS_SUSPSTS                     USB_OTG_DSTS_SUSPSTS_Msk      /*!< Suspend status   */
+
+#define USB_OTG_DSTS_ENUMSPD_Pos                 (1U)                          
+#define USB_OTG_DSTS_ENUMSPD_Msk                 (0x3UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000006 */
+#define USB_OTG_DSTS_ENUMSPD                     USB_OTG_DSTS_ENUMSPD_Msk      /*!< Enumerated speed */
+#define USB_OTG_DSTS_ENUMSPD_0                   (0x1UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000002 */
+#define USB_OTG_DSTS_ENUMSPD_1                   (0x2UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000004 */
+#define USB_OTG_DSTS_EERR_Pos                    (3U)                          
+#define USB_OTG_DSTS_EERR_Msk                    (0x1UL << USB_OTG_DSTS_EERR_Pos) /*!< 0x00000008 */
+#define USB_OTG_DSTS_EERR                        USB_OTG_DSTS_EERR_Msk         /*!< Erratic error     */
+#define USB_OTG_DSTS_FNSOF_Pos                   (8U)                          
+#define USB_OTG_DSTS_FNSOF_Msk                   (0x3FFFUL << USB_OTG_DSTS_FNSOF_Pos) /*!< 0x003FFF00 */
+#define USB_OTG_DSTS_FNSOF                       USB_OTG_DSTS_FNSOF_Msk        /*!< Frame number of the received SOF */
+
+/********************  Bit definition for USB_OTG_GAHBCFG register  ********************/
+#define USB_OTG_GAHBCFG_GINT_Pos                 (0U)                          
+#define USB_OTG_GAHBCFG_GINT_Msk                 (0x1UL << USB_OTG_GAHBCFG_GINT_Pos) /*!< 0x00000001 */
+#define USB_OTG_GAHBCFG_GINT                     USB_OTG_GAHBCFG_GINT_Msk      /*!< Global interrupt mask */
+#define USB_OTG_GAHBCFG_HBSTLEN_Pos              (1U)                          
+#define USB_OTG_GAHBCFG_HBSTLEN_Msk              (0xFUL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x0000001E */
+#define USB_OTG_GAHBCFG_HBSTLEN                  USB_OTG_GAHBCFG_HBSTLEN_Msk   /*!< Burst length/type */
+#define USB_OTG_GAHBCFG_HBSTLEN_0                (0x0UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< Single */
+#define USB_OTG_GAHBCFG_HBSTLEN_1                (0x1UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR */
+#define USB_OTG_GAHBCFG_HBSTLEN_2                (0x3UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR4 */
+#define USB_OTG_GAHBCFG_HBSTLEN_3                (0x5UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR8 */
+#define USB_OTG_GAHBCFG_HBSTLEN_4                (0x7UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR16 */
+#define USB_OTG_GAHBCFG_DMAEN_Pos                (5U)                          
+#define USB_OTG_GAHBCFG_DMAEN_Msk                (0x1UL << USB_OTG_GAHBCFG_DMAEN_Pos) /*!< 0x00000020 */
+#define USB_OTG_GAHBCFG_DMAEN                    USB_OTG_GAHBCFG_DMAEN_Msk     /*!< DMA enable */
+#define USB_OTG_GAHBCFG_TXFELVL_Pos              (7U)                          
+#define USB_OTG_GAHBCFG_TXFELVL_Msk              (0x1UL << USB_OTG_GAHBCFG_TXFELVL_Pos) /*!< 0x00000080 */
+#define USB_OTG_GAHBCFG_TXFELVL                  USB_OTG_GAHBCFG_TXFELVL_Msk   /*!< TxFIFO empty level */
+#define USB_OTG_GAHBCFG_PTXFELVL_Pos             (8U)                          
+#define USB_OTG_GAHBCFG_PTXFELVL_Msk             (0x1UL << USB_OTG_GAHBCFG_PTXFELVL_Pos) /*!< 0x00000100 */
+#define USB_OTG_GAHBCFG_PTXFELVL                 USB_OTG_GAHBCFG_PTXFELVL_Msk  /*!< Periodic TxFIFO empty level */
+
+/********************  Bit definition for USB_OTG_GUSBCFG register  ********************/
+
+#define USB_OTG_GUSBCFG_TOCAL_Pos                (0U)                          
+#define USB_OTG_GUSBCFG_TOCAL_Msk                (0x7UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000007 */
+#define USB_OTG_GUSBCFG_TOCAL                    USB_OTG_GUSBCFG_TOCAL_Msk     /*!< FS timeout calibration */
+#define USB_OTG_GUSBCFG_TOCAL_0                  (0x1UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000001 */
+#define USB_OTG_GUSBCFG_TOCAL_1                  (0x2UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000002 */
+#define USB_OTG_GUSBCFG_TOCAL_2                  (0x4UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000004 */
+#define USB_OTG_GUSBCFG_PHYSEL_Pos               (6U)                          
+#define USB_OTG_GUSBCFG_PHYSEL_Msk               (0x1UL << USB_OTG_GUSBCFG_PHYSEL_Pos) /*!< 0x00000040 */
+#define USB_OTG_GUSBCFG_PHYSEL                   USB_OTG_GUSBCFG_PHYSEL_Msk    /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
+#define USB_OTG_GUSBCFG_SRPCAP_Pos               (8U)                          
+#define USB_OTG_GUSBCFG_SRPCAP_Msk               (0x1UL << USB_OTG_GUSBCFG_SRPCAP_Pos) /*!< 0x00000100 */
+#define USB_OTG_GUSBCFG_SRPCAP                   USB_OTG_GUSBCFG_SRPCAP_Msk    /*!< SRP-capable */
+#define USB_OTG_GUSBCFG_HNPCAP_Pos               (9U)                          
+#define USB_OTG_GUSBCFG_HNPCAP_Msk               (0x1UL << USB_OTG_GUSBCFG_HNPCAP_Pos) /*!< 0x00000200 */
+#define USB_OTG_GUSBCFG_HNPCAP                   USB_OTG_GUSBCFG_HNPCAP_Msk    /*!< HNP-capable */
+#define USB_OTG_GUSBCFG_TRDT_Pos                 (10U)                         
+#define USB_OTG_GUSBCFG_TRDT_Msk                 (0xFUL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00003C00 */
+#define USB_OTG_GUSBCFG_TRDT                     USB_OTG_GUSBCFG_TRDT_Msk      /*!< USB turnaround time */
+#define USB_OTG_GUSBCFG_TRDT_0                   (0x1UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000400 */
+#define USB_OTG_GUSBCFG_TRDT_1                   (0x2UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000800 */
+#define USB_OTG_GUSBCFG_TRDT_2                   (0x4UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00001000 */
+#define USB_OTG_GUSBCFG_TRDT_3                   (0x8UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00002000 */
+#define USB_OTG_GUSBCFG_PHYLPCS_Pos              (15U)                         
+#define USB_OTG_GUSBCFG_PHYLPCS_Msk              (0x1UL << USB_OTG_GUSBCFG_PHYLPCS_Pos) /*!< 0x00008000 */
+#define USB_OTG_GUSBCFG_PHYLPCS                  USB_OTG_GUSBCFG_PHYLPCS_Msk   /*!< PHY Low-power clock select */
+#define USB_OTG_GUSBCFG_ULPIFSLS_Pos             (17U)                         
+#define USB_OTG_GUSBCFG_ULPIFSLS_Msk             (0x1UL << USB_OTG_GUSBCFG_ULPIFSLS_Pos) /*!< 0x00020000 */
+#define USB_OTG_GUSBCFG_ULPIFSLS                 USB_OTG_GUSBCFG_ULPIFSLS_Msk  /*!< ULPI FS/LS select               */
+#define USB_OTG_GUSBCFG_ULPIAR_Pos               (18U)                         
+#define USB_OTG_GUSBCFG_ULPIAR_Msk               (0x1UL << USB_OTG_GUSBCFG_ULPIAR_Pos) /*!< 0x00040000 */
+#define USB_OTG_GUSBCFG_ULPIAR                   USB_OTG_GUSBCFG_ULPIAR_Msk    /*!< ULPI Auto-resume                */
+#define USB_OTG_GUSBCFG_ULPICSM_Pos              (19U)                         
+#define USB_OTG_GUSBCFG_ULPICSM_Msk              (0x1UL << USB_OTG_GUSBCFG_ULPICSM_Pos) /*!< 0x00080000 */
+#define USB_OTG_GUSBCFG_ULPICSM                  USB_OTG_GUSBCFG_ULPICSM_Msk   /*!< ULPI Clock SuspendM             */
+#define USB_OTG_GUSBCFG_ULPIEVBUSD_Pos           (20U)                         
+#define USB_OTG_GUSBCFG_ULPIEVBUSD_Msk           (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSD_Pos) /*!< 0x00100000 */
+#define USB_OTG_GUSBCFG_ULPIEVBUSD               USB_OTG_GUSBCFG_ULPIEVBUSD_Msk /*!< ULPI External VBUS Drive        */
+#define USB_OTG_GUSBCFG_ULPIEVBUSI_Pos           (21U)                         
+#define USB_OTG_GUSBCFG_ULPIEVBUSI_Msk           (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSI_Pos) /*!< 0x00200000 */
+#define USB_OTG_GUSBCFG_ULPIEVBUSI               USB_OTG_GUSBCFG_ULPIEVBUSI_Msk /*!< ULPI external VBUS indicator    */
+#define USB_OTG_GUSBCFG_TSDPS_Pos                (22U)                         
+#define USB_OTG_GUSBCFG_TSDPS_Msk                (0x1UL << USB_OTG_GUSBCFG_TSDPS_Pos) /*!< 0x00400000 */
+#define USB_OTG_GUSBCFG_TSDPS                    USB_OTG_GUSBCFG_TSDPS_Msk     /*!< TermSel DLine pulsing selection */
+#define USB_OTG_GUSBCFG_PCCI_Pos                 (23U)                         
+#define USB_OTG_GUSBCFG_PCCI_Msk                 (0x1UL << USB_OTG_GUSBCFG_PCCI_Pos) /*!< 0x00800000 */
+#define USB_OTG_GUSBCFG_PCCI                     USB_OTG_GUSBCFG_PCCI_Msk      /*!< Indicator complement            */
+#define USB_OTG_GUSBCFG_PTCI_Pos                 (24U)                         
+#define USB_OTG_GUSBCFG_PTCI_Msk                 (0x1UL << USB_OTG_GUSBCFG_PTCI_Pos) /*!< 0x01000000 */
+#define USB_OTG_GUSBCFG_PTCI                     USB_OTG_GUSBCFG_PTCI_Msk      /*!< Indicator pass through          */
+#define USB_OTG_GUSBCFG_ULPIIPD_Pos              (25U)                         
+#define USB_OTG_GUSBCFG_ULPIIPD_Msk              (0x1UL << USB_OTG_GUSBCFG_ULPIIPD_Pos) /*!< 0x02000000 */
+#define USB_OTG_GUSBCFG_ULPIIPD                  USB_OTG_GUSBCFG_ULPIIPD_Msk   /*!< ULPI interface protect disable  */
+#define USB_OTG_GUSBCFG_FHMOD_Pos                (29U)                         
+#define USB_OTG_GUSBCFG_FHMOD_Msk                (0x1UL << USB_OTG_GUSBCFG_FHMOD_Pos) /*!< 0x20000000 */
+#define USB_OTG_GUSBCFG_FHMOD                    USB_OTG_GUSBCFG_FHMOD_Msk     /*!< Forced host mode                */
+#define USB_OTG_GUSBCFG_FDMOD_Pos                (30U)                         
+#define USB_OTG_GUSBCFG_FDMOD_Msk                (0x1UL << USB_OTG_GUSBCFG_FDMOD_Pos) /*!< 0x40000000 */
+#define USB_OTG_GUSBCFG_FDMOD                    USB_OTG_GUSBCFG_FDMOD_Msk     /*!< Forced peripheral mode          */
+#define USB_OTG_GUSBCFG_CTXPKT_Pos               (31U)                         
+#define USB_OTG_GUSBCFG_CTXPKT_Msk               (0x1UL << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */
+#define USB_OTG_GUSBCFG_CTXPKT                   USB_OTG_GUSBCFG_CTXPKT_Msk    /*!< Corrupt Tx packet               */
+
+/********************  Bit definition for USB_OTG_GRSTCTL register  ********************/
+#define USB_OTG_GRSTCTL_CSRST_Pos                (0U)                          
+#define USB_OTG_GRSTCTL_CSRST_Msk                (0x1UL << USB_OTG_GRSTCTL_CSRST_Pos) /*!< 0x00000001 */
+#define USB_OTG_GRSTCTL_CSRST                    USB_OTG_GRSTCTL_CSRST_Msk     /*!< Core soft reset          */
+#define USB_OTG_GRSTCTL_HSRST_Pos                (1U)                          
+#define USB_OTG_GRSTCTL_HSRST_Msk                (0x1UL << USB_OTG_GRSTCTL_HSRST_Pos) /*!< 0x00000002 */
+#define USB_OTG_GRSTCTL_HSRST                    USB_OTG_GRSTCTL_HSRST_Msk     /*!< HCLK soft reset          */
+#define USB_OTG_GRSTCTL_FCRST_Pos                (2U)                          
+#define USB_OTG_GRSTCTL_FCRST_Msk                (0x1UL << USB_OTG_GRSTCTL_FCRST_Pos) /*!< 0x00000004 */
+#define USB_OTG_GRSTCTL_FCRST                    USB_OTG_GRSTCTL_FCRST_Msk     /*!< Host frame counter reset */
+#define USB_OTG_GRSTCTL_RXFFLSH_Pos              (4U)                          
+#define USB_OTG_GRSTCTL_RXFFLSH_Msk              (0x1UL << USB_OTG_GRSTCTL_RXFFLSH_Pos) /*!< 0x00000010 */
+#define USB_OTG_GRSTCTL_RXFFLSH                  USB_OTG_GRSTCTL_RXFFLSH_Msk   /*!< RxFIFO flush             */
+#define USB_OTG_GRSTCTL_TXFFLSH_Pos              (5U)                          
+#define USB_OTG_GRSTCTL_TXFFLSH_Msk              (0x1UL << USB_OTG_GRSTCTL_TXFFLSH_Pos) /*!< 0x00000020 */
+#define USB_OTG_GRSTCTL_TXFFLSH                  USB_OTG_GRSTCTL_TXFFLSH_Msk   /*!< TxFIFO flush             */
+
+
+#define USB_OTG_GRSTCTL_TXFNUM_Pos               (6U)                          
+#define USB_OTG_GRSTCTL_TXFNUM_Msk               (0x1FUL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x000007C0 */
+#define USB_OTG_GRSTCTL_TXFNUM                   USB_OTG_GRSTCTL_TXFNUM_Msk    /*!< TxFIFO number */
+#define USB_OTG_GRSTCTL_TXFNUM_0                 (0x01UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000040 */
+#define USB_OTG_GRSTCTL_TXFNUM_1                 (0x02UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000080 */
+#define USB_OTG_GRSTCTL_TXFNUM_2                 (0x04UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000100 */
+#define USB_OTG_GRSTCTL_TXFNUM_3                 (0x08UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000200 */
+#define USB_OTG_GRSTCTL_TXFNUM_4                 (0x10UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000400 */
+#define USB_OTG_GRSTCTL_DMAREQ_Pos               (30U)                         
+#define USB_OTG_GRSTCTL_DMAREQ_Msk               (0x1UL << USB_OTG_GRSTCTL_DMAREQ_Pos) /*!< 0x40000000 */
+#define USB_OTG_GRSTCTL_DMAREQ                   USB_OTG_GRSTCTL_DMAREQ_Msk    /*!< DMA request signal */
+#define USB_OTG_GRSTCTL_AHBIDL_Pos               (31U)                         
+#define USB_OTG_GRSTCTL_AHBIDL_Msk               (0x1UL << USB_OTG_GRSTCTL_AHBIDL_Pos) /*!< 0x80000000 */
+#define USB_OTG_GRSTCTL_AHBIDL                   USB_OTG_GRSTCTL_AHBIDL_Msk    /*!< AHB master idle */
+
+/********************  Bit definition for USB_OTG_DIEPMSK register  ********************/
+#define USB_OTG_DIEPMSK_XFRCM_Pos                (0U)                          
+#define USB_OTG_DIEPMSK_XFRCM_Msk                (0x1UL << USB_OTG_DIEPMSK_XFRCM_Pos) /*!< 0x00000001 */
+#define USB_OTG_DIEPMSK_XFRCM                    USB_OTG_DIEPMSK_XFRCM_Msk     /*!< Transfer completed interrupt mask                 */
+#define USB_OTG_DIEPMSK_EPDM_Pos                 (1U)                          
+#define USB_OTG_DIEPMSK_EPDM_Msk                 (0x1UL << USB_OTG_DIEPMSK_EPDM_Pos) /*!< 0x00000002 */
+#define USB_OTG_DIEPMSK_EPDM                     USB_OTG_DIEPMSK_EPDM_Msk      /*!< Endpoint disabled interrupt mask                  */
+#define USB_OTG_DIEPMSK_TOM_Pos                  (3U)                          
+#define USB_OTG_DIEPMSK_TOM_Msk                  (0x1UL << USB_OTG_DIEPMSK_TOM_Pos) /*!< 0x00000008 */
+#define USB_OTG_DIEPMSK_TOM                      USB_OTG_DIEPMSK_TOM_Msk       /*!< Timeout condition mask (nonisochronous endpoints) */
+#define USB_OTG_DIEPMSK_ITTXFEMSK_Pos            (4U)                          
+#define USB_OTG_DIEPMSK_ITTXFEMSK_Msk            (0x1UL << USB_OTG_DIEPMSK_ITTXFEMSK_Pos) /*!< 0x00000010 */
+#define USB_OTG_DIEPMSK_ITTXFEMSK                USB_OTG_DIEPMSK_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask          */
+#define USB_OTG_DIEPMSK_INEPNMM_Pos              (5U)                          
+#define USB_OTG_DIEPMSK_INEPNMM_Msk              (0x1UL << USB_OTG_DIEPMSK_INEPNMM_Pos) /*!< 0x00000020 */
+#define USB_OTG_DIEPMSK_INEPNMM                  USB_OTG_DIEPMSK_INEPNMM_Msk   /*!< IN token received with EP mismatch mask           */
+#define USB_OTG_DIEPMSK_INEPNEM_Pos              (6U)                          
+#define USB_OTG_DIEPMSK_INEPNEM_Msk              (0x1UL << USB_OTG_DIEPMSK_INEPNEM_Pos) /*!< 0x00000040 */
+#define USB_OTG_DIEPMSK_INEPNEM                  USB_OTG_DIEPMSK_INEPNEM_Msk   /*!< IN endpoint NAK effective mask                    */
+#define USB_OTG_DIEPMSK_TXFURM_Pos               (8U)                          
+#define USB_OTG_DIEPMSK_TXFURM_Msk               (0x1UL << USB_OTG_DIEPMSK_TXFURM_Pos) /*!< 0x00000100 */
+#define USB_OTG_DIEPMSK_TXFURM                   USB_OTG_DIEPMSK_TXFURM_Msk    /*!< FIFO underrun mask                                */
+#define USB_OTG_DIEPMSK_BIM_Pos                  (9U)                          
+#define USB_OTG_DIEPMSK_BIM_Msk                  (0x1UL << USB_OTG_DIEPMSK_BIM_Pos) /*!< 0x00000200 */
+#define USB_OTG_DIEPMSK_BIM                      USB_OTG_DIEPMSK_BIM_Msk       /*!< BNA interrupt mask                                */
+
+/********************  Bit definition for USB_OTG_HPTXSTS register  ********************/
+#define USB_OTG_HPTXSTS_PTXFSAVL_Pos             (0U)                          
+#define USB_OTG_HPTXSTS_PTXFSAVL_Msk             (0xFFFFUL << USB_OTG_HPTXSTS_PTXFSAVL_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HPTXSTS_PTXFSAVL                 USB_OTG_HPTXSTS_PTXFSAVL_Msk  /*!< Periodic transmit data FIFO space available     */
+#define USB_OTG_HPTXSTS_PTXQSAV_Pos              (16U)                         
+#define USB_OTG_HPTXSTS_PTXQSAV_Msk              (0xFFUL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00FF0000 */
+#define USB_OTG_HPTXSTS_PTXQSAV                  USB_OTG_HPTXSTS_PTXQSAV_Msk   /*!< Periodic transmit request queue space available */
+#define USB_OTG_HPTXSTS_PTXQSAV_0                (0x01UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00010000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_1                (0x02UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00020000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_2                (0x04UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00040000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_3                (0x08UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00080000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_4                (0x10UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00100000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_5                (0x20UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00200000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_6                (0x40UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00400000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_7                (0x80UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00800000 */
+
+#define USB_OTG_HPTXSTS_PTXQTOP_Pos              (24U)                         
+#define USB_OTG_HPTXSTS_PTXQTOP_Msk              (0xFFUL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0xFF000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP                  USB_OTG_HPTXSTS_PTXQTOP_Msk   /*!< Top of the periodic transmit request queue */
+#define USB_OTG_HPTXSTS_PTXQTOP_0                (0x01UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x01000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_1                (0x02UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x02000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_2                (0x04UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x04000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_3                (0x08UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x08000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_4                (0x10UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x10000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_5                (0x20UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x20000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_6                (0x40UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x40000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_7                (0x80UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x80000000 */
+
+/********************  Bit definition for USB_OTG_HAINT register  ********************/
+#define USB_OTG_HAINT_HAINT_Pos                  (0U)                          
+#define USB_OTG_HAINT_HAINT_Msk                  (0xFFFFUL << USB_OTG_HAINT_HAINT_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HAINT_HAINT                      USB_OTG_HAINT_HAINT_Msk       /*!< Channel interrupts */
+
+/********************  Bit definition for USB_OTG_DOEPMSK register  ********************/
+#define USB_OTG_DOEPMSK_XFRCM_Pos                (0U)                          
+#define USB_OTG_DOEPMSK_XFRCM_Msk                (0x1UL << USB_OTG_DOEPMSK_XFRCM_Pos) /*!< 0x00000001 */
+#define USB_OTG_DOEPMSK_XFRCM                    USB_OTG_DOEPMSK_XFRCM_Msk     /*!< Transfer completed interrupt mask              */
+#define USB_OTG_DOEPMSK_EPDM_Pos                 (1U)                          
+#define USB_OTG_DOEPMSK_EPDM_Msk                 (0x1UL << USB_OTG_DOEPMSK_EPDM_Pos) /*!< 0x00000002 */
+#define USB_OTG_DOEPMSK_EPDM                     USB_OTG_DOEPMSK_EPDM_Msk      /*!< Endpoint disabled interrupt mask               */
+#define USB_OTG_DOEPMSK_AHBERRM_Pos              (2U)
+#define USB_OTG_DOEPMSK_AHBERRM_Msk              (0x1UL << USB_OTG_DOEPMSK_AHBERRM_Pos) /*!< 0x00000004 */
+#define USB_OTG_DOEPMSK_AHBERRM                  USB_OTG_DOEPMSK_AHBERRM_Msk   /*!< OUT transaction AHB Error interrupt mask       */
+#define USB_OTG_DOEPMSK_STUPM_Pos                (3U)                          
+#define USB_OTG_DOEPMSK_STUPM_Msk                (0x1UL << USB_OTG_DOEPMSK_STUPM_Pos) /*!< 0x00000008 */
+#define USB_OTG_DOEPMSK_STUPM                    USB_OTG_DOEPMSK_STUPM_Msk     /*!< SETUP phase done mask                          */
+#define USB_OTG_DOEPMSK_OTEPDM_Pos               (4U)                          
+#define USB_OTG_DOEPMSK_OTEPDM_Msk               (0x1UL << USB_OTG_DOEPMSK_OTEPDM_Pos) /*!< 0x00000010 */
+#define USB_OTG_DOEPMSK_OTEPDM                   USB_OTG_DOEPMSK_OTEPDM_Msk    /*!< OUT token received when endpoint disabled mask */
+#define USB_OTG_DOEPMSK_OTEPSPRM_Pos             (5U)                          
+#define USB_OTG_DOEPMSK_OTEPSPRM_Msk             (0x1UL << USB_OTG_DOEPMSK_OTEPSPRM_Pos) /*!< 0x00000020 */
+#define USB_OTG_DOEPMSK_OTEPSPRM                 USB_OTG_DOEPMSK_OTEPSPRM_Msk  /*!< Status Phase Received mask                     */
+#define USB_OTG_DOEPMSK_B2BSTUP_Pos              (6U)                          
+#define USB_OTG_DOEPMSK_B2BSTUP_Msk              (0x1UL << USB_OTG_DOEPMSK_B2BSTUP_Pos) /*!< 0x00000040 */
+#define USB_OTG_DOEPMSK_B2BSTUP                  USB_OTG_DOEPMSK_B2BSTUP_Msk   /*!< Back-to-back SETUP packets received mask       */
+#define USB_OTG_DOEPMSK_OPEM_Pos                 (8U)                          
+#define USB_OTG_DOEPMSK_OPEM_Msk                 (0x1UL << USB_OTG_DOEPMSK_OPEM_Pos) /*!< 0x00000100 */
+#define USB_OTG_DOEPMSK_OPEM                     USB_OTG_DOEPMSK_OPEM_Msk      /*!< OUT packet error mask                          */
+#define USB_OTG_DOEPMSK_BOIM_Pos                 (9U)                          
+#define USB_OTG_DOEPMSK_BOIM_Msk                 (0x1UL << USB_OTG_DOEPMSK_BOIM_Pos) /*!< 0x00000200 */
+#define USB_OTG_DOEPMSK_BOIM                     USB_OTG_DOEPMSK_BOIM_Msk      /*!< BNA interrupt mask                             */
+#define USB_OTG_DOEPMSK_BERRM_Pos                (12U)
+#define USB_OTG_DOEPMSK_BERRM_Msk                (0x1UL << USB_OTG_DOEPMSK_BERRM_Pos) /*!< 0x00001000 */
+#define USB_OTG_DOEPMSK_BERRM                    USB_OTG_DOEPMSK_BERRM_Msk      /*!< Babble error interrupt mask                   */
+#define USB_OTG_DOEPMSK_NAKM_Pos                 (13U)
+#define USB_OTG_DOEPMSK_NAKM_Msk                 (0x1UL << USB_OTG_DOEPMSK_NAKM_Pos) /*!< 0x00002000 */
+#define USB_OTG_DOEPMSK_NAKM                     USB_OTG_DOEPMSK_NAKM_Msk      /*!< OUT Packet NAK interrupt mask                  */
+#define USB_OTG_DOEPMSK_NYETM_Pos                (14U)
+#define USB_OTG_DOEPMSK_NYETM_Msk                (0x1UL << USB_OTG_DOEPMSK_NYETM_Pos) /*!< 0x00004000 */
+#define USB_OTG_DOEPMSK_NYETM                    USB_OTG_DOEPMSK_NYETM_Msk     /*!< NYET interrupt mask                            */
+/********************  Bit definition for USB_OTG_GINTSTS register  ********************/
+#define USB_OTG_GINTSTS_CMOD_Pos                 (0U)                          
+#define USB_OTG_GINTSTS_CMOD_Msk                 (0x1UL << USB_OTG_GINTSTS_CMOD_Pos) /*!< 0x00000001 */
+#define USB_OTG_GINTSTS_CMOD                     USB_OTG_GINTSTS_CMOD_Msk      /*!< Current mode of operation                      */
+#define USB_OTG_GINTSTS_MMIS_Pos                 (1U)                          
+#define USB_OTG_GINTSTS_MMIS_Msk                 (0x1UL << USB_OTG_GINTSTS_MMIS_Pos) /*!< 0x00000002 */
+#define USB_OTG_GINTSTS_MMIS                     USB_OTG_GINTSTS_MMIS_Msk      /*!< Mode mismatch interrupt                        */
+#define USB_OTG_GINTSTS_OTGINT_Pos               (2U)                          
+#define USB_OTG_GINTSTS_OTGINT_Msk               (0x1UL << USB_OTG_GINTSTS_OTGINT_Pos) /*!< 0x00000004 */
+#define USB_OTG_GINTSTS_OTGINT                   USB_OTG_GINTSTS_OTGINT_Msk    /*!< OTG interrupt                                  */
+#define USB_OTG_GINTSTS_SOF_Pos                  (3U)                          
+#define USB_OTG_GINTSTS_SOF_Msk                  (0x1UL << USB_OTG_GINTSTS_SOF_Pos) /*!< 0x00000008 */
+#define USB_OTG_GINTSTS_SOF                      USB_OTG_GINTSTS_SOF_Msk       /*!< Start of frame                                 */
+#define USB_OTG_GINTSTS_RXFLVL_Pos               (4U)                          
+#define USB_OTG_GINTSTS_RXFLVL_Msk               (0x1UL << USB_OTG_GINTSTS_RXFLVL_Pos) /*!< 0x00000010 */
+#define USB_OTG_GINTSTS_RXFLVL                   USB_OTG_GINTSTS_RXFLVL_Msk    /*!< RxFIFO nonempty                                */
+#define USB_OTG_GINTSTS_NPTXFE_Pos               (5U)                          
+#define USB_OTG_GINTSTS_NPTXFE_Msk               (0x1UL << USB_OTG_GINTSTS_NPTXFE_Pos) /*!< 0x00000020 */
+#define USB_OTG_GINTSTS_NPTXFE                   USB_OTG_GINTSTS_NPTXFE_Msk    /*!< Nonperiodic TxFIFO empty                       */
+#define USB_OTG_GINTSTS_GINAKEFF_Pos             (6U)                          
+#define USB_OTG_GINTSTS_GINAKEFF_Msk             (0x1UL << USB_OTG_GINTSTS_GINAKEFF_Pos) /*!< 0x00000040 */
+#define USB_OTG_GINTSTS_GINAKEFF                 USB_OTG_GINTSTS_GINAKEFF_Msk  /*!< Global IN nonperiodic NAK effective            */
+#define USB_OTG_GINTSTS_BOUTNAKEFF_Pos           (7U)                          
+#define USB_OTG_GINTSTS_BOUTNAKEFF_Msk           (0x1UL << USB_OTG_GINTSTS_BOUTNAKEFF_Pos) /*!< 0x00000080 */
+#define USB_OTG_GINTSTS_BOUTNAKEFF               USB_OTG_GINTSTS_BOUTNAKEFF_Msk /*!< Global OUT NAK effective                       */
+#define USB_OTG_GINTSTS_ESUSP_Pos                (10U)                         
+#define USB_OTG_GINTSTS_ESUSP_Msk                (0x1UL << USB_OTG_GINTSTS_ESUSP_Pos) /*!< 0x00000400 */
+#define USB_OTG_GINTSTS_ESUSP                    USB_OTG_GINTSTS_ESUSP_Msk     /*!< Early suspend                                  */
+#define USB_OTG_GINTSTS_USBSUSP_Pos              (11U)                         
+#define USB_OTG_GINTSTS_USBSUSP_Msk              (0x1UL << USB_OTG_GINTSTS_USBSUSP_Pos) /*!< 0x00000800 */
+#define USB_OTG_GINTSTS_USBSUSP                  USB_OTG_GINTSTS_USBSUSP_Msk   /*!< USB suspend                                    */
+#define USB_OTG_GINTSTS_USBRST_Pos               (12U)                         
+#define USB_OTG_GINTSTS_USBRST_Msk               (0x1UL << USB_OTG_GINTSTS_USBRST_Pos) /*!< 0x00001000 */
+#define USB_OTG_GINTSTS_USBRST                   USB_OTG_GINTSTS_USBRST_Msk    /*!< USB reset                                      */
+#define USB_OTG_GINTSTS_ENUMDNE_Pos              (13U)                         
+#define USB_OTG_GINTSTS_ENUMDNE_Msk              (0x1UL << USB_OTG_GINTSTS_ENUMDNE_Pos) /*!< 0x00002000 */
+#define USB_OTG_GINTSTS_ENUMDNE                  USB_OTG_GINTSTS_ENUMDNE_Msk   /*!< Enumeration done                               */
+#define USB_OTG_GINTSTS_ISOODRP_Pos              (14U)                         
+#define USB_OTG_GINTSTS_ISOODRP_Msk              (0x1UL << USB_OTG_GINTSTS_ISOODRP_Pos) /*!< 0x00004000 */
+#define USB_OTG_GINTSTS_ISOODRP                  USB_OTG_GINTSTS_ISOODRP_Msk   /*!< Isochronous OUT packet dropped interrupt       */
+#define USB_OTG_GINTSTS_EOPF_Pos                 (15U)                         
+#define USB_OTG_GINTSTS_EOPF_Msk                 (0x1UL << USB_OTG_GINTSTS_EOPF_Pos) /*!< 0x00008000 */
+#define USB_OTG_GINTSTS_EOPF                     USB_OTG_GINTSTS_EOPF_Msk      /*!< End of periodic frame interrupt                */
+#define USB_OTG_GINTSTS_IEPINT_Pos               (18U)                         
+#define USB_OTG_GINTSTS_IEPINT_Msk               (0x1UL << USB_OTG_GINTSTS_IEPINT_Pos) /*!< 0x00040000 */
+#define USB_OTG_GINTSTS_IEPINT                   USB_OTG_GINTSTS_IEPINT_Msk    /*!< IN endpoint interrupt                          */
+#define USB_OTG_GINTSTS_OEPINT_Pos               (19U)                         
+#define USB_OTG_GINTSTS_OEPINT_Msk               (0x1UL << USB_OTG_GINTSTS_OEPINT_Pos) /*!< 0x00080000 */
+#define USB_OTG_GINTSTS_OEPINT                   USB_OTG_GINTSTS_OEPINT_Msk    /*!< OUT endpoint interrupt                         */
+#define USB_OTG_GINTSTS_IISOIXFR_Pos             (20U)                         
+#define USB_OTG_GINTSTS_IISOIXFR_Msk             (0x1UL << USB_OTG_GINTSTS_IISOIXFR_Pos) /*!< 0x00100000 */
+#define USB_OTG_GINTSTS_IISOIXFR                 USB_OTG_GINTSTS_IISOIXFR_Msk  /*!< Incomplete isochronous IN transfer             */
+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos    (21U)                         
+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk    (0x1UL << USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos) /*!< 0x00200000 */
+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT        USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk /*!< Incomplete periodic transfer                   */
+#define USB_OTG_GINTSTS_DATAFSUSP_Pos            (22U)                         
+#define USB_OTG_GINTSTS_DATAFSUSP_Msk            (0x1UL << USB_OTG_GINTSTS_DATAFSUSP_Pos) /*!< 0x00400000 */
+#define USB_OTG_GINTSTS_DATAFSUSP                USB_OTG_GINTSTS_DATAFSUSP_Msk /*!< Data fetch suspended                           */
+#define USB_OTG_GINTSTS_RSTDET_Pos               (23U)                         
+#define USB_OTG_GINTSTS_RSTDET_Msk               (0x1UL << USB_OTG_GINTSTS_RSTDET_Pos) /*!< 0x00800000 */
+#define USB_OTG_GINTSTS_RSTDET                   USB_OTG_GINTSTS_RSTDET_Msk    /*!< Reset detected interrupt                       */
+#define USB_OTG_GINTSTS_HPRTINT_Pos              (24U)                         
+#define USB_OTG_GINTSTS_HPRTINT_Msk              (0x1UL << USB_OTG_GINTSTS_HPRTINT_Pos) /*!< 0x01000000 */
+#define USB_OTG_GINTSTS_HPRTINT                  USB_OTG_GINTSTS_HPRTINT_Msk   /*!< Host port interrupt                            */
+#define USB_OTG_GINTSTS_HCINT_Pos                (25U)                         
+#define USB_OTG_GINTSTS_HCINT_Msk                (0x1UL << USB_OTG_GINTSTS_HCINT_Pos) /*!< 0x02000000 */
+#define USB_OTG_GINTSTS_HCINT                    USB_OTG_GINTSTS_HCINT_Msk     /*!< Host channels interrupt                        */
+#define USB_OTG_GINTSTS_PTXFE_Pos                (26U)                         
+#define USB_OTG_GINTSTS_PTXFE_Msk                (0x1UL << USB_OTG_GINTSTS_PTXFE_Pos) /*!< 0x04000000 */
+#define USB_OTG_GINTSTS_PTXFE                    USB_OTG_GINTSTS_PTXFE_Msk     /*!< Periodic TxFIFO empty                          */
+#define USB_OTG_GINTSTS_LPMINT_Pos               (27U)                         
+#define USB_OTG_GINTSTS_LPMINT_Msk               (0x1UL << USB_OTG_GINTSTS_LPMINT_Pos) /*!< 0x08000000 */
+#define USB_OTG_GINTSTS_LPMINT                   USB_OTG_GINTSTS_LPMINT_Msk    /*!< LPM interrupt                                  */
+#define USB_OTG_GINTSTS_CIDSCHG_Pos              (28U)                         
+#define USB_OTG_GINTSTS_CIDSCHG_Msk              (0x1UL << USB_OTG_GINTSTS_CIDSCHG_Pos) /*!< 0x10000000 */
+#define USB_OTG_GINTSTS_CIDSCHG                  USB_OTG_GINTSTS_CIDSCHG_Msk   /*!< Connector ID status change                     */
+#define USB_OTG_GINTSTS_DISCINT_Pos              (29U)                         
+#define USB_OTG_GINTSTS_DISCINT_Msk              (0x1UL << USB_OTG_GINTSTS_DISCINT_Pos) /*!< 0x20000000 */
+#define USB_OTG_GINTSTS_DISCINT                  USB_OTG_GINTSTS_DISCINT_Msk   /*!< Disconnect detected interrupt                  */
+#define USB_OTG_GINTSTS_SRQINT_Pos               (30U)                         
+#define USB_OTG_GINTSTS_SRQINT_Msk               (0x1UL << USB_OTG_GINTSTS_SRQINT_Pos) /*!< 0x40000000 */
+#define USB_OTG_GINTSTS_SRQINT                   USB_OTG_GINTSTS_SRQINT_Msk    /*!< Session request/new session detected interrupt */
+#define USB_OTG_GINTSTS_WKUINT_Pos               (31U)                         
+#define USB_OTG_GINTSTS_WKUINT_Msk               (0x1UL << USB_OTG_GINTSTS_WKUINT_Pos) /*!< 0x80000000 */
+#define USB_OTG_GINTSTS_WKUINT                   USB_OTG_GINTSTS_WKUINT_Msk    /*!< Resume/remote wakeup detected interrupt        */
+
+/********************  Bit definition for USB_OTG_GINTMSK register  ********************/
+#define USB_OTG_GINTMSK_MMISM_Pos                (1U)                          
+#define USB_OTG_GINTMSK_MMISM_Msk                (0x1UL << USB_OTG_GINTMSK_MMISM_Pos) /*!< 0x00000002 */
+#define USB_OTG_GINTMSK_MMISM                    USB_OTG_GINTMSK_MMISM_Msk     /*!< Mode mismatch interrupt mask                        */
+#define USB_OTG_GINTMSK_OTGINT_Pos               (2U)                          
+#define USB_OTG_GINTMSK_OTGINT_Msk               (0x1UL << USB_OTG_GINTMSK_OTGINT_Pos) /*!< 0x00000004 */
+#define USB_OTG_GINTMSK_OTGINT                   USB_OTG_GINTMSK_OTGINT_Msk    /*!< OTG interrupt mask                                  */
+#define USB_OTG_GINTMSK_SOFM_Pos                 (3U)                          
+#define USB_OTG_GINTMSK_SOFM_Msk                 (0x1UL << USB_OTG_GINTMSK_SOFM_Pos) /*!< 0x00000008 */
+#define USB_OTG_GINTMSK_SOFM                     USB_OTG_GINTMSK_SOFM_Msk      /*!< Start of frame mask                                 */
+#define USB_OTG_GINTMSK_RXFLVLM_Pos              (4U)                          
+#define USB_OTG_GINTMSK_RXFLVLM_Msk              (0x1UL << USB_OTG_GINTMSK_RXFLVLM_Pos) /*!< 0x00000010 */
+#define USB_OTG_GINTMSK_RXFLVLM                  USB_OTG_GINTMSK_RXFLVLM_Msk   /*!< Receive FIFO nonempty mask                          */
+#define USB_OTG_GINTMSK_NPTXFEM_Pos              (5U)                          
+#define USB_OTG_GINTMSK_NPTXFEM_Msk              (0x1UL << USB_OTG_GINTMSK_NPTXFEM_Pos) /*!< 0x00000020 */
+#define USB_OTG_GINTMSK_NPTXFEM                  USB_OTG_GINTMSK_NPTXFEM_Msk   /*!< Nonperiodic TxFIFO empty mask                       */
+#define USB_OTG_GINTMSK_GINAKEFFM_Pos            (6U)                          
+#define USB_OTG_GINTMSK_GINAKEFFM_Msk            (0x1UL << USB_OTG_GINTMSK_GINAKEFFM_Pos) /*!< 0x00000040 */
+#define USB_OTG_GINTMSK_GINAKEFFM                USB_OTG_GINTMSK_GINAKEFFM_Msk /*!< Global nonperiodic IN NAK effective mask            */
+#define USB_OTG_GINTMSK_GONAKEFFM_Pos            (7U)                          
+#define USB_OTG_GINTMSK_GONAKEFFM_Msk            (0x1UL << USB_OTG_GINTMSK_GONAKEFFM_Pos) /*!< 0x00000080 */
+#define USB_OTG_GINTMSK_GONAKEFFM                USB_OTG_GINTMSK_GONAKEFFM_Msk /*!< Global OUT NAK effective mask                       */
+#define USB_OTG_GINTMSK_ESUSPM_Pos               (10U)                         
+#define USB_OTG_GINTMSK_ESUSPM_Msk               (0x1UL << USB_OTG_GINTMSK_ESUSPM_Pos) /*!< 0x00000400 */
+#define USB_OTG_GINTMSK_ESUSPM                   USB_OTG_GINTMSK_ESUSPM_Msk    /*!< Early suspend mask                                  */
+#define USB_OTG_GINTMSK_USBSUSPM_Pos             (11U)                         
+#define USB_OTG_GINTMSK_USBSUSPM_Msk             (0x1UL << USB_OTG_GINTMSK_USBSUSPM_Pos) /*!< 0x00000800 */
+#define USB_OTG_GINTMSK_USBSUSPM                 USB_OTG_GINTMSK_USBSUSPM_Msk  /*!< USB suspend mask                                    */
+#define USB_OTG_GINTMSK_USBRST_Pos               (12U)                         
+#define USB_OTG_GINTMSK_USBRST_Msk               (0x1UL << USB_OTG_GINTMSK_USBRST_Pos) /*!< 0x00001000 */
+#define USB_OTG_GINTMSK_USBRST                   USB_OTG_GINTMSK_USBRST_Msk    /*!< USB reset mask                                      */
+#define USB_OTG_GINTMSK_ENUMDNEM_Pos             (13U)                         
+#define USB_OTG_GINTMSK_ENUMDNEM_Msk             (0x1UL << USB_OTG_GINTMSK_ENUMDNEM_Pos) /*!< 0x00002000 */
+#define USB_OTG_GINTMSK_ENUMDNEM                 USB_OTG_GINTMSK_ENUMDNEM_Msk  /*!< Enumeration done mask                               */
+#define USB_OTG_GINTMSK_ISOODRPM_Pos             (14U)                         
+#define USB_OTG_GINTMSK_ISOODRPM_Msk             (0x1UL << USB_OTG_GINTMSK_ISOODRPM_Pos) /*!< 0x00004000 */
+#define USB_OTG_GINTMSK_ISOODRPM                 USB_OTG_GINTMSK_ISOODRPM_Msk  /*!< Isochronous OUT packet dropped interrupt mask       */
+#define USB_OTG_GINTMSK_EOPFM_Pos                (15U)                         
+#define USB_OTG_GINTMSK_EOPFM_Msk                (0x1UL << USB_OTG_GINTMSK_EOPFM_Pos) /*!< 0x00008000 */
+#define USB_OTG_GINTMSK_EOPFM                    USB_OTG_GINTMSK_EOPFM_Msk     /*!< End of periodic frame interrupt mask                */
+#define USB_OTG_GINTMSK_EPMISM_Pos               (17U)                         
+#define USB_OTG_GINTMSK_EPMISM_Msk               (0x1UL << USB_OTG_GINTMSK_EPMISM_Pos) /*!< 0x00020000 */
+#define USB_OTG_GINTMSK_EPMISM                   USB_OTG_GINTMSK_EPMISM_Msk    /*!< Endpoint mismatch interrupt mask                    */
+#define USB_OTG_GINTMSK_IEPINT_Pos               (18U)                         
+#define USB_OTG_GINTMSK_IEPINT_Msk               (0x1UL << USB_OTG_GINTMSK_IEPINT_Pos) /*!< 0x00040000 */
+#define USB_OTG_GINTMSK_IEPINT                   USB_OTG_GINTMSK_IEPINT_Msk    /*!< IN endpoints interrupt mask                         */
+#define USB_OTG_GINTMSK_OEPINT_Pos               (19U)                         
+#define USB_OTG_GINTMSK_OEPINT_Msk               (0x1UL << USB_OTG_GINTMSK_OEPINT_Pos) /*!< 0x00080000 */
+#define USB_OTG_GINTMSK_OEPINT                   USB_OTG_GINTMSK_OEPINT_Msk    /*!< OUT endpoints interrupt mask                        */
+#define USB_OTG_GINTMSK_IISOIXFRM_Pos            (20U)                         
+#define USB_OTG_GINTMSK_IISOIXFRM_Msk            (0x1UL << USB_OTG_GINTMSK_IISOIXFRM_Pos) /*!< 0x00100000 */
+#define USB_OTG_GINTMSK_IISOIXFRM                USB_OTG_GINTMSK_IISOIXFRM_Msk /*!< Incomplete isochronous IN transfer mask             */
+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos      (21U)                         
+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk      (0x1UL << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos) /*!< 0x00200000 */
+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM          USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask                   */
+#define USB_OTG_GINTMSK_FSUSPM_Pos               (22U)                         
+#define USB_OTG_GINTMSK_FSUSPM_Msk               (0x1UL << USB_OTG_GINTMSK_FSUSPM_Pos) /*!< 0x00400000 */
+#define USB_OTG_GINTMSK_FSUSPM                   USB_OTG_GINTMSK_FSUSPM_Msk    /*!< Data fetch suspended mask                           */
+#define USB_OTG_GINTMSK_RSTDEM_Pos               (23U)                         
+#define USB_OTG_GINTMSK_RSTDEM_Msk               (0x1UL << USB_OTG_GINTMSK_RSTDEM_Pos) /*!< 0x00800000 */
+#define USB_OTG_GINTMSK_RSTDEM                   USB_OTG_GINTMSK_RSTDEM_Msk    /*!< Reset detected interrupt mask                      */
+#define USB_OTG_GINTMSK_PRTIM_Pos                (24U)                         
+#define USB_OTG_GINTMSK_PRTIM_Msk                (0x1UL << USB_OTG_GINTMSK_PRTIM_Pos) /*!< 0x01000000 */
+#define USB_OTG_GINTMSK_PRTIM                    USB_OTG_GINTMSK_PRTIM_Msk     /*!< Host port interrupt mask                            */
+#define USB_OTG_GINTMSK_HCIM_Pos                 (25U)                         
+#define USB_OTG_GINTMSK_HCIM_Msk                 (0x1UL << USB_OTG_GINTMSK_HCIM_Pos) /*!< 0x02000000 */
+#define USB_OTG_GINTMSK_HCIM                     USB_OTG_GINTMSK_HCIM_Msk      /*!< Host channels interrupt mask                        */
+#define USB_OTG_GINTMSK_PTXFEM_Pos               (26U)                         
+#define USB_OTG_GINTMSK_PTXFEM_Msk               (0x1UL << USB_OTG_GINTMSK_PTXFEM_Pos) /*!< 0x04000000 */
+#define USB_OTG_GINTMSK_PTXFEM                   USB_OTG_GINTMSK_PTXFEM_Msk    /*!< Periodic TxFIFO empty mask                          */
+#define USB_OTG_GINTMSK_LPMINTM_Pos              (27U)                         
+#define USB_OTG_GINTMSK_LPMINTM_Msk              (0x1UL << USB_OTG_GINTMSK_LPMINTM_Pos) /*!< 0x08000000 */
+#define USB_OTG_GINTMSK_LPMINTM                  USB_OTG_GINTMSK_LPMINTM_Msk   /*!< LPM interrupt Mask                                  */
+#define USB_OTG_GINTMSK_CIDSCHGM_Pos             (28U)                         
+#define USB_OTG_GINTMSK_CIDSCHGM_Msk             (0x1UL << USB_OTG_GINTMSK_CIDSCHGM_Pos) /*!< 0x10000000 */
+#define USB_OTG_GINTMSK_CIDSCHGM                 USB_OTG_GINTMSK_CIDSCHGM_Msk  /*!< Connector ID status change mask                     */
+#define USB_OTG_GINTMSK_DISCINT_Pos              (29U)                         
+#define USB_OTG_GINTMSK_DISCINT_Msk              (0x1UL << USB_OTG_GINTMSK_DISCINT_Pos) /*!< 0x20000000 */
+#define USB_OTG_GINTMSK_DISCINT                  USB_OTG_GINTMSK_DISCINT_Msk   /*!< Disconnect detected interrupt mask                  */
+#define USB_OTG_GINTMSK_SRQIM_Pos                (30U)                         
+#define USB_OTG_GINTMSK_SRQIM_Msk                (0x1UL << USB_OTG_GINTMSK_SRQIM_Pos) /*!< 0x40000000 */
+#define USB_OTG_GINTMSK_SRQIM                    USB_OTG_GINTMSK_SRQIM_Msk     /*!< Session request/new session detected interrupt mask */
+#define USB_OTG_GINTMSK_WUIM_Pos                 (31U)                         
+#define USB_OTG_GINTMSK_WUIM_Msk                 (0x1UL << USB_OTG_GINTMSK_WUIM_Pos) /*!< 0x80000000 */
+#define USB_OTG_GINTMSK_WUIM                     USB_OTG_GINTMSK_WUIM_Msk      /*!< Resume/remote wakeup detected interrupt mask        */
+
+/********************  Bit definition for USB_OTG_DAINT register  ********************/
+#define USB_OTG_DAINT_IEPINT_Pos                 (0U)                          
+#define USB_OTG_DAINT_IEPINT_Msk                 (0xFFFFUL << USB_OTG_DAINT_IEPINT_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DAINT_IEPINT                     USB_OTG_DAINT_IEPINT_Msk      /*!< IN endpoint interrupt bits  */
+#define USB_OTG_DAINT_OEPINT_Pos                 (16U)                         
+#define USB_OTG_DAINT_OEPINT_Msk                 (0xFFFFUL << USB_OTG_DAINT_OEPINT_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_DAINT_OEPINT                     USB_OTG_DAINT_OEPINT_Msk      /*!< OUT endpoint interrupt bits */
+
+/********************  Bit definition for USB_OTG_HAINTMSK register  ********************/
+#define USB_OTG_HAINTMSK_HAINTM_Pos              (0U)                          
+#define USB_OTG_HAINTMSK_HAINTM_Msk              (0xFFFFUL << USB_OTG_HAINTMSK_HAINTM_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HAINTMSK_HAINTM                  USB_OTG_HAINTMSK_HAINTM_Msk   /*!< Channel interrupt mask */
+
+/********************  Bit definition for USB_OTG_GRXSTSP register  ********************/
+#define USB_OTG_GRXSTSP_EPNUM_Pos                (0U)                          
+#define USB_OTG_GRXSTSP_EPNUM_Msk                (0xFUL << USB_OTG_GRXSTSP_EPNUM_Pos) /*!< 0x0000000F */
+#define USB_OTG_GRXSTSP_EPNUM                    USB_OTG_GRXSTSP_EPNUM_Msk     /*!< IN EP interrupt mask bits  */
+#define USB_OTG_GRXSTSP_BCNT_Pos                 (4U)                          
+#define USB_OTG_GRXSTSP_BCNT_Msk                 (0x7FFUL << USB_OTG_GRXSTSP_BCNT_Pos) /*!< 0x00007FF0 */
+#define USB_OTG_GRXSTSP_BCNT                     USB_OTG_GRXSTSP_BCNT_Msk      /*!< OUT EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_DPID_Pos                 (15U)                         
+#define USB_OTG_GRXSTSP_DPID_Msk                 (0x3UL << USB_OTG_GRXSTSP_DPID_Pos) /*!< 0x00018000 */
+#define USB_OTG_GRXSTSP_DPID                     USB_OTG_GRXSTSP_DPID_Msk      /*!< OUT EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_PKTSTS_Pos               (17U)                         
+#define USB_OTG_GRXSTSP_PKTSTS_Msk               (0xFUL << USB_OTG_GRXSTSP_PKTSTS_Pos) /*!< 0x001E0000 */
+#define USB_OTG_GRXSTSP_PKTSTS                   USB_OTG_GRXSTSP_PKTSTS_Msk    /*!< OUT EP interrupt mask bits */
+
+/********************  Bit definition for USB_OTG_DAINTMSK register  ********************/
+#define USB_OTG_DAINTMSK_IEPM_Pos                (0U)                          
+#define USB_OTG_DAINTMSK_IEPM_Msk                (0xFFFFUL << USB_OTG_DAINTMSK_IEPM_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DAINTMSK_IEPM                    USB_OTG_DAINTMSK_IEPM_Msk     /*!< IN EP interrupt mask bits */
+#define USB_OTG_DAINTMSK_OEPM_Pos                (16U)                         
+#define USB_OTG_DAINTMSK_OEPM_Msk                (0xFFFFUL << USB_OTG_DAINTMSK_OEPM_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_DAINTMSK_OEPM                    USB_OTG_DAINTMSK_OEPM_Msk     /*!< OUT EP interrupt mask bits */
+
+/********************  Bit definition for USB_OTG_GRXFSIZ register  ********************/
+#define USB_OTG_GRXFSIZ_RXFD_Pos                 (0U)                          
+#define USB_OTG_GRXFSIZ_RXFD_Msk                 (0xFFFFUL << USB_OTG_GRXFSIZ_RXFD_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_GRXFSIZ_RXFD                     USB_OTG_GRXFSIZ_RXFD_Msk      /*!< RxFIFO depth */
+
+/********************  Bit definition for USB_OTG_DVBUSDIS register  ********************/
+#define USB_OTG_DVBUSDIS_VBUSDT_Pos              (0U)                          
+#define USB_OTG_DVBUSDIS_VBUSDT_Msk              (0xFFFFUL << USB_OTG_DVBUSDIS_VBUSDT_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DVBUSDIS_VBUSDT                  USB_OTG_DVBUSDIS_VBUSDT_Msk   /*!< Device VBUS discharge time */
+
+/********************  Bit definition for OTG register  ********************/
+#define USB_OTG_NPTXFSA_Pos                      (0U)                          
+#define USB_OTG_NPTXFSA_Msk                      (0xFFFFUL << USB_OTG_NPTXFSA_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_NPTXFSA                          USB_OTG_NPTXFSA_Msk           /*!< Nonperiodic transmit RAM start address */
+#define USB_OTG_NPTXFD_Pos                       (16U)                         
+#define USB_OTG_NPTXFD_Msk                       (0xFFFFUL << USB_OTG_NPTXFD_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_NPTXFD                           USB_OTG_NPTXFD_Msk            /*!< Nonperiodic TxFIFO depth               */
+#define USB_OTG_TX0FSA_Pos                       (0U)                          
+#define USB_OTG_TX0FSA_Msk                       (0xFFFFUL << USB_OTG_TX0FSA_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_TX0FSA                           USB_OTG_TX0FSA_Msk            /*!< Endpoint 0 transmit RAM start address  */
+#define USB_OTG_TX0FD_Pos                        (16U)                         
+#define USB_OTG_TX0FD_Msk                        (0xFFFFUL << USB_OTG_TX0FD_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_TX0FD                            USB_OTG_TX0FD_Msk             /*!< Endpoint 0 TxFIFO depth                */
+
+/********************  Bit definition forUSB_OTG_DVBUSPULSE register  ********************/
+#define USB_OTG_DVBUSPULSE_DVBUSP_Pos            (0U)                          
+#define USB_OTG_DVBUSPULSE_DVBUSP_Msk            (0xFFFUL << USB_OTG_DVBUSPULSE_DVBUSP_Pos) /*!< 0x00000FFF */
+#define USB_OTG_DVBUSPULSE_DVBUSP                USB_OTG_DVBUSPULSE_DVBUSP_Msk /*!< Device VBUS pulsing time */
+
+/********************  Bit definition for USB_OTG_GNPTXSTS register  ********************/
+#define USB_OTG_GNPTXSTS_NPTXFSAV_Pos            (0U)                          
+#define USB_OTG_GNPTXSTS_NPTXFSAV_Msk            (0xFFFFUL << USB_OTG_GNPTXSTS_NPTXFSAV_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_GNPTXSTS_NPTXFSAV                USB_OTG_GNPTXSTS_NPTXFSAV_Msk /*!< Nonperiodic TxFIFO space available */
+
+#define USB_OTG_GNPTXSTS_NPTQXSAV_Pos            (16U)                         
+#define USB_OTG_GNPTXSTS_NPTQXSAV_Msk            (0xFFUL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00FF0000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV                USB_OTG_GNPTXSTS_NPTQXSAV_Msk /*!< Nonperiodic transmit request queue space available */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_0              (0x01UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00010000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_1              (0x02UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00020000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_2              (0x04UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00040000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_3              (0x08UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00080000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_4              (0x10UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00100000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_5              (0x20UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00200000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_6              (0x40UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00400000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_7              (0x80UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00800000 */
+
+#define USB_OTG_GNPTXSTS_NPTXQTOP_Pos            (24U)                         
+#define USB_OTG_GNPTXSTS_NPTXQTOP_Msk            (0x7FUL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x7F000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP                USB_OTG_GNPTXSTS_NPTXQTOP_Msk /*!< Top of the nonperiodic transmit request queue */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_0              (0x01UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x01000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_1              (0x02UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x02000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_2              (0x04UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x04000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_3              (0x08UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x08000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_4              (0x10UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x10000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_5              (0x20UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x20000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_6              (0x40UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x40000000 */
+
+/********************  Bit definition for USB_OTG_DTHRCTL register  ********************/
+#define USB_OTG_DTHRCTL_NONISOTHREN_Pos          (0U)                          
+#define USB_OTG_DTHRCTL_NONISOTHREN_Msk          (0x1UL << USB_OTG_DTHRCTL_NONISOTHREN_Pos) /*!< 0x00000001 */
+#define USB_OTG_DTHRCTL_NONISOTHREN              USB_OTG_DTHRCTL_NONISOTHREN_Msk /*!< Nonisochronous IN endpoints threshold enable */
+#define USB_OTG_DTHRCTL_ISOTHREN_Pos             (1U)                          
+#define USB_OTG_DTHRCTL_ISOTHREN_Msk             (0x1UL << USB_OTG_DTHRCTL_ISOTHREN_Pos) /*!< 0x00000002 */
+#define USB_OTG_DTHRCTL_ISOTHREN                 USB_OTG_DTHRCTL_ISOTHREN_Msk  /*!< ISO IN endpoint threshold enable */
+
+#define USB_OTG_DTHRCTL_TXTHRLEN_Pos             (2U)                          
+#define USB_OTG_DTHRCTL_TXTHRLEN_Msk             (0x1FFUL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x000007FC */
+#define USB_OTG_DTHRCTL_TXTHRLEN                 USB_OTG_DTHRCTL_TXTHRLEN_Msk  /*!< Transmit threshold length */
+#define USB_OTG_DTHRCTL_TXTHRLEN_0               (0x001UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000004 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_1               (0x002UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000008 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_2               (0x004UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000010 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_3               (0x008UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000020 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_4               (0x010UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000040 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_5               (0x020UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000080 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_6               (0x040UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000100 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_7               (0x080UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000200 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_8               (0x100UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000400 */
+#define USB_OTG_DTHRCTL_RXTHREN_Pos              (16U)                         
+#define USB_OTG_DTHRCTL_RXTHREN_Msk              (0x1UL << USB_OTG_DTHRCTL_RXTHREN_Pos) /*!< 0x00010000 */
+#define USB_OTG_DTHRCTL_RXTHREN                  USB_OTG_DTHRCTL_RXTHREN_Msk   /*!< Receive threshold enable */
+
+#define USB_OTG_DTHRCTL_RXTHRLEN_Pos             (17U)                         
+#define USB_OTG_DTHRCTL_RXTHRLEN_Msk             (0x1FFUL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x03FE0000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN                 USB_OTG_DTHRCTL_RXTHRLEN_Msk  /*!< Receive threshold length */
+#define USB_OTG_DTHRCTL_RXTHRLEN_0               (0x001UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00020000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_1               (0x002UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00040000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_2               (0x004UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00080000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_3               (0x008UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00100000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_4               (0x010UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00200000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_5               (0x020UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00400000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_6               (0x040UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00800000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_7               (0x080UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x01000000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_8               (0x100UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x02000000 */
+#define USB_OTG_DTHRCTL_ARPEN_Pos                (27U)                         
+#define USB_OTG_DTHRCTL_ARPEN_Msk                (0x1UL << USB_OTG_DTHRCTL_ARPEN_Pos) /*!< 0x08000000 */
+#define USB_OTG_DTHRCTL_ARPEN                    USB_OTG_DTHRCTL_ARPEN_Msk     /*!< Arbiter parking enable */
+
+/********************  Bit definition for USB_OTG_DIEPEMPMSK register  ********************/
+#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos         (0U)                          
+#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk         (0xFFFFUL << USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DIEPEMPMSK_INEPTXFEM             USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk /*!< IN EP Tx FIFO empty interrupt mask bits */
+
+/********************  Bit definition for USB_OTG_DEACHINT register  ********************/
+#define USB_OTG_DEACHINT_IEP1INT_Pos             (1U)                          
+#define USB_OTG_DEACHINT_IEP1INT_Msk             (0x1UL << USB_OTG_DEACHINT_IEP1INT_Pos) /*!< 0x00000002 */
+#define USB_OTG_DEACHINT_IEP1INT                 USB_OTG_DEACHINT_IEP1INT_Msk  /*!< IN endpoint 1interrupt bit   */
+#define USB_OTG_DEACHINT_OEP1INT_Pos             (17U)                         
+#define USB_OTG_DEACHINT_OEP1INT_Msk             (0x1UL << USB_OTG_DEACHINT_OEP1INT_Pos) /*!< 0x00020000 */
+#define USB_OTG_DEACHINT_OEP1INT                 USB_OTG_DEACHINT_OEP1INT_Msk  /*!< OUT endpoint 1 interrupt bit */
+
+/********************  Bit definition for USB_OTG_GCCFG register  ********************/
+#define USB_OTG_GCCFG_PWRDWN_Pos                 (16U)                         
+#define USB_OTG_GCCFG_PWRDWN_Msk                 (0x1UL << USB_OTG_GCCFG_PWRDWN_Pos) /*!< 0x00010000 */
+#define USB_OTG_GCCFG_PWRDWN                     USB_OTG_GCCFG_PWRDWN_Msk      /*!< Power down */
+#define USB_OTG_GCCFG_VBDEN_Pos                  (21U)                         
+#define USB_OTG_GCCFG_VBDEN_Msk                  (0x1UL << USB_OTG_GCCFG_VBDEN_Pos) /*!< 0x00200000 */
+#define USB_OTG_GCCFG_VBDEN                      USB_OTG_GCCFG_VBDEN_Msk       /*!< USB VBUS Detection Enable */
+
+/********************  Bit definition forUSB_OTG_DEACHINTMSK register  ********************/
+#define USB_OTG_DEACHINTMSK_IEP1INTM_Pos         (1U)                          
+#define USB_OTG_DEACHINTMSK_IEP1INTM_Msk         (0x1UL << USB_OTG_DEACHINTMSK_IEP1INTM_Pos) /*!< 0x00000002 */
+#define USB_OTG_DEACHINTMSK_IEP1INTM             USB_OTG_DEACHINTMSK_IEP1INTM_Msk /*!< IN Endpoint 1 interrupt mask bit  */
+#define USB_OTG_DEACHINTMSK_OEP1INTM_Pos         (17U)                         
+#define USB_OTG_DEACHINTMSK_OEP1INTM_Msk         (0x1UL << USB_OTG_DEACHINTMSK_OEP1INTM_Pos) /*!< 0x00020000 */
+#define USB_OTG_DEACHINTMSK_OEP1INTM             USB_OTG_DEACHINTMSK_OEP1INTM_Msk /*!< OUT Endpoint 1 interrupt mask bit */
+
+/********************  Bit definition for USB_OTG_CID register  ********************/
+#define USB_OTG_CID_PRODUCT_ID_Pos               (0U)                          
+#define USB_OTG_CID_PRODUCT_ID_Msk               (0xFFFFFFFFUL << USB_OTG_CID_PRODUCT_ID_Pos) /*!< 0xFFFFFFFF */
+#define USB_OTG_CID_PRODUCT_ID                   USB_OTG_CID_PRODUCT_ID_Msk    /*!< Product ID field */
+
+/********************  Bit definition for USB_OTG_GLPMCFG register  ********************/
+#define USB_OTG_GLPMCFG_LPMEN_Pos                (0U)                          
+#define USB_OTG_GLPMCFG_LPMEN_Msk                (0x1UL << USB_OTG_GLPMCFG_LPMEN_Pos) /*!< 0x00000001 */
+#define USB_OTG_GLPMCFG_LPMEN                    USB_OTG_GLPMCFG_LPMEN_Msk     /*!< LPM support enable                                     */
+#define USB_OTG_GLPMCFG_LPMACK_Pos               (1U)                          
+#define USB_OTG_GLPMCFG_LPMACK_Msk               (0x1UL << USB_OTG_GLPMCFG_LPMACK_Pos) /*!< 0x00000002 */
+#define USB_OTG_GLPMCFG_LPMACK                   USB_OTG_GLPMCFG_LPMACK_Msk    /*!< LPM Token acknowledge enable                           */
+#define USB_OTG_GLPMCFG_BESL_Pos                 (2U)                          
+#define USB_OTG_GLPMCFG_BESL_Msk                 (0xFUL << USB_OTG_GLPMCFG_BESL_Pos) /*!< 0x0000003C */
+#define USB_OTG_GLPMCFG_BESL                     USB_OTG_GLPMCFG_BESL_Msk      /*!< BESL value received with last ACKed LPM Token          */
+#define USB_OTG_GLPMCFG_REMWAKE_Pos              (6U)                          
+#define USB_OTG_GLPMCFG_REMWAKE_Msk              (0x1UL << USB_OTG_GLPMCFG_REMWAKE_Pos) /*!< 0x00000040 */
+#define USB_OTG_GLPMCFG_REMWAKE                  USB_OTG_GLPMCFG_REMWAKE_Msk   /*!< bRemoteWake value received with last ACKed LPM Token   */
+#define USB_OTG_GLPMCFG_L1SSEN_Pos               (7U)                          
+#define USB_OTG_GLPMCFG_L1SSEN_Msk               (0x1UL << USB_OTG_GLPMCFG_L1SSEN_Pos) /*!< 0x00000080 */
+#define USB_OTG_GLPMCFG_L1SSEN                   USB_OTG_GLPMCFG_L1SSEN_Msk    /*!< L1 shallow sleep enable                                */
+#define USB_OTG_GLPMCFG_BESLTHRS_Pos             (8U)                          
+#define USB_OTG_GLPMCFG_BESLTHRS_Msk             (0xFUL << USB_OTG_GLPMCFG_BESLTHRS_Pos) /*!< 0x00000F00 */
+#define USB_OTG_GLPMCFG_BESLTHRS                 USB_OTG_GLPMCFG_BESLTHRS_Msk  /*!< BESL threshold                                         */
+#define USB_OTG_GLPMCFG_L1DSEN_Pos               (12U)                         
+#define USB_OTG_GLPMCFG_L1DSEN_Msk               (0x1UL << USB_OTG_GLPMCFG_L1DSEN_Pos) /*!< 0x00001000 */
+#define USB_OTG_GLPMCFG_L1DSEN                   USB_OTG_GLPMCFG_L1DSEN_Msk    /*!< L1 deep sleep enable                                   */
+#define USB_OTG_GLPMCFG_LPMRSP_Pos               (13U)                         
+#define USB_OTG_GLPMCFG_LPMRSP_Msk               (0x3UL << USB_OTG_GLPMCFG_LPMRSP_Pos) /*!< 0x00006000 */
+#define USB_OTG_GLPMCFG_LPMRSP                   USB_OTG_GLPMCFG_LPMRSP_Msk    /*!< LPM response                                           */
+#define USB_OTG_GLPMCFG_SLPSTS_Pos               (15U)                         
+#define USB_OTG_GLPMCFG_SLPSTS_Msk               (0x1UL << USB_OTG_GLPMCFG_SLPSTS_Pos) /*!< 0x00008000 */
+#define USB_OTG_GLPMCFG_SLPSTS                   USB_OTG_GLPMCFG_SLPSTS_Msk    /*!< Port sleep status                                      */
+#define USB_OTG_GLPMCFG_L1RSMOK_Pos              (16U)                         
+#define USB_OTG_GLPMCFG_L1RSMOK_Msk              (0x1UL << USB_OTG_GLPMCFG_L1RSMOK_Pos) /*!< 0x00010000 */
+#define USB_OTG_GLPMCFG_L1RSMOK                  USB_OTG_GLPMCFG_L1RSMOK_Msk   /*!< Sleep State Resume OK                                  */
+#define USB_OTG_GLPMCFG_LPMCHIDX_Pos             (17U)                         
+#define USB_OTG_GLPMCFG_LPMCHIDX_Msk             (0xFUL << USB_OTG_GLPMCFG_LPMCHIDX_Pos) /*!< 0x001E0000 */
+#define USB_OTG_GLPMCFG_LPMCHIDX                 USB_OTG_GLPMCFG_LPMCHIDX_Msk  /*!< LPM Channel Index                                      */
+#define USB_OTG_GLPMCFG_LPMRCNT_Pos              (21U)                         
+#define USB_OTG_GLPMCFG_LPMRCNT_Msk              (0x7UL << USB_OTG_GLPMCFG_LPMRCNT_Pos) /*!< 0x00E00000 */
+#define USB_OTG_GLPMCFG_LPMRCNT                  USB_OTG_GLPMCFG_LPMRCNT_Msk   /*!< LPM retry count                                        */
+#define USB_OTG_GLPMCFG_SNDLPM_Pos               (24U)                         
+#define USB_OTG_GLPMCFG_SNDLPM_Msk               (0x1UL << USB_OTG_GLPMCFG_SNDLPM_Pos) /*!< 0x01000000 */
+#define USB_OTG_GLPMCFG_SNDLPM                   USB_OTG_GLPMCFG_SNDLPM_Msk    /*!< Send LPM transaction                                   */
+#define USB_OTG_GLPMCFG_LPMRCNTSTS_Pos           (25U)                         
+#define USB_OTG_GLPMCFG_LPMRCNTSTS_Msk           (0x7UL << USB_OTG_GLPMCFG_LPMRCNTSTS_Pos) /*!< 0x0E000000 */
+#define USB_OTG_GLPMCFG_LPMRCNTSTS               USB_OTG_GLPMCFG_LPMRCNTSTS_Msk /*!< LPM retry count status                                 */
+#define USB_OTG_GLPMCFG_ENBESL_Pos               (28U)                         
+#define USB_OTG_GLPMCFG_ENBESL_Msk               (0x1UL << USB_OTG_GLPMCFG_ENBESL_Pos) /*!< 0x10000000 */
+#define USB_OTG_GLPMCFG_ENBESL                   USB_OTG_GLPMCFG_ENBESL_Msk    /*!< Enable best effort service latency                     */
+
+/********************  Bit definition for USB_OTG_DIEPEACHMSK1 register  ********************/
+#define USB_OTG_DIEPEACHMSK1_XFRCM_Pos           (0U)                          
+#define USB_OTG_DIEPEACHMSK1_XFRCM_Msk           (0x1UL << USB_OTG_DIEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */
+#define USB_OTG_DIEPEACHMSK1_XFRCM               USB_OTG_DIEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask                 */
+#define USB_OTG_DIEPEACHMSK1_EPDM_Pos            (1U)                          
+#define USB_OTG_DIEPEACHMSK1_EPDM_Msk            (0x1UL << USB_OTG_DIEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */
+#define USB_OTG_DIEPEACHMSK1_EPDM                USB_OTG_DIEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask                  */
+#define USB_OTG_DIEPEACHMSK1_TOM_Pos             (3U)                          
+#define USB_OTG_DIEPEACHMSK1_TOM_Msk             (0x1UL << USB_OTG_DIEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */
+#define USB_OTG_DIEPEACHMSK1_TOM                 USB_OTG_DIEPEACHMSK1_TOM_Msk  /*!< Timeout condition mask (nonisochronous endpoints) */
+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos       (4U)                          
+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk       (0x1UL << USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */
+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK           USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask          */
+#define USB_OTG_DIEPEACHMSK1_INEPNMM_Pos         (5U)                          
+#define USB_OTG_DIEPEACHMSK1_INEPNMM_Msk         (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */
+#define USB_OTG_DIEPEACHMSK1_INEPNMM             USB_OTG_DIEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask           */
+#define USB_OTG_DIEPEACHMSK1_INEPNEM_Pos         (6U)                          
+#define USB_OTG_DIEPEACHMSK1_INEPNEM_Msk         (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */
+#define USB_OTG_DIEPEACHMSK1_INEPNEM             USB_OTG_DIEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask                    */
+#define USB_OTG_DIEPEACHMSK1_TXFURM_Pos          (8U)                          
+#define USB_OTG_DIEPEACHMSK1_TXFURM_Msk          (0x1UL << USB_OTG_DIEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */
+#define USB_OTG_DIEPEACHMSK1_TXFURM              USB_OTG_DIEPEACHMSK1_TXFURM_Msk /*!< FIFO underrun mask                                */
+#define USB_OTG_DIEPEACHMSK1_BIM_Pos             (9U)                          
+#define USB_OTG_DIEPEACHMSK1_BIM_Msk             (0x1UL << USB_OTG_DIEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */
+#define USB_OTG_DIEPEACHMSK1_BIM                 USB_OTG_DIEPEACHMSK1_BIM_Msk  /*!< BNA interrupt mask                                */
+#define USB_OTG_DIEPEACHMSK1_NAKM_Pos            (13U)                         
+#define USB_OTG_DIEPEACHMSK1_NAKM_Msk            (0x1UL << USB_OTG_DIEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */
+#define USB_OTG_DIEPEACHMSK1_NAKM                USB_OTG_DIEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask                                */
+
+/********************  Bit definition for USB_OTG_HPRT register  ********************/
+#define USB_OTG_HPRT_PCSTS_Pos                   (0U)                          
+#define USB_OTG_HPRT_PCSTS_Msk                   (0x1UL << USB_OTG_HPRT_PCSTS_Pos) /*!< 0x00000001 */
+#define USB_OTG_HPRT_PCSTS                       USB_OTG_HPRT_PCSTS_Msk        /*!< Port connect status        */
+#define USB_OTG_HPRT_PCDET_Pos                   (1U)                          
+#define USB_OTG_HPRT_PCDET_Msk                   (0x1UL << USB_OTG_HPRT_PCDET_Pos) /*!< 0x00000002 */
+#define USB_OTG_HPRT_PCDET                       USB_OTG_HPRT_PCDET_Msk        /*!< Port connect detected      */
+#define USB_OTG_HPRT_PENA_Pos                    (2U)                          
+#define USB_OTG_HPRT_PENA_Msk                    (0x1UL << USB_OTG_HPRT_PENA_Pos) /*!< 0x00000004 */
+#define USB_OTG_HPRT_PENA                        USB_OTG_HPRT_PENA_Msk         /*!< Port enable                */
+#define USB_OTG_HPRT_PENCHNG_Pos                 (3U)                          
+#define USB_OTG_HPRT_PENCHNG_Msk                 (0x1UL << USB_OTG_HPRT_PENCHNG_Pos) /*!< 0x00000008 */
+#define USB_OTG_HPRT_PENCHNG                     USB_OTG_HPRT_PENCHNG_Msk      /*!< Port enable/disable change */
+#define USB_OTG_HPRT_POCA_Pos                    (4U)                          
+#define USB_OTG_HPRT_POCA_Msk                    (0x1UL << USB_OTG_HPRT_POCA_Pos) /*!< 0x00000010 */
+#define USB_OTG_HPRT_POCA                        USB_OTG_HPRT_POCA_Msk         /*!< Port overcurrent active    */
+#define USB_OTG_HPRT_POCCHNG_Pos                 (5U)                          
+#define USB_OTG_HPRT_POCCHNG_Msk                 (0x1UL << USB_OTG_HPRT_POCCHNG_Pos) /*!< 0x00000020 */
+#define USB_OTG_HPRT_POCCHNG                     USB_OTG_HPRT_POCCHNG_Msk      /*!< Port overcurrent change    */
+#define USB_OTG_HPRT_PRES_Pos                    (6U)                          
+#define USB_OTG_HPRT_PRES_Msk                    (0x1UL << USB_OTG_HPRT_PRES_Pos) /*!< 0x00000040 */
+#define USB_OTG_HPRT_PRES                        USB_OTG_HPRT_PRES_Msk         /*!< Port resume                */
+#define USB_OTG_HPRT_PSUSP_Pos                   (7U)                          
+#define USB_OTG_HPRT_PSUSP_Msk                   (0x1UL << USB_OTG_HPRT_PSUSP_Pos) /*!< 0x00000080 */
+#define USB_OTG_HPRT_PSUSP                       USB_OTG_HPRT_PSUSP_Msk        /*!< Port suspend               */
+#define USB_OTG_HPRT_PRST_Pos                    (8U)                          
+#define USB_OTG_HPRT_PRST_Msk                    (0x1UL << USB_OTG_HPRT_PRST_Pos) /*!< 0x00000100 */
+#define USB_OTG_HPRT_PRST                        USB_OTG_HPRT_PRST_Msk         /*!< Port reset                 */
+
+#define USB_OTG_HPRT_PLSTS_Pos                   (10U)                         
+#define USB_OTG_HPRT_PLSTS_Msk                   (0x3UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000C00 */
+#define USB_OTG_HPRT_PLSTS                       USB_OTG_HPRT_PLSTS_Msk        /*!< Port line status           */
+#define USB_OTG_HPRT_PLSTS_0                     (0x1UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000400 */
+#define USB_OTG_HPRT_PLSTS_1                     (0x2UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000800 */
+#define USB_OTG_HPRT_PPWR_Pos                    (12U)                         
+#define USB_OTG_HPRT_PPWR_Msk                    (0x1UL << USB_OTG_HPRT_PPWR_Pos) /*!< 0x00001000 */
+#define USB_OTG_HPRT_PPWR                        USB_OTG_HPRT_PPWR_Msk         /*!< Port power                 */
+
+#define USB_OTG_HPRT_PTCTL_Pos                   (13U)                         
+#define USB_OTG_HPRT_PTCTL_Msk                   (0xFUL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x0001E000 */
+#define USB_OTG_HPRT_PTCTL                       USB_OTG_HPRT_PTCTL_Msk        /*!< Port test control          */
+#define USB_OTG_HPRT_PTCTL_0                     (0x1UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00002000 */
+#define USB_OTG_HPRT_PTCTL_1                     (0x2UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00004000 */
+#define USB_OTG_HPRT_PTCTL_2                     (0x4UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00008000 */
+#define USB_OTG_HPRT_PTCTL_3                     (0x8UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00010000 */
+
+#define USB_OTG_HPRT_PSPD_Pos                    (17U)                         
+#define USB_OTG_HPRT_PSPD_Msk                    (0x3UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00060000 */
+#define USB_OTG_HPRT_PSPD                        USB_OTG_HPRT_PSPD_Msk         /*!< Port speed                 */
+#define USB_OTG_HPRT_PSPD_0                      (0x1UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00020000 */
+#define USB_OTG_HPRT_PSPD_1                      (0x2UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00040000 */
+
+/********************  Bit definition for USB_OTG_DOEPEACHMSK1 register  ********************/
+#define USB_OTG_DOEPEACHMSK1_XFRCM_Pos           (0U)                          
+#define USB_OTG_DOEPEACHMSK1_XFRCM_Msk           (0x1UL << USB_OTG_DOEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */
+#define USB_OTG_DOEPEACHMSK1_XFRCM               USB_OTG_DOEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask         */
+#define USB_OTG_DOEPEACHMSK1_EPDM_Pos            (1U)                          
+#define USB_OTG_DOEPEACHMSK1_EPDM_Msk            (0x1UL << USB_OTG_DOEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */
+#define USB_OTG_DOEPEACHMSK1_EPDM                USB_OTG_DOEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask          */
+#define USB_OTG_DOEPEACHMSK1_TOM_Pos             (3U)                          
+#define USB_OTG_DOEPEACHMSK1_TOM_Msk             (0x1UL << USB_OTG_DOEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */
+#define USB_OTG_DOEPEACHMSK1_TOM                 USB_OTG_DOEPEACHMSK1_TOM_Msk  /*!< Timeout condition mask                    */
+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos       (4U)                          
+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk       (0x1UL << USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */
+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK           USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask  */
+#define USB_OTG_DOEPEACHMSK1_INEPNMM_Pos         (5U)                          
+#define USB_OTG_DOEPEACHMSK1_INEPNMM_Msk         (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */
+#define USB_OTG_DOEPEACHMSK1_INEPNMM             USB_OTG_DOEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask   */
+#define USB_OTG_DOEPEACHMSK1_INEPNEM_Pos         (6U)                          
+#define USB_OTG_DOEPEACHMSK1_INEPNEM_Msk         (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */
+#define USB_OTG_DOEPEACHMSK1_INEPNEM             USB_OTG_DOEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask            */
+#define USB_OTG_DOEPEACHMSK1_TXFURM_Pos          (8U)                          
+#define USB_OTG_DOEPEACHMSK1_TXFURM_Msk          (0x1UL << USB_OTG_DOEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */
+#define USB_OTG_DOEPEACHMSK1_TXFURM              USB_OTG_DOEPEACHMSK1_TXFURM_Msk /*!< OUT packet error mask                     */
+#define USB_OTG_DOEPEACHMSK1_BIM_Pos             (9U)                          
+#define USB_OTG_DOEPEACHMSK1_BIM_Msk             (0x1UL << USB_OTG_DOEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */
+#define USB_OTG_DOEPEACHMSK1_BIM                 USB_OTG_DOEPEACHMSK1_BIM_Msk  /*!< BNA interrupt mask                        */
+#define USB_OTG_DOEPEACHMSK1_BERRM_Pos           (12U)                         
+#define USB_OTG_DOEPEACHMSK1_BERRM_Msk           (0x1UL << USB_OTG_DOEPEACHMSK1_BERRM_Pos) /*!< 0x00001000 */
+#define USB_OTG_DOEPEACHMSK1_BERRM               USB_OTG_DOEPEACHMSK1_BERRM_Msk /*!< Bubble error interrupt mask               */
+#define USB_OTG_DOEPEACHMSK1_NAKM_Pos            (13U)                         
+#define USB_OTG_DOEPEACHMSK1_NAKM_Msk            (0x1UL << USB_OTG_DOEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */
+#define USB_OTG_DOEPEACHMSK1_NAKM                USB_OTG_DOEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask                        */
+#define USB_OTG_DOEPEACHMSK1_NYETM_Pos           (14U)                         
+#define USB_OTG_DOEPEACHMSK1_NYETM_Msk           (0x1UL << USB_OTG_DOEPEACHMSK1_NYETM_Pos) /*!< 0x00004000 */
+#define USB_OTG_DOEPEACHMSK1_NYETM               USB_OTG_DOEPEACHMSK1_NYETM_Msk /*!< NYET interrupt mask                       */
+
+/********************  Bit definition for USB_OTG_HPTXFSIZ register  ********************/
+#define USB_OTG_HPTXFSIZ_PTXSA_Pos               (0U)                          
+#define USB_OTG_HPTXFSIZ_PTXSA_Msk               (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXSA_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HPTXFSIZ_PTXSA                   USB_OTG_HPTXFSIZ_PTXSA_Msk    /*!< Host periodic TxFIFO start address            */
+#define USB_OTG_HPTXFSIZ_PTXFD_Pos               (16U)                         
+#define USB_OTG_HPTXFSIZ_PTXFD_Msk               (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXFD_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_HPTXFSIZ_PTXFD                   USB_OTG_HPTXFSIZ_PTXFD_Msk    /*!< Host periodic TxFIFO depth                    */
+
+/********************  Bit definition for USB_OTG_DIEPCTL register  ********************/
+#define USB_OTG_DIEPCTL_MPSIZ_Pos                (0U)                          
+#define USB_OTG_DIEPCTL_MPSIZ_Msk                (0x7FFUL << USB_OTG_DIEPCTL_MPSIZ_Pos) /*!< 0x000007FF */
+#define USB_OTG_DIEPCTL_MPSIZ                    USB_OTG_DIEPCTL_MPSIZ_Msk     /*!< Maximum packet size              */
+#define USB_OTG_DIEPCTL_USBAEP_Pos               (15U)                         
+#define USB_OTG_DIEPCTL_USBAEP_Msk               (0x1UL << USB_OTG_DIEPCTL_USBAEP_Pos) /*!< 0x00008000 */
+#define USB_OTG_DIEPCTL_USBAEP                   USB_OTG_DIEPCTL_USBAEP_Msk    /*!< USB active endpoint              */
+#define USB_OTG_DIEPCTL_EONUM_DPID_Pos           (16U)                         
+#define USB_OTG_DIEPCTL_EONUM_DPID_Msk           (0x1UL << USB_OTG_DIEPCTL_EONUM_DPID_Pos) /*!< 0x00010000 */
+#define USB_OTG_DIEPCTL_EONUM_DPID               USB_OTG_DIEPCTL_EONUM_DPID_Msk /*!< Even/odd frame                   */
+#define USB_OTG_DIEPCTL_NAKSTS_Pos               (17U)                         
+#define USB_OTG_DIEPCTL_NAKSTS_Msk               (0x1UL << USB_OTG_DIEPCTL_NAKSTS_Pos) /*!< 0x00020000 */
+#define USB_OTG_DIEPCTL_NAKSTS                   USB_OTG_DIEPCTL_NAKSTS_Msk    /*!< NAK status                       */
+
+#define USB_OTG_DIEPCTL_EPTYP_Pos                (18U)                         
+#define USB_OTG_DIEPCTL_EPTYP_Msk                (0x3UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x000C0000 */
+#define USB_OTG_DIEPCTL_EPTYP                    USB_OTG_DIEPCTL_EPTYP_Msk     /*!< Endpoint type                    */
+#define USB_OTG_DIEPCTL_EPTYP_0                  (0x1UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00040000 */
+#define USB_OTG_DIEPCTL_EPTYP_1                  (0x2UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00080000 */
+#define USB_OTG_DIEPCTL_STALL_Pos                (21U)                         
+#define USB_OTG_DIEPCTL_STALL_Msk                (0x1UL << USB_OTG_DIEPCTL_STALL_Pos) /*!< 0x00200000 */
+#define USB_OTG_DIEPCTL_STALL                    USB_OTG_DIEPCTL_STALL_Msk     /*!< STALL handshake                  */
+
+#define USB_OTG_DIEPCTL_TXFNUM_Pos               (22U)                         
+#define USB_OTG_DIEPCTL_TXFNUM_Msk               (0xFUL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x03C00000 */
+#define USB_OTG_DIEPCTL_TXFNUM                   USB_OTG_DIEPCTL_TXFNUM_Msk    /*!< TxFIFO number                    */
+#define USB_OTG_DIEPCTL_TXFNUM_0                 (0x1UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00400000 */
+#define USB_OTG_DIEPCTL_TXFNUM_1                 (0x2UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00800000 */
+#define USB_OTG_DIEPCTL_TXFNUM_2                 (0x4UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x01000000 */
+#define USB_OTG_DIEPCTL_TXFNUM_3                 (0x8UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x02000000 */
+#define USB_OTG_DIEPCTL_CNAK_Pos                 (26U)                         
+#define USB_OTG_DIEPCTL_CNAK_Msk                 (0x1UL << USB_OTG_DIEPCTL_CNAK_Pos) /*!< 0x04000000 */
+#define USB_OTG_DIEPCTL_CNAK                     USB_OTG_DIEPCTL_CNAK_Msk      /*!< Clear NAK                        */
+#define USB_OTG_DIEPCTL_SNAK_Pos                 (27U)                         
+#define USB_OTG_DIEPCTL_SNAK_Msk                 (0x1UL << USB_OTG_DIEPCTL_SNAK_Pos) /*!< 0x08000000 */
+#define USB_OTG_DIEPCTL_SNAK                     USB_OTG_DIEPCTL_SNAK_Msk      /*!< Set NAK */
+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos       (28U)                         
+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk       (0x1UL << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */
+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM           USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID                    */
+#define USB_OTG_DIEPCTL_SODDFRM_Pos              (29U)                         
+#define USB_OTG_DIEPCTL_SODDFRM_Msk              (0x1UL << USB_OTG_DIEPCTL_SODDFRM_Pos) /*!< 0x20000000 */
+#define USB_OTG_DIEPCTL_SODDFRM                  USB_OTG_DIEPCTL_SODDFRM_Msk   /*!< Set odd frame                    */
+#define USB_OTG_DIEPCTL_EPDIS_Pos                (30U)                         
+#define USB_OTG_DIEPCTL_EPDIS_Msk                (0x1UL << USB_OTG_DIEPCTL_EPDIS_Pos) /*!< 0x40000000 */
+#define USB_OTG_DIEPCTL_EPDIS                    USB_OTG_DIEPCTL_EPDIS_Msk     /*!< Endpoint disable                 */
+#define USB_OTG_DIEPCTL_EPENA_Pos                (31U)                         
+#define USB_OTG_DIEPCTL_EPENA_Msk                (0x1UL << USB_OTG_DIEPCTL_EPENA_Pos) /*!< 0x80000000 */
+#define USB_OTG_DIEPCTL_EPENA                    USB_OTG_DIEPCTL_EPENA_Msk     /*!< Endpoint enable                  */
+
+/********************  Bit definition for USB_OTG_HCCHAR register  ********************/
+#define USB_OTG_HCCHAR_MPSIZ_Pos                 (0U)                          
+#define USB_OTG_HCCHAR_MPSIZ_Msk                 (0x7FFUL << USB_OTG_HCCHAR_MPSIZ_Pos) /*!< 0x000007FF */
+#define USB_OTG_HCCHAR_MPSIZ                     USB_OTG_HCCHAR_MPSIZ_Msk      /*!< Maximum packet size */
+
+#define USB_OTG_HCCHAR_EPNUM_Pos                 (11U)                         
+#define USB_OTG_HCCHAR_EPNUM_Msk                 (0xFUL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00007800 */
+#define USB_OTG_HCCHAR_EPNUM                     USB_OTG_HCCHAR_EPNUM_Msk      /*!< Endpoint number */
+#define USB_OTG_HCCHAR_EPNUM_0                   (0x1UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00000800 */
+#define USB_OTG_HCCHAR_EPNUM_1                   (0x2UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00001000 */
+#define USB_OTG_HCCHAR_EPNUM_2                   (0x4UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00002000 */
+#define USB_OTG_HCCHAR_EPNUM_3                   (0x8UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00004000 */
+#define USB_OTG_HCCHAR_EPDIR_Pos                 (15U)                         
+#define USB_OTG_HCCHAR_EPDIR_Msk                 (0x1UL << USB_OTG_HCCHAR_EPDIR_Pos) /*!< 0x00008000 */
+#define USB_OTG_HCCHAR_EPDIR                     USB_OTG_HCCHAR_EPDIR_Msk      /*!< Endpoint direction */
+#define USB_OTG_HCCHAR_LSDEV_Pos                 (17U)                         
+#define USB_OTG_HCCHAR_LSDEV_Msk                 (0x1UL << USB_OTG_HCCHAR_LSDEV_Pos) /*!< 0x00020000 */
+#define USB_OTG_HCCHAR_LSDEV                     USB_OTG_HCCHAR_LSDEV_Msk      /*!< Low-speed device */
+
+#define USB_OTG_HCCHAR_EPTYP_Pos                 (18U)                         
+#define USB_OTG_HCCHAR_EPTYP_Msk                 (0x3UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x000C0000 */
+#define USB_OTG_HCCHAR_EPTYP                     USB_OTG_HCCHAR_EPTYP_Msk      /*!< Endpoint type */
+#define USB_OTG_HCCHAR_EPTYP_0                   (0x1UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00040000 */
+#define USB_OTG_HCCHAR_EPTYP_1                   (0x2UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00080000 */
+
+#define USB_OTG_HCCHAR_MC_Pos                    (20U)                         
+#define USB_OTG_HCCHAR_MC_Msk                    (0x3UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00300000 */
+#define USB_OTG_HCCHAR_MC                        USB_OTG_HCCHAR_MC_Msk         /*!< Multi Count (MC) / Error Count (EC) */
+#define USB_OTG_HCCHAR_MC_0                      (0x1UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00100000 */
+#define USB_OTG_HCCHAR_MC_1                      (0x2UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00200000 */
+
+#define USB_OTG_HCCHAR_DAD_Pos                   (22U)                         
+#define USB_OTG_HCCHAR_DAD_Msk                   (0x7FUL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x1FC00000 */
+#define USB_OTG_HCCHAR_DAD                       USB_OTG_HCCHAR_DAD_Msk        /*!< Device address */
+#define USB_OTG_HCCHAR_DAD_0                     (0x01UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00400000 */
+#define USB_OTG_HCCHAR_DAD_1                     (0x02UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00800000 */
+#define USB_OTG_HCCHAR_DAD_2                     (0x04UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x01000000 */
+#define USB_OTG_HCCHAR_DAD_3                     (0x08UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x02000000 */
+#define USB_OTG_HCCHAR_DAD_4                     (0x10UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x04000000 */
+#define USB_OTG_HCCHAR_DAD_5                     (0x20UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x08000000 */
+#define USB_OTG_HCCHAR_DAD_6                     (0x40UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x10000000 */
+#define USB_OTG_HCCHAR_ODDFRM_Pos                (29U)                         
+#define USB_OTG_HCCHAR_ODDFRM_Msk                (0x1UL << USB_OTG_HCCHAR_ODDFRM_Pos) /*!< 0x20000000 */
+#define USB_OTG_HCCHAR_ODDFRM                    USB_OTG_HCCHAR_ODDFRM_Msk     /*!< Odd frame */
+#define USB_OTG_HCCHAR_CHDIS_Pos                 (30U)                         
+#define USB_OTG_HCCHAR_CHDIS_Msk                 (0x1UL << USB_OTG_HCCHAR_CHDIS_Pos) /*!< 0x40000000 */
+#define USB_OTG_HCCHAR_CHDIS                     USB_OTG_HCCHAR_CHDIS_Msk      /*!< Channel disable */
+#define USB_OTG_HCCHAR_CHENA_Pos                 (31U)                         
+#define USB_OTG_HCCHAR_CHENA_Msk                 (0x1UL << USB_OTG_HCCHAR_CHENA_Pos) /*!< 0x80000000 */
+#define USB_OTG_HCCHAR_CHENA                     USB_OTG_HCCHAR_CHENA_Msk      /*!< Channel enable */
+
+/********************  Bit definition for USB_OTG_HCSPLT register  ********************/
+
+#define USB_OTG_HCSPLT_PRTADDR_Pos               (0U)                          
+#define USB_OTG_HCSPLT_PRTADDR_Msk               (0x7FUL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x0000007F */
+#define USB_OTG_HCSPLT_PRTADDR                   USB_OTG_HCSPLT_PRTADDR_Msk    /*!< Port address */
+#define USB_OTG_HCSPLT_PRTADDR_0                 (0x01UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000001 */
+#define USB_OTG_HCSPLT_PRTADDR_1                 (0x02UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000002 */
+#define USB_OTG_HCSPLT_PRTADDR_2                 (0x04UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000004 */
+#define USB_OTG_HCSPLT_PRTADDR_3                 (0x08UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000008 */
+#define USB_OTG_HCSPLT_PRTADDR_4                 (0x10UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000010 */
+#define USB_OTG_HCSPLT_PRTADDR_5                 (0x20UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000020 */
+#define USB_OTG_HCSPLT_PRTADDR_6                 (0x40UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000040 */
+
+#define USB_OTG_HCSPLT_HUBADDR_Pos               (7U)                          
+#define USB_OTG_HCSPLT_HUBADDR_Msk               (0x7FUL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00003F80 */
+#define USB_OTG_HCSPLT_HUBADDR                   USB_OTG_HCSPLT_HUBADDR_Msk    /*!< Hub address */
+#define USB_OTG_HCSPLT_HUBADDR_0                 (0x01UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000080 */
+#define USB_OTG_HCSPLT_HUBADDR_1                 (0x02UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000100 */
+#define USB_OTG_HCSPLT_HUBADDR_2                 (0x04UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000200 */
+#define USB_OTG_HCSPLT_HUBADDR_3                 (0x08UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000400 */
+#define USB_OTG_HCSPLT_HUBADDR_4                 (0x10UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000800 */
+#define USB_OTG_HCSPLT_HUBADDR_5                 (0x20UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00001000 */
+#define USB_OTG_HCSPLT_HUBADDR_6                 (0x40UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00002000 */
+
+#define USB_OTG_HCSPLT_XACTPOS_Pos               (14U)                         
+#define USB_OTG_HCSPLT_XACTPOS_Msk               (0x3UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x0000C000 */
+#define USB_OTG_HCSPLT_XACTPOS                   USB_OTG_HCSPLT_XACTPOS_Msk    /*!< XACTPOS */
+#define USB_OTG_HCSPLT_XACTPOS_0                 (0x1UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00004000 */
+#define USB_OTG_HCSPLT_XACTPOS_1                 (0x2UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00008000 */
+#define USB_OTG_HCSPLT_COMPLSPLT_Pos             (16U)                         
+#define USB_OTG_HCSPLT_COMPLSPLT_Msk             (0x1UL << USB_OTG_HCSPLT_COMPLSPLT_Pos) /*!< 0x00010000 */
+#define USB_OTG_HCSPLT_COMPLSPLT                 USB_OTG_HCSPLT_COMPLSPLT_Msk  /*!< Do complete split */
+#define USB_OTG_HCSPLT_SPLITEN_Pos               (31U)                         
+#define USB_OTG_HCSPLT_SPLITEN_Msk               (0x1UL << USB_OTG_HCSPLT_SPLITEN_Pos) /*!< 0x80000000 */
+#define USB_OTG_HCSPLT_SPLITEN                   USB_OTG_HCSPLT_SPLITEN_Msk    /*!< Split enable */
+
+/********************  Bit definition for USB_OTG_HCINT register  ********************/
+#define USB_OTG_HCINT_XFRC_Pos                   (0U)                          
+#define USB_OTG_HCINT_XFRC_Msk                   (0x1UL << USB_OTG_HCINT_XFRC_Pos) /*!< 0x00000001 */
+#define USB_OTG_HCINT_XFRC                       USB_OTG_HCINT_XFRC_Msk        /*!< Transfer completed */
+#define USB_OTG_HCINT_CHH_Pos                    (1U)                          
+#define USB_OTG_HCINT_CHH_Msk                    (0x1UL << USB_OTG_HCINT_CHH_Pos) /*!< 0x00000002 */
+#define USB_OTG_HCINT_CHH                        USB_OTG_HCINT_CHH_Msk         /*!< Channel halted */
+#define USB_OTG_HCINT_AHBERR_Pos                 (2U)                          
+#define USB_OTG_HCINT_AHBERR_Msk                 (0x1UL << USB_OTG_HCINT_AHBERR_Pos) /*!< 0x00000004 */
+#define USB_OTG_HCINT_AHBERR                     USB_OTG_HCINT_AHBERR_Msk      /*!< AHB error */
+#define USB_OTG_HCINT_STALL_Pos                  (3U)                          
+#define USB_OTG_HCINT_STALL_Msk                  (0x1UL << USB_OTG_HCINT_STALL_Pos) /*!< 0x00000008 */
+#define USB_OTG_HCINT_STALL                      USB_OTG_HCINT_STALL_Msk       /*!< STALL response received interrupt */
+#define USB_OTG_HCINT_NAK_Pos                    (4U)                          
+#define USB_OTG_HCINT_NAK_Msk                    (0x1UL << USB_OTG_HCINT_NAK_Pos) /*!< 0x00000010 */
+#define USB_OTG_HCINT_NAK                        USB_OTG_HCINT_NAK_Msk         /*!< NAK response received interrupt */
+#define USB_OTG_HCINT_ACK_Pos                    (5U)                          
+#define USB_OTG_HCINT_ACK_Msk                    (0x1UL << USB_OTG_HCINT_ACK_Pos) /*!< 0x00000020 */
+#define USB_OTG_HCINT_ACK                        USB_OTG_HCINT_ACK_Msk         /*!< ACK response received/transmitted interrupt */
+#define USB_OTG_HCINT_NYET_Pos                   (6U)                          
+#define USB_OTG_HCINT_NYET_Msk                   (0x1UL << USB_OTG_HCINT_NYET_Pos) /*!< 0x00000040 */
+#define USB_OTG_HCINT_NYET                       USB_OTG_HCINT_NYET_Msk        /*!< Response received interrupt */
+#define USB_OTG_HCINT_TXERR_Pos                  (7U)                          
+#define USB_OTG_HCINT_TXERR_Msk                  (0x1UL << USB_OTG_HCINT_TXERR_Pos) /*!< 0x00000080 */
+#define USB_OTG_HCINT_TXERR                      USB_OTG_HCINT_TXERR_Msk       /*!< Transaction error */
+#define USB_OTG_HCINT_BBERR_Pos                  (8U)                          
+#define USB_OTG_HCINT_BBERR_Msk                  (0x1UL << USB_OTG_HCINT_BBERR_Pos) /*!< 0x00000100 */
+#define USB_OTG_HCINT_BBERR                      USB_OTG_HCINT_BBERR_Msk       /*!< Babble error */
+#define USB_OTG_HCINT_FRMOR_Pos                  (9U)                          
+#define USB_OTG_HCINT_FRMOR_Msk                  (0x1UL << USB_OTG_HCINT_FRMOR_Pos) /*!< 0x00000200 */
+#define USB_OTG_HCINT_FRMOR                      USB_OTG_HCINT_FRMOR_Msk       /*!< Frame overrun */
+#define USB_OTG_HCINT_DTERR_Pos                  (10U)                         
+#define USB_OTG_HCINT_DTERR_Msk                  (0x1UL << USB_OTG_HCINT_DTERR_Pos) /*!< 0x00000400 */
+#define USB_OTG_HCINT_DTERR                      USB_OTG_HCINT_DTERR_Msk       /*!< Data toggle error */
+
+/********************  Bit definition for USB_OTG_DIEPINT register  ********************/
+#define USB_OTG_DIEPINT_XFRC_Pos                 (0U)                          
+#define USB_OTG_DIEPINT_XFRC_Msk                 (0x1UL << USB_OTG_DIEPINT_XFRC_Pos) /*!< 0x00000001 */
+#define USB_OTG_DIEPINT_XFRC                     USB_OTG_DIEPINT_XFRC_Msk      /*!< Transfer completed interrupt */
+#define USB_OTG_DIEPINT_EPDISD_Pos               (1U)                          
+#define USB_OTG_DIEPINT_EPDISD_Msk               (0x1UL << USB_OTG_DIEPINT_EPDISD_Pos) /*!< 0x00000002 */
+#define USB_OTG_DIEPINT_EPDISD                   USB_OTG_DIEPINT_EPDISD_Msk    /*!< Endpoint disabled interrupt */
+#define USB_OTG_DIEPINT_AHBERR_Pos               (2U)
+#define USB_OTG_DIEPINT_AHBERR_Msk               (0x1UL << USB_OTG_DIEPINT_AHBERR_Pos) /*!< 0x00000004 */
+#define USB_OTG_DIEPINT_AHBERR                   USB_OTG_DIEPINT_AHBERR_Msk   /*!< AHB Error (AHBErr) during an IN transaction */
+#define USB_OTG_DIEPINT_TOC_Pos                  (3U)                          
+#define USB_OTG_DIEPINT_TOC_Msk                  (0x1UL << USB_OTG_DIEPINT_TOC_Pos) /*!< 0x00000008 */
+#define USB_OTG_DIEPINT_TOC                      USB_OTG_DIEPINT_TOC_Msk       /*!< Timeout condition */
+#define USB_OTG_DIEPINT_ITTXFE_Pos               (4U)                          
+#define USB_OTG_DIEPINT_ITTXFE_Msk               (0x1UL << USB_OTG_DIEPINT_ITTXFE_Pos) /*!< 0x00000010 */
+#define USB_OTG_DIEPINT_ITTXFE                   USB_OTG_DIEPINT_ITTXFE_Msk    /*!< IN token received when TxFIFO is empty */
+#define USB_OTG_DIEPINT_INEPNM_Pos               (5U)
+#define USB_OTG_DIEPINT_INEPNM_Msk               (0x1UL << USB_OTG_DIEPINT_INEPNM_Pos) /*!< 0x00000004 */
+#define USB_OTG_DIEPINT_INEPNM                   USB_OTG_DIEPINT_INEPNM_Msk   /*!< IN token received with EP mismatch */
+#define USB_OTG_DIEPINT_INEPNE_Pos               (6U)                          
+#define USB_OTG_DIEPINT_INEPNE_Msk               (0x1UL << USB_OTG_DIEPINT_INEPNE_Pos) /*!< 0x00000040 */
+#define USB_OTG_DIEPINT_INEPNE                   USB_OTG_DIEPINT_INEPNE_Msk    /*!< IN endpoint NAK effective */
+#define USB_OTG_DIEPINT_TXFE_Pos                 (7U)                          
+#define USB_OTG_DIEPINT_TXFE_Msk                 (0x1UL << USB_OTG_DIEPINT_TXFE_Pos) /*!< 0x00000080 */
+#define USB_OTG_DIEPINT_TXFE                     USB_OTG_DIEPINT_TXFE_Msk      /*!< Transmit FIFO empty */
+#define USB_OTG_DIEPINT_TXFIFOUDRN_Pos           (8U)                          
+#define USB_OTG_DIEPINT_TXFIFOUDRN_Msk           (0x1UL << USB_OTG_DIEPINT_TXFIFOUDRN_Pos) /*!< 0x00000100 */
+#define USB_OTG_DIEPINT_TXFIFOUDRN               USB_OTG_DIEPINT_TXFIFOUDRN_Msk /*!< Transmit Fifo Underrun */
+#define USB_OTG_DIEPINT_BNA_Pos                  (9U)                          
+#define USB_OTG_DIEPINT_BNA_Msk                  (0x1UL << USB_OTG_DIEPINT_BNA_Pos) /*!< 0x00000200 */
+#define USB_OTG_DIEPINT_BNA                      USB_OTG_DIEPINT_BNA_Msk       /*!< Buffer not available interrupt */
+#define USB_OTG_DIEPINT_PKTDRPSTS_Pos            (11U)                         
+#define USB_OTG_DIEPINT_PKTDRPSTS_Msk            (0x1UL << USB_OTG_DIEPINT_PKTDRPSTS_Pos) /*!< 0x00000800 */
+#define USB_OTG_DIEPINT_PKTDRPSTS                USB_OTG_DIEPINT_PKTDRPSTS_Msk /*!< Packet dropped status */
+#define USB_OTG_DIEPINT_BERR_Pos                 (12U)                         
+#define USB_OTG_DIEPINT_BERR_Msk                 (0x1UL << USB_OTG_DIEPINT_BERR_Pos) /*!< 0x00001000 */
+#define USB_OTG_DIEPINT_BERR                     USB_OTG_DIEPINT_BERR_Msk      /*!< Babble error interrupt */
+#define USB_OTG_DIEPINT_NAK_Pos                  (13U)                         
+#define USB_OTG_DIEPINT_NAK_Msk                  (0x1UL << USB_OTG_DIEPINT_NAK_Pos) /*!< 0x00002000 */
+#define USB_OTG_DIEPINT_NAK                      USB_OTG_DIEPINT_NAK_Msk       /*!< NAK interrupt */
+
+/********************  Bit definition forUSB_OTG_HCINTMSK register  ********************/
+#define USB_OTG_HCINTMSK_XFRCM_Pos               (0U)                          
+#define USB_OTG_HCINTMSK_XFRCM_Msk               (0x1UL << USB_OTG_HCINTMSK_XFRCM_Pos) /*!< 0x00000001 */
+#define USB_OTG_HCINTMSK_XFRCM                   USB_OTG_HCINTMSK_XFRCM_Msk    /*!< Transfer completed mask */
+#define USB_OTG_HCINTMSK_CHHM_Pos                (1U)                          
+#define USB_OTG_HCINTMSK_CHHM_Msk                (0x1UL << USB_OTG_HCINTMSK_CHHM_Pos) /*!< 0x00000002 */
+#define USB_OTG_HCINTMSK_CHHM                    USB_OTG_HCINTMSK_CHHM_Msk     /*!< Channel halted mask */
+#define USB_OTG_HCINTMSK_AHBERR_Pos              (2U)                          
+#define USB_OTG_HCINTMSK_AHBERR_Msk              (0x1UL << USB_OTG_HCINTMSK_AHBERR_Pos) /*!< 0x00000004 */
+#define USB_OTG_HCINTMSK_AHBERR                  USB_OTG_HCINTMSK_AHBERR_Msk   /*!< AHB error */
+#define USB_OTG_HCINTMSK_STALLM_Pos              (3U)                          
+#define USB_OTG_HCINTMSK_STALLM_Msk              (0x1UL << USB_OTG_HCINTMSK_STALLM_Pos) /*!< 0x00000008 */
+#define USB_OTG_HCINTMSK_STALLM                  USB_OTG_HCINTMSK_STALLM_Msk   /*!< STALL response received interrupt mask */
+#define USB_OTG_HCINTMSK_NAKM_Pos                (4U)                          
+#define USB_OTG_HCINTMSK_NAKM_Msk                (0x1UL << USB_OTG_HCINTMSK_NAKM_Pos) /*!< 0x00000010 */
+#define USB_OTG_HCINTMSK_NAKM                    USB_OTG_HCINTMSK_NAKM_Msk     /*!< NAK response received interrupt mask */
+#define USB_OTG_HCINTMSK_ACKM_Pos                (5U)                          
+#define USB_OTG_HCINTMSK_ACKM_Msk                (0x1UL << USB_OTG_HCINTMSK_ACKM_Pos) /*!< 0x00000020 */
+#define USB_OTG_HCINTMSK_ACKM                    USB_OTG_HCINTMSK_ACKM_Msk     /*!< ACK response received/transmitted interrupt mask */
+#define USB_OTG_HCINTMSK_NYET_Pos                (6U)                          
+#define USB_OTG_HCINTMSK_NYET_Msk                (0x1UL << USB_OTG_HCINTMSK_NYET_Pos) /*!< 0x00000040 */
+#define USB_OTG_HCINTMSK_NYET                    USB_OTG_HCINTMSK_NYET_Msk     /*!< response received interrupt mask */
+#define USB_OTG_HCINTMSK_TXERRM_Pos              (7U)                          
+#define USB_OTG_HCINTMSK_TXERRM_Msk              (0x1UL << USB_OTG_HCINTMSK_TXERRM_Pos) /*!< 0x00000080 */
+#define USB_OTG_HCINTMSK_TXERRM                  USB_OTG_HCINTMSK_TXERRM_Msk   /*!< Transaction error mask */
+#define USB_OTG_HCINTMSK_BBERRM_Pos              (8U)                          
+#define USB_OTG_HCINTMSK_BBERRM_Msk              (0x1UL << USB_OTG_HCINTMSK_BBERRM_Pos) /*!< 0x00000100 */
+#define USB_OTG_HCINTMSK_BBERRM                  USB_OTG_HCINTMSK_BBERRM_Msk   /*!< Babble error mask */
+#define USB_OTG_HCINTMSK_FRMORM_Pos              (9U)                          
+#define USB_OTG_HCINTMSK_FRMORM_Msk              (0x1UL << USB_OTG_HCINTMSK_FRMORM_Pos) /*!< 0x00000200 */
+#define USB_OTG_HCINTMSK_FRMORM                  USB_OTG_HCINTMSK_FRMORM_Msk   /*!< Frame overrun mask */
+#define USB_OTG_HCINTMSK_DTERRM_Pos              (10U)                         
+#define USB_OTG_HCINTMSK_DTERRM_Msk              (0x1UL << USB_OTG_HCINTMSK_DTERRM_Pos) /*!< 0x00000400 */
+#define USB_OTG_HCINTMSK_DTERRM                  USB_OTG_HCINTMSK_DTERRM_Msk   /*!< Data toggle error mask */
+
+/********************  Bit definition for USB_OTG_DIEPTSIZ register  ********************/
+
+#define USB_OTG_DIEPTSIZ_XFRSIZ_Pos              (0U)                          
+#define USB_OTG_DIEPTSIZ_XFRSIZ_Msk              (0x7FFFFUL << USB_OTG_DIEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
+#define USB_OTG_DIEPTSIZ_XFRSIZ                  USB_OTG_DIEPTSIZ_XFRSIZ_Msk   /*!< Transfer size */
+#define USB_OTG_DIEPTSIZ_PKTCNT_Pos              (19U)                         
+#define USB_OTG_DIEPTSIZ_PKTCNT_Msk              (0x3FFUL << USB_OTG_DIEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
+#define USB_OTG_DIEPTSIZ_PKTCNT                  USB_OTG_DIEPTSIZ_PKTCNT_Msk   /*!< Packet count */
+#define USB_OTG_DIEPTSIZ_MULCNT_Pos              (29U)                         
+#define USB_OTG_DIEPTSIZ_MULCNT_Msk              (0x3UL << USB_OTG_DIEPTSIZ_MULCNT_Pos) /*!< 0x60000000 */
+#define USB_OTG_DIEPTSIZ_MULCNT                  USB_OTG_DIEPTSIZ_MULCNT_Msk   /*!< Packet count */
+/********************  Bit definition for USB_OTG_HCTSIZ register  ********************/
+#define USB_OTG_HCTSIZ_XFRSIZ_Pos                (0U)                          
+#define USB_OTG_HCTSIZ_XFRSIZ_Msk                (0x7FFFFUL << USB_OTG_HCTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
+#define USB_OTG_HCTSIZ_XFRSIZ                    USB_OTG_HCTSIZ_XFRSIZ_Msk     /*!< Transfer size */
+#define USB_OTG_HCTSIZ_PKTCNT_Pos                (19U)                         
+#define USB_OTG_HCTSIZ_PKTCNT_Msk                (0x3FFUL << USB_OTG_HCTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
+#define USB_OTG_HCTSIZ_PKTCNT                    USB_OTG_HCTSIZ_PKTCNT_Msk     /*!< Packet count */
+#define USB_OTG_HCTSIZ_DOPING_Pos                (31U)                         
+#define USB_OTG_HCTSIZ_DOPING_Msk                (0x1UL << USB_OTG_HCTSIZ_DOPING_Pos) /*!< 0x80000000 */
+#define USB_OTG_HCTSIZ_DOPING                    USB_OTG_HCTSIZ_DOPING_Msk     /*!< Do PING */
+#define USB_OTG_HCTSIZ_DPID_Pos                  (29U)                         
+#define USB_OTG_HCTSIZ_DPID_Msk                  (0x3UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x60000000 */
+#define USB_OTG_HCTSIZ_DPID                      USB_OTG_HCTSIZ_DPID_Msk       /*!< Data PID */
+#define USB_OTG_HCTSIZ_DPID_0                    (0x1UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x20000000 */
+#define USB_OTG_HCTSIZ_DPID_1                    (0x2UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x40000000 */
+
+/********************  Bit definition for USB_OTG_DIEPDMA register  ********************/
+#define USB_OTG_DIEPDMA_DMAADDR_Pos              (0U)                          
+#define USB_OTG_DIEPDMA_DMAADDR_Msk              (0xFFFFFFFFUL << USB_OTG_DIEPDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */
+#define USB_OTG_DIEPDMA_DMAADDR                  USB_OTG_DIEPDMA_DMAADDR_Msk   /*!< DMA address */
+
+/********************  Bit definition for USB_OTG_HCDMA register  ********************/
+#define USB_OTG_HCDMA_DMAADDR_Pos                (0U)                          
+#define USB_OTG_HCDMA_DMAADDR_Msk                (0xFFFFFFFFUL << USB_OTG_HCDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */
+#define USB_OTG_HCDMA_DMAADDR                    USB_OTG_HCDMA_DMAADDR_Msk     /*!< DMA address */
+
+/********************  Bit definition for USB_OTG_DTXFSTS register  ********************/
+#define USB_OTG_DTXFSTS_INEPTFSAV_Pos            (0U)                          
+#define USB_OTG_DTXFSTS_INEPTFSAV_Msk            (0xFFFFUL << USB_OTG_DTXFSTS_INEPTFSAV_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DTXFSTS_INEPTFSAV                USB_OTG_DTXFSTS_INEPTFSAV_Msk /*!< IN endpoint TxFIFO space available */
+
+/********************  Bit definition for USB_OTG_DIEPTXF register  ********************/
+#define USB_OTG_DIEPTXF_INEPTXSA_Pos             (0U)                          
+#define USB_OTG_DIEPTXF_INEPTXSA_Msk             (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXSA_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DIEPTXF_INEPTXSA                 USB_OTG_DIEPTXF_INEPTXSA_Msk  /*!< IN endpoint FIFOx transmit RAM start address */
+#define USB_OTG_DIEPTXF_INEPTXFD_Pos             (16U)                         
+#define USB_OTG_DIEPTXF_INEPTXFD_Msk             (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXFD_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_DIEPTXF_INEPTXFD                 USB_OTG_DIEPTXF_INEPTXFD_Msk  /*!< IN endpoint TxFIFO depth */
+
+/********************  Bit definition for USB_OTG_DOEPCTL register  ********************/
+
+#define USB_OTG_DOEPCTL_MPSIZ_Pos                (0U)                          
+#define USB_OTG_DOEPCTL_MPSIZ_Msk                (0x7FFUL << USB_OTG_DOEPCTL_MPSIZ_Pos) /*!< 0x000007FF */
+#define USB_OTG_DOEPCTL_MPSIZ                    USB_OTG_DOEPCTL_MPSIZ_Msk     /*!< Maximum packet size */          /*!<Bit 1 */
+#define USB_OTG_DOEPCTL_USBAEP_Pos               (15U)                         
+#define USB_OTG_DOEPCTL_USBAEP_Msk               (0x1UL << USB_OTG_DOEPCTL_USBAEP_Pos) /*!< 0x00008000 */
+#define USB_OTG_DOEPCTL_USBAEP                   USB_OTG_DOEPCTL_USBAEP_Msk    /*!< USB active endpoint */
+#define USB_OTG_DOEPCTL_NAKSTS_Pos               (17U)                         
+#define USB_OTG_DOEPCTL_NAKSTS_Msk               (0x1UL << USB_OTG_DOEPCTL_NAKSTS_Pos) /*!< 0x00020000 */
+#define USB_OTG_DOEPCTL_NAKSTS                   USB_OTG_DOEPCTL_NAKSTS_Msk    /*!< NAK status */
+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos       (28U)                         
+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk       (0x1UL << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */
+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM           USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */
+#define USB_OTG_DOEPCTL_SODDFRM_Pos              (29U)                         
+#define USB_OTG_DOEPCTL_SODDFRM_Msk              (0x1UL << USB_OTG_DOEPCTL_SODDFRM_Pos) /*!< 0x20000000 */
+#define USB_OTG_DOEPCTL_SODDFRM                  USB_OTG_DOEPCTL_SODDFRM_Msk   /*!< Set odd frame */
+#define USB_OTG_DOEPCTL_EPTYP_Pos                (18U)                         
+#define USB_OTG_DOEPCTL_EPTYP_Msk                (0x3UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x000C0000 */
+#define USB_OTG_DOEPCTL_EPTYP                    USB_OTG_DOEPCTL_EPTYP_Msk     /*!< Endpoint type */
+#define USB_OTG_DOEPCTL_EPTYP_0                  (0x1UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00040000 */
+#define USB_OTG_DOEPCTL_EPTYP_1                  (0x2UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00080000 */
+#define USB_OTG_DOEPCTL_SNPM_Pos                 (20U)                         
+#define USB_OTG_DOEPCTL_SNPM_Msk                 (0x1UL << USB_OTG_DOEPCTL_SNPM_Pos) /*!< 0x00100000 */
+#define USB_OTG_DOEPCTL_SNPM                     USB_OTG_DOEPCTL_SNPM_Msk      /*!< Snoop mode */
+#define USB_OTG_DOEPCTL_STALL_Pos                (21U)                         
+#define USB_OTG_DOEPCTL_STALL_Msk                (0x1UL << USB_OTG_DOEPCTL_STALL_Pos) /*!< 0x00200000 */
+#define USB_OTG_DOEPCTL_STALL                    USB_OTG_DOEPCTL_STALL_Msk     /*!< STALL handshake */
+#define USB_OTG_DOEPCTL_CNAK_Pos                 (26U)                         
+#define USB_OTG_DOEPCTL_CNAK_Msk                 (0x1UL << USB_OTG_DOEPCTL_CNAK_Pos) /*!< 0x04000000 */
+#define USB_OTG_DOEPCTL_CNAK                     USB_OTG_DOEPCTL_CNAK_Msk      /*!< Clear NAK */
+#define USB_OTG_DOEPCTL_SNAK_Pos                 (27U)                         
+#define USB_OTG_DOEPCTL_SNAK_Msk                 (0x1UL << USB_OTG_DOEPCTL_SNAK_Pos) /*!< 0x08000000 */
+#define USB_OTG_DOEPCTL_SNAK                     USB_OTG_DOEPCTL_SNAK_Msk      /*!< Set NAK */
+#define USB_OTG_DOEPCTL_EPDIS_Pos                (30U)                         
+#define USB_OTG_DOEPCTL_EPDIS_Msk                (0x1UL << USB_OTG_DOEPCTL_EPDIS_Pos) /*!< 0x40000000 */
+#define USB_OTG_DOEPCTL_EPDIS                    USB_OTG_DOEPCTL_EPDIS_Msk     /*!< Endpoint disable */
+#define USB_OTG_DOEPCTL_EPENA_Pos                (31U)                         
+#define USB_OTG_DOEPCTL_EPENA_Msk                (0x1UL << USB_OTG_DOEPCTL_EPENA_Pos) /*!< 0x80000000 */
+#define USB_OTG_DOEPCTL_EPENA                    USB_OTG_DOEPCTL_EPENA_Msk     /*!< Endpoint enable */
+
+/********************  Bit definition for USB_OTG_DOEPINT register  ********************/
+#define USB_OTG_DOEPINT_XFRC_Pos                 (0U)                          
+#define USB_OTG_DOEPINT_XFRC_Msk                 (0x1UL << USB_OTG_DOEPINT_XFRC_Pos) /*!< 0x00000001 */
+#define USB_OTG_DOEPINT_XFRC                     USB_OTG_DOEPINT_XFRC_Msk      /*!< Transfer completed interrupt */
+#define USB_OTG_DOEPINT_EPDISD_Pos               (1U)                          
+#define USB_OTG_DOEPINT_EPDISD_Msk               (0x1UL << USB_OTG_DOEPINT_EPDISD_Pos) /*!< 0x00000002 */
+#define USB_OTG_DOEPINT_EPDISD                   USB_OTG_DOEPINT_EPDISD_Msk    /*!< Endpoint disabled interrupt */
+#define USB_OTG_DOEPINT_AHBERR_Pos               (2U)
+#define USB_OTG_DOEPINT_AHBERR_Msk               (0x1UL << USB_OTG_DOEPINT_AHBERR_Pos) /*!< 0x00000004 */
+#define USB_OTG_DOEPINT_AHBERR                   USB_OTG_DOEPINT_AHBERR_Msk   /*!< AHB Error (AHBErr) during an OUT transaction */
+#define USB_OTG_DOEPINT_STUP_Pos                 (3U)                          
+#define USB_OTG_DOEPINT_STUP_Msk                 (0x1UL << USB_OTG_DOEPINT_STUP_Pos) /*!< 0x00000008 */
+#define USB_OTG_DOEPINT_STUP                     USB_OTG_DOEPINT_STUP_Msk      /*!< SETUP phase done */
+#define USB_OTG_DOEPINT_OTEPDIS_Pos              (4U)                          
+#define USB_OTG_DOEPINT_OTEPDIS_Msk              (0x1UL << USB_OTG_DOEPINT_OTEPDIS_Pos) /*!< 0x00000010 */
+#define USB_OTG_DOEPINT_OTEPDIS                  USB_OTG_DOEPINT_OTEPDIS_Msk   /*!< OUT token received when endpoint disabled */
+#define USB_OTG_DOEPINT_OTEPSPR_Pos              (5U)                          
+#define USB_OTG_DOEPINT_OTEPSPR_Msk              (0x1UL << USB_OTG_DOEPINT_OTEPSPR_Pos) /*!< 0x00000020 */
+#define USB_OTG_DOEPINT_OTEPSPR                  USB_OTG_DOEPINT_OTEPSPR_Msk   /*!< Status Phase Received For Control Write */
+#define USB_OTG_DOEPINT_B2BSTUP_Pos              (6U)                          
+#define USB_OTG_DOEPINT_B2BSTUP_Msk              (0x1UL << USB_OTG_DOEPINT_B2BSTUP_Pos) /*!< 0x00000040 */
+#define USB_OTG_DOEPINT_B2BSTUP                  USB_OTG_DOEPINT_B2BSTUP_Msk   /*!< Back-to-back SETUP packets received */
+#define USB_OTG_DOEPINT_OUTPKTERR_Pos            (8U)
+#define USB_OTG_DOEPINT_OUTPKTERR_Msk            (0x1UL << USB_OTG_DOEPINT_OUTPKTERR_Pos) /*!< 0x00000100 */
+#define USB_OTG_DOEPINT_OUTPKTERR                USB_OTG_DOEPINT_OUTPKTERR_Msk   /*!< OUT packet error */
+#define USB_OTG_DOEPINT_NAK_Pos                  (13U)
+#define USB_OTG_DOEPINT_NAK_Msk                  (0x1UL << USB_OTG_DOEPINT_NAK_Pos) /*!< 0x00002000 */
+#define USB_OTG_DOEPINT_NAK                      USB_OTG_DOEPINT_NAK_Msk   /*!< NAK Packet is transmitted by the device */
+#define USB_OTG_DOEPINT_NYET_Pos                 (14U)                         
+#define USB_OTG_DOEPINT_NYET_Msk                 (0x1UL << USB_OTG_DOEPINT_NYET_Pos) /*!< 0x00004000 */
+#define USB_OTG_DOEPINT_NYET                     USB_OTG_DOEPINT_NYET_Msk      /*!< NYET interrupt */
+#define USB_OTG_DOEPINT_STPKTRX_Pos              (15U)
+#define USB_OTG_DOEPINT_STPKTRX_Msk              (0x1UL << USB_OTG_DOEPINT_STPKTRX_Pos) /*!< 0x00008000 */
+#define USB_OTG_DOEPINT_STPKTRX                  USB_OTG_DOEPINT_STPKTRX_Msk   /*!< Setup Packet Received */
+/********************  Bit definition for USB_OTG_DOEPTSIZ register  ********************/
+
+#define USB_OTG_DOEPTSIZ_XFRSIZ_Pos              (0U)                          
+#define USB_OTG_DOEPTSIZ_XFRSIZ_Msk              (0x7FFFFUL << USB_OTG_DOEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
+#define USB_OTG_DOEPTSIZ_XFRSIZ                  USB_OTG_DOEPTSIZ_XFRSIZ_Msk   /*!< Transfer size */
+#define USB_OTG_DOEPTSIZ_PKTCNT_Pos              (19U)                         
+#define USB_OTG_DOEPTSIZ_PKTCNT_Msk              (0x3FFUL << USB_OTG_DOEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
+#define USB_OTG_DOEPTSIZ_PKTCNT                  USB_OTG_DOEPTSIZ_PKTCNT_Msk   /*!< Packet count */
+
+#define USB_OTG_DOEPTSIZ_STUPCNT_Pos             (29U)                         
+#define USB_OTG_DOEPTSIZ_STUPCNT_Msk             (0x3UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x60000000 */
+#define USB_OTG_DOEPTSIZ_STUPCNT                 USB_OTG_DOEPTSIZ_STUPCNT_Msk  /*!< SETUP packet count */
+#define USB_OTG_DOEPTSIZ_STUPCNT_0               (0x1UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x20000000 */
+#define USB_OTG_DOEPTSIZ_STUPCNT_1               (0x2UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x40000000 */
+
+/********************  Bit definition for PCGCCTL register  ********************/
+#define USB_OTG_PCGCCTL_STOPCLK_Pos              (0U)                          
+#define USB_OTG_PCGCCTL_STOPCLK_Msk              (0x1UL << USB_OTG_PCGCCTL_STOPCLK_Pos) /*!< 0x00000001 */
+#define USB_OTG_PCGCCTL_STOPCLK                  USB_OTG_PCGCCTL_STOPCLK_Msk   /*!< SETUP packet count */
+#define USB_OTG_PCGCCTL_GATECLK_Pos              (1U)                          
+#define USB_OTG_PCGCCTL_GATECLK_Msk              (0x1UL << USB_OTG_PCGCCTL_GATECLK_Pos) /*!< 0x00000002 */
+#define USB_OTG_PCGCCTL_GATECLK                  USB_OTG_PCGCCTL_GATECLK_Msk   /*!<Bit 0 */
+#define USB_OTG_PCGCCTL_PHYSUSP_Pos              (4U)                          
+#define USB_OTG_PCGCCTL_PHYSUSP_Msk              (0x1UL << USB_OTG_PCGCCTL_PHYSUSP_Pos) /*!< 0x00000010 */
+#define USB_OTG_PCGCCTL_PHYSUSP                  USB_OTG_PCGCCTL_PHYSUSP_Msk   /*!<Bit 1 */
+
+/* Legacy define */
+/********************  Bit definition for OTG register  ********************/
+#define USB_OTG_CHNUM_Pos                        (0U)                          
+#define USB_OTG_CHNUM_Msk                        (0xFUL << USB_OTG_CHNUM_Pos)   /*!< 0x0000000F */
+#define USB_OTG_CHNUM                            USB_OTG_CHNUM_Msk             /*!< Channel number */
+#define USB_OTG_CHNUM_0                          (0x1UL << USB_OTG_CHNUM_Pos)   /*!< 0x00000001 */
+#define USB_OTG_CHNUM_1                          (0x2UL << USB_OTG_CHNUM_Pos)   /*!< 0x00000002 */
+#define USB_OTG_CHNUM_2                          (0x4UL << USB_OTG_CHNUM_Pos)   /*!< 0x00000004 */
+#define USB_OTG_CHNUM_3                          (0x8UL << USB_OTG_CHNUM_Pos)   /*!< 0x00000008 */
+#define USB_OTG_BCNT_Pos                         (4U)                          
+#define USB_OTG_BCNT_Msk                         (0x7FFUL << USB_OTG_BCNT_Pos)  /*!< 0x00007FF0 */
+#define USB_OTG_BCNT                             USB_OTG_BCNT_Msk              /*!< Byte count */
+
+#define USB_OTG_DPID_Pos                         (15U)                         
+#define USB_OTG_DPID_Msk                         (0x3UL << USB_OTG_DPID_Pos)    /*!< 0x00018000 */
+#define USB_OTG_DPID                             USB_OTG_DPID_Msk              /*!< Data PID */
+#define USB_OTG_DPID_0                           (0x1UL << USB_OTG_DPID_Pos)    /*!< 0x00008000 */
+#define USB_OTG_DPID_1                           (0x2UL << USB_OTG_DPID_Pos)    /*!< 0x00010000 */
+
+#define USB_OTG_PKTSTS_Pos                       (17U)                         
+#define USB_OTG_PKTSTS_Msk                       (0xFUL << USB_OTG_PKTSTS_Pos)  /*!< 0x001E0000 */
+#define USB_OTG_PKTSTS                           USB_OTG_PKTSTS_Msk            /*!< Packet status */
+#define USB_OTG_PKTSTS_0                         (0x1UL << USB_OTG_PKTSTS_Pos)  /*!< 0x00020000 */
+#define USB_OTG_PKTSTS_1                         (0x2UL << USB_OTG_PKTSTS_Pos)  /*!< 0x00040000 */
+#define USB_OTG_PKTSTS_2                         (0x4UL << USB_OTG_PKTSTS_Pos)  /*!< 0x00080000 */
+#define USB_OTG_PKTSTS_3                         (0x8UL << USB_OTG_PKTSTS_Pos)  /*!< 0x00100000 */
+
+#define USB_OTG_EPNUM_Pos                        (0U)                          
+#define USB_OTG_EPNUM_Msk                        (0xFUL << USB_OTG_EPNUM_Pos)   /*!< 0x0000000F */
+#define USB_OTG_EPNUM                            USB_OTG_EPNUM_Msk             /*!< Endpoint number */
+#define USB_OTG_EPNUM_0                          (0x1UL << USB_OTG_EPNUM_Pos)   /*!< 0x00000001 */
+#define USB_OTG_EPNUM_1                          (0x2UL << USB_OTG_EPNUM_Pos)   /*!< 0x00000002 */
+#define USB_OTG_EPNUM_2                          (0x4UL << USB_OTG_EPNUM_Pos)   /*!< 0x00000004 */
+#define USB_OTG_EPNUM_3                          (0x8UL << USB_OTG_EPNUM_Pos)   /*!< 0x00000008 */
+
+#define USB_OTG_FRMNUM_Pos                       (21U)                         
+#define USB_OTG_FRMNUM_Msk                       (0xFUL << USB_OTG_FRMNUM_Pos)  /*!< 0x01E00000 */
+#define USB_OTG_FRMNUM                           USB_OTG_FRMNUM_Msk            /*!< Frame number */
+#define USB_OTG_FRMNUM_0                         (0x1UL << USB_OTG_FRMNUM_Pos)  /*!< 0x00200000 */
+#define USB_OTG_FRMNUM_1                         (0x2UL << USB_OTG_FRMNUM_Pos)  /*!< 0x00400000 */
+#define USB_OTG_FRMNUM_2                         (0x4UL << USB_OTG_FRMNUM_Pos)  /*!< 0x00800000 */
+#define USB_OTG_FRMNUM_3                         (0x8UL << USB_OTG_FRMNUM_Pos)  /*!< 0x01000000 */
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */
+
+/** @addtogroup Exported_macros
+  * @{
+  */
+
+/******************************* ADC Instances ********************************/
+#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
+                                       ((INSTANCE) == ADC2) || \
+                                       ((INSTANCE) == ADC3))
+
+#define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
+
+#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC123_COMMON)
+
+/******************************* CAN Instances ********************************/
+#define IS_CAN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CAN1) || \
+                                       ((INSTANCE) == CAN2))
+/******************************* CRC Instances ********************************/
+#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
+
+/******************************* DAC Instances ********************************/
+#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC1)
+
+/******************************* DCMI Instances *******************************/
+#define IS_DCMI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DCMI)
+
+/******************************* DMA2D Instances *******************************/
+#define IS_DMA2D_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DMA2D)
+
+/******************************** DMA Instances *******************************/
+#define IS_DMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
+                                              ((INSTANCE) == DMA1_Stream1) || \
+                                              ((INSTANCE) == DMA1_Stream2) || \
+                                              ((INSTANCE) == DMA1_Stream3) || \
+                                              ((INSTANCE) == DMA1_Stream4) || \
+                                              ((INSTANCE) == DMA1_Stream5) || \
+                                              ((INSTANCE) == DMA1_Stream6) || \
+                                              ((INSTANCE) == DMA1_Stream7) || \
+                                              ((INSTANCE) == DMA2_Stream0) || \
+                                              ((INSTANCE) == DMA2_Stream1) || \
+                                              ((INSTANCE) == DMA2_Stream2) || \
+                                              ((INSTANCE) == DMA2_Stream3) || \
+                                              ((INSTANCE) == DMA2_Stream4) || \
+                                              ((INSTANCE) == DMA2_Stream5) || \
+                                              ((INSTANCE) == DMA2_Stream6) || \
+                                              ((INSTANCE) == DMA2_Stream7))
+
+/******************************* GPIO Instances *******************************/
+#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
+                                        ((INSTANCE) == GPIOB) || \
+                                        ((INSTANCE) == GPIOC) || \
+                                        ((INSTANCE) == GPIOD) || \
+                                        ((INSTANCE) == GPIOE) || \
+                                        ((INSTANCE) == GPIOF) || \
+                                        ((INSTANCE) == GPIOG) || \
+                                        ((INSTANCE) == GPIOH) || \
+                                        ((INSTANCE) == GPIOI) || \
+                                        ((INSTANCE) == GPIOJ) || \
+                                        ((INSTANCE) == GPIOK))
+
+/******************************** I2C Instances *******************************/
+#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
+                                       ((INSTANCE) == I2C2) || \
+                                       ((INSTANCE) == I2C3))
+
+/******************************* SMBUS Instances ******************************/
+#define IS_SMBUS_ALL_INSTANCE         IS_I2C_ALL_INSTANCE
+
+/******************************** I2S Instances *******************************/
+
+#define IS_I2S_ALL_INSTANCE(INSTANCE)  (((INSTANCE) == SPI2) || \
+                                       ((INSTANCE) == SPI3))
+
+/*************************** I2S Extended Instances ***************************/
+#define IS_I2S_EXT_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2S2ext)|| \
+                                           ((INSTANCE) == I2S3ext))
+/* Legacy Defines */
+#define IS_I2S_ALL_INSTANCE_EXT    IS_I2S_EXT_ALL_INSTANCE
+
+/****************************** LTDC Instances ********************************/
+#define IS_LTDC_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == LTDC)
+/******************************* RNG Instances ********************************/
+#define IS_RNG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RNG)
+
+/****************************** RTC Instances *********************************/
+#define IS_RTC_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RTC)
+
+/******************************* SAI Instances ********************************/
+#define IS_SAI_ALL_INSTANCE(PERIPH) (((PERIPH) == SAI1_Block_A) || \
+                                     ((PERIPH) == SAI1_Block_B))
+/* Legacy define */
+
+#define IS_SAI_BLOCK_PERIPH IS_SAI_ALL_INSTANCE
+
+/******************************** SPI Instances *******************************/
+#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1)  || \
+                                       ((INSTANCE) == SPI2)  || \
+                                       ((INSTANCE) == SPI3)  || \
+                                       ((INSTANCE) == SPI4)  || \
+                                       ((INSTANCE) == SPI5)  || \
+                                       ((INSTANCE) == SPI6))
+
+
+/****************** TIM Instances : All supported instances *******************/
+#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)  || \
+                                    ((INSTANCE) == TIM2) || \
+                                    ((INSTANCE) == TIM3) || \
+                                    ((INSTANCE) == TIM4) || \
+                                    ((INSTANCE) == TIM5) || \
+                                    ((INSTANCE) == TIM6) || \
+                                    ((INSTANCE) == TIM7) || \
+                                    ((INSTANCE) == TIM8) || \
+                                    ((INSTANCE) == TIM9) || \
+                                    ((INSTANCE) == TIM10)|| \
+                                    ((INSTANCE) == TIM11)|| \
+                                    ((INSTANCE) == TIM12)|| \
+                                    ((INSTANCE) == TIM13)|| \
+                                    ((INSTANCE) == TIM14))
+
+/************* TIM Instances : at least 1 capture/compare channel *************/
+#define IS_TIM_CC1_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)  || \
+                                         ((INSTANCE) == TIM2)  || \
+                                         ((INSTANCE) == TIM3)  || \
+                                         ((INSTANCE) == TIM4)  || \
+                                         ((INSTANCE) == TIM5)  || \
+                                         ((INSTANCE) == TIM8)  || \
+                                         ((INSTANCE) == TIM9)  || \
+                                         ((INSTANCE) == TIM10) || \
+                                         ((INSTANCE) == TIM11) || \
+                                         ((INSTANCE) == TIM12) || \
+                                         ((INSTANCE) == TIM13) || \
+                                         ((INSTANCE) == TIM14))
+
+/************ TIM Instances : at least 2 capture/compare channels *************/
+#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+                                       ((INSTANCE) == TIM2) || \
+                                       ((INSTANCE) == TIM3) || \
+                                       ((INSTANCE) == TIM4) || \
+                                       ((INSTANCE) == TIM5) || \
+                                       ((INSTANCE) == TIM8) || \
+                                       ((INSTANCE) == TIM9) || \
+                                       ((INSTANCE) == TIM12)) 
+
+/************ TIM Instances : at least 3 capture/compare channels *************/
+#define IS_TIM_CC3_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1) || \
+                                         ((INSTANCE) == TIM2) || \
+                                         ((INSTANCE) == TIM3) || \
+                                         ((INSTANCE) == TIM4) || \
+                                         ((INSTANCE) == TIM5) || \
+                                         ((INSTANCE) == TIM8))
+
+/************ TIM Instances : at least 4 capture/compare channels *************/
+#define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+                                       ((INSTANCE) == TIM2) || \
+                                       ((INSTANCE) == TIM3) || \
+                                       ((INSTANCE) == TIM4) || \
+                                       ((INSTANCE) == TIM5) || \
+                                       ((INSTANCE) == TIM8))
+
+/******************** TIM Instances : Advanced-control timers *****************/
+#define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+                                           ((INSTANCE) == TIM8))
+
+/******************* TIM Instances : Timer input XOR function *****************/
+#define IS_TIM_XOR_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1) || \
+                                         ((INSTANCE) == TIM2) || \
+                                         ((INSTANCE) == TIM3) || \
+                                         ((INSTANCE) == TIM4) || \
+                                         ((INSTANCE) == TIM5) || \
+                                         ((INSTANCE) == TIM8))
+
+/****************** TIM Instances : DMA requests generation (UDE) *************/
+#define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+                                       ((INSTANCE) == TIM2) || \
+                                       ((INSTANCE) == TIM3) || \
+                                       ((INSTANCE) == TIM4) || \
+                                       ((INSTANCE) == TIM5) || \
+                                       ((INSTANCE) == TIM6) || \
+                                       ((INSTANCE) == TIM7) || \
+                                       ((INSTANCE) == TIM8))
+
+/************ TIM Instances : DMA requests generation (CCxDE) *****************/
+#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+                                          ((INSTANCE) == TIM2) || \
+                                          ((INSTANCE) == TIM3) || \
+                                          ((INSTANCE) == TIM4) || \
+                                          ((INSTANCE) == TIM5) || \
+                                          ((INSTANCE) == TIM8))
+
+/************ TIM Instances : DMA requests generation (COMDE) *****************/
+#define IS_TIM_CCDMA_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \
+                                          ((INSTANCE) == TIM2) || \
+                                          ((INSTANCE) == TIM3) || \
+                                          ((INSTANCE) == TIM4) || \
+                                          ((INSTANCE) == TIM5) || \
+                                          ((INSTANCE) == TIM8))
+
+/******************** TIM Instances : DMA burst feature ***********************/
+#define IS_TIM_DMABURST_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \
+                                             ((INSTANCE) == TIM2) || \
+                                             ((INSTANCE) == TIM3) || \
+                                             ((INSTANCE) == TIM4) || \
+                                             ((INSTANCE) == TIM5) || \
+                                             ((INSTANCE) == TIM8))
+
+/****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
+#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)  || \
+                                          ((INSTANCE) == TIM2)  || \
+                                          ((INSTANCE) == TIM3)  || \
+                                          ((INSTANCE) == TIM4)  || \
+                                          ((INSTANCE) == TIM5)  || \
+                                          ((INSTANCE) == TIM6)  || \
+                                          ((INSTANCE) == TIM7)  || \
+                                          ((INSTANCE) == TIM8))
+
+/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
+#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+                                         ((INSTANCE) == TIM2) || \
+                                         ((INSTANCE) == TIM3) || \
+                                         ((INSTANCE) == TIM4) || \
+                                         ((INSTANCE) == TIM5) || \
+                                         ((INSTANCE) == TIM8) || \
+                                         ((INSTANCE) == TIM9) || \
+                                         ((INSTANCE) == TIM12))
+/********************** TIM Instances : 32 bit Counter ************************/
+#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(((INSTANCE) == TIM2) || \
+                                              ((INSTANCE) == TIM5))
+
+/***************** TIM Instances : external trigger input available ************/
+#define IS_TIM_ETR_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \
+                                        ((INSTANCE) == TIM2) || \
+                                        ((INSTANCE) == TIM3) || \
+                                        ((INSTANCE) == TIM4) || \
+                                        ((INSTANCE) == TIM5) || \
+                                        ((INSTANCE) == TIM8))
+
+/****************** TIM Instances : remapping capability **********************/
+#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
+                                         ((INSTANCE) == TIM5)  || \
+                                         ((INSTANCE) == TIM11))
+
+/******************* TIM Instances : output(s) available **********************/
+#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
+    ((((INSTANCE) == TIM1) &&                  \
+     (((CHANNEL) == TIM_CHANNEL_1) ||          \
+      ((CHANNEL) == TIM_CHANNEL_2) ||          \
+      ((CHANNEL) == TIM_CHANNEL_3) ||          \
+      ((CHANNEL) == TIM_CHANNEL_4)))           \
+    ||                                         \
+    (((INSTANCE) == TIM2) &&                   \
+     (((CHANNEL) == TIM_CHANNEL_1) ||          \
+      ((CHANNEL) == TIM_CHANNEL_2) ||          \
+      ((CHANNEL) == TIM_CHANNEL_3) ||          \
+      ((CHANNEL) == TIM_CHANNEL_4)))           \
+    ||                                         \
+    (((INSTANCE) == TIM3) &&                   \
+     (((CHANNEL) == TIM_CHANNEL_1) ||          \
+      ((CHANNEL) == TIM_CHANNEL_2) ||          \
+      ((CHANNEL) == TIM_CHANNEL_3) ||          \
+      ((CHANNEL) == TIM_CHANNEL_4)))           \
+    ||                                         \
+    (((INSTANCE) == TIM4) &&                   \
+     (((CHANNEL) == TIM_CHANNEL_1) ||          \
+      ((CHANNEL) == TIM_CHANNEL_2) ||          \
+      ((CHANNEL) == TIM_CHANNEL_3) ||          \
+      ((CHANNEL) == TIM_CHANNEL_4)))           \
+    ||                                         \
+    (((INSTANCE) == TIM5) &&                   \
+     (((CHANNEL) == TIM_CHANNEL_1) ||          \
+      ((CHANNEL) == TIM_CHANNEL_2) ||          \
+      ((CHANNEL) == TIM_CHANNEL_3) ||          \
+      ((CHANNEL) == TIM_CHANNEL_4)))           \
+    ||                                         \
+    (((INSTANCE) == TIM8) &&                   \
+     (((CHANNEL) == TIM_CHANNEL_1) ||          \
+      ((CHANNEL) == TIM_CHANNEL_2) ||          \
+      ((CHANNEL) == TIM_CHANNEL_3) ||          \
+      ((CHANNEL) == TIM_CHANNEL_4)))           \
+    ||                                         \
+    (((INSTANCE) == TIM9) &&                   \
+     (((CHANNEL) == TIM_CHANNEL_1) ||          \
+      ((CHANNEL) == TIM_CHANNEL_2)))           \
+    ||                                         \
+    (((INSTANCE) == TIM10) &&                  \
+     (((CHANNEL) == TIM_CHANNEL_1)))           \
+    ||                                         \
+    (((INSTANCE) == TIM11) &&                  \
+     (((CHANNEL) == TIM_CHANNEL_1)))           \
+    ||                                         \
+    (((INSTANCE) == TIM12) &&                  \
+     (((CHANNEL) == TIM_CHANNEL_1) ||          \
+      ((CHANNEL) == TIM_CHANNEL_2)))           \
+    ||                                         \
+    (((INSTANCE) == TIM13) &&                  \
+     (((CHANNEL) == TIM_CHANNEL_1)))           \
+    ||                                         \
+    (((INSTANCE) == TIM14) &&                  \
+     (((CHANNEL) == TIM_CHANNEL_1))))
+
+/************ TIM Instances : complementary output(s) available ***************/
+#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
+   ((((INSTANCE) == TIM1) &&                    \
+     (((CHANNEL) == TIM_CHANNEL_1) ||           \
+      ((CHANNEL) == TIM_CHANNEL_2) ||           \
+      ((CHANNEL) == TIM_CHANNEL_3)))            \
+    ||                                          \
+    (((INSTANCE) == TIM8) &&                    \
+     (((CHANNEL) == TIM_CHANNEL_1) ||           \
+      ((CHANNEL) == TIM_CHANNEL_2) ||           \
+      ((CHANNEL) == TIM_CHANNEL_3))))
+
+/****************** TIM Instances : supporting counting mode selection ********/
+#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \
+                                                        ((INSTANCE) == TIM2) || \
+                                                        ((INSTANCE) == TIM3) || \
+                                                        ((INSTANCE) == TIM4) || \
+                                                        ((INSTANCE) == TIM5) || \
+                                                        ((INSTANCE) == TIM8))
+
+/****************** TIM Instances : supporting clock division *****************/
+#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)  || \
+                                                  ((INSTANCE) == TIM2) || \
+                                                  ((INSTANCE) == TIM3) || \
+                                                  ((INSTANCE) == TIM4) || \
+                                                  ((INSTANCE) == TIM5) || \
+                                                  ((INSTANCE) == TIM8) || \
+                                                  ((INSTANCE) == TIM9) || \
+                                                  ((INSTANCE) == TIM10)|| \
+                                                  ((INSTANCE) == TIM11)|| \
+                                                  ((INSTANCE) == TIM12)|| \
+                                                  ((INSTANCE) == TIM13)|| \
+                                                  ((INSTANCE) == TIM14))
+
+/****************** TIM Instances : supporting commutation event generation ***/
+#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)|| \
+                                                     ((INSTANCE) == TIM8))
+
+
+/****************** TIM Instances : supporting OCxREF clear *******************/
+#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)        (((INSTANCE) == TIM1) || \
+                                                       ((INSTANCE) == TIM2) || \
+                                                       ((INSTANCE) == TIM3) || \
+                                                       ((INSTANCE) == TIM4) || \
+                                                       ((INSTANCE) == TIM5) || \
+                                                       ((INSTANCE) == TIM8))
+
+/****** TIM Instances : supporting external clock mode 1 for ETRF input *******/
+#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+                                                        ((INSTANCE) == TIM2) || \
+                                                        ((INSTANCE) == TIM3) || \
+                                                        ((INSTANCE) == TIM4) || \
+                                                        ((INSTANCE) == TIM5) || \
+                                                        ((INSTANCE) == TIM8) || \
+                                                        ((INSTANCE) == TIM9) || \
+                                                        ((INSTANCE) == TIM12))
+
+/****** TIM Instances : supporting external clock mode 2 for ETRF input *******/
+#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+                                                        ((INSTANCE) == TIM2) || \
+                                                        ((INSTANCE) == TIM3) || \
+                                                        ((INSTANCE) == TIM4) || \
+                                                        ((INSTANCE) == TIM5) || \
+                                                        ((INSTANCE) == TIM8))
+
+/****** TIM Instances : supporting external clock mode 1 for TIX inputs ******/
+#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)      (((INSTANCE) == TIM1) || \
+                                                        ((INSTANCE) == TIM2) || \
+                                                        ((INSTANCE) == TIM3) || \
+                                                        ((INSTANCE) == TIM4) || \
+                                                        ((INSTANCE) == TIM5) || \
+                                                        ((INSTANCE) == TIM8) || \
+                                                        ((INSTANCE) == TIM9) || \
+                                                        ((INSTANCE) == TIM12))
+
+/********** TIM Instances : supporting internal trigger inputs(ITRX) *********/
+#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)     (((INSTANCE) == TIM1) || \
+                                                        ((INSTANCE) == TIM2) || \
+                                                        ((INSTANCE) == TIM3) || \
+                                                        ((INSTANCE) == TIM4) || \
+                                                        ((INSTANCE) == TIM5) || \
+                                                        ((INSTANCE) == TIM8) || \
+                                                        ((INSTANCE) == TIM9) || \
+                                                        ((INSTANCE) == TIM12))
+
+/****************** TIM Instances : supporting repetition counter *************/
+#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \
+                                                       ((INSTANCE) == TIM8))
+
+/****************** TIM Instances : supporting encoder interface **************/
+#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \
+                                                      ((INSTANCE) == TIM2) || \
+                                                      ((INSTANCE) == TIM3) || \
+                                                      ((INSTANCE) == TIM4) || \
+                                                      ((INSTANCE) == TIM5) || \
+                                                      ((INSTANCE) == TIM8) || \
+                                                      ((INSTANCE) == TIM9) || \
+                                                      ((INSTANCE) == TIM12))
+/****************** TIM Instances : supporting Hall sensor interface **********/
+#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \
+                                                          ((INSTANCE) == TIM2) || \
+                                                          ((INSTANCE) == TIM3) || \
+                                                          ((INSTANCE) == TIM4) || \
+                                                          ((INSTANCE) == TIM5) || \
+                                                          ((INSTANCE) == TIM8))
+/****************** TIM Instances : supporting the break function *************/
+#define IS_TIM_BREAK_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \
+                                          ((INSTANCE) == TIM8))
+
+/******************** USART Instances : Synchronous mode **********************/
+#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+                                     ((INSTANCE) == USART2) || \
+                                     ((INSTANCE) == USART3) || \
+                                     ((INSTANCE) == USART6))
+
+/******************** UART Instances : Half-Duplex mode **********************/
+#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+                                               ((INSTANCE) == USART2) || \
+                                               ((INSTANCE) == USART3) || \
+                                               ((INSTANCE) == UART4)  || \
+                                               ((INSTANCE) == UART5)  || \
+                                               ((INSTANCE) == USART6) || \
+                                               ((INSTANCE) == UART7)  || \
+                                               ((INSTANCE) == UART8))
+
+/* Legacy defines */
+#define IS_UART_INSTANCE          IS_UART_HALFDUPLEX_INSTANCE
+
+/****************** UART Instances : Hardware Flow control ********************/
+#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+                                           ((INSTANCE) == USART2) || \
+                                           ((INSTANCE) == USART3) || \
+                                           ((INSTANCE) == USART6))
+/******************** UART Instances : LIN mode **********************/
+#define IS_UART_LIN_INSTANCE          IS_UART_HALFDUPLEX_INSTANCE
+
+/********************* UART Instances : Smart card mode ***********************/
+#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+                                         ((INSTANCE) == USART2) || \
+                                         ((INSTANCE) == USART3) || \
+                                         ((INSTANCE) == USART6))
+
+/*********************** UART Instances : IRDA mode ***************************/
+#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+                                    ((INSTANCE) == USART2) || \
+                                    ((INSTANCE) == USART3) || \
+                                    ((INSTANCE) == UART4)  || \
+                                    ((INSTANCE) == UART5)  || \
+                                    ((INSTANCE) == USART6) || \
+                                    ((INSTANCE) == UART7)  || \
+                                    ((INSTANCE) == UART8))                                     
+
+/*********************** PCD Instances ****************************************/
+#define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
+                                       ((INSTANCE) == USB_OTG_HS))
+
+/*********************** HCD Instances ****************************************/
+#define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
+                                       ((INSTANCE) == USB_OTG_HS))
+
+/****************************** SDIO Instances ********************************/
+#define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO)
+
+/****************************** IWDG Instances ********************************/
+#define IS_IWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == IWDG)
+
+/****************************** WWDG Instances ********************************/
+#define IS_WWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == WWDG)
+
+
+/****************************** QSPI Instances ********************************/
+#define IS_QSPI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == QUADSPI)
+/****************************** USB Exported Constants ************************/
+#define USB_OTG_FS_HOST_MAX_CHANNEL_NBR                12U
+#define USB_OTG_FS_MAX_IN_ENDPOINTS                    6U    /* Including EP0 */
+#define USB_OTG_FS_MAX_OUT_ENDPOINTS                   6U    /* Including EP0 */
+#define USB_OTG_FS_TOTAL_FIFO_SIZE                     1280U /* in Bytes */
+#define USB_OTG_HS_HOST_MAX_CHANNEL_NBR                16U
+#define USB_OTG_HS_MAX_IN_ENDPOINTS                    9U    /* Including EP0 */
+#define USB_OTG_HS_MAX_OUT_ENDPOINTS                   9U    /* Including EP0 */
+#define USB_OTG_HS_TOTAL_FIFO_SIZE                     4096U /* in Bytes */
+
+/*
+ * @brief Specific devices reset values definitions
+ */
+#define RCC_PLLCFGR_RST_VALUE              0x24003010U
+#define RCC_PLLI2SCFGR_RST_VALUE           0x24003000U
+#define RCC_PLLSAICFGR_RST_VALUE           0x24003000U
+
+#define RCC_MAX_FREQUENCY           180000000U         /*!< Max frequency of family in Hz*/
+#define RCC_MAX_FREQUENCY_SCALE1    RCC_MAX_FREQUENCY  /*!< Maximum frequency for system clock at power scale1, in Hz */
+#define RCC_MAX_FREQUENCY_SCALE2    168000000U         /*!< Maximum frequency for system clock at power scale2, in Hz */
+#define RCC_MAX_FREQUENCY_SCALE3    120000000U         /*!< Maximum frequency for system clock at power scale3, in Hz */
+#define RCC_PLLVCO_OUTPUT_MIN       192000000U       /*!< Frequency min for PLLVCO output, in Hz */
+#define RCC_PLLVCO_INPUT_MIN           950000U       /*!< Frequency min for PLLVCO input, in Hz  */
+#define RCC_PLLVCO_INPUT_MAX          2100000U       /*!< Frequency max for PLLVCO input, in Hz  */
+#define RCC_PLLVCO_OUTPUT_MAX       432000000U       /*!< Frequency max for PLLVCO output, in Hz */
+
+#define RCC_PLLN_MIN_VALUE                 50U
+#define RCC_PLLN_MAX_VALUE                432U
+
+#define FLASH_SCALE1_LATENCY1_FREQ   30000000U      /*!< HCLK frequency to set FLASH latency 1 in power scale 1  */
+#define FLASH_SCALE1_LATENCY2_FREQ   60000000U      /*!< HCLK frequency to set FLASH latency 2 in power scale 1  */
+#define FLASH_SCALE1_LATENCY3_FREQ   90000000U      /*!< HCLK frequency to set FLASH latency 3 in power scale 1  */
+#define FLASH_SCALE1_LATENCY4_FREQ   120000000U     /*!< HCLK frequency to set FLASH latency 4 in power scale 1  */
+#define FLASH_SCALE1_LATENCY5_FREQ   150000000U     /*!< HCLK frequency to set FLASH latency 5 in power scale 1  */
+
+#define FLASH_SCALE2_LATENCY1_FREQ   30000000U      /*!< HCLK frequency to set FLASH latency 1 in power scale 2  */
+#define FLASH_SCALE2_LATENCY2_FREQ   60000000U      /*!< HCLK frequency to set FLASH latency 2 in power scale 2  */
+#define FLASH_SCALE2_LATENCY3_FREQ   90000000U      /*!< HCLK frequency to set FLASH latency 3 in power scale 2  */
+#define FLASH_SCALE2_LATENCY4_FREQ   12000000U      /*!< HCLK frequency to set FLASH latency 4 in power scale 2  */
+#define FLASH_SCALE2_LATENCY5_FREQ   150000000U     /*!< HCLK frequency to set FLASH latency 5 in power scale 2  */
+
+#define FLASH_SCALE3_LATENCY1_FREQ   30000000U      /*!< HCLK frequency to set FLASH latency 1 in power scale 3  */
+#define FLASH_SCALE3_LATENCY2_FREQ   60000000U      /*!< HCLK frequency to set FLASH latency 2 in power scale 3  */
+#define FLASH_SCALE3_LATENCY3_FREQ   90000000U      /*!< HCLK frequency to set FLASH latency 3 in power scale 3  */
+
+/******************************************************************************/
+/*  For a painless codes migration between the STM32F4xx device product       */
+/*  lines, the aliases defined below are put in place to overcome the         */
+/*  differences in the interrupt handlers and IRQn definitions.               */
+/*  No need to update developed interrupt code when moving across             */
+/*  product lines within the same STM32F4 Family                              */
+/******************************************************************************/
+/* Aliases for __IRQn */
+#define FSMC_IRQn              FMC_IRQn
+
+/* Aliases for __IRQHandler */
+#define FSMC_IRQHandler        FMC_IRQHandler
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __STM32F469xx_H */
diff --git a/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h b/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h
new file mode 100644
index 0000000..92fe3a7
--- /dev/null
+++ b/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h
@@ -0,0 +1,301 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx.h
+  * @author  MCD Application Team
+  * @brief   CMSIS STM32F4xx Device Peripheral Access Layer Header File.
+  *            
+  *          The file is the unique include file that the application programmer
+  *          is using in the C source code, usually in main.c. This file contains:
+  *           - Configuration section that allows to select:
+  *              - The STM32F4xx device used in the target application
+  *              - To use or not the peripheral's drivers in application code(i.e. 
+  *                code will be based on direct access to peripheral's registers 
+  *                rather than drivers API), this option is controlled by 
+  *                "#define USE_HAL_DRIVER"
+  *  
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32f4xx
+  * @{
+  */
+    
+#ifndef __STM32F4xx_H
+#define __STM32F4xx_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif /* __cplusplus */
+   
+/** @addtogroup Library_configuration_section
+  * @{
+  */
+  
+/**
+  * @brief STM32 Family
+  */
+#if !defined  (STM32F4)
+#define STM32F4
+#endif /* STM32F4 */
+
+/* Uncomment the line below according to the target STM32 device used in your
+   application 
+  */
+#if !defined (STM32F405xx) && !defined (STM32F415xx) && !defined (STM32F407xx) && !defined (STM32F417xx) && \
+    !defined (STM32F427xx) && !defined (STM32F437xx) && !defined (STM32F429xx) && !defined (STM32F439xx) && \
+    !defined (STM32F401xC) && !defined (STM32F401xE) && !defined (STM32F410Tx) && !defined (STM32F410Cx) && \
+    !defined (STM32F410Rx) && !defined (STM32F411xE) && !defined (STM32F446xx) && !defined (STM32F469xx) && \
+    !defined (STM32F479xx) && !defined (STM32F412Cx) && !defined (STM32F412Rx) && !defined (STM32F412Vx) && \
+    !defined (STM32F412Zx) && !defined (STM32F413xx) && !defined (STM32F423xx)
+  /* #define STM32F405xx */   /*!< STM32F405RG, STM32F405VG and STM32F405ZG Devices */
+  /* #define STM32F415xx */   /*!< STM32F415RG, STM32F415VG and STM32F415ZG Devices */
+  /* #define STM32F407xx */   /*!< STM32F407VG, STM32F407VE, STM32F407ZG, STM32F407ZE, STM32F407IG  and STM32F407IE Devices */
+  /* #define STM32F417xx */   /*!< STM32F417VG, STM32F417VE, STM32F417ZG, STM32F417ZE, STM32F417IG and STM32F417IE Devices */
+  /* #define STM32F427xx */   /*!< STM32F427VG, STM32F427VI, STM32F427ZG, STM32F427ZI, STM32F427IG and STM32F427II Devices */
+  /* #define STM32F437xx */   /*!< STM32F437VG, STM32F437VI, STM32F437ZG, STM32F437ZI, STM32F437IG and STM32F437II Devices */
+  /* #define STM32F429xx */   /*!< STM32F429VG, STM32F429VI, STM32F429ZG, STM32F429ZI, STM32F429BG, STM32F429BI, STM32F429NG, 
+                                   STM32F439NI, STM32F429IG  and STM32F429II Devices */
+  /* #define STM32F439xx */   /*!< STM32F439VG, STM32F439VI, STM32F439ZG, STM32F439ZI, STM32F439BG, STM32F439BI, STM32F439NG, 
+                                   STM32F439NI, STM32F439IG and STM32F439II Devices */
+  /* #define STM32F401xC */   /*!< STM32F401CB, STM32F401CC, STM32F401RB, STM32F401RC, STM32F401VB and STM32F401VC Devices */
+  /* #define STM32F401xE */   /*!< STM32F401CD, STM32F401RD, STM32F401VD, STM32F401CE, STM32F401RE and STM32F401VE Devices */
+  /* #define STM32F410Tx */   /*!< STM32F410T8 and STM32F410TB Devices */
+  /* #define STM32F410Cx */   /*!< STM32F410C8 and STM32F410CB Devices */
+  /* #define STM32F410Rx */   /*!< STM32F410R8 and STM32F410RB Devices */
+  /* #define STM32F411xE */   /*!< STM32F411CC, STM32F411RC, STM32F411VC, STM32F411CE, STM32F411RE and STM32F411VE Devices */
+  /* #define STM32F446xx */   /*!< STM32F446MC, STM32F446ME, STM32F446RC, STM32F446RE, STM32F446VC, STM32F446VE, STM32F446ZC, 
+                                   and STM32F446ZE Devices */
+  /* #define STM32F469xx */   /*!< STM32F469AI, STM32F469II, STM32F469BI, STM32F469NI, STM32F469AG, STM32F469IG, STM32F469BG, 
+                                   STM32F469NG, STM32F469AE, STM32F469IE, STM32F469BE and STM32F469NE Devices */
+  /* #define STM32F479xx */   /*!< STM32F479AI, STM32F479II, STM32F479BI, STM32F479NI, STM32F479AG, STM32F479IG, STM32F479BG 
+                                   and STM32F479NG Devices */
+  /* #define STM32F412Cx */   /*!< STM32F412CEU and STM32F412CGU Devices */
+  /* #define STM32F412Zx */   /*!< STM32F412ZET, STM32F412ZGT, STM32F412ZEJ and STM32F412ZGJ Devices */
+  /* #define STM32F412Vx */   /*!< STM32F412VET, STM32F412VGT, STM32F412VEH and STM32F412VGH Devices */
+  /* #define STM32F412Rx */   /*!< STM32F412RET, STM32F412RGT, STM32F412REY and STM32F412RGY Devices */
+  /* #define STM32F413xx */   /*!< STM32F413CH, STM32F413MH, STM32F413RH, STM32F413VH, STM32F413ZH, STM32F413CG, STM32F413MG,
+                                   STM32F413RG, STM32F413VG and STM32F413ZG Devices */
+  /* #define STM32F423xx */   /*!< STM32F423CH, STM32F423RH, STM32F423VH and STM32F423ZH Devices */
+#endif
+   
+/*  Tip: To avoid modifying this file each time you need to switch between these
+        devices, you can define the device in your toolchain compiler preprocessor.
+  */
+#if !defined  (USE_HAL_DRIVER)
+/**
+ * @brief Comment the line below if you will not use the peripherals drivers.
+   In this case, these drivers will not be included and the application code will 
+   be based on direct access to peripherals registers 
+   */
+  /*#define USE_HAL_DRIVER */
+#endif /* USE_HAL_DRIVER */
+
+/**
+  * @brief CMSIS version number V2.6.8
+  */
+#define __STM32F4xx_CMSIS_VERSION_MAIN   (0x02U) /*!< [31:24] main version */
+#define __STM32F4xx_CMSIS_VERSION_SUB1   (0x06U) /*!< [23:16] sub1 version */
+#define __STM32F4xx_CMSIS_VERSION_SUB2   (0x08U) /*!< [15:8]  sub2 version */
+#define __STM32F4xx_CMSIS_VERSION_RC     (0x00U) /*!< [7:0]  release candidate */
+#define __STM32F4xx_CMSIS_VERSION        ((__STM32F4xx_CMSIS_VERSION_MAIN << 24)\
+                                         |(__STM32F4xx_CMSIS_VERSION_SUB1 << 16)\
+                                         |(__STM32F4xx_CMSIS_VERSION_SUB2 << 8 )\
+                                         |(__STM32F4xx_CMSIS_VERSION_RC))
+
+/**
+  * @}
+  */
+
+/** @addtogroup Device_Included
+  * @{
+  */
+
+#if defined(STM32F405xx)
+  #include "stm32f405xx.h"
+#elif defined(STM32F415xx)
+  #include "stm32f415xx.h"
+#elif defined(STM32F407xx)
+  #include "stm32f407xx.h"
+#elif defined(STM32F417xx)
+  #include "stm32f417xx.h"
+#elif defined(STM32F427xx)
+  #include "stm32f427xx.h"
+#elif defined(STM32F437xx)
+  #include "stm32f437xx.h"
+#elif defined(STM32F429xx)
+  #include "stm32f429xx.h"
+#elif defined(STM32F439xx)
+  #include "stm32f439xx.h"
+#elif defined(STM32F401xC)
+  #include "stm32f401xc.h"
+#elif defined(STM32F401xE)
+  #include "stm32f401xe.h"
+#elif defined(STM32F410Tx)
+  #include "stm32f410tx.h"
+#elif defined(STM32F410Cx)
+  #include "stm32f410cx.h"
+#elif defined(STM32F410Rx)
+  #include "stm32f410rx.h"
+#elif defined(STM32F411xE)
+  #include "stm32f411xe.h"
+#elif defined(STM32F446xx)
+  #include "stm32f446xx.h"
+#elif defined(STM32F469xx)
+  #include "stm32f469xx.h"
+#elif defined(STM32F479xx)
+  #include "stm32f479xx.h"
+#elif defined(STM32F412Cx)
+  #include "stm32f412cx.h"
+#elif defined(STM32F412Zx)
+  #include "stm32f412zx.h"
+#elif defined(STM32F412Rx)
+  #include "stm32f412rx.h"
+#elif defined(STM32F412Vx)
+  #include "stm32f412vx.h"
+#elif defined(STM32F413xx)
+  #include "stm32f413xx.h"
+#elif defined(STM32F423xx)
+  #include "stm32f423xx.h"
+#else
+ #error "Please select first the target STM32F4xx device used in your application (in stm32f4xx.h file)"
+#endif
+
+/**
+  * @}
+  */
+
+/** @addtogroup Exported_types
+  * @{
+  */ 
+typedef enum 
+{
+  RESET = 0U, 
+  SET = !RESET
+} FlagStatus, ITStatus;
+
+typedef enum 
+{
+  DISABLE = 0U, 
+  ENABLE = !DISABLE
+} FunctionalState;
+#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
+
+typedef enum
+{
+  SUCCESS = 0U,
+  ERROR = !SUCCESS
+} ErrorStatus;
+
+/**
+  * @}
+  */
+
+
+/** @addtogroup Exported_macro
+  * @{
+  */
+#define SET_BIT(REG, BIT)     ((REG) |= (BIT))
+
+#define CLEAR_BIT(REG, BIT)   ((REG) &= ~(BIT))
+
+#define READ_BIT(REG, BIT)    ((REG) & (BIT))
+
+#define CLEAR_REG(REG)        ((REG) = (0x0))
+
+#define WRITE_REG(REG, VAL)   ((REG) = (VAL))
+
+#define READ_REG(REG)         ((REG))
+
+#define MODIFY_REG(REG, CLEARMASK, SETMASK)  WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
+
+#define POSITION_VAL(VAL)     (__CLZ(__RBIT(VAL))) 
+
+/* Use of CMSIS compiler intrinsics for register exclusive access */
+/* Atomic 32-bit register access macro to set one or several bits */
+#define ATOMIC_SET_BIT(REG, BIT)                             \
+  do {                                                       \
+    uint32_t val;                                            \
+    do {                                                     \
+      val = __LDREXW((__IO uint32_t *)&(REG)) | (BIT);       \
+    } while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); \
+  } while(0)
+
+/* Atomic 32-bit register access macro to clear one or several bits */
+#define ATOMIC_CLEAR_BIT(REG, BIT)                           \
+  do {                                                       \
+    uint32_t val;                                            \
+    do {                                                     \
+      val = __LDREXW((__IO uint32_t *)&(REG)) & ~(BIT);      \
+    } while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); \
+  } while(0)
+
+/* Atomic 32-bit register access macro to clear and set one or several bits */
+#define ATOMIC_MODIFY_REG(REG, CLEARMSK, SETMASK)                          \
+  do {                                                                     \
+    uint32_t val;                                                          \
+    do {                                                                   \
+      val = (__LDREXW((__IO uint32_t *)&(REG)) & ~(CLEARMSK)) | (SETMASK); \
+    } while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U);               \
+  } while(0)
+
+/* Atomic 16-bit register access macro to set one or several bits */
+#define ATOMIC_SETH_BIT(REG, BIT)                            \
+  do {                                                       \
+    uint16_t val;                                            \
+    do {                                                     \
+      val = __LDREXH((__IO uint16_t *)&(REG)) | (BIT);       \
+    } while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); \
+  } while(0)
+
+/* Atomic 16-bit register access macro to clear one or several bits */
+#define ATOMIC_CLEARH_BIT(REG, BIT)                          \
+  do {                                                       \
+    uint16_t val;                                            \
+    do {                                                     \
+      val = __LDREXH((__IO uint16_t *)&(REG)) & ~(BIT);      \
+    } while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); \
+  } while(0)
+
+/* Atomic 16-bit register access macro to clear and set one or several bits */
+#define ATOMIC_MODIFYH_REG(REG, CLEARMSK, SETMASK)                         \
+  do {                                                                     \
+    uint16_t val;                                                          \
+    do {                                                                   \
+      val = (__LDREXH((__IO uint16_t *)&(REG)) & ~(CLEARMSK)) | (SETMASK); \
+    } while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U);               \
+  } while(0)
+
+/**
+  * @}
+  */
+
+#if defined (USE_HAL_DRIVER)
+ #include "stm32f4xx_hal.h"
+#endif /* USE_HAL_DRIVER */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __STM32F4xx_H */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
diff --git a/Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h b/Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h
new file mode 100644
index 0000000..d92c6f1
--- /dev/null
+++ b/Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h
@@ -0,0 +1,104 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32f4xx.h
+  * @author  MCD Application Team
+  * @brief   CMSIS Cortex-M4 Device System Source File for STM32F4xx devices.       
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************  
+  */ 
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32f4xx_system
+  * @{
+  */  
+  
+/**
+  * @brief Define to prevent recursive inclusion
+  */
+#ifndef __SYSTEM_STM32F4XX_H
+#define __SYSTEM_STM32F4XX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+
+/** @addtogroup STM32F4xx_System_Includes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+
+/** @addtogroup STM32F4xx_System_Exported_types
+  * @{
+  */
+  /* This variable is updated in three ways:
+      1) by calling CMSIS function SystemCoreClockUpdate()
+      2) by calling HAL API function HAL_RCC_GetSysClockFreq()
+      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency 
+         Note: If you use this function to configure the system clock; then there
+               is no need to call the 2 first functions listed above, since SystemCoreClock
+               variable is updated automatically.
+  */
+extern uint32_t SystemCoreClock;          /*!< System Clock Frequency (Core Clock) */
+
+extern const uint8_t  AHBPrescTable[16];    /*!< AHB prescalers table values */
+extern const uint8_t  APBPrescTable[8];     /*!< APB prescalers table values */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F4xx_System_Exported_Constants
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F4xx_System_Exported_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F4xx_System_Exported_Functions
+  * @{
+  */
+  
+extern void SystemInit(void);
+extern void SystemCoreClockUpdate(void);
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__SYSTEM_STM32F4XX_H */
+
+/**
+  * @}
+  */
+  
+/**
+  * @}
+  */  
diff --git a/Drivers/CMSIS/Device/ST/STM32F4xx/LICENSE.txt b/Drivers/CMSIS/Device/ST/STM32F4xx/LICENSE.txt
new file mode 100644
index 0000000..5306686
--- /dev/null
+++ b/Drivers/CMSIS/Device/ST/STM32F4xx/LICENSE.txt
@@ -0,0 +1,6 @@
+This software component is provided to you as part of a software package and
+applicable license terms are in the  Package_license file. If you received this
+software component outside of a package or without applicable license terms,
+the terms of the Apache-2.0 license shall apply. 
+You may obtain a copy of the Apache-2.0 at:
+https://opensource.org/licenses/Apache-2.0
diff --git a/Drivers/CMSIS/Include/cmsis_armcc.h b/Drivers/CMSIS/Include/cmsis_armcc.h
new file mode 100644
index 0000000..7d751fb
--- /dev/null
+++ b/Drivers/CMSIS/Include/cmsis_armcc.h
@@ -0,0 +1,865 @@
+/**************************************************************************//**
+ * @file     cmsis_armcc.h
+ * @brief    CMSIS compiler ARMCC (Arm Compiler 5) header file
+ * @version  V5.0.4
+ * @date     10. January 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_ARMCC_H
+#define __CMSIS_ARMCC_H
+
+
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677)
+  #error "Please use Arm Compiler Toolchain V4.0.677 or later!"
+#endif
+
+/* CMSIS compiler control architecture macros */
+#if ((defined (__TARGET_ARCH_6_M  ) && (__TARGET_ARCH_6_M   == 1)) || \
+     (defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M  == 1))   )
+  #define __ARM_ARCH_6M__           1
+#endif
+
+#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M  == 1))
+  #define __ARM_ARCH_7M__           1
+#endif
+
+#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1))
+  #define __ARM_ARCH_7EM__          1
+#endif
+
+  /* __ARM_ARCH_8M_BASE__  not applicable */
+  /* __ARM_ARCH_8M_MAIN__  not applicable */
+
+
+/* CMSIS compiler specific defines */
+#ifndef   __ASM
+  #define __ASM                                  __asm
+#endif
+#ifndef   __INLINE
+  #define __INLINE                               __inline
+#endif
+#ifndef   __STATIC_INLINE
+  #define __STATIC_INLINE                        static __inline
+#endif
+#ifndef   __STATIC_FORCEINLINE                 
+  #define __STATIC_FORCEINLINE                   static __forceinline
+#endif           
+#ifndef   __NO_RETURN
+  #define __NO_RETURN                            __declspec(noreturn)
+#endif
+#ifndef   __USED
+  #define __USED                                 __attribute__((used))
+#endif
+#ifndef   __WEAK
+  #define __WEAK                                 __attribute__((weak))
+#endif
+#ifndef   __PACKED
+  #define __PACKED                               __attribute__((packed))
+#endif
+#ifndef   __PACKED_STRUCT
+  #define __PACKED_STRUCT                        __packed struct
+#endif
+#ifndef   __PACKED_UNION
+  #define __PACKED_UNION                         __packed union
+#endif
+#ifndef   __UNALIGNED_UINT32        /* deprecated */
+  #define __UNALIGNED_UINT32(x)                  (*((__packed uint32_t *)(x)))
+#endif
+#ifndef   __UNALIGNED_UINT16_WRITE
+  #define __UNALIGNED_UINT16_WRITE(addr, val)    ((*((__packed uint16_t *)(addr))) = (val))
+#endif
+#ifndef   __UNALIGNED_UINT16_READ
+  #define __UNALIGNED_UINT16_READ(addr)          (*((const __packed uint16_t *)(addr)))
+#endif
+#ifndef   __UNALIGNED_UINT32_WRITE
+  #define __UNALIGNED_UINT32_WRITE(addr, val)    ((*((__packed uint32_t *)(addr))) = (val))
+#endif
+#ifndef   __UNALIGNED_UINT32_READ
+  #define __UNALIGNED_UINT32_READ(addr)          (*((const __packed uint32_t *)(addr)))
+#endif
+#ifndef   __ALIGNED
+  #define __ALIGNED(x)                           __attribute__((aligned(x)))
+#endif
+#ifndef   __RESTRICT
+  #define __RESTRICT                             __restrict
+#endif
+
+/* ###########################  Core Function Access  ########################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+  @{
+ */
+
+/**
+  \brief   Enable IRQ Interrupts
+  \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+/* intrinsic void __enable_irq();     */
+
+
+/**
+  \brief   Disable IRQ Interrupts
+  \details Disables IRQ interrupts by setting the I-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+/* intrinsic void __disable_irq();    */
+
+/**
+  \brief   Get Control Register
+  \details Returns the content of the Control Register.
+  \return               Control Register value
+ */
+__STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+  register uint32_t __regControl         __ASM("control");
+  return(__regControl);
+}
+
+
+/**
+  \brief   Set Control Register
+  \details Writes the given value to the Control Register.
+  \param [in]    control  Control Register value to set
+ */
+__STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+  register uint32_t __regControl         __ASM("control");
+  __regControl = control;
+}
+
+
+/**
+  \brief   Get IPSR Register
+  \details Returns the content of the IPSR Register.
+  \return               IPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_IPSR(void)
+{
+  register uint32_t __regIPSR          __ASM("ipsr");
+  return(__regIPSR);
+}
+
+
+/**
+  \brief   Get APSR Register
+  \details Returns the content of the APSR Register.
+  \return               APSR Register value
+ */
+__STATIC_INLINE uint32_t __get_APSR(void)
+{
+  register uint32_t __regAPSR          __ASM("apsr");
+  return(__regAPSR);
+}
+
+
+/**
+  \brief   Get xPSR Register
+  \details Returns the content of the xPSR Register.
+  \return               xPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_xPSR(void)
+{
+  register uint32_t __regXPSR          __ASM("xpsr");
+  return(__regXPSR);
+}
+
+
+/**
+  \brief   Get Process Stack Pointer
+  \details Returns the current value of the Process Stack Pointer (PSP).
+  \return               PSP Register value
+ */
+__STATIC_INLINE uint32_t __get_PSP(void)
+{
+  register uint32_t __regProcessStackPointer  __ASM("psp");
+  return(__regProcessStackPointer);
+}
+
+
+/**
+  \brief   Set Process Stack Pointer
+  \details Assigns the given value to the Process Stack Pointer (PSP).
+  \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+  register uint32_t __regProcessStackPointer  __ASM("psp");
+  __regProcessStackPointer = topOfProcStack;
+}
+
+
+/**
+  \brief   Get Main Stack Pointer
+  \details Returns the current value of the Main Stack Pointer (MSP).
+  \return               MSP Register value
+ */
+__STATIC_INLINE uint32_t __get_MSP(void)
+{
+  register uint32_t __regMainStackPointer     __ASM("msp");
+  return(__regMainStackPointer);
+}
+
+
+/**
+  \brief   Set Main Stack Pointer
+  \details Assigns the given value to the Main Stack Pointer (MSP).
+  \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+  register uint32_t __regMainStackPointer     __ASM("msp");
+  __regMainStackPointer = topOfMainStack;
+}
+
+
+/**
+  \brief   Get Priority Mask
+  \details Returns the current state of the priority mask bit from the Priority Mask Register.
+  \return               Priority Mask value
+ */
+__STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+  register uint32_t __regPriMask         __ASM("primask");
+  return(__regPriMask);
+}
+
+
+/**
+  \brief   Set Priority Mask
+  \details Assigns the given value to the Priority Mask Register.
+  \param [in]    priMask  Priority Mask
+ */
+__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+  register uint32_t __regPriMask         __ASM("primask");
+  __regPriMask = (priMask);
+}
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
+     (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     )
+
+/**
+  \brief   Enable FIQ
+  \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+#define __enable_fault_irq                __enable_fiq
+
+
+/**
+  \brief   Disable FIQ
+  \details Disables FIQ interrupts by setting the F-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+#define __disable_fault_irq               __disable_fiq
+
+
+/**
+  \brief   Get Base Priority
+  \details Returns the current value of the Base Priority register.
+  \return               Base Priority register value
+ */
+__STATIC_INLINE uint32_t  __get_BASEPRI(void)
+{
+  register uint32_t __regBasePri         __ASM("basepri");
+  return(__regBasePri);
+}
+
+
+/**
+  \brief   Set Base Priority
+  \details Assigns the given value to the Base Priority register.
+  \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
+{
+  register uint32_t __regBasePri         __ASM("basepri");
+  __regBasePri = (basePri & 0xFFU);
+}
+
+
+/**
+  \brief   Set Base Priority with condition
+  \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
+           or the new value increases the BASEPRI priority level.
+  \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
+{
+  register uint32_t __regBasePriMax      __ASM("basepri_max");
+  __regBasePriMax = (basePri & 0xFFU);
+}
+
+
+/**
+  \brief   Get Fault Mask
+  \details Returns the current value of the Fault Mask register.
+  \return               Fault Mask register value
+ */
+__STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+  register uint32_t __regFaultMask       __ASM("faultmask");
+  return(__regFaultMask);
+}
+
+
+/**
+  \brief   Set Fault Mask
+  \details Assigns the given value to the Fault Mask register.
+  \param [in]    faultMask  Fault Mask value to set
+ */
+__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+  register uint32_t __regFaultMask       __ASM("faultmask");
+  __regFaultMask = (faultMask & (uint32_t)1U);
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
+           (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     ) */
+
+
+/**
+  \brief   Get FPSCR
+  \details Returns the current value of the Floating Point Status/Control register.
+  \return               Floating Point Status/Control register value
+ */
+__STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+  register uint32_t __regfpscr         __ASM("fpscr");
+  return(__regfpscr);
+#else
+   return(0U);
+#endif
+}
+
+
+/**
+  \brief   Set FPSCR
+  \details Assigns the given value to the Floating Point Status/Control register.
+  \param [in]    fpscr  Floating Point Status/Control value to set
+ */
+__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+  register uint32_t __regfpscr         __ASM("fpscr");
+  __regfpscr = (fpscr);
+#else
+  (void)fpscr;
+#endif
+}
+
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+/* ##########################  Core Instruction Access  ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+  Access to dedicated instructions
+  @{
+*/
+
+/**
+  \brief   No Operation
+  \details No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP                             __nop
+
+
+/**
+  \brief   Wait For Interrupt
+  \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
+ */
+#define __WFI                             __wfi
+
+
+/**
+  \brief   Wait For Event
+  \details Wait For Event is a hint instruction that permits the processor to enter
+           a low-power state until one of a number of events occurs.
+ */
+#define __WFE                             __wfe
+
+
+/**
+  \brief   Send Event
+  \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV                             __sev
+
+
+/**
+  \brief   Instruction Synchronization Barrier
+  \details Instruction Synchronization Barrier flushes the pipeline in the processor,
+           so that all instructions following the ISB are fetched from cache or memory,
+           after the instruction has been completed.
+ */
+#define __ISB() do {\
+                   __schedule_barrier();\
+                   __isb(0xF);\
+                   __schedule_barrier();\
+                } while (0U)
+
+/**
+  \brief   Data Synchronization Barrier
+  \details Acts as a special kind of Data Memory Barrier.
+           It completes when all explicit memory accesses before this instruction complete.
+ */
+#define __DSB() do {\
+                   __schedule_barrier();\
+                   __dsb(0xF);\
+                   __schedule_barrier();\
+                } while (0U)
+
+/**
+  \brief   Data Memory Barrier
+  \details Ensures the apparent order of the explicit memory operations before
+           and after the instruction, without ensuring their completion.
+ */
+#define __DMB() do {\
+                   __schedule_barrier();\
+                   __dmb(0xF);\
+                   __schedule_barrier();\
+                } while (0U)
+
+                  
+/**
+  \brief   Reverse byte order (32 bit)
+  \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#define __REV                             __rev
+
+
+/**
+  \brief   Reverse byte order (16 bit)
+  \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
+{
+  rev16 r0, r0
+  bx lr
+}
+#endif
+
+
+/**
+  \brief   Reverse byte order (16 bit)
+  \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value)
+{
+  revsh r0, r0
+  bx lr
+}
+#endif
+
+
+/**
+  \brief   Rotate Right in unsigned value (32 bit)
+  \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+  \param [in]    op1  Value to rotate
+  \param [in]    op2  Number of Bits to rotate
+  \return               Rotated value
+ */
+#define __ROR                             __ror
+
+
+/**
+  \brief   Breakpoint
+  \details Causes the processor to enter Debug state.
+           Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+  \param [in]    value  is ignored by the processor.
+                 If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value)                       __breakpoint(value)
+
+
+/**
+  \brief   Reverse bit order of value
+  \details Reverses the bit order of the given value.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
+     (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     )
+  #define __RBIT                          __rbit
+#else
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
+{
+  uint32_t result;
+  uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */
+
+  result = value;                      /* r will be reversed bits of v; first get LSB of v */
+  for (value >>= 1U; value != 0U; value >>= 1U)
+  {
+    result <<= 1U;
+    result |= value & 1U;
+    s--;
+  }
+  result <<= s;                        /* shift when v's highest bits are zero */
+  return result;
+}
+#endif
+
+
+/**
+  \brief   Count leading zeros
+  \details Counts the number of leading zeros of a data value.
+  \param [in]  value  Value to count the leading zeros
+  \return             number of leading zeros in value
+ */
+#define __CLZ                             __clz
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
+     (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     )
+
+/**
+  \brief   LDR Exclusive (8 bit)
+  \details Executes a exclusive LDR instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+  #define __LDREXB(ptr)                                                        ((uint8_t ) __ldrex(ptr))
+#else
+  #define __LDREXB(ptr)          _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr))  _Pragma("pop")
+#endif
+
+
+/**
+  \brief   LDR Exclusive (16 bit)
+  \details Executes a exclusive LDR instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+  #define __LDREXH(ptr)                                                        ((uint16_t) __ldrex(ptr))
+#else
+  #define __LDREXH(ptr)          _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr))  _Pragma("pop")
+#endif
+
+
+/**
+  \brief   LDR Exclusive (32 bit)
+  \details Executes a exclusive LDR instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+  #define __LDREXW(ptr)                                                        ((uint32_t ) __ldrex(ptr))
+#else
+  #define __LDREXW(ptr)          _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr))  _Pragma("pop")
+#endif
+
+
+/**
+  \brief   STR Exclusive (8 bit)
+  \details Executes a exclusive STR instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+  #define __STREXB(value, ptr)                                                 __strex(value, ptr)
+#else
+  #define __STREXB(value, ptr)   _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr)        _Pragma("pop")
+#endif
+
+
+/**
+  \brief   STR Exclusive (16 bit)
+  \details Executes a exclusive STR instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+  #define __STREXH(value, ptr)                                                 __strex(value, ptr)
+#else
+  #define __STREXH(value, ptr)   _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr)        _Pragma("pop")
+#endif
+
+
+/**
+  \brief   STR Exclusive (32 bit)
+  \details Executes a exclusive STR instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+  #define __STREXW(value, ptr)                                                 __strex(value, ptr)
+#else
+  #define __STREXW(value, ptr)   _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr)        _Pragma("pop")
+#endif
+
+
+/**
+  \brief   Remove the exclusive lock
+  \details Removes the exclusive lock which is created by LDREX.
+ */
+#define __CLREX                           __clrex
+
+
+/**
+  \brief   Signed Saturate
+  \details Saturates a signed value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (1..32)
+  \return             Saturated value
+ */
+#define __SSAT                            __ssat
+
+
+/**
+  \brief   Unsigned Saturate
+  \details Saturates an unsigned value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (0..31)
+  \return             Saturated value
+ */
+#define __USAT                            __usat
+
+
+/**
+  \brief   Rotate Right with Extend (32 bit)
+  \details Moves each bit of a bitstring right by one bit.
+           The carry input is shifted in at the left end of the bitstring.
+  \param [in]    value  Value to rotate
+  \return               Rotated value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
+{
+  rrx r0, r0
+  bx lr
+}
+#endif
+
+
+/**
+  \brief   LDRT Unprivileged (8 bit)
+  \details Executes a Unprivileged LDRT instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+#define __LDRBT(ptr)                      ((uint8_t )  __ldrt(ptr))
+
+
+/**
+  \brief   LDRT Unprivileged (16 bit)
+  \details Executes a Unprivileged LDRT instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+#define __LDRHT(ptr)                      ((uint16_t)  __ldrt(ptr))
+
+
+/**
+  \brief   LDRT Unprivileged (32 bit)
+  \details Executes a Unprivileged LDRT instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+#define __LDRT(ptr)                       ((uint32_t ) __ldrt(ptr))
+
+
+/**
+  \brief   STRT Unprivileged (8 bit)
+  \details Executes a Unprivileged STRT instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+#define __STRBT(value, ptr)               __strt(value, ptr)
+
+
+/**
+  \brief   STRT Unprivileged (16 bit)
+  \details Executes a Unprivileged STRT instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+#define __STRHT(value, ptr)               __strt(value, ptr)
+
+
+/**
+  \brief   STRT Unprivileged (32 bit)
+  \details Executes a Unprivileged STRT instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+#define __STRT(value, ptr)                __strt(value, ptr)
+
+#else  /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
+           (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     ) */
+
+/**
+  \brief   Signed Saturate
+  \details Saturates a signed value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (1..32)
+  \return             Saturated value
+ */
+__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
+{
+  if ((sat >= 1U) && (sat <= 32U))
+  {
+    const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
+    const int32_t min = -1 - max ;
+    if (val > max)
+    {
+      return max;
+    }
+    else if (val < min)
+    {
+      return min;
+    }
+  }
+  return val;
+}
+
+/**
+  \brief   Unsigned Saturate
+  \details Saturates an unsigned value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (0..31)
+  \return             Saturated value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
+{
+  if (sat <= 31U)
+  {
+    const uint32_t max = ((1U << sat) - 1U);
+    if (val > (int32_t)max)
+    {
+      return max;
+    }
+    else if (val < 0)
+    {
+      return 0U;
+    }
+  }
+  return (uint32_t)val;
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
+           (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     ) */
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+
+/* ###################  Compiler specific Intrinsics  ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+  Access to dedicated SIMD instructions
+  @{
+*/
+
+#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     )
+
+#define __SADD8                           __sadd8
+#define __QADD8                           __qadd8
+#define __SHADD8                          __shadd8
+#define __UADD8                           __uadd8
+#define __UQADD8                          __uqadd8
+#define __UHADD8                          __uhadd8
+#define __SSUB8                           __ssub8
+#define __QSUB8                           __qsub8
+#define __SHSUB8                          __shsub8
+#define __USUB8                           __usub8
+#define __UQSUB8                          __uqsub8
+#define __UHSUB8                          __uhsub8
+#define __SADD16                          __sadd16
+#define __QADD16                          __qadd16
+#define __SHADD16                         __shadd16
+#define __UADD16                          __uadd16
+#define __UQADD16                         __uqadd16
+#define __UHADD16                         __uhadd16
+#define __SSUB16                          __ssub16
+#define __QSUB16                          __qsub16
+#define __SHSUB16                         __shsub16
+#define __USUB16                          __usub16
+#define __UQSUB16                         __uqsub16
+#define __UHSUB16                         __uhsub16
+#define __SASX                            __sasx
+#define __QASX                            __qasx
+#define __SHASX                           __shasx
+#define __UASX                            __uasx
+#define __UQASX                           __uqasx
+#define __UHASX                           __uhasx
+#define __SSAX                            __ssax
+#define __QSAX                            __qsax
+#define __SHSAX                           __shsax
+#define __USAX                            __usax
+#define __UQSAX                           __uqsax
+#define __UHSAX                           __uhsax
+#define __USAD8                           __usad8
+#define __USADA8                          __usada8
+#define __SSAT16                          __ssat16
+#define __USAT16                          __usat16
+#define __UXTB16                          __uxtb16
+#define __UXTAB16                         __uxtab16
+#define __SXTB16                          __sxtb16
+#define __SXTAB16                         __sxtab16
+#define __SMUAD                           __smuad
+#define __SMUADX                          __smuadx
+#define __SMLAD                           __smlad
+#define __SMLADX                          __smladx
+#define __SMLALD                          __smlald
+#define __SMLALDX                         __smlaldx
+#define __SMUSD                           __smusd
+#define __SMUSDX                          __smusdx
+#define __SMLSD                           __smlsd
+#define __SMLSDX                          __smlsdx
+#define __SMLSLD                          __smlsld
+#define __SMLSLDX                         __smlsldx
+#define __SEL                             __sel
+#define __QADD                            __qadd
+#define __QSUB                            __qsub
+
+#define __PKHBT(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0x0000FFFFUL) |  \
+                                           ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL)  )
+
+#define __PKHTB(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0xFFFF0000UL) |  \
+                                           ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)  )
+
+#define __SMMLA(ARG1,ARG2,ARG3)          ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
+                                                      ((int64_t)(ARG3) << 32U)     ) >> 32U))
+
+#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     ) */
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#endif /* __CMSIS_ARMCC_H */
diff --git a/Drivers/CMSIS/Include/cmsis_armclang.h b/Drivers/CMSIS/Include/cmsis_armclang.h
new file mode 100644
index 0000000..d8031b0
--- /dev/null
+++ b/Drivers/CMSIS/Include/cmsis_armclang.h
@@ -0,0 +1,1869 @@
+/**************************************************************************//**
+ * @file     cmsis_armclang.h
+ * @brief    CMSIS compiler armclang (Arm Compiler 6) header file
+ * @version  V5.0.4
+ * @date     10. January 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */
+
+#ifndef __CMSIS_ARMCLANG_H
+#define __CMSIS_ARMCLANG_H
+
+#pragma clang system_header   /* treat file as system include file */
+
+#ifndef __ARM_COMPAT_H
+#include <arm_compat.h>    /* Compatibility header for Arm Compiler 5 intrinsics */
+#endif
+
+/* CMSIS compiler specific defines */
+#ifndef   __ASM
+  #define __ASM                                  __asm
+#endif
+#ifndef   __INLINE
+  #define __INLINE                               __inline
+#endif
+#ifndef   __STATIC_INLINE
+  #define __STATIC_INLINE                        static __inline
+#endif
+#ifndef   __STATIC_FORCEINLINE                 
+  #define __STATIC_FORCEINLINE                   __attribute__((always_inline)) static __inline
+#endif                                           
+#ifndef   __NO_RETURN
+  #define __NO_RETURN                            __attribute__((__noreturn__))
+#endif
+#ifndef   __USED
+  #define __USED                                 __attribute__((used))
+#endif
+#ifndef   __WEAK
+  #define __WEAK                                 __attribute__((weak))
+#endif
+#ifndef   __PACKED
+  #define __PACKED                               __attribute__((packed, aligned(1)))
+#endif
+#ifndef   __PACKED_STRUCT
+  #define __PACKED_STRUCT                        struct __attribute__((packed, aligned(1)))
+#endif
+#ifndef   __PACKED_UNION
+  #define __PACKED_UNION                         union __attribute__((packed, aligned(1)))
+#endif
+#ifndef   __UNALIGNED_UINT32        /* deprecated */
+  #pragma clang diagnostic push
+  #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */
+  struct __attribute__((packed)) T_UINT32 { uint32_t v; };
+  #pragma clang diagnostic pop
+  #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+#endif
+#ifndef   __UNALIGNED_UINT16_WRITE
+  #pragma clang diagnostic push
+  #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */
+  __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+  #pragma clang diagnostic pop
+  #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef   __UNALIGNED_UINT16_READ
+  #pragma clang diagnostic push
+  #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */
+  __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+  #pragma clang diagnostic pop
+  #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+#endif
+#ifndef   __UNALIGNED_UINT32_WRITE
+  #pragma clang diagnostic push
+  #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */
+  __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+  #pragma clang diagnostic pop
+  #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef   __UNALIGNED_UINT32_READ
+  #pragma clang diagnostic push
+  #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */
+  __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+  #pragma clang diagnostic pop
+  #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+#endif
+#ifndef   __ALIGNED
+  #define __ALIGNED(x)                           __attribute__((aligned(x)))
+#endif
+#ifndef   __RESTRICT
+  #define __RESTRICT                             __restrict
+#endif
+
+
+/* ###########################  Core Function Access  ########################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+  @{
+ */
+
+/**
+  \brief   Enable IRQ Interrupts
+  \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+/* intrinsic void __enable_irq();  see arm_compat.h */
+
+
+/**
+  \brief   Disable IRQ Interrupts
+  \details Disables IRQ interrupts by setting the I-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+/* intrinsic void __disable_irq();  see arm_compat.h */
+
+
+/**
+  \brief   Get Control Register
+  \details Returns the content of the Control Register.
+  \return               Control Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_CONTROL(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, control" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Control Register (non-secure)
+  \details Returns the content of the non-secure Control Register when in secure mode.
+  \return               non-secure Control Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, control_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Control Register
+  \details Writes the given value to the Control Register.
+  \param [in]    control  Control Register value to set
+ */
+__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control)
+{
+  __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Control Register (non-secure)
+  \details Writes the given value to the non-secure Control Register when in secure state.
+  \param [in]    control  Control Register value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)
+{
+  __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");
+}
+#endif
+
+
+/**
+  \brief   Get IPSR Register
+  \details Returns the content of the IPSR Register.
+  \return               IPSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_IPSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+  return(result);
+}
+
+
+/**
+  \brief   Get APSR Register
+  \details Returns the content of the APSR Register.
+  \return               APSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_APSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+  return(result);
+}
+
+
+/**
+  \brief   Get xPSR Register
+  \details Returns the content of the xPSR Register.
+  \return               xPSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_xPSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+  return(result);
+}
+
+
+/**
+  \brief   Get Process Stack Pointer
+  \details Returns the current value of the Process Stack Pointer (PSP).
+  \return               PSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PSP(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, psp"  : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Process Stack Pointer (non-secure)
+  \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.
+  \return               PSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, psp_ns"  : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Process Stack Pointer
+  \details Assigns the given value to the Process Stack Pointer (PSP).
+  \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack)
+{
+  __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Process Stack Pointer (non-secure)
+  \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.
+  \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
+{
+  __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );
+}
+#endif
+
+
+/**
+  \brief   Get Main Stack Pointer
+  \details Returns the current value of the Main Stack Pointer (MSP).
+  \return               MSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_MSP(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, msp" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Main Stack Pointer (non-secure)
+  \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.
+  \return               MSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Main Stack Pointer
+  \details Assigns the given value to the Main Stack Pointer (MSP).
+  \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack)
+{
+  __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Main Stack Pointer (non-secure)
+  \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
+  \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
+{
+  __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );
+}
+#endif
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Stack Pointer (non-secure)
+  \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.
+  \return               SP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, sp_ns" : "=r" (result) );
+  return(result);
+}
+
+
+/**
+  \brief   Set Stack Pointer (non-secure)
+  \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.
+  \param [in]    topOfStack  Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack)
+{
+  __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : );
+}
+#endif
+
+
+/**
+  \brief   Get Priority Mask
+  \details Returns the current state of the priority mask bit from the Priority Mask Register.
+  \return               Priority Mask value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, primask" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Priority Mask (non-secure)
+  \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.
+  \return               Priority Mask value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, primask_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Priority Mask
+  \details Assigns the given value to the Priority Mask Register.
+  \param [in]    priMask  Priority Mask
+ */
+__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask)
+{
+  __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Priority Mask (non-secure)
+  \details Assigns the given value to the non-secure Priority Mask Register when in secure state.
+  \param [in]    priMask  Priority Mask
+ */
+__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)
+{
+  __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");
+}
+#endif
+
+
+#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+/**
+  \brief   Enable FIQ
+  \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+#define __enable_fault_irq                __enable_fiq   /* see arm_compat.h */
+
+
+/**
+  \brief   Disable FIQ
+  \details Disables FIQ interrupts by setting the F-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+#define __disable_fault_irq               __disable_fiq   /* see arm_compat.h */
+
+
+/**
+  \brief   Get Base Priority
+  \details Returns the current value of the Base Priority register.
+  \return               Base Priority register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, basepri" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Base Priority (non-secure)
+  \details Returns the current value of the non-secure Base Priority register when in secure state.
+  \return               Base Priority register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Base Priority
+  \details Assigns the given value to the Base Priority register.
+  \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri)
+{
+  __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Base Priority (non-secure)
+  \details Assigns the given value to the non-secure Base Priority register when in secure state.
+  \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)
+{
+  __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");
+}
+#endif
+
+
+/**
+  \brief   Set Base Priority with condition
+  \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
+           or the new value increases the BASEPRI priority level.
+  \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri)
+{
+  __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");
+}
+
+
+/**
+  \brief   Get Fault Mask
+  \details Returns the current value of the Fault Mask register.
+  \return               Fault Mask register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Fault Mask (non-secure)
+  \details Returns the current value of the non-secure Fault Mask register when in secure state.
+  \return               Fault Mask register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Fault Mask
+  \details Assigns the given value to the Fault Mask register.
+  \param [in]    faultMask  Fault Mask value to set
+ */
+__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+  __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Fault Mask (non-secure)
+  \details Assigns the given value to the non-secure Fault Mask register when in secure state.
+  \param [in]    faultMask  Fault Mask value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
+{
+  __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
+
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
+
+/**
+  \brief   Get Process Stack Pointer Limit
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence zero is returned always in non-secure
+  mode.
+  
+  \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
+  \return               PSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+    // without main extensions, the non-secure PSPLIM is RAZ/WI
+  return 0U;
+#else
+  uint32_t result;
+  __ASM volatile ("MRS %0, psplim"  : "=r" (result) );
+  return result;
+#endif
+}
+
+#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Process Stack Pointer Limit (non-secure)
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence zero is returned always in non-secure
+  mode.
+
+  \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+  \return               PSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+  // without main extensions, the non-secure PSPLIM is RAZ/WI
+  return 0U;
+#else
+  uint32_t result;
+  __ASM volatile ("MRS %0, psplim_ns"  : "=r" (result) );
+  return result;
+#endif
+}
+#endif
+
+
+/**
+  \brief   Set Process Stack Pointer Limit
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence the write is silently ignored in non-secure
+  mode.
+  
+  \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
+  \param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+  // without main extensions, the non-secure PSPLIM is RAZ/WI
+  (void)ProcStackPtrLimit;
+#else
+  __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))
+/**
+  \brief   Set Process Stack Pointer (non-secure)
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence the write is silently ignored in non-secure
+  mode.
+
+  \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+  \param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+  // without main extensions, the non-secure PSPLIM is RAZ/WI
+  (void)ProcStackPtrLimit;
+#else
+  __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
+#endif
+}
+#endif
+
+
+/**
+  \brief   Get Main Stack Pointer Limit
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence zero is returned always.
+
+  \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
+  \return               MSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+  // without main extensions, the non-secure MSPLIM is RAZ/WI
+  return 0U;
+#else
+  uint32_t result;
+  __ASM volatile ("MRS %0, msplim" : "=r" (result) );
+  return result;
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))
+/**
+  \brief   Get Main Stack Pointer Limit (non-secure)
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence zero is returned always.
+
+  \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.
+  \return               MSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+  // without main extensions, the non-secure MSPLIM is RAZ/WI
+  return 0U;
+#else
+  uint32_t result;
+  __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );
+  return result;
+#endif
+}
+#endif
+
+
+/**
+  \brief   Set Main Stack Pointer Limit
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence the write is silently ignored.
+
+  \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
+  \param [in]    MainStackPtrLimit  Main Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+  // without main extensions, the non-secure MSPLIM is RAZ/WI
+  (void)MainStackPtrLimit;
+#else
+  __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))
+/**
+  \brief   Set Main Stack Pointer Limit (non-secure)
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence the write is silently ignored.
+
+  \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.
+  \param [in]    MainStackPtrLimit  Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+  // without main extensions, the non-secure MSPLIM is RAZ/WI
+  (void)MainStackPtrLimit;
+#else
+  __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));
+#endif
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
+
+/**
+  \brief   Get FPSCR
+  \details Returns the current value of the Floating Point Status/Control register.
+  \return               Floating Point Status/Control register value
+ */
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+#define __get_FPSCR      (uint32_t)__builtin_arm_get_fpscr
+#else
+#define __get_FPSCR()      ((uint32_t)0U)
+#endif
+
+/**
+  \brief   Set FPSCR
+  \details Assigns the given value to the Floating Point Status/Control register.
+  \param [in]    fpscr  Floating Point Status/Control value to set
+ */
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+#define __set_FPSCR      __builtin_arm_set_fpscr
+#else
+#define __set_FPSCR(x)      ((void)(x))
+#endif
+
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+/* ##########################  Core Instruction Access  ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+  Access to dedicated instructions
+  @{
+*/
+
+/* Define macros for porting to both thumb1 and thumb2.
+ * For thumb1, use low register (r0-r7), specified by constraint "l"
+ * Otherwise, use general registers, specified by constraint "r" */
+#if defined (__thumb__) && !defined (__thumb2__)
+#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
+#define __CMSIS_GCC_USE_REG(r) "l" (r)
+#else
+#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
+#define __CMSIS_GCC_USE_REG(r) "r" (r)
+#endif
+
+/**
+  \brief   No Operation
+  \details No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP          __builtin_arm_nop
+
+/**
+  \brief   Wait For Interrupt
+  \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
+ */
+#define __WFI          __builtin_arm_wfi
+
+
+/**
+  \brief   Wait For Event
+  \details Wait For Event is a hint instruction that permits the processor to enter
+           a low-power state until one of a number of events occurs.
+ */
+#define __WFE          __builtin_arm_wfe
+
+
+/**
+  \brief   Send Event
+  \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV          __builtin_arm_sev
+
+
+/**
+  \brief   Instruction Synchronization Barrier
+  \details Instruction Synchronization Barrier flushes the pipeline in the processor,
+           so that all instructions following the ISB are fetched from cache or memory,
+           after the instruction has been completed.
+ */
+#define __ISB()        __builtin_arm_isb(0xF);
+
+/**
+  \brief   Data Synchronization Barrier
+  \details Acts as a special kind of Data Memory Barrier.
+           It completes when all explicit memory accesses before this instruction complete.
+ */
+#define __DSB()        __builtin_arm_dsb(0xF);
+
+
+/**
+  \brief   Data Memory Barrier
+  \details Ensures the apparent order of the explicit memory operations before
+           and after the instruction, without ensuring their completion.
+ */
+#define __DMB()        __builtin_arm_dmb(0xF);
+
+
+/**
+  \brief   Reverse byte order (32 bit)
+  \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#define __REV(value)   __builtin_bswap32(value)
+
+
+/**
+  \brief   Reverse byte order (16 bit)
+  \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#define __REV16(value) __ROR(__REV(value), 16)
+
+
+/**
+  \brief   Reverse byte order (16 bit)
+  \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#define __REVSH(value) (int16_t)__builtin_bswap16(value)
+
+
+/**
+  \brief   Rotate Right in unsigned value (32 bit)
+  \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+  \param [in]    op1  Value to rotate
+  \param [in]    op2  Number of Bits to rotate
+  \return               Rotated value
+ */
+__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
+{
+  op2 %= 32U;
+  if (op2 == 0U)
+  {
+    return op1;
+  }
+  return (op1 >> op2) | (op1 << (32U - op2));
+}
+
+
+/**
+  \brief   Breakpoint
+  \details Causes the processor to enter Debug state.
+           Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+  \param [in]    value  is ignored by the processor.
+                 If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value)     __ASM volatile ("bkpt "#value)
+
+
+/**
+  \brief   Reverse bit order of value
+  \details Reverses the bit order of the given value.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#define __RBIT            __builtin_arm_rbit
+
+/**
+  \brief   Count leading zeros
+  \details Counts the number of leading zeros of a data value.
+  \param [in]  value  Value to count the leading zeros
+  \return             number of leading zeros in value
+ */
+#define __CLZ             (uint8_t)__builtin_clz
+
+
+#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
+/**
+  \brief   LDR Exclusive (8 bit)
+  \details Executes a exclusive LDR instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+#define __LDREXB        (uint8_t)__builtin_arm_ldrex
+
+
+/**
+  \brief   LDR Exclusive (16 bit)
+  \details Executes a exclusive LDR instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+#define __LDREXH        (uint16_t)__builtin_arm_ldrex
+
+
+/**
+  \brief   LDR Exclusive (32 bit)
+  \details Executes a exclusive LDR instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+#define __LDREXW        (uint32_t)__builtin_arm_ldrex
+
+
+/**
+  \brief   STR Exclusive (8 bit)
+  \details Executes a exclusive STR instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#define __STREXB        (uint32_t)__builtin_arm_strex
+
+
+/**
+  \brief   STR Exclusive (16 bit)
+  \details Executes a exclusive STR instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#define __STREXH        (uint32_t)__builtin_arm_strex
+
+
+/**
+  \brief   STR Exclusive (32 bit)
+  \details Executes a exclusive STR instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#define __STREXW        (uint32_t)__builtin_arm_strex
+
+
+/**
+  \brief   Remove the exclusive lock
+  \details Removes the exclusive lock which is created by LDREX.
+ */
+#define __CLREX             __builtin_arm_clrex
+
+#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
+
+
+#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+
+/**
+  \brief   Signed Saturate
+  \details Saturates a signed value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (1..32)
+  \return             Saturated value
+ */
+#define __SSAT             __builtin_arm_ssat
+
+
+/**
+  \brief   Unsigned Saturate
+  \details Saturates an unsigned value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (0..31)
+  \return             Saturated value
+ */
+#define __USAT             __builtin_arm_usat
+
+
+/**
+  \brief   Rotate Right with Extend (32 bit)
+  \details Moves each bit of a bitstring right by one bit.
+           The carry input is shifted in at the left end of the bitstring.
+  \param [in]    value  Value to rotate
+  \return               Rotated value
+ */
+__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value)
+{
+  uint32_t result;
+
+  __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return(result);
+}
+
+
+/**
+  \brief   LDRT Unprivileged (8 bit)
+  \details Executes a Unprivileged LDRT instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr)
+{
+  uint32_t result;
+
+  __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) );
+  return ((uint8_t) result);    /* Add explicit type cast here */
+}
+
+
+/**
+  \brief   LDRT Unprivileged (16 bit)
+  \details Executes a Unprivileged LDRT instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr)
+{
+  uint32_t result;
+
+  __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) );
+  return ((uint16_t) result);    /* Add explicit type cast here */
+}
+
+
+/**
+  \brief   LDRT Unprivileged (32 bit)
+  \details Executes a Unprivileged LDRT instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr)
+{
+  uint32_t result;
+
+  __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) );
+  return(result);
+}
+
+
+/**
+  \brief   STRT Unprivileged (8 bit)
+  \details Executes a Unprivileged STRT instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)
+{
+  __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   STRT Unprivileged (16 bit)
+  \details Executes a Unprivileged STRT instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)
+{
+  __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   STRT Unprivileged (32 bit)
+  \details Executes a Unprivileged STRT instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr)
+{
+  __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) );
+}
+
+#else  /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
+
+/**
+  \brief   Signed Saturate
+  \details Saturates a signed value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (1..32)
+  \return             Saturated value
+ */
+__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat)
+{
+  if ((sat >= 1U) && (sat <= 32U))
+  {
+    const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
+    const int32_t min = -1 - max ;
+    if (val > max)
+    {
+      return max;
+    }
+    else if (val < min)
+    {
+      return min;
+    }
+  }
+  return val;
+}
+
+/**
+  \brief   Unsigned Saturate
+  \details Saturates an unsigned value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (0..31)
+  \return             Saturated value
+ */
+__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat)
+{
+  if (sat <= 31U)
+  {
+    const uint32_t max = ((1U << sat) - 1U);
+    if (val > (int32_t)max)
+    {
+      return max;
+    }
+    else if (val < 0)
+    {
+      return 0U;
+    }
+  }
+  return (uint32_t)val;
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
+
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
+/**
+  \brief   Load-Acquire (8 bit)
+  \details Executes a LDAB instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr)
+{
+  uint32_t result;
+
+  __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) );
+  return ((uint8_t) result);
+}
+
+
+/**
+  \brief   Load-Acquire (16 bit)
+  \details Executes a LDAH instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr)
+{
+  uint32_t result;
+
+  __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) );
+  return ((uint16_t) result);
+}
+
+
+/**
+  \brief   Load-Acquire (32 bit)
+  \details Executes a LDA instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr)
+{
+  uint32_t result;
+
+  __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) );
+  return(result);
+}
+
+
+/**
+  \brief   Store-Release (8 bit)
+  \details Executes a STLB instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr)
+{
+  __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   Store-Release (16 bit)
+  \details Executes a STLH instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr)
+{
+  __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   Store-Release (32 bit)
+  \details Executes a STL instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr)
+{
+  __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   Load-Acquire Exclusive (8 bit)
+  \details Executes a LDAB exclusive instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+#define     __LDAEXB                 (uint8_t)__builtin_arm_ldaex
+
+
+/**
+  \brief   Load-Acquire Exclusive (16 bit)
+  \details Executes a LDAH exclusive instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+#define     __LDAEXH                 (uint16_t)__builtin_arm_ldaex
+
+
+/**
+  \brief   Load-Acquire Exclusive (32 bit)
+  \details Executes a LDA exclusive instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+#define     __LDAEX                  (uint32_t)__builtin_arm_ldaex
+
+
+/**
+  \brief   Store-Release Exclusive (8 bit)
+  \details Executes a STLB exclusive instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#define     __STLEXB                 (uint32_t)__builtin_arm_stlex
+
+
+/**
+  \brief   Store-Release Exclusive (16 bit)
+  \details Executes a STLH exclusive instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#define     __STLEXH                 (uint32_t)__builtin_arm_stlex
+
+
+/**
+  \brief   Store-Release Exclusive (32 bit)
+  \details Executes a STL exclusive instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#define     __STLEX                  (uint32_t)__builtin_arm_stlex
+
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+
+/* ###################  Compiler specific Intrinsics  ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+  Access to dedicated SIMD instructions
+  @{
+*/
+
+#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1))
+
+__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+
+__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+
+__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+#define __SSAT16(ARG1,ARG2) \
+({                          \
+  int32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+#define __USAT16(ARG1,ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("usat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1)
+{
+  uint32_t result;
+
+  __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1)
+{
+  uint32_t result;
+
+  __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUAD  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   /* Little endian */
+  __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               /* Big endian */
+  __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   /* Little endian */
+  __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               /* Big endian */
+  __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUSD  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   /* Little endian */
+  __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               /* Big endian */
+  __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   /* Little endian */
+  __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               /* Big endian */
+  __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint32_t __SEL  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE  int32_t __QADD( int32_t op1,  int32_t op2)
+{
+  int32_t result;
+
+  __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE  int32_t __QSUB( int32_t op1,  int32_t op2)
+{
+  int32_t result;
+
+  __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+#if 0
+#define __PKHBT(ARG1,ARG2,ARG3) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+  __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
+  __RES; \
+ })
+
+#define __PKHTB(ARG1,ARG2,ARG3) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+  if (ARG3 == 0) \
+    __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2)  ); \
+  else \
+    __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
+  __RES; \
+ })
+#endif
+
+#define __PKHBT(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0x0000FFFFUL) |  \
+                                           ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL)  )
+
+#define __PKHTB(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0xFFFF0000UL) |  \
+                                           ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)  )
+
+__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
+{
+  int32_t result;
+
+  __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r"  (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+#endif /* (__ARM_FEATURE_DSP == 1) */
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#endif /* __CMSIS_ARMCLANG_H */
diff --git a/Drivers/CMSIS/Include/cmsis_compiler.h b/Drivers/CMSIS/Include/cmsis_compiler.h
new file mode 100644
index 0000000..79a2cac
--- /dev/null
+++ b/Drivers/CMSIS/Include/cmsis_compiler.h
@@ -0,0 +1,266 @@
+/**************************************************************************//**
+ * @file     cmsis_compiler.h
+ * @brief    CMSIS compiler generic header file
+ * @version  V5.0.4
+ * @date     10. January 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_COMPILER_H
+#define __CMSIS_COMPILER_H
+
+#include <stdint.h>
+
+/*
+ * Arm Compiler 4/5
+ */
+#if   defined ( __CC_ARM )
+  #include "cmsis_armcc.h"
+
+
+/*
+ * Arm Compiler 6 (armclang)
+ */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #include "cmsis_armclang.h"
+
+
+/*
+ * GNU Compiler
+ */
+#elif defined ( __GNUC__ )
+  #include "cmsis_gcc.h"
+
+
+/*
+ * IAR Compiler
+ */
+#elif defined ( __ICCARM__ )
+  #include <cmsis_iccarm.h>
+
+
+/*
+ * TI Arm Compiler
+ */
+#elif defined ( __TI_ARM__ )
+  #include <cmsis_ccs.h>
+
+  #ifndef   __ASM
+    #define __ASM                                  __asm
+  #endif
+  #ifndef   __INLINE
+    #define __INLINE                               inline
+  #endif
+  #ifndef   __STATIC_INLINE
+    #define __STATIC_INLINE                        static inline
+  #endif
+  #ifndef   __STATIC_FORCEINLINE
+    #define __STATIC_FORCEINLINE                   __STATIC_INLINE
+  #endif
+  #ifndef   __NO_RETURN
+    #define __NO_RETURN                            __attribute__((noreturn))
+  #endif
+  #ifndef   __USED
+    #define __USED                                 __attribute__((used))
+  #endif
+  #ifndef   __WEAK
+    #define __WEAK                                 __attribute__((weak))
+  #endif
+  #ifndef   __PACKED
+    #define __PACKED                               __attribute__((packed))
+  #endif
+  #ifndef   __PACKED_STRUCT
+    #define __PACKED_STRUCT                        struct __attribute__((packed))
+  #endif
+  #ifndef   __PACKED_UNION
+    #define __PACKED_UNION                         union __attribute__((packed))
+  #endif
+  #ifndef   __UNALIGNED_UINT32        /* deprecated */
+    struct __attribute__((packed)) T_UINT32 { uint32_t v; };
+    #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT16_WRITE
+    __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+    #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT16_READ
+    __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+    #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT32_WRITE
+    __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+    #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT32_READ
+    __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+    #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __ALIGNED
+    #define __ALIGNED(x)                           __attribute__((aligned(x)))
+  #endif
+  #ifndef   __RESTRICT
+    #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
+    #define __RESTRICT
+  #endif
+
+
+/*
+ * TASKING Compiler
+ */
+#elif defined ( __TASKING__ )
+  /*
+   * The CMSIS functions have been implemented as intrinsics in the compiler.
+   * Please use "carm -?i" to get an up to date list of all intrinsics,
+   * Including the CMSIS ones.
+   */
+
+  #ifndef   __ASM
+    #define __ASM                                  __asm
+  #endif
+  #ifndef   __INLINE
+    #define __INLINE                               inline
+  #endif
+  #ifndef   __STATIC_INLINE
+    #define __STATIC_INLINE                        static inline
+  #endif
+  #ifndef   __STATIC_FORCEINLINE
+    #define __STATIC_FORCEINLINE                   __STATIC_INLINE
+  #endif
+  #ifndef   __NO_RETURN
+    #define __NO_RETURN                            __attribute__((noreturn))
+  #endif
+  #ifndef   __USED
+    #define __USED                                 __attribute__((used))
+  #endif
+  #ifndef   __WEAK
+    #define __WEAK                                 __attribute__((weak))
+  #endif
+  #ifndef   __PACKED
+    #define __PACKED                               __packed__
+  #endif
+  #ifndef   __PACKED_STRUCT
+    #define __PACKED_STRUCT                        struct __packed__
+  #endif
+  #ifndef   __PACKED_UNION
+    #define __PACKED_UNION                         union __packed__
+  #endif
+  #ifndef   __UNALIGNED_UINT32        /* deprecated */
+    struct __packed__ T_UINT32 { uint32_t v; };
+    #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT16_WRITE
+    __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+    #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT16_READ
+    __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+    #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT32_WRITE
+    __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+    #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT32_READ
+    __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+    #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __ALIGNED
+    #define __ALIGNED(x)              __align(x)
+  #endif
+  #ifndef   __RESTRICT
+    #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
+    #define __RESTRICT
+  #endif
+
+
+/*
+ * COSMIC Compiler
+ */
+#elif defined ( __CSMC__ )
+   #include <cmsis_csm.h>
+
+ #ifndef   __ASM
+    #define __ASM                                  _asm
+  #endif
+  #ifndef   __INLINE
+    #define __INLINE                               inline
+  #endif
+  #ifndef   __STATIC_INLINE
+    #define __STATIC_INLINE                        static inline
+  #endif
+  #ifndef   __STATIC_FORCEINLINE
+    #define __STATIC_FORCEINLINE                   __STATIC_INLINE
+  #endif
+  #ifndef   __NO_RETURN
+    // NO RETURN is automatically detected hence no warning here
+    #define __NO_RETURN
+  #endif
+  #ifndef   __USED
+    #warning No compiler specific solution for __USED. __USED is ignored.
+    #define __USED
+  #endif
+  #ifndef   __WEAK
+    #define __WEAK                                 __weak
+  #endif
+  #ifndef   __PACKED
+    #define __PACKED                               @packed
+  #endif
+  #ifndef   __PACKED_STRUCT
+    #define __PACKED_STRUCT                        @packed struct
+  #endif
+  #ifndef   __PACKED_UNION
+    #define __PACKED_UNION                         @packed union
+  #endif
+  #ifndef   __UNALIGNED_UINT32        /* deprecated */
+    @packed struct T_UINT32 { uint32_t v; };
+    #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT16_WRITE
+    __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+    #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT16_READ
+    __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+    #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT32_WRITE
+    __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+    #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT32_READ
+    __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+    #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __ALIGNED
+    #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
+    #define __ALIGNED(x)
+  #endif
+  #ifndef   __RESTRICT
+    #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
+    #define __RESTRICT
+  #endif
+
+
+#else
+  #error Unknown compiler.
+#endif
+
+
+#endif /* __CMSIS_COMPILER_H */
+
diff --git a/Drivers/CMSIS/Include/cmsis_gcc.h b/Drivers/CMSIS/Include/cmsis_gcc.h
new file mode 100644
index 0000000..1bd41a4
--- /dev/null
+++ b/Drivers/CMSIS/Include/cmsis_gcc.h
@@ -0,0 +1,2085 @@
+/**************************************************************************//**
+ * @file     cmsis_gcc.h
+ * @brief    CMSIS compiler GCC header file
+ * @version  V5.0.4
+ * @date     09. April 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_GCC_H
+#define __CMSIS_GCC_H
+
+/* ignore some GCC warnings */
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wsign-conversion"
+#pragma GCC diagnostic ignored "-Wconversion"
+#pragma GCC diagnostic ignored "-Wunused-parameter"
+
+/* Fallback for __has_builtin */
+#ifndef __has_builtin
+  #define __has_builtin(x) (0)
+#endif
+
+/* CMSIS compiler specific defines */
+#ifndef   __ASM
+  #define __ASM                                  __asm
+#endif
+#ifndef   __INLINE
+  #define __INLINE                               inline
+#endif
+#ifndef   __STATIC_INLINE
+  #define __STATIC_INLINE                        static inline
+#endif
+#ifndef   __STATIC_FORCEINLINE                 
+  #define __STATIC_FORCEINLINE                   __attribute__((always_inline)) static inline
+#endif                                           
+#ifndef   __NO_RETURN
+  #define __NO_RETURN                            __attribute__((__noreturn__))
+#endif
+#ifndef   __USED
+  #define __USED                                 __attribute__((used))
+#endif
+#ifndef   __WEAK
+  #define __WEAK                                 __attribute__((weak))
+#endif
+#ifndef   __PACKED
+  #define __PACKED                               __attribute__((packed, aligned(1)))
+#endif
+#ifndef   __PACKED_STRUCT
+  #define __PACKED_STRUCT                        struct __attribute__((packed, aligned(1)))
+#endif
+#ifndef   __PACKED_UNION
+  #define __PACKED_UNION                         union __attribute__((packed, aligned(1)))
+#endif
+#ifndef   __UNALIGNED_UINT32        /* deprecated */
+  #pragma GCC diagnostic push
+  #pragma GCC diagnostic ignored "-Wpacked"
+  #pragma GCC diagnostic ignored "-Wattributes"
+  struct __attribute__((packed)) T_UINT32 { uint32_t v; };
+  #pragma GCC diagnostic pop
+  #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+#endif
+#ifndef   __UNALIGNED_UINT16_WRITE
+  #pragma GCC diagnostic push
+  #pragma GCC diagnostic ignored "-Wpacked"
+  #pragma GCC diagnostic ignored "-Wattributes"
+  __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+  #pragma GCC diagnostic pop
+  #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef   __UNALIGNED_UINT16_READ
+  #pragma GCC diagnostic push
+  #pragma GCC diagnostic ignored "-Wpacked"
+  #pragma GCC diagnostic ignored "-Wattributes"
+  __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+  #pragma GCC diagnostic pop
+  #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+#endif
+#ifndef   __UNALIGNED_UINT32_WRITE
+  #pragma GCC diagnostic push
+  #pragma GCC diagnostic ignored "-Wpacked"
+  #pragma GCC diagnostic ignored "-Wattributes"
+  __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+  #pragma GCC diagnostic pop
+  #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef   __UNALIGNED_UINT32_READ
+  #pragma GCC diagnostic push
+  #pragma GCC diagnostic ignored "-Wpacked"
+  #pragma GCC diagnostic ignored "-Wattributes"
+  __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+  #pragma GCC diagnostic pop
+  #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+#endif
+#ifndef   __ALIGNED
+  #define __ALIGNED(x)                           __attribute__((aligned(x)))
+#endif
+#ifndef   __RESTRICT
+  #define __RESTRICT                             __restrict
+#endif
+
+
+/* ###########################  Core Function Access  ########################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+  @{
+ */
+
+/**
+  \brief   Enable IRQ Interrupts
+  \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+__STATIC_FORCEINLINE void __enable_irq(void)
+{
+  __ASM volatile ("cpsie i" : : : "memory");
+}
+
+
+/**
+  \brief   Disable IRQ Interrupts
+  \details Disables IRQ interrupts by setting the I-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+__STATIC_FORCEINLINE void __disable_irq(void)
+{
+  __ASM volatile ("cpsid i" : : : "memory");
+}
+
+
+/**
+  \brief   Get Control Register
+  \details Returns the content of the Control Register.
+  \return               Control Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_CONTROL(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, control" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Control Register (non-secure)
+  \details Returns the content of the non-secure Control Register when in secure mode.
+  \return               non-secure Control Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, control_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Control Register
+  \details Writes the given value to the Control Register.
+  \param [in]    control  Control Register value to set
+ */
+__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control)
+{
+  __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Control Register (non-secure)
+  \details Writes the given value to the non-secure Control Register when in secure state.
+  \param [in]    control  Control Register value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)
+{
+  __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");
+}
+#endif
+
+
+/**
+  \brief   Get IPSR Register
+  \details Returns the content of the IPSR Register.
+  \return               IPSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_IPSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+  return(result);
+}
+
+
+/**
+  \brief   Get APSR Register
+  \details Returns the content of the APSR Register.
+  \return               APSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_APSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+  return(result);
+}
+
+
+/**
+  \brief   Get xPSR Register
+  \details Returns the content of the xPSR Register.
+  \return               xPSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_xPSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+  return(result);
+}
+
+
+/**
+  \brief   Get Process Stack Pointer
+  \details Returns the current value of the Process Stack Pointer (PSP).
+  \return               PSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PSP(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, psp"  : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Process Stack Pointer (non-secure)
+  \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.
+  \return               PSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, psp_ns"  : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Process Stack Pointer
+  \details Assigns the given value to the Process Stack Pointer (PSP).
+  \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack)
+{
+  __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Process Stack Pointer (non-secure)
+  \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.
+  \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
+{
+  __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );
+}
+#endif
+
+
+/**
+  \brief   Get Main Stack Pointer
+  \details Returns the current value of the Main Stack Pointer (MSP).
+  \return               MSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_MSP(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, msp" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Main Stack Pointer (non-secure)
+  \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.
+  \return               MSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Main Stack Pointer
+  \details Assigns the given value to the Main Stack Pointer (MSP).
+  \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack)
+{
+  __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Main Stack Pointer (non-secure)
+  \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
+  \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
+{
+  __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );
+}
+#endif
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Stack Pointer (non-secure)
+  \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.
+  \return               SP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, sp_ns" : "=r" (result) );
+  return(result);
+}
+
+
+/**
+  \brief   Set Stack Pointer (non-secure)
+  \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.
+  \param [in]    topOfStack  Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack)
+{
+  __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : );
+}
+#endif
+
+
+/**
+  \brief   Get Priority Mask
+  \details Returns the current state of the priority mask bit from the Priority Mask Register.
+  \return               Priority Mask value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Priority Mask (non-secure)
+  \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.
+  \return               Priority Mask value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, primask_ns" : "=r" (result) :: "memory");
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Priority Mask
+  \details Assigns the given value to the Priority Mask Register.
+  \param [in]    priMask  Priority Mask
+ */
+__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask)
+{
+  __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Priority Mask (non-secure)
+  \details Assigns the given value to the non-secure Priority Mask Register when in secure state.
+  \param [in]    priMask  Priority Mask
+ */
+__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)
+{
+  __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");
+}
+#endif
+
+
+#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+/**
+  \brief   Enable FIQ
+  \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+__STATIC_FORCEINLINE void __enable_fault_irq(void)
+{
+  __ASM volatile ("cpsie f" : : : "memory");
+}
+
+
+/**
+  \brief   Disable FIQ
+  \details Disables FIQ interrupts by setting the F-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+__STATIC_FORCEINLINE void __disable_fault_irq(void)
+{
+  __ASM volatile ("cpsid f" : : : "memory");
+}
+
+
+/**
+  \brief   Get Base Priority
+  \details Returns the current value of the Base Priority register.
+  \return               Base Priority register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, basepri" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Base Priority (non-secure)
+  \details Returns the current value of the non-secure Base Priority register when in secure state.
+  \return               Base Priority register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Base Priority
+  \details Assigns the given value to the Base Priority register.
+  \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri)
+{
+  __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Base Priority (non-secure)
+  \details Assigns the given value to the non-secure Base Priority register when in secure state.
+  \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)
+{
+  __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");
+}
+#endif
+
+
+/**
+  \brief   Set Base Priority with condition
+  \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
+           or the new value increases the BASEPRI priority level.
+  \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri)
+{
+  __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");
+}
+
+
+/**
+  \brief   Get Fault Mask
+  \details Returns the current value of the Fault Mask register.
+  \return               Fault Mask register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Fault Mask (non-secure)
+  \details Returns the current value of the non-secure Fault Mask register when in secure state.
+  \return               Fault Mask register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Fault Mask
+  \details Assigns the given value to the Fault Mask register.
+  \param [in]    faultMask  Fault Mask value to set
+ */
+__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+  __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Fault Mask (non-secure)
+  \details Assigns the given value to the non-secure Fault Mask register when in secure state.
+  \param [in]    faultMask  Fault Mask value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
+{
+  __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
+
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
+
+/**
+  \brief   Get Process Stack Pointer Limit
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence zero is returned always in non-secure
+  mode.
+  
+  \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
+  \return               PSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+    // without main extensions, the non-secure PSPLIM is RAZ/WI
+  return 0U;
+#else
+  uint32_t result;
+  __ASM volatile ("MRS %0, psplim"  : "=r" (result) );
+  return result;
+#endif
+}
+
+#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Process Stack Pointer Limit (non-secure)
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence zero is returned always.
+
+  \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+  \return               PSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+  // without main extensions, the non-secure PSPLIM is RAZ/WI
+  return 0U;
+#else
+  uint32_t result;
+  __ASM volatile ("MRS %0, psplim_ns"  : "=r" (result) );
+  return result;
+#endif
+}
+#endif
+
+
+/**
+  \brief   Set Process Stack Pointer Limit
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence the write is silently ignored in non-secure
+  mode.
+  
+  \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
+  \param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+  // without main extensions, the non-secure PSPLIM is RAZ/WI
+  (void)ProcStackPtrLimit;
+#else
+  __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))
+/**
+  \brief   Set Process Stack Pointer (non-secure)
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence the write is silently ignored.
+
+  \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+  \param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+  // without main extensions, the non-secure PSPLIM is RAZ/WI
+  (void)ProcStackPtrLimit;
+#else
+  __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
+#endif
+}
+#endif
+
+
+/**
+  \brief   Get Main Stack Pointer Limit
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence zero is returned always in non-secure
+  mode.
+
+  \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
+  \return               MSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+  // without main extensions, the non-secure MSPLIM is RAZ/WI
+  return 0U;
+#else
+  uint32_t result;
+  __ASM volatile ("MRS %0, msplim" : "=r" (result) );
+  return result;
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))
+/**
+  \brief   Get Main Stack Pointer Limit (non-secure)
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence zero is returned always.
+
+  \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.
+  \return               MSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+  // without main extensions, the non-secure MSPLIM is RAZ/WI
+  return 0U;
+#else
+  uint32_t result;
+  __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );
+  return result;
+#endif
+}
+#endif
+
+
+/**
+  \brief   Set Main Stack Pointer Limit
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence the write is silently ignored in non-secure
+  mode.
+
+  \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
+  \param [in]    MainStackPtrLimit  Main Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+  // without main extensions, the non-secure MSPLIM is RAZ/WI
+  (void)MainStackPtrLimit;
+#else
+  __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))
+/**
+  \brief   Set Main Stack Pointer Limit (non-secure)
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence the write is silently ignored.
+
+  \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.
+  \param [in]    MainStackPtrLimit  Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+  // without main extensions, the non-secure MSPLIM is RAZ/WI
+  (void)MainStackPtrLimit;
+#else
+  __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));
+#endif
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
+
+
+/**
+  \brief   Get FPSCR
+  \details Returns the current value of the Floating Point Status/Control register.
+  \return               Floating Point Status/Control register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_FPSCR(void)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+#if __has_builtin(__builtin_arm_get_fpscr) 
+// Re-enable using built-in when GCC has been fixed
+// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
+  /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
+  return __builtin_arm_get_fpscr();
+#else
+  uint32_t result;
+
+  __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
+  return(result);
+#endif
+#else
+  return(0U);
+#endif
+}
+
+
+/**
+  \brief   Set FPSCR
+  \details Assigns the given value to the Floating Point Status/Control register.
+  \param [in]    fpscr  Floating Point Status/Control value to set
+ */
+__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+#if __has_builtin(__builtin_arm_set_fpscr)
+// Re-enable using built-in when GCC has been fixed
+// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
+  /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
+  __builtin_arm_set_fpscr(fpscr);
+#else
+  __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory");
+#endif
+#else
+  (void)fpscr;
+#endif
+}
+
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+/* ##########################  Core Instruction Access  ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+  Access to dedicated instructions
+  @{
+*/
+
+/* Define macros for porting to both thumb1 and thumb2.
+ * For thumb1, use low register (r0-r7), specified by constraint "l"
+ * Otherwise, use general registers, specified by constraint "r" */
+#if defined (__thumb__) && !defined (__thumb2__)
+#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
+#define __CMSIS_GCC_RW_REG(r) "+l" (r)
+#define __CMSIS_GCC_USE_REG(r) "l" (r)
+#else
+#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
+#define __CMSIS_GCC_RW_REG(r) "+r" (r)
+#define __CMSIS_GCC_USE_REG(r) "r" (r)
+#endif
+
+/**
+  \brief   No Operation
+  \details No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP()                             __ASM volatile ("nop")
+
+/**
+  \brief   Wait For Interrupt
+  \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
+ */
+#define __WFI()                             __ASM volatile ("wfi")
+
+
+/**
+  \brief   Wait For Event
+  \details Wait For Event is a hint instruction that permits the processor to enter
+           a low-power state until one of a number of events occurs.
+ */
+#define __WFE()                             __ASM volatile ("wfe")
+
+
+/**
+  \brief   Send Event
+  \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV()                             __ASM volatile ("sev")
+
+
+/**
+  \brief   Instruction Synchronization Barrier
+  \details Instruction Synchronization Barrier flushes the pipeline in the processor,
+           so that all instructions following the ISB are fetched from cache or memory,
+           after the instruction has been completed.
+ */
+__STATIC_FORCEINLINE void __ISB(void)
+{
+  __ASM volatile ("isb 0xF":::"memory");
+}
+
+
+/**
+  \brief   Data Synchronization Barrier
+  \details Acts as a special kind of Data Memory Barrier.
+           It completes when all explicit memory accesses before this instruction complete.
+ */
+__STATIC_FORCEINLINE void __DSB(void)
+{
+  __ASM volatile ("dsb 0xF":::"memory");
+}
+
+
+/**
+  \brief   Data Memory Barrier
+  \details Ensures the apparent order of the explicit memory operations before
+           and after the instruction, without ensuring their completion.
+ */
+__STATIC_FORCEINLINE void __DMB(void)
+{
+  __ASM volatile ("dmb 0xF":::"memory");
+}
+
+
+/**
+  \brief   Reverse byte order (32 bit)
+  \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+__STATIC_FORCEINLINE uint32_t __REV(uint32_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
+  return __builtin_bswap32(value);
+#else
+  uint32_t result;
+
+  __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return result;
+#endif
+}
+
+
+/**
+  \brief   Reverse byte order (16 bit)
+  \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+__STATIC_FORCEINLINE uint32_t __REV16(uint32_t value)
+{
+  uint32_t result;
+
+  __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return result;
+}
+
+
+/**
+  \brief   Reverse byte order (16 bit)
+  \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+__STATIC_FORCEINLINE int16_t __REVSH(int16_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+  return (int16_t)__builtin_bswap16(value);
+#else
+  int16_t result;
+
+  __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return result;
+#endif
+}
+
+
+/**
+  \brief   Rotate Right in unsigned value (32 bit)
+  \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+  \param [in]    op1  Value to rotate
+  \param [in]    op2  Number of Bits to rotate
+  \return               Rotated value
+ */
+__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
+{
+  op2 %= 32U;
+  if (op2 == 0U)
+  {
+    return op1;
+  }
+  return (op1 >> op2) | (op1 << (32U - op2));
+}
+
+
+/**
+  \brief   Breakpoint
+  \details Causes the processor to enter Debug state.
+           Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+  \param [in]    value  is ignored by the processor.
+                 If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value)                       __ASM volatile ("bkpt "#value)
+
+
+/**
+  \brief   Reverse bit order of value
+  \details Reverses the bit order of the given value.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value)
+{
+  uint32_t result;
+
+#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+   __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
+#else
+  uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */
+
+  result = value;                      /* r will be reversed bits of v; first get LSB of v */
+  for (value >>= 1U; value != 0U; value >>= 1U)
+  {
+    result <<= 1U;
+    result |= value & 1U;
+    s--;
+  }
+  result <<= s;                        /* shift when v's highest bits are zero */
+#endif
+  return result;
+}
+
+
+/**
+  \brief   Count leading zeros
+  \details Counts the number of leading zeros of a data value.
+  \param [in]  value  Value to count the leading zeros
+  \return             number of leading zeros in value
+ */
+#define __CLZ             (uint8_t)__builtin_clz
+
+
+#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
+/**
+  \brief   LDR Exclusive (8 bit)
+  \details Executes a exclusive LDR instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+   __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+   __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+   return ((uint8_t) result);    /* Add explicit type cast here */
+}
+
+
+/**
+  \brief   LDR Exclusive (16 bit)
+  \details Executes a exclusive LDR instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+   __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+   __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+   return ((uint16_t) result);    /* Add explicit type cast here */
+}
+
+
+/**
+  \brief   LDR Exclusive (32 bit)
+  \details Executes a exclusive LDR instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
+   return(result);
+}
+
+
+/**
+  \brief   STR Exclusive (8 bit)
+  \details Executes a exclusive STR instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
+{
+   uint32_t result;
+
+   __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
+   return(result);
+}
+
+
+/**
+  \brief   STR Exclusive (16 bit)
+  \details Executes a exclusive STR instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
+{
+   uint32_t result;
+
+   __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
+   return(result);
+}
+
+
+/**
+  \brief   STR Exclusive (32 bit)
+  \details Executes a exclusive STR instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
+{
+   uint32_t result;
+
+   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+   return(result);
+}
+
+
+/**
+  \brief   Remove the exclusive lock
+  \details Removes the exclusive lock which is created by LDREX.
+ */
+__STATIC_FORCEINLINE void __CLREX(void)
+{
+  __ASM volatile ("clrex" ::: "memory");
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
+
+
+#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+/**
+  \brief   Signed Saturate
+  \details Saturates a signed value.
+  \param [in]  ARG1  Value to be saturated
+  \param [in]  ARG2  Bit position to saturate to (1..32)
+  \return             Saturated value
+ */
+#define __SSAT(ARG1,ARG2) \
+__extension__ \
+({                          \
+  int32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("ssat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+
+/**
+  \brief   Unsigned Saturate
+  \details Saturates an unsigned value.
+  \param [in]  ARG1  Value to be saturated
+  \param [in]  ARG2  Bit position to saturate to (0..31)
+  \return             Saturated value
+ */
+#define __USAT(ARG1,ARG2) \
+ __extension__ \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("usat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+
+/**
+  \brief   Rotate Right with Extend (32 bit)
+  \details Moves each bit of a bitstring right by one bit.
+           The carry input is shifted in at the left end of the bitstring.
+  \param [in]    value  Value to rotate
+  \return               Rotated value
+ */
+__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value)
+{
+  uint32_t result;
+
+  __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return(result);
+}
+
+
+/**
+  \brief   LDRT Unprivileged (8 bit)
+  \details Executes a Unprivileged LDRT instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+   __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+   __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" );
+#endif
+   return ((uint8_t) result);    /* Add explicit type cast here */
+}
+
+
+/**
+  \brief   LDRT Unprivileged (16 bit)
+  \details Executes a Unprivileged LDRT instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+   __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+   __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" );
+#endif
+   return ((uint16_t) result);    /* Add explicit type cast here */
+}
+
+
+/**
+  \brief   LDRT Unprivileged (32 bit)
+  \details Executes a Unprivileged LDRT instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) );
+   return(result);
+}
+
+
+/**
+  \brief   STRT Unprivileged (8 bit)
+  \details Executes a Unprivileged STRT instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)
+{
+   __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   STRT Unprivileged (16 bit)
+  \details Executes a Unprivileged STRT instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)
+{
+   __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   STRT Unprivileged (32 bit)
+  \details Executes a Unprivileged STRT instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr)
+{
+   __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) );
+}
+
+#else  /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
+
+/**
+  \brief   Signed Saturate
+  \details Saturates a signed value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (1..32)
+  \return             Saturated value
+ */
+__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat)
+{
+  if ((sat >= 1U) && (sat <= 32U))
+  {
+    const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
+    const int32_t min = -1 - max ;
+    if (val > max)
+    {
+      return max;
+    }
+    else if (val < min)
+    {
+      return min;
+    }
+  }
+  return val;
+}
+
+/**
+  \brief   Unsigned Saturate
+  \details Saturates an unsigned value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (0..31)
+  \return             Saturated value
+ */
+__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat)
+{
+  if (sat <= 31U)
+  {
+    const uint32_t max = ((1U << sat) - 1U);
+    if (val > (int32_t)max)
+    {
+      return max;
+    }
+    else if (val < 0)
+    {
+      return 0U;
+    }
+  }
+  return (uint32_t)val;
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
+
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
+/**
+  \brief   Load-Acquire (8 bit)
+  \details Executes a LDAB instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) );
+   return ((uint8_t) result);
+}
+
+
+/**
+  \brief   Load-Acquire (16 bit)
+  \details Executes a LDAH instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) );
+   return ((uint16_t) result);
+}
+
+
+/**
+  \brief   Load-Acquire (32 bit)
+  \details Executes a LDA instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr)
+{
+    uint32_t result;
+
+   __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) );
+   return(result);
+}
+
+
+/**
+  \brief   Store-Release (8 bit)
+  \details Executes a STLB instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr)
+{
+   __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   Store-Release (16 bit)
+  \details Executes a STLH instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr)
+{
+   __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   Store-Release (32 bit)
+  \details Executes a STL instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr)
+{
+   __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   Load-Acquire Exclusive (8 bit)
+  \details Executes a LDAB exclusive instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) );
+   return ((uint8_t) result);
+}
+
+
+/**
+  \brief   Load-Acquire Exclusive (16 bit)
+  \details Executes a LDAH exclusive instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) );
+   return ((uint16_t) result);
+}
+
+
+/**
+  \brief   Load-Acquire Exclusive (32 bit)
+  \details Executes a LDA exclusive instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) );
+   return(result);
+}
+
+
+/**
+  \brief   Store-Release Exclusive (8 bit)
+  \details Executes a STLB exclusive instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr)
+{
+   uint32_t result;
+
+   __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) );
+   return(result);
+}
+
+
+/**
+  \brief   Store-Release Exclusive (16 bit)
+  \details Executes a STLH exclusive instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr)
+{
+   uint32_t result;
+
+   __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) );
+   return(result);
+}
+
+
+/**
+  \brief   Store-Release Exclusive (32 bit)
+  \details Executes a STL exclusive instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr)
+{
+   uint32_t result;
+
+   __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) );
+   return(result);
+}
+
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+
+/* ###################  Compiler specific Intrinsics  ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+  Access to dedicated SIMD instructions
+  @{
+*/
+
+#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1))
+
+__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+
+__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+
+__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+#define __SSAT16(ARG1,ARG2) \
+({                          \
+  int32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+#define __USAT16(ARG1,ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("usat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1)
+{
+  uint32_t result;
+
+  __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1)
+{
+  uint32_t result;
+
+  __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUAD  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   /* Little endian */
+  __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               /* Big endian */
+  __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   /* Little endian */
+  __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               /* Big endian */
+  __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUSD  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   /* Little endian */
+  __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               /* Big endian */
+  __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   /* Little endian */
+  __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               /* Big endian */
+  __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint32_t __SEL  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE  int32_t __QADD( int32_t op1,  int32_t op2)
+{
+  int32_t result;
+
+  __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE  int32_t __QSUB( int32_t op1,  int32_t op2)
+{
+  int32_t result;
+
+  __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+#if 0
+#define __PKHBT(ARG1,ARG2,ARG3) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+  __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
+  __RES; \
+ })
+
+#define __PKHTB(ARG1,ARG2,ARG3) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+  if (ARG3 == 0) \
+    __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2)  ); \
+  else \
+    __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
+  __RES; \
+ })
+#endif
+
+#define __PKHBT(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0x0000FFFFUL) |  \
+                                           ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL)  )
+
+#define __PKHTB(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0xFFFF0000UL) |  \
+                                           ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)  )
+
+__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
+{
+ int32_t result;
+
+ __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r"  (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+#endif /* (__ARM_FEATURE_DSP == 1) */
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#pragma GCC diagnostic pop
+
+#endif /* __CMSIS_GCC_H */
diff --git a/Drivers/CMSIS/Include/cmsis_iccarm.h b/Drivers/CMSIS/Include/cmsis_iccarm.h
new file mode 100644
index 0000000..3c90a2c
--- /dev/null
+++ b/Drivers/CMSIS/Include/cmsis_iccarm.h
@@ -0,0 +1,935 @@
+/**************************************************************************//**
+ * @file     cmsis_iccarm.h
+ * @brief    CMSIS compiler ICCARM (IAR Compiler for Arm) header file
+ * @version  V5.0.7
+ * @date     19. June 2018
+ ******************************************************************************/
+
+//------------------------------------------------------------------------------
+//
+// Copyright (c) 2017-2018 IAR Systems
+//
+// Licensed under the Apache License, Version 2.0 (the "License")
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+//------------------------------------------------------------------------------
+
+
+#ifndef __CMSIS_ICCARM_H__
+#define __CMSIS_ICCARM_H__
+
+#ifndef __ICCARM__
+  #error This file should only be compiled by ICCARM
+#endif
+
+#pragma system_include
+
+#define __IAR_FT _Pragma("inline=forced") __intrinsic
+
+#if (__VER__ >= 8000000)
+  #define __ICCARM_V8 1
+#else
+  #define __ICCARM_V8 0
+#endif
+
+#ifndef __ALIGNED
+  #if __ICCARM_V8
+    #define __ALIGNED(x) __attribute__((aligned(x)))
+  #elif (__VER__ >= 7080000)
+    /* Needs IAR language extensions */
+    #define __ALIGNED(x) __attribute__((aligned(x)))
+  #else
+    #warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored.
+    #define __ALIGNED(x)
+  #endif
+#endif
+
+
+/* Define compiler macros for CPU architecture, used in CMSIS 5.
+ */
+#if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__
+/* Macros already defined */
+#else
+  #if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__)
+    #define __ARM_ARCH_8M_MAIN__ 1
+  #elif defined(__ARM8M_BASELINE__)
+    #define __ARM_ARCH_8M_BASE__ 1
+  #elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M'
+    #if __ARM_ARCH == 6
+      #define __ARM_ARCH_6M__ 1
+    #elif __ARM_ARCH == 7
+      #if __ARM_FEATURE_DSP
+        #define __ARM_ARCH_7EM__ 1
+      #else
+        #define __ARM_ARCH_7M__ 1
+      #endif
+    #endif /* __ARM_ARCH */
+  #endif /* __ARM_ARCH_PROFILE == 'M' */
+#endif
+
+/* Alternativ core deduction for older ICCARM's */
+#if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \
+    !defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__)
+  #if defined(__ARM6M__) && (__CORE__ == __ARM6M__)
+    #define __ARM_ARCH_6M__ 1
+  #elif defined(__ARM7M__) && (__CORE__ == __ARM7M__)
+    #define __ARM_ARCH_7M__ 1
+  #elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__)
+    #define __ARM_ARCH_7EM__  1
+  #elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__)
+    #define __ARM_ARCH_8M_BASE__ 1
+  #elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__)
+    #define __ARM_ARCH_8M_MAIN__ 1
+  #elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__)
+    #define __ARM_ARCH_8M_MAIN__ 1
+  #else
+    #error "Unknown target."
+  #endif
+#endif
+
+
+
+#if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1
+  #define __IAR_M0_FAMILY  1
+#elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1
+  #define __IAR_M0_FAMILY  1
+#else
+  #define __IAR_M0_FAMILY  0
+#endif
+
+
+#ifndef __ASM
+  #define __ASM __asm
+#endif
+
+#ifndef __INLINE
+  #define __INLINE inline
+#endif
+
+#ifndef   __NO_RETURN
+  #if __ICCARM_V8
+    #define __NO_RETURN __attribute__((__noreturn__))
+  #else
+    #define __NO_RETURN _Pragma("object_attribute=__noreturn")
+  #endif
+#endif
+
+#ifndef   __PACKED
+  #if __ICCARM_V8
+    #define __PACKED __attribute__((packed, aligned(1)))
+  #else
+    /* Needs IAR language extensions */
+    #define __PACKED __packed
+  #endif
+#endif
+
+#ifndef   __PACKED_STRUCT
+  #if __ICCARM_V8
+    #define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
+  #else
+    /* Needs IAR language extensions */
+    #define __PACKED_STRUCT __packed struct
+  #endif
+#endif
+
+#ifndef   __PACKED_UNION
+  #if __ICCARM_V8
+    #define __PACKED_UNION union __attribute__((packed, aligned(1)))
+  #else
+    /* Needs IAR language extensions */
+    #define __PACKED_UNION __packed union
+  #endif
+#endif
+
+#ifndef   __RESTRICT
+  #define __RESTRICT            __restrict
+#endif
+
+#ifndef   __STATIC_INLINE
+  #define __STATIC_INLINE       static inline
+#endif
+
+#ifndef   __FORCEINLINE
+  #define __FORCEINLINE         _Pragma("inline=forced")
+#endif
+
+#ifndef   __STATIC_FORCEINLINE
+  #define __STATIC_FORCEINLINE  __FORCEINLINE __STATIC_INLINE
+#endif
+
+#ifndef __UNALIGNED_UINT16_READ
+#pragma language=save
+#pragma language=extended
+__IAR_FT uint16_t __iar_uint16_read(void const *ptr)
+{
+  return *(__packed uint16_t*)(ptr);
+}
+#pragma language=restore
+#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR)
+#endif
+
+
+#ifndef __UNALIGNED_UINT16_WRITE
+#pragma language=save
+#pragma language=extended
+__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val)
+{
+  *(__packed uint16_t*)(ptr) = val;;
+}
+#pragma language=restore
+#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL)
+#endif
+
+#ifndef __UNALIGNED_UINT32_READ
+#pragma language=save
+#pragma language=extended
+__IAR_FT uint32_t __iar_uint32_read(void const *ptr)
+{
+  return *(__packed uint32_t*)(ptr);
+}
+#pragma language=restore
+#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR)
+#endif
+
+#ifndef __UNALIGNED_UINT32_WRITE
+#pragma language=save
+#pragma language=extended
+__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val)
+{
+  *(__packed uint32_t*)(ptr) = val;;
+}
+#pragma language=restore
+#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL)
+#endif
+
+#ifndef __UNALIGNED_UINT32   /* deprecated */
+#pragma language=save
+#pragma language=extended
+__packed struct  __iar_u32 { uint32_t v; };
+#pragma language=restore
+#define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v)
+#endif
+
+#ifndef   __USED
+  #if __ICCARM_V8
+    #define __USED __attribute__((used))
+  #else
+    #define __USED _Pragma("__root")
+  #endif
+#endif
+
+#ifndef   __WEAK
+  #if __ICCARM_V8
+    #define __WEAK __attribute__((weak))
+  #else
+    #define __WEAK _Pragma("__weak")
+  #endif
+#endif
+
+
+#ifndef __ICCARM_INTRINSICS_VERSION__
+  #define __ICCARM_INTRINSICS_VERSION__  0
+#endif
+
+#if __ICCARM_INTRINSICS_VERSION__ == 2
+
+  #if defined(__CLZ)
+    #undef __CLZ
+  #endif
+  #if defined(__REVSH)
+    #undef __REVSH
+  #endif
+  #if defined(__RBIT)
+    #undef __RBIT
+  #endif
+  #if defined(__SSAT)
+    #undef __SSAT
+  #endif
+  #if defined(__USAT)
+    #undef __USAT
+  #endif
+
+  #include "iccarm_builtin.h"
+
+  #define __disable_fault_irq __iar_builtin_disable_fiq
+  #define __disable_irq       __iar_builtin_disable_interrupt
+  #define __enable_fault_irq  __iar_builtin_enable_fiq
+  #define __enable_irq        __iar_builtin_enable_interrupt
+  #define __arm_rsr           __iar_builtin_rsr
+  #define __arm_wsr           __iar_builtin_wsr
+
+
+  #define __get_APSR()                (__arm_rsr("APSR"))
+  #define __get_BASEPRI()             (__arm_rsr("BASEPRI"))
+  #define __get_CONTROL()             (__arm_rsr("CONTROL"))
+  #define __get_FAULTMASK()           (__arm_rsr("FAULTMASK"))
+
+  #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+       (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+    #define __get_FPSCR()             (__arm_rsr("FPSCR"))
+    #define __set_FPSCR(VALUE)        (__arm_wsr("FPSCR", (VALUE)))
+  #else
+    #define __get_FPSCR()             ( 0 )
+    #define __set_FPSCR(VALUE)        ((void)VALUE)
+  #endif
+
+  #define __get_IPSR()                (__arm_rsr("IPSR"))
+  #define __get_MSP()                 (__arm_rsr("MSP"))
+  #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+       (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+    // without main extensions, the non-secure MSPLIM is RAZ/WI
+    #define __get_MSPLIM()            (0U)
+  #else
+    #define __get_MSPLIM()            (__arm_rsr("MSPLIM"))
+  #endif
+  #define __get_PRIMASK()             (__arm_rsr("PRIMASK"))
+  #define __get_PSP()                 (__arm_rsr("PSP"))
+
+  #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+       (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+    // without main extensions, the non-secure PSPLIM is RAZ/WI
+    #define __get_PSPLIM()            (0U)
+  #else
+    #define __get_PSPLIM()            (__arm_rsr("PSPLIM"))
+  #endif
+
+  #define __get_xPSR()                (__arm_rsr("xPSR"))
+
+  #define __set_BASEPRI(VALUE)        (__arm_wsr("BASEPRI", (VALUE)))
+  #define __set_BASEPRI_MAX(VALUE)    (__arm_wsr("BASEPRI_MAX", (VALUE)))
+  #define __set_CONTROL(VALUE)        (__arm_wsr("CONTROL", (VALUE)))
+  #define __set_FAULTMASK(VALUE)      (__arm_wsr("FAULTMASK", (VALUE)))
+  #define __set_MSP(VALUE)            (__arm_wsr("MSP", (VALUE)))
+
+  #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+       (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+    // without main extensions, the non-secure MSPLIM is RAZ/WI
+    #define __set_MSPLIM(VALUE)       ((void)(VALUE))
+  #else
+    #define __set_MSPLIM(VALUE)       (__arm_wsr("MSPLIM", (VALUE)))
+  #endif
+  #define __set_PRIMASK(VALUE)        (__arm_wsr("PRIMASK", (VALUE)))
+  #define __set_PSP(VALUE)            (__arm_wsr("PSP", (VALUE)))
+  #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+       (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+    // without main extensions, the non-secure PSPLIM is RAZ/WI
+    #define __set_PSPLIM(VALUE)       ((void)(VALUE))
+  #else
+    #define __set_PSPLIM(VALUE)       (__arm_wsr("PSPLIM", (VALUE)))
+  #endif
+
+  #define __TZ_get_CONTROL_NS()       (__arm_rsr("CONTROL_NS"))
+  #define __TZ_set_CONTROL_NS(VALUE)  (__arm_wsr("CONTROL_NS", (VALUE)))
+  #define __TZ_get_PSP_NS()           (__arm_rsr("PSP_NS"))
+  #define __TZ_set_PSP_NS(VALUE)      (__arm_wsr("PSP_NS", (VALUE)))
+  #define __TZ_get_MSP_NS()           (__arm_rsr("MSP_NS"))
+  #define __TZ_set_MSP_NS(VALUE)      (__arm_wsr("MSP_NS", (VALUE)))
+  #define __TZ_get_SP_NS()            (__arm_rsr("SP_NS"))
+  #define __TZ_set_SP_NS(VALUE)       (__arm_wsr("SP_NS", (VALUE)))
+  #define __TZ_get_PRIMASK_NS()       (__arm_rsr("PRIMASK_NS"))
+  #define __TZ_set_PRIMASK_NS(VALUE)  (__arm_wsr("PRIMASK_NS", (VALUE)))
+  #define __TZ_get_BASEPRI_NS()       (__arm_rsr("BASEPRI_NS"))
+  #define __TZ_set_BASEPRI_NS(VALUE)  (__arm_wsr("BASEPRI_NS", (VALUE)))
+  #define __TZ_get_FAULTMASK_NS()     (__arm_rsr("FAULTMASK_NS"))
+  #define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE)))
+
+  #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+       (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+    // without main extensions, the non-secure PSPLIM is RAZ/WI
+    #define __TZ_get_PSPLIM_NS()      (0U)
+    #define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE))
+  #else
+    #define __TZ_get_PSPLIM_NS()      (__arm_rsr("PSPLIM_NS"))
+    #define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE)))
+  #endif
+
+  #define __TZ_get_MSPLIM_NS()        (__arm_rsr("MSPLIM_NS"))
+  #define __TZ_set_MSPLIM_NS(VALUE)   (__arm_wsr("MSPLIM_NS", (VALUE)))
+
+  #define __NOP     __iar_builtin_no_operation
+
+  #define __CLZ     __iar_builtin_CLZ
+  #define __CLREX   __iar_builtin_CLREX
+
+  #define __DMB     __iar_builtin_DMB
+  #define __DSB     __iar_builtin_DSB
+  #define __ISB     __iar_builtin_ISB
+
+  #define __LDREXB  __iar_builtin_LDREXB
+  #define __LDREXH  __iar_builtin_LDREXH
+  #define __LDREXW  __iar_builtin_LDREX
+
+  #define __RBIT    __iar_builtin_RBIT
+  #define __REV     __iar_builtin_REV
+  #define __REV16   __iar_builtin_REV16
+
+  __IAR_FT int16_t __REVSH(int16_t val)
+  {
+    return (int16_t) __iar_builtin_REVSH(val);
+  }
+
+  #define __ROR     __iar_builtin_ROR
+  #define __RRX     __iar_builtin_RRX
+
+  #define __SEV     __iar_builtin_SEV
+
+  #if !__IAR_M0_FAMILY
+    #define __SSAT    __iar_builtin_SSAT
+  #endif
+
+  #define __STREXB  __iar_builtin_STREXB
+  #define __STREXH  __iar_builtin_STREXH
+  #define __STREXW  __iar_builtin_STREX
+
+  #if !__IAR_M0_FAMILY
+    #define __USAT    __iar_builtin_USAT
+  #endif
+
+  #define __WFE     __iar_builtin_WFE
+  #define __WFI     __iar_builtin_WFI
+
+  #if __ARM_MEDIA__
+    #define __SADD8   __iar_builtin_SADD8
+    #define __QADD8   __iar_builtin_QADD8
+    #define __SHADD8  __iar_builtin_SHADD8
+    #define __UADD8   __iar_builtin_UADD8
+    #define __UQADD8  __iar_builtin_UQADD8
+    #define __UHADD8  __iar_builtin_UHADD8
+    #define __SSUB8   __iar_builtin_SSUB8
+    #define __QSUB8   __iar_builtin_QSUB8
+    #define __SHSUB8  __iar_builtin_SHSUB8
+    #define __USUB8   __iar_builtin_USUB8
+    #define __UQSUB8  __iar_builtin_UQSUB8
+    #define __UHSUB8  __iar_builtin_UHSUB8
+    #define __SADD16  __iar_builtin_SADD16
+    #define __QADD16  __iar_builtin_QADD16
+    #define __SHADD16 __iar_builtin_SHADD16
+    #define __UADD16  __iar_builtin_UADD16
+    #define __UQADD16 __iar_builtin_UQADD16
+    #define __UHADD16 __iar_builtin_UHADD16
+    #define __SSUB16  __iar_builtin_SSUB16
+    #define __QSUB16  __iar_builtin_QSUB16
+    #define __SHSUB16 __iar_builtin_SHSUB16
+    #define __USUB16  __iar_builtin_USUB16
+    #define __UQSUB16 __iar_builtin_UQSUB16
+    #define __UHSUB16 __iar_builtin_UHSUB16
+    #define __SASX    __iar_builtin_SASX
+    #define __QASX    __iar_builtin_QASX
+    #define __SHASX   __iar_builtin_SHASX
+    #define __UASX    __iar_builtin_UASX
+    #define __UQASX   __iar_builtin_UQASX
+    #define __UHASX   __iar_builtin_UHASX
+    #define __SSAX    __iar_builtin_SSAX
+    #define __QSAX    __iar_builtin_QSAX
+    #define __SHSAX   __iar_builtin_SHSAX
+    #define __USAX    __iar_builtin_USAX
+    #define __UQSAX   __iar_builtin_UQSAX
+    #define __UHSAX   __iar_builtin_UHSAX
+    #define __USAD8   __iar_builtin_USAD8
+    #define __USADA8  __iar_builtin_USADA8
+    #define __SSAT16  __iar_builtin_SSAT16
+    #define __USAT16  __iar_builtin_USAT16
+    #define __UXTB16  __iar_builtin_UXTB16
+    #define __UXTAB16 __iar_builtin_UXTAB16
+    #define __SXTB16  __iar_builtin_SXTB16
+    #define __SXTAB16 __iar_builtin_SXTAB16
+    #define __SMUAD   __iar_builtin_SMUAD
+    #define __SMUADX  __iar_builtin_SMUADX
+    #define __SMMLA   __iar_builtin_SMMLA
+    #define __SMLAD   __iar_builtin_SMLAD
+    #define __SMLADX  __iar_builtin_SMLADX
+    #define __SMLALD  __iar_builtin_SMLALD
+    #define __SMLALDX __iar_builtin_SMLALDX
+    #define __SMUSD   __iar_builtin_SMUSD
+    #define __SMUSDX  __iar_builtin_SMUSDX
+    #define __SMLSD   __iar_builtin_SMLSD
+    #define __SMLSDX  __iar_builtin_SMLSDX
+    #define __SMLSLD  __iar_builtin_SMLSLD
+    #define __SMLSLDX __iar_builtin_SMLSLDX
+    #define __SEL     __iar_builtin_SEL
+    #define __QADD    __iar_builtin_QADD
+    #define __QSUB    __iar_builtin_QSUB
+    #define __PKHBT   __iar_builtin_PKHBT
+    #define __PKHTB   __iar_builtin_PKHTB
+  #endif
+
+#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */
+
+  #if __IAR_M0_FAMILY
+   /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */
+    #define __CLZ  __cmsis_iar_clz_not_active
+    #define __SSAT __cmsis_iar_ssat_not_active
+    #define __USAT __cmsis_iar_usat_not_active
+    #define __RBIT __cmsis_iar_rbit_not_active
+    #define __get_APSR  __cmsis_iar_get_APSR_not_active
+  #endif
+
+
+  #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+         (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     ))
+    #define __get_FPSCR __cmsis_iar_get_FPSR_not_active
+    #define __set_FPSCR __cmsis_iar_set_FPSR_not_active
+  #endif
+
+  #ifdef __INTRINSICS_INCLUDED
+  #error intrinsics.h is already included previously!
+  #endif
+
+  #include <intrinsics.h>
+
+  #if __IAR_M0_FAMILY
+   /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */
+    #undef __CLZ
+    #undef __SSAT
+    #undef __USAT
+    #undef __RBIT
+    #undef __get_APSR
+
+    __STATIC_INLINE uint8_t __CLZ(uint32_t data)
+    {
+      if (data == 0U) { return 32U; }
+
+      uint32_t count = 0U;
+      uint32_t mask = 0x80000000U;
+
+      while ((data & mask) == 0U)
+      {
+        count += 1U;
+        mask = mask >> 1U;
+      }
+      return count;
+    }
+
+    __STATIC_INLINE uint32_t __RBIT(uint32_t v)
+    {
+      uint8_t sc = 31U;
+      uint32_t r = v;
+      for (v >>= 1U; v; v >>= 1U)
+      {
+        r <<= 1U;
+        r |= v & 1U;
+        sc--;
+      }
+      return (r << sc);
+    }
+
+    __STATIC_INLINE  uint32_t __get_APSR(void)
+    {
+      uint32_t res;
+      __asm("MRS      %0,APSR" : "=r" (res));
+      return res;
+    }
+
+  #endif
+
+  #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+         (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     ))
+    #undef __get_FPSCR
+    #undef __set_FPSCR
+    #define __get_FPSCR()       (0)
+    #define __set_FPSCR(VALUE)  ((void)VALUE)
+  #endif
+
+  #pragma diag_suppress=Pe940
+  #pragma diag_suppress=Pe177
+
+  #define __enable_irq    __enable_interrupt
+  #define __disable_irq   __disable_interrupt
+  #define __NOP           __no_operation
+
+  #define __get_xPSR      __get_PSR
+
+  #if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0)
+
+    __IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr)
+    {
+      return __LDREX((unsigned long *)ptr);
+    }
+
+    __IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr)
+    {
+      return __STREX(value, (unsigned long *)ptr);
+    }
+  #endif
+
+
+  /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */
+  #if (__CORTEX_M >= 0x03)
+
+    __IAR_FT uint32_t __RRX(uint32_t value)
+    {
+      uint32_t result;
+      __ASM("RRX      %0, %1" : "=r"(result) : "r" (value) : "cc");
+      return(result);
+    }
+
+    __IAR_FT void __set_BASEPRI_MAX(uint32_t value)
+    {
+      __asm volatile("MSR      BASEPRI_MAX,%0"::"r" (value));
+    }
+
+
+    #define __enable_fault_irq  __enable_fiq
+    #define __disable_fault_irq __disable_fiq
+
+
+  #endif /* (__CORTEX_M >= 0x03) */
+
+  __IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2)
+  {
+    return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2));
+  }
+
+  #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+       (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
+
+   __IAR_FT uint32_t __get_MSPLIM(void)
+    {
+      uint32_t res;
+    #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+         (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))
+      // without main extensions, the non-secure MSPLIM is RAZ/WI
+      res = 0U;
+    #else
+      __asm volatile("MRS      %0,MSPLIM" : "=r" (res));
+    #endif
+      return res;
+    }
+
+    __IAR_FT void   __set_MSPLIM(uint32_t value)
+    {
+    #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+         (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))
+      // without main extensions, the non-secure MSPLIM is RAZ/WI
+      (void)value;
+    #else
+      __asm volatile("MSR      MSPLIM,%0" :: "r" (value));
+    #endif
+    }
+
+    __IAR_FT uint32_t __get_PSPLIM(void)
+    {
+      uint32_t res;
+    #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+         (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))
+      // without main extensions, the non-secure PSPLIM is RAZ/WI
+      res = 0U;
+    #else
+      __asm volatile("MRS      %0,PSPLIM" : "=r" (res));
+    #endif
+      return res;
+    }
+
+    __IAR_FT void   __set_PSPLIM(uint32_t value)
+    {
+    #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+         (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))
+      // without main extensions, the non-secure PSPLIM is RAZ/WI
+      (void)value;
+    #else
+      __asm volatile("MSR      PSPLIM,%0" :: "r" (value));
+    #endif
+    }
+
+    __IAR_FT uint32_t __TZ_get_CONTROL_NS(void)
+    {
+      uint32_t res;
+      __asm volatile("MRS      %0,CONTROL_NS" : "=r" (res));
+      return res;
+    }
+
+    __IAR_FT void   __TZ_set_CONTROL_NS(uint32_t value)
+    {
+      __asm volatile("MSR      CONTROL_NS,%0" :: "r" (value));
+    }
+
+    __IAR_FT uint32_t   __TZ_get_PSP_NS(void)
+    {
+      uint32_t res;
+      __asm volatile("MRS      %0,PSP_NS" : "=r" (res));
+      return res;
+    }
+
+    __IAR_FT void   __TZ_set_PSP_NS(uint32_t value)
+    {
+      __asm volatile("MSR      PSP_NS,%0" :: "r" (value));
+    }
+
+    __IAR_FT uint32_t   __TZ_get_MSP_NS(void)
+    {
+      uint32_t res;
+      __asm volatile("MRS      %0,MSP_NS" : "=r" (res));
+      return res;
+    }
+
+    __IAR_FT void   __TZ_set_MSP_NS(uint32_t value)
+    {
+      __asm volatile("MSR      MSP_NS,%0" :: "r" (value));
+    }
+
+    __IAR_FT uint32_t   __TZ_get_SP_NS(void)
+    {
+      uint32_t res;
+      __asm volatile("MRS      %0,SP_NS" : "=r" (res));
+      return res;
+    }
+    __IAR_FT void   __TZ_set_SP_NS(uint32_t value)
+    {
+      __asm volatile("MSR      SP_NS,%0" :: "r" (value));
+    }
+
+    __IAR_FT uint32_t   __TZ_get_PRIMASK_NS(void)
+    {
+      uint32_t res;
+      __asm volatile("MRS      %0,PRIMASK_NS" : "=r" (res));
+      return res;
+    }
+
+    __IAR_FT void   __TZ_set_PRIMASK_NS(uint32_t value)
+    {
+      __asm volatile("MSR      PRIMASK_NS,%0" :: "r" (value));
+    }
+
+    __IAR_FT uint32_t   __TZ_get_BASEPRI_NS(void)
+    {
+      uint32_t res;
+      __asm volatile("MRS      %0,BASEPRI_NS" : "=r" (res));
+      return res;
+    }
+
+    __IAR_FT void   __TZ_set_BASEPRI_NS(uint32_t value)
+    {
+      __asm volatile("MSR      BASEPRI_NS,%0" :: "r" (value));
+    }
+
+    __IAR_FT uint32_t   __TZ_get_FAULTMASK_NS(void)
+    {
+      uint32_t res;
+      __asm volatile("MRS      %0,FAULTMASK_NS" : "=r" (res));
+      return res;
+    }
+
+    __IAR_FT void   __TZ_set_FAULTMASK_NS(uint32_t value)
+    {
+      __asm volatile("MSR      FAULTMASK_NS,%0" :: "r" (value));
+    }
+
+    __IAR_FT uint32_t   __TZ_get_PSPLIM_NS(void)
+    {
+      uint32_t res;
+    #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+         (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))
+      // without main extensions, the non-secure PSPLIM is RAZ/WI
+      res = 0U;
+    #else
+      __asm volatile("MRS      %0,PSPLIM_NS" : "=r" (res));
+    #endif
+      return res;
+    }
+
+    __IAR_FT void   __TZ_set_PSPLIM_NS(uint32_t value)
+    {
+    #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+         (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))
+      // without main extensions, the non-secure PSPLIM is RAZ/WI
+      (void)value;
+    #else
+      __asm volatile("MSR      PSPLIM_NS,%0" :: "r" (value));
+    #endif
+    }
+
+    __IAR_FT uint32_t   __TZ_get_MSPLIM_NS(void)
+    {
+      uint32_t res;
+      __asm volatile("MRS      %0,MSPLIM_NS" : "=r" (res));
+      return res;
+    }
+
+    __IAR_FT void   __TZ_set_MSPLIM_NS(uint32_t value)
+    {
+      __asm volatile("MSR      MSPLIM_NS,%0" :: "r" (value));
+    }
+
+  #endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */
+
+#endif   /* __ICCARM_INTRINSICS_VERSION__ == 2 */
+
+#define __BKPT(value)    __asm volatile ("BKPT     %0" : : "i"(value))
+
+#if __IAR_M0_FAMILY
+  __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
+  {
+    if ((sat >= 1U) && (sat <= 32U))
+    {
+      const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
+      const int32_t min = -1 - max ;
+      if (val > max)
+      {
+        return max;
+      }
+      else if (val < min)
+      {
+        return min;
+      }
+    }
+    return val;
+  }
+
+  __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
+  {
+    if (sat <= 31U)
+    {
+      const uint32_t max = ((1U << sat) - 1U);
+      if (val > (int32_t)max)
+      {
+        return max;
+      }
+      else if (val < 0)
+      {
+        return 0U;
+      }
+    }
+    return (uint32_t)val;
+  }
+#endif
+
+#if (__CORTEX_M >= 0x03)   /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */
+
+  __IAR_FT uint8_t __LDRBT(volatile uint8_t *addr)
+  {
+    uint32_t res;
+    __ASM("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
+    return ((uint8_t)res);
+  }
+
+  __IAR_FT uint16_t __LDRHT(volatile uint16_t *addr)
+  {
+    uint32_t res;
+    __ASM("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
+    return ((uint16_t)res);
+  }
+
+  __IAR_FT uint32_t __LDRT(volatile uint32_t *addr)
+  {
+    uint32_t res;
+    __ASM("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
+    return res;
+  }
+
+  __IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr)
+  {
+    __ASM("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");
+  }
+
+  __IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr)
+  {
+    __ASM("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");
+  }
+
+  __IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr)
+  {
+    __ASM("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory");
+  }
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
+
+
+  __IAR_FT uint8_t __LDAB(volatile uint8_t *ptr)
+  {
+    uint32_t res;
+    __ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+    return ((uint8_t)res);
+  }
+
+  __IAR_FT uint16_t __LDAH(volatile uint16_t *ptr)
+  {
+    uint32_t res;
+    __ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+    return ((uint16_t)res);
+  }
+
+  __IAR_FT uint32_t __LDA(volatile uint32_t *ptr)
+  {
+    uint32_t res;
+    __ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+    return res;
+  }
+
+  __IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr)
+  {
+    __ASM volatile ("STLB %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
+  }
+
+  __IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr)
+  {
+    __ASM volatile ("STLH %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
+  }
+
+  __IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr)
+  {
+    __ASM volatile ("STL %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
+  }
+
+  __IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr)
+  {
+    uint32_t res;
+    __ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+    return ((uint8_t)res);
+  }
+
+  __IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr)
+  {
+    uint32_t res;
+    __ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+    return ((uint16_t)res);
+  }
+
+  __IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr)
+  {
+    uint32_t res;
+    __ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+    return res;
+  }
+
+  __IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr)
+  {
+    uint32_t res;
+    __ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
+    return res;
+  }
+
+  __IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr)
+  {
+    uint32_t res;
+    __ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
+    return res;
+  }
+
+  __IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr)
+  {
+    uint32_t res;
+    __ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
+    return res;
+  }
+
+#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */
+
+#undef __IAR_FT
+#undef __IAR_M0_FAMILY
+#undef __ICCARM_V8
+
+#pragma diag_default=Pe940
+#pragma diag_default=Pe177
+
+#endif /* __CMSIS_ICCARM_H__ */
diff --git a/Drivers/CMSIS/Include/cmsis_version.h b/Drivers/CMSIS/Include/cmsis_version.h
new file mode 100644
index 0000000..ae3f2e3
--- /dev/null
+++ b/Drivers/CMSIS/Include/cmsis_version.h
@@ -0,0 +1,39 @@
+/**************************************************************************//**
+ * @file     cmsis_version.h
+ * @brief    CMSIS Core(M) Version definitions
+ * @version  V5.0.2
+ * @date     19. April 2017
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CMSIS_VERSION_H
+#define __CMSIS_VERSION_H
+
+/*  CMSIS Version definitions */
+#define __CM_CMSIS_VERSION_MAIN  ( 5U)                                      /*!< [31:16] CMSIS Core(M) main version */
+#define __CM_CMSIS_VERSION_SUB   ( 1U)                                      /*!< [15:0]  CMSIS Core(M) sub version */
+#define __CM_CMSIS_VERSION       ((__CM_CMSIS_VERSION_MAIN << 16U) | \
+                                   __CM_CMSIS_VERSION_SUB           )       /*!< CMSIS Core(M) version number */
+#endif
diff --git a/Drivers/CMSIS/Include/core_armv8mbl.h b/Drivers/CMSIS/Include/core_armv8mbl.h
new file mode 100644
index 0000000..ec76ab2
--- /dev/null
+++ b/Drivers/CMSIS/Include/core_armv8mbl.h
@@ -0,0 +1,1918 @@
+/**************************************************************************//**
+ * @file     core_armv8mbl.h
+ * @brief    CMSIS Armv8-M Baseline Core Peripheral Access Layer Header File
+ * @version  V5.0.7
+ * @date     22. June 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_ARMV8MBL_H_GENERIC
+#define __CORE_ARMV8MBL_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup Cortex_ARMv8MBL
+  @{
+ */
+
+#include "cmsis_version.h"
+
+/*  CMSIS definitions */
+#define __ARMv8MBL_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)                   /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __ARMv8MBL_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)                    /*!< \deprecated [15:0]  CMSIS HAL sub version */
+#define __ARMv8MBL_CMSIS_VERSION       ((__ARMv8MBL_CMSIS_VERSION_MAIN << 16U) | \
+                                         __ARMv8MBL_CMSIS_VERSION_SUB           )  /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M                     ( 2U)                                            /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    This core does not support an FPU at all
+*/
+#define __FPU_USED       0U
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #if defined __ARM_PCS_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TI_ARM__ )
+  #if defined __TI_VFP_SUPPORT__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __CSMC__ )
+  #if ( __CSMC__ & 0x400U)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#endif
+
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_ARMV8MBL_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_ARMV8MBL_H_DEPENDANT
+#define __CORE_ARMV8MBL_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __ARMv8MBL_REV
+    #define __ARMv8MBL_REV               0x0000U
+    #warning "__ARMv8MBL_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __FPU_PRESENT
+    #define __FPU_PRESENT             0U
+    #warning "__FPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0U
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __SAUREGION_PRESENT
+    #define __SAUREGION_PRESENT       0U
+    #warning "__SAUREGION_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __VTOR_PRESENT
+    #define __VTOR_PRESENT            0U
+    #warning "__VTOR_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          2U
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0U
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+
+  #ifndef __ETM_PRESENT
+    #define __ETM_PRESENT             0U
+    #warning "__ETM_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MTB_PRESENT
+    #define __MTB_PRESENT             0U
+    #warning "__MTB_PRESENT not defined in device header file; using default!"
+  #endif
+
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group ARMv8MBL */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core Debug Register
+  - Core MPU Register
+  - Core SAU Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:28;              /*!< bit:  0..27  Reserved */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */
+    uint32_t _reserved1:3;               /*!< bit: 25..27  Reserved */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack-pointer select */
+    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IOM uint32_t ISER[16U];              /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+        uint32_t RESERVED0[16U];
+  __IOM uint32_t ICER[16U];              /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+        uint32_t RSERVED1[16U];
+  __IOM uint32_t ISPR[16U];              /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+        uint32_t RESERVED2[16U];
+  __IOM uint32_t ICPR[16U];              /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+        uint32_t RESERVED3[16U];
+  __IOM uint32_t IABR[16U];              /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */
+        uint32_t RESERVED4[16U];
+  __IOM uint32_t ITNS[16U];              /*!< Offset: 0x280 (R/W)  Interrupt Non-Secure State Register */
+        uint32_t RESERVED5[16U];
+  __IOM uint32_t IPR[124U];              /*!< Offset: 0x300 (R/W)  Interrupt Priority Register */
+}  NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
+#else
+        uint32_t RESERVED0;
+#endif
+  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+        uint32_t RESERVED1;
+  __IOM uint32_t SHPR[2U];               /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED */
+  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_PENDNMISET_Pos            31U                                            /*!< SCB ICSR: PENDNMISET Position */
+#define SCB_ICSR_PENDNMISET_Msk            (1UL << SCB_ICSR_PENDNMISET_Pos)               /*!< SCB ICSR: PENDNMISET Mask */
+
+#define SCB_ICSR_NMIPENDSET_Pos            SCB_ICSR_PENDNMISET_Pos                        /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */
+#define SCB_ICSR_NMIPENDSET_Msk            SCB_ICSR_PENDNMISET_Msk                        /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */
+
+#define SCB_ICSR_PENDNMICLR_Pos            30U                                            /*!< SCB ICSR: PENDNMICLR Position */
+#define SCB_ICSR_PENDNMICLR_Msk            (1UL << SCB_ICSR_PENDNMICLR_Pos)               /*!< SCB ICSR: PENDNMICLR Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_STTNS_Pos                 24U                                            /*!< SCB ICSR: STTNS Position (Security Extension) */
+#define SCB_ICSR_STTNS_Msk                 (1UL << SCB_ICSR_STTNS_Pos)                    /*!< SCB ICSR: STTNS Mask (Security Extension) */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
+#endif
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIS_Pos                 14U                                            /*!< SCB AIRCR: PRIS Position */
+#define SCB_AIRCR_PRIS_Msk                 (1UL << SCB_AIRCR_PRIS_Pos)                    /*!< SCB AIRCR: PRIS Mask */
+
+#define SCB_AIRCR_BFHFNMINS_Pos            13U                                            /*!< SCB AIRCR: BFHFNMINS Position */
+#define SCB_AIRCR_BFHFNMINS_Msk            (1UL << SCB_AIRCR_BFHFNMINS_Pos)               /*!< SCB AIRCR: BFHFNMINS Mask */
+
+#define SCB_AIRCR_SYSRESETREQS_Pos          3U                                            /*!< SCB AIRCR: SYSRESETREQS Position */
+#define SCB_AIRCR_SYSRESETREQS_Msk         (1UL << SCB_AIRCR_SYSRESETREQS_Pos)            /*!< SCB AIRCR: SYSRESETREQS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEPS_Pos              3U                                            /*!< SCB SCR: SLEEPDEEPS Position */
+#define SCB_SCR_SLEEPDEEPS_Msk             (1UL << SCB_SCR_SLEEPDEEPS_Pos)                /*!< SCB SCR: SLEEPDEEPS Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_BP_Pos                     18U                                            /*!< SCB CCR: BP Position */
+#define SCB_CCR_BP_Msk                     (1UL << SCB_CCR_BP_Pos)                        /*!< SCB CCR: BP Mask */
+
+#define SCB_CCR_IC_Pos                     17U                                            /*!< SCB CCR: IC Position */
+#define SCB_CCR_IC_Msk                     (1UL << SCB_CCR_IC_Pos)                        /*!< SCB CCR: IC Mask */
+
+#define SCB_CCR_DC_Pos                     16U                                            /*!< SCB CCR: DC Position */
+#define SCB_CCR_DC_Msk                     (1UL << SCB_CCR_DC_Pos)                        /*!< SCB CCR: DC Mask */
+
+#define SCB_CCR_STKOFHFNMIGN_Pos           10U                                            /*!< SCB CCR: STKOFHFNMIGN Position */
+#define SCB_CCR_STKOFHFNMIGN_Msk           (1UL << SCB_CCR_STKOFHFNMIGN_Pos)              /*!< SCB CCR: STKOFHFNMIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_HARDFAULTPENDED_Pos      21U                                            /*!< SCB SHCSR: HARDFAULTPENDED Position */
+#define SCB_SHCSR_HARDFAULTPENDED_Msk      (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)         /*!< SCB SHCSR: HARDFAULTPENDED Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_NMIACT_Pos                5U                                            /*!< SCB SHCSR: NMIACT Position */
+#define SCB_SHCSR_NMIACT_Msk               (1UL << SCB_SHCSR_NMIACT_Pos)                  /*!< SCB SHCSR: NMIACT Mask */
+
+#define SCB_SHCSR_HARDFAULTACT_Pos          2U                                            /*!< SCB SHCSR: HARDFAULTACT Position */
+#define SCB_SHCSR_HARDFAULTACT_Msk         (1UL << SCB_SHCSR_HARDFAULTACT_Pos)            /*!< SCB SHCSR: HARDFAULTACT Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
+  \brief    Type definitions for the Data Watchpoint and Trace (DWT)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */
+        uint32_t RESERVED0[6U];
+  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */
+  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */
+        uint32_t RESERVED1[1U];
+  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */
+        uint32_t RESERVED2[1U];
+  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */
+        uint32_t RESERVED3[1U];
+  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */
+        uint32_t RESERVED4[1U];
+  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */
+        uint32_t RESERVED5[1U];
+  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */
+        uint32_t RESERVED6[1U];
+  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */
+        uint32_t RESERVED7[1U];
+  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */
+        uint32_t RESERVED8[1U];
+  __IOM uint32_t COMP4;                  /*!< Offset: 0x060 (R/W)  Comparator Register 4 */
+        uint32_t RESERVED9[1U];
+  __IOM uint32_t FUNCTION4;              /*!< Offset: 0x068 (R/W)  Function Register 4 */
+        uint32_t RESERVED10[1U];
+  __IOM uint32_t COMP5;                  /*!< Offset: 0x070 (R/W)  Comparator Register 5 */
+        uint32_t RESERVED11[1U];
+  __IOM uint32_t FUNCTION5;              /*!< Offset: 0x078 (R/W)  Function Register 5 */
+        uint32_t RESERVED12[1U];
+  __IOM uint32_t COMP6;                  /*!< Offset: 0x080 (R/W)  Comparator Register 6 */
+        uint32_t RESERVED13[1U];
+  __IOM uint32_t FUNCTION6;              /*!< Offset: 0x088 (R/W)  Function Register 6 */
+        uint32_t RESERVED14[1U];
+  __IOM uint32_t COMP7;                  /*!< Offset: 0x090 (R/W)  Comparator Register 7 */
+        uint32_t RESERVED15[1U];
+  __IOM uint32_t FUNCTION7;              /*!< Offset: 0x098 (R/W)  Function Register 7 */
+        uint32_t RESERVED16[1U];
+  __IOM uint32_t COMP8;                  /*!< Offset: 0x0A0 (R/W)  Comparator Register 8 */
+        uint32_t RESERVED17[1U];
+  __IOM uint32_t FUNCTION8;              /*!< Offset: 0x0A8 (R/W)  Function Register 8 */
+        uint32_t RESERVED18[1U];
+  __IOM uint32_t COMP9;                  /*!< Offset: 0x0B0 (R/W)  Comparator Register 9 */
+        uint32_t RESERVED19[1U];
+  __IOM uint32_t FUNCTION9;              /*!< Offset: 0x0B8 (R/W)  Function Register 9 */
+        uint32_t RESERVED20[1U];
+  __IOM uint32_t COMP10;                 /*!< Offset: 0x0C0 (R/W)  Comparator Register 10 */
+        uint32_t RESERVED21[1U];
+  __IOM uint32_t FUNCTION10;             /*!< Offset: 0x0C8 (R/W)  Function Register 10 */
+        uint32_t RESERVED22[1U];
+  __IOM uint32_t COMP11;                 /*!< Offset: 0x0D0 (R/W)  Comparator Register 11 */
+        uint32_t RESERVED23[1U];
+  __IOM uint32_t FUNCTION11;             /*!< Offset: 0x0D8 (R/W)  Function Register 11 */
+        uint32_t RESERVED24[1U];
+  __IOM uint32_t COMP12;                 /*!< Offset: 0x0E0 (R/W)  Comparator Register 12 */
+        uint32_t RESERVED25[1U];
+  __IOM uint32_t FUNCTION12;             /*!< Offset: 0x0E8 (R/W)  Function Register 12 */
+        uint32_t RESERVED26[1U];
+  __IOM uint32_t COMP13;                 /*!< Offset: 0x0F0 (R/W)  Comparator Register 13 */
+        uint32_t RESERVED27[1U];
+  __IOM uint32_t FUNCTION13;             /*!< Offset: 0x0F8 (R/W)  Function Register 13 */
+        uint32_t RESERVED28[1U];
+  __IOM uint32_t COMP14;                 /*!< Offset: 0x100 (R/W)  Comparator Register 14 */
+        uint32_t RESERVED29[1U];
+  __IOM uint32_t FUNCTION14;             /*!< Offset: 0x108 (R/W)  Function Register 14 */
+        uint32_t RESERVED30[1U];
+  __IOM uint32_t COMP15;                 /*!< Offset: 0x110 (R/W)  Comparator Register 15 */
+        uint32_t RESERVED31[1U];
+  __IOM uint32_t FUNCTION15;             /*!< Offset: 0x118 (R/W)  Function Register 15 */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_ID_Pos                27U                                         /*!< DWT FUNCTION: ID Position */
+#define DWT_FUNCTION_ID_Msk                (0x1FUL << DWT_FUNCTION_ID_Pos)             /*!< DWT FUNCTION: ID Mask */
+
+#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_ACTION_Pos             4U                                         /*!< DWT FUNCTION: ACTION Position */
+#define DWT_FUNCTION_ACTION_Msk            (0x3UL << DWT_FUNCTION_ACTION_Pos)          /*!< DWT FUNCTION: ACTION Mask */
+
+#define DWT_FUNCTION_MATCH_Pos              0U                                         /*!< DWT FUNCTION: MATCH Position */
+#define DWT_FUNCTION_MATCH_Msk             (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/)       /*!< DWT FUNCTION: MATCH Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_TPI     Trace Port Interface (TPI)
+  \brief    Type definitions for the Trace Port Interface (TPI)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+  __IM  uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Sizes Register */
+  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Sizes Register */
+        uint32_t RESERVED0[2U];
+  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
+        uint32_t RESERVED1[55U];
+  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
+        uint32_t RESERVED2[131U];
+  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
+  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
+  __IOM uint32_t PSCR;                   /*!< Offset: 0x308 (R/W)  Periodic Synchronization Control Register */
+        uint32_t RESERVED3[809U];
+  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  Software Lock Access Register */
+  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  Software Lock Status Register */
+        uint32_t RESERVED4[4U];
+  __IM  uint32_t TYPE;                   /*!< Offset: 0xFC8 (R/ )  Device Identifier Register */
+  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  Device Type Register */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_SWOSCALER_Pos              0U                                         /*!< TPI ACPR: SWOSCALER Position */
+#define TPI_ACPR_SWOSCALER_Msk             (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/)    /*!< TPI ACPR: SWOSCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_FOnMan_Pos                 6U                                         /*!< TPI FFCR: FOnMan Position */
+#define TPI_FFCR_FOnMan_Msk                (0x1UL << TPI_FFCR_FOnMan_Pos)              /*!< TPI FFCR: FOnMan Mask */
+
+#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI Periodic Synchronization Control Register Definitions */
+#define TPI_PSCR_PSCount_Pos                0U                                         /*!< TPI PSCR: PSCount Position */
+#define TPI_PSCR_PSCount_Msk               (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/)        /*!< TPI PSCR: TPSCount Mask */
+
+/* TPI Software Lock Status Register Definitions */
+#define TPI_LSR_nTT_Pos                     1U                                         /*!< TPI LSR: Not thirty-two bit. Position */
+#define TPI_LSR_nTT_Msk                    (0x1UL << TPI_LSR_nTT_Pos)                  /*!< TPI LSR: Not thirty-two bit. Mask */
+
+#define TPI_LSR_SLK_Pos                     1U                                         /*!< TPI LSR: Software Lock status Position */
+#define TPI_LSR_SLK_Msk                    (0x1UL << TPI_LSR_SLK_Pos)                  /*!< TPI LSR: Software Lock status Mask */
+
+#define TPI_LSR_SLI_Pos                     0U                                         /*!< TPI LSR: Software Lock implemented Position */
+#define TPI_LSR_SLI_Msk                    (0x1UL /*<< TPI_LSR_SLI_Pos*/)              /*!< TPI LSR: Software Lock implemented Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_FIFOSZ_Pos                6U                                         /*!< TPI DEVID: FIFO depth Position */
+#define TPI_DEVID_FIFOSZ_Msk               (0x7UL << TPI_DEVID_FIFOSZ_Pos)             /*!< TPI DEVID: FIFO depth Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos             4U                                         /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos           0U                                         /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+  \brief    Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region Number Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
+  __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  MPU Region Limit Address Register */
+        uint32_t RESERVED0[7U];
+  union {
+  __IOM uint32_t MAIR[2];
+  struct {
+  __IOM uint32_t MAIR0;                  /*!< Offset: 0x030 (R/W)  MPU Memory Attribute Indirection Register 0 */
+  __IOM uint32_t MAIR1;                  /*!< Offset: 0x034 (R/W)  MPU Memory Attribute Indirection Register 1 */
+  };
+  };
+} MPU_Type;
+
+#define MPU_TYPE_RALIASES                  1U
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_BASE_Pos                   5U                                            /*!< MPU RBAR: BASE Position */
+#define MPU_RBAR_BASE_Msk                  (0x7FFFFFFUL << MPU_RBAR_BASE_Pos)             /*!< MPU RBAR: BASE Mask */
+
+#define MPU_RBAR_SH_Pos                     3U                                            /*!< MPU RBAR: SH Position */
+#define MPU_RBAR_SH_Msk                    (0x3UL << MPU_RBAR_SH_Pos)                     /*!< MPU RBAR: SH Mask */
+
+#define MPU_RBAR_AP_Pos                     1U                                            /*!< MPU RBAR: AP Position */
+#define MPU_RBAR_AP_Msk                    (0x3UL << MPU_RBAR_AP_Pos)                     /*!< MPU RBAR: AP Mask */
+
+#define MPU_RBAR_XN_Pos                     0U                                            /*!< MPU RBAR: XN Position */
+#define MPU_RBAR_XN_Msk                    (01UL /*<< MPU_RBAR_XN_Pos*/)                  /*!< MPU RBAR: XN Mask */
+
+/* MPU Region Limit Address Register Definitions */
+#define MPU_RLAR_LIMIT_Pos                  5U                                            /*!< MPU RLAR: LIMIT Position */
+#define MPU_RLAR_LIMIT_Msk                 (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos)            /*!< MPU RLAR: LIMIT Mask */
+
+#define MPU_RLAR_AttrIndx_Pos               1U                                            /*!< MPU RLAR: AttrIndx Position */
+#define MPU_RLAR_AttrIndx_Msk              (0x7UL << MPU_RLAR_AttrIndx_Pos)               /*!< MPU RLAR: AttrIndx Mask */
+
+#define MPU_RLAR_EN_Pos                     0U                                            /*!< MPU RLAR: EN Position */
+#define MPU_RLAR_EN_Msk                    (1UL /*<< MPU_RLAR_EN_Pos*/)                   /*!< MPU RLAR: EN Mask */
+
+/* MPU Memory Attribute Indirection Register 0 Definitions */
+#define MPU_MAIR0_Attr3_Pos                24U                                            /*!< MPU MAIR0: Attr3 Position */
+#define MPU_MAIR0_Attr3_Msk                (0xFFUL << MPU_MAIR0_Attr3_Pos)                /*!< MPU MAIR0: Attr3 Mask */
+
+#define MPU_MAIR0_Attr2_Pos                16U                                            /*!< MPU MAIR0: Attr2 Position */
+#define MPU_MAIR0_Attr2_Msk                (0xFFUL << MPU_MAIR0_Attr2_Pos)                /*!< MPU MAIR0: Attr2 Mask */
+
+#define MPU_MAIR0_Attr1_Pos                 8U                                            /*!< MPU MAIR0: Attr1 Position */
+#define MPU_MAIR0_Attr1_Msk                (0xFFUL << MPU_MAIR0_Attr1_Pos)                /*!< MPU MAIR0: Attr1 Mask */
+
+#define MPU_MAIR0_Attr0_Pos                 0U                                            /*!< MPU MAIR0: Attr0 Position */
+#define MPU_MAIR0_Attr0_Msk                (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/)            /*!< MPU MAIR0: Attr0 Mask */
+
+/* MPU Memory Attribute Indirection Register 1 Definitions */
+#define MPU_MAIR1_Attr7_Pos                24U                                            /*!< MPU MAIR1: Attr7 Position */
+#define MPU_MAIR1_Attr7_Msk                (0xFFUL << MPU_MAIR1_Attr7_Pos)                /*!< MPU MAIR1: Attr7 Mask */
+
+#define MPU_MAIR1_Attr6_Pos                16U                                            /*!< MPU MAIR1: Attr6 Position */
+#define MPU_MAIR1_Attr6_Msk                (0xFFUL << MPU_MAIR1_Attr6_Pos)                /*!< MPU MAIR1: Attr6 Mask */
+
+#define MPU_MAIR1_Attr5_Pos                 8U                                            /*!< MPU MAIR1: Attr5 Position */
+#define MPU_MAIR1_Attr5_Msk                (0xFFUL << MPU_MAIR1_Attr5_Pos)                /*!< MPU MAIR1: Attr5 Mask */
+
+#define MPU_MAIR1_Attr4_Pos                 0U                                            /*!< MPU MAIR1: Attr4 Position */
+#define MPU_MAIR1_Attr4_Msk                (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/)            /*!< MPU MAIR1: Attr4 Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SAU     Security Attribution Unit (SAU)
+  \brief    Type definitions for the Security Attribution Unit (SAU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Security Attribution Unit (SAU).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SAU Control Register */
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x004 (R/ )  SAU Type Register */
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  SAU Region Number Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  SAU Region Base Address Register */
+  __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  SAU Region Limit Address Register */
+#endif
+} SAU_Type;
+
+/* SAU Control Register Definitions */
+#define SAU_CTRL_ALLNS_Pos                  1U                                            /*!< SAU CTRL: ALLNS Position */
+#define SAU_CTRL_ALLNS_Msk                 (1UL << SAU_CTRL_ALLNS_Pos)                    /*!< SAU CTRL: ALLNS Mask */
+
+#define SAU_CTRL_ENABLE_Pos                 0U                                            /*!< SAU CTRL: ENABLE Position */
+#define SAU_CTRL_ENABLE_Msk                (1UL /*<< SAU_CTRL_ENABLE_Pos*/)               /*!< SAU CTRL: ENABLE Mask */
+
+/* SAU Type Register Definitions */
+#define SAU_TYPE_SREGION_Pos                0U                                            /*!< SAU TYPE: SREGION Position */
+#define SAU_TYPE_SREGION_Msk               (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/)           /*!< SAU TYPE: SREGION Mask */
+
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+/* SAU Region Number Register Definitions */
+#define SAU_RNR_REGION_Pos                  0U                                            /*!< SAU RNR: REGION Position */
+#define SAU_RNR_REGION_Msk                 (0xFFUL /*<< SAU_RNR_REGION_Pos*/)             /*!< SAU RNR: REGION Mask */
+
+/* SAU Region Base Address Register Definitions */
+#define SAU_RBAR_BADDR_Pos                  5U                                            /*!< SAU RBAR: BADDR Position */
+#define SAU_RBAR_BADDR_Msk                 (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos)            /*!< SAU RBAR: BADDR Mask */
+
+/* SAU Region Limit Address Register Definitions */
+#define SAU_RLAR_LADDR_Pos                  5U                                            /*!< SAU RLAR: LADDR Position */
+#define SAU_RLAR_LADDR_Msk                 (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos)            /*!< SAU RLAR: LADDR Mask */
+
+#define SAU_RLAR_NSC_Pos                    1U                                            /*!< SAU RLAR: NSC Position */
+#define SAU_RLAR_NSC_Msk                   (1UL << SAU_RLAR_NSC_Pos)                      /*!< SAU RLAR: NSC Mask */
+
+#define SAU_RLAR_ENABLE_Pos                 0U                                            /*!< SAU RLAR: ENABLE Position */
+#define SAU_RLAR_ENABLE_Msk                (1UL /*<< SAU_RLAR_ENABLE_Pos*/)               /*!< SAU RLAR: ENABLE Mask */
+
+#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
+
+/*@} end of group CMSIS_SAU */
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    Type definitions for the Core Debug Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */
+  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */
+  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */
+  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
+        uint32_t RESERVED4[1U];
+  __IOM uint32_t DAUTHCTRL;              /*!< Offset: 0x014 (R/W)  Debug Authentication Control Register */
+  __IOM uint32_t DSCSR;                  /*!< Offset: 0x018 (R/W)  Debug Security Control and Status Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESTART_ST_Pos   26U                                            /*!< CoreDebug DHCSR: S_RESTART_ST Position */
+#define CoreDebug_DHCSR_S_RESTART_ST_Msk   (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)      /*!< CoreDebug DHCSR: S_RESTART_ST Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register */
+#define CoreDebug_DEMCR_DWTENA_Pos         24U                                            /*!< CoreDebug DEMCR: DWTENA Position */
+#define CoreDebug_DEMCR_DWTENA_Msk         (1UL << CoreDebug_DEMCR_DWTENA_Pos)            /*!< CoreDebug DEMCR: DWTENA Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/* Debug Authentication Control Register Definitions */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos  3U                                            /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)    /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */
+
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos  2U                                            /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)    /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */
+
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos   1U                                            /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk  (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)     /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */
+
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos   0U                                            /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk  (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */
+
+/* Debug Security Control and Status Register Definitions */
+#define CoreDebug_DSCSR_CDS_Pos            16U                                            /*!< CoreDebug DSCSR: CDS Position */
+#define CoreDebug_DSCSR_CDS_Msk            (1UL << CoreDebug_DSCSR_CDS_Pos)               /*!< CoreDebug DSCSR: CDS Mask */
+
+#define CoreDebug_DSCSR_SBRSEL_Pos          1U                                            /*!< CoreDebug DSCSR: SBRSEL Position */
+#define CoreDebug_DSCSR_SBRSEL_Msk         (1UL << CoreDebug_DSCSR_SBRSEL_Pos)            /*!< CoreDebug DSCSR: SBRSEL Mask */
+
+#define CoreDebug_DSCSR_SBRSELEN_Pos        0U                                            /*!< CoreDebug DSCSR: SBRSELEN Position */
+#define CoreDebug_DSCSR_SBRSELEN_Msk       (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/)      /*!< CoreDebug DSCSR: SBRSELEN Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Core Hardware */
+  #define SCS_BASE            (0xE000E000UL)                             /*!< System Control Space Base Address */
+  #define DWT_BASE            (0xE0001000UL)                             /*!< DWT Base Address */
+  #define TPI_BASE            (0xE0040000UL)                             /*!< TPI Base Address */
+  #define CoreDebug_BASE      (0xE000EDF0UL)                             /*!< Core Debug Base Address */
+  #define SysTick_BASE        (SCS_BASE +  0x0010UL)                     /*!< SysTick Base Address */
+  #define NVIC_BASE           (SCS_BASE +  0x0100UL)                     /*!< NVIC Base Address */
+  #define SCB_BASE            (SCS_BASE +  0x0D00UL)                     /*!< System Control Block Base Address */
+
+
+  #define SCB                 ((SCB_Type       *)     SCB_BASE         ) /*!< SCB configuration struct */
+  #define SysTick             ((SysTick_Type   *)     SysTick_BASE     ) /*!< SysTick configuration struct */
+  #define NVIC                ((NVIC_Type      *)     NVIC_BASE        ) /*!< NVIC configuration struct */
+  #define DWT                 ((DWT_Type       *)     DWT_BASE         ) /*!< DWT configuration struct */
+  #define TPI                 ((TPI_Type       *)     TPI_BASE         ) /*!< TPI configuration struct */
+  #define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE   ) /*!< Core Debug configuration struct */
+
+  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+    #define MPU_BASE          (SCS_BASE +  0x0D90UL)                     /*!< Memory Protection Unit */
+    #define MPU               ((MPU_Type       *)     MPU_BASE         ) /*!< Memory Protection Unit */
+  #endif
+
+  #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+    #define SAU_BASE          (SCS_BASE +  0x0DD0UL)                     /*!< Security Attribution Unit */
+    #define SAU               ((SAU_Type       *)     SAU_BASE         ) /*!< Security Attribution Unit */
+  #endif
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+  #define SCS_BASE_NS         (0xE002E000UL)                             /*!< System Control Space Base Address (non-secure address space) */
+  #define CoreDebug_BASE_NS   (0xE002EDF0UL)                             /*!< Core Debug Base Address           (non-secure address space) */
+  #define SysTick_BASE_NS     (SCS_BASE_NS +  0x0010UL)                  /*!< SysTick Base Address              (non-secure address space) */
+  #define NVIC_BASE_NS        (SCS_BASE_NS +  0x0100UL)                  /*!< NVIC Base Address                 (non-secure address space) */
+  #define SCB_BASE_NS         (SCS_BASE_NS +  0x0D00UL)                  /*!< System Control Block Base Address (non-secure address space) */
+
+  #define SCB_NS              ((SCB_Type       *)     SCB_BASE_NS      ) /*!< SCB configuration struct          (non-secure address space) */
+  #define SysTick_NS          ((SysTick_Type   *)     SysTick_BASE_NS  ) /*!< SysTick configuration struct      (non-secure address space) */
+  #define NVIC_NS             ((NVIC_Type      *)     NVIC_BASE_NS     ) /*!< NVIC configuration struct         (non-secure address space) */
+  #define CoreDebug_NS        ((CoreDebug_Type *)     CoreDebug_BASE_NS) /*!< Core Debug configuration struct   (non-secure address space) */
+
+  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+    #define MPU_BASE_NS       (SCS_BASE_NS +  0x0D90UL)                  /*!< Memory Protection Unit            (non-secure address space) */
+    #define MPU_NS            ((MPU_Type       *)     MPU_BASE_NS      ) /*!< Memory Protection Unit            (non-secure address space) */
+  #endif
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+  #endif
+  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
+  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
+  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
+  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
+  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
+  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+  #define NVIC_GetActive              __NVIC_GetActive
+  #define NVIC_SetPriority            __NVIC_SetPriority
+  #define NVIC_GetPriority            __NVIC_GetPriority
+  #define NVIC_SystemReset            __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+  #endif
+  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetVector              __NVIC_SetVector
+  #define NVIC_GetVector              __NVIC_GetVector
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET          16
+
+
+/* Special LR values for Secure/Non-Secure call handling and exception handling                                               */
+
+/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS                   */
+#define FNC_RETURN                 (0xFEFFFFFFUL)     /* bit [0] ignored when processing a branch                             */
+
+/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */
+#define EXC_RETURN_PREFIX          (0xFF000000UL)     /* bits [31:24] set to indicate an EXC_RETURN value                     */
+#define EXC_RETURN_S               (0x00000040UL)     /* bit [6] stack used to push registers: 0=Non-secure 1=Secure          */
+#define EXC_RETURN_DCRS            (0x00000020UL)     /* bit [5] stacking rules for called registers: 0=skipped 1=saved       */
+#define EXC_RETURN_FTYPE           (0x00000010UL)     /* bit [4] allocate stack for floating-point context: 0=done 1=skipped  */
+#define EXC_RETURN_MODE            (0x00000008UL)     /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode      */
+#define EXC_RETURN_SPSEL           (0x00000002UL)     /* bit [1] stack pointer used to restore context: 0=MSP 1=PSP           */
+#define EXC_RETURN_ES              (0x00000001UL)     /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */
+
+/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking                            */
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)  /* Value for processors with floating-point extension:                  */
+#define EXC_INTEGRITY_SIGNATURE     (0xFEFA125AUL)     /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE                   */
+#else
+#define EXC_INTEGRITY_SIGNATURE     (0xFEFA125BUL)     /* Value for processors without floating-point extension                */
+#endif
+
+
+/* Interrupt Priorities are WORD accessible only under Armv6-M                  */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)
+#define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )
+#define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )
+
+#define __NVIC_SetPriorityGrouping(X) (void)(X)
+#define __NVIC_GetPriorityGrouping()  (0U)
+
+/**
+  \brief   Enable Interrupt
+  \details Enables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt
+  \details Disables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+    __DSB();
+    __ISB();
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Active Interrupt
+  \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not active.
+  \return             1  Interrupt status is active.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   Get Interrupt Target State
+  \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  if interrupt is assigned to Secure
+  \return             1  if interrupt is assigned to Non Secure
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Target State
+  \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  if interrupt is assigned to Secure
+                      1  if interrupt is assigned to Non Secure
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |=  ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
+    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Clear Interrupt Target State
+  \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  if interrupt is assigned to Secure
+                      1  if interrupt is assigned to Non Secure
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
+    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->IPR[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+  else
+  {
+    SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+
+
+/**
+  \brief   Encode Priority
+  \details Encodes the priority for an interrupt with the given priority group,
+           preemptive priority value, and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]     PriorityGroup  Used priority group.
+  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+  \param [in]       SubPriority  Subpriority value (starting from 0).
+  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  return (
+           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
+         );
+}
+
+
+/**
+  \brief   Decode Priority
+  \details Decodes an interrupt priority value with a given priority group to
+           preemptive priority value and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+  \param [in]     PriorityGroup  Used priority group.
+  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+  \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
+}
+
+
+/**
+  \brief   Set Interrupt Vector
+  \details Sets an interrupt vector in SRAM based interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+           VTOR must been relocated to SRAM before.
+           If VTOR is not present address 0 must be mapped to SRAM.
+  \param [in]   IRQn      Interrupt number
+  \param [in]   vector    Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+#else
+  uint32_t *vectors = (uint32_t *)0x0U;
+#endif
+  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+  \brief   Get Interrupt Vector
+  \details Reads an interrupt vector from interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn      Interrupt number.
+  \return                 Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+#else
+  uint32_t *vectors = (uint32_t *)0x0U;
+#endif
+  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+  __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+  SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                 SCB_AIRCR_SYSRESETREQ_Msk);
+  __DSB();                                                          /* Ensure completion of memory access */
+
+  for(;;)                                                           /* wait until reset */
+  {
+    __NOP();
+  }
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   Enable Interrupt (non-secure)
+  \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status (non-secure)
+  \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt (non-secure)
+  \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt (non-secure)
+  \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt (non-secure)
+  \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt (non-secure)
+  \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Active Interrupt (non-secure)
+  \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not active.
+  \return             1  Interrupt status is active.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Priority (non-secure)
+  \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every non-secure processor exception.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->IPR[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+  else
+  {
+    SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority (non-secure)
+  \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+#endif /*  defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+/* ##########################  MPU functions  #################################### */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+
+#include "mpu_armv8.h"
+
+#endif
+
+/* ##########################  FPU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions
+  \brief    Function that provides FPU type.
+  @{
+ */
+
+/**
+  \brief   get FPU type
+  \details returns the FPU type
+  \returns
+   - \b  0: No FPU
+   - \b  1: Single precision FPU
+   - \b  2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+    return 0U;           /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ##########################   SAU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SAUFunctions SAU Functions
+  \brief    Functions that configure the SAU.
+  @{
+ */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+
+/**
+  \brief   Enable SAU
+  \details Enables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Enable(void)
+{
+    SAU->CTRL |=  (SAU_CTRL_ENABLE_Msk);
+}
+
+
+
+/**
+  \brief   Disable SAU
+  \details Disables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Disable(void)
+{
+    SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
+}
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_SAUFunctions */
+
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                   /* Reload value impossible */
+  }
+
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                     /* Function successful */
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   System Tick Configuration (non-secure)
+  \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                         /* Reload value impossible */
+  }
+
+  SysTick_NS->LOAD  = (uint32_t)(ticks - 1UL);                            /* set reload register */
+  TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick_NS->VAL   = 0UL;                                                /* Load the SysTick Counter Value */
+  SysTick_NS->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                      SysTick_CTRL_TICKINT_Msk   |
+                      SysTick_CTRL_ENABLE_Msk;                            /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                           /* Function successful */
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_ARMV8MBL_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/Drivers/CMSIS/Include/core_armv8mml.h b/Drivers/CMSIS/Include/core_armv8mml.h
new file mode 100644
index 0000000..2d0f106
--- /dev/null
+++ b/Drivers/CMSIS/Include/core_armv8mml.h
@@ -0,0 +1,2927 @@
+/**************************************************************************//**
+ * @file     core_armv8mml.h
+ * @brief    CMSIS Armv8-M Mainline Core Peripheral Access Layer Header File
+ * @version  V5.0.7
+ * @date     06. July 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_ARMV8MML_H_GENERIC
+#define __CORE_ARMV8MML_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup Cortex_ARMv8MML
+  @{
+ */
+
+#include "cmsis_version.h"
+
+/*  CMSIS Armv8MML definitions */
+#define __ARMv8MML_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)                   /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __ARMv8MML_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)                    /*!< \deprecated [15:0]  CMSIS HAL sub version */
+#define __ARMv8MML_CMSIS_VERSION       ((__ARMv8MML_CMSIS_VERSION_MAIN << 16U) | \
+                                         __ARMv8MML_CMSIS_VERSION_SUB           )  /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M                     (81U)                                       /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
+*/
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+  #if defined(__ARM_FEATURE_DSP)
+    #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)
+      #define __DSP_USED       1U
+    #else
+      #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
+      #define __DSP_USED         0U
+    #endif
+  #else
+    #define __DSP_USED         0U
+  #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #if defined __ARM_PCS_VFP
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+  #if defined(__ARM_FEATURE_DSP)
+    #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)
+      #define __DSP_USED       1U
+    #else
+      #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
+      #define __DSP_USED         0U
+    #endif
+  #else
+    #define __DSP_USED         0U
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+  #if defined(__ARM_FEATURE_DSP)
+    #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)
+      #define __DSP_USED       1U
+    #else
+      #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
+      #define __DSP_USED         0U
+    #endif
+  #else
+    #define __DSP_USED         0U
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+  #if defined(__ARM_FEATURE_DSP)
+    #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)
+      #define __DSP_USED       1U
+    #else
+      #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
+      #define __DSP_USED         0U
+    #endif
+  #else
+    #define __DSP_USED         0U
+  #endif
+
+#elif defined ( __TI_ARM__ )
+  #if defined __TI_VFP_SUPPORT__
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __CSMC__ )
+  #if ( __CSMC__ & 0x400U)
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#endif
+
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_ARMV8MML_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_ARMV8MML_H_DEPENDANT
+#define __CORE_ARMV8MML_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __ARMv8MML_REV
+    #define __ARMv8MML_REV               0x0000U
+    #warning "__ARMv8MML_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __FPU_PRESENT
+    #define __FPU_PRESENT             0U
+    #warning "__FPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0U
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __SAUREGION_PRESENT
+    #define __SAUREGION_PRESENT       0U
+    #warning "__SAUREGION_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __DSP_PRESENT
+    #define __DSP_PRESENT             0U
+    #warning "__DSP_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          3U
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0U
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group ARMv8MML */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core Debug Register
+  - Core MPU Register
+  - Core SAU Register
+  - Core FPU Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */
+    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+#define APSR_Q_Pos                         27U                                            /*!< APSR: Q Position */
+#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */
+
+#define APSR_GE_Pos                        16U                                            /*!< APSR: GE Position */
+#define APSR_GE_Msk                        (0xFUL << APSR_GE_Pos)                         /*!< APSR: GE Mask */
+
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */
+    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */
+    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0) */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos                         27U                                            /*!< xPSR: Q Position */
+#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */
+
+#define xPSR_IT_Pos                        25U                                            /*!< xPSR: IT Position */
+#define xPSR_IT_Msk                        (3UL << xPSR_IT_Pos)                           /*!< xPSR: IT Mask */
+
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_GE_Pos                        16U                                            /*!< xPSR: GE Position */
+#define xPSR_GE_Msk                        (0xFUL << xPSR_GE_Pos)                         /*!< xPSR: GE Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack-pointer select */
+    uint32_t FPCA:1;                     /*!< bit:      2  Floating-point context active */
+    uint32_t SFPA:1;                     /*!< bit:      3  Secure floating-point active */
+    uint32_t _reserved1:28;              /*!< bit:  4..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SFPA_Pos                    3U                                            /*!< CONTROL: SFPA Position */
+#define CONTROL_SFPA_Msk                   (1UL << CONTROL_SFPA_Pos)                      /*!< CONTROL: SFPA Mask */
+
+#define CONTROL_FPCA_Pos                    2U                                            /*!< CONTROL: FPCA Position */
+#define CONTROL_FPCA_Msk                   (1UL << CONTROL_FPCA_Pos)                      /*!< CONTROL: FPCA Mask */
+
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IOM uint32_t ISER[16U];              /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+        uint32_t RESERVED0[16U];
+  __IOM uint32_t ICER[16U];              /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+        uint32_t RSERVED1[16U];
+  __IOM uint32_t ISPR[16U];              /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+        uint32_t RESERVED2[16U];
+  __IOM uint32_t ICPR[16U];              /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+        uint32_t RESERVED3[16U];
+  __IOM uint32_t IABR[16U];              /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */
+        uint32_t RESERVED4[16U];
+  __IOM uint32_t ITNS[16U];              /*!< Offset: 0x280 (R/W)  Interrupt Non-Secure State Register */
+        uint32_t RESERVED5[16U];
+  __IOM uint8_t  IPR[496U];              /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
+        uint32_t RESERVED6[580U];
+  __OM  uint32_t STIR;                   /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register */
+}  NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos                 0U                                         /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
+  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+  __IOM uint8_t  SHPR[12U];              /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
+  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+  __IOM uint32_t CFSR;                   /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register */
+  __IOM uint32_t HFSR;                   /*!< Offset: 0x02C (R/W)  HardFault Status Register */
+  __IOM uint32_t DFSR;                   /*!< Offset: 0x030 (R/W)  Debug Fault Status Register */
+  __IOM uint32_t MMFAR;                  /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register */
+  __IOM uint32_t BFAR;                   /*!< Offset: 0x038 (R/W)  BusFault Address Register */
+  __IOM uint32_t AFSR;                   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register */
+  __IM  uint32_t ID_PFR[2U];             /*!< Offset: 0x040 (R/ )  Processor Feature Register */
+  __IM  uint32_t ID_DFR;                 /*!< Offset: 0x048 (R/ )  Debug Feature Register */
+  __IM  uint32_t ID_ADR;                 /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */
+  __IM  uint32_t ID_MMFR[4U];            /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */
+  __IM  uint32_t ID_ISAR[6U];            /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register */
+  __IM  uint32_t CLIDR;                  /*!< Offset: 0x078 (R/ )  Cache Level ID register */
+  __IM  uint32_t CTR;                    /*!< Offset: 0x07C (R/ )  Cache Type register */
+  __IM  uint32_t CCSIDR;                 /*!< Offset: 0x080 (R/ )  Cache Size ID Register */
+  __IOM uint32_t CSSELR;                 /*!< Offset: 0x084 (R/W)  Cache Size Selection Register */
+  __IOM uint32_t CPACR;                  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register */
+  __IOM uint32_t NSACR;                  /*!< Offset: 0x08C (R/W)  Non-Secure Access Control Register */
+        uint32_t RESERVED3[92U];
+  __OM  uint32_t STIR;                   /*!< Offset: 0x200 ( /W)  Software Triggered Interrupt Register */
+        uint32_t RESERVED4[15U];
+  __IM  uint32_t MVFR0;                  /*!< Offset: 0x240 (R/ )  Media and VFP Feature Register 0 */
+  __IM  uint32_t MVFR1;                  /*!< Offset: 0x244 (R/ )  Media and VFP Feature Register 1 */
+  __IM  uint32_t MVFR2;                  /*!< Offset: 0x248 (R/ )  Media and VFP Feature Register 2 */
+        uint32_t RESERVED5[1U];
+  __OM  uint32_t ICIALLU;                /*!< Offset: 0x250 ( /W)  I-Cache Invalidate All to PoU */
+        uint32_t RESERVED6[1U];
+  __OM  uint32_t ICIMVAU;                /*!< Offset: 0x258 ( /W)  I-Cache Invalidate by MVA to PoU */
+  __OM  uint32_t DCIMVAC;                /*!< Offset: 0x25C ( /W)  D-Cache Invalidate by MVA to PoC */
+  __OM  uint32_t DCISW;                  /*!< Offset: 0x260 ( /W)  D-Cache Invalidate by Set-way */
+  __OM  uint32_t DCCMVAU;                /*!< Offset: 0x264 ( /W)  D-Cache Clean by MVA to PoU */
+  __OM  uint32_t DCCMVAC;                /*!< Offset: 0x268 ( /W)  D-Cache Clean by MVA to PoC */
+  __OM  uint32_t DCCSW;                  /*!< Offset: 0x26C ( /W)  D-Cache Clean by Set-way */
+  __OM  uint32_t DCCIMVAC;               /*!< Offset: 0x270 ( /W)  D-Cache Clean and Invalidate by MVA to PoC */
+  __OM  uint32_t DCCISW;                 /*!< Offset: 0x274 ( /W)  D-Cache Clean and Invalidate by Set-way */
+        uint32_t RESERVED7[6U];
+  __IOM uint32_t ITCMCR;                 /*!< Offset: 0x290 (R/W)  Instruction Tightly-Coupled Memory Control Register */
+  __IOM uint32_t DTCMCR;                 /*!< Offset: 0x294 (R/W)  Data Tightly-Coupled Memory Control Registers */
+  __IOM uint32_t AHBPCR;                 /*!< Offset: 0x298 (R/W)  AHBP Control Register */
+  __IOM uint32_t CACR;                   /*!< Offset: 0x29C (R/W)  L1 Cache Control Register */
+  __IOM uint32_t AHBSCR;                 /*!< Offset: 0x2A0 (R/W)  AHB Slave Control Register */
+        uint32_t RESERVED8[1U];
+  __IOM uint32_t ABFSR;                  /*!< Offset: 0x2A8 (R/W)  Auxiliary Bus Fault Status Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_PENDNMISET_Pos            31U                                            /*!< SCB ICSR: PENDNMISET Position */
+#define SCB_ICSR_PENDNMISET_Msk            (1UL << SCB_ICSR_PENDNMISET_Pos)               /*!< SCB ICSR: PENDNMISET Mask */
+
+#define SCB_ICSR_NMIPENDSET_Pos            SCB_ICSR_PENDNMISET_Pos                        /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */
+#define SCB_ICSR_NMIPENDSET_Msk            SCB_ICSR_PENDNMISET_Msk                        /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */
+
+#define SCB_ICSR_PENDNMICLR_Pos            30U                                            /*!< SCB ICSR: PENDNMICLR Position */
+#define SCB_ICSR_PENDNMICLR_Msk            (1UL << SCB_ICSR_PENDNMICLR_Pos)               /*!< SCB ICSR: PENDNMICLR Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_STTNS_Pos                 24U                                            /*!< SCB ICSR: STTNS Position (Security Extension) */
+#define SCB_ICSR_STTNS_Msk                 (1UL << SCB_ICSR_STTNS_Pos)                    /*!< SCB ICSR: STTNS Mask (Security Extension) */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIS_Pos                 14U                                            /*!< SCB AIRCR: PRIS Position */
+#define SCB_AIRCR_PRIS_Msk                 (1UL << SCB_AIRCR_PRIS_Pos)                    /*!< SCB AIRCR: PRIS Mask */
+
+#define SCB_AIRCR_BFHFNMINS_Pos            13U                                            /*!< SCB AIRCR: BFHFNMINS Position */
+#define SCB_AIRCR_BFHFNMINS_Msk            (1UL << SCB_AIRCR_BFHFNMINS_Pos)               /*!< SCB AIRCR: BFHFNMINS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos              8U                                            /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQS_Pos          3U                                            /*!< SCB AIRCR: SYSRESETREQS Position */
+#define SCB_AIRCR_SYSRESETREQS_Msk         (1UL << SCB_AIRCR_SYSRESETREQS_Pos)            /*!< SCB AIRCR: SYSRESETREQS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEPS_Pos              3U                                            /*!< SCB SCR: SLEEPDEEPS Position */
+#define SCB_SCR_SLEEPDEEPS_Msk             (1UL << SCB_SCR_SLEEPDEEPS_Pos)                /*!< SCB SCR: SLEEPDEEPS Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_BP_Pos                     18U                                            /*!< SCB CCR: BP Position */
+#define SCB_CCR_BP_Msk                     (1UL << SCB_CCR_BP_Pos)                        /*!< SCB CCR: BP Mask */
+
+#define SCB_CCR_IC_Pos                     17U                                            /*!< SCB CCR: IC Position */
+#define SCB_CCR_IC_Msk                     (1UL << SCB_CCR_IC_Pos)                        /*!< SCB CCR: IC Mask */
+
+#define SCB_CCR_DC_Pos                     16U                                            /*!< SCB CCR: DC Position */
+#define SCB_CCR_DC_Msk                     (1UL << SCB_CCR_DC_Pos)                        /*!< SCB CCR: DC Mask */
+
+#define SCB_CCR_STKOFHFNMIGN_Pos           10U                                            /*!< SCB CCR: STKOFHFNMIGN Position */
+#define SCB_CCR_STKOFHFNMIGN_Msk           (1UL << SCB_CCR_STKOFHFNMIGN_Pos)              /*!< SCB CCR: STKOFHFNMIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_HARDFAULTPENDED_Pos      21U                                            /*!< SCB SHCSR: HARDFAULTPENDED Position */
+#define SCB_SHCSR_HARDFAULTPENDED_Msk      (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)         /*!< SCB SHCSR: HARDFAULTPENDED Mask */
+
+#define SCB_SHCSR_SECUREFAULTPENDED_Pos    20U                                            /*!< SCB SHCSR: SECUREFAULTPENDED Position */
+#define SCB_SHCSR_SECUREFAULTPENDED_Msk    (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos)       /*!< SCB SHCSR: SECUREFAULTPENDED Mask */
+
+#define SCB_SHCSR_SECUREFAULTENA_Pos       19U                                            /*!< SCB SHCSR: SECUREFAULTENA Position */
+#define SCB_SHCSR_SECUREFAULTENA_Msk       (1UL << SCB_SHCSR_SECUREFAULTENA_Pos)          /*!< SCB SHCSR: SECUREFAULTENA Mask */
+
+#define SCB_SHCSR_USGFAULTENA_Pos          18U                                            /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos          17U                                            /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos          16U                                            /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos       14U                                            /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos       13U                                            /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos       12U                                            /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos            8U                                            /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_NMIACT_Pos                5U                                            /*!< SCB SHCSR: NMIACT Position */
+#define SCB_SHCSR_NMIACT_Msk               (1UL << SCB_SHCSR_NMIACT_Pos)                  /*!< SCB SHCSR: NMIACT Mask */
+
+#define SCB_SHCSR_SECUREFAULTACT_Pos        4U                                            /*!< SCB SHCSR: SECUREFAULTACT Position */
+#define SCB_SHCSR_SECUREFAULTACT_Msk       (1UL << SCB_SHCSR_SECUREFAULTACT_Pos)          /*!< SCB SHCSR: SECUREFAULTACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos           3U                                            /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_HARDFAULTACT_Pos          2U                                            /*!< SCB SHCSR: HARDFAULTACT Position */
+#define SCB_SHCSR_HARDFAULTACT_Msk         (1UL << SCB_SHCSR_HARDFAULTACT_Pos)            /*!< SCB SHCSR: HARDFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos           1U                                            /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos           0U                                            /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos            16U                                            /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos             8U                                            /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos             0U                                            /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_MMARVALID_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 7U)               /*!< SCB CFSR (MMFSR): MMARVALID Position */
+#define SCB_CFSR_MMARVALID_Msk             (1UL << SCB_CFSR_MMARVALID_Pos)                /*!< SCB CFSR (MMFSR): MMARVALID Mask */
+
+#define SCB_CFSR_MLSPERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 5U)               /*!< SCB CFSR (MMFSR): MLSPERR Position */
+#define SCB_CFSR_MLSPERR_Msk               (1UL << SCB_CFSR_MLSPERR_Pos)                  /*!< SCB CFSR (MMFSR): MLSPERR Mask */
+
+#define SCB_CFSR_MSTKERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 4U)               /*!< SCB CFSR (MMFSR): MSTKERR Position */
+#define SCB_CFSR_MSTKERR_Msk               (1UL << SCB_CFSR_MSTKERR_Pos)                  /*!< SCB CFSR (MMFSR): MSTKERR Mask */
+
+#define SCB_CFSR_MUNSTKERR_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 3U)               /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
+#define SCB_CFSR_MUNSTKERR_Msk             (1UL << SCB_CFSR_MUNSTKERR_Pos)                /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
+
+#define SCB_CFSR_DACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 1U)               /*!< SCB CFSR (MMFSR): DACCVIOL Position */
+#define SCB_CFSR_DACCVIOL_Msk              (1UL << SCB_CFSR_DACCVIOL_Pos)                 /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
+
+#define SCB_CFSR_IACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 0U)               /*!< SCB CFSR (MMFSR): IACCVIOL Position */
+#define SCB_CFSR_IACCVIOL_Msk              (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)             /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
+
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_BFARVALID_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 7U)                  /*!< SCB CFSR (BFSR): BFARVALID Position */
+#define SCB_CFSR_BFARVALID_Msk            (1UL << SCB_CFSR_BFARVALID_Pos)                 /*!< SCB CFSR (BFSR): BFARVALID Mask */
+
+#define SCB_CFSR_LSPERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 5U)                  /*!< SCB CFSR (BFSR): LSPERR Position */
+#define SCB_CFSR_LSPERR_Msk               (1UL << SCB_CFSR_LSPERR_Pos)                    /*!< SCB CFSR (BFSR): LSPERR Mask */
+
+#define SCB_CFSR_STKERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 4U)                  /*!< SCB CFSR (BFSR): STKERR Position */
+#define SCB_CFSR_STKERR_Msk               (1UL << SCB_CFSR_STKERR_Pos)                    /*!< SCB CFSR (BFSR): STKERR Mask */
+
+#define SCB_CFSR_UNSTKERR_Pos             (SCB_CFSR_BUSFAULTSR_Pos + 3U)                  /*!< SCB CFSR (BFSR): UNSTKERR Position */
+#define SCB_CFSR_UNSTKERR_Msk             (1UL << SCB_CFSR_UNSTKERR_Pos)                  /*!< SCB CFSR (BFSR): UNSTKERR Mask */
+
+#define SCB_CFSR_IMPRECISERR_Pos          (SCB_CFSR_BUSFAULTSR_Pos + 2U)                  /*!< SCB CFSR (BFSR): IMPRECISERR Position */
+#define SCB_CFSR_IMPRECISERR_Msk          (1UL << SCB_CFSR_IMPRECISERR_Pos)               /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
+
+#define SCB_CFSR_PRECISERR_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 1U)                  /*!< SCB CFSR (BFSR): PRECISERR Position */
+#define SCB_CFSR_PRECISERR_Msk            (1UL << SCB_CFSR_PRECISERR_Pos)                 /*!< SCB CFSR (BFSR): PRECISERR Mask */
+
+#define SCB_CFSR_IBUSERR_Pos              (SCB_CFSR_BUSFAULTSR_Pos + 0U)                  /*!< SCB CFSR (BFSR): IBUSERR Position */
+#define SCB_CFSR_IBUSERR_Msk              (1UL << SCB_CFSR_IBUSERR_Pos)                   /*!< SCB CFSR (BFSR): IBUSERR Mask */
+
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_DIVBYZERO_Pos            (SCB_CFSR_USGFAULTSR_Pos + 9U)                  /*!< SCB CFSR (UFSR): DIVBYZERO Position */
+#define SCB_CFSR_DIVBYZERO_Msk            (1UL << SCB_CFSR_DIVBYZERO_Pos)                 /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
+
+#define SCB_CFSR_UNALIGNED_Pos            (SCB_CFSR_USGFAULTSR_Pos + 8U)                  /*!< SCB CFSR (UFSR): UNALIGNED Position */
+#define SCB_CFSR_UNALIGNED_Msk            (1UL << SCB_CFSR_UNALIGNED_Pos)                 /*!< SCB CFSR (UFSR): UNALIGNED Mask */
+
+#define SCB_CFSR_STKOF_Pos                (SCB_CFSR_USGFAULTSR_Pos + 4U)                  /*!< SCB CFSR (UFSR): STKOF Position */
+#define SCB_CFSR_STKOF_Msk                (1UL << SCB_CFSR_STKOF_Pos)                     /*!< SCB CFSR (UFSR): STKOF Mask */
+
+#define SCB_CFSR_NOCP_Pos                 (SCB_CFSR_USGFAULTSR_Pos + 3U)                  /*!< SCB CFSR (UFSR): NOCP Position */
+#define SCB_CFSR_NOCP_Msk                 (1UL << SCB_CFSR_NOCP_Pos)                      /*!< SCB CFSR (UFSR): NOCP Mask */
+
+#define SCB_CFSR_INVPC_Pos                (SCB_CFSR_USGFAULTSR_Pos + 2U)                  /*!< SCB CFSR (UFSR): INVPC Position */
+#define SCB_CFSR_INVPC_Msk                (1UL << SCB_CFSR_INVPC_Pos)                     /*!< SCB CFSR (UFSR): INVPC Mask */
+
+#define SCB_CFSR_INVSTATE_Pos             (SCB_CFSR_USGFAULTSR_Pos + 1U)                  /*!< SCB CFSR (UFSR): INVSTATE Position */
+#define SCB_CFSR_INVSTATE_Msk             (1UL << SCB_CFSR_INVSTATE_Pos)                  /*!< SCB CFSR (UFSR): INVSTATE Mask */
+
+#define SCB_CFSR_UNDEFINSTR_Pos           (SCB_CFSR_USGFAULTSR_Pos + 0U)                  /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
+#define SCB_CFSR_UNDEFINSTR_Msk           (1UL << SCB_CFSR_UNDEFINSTR_Pos)                /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos              31U                                            /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos                30U                                            /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos                1U                                            /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos               4U                                            /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos                 3U                                            /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos                2U                                            /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos                   1U                                            /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos                 0U                                            /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */
+
+/* SCB Non-Secure Access Control Register Definitions */
+#define SCB_NSACR_CP11_Pos                 11U                                            /*!< SCB NSACR: CP11 Position */
+#define SCB_NSACR_CP11_Msk                 (1UL << SCB_NSACR_CP11_Pos)                    /*!< SCB NSACR: CP11 Mask */
+
+#define SCB_NSACR_CP10_Pos                 10U                                            /*!< SCB NSACR: CP10 Position */
+#define SCB_NSACR_CP10_Msk                 (1UL << SCB_NSACR_CP10_Pos)                    /*!< SCB NSACR: CP10 Mask */
+
+#define SCB_NSACR_CPn_Pos                   0U                                            /*!< SCB NSACR: CPn Position */
+#define SCB_NSACR_CPn_Msk                  (1UL /*<< SCB_NSACR_CPn_Pos*/)                 /*!< SCB NSACR: CPn Mask */
+
+/* SCB Cache Level ID Register Definitions */
+#define SCB_CLIDR_LOUU_Pos                 27U                                            /*!< SCB CLIDR: LoUU Position */
+#define SCB_CLIDR_LOUU_Msk                 (7UL << SCB_CLIDR_LOUU_Pos)                    /*!< SCB CLIDR: LoUU Mask */
+
+#define SCB_CLIDR_LOC_Pos                  24U                                            /*!< SCB CLIDR: LoC Position */
+#define SCB_CLIDR_LOC_Msk                  (7UL << SCB_CLIDR_LOC_Pos)                     /*!< SCB CLIDR: LoC Mask */
+
+/* SCB Cache Type Register Definitions */
+#define SCB_CTR_FORMAT_Pos                 29U                                            /*!< SCB CTR: Format Position */
+#define SCB_CTR_FORMAT_Msk                 (7UL << SCB_CTR_FORMAT_Pos)                    /*!< SCB CTR: Format Mask */
+
+#define SCB_CTR_CWG_Pos                    24U                                            /*!< SCB CTR: CWG Position */
+#define SCB_CTR_CWG_Msk                    (0xFUL << SCB_CTR_CWG_Pos)                     /*!< SCB CTR: CWG Mask */
+
+#define SCB_CTR_ERG_Pos                    20U                                            /*!< SCB CTR: ERG Position */
+#define SCB_CTR_ERG_Msk                    (0xFUL << SCB_CTR_ERG_Pos)                     /*!< SCB CTR: ERG Mask */
+
+#define SCB_CTR_DMINLINE_Pos               16U                                            /*!< SCB CTR: DminLine Position */
+#define SCB_CTR_DMINLINE_Msk               (0xFUL << SCB_CTR_DMINLINE_Pos)                /*!< SCB CTR: DminLine Mask */
+
+#define SCB_CTR_IMINLINE_Pos                0U                                            /*!< SCB CTR: ImInLine Position */
+#define SCB_CTR_IMINLINE_Msk               (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/)            /*!< SCB CTR: ImInLine Mask */
+
+/* SCB Cache Size ID Register Definitions */
+#define SCB_CCSIDR_WT_Pos                  31U                                            /*!< SCB CCSIDR: WT Position */
+#define SCB_CCSIDR_WT_Msk                  (1UL << SCB_CCSIDR_WT_Pos)                     /*!< SCB CCSIDR: WT Mask */
+
+#define SCB_CCSIDR_WB_Pos                  30U                                            /*!< SCB CCSIDR: WB Position */
+#define SCB_CCSIDR_WB_Msk                  (1UL << SCB_CCSIDR_WB_Pos)                     /*!< SCB CCSIDR: WB Mask */
+
+#define SCB_CCSIDR_RA_Pos                  29U                                            /*!< SCB CCSIDR: RA Position */
+#define SCB_CCSIDR_RA_Msk                  (1UL << SCB_CCSIDR_RA_Pos)                     /*!< SCB CCSIDR: RA Mask */
+
+#define SCB_CCSIDR_WA_Pos                  28U                                            /*!< SCB CCSIDR: WA Position */
+#define SCB_CCSIDR_WA_Msk                  (1UL << SCB_CCSIDR_WA_Pos)                     /*!< SCB CCSIDR: WA Mask */
+
+#define SCB_CCSIDR_NUMSETS_Pos             13U                                            /*!< SCB CCSIDR: NumSets Position */
+#define SCB_CCSIDR_NUMSETS_Msk             (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)           /*!< SCB CCSIDR: NumSets Mask */
+
+#define SCB_CCSIDR_ASSOCIATIVITY_Pos        3U                                            /*!< SCB CCSIDR: Associativity Position */
+#define SCB_CCSIDR_ASSOCIATIVITY_Msk       (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)      /*!< SCB CCSIDR: Associativity Mask */
+
+#define SCB_CCSIDR_LINESIZE_Pos             0U                                            /*!< SCB CCSIDR: LineSize Position */
+#define SCB_CCSIDR_LINESIZE_Msk            (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/)           /*!< SCB CCSIDR: LineSize Mask */
+
+/* SCB Cache Size Selection Register Definitions */
+#define SCB_CSSELR_LEVEL_Pos                1U                                            /*!< SCB CSSELR: Level Position */
+#define SCB_CSSELR_LEVEL_Msk               (7UL << SCB_CSSELR_LEVEL_Pos)                  /*!< SCB CSSELR: Level Mask */
+
+#define SCB_CSSELR_IND_Pos                  0U                                            /*!< SCB CSSELR: InD Position */
+#define SCB_CSSELR_IND_Msk                 (1UL /*<< SCB_CSSELR_IND_Pos*/)                /*!< SCB CSSELR: InD Mask */
+
+/* SCB Software Triggered Interrupt Register Definitions */
+#define SCB_STIR_INTID_Pos                  0U                                            /*!< SCB STIR: INTID Position */
+#define SCB_STIR_INTID_Msk                 (0x1FFUL /*<< SCB_STIR_INTID_Pos*/)            /*!< SCB STIR: INTID Mask */
+
+/* SCB D-Cache Invalidate by Set-way Register Definitions */
+#define SCB_DCISW_WAY_Pos                  30U                                            /*!< SCB DCISW: Way Position */
+#define SCB_DCISW_WAY_Msk                  (3UL << SCB_DCISW_WAY_Pos)                     /*!< SCB DCISW: Way Mask */
+
+#define SCB_DCISW_SET_Pos                   5U                                            /*!< SCB DCISW: Set Position */
+#define SCB_DCISW_SET_Msk                  (0x1FFUL << SCB_DCISW_SET_Pos)                 /*!< SCB DCISW: Set Mask */
+
+/* SCB D-Cache Clean by Set-way Register Definitions */
+#define SCB_DCCSW_WAY_Pos                  30U                                            /*!< SCB DCCSW: Way Position */
+#define SCB_DCCSW_WAY_Msk                  (3UL << SCB_DCCSW_WAY_Pos)                     /*!< SCB DCCSW: Way Mask */
+
+#define SCB_DCCSW_SET_Pos                   5U                                            /*!< SCB DCCSW: Set Position */
+#define SCB_DCCSW_SET_Msk                  (0x1FFUL << SCB_DCCSW_SET_Pos)                 /*!< SCB DCCSW: Set Mask */
+
+/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */
+#define SCB_DCCISW_WAY_Pos                 30U                                            /*!< SCB DCCISW: Way Position */
+#define SCB_DCCISW_WAY_Msk                 (3UL << SCB_DCCISW_WAY_Pos)                    /*!< SCB DCCISW: Way Mask */
+
+#define SCB_DCCISW_SET_Pos                  5U                                            /*!< SCB DCCISW: Set Position */
+#define SCB_DCCISW_SET_Msk                 (0x1FFUL << SCB_DCCISW_SET_Pos)                /*!< SCB DCCISW: Set Mask */
+
+/* Instruction Tightly-Coupled Memory Control Register Definitions */
+#define SCB_ITCMCR_SZ_Pos                   3U                                            /*!< SCB ITCMCR: SZ Position */
+#define SCB_ITCMCR_SZ_Msk                  (0xFUL << SCB_ITCMCR_SZ_Pos)                   /*!< SCB ITCMCR: SZ Mask */
+
+#define SCB_ITCMCR_RETEN_Pos                2U                                            /*!< SCB ITCMCR: RETEN Position */
+#define SCB_ITCMCR_RETEN_Msk               (1UL << SCB_ITCMCR_RETEN_Pos)                  /*!< SCB ITCMCR: RETEN Mask */
+
+#define SCB_ITCMCR_RMW_Pos                  1U                                            /*!< SCB ITCMCR: RMW Position */
+#define SCB_ITCMCR_RMW_Msk                 (1UL << SCB_ITCMCR_RMW_Pos)                    /*!< SCB ITCMCR: RMW Mask */
+
+#define SCB_ITCMCR_EN_Pos                   0U                                            /*!< SCB ITCMCR: EN Position */
+#define SCB_ITCMCR_EN_Msk                  (1UL /*<< SCB_ITCMCR_EN_Pos*/)                 /*!< SCB ITCMCR: EN Mask */
+
+/* Data Tightly-Coupled Memory Control Register Definitions */
+#define SCB_DTCMCR_SZ_Pos                   3U                                            /*!< SCB DTCMCR: SZ Position */
+#define SCB_DTCMCR_SZ_Msk                  (0xFUL << SCB_DTCMCR_SZ_Pos)                   /*!< SCB DTCMCR: SZ Mask */
+
+#define SCB_DTCMCR_RETEN_Pos                2U                                            /*!< SCB DTCMCR: RETEN Position */
+#define SCB_DTCMCR_RETEN_Msk               (1UL << SCB_DTCMCR_RETEN_Pos)                   /*!< SCB DTCMCR: RETEN Mask */
+
+#define SCB_DTCMCR_RMW_Pos                  1U                                            /*!< SCB DTCMCR: RMW Position */
+#define SCB_DTCMCR_RMW_Msk                 (1UL << SCB_DTCMCR_RMW_Pos)                    /*!< SCB DTCMCR: RMW Mask */
+
+#define SCB_DTCMCR_EN_Pos                   0U                                            /*!< SCB DTCMCR: EN Position */
+#define SCB_DTCMCR_EN_Msk                  (1UL /*<< SCB_DTCMCR_EN_Pos*/)                 /*!< SCB DTCMCR: EN Mask */
+
+/* AHBP Control Register Definitions */
+#define SCB_AHBPCR_SZ_Pos                   1U                                            /*!< SCB AHBPCR: SZ Position */
+#define SCB_AHBPCR_SZ_Msk                  (7UL << SCB_AHBPCR_SZ_Pos)                     /*!< SCB AHBPCR: SZ Mask */
+
+#define SCB_AHBPCR_EN_Pos                   0U                                            /*!< SCB AHBPCR: EN Position */
+#define SCB_AHBPCR_EN_Msk                  (1UL /*<< SCB_AHBPCR_EN_Pos*/)                 /*!< SCB AHBPCR: EN Mask */
+
+/* L1 Cache Control Register Definitions */
+#define SCB_CACR_FORCEWT_Pos                2U                                            /*!< SCB CACR: FORCEWT Position */
+#define SCB_CACR_FORCEWT_Msk               (1UL << SCB_CACR_FORCEWT_Pos)                  /*!< SCB CACR: FORCEWT Mask */
+
+#define SCB_CACR_ECCEN_Pos                  1U                                            /*!< SCB CACR: ECCEN Position */
+#define SCB_CACR_ECCEN_Msk                 (1UL << SCB_CACR_ECCEN_Pos)                    /*!< SCB CACR: ECCEN Mask */
+
+#define SCB_CACR_SIWT_Pos                   0U                                            /*!< SCB CACR: SIWT Position */
+#define SCB_CACR_SIWT_Msk                  (1UL /*<< SCB_CACR_SIWT_Pos*/)                 /*!< SCB CACR: SIWT Mask */
+
+/* AHBS Control Register Definitions */
+#define SCB_AHBSCR_INITCOUNT_Pos           11U                                            /*!< SCB AHBSCR: INITCOUNT Position */
+#define SCB_AHBSCR_INITCOUNT_Msk           (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos)           /*!< SCB AHBSCR: INITCOUNT Mask */
+
+#define SCB_AHBSCR_TPRI_Pos                 2U                                            /*!< SCB AHBSCR: TPRI Position */
+#define SCB_AHBSCR_TPRI_Msk                (0x1FFUL << SCB_AHBPCR_TPRI_Pos)               /*!< SCB AHBSCR: TPRI Mask */
+
+#define SCB_AHBSCR_CTL_Pos                  0U                                            /*!< SCB AHBSCR: CTL Position*/
+#define SCB_AHBSCR_CTL_Msk                 (3UL /*<< SCB_AHBPCR_CTL_Pos*/)                /*!< SCB AHBSCR: CTL Mask */
+
+/* Auxiliary Bus Fault Status Register Definitions */
+#define SCB_ABFSR_AXIMTYPE_Pos              8U                                            /*!< SCB ABFSR: AXIMTYPE Position*/
+#define SCB_ABFSR_AXIMTYPE_Msk             (3UL << SCB_ABFSR_AXIMTYPE_Pos)                /*!< SCB ABFSR: AXIMTYPE Mask */
+
+#define SCB_ABFSR_EPPB_Pos                  4U                                            /*!< SCB ABFSR: EPPB Position*/
+#define SCB_ABFSR_EPPB_Msk                 (1UL << SCB_ABFSR_EPPB_Pos)                    /*!< SCB ABFSR: EPPB Mask */
+
+#define SCB_ABFSR_AXIM_Pos                  3U                                            /*!< SCB ABFSR: AXIM Position*/
+#define SCB_ABFSR_AXIM_Msk                 (1UL << SCB_ABFSR_AXIM_Pos)                    /*!< SCB ABFSR: AXIM Mask */
+
+#define SCB_ABFSR_AHBP_Pos                  2U                                            /*!< SCB ABFSR: AHBP Position*/
+#define SCB_ABFSR_AHBP_Msk                 (1UL << SCB_ABFSR_AHBP_Pos)                    /*!< SCB ABFSR: AHBP Mask */
+
+#define SCB_ABFSR_DTCM_Pos                  1U                                            /*!< SCB ABFSR: DTCM Position*/
+#define SCB_ABFSR_DTCM_Msk                 (1UL << SCB_ABFSR_DTCM_Pos)                    /*!< SCB ABFSR: DTCM Mask */
+
+#define SCB_ABFSR_ITCM_Pos                  0U                                            /*!< SCB ABFSR: ITCM Position*/
+#define SCB_ABFSR_ITCM_Msk                 (1UL /*<< SCB_ABFSR_ITCM_Pos*/)                /*!< SCB ABFSR: ITCM Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+  \brief    Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+        uint32_t RESERVED0[1U];
+  __IM  uint32_t ICTR;                   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register */
+  __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */
+  __IOM uint32_t CPPWR;                  /*!< Offset: 0x00C (R/W)  Coprocessor Power Control  Register */
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos         0U                                         /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
+  \brief    Type definitions for the Instrumentation Trace Macrocell (ITM)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+  __OM  union
+  {
+    __OM  uint8_t    u8;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */
+    __OM  uint16_t   u16;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */
+    __OM  uint32_t   u32;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */
+  }  PORT [32U];                         /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers */
+        uint32_t RESERVED0[864U];
+  __IOM uint32_t TER;                    /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register */
+        uint32_t RESERVED1[15U];
+  __IOM uint32_t TPR;                    /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */
+        uint32_t RESERVED2[15U];
+  __IOM uint32_t TCR;                    /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */
+        uint32_t RESERVED3[29U];
+  __OM  uint32_t IWR;                    /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register */
+  __IM  uint32_t IRR;                    /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register */
+  __IOM uint32_t IMCR;                   /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register */
+        uint32_t RESERVED4[43U];
+  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register */
+  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register */
+        uint32_t RESERVED5[1U];
+  __IM  uint32_t DEVARCH;                /*!< Offset: 0xFBC (R/ )  ITM Device Architecture Register */
+        uint32_t RESERVED6[4U];
+  __IM  uint32_t PID4;                   /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
+  __IM  uint32_t PID5;                   /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
+  __IM  uint32_t PID6;                   /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
+  __IM  uint32_t PID7;                   /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
+  __IM  uint32_t PID0;                   /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
+  __IM  uint32_t PID1;                   /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
+  __IM  uint32_t PID2;                   /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
+  __IM  uint32_t PID3;                   /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
+  __IM  uint32_t CID0;                   /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
+  __IM  uint32_t CID1;                   /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
+  __IM  uint32_t CID2;                   /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
+  __IM  uint32_t CID3;                   /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
+} ITM_Type;
+
+/* ITM Stimulus Port Register Definitions */
+#define ITM_STIM_DISABLED_Pos               1U                                            /*!< ITM STIM: DISABLED Position */
+#define ITM_STIM_DISABLED_Msk              (0x1UL << ITM_STIM_DISABLED_Pos)               /*!< ITM STIM: DISABLED Mask */
+
+#define ITM_STIM_FIFOREADY_Pos              0U                                            /*!< ITM STIM: FIFOREADY Position */
+#define ITM_STIM_FIFOREADY_Msk             (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/)          /*!< ITM STIM: FIFOREADY Mask */
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos                0U                                            /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk               (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/)            /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos                   23U                                            /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TRACEBUSID_Pos             16U                                            /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TRACEBUSID_Msk             (0x7FUL << ITM_TCR_TRACEBUSID_Pos)             /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos                10U                                            /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPRESCALE_Pos              8U                                            /*!< ITM TCR: TSPRESCALE Position */
+#define ITM_TCR_TSPRESCALE_Msk             (3UL << ITM_TCR_TSPRESCALE_Pos)                /*!< ITM TCR: TSPRESCALE Mask */
+
+#define ITM_TCR_STALLENA_Pos                5U                                            /*!< ITM TCR: STALLENA Position */
+#define ITM_TCR_STALLENA_Msk               (1UL << ITM_TCR_STALLENA_Pos)                  /*!< ITM TCR: STALLENA Mask */
+
+#define ITM_TCR_SWOENA_Pos                  4U                                            /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos                  3U                                            /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos                 2U                                            /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos                   1U                                            /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos                  0U                                            /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos                0U                                            /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk               (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)              /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos                0U                                            /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk               (1UL /*<< ITM_IRR_ATREADYM_Pos*/)              /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos            0U                                            /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk           (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)          /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos                 2U                                            /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos                  1U                                            /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos                 0U                                            /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
+  \brief    Type definitions for the Data Watchpoint and Trace (DWT)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */
+  __IOM uint32_t CYCCNT;                 /*!< Offset: 0x004 (R/W)  Cycle Count Register */
+  __IOM uint32_t CPICNT;                 /*!< Offset: 0x008 (R/W)  CPI Count Register */
+  __IOM uint32_t EXCCNT;                 /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register */
+  __IOM uint32_t SLEEPCNT;               /*!< Offset: 0x010 (R/W)  Sleep Count Register */
+  __IOM uint32_t LSUCNT;                 /*!< Offset: 0x014 (R/W)  LSU Count Register */
+  __IOM uint32_t FOLDCNT;                /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register */
+  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */
+  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */
+        uint32_t RESERVED1[1U];
+  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */
+        uint32_t RESERVED2[1U];
+  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */
+        uint32_t RESERVED3[1U];
+  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */
+        uint32_t RESERVED4[1U];
+  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */
+        uint32_t RESERVED5[1U];
+  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */
+        uint32_t RESERVED6[1U];
+  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */
+        uint32_t RESERVED7[1U];
+  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */
+        uint32_t RESERVED8[1U];
+  __IOM uint32_t COMP4;                  /*!< Offset: 0x060 (R/W)  Comparator Register 4 */
+        uint32_t RESERVED9[1U];
+  __IOM uint32_t FUNCTION4;              /*!< Offset: 0x068 (R/W)  Function Register 4 */
+        uint32_t RESERVED10[1U];
+  __IOM uint32_t COMP5;                  /*!< Offset: 0x070 (R/W)  Comparator Register 5 */
+        uint32_t RESERVED11[1U];
+  __IOM uint32_t FUNCTION5;              /*!< Offset: 0x078 (R/W)  Function Register 5 */
+        uint32_t RESERVED12[1U];
+  __IOM uint32_t COMP6;                  /*!< Offset: 0x080 (R/W)  Comparator Register 6 */
+        uint32_t RESERVED13[1U];
+  __IOM uint32_t FUNCTION6;              /*!< Offset: 0x088 (R/W)  Function Register 6 */
+        uint32_t RESERVED14[1U];
+  __IOM uint32_t COMP7;                  /*!< Offset: 0x090 (R/W)  Comparator Register 7 */
+        uint32_t RESERVED15[1U];
+  __IOM uint32_t FUNCTION7;              /*!< Offset: 0x098 (R/W)  Function Register 7 */
+        uint32_t RESERVED16[1U];
+  __IOM uint32_t COMP8;                  /*!< Offset: 0x0A0 (R/W)  Comparator Register 8 */
+        uint32_t RESERVED17[1U];
+  __IOM uint32_t FUNCTION8;              /*!< Offset: 0x0A8 (R/W)  Function Register 8 */
+        uint32_t RESERVED18[1U];
+  __IOM uint32_t COMP9;                  /*!< Offset: 0x0B0 (R/W)  Comparator Register 9 */
+        uint32_t RESERVED19[1U];
+  __IOM uint32_t FUNCTION9;              /*!< Offset: 0x0B8 (R/W)  Function Register 9 */
+        uint32_t RESERVED20[1U];
+  __IOM uint32_t COMP10;                 /*!< Offset: 0x0C0 (R/W)  Comparator Register 10 */
+        uint32_t RESERVED21[1U];
+  __IOM uint32_t FUNCTION10;             /*!< Offset: 0x0C8 (R/W)  Function Register 10 */
+        uint32_t RESERVED22[1U];
+  __IOM uint32_t COMP11;                 /*!< Offset: 0x0D0 (R/W)  Comparator Register 11 */
+        uint32_t RESERVED23[1U];
+  __IOM uint32_t FUNCTION11;             /*!< Offset: 0x0D8 (R/W)  Function Register 11 */
+        uint32_t RESERVED24[1U];
+  __IOM uint32_t COMP12;                 /*!< Offset: 0x0E0 (R/W)  Comparator Register 12 */
+        uint32_t RESERVED25[1U];
+  __IOM uint32_t FUNCTION12;             /*!< Offset: 0x0E8 (R/W)  Function Register 12 */
+        uint32_t RESERVED26[1U];
+  __IOM uint32_t COMP13;                 /*!< Offset: 0x0F0 (R/W)  Comparator Register 13 */
+        uint32_t RESERVED27[1U];
+  __IOM uint32_t FUNCTION13;             /*!< Offset: 0x0F8 (R/W)  Function Register 13 */
+        uint32_t RESERVED28[1U];
+  __IOM uint32_t COMP14;                 /*!< Offset: 0x100 (R/W)  Comparator Register 14 */
+        uint32_t RESERVED29[1U];
+  __IOM uint32_t FUNCTION14;             /*!< Offset: 0x108 (R/W)  Function Register 14 */
+        uint32_t RESERVED30[1U];
+  __IOM uint32_t COMP15;                 /*!< Offset: 0x110 (R/W)  Comparator Register 15 */
+        uint32_t RESERVED31[1U];
+  __IOM uint32_t FUNCTION15;             /*!< Offset: 0x118 (R/W)  Function Register 15 */
+        uint32_t RESERVED32[934U];
+  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R  )  Lock Status Register */
+        uint32_t RESERVED33[1U];
+  __IM  uint32_t DEVARCH;                /*!< Offset: 0xFBC (R/ )  Device Architecture Register */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCDISS_Pos               23U                                         /*!< DWT CTRL: CYCDISS Position */
+#define DWT_CTRL_CYCDISS_Msk               (0x1UL << DWT_CTRL_CYCDISS_Pos)             /*!< DWT CTRL: CYCDISS Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos             22U                                         /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos            21U                                         /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos             20U                                         /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos           19U                                         /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos             18U                                         /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos             17U                                         /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos             16U                                         /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos            12U                                         /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos               10U                                         /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos                 9U                                         /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos               5U                                         /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos             1U                                         /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos              0U                                         /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos               0U                                         /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos               0U                                         /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos           0U                                         /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos               0U                                         /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos             0U                                         /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_ID_Pos                27U                                         /*!< DWT FUNCTION: ID Position */
+#define DWT_FUNCTION_ID_Msk                (0x1FUL << DWT_FUNCTION_ID_Pos)             /*!< DWT FUNCTION: ID Mask */
+
+#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_ACTION_Pos             4U                                         /*!< DWT FUNCTION: ACTION Position */
+#define DWT_FUNCTION_ACTION_Msk            (0x1UL << DWT_FUNCTION_ACTION_Pos)          /*!< DWT FUNCTION: ACTION Mask */
+
+#define DWT_FUNCTION_MATCH_Pos              0U                                         /*!< DWT FUNCTION: MATCH Position */
+#define DWT_FUNCTION_MATCH_Msk             (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/)       /*!< DWT FUNCTION: MATCH Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_TPI     Trace Port Interface (TPI)
+  \brief    Type definitions for the Trace Port Interface (TPI)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+  __IM  uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Sizes Register */
+  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Sizes Register */
+        uint32_t RESERVED0[2U];
+  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
+        uint32_t RESERVED1[55U];
+  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
+        uint32_t RESERVED2[131U];
+  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
+  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
+  __IOM uint32_t PSCR;                   /*!< Offset: 0x308 (R/W)  Periodic Synchronization Control Register */
+        uint32_t RESERVED3[809U];
+  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  Software Lock Access Register */
+  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  Software Lock Status Register */
+        uint32_t RESERVED4[4U];
+  __IM  uint32_t TYPE;                   /*!< Offset: 0xFC8 (R/ )  Device Identifier Register */
+  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  Device Type Register */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_SWOSCALER_Pos              0U                                         /*!< TPI ACPR: SWOSCALER Position */
+#define TPI_ACPR_SWOSCALER_Msk             (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/)    /*!< TPI ACPR: SWOSCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_FOnMan_Pos                 6U                                         /*!< TPI FFCR: FOnMan Position */
+#define TPI_FFCR_FOnMan_Msk                (0x1UL << TPI_FFCR_FOnMan_Pos)              /*!< TPI FFCR: FOnMan Mask */
+
+#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI Periodic Synchronization Control Register Definitions */
+#define TPI_PSCR_PSCount_Pos                0U                                         /*!< TPI PSCR: PSCount Position */
+#define TPI_PSCR_PSCount_Msk               (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/)        /*!< TPI PSCR: TPSCount Mask */
+
+/* TPI Software Lock Status Register Definitions */
+#define TPI_LSR_nTT_Pos                     1U                                         /*!< TPI LSR: Not thirty-two bit. Position */
+#define TPI_LSR_nTT_Msk                    (0x1UL << TPI_LSR_nTT_Pos)                  /*!< TPI LSR: Not thirty-two bit. Mask */
+
+#define TPI_LSR_SLK_Pos                     1U                                         /*!< TPI LSR: Software Lock status Position */
+#define TPI_LSR_SLK_Msk                    (0x1UL << TPI_LSR_SLK_Pos)                  /*!< TPI LSR: Software Lock status Mask */
+
+#define TPI_LSR_SLI_Pos                     0U                                         /*!< TPI LSR: Software Lock implemented Position */
+#define TPI_LSR_SLI_Msk                    (0x1UL /*<< TPI_LSR_SLI_Pos*/)              /*!< TPI LSR: Software Lock implemented Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_FIFOSZ_Pos                6U                                         /*!< TPI DEVID: FIFO depth Position */
+#define TPI_DEVID_FIFOSZ_Msk               (0x7UL << TPI_DEVID_FIFOSZ_Pos)             /*!< TPI DEVID: FIFO depth Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos             4U                                         /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos           0U                                         /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+  \brief    Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region Number Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
+  __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  MPU Region Limit Address Register */
+  __IOM uint32_t RBAR_A1;                /*!< Offset: 0x014 (R/W)  MPU Region Base Address Register Alias 1 */
+  __IOM uint32_t RLAR_A1;                /*!< Offset: 0x018 (R/W)  MPU Region Limit Address Register Alias 1 */
+  __IOM uint32_t RBAR_A2;                /*!< Offset: 0x01C (R/W)  MPU Region Base Address Register Alias 2 */
+  __IOM uint32_t RLAR_A2;                /*!< Offset: 0x020 (R/W)  MPU Region Limit Address Register Alias 2 */
+  __IOM uint32_t RBAR_A3;                /*!< Offset: 0x024 (R/W)  MPU Region Base Address Register Alias 3 */
+  __IOM uint32_t RLAR_A3;                /*!< Offset: 0x028 (R/W)  MPU Region Limit Address Register Alias 3 */
+        uint32_t RESERVED0[1];
+  union {
+  __IOM uint32_t MAIR[2];
+  struct {
+  __IOM uint32_t MAIR0;                  /*!< Offset: 0x030 (R/W)  MPU Memory Attribute Indirection Register 0 */
+  __IOM uint32_t MAIR1;                  /*!< Offset: 0x034 (R/W)  MPU Memory Attribute Indirection Register 1 */
+  };
+  };
+} MPU_Type;
+
+#define MPU_TYPE_RALIASES                  4U
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_BASE_Pos                   5U                                            /*!< MPU RBAR: BASE Position */
+#define MPU_RBAR_BASE_Msk                  (0x7FFFFFFUL << MPU_RBAR_BASE_Pos)             /*!< MPU RBAR: BASE Mask */
+
+#define MPU_RBAR_SH_Pos                     3U                                            /*!< MPU RBAR: SH Position */
+#define MPU_RBAR_SH_Msk                    (0x3UL << MPU_RBAR_SH_Pos)                     /*!< MPU RBAR: SH Mask */
+
+#define MPU_RBAR_AP_Pos                     1U                                            /*!< MPU RBAR: AP Position */
+#define MPU_RBAR_AP_Msk                    (0x3UL << MPU_RBAR_AP_Pos)                     /*!< MPU RBAR: AP Mask */
+
+#define MPU_RBAR_XN_Pos                     0U                                            /*!< MPU RBAR: XN Position */
+#define MPU_RBAR_XN_Msk                    (01UL /*<< MPU_RBAR_XN_Pos*/)                  /*!< MPU RBAR: XN Mask */
+
+/* MPU Region Limit Address Register Definitions */
+#define MPU_RLAR_LIMIT_Pos                  5U                                            /*!< MPU RLAR: LIMIT Position */
+#define MPU_RLAR_LIMIT_Msk                 (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos)            /*!< MPU RLAR: LIMIT Mask */
+
+#define MPU_RLAR_AttrIndx_Pos               1U                                            /*!< MPU RLAR: AttrIndx Position */
+#define MPU_RLAR_AttrIndx_Msk              (0x7UL << MPU_RLAR_AttrIndx_Pos)               /*!< MPU RLAR: AttrIndx Mask */
+
+#define MPU_RLAR_EN_Pos                     0U                                            /*!< MPU RLAR: Region enable bit Position */
+#define MPU_RLAR_EN_Msk                    (1UL /*<< MPU_RLAR_EN_Pos*/)                   /*!< MPU RLAR: Region enable bit Disable Mask */
+
+/* MPU Memory Attribute Indirection Register 0 Definitions */
+#define MPU_MAIR0_Attr3_Pos                24U                                            /*!< MPU MAIR0: Attr3 Position */
+#define MPU_MAIR0_Attr3_Msk                (0xFFUL << MPU_MAIR0_Attr3_Pos)                /*!< MPU MAIR0: Attr3 Mask */
+
+#define MPU_MAIR0_Attr2_Pos                16U                                            /*!< MPU MAIR0: Attr2 Position */
+#define MPU_MAIR0_Attr2_Msk                (0xFFUL << MPU_MAIR0_Attr2_Pos)                /*!< MPU MAIR0: Attr2 Mask */
+
+#define MPU_MAIR0_Attr1_Pos                 8U                                            /*!< MPU MAIR0: Attr1 Position */
+#define MPU_MAIR0_Attr1_Msk                (0xFFUL << MPU_MAIR0_Attr1_Pos)                /*!< MPU MAIR0: Attr1 Mask */
+
+#define MPU_MAIR0_Attr0_Pos                 0U                                            /*!< MPU MAIR0: Attr0 Position */
+#define MPU_MAIR0_Attr0_Msk                (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/)            /*!< MPU MAIR0: Attr0 Mask */
+
+/* MPU Memory Attribute Indirection Register 1 Definitions */
+#define MPU_MAIR1_Attr7_Pos                24U                                            /*!< MPU MAIR1: Attr7 Position */
+#define MPU_MAIR1_Attr7_Msk                (0xFFUL << MPU_MAIR1_Attr7_Pos)                /*!< MPU MAIR1: Attr7 Mask */
+
+#define MPU_MAIR1_Attr6_Pos                16U                                            /*!< MPU MAIR1: Attr6 Position */
+#define MPU_MAIR1_Attr6_Msk                (0xFFUL << MPU_MAIR1_Attr6_Pos)                /*!< MPU MAIR1: Attr6 Mask */
+
+#define MPU_MAIR1_Attr5_Pos                 8U                                            /*!< MPU MAIR1: Attr5 Position */
+#define MPU_MAIR1_Attr5_Msk                (0xFFUL << MPU_MAIR1_Attr5_Pos)                /*!< MPU MAIR1: Attr5 Mask */
+
+#define MPU_MAIR1_Attr4_Pos                 0U                                            /*!< MPU MAIR1: Attr4 Position */
+#define MPU_MAIR1_Attr4_Msk                (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/)            /*!< MPU MAIR1: Attr4 Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SAU     Security Attribution Unit (SAU)
+  \brief    Type definitions for the Security Attribution Unit (SAU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Security Attribution Unit (SAU).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SAU Control Register */
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x004 (R/ )  SAU Type Register */
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  SAU Region Number Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  SAU Region Base Address Register */
+  __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  SAU Region Limit Address Register */
+#else
+        uint32_t RESERVED0[3];
+#endif
+  __IOM uint32_t SFSR;                   /*!< Offset: 0x014 (R/W)  Secure Fault Status Register */
+  __IOM uint32_t SFAR;                   /*!< Offset: 0x018 (R/W)  Secure Fault Address Register */
+} SAU_Type;
+
+/* SAU Control Register Definitions */
+#define SAU_CTRL_ALLNS_Pos                  1U                                            /*!< SAU CTRL: ALLNS Position */
+#define SAU_CTRL_ALLNS_Msk                 (1UL << SAU_CTRL_ALLNS_Pos)                    /*!< SAU CTRL: ALLNS Mask */
+
+#define SAU_CTRL_ENABLE_Pos                 0U                                            /*!< SAU CTRL: ENABLE Position */
+#define SAU_CTRL_ENABLE_Msk                (1UL /*<< SAU_CTRL_ENABLE_Pos*/)               /*!< SAU CTRL: ENABLE Mask */
+
+/* SAU Type Register Definitions */
+#define SAU_TYPE_SREGION_Pos                0U                                            /*!< SAU TYPE: SREGION Position */
+#define SAU_TYPE_SREGION_Msk               (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/)           /*!< SAU TYPE: SREGION Mask */
+
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+/* SAU Region Number Register Definitions */
+#define SAU_RNR_REGION_Pos                  0U                                            /*!< SAU RNR: REGION Position */
+#define SAU_RNR_REGION_Msk                 (0xFFUL /*<< SAU_RNR_REGION_Pos*/)             /*!< SAU RNR: REGION Mask */
+
+/* SAU Region Base Address Register Definitions */
+#define SAU_RBAR_BADDR_Pos                  5U                                            /*!< SAU RBAR: BADDR Position */
+#define SAU_RBAR_BADDR_Msk                 (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos)            /*!< SAU RBAR: BADDR Mask */
+
+/* SAU Region Limit Address Register Definitions */
+#define SAU_RLAR_LADDR_Pos                  5U                                            /*!< SAU RLAR: LADDR Position */
+#define SAU_RLAR_LADDR_Msk                 (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos)            /*!< SAU RLAR: LADDR Mask */
+
+#define SAU_RLAR_NSC_Pos                    1U                                            /*!< SAU RLAR: NSC Position */
+#define SAU_RLAR_NSC_Msk                   (1UL << SAU_RLAR_NSC_Pos)                      /*!< SAU RLAR: NSC Mask */
+
+#define SAU_RLAR_ENABLE_Pos                 0U                                            /*!< SAU RLAR: ENABLE Position */
+#define SAU_RLAR_ENABLE_Msk                (1UL /*<< SAU_RLAR_ENABLE_Pos*/)               /*!< SAU RLAR: ENABLE Mask */
+
+#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
+
+/* Secure Fault Status Register Definitions */
+#define SAU_SFSR_LSERR_Pos                  7U                                            /*!< SAU SFSR: LSERR Position */
+#define SAU_SFSR_LSERR_Msk                 (1UL << SAU_SFSR_LSERR_Pos)                    /*!< SAU SFSR: LSERR Mask */
+
+#define SAU_SFSR_SFARVALID_Pos              6U                                            /*!< SAU SFSR: SFARVALID Position */
+#define SAU_SFSR_SFARVALID_Msk             (1UL << SAU_SFSR_SFARVALID_Pos)                /*!< SAU SFSR: SFARVALID Mask */
+
+#define SAU_SFSR_LSPERR_Pos                 5U                                            /*!< SAU SFSR: LSPERR Position */
+#define SAU_SFSR_LSPERR_Msk                (1UL << SAU_SFSR_LSPERR_Pos)                   /*!< SAU SFSR: LSPERR Mask */
+
+#define SAU_SFSR_INVTRAN_Pos                4U                                            /*!< SAU SFSR: INVTRAN Position */
+#define SAU_SFSR_INVTRAN_Msk               (1UL << SAU_SFSR_INVTRAN_Pos)                  /*!< SAU SFSR: INVTRAN Mask */
+
+#define SAU_SFSR_AUVIOL_Pos                 3U                                            /*!< SAU SFSR: AUVIOL Position */
+#define SAU_SFSR_AUVIOL_Msk                (1UL << SAU_SFSR_AUVIOL_Pos)                   /*!< SAU SFSR: AUVIOL Mask */
+
+#define SAU_SFSR_INVER_Pos                  2U                                            /*!< SAU SFSR: INVER Position */
+#define SAU_SFSR_INVER_Msk                 (1UL << SAU_SFSR_INVER_Pos)                    /*!< SAU SFSR: INVER Mask */
+
+#define SAU_SFSR_INVIS_Pos                  1U                                            /*!< SAU SFSR: INVIS Position */
+#define SAU_SFSR_INVIS_Msk                 (1UL << SAU_SFSR_INVIS_Pos)                    /*!< SAU SFSR: INVIS Mask */
+
+#define SAU_SFSR_INVEP_Pos                  0U                                            /*!< SAU SFSR: INVEP Position */
+#define SAU_SFSR_INVEP_Msk                 (1UL /*<< SAU_SFSR_INVEP_Pos*/)                /*!< SAU SFSR: INVEP Mask */
+
+/*@} end of group CMSIS_SAU */
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_FPU     Floating Point Unit (FPU)
+  \brief    Type definitions for the Floating Point Unit (FPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Floating Point Unit (FPU).
+ */
+typedef struct
+{
+        uint32_t RESERVED0[1U];
+  __IOM uint32_t FPCCR;                  /*!< Offset: 0x004 (R/W)  Floating-Point Context Control Register */
+  __IOM uint32_t FPCAR;                  /*!< Offset: 0x008 (R/W)  Floating-Point Context Address Register */
+  __IOM uint32_t FPDSCR;                 /*!< Offset: 0x00C (R/W)  Floating-Point Default Status Control Register */
+  __IM  uint32_t MVFR0;                  /*!< Offset: 0x010 (R/ )  Media and FP Feature Register 0 */
+  __IM  uint32_t MVFR1;                  /*!< Offset: 0x014 (R/ )  Media and FP Feature Register 1 */
+} FPU_Type;
+
+/* Floating-Point Context Control Register Definitions */
+#define FPU_FPCCR_ASPEN_Pos                31U                                            /*!< FPCCR: ASPEN bit Position */
+#define FPU_FPCCR_ASPEN_Msk                (1UL << FPU_FPCCR_ASPEN_Pos)                   /*!< FPCCR: ASPEN bit Mask */
+
+#define FPU_FPCCR_LSPEN_Pos                30U                                            /*!< FPCCR: LSPEN Position */
+#define FPU_FPCCR_LSPEN_Msk                (1UL << FPU_FPCCR_LSPEN_Pos)                   /*!< FPCCR: LSPEN bit Mask */
+
+#define FPU_FPCCR_LSPENS_Pos               29U                                            /*!< FPCCR: LSPENS Position */
+#define FPU_FPCCR_LSPENS_Msk               (1UL << FPU_FPCCR_LSPENS_Pos)                  /*!< FPCCR: LSPENS bit Mask */
+
+#define FPU_FPCCR_CLRONRET_Pos             28U                                            /*!< FPCCR: CLRONRET Position */
+#define FPU_FPCCR_CLRONRET_Msk             (1UL << FPU_FPCCR_CLRONRET_Pos)                /*!< FPCCR: CLRONRET bit Mask */
+
+#define FPU_FPCCR_CLRONRETS_Pos            27U                                            /*!< FPCCR: CLRONRETS Position */
+#define FPU_FPCCR_CLRONRETS_Msk            (1UL << FPU_FPCCR_CLRONRETS_Pos)               /*!< FPCCR: CLRONRETS bit Mask */
+
+#define FPU_FPCCR_TS_Pos                   26U                                            /*!< FPCCR: TS Position */
+#define FPU_FPCCR_TS_Msk                   (1UL << FPU_FPCCR_TS_Pos)                      /*!< FPCCR: TS bit Mask */
+
+#define FPU_FPCCR_UFRDY_Pos                10U                                            /*!< FPCCR: UFRDY Position */
+#define FPU_FPCCR_UFRDY_Msk                (1UL << FPU_FPCCR_UFRDY_Pos)                   /*!< FPCCR: UFRDY bit Mask */
+
+#define FPU_FPCCR_SPLIMVIOL_Pos             9U                                            /*!< FPCCR: SPLIMVIOL Position */
+#define FPU_FPCCR_SPLIMVIOL_Msk            (1UL << FPU_FPCCR_SPLIMVIOL_Pos)               /*!< FPCCR: SPLIMVIOL bit Mask */
+
+#define FPU_FPCCR_MONRDY_Pos                8U                                            /*!< FPCCR: MONRDY Position */
+#define FPU_FPCCR_MONRDY_Msk               (1UL << FPU_FPCCR_MONRDY_Pos)                  /*!< FPCCR: MONRDY bit Mask */
+
+#define FPU_FPCCR_SFRDY_Pos                 7U                                            /*!< FPCCR: SFRDY Position */
+#define FPU_FPCCR_SFRDY_Msk                (1UL << FPU_FPCCR_SFRDY_Pos)                   /*!< FPCCR: SFRDY bit Mask */
+
+#define FPU_FPCCR_BFRDY_Pos                 6U                                            /*!< FPCCR: BFRDY Position */
+#define FPU_FPCCR_BFRDY_Msk                (1UL << FPU_FPCCR_BFRDY_Pos)                   /*!< FPCCR: BFRDY bit Mask */
+
+#define FPU_FPCCR_MMRDY_Pos                 5U                                            /*!< FPCCR: MMRDY Position */
+#define FPU_FPCCR_MMRDY_Msk                (1UL << FPU_FPCCR_MMRDY_Pos)                   /*!< FPCCR: MMRDY bit Mask */
+
+#define FPU_FPCCR_HFRDY_Pos                 4U                                            /*!< FPCCR: HFRDY Position */
+#define FPU_FPCCR_HFRDY_Msk                (1UL << FPU_FPCCR_HFRDY_Pos)                   /*!< FPCCR: HFRDY bit Mask */
+
+#define FPU_FPCCR_THREAD_Pos                3U                                            /*!< FPCCR: processor mode bit Position */
+#define FPU_FPCCR_THREAD_Msk               (1UL << FPU_FPCCR_THREAD_Pos)                  /*!< FPCCR: processor mode active bit Mask */
+
+#define FPU_FPCCR_S_Pos                     2U                                            /*!< FPCCR: Security status of the FP context bit Position */
+#define FPU_FPCCR_S_Msk                    (1UL << FPU_FPCCR_S_Pos)                       /*!< FPCCR: Security status of the FP context bit Mask */
+
+#define FPU_FPCCR_USER_Pos                  1U                                            /*!< FPCCR: privilege level bit Position */
+#define FPU_FPCCR_USER_Msk                 (1UL << FPU_FPCCR_USER_Pos)                    /*!< FPCCR: privilege level bit Mask */
+
+#define FPU_FPCCR_LSPACT_Pos                0U                                            /*!< FPCCR: Lazy state preservation active bit Position */
+#define FPU_FPCCR_LSPACT_Msk               (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)              /*!< FPCCR: Lazy state preservation active bit Mask */
+
+/* Floating-Point Context Address Register Definitions */
+#define FPU_FPCAR_ADDRESS_Pos               3U                                            /*!< FPCAR: ADDRESS bit Position */
+#define FPU_FPCAR_ADDRESS_Msk              (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)        /*!< FPCAR: ADDRESS bit Mask */
+
+/* Floating-Point Default Status Control Register Definitions */
+#define FPU_FPDSCR_AHP_Pos                 26U                                            /*!< FPDSCR: AHP bit Position */
+#define FPU_FPDSCR_AHP_Msk                 (1UL << FPU_FPDSCR_AHP_Pos)                    /*!< FPDSCR: AHP bit Mask */
+
+#define FPU_FPDSCR_DN_Pos                  25U                                            /*!< FPDSCR: DN bit Position */
+#define FPU_FPDSCR_DN_Msk                  (1UL << FPU_FPDSCR_DN_Pos)                     /*!< FPDSCR: DN bit Mask */
+
+#define FPU_FPDSCR_FZ_Pos                  24U                                            /*!< FPDSCR: FZ bit Position */
+#define FPU_FPDSCR_FZ_Msk                  (1UL << FPU_FPDSCR_FZ_Pos)                     /*!< FPDSCR: FZ bit Mask */
+
+#define FPU_FPDSCR_RMode_Pos               22U                                            /*!< FPDSCR: RMode bit Position */
+#define FPU_FPDSCR_RMode_Msk               (3UL << FPU_FPDSCR_RMode_Pos)                  /*!< FPDSCR: RMode bit Mask */
+
+/* Media and FP Feature Register 0 Definitions */
+#define FPU_MVFR0_FP_rounding_modes_Pos    28U                                            /*!< MVFR0: FP rounding modes bits Position */
+#define FPU_MVFR0_FP_rounding_modes_Msk    (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)     /*!< MVFR0: FP rounding modes bits Mask */
+
+#define FPU_MVFR0_Short_vectors_Pos        24U                                            /*!< MVFR0: Short vectors bits Position */
+#define FPU_MVFR0_Short_vectors_Msk        (0xFUL << FPU_MVFR0_Short_vectors_Pos)         /*!< MVFR0: Short vectors bits Mask */
+
+#define FPU_MVFR0_Square_root_Pos          20U                                            /*!< MVFR0: Square root bits Position */
+#define FPU_MVFR0_Square_root_Msk          (0xFUL << FPU_MVFR0_Square_root_Pos)           /*!< MVFR0: Square root bits Mask */
+
+#define FPU_MVFR0_Divide_Pos               16U                                            /*!< MVFR0: Divide bits Position */
+#define FPU_MVFR0_Divide_Msk               (0xFUL << FPU_MVFR0_Divide_Pos)                /*!< MVFR0: Divide bits Mask */
+
+#define FPU_MVFR0_FP_excep_trapping_Pos    12U                                            /*!< MVFR0: FP exception trapping bits Position */
+#define FPU_MVFR0_FP_excep_trapping_Msk    (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)     /*!< MVFR0: FP exception trapping bits Mask */
+
+#define FPU_MVFR0_Double_precision_Pos      8U                                            /*!< MVFR0: Double-precision bits Position */
+#define FPU_MVFR0_Double_precision_Msk     (0xFUL << FPU_MVFR0_Double_precision_Pos)      /*!< MVFR0: Double-precision bits Mask */
+
+#define FPU_MVFR0_Single_precision_Pos      4U                                            /*!< MVFR0: Single-precision bits Position */
+#define FPU_MVFR0_Single_precision_Msk     (0xFUL << FPU_MVFR0_Single_precision_Pos)      /*!< MVFR0: Single-precision bits Mask */
+
+#define FPU_MVFR0_A_SIMD_registers_Pos      0U                                            /*!< MVFR0: A_SIMD registers bits Position */
+#define FPU_MVFR0_A_SIMD_registers_Msk     (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)  /*!< MVFR0: A_SIMD registers bits Mask */
+
+/* Media and FP Feature Register 1 Definitions */
+#define FPU_MVFR1_FP_fused_MAC_Pos         28U                                            /*!< MVFR1: FP fused MAC bits Position */
+#define FPU_MVFR1_FP_fused_MAC_Msk         (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)          /*!< MVFR1: FP fused MAC bits Mask */
+
+#define FPU_MVFR1_FP_HPFP_Pos              24U                                            /*!< MVFR1: FP HPFP bits Position */
+#define FPU_MVFR1_FP_HPFP_Msk              (0xFUL << FPU_MVFR1_FP_HPFP_Pos)               /*!< MVFR1: FP HPFP bits Mask */
+
+#define FPU_MVFR1_D_NaN_mode_Pos            4U                                            /*!< MVFR1: D_NaN mode bits Position */
+#define FPU_MVFR1_D_NaN_mode_Msk           (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)            /*!< MVFR1: D_NaN mode bits Mask */
+
+#define FPU_MVFR1_FtZ_mode_Pos              0U                                            /*!< MVFR1: FtZ mode bits Position */
+#define FPU_MVFR1_FtZ_mode_Msk             (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)          /*!< MVFR1: FtZ mode bits Mask */
+
+/*@} end of group CMSIS_FPU */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    Type definitions for the Core Debug Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */
+  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */
+  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */
+  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
+        uint32_t RESERVED4[1U];
+  __IOM uint32_t DAUTHCTRL;              /*!< Offset: 0x014 (R/W)  Debug Authentication Control Register */
+  __IOM uint32_t DSCSR;                  /*!< Offset: 0x018 (R/W)  Debug Security Control and Status Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESTART_ST_Pos   26U                                            /*!< CoreDebug DHCSR: S_RESTART_ST Position */
+#define CoreDebug_DHCSR_S_RESTART_ST_Msk   (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)      /*!< CoreDebug DHCSR: S_RESTART_ST Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5U                                            /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos         24U                                            /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos        19U                                            /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos       18U                                            /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos       17U                                            /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos         16U                                            /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos       9U                                            /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos       8U                                            /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos      7U                                            /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos       6U                                            /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5U                                            /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos        4U                                            /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/* Debug Authentication Control Register Definitions */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos  3U                                            /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)    /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */
+
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos  2U                                            /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)    /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */
+
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos   1U                                            /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk  (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)     /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */
+
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos   0U                                            /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk  (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */
+
+/* Debug Security Control and Status Register Definitions */
+#define CoreDebug_DSCSR_CDS_Pos            16U                                            /*!< CoreDebug DSCSR: CDS Position */
+#define CoreDebug_DSCSR_CDS_Msk            (1UL << CoreDebug_DSCSR_CDS_Pos)               /*!< CoreDebug DSCSR: CDS Mask */
+
+#define CoreDebug_DSCSR_SBRSEL_Pos          1U                                            /*!< CoreDebug DSCSR: SBRSEL Position */
+#define CoreDebug_DSCSR_SBRSEL_Msk         (1UL << CoreDebug_DSCSR_SBRSEL_Pos)            /*!< CoreDebug DSCSR: SBRSEL Mask */
+
+#define CoreDebug_DSCSR_SBRSELEN_Pos        0U                                            /*!< CoreDebug DSCSR: SBRSELEN Position */
+#define CoreDebug_DSCSR_SBRSELEN_Msk       (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/)      /*!< CoreDebug DSCSR: SBRSELEN Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Core Hardware */
+  #define SCS_BASE            (0xE000E000UL)                             /*!< System Control Space Base Address */
+  #define ITM_BASE            (0xE0000000UL)                             /*!< ITM Base Address */
+  #define DWT_BASE            (0xE0001000UL)                             /*!< DWT Base Address */
+  #define TPI_BASE            (0xE0040000UL)                             /*!< TPI Base Address */
+  #define CoreDebug_BASE      (0xE000EDF0UL)                             /*!< Core Debug Base Address */
+  #define SysTick_BASE        (SCS_BASE +  0x0010UL)                     /*!< SysTick Base Address */
+  #define NVIC_BASE           (SCS_BASE +  0x0100UL)                     /*!< NVIC Base Address */
+  #define SCB_BASE            (SCS_BASE +  0x0D00UL)                     /*!< System Control Block Base Address */
+
+  #define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE         ) /*!< System control Register not in SCB */
+  #define SCB                 ((SCB_Type       *)     SCB_BASE         ) /*!< SCB configuration struct */
+  #define SysTick             ((SysTick_Type   *)     SysTick_BASE     ) /*!< SysTick configuration struct */
+  #define NVIC                ((NVIC_Type      *)     NVIC_BASE        ) /*!< NVIC configuration struct */
+  #define ITM                 ((ITM_Type       *)     ITM_BASE         ) /*!< ITM configuration struct */
+  #define DWT                 ((DWT_Type       *)     DWT_BASE         ) /*!< DWT configuration struct */
+  #define TPI                 ((TPI_Type       *)     TPI_BASE         ) /*!< TPI configuration struct */
+  #define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE   ) /*!< Core Debug configuration struct */
+
+  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+    #define MPU_BASE          (SCS_BASE +  0x0D90UL)                     /*!< Memory Protection Unit */
+    #define MPU               ((MPU_Type       *)     MPU_BASE         ) /*!< Memory Protection Unit */
+  #endif
+
+  #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+    #define SAU_BASE          (SCS_BASE +  0x0DD0UL)                     /*!< Security Attribution Unit */
+    #define SAU               ((SAU_Type       *)     SAU_BASE         ) /*!< Security Attribution Unit */
+  #endif
+
+  #define FPU_BASE            (SCS_BASE +  0x0F30UL)                     /*!< Floating Point Unit */
+  #define FPU                 ((FPU_Type       *)     FPU_BASE         ) /*!< Floating Point Unit */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+  #define SCS_BASE_NS         (0xE002E000UL)                             /*!< System Control Space Base Address (non-secure address space) */
+  #define CoreDebug_BASE_NS   (0xE002EDF0UL)                             /*!< Core Debug Base Address           (non-secure address space) */
+  #define SysTick_BASE_NS     (SCS_BASE_NS +  0x0010UL)                  /*!< SysTick Base Address              (non-secure address space) */
+  #define NVIC_BASE_NS        (SCS_BASE_NS +  0x0100UL)                  /*!< NVIC Base Address                 (non-secure address space) */
+  #define SCB_BASE_NS         (SCS_BASE_NS +  0x0D00UL)                  /*!< System Control Block Base Address (non-secure address space) */
+
+  #define SCnSCB_NS           ((SCnSCB_Type    *)     SCS_BASE_NS      ) /*!< System control Register not in SCB(non-secure address space) */
+  #define SCB_NS              ((SCB_Type       *)     SCB_BASE_NS      ) /*!< SCB configuration struct          (non-secure address space) */
+  #define SysTick_NS          ((SysTick_Type   *)     SysTick_BASE_NS  ) /*!< SysTick configuration struct      (non-secure address space) */
+  #define NVIC_NS             ((NVIC_Type      *)     NVIC_BASE_NS     ) /*!< NVIC configuration struct         (non-secure address space) */
+  #define CoreDebug_NS        ((CoreDebug_Type *)     CoreDebug_BASE_NS) /*!< Core Debug configuration struct   (non-secure address space) */
+
+  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+    #define MPU_BASE_NS       (SCS_BASE_NS +  0x0D90UL)                  /*!< Memory Protection Unit            (non-secure address space) */
+    #define MPU_NS            ((MPU_Type       *)     MPU_BASE_NS      ) /*!< Memory Protection Unit            (non-secure address space) */
+  #endif
+
+  #define FPU_BASE_NS         (SCS_BASE_NS +  0x0F30UL)                  /*!< Floating Point Unit               (non-secure address space) */
+  #define FPU_NS              ((FPU_Type       *)     FPU_BASE_NS      ) /*!< Floating Point Unit               (non-secure address space) */
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Debug Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+  #endif
+  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
+  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
+  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
+  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
+  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
+  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+  #define NVIC_GetActive              __NVIC_GetActive
+  #define NVIC_SetPriority            __NVIC_SetPriority
+  #define NVIC_GetPriority            __NVIC_GetPriority
+  #define NVIC_SystemReset            __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+  #endif
+  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetVector              __NVIC_SetVector
+  #define NVIC_GetVector              __NVIC_GetVector
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET          16
+
+
+/* Special LR values for Secure/Non-Secure call handling and exception handling                                               */
+
+/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS                   */
+#define FNC_RETURN                 (0xFEFFFFFFUL)     /* bit [0] ignored when processing a branch                             */
+
+/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */
+#define EXC_RETURN_PREFIX          (0xFF000000UL)     /* bits [31:24] set to indicate an EXC_RETURN value                     */
+#define EXC_RETURN_S               (0x00000040UL)     /* bit [6] stack used to push registers: 0=Non-secure 1=Secure          */
+#define EXC_RETURN_DCRS            (0x00000020UL)     /* bit [5] stacking rules for called registers: 0=skipped 1=saved       */
+#define EXC_RETURN_FTYPE           (0x00000010UL)     /* bit [4] allocate stack for floating-point context: 0=done 1=skipped  */
+#define EXC_RETURN_MODE            (0x00000008UL)     /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode      */
+#define EXC_RETURN_SPSEL           (0x00000002UL)     /* bit [1] stack pointer used to restore context: 0=MSP 1=PSP           */
+#define EXC_RETURN_ES              (0x00000001UL)     /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */
+
+/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking                            */
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)  /* Value for processors with floating-point extension:                  */
+#define EXC_INTEGRITY_SIGNATURE     (0xFEFA125AUL)     /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE                   */
+#else
+#define EXC_INTEGRITY_SIGNATURE     (0xFEFA125BUL)     /* Value for processors without floating-point extension                */
+#endif
+
+
+/**
+  \brief   Set Priority Grouping
+  \details Sets the priority grouping field using the required unlock sequence.
+           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+           Only values from 0..7 are used.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]      PriorityGroup  Priority grouping field.
+ */
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+  uint32_t reg_value;
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
+
+  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
+  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */
+  reg_value  =  (reg_value                                   |
+                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                (PriorityGroupTmp << 8U)                      );              /* Insert write key and priorty group */
+  SCB->AIRCR =  reg_value;
+}
+
+
+/**
+  \brief   Get Priority Grouping
+  \details Reads the priority grouping field from the NVIC Interrupt Controller.
+  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
+{
+  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+  \brief   Enable Interrupt
+  \details Enables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt
+  \details Disables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+    __DSB();
+    __ISB();
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Active Interrupt
+  \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not active.
+  \return             1  Interrupt status is active.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   Get Interrupt Target State
+  \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  if interrupt is assigned to Secure
+  \return             1  if interrupt is assigned to Non Secure
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Target State
+  \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  if interrupt is assigned to Secure
+                      1  if interrupt is assigned to Non Secure
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |=  ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
+    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Clear Interrupt Target State
+  \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  if interrupt is assigned to Secure
+                      1  if interrupt is assigned to Non Secure
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
+    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->IPR[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+  else
+  {
+    SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+
+
+/**
+  \brief   Encode Priority
+  \details Encodes the priority for an interrupt with the given priority group,
+           preemptive priority value, and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]     PriorityGroup  Used priority group.
+  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+  \param [in]       SubPriority  Subpriority value (starting from 0).
+  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  return (
+           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
+         );
+}
+
+
+/**
+  \brief   Decode Priority
+  \details Decodes an interrupt priority value with a given priority group to
+           preemptive priority value and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+  \param [in]     PriorityGroup  Used priority group.
+  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+  \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
+}
+
+
+/**
+  \brief   Set Interrupt Vector
+  \details Sets an interrupt vector in SRAM based interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+           VTOR must been relocated to SRAM before.
+  \param [in]   IRQn      Interrupt number
+  \param [in]   vector    Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+  \brief   Get Interrupt Vector
+  \details Reads an interrupt vector from interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn      Interrupt number.
+  \return                 Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+  __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
+                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */
+  __DSB();                                                          /* Ensure completion of memory access */
+
+  for(;;)                                                           /* wait until reset */
+  {
+    __NOP();
+  }
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   Set Priority Grouping (non-secure)
+  \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence.
+           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+           Only values from 0..7 are used.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]      PriorityGroup  Priority grouping field.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup)
+{
+  uint32_t reg_value;
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
+
+  reg_value  =  SCB_NS->AIRCR;                                                   /* read old register configuration    */
+  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk));             /* clear bits to change               */
+  reg_value  =  (reg_value                                   |
+                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                (PriorityGroupTmp << 8U)                      );              /* Insert write key and priorty group */
+  SCB_NS->AIRCR =  reg_value;
+}
+
+
+/**
+  \brief   Get Priority Grouping (non-secure)
+  \details Reads the priority grouping field from the non-secure NVIC when in secure state.
+  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void)
+{
+  return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+  \brief   Enable Interrupt (non-secure)
+  \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status (non-secure)
+  \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt (non-secure)
+  \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt (non-secure)
+  \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt (non-secure)
+  \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt (non-secure)
+  \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Active Interrupt (non-secure)
+  \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not active.
+  \return             1  Interrupt status is active.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Priority (non-secure)
+  \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every non-secure processor exception.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->IPR[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+  else
+  {
+    SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority (non-secure)
+  \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+#endif /*  defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+/* ##########################  MPU functions  #################################### */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+
+#include "mpu_armv8.h"
+
+#endif
+
+/* ##########################  FPU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions
+  \brief    Function that provides FPU type.
+  @{
+ */
+
+/**
+  \brief   get FPU type
+  \details returns the FPU type
+  \returns
+   - \b  0: No FPU
+   - \b  1: Single precision FPU
+   - \b  2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+  uint32_t mvfr0;
+
+  mvfr0 = FPU->MVFR0;
+  if      ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U)
+  {
+    return 2U;           /* Double + Single precision FPU */
+  }
+  else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)
+  {
+    return 1U;           /* Single precision FPU */
+  }
+  else
+  {
+    return 0U;           /* No FPU */
+  }
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ##########################   SAU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SAUFunctions SAU Functions
+  \brief    Functions that configure the SAU.
+  @{
+ */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+
+/**
+  \brief   Enable SAU
+  \details Enables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Enable(void)
+{
+    SAU->CTRL |=  (SAU_CTRL_ENABLE_Msk);
+}
+
+
+
+/**
+  \brief   Disable SAU
+  \details Disables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Disable(void)
+{
+    SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
+}
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_SAUFunctions */
+
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                   /* Reload value impossible */
+  }
+
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                     /* Function successful */
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   System Tick Configuration (non-secure)
+  \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                         /* Reload value impossible */
+  }
+
+  SysTick_NS->LOAD  = (uint32_t)(ticks - 1UL);                            /* set reload register */
+  TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick_NS->VAL   = 0UL;                                                /* Load the SysTick Counter Value */
+  SysTick_NS->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                      SysTick_CTRL_TICKINT_Msk   |
+                      SysTick_CTRL_ENABLE_Msk;                            /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                           /* Function successful */
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_core_DebugFunctions ITM Functions
+  \brief    Functions that access the ITM debug interface.
+  @{
+ */
+
+extern volatile int32_t ITM_RxBuffer;                              /*!< External variable to receive characters. */
+#define                 ITM_RXBUFFER_EMPTY  ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/**
+  \brief   ITM Send Character
+  \details Transmits a character via the ITM channel 0, and
+           \li Just returns when no debugger is connected that has booked the output.
+           \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+  \param [in]     ch  Character to transmit.
+  \returns            Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */
+      ((ITM->TER & 1UL               ) != 0UL)   )     /* ITM Port #0 enabled */
+  {
+    while (ITM->PORT[0U].u32 == 0UL)
+    {
+      __NOP();
+    }
+    ITM->PORT[0U].u8 = (uint8_t)ch;
+  }
+  return (ch);
+}
+
+
+/**
+  \brief   ITM Receive Character
+  \details Inputs a character via the external variable \ref ITM_RxBuffer.
+  \return             Received character.
+  \return         -1  No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)
+{
+  int32_t ch = -1;                           /* no character available */
+
+  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
+  {
+    ch = ITM_RxBuffer;
+    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
+  }
+
+  return (ch);
+}
+
+
+/**
+  \brief   ITM Check Character
+  \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+  \return          0  No character available.
+  \return          1  Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void)
+{
+
+  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
+  {
+    return (0);                              /* no character available */
+  }
+  else
+  {
+    return (1);                              /*    character available */
+  }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_ARMV8MML_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/Drivers/CMSIS/Include/core_cm0.h b/Drivers/CMSIS/Include/core_cm0.h
new file mode 100644
index 0000000..6f82227
--- /dev/null
+++ b/Drivers/CMSIS/Include/core_cm0.h
@@ -0,0 +1,949 @@
+/**************************************************************************//**
+ * @file     core_cm0.h
+ * @brief    CMSIS Cortex-M0 Core Peripheral Access Layer Header File
+ * @version  V5.0.5
+ * @date     28. May 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM0_H_GENERIC
+#define __CORE_CM0_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup Cortex_M0
+  @{
+ */
+
+#include "cmsis_version.h"
+ 
+/*  CMSIS CM0 definitions */
+#define __CM0_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)              /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __CM0_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)               /*!< \deprecated [15:0]  CMSIS HAL sub version */
+#define __CM0_CMSIS_VERSION       ((__CM0_CMSIS_VERSION_MAIN << 16U) | \
+                                    __CM0_CMSIS_VERSION_SUB           )  /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M                (0U)                                   /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    This core does not support an FPU at all
+*/
+#define __FPU_USED       0U
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #if defined __ARM_PCS_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TI_ARM__ )
+  #if defined __TI_VFP_SUPPORT__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __CSMC__ )
+  #if ( __CSMC__ & 0x400U)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#endif
+
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM0_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM0_H_DEPENDANT
+#define __CORE_CM0_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM0_REV
+    #define __CM0_REV               0x0000U
+    #warning "__CM0_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          2U
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0U
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M0 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:28;              /*!< bit:  0..27  Reserved */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */
+    uint32_t _reserved1:3;               /*!< bit: 25..27  Reserved */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:1;               /*!< bit:      0  Reserved */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */
+    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IOM uint32_t ISER[1U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+        uint32_t RESERVED0[31U];
+  __IOM uint32_t ICER[1U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+        uint32_t RSERVED1[31U];
+  __IOM uint32_t ISPR[1U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+        uint32_t RESERVED2[31U];
+  __IOM uint32_t ICPR[1U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+        uint32_t RESERVED3[31U];
+        uint32_t RESERVED4[64U];
+  __IOM uint32_t IP[8U];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register */
+}  NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+        uint32_t RESERVED0;
+  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+        uint32_t RESERVED1;
+  __IOM uint32_t SHP[2U];                /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED */
+  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
+            Therefore they are not covered by the Cortex-M0 header file.
+  @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
+
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */
+
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+  #endif
+  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
+  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
+  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
+  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
+  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
+  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+/*#define NVIC_GetActive              __NVIC_GetActive             not available for Cortex-M0 */
+  #define NVIC_SetPriority            __NVIC_SetPriority
+  #define NVIC_GetPriority            __NVIC_GetPriority
+  #define NVIC_SystemReset            __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+  #endif
+  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetVector              __NVIC_SetVector
+  #define NVIC_GetVector              __NVIC_GetVector
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET          16
+
+
+/* The following EXC_RETURN values are saved the LR on exception entry */
+#define EXC_RETURN_HANDLER         (0xFFFFFFF1UL)     /* return to Handler mode, uses MSP after return                               */
+#define EXC_RETURN_THREAD_MSP      (0xFFFFFFF9UL)     /* return to Thread mode, uses MSP after return                                */
+#define EXC_RETURN_THREAD_PSP      (0xFFFFFFFDUL)     /* return to Thread mode, uses PSP after return                                */
+
+
+/* Interrupt Priorities are WORD accessible only under Armv6-M                  */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)
+#define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )
+#define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )
+
+#define __NVIC_SetPriorityGrouping(X) (void)(X)
+#define __NVIC_GetPriorityGrouping()  (0U)
+
+/**
+  \brief   Enable Interrupt
+  \details Enables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt
+  \details Disables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+    __DSB();
+    __ISB();
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->IP[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+  else
+  {
+    SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+
+
+/**
+  \brief   Encode Priority
+  \details Encodes the priority for an interrupt with the given priority group,
+           preemptive priority value, and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]     PriorityGroup  Used priority group.
+  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+  \param [in]       SubPriority  Subpriority value (starting from 0).
+  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  return (
+           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
+         );
+}
+
+
+/**
+  \brief   Decode Priority
+  \details Decodes an interrupt priority value with a given priority group to
+           preemptive priority value and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+  \param [in]     PriorityGroup  Used priority group.
+  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+  \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
+}
+
+
+
+/**
+  \brief   Set Interrupt Vector
+  \details Sets an interrupt vector in SRAM based interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+           Address 0 must be mapped to SRAM.
+  \param [in]   IRQn      Interrupt number
+  \param [in]   vector    Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+  uint32_t *vectors = (uint32_t *)0x0U;
+  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+  \brief   Get Interrupt Vector
+  \details Reads an interrupt vector from interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn      Interrupt number.
+  \return                 Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+  uint32_t *vectors = (uint32_t *)0x0U;
+  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+  __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+  SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                 SCB_AIRCR_SYSRESETREQ_Msk);
+  __DSB();                                                          /* Ensure completion of memory access */
+
+  for(;;)                                                           /* wait until reset */
+  {
+    __NOP();
+  }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+/* ##########################  FPU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions
+  \brief    Function that provides FPU type.
+  @{
+ */
+
+/**
+  \brief   get FPU type
+  \details returns the FPU type
+  \returns
+   - \b  0: No FPU
+   - \b  1: Single precision FPU
+   - \b  2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+    return 0U;           /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                   /* Reload value impossible */
+  }
+
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                     /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM0_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/Drivers/CMSIS/Include/core_cm0plus.h b/Drivers/CMSIS/Include/core_cm0plus.h
new file mode 100644
index 0000000..b9377e8
--- /dev/null
+++ b/Drivers/CMSIS/Include/core_cm0plus.h
@@ -0,0 +1,1083 @@
+/**************************************************************************//**
+ * @file     core_cm0plus.h
+ * @brief    CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
+ * @version  V5.0.6
+ * @date     28. May 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM0PLUS_H_GENERIC
+#define __CORE_CM0PLUS_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup Cortex-M0+
+  @{
+ */
+
+#include "cmsis_version.h"
+ 
+/*  CMSIS CM0+ definitions */
+#define __CM0PLUS_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN)                  /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __CM0PLUS_CMSIS_VERSION_SUB  (__CM_CMSIS_VERSION_SUB)                   /*!< \deprecated [15:0]  CMSIS HAL sub version */
+#define __CM0PLUS_CMSIS_VERSION      ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \
+                                       __CM0PLUS_CMSIS_VERSION_SUB           )  /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M                   (0U)                                       /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    This core does not support an FPU at all
+*/
+#define __FPU_USED       0U
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #if defined __ARM_PCS_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TI_ARM__ )
+  #if defined __TI_VFP_SUPPORT__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __CSMC__ )
+  #if ( __CSMC__ & 0x400U)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#endif
+
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM0PLUS_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM0PLUS_H_DEPENDANT
+#define __CORE_CM0PLUS_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM0PLUS_REV
+    #define __CM0PLUS_REV             0x0000U
+    #warning "__CM0PLUS_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0U
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __VTOR_PRESENT
+    #define __VTOR_PRESENT            0U
+    #warning "__VTOR_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          2U
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0U
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex-M0+ */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core MPU Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:28;              /*!< bit:  0..27  Reserved */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */
+    uint32_t _reserved1:3;               /*!< bit: 25..27  Reserved */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */
+    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IOM uint32_t ISER[1U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+        uint32_t RESERVED0[31U];
+  __IOM uint32_t ICER[1U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+        uint32_t RSERVED1[31U];
+  __IOM uint32_t ISPR[1U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+        uint32_t RESERVED2[31U];
+  __IOM uint32_t ICPR[1U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+        uint32_t RESERVED3[31U];
+        uint32_t RESERVED4[64U];
+  __IOM uint32_t IP[8U];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register */
+}  NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
+#else
+        uint32_t RESERVED0;
+#endif
+  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+        uint32_t RESERVED1;
+  __IOM uint32_t SHP[2U];                /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED */
+  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos                 8U                                            /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos)            /*!< SCB VTOR: TBLOFF Mask */
+#endif
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+  \brief    Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
+  __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */
+} MPU_Type;
+
+#define MPU_TYPE_RALIASES                  1U
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos                   8U                                            /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0xFFFFFFUL << MPU_RBAR_ADDR_Pos)              /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos                    28U                                            /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos                    24U                                            /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos                     18U                                            /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos                     17U                                            /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos                     16U                                            /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
+            Therefore they are not covered by the Cortex-M0+ header file.
+  @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
+
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit */
+  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+  #endif
+  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
+  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
+  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
+  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
+  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
+  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+/*#define NVIC_GetActive              __NVIC_GetActive             not available for Cortex-M0+ */
+  #define NVIC_SetPriority            __NVIC_SetPriority
+  #define NVIC_GetPriority            __NVIC_GetPriority
+  #define NVIC_SystemReset            __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+  #endif
+  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetVector              __NVIC_SetVector
+  #define NVIC_GetVector              __NVIC_GetVector
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET          16
+
+
+/* The following EXC_RETURN values are saved the LR on exception entry */
+#define EXC_RETURN_HANDLER         (0xFFFFFFF1UL)     /* return to Handler mode, uses MSP after return                               */
+#define EXC_RETURN_THREAD_MSP      (0xFFFFFFF9UL)     /* return to Thread mode, uses MSP after return                                */
+#define EXC_RETURN_THREAD_PSP      (0xFFFFFFFDUL)     /* return to Thread mode, uses PSP after return                                */
+
+
+/* Interrupt Priorities are WORD accessible only under Armv6-M                  */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)
+#define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )
+#define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )
+
+#define __NVIC_SetPriorityGrouping(X) (void)(X)
+#define __NVIC_GetPriorityGrouping()  (0U)
+
+/**
+  \brief   Enable Interrupt
+  \details Enables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt
+  \details Disables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+    __DSB();
+    __ISB();
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->IP[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+  else
+  {
+    SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+
+
+/**
+  \brief   Encode Priority
+  \details Encodes the priority for an interrupt with the given priority group,
+           preemptive priority value, and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]     PriorityGroup  Used priority group.
+  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+  \param [in]       SubPriority  Subpriority value (starting from 0).
+  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  return (
+           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
+         );
+}
+
+
+/**
+  \brief   Decode Priority
+  \details Decodes an interrupt priority value with a given priority group to
+           preemptive priority value and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+  \param [in]     PriorityGroup  Used priority group.
+  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+  \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
+}
+
+
+/**
+  \brief   Set Interrupt Vector
+  \details Sets an interrupt vector in SRAM based interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+           VTOR must been relocated to SRAM before.
+           If VTOR is not present address 0 must be mapped to SRAM.
+  \param [in]   IRQn      Interrupt number
+  \param [in]   vector    Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+#else
+    uint32_t *vectors = (uint32_t *)0x0U;
+#endif
+  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+  \brief   Get Interrupt Vector
+  \details Reads an interrupt vector from interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn      Interrupt number.
+  \return                 Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+#else
+  uint32_t *vectors = (uint32_t *)0x0U;
+#endif
+  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+  __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+  SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                 SCB_AIRCR_SYSRESETREQ_Msk);
+  __DSB();                                                          /* Ensure completion of memory access */
+
+  for(;;)                                                           /* wait until reset */
+  {
+    __NOP();
+  }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+/* ##########################  MPU functions  #################################### */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+
+#include "mpu_armv7.h"
+
+#endif
+
+/* ##########################  FPU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions
+  \brief    Function that provides FPU type.
+  @{
+ */
+
+/**
+  \brief   get FPU type
+  \details returns the FPU type
+  \returns
+   - \b  0: No FPU
+   - \b  1: Single precision FPU
+   - \b  2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+    return 0U;           /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                   /* Reload value impossible */
+  }
+
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                     /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM0PLUS_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/Drivers/CMSIS/Include/core_cm1.h b/Drivers/CMSIS/Include/core_cm1.h
new file mode 100644
index 0000000..fd1c407
--- /dev/null
+++ b/Drivers/CMSIS/Include/core_cm1.h
@@ -0,0 +1,976 @@
+/**************************************************************************//**
+ * @file     core_cm1.h
+ * @brief    CMSIS Cortex-M1 Core Peripheral Access Layer Header File
+ * @version  V1.0.0
+ * @date     23. July 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM1_H_GENERIC
+#define __CORE_CM1_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup Cortex_M1
+  @{
+ */
+
+#include "cmsis_version.h"
+ 
+/*  CMSIS CM1 definitions */
+#define __CM1_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)              /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __CM1_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)               /*!< \deprecated [15:0]  CMSIS HAL sub version */
+#define __CM1_CMSIS_VERSION       ((__CM1_CMSIS_VERSION_MAIN << 16U) | \
+                                    __CM1_CMSIS_VERSION_SUB           )  /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M                (1U)                                   /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    This core does not support an FPU at all
+*/
+#define __FPU_USED       0U
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #if defined __ARM_PCS_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TI_ARM__ )
+  #if defined __TI_VFP_SUPPORT__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __CSMC__ )
+  #if ( __CSMC__ & 0x400U)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#endif
+
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM1_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM1_H_DEPENDANT
+#define __CORE_CM1_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM1_REV
+    #define __CM1_REV               0x0100U
+    #warning "__CM1_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          2U
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0U
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M1 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:28;              /*!< bit:  0..27  Reserved */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */
+    uint32_t _reserved1:3;               /*!< bit: 25..27  Reserved */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:1;               /*!< bit:      0  Reserved */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */
+    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IOM uint32_t ISER[1U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+        uint32_t RESERVED0[31U];
+  __IOM uint32_t ICER[1U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+        uint32_t RSERVED1[31U];
+  __IOM uint32_t ISPR[1U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+        uint32_t RESERVED2[31U];
+  __IOM uint32_t ICPR[1U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+        uint32_t RESERVED3[31U];
+        uint32_t RESERVED4[64U];
+  __IOM uint32_t IP[8U];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register */
+}  NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+        uint32_t RESERVED0;
+  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+        uint32_t RESERVED1;
+  __IOM uint32_t SHP[2U];                /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED */
+  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+  \brief    Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+        uint32_t RESERVED0[2U];
+  __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */
+} SCnSCB_Type;
+
+/* Auxiliary Control Register Definitions */
+#define SCnSCB_ACTLR_ITCMUAEN_Pos            4U                                        /*!< ACTLR: Instruction TCM Upper Alias Enable Position */
+#define SCnSCB_ACTLR_ITCMUAEN_Msk           (1UL << SCnSCB_ACTLR_ITCMUAEN_Pos)         /*!< ACTLR: Instruction TCM Upper Alias Enable Mask */
+
+#define SCnSCB_ACTLR_ITCMLAEN_Pos            3U                                        /*!< ACTLR: Instruction TCM Lower Alias Enable Position */
+#define SCnSCB_ACTLR_ITCMLAEN_Msk           (1UL << SCnSCB_ACTLR_ITCMLAEN_Pos)         /*!< ACTLR: Instruction TCM Lower Alias Enable Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    Cortex-M1 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
+            Therefore they are not covered by the Cortex-M1 header file.
+  @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
+
+#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */
+
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+  #endif
+  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
+  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
+  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
+  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
+  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
+  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+/*#define NVIC_GetActive              __NVIC_GetActive             not available for Cortex-M1 */
+  #define NVIC_SetPriority            __NVIC_SetPriority
+  #define NVIC_GetPriority            __NVIC_GetPriority
+  #define NVIC_SystemReset            __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+  #endif
+  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetVector              __NVIC_SetVector
+  #define NVIC_GetVector              __NVIC_GetVector
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET          16
+
+
+/* The following EXC_RETURN values are saved the LR on exception entry */
+#define EXC_RETURN_HANDLER         (0xFFFFFFF1UL)     /* return to Handler mode, uses MSP after return                               */
+#define EXC_RETURN_THREAD_MSP      (0xFFFFFFF9UL)     /* return to Thread mode, uses MSP after return                                */
+#define EXC_RETURN_THREAD_PSP      (0xFFFFFFFDUL)     /* return to Thread mode, uses PSP after return                                */
+
+
+/* Interrupt Priorities are WORD accessible only under Armv6-M                  */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)
+#define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )
+#define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )
+
+#define __NVIC_SetPriorityGrouping(X) (void)(X)
+#define __NVIC_GetPriorityGrouping()  (0U)
+
+/**
+  \brief   Enable Interrupt
+  \details Enables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt
+  \details Disables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+    __DSB();
+    __ISB();
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->IP[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+  else
+  {
+    SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+
+
+/**
+  \brief   Encode Priority
+  \details Encodes the priority for an interrupt with the given priority group,
+           preemptive priority value, and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]     PriorityGroup  Used priority group.
+  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+  \param [in]       SubPriority  Subpriority value (starting from 0).
+  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  return (
+           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
+         );
+}
+
+
+/**
+  \brief   Decode Priority
+  \details Decodes an interrupt priority value with a given priority group to
+           preemptive priority value and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+  \param [in]     PriorityGroup  Used priority group.
+  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+  \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
+}
+
+
+
+/**
+  \brief   Set Interrupt Vector
+  \details Sets an interrupt vector in SRAM based interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+           Address 0 must be mapped to SRAM.
+  \param [in]   IRQn      Interrupt number
+  \param [in]   vector    Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+  uint32_t *vectors = (uint32_t *)0x0U;
+  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+  \brief   Get Interrupt Vector
+  \details Reads an interrupt vector from interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn      Interrupt number.
+  \return                 Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+  uint32_t *vectors = (uint32_t *)0x0U;
+  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+  __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+  SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                 SCB_AIRCR_SYSRESETREQ_Msk);
+  __DSB();                                                          /* Ensure completion of memory access */
+
+  for(;;)                                                           /* wait until reset */
+  {
+    __NOP();
+  }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+/* ##########################  FPU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions
+  \brief    Function that provides FPU type.
+  @{
+ */
+
+/**
+  \brief   get FPU type
+  \details returns the FPU type
+  \returns
+   - \b  0: No FPU
+   - \b  1: Single precision FPU
+   - \b  2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+    return 0U;           /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                   /* Reload value impossible */
+  }
+
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                     /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM1_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/Drivers/CMSIS/Include/core_cm23.h b/Drivers/CMSIS/Include/core_cm23.h
new file mode 100644
index 0000000..8202a8d
--- /dev/null
+++ b/Drivers/CMSIS/Include/core_cm23.h
@@ -0,0 +1,1993 @@
+/**************************************************************************//**
+ * @file     core_cm23.h
+ * @brief    CMSIS Cortex-M23 Core Peripheral Access Layer Header File
+ * @version  V5.0.7
+ * @date     22. June 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM23_H_GENERIC
+#define __CORE_CM23_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup Cortex_M23
+  @{
+ */
+
+#include "cmsis_version.h"
+
+/*  CMSIS definitions */
+#define __CM23_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)                   /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __CM23_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)                    /*!< \deprecated [15:0]  CMSIS HAL sub version */
+#define __CM23_CMSIS_VERSION       ((__CM23_CMSIS_VERSION_MAIN << 16U) | \
+                                     __CM23_CMSIS_VERSION_SUB           )      /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M                 (23U)                                       /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    This core does not support an FPU at all
+*/
+#define __FPU_USED       0U
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #if defined __ARM_PCS_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TI_ARM__ )
+  #if defined __TI_VFP_SUPPORT__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __CSMC__ )
+  #if ( __CSMC__ & 0x400U)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#endif
+
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM23_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM23_H_DEPENDANT
+#define __CORE_CM23_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM23_REV
+    #define __CM23_REV                0x0000U
+    #warning "__CM23_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __FPU_PRESENT
+    #define __FPU_PRESENT             0U
+    #warning "__FPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0U
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __SAUREGION_PRESENT
+    #define __SAUREGION_PRESENT       0U
+    #warning "__SAUREGION_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __VTOR_PRESENT
+    #define __VTOR_PRESENT            0U
+    #warning "__VTOR_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          2U
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0U
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+
+  #ifndef __ETM_PRESENT
+    #define __ETM_PRESENT             0U
+    #warning "__ETM_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MTB_PRESENT
+    #define __MTB_PRESENT             0U
+    #warning "__MTB_PRESENT not defined in device header file; using default!"
+  #endif
+
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M23 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core Debug Register
+  - Core MPU Register
+  - Core SAU Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:28;              /*!< bit:  0..27  Reserved */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */
+    uint32_t _reserved1:3;               /*!< bit: 25..27  Reserved */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack-pointer select */
+    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IOM uint32_t ISER[16U];              /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+        uint32_t RESERVED0[16U];
+  __IOM uint32_t ICER[16U];              /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+        uint32_t RSERVED1[16U];
+  __IOM uint32_t ISPR[16U];              /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+        uint32_t RESERVED2[16U];
+  __IOM uint32_t ICPR[16U];              /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+        uint32_t RESERVED3[16U];
+  __IOM uint32_t IABR[16U];              /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */
+        uint32_t RESERVED4[16U];
+  __IOM uint32_t ITNS[16U];              /*!< Offset: 0x280 (R/W)  Interrupt Non-Secure State Register */
+        uint32_t RESERVED5[16U];
+  __IOM uint32_t IPR[124U];              /*!< Offset: 0x300 (R/W)  Interrupt Priority Register */
+}  NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
+#else
+        uint32_t RESERVED0;
+#endif
+  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+        uint32_t RESERVED1;
+  __IOM uint32_t SHPR[2U];               /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED */
+  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_PENDNMISET_Pos            31U                                            /*!< SCB ICSR: PENDNMISET Position */
+#define SCB_ICSR_PENDNMISET_Msk            (1UL << SCB_ICSR_PENDNMISET_Pos)               /*!< SCB ICSR: PENDNMISET Mask */
+
+#define SCB_ICSR_NMIPENDSET_Pos            SCB_ICSR_PENDNMISET_Pos                        /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */
+#define SCB_ICSR_NMIPENDSET_Msk            SCB_ICSR_PENDNMISET_Msk                        /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */
+
+#define SCB_ICSR_PENDNMICLR_Pos            30U                                            /*!< SCB ICSR: PENDNMICLR Position */
+#define SCB_ICSR_PENDNMICLR_Msk            (1UL << SCB_ICSR_PENDNMICLR_Pos)               /*!< SCB ICSR: PENDNMICLR Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_STTNS_Pos                 24U                                            /*!< SCB ICSR: STTNS Position (Security Extension) */
+#define SCB_ICSR_STTNS_Msk                 (1UL << SCB_ICSR_STTNS_Pos)                    /*!< SCB ICSR: STTNS Mask (Security Extension) */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
+#endif
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIS_Pos                 14U                                            /*!< SCB AIRCR: PRIS Position */
+#define SCB_AIRCR_PRIS_Msk                 (1UL << SCB_AIRCR_PRIS_Pos)                    /*!< SCB AIRCR: PRIS Mask */
+
+#define SCB_AIRCR_BFHFNMINS_Pos            13U                                            /*!< SCB AIRCR: BFHFNMINS Position */
+#define SCB_AIRCR_BFHFNMINS_Msk            (1UL << SCB_AIRCR_BFHFNMINS_Pos)               /*!< SCB AIRCR: BFHFNMINS Mask */
+
+#define SCB_AIRCR_SYSRESETREQS_Pos          3U                                            /*!< SCB AIRCR: SYSRESETREQS Position */
+#define SCB_AIRCR_SYSRESETREQS_Msk         (1UL << SCB_AIRCR_SYSRESETREQS_Pos)            /*!< SCB AIRCR: SYSRESETREQS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEPS_Pos              3U                                            /*!< SCB SCR: SLEEPDEEPS Position */
+#define SCB_SCR_SLEEPDEEPS_Msk             (1UL << SCB_SCR_SLEEPDEEPS_Pos)                /*!< SCB SCR: SLEEPDEEPS Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_BP_Pos                     18U                                            /*!< SCB CCR: BP Position */
+#define SCB_CCR_BP_Msk                     (1UL << SCB_CCR_BP_Pos)                        /*!< SCB CCR: BP Mask */
+
+#define SCB_CCR_IC_Pos                     17U                                            /*!< SCB CCR: IC Position */
+#define SCB_CCR_IC_Msk                     (1UL << SCB_CCR_IC_Pos)                        /*!< SCB CCR: IC Mask */
+
+#define SCB_CCR_DC_Pos                     16U                                            /*!< SCB CCR: DC Position */
+#define SCB_CCR_DC_Msk                     (1UL << SCB_CCR_DC_Pos)                        /*!< SCB CCR: DC Mask */
+
+#define SCB_CCR_STKOFHFNMIGN_Pos           10U                                            /*!< SCB CCR: STKOFHFNMIGN Position */
+#define SCB_CCR_STKOFHFNMIGN_Msk           (1UL << SCB_CCR_STKOFHFNMIGN_Pos)              /*!< SCB CCR: STKOFHFNMIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_HARDFAULTPENDED_Pos      21U                                            /*!< SCB SHCSR: HARDFAULTPENDED Position */
+#define SCB_SHCSR_HARDFAULTPENDED_Msk      (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)         /*!< SCB SHCSR: HARDFAULTPENDED Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_NMIACT_Pos                5U                                            /*!< SCB SHCSR: NMIACT Position */
+#define SCB_SHCSR_NMIACT_Msk               (1UL << SCB_SHCSR_NMIACT_Pos)                  /*!< SCB SHCSR: NMIACT Mask */
+
+#define SCB_SHCSR_HARDFAULTACT_Pos          2U                                            /*!< SCB SHCSR: HARDFAULTACT Position */
+#define SCB_SHCSR_HARDFAULTACT_Msk         (1UL << SCB_SHCSR_HARDFAULTACT_Pos)            /*!< SCB SHCSR: HARDFAULTACT Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
+  \brief    Type definitions for the Data Watchpoint and Trace (DWT)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */
+        uint32_t RESERVED0[6U];
+  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */
+  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */
+        uint32_t RESERVED1[1U];
+  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */
+        uint32_t RESERVED2[1U];
+  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */
+        uint32_t RESERVED3[1U];
+  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */
+        uint32_t RESERVED4[1U];
+  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */
+        uint32_t RESERVED5[1U];
+  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */
+        uint32_t RESERVED6[1U];
+  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */
+        uint32_t RESERVED7[1U];
+  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */
+        uint32_t RESERVED8[1U];
+  __IOM uint32_t COMP4;                  /*!< Offset: 0x060 (R/W)  Comparator Register 4 */
+        uint32_t RESERVED9[1U];
+  __IOM uint32_t FUNCTION4;              /*!< Offset: 0x068 (R/W)  Function Register 4 */
+        uint32_t RESERVED10[1U];
+  __IOM uint32_t COMP5;                  /*!< Offset: 0x070 (R/W)  Comparator Register 5 */
+        uint32_t RESERVED11[1U];
+  __IOM uint32_t FUNCTION5;              /*!< Offset: 0x078 (R/W)  Function Register 5 */
+        uint32_t RESERVED12[1U];
+  __IOM uint32_t COMP6;                  /*!< Offset: 0x080 (R/W)  Comparator Register 6 */
+        uint32_t RESERVED13[1U];
+  __IOM uint32_t FUNCTION6;              /*!< Offset: 0x088 (R/W)  Function Register 6 */
+        uint32_t RESERVED14[1U];
+  __IOM uint32_t COMP7;                  /*!< Offset: 0x090 (R/W)  Comparator Register 7 */
+        uint32_t RESERVED15[1U];
+  __IOM uint32_t FUNCTION7;              /*!< Offset: 0x098 (R/W)  Function Register 7 */
+        uint32_t RESERVED16[1U];
+  __IOM uint32_t COMP8;                  /*!< Offset: 0x0A0 (R/W)  Comparator Register 8 */
+        uint32_t RESERVED17[1U];
+  __IOM uint32_t FUNCTION8;              /*!< Offset: 0x0A8 (R/W)  Function Register 8 */
+        uint32_t RESERVED18[1U];
+  __IOM uint32_t COMP9;                  /*!< Offset: 0x0B0 (R/W)  Comparator Register 9 */
+        uint32_t RESERVED19[1U];
+  __IOM uint32_t FUNCTION9;              /*!< Offset: 0x0B8 (R/W)  Function Register 9 */
+        uint32_t RESERVED20[1U];
+  __IOM uint32_t COMP10;                 /*!< Offset: 0x0C0 (R/W)  Comparator Register 10 */
+        uint32_t RESERVED21[1U];
+  __IOM uint32_t FUNCTION10;             /*!< Offset: 0x0C8 (R/W)  Function Register 10 */
+        uint32_t RESERVED22[1U];
+  __IOM uint32_t COMP11;                 /*!< Offset: 0x0D0 (R/W)  Comparator Register 11 */
+        uint32_t RESERVED23[1U];
+  __IOM uint32_t FUNCTION11;             /*!< Offset: 0x0D8 (R/W)  Function Register 11 */
+        uint32_t RESERVED24[1U];
+  __IOM uint32_t COMP12;                 /*!< Offset: 0x0E0 (R/W)  Comparator Register 12 */
+        uint32_t RESERVED25[1U];
+  __IOM uint32_t FUNCTION12;             /*!< Offset: 0x0E8 (R/W)  Function Register 12 */
+        uint32_t RESERVED26[1U];
+  __IOM uint32_t COMP13;                 /*!< Offset: 0x0F0 (R/W)  Comparator Register 13 */
+        uint32_t RESERVED27[1U];
+  __IOM uint32_t FUNCTION13;             /*!< Offset: 0x0F8 (R/W)  Function Register 13 */
+        uint32_t RESERVED28[1U];
+  __IOM uint32_t COMP14;                 /*!< Offset: 0x100 (R/W)  Comparator Register 14 */
+        uint32_t RESERVED29[1U];
+  __IOM uint32_t FUNCTION14;             /*!< Offset: 0x108 (R/W)  Function Register 14 */
+        uint32_t RESERVED30[1U];
+  __IOM uint32_t COMP15;                 /*!< Offset: 0x110 (R/W)  Comparator Register 15 */
+        uint32_t RESERVED31[1U];
+  __IOM uint32_t FUNCTION15;             /*!< Offset: 0x118 (R/W)  Function Register 15 */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_ID_Pos                27U                                         /*!< DWT FUNCTION: ID Position */
+#define DWT_FUNCTION_ID_Msk                (0x1FUL << DWT_FUNCTION_ID_Pos)             /*!< DWT FUNCTION: ID Mask */
+
+#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_ACTION_Pos             4U                                         /*!< DWT FUNCTION: ACTION Position */
+#define DWT_FUNCTION_ACTION_Msk            (0x3UL << DWT_FUNCTION_ACTION_Pos)          /*!< DWT FUNCTION: ACTION Mask */
+
+#define DWT_FUNCTION_MATCH_Pos              0U                                         /*!< DWT FUNCTION: MATCH Position */
+#define DWT_FUNCTION_MATCH_Msk             (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/)       /*!< DWT FUNCTION: MATCH Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_TPI     Trace Port Interface (TPI)
+  \brief    Type definitions for the Trace Port Interface (TPI)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+  __IM  uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */
+  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
+        uint32_t RESERVED0[2U];
+  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
+        uint32_t RESERVED1[55U];
+  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
+        uint32_t RESERVED2[131U];
+  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
+  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
+  __IOM uint32_t PSCR;                   /*!< Offset: 0x308 (R/W)  Periodic Synchronization Control Register */
+        uint32_t RESERVED3[759U];
+  __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER Register */
+  __IM  uint32_t ITFTTD0;                /*!< Offset: 0xEEC (R/ )  Integration Test FIFO Test Data 0 Register */
+  __IOM uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/W)  Integration Test ATB Control Register 2 */
+        uint32_t RESERVED4[1U];
+  __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  Integration Test ATB Control Register 0 */
+  __IM  uint32_t ITFTTD1;                /*!< Offset: 0xEFC (R/ )  Integration Test FIFO Test Data 1 Register */
+  __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
+        uint32_t RESERVED5[39U];
+  __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */
+  __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
+        uint32_t RESERVED7[8U];
+  __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  Device Configuration Register */
+  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  Device Type Identifier Register */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_FOnMan_Pos                 6U                                         /*!< TPI FFCR: FOnMan Position */
+#define TPI_FFCR_FOnMan_Msk                (0x1UL << TPI_FFCR_FOnMan_Pos)              /*!< TPI FFCR: FOnMan Mask */
+
+#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration Test FIFO Test Data 0 Register Definitions */
+#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos    29U                                         /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */
+#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk    (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos)  /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */
+
+#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos  27U                                         /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */
+#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk  (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos    26U                                         /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */
+#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk    (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos)  /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos  24U                                         /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */
+#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk  (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_data2_Pos      16U                                         /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */
+#define TPI_ITFTTD0_ATB_IF1_data2_Msk      (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos)   /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_data1_Pos       8U                                         /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */
+#define TPI_ITFTTD0_ATB_IF1_data1_Msk      (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos)   /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_data0_Pos       0U                                          /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */
+#define TPI_ITFTTD0_ATB_IF1_data0_Msk      (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */
+
+/* TPI Integration Test ATB Control Register 2 Register Definitions */
+#define TPI_ITATBCTR2_AFVALID2S_Pos         1U                                         /*!< TPI ITATBCTR2: AFVALID2S Position */
+#define TPI_ITATBCTR2_AFVALID2S_Msk        (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos)      /*!< TPI ITATBCTR2: AFVALID2SS Mask */
+
+#define TPI_ITATBCTR2_AFVALID1S_Pos         1U                                         /*!< TPI ITATBCTR2: AFVALID1S Position */
+#define TPI_ITATBCTR2_AFVALID1S_Msk        (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos)      /*!< TPI ITATBCTR2: AFVALID1SS Mask */
+
+#define TPI_ITATBCTR2_ATREADY2S_Pos         0U                                         /*!< TPI ITATBCTR2: ATREADY2S Position */
+#define TPI_ITATBCTR2_ATREADY2S_Msk        (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/)  /*!< TPI ITATBCTR2: ATREADY2S Mask */
+
+#define TPI_ITATBCTR2_ATREADY1S_Pos         0U                                         /*!< TPI ITATBCTR2: ATREADY1S Position */
+#define TPI_ITATBCTR2_ATREADY1S_Msk        (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/)  /*!< TPI ITATBCTR2: ATREADY1S Mask */
+
+/* TPI Integration Test FIFO Test Data 1 Register Definitions */
+#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos    29U                                         /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */
+#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk    (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos)  /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */
+
+#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos  27U                                         /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */
+#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk  (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */
+
+#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos    26U                                         /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */
+#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk    (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos)  /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */
+
+#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos  24U                                         /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */
+#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk  (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */
+
+#define TPI_ITFTTD1_ATB_IF2_data2_Pos      16U                                         /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */
+#define TPI_ITFTTD1_ATB_IF2_data2_Msk      (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos)   /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */
+
+#define TPI_ITFTTD1_ATB_IF2_data1_Pos       8U                                         /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */
+#define TPI_ITFTTD1_ATB_IF2_data1_Msk      (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos)   /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */
+
+#define TPI_ITFTTD1_ATB_IF2_data0_Pos       0U                                          /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */
+#define TPI_ITFTTD1_ATB_IF2_data0_Msk      (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */
+
+/* TPI Integration Test ATB Control Register 0 Definitions */
+#define TPI_ITATBCTR0_AFVALID2S_Pos         1U                                         /*!< TPI ITATBCTR0: AFVALID2S Position */
+#define TPI_ITATBCTR0_AFVALID2S_Msk        (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos)      /*!< TPI ITATBCTR0: AFVALID2SS Mask */
+
+#define TPI_ITATBCTR0_AFVALID1S_Pos         1U                                         /*!< TPI ITATBCTR0: AFVALID1S Position */
+#define TPI_ITATBCTR0_AFVALID1S_Msk        (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos)      /*!< TPI ITATBCTR0: AFVALID1SS Mask */
+
+#define TPI_ITATBCTR0_ATREADY2S_Pos         0U                                         /*!< TPI ITATBCTR0: ATREADY2S Position */
+#define TPI_ITATBCTR0_ATREADY2S_Msk        (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/)  /*!< TPI ITATBCTR0: ATREADY2S Mask */
+
+#define TPI_ITATBCTR0_ATREADY1S_Pos         0U                                         /*!< TPI ITATBCTR0: ATREADY1S Position */
+#define TPI_ITATBCTR0_ATREADY1S_Msk        (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/)  /*!< TPI ITATBCTR0: ATREADY1S Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk                (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_FIFOSZ_Pos                6U                                         /*!< TPI DEVID: FIFOSZ Position */
+#define TPI_DEVID_FIFOSZ_Msk               (0x7UL << TPI_DEVID_FIFOSZ_Pos)             /*!< TPI DEVID: FIFOSZ Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk         (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos             4U                                         /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos           0U                                         /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+  \brief    Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region Number Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
+  __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  MPU Region Limit Address Register */
+        uint32_t RESERVED0[7U];
+  union {
+  __IOM uint32_t MAIR[2];
+  struct {
+  __IOM uint32_t MAIR0;                  /*!< Offset: 0x030 (R/W)  MPU Memory Attribute Indirection Register 0 */
+  __IOM uint32_t MAIR1;                  /*!< Offset: 0x034 (R/W)  MPU Memory Attribute Indirection Register 1 */
+  };
+  };
+} MPU_Type;
+
+#define MPU_TYPE_RALIASES                  1U
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_BASE_Pos                   5U                                            /*!< MPU RBAR: BASE Position */
+#define MPU_RBAR_BASE_Msk                  (0x7FFFFFFUL << MPU_RBAR_BASE_Pos)             /*!< MPU RBAR: BASE Mask */
+
+#define MPU_RBAR_SH_Pos                     3U                                            /*!< MPU RBAR: SH Position */
+#define MPU_RBAR_SH_Msk                    (0x3UL << MPU_RBAR_SH_Pos)                     /*!< MPU RBAR: SH Mask */
+
+#define MPU_RBAR_AP_Pos                     1U                                            /*!< MPU RBAR: AP Position */
+#define MPU_RBAR_AP_Msk                    (0x3UL << MPU_RBAR_AP_Pos)                     /*!< MPU RBAR: AP Mask */
+
+#define MPU_RBAR_XN_Pos                     0U                                            /*!< MPU RBAR: XN Position */
+#define MPU_RBAR_XN_Msk                    (01UL /*<< MPU_RBAR_XN_Pos*/)                  /*!< MPU RBAR: XN Mask */
+
+/* MPU Region Limit Address Register Definitions */
+#define MPU_RLAR_LIMIT_Pos                  5U                                            /*!< MPU RLAR: LIMIT Position */
+#define MPU_RLAR_LIMIT_Msk                 (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos)            /*!< MPU RLAR: LIMIT Mask */
+
+#define MPU_RLAR_AttrIndx_Pos               1U                                            /*!< MPU RLAR: AttrIndx Position */
+#define MPU_RLAR_AttrIndx_Msk              (0x7UL << MPU_RLAR_AttrIndx_Pos)               /*!< MPU RLAR: AttrIndx Mask */
+
+#define MPU_RLAR_EN_Pos                     0U                                            /*!< MPU RLAR: EN Position */
+#define MPU_RLAR_EN_Msk                    (1UL /*<< MPU_RLAR_EN_Pos*/)                   /*!< MPU RLAR: EN Mask */
+
+/* MPU Memory Attribute Indirection Register 0 Definitions */
+#define MPU_MAIR0_Attr3_Pos                24U                                            /*!< MPU MAIR0: Attr3 Position */
+#define MPU_MAIR0_Attr3_Msk                (0xFFUL << MPU_MAIR0_Attr3_Pos)                /*!< MPU MAIR0: Attr3 Mask */
+
+#define MPU_MAIR0_Attr2_Pos                16U                                            /*!< MPU MAIR0: Attr2 Position */
+#define MPU_MAIR0_Attr2_Msk                (0xFFUL << MPU_MAIR0_Attr2_Pos)                /*!< MPU MAIR0: Attr2 Mask */
+
+#define MPU_MAIR0_Attr1_Pos                 8U                                            /*!< MPU MAIR0: Attr1 Position */
+#define MPU_MAIR0_Attr1_Msk                (0xFFUL << MPU_MAIR0_Attr1_Pos)                /*!< MPU MAIR0: Attr1 Mask */
+
+#define MPU_MAIR0_Attr0_Pos                 0U                                            /*!< MPU MAIR0: Attr0 Position */
+#define MPU_MAIR0_Attr0_Msk                (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/)            /*!< MPU MAIR0: Attr0 Mask */
+
+/* MPU Memory Attribute Indirection Register 1 Definitions */
+#define MPU_MAIR1_Attr7_Pos                24U                                            /*!< MPU MAIR1: Attr7 Position */
+#define MPU_MAIR1_Attr7_Msk                (0xFFUL << MPU_MAIR1_Attr7_Pos)                /*!< MPU MAIR1: Attr7 Mask */
+
+#define MPU_MAIR1_Attr6_Pos                16U                                            /*!< MPU MAIR1: Attr6 Position */
+#define MPU_MAIR1_Attr6_Msk                (0xFFUL << MPU_MAIR1_Attr6_Pos)                /*!< MPU MAIR1: Attr6 Mask */
+
+#define MPU_MAIR1_Attr5_Pos                 8U                                            /*!< MPU MAIR1: Attr5 Position */
+#define MPU_MAIR1_Attr5_Msk                (0xFFUL << MPU_MAIR1_Attr5_Pos)                /*!< MPU MAIR1: Attr5 Mask */
+
+#define MPU_MAIR1_Attr4_Pos                 0U                                            /*!< MPU MAIR1: Attr4 Position */
+#define MPU_MAIR1_Attr4_Msk                (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/)            /*!< MPU MAIR1: Attr4 Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SAU     Security Attribution Unit (SAU)
+  \brief    Type definitions for the Security Attribution Unit (SAU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Security Attribution Unit (SAU).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SAU Control Register */
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x004 (R/ )  SAU Type Register */
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  SAU Region Number Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  SAU Region Base Address Register */
+  __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  SAU Region Limit Address Register */
+#endif
+} SAU_Type;
+
+/* SAU Control Register Definitions */
+#define SAU_CTRL_ALLNS_Pos                  1U                                            /*!< SAU CTRL: ALLNS Position */
+#define SAU_CTRL_ALLNS_Msk                 (1UL << SAU_CTRL_ALLNS_Pos)                    /*!< SAU CTRL: ALLNS Mask */
+
+#define SAU_CTRL_ENABLE_Pos                 0U                                            /*!< SAU CTRL: ENABLE Position */
+#define SAU_CTRL_ENABLE_Msk                (1UL /*<< SAU_CTRL_ENABLE_Pos*/)               /*!< SAU CTRL: ENABLE Mask */
+
+/* SAU Type Register Definitions */
+#define SAU_TYPE_SREGION_Pos                0U                                            /*!< SAU TYPE: SREGION Position */
+#define SAU_TYPE_SREGION_Msk               (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/)           /*!< SAU TYPE: SREGION Mask */
+
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+/* SAU Region Number Register Definitions */
+#define SAU_RNR_REGION_Pos                  0U                                            /*!< SAU RNR: REGION Position */
+#define SAU_RNR_REGION_Msk                 (0xFFUL /*<< SAU_RNR_REGION_Pos*/)             /*!< SAU RNR: REGION Mask */
+
+/* SAU Region Base Address Register Definitions */
+#define SAU_RBAR_BADDR_Pos                  5U                                            /*!< SAU RBAR: BADDR Position */
+#define SAU_RBAR_BADDR_Msk                 (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos)            /*!< SAU RBAR: BADDR Mask */
+
+/* SAU Region Limit Address Register Definitions */
+#define SAU_RLAR_LADDR_Pos                  5U                                            /*!< SAU RLAR: LADDR Position */
+#define SAU_RLAR_LADDR_Msk                 (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos)            /*!< SAU RLAR: LADDR Mask */
+
+#define SAU_RLAR_NSC_Pos                    1U                                            /*!< SAU RLAR: NSC Position */
+#define SAU_RLAR_NSC_Msk                   (1UL << SAU_RLAR_NSC_Pos)                      /*!< SAU RLAR: NSC Mask */
+
+#define SAU_RLAR_ENABLE_Pos                 0U                                            /*!< SAU RLAR: ENABLE Position */
+#define SAU_RLAR_ENABLE_Msk                (1UL /*<< SAU_RLAR_ENABLE_Pos*/)               /*!< SAU RLAR: ENABLE Mask */
+
+#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
+
+/*@} end of group CMSIS_SAU */
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    Type definitions for the Core Debug Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */
+  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */
+  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */
+  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
+        uint32_t RESERVED4[1U];
+  __IOM uint32_t DAUTHCTRL;              /*!< Offset: 0x014 (R/W)  Debug Authentication Control Register */
+  __IOM uint32_t DSCSR;                  /*!< Offset: 0x018 (R/W)  Debug Security Control and Status Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESTART_ST_Pos   26U                                            /*!< CoreDebug DHCSR: S_RESTART_ST Position */
+#define CoreDebug_DHCSR_S_RESTART_ST_Msk   (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)      /*!< CoreDebug DHCSR: S_RESTART_ST Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register */
+#define CoreDebug_DEMCR_DWTENA_Pos         24U                                            /*!< CoreDebug DEMCR: DWTENA Position */
+#define CoreDebug_DEMCR_DWTENA_Msk         (1UL << CoreDebug_DEMCR_DWTENA_Pos)            /*!< CoreDebug DEMCR: DWTENA Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/* Debug Authentication Control Register Definitions */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos  3U                                            /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)    /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */
+
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos  2U                                            /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)    /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */
+
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos   1U                                            /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk  (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)     /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */
+
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos   0U                                            /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk  (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */
+
+/* Debug Security Control and Status Register Definitions */
+#define CoreDebug_DSCSR_CDS_Pos            16U                                            /*!< CoreDebug DSCSR: CDS Position */
+#define CoreDebug_DSCSR_CDS_Msk            (1UL << CoreDebug_DSCSR_CDS_Pos)               /*!< CoreDebug DSCSR: CDS Mask */
+
+#define CoreDebug_DSCSR_SBRSEL_Pos          1U                                            /*!< CoreDebug DSCSR: SBRSEL Position */
+#define CoreDebug_DSCSR_SBRSEL_Msk         (1UL << CoreDebug_DSCSR_SBRSEL_Pos)            /*!< CoreDebug DSCSR: SBRSEL Mask */
+
+#define CoreDebug_DSCSR_SBRSELEN_Pos        0U                                            /*!< CoreDebug DSCSR: SBRSELEN Position */
+#define CoreDebug_DSCSR_SBRSELEN_Msk       (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/)      /*!< CoreDebug DSCSR: SBRSELEN Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Core Hardware */
+  #define SCS_BASE            (0xE000E000UL)                             /*!< System Control Space Base Address */
+  #define DWT_BASE            (0xE0001000UL)                             /*!< DWT Base Address */
+  #define TPI_BASE            (0xE0040000UL)                             /*!< TPI Base Address */
+  #define CoreDebug_BASE      (0xE000EDF0UL)                             /*!< Core Debug Base Address */
+  #define SysTick_BASE        (SCS_BASE +  0x0010UL)                     /*!< SysTick Base Address */
+  #define NVIC_BASE           (SCS_BASE +  0x0100UL)                     /*!< NVIC Base Address */
+  #define SCB_BASE            (SCS_BASE +  0x0D00UL)                     /*!< System Control Block Base Address */
+
+
+  #define SCB                 ((SCB_Type       *)     SCB_BASE         ) /*!< SCB configuration struct */
+  #define SysTick             ((SysTick_Type   *)     SysTick_BASE     ) /*!< SysTick configuration struct */
+  #define NVIC                ((NVIC_Type      *)     NVIC_BASE        ) /*!< NVIC configuration struct */
+  #define DWT                 ((DWT_Type       *)     DWT_BASE         ) /*!< DWT configuration struct */
+  #define TPI                 ((TPI_Type       *)     TPI_BASE         ) /*!< TPI configuration struct */
+  #define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE   ) /*!< Core Debug configuration struct */
+
+  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+    #define MPU_BASE          (SCS_BASE +  0x0D90UL)                     /*!< Memory Protection Unit */
+    #define MPU               ((MPU_Type       *)     MPU_BASE         ) /*!< Memory Protection Unit */
+  #endif
+
+  #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+    #define SAU_BASE          (SCS_BASE +  0x0DD0UL)                     /*!< Security Attribution Unit */
+    #define SAU               ((SAU_Type       *)     SAU_BASE         ) /*!< Security Attribution Unit */
+  #endif
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+  #define SCS_BASE_NS         (0xE002E000UL)                             /*!< System Control Space Base Address (non-secure address space) */
+  #define CoreDebug_BASE_NS   (0xE002EDF0UL)                             /*!< Core Debug Base Address           (non-secure address space) */
+  #define SysTick_BASE_NS     (SCS_BASE_NS +  0x0010UL)                  /*!< SysTick Base Address              (non-secure address space) */
+  #define NVIC_BASE_NS        (SCS_BASE_NS +  0x0100UL)                  /*!< NVIC Base Address                 (non-secure address space) */
+  #define SCB_BASE_NS         (SCS_BASE_NS +  0x0D00UL)                  /*!< System Control Block Base Address (non-secure address space) */
+
+  #define SCB_NS              ((SCB_Type       *)     SCB_BASE_NS      ) /*!< SCB configuration struct          (non-secure address space) */
+  #define SysTick_NS          ((SysTick_Type   *)     SysTick_BASE_NS  ) /*!< SysTick configuration struct      (non-secure address space) */
+  #define NVIC_NS             ((NVIC_Type      *)     NVIC_BASE_NS     ) /*!< NVIC configuration struct         (non-secure address space) */
+  #define CoreDebug_NS        ((CoreDebug_Type *)     CoreDebug_BASE_NS) /*!< Core Debug configuration struct   (non-secure address space) */
+
+  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+    #define MPU_BASE_NS       (SCS_BASE_NS +  0x0D90UL)                  /*!< Memory Protection Unit            (non-secure address space) */
+    #define MPU_NS            ((MPU_Type       *)     MPU_BASE_NS      ) /*!< Memory Protection Unit            (non-secure address space) */
+  #endif
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+  #endif
+  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+/*#define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping   not available for Cortex-M23 */
+/*#define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping   not available for Cortex-M23 */
+  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
+  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
+  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
+  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+  #define NVIC_GetActive              __NVIC_GetActive
+  #define NVIC_SetPriority            __NVIC_SetPriority
+  #define NVIC_GetPriority            __NVIC_GetPriority
+  #define NVIC_SystemReset            __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+  #endif
+  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetVector              __NVIC_SetVector
+  #define NVIC_GetVector              __NVIC_GetVector
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET          16
+
+
+/* Special LR values for Secure/Non-Secure call handling and exception handling                                               */
+
+/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS                   */ 
+#define FNC_RETURN                 (0xFEFFFFFFUL)     /* bit [0] ignored when processing a branch                             */
+
+/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */
+#define EXC_RETURN_PREFIX          (0xFF000000UL)     /* bits [31:24] set to indicate an EXC_RETURN value                     */
+#define EXC_RETURN_S               (0x00000040UL)     /* bit [6] stack used to push registers: 0=Non-secure 1=Secure          */
+#define EXC_RETURN_DCRS            (0x00000020UL)     /* bit [5] stacking rules for called registers: 0=skipped 1=saved       */
+#define EXC_RETURN_FTYPE           (0x00000010UL)     /* bit [4] allocate stack for floating-point context: 0=done 1=skipped  */
+#define EXC_RETURN_MODE            (0x00000008UL)     /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode      */
+#define EXC_RETURN_SPSEL           (0x00000002UL)     /* bit [1] stack pointer used to restore context: 0=MSP 1=PSP           */
+#define EXC_RETURN_ES              (0x00000001UL)     /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */
+
+/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking                            */
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)  /* Value for processors with floating-point extension:                  */
+#define EXC_INTEGRITY_SIGNATURE     (0xFEFA125AUL)     /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE                   */
+#else 
+#define EXC_INTEGRITY_SIGNATURE     (0xFEFA125BUL)     /* Value for processors without floating-point extension                */
+#endif
+
+	
+/* Interrupt Priorities are WORD accessible only under Armv6-M                  */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)
+#define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )
+#define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )
+
+#define __NVIC_SetPriorityGrouping(X) (void)(X)
+#define __NVIC_GetPriorityGrouping()  (0U)
+
+/**
+  \brief   Enable Interrupt
+  \details Enables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt
+  \details Disables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+    __DSB();
+    __ISB();
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Active Interrupt
+  \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not active.
+  \return             1  Interrupt status is active.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   Get Interrupt Target State
+  \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  if interrupt is assigned to Secure
+  \return             1  if interrupt is assigned to Non Secure
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Target State
+  \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  if interrupt is assigned to Secure
+                      1  if interrupt is assigned to Non Secure
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |=  ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
+    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Clear Interrupt Target State
+  \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  if interrupt is assigned to Secure
+                      1  if interrupt is assigned to Non Secure
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
+    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->IPR[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+  else
+  {
+    SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+
+
+/**
+  \brief   Encode Priority
+  \details Encodes the priority for an interrupt with the given priority group,
+           preemptive priority value, and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]     PriorityGroup  Used priority group.
+  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+  \param [in]       SubPriority  Subpriority value (starting from 0).
+  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  return (
+           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
+         );
+}
+
+
+/**
+  \brief   Decode Priority
+  \details Decodes an interrupt priority value with a given priority group to
+           preemptive priority value and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+  \param [in]     PriorityGroup  Used priority group.
+  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+  \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
+}
+
+
+/**
+  \brief   Set Interrupt Vector
+  \details Sets an interrupt vector in SRAM based interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+           VTOR must been relocated to SRAM before.
+           If VTOR is not present address 0 must be mapped to SRAM.
+  \param [in]   IRQn      Interrupt number
+  \param [in]   vector    Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+#else
+  uint32_t *vectors = (uint32_t *)0x0U;
+#endif
+  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+  \brief   Get Interrupt Vector
+  \details Reads an interrupt vector from interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn      Interrupt number.
+  \return                 Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+#else
+  uint32_t *vectors = (uint32_t *)0x0U;
+#endif
+  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+  __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+  SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                 SCB_AIRCR_SYSRESETREQ_Msk);
+  __DSB();                                                          /* Ensure completion of memory access */
+
+  for(;;)                                                           /* wait until reset */
+  {
+    __NOP();
+  }
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   Enable Interrupt (non-secure)
+  \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status (non-secure)
+  \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt (non-secure)
+  \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt (non-secure)
+  \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt (non-secure)
+  \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt (non-secure)
+  \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Active Interrupt (non-secure)
+  \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not active.
+  \return             1  Interrupt status is active.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Priority (non-secure)
+  \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every non-secure processor exception.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->IPR[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+  else
+  {
+    SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority (non-secure)
+  \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+#endif /*  defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+/* ##########################  MPU functions  #################################### */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+
+#include "mpu_armv8.h"
+
+#endif
+
+/* ##########################  FPU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions
+  \brief    Function that provides FPU type.
+  @{
+ */
+
+/**
+  \brief   get FPU type
+  \details returns the FPU type
+  \returns
+   - \b  0: No FPU
+   - \b  1: Single precision FPU
+   - \b  2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+    return 0U;           /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ##########################   SAU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SAUFunctions SAU Functions
+  \brief    Functions that configure the SAU.
+  @{
+ */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+
+/**
+  \brief   Enable SAU
+  \details Enables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Enable(void)
+{
+    SAU->CTRL |=  (SAU_CTRL_ENABLE_Msk);
+}
+
+
+
+/**
+  \brief   Disable SAU
+  \details Disables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Disable(void)
+{
+    SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
+}
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_SAUFunctions */
+
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                   /* Reload value impossible */
+  }
+
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                     /* Function successful */
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   System Tick Configuration (non-secure)
+  \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                         /* Reload value impossible */
+  }
+
+  SysTick_NS->LOAD  = (uint32_t)(ticks - 1UL);                            /* set reload register */
+  TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick_NS->VAL   = 0UL;                                                /* Load the SysTick Counter Value */
+  SysTick_NS->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                      SysTick_CTRL_TICKINT_Msk   |
+                      SysTick_CTRL_ENABLE_Msk;                            /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                           /* Function successful */
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM23_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/Drivers/CMSIS/Include/core_cm3.h b/Drivers/CMSIS/Include/core_cm3.h
new file mode 100644
index 0000000..b0dfbd3
--- /dev/null
+++ b/Drivers/CMSIS/Include/core_cm3.h
@@ -0,0 +1,1941 @@
+/**************************************************************************//**
+ * @file     core_cm3.h
+ * @brief    CMSIS Cortex-M3 Core Peripheral Access Layer Header File
+ * @version  V5.0.8
+ * @date     04. June 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM3_H_GENERIC
+#define __CORE_CM3_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup Cortex_M3
+  @{
+ */
+
+#include "cmsis_version.h"
+
+/*  CMSIS CM3 definitions */
+#define __CM3_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)              /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __CM3_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)               /*!< \deprecated [15:0]  CMSIS HAL sub version */
+#define __CM3_CMSIS_VERSION       ((__CM3_CMSIS_VERSION_MAIN << 16U) | \
+                                    __CM3_CMSIS_VERSION_SUB           )  /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M                (3U)                                   /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    This core does not support an FPU at all
+*/
+#define __FPU_USED       0U
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #if defined __ARM_PCS_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TI_ARM__ )
+  #if defined __TI_VFP_SUPPORT__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __CSMC__ )
+  #if ( __CSMC__ & 0x400U)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#endif
+
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM3_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM3_H_DEPENDANT
+#define __CORE_CM3_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM3_REV
+    #define __CM3_REV               0x0200U
+    #warning "__CM3_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0U
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          3U
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0U
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M3 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core Debug Register
+  - Core MPU Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+#define APSR_Q_Pos                         27U                                            /*!< APSR: Q Position */
+#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */
+
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:1;               /*!< bit:      9  Reserved */
+    uint32_t ICI_IT_1:6;                 /*!< bit: 10..15  ICI/IT part 1 */
+    uint32_t _reserved1:8;               /*!< bit: 16..23  Reserved */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit */
+    uint32_t ICI_IT_2:2;                 /*!< bit: 25..26  ICI/IT part 2 */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos                         27U                                            /*!< xPSR: Q Position */
+#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */
+
+#define xPSR_ICI_IT_2_Pos                  25U                                            /*!< xPSR: ICI/IT part 2 Position */
+#define xPSR_ICI_IT_2_Msk                  (3UL << xPSR_ICI_IT_2_Pos)                     /*!< xPSR: ICI/IT part 2 Mask */
+
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_ICI_IT_1_Pos                  10U                                            /*!< xPSR: ICI/IT part 1 Position */
+#define xPSR_ICI_IT_1_Msk                  (0x3FUL << xPSR_ICI_IT_1_Pos)                  /*!< xPSR: ICI/IT part 1 Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */
+    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IOM uint32_t ISER[8U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+        uint32_t RESERVED0[24U];
+  __IOM uint32_t ICER[8U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+        uint32_t RSERVED1[24U];
+  __IOM uint32_t ISPR[8U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+        uint32_t RESERVED2[24U];
+  __IOM uint32_t ICPR[8U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+        uint32_t RESERVED3[24U];
+  __IOM uint32_t IABR[8U];               /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */
+        uint32_t RESERVED4[56U];
+  __IOM uint8_t  IP[240U];               /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
+        uint32_t RESERVED5[644U];
+  __OM  uint32_t STIR;                   /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register */
+}  NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos                 0U                                         /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
+  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+  __IOM uint8_t  SHP[12U];               /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
+  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+  __IOM uint32_t CFSR;                   /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register */
+  __IOM uint32_t HFSR;                   /*!< Offset: 0x02C (R/W)  HardFault Status Register */
+  __IOM uint32_t DFSR;                   /*!< Offset: 0x030 (R/W)  Debug Fault Status Register */
+  __IOM uint32_t MMFAR;                  /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register */
+  __IOM uint32_t BFAR;                   /*!< Offset: 0x038 (R/W)  BusFault Address Register */
+  __IOM uint32_t AFSR;                   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register */
+  __IM  uint32_t PFR[2U];                /*!< Offset: 0x040 (R/ )  Processor Feature Register */
+  __IM  uint32_t DFR;                    /*!< Offset: 0x048 (R/ )  Debug Feature Register */
+  __IM  uint32_t ADR;                    /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */
+  __IM  uint32_t MMFR[4U];               /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */
+  __IM  uint32_t ISAR[5U];               /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register */
+        uint32_t RESERVED0[5U];
+  __IOM uint32_t CPACR;                  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#if defined (__CM3_REV) && (__CM3_REV < 0x0201U)                   /* core r2p1 */
+#define SCB_VTOR_TBLBASE_Pos               29U                                            /*!< SCB VTOR: TBLBASE Position */
+#define SCB_VTOR_TBLBASE_Msk               (1UL << SCB_VTOR_TBLBASE_Pos)                  /*!< SCB VTOR: TBLBASE Mask */
+
+#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos)            /*!< SCB VTOR: TBLOFF Mask */
+#else
+#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
+#endif
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos              8U                                            /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos             0U                                            /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk            (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)           /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos          0U                                            /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk         (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)        /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos          18U                                            /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos          17U                                            /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos          16U                                            /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos       14U                                            /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos       13U                                            /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos       12U                                            /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos            8U                                            /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos           3U                                            /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos           1U                                            /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos           0U                                            /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos            16U                                            /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos             8U                                            /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos             0U                                            /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_MMARVALID_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 7U)               /*!< SCB CFSR (MMFSR): MMARVALID Position */
+#define SCB_CFSR_MMARVALID_Msk             (1UL << SCB_CFSR_MMARVALID_Pos)                /*!< SCB CFSR (MMFSR): MMARVALID Mask */
+
+#define SCB_CFSR_MSTKERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 4U)               /*!< SCB CFSR (MMFSR): MSTKERR Position */
+#define SCB_CFSR_MSTKERR_Msk               (1UL << SCB_CFSR_MSTKERR_Pos)                  /*!< SCB CFSR (MMFSR): MSTKERR Mask */
+
+#define SCB_CFSR_MUNSTKERR_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 3U)               /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
+#define SCB_CFSR_MUNSTKERR_Msk             (1UL << SCB_CFSR_MUNSTKERR_Pos)                /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
+
+#define SCB_CFSR_DACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 1U)               /*!< SCB CFSR (MMFSR): DACCVIOL Position */
+#define SCB_CFSR_DACCVIOL_Msk              (1UL << SCB_CFSR_DACCVIOL_Pos)                 /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
+
+#define SCB_CFSR_IACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 0U)               /*!< SCB CFSR (MMFSR): IACCVIOL Position */
+#define SCB_CFSR_IACCVIOL_Msk              (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)             /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
+
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_BFARVALID_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 7U)                  /*!< SCB CFSR (BFSR): BFARVALID Position */
+#define SCB_CFSR_BFARVALID_Msk            (1UL << SCB_CFSR_BFARVALID_Pos)                 /*!< SCB CFSR (BFSR): BFARVALID Mask */
+
+#define SCB_CFSR_STKERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 4U)                  /*!< SCB CFSR (BFSR): STKERR Position */
+#define SCB_CFSR_STKERR_Msk               (1UL << SCB_CFSR_STKERR_Pos)                    /*!< SCB CFSR (BFSR): STKERR Mask */
+
+#define SCB_CFSR_UNSTKERR_Pos             (SCB_CFSR_BUSFAULTSR_Pos + 3U)                  /*!< SCB CFSR (BFSR): UNSTKERR Position */
+#define SCB_CFSR_UNSTKERR_Msk             (1UL << SCB_CFSR_UNSTKERR_Pos)                  /*!< SCB CFSR (BFSR): UNSTKERR Mask */
+
+#define SCB_CFSR_IMPRECISERR_Pos          (SCB_CFSR_BUSFAULTSR_Pos + 2U)                  /*!< SCB CFSR (BFSR): IMPRECISERR Position */
+#define SCB_CFSR_IMPRECISERR_Msk          (1UL << SCB_CFSR_IMPRECISERR_Pos)               /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
+
+#define SCB_CFSR_PRECISERR_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 1U)                  /*!< SCB CFSR (BFSR): PRECISERR Position */
+#define SCB_CFSR_PRECISERR_Msk            (1UL << SCB_CFSR_PRECISERR_Pos)                 /*!< SCB CFSR (BFSR): PRECISERR Mask */
+
+#define SCB_CFSR_IBUSERR_Pos              (SCB_CFSR_BUSFAULTSR_Pos + 0U)                  /*!< SCB CFSR (BFSR): IBUSERR Position */
+#define SCB_CFSR_IBUSERR_Msk              (1UL << SCB_CFSR_IBUSERR_Pos)                   /*!< SCB CFSR (BFSR): IBUSERR Mask */
+
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_DIVBYZERO_Pos            (SCB_CFSR_USGFAULTSR_Pos + 9U)                  /*!< SCB CFSR (UFSR): DIVBYZERO Position */
+#define SCB_CFSR_DIVBYZERO_Msk            (1UL << SCB_CFSR_DIVBYZERO_Pos)                 /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
+
+#define SCB_CFSR_UNALIGNED_Pos            (SCB_CFSR_USGFAULTSR_Pos + 8U)                  /*!< SCB CFSR (UFSR): UNALIGNED Position */
+#define SCB_CFSR_UNALIGNED_Msk            (1UL << SCB_CFSR_UNALIGNED_Pos)                 /*!< SCB CFSR (UFSR): UNALIGNED Mask */
+
+#define SCB_CFSR_NOCP_Pos                 (SCB_CFSR_USGFAULTSR_Pos + 3U)                  /*!< SCB CFSR (UFSR): NOCP Position */
+#define SCB_CFSR_NOCP_Msk                 (1UL << SCB_CFSR_NOCP_Pos)                      /*!< SCB CFSR (UFSR): NOCP Mask */
+
+#define SCB_CFSR_INVPC_Pos                (SCB_CFSR_USGFAULTSR_Pos + 2U)                  /*!< SCB CFSR (UFSR): INVPC Position */
+#define SCB_CFSR_INVPC_Msk                (1UL << SCB_CFSR_INVPC_Pos)                     /*!< SCB CFSR (UFSR): INVPC Mask */
+
+#define SCB_CFSR_INVSTATE_Pos             (SCB_CFSR_USGFAULTSR_Pos + 1U)                  /*!< SCB CFSR (UFSR): INVSTATE Position */
+#define SCB_CFSR_INVSTATE_Msk             (1UL << SCB_CFSR_INVSTATE_Pos)                  /*!< SCB CFSR (UFSR): INVSTATE Mask */
+
+#define SCB_CFSR_UNDEFINSTR_Pos           (SCB_CFSR_USGFAULTSR_Pos + 0U)                  /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
+#define SCB_CFSR_UNDEFINSTR_Msk           (1UL << SCB_CFSR_UNDEFINSTR_Pos)                /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos              31U                                            /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos                30U                                            /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos                1U                                            /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos               4U                                            /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos                 3U                                            /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos                2U                                            /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos                   1U                                            /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos                 0U                                            /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+  \brief    Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+        uint32_t RESERVED0[1U];
+  __IM  uint32_t ICTR;                   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register */
+#if defined (__CM3_REV) && (__CM3_REV >= 0x200U)
+  __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */
+#else
+        uint32_t RESERVED1[1U];
+#endif
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos         0U                                         /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+
+#define SCnSCB_ACTLR_DISFOLD_Pos            2U                                         /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Msk           (1UL << SCnSCB_ACTLR_DISFOLD_Pos)           /*!< ACTLR: DISFOLD Mask */
+
+#define SCnSCB_ACTLR_DISDEFWBUF_Pos         1U                                         /*!< ACTLR: DISDEFWBUF Position */
+#define SCnSCB_ACTLR_DISDEFWBUF_Msk        (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos)        /*!< ACTLR: DISDEFWBUF Mask */
+
+#define SCnSCB_ACTLR_DISMCYCINT_Pos         0U                                         /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/)    /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
+  \brief    Type definitions for the Instrumentation Trace Macrocell (ITM)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+  __OM  union
+  {
+    __OM  uint8_t    u8;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */
+    __OM  uint16_t   u16;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */
+    __OM  uint32_t   u32;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */
+  }  PORT [32U];                         /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers */
+        uint32_t RESERVED0[864U];
+  __IOM uint32_t TER;                    /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register */
+        uint32_t RESERVED1[15U];
+  __IOM uint32_t TPR;                    /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */
+        uint32_t RESERVED2[15U];
+  __IOM uint32_t TCR;                    /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */
+        uint32_t RESERVED3[29U];
+  __OM  uint32_t IWR;                    /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register */
+  __IM  uint32_t IRR;                    /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register */
+  __IOM uint32_t IMCR;                   /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register */
+        uint32_t RESERVED4[43U];
+  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register */
+  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register */
+        uint32_t RESERVED5[6U];
+  __IM  uint32_t PID4;                   /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
+  __IM  uint32_t PID5;                   /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
+  __IM  uint32_t PID6;                   /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
+  __IM  uint32_t PID7;                   /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
+  __IM  uint32_t PID0;                   /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
+  __IM  uint32_t PID1;                   /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
+  __IM  uint32_t PID2;                   /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
+  __IM  uint32_t PID3;                   /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
+  __IM  uint32_t CID0;                   /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
+  __IM  uint32_t CID1;                   /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
+  __IM  uint32_t CID2;                   /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
+  __IM  uint32_t CID3;                   /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos                0U                                            /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk               (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/)     /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos                   23U                                            /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos             16U                                            /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos                10U                                            /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos              8U                                            /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos                  4U                                            /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos                  3U                                            /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos                 2U                                            /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos                   1U                                            /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos                  0U                                            /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos                0U                                            /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk               (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)              /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos                0U                                            /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk               (1UL /*<< ITM_IRR_ATREADYM_Pos*/)              /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos            0U                                            /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk           (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)          /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos                 2U                                            /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos                  1U                                            /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos                 0U                                            /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
+  \brief    Type definitions for the Data Watchpoint and Trace (DWT)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */
+  __IOM uint32_t CYCCNT;                 /*!< Offset: 0x004 (R/W)  Cycle Count Register */
+  __IOM uint32_t CPICNT;                 /*!< Offset: 0x008 (R/W)  CPI Count Register */
+  __IOM uint32_t EXCCNT;                 /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register */
+  __IOM uint32_t SLEEPCNT;               /*!< Offset: 0x010 (R/W)  Sleep Count Register */
+  __IOM uint32_t LSUCNT;                 /*!< Offset: 0x014 (R/W)  LSU Count Register */
+  __IOM uint32_t FOLDCNT;                /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register */
+  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */
+  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */
+  __IOM uint32_t MASK0;                  /*!< Offset: 0x024 (R/W)  Mask Register 0 */
+  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */
+        uint32_t RESERVED0[1U];
+  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */
+  __IOM uint32_t MASK1;                  /*!< Offset: 0x034 (R/W)  Mask Register 1 */
+  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */
+        uint32_t RESERVED1[1U];
+  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */
+  __IOM uint32_t MASK2;                  /*!< Offset: 0x044 (R/W)  Mask Register 2 */
+  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */
+        uint32_t RESERVED2[1U];
+  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */
+  __IOM uint32_t MASK3;                  /*!< Offset: 0x054 (R/W)  Mask Register 3 */
+  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos             22U                                         /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos            21U                                         /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos             20U                                         /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos           19U                                         /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos             18U                                         /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos             17U                                         /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos             16U                                         /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos            12U                                         /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos               10U                                         /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos                 9U                                         /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos               5U                                         /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos             1U                                         /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos              0U                                         /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos               0U                                         /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos               0U                                         /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos           0U                                         /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos               0U                                         /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos             0U                                         /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos                   0U                                         /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk                  (0x1FUL /*<< DWT_MASK_MASK_Pos*/)           /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos        16U                                         /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos        12U                                         /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos            9U                                         /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos         8U                                         /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos           7U                                         /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos          5U                                         /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos           0U                                         /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/)    /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_TPI     Trace Port Interface (TPI)
+  \brief    Type definitions for the Trace Port Interface (TPI)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+  __IM  uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */
+  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
+        uint32_t RESERVED0[2U];
+  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
+        uint32_t RESERVED1[55U];
+  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
+        uint32_t RESERVED2[131U];
+  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
+  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
+  __IM  uint32_t FSCR;                   /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
+        uint32_t RESERVED3[759U];
+  __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER Register */
+  __IM  uint32_t FIFO0;                  /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
+  __IM  uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
+        uint32_t RESERVED4[1U];
+  __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
+  __IM  uint32_t FIFO1;                  /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
+  __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
+        uint32_t RESERVED5[39U];
+  __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */
+  __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
+        uint32_t RESERVED7[8U];
+  __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
+  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos                 16U                                         /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos                  8U                                         /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos                  0U                                         /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk                 (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)          /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY2_Pos          0U                                         /*!< TPI ITATBCTR2: ATREADY2 Position */
+#define TPI_ITATBCTR2_ATREADY2_Msk         (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/)   /*!< TPI ITATBCTR2: ATREADY2 Mask */
+
+#define TPI_ITATBCTR2_ATREADY1_Pos          0U                                         /*!< TPI ITATBCTR2: ATREADY1 Position */
+#define TPI_ITATBCTR2_ATREADY1_Msk         (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/)   /*!< TPI ITATBCTR2: ATREADY1 Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos                 16U                                         /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos                  8U                                         /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos                  0U                                         /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk                 (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)          /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY2_Pos          0U                                         /*!< TPI ITATBCTR0: ATREADY2 Position */
+#define TPI_ITATBCTR0_ATREADY2_Msk         (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/)   /*!< TPI ITATBCTR0: ATREADY2 Mask */
+
+#define TPI_ITATBCTR0_ATREADY1_Pos          0U                                         /*!< TPI ITATBCTR0: ATREADY1 Position */
+#define TPI_ITATBCTR0_ATREADY1_Msk         (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/)   /*!< TPI ITATBCTR0: ATREADY1 Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk                (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos              6U                                         /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos             5U                                         /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos             4U                                         /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos           0U                                         /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+  \brief    Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
+  __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */
+  __IOM uint32_t RBAR_A1;                /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register */
+  __IOM uint32_t RASR_A1;                /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */
+  __IOM uint32_t RBAR_A2;                /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register */
+  __IOM uint32_t RASR_A2;                /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */
+  __IOM uint32_t RBAR_A3;                /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register */
+  __IOM uint32_t RASR_A3;                /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+#define MPU_TYPE_RALIASES                  4U
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos                   5U                                            /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos                    28U                                            /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos                    24U                                            /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos                     18U                                            /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos                     17U                                            /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos                     16U                                            /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    Type definitions for the Core Debug Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */
+  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */
+  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */
+  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5U                                            /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos         24U                                            /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos        19U                                            /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos       18U                                            /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos       17U                                            /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos         16U                                            /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos       9U                                            /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos       8U                                            /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos      7U                                            /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos       6U                                            /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5U                                            /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos        4U                                            /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
+#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address */
+#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address */
+#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address */
+#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
+
+#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */
+#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct */
+#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct */
+#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct */
+#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit */
+  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Debug Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+  #endif
+  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
+  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
+  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
+  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
+  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
+  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+  #define NVIC_GetActive              __NVIC_GetActive
+  #define NVIC_SetPriority            __NVIC_SetPriority
+  #define NVIC_GetPriority            __NVIC_GetPriority
+  #define NVIC_SystemReset            __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+   #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+  #endif
+  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetVector              __NVIC_SetVector
+  #define NVIC_GetVector              __NVIC_GetVector
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET          16
+
+
+/* The following EXC_RETURN values are saved the LR on exception entry */
+#define EXC_RETURN_HANDLER         (0xFFFFFFF1UL)     /* return to Handler mode, uses MSP after return                               */
+#define EXC_RETURN_THREAD_MSP      (0xFFFFFFF9UL)     /* return to Thread mode, uses MSP after return                                */
+#define EXC_RETURN_THREAD_PSP      (0xFFFFFFFDUL)     /* return to Thread mode, uses PSP after return                                */
+
+
+/**
+  \brief   Set Priority Grouping
+  \details Sets the priority grouping field using the required unlock sequence.
+           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+           Only values from 0..7 are used.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]      PriorityGroup  Priority grouping field.
+ */
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+  uint32_t reg_value;
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
+
+  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
+  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */
+  reg_value  =  (reg_value                                   |
+                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) );               /* Insert write key and priority group */
+  SCB->AIRCR =  reg_value;
+}
+
+
+/**
+  \brief   Get Priority Grouping
+  \details Reads the priority grouping field from the NVIC Interrupt Controller.
+  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
+{
+  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+  \brief   Enable Interrupt
+  \details Enables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt
+  \details Disables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+    __DSB();
+    __ISB();
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Active Interrupt
+  \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not active.
+  \return             1  Interrupt status is active.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->IP[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+  else
+  {
+    SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return(((uint32_t)NVIC->IP[((uint32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+
+
+/**
+  \brief   Encode Priority
+  \details Encodes the priority for an interrupt with the given priority group,
+           preemptive priority value, and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]     PriorityGroup  Used priority group.
+  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+  \param [in]       SubPriority  Subpriority value (starting from 0).
+  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  return (
+           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
+         );
+}
+
+
+/**
+  \brief   Decode Priority
+  \details Decodes an interrupt priority value with a given priority group to
+           preemptive priority value and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+  \param [in]     PriorityGroup  Used priority group.
+  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+  \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
+}
+
+
+/**
+  \brief   Set Interrupt Vector
+  \details Sets an interrupt vector in SRAM based interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+           VTOR must been relocated to SRAM before.
+  \param [in]   IRQn      Interrupt number
+  \param [in]   vector    Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+  \brief   Get Interrupt Vector
+  \details Reads an interrupt vector from interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn      Interrupt number.
+  \return                 Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+  __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
+                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */
+  __DSB();                                                          /* Ensure completion of memory access */
+
+  for(;;)                                                           /* wait until reset */
+  {
+    __NOP();
+  }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+/* ##########################  MPU functions  #################################### */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+
+#include "mpu_armv7.h"
+
+#endif
+
+/* ##########################  FPU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions
+  \brief    Function that provides FPU type.
+  @{
+ */
+
+/**
+  \brief   get FPU type
+  \details returns the FPU type
+  \returns
+   - \b  0: No FPU
+   - \b  1: Single precision FPU
+   - \b  2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+    return 0U;           /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                   /* Reload value impossible */
+  }
+
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                     /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_core_DebugFunctions ITM Functions
+  \brief    Functions that access the ITM debug interface.
+  @{
+ */
+
+extern volatile int32_t ITM_RxBuffer;                              /*!< External variable to receive characters. */
+#define                 ITM_RXBUFFER_EMPTY  ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/**
+  \brief   ITM Send Character
+  \details Transmits a character via the ITM channel 0, and
+           \li Just returns when no debugger is connected that has booked the output.
+           \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+  \param [in]     ch  Character to transmit.
+  \returns            Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */
+      ((ITM->TER & 1UL               ) != 0UL)   )     /* ITM Port #0 enabled */
+  {
+    while (ITM->PORT[0U].u32 == 0UL)
+    {
+      __NOP();
+    }
+    ITM->PORT[0U].u8 = (uint8_t)ch;
+  }
+  return (ch);
+}
+
+
+/**
+  \brief   ITM Receive Character
+  \details Inputs a character via the external variable \ref ITM_RxBuffer.
+  \return             Received character.
+  \return         -1  No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)
+{
+  int32_t ch = -1;                           /* no character available */
+
+  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
+  {
+    ch = ITM_RxBuffer;
+    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
+  }
+
+  return (ch);
+}
+
+
+/**
+  \brief   ITM Check Character
+  \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+  \return          0  No character available.
+  \return          1  Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void)
+{
+
+  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
+  {
+    return (0);                              /* no character available */
+  }
+  else
+  {
+    return (1);                              /*    character available */
+  }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM3_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/Drivers/CMSIS/Include/core_cm33.h b/Drivers/CMSIS/Include/core_cm33.h
new file mode 100644
index 0000000..02f82e2
--- /dev/null
+++ b/Drivers/CMSIS/Include/core_cm33.h
@@ -0,0 +1,3002 @@
+/**************************************************************************//**
+ * @file     core_cm33.h
+ * @brief    CMSIS Cortex-M33 Core Peripheral Access Layer Header File
+ * @version  V5.0.9
+ * @date     06. July 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM33_H_GENERIC
+#define __CORE_CM33_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup Cortex_M33
+  @{
+ */
+
+#include "cmsis_version.h"
+
+/*  CMSIS CM33 definitions */
+#define __CM33_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)                   /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __CM33_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)                    /*!< \deprecated [15:0]  CMSIS HAL sub version */
+#define __CM33_CMSIS_VERSION       ((__CM33_CMSIS_VERSION_MAIN << 16U) | \
+                                     __CM33_CMSIS_VERSION_SUB           )      /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M                 (33U)                                       /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
+*/
+#if defined ( __CC_ARM )
+  #if defined (__TARGET_FPU_VFP)
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+  #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)
+    #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)
+      #define __DSP_USED       1U
+    #else
+      #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
+      #define __DSP_USED         0U
+    #endif
+  #else
+    #define __DSP_USED         0U
+  #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #if defined (__ARM_PCS_VFP)
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+  #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)
+    #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)
+      #define __DSP_USED       1U
+    #else
+      #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
+      #define __DSP_USED         0U
+    #endif
+  #else
+    #define __DSP_USED         0U
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+  #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)
+    #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)
+      #define __DSP_USED       1U
+    #else
+      #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
+      #define __DSP_USED         0U
+    #endif
+  #else
+    #define __DSP_USED         0U
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined (__ARMVFP__)
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+  #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)
+    #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)
+      #define __DSP_USED       1U
+    #else
+      #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
+      #define __DSP_USED         0U
+    #endif
+  #else
+    #define __DSP_USED         0U
+  #endif
+
+#elif defined ( __TI_ARM__ )
+  #if defined (__TI_VFP_SUPPORT__)
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined (__FPU_VFP__)
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __CSMC__ )
+  #if ( __CSMC__ & 0x400U)
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#endif
+
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM33_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM33_H_DEPENDANT
+#define __CORE_CM33_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM33_REV
+    #define __CM33_REV                0x0000U
+    #warning "__CM33_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __FPU_PRESENT
+    #define __FPU_PRESENT             0U
+    #warning "__FPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0U
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __SAUREGION_PRESENT
+    #define __SAUREGION_PRESENT       0U
+    #warning "__SAUREGION_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __DSP_PRESENT
+    #define __DSP_PRESENT             0U
+    #warning "__DSP_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          3U
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0U
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M33 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core Debug Register
+  - Core MPU Register
+  - Core SAU Register
+  - Core FPU Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */
+    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+#define APSR_Q_Pos                         27U                                            /*!< APSR: Q Position */
+#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */
+
+#define APSR_GE_Pos                        16U                                            /*!< APSR: GE Position */
+#define APSR_GE_Msk                        (0xFUL << APSR_GE_Pos)                         /*!< APSR: GE Mask */
+
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */
+    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */
+    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0) */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos                         27U                                            /*!< xPSR: Q Position */
+#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */
+
+#define xPSR_IT_Pos                        25U                                            /*!< xPSR: IT Position */
+#define xPSR_IT_Msk                        (3UL << xPSR_IT_Pos)                           /*!< xPSR: IT Mask */
+
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_GE_Pos                        16U                                            /*!< xPSR: GE Position */
+#define xPSR_GE_Msk                        (0xFUL << xPSR_GE_Pos)                         /*!< xPSR: GE Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack-pointer select */
+    uint32_t FPCA:1;                     /*!< bit:      2  Floating-point context active */
+    uint32_t SFPA:1;                     /*!< bit:      3  Secure floating-point active */
+    uint32_t _reserved1:28;              /*!< bit:  4..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SFPA_Pos                    3U                                            /*!< CONTROL: SFPA Position */
+#define CONTROL_SFPA_Msk                   (1UL << CONTROL_SFPA_Pos)                      /*!< CONTROL: SFPA Mask */
+
+#define CONTROL_FPCA_Pos                    2U                                            /*!< CONTROL: FPCA Position */
+#define CONTROL_FPCA_Msk                   (1UL << CONTROL_FPCA_Pos)                      /*!< CONTROL: FPCA Mask */
+
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IOM uint32_t ISER[16U];              /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+        uint32_t RESERVED0[16U];
+  __IOM uint32_t ICER[16U];              /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+        uint32_t RSERVED1[16U];
+  __IOM uint32_t ISPR[16U];              /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+        uint32_t RESERVED2[16U];
+  __IOM uint32_t ICPR[16U];              /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+        uint32_t RESERVED3[16U];
+  __IOM uint32_t IABR[16U];              /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */
+        uint32_t RESERVED4[16U];
+  __IOM uint32_t ITNS[16U];              /*!< Offset: 0x280 (R/W)  Interrupt Non-Secure State Register */
+        uint32_t RESERVED5[16U];
+  __IOM uint8_t  IPR[496U];              /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
+        uint32_t RESERVED6[580U];
+  __OM  uint32_t STIR;                   /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register */
+}  NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos                 0U                                         /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
+  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+  __IOM uint8_t  SHPR[12U];              /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
+  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+  __IOM uint32_t CFSR;                   /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register */
+  __IOM uint32_t HFSR;                   /*!< Offset: 0x02C (R/W)  HardFault Status Register */
+  __IOM uint32_t DFSR;                   /*!< Offset: 0x030 (R/W)  Debug Fault Status Register */
+  __IOM uint32_t MMFAR;                  /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register */
+  __IOM uint32_t BFAR;                   /*!< Offset: 0x038 (R/W)  BusFault Address Register */
+  __IOM uint32_t AFSR;                   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register */
+  __IM  uint32_t ID_PFR[2U];             /*!< Offset: 0x040 (R/ )  Processor Feature Register */
+  __IM  uint32_t ID_DFR;                 /*!< Offset: 0x048 (R/ )  Debug Feature Register */
+  __IM  uint32_t ID_ADR;                 /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */
+  __IM  uint32_t ID_MMFR[4U];            /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */
+  __IM  uint32_t ID_ISAR[6U];            /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register */
+  __IM  uint32_t CLIDR;                  /*!< Offset: 0x078 (R/ )  Cache Level ID register */
+  __IM  uint32_t CTR;                    /*!< Offset: 0x07C (R/ )  Cache Type register */
+  __IM  uint32_t CCSIDR;                 /*!< Offset: 0x080 (R/ )  Cache Size ID Register */
+  __IOM uint32_t CSSELR;                 /*!< Offset: 0x084 (R/W)  Cache Size Selection Register */
+  __IOM uint32_t CPACR;                  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register */
+  __IOM uint32_t NSACR;                  /*!< Offset: 0x08C (R/W)  Non-Secure Access Control Register */
+        uint32_t RESERVED3[92U];
+  __OM  uint32_t STIR;                   /*!< Offset: 0x200 ( /W)  Software Triggered Interrupt Register */
+        uint32_t RESERVED4[15U];
+  __IM  uint32_t MVFR0;                  /*!< Offset: 0x240 (R/ )  Media and VFP Feature Register 0 */
+  __IM  uint32_t MVFR1;                  /*!< Offset: 0x244 (R/ )  Media and VFP Feature Register 1 */
+  __IM  uint32_t MVFR2;                  /*!< Offset: 0x248 (R/ )  Media and VFP Feature Register 2 */
+        uint32_t RESERVED5[1U];
+  __OM  uint32_t ICIALLU;                /*!< Offset: 0x250 ( /W)  I-Cache Invalidate All to PoU */
+        uint32_t RESERVED6[1U];
+  __OM  uint32_t ICIMVAU;                /*!< Offset: 0x258 ( /W)  I-Cache Invalidate by MVA to PoU */
+  __OM  uint32_t DCIMVAC;                /*!< Offset: 0x25C ( /W)  D-Cache Invalidate by MVA to PoC */
+  __OM  uint32_t DCISW;                  /*!< Offset: 0x260 ( /W)  D-Cache Invalidate by Set-way */
+  __OM  uint32_t DCCMVAU;                /*!< Offset: 0x264 ( /W)  D-Cache Clean by MVA to PoU */
+  __OM  uint32_t DCCMVAC;                /*!< Offset: 0x268 ( /W)  D-Cache Clean by MVA to PoC */
+  __OM  uint32_t DCCSW;                  /*!< Offset: 0x26C ( /W)  D-Cache Clean by Set-way */
+  __OM  uint32_t DCCIMVAC;               /*!< Offset: 0x270 ( /W)  D-Cache Clean and Invalidate by MVA to PoC */
+  __OM  uint32_t DCCISW;                 /*!< Offset: 0x274 ( /W)  D-Cache Clean and Invalidate by Set-way */
+        uint32_t RESERVED7[6U];
+  __IOM uint32_t ITCMCR;                 /*!< Offset: 0x290 (R/W)  Instruction Tightly-Coupled Memory Control Register */
+  __IOM uint32_t DTCMCR;                 /*!< Offset: 0x294 (R/W)  Data Tightly-Coupled Memory Control Registers */
+  __IOM uint32_t AHBPCR;                 /*!< Offset: 0x298 (R/W)  AHBP Control Register */
+  __IOM uint32_t CACR;                   /*!< Offset: 0x29C (R/W)  L1 Cache Control Register */
+  __IOM uint32_t AHBSCR;                 /*!< Offset: 0x2A0 (R/W)  AHB Slave Control Register */
+        uint32_t RESERVED8[1U];
+  __IOM uint32_t ABFSR;                  /*!< Offset: 0x2A8 (R/W)  Auxiliary Bus Fault Status Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_PENDNMISET_Pos            31U                                            /*!< SCB ICSR: PENDNMISET Position */
+#define SCB_ICSR_PENDNMISET_Msk            (1UL << SCB_ICSR_PENDNMISET_Pos)               /*!< SCB ICSR: PENDNMISET Mask */
+
+#define SCB_ICSR_NMIPENDSET_Pos            SCB_ICSR_PENDNMISET_Pos                        /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */
+#define SCB_ICSR_NMIPENDSET_Msk            SCB_ICSR_PENDNMISET_Msk                        /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */
+
+#define SCB_ICSR_PENDNMICLR_Pos            30U                                            /*!< SCB ICSR: PENDNMICLR Position */
+#define SCB_ICSR_PENDNMICLR_Msk            (1UL << SCB_ICSR_PENDNMICLR_Pos)               /*!< SCB ICSR: PENDNMICLR Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_STTNS_Pos                 24U                                            /*!< SCB ICSR: STTNS Position (Security Extension) */
+#define SCB_ICSR_STTNS_Msk                 (1UL << SCB_ICSR_STTNS_Pos)                    /*!< SCB ICSR: STTNS Mask (Security Extension) */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIS_Pos                 14U                                            /*!< SCB AIRCR: PRIS Position */
+#define SCB_AIRCR_PRIS_Msk                 (1UL << SCB_AIRCR_PRIS_Pos)                    /*!< SCB AIRCR: PRIS Mask */
+
+#define SCB_AIRCR_BFHFNMINS_Pos            13U                                            /*!< SCB AIRCR: BFHFNMINS Position */
+#define SCB_AIRCR_BFHFNMINS_Msk            (1UL << SCB_AIRCR_BFHFNMINS_Pos)               /*!< SCB AIRCR: BFHFNMINS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos              8U                                            /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQS_Pos          3U                                            /*!< SCB AIRCR: SYSRESETREQS Position */
+#define SCB_AIRCR_SYSRESETREQS_Msk         (1UL << SCB_AIRCR_SYSRESETREQS_Pos)            /*!< SCB AIRCR: SYSRESETREQS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEPS_Pos              3U                                            /*!< SCB SCR: SLEEPDEEPS Position */
+#define SCB_SCR_SLEEPDEEPS_Msk             (1UL << SCB_SCR_SLEEPDEEPS_Pos)                /*!< SCB SCR: SLEEPDEEPS Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_BP_Pos                     18U                                            /*!< SCB CCR: BP Position */
+#define SCB_CCR_BP_Msk                     (1UL << SCB_CCR_BP_Pos)                        /*!< SCB CCR: BP Mask */
+
+#define SCB_CCR_IC_Pos                     17U                                            /*!< SCB CCR: IC Position */
+#define SCB_CCR_IC_Msk                     (1UL << SCB_CCR_IC_Pos)                        /*!< SCB CCR: IC Mask */
+
+#define SCB_CCR_DC_Pos                     16U                                            /*!< SCB CCR: DC Position */
+#define SCB_CCR_DC_Msk                     (1UL << SCB_CCR_DC_Pos)                        /*!< SCB CCR: DC Mask */
+
+#define SCB_CCR_STKOFHFNMIGN_Pos           10U                                            /*!< SCB CCR: STKOFHFNMIGN Position */
+#define SCB_CCR_STKOFHFNMIGN_Msk           (1UL << SCB_CCR_STKOFHFNMIGN_Pos)              /*!< SCB CCR: STKOFHFNMIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_HARDFAULTPENDED_Pos      21U                                            /*!< SCB SHCSR: HARDFAULTPENDED Position */
+#define SCB_SHCSR_HARDFAULTPENDED_Msk      (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)         /*!< SCB SHCSR: HARDFAULTPENDED Mask */
+
+#define SCB_SHCSR_SECUREFAULTPENDED_Pos    20U                                            /*!< SCB SHCSR: SECUREFAULTPENDED Position */
+#define SCB_SHCSR_SECUREFAULTPENDED_Msk    (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos)       /*!< SCB SHCSR: SECUREFAULTPENDED Mask */
+
+#define SCB_SHCSR_SECUREFAULTENA_Pos       19U                                            /*!< SCB SHCSR: SECUREFAULTENA Position */
+#define SCB_SHCSR_SECUREFAULTENA_Msk       (1UL << SCB_SHCSR_SECUREFAULTENA_Pos)          /*!< SCB SHCSR: SECUREFAULTENA Mask */
+
+#define SCB_SHCSR_USGFAULTENA_Pos          18U                                            /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos          17U                                            /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos          16U                                            /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos       14U                                            /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos       13U                                            /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos       12U                                            /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos            8U                                            /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_NMIACT_Pos                5U                                            /*!< SCB SHCSR: NMIACT Position */
+#define SCB_SHCSR_NMIACT_Msk               (1UL << SCB_SHCSR_NMIACT_Pos)                  /*!< SCB SHCSR: NMIACT Mask */
+
+#define SCB_SHCSR_SECUREFAULTACT_Pos        4U                                            /*!< SCB SHCSR: SECUREFAULTACT Position */
+#define SCB_SHCSR_SECUREFAULTACT_Msk       (1UL << SCB_SHCSR_SECUREFAULTACT_Pos)          /*!< SCB SHCSR: SECUREFAULTACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos           3U                                            /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_HARDFAULTACT_Pos          2U                                            /*!< SCB SHCSR: HARDFAULTACT Position */
+#define SCB_SHCSR_HARDFAULTACT_Msk         (1UL << SCB_SHCSR_HARDFAULTACT_Pos)            /*!< SCB SHCSR: HARDFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos           1U                                            /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos           0U                                            /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos            16U                                            /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos             8U                                            /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos             0U                                            /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_MMARVALID_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 7U)               /*!< SCB CFSR (MMFSR): MMARVALID Position */
+#define SCB_CFSR_MMARVALID_Msk             (1UL << SCB_CFSR_MMARVALID_Pos)                /*!< SCB CFSR (MMFSR): MMARVALID Mask */
+
+#define SCB_CFSR_MLSPERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 5U)               /*!< SCB CFSR (MMFSR): MLSPERR Position */
+#define SCB_CFSR_MLSPERR_Msk               (1UL << SCB_CFSR_MLSPERR_Pos)                  /*!< SCB CFSR (MMFSR): MLSPERR Mask */
+
+#define SCB_CFSR_MSTKERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 4U)               /*!< SCB CFSR (MMFSR): MSTKERR Position */
+#define SCB_CFSR_MSTKERR_Msk               (1UL << SCB_CFSR_MSTKERR_Pos)                  /*!< SCB CFSR (MMFSR): MSTKERR Mask */
+
+#define SCB_CFSR_MUNSTKERR_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 3U)               /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
+#define SCB_CFSR_MUNSTKERR_Msk             (1UL << SCB_CFSR_MUNSTKERR_Pos)                /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
+
+#define SCB_CFSR_DACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 1U)               /*!< SCB CFSR (MMFSR): DACCVIOL Position */
+#define SCB_CFSR_DACCVIOL_Msk              (1UL << SCB_CFSR_DACCVIOL_Pos)                 /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
+
+#define SCB_CFSR_IACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 0U)               /*!< SCB CFSR (MMFSR): IACCVIOL Position */
+#define SCB_CFSR_IACCVIOL_Msk              (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)             /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
+
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_BFARVALID_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 7U)                  /*!< SCB CFSR (BFSR): BFARVALID Position */
+#define SCB_CFSR_BFARVALID_Msk            (1UL << SCB_CFSR_BFARVALID_Pos)                 /*!< SCB CFSR (BFSR): BFARVALID Mask */
+
+#define SCB_CFSR_LSPERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 5U)                  /*!< SCB CFSR (BFSR): LSPERR Position */
+#define SCB_CFSR_LSPERR_Msk               (1UL << SCB_CFSR_LSPERR_Pos)                    /*!< SCB CFSR (BFSR): LSPERR Mask */
+
+#define SCB_CFSR_STKERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 4U)                  /*!< SCB CFSR (BFSR): STKERR Position */
+#define SCB_CFSR_STKERR_Msk               (1UL << SCB_CFSR_STKERR_Pos)                    /*!< SCB CFSR (BFSR): STKERR Mask */
+
+#define SCB_CFSR_UNSTKERR_Pos             (SCB_CFSR_BUSFAULTSR_Pos + 3U)                  /*!< SCB CFSR (BFSR): UNSTKERR Position */
+#define SCB_CFSR_UNSTKERR_Msk             (1UL << SCB_CFSR_UNSTKERR_Pos)                  /*!< SCB CFSR (BFSR): UNSTKERR Mask */
+
+#define SCB_CFSR_IMPRECISERR_Pos          (SCB_CFSR_BUSFAULTSR_Pos + 2U)                  /*!< SCB CFSR (BFSR): IMPRECISERR Position */
+#define SCB_CFSR_IMPRECISERR_Msk          (1UL << SCB_CFSR_IMPRECISERR_Pos)               /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
+
+#define SCB_CFSR_PRECISERR_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 1U)                  /*!< SCB CFSR (BFSR): PRECISERR Position */
+#define SCB_CFSR_PRECISERR_Msk            (1UL << SCB_CFSR_PRECISERR_Pos)                 /*!< SCB CFSR (BFSR): PRECISERR Mask */
+
+#define SCB_CFSR_IBUSERR_Pos              (SCB_CFSR_BUSFAULTSR_Pos + 0U)                  /*!< SCB CFSR (BFSR): IBUSERR Position */
+#define SCB_CFSR_IBUSERR_Msk              (1UL << SCB_CFSR_IBUSERR_Pos)                   /*!< SCB CFSR (BFSR): IBUSERR Mask */
+
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_DIVBYZERO_Pos            (SCB_CFSR_USGFAULTSR_Pos + 9U)                  /*!< SCB CFSR (UFSR): DIVBYZERO Position */
+#define SCB_CFSR_DIVBYZERO_Msk            (1UL << SCB_CFSR_DIVBYZERO_Pos)                 /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
+
+#define SCB_CFSR_UNALIGNED_Pos            (SCB_CFSR_USGFAULTSR_Pos + 8U)                  /*!< SCB CFSR (UFSR): UNALIGNED Position */
+#define SCB_CFSR_UNALIGNED_Msk            (1UL << SCB_CFSR_UNALIGNED_Pos)                 /*!< SCB CFSR (UFSR): UNALIGNED Mask */
+
+#define SCB_CFSR_STKOF_Pos                (SCB_CFSR_USGFAULTSR_Pos + 4U)                  /*!< SCB CFSR (UFSR): STKOF Position */
+#define SCB_CFSR_STKOF_Msk                (1UL << SCB_CFSR_STKOF_Pos)                     /*!< SCB CFSR (UFSR): STKOF Mask */
+
+#define SCB_CFSR_NOCP_Pos                 (SCB_CFSR_USGFAULTSR_Pos + 3U)                  /*!< SCB CFSR (UFSR): NOCP Position */
+#define SCB_CFSR_NOCP_Msk                 (1UL << SCB_CFSR_NOCP_Pos)                      /*!< SCB CFSR (UFSR): NOCP Mask */
+
+#define SCB_CFSR_INVPC_Pos                (SCB_CFSR_USGFAULTSR_Pos + 2U)                  /*!< SCB CFSR (UFSR): INVPC Position */
+#define SCB_CFSR_INVPC_Msk                (1UL << SCB_CFSR_INVPC_Pos)                     /*!< SCB CFSR (UFSR): INVPC Mask */
+
+#define SCB_CFSR_INVSTATE_Pos             (SCB_CFSR_USGFAULTSR_Pos + 1U)                  /*!< SCB CFSR (UFSR): INVSTATE Position */
+#define SCB_CFSR_INVSTATE_Msk             (1UL << SCB_CFSR_INVSTATE_Pos)                  /*!< SCB CFSR (UFSR): INVSTATE Mask */
+
+#define SCB_CFSR_UNDEFINSTR_Pos           (SCB_CFSR_USGFAULTSR_Pos + 0U)                  /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
+#define SCB_CFSR_UNDEFINSTR_Msk           (1UL << SCB_CFSR_UNDEFINSTR_Pos)                /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos              31U                                            /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos                30U                                            /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos                1U                                            /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos               4U                                            /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos                 3U                                            /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos                2U                                            /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos                   1U                                            /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos                 0U                                            /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */
+
+/* SCB Non-Secure Access Control Register Definitions */
+#define SCB_NSACR_CP11_Pos                 11U                                            /*!< SCB NSACR: CP11 Position */
+#define SCB_NSACR_CP11_Msk                 (1UL << SCB_NSACR_CP11_Pos)                    /*!< SCB NSACR: CP11 Mask */
+
+#define SCB_NSACR_CP10_Pos                 10U                                            /*!< SCB NSACR: CP10 Position */
+#define SCB_NSACR_CP10_Msk                 (1UL << SCB_NSACR_CP10_Pos)                    /*!< SCB NSACR: CP10 Mask */
+
+#define SCB_NSACR_CPn_Pos                   0U                                            /*!< SCB NSACR: CPn Position */
+#define SCB_NSACR_CPn_Msk                  (1UL /*<< SCB_NSACR_CPn_Pos*/)                 /*!< SCB NSACR: CPn Mask */
+
+/* SCB Cache Level ID Register Definitions */
+#define SCB_CLIDR_LOUU_Pos                 27U                                            /*!< SCB CLIDR: LoUU Position */
+#define SCB_CLIDR_LOUU_Msk                 (7UL << SCB_CLIDR_LOUU_Pos)                    /*!< SCB CLIDR: LoUU Mask */
+
+#define SCB_CLIDR_LOC_Pos                  24U                                            /*!< SCB CLIDR: LoC Position */
+#define SCB_CLIDR_LOC_Msk                  (7UL << SCB_CLIDR_LOC_Pos)                     /*!< SCB CLIDR: LoC Mask */
+
+/* SCB Cache Type Register Definitions */
+#define SCB_CTR_FORMAT_Pos                 29U                                            /*!< SCB CTR: Format Position */
+#define SCB_CTR_FORMAT_Msk                 (7UL << SCB_CTR_FORMAT_Pos)                    /*!< SCB CTR: Format Mask */
+
+#define SCB_CTR_CWG_Pos                    24U                                            /*!< SCB CTR: CWG Position */
+#define SCB_CTR_CWG_Msk                    (0xFUL << SCB_CTR_CWG_Pos)                     /*!< SCB CTR: CWG Mask */
+
+#define SCB_CTR_ERG_Pos                    20U                                            /*!< SCB CTR: ERG Position */
+#define SCB_CTR_ERG_Msk                    (0xFUL << SCB_CTR_ERG_Pos)                     /*!< SCB CTR: ERG Mask */
+
+#define SCB_CTR_DMINLINE_Pos               16U                                            /*!< SCB CTR: DminLine Position */
+#define SCB_CTR_DMINLINE_Msk               (0xFUL << SCB_CTR_DMINLINE_Pos)                /*!< SCB CTR: DminLine Mask */
+
+#define SCB_CTR_IMINLINE_Pos                0U                                            /*!< SCB CTR: ImInLine Position */
+#define SCB_CTR_IMINLINE_Msk               (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/)            /*!< SCB CTR: ImInLine Mask */
+
+/* SCB Cache Size ID Register Definitions */
+#define SCB_CCSIDR_WT_Pos                  31U                                            /*!< SCB CCSIDR: WT Position */
+#define SCB_CCSIDR_WT_Msk                  (1UL << SCB_CCSIDR_WT_Pos)                     /*!< SCB CCSIDR: WT Mask */
+
+#define SCB_CCSIDR_WB_Pos                  30U                                            /*!< SCB CCSIDR: WB Position */
+#define SCB_CCSIDR_WB_Msk                  (1UL << SCB_CCSIDR_WB_Pos)                     /*!< SCB CCSIDR: WB Mask */
+
+#define SCB_CCSIDR_RA_Pos                  29U                                            /*!< SCB CCSIDR: RA Position */
+#define SCB_CCSIDR_RA_Msk                  (1UL << SCB_CCSIDR_RA_Pos)                     /*!< SCB CCSIDR: RA Mask */
+
+#define SCB_CCSIDR_WA_Pos                  28U                                            /*!< SCB CCSIDR: WA Position */
+#define SCB_CCSIDR_WA_Msk                  (1UL << SCB_CCSIDR_WA_Pos)                     /*!< SCB CCSIDR: WA Mask */
+
+#define SCB_CCSIDR_NUMSETS_Pos             13U                                            /*!< SCB CCSIDR: NumSets Position */
+#define SCB_CCSIDR_NUMSETS_Msk             (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)           /*!< SCB CCSIDR: NumSets Mask */
+
+#define SCB_CCSIDR_ASSOCIATIVITY_Pos        3U                                            /*!< SCB CCSIDR: Associativity Position */
+#define SCB_CCSIDR_ASSOCIATIVITY_Msk       (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)      /*!< SCB CCSIDR: Associativity Mask */
+
+#define SCB_CCSIDR_LINESIZE_Pos             0U                                            /*!< SCB CCSIDR: LineSize Position */
+#define SCB_CCSIDR_LINESIZE_Msk            (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/)           /*!< SCB CCSIDR: LineSize Mask */
+
+/* SCB Cache Size Selection Register Definitions */
+#define SCB_CSSELR_LEVEL_Pos                1U                                            /*!< SCB CSSELR: Level Position */
+#define SCB_CSSELR_LEVEL_Msk               (7UL << SCB_CSSELR_LEVEL_Pos)                  /*!< SCB CSSELR: Level Mask */
+
+#define SCB_CSSELR_IND_Pos                  0U                                            /*!< SCB CSSELR: InD Position */
+#define SCB_CSSELR_IND_Msk                 (1UL /*<< SCB_CSSELR_IND_Pos*/)                /*!< SCB CSSELR: InD Mask */
+
+/* SCB Software Triggered Interrupt Register Definitions */
+#define SCB_STIR_INTID_Pos                  0U                                            /*!< SCB STIR: INTID Position */
+#define SCB_STIR_INTID_Msk                 (0x1FFUL /*<< SCB_STIR_INTID_Pos*/)            /*!< SCB STIR: INTID Mask */
+
+/* SCB D-Cache Invalidate by Set-way Register Definitions */
+#define SCB_DCISW_WAY_Pos                  30U                                            /*!< SCB DCISW: Way Position */
+#define SCB_DCISW_WAY_Msk                  (3UL << SCB_DCISW_WAY_Pos)                     /*!< SCB DCISW: Way Mask */
+
+#define SCB_DCISW_SET_Pos                   5U                                            /*!< SCB DCISW: Set Position */
+#define SCB_DCISW_SET_Msk                  (0x1FFUL << SCB_DCISW_SET_Pos)                 /*!< SCB DCISW: Set Mask */
+
+/* SCB D-Cache Clean by Set-way Register Definitions */
+#define SCB_DCCSW_WAY_Pos                  30U                                            /*!< SCB DCCSW: Way Position */
+#define SCB_DCCSW_WAY_Msk                  (3UL << SCB_DCCSW_WAY_Pos)                     /*!< SCB DCCSW: Way Mask */
+
+#define SCB_DCCSW_SET_Pos                   5U                                            /*!< SCB DCCSW: Set Position */
+#define SCB_DCCSW_SET_Msk                  (0x1FFUL << SCB_DCCSW_SET_Pos)                 /*!< SCB DCCSW: Set Mask */
+
+/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */
+#define SCB_DCCISW_WAY_Pos                 30U                                            /*!< SCB DCCISW: Way Position */
+#define SCB_DCCISW_WAY_Msk                 (3UL << SCB_DCCISW_WAY_Pos)                    /*!< SCB DCCISW: Way Mask */
+
+#define SCB_DCCISW_SET_Pos                  5U                                            /*!< SCB DCCISW: Set Position */
+#define SCB_DCCISW_SET_Msk                 (0x1FFUL << SCB_DCCISW_SET_Pos)                /*!< SCB DCCISW: Set Mask */
+
+/* Instruction Tightly-Coupled Memory Control Register Definitions */
+#define SCB_ITCMCR_SZ_Pos                   3U                                            /*!< SCB ITCMCR: SZ Position */
+#define SCB_ITCMCR_SZ_Msk                  (0xFUL << SCB_ITCMCR_SZ_Pos)                   /*!< SCB ITCMCR: SZ Mask */
+
+#define SCB_ITCMCR_RETEN_Pos                2U                                            /*!< SCB ITCMCR: RETEN Position */
+#define SCB_ITCMCR_RETEN_Msk               (1UL << SCB_ITCMCR_RETEN_Pos)                  /*!< SCB ITCMCR: RETEN Mask */
+
+#define SCB_ITCMCR_RMW_Pos                  1U                                            /*!< SCB ITCMCR: RMW Position */
+#define SCB_ITCMCR_RMW_Msk                 (1UL << SCB_ITCMCR_RMW_Pos)                    /*!< SCB ITCMCR: RMW Mask */
+
+#define SCB_ITCMCR_EN_Pos                   0U                                            /*!< SCB ITCMCR: EN Position */
+#define SCB_ITCMCR_EN_Msk                  (1UL /*<< SCB_ITCMCR_EN_Pos*/)                 /*!< SCB ITCMCR: EN Mask */
+
+/* Data Tightly-Coupled Memory Control Register Definitions */
+#define SCB_DTCMCR_SZ_Pos                   3U                                            /*!< SCB DTCMCR: SZ Position */
+#define SCB_DTCMCR_SZ_Msk                  (0xFUL << SCB_DTCMCR_SZ_Pos)                   /*!< SCB DTCMCR: SZ Mask */
+
+#define SCB_DTCMCR_RETEN_Pos                2U                                            /*!< SCB DTCMCR: RETEN Position */
+#define SCB_DTCMCR_RETEN_Msk               (1UL << SCB_DTCMCR_RETEN_Pos)                   /*!< SCB DTCMCR: RETEN Mask */
+
+#define SCB_DTCMCR_RMW_Pos                  1U                                            /*!< SCB DTCMCR: RMW Position */
+#define SCB_DTCMCR_RMW_Msk                 (1UL << SCB_DTCMCR_RMW_Pos)                    /*!< SCB DTCMCR: RMW Mask */
+
+#define SCB_DTCMCR_EN_Pos                   0U                                            /*!< SCB DTCMCR: EN Position */
+#define SCB_DTCMCR_EN_Msk                  (1UL /*<< SCB_DTCMCR_EN_Pos*/)                 /*!< SCB DTCMCR: EN Mask */
+
+/* AHBP Control Register Definitions */
+#define SCB_AHBPCR_SZ_Pos                   1U                                            /*!< SCB AHBPCR: SZ Position */
+#define SCB_AHBPCR_SZ_Msk                  (7UL << SCB_AHBPCR_SZ_Pos)                     /*!< SCB AHBPCR: SZ Mask */
+
+#define SCB_AHBPCR_EN_Pos                   0U                                            /*!< SCB AHBPCR: EN Position */
+#define SCB_AHBPCR_EN_Msk                  (1UL /*<< SCB_AHBPCR_EN_Pos*/)                 /*!< SCB AHBPCR: EN Mask */
+
+/* L1 Cache Control Register Definitions */
+#define SCB_CACR_FORCEWT_Pos                2U                                            /*!< SCB CACR: FORCEWT Position */
+#define SCB_CACR_FORCEWT_Msk               (1UL << SCB_CACR_FORCEWT_Pos)                  /*!< SCB CACR: FORCEWT Mask */
+
+#define SCB_CACR_ECCEN_Pos                  1U                                            /*!< SCB CACR: ECCEN Position */
+#define SCB_CACR_ECCEN_Msk                 (1UL << SCB_CACR_ECCEN_Pos)                    /*!< SCB CACR: ECCEN Mask */
+
+#define SCB_CACR_SIWT_Pos                   0U                                            /*!< SCB CACR: SIWT Position */
+#define SCB_CACR_SIWT_Msk                  (1UL /*<< SCB_CACR_SIWT_Pos*/)                 /*!< SCB CACR: SIWT Mask */
+
+/* AHBS Control Register Definitions */
+#define SCB_AHBSCR_INITCOUNT_Pos           11U                                            /*!< SCB AHBSCR: INITCOUNT Position */
+#define SCB_AHBSCR_INITCOUNT_Msk           (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos)           /*!< SCB AHBSCR: INITCOUNT Mask */
+
+#define SCB_AHBSCR_TPRI_Pos                 2U                                            /*!< SCB AHBSCR: TPRI Position */
+#define SCB_AHBSCR_TPRI_Msk                (0x1FFUL << SCB_AHBPCR_TPRI_Pos)               /*!< SCB AHBSCR: TPRI Mask */
+
+#define SCB_AHBSCR_CTL_Pos                  0U                                            /*!< SCB AHBSCR: CTL Position*/
+#define SCB_AHBSCR_CTL_Msk                 (3UL /*<< SCB_AHBPCR_CTL_Pos*/)                /*!< SCB AHBSCR: CTL Mask */
+
+/* Auxiliary Bus Fault Status Register Definitions */
+#define SCB_ABFSR_AXIMTYPE_Pos              8U                                            /*!< SCB ABFSR: AXIMTYPE Position*/
+#define SCB_ABFSR_AXIMTYPE_Msk             (3UL << SCB_ABFSR_AXIMTYPE_Pos)                /*!< SCB ABFSR: AXIMTYPE Mask */
+
+#define SCB_ABFSR_EPPB_Pos                  4U                                            /*!< SCB ABFSR: EPPB Position*/
+#define SCB_ABFSR_EPPB_Msk                 (1UL << SCB_ABFSR_EPPB_Pos)                    /*!< SCB ABFSR: EPPB Mask */
+
+#define SCB_ABFSR_AXIM_Pos                  3U                                            /*!< SCB ABFSR: AXIM Position*/
+#define SCB_ABFSR_AXIM_Msk                 (1UL << SCB_ABFSR_AXIM_Pos)                    /*!< SCB ABFSR: AXIM Mask */
+
+#define SCB_ABFSR_AHBP_Pos                  2U                                            /*!< SCB ABFSR: AHBP Position*/
+#define SCB_ABFSR_AHBP_Msk                 (1UL << SCB_ABFSR_AHBP_Pos)                    /*!< SCB ABFSR: AHBP Mask */
+
+#define SCB_ABFSR_DTCM_Pos                  1U                                            /*!< SCB ABFSR: DTCM Position*/
+#define SCB_ABFSR_DTCM_Msk                 (1UL << SCB_ABFSR_DTCM_Pos)                    /*!< SCB ABFSR: DTCM Mask */
+
+#define SCB_ABFSR_ITCM_Pos                  0U                                            /*!< SCB ABFSR: ITCM Position*/
+#define SCB_ABFSR_ITCM_Msk                 (1UL /*<< SCB_ABFSR_ITCM_Pos*/)                /*!< SCB ABFSR: ITCM Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+  \brief    Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+        uint32_t RESERVED0[1U];
+  __IM  uint32_t ICTR;                   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register */
+  __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */
+  __IOM uint32_t CPPWR;                  /*!< Offset: 0x00C (R/W)  Coprocessor Power Control  Register */
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos         0U                                         /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
+  \brief    Type definitions for the Instrumentation Trace Macrocell (ITM)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+  __OM  union
+  {
+    __OM  uint8_t    u8;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */
+    __OM  uint16_t   u16;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */
+    __OM  uint32_t   u32;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */
+  }  PORT [32U];                         /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers */
+        uint32_t RESERVED0[864U];
+  __IOM uint32_t TER;                    /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register */
+        uint32_t RESERVED1[15U];
+  __IOM uint32_t TPR;                    /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */
+        uint32_t RESERVED2[15U];
+  __IOM uint32_t TCR;                    /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */
+        uint32_t RESERVED3[29U];
+  __OM  uint32_t IWR;                    /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register */
+  __IM  uint32_t IRR;                    /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register */
+  __IOM uint32_t IMCR;                   /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register */
+        uint32_t RESERVED4[43U];
+  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register */
+  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register */
+        uint32_t RESERVED5[1U];
+  __IM  uint32_t DEVARCH;                /*!< Offset: 0xFBC (R/ )  ITM Device Architecture Register */
+        uint32_t RESERVED6[4U];
+  __IM  uint32_t PID4;                   /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
+  __IM  uint32_t PID5;                   /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
+  __IM  uint32_t PID6;                   /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
+  __IM  uint32_t PID7;                   /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
+  __IM  uint32_t PID0;                   /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
+  __IM  uint32_t PID1;                   /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
+  __IM  uint32_t PID2;                   /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
+  __IM  uint32_t PID3;                   /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
+  __IM  uint32_t CID0;                   /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
+  __IM  uint32_t CID1;                   /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
+  __IM  uint32_t CID2;                   /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
+  __IM  uint32_t CID3;                   /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
+} ITM_Type;
+
+/* ITM Stimulus Port Register Definitions */
+#define ITM_STIM_DISABLED_Pos               1U                                            /*!< ITM STIM: DISABLED Position */
+#define ITM_STIM_DISABLED_Msk              (0x1UL << ITM_STIM_DISABLED_Pos)               /*!< ITM STIM: DISABLED Mask */
+
+#define ITM_STIM_FIFOREADY_Pos              0U                                            /*!< ITM STIM: FIFOREADY Position */
+#define ITM_STIM_FIFOREADY_Msk             (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/)          /*!< ITM STIM: FIFOREADY Mask */
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos                0U                                            /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk               (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/)     /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos                   23U                                            /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TRACEBUSID_Pos             16U                                            /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TRACEBUSID_Msk             (0x7FUL << ITM_TCR_TRACEBUSID_Pos)             /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos                10U                                            /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPRESCALE_Pos              8U                                            /*!< ITM TCR: TSPRESCALE Position */
+#define ITM_TCR_TSPRESCALE_Msk             (3UL << ITM_TCR_TSPRESCALE_Pos)                /*!< ITM TCR: TSPRESCALE Mask */
+
+#define ITM_TCR_STALLENA_Pos                5U                                            /*!< ITM TCR: STALLENA Position */
+#define ITM_TCR_STALLENA_Msk               (1UL << ITM_TCR_STALLENA_Pos)                  /*!< ITM TCR: STALLENA Mask */
+
+#define ITM_TCR_SWOENA_Pos                  4U                                            /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos                  3U                                            /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos                 2U                                            /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos                   1U                                            /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos                  0U                                            /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos                0U                                            /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk               (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)              /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos                0U                                            /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk               (1UL /*<< ITM_IRR_ATREADYM_Pos*/)              /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos            0U                                            /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk           (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)          /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos                 2U                                            /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos                  1U                                            /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos                 0U                                            /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
+  \brief    Type definitions for the Data Watchpoint and Trace (DWT)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */
+  __IOM uint32_t CYCCNT;                 /*!< Offset: 0x004 (R/W)  Cycle Count Register */
+  __IOM uint32_t CPICNT;                 /*!< Offset: 0x008 (R/W)  CPI Count Register */
+  __IOM uint32_t EXCCNT;                 /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register */
+  __IOM uint32_t SLEEPCNT;               /*!< Offset: 0x010 (R/W)  Sleep Count Register */
+  __IOM uint32_t LSUCNT;                 /*!< Offset: 0x014 (R/W)  LSU Count Register */
+  __IOM uint32_t FOLDCNT;                /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register */
+  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */
+  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */
+        uint32_t RESERVED1[1U];
+  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */
+        uint32_t RESERVED2[1U];
+  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */
+        uint32_t RESERVED3[1U];
+  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */
+        uint32_t RESERVED4[1U];
+  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */
+        uint32_t RESERVED5[1U];
+  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */
+        uint32_t RESERVED6[1U];
+  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */
+        uint32_t RESERVED7[1U];
+  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */
+        uint32_t RESERVED8[1U];
+  __IOM uint32_t COMP4;                  /*!< Offset: 0x060 (R/W)  Comparator Register 4 */
+        uint32_t RESERVED9[1U];
+  __IOM uint32_t FUNCTION4;              /*!< Offset: 0x068 (R/W)  Function Register 4 */
+        uint32_t RESERVED10[1U];
+  __IOM uint32_t COMP5;                  /*!< Offset: 0x070 (R/W)  Comparator Register 5 */
+        uint32_t RESERVED11[1U];
+  __IOM uint32_t FUNCTION5;              /*!< Offset: 0x078 (R/W)  Function Register 5 */
+        uint32_t RESERVED12[1U];
+  __IOM uint32_t COMP6;                  /*!< Offset: 0x080 (R/W)  Comparator Register 6 */
+        uint32_t RESERVED13[1U];
+  __IOM uint32_t FUNCTION6;              /*!< Offset: 0x088 (R/W)  Function Register 6 */
+        uint32_t RESERVED14[1U];
+  __IOM uint32_t COMP7;                  /*!< Offset: 0x090 (R/W)  Comparator Register 7 */
+        uint32_t RESERVED15[1U];
+  __IOM uint32_t FUNCTION7;              /*!< Offset: 0x098 (R/W)  Function Register 7 */
+        uint32_t RESERVED16[1U];
+  __IOM uint32_t COMP8;                  /*!< Offset: 0x0A0 (R/W)  Comparator Register 8 */
+        uint32_t RESERVED17[1U];
+  __IOM uint32_t FUNCTION8;              /*!< Offset: 0x0A8 (R/W)  Function Register 8 */
+        uint32_t RESERVED18[1U];
+  __IOM uint32_t COMP9;                  /*!< Offset: 0x0B0 (R/W)  Comparator Register 9 */
+        uint32_t RESERVED19[1U];
+  __IOM uint32_t FUNCTION9;              /*!< Offset: 0x0B8 (R/W)  Function Register 9 */
+        uint32_t RESERVED20[1U];
+  __IOM uint32_t COMP10;                 /*!< Offset: 0x0C0 (R/W)  Comparator Register 10 */
+        uint32_t RESERVED21[1U];
+  __IOM uint32_t FUNCTION10;             /*!< Offset: 0x0C8 (R/W)  Function Register 10 */
+        uint32_t RESERVED22[1U];
+  __IOM uint32_t COMP11;                 /*!< Offset: 0x0D0 (R/W)  Comparator Register 11 */
+        uint32_t RESERVED23[1U];
+  __IOM uint32_t FUNCTION11;             /*!< Offset: 0x0D8 (R/W)  Function Register 11 */
+        uint32_t RESERVED24[1U];
+  __IOM uint32_t COMP12;                 /*!< Offset: 0x0E0 (R/W)  Comparator Register 12 */
+        uint32_t RESERVED25[1U];
+  __IOM uint32_t FUNCTION12;             /*!< Offset: 0x0E8 (R/W)  Function Register 12 */
+        uint32_t RESERVED26[1U];
+  __IOM uint32_t COMP13;                 /*!< Offset: 0x0F0 (R/W)  Comparator Register 13 */
+        uint32_t RESERVED27[1U];
+  __IOM uint32_t FUNCTION13;             /*!< Offset: 0x0F8 (R/W)  Function Register 13 */
+        uint32_t RESERVED28[1U];
+  __IOM uint32_t COMP14;                 /*!< Offset: 0x100 (R/W)  Comparator Register 14 */
+        uint32_t RESERVED29[1U];
+  __IOM uint32_t FUNCTION14;             /*!< Offset: 0x108 (R/W)  Function Register 14 */
+        uint32_t RESERVED30[1U];
+  __IOM uint32_t COMP15;                 /*!< Offset: 0x110 (R/W)  Comparator Register 15 */
+        uint32_t RESERVED31[1U];
+  __IOM uint32_t FUNCTION15;             /*!< Offset: 0x118 (R/W)  Function Register 15 */
+        uint32_t RESERVED32[934U];
+  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R  )  Lock Status Register */
+        uint32_t RESERVED33[1U];
+  __IM  uint32_t DEVARCH;                /*!< Offset: 0xFBC (R/ )  Device Architecture Register */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCDISS_Pos               23U                                         /*!< DWT CTRL: CYCDISS Position */
+#define DWT_CTRL_CYCDISS_Msk               (0x1UL << DWT_CTRL_CYCDISS_Pos)             /*!< DWT CTRL: CYCDISS Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos             22U                                         /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos            21U                                         /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos             20U                                         /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos           19U                                         /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos             18U                                         /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos             17U                                         /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos             16U                                         /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos            12U                                         /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos               10U                                         /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos                 9U                                         /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos               5U                                         /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos             1U                                         /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos              0U                                         /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos               0U                                         /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos               0U                                         /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos           0U                                         /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos               0U                                         /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos             0U                                         /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_ID_Pos                27U                                         /*!< DWT FUNCTION: ID Position */
+#define DWT_FUNCTION_ID_Msk                (0x1FUL << DWT_FUNCTION_ID_Pos)             /*!< DWT FUNCTION: ID Mask */
+
+#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_ACTION_Pos             4U                                         /*!< DWT FUNCTION: ACTION Position */
+#define DWT_FUNCTION_ACTION_Msk            (0x1UL << DWT_FUNCTION_ACTION_Pos)          /*!< DWT FUNCTION: ACTION Mask */
+
+#define DWT_FUNCTION_MATCH_Pos              0U                                         /*!< DWT FUNCTION: MATCH Position */
+#define DWT_FUNCTION_MATCH_Msk             (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/)       /*!< DWT FUNCTION: MATCH Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_TPI     Trace Port Interface (TPI)
+  \brief    Type definitions for the Trace Port Interface (TPI)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+  __IM  uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */
+  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
+        uint32_t RESERVED0[2U];
+  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
+        uint32_t RESERVED1[55U];
+  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
+        uint32_t RESERVED2[131U];
+  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
+  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
+  __IOM uint32_t PSCR;                   /*!< Offset: 0x308 (R/W)  Periodic Synchronization Control Register */
+        uint32_t RESERVED3[759U];
+  __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER Register */
+  __IM  uint32_t ITFTTD0;                /*!< Offset: 0xEEC (R/ )  Integration Test FIFO Test Data 0 Register */
+  __IOM uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/W)  Integration Test ATB Control Register 2 */
+        uint32_t RESERVED4[1U];
+  __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  Integration Test ATB Control Register 0 */
+  __IM  uint32_t ITFTTD1;                /*!< Offset: 0xEFC (R/ )  Integration Test FIFO Test Data 1 Register */
+  __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
+        uint32_t RESERVED5[39U];
+  __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */
+  __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
+        uint32_t RESERVED7[8U];
+  __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  Device Configuration Register */
+  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  Device Type Identifier Register */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_FOnMan_Pos                 6U                                         /*!< TPI FFCR: FOnMan Position */
+#define TPI_FFCR_FOnMan_Msk                (0x1UL << TPI_FFCR_FOnMan_Pos)              /*!< TPI FFCR: FOnMan Mask */
+
+#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration Test FIFO Test Data 0 Register Definitions */
+#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos    29U                                         /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */
+#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk    (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos)  /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */
+
+#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos  27U                                         /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */
+#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk  (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos    26U                                         /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */
+#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk    (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos)  /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos  24U                                         /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */
+#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk  (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_data2_Pos      16U                                         /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */
+#define TPI_ITFTTD0_ATB_IF1_data2_Msk      (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos)   /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_data1_Pos       8U                                         /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */
+#define TPI_ITFTTD0_ATB_IF1_data1_Msk      (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos)   /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_data0_Pos       0U                                          /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */
+#define TPI_ITFTTD0_ATB_IF1_data0_Msk      (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */
+
+/* TPI Integration Test ATB Control Register 2 Register Definitions */
+#define TPI_ITATBCTR2_AFVALID2S_Pos         1U                                         /*!< TPI ITATBCTR2: AFVALID2S Position */
+#define TPI_ITATBCTR2_AFVALID2S_Msk        (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos)      /*!< TPI ITATBCTR2: AFVALID2SS Mask */
+
+#define TPI_ITATBCTR2_AFVALID1S_Pos         1U                                         /*!< TPI ITATBCTR2: AFVALID1S Position */
+#define TPI_ITATBCTR2_AFVALID1S_Msk        (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos)      /*!< TPI ITATBCTR2: AFVALID1SS Mask */
+
+#define TPI_ITATBCTR2_ATREADY2S_Pos         0U                                         /*!< TPI ITATBCTR2: ATREADY2S Position */
+#define TPI_ITATBCTR2_ATREADY2S_Msk        (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/)  /*!< TPI ITATBCTR2: ATREADY2S Mask */
+
+#define TPI_ITATBCTR2_ATREADY1S_Pos         0U                                         /*!< TPI ITATBCTR2: ATREADY1S Position */
+#define TPI_ITATBCTR2_ATREADY1S_Msk        (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/)  /*!< TPI ITATBCTR2: ATREADY1S Mask */
+
+/* TPI Integration Test FIFO Test Data 1 Register Definitions */
+#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos    29U                                         /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */
+#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk    (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos)  /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */
+
+#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos  27U                                         /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */
+#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk  (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */
+
+#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos    26U                                         /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */
+#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk    (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos)  /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */
+
+#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos  24U                                         /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */
+#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk  (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */
+
+#define TPI_ITFTTD1_ATB_IF2_data2_Pos      16U                                         /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */
+#define TPI_ITFTTD1_ATB_IF2_data2_Msk      (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos)   /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */
+
+#define TPI_ITFTTD1_ATB_IF2_data1_Pos       8U                                         /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */
+#define TPI_ITFTTD1_ATB_IF2_data1_Msk      (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos)   /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */
+
+#define TPI_ITFTTD1_ATB_IF2_data0_Pos       0U                                          /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */
+#define TPI_ITFTTD1_ATB_IF2_data0_Msk      (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */
+
+/* TPI Integration Test ATB Control Register 0 Definitions */
+#define TPI_ITATBCTR0_AFVALID2S_Pos         1U                                         /*!< TPI ITATBCTR0: AFVALID2S Position */
+#define TPI_ITATBCTR0_AFVALID2S_Msk        (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos)      /*!< TPI ITATBCTR0: AFVALID2SS Mask */
+
+#define TPI_ITATBCTR0_AFVALID1S_Pos         1U                                         /*!< TPI ITATBCTR0: AFVALID1S Position */
+#define TPI_ITATBCTR0_AFVALID1S_Msk        (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos)      /*!< TPI ITATBCTR0: AFVALID1SS Mask */
+
+#define TPI_ITATBCTR0_ATREADY2S_Pos         0U                                         /*!< TPI ITATBCTR0: ATREADY2S Position */
+#define TPI_ITATBCTR0_ATREADY2S_Msk        (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/)  /*!< TPI ITATBCTR0: ATREADY2S Mask */
+
+#define TPI_ITATBCTR0_ATREADY1S_Pos         0U                                         /*!< TPI ITATBCTR0: ATREADY1S Position */
+#define TPI_ITATBCTR0_ATREADY1S_Msk        (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/)  /*!< TPI ITATBCTR0: ATREADY1S Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk                (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_FIFOSZ_Pos                6U                                         /*!< TPI DEVID: FIFOSZ Position */
+#define TPI_DEVID_FIFOSZ_Msk               (0x7UL << TPI_DEVID_FIFOSZ_Pos)             /*!< TPI DEVID: FIFOSZ Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk         (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos             4U                                         /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos           0U                                         /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+  \brief    Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region Number Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
+  __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  MPU Region Limit Address Register */
+  __IOM uint32_t RBAR_A1;                /*!< Offset: 0x014 (R/W)  MPU Region Base Address Register Alias 1 */
+  __IOM uint32_t RLAR_A1;                /*!< Offset: 0x018 (R/W)  MPU Region Limit Address Register Alias 1 */
+  __IOM uint32_t RBAR_A2;                /*!< Offset: 0x01C (R/W)  MPU Region Base Address Register Alias 2 */
+  __IOM uint32_t RLAR_A2;                /*!< Offset: 0x020 (R/W)  MPU Region Limit Address Register Alias 2 */
+  __IOM uint32_t RBAR_A3;                /*!< Offset: 0x024 (R/W)  MPU Region Base Address Register Alias 3 */
+  __IOM uint32_t RLAR_A3;                /*!< Offset: 0x028 (R/W)  MPU Region Limit Address Register Alias 3 */
+        uint32_t RESERVED0[1];
+  union {
+  __IOM uint32_t MAIR[2];
+  struct {
+  __IOM uint32_t MAIR0;                  /*!< Offset: 0x030 (R/W)  MPU Memory Attribute Indirection Register 0 */
+  __IOM uint32_t MAIR1;                  /*!< Offset: 0x034 (R/W)  MPU Memory Attribute Indirection Register 1 */
+  };
+  };
+} MPU_Type;
+
+#define MPU_TYPE_RALIASES                  4U
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_BASE_Pos                   5U                                            /*!< MPU RBAR: BASE Position */
+#define MPU_RBAR_BASE_Msk                  (0x7FFFFFFUL << MPU_RBAR_BASE_Pos)             /*!< MPU RBAR: BASE Mask */
+
+#define MPU_RBAR_SH_Pos                     3U                                            /*!< MPU RBAR: SH Position */
+#define MPU_RBAR_SH_Msk                    (0x3UL << MPU_RBAR_SH_Pos)                     /*!< MPU RBAR: SH Mask */
+
+#define MPU_RBAR_AP_Pos                     1U                                            /*!< MPU RBAR: AP Position */
+#define MPU_RBAR_AP_Msk                    (0x3UL << MPU_RBAR_AP_Pos)                     /*!< MPU RBAR: AP Mask */
+
+#define MPU_RBAR_XN_Pos                     0U                                            /*!< MPU RBAR: XN Position */
+#define MPU_RBAR_XN_Msk                    (01UL /*<< MPU_RBAR_XN_Pos*/)                  /*!< MPU RBAR: XN Mask */
+
+/* MPU Region Limit Address Register Definitions */
+#define MPU_RLAR_LIMIT_Pos                  5U                                            /*!< MPU RLAR: LIMIT Position */
+#define MPU_RLAR_LIMIT_Msk                 (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos)            /*!< MPU RLAR: LIMIT Mask */
+
+#define MPU_RLAR_AttrIndx_Pos               1U                                            /*!< MPU RLAR: AttrIndx Position */
+#define MPU_RLAR_AttrIndx_Msk              (0x7UL << MPU_RLAR_AttrIndx_Pos)               /*!< MPU RLAR: AttrIndx Mask */
+
+#define MPU_RLAR_EN_Pos                     0U                                            /*!< MPU RLAR: Region enable bit Position */
+#define MPU_RLAR_EN_Msk                    (1UL /*<< MPU_RLAR_EN_Pos*/)                   /*!< MPU RLAR: Region enable bit Disable Mask */
+
+/* MPU Memory Attribute Indirection Register 0 Definitions */
+#define MPU_MAIR0_Attr3_Pos                24U                                            /*!< MPU MAIR0: Attr3 Position */
+#define MPU_MAIR0_Attr3_Msk                (0xFFUL << MPU_MAIR0_Attr3_Pos)                /*!< MPU MAIR0: Attr3 Mask */
+
+#define MPU_MAIR0_Attr2_Pos                16U                                            /*!< MPU MAIR0: Attr2 Position */
+#define MPU_MAIR0_Attr2_Msk                (0xFFUL << MPU_MAIR0_Attr2_Pos)                /*!< MPU MAIR0: Attr2 Mask */
+
+#define MPU_MAIR0_Attr1_Pos                 8U                                            /*!< MPU MAIR0: Attr1 Position */
+#define MPU_MAIR0_Attr1_Msk                (0xFFUL << MPU_MAIR0_Attr1_Pos)                /*!< MPU MAIR0: Attr1 Mask */
+
+#define MPU_MAIR0_Attr0_Pos                 0U                                            /*!< MPU MAIR0: Attr0 Position */
+#define MPU_MAIR0_Attr0_Msk                (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/)            /*!< MPU MAIR0: Attr0 Mask */
+
+/* MPU Memory Attribute Indirection Register 1 Definitions */
+#define MPU_MAIR1_Attr7_Pos                24U                                            /*!< MPU MAIR1: Attr7 Position */
+#define MPU_MAIR1_Attr7_Msk                (0xFFUL << MPU_MAIR1_Attr7_Pos)                /*!< MPU MAIR1: Attr7 Mask */
+
+#define MPU_MAIR1_Attr6_Pos                16U                                            /*!< MPU MAIR1: Attr6 Position */
+#define MPU_MAIR1_Attr6_Msk                (0xFFUL << MPU_MAIR1_Attr6_Pos)                /*!< MPU MAIR1: Attr6 Mask */
+
+#define MPU_MAIR1_Attr5_Pos                 8U                                            /*!< MPU MAIR1: Attr5 Position */
+#define MPU_MAIR1_Attr5_Msk                (0xFFUL << MPU_MAIR1_Attr5_Pos)                /*!< MPU MAIR1: Attr5 Mask */
+
+#define MPU_MAIR1_Attr4_Pos                 0U                                            /*!< MPU MAIR1: Attr4 Position */
+#define MPU_MAIR1_Attr4_Msk                (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/)            /*!< MPU MAIR1: Attr4 Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SAU     Security Attribution Unit (SAU)
+  \brief    Type definitions for the Security Attribution Unit (SAU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Security Attribution Unit (SAU).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SAU Control Register */
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x004 (R/ )  SAU Type Register */
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  SAU Region Number Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  SAU Region Base Address Register */
+  __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  SAU Region Limit Address Register */
+#else
+        uint32_t RESERVED0[3];
+#endif
+  __IOM uint32_t SFSR;                   /*!< Offset: 0x014 (R/W)  Secure Fault Status Register */
+  __IOM uint32_t SFAR;                   /*!< Offset: 0x018 (R/W)  Secure Fault Address Register */
+} SAU_Type;
+
+/* SAU Control Register Definitions */
+#define SAU_CTRL_ALLNS_Pos                  1U                                            /*!< SAU CTRL: ALLNS Position */
+#define SAU_CTRL_ALLNS_Msk                 (1UL << SAU_CTRL_ALLNS_Pos)                    /*!< SAU CTRL: ALLNS Mask */
+
+#define SAU_CTRL_ENABLE_Pos                 0U                                            /*!< SAU CTRL: ENABLE Position */
+#define SAU_CTRL_ENABLE_Msk                (1UL /*<< SAU_CTRL_ENABLE_Pos*/)               /*!< SAU CTRL: ENABLE Mask */
+
+/* SAU Type Register Definitions */
+#define SAU_TYPE_SREGION_Pos                0U                                            /*!< SAU TYPE: SREGION Position */
+#define SAU_TYPE_SREGION_Msk               (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/)           /*!< SAU TYPE: SREGION Mask */
+
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+/* SAU Region Number Register Definitions */
+#define SAU_RNR_REGION_Pos                  0U                                            /*!< SAU RNR: REGION Position */
+#define SAU_RNR_REGION_Msk                 (0xFFUL /*<< SAU_RNR_REGION_Pos*/)             /*!< SAU RNR: REGION Mask */
+
+/* SAU Region Base Address Register Definitions */
+#define SAU_RBAR_BADDR_Pos                  5U                                            /*!< SAU RBAR: BADDR Position */
+#define SAU_RBAR_BADDR_Msk                 (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos)            /*!< SAU RBAR: BADDR Mask */
+
+/* SAU Region Limit Address Register Definitions */
+#define SAU_RLAR_LADDR_Pos                  5U                                            /*!< SAU RLAR: LADDR Position */
+#define SAU_RLAR_LADDR_Msk                 (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos)            /*!< SAU RLAR: LADDR Mask */
+
+#define SAU_RLAR_NSC_Pos                    1U                                            /*!< SAU RLAR: NSC Position */
+#define SAU_RLAR_NSC_Msk                   (1UL << SAU_RLAR_NSC_Pos)                      /*!< SAU RLAR: NSC Mask */
+
+#define SAU_RLAR_ENABLE_Pos                 0U                                            /*!< SAU RLAR: ENABLE Position */
+#define SAU_RLAR_ENABLE_Msk                (1UL /*<< SAU_RLAR_ENABLE_Pos*/)               /*!< SAU RLAR: ENABLE Mask */
+
+#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
+
+/* Secure Fault Status Register Definitions */
+#define SAU_SFSR_LSERR_Pos                  7U                                            /*!< SAU SFSR: LSERR Position */
+#define SAU_SFSR_LSERR_Msk                 (1UL << SAU_SFSR_LSERR_Pos)                    /*!< SAU SFSR: LSERR Mask */
+
+#define SAU_SFSR_SFARVALID_Pos              6U                                            /*!< SAU SFSR: SFARVALID Position */
+#define SAU_SFSR_SFARVALID_Msk             (1UL << SAU_SFSR_SFARVALID_Pos)                /*!< SAU SFSR: SFARVALID Mask */
+
+#define SAU_SFSR_LSPERR_Pos                 5U                                            /*!< SAU SFSR: LSPERR Position */
+#define SAU_SFSR_LSPERR_Msk                (1UL << SAU_SFSR_LSPERR_Pos)                   /*!< SAU SFSR: LSPERR Mask */
+
+#define SAU_SFSR_INVTRAN_Pos                4U                                            /*!< SAU SFSR: INVTRAN Position */
+#define SAU_SFSR_INVTRAN_Msk               (1UL << SAU_SFSR_INVTRAN_Pos)                  /*!< SAU SFSR: INVTRAN Mask */
+
+#define SAU_SFSR_AUVIOL_Pos                 3U                                            /*!< SAU SFSR: AUVIOL Position */
+#define SAU_SFSR_AUVIOL_Msk                (1UL << SAU_SFSR_AUVIOL_Pos)                   /*!< SAU SFSR: AUVIOL Mask */
+
+#define SAU_SFSR_INVER_Pos                  2U                                            /*!< SAU SFSR: INVER Position */
+#define SAU_SFSR_INVER_Msk                 (1UL << SAU_SFSR_INVER_Pos)                    /*!< SAU SFSR: INVER Mask */
+
+#define SAU_SFSR_INVIS_Pos                  1U                                            /*!< SAU SFSR: INVIS Position */
+#define SAU_SFSR_INVIS_Msk                 (1UL << SAU_SFSR_INVIS_Pos)                    /*!< SAU SFSR: INVIS Mask */
+
+#define SAU_SFSR_INVEP_Pos                  0U                                            /*!< SAU SFSR: INVEP Position */
+#define SAU_SFSR_INVEP_Msk                 (1UL /*<< SAU_SFSR_INVEP_Pos*/)                /*!< SAU SFSR: INVEP Mask */
+
+/*@} end of group CMSIS_SAU */
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_FPU     Floating Point Unit (FPU)
+  \brief    Type definitions for the Floating Point Unit (FPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Floating Point Unit (FPU).
+ */
+typedef struct
+{
+        uint32_t RESERVED0[1U];
+  __IOM uint32_t FPCCR;                  /*!< Offset: 0x004 (R/W)  Floating-Point Context Control Register */
+  __IOM uint32_t FPCAR;                  /*!< Offset: 0x008 (R/W)  Floating-Point Context Address Register */
+  __IOM uint32_t FPDSCR;                 /*!< Offset: 0x00C (R/W)  Floating-Point Default Status Control Register */
+  __IM  uint32_t MVFR0;                  /*!< Offset: 0x010 (R/ )  Media and FP Feature Register 0 */
+  __IM  uint32_t MVFR1;                  /*!< Offset: 0x014 (R/ )  Media and FP Feature Register 1 */
+} FPU_Type;
+
+/* Floating-Point Context Control Register Definitions */
+#define FPU_FPCCR_ASPEN_Pos                31U                                            /*!< FPCCR: ASPEN bit Position */
+#define FPU_FPCCR_ASPEN_Msk                (1UL << FPU_FPCCR_ASPEN_Pos)                   /*!< FPCCR: ASPEN bit Mask */
+
+#define FPU_FPCCR_LSPEN_Pos                30U                                            /*!< FPCCR: LSPEN Position */
+#define FPU_FPCCR_LSPEN_Msk                (1UL << FPU_FPCCR_LSPEN_Pos)                   /*!< FPCCR: LSPEN bit Mask */
+
+#define FPU_FPCCR_LSPENS_Pos               29U                                            /*!< FPCCR: LSPENS Position */
+#define FPU_FPCCR_LSPENS_Msk               (1UL << FPU_FPCCR_LSPENS_Pos)                  /*!< FPCCR: LSPENS bit Mask */
+
+#define FPU_FPCCR_CLRONRET_Pos             28U                                            /*!< FPCCR: CLRONRET Position */
+#define FPU_FPCCR_CLRONRET_Msk             (1UL << FPU_FPCCR_CLRONRET_Pos)                /*!< FPCCR: CLRONRET bit Mask */
+
+#define FPU_FPCCR_CLRONRETS_Pos            27U                                            /*!< FPCCR: CLRONRETS Position */
+#define FPU_FPCCR_CLRONRETS_Msk            (1UL << FPU_FPCCR_CLRONRETS_Pos)               /*!< FPCCR: CLRONRETS bit Mask */
+
+#define FPU_FPCCR_TS_Pos                   26U                                            /*!< FPCCR: TS Position */
+#define FPU_FPCCR_TS_Msk                   (1UL << FPU_FPCCR_TS_Pos)                      /*!< FPCCR: TS bit Mask */
+
+#define FPU_FPCCR_UFRDY_Pos                10U                                            /*!< FPCCR: UFRDY Position */
+#define FPU_FPCCR_UFRDY_Msk                (1UL << FPU_FPCCR_UFRDY_Pos)                   /*!< FPCCR: UFRDY bit Mask */
+
+#define FPU_FPCCR_SPLIMVIOL_Pos             9U                                            /*!< FPCCR: SPLIMVIOL Position */
+#define FPU_FPCCR_SPLIMVIOL_Msk            (1UL << FPU_FPCCR_SPLIMVIOL_Pos)               /*!< FPCCR: SPLIMVIOL bit Mask */
+
+#define FPU_FPCCR_MONRDY_Pos                8U                                            /*!< FPCCR: MONRDY Position */
+#define FPU_FPCCR_MONRDY_Msk               (1UL << FPU_FPCCR_MONRDY_Pos)                  /*!< FPCCR: MONRDY bit Mask */
+
+#define FPU_FPCCR_SFRDY_Pos                 7U                                            /*!< FPCCR: SFRDY Position */
+#define FPU_FPCCR_SFRDY_Msk                (1UL << FPU_FPCCR_SFRDY_Pos)                   /*!< FPCCR: SFRDY bit Mask */
+
+#define FPU_FPCCR_BFRDY_Pos                 6U                                            /*!< FPCCR: BFRDY Position */
+#define FPU_FPCCR_BFRDY_Msk                (1UL << FPU_FPCCR_BFRDY_Pos)                   /*!< FPCCR: BFRDY bit Mask */
+
+#define FPU_FPCCR_MMRDY_Pos                 5U                                            /*!< FPCCR: MMRDY Position */
+#define FPU_FPCCR_MMRDY_Msk                (1UL << FPU_FPCCR_MMRDY_Pos)                   /*!< FPCCR: MMRDY bit Mask */
+
+#define FPU_FPCCR_HFRDY_Pos                 4U                                            /*!< FPCCR: HFRDY Position */
+#define FPU_FPCCR_HFRDY_Msk                (1UL << FPU_FPCCR_HFRDY_Pos)                   /*!< FPCCR: HFRDY bit Mask */
+
+#define FPU_FPCCR_THREAD_Pos                3U                                            /*!< FPCCR: processor mode bit Position */
+#define FPU_FPCCR_THREAD_Msk               (1UL << FPU_FPCCR_THREAD_Pos)                  /*!< FPCCR: processor mode active bit Mask */
+
+#define FPU_FPCCR_S_Pos                     2U                                            /*!< FPCCR: Security status of the FP context bit Position */
+#define FPU_FPCCR_S_Msk                    (1UL << FPU_FPCCR_S_Pos)                       /*!< FPCCR: Security status of the FP context bit Mask */
+
+#define FPU_FPCCR_USER_Pos                  1U                                            /*!< FPCCR: privilege level bit Position */
+#define FPU_FPCCR_USER_Msk                 (1UL << FPU_FPCCR_USER_Pos)                    /*!< FPCCR: privilege level bit Mask */
+
+#define FPU_FPCCR_LSPACT_Pos                0U                                            /*!< FPCCR: Lazy state preservation active bit Position */
+#define FPU_FPCCR_LSPACT_Msk               (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)              /*!< FPCCR: Lazy state preservation active bit Mask */
+
+/* Floating-Point Context Address Register Definitions */
+#define FPU_FPCAR_ADDRESS_Pos               3U                                            /*!< FPCAR: ADDRESS bit Position */
+#define FPU_FPCAR_ADDRESS_Msk              (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)        /*!< FPCAR: ADDRESS bit Mask */
+
+/* Floating-Point Default Status Control Register Definitions */
+#define FPU_FPDSCR_AHP_Pos                 26U                                            /*!< FPDSCR: AHP bit Position */
+#define FPU_FPDSCR_AHP_Msk                 (1UL << FPU_FPDSCR_AHP_Pos)                    /*!< FPDSCR: AHP bit Mask */
+
+#define FPU_FPDSCR_DN_Pos                  25U                                            /*!< FPDSCR: DN bit Position */
+#define FPU_FPDSCR_DN_Msk                  (1UL << FPU_FPDSCR_DN_Pos)                     /*!< FPDSCR: DN bit Mask */
+
+#define FPU_FPDSCR_FZ_Pos                  24U                                            /*!< FPDSCR: FZ bit Position */
+#define FPU_FPDSCR_FZ_Msk                  (1UL << FPU_FPDSCR_FZ_Pos)                     /*!< FPDSCR: FZ bit Mask */
+
+#define FPU_FPDSCR_RMode_Pos               22U                                            /*!< FPDSCR: RMode bit Position */
+#define FPU_FPDSCR_RMode_Msk               (3UL << FPU_FPDSCR_RMode_Pos)                  /*!< FPDSCR: RMode bit Mask */
+
+/* Media and FP Feature Register 0 Definitions */
+#define FPU_MVFR0_FP_rounding_modes_Pos    28U                                            /*!< MVFR0: FP rounding modes bits Position */
+#define FPU_MVFR0_FP_rounding_modes_Msk    (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)     /*!< MVFR0: FP rounding modes bits Mask */
+
+#define FPU_MVFR0_Short_vectors_Pos        24U                                            /*!< MVFR0: Short vectors bits Position */
+#define FPU_MVFR0_Short_vectors_Msk        (0xFUL << FPU_MVFR0_Short_vectors_Pos)         /*!< MVFR0: Short vectors bits Mask */
+
+#define FPU_MVFR0_Square_root_Pos          20U                                            /*!< MVFR0: Square root bits Position */
+#define FPU_MVFR0_Square_root_Msk          (0xFUL << FPU_MVFR0_Square_root_Pos)           /*!< MVFR0: Square root bits Mask */
+
+#define FPU_MVFR0_Divide_Pos               16U                                            /*!< MVFR0: Divide bits Position */
+#define FPU_MVFR0_Divide_Msk               (0xFUL << FPU_MVFR0_Divide_Pos)                /*!< MVFR0: Divide bits Mask */
+
+#define FPU_MVFR0_FP_excep_trapping_Pos    12U                                            /*!< MVFR0: FP exception trapping bits Position */
+#define FPU_MVFR0_FP_excep_trapping_Msk    (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)     /*!< MVFR0: FP exception trapping bits Mask */
+
+#define FPU_MVFR0_Double_precision_Pos      8U                                            /*!< MVFR0: Double-precision bits Position */
+#define FPU_MVFR0_Double_precision_Msk     (0xFUL << FPU_MVFR0_Double_precision_Pos)      /*!< MVFR0: Double-precision bits Mask */
+
+#define FPU_MVFR0_Single_precision_Pos      4U                                            /*!< MVFR0: Single-precision bits Position */
+#define FPU_MVFR0_Single_precision_Msk     (0xFUL << FPU_MVFR0_Single_precision_Pos)      /*!< MVFR0: Single-precision bits Mask */
+
+#define FPU_MVFR0_A_SIMD_registers_Pos      0U                                            /*!< MVFR0: A_SIMD registers bits Position */
+#define FPU_MVFR0_A_SIMD_registers_Msk     (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)  /*!< MVFR0: A_SIMD registers bits Mask */
+
+/* Media and FP Feature Register 1 Definitions */
+#define FPU_MVFR1_FP_fused_MAC_Pos         28U                                            /*!< MVFR1: FP fused MAC bits Position */
+#define FPU_MVFR1_FP_fused_MAC_Msk         (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)          /*!< MVFR1: FP fused MAC bits Mask */
+
+#define FPU_MVFR1_FP_HPFP_Pos              24U                                            /*!< MVFR1: FP HPFP bits Position */
+#define FPU_MVFR1_FP_HPFP_Msk              (0xFUL << FPU_MVFR1_FP_HPFP_Pos)               /*!< MVFR1: FP HPFP bits Mask */
+
+#define FPU_MVFR1_D_NaN_mode_Pos            4U                                            /*!< MVFR1: D_NaN mode bits Position */
+#define FPU_MVFR1_D_NaN_mode_Msk           (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)            /*!< MVFR1: D_NaN mode bits Mask */
+
+#define FPU_MVFR1_FtZ_mode_Pos              0U                                            /*!< MVFR1: FtZ mode bits Position */
+#define FPU_MVFR1_FtZ_mode_Msk             (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)          /*!< MVFR1: FtZ mode bits Mask */
+
+/*@} end of group CMSIS_FPU */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    Type definitions for the Core Debug Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */
+  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */
+  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */
+  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
+        uint32_t RESERVED4[1U];
+  __IOM uint32_t DAUTHCTRL;              /*!< Offset: 0x014 (R/W)  Debug Authentication Control Register */
+  __IOM uint32_t DSCSR;                  /*!< Offset: 0x018 (R/W)  Debug Security Control and Status Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESTART_ST_Pos   26U                                            /*!< CoreDebug DHCSR: S_RESTART_ST Position */
+#define CoreDebug_DHCSR_S_RESTART_ST_Msk   (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)      /*!< CoreDebug DHCSR: S_RESTART_ST Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5U                                            /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos         24U                                            /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos        19U                                            /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos       18U                                            /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos       17U                                            /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos         16U                                            /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos       9U                                            /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos       8U                                            /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos      7U                                            /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos       6U                                            /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5U                                            /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos        4U                                            /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/* Debug Authentication Control Register Definitions */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos  3U                                            /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)    /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */
+
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos  2U                                            /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)    /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */
+
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos   1U                                            /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk  (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)     /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */
+
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos   0U                                            /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk  (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */
+
+/* Debug Security Control and Status Register Definitions */
+#define CoreDebug_DSCSR_CDS_Pos            16U                                            /*!< CoreDebug DSCSR: CDS Position */
+#define CoreDebug_DSCSR_CDS_Msk            (1UL << CoreDebug_DSCSR_CDS_Pos)               /*!< CoreDebug DSCSR: CDS Mask */
+
+#define CoreDebug_DSCSR_SBRSEL_Pos          1U                                            /*!< CoreDebug DSCSR: SBRSEL Position */
+#define CoreDebug_DSCSR_SBRSEL_Msk         (1UL << CoreDebug_DSCSR_SBRSEL_Pos)            /*!< CoreDebug DSCSR: SBRSEL Mask */
+
+#define CoreDebug_DSCSR_SBRSELEN_Pos        0U                                            /*!< CoreDebug DSCSR: SBRSELEN Position */
+#define CoreDebug_DSCSR_SBRSELEN_Msk       (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/)      /*!< CoreDebug DSCSR: SBRSELEN Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Core Hardware */
+  #define SCS_BASE            (0xE000E000UL)                             /*!< System Control Space Base Address */
+  #define ITM_BASE            (0xE0000000UL)                             /*!< ITM Base Address */
+  #define DWT_BASE            (0xE0001000UL)                             /*!< DWT Base Address */
+  #define TPI_BASE            (0xE0040000UL)                             /*!< TPI Base Address */
+  #define CoreDebug_BASE      (0xE000EDF0UL)                             /*!< Core Debug Base Address */
+  #define SysTick_BASE        (SCS_BASE +  0x0010UL)                     /*!< SysTick Base Address */
+  #define NVIC_BASE           (SCS_BASE +  0x0100UL)                     /*!< NVIC Base Address */
+  #define SCB_BASE            (SCS_BASE +  0x0D00UL)                     /*!< System Control Block Base Address */
+
+  #define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE         ) /*!< System control Register not in SCB */
+  #define SCB                 ((SCB_Type       *)     SCB_BASE         ) /*!< SCB configuration struct */
+  #define SysTick             ((SysTick_Type   *)     SysTick_BASE     ) /*!< SysTick configuration struct */
+  #define NVIC                ((NVIC_Type      *)     NVIC_BASE        ) /*!< NVIC configuration struct */
+  #define ITM                 ((ITM_Type       *)     ITM_BASE         ) /*!< ITM configuration struct */
+  #define DWT                 ((DWT_Type       *)     DWT_BASE         ) /*!< DWT configuration struct */
+  #define TPI                 ((TPI_Type       *)     TPI_BASE         ) /*!< TPI configuration struct */
+  #define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE   ) /*!< Core Debug configuration struct */
+
+  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+    #define MPU_BASE          (SCS_BASE +  0x0D90UL)                     /*!< Memory Protection Unit */
+    #define MPU               ((MPU_Type       *)     MPU_BASE         ) /*!< Memory Protection Unit */
+  #endif
+
+  #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+    #define SAU_BASE          (SCS_BASE +  0x0DD0UL)                     /*!< Security Attribution Unit */
+    #define SAU               ((SAU_Type       *)     SAU_BASE         ) /*!< Security Attribution Unit */
+  #endif
+
+  #define FPU_BASE            (SCS_BASE +  0x0F30UL)                     /*!< Floating Point Unit */
+  #define FPU                 ((FPU_Type       *)     FPU_BASE         ) /*!< Floating Point Unit */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+  #define SCS_BASE_NS         (0xE002E000UL)                             /*!< System Control Space Base Address (non-secure address space) */
+  #define CoreDebug_BASE_NS   (0xE002EDF0UL)                             /*!< Core Debug Base Address           (non-secure address space) */
+  #define SysTick_BASE_NS     (SCS_BASE_NS +  0x0010UL)                  /*!< SysTick Base Address              (non-secure address space) */
+  #define NVIC_BASE_NS        (SCS_BASE_NS +  0x0100UL)                  /*!< NVIC Base Address                 (non-secure address space) */
+  #define SCB_BASE_NS         (SCS_BASE_NS +  0x0D00UL)                  /*!< System Control Block Base Address (non-secure address space) */
+
+  #define SCnSCB_NS           ((SCnSCB_Type    *)     SCS_BASE_NS      ) /*!< System control Register not in SCB(non-secure address space) */
+  #define SCB_NS              ((SCB_Type       *)     SCB_BASE_NS      ) /*!< SCB configuration struct          (non-secure address space) */
+  #define SysTick_NS          ((SysTick_Type   *)     SysTick_BASE_NS  ) /*!< SysTick configuration struct      (non-secure address space) */
+  #define NVIC_NS             ((NVIC_Type      *)     NVIC_BASE_NS     ) /*!< NVIC configuration struct         (non-secure address space) */
+  #define CoreDebug_NS        ((CoreDebug_Type *)     CoreDebug_BASE_NS) /*!< Core Debug configuration struct   (non-secure address space) */
+
+  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+    #define MPU_BASE_NS       (SCS_BASE_NS +  0x0D90UL)                  /*!< Memory Protection Unit            (non-secure address space) */
+    #define MPU_NS            ((MPU_Type       *)     MPU_BASE_NS      ) /*!< Memory Protection Unit            (non-secure address space) */
+  #endif
+
+  #define FPU_BASE_NS         (SCS_BASE_NS +  0x0F30UL)                  /*!< Floating Point Unit               (non-secure address space) */
+  #define FPU_NS              ((FPU_Type       *)     FPU_BASE_NS      ) /*!< Floating Point Unit               (non-secure address space) */
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Debug Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+  #endif
+  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
+  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
+  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
+  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
+  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
+  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+  #define NVIC_GetActive              __NVIC_GetActive
+  #define NVIC_SetPriority            __NVIC_SetPriority
+  #define NVIC_GetPriority            __NVIC_GetPriority
+  #define NVIC_SystemReset            __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+  #endif
+  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetVector              __NVIC_SetVector
+  #define NVIC_GetVector              __NVIC_GetVector
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET          16
+
+
+/* Special LR values for Secure/Non-Secure call handling and exception handling                                               */
+
+/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS                   */ 
+#define FNC_RETURN                 (0xFEFFFFFFUL)     /* bit [0] ignored when processing a branch                             */
+
+/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */
+#define EXC_RETURN_PREFIX          (0xFF000000UL)     /* bits [31:24] set to indicate an EXC_RETURN value                     */
+#define EXC_RETURN_S               (0x00000040UL)     /* bit [6] stack used to push registers: 0=Non-secure 1=Secure          */
+#define EXC_RETURN_DCRS            (0x00000020UL)     /* bit [5] stacking rules for called registers: 0=skipped 1=saved       */
+#define EXC_RETURN_FTYPE           (0x00000010UL)     /* bit [4] allocate stack for floating-point context: 0=done 1=skipped  */
+#define EXC_RETURN_MODE            (0x00000008UL)     /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode      */
+#define EXC_RETURN_SPSEL           (0x00000002UL)     /* bit [1] stack pointer used to restore context: 0=MSP 1=PSP           */
+#define EXC_RETURN_ES              (0x00000001UL)     /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */
+
+/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking                            */
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)  /* Value for processors with floating-point extension:                  */
+#define EXC_INTEGRITY_SIGNATURE     (0xFEFA125AUL)     /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE                   */
+#else 
+#define EXC_INTEGRITY_SIGNATURE     (0xFEFA125BUL)     /* Value for processors without floating-point extension                */
+#endif
+
+
+/**
+  \brief   Set Priority Grouping
+  \details Sets the priority grouping field using the required unlock sequence.
+           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+           Only values from 0..7 are used.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]      PriorityGroup  Priority grouping field.
+ */
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+  uint32_t reg_value;
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
+
+  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
+  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */
+  reg_value  =  (reg_value                                   |
+                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                (PriorityGroupTmp << 8U)                      );              /* Insert write key and priority group */
+  SCB->AIRCR =  reg_value;
+}
+
+
+/**
+  \brief   Get Priority Grouping
+  \details Reads the priority grouping field from the NVIC Interrupt Controller.
+  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
+{
+  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+  \brief   Enable Interrupt
+  \details Enables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt
+  \details Disables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+    __DSB();
+    __ISB();
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Active Interrupt
+  \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not active.
+  \return             1  Interrupt status is active.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   Get Interrupt Target State
+  \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  if interrupt is assigned to Secure
+  \return             1  if interrupt is assigned to Non Secure
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Target State
+  \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  if interrupt is assigned to Secure
+                      1  if interrupt is assigned to Non Secure
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |=  ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
+    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Clear Interrupt Target State
+  \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  if interrupt is assigned to Secure
+                      1  if interrupt is assigned to Non Secure
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
+    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->IPR[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+  else
+  {
+    SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+
+
+/**
+  \brief   Encode Priority
+  \details Encodes the priority for an interrupt with the given priority group,
+           preemptive priority value, and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]     PriorityGroup  Used priority group.
+  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+  \param [in]       SubPriority  Subpriority value (starting from 0).
+  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  return (
+           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
+         );
+}
+
+
+/**
+  \brief   Decode Priority
+  \details Decodes an interrupt priority value with a given priority group to
+           preemptive priority value and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+  \param [in]     PriorityGroup  Used priority group.
+  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+  \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
+}
+
+
+/**
+  \brief   Set Interrupt Vector
+  \details Sets an interrupt vector in SRAM based interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+           VTOR must been relocated to SRAM before.
+  \param [in]   IRQn      Interrupt number
+  \param [in]   vector    Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+  \brief   Get Interrupt Vector
+  \details Reads an interrupt vector from interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn      Interrupt number.
+  \return                 Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+  __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
+                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */
+  __DSB();                                                          /* Ensure completion of memory access */
+
+  for(;;)                                                           /* wait until reset */
+  {
+    __NOP();
+  }
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   Set Priority Grouping (non-secure)
+  \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence.
+           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+           Only values from 0..7 are used.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]      PriorityGroup  Priority grouping field.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup)
+{
+  uint32_t reg_value;
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
+
+  reg_value  =  SCB_NS->AIRCR;                                                /* read old register configuration    */
+  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */
+  reg_value  =  (reg_value                                   |
+                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos)  );              /* Insert write key and priority group */
+  SCB_NS->AIRCR =  reg_value;
+}
+
+
+/**
+  \brief   Get Priority Grouping (non-secure)
+  \details Reads the priority grouping field from the non-secure NVIC when in secure state.
+  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void)
+{
+  return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+  \brief   Enable Interrupt (non-secure)
+  \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status (non-secure)
+  \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt (non-secure)
+  \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt (non-secure)
+  \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt (non-secure)
+  \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt (non-secure)
+  \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Active Interrupt (non-secure)
+  \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not active.
+  \return             1  Interrupt status is active.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Priority (non-secure)
+  \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every non-secure processor exception.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->IPR[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+  else
+  {
+    SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority (non-secure)
+  \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+#endif /*  defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+/* ##########################  MPU functions  #################################### */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+
+#include "mpu_armv8.h"
+
+#endif
+
+/* ##########################  FPU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions
+  \brief    Function that provides FPU type.
+  @{
+ */
+
+/**
+  \brief   get FPU type
+  \details returns the FPU type
+  \returns
+   - \b  0: No FPU
+   - \b  1: Single precision FPU
+   - \b  2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+  uint32_t mvfr0;
+
+  mvfr0 = FPU->MVFR0;
+  if      ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U)
+  {
+    return 2U;           /* Double + Single precision FPU */
+  }
+  else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)
+  {
+    return 1U;           /* Single precision FPU */
+  }
+  else
+  {
+    return 0U;           /* No FPU */
+  }
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ##########################   SAU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SAUFunctions SAU Functions
+  \brief    Functions that configure the SAU.
+  @{
+ */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+
+/**
+  \brief   Enable SAU
+  \details Enables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Enable(void)
+{
+    SAU->CTRL |=  (SAU_CTRL_ENABLE_Msk);
+}
+
+
+
+/**
+  \brief   Disable SAU
+  \details Disables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Disable(void)
+{
+    SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
+}
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_SAUFunctions */
+
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                   /* Reload value impossible */
+  }
+
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                     /* Function successful */
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   System Tick Configuration (non-secure)
+  \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                         /* Reload value impossible */
+  }
+
+  SysTick_NS->LOAD  = (uint32_t)(ticks - 1UL);                            /* set reload register */
+  TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick_NS->VAL   = 0UL;                                                /* Load the SysTick Counter Value */
+  SysTick_NS->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                      SysTick_CTRL_TICKINT_Msk   |
+                      SysTick_CTRL_ENABLE_Msk;                            /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                           /* Function successful */
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_core_DebugFunctions ITM Functions
+  \brief    Functions that access the ITM debug interface.
+  @{
+ */
+
+extern volatile int32_t ITM_RxBuffer;                              /*!< External variable to receive characters. */
+#define                 ITM_RXBUFFER_EMPTY  ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/**
+  \brief   ITM Send Character
+  \details Transmits a character via the ITM channel 0, and
+           \li Just returns when no debugger is connected that has booked the output.
+           \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+  \param [in]     ch  Character to transmit.
+  \returns            Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */
+      ((ITM->TER & 1UL               ) != 0UL)   )     /* ITM Port #0 enabled */
+  {
+    while (ITM->PORT[0U].u32 == 0UL)
+    {
+      __NOP();
+    }
+    ITM->PORT[0U].u8 = (uint8_t)ch;
+  }
+  return (ch);
+}
+
+
+/**
+  \brief   ITM Receive Character
+  \details Inputs a character via the external variable \ref ITM_RxBuffer.
+  \return             Received character.
+  \return         -1  No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)
+{
+  int32_t ch = -1;                           /* no character available */
+
+  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
+  {
+    ch = ITM_RxBuffer;
+    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
+  }
+
+  return (ch);
+}
+
+
+/**
+  \brief   ITM Check Character
+  \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+  \return          0  No character available.
+  \return          1  Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void)
+{
+
+  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
+  {
+    return (0);                              /* no character available */
+  }
+  else
+  {
+    return (1);                              /*    character available */
+  }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM33_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/Drivers/CMSIS/Include/core_cm4.h b/Drivers/CMSIS/Include/core_cm4.h
new file mode 100644
index 0000000..308b868
--- /dev/null
+++ b/Drivers/CMSIS/Include/core_cm4.h
@@ -0,0 +1,2129 @@
+/**************************************************************************//**
+ * @file     core_cm4.h
+ * @brief    CMSIS Cortex-M4 Core Peripheral Access Layer Header File
+ * @version  V5.0.8
+ * @date     04. June 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM4_H_GENERIC
+#define __CORE_CM4_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup Cortex_M4
+  @{
+ */
+
+#include "cmsis_version.h"
+
+/* CMSIS CM4 definitions */
+#define __CM4_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)              /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __CM4_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)               /*!< \deprecated [15:0]  CMSIS HAL sub version */
+#define __CM4_CMSIS_VERSION       ((__CM4_CMSIS_VERSION_MAIN << 16U) | \
+                                    __CM4_CMSIS_VERSION_SUB           )  /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M                (4U)                                   /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
+*/
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #if defined __ARM_PCS_VFP
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __TI_ARM__ )
+  #if defined __TI_VFP_SUPPORT__
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __CSMC__ )
+  #if ( __CSMC__ & 0x400U)
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#endif
+
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM4_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM4_H_DEPENDANT
+#define __CORE_CM4_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM4_REV
+    #define __CM4_REV               0x0000U
+    #warning "__CM4_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __FPU_PRESENT
+    #define __FPU_PRESENT             0U
+    #warning "__FPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0U
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          3U
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0U
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M4 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core Debug Register
+  - Core MPU Register
+  - Core FPU Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */
+    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+#define APSR_Q_Pos                         27U                                            /*!< APSR: Q Position */
+#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */
+
+#define APSR_GE_Pos                        16U                                            /*!< APSR: GE Position */
+#define APSR_GE_Msk                        (0xFUL << APSR_GE_Pos)                         /*!< APSR: GE Mask */
+
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:1;               /*!< bit:      9  Reserved */
+    uint32_t ICI_IT_1:6;                 /*!< bit: 10..15  ICI/IT part 1 */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */
+    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit */
+    uint32_t ICI_IT_2:2;                 /*!< bit: 25..26  ICI/IT part 2 */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos                         27U                                            /*!< xPSR: Q Position */
+#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */
+
+#define xPSR_ICI_IT_2_Pos                  25U                                            /*!< xPSR: ICI/IT part 2 Position */
+#define xPSR_ICI_IT_2_Msk                  (3UL << xPSR_ICI_IT_2_Pos)                     /*!< xPSR: ICI/IT part 2 Mask */
+
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_GE_Pos                        16U                                            /*!< xPSR: GE Position */
+#define xPSR_GE_Msk                        (0xFUL << xPSR_GE_Pos)                         /*!< xPSR: GE Mask */
+
+#define xPSR_ICI_IT_1_Pos                  10U                                            /*!< xPSR: ICI/IT part 1 Position */
+#define xPSR_ICI_IT_1_Msk                  (0x3FUL << xPSR_ICI_IT_1_Pos)                  /*!< xPSR: ICI/IT part 1 Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */
+    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag */
+    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_FPCA_Pos                    2U                                            /*!< CONTROL: FPCA Position */
+#define CONTROL_FPCA_Msk                   (1UL << CONTROL_FPCA_Pos)                      /*!< CONTROL: FPCA Mask */
+
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IOM uint32_t ISER[8U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+        uint32_t RESERVED0[24U];
+  __IOM uint32_t ICER[8U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+        uint32_t RSERVED1[24U];
+  __IOM uint32_t ISPR[8U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+        uint32_t RESERVED2[24U];
+  __IOM uint32_t ICPR[8U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+        uint32_t RESERVED3[24U];
+  __IOM uint32_t IABR[8U];               /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */
+        uint32_t RESERVED4[56U];
+  __IOM uint8_t  IP[240U];               /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
+        uint32_t RESERVED5[644U];
+  __OM  uint32_t STIR;                   /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register */
+}  NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos                 0U                                         /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
+  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+  __IOM uint8_t  SHP[12U];               /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
+  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+  __IOM uint32_t CFSR;                   /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register */
+  __IOM uint32_t HFSR;                   /*!< Offset: 0x02C (R/W)  HardFault Status Register */
+  __IOM uint32_t DFSR;                   /*!< Offset: 0x030 (R/W)  Debug Fault Status Register */
+  __IOM uint32_t MMFAR;                  /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register */
+  __IOM uint32_t BFAR;                   /*!< Offset: 0x038 (R/W)  BusFault Address Register */
+  __IOM uint32_t AFSR;                   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register */
+  __IM  uint32_t PFR[2U];                /*!< Offset: 0x040 (R/ )  Processor Feature Register */
+  __IM  uint32_t DFR;                    /*!< Offset: 0x048 (R/ )  Debug Feature Register */
+  __IM  uint32_t ADR;                    /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */
+  __IM  uint32_t MMFR[4U];               /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */
+  __IM  uint32_t ISAR[5U];               /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register */
+        uint32_t RESERVED0[5U];
+  __IOM uint32_t CPACR;                  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos              8U                                            /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos             0U                                            /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk            (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)           /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos          0U                                            /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk         (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)        /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos          18U                                            /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos          17U                                            /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos          16U                                            /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos       14U                                            /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos       13U                                            /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos       12U                                            /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos            8U                                            /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos           3U                                            /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos           1U                                            /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos           0U                                            /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos            16U                                            /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos             8U                                            /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos             0U                                            /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_MMARVALID_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 7U)               /*!< SCB CFSR (MMFSR): MMARVALID Position */
+#define SCB_CFSR_MMARVALID_Msk             (1UL << SCB_CFSR_MMARVALID_Pos)                /*!< SCB CFSR (MMFSR): MMARVALID Mask */
+
+#define SCB_CFSR_MLSPERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 5U)               /*!< SCB CFSR (MMFSR): MLSPERR Position */
+#define SCB_CFSR_MLSPERR_Msk               (1UL << SCB_CFSR_MLSPERR_Pos)                  /*!< SCB CFSR (MMFSR): MLSPERR Mask */
+
+#define SCB_CFSR_MSTKERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 4U)               /*!< SCB CFSR (MMFSR): MSTKERR Position */
+#define SCB_CFSR_MSTKERR_Msk               (1UL << SCB_CFSR_MSTKERR_Pos)                  /*!< SCB CFSR (MMFSR): MSTKERR Mask */
+
+#define SCB_CFSR_MUNSTKERR_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 3U)               /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
+#define SCB_CFSR_MUNSTKERR_Msk             (1UL << SCB_CFSR_MUNSTKERR_Pos)                /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
+
+#define SCB_CFSR_DACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 1U)               /*!< SCB CFSR (MMFSR): DACCVIOL Position */
+#define SCB_CFSR_DACCVIOL_Msk              (1UL << SCB_CFSR_DACCVIOL_Pos)                 /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
+
+#define SCB_CFSR_IACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 0U)               /*!< SCB CFSR (MMFSR): IACCVIOL Position */
+#define SCB_CFSR_IACCVIOL_Msk              (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)             /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
+
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_BFARVALID_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 7U)                  /*!< SCB CFSR (BFSR): BFARVALID Position */
+#define SCB_CFSR_BFARVALID_Msk            (1UL << SCB_CFSR_BFARVALID_Pos)                 /*!< SCB CFSR (BFSR): BFARVALID Mask */
+
+#define SCB_CFSR_LSPERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 5U)                  /*!< SCB CFSR (BFSR): LSPERR Position */
+#define SCB_CFSR_LSPERR_Msk               (1UL << SCB_CFSR_LSPERR_Pos)                    /*!< SCB CFSR (BFSR): LSPERR Mask */
+
+#define SCB_CFSR_STKERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 4U)                  /*!< SCB CFSR (BFSR): STKERR Position */
+#define SCB_CFSR_STKERR_Msk               (1UL << SCB_CFSR_STKERR_Pos)                    /*!< SCB CFSR (BFSR): STKERR Mask */
+
+#define SCB_CFSR_UNSTKERR_Pos             (SCB_CFSR_BUSFAULTSR_Pos + 3U)                  /*!< SCB CFSR (BFSR): UNSTKERR Position */
+#define SCB_CFSR_UNSTKERR_Msk             (1UL << SCB_CFSR_UNSTKERR_Pos)                  /*!< SCB CFSR (BFSR): UNSTKERR Mask */
+
+#define SCB_CFSR_IMPRECISERR_Pos          (SCB_CFSR_BUSFAULTSR_Pos + 2U)                  /*!< SCB CFSR (BFSR): IMPRECISERR Position */
+#define SCB_CFSR_IMPRECISERR_Msk          (1UL << SCB_CFSR_IMPRECISERR_Pos)               /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
+
+#define SCB_CFSR_PRECISERR_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 1U)                  /*!< SCB CFSR (BFSR): PRECISERR Position */
+#define SCB_CFSR_PRECISERR_Msk            (1UL << SCB_CFSR_PRECISERR_Pos)                 /*!< SCB CFSR (BFSR): PRECISERR Mask */
+
+#define SCB_CFSR_IBUSERR_Pos              (SCB_CFSR_BUSFAULTSR_Pos + 0U)                  /*!< SCB CFSR (BFSR): IBUSERR Position */
+#define SCB_CFSR_IBUSERR_Msk              (1UL << SCB_CFSR_IBUSERR_Pos)                   /*!< SCB CFSR (BFSR): IBUSERR Mask */
+
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_DIVBYZERO_Pos            (SCB_CFSR_USGFAULTSR_Pos + 9U)                  /*!< SCB CFSR (UFSR): DIVBYZERO Position */
+#define SCB_CFSR_DIVBYZERO_Msk            (1UL << SCB_CFSR_DIVBYZERO_Pos)                 /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
+
+#define SCB_CFSR_UNALIGNED_Pos            (SCB_CFSR_USGFAULTSR_Pos + 8U)                  /*!< SCB CFSR (UFSR): UNALIGNED Position */
+#define SCB_CFSR_UNALIGNED_Msk            (1UL << SCB_CFSR_UNALIGNED_Pos)                 /*!< SCB CFSR (UFSR): UNALIGNED Mask */
+
+#define SCB_CFSR_NOCP_Pos                 (SCB_CFSR_USGFAULTSR_Pos + 3U)                  /*!< SCB CFSR (UFSR): NOCP Position */
+#define SCB_CFSR_NOCP_Msk                 (1UL << SCB_CFSR_NOCP_Pos)                      /*!< SCB CFSR (UFSR): NOCP Mask */
+
+#define SCB_CFSR_INVPC_Pos                (SCB_CFSR_USGFAULTSR_Pos + 2U)                  /*!< SCB CFSR (UFSR): INVPC Position */
+#define SCB_CFSR_INVPC_Msk                (1UL << SCB_CFSR_INVPC_Pos)                     /*!< SCB CFSR (UFSR): INVPC Mask */
+
+#define SCB_CFSR_INVSTATE_Pos             (SCB_CFSR_USGFAULTSR_Pos + 1U)                  /*!< SCB CFSR (UFSR): INVSTATE Position */
+#define SCB_CFSR_INVSTATE_Msk             (1UL << SCB_CFSR_INVSTATE_Pos)                  /*!< SCB CFSR (UFSR): INVSTATE Mask */
+
+#define SCB_CFSR_UNDEFINSTR_Pos           (SCB_CFSR_USGFAULTSR_Pos + 0U)                  /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
+#define SCB_CFSR_UNDEFINSTR_Msk           (1UL << SCB_CFSR_UNDEFINSTR_Pos)                /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos              31U                                            /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos                30U                                            /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos                1U                                            /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos               4U                                            /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos                 3U                                            /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos                2U                                            /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos                   1U                                            /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos                 0U                                            /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+  \brief    Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+        uint32_t RESERVED0[1U];
+  __IM  uint32_t ICTR;                   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register */
+  __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos         0U                                         /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+#define SCnSCB_ACTLR_DISOOFP_Pos            9U                                         /*!< ACTLR: DISOOFP Position */
+#define SCnSCB_ACTLR_DISOOFP_Msk           (1UL << SCnSCB_ACTLR_DISOOFP_Pos)           /*!< ACTLR: DISOOFP Mask */
+
+#define SCnSCB_ACTLR_DISFPCA_Pos            8U                                         /*!< ACTLR: DISFPCA Position */
+#define SCnSCB_ACTLR_DISFPCA_Msk           (1UL << SCnSCB_ACTLR_DISFPCA_Pos)           /*!< ACTLR: DISFPCA Mask */
+
+#define SCnSCB_ACTLR_DISFOLD_Pos            2U                                         /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Msk           (1UL << SCnSCB_ACTLR_DISFOLD_Pos)           /*!< ACTLR: DISFOLD Mask */
+
+#define SCnSCB_ACTLR_DISDEFWBUF_Pos         1U                                         /*!< ACTLR: DISDEFWBUF Position */
+#define SCnSCB_ACTLR_DISDEFWBUF_Msk        (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos)        /*!< ACTLR: DISDEFWBUF Mask */
+
+#define SCnSCB_ACTLR_DISMCYCINT_Pos         0U                                         /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/)    /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
+  \brief    Type definitions for the Instrumentation Trace Macrocell (ITM)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+  __OM  union
+  {
+    __OM  uint8_t    u8;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */
+    __OM  uint16_t   u16;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */
+    __OM  uint32_t   u32;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */
+  }  PORT [32U];                         /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers */
+        uint32_t RESERVED0[864U];
+  __IOM uint32_t TER;                    /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register */
+        uint32_t RESERVED1[15U];
+  __IOM uint32_t TPR;                    /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */
+        uint32_t RESERVED2[15U];
+  __IOM uint32_t TCR;                    /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */
+        uint32_t RESERVED3[29U];
+  __OM  uint32_t IWR;                    /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register */
+  __IM  uint32_t IRR;                    /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register */
+  __IOM uint32_t IMCR;                   /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register */
+        uint32_t RESERVED4[43U];
+  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register */
+  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register */
+        uint32_t RESERVED5[6U];
+  __IM  uint32_t PID4;                   /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
+  __IM  uint32_t PID5;                   /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
+  __IM  uint32_t PID6;                   /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
+  __IM  uint32_t PID7;                   /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
+  __IM  uint32_t PID0;                   /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
+  __IM  uint32_t PID1;                   /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
+  __IM  uint32_t PID2;                   /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
+  __IM  uint32_t PID3;                   /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
+  __IM  uint32_t CID0;                   /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
+  __IM  uint32_t CID1;                   /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
+  __IM  uint32_t CID2;                   /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
+  __IM  uint32_t CID3;                   /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos                0U                                            /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk               (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/)     /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos                   23U                                            /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos             16U                                            /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos                10U                                            /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos              8U                                            /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos                  4U                                            /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos                  3U                                            /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos                 2U                                            /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos                   1U                                            /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos                  0U                                            /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos                0U                                            /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk               (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)              /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos                0U                                            /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk               (1UL /*<< ITM_IRR_ATREADYM_Pos*/)              /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos            0U                                            /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk           (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)          /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos                 2U                                            /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos                  1U                                            /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos                 0U                                            /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
+  \brief    Type definitions for the Data Watchpoint and Trace (DWT)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */
+  __IOM uint32_t CYCCNT;                 /*!< Offset: 0x004 (R/W)  Cycle Count Register */
+  __IOM uint32_t CPICNT;                 /*!< Offset: 0x008 (R/W)  CPI Count Register */
+  __IOM uint32_t EXCCNT;                 /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register */
+  __IOM uint32_t SLEEPCNT;               /*!< Offset: 0x010 (R/W)  Sleep Count Register */
+  __IOM uint32_t LSUCNT;                 /*!< Offset: 0x014 (R/W)  LSU Count Register */
+  __IOM uint32_t FOLDCNT;                /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register */
+  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */
+  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */
+  __IOM uint32_t MASK0;                  /*!< Offset: 0x024 (R/W)  Mask Register 0 */
+  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */
+        uint32_t RESERVED0[1U];
+  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */
+  __IOM uint32_t MASK1;                  /*!< Offset: 0x034 (R/W)  Mask Register 1 */
+  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */
+        uint32_t RESERVED1[1U];
+  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */
+  __IOM uint32_t MASK2;                  /*!< Offset: 0x044 (R/W)  Mask Register 2 */
+  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */
+        uint32_t RESERVED2[1U];
+  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */
+  __IOM uint32_t MASK3;                  /*!< Offset: 0x054 (R/W)  Mask Register 3 */
+  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos             22U                                         /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos            21U                                         /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos             20U                                         /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos           19U                                         /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos             18U                                         /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos             17U                                         /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos             16U                                         /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos            12U                                         /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos               10U                                         /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos                 9U                                         /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos               5U                                         /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos             1U                                         /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos              0U                                         /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos               0U                                         /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos               0U                                         /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos           0U                                         /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos               0U                                         /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos             0U                                         /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos                   0U                                         /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk                  (0x1FUL /*<< DWT_MASK_MASK_Pos*/)           /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos        16U                                         /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos        12U                                         /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos            9U                                         /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos         8U                                         /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos           7U                                         /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos          5U                                         /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos           0U                                         /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/)    /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_TPI     Trace Port Interface (TPI)
+  \brief    Type definitions for the Trace Port Interface (TPI)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+  __IM  uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */
+  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
+        uint32_t RESERVED0[2U];
+  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
+        uint32_t RESERVED1[55U];
+  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
+        uint32_t RESERVED2[131U];
+  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
+  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
+  __IM  uint32_t FSCR;                   /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
+        uint32_t RESERVED3[759U];
+  __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER Register */
+  __IM  uint32_t FIFO0;                  /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
+  __IM  uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
+        uint32_t RESERVED4[1U];
+  __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
+  __IM  uint32_t FIFO1;                  /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
+  __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
+        uint32_t RESERVED5[39U];
+  __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */
+  __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
+        uint32_t RESERVED7[8U];
+  __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
+  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos                 16U                                         /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos                  8U                                         /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos                  0U                                         /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk                 (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)          /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY2_Pos          0U                                         /*!< TPI ITATBCTR2: ATREADY2 Position */
+#define TPI_ITATBCTR2_ATREADY2_Msk         (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/)   /*!< TPI ITATBCTR2: ATREADY2 Mask */
+
+#define TPI_ITATBCTR2_ATREADY1_Pos          0U                                         /*!< TPI ITATBCTR2: ATREADY1 Position */
+#define TPI_ITATBCTR2_ATREADY1_Msk         (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/)   /*!< TPI ITATBCTR2: ATREADY1 Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos                 16U                                         /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos                  8U                                         /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos                  0U                                         /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk                 (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)          /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY2_Pos          0U                                         /*!< TPI ITATBCTR0: ATREADY2 Position */
+#define TPI_ITATBCTR0_ATREADY2_Msk         (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/)   /*!< TPI ITATBCTR0: ATREADY2 Mask */
+
+#define TPI_ITATBCTR0_ATREADY1_Pos          0U                                         /*!< TPI ITATBCTR0: ATREADY1 Position */
+#define TPI_ITATBCTR0_ATREADY1_Msk         (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/)   /*!< TPI ITATBCTR0: ATREADY1 Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk                (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos              6U                                         /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos             5U                                         /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos             4U                                         /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos           0U                                         /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+  \brief    Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
+  __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */
+  __IOM uint32_t RBAR_A1;                /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register */
+  __IOM uint32_t RASR_A1;                /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */
+  __IOM uint32_t RBAR_A2;                /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register */
+  __IOM uint32_t RASR_A2;                /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */
+  __IOM uint32_t RBAR_A3;                /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register */
+  __IOM uint32_t RASR_A3;                /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+#define MPU_TYPE_RALIASES                  4U
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos                   5U                                            /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos                    28U                                            /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos                    24U                                            /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos                     18U                                            /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos                     17U                                            /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos                     16U                                            /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_FPU     Floating Point Unit (FPU)
+  \brief    Type definitions for the Floating Point Unit (FPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Floating Point Unit (FPU).
+ */
+typedef struct
+{
+        uint32_t RESERVED0[1U];
+  __IOM uint32_t FPCCR;                  /*!< Offset: 0x004 (R/W)  Floating-Point Context Control Register */
+  __IOM uint32_t FPCAR;                  /*!< Offset: 0x008 (R/W)  Floating-Point Context Address Register */
+  __IOM uint32_t FPDSCR;                 /*!< Offset: 0x00C (R/W)  Floating-Point Default Status Control Register */
+  __IM  uint32_t MVFR0;                  /*!< Offset: 0x010 (R/ )  Media and FP Feature Register 0 */
+  __IM  uint32_t MVFR1;                  /*!< Offset: 0x014 (R/ )  Media and FP Feature Register 1 */
+} FPU_Type;
+
+/* Floating-Point Context Control Register Definitions */
+#define FPU_FPCCR_ASPEN_Pos                31U                                            /*!< FPCCR: ASPEN bit Position */
+#define FPU_FPCCR_ASPEN_Msk                (1UL << FPU_FPCCR_ASPEN_Pos)                   /*!< FPCCR: ASPEN bit Mask */
+
+#define FPU_FPCCR_LSPEN_Pos                30U                                            /*!< FPCCR: LSPEN Position */
+#define FPU_FPCCR_LSPEN_Msk                (1UL << FPU_FPCCR_LSPEN_Pos)                   /*!< FPCCR: LSPEN bit Mask */
+
+#define FPU_FPCCR_MONRDY_Pos                8U                                            /*!< FPCCR: MONRDY Position */
+#define FPU_FPCCR_MONRDY_Msk               (1UL << FPU_FPCCR_MONRDY_Pos)                  /*!< FPCCR: MONRDY bit Mask */
+
+#define FPU_FPCCR_BFRDY_Pos                 6U                                            /*!< FPCCR: BFRDY Position */
+#define FPU_FPCCR_BFRDY_Msk                (1UL << FPU_FPCCR_BFRDY_Pos)                   /*!< FPCCR: BFRDY bit Mask */
+
+#define FPU_FPCCR_MMRDY_Pos                 5U                                            /*!< FPCCR: MMRDY Position */
+#define FPU_FPCCR_MMRDY_Msk                (1UL << FPU_FPCCR_MMRDY_Pos)                   /*!< FPCCR: MMRDY bit Mask */
+
+#define FPU_FPCCR_HFRDY_Pos                 4U                                            /*!< FPCCR: HFRDY Position */
+#define FPU_FPCCR_HFRDY_Msk                (1UL << FPU_FPCCR_HFRDY_Pos)                   /*!< FPCCR: HFRDY bit Mask */
+
+#define FPU_FPCCR_THREAD_Pos                3U                                            /*!< FPCCR: processor mode bit Position */
+#define FPU_FPCCR_THREAD_Msk               (1UL << FPU_FPCCR_THREAD_Pos)                  /*!< FPCCR: processor mode active bit Mask */
+
+#define FPU_FPCCR_USER_Pos                  1U                                            /*!< FPCCR: privilege level bit Position */
+#define FPU_FPCCR_USER_Msk                 (1UL << FPU_FPCCR_USER_Pos)                    /*!< FPCCR: privilege level bit Mask */
+
+#define FPU_FPCCR_LSPACT_Pos                0U                                            /*!< FPCCR: Lazy state preservation active bit Position */
+#define FPU_FPCCR_LSPACT_Msk               (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)              /*!< FPCCR: Lazy state preservation active bit Mask */
+
+/* Floating-Point Context Address Register Definitions */
+#define FPU_FPCAR_ADDRESS_Pos               3U                                            /*!< FPCAR: ADDRESS bit Position */
+#define FPU_FPCAR_ADDRESS_Msk              (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)        /*!< FPCAR: ADDRESS bit Mask */
+
+/* Floating-Point Default Status Control Register Definitions */
+#define FPU_FPDSCR_AHP_Pos                 26U                                            /*!< FPDSCR: AHP bit Position */
+#define FPU_FPDSCR_AHP_Msk                 (1UL << FPU_FPDSCR_AHP_Pos)                    /*!< FPDSCR: AHP bit Mask */
+
+#define FPU_FPDSCR_DN_Pos                  25U                                            /*!< FPDSCR: DN bit Position */
+#define FPU_FPDSCR_DN_Msk                  (1UL << FPU_FPDSCR_DN_Pos)                     /*!< FPDSCR: DN bit Mask */
+
+#define FPU_FPDSCR_FZ_Pos                  24U                                            /*!< FPDSCR: FZ bit Position */
+#define FPU_FPDSCR_FZ_Msk                  (1UL << FPU_FPDSCR_FZ_Pos)                     /*!< FPDSCR: FZ bit Mask */
+
+#define FPU_FPDSCR_RMode_Pos               22U                                            /*!< FPDSCR: RMode bit Position */
+#define FPU_FPDSCR_RMode_Msk               (3UL << FPU_FPDSCR_RMode_Pos)                  /*!< FPDSCR: RMode bit Mask */
+
+/* Media and FP Feature Register 0 Definitions */
+#define FPU_MVFR0_FP_rounding_modes_Pos    28U                                            /*!< MVFR0: FP rounding modes bits Position */
+#define FPU_MVFR0_FP_rounding_modes_Msk    (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)     /*!< MVFR0: FP rounding modes bits Mask */
+
+#define FPU_MVFR0_Short_vectors_Pos        24U                                            /*!< MVFR0: Short vectors bits Position */
+#define FPU_MVFR0_Short_vectors_Msk        (0xFUL << FPU_MVFR0_Short_vectors_Pos)         /*!< MVFR0: Short vectors bits Mask */
+
+#define FPU_MVFR0_Square_root_Pos          20U                                            /*!< MVFR0: Square root bits Position */
+#define FPU_MVFR0_Square_root_Msk          (0xFUL << FPU_MVFR0_Square_root_Pos)           /*!< MVFR0: Square root bits Mask */
+
+#define FPU_MVFR0_Divide_Pos               16U                                            /*!< MVFR0: Divide bits Position */
+#define FPU_MVFR0_Divide_Msk               (0xFUL << FPU_MVFR0_Divide_Pos)                /*!< MVFR0: Divide bits Mask */
+
+#define FPU_MVFR0_FP_excep_trapping_Pos    12U                                            /*!< MVFR0: FP exception trapping bits Position */
+#define FPU_MVFR0_FP_excep_trapping_Msk    (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)     /*!< MVFR0: FP exception trapping bits Mask */
+
+#define FPU_MVFR0_Double_precision_Pos      8U                                            /*!< MVFR0: Double-precision bits Position */
+#define FPU_MVFR0_Double_precision_Msk     (0xFUL << FPU_MVFR0_Double_precision_Pos)      /*!< MVFR0: Double-precision bits Mask */
+
+#define FPU_MVFR0_Single_precision_Pos      4U                                            /*!< MVFR0: Single-precision bits Position */
+#define FPU_MVFR0_Single_precision_Msk     (0xFUL << FPU_MVFR0_Single_precision_Pos)      /*!< MVFR0: Single-precision bits Mask */
+
+#define FPU_MVFR0_A_SIMD_registers_Pos      0U                                            /*!< MVFR0: A_SIMD registers bits Position */
+#define FPU_MVFR0_A_SIMD_registers_Msk     (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)  /*!< MVFR0: A_SIMD registers bits Mask */
+
+/* Media and FP Feature Register 1 Definitions */
+#define FPU_MVFR1_FP_fused_MAC_Pos         28U                                            /*!< MVFR1: FP fused MAC bits Position */
+#define FPU_MVFR1_FP_fused_MAC_Msk         (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)          /*!< MVFR1: FP fused MAC bits Mask */
+
+#define FPU_MVFR1_FP_HPFP_Pos              24U                                            /*!< MVFR1: FP HPFP bits Position */
+#define FPU_MVFR1_FP_HPFP_Msk              (0xFUL << FPU_MVFR1_FP_HPFP_Pos)               /*!< MVFR1: FP HPFP bits Mask */
+
+#define FPU_MVFR1_D_NaN_mode_Pos            4U                                            /*!< MVFR1: D_NaN mode bits Position */
+#define FPU_MVFR1_D_NaN_mode_Msk           (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)            /*!< MVFR1: D_NaN mode bits Mask */
+
+#define FPU_MVFR1_FtZ_mode_Pos              0U                                            /*!< MVFR1: FtZ mode bits Position */
+#define FPU_MVFR1_FtZ_mode_Msk             (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)          /*!< MVFR1: FtZ mode bits Mask */
+
+/*@} end of group CMSIS_FPU */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    Type definitions for the Core Debug Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */
+  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */
+  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */
+  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5U                                            /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos         24U                                            /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos        19U                                            /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos       18U                                            /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos       17U                                            /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos         16U                                            /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos       9U                                            /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos       8U                                            /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos      7U                                            /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos       6U                                            /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5U                                            /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos        4U                                            /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
+#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address */
+#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address */
+#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address */
+#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
+
+#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */
+#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct */
+#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct */
+#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct */
+#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit */
+  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit */
+#endif
+
+#define FPU_BASE            (SCS_BASE +  0x0F30UL)                    /*!< Floating Point Unit */
+#define FPU                 ((FPU_Type       *)     FPU_BASE      )   /*!< Floating Point Unit */
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Debug Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+  #endif
+  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
+  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
+  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
+  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
+  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
+  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+  #define NVIC_GetActive              __NVIC_GetActive
+  #define NVIC_SetPriority            __NVIC_SetPriority
+  #define NVIC_GetPriority            __NVIC_GetPriority
+  #define NVIC_SystemReset            __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+   #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+  #endif
+  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetVector              __NVIC_SetVector
+  #define NVIC_GetVector              __NVIC_GetVector
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET          16
+
+
+/* The following EXC_RETURN values are saved the LR on exception entry */
+#define EXC_RETURN_HANDLER         (0xFFFFFFF1UL)     /* return to Handler mode, uses MSP after return                               */
+#define EXC_RETURN_THREAD_MSP      (0xFFFFFFF9UL)     /* return to Thread mode, uses MSP after return                                */
+#define EXC_RETURN_THREAD_PSP      (0xFFFFFFFDUL)     /* return to Thread mode, uses PSP after return                                */
+#define EXC_RETURN_HANDLER_FPU     (0xFFFFFFE1UL)     /* return to Handler mode, uses MSP after return, restore floating-point state */
+#define EXC_RETURN_THREAD_MSP_FPU  (0xFFFFFFE9UL)     /* return to Thread mode, uses MSP after return, restore floating-point state  */
+#define EXC_RETURN_THREAD_PSP_FPU  (0xFFFFFFEDUL)     /* return to Thread mode, uses PSP after return, restore floating-point state  */
+
+
+/**
+  \brief   Set Priority Grouping
+  \details Sets the priority grouping field using the required unlock sequence.
+           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+           Only values from 0..7 are used.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]      PriorityGroup  Priority grouping field.
+ */
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+  uint32_t reg_value;
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
+
+  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
+  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */
+  reg_value  =  (reg_value                                   |
+                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos)  );              /* Insert write key and priority group */
+  SCB->AIRCR =  reg_value;
+}
+
+
+/**
+  \brief   Get Priority Grouping
+  \details Reads the priority grouping field from the NVIC Interrupt Controller.
+  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
+{
+  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+  \brief   Enable Interrupt
+  \details Enables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt
+  \details Disables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+    __DSB();
+    __ISB();
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Active Interrupt
+  \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not active.
+  \return             1  Interrupt status is active.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->IP[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+  else
+  {
+    SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return(((uint32_t)NVIC->IP[((uint32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+
+
+/**
+  \brief   Encode Priority
+  \details Encodes the priority for an interrupt with the given priority group,
+           preemptive priority value, and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]     PriorityGroup  Used priority group.
+  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+  \param [in]       SubPriority  Subpriority value (starting from 0).
+  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  return (
+           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
+         );
+}
+
+
+/**
+  \brief   Decode Priority
+  \details Decodes an interrupt priority value with a given priority group to
+           preemptive priority value and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+  \param [in]     PriorityGroup  Used priority group.
+  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+  \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
+}
+
+
+/**
+  \brief   Set Interrupt Vector
+  \details Sets an interrupt vector in SRAM based interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+           VTOR must been relocated to SRAM before.
+  \param [in]   IRQn      Interrupt number
+  \param [in]   vector    Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+  \brief   Get Interrupt Vector
+  \details Reads an interrupt vector from interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn      Interrupt number.
+  \return                 Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+  __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
+                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */
+  __DSB();                                                          /* Ensure completion of memory access */
+
+  for(;;)                                                           /* wait until reset */
+  {
+    __NOP();
+  }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+/* ##########################  MPU functions  #################################### */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+
+#include "mpu_armv7.h"
+
+#endif
+
+
+/* ##########################  FPU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions
+  \brief    Function that provides FPU type.
+  @{
+ */
+
+/**
+  \brief   get FPU type
+  \details returns the FPU type
+  \returns
+   - \b  0: No FPU
+   - \b  1: Single precision FPU
+   - \b  2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+  uint32_t mvfr0;
+
+  mvfr0 = FPU->MVFR0;
+  if      ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)
+  {
+    return 1U;           /* Single precision FPU */
+  }
+  else
+  {
+    return 0U;           /* No FPU */
+  }
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                   /* Reload value impossible */
+  }
+
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                     /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_core_DebugFunctions ITM Functions
+  \brief    Functions that access the ITM debug interface.
+  @{
+ */
+
+extern volatile int32_t ITM_RxBuffer;                              /*!< External variable to receive characters. */
+#define                 ITM_RXBUFFER_EMPTY  ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/**
+  \brief   ITM Send Character
+  \details Transmits a character via the ITM channel 0, and
+           \li Just returns when no debugger is connected that has booked the output.
+           \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+  \param [in]     ch  Character to transmit.
+  \returns            Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */
+      ((ITM->TER & 1UL               ) != 0UL)   )     /* ITM Port #0 enabled */
+  {
+    while (ITM->PORT[0U].u32 == 0UL)
+    {
+      __NOP();
+    }
+    ITM->PORT[0U].u8 = (uint8_t)ch;
+  }
+  return (ch);
+}
+
+
+/**
+  \brief   ITM Receive Character
+  \details Inputs a character via the external variable \ref ITM_RxBuffer.
+  \return             Received character.
+  \return         -1  No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)
+{
+  int32_t ch = -1;                           /* no character available */
+
+  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
+  {
+    ch = ITM_RxBuffer;
+    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
+  }
+
+  return (ch);
+}
+
+
+/**
+  \brief   ITM Check Character
+  \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+  \return          0  No character available.
+  \return          1  Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void)
+{
+
+  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
+  {
+    return (0);                              /* no character available */
+  }
+  else
+  {
+    return (1);                              /*    character available */
+  }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM4_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/Drivers/CMSIS/Include/core_cm7.h b/Drivers/CMSIS/Include/core_cm7.h
new file mode 100644
index 0000000..ada6c2a
--- /dev/null
+++ b/Drivers/CMSIS/Include/core_cm7.h
@@ -0,0 +1,2671 @@
+/**************************************************************************//**
+ * @file     core_cm7.h
+ * @brief    CMSIS Cortex-M7 Core Peripheral Access Layer Header File
+ * @version  V5.0.8
+ * @date     04. June 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM7_H_GENERIC
+#define __CORE_CM7_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup Cortex_M7
+  @{
+ */
+
+#include "cmsis_version.h"
+
+/* CMSIS CM7 definitions */
+#define __CM7_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)                  /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __CM7_CMSIS_VERSION_SUB   ( __CM_CMSIS_VERSION_SUB)                  /*!< \deprecated [15:0]  CMSIS HAL sub version */
+#define __CM7_CMSIS_VERSION       ((__CM7_CMSIS_VERSION_MAIN << 16U) | \
+                                    __CM7_CMSIS_VERSION_SUB           )      /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M                (7U)                                       /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
+*/
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #if defined __ARM_PCS_VFP
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __TI_ARM__ )
+  #if defined __TI_VFP_SUPPORT__
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __CSMC__ )
+  #if ( __CSMC__ & 0x400U)
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#endif
+
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM7_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM7_H_DEPENDANT
+#define __CORE_CM7_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM7_REV
+    #define __CM7_REV               0x0000U
+    #warning "__CM7_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __FPU_PRESENT
+    #define __FPU_PRESENT             0U
+    #warning "__FPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0U
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __ICACHE_PRESENT
+    #define __ICACHE_PRESENT          0U
+    #warning "__ICACHE_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __DCACHE_PRESENT
+    #define __DCACHE_PRESENT          0U
+    #warning "__DCACHE_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __DTCM_PRESENT
+    #define __DTCM_PRESENT            0U
+    #warning "__DTCM_PRESENT        not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          3U
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0U
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M7 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core Debug Register
+  - Core MPU Register
+  - Core FPU Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */
+    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+#define APSR_Q_Pos                         27U                                            /*!< APSR: Q Position */
+#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */
+
+#define APSR_GE_Pos                        16U                                            /*!< APSR: GE Position */
+#define APSR_GE_Msk                        (0xFUL << APSR_GE_Pos)                         /*!< APSR: GE Mask */
+
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:1;               /*!< bit:      9  Reserved */
+    uint32_t ICI_IT_1:6;                 /*!< bit: 10..15  ICI/IT part 1 */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */
+    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit */
+    uint32_t ICI_IT_2:2;                 /*!< bit: 25..26  ICI/IT part 2 */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos                         27U                                            /*!< xPSR: Q Position */
+#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */
+
+#define xPSR_ICI_IT_2_Pos                  25U                                            /*!< xPSR: ICI/IT part 2 Position */
+#define xPSR_ICI_IT_2_Msk                  (3UL << xPSR_ICI_IT_2_Pos)                     /*!< xPSR: ICI/IT part 2 Mask */
+
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_GE_Pos                        16U                                            /*!< xPSR: GE Position */
+#define xPSR_GE_Msk                        (0xFUL << xPSR_GE_Pos)                         /*!< xPSR: GE Mask */
+
+#define xPSR_ICI_IT_1_Pos                  10U                                            /*!< xPSR: ICI/IT part 1 Position */
+#define xPSR_ICI_IT_1_Msk                  (0x3FUL << xPSR_ICI_IT_1_Pos)                  /*!< xPSR: ICI/IT part 1 Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */
+    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag */
+    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_FPCA_Pos                    2U                                            /*!< CONTROL: FPCA Position */
+#define CONTROL_FPCA_Msk                   (1UL << CONTROL_FPCA_Pos)                      /*!< CONTROL: FPCA Mask */
+
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IOM uint32_t ISER[8U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+        uint32_t RESERVED0[24U];
+  __IOM uint32_t ICER[8U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+        uint32_t RSERVED1[24U];
+  __IOM uint32_t ISPR[8U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+        uint32_t RESERVED2[24U];
+  __IOM uint32_t ICPR[8U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+        uint32_t RESERVED3[24U];
+  __IOM uint32_t IABR[8U];               /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */
+        uint32_t RESERVED4[56U];
+  __IOM uint8_t  IP[240U];               /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
+        uint32_t RESERVED5[644U];
+  __OM  uint32_t STIR;                   /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register */
+}  NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos                 0U                                         /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
+  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+  __IOM uint8_t  SHPR[12U];              /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
+  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+  __IOM uint32_t CFSR;                   /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register */
+  __IOM uint32_t HFSR;                   /*!< Offset: 0x02C (R/W)  HardFault Status Register */
+  __IOM uint32_t DFSR;                   /*!< Offset: 0x030 (R/W)  Debug Fault Status Register */
+  __IOM uint32_t MMFAR;                  /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register */
+  __IOM uint32_t BFAR;                   /*!< Offset: 0x038 (R/W)  BusFault Address Register */
+  __IOM uint32_t AFSR;                   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register */
+  __IM  uint32_t ID_PFR[2U];             /*!< Offset: 0x040 (R/ )  Processor Feature Register */
+  __IM  uint32_t ID_DFR;                 /*!< Offset: 0x048 (R/ )  Debug Feature Register */
+  __IM  uint32_t ID_AFR;                 /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */
+  __IM  uint32_t ID_MFR[4U];             /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */
+  __IM  uint32_t ID_ISAR[5U];            /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register */
+        uint32_t RESERVED0[1U];
+  __IM  uint32_t CLIDR;                  /*!< Offset: 0x078 (R/ )  Cache Level ID register */
+  __IM  uint32_t CTR;                    /*!< Offset: 0x07C (R/ )  Cache Type register */
+  __IM  uint32_t CCSIDR;                 /*!< Offset: 0x080 (R/ )  Cache Size ID Register */
+  __IOM uint32_t CSSELR;                 /*!< Offset: 0x084 (R/W)  Cache Size Selection Register */
+  __IOM uint32_t CPACR;                  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register */
+        uint32_t RESERVED3[93U];
+  __OM  uint32_t STIR;                   /*!< Offset: 0x200 ( /W)  Software Triggered Interrupt Register */
+        uint32_t RESERVED4[15U];
+  __IM  uint32_t MVFR0;                  /*!< Offset: 0x240 (R/ )  Media and VFP Feature Register 0 */
+  __IM  uint32_t MVFR1;                  /*!< Offset: 0x244 (R/ )  Media and VFP Feature Register 1 */
+  __IM  uint32_t MVFR2;                  /*!< Offset: 0x248 (R/ )  Media and VFP Feature Register 2 */
+        uint32_t RESERVED5[1U];
+  __OM  uint32_t ICIALLU;                /*!< Offset: 0x250 ( /W)  I-Cache Invalidate All to PoU */
+        uint32_t RESERVED6[1U];
+  __OM  uint32_t ICIMVAU;                /*!< Offset: 0x258 ( /W)  I-Cache Invalidate by MVA to PoU */
+  __OM  uint32_t DCIMVAC;                /*!< Offset: 0x25C ( /W)  D-Cache Invalidate by MVA to PoC */
+  __OM  uint32_t DCISW;                  /*!< Offset: 0x260 ( /W)  D-Cache Invalidate by Set-way */
+  __OM  uint32_t DCCMVAU;                /*!< Offset: 0x264 ( /W)  D-Cache Clean by MVA to PoU */
+  __OM  uint32_t DCCMVAC;                /*!< Offset: 0x268 ( /W)  D-Cache Clean by MVA to PoC */
+  __OM  uint32_t DCCSW;                  /*!< Offset: 0x26C ( /W)  D-Cache Clean by Set-way */
+  __OM  uint32_t DCCIMVAC;               /*!< Offset: 0x270 ( /W)  D-Cache Clean and Invalidate by MVA to PoC */
+  __OM  uint32_t DCCISW;                 /*!< Offset: 0x274 ( /W)  D-Cache Clean and Invalidate by Set-way */
+        uint32_t RESERVED7[6U];
+  __IOM uint32_t ITCMCR;                 /*!< Offset: 0x290 (R/W)  Instruction Tightly-Coupled Memory Control Register */
+  __IOM uint32_t DTCMCR;                 /*!< Offset: 0x294 (R/W)  Data Tightly-Coupled Memory Control Registers */
+  __IOM uint32_t AHBPCR;                 /*!< Offset: 0x298 (R/W)  AHBP Control Register */
+  __IOM uint32_t CACR;                   /*!< Offset: 0x29C (R/W)  L1 Cache Control Register */
+  __IOM uint32_t AHBSCR;                 /*!< Offset: 0x2A0 (R/W)  AHB Slave Control Register */
+        uint32_t RESERVED8[1U];
+  __IOM uint32_t ABFSR;                  /*!< Offset: 0x2A8 (R/W)  Auxiliary Bus Fault Status Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos              8U                                            /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos             0U                                            /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk            (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)           /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_BP_Pos                      18U                                           /*!< SCB CCR: Branch prediction enable bit Position */
+#define SCB_CCR_BP_Msk                     (1UL << SCB_CCR_BP_Pos)                        /*!< SCB CCR: Branch prediction enable bit Mask */
+
+#define SCB_CCR_IC_Pos                      17U                                           /*!< SCB CCR: Instruction cache enable bit Position */
+#define SCB_CCR_IC_Msk                     (1UL << SCB_CCR_IC_Pos)                        /*!< SCB CCR: Instruction cache enable bit Mask */
+
+#define SCB_CCR_DC_Pos                      16U                                           /*!< SCB CCR: Cache enable bit Position */
+#define SCB_CCR_DC_Msk                     (1UL << SCB_CCR_DC_Pos)                        /*!< SCB CCR: Cache enable bit Mask */
+
+#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos          0U                                            /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk         (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)        /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos          18U                                            /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos          17U                                            /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos          16U                                            /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos       14U                                            /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos       13U                                            /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos       12U                                            /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos            8U                                            /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos           3U                                            /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos           1U                                            /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos           0U                                            /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos            16U                                            /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos             8U                                            /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos             0U                                            /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_MMARVALID_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 7U)               /*!< SCB CFSR (MMFSR): MMARVALID Position */
+#define SCB_CFSR_MMARVALID_Msk             (1UL << SCB_CFSR_MMARVALID_Pos)                /*!< SCB CFSR (MMFSR): MMARVALID Mask */
+
+#define SCB_CFSR_MLSPERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 5U)               /*!< SCB CFSR (MMFSR): MLSPERR Position */
+#define SCB_CFSR_MLSPERR_Msk               (1UL << SCB_CFSR_MLSPERR_Pos)                  /*!< SCB CFSR (MMFSR): MLSPERR Mask */
+
+#define SCB_CFSR_MSTKERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 4U)               /*!< SCB CFSR (MMFSR): MSTKERR Position */
+#define SCB_CFSR_MSTKERR_Msk               (1UL << SCB_CFSR_MSTKERR_Pos)                  /*!< SCB CFSR (MMFSR): MSTKERR Mask */
+
+#define SCB_CFSR_MUNSTKERR_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 3U)               /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
+#define SCB_CFSR_MUNSTKERR_Msk             (1UL << SCB_CFSR_MUNSTKERR_Pos)                /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
+
+#define SCB_CFSR_DACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 1U)               /*!< SCB CFSR (MMFSR): DACCVIOL Position */
+#define SCB_CFSR_DACCVIOL_Msk              (1UL << SCB_CFSR_DACCVIOL_Pos)                 /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
+
+#define SCB_CFSR_IACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 0U)               /*!< SCB CFSR (MMFSR): IACCVIOL Position */
+#define SCB_CFSR_IACCVIOL_Msk              (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)             /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
+
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_BFARVALID_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 7U)                  /*!< SCB CFSR (BFSR): BFARVALID Position */
+#define SCB_CFSR_BFARVALID_Msk            (1UL << SCB_CFSR_BFARVALID_Pos)                 /*!< SCB CFSR (BFSR): BFARVALID Mask */
+
+#define SCB_CFSR_LSPERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 5U)                  /*!< SCB CFSR (BFSR): LSPERR Position */
+#define SCB_CFSR_LSPERR_Msk               (1UL << SCB_CFSR_LSPERR_Pos)                    /*!< SCB CFSR (BFSR): LSPERR Mask */
+
+#define SCB_CFSR_STKERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 4U)                  /*!< SCB CFSR (BFSR): STKERR Position */
+#define SCB_CFSR_STKERR_Msk               (1UL << SCB_CFSR_STKERR_Pos)                    /*!< SCB CFSR (BFSR): STKERR Mask */
+
+#define SCB_CFSR_UNSTKERR_Pos             (SCB_CFSR_BUSFAULTSR_Pos + 3U)                  /*!< SCB CFSR (BFSR): UNSTKERR Position */
+#define SCB_CFSR_UNSTKERR_Msk             (1UL << SCB_CFSR_UNSTKERR_Pos)                  /*!< SCB CFSR (BFSR): UNSTKERR Mask */
+
+#define SCB_CFSR_IMPRECISERR_Pos          (SCB_CFSR_BUSFAULTSR_Pos + 2U)                  /*!< SCB CFSR (BFSR): IMPRECISERR Position */
+#define SCB_CFSR_IMPRECISERR_Msk          (1UL << SCB_CFSR_IMPRECISERR_Pos)               /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
+
+#define SCB_CFSR_PRECISERR_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 1U)                  /*!< SCB CFSR (BFSR): PRECISERR Position */
+#define SCB_CFSR_PRECISERR_Msk            (1UL << SCB_CFSR_PRECISERR_Pos)                 /*!< SCB CFSR (BFSR): PRECISERR Mask */
+
+#define SCB_CFSR_IBUSERR_Pos              (SCB_CFSR_BUSFAULTSR_Pos + 0U)                  /*!< SCB CFSR (BFSR): IBUSERR Position */
+#define SCB_CFSR_IBUSERR_Msk              (1UL << SCB_CFSR_IBUSERR_Pos)                   /*!< SCB CFSR (BFSR): IBUSERR Mask */
+
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_DIVBYZERO_Pos            (SCB_CFSR_USGFAULTSR_Pos + 9U)                  /*!< SCB CFSR (UFSR): DIVBYZERO Position */
+#define SCB_CFSR_DIVBYZERO_Msk            (1UL << SCB_CFSR_DIVBYZERO_Pos)                 /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
+
+#define SCB_CFSR_UNALIGNED_Pos            (SCB_CFSR_USGFAULTSR_Pos + 8U)                  /*!< SCB CFSR (UFSR): UNALIGNED Position */
+#define SCB_CFSR_UNALIGNED_Msk            (1UL << SCB_CFSR_UNALIGNED_Pos)                 /*!< SCB CFSR (UFSR): UNALIGNED Mask */
+
+#define SCB_CFSR_NOCP_Pos                 (SCB_CFSR_USGFAULTSR_Pos + 3U)                  /*!< SCB CFSR (UFSR): NOCP Position */
+#define SCB_CFSR_NOCP_Msk                 (1UL << SCB_CFSR_NOCP_Pos)                      /*!< SCB CFSR (UFSR): NOCP Mask */
+
+#define SCB_CFSR_INVPC_Pos                (SCB_CFSR_USGFAULTSR_Pos + 2U)                  /*!< SCB CFSR (UFSR): INVPC Position */
+#define SCB_CFSR_INVPC_Msk                (1UL << SCB_CFSR_INVPC_Pos)                     /*!< SCB CFSR (UFSR): INVPC Mask */
+
+#define SCB_CFSR_INVSTATE_Pos             (SCB_CFSR_USGFAULTSR_Pos + 1U)                  /*!< SCB CFSR (UFSR): INVSTATE Position */
+#define SCB_CFSR_INVSTATE_Msk             (1UL << SCB_CFSR_INVSTATE_Pos)                  /*!< SCB CFSR (UFSR): INVSTATE Mask */
+
+#define SCB_CFSR_UNDEFINSTR_Pos           (SCB_CFSR_USGFAULTSR_Pos + 0U)                  /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
+#define SCB_CFSR_UNDEFINSTR_Msk           (1UL << SCB_CFSR_UNDEFINSTR_Pos)                /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos              31U                                            /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos                30U                                            /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos                1U                                            /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos               4U                                            /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos                 3U                                            /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos                2U                                            /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos                   1U                                            /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos                 0U                                            /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */
+
+/* SCB Cache Level ID Register Definitions */
+#define SCB_CLIDR_LOUU_Pos                 27U                                            /*!< SCB CLIDR: LoUU Position */
+#define SCB_CLIDR_LOUU_Msk                 (7UL << SCB_CLIDR_LOUU_Pos)                    /*!< SCB CLIDR: LoUU Mask */
+
+#define SCB_CLIDR_LOC_Pos                  24U                                            /*!< SCB CLIDR: LoC Position */
+#define SCB_CLIDR_LOC_Msk                  (7UL << SCB_CLIDR_LOC_Pos)                     /*!< SCB CLIDR: LoC Mask */
+
+/* SCB Cache Type Register Definitions */
+#define SCB_CTR_FORMAT_Pos                 29U                                            /*!< SCB CTR: Format Position */
+#define SCB_CTR_FORMAT_Msk                 (7UL << SCB_CTR_FORMAT_Pos)                    /*!< SCB CTR: Format Mask */
+
+#define SCB_CTR_CWG_Pos                    24U                                            /*!< SCB CTR: CWG Position */
+#define SCB_CTR_CWG_Msk                    (0xFUL << SCB_CTR_CWG_Pos)                     /*!< SCB CTR: CWG Mask */
+
+#define SCB_CTR_ERG_Pos                    20U                                            /*!< SCB CTR: ERG Position */
+#define SCB_CTR_ERG_Msk                    (0xFUL << SCB_CTR_ERG_Pos)                     /*!< SCB CTR: ERG Mask */
+
+#define SCB_CTR_DMINLINE_Pos               16U                                            /*!< SCB CTR: DminLine Position */
+#define SCB_CTR_DMINLINE_Msk               (0xFUL << SCB_CTR_DMINLINE_Pos)                /*!< SCB CTR: DminLine Mask */
+
+#define SCB_CTR_IMINLINE_Pos                0U                                            /*!< SCB CTR: ImInLine Position */
+#define SCB_CTR_IMINLINE_Msk               (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/)            /*!< SCB CTR: ImInLine Mask */
+
+/* SCB Cache Size ID Register Definitions */
+#define SCB_CCSIDR_WT_Pos                  31U                                            /*!< SCB CCSIDR: WT Position */
+#define SCB_CCSIDR_WT_Msk                  (1UL << SCB_CCSIDR_WT_Pos)                     /*!< SCB CCSIDR: WT Mask */
+
+#define SCB_CCSIDR_WB_Pos                  30U                                            /*!< SCB CCSIDR: WB Position */
+#define SCB_CCSIDR_WB_Msk                  (1UL << SCB_CCSIDR_WB_Pos)                     /*!< SCB CCSIDR: WB Mask */
+
+#define SCB_CCSIDR_RA_Pos                  29U                                            /*!< SCB CCSIDR: RA Position */
+#define SCB_CCSIDR_RA_Msk                  (1UL << SCB_CCSIDR_RA_Pos)                     /*!< SCB CCSIDR: RA Mask */
+
+#define SCB_CCSIDR_WA_Pos                  28U                                            /*!< SCB CCSIDR: WA Position */
+#define SCB_CCSIDR_WA_Msk                  (1UL << SCB_CCSIDR_WA_Pos)                     /*!< SCB CCSIDR: WA Mask */
+
+#define SCB_CCSIDR_NUMSETS_Pos             13U                                            /*!< SCB CCSIDR: NumSets Position */
+#define SCB_CCSIDR_NUMSETS_Msk             (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)           /*!< SCB CCSIDR: NumSets Mask */
+
+#define SCB_CCSIDR_ASSOCIATIVITY_Pos        3U                                            /*!< SCB CCSIDR: Associativity Position */
+#define SCB_CCSIDR_ASSOCIATIVITY_Msk       (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)      /*!< SCB CCSIDR: Associativity Mask */
+
+#define SCB_CCSIDR_LINESIZE_Pos             0U                                            /*!< SCB CCSIDR: LineSize Position */
+#define SCB_CCSIDR_LINESIZE_Msk            (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/)           /*!< SCB CCSIDR: LineSize Mask */
+
+/* SCB Cache Size Selection Register Definitions */
+#define SCB_CSSELR_LEVEL_Pos                1U                                            /*!< SCB CSSELR: Level Position */
+#define SCB_CSSELR_LEVEL_Msk               (7UL << SCB_CSSELR_LEVEL_Pos)                  /*!< SCB CSSELR: Level Mask */
+
+#define SCB_CSSELR_IND_Pos                  0U                                            /*!< SCB CSSELR: InD Position */
+#define SCB_CSSELR_IND_Msk                 (1UL /*<< SCB_CSSELR_IND_Pos*/)                /*!< SCB CSSELR: InD Mask */
+
+/* SCB Software Triggered Interrupt Register Definitions */
+#define SCB_STIR_INTID_Pos                  0U                                            /*!< SCB STIR: INTID Position */
+#define SCB_STIR_INTID_Msk                 (0x1FFUL /*<< SCB_STIR_INTID_Pos*/)            /*!< SCB STIR: INTID Mask */
+
+/* SCB D-Cache Invalidate by Set-way Register Definitions */
+#define SCB_DCISW_WAY_Pos                  30U                                            /*!< SCB DCISW: Way Position */
+#define SCB_DCISW_WAY_Msk                  (3UL << SCB_DCISW_WAY_Pos)                     /*!< SCB DCISW: Way Mask */
+
+#define SCB_DCISW_SET_Pos                   5U                                            /*!< SCB DCISW: Set Position */
+#define SCB_DCISW_SET_Msk                  (0x1FFUL << SCB_DCISW_SET_Pos)                 /*!< SCB DCISW: Set Mask */
+
+/* SCB D-Cache Clean by Set-way Register Definitions */
+#define SCB_DCCSW_WAY_Pos                  30U                                            /*!< SCB DCCSW: Way Position */
+#define SCB_DCCSW_WAY_Msk                  (3UL << SCB_DCCSW_WAY_Pos)                     /*!< SCB DCCSW: Way Mask */
+
+#define SCB_DCCSW_SET_Pos                   5U                                            /*!< SCB DCCSW: Set Position */
+#define SCB_DCCSW_SET_Msk                  (0x1FFUL << SCB_DCCSW_SET_Pos)                 /*!< SCB DCCSW: Set Mask */
+
+/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */
+#define SCB_DCCISW_WAY_Pos                 30U                                            /*!< SCB DCCISW: Way Position */
+#define SCB_DCCISW_WAY_Msk                 (3UL << SCB_DCCISW_WAY_Pos)                    /*!< SCB DCCISW: Way Mask */
+
+#define SCB_DCCISW_SET_Pos                  5U                                            /*!< SCB DCCISW: Set Position */
+#define SCB_DCCISW_SET_Msk                 (0x1FFUL << SCB_DCCISW_SET_Pos)                /*!< SCB DCCISW: Set Mask */
+
+/* Instruction Tightly-Coupled Memory Control Register Definitions */
+#define SCB_ITCMCR_SZ_Pos                   3U                                            /*!< SCB ITCMCR: SZ Position */
+#define SCB_ITCMCR_SZ_Msk                  (0xFUL << SCB_ITCMCR_SZ_Pos)                   /*!< SCB ITCMCR: SZ Mask */
+
+#define SCB_ITCMCR_RETEN_Pos                2U                                            /*!< SCB ITCMCR: RETEN Position */
+#define SCB_ITCMCR_RETEN_Msk               (1UL << SCB_ITCMCR_RETEN_Pos)                  /*!< SCB ITCMCR: RETEN Mask */
+
+#define SCB_ITCMCR_RMW_Pos                  1U                                            /*!< SCB ITCMCR: RMW Position */
+#define SCB_ITCMCR_RMW_Msk                 (1UL << SCB_ITCMCR_RMW_Pos)                    /*!< SCB ITCMCR: RMW Mask */
+
+#define SCB_ITCMCR_EN_Pos                   0U                                            /*!< SCB ITCMCR: EN Position */
+#define SCB_ITCMCR_EN_Msk                  (1UL /*<< SCB_ITCMCR_EN_Pos*/)                 /*!< SCB ITCMCR: EN Mask */
+
+/* Data Tightly-Coupled Memory Control Register Definitions */
+#define SCB_DTCMCR_SZ_Pos                   3U                                            /*!< SCB DTCMCR: SZ Position */
+#define SCB_DTCMCR_SZ_Msk                  (0xFUL << SCB_DTCMCR_SZ_Pos)                   /*!< SCB DTCMCR: SZ Mask */
+
+#define SCB_DTCMCR_RETEN_Pos                2U                                            /*!< SCB DTCMCR: RETEN Position */
+#define SCB_DTCMCR_RETEN_Msk               (1UL << SCB_DTCMCR_RETEN_Pos)                   /*!< SCB DTCMCR: RETEN Mask */
+
+#define SCB_DTCMCR_RMW_Pos                  1U                                            /*!< SCB DTCMCR: RMW Position */
+#define SCB_DTCMCR_RMW_Msk                 (1UL << SCB_DTCMCR_RMW_Pos)                    /*!< SCB DTCMCR: RMW Mask */
+
+#define SCB_DTCMCR_EN_Pos                   0U                                            /*!< SCB DTCMCR: EN Position */
+#define SCB_DTCMCR_EN_Msk                  (1UL /*<< SCB_DTCMCR_EN_Pos*/)                 /*!< SCB DTCMCR: EN Mask */
+
+/* AHBP Control Register Definitions */
+#define SCB_AHBPCR_SZ_Pos                   1U                                            /*!< SCB AHBPCR: SZ Position */
+#define SCB_AHBPCR_SZ_Msk                  (7UL << SCB_AHBPCR_SZ_Pos)                     /*!< SCB AHBPCR: SZ Mask */
+
+#define SCB_AHBPCR_EN_Pos                   0U                                            /*!< SCB AHBPCR: EN Position */
+#define SCB_AHBPCR_EN_Msk                  (1UL /*<< SCB_AHBPCR_EN_Pos*/)                 /*!< SCB AHBPCR: EN Mask */
+
+/* L1 Cache Control Register Definitions */
+#define SCB_CACR_FORCEWT_Pos                2U                                            /*!< SCB CACR: FORCEWT Position */
+#define SCB_CACR_FORCEWT_Msk               (1UL << SCB_CACR_FORCEWT_Pos)                  /*!< SCB CACR: FORCEWT Mask */
+
+#define SCB_CACR_ECCEN_Pos                  1U                                            /*!< SCB CACR: ECCEN Position */
+#define SCB_CACR_ECCEN_Msk                 (1UL << SCB_CACR_ECCEN_Pos)                    /*!< SCB CACR: ECCEN Mask */
+
+#define SCB_CACR_SIWT_Pos                   0U                                            /*!< SCB CACR: SIWT Position */
+#define SCB_CACR_SIWT_Msk                  (1UL /*<< SCB_CACR_SIWT_Pos*/)                 /*!< SCB CACR: SIWT Mask */
+
+/* AHBS Control Register Definitions */
+#define SCB_AHBSCR_INITCOUNT_Pos           11U                                            /*!< SCB AHBSCR: INITCOUNT Position */
+#define SCB_AHBSCR_INITCOUNT_Msk           (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos)           /*!< SCB AHBSCR: INITCOUNT Mask */
+
+#define SCB_AHBSCR_TPRI_Pos                 2U                                            /*!< SCB AHBSCR: TPRI Position */
+#define SCB_AHBSCR_TPRI_Msk                (0x1FFUL << SCB_AHBPCR_TPRI_Pos)               /*!< SCB AHBSCR: TPRI Mask */
+
+#define SCB_AHBSCR_CTL_Pos                  0U                                            /*!< SCB AHBSCR: CTL Position*/
+#define SCB_AHBSCR_CTL_Msk                 (3UL /*<< SCB_AHBPCR_CTL_Pos*/)                /*!< SCB AHBSCR: CTL Mask */
+
+/* Auxiliary Bus Fault Status Register Definitions */
+#define SCB_ABFSR_AXIMTYPE_Pos              8U                                            /*!< SCB ABFSR: AXIMTYPE Position*/
+#define SCB_ABFSR_AXIMTYPE_Msk             (3UL << SCB_ABFSR_AXIMTYPE_Pos)                /*!< SCB ABFSR: AXIMTYPE Mask */
+
+#define SCB_ABFSR_EPPB_Pos                  4U                                            /*!< SCB ABFSR: EPPB Position*/
+#define SCB_ABFSR_EPPB_Msk                 (1UL << SCB_ABFSR_EPPB_Pos)                    /*!< SCB ABFSR: EPPB Mask */
+
+#define SCB_ABFSR_AXIM_Pos                  3U                                            /*!< SCB ABFSR: AXIM Position*/
+#define SCB_ABFSR_AXIM_Msk                 (1UL << SCB_ABFSR_AXIM_Pos)                    /*!< SCB ABFSR: AXIM Mask */
+
+#define SCB_ABFSR_AHBP_Pos                  2U                                            /*!< SCB ABFSR: AHBP Position*/
+#define SCB_ABFSR_AHBP_Msk                 (1UL << SCB_ABFSR_AHBP_Pos)                    /*!< SCB ABFSR: AHBP Mask */
+
+#define SCB_ABFSR_DTCM_Pos                  1U                                            /*!< SCB ABFSR: DTCM Position*/
+#define SCB_ABFSR_DTCM_Msk                 (1UL << SCB_ABFSR_DTCM_Pos)                    /*!< SCB ABFSR: DTCM Mask */
+
+#define SCB_ABFSR_ITCM_Pos                  0U                                            /*!< SCB ABFSR: ITCM Position*/
+#define SCB_ABFSR_ITCM_Msk                 (1UL /*<< SCB_ABFSR_ITCM_Pos*/)                /*!< SCB ABFSR: ITCM Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+  \brief    Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+        uint32_t RESERVED0[1U];
+  __IM  uint32_t ICTR;                   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register */
+  __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos         0U                                         /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos    12U                                         /*!< ACTLR: DISITMATBFLUSH Position */
+#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk    (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos)    /*!< ACTLR: DISITMATBFLUSH Mask */
+
+#define SCnSCB_ACTLR_DISRAMODE_Pos         11U                                         /*!< ACTLR: DISRAMODE Position */
+#define SCnSCB_ACTLR_DISRAMODE_Msk         (1UL << SCnSCB_ACTLR_DISRAMODE_Pos)         /*!< ACTLR: DISRAMODE Mask */
+
+#define SCnSCB_ACTLR_FPEXCODIS_Pos         10U                                         /*!< ACTLR: FPEXCODIS Position */
+#define SCnSCB_ACTLR_FPEXCODIS_Msk         (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos)         /*!< ACTLR: FPEXCODIS Mask */
+
+#define SCnSCB_ACTLR_DISFOLD_Pos            2U                                         /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Msk           (1UL << SCnSCB_ACTLR_DISFOLD_Pos)           /*!< ACTLR: DISFOLD Mask */
+
+#define SCnSCB_ACTLR_DISMCYCINT_Pos         0U                                         /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/)    /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
+  \brief    Type definitions for the Instrumentation Trace Macrocell (ITM)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+  __OM  union
+  {
+    __OM  uint8_t    u8;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */
+    __OM  uint16_t   u16;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */
+    __OM  uint32_t   u32;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */
+  }  PORT [32U];                         /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers */
+        uint32_t RESERVED0[864U];
+  __IOM uint32_t TER;                    /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register */
+        uint32_t RESERVED1[15U];
+  __IOM uint32_t TPR;                    /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */
+        uint32_t RESERVED2[15U];
+  __IOM uint32_t TCR;                    /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */
+        uint32_t RESERVED3[29U];
+  __OM  uint32_t IWR;                    /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register */
+  __IM  uint32_t IRR;                    /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register */
+  __IOM uint32_t IMCR;                   /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register */
+        uint32_t RESERVED4[43U];
+  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register */
+  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register */
+        uint32_t RESERVED5[6U];
+  __IM  uint32_t PID4;                   /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
+  __IM  uint32_t PID5;                   /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
+  __IM  uint32_t PID6;                   /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
+  __IM  uint32_t PID7;                   /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
+  __IM  uint32_t PID0;                   /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
+  __IM  uint32_t PID1;                   /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
+  __IM  uint32_t PID2;                   /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
+  __IM  uint32_t PID3;                   /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
+  __IM  uint32_t CID0;                   /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
+  __IM  uint32_t CID1;                   /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
+  __IM  uint32_t CID2;                   /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
+  __IM  uint32_t CID3;                   /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos                0U                                            /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk               (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/)     /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos                   23U                                            /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos             16U                                            /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos                10U                                            /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos              8U                                            /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos                  4U                                            /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos                  3U                                            /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos                 2U                                            /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos                   1U                                            /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos                  0U                                            /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos                0U                                            /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk               (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)              /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos                0U                                            /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk               (1UL /*<< ITM_IRR_ATREADYM_Pos*/)              /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos            0U                                            /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk           (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)          /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos                 2U                                            /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos                  1U                                            /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos                 0U                                            /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
+  \brief    Type definitions for the Data Watchpoint and Trace (DWT)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */
+  __IOM uint32_t CYCCNT;                 /*!< Offset: 0x004 (R/W)  Cycle Count Register */
+  __IOM uint32_t CPICNT;                 /*!< Offset: 0x008 (R/W)  CPI Count Register */
+  __IOM uint32_t EXCCNT;                 /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register */
+  __IOM uint32_t SLEEPCNT;               /*!< Offset: 0x010 (R/W)  Sleep Count Register */
+  __IOM uint32_t LSUCNT;                 /*!< Offset: 0x014 (R/W)  LSU Count Register */
+  __IOM uint32_t FOLDCNT;                /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register */
+  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */
+  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */
+  __IOM uint32_t MASK0;                  /*!< Offset: 0x024 (R/W)  Mask Register 0 */
+  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */
+        uint32_t RESERVED0[1U];
+  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */
+  __IOM uint32_t MASK1;                  /*!< Offset: 0x034 (R/W)  Mask Register 1 */
+  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */
+        uint32_t RESERVED1[1U];
+  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */
+  __IOM uint32_t MASK2;                  /*!< Offset: 0x044 (R/W)  Mask Register 2 */
+  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */
+        uint32_t RESERVED2[1U];
+  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */
+  __IOM uint32_t MASK3;                  /*!< Offset: 0x054 (R/W)  Mask Register 3 */
+  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */
+        uint32_t RESERVED3[981U];
+  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 (  W)  Lock Access Register */
+  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R  )  Lock Status Register */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos             22U                                         /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos            21U                                         /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos             20U                                         /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos           19U                                         /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos             18U                                         /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos             17U                                         /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos             16U                                         /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos            12U                                         /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos               10U                                         /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos                 9U                                         /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos               5U                                         /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos             1U                                         /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos              0U                                         /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos               0U                                         /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos               0U                                         /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos           0U                                         /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos               0U                                         /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos             0U                                         /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos                   0U                                         /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk                  (0x1FUL /*<< DWT_MASK_MASK_Pos*/)           /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos        16U                                         /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos        12U                                         /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos            9U                                         /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos         8U                                         /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos           7U                                         /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos          5U                                         /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos           0U                                         /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/)    /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_TPI     Trace Port Interface (TPI)
+  \brief    Type definitions for the Trace Port Interface (TPI)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+  __IM  uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */
+  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
+        uint32_t RESERVED0[2U];
+  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
+        uint32_t RESERVED1[55U];
+  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
+        uint32_t RESERVED2[131U];
+  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
+  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
+  __IM  uint32_t FSCR;                   /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
+        uint32_t RESERVED3[759U];
+  __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER Register */
+  __IM  uint32_t FIFO0;                  /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
+  __IM  uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
+        uint32_t RESERVED4[1U];
+  __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
+  __IM  uint32_t FIFO1;                  /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
+  __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
+        uint32_t RESERVED5[39U];
+  __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */
+  __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
+        uint32_t RESERVED7[8U];
+  __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
+  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos                 16U                                         /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos                  8U                                         /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos                  0U                                         /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk                 (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)          /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY2_Pos          0U                                         /*!< TPI ITATBCTR2: ATREADY2 Position */
+#define TPI_ITATBCTR2_ATREADY2_Msk         (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/)   /*!< TPI ITATBCTR2: ATREADY2 Mask */
+
+#define TPI_ITATBCTR2_ATREADY1_Pos          0U                                         /*!< TPI ITATBCTR2: ATREADY1 Position */
+#define TPI_ITATBCTR2_ATREADY1_Msk         (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/)   /*!< TPI ITATBCTR2: ATREADY1 Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos                 16U                                         /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos                  8U                                         /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos                  0U                                         /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk                 (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)          /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY2_Pos          0U                                         /*!< TPI ITATBCTR0: ATREADY2 Position */
+#define TPI_ITATBCTR0_ATREADY2_Msk         (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/)   /*!< TPI ITATBCTR0: ATREADY2 Mask */
+
+#define TPI_ITATBCTR0_ATREADY1_Pos          0U                                         /*!< TPI ITATBCTR0: ATREADY1 Position */
+#define TPI_ITATBCTR0_ATREADY1_Msk         (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/)   /*!< TPI ITATBCTR0: ATREADY1 Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk                (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos              6U                                         /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos             5U                                         /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos             4U                                         /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos           0U                                         /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+  \brief    Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
+  __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */
+  __IOM uint32_t RBAR_A1;                /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register */
+  __IOM uint32_t RASR_A1;                /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */
+  __IOM uint32_t RBAR_A2;                /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register */
+  __IOM uint32_t RASR_A2;                /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */
+  __IOM uint32_t RBAR_A3;                /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register */
+  __IOM uint32_t RASR_A3;                /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+#define MPU_TYPE_RALIASES                  4U
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos                   5U                                            /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos                    28U                                            /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos                    24U                                            /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos                     18U                                            /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos                     17U                                            /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos                     16U                                            /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_FPU     Floating Point Unit (FPU)
+  \brief    Type definitions for the Floating Point Unit (FPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Floating Point Unit (FPU).
+ */
+typedef struct
+{
+        uint32_t RESERVED0[1U];
+  __IOM uint32_t FPCCR;                  /*!< Offset: 0x004 (R/W)  Floating-Point Context Control Register */
+  __IOM uint32_t FPCAR;                  /*!< Offset: 0x008 (R/W)  Floating-Point Context Address Register */
+  __IOM uint32_t FPDSCR;                 /*!< Offset: 0x00C (R/W)  Floating-Point Default Status Control Register */
+  __IM  uint32_t MVFR0;                  /*!< Offset: 0x010 (R/ )  Media and FP Feature Register 0 */
+  __IM  uint32_t MVFR1;                  /*!< Offset: 0x014 (R/ )  Media and FP Feature Register 1 */
+  __IM  uint32_t MVFR2;                  /*!< Offset: 0x018 (R/ )  Media and FP Feature Register 2 */
+} FPU_Type;
+
+/* Floating-Point Context Control Register Definitions */
+#define FPU_FPCCR_ASPEN_Pos                31U                                            /*!< FPCCR: ASPEN bit Position */
+#define FPU_FPCCR_ASPEN_Msk                (1UL << FPU_FPCCR_ASPEN_Pos)                   /*!< FPCCR: ASPEN bit Mask */
+
+#define FPU_FPCCR_LSPEN_Pos                30U                                            /*!< FPCCR: LSPEN Position */
+#define FPU_FPCCR_LSPEN_Msk                (1UL << FPU_FPCCR_LSPEN_Pos)                   /*!< FPCCR: LSPEN bit Mask */
+
+#define FPU_FPCCR_MONRDY_Pos                8U                                            /*!< FPCCR: MONRDY Position */
+#define FPU_FPCCR_MONRDY_Msk               (1UL << FPU_FPCCR_MONRDY_Pos)                  /*!< FPCCR: MONRDY bit Mask */
+
+#define FPU_FPCCR_BFRDY_Pos                 6U                                            /*!< FPCCR: BFRDY Position */
+#define FPU_FPCCR_BFRDY_Msk                (1UL << FPU_FPCCR_BFRDY_Pos)                   /*!< FPCCR: BFRDY bit Mask */
+
+#define FPU_FPCCR_MMRDY_Pos                 5U                                            /*!< FPCCR: MMRDY Position */
+#define FPU_FPCCR_MMRDY_Msk                (1UL << FPU_FPCCR_MMRDY_Pos)                   /*!< FPCCR: MMRDY bit Mask */
+
+#define FPU_FPCCR_HFRDY_Pos                 4U                                            /*!< FPCCR: HFRDY Position */
+#define FPU_FPCCR_HFRDY_Msk                (1UL << FPU_FPCCR_HFRDY_Pos)                   /*!< FPCCR: HFRDY bit Mask */
+
+#define FPU_FPCCR_THREAD_Pos                3U                                            /*!< FPCCR: processor mode bit Position */
+#define FPU_FPCCR_THREAD_Msk               (1UL << FPU_FPCCR_THREAD_Pos)                  /*!< FPCCR: processor mode active bit Mask */
+
+#define FPU_FPCCR_USER_Pos                  1U                                            /*!< FPCCR: privilege level bit Position */
+#define FPU_FPCCR_USER_Msk                 (1UL << FPU_FPCCR_USER_Pos)                    /*!< FPCCR: privilege level bit Mask */
+
+#define FPU_FPCCR_LSPACT_Pos                0U                                            /*!< FPCCR: Lazy state preservation active bit Position */
+#define FPU_FPCCR_LSPACT_Msk               (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)              /*!< FPCCR: Lazy state preservation active bit Mask */
+
+/* Floating-Point Context Address Register Definitions */
+#define FPU_FPCAR_ADDRESS_Pos               3U                                            /*!< FPCAR: ADDRESS bit Position */
+#define FPU_FPCAR_ADDRESS_Msk              (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)        /*!< FPCAR: ADDRESS bit Mask */
+
+/* Floating-Point Default Status Control Register Definitions */
+#define FPU_FPDSCR_AHP_Pos                 26U                                            /*!< FPDSCR: AHP bit Position */
+#define FPU_FPDSCR_AHP_Msk                 (1UL << FPU_FPDSCR_AHP_Pos)                    /*!< FPDSCR: AHP bit Mask */
+
+#define FPU_FPDSCR_DN_Pos                  25U                                            /*!< FPDSCR: DN bit Position */
+#define FPU_FPDSCR_DN_Msk                  (1UL << FPU_FPDSCR_DN_Pos)                     /*!< FPDSCR: DN bit Mask */
+
+#define FPU_FPDSCR_FZ_Pos                  24U                                            /*!< FPDSCR: FZ bit Position */
+#define FPU_FPDSCR_FZ_Msk                  (1UL << FPU_FPDSCR_FZ_Pos)                     /*!< FPDSCR: FZ bit Mask */
+
+#define FPU_FPDSCR_RMode_Pos               22U                                            /*!< FPDSCR: RMode bit Position */
+#define FPU_FPDSCR_RMode_Msk               (3UL << FPU_FPDSCR_RMode_Pos)                  /*!< FPDSCR: RMode bit Mask */
+
+/* Media and FP Feature Register 0 Definitions */
+#define FPU_MVFR0_FP_rounding_modes_Pos    28U                                            /*!< MVFR0: FP rounding modes bits Position */
+#define FPU_MVFR0_FP_rounding_modes_Msk    (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)     /*!< MVFR0: FP rounding modes bits Mask */
+
+#define FPU_MVFR0_Short_vectors_Pos        24U                                            /*!< MVFR0: Short vectors bits Position */
+#define FPU_MVFR0_Short_vectors_Msk        (0xFUL << FPU_MVFR0_Short_vectors_Pos)         /*!< MVFR0: Short vectors bits Mask */
+
+#define FPU_MVFR0_Square_root_Pos          20U                                            /*!< MVFR0: Square root bits Position */
+#define FPU_MVFR0_Square_root_Msk          (0xFUL << FPU_MVFR0_Square_root_Pos)           /*!< MVFR0: Square root bits Mask */
+
+#define FPU_MVFR0_Divide_Pos               16U                                            /*!< MVFR0: Divide bits Position */
+#define FPU_MVFR0_Divide_Msk               (0xFUL << FPU_MVFR0_Divide_Pos)                /*!< MVFR0: Divide bits Mask */
+
+#define FPU_MVFR0_FP_excep_trapping_Pos    12U                                            /*!< MVFR0: FP exception trapping bits Position */
+#define FPU_MVFR0_FP_excep_trapping_Msk    (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)     /*!< MVFR0: FP exception trapping bits Mask */
+
+#define FPU_MVFR0_Double_precision_Pos      8U                                            /*!< MVFR0: Double-precision bits Position */
+#define FPU_MVFR0_Double_precision_Msk     (0xFUL << FPU_MVFR0_Double_precision_Pos)      /*!< MVFR0: Double-precision bits Mask */
+
+#define FPU_MVFR0_Single_precision_Pos      4U                                            /*!< MVFR0: Single-precision bits Position */
+#define FPU_MVFR0_Single_precision_Msk     (0xFUL << FPU_MVFR0_Single_precision_Pos)      /*!< MVFR0: Single-precision bits Mask */
+
+#define FPU_MVFR0_A_SIMD_registers_Pos      0U                                            /*!< MVFR0: A_SIMD registers bits Position */
+#define FPU_MVFR0_A_SIMD_registers_Msk     (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)  /*!< MVFR0: A_SIMD registers bits Mask */
+
+/* Media and FP Feature Register 1 Definitions */
+#define FPU_MVFR1_FP_fused_MAC_Pos         28U                                            /*!< MVFR1: FP fused MAC bits Position */
+#define FPU_MVFR1_FP_fused_MAC_Msk         (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)          /*!< MVFR1: FP fused MAC bits Mask */
+
+#define FPU_MVFR1_FP_HPFP_Pos              24U                                            /*!< MVFR1: FP HPFP bits Position */
+#define FPU_MVFR1_FP_HPFP_Msk              (0xFUL << FPU_MVFR1_FP_HPFP_Pos)               /*!< MVFR1: FP HPFP bits Mask */
+
+#define FPU_MVFR1_D_NaN_mode_Pos            4U                                            /*!< MVFR1: D_NaN mode bits Position */
+#define FPU_MVFR1_D_NaN_mode_Msk           (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)            /*!< MVFR1: D_NaN mode bits Mask */
+
+#define FPU_MVFR1_FtZ_mode_Pos              0U                                            /*!< MVFR1: FtZ mode bits Position */
+#define FPU_MVFR1_FtZ_mode_Msk             (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)          /*!< MVFR1: FtZ mode bits Mask */
+
+/* Media and FP Feature Register 2 Definitions */
+
+/*@} end of group CMSIS_FPU */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    Type definitions for the Core Debug Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */
+  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */
+  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */
+  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5U                                            /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos         24U                                            /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos        19U                                            /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos       18U                                            /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos       17U                                            /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos         16U                                            /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos       9U                                            /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos       8U                                            /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos      7U                                            /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos       6U                                            /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5U                                            /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos        4U                                            /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
+#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address */
+#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address */
+#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address */
+#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
+
+#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */
+#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct */
+#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct */
+#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct */
+#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit */
+  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit */
+#endif
+
+#define FPU_BASE            (SCS_BASE +  0x0F30UL)                    /*!< Floating Point Unit */
+#define FPU                 ((FPU_Type       *)     FPU_BASE      )   /*!< Floating Point Unit */
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Debug Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+  #endif
+  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
+  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
+  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
+  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
+  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
+  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+  #define NVIC_GetActive              __NVIC_GetActive
+  #define NVIC_SetPriority            __NVIC_SetPriority
+  #define NVIC_GetPriority            __NVIC_GetPriority
+  #define NVIC_SystemReset            __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+  #endif
+  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetVector              __NVIC_SetVector
+  #define NVIC_GetVector              __NVIC_GetVector
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET          16
+
+
+/* The following EXC_RETURN values are saved the LR on exception entry */
+#define EXC_RETURN_HANDLER         (0xFFFFFFF1UL)     /* return to Handler mode, uses MSP after return                               */
+#define EXC_RETURN_THREAD_MSP      (0xFFFFFFF9UL)     /* return to Thread mode, uses MSP after return                                */
+#define EXC_RETURN_THREAD_PSP      (0xFFFFFFFDUL)     /* return to Thread mode, uses PSP after return                                */
+#define EXC_RETURN_HANDLER_FPU     (0xFFFFFFE1UL)     /* return to Handler mode, uses MSP after return, restore floating-point state */
+#define EXC_RETURN_THREAD_MSP_FPU  (0xFFFFFFE9UL)     /* return to Thread mode, uses MSP after return, restore floating-point state  */
+#define EXC_RETURN_THREAD_PSP_FPU  (0xFFFFFFEDUL)     /* return to Thread mode, uses PSP after return, restore floating-point state  */
+
+
+/**
+  \brief   Set Priority Grouping
+  \details Sets the priority grouping field using the required unlock sequence.
+           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+           Only values from 0..7 are used.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]      PriorityGroup  Priority grouping field.
+ */
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+  uint32_t reg_value;
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
+
+  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
+  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */
+  reg_value  =  (reg_value                                   |
+                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos)  );              /* Insert write key and priority group */
+  SCB->AIRCR =  reg_value;
+}
+
+
+/**
+  \brief   Get Priority Grouping
+  \details Reads the priority grouping field from the NVIC Interrupt Controller.
+  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
+{
+  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+  \brief   Enable Interrupt
+  \details Enables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt
+  \details Disables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+    __DSB();
+    __ISB();
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Active Interrupt
+  \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not active.
+  \return             1  Interrupt status is active.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->IP[((uint32_t)IRQn)]                = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+  else
+  {
+    SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return(((uint32_t)NVIC->IP[((uint32_t)IRQn)]                >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+
+
+/**
+  \brief   Encode Priority
+  \details Encodes the priority for an interrupt with the given priority group,
+           preemptive priority value, and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]     PriorityGroup  Used priority group.
+  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+  \param [in]       SubPriority  Subpriority value (starting from 0).
+  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  return (
+           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
+         );
+}
+
+
+/**
+  \brief   Decode Priority
+  \details Decodes an interrupt priority value with a given priority group to
+           preemptive priority value and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+  \param [in]     PriorityGroup  Used priority group.
+  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+  \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
+}
+
+
+/**
+  \brief   Set Interrupt Vector
+  \details Sets an interrupt vector in SRAM based interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+           VTOR must been relocated to SRAM before.
+  \param [in]   IRQn      Interrupt number
+  \param [in]   vector    Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+  \brief   Get Interrupt Vector
+  \details Reads an interrupt vector from interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn      Interrupt number.
+  \return                 Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+  __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
+                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */
+  __DSB();                                                          /* Ensure completion of memory access */
+
+  for(;;)                                                           /* wait until reset */
+  {
+    __NOP();
+  }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+/* ##########################  MPU functions  #################################### */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+
+#include "mpu_armv7.h"
+
+#endif
+
+/* ##########################  FPU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions
+  \brief    Function that provides FPU type.
+  @{
+ */
+
+/**
+  \brief   get FPU type
+  \details returns the FPU type
+  \returns
+   - \b  0: No FPU
+   - \b  1: Single precision FPU
+   - \b  2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+  uint32_t mvfr0;
+
+  mvfr0 = SCB->MVFR0;
+  if      ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U)
+  {
+    return 2U;           /* Double + Single precision FPU */
+  }
+  else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)
+  {
+    return 1U;           /* Single precision FPU */
+  }
+  else
+  {
+    return 0U;           /* No FPU */
+  }
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ##########################  Cache functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_CacheFunctions Cache Functions
+  \brief    Functions that configure Instruction and Data cache.
+  @{
+ */
+
+/* Cache Size ID Register Macros */
+#define CCSIDR_WAYS(x)         (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos)
+#define CCSIDR_SETS(x)         (((x) & SCB_CCSIDR_NUMSETS_Msk      ) >> SCB_CCSIDR_NUMSETS_Pos      )
+
+
+/**
+  \brief   Enable I-Cache
+  \details Turns on I-Cache
+  */
+__STATIC_INLINE void SCB_EnableICache (void)
+{
+  #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
+    __DSB();
+    __ISB();
+    SCB->ICIALLU = 0UL;                     /* invalidate I-Cache */
+    __DSB();
+    __ISB();
+    SCB->CCR |=  (uint32_t)SCB_CCR_IC_Msk;  /* enable I-Cache */
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/**
+  \brief   Disable I-Cache
+  \details Turns off I-Cache
+  */
+__STATIC_INLINE void SCB_DisableICache (void)
+{
+  #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
+    __DSB();
+    __ISB();
+    SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk;  /* disable I-Cache */
+    SCB->ICIALLU = 0UL;                     /* invalidate I-Cache */
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/**
+  \brief   Invalidate I-Cache
+  \details Invalidates I-Cache
+  */
+__STATIC_INLINE void SCB_InvalidateICache (void)
+{
+  #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
+    __DSB();
+    __ISB();
+    SCB->ICIALLU = 0UL;
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/**
+  \brief   Enable D-Cache
+  \details Turns on D-Cache
+  */
+__STATIC_INLINE void SCB_EnableDCache (void)
+{
+  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+    uint32_t ccsidr;
+    uint32_t sets;
+    uint32_t ways;
+
+    SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/  /* Level 1 data cache */
+    __DSB();
+
+    ccsidr = SCB->CCSIDR;
+
+                                            /* invalidate D-Cache */
+    sets = (uint32_t)(CCSIDR_SETS(ccsidr));
+    do {
+      ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
+      do {
+        SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |
+                      ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk)  );
+        #if defined ( __CC_ARM )
+          __schedule_barrier();
+        #endif
+      } while (ways-- != 0U);
+    } while(sets-- != 0U);
+    __DSB();
+
+    SCB->CCR |=  (uint32_t)SCB_CCR_DC_Msk;  /* enable D-Cache */
+
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/**
+  \brief   Disable D-Cache
+  \details Turns off D-Cache
+  */
+__STATIC_INLINE void SCB_DisableDCache (void)
+{
+  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+    uint32_t ccsidr;
+    uint32_t sets;
+    uint32_t ways;
+
+    SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/  /* Level 1 data cache */
+    __DSB();
+
+    SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk;  /* disable D-Cache */
+    __DSB();
+
+    ccsidr = SCB->CCSIDR;
+
+                                            /* clean & invalidate D-Cache */
+    sets = (uint32_t)(CCSIDR_SETS(ccsidr));
+    do {
+      ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
+      do {
+        SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |
+                       ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk)  );
+        #if defined ( __CC_ARM )
+          __schedule_barrier();
+        #endif
+      } while (ways-- != 0U);
+    } while(sets-- != 0U);
+
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/**
+  \brief   Invalidate D-Cache
+  \details Invalidates D-Cache
+  */
+__STATIC_INLINE void SCB_InvalidateDCache (void)
+{
+  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+    uint32_t ccsidr;
+    uint32_t sets;
+    uint32_t ways;
+
+    SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/  /* Level 1 data cache */
+    __DSB();
+
+    ccsidr = SCB->CCSIDR;
+
+                                            /* invalidate D-Cache */
+    sets = (uint32_t)(CCSIDR_SETS(ccsidr));
+    do {
+      ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
+      do {
+        SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |
+                      ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk)  );
+        #if defined ( __CC_ARM )
+          __schedule_barrier();
+        #endif
+      } while (ways-- != 0U);
+    } while(sets-- != 0U);
+
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/**
+  \brief   Clean D-Cache
+  \details Cleans D-Cache
+  */
+__STATIC_INLINE void SCB_CleanDCache (void)
+{
+  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+    uint32_t ccsidr;
+    uint32_t sets;
+    uint32_t ways;
+
+     SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/  /* Level 1 data cache */
+   __DSB();
+
+    ccsidr = SCB->CCSIDR;
+
+                                            /* clean D-Cache */
+    sets = (uint32_t)(CCSIDR_SETS(ccsidr));
+    do {
+      ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
+      do {
+        SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) |
+                      ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk)  );
+        #if defined ( __CC_ARM )
+          __schedule_barrier();
+        #endif
+      } while (ways-- != 0U);
+    } while(sets-- != 0U);
+
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/**
+  \brief   Clean & Invalidate D-Cache
+  \details Cleans and Invalidates D-Cache
+  */
+__STATIC_INLINE void SCB_CleanInvalidateDCache (void)
+{
+  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+    uint32_t ccsidr;
+    uint32_t sets;
+    uint32_t ways;
+
+    SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/  /* Level 1 data cache */
+    __DSB();
+
+    ccsidr = SCB->CCSIDR;
+
+                                            /* clean & invalidate D-Cache */
+    sets = (uint32_t)(CCSIDR_SETS(ccsidr));
+    do {
+      ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
+      do {
+        SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |
+                       ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk)  );
+        #if defined ( __CC_ARM )
+          __schedule_barrier();
+        #endif
+      } while (ways-- != 0U);
+    } while(sets-- != 0U);
+
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/**
+  \brief   D-Cache Invalidate by address
+  \details Invalidates D-Cache for the given address
+  \param[in]   addr    address (aligned to 32-byte boundary)
+  \param[in]   dsize   size of memory block (in number of bytes)
+*/
+__STATIC_INLINE void SCB_InvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)
+{
+  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+     int32_t op_size = dsize;
+    uint32_t op_addr = (uint32_t)addr;
+     int32_t linesize = 32;                /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */
+
+    __DSB();
+
+    while (op_size > 0) {
+      SCB->DCIMVAC = op_addr;
+      op_addr += (uint32_t)linesize;
+      op_size -=           linesize;
+    }
+
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/**
+  \brief   D-Cache Clean by address
+  \details Cleans D-Cache for the given address
+  \param[in]   addr    address (aligned to 32-byte boundary)
+  \param[in]   dsize   size of memory block (in number of bytes)
+*/
+__STATIC_INLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize)
+{
+  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+     int32_t op_size = dsize;
+    uint32_t op_addr = (uint32_t) addr;
+     int32_t linesize = 32;                /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */
+
+    __DSB();
+
+    while (op_size > 0) {
+      SCB->DCCMVAC = op_addr;
+      op_addr += (uint32_t)linesize;
+      op_size -=           linesize;
+    }
+
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/**
+  \brief   D-Cache Clean and Invalidate by address
+  \details Cleans and invalidates D_Cache for the given address
+  \param[in]   addr    address (aligned to 32-byte boundary)
+  \param[in]   dsize   size of memory block (in number of bytes)
+*/
+__STATIC_INLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)
+{
+  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+     int32_t op_size = dsize;
+    uint32_t op_addr = (uint32_t) addr;
+     int32_t linesize = 32;                /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */
+
+    __DSB();
+
+    while (op_size > 0) {
+      SCB->DCCIMVAC = op_addr;
+      op_addr += (uint32_t)linesize;
+      op_size -=           linesize;
+    }
+
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/*@} end of CMSIS_Core_CacheFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                   /* Reload value impossible */
+  }
+
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                     /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_core_DebugFunctions ITM Functions
+  \brief    Functions that access the ITM debug interface.
+  @{
+ */
+
+extern volatile int32_t ITM_RxBuffer;                              /*!< External variable to receive characters. */
+#define                 ITM_RXBUFFER_EMPTY  ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/**
+  \brief   ITM Send Character
+  \details Transmits a character via the ITM channel 0, and
+           \li Just returns when no debugger is connected that has booked the output.
+           \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+  \param [in]     ch  Character to transmit.
+  \returns            Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */
+      ((ITM->TER & 1UL               ) != 0UL)   )     /* ITM Port #0 enabled */
+  {
+    while (ITM->PORT[0U].u32 == 0UL)
+    {
+      __NOP();
+    }
+    ITM->PORT[0U].u8 = (uint8_t)ch;
+  }
+  return (ch);
+}
+
+
+/**
+  \brief   ITM Receive Character
+  \details Inputs a character via the external variable \ref ITM_RxBuffer.
+  \return             Received character.
+  \return         -1  No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)
+{
+  int32_t ch = -1;                           /* no character available */
+
+  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
+  {
+    ch = ITM_RxBuffer;
+    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
+  }
+
+  return (ch);
+}
+
+
+/**
+  \brief   ITM Check Character
+  \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+  \return          0  No character available.
+  \return          1  Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void)
+{
+
+  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
+  {
+    return (0);                              /* no character available */
+  }
+  else
+  {
+    return (1);                              /*    character available */
+  }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM7_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/Drivers/CMSIS/Include/core_sc000.h b/Drivers/CMSIS/Include/core_sc000.h
new file mode 100644
index 0000000..9086c64
--- /dev/null
+++ b/Drivers/CMSIS/Include/core_sc000.h
@@ -0,0 +1,1022 @@
+/**************************************************************************//**
+ * @file     core_sc000.h
+ * @brief    CMSIS SC000 Core Peripheral Access Layer Header File
+ * @version  V5.0.5
+ * @date     28. May 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_SC000_H_GENERIC
+#define __CORE_SC000_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup SC000
+  @{
+ */
+
+#include "cmsis_version.h"
+
+/*  CMSIS SC000 definitions */
+#define __SC000_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)                /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __SC000_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)                 /*!< \deprecated [15:0]  CMSIS HAL sub version */
+#define __SC000_CMSIS_VERSION       ((__SC000_CMSIS_VERSION_MAIN << 16U) | \
+                                      __SC000_CMSIS_VERSION_SUB           )  /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_SC                 (000U)                                   /*!< Cortex secure core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    This core does not support an FPU at all
+*/
+#define __FPU_USED       0U
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #if defined __ARM_PCS_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TI_ARM__ )
+  #if defined __TI_VFP_SUPPORT__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __CSMC__ )
+  #if ( __CSMC__ & 0x400U)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#endif
+
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_SC000_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_SC000_H_DEPENDANT
+#define __CORE_SC000_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __SC000_REV
+    #define __SC000_REV             0x0000U
+    #warning "__SC000_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0U
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          2U
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0U
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group SC000 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core MPU Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:28;              /*!< bit:  0..27  Reserved */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */
+    uint32_t _reserved1:3;               /*!< bit: 25..27  Reserved */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:1;               /*!< bit:      0  Reserved */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */
+    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IOM uint32_t ISER[1U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+        uint32_t RESERVED0[31U];
+  __IOM uint32_t ICER[1U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+        uint32_t RSERVED1[31U];
+  __IOM uint32_t ISPR[1U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+        uint32_t RESERVED2[31U];
+  __IOM uint32_t ICPR[1U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+        uint32_t RESERVED3[31U];
+        uint32_t RESERVED4[64U];
+  __IOM uint32_t IP[8U];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register */
+}  NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
+  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+        uint32_t RESERVED0[1U];
+  __IOM uint32_t SHP[2U];                /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED */
+  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+        uint32_t RESERVED1[154U];
+  __IOM uint32_t SFCR;                   /*!< Offset: 0x290 (R/W)  Security Features Control Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+  \brief    Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+        uint32_t RESERVED0[2U];
+  __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */
+} SCnSCB_Type;
+
+/* Auxiliary Control Register Definitions */
+#define SCnSCB_ACTLR_DISMCYCINT_Pos         0U                                         /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/)    /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+  \brief    Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
+  __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos                   8U                                            /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0xFFFFFFUL << MPU_RBAR_ADDR_Pos)              /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos                    28U                                            /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos                    24U                                            /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos                     18U                                            /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos                     17U                                            /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos                     16U                                            /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
+            Therefore they are not covered by the SC000 header file.
+  @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
+
+#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit */
+  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+  #endif
+  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+/*#define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping   not available for SC000 */
+/*#define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping   not available for SC000 */
+  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
+  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
+  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
+  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+/*#define NVIC_GetActive              __NVIC_GetActive             not available for SC000 */
+  #define NVIC_SetPriority            __NVIC_SetPriority
+  #define NVIC_GetPriority            __NVIC_GetPriority
+  #define NVIC_SystemReset            __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+  #endif
+  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetVector              __NVIC_SetVector
+  #define NVIC_GetVector              __NVIC_GetVector
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET          16
+
+
+/* The following EXC_RETURN values are saved the LR on exception entry */
+#define EXC_RETURN_HANDLER         (0xFFFFFFF1UL)     /* return to Handler mode, uses MSP after return                               */
+#define EXC_RETURN_THREAD_MSP      (0xFFFFFFF9UL)     /* return to Thread mode, uses MSP after return                                */
+#define EXC_RETURN_THREAD_PSP      (0xFFFFFFFDUL)     /* return to Thread mode, uses PSP after return                                */
+
+
+/* Interrupt Priorities are WORD accessible only under Armv6-M                  */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)
+#define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )
+#define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )
+
+
+/**
+  \brief   Enable Interrupt
+  \details Enables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt
+  \details Disables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+    __DSB();
+    __ISB();
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->IP[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+  else
+  {
+    SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Vector
+  \details Sets an interrupt vector in SRAM based interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+           VTOR must been relocated to SRAM before.
+  \param [in]   IRQn      Interrupt number
+  \param [in]   vector    Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+  \brief   Get Interrupt Vector
+  \details Reads an interrupt vector from interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn      Interrupt number.
+  \return                 Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+  __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+  SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                 SCB_AIRCR_SYSRESETREQ_Msk);
+  __DSB();                                                          /* Ensure completion of memory access */
+
+  for(;;)                                                           /* wait until reset */
+  {
+    __NOP();
+  }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+/* ##########################  FPU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions
+  \brief    Function that provides FPU type.
+  @{
+ */
+
+/**
+  \brief   get FPU type
+  \details returns the FPU type
+  \returns
+   - \b  0: No FPU
+   - \b  1: Single precision FPU
+   - \b  2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+    return 0U;           /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                   /* Reload value impossible */
+  }
+
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                     /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_SC000_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/Drivers/CMSIS/Include/core_sc300.h b/Drivers/CMSIS/Include/core_sc300.h
new file mode 100644
index 0000000..665822d
--- /dev/null
+++ b/Drivers/CMSIS/Include/core_sc300.h
@@ -0,0 +1,1915 @@
+/**************************************************************************//**
+ * @file     core_sc300.h
+ * @brief    CMSIS SC300 Core Peripheral Access Layer Header File
+ * @version  V5.0.6
+ * @date     04. June 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_SC300_H_GENERIC
+#define __CORE_SC300_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup SC3000
+  @{
+ */
+
+#include "cmsis_version.h"
+
+/*  CMSIS SC300 definitions */
+#define __SC300_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)                /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __SC300_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)                 /*!< \deprecated [15:0]  CMSIS HAL sub version */
+#define __SC300_CMSIS_VERSION       ((__SC300_CMSIS_VERSION_MAIN << 16U) | \
+                                      __SC300_CMSIS_VERSION_SUB           )  /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_SC                 (300U)                                   /*!< Cortex secure core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    This core does not support an FPU at all
+*/
+#define __FPU_USED       0U
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #if defined __ARM_PCS_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TI_ARM__ )
+  #if defined __TI_VFP_SUPPORT__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __CSMC__ )
+  #if ( __CSMC__ & 0x400U)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#endif
+
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_SC300_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_SC300_H_DEPENDANT
+#define __CORE_SC300_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __SC300_REV
+    #define __SC300_REV               0x0000U
+    #warning "__SC300_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0U
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          3U
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0U
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group SC300 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core Debug Register
+  - Core MPU Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+#define APSR_Q_Pos                         27U                                            /*!< APSR: Q Position */
+#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */
+
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:1;               /*!< bit:      9  Reserved */
+    uint32_t ICI_IT_1:6;                 /*!< bit: 10..15  ICI/IT part 1 */
+    uint32_t _reserved1:8;               /*!< bit: 16..23  Reserved */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit */
+    uint32_t ICI_IT_2:2;                 /*!< bit: 25..26  ICI/IT part 2 */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos                         27U                                            /*!< xPSR: Q Position */
+#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */
+
+#define xPSR_ICI_IT_2_Pos                  25U                                            /*!< xPSR: ICI/IT part 2 Position */
+#define xPSR_ICI_IT_2_Msk                  (3UL << xPSR_ICI_IT_2_Pos)                     /*!< xPSR: ICI/IT part 2 Mask */
+
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_ICI_IT_1_Pos                  10U                                            /*!< xPSR: ICI/IT part 1 Position */
+#define xPSR_ICI_IT_1_Msk                  (0x3FUL << xPSR_ICI_IT_1_Pos)                  /*!< xPSR: ICI/IT part 1 Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */
+    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IOM uint32_t ISER[8U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+        uint32_t RESERVED0[24U];
+  __IOM uint32_t ICER[8U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+        uint32_t RSERVED1[24U];
+  __IOM uint32_t ISPR[8U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+        uint32_t RESERVED2[24U];
+  __IOM uint32_t ICPR[8U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+        uint32_t RESERVED3[24U];
+  __IOM uint32_t IABR[8U];               /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */
+        uint32_t RESERVED4[56U];
+  __IOM uint8_t  IP[240U];               /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
+        uint32_t RESERVED5[644U];
+  __OM  uint32_t STIR;                   /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register */
+}  NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos                 0U                                         /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
+  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+  __IOM uint8_t  SHP[12U];               /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
+  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+  __IOM uint32_t CFSR;                   /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register */
+  __IOM uint32_t HFSR;                   /*!< Offset: 0x02C (R/W)  HardFault Status Register */
+  __IOM uint32_t DFSR;                   /*!< Offset: 0x030 (R/W)  Debug Fault Status Register */
+  __IOM uint32_t MMFAR;                  /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register */
+  __IOM uint32_t BFAR;                   /*!< Offset: 0x038 (R/W)  BusFault Address Register */
+  __IOM uint32_t AFSR;                   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register */
+  __IM  uint32_t PFR[2U];                /*!< Offset: 0x040 (R/ )  Processor Feature Register */
+  __IM  uint32_t DFR;                    /*!< Offset: 0x048 (R/ )  Debug Feature Register */
+  __IM  uint32_t ADR;                    /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */
+  __IM  uint32_t MMFR[4U];               /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */
+  __IM  uint32_t ISAR[5U];               /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register */
+        uint32_t RESERVED0[5U];
+  __IOM uint32_t CPACR;                  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register */
+        uint32_t RESERVED1[129U];
+  __IOM uint32_t SFCR;                   /*!< Offset: 0x290 (R/W)  Security Features Control Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLBASE_Pos               29U                                            /*!< SCB VTOR: TBLBASE Position */
+#define SCB_VTOR_TBLBASE_Msk               (1UL << SCB_VTOR_TBLBASE_Pos)                  /*!< SCB VTOR: TBLBASE Mask */
+
+#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos)            /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos              8U                                            /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos             0U                                            /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk            (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)           /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos          0U                                            /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk         (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)        /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos          18U                                            /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos          17U                                            /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos          16U                                            /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos       14U                                            /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos       13U                                            /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos       12U                                            /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos            8U                                            /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos           3U                                            /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos           1U                                            /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos           0U                                            /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos            16U                                            /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos             8U                                            /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos             0U                                            /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_MMARVALID_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 7U)               /*!< SCB CFSR (MMFSR): MMARVALID Position */
+#define SCB_CFSR_MMARVALID_Msk             (1UL << SCB_CFSR_MMARVALID_Pos)                /*!< SCB CFSR (MMFSR): MMARVALID Mask */
+
+#define SCB_CFSR_MSTKERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 4U)               /*!< SCB CFSR (MMFSR): MSTKERR Position */
+#define SCB_CFSR_MSTKERR_Msk               (1UL << SCB_CFSR_MSTKERR_Pos)                  /*!< SCB CFSR (MMFSR): MSTKERR Mask */
+
+#define SCB_CFSR_MUNSTKERR_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 3U)               /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
+#define SCB_CFSR_MUNSTKERR_Msk             (1UL << SCB_CFSR_MUNSTKERR_Pos)                /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
+
+#define SCB_CFSR_DACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 1U)               /*!< SCB CFSR (MMFSR): DACCVIOL Position */
+#define SCB_CFSR_DACCVIOL_Msk              (1UL << SCB_CFSR_DACCVIOL_Pos)                 /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
+
+#define SCB_CFSR_IACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 0U)               /*!< SCB CFSR (MMFSR): IACCVIOL Position */
+#define SCB_CFSR_IACCVIOL_Msk              (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)             /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
+
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_BFARVALID_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 7U)                  /*!< SCB CFSR (BFSR): BFARVALID Position */
+#define SCB_CFSR_BFARVALID_Msk            (1UL << SCB_CFSR_BFARVALID_Pos)                 /*!< SCB CFSR (BFSR): BFARVALID Mask */
+
+#define SCB_CFSR_STKERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 4U)                  /*!< SCB CFSR (BFSR): STKERR Position */
+#define SCB_CFSR_STKERR_Msk               (1UL << SCB_CFSR_STKERR_Pos)                    /*!< SCB CFSR (BFSR): STKERR Mask */
+
+#define SCB_CFSR_UNSTKERR_Pos             (SCB_CFSR_BUSFAULTSR_Pos + 3U)                  /*!< SCB CFSR (BFSR): UNSTKERR Position */
+#define SCB_CFSR_UNSTKERR_Msk             (1UL << SCB_CFSR_UNSTKERR_Pos)                  /*!< SCB CFSR (BFSR): UNSTKERR Mask */
+
+#define SCB_CFSR_IMPRECISERR_Pos          (SCB_CFSR_BUSFAULTSR_Pos + 2U)                  /*!< SCB CFSR (BFSR): IMPRECISERR Position */
+#define SCB_CFSR_IMPRECISERR_Msk          (1UL << SCB_CFSR_IMPRECISERR_Pos)               /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
+
+#define SCB_CFSR_PRECISERR_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 1U)                  /*!< SCB CFSR (BFSR): PRECISERR Position */
+#define SCB_CFSR_PRECISERR_Msk            (1UL << SCB_CFSR_PRECISERR_Pos)                 /*!< SCB CFSR (BFSR): PRECISERR Mask */
+
+#define SCB_CFSR_IBUSERR_Pos              (SCB_CFSR_BUSFAULTSR_Pos + 0U)                  /*!< SCB CFSR (BFSR): IBUSERR Position */
+#define SCB_CFSR_IBUSERR_Msk              (1UL << SCB_CFSR_IBUSERR_Pos)                   /*!< SCB CFSR (BFSR): IBUSERR Mask */
+
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_DIVBYZERO_Pos            (SCB_CFSR_USGFAULTSR_Pos + 9U)                  /*!< SCB CFSR (UFSR): DIVBYZERO Position */
+#define SCB_CFSR_DIVBYZERO_Msk            (1UL << SCB_CFSR_DIVBYZERO_Pos)                 /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
+
+#define SCB_CFSR_UNALIGNED_Pos            (SCB_CFSR_USGFAULTSR_Pos + 8U)                  /*!< SCB CFSR (UFSR): UNALIGNED Position */
+#define SCB_CFSR_UNALIGNED_Msk            (1UL << SCB_CFSR_UNALIGNED_Pos)                 /*!< SCB CFSR (UFSR): UNALIGNED Mask */
+
+#define SCB_CFSR_NOCP_Pos                 (SCB_CFSR_USGFAULTSR_Pos + 3U)                  /*!< SCB CFSR (UFSR): NOCP Position */
+#define SCB_CFSR_NOCP_Msk                 (1UL << SCB_CFSR_NOCP_Pos)                      /*!< SCB CFSR (UFSR): NOCP Mask */
+
+#define SCB_CFSR_INVPC_Pos                (SCB_CFSR_USGFAULTSR_Pos + 2U)                  /*!< SCB CFSR (UFSR): INVPC Position */
+#define SCB_CFSR_INVPC_Msk                (1UL << SCB_CFSR_INVPC_Pos)                     /*!< SCB CFSR (UFSR): INVPC Mask */
+
+#define SCB_CFSR_INVSTATE_Pos             (SCB_CFSR_USGFAULTSR_Pos + 1U)                  /*!< SCB CFSR (UFSR): INVSTATE Position */
+#define SCB_CFSR_INVSTATE_Msk             (1UL << SCB_CFSR_INVSTATE_Pos)                  /*!< SCB CFSR (UFSR): INVSTATE Mask */
+
+#define SCB_CFSR_UNDEFINSTR_Pos           (SCB_CFSR_USGFAULTSR_Pos + 0U)                  /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
+#define SCB_CFSR_UNDEFINSTR_Msk           (1UL << SCB_CFSR_UNDEFINSTR_Pos)                /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos              31U                                            /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos                30U                                            /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos                1U                                            /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos               4U                                            /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos                 3U                                            /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos                2U                                            /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos                   1U                                            /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos                 0U                                            /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+  \brief    Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+        uint32_t RESERVED0[1U];
+  __IM  uint32_t ICTR;                   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register */
+        uint32_t RESERVED1[1U];
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos         0U                                         /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
+  \brief    Type definitions for the Instrumentation Trace Macrocell (ITM)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+  __OM  union
+  {
+    __OM  uint8_t    u8;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */
+    __OM  uint16_t   u16;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */
+    __OM  uint32_t   u32;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */
+  }  PORT [32U];                         /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers */
+        uint32_t RESERVED0[864U];
+  __IOM uint32_t TER;                    /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register */
+        uint32_t RESERVED1[15U];
+  __IOM uint32_t TPR;                    /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */
+        uint32_t RESERVED2[15U];
+  __IOM uint32_t TCR;                    /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */
+        uint32_t RESERVED3[29U];
+  __OM  uint32_t IWR;                    /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register */
+  __IM  uint32_t IRR;                    /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register */
+  __IOM uint32_t IMCR;                   /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register */
+        uint32_t RESERVED4[43U];
+  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register */
+  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register */
+        uint32_t RESERVED5[6U];
+  __IM  uint32_t PID4;                   /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
+  __IM  uint32_t PID5;                   /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
+  __IM  uint32_t PID6;                   /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
+  __IM  uint32_t PID7;                   /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
+  __IM  uint32_t PID0;                   /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
+  __IM  uint32_t PID1;                   /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
+  __IM  uint32_t PID2;                   /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
+  __IM  uint32_t PID3;                   /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
+  __IM  uint32_t CID0;                   /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
+  __IM  uint32_t CID1;                   /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
+  __IM  uint32_t CID2;                   /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
+  __IM  uint32_t CID3;                   /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos                0U                                            /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk               (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/)            /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos                   23U                                            /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos             16U                                            /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos                10U                                            /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos              8U                                            /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos                  4U                                            /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos                  3U                                            /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos                 2U                                            /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos                   1U                                            /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos                  0U                                            /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos                0U                                            /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk               (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)              /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos                0U                                            /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk               (1UL /*<< ITM_IRR_ATREADYM_Pos*/)              /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos            0U                                            /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk           (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)          /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos                 2U                                            /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos                  1U                                            /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos                 0U                                            /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
+  \brief    Type definitions for the Data Watchpoint and Trace (DWT)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */
+  __IOM uint32_t CYCCNT;                 /*!< Offset: 0x004 (R/W)  Cycle Count Register */
+  __IOM uint32_t CPICNT;                 /*!< Offset: 0x008 (R/W)  CPI Count Register */
+  __IOM uint32_t EXCCNT;                 /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register */
+  __IOM uint32_t SLEEPCNT;               /*!< Offset: 0x010 (R/W)  Sleep Count Register */
+  __IOM uint32_t LSUCNT;                 /*!< Offset: 0x014 (R/W)  LSU Count Register */
+  __IOM uint32_t FOLDCNT;                /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register */
+  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */
+  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */
+  __IOM uint32_t MASK0;                  /*!< Offset: 0x024 (R/W)  Mask Register 0 */
+  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */
+        uint32_t RESERVED0[1U];
+  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */
+  __IOM uint32_t MASK1;                  /*!< Offset: 0x034 (R/W)  Mask Register 1 */
+  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */
+        uint32_t RESERVED1[1U];
+  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */
+  __IOM uint32_t MASK2;                  /*!< Offset: 0x044 (R/W)  Mask Register 2 */
+  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */
+        uint32_t RESERVED2[1U];
+  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */
+  __IOM uint32_t MASK3;                  /*!< Offset: 0x054 (R/W)  Mask Register 3 */
+  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos             22U                                         /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos            21U                                         /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos             20U                                         /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos           19U                                         /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos             18U                                         /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos             17U                                         /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos             16U                                         /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos            12U                                         /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos               10U                                         /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos                 9U                                         /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos               5U                                         /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos             1U                                         /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos              0U                                         /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos               0U                                         /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos               0U                                         /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos           0U                                         /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos               0U                                         /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos             0U                                         /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos                   0U                                         /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk                  (0x1FUL /*<< DWT_MASK_MASK_Pos*/)           /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos        16U                                         /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos        12U                                         /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos            9U                                         /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos         8U                                         /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos           7U                                         /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos          5U                                         /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos           0U                                         /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/)    /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_TPI     Trace Port Interface (TPI)
+  \brief    Type definitions for the Trace Port Interface (TPI)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+  __IM  uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */
+  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
+        uint32_t RESERVED0[2U];
+  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
+        uint32_t RESERVED1[55U];
+  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
+        uint32_t RESERVED2[131U];
+  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
+  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
+  __IM  uint32_t FSCR;                   /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
+        uint32_t RESERVED3[759U];
+  __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER Register */
+  __IM  uint32_t FIFO0;                  /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
+  __IM  uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
+        uint32_t RESERVED4[1U];
+  __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
+  __IM  uint32_t FIFO1;                  /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
+  __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
+        uint32_t RESERVED5[39U];
+  __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */
+  __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
+        uint32_t RESERVED7[8U];
+  __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
+  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos                 16U                                         /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos                  8U                                         /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos                  0U                                         /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk                 (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)          /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY2_Pos          0U                                         /*!< TPI ITATBCTR2: ATREADY2 Position */
+#define TPI_ITATBCTR2_ATREADY2_Msk         (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/)   /*!< TPI ITATBCTR2: ATREADY2 Mask */
+
+#define TPI_ITATBCTR2_ATREADY1_Pos          0U                                         /*!< TPI ITATBCTR2: ATREADY1 Position */
+#define TPI_ITATBCTR2_ATREADY1_Msk         (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/)   /*!< TPI ITATBCTR2: ATREADY1 Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos                 16U                                         /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos                  8U                                         /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos                  0U                                         /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk                 (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)          /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY2_Pos          0U                                         /*!< TPI ITATBCTR0: ATREADY2 Position */
+#define TPI_ITATBCTR0_ATREADY2_Msk         (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/)   /*!< TPI ITATBCTR0: ATREADY2 Mask */
+
+#define TPI_ITATBCTR0_ATREADY1_Pos          0U                                         /*!< TPI ITATBCTR0: ATREADY1 Position */
+#define TPI_ITATBCTR0_ATREADY1_Msk         (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/)   /*!< TPI ITATBCTR0: ATREADY1 Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk                (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos              6U                                         /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos             5U                                         /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos             4U                                         /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos           0U                                         /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+  \brief    Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
+  __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */
+  __IOM uint32_t RBAR_A1;                /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register */
+  __IOM uint32_t RASR_A1;                /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */
+  __IOM uint32_t RBAR_A2;                /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register */
+  __IOM uint32_t RASR_A2;                /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */
+  __IOM uint32_t RBAR_A3;                /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register */
+  __IOM uint32_t RASR_A3;                /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos                   5U                                            /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos                    28U                                            /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos                    24U                                            /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos                     18U                                            /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos                     17U                                            /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos                     16U                                            /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    Type definitions for the Core Debug Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */
+  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */
+  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */
+  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5U                                            /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos         24U                                            /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos        19U                                            /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos       18U                                            /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos       17U                                            /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos         16U                                            /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos       9U                                            /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos       8U                                            /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos      7U                                            /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos       6U                                            /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5U                                            /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos        4U                                            /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
+#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address */
+#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address */
+#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address */
+#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
+
+#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */
+#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct */
+#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct */
+#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct */
+#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit */
+  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Debug Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+  #endif
+  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
+  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
+  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
+  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
+  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
+  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+  #define NVIC_GetActive              __NVIC_GetActive
+  #define NVIC_SetPriority            __NVIC_SetPriority
+  #define NVIC_GetPriority            __NVIC_GetPriority
+  #define NVIC_SystemReset            __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+  #endif
+  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetVector              __NVIC_SetVector
+  #define NVIC_GetVector              __NVIC_GetVector
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET          16
+
+
+/* The following EXC_RETURN values are saved the LR on exception entry */
+#define EXC_RETURN_HANDLER         (0xFFFFFFF1UL)     /* return to Handler mode, uses MSP after return                               */
+#define EXC_RETURN_THREAD_MSP      (0xFFFFFFF9UL)     /* return to Thread mode, uses MSP after return                                */
+#define EXC_RETURN_THREAD_PSP      (0xFFFFFFFDUL)     /* return to Thread mode, uses PSP after return                                */
+
+
+
+/**
+  \brief   Set Priority Grouping
+  \details Sets the priority grouping field using the required unlock sequence.
+           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+           Only values from 0..7 are used.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]      PriorityGroup  Priority grouping field.
+ */
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+  uint32_t reg_value;
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
+
+  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
+  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */
+  reg_value  =  (reg_value                                   |
+                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                (PriorityGroupTmp << 8U)                      );              /* Insert write key and priorty group */
+  SCB->AIRCR =  reg_value;
+}
+
+
+/**
+  \brief   Get Priority Grouping
+  \details Reads the priority grouping field from the NVIC Interrupt Controller.
+  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
+{
+  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+  \brief   Enable Interrupt
+  \details Enables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt
+  \details Disables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+    __DSB();
+    __ISB();
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Active Interrupt
+  \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not active.
+  \return             1  Interrupt status is active.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->IP[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+  else
+  {
+    SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return(((uint32_t)NVIC->IP[((uint32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+
+
+/**
+  \brief   Encode Priority
+  \details Encodes the priority for an interrupt with the given priority group,
+           preemptive priority value, and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]     PriorityGroup  Used priority group.
+  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+  \param [in]       SubPriority  Subpriority value (starting from 0).
+  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  return (
+           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
+         );
+}
+
+
+/**
+  \brief   Decode Priority
+  \details Decodes an interrupt priority value with a given priority group to
+           preemptive priority value and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+  \param [in]     PriorityGroup  Used priority group.
+  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+  \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
+}
+
+
+/**
+  \brief   Set Interrupt Vector
+  \details Sets an interrupt vector in SRAM based interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+           VTOR must been relocated to SRAM before.
+  \param [in]   IRQn      Interrupt number
+  \param [in]   vector    Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+  \brief   Get Interrupt Vector
+  \details Reads an interrupt vector from interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn      Interrupt number.
+  \return                 Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+  __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
+                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */
+  __DSB();                                                          /* Ensure completion of memory access */
+
+  for(;;)                                                           /* wait until reset */
+  {
+    __NOP();
+  }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+/* ##########################  FPU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions
+  \brief    Function that provides FPU type.
+  @{
+ */
+
+/**
+  \brief   get FPU type
+  \details returns the FPU type
+  \returns
+   - \b  0: No FPU
+   - \b  1: Single precision FPU
+   - \b  2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+    return 0U;           /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                   /* Reload value impossible */
+  }
+
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                     /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_core_DebugFunctions ITM Functions
+  \brief    Functions that access the ITM debug interface.
+  @{
+ */
+
+extern volatile int32_t ITM_RxBuffer;                              /*!< External variable to receive characters. */
+#define                 ITM_RXBUFFER_EMPTY  ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/**
+  \brief   ITM Send Character
+  \details Transmits a character via the ITM channel 0, and
+           \li Just returns when no debugger is connected that has booked the output.
+           \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+  \param [in]     ch  Character to transmit.
+  \returns            Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */
+      ((ITM->TER & 1UL               ) != 0UL)   )     /* ITM Port #0 enabled */
+  {
+    while (ITM->PORT[0U].u32 == 0UL)
+    {
+      __NOP();
+    }
+    ITM->PORT[0U].u8 = (uint8_t)ch;
+  }
+  return (ch);
+}
+
+
+/**
+  \brief   ITM Receive Character
+  \details Inputs a character via the external variable \ref ITM_RxBuffer.
+  \return             Received character.
+  \return         -1  No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)
+{
+  int32_t ch = -1;                           /* no character available */
+
+  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
+  {
+    ch = ITM_RxBuffer;
+    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
+  }
+
+  return (ch);
+}
+
+
+/**
+  \brief   ITM Check Character
+  \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+  \return          0  No character available.
+  \return          1  Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void)
+{
+
+  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
+  {
+    return (0);                              /* no character available */
+  }
+  else
+  {
+    return (1);                              /*    character available */
+  }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_SC300_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/Drivers/CMSIS/Include/mpu_armv7.h b/Drivers/CMSIS/Include/mpu_armv7.h
new file mode 100644
index 0000000..7d4b600
--- /dev/null
+++ b/Drivers/CMSIS/Include/mpu_armv7.h
@@ -0,0 +1,270 @@
+/******************************************************************************
+ * @file     mpu_armv7.h
+ * @brief    CMSIS MPU API for Armv7-M MPU
+ * @version  V5.0.4
+ * @date     10. January 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2017-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+ 
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header    /* treat file as system include file */
+#endif
+ 
+#ifndef ARM_MPU_ARMV7_H
+#define ARM_MPU_ARMV7_H
+
+#define ARM_MPU_REGION_SIZE_32B      ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes
+#define ARM_MPU_REGION_SIZE_64B      ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes
+#define ARM_MPU_REGION_SIZE_128B     ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes
+#define ARM_MPU_REGION_SIZE_256B     ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes
+#define ARM_MPU_REGION_SIZE_512B     ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes
+#define ARM_MPU_REGION_SIZE_1KB      ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte
+#define ARM_MPU_REGION_SIZE_2KB      ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes
+#define ARM_MPU_REGION_SIZE_4KB      ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes
+#define ARM_MPU_REGION_SIZE_8KB      ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes
+#define ARM_MPU_REGION_SIZE_16KB     ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes
+#define ARM_MPU_REGION_SIZE_32KB     ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes
+#define ARM_MPU_REGION_SIZE_64KB     ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes
+#define ARM_MPU_REGION_SIZE_128KB    ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes
+#define ARM_MPU_REGION_SIZE_256KB    ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes
+#define ARM_MPU_REGION_SIZE_512KB    ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes
+#define ARM_MPU_REGION_SIZE_1MB      ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte
+#define ARM_MPU_REGION_SIZE_2MB      ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes
+#define ARM_MPU_REGION_SIZE_4MB      ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes
+#define ARM_MPU_REGION_SIZE_8MB      ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes
+#define ARM_MPU_REGION_SIZE_16MB     ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes
+#define ARM_MPU_REGION_SIZE_32MB     ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes
+#define ARM_MPU_REGION_SIZE_64MB     ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes
+#define ARM_MPU_REGION_SIZE_128MB    ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes
+#define ARM_MPU_REGION_SIZE_256MB    ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes
+#define ARM_MPU_REGION_SIZE_512MB    ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes
+#define ARM_MPU_REGION_SIZE_1GB      ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte
+#define ARM_MPU_REGION_SIZE_2GB      ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes
+#define ARM_MPU_REGION_SIZE_4GB      ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes
+
+#define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access
+#define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only
+#define ARM_MPU_AP_URO  2U ///!< MPU Access Permission unprivileged access read-only
+#define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access
+#define ARM_MPU_AP_PRO  5U ///!< MPU Access Permission privileged access read-only
+#define ARM_MPU_AP_RO   6U ///!< MPU Access Permission read-only access
+
+/** MPU Region Base Address Register Value
+*
+* \param Region The region to be configured, number 0 to 15.
+* \param BaseAddress The base address for the region.
+*/
+#define ARM_MPU_RBAR(Region, BaseAddress) \
+  (((BaseAddress) & MPU_RBAR_ADDR_Msk) |  \
+   ((Region) & MPU_RBAR_REGION_Msk)    |  \
+   (MPU_RBAR_VALID_Msk))
+
+/**
+* MPU Memory Access Attributes
+* 
+* \param TypeExtField      Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
+* \param IsShareable       Region is shareable between multiple bus masters.
+* \param IsCacheable       Region is cacheable, i.e. its value may be kept in cache.
+* \param IsBufferable      Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
+*/  
+#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable)   \
+  ((((TypeExtField ) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk)                 | \
+   (((IsShareable ) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk)                      | \
+   (((IsCacheable ) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk)                      | \
+   (((IsBufferable ) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk))
+
+/**
+* MPU Region Attribute and Size Register Value
+* 
+* \param DisableExec       Instruction access disable bit, 1= disable instruction fetches.
+* \param AccessPermission  Data access permissions, allows you to configure read/write access for User and Privileged mode.
+* \param AccessAttributes  Memory access attribution, see \ref ARM_MPU_ACCESS_.
+* \param SubRegionDisable  Sub-region disable field.
+* \param Size              Region size of the region to be configured, for example 4K, 8K.
+*/
+#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size)      \
+  ((((DisableExec ) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk)                                          | \
+   (((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk)                                      | \
+   (((AccessAttributes) ) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk)))
+  
+/**
+* MPU Region Attribute and Size Register Value
+* 
+* \param DisableExec       Instruction access disable bit, 1= disable instruction fetches.
+* \param AccessPermission  Data access permissions, allows you to configure read/write access for User and Privileged mode.
+* \param TypeExtField      Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
+* \param IsShareable       Region is shareable between multiple bus masters.
+* \param IsCacheable       Region is cacheable, i.e. its value may be kept in cache.
+* \param IsBufferable      Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
+* \param SubRegionDisable  Sub-region disable field.
+* \param Size              Region size of the region to be configured, for example 4K, 8K.
+*/                         
+#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \
+  ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size)
+
+/**
+* MPU Memory Access Attribute for strongly ordered memory.
+*  - TEX: 000b
+*  - Shareable
+*  - Non-cacheable
+*  - Non-bufferable
+*/ 
+#define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U)
+
+/**
+* MPU Memory Access Attribute for device memory.
+*  - TEX: 000b (if non-shareable) or 010b (if shareable)
+*  - Shareable or non-shareable
+*  - Non-cacheable
+*  - Bufferable (if shareable) or non-bufferable (if non-shareable)
+*
+* \param IsShareable Configures the device memory as shareable or non-shareable.
+*/ 
+#define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U))
+
+/**
+* MPU Memory Access Attribute for normal memory.
+*  - TEX: 1BBb (reflecting outer cacheability rules)
+*  - Shareable or non-shareable
+*  - Cacheable or non-cacheable (reflecting inner cacheability rules)
+*  - Bufferable or non-bufferable (reflecting inner cacheability rules)
+*
+* \param OuterCp Configures the outer cache policy.
+* \param InnerCp Configures the inner cache policy.
+* \param IsShareable Configures the memory as shareable or non-shareable.
+*/ 
+#define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) & 2U), ((InnerCp) & 1U))
+
+/**
+* MPU Memory Access Attribute non-cacheable policy.
+*/
+#define ARM_MPU_CACHEP_NOCACHE 0U
+
+/**
+* MPU Memory Access Attribute write-back, write and read allocate policy.
+*/
+#define ARM_MPU_CACHEP_WB_WRA 1U
+
+/**
+* MPU Memory Access Attribute write-through, no write allocate policy.
+*/
+#define ARM_MPU_CACHEP_WT_NWA 2U
+
+/**
+* MPU Memory Access Attribute write-back, no write allocate policy.
+*/
+#define ARM_MPU_CACHEP_WB_NWA 3U
+
+
+/**
+* Struct for a single MPU Region
+*/
+typedef struct {
+  uint32_t RBAR; //!< The region base address register value (RBAR)
+  uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR
+} ARM_MPU_Region_t;
+    
+/** Enable the MPU.
+* \param MPU_Control Default access permissions for unconfigured regions.
+*/
+__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
+{
+  __DSB();
+  __ISB();
+  MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+  SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+}
+
+/** Disable the MPU.
+*/
+__STATIC_INLINE void ARM_MPU_Disable(void)
+{
+  __DSB();
+  __ISB();
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+  SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+  MPU->CTRL  &= ~MPU_CTRL_ENABLE_Msk;
+}
+
+/** Clear and disable the given MPU region.
+* \param rnr Region number to be cleared.
+*/
+__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
+{
+  MPU->RNR = rnr;
+  MPU->RASR = 0U;
+}
+
+/** Configure an MPU region.
+* \param rbar Value for RBAR register.
+* \param rsar Value for RSAR register.
+*/   
+__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr)
+{
+  MPU->RBAR = rbar;
+  MPU->RASR = rasr;
+}
+
+/** Configure the given MPU region.
+* \param rnr Region number to be configured.
+* \param rbar Value for RBAR register.
+* \param rsar Value for RSAR register.
+*/   
+__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr)
+{
+  MPU->RNR = rnr;
+  MPU->RBAR = rbar;
+  MPU->RASR = rasr;
+}
+
+/** Memcopy with strictly ordered memory access, e.g. for register targets.
+* \param dst Destination data is copied to.
+* \param src Source data is copied from.
+* \param len Amount of data words to be copied.
+*/
+__STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
+{
+  uint32_t i;
+  for (i = 0U; i < len; ++i) 
+  {
+    dst[i] = src[i];
+  }
+}
+
+/** Load the given number of MPU regions from a table.
+* \param table Pointer to the MPU configuration table.
+* \param cnt Amount of regions to be configured.
+*/
+__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt) 
+{
+  const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
+  while (cnt > MPU_TYPE_RALIASES) {
+    orderedCpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize);
+    table += MPU_TYPE_RALIASES;
+    cnt -= MPU_TYPE_RALIASES;
+  }
+  orderedCpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize);
+}
+
+#endif
diff --git a/Drivers/CMSIS/Include/mpu_armv8.h b/Drivers/CMSIS/Include/mpu_armv8.h
new file mode 100644
index 0000000..99ee9f9
--- /dev/null
+++ b/Drivers/CMSIS/Include/mpu_armv8.h
@@ -0,0 +1,333 @@
+/******************************************************************************
+ * @file     mpu_armv8.h
+ * @brief    CMSIS MPU API for Armv8-M MPU
+ * @version  V5.0.4
+ * @date     10. January 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2017-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header    /* treat file as system include file */
+#endif
+
+#ifndef ARM_MPU_ARMV8_H
+#define ARM_MPU_ARMV8_H
+
+/** \brief Attribute for device memory (outer only) */
+#define ARM_MPU_ATTR_DEVICE                           ( 0U )
+
+/** \brief Attribute for non-cacheable, normal memory */
+#define ARM_MPU_ATTR_NON_CACHEABLE                    ( 4U )
+
+/** \brief Attribute for normal memory (outer and inner)
+* \param NT Non-Transient: Set to 1 for non-transient data.
+* \param WB Write-Back: Set to 1 to use write-back update policy.
+* \param RA Read Allocation: Set to 1 to use cache allocation on read miss.
+* \param WA Write Allocation: Set to 1 to use cache allocation on write miss.
+*/
+#define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \
+  (((NT & 1U) << 3U) | ((WB & 1U) << 2U) | ((RA & 1U) << 1U) | (WA & 1U))
+
+/** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */
+#define ARM_MPU_ATTR_DEVICE_nGnRnE (0U)
+
+/** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */
+#define ARM_MPU_ATTR_DEVICE_nGnRE  (1U)
+
+/** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */
+#define ARM_MPU_ATTR_DEVICE_nGRE   (2U)
+
+/** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */
+#define ARM_MPU_ATTR_DEVICE_GRE    (3U)
+
+/** \brief Memory Attribute
+* \param O Outer memory attributes
+* \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes
+*/
+#define ARM_MPU_ATTR(O, I) (((O & 0xFU) << 4U) | (((O & 0xFU) != 0U) ? (I & 0xFU) : ((I & 0x3U) << 2U)))
+
+/** \brief Normal memory non-shareable  */
+#define ARM_MPU_SH_NON   (0U)
+
+/** \brief Normal memory outer shareable  */
+#define ARM_MPU_SH_OUTER (2U)
+
+/** \brief Normal memory inner shareable  */
+#define ARM_MPU_SH_INNER (3U)
+
+/** \brief Memory access permissions
+* \param RO Read-Only: Set to 1 for read-only memory.
+* \param NP Non-Privileged: Set to 1 for non-privileged memory.
+*/
+#define ARM_MPU_AP_(RO, NP) (((RO & 1U) << 1U) | (NP & 1U))
+
+/** \brief Region Base Address Register value
+* \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned.
+* \param SH Defines the Shareability domain for this memory region.
+* \param RO Read-Only: Set to 1 for a read-only memory region.
+* \param NP Non-Privileged: Set to 1 for a non-privileged memory region.
+* \oaram XN eXecute Never: Set to 1 for a non-executable memory region.
+*/
+#define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \
+  ((BASE & MPU_RBAR_BASE_Msk) | \
+  ((SH << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \
+  ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \
+  ((XN << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk))
+
+/** \brief Region Limit Address Register value
+* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended.
+* \param IDX The attribute index to be associated with this memory region.
+*/
+#define ARM_MPU_RLAR(LIMIT, IDX) \
+  ((LIMIT & MPU_RLAR_LIMIT_Msk) | \
+  ((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \
+  (MPU_RLAR_EN_Msk))
+
+/**
+* Struct for a single MPU Region
+*/
+typedef struct {
+  uint32_t RBAR;                   /*!< Region Base Address Register value */
+  uint32_t RLAR;                   /*!< Region Limit Address Register value */
+} ARM_MPU_Region_t;
+    
+/** Enable the MPU.
+* \param MPU_Control Default access permissions for unconfigured regions.
+*/
+__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
+{
+  __DSB();
+  __ISB();
+  MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+  SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+}
+
+/** Disable the MPU.
+*/
+__STATIC_INLINE void ARM_MPU_Disable(void)
+{
+  __DSB();
+  __ISB();
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+  SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+  MPU->CTRL  &= ~MPU_CTRL_ENABLE_Msk;
+}
+
+#ifdef MPU_NS
+/** Enable the Non-secure MPU.
+* \param MPU_Control Default access permissions for unconfigured regions.
+*/
+__STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control)
+{
+  __DSB();
+  __ISB();
+  MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+  SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+}
+
+/** Disable the Non-secure MPU.
+*/
+__STATIC_INLINE void ARM_MPU_Disable_NS(void)
+{
+  __DSB();
+  __ISB();
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+  SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+  MPU_NS->CTRL  &= ~MPU_CTRL_ENABLE_Msk;
+}
+#endif
+
+/** Set the memory attribute encoding to the given MPU.
+* \param mpu Pointer to the MPU to be configured.
+* \param idx The attribute index to be set [0-7]
+* \param attr The attribute value to be set.
+*/
+__STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr)
+{
+  const uint8_t reg = idx / 4U;
+  const uint32_t pos = ((idx % 4U) * 8U);
+  const uint32_t mask = 0xFFU << pos;
+  
+  if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) {
+    return; // invalid index
+  }
+  
+  mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask));
+}
+
+/** Set the memory attribute encoding.
+* \param idx The attribute index to be set [0-7]
+* \param attr The attribute value to be set.
+*/
+__STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr)
+{
+  ARM_MPU_SetMemAttrEx(MPU, idx, attr);
+}
+
+#ifdef MPU_NS
+/** Set the memory attribute encoding to the Non-secure MPU.
+* \param idx The attribute index to be set [0-7]
+* \param attr The attribute value to be set.
+*/
+__STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr)
+{
+  ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr);
+}
+#endif
+
+/** Clear and disable the given MPU region of the given MPU.
+* \param mpu Pointer to MPU to be used.
+* \param rnr Region number to be cleared.
+*/
+__STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr)
+{
+  mpu->RNR = rnr;
+  mpu->RLAR = 0U;
+}
+
+/** Clear and disable the given MPU region.
+* \param rnr Region number to be cleared.
+*/
+__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
+{
+  ARM_MPU_ClrRegionEx(MPU, rnr);
+}
+
+#ifdef MPU_NS
+/** Clear and disable the given Non-secure MPU region.
+* \param rnr Region number to be cleared.
+*/
+__STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr)
+{  
+  ARM_MPU_ClrRegionEx(MPU_NS, rnr);
+}
+#endif
+
+/** Configure the given MPU region of the given MPU.
+* \param mpu Pointer to MPU to be used.
+* \param rnr Region number to be configured.
+* \param rbar Value for RBAR register.
+* \param rlar Value for RLAR register.
+*/   
+__STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar)
+{
+  mpu->RNR = rnr;
+  mpu->RBAR = rbar;
+  mpu->RLAR = rlar;
+}
+
+/** Configure the given MPU region.
+* \param rnr Region number to be configured.
+* \param rbar Value for RBAR register.
+* \param rlar Value for RLAR register.
+*/   
+__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar)
+{
+  ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar);
+}
+
+#ifdef MPU_NS
+/** Configure the given Non-secure MPU region.
+* \param rnr Region number to be configured.
+* \param rbar Value for RBAR register.
+* \param rlar Value for RLAR register.
+*/   
+__STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar)
+{
+  ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar);  
+}
+#endif
+
+/** Memcopy with strictly ordered memory access, e.g. for register targets.
+* \param dst Destination data is copied to.
+* \param src Source data is copied from.
+* \param len Amount of data words to be copied.
+*/
+__STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
+{
+  uint32_t i;
+  for (i = 0U; i < len; ++i) 
+  {
+    dst[i] = src[i];
+  }
+}
+
+/** Load the given number of MPU regions from a table to the given MPU.
+* \param mpu Pointer to the MPU registers to be used.
+* \param rnr First region number to be configured.
+* \param table Pointer to the MPU configuration table.
+* \param cnt Amount of regions to be configured.
+*/
+__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) 
+{
+  const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
+  if (cnt == 1U) {
+    mpu->RNR = rnr;
+    orderedCpy(&(mpu->RBAR), &(table->RBAR), rowWordSize);
+  } else {
+    uint32_t rnrBase   = rnr & ~(MPU_TYPE_RALIASES-1U);
+    uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES;
+    
+    mpu->RNR = rnrBase;
+    while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) {
+      uint32_t c = MPU_TYPE_RALIASES - rnrOffset;
+      orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize);
+      table += c;
+      cnt -= c;
+      rnrOffset = 0U;
+      rnrBase += MPU_TYPE_RALIASES;
+      mpu->RNR = rnrBase;
+    }
+    
+    orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize);
+  }
+}
+
+/** Load the given number of MPU regions from a table.
+* \param rnr First region number to be configured.
+* \param table Pointer to the MPU configuration table.
+* \param cnt Amount of regions to be configured.
+*/
+__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) 
+{
+  ARM_MPU_LoadEx(MPU, rnr, table, cnt);
+}
+
+#ifdef MPU_NS
+/** Load the given number of MPU regions from a table to the Non-secure MPU.
+* \param rnr First region number to be configured.
+* \param table Pointer to the MPU configuration table.
+* \param cnt Amount of regions to be configured.
+*/
+__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) 
+{
+  ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt);
+}
+#endif
+
+#endif
+
diff --git a/Drivers/CMSIS/Include/tz_context.h b/Drivers/CMSIS/Include/tz_context.h
new file mode 100644
index 0000000..d4c1474
--- /dev/null
+++ b/Drivers/CMSIS/Include/tz_context.h
@@ -0,0 +1,70 @@
+/******************************************************************************
+ * @file     tz_context.h
+ * @brief    Context Management for Armv8-M TrustZone
+ * @version  V1.0.1
+ * @date     10. January 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2017-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef TZ_CONTEXT_H
+#define TZ_CONTEXT_H
+ 
+#include <stdint.h>
+ 
+#ifndef TZ_MODULEID_T
+#define TZ_MODULEID_T
+/// \details Data type that identifies secure software modules called by a process.
+typedef uint32_t TZ_ModuleId_t;
+#endif
+ 
+/// \details TZ Memory ID identifies an allocated memory slot.
+typedef uint32_t TZ_MemoryId_t;
+  
+/// Initialize secure context memory system
+/// \return execution status (1: success, 0: error)
+uint32_t TZ_InitContextSystem_S (void);
+ 
+/// Allocate context memory for calling secure software modules in TrustZone
+/// \param[in]  module   identifies software modules called from non-secure mode
+/// \return value != 0 id TrustZone memory slot identifier
+/// \return value 0    no memory available or internal error
+TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module);
+ 
+/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S
+/// \param[in]  id  TrustZone memory slot identifier
+/// \return execution status (1: success, 0: error)
+uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id);
+ 
+/// Load secure context (called on RTOS thread context switch)
+/// \param[in]  id  TrustZone memory slot identifier
+/// \return execution status (1: success, 0: error)
+uint32_t TZ_LoadContext_S (TZ_MemoryId_t id);
+ 
+/// Store secure context (called on RTOS thread context switch)
+/// \param[in]  id  TrustZone memory slot identifier
+/// \return execution status (1: success, 0: error)
+uint32_t TZ_StoreContext_S (TZ_MemoryId_t id);
+ 
+#endif  // TZ_CONTEXT_H
diff --git a/Drivers/CMSIS/LICENSE.txt b/Drivers/CMSIS/LICENSE.txt
new file mode 100644
index 0000000..c0ee812
--- /dev/null
+++ b/Drivers/CMSIS/LICENSE.txt
@@ -0,0 +1,201 @@
+                                 Apache License
+                           Version 2.0, January 2004
+                        http://www.apache.org/licenses/
+
+   TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION
+
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+
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diff --git a/Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h b/Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h
new file mode 100644
index 0000000..ea65581
--- /dev/null
+++ b/Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h
@@ -0,0 +1,3982 @@
+/**
+  ******************************************************************************
+  * @file    stm32_hal_legacy.h
+  * @author  MCD Application Team
+  * @brief   This file contains aliases definition for the STM32Cube HAL constants
+  *          macros and functions maintained for legacy purpose.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2021 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32_HAL_LEGACY
+#define STM32_HAL_LEGACY
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup HAL_AES_Aliased_Defines HAL CRYP Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define AES_FLAG_RDERR                  CRYP_FLAG_RDERR
+#define AES_FLAG_WRERR                  CRYP_FLAG_WRERR
+#define AES_CLEARFLAG_CCF               CRYP_CLEARFLAG_CCF
+#define AES_CLEARFLAG_RDERR             CRYP_CLEARFLAG_RDERR
+#define AES_CLEARFLAG_WRERR             CRYP_CLEARFLAG_WRERR
+#if defined(STM32U5)
+#define CRYP_DATATYPE_32B               CRYP_NO_SWAP
+#define CRYP_DATATYPE_16B               CRYP_HALFWORD_SWAP
+#define CRYP_DATATYPE_8B                CRYP_BYTE_SWAP
+#define CRYP_DATATYPE_1B                CRYP_BIT_SWAP
+#define CRYP_CCF_CLEAR                  CRYP_CLEAR_CCF
+#define CRYP_ERR_CLEAR                  CRYP_CLEAR_RWEIF
+#endif /* STM32U5 */
+/**
+  * @}
+  */
+
+/** @defgroup HAL_ADC_Aliased_Defines HAL ADC Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define ADC_RESOLUTION12b               ADC_RESOLUTION_12B
+#define ADC_RESOLUTION10b               ADC_RESOLUTION_10B
+#define ADC_RESOLUTION8b                ADC_RESOLUTION_8B
+#define ADC_RESOLUTION6b                ADC_RESOLUTION_6B
+#define OVR_DATA_OVERWRITTEN            ADC_OVR_DATA_OVERWRITTEN
+#define OVR_DATA_PRESERVED              ADC_OVR_DATA_PRESERVED
+#define EOC_SINGLE_CONV                 ADC_EOC_SINGLE_CONV
+#define EOC_SEQ_CONV                    ADC_EOC_SEQ_CONV
+#define EOC_SINGLE_SEQ_CONV             ADC_EOC_SINGLE_SEQ_CONV
+#define REGULAR_GROUP                   ADC_REGULAR_GROUP
+#define INJECTED_GROUP                  ADC_INJECTED_GROUP
+#define REGULAR_INJECTED_GROUP          ADC_REGULAR_INJECTED_GROUP
+#define AWD_EVENT                       ADC_AWD_EVENT
+#define AWD1_EVENT                      ADC_AWD1_EVENT
+#define AWD2_EVENT                      ADC_AWD2_EVENT
+#define AWD3_EVENT                      ADC_AWD3_EVENT
+#define OVR_EVENT                       ADC_OVR_EVENT
+#define JQOVF_EVENT                     ADC_JQOVF_EVENT
+#define ALL_CHANNELS                    ADC_ALL_CHANNELS
+#define REGULAR_CHANNELS                ADC_REGULAR_CHANNELS
+#define INJECTED_CHANNELS               ADC_INJECTED_CHANNELS
+#define SYSCFG_FLAG_SENSOR_ADC          ADC_FLAG_SENSOR
+#define SYSCFG_FLAG_VREF_ADC            ADC_FLAG_VREFINT
+#define ADC_CLOCKPRESCALER_PCLK_DIV1    ADC_CLOCK_SYNC_PCLK_DIV1
+#define ADC_CLOCKPRESCALER_PCLK_DIV2    ADC_CLOCK_SYNC_PCLK_DIV2
+#define ADC_CLOCKPRESCALER_PCLK_DIV4    ADC_CLOCK_SYNC_PCLK_DIV4
+#define ADC_CLOCKPRESCALER_PCLK_DIV6    ADC_CLOCK_SYNC_PCLK_DIV6
+#define ADC_CLOCKPRESCALER_PCLK_DIV8    ADC_CLOCK_SYNC_PCLK_DIV8
+#define ADC_EXTERNALTRIG0_T6_TRGO       ADC_EXTERNALTRIGCONV_T6_TRGO
+#define ADC_EXTERNALTRIG1_T21_CC2       ADC_EXTERNALTRIGCONV_T21_CC2
+#define ADC_EXTERNALTRIG2_T2_TRGO       ADC_EXTERNALTRIGCONV_T2_TRGO
+#define ADC_EXTERNALTRIG3_T2_CC4        ADC_EXTERNALTRIGCONV_T2_CC4
+#define ADC_EXTERNALTRIG4_T22_TRGO      ADC_EXTERNALTRIGCONV_T22_TRGO
+#define ADC_EXTERNALTRIG7_EXT_IT11      ADC_EXTERNALTRIGCONV_EXT_IT11
+#define ADC_CLOCK_ASYNC                 ADC_CLOCK_ASYNC_DIV1
+#define ADC_EXTERNALTRIG_EDGE_NONE      ADC_EXTERNALTRIGCONVEDGE_NONE
+#define ADC_EXTERNALTRIG_EDGE_RISING    ADC_EXTERNALTRIGCONVEDGE_RISING
+#define ADC_EXTERNALTRIG_EDGE_FALLING   ADC_EXTERNALTRIGCONVEDGE_FALLING
+#define ADC_EXTERNALTRIG_EDGE_RISINGFALLING ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING
+#define ADC_SAMPLETIME_2CYCLE_5         ADC_SAMPLETIME_2CYCLES_5
+
+#define HAL_ADC_STATE_BUSY_REG          HAL_ADC_STATE_REG_BUSY
+#define HAL_ADC_STATE_BUSY_INJ          HAL_ADC_STATE_INJ_BUSY
+#define HAL_ADC_STATE_EOC_REG           HAL_ADC_STATE_REG_EOC
+#define HAL_ADC_STATE_EOC_INJ           HAL_ADC_STATE_INJ_EOC
+#define HAL_ADC_STATE_ERROR             HAL_ADC_STATE_ERROR_INTERNAL
+#define HAL_ADC_STATE_BUSY              HAL_ADC_STATE_BUSY_INTERNAL
+#define HAL_ADC_STATE_AWD               HAL_ADC_STATE_AWD1
+
+#if defined(STM32H7)
+#define ADC_CHANNEL_VBAT_DIV4           ADC_CHANNEL_VBAT
+#endif /* STM32H7 */
+
+#if defined(STM32U5)
+#define ADC_SAMPLETIME_5CYCLE           ADC_SAMPLETIME_5CYCLES
+#define ADC_SAMPLETIME_391CYCLES_5      ADC_SAMPLETIME_391CYCLES
+#define ADC4_SAMPLETIME_160CYCLES_5     ADC4_SAMPLETIME_814CYCLES_5
+#endif /* STM32U5 */
+/**
+  * @}
+  */
+
+/** @defgroup HAL_CEC_Aliased_Defines HAL CEC Aliased Defines maintained for legacy purpose
+  * @{
+  */
+
+#define __HAL_CEC_GET_IT __HAL_CEC_GET_FLAG
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_COMP_Aliased_Defines HAL COMP Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define COMP_WINDOWMODE_DISABLED       COMP_WINDOWMODE_DISABLE
+#define COMP_WINDOWMODE_ENABLED        COMP_WINDOWMODE_ENABLE
+#define COMP_EXTI_LINE_COMP1_EVENT     COMP_EXTI_LINE_COMP1
+#define COMP_EXTI_LINE_COMP2_EVENT     COMP_EXTI_LINE_COMP2
+#define COMP_EXTI_LINE_COMP3_EVENT     COMP_EXTI_LINE_COMP3
+#define COMP_EXTI_LINE_COMP4_EVENT     COMP_EXTI_LINE_COMP4
+#define COMP_EXTI_LINE_COMP5_EVENT     COMP_EXTI_LINE_COMP5
+#define COMP_EXTI_LINE_COMP6_EVENT     COMP_EXTI_LINE_COMP6
+#define COMP_EXTI_LINE_COMP7_EVENT     COMP_EXTI_LINE_COMP7
+#if defined(STM32L0)
+#define COMP_LPTIMCONNECTION_ENABLED   ((uint32_t)0x00000003U)    /*!< COMPX output generic naming: connected to LPTIM input 1 for COMP1, LPTIM input 2 for COMP2 */
+#endif
+#define COMP_OUTPUT_COMP6TIM2OCREFCLR  COMP_OUTPUT_COMP6_TIM2OCREFCLR
+#if defined(STM32F373xC) || defined(STM32F378xx)
+#define COMP_OUTPUT_TIM3IC1            COMP_OUTPUT_COMP1_TIM3IC1
+#define COMP_OUTPUT_TIM3OCREFCLR       COMP_OUTPUT_COMP1_TIM3OCREFCLR
+#endif /* STM32F373xC || STM32F378xx */
+
+#if defined(STM32L0) || defined(STM32L4)
+#define COMP_WINDOWMODE_ENABLE         COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON
+
+#define COMP_NONINVERTINGINPUT_IO1      COMP_INPUT_PLUS_IO1
+#define COMP_NONINVERTINGINPUT_IO2      COMP_INPUT_PLUS_IO2
+#define COMP_NONINVERTINGINPUT_IO3      COMP_INPUT_PLUS_IO3
+#define COMP_NONINVERTINGINPUT_IO4      COMP_INPUT_PLUS_IO4
+#define COMP_NONINVERTINGINPUT_IO5      COMP_INPUT_PLUS_IO5
+#define COMP_NONINVERTINGINPUT_IO6      COMP_INPUT_PLUS_IO6
+
+#define COMP_INVERTINGINPUT_1_4VREFINT  COMP_INPUT_MINUS_1_4VREFINT
+#define COMP_INVERTINGINPUT_1_2VREFINT  COMP_INPUT_MINUS_1_2VREFINT
+#define COMP_INVERTINGINPUT_3_4VREFINT  COMP_INPUT_MINUS_3_4VREFINT
+#define COMP_INVERTINGINPUT_VREFINT     COMP_INPUT_MINUS_VREFINT
+#define COMP_INVERTINGINPUT_DAC1_CH1    COMP_INPUT_MINUS_DAC1_CH1
+#define COMP_INVERTINGINPUT_DAC1_CH2    COMP_INPUT_MINUS_DAC1_CH2
+#define COMP_INVERTINGINPUT_DAC1        COMP_INPUT_MINUS_DAC1_CH1
+#define COMP_INVERTINGINPUT_DAC2        COMP_INPUT_MINUS_DAC1_CH2
+#define COMP_INVERTINGINPUT_IO1         COMP_INPUT_MINUS_IO1
+#if defined(STM32L0)
+/* Issue fixed on STM32L0 COMP driver: only 2 dedicated IO (IO1 and IO2),     */
+/* IO2 was wrongly assigned to IO shared with DAC and IO3 was corresponding   */
+/* to the second dedicated IO (only for COMP2).                               */
+#define COMP_INVERTINGINPUT_IO2         COMP_INPUT_MINUS_DAC1_CH2
+#define COMP_INVERTINGINPUT_IO3         COMP_INPUT_MINUS_IO2
+#else
+#define COMP_INVERTINGINPUT_IO2         COMP_INPUT_MINUS_IO2
+#define COMP_INVERTINGINPUT_IO3         COMP_INPUT_MINUS_IO3
+#endif
+#define COMP_INVERTINGINPUT_IO4         COMP_INPUT_MINUS_IO4
+#define COMP_INVERTINGINPUT_IO5         COMP_INPUT_MINUS_IO5
+
+#define COMP_OUTPUTLEVEL_LOW            COMP_OUTPUT_LEVEL_LOW
+#define COMP_OUTPUTLEVEL_HIGH           COMP_OUTPUT_LEVEL_HIGH
+
+/* Note: Literal "COMP_FLAG_LOCK" kept for legacy purpose.                    */
+/*       To check COMP lock state, use macro "__HAL_COMP_IS_LOCKED()".        */
+#if defined(COMP_CSR_LOCK)
+#define COMP_FLAG_LOCK                 COMP_CSR_LOCK
+#elif defined(COMP_CSR_COMP1LOCK)
+#define COMP_FLAG_LOCK                 COMP_CSR_COMP1LOCK
+#elif defined(COMP_CSR_COMPxLOCK)
+#define COMP_FLAG_LOCK                 COMP_CSR_COMPxLOCK
+#endif
+
+#if defined(STM32L4)
+#define COMP_BLANKINGSRCE_TIM1OC5        COMP_BLANKINGSRC_TIM1_OC5_COMP1
+#define COMP_BLANKINGSRCE_TIM2OC3        COMP_BLANKINGSRC_TIM2_OC3_COMP1
+#define COMP_BLANKINGSRCE_TIM3OC3        COMP_BLANKINGSRC_TIM3_OC3_COMP1
+#define COMP_BLANKINGSRCE_TIM3OC4        COMP_BLANKINGSRC_TIM3_OC4_COMP2
+#define COMP_BLANKINGSRCE_TIM8OC5        COMP_BLANKINGSRC_TIM8_OC5_COMP2
+#define COMP_BLANKINGSRCE_TIM15OC1       COMP_BLANKINGSRC_TIM15_OC1_COMP2
+#define COMP_BLANKINGSRCE_NONE           COMP_BLANKINGSRC_NONE
+#endif
+
+#if defined(STM32L0)
+#define COMP_MODE_HIGHSPEED              COMP_POWERMODE_MEDIUMSPEED
+#define COMP_MODE_LOWSPEED               COMP_POWERMODE_ULTRALOWPOWER
+#else
+#define COMP_MODE_HIGHSPEED              COMP_POWERMODE_HIGHSPEED
+#define COMP_MODE_MEDIUMSPEED            COMP_POWERMODE_MEDIUMSPEED
+#define COMP_MODE_LOWPOWER               COMP_POWERMODE_LOWPOWER
+#define COMP_MODE_ULTRALOWPOWER          COMP_POWERMODE_ULTRALOWPOWER
+#endif
+
+#endif
+/**
+  * @}
+  */
+
+/** @defgroup HAL_CORTEX_Aliased_Defines HAL CORTEX Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define __HAL_CORTEX_SYSTICKCLK_CONFIG HAL_SYSTICK_CLKSourceConfig
+#if defined(STM32U5)
+#define  MPU_DEVICE_nGnRnE          MPU_DEVICE_NGNRNE
+#define  MPU_DEVICE_nGnRE           MPU_DEVICE_NGNRE
+#define  MPU_DEVICE_nGRE            MPU_DEVICE_NGRE
+#endif /* STM32U5 */
+/**
+  * @}
+  */
+
+/** @defgroup CRC_Aliases CRC API aliases
+  * @{
+  */
+#define HAL_CRC_Input_Data_Reverse   HAL_CRCEx_Input_Data_Reverse    /*!< Aliased to HAL_CRCEx_Input_Data_Reverse for inter STM32 series compatibility  */
+#define HAL_CRC_Output_Data_Reverse  HAL_CRCEx_Output_Data_Reverse   /*!< Aliased to HAL_CRCEx_Output_Data_Reverse for inter STM32 series compatibility */
+/**
+  * @}
+  */
+
+/** @defgroup HAL_CRC_Aliased_Defines HAL CRC Aliased Defines maintained for legacy purpose
+  * @{
+  */
+
+#define CRC_OUTPUTDATA_INVERSION_DISABLED    CRC_OUTPUTDATA_INVERSION_DISABLE
+#define CRC_OUTPUTDATA_INVERSION_ENABLED     CRC_OUTPUTDATA_INVERSION_ENABLE
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_DAC_Aliased_Defines HAL DAC Aliased Defines maintained for legacy purpose
+  * @{
+  */
+
+#define DAC1_CHANNEL_1                                  DAC_CHANNEL_1
+#define DAC1_CHANNEL_2                                  DAC_CHANNEL_2
+#define DAC2_CHANNEL_1                                  DAC_CHANNEL_1
+#define DAC_WAVE_NONE                                   0x00000000U
+#define DAC_WAVE_NOISE                                  DAC_CR_WAVE1_0
+#define DAC_WAVE_TRIANGLE                               DAC_CR_WAVE1_1
+#define DAC_WAVEGENERATION_NONE                         DAC_WAVE_NONE
+#define DAC_WAVEGENERATION_NOISE                        DAC_WAVE_NOISE
+#define DAC_WAVEGENERATION_TRIANGLE                     DAC_WAVE_TRIANGLE
+
+#if defined(STM32G4) || defined(STM32H7) || defined (STM32U5)
+#define DAC_CHIPCONNECT_DISABLE       DAC_CHIPCONNECT_EXTERNAL
+#define DAC_CHIPCONNECT_ENABLE        DAC_CHIPCONNECT_INTERNAL
+#endif
+
+#if defined(STM32U5)
+#define DAC_TRIGGER_STOP_LPTIM1_OUT  DAC_TRIGGER_STOP_LPTIM1_CH1
+#define DAC_TRIGGER_STOP_LPTIM3_OUT  DAC_TRIGGER_STOP_LPTIM3_CH1
+#define DAC_TRIGGER_LPTIM1_OUT       DAC_TRIGGER_LPTIM1_CH1
+#define DAC_TRIGGER_LPTIM3_OUT       DAC_TRIGGER_LPTIM3_CH1
+#endif
+
+#if defined(STM32L1) || defined(STM32L4) || defined(STM32G0) || defined(STM32L5) || defined(STM32H7) || defined(STM32F4) || defined(STM32G4)
+#define HAL_DAC_MSP_INIT_CB_ID       HAL_DAC_MSPINIT_CB_ID
+#define HAL_DAC_MSP_DEINIT_CB_ID     HAL_DAC_MSPDEINIT_CB_ID
+#endif
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_DMA_Aliased_Defines HAL DMA Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define HAL_REMAPDMA_ADC_DMA_CH2                DMA_REMAP_ADC_DMA_CH2
+#define HAL_REMAPDMA_USART1_TX_DMA_CH4          DMA_REMAP_USART1_TX_DMA_CH4
+#define HAL_REMAPDMA_USART1_RX_DMA_CH5          DMA_REMAP_USART1_RX_DMA_CH5
+#define HAL_REMAPDMA_TIM16_DMA_CH4              DMA_REMAP_TIM16_DMA_CH4
+#define HAL_REMAPDMA_TIM17_DMA_CH2              DMA_REMAP_TIM17_DMA_CH2
+#define HAL_REMAPDMA_USART3_DMA_CH32            DMA_REMAP_USART3_DMA_CH32
+#define HAL_REMAPDMA_TIM16_DMA_CH6              DMA_REMAP_TIM16_DMA_CH6
+#define HAL_REMAPDMA_TIM17_DMA_CH7              DMA_REMAP_TIM17_DMA_CH7
+#define HAL_REMAPDMA_SPI2_DMA_CH67              DMA_REMAP_SPI2_DMA_CH67
+#define HAL_REMAPDMA_USART2_DMA_CH67            DMA_REMAP_USART2_DMA_CH67
+#define HAL_REMAPDMA_I2C1_DMA_CH76              DMA_REMAP_I2C1_DMA_CH76
+#define HAL_REMAPDMA_TIM1_DMA_CH6               DMA_REMAP_TIM1_DMA_CH6
+#define HAL_REMAPDMA_TIM2_DMA_CH7               DMA_REMAP_TIM2_DMA_CH7
+#define HAL_REMAPDMA_TIM3_DMA_CH6               DMA_REMAP_TIM3_DMA_CH6
+
+#define IS_HAL_REMAPDMA                          IS_DMA_REMAP
+#define __HAL_REMAPDMA_CHANNEL_ENABLE            __HAL_DMA_REMAP_CHANNEL_ENABLE
+#define __HAL_REMAPDMA_CHANNEL_DISABLE           __HAL_DMA_REMAP_CHANNEL_DISABLE
+
+#if defined(STM32L4)
+
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI0            HAL_DMAMUX1_REQ_GEN_EXTI0
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI1            HAL_DMAMUX1_REQ_GEN_EXTI1
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI2            HAL_DMAMUX1_REQ_GEN_EXTI2
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI3            HAL_DMAMUX1_REQ_GEN_EXTI3
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI4            HAL_DMAMUX1_REQ_GEN_EXTI4
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI5            HAL_DMAMUX1_REQ_GEN_EXTI5
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI6            HAL_DMAMUX1_REQ_GEN_EXTI6
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI7            HAL_DMAMUX1_REQ_GEN_EXTI7
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI8            HAL_DMAMUX1_REQ_GEN_EXTI8
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI9            HAL_DMAMUX1_REQ_GEN_EXTI9
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI10           HAL_DMAMUX1_REQ_GEN_EXTI10
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI11           HAL_DMAMUX1_REQ_GEN_EXTI11
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI12           HAL_DMAMUX1_REQ_GEN_EXTI12
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI13           HAL_DMAMUX1_REQ_GEN_EXTI13
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI14           HAL_DMAMUX1_REQ_GEN_EXTI14
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI15           HAL_DMAMUX1_REQ_GEN_EXTI15
+#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT  HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT
+#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT  HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT
+#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT  HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT
+#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH3_EVT  HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH3_EVT
+#define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT       HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT
+#define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT       HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT
+#define HAL_DMAMUX1_REQUEST_GEN_DSI_TE           HAL_DMAMUX1_REQ_GEN_DSI_TE
+#define HAL_DMAMUX1_REQUEST_GEN_DSI_EOT          HAL_DMAMUX1_REQ_GEN_DSI_EOT
+#define HAL_DMAMUX1_REQUEST_GEN_DMA2D_EOT        HAL_DMAMUX1_REQ_GEN_DMA2D_EOT
+#define HAL_DMAMUX1_REQUEST_GEN_LTDC_IT          HAL_DMAMUX1_REQ_GEN_LTDC_IT
+
+#define HAL_DMAMUX_REQUEST_GEN_NO_EVENT          HAL_DMAMUX_REQ_GEN_NO_EVENT
+#define HAL_DMAMUX_REQUEST_GEN_RISING            HAL_DMAMUX_REQ_GEN_RISING
+#define HAL_DMAMUX_REQUEST_GEN_FALLING           HAL_DMAMUX_REQ_GEN_FALLING
+#define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING    HAL_DMAMUX_REQ_GEN_RISING_FALLING
+
+#if defined(STM32L4R5xx) || defined(STM32L4R9xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
+#define DMA_REQUEST_DCMI_PSSI                    DMA_REQUEST_DCMI
+#endif
+
+#endif /* STM32L4 */
+
+#if defined(STM32G0)
+#define DMA_REQUEST_DAC1_CHANNEL1                DMA_REQUEST_DAC1_CH1
+#define DMA_REQUEST_DAC1_CHANNEL2                DMA_REQUEST_DAC1_CH2
+#define DMA_REQUEST_TIM16_TRIG_COM               DMA_REQUEST_TIM16_COM
+#define DMA_REQUEST_TIM17_TRIG_COM               DMA_REQUEST_TIM17_COM
+
+#define LL_DMAMUX_REQ_TIM16_TRIG_COM             LL_DMAMUX_REQ_TIM16_COM
+#define LL_DMAMUX_REQ_TIM17_TRIG_COM             LL_DMAMUX_REQ_TIM17_COM
+#endif
+
+#if defined(STM32H7)
+
+#define DMA_REQUEST_DAC1 DMA_REQUEST_DAC1_CH1
+#define DMA_REQUEST_DAC2 DMA_REQUEST_DAC1_CH2
+
+#define BDMA_REQUEST_LP_UART1_RX BDMA_REQUEST_LPUART1_RX
+#define BDMA_REQUEST_LP_UART1_TX BDMA_REQUEST_LPUART1_TX
+
+#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT    HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT
+#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT    HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT
+#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT    HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT
+#define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT         HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT
+#define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT         HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT
+#define HAL_DMAMUX1_REQUEST_GEN_LPTIM3_OUT         HAL_DMAMUX1_REQ_GEN_LPTIM3_OUT
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI0              HAL_DMAMUX1_REQ_GEN_EXTI0
+#define HAL_DMAMUX1_REQUEST_GEN_TIM12_TRGO         HAL_DMAMUX1_REQ_GEN_TIM12_TRGO
+
+#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH0_EVT    HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH0_EVT
+#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH1_EVT    HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH1_EVT
+#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH2_EVT    HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH2_EVT
+#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH3_EVT    HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH3_EVT
+#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH4_EVT    HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH4_EVT
+#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH5_EVT    HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH5_EVT
+#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH6_EVT    HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH6_EVT
+#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_WKUP    HAL_DMAMUX2_REQ_GEN_LPUART1_RX_WKUP
+#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_WKUP    HAL_DMAMUX2_REQ_GEN_LPUART1_TX_WKUP
+#define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_WKUP        HAL_DMAMUX2_REQ_GEN_LPTIM2_WKUP
+#define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_OUT         HAL_DMAMUX2_REQ_GEN_LPTIM2_OUT
+#define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_WKUP        HAL_DMAMUX2_REQ_GEN_LPTIM3_WKUP
+#define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_OUT         HAL_DMAMUX2_REQ_GEN_LPTIM3_OUT
+#define HAL_DMAMUX2_REQUEST_GEN_LPTIM4_WKUP        HAL_DMAMUX2_REQ_GEN_LPTIM4_WKUP
+#define HAL_DMAMUX2_REQUEST_GEN_LPTIM5_WKUP        HAL_DMAMUX2_REQ_GEN_LPTIM5_WKUP
+#define HAL_DMAMUX2_REQUEST_GEN_I2C4_WKUP          HAL_DMAMUX2_REQ_GEN_I2C4_WKUP
+#define HAL_DMAMUX2_REQUEST_GEN_SPI6_WKUP          HAL_DMAMUX2_REQ_GEN_SPI6_WKUP
+#define HAL_DMAMUX2_REQUEST_GEN_COMP1_OUT          HAL_DMAMUX2_REQ_GEN_COMP1_OUT
+#define HAL_DMAMUX2_REQUEST_GEN_COMP2_OUT          HAL_DMAMUX2_REQ_GEN_COMP2_OUT
+#define HAL_DMAMUX2_REQUEST_GEN_RTC_WKUP           HAL_DMAMUX2_REQ_GEN_RTC_WKUP
+#define HAL_DMAMUX2_REQUEST_GEN_EXTI0              HAL_DMAMUX2_REQ_GEN_EXTI0
+#define HAL_DMAMUX2_REQUEST_GEN_EXTI2              HAL_DMAMUX2_REQ_GEN_EXTI2
+#define HAL_DMAMUX2_REQUEST_GEN_I2C4_IT_EVT        HAL_DMAMUX2_REQ_GEN_I2C4_IT_EVT
+#define HAL_DMAMUX2_REQUEST_GEN_SPI6_IT            HAL_DMAMUX2_REQ_GEN_SPI6_IT
+#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_IT      HAL_DMAMUX2_REQ_GEN_LPUART1_TX_IT
+#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_IT      HAL_DMAMUX2_REQ_GEN_LPUART1_RX_IT
+#define HAL_DMAMUX2_REQUEST_GEN_ADC3_IT            HAL_DMAMUX2_REQ_GEN_ADC3_IT
+#define HAL_DMAMUX2_REQUEST_GEN_ADC3_AWD1_OUT      HAL_DMAMUX2_REQ_GEN_ADC3_AWD1_OUT
+#define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH0_IT        HAL_DMAMUX2_REQ_GEN_BDMA_CH0_IT
+#define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH1_IT        HAL_DMAMUX2_REQ_GEN_BDMA_CH1_IT
+
+#define HAL_DMAMUX_REQUEST_GEN_NO_EVENT            HAL_DMAMUX_REQ_GEN_NO_EVENT
+#define HAL_DMAMUX_REQUEST_GEN_RISING              HAL_DMAMUX_REQ_GEN_RISING
+#define HAL_DMAMUX_REQUEST_GEN_FALLING             HAL_DMAMUX_REQ_GEN_FALLING
+#define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING      HAL_DMAMUX_REQ_GEN_RISING_FALLING
+
+#define DFSDM_FILTER_EXT_TRIG_LPTIM1               DFSDM_FILTER_EXT_TRIG_LPTIM1_OUT
+#define DFSDM_FILTER_EXT_TRIG_LPTIM2               DFSDM_FILTER_EXT_TRIG_LPTIM2_OUT
+#define DFSDM_FILTER_EXT_TRIG_LPTIM3               DFSDM_FILTER_EXT_TRIG_LPTIM3_OUT
+
+#define DAC_TRIGGER_LP1_OUT                        DAC_TRIGGER_LPTIM1_OUT
+#define DAC_TRIGGER_LP2_OUT                        DAC_TRIGGER_LPTIM2_OUT
+
+#endif /* STM32H7 */
+
+#if defined(STM32U5)
+#define GPDMA1_REQUEST_DCMI                        GPDMA1_REQUEST_DCMI_PSSI
+#endif /* STM32U5 */
+/**
+  * @}
+  */
+
+/** @defgroup HAL_FLASH_Aliased_Defines HAL FLASH Aliased Defines maintained for legacy purpose
+  * @{
+  */
+
+#define TYPEPROGRAM_BYTE              FLASH_TYPEPROGRAM_BYTE
+#define TYPEPROGRAM_HALFWORD          FLASH_TYPEPROGRAM_HALFWORD
+#define TYPEPROGRAM_WORD              FLASH_TYPEPROGRAM_WORD
+#define TYPEPROGRAM_DOUBLEWORD        FLASH_TYPEPROGRAM_DOUBLEWORD
+#define TYPEERASE_SECTORS             FLASH_TYPEERASE_SECTORS
+#define TYPEERASE_PAGES               FLASH_TYPEERASE_PAGES
+#define TYPEERASE_PAGEERASE           FLASH_TYPEERASE_PAGES
+#define TYPEERASE_MASSERASE           FLASH_TYPEERASE_MASSERASE
+#define WRPSTATE_DISABLE              OB_WRPSTATE_DISABLE
+#define WRPSTATE_ENABLE               OB_WRPSTATE_ENABLE
+#define HAL_FLASH_TIMEOUT_VALUE       FLASH_TIMEOUT_VALUE
+#define OBEX_PCROP                    OPTIONBYTE_PCROP
+#define OBEX_BOOTCONFIG               OPTIONBYTE_BOOTCONFIG
+#define PCROPSTATE_DISABLE            OB_PCROP_STATE_DISABLE
+#define PCROPSTATE_ENABLE             OB_PCROP_STATE_ENABLE
+#define TYPEERASEDATA_BYTE            FLASH_TYPEERASEDATA_BYTE
+#define TYPEERASEDATA_HALFWORD        FLASH_TYPEERASEDATA_HALFWORD
+#define TYPEERASEDATA_WORD            FLASH_TYPEERASEDATA_WORD
+#define TYPEPROGRAMDATA_BYTE          FLASH_TYPEPROGRAMDATA_BYTE
+#define TYPEPROGRAMDATA_HALFWORD      FLASH_TYPEPROGRAMDATA_HALFWORD
+#define TYPEPROGRAMDATA_WORD          FLASH_TYPEPROGRAMDATA_WORD
+#define TYPEPROGRAMDATA_FASTBYTE      FLASH_TYPEPROGRAMDATA_FASTBYTE
+#define TYPEPROGRAMDATA_FASTHALFWORD  FLASH_TYPEPROGRAMDATA_FASTHALFWORD
+#define TYPEPROGRAMDATA_FASTWORD      FLASH_TYPEPROGRAMDATA_FASTWORD
+#define PAGESIZE                      FLASH_PAGE_SIZE
+#define TYPEPROGRAM_FASTBYTE          FLASH_TYPEPROGRAM_BYTE
+#define TYPEPROGRAM_FASTHALFWORD      FLASH_TYPEPROGRAM_HALFWORD
+#define TYPEPROGRAM_FASTWORD          FLASH_TYPEPROGRAM_WORD
+#define VOLTAGE_RANGE_1               FLASH_VOLTAGE_RANGE_1
+#define VOLTAGE_RANGE_2               FLASH_VOLTAGE_RANGE_2
+#define VOLTAGE_RANGE_3               FLASH_VOLTAGE_RANGE_3
+#define VOLTAGE_RANGE_4               FLASH_VOLTAGE_RANGE_4
+#define TYPEPROGRAM_FAST              FLASH_TYPEPROGRAM_FAST
+#define TYPEPROGRAM_FAST_AND_LAST     FLASH_TYPEPROGRAM_FAST_AND_LAST
+#define WRPAREA_BANK1_AREAA           OB_WRPAREA_BANK1_AREAA
+#define WRPAREA_BANK1_AREAB           OB_WRPAREA_BANK1_AREAB
+#define WRPAREA_BANK2_AREAA           OB_WRPAREA_BANK2_AREAA
+#define WRPAREA_BANK2_AREAB           OB_WRPAREA_BANK2_AREAB
+#define IWDG_STDBY_FREEZE             OB_IWDG_STDBY_FREEZE
+#define IWDG_STDBY_ACTIVE             OB_IWDG_STDBY_RUN
+#define IWDG_STOP_FREEZE              OB_IWDG_STOP_FREEZE
+#define IWDG_STOP_ACTIVE              OB_IWDG_STOP_RUN
+#define FLASH_ERROR_NONE              HAL_FLASH_ERROR_NONE
+#define FLASH_ERROR_RD                HAL_FLASH_ERROR_RD
+#define FLASH_ERROR_PG                HAL_FLASH_ERROR_PROG
+#define FLASH_ERROR_PGP               HAL_FLASH_ERROR_PGS
+#define FLASH_ERROR_WRP               HAL_FLASH_ERROR_WRP
+#define FLASH_ERROR_OPTV              HAL_FLASH_ERROR_OPTV
+#define FLASH_ERROR_OPTVUSR           HAL_FLASH_ERROR_OPTVUSR
+#define FLASH_ERROR_PROG              HAL_FLASH_ERROR_PROG
+#define FLASH_ERROR_OP                HAL_FLASH_ERROR_OPERATION
+#define FLASH_ERROR_PGA               HAL_FLASH_ERROR_PGA
+#define FLASH_ERROR_SIZE              HAL_FLASH_ERROR_SIZE
+#define FLASH_ERROR_SIZ               HAL_FLASH_ERROR_SIZE
+#define FLASH_ERROR_PGS               HAL_FLASH_ERROR_PGS
+#define FLASH_ERROR_MIS               HAL_FLASH_ERROR_MIS
+#define FLASH_ERROR_FAST              HAL_FLASH_ERROR_FAST
+#define FLASH_ERROR_FWWERR            HAL_FLASH_ERROR_FWWERR
+#define FLASH_ERROR_NOTZERO           HAL_FLASH_ERROR_NOTZERO
+#define FLASH_ERROR_OPERATION         HAL_FLASH_ERROR_OPERATION
+#define FLASH_ERROR_ERS               HAL_FLASH_ERROR_ERS
+#define OB_WDG_SW                     OB_IWDG_SW
+#define OB_WDG_HW                     OB_IWDG_HW
+#define OB_SDADC12_VDD_MONITOR_SET    OB_SDACD_VDD_MONITOR_SET
+#define OB_SDADC12_VDD_MONITOR_RESET  OB_SDACD_VDD_MONITOR_RESET
+#define OB_RAM_PARITY_CHECK_SET       OB_SRAM_PARITY_SET
+#define OB_RAM_PARITY_CHECK_RESET     OB_SRAM_PARITY_RESET
+#define IS_OB_SDADC12_VDD_MONITOR     IS_OB_SDACD_VDD_MONITOR
+#define OB_RDP_LEVEL0                 OB_RDP_LEVEL_0
+#define OB_RDP_LEVEL1                 OB_RDP_LEVEL_1
+#define OB_RDP_LEVEL2                 OB_RDP_LEVEL_2
+#if defined(STM32G0)
+#define OB_BOOT_LOCK_DISABLE          OB_BOOT_ENTRY_FORCED_NONE
+#define OB_BOOT_LOCK_ENABLE           OB_BOOT_ENTRY_FORCED_FLASH
+#else
+#define OB_BOOT_ENTRY_FORCED_NONE     OB_BOOT_LOCK_DISABLE
+#define OB_BOOT_ENTRY_FORCED_FLASH    OB_BOOT_LOCK_ENABLE
+#endif
+#if defined(STM32H7)
+#define FLASH_FLAG_SNECCE_BANK1RR     FLASH_FLAG_SNECCERR_BANK1
+#define FLASH_FLAG_DBECCE_BANK1RR     FLASH_FLAG_DBECCERR_BANK1
+#define FLASH_FLAG_STRBER_BANK1R      FLASH_FLAG_STRBERR_BANK1
+#define FLASH_FLAG_SNECCE_BANK2RR     FLASH_FLAG_SNECCERR_BANK2
+#define FLASH_FLAG_DBECCE_BANK2RR     FLASH_FLAG_DBECCERR_BANK2
+#define FLASH_FLAG_STRBER_BANK2R      FLASH_FLAG_STRBERR_BANK2
+#define FLASH_FLAG_WDW                FLASH_FLAG_WBNE
+#define OB_WRP_SECTOR_All             OB_WRP_SECTOR_ALL
+#endif /* STM32H7 */
+#if defined(STM32U5)
+#define OB_USER_nRST_STOP             OB_USER_NRST_STOP
+#define OB_USER_nRST_STDBY            OB_USER_NRST_STDBY
+#define OB_USER_nRST_SHDW             OB_USER_NRST_SHDW
+#define OB_USER_nSWBOOT0              OB_USER_NSWBOOT0
+#define OB_USER_nBOOT0                OB_USER_NBOOT0
+#define OB_nBOOT0_RESET               OB_NBOOT0_RESET
+#define OB_nBOOT0_SET                 OB_NBOOT0_SET
+#endif /* STM32U5 */
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_JPEG_Aliased_Macros HAL JPEG Aliased Macros maintained for legacy purpose
+  * @{
+  */
+
+#if defined(STM32H7)
+#define __HAL_RCC_JPEG_CLK_ENABLE               __HAL_RCC_JPGDECEN_CLK_ENABLE
+#define __HAL_RCC_JPEG_CLK_DISABLE              __HAL_RCC_JPGDECEN_CLK_DISABLE
+#define __HAL_RCC_JPEG_FORCE_RESET              __HAL_RCC_JPGDECRST_FORCE_RESET
+#define __HAL_RCC_JPEG_RELEASE_RESET            __HAL_RCC_JPGDECRST_RELEASE_RESET
+#define __HAL_RCC_JPEG_CLK_SLEEP_ENABLE         __HAL_RCC_JPGDEC_CLK_SLEEP_ENABLE
+#define __HAL_RCC_JPEG_CLK_SLEEP_DISABLE        __HAL_RCC_JPGDEC_CLK_SLEEP_DISABLE
+#endif /* STM32H7 */
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_SYSCFG_Aliased_Defines HAL SYSCFG Aliased Defines maintained for legacy purpose
+  * @{
+  */
+
+#define HAL_SYSCFG_FASTMODEPLUS_I2C_PA9    I2C_FASTMODEPLUS_PA9
+#define HAL_SYSCFG_FASTMODEPLUS_I2C_PA10   I2C_FASTMODEPLUS_PA10
+#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB6    I2C_FASTMODEPLUS_PB6
+#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB7    I2C_FASTMODEPLUS_PB7
+#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB8    I2C_FASTMODEPLUS_PB8
+#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB9    I2C_FASTMODEPLUS_PB9
+#define HAL_SYSCFG_FASTMODEPLUS_I2C1       I2C_FASTMODEPLUS_I2C1
+#define HAL_SYSCFG_FASTMODEPLUS_I2C2       I2C_FASTMODEPLUS_I2C2
+#define HAL_SYSCFG_FASTMODEPLUS_I2C3       I2C_FASTMODEPLUS_I2C3
+#if defined(STM32G4)
+
+#define HAL_SYSCFG_EnableIOAnalogSwitchBooster    HAL_SYSCFG_EnableIOSwitchBooster
+#define HAL_SYSCFG_DisableIOAnalogSwitchBooster   HAL_SYSCFG_DisableIOSwitchBooster
+#define HAL_SYSCFG_EnableIOAnalogSwitchVDD        HAL_SYSCFG_EnableIOSwitchVDD
+#define HAL_SYSCFG_DisableIOAnalogSwitchVDD       HAL_SYSCFG_DisableIOSwitchVDD
+#endif /* STM32G4 */
+
+
+/**
+  * @}
+  */
+
+
+/** @defgroup LL_FMC_Aliased_Defines LL FMC Aliased Defines maintained for compatibility purpose
+  * @{
+  */
+#if defined(STM32L4) || defined(STM32F7) || defined(STM32H7) || defined(STM32G4)
+#define FMC_NAND_PCC_WAIT_FEATURE_DISABLE       FMC_NAND_WAIT_FEATURE_DISABLE
+#define FMC_NAND_PCC_WAIT_FEATURE_ENABLE        FMC_NAND_WAIT_FEATURE_ENABLE
+#define FMC_NAND_PCC_MEM_BUS_WIDTH_8            FMC_NAND_MEM_BUS_WIDTH_8
+#define FMC_NAND_PCC_MEM_BUS_WIDTH_16           FMC_NAND_MEM_BUS_WIDTH_16
+#elif defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4)
+#define FMC_NAND_WAIT_FEATURE_DISABLE           FMC_NAND_PCC_WAIT_FEATURE_DISABLE
+#define FMC_NAND_WAIT_FEATURE_ENABLE            FMC_NAND_PCC_WAIT_FEATURE_ENABLE
+#define FMC_NAND_MEM_BUS_WIDTH_8                FMC_NAND_PCC_MEM_BUS_WIDTH_8
+#define FMC_NAND_MEM_BUS_WIDTH_16               FMC_NAND_PCC_MEM_BUS_WIDTH_16
+#endif
+/**
+  * @}
+  */
+
+/** @defgroup LL_FSMC_Aliased_Defines LL FSMC Aliased Defines maintained for legacy purpose
+  * @{
+  */
+
+#define FSMC_NORSRAM_TYPEDEF                      FSMC_NORSRAM_TypeDef
+#define FSMC_NORSRAM_EXTENDED_TYPEDEF             FSMC_NORSRAM_EXTENDED_TypeDef
+/**
+  * @}
+  */
+
+/** @defgroup HAL_GPIO_Aliased_Macros HAL GPIO Aliased Macros maintained for legacy purpose
+  * @{
+  */
+#define GET_GPIO_SOURCE                           GPIO_GET_INDEX
+#define GET_GPIO_INDEX                            GPIO_GET_INDEX
+
+#if defined(STM32F4)
+#define GPIO_AF12_SDMMC                           GPIO_AF12_SDIO
+#define GPIO_AF12_SDMMC1                          GPIO_AF12_SDIO
+#endif
+
+#if defined(STM32F7)
+#define GPIO_AF12_SDIO                            GPIO_AF12_SDMMC1
+#define GPIO_AF12_SDMMC                           GPIO_AF12_SDMMC1
+#endif
+
+#if defined(STM32L4)
+#define GPIO_AF12_SDIO                            GPIO_AF12_SDMMC1
+#define GPIO_AF12_SDMMC                           GPIO_AF12_SDMMC1
+#endif
+
+#if defined(STM32H7)
+#define GPIO_AF7_SDIO1                            GPIO_AF7_SDMMC1
+#define GPIO_AF8_SDIO1                            GPIO_AF8_SDMMC1
+#define GPIO_AF12_SDIO1                           GPIO_AF12_SDMMC1
+#define GPIO_AF9_SDIO2                            GPIO_AF9_SDMMC2
+#define GPIO_AF10_SDIO2                           GPIO_AF10_SDMMC2
+#define GPIO_AF11_SDIO2                           GPIO_AF11_SDMMC2
+
+#if defined (STM32H743xx) || defined (STM32H753xx)  || defined (STM32H750xx) || defined (STM32H742xx) || \
+    defined (STM32H745xx) || defined (STM32H755xx)  || defined (STM32H747xx) || defined (STM32H757xx)
+#define GPIO_AF10_OTG2_HS  GPIO_AF10_OTG2_FS
+#define GPIO_AF10_OTG1_FS  GPIO_AF10_OTG1_HS
+#define GPIO_AF12_OTG2_FS  GPIO_AF12_OTG1_FS
+#endif /*STM32H743xx || STM32H753xx || STM32H750xx || STM32H742xx || STM32H745xx || STM32H755xx || STM32H747xx || STM32H757xx */
+#endif /* STM32H7 */
+
+#define GPIO_AF0_LPTIM                            GPIO_AF0_LPTIM1
+#define GPIO_AF1_LPTIM                            GPIO_AF1_LPTIM1
+#define GPIO_AF2_LPTIM                            GPIO_AF2_LPTIM1
+
+#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || defined(STM32G4) || defined(STM32H7) || defined(STM32WB) || defined(STM32U5)
+#define  GPIO_SPEED_LOW                           GPIO_SPEED_FREQ_LOW
+#define  GPIO_SPEED_MEDIUM                        GPIO_SPEED_FREQ_MEDIUM
+#define  GPIO_SPEED_FAST                          GPIO_SPEED_FREQ_HIGH
+#define  GPIO_SPEED_HIGH                          GPIO_SPEED_FREQ_VERY_HIGH
+#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 || STM32G4 || STM32H7 || STM32WB || STM32U5*/
+
+#if defined(STM32L1)
+#define  GPIO_SPEED_VERY_LOW    GPIO_SPEED_FREQ_LOW
+#define  GPIO_SPEED_LOW         GPIO_SPEED_FREQ_MEDIUM
+#define  GPIO_SPEED_MEDIUM      GPIO_SPEED_FREQ_HIGH
+#define  GPIO_SPEED_HIGH        GPIO_SPEED_FREQ_VERY_HIGH
+#endif /* STM32L1 */
+
+#if defined(STM32F0) || defined(STM32F3) || defined(STM32F1)
+#define  GPIO_SPEED_LOW    GPIO_SPEED_FREQ_LOW
+#define  GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM
+#define  GPIO_SPEED_HIGH   GPIO_SPEED_FREQ_HIGH
+#endif /* STM32F0 || STM32F3 || STM32F1 */
+
+#define GPIO_AF6_DFSDM                            GPIO_AF6_DFSDM1
+
+#if defined(STM32U5)
+#define GPIO_AF0_RTC_50Hz                         GPIO_AF0_RTC_50HZ
+#endif /* STM32U5 */
+/**
+  * @}
+  */
+
+/** @defgroup HAL_GTZC_Aliased_Defines HAL GTZC Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#if defined(STM32U5)
+#define GTZC_PERIPH_DCMI                      GTZC_PERIPH_DCMI_PSSI
+#endif /* STM32U5 */
+/**
+  * @}
+  */
+
+/** @defgroup HAL_HRTIM_Aliased_Macros HAL HRTIM Aliased Macros maintained for legacy purpose
+  * @{
+  */
+#define HRTIM_TIMDELAYEDPROTECTION_DISABLED           HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DISABLED
+#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_EEV68  HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_EEV6
+#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_EEV68  HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_EEV6
+#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV68  HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV6
+#define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV68     HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6
+#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_DEEV7
+#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_DEEV7
+#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV79  HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV7
+#define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV79     HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7
+
+#define __HAL_HRTIM_SetCounter        __HAL_HRTIM_SETCOUNTER
+#define __HAL_HRTIM_GetCounter        __HAL_HRTIM_GETCOUNTER
+#define __HAL_HRTIM_SetPeriod         __HAL_HRTIM_SETPERIOD
+#define __HAL_HRTIM_GetPeriod         __HAL_HRTIM_GETPERIOD
+#define __HAL_HRTIM_SetClockPrescaler __HAL_HRTIM_SETCLOCKPRESCALER
+#define __HAL_HRTIM_GetClockPrescaler __HAL_HRTIM_GETCLOCKPRESCALER
+#define __HAL_HRTIM_SetCompare        __HAL_HRTIM_SETCOMPARE
+#define __HAL_HRTIM_GetCompare        __HAL_HRTIM_GETCOMPARE
+
+#if defined(STM32G4)
+#define HAL_HRTIM_ExternalEventCounterConfig    HAL_HRTIM_ExtEventCounterConfig
+#define HAL_HRTIM_ExternalEventCounterEnable    HAL_HRTIM_ExtEventCounterEnable
+#define HAL_HRTIM_ExternalEventCounterDisable   HAL_HRTIM_ExtEventCounterDisable
+#define HAL_HRTIM_ExternalEventCounterReset     HAL_HRTIM_ExtEventCounterReset
+#define HRTIM_TIMEEVENT_A                       HRTIM_EVENTCOUNTER_A
+#define HRTIM_TIMEEVENT_B                       HRTIM_EVENTCOUNTER_B
+#define HRTIM_TIMEEVENTRESETMODE_UNCONDITIONAL  HRTIM_EVENTCOUNTER_RSTMODE_UNCONDITIONAL
+#define HRTIM_TIMEEVENTRESETMODE_CONDITIONAL    HRTIM_EVENTCOUNTER_RSTMODE_CONDITIONAL
+#endif /* STM32G4 */
+
+#if defined(STM32H7)
+#define HRTIM_OUTPUTSET_TIMAEV1_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTSET_TIMAEV2_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTSET_TIMAEV3_TIMCCMP2 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTSET_TIMAEV4_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTSET_TIMAEV5_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTSET_TIMAEV6_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTSET_TIMAEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTSET_TIMAEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTSET_TIMAEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9
+#define HRTIM_OUTPUTSET_TIMBEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTSET_TIMBEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTSET_TIMBEV3_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTSET_TIMBEV4_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTSET_TIMBEV5_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTSET_TIMBEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTSET_TIMBEV7_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTSET_TIMBEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTSET_TIMBEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9
+#define HRTIM_OUTPUTSET_TIMCEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTSET_TIMCEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTSET_TIMCEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTSET_TIMCEV4_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTSET_TIMCEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTSET_TIMCEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTSET_TIMCEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTSET_TIMCEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTSET_TIMCEV9_TIMFCMP2 HRTIM_OUTPUTSET_TIMEV_9
+#define HRTIM_OUTPUTSET_TIMDEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTSET_TIMDEV2_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTSET_TIMDEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTSET_TIMDEV4_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTSET_TIMDEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTSET_TIMDEV6_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTSET_TIMDEV7_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTSET_TIMDEV8_TIMFCMP1 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTSET_TIMDEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9
+#define HRTIM_OUTPUTSET_TIMEEV1_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTSET_TIMEEV2_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTSET_TIMEEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTSET_TIMEEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTSET_TIMEEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTSET_TIMEEV6_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTSET_TIMEEV7_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTSET_TIMEEV8_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTSET_TIMEEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9
+#define HRTIM_OUTPUTSET_TIMFEV1_TIMACMP3 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTSET_TIMFEV2_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTSET_TIMFEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTSET_TIMFEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTSET_TIMFEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTSET_TIMFEV6_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTSET_TIMFEV7_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTSET_TIMFEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTSET_TIMFEV9_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_9
+
+#define HRTIM_OUTPUTRESET_TIMAEV1_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTRESET_TIMAEV2_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTRESET_TIMAEV3_TIMCCMP2 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTRESET_TIMAEV4_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTRESET_TIMAEV5_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTRESET_TIMAEV6_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTRESET_TIMAEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTRESET_TIMAEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTRESET_TIMAEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9
+#define HRTIM_OUTPUTRESET_TIMBEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTRESET_TIMBEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTRESET_TIMBEV3_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTRESET_TIMBEV4_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTRESET_TIMBEV5_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTRESET_TIMBEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTRESET_TIMBEV7_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTRESET_TIMBEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTRESET_TIMBEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9
+#define HRTIM_OUTPUTRESET_TIMCEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTRESET_TIMCEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTRESET_TIMCEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTRESET_TIMCEV4_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTRESET_TIMCEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTRESET_TIMCEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTRESET_TIMCEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTRESET_TIMCEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTRESET_TIMCEV9_TIMFCMP2 HRTIM_OUTPUTSET_TIMEV_9
+#define HRTIM_OUTPUTRESET_TIMDEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTRESET_TIMDEV2_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTRESET_TIMDEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTRESET_TIMDEV4_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTRESET_TIMDEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTRESET_TIMDEV6_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTRESET_TIMDEV7_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTRESET_TIMDEV8_TIMFCMP1 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTRESET_TIMDEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9
+#define HRTIM_OUTPUTRESET_TIMEEV1_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTRESET_TIMEEV2_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTRESET_TIMEEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTRESET_TIMEEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTRESET_TIMEEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTRESET_TIMEEV6_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTRESET_TIMEEV7_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTRESET_TIMEEV8_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTRESET_TIMEEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9
+#define HRTIM_OUTPUTRESET_TIMFEV1_TIMACMP3 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTRESET_TIMFEV2_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTRESET_TIMFEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTRESET_TIMFEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTRESET_TIMFEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTRESET_TIMFEV6_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTRESET_TIMFEV7_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTRESET_TIMFEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTRESET_TIMFEV9_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_9
+#endif /* STM32H7 */
+
+#if defined(STM32F3)
+/** @brief Constants defining available sources associated to external events.
+  */
+#define HRTIM_EVENTSRC_1              (0x00000000U)
+#define HRTIM_EVENTSRC_2              (HRTIM_EECR1_EE1SRC_0)
+#define HRTIM_EVENTSRC_3              (HRTIM_EECR1_EE1SRC_1)
+#define HRTIM_EVENTSRC_4              (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0)
+
+/** @brief Constants defining the DLL calibration periods (in micro seconds)
+  */
+#define HRTIM_CALIBRATIONRATE_7300             0x00000000U
+#define HRTIM_CALIBRATIONRATE_910              (HRTIM_DLLCR_CALRTE_0)
+#define HRTIM_CALIBRATIONRATE_114              (HRTIM_DLLCR_CALRTE_1)
+#define HRTIM_CALIBRATIONRATE_14               (HRTIM_DLLCR_CALRTE_1 | HRTIM_DLLCR_CALRTE_0)
+
+#endif /* STM32F3 */
+/**
+  * @}
+  */
+
+/** @defgroup HAL_I2C_Aliased_Defines HAL I2C Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define I2C_DUALADDRESS_DISABLED                I2C_DUALADDRESS_DISABLE
+#define I2C_DUALADDRESS_ENABLED                 I2C_DUALADDRESS_ENABLE
+#define I2C_GENERALCALL_DISABLED                I2C_GENERALCALL_DISABLE
+#define I2C_GENERALCALL_ENABLED                 I2C_GENERALCALL_ENABLE
+#define I2C_NOSTRETCH_DISABLED                  I2C_NOSTRETCH_DISABLE
+#define I2C_NOSTRETCH_ENABLED                   I2C_NOSTRETCH_ENABLE
+#define I2C_ANALOGFILTER_ENABLED                I2C_ANALOGFILTER_ENABLE
+#define I2C_ANALOGFILTER_DISABLED               I2C_ANALOGFILTER_DISABLE
+#if defined(STM32F0) || defined(STM32F1) || defined(STM32F3) || defined(STM32G0) || defined(STM32L4) || defined(STM32L1) || defined(STM32F7)
+#define HAL_I2C_STATE_MEM_BUSY_TX               HAL_I2C_STATE_BUSY_TX
+#define HAL_I2C_STATE_MEM_BUSY_RX               HAL_I2C_STATE_BUSY_RX
+#define HAL_I2C_STATE_MASTER_BUSY_TX            HAL_I2C_STATE_BUSY_TX
+#define HAL_I2C_STATE_MASTER_BUSY_RX            HAL_I2C_STATE_BUSY_RX
+#define HAL_I2C_STATE_SLAVE_BUSY_TX             HAL_I2C_STATE_BUSY_TX
+#define HAL_I2C_STATE_SLAVE_BUSY_RX             HAL_I2C_STATE_BUSY_RX
+#endif
+/**
+  * @}
+  */
+
+/** @defgroup HAL_IRDA_Aliased_Defines HAL IRDA Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define IRDA_ONE_BIT_SAMPLE_DISABLED            IRDA_ONE_BIT_SAMPLE_DISABLE
+#define IRDA_ONE_BIT_SAMPLE_ENABLED             IRDA_ONE_BIT_SAMPLE_ENABLE
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_IWDG_Aliased_Defines HAL IWDG Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define KR_KEY_RELOAD                   IWDG_KEY_RELOAD
+#define KR_KEY_ENABLE                   IWDG_KEY_ENABLE
+#define KR_KEY_EWA                      IWDG_KEY_WRITE_ACCESS_ENABLE
+#define KR_KEY_DWA                      IWDG_KEY_WRITE_ACCESS_DISABLE
+/**
+  * @}
+  */
+
+/** @defgroup HAL_LPTIM_Aliased_Defines HAL LPTIM Aliased Defines maintained for legacy purpose
+  * @{
+  */
+
+#define LPTIM_CLOCKSAMPLETIME_DIRECTTRANSISTION LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION
+#define LPTIM_CLOCKSAMPLETIME_2TRANSISTIONS     LPTIM_CLOCKSAMPLETIME_2TRANSITIONS
+#define LPTIM_CLOCKSAMPLETIME_4TRANSISTIONS     LPTIM_CLOCKSAMPLETIME_4TRANSITIONS
+#define LPTIM_CLOCKSAMPLETIME_8TRANSISTIONS     LPTIM_CLOCKSAMPLETIME_8TRANSITIONS
+
+#define LPTIM_CLOCKPOLARITY_RISINGEDGE          LPTIM_CLOCKPOLARITY_RISING
+#define LPTIM_CLOCKPOLARITY_FALLINGEDGE         LPTIM_CLOCKPOLARITY_FALLING
+#define LPTIM_CLOCKPOLARITY_BOTHEDGES           LPTIM_CLOCKPOLARITY_RISING_FALLING
+
+#define LPTIM_TRIGSAMPLETIME_DIRECTTRANSISTION  LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION
+#define LPTIM_TRIGSAMPLETIME_2TRANSISTIONS      LPTIM_TRIGSAMPLETIME_2TRANSITIONS
+#define LPTIM_TRIGSAMPLETIME_4TRANSISTIONS      LPTIM_TRIGSAMPLETIME_4TRANSITIONS
+#define LPTIM_TRIGSAMPLETIME_8TRANSISTIONS      LPTIM_TRIGSAMPLETIME_8TRANSITIONS
+
+/* The following 3 definition have also been present in a temporary version of lptim.h */
+/* They need to be renamed also to the right name, just in case */
+#define LPTIM_TRIGSAMPLETIME_2TRANSITION        LPTIM_TRIGSAMPLETIME_2TRANSITIONS
+#define LPTIM_TRIGSAMPLETIME_4TRANSITION        LPTIM_TRIGSAMPLETIME_4TRANSITIONS
+#define LPTIM_TRIGSAMPLETIME_8TRANSITION        LPTIM_TRIGSAMPLETIME_8TRANSITIONS
+
+
+/** @defgroup HAL_LPTIM_Aliased_Defines HAL LPTIM Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define HAL_LPTIM_ReadCompare      HAL_LPTIM_ReadCapturedValue
+/**
+  * @}
+  */
+
+#if defined(STM32U5)
+#define LPTIM_ISR_CC1        LPTIM_ISR_CC1IF
+#define LPTIM_ISR_CC2        LPTIM_ISR_CC2IF
+#define LPTIM_CHANNEL_ALL    0x00000000U
+#endif /* STM32U5 */
+/**
+  * @}
+  */
+
+/** @defgroup HAL_NAND_Aliased_Defines HAL NAND Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define HAL_NAND_Read_Page              HAL_NAND_Read_Page_8b
+#define HAL_NAND_Write_Page             HAL_NAND_Write_Page_8b
+#define HAL_NAND_Read_SpareArea         HAL_NAND_Read_SpareArea_8b
+#define HAL_NAND_Write_SpareArea        HAL_NAND_Write_SpareArea_8b
+
+#define NAND_AddressTypedef             NAND_AddressTypeDef
+
+#define __ARRAY_ADDRESS                 ARRAY_ADDRESS
+#define __ADDR_1st_CYCLE                ADDR_1ST_CYCLE
+#define __ADDR_2nd_CYCLE                ADDR_2ND_CYCLE
+#define __ADDR_3rd_CYCLE                ADDR_3RD_CYCLE
+#define __ADDR_4th_CYCLE                ADDR_4TH_CYCLE
+/**
+  * @}
+  */
+
+/** @defgroup HAL_NOR_Aliased_Defines HAL NOR Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define NOR_StatusTypedef              HAL_NOR_StatusTypeDef
+#define NOR_SUCCESS                    HAL_NOR_STATUS_SUCCESS
+#define NOR_ONGOING                    HAL_NOR_STATUS_ONGOING
+#define NOR_ERROR                      HAL_NOR_STATUS_ERROR
+#define NOR_TIMEOUT                    HAL_NOR_STATUS_TIMEOUT
+
+#define __NOR_WRITE                    NOR_WRITE
+#define __NOR_ADDR_SHIFT               NOR_ADDR_SHIFT
+/**
+  * @}
+  */
+
+/** @defgroup HAL_OPAMP_Aliased_Defines HAL OPAMP Aliased Defines maintained for legacy purpose
+  * @{
+  */
+
+#define OPAMP_NONINVERTINGINPUT_VP0           OPAMP_NONINVERTINGINPUT_IO0
+#define OPAMP_NONINVERTINGINPUT_VP1           OPAMP_NONINVERTINGINPUT_IO1
+#define OPAMP_NONINVERTINGINPUT_VP2           OPAMP_NONINVERTINGINPUT_IO2
+#define OPAMP_NONINVERTINGINPUT_VP3           OPAMP_NONINVERTINGINPUT_IO3
+
+#define OPAMP_SEC_NONINVERTINGINPUT_VP0       OPAMP_SEC_NONINVERTINGINPUT_IO0
+#define OPAMP_SEC_NONINVERTINGINPUT_VP1       OPAMP_SEC_NONINVERTINGINPUT_IO1
+#define OPAMP_SEC_NONINVERTINGINPUT_VP2       OPAMP_SEC_NONINVERTINGINPUT_IO2
+#define OPAMP_SEC_NONINVERTINGINPUT_VP3       OPAMP_SEC_NONINVERTINGINPUT_IO3
+
+#define OPAMP_INVERTINGINPUT_VM0              OPAMP_INVERTINGINPUT_IO0
+#define OPAMP_INVERTINGINPUT_VM1              OPAMP_INVERTINGINPUT_IO1
+
+#define IOPAMP_INVERTINGINPUT_VM0             OPAMP_INVERTINGINPUT_IO0
+#define IOPAMP_INVERTINGINPUT_VM1             OPAMP_INVERTINGINPUT_IO1
+
+#define OPAMP_SEC_INVERTINGINPUT_VM0          OPAMP_SEC_INVERTINGINPUT_IO0
+#define OPAMP_SEC_INVERTINGINPUT_VM1          OPAMP_SEC_INVERTINGINPUT_IO1
+
+#define OPAMP_INVERTINGINPUT_VINM             OPAMP_SEC_INVERTINGINPUT_IO1
+
+#define OPAMP_PGACONNECT_NO                   OPAMP_PGA_CONNECT_INVERTINGINPUT_NO
+#define OPAMP_PGACONNECT_VM0                  OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0
+#define OPAMP_PGACONNECT_VM1                  OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1
+
+#if defined(STM32L1) || defined(STM32L4) || defined(STM32L5) || defined(STM32H7) || defined(STM32G4)
+#define HAL_OPAMP_MSP_INIT_CB_ID       HAL_OPAMP_MSPINIT_CB_ID
+#define HAL_OPAMP_MSP_DEINIT_CB_ID     HAL_OPAMP_MSPDEINIT_CB_ID
+#endif
+
+#if defined(STM32L4) || defined(STM32L5)
+#define OPAMP_POWERMODE_NORMAL                OPAMP_POWERMODE_NORMALPOWER
+#elif defined(STM32G4)
+#define OPAMP_POWERMODE_NORMAL                OPAMP_POWERMODE_NORMALSPEED
+#endif
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_I2S_Aliased_Defines HAL I2S Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define I2S_STANDARD_PHILLIPS      I2S_STANDARD_PHILIPS
+
+#if defined(STM32H7)
+#define I2S_IT_TXE               I2S_IT_TXP
+#define I2S_IT_RXNE              I2S_IT_RXP
+
+#define I2S_FLAG_TXE             I2S_FLAG_TXP
+#define I2S_FLAG_RXNE            I2S_FLAG_RXP
+#endif
+
+#if defined(STM32F7)
+#define I2S_CLOCK_SYSCLK           I2S_CLOCK_PLL
+#endif
+/**
+  * @}
+  */
+
+/** @defgroup HAL_PCCARD_Aliased_Defines HAL PCCARD Aliased Defines maintained for legacy purpose
+  * @{
+  */
+
+/* Compact Flash-ATA registers description */
+#define CF_DATA                       ATA_DATA
+#define CF_SECTOR_COUNT               ATA_SECTOR_COUNT
+#define CF_SECTOR_NUMBER              ATA_SECTOR_NUMBER
+#define CF_CYLINDER_LOW               ATA_CYLINDER_LOW
+#define CF_CYLINDER_HIGH              ATA_CYLINDER_HIGH
+#define CF_CARD_HEAD                  ATA_CARD_HEAD
+#define CF_STATUS_CMD                 ATA_STATUS_CMD
+#define CF_STATUS_CMD_ALTERNATE       ATA_STATUS_CMD_ALTERNATE
+#define CF_COMMON_DATA_AREA           ATA_COMMON_DATA_AREA
+
+/* Compact Flash-ATA commands */
+#define CF_READ_SECTOR_CMD            ATA_READ_SECTOR_CMD
+#define CF_WRITE_SECTOR_CMD           ATA_WRITE_SECTOR_CMD
+#define CF_ERASE_SECTOR_CMD           ATA_ERASE_SECTOR_CMD
+#define CF_IDENTIFY_CMD               ATA_IDENTIFY_CMD
+
+#define PCCARD_StatusTypedef          HAL_PCCARD_StatusTypeDef
+#define PCCARD_SUCCESS                HAL_PCCARD_STATUS_SUCCESS
+#define PCCARD_ONGOING                HAL_PCCARD_STATUS_ONGOING
+#define PCCARD_ERROR                  HAL_PCCARD_STATUS_ERROR
+#define PCCARD_TIMEOUT                HAL_PCCARD_STATUS_TIMEOUT
+/**
+  * @}
+  */
+
+/** @defgroup HAL_RTC_Aliased_Defines HAL RTC Aliased Defines maintained for legacy purpose
+  * @{
+  */
+
+#define FORMAT_BIN                  RTC_FORMAT_BIN
+#define FORMAT_BCD                  RTC_FORMAT_BCD
+
+#define RTC_ALARMSUBSECONDMASK_None     RTC_ALARMSUBSECONDMASK_NONE
+#define RTC_TAMPERERASEBACKUP_DISABLED  RTC_TAMPER_ERASE_BACKUP_DISABLE
+#define RTC_TAMPERMASK_FLAG_DISABLED    RTC_TAMPERMASK_FLAG_DISABLE
+#define RTC_TAMPERMASK_FLAG_ENABLED     RTC_TAMPERMASK_FLAG_ENABLE
+
+#define RTC_MASKTAMPERFLAG_DISABLED     RTC_TAMPERMASK_FLAG_DISABLE
+#define RTC_MASKTAMPERFLAG_ENABLED      RTC_TAMPERMASK_FLAG_ENABLE
+#define RTC_TAMPERERASEBACKUP_ENABLED   RTC_TAMPER_ERASE_BACKUP_ENABLE
+#define RTC_TAMPER1_2_INTERRUPT         RTC_ALL_TAMPER_INTERRUPT
+#define RTC_TAMPER1_2_3_INTERRUPT       RTC_ALL_TAMPER_INTERRUPT
+
+#define RTC_TIMESTAMPPIN_PC13  RTC_TIMESTAMPPIN_DEFAULT
+#define RTC_TIMESTAMPPIN_PA0 RTC_TIMESTAMPPIN_POS1
+#define RTC_TIMESTAMPPIN_PI8 RTC_TIMESTAMPPIN_POS1
+#define RTC_TIMESTAMPPIN_PC1   RTC_TIMESTAMPPIN_POS2
+
+#define RTC_OUTPUT_REMAP_PC13  RTC_OUTPUT_REMAP_NONE
+#define RTC_OUTPUT_REMAP_PB14  RTC_OUTPUT_REMAP_POS1
+#define RTC_OUTPUT_REMAP_PB2   RTC_OUTPUT_REMAP_POS1
+
+#define RTC_TAMPERPIN_PC13 RTC_TAMPERPIN_DEFAULT
+#define RTC_TAMPERPIN_PA0  RTC_TAMPERPIN_POS1
+#define RTC_TAMPERPIN_PI8  RTC_TAMPERPIN_POS1
+
+#if defined(STM32H7)
+#define RTC_TAMPCR_TAMPXE          RTC_TAMPER_X
+#define RTC_TAMPCR_TAMPXIE         RTC_TAMPER_X_INTERRUPT
+
+#define RTC_TAMPER1_INTERRUPT      RTC_IT_TAMP1
+#define RTC_TAMPER2_INTERRUPT      RTC_IT_TAMP2
+#define RTC_TAMPER3_INTERRUPT      RTC_IT_TAMP3
+#define RTC_ALL_TAMPER_INTERRUPT   RTC_IT_TAMPALL
+#endif /* STM32H7 */
+
+/**
+  * @}
+  */
+
+
+/** @defgroup HAL_SMARTCARD_Aliased_Defines HAL SMARTCARD Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define SMARTCARD_NACK_ENABLED                  SMARTCARD_NACK_ENABLE
+#define SMARTCARD_NACK_DISABLED                 SMARTCARD_NACK_DISABLE
+
+#define SMARTCARD_ONEBIT_SAMPLING_DISABLED      SMARTCARD_ONE_BIT_SAMPLE_DISABLE
+#define SMARTCARD_ONEBIT_SAMPLING_ENABLED       SMARTCARD_ONE_BIT_SAMPLE_ENABLE
+#define SMARTCARD_ONEBIT_SAMPLING_DISABLE       SMARTCARD_ONE_BIT_SAMPLE_DISABLE
+#define SMARTCARD_ONEBIT_SAMPLING_ENABLE        SMARTCARD_ONE_BIT_SAMPLE_ENABLE
+
+#define SMARTCARD_TIMEOUT_DISABLED              SMARTCARD_TIMEOUT_DISABLE
+#define SMARTCARD_TIMEOUT_ENABLED               SMARTCARD_TIMEOUT_ENABLE
+
+#define SMARTCARD_LASTBIT_DISABLED              SMARTCARD_LASTBIT_DISABLE
+#define SMARTCARD_LASTBIT_ENABLED               SMARTCARD_LASTBIT_ENABLE
+/**
+  * @}
+  */
+
+
+/** @defgroup HAL_SMBUS_Aliased_Defines HAL SMBUS Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define SMBUS_DUALADDRESS_DISABLED      SMBUS_DUALADDRESS_DISABLE
+#define SMBUS_DUALADDRESS_ENABLED       SMBUS_DUALADDRESS_ENABLE
+#define SMBUS_GENERALCALL_DISABLED      SMBUS_GENERALCALL_DISABLE
+#define SMBUS_GENERALCALL_ENABLED       SMBUS_GENERALCALL_ENABLE
+#define SMBUS_NOSTRETCH_DISABLED        SMBUS_NOSTRETCH_DISABLE
+#define SMBUS_NOSTRETCH_ENABLED         SMBUS_NOSTRETCH_ENABLE
+#define SMBUS_ANALOGFILTER_ENABLED      SMBUS_ANALOGFILTER_ENABLE
+#define SMBUS_ANALOGFILTER_DISABLED     SMBUS_ANALOGFILTER_DISABLE
+#define SMBUS_PEC_DISABLED              SMBUS_PEC_DISABLE
+#define SMBUS_PEC_ENABLED               SMBUS_PEC_ENABLE
+#define HAL_SMBUS_STATE_SLAVE_LISTEN    HAL_SMBUS_STATE_LISTEN
+/**
+  * @}
+  */
+
+/** @defgroup HAL_SPI_Aliased_Defines HAL SPI Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define SPI_TIMODE_DISABLED             SPI_TIMODE_DISABLE
+#define SPI_TIMODE_ENABLED              SPI_TIMODE_ENABLE
+
+#define SPI_CRCCALCULATION_DISABLED     SPI_CRCCALCULATION_DISABLE
+#define SPI_CRCCALCULATION_ENABLED      SPI_CRCCALCULATION_ENABLE
+
+#define SPI_NSS_PULSE_DISABLED          SPI_NSS_PULSE_DISABLE
+#define SPI_NSS_PULSE_ENABLED           SPI_NSS_PULSE_ENABLE
+
+#if defined(STM32H7)
+
+#define SPI_FLAG_TXE                    SPI_FLAG_TXP
+#define SPI_FLAG_RXNE                   SPI_FLAG_RXP
+
+#define SPI_IT_TXE                      SPI_IT_TXP
+#define SPI_IT_RXNE                     SPI_IT_RXP
+
+#define SPI_FRLVL_EMPTY                 SPI_RX_FIFO_0PACKET
+#define SPI_FRLVL_QUARTER_FULL          SPI_RX_FIFO_1PACKET
+#define SPI_FRLVL_HALF_FULL             SPI_RX_FIFO_2PACKET
+#define SPI_FRLVL_FULL                  SPI_RX_FIFO_3PACKET
+
+#endif /* STM32H7 */
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_TIM_Aliased_Defines HAL TIM Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define CCER_CCxE_MASK                   TIM_CCER_CCxE_MASK
+#define CCER_CCxNE_MASK                  TIM_CCER_CCxNE_MASK
+
+#define TIM_DMABase_CR1                  TIM_DMABASE_CR1
+#define TIM_DMABase_CR2                  TIM_DMABASE_CR2
+#define TIM_DMABase_SMCR                 TIM_DMABASE_SMCR
+#define TIM_DMABase_DIER                 TIM_DMABASE_DIER
+#define TIM_DMABase_SR                   TIM_DMABASE_SR
+#define TIM_DMABase_EGR                  TIM_DMABASE_EGR
+#define TIM_DMABase_CCMR1                TIM_DMABASE_CCMR1
+#define TIM_DMABase_CCMR2                TIM_DMABASE_CCMR2
+#define TIM_DMABase_CCER                 TIM_DMABASE_CCER
+#define TIM_DMABase_CNT                  TIM_DMABASE_CNT
+#define TIM_DMABase_PSC                  TIM_DMABASE_PSC
+#define TIM_DMABase_ARR                  TIM_DMABASE_ARR
+#define TIM_DMABase_RCR                  TIM_DMABASE_RCR
+#define TIM_DMABase_CCR1                 TIM_DMABASE_CCR1
+#define TIM_DMABase_CCR2                 TIM_DMABASE_CCR2
+#define TIM_DMABase_CCR3                 TIM_DMABASE_CCR3
+#define TIM_DMABase_CCR4                 TIM_DMABASE_CCR4
+#define TIM_DMABase_BDTR                 TIM_DMABASE_BDTR
+#define TIM_DMABase_DCR                  TIM_DMABASE_DCR
+#define TIM_DMABase_DMAR                 TIM_DMABASE_DMAR
+#define TIM_DMABase_OR1                  TIM_DMABASE_OR1
+#define TIM_DMABase_CCMR3                TIM_DMABASE_CCMR3
+#define TIM_DMABase_CCR5                 TIM_DMABASE_CCR5
+#define TIM_DMABase_CCR6                 TIM_DMABASE_CCR6
+#define TIM_DMABase_OR2                  TIM_DMABASE_OR2
+#define TIM_DMABase_OR3                  TIM_DMABASE_OR3
+#define TIM_DMABase_OR                   TIM_DMABASE_OR
+
+#define TIM_EventSource_Update           TIM_EVENTSOURCE_UPDATE
+#define TIM_EventSource_CC1              TIM_EVENTSOURCE_CC1
+#define TIM_EventSource_CC2              TIM_EVENTSOURCE_CC2
+#define TIM_EventSource_CC3              TIM_EVENTSOURCE_CC3
+#define TIM_EventSource_CC4              TIM_EVENTSOURCE_CC4
+#define TIM_EventSource_COM              TIM_EVENTSOURCE_COM
+#define TIM_EventSource_Trigger          TIM_EVENTSOURCE_TRIGGER
+#define TIM_EventSource_Break            TIM_EVENTSOURCE_BREAK
+#define TIM_EventSource_Break2           TIM_EVENTSOURCE_BREAK2
+
+#define TIM_DMABurstLength_1Transfer     TIM_DMABURSTLENGTH_1TRANSFER
+#define TIM_DMABurstLength_2Transfers    TIM_DMABURSTLENGTH_2TRANSFERS
+#define TIM_DMABurstLength_3Transfers    TIM_DMABURSTLENGTH_3TRANSFERS
+#define TIM_DMABurstLength_4Transfers    TIM_DMABURSTLENGTH_4TRANSFERS
+#define TIM_DMABurstLength_5Transfers    TIM_DMABURSTLENGTH_5TRANSFERS
+#define TIM_DMABurstLength_6Transfers    TIM_DMABURSTLENGTH_6TRANSFERS
+#define TIM_DMABurstLength_7Transfers    TIM_DMABURSTLENGTH_7TRANSFERS
+#define TIM_DMABurstLength_8Transfers    TIM_DMABURSTLENGTH_8TRANSFERS
+#define TIM_DMABurstLength_9Transfers    TIM_DMABURSTLENGTH_9TRANSFERS
+#define TIM_DMABurstLength_10Transfers   TIM_DMABURSTLENGTH_10TRANSFERS
+#define TIM_DMABurstLength_11Transfers   TIM_DMABURSTLENGTH_11TRANSFERS
+#define TIM_DMABurstLength_12Transfers   TIM_DMABURSTLENGTH_12TRANSFERS
+#define TIM_DMABurstLength_13Transfers   TIM_DMABURSTLENGTH_13TRANSFERS
+#define TIM_DMABurstLength_14Transfers   TIM_DMABURSTLENGTH_14TRANSFERS
+#define TIM_DMABurstLength_15Transfers   TIM_DMABURSTLENGTH_15TRANSFERS
+#define TIM_DMABurstLength_16Transfers   TIM_DMABURSTLENGTH_16TRANSFERS
+#define TIM_DMABurstLength_17Transfers   TIM_DMABURSTLENGTH_17TRANSFERS
+#define TIM_DMABurstLength_18Transfers   TIM_DMABURSTLENGTH_18TRANSFERS
+
+#if defined(STM32L0)
+#define TIM22_TI1_GPIO1   TIM22_TI1_GPIO
+#define TIM22_TI1_GPIO2   TIM22_TI1_GPIO
+#endif
+
+#if defined(STM32F3)
+#define IS_TIM_HALL_INTERFACE_INSTANCE   IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE
+#endif
+
+#if defined(STM32H7)
+#define TIM_TIM1_ETR_COMP1_OUT        TIM_TIM1_ETR_COMP1
+#define TIM_TIM1_ETR_COMP2_OUT        TIM_TIM1_ETR_COMP2
+#define TIM_TIM8_ETR_COMP1_OUT        TIM_TIM8_ETR_COMP1
+#define TIM_TIM8_ETR_COMP2_OUT        TIM_TIM8_ETR_COMP2
+#define TIM_TIM2_ETR_COMP1_OUT        TIM_TIM2_ETR_COMP1
+#define TIM_TIM2_ETR_COMP2_OUT        TIM_TIM2_ETR_COMP2
+#define TIM_TIM3_ETR_COMP1_OUT        TIM_TIM3_ETR_COMP1
+#define TIM_TIM1_TI1_COMP1_OUT        TIM_TIM1_TI1_COMP1
+#define TIM_TIM8_TI1_COMP2_OUT        TIM_TIM8_TI1_COMP2
+#define TIM_TIM2_TI4_COMP1_OUT        TIM_TIM2_TI4_COMP1
+#define TIM_TIM2_TI4_COMP2_OUT        TIM_TIM2_TI4_COMP2
+#define TIM_TIM2_TI4_COMP1COMP2_OUT   TIM_TIM2_TI4_COMP1_COMP2
+#define TIM_TIM3_TI1_COMP1_OUT        TIM_TIM3_TI1_COMP1
+#define TIM_TIM3_TI1_COMP2_OUT        TIM_TIM3_TI1_COMP2
+#define TIM_TIM3_TI1_COMP1COMP2_OUT   TIM_TIM3_TI1_COMP1_COMP2
+#endif
+
+#if defined(STM32U5) || defined(STM32MP2)
+#define OCREF_CLEAR_SELECT_Pos       OCREF_CLEAR_SELECT_POS
+#define OCREF_CLEAR_SELECT_Msk       OCREF_CLEAR_SELECT_MSK
+#endif
+/**
+  * @}
+  */
+
+/** @defgroup HAL_TSC_Aliased_Defines HAL TSC Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define TSC_SYNC_POL_FALL        TSC_SYNC_POLARITY_FALLING
+#define TSC_SYNC_POL_RISE_HIGH   TSC_SYNC_POLARITY_RISING
+/**
+  * @}
+  */
+
+/** @defgroup HAL_UART_Aliased_Defines HAL UART Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define UART_ONEBIT_SAMPLING_DISABLED   UART_ONE_BIT_SAMPLE_DISABLE
+#define UART_ONEBIT_SAMPLING_ENABLED    UART_ONE_BIT_SAMPLE_ENABLE
+#define UART_ONE_BIT_SAMPLE_DISABLED    UART_ONE_BIT_SAMPLE_DISABLE
+#define UART_ONE_BIT_SAMPLE_ENABLED     UART_ONE_BIT_SAMPLE_ENABLE
+
+#define __HAL_UART_ONEBIT_ENABLE        __HAL_UART_ONE_BIT_SAMPLE_ENABLE
+#define __HAL_UART_ONEBIT_DISABLE       __HAL_UART_ONE_BIT_SAMPLE_DISABLE
+
+#define __DIV_SAMPLING16                UART_DIV_SAMPLING16
+#define __DIVMANT_SAMPLING16            UART_DIVMANT_SAMPLING16
+#define __DIVFRAQ_SAMPLING16            UART_DIVFRAQ_SAMPLING16
+#define __UART_BRR_SAMPLING16           UART_BRR_SAMPLING16
+
+#define __DIV_SAMPLING8                 UART_DIV_SAMPLING8
+#define __DIVMANT_SAMPLING8             UART_DIVMANT_SAMPLING8
+#define __DIVFRAQ_SAMPLING8             UART_DIVFRAQ_SAMPLING8
+#define __UART_BRR_SAMPLING8            UART_BRR_SAMPLING8
+
+#define __DIV_LPUART                    UART_DIV_LPUART
+
+#define UART_WAKEUPMETHODE_IDLELINE     UART_WAKEUPMETHOD_IDLELINE
+#define UART_WAKEUPMETHODE_ADDRESSMARK  UART_WAKEUPMETHOD_ADDRESSMARK
+
+/**
+  * @}
+  */
+
+
+/** @defgroup HAL_USART_Aliased_Defines HAL USART Aliased Defines maintained for legacy purpose
+  * @{
+  */
+
+#define USART_CLOCK_DISABLED            USART_CLOCK_DISABLE
+#define USART_CLOCK_ENABLED             USART_CLOCK_ENABLE
+
+#define USARTNACK_ENABLED               USART_NACK_ENABLE
+#define USARTNACK_DISABLED              USART_NACK_DISABLE
+/**
+  * @}
+  */
+
+/** @defgroup HAL_WWDG_Aliased_Defines HAL WWDG Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define CFR_BASE                    WWDG_CFR_BASE
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_CAN_Aliased_Defines HAL CAN Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define CAN_FilterFIFO0             CAN_FILTER_FIFO0
+#define CAN_FilterFIFO1             CAN_FILTER_FIFO1
+#define CAN_IT_RQCP0                CAN_IT_TME
+#define CAN_IT_RQCP1                CAN_IT_TME
+#define CAN_IT_RQCP2                CAN_IT_TME
+#define INAK_TIMEOUT                CAN_TIMEOUT_VALUE
+#define SLAK_TIMEOUT                CAN_TIMEOUT_VALUE
+#define CAN_TXSTATUS_FAILED         ((uint8_t)0x00U)
+#define CAN_TXSTATUS_OK             ((uint8_t)0x01U)
+#define CAN_TXSTATUS_PENDING        ((uint8_t)0x02U)
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_ETH_Aliased_Defines HAL ETH Aliased Defines maintained for legacy purpose
+  * @{
+  */
+
+#define VLAN_TAG                ETH_VLAN_TAG
+#define MIN_ETH_PAYLOAD         ETH_MIN_ETH_PAYLOAD
+#define MAX_ETH_PAYLOAD         ETH_MAX_ETH_PAYLOAD
+#define JUMBO_FRAME_PAYLOAD     ETH_JUMBO_FRAME_PAYLOAD
+#define MACMIIAR_CR_MASK        ETH_MACMIIAR_CR_MASK
+#define MACCR_CLEAR_MASK        ETH_MACCR_CLEAR_MASK
+#define MACFCR_CLEAR_MASK       ETH_MACFCR_CLEAR_MASK
+#define DMAOMR_CLEAR_MASK       ETH_DMAOMR_CLEAR_MASK
+
+#define ETH_MMCCR              0x00000100U
+#define ETH_MMCRIR             0x00000104U
+#define ETH_MMCTIR             0x00000108U
+#define ETH_MMCRIMR            0x0000010CU
+#define ETH_MMCTIMR            0x00000110U
+#define ETH_MMCTGFSCCR         0x0000014CU
+#define ETH_MMCTGFMSCCR        0x00000150U
+#define ETH_MMCTGFCR           0x00000168U
+#define ETH_MMCRFCECR          0x00000194U
+#define ETH_MMCRFAECR          0x00000198U
+#define ETH_MMCRGUFCR          0x000001C4U
+
+#define ETH_MAC_TXFIFO_FULL                             0x02000000U  /* Tx FIFO full */
+#define ETH_MAC_TXFIFONOT_EMPTY                         0x01000000U  /* Tx FIFO not empty */
+#define ETH_MAC_TXFIFO_WRITE_ACTIVE                     0x00400000U  /* Tx FIFO write active */
+#define ETH_MAC_TXFIFO_IDLE                             0x00000000U  /* Tx FIFO read status: Idle */
+#define ETH_MAC_TXFIFO_READ                             0x00100000U  /* Tx FIFO read status: Read (transferring data to the MAC transmitter) */
+#define ETH_MAC_TXFIFO_WAITING                          0x00200000U  /* Tx FIFO read status: Waiting for TxStatus from MAC transmitter */
+#define ETH_MAC_TXFIFO_WRITING                          0x00300000U  /* Tx FIFO read status: Writing the received TxStatus or flushing the TxFIFO */
+#define ETH_MAC_TRANSMISSION_PAUSE                      0x00080000U  /* MAC transmitter in pause */
+#define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE            0x00000000U  /* MAC transmit frame controller: Idle */
+#define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING         0x00020000U  /* MAC transmit frame controller: Waiting for Status of previous frame or IFG/backoff period to be over */
+#define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF   0x00040000U  /* MAC transmit frame controller: Generating and transmitting a Pause control frame (in full duplex mode) */
+#define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING    0x00060000U  /* MAC transmit frame controller: Transferring input frame for transmission */
+#define ETH_MAC_MII_TRANSMIT_ACTIVE           0x00010000U  /* MAC MII transmit engine active */
+#define ETH_MAC_RXFIFO_EMPTY                  0x00000000U  /* Rx FIFO fill level: empty */
+#define ETH_MAC_RXFIFO_BELOW_THRESHOLD        0x00000100U  /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */
+#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD        0x00000200U  /* Rx FIFO fill level: fill-level above flow-control activate threshold */
+#define ETH_MAC_RXFIFO_FULL                   0x00000300U  /* Rx FIFO fill level: full */
+#if defined(STM32F1)
+#else
+#define ETH_MAC_READCONTROLLER_IDLE           0x00000000U  /* Rx FIFO read controller IDLE state */
+#define ETH_MAC_READCONTROLLER_READING_DATA   0x00000020U  /* Rx FIFO read controller Reading frame data */
+#define ETH_MAC_READCONTROLLER_READING_STATUS 0x00000040U  /* Rx FIFO read controller Reading frame status (or time-stamp) */
+#endif
+#define ETH_MAC_READCONTROLLER_FLUSHING       0x00000060U  /* Rx FIFO read controller Flushing the frame data and status */
+#define ETH_MAC_RXFIFO_WRITE_ACTIVE           0x00000010U  /* Rx FIFO write controller active */
+#define ETH_MAC_SMALL_FIFO_NOTACTIVE          0x00000000U  /* MAC small FIFO read / write controllers not active */
+#define ETH_MAC_SMALL_FIFO_READ_ACTIVE        0x00000002U  /* MAC small FIFO read controller active */
+#define ETH_MAC_SMALL_FIFO_WRITE_ACTIVE       0x00000004U  /* MAC small FIFO write controller active */
+#define ETH_MAC_SMALL_FIFO_RW_ACTIVE          0x00000006U  /* MAC small FIFO read / write controllers active */
+#define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE   0x00000001U  /* MAC MII receive protocol engine active */
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_DCMI_Aliased_Defines HAL DCMI Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define HAL_DCMI_ERROR_OVF      HAL_DCMI_ERROR_OVR
+#define DCMI_IT_OVF             DCMI_IT_OVR
+#define DCMI_FLAG_OVFRI         DCMI_FLAG_OVRRI
+#define DCMI_FLAG_OVFMI         DCMI_FLAG_OVRMI
+
+#define HAL_DCMI_ConfigCROP     HAL_DCMI_ConfigCrop
+#define HAL_DCMI_EnableCROP     HAL_DCMI_EnableCrop
+#define HAL_DCMI_DisableCROP    HAL_DCMI_DisableCrop
+
+/**
+  * @}
+  */
+
+#if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) \
+  || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) \
+  || defined(STM32H7)
+/** @defgroup HAL_DMA2D_Aliased_Defines HAL DMA2D Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define DMA2D_ARGB8888          DMA2D_OUTPUT_ARGB8888
+#define DMA2D_RGB888            DMA2D_OUTPUT_RGB888
+#define DMA2D_RGB565            DMA2D_OUTPUT_RGB565
+#define DMA2D_ARGB1555          DMA2D_OUTPUT_ARGB1555
+#define DMA2D_ARGB4444          DMA2D_OUTPUT_ARGB4444
+
+#define CM_ARGB8888             DMA2D_INPUT_ARGB8888
+#define CM_RGB888               DMA2D_INPUT_RGB888
+#define CM_RGB565               DMA2D_INPUT_RGB565
+#define CM_ARGB1555             DMA2D_INPUT_ARGB1555
+#define CM_ARGB4444             DMA2D_INPUT_ARGB4444
+#define CM_L8                   DMA2D_INPUT_L8
+#define CM_AL44                 DMA2D_INPUT_AL44
+#define CM_AL88                 DMA2D_INPUT_AL88
+#define CM_L4                   DMA2D_INPUT_L4
+#define CM_A8                   DMA2D_INPUT_A8
+#define CM_A4                   DMA2D_INPUT_A4
+/**
+  * @}
+  */
+#endif  /* STM32L4 ||  STM32F7 ||  STM32F4 ||  STM32H7 */
+
+#if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) \
+  || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) \
+  || defined(STM32H7) || defined(STM32U5)
+/** @defgroup DMA2D_Aliases DMA2D API Aliases
+  * @{
+  */
+#define HAL_DMA2D_DisableCLUT       HAL_DMA2D_CLUTLoading_Abort    /*!< Aliased to HAL_DMA2D_CLUTLoading_Abort
+                                                                        for compatibility with legacy code */
+/**
+  * @}
+  */
+
+#endif  /* STM32L4 ||  STM32F7 ||  STM32F4 ||  STM32H7 || STM32U5 */
+
+/** @defgroup HAL_PPP_Aliased_Defines HAL PPP Aliased Defines maintained for legacy purpose
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup HAL_CRYP_Aliased_Functions HAL CRYP Aliased Functions maintained for legacy purpose
+  * @{
+  */
+#define HAL_CRYP_ComputationCpltCallback     HAL_CRYPEx_ComputationCpltCallback
+/**
+  * @}
+  */
+
+/** @defgroup HAL_DCACHE_Aliased_Functions HAL DCACHE Aliased Functions maintained for legacy purpose
+  * @{
+  */
+
+#if defined(STM32U5)
+#define HAL_DCACHE_CleanInvalidateByAddr     HAL_DCACHE_CleanInvalidByAddr
+#define HAL_DCACHE_CleanInvalidateByAddr_IT  HAL_DCACHE_CleanInvalidByAddr_IT
+#endif /* STM32U5 */
+
+/**
+  * @}
+  */
+
+#if !defined(STM32F2)
+/** @defgroup HASH_alias HASH API alias
+  * @{
+  */
+#define HAL_HASHEx_IRQHandler   HAL_HASH_IRQHandler  /*!< Redirection for compatibility with legacy code */
+/**
+  *
+  * @}
+  */
+#endif /* STM32F2 */
+/** @defgroup HAL_HASH_Aliased_Functions HAL HASH Aliased Functions maintained for legacy purpose
+  * @{
+  */
+#define HAL_HASH_STATETypeDef        HAL_HASH_StateTypeDef
+#define HAL_HASHPhaseTypeDef         HAL_HASH_PhaseTypeDef
+#define HAL_HMAC_MD5_Finish          HAL_HASH_MD5_Finish
+#define HAL_HMAC_SHA1_Finish         HAL_HASH_SHA1_Finish
+#define HAL_HMAC_SHA224_Finish       HAL_HASH_SHA224_Finish
+#define HAL_HMAC_SHA256_Finish       HAL_HASH_SHA256_Finish
+
+/*HASH Algorithm Selection*/
+
+#define HASH_AlgoSelection_SHA1      HASH_ALGOSELECTION_SHA1
+#define HASH_AlgoSelection_SHA224    HASH_ALGOSELECTION_SHA224
+#define HASH_AlgoSelection_SHA256    HASH_ALGOSELECTION_SHA256
+#define HASH_AlgoSelection_MD5       HASH_ALGOSELECTION_MD5
+
+#define HASH_AlgoMode_HASH         HASH_ALGOMODE_HASH
+#define HASH_AlgoMode_HMAC         HASH_ALGOMODE_HMAC
+
+#define HASH_HMACKeyType_ShortKey  HASH_HMAC_KEYTYPE_SHORTKEY
+#define HASH_HMACKeyType_LongKey   HASH_HMAC_KEYTYPE_LONGKEY
+
+#if defined(STM32L4) || defined(STM32L5) || defined(STM32F2) || defined(STM32F4) || defined(STM32F7) || defined(STM32H7)
+
+#define HAL_HASH_MD5_Accumulate                HAL_HASH_MD5_Accmlt
+#define HAL_HASH_MD5_Accumulate_End            HAL_HASH_MD5_Accmlt_End
+#define HAL_HASH_MD5_Accumulate_IT             HAL_HASH_MD5_Accmlt_IT
+#define HAL_HASH_MD5_Accumulate_End_IT         HAL_HASH_MD5_Accmlt_End_IT
+
+#define HAL_HASH_SHA1_Accumulate               HAL_HASH_SHA1_Accmlt
+#define HAL_HASH_SHA1_Accumulate_End           HAL_HASH_SHA1_Accmlt_End
+#define HAL_HASH_SHA1_Accumulate_IT            HAL_HASH_SHA1_Accmlt_IT
+#define HAL_HASH_SHA1_Accumulate_End_IT        HAL_HASH_SHA1_Accmlt_End_IT
+
+#define HAL_HASHEx_SHA224_Accumulate           HAL_HASHEx_SHA224_Accmlt
+#define HAL_HASHEx_SHA224_Accumulate_End       HAL_HASHEx_SHA224_Accmlt_End
+#define HAL_HASHEx_SHA224_Accumulate_IT        HAL_HASHEx_SHA224_Accmlt_IT
+#define HAL_HASHEx_SHA224_Accumulate_End_IT    HAL_HASHEx_SHA224_Accmlt_End_IT
+
+#define HAL_HASHEx_SHA256_Accumulate           HAL_HASHEx_SHA256_Accmlt
+#define HAL_HASHEx_SHA256_Accumulate_End       HAL_HASHEx_SHA256_Accmlt_End
+#define HAL_HASHEx_SHA256_Accumulate_IT        HAL_HASHEx_SHA256_Accmlt_IT
+#define HAL_HASHEx_SHA256_Accumulate_End_IT    HAL_HASHEx_SHA256_Accmlt_End_IT
+
+#endif  /* STM32L4 || STM32L5 || STM32F2 || STM32F4 || STM32F7 || STM32H7 */
+/**
+  * @}
+  */
+
+/** @defgroup HAL_Aliased_Functions HAL Generic Aliased Functions maintained for legacy purpose
+  * @{
+  */
+#define HAL_EnableDBGSleepMode HAL_DBGMCU_EnableDBGSleepMode
+#define HAL_DisableDBGSleepMode HAL_DBGMCU_DisableDBGSleepMode
+#define HAL_EnableDBGStopMode HAL_DBGMCU_EnableDBGStopMode
+#define HAL_DisableDBGStopMode HAL_DBGMCU_DisableDBGStopMode
+#define HAL_EnableDBGStandbyMode HAL_DBGMCU_EnableDBGStandbyMode
+#define HAL_DisableDBGStandbyMode HAL_DBGMCU_DisableDBGStandbyMode
+#define HAL_DBG_LowPowerConfig(Periph, cmd) (((cmd\
+                                              )==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph))
+#define HAL_VREFINT_OutputSelect  HAL_SYSCFG_VREFINT_OutputSelect
+#define HAL_Lock_Cmd(cmd) (((cmd)==ENABLE) ? HAL_SYSCFG_Enable_Lock_VREFINT() : HAL_SYSCFG_Disable_Lock_VREFINT())
+#if defined(STM32L0)
+#else
+#define HAL_VREFINT_Cmd(cmd) (((cmd)==ENABLE)? HAL_SYSCFG_EnableVREFINT() : HAL_SYSCFG_DisableVREFINT())
+#endif
+#define HAL_ADC_EnableBuffer_Cmd(cmd)  (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT())
+#define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd\
+                                              )==ENABLE) ?  HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor())
+#if defined(STM32H7A3xx) || defined(STM32H7B3xx) || defined(STM32H7B0xx) || defined(STM32H7A3xxQ) || defined(STM32H7B3xxQ) || defined(STM32H7B0xxQ)
+#define HAL_EnableSRDomainDBGStopMode      HAL_EnableDomain3DBGStopMode
+#define HAL_DisableSRDomainDBGStopMode     HAL_DisableDomain3DBGStopMode
+#define HAL_EnableSRDomainDBGStandbyMode   HAL_EnableDomain3DBGStandbyMode
+#define HAL_DisableSRDomainDBGStandbyMode  HAL_DisableDomain3DBGStandbyMode
+#endif /* STM32H7A3xx || STM32H7B3xx || STM32H7B0xx || STM32H7A3xxQ || STM32H7B3xxQ  || STM32H7B0xxQ */
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_FLASH_Aliased_Functions HAL FLASH Aliased Functions maintained for legacy purpose
+  * @{
+  */
+#define FLASH_HalfPageProgram      HAL_FLASHEx_HalfPageProgram
+#define FLASH_EnableRunPowerDown   HAL_FLASHEx_EnableRunPowerDown
+#define FLASH_DisableRunPowerDown  HAL_FLASHEx_DisableRunPowerDown
+#define HAL_DATA_EEPROMEx_Unlock   HAL_FLASHEx_DATAEEPROM_Unlock
+#define HAL_DATA_EEPROMEx_Lock     HAL_FLASHEx_DATAEEPROM_Lock
+#define HAL_DATA_EEPROMEx_Erase    HAL_FLASHEx_DATAEEPROM_Erase
+#define HAL_DATA_EEPROMEx_Program  HAL_FLASHEx_DATAEEPROM_Program
+
+/**
+  * @}
+ */
+
+/** @defgroup HAL_I2C_Aliased_Functions HAL I2C Aliased Functions maintained for legacy purpose
+  * @{
+  */
+#define HAL_I2CEx_AnalogFilter_Config         HAL_I2CEx_ConfigAnalogFilter
+#define HAL_I2CEx_DigitalFilter_Config        HAL_I2CEx_ConfigDigitalFilter
+#define HAL_FMPI2CEx_AnalogFilter_Config      HAL_FMPI2CEx_ConfigAnalogFilter
+#define HAL_FMPI2CEx_DigitalFilter_Config     HAL_FMPI2CEx_ConfigDigitalFilter
+
+#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd\
+                                                                 )==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus))
+
+#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4) || defined(STM32L1)
+#define HAL_I2C_Master_Sequential_Transmit_IT  HAL_I2C_Master_Seq_Transmit_IT
+#define HAL_I2C_Master_Sequential_Receive_IT   HAL_I2C_Master_Seq_Receive_IT
+#define HAL_I2C_Slave_Sequential_Transmit_IT   HAL_I2C_Slave_Seq_Transmit_IT
+#define HAL_I2C_Slave_Sequential_Receive_IT    HAL_I2C_Slave_Seq_Receive_IT
+#endif /* STM32H7 || STM32WB  || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 || STM32L1 */
+#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4)|| defined(STM32L1)
+#define HAL_I2C_Master_Sequential_Transmit_DMA HAL_I2C_Master_Seq_Transmit_DMA
+#define HAL_I2C_Master_Sequential_Receive_DMA  HAL_I2C_Master_Seq_Receive_DMA
+#define HAL_I2C_Slave_Sequential_Transmit_DMA  HAL_I2C_Slave_Seq_Transmit_DMA
+#define HAL_I2C_Slave_Sequential_Receive_DMA   HAL_I2C_Slave_Seq_Receive_DMA
+#endif /* STM32H7 || STM32WB  || STM32G0 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 || STM32L1 */
+
+#if defined(STM32F4)
+#define HAL_FMPI2C_Master_Sequential_Transmit_IT  HAL_FMPI2C_Master_Seq_Transmit_IT
+#define HAL_FMPI2C_Master_Sequential_Receive_IT   HAL_FMPI2C_Master_Seq_Receive_IT
+#define HAL_FMPI2C_Slave_Sequential_Transmit_IT   HAL_FMPI2C_Slave_Seq_Transmit_IT
+#define HAL_FMPI2C_Slave_Sequential_Receive_IT    HAL_FMPI2C_Slave_Seq_Receive_IT
+#define HAL_FMPI2C_Master_Sequential_Transmit_DMA HAL_FMPI2C_Master_Seq_Transmit_DMA
+#define HAL_FMPI2C_Master_Sequential_Receive_DMA  HAL_FMPI2C_Master_Seq_Receive_DMA
+#define HAL_FMPI2C_Slave_Sequential_Transmit_DMA  HAL_FMPI2C_Slave_Seq_Transmit_DMA
+#define HAL_FMPI2C_Slave_Sequential_Receive_DMA   HAL_FMPI2C_Slave_Seq_Receive_DMA
+#endif /* STM32F4 */
+/**
+  * @}
+ */
+
+/** @defgroup HAL_PWR_Aliased HAL PWR Aliased maintained for legacy purpose
+  * @{
+  */
+
+#if defined(STM32G0)
+#define HAL_PWR_ConfigPVD                             HAL_PWREx_ConfigPVD
+#define HAL_PWR_EnablePVD                             HAL_PWREx_EnablePVD
+#define HAL_PWR_DisablePVD                            HAL_PWREx_DisablePVD
+#define HAL_PWR_PVD_IRQHandler                        HAL_PWREx_PVD_IRQHandler
+#endif
+#define HAL_PWR_PVDConfig                             HAL_PWR_ConfigPVD
+#define HAL_PWR_DisableBkUpReg                        HAL_PWREx_DisableBkUpReg
+#define HAL_PWR_DisableFlashPowerDown                 HAL_PWREx_DisableFlashPowerDown
+#define HAL_PWR_DisableVddio2Monitor                  HAL_PWREx_DisableVddio2Monitor
+#define HAL_PWR_EnableBkUpReg                         HAL_PWREx_EnableBkUpReg
+#define HAL_PWR_EnableFlashPowerDown                  HAL_PWREx_EnableFlashPowerDown
+#define HAL_PWR_EnableVddio2Monitor                   HAL_PWREx_EnableVddio2Monitor
+#define HAL_PWR_PVD_PVM_IRQHandler                    HAL_PWREx_PVD_PVM_IRQHandler
+#define HAL_PWR_PVDLevelConfig                        HAL_PWR_ConfigPVD
+#define HAL_PWR_Vddio2Monitor_IRQHandler              HAL_PWREx_Vddio2Monitor_IRQHandler
+#define HAL_PWR_Vddio2MonitorCallback                 HAL_PWREx_Vddio2MonitorCallback
+#define HAL_PWREx_ActivateOverDrive                   HAL_PWREx_EnableOverDrive
+#define HAL_PWREx_DeactivateOverDrive                 HAL_PWREx_DisableOverDrive
+#define HAL_PWREx_DisableSDADCAnalog                  HAL_PWREx_DisableSDADC
+#define HAL_PWREx_EnableSDADCAnalog                   HAL_PWREx_EnableSDADC
+#define HAL_PWREx_PVMConfig                           HAL_PWREx_ConfigPVM
+
+#define PWR_MODE_NORMAL                               PWR_PVD_MODE_NORMAL
+#define PWR_MODE_IT_RISING                            PWR_PVD_MODE_IT_RISING
+#define PWR_MODE_IT_FALLING                           PWR_PVD_MODE_IT_FALLING
+#define PWR_MODE_IT_RISING_FALLING                    PWR_PVD_MODE_IT_RISING_FALLING
+#define PWR_MODE_EVENT_RISING                         PWR_PVD_MODE_EVENT_RISING
+#define PWR_MODE_EVENT_FALLING                        PWR_PVD_MODE_EVENT_FALLING
+#define PWR_MODE_EVENT_RISING_FALLING                 PWR_PVD_MODE_EVENT_RISING_FALLING
+
+#define CR_OFFSET_BB                                  PWR_CR_OFFSET_BB
+#define CSR_OFFSET_BB                                 PWR_CSR_OFFSET_BB
+#define PMODE_BIT_NUMBER                              VOS_BIT_NUMBER
+#define CR_PMODE_BB                                   CR_VOS_BB
+
+#define DBP_BitNumber                                 DBP_BIT_NUMBER
+#define PVDE_BitNumber                                PVDE_BIT_NUMBER
+#define PMODE_BitNumber                               PMODE_BIT_NUMBER
+#define EWUP_BitNumber                                EWUP_BIT_NUMBER
+#define FPDS_BitNumber                                FPDS_BIT_NUMBER
+#define ODEN_BitNumber                                ODEN_BIT_NUMBER
+#define ODSWEN_BitNumber                              ODSWEN_BIT_NUMBER
+#define MRLVDS_BitNumber                              MRLVDS_BIT_NUMBER
+#define LPLVDS_BitNumber                              LPLVDS_BIT_NUMBER
+#define BRE_BitNumber                                 BRE_BIT_NUMBER
+
+#define PWR_MODE_EVT                                  PWR_PVD_MODE_NORMAL
+
+#if defined (STM32U5)
+#define PWR_SRAM1_PAGE1_STOP_RETENTION                PWR_SRAM1_PAGE1_STOP
+#define PWR_SRAM1_PAGE2_STOP_RETENTION                PWR_SRAM1_PAGE2_STOP
+#define PWR_SRAM1_PAGE3_STOP_RETENTION                PWR_SRAM1_PAGE3_STOP
+#define PWR_SRAM1_PAGE4_STOP_RETENTION                PWR_SRAM1_PAGE4_STOP
+#define PWR_SRAM1_PAGE5_STOP_RETENTION                PWR_SRAM1_PAGE5_STOP
+#define PWR_SRAM1_PAGE6_STOP_RETENTION                PWR_SRAM1_PAGE6_STOP
+#define PWR_SRAM1_PAGE7_STOP_RETENTION                PWR_SRAM1_PAGE7_STOP
+#define PWR_SRAM1_PAGE8_STOP_RETENTION                PWR_SRAM1_PAGE8_STOP
+#define PWR_SRAM1_PAGE9_STOP_RETENTION                PWR_SRAM1_PAGE9_STOP
+#define PWR_SRAM1_PAGE10_STOP_RETENTION               PWR_SRAM1_PAGE10_STOP
+#define PWR_SRAM1_PAGE11_STOP_RETENTION               PWR_SRAM1_PAGE11_STOP
+#define PWR_SRAM1_PAGE12_STOP_RETENTION               PWR_SRAM1_PAGE12_STOP
+#define PWR_SRAM1_FULL_STOP_RETENTION                 PWR_SRAM1_FULL_STOP
+
+#define PWR_SRAM2_PAGE1_STOP_RETENTION                PWR_SRAM2_PAGE1_STOP
+#define PWR_SRAM2_PAGE2_STOP_RETENTION                PWR_SRAM2_PAGE2_STOP
+#define PWR_SRAM2_FULL_STOP_RETENTION                 PWR_SRAM2_FULL_STOP
+
+#define PWR_SRAM3_PAGE1_STOP_RETENTION                PWR_SRAM3_PAGE1_STOP
+#define PWR_SRAM3_PAGE2_STOP_RETENTION                PWR_SRAM3_PAGE2_STOP
+#define PWR_SRAM3_PAGE3_STOP_RETENTION                PWR_SRAM3_PAGE3_STOP
+#define PWR_SRAM3_PAGE4_STOP_RETENTION                PWR_SRAM3_PAGE4_STOP
+#define PWR_SRAM3_PAGE5_STOP_RETENTION                PWR_SRAM3_PAGE5_STOP
+#define PWR_SRAM3_PAGE6_STOP_RETENTION                PWR_SRAM3_PAGE6_STOP
+#define PWR_SRAM3_PAGE7_STOP_RETENTION                PWR_SRAM3_PAGE7_STOP
+#define PWR_SRAM3_PAGE8_STOP_RETENTION                PWR_SRAM3_PAGE8_STOP
+#define PWR_SRAM3_PAGE9_STOP_RETENTION                PWR_SRAM3_PAGE9_STOP
+#define PWR_SRAM3_PAGE10_STOP_RETENTION               PWR_SRAM3_PAGE10_STOP
+#define PWR_SRAM3_PAGE11_STOP_RETENTION               PWR_SRAM3_PAGE11_STOP
+#define PWR_SRAM3_PAGE12_STOP_RETENTION               PWR_SRAM3_PAGE12_STOP
+#define PWR_SRAM3_PAGE13_STOP_RETENTION               PWR_SRAM3_PAGE13_STOP
+#define PWR_SRAM3_FULL_STOP_RETENTION                 PWR_SRAM3_FULL_STOP
+
+#define PWR_SRAM4_FULL_STOP_RETENTION                 PWR_SRAM4_FULL_STOP
+
+#define PWR_SRAM5_PAGE1_STOP_RETENTION                PWR_SRAM5_PAGE1_STOP
+#define PWR_SRAM5_PAGE2_STOP_RETENTION                PWR_SRAM5_PAGE2_STOP
+#define PWR_SRAM5_PAGE3_STOP_RETENTION                PWR_SRAM5_PAGE3_STOP
+#define PWR_SRAM5_PAGE4_STOP_RETENTION                PWR_SRAM5_PAGE4_STOP
+#define PWR_SRAM5_PAGE5_STOP_RETENTION                PWR_SRAM5_PAGE5_STOP
+#define PWR_SRAM5_PAGE6_STOP_RETENTION                PWR_SRAM5_PAGE6_STOP
+#define PWR_SRAM5_PAGE7_STOP_RETENTION                PWR_SRAM5_PAGE7_STOP
+#define PWR_SRAM5_PAGE8_STOP_RETENTION                PWR_SRAM5_PAGE8_STOP
+#define PWR_SRAM5_PAGE9_STOP_RETENTION                PWR_SRAM5_PAGE9_STOP
+#define PWR_SRAM5_PAGE10_STOP_RETENTION               PWR_SRAM5_PAGE10_STOP
+#define PWR_SRAM5_PAGE11_STOP_RETENTION               PWR_SRAM5_PAGE11_STOP
+#define PWR_SRAM5_PAGE12_STOP_RETENTION               PWR_SRAM5_PAGE12_STOP
+#define PWR_SRAM5_PAGE13_STOP_RETENTION               PWR_SRAM5_PAGE13_STOP
+#define PWR_SRAM5_FULL_STOP_RETENTION                 PWR_SRAM5_FULL_STOP
+
+#define PWR_ICACHE_FULL_STOP_RETENTION                PWR_ICACHE_FULL_STOP
+#define PWR_DCACHE1_FULL_STOP_RETENTION               PWR_DCACHE1_FULL_STOP
+#define PWR_DCACHE2_FULL_STOP_RETENTION               PWR_DCACHE2_FULL_STOP
+#define PWR_DMA2DRAM_FULL_STOP_RETENTION              PWR_DMA2DRAM_FULL_STOP
+#define PWR_PERIPHRAM_FULL_STOP_RETENTION             PWR_PERIPHRAM_FULL_STOP
+#define PWR_PKA32RAM_FULL_STOP_RETENTION              PWR_PKA32RAM_FULL_STOP
+#define PWR_GRAPHICPRAM_FULL_STOP_RETENTION           PWR_GRAPHICPRAM_FULL_STOP
+#define PWR_DSIRAM_FULL_STOP_RETENTION                PWR_DSIRAM_FULL_STOP
+
+#define PWR_SRAM2_PAGE1_STANDBY_RETENTION             PWR_SRAM2_PAGE1_STANDBY
+#define PWR_SRAM2_PAGE2_STANDBY_RETENTION             PWR_SRAM2_PAGE2_STANDBY
+#define PWR_SRAM2_FULL_STANDBY_RETENTION              PWR_SRAM2_FULL_STANDBY
+
+#define PWR_SRAM1_FULL_RUN_RETENTION                  PWR_SRAM1_FULL_RUN
+#define PWR_SRAM2_FULL_RUN_RETENTION                  PWR_SRAM2_FULL_RUN
+#define PWR_SRAM3_FULL_RUN_RETENTION                  PWR_SRAM3_FULL_RUN
+#define PWR_SRAM4_FULL_RUN_RETENTION                  PWR_SRAM4_FULL_RUN
+#define PWR_SRAM5_FULL_RUN_RETENTION                  PWR_SRAM5_FULL_RUN
+
+#define PWR_ALL_RAM_RUN_RETENTION_MASK                PWR_ALL_RAM_RUN_MASK
+#endif
+
+/**
+  * @}
+ */
+
+/** @defgroup HAL_SMBUS_Aliased_Functions HAL SMBUS Aliased Functions maintained for legacy purpose
+  * @{
+  */
+#define HAL_SMBUS_Slave_Listen_IT          HAL_SMBUS_EnableListen_IT
+#define HAL_SMBUS_SlaveAddrCallback        HAL_SMBUS_AddrCallback
+#define HAL_SMBUS_SlaveListenCpltCallback  HAL_SMBUS_ListenCpltCallback
+/**
+  * @}
+  */
+
+/** @defgroup HAL_SPI_Aliased_Functions HAL SPI Aliased Functions maintained for legacy purpose
+  * @{
+  */
+#define HAL_SPI_FlushRxFifo                HAL_SPIEx_FlushRxFifo
+/**
+  * @}
+  */
+
+/** @defgroup HAL_TIM_Aliased_Functions HAL TIM Aliased Functions maintained for legacy purpose
+  * @{
+  */
+#define HAL_TIM_DMADelayPulseCplt                       TIM_DMADelayPulseCplt
+#define HAL_TIM_DMAError                                TIM_DMAError
+#define HAL_TIM_DMACaptureCplt                          TIM_DMACaptureCplt
+#define HAL_TIMEx_DMACommutationCplt                    TIMEx_DMACommutationCplt
+#if defined(STM32H7) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4)
+#define HAL_TIM_SlaveConfigSynchronization              HAL_TIM_SlaveConfigSynchro
+#define HAL_TIM_SlaveConfigSynchronization_IT           HAL_TIM_SlaveConfigSynchro_IT
+#define HAL_TIMEx_CommutationCallback                   HAL_TIMEx_CommutCallback
+#define HAL_TIMEx_ConfigCommutationEvent                HAL_TIMEx_ConfigCommutEvent
+#define HAL_TIMEx_ConfigCommutationEvent_IT             HAL_TIMEx_ConfigCommutEvent_IT
+#define HAL_TIMEx_ConfigCommutationEvent_DMA            HAL_TIMEx_ConfigCommutEvent_DMA
+#endif /* STM32H7 || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 */
+/**
+  * @}
+  */
+
+/** @defgroup HAL_UART_Aliased_Functions HAL UART Aliased Functions maintained for legacy purpose
+  * @{
+  */
+#define HAL_UART_WakeupCallback HAL_UARTEx_WakeupCallback
+/**
+  * @}
+  */
+
+/** @defgroup HAL_LTDC_Aliased_Functions HAL LTDC Aliased Functions maintained for legacy purpose
+  * @{
+  */
+#define HAL_LTDC_LineEvenCallback HAL_LTDC_LineEventCallback
+#define HAL_LTDC_Relaod           HAL_LTDC_Reload
+#define HAL_LTDC_StructInitFromVideoConfig  HAL_LTDCEx_StructInitFromVideoConfig
+#define HAL_LTDC_StructInitFromAdaptedCommandConfig  HAL_LTDCEx_StructInitFromAdaptedCommandConfig
+/**
+  * @}
+  */
+
+
+/** @defgroup HAL_PPP_Aliased_Functions HAL PPP Aliased Functions maintained for legacy purpose
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macros ------------------------------------------------------------*/
+
+/** @defgroup HAL_AES_Aliased_Macros HAL CRYP Aliased Macros maintained for legacy purpose
+  * @{
+  */
+#define AES_IT_CC                      CRYP_IT_CC
+#define AES_IT_ERR                     CRYP_IT_ERR
+#define AES_FLAG_CCF                   CRYP_FLAG_CCF
+/**
+  * @}
+  */
+
+/** @defgroup HAL_Aliased_Macros HAL Generic Aliased Macros maintained for legacy purpose
+  * @{
+  */
+#define __HAL_GET_BOOT_MODE                   __HAL_SYSCFG_GET_BOOT_MODE
+#define __HAL_REMAPMEMORY_FLASH               __HAL_SYSCFG_REMAPMEMORY_FLASH
+#define __HAL_REMAPMEMORY_SYSTEMFLASH         __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH
+#define __HAL_REMAPMEMORY_SRAM                __HAL_SYSCFG_REMAPMEMORY_SRAM
+#define __HAL_REMAPMEMORY_FMC                 __HAL_SYSCFG_REMAPMEMORY_FMC
+#define __HAL_REMAPMEMORY_FMC_SDRAM           __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM
+#define __HAL_REMAPMEMORY_FSMC                __HAL_SYSCFG_REMAPMEMORY_FSMC
+#define __HAL_REMAPMEMORY_QUADSPI             __HAL_SYSCFG_REMAPMEMORY_QUADSPI
+#define __HAL_FMC_BANK                        __HAL_SYSCFG_FMC_BANK
+#define __HAL_GET_FLAG                        __HAL_SYSCFG_GET_FLAG
+#define __HAL_CLEAR_FLAG                      __HAL_SYSCFG_CLEAR_FLAG
+#define __HAL_VREFINT_OUT_ENABLE              __HAL_SYSCFG_VREFINT_OUT_ENABLE
+#define __HAL_VREFINT_OUT_DISABLE             __HAL_SYSCFG_VREFINT_OUT_DISABLE
+#define __HAL_SYSCFG_SRAM2_WRP_ENABLE         __HAL_SYSCFG_SRAM2_WRP_0_31_ENABLE
+
+#define SYSCFG_FLAG_VREF_READY                SYSCFG_FLAG_VREFINT_READY
+#define SYSCFG_FLAG_RC48                      RCC_FLAG_HSI48
+#define IS_SYSCFG_FASTMODEPLUS_CONFIG         IS_I2C_FASTMODEPLUS
+#define UFB_MODE_BitNumber                    UFB_MODE_BIT_NUMBER
+#define CMP_PD_BitNumber                      CMP_PD_BIT_NUMBER
+
+/**
+  * @}
+  */
+
+
+/** @defgroup HAL_ADC_Aliased_Macros HAL ADC Aliased Macros maintained for legacy purpose
+  * @{
+  */
+#define __ADC_ENABLE                                     __HAL_ADC_ENABLE
+#define __ADC_DISABLE                                    __HAL_ADC_DISABLE
+#define __HAL_ADC_ENABLING_CONDITIONS                    ADC_ENABLING_CONDITIONS
+#define __HAL_ADC_DISABLING_CONDITIONS                   ADC_DISABLING_CONDITIONS
+#define __HAL_ADC_IS_ENABLED                             ADC_IS_ENABLE
+#define __ADC_IS_ENABLED                                 ADC_IS_ENABLE
+#define __HAL_ADC_IS_SOFTWARE_START_REGULAR              ADC_IS_SOFTWARE_START_REGULAR
+#define __HAL_ADC_IS_SOFTWARE_START_INJECTED             ADC_IS_SOFTWARE_START_INJECTED
+#define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED
+#define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR          ADC_IS_CONVERSION_ONGOING_REGULAR
+#define __HAL_ADC_IS_CONVERSION_ONGOING_INJECTED         ADC_IS_CONVERSION_ONGOING_INJECTED
+#define __HAL_ADC_IS_CONVERSION_ONGOING                  ADC_IS_CONVERSION_ONGOING
+#define __HAL_ADC_CLEAR_ERRORCODE                        ADC_CLEAR_ERRORCODE
+
+#define __HAL_ADC_GET_RESOLUTION                         ADC_GET_RESOLUTION
+#define __HAL_ADC_JSQR_RK                                ADC_JSQR_RK
+#define __HAL_ADC_CFGR_AWD1CH                            ADC_CFGR_AWD1CH_SHIFT
+#define __HAL_ADC_CFGR_AWD23CR                           ADC_CFGR_AWD23CR
+#define __HAL_ADC_CFGR_INJECT_AUTO_CONVERSION            ADC_CFGR_INJECT_AUTO_CONVERSION
+#define __HAL_ADC_CFGR_INJECT_CONTEXT_QUEUE              ADC_CFGR_INJECT_CONTEXT_QUEUE
+#define __HAL_ADC_CFGR_INJECT_DISCCONTINUOUS             ADC_CFGR_INJECT_DISCCONTINUOUS
+#define __HAL_ADC_CFGR_REG_DISCCONTINUOUS                ADC_CFGR_REG_DISCCONTINUOUS
+#define __HAL_ADC_CFGR_DISCONTINUOUS_NUM                 ADC_CFGR_DISCONTINUOUS_NUM
+#define __HAL_ADC_CFGR_AUTOWAIT                          ADC_CFGR_AUTOWAIT
+#define __HAL_ADC_CFGR_CONTINUOUS                        ADC_CFGR_CONTINUOUS
+#define __HAL_ADC_CFGR_OVERRUN                           ADC_CFGR_OVERRUN
+#define __HAL_ADC_CFGR_DMACONTREQ                        ADC_CFGR_DMACONTREQ
+#define __HAL_ADC_CFGR_EXTSEL                            ADC_CFGR_EXTSEL_SET
+#define __HAL_ADC_JSQR_JEXTSEL                           ADC_JSQR_JEXTSEL_SET
+#define __HAL_ADC_OFR_CHANNEL                            ADC_OFR_CHANNEL
+#define __HAL_ADC_DIFSEL_CHANNEL                         ADC_DIFSEL_CHANNEL
+#define __HAL_ADC_CALFACT_DIFF_SET                       ADC_CALFACT_DIFF_SET
+#define __HAL_ADC_CALFACT_DIFF_GET                       ADC_CALFACT_DIFF_GET
+#define __HAL_ADC_TRX_HIGHTHRESHOLD                      ADC_TRX_HIGHTHRESHOLD
+
+#define __HAL_ADC_OFFSET_SHIFT_RESOLUTION                ADC_OFFSET_SHIFT_RESOLUTION
+#define __HAL_ADC_AWD1THRESHOLD_SHIFT_RESOLUTION         ADC_AWD1THRESHOLD_SHIFT_RESOLUTION
+#define __HAL_ADC_AWD23THRESHOLD_SHIFT_RESOLUTION        ADC_AWD23THRESHOLD_SHIFT_RESOLUTION
+#define __HAL_ADC_COMMON_REGISTER                        ADC_COMMON_REGISTER
+#define __HAL_ADC_COMMON_CCR_MULTI                       ADC_COMMON_CCR_MULTI
+#define __HAL_ADC_MULTIMODE_IS_ENABLED                   ADC_MULTIMODE_IS_ENABLE
+#define __ADC_MULTIMODE_IS_ENABLED                       ADC_MULTIMODE_IS_ENABLE
+#define __HAL_ADC_NONMULTIMODE_OR_MULTIMODEMASTER        ADC_NONMULTIMODE_OR_MULTIMODEMASTER
+#define __HAL_ADC_COMMON_ADC_OTHER                       ADC_COMMON_ADC_OTHER
+#define __HAL_ADC_MULTI_SLAVE                            ADC_MULTI_SLAVE
+
+#define __HAL_ADC_SQR1_L                                 ADC_SQR1_L_SHIFT
+#define __HAL_ADC_JSQR_JL                                ADC_JSQR_JL_SHIFT
+#define __HAL_ADC_JSQR_RK_JL                             ADC_JSQR_RK_JL
+#define __HAL_ADC_CR1_DISCONTINUOUS_NUM                  ADC_CR1_DISCONTINUOUS_NUM
+#define __HAL_ADC_CR1_SCAN                               ADC_CR1_SCAN_SET
+#define __HAL_ADC_CONVCYCLES_MAX_RANGE                   ADC_CONVCYCLES_MAX_RANGE
+#define __HAL_ADC_CLOCK_PRESCALER_RANGE                  ADC_CLOCK_PRESCALER_RANGE
+#define __HAL_ADC_GET_CLOCK_PRESCALER                    ADC_GET_CLOCK_PRESCALER
+
+#define __HAL_ADC_SQR1                                   ADC_SQR1
+#define __HAL_ADC_SMPR1                                  ADC_SMPR1
+#define __HAL_ADC_SMPR2                                  ADC_SMPR2
+#define __HAL_ADC_SQR3_RK                                ADC_SQR3_RK
+#define __HAL_ADC_SQR2_RK                                ADC_SQR2_RK
+#define __HAL_ADC_SQR1_RK                                ADC_SQR1_RK
+#define __HAL_ADC_CR2_CONTINUOUS                         ADC_CR2_CONTINUOUS
+#define __HAL_ADC_CR1_DISCONTINUOUS                      ADC_CR1_DISCONTINUOUS
+#define __HAL_ADC_CR1_SCANCONV                           ADC_CR1_SCANCONV
+#define __HAL_ADC_CR2_EOCSelection                       ADC_CR2_EOCSelection
+#define __HAL_ADC_CR2_DMAContReq                         ADC_CR2_DMAContReq
+#define __HAL_ADC_JSQR                                   ADC_JSQR
+
+#define __HAL_ADC_CHSELR_CHANNEL                         ADC_CHSELR_CHANNEL
+#define __HAL_ADC_CFGR1_REG_DISCCONTINUOUS               ADC_CFGR1_REG_DISCCONTINUOUS
+#define __HAL_ADC_CFGR1_AUTOOFF                          ADC_CFGR1_AUTOOFF
+#define __HAL_ADC_CFGR1_AUTOWAIT                         ADC_CFGR1_AUTOWAIT
+#define __HAL_ADC_CFGR1_CONTINUOUS                       ADC_CFGR1_CONTINUOUS
+#define __HAL_ADC_CFGR1_OVERRUN                          ADC_CFGR1_OVERRUN
+#define __HAL_ADC_CFGR1_SCANDIR                          ADC_CFGR1_SCANDIR
+#define __HAL_ADC_CFGR1_DMACONTREQ                       ADC_CFGR1_DMACONTREQ
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose
+  * @{
+  */
+#define __HAL_DHR12R1_ALIGNEMENT                        DAC_DHR12R1_ALIGNMENT
+#define __HAL_DHR12R2_ALIGNEMENT                        DAC_DHR12R2_ALIGNMENT
+#define __HAL_DHR12RD_ALIGNEMENT                        DAC_DHR12RD_ALIGNMENT
+#define IS_DAC_GENERATE_WAVE                            IS_DAC_WAVE
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_DBGMCU_Aliased_Macros HAL DBGMCU Aliased Macros maintained for legacy purpose
+  * @{
+  */
+#define __HAL_FREEZE_TIM1_DBGMCU __HAL_DBGMCU_FREEZE_TIM1
+#define __HAL_UNFREEZE_TIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM1
+#define __HAL_FREEZE_TIM2_DBGMCU __HAL_DBGMCU_FREEZE_TIM2
+#define __HAL_UNFREEZE_TIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM2
+#define __HAL_FREEZE_TIM3_DBGMCU __HAL_DBGMCU_FREEZE_TIM3
+#define __HAL_UNFREEZE_TIM3_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM3
+#define __HAL_FREEZE_TIM4_DBGMCU __HAL_DBGMCU_FREEZE_TIM4
+#define __HAL_UNFREEZE_TIM4_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM4
+#define __HAL_FREEZE_TIM5_DBGMCU __HAL_DBGMCU_FREEZE_TIM5
+#define __HAL_UNFREEZE_TIM5_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM5
+#define __HAL_FREEZE_TIM6_DBGMCU __HAL_DBGMCU_FREEZE_TIM6
+#define __HAL_UNFREEZE_TIM6_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM6
+#define __HAL_FREEZE_TIM7_DBGMCU __HAL_DBGMCU_FREEZE_TIM7
+#define __HAL_UNFREEZE_TIM7_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM7
+#define __HAL_FREEZE_TIM8_DBGMCU __HAL_DBGMCU_FREEZE_TIM8
+#define __HAL_UNFREEZE_TIM8_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM8
+
+#define __HAL_FREEZE_TIM9_DBGMCU __HAL_DBGMCU_FREEZE_TIM9
+#define __HAL_UNFREEZE_TIM9_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM9
+#define __HAL_FREEZE_TIM10_DBGMCU __HAL_DBGMCU_FREEZE_TIM10
+#define __HAL_UNFREEZE_TIM10_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM10
+#define __HAL_FREEZE_TIM11_DBGMCU __HAL_DBGMCU_FREEZE_TIM11
+#define __HAL_UNFREEZE_TIM11_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM11
+#define __HAL_FREEZE_TIM12_DBGMCU __HAL_DBGMCU_FREEZE_TIM12
+#define __HAL_UNFREEZE_TIM12_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM12
+#define __HAL_FREEZE_TIM13_DBGMCU __HAL_DBGMCU_FREEZE_TIM13
+#define __HAL_UNFREEZE_TIM13_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM13
+#define __HAL_FREEZE_TIM14_DBGMCU __HAL_DBGMCU_FREEZE_TIM14
+#define __HAL_UNFREEZE_TIM14_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM14
+#define __HAL_FREEZE_CAN2_DBGMCU __HAL_DBGMCU_FREEZE_CAN2
+#define __HAL_UNFREEZE_CAN2_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN2
+
+
+#define __HAL_FREEZE_TIM15_DBGMCU __HAL_DBGMCU_FREEZE_TIM15
+#define __HAL_UNFREEZE_TIM15_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM15
+#define __HAL_FREEZE_TIM16_DBGMCU __HAL_DBGMCU_FREEZE_TIM16
+#define __HAL_UNFREEZE_TIM16_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM16
+#define __HAL_FREEZE_TIM17_DBGMCU __HAL_DBGMCU_FREEZE_TIM17
+#define __HAL_UNFREEZE_TIM17_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM17
+#define __HAL_FREEZE_RTC_DBGMCU __HAL_DBGMCU_FREEZE_RTC
+#define __HAL_UNFREEZE_RTC_DBGMCU __HAL_DBGMCU_UNFREEZE_RTC
+#if defined(STM32H7)
+#define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG1
+#define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UnFreeze_WWDG1
+#define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG1
+#define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UnFreeze_IWDG1
+#else
+#define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG
+#define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_WWDG
+#define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG
+#define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_IWDG
+#endif /* STM32H7 */
+#define __HAL_FREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT
+#define __HAL_UNFREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT
+#define __HAL_FREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT
+#define __HAL_UNFREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT
+#define __HAL_FREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT
+#define __HAL_UNFREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT
+#define __HAL_FREEZE_CAN1_DBGMCU __HAL_DBGMCU_FREEZE_CAN1
+#define __HAL_UNFREEZE_CAN1_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN1
+#define __HAL_FREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM1
+#define __HAL_UNFREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM1
+#define __HAL_FREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM2
+#define __HAL_UNFREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM2
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_COMP_Aliased_Macros HAL COMP Aliased Macros maintained for legacy purpose
+  * @{
+  */
+#if defined(STM32F3)
+#define COMP_START                                       __HAL_COMP_ENABLE
+#define COMP_STOP                                        __HAL_COMP_DISABLE
+#define COMP_LOCK                                        __HAL_COMP_LOCK
+
+#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
+#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__)   (((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \
+                                                          __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \
+                                                          __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \
+                                                          __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \
+                                                          __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__)          (((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \
+                                                          __HAL_COMP_COMP6_EXTI_ENABLE_IT())
+#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__)         (((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \
+                                                          __HAL_COMP_COMP6_EXTI_DISABLE_IT())
+#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__)               (((__FLAG__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \
+                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \
+                                                          __HAL_COMP_COMP6_EXTI_GET_FLAG())
+#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__)             (((__FLAG__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \
+                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \
+                                                          __HAL_COMP_COMP6_EXTI_CLEAR_FLAG())
+# endif
+# if defined(STM32F302xE) || defined(STM32F302xC)
+#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__)   (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \
+                                                          __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \
+                                                          __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \
+                                                          __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \
+                                                          __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__)          (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \
+                                                          __HAL_COMP_COMP6_EXTI_ENABLE_IT())
+#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__)         (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \
+                                                          __HAL_COMP_COMP6_EXTI_DISABLE_IT())
+#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__)               (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
+                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \
+                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \
+                                                          __HAL_COMP_COMP6_EXTI_GET_FLAG())
+#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__)             (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
+                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \
+                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \
+                                                          __HAL_COMP_COMP6_EXTI_CLEAR_FLAG())
+# endif
+# if defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F303xC) || defined(STM32F358xx)
+#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__)   (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_RISING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_RISING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE() : \
+                                                          __HAL_COMP_COMP7_EXTI_ENABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_RISING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_RISING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE() : \
+                                                          __HAL_COMP_COMP7_EXTI_DISABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_FALLING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_FALLING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE() : \
+                                                          __HAL_COMP_COMP7_EXTI_ENABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_FALLING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_FALLING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE() : \
+                                                          __HAL_COMP_COMP7_EXTI_DISABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__)          (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_IT() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_IT() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_IT() : \
+                                                          __HAL_COMP_COMP7_EXTI_ENABLE_IT())
+#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__)         (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_IT() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_IT() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_IT() : \
+                                                          __HAL_COMP_COMP7_EXTI_DISABLE_IT())
+#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__)               (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
+                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \
+                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_GET_FLAG() : \
+                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \
+                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_GET_FLAG() : \
+                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_GET_FLAG() : \
+                                                          __HAL_COMP_COMP7_EXTI_GET_FLAG())
+#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__)             (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
+                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \
+                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_CLEAR_FLAG() : \
+                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \
+                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_CLEAR_FLAG() : \
+                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_CLEAR_FLAG() : \
+                                                          __HAL_COMP_COMP7_EXTI_CLEAR_FLAG())
+# endif
+# if defined(STM32F373xC) ||defined(STM32F378xx)
+#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__)   (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
+                                                          __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
+                                                          __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
+                                                          __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
+                                                          __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__)          (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
+                                                          __HAL_COMP_COMP2_EXTI_ENABLE_IT())
+#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__)         (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
+                                                          __HAL_COMP_COMP2_EXTI_DISABLE_IT())
+#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__)               (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
+                                                          __HAL_COMP_COMP2_EXTI_GET_FLAG())
+#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__)             (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
+                                                          __HAL_COMP_COMP2_EXTI_CLEAR_FLAG())
+# endif
+#else
+#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__)   (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
+                                                          __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
+                                                          __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
+                                                          __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
+                                                          __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__)          (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
+                                                          __HAL_COMP_COMP2_EXTI_ENABLE_IT())
+#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__)         (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
+                                                          __HAL_COMP_COMP2_EXTI_DISABLE_IT())
+#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__)               (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
+                                                          __HAL_COMP_COMP2_EXTI_GET_FLAG())
+#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__)             (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
+                                                          __HAL_COMP_COMP2_EXTI_CLEAR_FLAG())
+#endif
+
+#define __HAL_COMP_GET_EXTI_LINE  COMP_GET_EXTI_LINE
+
+#if defined(STM32L0) || defined(STM32L4)
+/* Note: On these STM32 families, the only argument of this macro             */
+/*       is COMP_FLAG_LOCK.                                                   */
+/*       This macro is replaced by __HAL_COMP_IS_LOCKED with only HAL handle  */
+/*       argument.                                                            */
+#define __HAL_COMP_GET_FLAG(__HANDLE__, __FLAG__)  (__HAL_COMP_IS_LOCKED(__HANDLE__))
+#endif
+/**
+  * @}
+  */
+
+#if defined(STM32L0) || defined(STM32L4)
+/** @defgroup HAL_COMP_Aliased_Functions HAL COMP Aliased Functions maintained for legacy purpose
+  * @{
+  */
+#define HAL_COMP_Start_IT       HAL_COMP_Start /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */
+#define HAL_COMP_Stop_IT        HAL_COMP_Stop  /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */
+/**
+  * @}
+  */
+#endif
+
+/** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose
+  * @{
+  */
+
+#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_WAVE_NONE) || \
+                           ((WAVE) == DAC_WAVE_NOISE)|| \
+                           ((WAVE) == DAC_WAVE_TRIANGLE))
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_FLASH_Aliased_Macros HAL FLASH Aliased Macros maintained for legacy purpose
+  * @{
+  */
+
+#define IS_WRPAREA          IS_OB_WRPAREA
+#define IS_TYPEPROGRAM      IS_FLASH_TYPEPROGRAM
+#define IS_TYPEPROGRAMFLASH IS_FLASH_TYPEPROGRAM
+#define IS_TYPEERASE        IS_FLASH_TYPEERASE
+#define IS_NBSECTORS        IS_FLASH_NBSECTORS
+#define IS_OB_WDG_SOURCE    IS_OB_IWDG_SOURCE
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_I2C_Aliased_Macros HAL I2C Aliased Macros maintained for legacy purpose
+  * @{
+  */
+
+#define __HAL_I2C_RESET_CR2             I2C_RESET_CR2
+#define __HAL_I2C_GENERATE_START        I2C_GENERATE_START
+#if defined(STM32F1)
+#define __HAL_I2C_FREQ_RANGE            I2C_FREQRANGE
+#else
+#define __HAL_I2C_FREQ_RANGE            I2C_FREQ_RANGE
+#endif /* STM32F1 */
+#define __HAL_I2C_RISE_TIME             I2C_RISE_TIME
+#define __HAL_I2C_SPEED_STANDARD        I2C_SPEED_STANDARD
+#define __HAL_I2C_SPEED_FAST            I2C_SPEED_FAST
+#define __HAL_I2C_SPEED                 I2C_SPEED
+#define __HAL_I2C_7BIT_ADD_WRITE        I2C_7BIT_ADD_WRITE
+#define __HAL_I2C_7BIT_ADD_READ         I2C_7BIT_ADD_READ
+#define __HAL_I2C_10BIT_ADDRESS         I2C_10BIT_ADDRESS
+#define __HAL_I2C_10BIT_HEADER_WRITE    I2C_10BIT_HEADER_WRITE
+#define __HAL_I2C_10BIT_HEADER_READ     I2C_10BIT_HEADER_READ
+#define __HAL_I2C_MEM_ADD_MSB           I2C_MEM_ADD_MSB
+#define __HAL_I2C_MEM_ADD_LSB           I2C_MEM_ADD_LSB
+#define __HAL_I2C_FREQRANGE             I2C_FREQRANGE
+/**
+  * @}
+  */
+
+/** @defgroup HAL_I2S_Aliased_Macros HAL I2S Aliased Macros maintained for legacy purpose
+  * @{
+  */
+
+#define IS_I2S_INSTANCE                 IS_I2S_ALL_INSTANCE
+#define IS_I2S_INSTANCE_EXT             IS_I2S_ALL_INSTANCE_EXT
+
+#if defined(STM32H7)
+#define __HAL_I2S_CLEAR_FREFLAG       __HAL_I2S_CLEAR_TIFREFLAG
+#endif
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_IRDA_Aliased_Macros HAL IRDA Aliased Macros maintained for legacy purpose
+  * @{
+  */
+
+#define __IRDA_DISABLE                  __HAL_IRDA_DISABLE
+#define __IRDA_ENABLE                   __HAL_IRDA_ENABLE
+
+#define __HAL_IRDA_GETCLOCKSOURCE       IRDA_GETCLOCKSOURCE
+#define __HAL_IRDA_MASK_COMPUTATION     IRDA_MASK_COMPUTATION
+#define __IRDA_GETCLOCKSOURCE           IRDA_GETCLOCKSOURCE
+#define __IRDA_MASK_COMPUTATION         IRDA_MASK_COMPUTATION
+
+#define IS_IRDA_ONEBIT_SAMPLE           IS_IRDA_ONE_BIT_SAMPLE
+
+
+/**
+  * @}
+  */
+
+
+/** @defgroup HAL_IWDG_Aliased_Macros HAL IWDG Aliased Macros maintained for legacy purpose
+  * @{
+  */
+#define __HAL_IWDG_ENABLE_WRITE_ACCESS  IWDG_ENABLE_WRITE_ACCESS
+#define __HAL_IWDG_DISABLE_WRITE_ACCESS IWDG_DISABLE_WRITE_ACCESS
+/**
+  * @}
+  */
+
+
+/** @defgroup HAL_LPTIM_Aliased_Macros HAL LPTIM Aliased Macros maintained for legacy purpose
+  * @{
+  */
+
+#define __HAL_LPTIM_ENABLE_INTERRUPT    __HAL_LPTIM_ENABLE_IT
+#define __HAL_LPTIM_DISABLE_INTERRUPT   __HAL_LPTIM_DISABLE_IT
+#define __HAL_LPTIM_GET_ITSTATUS        __HAL_LPTIM_GET_IT_SOURCE
+
+/**
+  * @}
+  */
+
+
+/** @defgroup HAL_OPAMP_Aliased_Macros HAL OPAMP Aliased Macros maintained for legacy purpose
+  * @{
+  */
+#define __OPAMP_CSR_OPAXPD                OPAMP_CSR_OPAXPD
+#define __OPAMP_CSR_S3SELX                OPAMP_CSR_S3SELX
+#define __OPAMP_CSR_S4SELX                OPAMP_CSR_S4SELX
+#define __OPAMP_CSR_S5SELX                OPAMP_CSR_S5SELX
+#define __OPAMP_CSR_S6SELX                OPAMP_CSR_S6SELX
+#define __OPAMP_CSR_OPAXCAL_L             OPAMP_CSR_OPAXCAL_L
+#define __OPAMP_CSR_OPAXCAL_H             OPAMP_CSR_OPAXCAL_H
+#define __OPAMP_CSR_OPAXLPM               OPAMP_CSR_OPAXLPM
+#define __OPAMP_CSR_ALL_SWITCHES          OPAMP_CSR_ALL_SWITCHES
+#define __OPAMP_CSR_ANAWSELX              OPAMP_CSR_ANAWSELX
+#define __OPAMP_CSR_OPAXCALOUT            OPAMP_CSR_OPAXCALOUT
+#define __OPAMP_OFFSET_TRIM_BITSPOSITION  OPAMP_OFFSET_TRIM_BITSPOSITION
+#define __OPAMP_OFFSET_TRIM_SET           OPAMP_OFFSET_TRIM_SET
+
+/**
+  * @}
+  */
+
+
+/** @defgroup HAL_PWR_Aliased_Macros HAL PWR Aliased Macros maintained for legacy purpose
+  * @{
+  */
+#define __HAL_PVD_EVENT_DISABLE                                  __HAL_PWR_PVD_EXTI_DISABLE_EVENT
+#define __HAL_PVD_EVENT_ENABLE                                   __HAL_PWR_PVD_EXTI_ENABLE_EVENT
+#define __HAL_PVD_EXTI_FALLINGTRIGGER_DISABLE                    __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE
+#define __HAL_PVD_EXTI_FALLINGTRIGGER_ENABLE                     __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
+#define __HAL_PVD_EXTI_RISINGTRIGGER_DISABLE                     __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE
+#define __HAL_PVD_EXTI_RISINGTRIGGER_ENABLE                      __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
+#define __HAL_PVM_EVENT_DISABLE                                  __HAL_PWR_PVM_EVENT_DISABLE
+#define __HAL_PVM_EVENT_ENABLE                                   __HAL_PWR_PVM_EVENT_ENABLE
+#define __HAL_PVM_EXTI_FALLINGTRIGGER_DISABLE                    __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_DISABLE
+#define __HAL_PVM_EXTI_FALLINGTRIGGER_ENABLE                     __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_ENABLE
+#define __HAL_PVM_EXTI_RISINGTRIGGER_DISABLE                     __HAL_PWR_PVM_EXTI_RISINGTRIGGER_DISABLE
+#define __HAL_PVM_EXTI_RISINGTRIGGER_ENABLE                      __HAL_PWR_PVM_EXTI_RISINGTRIGGER_ENABLE
+#define __HAL_PWR_INTERNALWAKEUP_DISABLE                         HAL_PWREx_DisableInternalWakeUpLine
+#define __HAL_PWR_INTERNALWAKEUP_ENABLE                          HAL_PWREx_EnableInternalWakeUpLine
+#define __HAL_PWR_PULL_UP_DOWN_CONFIG_DISABLE                    HAL_PWREx_DisablePullUpPullDownConfig
+#define __HAL_PWR_PULL_UP_DOWN_CONFIG_ENABLE                     HAL_PWREx_EnablePullUpPullDownConfig
+#define __HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER()                  do { __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); } while(0)
+#define __HAL_PWR_PVD_EXTI_EVENT_DISABLE                         __HAL_PWR_PVD_EXTI_DISABLE_EVENT
+#define __HAL_PWR_PVD_EXTI_EVENT_ENABLE                          __HAL_PWR_PVD_EXTI_ENABLE_EVENT
+#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_DISABLE                __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE
+#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_ENABLE                 __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
+#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_DISABLE                 __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE
+#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_ENABLE                  __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
+#define __HAL_PWR_PVD_EXTI_SET_FALLING_EGDE_TRIGGER              __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
+#define __HAL_PWR_PVD_EXTI_SET_RISING_EDGE_TRIGGER               __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
+#define __HAL_PWR_PVM_DISABLE()                                  do { HAL_PWREx_DisablePVM1();HAL_PWREx_DisablePVM2();HAL_PWREx_DisablePVM3();HAL_PWREx_DisablePVM4(); } while(0)
+#define __HAL_PWR_PVM_ENABLE()                                   do { HAL_PWREx_EnablePVM1();HAL_PWREx_EnablePVM2();HAL_PWREx_EnablePVM3();HAL_PWREx_EnablePVM4(); } while(0)
+#define __HAL_PWR_SRAM2CONTENT_PRESERVE_DISABLE                  HAL_PWREx_DisableSRAM2ContentRetention
+#define __HAL_PWR_SRAM2CONTENT_PRESERVE_ENABLE                   HAL_PWREx_EnableSRAM2ContentRetention
+#define __HAL_PWR_VDDIO2_DISABLE                                 HAL_PWREx_DisableVddIO2
+#define __HAL_PWR_VDDIO2_ENABLE                                  HAL_PWREx_EnableVddIO2
+#define __HAL_PWR_VDDIO2_EXTI_CLEAR_EGDE_TRIGGER                 __HAL_PWR_VDDIO2_EXTI_DISABLE_FALLING_EDGE
+#define __HAL_PWR_VDDIO2_EXTI_SET_FALLING_EGDE_TRIGGER           __HAL_PWR_VDDIO2_EXTI_ENABLE_FALLING_EDGE
+#define __HAL_PWR_VDDUSB_DISABLE                                 HAL_PWREx_DisableVddUSB
+#define __HAL_PWR_VDDUSB_ENABLE                                  HAL_PWREx_EnableVddUSB
+
+#if defined (STM32F4)
+#define __HAL_PVD_EXTI_ENABLE_IT(PWR_EXTI_LINE_PVD)         __HAL_PWR_PVD_EXTI_ENABLE_IT()
+#define __HAL_PVD_EXTI_DISABLE_IT(PWR_EXTI_LINE_PVD)        __HAL_PWR_PVD_EXTI_DISABLE_IT()
+#define __HAL_PVD_EXTI_GET_FLAG(PWR_EXTI_LINE_PVD)          __HAL_PWR_PVD_EXTI_GET_FLAG()
+#define __HAL_PVD_EXTI_CLEAR_FLAG(PWR_EXTI_LINE_PVD)        __HAL_PWR_PVD_EXTI_CLEAR_FLAG()
+#define __HAL_PVD_EXTI_GENERATE_SWIT(PWR_EXTI_LINE_PVD)     __HAL_PWR_PVD_EXTI_GENERATE_SWIT()
+#else
+#define __HAL_PVD_EXTI_CLEAR_FLAG                                __HAL_PWR_PVD_EXTI_CLEAR_FLAG
+#define __HAL_PVD_EXTI_DISABLE_IT                                __HAL_PWR_PVD_EXTI_DISABLE_IT
+#define __HAL_PVD_EXTI_ENABLE_IT                                 __HAL_PWR_PVD_EXTI_ENABLE_IT
+#define __HAL_PVD_EXTI_GENERATE_SWIT                             __HAL_PWR_PVD_EXTI_GENERATE_SWIT
+#define __HAL_PVD_EXTI_GET_FLAG                                  __HAL_PWR_PVD_EXTI_GET_FLAG
+#endif /* STM32F4 */
+/**
+  * @}
+  */
+
+
+/** @defgroup HAL_RCC_Aliased HAL RCC Aliased maintained for legacy purpose
+  * @{
+  */
+
+#define RCC_StopWakeUpClock_MSI     RCC_STOP_WAKEUPCLOCK_MSI
+#define RCC_StopWakeUpClock_HSI     RCC_STOP_WAKEUPCLOCK_HSI
+
+#define HAL_RCC_CCSCallback HAL_RCC_CSSCallback
+#define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd\
+                                         )==ENABLE) ? HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT())
+
+#define __ADC_CLK_DISABLE          __HAL_RCC_ADC_CLK_DISABLE
+#define __ADC_CLK_ENABLE           __HAL_RCC_ADC_CLK_ENABLE
+#define __ADC_CLK_SLEEP_DISABLE    __HAL_RCC_ADC_CLK_SLEEP_DISABLE
+#define __ADC_CLK_SLEEP_ENABLE     __HAL_RCC_ADC_CLK_SLEEP_ENABLE
+#define __ADC_FORCE_RESET          __HAL_RCC_ADC_FORCE_RESET
+#define __ADC_RELEASE_RESET        __HAL_RCC_ADC_RELEASE_RESET
+#define __ADC1_CLK_DISABLE         __HAL_RCC_ADC1_CLK_DISABLE
+#define __ADC1_CLK_ENABLE          __HAL_RCC_ADC1_CLK_ENABLE
+#define __ADC1_FORCE_RESET         __HAL_RCC_ADC1_FORCE_RESET
+#define __ADC1_RELEASE_RESET       __HAL_RCC_ADC1_RELEASE_RESET
+#define __ADC1_CLK_SLEEP_ENABLE    __HAL_RCC_ADC1_CLK_SLEEP_ENABLE
+#define __ADC1_CLK_SLEEP_DISABLE   __HAL_RCC_ADC1_CLK_SLEEP_DISABLE
+#define __ADC2_CLK_DISABLE         __HAL_RCC_ADC2_CLK_DISABLE
+#define __ADC2_CLK_ENABLE          __HAL_RCC_ADC2_CLK_ENABLE
+#define __ADC2_FORCE_RESET __HAL_RCC_ADC2_FORCE_RESET
+#define __ADC2_RELEASE_RESET __HAL_RCC_ADC2_RELEASE_RESET
+#define __ADC3_CLK_DISABLE __HAL_RCC_ADC3_CLK_DISABLE
+#define __ADC3_CLK_ENABLE __HAL_RCC_ADC3_CLK_ENABLE
+#define __ADC3_FORCE_RESET __HAL_RCC_ADC3_FORCE_RESET
+#define __ADC3_RELEASE_RESET __HAL_RCC_ADC3_RELEASE_RESET
+#define __AES_CLK_DISABLE __HAL_RCC_AES_CLK_DISABLE
+#define __AES_CLK_ENABLE __HAL_RCC_AES_CLK_ENABLE
+#define __AES_CLK_SLEEP_DISABLE __HAL_RCC_AES_CLK_SLEEP_DISABLE
+#define __AES_CLK_SLEEP_ENABLE __HAL_RCC_AES_CLK_SLEEP_ENABLE
+#define __AES_FORCE_RESET __HAL_RCC_AES_FORCE_RESET
+#define __AES_RELEASE_RESET __HAL_RCC_AES_RELEASE_RESET
+#define __CRYP_CLK_SLEEP_ENABLE      __HAL_RCC_CRYP_CLK_SLEEP_ENABLE
+#define __CRYP_CLK_SLEEP_DISABLE  __HAL_RCC_CRYP_CLK_SLEEP_DISABLE
+#define __CRYP_CLK_ENABLE  __HAL_RCC_CRYP_CLK_ENABLE
+#define __CRYP_CLK_DISABLE  __HAL_RCC_CRYP_CLK_DISABLE
+#define __CRYP_FORCE_RESET       __HAL_RCC_CRYP_FORCE_RESET
+#define __CRYP_RELEASE_RESET  __HAL_RCC_CRYP_RELEASE_RESET
+#define __AFIO_CLK_DISABLE __HAL_RCC_AFIO_CLK_DISABLE
+#define __AFIO_CLK_ENABLE __HAL_RCC_AFIO_CLK_ENABLE
+#define __AFIO_FORCE_RESET __HAL_RCC_AFIO_FORCE_RESET
+#define __AFIO_RELEASE_RESET __HAL_RCC_AFIO_RELEASE_RESET
+#define __AHB_FORCE_RESET __HAL_RCC_AHB_FORCE_RESET
+#define __AHB_RELEASE_RESET __HAL_RCC_AHB_RELEASE_RESET
+#define __AHB1_FORCE_RESET __HAL_RCC_AHB1_FORCE_RESET
+#define __AHB1_RELEASE_RESET __HAL_RCC_AHB1_RELEASE_RESET
+#define __AHB2_FORCE_RESET __HAL_RCC_AHB2_FORCE_RESET
+#define __AHB2_RELEASE_RESET __HAL_RCC_AHB2_RELEASE_RESET
+#define __AHB3_FORCE_RESET __HAL_RCC_AHB3_FORCE_RESET
+#define __AHB3_RELEASE_RESET __HAL_RCC_AHB3_RELEASE_RESET
+#define __APB1_FORCE_RESET __HAL_RCC_APB1_FORCE_RESET
+#define __APB1_RELEASE_RESET __HAL_RCC_APB1_RELEASE_RESET
+#define __APB2_FORCE_RESET __HAL_RCC_APB2_FORCE_RESET
+#define __APB2_RELEASE_RESET __HAL_RCC_APB2_RELEASE_RESET
+#define __BKP_CLK_DISABLE __HAL_RCC_BKP_CLK_DISABLE
+#define __BKP_CLK_ENABLE __HAL_RCC_BKP_CLK_ENABLE
+#define __BKP_FORCE_RESET __HAL_RCC_BKP_FORCE_RESET
+#define __BKP_RELEASE_RESET __HAL_RCC_BKP_RELEASE_RESET
+#define __CAN1_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE
+#define __CAN1_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE
+#define __CAN1_CLK_SLEEP_DISABLE __HAL_RCC_CAN1_CLK_SLEEP_DISABLE
+#define __CAN1_CLK_SLEEP_ENABLE __HAL_RCC_CAN1_CLK_SLEEP_ENABLE
+#define __CAN1_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET
+#define __CAN1_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET
+#define __CAN_CLK_DISABLE         __HAL_RCC_CAN1_CLK_DISABLE
+#define __CAN_CLK_ENABLE          __HAL_RCC_CAN1_CLK_ENABLE
+#define __CAN_FORCE_RESET         __HAL_RCC_CAN1_FORCE_RESET
+#define __CAN_RELEASE_RESET       __HAL_RCC_CAN1_RELEASE_RESET
+#define __CAN2_CLK_DISABLE __HAL_RCC_CAN2_CLK_DISABLE
+#define __CAN2_CLK_ENABLE __HAL_RCC_CAN2_CLK_ENABLE
+#define __CAN2_FORCE_RESET __HAL_RCC_CAN2_FORCE_RESET
+#define __CAN2_RELEASE_RESET __HAL_RCC_CAN2_RELEASE_RESET
+#define __CEC_CLK_DISABLE __HAL_RCC_CEC_CLK_DISABLE
+#define __CEC_CLK_ENABLE __HAL_RCC_CEC_CLK_ENABLE
+#define __COMP_CLK_DISABLE        __HAL_RCC_COMP_CLK_DISABLE
+#define __COMP_CLK_ENABLE         __HAL_RCC_COMP_CLK_ENABLE
+#define __COMP_FORCE_RESET        __HAL_RCC_COMP_FORCE_RESET
+#define __COMP_RELEASE_RESET      __HAL_RCC_COMP_RELEASE_RESET
+#define __COMP_CLK_SLEEP_ENABLE   __HAL_RCC_COMP_CLK_SLEEP_ENABLE
+#define __COMP_CLK_SLEEP_DISABLE  __HAL_RCC_COMP_CLK_SLEEP_DISABLE
+#define __CEC_FORCE_RESET __HAL_RCC_CEC_FORCE_RESET
+#define __CEC_RELEASE_RESET __HAL_RCC_CEC_RELEASE_RESET
+#define __CRC_CLK_DISABLE __HAL_RCC_CRC_CLK_DISABLE
+#define __CRC_CLK_ENABLE __HAL_RCC_CRC_CLK_ENABLE
+#define __CRC_CLK_SLEEP_DISABLE __HAL_RCC_CRC_CLK_SLEEP_DISABLE
+#define __CRC_CLK_SLEEP_ENABLE __HAL_RCC_CRC_CLK_SLEEP_ENABLE
+#define __CRC_FORCE_RESET __HAL_RCC_CRC_FORCE_RESET
+#define __CRC_RELEASE_RESET __HAL_RCC_CRC_RELEASE_RESET
+#define __DAC_CLK_DISABLE __HAL_RCC_DAC_CLK_DISABLE
+#define __DAC_CLK_ENABLE __HAL_RCC_DAC_CLK_ENABLE
+#define __DAC_FORCE_RESET __HAL_RCC_DAC_FORCE_RESET
+#define __DAC_RELEASE_RESET __HAL_RCC_DAC_RELEASE_RESET
+#define __DAC1_CLK_DISABLE __HAL_RCC_DAC1_CLK_DISABLE
+#define __DAC1_CLK_ENABLE __HAL_RCC_DAC1_CLK_ENABLE
+#define __DAC1_CLK_SLEEP_DISABLE __HAL_RCC_DAC1_CLK_SLEEP_DISABLE
+#define __DAC1_CLK_SLEEP_ENABLE __HAL_RCC_DAC1_CLK_SLEEP_ENABLE
+#define __DAC1_FORCE_RESET __HAL_RCC_DAC1_FORCE_RESET
+#define __DAC1_RELEASE_RESET __HAL_RCC_DAC1_RELEASE_RESET
+#define __DBGMCU_CLK_ENABLE     __HAL_RCC_DBGMCU_CLK_ENABLE
+#define __DBGMCU_CLK_DISABLE     __HAL_RCC_DBGMCU_CLK_DISABLE
+#define __DBGMCU_FORCE_RESET    __HAL_RCC_DBGMCU_FORCE_RESET
+#define __DBGMCU_RELEASE_RESET  __HAL_RCC_DBGMCU_RELEASE_RESET
+#define __DFSDM_CLK_DISABLE __HAL_RCC_DFSDM_CLK_DISABLE
+#define __DFSDM_CLK_ENABLE __HAL_RCC_DFSDM_CLK_ENABLE
+#define __DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE
+#define __DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE
+#define __DFSDM_FORCE_RESET __HAL_RCC_DFSDM_FORCE_RESET
+#define __DFSDM_RELEASE_RESET __HAL_RCC_DFSDM_RELEASE_RESET
+#define __DMA1_CLK_DISABLE __HAL_RCC_DMA1_CLK_DISABLE
+#define __DMA1_CLK_ENABLE __HAL_RCC_DMA1_CLK_ENABLE
+#define __DMA1_CLK_SLEEP_DISABLE __HAL_RCC_DMA1_CLK_SLEEP_DISABLE
+#define __DMA1_CLK_SLEEP_ENABLE __HAL_RCC_DMA1_CLK_SLEEP_ENABLE
+#define __DMA1_FORCE_RESET __HAL_RCC_DMA1_FORCE_RESET
+#define __DMA1_RELEASE_RESET __HAL_RCC_DMA1_RELEASE_RESET
+#define __DMA2_CLK_DISABLE __HAL_RCC_DMA2_CLK_DISABLE
+#define __DMA2_CLK_ENABLE __HAL_RCC_DMA2_CLK_ENABLE
+#define __DMA2_CLK_SLEEP_DISABLE __HAL_RCC_DMA2_CLK_SLEEP_DISABLE
+#define __DMA2_CLK_SLEEP_ENABLE __HAL_RCC_DMA2_CLK_SLEEP_ENABLE
+#define __DMA2_FORCE_RESET __HAL_RCC_DMA2_FORCE_RESET
+#define __DMA2_RELEASE_RESET __HAL_RCC_DMA2_RELEASE_RESET
+#define __ETHMAC_CLK_DISABLE __HAL_RCC_ETHMAC_CLK_DISABLE
+#define __ETHMAC_CLK_ENABLE __HAL_RCC_ETHMAC_CLK_ENABLE
+#define __ETHMAC_FORCE_RESET __HAL_RCC_ETHMAC_FORCE_RESET
+#define __ETHMAC_RELEASE_RESET __HAL_RCC_ETHMAC_RELEASE_RESET
+#define __ETHMACRX_CLK_DISABLE __HAL_RCC_ETHMACRX_CLK_DISABLE
+#define __ETHMACRX_CLK_ENABLE __HAL_RCC_ETHMACRX_CLK_ENABLE
+#define __ETHMACTX_CLK_DISABLE __HAL_RCC_ETHMACTX_CLK_DISABLE
+#define __ETHMACTX_CLK_ENABLE __HAL_RCC_ETHMACTX_CLK_ENABLE
+#define __FIREWALL_CLK_DISABLE __HAL_RCC_FIREWALL_CLK_DISABLE
+#define __FIREWALL_CLK_ENABLE __HAL_RCC_FIREWALL_CLK_ENABLE
+#define __FLASH_CLK_DISABLE __HAL_RCC_FLASH_CLK_DISABLE
+#define __FLASH_CLK_ENABLE __HAL_RCC_FLASH_CLK_ENABLE
+#define __FLASH_CLK_SLEEP_DISABLE __HAL_RCC_FLASH_CLK_SLEEP_DISABLE
+#define __FLASH_CLK_SLEEP_ENABLE __HAL_RCC_FLASH_CLK_SLEEP_ENABLE
+#define __FLASH_FORCE_RESET __HAL_RCC_FLASH_FORCE_RESET
+#define __FLASH_RELEASE_RESET __HAL_RCC_FLASH_RELEASE_RESET
+#define __FLITF_CLK_DISABLE       __HAL_RCC_FLITF_CLK_DISABLE
+#define __FLITF_CLK_ENABLE        __HAL_RCC_FLITF_CLK_ENABLE
+#define __FLITF_FORCE_RESET       __HAL_RCC_FLITF_FORCE_RESET
+#define __FLITF_RELEASE_RESET     __HAL_RCC_FLITF_RELEASE_RESET
+#define __FLITF_CLK_SLEEP_ENABLE  __HAL_RCC_FLITF_CLK_SLEEP_ENABLE
+#define __FLITF_CLK_SLEEP_DISABLE __HAL_RCC_FLITF_CLK_SLEEP_DISABLE
+#define __FMC_CLK_DISABLE __HAL_RCC_FMC_CLK_DISABLE
+#define __FMC_CLK_ENABLE __HAL_RCC_FMC_CLK_ENABLE
+#define __FMC_CLK_SLEEP_DISABLE __HAL_RCC_FMC_CLK_SLEEP_DISABLE
+#define __FMC_CLK_SLEEP_ENABLE __HAL_RCC_FMC_CLK_SLEEP_ENABLE
+#define __FMC_FORCE_RESET __HAL_RCC_FMC_FORCE_RESET
+#define __FMC_RELEASE_RESET __HAL_RCC_FMC_RELEASE_RESET
+#define __FSMC_CLK_DISABLE __HAL_RCC_FSMC_CLK_DISABLE
+#define __FSMC_CLK_ENABLE __HAL_RCC_FSMC_CLK_ENABLE
+#define __GPIOA_CLK_DISABLE __HAL_RCC_GPIOA_CLK_DISABLE
+#define __GPIOA_CLK_ENABLE __HAL_RCC_GPIOA_CLK_ENABLE
+#define __GPIOA_CLK_SLEEP_DISABLE __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE
+#define __GPIOA_CLK_SLEEP_ENABLE __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE
+#define __GPIOA_FORCE_RESET __HAL_RCC_GPIOA_FORCE_RESET
+#define __GPIOA_RELEASE_RESET __HAL_RCC_GPIOA_RELEASE_RESET
+#define __GPIOB_CLK_DISABLE __HAL_RCC_GPIOB_CLK_DISABLE
+#define __GPIOB_CLK_ENABLE __HAL_RCC_GPIOB_CLK_ENABLE
+#define __GPIOB_CLK_SLEEP_DISABLE __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE
+#define __GPIOB_CLK_SLEEP_ENABLE __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE
+#define __GPIOB_FORCE_RESET __HAL_RCC_GPIOB_FORCE_RESET
+#define __GPIOB_RELEASE_RESET __HAL_RCC_GPIOB_RELEASE_RESET
+#define __GPIOC_CLK_DISABLE __HAL_RCC_GPIOC_CLK_DISABLE
+#define __GPIOC_CLK_ENABLE __HAL_RCC_GPIOC_CLK_ENABLE
+#define __GPIOC_CLK_SLEEP_DISABLE __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE
+#define __GPIOC_CLK_SLEEP_ENABLE __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE
+#define __GPIOC_FORCE_RESET __HAL_RCC_GPIOC_FORCE_RESET
+#define __GPIOC_RELEASE_RESET __HAL_RCC_GPIOC_RELEASE_RESET
+#define __GPIOD_CLK_DISABLE __HAL_RCC_GPIOD_CLK_DISABLE
+#define __GPIOD_CLK_ENABLE __HAL_RCC_GPIOD_CLK_ENABLE
+#define __GPIOD_CLK_SLEEP_DISABLE __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE
+#define __GPIOD_CLK_SLEEP_ENABLE __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE
+#define __GPIOD_FORCE_RESET __HAL_RCC_GPIOD_FORCE_RESET
+#define __GPIOD_RELEASE_RESET __HAL_RCC_GPIOD_RELEASE_RESET
+#define __GPIOE_CLK_DISABLE __HAL_RCC_GPIOE_CLK_DISABLE
+#define __GPIOE_CLK_ENABLE __HAL_RCC_GPIOE_CLK_ENABLE
+#define __GPIOE_CLK_SLEEP_DISABLE __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE
+#define __GPIOE_CLK_SLEEP_ENABLE __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE
+#define __GPIOE_FORCE_RESET __HAL_RCC_GPIOE_FORCE_RESET
+#define __GPIOE_RELEASE_RESET __HAL_RCC_GPIOE_RELEASE_RESET
+#define __GPIOF_CLK_DISABLE __HAL_RCC_GPIOF_CLK_DISABLE
+#define __GPIOF_CLK_ENABLE __HAL_RCC_GPIOF_CLK_ENABLE
+#define __GPIOF_CLK_SLEEP_DISABLE __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE
+#define __GPIOF_CLK_SLEEP_ENABLE __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE
+#define __GPIOF_FORCE_RESET __HAL_RCC_GPIOF_FORCE_RESET
+#define __GPIOF_RELEASE_RESET __HAL_RCC_GPIOF_RELEASE_RESET
+#define __GPIOG_CLK_DISABLE __HAL_RCC_GPIOG_CLK_DISABLE
+#define __GPIOG_CLK_ENABLE __HAL_RCC_GPIOG_CLK_ENABLE
+#define __GPIOG_CLK_SLEEP_DISABLE __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE
+#define __GPIOG_CLK_SLEEP_ENABLE __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE
+#define __GPIOG_FORCE_RESET __HAL_RCC_GPIOG_FORCE_RESET
+#define __GPIOG_RELEASE_RESET __HAL_RCC_GPIOG_RELEASE_RESET
+#define __GPIOH_CLK_DISABLE __HAL_RCC_GPIOH_CLK_DISABLE
+#define __GPIOH_CLK_ENABLE __HAL_RCC_GPIOH_CLK_ENABLE
+#define __GPIOH_CLK_SLEEP_DISABLE __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE
+#define __GPIOH_CLK_SLEEP_ENABLE __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE
+#define __GPIOH_FORCE_RESET __HAL_RCC_GPIOH_FORCE_RESET
+#define __GPIOH_RELEASE_RESET __HAL_RCC_GPIOH_RELEASE_RESET
+#define __I2C1_CLK_DISABLE __HAL_RCC_I2C1_CLK_DISABLE
+#define __I2C1_CLK_ENABLE __HAL_RCC_I2C1_CLK_ENABLE
+#define __I2C1_CLK_SLEEP_DISABLE __HAL_RCC_I2C1_CLK_SLEEP_DISABLE
+#define __I2C1_CLK_SLEEP_ENABLE __HAL_RCC_I2C1_CLK_SLEEP_ENABLE
+#define __I2C1_FORCE_RESET __HAL_RCC_I2C1_FORCE_RESET
+#define __I2C1_RELEASE_RESET __HAL_RCC_I2C1_RELEASE_RESET
+#define __I2C2_CLK_DISABLE __HAL_RCC_I2C2_CLK_DISABLE
+#define __I2C2_CLK_ENABLE __HAL_RCC_I2C2_CLK_ENABLE
+#define __I2C2_CLK_SLEEP_DISABLE __HAL_RCC_I2C2_CLK_SLEEP_DISABLE
+#define __I2C2_CLK_SLEEP_ENABLE __HAL_RCC_I2C2_CLK_SLEEP_ENABLE
+#define __I2C2_FORCE_RESET __HAL_RCC_I2C2_FORCE_RESET
+#define __I2C2_RELEASE_RESET __HAL_RCC_I2C2_RELEASE_RESET
+#define __I2C3_CLK_DISABLE __HAL_RCC_I2C3_CLK_DISABLE
+#define __I2C3_CLK_ENABLE __HAL_RCC_I2C3_CLK_ENABLE
+#define __I2C3_CLK_SLEEP_DISABLE __HAL_RCC_I2C3_CLK_SLEEP_DISABLE
+#define __I2C3_CLK_SLEEP_ENABLE __HAL_RCC_I2C3_CLK_SLEEP_ENABLE
+#define __I2C3_FORCE_RESET __HAL_RCC_I2C3_FORCE_RESET
+#define __I2C3_RELEASE_RESET __HAL_RCC_I2C3_RELEASE_RESET
+#define __LCD_CLK_DISABLE __HAL_RCC_LCD_CLK_DISABLE
+#define __LCD_CLK_ENABLE __HAL_RCC_LCD_CLK_ENABLE
+#define __LCD_CLK_SLEEP_DISABLE __HAL_RCC_LCD_CLK_SLEEP_DISABLE
+#define __LCD_CLK_SLEEP_ENABLE __HAL_RCC_LCD_CLK_SLEEP_ENABLE
+#define __LCD_FORCE_RESET __HAL_RCC_LCD_FORCE_RESET
+#define __LCD_RELEASE_RESET __HAL_RCC_LCD_RELEASE_RESET
+#define __LPTIM1_CLK_DISABLE __HAL_RCC_LPTIM1_CLK_DISABLE
+#define __LPTIM1_CLK_ENABLE __HAL_RCC_LPTIM1_CLK_ENABLE
+#define __LPTIM1_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE
+#define __LPTIM1_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE
+#define __LPTIM1_FORCE_RESET __HAL_RCC_LPTIM1_FORCE_RESET
+#define __LPTIM1_RELEASE_RESET __HAL_RCC_LPTIM1_RELEASE_RESET
+#define __LPTIM2_CLK_DISABLE __HAL_RCC_LPTIM2_CLK_DISABLE
+#define __LPTIM2_CLK_ENABLE __HAL_RCC_LPTIM2_CLK_ENABLE
+#define __LPTIM2_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE
+#define __LPTIM2_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE
+#define __LPTIM2_FORCE_RESET __HAL_RCC_LPTIM2_FORCE_RESET
+#define __LPTIM2_RELEASE_RESET __HAL_RCC_LPTIM2_RELEASE_RESET
+#define __LPUART1_CLK_DISABLE __HAL_RCC_LPUART1_CLK_DISABLE
+#define __LPUART1_CLK_ENABLE __HAL_RCC_LPUART1_CLK_ENABLE
+#define __LPUART1_CLK_SLEEP_DISABLE __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE
+#define __LPUART1_CLK_SLEEP_ENABLE __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE
+#define __LPUART1_FORCE_RESET __HAL_RCC_LPUART1_FORCE_RESET
+#define __LPUART1_RELEASE_RESET __HAL_RCC_LPUART1_RELEASE_RESET
+#define __OPAMP_CLK_DISABLE __HAL_RCC_OPAMP_CLK_DISABLE
+#define __OPAMP_CLK_ENABLE __HAL_RCC_OPAMP_CLK_ENABLE
+#define __OPAMP_CLK_SLEEP_DISABLE __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE
+#define __OPAMP_CLK_SLEEP_ENABLE __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE
+#define __OPAMP_FORCE_RESET __HAL_RCC_OPAMP_FORCE_RESET
+#define __OPAMP_RELEASE_RESET __HAL_RCC_OPAMP_RELEASE_RESET
+#define __OTGFS_CLK_DISABLE __HAL_RCC_OTGFS_CLK_DISABLE
+#define __OTGFS_CLK_ENABLE __HAL_RCC_OTGFS_CLK_ENABLE
+#define __OTGFS_CLK_SLEEP_DISABLE __HAL_RCC_OTGFS_CLK_SLEEP_DISABLE
+#define __OTGFS_CLK_SLEEP_ENABLE __HAL_RCC_OTGFS_CLK_SLEEP_ENABLE
+#define __OTGFS_FORCE_RESET __HAL_RCC_OTGFS_FORCE_RESET
+#define __OTGFS_RELEASE_RESET __HAL_RCC_OTGFS_RELEASE_RESET
+#define __PWR_CLK_DISABLE __HAL_RCC_PWR_CLK_DISABLE
+#define __PWR_CLK_ENABLE __HAL_RCC_PWR_CLK_ENABLE
+#define __PWR_CLK_SLEEP_DISABLE __HAL_RCC_PWR_CLK_SLEEP_DISABLE
+#define __PWR_CLK_SLEEP_ENABLE __HAL_RCC_PWR_CLK_SLEEP_ENABLE
+#define __PWR_FORCE_RESET __HAL_RCC_PWR_FORCE_RESET
+#define __PWR_RELEASE_RESET __HAL_RCC_PWR_RELEASE_RESET
+#define __QSPI_CLK_DISABLE __HAL_RCC_QSPI_CLK_DISABLE
+#define __QSPI_CLK_ENABLE __HAL_RCC_QSPI_CLK_ENABLE
+#define __QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QSPI_CLK_SLEEP_DISABLE
+#define __QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QSPI_CLK_SLEEP_ENABLE
+#define __QSPI_FORCE_RESET __HAL_RCC_QSPI_FORCE_RESET
+#define __QSPI_RELEASE_RESET __HAL_RCC_QSPI_RELEASE_RESET
+
+#if defined(STM32WB)
+#define __HAL_RCC_QSPI_CLK_DISABLE            __HAL_RCC_QUADSPI_CLK_DISABLE
+#define __HAL_RCC_QSPI_CLK_ENABLE             __HAL_RCC_QUADSPI_CLK_ENABLE
+#define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE      __HAL_RCC_QUADSPI_CLK_SLEEP_DISABLE
+#define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE       __HAL_RCC_QUADSPI_CLK_SLEEP_ENABLE
+#define __HAL_RCC_QSPI_FORCE_RESET            __HAL_RCC_QUADSPI_FORCE_RESET
+#define __HAL_RCC_QSPI_RELEASE_RESET          __HAL_RCC_QUADSPI_RELEASE_RESET
+#define __HAL_RCC_QSPI_IS_CLK_ENABLED         __HAL_RCC_QUADSPI_IS_CLK_ENABLED
+#define __HAL_RCC_QSPI_IS_CLK_DISABLED        __HAL_RCC_QUADSPI_IS_CLK_DISABLED
+#define __HAL_RCC_QSPI_IS_CLK_SLEEP_ENABLED   __HAL_RCC_QUADSPI_IS_CLK_SLEEP_ENABLED
+#define __HAL_RCC_QSPI_IS_CLK_SLEEP_DISABLED  __HAL_RCC_QUADSPI_IS_CLK_SLEEP_DISABLED
+#define QSPI_IRQHandler QUADSPI_IRQHandler
+#endif /* __HAL_RCC_QUADSPI_CLK_ENABLE */
+
+#define __RNG_CLK_DISABLE __HAL_RCC_RNG_CLK_DISABLE
+#define __RNG_CLK_ENABLE __HAL_RCC_RNG_CLK_ENABLE
+#define __RNG_CLK_SLEEP_DISABLE __HAL_RCC_RNG_CLK_SLEEP_DISABLE
+#define __RNG_CLK_SLEEP_ENABLE __HAL_RCC_RNG_CLK_SLEEP_ENABLE
+#define __RNG_FORCE_RESET __HAL_RCC_RNG_FORCE_RESET
+#define __RNG_RELEASE_RESET __HAL_RCC_RNG_RELEASE_RESET
+#define __SAI1_CLK_DISABLE __HAL_RCC_SAI1_CLK_DISABLE
+#define __SAI1_CLK_ENABLE __HAL_RCC_SAI1_CLK_ENABLE
+#define __SAI1_CLK_SLEEP_DISABLE __HAL_RCC_SAI1_CLK_SLEEP_DISABLE
+#define __SAI1_CLK_SLEEP_ENABLE __HAL_RCC_SAI1_CLK_SLEEP_ENABLE
+#define __SAI1_FORCE_RESET __HAL_RCC_SAI1_FORCE_RESET
+#define __SAI1_RELEASE_RESET __HAL_RCC_SAI1_RELEASE_RESET
+#define __SAI2_CLK_DISABLE __HAL_RCC_SAI2_CLK_DISABLE
+#define __SAI2_CLK_ENABLE __HAL_RCC_SAI2_CLK_ENABLE
+#define __SAI2_CLK_SLEEP_DISABLE __HAL_RCC_SAI2_CLK_SLEEP_DISABLE
+#define __SAI2_CLK_SLEEP_ENABLE __HAL_RCC_SAI2_CLK_SLEEP_ENABLE
+#define __SAI2_FORCE_RESET __HAL_RCC_SAI2_FORCE_RESET
+#define __SAI2_RELEASE_RESET __HAL_RCC_SAI2_RELEASE_RESET
+#define __SDIO_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE
+#define __SDIO_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE
+#define __SDMMC_CLK_DISABLE __HAL_RCC_SDMMC_CLK_DISABLE
+#define __SDMMC_CLK_ENABLE __HAL_RCC_SDMMC_CLK_ENABLE
+#define __SDMMC_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC_CLK_SLEEP_DISABLE
+#define __SDMMC_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC_CLK_SLEEP_ENABLE
+#define __SDMMC_FORCE_RESET __HAL_RCC_SDMMC_FORCE_RESET
+#define __SDMMC_RELEASE_RESET __HAL_RCC_SDMMC_RELEASE_RESET
+#define __SPI1_CLK_DISABLE __HAL_RCC_SPI1_CLK_DISABLE
+#define __SPI1_CLK_ENABLE __HAL_RCC_SPI1_CLK_ENABLE
+#define __SPI1_CLK_SLEEP_DISABLE __HAL_RCC_SPI1_CLK_SLEEP_DISABLE
+#define __SPI1_CLK_SLEEP_ENABLE __HAL_RCC_SPI1_CLK_SLEEP_ENABLE
+#define __SPI1_FORCE_RESET __HAL_RCC_SPI1_FORCE_RESET
+#define __SPI1_RELEASE_RESET __HAL_RCC_SPI1_RELEASE_RESET
+#define __SPI2_CLK_DISABLE __HAL_RCC_SPI2_CLK_DISABLE
+#define __SPI2_CLK_ENABLE __HAL_RCC_SPI2_CLK_ENABLE
+#define __SPI2_CLK_SLEEP_DISABLE __HAL_RCC_SPI2_CLK_SLEEP_DISABLE
+#define __SPI2_CLK_SLEEP_ENABLE __HAL_RCC_SPI2_CLK_SLEEP_ENABLE
+#define __SPI2_FORCE_RESET __HAL_RCC_SPI2_FORCE_RESET
+#define __SPI2_RELEASE_RESET __HAL_RCC_SPI2_RELEASE_RESET
+#define __SPI3_CLK_DISABLE __HAL_RCC_SPI3_CLK_DISABLE
+#define __SPI3_CLK_ENABLE __HAL_RCC_SPI3_CLK_ENABLE
+#define __SPI3_CLK_SLEEP_DISABLE __HAL_RCC_SPI3_CLK_SLEEP_DISABLE
+#define __SPI3_CLK_SLEEP_ENABLE __HAL_RCC_SPI3_CLK_SLEEP_ENABLE
+#define __SPI3_FORCE_RESET __HAL_RCC_SPI3_FORCE_RESET
+#define __SPI3_RELEASE_RESET __HAL_RCC_SPI3_RELEASE_RESET
+#define __SRAM_CLK_DISABLE __HAL_RCC_SRAM_CLK_DISABLE
+#define __SRAM_CLK_ENABLE __HAL_RCC_SRAM_CLK_ENABLE
+#define __SRAM1_CLK_SLEEP_DISABLE __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE
+#define __SRAM1_CLK_SLEEP_ENABLE __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE
+#define __SRAM2_CLK_SLEEP_DISABLE __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE
+#define __SRAM2_CLK_SLEEP_ENABLE __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE
+#define __SWPMI1_CLK_DISABLE __HAL_RCC_SWPMI1_CLK_DISABLE
+#define __SWPMI1_CLK_ENABLE __HAL_RCC_SWPMI1_CLK_ENABLE
+#define __SWPMI1_CLK_SLEEP_DISABLE __HAL_RCC_SWPMI1_CLK_SLEEP_DISABLE
+#define __SWPMI1_CLK_SLEEP_ENABLE __HAL_RCC_SWPMI1_CLK_SLEEP_ENABLE
+#define __SWPMI1_FORCE_RESET __HAL_RCC_SWPMI1_FORCE_RESET
+#define __SWPMI1_RELEASE_RESET __HAL_RCC_SWPMI1_RELEASE_RESET
+#define __SYSCFG_CLK_DISABLE __HAL_RCC_SYSCFG_CLK_DISABLE
+#define __SYSCFG_CLK_ENABLE __HAL_RCC_SYSCFG_CLK_ENABLE
+#define __SYSCFG_CLK_SLEEP_DISABLE __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE
+#define __SYSCFG_CLK_SLEEP_ENABLE __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE
+#define __SYSCFG_FORCE_RESET __HAL_RCC_SYSCFG_FORCE_RESET
+#define __SYSCFG_RELEASE_RESET __HAL_RCC_SYSCFG_RELEASE_RESET
+#define __TIM1_CLK_DISABLE __HAL_RCC_TIM1_CLK_DISABLE
+#define __TIM1_CLK_ENABLE __HAL_RCC_TIM1_CLK_ENABLE
+#define __TIM1_CLK_SLEEP_DISABLE __HAL_RCC_TIM1_CLK_SLEEP_DISABLE
+#define __TIM1_CLK_SLEEP_ENABLE __HAL_RCC_TIM1_CLK_SLEEP_ENABLE
+#define __TIM1_FORCE_RESET __HAL_RCC_TIM1_FORCE_RESET
+#define __TIM1_RELEASE_RESET __HAL_RCC_TIM1_RELEASE_RESET
+#define __TIM10_CLK_DISABLE __HAL_RCC_TIM10_CLK_DISABLE
+#define __TIM10_CLK_ENABLE __HAL_RCC_TIM10_CLK_ENABLE
+#define __TIM10_FORCE_RESET __HAL_RCC_TIM10_FORCE_RESET
+#define __TIM10_RELEASE_RESET __HAL_RCC_TIM10_RELEASE_RESET
+#define __TIM11_CLK_DISABLE __HAL_RCC_TIM11_CLK_DISABLE
+#define __TIM11_CLK_ENABLE __HAL_RCC_TIM11_CLK_ENABLE
+#define __TIM11_FORCE_RESET __HAL_RCC_TIM11_FORCE_RESET
+#define __TIM11_RELEASE_RESET __HAL_RCC_TIM11_RELEASE_RESET
+#define __TIM12_CLK_DISABLE __HAL_RCC_TIM12_CLK_DISABLE
+#define __TIM12_CLK_ENABLE __HAL_RCC_TIM12_CLK_ENABLE
+#define __TIM12_FORCE_RESET __HAL_RCC_TIM12_FORCE_RESET
+#define __TIM12_RELEASE_RESET __HAL_RCC_TIM12_RELEASE_RESET
+#define __TIM13_CLK_DISABLE __HAL_RCC_TIM13_CLK_DISABLE
+#define __TIM13_CLK_ENABLE __HAL_RCC_TIM13_CLK_ENABLE
+#define __TIM13_FORCE_RESET __HAL_RCC_TIM13_FORCE_RESET
+#define __TIM13_RELEASE_RESET __HAL_RCC_TIM13_RELEASE_RESET
+#define __TIM14_CLK_DISABLE __HAL_RCC_TIM14_CLK_DISABLE
+#define __TIM14_CLK_ENABLE __HAL_RCC_TIM14_CLK_ENABLE
+#define __TIM14_FORCE_RESET __HAL_RCC_TIM14_FORCE_RESET
+#define __TIM14_RELEASE_RESET __HAL_RCC_TIM14_RELEASE_RESET
+#define __TIM15_CLK_DISABLE __HAL_RCC_TIM15_CLK_DISABLE
+#define __TIM15_CLK_ENABLE __HAL_RCC_TIM15_CLK_ENABLE
+#define __TIM15_CLK_SLEEP_DISABLE __HAL_RCC_TIM15_CLK_SLEEP_DISABLE
+#define __TIM15_CLK_SLEEP_ENABLE __HAL_RCC_TIM15_CLK_SLEEP_ENABLE
+#define __TIM15_FORCE_RESET __HAL_RCC_TIM15_FORCE_RESET
+#define __TIM15_RELEASE_RESET __HAL_RCC_TIM15_RELEASE_RESET
+#define __TIM16_CLK_DISABLE __HAL_RCC_TIM16_CLK_DISABLE
+#define __TIM16_CLK_ENABLE __HAL_RCC_TIM16_CLK_ENABLE
+#define __TIM16_CLK_SLEEP_DISABLE __HAL_RCC_TIM16_CLK_SLEEP_DISABLE
+#define __TIM16_CLK_SLEEP_ENABLE __HAL_RCC_TIM16_CLK_SLEEP_ENABLE
+#define __TIM16_FORCE_RESET __HAL_RCC_TIM16_FORCE_RESET
+#define __TIM16_RELEASE_RESET __HAL_RCC_TIM16_RELEASE_RESET
+#define __TIM17_CLK_DISABLE __HAL_RCC_TIM17_CLK_DISABLE
+#define __TIM17_CLK_ENABLE __HAL_RCC_TIM17_CLK_ENABLE
+#define __TIM17_CLK_SLEEP_DISABLE __HAL_RCC_TIM17_CLK_SLEEP_DISABLE
+#define __TIM17_CLK_SLEEP_ENABLE __HAL_RCC_TIM17_CLK_SLEEP_ENABLE
+#define __TIM17_FORCE_RESET __HAL_RCC_TIM17_FORCE_RESET
+#define __TIM17_RELEASE_RESET __HAL_RCC_TIM17_RELEASE_RESET
+#define __TIM2_CLK_DISABLE __HAL_RCC_TIM2_CLK_DISABLE
+#define __TIM2_CLK_ENABLE __HAL_RCC_TIM2_CLK_ENABLE
+#define __TIM2_CLK_SLEEP_DISABLE __HAL_RCC_TIM2_CLK_SLEEP_DISABLE
+#define __TIM2_CLK_SLEEP_ENABLE __HAL_RCC_TIM2_CLK_SLEEP_ENABLE
+#define __TIM2_FORCE_RESET __HAL_RCC_TIM2_FORCE_RESET
+#define __TIM2_RELEASE_RESET __HAL_RCC_TIM2_RELEASE_RESET
+#define __TIM3_CLK_DISABLE __HAL_RCC_TIM3_CLK_DISABLE
+#define __TIM3_CLK_ENABLE __HAL_RCC_TIM3_CLK_ENABLE
+#define __TIM3_CLK_SLEEP_DISABLE __HAL_RCC_TIM3_CLK_SLEEP_DISABLE
+#define __TIM3_CLK_SLEEP_ENABLE __HAL_RCC_TIM3_CLK_SLEEP_ENABLE
+#define __TIM3_FORCE_RESET __HAL_RCC_TIM3_FORCE_RESET
+#define __TIM3_RELEASE_RESET __HAL_RCC_TIM3_RELEASE_RESET
+#define __TIM4_CLK_DISABLE __HAL_RCC_TIM4_CLK_DISABLE
+#define __TIM4_CLK_ENABLE __HAL_RCC_TIM4_CLK_ENABLE
+#define __TIM4_CLK_SLEEP_DISABLE __HAL_RCC_TIM4_CLK_SLEEP_DISABLE
+#define __TIM4_CLK_SLEEP_ENABLE __HAL_RCC_TIM4_CLK_SLEEP_ENABLE
+#define __TIM4_FORCE_RESET __HAL_RCC_TIM4_FORCE_RESET
+#define __TIM4_RELEASE_RESET __HAL_RCC_TIM4_RELEASE_RESET
+#define __TIM5_CLK_DISABLE __HAL_RCC_TIM5_CLK_DISABLE
+#define __TIM5_CLK_ENABLE __HAL_RCC_TIM5_CLK_ENABLE
+#define __TIM5_CLK_SLEEP_DISABLE __HAL_RCC_TIM5_CLK_SLEEP_DISABLE
+#define __TIM5_CLK_SLEEP_ENABLE __HAL_RCC_TIM5_CLK_SLEEP_ENABLE
+#define __TIM5_FORCE_RESET __HAL_RCC_TIM5_FORCE_RESET
+#define __TIM5_RELEASE_RESET __HAL_RCC_TIM5_RELEASE_RESET
+#define __TIM6_CLK_DISABLE __HAL_RCC_TIM6_CLK_DISABLE
+#define __TIM6_CLK_ENABLE __HAL_RCC_TIM6_CLK_ENABLE
+#define __TIM6_CLK_SLEEP_DISABLE __HAL_RCC_TIM6_CLK_SLEEP_DISABLE
+#define __TIM6_CLK_SLEEP_ENABLE __HAL_RCC_TIM6_CLK_SLEEP_ENABLE
+#define __TIM6_FORCE_RESET __HAL_RCC_TIM6_FORCE_RESET
+#define __TIM6_RELEASE_RESET __HAL_RCC_TIM6_RELEASE_RESET
+#define __TIM7_CLK_DISABLE __HAL_RCC_TIM7_CLK_DISABLE
+#define __TIM7_CLK_ENABLE __HAL_RCC_TIM7_CLK_ENABLE
+#define __TIM7_CLK_SLEEP_DISABLE __HAL_RCC_TIM7_CLK_SLEEP_DISABLE
+#define __TIM7_CLK_SLEEP_ENABLE __HAL_RCC_TIM7_CLK_SLEEP_ENABLE
+#define __TIM7_FORCE_RESET __HAL_RCC_TIM7_FORCE_RESET
+#define __TIM7_RELEASE_RESET __HAL_RCC_TIM7_RELEASE_RESET
+#define __TIM8_CLK_DISABLE __HAL_RCC_TIM8_CLK_DISABLE
+#define __TIM8_CLK_ENABLE __HAL_RCC_TIM8_CLK_ENABLE
+#define __TIM8_CLK_SLEEP_DISABLE __HAL_RCC_TIM8_CLK_SLEEP_DISABLE
+#define __TIM8_CLK_SLEEP_ENABLE __HAL_RCC_TIM8_CLK_SLEEP_ENABLE
+#define __TIM8_FORCE_RESET __HAL_RCC_TIM8_FORCE_RESET
+#define __TIM8_RELEASE_RESET __HAL_RCC_TIM8_RELEASE_RESET
+#define __TIM9_CLK_DISABLE __HAL_RCC_TIM9_CLK_DISABLE
+#define __TIM9_CLK_ENABLE __HAL_RCC_TIM9_CLK_ENABLE
+#define __TIM9_FORCE_RESET __HAL_RCC_TIM9_FORCE_RESET
+#define __TIM9_RELEASE_RESET __HAL_RCC_TIM9_RELEASE_RESET
+#define __TSC_CLK_DISABLE __HAL_RCC_TSC_CLK_DISABLE
+#define __TSC_CLK_ENABLE __HAL_RCC_TSC_CLK_ENABLE
+#define __TSC_CLK_SLEEP_DISABLE __HAL_RCC_TSC_CLK_SLEEP_DISABLE
+#define __TSC_CLK_SLEEP_ENABLE __HAL_RCC_TSC_CLK_SLEEP_ENABLE
+#define __TSC_FORCE_RESET __HAL_RCC_TSC_FORCE_RESET
+#define __TSC_RELEASE_RESET __HAL_RCC_TSC_RELEASE_RESET
+#define __UART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE
+#define __UART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE
+#define __UART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE
+#define __UART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE
+#define __UART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET
+#define __UART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET
+#define __UART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE
+#define __UART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE
+#define __UART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE
+#define __UART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE
+#define __UART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET
+#define __UART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET
+#define __USART1_CLK_DISABLE __HAL_RCC_USART1_CLK_DISABLE
+#define __USART1_CLK_ENABLE __HAL_RCC_USART1_CLK_ENABLE
+#define __USART1_CLK_SLEEP_DISABLE __HAL_RCC_USART1_CLK_SLEEP_DISABLE
+#define __USART1_CLK_SLEEP_ENABLE __HAL_RCC_USART1_CLK_SLEEP_ENABLE
+#define __USART1_FORCE_RESET __HAL_RCC_USART1_FORCE_RESET
+#define __USART1_RELEASE_RESET __HAL_RCC_USART1_RELEASE_RESET
+#define __USART2_CLK_DISABLE __HAL_RCC_USART2_CLK_DISABLE
+#define __USART2_CLK_ENABLE __HAL_RCC_USART2_CLK_ENABLE
+#define __USART2_CLK_SLEEP_DISABLE __HAL_RCC_USART2_CLK_SLEEP_DISABLE
+#define __USART2_CLK_SLEEP_ENABLE __HAL_RCC_USART2_CLK_SLEEP_ENABLE
+#define __USART2_FORCE_RESET __HAL_RCC_USART2_FORCE_RESET
+#define __USART2_RELEASE_RESET __HAL_RCC_USART2_RELEASE_RESET
+#define __USART3_CLK_DISABLE __HAL_RCC_USART3_CLK_DISABLE
+#define __USART3_CLK_ENABLE __HAL_RCC_USART3_CLK_ENABLE
+#define __USART3_CLK_SLEEP_DISABLE __HAL_RCC_USART3_CLK_SLEEP_DISABLE
+#define __USART3_CLK_SLEEP_ENABLE __HAL_RCC_USART3_CLK_SLEEP_ENABLE
+#define __USART3_FORCE_RESET __HAL_RCC_USART3_FORCE_RESET
+#define __USART3_RELEASE_RESET __HAL_RCC_USART3_RELEASE_RESET
+#define __USART4_CLK_DISABLE        __HAL_RCC_UART4_CLK_DISABLE
+#define __USART4_CLK_ENABLE         __HAL_RCC_UART4_CLK_ENABLE
+#define __USART4_CLK_SLEEP_ENABLE   __HAL_RCC_UART4_CLK_SLEEP_ENABLE
+#define __USART4_CLK_SLEEP_DISABLE  __HAL_RCC_UART4_CLK_SLEEP_DISABLE
+#define __USART4_FORCE_RESET        __HAL_RCC_UART4_FORCE_RESET
+#define __USART4_RELEASE_RESET      __HAL_RCC_UART4_RELEASE_RESET
+#define __USART5_CLK_DISABLE        __HAL_RCC_UART5_CLK_DISABLE
+#define __USART5_CLK_ENABLE         __HAL_RCC_UART5_CLK_ENABLE
+#define __USART5_CLK_SLEEP_ENABLE   __HAL_RCC_UART5_CLK_SLEEP_ENABLE
+#define __USART5_CLK_SLEEP_DISABLE  __HAL_RCC_UART5_CLK_SLEEP_DISABLE
+#define __USART5_FORCE_RESET        __HAL_RCC_UART5_FORCE_RESET
+#define __USART5_RELEASE_RESET      __HAL_RCC_UART5_RELEASE_RESET
+#define __USART7_CLK_DISABLE        __HAL_RCC_UART7_CLK_DISABLE
+#define __USART7_CLK_ENABLE         __HAL_RCC_UART7_CLK_ENABLE
+#define __USART7_FORCE_RESET        __HAL_RCC_UART7_FORCE_RESET
+#define __USART7_RELEASE_RESET      __HAL_RCC_UART7_RELEASE_RESET
+#define __USART8_CLK_DISABLE        __HAL_RCC_UART8_CLK_DISABLE
+#define __USART8_CLK_ENABLE         __HAL_RCC_UART8_CLK_ENABLE
+#define __USART8_FORCE_RESET        __HAL_RCC_UART8_FORCE_RESET
+#define __USART8_RELEASE_RESET      __HAL_RCC_UART8_RELEASE_RESET
+#define __USB_CLK_DISABLE         __HAL_RCC_USB_CLK_DISABLE
+#define __USB_CLK_ENABLE          __HAL_RCC_USB_CLK_ENABLE
+#define __USB_FORCE_RESET         __HAL_RCC_USB_FORCE_RESET
+#define __USB_CLK_SLEEP_ENABLE    __HAL_RCC_USB_CLK_SLEEP_ENABLE
+#define __USB_CLK_SLEEP_DISABLE   __HAL_RCC_USB_CLK_SLEEP_DISABLE
+#define __USB_OTG_FS_CLK_DISABLE __HAL_RCC_USB_OTG_FS_CLK_DISABLE
+#define __USB_OTG_FS_CLK_ENABLE __HAL_RCC_USB_OTG_FS_CLK_ENABLE
+#define __USB_RELEASE_RESET __HAL_RCC_USB_RELEASE_RESET
+
+#if defined(STM32H7)
+#define __HAL_RCC_WWDG_CLK_DISABLE   __HAL_RCC_WWDG1_CLK_DISABLE
+#define __HAL_RCC_WWDG_CLK_ENABLE   __HAL_RCC_WWDG1_CLK_ENABLE
+#define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE  __HAL_RCC_WWDG1_CLK_SLEEP_DISABLE
+#define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE  __HAL_RCC_WWDG1_CLK_SLEEP_ENABLE
+
+#define __HAL_RCC_WWDG_FORCE_RESET    ((void)0U)  /* Not available on the STM32H7*/
+#define __HAL_RCC_WWDG_RELEASE_RESET ((void)0U) /* Not available on the STM32H7*/
+
+
+#define  __HAL_RCC_WWDG_IS_CLK_ENABLED    __HAL_RCC_WWDG1_IS_CLK_ENABLED
+#define  __HAL_RCC_WWDG_IS_CLK_DISABLED  __HAL_RCC_WWDG1_IS_CLK_DISABLED
+#endif
+
+#define __WWDG_CLK_DISABLE __HAL_RCC_WWDG_CLK_DISABLE
+#define __WWDG_CLK_ENABLE __HAL_RCC_WWDG_CLK_ENABLE
+#define __WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG_CLK_SLEEP_DISABLE
+#define __WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG_CLK_SLEEP_ENABLE
+#define __WWDG_FORCE_RESET __HAL_RCC_WWDG_FORCE_RESET
+#define __WWDG_RELEASE_RESET __HAL_RCC_WWDG_RELEASE_RESET
+
+#define __TIM21_CLK_ENABLE   __HAL_RCC_TIM21_CLK_ENABLE
+#define __TIM21_CLK_DISABLE   __HAL_RCC_TIM21_CLK_DISABLE
+#define __TIM21_FORCE_RESET   __HAL_RCC_TIM21_FORCE_RESET
+#define __TIM21_RELEASE_RESET  __HAL_RCC_TIM21_RELEASE_RESET
+#define __TIM21_CLK_SLEEP_ENABLE   __HAL_RCC_TIM21_CLK_SLEEP_ENABLE
+#define __TIM21_CLK_SLEEP_DISABLE   __HAL_RCC_TIM21_CLK_SLEEP_DISABLE
+#define __TIM22_CLK_ENABLE   __HAL_RCC_TIM22_CLK_ENABLE
+#define __TIM22_CLK_DISABLE   __HAL_RCC_TIM22_CLK_DISABLE
+#define __TIM22_FORCE_RESET   __HAL_RCC_TIM22_FORCE_RESET
+#define __TIM22_RELEASE_RESET  __HAL_RCC_TIM22_RELEASE_RESET
+#define __TIM22_CLK_SLEEP_ENABLE   __HAL_RCC_TIM22_CLK_SLEEP_ENABLE
+#define __TIM22_CLK_SLEEP_DISABLE   __HAL_RCC_TIM22_CLK_SLEEP_DISABLE
+#define __CRS_CLK_DISABLE __HAL_RCC_CRS_CLK_DISABLE
+#define __CRS_CLK_ENABLE __HAL_RCC_CRS_CLK_ENABLE
+#define __CRS_CLK_SLEEP_DISABLE __HAL_RCC_CRS_CLK_SLEEP_DISABLE
+#define __CRS_CLK_SLEEP_ENABLE __HAL_RCC_CRS_CLK_SLEEP_ENABLE
+#define __CRS_FORCE_RESET __HAL_RCC_CRS_FORCE_RESET
+#define __CRS_RELEASE_RESET __HAL_RCC_CRS_RELEASE_RESET
+#define __RCC_BACKUPRESET_FORCE __HAL_RCC_BACKUPRESET_FORCE
+#define __RCC_BACKUPRESET_RELEASE __HAL_RCC_BACKUPRESET_RELEASE
+
+#define __USB_OTG_FS_FORCE_RESET  __HAL_RCC_USB_OTG_FS_FORCE_RESET
+#define __USB_OTG_FS_RELEASE_RESET  __HAL_RCC_USB_OTG_FS_RELEASE_RESET
+#define __USB_OTG_FS_CLK_SLEEP_ENABLE  __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE
+#define __USB_OTG_FS_CLK_SLEEP_DISABLE  __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE
+#define __USB_OTG_HS_CLK_DISABLE  __HAL_RCC_USB_OTG_HS_CLK_DISABLE
+#define __USB_OTG_HS_CLK_ENABLE          __HAL_RCC_USB_OTG_HS_CLK_ENABLE
+#define __USB_OTG_HS_ULPI_CLK_ENABLE  __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE
+#define __USB_OTG_HS_ULPI_CLK_DISABLE  __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE
+#define __TIM9_CLK_SLEEP_ENABLE          __HAL_RCC_TIM9_CLK_SLEEP_ENABLE
+#define __TIM9_CLK_SLEEP_DISABLE  __HAL_RCC_TIM9_CLK_SLEEP_DISABLE
+#define __TIM10_CLK_SLEEP_ENABLE  __HAL_RCC_TIM10_CLK_SLEEP_ENABLE
+#define __TIM10_CLK_SLEEP_DISABLE  __HAL_RCC_TIM10_CLK_SLEEP_DISABLE
+#define __TIM11_CLK_SLEEP_ENABLE  __HAL_RCC_TIM11_CLK_SLEEP_ENABLE
+#define __TIM11_CLK_SLEEP_DISABLE  __HAL_RCC_TIM11_CLK_SLEEP_DISABLE
+#define __ETHMACPTP_CLK_SLEEP_ENABLE  __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE
+#define __ETHMACPTP_CLK_SLEEP_DISABLE  __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE
+#define __ETHMACPTP_CLK_ENABLE          __HAL_RCC_ETHMACPTP_CLK_ENABLE
+#define __ETHMACPTP_CLK_DISABLE          __HAL_RCC_ETHMACPTP_CLK_DISABLE
+#define __HASH_CLK_ENABLE          __HAL_RCC_HASH_CLK_ENABLE
+#define __HASH_FORCE_RESET          __HAL_RCC_HASH_FORCE_RESET
+#define __HASH_RELEASE_RESET          __HAL_RCC_HASH_RELEASE_RESET
+#define __HASH_CLK_SLEEP_ENABLE          __HAL_RCC_HASH_CLK_SLEEP_ENABLE
+#define __HASH_CLK_SLEEP_DISABLE  __HAL_RCC_HASH_CLK_SLEEP_DISABLE
+#define __HASH_CLK_DISABLE            __HAL_RCC_HASH_CLK_DISABLE
+#define __SPI5_CLK_ENABLE          __HAL_RCC_SPI5_CLK_ENABLE
+#define __SPI5_CLK_DISABLE              __HAL_RCC_SPI5_CLK_DISABLE
+#define __SPI5_FORCE_RESET          __HAL_RCC_SPI5_FORCE_RESET
+#define __SPI5_RELEASE_RESET          __HAL_RCC_SPI5_RELEASE_RESET
+#define __SPI5_CLK_SLEEP_ENABLE          __HAL_RCC_SPI5_CLK_SLEEP_ENABLE
+#define __SPI5_CLK_SLEEP_DISABLE  __HAL_RCC_SPI5_CLK_SLEEP_DISABLE
+#define __SPI6_CLK_ENABLE          __HAL_RCC_SPI6_CLK_ENABLE
+#define __SPI6_CLK_DISABLE          __HAL_RCC_SPI6_CLK_DISABLE
+#define __SPI6_FORCE_RESET          __HAL_RCC_SPI6_FORCE_RESET
+#define __SPI6_RELEASE_RESET         __HAL_RCC_SPI6_RELEASE_RESET
+#define __SPI6_CLK_SLEEP_ENABLE          __HAL_RCC_SPI6_CLK_SLEEP_ENABLE
+#define __SPI6_CLK_SLEEP_DISABLE  __HAL_RCC_SPI6_CLK_SLEEP_DISABLE
+#define __LTDC_CLK_ENABLE          __HAL_RCC_LTDC_CLK_ENABLE
+#define __LTDC_CLK_DISABLE          __HAL_RCC_LTDC_CLK_DISABLE
+#define __LTDC_FORCE_RESET          __HAL_RCC_LTDC_FORCE_RESET
+#define __LTDC_RELEASE_RESET          __HAL_RCC_LTDC_RELEASE_RESET
+#define __LTDC_CLK_SLEEP_ENABLE          __HAL_RCC_LTDC_CLK_SLEEP_ENABLE
+#define __ETHMAC_CLK_SLEEP_ENABLE  __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE
+#define __ETHMAC_CLK_SLEEP_DISABLE  __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE
+#define __ETHMACTX_CLK_SLEEP_ENABLE  __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE
+#define __ETHMACTX_CLK_SLEEP_DISABLE  __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE
+#define __ETHMACRX_CLK_SLEEP_ENABLE  __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE
+#define __ETHMACRX_CLK_SLEEP_DISABLE  __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE
+#define __TIM12_CLK_SLEEP_ENABLE  __HAL_RCC_TIM12_CLK_SLEEP_ENABLE
+#define __TIM12_CLK_SLEEP_DISABLE  __HAL_RCC_TIM12_CLK_SLEEP_DISABLE
+#define __TIM13_CLK_SLEEP_ENABLE  __HAL_RCC_TIM13_CLK_SLEEP_ENABLE
+#define __TIM13_CLK_SLEEP_DISABLE  __HAL_RCC_TIM13_CLK_SLEEP_DISABLE
+#define __TIM14_CLK_SLEEP_ENABLE  __HAL_RCC_TIM14_CLK_SLEEP_ENABLE
+#define __TIM14_CLK_SLEEP_DISABLE  __HAL_RCC_TIM14_CLK_SLEEP_DISABLE
+#define __BKPSRAM_CLK_ENABLE          __HAL_RCC_BKPSRAM_CLK_ENABLE
+#define __BKPSRAM_CLK_DISABLE          __HAL_RCC_BKPSRAM_CLK_DISABLE
+#define __BKPSRAM_CLK_SLEEP_ENABLE  __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE
+#define __BKPSRAM_CLK_SLEEP_DISABLE  __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE
+#define __CCMDATARAMEN_CLK_ENABLE  __HAL_RCC_CCMDATARAMEN_CLK_ENABLE
+#define __CCMDATARAMEN_CLK_DISABLE  __HAL_RCC_CCMDATARAMEN_CLK_DISABLE
+#define __USART6_CLK_ENABLE          __HAL_RCC_USART6_CLK_ENABLE
+#define __USART6_CLK_DISABLE          __HAL_RCC_USART6_CLK_DISABLE
+#define __USART6_FORCE_RESET        __HAL_RCC_USART6_FORCE_RESET
+#define __USART6_RELEASE_RESET        __HAL_RCC_USART6_RELEASE_RESET
+#define __USART6_CLK_SLEEP_ENABLE  __HAL_RCC_USART6_CLK_SLEEP_ENABLE
+#define __USART6_CLK_SLEEP_DISABLE  __HAL_RCC_USART6_CLK_SLEEP_DISABLE
+#define __SPI4_CLK_ENABLE          __HAL_RCC_SPI4_CLK_ENABLE
+#define __SPI4_CLK_DISABLE          __HAL_RCC_SPI4_CLK_DISABLE
+#define __SPI4_FORCE_RESET          __HAL_RCC_SPI4_FORCE_RESET
+#define __SPI4_RELEASE_RESET        __HAL_RCC_SPI4_RELEASE_RESET
+#define __SPI4_CLK_SLEEP_ENABLE   __HAL_RCC_SPI4_CLK_SLEEP_ENABLE
+#define __SPI4_CLK_SLEEP_DISABLE  __HAL_RCC_SPI4_CLK_SLEEP_DISABLE
+#define __GPIOI_CLK_ENABLE          __HAL_RCC_GPIOI_CLK_ENABLE
+#define __GPIOI_CLK_DISABLE          __HAL_RCC_GPIOI_CLK_DISABLE
+#define __GPIOI_FORCE_RESET          __HAL_RCC_GPIOI_FORCE_RESET
+#define __GPIOI_RELEASE_RESET          __HAL_RCC_GPIOI_RELEASE_RESET
+#define __GPIOI_CLK_SLEEP_ENABLE  __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE
+#define __GPIOI_CLK_SLEEP_DISABLE  __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE
+#define __GPIOJ_CLK_ENABLE          __HAL_RCC_GPIOJ_CLK_ENABLE
+#define __GPIOJ_CLK_DISABLE          __HAL_RCC_GPIOJ_CLK_DISABLE
+#define __GPIOJ_FORCE_RESET         __HAL_RCC_GPIOJ_FORCE_RESET
+#define __GPIOJ_RELEASE_RESET          __HAL_RCC_GPIOJ_RELEASE_RESET
+#define __GPIOJ_CLK_SLEEP_ENABLE  __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE
+#define __GPIOJ_CLK_SLEEP_DISABLE  __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE
+#define __GPIOK_CLK_ENABLE          __HAL_RCC_GPIOK_CLK_ENABLE
+#define __GPIOK_CLK_DISABLE          __HAL_RCC_GPIOK_CLK_DISABLE
+#define __GPIOK_RELEASE_RESET          __HAL_RCC_GPIOK_RELEASE_RESET
+#define __GPIOK_CLK_SLEEP_ENABLE  __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE
+#define __GPIOK_CLK_SLEEP_DISABLE  __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE
+#define __ETH_CLK_ENABLE          __HAL_RCC_ETH_CLK_ENABLE
+#define __ETH_CLK_DISABLE          __HAL_RCC_ETH_CLK_DISABLE
+#define __DCMI_CLK_ENABLE          __HAL_RCC_DCMI_CLK_ENABLE
+#define __DCMI_CLK_DISABLE          __HAL_RCC_DCMI_CLK_DISABLE
+#define __DCMI_FORCE_RESET          __HAL_RCC_DCMI_FORCE_RESET
+#define __DCMI_RELEASE_RESET          __HAL_RCC_DCMI_RELEASE_RESET
+#define __DCMI_CLK_SLEEP_ENABLE   __HAL_RCC_DCMI_CLK_SLEEP_ENABLE
+#define __DCMI_CLK_SLEEP_DISABLE  __HAL_RCC_DCMI_CLK_SLEEP_DISABLE
+#define __UART7_CLK_ENABLE          __HAL_RCC_UART7_CLK_ENABLE
+#define __UART7_CLK_DISABLE          __HAL_RCC_UART7_CLK_DISABLE
+#define __UART7_RELEASE_RESET       __HAL_RCC_UART7_RELEASE_RESET
+#define __UART7_FORCE_RESET       __HAL_RCC_UART7_FORCE_RESET
+#define __UART7_CLK_SLEEP_ENABLE  __HAL_RCC_UART7_CLK_SLEEP_ENABLE
+#define __UART7_CLK_SLEEP_DISABLE  __HAL_RCC_UART7_CLK_SLEEP_DISABLE
+#define __UART8_CLK_ENABLE          __HAL_RCC_UART8_CLK_ENABLE
+#define __UART8_CLK_DISABLE          __HAL_RCC_UART8_CLK_DISABLE
+#define __UART8_FORCE_RESET          __HAL_RCC_UART8_FORCE_RESET
+#define __UART8_RELEASE_RESET          __HAL_RCC_UART8_RELEASE_RESET
+#define __UART8_CLK_SLEEP_ENABLE  __HAL_RCC_UART8_CLK_SLEEP_ENABLE
+#define __UART8_CLK_SLEEP_DISABLE  __HAL_RCC_UART8_CLK_SLEEP_DISABLE
+#define __OTGHS_CLK_SLEEP_ENABLE  __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE
+#define __OTGHS_CLK_SLEEP_DISABLE  __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE
+#define __OTGHS_FORCE_RESET          __HAL_RCC_USB_OTG_HS_FORCE_RESET
+#define __OTGHS_RELEASE_RESET          __HAL_RCC_USB_OTG_HS_RELEASE_RESET
+#define __OTGHSULPI_CLK_SLEEP_ENABLE  __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE
+#define __OTGHSULPI_CLK_SLEEP_DISABLE  __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE
+#define __HAL_RCC_OTGHS_CLK_SLEEP_ENABLE  __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE
+#define __HAL_RCC_OTGHS_CLK_SLEEP_DISABLE  __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE
+#define __HAL_RCC_OTGHS_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_ENABLED
+#define __HAL_RCC_OTGHS_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_DISABLED
+#define __HAL_RCC_OTGHS_FORCE_RESET          __HAL_RCC_USB_OTG_HS_FORCE_RESET
+#define __HAL_RCC_OTGHS_RELEASE_RESET          __HAL_RCC_USB_OTG_HS_RELEASE_RESET
+#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_ENABLE      __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE
+#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_DISABLE     __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE
+#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_ENABLED  __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED
+#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED
+#define __SRAM3_CLK_SLEEP_ENABLE       __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE
+#define __CAN2_CLK_SLEEP_ENABLE        __HAL_RCC_CAN2_CLK_SLEEP_ENABLE
+#define __CAN2_CLK_SLEEP_DISABLE       __HAL_RCC_CAN2_CLK_SLEEP_DISABLE
+#define __DAC_CLK_SLEEP_ENABLE         __HAL_RCC_DAC_CLK_SLEEP_ENABLE
+#define __DAC_CLK_SLEEP_DISABLE        __HAL_RCC_DAC_CLK_SLEEP_DISABLE
+#define __ADC2_CLK_SLEEP_ENABLE        __HAL_RCC_ADC2_CLK_SLEEP_ENABLE
+#define __ADC2_CLK_SLEEP_DISABLE       __HAL_RCC_ADC2_CLK_SLEEP_DISABLE
+#define __ADC3_CLK_SLEEP_ENABLE        __HAL_RCC_ADC3_CLK_SLEEP_ENABLE
+#define __ADC3_CLK_SLEEP_DISABLE       __HAL_RCC_ADC3_CLK_SLEEP_DISABLE
+#define __FSMC_FORCE_RESET             __HAL_RCC_FSMC_FORCE_RESET
+#define __FSMC_RELEASE_RESET           __HAL_RCC_FSMC_RELEASE_RESET
+#define __FSMC_CLK_SLEEP_ENABLE        __HAL_RCC_FSMC_CLK_SLEEP_ENABLE
+#define __FSMC_CLK_SLEEP_DISABLE       __HAL_RCC_FSMC_CLK_SLEEP_DISABLE
+#define __SDIO_FORCE_RESET             __HAL_RCC_SDIO_FORCE_RESET
+#define __SDIO_RELEASE_RESET           __HAL_RCC_SDIO_RELEASE_RESET
+#define __SDIO_CLK_SLEEP_DISABLE       __HAL_RCC_SDIO_CLK_SLEEP_DISABLE
+#define __SDIO_CLK_SLEEP_ENABLE        __HAL_RCC_SDIO_CLK_SLEEP_ENABLE
+#define __DMA2D_CLK_ENABLE             __HAL_RCC_DMA2D_CLK_ENABLE
+#define __DMA2D_CLK_DISABLE            __HAL_RCC_DMA2D_CLK_DISABLE
+#define __DMA2D_FORCE_RESET            __HAL_RCC_DMA2D_FORCE_RESET
+#define __DMA2D_RELEASE_RESET          __HAL_RCC_DMA2D_RELEASE_RESET
+#define __DMA2D_CLK_SLEEP_ENABLE       __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE
+#define __DMA2D_CLK_SLEEP_DISABLE      __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE
+
+/* alias define maintained for legacy */
+#define __HAL_RCC_OTGFS_FORCE_RESET    __HAL_RCC_USB_OTG_FS_FORCE_RESET
+#define __HAL_RCC_OTGFS_RELEASE_RESET  __HAL_RCC_USB_OTG_FS_RELEASE_RESET
+
+#define __ADC12_CLK_ENABLE          __HAL_RCC_ADC12_CLK_ENABLE
+#define __ADC12_CLK_DISABLE         __HAL_RCC_ADC12_CLK_DISABLE
+#define __ADC34_CLK_ENABLE          __HAL_RCC_ADC34_CLK_ENABLE
+#define __ADC34_CLK_DISABLE         __HAL_RCC_ADC34_CLK_DISABLE
+#define __DAC2_CLK_ENABLE           __HAL_RCC_DAC2_CLK_ENABLE
+#define __DAC2_CLK_DISABLE          __HAL_RCC_DAC2_CLK_DISABLE
+#define __TIM18_CLK_ENABLE          __HAL_RCC_TIM18_CLK_ENABLE
+#define __TIM18_CLK_DISABLE         __HAL_RCC_TIM18_CLK_DISABLE
+#define __TIM19_CLK_ENABLE          __HAL_RCC_TIM19_CLK_ENABLE
+#define __TIM19_CLK_DISABLE         __HAL_RCC_TIM19_CLK_DISABLE
+#define __TIM20_CLK_ENABLE          __HAL_RCC_TIM20_CLK_ENABLE
+#define __TIM20_CLK_DISABLE         __HAL_RCC_TIM20_CLK_DISABLE
+#define __HRTIM1_CLK_ENABLE         __HAL_RCC_HRTIM1_CLK_ENABLE
+#define __HRTIM1_CLK_DISABLE        __HAL_RCC_HRTIM1_CLK_DISABLE
+#define __SDADC1_CLK_ENABLE         __HAL_RCC_SDADC1_CLK_ENABLE
+#define __SDADC2_CLK_ENABLE         __HAL_RCC_SDADC2_CLK_ENABLE
+#define __SDADC3_CLK_ENABLE         __HAL_RCC_SDADC3_CLK_ENABLE
+#define __SDADC1_CLK_DISABLE        __HAL_RCC_SDADC1_CLK_DISABLE
+#define __SDADC2_CLK_DISABLE        __HAL_RCC_SDADC2_CLK_DISABLE
+#define __SDADC3_CLK_DISABLE        __HAL_RCC_SDADC3_CLK_DISABLE
+
+#define __ADC12_FORCE_RESET         __HAL_RCC_ADC12_FORCE_RESET
+#define __ADC12_RELEASE_RESET       __HAL_RCC_ADC12_RELEASE_RESET
+#define __ADC34_FORCE_RESET         __HAL_RCC_ADC34_FORCE_RESET
+#define __ADC34_RELEASE_RESET       __HAL_RCC_ADC34_RELEASE_RESET
+#define __DAC2_FORCE_RESET          __HAL_RCC_DAC2_FORCE_RESET
+#define __DAC2_RELEASE_RESET        __HAL_RCC_DAC2_RELEASE_RESET
+#define __TIM18_FORCE_RESET         __HAL_RCC_TIM18_FORCE_RESET
+#define __TIM18_RELEASE_RESET       __HAL_RCC_TIM18_RELEASE_RESET
+#define __TIM19_FORCE_RESET         __HAL_RCC_TIM19_FORCE_RESET
+#define __TIM19_RELEASE_RESET       __HAL_RCC_TIM19_RELEASE_RESET
+#define __TIM20_FORCE_RESET         __HAL_RCC_TIM20_FORCE_RESET
+#define __TIM20_RELEASE_RESET       __HAL_RCC_TIM20_RELEASE_RESET
+#define __HRTIM1_FORCE_RESET        __HAL_RCC_HRTIM1_FORCE_RESET
+#define __HRTIM1_RELEASE_RESET      __HAL_RCC_HRTIM1_RELEASE_RESET
+#define __SDADC1_FORCE_RESET        __HAL_RCC_SDADC1_FORCE_RESET
+#define __SDADC2_FORCE_RESET        __HAL_RCC_SDADC2_FORCE_RESET
+#define __SDADC3_FORCE_RESET        __HAL_RCC_SDADC3_FORCE_RESET
+#define __SDADC1_RELEASE_RESET      __HAL_RCC_SDADC1_RELEASE_RESET
+#define __SDADC2_RELEASE_RESET      __HAL_RCC_SDADC2_RELEASE_RESET
+#define __SDADC3_RELEASE_RESET      __HAL_RCC_SDADC3_RELEASE_RESET
+
+#define __ADC1_IS_CLK_ENABLED       __HAL_RCC_ADC1_IS_CLK_ENABLED
+#define __ADC1_IS_CLK_DISABLED      __HAL_RCC_ADC1_IS_CLK_DISABLED
+#define __ADC12_IS_CLK_ENABLED      __HAL_RCC_ADC12_IS_CLK_ENABLED
+#define __ADC12_IS_CLK_DISABLED     __HAL_RCC_ADC12_IS_CLK_DISABLED
+#define __ADC34_IS_CLK_ENABLED      __HAL_RCC_ADC34_IS_CLK_ENABLED
+#define __ADC34_IS_CLK_DISABLED     __HAL_RCC_ADC34_IS_CLK_DISABLED
+#define __CEC_IS_CLK_ENABLED        __HAL_RCC_CEC_IS_CLK_ENABLED
+#define __CEC_IS_CLK_DISABLED       __HAL_RCC_CEC_IS_CLK_DISABLED
+#define __CRC_IS_CLK_ENABLED        __HAL_RCC_CRC_IS_CLK_ENABLED
+#define __CRC_IS_CLK_DISABLED       __HAL_RCC_CRC_IS_CLK_DISABLED
+#define __DAC1_IS_CLK_ENABLED       __HAL_RCC_DAC1_IS_CLK_ENABLED
+#define __DAC1_IS_CLK_DISABLED      __HAL_RCC_DAC1_IS_CLK_DISABLED
+#define __DAC2_IS_CLK_ENABLED       __HAL_RCC_DAC2_IS_CLK_ENABLED
+#define __DAC2_IS_CLK_DISABLED      __HAL_RCC_DAC2_IS_CLK_DISABLED
+#define __DMA1_IS_CLK_ENABLED       __HAL_RCC_DMA1_IS_CLK_ENABLED
+#define __DMA1_IS_CLK_DISABLED      __HAL_RCC_DMA1_IS_CLK_DISABLED
+#define __DMA2_IS_CLK_ENABLED       __HAL_RCC_DMA2_IS_CLK_ENABLED
+#define __DMA2_IS_CLK_DISABLED      __HAL_RCC_DMA2_IS_CLK_DISABLED
+#define __FLITF_IS_CLK_ENABLED      __HAL_RCC_FLITF_IS_CLK_ENABLED
+#define __FLITF_IS_CLK_DISABLED     __HAL_RCC_FLITF_IS_CLK_DISABLED
+#define __FMC_IS_CLK_ENABLED        __HAL_RCC_FMC_IS_CLK_ENABLED
+#define __FMC_IS_CLK_DISABLED       __HAL_RCC_FMC_IS_CLK_DISABLED
+#define __GPIOA_IS_CLK_ENABLED      __HAL_RCC_GPIOA_IS_CLK_ENABLED
+#define __GPIOA_IS_CLK_DISABLED     __HAL_RCC_GPIOA_IS_CLK_DISABLED
+#define __GPIOB_IS_CLK_ENABLED      __HAL_RCC_GPIOB_IS_CLK_ENABLED
+#define __GPIOB_IS_CLK_DISABLED     __HAL_RCC_GPIOB_IS_CLK_DISABLED
+#define __GPIOC_IS_CLK_ENABLED      __HAL_RCC_GPIOC_IS_CLK_ENABLED
+#define __GPIOC_IS_CLK_DISABLED     __HAL_RCC_GPIOC_IS_CLK_DISABLED
+#define __GPIOD_IS_CLK_ENABLED      __HAL_RCC_GPIOD_IS_CLK_ENABLED
+#define __GPIOD_IS_CLK_DISABLED     __HAL_RCC_GPIOD_IS_CLK_DISABLED
+#define __GPIOE_IS_CLK_ENABLED      __HAL_RCC_GPIOE_IS_CLK_ENABLED
+#define __GPIOE_IS_CLK_DISABLED     __HAL_RCC_GPIOE_IS_CLK_DISABLED
+#define __GPIOF_IS_CLK_ENABLED      __HAL_RCC_GPIOF_IS_CLK_ENABLED
+#define __GPIOF_IS_CLK_DISABLED     __HAL_RCC_GPIOF_IS_CLK_DISABLED
+#define __GPIOG_IS_CLK_ENABLED      __HAL_RCC_GPIOG_IS_CLK_ENABLED
+#define __GPIOG_IS_CLK_DISABLED     __HAL_RCC_GPIOG_IS_CLK_DISABLED
+#define __GPIOH_IS_CLK_ENABLED      __HAL_RCC_GPIOH_IS_CLK_ENABLED
+#define __GPIOH_IS_CLK_DISABLED     __HAL_RCC_GPIOH_IS_CLK_DISABLED
+#define __HRTIM1_IS_CLK_ENABLED     __HAL_RCC_HRTIM1_IS_CLK_ENABLED
+#define __HRTIM1_IS_CLK_DISABLED    __HAL_RCC_HRTIM1_IS_CLK_DISABLED
+#define __I2C1_IS_CLK_ENABLED       __HAL_RCC_I2C1_IS_CLK_ENABLED
+#define __I2C1_IS_CLK_DISABLED      __HAL_RCC_I2C1_IS_CLK_DISABLED
+#define __I2C2_IS_CLK_ENABLED       __HAL_RCC_I2C2_IS_CLK_ENABLED
+#define __I2C2_IS_CLK_DISABLED      __HAL_RCC_I2C2_IS_CLK_DISABLED
+#define __I2C3_IS_CLK_ENABLED       __HAL_RCC_I2C3_IS_CLK_ENABLED
+#define __I2C3_IS_CLK_DISABLED      __HAL_RCC_I2C3_IS_CLK_DISABLED
+#define __PWR_IS_CLK_ENABLED        __HAL_RCC_PWR_IS_CLK_ENABLED
+#define __PWR_IS_CLK_DISABLED       __HAL_RCC_PWR_IS_CLK_DISABLED
+#define __SYSCFG_IS_CLK_ENABLED     __HAL_RCC_SYSCFG_IS_CLK_ENABLED
+#define __SYSCFG_IS_CLK_DISABLED    __HAL_RCC_SYSCFG_IS_CLK_DISABLED
+#define __SPI1_IS_CLK_ENABLED       __HAL_RCC_SPI1_IS_CLK_ENABLED
+#define __SPI1_IS_CLK_DISABLED      __HAL_RCC_SPI1_IS_CLK_DISABLED
+#define __SPI2_IS_CLK_ENABLED       __HAL_RCC_SPI2_IS_CLK_ENABLED
+#define __SPI2_IS_CLK_DISABLED      __HAL_RCC_SPI2_IS_CLK_DISABLED
+#define __SPI3_IS_CLK_ENABLED       __HAL_RCC_SPI3_IS_CLK_ENABLED
+#define __SPI3_IS_CLK_DISABLED      __HAL_RCC_SPI3_IS_CLK_DISABLED
+#define __SPI4_IS_CLK_ENABLED       __HAL_RCC_SPI4_IS_CLK_ENABLED
+#define __SPI4_IS_CLK_DISABLED      __HAL_RCC_SPI4_IS_CLK_DISABLED
+#define __SDADC1_IS_CLK_ENABLED     __HAL_RCC_SDADC1_IS_CLK_ENABLED
+#define __SDADC1_IS_CLK_DISABLED    __HAL_RCC_SDADC1_IS_CLK_DISABLED
+#define __SDADC2_IS_CLK_ENABLED     __HAL_RCC_SDADC2_IS_CLK_ENABLED
+#define __SDADC2_IS_CLK_DISABLED    __HAL_RCC_SDADC2_IS_CLK_DISABLED
+#define __SDADC3_IS_CLK_ENABLED     __HAL_RCC_SDADC3_IS_CLK_ENABLED
+#define __SDADC3_IS_CLK_DISABLED    __HAL_RCC_SDADC3_IS_CLK_DISABLED
+#define __SRAM_IS_CLK_ENABLED       __HAL_RCC_SRAM_IS_CLK_ENABLED
+#define __SRAM_IS_CLK_DISABLED      __HAL_RCC_SRAM_IS_CLK_DISABLED
+#define __TIM1_IS_CLK_ENABLED       __HAL_RCC_TIM1_IS_CLK_ENABLED
+#define __TIM1_IS_CLK_DISABLED      __HAL_RCC_TIM1_IS_CLK_DISABLED
+#define __TIM2_IS_CLK_ENABLED       __HAL_RCC_TIM2_IS_CLK_ENABLED
+#define __TIM2_IS_CLK_DISABLED      __HAL_RCC_TIM2_IS_CLK_DISABLED
+#define __TIM3_IS_CLK_ENABLED       __HAL_RCC_TIM3_IS_CLK_ENABLED
+#define __TIM3_IS_CLK_DISABLED      __HAL_RCC_TIM3_IS_CLK_DISABLED
+#define __TIM4_IS_CLK_ENABLED       __HAL_RCC_TIM4_IS_CLK_ENABLED
+#define __TIM4_IS_CLK_DISABLED      __HAL_RCC_TIM4_IS_CLK_DISABLED
+#define __TIM5_IS_CLK_ENABLED       __HAL_RCC_TIM5_IS_CLK_ENABLED
+#define __TIM5_IS_CLK_DISABLED      __HAL_RCC_TIM5_IS_CLK_DISABLED
+#define __TIM6_IS_CLK_ENABLED       __HAL_RCC_TIM6_IS_CLK_ENABLED
+#define __TIM6_IS_CLK_DISABLED      __HAL_RCC_TIM6_IS_CLK_DISABLED
+#define __TIM7_IS_CLK_ENABLED       __HAL_RCC_TIM7_IS_CLK_ENABLED
+#define __TIM7_IS_CLK_DISABLED      __HAL_RCC_TIM7_IS_CLK_DISABLED
+#define __TIM8_IS_CLK_ENABLED       __HAL_RCC_TIM8_IS_CLK_ENABLED
+#define __TIM8_IS_CLK_DISABLED      __HAL_RCC_TIM8_IS_CLK_DISABLED
+#define __TIM12_IS_CLK_ENABLED      __HAL_RCC_TIM12_IS_CLK_ENABLED
+#define __TIM12_IS_CLK_DISABLED     __HAL_RCC_TIM12_IS_CLK_DISABLED
+#define __TIM13_IS_CLK_ENABLED      __HAL_RCC_TIM13_IS_CLK_ENABLED
+#define __TIM13_IS_CLK_DISABLED     __HAL_RCC_TIM13_IS_CLK_DISABLED
+#define __TIM14_IS_CLK_ENABLED      __HAL_RCC_TIM14_IS_CLK_ENABLED
+#define __TIM14_IS_CLK_DISABLED     __HAL_RCC_TIM14_IS_CLK_DISABLED
+#define __TIM15_IS_CLK_ENABLED      __HAL_RCC_TIM15_IS_CLK_ENABLED
+#define __TIM15_IS_CLK_DISABLED     __HAL_RCC_TIM15_IS_CLK_DISABLED
+#define __TIM16_IS_CLK_ENABLED      __HAL_RCC_TIM16_IS_CLK_ENABLED
+#define __TIM16_IS_CLK_DISABLED     __HAL_RCC_TIM16_IS_CLK_DISABLED
+#define __TIM17_IS_CLK_ENABLED      __HAL_RCC_TIM17_IS_CLK_ENABLED
+#define __TIM17_IS_CLK_DISABLED     __HAL_RCC_TIM17_IS_CLK_DISABLED
+#define __TIM18_IS_CLK_ENABLED      __HAL_RCC_TIM18_IS_CLK_ENABLED
+#define __TIM18_IS_CLK_DISABLED     __HAL_RCC_TIM18_IS_CLK_DISABLED
+#define __TIM19_IS_CLK_ENABLED      __HAL_RCC_TIM19_IS_CLK_ENABLED
+#define __TIM19_IS_CLK_DISABLED     __HAL_RCC_TIM19_IS_CLK_DISABLED
+#define __TIM20_IS_CLK_ENABLED      __HAL_RCC_TIM20_IS_CLK_ENABLED
+#define __TIM20_IS_CLK_DISABLED     __HAL_RCC_TIM20_IS_CLK_DISABLED
+#define __TSC_IS_CLK_ENABLED        __HAL_RCC_TSC_IS_CLK_ENABLED
+#define __TSC_IS_CLK_DISABLED       __HAL_RCC_TSC_IS_CLK_DISABLED
+#define __UART4_IS_CLK_ENABLED      __HAL_RCC_UART4_IS_CLK_ENABLED
+#define __UART4_IS_CLK_DISABLED     __HAL_RCC_UART4_IS_CLK_DISABLED
+#define __UART5_IS_CLK_ENABLED      __HAL_RCC_UART5_IS_CLK_ENABLED
+#define __UART5_IS_CLK_DISABLED     __HAL_RCC_UART5_IS_CLK_DISABLED
+#define __USART1_IS_CLK_ENABLED     __HAL_RCC_USART1_IS_CLK_ENABLED
+#define __USART1_IS_CLK_DISABLED    __HAL_RCC_USART1_IS_CLK_DISABLED
+#define __USART2_IS_CLK_ENABLED     __HAL_RCC_USART2_IS_CLK_ENABLED
+#define __USART2_IS_CLK_DISABLED    __HAL_RCC_USART2_IS_CLK_DISABLED
+#define __USART3_IS_CLK_ENABLED     __HAL_RCC_USART3_IS_CLK_ENABLED
+#define __USART3_IS_CLK_DISABLED    __HAL_RCC_USART3_IS_CLK_DISABLED
+#define __USB_IS_CLK_ENABLED        __HAL_RCC_USB_IS_CLK_ENABLED
+#define __USB_IS_CLK_DISABLED       __HAL_RCC_USB_IS_CLK_DISABLED
+#define __WWDG_IS_CLK_ENABLED       __HAL_RCC_WWDG_IS_CLK_ENABLED
+#define __WWDG_IS_CLK_DISABLED      __HAL_RCC_WWDG_IS_CLK_DISABLED
+
+#if defined(STM32L1)
+#define __HAL_RCC_CRYP_CLK_DISABLE         __HAL_RCC_AES_CLK_DISABLE
+#define __HAL_RCC_CRYP_CLK_ENABLE          __HAL_RCC_AES_CLK_ENABLE
+#define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE   __HAL_RCC_AES_CLK_SLEEP_DISABLE
+#define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE    __HAL_RCC_AES_CLK_SLEEP_ENABLE
+#define __HAL_RCC_CRYP_FORCE_RESET         __HAL_RCC_AES_FORCE_RESET
+#define __HAL_RCC_CRYP_RELEASE_RESET       __HAL_RCC_AES_RELEASE_RESET
+#endif /* STM32L1 */
+
+#if defined(STM32F4)
+#define __HAL_RCC_SDMMC1_FORCE_RESET       __HAL_RCC_SDIO_FORCE_RESET
+#define __HAL_RCC_SDMMC1_RELEASE_RESET     __HAL_RCC_SDIO_RELEASE_RESET
+#define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE  __HAL_RCC_SDIO_CLK_SLEEP_ENABLE
+#define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE
+#define __HAL_RCC_SDMMC1_CLK_ENABLE        __HAL_RCC_SDIO_CLK_ENABLE
+#define __HAL_RCC_SDMMC1_CLK_DISABLE       __HAL_RCC_SDIO_CLK_DISABLE
+#define __HAL_RCC_SDMMC1_IS_CLK_ENABLED    __HAL_RCC_SDIO_IS_CLK_ENABLED
+#define __HAL_RCC_SDMMC1_IS_CLK_DISABLED   __HAL_RCC_SDIO_IS_CLK_DISABLED
+#define Sdmmc1ClockSelection               SdioClockSelection
+#define RCC_PERIPHCLK_SDMMC1               RCC_PERIPHCLK_SDIO
+#define RCC_SDMMC1CLKSOURCE_CLK48          RCC_SDIOCLKSOURCE_CK48
+#define RCC_SDMMC1CLKSOURCE_SYSCLK         RCC_SDIOCLKSOURCE_SYSCLK
+#define __HAL_RCC_SDMMC1_CONFIG            __HAL_RCC_SDIO_CONFIG
+#define __HAL_RCC_GET_SDMMC1_SOURCE        __HAL_RCC_GET_SDIO_SOURCE
+#endif
+
+#if defined(STM32F7) || defined(STM32L4)
+#define __HAL_RCC_SDIO_FORCE_RESET         __HAL_RCC_SDMMC1_FORCE_RESET
+#define __HAL_RCC_SDIO_RELEASE_RESET       __HAL_RCC_SDMMC1_RELEASE_RESET
+#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE    __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE
+#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE   __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE
+#define __HAL_RCC_SDIO_CLK_ENABLE          __HAL_RCC_SDMMC1_CLK_ENABLE
+#define __HAL_RCC_SDIO_CLK_DISABLE         __HAL_RCC_SDMMC1_CLK_DISABLE
+#define __HAL_RCC_SDIO_IS_CLK_ENABLED      __HAL_RCC_SDMMC1_IS_CLK_ENABLED
+#define __HAL_RCC_SDIO_IS_CLK_DISABLED     __HAL_RCC_SDMMC1_IS_CLK_DISABLED
+#define SdioClockSelection                 Sdmmc1ClockSelection
+#define RCC_PERIPHCLK_SDIO                 RCC_PERIPHCLK_SDMMC1
+#define __HAL_RCC_SDIO_CONFIG              __HAL_RCC_SDMMC1_CONFIG
+#define __HAL_RCC_GET_SDIO_SOURCE          __HAL_RCC_GET_SDMMC1_SOURCE
+#endif
+
+#if defined(STM32F7)
+#define RCC_SDIOCLKSOURCE_CLK48             RCC_SDMMC1CLKSOURCE_CLK48
+#define RCC_SDIOCLKSOURCE_SYSCLK           RCC_SDMMC1CLKSOURCE_SYSCLK
+#endif
+
+#if defined(STM32H7)
+#define __HAL_RCC_USB_OTG_HS_CLK_ENABLE()              __HAL_RCC_USB1_OTG_HS_CLK_ENABLE()
+#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE()         __HAL_RCC_USB1_OTG_HS_ULPI_CLK_ENABLE()
+#define __HAL_RCC_USB_OTG_HS_CLK_DISABLE()             __HAL_RCC_USB1_OTG_HS_CLK_DISABLE()
+#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE()        __HAL_RCC_USB1_OTG_HS_ULPI_CLK_DISABLE()
+#define __HAL_RCC_USB_OTG_HS_FORCE_RESET()             __HAL_RCC_USB1_OTG_HS_FORCE_RESET()
+#define __HAL_RCC_USB_OTG_HS_RELEASE_RESET()           __HAL_RCC_USB1_OTG_HS_RELEASE_RESET()
+#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE()        __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_ENABLE()
+#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE()   __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_ENABLE()
+#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE()       __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_DISABLE()
+#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE()  __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_DISABLE()
+
+#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE()             __HAL_RCC_USB2_OTG_FS_CLK_ENABLE()
+#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_ENABLE()        __HAL_RCC_USB2_OTG_FS_ULPI_CLK_ENABLE()
+#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE()            __HAL_RCC_USB2_OTG_FS_CLK_DISABLE()
+#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_DISABLE()       __HAL_RCC_USB2_OTG_FS_ULPI_CLK_DISABLE()
+#define __HAL_RCC_USB_OTG_FS_FORCE_RESET()            __HAL_RCC_USB2_OTG_FS_FORCE_RESET()
+#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET()          __HAL_RCC_USB2_OTG_FS_RELEASE_RESET()
+#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE()       __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_ENABLE()
+#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_SLEEP_ENABLE()  __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_ENABLE()
+#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE()      __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_DISABLE()
+#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_SLEEP_DISABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_DISABLE()
+#endif
+
+#define __HAL_RCC_I2SCLK            __HAL_RCC_I2S_CONFIG
+#define __HAL_RCC_I2SCLK_CONFIG     __HAL_RCC_I2S_CONFIG
+
+#define __RCC_PLLSRC                RCC_GET_PLL_OSCSOURCE
+
+#define IS_RCC_MSIRANGE             IS_RCC_MSI_CLOCK_RANGE
+#define IS_RCC_RTCCLK_SOURCE        IS_RCC_RTCCLKSOURCE
+#define IS_RCC_SYSCLK_DIV           IS_RCC_HCLK
+#define IS_RCC_HCLK_DIV             IS_RCC_PCLK
+#define IS_RCC_PERIPHCLK            IS_RCC_PERIPHCLOCK
+
+#define RCC_IT_HSI14                RCC_IT_HSI14RDY
+
+#define RCC_IT_CSSLSE               RCC_IT_LSECSS
+#define RCC_IT_CSSHSE               RCC_IT_CSS
+
+#define RCC_PLLMUL_3                RCC_PLL_MUL3
+#define RCC_PLLMUL_4                RCC_PLL_MUL4
+#define RCC_PLLMUL_6                RCC_PLL_MUL6
+#define RCC_PLLMUL_8                RCC_PLL_MUL8
+#define RCC_PLLMUL_12               RCC_PLL_MUL12
+#define RCC_PLLMUL_16               RCC_PLL_MUL16
+#define RCC_PLLMUL_24               RCC_PLL_MUL24
+#define RCC_PLLMUL_32               RCC_PLL_MUL32
+#define RCC_PLLMUL_48               RCC_PLL_MUL48
+
+#define RCC_PLLDIV_2                RCC_PLL_DIV2
+#define RCC_PLLDIV_3                RCC_PLL_DIV3
+#define RCC_PLLDIV_4                RCC_PLL_DIV4
+
+#define IS_RCC_MCOSOURCE            IS_RCC_MCO1SOURCE
+#define __HAL_RCC_MCO_CONFIG        __HAL_RCC_MCO1_CONFIG
+#define RCC_MCO_NODIV               RCC_MCODIV_1
+#define RCC_MCO_DIV1                RCC_MCODIV_1
+#define RCC_MCO_DIV2                RCC_MCODIV_2
+#define RCC_MCO_DIV4                RCC_MCODIV_4
+#define RCC_MCO_DIV8                RCC_MCODIV_8
+#define RCC_MCO_DIV16               RCC_MCODIV_16
+#define RCC_MCO_DIV32               RCC_MCODIV_32
+#define RCC_MCO_DIV64               RCC_MCODIV_64
+#define RCC_MCO_DIV128              RCC_MCODIV_128
+#define RCC_MCOSOURCE_NONE          RCC_MCO1SOURCE_NOCLOCK
+#define RCC_MCOSOURCE_LSI           RCC_MCO1SOURCE_LSI
+#define RCC_MCOSOURCE_LSE           RCC_MCO1SOURCE_LSE
+#define RCC_MCOSOURCE_SYSCLK        RCC_MCO1SOURCE_SYSCLK
+#define RCC_MCOSOURCE_HSI           RCC_MCO1SOURCE_HSI
+#define RCC_MCOSOURCE_HSI14         RCC_MCO1SOURCE_HSI14
+#define RCC_MCOSOURCE_HSI48         RCC_MCO1SOURCE_HSI48
+#define RCC_MCOSOURCE_HSE           RCC_MCO1SOURCE_HSE
+#define RCC_MCOSOURCE_PLLCLK_DIV1   RCC_MCO1SOURCE_PLLCLK
+#define RCC_MCOSOURCE_PLLCLK_NODIV  RCC_MCO1SOURCE_PLLCLK
+#define RCC_MCOSOURCE_PLLCLK_DIV2   RCC_MCO1SOURCE_PLLCLK_DIV2
+
+#if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || defined(STM32WL)
+#define RCC_RTCCLKSOURCE_NO_CLK     RCC_RTCCLKSOURCE_NONE
+#else
+#define RCC_RTCCLKSOURCE_NONE       RCC_RTCCLKSOURCE_NO_CLK
+#endif
+
+#define RCC_USBCLK_PLLSAI1          RCC_USBCLKSOURCE_PLLSAI1
+#define RCC_USBCLK_PLL              RCC_USBCLKSOURCE_PLL
+#define RCC_USBCLK_MSI              RCC_USBCLKSOURCE_MSI
+#define RCC_USBCLKSOURCE_PLLCLK     RCC_USBCLKSOURCE_PLL
+#define RCC_USBPLLCLK_DIV1          RCC_USBCLKSOURCE_PLL
+#define RCC_USBPLLCLK_DIV1_5        RCC_USBCLKSOURCE_PLL_DIV1_5
+#define RCC_USBPLLCLK_DIV2          RCC_USBCLKSOURCE_PLL_DIV2
+#define RCC_USBPLLCLK_DIV3          RCC_USBCLKSOURCE_PLL_DIV3
+
+#define HSION_BitNumber        RCC_HSION_BIT_NUMBER
+#define HSION_BITNUMBER        RCC_HSION_BIT_NUMBER
+#define HSEON_BitNumber        RCC_HSEON_BIT_NUMBER
+#define HSEON_BITNUMBER        RCC_HSEON_BIT_NUMBER
+#define MSION_BITNUMBER        RCC_MSION_BIT_NUMBER
+#define CSSON_BitNumber        RCC_CSSON_BIT_NUMBER
+#define CSSON_BITNUMBER        RCC_CSSON_BIT_NUMBER
+#define PLLON_BitNumber        RCC_PLLON_BIT_NUMBER
+#define PLLON_BITNUMBER        RCC_PLLON_BIT_NUMBER
+#define PLLI2SON_BitNumber     RCC_PLLI2SON_BIT_NUMBER
+#define I2SSRC_BitNumber       RCC_I2SSRC_BIT_NUMBER
+#define RTCEN_BitNumber        RCC_RTCEN_BIT_NUMBER
+#define RTCEN_BITNUMBER        RCC_RTCEN_BIT_NUMBER
+#define BDRST_BitNumber        RCC_BDRST_BIT_NUMBER
+#define BDRST_BITNUMBER        RCC_BDRST_BIT_NUMBER
+#define RTCRST_BITNUMBER       RCC_RTCRST_BIT_NUMBER
+#define LSION_BitNumber        RCC_LSION_BIT_NUMBER
+#define LSION_BITNUMBER        RCC_LSION_BIT_NUMBER
+#define LSEON_BitNumber        RCC_LSEON_BIT_NUMBER
+#define LSEON_BITNUMBER        RCC_LSEON_BIT_NUMBER
+#define LSEBYP_BITNUMBER       RCC_LSEBYP_BIT_NUMBER
+#define PLLSAION_BitNumber     RCC_PLLSAION_BIT_NUMBER
+#define TIMPRE_BitNumber       RCC_TIMPRE_BIT_NUMBER
+#define RMVF_BitNumber         RCC_RMVF_BIT_NUMBER
+#define RMVF_BITNUMBER         RCC_RMVF_BIT_NUMBER
+#define RCC_CR2_HSI14TRIM_BitNumber RCC_HSI14TRIM_BIT_NUMBER
+#define CR_BYTE2_ADDRESS       RCC_CR_BYTE2_ADDRESS
+#define CIR_BYTE1_ADDRESS      RCC_CIR_BYTE1_ADDRESS
+#define CIR_BYTE2_ADDRESS      RCC_CIR_BYTE2_ADDRESS
+#define BDCR_BYTE0_ADDRESS     RCC_BDCR_BYTE0_ADDRESS
+#define DBP_TIMEOUT_VALUE      RCC_DBP_TIMEOUT_VALUE
+#define LSE_TIMEOUT_VALUE      RCC_LSE_TIMEOUT_VALUE
+
+#define CR_HSION_BB            RCC_CR_HSION_BB
+#define CR_CSSON_BB            RCC_CR_CSSON_BB
+#define CR_PLLON_BB            RCC_CR_PLLON_BB
+#define CR_PLLI2SON_BB         RCC_CR_PLLI2SON_BB
+#define CR_MSION_BB            RCC_CR_MSION_BB
+#define CSR_LSION_BB           RCC_CSR_LSION_BB
+#define CSR_LSEON_BB           RCC_CSR_LSEON_BB
+#define CSR_LSEBYP_BB          RCC_CSR_LSEBYP_BB
+#define CSR_RTCEN_BB           RCC_CSR_RTCEN_BB
+#define CSR_RTCRST_BB          RCC_CSR_RTCRST_BB
+#define CFGR_I2SSRC_BB         RCC_CFGR_I2SSRC_BB
+#define BDCR_RTCEN_BB          RCC_BDCR_RTCEN_BB
+#define BDCR_BDRST_BB          RCC_BDCR_BDRST_BB
+#define CR_HSEON_BB            RCC_CR_HSEON_BB
+#define CSR_RMVF_BB            RCC_CSR_RMVF_BB
+#define CR_PLLSAION_BB         RCC_CR_PLLSAION_BB
+#define DCKCFGR_TIMPRE_BB      RCC_DCKCFGR_TIMPRE_BB
+
+#define __HAL_RCC_CRS_ENABLE_FREQ_ERROR_COUNTER     __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE
+#define __HAL_RCC_CRS_DISABLE_FREQ_ERROR_COUNTER    __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE
+#define __HAL_RCC_CRS_ENABLE_AUTOMATIC_CALIB        __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE
+#define __HAL_RCC_CRS_DISABLE_AUTOMATIC_CALIB       __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE
+#define __HAL_RCC_CRS_CALCULATE_RELOADVALUE         __HAL_RCC_CRS_RELOADVALUE_CALCULATE
+
+#define __HAL_RCC_GET_IT_SOURCE                     __HAL_RCC_GET_IT
+
+#define RCC_CRS_SYNCWARM       RCC_CRS_SYNCWARN
+#define RCC_CRS_TRIMOV         RCC_CRS_TRIMOVF
+
+#define RCC_PERIPHCLK_CK48               RCC_PERIPHCLK_CLK48
+#define RCC_CK48CLKSOURCE_PLLQ           RCC_CLK48CLKSOURCE_PLLQ
+#define RCC_CK48CLKSOURCE_PLLSAIP        RCC_CLK48CLKSOURCE_PLLSAIP
+#define RCC_CK48CLKSOURCE_PLLI2SQ        RCC_CLK48CLKSOURCE_PLLI2SQ
+#define IS_RCC_CK48CLKSOURCE             IS_RCC_CLK48CLKSOURCE
+#define RCC_SDIOCLKSOURCE_CK48           RCC_SDIOCLKSOURCE_CLK48
+
+#define __HAL_RCC_DFSDM_CLK_ENABLE             __HAL_RCC_DFSDM1_CLK_ENABLE
+#define __HAL_RCC_DFSDM_CLK_DISABLE            __HAL_RCC_DFSDM1_CLK_DISABLE
+#define __HAL_RCC_DFSDM_IS_CLK_ENABLED         __HAL_RCC_DFSDM1_IS_CLK_ENABLED
+#define __HAL_RCC_DFSDM_IS_CLK_DISABLED        __HAL_RCC_DFSDM1_IS_CLK_DISABLED
+#define __HAL_RCC_DFSDM_FORCE_RESET            __HAL_RCC_DFSDM1_FORCE_RESET
+#define __HAL_RCC_DFSDM_RELEASE_RESET          __HAL_RCC_DFSDM1_RELEASE_RESET
+#define __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE       __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE
+#define __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE      __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE
+#define __HAL_RCC_DFSDM_IS_CLK_SLEEP_ENABLED   __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED
+#define __HAL_RCC_DFSDM_IS_CLK_SLEEP_DISABLED  __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED
+#define DfsdmClockSelection         Dfsdm1ClockSelection
+#define RCC_PERIPHCLK_DFSDM         RCC_PERIPHCLK_DFSDM1
+#define RCC_DFSDMCLKSOURCE_PCLK     RCC_DFSDM1CLKSOURCE_PCLK2
+#define RCC_DFSDMCLKSOURCE_SYSCLK   RCC_DFSDM1CLKSOURCE_SYSCLK
+#define __HAL_RCC_DFSDM_CONFIG      __HAL_RCC_DFSDM1_CONFIG
+#define __HAL_RCC_GET_DFSDM_SOURCE  __HAL_RCC_GET_DFSDM1_SOURCE
+#define RCC_DFSDM1CLKSOURCE_PCLK    RCC_DFSDM1CLKSOURCE_PCLK2
+#define RCC_SWPMI1CLKSOURCE_PCLK    RCC_SWPMI1CLKSOURCE_PCLK1
+#define RCC_LPTIM1CLKSOURCE_PCLK    RCC_LPTIM1CLKSOURCE_PCLK1
+#define RCC_LPTIM2CLKSOURCE_PCLK    RCC_LPTIM2CLKSOURCE_PCLK1
+
+#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB1    RCC_DFSDM1AUDIOCLKSOURCE_I2S1
+#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB2    RCC_DFSDM1AUDIOCLKSOURCE_I2S2
+#define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB1    RCC_DFSDM2AUDIOCLKSOURCE_I2S1
+#define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB2    RCC_DFSDM2AUDIOCLKSOURCE_I2S2
+#define RCC_DFSDM1CLKSOURCE_APB2            RCC_DFSDM1CLKSOURCE_PCLK2
+#define RCC_DFSDM2CLKSOURCE_APB2            RCC_DFSDM2CLKSOURCE_PCLK2
+#define RCC_FMPI2C1CLKSOURCE_APB            RCC_FMPI2C1CLKSOURCE_PCLK1
+#if defined(STM32U5)
+#define MSIKPLLModeSEL  RCC_MSIKPLL_MODE_SEL
+#define MSISPLLModeSEL  RCC_MSISPLL_MODE_SEL
+#define __HAL_RCC_AHB21_CLK_DISABLE           __HAL_RCC_AHB2_1_CLK_DISABLE
+#define __HAL_RCC_AHB22_CLK_DISABLE           __HAL_RCC_AHB2_2_CLK_DISABLE
+#define __HAL_RCC_AHB1_CLK_Disable_Clear      __HAL_RCC_AHB1_CLK_ENABLE
+#define __HAL_RCC_AHB21_CLK_Disable_Clear     __HAL_RCC_AHB2_1_CLK_ENABLE
+#define __HAL_RCC_AHB22_CLK_Disable_Clear     __HAL_RCC_AHB2_2_CLK_ENABLE
+#define __HAL_RCC_AHB3_CLK_Disable_Clear      __HAL_RCC_AHB3_CLK_ENABLE
+#define __HAL_RCC_APB1_CLK_Disable_Clear      __HAL_RCC_APB1_CLK_ENABLE
+#define __HAL_RCC_APB2_CLK_Disable_Clear      __HAL_RCC_APB2_CLK_ENABLE
+#define __HAL_RCC_APB3_CLK_Disable_Clear      __HAL_RCC_APB3_CLK_ENABLE
+#define IS_RCC_MSIPLLModeSelection            IS_RCC_MSIPLLMODE_SELECT
+#define RCC_PERIPHCLK_CLK48                   RCC_PERIPHCLK_ICLK
+#define RCC_CLK48CLKSOURCE_HSI48              RCC_ICLK_CLKSOURCE_HSI48
+#define RCC_CLK48CLKSOURCE_PLL2               RCC_ICLK_CLKSOURCE_PLL2
+#define RCC_CLK48CLKSOURCE_PLL1               RCC_ICLK_CLKSOURCE_PLL1
+#define RCC_CLK48CLKSOURCE_MSIK               RCC_ICLK_CLKSOURCE_MSIK
+#define __HAL_RCC_ADC1_CLK_ENABLE            __HAL_RCC_ADC12_CLK_ENABLE
+#define __HAL_RCC_ADC1_CLK_DISABLE          __HAL_RCC_ADC12_CLK_DISABLE
+#define __HAL_RCC_ADC1_IS_CLK_ENABLED       __HAL_RCC_ADC12_IS_CLK_ENABLED
+#define __HAL_RCC_ADC1_IS_CLK_DISABLED      __HAL_RCC_ADC12_IS_CLK_DISABLED
+#define __HAL_RCC_ADC1_FORCE_RESET          __HAL_RCC_ADC12_FORCE_RESET
+#define __HAL_RCC_ADC1_RELEASE_RESET        __HAL_RCC_ADC12_RELEASE_RESET
+#define __HAL_RCC_ADC1_CLK_SLEEP_ENABLE     __HAL_RCC_ADC12_CLK_SLEEP_ENABLE
+#define __HAL_RCC_ADC1_CLK_SLEEP_DISABLE    __HAL_RCC_ADC12_CLK_SLEEP_DISABLE
+#endif
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_RNG_Aliased_Macros HAL RNG Aliased Macros maintained for legacy purpose
+  * @{
+  */
+#define  HAL_RNG_ReadyCallback(__HANDLE__)  HAL_RNG_ReadyDataCallback((__HANDLE__), uint32_t random32bit)
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose
+  * @{
+  */
+#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) || defined (STM32U5)
+#else
+#define __HAL_RTC_CLEAR_FLAG                      __HAL_RTC_EXTI_CLEAR_FLAG
+#endif
+#define __HAL_RTC_DISABLE_IT                      __HAL_RTC_EXTI_DISABLE_IT
+#define __HAL_RTC_ENABLE_IT                       __HAL_RTC_EXTI_ENABLE_IT
+
+#if defined (STM32F1)
+#define __HAL_RTC_EXTI_CLEAR_FLAG(RTC_EXTI_LINE_ALARM_EVENT)  __HAL_RTC_ALARM_EXTI_CLEAR_FLAG()
+
+#define __HAL_RTC_EXTI_ENABLE_IT(RTC_EXTI_LINE_ALARM_EVENT)   __HAL_RTC_ALARM_EXTI_ENABLE_IT()
+
+#define __HAL_RTC_EXTI_DISABLE_IT(RTC_EXTI_LINE_ALARM_EVENT)  __HAL_RTC_ALARM_EXTI_DISABLE_IT()
+
+#define __HAL_RTC_EXTI_GET_FLAG(RTC_EXTI_LINE_ALARM_EVENT)    __HAL_RTC_ALARM_EXTI_GET_FLAG()
+
+#define __HAL_RTC_EXTI_GENERATE_SWIT(RTC_EXTI_LINE_ALARM_EVENT)   __HAL_RTC_ALARM_EXTI_GENERATE_SWIT()
+#else
+#define __HAL_RTC_EXTI_CLEAR_FLAG(__EXTI_LINE__)  (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() : \
+                                                   (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() : \
+                                                    __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG()))
+#define __HAL_RTC_EXTI_ENABLE_IT(__EXTI_LINE__)   (((__EXTI_LINE__)  == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_ENABLE_IT() : \
+                                                   (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() : \
+                                                    __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT()))
+#define __HAL_RTC_EXTI_DISABLE_IT(__EXTI_LINE__)  (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_DISABLE_IT() : \
+                                                   (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() : \
+                                                    __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT()))
+#define __HAL_RTC_EXTI_GET_FLAG(__EXTI_LINE__)    (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GET_FLAG() : \
+                                                   (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() : \
+                                                    __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG()))
+#define __HAL_RTC_EXTI_GENERATE_SWIT(__EXTI_LINE__)   (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() : \
+                                                       (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() :  \
+                                                        __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT()))
+#endif   /* STM32F1 */
+
+#define IS_ALARM                                  IS_RTC_ALARM
+#define IS_ALARM_MASK                             IS_RTC_ALARM_MASK
+#define IS_TAMPER                                 IS_RTC_TAMPER
+#define IS_TAMPER_ERASE_MODE                      IS_RTC_TAMPER_ERASE_MODE
+#define IS_TAMPER_FILTER                          IS_RTC_TAMPER_FILTER
+#define IS_TAMPER_INTERRUPT                       IS_RTC_TAMPER_INTERRUPT
+#define IS_TAMPER_MASKFLAG_STATE                  IS_RTC_TAMPER_MASKFLAG_STATE
+#define IS_TAMPER_PRECHARGE_DURATION              IS_RTC_TAMPER_PRECHARGE_DURATION
+#define IS_TAMPER_PULLUP_STATE                    IS_RTC_TAMPER_PULLUP_STATE
+#define IS_TAMPER_SAMPLING_FREQ                   IS_RTC_TAMPER_SAMPLING_FREQ
+#define IS_TAMPER_TIMESTAMPONTAMPER_DETECTION     IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION
+#define IS_TAMPER_TRIGGER                         IS_RTC_TAMPER_TRIGGER
+#define IS_WAKEUP_CLOCK                           IS_RTC_WAKEUP_CLOCK
+#define IS_WAKEUP_COUNTER                         IS_RTC_WAKEUP_COUNTER
+
+#define __RTC_WRITEPROTECTION_ENABLE  __HAL_RTC_WRITEPROTECTION_ENABLE
+#define __RTC_WRITEPROTECTION_DISABLE  __HAL_RTC_WRITEPROTECTION_DISABLE
+
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_SD_Aliased_Macros HAL SD/MMC Aliased Macros maintained for legacy purpose
+  * @{
+  */
+
+#define SD_OCR_CID_CSD_OVERWRIETE   SD_OCR_CID_CSD_OVERWRITE
+#define SD_CMD_SD_APP_STAUS         SD_CMD_SD_APP_STATUS
+
+#if !defined(STM32F1) && !defined(STM32F2) && !defined(STM32F4) && !defined(STM32F7) && !defined(STM32L1)
+#define eMMC_HIGH_VOLTAGE_RANGE     EMMC_HIGH_VOLTAGE_RANGE
+#define eMMC_DUAL_VOLTAGE_RANGE     EMMC_DUAL_VOLTAGE_RANGE
+#define eMMC_LOW_VOLTAGE_RANGE      EMMC_LOW_VOLTAGE_RANGE
+
+#define SDMMC_NSpeed_CLK_DIV        SDMMC_NSPEED_CLK_DIV
+#define SDMMC_HSpeed_CLK_DIV        SDMMC_HSPEED_CLK_DIV
+#endif
+
+#if defined(STM32F4) || defined(STM32F2)
+#define  SD_SDMMC_DISABLED          SD_SDIO_DISABLED
+#define  SD_SDMMC_FUNCTION_BUSY     SD_SDIO_FUNCTION_BUSY
+#define  SD_SDMMC_FUNCTION_FAILED   SD_SDIO_FUNCTION_FAILED
+#define  SD_SDMMC_UNKNOWN_FUNCTION  SD_SDIO_UNKNOWN_FUNCTION
+#define  SD_CMD_SDMMC_SEN_OP_COND   SD_CMD_SDIO_SEN_OP_COND
+#define  SD_CMD_SDMMC_RW_DIRECT     SD_CMD_SDIO_RW_DIRECT
+#define  SD_CMD_SDMMC_RW_EXTENDED   SD_CMD_SDIO_RW_EXTENDED
+#define  __HAL_SD_SDMMC_ENABLE      __HAL_SD_SDIO_ENABLE
+#define  __HAL_SD_SDMMC_DISABLE     __HAL_SD_SDIO_DISABLE
+#define  __HAL_SD_SDMMC_DMA_ENABLE  __HAL_SD_SDIO_DMA_ENABLE
+#define  __HAL_SD_SDMMC_DMA_DISABLE __HAL_SD_SDIO_DMA_DISABL
+#define  __HAL_SD_SDMMC_ENABLE_IT   __HAL_SD_SDIO_ENABLE_IT
+#define  __HAL_SD_SDMMC_DISABLE_IT  __HAL_SD_SDIO_DISABLE_IT
+#define  __HAL_SD_SDMMC_GET_FLAG    __HAL_SD_SDIO_GET_FLAG
+#define  __HAL_SD_SDMMC_CLEAR_FLAG  __HAL_SD_SDIO_CLEAR_FLAG
+#define  __HAL_SD_SDMMC_GET_IT      __HAL_SD_SDIO_GET_IT
+#define  __HAL_SD_SDMMC_CLEAR_IT    __HAL_SD_SDIO_CLEAR_IT
+#define  SDMMC_STATIC_FLAGS         SDIO_STATIC_FLAGS
+#define  SDMMC_CMD0TIMEOUT          SDIO_CMD0TIMEOUT
+#define  SD_SDMMC_SEND_IF_COND      SD_SDIO_SEND_IF_COND
+/* alias CMSIS */
+#define  SDMMC1_IRQn                SDIO_IRQn
+#define  SDMMC1_IRQHandler          SDIO_IRQHandler
+#endif
+
+#if defined(STM32F7) || defined(STM32L4)
+#define  SD_SDIO_DISABLED           SD_SDMMC_DISABLED
+#define  SD_SDIO_FUNCTION_BUSY      SD_SDMMC_FUNCTION_BUSY
+#define  SD_SDIO_FUNCTION_FAILED    SD_SDMMC_FUNCTION_FAILED
+#define  SD_SDIO_UNKNOWN_FUNCTION   SD_SDMMC_UNKNOWN_FUNCTION
+#define  SD_CMD_SDIO_SEN_OP_COND    SD_CMD_SDMMC_SEN_OP_COND
+#define  SD_CMD_SDIO_RW_DIRECT      SD_CMD_SDMMC_RW_DIRECT
+#define  SD_CMD_SDIO_RW_EXTENDED    SD_CMD_SDMMC_RW_EXTENDED
+#define  __HAL_SD_SDIO_ENABLE       __HAL_SD_SDMMC_ENABLE
+#define  __HAL_SD_SDIO_DISABLE      __HAL_SD_SDMMC_DISABLE
+#define  __HAL_SD_SDIO_DMA_ENABLE   __HAL_SD_SDMMC_DMA_ENABLE
+#define  __HAL_SD_SDIO_DMA_DISABL   __HAL_SD_SDMMC_DMA_DISABLE
+#define  __HAL_SD_SDIO_ENABLE_IT    __HAL_SD_SDMMC_ENABLE_IT
+#define  __HAL_SD_SDIO_DISABLE_IT   __HAL_SD_SDMMC_DISABLE_IT
+#define  __HAL_SD_SDIO_GET_FLAG     __HAL_SD_SDMMC_GET_FLAG
+#define  __HAL_SD_SDIO_CLEAR_FLAG   __HAL_SD_SDMMC_CLEAR_FLAG
+#define  __HAL_SD_SDIO_GET_IT       __HAL_SD_SDMMC_GET_IT
+#define  __HAL_SD_SDIO_CLEAR_IT     __HAL_SD_SDMMC_CLEAR_IT
+#define  SDIO_STATIC_FLAGS          SDMMC_STATIC_FLAGS
+#define  SDIO_CMD0TIMEOUT           SDMMC_CMD0TIMEOUT
+#define  SD_SDIO_SEND_IF_COND       SD_SDMMC_SEND_IF_COND
+/* alias CMSIS for compatibilities */
+#define  SDIO_IRQn                  SDMMC1_IRQn
+#define  SDIO_IRQHandler            SDMMC1_IRQHandler
+#endif
+
+#if defined(STM32F7) || defined(STM32F4) || defined(STM32F2) || defined(STM32L4) || defined(STM32H7)
+#define  HAL_SD_CardCIDTypedef       HAL_SD_CardCIDTypeDef
+#define  HAL_SD_CardCSDTypedef       HAL_SD_CardCSDTypeDef
+#define  HAL_SD_CardStatusTypedef    HAL_SD_CardStatusTypeDef
+#define  HAL_SD_CardStateTypedef     HAL_SD_CardStateTypeDef
+#endif
+
+#if defined(STM32H7) || defined(STM32L5)
+#define HAL_MMCEx_Read_DMADoubleBuffer0CpltCallback   HAL_MMCEx_Read_DMADoubleBuf0CpltCallback
+#define HAL_MMCEx_Read_DMADoubleBuffer1CpltCallback   HAL_MMCEx_Read_DMADoubleBuf1CpltCallback
+#define HAL_MMCEx_Write_DMADoubleBuffer0CpltCallback  HAL_MMCEx_Write_DMADoubleBuf0CpltCallback
+#define HAL_MMCEx_Write_DMADoubleBuffer1CpltCallback  HAL_MMCEx_Write_DMADoubleBuf1CpltCallback
+#define HAL_SDEx_Read_DMADoubleBuffer0CpltCallback    HAL_SDEx_Read_DMADoubleBuf0CpltCallback
+#define HAL_SDEx_Read_DMADoubleBuffer1CpltCallback    HAL_SDEx_Read_DMADoubleBuf1CpltCallback
+#define HAL_SDEx_Write_DMADoubleBuffer0CpltCallback   HAL_SDEx_Write_DMADoubleBuf0CpltCallback
+#define HAL_SDEx_Write_DMADoubleBuffer1CpltCallback   HAL_SDEx_Write_DMADoubleBuf1CpltCallback
+#define HAL_SD_DriveTransciver_1_8V_Callback          HAL_SD_DriveTransceiver_1_8V_Callback
+#endif
+/**
+  * @}
+  */
+
+/** @defgroup HAL_SMARTCARD_Aliased_Macros HAL SMARTCARD Aliased Macros maintained for legacy purpose
+  * @{
+  */
+
+#define __SMARTCARD_ENABLE_IT           __HAL_SMARTCARD_ENABLE_IT
+#define __SMARTCARD_DISABLE_IT          __HAL_SMARTCARD_DISABLE_IT
+#define __SMARTCARD_ENABLE              __HAL_SMARTCARD_ENABLE
+#define __SMARTCARD_DISABLE             __HAL_SMARTCARD_DISABLE
+#define __SMARTCARD_DMA_REQUEST_ENABLE  __HAL_SMARTCARD_DMA_REQUEST_ENABLE
+#define __SMARTCARD_DMA_REQUEST_DISABLE __HAL_SMARTCARD_DMA_REQUEST_DISABLE
+
+#define __HAL_SMARTCARD_GETCLOCKSOURCE  SMARTCARD_GETCLOCKSOURCE
+#define __SMARTCARD_GETCLOCKSOURCE      SMARTCARD_GETCLOCKSOURCE
+
+#define IS_SMARTCARD_ONEBIT_SAMPLING    IS_SMARTCARD_ONE_BIT_SAMPLE
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_SMBUS_Aliased_Macros HAL SMBUS Aliased Macros maintained for legacy purpose
+  * @{
+  */
+#define __HAL_SMBUS_RESET_CR1           SMBUS_RESET_CR1
+#define __HAL_SMBUS_RESET_CR2           SMBUS_RESET_CR2
+#define __HAL_SMBUS_GENERATE_START      SMBUS_GENERATE_START
+#define __HAL_SMBUS_GET_ADDR_MATCH      SMBUS_GET_ADDR_MATCH
+#define __HAL_SMBUS_GET_DIR             SMBUS_GET_DIR
+#define __HAL_SMBUS_GET_STOP_MODE       SMBUS_GET_STOP_MODE
+#define __HAL_SMBUS_GET_PEC_MODE        SMBUS_GET_PEC_MODE
+#define __HAL_SMBUS_GET_ALERT_ENABLED   SMBUS_GET_ALERT_ENABLED
+/**
+  * @}
+  */
+
+/** @defgroup HAL_SPI_Aliased_Macros HAL SPI Aliased Macros maintained for legacy purpose
+  * @{
+  */
+
+#define __HAL_SPI_1LINE_TX              SPI_1LINE_TX
+#define __HAL_SPI_1LINE_RX              SPI_1LINE_RX
+#define __HAL_SPI_RESET_CRC             SPI_RESET_CRC
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_UART_Aliased_Macros HAL UART Aliased Macros maintained for legacy purpose
+  * @{
+  */
+
+#define __HAL_UART_GETCLOCKSOURCE       UART_GETCLOCKSOURCE
+#define __HAL_UART_MASK_COMPUTATION     UART_MASK_COMPUTATION
+#define __UART_GETCLOCKSOURCE           UART_GETCLOCKSOURCE
+#define __UART_MASK_COMPUTATION         UART_MASK_COMPUTATION
+
+#define IS_UART_WAKEUPMETHODE           IS_UART_WAKEUPMETHOD
+
+#define IS_UART_ONEBIT_SAMPLE           IS_UART_ONE_BIT_SAMPLE
+#define IS_UART_ONEBIT_SAMPLING         IS_UART_ONE_BIT_SAMPLE
+
+/**
+  * @}
+  */
+
+
+/** @defgroup HAL_USART_Aliased_Macros HAL USART Aliased Macros maintained for legacy purpose
+  * @{
+  */
+
+#define __USART_ENABLE_IT               __HAL_USART_ENABLE_IT
+#define __USART_DISABLE_IT              __HAL_USART_DISABLE_IT
+#define __USART_ENABLE                  __HAL_USART_ENABLE
+#define __USART_DISABLE                 __HAL_USART_DISABLE
+
+#define __HAL_USART_GETCLOCKSOURCE      USART_GETCLOCKSOURCE
+#define __USART_GETCLOCKSOURCE          USART_GETCLOCKSOURCE
+
+#if defined(STM32F0) || defined(STM32F3) || defined(STM32F7)
+#define USART_OVERSAMPLING_16               0x00000000U
+#define USART_OVERSAMPLING_8                USART_CR1_OVER8
+
+#define IS_USART_OVERSAMPLING(__SAMPLING__) (((__SAMPLING__) == USART_OVERSAMPLING_16) || \
+                                             ((__SAMPLING__) == USART_OVERSAMPLING_8))
+#endif /* STM32F0 || STM32F3 || STM32F7 */
+/**
+  * @}
+  */
+
+/** @defgroup HAL_USB_Aliased_Macros HAL USB Aliased Macros maintained for legacy purpose
+  * @{
+  */
+#define USB_EXTI_LINE_WAKEUP                               USB_WAKEUP_EXTI_LINE
+
+#define USB_FS_EXTI_TRIGGER_RISING_EDGE                    USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE
+#define USB_FS_EXTI_TRIGGER_FALLING_EDGE                   USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE
+#define USB_FS_EXTI_TRIGGER_BOTH_EDGE                      USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE
+#define USB_FS_EXTI_LINE_WAKEUP                            USB_OTG_FS_WAKEUP_EXTI_LINE
+
+#define USB_HS_EXTI_TRIGGER_RISING_EDGE                    USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE
+#define USB_HS_EXTI_TRIGGER_FALLING_EDGE                   USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE
+#define USB_HS_EXTI_TRIGGER_BOTH_EDGE                      USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE
+#define USB_HS_EXTI_LINE_WAKEUP                            USB_OTG_HS_WAKEUP_EXTI_LINE
+
+#define __HAL_USB_EXTI_ENABLE_IT                           __HAL_USB_WAKEUP_EXTI_ENABLE_IT
+#define __HAL_USB_EXTI_DISABLE_IT                          __HAL_USB_WAKEUP_EXTI_DISABLE_IT
+#define __HAL_USB_EXTI_GET_FLAG                            __HAL_USB_WAKEUP_EXTI_GET_FLAG
+#define __HAL_USB_EXTI_CLEAR_FLAG                          __HAL_USB_WAKEUP_EXTI_CLEAR_FLAG
+#define __HAL_USB_EXTI_SET_RISING_EDGE_TRIGGER             __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_EDGE
+#define __HAL_USB_EXTI_SET_FALLING_EDGE_TRIGGER            __HAL_USB_WAKEUP_EXTI_ENABLE_FALLING_EDGE
+#define __HAL_USB_EXTI_SET_FALLINGRISING_TRIGGER           __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE
+
+#define __HAL_USB_FS_EXTI_ENABLE_IT                        __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT
+#define __HAL_USB_FS_EXTI_DISABLE_IT                       __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT
+#define __HAL_USB_FS_EXTI_GET_FLAG                         __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG
+#define __HAL_USB_FS_EXTI_CLEAR_FLAG                       __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG
+#define __HAL_USB_FS_EXTI_SET_RISING_EGDE_TRIGGER          __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE
+#define __HAL_USB_FS_EXTI_SET_FALLING_EGDE_TRIGGER         __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_FALLING_EDGE
+#define __HAL_USB_FS_EXTI_SET_FALLINGRISING_TRIGGER        __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE
+#define __HAL_USB_FS_EXTI_GENERATE_SWIT                    __HAL_USB_OTG_FS_WAKEUP_EXTI_GENERATE_SWIT
+
+#define __HAL_USB_HS_EXTI_ENABLE_IT                        __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT
+#define __HAL_USB_HS_EXTI_DISABLE_IT                       __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT
+#define __HAL_USB_HS_EXTI_GET_FLAG                         __HAL_USB_OTG_HS_WAKEUP_EXTI_GET_FLAG
+#define __HAL_USB_HS_EXTI_CLEAR_FLAG                       __HAL_USB_OTG_HS_WAKEUP_EXTI_CLEAR_FLAG
+#define __HAL_USB_HS_EXTI_SET_RISING_EGDE_TRIGGER          __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_EDGE
+#define __HAL_USB_HS_EXTI_SET_FALLING_EGDE_TRIGGER         __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_FALLING_EDGE
+#define __HAL_USB_HS_EXTI_SET_FALLINGRISING_TRIGGER        __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE
+#define __HAL_USB_HS_EXTI_GENERATE_SWIT                    __HAL_USB_OTG_HS_WAKEUP_EXTI_GENERATE_SWIT
+
+#define HAL_PCD_ActiveRemoteWakeup                         HAL_PCD_ActivateRemoteWakeup
+#define HAL_PCD_DeActiveRemoteWakeup                       HAL_PCD_DeActivateRemoteWakeup
+
+#define HAL_PCD_SetTxFiFo                                  HAL_PCDEx_SetTxFiFo
+#define HAL_PCD_SetRxFiFo                                  HAL_PCDEx_SetRxFiFo
+/**
+  * @}
+  */
+
+/** @defgroup HAL_TIM_Aliased_Macros HAL TIM Aliased Macros maintained for legacy purpose
+  * @{
+  */
+#define __HAL_TIM_SetICPrescalerValue   TIM_SET_ICPRESCALERVALUE
+#define __HAL_TIM_ResetICPrescalerValue TIM_RESET_ICPRESCALERVALUE
+
+#define TIM_GET_ITSTATUS                __HAL_TIM_GET_IT_SOURCE
+#define TIM_GET_CLEAR_IT                __HAL_TIM_CLEAR_IT
+
+#define __HAL_TIM_GET_ITSTATUS          __HAL_TIM_GET_IT_SOURCE
+
+#define __HAL_TIM_DIRECTION_STATUS      __HAL_TIM_IS_TIM_COUNTING_DOWN
+#define __HAL_TIM_PRESCALER             __HAL_TIM_SET_PRESCALER
+#define __HAL_TIM_SetCounter            __HAL_TIM_SET_COUNTER
+#define __HAL_TIM_GetCounter            __HAL_TIM_GET_COUNTER
+#define __HAL_TIM_SetAutoreload         __HAL_TIM_SET_AUTORELOAD
+#define __HAL_TIM_GetAutoreload         __HAL_TIM_GET_AUTORELOAD
+#define __HAL_TIM_SetClockDivision      __HAL_TIM_SET_CLOCKDIVISION
+#define __HAL_TIM_GetClockDivision      __HAL_TIM_GET_CLOCKDIVISION
+#define __HAL_TIM_SetICPrescaler        __HAL_TIM_SET_ICPRESCALER
+#define __HAL_TIM_GetICPrescaler        __HAL_TIM_GET_ICPRESCALER
+#define __HAL_TIM_SetCompare            __HAL_TIM_SET_COMPARE
+#define __HAL_TIM_GetCompare            __HAL_TIM_GET_COMPARE
+
+#define TIM_BREAKINPUTSOURCE_DFSDM  TIM_BREAKINPUTSOURCE_DFSDM1
+/**
+  * @}
+  */
+
+/** @defgroup HAL_ETH_Aliased_Macros HAL ETH Aliased Macros maintained for legacy purpose
+  * @{
+  */
+
+#define __HAL_ETH_EXTI_ENABLE_IT                   __HAL_ETH_WAKEUP_EXTI_ENABLE_IT
+#define __HAL_ETH_EXTI_DISABLE_IT                  __HAL_ETH_WAKEUP_EXTI_DISABLE_IT
+#define __HAL_ETH_EXTI_GET_FLAG                    __HAL_ETH_WAKEUP_EXTI_GET_FLAG
+#define __HAL_ETH_EXTI_CLEAR_FLAG                  __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG
+#define __HAL_ETH_EXTI_SET_RISING_EGDE_TRIGGER     __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER
+#define __HAL_ETH_EXTI_SET_FALLING_EGDE_TRIGGER    __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER
+#define __HAL_ETH_EXTI_SET_FALLINGRISING_TRIGGER   __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER
+
+#define ETH_PROMISCIOUSMODE_ENABLE   ETH_PROMISCUOUS_MODE_ENABLE
+#define ETH_PROMISCIOUSMODE_DISABLE  ETH_PROMISCUOUS_MODE_DISABLE
+#define IS_ETH_PROMISCIOUS_MODE      IS_ETH_PROMISCUOUS_MODE
+/**
+  * @}
+  */
+
+/** @defgroup HAL_LTDC_Aliased_Macros HAL LTDC Aliased Macros maintained for legacy purpose
+  * @{
+  */
+#define __HAL_LTDC_LAYER LTDC_LAYER
+#define __HAL_LTDC_RELOAD_CONFIG  __HAL_LTDC_RELOAD_IMMEDIATE_CONFIG
+/**
+  * @}
+  */
+
+/** @defgroup HAL_SAI_Aliased_Macros HAL SAI Aliased Macros maintained for legacy purpose
+  * @{
+  */
+#define SAI_OUTPUTDRIVE_DISABLED          SAI_OUTPUTDRIVE_DISABLE
+#define SAI_OUTPUTDRIVE_ENABLED           SAI_OUTPUTDRIVE_ENABLE
+#define SAI_MASTERDIVIDER_ENABLED         SAI_MASTERDIVIDER_ENABLE
+#define SAI_MASTERDIVIDER_DISABLED        SAI_MASTERDIVIDER_DISABLE
+#define SAI_STREOMODE                     SAI_STEREOMODE
+#define SAI_FIFOStatus_Empty              SAI_FIFOSTATUS_EMPTY
+#define SAI_FIFOStatus_Less1QuarterFull   SAI_FIFOSTATUS_LESS1QUARTERFULL
+#define SAI_FIFOStatus_1QuarterFull       SAI_FIFOSTATUS_1QUARTERFULL
+#define SAI_FIFOStatus_HalfFull           SAI_FIFOSTATUS_HALFFULL
+#define SAI_FIFOStatus_3QuartersFull      SAI_FIFOSTATUS_3QUARTERFULL
+#define SAI_FIFOStatus_Full               SAI_FIFOSTATUS_FULL
+#define IS_SAI_BLOCK_MONO_STREO_MODE      IS_SAI_BLOCK_MONO_STEREO_MODE
+#define SAI_SYNCHRONOUS_EXT               SAI_SYNCHRONOUS_EXT_SAI1
+#define SAI_SYNCEXT_IN_ENABLE             SAI_SYNCEXT_OUTBLOCKA_ENABLE
+/**
+  * @}
+  */
+
+/** @defgroup HAL_SPDIFRX_Aliased_Macros HAL SPDIFRX Aliased Macros maintained for legacy purpose
+  * @{
+  */
+#if defined(STM32H7)
+#define HAL_SPDIFRX_ReceiveControlFlow      HAL_SPDIFRX_ReceiveCtrlFlow
+#define HAL_SPDIFRX_ReceiveControlFlow_IT   HAL_SPDIFRX_ReceiveCtrlFlow_IT
+#define HAL_SPDIFRX_ReceiveControlFlow_DMA  HAL_SPDIFRX_ReceiveCtrlFlow_DMA
+#endif
+/**
+  * @}
+  */
+
+/** @defgroup HAL_HRTIM_Aliased_Functions HAL HRTIM Aliased Functions maintained for legacy purpose
+  * @{
+  */
+#if defined (STM32H7) || defined (STM32G4) || defined (STM32F3)
+#define HAL_HRTIM_WaveformCounterStart_IT      HAL_HRTIM_WaveformCountStart_IT
+#define HAL_HRTIM_WaveformCounterStart_DMA     HAL_HRTIM_WaveformCountStart_DMA
+#define HAL_HRTIM_WaveformCounterStart         HAL_HRTIM_WaveformCountStart
+#define HAL_HRTIM_WaveformCounterStop_IT       HAL_HRTIM_WaveformCountStop_IT
+#define HAL_HRTIM_WaveformCounterStop_DMA      HAL_HRTIM_WaveformCountStop_DMA
+#define HAL_HRTIM_WaveformCounterStop          HAL_HRTIM_WaveformCountStop
+#endif
+/**
+  * @}
+  */
+
+/** @defgroup HAL_QSPI_Aliased_Macros HAL QSPI Aliased Macros maintained for legacy purpose
+  * @{
+  */
+#if defined (STM32L4) || defined (STM32F4) || defined (STM32F7) || defined(STM32H7)
+#define HAL_QPSI_TIMEOUT_DEFAULT_VALUE HAL_QSPI_TIMEOUT_DEFAULT_VALUE
+#endif /* STM32L4 || STM32F4 || STM32F7 */
+/**
+  * @}
+  */
+
+/** @defgroup HAL_PPP_Aliased_Macros HAL PPP Aliased Macros maintained for legacy purpose
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32_HAL_LEGACY */
+
+
diff --git a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h
new file mode 100644
index 0000000..5d8cdd3
--- /dev/null
+++ b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h
@@ -0,0 +1,297 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hal.h
+  * @author  MCD Application Team
+  * @brief   This file contains all the functions prototypes for the HAL 
+  *          module driver.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */ 
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_H
+#define __STM32F4xx_HAL_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_conf.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup HAL
+  * @{
+  */ 
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup HAL_Exported_Constants HAL Exported Constants
+  * @{
+  */
+
+/** @defgroup HAL_TICK_FREQ Tick Frequency
+  * @{
+  */
+typedef enum
+{
+  HAL_TICK_FREQ_10HZ         = 100U,
+  HAL_TICK_FREQ_100HZ        = 10U,
+  HAL_TICK_FREQ_1KHZ         = 1U,
+  HAL_TICK_FREQ_DEFAULT      = HAL_TICK_FREQ_1KHZ
+} HAL_TickFreqTypeDef;
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+   
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup HAL_Exported_Macros HAL Exported Macros
+  * @{
+  */
+
+/** @brief  Freeze/Unfreeze Peripherals in Debug mode 
+  */
+#define __HAL_DBGMCU_FREEZE_TIM2()           (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM2_STOP))
+#define __HAL_DBGMCU_FREEZE_TIM3()           (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM3_STOP))
+#define __HAL_DBGMCU_FREEZE_TIM4()           (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM4_STOP))
+#define __HAL_DBGMCU_FREEZE_TIM5()           (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM5_STOP))
+#define __HAL_DBGMCU_FREEZE_TIM6()           (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM6_STOP))
+#define __HAL_DBGMCU_FREEZE_TIM7()           (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM7_STOP))
+#define __HAL_DBGMCU_FREEZE_TIM12()          (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM12_STOP))
+#define __HAL_DBGMCU_FREEZE_TIM13()          (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM13_STOP))
+#define __HAL_DBGMCU_FREEZE_TIM14()          (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM14_STOP))
+#define __HAL_DBGMCU_FREEZE_RTC()            (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_RTC_STOP))
+#define __HAL_DBGMCU_FREEZE_WWDG()           (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_WWDG_STOP))
+#define __HAL_DBGMCU_FREEZE_IWDG()           (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_IWDG_STOP))
+#define __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT()   (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT))
+#define __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT()   (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT))
+#define __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT()   (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT))
+#define __HAL_DBGMCU_FREEZE_CAN1()           (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_CAN1_STOP))
+#define __HAL_DBGMCU_FREEZE_CAN2()           (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_CAN2_STOP))
+#define __HAL_DBGMCU_FREEZE_TIM1()           (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM1_STOP))
+#define __HAL_DBGMCU_FREEZE_TIM8()           (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM8_STOP))
+#define __HAL_DBGMCU_FREEZE_TIM9()           (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM9_STOP))
+#define __HAL_DBGMCU_FREEZE_TIM10()          (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM10_STOP))
+#define __HAL_DBGMCU_FREEZE_TIM11()          (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM11_STOP))
+
+#define __HAL_DBGMCU_UNFREEZE_TIM2()           (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM2_STOP))
+#define __HAL_DBGMCU_UNFREEZE_TIM3()           (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM3_STOP))
+#define __HAL_DBGMCU_UNFREEZE_TIM4()           (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM4_STOP))
+#define __HAL_DBGMCU_UNFREEZE_TIM5()           (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM5_STOP))
+#define __HAL_DBGMCU_UNFREEZE_TIM6()           (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM6_STOP))
+#define __HAL_DBGMCU_UNFREEZE_TIM7()           (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM7_STOP))
+#define __HAL_DBGMCU_UNFREEZE_TIM12()          (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM12_STOP))
+#define __HAL_DBGMCU_UNFREEZE_TIM13()          (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM13_STOP))
+#define __HAL_DBGMCU_UNFREEZE_TIM14()          (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM14_STOP))
+#define __HAL_DBGMCU_UNFREEZE_RTC()            (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_RTC_STOP))
+#define __HAL_DBGMCU_UNFREEZE_WWDG()           (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_WWDG_STOP))
+#define __HAL_DBGMCU_UNFREEZE_IWDG()           (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_IWDG_STOP))
+#define __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT()   (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT))
+#define __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT()   (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT))
+#define __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT()   (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT))
+#define __HAL_DBGMCU_UNFREEZE_CAN1()           (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_CAN1_STOP))
+#define __HAL_DBGMCU_UNFREEZE_CAN2()           (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_CAN2_STOP))
+#define __HAL_DBGMCU_UNFREEZE_TIM1()           (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM1_STOP))
+#define __HAL_DBGMCU_UNFREEZE_TIM8()           (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM8_STOP))
+#define __HAL_DBGMCU_UNFREEZE_TIM9()           (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM9_STOP))
+#define __HAL_DBGMCU_UNFREEZE_TIM10()          (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM10_STOP))
+#define __HAL_DBGMCU_UNFREEZE_TIM11()          (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM11_STOP))
+
+/** @brief  Main Flash memory mapped at 0x00000000
+  */
+#define __HAL_SYSCFG_REMAPMEMORY_FLASH()             (SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_MEM_MODE))
+
+/** @brief  System Flash memory mapped at 0x00000000
+  */
+#define __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH()       do {SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_MEM_MODE);\
+                                                         SYSCFG->MEMRMP |= SYSCFG_MEMRMP_MEM_MODE_0;\
+                                                        }while(0);
+
+/** @brief  Embedded SRAM mapped at 0x00000000
+  */
+#define __HAL_SYSCFG_REMAPMEMORY_SRAM()       do {SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_MEM_MODE);\
+                                                  SYSCFG->MEMRMP |= (SYSCFG_MEMRMP_MEM_MODE_0 | SYSCFG_MEMRMP_MEM_MODE_1);\
+                                                 }while(0);
+
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx)
+/** @brief  FSMC Bank1 (NOR/PSRAM 1 and 2) mapped at 0x00000000
+  */
+#define __HAL_SYSCFG_REMAPMEMORY_FSMC()       do {SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_MEM_MODE);\
+                                                  SYSCFG->MEMRMP |= (SYSCFG_MEMRMP_MEM_MODE_1);\
+                                                 }while(0);
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) ||\
+    defined(STM32F469xx) || defined(STM32F479xx)
+/** @brief  FMC Bank1 (NOR/PSRAM 1 and 2) mapped at 0x00000000
+  */
+#define __HAL_SYSCFG_REMAPMEMORY_FMC()       do {SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_MEM_MODE);\
+                                                 SYSCFG->MEMRMP |= (SYSCFG_MEMRMP_MEM_MODE_1);\
+                                                }while(0);
+
+/** @brief  FMC/SDRAM Bank 1 and 2 mapped at 0x00000000
+  */
+#define __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM()       do {SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_MEM_MODE);\
+                                                       SYSCFG->MEMRMP |= (SYSCFG_MEMRMP_MEM_MODE_2);\
+                                                      }while(0);
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ 
+
+#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F413xx) || defined(STM32F423xx)
+/** @defgroup Cortex_Lockup_Enable Cortex Lockup Enable
+  * @{
+  */
+/** @brief  SYSCFG Break Lockup lock
+  *         Enables and locks the connection of Cortex-M4 LOCKUP (Hardfault) output to TIM1/8 input
+  * @note   The selected configuration is locked and can be unlocked by system reset
+  */
+#define __HAL_SYSCFG_BREAK_PVD_LOCK()      do {SYSCFG->CFGR2 &= ~(SYSCFG_CFGR2_PVD_LOCK); \
+                                               SYSCFG->CFGR2 |= SYSCFG_CFGR2_PVD_LOCK;    \
+                                              }while(0)
+/**
+ * @}
+ */
+
+/** @defgroup PVD_Lock_Enable PVD Lock
+  * @{
+  */
+/** @brief  SYSCFG Break PVD lock
+  *         Enables and locks the PVD connection with Timer1/8 Break Input, , as well as the PVDE and PLS[2:0] in the PWR_CR register
+  * @note   The selected configuration is locked and can be unlocked by system reset
+  */
+#define __HAL_SYSCFG_BREAK_LOCKUP_LOCK()     do {SYSCFG->CFGR2 &= ~(SYSCFG_CFGR2_LOCKUP_LOCK); \
+                                                 SYSCFG->CFGR2 |= SYSCFG_CFGR2_LOCKUP_LOCK;    \
+                                                }while(0)
+/**
+ * @}
+ */
+#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx || STM32F413xx || STM32F423xx */
+/**
+  * @}
+  */
+
+/** @defgroup HAL_Private_Macros HAL Private Macros
+  * @{
+  */
+#define IS_TICKFREQ(FREQ) (((FREQ) == HAL_TICK_FREQ_10HZ)  || \
+                           ((FREQ) == HAL_TICK_FREQ_100HZ) || \
+                           ((FREQ) == HAL_TICK_FREQ_1KHZ))
+/**
+  * @}
+  */
+
+/* Exported variables --------------------------------------------------------*/
+
+/** @addtogroup HAL_Exported_Variables
+  * @{
+  */
+extern __IO uint32_t uwTick;
+extern uint32_t uwTickPrio;
+extern HAL_TickFreqTypeDef uwTickFreq;
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup HAL_Exported_Functions
+  * @{
+  */
+/** @addtogroup HAL_Exported_Functions_Group1
+  * @{
+  */
+/* Initialization and Configuration functions  ******************************/
+HAL_StatusTypeDef HAL_Init(void);
+HAL_StatusTypeDef HAL_DeInit(void);
+void HAL_MspInit(void);
+void HAL_MspDeInit(void);
+HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority);
+/**
+  * @}
+  */
+
+/** @addtogroup HAL_Exported_Functions_Group2
+  * @{
+  */
+/* Peripheral Control functions  ************************************************/
+void HAL_IncTick(void);
+void HAL_Delay(uint32_t Delay);
+uint32_t HAL_GetTick(void);
+uint32_t HAL_GetTickPrio(void);
+HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq);
+HAL_TickFreqTypeDef HAL_GetTickFreq(void);
+void HAL_SuspendTick(void);
+void HAL_ResumeTick(void);
+uint32_t HAL_GetHalVersion(void);
+uint32_t HAL_GetREVID(void);
+uint32_t HAL_GetDEVID(void);
+void HAL_DBGMCU_EnableDBGSleepMode(void);
+void HAL_DBGMCU_DisableDBGSleepMode(void);
+void HAL_DBGMCU_EnableDBGStopMode(void);
+void HAL_DBGMCU_DisableDBGStopMode(void);
+void HAL_DBGMCU_EnableDBGStandbyMode(void);
+void HAL_DBGMCU_DisableDBGStandbyMode(void);
+void HAL_EnableCompensationCell(void);
+void HAL_DisableCompensationCell(void);
+uint32_t HAL_GetUIDw0(void);
+uint32_t HAL_GetUIDw1(void);
+uint32_t HAL_GetUIDw2(void);
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) ||\
+    defined(STM32F469xx) || defined(STM32F479xx)
+void HAL_EnableMemorySwappingBank(void);
+void HAL_DisableMemorySwappingBank(void);
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ 
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup HAL_Private_Variables HAL Private Variables
+  * @{
+  */
+/**
+  * @}
+  */
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup HAL_Private_Constants HAL Private Constants
+  * @{
+  */
+/**
+  * @}
+  */
+/* Private macros ------------------------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */ 
+  
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_H */
+
+
diff --git a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h
new file mode 100644
index 0000000..935be05
--- /dev/null
+++ b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h
@@ -0,0 +1,407 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hal_cortex.h
+  * @author  MCD Application Team
+  * @brief   Header file of CORTEX HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file in
+  * the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  ******************************************************************************
+  */ 
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_CORTEX_H
+#define __STM32F4xx_HAL_CORTEX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup CORTEX
+  * @{
+  */ 
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup CORTEX_Exported_Types Cortex Exported Types
+  * @{
+  */
+
+#if (__MPU_PRESENT == 1U)
+/** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition
+  * @brief  MPU Region initialization structure 
+  * @{
+  */
+typedef struct
+{
+  uint8_t                Enable;                /*!< Specifies the status of the region. 
+                                                     This parameter can be a value of @ref CORTEX_MPU_Region_Enable                 */
+  uint8_t                Number;                /*!< Specifies the number of the region to protect. 
+                                                     This parameter can be a value of @ref CORTEX_MPU_Region_Number                 */
+  uint32_t               BaseAddress;           /*!< Specifies the base address of the region to protect.                           */
+  uint8_t                Size;                  /*!< Specifies the size of the region to protect. 
+                                                     This parameter can be a value of @ref CORTEX_MPU_Region_Size                   */
+  uint8_t                SubRegionDisable;      /*!< Specifies the number of the subregion protection to disable. 
+                                                     This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF    */         
+  uint8_t                TypeExtField;          /*!< Specifies the TEX field level.
+                                                     This parameter can be a value of @ref CORTEX_MPU_TEX_Levels                    */                 
+  uint8_t                AccessPermission;      /*!< Specifies the region access permission type. 
+                                                     This parameter can be a value of @ref CORTEX_MPU_Region_Permission_Attributes  */
+  uint8_t                DisableExec;           /*!< Specifies the instruction access status. 
+                                                     This parameter can be a value of @ref CORTEX_MPU_Instruction_Access            */
+  uint8_t                IsShareable;           /*!< Specifies the shareability status of the protected region. 
+                                                     This parameter can be a value of @ref CORTEX_MPU_Access_Shareable              */
+  uint8_t                IsCacheable;           /*!< Specifies the cacheable status of the region protected. 
+                                                     This parameter can be a value of @ref CORTEX_MPU_Access_Cacheable              */
+  uint8_t                IsBufferable;          /*!< Specifies the bufferable status of the protected region. 
+                                                     This parameter can be a value of @ref CORTEX_MPU_Access_Bufferable             */
+}MPU_Region_InitTypeDef;
+/**
+  * @}
+  */
+#endif /* __MPU_PRESENT */
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup CORTEX_Exported_Constants CORTEX Exported Constants
+  * @{
+  */
+
+/** @defgroup CORTEX_Preemption_Priority_Group CORTEX Preemption Priority Group
+  * @{
+  */
+#define NVIC_PRIORITYGROUP_0         0x00000007U /*!< 0 bits for pre-emption priority
+                                                      4 bits for subpriority */
+#define NVIC_PRIORITYGROUP_1         0x00000006U /*!< 1 bits for pre-emption priority
+                                                      3 bits for subpriority */
+#define NVIC_PRIORITYGROUP_2         0x00000005U /*!< 2 bits for pre-emption priority
+                                                      2 bits for subpriority */
+#define NVIC_PRIORITYGROUP_3         0x00000004U /*!< 3 bits for pre-emption priority
+                                                      1 bits for subpriority */
+#define NVIC_PRIORITYGROUP_4         0x00000003U /*!< 4 bits for pre-emption priority
+                                                      0 bits for subpriority */
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_SysTick_clock_source CORTEX _SysTick clock source 
+  * @{
+  */
+#define SYSTICK_CLKSOURCE_HCLK_DIV8    0x00000000U
+#define SYSTICK_CLKSOURCE_HCLK         0x00000004U
+
+/**
+  * @}
+  */
+
+#if (__MPU_PRESENT == 1)
+/** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control MPU HFNMI and PRIVILEGED Access control
+  * @{
+  */
+#define  MPU_HFNMI_PRIVDEF_NONE           0x00000000U
+#define  MPU_HARDFAULT_NMI                MPU_CTRL_HFNMIENA_Msk
+#define  MPU_PRIVILEGED_DEFAULT           MPU_CTRL_PRIVDEFENA_Msk
+#define  MPU_HFNMI_PRIVDEF               (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk)
+
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable
+  * @{
+  */
+#define  MPU_REGION_ENABLE     ((uint8_t)0x01)
+#define  MPU_REGION_DISABLE    ((uint8_t)0x00)
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access
+  * @{
+  */
+#define  MPU_INSTRUCTION_ACCESS_ENABLE      ((uint8_t)0x00)
+#define  MPU_INSTRUCTION_ACCESS_DISABLE     ((uint8_t)0x01)
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable
+  * @{
+  */
+#define  MPU_ACCESS_SHAREABLE        ((uint8_t)0x01)
+#define  MPU_ACCESS_NOT_SHAREABLE    ((uint8_t)0x00)
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_MPU_Access_Cacheable CORTEX MPU Instruction Access Cacheable
+  * @{
+  */
+#define  MPU_ACCESS_CACHEABLE         ((uint8_t)0x01)
+#define  MPU_ACCESS_NOT_CACHEABLE     ((uint8_t)0x00)
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_MPU_Access_Bufferable CORTEX MPU Instruction Access Bufferable
+  * @{
+  */
+#define  MPU_ACCESS_BUFFERABLE         ((uint8_t)0x01)
+#define  MPU_ACCESS_NOT_BUFFERABLE     ((uint8_t)0x00)
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_MPU_TEX_Levels MPU TEX Levels
+  * @{
+  */
+#define  MPU_TEX_LEVEL0    ((uint8_t)0x00)
+#define  MPU_TEX_LEVEL1    ((uint8_t)0x01)
+#define  MPU_TEX_LEVEL2    ((uint8_t)0x02)
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_MPU_Region_Size CORTEX MPU Region Size
+  * @{
+  */
+#define   MPU_REGION_SIZE_32B      ((uint8_t)0x04)
+#define   MPU_REGION_SIZE_64B      ((uint8_t)0x05)
+#define   MPU_REGION_SIZE_128B     ((uint8_t)0x06)
+#define   MPU_REGION_SIZE_256B     ((uint8_t)0x07)
+#define   MPU_REGION_SIZE_512B     ((uint8_t)0x08)
+#define   MPU_REGION_SIZE_1KB      ((uint8_t)0x09)
+#define   MPU_REGION_SIZE_2KB      ((uint8_t)0x0A)
+#define   MPU_REGION_SIZE_4KB      ((uint8_t)0x0B)
+#define   MPU_REGION_SIZE_8KB      ((uint8_t)0x0C)
+#define   MPU_REGION_SIZE_16KB     ((uint8_t)0x0D)
+#define   MPU_REGION_SIZE_32KB     ((uint8_t)0x0E)
+#define   MPU_REGION_SIZE_64KB     ((uint8_t)0x0F)
+#define   MPU_REGION_SIZE_128KB    ((uint8_t)0x10)
+#define   MPU_REGION_SIZE_256KB    ((uint8_t)0x11)
+#define   MPU_REGION_SIZE_512KB    ((uint8_t)0x12)
+#define   MPU_REGION_SIZE_1MB      ((uint8_t)0x13)
+#define   MPU_REGION_SIZE_2MB      ((uint8_t)0x14)
+#define   MPU_REGION_SIZE_4MB      ((uint8_t)0x15)
+#define   MPU_REGION_SIZE_8MB      ((uint8_t)0x16)
+#define   MPU_REGION_SIZE_16MB     ((uint8_t)0x17)
+#define   MPU_REGION_SIZE_32MB     ((uint8_t)0x18)
+#define   MPU_REGION_SIZE_64MB     ((uint8_t)0x19)
+#define   MPU_REGION_SIZE_128MB    ((uint8_t)0x1A)
+#define   MPU_REGION_SIZE_256MB    ((uint8_t)0x1B)
+#define   MPU_REGION_SIZE_512MB    ((uint8_t)0x1C)
+#define   MPU_REGION_SIZE_1GB      ((uint8_t)0x1D)
+#define   MPU_REGION_SIZE_2GB      ((uint8_t)0x1E)
+#define   MPU_REGION_SIZE_4GB      ((uint8_t)0x1F)
+/**
+  * @}
+  */
+   
+/** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes 
+  * @{
+  */
+#define  MPU_REGION_NO_ACCESS      ((uint8_t)0x00)
+#define  MPU_REGION_PRIV_RW        ((uint8_t)0x01)
+#define  MPU_REGION_PRIV_RW_URO    ((uint8_t)0x02)
+#define  MPU_REGION_FULL_ACCESS    ((uint8_t)0x03)
+#define  MPU_REGION_PRIV_RO        ((uint8_t)0x05)
+#define  MPU_REGION_PRIV_RO_URO    ((uint8_t)0x06)
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number
+  * @{
+  */
+#define  MPU_REGION_NUMBER0    ((uint8_t)0x00)
+#define  MPU_REGION_NUMBER1    ((uint8_t)0x01)
+#define  MPU_REGION_NUMBER2    ((uint8_t)0x02)
+#define  MPU_REGION_NUMBER3    ((uint8_t)0x03)
+#define  MPU_REGION_NUMBER4    ((uint8_t)0x04)
+#define  MPU_REGION_NUMBER5    ((uint8_t)0x05)
+#define  MPU_REGION_NUMBER6    ((uint8_t)0x06)
+#define  MPU_REGION_NUMBER7    ((uint8_t)0x07)
+/**
+  * @}
+  */
+#endif /* __MPU_PRESENT */
+
+/**
+  * @}
+  */
+
+
+/* Exported Macros -----------------------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup CORTEX_Exported_Functions
+  * @{
+  */
+  
+/** @addtogroup CORTEX_Exported_Functions_Group1
+  * @{
+  */
+/* Initialization and de-initialization functions *****************************/
+void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup);
+void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority);
+void HAL_NVIC_EnableIRQ(IRQn_Type IRQn);
+void HAL_NVIC_DisableIRQ(IRQn_Type IRQn);
+void HAL_NVIC_SystemReset(void);
+uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb);
+/**
+  * @}
+  */
+
+/** @addtogroup CORTEX_Exported_Functions_Group2
+  * @{
+  */
+/* Peripheral Control functions ***********************************************/
+uint32_t HAL_NVIC_GetPriorityGrouping(void);
+void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority);
+uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn);
+void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn);
+void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn);
+uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn);
+void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource);
+void HAL_SYSTICK_IRQHandler(void);
+void HAL_SYSTICK_Callback(void);
+
+#if (__MPU_PRESENT == 1U)
+void HAL_MPU_Enable(uint32_t MPU_Control);
+void HAL_MPU_Disable(void);
+void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init);
+#endif /* __MPU_PRESENT */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup CORTEX_Private_Macros CORTEX Private Macros
+  * @{
+  */
+#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PRIORITYGROUP_0) || \
+                                       ((GROUP) == NVIC_PRIORITYGROUP_1) || \
+                                       ((GROUP) == NVIC_PRIORITYGROUP_2) || \
+                                       ((GROUP) == NVIC_PRIORITYGROUP_3) || \
+                                       ((GROUP) == NVIC_PRIORITYGROUP_4))
+
+#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY)  ((PRIORITY) < 0x10U)
+
+#define IS_NVIC_SUB_PRIORITY(PRIORITY)         ((PRIORITY) < 0x10U)
+
+#define IS_NVIC_DEVICE_IRQ(IRQ)                ((IRQ) >= (IRQn_Type)0x00U)
+
+#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || \
+                                       ((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8))
+
+#if (__MPU_PRESENT == 1U)
+#define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || \
+                                     ((STATE) == MPU_REGION_DISABLE))
+
+#define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \
+                                          ((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE))
+
+#define IS_MPU_ACCESS_SHAREABLE(STATE)   (((STATE) == MPU_ACCESS_SHAREABLE) || \
+                                          ((STATE) == MPU_ACCESS_NOT_SHAREABLE))
+
+#define IS_MPU_ACCESS_CACHEABLE(STATE)   (((STATE) == MPU_ACCESS_CACHEABLE) || \
+                                          ((STATE) == MPU_ACCESS_NOT_CACHEABLE))
+
+#define IS_MPU_ACCESS_BUFFERABLE(STATE)   (((STATE) == MPU_ACCESS_BUFFERABLE) || \
+                                          ((STATE) == MPU_ACCESS_NOT_BUFFERABLE))
+
+#define IS_MPU_TEX_LEVEL(TYPE) (((TYPE) == MPU_TEX_LEVEL0)  || \
+                                ((TYPE) == MPU_TEX_LEVEL1)  || \
+                                ((TYPE) == MPU_TEX_LEVEL2))
+
+#define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_NO_ACCESS)   || \
+                                                  ((TYPE) == MPU_REGION_PRIV_RW)     || \
+                                                  ((TYPE) == MPU_REGION_PRIV_RW_URO) || \
+                                                  ((TYPE) == MPU_REGION_FULL_ACCESS) || \
+                                                  ((TYPE) == MPU_REGION_PRIV_RO)     || \
+                                                  ((TYPE) == MPU_REGION_PRIV_RO_URO))
+
+#define IS_MPU_REGION_NUMBER(NUMBER)    (((NUMBER) == MPU_REGION_NUMBER0) || \
+                                         ((NUMBER) == MPU_REGION_NUMBER1) || \
+                                         ((NUMBER) == MPU_REGION_NUMBER2) || \
+                                         ((NUMBER) == MPU_REGION_NUMBER3) || \
+                                         ((NUMBER) == MPU_REGION_NUMBER4) || \
+                                         ((NUMBER) == MPU_REGION_NUMBER5) || \
+                                         ((NUMBER) == MPU_REGION_NUMBER6) || \
+                                         ((NUMBER) == MPU_REGION_NUMBER7))
+
+#define IS_MPU_REGION_SIZE(SIZE)    (((SIZE) == MPU_REGION_SIZE_32B)   || \
+                                     ((SIZE) == MPU_REGION_SIZE_64B)   || \
+                                     ((SIZE) == MPU_REGION_SIZE_128B)  || \
+                                     ((SIZE) == MPU_REGION_SIZE_256B)  || \
+                                     ((SIZE) == MPU_REGION_SIZE_512B)  || \
+                                     ((SIZE) == MPU_REGION_SIZE_1KB)   || \
+                                     ((SIZE) == MPU_REGION_SIZE_2KB)   || \
+                                     ((SIZE) == MPU_REGION_SIZE_4KB)   || \
+                                     ((SIZE) == MPU_REGION_SIZE_8KB)   || \
+                                     ((SIZE) == MPU_REGION_SIZE_16KB)  || \
+                                     ((SIZE) == MPU_REGION_SIZE_32KB)  || \
+                                     ((SIZE) == MPU_REGION_SIZE_64KB)  || \
+                                     ((SIZE) == MPU_REGION_SIZE_128KB) || \
+                                     ((SIZE) == MPU_REGION_SIZE_256KB) || \
+                                     ((SIZE) == MPU_REGION_SIZE_512KB) || \
+                                     ((SIZE) == MPU_REGION_SIZE_1MB)   || \
+                                     ((SIZE) == MPU_REGION_SIZE_2MB)   || \
+                                     ((SIZE) == MPU_REGION_SIZE_4MB)   || \
+                                     ((SIZE) == MPU_REGION_SIZE_8MB)   || \
+                                     ((SIZE) == MPU_REGION_SIZE_16MB)  || \
+                                     ((SIZE) == MPU_REGION_SIZE_32MB)  || \
+                                     ((SIZE) == MPU_REGION_SIZE_64MB)  || \
+                                     ((SIZE) == MPU_REGION_SIZE_128MB) || \
+                                     ((SIZE) == MPU_REGION_SIZE_256MB) || \
+                                     ((SIZE) == MPU_REGION_SIZE_512MB) || \
+                                     ((SIZE) == MPU_REGION_SIZE_1GB)   || \
+                                     ((SIZE) == MPU_REGION_SIZE_2GB)   || \
+                                     ((SIZE) == MPU_REGION_SIZE_4GB))
+
+#define IS_MPU_SUB_REGION_DISABLE(SUBREGION)  ((SUBREGION) < (uint16_t)0x00FF)
+#endif /* __MPU_PRESENT */
+
+/**                                                                          
+  * @}                                                                  
+  */
+
+/* Private functions ---------------------------------------------------------*/
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */
+  
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_CORTEX_H */
+ 
+
diff --git a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_crc.h b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_crc.h
new file mode 100644
index 0000000..2361582
--- /dev/null
+++ b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_crc.h
@@ -0,0 +1,181 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hal_crc.h
+  * @author  MCD Application Team
+  * @brief   Header file of CRC HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2016 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32F4xx_HAL_CRC_H
+#define STM32F4xx_HAL_CRC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup CRC
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup CRC_Exported_Types CRC Exported Types
+  * @{
+  */
+
+/**
+  * @brief  CRC HAL State Structure definition
+  */
+typedef enum
+{
+  HAL_CRC_STATE_RESET     = 0x00U,  /*!< CRC not yet initialized or disabled */
+  HAL_CRC_STATE_READY     = 0x01U,  /*!< CRC initialized and ready for use   */
+  HAL_CRC_STATE_BUSY      = 0x02U,  /*!< CRC internal process is ongoing     */
+  HAL_CRC_STATE_TIMEOUT   = 0x03U,  /*!< CRC timeout state                   */
+  HAL_CRC_STATE_ERROR     = 0x04U   /*!< CRC error state                     */
+} HAL_CRC_StateTypeDef;
+
+
+/**
+  * @brief  CRC Handle Structure definition
+  */
+typedef struct
+{
+  CRC_TypeDef                 *Instance;   /*!< Register base address        */
+
+  HAL_LockTypeDef             Lock;        /*!< CRC Locking object           */
+
+  __IO HAL_CRC_StateTypeDef   State;       /*!< CRC communication state      */
+
+} CRC_HandleTypeDef;
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup CRC_Exported_Constants CRC Exported Constants
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup CRC_Exported_Macros CRC Exported Macros
+  * @{
+  */
+
+/** @brief Reset CRC handle state.
+  * @param  __HANDLE__ CRC handle.
+  * @retval None
+  */
+#define __HAL_CRC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CRC_STATE_RESET)
+
+/**
+  * @brief  Reset CRC Data Register.
+  * @param  __HANDLE__ CRC handle
+  * @retval None
+  */
+#define __HAL_CRC_DR_RESET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRC_CR_RESET)
+
+/**
+  * @brief Store data in the Independent Data (ID) register.
+  * @param __HANDLE__ CRC handle
+  * @param __VALUE__  Value to be stored in the ID register
+  * @note  Refer to the Reference Manual to get the authorized __VALUE__ length in bits
+  * @retval None
+  */
+#define __HAL_CRC_SET_IDR(__HANDLE__, __VALUE__) (WRITE_REG((__HANDLE__)->Instance->IDR, (__VALUE__)))
+
+/**
+  * @brief Return the data stored in the Independent Data (ID) register.
+  * @param __HANDLE__ CRC handle
+  * @note  Refer to the Reference Manual to get the authorized __VALUE__ length in bits
+  * @retval Value of the ID register
+  */
+#define __HAL_CRC_GET_IDR(__HANDLE__) (((__HANDLE__)->Instance->IDR) & CRC_IDR_IDR)
+/**
+  * @}
+  */
+
+
+/* Private macros --------------------------------------------------------*/
+/** @defgroup  CRC_Private_Macros CRC Private Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup CRC_Exported_Functions CRC Exported Functions
+  * @{
+  */
+
+/* Initialization and de-initialization functions  ****************************/
+/** @defgroup CRC_Exported_Functions_Group1 Initialization and de-initialization functions
+  * @{
+  */
+HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc);
+HAL_StatusTypeDef HAL_CRC_DeInit(CRC_HandleTypeDef *hcrc);
+void HAL_CRC_MspInit(CRC_HandleTypeDef *hcrc);
+void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc);
+/**
+  * @}
+  */
+
+/* Peripheral Control functions ***********************************************/
+/** @defgroup CRC_Exported_Functions_Group2 Peripheral Control functions
+  * @{
+  */
+uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength);
+uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength);
+/**
+  * @}
+  */
+
+/* Peripheral State and Error functions ***************************************/
+/** @defgroup CRC_Exported_Functions_Group3 Peripheral State functions
+  * @{
+  */
+HAL_CRC_StateTypeDef HAL_CRC_GetState(CRC_HandleTypeDef *hcrc);
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32F4xx_HAL_CRC_H */
diff --git a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h
new file mode 100644
index 0000000..094b411
--- /dev/null
+++ b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h
@@ -0,0 +1,210 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hal_def.h
+  * @author  MCD Application Team
+  * @brief   This file contains HAL common defines, enumeration, macros and 
+  *          structures definitions. 
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_DEF
+#define __STM32F4xx_HAL_DEF
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx.h"
+#include "Legacy/stm32_hal_legacy.h"
+#include <stddef.h>
+
+/* Exported types ------------------------------------------------------------*/
+
+/** 
+  * @brief  HAL Status structures definition  
+  */  
+typedef enum 
+{
+  HAL_OK       = 0x00U,
+  HAL_ERROR    = 0x01U,
+  HAL_BUSY     = 0x02U,
+  HAL_TIMEOUT  = 0x03U
+} HAL_StatusTypeDef;
+
+/** 
+  * @brief  HAL Lock structures definition  
+  */
+typedef enum 
+{
+  HAL_UNLOCKED = 0x00U,
+  HAL_LOCKED   = 0x01U  
+} HAL_LockTypeDef;
+
+/* Exported macro ------------------------------------------------------------*/
+
+#define UNUSED(X) (void)X      /* To avoid gcc/g++ warnings */
+
+#define HAL_MAX_DELAY      0xFFFFFFFFU
+
+#define HAL_IS_BIT_SET(REG, BIT)         (((REG) & (BIT)) == (BIT))
+#define HAL_IS_BIT_CLR(REG, BIT)         (((REG) & (BIT)) == 0U)
+
+#define __HAL_LINKDMA(__HANDLE__, __PPP_DMA_FIELD__, __DMA_HANDLE__)               \
+                        do{                                                      \
+                              (__HANDLE__)->__PPP_DMA_FIELD__ = &(__DMA_HANDLE__); \
+                              (__DMA_HANDLE__).Parent = (__HANDLE__);             \
+                          } while(0U)
+
+/** @brief Reset the Handle's State field.
+  * @param __HANDLE__ specifies the Peripheral Handle.
+  * @note  This macro can be used for the following purpose: 
+  *          - When the Handle is declared as local variable; before passing it as parameter
+  *            to HAL_PPP_Init() for the first time, it is mandatory to use this macro 
+  *            to set to 0 the Handle's "State" field.
+  *            Otherwise, "State" field may have any random value and the first time the function 
+  *            HAL_PPP_Init() is called, the low level hardware initialization will be missed
+  *            (i.e. HAL_PPP_MspInit() will not be executed).
+  *          - When there is a need to reconfigure the low level hardware: instead of calling
+  *            HAL_PPP_DeInit() then HAL_PPP_Init(), user can make a call to this macro then HAL_PPP_Init().
+  *            In this later function, when the Handle's "State" field is set to 0, it will execute the function
+  *            HAL_PPP_MspInit() which will reconfigure the low level hardware.
+  * @retval None
+  */
+#define __HAL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = 0U)
+
+#if (USE_RTOS == 1U)
+  /* Reserved for future use */
+  #error "USE_RTOS should be 0 in the current HAL release"
+#else
+  #define __HAL_LOCK(__HANDLE__)                                           \
+                                do{                                        \
+                                    if((__HANDLE__)->Lock == HAL_LOCKED)   \
+                                    {                                      \
+                                       return HAL_BUSY;                    \
+                                    }                                      \
+                                    else                                   \
+                                    {                                      \
+                                       (__HANDLE__)->Lock = HAL_LOCKED;    \
+                                    }                                      \
+                                  }while (0U)
+
+  #define __HAL_UNLOCK(__HANDLE__)                                          \
+                                  do{                                       \
+                                      (__HANDLE__)->Lock = HAL_UNLOCKED;    \
+                                    }while (0U)
+#endif /* USE_RTOS */
+
+#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) /* ARM Compiler V6 */
+  #ifndef __weak
+    #define __weak  __attribute__((weak))
+  #endif
+  #ifndef __packed
+    #define __packed  __attribute__((packed))
+  #endif
+#elif defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */
+  #ifndef __weak
+    #define __weak   __attribute__((weak))
+  #endif /* __weak */
+  #ifndef __packed
+    #define __packed __attribute__((__packed__))
+  #endif /* __packed */
+#endif /* __GNUC__ */
+
+
+/* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive "#pragma data_alignment=4" must be used instead */
+#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) /* ARM Compiler V6 */
+  #ifndef __ALIGN_BEGIN
+    #define __ALIGN_BEGIN
+  #endif
+  #ifndef __ALIGN_END
+    #define __ALIGN_END      __attribute__ ((aligned (4)))
+  #endif
+#elif defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */
+  #ifndef __ALIGN_END
+#define __ALIGN_END    __attribute__ ((aligned (4)))
+  #endif /* __ALIGN_END */
+  #ifndef __ALIGN_BEGIN  
+    #define __ALIGN_BEGIN
+  #endif /* __ALIGN_BEGIN */
+#else
+  #ifndef __ALIGN_END
+    #define __ALIGN_END
+  #endif /* __ALIGN_END */
+  #ifndef __ALIGN_BEGIN      
+    #if defined   (__CC_ARM)      /* ARM Compiler V5*/
+#define __ALIGN_BEGIN    __align(4)
+    #elif defined (__ICCARM__)    /* IAR Compiler */
+      #define __ALIGN_BEGIN 
+    #endif /* __CC_ARM */
+  #endif /* __ALIGN_BEGIN */
+#endif /* __GNUC__ */
+
+
+/** 
+  * @brief  __RAM_FUNC definition
+  */ 
+#if defined ( __CC_ARM   ) || (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
+/* ARM Compiler V4/V5 and V6
+   --------------------------
+   RAM functions are defined using the toolchain options. 
+   Functions that are executed in RAM should reside in a separate source module.
+   Using the 'Options for File' dialog you can simply change the 'Code / Const' 
+   area of a module to a memory space in physical RAM.
+   Available memory areas are declared in the 'Target' tab of the 'Options for Target'
+   dialog. 
+*/
+#define __RAM_FUNC
+
+#elif defined ( __ICCARM__ )
+/* ICCARM Compiler
+   ---------------
+   RAM functions are defined using a specific toolchain keyword "__ramfunc". 
+*/
+#define __RAM_FUNC __ramfunc
+
+#elif defined   (  __GNUC__  )
+/* GNU Compiler
+   ------------
+  RAM functions are defined using a specific toolchain attribute 
+   "__attribute__((section(".RamFunc")))".
+*/
+#define __RAM_FUNC __attribute__((section(".RamFunc")))
+
+#endif
+
+/** 
+  * @brief  __NOINLINE definition
+  */ 
+#if defined ( __CC_ARM   ) || (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) || defined   (  __GNUC__  )
+/* ARM V4/V5 and V6 & GNU Compiler
+   -------------------------------
+*/
+#define __NOINLINE __attribute__ ( (noinline) )
+
+#elif defined ( __ICCARM__ )
+/* ICCARM Compiler
+   ---------------
+*/
+#define __NOINLINE _Pragma("optimize = no_inline")
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* ___STM32F4xx_HAL_DEF */
+
+
diff --git a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h
new file mode 100644
index 0000000..336b2bb
--- /dev/null
+++ b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h
@@ -0,0 +1,802 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hal_dma.h
+  * @author  MCD Application Team
+  * @brief   Header file of DMA HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file in
+  * the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */ 
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_DMA_H
+#define __STM32F4xx_HAL_DMA_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup DMA
+  * @{
+  */ 
+
+/* Exported types ------------------------------------------------------------*/
+
+/** @defgroup DMA_Exported_Types DMA Exported Types
+  * @brief    DMA Exported Types 
+  * @{
+  */
+   
+/** 
+  * @brief  DMA Configuration Structure definition
+  */
+typedef struct
+{
+  uint32_t Channel;              /*!< Specifies the channel used for the specified stream. 
+                                      This parameter can be a value of @ref DMA_Channel_selection                    */
+
+  uint32_t Direction;            /*!< Specifies if the data will be transferred from memory to peripheral, 
+                                      from memory to memory or from peripheral to memory.
+                                      This parameter can be a value of @ref DMA_Data_transfer_direction              */
+
+  uint32_t PeriphInc;            /*!< Specifies whether the Peripheral address register should be incremented or not.
+                                      This parameter can be a value of @ref DMA_Peripheral_incremented_mode          */
+
+  uint32_t MemInc;               /*!< Specifies whether the memory address register should be incremented or not.
+                                      This parameter can be a value of @ref DMA_Memory_incremented_mode              */
+
+  uint32_t PeriphDataAlignment;  /*!< Specifies the Peripheral data width.
+                                      This parameter can be a value of @ref DMA_Peripheral_data_size                 */
+
+  uint32_t MemDataAlignment;     /*!< Specifies the Memory data width.
+                                      This parameter can be a value of @ref DMA_Memory_data_size                     */
+
+  uint32_t Mode;                 /*!< Specifies the operation mode of the DMAy Streamx.
+                                      This parameter can be a value of @ref DMA_mode
+                                      @note The circular buffer mode cannot be used if the memory-to-memory
+                                            data transfer is configured on the selected Stream                        */
+
+  uint32_t Priority;             /*!< Specifies the software priority for the DMAy Streamx.
+                                      This parameter can be a value of @ref DMA_Priority_level                       */
+
+  uint32_t FIFOMode;             /*!< Specifies if the FIFO mode or Direct mode will be used for the specified stream.
+                                      This parameter can be a value of @ref DMA_FIFO_direct_mode
+                                      @note The Direct mode (FIFO mode disabled) cannot be used if the 
+                                            memory-to-memory data transfer is configured on the selected stream       */
+
+  uint32_t FIFOThreshold;        /*!< Specifies the FIFO threshold level.
+                                      This parameter can be a value of @ref DMA_FIFO_threshold_level                  */
+
+  uint32_t MemBurst;             /*!< Specifies the Burst transfer configuration for the memory transfers. 
+                                      It specifies the amount of data to be transferred in a single non interruptible
+                                      transaction.
+                                      This parameter can be a value of @ref DMA_Memory_burst 
+                                      @note The burst mode is possible only if the address Increment mode is enabled. */
+
+  uint32_t PeriphBurst;          /*!< Specifies the Burst transfer configuration for the peripheral transfers. 
+                                      It specifies the amount of data to be transferred in a single non interruptible 
+                                      transaction. 
+                                      This parameter can be a value of @ref DMA_Peripheral_burst
+                                      @note The burst mode is possible only if the address Increment mode is enabled. */
+}DMA_InitTypeDef;
+
+
+/** 
+  * @brief  HAL DMA State structures definition
+  */
+typedef enum
+{
+  HAL_DMA_STATE_RESET             = 0x00U,  /*!< DMA not yet initialized or disabled */
+  HAL_DMA_STATE_READY             = 0x01U,  /*!< DMA initialized and ready for use   */
+  HAL_DMA_STATE_BUSY              = 0x02U,  /*!< DMA process is ongoing              */
+  HAL_DMA_STATE_TIMEOUT           = 0x03U,  /*!< DMA timeout state                   */
+  HAL_DMA_STATE_ERROR             = 0x04U,  /*!< DMA error state                     */
+  HAL_DMA_STATE_ABORT             = 0x05U,  /*!< DMA Abort state                     */
+}HAL_DMA_StateTypeDef;
+
+/** 
+  * @brief  HAL DMA Error Code structure definition
+  */
+typedef enum
+{
+  HAL_DMA_FULL_TRANSFER           = 0x00U,  /*!< Full transfer     */
+  HAL_DMA_HALF_TRANSFER           = 0x01U   /*!< Half Transfer     */
+}HAL_DMA_LevelCompleteTypeDef;
+
+/** 
+  * @brief  HAL DMA Error Code structure definition
+  */
+typedef enum
+{
+  HAL_DMA_XFER_CPLT_CB_ID         = 0x00U,  /*!< Full transfer     */
+  HAL_DMA_XFER_HALFCPLT_CB_ID     = 0x01U,  /*!< Half Transfer     */
+  HAL_DMA_XFER_M1CPLT_CB_ID       = 0x02U,  /*!< M1 Full Transfer  */
+  HAL_DMA_XFER_M1HALFCPLT_CB_ID   = 0x03U,  /*!< M1 Half Transfer  */
+  HAL_DMA_XFER_ERROR_CB_ID        = 0x04U,  /*!< Error             */
+  HAL_DMA_XFER_ABORT_CB_ID        = 0x05U,  /*!< Abort             */
+  HAL_DMA_XFER_ALL_CB_ID          = 0x06U   /*!< All               */
+}HAL_DMA_CallbackIDTypeDef;
+
+/** 
+  * @brief  DMA handle Structure definition
+  */
+typedef struct __DMA_HandleTypeDef
+{
+  DMA_Stream_TypeDef         *Instance;                                                        /*!< Register base address                  */
+
+  DMA_InitTypeDef            Init;                                                             /*!< DMA communication parameters           */ 
+
+  HAL_LockTypeDef            Lock;                                                             /*!< DMA locking object                     */  
+
+  __IO HAL_DMA_StateTypeDef  State;                                                            /*!< DMA transfer state                     */
+
+  void                       *Parent;                                                          /*!< Parent object state                    */ 
+
+  void                       (* XferCpltCallback)( struct __DMA_HandleTypeDef * hdma);         /*!< DMA transfer complete callback         */
+
+  void                       (* XferHalfCpltCallback)( struct __DMA_HandleTypeDef * hdma);     /*!< DMA Half transfer complete callback    */
+
+  void                       (* XferM1CpltCallback)( struct __DMA_HandleTypeDef * hdma);       /*!< DMA transfer complete Memory1 callback */
+  
+  void                       (* XferM1HalfCpltCallback)( struct __DMA_HandleTypeDef * hdma);   /*!< DMA transfer Half complete Memory1 callback */
+  
+  void                       (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma);        /*!< DMA transfer error callback            */
+  
+  void                       (* XferAbortCallback)( struct __DMA_HandleTypeDef * hdma);        /*!< DMA transfer Abort callback            */  
+
+  __IO uint32_t              ErrorCode;                                                        /*!< DMA Error code                          */
+  
+  uint32_t                   StreamBaseAddress;                                                /*!< DMA Stream Base Address                */
+
+  uint32_t                   StreamIndex;                                                      /*!< DMA Stream Index                       */
+ 
+}DMA_HandleTypeDef;
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup DMA_Exported_Constants DMA Exported Constants
+  * @brief    DMA Exported constants 
+  * @{
+  */
+
+/** @defgroup DMA_Error_Code DMA Error Code
+  * @brief    DMA Error Code 
+  * @{
+  */ 
+#define HAL_DMA_ERROR_NONE            0x00000000U    /*!< No error                               */
+#define HAL_DMA_ERROR_TE              0x00000001U    /*!< Transfer error                         */
+#define HAL_DMA_ERROR_FE              0x00000002U    /*!< FIFO error                             */
+#define HAL_DMA_ERROR_DME             0x00000004U    /*!< Direct Mode error                      */
+#define HAL_DMA_ERROR_TIMEOUT         0x00000020U    /*!< Timeout error                          */
+#define HAL_DMA_ERROR_PARAM           0x00000040U    /*!< Parameter error                        */
+#define HAL_DMA_ERROR_NO_XFER         0x00000080U    /*!< Abort requested with no Xfer ongoing   */
+#define HAL_DMA_ERROR_NOT_SUPPORTED   0x00000100U    /*!< Not supported mode                     */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_Channel_selection DMA Channel selection
+  * @brief    DMA channel selection 
+  * @{
+  */ 
+#define DMA_CHANNEL_0                 0x00000000U    /*!< DMA Channel 0 */
+#define DMA_CHANNEL_1                 0x02000000U    /*!< DMA Channel 1 */
+#define DMA_CHANNEL_2                 0x04000000U    /*!< DMA Channel 2 */
+#define DMA_CHANNEL_3                 0x06000000U    /*!< DMA Channel 3 */
+#define DMA_CHANNEL_4                 0x08000000U    /*!< DMA Channel 4 */
+#define DMA_CHANNEL_5                 0x0A000000U    /*!< DMA Channel 5 */
+#define DMA_CHANNEL_6                 0x0C000000U    /*!< DMA Channel 6 */
+#define DMA_CHANNEL_7                 0x0E000000U    /*!< DMA Channel 7 */
+#if defined (DMA_SxCR_CHSEL_3)
+#define DMA_CHANNEL_8                 0x10000000U    /*!< DMA Channel 8 */
+#define DMA_CHANNEL_9                 0x12000000U    /*!< DMA Channel 9 */
+#define DMA_CHANNEL_10                0x14000000U    /*!< DMA Channel 10 */
+#define DMA_CHANNEL_11                0x16000000U    /*!< DMA Channel 11 */
+#define DMA_CHANNEL_12                0x18000000U    /*!< DMA Channel 12 */
+#define DMA_CHANNEL_13                0x1A000000U    /*!< DMA Channel 13 */
+#define DMA_CHANNEL_14                0x1C000000U    /*!< DMA Channel 14 */
+#define DMA_CHANNEL_15                0x1E000000U    /*!< DMA Channel 15 */
+#endif /* DMA_SxCR_CHSEL_3 */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_Data_transfer_direction DMA Data transfer direction
+  * @brief    DMA data transfer direction 
+  * @{
+  */ 
+#define DMA_PERIPH_TO_MEMORY          0x00000000U                 /*!< Peripheral to memory direction */
+#define DMA_MEMORY_TO_PERIPH          ((uint32_t)DMA_SxCR_DIR_0)  /*!< Memory to peripheral direction */
+#define DMA_MEMORY_TO_MEMORY          ((uint32_t)DMA_SxCR_DIR_1)  /*!< Memory to memory direction     */
+/**
+  * @}
+  */
+        
+/** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode
+  * @brief    DMA peripheral incremented mode 
+  * @{
+  */ 
+#define DMA_PINC_ENABLE               ((uint32_t)DMA_SxCR_PINC)   /*!< Peripheral increment mode enable  */
+#define DMA_PINC_DISABLE              0x00000000U                 /*!< Peripheral increment mode disable */
+/**
+  * @}
+  */ 
+
+/** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode
+  * @brief    DMA memory incremented mode 
+  * @{
+  */ 
+#define DMA_MINC_ENABLE               ((uint32_t)DMA_SxCR_MINC)   /*!< Memory increment mode enable  */
+#define DMA_MINC_DISABLE              0x00000000U                 /*!< Memory increment mode disable */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_Peripheral_data_size DMA Peripheral data size
+  * @brief    DMA peripheral data size 
+  * @{
+  */ 
+#define DMA_PDATAALIGN_BYTE           0x00000000U                  /*!< Peripheral data alignment: Byte     */
+#define DMA_PDATAALIGN_HALFWORD       ((uint32_t)DMA_SxCR_PSIZE_0) /*!< Peripheral data alignment: HalfWord */
+#define DMA_PDATAALIGN_WORD           ((uint32_t)DMA_SxCR_PSIZE_1) /*!< Peripheral data alignment: Word     */
+/**
+  * @}
+  */ 
+
+/** @defgroup DMA_Memory_data_size DMA Memory data size
+  * @brief    DMA memory data size 
+  * @{ 
+  */
+#define DMA_MDATAALIGN_BYTE           0x00000000U                  /*!< Memory data alignment: Byte     */
+#define DMA_MDATAALIGN_HALFWORD       ((uint32_t)DMA_SxCR_MSIZE_0) /*!< Memory data alignment: HalfWord */
+#define DMA_MDATAALIGN_WORD           ((uint32_t)DMA_SxCR_MSIZE_1) /*!< Memory data alignment: Word     */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_mode DMA mode
+  * @brief    DMA mode 
+  * @{
+  */ 
+#define DMA_NORMAL                    0x00000000U                  /*!< Normal mode                  */
+#define DMA_CIRCULAR                  ((uint32_t)DMA_SxCR_CIRC)    /*!< Circular mode                */
+#define DMA_PFCTRL                    ((uint32_t)DMA_SxCR_PFCTRL)  /*!< Peripheral flow control mode */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_Priority_level DMA Priority level
+  * @brief    DMA priority levels 
+  * @{
+  */
+#define DMA_PRIORITY_LOW              0x00000000U                 /*!< Priority level: Low       */
+#define DMA_PRIORITY_MEDIUM           ((uint32_t)DMA_SxCR_PL_0)   /*!< Priority level: Medium    */
+#define DMA_PRIORITY_HIGH             ((uint32_t)DMA_SxCR_PL_1)   /*!< Priority level: High      */
+#define DMA_PRIORITY_VERY_HIGH        ((uint32_t)DMA_SxCR_PL)     /*!< Priority level: Very High */
+/**
+  * @}
+  */ 
+
+/** @defgroup DMA_FIFO_direct_mode DMA FIFO direct mode
+  * @brief    DMA FIFO direct mode
+  * @{
+  */
+#define DMA_FIFOMODE_DISABLE          0x00000000U                 /*!< FIFO mode disable */
+#define DMA_FIFOMODE_ENABLE           ((uint32_t)DMA_SxFCR_DMDIS) /*!< FIFO mode enable  */
+/**
+  * @}
+  */ 
+
+/** @defgroup DMA_FIFO_threshold_level DMA FIFO threshold level
+  * @brief    DMA FIFO level 
+  * @{
+  */
+#define DMA_FIFO_THRESHOLD_1QUARTERFULL       0x00000000U                  /*!< FIFO threshold 1 quart full configuration  */
+#define DMA_FIFO_THRESHOLD_HALFFULL           ((uint32_t)DMA_SxFCR_FTH_0)  /*!< FIFO threshold half full configuration     */
+#define DMA_FIFO_THRESHOLD_3QUARTERSFULL      ((uint32_t)DMA_SxFCR_FTH_1)  /*!< FIFO threshold 3 quarts full configuration */
+#define DMA_FIFO_THRESHOLD_FULL               ((uint32_t)DMA_SxFCR_FTH)    /*!< FIFO threshold full configuration          */
+/**
+  * @}
+  */ 
+
+/** @defgroup DMA_Memory_burst DMA Memory burst
+  * @brief    DMA memory burst 
+  * @{
+  */ 
+#define DMA_MBURST_SINGLE             0x00000000U
+#define DMA_MBURST_INC4               ((uint32_t)DMA_SxCR_MBURST_0)  
+#define DMA_MBURST_INC8               ((uint32_t)DMA_SxCR_MBURST_1)  
+#define DMA_MBURST_INC16              ((uint32_t)DMA_SxCR_MBURST)  
+/**
+  * @}
+  */ 
+
+/** @defgroup DMA_Peripheral_burst DMA Peripheral burst
+  * @brief    DMA peripheral burst 
+  * @{
+  */ 
+#define DMA_PBURST_SINGLE             0x00000000U
+#define DMA_PBURST_INC4               ((uint32_t)DMA_SxCR_PBURST_0)
+#define DMA_PBURST_INC8               ((uint32_t)DMA_SxCR_PBURST_1)
+#define DMA_PBURST_INC16              ((uint32_t)DMA_SxCR_PBURST)
+/**
+  * @}
+  */
+
+/** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions
+  * @brief    DMA interrupts definition 
+  * @{
+  */
+#define DMA_IT_TC                     ((uint32_t)DMA_SxCR_TCIE)
+#define DMA_IT_HT                     ((uint32_t)DMA_SxCR_HTIE)
+#define DMA_IT_TE                     ((uint32_t)DMA_SxCR_TEIE)
+#define DMA_IT_DME                    ((uint32_t)DMA_SxCR_DMEIE)
+#define DMA_IT_FE                     0x00000080U
+/**
+  * @}
+  */
+
+/** @defgroup DMA_flag_definitions DMA flag definitions
+  * @brief    DMA flag definitions 
+  * @{
+  */ 
+#define DMA_FLAG_FEIF0_4              0x00000001U
+#define DMA_FLAG_DMEIF0_4             0x00000004U
+#define DMA_FLAG_TEIF0_4              0x00000008U
+#define DMA_FLAG_HTIF0_4              0x00000010U
+#define DMA_FLAG_TCIF0_4              0x00000020U
+#define DMA_FLAG_FEIF1_5              0x00000040U
+#define DMA_FLAG_DMEIF1_5             0x00000100U
+#define DMA_FLAG_TEIF1_5              0x00000200U
+#define DMA_FLAG_HTIF1_5              0x00000400U
+#define DMA_FLAG_TCIF1_5              0x00000800U
+#define DMA_FLAG_FEIF2_6              0x00010000U
+#define DMA_FLAG_DMEIF2_6             0x00040000U
+#define DMA_FLAG_TEIF2_6              0x00080000U
+#define DMA_FLAG_HTIF2_6              0x00100000U
+#define DMA_FLAG_TCIF2_6              0x00200000U
+#define DMA_FLAG_FEIF3_7              0x00400000U
+#define DMA_FLAG_DMEIF3_7             0x01000000U
+#define DMA_FLAG_TEIF3_7              0x02000000U
+#define DMA_FLAG_HTIF3_7              0x04000000U
+#define DMA_FLAG_TCIF3_7              0x08000000U
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+ 
+/* Exported macro ------------------------------------------------------------*/
+
+/** @brief Reset DMA handle state
+  * @param  __HANDLE__ specifies the DMA handle.
+  * @retval None
+  */
+#define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)
+
+/**
+  * @brief  Return the current DMA Stream FIFO filled level.
+  * @param  __HANDLE__ DMA handle
+  * @retval The FIFO filling state.
+  *           - DMA_FIFOStatus_Less1QuarterFull: when FIFO is less than 1 quarter-full 
+  *                                              and not empty.
+  *           - DMA_FIFOStatus_1QuarterFull: if more than 1 quarter-full.
+  *           - DMA_FIFOStatus_HalfFull: if more than 1 half-full.
+  *           - DMA_FIFOStatus_3QuartersFull: if more than 3 quarters-full.
+  *           - DMA_FIFOStatus_Empty: when FIFO is empty
+  *           - DMA_FIFOStatus_Full: when FIFO is full
+  */
+#define __HAL_DMA_GET_FS(__HANDLE__)      (((__HANDLE__)->Instance->FCR & (DMA_SxFCR_FS)))
+
+/**
+  * @brief  Enable the specified DMA Stream.
+  * @param  __HANDLE__ DMA handle
+  * @retval None
+  */
+#define __HAL_DMA_ENABLE(__HANDLE__)      ((__HANDLE__)->Instance->CR |=  DMA_SxCR_EN)
+
+/**
+  * @brief  Disable the specified DMA Stream.
+  * @param  __HANDLE__ DMA handle
+  * @retval None
+  */
+#define __HAL_DMA_DISABLE(__HANDLE__)     ((__HANDLE__)->Instance->CR &=  ~DMA_SxCR_EN)
+
+/* Interrupt & Flag management */
+
+/**
+  * @brief  Return the current DMA Stream transfer complete flag.
+  * @param  __HANDLE__ DMA handle
+  * @retval The specified transfer complete flag index.
+  */
+#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
+(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TCIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TCIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TCIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TCIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TCIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TCIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TCIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TCIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TCIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TCIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TCIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TCIF2_6 :\
+   DMA_FLAG_TCIF3_7)
+
+/**
+  * @brief  Return the current DMA Stream half transfer complete flag.
+  * @param  __HANDLE__ DMA handle
+  * @retval The specified half transfer complete flag index.
+  */      
+#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
+(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_HTIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_HTIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_HTIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_HTIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_HTIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_HTIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_HTIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_HTIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_HTIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_HTIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_HTIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_HTIF2_6 :\
+   DMA_FLAG_HTIF3_7)
+
+/**
+  * @brief  Return the current DMA Stream transfer error flag.
+  * @param  __HANDLE__ DMA handle
+  * @retval The specified transfer error flag index.
+  */
+#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
+(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TEIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TEIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TEIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TEIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TEIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TEIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TEIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TEIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TEIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TEIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TEIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TEIF2_6 :\
+   DMA_FLAG_TEIF3_7)
+
+/**
+  * @brief  Return the current DMA Stream FIFO error flag.
+  * @param  __HANDLE__ DMA handle
+  * @retval The specified FIFO error flag index.
+  */
+#define __HAL_DMA_GET_FE_FLAG_INDEX(__HANDLE__)\
+(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_FEIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_FEIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_FEIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_FEIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_FEIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_FEIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_FEIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_FEIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_FEIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_FEIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_FEIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_FEIF2_6 :\
+   DMA_FLAG_FEIF3_7)
+
+/**
+  * @brief  Return the current DMA Stream direct mode error flag.
+  * @param  __HANDLE__ DMA handle
+  * @retval The specified direct mode error flag index.
+  */
+#define __HAL_DMA_GET_DME_FLAG_INDEX(__HANDLE__)\
+(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_DMEIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_DMEIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_DMEIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_DMEIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_DMEIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_DMEIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_DMEIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_DMEIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_DMEIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_DMEIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_DMEIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_DMEIF2_6 :\
+   DMA_FLAG_DMEIF3_7)
+
+/**
+  * @brief  Get the DMA Stream pending flags.
+  * @param  __HANDLE__ DMA handle
+  * @param  __FLAG__ Get the specified flag.
+  *          This parameter can be any combination of the following values:
+  *            @arg DMA_FLAG_TCIFx: Transfer complete flag.
+  *            @arg DMA_FLAG_HTIFx: Half transfer complete flag.
+  *            @arg DMA_FLAG_TEIFx: Transfer error flag.
+  *            @arg DMA_FLAG_DMEIFx: Direct mode error flag.
+  *            @arg DMA_FLAG_FEIFx: FIFO error flag.
+  *         Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Stream flag.   
+  * @retval The state of FLAG (SET or RESET).
+  */
+#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)\
+(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HISR & (__FLAG__)) :\
+ ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LISR & (__FLAG__)) :\
+ ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HISR & (__FLAG__)) : (DMA1->LISR & (__FLAG__)))
+
+/**
+  * @brief  Clear the DMA Stream pending flags.
+  * @param  __HANDLE__ DMA handle
+  * @param  __FLAG__ specifies the flag to clear.
+  *          This parameter can be any combination of the following values:
+  *            @arg DMA_FLAG_TCIFx: Transfer complete flag.
+  *            @arg DMA_FLAG_HTIFx: Half transfer complete flag.
+  *            @arg DMA_FLAG_TEIFx: Transfer error flag.
+  *            @arg DMA_FLAG_DMEIFx: Direct mode error flag.
+  *            @arg DMA_FLAG_FEIFx: FIFO error flag.
+  *         Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Stream flag.   
+  * @retval None
+  */
+#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) \
+(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HIFCR = (__FLAG__)) :\
+ ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LIFCR = (__FLAG__)) :\
+ ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HIFCR = (__FLAG__)) : (DMA1->LIFCR = (__FLAG__)))
+
+/**
+  * @brief  Enable the specified DMA Stream interrupts.
+  * @param  __HANDLE__ DMA handle
+  * @param  __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled. 
+  *        This parameter can be any combination of the following values:
+  *           @arg DMA_IT_TC: Transfer complete interrupt mask.
+  *           @arg DMA_IT_HT: Half transfer complete interrupt mask.
+  *           @arg DMA_IT_TE: Transfer error interrupt mask.
+  *           @arg DMA_IT_FE: FIFO error interrupt mask.
+  *           @arg DMA_IT_DME: Direct mode error interrupt.
+  * @retval None
+  */
+#define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__)   (((__INTERRUPT__) != DMA_IT_FE)? \
+((__HANDLE__)->Instance->CR |= (__INTERRUPT__)) : ((__HANDLE__)->Instance->FCR |= (__INTERRUPT__)))
+
+/**
+  * @brief  Disable the specified DMA Stream interrupts.
+  * @param  __HANDLE__ DMA handle
+  * @param  __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled. 
+  *         This parameter can be any combination of the following values:
+  *            @arg DMA_IT_TC: Transfer complete interrupt mask.
+  *            @arg DMA_IT_HT: Half transfer complete interrupt mask.
+  *            @arg DMA_IT_TE: Transfer error interrupt mask.
+  *            @arg DMA_IT_FE: FIFO error interrupt mask.
+  *            @arg DMA_IT_DME: Direct mode error interrupt.
+  * @retval None
+  */
+#define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__)  (((__INTERRUPT__) != DMA_IT_FE)? \
+((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__)) : ((__HANDLE__)->Instance->FCR &= ~(__INTERRUPT__)))
+
+/**
+  * @brief  Check whether the specified DMA Stream interrupt is enabled or disabled.
+  * @param  __HANDLE__ DMA handle
+  * @param  __INTERRUPT__ specifies the DMA interrupt source to check.
+  *         This parameter can be one of the following values:
+  *            @arg DMA_IT_TC: Transfer complete interrupt mask.
+  *            @arg DMA_IT_HT: Half transfer complete interrupt mask.
+  *            @arg DMA_IT_TE: Transfer error interrupt mask.
+  *            @arg DMA_IT_FE: FIFO error interrupt mask.
+  *            @arg DMA_IT_DME: Direct mode error interrupt.
+  * @retval The state of DMA_IT.
+  */
+#define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)  (((__INTERRUPT__) != DMA_IT_FE)? \
+                                                        ((__HANDLE__)->Instance->CR & (__INTERRUPT__)) : \
+                                                        ((__HANDLE__)->Instance->FCR & (__INTERRUPT__)))
+
+/**
+  * @brief  Writes the number of data units to be transferred on the DMA Stream.
+  * @param  __HANDLE__ DMA handle
+  * @param  __COUNTER__ Number of data units to be transferred (from 0 to 65535) 
+  *          Number of data items depends only on the Peripheral data format.
+  *            
+  * @note   If Peripheral data format is Bytes: number of data units is equal 
+  *         to total number of bytes to be transferred.
+  *           
+  * @note   If Peripheral data format is Half-Word: number of data units is  
+  *         equal to total number of bytes to be transferred / 2.
+  *           
+  * @note   If Peripheral data format is Word: number of data units is equal 
+  *         to total  number of bytes to be transferred / 4.
+  *      
+  * @retval The number of remaining data units in the current DMAy Streamx transfer.
+  */
+#define __HAL_DMA_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->NDTR = (uint16_t)(__COUNTER__))
+
+/**
+  * @brief  Returns the number of remaining data units in the current DMAy Streamx transfer.
+  * @param  __HANDLE__ DMA handle
+  *   
+  * @retval The number of remaining data units in the current DMA Stream transfer.
+  */
+#define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->NDTR)
+
+
+/* Include DMA HAL Extension module */
+#include "stm32f4xx_hal_dma_ex.h"   
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup DMA_Exported_Functions DMA Exported Functions
+  * @brief    DMA Exported functions 
+  * @{
+  */
+
+/** @defgroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions
+  * @brief   Initialization and de-initialization functions 
+  * @{
+  */
+HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma); 
+HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma);
+/**
+  * @}
+  */
+
+/** @defgroup DMA_Exported_Functions_Group2 I/O operation functions
+  * @brief   I/O operation functions  
+  * @{
+  */
+HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
+HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
+HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma);
+HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma);
+HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout);
+void              HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma);
+HAL_StatusTypeDef HAL_DMA_CleanCallbacks(DMA_HandleTypeDef *hdma);
+HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)(DMA_HandleTypeDef *_hdma));
+HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID);
+
+/**
+  * @}
+  */ 
+
+/** @defgroup DMA_Exported_Functions_Group3 Peripheral State functions
+  * @brief    Peripheral State functions 
+  * @{
+  */
+HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma);
+uint32_t             HAL_DMA_GetError(DMA_HandleTypeDef *hdma);
+/**
+  * @}
+  */ 
+/**
+  * @}
+  */ 
+/* Private Constants -------------------------------------------------------------*/
+/** @defgroup DMA_Private_Constants DMA Private Constants
+  * @brief    DMA private defines and constants 
+  * @{
+  */
+/**
+  * @}
+  */ 
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup DMA_Private_Macros DMA Private Macros
+  * @brief    DMA private macros 
+  * @{
+  */
+#if defined (DMA_SxCR_CHSEL_3)
+#define IS_DMA_CHANNEL(CHANNEL) (((CHANNEL) == DMA_CHANNEL_0) || \
+                                 ((CHANNEL) == DMA_CHANNEL_1) || \
+                                 ((CHANNEL) == DMA_CHANNEL_2) || \
+                                 ((CHANNEL) == DMA_CHANNEL_3) || \
+                                 ((CHANNEL) == DMA_CHANNEL_4) || \
+                                 ((CHANNEL) == DMA_CHANNEL_5) || \
+                                 ((CHANNEL) == DMA_CHANNEL_6) || \
+                                 ((CHANNEL) == DMA_CHANNEL_7) || \
+                                 ((CHANNEL) == DMA_CHANNEL_8) || \
+                                 ((CHANNEL) == DMA_CHANNEL_9) || \
+                                 ((CHANNEL) == DMA_CHANNEL_10)|| \
+                                 ((CHANNEL) == DMA_CHANNEL_11)|| \
+                                 ((CHANNEL) == DMA_CHANNEL_12)|| \
+                                 ((CHANNEL) == DMA_CHANNEL_13)|| \
+                                 ((CHANNEL) == DMA_CHANNEL_14)|| \
+                                 ((CHANNEL) == DMA_CHANNEL_15))
+#else
+#define IS_DMA_CHANNEL(CHANNEL) (((CHANNEL) == DMA_CHANNEL_0) || \
+                                 ((CHANNEL) == DMA_CHANNEL_1) || \
+                                 ((CHANNEL) == DMA_CHANNEL_2) || \
+                                 ((CHANNEL) == DMA_CHANNEL_3) || \
+                                 ((CHANNEL) == DMA_CHANNEL_4) || \
+                                 ((CHANNEL) == DMA_CHANNEL_5) || \
+                                 ((CHANNEL) == DMA_CHANNEL_6) || \
+                                 ((CHANNEL) == DMA_CHANNEL_7))
+#endif /* DMA_SxCR_CHSEL_3 */
+
+#define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \
+                                     ((DIRECTION) == DMA_MEMORY_TO_PERIPH)  || \
+                                     ((DIRECTION) == DMA_MEMORY_TO_MEMORY)) 
+
+#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x01U) && ((SIZE) < 0x10000U))
+
+#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \
+                                            ((STATE) == DMA_PINC_DISABLE))
+
+#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE)  || \
+                                        ((STATE) == DMA_MINC_DISABLE))
+
+#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE)     || \
+                                           ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \
+                                           ((SIZE) == DMA_PDATAALIGN_WORD))
+
+#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE)     || \
+                                       ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \
+                                       ((SIZE) == DMA_MDATAALIGN_WORD ))
+
+#define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL )  || \
+                           ((MODE) == DMA_CIRCULAR) || \
+                           ((MODE) == DMA_PFCTRL)) 
+
+#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW )   || \
+                                   ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \
+                                   ((PRIORITY) == DMA_PRIORITY_HIGH)   || \
+                                   ((PRIORITY) == DMA_PRIORITY_VERY_HIGH)) 
+
+#define IS_DMA_FIFO_MODE_STATE(STATE) (((STATE) == DMA_FIFOMODE_DISABLE ) || \
+                                       ((STATE) == DMA_FIFOMODE_ENABLE))
+
+#define IS_DMA_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == DMA_FIFO_THRESHOLD_1QUARTERFULL ) || \
+                                          ((THRESHOLD) == DMA_FIFO_THRESHOLD_HALFFULL)      || \
+                                          ((THRESHOLD) == DMA_FIFO_THRESHOLD_3QUARTERSFULL) || \
+                                          ((THRESHOLD) == DMA_FIFO_THRESHOLD_FULL))
+
+#define IS_DMA_MEMORY_BURST(BURST) (((BURST) == DMA_MBURST_SINGLE) || \
+                                    ((BURST) == DMA_MBURST_INC4)   || \
+                                    ((BURST) == DMA_MBURST_INC8)   || \
+                                    ((BURST) == DMA_MBURST_INC16))
+
+#define IS_DMA_PERIPHERAL_BURST(BURST) (((BURST) == DMA_PBURST_SINGLE) || \
+                                        ((BURST) == DMA_PBURST_INC4)   || \
+                                        ((BURST) == DMA_PBURST_INC8)   || \
+                                        ((BURST) == DMA_PBURST_INC16))
+/**
+  * @}
+  */ 
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup DMA_Private_Functions DMA Private Functions
+  * @brief    DMA private  functions 
+  * @{
+  */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_DMA_H */
+
diff --git a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma2d.h b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma2d.h
new file mode 100644
index 0000000..ef2ae59
--- /dev/null
+++ b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma2d.h
@@ -0,0 +1,638 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hal_dma2d.h
+  * @author  MCD Application Team
+  * @brief   Header file of DMA2D HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2016 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32F4xx_HAL_DMA2D_H
+#define STM32F4xx_HAL_DMA2D_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+  * @{
+  */
+
+#if defined (DMA2D)
+
+/** @addtogroup DMA2D DMA2D
+  * @brief DMA2D HAL module driver
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup DMA2D_Exported_Types DMA2D Exported Types
+  * @{
+  */
+#define MAX_DMA2D_LAYER  2U  /*!< DMA2D maximum number of layers */
+
+/**
+  * @brief DMA2D CLUT Structure definition
+  */
+typedef struct
+{
+  uint32_t *pCLUT;                  /*!< Configures the DMA2D CLUT memory address.*/
+
+  uint32_t CLUTColorMode;           /*!< Configures the DMA2D CLUT color mode.
+                                         This parameter can be one value of @ref DMA2D_CLUT_CM. */
+
+  uint32_t Size;                    /*!< Configures the DMA2D CLUT size.
+                                         This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.*/
+} DMA2D_CLUTCfgTypeDef;
+
+/**
+  * @brief DMA2D Init structure definition
+  */
+typedef struct
+{
+  uint32_t             Mode;               /*!< Configures the DMA2D transfer mode.
+                                                This parameter can be one value of @ref DMA2D_Mode. */
+
+  uint32_t             ColorMode;          /*!< Configures the color format of the output image.
+                                                This parameter can be one value of @ref DMA2D_Output_Color_Mode. */
+
+  uint32_t             OutputOffset;       /*!< Specifies the Offset value.
+                                                This parameter must be a number between
+                                                Min_Data = 0x0000 and Max_Data = 0x3FFF. */
+
+
+
+
+} DMA2D_InitTypeDef;
+
+
+/**
+  * @brief DMA2D Layer structure definition
+  */
+typedef struct
+{
+  uint32_t             InputOffset;       /*!< Configures the DMA2D foreground or background offset.
+                                               This parameter must be a number between
+                                               Min_Data = 0x0000 and Max_Data = 0x3FFF. */
+
+  uint32_t             InputColorMode;    /*!< Configures the DMA2D foreground or background color mode.
+                                               This parameter can be one value of @ref DMA2D_Input_Color_Mode. */
+
+  uint32_t             AlphaMode;         /*!< Configures the DMA2D foreground or background alpha mode.
+                                               This parameter can be one value of @ref DMA2D_Alpha_Mode. */
+
+  uint32_t             InputAlpha;        /*!< Specifies the DMA2D foreground or background alpha value and color value
+                                               in case of A8 or A4 color mode.
+                                               This parameter must be a number between Min_Data = 0x00
+                                               and Max_Data = 0xFF except for the color modes detailed below.
+                                               @note In case of A8 or A4 color mode (ARGB),
+                                               this parameter must be a number between
+                                               Min_Data = 0x00000000 and Max_Data = 0xFFFFFFFF where
+                                               - InputAlpha[24:31] is the alpha value ALPHA[0:7]
+                                               - InputAlpha[16:23] is the red value RED[0:7]
+                                               - InputAlpha[8:15] is the green value GREEN[0:7]
+                                               - InputAlpha[0:7] is the blue value BLUE[0:7]. */
+
+
+} DMA2D_LayerCfgTypeDef;
+
+/**
+  * @brief  HAL DMA2D State structures definition
+  */
+typedef enum
+{
+  HAL_DMA2D_STATE_RESET             = 0x00U,    /*!< DMA2D not yet initialized or disabled       */
+  HAL_DMA2D_STATE_READY             = 0x01U,    /*!< Peripheral Initialized and ready for use    */
+  HAL_DMA2D_STATE_BUSY              = 0x02U,    /*!< An internal process is ongoing              */
+  HAL_DMA2D_STATE_TIMEOUT           = 0x03U,    /*!< Timeout state                               */
+  HAL_DMA2D_STATE_ERROR             = 0x04U,    /*!< DMA2D state error                           */
+  HAL_DMA2D_STATE_SUSPEND           = 0x05U     /*!< DMA2D process is suspended                  */
+} HAL_DMA2D_StateTypeDef;
+
+/**
+  * @brief  DMA2D handle Structure definition
+  */
+typedef struct __DMA2D_HandleTypeDef
+{
+  DMA2D_TypeDef               *Instance;                                  /*!< DMA2D register base address.           */
+
+  DMA2D_InitTypeDef           Init;                                       /*!< DMA2D communication parameters.        */
+
+  void (* XferCpltCallback)(struct __DMA2D_HandleTypeDef *hdma2d);        /*!< DMA2D transfer complete callback.      */
+
+  void (* XferErrorCallback)(struct __DMA2D_HandleTypeDef *hdma2d);       /*!< DMA2D transfer error callback.         */
+
+#if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
+  void (* LineEventCallback)(struct __DMA2D_HandleTypeDef *hdma2d);       /*!< DMA2D line event callback.             */
+
+  void (* CLUTLoadingCpltCallback)(struct __DMA2D_HandleTypeDef *hdma2d); /*!< DMA2D CLUT loading completion callback */
+
+  void (* MspInitCallback)(struct __DMA2D_HandleTypeDef *hdma2d);         /*!< DMA2D Msp Init callback.               */
+
+  void (* MspDeInitCallback)(struct __DMA2D_HandleTypeDef *hdma2d);       /*!< DMA2D Msp DeInit callback.             */
+
+#endif /* (USE_HAL_DMA2D_REGISTER_CALLBACKS) */
+
+  DMA2D_LayerCfgTypeDef       LayerCfg[MAX_DMA2D_LAYER];                  /*!< DMA2D Layers parameters                */
+
+  HAL_LockTypeDef             Lock;                                       /*!< DMA2D lock.                            */
+
+  __IO HAL_DMA2D_StateTypeDef State;                                      /*!< DMA2D transfer state.                  */
+
+  __IO uint32_t               ErrorCode;                                  /*!< DMA2D error code.                      */
+} DMA2D_HandleTypeDef;
+
+#if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
+/**
+  * @brief  HAL DMA2D Callback pointer definition
+  */
+typedef void (*pDMA2D_CallbackTypeDef)(DMA2D_HandleTypeDef *hdma2d); /*!< Pointer to a DMA2D common callback function */
+#endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup DMA2D_Exported_Constants DMA2D Exported Constants
+  * @{
+  */
+
+/** @defgroup DMA2D_Error_Code DMA2D Error Code
+  * @{
+  */
+#define HAL_DMA2D_ERROR_NONE        0x00000000U  /*!< No error             */
+#define HAL_DMA2D_ERROR_TE          0x00000001U  /*!< Transfer error       */
+#define HAL_DMA2D_ERROR_CE          0x00000002U  /*!< Configuration error  */
+#define HAL_DMA2D_ERROR_CAE         0x00000004U  /*!< CLUT access error    */
+#define HAL_DMA2D_ERROR_TIMEOUT     0x00000020U  /*!< Timeout error        */
+#if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
+#define HAL_DMA2D_ERROR_INVALID_CALLBACK 0x00000040U  /*!< Invalid callback error  */
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+
+/** @defgroup DMA2D_Mode DMA2D Mode
+  * @{
+  */
+#define DMA2D_M2M                   0x00000000U                         /*!< DMA2D memory to memory transfer mode */
+#define DMA2D_M2M_PFC               DMA2D_CR_MODE_0                     /*!< DMA2D memory to memory with pixel format conversion transfer mode */
+#define DMA2D_M2M_BLEND             DMA2D_CR_MODE_1                     /*!< DMA2D memory to memory with blending transfer mode */
+#define DMA2D_R2M                   DMA2D_CR_MODE            /*!< DMA2D register to memory transfer mode */
+/**
+  * @}
+  */
+
+/** @defgroup DMA2D_Output_Color_Mode DMA2D Output Color Mode
+  * @{
+  */
+#define DMA2D_OUTPUT_ARGB8888       0x00000000U                           /*!< ARGB8888 DMA2D color mode */
+#define DMA2D_OUTPUT_RGB888         DMA2D_OPFCCR_CM_0                     /*!< RGB888 DMA2D color mode   */
+#define DMA2D_OUTPUT_RGB565         DMA2D_OPFCCR_CM_1                     /*!< RGB565 DMA2D color mode   */
+#define DMA2D_OUTPUT_ARGB1555       (DMA2D_OPFCCR_CM_0|DMA2D_OPFCCR_CM_1) /*!< ARGB1555 DMA2D color mode */
+#define DMA2D_OUTPUT_ARGB4444       DMA2D_OPFCCR_CM_2                     /*!< ARGB4444 DMA2D color mode */
+/**
+  * @}
+  */
+
+/** @defgroup DMA2D_Input_Color_Mode DMA2D Input Color Mode
+  * @{
+  */
+#define DMA2D_INPUT_ARGB8888        0x00000000U  /*!< ARGB8888 color mode */
+#define DMA2D_INPUT_RGB888          0x00000001U  /*!< RGB888 color mode   */
+#define DMA2D_INPUT_RGB565          0x00000002U  /*!< RGB565 color mode   */
+#define DMA2D_INPUT_ARGB1555        0x00000003U  /*!< ARGB1555 color mode */
+#define DMA2D_INPUT_ARGB4444        0x00000004U  /*!< ARGB4444 color mode */
+#define DMA2D_INPUT_L8              0x00000005U  /*!< L8 color mode       */
+#define DMA2D_INPUT_AL44            0x00000006U  /*!< AL44 color mode     */
+#define DMA2D_INPUT_AL88            0x00000007U  /*!< AL88 color mode     */
+#define DMA2D_INPUT_L4              0x00000008U  /*!< L4 color mode       */
+#define DMA2D_INPUT_A8              0x00000009U  /*!< A8 color mode       */
+#define DMA2D_INPUT_A4              0x0000000AU  /*!< A4 color mode       */
+/**
+  * @}
+  */
+
+/** @defgroup DMA2D_Alpha_Mode DMA2D Alpha Mode
+  * @{
+  */
+#define DMA2D_NO_MODIF_ALPHA        0x00000000U  /*!< No modification of the alpha channel value                     */
+#define DMA2D_REPLACE_ALPHA         0x00000001U  /*!< Replace original alpha channel value by programmed alpha value */
+#define DMA2D_COMBINE_ALPHA         0x00000002U  /*!< Replace original alpha channel value by programmed alpha value
+                                                      with original alpha channel value                              */
+/**
+  * @}
+  */
+
+
+
+
+
+
+/** @defgroup DMA2D_CLUT_CM DMA2D CLUT Color Mode
+  * @{
+  */
+#define DMA2D_CCM_ARGB8888          0x00000000U  /*!< ARGB8888 DMA2D CLUT color mode */
+#define DMA2D_CCM_RGB888            0x00000001U  /*!< RGB888 DMA2D CLUT color mode   */
+/**
+  * @}
+  */
+
+/** @defgroup DMA2D_Interrupts DMA2D Interrupts
+  * @{
+  */
+#define DMA2D_IT_CE                 DMA2D_CR_CEIE            /*!< Configuration Error Interrupt */
+#define DMA2D_IT_CTC                DMA2D_CR_CTCIE           /*!< CLUT Transfer Complete Interrupt */
+#define DMA2D_IT_CAE                DMA2D_CR_CAEIE           /*!< CLUT Access Error Interrupt */
+#define DMA2D_IT_TW                 DMA2D_CR_TWIE            /*!< Transfer Watermark Interrupt */
+#define DMA2D_IT_TC                 DMA2D_CR_TCIE            /*!< Transfer Complete Interrupt */
+#define DMA2D_IT_TE                 DMA2D_CR_TEIE            /*!< Transfer Error Interrupt */
+/**
+  * @}
+  */
+
+/** @defgroup DMA2D_Flags DMA2D Flags
+  * @{
+  */
+#define DMA2D_FLAG_CE               DMA2D_ISR_CEIF           /*!< Configuration Error Interrupt Flag */
+#define DMA2D_FLAG_CTC              DMA2D_ISR_CTCIF          /*!< CLUT Transfer Complete Interrupt Flag */
+#define DMA2D_FLAG_CAE              DMA2D_ISR_CAEIF          /*!< CLUT Access Error Interrupt Flag */
+#define DMA2D_FLAG_TW               DMA2D_ISR_TWIF           /*!< Transfer Watermark Interrupt Flag */
+#define DMA2D_FLAG_TC               DMA2D_ISR_TCIF           /*!< Transfer Complete Interrupt Flag */
+#define DMA2D_FLAG_TE               DMA2D_ISR_TEIF           /*!< Transfer Error Interrupt Flag */
+/**
+  * @}
+  */
+
+#if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
+/**
+  * @brief  HAL DMA2D common Callback ID enumeration definition
+  */
+typedef enum
+{
+  HAL_DMA2D_MSPINIT_CB_ID           = 0x00U,    /*!< DMA2D MspInit callback ID                 */
+  HAL_DMA2D_MSPDEINIT_CB_ID         = 0x01U,    /*!< DMA2D MspDeInit callback ID               */
+  HAL_DMA2D_TRANSFERCOMPLETE_CB_ID  = 0x02U,    /*!< DMA2D transfer complete callback ID       */
+  HAL_DMA2D_TRANSFERERROR_CB_ID     = 0x03U,    /*!< DMA2D transfer error callback ID          */
+  HAL_DMA2D_LINEEVENT_CB_ID         = 0x04U,    /*!< DMA2D line event callback ID              */
+  HAL_DMA2D_CLUTLOADINGCPLT_CB_ID   = 0x05U,    /*!< DMA2D CLUT loading completion callback ID */
+} HAL_DMA2D_CallbackIDTypeDef;
+#endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */
+
+
+/**
+  * @}
+  */
+/* Exported macros ------------------------------------------------------------*/
+/** @defgroup DMA2D_Exported_Macros DMA2D Exported Macros
+  * @{
+  */
+
+/** @brief Reset DMA2D handle state
+  * @param  __HANDLE__ specifies the DMA2D handle.
+  * @retval None
+  */
+#if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
+#define __HAL_DMA2D_RESET_HANDLE_STATE(__HANDLE__) do{                                             \
+                                                       (__HANDLE__)->State = HAL_DMA2D_STATE_RESET;\
+                                                       (__HANDLE__)->MspInitCallback = NULL;       \
+                                                       (__HANDLE__)->MspDeInitCallback = NULL;     \
+                                                     }while(0)
+#else
+#define __HAL_DMA2D_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA2D_STATE_RESET)
+#endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */
+
+
+/**
+  * @brief  Enable the DMA2D.
+  * @param  __HANDLE__ DMA2D handle
+  * @retval None.
+  */
+#define __HAL_DMA2D_ENABLE(__HANDLE__)        ((__HANDLE__)->Instance->CR |= DMA2D_CR_START)
+
+
+/* Interrupt & Flag management */
+/**
+  * @brief  Get the DMA2D pending flags.
+  * @param  __HANDLE__ DMA2D handle
+  * @param  __FLAG__ flag to check.
+  *          This parameter can be any combination of the following values:
+  *            @arg DMA2D_FLAG_CE:  Configuration error flag
+  *            @arg DMA2D_FLAG_CTC: CLUT transfer complete flag
+  *            @arg DMA2D_FLAG_CAE: CLUT access error flag
+  *            @arg DMA2D_FLAG_TW:  Transfer Watermark flag
+  *            @arg DMA2D_FLAG_TC:  Transfer complete flag
+  *            @arg DMA2D_FLAG_TE:  Transfer error flag
+  * @retval The state of FLAG.
+  */
+#define __HAL_DMA2D_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR & (__FLAG__))
+
+/**
+  * @brief  Clear the DMA2D pending flags.
+  * @param  __HANDLE__ DMA2D handle
+  * @param  __FLAG__ specifies the flag to clear.
+  *          This parameter can be any combination of the following values:
+  *            @arg DMA2D_FLAG_CE:  Configuration error flag
+  *            @arg DMA2D_FLAG_CTC: CLUT transfer complete flag
+  *            @arg DMA2D_FLAG_CAE: CLUT access error flag
+  *            @arg DMA2D_FLAG_TW:  Transfer Watermark flag
+  *            @arg DMA2D_FLAG_TC:  Transfer complete flag
+  *            @arg DMA2D_FLAG_TE:  Transfer error flag
+  * @retval None
+  */
+#define __HAL_DMA2D_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->IFCR = (__FLAG__))
+
+/**
+  * @brief  Enable the specified DMA2D interrupts.
+  * @param  __HANDLE__ DMA2D handle
+  * @param __INTERRUPT__ specifies the DMA2D interrupt sources to be enabled.
+  *          This parameter can be any combination of the following values:
+  *            @arg DMA2D_IT_CE:  Configuration error interrupt mask
+  *            @arg DMA2D_IT_CTC: CLUT transfer complete interrupt mask
+  *            @arg DMA2D_IT_CAE: CLUT access error interrupt mask
+  *            @arg DMA2D_IT_TW:  Transfer Watermark interrupt mask
+  *            @arg DMA2D_IT_TC:  Transfer complete interrupt mask
+  *            @arg DMA2D_IT_TE:  Transfer error interrupt mask
+  * @retval None
+  */
+#define __HAL_DMA2D_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
+
+/**
+  * @brief  Disable the specified DMA2D interrupts.
+  * @param  __HANDLE__ DMA2D handle
+  * @param __INTERRUPT__ specifies the DMA2D interrupt sources to be disabled.
+  *          This parameter can be any combination of the following values:
+  *            @arg DMA2D_IT_CE:  Configuration error interrupt mask
+  *            @arg DMA2D_IT_CTC: CLUT transfer complete interrupt mask
+  *            @arg DMA2D_IT_CAE: CLUT access error interrupt mask
+  *            @arg DMA2D_IT_TW:  Transfer Watermark interrupt mask
+  *            @arg DMA2D_IT_TC:  Transfer complete interrupt mask
+  *            @arg DMA2D_IT_TE:  Transfer error interrupt mask
+  * @retval None
+  */
+#define __HAL_DMA2D_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
+
+/**
+  * @brief  Check whether the specified DMA2D interrupt source is enabled or not.
+  * @param  __HANDLE__ DMA2D handle
+  * @param  __INTERRUPT__ specifies the DMA2D interrupt source to check.
+  *          This parameter can be one of the following values:
+  *            @arg DMA2D_IT_CE:  Configuration error interrupt mask
+  *            @arg DMA2D_IT_CTC: CLUT transfer complete interrupt mask
+  *            @arg DMA2D_IT_CAE: CLUT access error interrupt mask
+  *            @arg DMA2D_IT_TW:  Transfer Watermark interrupt mask
+  *            @arg DMA2D_IT_TC:  Transfer complete interrupt mask
+  *            @arg DMA2D_IT_TE:  Transfer error interrupt mask
+  * @retval The state of INTERRUPT source.
+  */
+#define __HAL_DMA2D_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR & (__INTERRUPT__))
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup DMA2D_Exported_Functions DMA2D Exported Functions
+  * @{
+  */
+
+/** @addtogroup DMA2D_Exported_Functions_Group1 Initialization and de-initialization functions
+  * @{
+  */
+
+/* Initialization and de-initialization functions *******************************/
+HAL_StatusTypeDef HAL_DMA2D_Init(DMA2D_HandleTypeDef *hdma2d);
+HAL_StatusTypeDef HAL_DMA2D_DeInit(DMA2D_HandleTypeDef *hdma2d);
+void              HAL_DMA2D_MspInit(DMA2D_HandleTypeDef *hdma2d);
+void              HAL_DMA2D_MspDeInit(DMA2D_HandleTypeDef *hdma2d);
+/* Callbacks Register/UnRegister functions  ***********************************/
+#if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
+HAL_StatusTypeDef HAL_DMA2D_RegisterCallback(DMA2D_HandleTypeDef *hdma2d, HAL_DMA2D_CallbackIDTypeDef CallbackID,
+                                             pDMA2D_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_DMA2D_UnRegisterCallback(DMA2D_HandleTypeDef *hdma2d, HAL_DMA2D_CallbackIDTypeDef CallbackID);
+#endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+
+
+/** @addtogroup DMA2D_Exported_Functions_Group2 IO operation functions
+  * @{
+  */
+
+/* IO operation functions *******************************************************/
+HAL_StatusTypeDef HAL_DMA2D_Start(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width,
+                                  uint32_t Height);
+HAL_StatusTypeDef HAL_DMA2D_BlendingStart(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2,
+                                          uint32_t DstAddress, uint32_t Width,  uint32_t Height);
+HAL_StatusTypeDef HAL_DMA2D_Start_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width,
+                                     uint32_t Height);
+HAL_StatusTypeDef HAL_DMA2D_BlendingStart_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2,
+                                             uint32_t DstAddress, uint32_t Width, uint32_t Height);
+HAL_StatusTypeDef HAL_DMA2D_Suspend(DMA2D_HandleTypeDef *hdma2d);
+HAL_StatusTypeDef HAL_DMA2D_Resume(DMA2D_HandleTypeDef *hdma2d);
+HAL_StatusTypeDef HAL_DMA2D_Abort(DMA2D_HandleTypeDef *hdma2d);
+HAL_StatusTypeDef HAL_DMA2D_EnableCLUT(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);
+HAL_StatusTypeDef HAL_DMA2D_CLUTStartLoad(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef *CLUTCfg,
+                                          uint32_t LayerIdx);
+HAL_StatusTypeDef HAL_DMA2D_CLUTStartLoad_IT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef *CLUTCfg,
+                                             uint32_t LayerIdx);
+HAL_StatusTypeDef HAL_DMA2D_CLUTLoad(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx);
+HAL_StatusTypeDef HAL_DMA2D_CLUTLoad_IT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx);
+HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Abort(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);
+HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Suspend(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);
+HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Resume(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);
+HAL_StatusTypeDef HAL_DMA2D_PollForTransfer(DMA2D_HandleTypeDef *hdma2d, uint32_t Timeout);
+void              HAL_DMA2D_IRQHandler(DMA2D_HandleTypeDef *hdma2d);
+void              HAL_DMA2D_LineEventCallback(DMA2D_HandleTypeDef *hdma2d);
+void              HAL_DMA2D_CLUTLoadingCpltCallback(DMA2D_HandleTypeDef *hdma2d);
+
+/**
+  * @}
+  */
+
+/** @addtogroup DMA2D_Exported_Functions_Group3 Peripheral Control functions
+  * @{
+  */
+
+/* Peripheral Control functions *************************************************/
+HAL_StatusTypeDef HAL_DMA2D_ConfigLayer(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);
+HAL_StatusTypeDef HAL_DMA2D_ConfigCLUT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx);
+HAL_StatusTypeDef HAL_DMA2D_ProgramLineEvent(DMA2D_HandleTypeDef *hdma2d, uint32_t Line);
+HAL_StatusTypeDef HAL_DMA2D_EnableDeadTime(DMA2D_HandleTypeDef *hdma2d);
+HAL_StatusTypeDef HAL_DMA2D_DisableDeadTime(DMA2D_HandleTypeDef *hdma2d);
+HAL_StatusTypeDef HAL_DMA2D_ConfigDeadTime(DMA2D_HandleTypeDef *hdma2d, uint8_t DeadTime);
+
+/**
+  * @}
+  */
+
+/** @addtogroup DMA2D_Exported_Functions_Group4 Peripheral State and Error functions
+  * @{
+  */
+
+/* Peripheral State functions ***************************************************/
+HAL_DMA2D_StateTypeDef HAL_DMA2D_GetState(DMA2D_HandleTypeDef *hdma2d);
+uint32_t               HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private constants ---------------------------------------------------------*/
+
+/** @addtogroup DMA2D_Private_Constants DMA2D Private Constants
+  * @{
+  */
+
+/** @defgroup DMA2D_Maximum_Line_WaterMark DMA2D Maximum Line Watermark
+  * @{
+  */
+#define DMA2D_LINE_WATERMARK_MAX            DMA2D_LWR_LW       /*!< DMA2D maximum line watermark */
+/**
+  * @}
+  */
+
+/** @defgroup DMA2D_Color_Value DMA2D Color Value
+  * @{
+  */
+#define DMA2D_COLOR_VALUE                 0x000000FFU  /*!< Color value mask */
+/**
+  * @}
+  */
+
+/** @defgroup DMA2D_Max_Layer DMA2D Maximum Number of Layers
+  * @{
+  */
+#define DMA2D_MAX_LAYER         2U         /*!< DMA2D maximum number of layers */
+/**
+  * @}
+  */
+
+/** @defgroup DMA2D_Layers DMA2D Layers
+  * @{
+  */
+#define DMA2D_BACKGROUND_LAYER             0x00000000U   /*!< DMA2D Background Layer (layer 0) */
+#define DMA2D_FOREGROUND_LAYER             0x00000001U   /*!< DMA2D Foreground Layer (layer 1) */
+/**
+  * @}
+  */
+
+/** @defgroup DMA2D_Offset DMA2D Offset
+  * @{
+  */
+#define DMA2D_OFFSET                DMA2D_FGOR_LO            /*!< maximum Line Offset */
+/**
+  * @}
+  */
+
+/** @defgroup DMA2D_Size DMA2D Size
+  * @{
+  */
+#define DMA2D_PIXEL                 (DMA2D_NLR_PL >> 16U)    /*!< DMA2D maximum number of pixels per line */
+#define DMA2D_LINE                  DMA2D_NLR_NL             /*!< DMA2D maximum number of lines           */
+/**
+  * @}
+  */
+
+/** @defgroup DMA2D_CLUT_Size DMA2D CLUT Size
+  * @{
+  */
+#define DMA2D_CLUT_SIZE             (DMA2D_FGPFCCR_CS >> 8U)  /*!< DMA2D maximum CLUT size */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup DMA2D_Private_Macros DMA2D Private Macros
+  * @{
+  */
+#define IS_DMA2D_LAYER(LAYER)                 (((LAYER) == DMA2D_BACKGROUND_LAYER)\
+                                               || ((LAYER) == DMA2D_FOREGROUND_LAYER))
+
+#define IS_DMA2D_MODE(MODE)                   (((MODE) == DMA2D_M2M)       || ((MODE) == DMA2D_M2M_PFC) || \
+                                               ((MODE) == DMA2D_M2M_BLEND) || ((MODE) == DMA2D_R2M))
+
+#define IS_DMA2D_CMODE(MODE_ARGB)             (((MODE_ARGB) == DMA2D_OUTPUT_ARGB8888) || \
+                                               ((MODE_ARGB) == DMA2D_OUTPUT_RGB888)   || \
+                                               ((MODE_ARGB) == DMA2D_OUTPUT_RGB565)   || \
+                                               ((MODE_ARGB) == DMA2D_OUTPUT_ARGB1555) || \
+                                               ((MODE_ARGB) == DMA2D_OUTPUT_ARGB4444))
+
+#define IS_DMA2D_COLOR(COLOR)                 ((COLOR) <= DMA2D_COLOR_VALUE)
+#define IS_DMA2D_LINE(LINE)                   ((LINE) <= DMA2D_LINE)
+#define IS_DMA2D_PIXEL(PIXEL)                 ((PIXEL) <= DMA2D_PIXEL)
+#define IS_DMA2D_OFFSET(OOFFSET)              ((OOFFSET) <= DMA2D_OFFSET)
+
+#define IS_DMA2D_INPUT_COLOR_MODE(INPUT_CM)   (((INPUT_CM) == DMA2D_INPUT_ARGB8888) || \
+                                               ((INPUT_CM) == DMA2D_INPUT_RGB888)   || \
+                                               ((INPUT_CM) == DMA2D_INPUT_RGB565)   || \
+                                               ((INPUT_CM) == DMA2D_INPUT_ARGB1555) || \
+                                               ((INPUT_CM) == DMA2D_INPUT_ARGB4444) || \
+                                               ((INPUT_CM) == DMA2D_INPUT_L8)       || \
+                                               ((INPUT_CM) == DMA2D_INPUT_AL44)     || \
+                                               ((INPUT_CM) == DMA2D_INPUT_AL88)     || \
+                                               ((INPUT_CM) == DMA2D_INPUT_L4)       || \
+                                               ((INPUT_CM) == DMA2D_INPUT_A8)       || \
+                                               ((INPUT_CM) == DMA2D_INPUT_A4))
+
+#define IS_DMA2D_ALPHA_MODE(AlphaMode)        (((AlphaMode) == DMA2D_NO_MODIF_ALPHA) || \
+                                               ((AlphaMode) == DMA2D_REPLACE_ALPHA)  || \
+                                               ((AlphaMode) == DMA2D_COMBINE_ALPHA))
+
+
+
+
+
+#define IS_DMA2D_CLUT_CM(CLUT_CM)             (((CLUT_CM) == DMA2D_CCM_ARGB8888) || ((CLUT_CM) == DMA2D_CCM_RGB888))
+#define IS_DMA2D_CLUT_SIZE(CLUT_SIZE)         ((CLUT_SIZE) <= DMA2D_CLUT_SIZE)
+#define IS_DMA2D_LINEWATERMARK(LineWatermark) ((LineWatermark) <= DMA2D_LINE_WATERMARK_MAX)
+#define IS_DMA2D_IT(IT)                       (((IT) == DMA2D_IT_CTC) || ((IT) == DMA2D_IT_CAE) || \
+                                               ((IT) == DMA2D_IT_TW)  || ((IT) == DMA2D_IT_TC)  || \
+                                               ((IT) == DMA2D_IT_TE)  || ((IT) == DMA2D_IT_CE))
+#define IS_DMA2D_GET_FLAG(FLAG)               (((FLAG) == DMA2D_FLAG_CTC) || ((FLAG) == DMA2D_FLAG_CAE) || \
+                                               ((FLAG) == DMA2D_FLAG_TW)  || ((FLAG) == DMA2D_FLAG_TC)  || \
+                                               ((FLAG) == DMA2D_FLAG_TE)  || ((FLAG) == DMA2D_FLAG_CE))
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* defined (DMA2D) */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32F4xx_HAL_DMA2D_H */
diff --git a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h
new file mode 100644
index 0000000..266c1fa
--- /dev/null
+++ b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h
@@ -0,0 +1,102 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hal_dma_ex.h
+  * @author  MCD Application Team
+  * @brief   Header file of DMA HAL extension module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file in
+  * the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_DMA_EX_H
+#define __STM32F4xx_HAL_DMA_EX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup DMAEx
+  * @{
+  */ 
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup DMAEx_Exported_Types DMAEx Exported Types
+  * @brief DMAEx Exported types
+  * @{
+  */
+   
+/** 
+  * @brief  HAL DMA Memory definition  
+  */ 
+typedef enum
+{
+  MEMORY0      = 0x00U,    /*!< Memory 0     */
+  MEMORY1      = 0x01U     /*!< Memory 1     */
+}HAL_DMA_MemoryTypeDef;
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup DMAEx_Exported_Functions DMAEx Exported Functions
+  * @brief   DMAEx Exported functions
+  * @{
+  */
+
+/** @defgroup DMAEx_Exported_Functions_Group1 Extended features functions
+  * @brief   Extended features functions
+  * @{
+  */
+
+/* IO operation functions *******************************************************/
+HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength);
+HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength);
+HAL_StatusTypeDef HAL_DMAEx_ChangeMemory(DMA_HandleTypeDef *hdma, uint32_t Address, HAL_DMA_MemoryTypeDef memory);
+
+/**
+  * @}
+  */
+/**
+  * @}
+  */
+         
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup DMAEx_Private_Functions DMAEx Private Functions
+  * @brief DMAEx Private functions
+  * @{
+  */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__STM32F4xx_HAL_DMA_EX_H*/
+
diff --git a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dsi.h b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dsi.h
new file mode 100644
index 0000000..f54362a
--- /dev/null
+++ b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dsi.h
@@ -0,0 +1,1377 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hal_dsi.h
+  * @author  MCD Application Team
+  * @brief   Header file of DSI HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2016 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32F4xx_HAL_DSI_H
+#define STM32F4xx_HAL_DSI_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+#if defined(DSI)
+
+/** @addtogroup STM32F4xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup DSI DSI
+  * @brief DSI HAL module driver
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup DSI_Exported_Types DSI Exported Types
+  * @{
+  */
+/**
+  * @brief  DSI Init Structure definition
+  */
+typedef struct
+{
+  uint32_t AutomaticClockLaneControl;    /*!< Automatic clock lane control
+                                              This parameter can be any value of @ref DSI_Automatic_Clk_Lane_Control */
+
+  uint32_t TXEscapeCkdiv;                /*!< TX Escape clock division
+                                              The values 0 and 1 stop the TX_ESC clock generation                    */
+
+  uint32_t NumberOfLanes;                /*!< Number of lanes
+                                              This parameter can be any value of @ref DSI_Number_Of_Lanes            */
+
+} DSI_InitTypeDef;
+
+/**
+  * @brief  DSI PLL Clock structure definition
+  */
+typedef struct
+{
+  uint32_t PLLNDIV;                 /*!< PLL Loop Division Factor
+                                         This parameter must be a value between 10 and 125                    */
+
+  uint32_t PLLIDF;                  /*!< PLL Input Division Factor
+                                         This parameter can be any value of @ref DSI_PLL_IDF                  */
+
+  uint32_t PLLODF;                  /*!< PLL Output Division Factor
+                                         This parameter can be any value of @ref DSI_PLL_ODF                  */
+
+} DSI_PLLInitTypeDef;
+
+/**
+  * @brief  DSI Video mode configuration
+  */
+typedef struct
+{
+  uint32_t VirtualChannelID;             /*!< Virtual channel ID                                                 */
+
+  uint32_t ColorCoding;                  /*!< Color coding for LTDC interface
+                                              This parameter can be any value of @ref DSI_Color_Coding           */
+
+  uint32_t LooselyPacked;                /*!< Enable or disable loosely packed stream (needed only when using
+                                              18-bit configuration).
+                                              This parameter can be any value of @ref DSI_LooselyPacked          */
+
+  uint32_t Mode;                         /*!< Video mode type
+                                              This parameter can be any value of @ref DSI_Video_Mode_Type        */
+
+  uint32_t PacketSize;                   /*!< Video packet size                                                  */
+
+  uint32_t NumberOfChunks;               /*!< Number of chunks                                                   */
+
+  uint32_t NullPacketSize;               /*!< Null packet size                                                   */
+
+  uint32_t HSPolarity;                   /*!< HSYNC pin polarity
+                                              This parameter can be any value of @ref DSI_HSYNC_Polarity         */
+
+  uint32_t VSPolarity;                   /*!< VSYNC pin polarity
+                                              This parameter can be any value of @ref DSI_VSYNC_Active_Polarity  */
+
+  uint32_t DEPolarity;                   /*!< Data Enable pin polarity
+                                              This parameter can be any value of @ref DSI_DATA_ENABLE_Polarity   */
+
+  uint32_t HorizontalSyncActive;         /*!< Horizontal synchronism active duration (in lane byte clock cycles) */
+
+  uint32_t HorizontalBackPorch;          /*!< Horizontal back-porch duration (in lane byte clock cycles)         */
+
+  uint32_t HorizontalLine;               /*!< Horizontal line duration (in lane byte clock cycles)               */
+
+  uint32_t VerticalSyncActive;           /*!< Vertical synchronism active duration                               */
+
+  uint32_t VerticalBackPorch;            /*!< Vertical back-porch duration                                       */
+
+  uint32_t VerticalFrontPorch;           /*!< Vertical front-porch duration                                      */
+
+  uint32_t VerticalActive;               /*!< Vertical active duration                                           */
+
+  uint32_t LPCommandEnable;              /*!< Low-power command enable
+                                              This parameter can be any value of @ref DSI_LP_Command             */
+
+  uint32_t LPLargestPacketSize;          /*!< The size, in bytes, of the low power largest packet that
+                                              can fit in a line during VSA, VBP and VFP regions                  */
+
+  uint32_t LPVACTLargestPacketSize;      /*!< The size, in bytes, of the low power largest packet that
+                                              can fit in a line during VACT region                               */
+
+  uint32_t LPHorizontalFrontPorchEnable; /*!< Low-power horizontal front-porch enable
+                                              This parameter can be any value of @ref DSI_LP_HFP                 */
+
+  uint32_t LPHorizontalBackPorchEnable;  /*!< Low-power horizontal back-porch enable
+                                              This parameter can be any value of @ref DSI_LP_HBP                 */
+
+  uint32_t LPVerticalActiveEnable;       /*!< Low-power vertical active enable
+                                              This parameter can be any value of @ref DSI_LP_VACT                */
+
+  uint32_t LPVerticalFrontPorchEnable;   /*!< Low-power vertical front-porch enable
+                                              This parameter can be any value of @ref DSI_LP_VFP                 */
+
+  uint32_t LPVerticalBackPorchEnable;    /*!< Low-power vertical back-porch enable
+                                              This parameter can be any value of @ref DSI_LP_VBP                 */
+
+  uint32_t LPVerticalSyncActiveEnable;   /*!< Low-power vertical sync active enable
+                                              This parameter can be any value of @ref DSI_LP_VSYNC               */
+
+  uint32_t FrameBTAAcknowledgeEnable;    /*!< Frame bus-turn-around acknowledge enable
+                                              This parameter can be any value of @ref DSI_FBTA_acknowledge       */
+
+} DSI_VidCfgTypeDef;
+
+/**
+  * @brief  DSI Adapted command mode configuration
+  */
+typedef struct
+{
+  uint32_t VirtualChannelID;             /*!< Virtual channel ID                                                */
+
+  uint32_t ColorCoding;                  /*!< Color coding for LTDC interface
+                                              This parameter can be any value of @ref DSI_Color_Coding          */
+
+  uint32_t CommandSize;                  /*!< Maximum allowed size for an LTDC write memory command, measured in
+                                              pixels. This parameter can be any value between 0x00 and 0xFFFFU   */
+
+  uint32_t TearingEffectSource;          /*!< Tearing effect source
+                                              This parameter can be any value of @ref DSI_TearingEffectSource   */
+
+  uint32_t TearingEffectPolarity;        /*!< Tearing effect pin polarity
+                                              This parameter can be any value of @ref DSI_TearingEffectPolarity */
+
+  uint32_t HSPolarity;                   /*!< HSYNC pin polarity
+                                              This parameter can be any value of @ref DSI_HSYNC_Polarity        */
+
+  uint32_t VSPolarity;                   /*!< VSYNC pin polarity
+                                              This parameter can be any value of @ref DSI_VSYNC_Active_Polarity */
+
+  uint32_t DEPolarity;                   /*!< Data Enable pin polarity
+                                              This parameter can be any value of @ref DSI_DATA_ENABLE_Polarity  */
+
+  uint32_t VSyncPol;                     /*!< VSync edge on which the LTDC is halted
+                                              This parameter can be any value of @ref DSI_Vsync_Polarity        */
+
+  uint32_t AutomaticRefresh;             /*!< Automatic refresh mode
+                                              This parameter can be any value of @ref DSI_AutomaticRefresh      */
+
+  uint32_t TEAcknowledgeRequest;         /*!< Tearing Effect Acknowledge Request Enable
+                                              This parameter can be any value of @ref DSI_TE_AcknowledgeRequest */
+
+} DSI_CmdCfgTypeDef;
+
+/**
+  * @brief  DSI command transmission mode configuration
+  */
+typedef struct
+{
+  uint32_t LPGenShortWriteNoP;           /*!< Generic Short Write Zero parameters Transmission
+                                              This parameter can be any value of @ref DSI_LP_LPGenShortWriteNoP  */
+
+  uint32_t LPGenShortWriteOneP;          /*!< Generic Short Write One parameter Transmission
+                                              This parameter can be any value of @ref DSI_LP_LPGenShortWriteOneP */
+
+  uint32_t LPGenShortWriteTwoP;          /*!< Generic Short Write Two parameters Transmission
+                                              This parameter can be any value of @ref DSI_LP_LPGenShortWriteTwoP */
+
+  uint32_t LPGenShortReadNoP;            /*!< Generic Short Read Zero parameters Transmission
+                                              This parameter can be any value of @ref DSI_LP_LPGenShortReadNoP   */
+
+  uint32_t LPGenShortReadOneP;           /*!< Generic Short Read One parameter Transmission
+                                              This parameter can be any value of @ref DSI_LP_LPGenShortReadOneP  */
+
+  uint32_t LPGenShortReadTwoP;           /*!< Generic Short Read Two parameters Transmission
+                                              This parameter can be any value of @ref DSI_LP_LPGenShortReadTwoP  */
+
+  uint32_t LPGenLongWrite;               /*!< Generic Long Write Transmission
+                                              This parameter can be any value of @ref DSI_LP_LPGenLongWrite      */
+
+  uint32_t LPDcsShortWriteNoP;           /*!< DCS Short Write Zero parameters Transmission
+                                              This parameter can be any value of @ref DSI_LP_LPDcsShortWriteNoP  */
+
+  uint32_t LPDcsShortWriteOneP;          /*!< DCS Short Write One parameter Transmission
+                                              This parameter can be any value of @ref DSI_LP_LPDcsShortWriteOneP */
+
+  uint32_t LPDcsShortReadNoP;            /*!< DCS Short Read Zero parameters Transmission
+                                              This parameter can be any value of @ref DSI_LP_LPDcsShortReadNoP   */
+
+  uint32_t LPDcsLongWrite;               /*!< DCS Long Write Transmission
+                                              This parameter can be any value of @ref DSI_LP_LPDcsLongWrite      */
+
+  uint32_t LPMaxReadPacket;              /*!< Maximum Read Packet Size Transmission
+                                              This parameter can be any value of @ref DSI_LP_LPMaxReadPacket     */
+
+  uint32_t AcknowledgeRequest;           /*!< Acknowledge Request Enable
+                                              This parameter can be any value of @ref DSI_AcknowledgeRequest     */
+
+} DSI_LPCmdTypeDef;
+
+/**
+  * @brief  DSI PHY Timings definition
+  */
+typedef struct
+{
+  uint32_t ClockLaneHS2LPTime;           /*!< The maximum time that the D-PHY clock lane takes to go from high-speed
+                                              to low-power transmission                                              */
+
+  uint32_t ClockLaneLP2HSTime;           /*!< The maximum time that the D-PHY clock lane takes to go from low-power
+                                              to high-speed transmission                                             */
+
+  uint32_t DataLaneHS2LPTime;            /*!< The maximum time that the D-PHY data lanes takes to go from high-speed
+                                              to low-power transmission                                              */
+
+  uint32_t DataLaneLP2HSTime;            /*!< The maximum time that the D-PHY data lanes takes to go from low-power
+                                              to high-speed transmission                                             */
+
+  uint32_t DataLaneMaxReadTime;          /*!< The maximum time required to perform a read command */
+
+  uint32_t StopWaitTime;                 /*!< The minimum wait period to request a High-Speed transmission after the
+                                              Stop state                                                             */
+
+} DSI_PHY_TimerTypeDef;
+
+/**
+  * @brief  DSI HOST Timeouts definition
+  */
+typedef struct
+{
+  uint32_t TimeoutCkdiv;                 /*!< Time-out clock division                                  */
+
+  uint32_t HighSpeedTransmissionTimeout; /*!< High-speed transmission time-out                         */
+
+  uint32_t LowPowerReceptionTimeout;     /*!< Low-power reception time-out                             */
+
+  uint32_t HighSpeedReadTimeout;         /*!< High-speed read time-out                                 */
+
+  uint32_t LowPowerReadTimeout;          /*!< Low-power read time-out                                  */
+
+  uint32_t HighSpeedWriteTimeout;        /*!< High-speed write time-out                                */
+
+  uint32_t HighSpeedWritePrespMode;      /*!< High-speed write presp mode
+                                              This parameter can be any value of @ref DSI_HS_PrespMode */
+
+  uint32_t LowPowerWriteTimeout;         /*!< Low-speed write time-out                                 */
+
+  uint32_t BTATimeout;                   /*!< BTA time-out                                             */
+
+} DSI_HOST_TimeoutTypeDef;
+
+/**
+  * @brief  DSI States Structure definition
+  */
+typedef enum
+{
+  HAL_DSI_STATE_RESET   = 0x00U,
+  HAL_DSI_STATE_READY   = 0x01U,
+  HAL_DSI_STATE_ERROR   = 0x02U,
+  HAL_DSI_STATE_BUSY    = 0x03U,
+  HAL_DSI_STATE_TIMEOUT = 0x04U
+} HAL_DSI_StateTypeDef;
+
+/**
+  * @brief  DSI Handle Structure definition
+  */
+#if (USE_HAL_DSI_REGISTER_CALLBACKS == 1)
+typedef struct __DSI_HandleTypeDef
+#else
+typedef struct
+#endif /* USE_HAL_DSI_REGISTER_CALLBACKS */
+{
+  DSI_TypeDef               *Instance;    /*!< Register base address      */
+  DSI_InitTypeDef           Init;         /*!< DSI required parameters    */
+  HAL_LockTypeDef           Lock;         /*!< DSI peripheral status      */
+  __IO HAL_DSI_StateTypeDef State;        /*!< DSI communication state    */
+  __IO uint32_t             ErrorCode;    /*!< DSI Error code             */
+  uint32_t                  ErrorMsk;     /*!< DSI Error monitoring mask  */
+
+#if (USE_HAL_DSI_REGISTER_CALLBACKS == 1)
+  void (* TearingEffectCallback)(struct __DSI_HandleTypeDef *hdsi);   /*!< DSI Tearing Effect Callback */
+  void (* EndOfRefreshCallback)(struct __DSI_HandleTypeDef *hdsi);    /*!< DSI End Of Refresh Callback */
+  void (* ErrorCallback)(struct __DSI_HandleTypeDef *hdsi);           /*!< DSI Error Callback          */
+
+  void (* MspInitCallback)(struct __DSI_HandleTypeDef *hdsi);         /*!< DSI Msp Init callback       */
+  void (* MspDeInitCallback)(struct __DSI_HandleTypeDef *hdsi);       /*!< DSI Msp DeInit callback     */
+
+#endif /* USE_HAL_DSI_REGISTER_CALLBACKS */
+
+} DSI_HandleTypeDef;
+
+#if (USE_HAL_DSI_REGISTER_CALLBACKS == 1)
+/**
+  * @brief  HAL DSI Callback ID enumeration definition
+  */
+typedef enum
+{
+  HAL_DSI_MSPINIT_CB_ID            = 0x00U,    /*!< DSI MspInit callback ID        */
+  HAL_DSI_MSPDEINIT_CB_ID          = 0x01U,    /*!< DSI MspDeInit callback ID      */
+
+  HAL_DSI_TEARING_EFFECT_CB_ID     = 0x02U,    /*!< DSI Tearing Effect Callback ID */
+  HAL_DSI_ENDOF_REFRESH_CB_ID      = 0x03U,    /*!< DSI End Of Refresh Callback ID */
+  HAL_DSI_ERROR_CB_ID              = 0x04U     /*!< DSI Error Callback ID          */
+
+} HAL_DSI_CallbackIDTypeDef;
+
+/**
+  * @brief  HAL DSI Callback pointer definition
+  */
+typedef  void (*pDSI_CallbackTypeDef)(DSI_HandleTypeDef *hdsi);  /*!< pointer to an DSI callback function */
+
+#endif /* USE_HAL_DSI_REGISTER_CALLBACKS */
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup DSI_Exported_Constants DSI Exported Constants
+  * @{
+  */
+/** @defgroup DSI_DCS_Command DSI DCS Command
+  * @{
+  */
+#define DSI_ENTER_IDLE_MODE       0x39U
+#define DSI_ENTER_INVERT_MODE     0x21U
+#define DSI_ENTER_NORMAL_MODE     0x13U
+#define DSI_ENTER_PARTIAL_MODE    0x12U
+#define DSI_ENTER_SLEEP_MODE      0x10U
+#define DSI_EXIT_IDLE_MODE        0x38U
+#define DSI_EXIT_INVERT_MODE      0x20U
+#define DSI_EXIT_SLEEP_MODE       0x11U
+#define DSI_GET_3D_CONTROL        0x3FU
+#define DSI_GET_ADDRESS_MODE      0x0BU
+#define DSI_GET_BLUE_CHANNEL      0x08U
+#define DSI_GET_DIAGNOSTIC_RESULT 0x0FU
+#define DSI_GET_DISPLAY_MODE      0x0DU
+#define DSI_GET_GREEN_CHANNEL     0x07U
+#define DSI_GET_PIXEL_FORMAT      0x0CU
+#define DSI_GET_POWER_MODE        0x0AU
+#define DSI_GET_RED_CHANNEL       0x06U
+#define DSI_GET_SCANLINE          0x45U
+#define DSI_GET_SIGNAL_MODE       0x0EU
+#define DSI_NOP                   0x00U
+#define DSI_READ_DDB_CONTINUE     0xA8U
+#define DSI_READ_DDB_START        0xA1U
+#define DSI_READ_MEMORY_CONTINUE  0x3EU
+#define DSI_READ_MEMORY_START     0x2EU
+#define DSI_SET_3D_CONTROL        0x3DU
+#define DSI_SET_ADDRESS_MODE      0x36U
+#define DSI_SET_COLUMN_ADDRESS    0x2AU
+#define DSI_SET_DISPLAY_OFF       0x28U
+#define DSI_SET_DISPLAY_ON        0x29U
+#define DSI_SET_GAMMA_CURVE       0x26U
+#define DSI_SET_PAGE_ADDRESS      0x2BU
+#define DSI_SET_PARTIAL_COLUMNS   0x31U
+#define DSI_SET_PARTIAL_ROWS      0x30U
+#define DSI_SET_PIXEL_FORMAT      0x3AU
+#define DSI_SET_SCROLL_AREA       0x33U
+#define DSI_SET_SCROLL_START      0x37U
+#define DSI_SET_TEAR_OFF          0x34U
+#define DSI_SET_TEAR_ON           0x35U
+#define DSI_SET_TEAR_SCANLINE     0x44U
+#define DSI_SET_VSYNC_TIMING      0x40U
+#define DSI_SOFT_RESET            0x01U
+#define DSI_WRITE_LUT             0x2DU
+#define DSI_WRITE_MEMORY_CONTINUE 0x3CU
+#define DSI_WRITE_MEMORY_START    0x2CU
+/**
+  * @}
+  */
+
+/** @defgroup DSI_Video_Mode_Type DSI Video Mode Type
+  * @{
+  */
+#define DSI_VID_MODE_NB_PULSES    0U
+#define DSI_VID_MODE_NB_EVENTS    1U
+#define DSI_VID_MODE_BURST        2U
+/**
+  * @}
+  */
+
+/** @defgroup DSI_Color_Mode DSI Color Mode
+  * @{
+  */
+#define DSI_COLOR_MODE_FULL       0x00000000U
+#define DSI_COLOR_MODE_EIGHT      DSI_WCR_COLM
+/**
+  * @}
+  */
+
+/** @defgroup DSI_ShutDown DSI ShutDown
+  * @{
+  */
+#define DSI_DISPLAY_ON            0x00000000U
+#define DSI_DISPLAY_OFF           DSI_WCR_SHTDN
+/**
+  * @}
+  */
+
+/** @defgroup DSI_LP_Command DSI LP Command
+  * @{
+  */
+#define DSI_LP_COMMAND_DISABLE    0x00000000U
+#define DSI_LP_COMMAND_ENABLE     DSI_VMCR_LPCE
+/**
+  * @}
+  */
+
+/** @defgroup DSI_LP_HFP DSI LP HFP
+  * @{
+  */
+#define DSI_LP_HFP_DISABLE        0x00000000U
+#define DSI_LP_HFP_ENABLE         DSI_VMCR_LPHFPE
+/**
+  * @}
+  */
+
+/** @defgroup DSI_LP_HBP DSI LP HBP
+  * @{
+  */
+#define DSI_LP_HBP_DISABLE        0x00000000U
+#define DSI_LP_HBP_ENABLE         DSI_VMCR_LPHBPE
+/**
+  * @}
+  */
+
+/** @defgroup DSI_LP_VACT DSI LP VACT
+  * @{
+  */
+#define DSI_LP_VACT_DISABLE       0x00000000U
+#define DSI_LP_VACT_ENABLE        DSI_VMCR_LPVAE
+/**
+  * @}
+  */
+
+/** @defgroup DSI_LP_VFP DSI LP VFP
+  * @{
+  */
+#define DSI_LP_VFP_DISABLE       0x00000000U
+#define DSI_LP_VFP_ENABLE        DSI_VMCR_LPVFPE
+/**
+  * @}
+  */
+
+/** @defgroup DSI_LP_VBP DSI LP VBP
+  * @{
+  */
+#define DSI_LP_VBP_DISABLE       0x00000000U
+#define DSI_LP_VBP_ENABLE        DSI_VMCR_LPVBPE
+/**
+  * @}
+  */
+
+/** @defgroup DSI_LP_VSYNC DSI LP VSYNC
+  * @{
+  */
+#define DSI_LP_VSYNC_DISABLE     0x00000000U
+#define DSI_LP_VSYNC_ENABLE      DSI_VMCR_LPVSAE
+/**
+  * @}
+  */
+
+/** @defgroup DSI_FBTA_acknowledge DSI FBTA Acknowledge
+  * @{
+  */
+#define DSI_FBTAA_DISABLE        0x00000000U
+#define DSI_FBTAA_ENABLE         DSI_VMCR_FBTAAE
+/**
+  * @}
+  */
+
+/** @defgroup DSI_TearingEffectSource DSI Tearing Effect Source
+  * @{
+  */
+#define DSI_TE_DSILINK           0x00000000U
+#define DSI_TE_EXTERNAL          DSI_WCFGR_TESRC
+/**
+  * @}
+  */
+
+/** @defgroup DSI_TearingEffectPolarity DSI Tearing Effect Polarity
+  * @{
+  */
+#define DSI_TE_RISING_EDGE       0x00000000U
+#define DSI_TE_FALLING_EDGE      DSI_WCFGR_TEPOL
+/**
+  * @}
+  */
+
+/** @defgroup DSI_Vsync_Polarity DSI Vsync Polarity
+  * @{
+  */
+#define DSI_VSYNC_FALLING        0x00000000U
+#define DSI_VSYNC_RISING         DSI_WCFGR_VSPOL
+/**
+  * @}
+  */
+
+/** @defgroup DSI_AutomaticRefresh DSI Automatic Refresh
+  * @{
+  */
+#define DSI_AR_DISABLE           0x00000000U
+#define DSI_AR_ENABLE            DSI_WCFGR_AR
+/**
+  * @}
+  */
+
+/** @defgroup DSI_TE_AcknowledgeRequest DSI TE Acknowledge Request
+  * @{
+  */
+#define DSI_TE_ACKNOWLEDGE_DISABLE 0x00000000U
+#define DSI_TE_ACKNOWLEDGE_ENABLE  DSI_CMCR_TEARE
+/**
+  * @}
+  */
+
+/** @defgroup DSI_AcknowledgeRequest DSI Acknowledge Request
+  * @{
+  */
+#define DSI_ACKNOWLEDGE_DISABLE   0x00000000U
+#define DSI_ACKNOWLEDGE_ENABLE    DSI_CMCR_ARE
+/**
+  * @}
+  */
+
+/** @defgroup DSI_LP_LPGenShortWriteNoP DSI LP LPGen Short Write NoP
+  * @{
+  */
+#define DSI_LP_GSW0P_DISABLE     0x00000000U
+#define DSI_LP_GSW0P_ENABLE      DSI_CMCR_GSW0TX
+/**
+  * @}
+  */
+
+/** @defgroup DSI_LP_LPGenShortWriteOneP DSI LP LPGen Short Write OneP
+  * @{
+  */
+#define DSI_LP_GSW1P_DISABLE     0x00000000U
+#define DSI_LP_GSW1P_ENABLE      DSI_CMCR_GSW1TX
+/**
+  * @}
+  */
+
+/** @defgroup DSI_LP_LPGenShortWriteTwoP DSI LP LPGen Short Write TwoP
+  * @{
+  */
+#define DSI_LP_GSW2P_DISABLE     0x00000000U
+#define DSI_LP_GSW2P_ENABLE      DSI_CMCR_GSW2TX
+/**
+  * @}
+  */
+
+/** @defgroup DSI_LP_LPGenShortReadNoP DSI LP LPGen Short Read NoP
+  * @{
+  */
+#define DSI_LP_GSR0P_DISABLE     0x00000000U
+#define DSI_LP_GSR0P_ENABLE      DSI_CMCR_GSR0TX
+/**
+  * @}
+  */
+
+/** @defgroup DSI_LP_LPGenShortReadOneP DSI LP LPGen Short Read OneP
+  * @{
+  */
+#define DSI_LP_GSR1P_DISABLE     0x00000000U
+#define DSI_LP_GSR1P_ENABLE      DSI_CMCR_GSR1TX
+/**
+  * @}
+  */
+
+/** @defgroup DSI_LP_LPGenShortReadTwoP DSI LP LPGen Short Read TwoP
+  * @{
+  */
+#define DSI_LP_GSR2P_DISABLE     0x00000000U
+#define DSI_LP_GSR2P_ENABLE      DSI_CMCR_GSR2TX
+/**
+  * @}
+  */
+
+/** @defgroup DSI_LP_LPGenLongWrite DSI LP LPGen LongWrite
+  * @{
+  */
+#define DSI_LP_GLW_DISABLE       0x00000000U
+#define DSI_LP_GLW_ENABLE        DSI_CMCR_GLWTX
+/**
+  * @}
+  */
+
+/** @defgroup DSI_LP_LPDcsShortWriteNoP DSI LP LPDcs Short Write NoP
+  * @{
+  */
+#define DSI_LP_DSW0P_DISABLE     0x00000000U
+#define DSI_LP_DSW0P_ENABLE      DSI_CMCR_DSW0TX
+/**
+  * @}
+  */
+
+/** @defgroup DSI_LP_LPDcsShortWriteOneP DSI LP LPDcs Short Write OneP
+  * @{
+  */
+#define DSI_LP_DSW1P_DISABLE     0x00000000U
+#define DSI_LP_DSW1P_ENABLE      DSI_CMCR_DSW1TX
+/**
+  * @}
+  */
+
+/** @defgroup DSI_LP_LPDcsShortReadNoP DSI LP LPDcs Short Read NoP
+  * @{
+  */
+#define DSI_LP_DSR0P_DISABLE     0x00000000U
+#define DSI_LP_DSR0P_ENABLE      DSI_CMCR_DSR0TX
+/**
+  * @}
+  */
+
+/** @defgroup DSI_LP_LPDcsLongWrite DSI LP LPDcs Long Write
+  * @{
+  */
+#define DSI_LP_DLW_DISABLE       0x00000000U
+#define DSI_LP_DLW_ENABLE        DSI_CMCR_DLWTX
+/**
+  * @}
+  */
+
+/** @defgroup DSI_LP_LPMaxReadPacket DSI LP LPMax Read Packet
+  * @{
+  */
+#define DSI_LP_MRDP_DISABLE      0x00000000U
+#define DSI_LP_MRDP_ENABLE       DSI_CMCR_MRDPS
+/**
+  * @}
+  */
+
+/** @defgroup DSI_HS_PrespMode DSI HS Presp Mode
+  * @{
+  */
+#define DSI_HS_PM_DISABLE        0x00000000U
+#define DSI_HS_PM_ENABLE         DSI_TCCR3_PM
+/**
+  * @}
+  */
+
+
+/** @defgroup DSI_Automatic_Clk_Lane_Control DSI Automatic Clk Lane Control
+  * @{
+  */
+#define DSI_AUTO_CLK_LANE_CTRL_DISABLE 0x00000000U
+#define DSI_AUTO_CLK_LANE_CTRL_ENABLE  DSI_CLCR_ACR
+/**
+  * @}
+  */
+
+/** @defgroup DSI_Number_Of_Lanes DSI Number Of Lanes
+  * @{
+  */
+#define DSI_ONE_DATA_LANE          0U
+#define DSI_TWO_DATA_LANES         1U
+/**
+  * @}
+  */
+
+/** @defgroup DSI_FlowControl DSI Flow Control
+  * @{
+  */
+#define DSI_FLOW_CONTROL_CRC_RX    DSI_PCR_CRCRXE
+#define DSI_FLOW_CONTROL_ECC_RX    DSI_PCR_ECCRXE
+#define DSI_FLOW_CONTROL_BTA       DSI_PCR_BTAE
+#define DSI_FLOW_CONTROL_EOTP_RX   DSI_PCR_ETRXE
+#define DSI_FLOW_CONTROL_EOTP_TX   DSI_PCR_ETTXE
+#define DSI_FLOW_CONTROL_ALL       (DSI_FLOW_CONTROL_CRC_RX | DSI_FLOW_CONTROL_ECC_RX  | \
+                                    DSI_FLOW_CONTROL_BTA    | DSI_FLOW_CONTROL_EOTP_RX | \
+                                    DSI_FLOW_CONTROL_EOTP_TX)
+/**
+  * @}
+  */
+
+/** @defgroup DSI_Color_Coding DSI Color Coding
+  * @{
+  */
+#define DSI_RGB565                 0x00000000U /*!< The values 0x00000001 and 0x00000002 can also be used for the RGB565 color mode configuration */
+#define DSI_RGB666                 0x00000003U /*!< The value 0x00000004 can also be used for the RGB666 color mode configuration                 */
+#define DSI_RGB888                 0x00000005U
+/**
+  * @}
+  */
+
+/** @defgroup DSI_LooselyPacked DSI Loosely Packed
+  * @{
+  */
+#define DSI_LOOSELY_PACKED_ENABLE  DSI_LCOLCR_LPE
+#define DSI_LOOSELY_PACKED_DISABLE 0x00000000U
+/**
+  * @}
+  */
+
+/** @defgroup DSI_HSYNC_Polarity DSI HSYNC Polarity
+  * @{
+  */
+#define DSI_HSYNC_ACTIVE_HIGH       0x00000000U
+#define DSI_HSYNC_ACTIVE_LOW        DSI_LPCR_HSP
+/**
+  * @}
+  */
+
+/** @defgroup DSI_VSYNC_Active_Polarity DSI VSYNC Active Polarity
+  * @{
+  */
+#define DSI_VSYNC_ACTIVE_HIGH       0x00000000U
+#define DSI_VSYNC_ACTIVE_LOW        DSI_LPCR_VSP
+/**
+  * @}
+  */
+
+/** @defgroup DSI_DATA_ENABLE_Polarity DSI DATA ENABLE Polarity
+  * @{
+  */
+#define DSI_DATA_ENABLE_ACTIVE_HIGH 0x00000000U
+#define DSI_DATA_ENABLE_ACTIVE_LOW  DSI_LPCR_DEP
+/**
+  * @}
+  */
+
+/** @defgroup DSI_PLL_IDF DSI PLL IDF
+  * @{
+  */
+#define DSI_PLL_IN_DIV1             0x00000001U
+#define DSI_PLL_IN_DIV2             0x00000002U
+#define DSI_PLL_IN_DIV3             0x00000003U
+#define DSI_PLL_IN_DIV4             0x00000004U
+#define DSI_PLL_IN_DIV5             0x00000005U
+#define DSI_PLL_IN_DIV6             0x00000006U
+#define DSI_PLL_IN_DIV7             0x00000007U
+/**
+  * @}
+  */
+
+/** @defgroup DSI_PLL_ODF DSI PLL ODF
+  * @{
+  */
+#define DSI_PLL_OUT_DIV1            0x00000000U
+#define DSI_PLL_OUT_DIV2            0x00000001U
+#define DSI_PLL_OUT_DIV4            0x00000002U
+#define DSI_PLL_OUT_DIV8            0x00000003U
+/**
+  * @}
+  */
+
+/** @defgroup DSI_Flags DSI Flags
+  * @{
+  */
+#define DSI_FLAG_TE                 DSI_WISR_TEIF
+#define DSI_FLAG_ER                 DSI_WISR_ERIF
+#define DSI_FLAG_BUSY               DSI_WISR_BUSY
+#define DSI_FLAG_PLLLS              DSI_WISR_PLLLS
+#define DSI_FLAG_PLLL               DSI_WISR_PLLLIF
+#define DSI_FLAG_PLLU               DSI_WISR_PLLUIF
+#define DSI_FLAG_RRS                DSI_WISR_RRS
+#define DSI_FLAG_RR                 DSI_WISR_RRIF
+/**
+  * @}
+  */
+
+/** @defgroup DSI_Interrupts DSI Interrupts
+  * @{
+  */
+#define DSI_IT_TE                   DSI_WIER_TEIE
+#define DSI_IT_ER                   DSI_WIER_ERIE
+#define DSI_IT_PLLL                 DSI_WIER_PLLLIE
+#define DSI_IT_PLLU                 DSI_WIER_PLLUIE
+#define DSI_IT_RR                   DSI_WIER_RRIE
+/**
+  * @}
+  */
+
+/** @defgroup DSI_SHORT_WRITE_PKT_Data_Type DSI SHORT WRITE PKT Data Type
+  * @{
+  */
+#define DSI_DCS_SHORT_PKT_WRITE_P0  0x00000005U /*!< DCS short write, no parameters      */
+#define DSI_DCS_SHORT_PKT_WRITE_P1  0x00000015U /*!< DCS short write, one parameter      */
+#define DSI_GEN_SHORT_PKT_WRITE_P0  0x00000003U /*!< Generic short write, no parameters  */
+#define DSI_GEN_SHORT_PKT_WRITE_P1  0x00000013U /*!< Generic short write, one parameter  */
+#define DSI_GEN_SHORT_PKT_WRITE_P2  0x00000023U /*!< Generic short write, two parameters */
+/**
+  * @}
+  */
+
+/** @defgroup DSI_LONG_WRITE_PKT_Data_Type DSI LONG WRITE PKT Data Type
+  * @{
+  */
+#define DSI_DCS_LONG_PKT_WRITE      0x00000039U /*!< DCS long write     */
+#define DSI_GEN_LONG_PKT_WRITE      0x00000029U /*!< Generic long write */
+/**
+  * @}
+  */
+
+/** @defgroup DSI_SHORT_READ_PKT_Data_Type DSI SHORT READ PKT Data Type
+  * @{
+  */
+#define DSI_DCS_SHORT_PKT_READ      0x00000006U /*!< DCS short read                     */
+#define DSI_GEN_SHORT_PKT_READ_P0   0x00000004U /*!< Generic short read, no parameters  */
+#define DSI_GEN_SHORT_PKT_READ_P1   0x00000014U /*!< Generic short read, one parameter  */
+#define DSI_GEN_SHORT_PKT_READ_P2   0x00000024U /*!< Generic short read, two parameters */
+/**
+  * @}
+  */
+
+/** @defgroup DSI_Error_Data_Type DSI Error Data Type
+  * @{
+  */
+#define HAL_DSI_ERROR_NONE              0U
+#define HAL_DSI_ERROR_ACK               0x00000001U /*!< Acknowledge errors             */
+#define HAL_DSI_ERROR_PHY               0x00000002U /*!< PHY related errors             */
+#define HAL_DSI_ERROR_TX                0x00000004U /*!< Transmission error             */
+#define HAL_DSI_ERROR_RX                0x00000008U /*!< Reception error                */
+#define HAL_DSI_ERROR_ECC               0x00000010U /*!< ECC errors                     */
+#define HAL_DSI_ERROR_CRC               0x00000020U /*!< CRC error                      */
+#define HAL_DSI_ERROR_PSE               0x00000040U /*!< Packet Size error              */
+#define HAL_DSI_ERROR_EOT               0x00000080U /*!< End Of Transmission error      */
+#define HAL_DSI_ERROR_OVF               0x00000100U /*!< FIFO overflow error            */
+#define HAL_DSI_ERROR_GEN               0x00000200U /*!< Generic FIFO related errors    */
+#if (USE_HAL_DSI_REGISTER_CALLBACKS == 1)
+#define HAL_DSI_ERROR_INVALID_CALLBACK  0x00000400U /*!< DSI Invalid Callback error      */
+#endif /* USE_HAL_DSI_REGISTER_CALLBACKS */
+/**
+  * @}
+  */
+
+/** @defgroup DSI_Lane_Group DSI Lane Group
+  * @{
+  */
+#define DSI_CLOCK_LANE              0x00000000U
+#define DSI_DATA_LANES              0x00000001U
+/**
+  * @}
+  */
+
+/** @defgroup DSI_Communication_Delay DSI Communication Delay
+  * @{
+  */
+#define DSI_SLEW_RATE_HSTX          0x00000000U
+#define DSI_SLEW_RATE_LPTX          0x00000001U
+#define DSI_HS_DELAY                0x00000002U
+/**
+  * @}
+  */
+
+/** @defgroup DSI_CustomLane DSI CustomLane
+  * @{
+  */
+#define DSI_SWAP_LANE_PINS          0x00000000U
+#define DSI_INVERT_HS_SIGNAL        0x00000001U
+/**
+  * @}
+  */
+
+/** @defgroup DSI_Lane_Select DSI Lane Select
+  * @{
+  */
+#define DSI_CLK_LANE                0x00000000U
+#define DSI_DATA_LANE0              0x00000001U
+#define DSI_DATA_LANE1              0x00000002U
+/**
+  * @}
+  */
+
+/** @defgroup DSI_PHY_Timing DSI PHY Timing
+  * @{
+  */
+#define DSI_TCLK_POST               0x00000000U
+#define DSI_TLPX_CLK                0x00000001U
+#define DSI_THS_EXIT                0x00000002U
+#define DSI_TLPX_DATA               0x00000003U
+#define DSI_THS_ZERO                0x00000004U
+#define DSI_THS_TRAIL               0x00000005U
+#define DSI_THS_PREPARE             0x00000006U
+#define DSI_TCLK_ZERO               0x00000007U
+#define DSI_TCLK_PREPARE            0x00000008U
+/**
+  * @}
+  */
+
+
+/**
+  * @}
+  */
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup DSI_Exported_Macros DSI Exported Macros
+  * @{
+  */
+
+/**
+  * @brief Reset DSI handle state.
+  * @param  __HANDLE__ DSI handle
+  * @retval None
+  */
+#if (USE_HAL_DSI_REGISTER_CALLBACKS == 1)
+#define __HAL_DSI_RESET_HANDLE_STATE(__HANDLE__) do{                                               \
+                                                     (__HANDLE__)->State = HAL_DSI_STATE_RESET;    \
+                                                     (__HANDLE__)->MspInitCallback = NULL;         \
+                                                     (__HANDLE__)->MspDeInitCallback = NULL;       \
+                                                   } while(0)
+#else
+#define __HAL_DSI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DSI_STATE_RESET)
+#endif /*USE_HAL_DSI_REGISTER_CALLBACKS */
+
+/**
+  * @brief  Enables the DSI host.
+  * @param  __HANDLE__  DSI handle
+  * @retval None.
+  */
+#define __HAL_DSI_ENABLE(__HANDLE__) do { \
+                                          __IO uint32_t tmpreg = 0x00U; \
+                                          SET_BIT((__HANDLE__)->Instance->CR, DSI_CR_EN);\
+                                          /* Delay after an DSI Host enabling */ \
+                                          tmpreg = READ_BIT((__HANDLE__)->Instance->CR, DSI_CR_EN);\
+                                          UNUSED(tmpreg); \
+                                        } while(0U)
+
+/**
+  * @brief  Disables the DSI host.
+  * @param  __HANDLE__  DSI handle
+  * @retval None.
+  */
+#define __HAL_DSI_DISABLE(__HANDLE__) do { \
+                                           __IO uint32_t tmpreg = 0x00U; \
+                                           CLEAR_BIT((__HANDLE__)->Instance->CR, DSI_CR_EN);\
+                                           /* Delay after an DSI Host disabling */ \
+                                           tmpreg = READ_BIT((__HANDLE__)->Instance->CR, DSI_CR_EN);\
+                                           UNUSED(tmpreg); \
+                                         } while(0U)
+
+/**
+  * @brief  Enables the DSI wrapper.
+  * @param  __HANDLE__  DSI handle
+  * @retval None.
+  */
+#define __HAL_DSI_WRAPPER_ENABLE(__HANDLE__) do { \
+                                                  __IO uint32_t tmpreg = 0x00U; \
+                                                  SET_BIT((__HANDLE__)->Instance->WCR, DSI_WCR_DSIEN);\
+                                                  /* Delay after an DSI warpper enabling */ \
+                                                  tmpreg = READ_BIT((__HANDLE__)->Instance->WCR, DSI_WCR_DSIEN);\
+                                                  UNUSED(tmpreg); \
+                                                } while(0U)
+
+/**
+  * @brief  Disable the DSI wrapper.
+  * @param  __HANDLE__  DSI handle
+  * @retval None.
+  */
+#define __HAL_DSI_WRAPPER_DISABLE(__HANDLE__) do { \
+                                                   __IO uint32_t tmpreg = 0x00U; \
+                                                   CLEAR_BIT((__HANDLE__)->Instance->WCR, DSI_WCR_DSIEN);\
+                                                   /* Delay after an DSI warpper disabling*/ \
+                                                   tmpreg = READ_BIT((__HANDLE__)->Instance->WCR, DSI_WCR_DSIEN);\
+                                                   UNUSED(tmpreg); \
+                                                 } while(0U)
+
+/**
+  * @brief  Enables the DSI PLL.
+  * @param  __HANDLE__  DSI handle
+  * @retval None.
+  */
+#define __HAL_DSI_PLL_ENABLE(__HANDLE__) do { \
+                                              __IO uint32_t tmpreg = 0x00U; \
+                                              SET_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_PLLEN);\
+                                              /* Delay after an DSI PLL enabling */ \
+                                              tmpreg = READ_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_PLLEN);\
+                                              UNUSED(tmpreg); \
+                                            } while(0U)
+
+/**
+  * @brief  Disables the DSI PLL.
+  * @param  __HANDLE__  DSI handle
+  * @retval None.
+  */
+#define __HAL_DSI_PLL_DISABLE(__HANDLE__) do { \
+                                               __IO uint32_t tmpreg = 0x00U; \
+                                               CLEAR_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_PLLEN);\
+                                               /* Delay after an DSI PLL disabling */ \
+                                               tmpreg = READ_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_PLLEN);\
+                                               UNUSED(tmpreg); \
+                                             } while(0U)
+
+/**
+  * @brief  Enables the DSI regulator.
+  * @param  __HANDLE__  DSI handle
+  * @retval None.
+  */
+#define __HAL_DSI_REG_ENABLE(__HANDLE__) do { \
+                                              __IO uint32_t tmpreg = 0x00U; \
+                                              SET_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_REGEN);\
+                                              /* Delay after an DSI regulator enabling */ \
+                                              tmpreg = READ_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_REGEN);\
+                                              UNUSED(tmpreg); \
+                                            } while(0U)
+
+/**
+  * @brief  Disables the DSI regulator.
+  * @param  __HANDLE__  DSI handle
+  * @retval None.
+  */
+#define __HAL_DSI_REG_DISABLE(__HANDLE__) do { \
+                                               __IO uint32_t tmpreg = 0x00U; \
+                                               CLEAR_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_REGEN);\
+                                               /* Delay after an DSI regulator disabling */ \
+                                               tmpreg = READ_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_REGEN);\
+                                               UNUSED(tmpreg); \
+                                             } while(0U)
+
+/**
+  * @brief  Get the DSI pending flags.
+  * @param  __HANDLE__  DSI handle.
+  * @param  __FLAG__  Get the specified flag.
+  *          This parameter can be any combination of the following values:
+  *            @arg DSI_FLAG_TE   : Tearing Effect Interrupt Flag
+  *            @arg DSI_FLAG_ER   : End of Refresh Interrupt Flag
+  *            @arg DSI_FLAG_BUSY : Busy Flag
+  *            @arg DSI_FLAG_PLLLS: PLL Lock Status
+  *            @arg DSI_FLAG_PLLL : PLL Lock Interrupt Flag
+  *            @arg DSI_FLAG_PLLU : PLL Unlock Interrupt Flag
+  *            @arg DSI_FLAG_RRS  : Regulator Ready Flag
+  *            @arg DSI_FLAG_RR   : Regulator Ready Interrupt Flag
+  * @retval The state of FLAG (SET or RESET).
+  */
+#define __HAL_DSI_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->WISR & (__FLAG__))
+
+/**
+  * @brief  Clears the DSI pending flags.
+  * @param  __HANDLE__  DSI handle.
+  * @param  __FLAG__  specifies the flag to clear.
+  *          This parameter can be any combination of the following values:
+  *            @arg DSI_FLAG_TE   : Tearing Effect Interrupt Flag
+  *            @arg DSI_FLAG_ER   : End of Refresh Interrupt Flag
+  *            @arg DSI_FLAG_PLLL : PLL Lock Interrupt Flag
+  *            @arg DSI_FLAG_PLLU : PLL Unlock Interrupt Flag
+  *            @arg DSI_FLAG_RR   : Regulator Ready Interrupt Flag
+  * @retval None
+  */
+#define __HAL_DSI_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->WIFCR = (__FLAG__))
+
+/**
+  * @brief  Enables the specified DSI interrupts.
+  * @param  __HANDLE__  DSI handle.
+  * @param __INTERRUPT__  specifies the DSI interrupt sources to be enabled.
+  *          This parameter can be any combination of the following values:
+  *            @arg DSI_IT_TE  : Tearing Effect Interrupt
+  *            @arg DSI_IT_ER  : End of Refresh Interrupt
+  *            @arg DSI_IT_PLLL: PLL Lock Interrupt
+  *            @arg DSI_IT_PLLU: PLL Unlock Interrupt
+  *            @arg DSI_IT_RR  : Regulator Ready Interrupt
+  * @retval None
+  */
+#define __HAL_DSI_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->WIER |= (__INTERRUPT__))
+
+/**
+  * @brief  Disables the specified DSI interrupts.
+  * @param  __HANDLE__  DSI handle
+  * @param __INTERRUPT__  specifies the DSI interrupt sources to be disabled.
+  *          This parameter can be any combination of the following values:
+  *            @arg DSI_IT_TE  : Tearing Effect Interrupt
+  *            @arg DSI_IT_ER  : End of Refresh Interrupt
+  *            @arg DSI_IT_PLLL: PLL Lock Interrupt
+  *            @arg DSI_IT_PLLU: PLL Unlock Interrupt
+  *            @arg DSI_IT_RR  : Regulator Ready Interrupt
+  * @retval None
+  */
+#define __HAL_DSI_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->WIER &= ~(__INTERRUPT__))
+
+/**
+  * @brief  Checks whether the specified DSI interrupt source is enabled or not.
+  * @param  __HANDLE__  DSI handle
+  * @param  __INTERRUPT__  specifies the DSI interrupt source to check.
+  *          This parameter can be one of the following values:
+  *            @arg DSI_IT_TE  : Tearing Effect Interrupt
+  *            @arg DSI_IT_ER  : End of Refresh Interrupt
+  *            @arg DSI_IT_PLLL: PLL Lock Interrupt
+  *            @arg DSI_IT_PLLU: PLL Unlock Interrupt
+  *            @arg DSI_IT_RR  : Regulator Ready Interrupt
+  * @retval The state of INTERRUPT (SET or RESET).
+  */
+#define __HAL_DSI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->WIER & (__INTERRUPT__))
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup DSI_Exported_Functions DSI Exported Functions
+  * @{
+  */
+/** @defgroup DSI_Group1 Initialization and Configuration functions
+  *  @brief   Initialization and Configuration functions
+  * @{
+  */
+HAL_StatusTypeDef HAL_DSI_Init(DSI_HandleTypeDef *hdsi, DSI_PLLInitTypeDef *PLLInit);
+HAL_StatusTypeDef HAL_DSI_DeInit(DSI_HandleTypeDef *hdsi);
+void HAL_DSI_MspInit(DSI_HandleTypeDef *hdsi);
+void HAL_DSI_MspDeInit(DSI_HandleTypeDef *hdsi);
+HAL_StatusTypeDef HAL_DSI_ConfigErrorMonitor(DSI_HandleTypeDef *hdsi, uint32_t ActiveErrors);
+/* Callbacks Register/UnRegister functions  ***********************************/
+#if (USE_HAL_DSI_REGISTER_CALLBACKS == 1)
+HAL_StatusTypeDef HAL_DSI_RegisterCallback(DSI_HandleTypeDef *hdsi, HAL_DSI_CallbackIDTypeDef CallbackID,
+                                           pDSI_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_DSI_UnRegisterCallback(DSI_HandleTypeDef *hdsi, HAL_DSI_CallbackIDTypeDef CallbackID);
+#endif /* USE_HAL_DSI_REGISTER_CALLBACKS */
+/**
+  * @}
+  */
+
+/** @defgroup DSI_Group2 IO operation functions
+  *  @brief    IO operation functions
+  * @{
+  */
+void HAL_DSI_IRQHandler(DSI_HandleTypeDef *hdsi);
+void HAL_DSI_TearingEffectCallback(DSI_HandleTypeDef *hdsi);
+void HAL_DSI_EndOfRefreshCallback(DSI_HandleTypeDef *hdsi);
+void HAL_DSI_ErrorCallback(DSI_HandleTypeDef *hdsi);
+/**
+  * @}
+  */
+
+/** @defgroup DSI_Group3 Peripheral Control functions
+  *  @brief    Peripheral Control functions
+  * @{
+  */
+HAL_StatusTypeDef HAL_DSI_SetGenericVCID(DSI_HandleTypeDef *hdsi, uint32_t VirtualChannelID);
+HAL_StatusTypeDef HAL_DSI_ConfigVideoMode(DSI_HandleTypeDef *hdsi, DSI_VidCfgTypeDef *VidCfg);
+HAL_StatusTypeDef HAL_DSI_ConfigAdaptedCommandMode(DSI_HandleTypeDef *hdsi, DSI_CmdCfgTypeDef *CmdCfg);
+HAL_StatusTypeDef HAL_DSI_ConfigCommand(DSI_HandleTypeDef *hdsi, DSI_LPCmdTypeDef *LPCmd);
+HAL_StatusTypeDef HAL_DSI_ConfigFlowControl(DSI_HandleTypeDef *hdsi, uint32_t FlowControl);
+HAL_StatusTypeDef HAL_DSI_ConfigPhyTimer(DSI_HandleTypeDef *hdsi, DSI_PHY_TimerTypeDef *PhyTimers);
+HAL_StatusTypeDef HAL_DSI_ConfigHostTimeouts(DSI_HandleTypeDef *hdsi, DSI_HOST_TimeoutTypeDef *HostTimeouts);
+HAL_StatusTypeDef HAL_DSI_Start(DSI_HandleTypeDef *hdsi);
+HAL_StatusTypeDef HAL_DSI_Stop(DSI_HandleTypeDef *hdsi);
+HAL_StatusTypeDef HAL_DSI_Refresh(DSI_HandleTypeDef *hdsi);
+HAL_StatusTypeDef HAL_DSI_ColorMode(DSI_HandleTypeDef *hdsi, uint32_t ColorMode);
+HAL_StatusTypeDef HAL_DSI_Shutdown(DSI_HandleTypeDef *hdsi, uint32_t Shutdown);
+HAL_StatusTypeDef HAL_DSI_ShortWrite(DSI_HandleTypeDef *hdsi,
+                                     uint32_t ChannelID,
+                                     uint32_t Mode,
+                                     uint32_t Param1,
+                                     uint32_t Param2);
+HAL_StatusTypeDef HAL_DSI_LongWrite(DSI_HandleTypeDef *hdsi,
+                                    uint32_t ChannelID,
+                                    uint32_t Mode,
+                                    uint32_t NbParams,
+                                    uint32_t Param1,
+                                    uint8_t *ParametersTable);
+HAL_StatusTypeDef HAL_DSI_Read(DSI_HandleTypeDef *hdsi,
+                               uint32_t ChannelNbr,
+                               uint8_t *Array,
+                               uint32_t Size,
+                               uint32_t Mode,
+                               uint32_t DCSCmd,
+                               uint8_t *ParametersTable);
+HAL_StatusTypeDef HAL_DSI_EnterULPMData(DSI_HandleTypeDef *hdsi);
+HAL_StatusTypeDef HAL_DSI_ExitULPMData(DSI_HandleTypeDef *hdsi);
+HAL_StatusTypeDef HAL_DSI_EnterULPM(DSI_HandleTypeDef *hdsi);
+HAL_StatusTypeDef HAL_DSI_ExitULPM(DSI_HandleTypeDef *hdsi);
+
+HAL_StatusTypeDef HAL_DSI_PatternGeneratorStart(DSI_HandleTypeDef *hdsi, uint32_t Mode, uint32_t Orientation);
+HAL_StatusTypeDef HAL_DSI_PatternGeneratorStop(DSI_HandleTypeDef *hdsi);
+
+HAL_StatusTypeDef HAL_DSI_SetSlewRateAndDelayTuning(DSI_HandleTypeDef *hdsi, uint32_t CommDelay, uint32_t Lane,
+                                                    uint32_t Value);
+HAL_StatusTypeDef HAL_DSI_SetLowPowerRXFilter(DSI_HandleTypeDef *hdsi, uint32_t Frequency);
+HAL_StatusTypeDef HAL_DSI_SetSDD(DSI_HandleTypeDef *hdsi, FunctionalState State);
+HAL_StatusTypeDef HAL_DSI_SetLanePinsConfiguration(DSI_HandleTypeDef *hdsi, uint32_t CustomLane, uint32_t Lane,
+                                                   FunctionalState State);
+HAL_StatusTypeDef HAL_DSI_SetPHYTimings(DSI_HandleTypeDef *hdsi, uint32_t Timing, FunctionalState State,
+                                        uint32_t Value);
+HAL_StatusTypeDef HAL_DSI_ForceTXStopMode(DSI_HandleTypeDef *hdsi, uint32_t Lane, FunctionalState State);
+HAL_StatusTypeDef HAL_DSI_ForceRXLowPower(DSI_HandleTypeDef *hdsi, FunctionalState State);
+HAL_StatusTypeDef HAL_DSI_ForceDataLanesInRX(DSI_HandleTypeDef *hdsi, FunctionalState State);
+HAL_StatusTypeDef HAL_DSI_SetPullDown(DSI_HandleTypeDef *hdsi, FunctionalState State);
+HAL_StatusTypeDef HAL_DSI_SetContentionDetectionOff(DSI_HandleTypeDef *hdsi, FunctionalState State);
+
+/**
+  * @}
+  */
+
+/** @defgroup DSI_Group4 Peripheral State and Errors functions
+  *  @brief    Peripheral State and Errors functions
+  * @{
+  */
+uint32_t HAL_DSI_GetError(DSI_HandleTypeDef *hdsi);
+HAL_DSI_StateTypeDef HAL_DSI_GetState(DSI_HandleTypeDef *hdsi);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private defines -----------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup DSI_Private_Constants DSI Private Constants
+  * @{
+  */
+#define DSI_MAX_RETURN_PKT_SIZE (0x00000037U) /*!< Maximum return packet configuration */
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup DSI_Private_Macros DSI Private Macros
+  * @{
+  */
+#define IS_DSI_PLL_NDIV(NDIV)                       ((10U <= (NDIV)) && ((NDIV) <= 125U))
+#define IS_DSI_PLL_IDF(IDF)                         (((IDF) == DSI_PLL_IN_DIV1) || \
+                                                     ((IDF) == DSI_PLL_IN_DIV2) || \
+                                                     ((IDF) == DSI_PLL_IN_DIV3) || \
+                                                     ((IDF) == DSI_PLL_IN_DIV4) || \
+                                                     ((IDF) == DSI_PLL_IN_DIV5) || \
+                                                     ((IDF) == DSI_PLL_IN_DIV6) || \
+                                                     ((IDF) == DSI_PLL_IN_DIV7))
+#define IS_DSI_PLL_ODF(ODF)                         (((ODF) == DSI_PLL_OUT_DIV1) || \
+                                                     ((ODF) == DSI_PLL_OUT_DIV2) || \
+                                                     ((ODF) == DSI_PLL_OUT_DIV4) || \
+                                                     ((ODF) == DSI_PLL_OUT_DIV8))
+#define IS_DSI_AUTO_CLKLANE_CONTROL(AutoClkLane)    (((AutoClkLane) == DSI_AUTO_CLK_LANE_CTRL_DISABLE)\
+                                                     || ((AutoClkLane) == DSI_AUTO_CLK_LANE_CTRL_ENABLE))
+#define IS_DSI_NUMBER_OF_LANES(NumberOfLanes)       (((NumberOfLanes) == DSI_ONE_DATA_LANE)\
+                                                     || ((NumberOfLanes) == DSI_TWO_DATA_LANES))
+#define IS_DSI_FLOW_CONTROL(FlowControl)            (((FlowControl) | DSI_FLOW_CONTROL_ALL) == DSI_FLOW_CONTROL_ALL)
+#define IS_DSI_COLOR_CODING(ColorCoding)            ((ColorCoding) <= 5U)
+#define IS_DSI_LOOSELY_PACKED(LooselyPacked)        (((LooselyPacked) == DSI_LOOSELY_PACKED_ENABLE)\
+                                                     || ((LooselyPacked) == DSI_LOOSELY_PACKED_DISABLE))
+#define IS_DSI_DE_POLARITY(DataEnable)              (((DataEnable) == DSI_DATA_ENABLE_ACTIVE_HIGH)\
+                                                     || ((DataEnable) == DSI_DATA_ENABLE_ACTIVE_LOW))
+#define IS_DSI_VSYNC_POLARITY(VSYNC)                (((VSYNC) == DSI_VSYNC_ACTIVE_HIGH)\
+                                                     || ((VSYNC) == DSI_VSYNC_ACTIVE_LOW))
+#define IS_DSI_HSYNC_POLARITY(HSYNC)                (((HSYNC) == DSI_HSYNC_ACTIVE_HIGH)\
+                                                     || ((HSYNC) == DSI_HSYNC_ACTIVE_LOW))
+#define IS_DSI_VIDEO_MODE_TYPE(VideoModeType)       (((VideoModeType) == DSI_VID_MODE_NB_PULSES) || \
+                                                     ((VideoModeType) == DSI_VID_MODE_NB_EVENTS) || \
+                                                     ((VideoModeType) == DSI_VID_MODE_BURST))
+#define IS_DSI_COLOR_MODE(ColorMode)                (((ColorMode) == DSI_COLOR_MODE_FULL)\
+                                                     || ((ColorMode) == DSI_COLOR_MODE_EIGHT))
+#define IS_DSI_SHUT_DOWN(ShutDown)                  (((ShutDown) == DSI_DISPLAY_ON) || ((ShutDown) == DSI_DISPLAY_OFF))
+#define IS_DSI_LP_COMMAND(LPCommand)                (((LPCommand) == DSI_LP_COMMAND_DISABLE)\
+                                                     || ((LPCommand) == DSI_LP_COMMAND_ENABLE))
+#define IS_DSI_LP_HFP(LPHFP)                        (((LPHFP) == DSI_LP_HFP_DISABLE) || ((LPHFP) == DSI_LP_HFP_ENABLE))
+#define IS_DSI_LP_HBP(LPHBP)                        (((LPHBP) == DSI_LP_HBP_DISABLE) || ((LPHBP) == DSI_LP_HBP_ENABLE))
+#define IS_DSI_LP_VACTIVE(LPVActive)                (((LPVActive) == DSI_LP_VACT_DISABLE)\
+                                                     || ((LPVActive) == DSI_LP_VACT_ENABLE))
+#define IS_DSI_LP_VFP(LPVFP)                        (((LPVFP) == DSI_LP_VFP_DISABLE) || ((LPVFP) == DSI_LP_VFP_ENABLE))
+#define IS_DSI_LP_VBP(LPVBP)                        (((LPVBP) == DSI_LP_VBP_DISABLE) || ((LPVBP) == DSI_LP_VBP_ENABLE))
+#define IS_DSI_LP_VSYNC(LPVSYNC)                    (((LPVSYNC) == DSI_LP_VSYNC_DISABLE)\
+                                                     || ((LPVSYNC) == DSI_LP_VSYNC_ENABLE))
+#define IS_DSI_FBTAA(FrameBTAAcknowledge)           (((FrameBTAAcknowledge) == DSI_FBTAA_DISABLE)\
+                                                     || ((FrameBTAAcknowledge) == DSI_FBTAA_ENABLE))
+#define IS_DSI_TE_SOURCE(TESource)                  (((TESource) == DSI_TE_DSILINK) || ((TESource) == DSI_TE_EXTERNAL))
+#define IS_DSI_TE_POLARITY(TEPolarity)              (((TEPolarity) == DSI_TE_RISING_EDGE)\
+                                                     || ((TEPolarity) == DSI_TE_FALLING_EDGE))
+#define IS_DSI_AUTOMATIC_REFRESH(AutomaticRefresh)  (((AutomaticRefresh) == DSI_AR_DISABLE)\
+                                                     || ((AutomaticRefresh) == DSI_AR_ENABLE))
+#define IS_DSI_VS_POLARITY(VSPolarity)              (((VSPolarity) == DSI_VSYNC_FALLING)\
+                                                     || ((VSPolarity) == DSI_VSYNC_RISING))
+#define IS_DSI_TE_ACK_REQUEST(TEAcknowledgeRequest) (((TEAcknowledgeRequest) == DSI_TE_ACKNOWLEDGE_DISABLE)\
+                                                     || ((TEAcknowledgeRequest) == DSI_TE_ACKNOWLEDGE_ENABLE))
+#define IS_DSI_ACK_REQUEST(AcknowledgeRequest)      (((AcknowledgeRequest) == DSI_ACKNOWLEDGE_DISABLE)\
+                                                     || ((AcknowledgeRequest) == DSI_ACKNOWLEDGE_ENABLE))
+#define IS_DSI_LP_GSW0P(LP_GSW0P)                   (((LP_GSW0P) == DSI_LP_GSW0P_DISABLE)\
+                                                     || ((LP_GSW0P) == DSI_LP_GSW0P_ENABLE))
+#define IS_DSI_LP_GSW1P(LP_GSW1P)                   (((LP_GSW1P) == DSI_LP_GSW1P_DISABLE)\
+                                                     || ((LP_GSW1P) == DSI_LP_GSW1P_ENABLE))
+#define IS_DSI_LP_GSW2P(LP_GSW2P)                   (((LP_GSW2P) == DSI_LP_GSW2P_DISABLE)\
+                                                     || ((LP_GSW2P) == DSI_LP_GSW2P_ENABLE))
+#define IS_DSI_LP_GSR0P(LP_GSR0P)                   (((LP_GSR0P) == DSI_LP_GSR0P_DISABLE)\
+                                                     || ((LP_GSR0P) == DSI_LP_GSR0P_ENABLE))
+#define IS_DSI_LP_GSR1P(LP_GSR1P)                   (((LP_GSR1P) == DSI_LP_GSR1P_DISABLE)\
+                                                     || ((LP_GSR1P) == DSI_LP_GSR1P_ENABLE))
+#define IS_DSI_LP_GSR2P(LP_GSR2P)                   (((LP_GSR2P) == DSI_LP_GSR2P_DISABLE)\
+                                                     || ((LP_GSR2P) == DSI_LP_GSR2P_ENABLE))
+#define IS_DSI_LP_GLW(LP_GLW)                       (((LP_GLW) == DSI_LP_GLW_DISABLE)\
+                                                     || ((LP_GLW) == DSI_LP_GLW_ENABLE))
+#define IS_DSI_LP_DSW0P(LP_DSW0P)                   (((LP_DSW0P) == DSI_LP_DSW0P_DISABLE)\
+                                                     || ((LP_DSW0P) == DSI_LP_DSW0P_ENABLE))
+#define IS_DSI_LP_DSW1P(LP_DSW1P)                   (((LP_DSW1P) == DSI_LP_DSW1P_DISABLE)\
+                                                     || ((LP_DSW1P) == DSI_LP_DSW1P_ENABLE))
+#define IS_DSI_LP_DSR0P(LP_DSR0P)                   (((LP_DSR0P) == DSI_LP_DSR0P_DISABLE)\
+                                                     || ((LP_DSR0P) == DSI_LP_DSR0P_ENABLE))
+#define IS_DSI_LP_DLW(LP_DLW)                       (((LP_DLW) == DSI_LP_DLW_DISABLE)\
+                                                     || ((LP_DLW) == DSI_LP_DLW_ENABLE))
+#define IS_DSI_LP_MRDP(LP_MRDP)                     (((LP_MRDP) == DSI_LP_MRDP_DISABLE)\
+                                                     || ((LP_MRDP) == DSI_LP_MRDP_ENABLE))
+#define IS_DSI_SHORT_WRITE_PACKET_TYPE(MODE)        (((MODE) == DSI_DCS_SHORT_PKT_WRITE_P0) || \
+                                                     ((MODE) == DSI_DCS_SHORT_PKT_WRITE_P1) || \
+                                                     ((MODE) == DSI_GEN_SHORT_PKT_WRITE_P0) || \
+                                                     ((MODE) == DSI_GEN_SHORT_PKT_WRITE_P1) || \
+                                                     ((MODE) == DSI_GEN_SHORT_PKT_WRITE_P2))
+#define IS_DSI_LONG_WRITE_PACKET_TYPE(MODE)         (((MODE) == DSI_DCS_LONG_PKT_WRITE) || \
+                                                     ((MODE) == DSI_GEN_LONG_PKT_WRITE))
+#define IS_DSI_READ_PACKET_TYPE(MODE)               (((MODE) == DSI_DCS_SHORT_PKT_READ) || \
+                                                     ((MODE) == DSI_GEN_SHORT_PKT_READ_P0) || \
+                                                     ((MODE) == DSI_GEN_SHORT_PKT_READ_P1) || \
+                                                     ((MODE) == DSI_GEN_SHORT_PKT_READ_P2))
+#define IS_DSI_COMMUNICATION_DELAY(CommDelay)       (((CommDelay) == DSI_SLEW_RATE_HSTX) || \
+                                                     ((CommDelay) == DSI_SLEW_RATE_LPTX) || \
+                                                     ((CommDelay) == DSI_HS_DELAY))
+#define IS_DSI_LANE_GROUP(Lane)                     (((Lane) == DSI_CLOCK_LANE) || ((Lane) == DSI_DATA_LANES))
+#define IS_DSI_CUSTOM_LANE(CustomLane)              (((CustomLane) == DSI_SWAP_LANE_PINS)\
+                                                     || ((CustomLane) == DSI_INVERT_HS_SIGNAL))
+#define IS_DSI_LANE(Lane)                           (((Lane) == DSI_CLOCK_LANE) || \
+                                                     ((Lane) == DSI_DATA_LANE0) || ((Lane) == DSI_DATA_LANE1))
+#define IS_DSI_PHY_TIMING(Timing)                   (((Timing) == DSI_TCLK_POST   ) || \
+                                                     ((Timing) == DSI_TLPX_CLK    ) || \
+                                                     ((Timing) == DSI_THS_EXIT    ) || \
+                                                     ((Timing) == DSI_TLPX_DATA   ) || \
+                                                     ((Timing) == DSI_THS_ZERO    ) || \
+                                                     ((Timing) == DSI_THS_TRAIL   ) || \
+                                                     ((Timing) == DSI_THS_PREPARE ) || \
+                                                     ((Timing) == DSI_TCLK_ZERO   ) || \
+                                                     ((Timing) == DSI_TCLK_PREPARE))
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+#endif /* DSI */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32F4xx_HAL_DSI_H */
diff --git a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h
new file mode 100644
index 0000000..a7af121
--- /dev/null
+++ b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h
@@ -0,0 +1,366 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hal_exti.h
+  * @author  MCD Application Team
+  * @brief   Header file of EXTI HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2018 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32f4xx_HAL_EXTI_H
+#define STM32f4xx_HAL_EXTI_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup EXTI EXTI
+  * @brief EXTI HAL module driver
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+
+/** @defgroup EXTI_Exported_Types EXTI Exported Types
+  * @{
+  */
+typedef enum
+{
+  HAL_EXTI_COMMON_CB_ID          = 0x00U
+} EXTI_CallbackIDTypeDef;
+
+/**
+  * @brief  EXTI Handle structure definition
+  */
+typedef struct
+{
+  uint32_t Line;                    /*!<  Exti line number */
+  void (* PendingCallback)(void);   /*!<  Exti pending callback */
+} EXTI_HandleTypeDef;
+
+/**
+  * @brief  EXTI Configuration structure definition
+  */
+typedef struct
+{
+  uint32_t Line;      /*!< The Exti line to be configured. This parameter
+                           can be a value of @ref EXTI_Line */
+  uint32_t Mode;      /*!< The Exit Mode to be configured for a core.
+                           This parameter can be a combination of @ref EXTI_Mode */
+  uint32_t Trigger;   /*!< The Exti Trigger to be configured. This parameter
+                           can be a value of @ref EXTI_Trigger */
+  uint32_t GPIOSel;   /*!< The Exti GPIO multiplexer selection to be configured.
+                           This parameter is only possible for line 0 to 15. It
+                           can be a value of @ref EXTI_GPIOSel */
+} EXTI_ConfigTypeDef;
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup EXTI_Exported_Constants EXTI Exported Constants
+  * @{
+  */
+
+/** @defgroup EXTI_Line  EXTI Line
+  * @{
+  */
+#define EXTI_LINE_0                        (EXTI_GPIO       | 0x00u)    /*!< External interrupt line 0 */
+#define EXTI_LINE_1                        (EXTI_GPIO       | 0x01u)    /*!< External interrupt line 1 */
+#define EXTI_LINE_2                        (EXTI_GPIO       | 0x02u)    /*!< External interrupt line 2 */
+#define EXTI_LINE_3                        (EXTI_GPIO       | 0x03u)    /*!< External interrupt line 3 */
+#define EXTI_LINE_4                        (EXTI_GPIO       | 0x04u)    /*!< External interrupt line 4 */
+#define EXTI_LINE_5                        (EXTI_GPIO       | 0x05u)    /*!< External interrupt line 5 */
+#define EXTI_LINE_6                        (EXTI_GPIO       | 0x06u)    /*!< External interrupt line 6 */
+#define EXTI_LINE_7                        (EXTI_GPIO       | 0x07u)    /*!< External interrupt line 7 */
+#define EXTI_LINE_8                        (EXTI_GPIO       | 0x08u)    /*!< External interrupt line 8 */
+#define EXTI_LINE_9                        (EXTI_GPIO       | 0x09u)    /*!< External interrupt line 9 */
+#define EXTI_LINE_10                       (EXTI_GPIO       | 0x0Au)    /*!< External interrupt line 10 */
+#define EXTI_LINE_11                       (EXTI_GPIO       | 0x0Bu)    /*!< External interrupt line 11 */
+#define EXTI_LINE_12                       (EXTI_GPIO       | 0x0Cu)    /*!< External interrupt line 12 */
+#define EXTI_LINE_13                       (EXTI_GPIO       | 0x0Du)    /*!< External interrupt line 13 */
+#define EXTI_LINE_14                       (EXTI_GPIO       | 0x0Eu)    /*!< External interrupt line 14 */
+#define EXTI_LINE_15                       (EXTI_GPIO       | 0x0Fu)    /*!< External interrupt line 15 */
+#define EXTI_LINE_16                       (EXTI_CONFIG     | 0x10u)    /*!< External interrupt line 16 Connected to the PVD Output */
+#define EXTI_LINE_17                       (EXTI_CONFIG     | 0x11u)    /*!< External interrupt line 17 Connected to the RTC Alarm event */
+#if defined(EXTI_IMR_IM18)
+#define EXTI_LINE_18                       (EXTI_CONFIG     | 0x12u)    /*!< External interrupt line 18 Connected to the USB OTG FS Wakeup from suspend event */
+#else
+#define EXTI_LINE_18                       (EXTI_RESERVED   | 0x12u)    /*!< No interrupt supported in this line */
+#endif /* EXTI_IMR_IM18 */
+#if defined(EXTI_IMR_IM19)
+#define EXTI_LINE_19                       (EXTI_CONFIG     | 0x13u)    /*!< External interrupt line 19 Connected to the Ethernet Wakeup event */
+#else
+#define EXTI_LINE_19                       (EXTI_RESERVED   | 0x13u)    /*!< No interrupt supported in this line */
+#endif /* EXTI_IMR_IM19 */
+#if defined(EXTI_IMR_IM20)
+#define EXTI_LINE_20                       (EXTI_CONFIG     | 0x14u)    /*!< External interrupt line 20 Connected to the USB OTG HS (configured in FS) Wakeup event  */
+#else
+#define EXTI_LINE_20                       (EXTI_RESERVED   | 0x14u)    /*!< No interrupt supported in this line */
+#endif /* EXTI_IMR_IM20 */
+#define EXTI_LINE_21                       (EXTI_CONFIG     | 0x15u)    /*!< External interrupt line 21 Connected to the RTC Tamper and Time Stamp events */
+#define EXTI_LINE_22                       (EXTI_CONFIG     | 0x16u)    /*!< External interrupt line 22 Connected to the RTC Wakeup event */
+#if defined(EXTI_IMR_IM23)
+#define EXTI_LINE_23                       (EXTI_CONFIG     | 0x17u)    /*!< External interrupt line 23 Connected to the LPTIM1 asynchronous event */
+#endif /* EXTI_IMR_IM23 */
+
+/**
+  * @}
+  */
+
+/** @defgroup EXTI_Mode  EXTI Mode
+  * @{
+  */
+#define EXTI_MODE_NONE                      0x00000000u
+#define EXTI_MODE_INTERRUPT                 0x00000001u
+#define EXTI_MODE_EVENT                     0x00000002u
+/**
+  * @}
+  */
+
+/** @defgroup EXTI_Trigger  EXTI Trigger
+  * @{
+  */
+
+#define EXTI_TRIGGER_NONE                   0x00000000u
+#define EXTI_TRIGGER_RISING                 0x00000001u
+#define EXTI_TRIGGER_FALLING                0x00000002u
+#define EXTI_TRIGGER_RISING_FALLING         (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING)
+/**
+  * @}
+  */
+
+/** @defgroup EXTI_GPIOSel  EXTI GPIOSel
+  * @brief
+  * @{
+  */
+#define EXTI_GPIOA                          0x00000000u
+#define EXTI_GPIOB                          0x00000001u
+#define EXTI_GPIOC                          0x00000002u
+#if defined (GPIOD)
+#define EXTI_GPIOD                          0x00000003u
+#endif /* GPIOD */
+#if defined (GPIOE)
+#define EXTI_GPIOE                          0x00000004u
+#endif /* GPIOE */
+#if defined (GPIOF)
+#define EXTI_GPIOF                          0x00000005u
+#endif /* GPIOF */
+#if defined (GPIOG)
+#define EXTI_GPIOG                          0x00000006u
+#endif /* GPIOG */
+#if defined (GPIOH)
+#define EXTI_GPIOH                          0x00000007u
+#endif /* GPIOH */
+#if defined (GPIOI)
+#define EXTI_GPIOI                          0x00000008u
+#endif /* GPIOI */
+#if defined (GPIOJ)
+#define EXTI_GPIOJ                          0x00000009u
+#endif /* GPIOJ */
+#if defined (GPIOK)
+#define EXTI_GPIOK                          0x0000000Au
+#endif /* GPIOK */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup EXTI_Exported_Macros EXTI Exported Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Private constants --------------------------------------------------------*/
+/** @defgroup EXTI_Private_Constants EXTI Private Constants
+  * @{
+  */
+/**
+  * @brief  EXTI Line property definition
+  */
+#define EXTI_PROPERTY_SHIFT                  24u
+#define EXTI_CONFIG                         (0x02uL << EXTI_PROPERTY_SHIFT)
+#define EXTI_GPIO                           ((0x04uL << EXTI_PROPERTY_SHIFT) | EXTI_CONFIG)
+#define EXTI_RESERVED                       (0x08uL << EXTI_PROPERTY_SHIFT)
+#define EXTI_PROPERTY_MASK                  (EXTI_CONFIG | EXTI_GPIO)
+
+/**
+  * @brief  EXTI bit usage
+  */
+#define EXTI_PIN_MASK                       0x0000001Fu
+
+/**
+  * @brief  EXTI Mask for interrupt & event mode
+  */
+#define EXTI_MODE_MASK                      (EXTI_MODE_EVENT | EXTI_MODE_INTERRUPT)
+
+/**
+  * @brief  EXTI Mask for trigger possibilities
+  */
+#define EXTI_TRIGGER_MASK                   (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING)
+
+/**
+  * @brief  EXTI Line number
+  */
+#if defined(EXTI_IMR_IM23)
+#define EXTI_LINE_NB                        24UL
+#else
+#define EXTI_LINE_NB                        23UL
+#endif /* EXTI_IMR_IM23 */
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup EXTI_Private_Macros EXTI Private Macros
+  * @{
+  */
+#define IS_EXTI_LINE(__EXTI_LINE__)          ((((__EXTI_LINE__) & ~(EXTI_PROPERTY_MASK | EXTI_PIN_MASK)) == 0x00u) && \
+                                             ((((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_CONFIG)              || \
+                                              (((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_GPIO))               && \
+                                              (((__EXTI_LINE__) & EXTI_PIN_MASK) < EXTI_LINE_NB))
+
+#define IS_EXTI_MODE(__EXTI_LINE__)          ((((__EXTI_LINE__) & EXTI_MODE_MASK) != 0x00u) && \
+                                              (((__EXTI_LINE__) & ~EXTI_MODE_MASK) == 0x00u))
+
+#define IS_EXTI_TRIGGER(__EXTI_LINE__)       (((__EXTI_LINE__)  & ~EXTI_TRIGGER_MASK) == 0x00u)
+
+#define IS_EXTI_PENDING_EDGE(__EXTI_LINE__)  ((__EXTI_LINE__) == EXTI_TRIGGER_RISING_FALLING)
+
+#define IS_EXTI_CONFIG_LINE(__EXTI_LINE__)   (((__EXTI_LINE__) & EXTI_CONFIG) != 0x00u)
+
+#if !defined (GPIOD)
+#define IS_EXTI_GPIO_PORT(__PORT__)     (((__PORT__) == EXTI_GPIOA) || \
+                                         ((__PORT__) == EXTI_GPIOB) || \
+                                         ((__PORT__) == EXTI_GPIOC) || \
+                                         ((__PORT__) == EXTI_GPIOH))
+#elif !defined (GPIOE)
+#define IS_EXTI_GPIO_PORT(__PORT__)     (((__PORT__) == EXTI_GPIOA) || \
+                                         ((__PORT__) == EXTI_GPIOB) || \
+                                         ((__PORT__) == EXTI_GPIOC) || \
+                                         ((__PORT__) == EXTI_GPIOD) || \
+                                         ((__PORT__) == EXTI_GPIOH))
+#elif !defined (GPIOF)
+#define IS_EXTI_GPIO_PORT(__PORT__)     (((__PORT__) == EXTI_GPIOA) || \
+                                         ((__PORT__) == EXTI_GPIOB) || \
+                                         ((__PORT__) == EXTI_GPIOC) || \
+                                         ((__PORT__) == EXTI_GPIOD) || \
+                                         ((__PORT__) == EXTI_GPIOE) || \
+                                         ((__PORT__) == EXTI_GPIOH))
+#elif !defined (GPIOI)
+#define IS_EXTI_GPIO_PORT(__PORT__)     (((__PORT__) == EXTI_GPIOA) || \
+                                         ((__PORT__) == EXTI_GPIOB) || \
+                                         ((__PORT__) == EXTI_GPIOC) || \
+                                         ((__PORT__) == EXTI_GPIOD) || \
+                                         ((__PORT__) == EXTI_GPIOE) || \
+                                         ((__PORT__) == EXTI_GPIOF) || \
+                                         ((__PORT__) == EXTI_GPIOG) || \
+                                         ((__PORT__) == EXTI_GPIOH))
+#elif !defined (GPIOJ)
+#define IS_EXTI_GPIO_PORT(__PORT__)     (((__PORT__) == EXTI_GPIOA) || \
+                                         ((__PORT__) == EXTI_GPIOB) || \
+                                         ((__PORT__) == EXTI_GPIOC) || \
+                                         ((__PORT__) == EXTI_GPIOD) || \
+                                         ((__PORT__) == EXTI_GPIOE) || \
+                                         ((__PORT__) == EXTI_GPIOF) || \
+                                         ((__PORT__) == EXTI_GPIOG) || \
+                                         ((__PORT__) == EXTI_GPIOH) || \
+                                         ((__PORT__) == EXTI_GPIOI))
+#else
+#define IS_EXTI_GPIO_PORT(__PORT__)     (((__PORT__) == EXTI_GPIOA) || \
+                                         ((__PORT__) == EXTI_GPIOB) || \
+                                         ((__PORT__) == EXTI_GPIOC) || \
+                                         ((__PORT__) == EXTI_GPIOD) || \
+                                         ((__PORT__) == EXTI_GPIOE) || \
+                                         ((__PORT__) == EXTI_GPIOF) || \
+                                         ((__PORT__) == EXTI_GPIOG) || \
+                                         ((__PORT__) == EXTI_GPIOH) || \
+                                         ((__PORT__) == EXTI_GPIOI) || \
+                                         ((__PORT__) == EXTI_GPIOJ) || \
+                                         ((__PORT__) == EXTI_GPIOK))
+#endif /* GPIOD */
+
+#define IS_EXTI_GPIO_PIN(__PIN__)       ((__PIN__) < 16U)
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup EXTI_Exported_Functions EXTI Exported Functions
+  * @brief    EXTI Exported Functions
+  * @{
+  */
+
+/** @defgroup EXTI_Exported_Functions_Group1 Configuration functions
+  * @brief    Configuration functions
+  * @{
+  */
+/* Configuration functions ****************************************************/
+HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig);
+HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig);
+HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(EXTI_HandleTypeDef *hexti);
+HAL_StatusTypeDef HAL_EXTI_RegisterCallback(EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef CallbackID, void (*pPendingCbfn)(void));
+HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLine);
+/**
+  * @}
+  */
+
+/** @defgroup EXTI_Exported_Functions_Group2 IO operation functions
+  * @brief    IO operation functions
+  * @{
+  */
+/* IO operation functions *****************************************************/
+void HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *hexti);
+uint32_t HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge);
+void HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge);
+void HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32f4xx_HAL_EXTI_H */
+
diff --git a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h
new file mode 100644
index 0000000..a047e82
--- /dev/null
+++ b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h
@@ -0,0 +1,425 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hal_flash.h
+  * @author  MCD Application Team
+  * @brief   Header file of FLASH HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file in
+  * the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  ******************************************************************************
+  */ 
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_FLASH_H
+#define __STM32F4xx_HAL_FLASH_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup FLASH
+  * @{
+  */ 
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup FLASH_Exported_Types FLASH Exported Types
+  * @{
+  */
+ 
+/**
+  * @brief  FLASH Procedure structure definition
+  */
+typedef enum 
+{
+  FLASH_PROC_NONE = 0U, 
+  FLASH_PROC_SECTERASE,
+  FLASH_PROC_MASSERASE,
+  FLASH_PROC_PROGRAM
+} FLASH_ProcedureTypeDef;
+
+/** 
+  * @brief  FLASH handle Structure definition  
+  */
+typedef struct
+{
+  __IO FLASH_ProcedureTypeDef ProcedureOnGoing;   /*Internal variable to indicate which procedure is ongoing or not in IT context*/
+  
+  __IO uint32_t               NbSectorsToErase;   /*Internal variable to save the remaining sectors to erase in IT context*/
+  
+  __IO uint8_t                VoltageForErase;    /*Internal variable to provide voltage range selected by user in IT context*/
+  
+  __IO uint32_t               Sector;             /*Internal variable to define the current sector which is erasing*/
+  
+  __IO uint32_t               Bank;               /*Internal variable to save current bank selected during mass erase*/
+  
+  __IO uint32_t               Address;            /*Internal variable to save address selected for program*/
+  
+  HAL_LockTypeDef             Lock;               /* FLASH locking object                */
+
+  __IO uint32_t               ErrorCode;          /* FLASH error code                    */
+
+}FLASH_ProcessTypeDef;
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup FLASH_Exported_Constants FLASH Exported Constants
+  * @{
+  */  
+/** @defgroup FLASH_Error_Code FLASH Error Code
+  * @brief    FLASH Error Code 
+  * @{
+  */ 
+#define HAL_FLASH_ERROR_NONE         0x00000000U    /*!< No error                      */
+#define HAL_FLASH_ERROR_RD           0x00000001U    /*!< Read Protection error         */
+#define HAL_FLASH_ERROR_PGS          0x00000002U    /*!< Programming Sequence error    */
+#define HAL_FLASH_ERROR_PGP          0x00000004U    /*!< Programming Parallelism error */
+#define HAL_FLASH_ERROR_PGA          0x00000008U    /*!< Programming Alignment error   */
+#define HAL_FLASH_ERROR_WRP          0x00000010U    /*!< Write protection error        */
+#define HAL_FLASH_ERROR_OPERATION    0x00000020U    /*!< Operation Error               */
+/**
+  * @}
+  */
+  
+/** @defgroup FLASH_Type_Program FLASH Type Program
+  * @{
+  */ 
+#define FLASH_TYPEPROGRAM_BYTE        0x00000000U  /*!< Program byte (8-bit) at a specified address           */
+#define FLASH_TYPEPROGRAM_HALFWORD    0x00000001U  /*!< Program a half-word (16-bit) at a specified address   */
+#define FLASH_TYPEPROGRAM_WORD        0x00000002U  /*!< Program a word (32-bit) at a specified address        */
+#define FLASH_TYPEPROGRAM_DOUBLEWORD  0x00000003U  /*!< Program a double word (64-bit) at a specified address */
+/**
+  * @}
+  */
+
+/** @defgroup FLASH_Flag_definition FLASH Flag definition
+  * @brief Flag definition
+  * @{
+  */ 
+#define FLASH_FLAG_EOP                 FLASH_SR_EOP            /*!< FLASH End of Operation flag               */
+#define FLASH_FLAG_OPERR               FLASH_SR_SOP            /*!< FLASH operation Error flag                */
+#define FLASH_FLAG_WRPERR              FLASH_SR_WRPERR         /*!< FLASH Write protected error flag          */
+#define FLASH_FLAG_PGAERR              FLASH_SR_PGAERR         /*!< FLASH Programming Alignment error flag    */
+#define FLASH_FLAG_PGPERR              FLASH_SR_PGPERR         /*!< FLASH Programming Parallelism error flag  */
+#define FLASH_FLAG_PGSERR              FLASH_SR_PGSERR         /*!< FLASH Programming Sequence error flag     */
+#if defined(FLASH_SR_RDERR)
+#define FLASH_FLAG_RDERR               FLASH_SR_RDERR          /*!< Read Protection error flag (PCROP)        */
+#endif /* FLASH_SR_RDERR */
+#define FLASH_FLAG_BSY                 FLASH_SR_BSY            /*!< FLASH Busy flag                           */ 
+/**
+  * @}
+  */
+  
+/** @defgroup FLASH_Interrupt_definition FLASH Interrupt definition
+  * @brief FLASH Interrupt definition
+  * @{
+  */ 
+#define FLASH_IT_EOP                   FLASH_CR_EOPIE          /*!< End of FLASH Operation Interrupt source */
+#define FLASH_IT_ERR                   0x02000000U             /*!< Error Interrupt source                  */
+/**
+  * @}
+  */  
+
+/** @defgroup FLASH_Program_Parallelism FLASH Program Parallelism
+  * @{
+  */
+#define FLASH_PSIZE_BYTE           0x00000000U
+#define FLASH_PSIZE_HALF_WORD      0x00000100U
+#define FLASH_PSIZE_WORD           0x00000200U
+#define FLASH_PSIZE_DOUBLE_WORD    0x00000300U
+#define CR_PSIZE_MASK              0xFFFFFCFFU
+/**
+  * @}
+  */ 
+
+/** @defgroup FLASH_Keys FLASH Keys
+  * @{
+  */ 
+#define RDP_KEY                  ((uint16_t)0x00A5)
+#define FLASH_KEY1               0x45670123U
+#define FLASH_KEY2               0xCDEF89ABU
+#define FLASH_OPT_KEY1           0x08192A3BU
+#define FLASH_OPT_KEY2           0x4C5D6E7FU
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+  
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup FLASH_Exported_Macros FLASH Exported Macros
+  * @{
+  */
+/**
+  * @brief  Set the FLASH Latency.
+  * @param  __LATENCY__ FLASH Latency
+  *         The value of this parameter depend on device used within the same series
+  * @retval none
+  */ 
+#define __HAL_FLASH_SET_LATENCY(__LATENCY__) (*(__IO uint8_t *)ACR_BYTE0_ADDRESS = (uint8_t)(__LATENCY__))
+
+/**
+  * @brief  Get the FLASH Latency.
+  * @retval FLASH Latency
+  *          The value of this parameter depend on device used within the same series
+  */ 
+#define __HAL_FLASH_GET_LATENCY()     (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY))
+
+/**
+  * @brief  Enable the FLASH prefetch buffer.
+  * @retval none
+  */ 
+#define __HAL_FLASH_PREFETCH_BUFFER_ENABLE()  (FLASH->ACR |= FLASH_ACR_PRFTEN)
+
+/**
+  * @brief  Disable the FLASH prefetch buffer.
+  * @retval none
+  */ 
+#define __HAL_FLASH_PREFETCH_BUFFER_DISABLE()   (FLASH->ACR &= (~FLASH_ACR_PRFTEN))
+
+/**
+  * @brief  Enable the FLASH instruction cache.
+  * @retval none
+  */ 
+#define __HAL_FLASH_INSTRUCTION_CACHE_ENABLE()  (FLASH->ACR |= FLASH_ACR_ICEN)
+
+/**
+  * @brief  Disable the FLASH instruction cache.
+  * @retval none
+  */ 
+#define __HAL_FLASH_INSTRUCTION_CACHE_DISABLE()   (FLASH->ACR &= (~FLASH_ACR_ICEN))
+
+/**
+  * @brief  Enable the FLASH data cache.
+  * @retval none
+  */ 
+#define __HAL_FLASH_DATA_CACHE_ENABLE()  (FLASH->ACR |= FLASH_ACR_DCEN)
+
+/**
+  * @brief  Disable the FLASH data cache.
+  * @retval none
+  */ 
+#define __HAL_FLASH_DATA_CACHE_DISABLE()   (FLASH->ACR &= (~FLASH_ACR_DCEN))
+
+/**
+  * @brief  Resets the FLASH instruction Cache.
+  * @note   This function must be used only when the Instruction Cache is disabled.  
+  * @retval None
+  */
+#define __HAL_FLASH_INSTRUCTION_CACHE_RESET() do {FLASH->ACR |= FLASH_ACR_ICRST;  \
+                                                  FLASH->ACR &= ~FLASH_ACR_ICRST; \
+                                                 }while(0U)
+
+/**
+  * @brief  Resets the FLASH data Cache.
+  * @note   This function must be used only when the data Cache is disabled.  
+  * @retval None
+  */
+#define __HAL_FLASH_DATA_CACHE_RESET() do {FLASH->ACR |= FLASH_ACR_DCRST;  \
+                                           FLASH->ACR &= ~FLASH_ACR_DCRST; \
+                                          }while(0U)
+/**
+  * @brief  Enable the specified FLASH interrupt.
+  * @param  __INTERRUPT__  FLASH interrupt 
+  *         This parameter can be any combination of the following values:
+  *     @arg FLASH_IT_EOP: End of FLASH Operation Interrupt
+  *     @arg FLASH_IT_ERR: Error Interrupt    
+  * @retval none
+  */  
+#define __HAL_FLASH_ENABLE_IT(__INTERRUPT__)  (FLASH->CR |= (__INTERRUPT__))
+
+/**
+  * @brief  Disable the specified FLASH interrupt.
+  * @param  __INTERRUPT__  FLASH interrupt 
+  *         This parameter can be any combination of the following values:
+  *     @arg FLASH_IT_EOP: End of FLASH Operation Interrupt
+  *     @arg FLASH_IT_ERR: Error Interrupt    
+  * @retval none
+  */  
+#define __HAL_FLASH_DISABLE_IT(__INTERRUPT__)  (FLASH->CR &= ~(uint32_t)(__INTERRUPT__))
+
+/**
+  * @brief  Get the specified FLASH flag status. 
+  * @param  __FLAG__ specifies the FLASH flags to check.
+  *          This parameter can be any combination of the following values:
+  *            @arg FLASH_FLAG_EOP   : FLASH End of Operation flag 
+  *            @arg FLASH_FLAG_OPERR : FLASH operation Error flag 
+  *            @arg FLASH_FLAG_WRPERR: FLASH Write protected error flag 
+  *            @arg FLASH_FLAG_PGAERR: FLASH Programming Alignment error flag
+  *            @arg FLASH_FLAG_PGPERR: FLASH Programming Parallelism error flag
+  *            @arg FLASH_FLAG_PGSERR: FLASH Programming Sequence error flag
+  *            @arg FLASH_FLAG_RDERR : FLASH Read Protection error flag (PCROP) (*)
+  *            @arg FLASH_FLAG_BSY   : FLASH Busy flag
+  *           (*) FLASH_FLAG_RDERR is not available for STM32F405xx/407xx/415xx/417xx devices                             
+  * @retval The new state of __FLAG__ (SET or RESET).
+  */
+#define __HAL_FLASH_GET_FLAG(__FLAG__)   ((FLASH->SR & (__FLAG__)))
+
+/**
+  * @brief  Clear the specified FLASH flags.
+  * @param  __FLAG__ specifies the FLASH flags to clear.
+  *          This parameter can be any combination of the following values:
+  *            @arg FLASH_FLAG_EOP   : FLASH End of Operation flag 
+  *            @arg FLASH_FLAG_OPERR : FLASH operation Error flag 
+  *            @arg FLASH_FLAG_WRPERR: FLASH Write protected error flag 
+  *            @arg FLASH_FLAG_PGAERR: FLASH Programming Alignment error flag 
+  *            @arg FLASH_FLAG_PGPERR: FLASH Programming Parallelism error flag
+  *            @arg FLASH_FLAG_PGSERR: FLASH Programming Sequence error flag
+  *            @arg FLASH_FLAG_RDERR : FLASH Read Protection error flag (PCROP) (*)
+  *           (*) FLASH_FLAG_RDERR is not available for STM32F405xx/407xx/415xx/417xx devices   
+  * @retval none
+  */
+#define __HAL_FLASH_CLEAR_FLAG(__FLAG__)   (FLASH->SR = (__FLAG__))
+/**
+  * @}
+  */
+
+/* Include FLASH HAL Extension module */
+#include "stm32f4xx_hal_flash_ex.h"
+#include "stm32f4xx_hal_flash_ramfunc.h"
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup FLASH_Exported_Functions
+  * @{
+  */
+/** @addtogroup FLASH_Exported_Functions_Group1
+  * @{
+  */
+/* Program operation functions  ***********************************************/
+HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data);
+HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data);
+/* FLASH IRQ handler method */
+void HAL_FLASH_IRQHandler(void);
+/* Callbacks in non blocking modes */ 
+void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue);
+void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue);
+/**
+  * @}
+  */
+
+/** @addtogroup FLASH_Exported_Functions_Group2
+  * @{
+  */
+/* Peripheral Control functions  **********************************************/
+HAL_StatusTypeDef HAL_FLASH_Unlock(void);
+HAL_StatusTypeDef HAL_FLASH_Lock(void);
+HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void);
+HAL_StatusTypeDef HAL_FLASH_OB_Lock(void);
+/* Option bytes control */
+HAL_StatusTypeDef HAL_FLASH_OB_Launch(void);
+/**
+  * @}
+  */
+
+/** @addtogroup FLASH_Exported_Functions_Group3
+  * @{
+  */
+/* Peripheral State functions  ************************************************/
+uint32_t HAL_FLASH_GetError(void);
+HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout);
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */ 
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup FLASH_Private_Variables FLASH Private Variables
+  * @{
+  */
+
+/**
+  * @}
+  */
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup FLASH_Private_Constants FLASH Private Constants
+  * @{
+  */
+
+/** 
+  * @brief   ACR register byte 0 (Bits[7:0]) base address  
+  */ 
+#define ACR_BYTE0_ADDRESS           0x40023C00U 
+/** 
+  * @brief   OPTCR register byte 0 (Bits[7:0]) base address  
+  */ 
+#define OPTCR_BYTE0_ADDRESS         0x40023C14U
+/** 
+  * @brief   OPTCR register byte 1 (Bits[15:8]) base address  
+  */ 
+#define OPTCR_BYTE1_ADDRESS         0x40023C15U
+/** 
+  * @brief   OPTCR register byte 2 (Bits[23:16]) base address  
+  */ 
+#define OPTCR_BYTE2_ADDRESS         0x40023C16U
+/** 
+  * @brief   OPTCR register byte 3 (Bits[31:24]) base address  
+  */ 
+#define OPTCR_BYTE3_ADDRESS         0x40023C17U
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup FLASH_Private_Macros FLASH Private Macros
+  * @{
+  */
+
+/** @defgroup FLASH_IS_FLASH_Definitions FLASH Private macros to check input parameters
+  * @{
+  */
+#define IS_FLASH_TYPEPROGRAM(VALUE)(((VALUE) == FLASH_TYPEPROGRAM_BYTE) || \
+                                    ((VALUE) == FLASH_TYPEPROGRAM_HALFWORD) || \
+                                    ((VALUE) == FLASH_TYPEPROGRAM_WORD) || \
+                                    ((VALUE) == FLASH_TYPEPROGRAM_DOUBLEWORD))  
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup FLASH_Private_Functions FLASH Private Functions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_FLASH_H */
+
diff --git a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h
new file mode 100644
index 0000000..908fd5e
--- /dev/null
+++ b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h
@@ -0,0 +1,1063 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hal_flash_ex.h
+  * @author  MCD Application Team
+  * @brief   Header file of FLASH HAL Extension module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file in
+  * the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  ******************************************************************************
+  */ 
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_FLASH_EX_H
+#define __STM32F4xx_HAL_FLASH_EX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup FLASHEx
+  * @{
+  */ 
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup FLASHEx_Exported_Types FLASH Exported Types
+  * @{
+  */
+
+/**
+  * @brief  FLASH Erase structure definition
+  */
+typedef struct
+{
+  uint32_t TypeErase;   /*!< Mass erase or sector Erase.
+                             This parameter can be a value of @ref FLASHEx_Type_Erase */
+
+  uint32_t Banks;       /*!< Select banks to erase when Mass erase is enabled.
+                             This parameter must be a value of @ref FLASHEx_Banks */
+
+  uint32_t Sector;      /*!< Initial FLASH sector to erase when Mass erase is disabled
+                             This parameter must be a value of @ref FLASHEx_Sectors */
+
+  uint32_t NbSectors;   /*!< Number of sectors to be erased.
+                             This parameter must be a value between 1 and (max number of sectors - value of Initial sector)*/
+
+  uint32_t VoltageRange;/*!< The device voltage range which defines the erase parallelism
+                             This parameter must be a value of @ref FLASHEx_Voltage_Range */
+
+} FLASH_EraseInitTypeDef;
+
+/**
+  * @brief  FLASH Option Bytes Program structure definition
+  */
+typedef struct
+{
+  uint32_t OptionType;   /*!< Option byte to be configured.
+                              This parameter can be a value of @ref FLASHEx_Option_Type */
+
+  uint32_t WRPState;     /*!< Write protection activation or deactivation.
+                              This parameter can be a value of @ref FLASHEx_WRP_State */
+
+  uint32_t WRPSector;         /*!< Specifies the sector(s) to be write protected.
+                              The value of this parameter depend on device used within the same series */
+
+  uint32_t Banks;        /*!< Select banks for WRP activation/deactivation of all sectors.
+                              This parameter must be a value of @ref FLASHEx_Banks */        
+
+  uint32_t RDPLevel;     /*!< Set the read protection level.
+                              This parameter can be a value of @ref FLASHEx_Option_Bytes_Read_Protection */
+
+  uint32_t BORLevel;     /*!< Set the BOR Level.
+                              This parameter can be a value of @ref FLASHEx_BOR_Reset_Level */
+
+  uint8_t  USERConfig;   /*!< Program the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY. */
+
+} FLASH_OBProgramInitTypeDef;
+
+/**
+  * @brief  FLASH Advanced Option Bytes Program structure definition
+  */
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
+    defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) ||\
+    defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F469xx) ||\
+    defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) ||\
+    defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
+typedef struct
+{
+  uint32_t OptionType;     /*!< Option byte to be configured for extension.
+                                This parameter can be a value of @ref FLASHEx_Advanced_Option_Type */
+
+  uint32_t PCROPState;     /*!< PCROP activation or deactivation.
+                                This parameter can be a value of @ref FLASHEx_PCROP_State */
+
+#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F412Zx) ||\
+    defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
+  uint16_t Sectors;        /*!< specifies the sector(s) set for PCROP.
+                                This parameter can be a value of @ref FLASHEx_Option_Bytes_PC_ReadWrite_Protection */
+#endif /* STM32F401xC || STM32F401xE || STM32F410xx || STM32F411xE || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx ||\
+          STM32F412Cx || STM32F413xx || STM32F423xx */
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
+  uint32_t Banks;          /*!< Select banks for PCROP activation/deactivation of all sectors.
+                                This parameter must be a value of @ref FLASHEx_Banks */
+
+  uint16_t SectorsBank1;   /*!< Specifies the sector(s) set for PCROP for Bank1.
+                                This parameter can be a value of @ref FLASHEx_Option_Bytes_PC_ReadWrite_Protection */
+
+  uint16_t SectorsBank2;   /*!< Specifies the sector(s) set for PCROP for Bank2.
+                                This parameter can be a value of @ref FLASHEx_Option_Bytes_PC_ReadWrite_Protection */
+
+  uint8_t BootConfig;      /*!< Specifies Option bytes for boot config.
+                                This parameter can be a value of @ref FLASHEx_Dual_Boot */
+
+#endif /*STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
+}FLASH_AdvOBProgramInitTypeDef;
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F401xC || STM32F401xE || STM32F410xx || STM32F411xE || STM32F446xx ||
+          STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup FLASHEx_Exported_Constants FLASH Exported Constants
+  * @{
+  */
+
+/** @defgroup FLASHEx_Type_Erase FLASH Type Erase
+  * @{
+  */ 
+#define FLASH_TYPEERASE_SECTORS         0x00000000U  /*!< Sectors erase only          */
+#define FLASH_TYPEERASE_MASSERASE       0x00000001U  /*!< Flash Mass erase activation */
+/**
+  * @}
+  */
+  
+/** @defgroup FLASHEx_Voltage_Range FLASH Voltage Range
+  * @{
+  */ 
+#define FLASH_VOLTAGE_RANGE_1        0x00000000U  /*!< Device operating range: 1.8V to 2.1V                */
+#define FLASH_VOLTAGE_RANGE_2        0x00000001U  /*!< Device operating range: 2.1V to 2.7V                */
+#define FLASH_VOLTAGE_RANGE_3        0x00000002U  /*!< Device operating range: 2.7V to 3.6V                */
+#define FLASH_VOLTAGE_RANGE_4        0x00000003U  /*!< Device operating range: 2.7V to 3.6V + External Vpp */
+/**
+  * @}
+  */
+  
+/** @defgroup FLASHEx_WRP_State FLASH WRP State
+  * @{
+  */ 
+#define OB_WRPSTATE_DISABLE       0x00000000U  /*!< Disable the write protection of the desired bank 1 sectors */
+#define OB_WRPSTATE_ENABLE        0x00000001U  /*!< Enable the write protection of the desired bank 1 sectors  */
+/**
+  * @}
+  */
+  
+/** @defgroup FLASHEx_Option_Type FLASH Option Type
+  * @{
+  */ 
+#define OPTIONBYTE_WRP        0x00000001U  /*!< WRP option byte configuration  */
+#define OPTIONBYTE_RDP        0x00000002U  /*!< RDP option byte configuration  */
+#define OPTIONBYTE_USER       0x00000004U  /*!< USER option byte configuration */
+#define OPTIONBYTE_BOR        0x00000008U  /*!< BOR option byte configuration  */
+/**
+  * @}
+  */
+  
+/** @defgroup FLASHEx_Option_Bytes_Read_Protection FLASH Option Bytes Read Protection
+  * @{
+  */
+#define OB_RDP_LEVEL_0   ((uint8_t)0xAA)
+#define OB_RDP_LEVEL_1   ((uint8_t)0x55)
+#define OB_RDP_LEVEL_2   ((uint8_t)0xCC) /*!< Warning: When enabling read protection level 2 
+                                              it s no more possible to go back to level 1 or 0 */
+/**
+  * @}
+  */ 
+  
+/** @defgroup FLASHEx_Option_Bytes_IWatchdog FLASH Option Bytes IWatchdog
+  * @{
+  */ 
+#define OB_IWDG_SW                     ((uint8_t)0x20)  /*!< Software IWDG selected */
+#define OB_IWDG_HW                     ((uint8_t)0x00)  /*!< Hardware IWDG selected */
+/**
+  * @}
+  */ 
+  
+/** @defgroup FLASHEx_Option_Bytes_nRST_STOP FLASH Option Bytes nRST_STOP
+  * @{
+  */ 
+#define OB_STOP_NO_RST                 ((uint8_t)0x40) /*!< No reset generated when entering in STOP */
+#define OB_STOP_RST                    ((uint8_t)0x00) /*!< Reset generated when entering in STOP    */
+/**
+  * @}
+  */ 
+
+
+/** @defgroup FLASHEx_Option_Bytes_nRST_STDBY FLASH Option Bytes nRST_STDBY
+  * @{
+  */ 
+#define OB_STDBY_NO_RST                ((uint8_t)0x80) /*!< No reset generated when entering in STANDBY */
+#define OB_STDBY_RST                   ((uint8_t)0x00) /*!< Reset generated when entering in STANDBY    */
+/**
+  * @}
+  */    
+
+/** @defgroup FLASHEx_BOR_Reset_Level FLASH BOR Reset Level
+  * @{
+  */  
+#define OB_BOR_LEVEL3          ((uint8_t)0x00)  /*!< Supply voltage ranges from 2.70 to 3.60 V */
+#define OB_BOR_LEVEL2          ((uint8_t)0x04)  /*!< Supply voltage ranges from 2.40 to 2.70 V */
+#define OB_BOR_LEVEL1          ((uint8_t)0x08)  /*!< Supply voltage ranges from 2.10 to 2.40 V */
+#define OB_BOR_OFF             ((uint8_t)0x0C)  /*!< Supply voltage ranges from 1.62 to 2.10 V */
+/**
+  * @}
+  */
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
+    defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) ||\
+    defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F469xx) ||\
+    defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) ||\
+    defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
+/** @defgroup FLASHEx_PCROP_State FLASH PCROP State
+  * @{
+  */ 
+#define OB_PCROP_STATE_DISABLE       0x00000000U  /*!< Disable PCROP */
+#define OB_PCROP_STATE_ENABLE        0x00000001U  /*!< Enable PCROP  */
+/**
+  * @}
+  */
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F401xC || STM32F401xE ||\
+          STM32F410xx || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx ||\
+          STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */
+
+/** @defgroup FLASHEx_Advanced_Option_Type FLASH Advanced Option Type
+  * @{
+  */ 
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
+    defined(STM32F469xx) || defined(STM32F479xx)
+#define OPTIONBYTE_PCROP        0x00000001U  /*!< PCROP option byte configuration      */
+#define OPTIONBYTE_BOOTCONFIG   0x00000002U  /*!< BOOTConfig option byte configuration */
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
+
+#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) ||\
+    defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F412Zx) ||\
+    defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) ||\
+    defined(STM32F423xx)
+#define OPTIONBYTE_PCROP        0x00000001U  /*!<PCROP option byte configuration */
+#endif /* STM32F401xC || STM32F401xE || STM32F410xx || STM32F411xE || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx ||
+          STM32F413xx || STM32F423xx */
+/**
+  * @}
+  */
+
+/** @defgroup FLASH_Latency FLASH Latency
+  * @{
+  */
+/*------------------------- STM32F42xxx/STM32F43xxx/STM32F446xx/STM32F469xx/STM32F479xx ----------------------*/  
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) ||\
+    defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
+#define FLASH_LATENCY_0                FLASH_ACR_LATENCY_0WS   /*!< FLASH Zero Latency cycle      */
+#define FLASH_LATENCY_1                FLASH_ACR_LATENCY_1WS   /*!< FLASH One Latency cycle       */
+#define FLASH_LATENCY_2                FLASH_ACR_LATENCY_2WS   /*!< FLASH Two Latency cycles      */
+#define FLASH_LATENCY_3                FLASH_ACR_LATENCY_3WS   /*!< FLASH Three Latency cycles    */
+#define FLASH_LATENCY_4                FLASH_ACR_LATENCY_4WS   /*!< FLASH Four Latency cycles     */
+#define FLASH_LATENCY_5                FLASH_ACR_LATENCY_5WS   /*!< FLASH Five Latency cycles     */
+#define FLASH_LATENCY_6                FLASH_ACR_LATENCY_6WS   /*!< FLASH Six Latency cycles      */
+#define FLASH_LATENCY_7                FLASH_ACR_LATENCY_7WS   /*!< FLASH Seven Latency cycles    */
+#define FLASH_LATENCY_8                FLASH_ACR_LATENCY_8WS   /*!< FLASH Eight Latency cycles    */
+#define FLASH_LATENCY_9                FLASH_ACR_LATENCY_9WS   /*!< FLASH Nine Latency cycles     */
+#define FLASH_LATENCY_10               FLASH_ACR_LATENCY_10WS  /*!< FLASH Ten Latency cycles      */
+#define FLASH_LATENCY_11               FLASH_ACR_LATENCY_11WS  /*!< FLASH Eleven Latency cycles   */
+#define FLASH_LATENCY_12               FLASH_ACR_LATENCY_12WS  /*!< FLASH Twelve Latency cycles   */
+#define FLASH_LATENCY_13               FLASH_ACR_LATENCY_13WS  /*!< FLASH Thirteen Latency cycles */
+#define FLASH_LATENCY_14               FLASH_ACR_LATENCY_14WS  /*!< FLASH Fourteen Latency cycles */
+#define FLASH_LATENCY_15               FLASH_ACR_LATENCY_15WS  /*!< FLASH Fifteen Latency cycles  */
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
+/*--------------------------------------------------------------------------------------------------------------*/
+
+/*-------------------------- STM32F40xxx/STM32F41xxx/STM32F401xx/STM32F411xx/STM32F423xx -----------------------*/ 
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
+    defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) ||\
+    defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F412Zx) || defined(STM32F412Vx) ||\
+    defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
+     
+#define FLASH_LATENCY_0                FLASH_ACR_LATENCY_0WS   /*!< FLASH Zero Latency cycle      */
+#define FLASH_LATENCY_1                FLASH_ACR_LATENCY_1WS   /*!< FLASH One Latency cycle       */
+#define FLASH_LATENCY_2                FLASH_ACR_LATENCY_2WS   /*!< FLASH Two Latency cycles      */
+#define FLASH_LATENCY_3                FLASH_ACR_LATENCY_3WS   /*!< FLASH Three Latency cycles    */
+#define FLASH_LATENCY_4                FLASH_ACR_LATENCY_4WS   /*!< FLASH Four Latency cycles     */
+#define FLASH_LATENCY_5                FLASH_ACR_LATENCY_5WS   /*!< FLASH Five Latency cycles     */
+#define FLASH_LATENCY_6                FLASH_ACR_LATENCY_6WS   /*!< FLASH Six Latency cycles      */
+#define FLASH_LATENCY_7                FLASH_ACR_LATENCY_7WS   /*!< FLASH Seven Latency cycles    */
+#endif /* STM32F40xxx || STM32F41xxx || STM32F401xx || STM32F410xx || STM32F411xE || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx ||
+          STM32F413xx || STM32F423xx */
+/*--------------------------------------------------------------------------------------------------------------*/
+
+/**
+  * @}
+  */ 
+  
+
+/** @defgroup FLASHEx_Banks FLASH Banks
+  * @{
+  */
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) ||\
+    defined(STM32F469xx) || defined(STM32F479xx)
+#define FLASH_BANK_1     1U /*!< Bank 1   */
+#define FLASH_BANK_2     2U /*!< Bank 2   */
+#define FLASH_BANK_BOTH  ((uint32_t)FLASH_BANK_1 | FLASH_BANK_2) /*!< Bank1 and Bank2  */
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx || STM32F469xx || STM32F479xx */
+
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
+    defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) ||\
+    defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F412Zx) ||\
+    defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) ||\
+    defined(STM32F423xx)
+#define FLASH_BANK_1     1U /*!< Bank 1   */
+#endif /* STM32F40xxx || STM32F41xxx || STM32F401xx || STM32F410xx || STM32F411xE || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx
+          STM32F413xx || STM32F423xx */
+/**
+  * @}
+  */ 
+    
+/** @defgroup FLASHEx_MassErase_bit FLASH Mass Erase bit
+  * @{
+  */
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) ||\
+    defined(STM32F469xx) || defined(STM32F479xx)
+#define FLASH_MER_BIT     (FLASH_CR_MER1 | FLASH_CR_MER2) /*!< 2 MER bits here to clear */
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx || STM32F469xx || STM32F479xx */
+
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
+    defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) ||\
+    defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F412Zx) ||\
+    defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) ||\
+    defined(STM32F423xx)
+#define FLASH_MER_BIT     (FLASH_CR_MER) /*!< only 1 MER Bit */
+#endif /* STM32F40xxx || STM32F41xxx || STM32F401xx || STM32F410xx || STM32F411xE || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx
+          STM32F413xx || STM32F423xx */
+/**
+  * @}
+  */ 
+
+/** @defgroup FLASHEx_Sectors FLASH Sectors
+  * @{
+  */
+/*-------------------------------------- STM32F42xxx/STM32F43xxx/STM32F469xx ------------------------------------*/   
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) ||\
+    defined(STM32F469xx) || defined(STM32F479xx)
+#define FLASH_SECTOR_0     0U  /*!< Sector Number 0   */
+#define FLASH_SECTOR_1     1U  /*!< Sector Number 1   */
+#define FLASH_SECTOR_2     2U  /*!< Sector Number 2   */
+#define FLASH_SECTOR_3     3U  /*!< Sector Number 3   */
+#define FLASH_SECTOR_4     4U  /*!< Sector Number 4   */
+#define FLASH_SECTOR_5     5U  /*!< Sector Number 5   */
+#define FLASH_SECTOR_6     6U  /*!< Sector Number 6   */
+#define FLASH_SECTOR_7     7U  /*!< Sector Number 7   */
+#define FLASH_SECTOR_8     8U  /*!< Sector Number 8   */
+#define FLASH_SECTOR_9     9U  /*!< Sector Number 9   */
+#define FLASH_SECTOR_10    10U /*!< Sector Number 10  */
+#define FLASH_SECTOR_11    11U /*!< Sector Number 11  */
+#define FLASH_SECTOR_12    12U /*!< Sector Number 12  */
+#define FLASH_SECTOR_13    13U /*!< Sector Number 13  */
+#define FLASH_SECTOR_14    14U /*!< Sector Number 14  */
+#define FLASH_SECTOR_15    15U /*!< Sector Number 15  */
+#define FLASH_SECTOR_16    16U /*!< Sector Number 16  */
+#define FLASH_SECTOR_17    17U /*!< Sector Number 17  */
+#define FLASH_SECTOR_18    18U /*!< Sector Number 18  */
+#define FLASH_SECTOR_19    19U /*!< Sector Number 19  */
+#define FLASH_SECTOR_20    20U /*!< Sector Number 20  */
+#define FLASH_SECTOR_21    21U /*!< Sector Number 21  */
+#define FLASH_SECTOR_22    22U /*!< Sector Number 22  */
+#define FLASH_SECTOR_23    23U /*!< Sector Number 23  */
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx || STM32F469xx || STM32F479xx */
+/*-----------------------------------------------------------------------------------------------------*/
+
+/*-------------------------------------- STM32F413xx/STM32F423xx --------------------------------------*/   
+#if defined(STM32F413xx) || defined(STM32F423xx)
+#define FLASH_SECTOR_0     0U  /*!< Sector Number 0   */
+#define FLASH_SECTOR_1     1U  /*!< Sector Number 1   */
+#define FLASH_SECTOR_2     2U  /*!< Sector Number 2   */
+#define FLASH_SECTOR_3     3U  /*!< Sector Number 3   */
+#define FLASH_SECTOR_4     4U  /*!< Sector Number 4   */
+#define FLASH_SECTOR_5     5U  /*!< Sector Number 5   */
+#define FLASH_SECTOR_6     6U  /*!< Sector Number 6   */
+#define FLASH_SECTOR_7     7U  /*!< Sector Number 7   */
+#define FLASH_SECTOR_8     8U  /*!< Sector Number 8   */
+#define FLASH_SECTOR_9     9U  /*!< Sector Number 9   */
+#define FLASH_SECTOR_10    10U /*!< Sector Number 10  */
+#define FLASH_SECTOR_11    11U /*!< Sector Number 11  */
+#define FLASH_SECTOR_12    12U /*!< Sector Number 12  */
+#define FLASH_SECTOR_13    13U /*!< Sector Number 13  */
+#define FLASH_SECTOR_14    14U /*!< Sector Number 14  */
+#define FLASH_SECTOR_15    15U /*!< Sector Number 15  */
+#endif /* STM32F413xx || STM32F423xx */
+/*-----------------------------------------------------------------------------------------------------*/      
+
+/*--------------------------------------- STM32F40xxx/STM32F41xxx -------------------------------------*/ 
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F412Zx) ||\
+    defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx)  
+#define FLASH_SECTOR_0     0U  /*!< Sector Number 0   */
+#define FLASH_SECTOR_1     1U  /*!< Sector Number 1   */
+#define FLASH_SECTOR_2     2U  /*!< Sector Number 2   */
+#define FLASH_SECTOR_3     3U  /*!< Sector Number 3   */
+#define FLASH_SECTOR_4     4U  /*!< Sector Number 4   */
+#define FLASH_SECTOR_5     5U  /*!< Sector Number 5   */
+#define FLASH_SECTOR_6     6U  /*!< Sector Number 6   */
+#define FLASH_SECTOR_7     7U  /*!< Sector Number 7   */
+#define FLASH_SECTOR_8     8U  /*!< Sector Number 8   */
+#define FLASH_SECTOR_9     9U  /*!< Sector Number 9   */
+#define FLASH_SECTOR_10    10U /*!< Sector Number 10  */
+#define FLASH_SECTOR_11    11U /*!< Sector Number 11  */
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */
+/*-----------------------------------------------------------------------------------------------------*/
+
+/*--------------------------------------------- STM32F401xC -------------------------------------------*/ 
+#if defined(STM32F401xC)
+#define FLASH_SECTOR_0     0U /*!< Sector Number 0   */
+#define FLASH_SECTOR_1     1U /*!< Sector Number 1   */
+#define FLASH_SECTOR_2     2U /*!< Sector Number 2   */
+#define FLASH_SECTOR_3     3U /*!< Sector Number 3   */
+#define FLASH_SECTOR_4     4U /*!< Sector Number 4   */
+#define FLASH_SECTOR_5     5U /*!< Sector Number 5   */
+#endif /* STM32F401xC */
+/*-----------------------------------------------------------------------------------------------------*/
+
+/*--------------------------------------------- STM32F410xx -------------------------------------------*/ 
+#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
+#define FLASH_SECTOR_0     0U /*!< Sector Number 0   */
+#define FLASH_SECTOR_1     1U /*!< Sector Number 1   */
+#define FLASH_SECTOR_2     2U /*!< Sector Number 2   */
+#define FLASH_SECTOR_3     3U /*!< Sector Number 3   */
+#define FLASH_SECTOR_4     4U /*!< Sector Number 4   */
+#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
+/*-----------------------------------------------------------------------------------------------------*/
+
+/*---------------------------------- STM32F401xE/STM32F411xE/STM32F446xx ------------------------------*/
+#if defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx)
+#define FLASH_SECTOR_0     0U /*!< Sector Number 0   */
+#define FLASH_SECTOR_1     1U /*!< Sector Number 1   */
+#define FLASH_SECTOR_2     2U /*!< Sector Number 2   */
+#define FLASH_SECTOR_3     3U /*!< Sector Number 3   */
+#define FLASH_SECTOR_4     4U /*!< Sector Number 4   */
+#define FLASH_SECTOR_5     5U /*!< Sector Number 5   */
+#define FLASH_SECTOR_6     6U /*!< Sector Number 6   */
+#define FLASH_SECTOR_7     7U /*!< Sector Number 7   */
+#endif /* STM32F401xE || STM32F411xE || STM32F446xx */
+/*-----------------------------------------------------------------------------------------------------*/
+
+/**
+  * @}
+  */ 
+
+/** @defgroup FLASHEx_Option_Bytes_Write_Protection FLASH Option Bytes Write Protection
+  * @{
+  */
+/*--------------------------- STM32F42xxx/STM32F43xxx/STM32F469xx/STM32F479xx -------------------------*/  
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
+    defined(STM32F469xx) || defined(STM32F479xx) 
+#define OB_WRP_SECTOR_0       0x00000001U /*!< Write protection of Sector0     */
+#define OB_WRP_SECTOR_1       0x00000002U /*!< Write protection of Sector1     */
+#define OB_WRP_SECTOR_2       0x00000004U /*!< Write protection of Sector2     */
+#define OB_WRP_SECTOR_3       0x00000008U /*!< Write protection of Sector3     */
+#define OB_WRP_SECTOR_4       0x00000010U /*!< Write protection of Sector4     */
+#define OB_WRP_SECTOR_5       0x00000020U /*!< Write protection of Sector5     */
+#define OB_WRP_SECTOR_6       0x00000040U /*!< Write protection of Sector6     */
+#define OB_WRP_SECTOR_7       0x00000080U /*!< Write protection of Sector7     */
+#define OB_WRP_SECTOR_8       0x00000100U /*!< Write protection of Sector8     */
+#define OB_WRP_SECTOR_9       0x00000200U /*!< Write protection of Sector9     */
+#define OB_WRP_SECTOR_10      0x00000400U /*!< Write protection of Sector10    */
+#define OB_WRP_SECTOR_11      0x00000800U /*!< Write protection of Sector11    */
+#define OB_WRP_SECTOR_12      0x00000001U << 12U /*!< Write protection of Sector12    */
+#define OB_WRP_SECTOR_13      0x00000002U << 12U /*!< Write protection of Sector13    */
+#define OB_WRP_SECTOR_14      0x00000004U << 12U /*!< Write protection of Sector14    */
+#define OB_WRP_SECTOR_15      0x00000008U << 12U /*!< Write protection of Sector15    */
+#define OB_WRP_SECTOR_16      0x00000010U << 12U /*!< Write protection of Sector16    */
+#define OB_WRP_SECTOR_17      0x00000020U << 12U /*!< Write protection of Sector17    */
+#define OB_WRP_SECTOR_18      0x00000040U << 12U /*!< Write protection of Sector18    */
+#define OB_WRP_SECTOR_19      0x00000080U << 12U /*!< Write protection of Sector19    */
+#define OB_WRP_SECTOR_20      0x00000100U << 12U /*!< Write protection of Sector20    */
+#define OB_WRP_SECTOR_21      0x00000200U << 12U /*!< Write protection of Sector21    */
+#define OB_WRP_SECTOR_22      0x00000400U << 12U /*!< Write protection of Sector22    */
+#define OB_WRP_SECTOR_23      0x00000800U << 12U /*!< Write protection of Sector23    */
+#define OB_WRP_SECTOR_All     0x00000FFFU << 12U /*!< Write protection of all Sectors */
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx || STM32F469xx || STM32F479xx */
+/*-----------------------------------------------------------------------------------------------------*/
+
+/*--------------------------------------- STM32F413xx/STM32F423xx -------------------------------------*/ 
+#if defined(STM32F413xx) || defined(STM32F423xx)  
+#define OB_WRP_SECTOR_0       0x00000001U /*!< Write protection of Sector0     */
+#define OB_WRP_SECTOR_1       0x00000002U /*!< Write protection of Sector1     */
+#define OB_WRP_SECTOR_2       0x00000004U /*!< Write protection of Sector2     */
+#define OB_WRP_SECTOR_3       0x00000008U /*!< Write protection of Sector3     */
+#define OB_WRP_SECTOR_4       0x00000010U /*!< Write protection of Sector4     */
+#define OB_WRP_SECTOR_5       0x00000020U /*!< Write protection of Sector5     */
+#define OB_WRP_SECTOR_6       0x00000040U /*!< Write protection of Sector6     */
+#define OB_WRP_SECTOR_7       0x00000080U /*!< Write protection of Sector7     */
+#define OB_WRP_SECTOR_8       0x00000100U /*!< Write protection of Sector8     */
+#define OB_WRP_SECTOR_9       0x00000200U /*!< Write protection of Sector9     */
+#define OB_WRP_SECTOR_10      0x00000400U /*!< Write protection of Sector10    */
+#define OB_WRP_SECTOR_11      0x00000800U /*!< Write protection of Sector11    */
+#define OB_WRP_SECTOR_12      0x00001000U /*!< Write protection of Sector12    */
+#define OB_WRP_SECTOR_13      0x00002000U /*!< Write protection of Sector13    */
+#define OB_WRP_SECTOR_14      0x00004000U /*!< Write protection of Sector14    */
+#define OB_WRP_SECTOR_15      0x00004000U /*!< Write protection of Sector15    */      
+#define OB_WRP_SECTOR_All     0x00007FFFU /*!< Write protection of all Sectors */
+#endif /* STM32F413xx || STM32F423xx */
+/*-----------------------------------------------------------------------------------------------------*/    
+      
+/*--------------------------------------- STM32F40xxx/STM32F41xxx -------------------------------------*/ 
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F412Zx) ||\
+    defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx)  
+#define OB_WRP_SECTOR_0       0x00000001U /*!< Write protection of Sector0     */
+#define OB_WRP_SECTOR_1       0x00000002U /*!< Write protection of Sector1     */
+#define OB_WRP_SECTOR_2       0x00000004U /*!< Write protection of Sector2     */
+#define OB_WRP_SECTOR_3       0x00000008U /*!< Write protection of Sector3     */
+#define OB_WRP_SECTOR_4       0x00000010U /*!< Write protection of Sector4     */
+#define OB_WRP_SECTOR_5       0x00000020U /*!< Write protection of Sector5     */
+#define OB_WRP_SECTOR_6       0x00000040U /*!< Write protection of Sector6     */
+#define OB_WRP_SECTOR_7       0x00000080U /*!< Write protection of Sector7     */
+#define OB_WRP_SECTOR_8       0x00000100U /*!< Write protection of Sector8     */
+#define OB_WRP_SECTOR_9       0x00000200U /*!< Write protection of Sector9     */
+#define OB_WRP_SECTOR_10      0x00000400U /*!< Write protection of Sector10    */
+#define OB_WRP_SECTOR_11      0x00000800U /*!< Write protection of Sector11    */
+#define OB_WRP_SECTOR_All     0x00000FFFU /*!< Write protection of all Sectors */
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */
+/*-----------------------------------------------------------------------------------------------------*/
+
+/*--------------------------------------------- STM32F401xC -------------------------------------------*/
+#if defined(STM32F401xC)
+#define OB_WRP_SECTOR_0       0x00000001U /*!< Write protection of Sector0     */
+#define OB_WRP_SECTOR_1       0x00000002U /*!< Write protection of Sector1     */
+#define OB_WRP_SECTOR_2       0x00000004U /*!< Write protection of Sector2     */
+#define OB_WRP_SECTOR_3       0x00000008U /*!< Write protection of Sector3     */
+#define OB_WRP_SECTOR_4       0x00000010U /*!< Write protection of Sector4     */
+#define OB_WRP_SECTOR_5       0x00000020U /*!< Write protection of Sector5     */
+#define OB_WRP_SECTOR_All     0x00000FFFU /*!< Write protection of all Sectors */
+#endif /* STM32F401xC */
+/*-----------------------------------------------------------------------------------------------------*/
+ 
+/*--------------------------------------------- STM32F410xx -------------------------------------------*/
+#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
+#define OB_WRP_SECTOR_0       0x00000001U /*!< Write protection of Sector0     */
+#define OB_WRP_SECTOR_1       0x00000002U /*!< Write protection of Sector1     */
+#define OB_WRP_SECTOR_2       0x00000004U /*!< Write protection of Sector2     */
+#define OB_WRP_SECTOR_3       0x00000008U /*!< Write protection of Sector3     */
+#define OB_WRP_SECTOR_4       0x00000010U /*!< Write protection of Sector4     */
+#define OB_WRP_SECTOR_All     0x00000FFFU /*!< Write protection of all Sectors */
+#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
+/*-----------------------------------------------------------------------------------------------------*/
+
+/*---------------------------------- STM32F401xE/STM32F411xE/STM32F446xx ------------------------------*/
+#if defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx)
+#define OB_WRP_SECTOR_0       0x00000001U /*!< Write protection of Sector0     */
+#define OB_WRP_SECTOR_1       0x00000002U /*!< Write protection of Sector1     */
+#define OB_WRP_SECTOR_2       0x00000004U /*!< Write protection of Sector2     */
+#define OB_WRP_SECTOR_3       0x00000008U /*!< Write protection of Sector3     */
+#define OB_WRP_SECTOR_4       0x00000010U /*!< Write protection of Sector4     */
+#define OB_WRP_SECTOR_5       0x00000020U /*!< Write protection of Sector5     */
+#define OB_WRP_SECTOR_6       0x00000040U /*!< Write protection of Sector6     */
+#define OB_WRP_SECTOR_7       0x00000080U /*!< Write protection of Sector7     */
+#define OB_WRP_SECTOR_All     0x00000FFFU /*!< Write protection of all Sectors */
+#endif /* STM32F401xE || STM32F411xE || STM32F446xx */
+/*-----------------------------------------------------------------------------------------------------*/
+/**
+  * @}
+  */
+  
+/** @defgroup FLASHEx_Option_Bytes_PC_ReadWrite_Protection FLASH Option Bytes PC ReadWrite Protection
+  * @{
+  */
+/*-------------------------------- STM32F42xxx/STM32F43xxx/STM32F469xx/STM32F479xx ---------------------------*/   
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) ||\
+    defined(STM32F469xx) || defined(STM32F479xx) 
+#define OB_PCROP_SECTOR_0        0x00000001U /*!< PC Read/Write protection of Sector0      */
+#define OB_PCROP_SECTOR_1        0x00000002U /*!< PC Read/Write protection of Sector1      */
+#define OB_PCROP_SECTOR_2        0x00000004U /*!< PC Read/Write protection of Sector2      */
+#define OB_PCROP_SECTOR_3        0x00000008U /*!< PC Read/Write protection of Sector3      */
+#define OB_PCROP_SECTOR_4        0x00000010U /*!< PC Read/Write protection of Sector4      */
+#define OB_PCROP_SECTOR_5        0x00000020U /*!< PC Read/Write protection of Sector5      */
+#define OB_PCROP_SECTOR_6        0x00000040U /*!< PC Read/Write protection of Sector6      */
+#define OB_PCROP_SECTOR_7        0x00000080U /*!< PC Read/Write protection of Sector7      */
+#define OB_PCROP_SECTOR_8        0x00000100U /*!< PC Read/Write protection of Sector8      */
+#define OB_PCROP_SECTOR_9        0x00000200U /*!< PC Read/Write protection of Sector9      */
+#define OB_PCROP_SECTOR_10       0x00000400U /*!< PC Read/Write protection of Sector10     */
+#define OB_PCROP_SECTOR_11       0x00000800U /*!< PC Read/Write protection of Sector11     */
+#define OB_PCROP_SECTOR_12       0x00000001U /*!< PC Read/Write protection of Sector12     */
+#define OB_PCROP_SECTOR_13       0x00000002U /*!< PC Read/Write protection of Sector13     */
+#define OB_PCROP_SECTOR_14       0x00000004U /*!< PC Read/Write protection of Sector14     */
+#define OB_PCROP_SECTOR_15       0x00000008U /*!< PC Read/Write protection of Sector15     */
+#define OB_PCROP_SECTOR_16       0x00000010U /*!< PC Read/Write protection of Sector16     */
+#define OB_PCROP_SECTOR_17       0x00000020U /*!< PC Read/Write protection of Sector17     */
+#define OB_PCROP_SECTOR_18       0x00000040U /*!< PC Read/Write protection of Sector18     */
+#define OB_PCROP_SECTOR_19       0x00000080U /*!< PC Read/Write protection of Sector19     */
+#define OB_PCROP_SECTOR_20       0x00000100U /*!< PC Read/Write protection of Sector20     */
+#define OB_PCROP_SECTOR_21       0x00000200U /*!< PC Read/Write protection of Sector21     */
+#define OB_PCROP_SECTOR_22       0x00000400U /*!< PC Read/Write protection of Sector22     */
+#define OB_PCROP_SECTOR_23       0x00000800U /*!< PC Read/Write protection of Sector23     */
+#define OB_PCROP_SECTOR_All      0x00000FFFU /*!< PC Read/Write protection of all Sectors  */
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx || STM32F469xx || STM32F479xx */
+/*-----------------------------------------------------------------------------------------------------*/
+      
+/*------------------------------------- STM32F413xx/STM32F423xx ---------------------------------------*/
+#if defined(STM32F413xx) || defined(STM32F423xx)  
+#define OB_PCROP_SECTOR_0        0x00000001U /*!< PC Read/Write protection of Sector0      */
+#define OB_PCROP_SECTOR_1        0x00000002U /*!< PC Read/Write protection of Sector1      */
+#define OB_PCROP_SECTOR_2        0x00000004U /*!< PC Read/Write protection of Sector2      */
+#define OB_PCROP_SECTOR_3        0x00000008U /*!< PC Read/Write protection of Sector3      */
+#define OB_PCROP_SECTOR_4        0x00000010U /*!< PC Read/Write protection of Sector4      */
+#define OB_PCROP_SECTOR_5        0x00000020U /*!< PC Read/Write protection of Sector5      */
+#define OB_PCROP_SECTOR_6        0x00000040U /*!< PC Read/Write protection of Sector6      */
+#define OB_PCROP_SECTOR_7        0x00000080U /*!< PC Read/Write protection of Sector7      */
+#define OB_PCROP_SECTOR_8        0x00000100U /*!< PC Read/Write protection of Sector8      */
+#define OB_PCROP_SECTOR_9        0x00000200U /*!< PC Read/Write protection of Sector9      */
+#define OB_PCROP_SECTOR_10       0x00000400U /*!< PC Read/Write protection of Sector10     */
+#define OB_PCROP_SECTOR_11       0x00000800U /*!< PC Read/Write protection of Sector11     */
+#define OB_PCROP_SECTOR_12       0x00001000U /*!< PC Read/Write protection of Sector12     */
+#define OB_PCROP_SECTOR_13       0x00002000U /*!< PC Read/Write protection of Sector13     */
+#define OB_PCROP_SECTOR_14       0x00004000U /*!< PC Read/Write protection of Sector14     */
+#define OB_PCROP_SECTOR_15       0x00004000U /*!< PC Read/Write protection of Sector15     */      
+#define OB_PCROP_SECTOR_All      0x00007FFFU /*!< PC Read/Write protection of all Sectors  */
+#endif /* STM32F413xx || STM32F423xx */
+/*-----------------------------------------------------------------------------------------------------*/      
+
+/*--------------------------------------------- STM32F401xC -------------------------------------------*/
+#if defined(STM32F401xC)
+#define OB_PCROP_SECTOR_0        0x00000001U /*!< PC Read/Write protection of Sector0      */
+#define OB_PCROP_SECTOR_1        0x00000002U /*!< PC Read/Write protection of Sector1      */
+#define OB_PCROP_SECTOR_2        0x00000004U /*!< PC Read/Write protection of Sector2      */
+#define OB_PCROP_SECTOR_3        0x00000008U /*!< PC Read/Write protection of Sector3      */
+#define OB_PCROP_SECTOR_4        0x00000010U /*!< PC Read/Write protection of Sector4      */
+#define OB_PCROP_SECTOR_5        0x00000020U /*!< PC Read/Write protection of Sector5      */
+#define OB_PCROP_SECTOR_All      0x00000FFFU /*!< PC Read/Write protection of all Sectors  */
+#endif /* STM32F401xC */
+/*-----------------------------------------------------------------------------------------------------*/
+
+/*--------------------------------------------- STM32F410xx -------------------------------------------*/
+#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
+#define OB_PCROP_SECTOR_0        0x00000001U /*!< PC Read/Write protection of Sector0      */
+#define OB_PCROP_SECTOR_1        0x00000002U /*!< PC Read/Write protection of Sector1      */
+#define OB_PCROP_SECTOR_2        0x00000004U /*!< PC Read/Write protection of Sector2      */
+#define OB_PCROP_SECTOR_3        0x00000008U /*!< PC Read/Write protection of Sector3      */
+#define OB_PCROP_SECTOR_4        0x00000010U /*!< PC Read/Write protection of Sector4      */
+#define OB_PCROP_SECTOR_All      0x00000FFFU /*!< PC Read/Write protection of all Sectors  */
+#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
+/*-----------------------------------------------------------------------------------------------------*/
+
+/*-------------- STM32F401xE/STM32F411xE/STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx/STM32F446xx --*/
+#if defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F412Zx) ||\
+    defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx)  
+#define OB_PCROP_SECTOR_0        0x00000001U /*!< PC Read/Write protection of Sector0      */
+#define OB_PCROP_SECTOR_1        0x00000002U /*!< PC Read/Write protection of Sector1      */
+#define OB_PCROP_SECTOR_2        0x00000004U /*!< PC Read/Write protection of Sector2      */
+#define OB_PCROP_SECTOR_3        0x00000008U /*!< PC Read/Write protection of Sector3      */
+#define OB_PCROP_SECTOR_4        0x00000010U /*!< PC Read/Write protection of Sector4      */
+#define OB_PCROP_SECTOR_5        0x00000020U /*!< PC Read/Write protection of Sector5      */
+#define OB_PCROP_SECTOR_6        0x00000040U /*!< PC Read/Write protection of Sector6      */
+#define OB_PCROP_SECTOR_7        0x00000080U /*!< PC Read/Write protection of Sector7      */
+#define OB_PCROP_SECTOR_All      0x00000FFFU /*!< PC Read/Write protection of all Sectors  */
+#endif /* STM32F401xE || STM32F411xE || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */
+/*-----------------------------------------------------------------------------------------------------*/
+
+/**
+  * @}
+  */
+  
+/** @defgroup FLASHEx_Dual_Boot FLASH Dual Boot
+  * @{
+  */
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) ||\
+    defined(STM32F469xx) || defined(STM32F479xx) 
+#define OB_DUAL_BOOT_ENABLE   ((uint8_t)0x10) /*!< Dual Bank Boot Enable                             */
+#define OB_DUAL_BOOT_DISABLE  ((uint8_t)0x00) /*!< Dual Bank Boot Disable, always boot on User Flash */
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx || STM32F469xx || STM32F479xx */
+/**
+  * @}
+  */
+
+/** @defgroup  FLASHEx_Selection_Protection_Mode FLASH Selection Protection Mode
+  * @{
+  */
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
+    defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) ||\
+    defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F469xx) ||\
+    defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) ||\
+    defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
+#define OB_PCROP_DESELECTED     ((uint8_t)0x00) /*!< Disabled PcROP, nWPRi bits used for Write Protection on sector i */
+#define OB_PCROP_SELECTED       ((uint8_t)0x80) /*!< Enable PcROP, nWPRi bits used for PCRoP Protection on sector i   */
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F401xC || STM32F401xE ||\
+          STM32F410xx || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx ||\
+          STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */ 
+  
+/* Exported macro ------------------------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup FLASHEx_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup FLASHEx_Exported_Functions_Group1
+  * @{
+  */
+/* Extension Program operation functions  *************************************/
+HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *SectorError);
+HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit);
+HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit);
+void              HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit);
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
+    defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) ||\
+    defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F469xx) ||\
+    defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) ||\
+    defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
+HAL_StatusTypeDef HAL_FLASHEx_AdvOBProgram (FLASH_AdvOBProgramInitTypeDef *pAdvOBInit);
+void              HAL_FLASHEx_AdvOBGetConfig(FLASH_AdvOBProgramInitTypeDef *pAdvOBInit);
+HAL_StatusTypeDef HAL_FLASHEx_OB_SelectPCROP(void);
+HAL_StatusTypeDef HAL_FLASHEx_OB_DeSelectPCROP(void);
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F401xC || STM32F401xE ||\
+          STM32F410xx || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx ||\
+          STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) ||\
+    defined(STM32F469xx) || defined(STM32F479xx)
+uint16_t          HAL_FLASHEx_OB_GetBank2WRP(void);
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx || STM32F469xx || STM32F479xx */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup FLASHEx_Private_Constants FLASH Private Constants
+  * @{
+  */
+/*--------------------------------- STM32F42xxx/STM32F43xxx/STM32F469xx/STM32F479xx---------------------*/ 
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
+#define FLASH_SECTOR_TOTAL  24U
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
+
+/*-------------------------------------- STM32F413xx/STM32F423xx ---------------------------------------*/
+#if defined(STM32F413xx) || defined(STM32F423xx)
+#define FLASH_SECTOR_TOTAL  16U
+#endif /* STM32F413xx || STM32F423xx */
+
+/*--------------------------------------- STM32F40xxx/STM32F41xxx -------------------------------------*/ 
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F412Zx) ||\
+    defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx)  
+#define FLASH_SECTOR_TOTAL  12U
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */
+
+/*--------------------------------------------- STM32F401xC -------------------------------------------*/ 
+#if defined(STM32F401xC)
+#define FLASH_SECTOR_TOTAL  6U
+#endif /* STM32F401xC */
+
+/*--------------------------------------------- STM32F410xx -------------------------------------------*/ 
+#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
+#define FLASH_SECTOR_TOTAL  5U
+#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
+
+/*--------------------------------- STM32F401xE/STM32F411xE/STM32F412xG/STM32F446xx -------------------*/
+#if defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx)
+#define FLASH_SECTOR_TOTAL  8U
+#endif /* STM32F401xE || STM32F411xE || STM32F446xx */
+
+/** 
+  * @brief OPTCR1 register byte 2 (Bits[23:16]) base address  
+  */ 
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)  
+#define OPTCR1_BYTE2_ADDRESS         0x40023C1AU
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup FLASHEx_Private_Macros FLASH Private Macros
+  * @{
+  */
+
+/** @defgroup FLASHEx_IS_FLASH_Definitions FLASH Private macros to check input parameters
+  * @{
+  */
+
+#define IS_FLASH_TYPEERASE(VALUE)(((VALUE) == FLASH_TYPEERASE_SECTORS) || \
+                                  ((VALUE) == FLASH_TYPEERASE_MASSERASE))  
+
+#define IS_VOLTAGERANGE(RANGE)(((RANGE) == FLASH_VOLTAGE_RANGE_1) || \
+                               ((RANGE) == FLASH_VOLTAGE_RANGE_2) || \
+                               ((RANGE) == FLASH_VOLTAGE_RANGE_3) || \
+                               ((RANGE) == FLASH_VOLTAGE_RANGE_4))  
+
+#define IS_WRPSTATE(VALUE)(((VALUE) == OB_WRPSTATE_DISABLE) || \
+                           ((VALUE) == OB_WRPSTATE_ENABLE))  
+
+#define IS_OPTIONBYTE(VALUE)(((VALUE) <= (OPTIONBYTE_WRP|OPTIONBYTE_RDP|OPTIONBYTE_USER|OPTIONBYTE_BOR)))
+
+#define IS_OB_RDP_LEVEL(LEVEL) (((LEVEL) == OB_RDP_LEVEL_0) ||\
+                                ((LEVEL) == OB_RDP_LEVEL_1) ||\
+                                ((LEVEL) == OB_RDP_LEVEL_2))
+
+#define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW))
+
+#define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NO_RST) || ((SOURCE) == OB_STOP_RST))
+
+#define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NO_RST) || ((SOURCE) == OB_STDBY_RST))
+
+#define IS_OB_BOR_LEVEL(LEVEL) (((LEVEL) == OB_BOR_LEVEL1) || ((LEVEL) == OB_BOR_LEVEL2) ||\
+                                ((LEVEL) == OB_BOR_LEVEL3) || ((LEVEL) == OB_BOR_OFF))
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
+    defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) ||\
+    defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F469xx) ||\
+    defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) ||\
+    defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
+#define IS_PCROPSTATE(VALUE)(((VALUE) == OB_PCROP_STATE_DISABLE) || \
+                             ((VALUE) == OB_PCROP_STATE_ENABLE))  
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F401xC || STM32F401xE ||\
+          STM32F410xx || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx ||\
+          STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
+    defined(STM32F469xx) || defined(STM32F479xx)
+#define IS_OBEX(VALUE)(((VALUE) == OPTIONBYTE_PCROP) || \
+                       ((VALUE) == OPTIONBYTE_BOOTCONFIG))  
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
+
+#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) ||\
+    defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F412Zx) ||\
+    defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) ||\
+    defined(STM32F423xx)
+#define IS_OBEX(VALUE)(((VALUE) == OPTIONBYTE_PCROP))  
+#endif /* STM32F401xC || STM32F401xE || STM32F410xx || STM32F411xE || STM32F446xx || STM32F412Zx ||\
+          STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */
+  
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) ||\
+    defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
+#define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_LATENCY_0)  || \
+                                   ((LATENCY) == FLASH_LATENCY_1)  || \
+                                   ((LATENCY) == FLASH_LATENCY_2)  || \
+                                   ((LATENCY) == FLASH_LATENCY_3)  || \
+                                   ((LATENCY) == FLASH_LATENCY_4)  || \
+                                   ((LATENCY) == FLASH_LATENCY_5)  || \
+                                   ((LATENCY) == FLASH_LATENCY_6)  || \
+                                   ((LATENCY) == FLASH_LATENCY_7)  || \
+                                   ((LATENCY) == FLASH_LATENCY_8)  || \
+                                   ((LATENCY) == FLASH_LATENCY_9)  || \
+                                   ((LATENCY) == FLASH_LATENCY_10) || \
+                                   ((LATENCY) == FLASH_LATENCY_11) || \
+                                   ((LATENCY) == FLASH_LATENCY_12) || \
+                                   ((LATENCY) == FLASH_LATENCY_13) || \
+                                   ((LATENCY) == FLASH_LATENCY_14) || \
+                                   ((LATENCY) == FLASH_LATENCY_15))
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
+
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
+    defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) ||\
+    defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F412Zx) || defined(STM32F412Vx) ||\
+    defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
+#define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_LATENCY_0)  || \
+                                   ((LATENCY) == FLASH_LATENCY_1)  || \
+                                   ((LATENCY) == FLASH_LATENCY_2)  || \
+                                   ((LATENCY) == FLASH_LATENCY_3)  || \
+                                   ((LATENCY) == FLASH_LATENCY_4)  || \
+                                   ((LATENCY) == FLASH_LATENCY_5)  || \
+                                   ((LATENCY) == FLASH_LATENCY_6)  || \
+                                   ((LATENCY) == FLASH_LATENCY_7))
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE || STM32F410xx || STM32F411xE || STM32F412Zx || STM32F412Vx ||\
+          STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
+#define IS_FLASH_BANK(BANK) (((BANK) == FLASH_BANK_1)  || \
+                             ((BANK) == FLASH_BANK_2)  || \
+                             ((BANK) == FLASH_BANK_BOTH))
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx || STM32F469xx || STM32F479xx */
+
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
+    defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) ||\
+    defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F412Zx) ||\
+    defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) ||\
+    defined(STM32F423xx)
+#define IS_FLASH_BANK(BANK) (((BANK) == FLASH_BANK_1))
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE || STM32F410xx || STM32F411xE || STM32F446xx || STM32F412Zx || STM32F412Vx ||\
+          STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */
+ 
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
+#define IS_FLASH_SECTOR(SECTOR) ( ((SECTOR) == FLASH_SECTOR_0)   || ((SECTOR) == FLASH_SECTOR_1)   ||\
+                                  ((SECTOR) == FLASH_SECTOR_2)   || ((SECTOR) == FLASH_SECTOR_3)   ||\
+                                  ((SECTOR) == FLASH_SECTOR_4)   || ((SECTOR) == FLASH_SECTOR_5)   ||\
+                                  ((SECTOR) == FLASH_SECTOR_6)   || ((SECTOR) == FLASH_SECTOR_7)   ||\
+                                  ((SECTOR) == FLASH_SECTOR_8)   || ((SECTOR) == FLASH_SECTOR_9)   ||\
+                                  ((SECTOR) == FLASH_SECTOR_10)  || ((SECTOR) == FLASH_SECTOR_11)  ||\
+                                  ((SECTOR) == FLASH_SECTOR_12)  || ((SECTOR) == FLASH_SECTOR_13)  ||\
+                                  ((SECTOR) == FLASH_SECTOR_14)  || ((SECTOR) == FLASH_SECTOR_15)  ||\
+                                  ((SECTOR) == FLASH_SECTOR_16)  || ((SECTOR) == FLASH_SECTOR_17)  ||\
+                                  ((SECTOR) == FLASH_SECTOR_18)  || ((SECTOR) == FLASH_SECTOR_19)  ||\
+                                  ((SECTOR) == FLASH_SECTOR_20)  || ((SECTOR) == FLASH_SECTOR_21)  ||\
+                                  ((SECTOR) == FLASH_SECTOR_22)  || ((SECTOR) == FLASH_SECTOR_23))
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
+
+#if defined(STM32F413xx) || defined(STM32F423xx)
+#define IS_FLASH_SECTOR(SECTOR) ( ((SECTOR) == FLASH_SECTOR_0)   || ((SECTOR) == FLASH_SECTOR_1)   ||\
+                                  ((SECTOR) == FLASH_SECTOR_2)   || ((SECTOR) == FLASH_SECTOR_3)   ||\
+                                  ((SECTOR) == FLASH_SECTOR_4)   || ((SECTOR) == FLASH_SECTOR_5)   ||\
+                                  ((SECTOR) == FLASH_SECTOR_6)   || ((SECTOR) == FLASH_SECTOR_7)   ||\
+                                  ((SECTOR) == FLASH_SECTOR_8)   || ((SECTOR) == FLASH_SECTOR_9)   ||\
+                                  ((SECTOR) == FLASH_SECTOR_10)  || ((SECTOR) == FLASH_SECTOR_11)  ||\
+                                  ((SECTOR) == FLASH_SECTOR_12)  || ((SECTOR) == FLASH_SECTOR_13)  ||\
+                                  ((SECTOR) == FLASH_SECTOR_14)  || ((SECTOR) == FLASH_SECTOR_15))
+#endif /* STM32F413xx || STM32F423xx */
+
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F412Zx) ||\
+    defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx)  
+#define IS_FLASH_SECTOR(SECTOR) (((SECTOR) == FLASH_SECTOR_0)   || ((SECTOR) == FLASH_SECTOR_1)   ||\
+                                 ((SECTOR) == FLASH_SECTOR_2)   || ((SECTOR) == FLASH_SECTOR_3)   ||\
+                                 ((SECTOR) == FLASH_SECTOR_4)   || ((SECTOR) == FLASH_SECTOR_5)   ||\
+                                 ((SECTOR) == FLASH_SECTOR_6)   || ((SECTOR) == FLASH_SECTOR_7)   ||\
+                                 ((SECTOR) == FLASH_SECTOR_8)   || ((SECTOR) == FLASH_SECTOR_9)   ||\
+                                 ((SECTOR) == FLASH_SECTOR_10)  || ((SECTOR) == FLASH_SECTOR_11))
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */
+
+#if defined(STM32F401xC)
+#define IS_FLASH_SECTOR(SECTOR) (((SECTOR) == FLASH_SECTOR_0)   || ((SECTOR) == FLASH_SECTOR_1)   ||\
+                                 ((SECTOR) == FLASH_SECTOR_2)   || ((SECTOR) == FLASH_SECTOR_3)   ||\
+                                 ((SECTOR) == FLASH_SECTOR_4)   || ((SECTOR) == FLASH_SECTOR_5))
+#endif /* STM32F401xC */
+
+#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
+#define IS_FLASH_SECTOR(SECTOR) (((SECTOR) == FLASH_SECTOR_0)   || ((SECTOR) == FLASH_SECTOR_1)   ||\
+                                 ((SECTOR) == FLASH_SECTOR_2)   || ((SECTOR) == FLASH_SECTOR_3)   ||\
+                                 ((SECTOR) == FLASH_SECTOR_4))
+#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
+
+#if defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx)
+#define IS_FLASH_SECTOR(SECTOR) (((SECTOR) == FLASH_SECTOR_0)   || ((SECTOR) == FLASH_SECTOR_1)   ||\
+                                 ((SECTOR) == FLASH_SECTOR_2)   || ((SECTOR) == FLASH_SECTOR_3)   ||\
+                                 ((SECTOR) == FLASH_SECTOR_4)   || ((SECTOR) == FLASH_SECTOR_5)   ||\
+                                 ((SECTOR) == FLASH_SECTOR_6)   || ((SECTOR) == FLASH_SECTOR_7))
+#endif /* STM32F401xE || STM32F411xE || STM32F446xx */
+
+#define IS_FLASH_ADDRESS(ADDRESS) ((((ADDRESS) >= FLASH_BASE) && ((ADDRESS) <= FLASH_END)) || \
+                                   (((ADDRESS) >= FLASH_OTP_BASE) && ((ADDRESS) <= FLASH_OTP_END)))
+
+#define IS_FLASH_NBSECTORS(NBSECTORS) (((NBSECTORS) != 0) && ((NBSECTORS) <= FLASH_SECTOR_TOTAL))
+  
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) 
+#define IS_OB_WRP_SECTOR(SECTOR)((((SECTOR) & 0xFF000000U) == 0x00000000U) && ((SECTOR) != 0x00000000U))
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
+
+#if defined(STM32F413xx) || defined(STM32F423xx) 
+#define IS_OB_WRP_SECTOR(SECTOR)((((SECTOR) & 0xFFFF8000U) == 0x00000000U) && ((SECTOR) != 0x00000000U))
+#endif /* STM32F413xx || STM32F423xx */
+
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
+#define IS_OB_WRP_SECTOR(SECTOR)((((SECTOR) & 0xFFFFF000U) == 0x00000000U) && ((SECTOR) != 0x00000000U))
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
+
+#if defined(STM32F401xC)
+#define IS_OB_WRP_SECTOR(SECTOR)((((SECTOR) & 0xFFFFF000U) == 0x00000000U) && ((SECTOR) != 0x00000000U))
+#endif /* STM32F401xC */
+
+#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
+#define IS_OB_WRP_SECTOR(SECTOR)((((SECTOR) & 0xFFFFF000U) == 0x00000000U) && ((SECTOR) != 0x00000000U))
+#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
+
+#if defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F412Zx) || defined(STM32F412Vx) ||\
+    defined(STM32F412Rx) || defined(STM32F412Cx)  
+#define IS_OB_WRP_SECTOR(SECTOR)((((SECTOR) & 0xFFFFF000U) == 0x00000000U) && ((SECTOR) != 0x00000000U))
+#endif /* STM32F401xE || STM32F411xE || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */
+   
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
+#define IS_OB_PCROP(SECTOR)((((SECTOR) & 0xFFFFF000U) == 0x00000000U) && ((SECTOR) != 0x00000000U))
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
+
+#if defined(STM32F413xx) || defined(STM32F423xx)
+#define IS_OB_PCROP(SECTOR)((((SECTOR) & 0xFFFF8000U) == 0x00000000U) && ((SECTOR) != 0x00000000U))      
+#endif /* STM32F413xx || STM32F423xx */
+
+#if defined(STM32F401xC)
+#define IS_OB_PCROP(SECTOR)((((SECTOR) & 0xFFFFF000U) == 0x00000000U) && ((SECTOR) != 0x00000000U))
+#endif /* STM32F401xC */
+
+#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
+#define IS_OB_PCROP(SECTOR)((((SECTOR) & 0xFFFFF000U) == 0x00000000U) && ((SECTOR) != 0x00000000U))
+#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
+
+#if defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F412Zx) || defined(STM32F412Vx) ||\
+    defined(STM32F412Rx) || defined(STM32F412Cx)  
+#define IS_OB_PCROP(SECTOR)((((SECTOR) & 0xFFFFF000U) == 0x00000000U) && ((SECTOR) != 0x00000000U))
+#endif /* STM32F401xE || STM32F411xE || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
+    defined(STM32F469xx) || defined(STM32F479xx) 
+#define IS_OB_BOOT(BOOT) (((BOOT) == OB_DUAL_BOOT_ENABLE) || ((BOOT) == OB_DUAL_BOOT_DISABLE))
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
+    defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) ||\
+    defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F469xx) ||\
+    defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) ||\
+    defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
+#define IS_OB_PCROP_SELECT(PCROP) (((PCROP) == OB_PCROP_SELECTED) || ((PCROP) == OB_PCROP_DESELECTED))
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F401xC || STM32F401xE ||\
+          STM32F410xx || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx ||\
+          STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup FLASHEx_Private_Functions FLASH Private Functions
+  * @{
+  */
+void FLASH_Erase_Sector(uint32_t Sector, uint8_t VoltageRange);
+void FLASH_FlushCaches(void);
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_FLASH_EX_H */
+
diff --git a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h
new file mode 100644
index 0000000..b4d5f60
--- /dev/null
+++ b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h
@@ -0,0 +1,76 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hal_flash_ramfunc.h
+  * @author  MCD Application Team
+  * @brief   Header file of FLASH RAMFUNC driver.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file in
+  * the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  ******************************************************************************
+  */ 
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_FLASH_RAMFUNC_H
+#define __STM32F4xx_FLASH_RAMFUNC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F412Zx) ||\
+    defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx)  
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup FLASH_RAMFUNC
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup FLASH_RAMFUNC_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup FLASH_RAMFUNC_Exported_Functions_Group1
+  * @{
+  */   
+__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_StopFlashInterfaceClk(void);
+__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_StartFlashInterfaceClk(void);
+__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_EnableFlashSleepMode(void);
+__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_DisableFlashSleepMode(void);
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */
+
+#endif /* STM32F410xx || STM32F411xE || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */  
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* __STM32F4xx_FLASH_RAMFUNC_H */
+
diff --git a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h
new file mode 100644
index 0000000..661400f
--- /dev/null
+++ b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h
@@ -0,0 +1,325 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hal_gpio.h
+  * @author  MCD Application Team
+  * @brief   Header file of GPIO HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */ 
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_GPIO_H
+#define __STM32F4xx_HAL_GPIO_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup GPIO
+  * @{
+  */ 
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup GPIO_Exported_Types GPIO Exported Types
+  * @{
+  */
+
+/** 
+  * @brief GPIO Init structure definition  
+  */ 
+typedef struct
+{
+  uint32_t Pin;       /*!< Specifies the GPIO pins to be configured.
+                           This parameter can be any value of @ref GPIO_pins_define */
+
+  uint32_t Mode;      /*!< Specifies the operating mode for the selected pins.
+                           This parameter can be a value of @ref GPIO_mode_define */
+
+  uint32_t Pull;      /*!< Specifies the Pull-up or Pull-Down activation for the selected pins.
+                           This parameter can be a value of @ref GPIO_pull_define */
+
+  uint32_t Speed;     /*!< Specifies the speed for the selected pins.
+                           This parameter can be a value of @ref GPIO_speed_define */
+
+  uint32_t Alternate;  /*!< Peripheral to be connected to the selected pins. 
+                            This parameter can be a value of @ref GPIO_Alternate_function_selection */
+}GPIO_InitTypeDef;
+
+/** 
+  * @brief  GPIO Bit SET and Bit RESET enumeration 
+  */
+typedef enum
+{
+  GPIO_PIN_RESET = 0,
+  GPIO_PIN_SET
+}GPIO_PinState;
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup GPIO_Exported_Constants GPIO Exported Constants
+  * @{
+  */ 
+
+/** @defgroup GPIO_pins_define GPIO pins define
+  * @{
+  */
+#define GPIO_PIN_0                 ((uint16_t)0x0001)  /* Pin 0 selected    */
+#define GPIO_PIN_1                 ((uint16_t)0x0002)  /* Pin 1 selected    */
+#define GPIO_PIN_2                 ((uint16_t)0x0004)  /* Pin 2 selected    */
+#define GPIO_PIN_3                 ((uint16_t)0x0008)  /* Pin 3 selected    */
+#define GPIO_PIN_4                 ((uint16_t)0x0010)  /* Pin 4 selected    */
+#define GPIO_PIN_5                 ((uint16_t)0x0020)  /* Pin 5 selected    */
+#define GPIO_PIN_6                 ((uint16_t)0x0040)  /* Pin 6 selected    */
+#define GPIO_PIN_7                 ((uint16_t)0x0080)  /* Pin 7 selected    */
+#define GPIO_PIN_8                 ((uint16_t)0x0100)  /* Pin 8 selected    */
+#define GPIO_PIN_9                 ((uint16_t)0x0200)  /* Pin 9 selected    */
+#define GPIO_PIN_10                ((uint16_t)0x0400)  /* Pin 10 selected   */
+#define GPIO_PIN_11                ((uint16_t)0x0800)  /* Pin 11 selected   */
+#define GPIO_PIN_12                ((uint16_t)0x1000)  /* Pin 12 selected   */
+#define GPIO_PIN_13                ((uint16_t)0x2000)  /* Pin 13 selected   */
+#define GPIO_PIN_14                ((uint16_t)0x4000)  /* Pin 14 selected   */
+#define GPIO_PIN_15                ((uint16_t)0x8000)  /* Pin 15 selected   */
+#define GPIO_PIN_All               ((uint16_t)0xFFFF)  /* All pins selected */
+
+#define GPIO_PIN_MASK              0x0000FFFFU /* PIN mask for assert test */
+/**
+  * @}
+  */
+
+/** @defgroup GPIO_mode_define GPIO mode define
+  * @brief GPIO Configuration Mode
+  *        Elements values convention: 0x00WX00YZ
+  *           - W  : EXTI trigger detection on 3 bits
+  *           - X  : EXTI mode (IT or Event) on 2 bits
+  *           - Y  : Output type (Push Pull or Open Drain) on 1 bit
+  *           - Z  : GPIO mode (Input, Output, Alternate or Analog) on 2 bits
+  * @{
+  */ 
+#define  GPIO_MODE_INPUT                        MODE_INPUT                                                  /*!< Input Floating Mode                   */
+#define  GPIO_MODE_OUTPUT_PP                    (MODE_OUTPUT | OUTPUT_PP)                                   /*!< Output Push Pull Mode                 */
+#define  GPIO_MODE_OUTPUT_OD                    (MODE_OUTPUT | OUTPUT_OD)                                   /*!< Output Open Drain Mode                */
+#define  GPIO_MODE_AF_PP                        (MODE_AF | OUTPUT_PP)                                       /*!< Alternate Function Push Pull Mode     */
+#define  GPIO_MODE_AF_OD                        (MODE_AF | OUTPUT_OD)                                       /*!< Alternate Function Open Drain Mode    */
+
+#define  GPIO_MODE_ANALOG                       MODE_ANALOG                                                 /*!< Analog Mode  */
+    
+#define  GPIO_MODE_IT_RISING                    (MODE_INPUT | EXTI_IT | TRIGGER_RISING)                     /*!< External Interrupt Mode with Rising edge trigger detection          */
+#define  GPIO_MODE_IT_FALLING                   (MODE_INPUT | EXTI_IT | TRIGGER_FALLING)                    /*!< External Interrupt Mode with Falling edge trigger detection         */
+#define  GPIO_MODE_IT_RISING_FALLING            (MODE_INPUT | EXTI_IT | TRIGGER_RISING | TRIGGER_FALLING)   /*!< External Interrupt Mode with Rising/Falling edge trigger detection  */
+ 
+#define  GPIO_MODE_EVT_RISING                   (MODE_INPUT | EXTI_EVT | TRIGGER_RISING)                     /*!< External Event Mode with Rising edge trigger detection             */
+#define  GPIO_MODE_EVT_FALLING                  (MODE_INPUT | EXTI_EVT | TRIGGER_FALLING)                    /*!< External Event Mode with Falling edge trigger detection            */
+#define  GPIO_MODE_EVT_RISING_FALLING           (MODE_INPUT | EXTI_EVT | TRIGGER_RISING | TRIGGER_FALLING)   /*!< External Event Mode with Rising/Falling edge trigger detection     */
+
+/**
+  * @}
+  */
+
+/** @defgroup GPIO_speed_define  GPIO speed define
+  * @brief GPIO Output Maximum frequency
+  * @{
+  */
+#define  GPIO_SPEED_FREQ_LOW         0x00000000U  /*!< IO works at 2 MHz, please refer to the product datasheet */
+#define  GPIO_SPEED_FREQ_MEDIUM      0x00000001U  /*!< range 12,5 MHz to 50 MHz, please refer to the product datasheet */
+#define  GPIO_SPEED_FREQ_HIGH        0x00000002U  /*!< range 25 MHz to 100 MHz, please refer to the product datasheet  */
+#define  GPIO_SPEED_FREQ_VERY_HIGH   0x00000003U  /*!< range 50 MHz to 200 MHz, please refer to the product datasheet  */
+/**
+  * @}
+  */
+
+ /** @defgroup GPIO_pull_define GPIO pull define
+   * @brief GPIO Pull-Up or Pull-Down Activation
+   * @{
+   */  
+#define  GPIO_NOPULL        0x00000000U   /*!< No Pull-up or Pull-down activation  */
+#define  GPIO_PULLUP        0x00000001U   /*!< Pull-up activation                  */
+#define  GPIO_PULLDOWN      0x00000002U   /*!< Pull-down activation                */
+/**
+  * @}
+  */
+  
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup GPIO_Exported_Macros GPIO Exported Macros
+  * @{
+  */
+
+/**
+  * @brief  Checks whether the specified EXTI line flag is set or not.
+  * @param  __EXTI_LINE__ specifies the EXTI line flag to check.
+  *         This parameter can be GPIO_PIN_x where x can be(0..15)
+  * @retval The new state of __EXTI_LINE__ (SET or RESET).
+  */
+#define __HAL_GPIO_EXTI_GET_FLAG(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__))
+
+/**
+  * @brief  Clears the EXTI's line pending flags.
+  * @param  __EXTI_LINE__ specifies the EXTI lines flags to clear.
+  *         This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
+  * @retval None
+  */
+#define __HAL_GPIO_EXTI_CLEAR_FLAG(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__))
+
+/**
+  * @brief  Checks whether the specified EXTI line is asserted or not.
+  * @param  __EXTI_LINE__ specifies the EXTI line to check.
+  *          This parameter can be GPIO_PIN_x where x can be(0..15)
+  * @retval The new state of __EXTI_LINE__ (SET or RESET).
+  */
+#define __HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__))
+
+/**
+  * @brief  Clears the EXTI's line pending bits.
+  * @param  __EXTI_LINE__ specifies the EXTI lines to clear.
+  *          This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
+  * @retval None
+  */
+#define __HAL_GPIO_EXTI_CLEAR_IT(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__))
+
+/**
+  * @brief  Generates a Software interrupt on selected EXTI line.
+  * @param  __EXTI_LINE__ specifies the EXTI line to check.
+  *          This parameter can be GPIO_PIN_x where x can be(0..15)
+  * @retval None
+  */
+#define __HAL_GPIO_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER |= (__EXTI_LINE__))
+/**
+  * @}
+  */
+
+/* Include GPIO HAL Extension module */
+#include "stm32f4xx_hal_gpio_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup GPIO_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup GPIO_Exported_Functions_Group1
+  * @{
+  */
+/* Initialization and de-initialization functions *****************************/
+void  HAL_GPIO_Init(GPIO_TypeDef  *GPIOx, GPIO_InitTypeDef *GPIO_Init);
+void  HAL_GPIO_DeInit(GPIO_TypeDef  *GPIOx, uint32_t GPIO_Pin);
+/**
+  * @}
+  */
+
+/** @addtogroup GPIO_Exported_Functions_Group2
+  * @{
+  */
+/* IO operation functions *****************************************************/
+GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
+void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState);
+void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
+HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
+void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin);
+void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin);
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup GPIO_Private_Constants GPIO Private Constants
+  * @{
+  */
+#define GPIO_MODE_Pos                           0U
+#define GPIO_MODE                               (0x3UL << GPIO_MODE_Pos)
+#define MODE_INPUT                              (0x0UL << GPIO_MODE_Pos)
+#define MODE_OUTPUT                             (0x1UL << GPIO_MODE_Pos)
+#define MODE_AF                                 (0x2UL << GPIO_MODE_Pos)
+#define MODE_ANALOG                             (0x3UL << GPIO_MODE_Pos)
+#define OUTPUT_TYPE_Pos                         4U
+#define OUTPUT_TYPE                             (0x1UL << OUTPUT_TYPE_Pos)
+#define OUTPUT_PP                               (0x0UL << OUTPUT_TYPE_Pos)
+#define OUTPUT_OD                               (0x1UL << OUTPUT_TYPE_Pos)
+#define EXTI_MODE_Pos                           16U
+#define EXTI_MODE                               (0x3UL << EXTI_MODE_Pos)
+#define EXTI_IT                                 (0x1UL << EXTI_MODE_Pos)
+#define EXTI_EVT                                (0x2UL << EXTI_MODE_Pos)
+#define TRIGGER_MODE_Pos                         20U
+#define TRIGGER_MODE                            (0x7UL << TRIGGER_MODE_Pos)
+#define TRIGGER_RISING                          (0x1UL << TRIGGER_MODE_Pos)
+#define TRIGGER_FALLING                         (0x2UL << TRIGGER_MODE_Pos)
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup GPIO_Private_Macros GPIO Private Macros
+  * @{
+  */
+#define IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET))
+#define IS_GPIO_PIN(PIN)           (((((uint32_t)PIN) & GPIO_PIN_MASK ) != 0x00U) && ((((uint32_t)PIN) & ~GPIO_PIN_MASK) == 0x00U))
+#define IS_GPIO_MODE(MODE) (((MODE) == GPIO_MODE_INPUT)              ||\
+                            ((MODE) == GPIO_MODE_OUTPUT_PP)          ||\
+                            ((MODE) == GPIO_MODE_OUTPUT_OD)          ||\
+                            ((MODE) == GPIO_MODE_AF_PP)              ||\
+                            ((MODE) == GPIO_MODE_AF_OD)              ||\
+                            ((MODE) == GPIO_MODE_IT_RISING)          ||\
+                            ((MODE) == GPIO_MODE_IT_FALLING)         ||\
+                            ((MODE) == GPIO_MODE_IT_RISING_FALLING)  ||\
+                            ((MODE) == GPIO_MODE_EVT_RISING)         ||\
+                            ((MODE) == GPIO_MODE_EVT_FALLING)        ||\
+                            ((MODE) == GPIO_MODE_EVT_RISING_FALLING) ||\
+                            ((MODE) == GPIO_MODE_ANALOG))
+#define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_SPEED_FREQ_LOW)  || ((SPEED) == GPIO_SPEED_FREQ_MEDIUM) || \
+                              ((SPEED) == GPIO_SPEED_FREQ_HIGH) || ((SPEED) == GPIO_SPEED_FREQ_VERY_HIGH))
+#define IS_GPIO_PULL(PULL) (((PULL) == GPIO_NOPULL) || ((PULL) == GPIO_PULLUP) || \
+                            ((PULL) == GPIO_PULLDOWN))
+/**
+  * @}
+  */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup GPIO_Private_Functions GPIO Private Functions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_GPIO_H */
+
diff --git a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h
new file mode 100644
index 0000000..393f388
--- /dev/null
+++ b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h
@@ -0,0 +1,1590 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hal_gpio_ex.h
+  * @author  MCD Application Team
+  * @brief   Header file of GPIO HAL Extension module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */ 
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_GPIO_EX_H
+#define __STM32F4xx_HAL_GPIO_EX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup GPIOEx GPIOEx
+  * @{
+  */ 
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup GPIOEx_Exported_Constants GPIO Exported Constants
+  * @{
+  */
+  
+/** @defgroup GPIO_Alternate_function_selection GPIO Alternate Function Selection
+  * @{
+  */
+
+/*------------------------------------------ STM32F429xx/STM32F439xx ---------*/
+#if defined(STM32F429xx) || defined(STM32F439xx)
+/** 
+  * @brief   AF 0 selection  
+  */ 
+#define GPIO_AF0_RTC_50Hz      ((uint8_t)0x00)  /* RTC_50Hz Alternate Function mapping                       */
+#define GPIO_AF0_MCO           ((uint8_t)0x00)  /* MCO (MCO1 and MCO2) Alternate Function mapping            */
+#define GPIO_AF0_TAMPER        ((uint8_t)0x00)  /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */
+#define GPIO_AF0_SWJ           ((uint8_t)0x00)  /* SWJ (SWD and JTAG) Alternate Function mapping             */
+#define GPIO_AF0_TRACE         ((uint8_t)0x00)  /* TRACE Alternate Function mapping                          */
+
+/** 
+  * @brief   AF 1 selection  
+  */ 
+#define GPIO_AF1_TIM1          ((uint8_t)0x01)  /* TIM1 Alternate Function mapping */
+#define GPIO_AF1_TIM2          ((uint8_t)0x01)  /* TIM2 Alternate Function mapping */
+
+/** 
+  * @brief   AF 2 selection  
+  */ 
+#define GPIO_AF2_TIM3          ((uint8_t)0x02)  /* TIM3 Alternate Function mapping */
+#define GPIO_AF2_TIM4          ((uint8_t)0x02)  /* TIM4 Alternate Function mapping */
+#define GPIO_AF2_TIM5          ((uint8_t)0x02)  /* TIM5 Alternate Function mapping */
+
+/** 
+  * @brief   AF 3 selection  
+  */ 
+#define GPIO_AF3_TIM8          ((uint8_t)0x03)  /* TIM8 Alternate Function mapping  */
+#define GPIO_AF3_TIM9          ((uint8_t)0x03)  /* TIM9 Alternate Function mapping  */
+#define GPIO_AF3_TIM10         ((uint8_t)0x03)  /* TIM10 Alternate Function mapping */
+#define GPIO_AF3_TIM11         ((uint8_t)0x03)  /* TIM11 Alternate Function mapping */
+
+/** 
+  * @brief   AF 4 selection  
+  */ 
+#define GPIO_AF4_I2C1          ((uint8_t)0x04)  /* I2C1 Alternate Function mapping */
+#define GPIO_AF4_I2C2          ((uint8_t)0x04)  /* I2C2 Alternate Function mapping */
+#define GPIO_AF4_I2C3          ((uint8_t)0x04)  /* I2C3 Alternate Function mapping */
+
+/** 
+  * @brief   AF 5 selection  
+  */ 
+#define GPIO_AF5_SPI1          ((uint8_t)0x05)  /* SPI1 Alternate Function mapping        */
+#define GPIO_AF5_SPI2          ((uint8_t)0x05)  /* SPI2/I2S2 Alternate Function mapping   */
+#define GPIO_AF5_SPI3          ((uint8_t)0x05)  /* SPI3/I2S3 Alternate Function mapping   */
+#define GPIO_AF5_SPI4          ((uint8_t)0x05)  /* SPI4 Alternate Function mapping        */
+#define GPIO_AF5_SPI5          ((uint8_t)0x05)  /* SPI5 Alternate Function mapping        */
+#define GPIO_AF5_SPI6          ((uint8_t)0x05)  /* SPI6 Alternate Function mapping        */
+#define GPIO_AF5_I2S3ext       ((uint8_t)0x05)  /* I2S3ext_SD Alternate Function mapping  */
+
+/** 
+  * @brief   AF 6 selection  
+  */ 
+#define GPIO_AF6_SPI3          ((uint8_t)0x06)  /* SPI3/I2S3 Alternate Function mapping  */
+#define GPIO_AF6_I2S2ext       ((uint8_t)0x06)  /* I2S2ext_SD Alternate Function mapping */
+#define GPIO_AF6_SAI1          ((uint8_t)0x06)  /* SAI1 Alternate Function mapping       */
+
+/** 
+  * @brief   AF 7 selection  
+  */ 
+#define GPIO_AF7_USART1        ((uint8_t)0x07)  /* USART1 Alternate Function mapping     */
+#define GPIO_AF7_USART2        ((uint8_t)0x07)  /* USART2 Alternate Function mapping     */
+#define GPIO_AF7_USART3        ((uint8_t)0x07)  /* USART3 Alternate Function mapping     */
+#define GPIO_AF7_I2S3ext       ((uint8_t)0x07)  /* I2S3ext_SD Alternate Function mapping */
+
+/** 
+  * @brief   AF 8 selection  
+  */ 
+#define GPIO_AF8_UART4         ((uint8_t)0x08)  /* UART4 Alternate Function mapping  */
+#define GPIO_AF8_UART5         ((uint8_t)0x08)  /* UART5 Alternate Function mapping  */
+#define GPIO_AF8_USART6        ((uint8_t)0x08)  /* USART6 Alternate Function mapping */
+#define GPIO_AF8_UART7         ((uint8_t)0x08)  /* UART7 Alternate Function mapping  */
+#define GPIO_AF8_UART8         ((uint8_t)0x08)  /* UART8 Alternate Function mapping  */
+
+/** 
+  * @brief   AF 9 selection 
+  */ 
+#define GPIO_AF9_CAN1          ((uint8_t)0x09)  /* CAN1 Alternate Function mapping    */
+#define GPIO_AF9_CAN2          ((uint8_t)0x09)  /* CAN2 Alternate Function mapping    */
+#define GPIO_AF9_TIM12         ((uint8_t)0x09)  /* TIM12 Alternate Function mapping   */
+#define GPIO_AF9_TIM13         ((uint8_t)0x09)  /* TIM13 Alternate Function mapping   */
+#define GPIO_AF9_TIM14         ((uint8_t)0x09)  /* TIM14 Alternate Function mapping   */
+#define GPIO_AF9_LTDC          ((uint8_t)0x09)  /* LCD-TFT Alternate Function mapping */
+
+/** 
+  * @brief   AF 10 selection  
+  */ 
+#define GPIO_AF10_OTG_FS        ((uint8_t)0x0A)  /* OTG_FS Alternate Function mapping */
+#define GPIO_AF10_OTG_HS        ((uint8_t)0x0A)  /* OTG_HS Alternate Function mapping */
+
+/** 
+  * @brief   AF 11 selection  
+  */ 
+#define GPIO_AF11_ETH           ((uint8_t)0x0B)  /* ETHERNET Alternate Function mapping */
+
+/** 
+  * @brief   AF 12 selection  
+  */ 
+#define GPIO_AF12_FMC           ((uint8_t)0x0C)  /* FMC Alternate Function mapping                      */
+#define GPIO_AF12_OTG_HS_FS     ((uint8_t)0x0C)  /* OTG HS configured in FS, Alternate Function mapping */
+#define GPIO_AF12_SDIO          ((uint8_t)0x0C)  /* SDIO Alternate Function mapping                     */
+
+/** 
+  * @brief   AF 13 selection  
+  */ 
+#define GPIO_AF13_DCMI          ((uint8_t)0x0D)  /* DCMI Alternate Function mapping */
+
+/** 
+  * @brief   AF 14 selection  
+  */
+#define GPIO_AF14_LTDC          ((uint8_t)0x0E)  /* LCD-TFT Alternate Function mapping */
+
+/** 
+  * @brief   AF 15 selection  
+  */ 
+#define GPIO_AF15_EVENTOUT      ((uint8_t)0x0F)  /* EVENTOUT Alternate Function mapping */
+#endif /* STM32F429xx || STM32F439xx */
+/*----------------------------------------------------------------------------*/
+
+/*---------------------------------- STM32F427xx/STM32F437xx------------------*/
+#if defined(STM32F427xx) || defined(STM32F437xx)
+/** 
+  * @brief   AF 0 selection  
+  */ 
+#define GPIO_AF0_RTC_50Hz      ((uint8_t)0x00)  /* RTC_50Hz Alternate Function mapping                       */
+#define GPIO_AF0_MCO           ((uint8_t)0x00)  /* MCO (MCO1 and MCO2) Alternate Function mapping            */
+#define GPIO_AF0_TAMPER        ((uint8_t)0x00)  /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */
+#define GPIO_AF0_SWJ           ((uint8_t)0x00)  /* SWJ (SWD and JTAG) Alternate Function mapping             */
+#define GPIO_AF0_TRACE         ((uint8_t)0x00)  /* TRACE Alternate Function mapping                          */
+
+/** 
+  * @brief   AF 1 selection  
+  */ 
+#define GPIO_AF1_TIM1          ((uint8_t)0x01)  /* TIM1 Alternate Function mapping */
+#define GPIO_AF1_TIM2          ((uint8_t)0x01)  /* TIM2 Alternate Function mapping */
+
+/** 
+  * @brief   AF 2 selection  
+  */ 
+#define GPIO_AF2_TIM3          ((uint8_t)0x02)  /* TIM3 Alternate Function mapping */
+#define GPIO_AF2_TIM4          ((uint8_t)0x02)  /* TIM4 Alternate Function mapping */
+#define GPIO_AF2_TIM5          ((uint8_t)0x02)  /* TIM5 Alternate Function mapping */
+
+/** 
+  * @brief   AF 3 selection  
+  */ 
+#define GPIO_AF3_TIM8          ((uint8_t)0x03)  /* TIM8 Alternate Function mapping  */
+#define GPIO_AF3_TIM9          ((uint8_t)0x03)  /* TIM9 Alternate Function mapping  */
+#define GPIO_AF3_TIM10         ((uint8_t)0x03)  /* TIM10 Alternate Function mapping */
+#define GPIO_AF3_TIM11         ((uint8_t)0x03)  /* TIM11 Alternate Function mapping */
+
+/** 
+  * @brief   AF 4 selection  
+  */ 
+#define GPIO_AF4_I2C1          ((uint8_t)0x04)  /* I2C1 Alternate Function mapping */
+#define GPIO_AF4_I2C2          ((uint8_t)0x04)  /* I2C2 Alternate Function mapping */
+#define GPIO_AF4_I2C3          ((uint8_t)0x04)  /* I2C3 Alternate Function mapping */
+
+/** 
+  * @brief   AF 5 selection  
+  */ 
+#define GPIO_AF5_SPI1          ((uint8_t)0x05)  /* SPI1 Alternate Function mapping        */
+#define GPIO_AF5_SPI2          ((uint8_t)0x05)  /* SPI2/I2S2 Alternate Function mapping   */
+#define GPIO_AF5_SPI3          ((uint8_t)0x05)  /* SPI3/I2S3 Alternate Function mapping   */
+#define GPIO_AF5_SPI4          ((uint8_t)0x05)  /* SPI4 Alternate Function mapping        */
+#define GPIO_AF5_SPI5          ((uint8_t)0x05)  /* SPI5 Alternate Function mapping        */
+#define GPIO_AF5_SPI6          ((uint8_t)0x05)  /* SPI6 Alternate Function mapping        */
+/** @brief  GPIO_Legacy 
+  */
+#define GPIO_AF5_I2S3ext       GPIO_AF5_SPI3   /* I2S3ext_SD Alternate Function mapping  */
+
+/** 
+  * @brief   AF 6 selection  
+  */ 
+#define GPIO_AF6_SPI3          ((uint8_t)0x06)  /* SPI3/I2S3 Alternate Function mapping  */
+#define GPIO_AF6_I2S2ext       ((uint8_t)0x06)  /* I2S2ext_SD Alternate Function mapping */
+#define GPIO_AF6_SAI1          ((uint8_t)0x06)  /* SAI1 Alternate Function mapping       */
+
+/** 
+  * @brief   AF 7 selection  
+  */ 
+#define GPIO_AF7_USART1        ((uint8_t)0x07)  /* USART1 Alternate Function mapping     */
+#define GPIO_AF7_USART2        ((uint8_t)0x07)  /* USART2 Alternate Function mapping     */
+#define GPIO_AF7_USART3        ((uint8_t)0x07)  /* USART3 Alternate Function mapping     */
+#define GPIO_AF7_I2S3ext       ((uint8_t)0x07)  /* I2S3ext_SD Alternate Function mapping */
+
+/** 
+  * @brief   AF 8 selection  
+  */ 
+#define GPIO_AF8_UART4         ((uint8_t)0x08)  /* UART4 Alternate Function mapping  */
+#define GPIO_AF8_UART5         ((uint8_t)0x08)  /* UART5 Alternate Function mapping  */
+#define GPIO_AF8_USART6        ((uint8_t)0x08)  /* USART6 Alternate Function mapping */
+#define GPIO_AF8_UART7         ((uint8_t)0x08)  /* UART7 Alternate Function mapping  */
+#define GPIO_AF8_UART8         ((uint8_t)0x08)  /* UART8 Alternate Function mapping  */
+
+/** 
+  * @brief   AF 9 selection 
+  */ 
+#define GPIO_AF9_CAN1          ((uint8_t)0x09)  /* CAN1 Alternate Function mapping  */
+#define GPIO_AF9_CAN2          ((uint8_t)0x09)  /* CAN2 Alternate Function mapping  */
+#define GPIO_AF9_TIM12         ((uint8_t)0x09)  /* TIM12 Alternate Function mapping */
+#define GPIO_AF9_TIM13         ((uint8_t)0x09)  /* TIM13 Alternate Function mapping */
+#define GPIO_AF9_TIM14         ((uint8_t)0x09)  /* TIM14 Alternate Function mapping */
+
+/** 
+  * @brief   AF 10 selection  
+  */ 
+#define GPIO_AF10_OTG_FS        ((uint8_t)0x0A)  /* OTG_FS Alternate Function mapping */
+#define GPIO_AF10_OTG_HS        ((uint8_t)0x0A)  /* OTG_HS Alternate Function mapping */
+
+/** 
+  * @brief   AF 11 selection  
+  */ 
+#define GPIO_AF11_ETH           ((uint8_t)0x0B)  /* ETHERNET Alternate Function mapping */
+
+/** 
+  * @brief   AF 12 selection  
+  */ 
+#define GPIO_AF12_FMC           ((uint8_t)0x0C)  /* FMC Alternate Function mapping                      */
+#define GPIO_AF12_OTG_HS_FS     ((uint8_t)0x0C)  /* OTG HS configured in FS, Alternate Function mapping */
+#define GPIO_AF12_SDIO          ((uint8_t)0x0C)  /* SDIO Alternate Function mapping                     */
+
+/** 
+  * @brief   AF 13 selection  
+  */ 
+#define GPIO_AF13_DCMI          ((uint8_t)0x0D)  /* DCMI Alternate Function mapping */
+
+/** 
+  * @brief   AF 15 selection  
+  */ 
+#define GPIO_AF15_EVENTOUT      ((uint8_t)0x0F)  /* EVENTOUT Alternate Function mapping */
+#endif /* STM32F427xx || STM32F437xx */
+/*----------------------------------------------------------------------------*/
+
+/*---------------------------------- STM32F407xx/STM32F417xx------------------*/
+#if defined(STM32F407xx) || defined(STM32F417xx)
+/** 
+  * @brief   AF 0 selection  
+  */ 
+#define GPIO_AF0_RTC_50Hz      ((uint8_t)0x00)  /* RTC_50Hz Alternate Function mapping                       */
+#define GPIO_AF0_MCO           ((uint8_t)0x00)  /* MCO (MCO1 and MCO2) Alternate Function mapping            */
+#define GPIO_AF0_TAMPER        ((uint8_t)0x00)  /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */
+#define GPIO_AF0_SWJ           ((uint8_t)0x00)  /* SWJ (SWD and JTAG) Alternate Function mapping             */
+#define GPIO_AF0_TRACE         ((uint8_t)0x00)  /* TRACE Alternate Function mapping                          */
+
+/** 
+  * @brief   AF 1 selection  
+  */ 
+#define GPIO_AF1_TIM1          ((uint8_t)0x01)  /* TIM1 Alternate Function mapping */
+#define GPIO_AF1_TIM2          ((uint8_t)0x01)  /* TIM2 Alternate Function mapping */
+
+/** 
+  * @brief   AF 2 selection  
+  */ 
+#define GPIO_AF2_TIM3          ((uint8_t)0x02)  /* TIM3 Alternate Function mapping */
+#define GPIO_AF2_TIM4          ((uint8_t)0x02)  /* TIM4 Alternate Function mapping */
+#define GPIO_AF2_TIM5          ((uint8_t)0x02)  /* TIM5 Alternate Function mapping */
+
+/** 
+  * @brief   AF 3 selection  
+  */ 
+#define GPIO_AF3_TIM8          ((uint8_t)0x03)  /* TIM8 Alternate Function mapping  */
+#define GPIO_AF3_TIM9          ((uint8_t)0x03)  /* TIM9 Alternate Function mapping  */
+#define GPIO_AF3_TIM10         ((uint8_t)0x03)  /* TIM10 Alternate Function mapping */
+#define GPIO_AF3_TIM11         ((uint8_t)0x03)  /* TIM11 Alternate Function mapping */
+
+/** 
+  * @brief   AF 4 selection  
+  */ 
+#define GPIO_AF4_I2C1          ((uint8_t)0x04)  /* I2C1 Alternate Function mapping */
+#define GPIO_AF4_I2C2          ((uint8_t)0x04)  /* I2C2 Alternate Function mapping */
+#define GPIO_AF4_I2C3          ((uint8_t)0x04)  /* I2C3 Alternate Function mapping */
+
+/** 
+  * @brief   AF 5 selection  
+  */ 
+#define GPIO_AF5_SPI1          ((uint8_t)0x05)  /* SPI1 Alternate Function mapping        */
+#define GPIO_AF5_SPI2          ((uint8_t)0x05)  /* SPI2/I2S2 Alternate Function mapping   */
+#define GPIO_AF5_I2S3ext       ((uint8_t)0x05)  /* I2S3ext_SD Alternate Function mapping  */
+
+/** 
+  * @brief   AF 6 selection  
+  */ 
+#define GPIO_AF6_SPI3          ((uint8_t)0x06)  /* SPI3/I2S3 Alternate Function mapping  */
+#define GPIO_AF6_I2S2ext       ((uint8_t)0x06)  /* I2S2ext_SD Alternate Function mapping */
+
+/** 
+  * @brief   AF 7 selection  
+  */ 
+#define GPIO_AF7_USART1        ((uint8_t)0x07)  /* USART1 Alternate Function mapping     */
+#define GPIO_AF7_USART2        ((uint8_t)0x07)  /* USART2 Alternate Function mapping     */
+#define GPIO_AF7_USART3        ((uint8_t)0x07)  /* USART3 Alternate Function mapping     */
+#define GPIO_AF7_I2S3ext       ((uint8_t)0x07)  /* I2S3ext_SD Alternate Function mapping */
+
+/** 
+  * @brief   AF 8 selection  
+  */ 
+#define GPIO_AF8_UART4         ((uint8_t)0x08)  /* UART4 Alternate Function mapping  */
+#define GPIO_AF8_UART5         ((uint8_t)0x08)  /* UART5 Alternate Function mapping  */
+#define GPIO_AF8_USART6        ((uint8_t)0x08)  /* USART6 Alternate Function mapping */
+
+/** 
+  * @brief   AF 9 selection 
+  */ 
+#define GPIO_AF9_CAN1          ((uint8_t)0x09)  /* CAN1 Alternate Function mapping  */
+#define GPIO_AF9_CAN2          ((uint8_t)0x09)  /* CAN2 Alternate Function mapping  */
+#define GPIO_AF9_TIM12         ((uint8_t)0x09)  /* TIM12 Alternate Function mapping */
+#define GPIO_AF9_TIM13         ((uint8_t)0x09)  /* TIM13 Alternate Function mapping */
+#define GPIO_AF9_TIM14         ((uint8_t)0x09)  /* TIM14 Alternate Function mapping */
+
+/** 
+  * @brief   AF 10 selection  
+  */ 
+#define GPIO_AF10_OTG_FS        ((uint8_t)0x0A)  /* OTG_FS Alternate Function mapping */
+#define GPIO_AF10_OTG_HS        ((uint8_t)0x0A)  /* OTG_HS Alternate Function mapping */
+
+/** 
+  * @brief   AF 11 selection  
+  */ 
+#define GPIO_AF11_ETH           ((uint8_t)0x0B)  /* ETHERNET Alternate Function mapping */
+
+/** 
+  * @brief   AF 12 selection  
+  */ 
+#define GPIO_AF12_FSMC          ((uint8_t)0x0C)  /* FSMC Alternate Function mapping                     */
+#define GPIO_AF12_OTG_HS_FS     ((uint8_t)0x0C)  /* OTG HS configured in FS, Alternate Function mapping */
+#define GPIO_AF12_SDIO          ((uint8_t)0x0C)  /* SDIO Alternate Function mapping                     */
+
+/** 
+  * @brief   AF 13 selection  
+  */ 
+#define GPIO_AF13_DCMI          ((uint8_t)0x0D)  /* DCMI Alternate Function mapping */
+
+/** 
+  * @brief   AF 15 selection  
+  */ 
+#define GPIO_AF15_EVENTOUT      ((uint8_t)0x0F)  /* EVENTOUT Alternate Function mapping */
+#endif /* STM32F407xx || STM32F417xx */
+/*----------------------------------------------------------------------------*/
+
+/*---------------------------------- STM32F405xx/STM32F415xx------------------*/
+#if defined(STM32F405xx) || defined(STM32F415xx)
+/** 
+  * @brief   AF 0 selection  
+  */ 
+#define GPIO_AF0_RTC_50Hz      ((uint8_t)0x00)  /* RTC_50Hz Alternate Function mapping                       */
+#define GPIO_AF0_MCO           ((uint8_t)0x00)  /* MCO (MCO1 and MCO2) Alternate Function mapping            */
+#define GPIO_AF0_TAMPER        ((uint8_t)0x00)  /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */
+#define GPIO_AF0_SWJ           ((uint8_t)0x00)  /* SWJ (SWD and JTAG) Alternate Function mapping             */
+#define GPIO_AF0_TRACE         ((uint8_t)0x00)  /* TRACE Alternate Function mapping                          */
+
+/** 
+  * @brief   AF 1 selection  
+  */ 
+#define GPIO_AF1_TIM1          ((uint8_t)0x01)  /* TIM1 Alternate Function mapping */
+#define GPIO_AF1_TIM2          ((uint8_t)0x01)  /* TIM2 Alternate Function mapping */
+
+/** 
+  * @brief   AF 2 selection  
+  */ 
+#define GPIO_AF2_TIM3          ((uint8_t)0x02)  /* TIM3 Alternate Function mapping */
+#define GPIO_AF2_TIM4          ((uint8_t)0x02)  /* TIM4 Alternate Function mapping */
+#define GPIO_AF2_TIM5          ((uint8_t)0x02)  /* TIM5 Alternate Function mapping */
+
+/** 
+  * @brief   AF 3 selection  
+  */ 
+#define GPIO_AF3_TIM8          ((uint8_t)0x03)  /* TIM8 Alternate Function mapping  */
+#define GPIO_AF3_TIM9          ((uint8_t)0x03)  /* TIM9 Alternate Function mapping  */
+#define GPIO_AF3_TIM10         ((uint8_t)0x03)  /* TIM10 Alternate Function mapping */
+#define GPIO_AF3_TIM11         ((uint8_t)0x03)  /* TIM11 Alternate Function mapping */
+
+/** 
+  * @brief   AF 4 selection  
+  */ 
+#define GPIO_AF4_I2C1          ((uint8_t)0x04)  /* I2C1 Alternate Function mapping */
+#define GPIO_AF4_I2C2          ((uint8_t)0x04)  /* I2C2 Alternate Function mapping */
+#define GPIO_AF4_I2C3          ((uint8_t)0x04)  /* I2C3 Alternate Function mapping */
+
+/** 
+  * @brief   AF 5 selection  
+  */ 
+#define GPIO_AF5_SPI1          ((uint8_t)0x05)  /* SPI1 Alternate Function mapping        */
+#define GPIO_AF5_SPI2          ((uint8_t)0x05)  /* SPI2/I2S2 Alternate Function mapping   */
+#define GPIO_AF5_I2S3ext       ((uint8_t)0x05)  /* I2S3ext_SD Alternate Function mapping  */
+
+/** 
+  * @brief   AF 6 selection  
+  */ 
+#define GPIO_AF6_SPI3          ((uint8_t)0x06)  /* SPI3/I2S3 Alternate Function mapping  */
+#define GPIO_AF6_I2S2ext       ((uint8_t)0x06)  /* I2S2ext_SD Alternate Function mapping */
+
+/** 
+  * @brief   AF 7 selection  
+  */ 
+#define GPIO_AF7_USART1        ((uint8_t)0x07)  /* USART1 Alternate Function mapping     */
+#define GPIO_AF7_USART2        ((uint8_t)0x07)  /* USART2 Alternate Function mapping     */
+#define GPIO_AF7_USART3        ((uint8_t)0x07)  /* USART3 Alternate Function mapping     */
+#define GPIO_AF7_I2S3ext       ((uint8_t)0x07)  /* I2S3ext_SD Alternate Function mapping */
+
+/** 
+  * @brief   AF 8 selection  
+  */ 
+#define GPIO_AF8_UART4         ((uint8_t)0x08)  /* UART4 Alternate Function mapping  */
+#define GPIO_AF8_UART5         ((uint8_t)0x08)  /* UART5 Alternate Function mapping  */
+#define GPIO_AF8_USART6        ((uint8_t)0x08)  /* USART6 Alternate Function mapping */
+
+/** 
+  * @brief   AF 9 selection 
+  */ 
+#define GPIO_AF9_CAN1          ((uint8_t)0x09)  /* CAN1 Alternate Function mapping  */
+#define GPIO_AF9_CAN2          ((uint8_t)0x09)  /* CAN2 Alternate Function mapping  */
+#define GPIO_AF9_TIM12         ((uint8_t)0x09)  /* TIM12 Alternate Function mapping */
+#define GPIO_AF9_TIM13         ((uint8_t)0x09)  /* TIM13 Alternate Function mapping */
+#define GPIO_AF9_TIM14         ((uint8_t)0x09)  /* TIM14 Alternate Function mapping */
+
+/** 
+  * @brief   AF 10 selection  
+  */ 
+#define GPIO_AF10_OTG_FS        ((uint8_t)0x0A)  /* OTG_FS Alternate Function mapping */
+#define GPIO_AF10_OTG_HS        ((uint8_t)0x0A)  /* OTG_HS Alternate Function mapping */
+
+/** 
+  * @brief   AF 12 selection  
+  */ 
+#define GPIO_AF12_FSMC          ((uint8_t)0x0C)  /* FSMC Alternate Function mapping                     */
+#define GPIO_AF12_OTG_HS_FS     ((uint8_t)0x0C)  /* OTG HS configured in FS, Alternate Function mapping */
+#define GPIO_AF12_SDIO          ((uint8_t)0x0C)  /* SDIO Alternate Function mapping                     */
+
+/** 
+  * @brief   AF 15 selection  
+  */ 
+#define GPIO_AF15_EVENTOUT      ((uint8_t)0x0F)  /* EVENTOUT Alternate Function mapping */
+#endif /* STM32F405xx || STM32F415xx */
+
+/*----------------------------------------------------------------------------*/
+
+/*---------------------------------------- STM32F401xx------------------------*/
+#if defined(STM32F401xC) || defined(STM32F401xE) 
+/** 
+  * @brief   AF 0 selection  
+  */ 
+#define GPIO_AF0_RTC_50Hz      ((uint8_t)0x00)  /* RTC_50Hz Alternate Function mapping                       */
+#define GPIO_AF0_MCO           ((uint8_t)0x00)  /* MCO (MCO1 and MCO2) Alternate Function mapping            */
+#define GPIO_AF0_TAMPER        ((uint8_t)0x00)  /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */
+#define GPIO_AF0_SWJ           ((uint8_t)0x00)  /* SWJ (SWD and JTAG) Alternate Function mapping             */
+#define GPIO_AF0_TRACE         ((uint8_t)0x00)  /* TRACE Alternate Function mapping                          */
+
+/** 
+  * @brief   AF 1 selection  
+  */ 
+#define GPIO_AF1_TIM1          ((uint8_t)0x01)  /* TIM1 Alternate Function mapping */
+#define GPIO_AF1_TIM2          ((uint8_t)0x01)  /* TIM2 Alternate Function mapping */
+
+/** 
+  * @brief   AF 2 selection  
+  */ 
+#define GPIO_AF2_TIM3          ((uint8_t)0x02)  /* TIM3 Alternate Function mapping */
+#define GPIO_AF2_TIM4          ((uint8_t)0x02)  /* TIM4 Alternate Function mapping */
+#define GPIO_AF2_TIM5          ((uint8_t)0x02)  /* TIM5 Alternate Function mapping */
+
+/** 
+  * @brief   AF 3 selection  
+  */ 
+#define GPIO_AF3_TIM9          ((uint8_t)0x03)  /* TIM9 Alternate Function mapping  */
+#define GPIO_AF3_TIM10         ((uint8_t)0x03)  /* TIM10 Alternate Function mapping */
+#define GPIO_AF3_TIM11         ((uint8_t)0x03)  /* TIM11 Alternate Function mapping */
+
+/** 
+  * @brief   AF 4 selection  
+  */ 
+#define GPIO_AF4_I2C1          ((uint8_t)0x04)  /* I2C1 Alternate Function mapping */
+#define GPIO_AF4_I2C2          ((uint8_t)0x04)  /* I2C2 Alternate Function mapping */
+#define GPIO_AF4_I2C3          ((uint8_t)0x04)  /* I2C3 Alternate Function mapping */
+
+/** 
+  * @brief   AF 5 selection  
+  */ 
+#define GPIO_AF5_SPI1          ((uint8_t)0x05)  /* SPI1 Alternate Function mapping        */
+#define GPIO_AF5_SPI2          ((uint8_t)0x05)  /* SPI2/I2S2 Alternate Function mapping   */
+#define GPIO_AF5_SPI3          ((uint8_t)0x05)  /* SPI3 Alternate Function mapping        */
+#define GPIO_AF5_SPI4          ((uint8_t)0x05)  /* SPI4 Alternate Function mapping        */
+#define GPIO_AF5_I2S3ext       ((uint8_t)0x05)  /* I2S3ext_SD Alternate Function mapping  */
+
+/** 
+  * @brief   AF 6 selection  
+  */ 
+#define GPIO_AF6_SPI3          ((uint8_t)0x06)  /* SPI3/I2S3 Alternate Function mapping  */
+#define GPIO_AF6_I2S2ext       ((uint8_t)0x06)  /* I2S2ext_SD Alternate Function mapping */
+
+/** 
+  * @brief   AF 7 selection  
+  */ 
+#define GPIO_AF7_USART1        ((uint8_t)0x07)  /* USART1 Alternate Function mapping     */
+#define GPIO_AF7_USART2        ((uint8_t)0x07)  /* USART2 Alternate Function mapping     */
+#define GPIO_AF7_I2S3ext       ((uint8_t)0x07)  /* I2S3ext_SD Alternate Function mapping */
+
+/** 
+  * @brief   AF 8 selection  
+  */ 
+#define GPIO_AF8_USART6        ((uint8_t)0x08)  /* USART6 Alternate Function mapping */
+
+/** 
+  * @brief   AF 9 selection 
+  */ 
+#define GPIO_AF9_I2C2          ((uint8_t)0x09)  /* I2C2 Alternate Function mapping  */
+#define GPIO_AF9_I2C3          ((uint8_t)0x09)  /* I2C3 Alternate Function mapping  */
+
+
+/** 
+  * @brief   AF 10 selection  
+  */ 
+#define GPIO_AF10_OTG_FS        ((uint8_t)0x0A)  /* OTG_FS Alternate Function mapping */
+
+/** 
+  * @brief   AF 12 selection  
+  */ 
+#define GPIO_AF12_SDIO          ((uint8_t)0x0C)  /* SDIO Alternate Function mapping  */
+
+/** 
+  * @brief   AF 15 selection  
+  */ 
+#define GPIO_AF15_EVENTOUT      ((uint8_t)0x0F)  /* EVENTOUT Alternate Function mapping */
+#endif /* STM32F401xC || STM32F401xE */
+/*----------------------------------------------------------------------------*/
+
+/*--------------- STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx-------------*/
+#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx)   
+/** 
+  * @brief   AF 0 selection  
+  */ 
+#define GPIO_AF0_RTC_50Hz      ((uint8_t)0x00)  /* RTC_50Hz Alternate Function mapping                       */
+#define GPIO_AF0_MCO           ((uint8_t)0x00)  /* MCO (MCO1 and MCO2) Alternate Function mapping            */
+#define GPIO_AF0_TAMPER        ((uint8_t)0x00)  /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */
+#define GPIO_AF0_SWJ           ((uint8_t)0x00)  /* SWJ (SWD and JTAG) Alternate Function mapping             */
+#define GPIO_AF0_TRACE         ((uint8_t)0x00)  /* TRACE Alternate Function mapping                          */
+
+/** 
+  * @brief   AF 1 selection  
+  */ 
+#define GPIO_AF1_TIM1          ((uint8_t)0x01)  /* TIM1 Alternate Function mapping */
+#define GPIO_AF1_TIM2          ((uint8_t)0x01)  /* TIM2 Alternate Function mapping */
+
+/** 
+  * @brief   AF 2 selection  
+  */ 
+#define GPIO_AF2_TIM3          ((uint8_t)0x02)  /* TIM3 Alternate Function mapping */
+#define GPIO_AF2_TIM4          ((uint8_t)0x02)  /* TIM4 Alternate Function mapping */
+#define GPIO_AF2_TIM5          ((uint8_t)0x02)  /* TIM5 Alternate Function mapping */
+
+/** 
+  * @brief   AF 3 selection  
+  */ 
+#define GPIO_AF3_TIM8          ((uint8_t)0x03)  /* TIM8 Alternate Function mapping  */
+#define GPIO_AF3_TIM9          ((uint8_t)0x03)  /* TIM9 Alternate Function mapping  */
+#define GPIO_AF3_TIM10         ((uint8_t)0x03)  /* TIM10 Alternate Function mapping */
+#define GPIO_AF3_TIM11         ((uint8_t)0x03)  /* TIM11 Alternate Function mapping */
+
+/** 
+  * @brief   AF 4 selection  
+  */ 
+#define GPIO_AF4_I2C1          ((uint8_t)0x04)  /* I2C1 Alternate Function mapping    */
+#define GPIO_AF4_I2C2          ((uint8_t)0x04)  /* I2C2 Alternate Function mapping    */
+#define GPIO_AF4_I2C3          ((uint8_t)0x04)  /* I2C3 Alternate Function mapping    */
+#define GPIO_AF4_FMPI2C1       ((uint8_t)0x04)  /* FMPI2C1 Alternate Function mapping */
+
+/** 
+  * @brief   AF 5 selection  
+  */ 
+#define GPIO_AF5_SPI1          ((uint8_t)0x05)  /* SPI1/I2S1 Alternate Function mapping   */
+#define GPIO_AF5_SPI2          ((uint8_t)0x05)  /* SPI2/I2S2 Alternate Function mapping   */
+#define GPIO_AF5_SPI3          ((uint8_t)0x05)  /* SPI3/I2S3 Alternate Function mapping   */
+#define GPIO_AF5_SPI4          ((uint8_t)0x05)  /* SPI4/I2S4 Alternate Function mapping   */
+#define GPIO_AF5_I2S3ext       ((uint8_t)0x05)  /* I2S3ext_SD Alternate Function mapping  */
+
+/** 
+  * @brief   AF 6 selection  
+  */
+#define GPIO_AF6_SPI2          ((uint8_t)0x06)  /* I2S2 Alternate Function mapping       */
+#define GPIO_AF6_SPI3          ((uint8_t)0x06)  /* SPI3/I2S3 Alternate Function mapping  */
+#define GPIO_AF6_SPI4          ((uint8_t)0x06)  /* SPI4/I2S4 Alternate Function mapping  */
+#define GPIO_AF6_SPI5          ((uint8_t)0x06)  /* SPI5/I2S5 Alternate Function mapping  */
+#define GPIO_AF6_I2S2ext       ((uint8_t)0x06)  /* I2S2ext_SD Alternate Function mapping */
+#define GPIO_AF6_DFSDM1        ((uint8_t)0x06)  /* DFSDM1 Alternate Function mapping     */
+/** 
+  * @brief   AF 7 selection  
+  */ 
+#define GPIO_AF7_SPI3          ((uint8_t)0x07)  /* SPI3/I2S3 Alternate Function mapping  */
+#define GPIO_AF7_USART1        ((uint8_t)0x07)  /* USART1 Alternate Function mapping     */
+#define GPIO_AF7_USART2        ((uint8_t)0x07)  /* USART2 Alternate Function mapping     */
+#define GPIO_AF7_USART3        ((uint8_t)0x07)  /* USART3 Alternate Function mapping     */
+#define GPIO_AF7_I2S3ext       ((uint8_t)0x07)  /* I2S3ext_SD Alternate Function mapping */
+
+/** 
+  * @brief   AF 8 selection  
+  */ 
+#define GPIO_AF8_USART6        ((uint8_t)0x08)  /* USART6 Alternate Function mapping */
+#define GPIO_AF8_USART3        ((uint8_t)0x08)  /* USART3 Alternate Function mapping */
+#define GPIO_AF8_DFSDM1        ((uint8_t)0x08)  /* DFSDM1 Alternate Function mapping */
+#define GPIO_AF8_CAN1          ((uint8_t)0x08)  /* CAN1 Alternate Function mapping   */
+
+/** 
+  * @brief   AF 9 selection 
+  */
+#define GPIO_AF9_TIM12         ((uint8_t)0x09)  /* TIM12 Alternate Function mapping   */
+#define GPIO_AF9_TIM13         ((uint8_t)0x09)  /* TIM13 Alternate Function mapping   */
+#define GPIO_AF9_TIM14         ((uint8_t)0x09)  /* TIM14 Alternate Function mapping   */
+#define GPIO_AF9_I2C2          ((uint8_t)0x09)  /* I2C2 Alternate Function mapping    */
+#define GPIO_AF9_I2C3          ((uint8_t)0x09)  /* I2C3 Alternate Function mapping    */
+#define GPIO_AF9_FMPI2C1       ((uint8_t)0x09)  /* FMPI2C1 Alternate Function mapping */
+#define GPIO_AF9_CAN1          ((uint8_t)0x09)  /* CAN1 Alternate Function mapping    */
+#define GPIO_AF9_CAN2          ((uint8_t)0x09)  /* CAN1 Alternate Function mapping    */  
+#define GPIO_AF9_QSPI          ((uint8_t)0x09)  /* QSPI Alternate Function mapping    */
+
+/** 
+  * @brief   AF 10 selection  
+  */ 
+#define GPIO_AF10_OTG_FS        ((uint8_t)0x0A)  /* OTG_FS Alternate Function mapping */
+#define GPIO_AF10_DFSDM1        ((uint8_t)0x0A)  /* DFSDM1 Alternate Function mapping */
+#define GPIO_AF10_QSPI          ((uint8_t)0x0A)  /* QSPI Alternate Function mapping   */
+#define GPIO_AF10_FMC           ((uint8_t)0x0A)  /* FMC Alternate Function mapping    */
+
+/** 
+  * @brief   AF 12 selection  
+  */ 
+#define GPIO_AF12_SDIO          ((uint8_t)0x0C)  /* SDIO Alternate Function mapping  */
+#define GPIO_AF12_FSMC          ((uint8_t)0x0C)  /* FMC Alternate Function mapping   */
+
+/** 
+  * @brief   AF 15 selection  
+  */ 
+#define GPIO_AF15_EVENTOUT      ((uint8_t)0x0F)  /* EVENTOUT Alternate Function mapping */
+#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */
+
+/*----------------------------------------------------------------------------*/
+
+/*--------------- STM32F413xx/STM32F423xx-------------------------------------*/
+#if defined(STM32F413xx) || defined(STM32F423xx)   
+/** 
+  * @brief   AF 0 selection  
+  */ 
+#define GPIO_AF0_RTC_50Hz      ((uint8_t)0x00)  /* RTC_50Hz Alternate Function mapping                       */
+#define GPIO_AF0_MCO           ((uint8_t)0x00)  /* MCO (MCO1 and MCO2) Alternate Function mapping            */
+#define GPIO_AF0_SWJ           ((uint8_t)0x00)  /* SWJ (SWD and JTAG) Alternate Function mapping             */
+#define GPIO_AF0_TRACE         ((uint8_t)0x00)  /* TRACE Alternate Function mapping                          */
+
+/** 
+  * @brief   AF 1 selection  
+  */ 
+#define GPIO_AF1_TIM1          ((uint8_t)0x01)  /* TIM1 Alternate Function mapping */
+#define GPIO_AF1_TIM2          ((uint8_t)0x01)  /* TIM2 Alternate Function mapping */
+#define GPIO_AF1_LPTIM1        ((uint8_t)0x01)  /* LPTIM1 Alternate Function mapping */
+
+/** 
+  * @brief   AF 2 selection  
+  */ 
+#define GPIO_AF2_TIM3          ((uint8_t)0x02)  /* TIM3 Alternate Function mapping */
+#define GPIO_AF2_TIM4          ((uint8_t)0x02)  /* TIM4 Alternate Function mapping */
+#define GPIO_AF2_TIM5          ((uint8_t)0x02)  /* TIM5 Alternate Function mapping */
+
+/** 
+  * @brief   AF 3 selection  
+  */ 
+#define GPIO_AF3_TIM8          ((uint8_t)0x03)  /* TIM8 Alternate Function mapping  */
+#define GPIO_AF3_TIM9          ((uint8_t)0x03)  /* TIM9 Alternate Function mapping  */
+#define GPIO_AF3_TIM10         ((uint8_t)0x03)  /* TIM10 Alternate Function mapping */
+#define GPIO_AF3_TIM11         ((uint8_t)0x03)  /* TIM11 Alternate Function mapping */
+#define GPIO_AF3_DFSDM2        ((uint8_t)0x03)  /* DFSDM2 Alternate Function mapping */   
+
+/** 
+  * @brief   AF 4 selection  
+  */ 
+#define GPIO_AF4_I2C1          ((uint8_t)0x04)  /* I2C1 Alternate Function mapping    */
+#define GPIO_AF4_I2C2          ((uint8_t)0x04)  /* I2C2 Alternate Function mapping    */
+#define GPIO_AF4_I2C3          ((uint8_t)0x04)  /* I2C3 Alternate Function mapping    */
+#define GPIO_AF4_FMPI2C1       ((uint8_t)0x04)  /* FMPI2C1 Alternate Function mapping */
+
+/** 
+  * @brief   AF 5 selection  
+  */ 
+#define GPIO_AF5_SPI1          ((uint8_t)0x05)  /* SPI1/I2S1 Alternate Function mapping   */
+#define GPIO_AF5_SPI2          ((uint8_t)0x05)  /* SPI2/I2S2 Alternate Function mapping   */
+#define GPIO_AF5_SPI3          ((uint8_t)0x05)  /* SPI3/I2S3 Alternate Function mapping   */
+#define GPIO_AF5_SPI4          ((uint8_t)0x05)  /* SPI4/I2S4 Alternate Function mapping   */
+#define GPIO_AF5_I2S3ext       ((uint8_t)0x05)  /* I2S3ext_SD Alternate Function mapping  */
+
+/** 
+  * @brief   AF 6 selection  
+  */
+#define GPIO_AF6_SPI2          ((uint8_t)0x06)  /* I2S2 Alternate Function mapping       */
+#define GPIO_AF6_SPI3          ((uint8_t)0x06)  /* SPI3/I2S3 Alternate Function mapping  */
+#define GPIO_AF6_SPI4          ((uint8_t)0x06)  /* SPI4/I2S4 Alternate Function mapping  */
+#define GPIO_AF6_SPI5          ((uint8_t)0x06)  /* SPI5/I2S5 Alternate Function mapping  */
+#define GPIO_AF6_I2S2ext       ((uint8_t)0x06)  /* I2S2ext_SD Alternate Function mapping */
+#define GPIO_AF6_DFSDM1        ((uint8_t)0x06)  /* DFSDM1 Alternate Function mapping     */
+#define GPIO_AF6_DFSDM2        ((uint8_t)0x06)  /* DFSDM2 Alternate Function mapping     */   
+/** 
+  * @brief   AF 7 selection  
+  */ 
+#define GPIO_AF7_SPI3          ((uint8_t)0x07)  /* SPI3/I2S3 Alternate Function mapping  */
+#define GPIO_AF7_SAI1          ((uint8_t)0x07)  /* SAI1 Alternate Function mapping       */
+#define GPIO_AF7_USART1        ((uint8_t)0x07)  /* USART1 Alternate Function mapping     */
+#define GPIO_AF7_USART2        ((uint8_t)0x07)  /* USART2 Alternate Function mapping     */
+#define GPIO_AF7_USART3        ((uint8_t)0x07)  /* USART3 Alternate Function mapping     */
+#define GPIO_AF7_I2S3ext       ((uint8_t)0x07)  /* I2S3ext_SD Alternate Function mapping */
+#define GPIO_AF7_DFSDM2        ((uint8_t)0x07)  /* DFSDM2 Alternate Function mapping     */
+
+/** 
+  * @brief   AF 8 selection  
+  */ 
+#define GPIO_AF8_USART6        ((uint8_t)0x08)  /* USART6 Alternate Function mapping */
+#define GPIO_AF8_USART3        ((uint8_t)0x08)  /* USART3 Alternate Function mapping */
+#define GPIO_AF8_UART4         ((uint8_t)0x08)  /* UART4 Alternate Function mapping  */
+#define GPIO_AF8_UART5         ((uint8_t)0x08)  /* UART5 Alternate Function mapping  */
+#define GPIO_AF8_UART7         ((uint8_t)0x08)  /* UART8 Alternate Function mapping  */
+#define GPIO_AF8_UART8         ((uint8_t)0x08)  /* UART8 Alternate Function mapping  */
+#define GPIO_AF8_DFSDM1        ((uint8_t)0x08)  /* DFSDM1 Alternate Function mapping */
+#define GPIO_AF8_CAN1          ((uint8_t)0x08)  /* CAN1 Alternate Function mapping   */
+
+/** 
+  * @brief   AF 9 selection 
+  */
+#define GPIO_AF9_TIM12         ((uint8_t)0x09)  /* TIM12 Alternate Function mapping   */
+#define GPIO_AF9_TIM13         ((uint8_t)0x09)  /* TIM13 Alternate Function mapping   */
+#define GPIO_AF9_TIM14         ((uint8_t)0x09)  /* TIM14 Alternate Function mapping   */
+#define GPIO_AF9_I2C2          ((uint8_t)0x09)  /* I2C2 Alternate Function mapping    */
+#define GPIO_AF9_I2C3          ((uint8_t)0x09)  /* I2C3 Alternate Function mapping    */
+#define GPIO_AF9_FMPI2C1       ((uint8_t)0x09)  /* FMPI2C1 Alternate Function mapping */
+#define GPIO_AF9_CAN1          ((uint8_t)0x09)  /* CAN1 Alternate Function mapping    */
+#define GPIO_AF9_CAN2          ((uint8_t)0x09)  /* CAN1 Alternate Function mapping    */
+#define GPIO_AF9_QSPI          ((uint8_t)0x09)  /* QSPI Alternate Function mapping    */
+
+/** 
+  * @brief   AF 10 selection  
+  */
+#define GPIO_AF10_SAI1          ((uint8_t)0x0A)  /* SAI1 Alternate Function mapping   */
+#define GPIO_AF10_OTG_FS        ((uint8_t)0x0A)  /* OTG_FS Alternate Function mapping */
+#define GPIO_AF10_DFSDM1        ((uint8_t)0x0A)  /* DFSDM1 Alternate Function mapping */
+#define GPIO_AF10_DFSDM2        ((uint8_t)0x0A)  /* DFSDM2 Alternate Function mapping */
+#define GPIO_AF10_QSPI          ((uint8_t)0x0A)  /* QSPI Alternate Function mapping   */
+#define GPIO_AF10_FSMC          ((uint8_t)0x0A)  /* FSMC Alternate Function mapping   */
+
+/** 
+  * @brief   AF 11 selection  
+  */
+#define GPIO_AF11_UART4         ((uint8_t)0x0B)  /* UART4 Alternate Function mapping  */
+#define GPIO_AF11_UART5         ((uint8_t)0x0B)  /* UART5 Alternate Function mapping  */
+#define GPIO_AF11_UART9         ((uint8_t)0x0B)  /* UART9 Alternate Function mapping  */
+#define GPIO_AF11_UART10        ((uint8_t)0x0B)  /* UART10 Alternate Function mapping */
+#define GPIO_AF11_CAN3          ((uint8_t)0x0B)  /* CAN3 Alternate Function mapping   */
+   
+/** 
+  * @brief   AF 12 selection  
+  */ 
+#define GPIO_AF12_SDIO          ((uint8_t)0x0C)  /* SDIO Alternate Function mapping  */
+#define GPIO_AF12_FSMC          ((uint8_t)0x0C)  /* FMC Alternate Function mapping   */
+
+/** 
+  * @brief   AF 14 selection  
+  */ 
+#define GPIO_AF14_RNG           ((uint8_t)0x0E)  /* RNG Alternate Function mapping  */
+   
+/** 
+  * @brief   AF 15 selection  
+  */ 
+#define GPIO_AF15_EVENTOUT      ((uint8_t)0x0F)  /* EVENTOUT Alternate Function mapping */
+#endif /* STM32F413xx || STM32F423xx */
+
+/*---------------------------------------- STM32F411xx------------------------*/
+#if defined(STM32F411xE) 
+/** 
+  * @brief   AF 0 selection  
+  */ 
+#define GPIO_AF0_RTC_50Hz      ((uint8_t)0x00)  /* RTC_50Hz Alternate Function mapping                       */
+#define GPIO_AF0_MCO           ((uint8_t)0x00)  /* MCO (MCO1 and MCO2) Alternate Function mapping            */
+#define GPIO_AF0_TAMPER        ((uint8_t)0x00)  /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */
+#define GPIO_AF0_SWJ           ((uint8_t)0x00)  /* SWJ (SWD and JTAG) Alternate Function mapping             */
+#define GPIO_AF0_TRACE         ((uint8_t)0x00)  /* TRACE Alternate Function mapping                          */
+
+/** 
+  * @brief   AF 1 selection  
+  */ 
+#define GPIO_AF1_TIM1          ((uint8_t)0x01)  /* TIM1 Alternate Function mapping */
+#define GPIO_AF1_TIM2          ((uint8_t)0x01)  /* TIM2 Alternate Function mapping */
+
+/** 
+  * @brief   AF 2 selection  
+  */ 
+#define GPIO_AF2_TIM3          ((uint8_t)0x02)  /* TIM3 Alternate Function mapping */
+#define GPIO_AF2_TIM4          ((uint8_t)0x02)  /* TIM4 Alternate Function mapping */
+#define GPIO_AF2_TIM5          ((uint8_t)0x02)  /* TIM5 Alternate Function mapping */
+
+/** 
+  * @brief   AF 3 selection  
+  */ 
+#define GPIO_AF3_TIM9          ((uint8_t)0x03)  /* TIM9 Alternate Function mapping  */
+#define GPIO_AF3_TIM10         ((uint8_t)0x03)  /* TIM10 Alternate Function mapping */
+#define GPIO_AF3_TIM11         ((uint8_t)0x03)  /* TIM11 Alternate Function mapping */
+
+/** 
+  * @brief   AF 4 selection  
+  */ 
+#define GPIO_AF4_I2C1          ((uint8_t)0x04)  /* I2C1 Alternate Function mapping */
+#define GPIO_AF4_I2C2          ((uint8_t)0x04)  /* I2C2 Alternate Function mapping */
+#define GPIO_AF4_I2C3          ((uint8_t)0x04)  /* I2C3 Alternate Function mapping */
+
+/** 
+  * @brief   AF 5 selection  
+  */ 
+#define GPIO_AF5_SPI1          ((uint8_t)0x05)  /* SPI1/I2S1 Alternate Function mapping   */
+#define GPIO_AF5_SPI2          ((uint8_t)0x05)  /* SPI2/I2S2 Alternate Function mapping   */
+#define GPIO_AF5_SPI3          ((uint8_t)0x05)  /* SPI3/I2S3 Alternate Function mapping   */
+#define GPIO_AF5_SPI4          ((uint8_t)0x05)  /* SPI4 Alternate Function mapping        */
+#define GPIO_AF5_I2S3ext       ((uint8_t)0x05)  /* I2S3ext_SD Alternate Function mapping  */
+
+/** 
+  * @brief   AF 6 selection  
+  */
+#define GPIO_AF6_SPI2          ((uint8_t)0x06)  /* I2S2 Alternate Function mapping       */
+#define GPIO_AF6_SPI3          ((uint8_t)0x06)  /* SPI3/I2S3 Alternate Function mapping  */
+#define GPIO_AF6_SPI4          ((uint8_t)0x06)  /* SPI4/I2S4 Alternate Function mapping  */
+#define GPIO_AF6_SPI5          ((uint8_t)0x06)  /* SPI5/I2S5 Alternate Function mapping  */
+#define GPIO_AF6_I2S2ext       ((uint8_t)0x06)  /* I2S2ext_SD Alternate Function mapping */
+
+/** 
+  * @brief   AF 7 selection  
+  */ 
+#define GPIO_AF7_SPI3          ((uint8_t)0x07)  /* SPI3/I2S3 Alternate Function mapping  */
+#define GPIO_AF7_USART1        ((uint8_t)0x07)  /* USART1 Alternate Function mapping     */
+#define GPIO_AF7_USART2        ((uint8_t)0x07)  /* USART2 Alternate Function mapping     */
+#define GPIO_AF7_I2S3ext       ((uint8_t)0x07)  /* I2S3ext_SD Alternate Function mapping */
+
+/** 
+  * @brief   AF 8 selection  
+  */ 
+#define GPIO_AF8_USART6        ((uint8_t)0x08)  /* USART6 Alternate Function mapping */
+
+/** 
+  * @brief   AF 9 selection 
+  */ 
+#define GPIO_AF9_TIM14         ((uint8_t)0x09)  /* TIM14 Alternate Function mapping */
+#define GPIO_AF9_I2C2          ((uint8_t)0x09)  /* I2C2 Alternate Function mapping  */
+#define GPIO_AF9_I2C3          ((uint8_t)0x09)  /* I2C3 Alternate Function mapping  */
+
+/** 
+  * @brief   AF 10 selection  
+  */ 
+#define GPIO_AF10_OTG_FS        ((uint8_t)0x0A)  /* OTG_FS Alternate Function mapping */
+
+/** 
+  * @brief   AF 12 selection  
+  */ 
+#define GPIO_AF12_SDIO          ((uint8_t)0x0C)  /* SDIO Alternate Function mapping  */
+
+/** 
+  * @brief   AF 15 selection  
+  */ 
+#define GPIO_AF15_EVENTOUT      ((uint8_t)0x0F)  /* EVENTOUT Alternate Function mapping */
+#endif /* STM32F411xE */
+
+/*---------------------------------------- STM32F410xx------------------------*/
+#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
+/** 
+  * @brief   AF 0 selection  
+  */ 
+#define GPIO_AF0_RTC_50Hz      ((uint8_t)0x00)  /* RTC_50Hz Alternate Function mapping                       */
+#define GPIO_AF0_MCO           ((uint8_t)0x00)  /* MCO (MCO1 and MCO2) Alternate Function mapping            */
+#define GPIO_AF0_TAMPER        ((uint8_t)0x00)  /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */
+#define GPIO_AF0_SWJ           ((uint8_t)0x00)  /* SWJ (SWD and JTAG) Alternate Function mapping             */
+#define GPIO_AF0_TRACE         ((uint8_t)0x00)  /* TRACE Alternate Function mapping                          */
+
+/** 
+  * @brief   AF 1 selection  
+  */ 
+#define GPIO_AF1_TIM1          ((uint8_t)0x01)  /* TIM1 Alternate Function mapping */
+#define GPIO_AF1_LPTIM1        ((uint8_t)0x01)  /* LPTIM1 Alternate Function mapping */
+
+/** 
+  * @brief   AF 2 selection  
+  */ 
+#define GPIO_AF2_TIM5          ((uint8_t)0x02)  /* TIM5 Alternate Function mapping */
+
+/** 
+  * @brief   AF 3 selection  
+  */ 
+#define GPIO_AF3_TIM9          ((uint8_t)0x03)  /* TIM9 Alternate Function mapping  */
+#define GPIO_AF3_TIM11         ((uint8_t)0x03)  /* TIM11 Alternate Function mapping */
+
+/** 
+  * @brief   AF 4 selection  
+  */ 
+#define GPIO_AF4_I2C1          ((uint8_t)0x04)  /* I2C1 Alternate Function mapping */
+#define GPIO_AF4_I2C2          ((uint8_t)0x04)  /* I2C2 Alternate Function mapping */
+#define GPIO_AF4_FMPI2C1       ((uint8_t)0x04)  /* FMPI2C1 Alternate Function mapping */
+
+/** 
+  * @brief   AF 5 selection  
+  */ 
+#define GPIO_AF5_SPI1          ((uint8_t)0x05)  /* SPI1/I2S1 Alternate Function mapping   */
+#if defined(STM32F410Cx) || defined(STM32F410Rx)  
+#define GPIO_AF5_SPI2          ((uint8_t)0x05)  /* SPI2/I2S2 Alternate Function mapping   */
+#endif /* STM32F410Cx || STM32F410Rx */   
+
+/** 
+  * @brief   AF 6 selection  
+  */
+#define GPIO_AF6_SPI1          ((uint8_t)0x06)  /* SPI1 Alternate Function mapping  */
+#if defined(STM32F410Cx) || defined(STM32F410Rx)   
+#define GPIO_AF6_SPI2          ((uint8_t)0x06)  /* I2S2 Alternate Function mapping       */
+#endif /* STM32F410Cx || STM32F410Rx */   
+#define GPIO_AF6_SPI5          ((uint8_t)0x06)  /* SPI5/I2S5 Alternate Function mapping  */
+/** 
+  * @brief   AF 7 selection  
+  */ 
+#define GPIO_AF7_USART1        ((uint8_t)0x07)  /* USART1 Alternate Function mapping     */
+#define GPIO_AF7_USART2        ((uint8_t)0x07)  /* USART2 Alternate Function mapping     */
+
+/** 
+  * @brief   AF 8 selection  
+  */ 
+#define GPIO_AF8_USART6        ((uint8_t)0x08)  /* USART6 Alternate Function mapping */
+
+/** 
+  * @brief   AF 9 selection 
+  */ 
+#define GPIO_AF9_I2C2          ((uint8_t)0x09)  /* I2C2 Alternate Function mapping  */
+#define GPIO_AF9_FMPI2C1       ((uint8_t)0x09)  /* FMPI2C1 Alternate Function mapping */
+
+/** 
+  * @brief   AF 15 selection  
+  */ 
+#define GPIO_AF15_EVENTOUT      ((uint8_t)0x0F)  /* EVENTOUT Alternate Function mapping */
+#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
+
+/*---------------------------------------- STM32F446xx -----------------------*/
+#if defined(STM32F446xx)
+/**
+  * @brief   AF 0 selection  
+  */ 
+#define GPIO_AF0_RTC_50Hz      ((uint8_t)0x00)  /* RTC_50Hz Alternate Function mapping                       */
+#define GPIO_AF0_MCO           ((uint8_t)0x00)  /* MCO (MCO1 and MCO2) Alternate Function mapping            */
+#define GPIO_AF0_TAMPER        ((uint8_t)0x00)  /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */
+#define GPIO_AF0_SWJ           ((uint8_t)0x00)  /* SWJ (SWD and JTAG) Alternate Function mapping             */
+#define GPIO_AF0_TRACE         ((uint8_t)0x00)  /* TRACE Alternate Function mapping                          */
+
+/** 
+  * @brief   AF 1 selection  
+  */ 
+#define GPIO_AF1_TIM1          ((uint8_t)0x01)  /* TIM1 Alternate Function mapping */
+#define GPIO_AF1_TIM2          ((uint8_t)0x01)  /* TIM2 Alternate Function mapping */
+
+/** 
+  * @brief   AF 2 selection  
+  */ 
+#define GPIO_AF2_TIM3          ((uint8_t)0x02)  /* TIM3 Alternate Function mapping */
+#define GPIO_AF2_TIM4          ((uint8_t)0x02)  /* TIM4 Alternate Function mapping */
+#define GPIO_AF2_TIM5          ((uint8_t)0x02)  /* TIM5 Alternate Function mapping */
+
+/** 
+  * @brief   AF 3 selection  
+  */ 
+#define GPIO_AF3_TIM8          ((uint8_t)0x03)  /* TIM8 Alternate Function mapping  */
+#define GPIO_AF3_TIM9          ((uint8_t)0x03)  /* TIM9 Alternate Function mapping  */
+#define GPIO_AF3_TIM10         ((uint8_t)0x03)  /* TIM10 Alternate Function mapping */
+#define GPIO_AF3_TIM11         ((uint8_t)0x03)  /* TIM11 Alternate Function mapping */
+#define GPIO_AF3_CEC           ((uint8_t)0x03)  /* CEC Alternate Function mapping   */
+
+/** 
+  * @brief   AF 4 selection  
+  */ 
+#define GPIO_AF4_I2C1          ((uint8_t)0x04)  /* I2C1 Alternate Function mapping */
+#define GPIO_AF4_I2C2          ((uint8_t)0x04)  /* I2C2 Alternate Function mapping */
+#define GPIO_AF4_I2C3          ((uint8_t)0x04)  /* I2C3 Alternate Function mapping */
+#define GPIO_AF4_FMPI2C1       ((uint8_t)0x04)  /* FMPI2C1 Alternate Function mapping */
+#define GPIO_AF4_CEC           ((uint8_t)0x04)  /* CEC Alternate Function mapping  */
+
+/** 
+  * @brief   AF 5 selection  
+  */ 
+#define GPIO_AF5_SPI1          ((uint8_t)0x05)  /* SPI1/I2S1 Alternate Function mapping   */
+#define GPIO_AF5_SPI2          ((uint8_t)0x05)  /* SPI2/I2S2 Alternate Function mapping   */
+#define GPIO_AF5_SPI3          ((uint8_t)0x05)  /* SPI3/I2S3 Alternate Function mapping   */
+#define GPIO_AF5_SPI4          ((uint8_t)0x05)  /* SPI4 Alternate Function mapping        */
+
+/** 
+  * @brief   AF 6 selection  
+  */ 
+#define GPIO_AF6_SPI2          ((uint8_t)0x06)  /* SPI2/I2S2 Alternate Function mapping  */
+#define GPIO_AF6_SPI3          ((uint8_t)0x06)  /* SPI3/I2S3 Alternate Function mapping  */
+#define GPIO_AF6_SPI4          ((uint8_t)0x06)  /* SPI4 Alternate Function mapping       */
+#define GPIO_AF6_SAI1          ((uint8_t)0x06)  /* SAI1 Alternate Function mapping       */
+
+/** 
+  * @brief   AF 7 selection  
+  */ 
+#define GPIO_AF7_USART1        ((uint8_t)0x07)  /* USART1 Alternate Function mapping     */
+#define GPIO_AF7_USART2        ((uint8_t)0x07)  /* USART2 Alternate Function mapping     */
+#define GPIO_AF7_USART3        ((uint8_t)0x07)  /* USART3 Alternate Function mapping     */
+#define GPIO_AF7_UART5         ((uint8_t)0x07)  /* UART5 Alternate Function mapping      */
+#define GPIO_AF7_SPI2          ((uint8_t)0x07)  /* SPI2/I2S2 Alternate Function mapping  */
+#define GPIO_AF7_SPI3          ((uint8_t)0x07)  /* SPI3/I2S3 Alternate Function mapping  */
+#define GPIO_AF7_SPDIFRX       ((uint8_t)0x07)  /* SPDIFRX Alternate Function mapping      */
+
+/** 
+  * @brief   AF 8 selection  
+  */ 
+#define GPIO_AF8_UART4         ((uint8_t)0x08)  /* UART4 Alternate Function mapping  */
+#define GPIO_AF8_UART5         ((uint8_t)0x08)  /* UART5 Alternate Function mapping  */
+#define GPIO_AF8_USART6        ((uint8_t)0x08)  /* USART6 Alternate Function mapping */
+#define GPIO_AF8_SPDIFRX       ((uint8_t)0x08)  /* SPDIFRX Alternate Function mapping  */
+#define GPIO_AF8_SAI2          ((uint8_t)0x08)  /* SAI2 Alternate Function mapping   */
+
+/** 
+  * @brief   AF 9 selection 
+  */ 
+#define GPIO_AF9_CAN1          ((uint8_t)0x09)  /* CAN1 Alternate Function mapping  */
+#define GPIO_AF9_CAN2          ((uint8_t)0x09)  /* CAN2 Alternate Function mapping  */
+#define GPIO_AF9_TIM12         ((uint8_t)0x09)  /* TIM12 Alternate Function mapping */
+#define GPIO_AF9_TIM13         ((uint8_t)0x09)  /* TIM13 Alternate Function mapping */
+#define GPIO_AF9_TIM14         ((uint8_t)0x09)  /* TIM14 Alternate Function mapping */
+#define GPIO_AF9_QSPI          ((uint8_t)0x09)  /* QSPI Alternate Function mapping  */
+
+/** 
+  * @brief   AF 10 selection  
+  */ 
+#define GPIO_AF10_OTG_FS        ((uint8_t)0x0A)  /* OTG_FS Alternate Function mapping */
+#define GPIO_AF10_OTG_HS        ((uint8_t)0x0A)  /* OTG_HS Alternate Function mapping */
+#define GPIO_AF10_SAI2          ((uint8_t)0x0A)  /* SAI2 Alternate Function mapping   */
+#define GPIO_AF10_QSPI          ((uint8_t)0x0A)  /* QSPI Alternate Function mapping  */
+
+/** 
+  * @brief   AF 11 selection  
+  */ 
+#define GPIO_AF11_ETH           ((uint8_t)0x0B)  /* ETHERNET Alternate Function mapping */
+
+/** 
+  * @brief   AF 12 selection  
+  */ 
+#define GPIO_AF12_FMC           ((uint8_t)0x0C)  /* FMC Alternate Function mapping                      */
+#define GPIO_AF12_OTG_HS_FS     ((uint8_t)0x0C)  /* OTG HS configured in FS, Alternate Function mapping */
+#define GPIO_AF12_SDIO          ((uint8_t)0x0C)  /* SDIO Alternate Function mapping                     */
+
+/** 
+  * @brief   AF 13 selection  
+  */ 
+#define GPIO_AF13_DCMI          ((uint8_t)0x0D)  /* DCMI Alternate Function mapping */
+
+/** 
+  * @brief   AF 15 selection  
+  */ 
+#define GPIO_AF15_EVENTOUT      ((uint8_t)0x0F)  /* EVENTOUT Alternate Function mapping */
+
+#endif /* STM32F446xx */
+/*----------------------------------------------------------------------------*/
+
+/*-------------------------------- STM32F469xx/STM32F479xx--------------------*/
+#if defined(STM32F469xx) || defined(STM32F479xx)
+/** 
+  * @brief   AF 0 selection  
+  */ 
+#define GPIO_AF0_RTC_50Hz      ((uint8_t)0x00)  /* RTC_50Hz Alternate Function mapping                       */
+#define GPIO_AF0_MCO           ((uint8_t)0x00)  /* MCO (MCO1 and MCO2) Alternate Function mapping            */
+#define GPIO_AF0_TAMPER        ((uint8_t)0x00)  /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */
+#define GPIO_AF0_SWJ           ((uint8_t)0x00)  /* SWJ (SWD and JTAG) Alternate Function mapping             */
+#define GPIO_AF0_TRACE         ((uint8_t)0x00)  /* TRACE Alternate Function mapping                          */
+
+/** 
+  * @brief   AF 1 selection  
+  */ 
+#define GPIO_AF1_TIM1          ((uint8_t)0x01)  /* TIM1 Alternate Function mapping */
+#define GPIO_AF1_TIM2          ((uint8_t)0x01)  /* TIM2 Alternate Function mapping */
+
+/** 
+  * @brief   AF 2 selection  
+  */ 
+#define GPIO_AF2_TIM3          ((uint8_t)0x02)  /* TIM3 Alternate Function mapping */
+#define GPIO_AF2_TIM4          ((uint8_t)0x02)  /* TIM4 Alternate Function mapping */
+#define GPIO_AF2_TIM5          ((uint8_t)0x02)  /* TIM5 Alternate Function mapping */
+
+/** 
+  * @brief   AF 3 selection  
+  */ 
+#define GPIO_AF3_TIM8          ((uint8_t)0x03)  /* TIM8 Alternate Function mapping  */
+#define GPIO_AF3_TIM9          ((uint8_t)0x03)  /* TIM9 Alternate Function mapping  */
+#define GPIO_AF3_TIM10         ((uint8_t)0x03)  /* TIM10 Alternate Function mapping */
+#define GPIO_AF3_TIM11         ((uint8_t)0x03)  /* TIM11 Alternate Function mapping */
+
+/** 
+  * @brief   AF 4 selection  
+  */ 
+#define GPIO_AF4_I2C1          ((uint8_t)0x04)  /* I2C1 Alternate Function mapping */
+#define GPIO_AF4_I2C2          ((uint8_t)0x04)  /* I2C2 Alternate Function mapping */
+#define GPIO_AF4_I2C3          ((uint8_t)0x04)  /* I2C3 Alternate Function mapping */
+
+/** 
+  * @brief   AF 5 selection  
+  */ 
+#define GPIO_AF5_SPI1          ((uint8_t)0x05)  /* SPI1 Alternate Function mapping        */
+#define GPIO_AF5_SPI2          ((uint8_t)0x05)  /* SPI2/I2S2 Alternate Function mapping   */
+#define GPIO_AF5_SPI3          ((uint8_t)0x05)  /* SPI3/I2S3 Alternate Function mapping   */
+#define GPIO_AF5_SPI4          ((uint8_t)0x05)  /* SPI4 Alternate Function mapping        */
+#define GPIO_AF5_SPI5          ((uint8_t)0x05)  /* SPI5 Alternate Function mapping        */
+#define GPIO_AF5_SPI6          ((uint8_t)0x05)  /* SPI6 Alternate Function mapping        */
+#define GPIO_AF5_I2S3ext       ((uint8_t)0x05)  /* I2S3ext_SD Alternate Function mapping  */
+
+/** 
+  * @brief   AF 6 selection  
+  */ 
+#define GPIO_AF6_SPI3          ((uint8_t)0x06)  /* SPI3/I2S3 Alternate Function mapping  */
+#define GPIO_AF6_I2S2ext       ((uint8_t)0x06)  /* I2S2ext_SD Alternate Function mapping */
+#define GPIO_AF6_SAI1          ((uint8_t)0x06)  /* SAI1 Alternate Function mapping       */
+
+/** 
+  * @brief   AF 7 selection  
+  */ 
+#define GPIO_AF7_USART1        ((uint8_t)0x07)  /* USART1 Alternate Function mapping     */
+#define GPIO_AF7_USART2        ((uint8_t)0x07)  /* USART2 Alternate Function mapping     */
+#define GPIO_AF7_USART3        ((uint8_t)0x07)  /* USART3 Alternate Function mapping     */
+#define GPIO_AF7_I2S3ext       ((uint8_t)0x07)  /* I2S3ext_SD Alternate Function mapping */
+
+/** 
+  * @brief   AF 8 selection  
+  */ 
+#define GPIO_AF8_UART4         ((uint8_t)0x08)  /* UART4 Alternate Function mapping  */
+#define GPIO_AF8_UART5         ((uint8_t)0x08)  /* UART5 Alternate Function mapping  */
+#define GPIO_AF8_USART6        ((uint8_t)0x08)  /* USART6 Alternate Function mapping */
+#define GPIO_AF8_UART7         ((uint8_t)0x08)  /* UART7 Alternate Function mapping  */
+#define GPIO_AF8_UART8         ((uint8_t)0x08)  /* UART8 Alternate Function mapping  */
+
+/** 
+  * @brief   AF 9 selection 
+  */ 
+#define GPIO_AF9_CAN1          ((uint8_t)0x09)  /* CAN1 Alternate Function mapping    */
+#define GPIO_AF9_CAN2          ((uint8_t)0x09)  /* CAN2 Alternate Function mapping    */
+#define GPIO_AF9_TIM12         ((uint8_t)0x09)  /* TIM12 Alternate Function mapping   */
+#define GPIO_AF9_TIM13         ((uint8_t)0x09)  /* TIM13 Alternate Function mapping   */
+#define GPIO_AF9_TIM14         ((uint8_t)0x09)  /* TIM14 Alternate Function mapping   */
+#define GPIO_AF9_LTDC          ((uint8_t)0x09)  /* LCD-TFT Alternate Function mapping */
+#define GPIO_AF9_QSPI          ((uint8_t)0x09)  /* QSPI Alternate Function mapping    */
+
+/** 
+  * @brief   AF 10 selection  
+  */ 
+#define GPIO_AF10_OTG_FS        ((uint8_t)0x0A)  /* OTG_FS Alternate Function mapping */
+#define GPIO_AF10_OTG_HS        ((uint8_t)0x0A)  /* OTG_HS Alternate Function mapping */
+#define GPIO_AF10_QSPI          ((uint8_t)0x0A)  /* QSPI Alternate Function mapping   */
+
+/** 
+  * @brief   AF 11 selection  
+  */ 
+#define GPIO_AF11_ETH           ((uint8_t)0x0B)  /* ETHERNET Alternate Function mapping */
+
+/** 
+  * @brief   AF 12 selection  
+  */ 
+#define GPIO_AF12_FMC           ((uint8_t)0x0C)  /* FMC Alternate Function mapping                      */
+#define GPIO_AF12_OTG_HS_FS     ((uint8_t)0x0C)  /* OTG HS configured in FS, Alternate Function mapping */
+#define GPIO_AF12_SDIO          ((uint8_t)0x0C)  /* SDIO Alternate Function mapping                     */
+
+/** 
+  * @brief   AF 13 selection  
+  */ 
+#define GPIO_AF13_DCMI          ((uint8_t)0x0D)  /* DCMI Alternate Function mapping */
+#define GPIO_AF13_DSI           ((uint8_t)0x0D)  /* DSI Alternate Function mapping  */
+
+/** 
+  * @brief   AF 14 selection  
+  */
+#define GPIO_AF14_LTDC          ((uint8_t)0x0E)  /* LCD-TFT Alternate Function mapping */
+
+/** 
+  * @brief   AF 15 selection  
+  */ 
+#define GPIO_AF15_EVENTOUT      ((uint8_t)0x0F)  /* EVENTOUT Alternate Function mapping */
+
+#endif /* STM32F469xx || STM32F479xx */
+/*----------------------------------------------------------------------------*/
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup GPIOEx_Exported_Macros GPIO Exported Macros
+  * @{
+  */
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup GPIOEx_Exported_Functions GPIO Exported Functions
+  * @{
+  */
+/**
+  * @}
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup GPIOEx_Private_Constants GPIO Private Constants
+  * @{
+  */
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup GPIOEx_Private_Macros GPIO Private Macros
+  * @{
+  */
+/** @defgroup GPIOEx_Get_Port_Index GPIO Get Port Index
+  * @{
+  */
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
+#define GPIO_GET_INDEX(__GPIOx__)    (uint8_t)(((__GPIOx__) == (GPIOA))? 0U :\
+                                               ((__GPIOx__) == (GPIOB))? 1U :\
+                                               ((__GPIOx__) == (GPIOC))? 2U :\
+                                               ((__GPIOx__) == (GPIOD))? 3U :\
+                                               ((__GPIOx__) == (GPIOE))? 4U :\
+                                               ((__GPIOx__) == (GPIOF))? 5U :\
+                                               ((__GPIOx__) == (GPIOG))? 6U :\
+                                               ((__GPIOx__) == (GPIOH))? 7U : 8U)
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
+    defined(STM32F469xx) || defined(STM32F479xx)
+#define GPIO_GET_INDEX(__GPIOx__)    (uint8_t)(((__GPIOx__) == (GPIOA))? 0U :\
+                                               ((__GPIOx__) == (GPIOB))? 1U :\
+                                               ((__GPIOx__) == (GPIOC))? 2U :\
+                                               ((__GPIOx__) == (GPIOD))? 3U :\
+                                               ((__GPIOx__) == (GPIOE))? 4U :\
+                                               ((__GPIOx__) == (GPIOF))? 5U :\
+                                               ((__GPIOx__) == (GPIOG))? 6U :\
+                                               ((__GPIOx__) == (GPIOH))? 7U :\
+                                               ((__GPIOx__) == (GPIOI))? 8U :\
+                                               ((__GPIOx__) == (GPIOJ))? 9U : 10U)
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
+
+#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) 
+#define GPIO_GET_INDEX(__GPIOx__)    (uint8_t)(((__GPIOx__) == (GPIOA))? 0U :\
+                                               ((__GPIOx__) == (GPIOB))? 1U :\
+                                               ((__GPIOx__) == (GPIOC))? 2U : 7U)
+#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
+
+#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) 
+#define GPIO_GET_INDEX(__GPIOx__)    (uint8_t)(((__GPIOx__) == (GPIOA))? 0U :\
+                                               ((__GPIOx__) == (GPIOB))? 1U :\
+                                               ((__GPIOx__) == (GPIOC))? 2U :\
+                                               ((__GPIOx__) == (GPIOD))? 3U :\
+                                               ((__GPIOx__) == (GPIOE))? 4U : 7U)
+#endif /* STM32F401xC || STM32F401xE || STM32F411xE */
+
+#if defined(STM32F446xx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx) 
+#define GPIO_GET_INDEX(__GPIOx__)    (uint8_t)(((__GPIOx__) == (GPIOA))? 0U :\
+                                               ((__GPIOx__) == (GPIOB))? 1U :\
+                                               ((__GPIOx__) == (GPIOC))? 2U :\
+                                               ((__GPIOx__) == (GPIOD))? 3U :\
+                                               ((__GPIOx__) == (GPIOE))? 4U :\
+                                               ((__GPIOx__) == (GPIOF))? 5U :\
+                                               ((__GPIOx__) == (GPIOG))? 6U : 7U)
+#endif /* STM32F446xx || STM32F412Zx  || STM32F413xx || STM32F423xx */
+#if defined(STM32F412Vx)
+#define GPIO_GET_INDEX(__GPIOx__)    (uint8_t)(((__GPIOx__) == (GPIOA))? 0U :\
+                                               ((__GPIOx__) == (GPIOB))? 1U :\
+                                               ((__GPIOx__) == (GPIOC))? 2U :\
+                                               ((__GPIOx__) == (GPIOD))? 3U :\
+                                               ((__GPIOx__) == (GPIOE))? 4U : 7U)
+#endif /* STM32F412Vx */
+#if defined(STM32F412Rx)
+#define GPIO_GET_INDEX(__GPIOx__)    (uint8_t)(((__GPIOx__) == (GPIOA))? 0U :\
+                                               ((__GPIOx__) == (GPIOB))? 1U :\
+                                               ((__GPIOx__) == (GPIOC))? 2U :\
+                                               ((__GPIOx__) == (GPIOD))? 3U : 7U)
+#endif /* STM32F412Rx */
+#if defined(STM32F412Cx)
+#define GPIO_GET_INDEX(__GPIOx__)    (uint8_t)(((__GPIOx__) == (GPIOA))? 0U :\
+                                               ((__GPIOx__) == (GPIOB))? 1U :\
+                                               ((__GPIOx__) == (GPIOC))? 2U : 7U)
+#endif /* STM32F412Cx */
+
+/**
+  * @}
+  */
+
+/** @defgroup GPIOEx_IS_Alternat_function_selection GPIO Check Alternate Function
+  * @{
+  */  
+/*------------------------- STM32F429xx/STM32F439xx---------------------------*/
+#if defined(STM32F429xx) || defined(STM32F439xx)
+#define IS_GPIO_AF(AF)   (((AF) == GPIO_AF0_RTC_50Hz)   || ((AF) == GPIO_AF9_TIM14)      || \
+                          ((AF) == GPIO_AF0_MCO)        || ((AF) == GPIO_AF0_TAMPER)     || \
+                          ((AF) == GPIO_AF0_SWJ)        || ((AF) == GPIO_AF0_TRACE)      || \
+                          ((AF) == GPIO_AF1_TIM1)       || ((AF) == GPIO_AF1_TIM2)       || \
+                          ((AF) == GPIO_AF2_TIM3)       || ((AF) == GPIO_AF2_TIM4)       || \
+                          ((AF) == GPIO_AF2_TIM5)       || ((AF) == GPIO_AF3_TIM8)       || \
+                          ((AF) == GPIO_AF4_I2C1)       || ((AF) == GPIO_AF4_I2C2)       || \
+                          ((AF) == GPIO_AF4_I2C3)       || ((AF) == GPIO_AF5_SPI1)       || \
+                          ((AF) == GPIO_AF5_SPI2)       || ((AF) == GPIO_AF9_TIM13)      || \
+                          ((AF) == GPIO_AF6_SPI3)       || ((AF) == GPIO_AF9_TIM12)      || \
+                          ((AF) == GPIO_AF7_USART1)     || ((AF) == GPIO_AF7_USART2)     || \
+                          ((AF) == GPIO_AF7_USART3)     || ((AF) == GPIO_AF8_UART4)      || \
+                          ((AF) == GPIO_AF8_UART5)      || ((AF) == GPIO_AF8_USART6)     || \
+                          ((AF) == GPIO_AF9_CAN1)       || ((AF) == GPIO_AF9_CAN2)       || \
+                          ((AF) == GPIO_AF10_OTG_FS)    || ((AF) == GPIO_AF10_OTG_HS)    || \
+                          ((AF) == GPIO_AF11_ETH)       || ((AF) == GPIO_AF12_OTG_HS_FS) || \
+                          ((AF) == GPIO_AF12_SDIO)      || ((AF) == GPIO_AF13_DCMI)      || \
+                          ((AF) == GPIO_AF15_EVENTOUT)  || ((AF) == GPIO_AF5_SPI4)       || \
+                          ((AF) == GPIO_AF5_SPI5)       || ((AF) == GPIO_AF5_SPI6)       || \
+                          ((AF) == GPIO_AF8_UART7)      || ((AF) == GPIO_AF8_UART8)      || \
+                          ((AF) == GPIO_AF12_FMC)       ||  ((AF) == GPIO_AF6_SAI1)      || \
+                          ((AF) == GPIO_AF14_LTDC))
+
+#endif /* STM32F429xx || STM32F439xx */
+/*----------------------------------------------------------------------------*/
+
+/*---------------------------------- STM32F427xx/STM32F437xx------------------*/
+#if defined(STM32F427xx) || defined(STM32F437xx)
+#define IS_GPIO_AF(AF)   (((AF) == GPIO_AF0_RTC_50Hz)   || ((AF) == GPIO_AF9_TIM14)      || \
+                          ((AF) == GPIO_AF0_MCO)        || ((AF) == GPIO_AF0_TAMPER)     || \
+                          ((AF) == GPIO_AF0_SWJ)        || ((AF) == GPIO_AF0_TRACE)      || \
+                          ((AF) == GPIO_AF1_TIM1)       || ((AF) == GPIO_AF1_TIM2)       || \
+                          ((AF) == GPIO_AF2_TIM3)       || ((AF) == GPIO_AF2_TIM4)       || \
+                          ((AF) == GPIO_AF2_TIM5)       || ((AF) == GPIO_AF3_TIM8)       || \
+                          ((AF) == GPIO_AF4_I2C1)       || ((AF) == GPIO_AF4_I2C2)       || \
+                          ((AF) == GPIO_AF4_I2C3)       || ((AF) == GPIO_AF5_SPI1)       || \
+                          ((AF) == GPIO_AF5_SPI2)       || ((AF) == GPIO_AF9_TIM13)      || \
+                          ((AF) == GPIO_AF6_SPI3)       || ((AF) == GPIO_AF9_TIM12)      || \
+                          ((AF) == GPIO_AF7_USART1)     || ((AF) == GPIO_AF7_USART2)     || \
+                          ((AF) == GPIO_AF7_USART3)     || ((AF) == GPIO_AF8_UART4)      || \
+                          ((AF) == GPIO_AF8_UART5)      || ((AF) == GPIO_AF8_USART6)     || \
+                          ((AF) == GPIO_AF9_CAN1)       || ((AF) == GPIO_AF9_CAN2)       || \
+                          ((AF) == GPIO_AF10_OTG_FS)    || ((AF) == GPIO_AF10_OTG_HS)    || \
+                          ((AF) == GPIO_AF11_ETH)       || ((AF) == GPIO_AF12_OTG_HS_FS) || \
+                          ((AF) == GPIO_AF12_SDIO)      || ((AF) == GPIO_AF13_DCMI)      || \
+                          ((AF) == GPIO_AF15_EVENTOUT)  || ((AF) == GPIO_AF5_SPI4)       || \
+                          ((AF) == GPIO_AF5_SPI5)       || ((AF) == GPIO_AF5_SPI6)       || \
+                          ((AF) == GPIO_AF8_UART7)      || ((AF) == GPIO_AF8_UART8)      || \
+                          ((AF) == GPIO_AF12_FMC)       ||  ((AF) == GPIO_AF6_SAI1))
+
+#endif /* STM32F427xx || STM32F437xx */
+/*----------------------------------------------------------------------------*/
+
+/*---------------------------------- STM32F407xx/STM32F417xx------------------*/
+#if defined(STM32F407xx) || defined(STM32F417xx)
+#define IS_GPIO_AF(AF)   (((AF) == GPIO_AF0_RTC_50Hz)   || ((AF) == GPIO_AF9_TIM14)      || \
+                          ((AF) == GPIO_AF0_MCO)        || ((AF) == GPIO_AF0_TAMPER)     || \
+                          ((AF) == GPIO_AF0_SWJ)        || ((AF) == GPIO_AF0_TRACE)      || \
+                          ((AF) == GPIO_AF1_TIM1)       || ((AF) == GPIO_AF1_TIM2)       || \
+                          ((AF) == GPIO_AF2_TIM3)       || ((AF) == GPIO_AF2_TIM4)       || \
+                          ((AF) == GPIO_AF2_TIM5)       || ((AF) == GPIO_AF3_TIM8)       || \
+                          ((AF) == GPIO_AF4_I2C1)       || ((AF) == GPIO_AF4_I2C2)       || \
+                          ((AF) == GPIO_AF4_I2C3)       || ((AF) == GPIO_AF5_SPI1)       || \
+                          ((AF) == GPIO_AF5_SPI2)       || ((AF) == GPIO_AF9_TIM13)      || \
+                          ((AF) == GPIO_AF6_SPI3)       || ((AF) == GPIO_AF9_TIM12)      || \
+                          ((AF) == GPIO_AF7_USART1)     || ((AF) == GPIO_AF7_USART2)     || \
+                          ((AF) == GPIO_AF7_USART3)     || ((AF) == GPIO_AF8_UART4)      || \
+                          ((AF) == GPIO_AF8_UART5)      || ((AF) == GPIO_AF8_USART6)     || \
+                          ((AF) == GPIO_AF9_CAN1)       || ((AF) == GPIO_AF9_CAN2)       || \
+                          ((AF) == GPIO_AF10_OTG_FS)    || ((AF) == GPIO_AF10_OTG_HS)    || \
+                          ((AF) == GPIO_AF11_ETH)       || ((AF) == GPIO_AF12_OTG_HS_FS) || \
+                          ((AF) == GPIO_AF12_SDIO)      || ((AF) == GPIO_AF13_DCMI)      || \
+                          ((AF) == GPIO_AF12_FSMC)      || ((AF) == GPIO_AF15_EVENTOUT))
+
+#endif /* STM32F407xx || STM32F417xx */
+/*----------------------------------------------------------------------------*/
+
+/*---------------------------------- STM32F405xx/STM32F415xx------------------*/
+#if defined(STM32F405xx) || defined(STM32F415xx)
+#define IS_GPIO_AF(AF)   (((AF) == GPIO_AF0_RTC_50Hz)   || ((AF) == GPIO_AF9_TIM14)      || \
+                          ((AF) == GPIO_AF0_MCO)        || ((AF) == GPIO_AF0_TAMPER)     || \
+                          ((AF) == GPIO_AF0_SWJ)        || ((AF) == GPIO_AF0_TRACE)      || \
+                          ((AF) == GPIO_AF1_TIM1)       || ((AF) == GPIO_AF1_TIM2)       || \
+                          ((AF) == GPIO_AF2_TIM3)       || ((AF) == GPIO_AF2_TIM4)       || \
+                          ((AF) == GPIO_AF2_TIM5)       || ((AF) == GPIO_AF3_TIM8)       || \
+                          ((AF) == GPIO_AF4_I2C1)       || ((AF) == GPIO_AF4_I2C2)       || \
+                          ((AF) == GPIO_AF4_I2C3)       || ((AF) == GPIO_AF5_SPI1)       || \
+                          ((AF) == GPIO_AF5_SPI2)       || ((AF) == GPIO_AF9_TIM13)      || \
+                          ((AF) == GPIO_AF6_SPI3)       || ((AF) == GPIO_AF9_TIM12)      || \
+                          ((AF) == GPIO_AF7_USART1)     || ((AF) == GPIO_AF7_USART2)     || \
+                          ((AF) == GPIO_AF7_USART3)     || ((AF) == GPIO_AF8_UART4)      || \
+                          ((AF) == GPIO_AF8_UART5)      || ((AF) == GPIO_AF8_USART6)     || \
+                          ((AF) == GPIO_AF9_CAN1)       || ((AF) == GPIO_AF9_CAN2)       || \
+                          ((AF) == GPIO_AF10_OTG_FS)    || ((AF) == GPIO_AF10_OTG_HS)    || \
+                          ((AF) == GPIO_AF12_OTG_HS_FS) || ((AF) == GPIO_AF12_SDIO)      || \
+                          ((AF) == GPIO_AF12_FSMC)      || ((AF) == GPIO_AF15_EVENTOUT))
+
+#endif /* STM32F405xx || STM32F415xx */
+
+/*----------------------------------------------------------------------------*/
+
+/*---------------------------------------- STM32F401xx------------------------*/
+#if defined(STM32F401xC) || defined(STM32F401xE)
+#define IS_GPIO_AF(AF)   (((AF) == GPIO_AF0_RTC_50Hz)   || ((AF) == GPIO_AF12_SDIO)      || \
+                          ((AF) == GPIO_AF0_MCO)        || ((AF) == GPIO_AF0_TAMPER)     || \
+                          ((AF) == GPIO_AF0_SWJ)        || ((AF) == GPIO_AF0_TRACE)      || \
+                          ((AF) == GPIO_AF1_TIM1)       || ((AF) == GPIO_AF1_TIM2)       || \
+                          ((AF) == GPIO_AF2_TIM3)       || ((AF) == GPIO_AF2_TIM4)       || \
+                          ((AF) == GPIO_AF2_TIM5)       || ((AF) == GPIO_AF3_TIM9)       || \
+                          ((AF) == GPIO_AF3_TIM10)      || ((AF) == GPIO_AF3_TIM11)      || \
+                          ((AF) == GPIO_AF4_I2C1)       || ((AF) == GPIO_AF4_I2C2)       || \
+                          ((AF) == GPIO_AF4_I2C3)       || ((AF) == GPIO_AF5_SPI1)       || \
+                          ((AF) == GPIO_AF5_SPI2)       || ((AF) == GPIO_AF5_SPI4)       || \
+                          ((AF) == GPIO_AF6_SPI3)       || ((AF) == GPIO_AF7_USART1)     || \
+                          ((AF) == GPIO_AF7_USART2)     || ((AF) == GPIO_AF8_USART6)     || \
+                          ((AF) == GPIO_AF9_I2C2)       || ((AF) == GPIO_AF9_I2C3)       || \
+                          ((AF) == GPIO_AF10_OTG_FS)    || ((AF) == GPIO_AF15_EVENTOUT))
+#endif /* STM32F401xC || STM32F401xE */
+/*----------------------------------------------------------------------------*/
+/*---------------------------------------- STM32F410xx------------------------*/
+#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) 
+#define IS_GPIO_AF(AF)   (((AF) < 10U) || ((AF) == 15U))
+#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
+
+/*---------------------------------------- STM32F411xx------------------------*/
+#if defined(STM32F411xE) 
+#define IS_GPIO_AF(AF)   (((AF) == GPIO_AF0_RTC_50Hz)   || ((AF) == GPIO_AF9_TIM14)      || \
+                          ((AF) == GPIO_AF0_MCO)        || ((AF) == GPIO_AF0_TAMPER)     || \
+                          ((AF) == GPIO_AF0_SWJ)        || ((AF) == GPIO_AF0_TRACE)      || \
+                          ((AF) == GPIO_AF1_TIM1)       || ((AF) == GPIO_AF1_TIM2)       || \
+                          ((AF) == GPIO_AF2_TIM3)       || ((AF) == GPIO_AF2_TIM4)       || \
+                          ((AF) == GPIO_AF2_TIM5)       || ((AF) == GPIO_AF4_I2C1)       || \
+                          ((AF) == GPIO_AF4_I2C2)       || ((AF) == GPIO_AF4_I2C3)       || \
+                          ((AF) == GPIO_AF5_SPI1)       || ((AF) == GPIO_AF5_SPI2)       || \
+                          ((AF) == GPIO_AF5_SPI3)       || ((AF) == GPIO_AF6_SPI4)       || \
+                          ((AF) == GPIO_AF6_SPI3)       || ((AF) == GPIO_AF5_SPI4)       || \
+                          ((AF) == GPIO_AF6_SPI5)       || ((AF) == GPIO_AF7_SPI3)       || \
+                          ((AF) == GPIO_AF7_USART1)     || ((AF) == GPIO_AF7_USART2)     || \
+                          ((AF) == GPIO_AF8_USART6)     || ((AF) == GPIO_AF10_OTG_FS)    || \
+                          ((AF) == GPIO_AF9_I2C2)       || ((AF) == GPIO_AF9_I2C3)       || \
+                          ((AF) == GPIO_AF12_SDIO)      || ((AF) == GPIO_AF15_EVENTOUT))
+
+#endif /* STM32F411xE */
+/*----------------------------------------------------------------------------*/
+
+/*----------------------------------------------- STM32F446xx ----------------*/
+#if defined(STM32F446xx) 
+#define IS_GPIO_AF(AF)   (((AF) == GPIO_AF0_RTC_50Hz)   || ((AF) == GPIO_AF9_TIM14)      || \
+                          ((AF) == GPIO_AF0_MCO)        || ((AF) == GPIO_AF0_TAMPER)     || \
+                          ((AF) == GPIO_AF0_SWJ)        || ((AF) == GPIO_AF0_TRACE)      || \
+                          ((AF) == GPIO_AF1_TIM1)       || ((AF) == GPIO_AF1_TIM2)       || \
+                          ((AF) == GPIO_AF2_TIM3)       || ((AF) == GPIO_AF2_TIM4)       || \
+                          ((AF) == GPIO_AF2_TIM5)       || ((AF) == GPIO_AF3_TIM8)       || \
+                          ((AF) == GPIO_AF4_I2C1)       || ((AF) == GPIO_AF4_I2C2)       || \
+                          ((AF) == GPIO_AF4_I2C3)       || ((AF) == GPIO_AF5_SPI1)       || \
+                          ((AF) == GPIO_AF5_SPI2)       || ((AF) == GPIO_AF9_TIM13)      || \
+                          ((AF) == GPIO_AF6_SPI3)       || ((AF) == GPIO_AF9_TIM12)      || \
+                          ((AF) == GPIO_AF7_USART1)     || ((AF) == GPIO_AF7_USART2)     || \
+                          ((AF) == GPIO_AF7_USART3)     || ((AF) == GPIO_AF8_UART4)      || \
+                          ((AF) == GPIO_AF8_UART5)      || ((AF) == GPIO_AF8_USART6)     || \
+                          ((AF) == GPIO_AF9_CAN1)       || ((AF) == GPIO_AF9_CAN2)       || \
+                          ((AF) == GPIO_AF10_OTG_FS)    || ((AF) == GPIO_AF10_OTG_HS)    || \
+                          ((AF) == GPIO_AF11_ETH)       || ((AF) == GPIO_AF12_OTG_HS_FS) || \
+                          ((AF) == GPIO_AF12_SDIO)      || ((AF) == GPIO_AF13_DCMI)      || \
+                          ((AF) == GPIO_AF15_EVENTOUT)  || ((AF) == GPIO_AF5_SPI4)       || \
+                          ((AF) == GPIO_AF12_FMC)       ||  ((AF) == GPIO_AF6_SAI1)      || \
+                          ((AF) == GPIO_AF3_CEC)        ||  ((AF) == GPIO_AF4_CEC)       || \
+                          ((AF) == GPIO_AF5_SPI3)       ||  ((AF) == GPIO_AF6_SPI2)      || \
+                          ((AF) == GPIO_AF6_SPI4)       ||  ((AF) == GPIO_AF7_UART5)     || \
+                          ((AF) == GPIO_AF7_SPI2)       ||  ((AF) == GPIO_AF7_SPI3)      || \
+                          ((AF) == GPIO_AF7_SPDIFRX)    ||  ((AF) == GPIO_AF8_SPDIFRX)   || \
+                          ((AF) == GPIO_AF8_SAI2)       ||  ((AF) == GPIO_AF9_QSPI)      || \
+                          ((AF) == GPIO_AF10_SAI2)      ||  ((AF) == GPIO_AF10_QSPI))
+
+#endif /* STM32F446xx */
+/*----------------------------------------------------------------------------*/
+
+/*------------------------------------------- STM32F469xx/STM32F479xx --------*/
+#if defined(STM32F469xx) || defined(STM32F479xx) 
+#define IS_GPIO_AF(AF)   (((AF) == GPIO_AF0_RTC_50Hz)   || ((AF) == GPIO_AF9_TIM14)      || \
+                          ((AF) == GPIO_AF0_MCO)        || ((AF) == GPIO_AF0_TAMPER)     || \
+                          ((AF) == GPIO_AF0_SWJ)        || ((AF) == GPIO_AF0_TRACE)      || \
+                          ((AF) == GPIO_AF1_TIM1)       || ((AF) == GPIO_AF1_TIM2)       || \
+                          ((AF) == GPIO_AF2_TIM3)       || ((AF) == GPIO_AF2_TIM4)       || \
+                          ((AF) == GPIO_AF2_TIM5)       || ((AF) == GPIO_AF3_TIM8)       || \
+                          ((AF) == GPIO_AF4_I2C1)       || ((AF) == GPIO_AF4_I2C2)       || \
+                          ((AF) == GPIO_AF4_I2C3)       || ((AF) == GPIO_AF5_SPI1)       || \
+                          ((AF) == GPIO_AF5_SPI2)       || ((AF) == GPIO_AF9_TIM13)      || \
+                          ((AF) == GPIO_AF6_SPI3)       || ((AF) == GPIO_AF9_TIM12)      || \
+                          ((AF) == GPIO_AF7_USART1)     || ((AF) == GPIO_AF7_USART2)     || \
+                          ((AF) == GPIO_AF7_USART3)     || ((AF) == GPIO_AF8_UART4)      || \
+                          ((AF) == GPIO_AF8_UART5)      || ((AF) == GPIO_AF8_USART6)     || \
+                          ((AF) == GPIO_AF9_CAN1)       || ((AF) == GPIO_AF9_CAN2)       || \
+                          ((AF) == GPIO_AF10_OTG_FS)    || ((AF) == GPIO_AF10_OTG_HS)    || \
+                          ((AF) == GPIO_AF11_ETH)       || ((AF) == GPIO_AF12_OTG_HS_FS) || \
+                          ((AF) == GPIO_AF12_SDIO)      || ((AF) == GPIO_AF13_DCMI)      || \
+                          ((AF) == GPIO_AF15_EVENTOUT)  || ((AF) == GPIO_AF5_SPI4)       || \
+                          ((AF) == GPIO_AF5_SPI5)       || ((AF) == GPIO_AF5_SPI6)       || \
+                          ((AF) == GPIO_AF8_UART7)      || ((AF) == GPIO_AF8_UART8)      || \
+                          ((AF) == GPIO_AF12_FMC)       || ((AF) == GPIO_AF6_SAI1)       || \
+                          ((AF) == GPIO_AF14_LTDC)      || ((AF) == GPIO_AF13_DSI)      || \
+                          ((AF) == GPIO_AF9_QSPI)       || ((AF) == GPIO_AF10_QSPI))
+
+#endif /* STM32F469xx || STM32F479xx */
+/*----------------------------------------------------------------------------*/
+
+/*------------------STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx-----------*/
+#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx)  
+#define IS_GPIO_AF(AF)   (((AF) < 16U) && ((AF) != 11U) && ((AF) != 14U) && ((AF) != 13U))
+#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */
+/*----------------------------------------------------------------------------*/
+
+/*------------------STM32F413xx/STM32F423xx-----------------------------------*/
+#if defined(STM32F413xx) || defined(STM32F423xx)  
+#define IS_GPIO_AF(AF)   (((AF) < 16U) && ((AF) != 13U))
+#endif /* STM32F413xx || STM32F423xx */
+/*----------------------------------------------------------------------------*/
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup GPIOEx_Private_Functions GPIO Private Functions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+  
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_GPIO_EX_H */
+
diff --git a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_hcd.h b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_hcd.h
new file mode 100644
index 0000000..31332a7
--- /dev/null
+++ b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_hcd.h
@@ -0,0 +1,316 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hal_hcd.h
+  * @author  MCD Application Team
+  * @brief   Header file of HCD HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2016 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32F4xx_HAL_HCD_H
+#define STM32F4xx_HAL_HCD_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_ll_usb.h"
+
+#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
+/** @addtogroup STM32F4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup HCD HCD
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup HCD_Exported_Types HCD Exported Types
+  * @{
+  */
+
+/** @defgroup HCD_Exported_Types_Group1 HCD State Structure definition
+  * @{
+  */
+typedef enum
+{
+  HAL_HCD_STATE_RESET    = 0x00,
+  HAL_HCD_STATE_READY    = 0x01,
+  HAL_HCD_STATE_ERROR    = 0x02,
+  HAL_HCD_STATE_BUSY     = 0x03,
+  HAL_HCD_STATE_TIMEOUT  = 0x04
+} HCD_StateTypeDef;
+
+typedef USB_OTG_GlobalTypeDef   HCD_TypeDef;
+typedef USB_OTG_CfgTypeDef      HCD_InitTypeDef;
+typedef USB_OTG_HCTypeDef       HCD_HCTypeDef;
+typedef USB_OTG_URBStateTypeDef HCD_URBStateTypeDef;
+typedef USB_OTG_HCStateTypeDef  HCD_HCStateTypeDef;
+/**
+  * @}
+  */
+
+/** @defgroup HCD_Exported_Types_Group2 HCD Handle Structure definition
+  * @{
+  */
+#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
+typedef struct __HCD_HandleTypeDef
+#else
+typedef struct
+#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
+{
+  HCD_TypeDef               *Instance;  /*!< Register base address    */
+  HCD_InitTypeDef           Init;       /*!< HCD required parameters  */
+  HCD_HCTypeDef             hc[16];     /*!< Host channels parameters */
+  HAL_LockTypeDef           Lock;       /*!< HCD peripheral status    */
+  __IO HCD_StateTypeDef     State;      /*!< HCD communication state  */
+  __IO  uint32_t            ErrorCode;  /*!< HCD Error code           */
+  void                      *pData;     /*!< Pointer Stack Handler    */
+#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
+  void (* SOFCallback)(struct __HCD_HandleTypeDef *hhcd);                               /*!< USB OTG HCD SOF callback                */
+  void (* ConnectCallback)(struct __HCD_HandleTypeDef *hhcd);                           /*!< USB OTG HCD Connect callback            */
+  void (* DisconnectCallback)(struct __HCD_HandleTypeDef *hhcd);                        /*!< USB OTG HCD Disconnect callback         */
+  void (* PortEnabledCallback)(struct __HCD_HandleTypeDef *hhcd);                       /*!< USB OTG HCD Port Enable callback        */
+  void (* PortDisabledCallback)(struct __HCD_HandleTypeDef *hhcd);                      /*!< USB OTG HCD Port Disable callback       */
+  void (* HC_NotifyURBChangeCallback)(struct __HCD_HandleTypeDef *hhcd, uint8_t chnum,
+                                      HCD_URBStateTypeDef urb_state);                   /*!< USB OTG HCD Host Channel Notify URB Change callback  */
+
+  void (* MspInitCallback)(struct __HCD_HandleTypeDef *hhcd);                           /*!< USB OTG HCD Msp Init callback           */
+  void (* MspDeInitCallback)(struct __HCD_HandleTypeDef *hhcd);                         /*!< USB OTG HCD Msp DeInit callback         */
+#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
+} HCD_HandleTypeDef;
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup HCD_Exported_Constants HCD Exported Constants
+  * @{
+  */
+
+/** @defgroup HCD_Speed HCD Speed
+  * @{
+  */
+#define HCD_SPEED_HIGH               USBH_HS_SPEED
+#define HCD_SPEED_FULL               USBH_FSLS_SPEED
+#define HCD_SPEED_LOW                USBH_FSLS_SPEED
+/**
+  * @}
+  */
+
+/** @defgroup HCD_Device_Speed HCD Device Speed
+  * @{
+  */
+#define HCD_DEVICE_SPEED_HIGH               0U
+#define HCD_DEVICE_SPEED_FULL               1U
+#define HCD_DEVICE_SPEED_LOW                2U
+/**
+  * @}
+  */
+
+/** @defgroup HCD_PHY_Module HCD PHY Module
+  * @{
+  */
+#define HCD_PHY_ULPI                 1U
+#define HCD_PHY_EMBEDDED             2U
+/**
+  * @}
+  */
+
+/** @defgroup HCD_Error_Code_definition HCD Error Code definition
+  * @brief  HCD Error Code definition
+  * @{
+  */
+#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
+#define  HAL_HCD_ERROR_INVALID_CALLBACK                        (0x00000010U)    /*!< Invalid Callback error  */
+#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup HCD_Exported_Macros HCD Exported Macros
+  *  @brief macros to handle interrupts and specific clock configurations
+  * @{
+  */
+#define __HAL_HCD_ENABLE(__HANDLE__)                   (void)USB_EnableGlobalInt ((__HANDLE__)->Instance)
+#define __HAL_HCD_DISABLE(__HANDLE__)                  (void)USB_DisableGlobalInt ((__HANDLE__)->Instance)
+
+#define __HAL_HCD_GET_FLAG(__HANDLE__, __INTERRUPT__)      ((USB_ReadInterrupts((__HANDLE__)->Instance)\
+                                                             & (__INTERRUPT__)) == (__INTERRUPT__))
+#define __HAL_HCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__)    (((__HANDLE__)->Instance->GINTSTS) = (__INTERRUPT__))
+#define __HAL_HCD_IS_INVALID_INTERRUPT(__HANDLE__)         (USB_ReadInterrupts((__HANDLE__)->Instance) == 0U)
+
+#define __HAL_HCD_CLEAR_HC_INT(chnum, __INTERRUPT__)  (USBx_HC(chnum)->HCINT = (__INTERRUPT__))
+#define __HAL_HCD_MASK_HALT_HC_INT(chnum)             (USBx_HC(chnum)->HCINTMSK &= ~USB_OTG_HCINTMSK_CHHM)
+#define __HAL_HCD_UNMASK_HALT_HC_INT(chnum)           (USBx_HC(chnum)->HCINTMSK |= USB_OTG_HCINTMSK_CHHM)
+#define __HAL_HCD_MASK_ACK_HC_INT(chnum)              (USBx_HC(chnum)->HCINTMSK &= ~USB_OTG_HCINTMSK_ACKM)
+#define __HAL_HCD_UNMASK_ACK_HC_INT(chnum)            (USBx_HC(chnum)->HCINTMSK |= USB_OTG_HCINTMSK_ACKM)
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup HCD_Exported_Functions HCD Exported Functions
+  * @{
+  */
+
+/** @defgroup HCD_Exported_Functions_Group1 Initialization and de-initialization functions
+  * @{
+  */
+HAL_StatusTypeDef HAL_HCD_Init(HCD_HandleTypeDef *hhcd);
+HAL_StatusTypeDef HAL_HCD_DeInit(HCD_HandleTypeDef *hhcd);
+HAL_StatusTypeDef HAL_HCD_HC_Init(HCD_HandleTypeDef *hhcd, uint8_t ch_num,
+                                  uint8_t epnum, uint8_t dev_address,
+                                  uint8_t speed, uint8_t ep_type, uint16_t mps);
+
+HAL_StatusTypeDef HAL_HCD_HC_Halt(HCD_HandleTypeDef *hhcd, uint8_t ch_num);
+void              HAL_HCD_MspInit(HCD_HandleTypeDef *hhcd);
+void              HAL_HCD_MspDeInit(HCD_HandleTypeDef *hhcd);
+
+#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
+/** @defgroup HAL_HCD_Callback_ID_enumeration_definition HAL USB OTG HCD Callback ID enumeration definition
+  * @brief  HAL USB OTG HCD Callback ID enumeration definition
+  * @{
+  */
+typedef enum
+{
+  HAL_HCD_SOF_CB_ID            = 0x01,       /*!< USB HCD SOF callback ID           */
+  HAL_HCD_CONNECT_CB_ID        = 0x02,       /*!< USB HCD Connect callback ID       */
+  HAL_HCD_DISCONNECT_CB_ID     = 0x03,       /*!< USB HCD Disconnect callback ID    */
+  HAL_HCD_PORT_ENABLED_CB_ID   = 0x04,       /*!< USB HCD Port Enable callback ID   */
+  HAL_HCD_PORT_DISABLED_CB_ID  = 0x05,       /*!< USB HCD Port Disable callback ID  */
+
+  HAL_HCD_MSPINIT_CB_ID        = 0x06,       /*!< USB HCD MspInit callback ID       */
+  HAL_HCD_MSPDEINIT_CB_ID      = 0x07        /*!< USB HCD MspDeInit callback ID     */
+
+} HAL_HCD_CallbackIDTypeDef;
+/**
+  * @}
+  */
+
+/** @defgroup HAL_HCD_Callback_pointer_definition HAL USB OTG HCD Callback pointer definition
+  * @brief  HAL USB OTG HCD Callback pointer definition
+  * @{
+  */
+
+typedef void (*pHCD_CallbackTypeDef)(HCD_HandleTypeDef *hhcd);                   /*!< pointer to a common USB OTG HCD callback function  */
+typedef void (*pHCD_HC_NotifyURBChangeCallbackTypeDef)(HCD_HandleTypeDef *hhcd,
+                                                       uint8_t epnum,
+                                                       HCD_URBStateTypeDef urb_state);   /*!< pointer to USB OTG HCD host channel  callback */
+/**
+  * @}
+  */
+
+HAL_StatusTypeDef HAL_HCD_RegisterCallback(HCD_HandleTypeDef *hhcd,
+                                           HAL_HCD_CallbackIDTypeDef CallbackID,
+                                           pHCD_CallbackTypeDef pCallback);
+
+HAL_StatusTypeDef HAL_HCD_UnRegisterCallback(HCD_HandleTypeDef *hhcd,
+                                             HAL_HCD_CallbackIDTypeDef CallbackID);
+
+HAL_StatusTypeDef HAL_HCD_RegisterHC_NotifyURBChangeCallback(HCD_HandleTypeDef *hhcd,
+                                                             pHCD_HC_NotifyURBChangeCallbackTypeDef pCallback);
+
+HAL_StatusTypeDef HAL_HCD_UnRegisterHC_NotifyURBChangeCallback(HCD_HandleTypeDef *hhcd);
+#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
+/**
+  * @}
+  */
+
+/* I/O operation functions  ***************************************************/
+/** @addtogroup HCD_Exported_Functions_Group2 Input and Output operation functions
+  * @{
+  */
+HAL_StatusTypeDef HAL_HCD_HC_SubmitRequest(HCD_HandleTypeDef *hhcd, uint8_t ch_num,
+                                           uint8_t direction, uint8_t ep_type,
+                                           uint8_t token, uint8_t *pbuff,
+                                           uint16_t length, uint8_t do_ping);
+
+/* Non-Blocking mode: Interrupt */
+void HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd);
+void HAL_HCD_WKUP_IRQHandler(HCD_HandleTypeDef *hhcd);
+void HAL_HCD_SOF_Callback(HCD_HandleTypeDef *hhcd);
+void HAL_HCD_Connect_Callback(HCD_HandleTypeDef *hhcd);
+void HAL_HCD_Disconnect_Callback(HCD_HandleTypeDef *hhcd);
+void HAL_HCD_PortEnabled_Callback(HCD_HandleTypeDef *hhcd);
+void HAL_HCD_PortDisabled_Callback(HCD_HandleTypeDef *hhcd);
+void HAL_HCD_HC_NotifyURBChange_Callback(HCD_HandleTypeDef *hhcd, uint8_t chnum,
+                                         HCD_URBStateTypeDef urb_state);
+/**
+  * @}
+  */
+
+/* Peripheral Control functions  **********************************************/
+/** @addtogroup HCD_Exported_Functions_Group3 Peripheral Control functions
+  * @{
+  */
+HAL_StatusTypeDef HAL_HCD_ResetPort(HCD_HandleTypeDef *hhcd);
+HAL_StatusTypeDef HAL_HCD_Start(HCD_HandleTypeDef *hhcd);
+HAL_StatusTypeDef HAL_HCD_Stop(HCD_HandleTypeDef *hhcd);
+/**
+  * @}
+  */
+
+/* Peripheral State functions  ************************************************/
+/** @addtogroup HCD_Exported_Functions_Group4 Peripheral State functions
+  * @{
+  */
+HCD_StateTypeDef        HAL_HCD_GetState(HCD_HandleTypeDef *hhcd);
+HCD_URBStateTypeDef     HAL_HCD_HC_GetURBState(HCD_HandleTypeDef *hhcd, uint8_t chnum);
+HCD_HCStateTypeDef      HAL_HCD_HC_GetState(HCD_HandleTypeDef *hhcd, uint8_t chnum);
+uint32_t                HAL_HCD_HC_GetXferCount(HCD_HandleTypeDef *hhcd, uint8_t chnum);
+uint32_t                HAL_HCD_GetCurrentFrame(HCD_HandleTypeDef *hhcd);
+uint32_t                HAL_HCD_GetCurrentSpeed(HCD_HandleTypeDef *hhcd);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup HCD_Private_Macros HCD Private Macros
+  * @{
+  */
+/**
+  * @}
+  */
+/* Private functions prototypes ----------------------------------------------*/
+
+/**
+  * @}
+  */
+/**
+  * @}
+  */
+#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32F4xx_HAL_HCD_H */
diff --git a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h
new file mode 100644
index 0000000..b37126e
--- /dev/null
+++ b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h
@@ -0,0 +1,741 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hal_i2c.h
+  * @author  MCD Application Team
+  * @brief   Header file of I2C HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2016 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_I2C_H
+#define __STM32F4xx_HAL_I2C_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup I2C
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup I2C_Exported_Types I2C Exported Types
+  * @{
+  */
+
+/** @defgroup I2C_Configuration_Structure_definition I2C Configuration Structure definition
+  * @brief  I2C Configuration Structure definition
+  * @{
+  */
+typedef struct
+{
+  uint32_t ClockSpeed;       /*!< Specifies the clock frequency.
+                                  This parameter must be set to a value lower than 400kHz */
+
+  uint32_t DutyCycle;        /*!< Specifies the I2C fast mode duty cycle.
+                                  This parameter can be a value of @ref I2C_duty_cycle_in_fast_mode */
+
+  uint32_t OwnAddress1;      /*!< Specifies the first device own address.
+                                  This parameter can be a 7-bit or 10-bit address. */
+
+  uint32_t AddressingMode;   /*!< Specifies if 7-bit or 10-bit addressing mode is selected.
+                                  This parameter can be a value of @ref I2C_addressing_mode */
+
+  uint32_t DualAddressMode;  /*!< Specifies if dual addressing mode is selected.
+                                  This parameter can be a value of @ref I2C_dual_addressing_mode */
+
+  uint32_t OwnAddress2;      /*!< Specifies the second device own address if dual addressing mode is selected
+                                  This parameter can be a 7-bit address. */
+
+  uint32_t GeneralCallMode;  /*!< Specifies if general call mode is selected.
+                                  This parameter can be a value of @ref I2C_general_call_addressing_mode */
+
+  uint32_t NoStretchMode;    /*!< Specifies if nostretch mode is selected.
+                                  This parameter can be a value of @ref I2C_nostretch_mode */
+
+} I2C_InitTypeDef;
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_state_structure_definition HAL state structure definition
+  * @brief  HAL State structure definition
+  * @note  HAL I2C State value coding follow below described bitmap :
+  *          b7-b6  Error information
+  *             00 : No Error
+  *             01 : Abort (Abort user request on going)
+  *             10 : Timeout
+  *             11 : Error
+  *          b5     Peripheral initialization status
+  *             0  : Reset (Peripheral not initialized)
+  *             1  : Init done (Peripheral initialized and ready to use. HAL I2C Init function called)
+  *          b4     (not used)
+  *             x  : Should be set to 0
+  *          b3
+  *             0  : Ready or Busy (No Listen mode ongoing)
+  *             1  : Listen (Peripheral in Address Listen Mode)
+  *          b2     Intrinsic process state
+  *             0  : Ready
+  *             1  : Busy (Peripheral busy with some configuration or internal operations)
+  *          b1     Rx state
+  *             0  : Ready (no Rx operation ongoing)
+  *             1  : Busy (Rx operation ongoing)
+  *          b0     Tx state
+  *             0  : Ready (no Tx operation ongoing)
+  *             1  : Busy (Tx operation ongoing)
+  * @{
+  */
+typedef enum
+{
+  HAL_I2C_STATE_RESET             = 0x00U,   /*!< Peripheral is not yet Initialized         */
+  HAL_I2C_STATE_READY             = 0x20U,   /*!< Peripheral Initialized and ready for use  */
+  HAL_I2C_STATE_BUSY              = 0x24U,   /*!< An internal process is ongoing            */
+  HAL_I2C_STATE_BUSY_TX           = 0x21U,   /*!< Data Transmission process is ongoing      */
+  HAL_I2C_STATE_BUSY_RX           = 0x22U,   /*!< Data Reception process is ongoing         */
+  HAL_I2C_STATE_LISTEN            = 0x28U,   /*!< Address Listen Mode is ongoing            */
+  HAL_I2C_STATE_BUSY_TX_LISTEN    = 0x29U,   /*!< Address Listen Mode and Data Transmission
+                                                 process is ongoing                         */
+  HAL_I2C_STATE_BUSY_RX_LISTEN    = 0x2AU,   /*!< Address Listen Mode and Data Reception
+                                                 process is ongoing                         */
+  HAL_I2C_STATE_ABORT             = 0x60U,   /*!< Abort user request ongoing                */
+  HAL_I2C_STATE_TIMEOUT           = 0xA0U,   /*!< Timeout state                             */
+  HAL_I2C_STATE_ERROR             = 0xE0U    /*!< Error                                     */
+
+} HAL_I2C_StateTypeDef;
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_mode_structure_definition HAL mode structure definition
+  * @brief  HAL Mode structure definition
+  * @note  HAL I2C Mode value coding follow below described bitmap :\n
+  *          b7     (not used)\n
+  *             x  : Should be set to 0\n
+  *          b6\n
+  *             0  : None\n
+  *             1  : Memory (HAL I2C communication is in Memory Mode)\n
+  *          b5\n
+  *             0  : None\n
+  *             1  : Slave (HAL I2C communication is in Slave Mode)\n
+  *          b4\n
+  *             0  : None\n
+  *             1  : Master (HAL I2C communication is in Master Mode)\n
+  *          b3-b2-b1-b0  (not used)\n
+  *             xxxx : Should be set to 0000
+  * @{
+  */
+typedef enum
+{
+  HAL_I2C_MODE_NONE               = 0x00U,   /*!< No I2C communication on going             */
+  HAL_I2C_MODE_MASTER             = 0x10U,   /*!< I2C communication is in Master Mode       */
+  HAL_I2C_MODE_SLAVE              = 0x20U,   /*!< I2C communication is in Slave Mode        */
+  HAL_I2C_MODE_MEM                = 0x40U    /*!< I2C communication is in Memory Mode       */
+
+} HAL_I2C_ModeTypeDef;
+
+/**
+  * @}
+  */
+
+/** @defgroup I2C_Error_Code_definition I2C Error Code definition
+  * @brief  I2C Error Code definition
+  * @{
+  */
+#define HAL_I2C_ERROR_NONE              0x00000000U    /*!< No error              */
+#define HAL_I2C_ERROR_BERR              0x00000001U    /*!< BERR error            */
+#define HAL_I2C_ERROR_ARLO              0x00000002U    /*!< ARLO error            */
+#define HAL_I2C_ERROR_AF                0x00000004U    /*!< AF error              */
+#define HAL_I2C_ERROR_OVR               0x00000008U    /*!< OVR error             */
+#define HAL_I2C_ERROR_DMA               0x00000010U    /*!< DMA transfer error    */
+#define HAL_I2C_ERROR_TIMEOUT           0x00000020U    /*!< Timeout Error         */
+#define HAL_I2C_ERROR_SIZE              0x00000040U    /*!< Size Management error */
+#define HAL_I2C_ERROR_DMA_PARAM         0x00000080U    /*!< DMA Parameter Error   */
+#define HAL_I2C_WRONG_START             0x00000200U    /*!< Wrong start Error     */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+#define HAL_I2C_ERROR_INVALID_CALLBACK  0x00000100U    /*!< Invalid Callback error */
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+/**
+  * @}
+  */
+
+/** @defgroup I2C_handle_Structure_definition I2C handle Structure definition
+  * @brief  I2C handle Structure definition
+  * @{
+  */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+typedef struct __I2C_HandleTypeDef
+#else
+typedef struct
+#endif  /* USE_HAL_I2C_REGISTER_CALLBACKS */
+{
+  I2C_TypeDef                *Instance;      /*!< I2C registers base address               */
+
+  I2C_InitTypeDef            Init;           /*!< I2C communication parameters             */
+
+  uint8_t                    *pBuffPtr;      /*!< Pointer to I2C transfer buffer           */
+
+  uint16_t                   XferSize;       /*!< I2C transfer size                        */
+
+  __IO uint16_t              XferCount;      /*!< I2C transfer counter                     */
+
+  __IO uint32_t              XferOptions;    /*!< I2C transfer options                     */
+
+  __IO uint32_t              PreviousState;  /*!< I2C communication Previous state and mode
+                                                  context for internal usage               */
+
+  DMA_HandleTypeDef          *hdmatx;        /*!< I2C Tx DMA handle parameters             */
+
+  DMA_HandleTypeDef          *hdmarx;        /*!< I2C Rx DMA handle parameters             */
+
+  HAL_LockTypeDef            Lock;           /*!< I2C locking object                       */
+
+  __IO HAL_I2C_StateTypeDef  State;          /*!< I2C communication state                  */
+
+  __IO HAL_I2C_ModeTypeDef   Mode;           /*!< I2C communication mode                   */
+
+  __IO uint32_t              ErrorCode;      /*!< I2C Error code                           */
+
+  __IO uint32_t              Devaddress;     /*!< I2C Target device address                */
+
+  __IO uint32_t              Memaddress;     /*!< I2C Target memory address                */
+
+  __IO uint32_t              MemaddSize;     /*!< I2C Target memory address  size          */
+
+  __IO uint32_t              EventCount;     /*!< I2C Event counter                        */
+
+
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+  void (* MasterTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);           /*!< I2C Master Tx Transfer completed callback */
+  void (* MasterRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);           /*!< I2C Master Rx Transfer completed callback */
+  void (* SlaveTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);            /*!< I2C Slave Tx Transfer completed callback  */
+  void (* SlaveRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);            /*!< I2C Slave Rx Transfer completed callback  */
+  void (* ListenCpltCallback)(struct __I2C_HandleTypeDef *hi2c);             /*!< I2C Listen Complete callback              */
+  void (* MemTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);              /*!< I2C Memory Tx Transfer completed callback */
+  void (* MemRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);              /*!< I2C Memory Rx Transfer completed callback */
+  void (* ErrorCallback)(struct __I2C_HandleTypeDef *hi2c);                  /*!< I2C Error callback                        */
+  void (* AbortCpltCallback)(struct __I2C_HandleTypeDef *hi2c);              /*!< I2C Abort callback                        */
+
+  void (* AddrCallback)(struct __I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode);  /*!< I2C Slave Address Match callback */
+
+  void (* MspInitCallback)(struct __I2C_HandleTypeDef *hi2c);                /*!< I2C Msp Init callback                     */
+  void (* MspDeInitCallback)(struct __I2C_HandleTypeDef *hi2c);              /*!< I2C Msp DeInit callback                   */
+
+#endif  /* USE_HAL_I2C_REGISTER_CALLBACKS */
+} I2C_HandleTypeDef;
+
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+/**
+  * @brief  HAL I2C Callback ID enumeration definition
+  */
+typedef enum
+{
+  HAL_I2C_MASTER_TX_COMPLETE_CB_ID      = 0x00U,    /*!< I2C Master Tx Transfer completed callback ID  */
+  HAL_I2C_MASTER_RX_COMPLETE_CB_ID      = 0x01U,    /*!< I2C Master Rx Transfer completed callback ID  */
+  HAL_I2C_SLAVE_TX_COMPLETE_CB_ID       = 0x02U,    /*!< I2C Slave Tx Transfer completed callback ID   */
+  HAL_I2C_SLAVE_RX_COMPLETE_CB_ID       = 0x03U,    /*!< I2C Slave Rx Transfer completed callback ID   */
+  HAL_I2C_LISTEN_COMPLETE_CB_ID         = 0x04U,    /*!< I2C Listen Complete callback ID               */
+  HAL_I2C_MEM_TX_COMPLETE_CB_ID         = 0x05U,    /*!< I2C Memory Tx Transfer callback ID            */
+  HAL_I2C_MEM_RX_COMPLETE_CB_ID         = 0x06U,    /*!< I2C Memory Rx Transfer completed callback ID  */
+  HAL_I2C_ERROR_CB_ID                   = 0x07U,    /*!< I2C Error callback ID                         */
+  HAL_I2C_ABORT_CB_ID                   = 0x08U,    /*!< I2C Abort callback ID                         */
+
+  HAL_I2C_MSPINIT_CB_ID                 = 0x09U,    /*!< I2C Msp Init callback ID                      */
+  HAL_I2C_MSPDEINIT_CB_ID               = 0x0AU     /*!< I2C Msp DeInit callback ID                    */
+
+} HAL_I2C_CallbackIDTypeDef;
+
+/**
+  * @brief  HAL I2C Callback pointer definition
+  */
+typedef  void (*pI2C_CallbackTypeDef)(I2C_HandleTypeDef *hi2c); /*!< pointer to an I2C callback function */
+typedef  void (*pI2C_AddrCallbackTypeDef)(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode); /*!< pointer to an I2C Address Match callback function */
+
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup I2C_Exported_Constants I2C Exported Constants
+  * @{
+  */
+
+/** @defgroup I2C_duty_cycle_in_fast_mode I2C duty cycle in fast mode
+  * @{
+  */
+#define I2C_DUTYCYCLE_2                 0x00000000U
+#define I2C_DUTYCYCLE_16_9              I2C_CCR_DUTY
+/**
+  * @}
+  */
+
+/** @defgroup I2C_addressing_mode I2C addressing mode
+  * @{
+  */
+#define I2C_ADDRESSINGMODE_7BIT         0x00004000U
+#define I2C_ADDRESSINGMODE_10BIT        (I2C_OAR1_ADDMODE | 0x00004000U)
+/**
+  * @}
+  */
+
+/** @defgroup I2C_dual_addressing_mode  I2C dual addressing mode
+  * @{
+  */
+#define I2C_DUALADDRESS_DISABLE        0x00000000U
+#define I2C_DUALADDRESS_ENABLE         I2C_OAR2_ENDUAL
+/**
+  * @}
+  */
+
+/** @defgroup I2C_general_call_addressing_mode I2C general call addressing mode
+  * @{
+  */
+#define I2C_GENERALCALL_DISABLE        0x00000000U
+#define I2C_GENERALCALL_ENABLE         I2C_CR1_ENGC
+/**
+  * @}
+  */
+
+/** @defgroup I2C_nostretch_mode I2C nostretch mode
+  * @{
+  */
+#define I2C_NOSTRETCH_DISABLE          0x00000000U
+#define I2C_NOSTRETCH_ENABLE           I2C_CR1_NOSTRETCH
+/**
+  * @}
+  */
+
+/** @defgroup I2C_Memory_Address_Size I2C Memory Address Size
+  * @{
+  */
+#define I2C_MEMADD_SIZE_8BIT            0x00000001U
+#define I2C_MEMADD_SIZE_16BIT           0x00000010U
+/**
+  * @}
+  */
+
+/** @defgroup I2C_XferDirection_definition I2C XferDirection definition
+  * @{
+  */
+#define I2C_DIRECTION_RECEIVE           0x00000000U
+#define I2C_DIRECTION_TRANSMIT          0x00000001U
+/**
+  * @}
+  */
+
+/** @defgroup I2C_XferOptions_definition I2C XferOptions definition
+  * @{
+  */
+#define  I2C_FIRST_FRAME                0x00000001U
+#define  I2C_FIRST_AND_NEXT_FRAME       0x00000002U
+#define  I2C_NEXT_FRAME                 0x00000004U
+#define  I2C_FIRST_AND_LAST_FRAME       0x00000008U
+#define  I2C_LAST_FRAME_NO_STOP         0x00000010U
+#define  I2C_LAST_FRAME                 0x00000020U
+
+/* List of XferOptions in usage of :
+ * 1- Restart condition in all use cases (direction change or not)
+ */
+#define  I2C_OTHER_FRAME                (0x00AA0000U)
+#define  I2C_OTHER_AND_LAST_FRAME       (0xAA000000U)
+/**
+  * @}
+  */
+
+/** @defgroup I2C_Interrupt_configuration_definition I2C Interrupt configuration definition
+  * @brief I2C Interrupt definition
+  *        Elements values convention: 0xXXXXXXXX
+  *           - XXXXXXXX  : Interrupt control mask
+  * @{
+  */
+#define I2C_IT_BUF                      I2C_CR2_ITBUFEN
+#define I2C_IT_EVT                      I2C_CR2_ITEVTEN
+#define I2C_IT_ERR                      I2C_CR2_ITERREN
+/**
+  * @}
+  */
+
+/** @defgroup I2C_Flag_definition I2C Flag definition
+  * @{
+  */
+
+#define I2C_FLAG_OVR                    0x00010800U
+#define I2C_FLAG_AF                     0x00010400U
+#define I2C_FLAG_ARLO                   0x00010200U
+#define I2C_FLAG_BERR                   0x00010100U
+#define I2C_FLAG_TXE                    0x00010080U
+#define I2C_FLAG_RXNE                   0x00010040U
+#define I2C_FLAG_STOPF                  0x00010010U
+#define I2C_FLAG_ADD10                  0x00010008U
+#define I2C_FLAG_BTF                    0x00010004U
+#define I2C_FLAG_ADDR                   0x00010002U
+#define I2C_FLAG_SB                     0x00010001U
+#define I2C_FLAG_DUALF                  0x00100080U
+#define I2C_FLAG_GENCALL                0x00100010U
+#define I2C_FLAG_TRA                    0x00100004U
+#define I2C_FLAG_BUSY                   0x00100002U
+#define I2C_FLAG_MSL                    0x00100001U
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macros -----------------------------------------------------------*/
+
+/** @defgroup I2C_Exported_Macros I2C Exported Macros
+  * @{
+  */
+
+/** @brief Reset I2C handle state.
+  * @param  __HANDLE__ specifies the I2C Handle.
+  * @retval None
+  */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__)                do{                                                   \
+                                                                    (__HANDLE__)->State = HAL_I2C_STATE_RESET;       \
+                                                                    (__HANDLE__)->MspInitCallback = NULL;            \
+                                                                    (__HANDLE__)->MspDeInitCallback = NULL;          \
+                                                                  } while(0)
+#else
+#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__)                ((__HANDLE__)->State = HAL_I2C_STATE_RESET)
+#endif
+
+/** @brief  Enable or disable the specified I2C interrupts.
+  * @param  __HANDLE__ specifies the I2C Handle.
+  * @param  __INTERRUPT__ specifies the interrupt source to enable or disable.
+  *         This parameter can be one of the following values:
+  *            @arg I2C_IT_BUF: Buffer interrupt enable
+  *            @arg I2C_IT_EVT: Event interrupt enable
+  *            @arg I2C_IT_ERR: Error interrupt enable
+  * @retval None
+  */
+#define __HAL_I2C_ENABLE_IT(__HANDLE__, __INTERRUPT__)   SET_BIT((__HANDLE__)->Instance->CR2,(__INTERRUPT__))
+#define __HAL_I2C_DISABLE_IT(__HANDLE__, __INTERRUPT__)  CLEAR_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__))
+
+/** @brief  Checks if the specified I2C interrupt source is enabled or disabled.
+  * @param  __HANDLE__ specifies the I2C Handle.
+  * @param  __INTERRUPT__ specifies the I2C interrupt source to check.
+  *          This parameter can be one of the following values:
+  *            @arg I2C_IT_BUF: Buffer interrupt enable
+  *            @arg I2C_IT_EVT: Event interrupt enable
+  *            @arg I2C_IT_ERR: Error interrupt enable
+  * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
+  */
+#define __HAL_I2C_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
+
+/** @brief  Checks whether the specified I2C flag is set or not.
+  * @param  __HANDLE__ specifies the I2C Handle.
+  * @param  __FLAG__ specifies the flag to check.
+  *         This parameter can be one of the following values:
+  *            @arg I2C_FLAG_OVR: Overrun/Underrun flag
+  *            @arg I2C_FLAG_AF: Acknowledge failure flag
+  *            @arg I2C_FLAG_ARLO: Arbitration lost flag
+  *            @arg I2C_FLAG_BERR: Bus error flag
+  *            @arg I2C_FLAG_TXE: Data register empty flag
+  *            @arg I2C_FLAG_RXNE: Data register not empty flag
+  *            @arg I2C_FLAG_STOPF: Stop detection flag
+  *            @arg I2C_FLAG_ADD10: 10-bit header sent flag
+  *            @arg I2C_FLAG_BTF: Byte transfer finished flag
+  *            @arg I2C_FLAG_ADDR: Address sent flag
+  *                                Address matched flag
+  *            @arg I2C_FLAG_SB: Start bit flag
+  *            @arg I2C_FLAG_DUALF: Dual flag
+  *            @arg I2C_FLAG_GENCALL: General call header flag
+  *            @arg I2C_FLAG_TRA: Transmitter/Receiver flag
+  *            @arg I2C_FLAG_BUSY: Bus busy flag
+  *            @arg I2C_FLAG_MSL: Master/Slave flag
+  * @retval The new state of __FLAG__ (TRUE or FALSE).
+  */
+#define __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__) ((((uint8_t)((__FLAG__) >> 16U)) == 0x01U) ? \
+                                                  (((((__HANDLE__)->Instance->SR1) & ((__FLAG__) & I2C_FLAG_MASK)) == ((__FLAG__) & I2C_FLAG_MASK)) ? SET : RESET) : \
+                                                  (((((__HANDLE__)->Instance->SR2) & ((__FLAG__) & I2C_FLAG_MASK)) == ((__FLAG__) & I2C_FLAG_MASK)) ? SET : RESET))
+
+/** @brief  Clears the I2C pending flags which are cleared by writing 0 in a specific bit.
+  * @param  __HANDLE__ specifies the I2C Handle.
+  * @param  __FLAG__ specifies the flag to clear.
+  *         This parameter can be any combination of the following values:
+  *            @arg I2C_FLAG_OVR: Overrun/Underrun flag (Slave mode)
+  *            @arg I2C_FLAG_AF: Acknowledge failure flag
+  *            @arg I2C_FLAG_ARLO: Arbitration lost flag (Master mode)
+  *            @arg I2C_FLAG_BERR: Bus error flag
+  * @retval None
+  */
+#define __HAL_I2C_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR1 = ~((__FLAG__) & I2C_FLAG_MASK))
+
+/** @brief  Clears the I2C ADDR pending flag.
+  * @param  __HANDLE__ specifies the I2C Handle.
+  *         This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral.
+  * @retval None
+  */
+#define __HAL_I2C_CLEAR_ADDRFLAG(__HANDLE__)    \
+  do{                                           \
+    __IO uint32_t tmpreg = 0x00U;               \
+    tmpreg = (__HANDLE__)->Instance->SR1;       \
+    tmpreg = (__HANDLE__)->Instance->SR2;       \
+    UNUSED(tmpreg);                             \
+  } while(0)
+
+/** @brief  Clears the I2C STOPF pending flag.
+  * @param  __HANDLE__ specifies the I2C Handle.
+  * @retval None
+  */
+#define __HAL_I2C_CLEAR_STOPFLAG(__HANDLE__)           \
+  do{                                                  \
+    __IO uint32_t tmpreg = 0x00U;                      \
+    tmpreg = (__HANDLE__)->Instance->SR1;              \
+    SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE);  \
+    UNUSED(tmpreg);                                    \
+  } while(0)
+
+/** @brief  Enable the specified I2C peripheral.
+  * @param  __HANDLE__ specifies the I2C Handle.
+  * @retval None
+  */
+#define __HAL_I2C_ENABLE(__HANDLE__)                  SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE)
+
+/** @brief  Disable the specified I2C peripheral.
+  * @param  __HANDLE__ specifies the I2C Handle.
+  * @retval None
+  */
+#define __HAL_I2C_DISABLE(__HANDLE__)                 CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE)
+
+/**
+  * @}
+  */
+
+/* Include I2C HAL Extension module */
+#include "stm32f4xx_hal_i2c_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup I2C_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions
+  * @{
+  */
+/* Initialization and de-initialization functions******************************/
+HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c);
+HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c);
+
+/* Callbacks Register/UnRegister functions  ***********************************/
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+HAL_StatusTypeDef HAL_I2C_RegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID, pI2C_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_I2C_UnRegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID);
+
+HAL_StatusTypeDef HAL_I2C_RegisterAddrCallback(I2C_HandleTypeDef *hi2c, pI2C_AddrCallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef *hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+/**
+  * @}
+  */
+
+/** @addtogroup I2C_Exported_Functions_Group2 Input and Output operation functions
+  * @{
+  */
+/* IO operation functions  ****************************************************/
+/******* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout);
+
+/******* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
+
+HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
+HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
+HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
+HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
+HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c);
+HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c);
+HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress);
+
+/******* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
+
+HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
+HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
+HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
+HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
+/**
+  * @}
+  */
+
+/** @addtogroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
+ * @{
+ */
+/******* I2C IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */
+void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode);
+void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c);
+/**
+  * @}
+  */
+
+/** @addtogroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions
+  * @{
+  */
+/* Peripheral State, Mode and Error functions  *********************************/
+HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c);
+HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c);
+uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup I2C_Private_Constants I2C Private Constants
+  * @{
+  */
+#define I2C_FLAG_MASK                    0x0000FFFFU
+#define I2C_MIN_PCLK_FREQ_STANDARD       2000000U     /*!< 2 MHz                     */
+#define I2C_MIN_PCLK_FREQ_FAST           4000000U     /*!< 4 MHz                     */
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup I2C_Private_Macros I2C Private Macros
+  * @{
+  */
+
+#define I2C_MIN_PCLK_FREQ(__PCLK__, __SPEED__)             (((__SPEED__) <= 100000U) ? ((__PCLK__) < I2C_MIN_PCLK_FREQ_STANDARD) : ((__PCLK__) < I2C_MIN_PCLK_FREQ_FAST))
+#define I2C_CCR_CALCULATION(__PCLK__, __SPEED__, __COEFF__)     (((((__PCLK__) - 1U)/((__SPEED__) * (__COEFF__))) + 1U) & I2C_CCR_CCR)
+#define I2C_FREQRANGE(__PCLK__)                            ((__PCLK__)/1000000U)
+#define I2C_RISE_TIME(__FREQRANGE__, __SPEED__)            (((__SPEED__) <= 100000U) ? ((__FREQRANGE__) + 1U) : ((((__FREQRANGE__) * 300U) / 1000U) + 1U))
+#define I2C_SPEED_STANDARD(__PCLK__, __SPEED__)            ((I2C_CCR_CALCULATION((__PCLK__), (__SPEED__), 2U) < 4U)? 4U:I2C_CCR_CALCULATION((__PCLK__), (__SPEED__), 2U))
+#define I2C_SPEED_FAST(__PCLK__, __SPEED__, __DUTYCYCLE__) (((__DUTYCYCLE__) == I2C_DUTYCYCLE_2)? I2C_CCR_CALCULATION((__PCLK__), (__SPEED__), 3U) : (I2C_CCR_CALCULATION((__PCLK__), (__SPEED__), 25U) | I2C_DUTYCYCLE_16_9))
+#define I2C_SPEED(__PCLK__, __SPEED__, __DUTYCYCLE__)      (((__SPEED__) <= 100000U)? (I2C_SPEED_STANDARD((__PCLK__), (__SPEED__))) : \
+                                                                  ((I2C_SPEED_FAST((__PCLK__), (__SPEED__), (__DUTYCYCLE__)) & I2C_CCR_CCR) == 0U)? 1U : \
+                                                                  ((I2C_SPEED_FAST((__PCLK__), (__SPEED__), (__DUTYCYCLE__))) | I2C_CCR_FS))
+
+#define I2C_7BIT_ADD_WRITE(__ADDRESS__)                    ((uint8_t)((__ADDRESS__) & (uint8_t)(~I2C_OAR1_ADD0)))
+#define I2C_7BIT_ADD_READ(__ADDRESS__)                     ((uint8_t)((__ADDRESS__) | I2C_OAR1_ADD0))
+
+#define I2C_10BIT_ADDRESS(__ADDRESS__)                     ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)0x00FF)))
+#define I2C_10BIT_HEADER_WRITE(__ADDRESS__)                ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)0x0300)) >> 7) | (uint16_t)0x00F0)))
+#define I2C_10BIT_HEADER_READ(__ADDRESS__)                 ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)0x0300)) >> 7) | (uint16_t)(0x00F1))))
+
+#define I2C_MEM_ADD_MSB(__ADDRESS__)                       ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)0xFF00)) >> 8)))
+#define I2C_MEM_ADD_LSB(__ADDRESS__)                       ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)0x00FF)))
+
+/** @defgroup I2C_IS_RTC_Definitions I2C Private macros to check input parameters
+  * @{
+  */
+#define IS_I2C_DUTY_CYCLE(CYCLE) (((CYCLE) == I2C_DUTYCYCLE_2) || \
+                                  ((CYCLE) == I2C_DUTYCYCLE_16_9))
+#define IS_I2C_ADDRESSING_MODE(ADDRESS) (((ADDRESS) == I2C_ADDRESSINGMODE_7BIT) || \
+                                         ((ADDRESS) == I2C_ADDRESSINGMODE_10BIT))
+#define IS_I2C_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == I2C_DUALADDRESS_DISABLE) || \
+                                      ((ADDRESS) == I2C_DUALADDRESS_ENABLE))
+#define IS_I2C_GENERAL_CALL(CALL) (((CALL) == I2C_GENERALCALL_DISABLE) || \
+                                   ((CALL) == I2C_GENERALCALL_ENABLE))
+#define IS_I2C_NO_STRETCH(STRETCH) (((STRETCH) == I2C_NOSTRETCH_DISABLE) || \
+                                    ((STRETCH) == I2C_NOSTRETCH_ENABLE))
+#define IS_I2C_MEMADD_SIZE(SIZE) (((SIZE) == I2C_MEMADD_SIZE_8BIT) || \
+                                  ((SIZE) == I2C_MEMADD_SIZE_16BIT))
+#define IS_I2C_CLOCK_SPEED(SPEED) (((SPEED) > 0U) && ((SPEED) <= 400000U))
+#define IS_I2C_OWN_ADDRESS1(ADDRESS1) (((ADDRESS1) & 0xFFFFFC00U) == 0U)
+#define IS_I2C_OWN_ADDRESS2(ADDRESS2) (((ADDRESS2) & 0xFFFFFF01U) == 0U)
+#define IS_I2C_TRANSFER_OPTIONS_REQUEST(REQUEST)      (((REQUEST) == I2C_FIRST_FRAME)              || \
+                                                       ((REQUEST) == I2C_FIRST_AND_NEXT_FRAME)     || \
+                                                       ((REQUEST) == I2C_NEXT_FRAME)               || \
+                                                       ((REQUEST) == I2C_FIRST_AND_LAST_FRAME)     || \
+                                                       ((REQUEST) == I2C_LAST_FRAME)               || \
+                                                       ((REQUEST) == I2C_LAST_FRAME_NO_STOP)       || \
+                                                       IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST))
+
+#define IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == I2C_OTHER_FRAME)     || \
+                                                        ((REQUEST) == I2C_OTHER_AND_LAST_FRAME))
+
+#define I2C_CHECK_FLAG(__ISR__, __FLAG__)         ((((__ISR__) & ((__FLAG__) & I2C_FLAG_MASK)) == ((__FLAG__) & I2C_FLAG_MASK)) ? SET : RESET)
+#define I2C_CHECK_IT_SOURCE(__CR1__, __IT__)      ((((__CR1__) & (__IT__)) == (__IT__)) ? SET : RESET)
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup I2C_Private_Functions I2C Private Functions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* __STM32F4xx_HAL_I2C_H */
+
diff --git a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c_ex.h b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c_ex.h
new file mode 100644
index 0000000..e2ee7c8
--- /dev/null
+++ b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c_ex.h
@@ -0,0 +1,115 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hal_i2c_ex.h
+  * @author  MCD Application Team
+  * @brief   Header file of I2C HAL Extension module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2016 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_I2C_EX_H
+#define __STM32F4xx_HAL_I2C_EX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if  defined(I2C_FLTR_ANOFF)&&defined(I2C_FLTR_DNF)
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup I2CEx
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup I2CEx_Exported_Constants I2C Exported Constants
+  * @{
+  */
+
+/** @defgroup I2CEx_Analog_Filter I2C Analog Filter
+  * @{
+  */
+#define I2C_ANALOGFILTER_ENABLE        0x00000000U
+#define I2C_ANALOGFILTER_DISABLE       I2C_FLTR_ANOFF
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup I2CEx_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup I2CEx_Exported_Functions_Group1
+  * @{
+  */
+/* Peripheral Control functions  ************************************************/
+HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter);
+HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter);
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup I2CEx_Private_Constants I2C Private Constants
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup I2CEx_Private_Macros I2C Private Macros
+  * @{
+  */
+#define IS_I2C_ANALOG_FILTER(FILTER) (((FILTER) == I2C_ANALOGFILTER_ENABLE) || \
+                                      ((FILTER) == I2C_ANALOGFILTER_DISABLE))
+#define IS_I2C_DIGITAL_FILTER(FILTER)   ((FILTER) <= 0x0000000FU)
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_I2C_EX_H */
+
+
diff --git a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_ltdc.h b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_ltdc.h
new file mode 100644
index 0000000..b398b81
--- /dev/null
+++ b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_ltdc.h
@@ -0,0 +1,719 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hal_ltdc.h
+  * @author  MCD Application Team
+  * @brief   Header file of LTDC HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2016 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32F4xx_HAL_LTDC_H
+#define STM32F4xx_HAL_LTDC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+#if defined (LTDC)
+
+/** @addtogroup STM32F4xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup LTDC LTDC
+  * @brief LTDC HAL module driver
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup LTDC_Exported_Types LTDC Exported Types
+  * @{
+  */
+#define MAX_LAYER  2U
+
+/**
+  * @brief  LTDC color structure definition
+  */
+typedef struct
+{
+  uint8_t Blue;                    /*!< Configures the blue value.
+                                        This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */
+
+  uint8_t Green;                   /*!< Configures the green value.
+                                        This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */
+
+  uint8_t Red;                     /*!< Configures the red value.
+                                        This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */
+
+  uint8_t Reserved;                /*!< Reserved 0xFF */
+} LTDC_ColorTypeDef;
+
+/**
+  * @brief  LTDC Init structure definition
+  */
+typedef struct
+{
+  uint32_t            HSPolarity;                /*!< configures the horizontal synchronization polarity.
+                                                      This parameter can be one value of @ref LTDC_HS_POLARITY */
+
+  uint32_t            VSPolarity;                /*!< configures the vertical synchronization polarity.
+                                                      This parameter can be one value of @ref LTDC_VS_POLARITY */
+
+  uint32_t            DEPolarity;                /*!< configures the data enable polarity.
+                                                      This parameter can be one of value of @ref LTDC_DE_POLARITY */
+
+  uint32_t            PCPolarity;                /*!< configures the pixel clock polarity.
+                                                      This parameter can be one of value of @ref LTDC_PC_POLARITY */
+
+  uint32_t            HorizontalSync;            /*!< configures the number of Horizontal synchronization width.
+                                                      This parameter must be a number between
+                                                      Min_Data = 0x000 and Max_Data = 0xFFF. */
+
+  uint32_t            VerticalSync;              /*!< configures the number of Vertical synchronization height.
+                                                      This parameter must be a number between
+                                                      Min_Data = 0x000 and Max_Data = 0x7FF. */
+
+  uint32_t            AccumulatedHBP;            /*!< configures the accumulated horizontal back porch width.
+                                                      This parameter must be a number between
+                                                      Min_Data = LTDC_HorizontalSync and Max_Data = 0xFFF. */
+
+  uint32_t            AccumulatedVBP;            /*!< configures the accumulated vertical back porch height.
+                                                      This parameter must be a number between
+                                                      Min_Data = LTDC_VerticalSync and Max_Data = 0x7FF. */
+
+  uint32_t            AccumulatedActiveW;        /*!< configures the accumulated active width.
+                                                      This parameter must be a number between
+                                                      Min_Data = LTDC_AccumulatedHBP and Max_Data = 0xFFF. */
+
+  uint32_t            AccumulatedActiveH;        /*!< configures the accumulated active height.
+                                                      This parameter must be a number between
+                                                      Min_Data = LTDC_AccumulatedVBP and Max_Data = 0x7FF. */
+
+  uint32_t            TotalWidth;                /*!< configures the total width.
+                                                      This parameter must be a number between
+                                                      Min_Data = LTDC_AccumulatedActiveW and Max_Data = 0xFFF. */
+
+  uint32_t            TotalHeigh;                /*!< configures the total height.
+                                                      This parameter must be a number between
+                                                      Min_Data = LTDC_AccumulatedActiveH and Max_Data = 0x7FF. */
+
+  LTDC_ColorTypeDef   Backcolor;                 /*!< Configures the background color. */
+} LTDC_InitTypeDef;
+
+/**
+  * @brief  LTDC Layer structure definition
+  */
+typedef struct
+{
+  uint32_t WindowX0;                   /*!< Configures the Window Horizontal Start Position.
+                                            This parameter must be a number between
+                                            Min_Data = 0x000 and Max_Data = 0xFFF. */
+
+  uint32_t WindowX1;                   /*!< Configures the Window Horizontal Stop Position.
+                                            This parameter must be a number between
+                                            Min_Data = 0x000 and Max_Data = 0xFFF. */
+
+  uint32_t WindowY0;                   /*!< Configures the Window vertical Start Position.
+                                            This parameter must be a number between
+                                            Min_Data = 0x000 and Max_Data = 0x7FF. */
+
+  uint32_t WindowY1;                   /*!< Configures the Window vertical Stop Position.
+                                            This parameter must be a number between
+                                            Min_Data = 0x0000 and Max_Data = 0x7FF. */
+
+  uint32_t PixelFormat;                /*!< Specifies the pixel format.
+                                            This parameter can be one of value of @ref LTDC_Pixelformat */
+
+  uint32_t Alpha;                      /*!< Specifies the constant alpha used for blending.
+                                            This parameter must be a number between
+                                            Min_Data = 0x00 and Max_Data = 0xFF. */
+
+  uint32_t Alpha0;                     /*!< Configures the default alpha value.
+                                            This parameter must be a number between
+                                            Min_Data = 0x00 and Max_Data = 0xFF. */
+
+  uint32_t BlendingFactor1;            /*!< Select the blending factor 1.
+                                            This parameter can be one of value of @ref LTDC_BlendingFactor1 */
+
+  uint32_t BlendingFactor2;            /*!< Select the blending factor 2.
+                                            This parameter can be one of value of @ref LTDC_BlendingFactor2 */
+
+  uint32_t FBStartAdress;              /*!< Configures the color frame buffer address */
+
+  uint32_t ImageWidth;                 /*!< Configures the color frame buffer line length.
+                                            This parameter must be a number between
+                                            Min_Data = 0x0000 and Max_Data = 0x1FFF. */
+
+  uint32_t ImageHeight;                /*!< Specifies the number of line in frame buffer.
+                                            This parameter must be a number between
+                                            Min_Data = 0x000 and Max_Data = 0x7FF. */
+
+  LTDC_ColorTypeDef   Backcolor;       /*!< Configures the layer background color. */
+} LTDC_LayerCfgTypeDef;
+
+/**
+  * @brief  HAL LTDC State structures definition
+  */
+typedef enum
+{
+  HAL_LTDC_STATE_RESET             = 0x00U,    /*!< LTDC not yet initialized or disabled */
+  HAL_LTDC_STATE_READY             = 0x01U,    /*!< LTDC initialized and ready for use   */
+  HAL_LTDC_STATE_BUSY              = 0x02U,    /*!< LTDC internal process is ongoing     */
+  HAL_LTDC_STATE_TIMEOUT           = 0x03U,    /*!< LTDC Timeout state                   */
+  HAL_LTDC_STATE_ERROR             = 0x04U     /*!< LTDC state error                     */
+} HAL_LTDC_StateTypeDef;
+
+/**
+  * @brief  LTDC handle Structure definition
+  */
+#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1)
+typedef struct __LTDC_HandleTypeDef
+#else
+typedef struct
+#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */
+{
+  LTDC_TypeDef                *Instance;                /*!< LTDC Register base address                */
+
+  LTDC_InitTypeDef            Init;                     /*!< LTDC parameters                           */
+
+  LTDC_LayerCfgTypeDef        LayerCfg[MAX_LAYER];      /*!< LTDC Layers parameters                    */
+
+  HAL_LockTypeDef             Lock;                     /*!< LTDC Lock                                 */
+
+  __IO HAL_LTDC_StateTypeDef  State;                    /*!< LTDC state                                */
+
+  __IO uint32_t               ErrorCode;                /*!< LTDC Error code                           */
+
+#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1)
+  void (* LineEventCallback)(struct __LTDC_HandleTypeDef *hltdc);     /*!< LTDC Line Event Callback    */
+  void (* ReloadEventCallback)(struct __LTDC_HandleTypeDef *hltdc);   /*!< LTDC Reload Event Callback  */
+  void (* ErrorCallback)(struct __LTDC_HandleTypeDef *hltdc);         /*!< LTDC Error Callback         */
+
+  void (* MspInitCallback)(struct __LTDC_HandleTypeDef *hltdc);       /*!< LTDC Msp Init callback      */
+  void (* MspDeInitCallback)(struct __LTDC_HandleTypeDef *hltdc);     /*!< LTDC Msp DeInit callback    */
+
+#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */
+
+
+} LTDC_HandleTypeDef;
+
+#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1)
+/**
+  * @brief  HAL LTDC Callback ID enumeration definition
+  */
+typedef enum
+{
+  HAL_LTDC_MSPINIT_CB_ID            = 0x00U,    /*!< LTDC MspInit callback ID       */
+  HAL_LTDC_MSPDEINIT_CB_ID          = 0x01U,    /*!< LTDC MspDeInit callback ID     */
+
+  HAL_LTDC_LINE_EVENT_CB_ID         = 0x02U,    /*!< LTDC Line Event Callback ID    */
+  HAL_LTDC_RELOAD_EVENT_CB_ID       = 0x03U,    /*!< LTDC Reload Callback ID        */
+  HAL_LTDC_ERROR_CB_ID              = 0x04U     /*!< LTDC Error Callback ID         */
+
+} HAL_LTDC_CallbackIDTypeDef;
+
+/**
+  * @brief  HAL LTDC Callback pointer definition
+  */
+typedef  void (*pLTDC_CallbackTypeDef)(LTDC_HandleTypeDef *hltdc);  /*!< pointer to an LTDC callback function */
+
+#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup LTDC_Exported_Constants LTDC Exported Constants
+  * @{
+  */
+
+/** @defgroup LTDC_Error_Code LTDC Error Code
+  * @{
+  */
+#define HAL_LTDC_ERROR_NONE               0x00000000U   /*!< LTDC No error             */
+#define HAL_LTDC_ERROR_TE                 0x00000001U   /*!< LTDC Transfer error       */
+#define HAL_LTDC_ERROR_FU                 0x00000002U   /*!< LTDC FIFO Underrun        */
+#define HAL_LTDC_ERROR_TIMEOUT            0x00000020U   /*!< LTDC Timeout error        */
+#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1)
+#define  HAL_LTDC_ERROR_INVALID_CALLBACK  0x00000040U   /*!< LTDC Invalid Callback error  */
+#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */
+/**
+  * @}
+  */
+
+/** @defgroup LTDC_Layer LTDC Layer
+  * @{
+  */
+#define LTDC_LAYER_1                      0x00000000U   /*!< LTDC Layer 1 */
+#define LTDC_LAYER_2                      0x00000001U   /*!< LTDC Layer 2 */
+/**
+  * @}
+  */
+
+/** @defgroup LTDC_HS_POLARITY LTDC HS POLARITY
+  * @{
+  */
+#define LTDC_HSPOLARITY_AL                0x00000000U   /*!< Horizontal Synchronization is active low. */
+#define LTDC_HSPOLARITY_AH                LTDC_GCR_HSPOL            /*!< Horizontal Synchronization is active high. */
+/**
+  * @}
+  */
+
+/** @defgroup LTDC_VS_POLARITY LTDC VS POLARITY
+  * @{
+  */
+#define LTDC_VSPOLARITY_AL                0x00000000U   /*!< Vertical Synchronization is active low. */
+#define LTDC_VSPOLARITY_AH                LTDC_GCR_VSPOL            /*!< Vertical Synchronization is active high. */
+/**
+  * @}
+  */
+
+/** @defgroup LTDC_DE_POLARITY LTDC DE POLARITY
+  * @{
+  */
+#define LTDC_DEPOLARITY_AL                0x00000000U   /*!< Data Enable, is active low. */
+#define LTDC_DEPOLARITY_AH                LTDC_GCR_DEPOL            /*!< Data Enable, is active high. */
+/**
+  * @}
+  */
+
+/** @defgroup LTDC_PC_POLARITY LTDC PC POLARITY
+  * @{
+  */
+#define LTDC_PCPOLARITY_IPC               0x00000000U   /*!< input pixel clock. */
+#define LTDC_PCPOLARITY_IIPC              LTDC_GCR_PCPOL            /*!< inverted input pixel clock. */
+/**
+  * @}
+  */
+
+/** @defgroup LTDC_SYNC LTDC SYNC
+  * @{
+  */
+#define LTDC_HORIZONTALSYNC               (LTDC_SSCR_HSW >> 16U)    /*!< Horizontal synchronization width. */
+#define LTDC_VERTICALSYNC                 LTDC_SSCR_VSH             /*!< Vertical synchronization height. */
+/**
+  * @}
+  */
+
+/** @defgroup LTDC_BACK_COLOR LTDC BACK COLOR
+  * @{
+  */
+#define LTDC_COLOR                        0x000000FFU   /*!< Color mask */
+/**
+  * @}
+  */
+
+/** @defgroup LTDC_BlendingFactor1 LTDC Blending Factor1
+  * @{
+  */
+#define LTDC_BLENDING_FACTOR1_CA          0x00000400U   /*!< Blending factor : Cte Alpha */
+#define LTDC_BLENDING_FACTOR1_PAxCA       0x00000600U   /*!< Blending factor : Cte Alpha x Pixel Alpha*/
+/**
+  * @}
+  */
+
+/** @defgroup LTDC_BlendingFactor2 LTDC Blending Factor2
+  * @{
+  */
+#define LTDC_BLENDING_FACTOR2_CA          0x00000005U   /*!< Blending factor : Cte Alpha */
+#define LTDC_BLENDING_FACTOR2_PAxCA       0x00000007U   /*!< Blending factor : Cte Alpha x Pixel Alpha*/
+/**
+  * @}
+  */
+
+/** @defgroup LTDC_Pixelformat LTDC Pixel format
+  * @{
+  */
+#define LTDC_PIXEL_FORMAT_ARGB8888        0x00000000U   /*!< ARGB8888 LTDC pixel format */
+#define LTDC_PIXEL_FORMAT_RGB888          0x00000001U   /*!< RGB888 LTDC pixel format   */
+#define LTDC_PIXEL_FORMAT_RGB565          0x00000002U   /*!< RGB565 LTDC pixel format   */
+#define LTDC_PIXEL_FORMAT_ARGB1555        0x00000003U   /*!< ARGB1555 LTDC pixel format */
+#define LTDC_PIXEL_FORMAT_ARGB4444        0x00000004U   /*!< ARGB4444 LTDC pixel format */
+#define LTDC_PIXEL_FORMAT_L8              0x00000005U   /*!< L8 LTDC pixel format       */
+#define LTDC_PIXEL_FORMAT_AL44            0x00000006U   /*!< AL44 LTDC pixel format     */
+#define LTDC_PIXEL_FORMAT_AL88            0x00000007U   /*!< AL88 LTDC pixel format     */
+/**
+  * @}
+  */
+
+/** @defgroup LTDC_Alpha LTDC Alpha
+  * @{
+  */
+#define LTDC_ALPHA                        LTDC_LxCACR_CONSTA        /*!< LTDC Constant Alpha mask */
+/**
+  * @}
+  */
+
+/** @defgroup LTDC_LAYER_Config LTDC LAYER Config
+  * @{
+  */
+#define LTDC_STOPPOSITION                 (LTDC_LxWHPCR_WHSPPOS >> 16U) /*!< LTDC Layer stop position  */
+#define LTDC_STARTPOSITION                LTDC_LxWHPCR_WHSTPOS          /*!< LTDC Layer start position */
+
+#define LTDC_COLOR_FRAME_BUFFER           LTDC_LxCFBLR_CFBLL            /*!< LTDC Layer Line length    */
+#define LTDC_LINE_NUMBER                  LTDC_LxCFBLNR_CFBLNBR         /*!< LTDC Layer Line number    */
+/**
+  * @}
+  */
+
+/** @defgroup LTDC_Interrupts LTDC Interrupts
+  * @{
+  */
+#define LTDC_IT_LI                        LTDC_IER_LIE              /*!< LTDC Line Interrupt            */
+#define LTDC_IT_FU                        LTDC_IER_FUIE             /*!< LTDC FIFO Underrun Interrupt   */
+#define LTDC_IT_TE                        LTDC_IER_TERRIE           /*!< LTDC Transfer Error Interrupt  */
+#define LTDC_IT_RR                        LTDC_IER_RRIE             /*!< LTDC Register Reload Interrupt */
+/**
+  * @}
+  */
+
+/** @defgroup LTDC_Flags LTDC Flags
+  * @{
+  */
+#define LTDC_FLAG_LI                      LTDC_ISR_LIF              /*!< LTDC Line Interrupt Flag            */
+#define LTDC_FLAG_FU                      LTDC_ISR_FUIF             /*!< LTDC FIFO Underrun interrupt Flag   */
+#define LTDC_FLAG_TE                      LTDC_ISR_TERRIF           /*!< LTDC Transfer Error interrupt Flag  */
+#define LTDC_FLAG_RR                      LTDC_ISR_RRIF             /*!< LTDC Register Reload interrupt Flag */
+/**
+  * @}
+  */
+
+/** @defgroup LTDC_Reload_Type LTDC Reload Type
+  * @{
+  */
+#define LTDC_RELOAD_IMMEDIATE             LTDC_SRCR_IMR             /*!< Immediate Reload */
+#define LTDC_RELOAD_VERTICAL_BLANKING     LTDC_SRCR_VBR             /*!< Vertical Blanking Reload */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup LTDC_Exported_Macros LTDC Exported Macros
+  * @{
+  */
+
+/** @brief Reset LTDC handle state.
+  * @param  __HANDLE__  LTDC handle
+  * @retval None
+  */
+#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1)
+#define __HAL_LTDC_RESET_HANDLE_STATE(__HANDLE__) do{                                                 \
+                                                      (__HANDLE__)->State = HAL_LTDC_STATE_RESET;     \
+                                                      (__HANDLE__)->MspInitCallback = NULL;           \
+                                                      (__HANDLE__)->MspDeInitCallback = NULL;         \
+                                                    } while(0)
+#else
+#define __HAL_LTDC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_LTDC_STATE_RESET)
+#endif /*USE_HAL_LTDC_REGISTER_CALLBACKS */
+
+/**
+  * @brief  Enable the LTDC.
+  * @param  __HANDLE__  LTDC handle
+  * @retval None.
+  */
+#define __HAL_LTDC_ENABLE(__HANDLE__)    ((__HANDLE__)->Instance->GCR |= LTDC_GCR_LTDCEN)
+
+/**
+  * @brief  Disable the LTDC.
+  * @param  __HANDLE__  LTDC handle
+  * @retval None.
+  */
+#define __HAL_LTDC_DISABLE(__HANDLE__)   ((__HANDLE__)->Instance->GCR &= ~(LTDC_GCR_LTDCEN))
+
+/**
+  * @brief  Enable the LTDC Layer.
+  * @param  __HANDLE__  LTDC handle
+  * @param  __LAYER__   Specify the layer to be enabled.
+  *                     This parameter can be LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1).
+  * @retval None.
+  */
+#define __HAL_LTDC_LAYER_ENABLE(__HANDLE__, __LAYER__)  ((LTDC_LAYER((__HANDLE__), (__LAYER__)))->CR\
+                                                         |= (uint32_t)LTDC_LxCR_LEN)
+
+/**
+  * @brief  Disable the LTDC Layer.
+  * @param  __HANDLE__  LTDC handle
+  * @param  __LAYER__   Specify the layer to be disabled.
+  *                     This parameter can be LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1).
+  * @retval None.
+  */
+#define __HAL_LTDC_LAYER_DISABLE(__HANDLE__, __LAYER__) ((LTDC_LAYER((__HANDLE__), (__LAYER__)))->CR\
+                                                         &= ~(uint32_t)LTDC_LxCR_LEN)
+
+/**
+  * @brief  Reload immediately all LTDC Layers.
+  * @param  __HANDLE__  LTDC handle
+  * @retval None.
+  */
+#define __HAL_LTDC_RELOAD_IMMEDIATE_CONFIG(__HANDLE__)  ((__HANDLE__)->Instance->SRCR |= LTDC_SRCR_IMR)
+
+/**
+  * @brief  Reload during vertical blanking period all LTDC Layers.
+  * @param  __HANDLE__  LTDC handle
+  * @retval None.
+  */
+#define __HAL_LTDC_VERTICAL_BLANKING_RELOAD_CONFIG(__HANDLE__)  ((__HANDLE__)->Instance->SRCR |= LTDC_SRCR_VBR)
+
+/* Interrupt & Flag management */
+/**
+  * @brief  Get the LTDC pending flags.
+  * @param  __HANDLE__  LTDC handle
+  * @param  __FLAG__    Get the specified flag.
+  *          This parameter can be any combination of the following values:
+  *            @arg LTDC_FLAG_LI: Line Interrupt flag
+  *            @arg LTDC_FLAG_FU: FIFO Underrun Interrupt flag
+  *            @arg LTDC_FLAG_TE: Transfer Error interrupt flag
+  *            @arg LTDC_FLAG_RR: Register Reload Interrupt Flag
+  * @retval The state of FLAG (SET or RESET).
+  */
+#define __HAL_LTDC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR & (__FLAG__))
+
+/**
+  * @brief  Clears the LTDC pending flags.
+  * @param  __HANDLE__  LTDC handle
+  * @param  __FLAG__    Specify the flag to clear.
+  *          This parameter can be any combination of the following values:
+  *            @arg LTDC_FLAG_LI: Line Interrupt flag
+  *            @arg LTDC_FLAG_FU: FIFO Underrun Interrupt flag
+  *            @arg LTDC_FLAG_TE: Transfer Error interrupt flag
+  *            @arg LTDC_FLAG_RR: Register Reload Interrupt Flag
+  * @retval None
+  */
+#define __HAL_LTDC_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
+
+/**
+  * @brief  Enables the specified LTDC interrupts.
+  * @param  __HANDLE__  LTDC handle
+  * @param __INTERRUPT__ Specify the LTDC interrupt sources to be enabled.
+  *          This parameter can be any combination of the following values:
+  *            @arg LTDC_IT_LI: Line Interrupt flag
+  *            @arg LTDC_IT_FU: FIFO Underrun Interrupt flag
+  *            @arg LTDC_IT_TE: Transfer Error interrupt flag
+  *            @arg LTDC_IT_RR: Register Reload Interrupt Flag
+  * @retval None
+  */
+#define __HAL_LTDC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))
+
+/**
+  * @brief  Disables the specified LTDC interrupts.
+  * @param  __HANDLE__  LTDC handle
+  * @param __INTERRUPT__ Specify the LTDC interrupt sources to be disabled.
+  *          This parameter can be any combination of the following values:
+  *            @arg LTDC_IT_LI: Line Interrupt flag
+  *            @arg LTDC_IT_FU: FIFO Underrun Interrupt flag
+  *            @arg LTDC_IT_TE: Transfer Error interrupt flag
+  *            @arg LTDC_IT_RR: Register Reload Interrupt Flag
+  * @retval None
+  */
+#define __HAL_LTDC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= ~(__INTERRUPT__))
+
+/**
+  * @brief  Check whether the specified LTDC interrupt has occurred or not.
+  * @param  __HANDLE__  LTDC handle
+  * @param __INTERRUPT__ Specify the LTDC interrupt source to check.
+  *          This parameter can be one of the following values:
+  *            @arg LTDC_IT_LI: Line Interrupt flag
+  *            @arg LTDC_IT_FU: FIFO Underrun Interrupt flag
+  *            @arg LTDC_IT_TE: Transfer Error interrupt flag
+  *            @arg LTDC_IT_RR: Register Reload Interrupt Flag
+  * @retval The state of INTERRUPT (SET or RESET).
+  */
+#define __HAL_LTDC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER & (__INTERRUPT__))
+/**
+  * @}
+  */
+
+/* Include LTDC HAL Extension module */
+#include "stm32f4xx_hal_ltdc_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup LTDC_Exported_Functions
+  * @{
+  */
+/** @addtogroup LTDC_Exported_Functions_Group1
+  * @{
+  */
+/* Initialization and de-initialization functions *****************************/
+HAL_StatusTypeDef HAL_LTDC_Init(LTDC_HandleTypeDef *hltdc);
+HAL_StatusTypeDef HAL_LTDC_DeInit(LTDC_HandleTypeDef *hltdc);
+void HAL_LTDC_MspInit(LTDC_HandleTypeDef *hltdc);
+void HAL_LTDC_MspDeInit(LTDC_HandleTypeDef *hltdc);
+void HAL_LTDC_ErrorCallback(LTDC_HandleTypeDef *hltdc);
+void HAL_LTDC_LineEventCallback(LTDC_HandleTypeDef *hltdc);
+void HAL_LTDC_ReloadEventCallback(LTDC_HandleTypeDef *hltdc);
+
+/* Callbacks Register/UnRegister functions  ***********************************/
+#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1)
+HAL_StatusTypeDef HAL_LTDC_RegisterCallback(LTDC_HandleTypeDef *hltdc, HAL_LTDC_CallbackIDTypeDef CallbackID,
+                                            pLTDC_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_LTDC_UnRegisterCallback(LTDC_HandleTypeDef *hltdc, HAL_LTDC_CallbackIDTypeDef CallbackID);
+#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+
+/** @addtogroup LTDC_Exported_Functions_Group2
+  * @{
+  */
+/* IO operation functions *****************************************************/
+void  HAL_LTDC_IRQHandler(LTDC_HandleTypeDef *hltdc);
+/**
+  * @}
+  */
+
+/** @addtogroup LTDC_Exported_Functions_Group3
+  * @{
+  */
+/* Peripheral Control functions ***********************************************/
+HAL_StatusTypeDef HAL_LTDC_ConfigLayer(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg, uint32_t LayerIdx);
+HAL_StatusTypeDef HAL_LTDC_SetWindowSize(LTDC_HandleTypeDef *hltdc, uint32_t XSize, uint32_t YSize, uint32_t LayerIdx);
+HAL_StatusTypeDef HAL_LTDC_SetWindowPosition(LTDC_HandleTypeDef *hltdc, uint32_t X0, uint32_t Y0, uint32_t LayerIdx);
+HAL_StatusTypeDef HAL_LTDC_SetPixelFormat(LTDC_HandleTypeDef *hltdc, uint32_t Pixelformat, uint32_t LayerIdx);
+HAL_StatusTypeDef HAL_LTDC_SetAlpha(LTDC_HandleTypeDef *hltdc, uint32_t Alpha, uint32_t LayerIdx);
+HAL_StatusTypeDef HAL_LTDC_SetAddress(LTDC_HandleTypeDef *hltdc, uint32_t Address, uint32_t LayerIdx);
+HAL_StatusTypeDef HAL_LTDC_SetPitch(LTDC_HandleTypeDef *hltdc, uint32_t LinePitchInPixels, uint32_t LayerIdx);
+HAL_StatusTypeDef HAL_LTDC_ConfigColorKeying(LTDC_HandleTypeDef *hltdc, uint32_t RGBValue, uint32_t LayerIdx);
+HAL_StatusTypeDef HAL_LTDC_ConfigCLUT(LTDC_HandleTypeDef *hltdc, uint32_t *pCLUT, uint32_t CLUTSize, uint32_t LayerIdx);
+HAL_StatusTypeDef HAL_LTDC_EnableColorKeying(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx);
+HAL_StatusTypeDef HAL_LTDC_DisableColorKeying(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx);
+HAL_StatusTypeDef HAL_LTDC_EnableCLUT(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx);
+HAL_StatusTypeDef HAL_LTDC_DisableCLUT(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx);
+HAL_StatusTypeDef HAL_LTDC_ProgramLineEvent(LTDC_HandleTypeDef *hltdc, uint32_t Line);
+HAL_StatusTypeDef HAL_LTDC_EnableDither(LTDC_HandleTypeDef *hltdc);
+HAL_StatusTypeDef HAL_LTDC_DisableDither(LTDC_HandleTypeDef *hltdc);
+HAL_StatusTypeDef HAL_LTDC_Reload(LTDC_HandleTypeDef *hltdc, uint32_t ReloadType);
+HAL_StatusTypeDef HAL_LTDC_ConfigLayer_NoReload(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg,
+                                                uint32_t LayerIdx);
+HAL_StatusTypeDef HAL_LTDC_SetWindowSize_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t XSize, uint32_t YSize,
+                                                  uint32_t LayerIdx);
+HAL_StatusTypeDef HAL_LTDC_SetWindowPosition_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t X0, uint32_t Y0,
+                                                      uint32_t LayerIdx);
+HAL_StatusTypeDef HAL_LTDC_SetPixelFormat_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t Pixelformat, uint32_t LayerIdx);
+HAL_StatusTypeDef HAL_LTDC_SetAlpha_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t Alpha, uint32_t LayerIdx);
+HAL_StatusTypeDef HAL_LTDC_SetAddress_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t Address, uint32_t LayerIdx);
+HAL_StatusTypeDef HAL_LTDC_SetPitch_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LinePitchInPixels, uint32_t LayerIdx);
+HAL_StatusTypeDef HAL_LTDC_ConfigColorKeying_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t RGBValue, uint32_t LayerIdx);
+HAL_StatusTypeDef HAL_LTDC_EnableColorKeying_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx);
+HAL_StatusTypeDef HAL_LTDC_DisableColorKeying_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx);
+HAL_StatusTypeDef HAL_LTDC_EnableCLUT_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx);
+HAL_StatusTypeDef HAL_LTDC_DisableCLUT_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx);
+
+/**
+  * @}
+  */
+
+/** @addtogroup LTDC_Exported_Functions_Group4
+  * @{
+  */
+/* Peripheral State functions *************************************************/
+HAL_LTDC_StateTypeDef HAL_LTDC_GetState(LTDC_HandleTypeDef *hltdc);
+uint32_t              HAL_LTDC_GetError(LTDC_HandleTypeDef *hltdc);
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup LTDC_Private_Macros LTDC Private Macros
+  * @{
+  */
+#define LTDC_LAYER(__HANDLE__, __LAYER__)              ((LTDC_Layer_TypeDef *)((uint32_t)(\
+                                                                               ((uint32_t)((__HANDLE__)->Instance))\
+                                                                               + 0x84U + (0x80U*(__LAYER__)))))
+#define IS_LTDC_LAYER(__LAYER__)                       ((__LAYER__) < MAX_LAYER)
+#define IS_LTDC_HSPOL(__HSPOL__)                       (((__HSPOL__) == LTDC_HSPOLARITY_AL)\
+                                                        || ((__HSPOL__) == LTDC_HSPOLARITY_AH))
+#define IS_LTDC_VSPOL(__VSPOL__)                       (((__VSPOL__) == LTDC_VSPOLARITY_AL)\
+                                                        || ((__VSPOL__) == LTDC_VSPOLARITY_AH))
+#define IS_LTDC_DEPOL(__DEPOL__)                       (((__DEPOL__) == LTDC_DEPOLARITY_AL)\
+                                                        || ((__DEPOL__) ==  LTDC_DEPOLARITY_AH))
+#define IS_LTDC_PCPOL(__PCPOL__)                       (((__PCPOL__) == LTDC_PCPOLARITY_IPC)\
+                                                        || ((__PCPOL__) ==  LTDC_PCPOLARITY_IIPC))
+#define IS_LTDC_HSYNC(__HSYNC__)                       ((__HSYNC__)  <= LTDC_HORIZONTALSYNC)
+#define IS_LTDC_VSYNC(__VSYNC__)                       ((__VSYNC__)  <= LTDC_VERTICALSYNC)
+#define IS_LTDC_AHBP(__AHBP__)                         ((__AHBP__)   <= LTDC_HORIZONTALSYNC)
+#define IS_LTDC_AVBP(__AVBP__)                         ((__AVBP__)   <= LTDC_VERTICALSYNC)
+#define IS_LTDC_AAW(__AAW__)                           ((__AAW__)    <= LTDC_HORIZONTALSYNC)
+#define IS_LTDC_AAH(__AAH__)                           ((__AAH__)    <= LTDC_VERTICALSYNC)
+#define IS_LTDC_TOTALW(__TOTALW__)                     ((__TOTALW__) <= LTDC_HORIZONTALSYNC)
+#define IS_LTDC_TOTALH(__TOTALH__)                     ((__TOTALH__) <= LTDC_VERTICALSYNC)
+#define IS_LTDC_BLUEVALUE(__BBLUE__)                   ((__BBLUE__)  <= LTDC_COLOR)
+#define IS_LTDC_GREENVALUE(__BGREEN__)                 ((__BGREEN__) <= LTDC_COLOR)
+#define IS_LTDC_REDVALUE(__BRED__)                     ((__BRED__)   <= LTDC_COLOR)
+#define IS_LTDC_BLENDING_FACTOR1(__BLENDING_FACTOR1__) (((__BLENDING_FACTOR1__) == LTDC_BLENDING_FACTOR1_CA) || \
+                                                        ((__BLENDING_FACTOR1__) == LTDC_BLENDING_FACTOR1_PAxCA))
+#define IS_LTDC_BLENDING_FACTOR2(__BLENDING_FACTOR1__) (((__BLENDING_FACTOR1__) == LTDC_BLENDING_FACTOR2_CA) || \
+                                                        ((__BLENDING_FACTOR1__) == LTDC_BLENDING_FACTOR2_PAxCA))
+#define IS_LTDC_PIXEL_FORMAT(__PIXEL_FORMAT__)         (((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_ARGB8888) || \
+                                                        ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_RGB888)   || \
+                                                        ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_RGB565)   || \
+                                                        ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_ARGB1555) || \
+                                                        ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_ARGB4444) || \
+                                                        ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_L8)       || \
+                                                        ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_AL44)     || \
+                                                        ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_AL88))
+#define IS_LTDC_ALPHA(__ALPHA__)                       ((__ALPHA__) <= LTDC_ALPHA)
+#define IS_LTDC_HCONFIGST(__HCONFIGST__)               ((__HCONFIGST__) <= LTDC_STARTPOSITION)
+#define IS_LTDC_HCONFIGSP(__HCONFIGSP__)               ((__HCONFIGSP__) <= LTDC_STOPPOSITION)
+#define IS_LTDC_VCONFIGST(__VCONFIGST__)               ((__VCONFIGST__) <= LTDC_STARTPOSITION)
+#define IS_LTDC_VCONFIGSP(__VCONFIGSP__)               ((__VCONFIGSP__) <= LTDC_STOPPOSITION)
+#define IS_LTDC_CFBP(__CFBP__)                         ((__CFBP__) <= LTDC_COLOR_FRAME_BUFFER)
+#define IS_LTDC_CFBLL(__CFBLL__)                       ((__CFBLL__) <= LTDC_COLOR_FRAME_BUFFER)
+#define IS_LTDC_CFBLNBR(__CFBLNBR__)                   ((__CFBLNBR__) <= LTDC_LINE_NUMBER)
+#define IS_LTDC_LIPOS(__LIPOS__)                       ((__LIPOS__) <= 0x7FFU)
+#define IS_LTDC_RELOAD(__RELOADTYPE__)                 (((__RELOADTYPE__) == LTDC_RELOAD_IMMEDIATE) || \
+                                                        ((__RELOADTYPE__) == LTDC_RELOAD_VERTICAL_BLANKING))
+/**
+  * @}
+  */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup LTDC_Private_Functions LTDC Private Functions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* LTDC */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32F4xx_HAL_LTDC_H */
+
diff --git a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_ltdc_ex.h b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_ltdc_ex.h
new file mode 100644
index 0000000..77d3814
--- /dev/null
+++ b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_ltdc_ex.h
@@ -0,0 +1,83 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hal_ltdc_ex.h
+  * @author  MCD Application Team
+  * @brief   Header file of LTDC HAL Extension module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2016 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32F4xx_HAL_LTDC_EX_H
+#define STM32F4xx_HAL_LTDC_EX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+#if defined (LTDC) && defined (DSI)
+
+#include "stm32f4xx_hal_dsi.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup LTDCEx
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup LTDCEx_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup LTDCEx_Exported_Functions_Group1
+  * @{
+  */
+HAL_StatusTypeDef HAL_LTDCEx_StructInitFromVideoConfig(LTDC_HandleTypeDef *hltdc, DSI_VidCfgTypeDef *VidCfg);
+HAL_StatusTypeDef HAL_LTDCEx_StructInitFromAdaptedCommandConfig(LTDC_HandleTypeDef *hltdc, DSI_CmdCfgTypeDef *CmdCfg);
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* LTDC && DSI */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32F4xx_HAL_LTDC_EX_H */
diff --git a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h
new file mode 100644
index 0000000..ab0412d
--- /dev/null
+++ b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h
@@ -0,0 +1,427 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hal_pwr.h
+  * @author  MCD Application Team
+  * @brief   Header file of PWR HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file in
+  * the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  ******************************************************************************
+  */ 
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_PWR_H
+#define __STM32F4xx_HAL_PWR_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup PWR
+  * @{
+  */ 
+
+/* Exported types ------------------------------------------------------------*/
+
+/** @defgroup PWR_Exported_Types PWR Exported Types
+  * @{
+  */
+   
+/**
+  * @brief  PWR PVD configuration structure definition
+  */
+typedef struct
+{
+  uint32_t PVDLevel;   /*!< PVDLevel: Specifies the PVD detection level.
+                            This parameter can be a value of @ref PWR_PVD_detection_level */
+
+  uint32_t Mode;      /*!< Mode: Specifies the operating mode for the selected pins.
+                           This parameter can be a value of @ref PWR_PVD_Mode */
+}PWR_PVDTypeDef;
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup PWR_Exported_Constants PWR Exported Constants
+  * @{
+  */
+  
+/** @defgroup PWR_WakeUp_Pins PWR WakeUp Pins
+  * @{
+  */
+#define PWR_WAKEUP_PIN1                 0x00000100U
+/**
+  * @}
+  */
+
+/** @defgroup PWR_PVD_detection_level PWR PVD detection level
+  * @{
+  */ 
+#define PWR_PVDLEVEL_0                  PWR_CR_PLS_LEV0
+#define PWR_PVDLEVEL_1                  PWR_CR_PLS_LEV1
+#define PWR_PVDLEVEL_2                  PWR_CR_PLS_LEV2
+#define PWR_PVDLEVEL_3                  PWR_CR_PLS_LEV3
+#define PWR_PVDLEVEL_4                  PWR_CR_PLS_LEV4
+#define PWR_PVDLEVEL_5                  PWR_CR_PLS_LEV5
+#define PWR_PVDLEVEL_6                  PWR_CR_PLS_LEV6
+#define PWR_PVDLEVEL_7                  PWR_CR_PLS_LEV7/* External input analog voltage 
+                                                          (Compare internally to VREFINT) */
+/**
+  * @}
+  */   
+ 
+/** @defgroup PWR_PVD_Mode PWR PVD Mode
+  * @{
+  */
+#define PWR_PVD_MODE_NORMAL                 0x00000000U   /*!< basic mode is used */
+#define PWR_PVD_MODE_IT_RISING              0x00010001U   /*!< External Interrupt Mode with Rising edge trigger detection */
+#define PWR_PVD_MODE_IT_FALLING             0x00010002U   /*!< External Interrupt Mode with Falling edge trigger detection */
+#define PWR_PVD_MODE_IT_RISING_FALLING      0x00010003U   /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
+#define PWR_PVD_MODE_EVENT_RISING           0x00020001U   /*!< Event Mode with Rising edge trigger detection */
+#define PWR_PVD_MODE_EVENT_FALLING          0x00020002U   /*!< Event Mode with Falling edge trigger detection */
+#define PWR_PVD_MODE_EVENT_RISING_FALLING   0x00020003U   /*!< Event Mode with Rising/Falling edge trigger detection */
+/**
+  * @}
+  */
+
+
+/** @defgroup PWR_Regulator_state_in_STOP_mode PWR Regulator state in SLEEP/STOP mode
+  * @{
+  */
+#define PWR_MAINREGULATOR_ON                        0x00000000U
+#define PWR_LOWPOWERREGULATOR_ON                    PWR_CR_LPDS
+/**
+  * @}
+  */
+    
+/** @defgroup PWR_SLEEP_mode_entry PWR SLEEP mode entry
+  * @{
+  */
+#define PWR_SLEEPENTRY_WFI              ((uint8_t)0x01)
+#define PWR_SLEEPENTRY_WFE              ((uint8_t)0x02)
+/**
+  * @}
+  */
+
+/** @defgroup PWR_STOP_mode_entry PWR STOP mode entry
+  * @{
+  */
+#define PWR_STOPENTRY_WFI               ((uint8_t)0x01)
+#define PWR_STOPENTRY_WFE               ((uint8_t)0x02)
+/**
+  * @}
+  */
+
+/** @defgroup PWR_Flag PWR Flag
+  * @{
+  */
+#define PWR_FLAG_WU                     PWR_CSR_WUF
+#define PWR_FLAG_SB                     PWR_CSR_SBF
+#define PWR_FLAG_PVDO                   PWR_CSR_PVDO
+#define PWR_FLAG_BRR                    PWR_CSR_BRR
+#define PWR_FLAG_VOSRDY                 PWR_CSR_VOSRDY
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */ 
+  
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup PWR_Exported_Macro PWR Exported Macro
+  * @{
+  */
+
+/** @brief  Check PWR flag is set or not.
+  * @param  __FLAG__ specifies the flag to check.
+  *           This parameter can be one of the following values:
+  *            @arg PWR_FLAG_WU: Wake Up flag. This flag indicates that a wakeup event 
+  *                  was received from the WKUP pin or from the RTC alarm (Alarm A 
+  *                  or Alarm B), RTC Tamper event, RTC TimeStamp event or RTC Wakeup.
+  *                  An additional wakeup event is detected if the WKUP pin is enabled 
+  *                  (by setting the EWUP bit) when the WKUP pin level is already high.  
+  *            @arg PWR_FLAG_SB: StandBy flag. This flag indicates that the system was
+  *                  resumed from StandBy mode.    
+  *            @arg PWR_FLAG_PVDO: PVD Output. This flag is valid only if PVD is enabled 
+  *                  by the HAL_PWR_EnablePVD() function. The PVD is stopped by Standby mode 
+  *                  For this reason, this bit is equal to 0 after Standby or reset
+  *                  until the PVDE bit is set.
+  *            @arg PWR_FLAG_BRR: Backup regulator ready flag. This bit is not reset 
+  *                  when the device wakes up from Standby mode or by a system reset 
+  *                  or power reset.  
+  *            @arg PWR_FLAG_VOSRDY: This flag indicates that the Regulator voltage 
+  *                 scaling output selection is ready.
+  * @retval The new state of __FLAG__ (TRUE or FALSE).
+  */
+#define __HAL_PWR_GET_FLAG(__FLAG__) ((PWR->CSR & (__FLAG__)) == (__FLAG__))
+
+/** @brief  Clear the PWR's pending flags.
+  * @param  __FLAG__ specifies the flag to clear.
+  *          This parameter can be one of the following values:
+  *            @arg PWR_FLAG_WU: Wake Up flag
+  *            @arg PWR_FLAG_SB: StandBy flag
+  */
+#define __HAL_PWR_CLEAR_FLAG(__FLAG__) (PWR->CR |=  (__FLAG__) << 2U)
+
+/**
+  * @brief Enable the PVD Exti Line 16.
+  * @retval None.
+  */
+#define __HAL_PWR_PVD_EXTI_ENABLE_IT()   (EXTI->IMR |= (PWR_EXTI_LINE_PVD))
+
+/**
+  * @brief Disable the PVD EXTI Line 16.
+  * @retval None.
+  */
+#define __HAL_PWR_PVD_EXTI_DISABLE_IT()  (EXTI->IMR &= ~(PWR_EXTI_LINE_PVD))
+
+/**
+  * @brief Enable event on PVD Exti Line 16.
+  * @retval None.
+  */
+#define __HAL_PWR_PVD_EXTI_ENABLE_EVENT()   (EXTI->EMR |= (PWR_EXTI_LINE_PVD))
+
+/**
+  * @brief Disable event on PVD Exti Line 16.
+  * @retval None.
+  */
+#define __HAL_PWR_PVD_EXTI_DISABLE_EVENT()  (EXTI->EMR &= ~(PWR_EXTI_LINE_PVD))
+
+/**
+  * @brief Enable the PVD Extended Interrupt Rising Trigger.
+  * @retval None.
+  */
+#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE()   SET_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD)
+
+/**
+  * @brief Disable the PVD Extended Interrupt Rising Trigger.
+  * @retval None.
+  */
+#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE()  CLEAR_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD)
+
+/**
+  * @brief Enable the PVD Extended Interrupt Falling Trigger.
+  * @retval None.
+  */
+#define __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE()   SET_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD)
+
+
+/**
+  * @brief Disable the PVD Extended Interrupt Falling Trigger.
+  * @retval None.
+  */
+#define __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE()  CLEAR_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD)
+
+
+/**
+  * @brief  PVD EXTI line configuration: set rising & falling edge trigger.
+  * @retval None.
+  */
+#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE()   do{__HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();\
+                                                             __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();\
+                                                            }while(0U)
+
+/**
+  * @brief Disable the PVD Extended Interrupt Rising & Falling Trigger.
+  * This parameter can be:
+  * @retval None.
+  */
+#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE()  do{__HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();\
+                                                             __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE();\
+                                                            }while(0U) 
+
+/**
+  * @brief checks whether the specified PVD Exti interrupt flag is set or not.
+  * @retval EXTI PVD Line Status.
+  */
+#define __HAL_PWR_PVD_EXTI_GET_FLAG()  (EXTI->PR & (PWR_EXTI_LINE_PVD))
+
+/**
+  * @brief Clear the PVD Exti flag.
+  * @retval None.
+  */
+#define __HAL_PWR_PVD_EXTI_CLEAR_FLAG()  (EXTI->PR = (PWR_EXTI_LINE_PVD))
+
+/**
+  * @brief  Generates a Software interrupt on PVD EXTI line.
+  * @retval None
+  */
+#define __HAL_PWR_PVD_EXTI_GENERATE_SWIT() (EXTI->SWIER |= (PWR_EXTI_LINE_PVD))
+
+/**
+  * @}
+  */
+
+/* Include PWR HAL Extension module */
+#include "stm32f4xx_hal_pwr_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup PWR_Exported_Functions PWR Exported Functions
+  * @{
+  */
+  
+/** @addtogroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions 
+  * @{
+  */
+/* Initialization and de-initialization functions *****************************/
+void HAL_PWR_DeInit(void);
+void HAL_PWR_EnableBkUpAccess(void);
+void HAL_PWR_DisableBkUpAccess(void);
+/**
+  * @}
+  */
+
+/** @addtogroup PWR_Exported_Functions_Group2 Peripheral Control functions 
+  * @{
+  */
+/* Peripheral Control functions  **********************************************/
+/* PVD configuration */
+void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD);
+void HAL_PWR_EnablePVD(void);
+void HAL_PWR_DisablePVD(void);
+
+/* WakeUp pins configuration */
+void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx);
+void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx);
+
+/* Low Power modes entry */
+void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry);
+void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry);
+void HAL_PWR_EnterSTANDBYMode(void);
+
+/* Power PVD IRQ Handler */
+void HAL_PWR_PVD_IRQHandler(void);
+void HAL_PWR_PVDCallback(void);
+
+/* Cortex System Control functions  *******************************************/
+void HAL_PWR_EnableSleepOnExit(void);
+void HAL_PWR_DisableSleepOnExit(void);
+void HAL_PWR_EnableSEVOnPend(void);
+void HAL_PWR_DisableSEVOnPend(void);
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup PWR_Private_Constants PWR Private Constants
+  * @{
+  */
+
+/** @defgroup PWR_PVD_EXTI_Line PWR PVD EXTI Line
+  * @{
+  */
+#define PWR_EXTI_LINE_PVD  ((uint32_t)EXTI_IMR_MR16)  /*!< External interrupt line 16 Connected to the PVD EXTI Line */
+/**
+  * @}
+  */
+
+/** @defgroup PWR_register_alias_address PWR Register alias address
+  * @{
+  */
+/* ------------- PWR registers bit address in the alias region ---------------*/
+#define PWR_OFFSET               (PWR_BASE - PERIPH_BASE)
+#define PWR_CR_OFFSET            0x00U
+#define PWR_CSR_OFFSET           0x04U
+#define PWR_CR_OFFSET_BB         (PWR_OFFSET + PWR_CR_OFFSET)
+#define PWR_CSR_OFFSET_BB        (PWR_OFFSET + PWR_CSR_OFFSET)
+/**
+  * @}
+  */
+
+/** @defgroup PWR_CR_register_alias PWR CR Register alias address
+  * @{
+  */
+/* --- CR Register ---*/
+/* Alias word address of DBP bit */
+#define DBP_BIT_NUMBER   PWR_CR_DBP_Pos
+#define CR_DBP_BB        (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (DBP_BIT_NUMBER * 4U))
+
+/* Alias word address of PVDE bit */
+#define PVDE_BIT_NUMBER  PWR_CR_PVDE_Pos
+#define CR_PVDE_BB       (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (PVDE_BIT_NUMBER * 4U))
+
+/* Alias word address of VOS bit */
+#define VOS_BIT_NUMBER  PWR_CR_VOS_Pos
+#define CR_VOS_BB      (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (VOS_BIT_NUMBER * 4U))
+/**
+  * @}
+  */
+
+/** @defgroup PWR_CSR_register_alias PWR CSR Register alias address
+  * @{
+  */
+/* --- CSR Register ---*/
+/* Alias word address of EWUP bit */
+#define EWUP_BIT_NUMBER  PWR_CSR_EWUP_Pos
+#define CSR_EWUP_BB      (PERIPH_BB_BASE + (PWR_CSR_OFFSET_BB * 32U) + (EWUP_BIT_NUMBER * 4U))
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup PWR_Private_Macros PWR Private Macros
+  * @{
+  */
+
+/** @defgroup PWR_IS_PWR_Definitions PWR Private macros to check input parameters
+  * @{
+  */
+#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLEVEL_0) || ((LEVEL) == PWR_PVDLEVEL_1)|| \
+                                 ((LEVEL) == PWR_PVDLEVEL_2) || ((LEVEL) == PWR_PVDLEVEL_3)|| \
+                                 ((LEVEL) == PWR_PVDLEVEL_4) || ((LEVEL) == PWR_PVDLEVEL_5)|| \
+                                 ((LEVEL) == PWR_PVDLEVEL_6) || ((LEVEL) == PWR_PVDLEVEL_7))
+#define IS_PWR_PVD_MODE(MODE) (((MODE) == PWR_PVD_MODE_IT_RISING)|| ((MODE) == PWR_PVD_MODE_IT_FALLING) || \
+                              ((MODE) == PWR_PVD_MODE_IT_RISING_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING) || \
+                              ((MODE) == PWR_PVD_MODE_EVENT_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING) || \
+                              ((MODE) == PWR_PVD_MODE_NORMAL))
+#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_ON) || \
+                                     ((REGULATOR) == PWR_LOWPOWERREGULATOR_ON))
+#define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE))
+#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE))
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */
+  
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* __STM32F4xx_HAL_PWR_H */
diff --git a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h
new file mode 100644
index 0000000..7b632a5
--- /dev/null
+++ b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h
@@ -0,0 +1,340 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hal_pwr_ex.h
+  * @author  MCD Application Team
+  * @brief   Header file of PWR HAL Extension module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file in
+  * the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  ******************************************************************************
+  */ 
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_PWR_EX_H
+#define __STM32F4xx_HAL_PWR_EX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup PWREx
+  * @{
+  */ 
+
+/* Exported types ------------------------------------------------------------*/ 
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup PWREx_Exported_Constants PWREx Exported Constants
+  * @{
+  */
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
+    defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
+   
+/** @defgroup PWREx_Regulator_state_in_UnderDrive_mode PWREx Regulator state in UnderDrive mode
+  * @{
+  */
+#define PWR_MAINREGULATOR_UNDERDRIVE_ON                       PWR_CR_MRUDS
+#define PWR_LOWPOWERREGULATOR_UNDERDRIVE_ON                   ((uint32_t)(PWR_CR_LPDS | PWR_CR_LPUDS))
+/**
+  * @}
+  */ 
+  
+/** @defgroup PWREx_Over_Under_Drive_Flag PWREx Over Under Drive Flag
+  * @{
+  */
+#define PWR_FLAG_ODRDY                  PWR_CSR_ODRDY
+#define PWR_FLAG_ODSWRDY                PWR_CSR_ODSWRDY
+#define PWR_FLAG_UDRDY                  PWR_CSR_UDSWRDY
+/**
+  * @}
+  */
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
+
+/** @defgroup PWREx_Regulator_Voltage_Scale PWREx Regulator Voltage Scale
+  * @{
+  */
+#if defined(STM32F405xx) || defined(STM32F407xx) || defined(STM32F415xx) || defined(STM32F417xx)   
+#define PWR_REGULATOR_VOLTAGE_SCALE1         PWR_CR_VOS             /* Scale 1 mode(default value at reset): the maximum value of fHCLK = 168 MHz. */
+#define PWR_REGULATOR_VOLTAGE_SCALE2         0x00000000U            /* Scale 2 mode: the maximum value of fHCLK = 144 MHz. */
+#else
+#define PWR_REGULATOR_VOLTAGE_SCALE1         PWR_CR_VOS             /* Scale 1 mode(default value at reset): the maximum value of fHCLK is 168 MHz. It can be extended to
+                                                                       180 MHz by activating the over-drive mode. */
+#define PWR_REGULATOR_VOLTAGE_SCALE2         PWR_CR_VOS_1           /* Scale 2 mode: the maximum value of fHCLK is 144 MHz. It can be extended to
+                                                                       168 MHz by activating the over-drive mode. */
+#define PWR_REGULATOR_VOLTAGE_SCALE3         PWR_CR_VOS_0           /* Scale 3 mode: the maximum value of fHCLK is 120 MHz. */
+#endif /* STM32F405xx || STM32F407xx || STM32F415xx || STM32F417xx */ 
+/**
+  * @}
+  */
+#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F446xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
+    defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
+/** @defgroup PWREx_WakeUp_Pins PWREx WakeUp Pins
+  * @{
+  */
+#define PWR_WAKEUP_PIN2                 0x00000080U
+#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
+    defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) 
+#define PWR_WAKEUP_PIN3                 0x00000040U
+#endif /* STM32F410xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Zx || STM32F412Vx || \
+          STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */
+/**
+  * @}
+  */   
+#endif /* STM32F410xx || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx ||
+          STM32F413xx || STM32F423xx */
+
+/**
+  * @}
+  */ 
+  
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup PWREx_Exported_Constants PWREx Exported Constants
+  *  @{
+  */
+
+#if defined(STM32F405xx) || defined(STM32F407xx) || defined(STM32F415xx) || defined(STM32F417xx)
+/** @brief  macros configure the main internal regulator output voltage.
+  * @param  __REGULATOR__ specifies the regulator output voltage to achieve
+  *         a tradeoff between performance and power consumption when the device does
+  *         not operate at the maximum frequency (refer to the datasheets for more details).
+  *          This parameter can be one of the following values:
+  *            @arg PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output Scale 1 mode
+  *            @arg PWR_REGULATOR_VOLTAGE_SCALE2: Regulator voltage output Scale 2 mode
+  * @retval None
+  */
+#define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__) do {                                                     \
+                                                            __IO uint32_t tmpreg = 0x00U;                        \
+                                                            MODIFY_REG(PWR->CR, PWR_CR_VOS, (__REGULATOR__));   \
+                                                            /* Delay after an RCC peripheral clock enabling */  \
+                                                            tmpreg = READ_BIT(PWR->CR, PWR_CR_VOS);             \
+                                                            UNUSED(tmpreg);                                     \
+                                                          } while(0U)
+#else
+/** @brief  macros configure the main internal regulator output voltage.
+  * @param  __REGULATOR__ specifies the regulator output voltage to achieve
+  *         a tradeoff between performance and power consumption when the device does
+  *         not operate at the maximum frequency (refer to the datasheets for more details).
+  *          This parameter can be one of the following values:
+  *            @arg PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output Scale 1 mode
+  *            @arg PWR_REGULATOR_VOLTAGE_SCALE2: Regulator voltage output Scale 2 mode
+  *            @arg PWR_REGULATOR_VOLTAGE_SCALE3: Regulator voltage output Scale 3 mode
+  * @retval None
+  */
+#define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__) do {                                                     \
+                                                            __IO uint32_t tmpreg = 0x00U;                        \
+                                                            MODIFY_REG(PWR->CR, PWR_CR_VOS, (__REGULATOR__));   \
+                                                            /* Delay after an RCC peripheral clock enabling */  \
+                                                            tmpreg = READ_BIT(PWR->CR, PWR_CR_VOS);             \
+                                                            UNUSED(tmpreg);                                     \
+                                                          } while(0U)
+#endif /* STM32F405xx || STM32F407xx || STM32F415xx || STM32F417xx */ 
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
+    defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
+/** @brief Macros to enable or disable the Over drive mode.
+  * @note  These macros can be used only for STM32F42xx/STM3243xx devices.
+  */
+#define __HAL_PWR_OVERDRIVE_ENABLE() (*(__IO uint32_t *) CR_ODEN_BB = ENABLE)
+#define __HAL_PWR_OVERDRIVE_DISABLE() (*(__IO uint32_t *) CR_ODEN_BB = DISABLE)
+
+/** @brief Macros to enable or disable the Over drive switching.
+  * @note  These macros can be used only for STM32F42xx/STM3243xx devices. 
+  */
+#define __HAL_PWR_OVERDRIVESWITCHING_ENABLE() (*(__IO uint32_t *) CR_ODSWEN_BB = ENABLE)
+#define __HAL_PWR_OVERDRIVESWITCHING_DISABLE() (*(__IO uint32_t *) CR_ODSWEN_BB = DISABLE)
+
+/** @brief Macros to enable or disable the Under drive mode.
+  * @note  This mode is enabled only with STOP low power mode.
+  *        In this mode, the 1.2V domain is preserved in reduced leakage mode. This 
+  *        mode is only available when the main regulator or the low power regulator 
+  *        is in low voltage mode.      
+  * @note  If the Under-drive mode was enabled, it is automatically disabled after 
+  *        exiting Stop mode. 
+  *        When the voltage regulator operates in Under-drive mode, an additional  
+  *        startup delay is induced when waking up from Stop mode.
+  */
+#define __HAL_PWR_UNDERDRIVE_ENABLE() (PWR->CR |= (uint32_t)PWR_CR_UDEN)
+#define __HAL_PWR_UNDERDRIVE_DISABLE() (PWR->CR &= (uint32_t)(~PWR_CR_UDEN))
+
+/** @brief  Check PWR flag is set or not.
+  * @note   These macros can be used only for STM32F42xx/STM3243xx devices.
+  * @param  __FLAG__ specifies the flag to check.
+  *         This parameter can be one of the following values:
+  *            @arg PWR_FLAG_ODRDY: This flag indicates that the Over-drive mode
+  *                                 is ready 
+  *            @arg PWR_FLAG_ODSWRDY: This flag indicates that the Over-drive mode
+  *                                   switching is ready  
+  *            @arg PWR_FLAG_UDRDY: This flag indicates that the Under-drive mode
+  *                                 is enabled in Stop mode
+  * @retval The new state of __FLAG__ (TRUE or FALSE).
+  */
+#define __HAL_PWR_GET_ODRUDR_FLAG(__FLAG__) ((PWR->CSR & (__FLAG__)) == (__FLAG__))
+
+/** @brief Clear the Under-Drive Ready flag.
+  * @note  These macros can be used only for STM32F42xx/STM3243xx devices.
+  */
+#define __HAL_PWR_CLEAR_ODRUDR_FLAG() (PWR->CSR |= PWR_FLAG_UDRDY)
+
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup PWREx_Exported_Functions PWREx Exported Functions
+  *  @{
+  */
+ 
+/** @addtogroup PWREx_Exported_Functions_Group1
+  * @{
+  */
+void HAL_PWREx_EnableFlashPowerDown(void);
+void HAL_PWREx_DisableFlashPowerDown(void); 
+HAL_StatusTypeDef HAL_PWREx_EnableBkUpReg(void);
+HAL_StatusTypeDef HAL_PWREx_DisableBkUpReg(void); 
+uint32_t HAL_PWREx_GetVoltageRange(void);
+HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling);
+
+#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F401xC) ||\
+    defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F412Zx) || defined(STM32F412Vx) ||\
+    defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
+void HAL_PWREx_EnableMainRegulatorLowVoltage(void);
+void HAL_PWREx_DisableMainRegulatorLowVoltage(void);
+void HAL_PWREx_EnableLowRegulatorLowVoltage(void);
+void HAL_PWREx_DisableLowRegulatorLowVoltage(void);
+#endif /* STM32F410xx || STM32F401xC || STM32F401xE || STM32F411xE || STM32F412Zx || STM32F412Vx ||\
+          STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx) ||\
+    defined(STM32F469xx) || defined(STM32F479xx)
+HAL_StatusTypeDef HAL_PWREx_EnableOverDrive(void);
+HAL_StatusTypeDef HAL_PWREx_DisableOverDrive(void);
+HAL_StatusTypeDef HAL_PWREx_EnterUnderDriveSTOPMode(uint32_t Regulator, uint8_t STOPEntry);
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup PWREx_Private_Constants PWREx Private Constants
+  * @{
+  */
+
+/** @defgroup PWREx_register_alias_address PWREx Register alias address
+  * @{
+  */
+/* ------------- PWR registers bit address in the alias region ---------------*/
+/* --- CR Register ---*/
+/* Alias word address of FPDS bit */
+#define FPDS_BIT_NUMBER          PWR_CR_FPDS_Pos
+#define CR_FPDS_BB               (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (FPDS_BIT_NUMBER * 4U))
+
+/* Alias word address of ODEN bit   */
+#define ODEN_BIT_NUMBER          PWR_CR_ODEN_Pos
+#define CR_ODEN_BB               (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (ODEN_BIT_NUMBER * 4U))
+
+/* Alias word address of ODSWEN bit */
+#define ODSWEN_BIT_NUMBER        PWR_CR_ODSWEN_Pos
+#define CR_ODSWEN_BB             (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (ODSWEN_BIT_NUMBER * 4U))
+    
+/* Alias word address of MRLVDS bit */
+#define MRLVDS_BIT_NUMBER        PWR_CR_MRLVDS_Pos
+#define CR_MRLVDS_BB             (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (MRLVDS_BIT_NUMBER * 4U))
+
+/* Alias word address of LPLVDS bit */
+#define LPLVDS_BIT_NUMBER        PWR_CR_LPLVDS_Pos
+#define CR_LPLVDS_BB             (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (LPLVDS_BIT_NUMBER * 4U))
+
+ /**
+  * @}
+  */
+
+/** @defgroup PWREx_CSR_register_alias PWRx CSR Register alias address
+  * @{
+  */  
+/* --- CSR Register ---*/
+/* Alias word address of BRE bit */
+#define BRE_BIT_NUMBER   PWR_CSR_BRE_Pos
+#define CSR_BRE_BB      (uint32_t)(PERIPH_BB_BASE + (PWR_CSR_OFFSET_BB * 32U) + (BRE_BIT_NUMBER * 4U))
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup PWREx_Private_Macros PWREx Private Macros
+  * @{
+  */
+
+/** @defgroup PWREx_IS_PWR_Definitions PWREx Private macros to check input parameters
+  * @{
+  */
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
+    defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
+#define IS_PWR_REGULATOR_UNDERDRIVE(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_UNDERDRIVE_ON) || \
+                                                ((REGULATOR) == PWR_LOWPOWERREGULATOR_UNDERDRIVE_ON))
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
+
+#if defined(STM32F405xx) || defined(STM32F407xx) || defined(STM32F415xx) || defined(STM32F417xx)
+#define IS_PWR_VOLTAGE_SCALING_RANGE(VOLTAGE) (((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE1) || \
+                                               ((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE2))
+#else
+#define IS_PWR_VOLTAGE_SCALING_RANGE(VOLTAGE) (((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE1) || \
+                                               ((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE2) || \
+                                               ((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE3))
+#endif /* STM32F405xx || STM32F407xx || STM32F415xx || STM32F417xx */ 
+
+#if defined(STM32F446xx)
+#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) || ((PIN) == PWR_WAKEUP_PIN2))
+#elif defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F412Zx) ||\
+      defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) ||\
+      defined(STM32F423xx)
+#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) || ((PIN) == PWR_WAKEUP_PIN2) || \
+                                ((PIN) == PWR_WAKEUP_PIN3))
+#else
+#define IS_PWR_WAKEUP_PIN(PIN) ((PIN) == PWR_WAKEUP_PIN1)
+#endif /* STM32F446xx */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */
+  
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* __STM32F4xx_HAL_PWR_EX_H */
diff --git a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_qspi.h b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_qspi.h
new file mode 100644
index 0000000..e4a99a4
--- /dev/null
+++ b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_qspi.h
@@ -0,0 +1,750 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hal_qspi.h
+  * @author  MCD Application Team
+  * @brief   Header file of QSPI HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2016 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32F4xx_HAL_QSPI_H
+#define STM32F4xx_HAL_QSPI_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+#if defined(QUADSPI)
+
+/** @addtogroup STM32F4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup QSPI
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup QSPI_Exported_Types QSPI Exported Types
+  * @{
+  */
+
+/**
+  * @brief  QSPI Init structure definition
+  */
+typedef struct
+{
+  uint32_t ClockPrescaler;     /* Specifies the prescaler factor for generating clock based on the AHB clock.
+                                  This parameter can be a number between 0 and 255 */
+  uint32_t FifoThreshold;      /* Specifies the threshold number of bytes in the FIFO (used only in indirect mode)
+                                  This parameter can be a value between 1 and 32 */
+  uint32_t SampleShifting;     /* Specifies the Sample Shift. The data is sampled 1/2 clock cycle delay later to
+                                  take in account external signal delays. (It should be QSPI_SAMPLE_SHIFTING_NONE in DDR mode)
+                                  This parameter can be a value of @ref QSPI_SampleShifting */
+  uint32_t FlashSize;          /* Specifies the Flash Size. FlashSize+1 is effectively the number of address bits
+                                  required to address the flash memory. The flash capacity can be up to 4GB
+                                  (addressed using 32 bits) in indirect mode, but the addressable space in
+                                  memory-mapped mode is limited to 256MB
+                                  This parameter can be a number between 0 and 31 */
+  uint32_t ChipSelectHighTime; /* Specifies the Chip Select High Time. ChipSelectHighTime+1 defines the minimum number
+                                  of clock cycles which the chip select must remain high between commands.
+                                  This parameter can be a value of @ref QSPI_ChipSelectHighTime */
+  uint32_t ClockMode;          /* Specifies the Clock Mode. It indicates the level that clock takes between commands.
+                                  This parameter can be a value of @ref QSPI_ClockMode */
+  uint32_t FlashID;            /* Specifies the Flash which will be used,
+                                  This parameter can be a value of @ref QSPI_Flash_Select */
+  uint32_t DualFlash;          /* Specifies the Dual Flash Mode State
+                                  This parameter can be a value of @ref QSPI_DualFlash_Mode */
+}QSPI_InitTypeDef;
+
+/**
+  * @brief HAL QSPI State structures definition
+  */
+typedef enum
+{
+  HAL_QSPI_STATE_RESET             = 0x00U,    /*!< Peripheral not initialized                            */
+  HAL_QSPI_STATE_READY             = 0x01U,    /*!< Peripheral initialized and ready for use              */
+  HAL_QSPI_STATE_BUSY              = 0x02U,    /*!< Peripheral in indirect mode and busy                  */
+  HAL_QSPI_STATE_BUSY_INDIRECT_TX  = 0x12U,    /*!< Peripheral in indirect mode with transmission ongoing */
+  HAL_QSPI_STATE_BUSY_INDIRECT_RX  = 0x22U,    /*!< Peripheral in indirect mode with reception ongoing    */
+  HAL_QSPI_STATE_BUSY_AUTO_POLLING = 0x42U,    /*!< Peripheral in auto polling mode ongoing               */
+  HAL_QSPI_STATE_BUSY_MEM_MAPPED   = 0x82U,    /*!< Peripheral in memory mapped mode ongoing              */
+  HAL_QSPI_STATE_ABORT             = 0x08U,    /*!< Peripheral with abort request ongoing                 */
+  HAL_QSPI_STATE_ERROR             = 0x04U     /*!< Peripheral in error                                   */
+}HAL_QSPI_StateTypeDef;
+
+/**
+  * @brief  QSPI Handle Structure definition
+  */
+#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
+typedef struct __QSPI_HandleTypeDef
+#else
+typedef struct
+#endif
+{
+  QUADSPI_TypeDef            *Instance;        /* QSPI registers base address        */
+  QSPI_InitTypeDef           Init;             /* QSPI communication parameters      */
+  uint8_t                    *pTxBuffPtr;      /* Pointer to QSPI Tx transfer Buffer */
+  __IO uint32_t              TxXferSize;       /* QSPI Tx Transfer size              */
+  __IO uint32_t              TxXferCount;      /* QSPI Tx Transfer Counter           */
+  uint8_t                    *pRxBuffPtr;      /* Pointer to QSPI Rx transfer Buffer */
+  __IO uint32_t              RxXferSize;       /* QSPI Rx Transfer size              */
+  __IO uint32_t              RxXferCount;      /* QSPI Rx Transfer Counter           */
+  DMA_HandleTypeDef          *hdma;            /* QSPI Rx/Tx DMA Handle parameters   */
+  __IO HAL_LockTypeDef       Lock;             /* Locking object                     */
+  __IO HAL_QSPI_StateTypeDef State;            /* QSPI communication state           */
+  __IO uint32_t              ErrorCode;        /* QSPI Error code                    */
+  uint32_t                   Timeout;          /* Timeout for the QSPI memory access */
+#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
+  void (* ErrorCallback)        (struct __QSPI_HandleTypeDef *hqspi);
+  void (* AbortCpltCallback)    (struct __QSPI_HandleTypeDef *hqspi);
+  void (* FifoThresholdCallback)(struct __QSPI_HandleTypeDef *hqspi);
+  void (* CmdCpltCallback)      (struct __QSPI_HandleTypeDef *hqspi);
+  void (* RxCpltCallback)       (struct __QSPI_HandleTypeDef *hqspi);
+  void (* TxCpltCallback)       (struct __QSPI_HandleTypeDef *hqspi);
+  void (* RxHalfCpltCallback)   (struct __QSPI_HandleTypeDef *hqspi);
+  void (* TxHalfCpltCallback)   (struct __QSPI_HandleTypeDef *hqspi);
+  void (* StatusMatchCallback)  (struct __QSPI_HandleTypeDef *hqspi);
+  void (* TimeOutCallback)      (struct __QSPI_HandleTypeDef *hqspi);
+
+  void (* MspInitCallback)      (struct __QSPI_HandleTypeDef *hqspi);
+  void (* MspDeInitCallback)    (struct __QSPI_HandleTypeDef *hqspi);
+#endif
+}QSPI_HandleTypeDef;
+
+/**
+  * @brief  QSPI Command structure definition
+  */
+typedef struct
+{
+  uint32_t Instruction;        /* Specifies the Instruction to be sent
+                                  This parameter can be a value (8-bit) between 0x00 and 0xFF */
+  uint32_t Address;            /* Specifies the Address to be sent (Size from 1 to 4 bytes according AddressSize)
+                                  This parameter can be a value (32-bits) between 0x0 and 0xFFFFFFFF */
+  uint32_t AlternateBytes;     /* Specifies the Alternate Bytes to be sent (Size from 1 to 4 bytes according AlternateBytesSize)
+                                  This parameter can be a value (32-bits) between 0x0 and 0xFFFFFFFF */
+  uint32_t AddressSize;        /* Specifies the Address Size
+                                  This parameter can be a value of @ref QSPI_AddressSize */
+  uint32_t AlternateBytesSize; /* Specifies the Alternate Bytes Size
+                                  This parameter can be a value of @ref QSPI_AlternateBytesSize */
+  uint32_t DummyCycles;        /* Specifies the Number of Dummy Cycles.
+                                  This parameter can be a number between 0 and 31 */
+  uint32_t InstructionMode;    /* Specifies the Instruction Mode
+                                  This parameter can be a value of @ref QSPI_InstructionMode */
+  uint32_t AddressMode;        /* Specifies the Address Mode
+                                  This parameter can be a value of @ref QSPI_AddressMode */
+  uint32_t AlternateByteMode;  /* Specifies the Alternate Bytes Mode
+                                  This parameter can be a value of @ref QSPI_AlternateBytesMode */
+  uint32_t DataMode;           /* Specifies the Data Mode (used for dummy cycles and data phases)
+                                  This parameter can be a value of @ref QSPI_DataMode */
+  uint32_t NbData;             /* Specifies the number of data to transfer. (This is the number of bytes)
+                                  This parameter can be any value between 0 and 0xFFFFFFFF (0 means undefined length
+                                  until end of memory)*/
+  uint32_t DdrMode;            /* Specifies the double data rate mode for address, alternate byte and data phase
+                                  This parameter can be a value of @ref QSPI_DdrMode */
+  uint32_t DdrHoldHalfCycle;   /* Specifies if the DDR hold is enabled. When enabled it delays the data
+                                  output by one half of system clock in DDR mode.
+                                  This parameter can be a value of @ref QSPI_DdrHoldHalfCycle */
+  uint32_t SIOOMode;           /* Specifies the send instruction only once mode
+                                  This parameter can be a value of @ref QSPI_SIOOMode */
+}QSPI_CommandTypeDef;
+
+/**
+  * @brief  QSPI Auto Polling mode configuration structure definition
+  */
+typedef struct
+{
+  uint32_t Match;              /* Specifies the value to be compared with the masked status register to get a match.
+                                  This parameter can be any value between 0 and 0xFFFFFFFF */
+  uint32_t Mask;               /* Specifies the mask to be applied to the status bytes received.
+                                  This parameter can be any value between 0 and 0xFFFFFFFF */
+  uint32_t Interval;           /* Specifies the number of clock cycles between two read during automatic polling phases.
+                                  This parameter can be any value between 0 and 0xFFFF */
+  uint32_t StatusBytesSize;    /* Specifies the size of the status bytes received.
+                                  This parameter can be any value between 1 and 4 */
+  uint32_t MatchMode;          /* Specifies the method used for determining a match.
+                                  This parameter can be a value of @ref QSPI_MatchMode */
+  uint32_t AutomaticStop;      /* Specifies if automatic polling is stopped after a match.
+                                  This parameter can be a value of @ref QSPI_AutomaticStop */
+}QSPI_AutoPollingTypeDef;
+
+/**
+  * @brief  QSPI Memory Mapped mode configuration structure definition
+  */
+typedef struct
+{
+  uint32_t TimeOutPeriod;      /* Specifies the number of clock to wait when the FIFO is full before to release the chip select.
+                                  This parameter can be any value between 0 and 0xFFFF */
+  uint32_t TimeOutActivation;  /* Specifies if the timeout counter is enabled to release the chip select.
+                                  This parameter can be a value of @ref QSPI_TimeOutActivation */
+}QSPI_MemoryMappedTypeDef;
+
+#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
+/**
+  * @brief  HAL QSPI Callback ID enumeration definition
+  */
+typedef enum
+{
+  HAL_QSPI_ERROR_CB_ID          = 0x00U,  /*!< QSPI Error Callback ID            */
+  HAL_QSPI_ABORT_CB_ID          = 0x01U,  /*!< QSPI Abort Callback ID            */
+  HAL_QSPI_FIFO_THRESHOLD_CB_ID = 0x02U,  /*!< QSPI FIFO Threshold Callback ID   */
+  HAL_QSPI_CMD_CPLT_CB_ID       = 0x03U,  /*!< QSPI Command Complete Callback ID */
+  HAL_QSPI_RX_CPLT_CB_ID        = 0x04U,  /*!< QSPI Rx Complete Callback ID      */
+  HAL_QSPI_TX_CPLT_CB_ID        = 0x05U,  /*!< QSPI Tx Complete Callback ID      */
+  HAL_QSPI_RX_HALF_CPLT_CB_ID   = 0x06U,  /*!< QSPI Rx Half Complete Callback ID */
+  HAL_QSPI_TX_HALF_CPLT_CB_ID   = 0x07U,  /*!< QSPI Tx Half Complete Callback ID */
+  HAL_QSPI_STATUS_MATCH_CB_ID   = 0x08U,  /*!< QSPI Status Match Callback ID     */
+  HAL_QSPI_TIMEOUT_CB_ID        = 0x09U,  /*!< QSPI Timeout Callback ID          */
+
+  HAL_QSPI_MSP_INIT_CB_ID       = 0x0AU,  /*!< QSPI MspInit Callback ID          */
+  HAL_QSPI_MSP_DEINIT_CB_ID     = 0x0B0   /*!< QSPI MspDeInit Callback ID        */
+}HAL_QSPI_CallbackIDTypeDef;
+
+/**
+  * @brief  HAL QSPI Callback pointer definition
+  */
+typedef void (*pQSPI_CallbackTypeDef)(QSPI_HandleTypeDef *hqspi);
+#endif
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup QSPI_Exported_Constants QSPI Exported Constants
+  * @{
+  */
+
+/** @defgroup QSPI_ErrorCode QSPI Error Code
+  * @{
+  */
+#define HAL_QSPI_ERROR_NONE             0x00000000U /*!< No error                 */
+#define HAL_QSPI_ERROR_TIMEOUT          0x00000001U /*!< Timeout error            */
+#define HAL_QSPI_ERROR_TRANSFER         0x00000002U /*!< Transfer error           */
+#define HAL_QSPI_ERROR_DMA              0x00000004U /*!< DMA transfer error       */
+#define HAL_QSPI_ERROR_INVALID_PARAM    0x00000008U /*!< Invalid parameters error */
+#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
+#define HAL_QSPI_ERROR_INVALID_CALLBACK 0x00000010U /*!< Invalid callback error   */
+#endif
+/**
+  * @}
+  */
+
+/** @defgroup QSPI_SampleShifting QSPI Sample Shifting
+  * @{
+  */
+#define QSPI_SAMPLE_SHIFTING_NONE      0x00000000U                   /*!<No clock cycle shift to sample data*/
+#define QSPI_SAMPLE_SHIFTING_HALFCYCLE ((uint32_t)QUADSPI_CR_SSHIFT) /*!<1/2 clock cycle shift to sample data*/
+/**
+  * @}
+  */
+
+/** @defgroup QSPI_ChipSelectHighTime QSPI ChipSelect High Time
+  * @{
+  */
+#define QSPI_CS_HIGH_TIME_1_CYCLE      0x00000000U                                         /*!<nCS stay high for at least 1 clock cycle between commands*/
+#define QSPI_CS_HIGH_TIME_2_CYCLE      ((uint32_t)QUADSPI_DCR_CSHT_0)                      /*!<nCS stay high for at least 2 clock cycles between commands*/
+#define QSPI_CS_HIGH_TIME_3_CYCLE      ((uint32_t)QUADSPI_DCR_CSHT_1)                      /*!<nCS stay high for at least 3 clock cycles between commands*/
+#define QSPI_CS_HIGH_TIME_4_CYCLE      ((uint32_t)QUADSPI_DCR_CSHT_0 | QUADSPI_DCR_CSHT_1) /*!<nCS stay high for at least 4 clock cycles between commands*/
+#define QSPI_CS_HIGH_TIME_5_CYCLE      ((uint32_t)QUADSPI_DCR_CSHT_2)                      /*!<nCS stay high for at least 5 clock cycles between commands*/
+#define QSPI_CS_HIGH_TIME_6_CYCLE      ((uint32_t)QUADSPI_DCR_CSHT_2 | QUADSPI_DCR_CSHT_0) /*!<nCS stay high for at least 6 clock cycles between commands*/
+#define QSPI_CS_HIGH_TIME_7_CYCLE      ((uint32_t)QUADSPI_DCR_CSHT_2 | QUADSPI_DCR_CSHT_1) /*!<nCS stay high for at least 7 clock cycles between commands*/
+#define QSPI_CS_HIGH_TIME_8_CYCLE      ((uint32_t)QUADSPI_DCR_CSHT)                        /*!<nCS stay high for at least 8 clock cycles between commands*/
+/**
+  * @}
+  */
+
+/** @defgroup QSPI_ClockMode QSPI Clock Mode
+  * @{
+  */
+#define QSPI_CLOCK_MODE_0              0x00000000U                    /*!<Clk stays low while nCS is released*/
+#define QSPI_CLOCK_MODE_3              ((uint32_t)QUADSPI_DCR_CKMODE) /*!<Clk goes high while nCS is released*/
+/**
+  * @}
+  */
+
+/** @defgroup QSPI_Flash_Select QSPI Flash Select
+  * @{
+  */
+#define QSPI_FLASH_ID_1                0x00000000U                 /*!<FLASH 1 selected*/
+#define QSPI_FLASH_ID_2                ((uint32_t)QUADSPI_CR_FSEL) /*!<FLASH 2 selected*/
+/**
+  * @}
+  */
+
+  /** @defgroup QSPI_DualFlash_Mode QSPI Dual Flash Mode
+  * @{
+  */
+#define QSPI_DUALFLASH_ENABLE          ((uint32_t)QUADSPI_CR_DFM) /*!<Dual-flash mode enabled*/
+#define QSPI_DUALFLASH_DISABLE         0x00000000U                /*!<Dual-flash mode disabled*/
+/**
+  * @}
+  */
+
+/** @defgroup QSPI_AddressSize QSPI Address Size
+  * @{
+  */
+#define QSPI_ADDRESS_8_BITS            0x00000000U                      /*!<8-bit address*/
+#define QSPI_ADDRESS_16_BITS           ((uint32_t)QUADSPI_CCR_ADSIZE_0) /*!<16-bit address*/
+#define QSPI_ADDRESS_24_BITS           ((uint32_t)QUADSPI_CCR_ADSIZE_1) /*!<24-bit address*/
+#define QSPI_ADDRESS_32_BITS           ((uint32_t)QUADSPI_CCR_ADSIZE)   /*!<32-bit address*/
+/**
+  * @}
+  */
+
+/** @defgroup QSPI_AlternateBytesSize QSPI Alternate Bytes Size
+  * @{
+  */
+#define QSPI_ALTERNATE_BYTES_8_BITS    0x00000000U                      /*!<8-bit alternate bytes*/
+#define QSPI_ALTERNATE_BYTES_16_BITS   ((uint32_t)QUADSPI_CCR_ABSIZE_0) /*!<16-bit alternate bytes*/
+#define QSPI_ALTERNATE_BYTES_24_BITS   ((uint32_t)QUADSPI_CCR_ABSIZE_1) /*!<24-bit alternate bytes*/
+#define QSPI_ALTERNATE_BYTES_32_BITS   ((uint32_t)QUADSPI_CCR_ABSIZE)   /*!<32-bit alternate bytes*/
+/**
+  * @}
+  */
+
+/** @defgroup QSPI_InstructionMode QSPI Instruction Mode
+* @{
+*/
+#define QSPI_INSTRUCTION_NONE          0x00000000U                     /*!<No instruction*/
+#define QSPI_INSTRUCTION_1_LINE        ((uint32_t)QUADSPI_CCR_IMODE_0) /*!<Instruction on a single line*/
+#define QSPI_INSTRUCTION_2_LINES       ((uint32_t)QUADSPI_CCR_IMODE_1) /*!<Instruction on two lines*/
+#define QSPI_INSTRUCTION_4_LINES       ((uint32_t)QUADSPI_CCR_IMODE)   /*!<Instruction on four lines*/
+/**
+  * @}
+  */
+
+/** @defgroup QSPI_AddressMode QSPI Address Mode
+* @{
+*/
+#define QSPI_ADDRESS_NONE              0x00000000U                      /*!<No address*/
+#define QSPI_ADDRESS_1_LINE            ((uint32_t)QUADSPI_CCR_ADMODE_0) /*!<Address on a single line*/
+#define QSPI_ADDRESS_2_LINES           ((uint32_t)QUADSPI_CCR_ADMODE_1) /*!<Address on two lines*/
+#define QSPI_ADDRESS_4_LINES           ((uint32_t)QUADSPI_CCR_ADMODE)   /*!<Address on four lines*/
+/**
+  * @}
+  */
+
+/** @defgroup QSPI_AlternateBytesMode QSPI Alternate Bytes Mode
+* @{
+*/
+#define QSPI_ALTERNATE_BYTES_NONE      0x00000000U                      /*!<No alternate bytes*/
+#define QSPI_ALTERNATE_BYTES_1_LINE    ((uint32_t)QUADSPI_CCR_ABMODE_0) /*!<Alternate bytes on a single line*/
+#define QSPI_ALTERNATE_BYTES_2_LINES   ((uint32_t)QUADSPI_CCR_ABMODE_1) /*!<Alternate bytes on two lines*/
+#define QSPI_ALTERNATE_BYTES_4_LINES   ((uint32_t)QUADSPI_CCR_ABMODE)   /*!<Alternate bytes on four lines*/
+/**
+  * @}
+  */
+
+/** @defgroup QSPI_DataMode QSPI Data Mode
+  * @{
+  */
+#define QSPI_DATA_NONE                 0x00000000U                     /*!<No data*/
+#define QSPI_DATA_1_LINE               ((uint32_t)QUADSPI_CCR_DMODE_0) /*!<Data on a single line*/
+#define QSPI_DATA_2_LINES              ((uint32_t)QUADSPI_CCR_DMODE_1) /*!<Data on two lines*/
+#define QSPI_DATA_4_LINES              ((uint32_t)QUADSPI_CCR_DMODE)   /*!<Data on four lines*/
+/**
+  * @}
+  */
+
+/** @defgroup QSPI_DdrMode QSPI DDR Mode
+  * @{
+  */
+#define QSPI_DDR_MODE_DISABLE          0x00000000U                  /*!<Double data rate mode disabled*/
+#define QSPI_DDR_MODE_ENABLE           ((uint32_t)QUADSPI_CCR_DDRM) /*!<Double data rate mode enabled*/
+/**
+  * @}
+  */
+
+/** @defgroup QSPI_DdrHoldHalfCycle QSPI DDR Data Output Delay
+  * @{
+  */
+#define QSPI_DDR_HHC_ANALOG_DELAY      0x00000000U                  /*!<Delay the data output using analog delay in DDR mode*/
+#define QSPI_DDR_HHC_HALF_CLK_DELAY    ((uint32_t)QUADSPI_CCR_DHHC) /*!<Delay the data output by one half of system clock in DDR mode*/
+/**
+  * @}
+  */
+
+/** @defgroup QSPI_SIOOMode QSPI Send Instruction Mode
+  * @{
+  */
+#define QSPI_SIOO_INST_EVERY_CMD       0x00000000U                  /*!<Send instruction on every transaction*/
+#define QSPI_SIOO_INST_ONLY_FIRST_CMD  ((uint32_t)QUADSPI_CCR_SIOO) /*!<Send instruction only for the first command*/
+/**
+  * @}
+  */
+
+/** @defgroup QSPI_MatchMode QSPI Match Mode
+  * @{
+  */
+#define QSPI_MATCH_MODE_AND            0x00000000U                /*!<AND match mode between unmasked bits*/
+#define QSPI_MATCH_MODE_OR             ((uint32_t)QUADSPI_CR_PMM) /*!<OR match mode between unmasked bits*/
+/**
+  * @}
+  */
+
+/** @defgroup QSPI_AutomaticStop QSPI Automatic Stop
+  * @{
+  */
+#define QSPI_AUTOMATIC_STOP_DISABLE    0x00000000U                 /*!<AutoPolling stops only with abort or QSPI disabling*/
+#define QSPI_AUTOMATIC_STOP_ENABLE     ((uint32_t)QUADSPI_CR_APMS) /*!<AutoPolling stops as soon as there is a match*/
+/**
+  * @}
+  */
+
+/** @defgroup QSPI_TimeOutActivation QSPI Timeout Activation
+  * @{
+  */
+#define QSPI_TIMEOUT_COUNTER_DISABLE   0x00000000U                 /*!<Timeout counter disabled, nCS remains active*/
+#define QSPI_TIMEOUT_COUNTER_ENABLE    ((uint32_t)QUADSPI_CR_TCEN) /*!<Timeout counter enabled, nCS released when timeout expires*/
+/**
+  * @}
+  */
+
+/** @defgroup QSPI_Flags QSPI Flags
+  * @{
+  */
+#define QSPI_FLAG_BUSY                 QUADSPI_SR_BUSY /*!<Busy flag: operation is ongoing*/
+#define QSPI_FLAG_TO                   QUADSPI_SR_TOF  /*!<Timeout flag: timeout occurs in memory-mapped mode*/
+#define QSPI_FLAG_SM                   QUADSPI_SR_SMF  /*!<Status match flag: received data matches in autopolling mode*/
+#define QSPI_FLAG_FT                   QUADSPI_SR_FTF  /*!<Fifo threshold flag: Fifo threshold reached or data left after read from memory is complete*/
+#define QSPI_FLAG_TC                   QUADSPI_SR_TCF  /*!<Transfer complete flag: programmed number of data have been transferred or the transfer has been aborted*/
+#define QSPI_FLAG_TE                   QUADSPI_SR_TEF  /*!<Transfer error flag: invalid address is being accessed*/
+/**
+  * @}
+  */
+
+/** @defgroup QSPI_Interrupts QSPI Interrupts
+  * @{
+  */
+#define QSPI_IT_TO                     QUADSPI_CR_TOIE /*!<Interrupt on the timeout flag*/
+#define QSPI_IT_SM                     QUADSPI_CR_SMIE /*!<Interrupt on the status match flag*/
+#define QSPI_IT_FT                     QUADSPI_CR_FTIE /*!<Interrupt on the fifo threshold flag*/
+#define QSPI_IT_TC                     QUADSPI_CR_TCIE /*!<Interrupt on the transfer complete flag*/
+#define QSPI_IT_TE                     QUADSPI_CR_TEIE /*!<Interrupt on the transfer error flag*/
+/**
+  * @}
+  */
+
+/** @defgroup QSPI_Timeout_definition QSPI Timeout definition
+  * @brief QSPI Timeout definition
+  * @{
+  */
+#define HAL_QSPI_TIMEOUT_DEFAULT_VALUE 5000U /* 5 s */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup QSPI_Exported_Macros QSPI Exported Macros
+  * @{
+  */
+/** @brief Reset QSPI handle state.
+  * @param  __HANDLE__ QSPI handle.
+  * @retval None
+  */
+#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
+#define __HAL_QSPI_RESET_HANDLE_STATE(__HANDLE__)           do {                                              \
+                                                                  (__HANDLE__)->State = HAL_QSPI_STATE_RESET; \
+                                                                  (__HANDLE__)->MspInitCallback = NULL;       \
+                                                                  (__HANDLE__)->MspDeInitCallback = NULL;     \
+                                                               } while(0)
+#else
+#define __HAL_QSPI_RESET_HANDLE_STATE(__HANDLE__)           ((__HANDLE__)->State = HAL_QSPI_STATE_RESET)
+#endif
+
+/** @brief  Enable the QSPI peripheral.
+  * @param  __HANDLE__ specifies the QSPI Handle.
+  * @retval None
+  */
+#define __HAL_QSPI_ENABLE(__HANDLE__)                       SET_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN)
+
+/** @brief  Disable the QSPI peripheral.
+  * @param  __HANDLE__ specifies the QSPI Handle.
+  * @retval None
+  */
+#define __HAL_QSPI_DISABLE(__HANDLE__)                      CLEAR_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN)
+
+/** @brief  Enable the specified QSPI interrupt.
+  * @param  __HANDLE__ specifies the QSPI Handle.
+  * @param  __INTERRUPT__ specifies the QSPI interrupt source to enable.
+  *          This parameter can be one of the following values:
+  *            @arg QSPI_IT_TO: QSPI Timeout interrupt
+  *            @arg QSPI_IT_SM: QSPI Status match interrupt
+  *            @arg QSPI_IT_FT: QSPI FIFO threshold interrupt
+  *            @arg QSPI_IT_TC: QSPI Transfer complete interrupt
+  *            @arg QSPI_IT_TE: QSPI Transfer error interrupt
+  * @retval None
+  */
+#define __HAL_QSPI_ENABLE_IT(__HANDLE__, __INTERRUPT__)     SET_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__))
+
+
+/** @brief  Disable the specified QSPI interrupt.
+  * @param  __HANDLE__ specifies the QSPI Handle.
+  * @param  __INTERRUPT__ specifies the QSPI interrupt source to disable.
+  *          This parameter can be one of the following values:
+  *            @arg QSPI_IT_TO: QSPI Timeout interrupt
+  *            @arg QSPI_IT_SM: QSPI Status match interrupt
+  *            @arg QSPI_IT_FT: QSPI FIFO threshold interrupt
+  *            @arg QSPI_IT_TC: QSPI Transfer complete interrupt
+  *            @arg QSPI_IT_TE: QSPI Transfer error interrupt
+  * @retval None
+  */
+#define __HAL_QSPI_DISABLE_IT(__HANDLE__, __INTERRUPT__)    CLEAR_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__))
+
+/** @brief  Check whether the specified QSPI interrupt source is enabled or not.
+  * @param  __HANDLE__ specifies the QSPI Handle.
+  * @param  __INTERRUPT__ specifies the QSPI interrupt source to check.
+  *          This parameter can be one of the following values:
+  *            @arg QSPI_IT_TO: QSPI Timeout interrupt
+  *            @arg QSPI_IT_SM: QSPI Status match interrupt
+  *            @arg QSPI_IT_FT: QSPI FIFO threshold interrupt
+  *            @arg QSPI_IT_TC: QSPI Transfer complete interrupt
+  *            @arg QSPI_IT_TE: QSPI Transfer error interrupt
+  * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
+  */
+#define __HAL_QSPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (READ_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) == (__INTERRUPT__))
+
+/**
+  * @brief  Check whether the selected QSPI flag is set or not.
+  * @param  __HANDLE__ specifies the QSPI Handle.
+  * @param  __FLAG__ specifies the QSPI flag to check.
+  *          This parameter can be one of the following values:
+  *            @arg QSPI_FLAG_BUSY: QSPI Busy flag
+  *            @arg QSPI_FLAG_TO:   QSPI Timeout flag
+  *            @arg QSPI_FLAG_SM:   QSPI Status match flag
+  *            @arg QSPI_FLAG_FT:   QSPI FIFO threshold flag
+  *            @arg QSPI_FLAG_TC:   QSPI Transfer complete flag
+  *            @arg QSPI_FLAG_TE:   QSPI Transfer error flag
+  * @retval None
+  */
+#define __HAL_QSPI_GET_FLAG(__HANDLE__, __FLAG__)           ((READ_BIT((__HANDLE__)->Instance->SR, (__FLAG__)) != 0U) ? SET : RESET)
+
+/** @brief  Clears the specified QSPI's flag status.
+  * @param  __HANDLE__ specifies the QSPI Handle.
+  * @param  __FLAG__ specifies the QSPI clear register flag that needs to be set
+  *          This parameter can be one of the following values:
+  *            @arg QSPI_FLAG_TO: QSPI Timeout flag
+  *            @arg QSPI_FLAG_SM: QSPI Status match flag
+  *            @arg QSPI_FLAG_TC: QSPI Transfer complete flag
+  *            @arg QSPI_FLAG_TE: QSPI Transfer error flag
+  * @retval None
+  */
+#define __HAL_QSPI_CLEAR_FLAG(__HANDLE__, __FLAG__)         WRITE_REG((__HANDLE__)->Instance->FCR, (__FLAG__))
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup QSPI_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup QSPI_Exported_Functions_Group1
+  * @{
+  */
+/* Initialization/de-initialization functions  ********************************/
+HAL_StatusTypeDef     HAL_QSPI_Init     (QSPI_HandleTypeDef *hqspi);
+HAL_StatusTypeDef     HAL_QSPI_DeInit   (QSPI_HandleTypeDef *hqspi);
+void                  HAL_QSPI_MspInit  (QSPI_HandleTypeDef *hqspi);
+void                  HAL_QSPI_MspDeInit(QSPI_HandleTypeDef *hqspi);
+/**
+  * @}
+  */
+
+/** @addtogroup QSPI_Exported_Functions_Group2
+  * @{
+  */
+/* IO operation functions *****************************************************/
+/* QSPI IRQ handler method */
+void                  HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi);
+
+/* QSPI indirect mode */
+HAL_StatusTypeDef     HAL_QSPI_Command      (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t Timeout);
+HAL_StatusTypeDef     HAL_QSPI_Transmit     (QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout);
+HAL_StatusTypeDef     HAL_QSPI_Receive      (QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout);
+HAL_StatusTypeDef     HAL_QSPI_Command_IT   (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd);
+HAL_StatusTypeDef     HAL_QSPI_Transmit_IT  (QSPI_HandleTypeDef *hqspi, uint8_t *pData);
+HAL_StatusTypeDef     HAL_QSPI_Receive_IT   (QSPI_HandleTypeDef *hqspi, uint8_t *pData);
+HAL_StatusTypeDef     HAL_QSPI_Transmit_DMA (QSPI_HandleTypeDef *hqspi, uint8_t *pData);
+HAL_StatusTypeDef     HAL_QSPI_Receive_DMA  (QSPI_HandleTypeDef *hqspi, uint8_t *pData);
+
+/* QSPI status flag polling mode */
+HAL_StatusTypeDef     HAL_QSPI_AutoPolling   (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg, uint32_t Timeout);
+HAL_StatusTypeDef     HAL_QSPI_AutoPolling_IT(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg);
+
+/* QSPI memory-mapped mode */
+HAL_StatusTypeDef     HAL_QSPI_MemoryMapped(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_MemoryMappedTypeDef *cfg);
+
+/* Callback functions in non-blocking modes ***********************************/
+void                  HAL_QSPI_ErrorCallback        (QSPI_HandleTypeDef *hqspi);
+void                  HAL_QSPI_AbortCpltCallback    (QSPI_HandleTypeDef *hqspi);
+void                  HAL_QSPI_FifoThresholdCallback(QSPI_HandleTypeDef *hqspi);
+
+/* QSPI indirect mode */
+void                  HAL_QSPI_CmdCpltCallback      (QSPI_HandleTypeDef *hqspi);
+void                  HAL_QSPI_RxCpltCallback       (QSPI_HandleTypeDef *hqspi);
+void                  HAL_QSPI_TxCpltCallback       (QSPI_HandleTypeDef *hqspi);
+void                  HAL_QSPI_RxHalfCpltCallback   (QSPI_HandleTypeDef *hqspi);
+void                  HAL_QSPI_TxHalfCpltCallback   (QSPI_HandleTypeDef *hqspi);
+
+/* QSPI status flag polling mode */
+void                  HAL_QSPI_StatusMatchCallback  (QSPI_HandleTypeDef *hqspi);
+
+/* QSPI memory-mapped mode */
+void                  HAL_QSPI_TimeOutCallback      (QSPI_HandleTypeDef *hqspi);
+
+#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
+/* QSPI callback registering/unregistering */
+HAL_StatusTypeDef     HAL_QSPI_RegisterCallback     (QSPI_HandleTypeDef *hqspi, HAL_QSPI_CallbackIDTypeDef CallbackId, pQSPI_CallbackTypeDef pCallback);
+HAL_StatusTypeDef     HAL_QSPI_UnRegisterCallback   (QSPI_HandleTypeDef *hqspi, HAL_QSPI_CallbackIDTypeDef CallbackId);
+#endif
+/**
+  * @}
+  */
+
+/** @addtogroup QSPI_Exported_Functions_Group3
+  * @{
+  */
+/* Peripheral Control and State functions  ************************************/
+HAL_QSPI_StateTypeDef HAL_QSPI_GetState        (QSPI_HandleTypeDef *hqspi);
+uint32_t              HAL_QSPI_GetError        (QSPI_HandleTypeDef *hqspi);
+HAL_StatusTypeDef     HAL_QSPI_Abort           (QSPI_HandleTypeDef *hqspi);
+HAL_StatusTypeDef     HAL_QSPI_Abort_IT        (QSPI_HandleTypeDef *hqspi);
+void                  HAL_QSPI_SetTimeout      (QSPI_HandleTypeDef *hqspi, uint32_t Timeout);
+HAL_StatusTypeDef     HAL_QSPI_SetFifoThreshold(QSPI_HandleTypeDef *hqspi, uint32_t Threshold);
+uint32_t              HAL_QSPI_GetFifoThreshold(QSPI_HandleTypeDef *hqspi);
+HAL_StatusTypeDef     HAL_QSPI_SetFlashID      (QSPI_HandleTypeDef *hqspi, uint32_t FlashID);
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+/* End of exported functions -------------------------------------------------*/
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup QSPI_Private_Macros QSPI Private Macros
+  * @{
+  */
+#define IS_QSPI_CLOCK_PRESCALER(PRESCALER) ((PRESCALER) <= 0xFFU)
+
+#define IS_QSPI_FIFO_THRESHOLD(THR)        (((THR) > 0U) && ((THR) <= 32U))
+
+#define IS_QSPI_SSHIFT(SSHIFT)             (((SSHIFT) == QSPI_SAMPLE_SHIFTING_NONE) || \
+                                            ((SSHIFT) == QSPI_SAMPLE_SHIFTING_HALFCYCLE))
+
+#define IS_QSPI_FLASH_SIZE(FSIZE)          (((FSIZE) <= 31U))
+
+#define IS_QSPI_CS_HIGH_TIME(CSHTIME)      (((CSHTIME) == QSPI_CS_HIGH_TIME_1_CYCLE) || \
+                                            ((CSHTIME) == QSPI_CS_HIGH_TIME_2_CYCLE) || \
+                                            ((CSHTIME) == QSPI_CS_HIGH_TIME_3_CYCLE) || \
+                                            ((CSHTIME) == QSPI_CS_HIGH_TIME_4_CYCLE) || \
+                                            ((CSHTIME) == QSPI_CS_HIGH_TIME_5_CYCLE) || \
+                                            ((CSHTIME) == QSPI_CS_HIGH_TIME_6_CYCLE) || \
+                                            ((CSHTIME) == QSPI_CS_HIGH_TIME_7_CYCLE) || \
+                                            ((CSHTIME) == QSPI_CS_HIGH_TIME_8_CYCLE))
+
+#define IS_QSPI_CLOCK_MODE(CLKMODE)        (((CLKMODE) == QSPI_CLOCK_MODE_0) || \
+                                            ((CLKMODE) == QSPI_CLOCK_MODE_3))
+
+#define IS_QSPI_FLASH_ID(FLASH_ID)         (((FLASH_ID) == QSPI_FLASH_ID_1) || \
+                                            ((FLASH_ID) == QSPI_FLASH_ID_2))
+
+#define IS_QSPI_DUAL_FLASH_MODE(MODE)      (((MODE) == QSPI_DUALFLASH_ENABLE) || \
+                                            ((MODE) == QSPI_DUALFLASH_DISABLE))
+
+#define IS_QSPI_INSTRUCTION(INSTRUCTION)   ((INSTRUCTION) <= 0xFFU)
+
+#define IS_QSPI_ADDRESS_SIZE(ADDR_SIZE)    (((ADDR_SIZE) == QSPI_ADDRESS_8_BITS)  || \
+                                            ((ADDR_SIZE) == QSPI_ADDRESS_16_BITS) || \
+                                            ((ADDR_SIZE) == QSPI_ADDRESS_24_BITS) || \
+                                            ((ADDR_SIZE) == QSPI_ADDRESS_32_BITS))
+
+#define IS_QSPI_ALTERNATE_BYTES_SIZE(SIZE) (((SIZE) == QSPI_ALTERNATE_BYTES_8_BITS)  || \
+                                            ((SIZE) == QSPI_ALTERNATE_BYTES_16_BITS) || \
+                                            ((SIZE) == QSPI_ALTERNATE_BYTES_24_BITS) || \
+                                            ((SIZE) == QSPI_ALTERNATE_BYTES_32_BITS))
+
+#define IS_QSPI_DUMMY_CYCLES(DCY)          ((DCY) <= 31U)
+
+#define IS_QSPI_INSTRUCTION_MODE(MODE)     (((MODE) == QSPI_INSTRUCTION_NONE)    || \
+                                            ((MODE) == QSPI_INSTRUCTION_1_LINE)  || \
+                                            ((MODE) == QSPI_INSTRUCTION_2_LINES) || \
+                                            ((MODE) == QSPI_INSTRUCTION_4_LINES))
+
+#define IS_QSPI_ADDRESS_MODE(MODE)         (((MODE) == QSPI_ADDRESS_NONE)    || \
+                                            ((MODE) == QSPI_ADDRESS_1_LINE)  || \
+                                            ((MODE) == QSPI_ADDRESS_2_LINES) || \
+                                            ((MODE) == QSPI_ADDRESS_4_LINES))
+
+#define IS_QSPI_ALTERNATE_BYTES_MODE(MODE) (((MODE) == QSPI_ALTERNATE_BYTES_NONE)    || \
+                                            ((MODE) == QSPI_ALTERNATE_BYTES_1_LINE)  || \
+                                            ((MODE) == QSPI_ALTERNATE_BYTES_2_LINES) || \
+                                            ((MODE) == QSPI_ALTERNATE_BYTES_4_LINES))
+
+#define IS_QSPI_DATA_MODE(MODE)            (((MODE) == QSPI_DATA_NONE)    || \
+                                            ((MODE) == QSPI_DATA_1_LINE)  || \
+                                            ((MODE) == QSPI_DATA_2_LINES) || \
+                                            ((MODE) == QSPI_DATA_4_LINES))
+
+#define IS_QSPI_DDR_MODE(DDR_MODE)         (((DDR_MODE) == QSPI_DDR_MODE_DISABLE) || \
+                                            ((DDR_MODE) == QSPI_DDR_MODE_ENABLE))
+
+#define IS_QSPI_DDR_HHC(DDR_HHC)           (((DDR_HHC) == QSPI_DDR_HHC_ANALOG_DELAY) || \
+                                            ((DDR_HHC) == QSPI_DDR_HHC_HALF_CLK_DELAY))
+
+#define IS_QSPI_SIOO_MODE(SIOO_MODE)       (((SIOO_MODE) == QSPI_SIOO_INST_EVERY_CMD) || \
+                                            ((SIOO_MODE) == QSPI_SIOO_INST_ONLY_FIRST_CMD))
+
+#define IS_QSPI_INTERVAL(INTERVAL)         ((INTERVAL) <= QUADSPI_PIR_INTERVAL)
+
+#define IS_QSPI_STATUS_BYTES_SIZE(SIZE)    (((SIZE) >= 1U) && ((SIZE) <= 4U))
+
+#define IS_QSPI_MATCH_MODE(MODE)           (((MODE) == QSPI_MATCH_MODE_AND) || \
+                                            ((MODE) == QSPI_MATCH_MODE_OR))
+
+#define IS_QSPI_AUTOMATIC_STOP(APMS)       (((APMS) == QSPI_AUTOMATIC_STOP_DISABLE) || \
+                                            ((APMS) == QSPI_AUTOMATIC_STOP_ENABLE))
+
+#define IS_QSPI_TIMEOUT_ACTIVATION(TCEN)   (((TCEN) == QSPI_TIMEOUT_COUNTER_DISABLE) || \
+                                            ((TCEN) == QSPI_TIMEOUT_COUNTER_ENABLE))
+
+#define IS_QSPI_TIMEOUT_PERIOD(PERIOD)     ((PERIOD) <= 0xFFFFU)
+/**
+* @}
+*/
+/* End of private macros -----------------------------------------------------*/
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* defined(QUADSPI) */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32F4xx_HAL_QSPI_H */
diff --git a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h
new file mode 100644
index 0000000..908432d
--- /dev/null
+++ b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h
@@ -0,0 +1,1459 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hal_rcc.h
+  * @author  MCD Application Team
+  * @brief   Header file of RCC HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file in
+  * the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_RCC_H
+#define __STM32F4xx_HAL_RCC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/* Include RCC HAL Extended module */
+/* (include on top of file since RCC structures are defined in extended file) */
+#include "stm32f4xx_hal_rcc_ex.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup RCC
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup RCC_Exported_Types RCC Exported Types
+  * @{
+  */
+
+/**
+  * @brief  RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition
+  */
+typedef struct
+{
+  uint32_t OscillatorType;       /*!< The oscillators to be configured.
+                                      This parameter can be a value of @ref RCC_Oscillator_Type                   */
+
+  uint32_t HSEState;             /*!< The new state of the HSE.
+                                      This parameter can be a value of @ref RCC_HSE_Config                        */
+
+  uint32_t LSEState;             /*!< The new state of the LSE.
+                                      This parameter can be a value of @ref RCC_LSE_Config                        */
+
+  uint32_t HSIState;             /*!< The new state of the HSI.
+                                      This parameter can be a value of @ref RCC_HSI_Config                        */
+
+  uint32_t HSICalibrationValue;  /*!< The HSI calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT).
+                                       This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */
+
+  uint32_t LSIState;             /*!< The new state of the LSI.
+                                      This parameter can be a value of @ref RCC_LSI_Config                        */
+
+  RCC_PLLInitTypeDef PLL;        /*!< PLL structure parameters                                                    */
+}RCC_OscInitTypeDef;
+
+/**
+  * @brief  RCC System, AHB and APB busses clock configuration structure definition
+  */
+typedef struct
+{
+  uint32_t ClockType;             /*!< The clock to be configured.
+                                       This parameter can be a value of @ref RCC_System_Clock_Type      */
+
+  uint32_t SYSCLKSource;          /*!< The clock source (SYSCLKS) used as system clock.
+                                       This parameter can be a value of @ref RCC_System_Clock_Source    */
+
+  uint32_t AHBCLKDivider;         /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
+                                       This parameter can be a value of @ref RCC_AHB_Clock_Source       */
+
+  uint32_t APB1CLKDivider;        /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
+                                       This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
+
+  uint32_t APB2CLKDivider;        /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).
+                                       This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
+
+}RCC_ClkInitTypeDef;
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup RCC_Exported_Constants RCC Exported Constants
+  * @{
+  */
+
+/** @defgroup RCC_Oscillator_Type Oscillator Type
+  * @{
+  */
+#define RCC_OSCILLATORTYPE_NONE            0x00000000U
+#define RCC_OSCILLATORTYPE_HSE             0x00000001U
+#define RCC_OSCILLATORTYPE_HSI             0x00000002U
+#define RCC_OSCILLATORTYPE_LSE             0x00000004U
+#define RCC_OSCILLATORTYPE_LSI             0x00000008U
+/**
+  * @}
+  */
+
+/** @defgroup RCC_HSE_Config HSE Config
+  * @{
+  */
+#define RCC_HSE_OFF                      0x00000000U
+#define RCC_HSE_ON                       RCC_CR_HSEON
+#define RCC_HSE_BYPASS                   ((uint32_t)(RCC_CR_HSEBYP | RCC_CR_HSEON))
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LSE_Config LSE Config
+  * @{
+  */
+#define RCC_LSE_OFF                    0x00000000U
+#define RCC_LSE_ON                     RCC_BDCR_LSEON
+#define RCC_LSE_BYPASS                 ((uint32_t)(RCC_BDCR_LSEBYP | RCC_BDCR_LSEON))
+/**
+  * @}
+  */
+
+/** @defgroup RCC_HSI_Config HSI Config
+  * @{
+  */
+#define RCC_HSI_OFF                      ((uint8_t)0x00)
+#define RCC_HSI_ON                       ((uint8_t)0x01)
+
+#define RCC_HSICALIBRATION_DEFAULT       0x10U         /* Default HSI calibration trimming value */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LSI_Config LSI Config
+  * @{
+  */
+#define RCC_LSI_OFF                      ((uint8_t)0x00)
+#define RCC_LSI_ON                       ((uint8_t)0x01)
+/**
+  * @}
+  */
+
+/** @defgroup RCC_PLL_Config PLL Config
+  * @{
+  */
+#define RCC_PLL_NONE                      ((uint8_t)0x00)
+#define RCC_PLL_OFF                       ((uint8_t)0x01)
+#define RCC_PLL_ON                        ((uint8_t)0x02)
+/**
+  * @}
+  */
+
+/** @defgroup RCC_PLLP_Clock_Divider PLLP Clock Divider
+  * @{
+  */
+#define RCC_PLLP_DIV2                  0x00000002U
+#define RCC_PLLP_DIV4                  0x00000004U
+#define RCC_PLLP_DIV6                  0x00000006U
+#define RCC_PLLP_DIV8                  0x00000008U
+/**
+  * @}
+  */
+
+/** @defgroup RCC_PLL_Clock_Source PLL Clock Source
+  * @{
+  */
+#define RCC_PLLSOURCE_HSI                RCC_PLLCFGR_PLLSRC_HSI
+#define RCC_PLLSOURCE_HSE                RCC_PLLCFGR_PLLSRC_HSE
+/**
+  * @}
+  */
+
+/** @defgroup RCC_System_Clock_Type System Clock Type
+  * @{
+  */
+#define RCC_CLOCKTYPE_SYSCLK             0x00000001U
+#define RCC_CLOCKTYPE_HCLK               0x00000002U
+#define RCC_CLOCKTYPE_PCLK1              0x00000004U
+#define RCC_CLOCKTYPE_PCLK2              0x00000008U
+/**
+  * @}
+  */
+
+/** @defgroup RCC_System_Clock_Source System Clock Source
+  * @note     The RCC_SYSCLKSOURCE_PLLRCLK parameter is available only for
+  *           STM32F446xx devices.
+  * @{
+  */
+#define RCC_SYSCLKSOURCE_HSI             RCC_CFGR_SW_HSI
+#define RCC_SYSCLKSOURCE_HSE             RCC_CFGR_SW_HSE
+#define RCC_SYSCLKSOURCE_PLLCLK          RCC_CFGR_SW_PLL
+#define RCC_SYSCLKSOURCE_PLLRCLK         ((uint32_t)(RCC_CFGR_SW_0 | RCC_CFGR_SW_1))
+/**
+  * @}
+  */
+
+/** @defgroup RCC_System_Clock_Source_Status System Clock Source Status
+  * @note     The RCC_SYSCLKSOURCE_STATUS_PLLRCLK parameter is available only for
+  *           STM32F446xx devices.
+  * @{
+  */
+#define RCC_SYSCLKSOURCE_STATUS_HSI     RCC_CFGR_SWS_HSI   /*!< HSI used as system clock */
+#define RCC_SYSCLKSOURCE_STATUS_HSE     RCC_CFGR_SWS_HSE   /*!< HSE used as system clock */
+#define RCC_SYSCLKSOURCE_STATUS_PLLCLK  RCC_CFGR_SWS_PLL   /*!< PLL used as system clock */
+#define RCC_SYSCLKSOURCE_STATUS_PLLRCLK ((uint32_t)(RCC_CFGR_SWS_0 | RCC_CFGR_SWS_1))   /*!< PLLR used as system clock */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_AHB_Clock_Source AHB Clock Source
+  * @{
+  */
+#define RCC_SYSCLK_DIV1                  RCC_CFGR_HPRE_DIV1
+#define RCC_SYSCLK_DIV2                  RCC_CFGR_HPRE_DIV2
+#define RCC_SYSCLK_DIV4                  RCC_CFGR_HPRE_DIV4
+#define RCC_SYSCLK_DIV8                  RCC_CFGR_HPRE_DIV8
+#define RCC_SYSCLK_DIV16                 RCC_CFGR_HPRE_DIV16
+#define RCC_SYSCLK_DIV64                 RCC_CFGR_HPRE_DIV64
+#define RCC_SYSCLK_DIV128                RCC_CFGR_HPRE_DIV128
+#define RCC_SYSCLK_DIV256                RCC_CFGR_HPRE_DIV256
+#define RCC_SYSCLK_DIV512                RCC_CFGR_HPRE_DIV512
+/**
+  * @}
+  */
+
+/** @defgroup RCC_APB1_APB2_Clock_Source APB1/APB2 Clock Source
+  * @{
+  */
+#define RCC_HCLK_DIV1                    RCC_CFGR_PPRE1_DIV1
+#define RCC_HCLK_DIV2                    RCC_CFGR_PPRE1_DIV2
+#define RCC_HCLK_DIV4                    RCC_CFGR_PPRE1_DIV4
+#define RCC_HCLK_DIV8                    RCC_CFGR_PPRE1_DIV8
+#define RCC_HCLK_DIV16                   RCC_CFGR_PPRE1_DIV16
+/**
+  * @}
+  */
+
+/** @defgroup RCC_RTC_Clock_Source RTC Clock Source
+  * @{
+  */
+#define RCC_RTCCLKSOURCE_NO_CLK          0x00000000U
+#define RCC_RTCCLKSOURCE_LSE             0x00000100U
+#define RCC_RTCCLKSOURCE_LSI             0x00000200U
+#define RCC_RTCCLKSOURCE_HSE_DIVX        0x00000300U
+#define RCC_RTCCLKSOURCE_HSE_DIV2        0x00020300U
+#define RCC_RTCCLKSOURCE_HSE_DIV3        0x00030300U
+#define RCC_RTCCLKSOURCE_HSE_DIV4        0x00040300U
+#define RCC_RTCCLKSOURCE_HSE_DIV5        0x00050300U
+#define RCC_RTCCLKSOURCE_HSE_DIV6        0x00060300U
+#define RCC_RTCCLKSOURCE_HSE_DIV7        0x00070300U
+#define RCC_RTCCLKSOURCE_HSE_DIV8        0x00080300U
+#define RCC_RTCCLKSOURCE_HSE_DIV9        0x00090300U
+#define RCC_RTCCLKSOURCE_HSE_DIV10       0x000A0300U
+#define RCC_RTCCLKSOURCE_HSE_DIV11       0x000B0300U
+#define RCC_RTCCLKSOURCE_HSE_DIV12       0x000C0300U
+#define RCC_RTCCLKSOURCE_HSE_DIV13       0x000D0300U
+#define RCC_RTCCLKSOURCE_HSE_DIV14       0x000E0300U
+#define RCC_RTCCLKSOURCE_HSE_DIV15       0x000F0300U
+#define RCC_RTCCLKSOURCE_HSE_DIV16       0x00100300U
+#define RCC_RTCCLKSOURCE_HSE_DIV17       0x00110300U
+#define RCC_RTCCLKSOURCE_HSE_DIV18       0x00120300U
+#define RCC_RTCCLKSOURCE_HSE_DIV19       0x00130300U
+#define RCC_RTCCLKSOURCE_HSE_DIV20       0x00140300U
+#define RCC_RTCCLKSOURCE_HSE_DIV21       0x00150300U
+#define RCC_RTCCLKSOURCE_HSE_DIV22       0x00160300U
+#define RCC_RTCCLKSOURCE_HSE_DIV23       0x00170300U
+#define RCC_RTCCLKSOURCE_HSE_DIV24       0x00180300U
+#define RCC_RTCCLKSOURCE_HSE_DIV25       0x00190300U
+#define RCC_RTCCLKSOURCE_HSE_DIV26       0x001A0300U
+#define RCC_RTCCLKSOURCE_HSE_DIV27       0x001B0300U
+#define RCC_RTCCLKSOURCE_HSE_DIV28       0x001C0300U
+#define RCC_RTCCLKSOURCE_HSE_DIV29       0x001D0300U
+#define RCC_RTCCLKSOURCE_HSE_DIV30       0x001E0300U
+#define RCC_RTCCLKSOURCE_HSE_DIV31       0x001F0300U
+/**
+  * @}
+  */
+
+/** @defgroup RCC_MCO_Index MCO Index
+  * @{
+  */
+#define RCC_MCO1                         0x00000000U
+#define RCC_MCO2                         0x00000001U
+/**
+  * @}
+  */
+
+/** @defgroup RCC_MCO1_Clock_Source MCO1 Clock Source
+  * @{
+  */
+#define RCC_MCO1SOURCE_HSI               0x00000000U
+#define RCC_MCO1SOURCE_LSE               RCC_CFGR_MCO1_0
+#define RCC_MCO1SOURCE_HSE               RCC_CFGR_MCO1_1
+#define RCC_MCO1SOURCE_PLLCLK            RCC_CFGR_MCO1
+/**
+  * @}
+  */
+
+/** @defgroup RCC_MCOx_Clock_Prescaler MCOx Clock Prescaler
+  * @{
+  */
+#define RCC_MCODIV_1                    0x00000000U
+#define RCC_MCODIV_2                    RCC_CFGR_MCO1PRE_2
+#define RCC_MCODIV_3                    ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_2)
+#define RCC_MCODIV_4                    ((uint32_t)RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_2)
+#define RCC_MCODIV_5                    RCC_CFGR_MCO1PRE
+/**
+  * @}
+  */
+
+/** @defgroup RCC_Interrupt Interrupts
+  * @{
+  */
+#define RCC_IT_LSIRDY                    ((uint8_t)0x01)
+#define RCC_IT_LSERDY                    ((uint8_t)0x02)
+#define RCC_IT_HSIRDY                    ((uint8_t)0x04)
+#define RCC_IT_HSERDY                    ((uint8_t)0x08)
+#define RCC_IT_PLLRDY                    ((uint8_t)0x10)
+#define RCC_IT_PLLI2SRDY                 ((uint8_t)0x20)
+#define RCC_IT_CSS                       ((uint8_t)0x80)
+/**
+  * @}
+  */
+
+/** @defgroup RCC_Flag Flags
+  *        Elements values convention: 0XXYYYYYb
+  *           - YYYYY  : Flag position in the register
+  *           - 0XX  : Register index
+  *                 - 01: CR register
+  *                 - 10: BDCR register
+  *                 - 11: CSR register
+  * @{
+  */
+/* Flags in the CR register */
+#define RCC_FLAG_HSIRDY                  ((uint8_t)0x21)
+#define RCC_FLAG_HSERDY                  ((uint8_t)0x31)
+#define RCC_FLAG_PLLRDY                  ((uint8_t)0x39)
+#define RCC_FLAG_PLLI2SRDY               ((uint8_t)0x3B)
+
+/* Flags in the BDCR register */
+#define RCC_FLAG_LSERDY                  ((uint8_t)0x41)
+
+/* Flags in the CSR register */
+#define RCC_FLAG_LSIRDY                  ((uint8_t)0x61)
+#define RCC_FLAG_BORRST                  ((uint8_t)0x79)
+#define RCC_FLAG_PINRST                  ((uint8_t)0x7A)
+#define RCC_FLAG_PORRST                  ((uint8_t)0x7B)
+#define RCC_FLAG_SFTRST                  ((uint8_t)0x7C)
+#define RCC_FLAG_IWDGRST                 ((uint8_t)0x7D)
+#define RCC_FLAG_WWDGRST                 ((uint8_t)0x7E)
+#define RCC_FLAG_LPWRRST                 ((uint8_t)0x7F)
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup RCC_Exported_Macros RCC Exported Macros
+  * @{
+  */
+
+/** @defgroup RCC_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable
+  * @brief  Enable or disable the AHB1 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  * @{
+  */
+#define __HAL_RCC_GPIOA_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOAEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOAEN);\
+                                        UNUSED(tmpreg); \
+                                          } while(0U)
+#define __HAL_RCC_GPIOB_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOBEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOBEN);\
+                                        UNUSED(tmpreg); \
+                                          } while(0U)
+#define __HAL_RCC_GPIOC_CLK_ENABLE()  do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);\
+                                        UNUSED(tmpreg); \
+                                          } while(0U)
+#define __HAL_RCC_GPIOH_CLK_ENABLE()  do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOHEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOHEN);\
+                                        UNUSED(tmpreg); \
+                                         } while(0U)
+#define __HAL_RCC_DMA1_CLK_ENABLE()  do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\
+                                        UNUSED(tmpreg); \
+                                         } while(0U)
+#define __HAL_RCC_DMA2_CLK_ENABLE()     do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\
+                                        UNUSED(tmpreg); \
+                                          } while(0U)
+
+#define __HAL_RCC_GPIOA_CLK_DISABLE()        (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOAEN))
+#define __HAL_RCC_GPIOB_CLK_DISABLE()        (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOBEN))
+#define __HAL_RCC_GPIOC_CLK_DISABLE()        (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOCEN))
+#define __HAL_RCC_GPIOH_CLK_DISABLE()        (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOHEN))
+#define __HAL_RCC_DMA1_CLK_DISABLE()         (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA1EN))
+#define __HAL_RCC_DMA2_CLK_DISABLE()         (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA2EN))
+/**
+  * @}
+  */
+
+/** @defgroup RCC_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status
+  * @brief  Get the enable or disable status of the AHB1 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  * @{
+  */
+#define __HAL_RCC_GPIOA_IS_CLK_ENABLED()        ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOAEN)) != RESET)
+#define __HAL_RCC_GPIOB_IS_CLK_ENABLED()        ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOBEN)) != RESET)
+#define __HAL_RCC_GPIOC_IS_CLK_ENABLED()        ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOCEN)) != RESET)
+#define __HAL_RCC_GPIOH_IS_CLK_ENABLED()        ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOHEN)) != RESET)
+#define __HAL_RCC_DMA1_IS_CLK_ENABLED()         ((RCC->AHB1ENR &(RCC_AHB1ENR_DMA1EN)) != RESET)
+#define __HAL_RCC_DMA2_IS_CLK_ENABLED()         ((RCC->AHB1ENR &(RCC_AHB1ENR_DMA2EN)) != RESET)
+
+#define __HAL_RCC_GPIOA_IS_CLK_DISABLED()       ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOAEN)) == RESET)
+#define __HAL_RCC_GPIOB_IS_CLK_DISABLED()       ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOBEN)) == RESET)
+#define __HAL_RCC_GPIOC_IS_CLK_DISABLED()       ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOCEN)) == RESET)
+#define __HAL_RCC_GPIOH_IS_CLK_DISABLED()       ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOHEN)) == RESET)
+#define __HAL_RCC_DMA1_IS_CLK_DISABLED()        ((RCC->AHB1ENR &(RCC_AHB1ENR_DMA1EN)) == RESET)
+#define __HAL_RCC_DMA2_IS_CLK_DISABLED()        ((RCC->AHB1ENR &(RCC_AHB1ENR_DMA2EN)) == RESET)
+/**
+  * @}
+  */
+
+/** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable
+  * @brief  Enable or disable the Low Speed APB (APB1) peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  * @{
+  */
+#define __HAL_RCC_TIM5_CLK_ENABLE()     do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
+                                        UNUSED(tmpreg); \
+                                          } while(0U)
+#define __HAL_RCC_WWDG_CLK_ENABLE()     do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
+                                        UNUSED(tmpreg); \
+                                          } while(0U)
+#define __HAL_RCC_SPI2_CLK_ENABLE()     do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
+                                        UNUSED(tmpreg); \
+                                          } while(0U)
+#define __HAL_RCC_USART2_CLK_ENABLE()     do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
+                                        UNUSED(tmpreg); \
+                                          } while(0U)
+#define __HAL_RCC_I2C1_CLK_ENABLE()     do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
+                                        UNUSED(tmpreg); \
+                                          } while(0U)
+#define __HAL_RCC_I2C2_CLK_ENABLE()     do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
+                                        UNUSED(tmpreg); \
+                                          } while(0U)
+#define __HAL_RCC_PWR_CLK_ENABLE()     do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
+                                        UNUSED(tmpreg); \
+                                          } while(0U)
+
+#define __HAL_RCC_TIM5_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN))
+#define __HAL_RCC_WWDG_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN))
+#define __HAL_RCC_SPI2_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN))
+#define __HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN))
+#define __HAL_RCC_I2C1_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN))
+#define __HAL_RCC_I2C2_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))
+#define __HAL_RCC_PWR_CLK_DISABLE()    (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN))
+/**
+  * @}
+  */
+
+/** @defgroup RCC_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status
+  * @brief  Get the enable or disable status of the APB1 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  * @{
+  */
+#define __HAL_RCC_TIM5_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) != RESET)
+#define __HAL_RCC_WWDG_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) != RESET)
+#define __HAL_RCC_SPI2_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) != RESET)
+#define __HAL_RCC_USART2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) != RESET)
+#define __HAL_RCC_I2C1_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) != RESET)
+#define __HAL_RCC_I2C2_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) != RESET)
+#define __HAL_RCC_PWR_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) != RESET)
+
+#define __HAL_RCC_TIM5_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) == RESET)
+#define __HAL_RCC_WWDG_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) == RESET)
+#define __HAL_RCC_SPI2_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) == RESET)
+#define __HAL_RCC_USART2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) == RESET)
+#define __HAL_RCC_I2C1_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) == RESET)
+#define __HAL_RCC_I2C2_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) == RESET)
+#define __HAL_RCC_PWR_IS_CLK_DISABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) == RESET)
+/**
+  * @}
+  */
+
+/** @defgroup RCC_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable
+  * @brief  Enable or disable the High Speed APB (APB2) peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  * @{
+  */
+#define __HAL_RCC_TIM1_CLK_ENABLE()     do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
+                                        UNUSED(tmpreg); \
+                                          } while(0U)
+#define __HAL_RCC_USART1_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
+                                        UNUSED(tmpreg); \
+                                          } while(0U)
+#define __HAL_RCC_USART6_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\
+                                        UNUSED(tmpreg); \
+                                          } while(0U)
+#define __HAL_RCC_ADC1_CLK_ENABLE()     do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
+                                        UNUSED(tmpreg); \
+                                          } while(0U)
+#define __HAL_RCC_SPI1_CLK_ENABLE()     do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
+                                        UNUSED(tmpreg); \
+                                          } while(0U)
+#define __HAL_RCC_SYSCFG_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\
+                                        UNUSED(tmpreg); \
+                                          } while(0U)
+#define __HAL_RCC_TIM9_CLK_ENABLE()     do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\
+                                        UNUSED(tmpreg); \
+                                          } while(0U)
+#define __HAL_RCC_TIM11_CLK_ENABLE()    do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\
+                                        UNUSED(tmpreg); \
+                                          } while(0U)
+
+#define __HAL_RCC_TIM1_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN))
+#define __HAL_RCC_USART1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN))
+#define __HAL_RCC_USART6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART6EN))
+#define __HAL_RCC_ADC1_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN))
+#define __HAL_RCC_SPI1_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))
+#define __HAL_RCC_SYSCFG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SYSCFGEN))
+#define __HAL_RCC_TIM9_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM9EN))
+#define __HAL_RCC_TIM11_CLK_DISABLE()  (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM11EN))
+/**
+  * @}
+  */
+
+/** @defgroup RCC_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status
+  * @brief  Get the enable or disable status of the APB2 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  * @{
+  */
+#define __HAL_RCC_TIM1_IS_CLK_ENABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) != RESET)
+#define __HAL_RCC_USART1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) != RESET)
+#define __HAL_RCC_USART6_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART6EN)) != RESET)
+#define __HAL_RCC_ADC1_IS_CLK_ENABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) != RESET)
+#define __HAL_RCC_SPI1_IS_CLK_ENABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) != RESET)
+#define __HAL_RCC_SYSCFG_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) != RESET)
+#define __HAL_RCC_TIM9_IS_CLK_ENABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) != RESET)
+#define __HAL_RCC_TIM11_IS_CLK_ENABLED()  ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) != RESET)
+
+#define __HAL_RCC_TIM1_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) == RESET)
+#define __HAL_RCC_USART1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) == RESET)
+#define __HAL_RCC_USART6_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART6EN)) == RESET)
+#define __HAL_RCC_ADC1_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) == RESET)
+#define __HAL_RCC_SPI1_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) == RESET)
+#define __HAL_RCC_SYSCFG_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) == RESET)
+#define __HAL_RCC_TIM9_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) == RESET)
+#define __HAL_RCC_TIM11_IS_CLK_DISABLED()  ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) == RESET)
+/**
+  * @}
+  */
+
+/** @defgroup RCC_AHB1_Force_Release_Reset AHB1 Force Release Reset
+  * @brief  Force or release AHB1 peripheral reset.
+  * @{
+  */
+#define __HAL_RCC_AHB1_FORCE_RESET()    (RCC->AHB1RSTR = 0xFFFFFFFFU)
+#define __HAL_RCC_GPIOA_FORCE_RESET()   (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOARST))
+#define __HAL_RCC_GPIOB_FORCE_RESET()   (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOBRST))
+#define __HAL_RCC_GPIOC_FORCE_RESET()   (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOCRST))
+#define __HAL_RCC_GPIOH_FORCE_RESET()   (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOHRST))
+#define __HAL_RCC_DMA1_FORCE_RESET()    (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA1RST))
+#define __HAL_RCC_DMA2_FORCE_RESET()    (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA2RST))
+
+#define __HAL_RCC_AHB1_RELEASE_RESET()  (RCC->AHB1RSTR = 0x00U)
+#define __HAL_RCC_GPIOA_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOARST))
+#define __HAL_RCC_GPIOB_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOBRST))
+#define __HAL_RCC_GPIOC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOCRST))
+#define __HAL_RCC_GPIOH_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOHRST))
+#define __HAL_RCC_DMA1_RELEASE_RESET()  (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA1RST))
+#define __HAL_RCC_DMA2_RELEASE_RESET()  (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA2RST))
+/**
+  * @}
+  */
+
+/** @defgroup RCC_APB1_Force_Release_Reset APB1 Force Release Reset
+  * @brief  Force or release APB1 peripheral reset.
+  * @{
+  */
+#define __HAL_RCC_APB1_FORCE_RESET()     (RCC->APB1RSTR = 0xFFFFFFFFU)
+#define __HAL_RCC_TIM5_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM5RST))
+#define __HAL_RCC_WWDG_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_WWDGRST))
+#define __HAL_RCC_SPI2_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST))
+#define __HAL_RCC_USART2_FORCE_RESET()   (RCC->APB1RSTR |= (RCC_APB1RSTR_USART2RST))
+#define __HAL_RCC_I2C1_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C1RST))
+#define __HAL_RCC_I2C2_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C2RST))
+#define __HAL_RCC_PWR_FORCE_RESET()      (RCC->APB1RSTR |= (RCC_APB1RSTR_PWRRST))
+
+#define __HAL_RCC_APB1_RELEASE_RESET()   (RCC->APB1RSTR = 0x00U)
+#define __HAL_RCC_TIM5_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM5RST))
+#define __HAL_RCC_WWDG_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_WWDGRST))
+#define __HAL_RCC_SPI2_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST))
+#define __HAL_RCC_USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST))
+#define __HAL_RCC_I2C1_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C1RST))
+#define __HAL_RCC_I2C2_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST))
+#define __HAL_RCC_PWR_RELEASE_RESET()    (RCC->APB1RSTR &= ~(RCC_APB1RSTR_PWRRST))
+/**
+  * @}
+  */
+
+/** @defgroup RCC_APB2_Force_Release_Reset APB2 Force Release Reset
+  * @brief  Force or release APB2 peripheral reset.
+  * @{
+  */
+#define __HAL_RCC_APB2_FORCE_RESET()     (RCC->APB2RSTR = 0xFFFFFFFFU)
+#define __HAL_RCC_TIM1_FORCE_RESET()     (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM1RST))
+#define __HAL_RCC_USART1_FORCE_RESET()   (RCC->APB2RSTR |= (RCC_APB2RSTR_USART1RST))
+#define __HAL_RCC_USART6_FORCE_RESET()   (RCC->APB2RSTR |= (RCC_APB2RSTR_USART6RST))
+#define __HAL_RCC_ADC_FORCE_RESET()      (RCC->APB2RSTR |= (RCC_APB2RSTR_ADCRST))
+#define __HAL_RCC_SPI1_FORCE_RESET()     (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI1RST))
+#define __HAL_RCC_SYSCFG_FORCE_RESET()   (RCC->APB2RSTR |= (RCC_APB2RSTR_SYSCFGRST))
+#define __HAL_RCC_TIM9_FORCE_RESET()     (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM9RST))
+#define __HAL_RCC_TIM11_FORCE_RESET()    (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM11RST))
+
+#define __HAL_RCC_APB2_RELEASE_RESET()   (RCC->APB2RSTR = 0x00U)
+#define __HAL_RCC_TIM1_RELEASE_RESET()   (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM1RST))
+#define __HAL_RCC_USART1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART1RST))
+#define __HAL_RCC_USART6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART6RST))
+#define __HAL_RCC_ADC_RELEASE_RESET()    (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADCRST))
+#define __HAL_RCC_SPI1_RELEASE_RESET()   (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST))
+#define __HAL_RCC_SYSCFG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SYSCFGRST))
+#define __HAL_RCC_TIM9_RELEASE_RESET()   (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM9RST))
+#define __HAL_RCC_TIM11_RELEASE_RESET()  (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM11RST))
+/**
+  * @}
+  */
+
+/** @defgroup RCC_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable
+  * @brief  Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wake-up from SLEEP mode, the peripheral clock is enabled again.
+  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
+  * @{
+  */
+#define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE()    (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOALPEN))
+#define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE()    (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOBLPEN))
+#define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE()    (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOCLPEN))
+#define __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE()    (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOHLPEN))
+#define __HAL_RCC_DMA1_CLK_SLEEP_ENABLE()     (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA1LPEN))
+#define __HAL_RCC_DMA2_CLK_SLEEP_ENABLE()     (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA2LPEN))
+
+#define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE()   (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOALPEN))
+#define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE()   (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOBLPEN))
+#define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE()   (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOCLPEN))
+#define __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE()   (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOHLPEN))
+#define __HAL_RCC_DMA1_CLK_SLEEP_DISABLE()    (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA1LPEN))
+#define __HAL_RCC_DMA2_CLK_SLEEP_DISABLE()    (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA2LPEN))
+/**
+  * @}
+  */
+
+/** @defgroup RCC_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable
+  * @brief  Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wake-up from SLEEP mode, the peripheral clock is enabled again.
+  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
+  * @{
+  */
+#define __HAL_RCC_TIM5_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM5LPEN))
+#define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_WWDGLPEN))
+#define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI2LPEN))
+#define __HAL_RCC_USART2_CLK_SLEEP_ENABLE()  (RCC->APB1LPENR |= (RCC_APB1LPENR_USART2LPEN))
+#define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C1LPEN))
+#define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C2LPEN))
+#define __HAL_RCC_PWR_CLK_SLEEP_ENABLE()     (RCC->APB1LPENR |= (RCC_APB1LPENR_PWRLPEN))
+
+#define __HAL_RCC_TIM5_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM5LPEN))
+#define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_WWDGLPEN))
+#define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI2LPEN))
+#define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART2LPEN))
+#define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C1LPEN))
+#define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C2LPEN))
+#define __HAL_RCC_PWR_CLK_SLEEP_DISABLE()    (RCC->APB1LPENR &= ~(RCC_APB1LPENR_PWRLPEN))
+/**
+  * @}
+  */
+
+/** @defgroup RCC_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable
+  * @brief  Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wake-up from SLEEP mode, the peripheral clock is enabled again.
+  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
+  * @{
+  */
+#define __HAL_RCC_TIM1_CLK_SLEEP_ENABLE()    (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM1LPEN))
+#define __HAL_RCC_USART1_CLK_SLEEP_ENABLE()  (RCC->APB2LPENR |= (RCC_APB2LPENR_USART1LPEN))
+#define __HAL_RCC_USART6_CLK_SLEEP_ENABLE()  (RCC->APB2LPENR |= (RCC_APB2LPENR_USART6LPEN))
+#define __HAL_RCC_ADC1_CLK_SLEEP_ENABLE()    (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC1LPEN))
+#define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE()    (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI1LPEN))
+#define __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE()  (RCC->APB2LPENR |= (RCC_APB2LPENR_SYSCFGLPEN))
+#define __HAL_RCC_TIM9_CLK_SLEEP_ENABLE()    (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM9LPEN))
+#define __HAL_RCC_TIM11_CLK_SLEEP_ENABLE()   (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM11LPEN))
+
+#define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE()   (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM1LPEN))
+#define __HAL_RCC_USART1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_USART1LPEN))
+#define __HAL_RCC_USART6_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_USART6LPEN))
+#define __HAL_RCC_ADC1_CLK_SLEEP_DISABLE()   (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC1LPEN))
+#define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE()   (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI1LPEN))
+#define __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SYSCFGLPEN))
+#define __HAL_RCC_TIM9_CLK_SLEEP_DISABLE()   (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM9LPEN))
+#define __HAL_RCC_TIM11_CLK_SLEEP_DISABLE()  (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM11LPEN))
+/**
+  * @}
+  */
+
+/** @defgroup RCC_HSI_Configuration HSI Configuration
+  * @{
+  */
+
+/** @brief  Macros to enable or disable the Internal High Speed oscillator (HSI).
+  * @note   The HSI is stopped by hardware when entering STOP and STANDBY modes.
+  *         It is used (enabled by hardware) as system clock source after startup
+  *         from Reset, wake-up from STOP and STANDBY mode, or in case of failure
+  *         of the HSE used directly or indirectly as system clock (if the Clock
+  *         Security System CSS is enabled).
+  * @note   HSI can not be stopped if it is used as system clock source. In this case,
+  *         you have to select another source of the system clock then stop the HSI.
+  * @note   After enabling the HSI, the application software should wait on HSIRDY
+  *         flag to be set indicating that HSI clock is stable and can be used as
+  *         system clock source.
+  *         This parameter can be: ENABLE or DISABLE.
+  * @note   When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
+  *         clock cycles.
+  */
+#define __HAL_RCC_HSI_ENABLE() (*(__IO uint32_t *) RCC_CR_HSION_BB = ENABLE)
+#define __HAL_RCC_HSI_DISABLE() (*(__IO uint32_t *) RCC_CR_HSION_BB = DISABLE)
+
+/** @brief  Macro to adjust the Internal High Speed oscillator (HSI) calibration value.
+  * @note   The calibration is used to compensate for the variations in voltage
+  *         and temperature that influence the frequency of the internal HSI RC.
+  * @param  __HSICalibrationValue__ specifies the calibration trimming value.
+  *         (default is RCC_HSICALIBRATION_DEFAULT).
+  *         This parameter must be a number between 0 and 0x1F.
+  */
+#define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICalibrationValue__) (MODIFY_REG(RCC->CR,\
+        RCC_CR_HSITRIM, (uint32_t)(__HSICalibrationValue__) << RCC_CR_HSITRIM_Pos))
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LSI_Configuration LSI Configuration
+  * @{
+  */
+
+/** @brief  Macros to enable or disable the Internal Low Speed oscillator (LSI).
+  * @note   After enabling the LSI, the application software should wait on
+  *         LSIRDY flag to be set indicating that LSI clock is stable and can
+  *         be used to clock the IWDG and/or the RTC.
+  * @note   LSI can not be disabled if the IWDG is running.
+  * @note   When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator
+  *         clock cycles.
+  */
+#define __HAL_RCC_LSI_ENABLE() (*(__IO uint32_t *) RCC_CSR_LSION_BB = ENABLE)
+#define __HAL_RCC_LSI_DISABLE() (*(__IO uint32_t *) RCC_CSR_LSION_BB = DISABLE)
+/**
+  * @}
+  */
+
+/** @defgroup RCC_HSE_Configuration HSE Configuration
+  * @{
+  */
+
+/**
+  * @brief  Macro to configure the External High Speed oscillator (HSE).
+  * @note   Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not supported by this macro.
+  *         User should request a transition to HSE Off first and then HSE On or HSE Bypass.
+  * @note   After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application
+  *         software should wait on HSERDY flag to be set indicating that HSE clock
+  *         is stable and can be used to clock the PLL and/or system clock.
+  * @note   HSE state can not be changed if it is used directly or through the
+  *         PLL as system clock. In this case, you have to select another source
+  *         of the system clock then change the HSE state (ex. disable it).
+  * @note   The HSE is stopped by hardware when entering STOP and STANDBY modes.
+  * @note   This function reset the CSSON bit, so if the clock security system(CSS)
+  *         was previously enabled you have to enable it again after calling this
+  *         function.
+  * @param  __STATE__ specifies the new state of the HSE.
+  *         This parameter can be one of the following values:
+  *            @arg RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after
+  *                              6 HSE oscillator clock cycles.
+  *            @arg RCC_HSE_ON: turn ON the HSE oscillator.
+  *            @arg RCC_HSE_BYPASS: HSE oscillator bypassed with external clock.
+  */
+#define __HAL_RCC_HSE_CONFIG(__STATE__)                         \
+                    do {                                        \
+                      if ((__STATE__) == RCC_HSE_ON)            \
+                      {                                         \
+                        SET_BIT(RCC->CR, RCC_CR_HSEON);         \
+                      }                                         \
+                      else if ((__STATE__) == RCC_HSE_BYPASS)   \
+                      {                                         \
+                        SET_BIT(RCC->CR, RCC_CR_HSEBYP);        \
+                        SET_BIT(RCC->CR, RCC_CR_HSEON);         \
+                      }                                         \
+                      else                                      \
+                      {                                         \
+                        CLEAR_BIT(RCC->CR, RCC_CR_HSEON);       \
+                        CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);      \
+                      }                                         \
+                    } while(0U)
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LSE_Configuration LSE Configuration
+  * @{
+  */
+
+/**
+  * @brief  Macro to configure the External Low Speed oscillator (LSE).
+  * @note   Transition LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this macro.
+  *         User should request a transition to LSE Off first and then LSE On or LSE Bypass.
+  * @note   As the LSE is in the Backup domain and write access is denied to
+  *         this domain after reset, you have to enable write access using
+  *         HAL_PWR_EnableBkUpAccess() function before to configure the LSE
+  *         (to be done once after reset).
+  * @note   After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application
+  *         software should wait on LSERDY flag to be set indicating that LSE clock
+  *         is stable and can be used to clock the RTC.
+  * @param  __STATE__ specifies the new state of the LSE.
+  *         This parameter can be one of the following values:
+  *            @arg RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after
+  *                              6 LSE oscillator clock cycles.
+  *            @arg RCC_LSE_ON: turn ON the LSE oscillator.
+  *            @arg RCC_LSE_BYPASS: LSE oscillator bypassed with external clock.
+  */
+#define __HAL_RCC_LSE_CONFIG(__STATE__) \
+                    do {                                       \
+                      if((__STATE__) == RCC_LSE_ON)            \
+                      {                                        \
+                        SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);    \
+                      }                                        \
+                      else if((__STATE__) == RCC_LSE_BYPASS)   \
+                      {                                        \
+                        SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);   \
+                        SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);    \
+                      }                                        \
+                      else                                     \
+                      {                                        \
+                        CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);  \
+                        CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
+                      }                                        \
+                    } while(0U)
+/**
+  * @}
+  */
+
+/** @defgroup RCC_Internal_RTC_Clock_Configuration RTC Clock Configuration
+  * @{
+  */
+
+/** @brief  Macros to enable or disable the RTC clock.
+  * @note   These macros must be used only after the RTC clock source was selected.
+  */
+#define __HAL_RCC_RTC_ENABLE() (*(__IO uint32_t *) RCC_BDCR_RTCEN_BB = ENABLE)
+#define __HAL_RCC_RTC_DISABLE() (*(__IO uint32_t *) RCC_BDCR_RTCEN_BB = DISABLE)
+
+/** @brief  Macros to configure the RTC clock (RTCCLK).
+  * @note   As the RTC clock configuration bits are in the Backup domain and write
+  *         access is denied to this domain after reset, you have to enable write
+  *         access using the Power Backup Access macro before to configure
+  *         the RTC clock source (to be done once after reset).
+  * @note   Once the RTC clock is configured it can't be changed unless the
+  *         Backup domain is reset using __HAL_RCC_BackupReset_RELEASE() macro, or by
+  *         a Power On Reset (POR).
+  * @param  __RTCCLKSource__ specifies the RTC clock source.
+  *         This parameter can be one of the following values:
+  *            @arg @ref RCC_RTCCLKSOURCE_NO_CLK : No clock selected as RTC clock.
+  *            @arg @ref RCC_RTCCLKSOURCE_LSE : LSE selected as RTC clock.
+  *            @arg @ref RCC_RTCCLKSOURCE_LSI : LSI selected as RTC clock.
+  *            @arg @ref RCC_RTCCLKSOURCE_HSE_DIVX HSE divided by X selected as RTC clock (X can be retrieved thanks to @ref __HAL_RCC_GET_RTC_HSE_PRESCALER()
+  * @note   If the LSE or LSI is used as RTC clock source, the RTC continues to
+  *         work in STOP and STANDBY modes, and can be used as wake-up source.
+  *         However, when the HSE clock is used as RTC clock source, the RTC
+  *         cannot be used in STOP and STANDBY modes.
+  * @note   The maximum input clock frequency for RTC is 1MHz (when using HSE as
+  *         RTC clock source).
+  */
+#define __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__) (((__RTCCLKSource__) & RCC_BDCR_RTCSEL) == RCC_BDCR_RTCSEL) ?    \
+                                                 MODIFY_REG(RCC->CFGR, RCC_CFGR_RTCPRE, ((__RTCCLKSource__) & 0xFFFFCFFU)) : CLEAR_BIT(RCC->CFGR, RCC_CFGR_RTCPRE)
+
+#define __HAL_RCC_RTC_CONFIG(__RTCCLKSource__) do { __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__);    \
+                                                    RCC->BDCR |= ((__RTCCLKSource__) & 0x00000FFFU);  \
+                                                   } while(0U)
+
+/** @brief Macro to get the RTC clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg @ref RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock
+  *            @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock
+  *            @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock
+  *            @arg @ref RCC_RTCCLKSOURCE_HSE_DIVX HSE divided by X selected as RTC clock (X can be retrieved thanks to @ref __HAL_RCC_GET_RTC_HSE_PRESCALER()
+  */
+#define __HAL_RCC_GET_RTC_SOURCE() (READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL))
+
+/**
+  * @brief   Get the RTC and HSE clock divider (RTCPRE).
+  * @retval Returned value can be one of the following values:
+ *            @arg @ref RCC_RTCCLKSOURCE_HSE_DIVX HSE divided by X selected as RTC clock (X can be retrieved thanks to @ref __HAL_RCC_GET_RTC_HSE_PRESCALER()
+  */
+#define  __HAL_RCC_GET_RTC_HSE_PRESCALER() (READ_BIT(RCC->CFGR, RCC_CFGR_RTCPRE) | RCC_BDCR_RTCSEL)
+
+/** @brief  Macros to force or release the Backup domain reset.
+  * @note   This function resets the RTC peripheral (including the backup registers)
+  *         and the RTC clock source selection in RCC_CSR register.
+  * @note   The BKPSRAM is not affected by this reset.
+  */
+#define __HAL_RCC_BACKUPRESET_FORCE() (*(__IO uint32_t *) RCC_BDCR_BDRST_BB = ENABLE)
+#define __HAL_RCC_BACKUPRESET_RELEASE() (*(__IO uint32_t *) RCC_BDCR_BDRST_BB = DISABLE)
+/**
+  * @}
+  */
+
+/** @defgroup RCC_PLL_Configuration PLL Configuration
+  * @{
+  */
+
+/** @brief  Macros to enable or disable the main PLL.
+  * @note   After enabling the main PLL, the application software should wait on
+  *         PLLRDY flag to be set indicating that PLL clock is stable and can
+  *         be used as system clock source.
+  * @note   The main PLL can not be disabled if it is used as system clock source
+  * @note   The main PLL is disabled by hardware when entering STOP and STANDBY modes.
+  */
+#define __HAL_RCC_PLL_ENABLE() (*(__IO uint32_t *) RCC_CR_PLLON_BB = ENABLE)
+#define __HAL_RCC_PLL_DISABLE() (*(__IO uint32_t *) RCC_CR_PLLON_BB = DISABLE)
+
+/** @brief  Macro to configure the PLL clock source.
+  * @note   This function must be used only when the main PLL is disabled.
+  * @param  __PLLSOURCE__ specifies the PLL entry clock source.
+  *         This parameter can be one of the following values:
+  *            @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
+  *            @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
+  *
+  */
+#define __HAL_RCC_PLL_PLLSOURCE_CONFIG(__PLLSOURCE__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (__PLLSOURCE__))
+
+/** @brief  Macro to configure the PLL multiplication factor.
+  * @note   This function must be used only when the main PLL is disabled.
+  * @param  __PLLM__ specifies the division factor for PLL VCO input clock
+  *         This parameter must be a number between Min_Data = 2 and Max_Data = 63.
+  * @note   You have to set the PLLM parameter correctly to ensure that the VCO input
+  *         frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
+  *         of 2 MHz to limit PLL jitter.
+  *
+  */
+#define __HAL_RCC_PLL_PLLM_CONFIG(__PLLM__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, (__PLLM__))
+/**
+  * @}
+  */
+
+/** @defgroup RCC_Get_Clock_source Get Clock source
+  * @{
+  */
+/**
+  * @brief Macro to configure the system clock source.
+  * @param __RCC_SYSCLKSOURCE__ specifies the system clock source.
+  * This parameter can be one of the following values:
+  *              - RCC_SYSCLKSOURCE_HSI: HSI oscillator is used as system clock source.
+  *              - RCC_SYSCLKSOURCE_HSE: HSE oscillator is used as system clock source.
+  *              - RCC_SYSCLKSOURCE_PLLCLK: PLL output is used as system clock source.
+  *              - RCC_SYSCLKSOURCE_PLLRCLK: PLLR output is used as system clock source. This
+  *                parameter is available only for STM32F446xx devices.
+  */
+#define __HAL_RCC_SYSCLK_CONFIG(__RCC_SYSCLKSOURCE__) MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__RCC_SYSCLKSOURCE__))
+
+/** @brief  Macro to get the clock source used as system clock.
+  * @retval The clock source used as system clock. The returned value can be one
+  *         of the following:
+  *              - RCC_SYSCLKSOURCE_STATUS_HSI: HSI used as system clock.
+  *              - RCC_SYSCLKSOURCE_STATUS_HSE: HSE used as system clock.
+  *              - RCC_SYSCLKSOURCE_STATUS_PLLCLK: PLL used as system clock.
+  *              - RCC_SYSCLKSOURCE_STATUS_PLLRCLK: PLLR used as system clock. This parameter
+  *                is available only for STM32F446xx devices.
+  */
+#define __HAL_RCC_GET_SYSCLK_SOURCE() (RCC->CFGR & RCC_CFGR_SWS)
+
+/** @brief  Macro to get the oscillator used as PLL clock source.
+  * @retval The oscillator used as PLL clock source. The returned value can be one
+  *         of the following:
+  *              - RCC_PLLSOURCE_HSI: HSI oscillator is used as PLL clock source.
+  *              - RCC_PLLSOURCE_HSE: HSE oscillator is used as PLL clock source.
+  */
+#define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC))
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_MCOx_Clock_Config RCC Extended MCOx Clock Config
+  * @{
+  */
+
+/** @brief  Macro to configure the MCO1 clock.
+  * @param  __MCOCLKSOURCE__ specifies the MCO clock source.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_MCO1SOURCE_HSI: HSI clock selected as MCO1 source
+  *            @arg RCC_MCO1SOURCE_LSE: LSE clock selected as MCO1 source
+  *            @arg RCC_MCO1SOURCE_HSE: HSE clock selected as MCO1 source
+  *            @arg RCC_MCO1SOURCE_PLLCLK: main PLL clock selected as MCO1 source
+  * @param  __MCODIV__ specifies the MCO clock prescaler.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_MCODIV_1: no division applied to MCOx clock
+  *            @arg RCC_MCODIV_2: division by 2 applied to MCOx clock
+  *            @arg RCC_MCODIV_3: division by 3 applied to MCOx clock
+  *            @arg RCC_MCODIV_4: division by 4 applied to MCOx clock
+  *            @arg RCC_MCODIV_5: division by 5 applied to MCOx clock
+  */
+#define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \
+                 MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO1 | RCC_CFGR_MCO1PRE), ((__MCOCLKSOURCE__) | (__MCODIV__)))
+
+/** @brief  Macro to configure the MCO2 clock.
+  * @param  __MCOCLKSOURCE__ specifies the MCO clock source.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_MCO2SOURCE_SYSCLK: System clock (SYSCLK) selected as MCO2 source
+  *            @arg RCC_MCO2SOURCE_PLLI2SCLK: PLLI2S clock selected as MCO2 source, available for all STM32F4 devices except STM32F410xx
+  *            @arg RCC_MCO2SOURCE_I2SCLK: I2SCLK clock selected as MCO2 source, available only for STM32F410Rx devices
+  *            @arg RCC_MCO2SOURCE_HSE: HSE clock selected as MCO2 source
+  *            @arg RCC_MCO2SOURCE_PLLCLK: main PLL clock selected as MCO2 source
+  * @param  __MCODIV__ specifies the MCO clock prescaler.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_MCODIV_1: no division applied to MCOx clock
+  *            @arg RCC_MCODIV_2: division by 2 applied to MCOx clock
+  *            @arg RCC_MCODIV_3: division by 3 applied to MCOx clock
+  *            @arg RCC_MCODIV_4: division by 4 applied to MCOx clock
+  *            @arg RCC_MCODIV_5: division by 5 applied to MCOx clock
+  * @note  For STM32F410Rx devices, to output I2SCLK clock on MCO2, you should have
+  *        at least one of the SPI clocks enabled (SPI1, SPI2 or SPI5).
+  */
+#define __HAL_RCC_MCO2_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \
+    MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO2 | RCC_CFGR_MCO2PRE), ((__MCOCLKSOURCE__) | ((__MCODIV__) << 3U)));
+/**
+  * @}
+  */
+
+/** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management
+  * @brief macros to manage the specified RCC Flags and interrupts.
+  * @{
+  */
+
+/** @brief  Enable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to enable
+  *         the selected interrupts).
+  * @param  __INTERRUPT__ specifies the RCC interrupt sources to be enabled.
+  *         This parameter can be any combination of the following values:
+  *            @arg RCC_IT_LSIRDY: LSI ready interrupt.
+  *            @arg RCC_IT_LSERDY: LSE ready interrupt.
+  *            @arg RCC_IT_HSIRDY: HSI ready interrupt.
+  *            @arg RCC_IT_HSERDY: HSE ready interrupt.
+  *            @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
+  *            @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
+  */
+#define __HAL_RCC_ENABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS |= (__INTERRUPT__))
+
+/** @brief Disable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to disable
+  *        the selected interrupts).
+  * @param  __INTERRUPT__ specifies the RCC interrupt sources to be disabled.
+  *         This parameter can be any combination of the following values:
+  *            @arg RCC_IT_LSIRDY: LSI ready interrupt.
+  *            @arg RCC_IT_LSERDY: LSE ready interrupt.
+  *            @arg RCC_IT_HSIRDY: HSI ready interrupt.
+  *            @arg RCC_IT_HSERDY: HSE ready interrupt.
+  *            @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
+  *            @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
+  */
+#define __HAL_RCC_DISABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS &= (uint8_t)(~(__INTERRUPT__)))
+
+/** @brief  Clear the RCC's interrupt pending bits (Perform Byte access to RCC_CIR[23:16]
+  *         bits to clear the selected interrupt pending bits.
+  * @param  __INTERRUPT__ specifies the interrupt pending bit to clear.
+  *         This parameter can be any combination of the following values:
+  *            @arg RCC_IT_LSIRDY: LSI ready interrupt.
+  *            @arg RCC_IT_LSERDY: LSE ready interrupt.
+  *            @arg RCC_IT_HSIRDY: HSI ready interrupt.
+  *            @arg RCC_IT_HSERDY: HSE ready interrupt.
+  *            @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
+  *            @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
+  *            @arg RCC_IT_CSS: Clock Security System interrupt
+  */
+#define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE2_ADDRESS = (__INTERRUPT__))
+
+/** @brief  Check the RCC's interrupt has occurred or not.
+  * @param  __INTERRUPT__ specifies the RCC interrupt source to check.
+  *         This parameter can be one of the following values:
+  *            @arg RCC_IT_LSIRDY: LSI ready interrupt.
+  *            @arg RCC_IT_LSERDY: LSE ready interrupt.
+  *            @arg RCC_IT_HSIRDY: HSI ready interrupt.
+  *            @arg RCC_IT_HSERDY: HSE ready interrupt.
+  *            @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
+  *            @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
+  *            @arg RCC_IT_CSS: Clock Security System interrupt
+  * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
+  */
+#define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIR & (__INTERRUPT__)) == (__INTERRUPT__))
+
+/** @brief Set RMVF bit to clear the reset flags: RCC_FLAG_PINRST, RCC_FLAG_PORRST,
+  *        RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST and RCC_FLAG_LPWRRST.
+  */
+#define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->CSR |= RCC_CSR_RMVF)
+
+/** @brief  Check RCC flag is set or not.
+  * @param  __FLAG__ specifies the flag to check.
+  *         This parameter can be one of the following values:
+  *            @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready.
+  *            @arg RCC_FLAG_HSERDY: HSE oscillator clock ready.
+  *            @arg RCC_FLAG_PLLRDY: Main PLL clock ready.
+  *            @arg RCC_FLAG_PLLI2SRDY: PLLI2S clock ready.
+  *            @arg RCC_FLAG_LSERDY: LSE oscillator clock ready.
+  *            @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready.
+  *            @arg RCC_FLAG_BORRST: POR/PDR or BOR reset.
+  *            @arg RCC_FLAG_PINRST: Pin reset.
+  *            @arg RCC_FLAG_PORRST: POR/PDR reset.
+  *            @arg RCC_FLAG_SFTRST: Software reset.
+  *            @arg RCC_FLAG_IWDGRST: Independent Watchdog reset.
+  *            @arg RCC_FLAG_WWDGRST: Window Watchdog reset.
+  *            @arg RCC_FLAG_LPWRRST: Low Power reset.
+  * @retval The new state of __FLAG__ (TRUE or FALSE).
+  */
+#define RCC_FLAG_MASK  ((uint8_t)0x1FU)
+#define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5U) == 1U)? RCC->CR :((((__FLAG__) >> 5U) == 2U) ? RCC->BDCR :((((__FLAG__) >> 5U) == 3U)? RCC->CSR :RCC->CIR))) & (1U << ((__FLAG__) & RCC_FLAG_MASK)))!= 0U)? 1U : 0U)
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+ /** @addtogroup RCC_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup RCC_Exported_Functions_Group1
+  * @{
+  */
+/* Initialization and de-initialization functions  ******************************/
+HAL_StatusTypeDef HAL_RCC_DeInit(void);
+HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
+HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency);
+/**
+  * @}
+  */
+
+/** @addtogroup RCC_Exported_Functions_Group2
+  * @{
+  */
+/* Peripheral Control functions  ************************************************/
+void     HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv);
+void     HAL_RCC_EnableCSS(void);
+void     HAL_RCC_DisableCSS(void);
+uint32_t HAL_RCC_GetSysClockFreq(void);
+uint32_t HAL_RCC_GetHCLKFreq(void);
+uint32_t HAL_RCC_GetPCLK1Freq(void);
+uint32_t HAL_RCC_GetPCLK2Freq(void);
+void     HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
+void     HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency);
+
+/* CSS NMI IRQ handler */
+void HAL_RCC_NMI_IRQHandler(void);
+
+/* User Callbacks in non blocking mode (IT mode) */
+void HAL_RCC_CSSCallback(void);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup RCC_Private_Constants RCC Private Constants
+  * @{
+  */
+
+/** @defgroup RCC_BitAddress_AliasRegion RCC BitAddress AliasRegion
+  * @brief RCC registers bit address in the alias region
+  * @{
+  */
+#define RCC_OFFSET                 (RCC_BASE - PERIPH_BASE)
+/* --- CR Register --- */
+/* Alias word address of HSION bit */
+#define RCC_CR_OFFSET              (RCC_OFFSET + 0x00U)
+#define RCC_HSION_BIT_NUMBER       0x00U
+#define RCC_CR_HSION_BB            (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32U) + (RCC_HSION_BIT_NUMBER * 4U))
+/* Alias word address of CSSON bit */
+#define RCC_CSSON_BIT_NUMBER       0x13U
+#define RCC_CR_CSSON_BB            (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32U) + (RCC_CSSON_BIT_NUMBER * 4U))
+/* Alias word address of PLLON bit */
+#define RCC_PLLON_BIT_NUMBER       0x18U
+#define RCC_CR_PLLON_BB            (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32U) + (RCC_PLLON_BIT_NUMBER * 4U))
+
+/* --- BDCR Register --- */
+/* Alias word address of RTCEN bit */
+#define RCC_BDCR_OFFSET            (RCC_OFFSET + 0x70U)
+#define RCC_RTCEN_BIT_NUMBER       0x0FU
+#define RCC_BDCR_RTCEN_BB          (PERIPH_BB_BASE + (RCC_BDCR_OFFSET * 32U) + (RCC_RTCEN_BIT_NUMBER * 4U))
+/* Alias word address of BDRST bit */
+#define RCC_BDRST_BIT_NUMBER       0x10U
+#define RCC_BDCR_BDRST_BB          (PERIPH_BB_BASE + (RCC_BDCR_OFFSET * 32U) + (RCC_BDRST_BIT_NUMBER * 4U))
+
+/* --- CSR Register --- */
+/* Alias word address of LSION bit */
+#define RCC_CSR_OFFSET             (RCC_OFFSET + 0x74U)
+#define RCC_LSION_BIT_NUMBER        0x00U
+#define RCC_CSR_LSION_BB           (PERIPH_BB_BASE + (RCC_CSR_OFFSET * 32U) + (RCC_LSION_BIT_NUMBER * 4U))
+
+/* CR register byte 3 (Bits[23:16]) base address */
+#define RCC_CR_BYTE2_ADDRESS       0x40023802U
+
+/* CIR register byte 2 (Bits[15:8]) base address */
+#define RCC_CIR_BYTE1_ADDRESS      ((uint32_t)(RCC_BASE + 0x0CU + 0x01U))
+
+/* CIR register byte 3 (Bits[23:16]) base address */
+#define RCC_CIR_BYTE2_ADDRESS      ((uint32_t)(RCC_BASE + 0x0CU + 0x02U))
+
+/* BDCR register base address */
+#define RCC_BDCR_BYTE0_ADDRESS     (PERIPH_BASE + RCC_BDCR_OFFSET)
+
+#define RCC_DBP_TIMEOUT_VALUE      2U
+#define RCC_LSE_TIMEOUT_VALUE      LSE_STARTUP_TIMEOUT
+
+#define HSE_TIMEOUT_VALUE          HSE_STARTUP_TIMEOUT
+#define HSI_TIMEOUT_VALUE          2U  /* 2 ms */
+#define LSI_TIMEOUT_VALUE          2U  /* 2 ms */
+#define CLOCKSWITCH_TIMEOUT_VALUE  5000U /* 5 s */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup RCC_Private_Macros RCC Private Macros
+  * @{
+  */
+
+/** @defgroup RCC_IS_RCC_Definitions RCC Private macros to check input parameters
+  * @{
+  */
+#define IS_RCC_OSCILLATORTYPE(OSCILLATOR) ((OSCILLATOR) <= 15U)
+
+#define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \
+                         ((HSE) == RCC_HSE_BYPASS))
+
+#define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \
+                         ((LSE) == RCC_LSE_BYPASS))
+
+#define IS_RCC_HSI(HSI) (((HSI) == RCC_HSI_OFF) || ((HSI) == RCC_HSI_ON))
+
+#define IS_RCC_LSI(LSI) (((LSI) == RCC_LSI_OFF) || ((LSI) == RCC_LSI_ON))
+
+#define IS_RCC_PLL(PLL) (((PLL) == RCC_PLL_NONE) ||((PLL) == RCC_PLL_OFF) || ((PLL) == RCC_PLL_ON))
+
+#define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_HSI) || \
+                                  ((SOURCE) == RCC_PLLSOURCE_HSE))
+
+#define IS_RCC_SYSCLKSOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_HSI) || \
+                                     ((SOURCE) == RCC_SYSCLKSOURCE_HSE) || \
+                                     ((SOURCE) == RCC_SYSCLKSOURCE_PLLCLK) || \
+                                     ((SOURCE) == RCC_SYSCLKSOURCE_PLLRCLK))
+
+#define IS_RCC_RTCCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_RTCCLKSOURCE_LSE) || \
+                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_LSI) || \
+                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV2) || \
+                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV3) || \
+                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV4) || \
+                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV5) || \
+                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV6) || \
+                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV7) || \
+                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV8) || \
+                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV9) || \
+                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV10) || \
+                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV11) || \
+                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV12) || \
+                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV13) || \
+                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV14) || \
+                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV15) || \
+                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV16) || \
+                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV17) || \
+                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV18) || \
+                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV19) || \
+                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV20) || \
+                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV21) || \
+                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV22) || \
+                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV23) || \
+                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV24) || \
+                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV25) || \
+                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV26) || \
+                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV27) || \
+                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV28) || \
+                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV29) || \
+                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV30) || \
+                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV31))
+
+#define IS_RCC_PLLM_VALUE(VALUE) ((VALUE) <= 63U)
+
+#define IS_RCC_PLLP_VALUE(VALUE) (((VALUE) == 2U) || ((VALUE) == 4U) || ((VALUE) == 6U) || ((VALUE) == 8U))
+
+#define IS_RCC_PLLQ_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 15U))
+
+#define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_DIV1)   || ((HCLK) == RCC_SYSCLK_DIV2)   || \
+                           ((HCLK) == RCC_SYSCLK_DIV4)   || ((HCLK) == RCC_SYSCLK_DIV8)   || \
+                           ((HCLK) == RCC_SYSCLK_DIV16)  || ((HCLK) == RCC_SYSCLK_DIV64)  || \
+                           ((HCLK) == RCC_SYSCLK_DIV128) || ((HCLK) == RCC_SYSCLK_DIV256) || \
+                           ((HCLK) == RCC_SYSCLK_DIV512))
+
+#define IS_RCC_CLOCKTYPE(CLK) ((1U <= (CLK)) && ((CLK) <= 15U))
+
+#define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_DIV1) || ((PCLK) == RCC_HCLK_DIV2) || \
+                           ((PCLK) == RCC_HCLK_DIV4) || ((PCLK) == RCC_HCLK_DIV8) || \
+                           ((PCLK) == RCC_HCLK_DIV16))
+
+#define IS_RCC_MCO(MCOx) (((MCOx) == RCC_MCO1) || ((MCOx) == RCC_MCO2))
+
+#define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1SOURCE_HSI) || ((SOURCE) == RCC_MCO1SOURCE_LSE) || \
+                                   ((SOURCE) == RCC_MCO1SOURCE_HSE) || ((SOURCE) == RCC_MCO1SOURCE_PLLCLK))
+
+#define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCODIV_1)  || ((DIV) == RCC_MCODIV_2) || \
+                             ((DIV) == RCC_MCODIV_3) || ((DIV) == RCC_MCODIV_4) || \
+                             ((DIV) == RCC_MCODIV_5))
+#define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1FU)
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_RCC_H */
+
diff --git a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h
new file mode 100644
index 0000000..1ac56e1
--- /dev/null
+++ b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h
@@ -0,0 +1,7111 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hal_rcc_ex.h
+  * @author  MCD Application Team
+  * @brief   Header file of RCC HAL Extension module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file in
+  * the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  ******************************************************************************
+  */ 
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_RCC_EX_H
+#define __STM32F4xx_HAL_RCC_EX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup RCCEx
+  * @{
+  */ 
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup RCCEx_Exported_Types RCCEx Exported Types
+  * @{
+  */
+
+/**
+  * @brief  RCC PLL configuration structure definition
+  */
+typedef struct
+{
+  uint32_t PLLState;   /*!< The new state of the PLL.
+                            This parameter can be a value of @ref RCC_PLL_Config                      */
+
+  uint32_t PLLSource;  /*!< RCC_PLLSource: PLL entry clock source.
+                            This parameter must be a value of @ref RCC_PLL_Clock_Source               */
+
+  uint32_t PLLM;       /*!< PLLM: Division factor for PLL VCO input clock.
+                            This parameter must be a number between Min_Data = 0 and Max_Data = 63    */
+
+  uint32_t PLLN;       /*!< PLLN: Multiplication factor for PLL VCO output clock.
+                            This parameter must be a number between Min_Data = 50 and Max_Data = 432 
+                            except for STM32F411xE devices where the Min_Data = 192 */
+
+  uint32_t PLLP;       /*!< PLLP: Division factor for main system clock (SYSCLK).
+                            This parameter must be a value of @ref RCC_PLLP_Clock_Divider             */
+
+  uint32_t PLLQ;       /*!< PLLQ: Division factor for OTG FS, SDIO and RNG clocks.
+                            This parameter must be a number between Min_Data = 2 and Max_Data = 15    */
+#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F446xx) || defined(STM32F469xx) ||\
+    defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) ||\
+    defined(STM32F413xx) || defined(STM32F423xx)
+  uint32_t PLLR;       /*!< PLLR: PLL division factor for I2S, SAI, SYSTEM, SPDIFRX clocks.
+                            This parameter is only available in STM32F410xx/STM32F446xx/STM32F469xx/STM32F479xx
+                            and STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx/STM32F413xx/STM32F423xx devices. 
+                            This parameter must be a number between Min_Data = 2 and Max_Data = 7     */
+#endif /* STM32F410xx || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */ 
+}RCC_PLLInitTypeDef;
+
+#if defined(STM32F446xx)
+/** 
+  * @brief  PLLI2S Clock structure definition  
+  */
+typedef struct
+{
+  uint32_t PLLI2SM;    /*!< Specifies division factor for PLL VCO input clock.
+                            This parameter must be a number between Min_Data = 2 and Max_Data = 63       */
+
+  uint32_t PLLI2SN;    /*!< Specifies the multiplication factor for PLLI2S VCO output clock.
+                            This parameter must be a number between Min_Data = 50 and Max_Data = 432    */
+
+  uint32_t PLLI2SP;    /*!< Specifies division factor for SPDIFRX Clock.
+                            This parameter must be a value of @ref RCCEx_PLLI2SP_Clock_Divider           */
+
+  uint32_t PLLI2SQ;    /*!< Specifies the division factor for SAI clock.
+                            This parameter must be a number between Min_Data = 2 and Max_Data = 15. 
+                            This parameter will be used only when PLLI2S is selected as Clock Source SAI */
+                           
+  uint32_t PLLI2SR;    /*!< Specifies the division factor for I2S clock.
+                            This parameter must be a number between Min_Data = 2 and Max_Data = 7. 
+                            This parameter will be used only when PLLI2S is selected as Clock Source I2S */
+}RCC_PLLI2SInitTypeDef;
+
+/** 
+  * @brief  PLLSAI Clock structure definition  
+  */
+typedef struct
+{
+  uint32_t PLLSAIM;    /*!< Specifies division factor for PLL VCO input clock.
+                            This parameter must be a number between Min_Data = 2 and Max_Data = 63       */
+
+  uint32_t PLLSAIN;    /*!< Specifies the multiplication factor for PLLI2S VCO output clock.
+                            This parameter must be a number between Min_Data = 50 and Max_Data = 432    */
+
+  uint32_t PLLSAIP;    /*!< Specifies division factor for OTG FS, SDIO and RNG clocks.
+                            This parameter must be a value of @ref RCCEx_PLLSAIP_Clock_Divider           */
+                                                             
+  uint32_t PLLSAIQ;    /*!< Specifies the division factor for SAI clock.
+                            This parameter must be a number between Min_Data = 2 and Max_Data = 15.
+                            This parameter will be used only when PLLSAI is selected as Clock Source SAI */
+}RCC_PLLSAIInitTypeDef;
+
+/** 
+  * @brief  RCC extended clocks structure definition  
+  */
+typedef struct
+{
+  uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
+                                      This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
+
+  RCC_PLLI2SInitTypeDef PLLI2S;  /*!< PLL I2S structure parameters. 
+                                      This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
+
+  RCC_PLLSAIInitTypeDef PLLSAI;  /*!< PLL SAI structure parameters. 
+                                      This parameter will be used only when PLLI2S is selected as Clock Source SAI or LTDC */
+
+  uint32_t PLLI2SDivQ;           /*!< Specifies the PLLI2S division factor for SAI1 clock.
+                                      This parameter must be a number between Min_Data = 1 and Max_Data = 32
+                                      This parameter will be used only when PLLI2S is selected as Clock Source SAI */
+
+  uint32_t PLLSAIDivQ;           /*!< Specifies the PLLI2S division factor for SAI1 clock.
+                                      This parameter must be a number between Min_Data = 1 and Max_Data = 32
+                                      This parameter will be used only when PLLSAI is selected as Clock Source SAI */
+
+  uint32_t Sai1ClockSelection;    /*!< Specifies SAI1 Clock Source Selection. 
+                                      This parameter can be a value of @ref RCCEx_SAI1_Clock_Source */
+
+  uint32_t Sai2ClockSelection;    /*!< Specifies SAI2 Clock Source Selection. 
+                                      This parameter can be a value of @ref RCCEx_SAI2_Clock_Source */
+                                      
+  uint32_t I2sApb1ClockSelection;    /*!< Specifies I2S APB1 Clock Source Selection. 
+                                      This parameter can be a value of @ref RCCEx_I2SAPB1_Clock_Source */
+
+  uint32_t I2sApb2ClockSelection;    /*!< Specifies I2S APB2 Clock Source Selection. 
+                                      This parameter can be a value of @ref RCCEx_I2SAPB2_Clock_Source */
+
+  uint32_t RTCClockSelection;      /*!< Specifies RTC Clock Source Selection. 
+                                      This parameter can be a value of @ref RCC_RTC_Clock_Source */
+
+  uint32_t SdioClockSelection;    /*!< Specifies SDIO Clock Source Selection. 
+                                      This parameter can be a value of @ref RCCEx_SDIO_Clock_Source */
+
+  uint32_t CecClockSelection;      /*!< Specifies CEC Clock Source Selection. 
+                                      This parameter can be a value of @ref RCCEx_CEC_Clock_Source */
+
+  uint32_t Fmpi2c1ClockSelection;  /*!< Specifies FMPI2C1 Clock Source Selection. 
+                                      This parameter can be a value of @ref RCCEx_FMPI2C1_Clock_Source */
+
+  uint32_t SpdifClockSelection;    /*!< Specifies SPDIFRX Clock Source Selection. 
+                                      This parameter can be a value of @ref RCCEx_SPDIFRX_Clock_Source */
+
+  uint32_t Clk48ClockSelection;     /*!< Specifies CLK48 Clock Selection this clock used OTG FS, SDIO and RNG clocks. 
+                                      This parameter can be a value of @ref RCCEx_CLK48_Clock_Source */
+  
+  uint8_t TIMPresSelection;      /*!< Specifies TIM Clock Source Selection. 
+                                      This parameter can be a value of @ref RCCEx_TIM_PRescaler_Selection */
+}RCC_PeriphCLKInitTypeDef;
+#endif /* STM32F446xx */   
+
+#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
+/** 
+  * @brief  RCC extended clocks structure definition
+  */
+typedef struct
+{
+  uint32_t PeriphClockSelection;   /*!< The Extended Clock to be configured.
+                                      This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
+
+  uint32_t I2SClockSelection;      /*!< Specifies RTC Clock Source Selection. 
+                                      This parameter can be a value of @ref RCCEx_I2S_APB_Clock_Source */
+                                      
+  uint32_t RTCClockSelection;      /*!< Specifies RTC Clock Source Selection. 
+                                      This parameter can be a value of @ref RCC_RTC_Clock_Source */
+
+  uint32_t Lptim1ClockSelection;   /*!< Specifies LPTIM1 Clock Source Selection. 
+                                      This parameter can be a value of @ref RCCEx_LPTIM1_Clock_Source */
+  
+  uint32_t Fmpi2c1ClockSelection;  /*!< Specifies FMPI2C1 Clock Source Selection. 
+                                      This parameter can be a value of @ref RCCEx_FMPI2C1_Clock_Source */
+
+  uint8_t TIMPresSelection;        /*!< Specifies TIM Clock Source Selection. 
+                                      This parameter can be a value of @ref RCCEx_TIM_PRescaler_Selection */
+}RCC_PeriphCLKInitTypeDef;
+#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
+
+#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
+/** 
+  * @brief  PLLI2S Clock structure definition  
+  */
+typedef struct
+{
+  uint32_t PLLI2SM;    /*!< Specifies division factor for PLL VCO input clock.
+                            This parameter must be a number between Min_Data = 2 and Max_Data = 63       */
+
+  uint32_t PLLI2SN;    /*!< Specifies the multiplication factor for PLLI2S VCO output clock.
+                            This parameter must be a number between Min_Data = 50 and Max_Data = 432    */
+
+  uint32_t PLLI2SQ;    /*!< Specifies the division factor for SAI clock.
+                            This parameter must be a number between Min_Data = 2 and Max_Data = 15. 
+                            This parameter will be used only when PLLI2S is selected as Clock Source SAI */
+                           
+  uint32_t PLLI2SR;    /*!< Specifies the division factor for I2S clock.
+                            This parameter must be a number between Min_Data = 2 and Max_Data = 7. 
+                            This parameter will be used only when PLLI2S is selected as Clock Source I2S */
+}RCC_PLLI2SInitTypeDef;
+
+/** 
+  * @brief  RCC extended clocks structure definition
+  */
+typedef struct
+{
+  uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
+                                      This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
+
+  RCC_PLLI2SInitTypeDef PLLI2S;  /*!< PLL I2S structure parameters. 
+                                      This parameter will be used only when PLLI2S is selected as Clock Source I2S */
+  
+#if defined(STM32F413xx) || defined(STM32F423xx)
+  uint32_t PLLDivR;              /*!< Specifies the PLL division factor for SAI1 clock.
+                                      This parameter must be a number between Min_Data = 1 and Max_Data = 32
+                                      This parameter will be used only when PLL is selected as Clock Source SAI */
+
+  uint32_t PLLI2SDivR;           /*!< Specifies the PLLI2S division factor for SAI1 clock.
+                                      This parameter must be a number between Min_Data = 1 and Max_Data = 32
+                                      This parameter will be used only when PLLI2S is selected as Clock Source SAI */
+#endif /* STM32F413xx || STM32F423xx */  
+                                      
+  uint32_t I2sApb1ClockSelection;    /*!< Specifies I2S APB1 Clock Source Selection. 
+                                      This parameter can be a value of @ref RCCEx_I2SAPB1_Clock_Source */
+
+  uint32_t I2sApb2ClockSelection;    /*!< Specifies I2S APB2 Clock Source Selection. 
+                                      This parameter can be a value of @ref RCCEx_I2SAPB2_Clock_Source */
+
+  uint32_t RTCClockSelection;      /*!< Specifies RTC Clock Source Selection. 
+                                      This parameter can be a value of @ref RCC_RTC_Clock_Source */
+
+  uint32_t SdioClockSelection;    /*!< Specifies SDIO Clock Source Selection. 
+                                      This parameter can be a value of @ref RCCEx_SDIO_Clock_Source */
+
+  uint32_t Fmpi2c1ClockSelection;  /*!< Specifies FMPI2C1 Clock Source Selection. 
+                                      This parameter can be a value of @ref RCCEx_FMPI2C1_Clock_Source */
+
+  uint32_t Clk48ClockSelection;     /*!< Specifies CLK48 Clock Selection this clock used OTG FS, SDIO and RNG clocks.
+                                      This parameter can be a value of @ref RCCEx_CLK48_Clock_Source */
+  
+  uint32_t Dfsdm1ClockSelection;    /*!< Specifies DFSDM1 Clock Selection.
+                                      This parameter can be a value of @ref RCCEx_DFSDM1_Kernel_Clock_Source */
+
+  uint32_t Dfsdm1AudioClockSelection;/*!< Specifies DFSDM1 Audio Clock Selection.
+                                      This parameter can be a value of @ref RCCEx_DFSDM1_Audio_Clock_Source */
+  
+#if defined(STM32F413xx) || defined(STM32F423xx)
+  uint32_t Dfsdm2ClockSelection;    /*!< Specifies DFSDM2 Clock Selection.
+                                      This parameter can be a value of @ref RCCEx_DFSDM2_Kernel_Clock_Source */
+
+  uint32_t Dfsdm2AudioClockSelection;/*!< Specifies DFSDM2 Audio Clock Selection.
+                                      This parameter can be a value of @ref RCCEx_DFSDM2_Audio_Clock_Source */
+  
+  uint32_t Lptim1ClockSelection;   /*!< Specifies LPTIM1 Clock Source Selection. 
+                                      This parameter can be a value of @ref RCCEx_LPTIM1_Clock_Source */
+  
+  uint32_t SaiAClockSelection;     /*!< Specifies SAI1_A Clock Prescalers Selection
+                                        This parameter can be a value of @ref RCCEx_SAI1_BlockA_Clock_Source */
+
+  uint32_t SaiBClockSelection;     /*!< Specifies SAI1_B Clock Prescalers Selection
+                                        This parameter can be a value of @ref RCCEx_SAI1_BlockB_Clock_Source */
+#endif /* STM32F413xx || STM32F423xx */
+
+  uint32_t PLLI2SSelection;      /*!< Specifies PLL I2S Clock Source Selection. 
+                                      This parameter can be a value of @ref RCCEx_PLL_I2S_Clock_Source */
+
+  uint8_t TIMPresSelection;      /*!< Specifies TIM Clock Source Selection. 
+                                      This parameter can be a value of @ref RCCEx_TIM_PRescaler_Selection */
+}RCC_PeriphCLKInitTypeDef;
+#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
+
+/** 
+  * @brief  PLLI2S Clock structure definition  
+  */
+typedef struct
+{
+  uint32_t PLLI2SN;    /*!< Specifies the multiplication factor for PLLI2S VCO output clock.
+                            This parameter must be a number between Min_Data = 50 and Max_Data = 432.
+                            This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
+
+  uint32_t PLLI2SR;    /*!< Specifies the division factor for I2S clock.
+                            This parameter must be a number between Min_Data = 2 and Max_Data = 7. 
+                            This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
+
+  uint32_t PLLI2SQ;    /*!< Specifies the division factor for SAI1 clock.
+                            This parameter must be a number between Min_Data = 2 and Max_Data = 15. 
+                            This parameter will be used only when PLLI2S is selected as Clock Source SAI */
+}RCC_PLLI2SInitTypeDef;
+
+/** 
+  * @brief  PLLSAI Clock structure definition  
+  */
+typedef struct
+{
+  uint32_t PLLSAIN;    /*!< Specifies the multiplication factor for PLLI2S VCO output clock.
+                            This parameter must be a number between Min_Data = 50 and Max_Data = 432.
+                            This parameter will be used only when PLLSAI is selected as Clock Source SAI or LTDC */ 
+#if defined(STM32F469xx) || defined(STM32F479xx)
+  uint32_t PLLSAIP;    /*!< Specifies division factor for OTG FS and SDIO clocks.
+                            This parameter is only available in STM32F469xx/STM32F479xx devices.
+                            This parameter must be a value of @ref RCCEx_PLLSAIP_Clock_Divider  */  
+#endif /* STM32F469xx || STM32F479xx */
+                                 
+  uint32_t PLLSAIQ;    /*!< Specifies the division factor for SAI1 clock.
+                            This parameter must be a number between Min_Data = 2 and Max_Data = 15.
+                            This parameter will be used only when PLLSAI is selected as Clock Source SAI or LTDC */
+                              
+  uint32_t PLLSAIR;    /*!< specifies the division factor for LTDC clock
+                            This parameter must be a number between Min_Data = 2 and Max_Data = 7.
+                            This parameter will be used only when PLLSAI is selected as Clock Source LTDC */
+
+}RCC_PLLSAIInitTypeDef;
+
+/** 
+  * @brief  RCC extended clocks structure definition  
+  */
+typedef struct
+{
+  uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
+                                      This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
+
+  RCC_PLLI2SInitTypeDef PLLI2S;  /*!< PLL I2S structure parameters. 
+                                      This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
+
+  RCC_PLLSAIInitTypeDef PLLSAI;  /*!< PLL SAI structure parameters. 
+                                      This parameter will be used only when PLLI2S is selected as Clock Source SAI or LTDC */
+
+  uint32_t PLLI2SDivQ;           /*!< Specifies the PLLI2S division factor for SAI1 clock.
+                                      This parameter must be a number between Min_Data = 1 and Max_Data = 32
+                                      This parameter will be used only when PLLI2S is selected as Clock Source SAI */
+
+  uint32_t PLLSAIDivQ;           /*!< Specifies the PLLI2S division factor for SAI1 clock.
+                                      This parameter must be a number between Min_Data = 1 and Max_Data = 32
+                                      This parameter will be used only when PLLSAI is selected as Clock Source SAI */
+
+  uint32_t PLLSAIDivR;           /*!< Specifies the PLLSAI division factor for LTDC clock.
+                                      This parameter must be one value of @ref RCCEx_PLLSAI_DIVR */
+
+  uint32_t RTCClockSelection;      /*!< Specifies RTC Clock Prescalers Selection. 
+                                      This parameter can be a value of @ref RCC_RTC_Clock_Source */
+
+  uint8_t TIMPresSelection;      /*!< Specifies TIM Clock Prescalers Selection. 
+                                      This parameter can be a value of @ref RCCEx_TIM_PRescaler_Selection */
+#if defined(STM32F469xx) || defined(STM32F479xx)
+  uint32_t Clk48ClockSelection;  /*!< Specifies CLK48 Clock Selection this clock used OTG FS, SDIO and RNG clocks. 
+                                      This parameter can be a value of @ref RCCEx_CLK48_Clock_Source */
+
+  uint32_t SdioClockSelection;   /*!< Specifies SDIO Clock Source Selection. 
+                                      This parameter can be a value of @ref RCCEx_SDIO_Clock_Source */  
+#endif /* STM32F469xx || STM32F479xx */  
+}RCC_PeriphCLKInitTypeDef;
+
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
+
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
+    defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE)
+/** 
+  * @brief  PLLI2S Clock structure definition  
+  */
+typedef struct
+{
+#if defined(STM32F411xE)
+  uint32_t PLLI2SM;    /*!< PLLM: Division factor for PLLI2S VCO input clock.
+                            This parameter must be a number between Min_Data = 2 and Max_Data = 62  */
+#endif /* STM32F411xE */
+                                
+  uint32_t PLLI2SN;    /*!< Specifies the multiplication factor for PLLI2S VCO output clock.
+                            This parameter must be a number between Min_Data = 50 and Max_Data = 432
+                            Except for STM32F411xE devices where the Min_Data = 192. 
+                            This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
+
+  uint32_t PLLI2SR;    /*!< Specifies the division factor for I2S clock.
+                            This parameter must be a number between Min_Data = 2 and Max_Data = 7. 
+                            This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
+
+}RCC_PLLI2SInitTypeDef;
+ 
+/** 
+  * @brief  RCC extended clocks structure definition  
+  */
+typedef struct
+{
+  uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
+                                      This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
+
+  RCC_PLLI2SInitTypeDef PLLI2S;  /*!< PLL I2S structure parameters.
+                                      This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
+
+  uint32_t RTCClockSelection;      /*!< Specifies RTC Clock Prescalers Selection.
+                                       This parameter can be a value of @ref RCC_RTC_Clock_Source */
+#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) 
+  uint8_t TIMPresSelection;        /*!< Specifies TIM Clock Source Selection. 
+                                      This parameter can be a value of @ref RCCEx_TIM_PRescaler_Selection */
+#endif /* STM32F401xC || STM32F401xE || STM32F411xE */
+}RCC_PeriphCLKInitTypeDef;
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE || STM32F411xE */
+/**
+  * @}
+  */ 
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants
+  * @{
+  */
+
+/** @defgroup RCCEx_Periph_Clock_Selection RCC Periph Clock Selection
+  * @{
+  */
+/* Peripheral Clock source for STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx */
+#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) ||\
+    defined(STM32F413xx) || defined(STM32F423xx)
+#define RCC_PERIPHCLK_I2S_APB1        0x00000001U
+#define RCC_PERIPHCLK_I2S_APB2        0x00000002U
+#define RCC_PERIPHCLK_TIM             0x00000004U
+#define RCC_PERIPHCLK_RTC             0x00000008U
+#define RCC_PERIPHCLK_FMPI2C1         0x00000010U
+#define RCC_PERIPHCLK_CLK48           0x00000020U
+#define RCC_PERIPHCLK_SDIO            0x00000040U
+#define RCC_PERIPHCLK_PLLI2S          0x00000080U
+#define RCC_PERIPHCLK_DFSDM1          0x00000100U
+#define RCC_PERIPHCLK_DFSDM1_AUDIO    0x00000200U
+#endif /* STM32F412Zx || STM32F412Vx) || STM32F412Rx || STM32F412Cx */
+#if defined(STM32F413xx) || defined(STM32F423xx)
+#define RCC_PERIPHCLK_DFSDM2          0x00000400U
+#define RCC_PERIPHCLK_DFSDM2_AUDIO    0x00000800U
+#define RCC_PERIPHCLK_LPTIM1          0x00001000U
+#define RCC_PERIPHCLK_SAIA            0x00002000U
+#define RCC_PERIPHCLK_SAIB            0x00004000U
+#endif /* STM32F413xx || STM32F423xx */
+/*----------------------------------------------------------------------------*/
+
+/*------------------- Peripheral Clock source for STM32F410xx ----------------*/
+#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
+#define RCC_PERIPHCLK_I2S             0x00000001U
+#define RCC_PERIPHCLK_TIM             0x00000002U
+#define RCC_PERIPHCLK_RTC             0x00000004U
+#define RCC_PERIPHCLK_FMPI2C1         0x00000008U
+#define RCC_PERIPHCLK_LPTIM1          0x00000010U
+#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
+/*----------------------------------------------------------------------------*/
+
+/*------------------- Peripheral Clock source for STM32F446xx ----------------*/
+#if defined(STM32F446xx)
+#define RCC_PERIPHCLK_I2S_APB1        0x00000001U
+#define RCC_PERIPHCLK_I2S_APB2        0x00000002U
+#define RCC_PERIPHCLK_SAI1            0x00000004U
+#define RCC_PERIPHCLK_SAI2            0x00000008U
+#define RCC_PERIPHCLK_TIM             0x00000010U
+#define RCC_PERIPHCLK_RTC             0x00000020U
+#define RCC_PERIPHCLK_CEC             0x00000040U
+#define RCC_PERIPHCLK_FMPI2C1         0x00000080U
+#define RCC_PERIPHCLK_CLK48           0x00000100U
+#define RCC_PERIPHCLK_SDIO            0x00000200U
+#define RCC_PERIPHCLK_SPDIFRX         0x00000400U
+#define RCC_PERIPHCLK_PLLI2S          0x00000800U
+#endif /* STM32F446xx */
+/*-----------------------------------------------------------------------------*/
+    
+/*----------- Peripheral Clock source for STM32F469xx/STM32F479xx -------------*/
+#if defined(STM32F469xx) || defined(STM32F479xx)
+#define RCC_PERIPHCLK_I2S             0x00000001U
+#define RCC_PERIPHCLK_SAI_PLLI2S      0x00000002U
+#define RCC_PERIPHCLK_SAI_PLLSAI      0x00000004U
+#define RCC_PERIPHCLK_LTDC            0x00000008U
+#define RCC_PERIPHCLK_TIM             0x00000010U
+#define RCC_PERIPHCLK_RTC             0x00000020U
+#define RCC_PERIPHCLK_PLLI2S          0x00000040U
+#define RCC_PERIPHCLK_CLK48           0x00000080U
+#define RCC_PERIPHCLK_SDIO            0x00000100U
+#endif /* STM32F469xx || STM32F479xx */
+/*----------------------------------------------------------------------------*/
+
+/*-------- Peripheral Clock source for STM32F42xxx/STM32F43xxx ---------------*/
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
+#define RCC_PERIPHCLK_I2S             0x00000001U
+#define RCC_PERIPHCLK_SAI_PLLI2S      0x00000002U
+#define RCC_PERIPHCLK_SAI_PLLSAI      0x00000004U
+#define RCC_PERIPHCLK_LTDC            0x00000008U
+#define RCC_PERIPHCLK_TIM             0x00000010U
+#define RCC_PERIPHCLK_RTC             0x00000020U
+#define RCC_PERIPHCLK_PLLI2S          0x00000040U
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+/*----------------------------------------------------------------------------*/
+
+/*-------- Peripheral Clock source for STM32F40xxx/STM32F41xxx ---------------*/
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx) ||\
+    defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) 
+#define RCC_PERIPHCLK_I2S             0x00000001U
+#define RCC_PERIPHCLK_RTC             0x00000002U
+#define RCC_PERIPHCLK_PLLI2S          0x00000004U
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE || STM32F411xE */
+#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE)
+#define RCC_PERIPHCLK_TIM             0x00000008U
+#endif /* STM32F401xC || STM32F401xE || STM32F411xE */      
+/*----------------------------------------------------------------------------*/
+/**
+  * @}
+  */
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \
+    defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
+    defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F469xx) || \
+    defined(STM32F479xx) 
+/** @defgroup RCCEx_I2S_Clock_Source I2S Clock Source
+  * @{
+  */
+#define RCC_I2SCLKSOURCE_PLLI2S         0x00000000U
+#define RCC_I2SCLKSOURCE_EXT            0x00000001U
+/**
+  * @}
+  */
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||
+          STM32F401xC || STM32F401xE || STM32F411xE || STM32F469xx || STM32F479xx */
+
+/** @defgroup RCCEx_PLLSAI_DIVR RCC PLLSAI DIVR
+  * @{
+  */
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx) ||\
+    defined(STM32F469xx) || defined(STM32F479xx) 
+#define RCC_PLLSAIDIVR_2                0x00000000U
+#define RCC_PLLSAIDIVR_4                0x00010000U
+#define RCC_PLLSAIDIVR_8                0x00020000U
+#define RCC_PLLSAIDIVR_16               0x00030000U
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_PLLI2SP_Clock_Divider RCC PLLI2SP Clock Divider
+  * @{
+  */
+#if defined(STM32F446xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
+    defined(STM32F412Rx) || defined(STM32F412Cx)
+#define RCC_PLLI2SP_DIV2                  0x00000002U
+#define RCC_PLLI2SP_DIV4                  0x00000004U
+#define RCC_PLLI2SP_DIV6                  0x00000006U
+#define RCC_PLLI2SP_DIV8                  0x00000008U
+#endif /* STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_PLLSAIP_Clock_Divider RCC PLLSAIP Clock Divider
+  * @{
+  */
+#if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) 
+#define RCC_PLLSAIP_DIV2                  0x00000002U
+#define RCC_PLLSAIP_DIV4                  0x00000004U
+#define RCC_PLLSAIP_DIV6                  0x00000006U
+#define RCC_PLLSAIP_DIV8                  0x00000008U
+#endif /* STM32F446xx || STM32F469xx || STM32F479xx */
+/**
+  * @}
+  */
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
+/** @defgroup RCCEx_SAI_BlockA_Clock_Source  RCC SAI BlockA Clock Source
+  * @{
+  */
+#define RCC_SAIACLKSOURCE_PLLSAI             0x00000000U
+#define RCC_SAIACLKSOURCE_PLLI2S             0x00100000U
+#define RCC_SAIACLKSOURCE_EXT                0x00200000U
+/**
+  * @}
+  */ 
+
+/** @defgroup RCCEx_SAI_BlockB_Clock_Source  RCC SAI BlockB Clock Source
+  * @{
+  */
+#define RCC_SAIBCLKSOURCE_PLLSAI             0x00000000U
+#define RCC_SAIBCLKSOURCE_PLLI2S             0x00400000U
+#define RCC_SAIBCLKSOURCE_EXT                0x00800000U
+/**
+  * @}
+  */ 
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
+      
+#if defined(STM32F469xx) || defined(STM32F479xx)
+/** @defgroup RCCEx_CLK48_Clock_Source  RCC CLK48 Clock Source
+  * @{
+  */
+#define RCC_CLK48CLKSOURCE_PLLQ              0x00000000U
+#define RCC_CLK48CLKSOURCE_PLLSAIP           ((uint32_t)RCC_DCKCFGR_CK48MSEL)
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_SDIO_Clock_Source  RCC SDIO Clock Source
+  * @{
+  */
+#define RCC_SDIOCLKSOURCE_CLK48             0x00000000U
+#define RCC_SDIOCLKSOURCE_SYSCLK            ((uint32_t)RCC_DCKCFGR_SDIOSEL)
+/**
+  * @}
+  */    
+  
+/** @defgroup RCCEx_DSI_Clock_Source  RCC DSI Clock Source
+  * @{
+  */
+#define RCC_DSICLKSOURCE_DSIPHY             0x00000000U
+#define RCC_DSICLKSOURCE_PLLR               ((uint32_t)RCC_DCKCFGR_DSISEL)
+/**
+  * @}
+  */
+#endif /* STM32F469xx || STM32F479xx */
+
+#if defined(STM32F446xx)
+/** @defgroup RCCEx_SAI1_Clock_Source RCC SAI1 Clock Source 
+  * @{
+  */
+#define RCC_SAI1CLKSOURCE_PLLSAI             0x00000000U
+#define RCC_SAI1CLKSOURCE_PLLI2S             ((uint32_t)RCC_DCKCFGR_SAI1SRC_0)
+#define RCC_SAI1CLKSOURCE_PLLR               ((uint32_t)RCC_DCKCFGR_SAI1SRC_1)
+#define RCC_SAI1CLKSOURCE_EXT                ((uint32_t)RCC_DCKCFGR_SAI1SRC)
+/**
+  * @}
+  */ 
+
+/** @defgroup RCCEx_SAI2_Clock_Source  RCC SAI2 Clock Source
+  * @{
+  */
+#define RCC_SAI2CLKSOURCE_PLLSAI             0x00000000U
+#define RCC_SAI2CLKSOURCE_PLLI2S             ((uint32_t)RCC_DCKCFGR_SAI2SRC_0)
+#define RCC_SAI2CLKSOURCE_PLLR               ((uint32_t)RCC_DCKCFGR_SAI2SRC_1)
+#define RCC_SAI2CLKSOURCE_PLLSRC             ((uint32_t)RCC_DCKCFGR_SAI2SRC)
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_I2SAPB1_Clock_Source  RCC I2S APB1 Clock Source
+  * @{
+  */
+#define RCC_I2SAPB1CLKSOURCE_PLLI2S          0x00000000U
+#define RCC_I2SAPB1CLKSOURCE_EXT             ((uint32_t)RCC_DCKCFGR_I2S1SRC_0)
+#define RCC_I2SAPB1CLKSOURCE_PLLR            ((uint32_t)RCC_DCKCFGR_I2S1SRC_1)
+#define RCC_I2SAPB1CLKSOURCE_PLLSRC          ((uint32_t)RCC_DCKCFGR_I2S1SRC)
+/**
+  * @}
+  */ 
+
+/** @defgroup RCCEx_I2SAPB2_Clock_Source  RCC I2S APB2 Clock Source
+  * @{
+  */
+#define RCC_I2SAPB2CLKSOURCE_PLLI2S          0x00000000U
+#define RCC_I2SAPB2CLKSOURCE_EXT             ((uint32_t)RCC_DCKCFGR_I2S2SRC_0)
+#define RCC_I2SAPB2CLKSOURCE_PLLR            ((uint32_t)RCC_DCKCFGR_I2S2SRC_1)
+#define RCC_I2SAPB2CLKSOURCE_PLLSRC          ((uint32_t)RCC_DCKCFGR_I2S2SRC)
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_FMPI2C1_Clock_Source  RCC FMPI2C1 Clock Source
+  * @{
+  */
+#define RCC_FMPI2C1CLKSOURCE_PCLK1            0x00000000U
+#define RCC_FMPI2C1CLKSOURCE_SYSCLK           ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_0)
+#define RCC_FMPI2C1CLKSOURCE_HSI              ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_1)
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_CEC_Clock_Source  RCC CEC Clock Source
+  * @{
+  */
+#define RCC_CECCLKSOURCE_HSI                0x00000000U
+#define RCC_CECCLKSOURCE_LSE                ((uint32_t)RCC_DCKCFGR2_CECSEL)
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_CLK48_Clock_Source  RCC CLK48 Clock Source
+  * @{
+  */
+#define RCC_CLK48CLKSOURCE_PLLQ              0x00000000U
+#define RCC_CLK48CLKSOURCE_PLLSAIP           ((uint32_t)RCC_DCKCFGR2_CK48MSEL)
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_SDIO_Clock_Source  RCC SDIO Clock Source
+  * @{
+  */
+#define RCC_SDIOCLKSOURCE_CLK48             0x00000000U
+#define RCC_SDIOCLKSOURCE_SYSCLK            ((uint32_t)RCC_DCKCFGR2_SDIOSEL)
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_SPDIFRX_Clock_Source   RCC SPDIFRX Clock Source
+  * @{
+  */
+#define RCC_SPDIFRXCLKSOURCE_PLLR           0x00000000U
+#define RCC_SPDIFRXCLKSOURCE_PLLI2SP        ((uint32_t)RCC_DCKCFGR2_SPDIFRXSEL)
+/**
+  * @}
+  */
+
+#endif /* STM32F446xx */
+
+#if defined(STM32F413xx) || defined(STM32F423xx)
+/** @defgroup RCCEx_SAI1_BlockA_Clock_Source  RCC SAI BlockA Clock Source
+  * @{
+  */
+#define RCC_SAIACLKSOURCE_PLLI2SR            0x00000000U
+#define RCC_SAIACLKSOURCE_EXT                ((uint32_t)RCC_DCKCFGR_SAI1ASRC_0)
+#define RCC_SAIACLKSOURCE_PLLR               ((uint32_t)RCC_DCKCFGR_SAI1ASRC_1)
+#define RCC_SAIACLKSOURCE_PLLSRC             ((uint32_t)RCC_DCKCFGR_SAI1ASRC_0 | RCC_DCKCFGR_SAI1ASRC_1)
+/**
+  * @}
+  */ 
+
+/** @defgroup RCCEx_SAI1_BlockB_Clock_Source  RCC SAI BlockB Clock Source
+  * @{
+  */
+#define RCC_SAIBCLKSOURCE_PLLI2SR            0x00000000U
+#define RCC_SAIBCLKSOURCE_EXT                ((uint32_t)RCC_DCKCFGR_SAI1BSRC_0)
+#define RCC_SAIBCLKSOURCE_PLLR               ((uint32_t)RCC_DCKCFGR_SAI1BSRC_1)
+#define RCC_SAIBCLKSOURCE_PLLSRC             ((uint32_t)RCC_DCKCFGR_SAI1BSRC_0 | RCC_DCKCFGR_SAI1BSRC_1)
+/**
+  * @}
+  */ 
+      
+/** @defgroup RCCEx_LPTIM1_Clock_Source  RCC LPTIM1 Clock Source
+  * @{
+  */
+#define RCC_LPTIM1CLKSOURCE_PCLK1           0x00000000U
+#define RCC_LPTIM1CLKSOURCE_HSI             ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_0)
+#define RCC_LPTIM1CLKSOURCE_LSI             ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_1)
+#define RCC_LPTIM1CLKSOURCE_LSE             ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_0 | RCC_DCKCFGR2_LPTIM1SEL_1)
+/**
+  * @}
+  */
+      
+
+/** @defgroup RCCEx_DFSDM2_Audio_Clock_Source  RCC DFSDM2 Audio Clock Source
+  * @{
+  */
+#define RCC_DFSDM2AUDIOCLKSOURCE_I2S1       0x00000000U
+#define RCC_DFSDM2AUDIOCLKSOURCE_I2S2       ((uint32_t)RCC_DCKCFGR_CKDFSDM2ASEL)
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_DFSDM2_Kernel_Clock_Source  RCC DFSDM2 Kernel Clock Source
+  * @{
+  */
+#define RCC_DFSDM2CLKSOURCE_PCLK2           0x00000000U
+#define RCC_DFSDM2CLKSOURCE_SYSCLK          ((uint32_t)RCC_DCKCFGR_CKDFSDM1SEL)
+/**
+  * @}
+  */
+
+#endif /* STM32F413xx || STM32F423xx */
+
+#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
+/** @defgroup RCCEx_PLL_I2S_Clock_Source PLL I2S Clock Source
+  * @{
+  */
+#define RCC_PLLI2SCLKSOURCE_PLLSRC          0x00000000U 
+#define RCC_PLLI2SCLKSOURCE_EXT             ((uint32_t)RCC_PLLI2SCFGR_PLLI2SSRC)
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_DFSDM1_Audio_Clock_Source  RCC DFSDM1 Audio Clock Source
+  * @{
+  */
+#define RCC_DFSDM1AUDIOCLKSOURCE_I2S1       0x00000000U
+#define RCC_DFSDM1AUDIOCLKSOURCE_I2S2       ((uint32_t)RCC_DCKCFGR_CKDFSDM1ASEL)
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_DFSDM1_Kernel_Clock_Source  RCC DFSDM1 Kernel Clock Source
+  * @{
+  */
+#define RCC_DFSDM1CLKSOURCE_PCLK2           0x00000000U
+#define RCC_DFSDM1CLKSOURCE_SYSCLK          ((uint32_t)RCC_DCKCFGR_CKDFSDM1SEL)
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_I2SAPB1_Clock_Source  RCC I2S APB1 Clock Source
+  * @{
+  */
+#define RCC_I2SAPB1CLKSOURCE_PLLI2S         0x00000000U
+#define RCC_I2SAPB1CLKSOURCE_EXT            ((uint32_t)RCC_DCKCFGR_I2S1SRC_0)
+#define RCC_I2SAPB1CLKSOURCE_PLLR           ((uint32_t)RCC_DCKCFGR_I2S1SRC_1)
+#define RCC_I2SAPB1CLKSOURCE_PLLSRC         ((uint32_t)RCC_DCKCFGR_I2S1SRC)
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_I2SAPB2_Clock_Source  RCC I2S APB2 Clock Source
+  * @{
+  */
+#define RCC_I2SAPB2CLKSOURCE_PLLI2S         0x00000000U
+#define RCC_I2SAPB2CLKSOURCE_EXT            ((uint32_t)RCC_DCKCFGR_I2S2SRC_0)
+#define RCC_I2SAPB2CLKSOURCE_PLLR           ((uint32_t)RCC_DCKCFGR_I2S2SRC_1)
+#define RCC_I2SAPB2CLKSOURCE_PLLSRC         ((uint32_t)RCC_DCKCFGR_I2S2SRC)
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_FMPI2C1_Clock_Source  RCC FMPI2C1 Clock Source
+  * @{
+  */
+#define RCC_FMPI2C1CLKSOURCE_PCLK1          0x00000000U
+#define RCC_FMPI2C1CLKSOURCE_SYSCLK         ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_0)
+#define RCC_FMPI2C1CLKSOURCE_HSI            ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_1)
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_CLK48_Clock_Source  RCC CLK48 Clock Source
+  * @{
+  */
+#define RCC_CLK48CLKSOURCE_PLLQ             0x00000000U
+#define RCC_CLK48CLKSOURCE_PLLI2SQ          ((uint32_t)RCC_DCKCFGR2_CK48MSEL)
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_SDIO_Clock_Source  RCC SDIO Clock Source
+  * @{
+  */
+#define RCC_SDIOCLKSOURCE_CLK48             0x00000000U
+#define RCC_SDIOCLKSOURCE_SYSCLK            ((uint32_t)RCC_DCKCFGR2_SDIOSEL)
+/**
+  * @}
+  */
+#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */
+
+#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
+
+/** @defgroup RCCEx_I2S_APB_Clock_Source  RCC I2S APB Clock Source
+  * @{
+  */
+#define RCC_I2SAPBCLKSOURCE_PLLR            0x00000000U
+#define RCC_I2SAPBCLKSOURCE_EXT             ((uint32_t)RCC_DCKCFGR_I2SSRC_0)
+#define RCC_I2SAPBCLKSOURCE_PLLSRC          ((uint32_t)RCC_DCKCFGR_I2SSRC_1)
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_FMPI2C1_Clock_Source  RCC FMPI2C1 Clock Source
+  * @{
+  */
+#define RCC_FMPI2C1CLKSOURCE_PCLK1              0x00000000U
+#define RCC_FMPI2C1CLKSOURCE_SYSCLK             ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_0)
+#define RCC_FMPI2C1CLKSOURCE_HSI                ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_1)
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_LPTIM1_Clock_Source  RCC LPTIM1 Clock Source
+  * @{
+  */
+#define RCC_LPTIM1CLKSOURCE_PCLK1          0x00000000U
+#define RCC_LPTIM1CLKSOURCE_HSI            ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_0)
+#define RCC_LPTIM1CLKSOURCE_LSI            ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_1)
+#define RCC_LPTIM1CLKSOURCE_LSE            ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_0 | RCC_DCKCFGR2_LPTIM1SEL_1)
+/**
+  * @}
+  */
+#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
+    defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) ||\
+    defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F469xx) ||\
+    defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) ||\
+    defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
+/** @defgroup RCCEx_TIM_PRescaler_Selection  RCC TIM PRescaler Selection
+  * @{
+  */
+#define RCC_TIMPRES_DESACTIVATED        ((uint8_t)0x00)
+#define RCC_TIMPRES_ACTIVATED           ((uint8_t)0x01)
+/**
+  * @}
+  */
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F401xC || STM32F401xE ||\
+          STM32F410xx || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx ||\
+          STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */
+
+#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F411xE) ||\
+    defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) ||\
+    defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) ||\
+    defined(STM32F423xx)
+/** @defgroup RCCEx_LSE_Dual_Mode_Selection  RCC LSE Dual Mode Selection
+  * @{
+  */
+#define RCC_LSE_LOWPOWER_MODE           ((uint8_t)0x00)
+#define RCC_LSE_HIGHDRIVE_MODE          ((uint8_t)0x01)
+/**
+  * @}
+  */
+#endif /* STM32F410xx || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx ||\
+          STM32F412Rx || STM32F412Cx */
+
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \
+    defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
+    defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \
+    defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
+    defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx)
+/** @defgroup RCC_MCO2_Clock_Source MCO2 Clock Source
+  * @{
+  */
+#define RCC_MCO2SOURCE_SYSCLK            0x00000000U
+#define RCC_MCO2SOURCE_PLLI2SCLK         RCC_CFGR_MCO2_0
+#define RCC_MCO2SOURCE_HSE               RCC_CFGR_MCO2_1
+#define RCC_MCO2SOURCE_PLLCLK            RCC_CFGR_MCO2
+/**
+  * @}
+  */
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||
+          STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx ||
+          STM32F412Rx || STM32F413xx | STM32F423xx */
+
+#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
+/** @defgroup RCC_MCO2_Clock_Source MCO2 Clock Source
+  * @{
+  */
+#define RCC_MCO2SOURCE_SYSCLK            0x00000000U
+#define RCC_MCO2SOURCE_I2SCLK            RCC_CFGR_MCO2_0
+#define RCC_MCO2SOURCE_HSE               RCC_CFGR_MCO2_1
+#define RCC_MCO2SOURCE_PLLCLK            RCC_CFGR_MCO2
+/**
+  * @}
+  */
+#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
+
+/**
+  * @}
+  */
+     
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros
+  * @{
+  */
+/*------------------- STM32F42xxx/STM32F43xxx/STM32F469xx/STM32F479xx --------*/
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
+/** @defgroup RCCEx_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable
+  * @brief  Enables or disables the AHB1 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before 
+  *         using it.
+  * @{
+  */
+#define __HAL_RCC_BKPSRAM_CLK_ENABLE() do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
+                                        UNUSED(tmpreg); \
+                                        } while(0U)
+#define __HAL_RCC_CCMDATARAMEN_CLK_ENABLE() do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\
+                                        UNUSED(tmpreg); \
+                                        } while(0U)
+#define __HAL_RCC_CRC_CLK_ENABLE()     do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
+                                        UNUSED(tmpreg); \
+                                        } while(0U)
+#define __HAL_RCC_GPIOD_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
+                                        UNUSED(tmpreg); \
+                                        } while(0U)
+#define __HAL_RCC_GPIOE_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
+                                        UNUSED(tmpreg); \
+                                        } while(0U)
+#define __HAL_RCC_GPIOI_CLK_ENABLE()    do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\
+                                        UNUSED(tmpreg); \
+                                        } while(0U)
+#define __HAL_RCC_GPIOF_CLK_ENABLE()    do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
+                                        UNUSED(tmpreg); \
+                                        } while(0U)
+#define __HAL_RCC_GPIOG_CLK_ENABLE()    do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
+                                        UNUSED(tmpreg); \
+                                        } while(0U)
+#define __HAL_RCC_GPIOJ_CLK_ENABLE()    do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOJEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOJEN);\
+                                        UNUSED(tmpreg); \
+                                        } while(0U)
+#define __HAL_RCC_GPIOK_CLK_ENABLE()    do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOKEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOKEN);\
+                                        UNUSED(tmpreg); \
+                                        } while(0U)
+#define __HAL_RCC_DMA2D_CLK_ENABLE()    do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN);\
+                                        UNUSED(tmpreg); \
+                                        } while(0U)
+#define __HAL_RCC_ETHMAC_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\
+                                        UNUSED(tmpreg); \
+                                        } while(0U)
+#define __HAL_RCC_ETHMACTX_CLK_ENABLE() do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\
+                                        UNUSED(tmpreg); \
+                                        } while(0U)
+#define __HAL_RCC_ETHMACRX_CLK_ENABLE() do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\
+                                         UNUSED(tmpreg); \
+                                         } while(0U)
+#define __HAL_RCC_ETHMACPTP_CLK_ENABLE() do { \
+                                         __IO uint32_t tmpreg = 0x00U; \
+                                         SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\
+                                         /* Delay after an RCC peripheral clock enabling */ \
+                                         tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\
+                                         UNUSED(tmpreg); \
+                                         } while(0U)
+#define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\
+                                        UNUSED(tmpreg); \
+                                        } while(0U)
+#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\
+                                        UNUSED(tmpreg); \
+                                        } while(0U)
+#define __HAL_RCC_GPIOD_CLK_DISABLE()           (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN))
+#define __HAL_RCC_GPIOE_CLK_DISABLE()           (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN))
+#define __HAL_RCC_GPIOF_CLK_DISABLE()           (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN))
+#define __HAL_RCC_GPIOG_CLK_DISABLE()           (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN))
+#define __HAL_RCC_GPIOI_CLK_DISABLE()           (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOIEN))
+#define __HAL_RCC_GPIOJ_CLK_DISABLE()           (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOJEN))
+#define __HAL_RCC_GPIOK_CLK_DISABLE()           (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOKEN))
+#define __HAL_RCC_DMA2D_CLK_DISABLE()           (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA2DEN))
+#define __HAL_RCC_ETHMAC_CLK_DISABLE()          (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACEN))
+#define __HAL_RCC_ETHMACTX_CLK_DISABLE()        (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACTXEN))
+#define __HAL_RCC_ETHMACRX_CLK_DISABLE()        (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACRXEN))
+#define __HAL_RCC_ETHMACPTP_CLK_DISABLE()       (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACPTPEN))
+#define __HAL_RCC_USB_OTG_HS_CLK_DISABLE()      (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSEN))
+#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSULPIEN))
+#define __HAL_RCC_BKPSRAM_CLK_DISABLE()         (RCC->AHB1ENR &= ~(RCC_AHB1ENR_BKPSRAMEN))
+#define __HAL_RCC_CCMDATARAMEN_CLK_DISABLE()    (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CCMDATARAMEN))
+#define __HAL_RCC_CRC_CLK_DISABLE()             (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN))
+
+/**
+  * @brief  Enable ETHERNET clock.
+  */
+#define __HAL_RCC_ETH_CLK_ENABLE() do {                                     \
+                                        __HAL_RCC_ETHMAC_CLK_ENABLE();      \
+                                        __HAL_RCC_ETHMACTX_CLK_ENABLE();    \
+                                        __HAL_RCC_ETHMACRX_CLK_ENABLE();    \
+                                      } while(0U)
+/**
+  * @brief  Disable ETHERNET clock.
+  */
+#define __HAL_RCC_ETH_CLK_DISABLE()  do {                                      \
+                                          __HAL_RCC_ETHMACTX_CLK_DISABLE();    \
+                                          __HAL_RCC_ETHMACRX_CLK_DISABLE();    \
+                                          __HAL_RCC_ETHMAC_CLK_DISABLE();      \
+                                        } while(0U)
+/**
+  * @}
+  */
+  
+/** @defgroup RCCEx_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status
+  * @brief  Get the enable or disable status of the AHB1 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  * @{
+  */
+#define __HAL_RCC_GPIOD_IS_CLK_ENABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) != RESET) 
+#define __HAL_RCC_GPIOE_IS_CLK_ENABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) != RESET) 
+#define __HAL_RCC_GPIOF_IS_CLK_ENABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) != RESET) 
+#define __HAL_RCC_GPIOG_IS_CLK_ENABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) != RESET)
+#define __HAL_RCC_GPIOI_IS_CLK_ENABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOIEN)) != RESET) 
+#define __HAL_RCC_GPIOJ_IS_CLK_ENABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOJEN)) != RESET) 
+#define __HAL_RCC_GPIOK_IS_CLK_ENABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOKEN)) != RESET)
+#define __HAL_RCC_DMA2D_IS_CLK_ENABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2DEN)) != RESET) 
+#define __HAL_RCC_ETHMAC_IS_CLK_ENABLED()          ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACEN)) != RESET) 
+#define __HAL_RCC_ETHMACTX_IS_CLK_ENABLED()        ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACTXEN)) != RESET)
+#define __HAL_RCC_ETHMACRX_IS_CLK_ENABLED()        ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACRXEN)) != RESET)
+#define __HAL_RCC_ETHMACPTP_IS_CLK_ENABLED()       ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACPTPEN)) != RESET)
+#define __HAL_RCC_USB_OTG_HS_IS_CLK_ENABLED()      ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) != RESET)
+#define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN)) != RESET)
+#define __HAL_RCC_BKPSRAM_IS_CLK_ENABLED()         ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) != RESET)
+#define __HAL_RCC_CCMDATARAMEN_IS_CLK_ENABLED()    ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) != RESET) 
+#define __HAL_RCC_CRC_IS_CLK_ENABLED()             ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET)
+#define __HAL_RCC_ETH_IS_CLK_ENABLED()             (__HAL_RCC_ETHMAC_IS_CLK_ENABLED()   && \
+                                                    __HAL_RCC_ETHMACTX_IS_CLK_ENABLED() && \
+                                                    __HAL_RCC_ETHMACRX_IS_CLK_ENABLED()) 
+
+#define __HAL_RCC_GPIOD_IS_CLK_DISABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) == RESET) 
+#define __HAL_RCC_GPIOE_IS_CLK_DISABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) == RESET) 
+#define __HAL_RCC_GPIOF_IS_CLK_DISABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) == RESET) 
+#define __HAL_RCC_GPIOG_IS_CLK_DISABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) == RESET)
+#define __HAL_RCC_GPIOI_IS_CLK_DISABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOIEN)) == RESET) 
+#define __HAL_RCC_GPIOJ_IS_CLK_DISABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOJEN)) == RESET) 
+#define __HAL_RCC_GPIOK_IS_CLK_DISABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOKEN)) == RESET)
+#define __HAL_RCC_DMA2D_IS_CLK_DISABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2DEN)) == RESET) 
+#define __HAL_RCC_ETHMAC_IS_CLK_DISABLED()          ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACEN)) == RESET) 
+#define __HAL_RCC_ETHMACTX_IS_CLK_DISABLED()        ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACTXEN)) == RESET)
+#define __HAL_RCC_ETHMACRX_IS_CLK_DISABLED()        ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACRXEN)) == RESET)
+#define __HAL_RCC_ETHMACPTP_IS_CLK_DISABLED()       ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACPTPEN)) == RESET)
+#define __HAL_RCC_USB_OTG_HS_IS_CLK_DISABLED()      ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) == RESET)
+#define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN)) == RESET)
+#define __HAL_RCC_BKPSRAM_IS_CLK_DISABLED()         ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) == RESET)
+#define __HAL_RCC_CCMDATARAMEN_IS_CLK_DISABLED()    ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) == RESET) 
+#define __HAL_RCC_CRC_IS_CLK_DISABLED()             ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET)
+#define __HAL_RCC_ETH_IS_CLK_DISABLED()             (__HAL_RCC_ETHMAC_IS_CLK_DISABLED()   && \
+                                                     __HAL_RCC_ETHMACTX_IS_CLK_DISABLED() && \
+                                                     __HAL_RCC_ETHMACRX_IS_CLK_DISABLED())
+/**
+  * @}
+  */
+  
+/** @defgroup RCCEx_AHB2_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable
+  * @brief  Enable or disable the AHB2 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before 
+  *         using it.
+  * @{
+  */
+ #define __HAL_RCC_DCMI_CLK_ENABLE()   do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_DCMI_CLK_DISABLE()  (RCC->AHB2ENR &= ~(RCC_AHB2ENR_DCMIEN))
+
+#if defined(STM32F437xx)|| defined(STM32F439xx) || defined(STM32F479xx)
+#define __HAL_RCC_CRYP_CLK_ENABLE()   do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_HASH_CLK_ENABLE()   do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0U)
+
+#define __HAL_RCC_CRYP_CLK_DISABLE()  (RCC->AHB2ENR &= ~(RCC_AHB2ENR_CRYPEN))
+#define __HAL_RCC_HASH_CLK_DISABLE()  (RCC->AHB2ENR &= ~(RCC_AHB2ENR_HASHEN))
+#endif /* STM32F437xx || STM32F439xx || STM32F479xx */
+
+#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE()  do {(RCC->AHB2ENR |= (RCC_AHB2ENR_OTGFSEN));\
+                                               __HAL_RCC_SYSCFG_CLK_ENABLE();\
+                                              }while(0U)
+                                        
+#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN))
+
+#define __HAL_RCC_RNG_CLK_ENABLE()    do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
+                                        UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_RNG_CLK_DISABLE()   (RCC->AHB2ENR &= ~(RCC_AHB2ENR_RNGEN))
+/**
+  * @}
+  */
+  
+/** @defgroup RCCEx_AHB2_Peripheral_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enable Disable Status
+  * @brief  Get the enable or disable status of the AHB1 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  * @{
+  */ 
+#define __HAL_RCC_DCMI_IS_CLK_ENABLED()        ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) != RESET)
+#define __HAL_RCC_DCMI_IS_CLK_DISABLED()       ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) == RESET)
+
+#if defined(STM32F437xx)|| defined(STM32F439xx) || defined(STM32F479xx)
+#define __HAL_RCC_CRYP_IS_CLK_ENABLED()        ((RCC->AHB2ENR & (RCC_AHB2ENR_CRYPEN)) != RESET)
+#define __HAL_RCC_CRYP_IS_CLK_DISABLED()       ((RCC->AHB2ENR & (RCC_AHB2ENR_CRYPEN)) == RESET)
+
+#define __HAL_RCC_HASH_IS_CLK_ENABLED()        ((RCC->AHB2ENR & (RCC_AHB2ENR_HASHEN)) != RESET)
+#define __HAL_RCC_HASH_IS_CLK_DISABLED()       ((RCC->AHB2ENR & (RCC_AHB2ENR_HASHEN)) == RESET)
+#endif /* STM32F437xx || STM32F439xx || STM32F479xx */
+
+#define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED()  ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) != RESET)
+#define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) == RESET)
+
+#define __HAL_RCC_RNG_IS_CLK_ENABLED()         ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) != RESET) 
+#define __HAL_RCC_RNG_IS_CLK_DISABLED()        ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) == RESET)     
+/**
+  * @}
+  */   
+
+/** @defgroup RCCEx_AHB3_Clock_Enable_Disable AHB3 Peripheral Clock Enable Disable
+  * @brief  Enables or disables the AHB3 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before 
+  *         using it.
+  * @{  
+  */
+#define __HAL_RCC_FMC_CLK_ENABLE()    do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_FMC_CLK_DISABLE()  (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FMCEN))
+#if defined(STM32F469xx) || defined(STM32F479xx)
+#define __HAL_RCC_QSPI_CLK_ENABLE()   do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_QSPI_CLK_DISABLE()  (RCC->AHB3ENR &= ~(RCC_AHB3ENR_QSPIEN))
+#endif /* STM32F469xx || STM32F479xx */
+/**
+  * @}
+  */
+
+
+/** @defgroup RCCEx_AHB3_Peripheral_Clock_Enable_Disable_Status AHB3 Peripheral Clock Enable Disable Status
+  * @brief  Get the enable or disable status of the AHB3 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  * @{
+  */
+#define __HAL_RCC_FMC_IS_CLK_ENABLED()   ((RCC->AHB3ENR & (RCC_AHB3ENR_FMCEN)) != RESET)
+#define __HAL_RCC_FMC_IS_CLK_DISABLED()  ((RCC->AHB3ENR & (RCC_AHB3ENR_FMCEN)) == RESET)
+#if defined(STM32F469xx) || defined(STM32F479xx)
+#define __HAL_RCC_QSPI_IS_CLK_ENABLED()  ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) != RESET)
+#define __HAL_RCC_QSPI_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) == RESET)
+#endif /* STM32F469xx || STM32F479xx */  
+/**
+  * @}
+  */
+    
+/** @defgroup RCCEx_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable
+  * @brief  Enable or disable the Low Speed APB (APB1) peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before 
+  *         using it.
+  * @{
+  */
+#define __HAL_RCC_TIM6_CLK_ENABLE()   do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_TIM7_CLK_ENABLE()   do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_TIM12_CLK_ENABLE()  do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_TIM13_CLK_ENABLE()  do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_TIM14_CLK_ENABLE()  do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_TIM14_CLK_ENABLE()  do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_USART3_CLK_ENABLE() do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_UART4_CLK_ENABLE()  do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_UART5_CLK_ENABLE()  do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_CAN1_CLK_ENABLE()   do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_CAN2_CLK_ENABLE()   do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_DAC_CLK_ENABLE()    do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_UART7_CLK_ENABLE()  do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART7EN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART7EN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_UART8_CLK_ENABLE()  do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART8EN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART8EN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_TIM2_CLK_ENABLE()     do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
+                                        UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_TIM3_CLK_ENABLE()     do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
+                                        UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_TIM4_CLK_ENABLE()     do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
+                                        UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_SPI3_CLK_ENABLE()     do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
+                                        UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_I2C3_CLK_ENABLE()     do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
+                                        UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_TIM2_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
+#define __HAL_RCC_TIM3_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
+#define __HAL_RCC_TIM4_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
+#define __HAL_RCC_SPI3_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
+#define __HAL_RCC_I2C3_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN))
+#define __HAL_RCC_TIM6_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
+#define __HAL_RCC_TIM7_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
+#define __HAL_RCC_TIM12_CLK_DISABLE()  (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN))
+#define __HAL_RCC_TIM13_CLK_DISABLE()  (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN))
+#define __HAL_RCC_TIM14_CLK_DISABLE()  (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))
+#define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
+#define __HAL_RCC_UART4_CLK_DISABLE()  (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))
+#define __HAL_RCC_UART5_CLK_DISABLE()  (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))
+#define __HAL_RCC_CAN1_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN))
+#define __HAL_RCC_CAN2_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN))
+#define __HAL_RCC_DAC_CLK_DISABLE()    (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
+#define __HAL_RCC_UART7_CLK_DISABLE()  (RCC->APB1ENR &= ~(RCC_APB1ENR_UART7EN))
+#define __HAL_RCC_UART8_CLK_DISABLE()  (RCC->APB1ENR &= ~(RCC_APB1ENR_UART8EN))
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status
+  * @brief  Get the enable or disable status of the APB1 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  * @{
+  */
+#define __HAL_RCC_TIM2_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET)  
+#define __HAL_RCC_TIM3_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET) 
+#define __HAL_RCC_TIM4_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET)
+#define __HAL_RCC_SPI3_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET) 
+#define __HAL_RCC_I2C3_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET)
+#define __HAL_RCC_TIM6_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET) 
+#define __HAL_RCC_TIM7_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET) 
+#define __HAL_RCC_TIM12_IS_CLK_ENABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) != RESET) 
+#define __HAL_RCC_TIM13_IS_CLK_ENABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET)  
+#define __HAL_RCC_TIM14_IS_CLK_ENABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET) 
+#define __HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET) 
+#define __HAL_RCC_UART4_IS_CLK_ENABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET) 
+#define __HAL_RCC_UART5_IS_CLK_ENABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != RESET) 
+#define __HAL_RCC_CAN1_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) != RESET)
+#define __HAL_RCC_CAN2_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) != RESET)
+#define __HAL_RCC_DAC_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET) 
+#define __HAL_RCC_UART7_IS_CLK_ENABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_UART7EN)) != RESET)
+#define __HAL_RCC_UART8_IS_CLK_ENABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_UART8EN)) != RESET) 
+
+#define __HAL_RCC_TIM2_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET)  
+#define __HAL_RCC_TIM3_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET) 
+#define __HAL_RCC_TIM4_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET)
+#define __HAL_RCC_SPI3_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET) 
+#define __HAL_RCC_I2C3_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET)
+#define __HAL_RCC_TIM6_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET) 
+#define __HAL_RCC_TIM7_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET) 
+#define __HAL_RCC_TIM12_IS_CLK_DISABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) == RESET) 
+#define __HAL_RCC_TIM13_IS_CLK_DISABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) == RESET)  
+#define __HAL_RCC_TIM14_IS_CLK_DISABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET) 
+#define __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET) 
+#define __HAL_RCC_UART4_IS_CLK_DISABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == RESET) 
+#define __HAL_RCC_UART5_IS_CLK_DISABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == RESET) 
+#define __HAL_RCC_CAN1_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) == RESET)
+#define __HAL_RCC_CAN2_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) == RESET)
+#define __HAL_RCC_DAC_IS_CLK_DISABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET) 
+#define __HAL_RCC_UART7_IS_CLK_DISABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_UART7EN)) == RESET)
+#define __HAL_RCC_UART8_IS_CLK_DISABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_UART8EN)) == RESET) 
+/**
+  * @}
+  */
+    
+/** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable
+  * @brief  Enable or disable the High Speed APB (APB2) peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before 
+  *         using it.
+  * @{
+  */
+#define __HAL_RCC_TIM8_CLK_ENABLE()   do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_ADC2_CLK_ENABLE()   do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_ADC3_CLK_ENABLE()   do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_SPI5_CLK_ENABLE()   do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_SPI6_CLK_ENABLE()   do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI6EN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI6EN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_SAI1_CLK_ENABLE()   do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_SDIO_CLK_ENABLE()     do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
+                                        UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_SPI4_CLK_ENABLE()     do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
+                                        UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_TIM10_CLK_ENABLE()    do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
+                                        UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_SDIO_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN))
+#define __HAL_RCC_SPI4_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN))
+#define __HAL_RCC_TIM10_CLK_DISABLE()  (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN))
+#define __HAL_RCC_TIM8_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN))
+#define __HAL_RCC_ADC2_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN))
+#define __HAL_RCC_ADC3_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN))
+#define __HAL_RCC_SPI5_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI5EN))
+#define __HAL_RCC_SPI6_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI6EN))
+#define __HAL_RCC_SAI1_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI1EN))
+
+#if defined(STM32F429xx)|| defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
+#define __HAL_RCC_LTDC_CLK_ENABLE()  do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0U)
+
+#define __HAL_RCC_LTDC_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_LTDCEN))
+#endif /* STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
+
+#if defined(STM32F469xx) || defined(STM32F479xx)
+#define __HAL_RCC_DSI_CLK_ENABLE() do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIEN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIEN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0U)
+
+#define __HAL_RCC_DSI_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_DSIEN))
+#endif /* STM32F469xx || STM32F479xx */
+/**
+  * @}
+  */
+  
+/** @defgroup RCCEx_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status
+  * @brief  Get the enable or disable status of the APB2 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  * @{
+  */  
+#define __HAL_RCC_TIM8_IS_CLK_ENABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) != RESET)
+#define __HAL_RCC_ADC2_IS_CLK_ENABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) != RESET)
+#define __HAL_RCC_ADC3_IS_CLK_ENABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) != RESET) 
+#define __HAL_RCC_SPI5_IS_CLK_ENABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) != RESET) 
+#define __HAL_RCC_SPI6_IS_CLK_ENABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_SPI6EN)) != RESET) 
+#define __HAL_RCC_SAI1_IS_CLK_ENABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) != RESET) 
+#define __HAL_RCC_SDIO_IS_CLK_ENABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) != RESET)
+#define __HAL_RCC_SPI4_IS_CLK_ENABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) != RESET)
+#define __HAL_RCC_TIM10_IS_CLK_ENABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN))!= RESET)  
+
+#define __HAL_RCC_SDIO_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) == RESET)
+#define __HAL_RCC_SPI4_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) == RESET)
+#define __HAL_RCC_TIM10_IS_CLK_DISABLED()  ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN))== RESET)
+#define __HAL_RCC_TIM8_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) == RESET)
+#define __HAL_RCC_ADC2_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) == RESET)
+#define __HAL_RCC_ADC3_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) == RESET)
+#define __HAL_RCC_SPI5_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) == RESET)
+#define __HAL_RCC_SPI6_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_SPI6EN)) == RESET)
+#define __HAL_RCC_SAI1_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) == RESET)
+
+#if defined(STM32F429xx)|| defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
+#define __HAL_RCC_LTDC_IS_CLK_ENABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_LTDCEN)) != RESET)
+#define __HAL_RCC_LTDC_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_LTDCEN)) == RESET)
+#endif /* STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
+
+#if defined(STM32F469xx) || defined(STM32F479xx)
+#define __HAL_RCC_DSI_IS_CLK_ENABLED()     ((RCC->APB2ENR & (RCC_APB2ENR_DSIEN)) != RESET)
+#define __HAL_RCC_DSI_IS_CLK_DISABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_DSIEN)) == RESET)
+#endif /* STM32F469xx || STM32F479xx */
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_AHB1_Force_Release_Reset AHB1 Force Release Reset 
+  * @brief  Force or release AHB1 peripheral reset.
+  * @{
+  */
+#define __HAL_RCC_GPIOD_FORCE_RESET()    (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIODRST))
+#define __HAL_RCC_GPIOE_FORCE_RESET()    (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOERST))
+#define __HAL_RCC_GPIOF_FORCE_RESET()    (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOFRST))
+#define __HAL_RCC_GPIOG_FORCE_RESET()    (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOGRST))
+#define __HAL_RCC_GPIOI_FORCE_RESET()    (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOIRST))
+#define __HAL_RCC_ETHMAC_FORCE_RESET()   (RCC->AHB1RSTR |= (RCC_AHB1RSTR_ETHMACRST))
+#define __HAL_RCC_USB_OTG_HS_FORCE_RESET()    (RCC->AHB1RSTR |= (RCC_AHB1RSTR_OTGHRST))
+#define __HAL_RCC_GPIOJ_FORCE_RESET()    (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOJRST))
+#define __HAL_RCC_GPIOK_FORCE_RESET()    (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOKRST))
+#define __HAL_RCC_DMA2D_FORCE_RESET()    (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA2DRST))
+#define __HAL_RCC_CRC_FORCE_RESET()      (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST))
+
+#define __HAL_RCC_GPIOD_RELEASE_RESET()  (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST))
+#define __HAL_RCC_GPIOE_RELEASE_RESET()  (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST))
+#define __HAL_RCC_GPIOF_RELEASE_RESET()  (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST))
+#define __HAL_RCC_GPIOG_RELEASE_RESET()  (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST))
+#define __HAL_RCC_GPIOI_RELEASE_RESET()  (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOIRST))
+#define __HAL_RCC_ETHMAC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_ETHMACRST))
+#define __HAL_RCC_USB_OTG_HS_RELEASE_RESET()  (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_OTGHRST))
+#define __HAL_RCC_GPIOJ_RELEASE_RESET()  (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOJRST))
+#define __HAL_RCC_GPIOK_RELEASE_RESET()  (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOKRST))
+#define __HAL_RCC_DMA2D_RELEASE_RESET()  (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA2DRST))
+#define __HAL_RCC_CRC_RELEASE_RESET()    (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST))
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_AHB2_Force_Release_Reset AHB2 Force Release Reset 
+  * @brief  Force or release AHB2 peripheral reset.
+  * @{
+  */
+#define __HAL_RCC_AHB2_FORCE_RESET()    (RCC->AHB2RSTR = 0xFFFFFFFFU) 
+#define __HAL_RCC_USB_OTG_FS_FORCE_RESET()   (RCC->AHB2RSTR |= (RCC_AHB2RSTR_OTGFSRST))
+#define __HAL_RCC_RNG_FORCE_RESET()    (RCC->AHB2RSTR |= (RCC_AHB2RSTR_RNGRST))
+#define __HAL_RCC_DCMI_FORCE_RESET()   (RCC->AHB2RSTR |= (RCC_AHB2RSTR_DCMIRST))
+
+#define __HAL_RCC_AHB2_RELEASE_RESET()  (RCC->AHB2RSTR = 0x00U)
+#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST))
+#define __HAL_RCC_RNG_RELEASE_RESET()  (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_RNGRST))
+#define __HAL_RCC_DCMI_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_DCMIRST))
+
+#if defined(STM32F437xx)|| defined(STM32F439xx) || defined(STM32F479xx) 
+#define __HAL_RCC_CRYP_FORCE_RESET()   (RCC->AHB2RSTR |= (RCC_AHB2RSTR_CRYPRST))
+#define __HAL_RCC_HASH_FORCE_RESET()   (RCC->AHB2RSTR |= (RCC_AHB2RSTR_HASHRST))
+
+#define __HAL_RCC_CRYP_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_CRYPRST))
+#define __HAL_RCC_HASH_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_HASHRST))
+#endif /* STM32F437xx || STM32F439xx || STM32F479xx */
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_AHB3_Force_Release_Reset AHB3 Force Release Reset 
+  * @brief  Force or release AHB3 peripheral reset.
+  * @{
+  */ 
+#define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFFU)
+#define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00U) 
+#define __HAL_RCC_FMC_FORCE_RESET()    (RCC->AHB3RSTR |= (RCC_AHB3RSTR_FMCRST))
+#define __HAL_RCC_FMC_RELEASE_RESET()  (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FMCRST))
+
+#if defined(STM32F469xx) || defined(STM32F479xx)
+#define __HAL_RCC_QSPI_FORCE_RESET()   (RCC->AHB3RSTR |= (RCC_AHB3RSTR_QSPIRST))
+#define __HAL_RCC_QSPI_RELEASE_RESET()   (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_QSPIRST))  
+#endif /* STM32F469xx || STM32F479xx */
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset 
+  * @brief  Force or release APB1 peripheral reset.
+  * @{
+  */ 
+#define __HAL_RCC_TIM6_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST))
+#define __HAL_RCC_TIM7_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST))
+#define __HAL_RCC_TIM12_FORCE_RESET()    (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM12RST))
+#define __HAL_RCC_TIM13_FORCE_RESET()    (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM13RST))
+#define __HAL_RCC_TIM14_FORCE_RESET()    (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST))
+#define __HAL_RCC_USART3_FORCE_RESET()   (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST))
+#define __HAL_RCC_UART4_FORCE_RESET()    (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST))
+#define __HAL_RCC_UART5_FORCE_RESET()    (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST))
+#define __HAL_RCC_CAN1_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN1RST))
+#define __HAL_RCC_CAN2_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN2RST))
+#define __HAL_RCC_DAC_FORCE_RESET()      (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST))
+#define __HAL_RCC_UART7_FORCE_RESET()    (RCC->APB1RSTR |= (RCC_APB1RSTR_UART7RST))
+#define __HAL_RCC_UART8_FORCE_RESET()    (RCC->APB1RSTR |= (RCC_APB1RSTR_UART8RST))
+#define __HAL_RCC_TIM2_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST))
+#define __HAL_RCC_TIM3_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST))
+#define __HAL_RCC_TIM4_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST))
+#define __HAL_RCC_SPI3_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST))
+#define __HAL_RCC_I2C3_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C3RST))
+
+#define __HAL_RCC_TIM2_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
+#define __HAL_RCC_TIM3_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
+#define __HAL_RCC_TIM4_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
+#define __HAL_RCC_SPI3_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
+#define __HAL_RCC_I2C3_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST))
+#define __HAL_RCC_TIM6_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
+#define __HAL_RCC_TIM7_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
+#define __HAL_RCC_TIM12_RELEASE_RESET()  (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST))
+#define __HAL_RCC_TIM13_RELEASE_RESET()  (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST))
+#define __HAL_RCC_TIM14_RELEASE_RESET()  (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))
+#define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
+#define __HAL_RCC_UART4_RELEASE_RESET()  (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST))
+#define __HAL_RCC_UART5_RELEASE_RESET()  (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST))
+#define __HAL_RCC_CAN1_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST))
+#define __HAL_RCC_CAN2_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST))
+#define __HAL_RCC_DAC_RELEASE_RESET()    (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
+#define __HAL_RCC_UART7_RELEASE_RESET()  (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART7RST))
+#define __HAL_RCC_UART8_RELEASE_RESET()  (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART8RST))
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset 
+  * @brief  Force or release APB2 peripheral reset.
+  * @{
+  */
+#define __HAL_RCC_TIM8_FORCE_RESET()   (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM8RST))
+#define __HAL_RCC_SPI5_FORCE_RESET()   (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI5RST))
+#define __HAL_RCC_SPI6_FORCE_RESET()   (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI6RST))
+#define __HAL_RCC_SAI1_FORCE_RESET()   (RCC->APB2RSTR |= (RCC_APB2RSTR_SAI1RST))
+#define __HAL_RCC_SDIO_FORCE_RESET()   (RCC->APB2RSTR |= (RCC_APB2RSTR_SDIORST))
+#define __HAL_RCC_SPI4_FORCE_RESET()   (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI4RST))
+#define __HAL_RCC_TIM10_FORCE_RESET()  (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM10RST))
+
+#define __HAL_RCC_SDIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST))
+#define __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST))
+#define __HAL_RCC_TIM10_RELEASE_RESET()(RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST))
+#define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST))
+#define __HAL_RCC_SPI5_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI5RST))
+#define __HAL_RCC_SPI6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI6RST))
+#define __HAL_RCC_SAI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI1RST))
+
+#if defined(STM32F429xx)|| defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
+#define __HAL_RCC_LTDC_FORCE_RESET()   (RCC->APB2RSTR |= (RCC_APB2RSTR_LTDCRST))
+#define __HAL_RCC_LTDC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_LTDCRST))
+#endif /* STM32F429xx|| STM32F439xx || STM32F469xx || STM32F479xx */
+
+#if defined(STM32F469xx) || defined(STM32F479xx)
+#define __HAL_RCC_DSI_FORCE_RESET()   (RCC->APB2RSTR |=  (RCC_APB2RSTR_DSIRST))
+#define __HAL_RCC_DSI_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_DSIRST))
+#endif /* STM32F469xx || STM32F479xx */
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable
+  * @brief  Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
+  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
+  * @{
+  */
+#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIODLPEN))
+#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOELPEN))
+#define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOFLPEN))
+#define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOGLPEN))
+#define __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOILPEN))
+#define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM2LPEN))
+#define __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE()     (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACLPEN))
+#define __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE()   (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACTXLPEN))
+#define __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE()   (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACRXLPEN))
+#define __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE()  (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACPTPLPEN))
+#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSLPEN))
+#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE()  (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSULPILPEN))
+#define __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOJLPEN))
+#define __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOKLPEN))
+#define __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM3LPEN))
+#define __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA2DLPEN))
+#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE()        (RCC->AHB1LPENR |= (RCC_AHB1LPENR_CRCLPEN))
+#define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_FLITFLPEN))
+#define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM1LPEN))
+#define __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE()    (RCC->AHB1LPENR |= (RCC_AHB1LPENR_BKPSRAMLPEN))
+
+#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN))
+#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN))
+#define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOFLPEN))
+#define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOGLPEN))
+#define __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOILPEN))
+#define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM2LPEN))
+#define __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE()    (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACLPEN))
+#define __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE()  (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACTXLPEN))
+#define __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE()  (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACRXLPEN))
+#define __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACPTPLPEN))
+#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSLPEN))
+#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSULPILPEN))
+#define __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOJLPEN))
+#define __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOKLPEN))
+#define __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA2DLPEN))
+#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE()       (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN))
+#define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN))
+#define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN))
+#define __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE()   (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_BKPSRAMLPEN))
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_AHB2_LowPower_Enable_Disable AHB2 Peripheral Low Power Enable Disable
+  * @brief  Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wake-up from SLEEP mode, the peripheral clock is enabled again.
+  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
+  * @{
+  */
+#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE()  (RCC->AHB2LPENR |= (RCC_AHB2LPENR_OTGFSLPEN))
+#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN))
+
+#define __HAL_RCC_RNG_CLK_SLEEP_ENABLE()   (RCC->AHB2LPENR |= (RCC_AHB2LPENR_RNGLPEN))
+#define __HAL_RCC_RNG_CLK_SLEEP_DISABLE()  (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_RNGLPEN))
+
+#define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE()  (RCC->AHB2LPENR |= (RCC_AHB2LPENR_DCMILPEN))
+#define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_DCMILPEN))
+
+#if defined(STM32F437xx)|| defined(STM32F439xx) || defined(STM32F479xx) 
+#define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE()  (RCC->AHB2LPENR |= (RCC_AHB2LPENR_CRYPLPEN))
+#define __HAL_RCC_HASH_CLK_SLEEP_ENABLE()  (RCC->AHB2LPENR |= (RCC_AHB2LPENR_HASHLPEN))
+
+#define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_CRYPLPEN))
+#define __HAL_RCC_HASH_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_HASHLPEN))
+#endif /* STM32F437xx || STM32F439xx || STM32F479xx */
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_AHB3_LowPower_Enable_Disable AHB3 Peripheral Low Power Enable Disable
+  * @brief  Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
+  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
+  * @{
+  */
+#define __HAL_RCC_FMC_CLK_SLEEP_ENABLE()  (RCC->AHB3LPENR |= (RCC_AHB3LPENR_FMCLPEN))
+#define __HAL_RCC_FMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_FMCLPEN))
+
+#if defined(STM32F469xx) || defined(STM32F479xx)
+#define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE()  (RCC->AHB3LPENR |= (RCC_AHB3LPENR_QSPILPEN))
+#define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE()  (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_QSPILPEN))
+#endif /* STM32F469xx || STM32F479xx */
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable
+  * @brief  Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
+  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
+  * @{
+  */  
+#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM6LPEN))
+#define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM7LPEN))
+#define __HAL_RCC_TIM12_CLK_SLEEP_ENABLE()   (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM12LPEN))
+#define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE()   (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM13LPEN))
+#define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE()   (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM14LPEN))
+#define __HAL_RCC_USART3_CLK_SLEEP_ENABLE()  (RCC->APB1LPENR |= (RCC_APB1LPENR_USART3LPEN))
+#define __HAL_RCC_UART4_CLK_SLEEP_ENABLE()   (RCC->APB1LPENR |= (RCC_APB1LPENR_UART4LPEN))
+#define __HAL_RCC_UART5_CLK_SLEEP_ENABLE()   (RCC->APB1LPENR |= (RCC_APB1LPENR_UART5LPEN))
+#define __HAL_RCC_CAN1_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN1LPEN))
+#define __HAL_RCC_CAN2_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN2LPEN))
+#define __HAL_RCC_DAC_CLK_SLEEP_ENABLE()     (RCC->APB1LPENR |= (RCC_APB1LPENR_DACLPEN))
+#define __HAL_RCC_UART7_CLK_SLEEP_ENABLE()   (RCC->APB1LPENR |= (RCC_APB1LPENR_UART7LPEN))
+#define __HAL_RCC_UART8_CLK_SLEEP_ENABLE()   (RCC->APB1LPENR |= (RCC_APB1LPENR_UART8LPEN))
+#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM2LPEN))
+#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM3LPEN))
+#define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM4LPEN))
+#define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI3LPEN))
+#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C3LPEN))
+
+#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN))
+#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN))
+#define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN))
+#define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN))
+#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN))
+#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN))
+#define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN))
+#define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE()  (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM12LPEN))
+#define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE()  (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM13LPEN))
+#define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE()  (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM14LPEN))
+#define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN))
+#define __HAL_RCC_UART4_CLK_SLEEP_DISABLE()  (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN))
+#define __HAL_RCC_UART5_CLK_SLEEP_DISABLE()  (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN))
+#define __HAL_RCC_CAN1_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN1LPEN))
+#define __HAL_RCC_CAN2_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN2LPEN))
+#define __HAL_RCC_DAC_CLK_SLEEP_DISABLE()    (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN))
+#define __HAL_RCC_UART7_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART7LPEN))
+#define __HAL_RCC_UART8_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART8LPEN))
+/**
+  * @}
+  */
+                                        
+/** @defgroup RCCEx_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable
+  * @brief  Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
+  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
+  * @{
+  */ 
+#define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM8LPEN))
+#define __HAL_RCC_ADC2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC2LPEN))
+#define __HAL_RCC_ADC3_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC3LPEN))
+#define __HAL_RCC_SPI5_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI5LPEN))
+#define __HAL_RCC_SPI6_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI6LPEN))
+#define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SAI1LPEN))
+#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SDIOLPEN))
+#define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI4LPEN))
+#define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE()(RCC->APB2LPENR |= (RCC_APB2LPENR_TIM10LPEN))
+
+#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN))
+#define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN))
+#define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE()(RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN))
+#define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM8LPEN))
+#define __HAL_RCC_ADC2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC2LPEN))
+#define __HAL_RCC_ADC3_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC3LPEN))
+#define __HAL_RCC_SPI5_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI5LPEN))
+#define __HAL_RCC_SPI6_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI6LPEN))
+#define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI1LPEN))
+
+#if defined(STM32F429xx)|| defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
+#define __HAL_RCC_LTDC_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_LTDCLPEN))
+
+#define __HAL_RCC_LTDC_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_LTDCLPEN))
+#endif /* STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
+
+#if defined(STM32F469xx) || defined(STM32F479xx)
+#define __HAL_RCC_DSI_CLK_SLEEP_ENABLE()  (RCC->APB2LPENR |=  (RCC_APB2LPENR_DSILPEN))
+#define __HAL_RCC_DSI_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_DSILPEN))
+#endif /* STM32F469xx || STM32F479xx */
+/**
+  * @}
+  */
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx || STM32F469xx || STM32F479xx */
+/*----------------------------------------------------------------------------*/
+
+/*----------------------------------- STM32F40xxx/STM32F41xxx-----------------*/
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx)
+/** @defgroup RCCEx_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable
+  * @brief  Enables or disables the AHB1 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before 
+  *         using it.
+  * @{
+  */
+#define __HAL_RCC_BKPSRAM_CLK_ENABLE() do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
+                                        UNUSED(tmpreg); \
+                                        } while(0U)
+#define __HAL_RCC_CCMDATARAMEN_CLK_ENABLE() do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\
+                                        UNUSED(tmpreg); \
+                                        } while(0U)
+#define __HAL_RCC_CRC_CLK_ENABLE()     do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
+                                        UNUSED(tmpreg); \
+                                        } while(0U)
+#define __HAL_RCC_GPIOD_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
+                                        UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_GPIOE_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
+                                        UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_GPIOI_CLK_ENABLE()   do { \
+                                       __IO uint32_t tmpreg = 0x00U; \
+                                       SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\
+                                       /* Delay after an RCC peripheral clock enabling */ \
+                                       tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\
+                                       UNUSED(tmpreg); \
+                                       } while(0U)
+#define __HAL_RCC_GPIOF_CLK_ENABLE()   do { \
+                                       __IO uint32_t tmpreg = 0x00U; \
+                                       SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
+                                       /* Delay after an RCC peripheral clock enabling */ \
+                                       tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
+                                       UNUSED(tmpreg); \
+                                       } while(0U)
+#define __HAL_RCC_GPIOG_CLK_ENABLE()   do { \
+                                       __IO uint32_t tmpreg = 0x00U; \
+                                       SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
+                                       /* Delay after an RCC peripheral clock enabling */ \
+                                       tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
+                                       UNUSED(tmpreg); \
+                                       } while(0U)
+#define __HAL_RCC_USB_OTG_HS_CLK_ENABLE()   do { \
+                                       __IO uint32_t tmpreg = 0x00U; \
+                                       SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\
+                                       /* Delay after an RCC peripheral clock enabling */ \
+                                       tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\
+                                       UNUSED(tmpreg); \
+                                       } while(0U)
+#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE()   do { \
+                                       __IO uint32_t tmpreg = 0x00U; \
+                                       SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\
+                                       /* Delay after an RCC peripheral clock enabling */ \
+                                       tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\
+                                       UNUSED(tmpreg); \
+                                       } while(0U)
+#define __HAL_RCC_GPIOD_CLK_DISABLE()           (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN))
+#define __HAL_RCC_GPIOE_CLK_DISABLE()           (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN))
+#define __HAL_RCC_GPIOF_CLK_DISABLE()           (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN))
+#define __HAL_RCC_GPIOG_CLK_DISABLE()           (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN))
+#define __HAL_RCC_GPIOI_CLK_DISABLE()           (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOIEN))
+#define __HAL_RCC_USB_OTG_HS_CLK_DISABLE()      (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSEN))
+#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSULPIEN))
+#define __HAL_RCC_BKPSRAM_CLK_DISABLE()         (RCC->AHB1ENR &= ~(RCC_AHB1ENR_BKPSRAMEN))
+#define __HAL_RCC_CCMDATARAMEN_CLK_DISABLE()    (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CCMDATARAMEN))
+#define __HAL_RCC_CRC_CLK_DISABLE()             (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN))
+#if defined(STM32F407xx)|| defined(STM32F417xx)
+/**
+  * @brief  Enable ETHERNET clock.
+  */
+#define __HAL_RCC_ETHMAC_CLK_ENABLE()  do { \
+                                       __IO uint32_t tmpreg = 0x00U; \
+                                       SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\
+                                       /* Delay after an RCC peripheral clock enabling */ \
+                                       tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\
+                                       UNUSED(tmpreg); \
+                                       } while(0U)
+#define __HAL_RCC_ETHMACTX_CLK_ENABLE() do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\
+                                        UNUSED(tmpreg); \
+                                        } while(0U)
+#define __HAL_RCC_ETHMACRX_CLK_ENABLE() do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\
+                                        UNUSED(tmpreg); \
+                                        } while(0U)
+#define __HAL_RCC_ETHMACPTP_CLK_ENABLE() do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\
+                                        UNUSED(tmpreg); \
+                                        } while(0U)
+#define __HAL_RCC_ETH_CLK_ENABLE()      do {                            \
+                                        __HAL_RCC_ETHMAC_CLK_ENABLE();      \
+                                        __HAL_RCC_ETHMACTX_CLK_ENABLE();    \
+                                        __HAL_RCC_ETHMACRX_CLK_ENABLE();    \
+                                        } while(0U)
+
+/**
+  * @brief  Disable ETHERNET clock.
+  */
+#define __HAL_RCC_ETHMAC_CLK_DISABLE()    (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACEN))
+#define __HAL_RCC_ETHMACTX_CLK_DISABLE()  (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACTXEN))
+#define __HAL_RCC_ETHMACRX_CLK_DISABLE()  (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACRXEN))
+#define __HAL_RCC_ETHMACPTP_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACPTPEN))  
+#define __HAL_RCC_ETH_CLK_DISABLE()       do {                             \
+                                           __HAL_RCC_ETHMACTX_CLK_DISABLE();    \
+                                           __HAL_RCC_ETHMACRX_CLK_DISABLE();    \
+                                           __HAL_RCC_ETHMAC_CLK_DISABLE();      \
+                                          } while(0U)
+#endif /* STM32F407xx || STM32F417xx */
+/**
+  * @}
+  */
+  
+/** @defgroup RCCEx_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status
+  * @brief  Get the enable or disable status of the AHB1 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  * @{
+  */  
+#define __HAL_RCC_BKPSRAM_IS_CLK_ENABLED()          ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) != RESET)
+#define __HAL_RCC_CCMDATARAMEN_IS_CLK_ENABLED()     ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) != RESET)
+#define __HAL_RCC_CRC_IS_CLK_ENABLED()              ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET)
+#define __HAL_RCC_GPIOD_IS_CLK_ENABLED()            ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) != RESET)
+#define __HAL_RCC_GPIOE_IS_CLK_ENABLED()            ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) != RESET)
+#define __HAL_RCC_GPIOI_IS_CLK_ENABLED()            ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOIEN)) != RESET)
+#define __HAL_RCC_GPIOF_IS_CLK_ENABLED()            ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) != RESET)
+#define __HAL_RCC_GPIOG_IS_CLK_ENABLED()            ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) != RESET)
+#define __HAL_RCC_USB_OTG_HS_IS_CLK_ENABLED()       ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) != RESET)
+#define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_ENABLED()  ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN)) != RESET)
+
+#define __HAL_RCC_GPIOD_IS_CLK_DISABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) == RESET)
+#define __HAL_RCC_GPIOE_IS_CLK_DISABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) == RESET)
+#define __HAL_RCC_GPIOF_IS_CLK_DISABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) == RESET)
+#define __HAL_RCC_GPIOG_IS_CLK_DISABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) == RESET)
+#define __HAL_RCC_GPIOI_IS_CLK_DISABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOIEN)) == RESET)
+#define __HAL_RCC_USB_OTG_HS_IS_CLK_DISABLED()      ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) == RESET)
+#define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN))== RESET)
+#define __HAL_RCC_BKPSRAM_IS_CLK_DISABLED()         ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) == RESET)
+#define __HAL_RCC_CCMDATARAMEN_IS_CLK_DISABLED()    ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) == RESET)
+#define __HAL_RCC_CRC_IS_CLK_DISABLED()             ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET)
+#if defined(STM32F407xx)|| defined(STM32F417xx)
+/**
+  * @brief  Enable ETHERNET clock.
+  */
+#define __HAL_RCC_ETHMAC_IS_CLK_ENABLED()     ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACEN)) != RESET)
+#define __HAL_RCC_ETHMACTX_IS_CLK_ENABLED()   ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACTXEN)) != RESET)
+#define __HAL_RCC_ETHMACRX_IS_CLK_ENABLED()   ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACRXEN)) != RESET)
+#define __HAL_RCC_ETHMACPTP_IS_CLK_ENABLED()  ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACPTPEN)) != RESET)
+#define __HAL_RCC_ETH_IS_CLK_ENABLED()        (__HAL_RCC_ETHMAC_IS_CLK_ENABLED()   && \
+                                               __HAL_RCC_ETHMACTX_IS_CLK_ENABLED() && \
+                                               __HAL_RCC_ETHMACRX_IS_CLK_ENABLED())
+/**
+  * @brief  Disable ETHERNET clock.
+  */
+#define __HAL_RCC_ETHMAC_IS_CLK_DISABLED()    ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACEN)) == RESET)
+#define __HAL_RCC_ETHMACTX_IS_CLK_DISABLED()  ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACTXEN)) == RESET)
+#define __HAL_RCC_ETHMACRX_IS_CLK_DISABLED()  ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACRXEN)) == RESET)
+#define __HAL_RCC_ETHMACPTP_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACPTPEN)) == RESET)
+#define __HAL_RCC_ETH_IS_CLK_DISABLED()        (__HAL_RCC_ETHMAC_IS_CLK_DISABLED()   && \
+                                                __HAL_RCC_ETHMACTX_IS_CLK_DISABLED() && \
+                                                __HAL_RCC_ETHMACRX_IS_CLK_DISABLED())
+#endif /* STM32F407xx || STM32F417xx */
+/**
+  * @}
+  */
+  
+/** @defgroup RCCEx_AHB2_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable 
+  * @brief  Enable or disable the AHB2 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before 
+  *         using it.
+  * @{
+  */
+#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE()  do {(RCC->AHB2ENR |= (RCC_AHB2ENR_OTGFSEN));\
+                                               __HAL_RCC_SYSCFG_CLK_ENABLE();\
+                                              }while(0U)
+                                        
+#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN))
+
+#define __HAL_RCC_RNG_CLK_ENABLE()    do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
+                                        UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_RNG_CLK_DISABLE()   (RCC->AHB2ENR &= ~(RCC_AHB2ENR_RNGEN))
+
+#if defined(STM32F407xx)|| defined(STM32F417xx) 
+#define __HAL_RCC_DCMI_CLK_ENABLE()   do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_DCMI_CLK_DISABLE()  (RCC->AHB2ENR &= ~(RCC_AHB2ENR_DCMIEN))
+#endif /* STM32F407xx || STM32F417xx */
+
+#if defined(STM32F415xx) || defined(STM32F417xx)
+#define __HAL_RCC_CRYP_CLK_ENABLE()   do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_HASH_CLK_ENABLE()   do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_CRYP_CLK_DISABLE()  (RCC->AHB2ENR &= ~(RCC_AHB2ENR_CRYPEN))
+#define __HAL_RCC_HASH_CLK_DISABLE()  (RCC->AHB2ENR &= ~(RCC_AHB2ENR_HASHEN))
+#endif /* STM32F415xx || STM32F417xx */
+/**
+  * @}
+  */
+
+
+/** @defgroup RCCEx_AHB2_Peripheral_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enable Disable Status
+  * @brief  Get the enable or disable status of the AHB2 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  * @{
+  */
+#define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED()  ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) != RESET)
+#define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) == RESET) 
+
+#define __HAL_RCC_RNG_IS_CLK_ENABLED()   ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) != RESET)   
+#define __HAL_RCC_RNG_IS_CLK_DISABLED()  ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) == RESET) 
+
+#if defined(STM32F407xx)|| defined(STM32F417xx) 
+#define __HAL_RCC_DCMI_IS_CLK_ENABLED()  ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) != RESET) 
+#define __HAL_RCC_DCMI_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) == RESET) 
+#endif /* STM32F407xx || STM32F417xx */
+
+#if defined(STM32F415xx) || defined(STM32F417xx)
+#define __HAL_RCC_CRYP_IS_CLK_ENABLED()   ((RCC->AHB2ENR & (RCC_AHB2ENR_CRYPEN)) != RESET) 
+#define __HAL_RCC_HASH_IS_CLK_ENABLED()   ((RCC->AHB2ENR & (RCC_AHB2ENR_HASHEN)) != RESET) 
+
+#define __HAL_RCC_CRYP_IS_CLK_DISABLED()  ((RCC->AHB2ENR & (RCC_AHB2ENR_CRYPEN)) == RESET) 
+#define __HAL_RCC_HASH_IS_CLK_DISABLED()  ((RCC->AHB2ENR & (RCC_AHB2ENR_HASHEN)) == RESET) 
+#endif /* STM32F415xx || STM32F417xx */  
+/**
+  * @}
+  */  
+  
+/** @defgroup RCCEx_AHB3_Clock_Enable_Disable AHB3 Peripheral Clock Enable Disable
+  * @brief  Enables or disables the AHB3 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before 
+  *         using it.
+  * @{  
+  */
+#define __HAL_RCC_FSMC_CLK_ENABLE()   do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_FSMC_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FSMCEN))
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_AHB3_Peripheral_Clock_Enable_Disable_Status AHB3 Peripheral Clock Enable Disable Status
+  * @brief  Get the enable or disable status of the AHB3 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  * @{
+  */
+#define __HAL_RCC_FSMC_IS_CLK_ENABLED()   ((RCC->AHB3ENR & (RCC_AHB3ENR_FSMCEN)) != RESET) 
+#define __HAL_RCC_FSMC_IS_CLK_DISABLED()  ((RCC->AHB3ENR & (RCC_AHB3ENR_FSMCEN)) == RESET) 
+/**
+  * @}
+  */   
+   
+/** @defgroup RCCEx_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable
+  * @brief  Enable or disable the Low Speed APB (APB1) peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before 
+  *         using it.
+  * @{  
+  */
+#define __HAL_RCC_TIM6_CLK_ENABLE()   do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_TIM7_CLK_ENABLE()   do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_TIM12_CLK_ENABLE()  do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_TIM13_CLK_ENABLE()  do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_TIM14_CLK_ENABLE()  do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_USART3_CLK_ENABLE() do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_UART4_CLK_ENABLE()  do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_UART5_CLK_ENABLE()  do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_CAN1_CLK_ENABLE()   do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_CAN2_CLK_ENABLE()   do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_DAC_CLK_ENABLE()    do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_TIM2_CLK_ENABLE()     do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
+                                        UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_TIM3_CLK_ENABLE()     do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
+                                        UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_TIM4_CLK_ENABLE()     do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
+                                        UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_SPI3_CLK_ENABLE()     do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
+                                        UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_I2C3_CLK_ENABLE()     do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
+                                        UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_TIM2_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
+#define __HAL_RCC_TIM3_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
+#define __HAL_RCC_TIM4_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
+#define __HAL_RCC_SPI3_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
+#define __HAL_RCC_I2C3_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN))
+#define __HAL_RCC_TIM6_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
+#define __HAL_RCC_TIM7_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
+#define __HAL_RCC_TIM12_CLK_DISABLE()  (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN))
+#define __HAL_RCC_TIM13_CLK_DISABLE()  (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN))
+#define __HAL_RCC_TIM14_CLK_DISABLE()  (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))
+#define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
+#define __HAL_RCC_UART4_CLK_DISABLE()  (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))
+#define __HAL_RCC_UART5_CLK_DISABLE()  (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))
+#define __HAL_RCC_CAN1_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN))
+#define __HAL_RCC_CAN2_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN))
+#define __HAL_RCC_DAC_CLK_DISABLE()    (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
+/**
+  * @}
+  */
+ 
+/** @defgroup RCCEx_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status
+  * @brief  Get the enable or disable status of the APB1 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  * @{
+  */ 
+#define __HAL_RCC_TIM2_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET)  
+#define __HAL_RCC_TIM3_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET) 
+#define __HAL_RCC_TIM4_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET)
+#define __HAL_RCC_SPI3_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET) 
+#define __HAL_RCC_I2C3_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET) 
+#define __HAL_RCC_TIM6_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET) 
+#define __HAL_RCC_TIM7_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET) 
+#define __HAL_RCC_TIM12_IS_CLK_ENABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) != RESET) 
+#define __HAL_RCC_TIM13_IS_CLK_ENABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET) 
+#define __HAL_RCC_TIM14_IS_CLK_ENABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET) 
+#define __HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET) 
+#define __HAL_RCC_UART4_IS_CLK_ENABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET) 
+#define __HAL_RCC_UART5_IS_CLK_ENABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != RESET) 
+#define __HAL_RCC_CAN1_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) != RESET) 
+#define __HAL_RCC_CAN2_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) != RESET) 
+#define __HAL_RCC_DAC_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET) 
+
+#define __HAL_RCC_TIM2_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET)  
+#define __HAL_RCC_TIM3_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET) 
+#define __HAL_RCC_TIM4_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET)
+#define __HAL_RCC_SPI3_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET) 
+#define __HAL_RCC_I2C3_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET) 
+#define __HAL_RCC_TIM6_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET) 
+#define __HAL_RCC_TIM7_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET) 
+#define __HAL_RCC_TIM12_IS_CLK_DISABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) == RESET) 
+#define __HAL_RCC_TIM13_IS_CLK_DISABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) == RESET) 
+#define __HAL_RCC_TIM14_IS_CLK_DISABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET) 
+#define __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET) 
+#define __HAL_RCC_UART4_IS_CLK_DISABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == RESET) 
+#define __HAL_RCC_UART5_IS_CLK_DISABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == RESET) 
+#define __HAL_RCC_CAN1_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) == RESET) 
+#define __HAL_RCC_CAN2_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) == RESET) 
+#define __HAL_RCC_DAC_IS_CLK_DISABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET) 
+  /**
+  * @}
+  */
+  
+/** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable
+  * @brief  Enable or disable the High Speed APB (APB2) peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before 
+  *         using it.
+  * @{
+  */ 
+#define __HAL_RCC_TIM8_CLK_ENABLE()   do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_ADC2_CLK_ENABLE()   do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_ADC3_CLK_ENABLE()   do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_SDIO_CLK_ENABLE()     do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
+                                        UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_SPI4_CLK_ENABLE()     do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
+                                        UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_TIM10_CLK_ENABLE()    do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
+                                        UNUSED(tmpreg); \
+                                      } while(0U)
+
+#define __HAL_RCC_SDIO_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN))
+#define __HAL_RCC_SPI4_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN))
+#define __HAL_RCC_TIM10_CLK_DISABLE()  (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN))
+#define __HAL_RCC_TIM8_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN))
+#define __HAL_RCC_ADC2_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN))
+#define __HAL_RCC_ADC3_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN))
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status
+  * @brief  Get the enable or disable status of the APB2 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  * @{
+  */
+#define __HAL_RCC_SDIO_IS_CLK_ENABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) != RESET)  
+#define __HAL_RCC_SPI4_IS_CLK_ENABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) != RESET)  
+#define __HAL_RCC_TIM10_IS_CLK_ENABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) != RESET) 
+#define __HAL_RCC_TIM8_IS_CLK_ENABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) != RESET) 
+#define __HAL_RCC_ADC2_IS_CLK_ENABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) != RESET) 
+#define __HAL_RCC_ADC3_IS_CLK_ENABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) != RESET)
+  
+#define __HAL_RCC_SDIO_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) == RESET)  
+#define __HAL_RCC_SPI4_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) == RESET)  
+#define __HAL_RCC_TIM10_IS_CLK_DISABLED()  ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) == RESET) 
+#define __HAL_RCC_TIM8_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) == RESET) 
+#define __HAL_RCC_ADC2_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) == RESET) 
+#define __HAL_RCC_ADC3_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) == RESET)
+/**
+  * @}
+  */
+    
+/** @defgroup RCCEx_AHB1_Force_Release_Reset AHB1 Force Release Reset 
+  * @brief  Force or release AHB1 peripheral reset.
+  * @{
+  */
+#define __HAL_RCC_GPIOD_FORCE_RESET()    (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIODRST))
+#define __HAL_RCC_GPIOE_FORCE_RESET()    (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOERST))
+#define __HAL_RCC_GPIOF_FORCE_RESET()    (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOFRST))
+#define __HAL_RCC_GPIOG_FORCE_RESET()    (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOGRST))
+#define __HAL_RCC_GPIOI_FORCE_RESET()    (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOIRST))
+#define __HAL_RCC_ETHMAC_FORCE_RESET()   (RCC->AHB1RSTR |= (RCC_AHB1RSTR_ETHMACRST))
+#define __HAL_RCC_USB_OTG_HS_FORCE_RESET()    (RCC->AHB1RSTR |= (RCC_AHB1RSTR_OTGHRST))
+#define __HAL_RCC_CRC_FORCE_RESET()     (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST))
+
+#define __HAL_RCC_GPIOD_RELEASE_RESET()  (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST))
+#define __HAL_RCC_GPIOE_RELEASE_RESET()  (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST))
+#define __HAL_RCC_GPIOF_RELEASE_RESET()  (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST))
+#define __HAL_RCC_GPIOG_RELEASE_RESET()  (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST))
+#define __HAL_RCC_GPIOI_RELEASE_RESET()  (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOIRST))
+#define __HAL_RCC_ETHMAC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_ETHMACRST))
+#define __HAL_RCC_USB_OTG_HS_RELEASE_RESET()  (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_OTGHRST))
+#define __HAL_RCC_CRC_RELEASE_RESET()    (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST))
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_AHB2_Force_Release_Reset AHB2 Force Release Reset 
+  * @brief  Force or release AHB2 peripheral reset.
+  * @{
+  */
+#define __HAL_RCC_AHB2_FORCE_RESET()         (RCC->AHB2RSTR = 0xFFFFFFFFU) 
+#define __HAL_RCC_AHB2_RELEASE_RESET()       (RCC->AHB2RSTR = 0x00U)
+
+#if defined(STM32F407xx)|| defined(STM32F417xx)  
+#define __HAL_RCC_DCMI_FORCE_RESET()   (RCC->AHB2RSTR |= (RCC_AHB2RSTR_DCMIRST))
+#define __HAL_RCC_DCMI_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_DCMIRST))
+#endif /* STM32F407xx || STM32F417xx */
+
+#if defined(STM32F415xx) || defined(STM32F417xx) 
+#define __HAL_RCC_CRYP_FORCE_RESET()   (RCC->AHB2RSTR |= (RCC_AHB2RSTR_CRYPRST))
+#define __HAL_RCC_HASH_FORCE_RESET()   (RCC->AHB2RSTR |= (RCC_AHB2RSTR_HASHRST))
+
+#define __HAL_RCC_CRYP_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_CRYPRST))
+#define __HAL_RCC_HASH_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_HASHRST))
+#endif /* STM32F415xx || STM32F417xx */
+   
+#define __HAL_RCC_USB_OTG_FS_FORCE_RESET()   (RCC->AHB2RSTR |= (RCC_AHB2RSTR_OTGFSRST))
+#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST))
+
+#define __HAL_RCC_RNG_FORCE_RESET()    (RCC->AHB2RSTR |= (RCC_AHB2RSTR_RNGRST))
+#define __HAL_RCC_RNG_RELEASE_RESET()  (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_RNGRST))
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_AHB3_Force_Release_Reset AHB3 Force Release Reset 
+  * @brief  Force or release AHB3 peripheral reset.
+  * @{
+  */ 
+#define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFFU)
+#define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00U) 
+
+#define __HAL_RCC_FSMC_FORCE_RESET()   (RCC->AHB3RSTR |= (RCC_AHB3RSTR_FSMCRST))
+#define __HAL_RCC_FSMC_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FSMCRST))
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset 
+  * @brief  Force or release APB1 peripheral reset.
+  * @{
+  */
+#define __HAL_RCC_TIM6_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST))
+#define __HAL_RCC_TIM7_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST))
+#define __HAL_RCC_TIM12_FORCE_RESET()    (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM12RST))
+#define __HAL_RCC_TIM13_FORCE_RESET()    (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM13RST))
+#define __HAL_RCC_TIM14_FORCE_RESET()    (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST))
+#define __HAL_RCC_USART3_FORCE_RESET()   (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST))
+#define __HAL_RCC_UART4_FORCE_RESET()    (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST))
+#define __HAL_RCC_UART5_FORCE_RESET()    (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST))
+#define __HAL_RCC_CAN1_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN1RST))
+#define __HAL_RCC_CAN2_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN2RST))
+#define __HAL_RCC_DAC_FORCE_RESET()      (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST))
+#define __HAL_RCC_TIM2_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST))
+#define __HAL_RCC_TIM3_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST))
+#define __HAL_RCC_TIM4_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST))
+#define __HAL_RCC_SPI3_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST))
+#define __HAL_RCC_I2C3_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C3RST))
+
+#define __HAL_RCC_TIM2_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
+#define __HAL_RCC_TIM3_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
+#define __HAL_RCC_TIM4_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
+#define __HAL_RCC_SPI3_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
+#define __HAL_RCC_I2C3_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST))
+#define __HAL_RCC_TIM6_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
+#define __HAL_RCC_TIM7_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
+#define __HAL_RCC_TIM12_RELEASE_RESET()  (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST))
+#define __HAL_RCC_TIM13_RELEASE_RESET()  (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST))
+#define __HAL_RCC_TIM14_RELEASE_RESET()  (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))
+#define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
+#define __HAL_RCC_UART4_RELEASE_RESET()  (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST))
+#define __HAL_RCC_UART5_RELEASE_RESET()  (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST))
+#define __HAL_RCC_CAN1_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST))
+#define __HAL_RCC_CAN2_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST))
+#define __HAL_RCC_DAC_RELEASE_RESET()    (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset 
+  * @brief  Force or release APB2 peripheral reset.
+  * @{
+  */
+#define __HAL_RCC_TIM8_FORCE_RESET()   (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM8RST))
+#define __HAL_RCC_SDIO_FORCE_RESET()   (RCC->APB2RSTR |= (RCC_APB2RSTR_SDIORST))
+#define __HAL_RCC_SPI4_FORCE_RESET()   (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI4RST))
+#define __HAL_RCC_TIM10_FORCE_RESET()  (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM10RST))
+                                          
+#define __HAL_RCC_SDIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST))
+#define __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST))
+#define __HAL_RCC_TIM10_RELEASE_RESET()(RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST))
+#define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST))
+/**
+  * @}
+  */
+                                        
+/** @defgroup RCCEx_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable
+  * @brief  Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
+  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
+  * @{
+  */
+#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIODLPEN))
+#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOELPEN))
+#define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOFLPEN))
+#define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOGLPEN))
+#define __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOILPEN))
+#define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM2LPEN))
+#define __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE()     (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACLPEN))
+#define __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE()   (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACTXLPEN))
+#define __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE()   (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACRXLPEN))
+#define __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE()  (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACPTPLPEN))
+#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSLPEN))
+#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE()  (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSULPILPEN))
+#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_CRCLPEN))
+#define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE()    (RCC->AHB1LPENR |= (RCC_AHB1LPENR_FLITFLPEN))
+#define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE()    (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM1LPEN))
+#define __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE()  (RCC->AHB1LPENR |= (RCC_AHB1LPENR_BKPSRAMLPEN))
+
+#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN))
+#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN))
+#define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOFLPEN))
+#define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOGLPEN))
+#define __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOILPEN))
+#define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM2LPEN))
+#define __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE()    (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACLPEN))
+#define __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE()  (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACTXLPEN))
+#define __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE()  (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACRXLPEN))
+#define __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACPTPLPEN))
+#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSLPEN))
+#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSULPILPEN))
+#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE()       (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN))
+#define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN))
+#define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN))
+#define __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE()   (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_BKPSRAMLPEN))
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_AHB2_LowPower_Enable_Disable AHB2 Peripheral Low Power Enable Disable
+  * @brief  Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wake-up from SLEEP mode, the peripheral clock is enabled again.
+  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
+  * @{
+  */
+#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE()  (RCC->AHB2LPENR |= (RCC_AHB2LPENR_OTGFSLPEN))
+#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN))
+
+#define __HAL_RCC_RNG_CLK_SLEEP_ENABLE()   (RCC->AHB2LPENR |= (RCC_AHB2LPENR_RNGLPEN))
+#define __HAL_RCC_RNG_CLK_SLEEP_DISABLE()  (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_RNGLPEN))
+
+#if defined(STM32F407xx)|| defined(STM32F417xx) 
+#define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE()  (RCC->AHB2LPENR |= (RCC_AHB2LPENR_DCMILPEN))
+#define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_DCMILPEN))
+#endif /* STM32F407xx || STM32F417xx */
+
+#if defined(STM32F415xx) || defined(STM32F417xx) 
+#define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE()  (RCC->AHB2LPENR |= (RCC_AHB2LPENR_CRYPLPEN))
+#define __HAL_RCC_HASH_CLK_SLEEP_ENABLE()  (RCC->AHB2LPENR |= (RCC_AHB2LPENR_HASHLPEN))
+
+#define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_CRYPLPEN))
+#define __HAL_RCC_HASH_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_HASHLPEN))
+#endif /* STM32F415xx || STM32F417xx */
+/**
+  * @}
+  */
+                                        
+/** @defgroup RCCEx_AHB3_LowPower_Enable_Disable AHB3 Peripheral Low Power Enable Disable
+  * @brief  Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
+  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
+  * @{
+  */
+#define __HAL_RCC_FSMC_CLK_SLEEP_ENABLE()  (RCC->AHB3LPENR |= (RCC_AHB3LPENR_FSMCLPEN))
+#define __HAL_RCC_FSMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_FSMCLPEN))
+/**
+  * @}
+  */
+                                        
+/** @defgroup RCCEx_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable
+  * @brief  Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
+  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
+  * @{
+  */
+#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM6LPEN))
+#define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM7LPEN))
+#define __HAL_RCC_TIM12_CLK_SLEEP_ENABLE()   (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM12LPEN))
+#define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE()   (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM13LPEN))
+#define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE()   (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM14LPEN))
+#define __HAL_RCC_USART3_CLK_SLEEP_ENABLE()  (RCC->APB1LPENR |= (RCC_APB1LPENR_USART3LPEN))
+#define __HAL_RCC_UART4_CLK_SLEEP_ENABLE()   (RCC->APB1LPENR |= (RCC_APB1LPENR_UART4LPEN))
+#define __HAL_RCC_UART5_CLK_SLEEP_ENABLE()   (RCC->APB1LPENR |= (RCC_APB1LPENR_UART5LPEN))
+#define __HAL_RCC_CAN1_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN1LPEN))
+#define __HAL_RCC_CAN2_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN2LPEN))
+#define __HAL_RCC_DAC_CLK_SLEEP_ENABLE()     (RCC->APB1LPENR |= (RCC_APB1LPENR_DACLPEN))
+#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM2LPEN))
+#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM3LPEN))
+#define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM4LPEN))
+#define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI3LPEN))
+#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C3LPEN))
+
+#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN))
+#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN))
+#define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN))
+#define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN))
+#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN))
+#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN))
+#define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN))
+#define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE()  (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM12LPEN))
+#define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE()  (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM13LPEN))
+#define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE()  (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM14LPEN))
+#define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN))
+#define __HAL_RCC_UART4_CLK_SLEEP_DISABLE()  (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN))
+#define __HAL_RCC_UART5_CLK_SLEEP_DISABLE()  (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN))
+#define __HAL_RCC_CAN1_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN1LPEN))
+#define __HAL_RCC_CAN2_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN2LPEN))
+#define __HAL_RCC_DAC_CLK_SLEEP_DISABLE()    (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN))
+/**
+  * @}
+  */
+                                        
+/** @defgroup RCCEx_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable
+  * @brief  Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
+  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
+  * @{
+  */
+#define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM8LPEN))
+#define __HAL_RCC_ADC2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC2LPEN))
+#define __HAL_RCC_ADC3_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC3LPEN))
+#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SDIOLPEN))
+#define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI4LPEN))
+#define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE()(RCC->APB2LPENR |= (RCC_APB2LPENR_TIM10LPEN))
+
+#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN))
+#define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN))
+#define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE()(RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN))
+#define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM8LPEN))
+#define __HAL_RCC_ADC2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC2LPEN))
+#define __HAL_RCC_ADC3_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC3LPEN))
+/**
+  * @}
+  */
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
+/*----------------------------------------------------------------------------*/
+
+/*------------------------- STM32F401xE/STM32F401xC --------------------------*/
+#if defined(STM32F401xC) || defined(STM32F401xE)
+/** @defgroup RCCEx_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable
+  * @brief  Enable or disable the AHB1 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before 
+  *         using it.   
+  * @{
+  */
+#define __HAL_RCC_GPIOD_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
+                                        UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_GPIOE_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
+                                        UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_CRC_CLK_ENABLE()    do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
+                                        UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_CCMDATARAMEN_CLK_ENABLE()  do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\
+                                        UNUSED(tmpreg); \
+                                      } while(0U)
+
+#define __HAL_RCC_GPIOD_CLK_DISABLE()        (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN))
+#define __HAL_RCC_GPIOE_CLK_DISABLE()        (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN))
+#define __HAL_RCC_CRC_CLK_DISABLE()          (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN))
+#define __HAL_RCC_CCMDATARAMEN_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CCMDATARAMEN))
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status
+  * @brief  Get the enable or disable status of the AHB1 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  * @{
+  */
+#define __HAL_RCC_GPIOD_IS_CLK_ENABLED()        ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) != RESET) 
+#define __HAL_RCC_GPIOE_IS_CLK_ENABLED()        ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) != RESET)  
+#define __HAL_RCC_CRC_IS_CLK_ENABLED()          ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET)  
+#define __HAL_RCC_CCMDATARAMEN_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) != RESET)  
+
+#define __HAL_RCC_GPIOD_IS_CLK_DISABLED()        ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) == RESET) 
+#define __HAL_RCC_GPIOE_IS_CLK_DISABLED()        ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) == RESET)  
+#define __HAL_RCC_CRC_IS_CLK_DISABLED()          ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET)  
+#define __HAL_RCC_CCMDATARAMEN_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) == RESET)  
+/**
+  * @}
+  */ 
+  
+/** @defgroup RCCEx_AHB2_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable
+  * @brief  Enable or disable the AHB2 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before 
+  *         using it.
+  * @{
+  */
+#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE()  do {(RCC->AHB2ENR |= (RCC_AHB2ENR_OTGFSEN));\
+                                               __HAL_RCC_SYSCFG_CLK_ENABLE();\
+                                              }while(0U)
+                                        
+#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN))
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_AHB2_Peripheral_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enable Disable Status
+  * @brief  Get the enable or disable status of the AHB2 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  * @{
+  */
+#define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED()  ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) != RESET)
+#define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) == RESET)
+/**
+  * @}
+  */  
+  
+/** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable
+  * @brief  Enable or disable the Low Speed APB (APB1) peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  * @{
+  */
+#define __HAL_RCC_TIM2_CLK_ENABLE()     do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
+                                        UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_TIM3_CLK_ENABLE()     do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
+                                        UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_TIM4_CLK_ENABLE()     do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
+                                        UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_SPI3_CLK_ENABLE()     do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
+                                        UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_I2C3_CLK_ENABLE()     do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
+                                        UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_TIM2_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
+#define __HAL_RCC_TIM3_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
+#define __HAL_RCC_TIM4_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
+#define __HAL_RCC_SPI3_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
+#define __HAL_RCC_I2C3_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN))
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status
+  * @brief  Get the enable or disable status of the APB1 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  * @{
+  */
+#define __HAL_RCC_TIM2_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET) 
+#define __HAL_RCC_TIM3_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET) 
+#define __HAL_RCC_TIM4_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET) 
+#define __HAL_RCC_SPI3_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET) 
+#define __HAL_RCC_I2C3_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET)
+
+#define __HAL_RCC_TIM2_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET) 
+#define __HAL_RCC_TIM3_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET) 
+#define __HAL_RCC_TIM4_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET) 
+#define __HAL_RCC_SPI3_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET) 
+#define __HAL_RCC_I2C3_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET)
+/**
+  * @}
+  */ 
+  
+/** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable
+  * @brief  Enable or disable the High Speed APB (APB2) peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before 
+  *         using it.
+  * @{
+  */
+#define __HAL_RCC_SDIO_CLK_ENABLE()     do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
+                                        UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_SPI4_CLK_ENABLE()     do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
+                                        UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_TIM10_CLK_ENABLE()    do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
+                                        UNUSED(tmpreg); \
+                                      } while(0U)
+
+#define __HAL_RCC_SDIO_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN))
+#define __HAL_RCC_SPI4_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN))
+#define __HAL_RCC_TIM10_CLK_DISABLE()  (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN))
+/**
+  * @}
+  */
+  
+/** @defgroup RCCEx_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status
+  * @brief  Get the enable or disable status of the APB2 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  * @{
+  */
+#define __HAL_RCC_SDIO_IS_CLK_ENABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) != RESET)  
+#define __HAL_RCC_SPI4_IS_CLK_ENABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) != RESET)   
+#define __HAL_RCC_TIM10_IS_CLK_ENABLED()  ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) != RESET)  
+
+#define __HAL_RCC_SDIO_IS_CLK_DISABLED()  ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) == RESET)
+#define __HAL_RCC_SPI4_IS_CLK_DISABLED()  ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) == RESET) 
+#define __HAL_RCC_TIM10_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) == RESET) 
+/**
+  * @}
+  */
+/** @defgroup RCCEx_AHB1_Force_Release_Reset AHB1 Force Release Reset 
+  * @brief  Force or release AHB1 peripheral reset.
+  * @{
+  */  
+#define __HAL_RCC_AHB1_FORCE_RESET()    (RCC->AHB1RSTR = 0xFFFFFFFFU)
+#define __HAL_RCC_GPIOD_FORCE_RESET()   (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIODRST))
+#define __HAL_RCC_GPIOE_FORCE_RESET()   (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOERST))
+#define __HAL_RCC_CRC_FORCE_RESET()     (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST))
+
+#define __HAL_RCC_AHB1_RELEASE_RESET()  (RCC->AHB1RSTR = 0x00U)
+#define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST))
+#define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST))
+#define __HAL_RCC_CRC_RELEASE_RESET()   (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST))
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_AHB2_Force_Release_Reset AHB2 Force Release Reset 
+  * @brief  Force or release AHB2 peripheral reset.
+  * @{
+  */
+#define __HAL_RCC_AHB2_FORCE_RESET()    (RCC->AHB2RSTR = 0xFFFFFFFFU) 
+#define __HAL_RCC_USB_OTG_FS_FORCE_RESET()   (RCC->AHB2RSTR |= (RCC_AHB2RSTR_OTGFSRST))
+
+#define __HAL_RCC_AHB2_RELEASE_RESET()  (RCC->AHB2RSTR = 0x00U)
+#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST))
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset 
+  * @brief  Force or release APB1 peripheral reset.
+  * @{
+  */
+#define __HAL_RCC_APB1_FORCE_RESET()     (RCC->APB1RSTR = 0xFFFFFFFFU)  
+#define __HAL_RCC_TIM2_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST))
+#define __HAL_RCC_TIM3_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST))
+#define __HAL_RCC_TIM4_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST))
+#define __HAL_RCC_SPI3_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST))
+#define __HAL_RCC_I2C3_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C3RST))
+
+#define __HAL_RCC_APB1_RELEASE_RESET()   (RCC->APB1RSTR = 0x00U) 
+#define __HAL_RCC_TIM2_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
+#define __HAL_RCC_TIM3_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
+#define __HAL_RCC_TIM4_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
+#define __HAL_RCC_SPI3_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
+#define __HAL_RCC_I2C3_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST))
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset 
+  * @brief  Force or release APB2 peripheral reset.
+  * @{
+  */
+#define __HAL_RCC_APB2_FORCE_RESET()     (RCC->APB2RSTR = 0xFFFFFFFFU)  
+#define __HAL_RCC_SDIO_FORCE_RESET()     (RCC->APB2RSTR |= (RCC_APB2RSTR_SDIORST))
+#define __HAL_RCC_SPI4_FORCE_RESET()     (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI4RST))
+#define __HAL_RCC_TIM10_FORCE_RESET()    (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM10RST))
+
+#define __HAL_RCC_APB2_RELEASE_RESET()   (RCC->APB2RSTR = 0x00U)
+#define __HAL_RCC_SDIO_RELEASE_RESET()   (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST))
+#define __HAL_RCC_SPI4_RELEASE_RESET()   (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST))
+#define __HAL_RCC_TIM10_RELEASE_RESET()  (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST))
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_AHB3_Force_Release_Reset AHB3 Force Release Reset 
+  * @brief  Force or release AHB3 peripheral reset.
+  * @{
+  */ 
+#define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFFU)
+#define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00U) 
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable 
+  * @brief  Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wake-up from SLEEP mode, the peripheral clock is enabled again.
+  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
+  * @{
+  */
+#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE()    (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIODLPEN))
+#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE()    (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOELPEN))
+#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_CRCLPEN))
+#define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE()    (RCC->AHB1LPENR |= (RCC_AHB1LPENR_FLITFLPEN))
+#define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE()    (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM1LPEN))
+
+#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE()   (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN))
+#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE()   (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN))
+#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN))
+#define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE()   (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN))
+#define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE()   (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN))
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_AHB2_LowPower_Enable_Disable AHB2 Peripheral Low Power Enable Disable
+  * @brief  Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wake-up from SLEEP mode, the peripheral clock is enabled again.
+  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
+  * @{
+  */
+#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE()  (RCC->AHB2LPENR |= (RCC_AHB2LPENR_OTGFSLPEN))
+
+#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE()   (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN))
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable
+  * @brief  Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wake-up from SLEEP mode, the peripheral clock is enabled again.
+  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
+  * @{
+  */
+#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM2LPEN))
+#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM3LPEN))
+#define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM4LPEN))
+#define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI3LPEN))
+#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C3LPEN))
+
+#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN))
+#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN))
+#define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN))
+#define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN))
+#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN))
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable
+  * @brief  Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wake-up from SLEEP mode, the peripheral clock is enabled again.
+  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
+  * @{
+  */
+#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE()    (RCC->APB2LPENR |= (RCC_APB2LPENR_SDIOLPEN))
+#define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE()    (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI4LPEN))
+#define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE()   (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM10LPEN))
+
+#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE()   (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN))
+#define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE()   (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN))
+#define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE()  (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN))
+/**
+  * @}
+  */
+#endif /* STM32F401xC || STM32F401xE*/
+/*----------------------------------------------------------------------------*/
+
+/*-------------------------------- STM32F410xx -------------------------------*/
+#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
+/** @defgroup RCCEx_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable     
+  * @brief  Enables or disables the AHB1 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before 
+  *         using it.
+  * @{
+  */
+#define __HAL_RCC_CRC_CLK_ENABLE()     do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
+                                        UNUSED(tmpreg); \
+                                        } while(0U)
+#define __HAL_RCC_RNG_CLK_ENABLE()     do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_RNGEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_RNGEN);\
+                                        UNUSED(tmpreg); \
+                                        } while(0U)
+#define __HAL_RCC_CRC_CLK_DISABLE()     (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN))
+#define __HAL_RCC_RNG_CLK_DISABLE()     (RCC->AHB1ENR &= ~(RCC_AHB1ENR_RNGEN))
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status
+  * @brief  Get the enable or disable status of the AHB1 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  * @{
+  */
+#define __HAL_RCC_CRC_IS_CLK_ENABLED()     ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET)
+#define __HAL_RCC_RNG_IS_CLK_ENABLED()     ((RCC->AHB1ENR & (RCC_AHB1ENR_RNGEN)) != RESET)
+      
+#define __HAL_RCC_CRC_IS_CLK_DISABLED()    ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET)
+#define __HAL_RCC_RNG_IS_CLK_DISABLED()    ((RCC->AHB1ENR & (RCC_AHB1ENR_RNGEN)) == RESET)
+/**
+  * @}
+  */
+  
+/** @defgroup RCCEx_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable  
+  * @brief  Enable or disable the High Speed APB (APB1) peripheral clock.
+  * @{
+  */
+#define __HAL_RCC_TIM6_CLK_ENABLE()   do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_LPTIM1_CLK_ENABLE()   do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_RTCAPB_CLK_ENABLE()   do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_RTCAPBEN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_RTCAPBEN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_FMPI2C1_CLK_ENABLE() do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_FMPI2C1EN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_FMPI2C1EN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0U) 
+#define __HAL_RCC_DAC_CLK_ENABLE()   do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0U)
+                                        
+#define __HAL_RCC_TIM6_CLK_DISABLE()    (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
+#define __HAL_RCC_RTCAPB_CLK_DISABLE()  (RCC->APB1ENR &= ~(RCC_APB1ENR_RTCAPBEN))
+#define __HAL_RCC_LPTIM1_CLK_DISABLE()  (RCC->APB1ENR &= ~(RCC_APB1ENR_LPTIM1EN))
+#define __HAL_RCC_FMPI2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_FMPI2C1EN))
+#define __HAL_RCC_DAC_CLK_DISABLE()     (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
+/**
+  * @}
+  */
+  
+/** @defgroup RCCEx_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status
+  * @brief  Get the enable or disable status of the APB1 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  * @{
+  */  
+#define __HAL_RCC_TIM6_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET) 
+#define __HAL_RCC_RTCAPB_IS_CLK_ENABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_RTCAPBEN)) != RESET)
+#define __HAL_RCC_LPTIM1_IS_CLK_ENABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_LPTIM1EN)) != RESET) 
+#define __HAL_RCC_FMPI2C1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_FMPI2C1EN)) != RESET)  
+#define __HAL_RCC_DAC_IS_CLK_ENABLED()     ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET) 
+
+#define __HAL_RCC_TIM6_IS_CLK_DISABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET) 
+#define __HAL_RCC_RTCAPB_IS_CLK_DISABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_RTCAPBEN)) == RESET)
+#define __HAL_RCC_LPTIM1_IS_CLK_DISABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_LPTIM1EN)) == RESET) 
+#define __HAL_RCC_FMPI2C1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_FMPI2C1EN)) == RESET)  
+#define __HAL_RCC_DAC_IS_CLK_DISABLED()     ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET)  
+/**
+  * @}
+  */
+  
+/** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable  
+  * @brief  Enable or disable the High Speed APB (APB2) peripheral clock.
+  * @{
+  */  
+#define __HAL_RCC_SPI5_CLK_ENABLE()   do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_EXTIT_CLK_ENABLE()  do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->APB2ENR, RCC_APB2ENR_EXTITEN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_EXTITEN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_SPI5_CLK_DISABLE()    (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI5EN))
+#define __HAL_RCC_EXTIT_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_EXTITEN))
+/**
+  * @}
+  */
+  
+/** @defgroup RCCEx_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status
+  * @brief  Get the enable or disable status of the APB2 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  * @{
+  */
+#define __HAL_RCC_SPI5_IS_CLK_ENABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) != RESET)  
+#define __HAL_RCC_EXTIT_IS_CLK_ENABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_EXTITEN)) != RESET)  
+  
+#define __HAL_RCC_SPI5_IS_CLK_DISABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) == RESET)  
+#define __HAL_RCC_EXTIT_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_EXTITEN)) == RESET)  
+/**
+  * @}
+  */
+  
+/** @defgroup RCCEx_AHB1_Force_Release_Reset AHB1 Force Release Reset 
+  * @brief  Force or release AHB1 peripheral reset.
+  * @{
+  */
+#define __HAL_RCC_CRC_FORCE_RESET()     (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST))
+#define __HAL_RCC_RNG_FORCE_RESET()     (RCC->AHB1RSTR |= (RCC_AHB1RSTR_RNGRST))
+#define __HAL_RCC_CRC_RELEASE_RESET()   (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST))
+#define __HAL_RCC_RNG_RELEASE_RESET()   (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_RNGRST))
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_AHB2_Force_Release_Reset AHB2 Force Release Reset 
+  * @brief  Force or release AHB2 peripheral reset.
+  * @{
+  */
+#define __HAL_RCC_AHB2_FORCE_RESET()
+#define __HAL_RCC_AHB2_RELEASE_RESET()
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_AHB3_Force_Release_Reset AHB3 Force Release Reset 
+  * @brief  Force or release AHB3 peripheral reset.
+  * @{
+  */ 
+#define __HAL_RCC_AHB3_FORCE_RESET()
+#define __HAL_RCC_AHB3_RELEASE_RESET()
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset 
+  * @brief  Force or release APB1 peripheral reset.
+  * @{
+  */
+#define __HAL_RCC_TIM6_FORCE_RESET()      (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST))
+#define __HAL_RCC_LPTIM1_FORCE_RESET()    (RCC->APB1RSTR |= (RCC_APB1RSTR_LPTIM1RST))
+#define __HAL_RCC_FMPI2C1_FORCE_RESET()   (RCC->APB1RSTR |= (RCC_APB1RSTR_FMPI2C1RST))
+#define __HAL_RCC_DAC_FORCE_RESET()       (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST))
+
+#define __HAL_RCC_TIM6_RELEASE_RESET()    (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
+#define __HAL_RCC_LPTIM1_RELEASE_RESET()  (RCC->APB1RSTR &= ~(RCC_APB1RSTR_LPTIM1RST))
+#define __HAL_RCC_FMPI2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_FMPI2C1RST))
+#define __HAL_RCC_DAC_RELEASE_RESET()     (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset 
+  * @brief  Force or release APB2 peripheral reset.
+  * @{
+  */
+#define __HAL_RCC_SPI5_FORCE_RESET()      (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI5RST))
+#define __HAL_RCC_SPI5_RELEASE_RESET()    (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI5RST))                                        
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable  
+  * @brief  Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
+  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
+  * @{
+  */
+#define __HAL_RCC_RNG_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_RNGLPEN))
+#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_CRCLPEN))
+#define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE()    (RCC->AHB1LPENR |= (RCC_AHB1LPENR_FLITFLPEN))
+#define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE()    (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM1LPEN))
+
+#define __HAL_RCC_RNG_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_RNGLPEN))
+#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN))
+#define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE()   (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN))
+#define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE()   (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN))
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable                                         
+  * @brief  Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
+  * @{
+  */
+#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM6LPEN))
+#define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE()  (RCC->APB1LPENR |= (RCC_APB1LPENR_LPTIM1LPEN))
+#define __HAL_RCC_RTCAPB_CLK_SLEEP_ENABLE()  (RCC->APB1LPENR |= (RCC_APB1LPENR_RTCAPBLPEN))
+#define __HAL_RCC_FMPI2C1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_FMPI2C1LPEN))
+#define __HAL_RCC_DAC_CLK_SLEEP_ENABLE()     (RCC->APB1LPENR |= (RCC_APB1LPENR_DACLPEN))
+
+#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE()    (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN))
+#define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE()  (RCC->APB1LPENR &= ~(RCC_APB1LPENR_LPTIM1LPEN))
+#define __HAL_RCC_RTCAPB_CLK_SLEEP_DISABLE()  (RCC->APB1LPENR &= ~(RCC_APB1LPENR_RTCAPBLPEN))
+#define __HAL_RCC_FMPI2C1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_FMPI2C1LPEN))
+#define __HAL_RCC_DAC_CLK_SLEEP_DISABLE()     (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN))
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable                                         
+  * @brief  Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
+  * @{
+  */
+#define __HAL_RCC_SPI5_CLK_SLEEP_ENABLE()     (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI5LPEN))
+#define __HAL_RCC_EXTIT_CLK_SLEEP_ENABLE()    (RCC->APB2LPENR |= (RCC_APB2LPENR_EXTITLPEN))                                
+#define __HAL_RCC_SPI5_CLK_SLEEP_DISABLE()    (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI5LPEN))                                        
+#define __HAL_RCC_EXTIT_CLK_SLEEP_DISABLE()   (RCC->APB2LPENR &= ~(RCC_APB2LPENR_EXTITLPEN))
+/**
+  * @}
+  */
+
+#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
+/*----------------------------------------------------------------------------*/
+
+/*-------------------------------- STM32F411xx -------------------------------*/
+#if defined(STM32F411xE)
+/** @defgroup RCCEx_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable
+  * @brief  Enables or disables the AHB1 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before 
+  *         using it.
+  * @{
+  */
+#define __HAL_RCC_CCMDATARAMEN_CLK_ENABLE() do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\
+                                        UNUSED(tmpreg); \
+                                        } while(0U)
+#define __HAL_RCC_GPIOD_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
+                                        UNUSED(tmpreg); \
+                                        } while(0U)
+#define __HAL_RCC_GPIOE_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
+                                        UNUSED(tmpreg); \
+                                        } while(0U)
+#define __HAL_RCC_CRC_CLK_ENABLE()     do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
+                                        UNUSED(tmpreg); \
+                                        } while(0U)
+#define __HAL_RCC_GPIOD_CLK_DISABLE()           (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN))
+#define __HAL_RCC_GPIOE_CLK_DISABLE()           (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN))
+#define __HAL_RCC_CCMDATARAMEN_CLK_DISABLE()    (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CCMDATARAMEN))
+#define __HAL_RCC_CRC_CLK_DISABLE()             (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN))
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status
+  * @brief  Get the enable or disable status of the AHB1 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  * @{
+  */  
+#define __HAL_RCC_GPIOD_IS_CLK_ENABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) != RESET) 
+#define __HAL_RCC_GPIOE_IS_CLK_ENABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) != RESET) 
+#define __HAL_RCC_CCMDATARAMEN_IS_CLK_ENABLED()    ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) != RESET) 
+#define __HAL_RCC_CRC_IS_CLK_ENABLED()             ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET) 
+
+#define __HAL_RCC_GPIOD_IS_CLK_DISABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) == RESET) 
+#define __HAL_RCC_GPIOE_IS_CLK_DISABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) == RESET) 
+#define __HAL_RCC_CCMDATARAMEN_IS_CLK_DISABLED()    ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) == RESET) 
+#define __HAL_RCC_CRC_IS_CLK_DISABLED()             ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET) 
+/**
+  * @}
+  */
+  
+/** @defgroup RCCEX_AHB2_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable
+  * @brief  Enable or disable the AHB2 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before 
+  *         using it.
+  * @{
+  */
+#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE()  do {(RCC->AHB2ENR |= (RCC_AHB2ENR_OTGFSEN));\
+                                               __HAL_RCC_SYSCFG_CLK_ENABLE();\
+                                              }while(0U)
+
+#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN))
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_AHB2_Peripheral_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enable Disable Status
+  * @brief  Get the enable or disable status of the AHB2 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  * @{
+  */
+#define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED()  ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) != RESET)
+#define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) == RESET)
+/**
+  * @}
+  */  
+
+/** @defgroup RCCEx_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable
+  * @brief  Enable or disable the Low Speed APB (APB1) peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before 
+  *         using it. 
+  * @{
+  */
+#define __HAL_RCC_TIM2_CLK_ENABLE()     do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
+                                        UNUSED(tmpreg); \
+                                        } while(0U)
+#define __HAL_RCC_TIM3_CLK_ENABLE()     do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
+                                        UNUSED(tmpreg); \
+                                        } while(0U)
+#define __HAL_RCC_TIM4_CLK_ENABLE()     do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
+                                        UNUSED(tmpreg); \
+                                        } while(0U)
+#define __HAL_RCC_SPI3_CLK_ENABLE()     do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
+                                        UNUSED(tmpreg); \
+                                        } while(0U)
+#define __HAL_RCC_I2C3_CLK_ENABLE()     do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
+                                        UNUSED(tmpreg); \
+                                        } while(0U)
+#define __HAL_RCC_TIM2_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
+#define __HAL_RCC_TIM3_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
+#define __HAL_RCC_TIM4_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
+#define __HAL_RCC_SPI3_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
+#define __HAL_RCC_I2C3_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN))
+/**
+  * @}
+  */ 
+  
+/** @defgroup RCCEx_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status
+  * @brief  Get the enable or disable status of the APB1 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  * @{
+  */
+#define __HAL_RCC_TIM2_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET) 
+#define __HAL_RCC_TIM3_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET) 
+#define __HAL_RCC_TIM4_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET) 
+#define __HAL_RCC_SPI3_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET) 
+#define __HAL_RCC_I2C3_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET)
+
+#define __HAL_RCC_TIM2_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET) 
+#define __HAL_RCC_TIM3_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET) 
+#define __HAL_RCC_TIM4_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET) 
+#define __HAL_RCC_SPI3_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET) 
+#define __HAL_RCC_I2C3_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET) 
+/**
+  * @}
+  */ 
+  
+/** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable
+  * @brief  Enable or disable the High Speed APB (APB2) peripheral clock.
+  * @{
+  */
+#define __HAL_RCC_SPI5_CLK_ENABLE()   do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_SDIO_CLK_ENABLE()     do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
+                                        UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_SPI4_CLK_ENABLE()     do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
+                                        UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_TIM10_CLK_ENABLE()    do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
+                                        UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_SDIO_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN))
+#define __HAL_RCC_SPI4_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN))
+#define __HAL_RCC_TIM10_CLK_DISABLE()  (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN))
+#define __HAL_RCC_SPI5_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI5EN))
+/**
+  * @}
+  */
+  
+/** @defgroup RCCEx_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status
+  * @brief  Get the enable or disable status of the APB2 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  * @{
+  */
+#define __HAL_RCC_SDIO_IS_CLK_ENABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) != RESET)  
+#define __HAL_RCC_SPI4_IS_CLK_ENABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) != RESET)   
+#define __HAL_RCC_TIM10_IS_CLK_ENABLED()  ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) != RESET)  
+#define __HAL_RCC_SPI5_IS_CLK_ENABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) != RESET) 
+
+#define __HAL_RCC_SDIO_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) == RESET)  
+#define __HAL_RCC_SPI4_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) == RESET)   
+#define __HAL_RCC_TIM10_IS_CLK_DISABLED()  ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) == RESET)  
+#define __HAL_RCC_SPI5_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) == RESET)   
+/**
+  * @}
+  */  
+  
+/** @defgroup RCCEx_AHB1_Force_Release_Reset AHB1 Force Release Reset 
+  * @brief  Force or release AHB1 peripheral reset.
+  * @{
+  */ 
+#define __HAL_RCC_GPIOD_FORCE_RESET()   (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIODRST))
+#define __HAL_RCC_GPIOE_FORCE_RESET()   (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOERST))
+#define __HAL_RCC_CRC_FORCE_RESET()     (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST))
+
+#define __HAL_RCC_GPIOD_RELEASE_RESET()  (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST))
+#define __HAL_RCC_GPIOE_RELEASE_RESET()  (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST))
+#define __HAL_RCC_CRC_RELEASE_RESET()    (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST))
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_AHB2_Force_Release_Reset AHB2 Force Release Reset 
+  * @brief  Force or release AHB2 peripheral reset.
+  * @{
+  */
+#define __HAL_RCC_AHB2_FORCE_RESET()    (RCC->AHB2RSTR = 0xFFFFFFFFU) 
+#define __HAL_RCC_USB_OTG_FS_FORCE_RESET()   (RCC->AHB2RSTR |= (RCC_AHB2RSTR_OTGFSRST))
+
+#define __HAL_RCC_AHB2_RELEASE_RESET()  (RCC->AHB2RSTR = 0x00U)
+#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST))
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_AHB3_Force_Release_Reset AHB3 Force Release Reset 
+  * @brief  Force or release AHB3 peripheral reset.
+  * @{
+  */ 
+#define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFFU)
+#define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00U) 
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset 
+  * @brief  Force or release APB1 peripheral reset.
+  * @{
+  */
+#define __HAL_RCC_TIM2_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST))
+#define __HAL_RCC_TIM3_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST))
+#define __HAL_RCC_TIM4_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST))
+#define __HAL_RCC_SPI3_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST))
+#define __HAL_RCC_I2C3_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C3RST))
+
+#define __HAL_RCC_TIM2_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
+#define __HAL_RCC_TIM3_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
+#define __HAL_RCC_TIM4_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
+#define __HAL_RCC_SPI3_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
+#define __HAL_RCC_I2C3_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST))
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset 
+  * @brief  Force or release APB2 peripheral reset.
+  * @{
+  */
+#define __HAL_RCC_SPI5_FORCE_RESET()     (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI5RST))
+#define __HAL_RCC_SDIO_FORCE_RESET()     (RCC->APB2RSTR |= (RCC_APB2RSTR_SDIORST))
+#define __HAL_RCC_SPI4_FORCE_RESET()     (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI4RST))
+#define __HAL_RCC_TIM10_FORCE_RESET()    (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM10RST))
+
+#define __HAL_RCC_SDIO_RELEASE_RESET()   (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST))
+#define __HAL_RCC_SPI4_RELEASE_RESET()   (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST))
+#define __HAL_RCC_TIM10_RELEASE_RESET()  (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST))
+#define __HAL_RCC_SPI5_RELEASE_RESET()   (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI5RST))
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable 
+  * @brief  Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
+  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
+  * @{
+  */
+#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE()    (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIODLPEN))
+#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE()    (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOELPEN))
+#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_CRCLPEN))
+#define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE()    (RCC->AHB1LPENR |= (RCC_AHB1LPENR_FLITFLPEN))
+#define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE()    (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM1LPEN))
+                                        
+#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE()   (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN))                                        
+#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE()   (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN))
+#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN))
+#define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE()   (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN))
+#define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE()   (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN))
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_AHB2_LowPower_Enable_Disable AHB2 Peripheral Low Power Enable Disable
+  * @brief  Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wake-up from SLEEP mode, the peripheral clock is enabled again.
+  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
+  * @{
+  */
+#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE()  (RCC->AHB2LPENR |= (RCC_AHB2LPENR_OTGFSLPEN))
+#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE()   (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN))
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable 
+  * @brief  Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
+  * @{
+  */
+#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM2LPEN))
+#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM3LPEN))
+#define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM4LPEN))
+#define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI3LPEN))
+#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C3LPEN))
+
+#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN))
+#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN))
+#define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN))
+#define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN))
+#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN))
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable 
+  * @brief  Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
+  * @{
+  */
+#define __HAL_RCC_SPI5_CLK_SLEEP_ENABLE()    (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI5LPEN))
+#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE()    (RCC->APB2LPENR |= (RCC_APB2LPENR_SDIOLPEN))
+#define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE()    (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI4LPEN))
+#define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE()   (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM10LPEN))
+
+#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE()   (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN))
+#define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE()   (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN))
+#define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE()  (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN))
+#define __HAL_RCC_SPI5_CLK_SLEEP_DISABLE()   (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI5LPEN))
+/**
+  * @}
+  */
+#endif /* STM32F411xE */
+/*----------------------------------------------------------------------------*/
+
+/*---------------------------------- STM32F446xx -----------------------------*/
+#if defined(STM32F446xx)
+/** @defgroup RCCEx_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable
+  * @brief  Enables or disables the AHB1 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before 
+  *         using it.
+  * @{
+  */
+#define __HAL_RCC_BKPSRAM_CLK_ENABLE() do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
+                                        UNUSED(tmpreg); \
+                                        } while(0U)
+#define __HAL_RCC_CCMDATARAMEN_CLK_ENABLE() do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\
+                                        UNUSED(tmpreg); \
+                                        } while(0U)
+#define __HAL_RCC_CRC_CLK_ENABLE()     do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
+                                        UNUSED(tmpreg); \
+                                        } while(0U)
+#define __HAL_RCC_GPIOD_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
+                                        UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_GPIOE_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
+                                        UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_GPIOF_CLK_ENABLE()  do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_GPIOG_CLK_ENABLE()  do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_USB_OTG_HS_CLK_ENABLE()   do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE()   do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_GPIOD_CLK_DISABLE()           (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN))
+#define __HAL_RCC_GPIOE_CLK_DISABLE()           (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN))
+#define __HAL_RCC_GPIOF_CLK_DISABLE()           (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN))
+#define __HAL_RCC_GPIOG_CLK_DISABLE()           (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN))
+#define __HAL_RCC_USB_OTG_HS_CLK_DISABLE()      (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSEN))
+#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSULPIEN))
+#define __HAL_RCC_BKPSRAM_CLK_DISABLE()         (RCC->AHB1ENR &= ~(RCC_AHB1ENR_BKPSRAMEN))
+#define __HAL_RCC_CCMDATARAMEN_CLK_DISABLE()    (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CCMDATARAMEN))
+#define __HAL_RCC_CRC_CLK_DISABLE()             (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN))
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status
+  * @brief  Get the enable or disable status of the AHB1 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  * @{
+  */
+#define __HAL_RCC_GPIOD_IS_CLK_ENABLED()            ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) != RESET) 
+#define __HAL_RCC_GPIOE_IS_CLK_ENABLED()            ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) != RESET) 
+#define __HAL_RCC_GPIOF_IS_CLK_ENABLED()            ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) != RESET) 
+#define __HAL_RCC_GPIOG_IS_CLK_ENABLED()            ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) != RESET) 
+#define __HAL_RCC_USB_OTG_HS_IS_CLK_ENABLED()       ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) != RESET)  
+#define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_ENABLED()  ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN)) != RESET) 
+#define __HAL_RCC_BKPSRAM_IS_CLK_ENABLED()          ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) != RESET)  
+#define __HAL_RCC_CCMDATARAMEN_IS_CLK_ENABLED()     ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN))!= RESET)  
+#define __HAL_RCC_CRC_IS_CLK_ENABLED()              ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET) 
+
+#define __HAL_RCC_GPIOD_IS_CLK_DISABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) == RESET) 
+#define __HAL_RCC_GPIOE_IS_CLK_DISABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) == RESET) 
+#define __HAL_RCC_GPIOF_IS_CLK_DISABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) == RESET) 
+#define __HAL_RCC_GPIOG_IS_CLK_DISABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) == RESET) 
+#define __HAL_RCC_USB_OTG_HS_IS_CLK_DISABLED()      ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) == RESET)  
+#define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN)) == RESET) 
+#define __HAL_RCC_BKPSRAM_IS_CLK_DISABLED()         ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) == RESET)  
+#define __HAL_RCC_CCMDATARAMEN_IS_CLK_DISABLED()    ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) == RESET)  
+#define __HAL_RCC_CRC_IS_CLK_DISABLED()             ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET) 
+/**
+  * @}
+  */  
+  
+/** @defgroup RCCEx_AHB2_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable
+  * @brief  Enable or disable the AHB2 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before 
+  *         using it.
+  * @{
+  */
+#define __HAL_RCC_DCMI_CLK_ENABLE()   do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_DCMI_CLK_DISABLE()  (RCC->AHB2ENR &= ~(RCC_AHB2ENR_DCMIEN))
+#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE()  do {(RCC->AHB2ENR |= (RCC_AHB2ENR_OTGFSEN));\
+                                               __HAL_RCC_SYSCFG_CLK_ENABLE();\
+                                              }while(0U)
+                                        
+#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN))
+
+#define __HAL_RCC_RNG_CLK_ENABLE()    do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
+                                        UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_RNG_CLK_DISABLE()   (RCC->AHB2ENR &= ~(RCC_AHB2ENR_RNGEN))
+/**
+  * @}
+  */
+  
+/** @defgroup RCCEx_AHB2_Peripheral_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enable Disable Status
+  * @brief  Get the enable or disable status of the AHB2 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  * @{
+  */
+#define __HAL_RCC_DCMI_IS_CLK_ENABLED()        ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) != RESET)
+#define __HAL_RCC_DCMI_IS_CLK_DISABLED()       ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) == RESET)
+
+#define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED()  ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) != RESET)
+#define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) == RESET)
+
+#define __HAL_RCC_RNG_IS_CLK_ENABLED()    ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) != RESET) 
+#define __HAL_RCC_RNG_IS_CLK_DISABLED()   ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) == RESET) 
+/**
+  * @}
+  */
+  
+/** @defgroup RCCEx_AHB3_Clock_Enable_Disable AHB3 Peripheral Clock Enable Disable
+  * @brief  Enables or disables the AHB3 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before 
+  *         using it. 
+  * @{
+  */
+#define __HAL_RCC_FMC_CLK_ENABLE()    do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_QSPI_CLK_ENABLE()   do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0U)
+
+#define __HAL_RCC_FMC_CLK_DISABLE()    (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FMCEN))
+#define __HAL_RCC_QSPI_CLK_DISABLE()   (RCC->AHB3ENR &= ~(RCC_AHB3ENR_QSPIEN))
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_AHB3_Peripheral_Clock_Enable_Disable_Status AHB3 Peripheral Clock Enable Disable Status
+  * @brief  Get the enable or disable status of the AHB3 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  * @{
+  */
+#define __HAL_RCC_FMC_IS_CLK_ENABLED()   ((RCC->AHB3ENR & (RCC_AHB3ENR_FMCEN)) != RESET)
+#define __HAL_RCC_QSPI_IS_CLK_ENABLED()  ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) != RESET)
+
+#define __HAL_RCC_FMC_IS_CLK_DISABLED()  ((RCC->AHB3ENR & (RCC_AHB3ENR_FMCEN)) == RESET)
+#define __HAL_RCC_QSPI_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) == RESET)
+/**
+  * @}
+  */
+  
+/** @defgroup RCCEx_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable
+  * @brief  Enable or disable the Low Speed APB (APB1) peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before 
+  *         using it. 
+  * @{
+  */
+#define __HAL_RCC_TIM6_CLK_ENABLE()   do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_TIM7_CLK_ENABLE()   do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_TIM12_CLK_ENABLE()  do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_TIM13_CLK_ENABLE()  do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_TIM14_CLK_ENABLE()  do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_SPDIFRX_CLK_ENABLE() do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPDIFRXEN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPDIFRXEN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_USART3_CLK_ENABLE() do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_UART4_CLK_ENABLE()  do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_UART5_CLK_ENABLE()  do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_FMPI2C1_CLK_ENABLE() do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_FMPI2C1EN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_FMPI2C1EN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_CAN1_CLK_ENABLE()   do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_CAN2_CLK_ENABLE()   do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_CEC_CLK_ENABLE()    do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_DAC_CLK_ENABLE()    do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_TIM2_CLK_ENABLE()     do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
+                                        UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_TIM3_CLK_ENABLE()     do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
+                                        UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_TIM4_CLK_ENABLE()     do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
+                                        UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_SPI3_CLK_ENABLE()     do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
+                                        UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_I2C3_CLK_ENABLE()     do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
+                                        UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_TIM2_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
+#define __HAL_RCC_TIM3_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
+#define __HAL_RCC_TIM4_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
+#define __HAL_RCC_SPI3_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
+#define __HAL_RCC_I2C3_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN))
+#define __HAL_RCC_TIM6_CLK_DISABLE()    (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
+#define __HAL_RCC_TIM7_CLK_DISABLE()    (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
+#define __HAL_RCC_TIM12_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN))
+#define __HAL_RCC_TIM13_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN))
+#define __HAL_RCC_TIM14_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))
+#define __HAL_RCC_SPDIFRX_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_SPDIFRXEN))
+#define __HAL_RCC_USART3_CLK_DISABLE()  (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
+#define __HAL_RCC_UART4_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))
+#define __HAL_RCC_UART5_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))
+#define __HAL_RCC_FMPI2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_FMPI2C1EN))
+#define __HAL_RCC_CAN1_CLK_DISABLE()    (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN))
+#define __HAL_RCC_CAN2_CLK_DISABLE()    (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN))
+#define __HAL_RCC_CEC_CLK_DISABLE()     (RCC->APB1ENR &= ~(RCC_APB1ENR_CECEN))
+#define __HAL_RCC_DAC_CLK_DISABLE()     (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status
+  * @brief  Get the enable or disable status of the APB1 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  * @{
+  */
+#define __HAL_RCC_TIM2_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET)  
+#define __HAL_RCC_TIM3_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET)
+#define __HAL_RCC_TIM4_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET) 
+#define __HAL_RCC_SPI3_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET)
+#define __HAL_RCC_I2C3_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET)
+#define __HAL_RCC_TIM6_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET)
+#define __HAL_RCC_TIM7_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET)
+#define __HAL_RCC_TIM12_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) != RESET)
+#define __HAL_RCC_TIM13_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET)
+#define __HAL_RCC_TIM14_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET)
+#define __HAL_RCC_SPDIFRX_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPDIFRXEN)) != RESET)
+#define __HAL_RCC_USART3_IS_CLK_ENABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET)
+#define __HAL_RCC_UART4_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET)
+#define __HAL_RCC_UART5_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != RESET)
+#define __HAL_RCC_FMPI2C1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_FMPI2C1EN)) != RESET)
+#define __HAL_RCC_CAN1_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) != RESET)
+#define __HAL_RCC_CAN2_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) != RESET)
+#define __HAL_RCC_CEC_IS_CLK_ENABLED()     ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) != RESET)
+#define __HAL_RCC_DAC_IS_CLK_ENABLED()     ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET)
+
+#define __HAL_RCC_TIM2_IS_CLK_DISABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET)  
+#define __HAL_RCC_TIM3_IS_CLK_DISABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET)
+#define __HAL_RCC_TIM4_IS_CLK_DISABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET) 
+#define __HAL_RCC_SPI3_IS_CLK_DISABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET)
+#define __HAL_RCC_I2C3_IS_CLK_DISABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET)
+#define __HAL_RCC_TIM6_IS_CLK_DISABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET)
+#define __HAL_RCC_TIM7_IS_CLK_DISABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET)
+#define __HAL_RCC_TIM12_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) == RESET)
+#define __HAL_RCC_TIM13_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) == RESET)
+#define __HAL_RCC_TIM14_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET)
+#define __HAL_RCC_SPDIFRX_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPDIFRXEN)) == RESET)
+#define __HAL_RCC_USART3_IS_CLK_DISABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET)
+#define __HAL_RCC_UART4_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == RESET)
+#define __HAL_RCC_UART5_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == RESET)
+#define __HAL_RCC_FMPI2C1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_FMPI2C1EN)) == RESET)
+#define __HAL_RCC_CAN1_IS_CLK_DISABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) == RESET)
+#define __HAL_RCC_CAN2_IS_CLK_DISABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) == RESET)
+#define __HAL_RCC_CEC_IS_CLK_DISABLED()     ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) == RESET)
+#define __HAL_RCC_DAC_IS_CLK_DISABLED()     ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET)
+/**
+  * @}
+  */
+  
+/** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable
+  * @brief  Enable or disable the High Speed APB (APB2) peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before 
+  *         using it.
+  * @{
+  */
+#define __HAL_RCC_TIM8_CLK_ENABLE()   do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_ADC2_CLK_ENABLE()   do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_ADC3_CLK_ENABLE()   do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_SAI1_CLK_ENABLE()   do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_SAI2_CLK_ENABLE()   do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_SDIO_CLK_ENABLE()     do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
+                                        UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_SPI4_CLK_ENABLE()     do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
+                                        UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_TIM10_CLK_ENABLE()    do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
+                                        UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_SDIO_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN))
+#define __HAL_RCC_SPI4_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN))
+#define __HAL_RCC_TIM10_CLK_DISABLE()  (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN))
+#define __HAL_RCC_TIM8_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN))
+#define __HAL_RCC_ADC2_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN))
+#define __HAL_RCC_ADC3_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN))
+#define __HAL_RCC_SAI1_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI1EN))
+#define __HAL_RCC_SAI2_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI2EN))
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status
+  * @brief  Get the enable or disable status of the APB2 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  * @{
+  */
+#define __HAL_RCC_SDIO_IS_CLK_ENABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) != RESET) 
+#define __HAL_RCC_SPI4_IS_CLK_ENABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) != RESET) 
+#define __HAL_RCC_TIM10_IS_CLK_ENABLED()  ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) != RESET)  
+#define __HAL_RCC_TIM8_IS_CLK_ENABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) != RESET)
+#define __HAL_RCC_ADC2_IS_CLK_ENABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) != RESET) 
+#define __HAL_RCC_ADC3_IS_CLK_ENABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) != RESET) 
+#define __HAL_RCC_SAI1_IS_CLK_ENABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) != RESET)
+#define __HAL_RCC_SAI2_IS_CLK_ENABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_SAI2EN)) != RESET)
+
+#define __HAL_RCC_SDIO_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) == RESET) 
+#define __HAL_RCC_SPI4_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) == RESET) 
+#define __HAL_RCC_TIM10_IS_CLK_DISABLED()  ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) == RESET)  
+#define __HAL_RCC_TIM8_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) == RESET)
+#define __HAL_RCC_ADC2_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) == RESET) 
+#define __HAL_RCC_ADC3_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) == RESET) 
+#define __HAL_RCC_SAI1_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) == RESET)
+#define __HAL_RCC_SAI2_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_SAI2EN)) == RESET) 
+/**
+  * @}
+  */
+  
+/** @defgroup RCCEx_AHB1_Force_Release_Reset AHB1 Force Release Reset 
+  * @brief  Force or release AHB1 peripheral reset.
+  * @{
+  */
+#define __HAL_RCC_GPIOD_FORCE_RESET()    (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIODRST))
+#define __HAL_RCC_GPIOE_FORCE_RESET()    (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOERST))
+#define __HAL_RCC_GPIOF_FORCE_RESET()    (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOFRST))
+#define __HAL_RCC_GPIOG_FORCE_RESET()    (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOGRST))
+#define __HAL_RCC_USB_OTG_HS_FORCE_RESET()    (RCC->AHB1RSTR |= (RCC_AHB1RSTR_OTGHRST))
+#define __HAL_RCC_CRC_FORCE_RESET()      (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST))
+
+#define __HAL_RCC_GPIOD_RELEASE_RESET()  (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST))
+#define __HAL_RCC_GPIOE_RELEASE_RESET()  (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST))
+#define __HAL_RCC_GPIOF_RELEASE_RESET()  (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST))
+#define __HAL_RCC_GPIOG_RELEASE_RESET()  (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST))
+#define __HAL_RCC_USB_OTG_HS_RELEASE_RESET()  (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_OTGHRST))
+#define __HAL_RCC_CRC_RELEASE_RESET()    (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST))
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_AHB2_Force_Release_Reset AHB2 Force Release Reset 
+  * @brief  Force or release AHB2 peripheral reset.
+  * @{
+  */
+#define __HAL_RCC_AHB2_FORCE_RESET()    (RCC->AHB2RSTR = 0xFFFFFFFFU) 
+#define __HAL_RCC_USB_OTG_FS_FORCE_RESET()   (RCC->AHB2RSTR |= (RCC_AHB2RSTR_OTGFSRST))
+#define __HAL_RCC_RNG_FORCE_RESET()    (RCC->AHB2RSTR |= (RCC_AHB2RSTR_RNGRST))
+#define __HAL_RCC_DCMI_FORCE_RESET()   (RCC->AHB2RSTR |= (RCC_AHB2RSTR_DCMIRST))
+
+#define __HAL_RCC_AHB2_RELEASE_RESET()  (RCC->AHB2RSTR = 0x00U)
+#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST))
+#define __HAL_RCC_RNG_RELEASE_RESET()  (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_RNGRST))
+#define __HAL_RCC_DCMI_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_DCMIRST))
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_AHB3_Force_Release_Reset AHB3 Force Release Reset 
+  * @brief  Force or release AHB3 peripheral reset.
+  * @{
+  */ 
+#define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFFU)
+#define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00U) 
+
+#define __HAL_RCC_FMC_FORCE_RESET()    (RCC->AHB3RSTR |= (RCC_AHB3RSTR_FMCRST))
+#define __HAL_RCC_QSPI_FORCE_RESET()   (RCC->AHB3RSTR |= (RCC_AHB3RSTR_QSPIRST))
+
+#define __HAL_RCC_FMC_RELEASE_RESET()    (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FMCRST))
+#define __HAL_RCC_QSPI_RELEASE_RESET()   (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_QSPIRST))
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset 
+  * @brief  Force or release APB1 peripheral reset.
+  * @{
+  */
+#define __HAL_RCC_TIM6_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST))
+#define __HAL_RCC_TIM7_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST))
+#define __HAL_RCC_TIM12_FORCE_RESET()    (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM12RST))
+#define __HAL_RCC_TIM13_FORCE_RESET()    (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM13RST))
+#define __HAL_RCC_TIM14_FORCE_RESET()    (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST))
+#define __HAL_RCC_SPDIFRX_FORCE_RESET()  (RCC->APB1RSTR |= (RCC_APB1RSTR_SPDIFRXRST))
+#define __HAL_RCC_USART3_FORCE_RESET()   (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST))
+#define __HAL_RCC_UART4_FORCE_RESET()    (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST))
+#define __HAL_RCC_UART5_FORCE_RESET()    (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST))
+#define __HAL_RCC_FMPI2C1_FORCE_RESET()  (RCC->APB1RSTR |= (RCC_APB1RSTR_FMPI2C1RST))
+#define __HAL_RCC_CAN1_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN1RST))
+#define __HAL_RCC_CAN2_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN2RST))
+#define __HAL_RCC_CEC_FORCE_RESET()      (RCC->APB1RSTR |= (RCC_APB1RSTR_CECRST))
+#define __HAL_RCC_DAC_FORCE_RESET()      (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST))
+#define __HAL_RCC_TIM2_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST))
+#define __HAL_RCC_TIM3_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST))
+#define __HAL_RCC_TIM4_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST))
+#define __HAL_RCC_SPI3_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST))
+#define __HAL_RCC_I2C3_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C3RST))
+                                          
+#define __HAL_RCC_TIM2_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
+#define __HAL_RCC_TIM3_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
+#define __HAL_RCC_TIM4_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
+#define __HAL_RCC_SPI3_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
+#define __HAL_RCC_I2C3_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST))
+#define __HAL_RCC_TIM6_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
+#define __HAL_RCC_TIM7_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
+#define __HAL_RCC_TIM12_RELEASE_RESET()  (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST))
+#define __HAL_RCC_TIM13_RELEASE_RESET()  (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST))
+#define __HAL_RCC_TIM14_RELEASE_RESET()  (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))
+#define __HAL_RCC_SPDIFRX_RELEASE_RESET()  (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPDIFRXRST))
+#define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
+#define __HAL_RCC_UART4_RELEASE_RESET()  (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST))
+#define __HAL_RCC_UART5_RELEASE_RESET()  (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST))
+#define __HAL_RCC_FMPI2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_FMPI2C1RST))
+#define __HAL_RCC_CAN1_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST))
+#define __HAL_RCC_CAN2_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST))
+#define __HAL_RCC_CEC_RELEASE_RESET()    (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CECRST))
+#define __HAL_RCC_DAC_RELEASE_RESET()    (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset 
+  * @brief  Force or release APB2 peripheral reset.
+  * @{
+  */
+#define __HAL_RCC_TIM8_FORCE_RESET()     (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM8RST))
+#define __HAL_RCC_SAI1_FORCE_RESET()     (RCC->APB2RSTR |= (RCC_APB2RSTR_SAI1RST)) 
+#define __HAL_RCC_SAI2_FORCE_RESET()     (RCC->APB2RSTR |= (RCC_APB2RSTR_SAI2RST))
+#define __HAL_RCC_SDIO_FORCE_RESET()     (RCC->APB2RSTR |= (RCC_APB2RSTR_SDIORST))
+#define __HAL_RCC_SPI4_FORCE_RESET()     (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI4RST))
+#define __HAL_RCC_TIM10_FORCE_RESET()    (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM10RST))
+
+#define __HAL_RCC_SDIO_RELEASE_RESET()   (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST))
+#define __HAL_RCC_SPI4_RELEASE_RESET()   (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST))
+#define __HAL_RCC_TIM10_RELEASE_RESET()  (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST))
+#define __HAL_RCC_TIM8_RELEASE_RESET()   (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST))
+#define __HAL_RCC_SAI1_RELEASE_RESET()   (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI1RST))
+#define __HAL_RCC_SAI2_RELEASE_RESET()   (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI2RST)) 
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable 
+  * @brief  Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
+  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
+  * @{
+  */
+#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIODLPEN))
+#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOELPEN))
+#define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOFLPEN))
+#define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOGLPEN))
+#define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM2LPEN))
+#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSLPEN))
+#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE()  (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSULPILPEN))
+#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE()        (RCC->AHB1LPENR |= (RCC_AHB1LPENR_CRCLPEN))
+#define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_FLITFLPEN))
+#define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM1LPEN))
+#define __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE()    (RCC->AHB1LPENR |= (RCC_AHB1LPENR_BKPSRAMLPEN))
+
+#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN))
+#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN))
+#define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOFLPEN))
+#define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOGLPEN))
+#define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM2LPEN))
+#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSLPEN))
+#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSULPILPEN))
+#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE()       (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN))
+#define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN))
+#define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN))
+#define __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE()   (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_BKPSRAMLPEN))
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_AHB2_LowPower_Enable_Disable AHB2 Peripheral Low Power Enable Disable
+  * @brief  Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wake-up from SLEEP mode, the peripheral clock is enabled again.
+  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
+  * @{
+  */
+#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE()  (RCC->AHB2LPENR |= (RCC_AHB2LPENR_OTGFSLPEN))
+#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN))
+
+#define __HAL_RCC_RNG_CLK_SLEEP_ENABLE()   (RCC->AHB2LPENR |= (RCC_AHB2LPENR_RNGLPEN))
+#define __HAL_RCC_RNG_CLK_SLEEP_DISABLE()  (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_RNGLPEN))
+
+#define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE()  (RCC->AHB2LPENR |= (RCC_AHB2LPENR_DCMILPEN))
+#define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_DCMILPEN))
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_AHB3_LowPower_Enable_Disable AHB3 Peripheral Low Power Enable Disable
+  * @brief  Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
+  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
+  * @{
+  */
+#define __HAL_RCC_FMC_CLK_SLEEP_ENABLE()   (RCC->AHB3LPENR |= (RCC_AHB3LPENR_FMCLPEN))
+#define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE()  (RCC->AHB3LPENR |= (RCC_AHB3LPENR_QSPILPEN))
+
+#define __HAL_RCC_FMC_CLK_SLEEP_DISABLE()   (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_FMCLPEN))
+#define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE()  (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_QSPILPEN))
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable
+  * @brief  Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
+  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
+  * @{
+  */ 
+#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM6LPEN))
+#define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM7LPEN))
+#define __HAL_RCC_TIM12_CLK_SLEEP_ENABLE()   (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM12LPEN))
+#define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE()   (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM13LPEN))
+#define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE()   (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM14LPEN))
+#define __HAL_RCC_SPDIFRX_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPDIFRXLPEN))
+#define __HAL_RCC_USART3_CLK_SLEEP_ENABLE()  (RCC->APB1LPENR |= (RCC_APB1LPENR_USART3LPEN))
+#define __HAL_RCC_UART4_CLK_SLEEP_ENABLE()   (RCC->APB1LPENR |= (RCC_APB1LPENR_UART4LPEN))
+#define __HAL_RCC_UART5_CLK_SLEEP_ENABLE()   (RCC->APB1LPENR |= (RCC_APB1LPENR_UART5LPEN))
+#define __HAL_RCC_FMPI2C1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_FMPI2C1LPEN))
+#define __HAL_RCC_CAN1_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN1LPEN))
+#define __HAL_RCC_CAN2_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN2LPEN))
+#define __HAL_RCC_CEC_CLK_SLEEP_ENABLE()     (RCC->APB1LPENR |= (RCC_APB1LPENR_CECLPEN))
+#define __HAL_RCC_DAC_CLK_SLEEP_ENABLE()     (RCC->APB1LPENR |= (RCC_APB1LPENR_DACLPEN))
+#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM2LPEN))
+#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM3LPEN))
+#define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM4LPEN))
+#define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI3LPEN))
+#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C3LPEN))
+
+#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN))
+#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN))
+#define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN))
+#define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN))
+#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN))
+#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN))
+#define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN))
+#define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE()  (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM12LPEN))
+#define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE()  (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM13LPEN))
+#define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE()  (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM14LPEN))
+#define __HAL_RCC_SPDIFRX_CLK_SLEEP_DISABLE()(RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPDIFRXLPEN))
+#define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN))
+#define __HAL_RCC_UART4_CLK_SLEEP_DISABLE()  (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN))
+#define __HAL_RCC_UART5_CLK_SLEEP_DISABLE()  (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN))
+#define __HAL_RCC_FMPI2C1_CLK_SLEEP_DISABLE()(RCC->APB1LPENR &= ~(RCC_APB1LPENR_FMPI2C1LPEN))
+#define __HAL_RCC_CAN1_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN1LPEN))
+#define __HAL_RCC_CAN2_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN2LPEN))
+#define __HAL_RCC_CEC_CLK_SLEEP_DISABLE()    (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CECLPEN))
+#define __HAL_RCC_DAC_CLK_SLEEP_DISABLE()    (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN))
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable
+  * @brief  Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
+  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
+  * @{
+  */
+#define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM8LPEN))
+#define __HAL_RCC_ADC2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC2LPEN))
+#define __HAL_RCC_ADC3_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC3LPEN))
+#define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SAI1LPEN))
+#define __HAL_RCC_SAI2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SAI2LPEN))
+#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SDIOLPEN))
+#define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI4LPEN))
+#define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE()(RCC->APB2LPENR |= (RCC_APB2LPENR_TIM10LPEN))
+
+#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN))
+#define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN))
+#define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE()(RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN))
+#define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM8LPEN))
+#define __HAL_RCC_ADC2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC2LPEN))
+#define __HAL_RCC_ADC3_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC3LPEN))
+#define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI1LPEN))
+#define __HAL_RCC_SAI2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI2LPEN))
+/**
+  * @}
+  */
+
+#endif /* STM32F446xx */
+/*----------------------------------------------------------------------------*/
+
+/*-------STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx-------*/
+#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) 
+/** @defgroup RCCEx_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable
+  * @brief  Enables or disables the AHB1 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before 
+  *         using it.
+  * @{
+  */
+#if defined(STM32F412Rx) || defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx) 
+#define __HAL_RCC_GPIOD_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
+                                        UNUSED(tmpreg); \
+                                      } while(0U)
+#endif /* STM32F412Rx || STM32F412Vx || STM32F412Zx ||  STM32F413xx || STM32F423xx */
+#if defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx) 
+#define __HAL_RCC_GPIOE_CLK_ENABLE()    do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
+                                        UNUSED(tmpreg); \
+                                      } while(0U)
+#endif /* STM32F412Vx || STM32F412Zx ||  STM32F413xx || STM32F423xx */
+#if defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx)                                        
+#define __HAL_RCC_GPIOF_CLK_ENABLE()  do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_GPIOG_CLK_ENABLE()  do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0U)
+#endif /*  STM32F412Zx || STM32F413xx || STM32F423xx */                                       
+#define __HAL_RCC_CRC_CLK_ENABLE()  do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0U)                                        
+#if defined(STM32F412Rx) || defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx) 
+#define __HAL_RCC_GPIOD_CLK_DISABLE()        (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN))
+#endif /* STM32F412Rx || STM32F412Vx || STM32F412Zx ||  STM32F413xx || STM32F423xx */
+#if defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx) 
+#define __HAL_RCC_GPIOE_CLK_DISABLE()        (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN))
+#endif /* STM32F412Vx || STM32F412Zx ||  STM32F413xx || STM32F423xx */
+#if defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx)
+#define __HAL_RCC_GPIOF_CLK_DISABLE()        (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN))
+#define __HAL_RCC_GPIOG_CLK_DISABLE()        (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN))
+#endif /*  STM32F412Zx || STM32F413xx || STM32F423xx */
+#define __HAL_RCC_CRC_CLK_DISABLE()          (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN))
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status
+  * @brief  Get the enable or disable status of the AHB1 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  * @{
+  */
+#if defined(STM32F412Rx) || defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx)
+#define __HAL_RCC_GPIOD_IS_CLK_ENABLED()     ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) != RESET)
+#endif /* STM32F412Rx || STM32F412Vx || STM32F412Zx ||  STM32F413xx || STM32F423xx */
+#if defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx)
+#define __HAL_RCC_GPIOE_IS_CLK_ENABLED()     ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) != RESET)
+#endif /* STM32F412Vx || STM32F412Zx ||  STM32F413xx || STM32F423xx */
+#if defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx)
+#define __HAL_RCC_GPIOF_IS_CLK_ENABLED()     ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) != RESET)
+#define __HAL_RCC_GPIOG_IS_CLK_ENABLED()     ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) != RESET)
+#endif /*  STM32F412Zx || STM32F413xx || STM32F423xx */
+#define __HAL_RCC_CRC_IS_CLK_ENABLED()       ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET)
+
+#if defined(STM32F412Rx) || defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx)
+#define __HAL_RCC_GPIOD_IS_CLK_DISABLED()     ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) == RESET)
+#endif /* STM32F412Rx || STM32F412Vx || STM32F412Zx ||  STM32F413xx || STM32F423xx */
+#if defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx)
+#define __HAL_RCC_GPIOE_IS_CLK_DISABLED()     ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) == RESET)
+#endif /* STM32F412Vx || STM32F412Zx ||  STM32F413xx || STM32F423xx */
+#if defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx)
+#define __HAL_RCC_GPIOF_IS_CLK_DISABLED()     ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) == RESET)
+#define __HAL_RCC_GPIOG_IS_CLK_DISABLED()     ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) == RESET)
+#endif /*  STM32F412Zx || STM32F413xx || STM32F423xx */
+#define __HAL_RCC_CRC_IS_CLK_DISABLED()       ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET)
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_AHB2_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable
+  * @brief  Enable or disable the AHB2 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before 
+  *         using it.
+  * @{
+  */
+#if defined(STM32F423xx)
+#define __HAL_RCC_AES_CLK_ENABLE()   do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0U)
+
+#define __HAL_RCC_AES_CLK_DISABLE()  (RCC->AHB2ENR &= ~(RCC_AHB2ENR_AESEN))
+#endif /* STM32F423xx */
+                                        
+#define __HAL_RCC_RNG_CLK_ENABLE()    do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
+                                        UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_RNG_CLK_DISABLE()   (RCC->AHB2ENR &= ~(RCC_AHB2ENR_RNGEN))
+                                     
+#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE()  do {(RCC->AHB2ENR |= (RCC_AHB2ENR_OTGFSEN));\
+                                               __HAL_RCC_SYSCFG_CLK_ENABLE();\
+                                              }while(0U)
+                                        
+#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN))
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_AHB2_Peripheral_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enable Disable Status
+  * @brief  Get the enable or disable status of the AHB2 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  * @{
+  */
+#if defined(STM32F423xx)
+#define __HAL_RCC_AES_IS_CLK_ENABLED()        ((RCC->AHB2ENR & (RCC_AHB2ENR_AESEN)) != RESET)
+#define __HAL_RCC_AES_IS_CLK_DISABLED()       ((RCC->AHB2ENR & (RCC_AHB2ENR_AESEN)) == RESET)
+#endif /* STM32F423xx */
+                                        
+#define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED()  ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) != RESET)
+#define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) == RESET)
+          
+#define __HAL_RCC_RNG_IS_CLK_ENABLED()         ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) != RESET)   
+#define __HAL_RCC_RNG_IS_CLK_DISABLED()        ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) == RESET)   
+/**
+  * @}
+  */  
+
+/** @defgroup RCCEx_AHB3_Clock_Enable_Disable AHB3 Peripheral Clock Enable Disable
+  * @brief  Enables or disables the AHB3 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before 
+  *         using it. 
+  * @{
+  */
+#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx)
+#define __HAL_RCC_FSMC_CLK_ENABLE()    do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_QSPI_CLK_ENABLE()   do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0U)
+
+#define __HAL_RCC_FSMC_CLK_DISABLE()    (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FSMCEN))
+#define __HAL_RCC_QSPI_CLK_DISABLE()    (RCC->AHB3ENR &= ~(RCC_AHB3ENR_QSPIEN))
+#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F413xx || STM32F423xx */ 
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_AHB3_Peripheral_Clock_Enable_Disable_Status AHB3 Peripheral Clock Enable Disable Status
+  * @brief  Get the enable or disable status of the AHB3 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  * @{
+  */
+#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx)
+#define __HAL_RCC_FSMC_IS_CLK_ENABLED()  ((RCC->AHB3ENR & (RCC_AHB3ENR_FSMCEN)) != RESET) 
+#define __HAL_RCC_QSPI_IS_CLK_ENABLED()  ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) != RESET) 
+
+#define __HAL_RCC_FSMC_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FSMCEN)) == RESET)
+#define __HAL_RCC_QSPI_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) == RESET)
+#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F413xx || STM32F423xx */
+
+/**
+  * @}
+  */
+  
+/** @defgroup RCCEx_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable
+  * @brief  Enable or disable the Low Speed APB (APB1) peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before 
+  *         using it. 
+  * @{
+  */
+#define __HAL_RCC_TIM6_CLK_ENABLE()   do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_TIM7_CLK_ENABLE()   do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_TIM12_CLK_ENABLE()  do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_TIM13_CLK_ENABLE()  do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_TIM14_CLK_ENABLE()  do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0U)
+#if defined(STM32F413xx) || defined(STM32F423xx)                                        
+#define __HAL_RCC_LPTIM1_CLK_ENABLE()   do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0U)
+#endif /* STM32F413xx || STM32F423xx */  
+#define __HAL_RCC_RTCAPB_CLK_ENABLE()  do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_RTCAPBEN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_RTCAPBEN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_USART3_CLK_ENABLE() do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0U)
+
+#if defined(STM32F413xx) || defined(STM32F423xx)
+#define __HAL_RCC_UART4_CLK_ENABLE()  do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_UART5_CLK_ENABLE()  do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0U)
+#endif /* STM32F413xx || STM32F423xx */
+                                        
+#define __HAL_RCC_FMPI2C1_CLK_ENABLE() do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_FMPI2C1EN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_FMPI2C1EN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_CAN1_CLK_ENABLE()   do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_CAN2_CLK_ENABLE()   do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0U)
+#if defined(STM32F413xx) || defined(STM32F423xx)
+#define __HAL_RCC_CAN3_CLK_ENABLE()  do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN3EN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN3EN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0U)
+#endif /* STM32F413xx || STM32F423xx */
+#define __HAL_RCC_TIM2_CLK_ENABLE()     do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
+                                        UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_TIM3_CLK_ENABLE()     do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
+                                        UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_TIM4_CLK_ENABLE()     do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
+                                        UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_SPI3_CLK_ENABLE()     do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
+                                        UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_I2C3_CLK_ENABLE()     do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
+                                        UNUSED(tmpreg); \
+                                      } while(0U)
+#if defined(STM32F413xx) || defined(STM32F423xx)
+#define __HAL_RCC_DAC_CLK_ENABLE()    do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_UART7_CLK_ENABLE()  do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART7EN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART7EN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_UART8_CLK_ENABLE()  do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART8EN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART8EN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0U)
+#endif /* STM32F413xx || STM32F423xx */
+                                        
+#define __HAL_RCC_TIM2_CLK_DISABLE()    (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
+#define __HAL_RCC_TIM3_CLK_DISABLE()    (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
+#define __HAL_RCC_TIM4_CLK_DISABLE()    (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
+#define __HAL_RCC_TIM6_CLK_DISABLE()    (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
+#define __HAL_RCC_TIM7_CLK_DISABLE()    (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
+#define __HAL_RCC_TIM12_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN))
+#define __HAL_RCC_TIM13_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN))
+#define __HAL_RCC_TIM14_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN)) 
+#if defined(STM32F413xx) || defined(STM32F423xx)                 
+#define __HAL_RCC_LPTIM1_CLK_DISABLE()  (RCC->APB1ENR &= ~(RCC_APB1ENR_LPTIM1EN))
+#endif /* STM32F413xx || STM32F423xx */
+#define __HAL_RCC_RTCAPB_CLK_DISABLE()  (RCC->APB1ENR &= ~(RCC_APB1ENR_RTCAPBEN))                                       
+#define __HAL_RCC_SPI3_CLK_DISABLE()    (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
+#define __HAL_RCC_USART3_CLK_DISABLE()  (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
+#if defined(STM32F413xx) || defined(STM32F423xx)   
+#define __HAL_RCC_UART4_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))
+#define __HAL_RCC_UART5_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))
+#endif /* STM32F413xx || STM32F423xx */                                        
+#define __HAL_RCC_I2C3_CLK_DISABLE()    (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN))
+#define __HAL_RCC_FMPI2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_FMPI2C1EN))
+#define __HAL_RCC_CAN1_CLK_DISABLE()    (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN))
+#define __HAL_RCC_CAN2_CLK_DISABLE()    (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN))
+#if defined(STM32F413xx) || defined(STM32F423xx)
+#define __HAL_RCC_CAN3_CLK_DISABLE()    (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN3EN))                                        
+#define __HAL_RCC_DAC_CLK_DISABLE()     (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
+#define __HAL_RCC_UART7_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_UART7EN))
+#define __HAL_RCC_UART8_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_UART8EN))
+#endif /* STM32F413xx || STM32F423xx */                                        
+                                        
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status
+  * @brief  Get the enable or disable status of the APB1 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  * @{
+  */
+#define __HAL_RCC_TIM2_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET) 
+#define __HAL_RCC_TIM3_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET)
+#define __HAL_RCC_TIM4_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET)
+#define __HAL_RCC_TIM6_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET)
+#define __HAL_RCC_TIM7_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET)
+#define __HAL_RCC_TIM12_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) != RESET)
+#define __HAL_RCC_TIM13_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET)
+#define __HAL_RCC_TIM14_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET) 
+#if defined(STM32F413xx) || defined(STM32F423xx)
+#define __HAL_RCC_LPTIM1_IS_CLK_ENABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_LPTIM1EN)) != RESET) 
+#endif /* STM32F413xx || STM32F423xx */                                            
+#define __HAL_RCC_RTCAPB_IS_CLK_ENABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_RTCAPBEN)) != RESET)                                    
+#define __HAL_RCC_SPI3_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET)
+#define __HAL_RCC_USART3_IS_CLK_ENABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET)
+#if defined(STM32F413xx) || defined(STM32F423xx)
+#define __HAL_RCC_UART4_IS_CLK_ENABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET) 
+#define __HAL_RCC_UART5_IS_CLK_ENABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != RESET) 
+#endif /* STM32F413xx || STM32F423xx */                                        
+#define __HAL_RCC_I2C3_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET)
+#define __HAL_RCC_FMPI2C1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_FMPI2C1EN)) != RESET)
+#define __HAL_RCC_CAN1_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN))!= RESET)
+#define __HAL_RCC_CAN2_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) != RESET)
+#if defined(STM32F413xx) || defined(STM32F423xx)
+#define __HAL_RCC_CAN3_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_CAN3EN)) != RESET)
+#define __HAL_RCC_DAC_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET) 
+#define __HAL_RCC_UART7_IS_CLK_ENABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_UART7EN)) != RESET)
+#define __HAL_RCC_UART8_IS_CLK_ENABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_UART8EN)) != RESET) 
+#endif /* STM32F413xx || STM32F423xx */                                         
+
+#define __HAL_RCC_TIM2_IS_CLK_DISABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET) 
+#define __HAL_RCC_TIM3_IS_CLK_DISABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET)
+#define __HAL_RCC_TIM4_IS_CLK_DISABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET)
+#define __HAL_RCC_TIM6_IS_CLK_DISABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET)
+#define __HAL_RCC_TIM7_IS_CLK_DISABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET)
+#define __HAL_RCC_TIM12_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) == RESET)
+#define __HAL_RCC_TIM13_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) == RESET)
+#define __HAL_RCC_TIM14_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET)
+#if defined(STM32F413xx) || defined(STM32F423xx)                                          
+#define __HAL_RCC_LPTIM1_IS_CLK_DISABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_LPTIM1EN)) == RESET) 
+#endif /* STM32F413xx || STM32F423xx */                                         
+#define __HAL_RCC_RTCAPB_IS_CLK_DISABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_RTCAPBEN)) == RESET)                                        
+#define __HAL_RCC_SPI3_IS_CLK_DISABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET)
+#define __HAL_RCC_USART3_IS_CLK_DISABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET)
+#if defined(STM32F413xx) || defined(STM32F423xx)                                           
+#define __HAL_RCC_UART4_IS_CLK_DISABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == RESET) 
+#define __HAL_RCC_UART5_IS_CLK_DISABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == RESET) 
+#endif /* STM32F413xx || STM32F423xx */                                          
+#define __HAL_RCC_I2C3_IS_CLK_DISABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET)
+#define __HAL_RCC_FMPI2C1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_FMPI2C1EN)) == RESET)
+#define __HAL_RCC_CAN1_IS_CLK_DISABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) == RESET)
+#define __HAL_RCC_CAN2_IS_CLK_DISABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) == RESET)
+#if defined(STM32F413xx) || defined(STM32F423xx)                                        
+#define __HAL_RCC_CAN3_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_CAN3EN)) == RESET)
+#define __HAL_RCC_DAC_IS_CLK_DISABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET) 
+#define __HAL_RCC_UART7_IS_CLK_DISABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_UART7EN)) == RESET)
+#define __HAL_RCC_UART8_IS_CLK_DISABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_UART8EN)) == RESET)
+#endif /* STM32F413xx || STM32F423xx */                                         
+/**
+  * @}
+  */  
+/** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable
+  * @brief  Enable or disable the High Speed APB (APB2) peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before 
+  *         using it.
+  * @{
+  */
+#define __HAL_RCC_TIM8_CLK_ENABLE()   do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0U)
+#if defined(STM32F413xx) || defined(STM32F423xx)
+#define __HAL_RCC_UART9_CLK_ENABLE()   do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->APB2ENR, RCC_APB2ENR_UART9EN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_UART9EN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_UART10_CLK_ENABLE()  do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->APB2ENR, RCC_APB2ENR_UART10EN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_UART10EN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0U)                                          
+#endif /* STM32F413xx || STM32F423xx */                                   
+#define __HAL_RCC_SDIO_CLK_ENABLE()     do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
+                                        UNUSED(tmpreg); \
+                                      } while(0U) 
+#define __HAL_RCC_SPI4_CLK_ENABLE()     do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
+                                        UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_EXTIT_CLK_ENABLE()  do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->APB2ENR, RCC_APB2ENR_EXTITEN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_EXTITEN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0U)                                        
+#define __HAL_RCC_TIM10_CLK_ENABLE()    do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
+                                        UNUSED(tmpreg); \
+                                      } while(0U) 
+#define __HAL_RCC_SPI5_CLK_ENABLE()   do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0U)
+#if defined(STM32F413xx) || defined(STM32F423xx)
+#define __HAL_RCC_SAI1_CLK_ENABLE()   do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0U)                                         
+#endif /* STM32F413xx || STM32F423xx */                                          
+#define __HAL_RCC_DFSDM1_CLK_ENABLE() do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0U)
+#if defined(STM32F413xx) || defined(STM32F423xx)
+#define __HAL_RCC_DFSDM2_CLK_ENABLE() do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM2EN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM2EN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0U)                                        
+#endif /* STM32F413xx || STM32F423xx */                                        
+ 
+#define __HAL_RCC_TIM8_CLK_DISABLE()    (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN))
+#if defined(STM32F413xx) || defined(STM32F423xx)
+#define __HAL_RCC_UART9_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_UART9EN))
+#define __HAL_RCC_UART10_CLK_DISABLE()  (RCC->APB2ENR &= ~(RCC_APB2ENR_UART10EN))                                        
+#endif /* STM32F413xx || STM32F423xx */                                         
+#define __HAL_RCC_SDIO_CLK_DISABLE()    (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN))
+#define __HAL_RCC_SPI4_CLK_DISABLE()    (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN))
+#define __HAL_RCC_EXTIT_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_EXTITEN))
+#define __HAL_RCC_TIM10_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN))
+#define __HAL_RCC_SPI5_CLK_DISABLE()    (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI5EN))
+#if defined(STM32F413xx) || defined(STM32F423xx)
+#define __HAL_RCC_SAI1_CLK_DISABLE()    (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI1EN))                                        
+#endif /* STM32F413xx || STM32F423xx */                                        
+#define __HAL_RCC_DFSDM1_CLK_DISABLE()  (RCC->APB2ENR &= ~(RCC_APB2ENR_DFSDM1EN))
+#if defined(STM32F413xx) || defined(STM32F423xx)
+#define __HAL_RCC_DFSDM2_CLK_DISABLE()  (RCC->APB2ENR &= ~(RCC_APB2ENR_DFSDM2EN))                                      
+#endif /* STM32F413xx || STM32F423xx */                                         
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status
+  * @brief  Get the enable or disable status of the APB2 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  * @{
+  */
+#define __HAL_RCC_TIM8_IS_CLK_ENABLED()      ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) != RESET)
+#if defined(STM32F413xx) || defined(STM32F423xx)
+#define __HAL_RCC_UART9_IS_CLK_ENABLED()     ((RCC->APB2ENR & (RCC_APB2ENR_UART9EN)) != RESET)
+#define __HAL_RCC_UART10_IS_CLK_ENABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_UART10EN)) != RESET)                                        
+#endif /* STM32F413xx || STM32F423xx */                                          
+#define __HAL_RCC_SDIO_IS_CLK_ENABLED()      ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) != RESET) 
+#define __HAL_RCC_SPI4_IS_CLK_ENABLED()      ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) != RESET)
+#define __HAL_RCC_EXTIT_IS_CLK_ENABLED()     ((RCC->APB2ENR & (RCC_APB2ENR_EXTITEN)) != RESET)
+#define __HAL_RCC_TIM10_IS_CLK_ENABLED()     ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) != RESET)
+#define __HAL_RCC_SPI5_IS_CLK_ENABLED()      ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) != RESET)
+#if defined(STM32F413xx) || defined(STM32F423xx)
+#define __HAL_RCC_SAI1_IS_CLK_ENABLED()     ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) != RESET)                                    
+#endif /* STM32F413xx || STM32F423xx */                                         
+#define __HAL_RCC_DFSDM1_IS_CLK_ENABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_DFSDM1EN)) != RESET)
+#if defined(STM32F413xx) || defined(STM32F423xx)
+#define __HAL_RCC_DFSDM2_IS_CLK_ENABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_DFSDM2EN)) != RESET)                                  
+#endif /* STM32F413xx || STM32F423xx */                                         
+
+#define __HAL_RCC_TIM8_IS_CLK_DISABLED()     ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) == RESET)
+#if defined(STM32F413xx) || defined(STM32F423xx)
+#define __HAL_RCC_UART9_IS_CLK_DISABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_UART9EN)) == RESET) 
+#define __HAL_RCC_UART10_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_UART10EN)) == RESET)                                         
+#endif /* STM32F413xx || STM32F423xx */                                         
+#define __HAL_RCC_SDIO_IS_CLK_DISABLED()     ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) == RESET) 
+#define __HAL_RCC_SPI4_IS_CLK_DISABLED()     ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) == RESET)
+#define __HAL_RCC_EXTIT_IS_CLK_DISABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_EXTITEN)) == RESET)
+#define __HAL_RCC_TIM10_IS_CLK_DISABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) == RESET)
+#define __HAL_RCC_SPI5_IS_CLK_DISABLED()     ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) == RESET)
+#if defined(STM32F413xx) || defined(STM32F423xx)
+#define __HAL_RCC_SAI1_IS_CLK_DISABLED()     ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) == RESET)                                       
+#endif /* STM32F413xx || STM32F423xx */                                        
+#define __HAL_RCC_DFSDM1_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_DFSDM1EN)) == RESET)
+#if defined(STM32F413xx) || defined(STM32F423xx)
+#define __HAL_RCC_DFSDM2_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_DFSDM2EN)) == RESET)                                       
+#endif /* STM32F413xx || STM32F423xx */                                         
+/**
+  * @}
+  */
+  
+/** @defgroup RCCEx_AHB1_Force_Release_Reset AHB1 Force Release Reset 
+  * @brief  Force or release AHB1 peripheral reset.
+  * @{
+  */
+#if defined(STM32F412Rx) || defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx)
+#define __HAL_RCC_GPIOD_FORCE_RESET()    (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIODRST))
+#endif /* STM32F412Rx || STM32F412Vx || STM32F412Zx ||  STM32F413xx || STM32F423xx */
+#if defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx)
+#define __HAL_RCC_GPIOE_FORCE_RESET()    (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOERST))
+#endif /* STM32F412Vx || STM32F412Zx ||  STM32F413xx || STM32F423xx */
+#if defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx)
+#define __HAL_RCC_GPIOF_FORCE_RESET()    (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOFRST))
+#define __HAL_RCC_GPIOG_FORCE_RESET()    (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOGRST))
+#endif /*  STM32F412Zx || STM32F413xx || STM32F423xx */
+#define __HAL_RCC_CRC_FORCE_RESET()      (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST))
+
+#if defined(STM32F412Rx) || defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx)
+#define __HAL_RCC_GPIOD_RELEASE_RESET()  (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST))
+#endif /* STM32F412Rx || STM32F412Vx || STM32F412Zx ||  STM32F413xx || STM32F423xx */
+#if defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx)
+#define __HAL_RCC_GPIOE_RELEASE_RESET()  (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST))
+#endif /* STM32F412Vx || STM32F412Zx ||  STM32F413xx || STM32F423xx */
+#if defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx)
+#define __HAL_RCC_GPIOF_RELEASE_RESET()  (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST))
+#define __HAL_RCC_GPIOG_RELEASE_RESET()  (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST))
+#endif /*  STM32F412Zx || STM32F413xx || STM32F423xx */
+#define __HAL_RCC_CRC_RELEASE_RESET()    (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST))
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_AHB2_Force_Release_Reset AHB2 Force Release Reset 
+  * @brief  Force or release AHB2 peripheral reset.
+  * @{
+  */
+#define __HAL_RCC_AHB2_FORCE_RESET()    (RCC->AHB2RSTR = 0xFFFFFFFFU)
+#define __HAL_RCC_AHB2_RELEASE_RESET()  (RCC->AHB2RSTR = 0x00U)
+
+#if defined(STM32F423xx)
+#define __HAL_RCC_AES_FORCE_RESET()    (RCC->AHB2RSTR |= (RCC_AHB2RSTR_AESRST))
+#define __HAL_RCC_AES_RELEASE_RESET()  (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_AESRST))                                        
+#endif /* STM32F423xx */ 
+                                        
+#define __HAL_RCC_USB_OTG_FS_FORCE_RESET()   (RCC->AHB2RSTR |= (RCC_AHB2RSTR_OTGFSRST))
+#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST))
+
+#define __HAL_RCC_RNG_FORCE_RESET()    (RCC->AHB2RSTR |= (RCC_AHB2RSTR_RNGRST))
+#define __HAL_RCC_RNG_RELEASE_RESET()  (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_RNGRST))
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_AHB3_Force_Release_Reset AHB3 Force Release Reset 
+  * @brief  Force or release AHB3 peripheral reset.
+  * @{
+  */ 
+#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx)
+#define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFFU)
+#define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00U) 
+
+#define __HAL_RCC_FSMC_FORCE_RESET()    (RCC->AHB3RSTR |= (RCC_AHB3RSTR_FSMCRST))
+#define __HAL_RCC_QSPI_FORCE_RESET()   (RCC->AHB3RSTR |= (RCC_AHB3RSTR_QSPIRST))
+
+#define __HAL_RCC_FSMC_RELEASE_RESET()    (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FSMCRST))
+#define __HAL_RCC_QSPI_RELEASE_RESET()   (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_QSPIRST))
+#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F413xx || STM32F423xx */ 
+#if defined(STM32F412Cx)
+#define __HAL_RCC_AHB3_FORCE_RESET()
+#define __HAL_RCC_AHB3_RELEASE_RESET()
+
+#define __HAL_RCC_FSMC_FORCE_RESET()
+#define __HAL_RCC_QSPI_FORCE_RESET()
+
+#define __HAL_RCC_FSMC_RELEASE_RESET()
+#define __HAL_RCC_QSPI_RELEASE_RESET()
+#endif /* STM32F412Cx */
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset 
+  * @brief  Force or release APB1 peripheral reset.
+  * @{
+  */
+#define __HAL_RCC_TIM2_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST))
+#define __HAL_RCC_TIM3_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST)) 
+#define __HAL_RCC_TIM4_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST))                                        
+#define __HAL_RCC_TIM6_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST))
+#define __HAL_RCC_TIM7_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST))
+#define __HAL_RCC_TIM12_FORCE_RESET()    (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM12RST))
+#define __HAL_RCC_TIM13_FORCE_RESET()    (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM13RST))
+#define __HAL_RCC_TIM14_FORCE_RESET()    (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST)) 
+#if defined(STM32F413xx) || defined(STM32F423xx)
+#define __HAL_RCC_LPTIM1_FORCE_RESET()   (RCC->APB1RSTR |= (RCC_APB1RSTR_LPTIM1RST)) 
+#endif /* STM32F413xx || STM32F423xx */                                        
+#define __HAL_RCC_SPI3_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST))                                        
+#define __HAL_RCC_USART3_FORCE_RESET()   (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST))
+#if defined(STM32F413xx) || defined(STM32F423xx)
+#define __HAL_RCC_UART4_FORCE_RESET()    (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST))
+#define __HAL_RCC_UART5_FORCE_RESET()    (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST))                                        
+#endif /* STM32F413xx || STM32F423xx */                                          
+#define __HAL_RCC_I2C3_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C3RST))                                        
+#define __HAL_RCC_FMPI2C1_FORCE_RESET()  (RCC->APB1RSTR |= (RCC_APB1RSTR_FMPI2C1RST))
+#define __HAL_RCC_CAN1_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN1RST))
+#define __HAL_RCC_CAN2_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN2RST))
+#if defined(STM32F413xx) || defined(STM32F423xx)
+#define __HAL_RCC_CAN3_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN3RST))
+#define __HAL_RCC_DAC_FORCE_RESET()      (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST))
+#define __HAL_RCC_UART7_FORCE_RESET()    (RCC->APB1RSTR |= (RCC_APB1RSTR_UART7RST))
+#define __HAL_RCC_UART8_FORCE_RESET()    (RCC->APB1RSTR |= (RCC_APB1RSTR_UART8RST))                                        
+#endif /* STM32F413xx || STM32F423xx */                                        
+
+#define __HAL_RCC_TIM2_RELEASE_RESET()    (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
+#define __HAL_RCC_TIM3_RELEASE_RESET()    (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
+#define __HAL_RCC_TIM4_RELEASE_RESET()    (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
+#define __HAL_RCC_TIM6_RELEASE_RESET()    (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
+#define __HAL_RCC_TIM7_RELEASE_RESET()    (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
+#define __HAL_RCC_TIM12_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST))
+#define __HAL_RCC_TIM13_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST))
+#define __HAL_RCC_TIM14_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST)) 
+#if defined(STM32F413xx) || defined(STM32F423xx)
+#define __HAL_RCC_LPTIM1_RELEASE_RESET()  (RCC->APB1RSTR &= ~(RCC_APB1RSTR_LPTIM1RST))
+#endif /* STM32F413xx || STM32F423xx */                                        
+#define __HAL_RCC_SPI3_RELEASE_RESET()    (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
+#define __HAL_RCC_USART3_RELEASE_RESET()  (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
+#if defined(STM32F413xx) || defined(STM32F423xx)
+#define __HAL_RCC_UART4_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST))
+#define __HAL_RCC_UART5_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST))
+#endif /* STM32F413xx || STM32F423xx */                                        
+#define __HAL_RCC_I2C3_RELEASE_RESET()    (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST))                                        
+#define __HAL_RCC_FMPI2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_FMPI2C1RST))
+#define __HAL_RCC_CAN1_RELEASE_RESET()    (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST))
+#define __HAL_RCC_CAN2_RELEASE_RESET()    (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST))
+#if defined(STM32F413xx) || defined(STM32F423xx)
+#define __HAL_RCC_CAN3_RELEASE_RESET()    (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN3RST))
+#define __HAL_RCC_DAC_RELEASE_RESET()     (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
+#define __HAL_RCC_UART7_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART7RST))
+#define __HAL_RCC_UART8_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART8RST))                                      
+#endif /* STM32F413xx || STM32F423xx */                                         
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset
+  * @brief  Force or release APB2 peripheral reset.
+  * @{
+  */
+#define __HAL_RCC_TIM8_FORCE_RESET()     (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM8RST))
+#if defined(STM32F413xx) || defined(STM32F423xx)
+#define __HAL_RCC_UART9_FORCE_RESET()    (RCC->APB2RSTR |= (RCC_APB2RSTR_UART9RST))
+#define __HAL_RCC_UART10_FORCE_RESET()   (RCC->APB2RSTR |= (RCC_APB2RSTR_UART10RST))                                        
+#endif /* STM32F413xx || STM32F423xx */                                        
+#define __HAL_RCC_SDIO_FORCE_RESET()     (RCC->APB2RSTR |= (RCC_APB2RSTR_SDIORST))
+#define __HAL_RCC_SPI4_FORCE_RESET()     (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI4RST))
+#define __HAL_RCC_TIM10_FORCE_RESET()    (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM10RST))                                        
+#define __HAL_RCC_SPI5_FORCE_RESET()     (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI5RST))
+#if defined(STM32F413xx) || defined(STM32F423xx)
+#define __HAL_RCC_SAI1_FORCE_RESET()     (RCC->APB2RSTR |= (RCC_APB2RSTR_SAI1RST))
+#endif /* STM32F413xx || STM32F423xx */                                         
+#define __HAL_RCC_DFSDM1_FORCE_RESET()   (RCC->APB2RSTR |= (RCC_APB2RSTR_DFSDM1RST))
+#if defined(STM32F413xx) || defined(STM32F423xx)
+#define __HAL_RCC_DFSDM2_FORCE_RESET()   (RCC->APB2RSTR |= (RCC_APB2RSTR_DFSDM2RST))
+#endif /* STM32F413xx || STM32F423xx */                                        
+
+#define __HAL_RCC_TIM8_RELEASE_RESET()   (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST))
+#if defined(STM32F413xx) || defined(STM32F423xx)
+#define __HAL_RCC_UART9_RELEASE_RESET()  (RCC->APB2RSTR &= ~(RCC_APB2RSTR_UART9RST))
+#define __HAL_RCC_UART10_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_UART10RST))                                        
+#endif /* STM32F413xx || STM32F423xx */                                        
+#define __HAL_RCC_SDIO_RELEASE_RESET()   (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST))
+#define __HAL_RCC_SPI4_RELEASE_RESET()   (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST))
+#define __HAL_RCC_TIM10_RELEASE_RESET()  (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST))
+#define __HAL_RCC_SPI5_RELEASE_RESET()   (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI5RST))
+#if defined(STM32F413xx) || defined(STM32F423xx)
+#define __HAL_RCC_SAI1_RELEASE_RESET()   (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI1RST))
+#endif /* STM32F413xx || STM32F423xx */                                        
+#define __HAL_RCC_DFSDM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_DFSDM1RST))
+#if defined(STM32F413xx) || defined(STM32F423xx)
+#define __HAL_RCC_DFSDM2_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_DFSDM2RST))
+#endif /* STM32F413xx || STM32F423xx */                                        
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable
+  * @brief  Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
+  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
+  * @{
+  */
+#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIODLPEN))
+#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOELPEN))
+#define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOFLPEN))
+#define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOGLPEN))
+#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE()        (RCC->AHB1LPENR |= (RCC_AHB1LPENR_CRCLPEN))
+#define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_FLITFLPEN))
+#define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM1LPEN))
+#if defined(STM32F413xx) || defined(STM32F423xx)
+#define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM2LPEN))
+#endif /* STM32F413xx || STM32F423xx */                                        
+
+#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN))
+#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN))
+#define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOFLPEN))
+#define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOGLPEN))
+#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE()       (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN))
+#define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN))
+#define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN))
+#if defined(STM32F413xx) || defined(STM32F423xx)
+#define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM2LPEN))
+#endif /* STM32F413xx || STM32F423xx */                                        
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_AHB2_LowPower_Enable_Disable AHB2 Peripheral Low Power Enable Disable
+  * @brief  Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wake-up from SLEEP mode, the peripheral clock is enabled again.
+  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
+  * @{
+  */
+#if defined(STM32F423xx)
+#define __HAL_RCC_AES_CLK_SLEEP_ENABLE()      (RCC->AHB2LPENR |= (RCC_AHB2LPENR_AESLPEN))                                        
+#define __HAL_RCC_AES_CLK_SLEEP_DISABLE()     (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_AESLPEN))
+#endif /* STM32F423xx */
+                                        
+#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE()  (RCC->AHB2LPENR |= (RCC_AHB2LPENR_OTGFSLPEN))
+#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE()   (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN))
+
+#define __HAL_RCC_RNG_CLK_SLEEP_ENABLE()   (RCC->AHB2LPENR |= (RCC_AHB2LPENR_RNGLPEN))
+#define __HAL_RCC_RNG_CLK_SLEEP_DISABLE()  (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_RNGLPEN))
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_AHB3_LowPower_Enable_Disable AHB3 Peripheral Low Power Enable Disable
+  * @brief  Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
+  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
+  * @{
+  */
+#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx)
+#define __HAL_RCC_FSMC_CLK_SLEEP_ENABLE()   (RCC->AHB3LPENR |= (RCC_AHB3LPENR_FSMCLPEN))
+#define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE()  (RCC->AHB3LPENR |= (RCC_AHB3LPENR_QSPILPEN))
+
+#define __HAL_RCC_FSMC_CLK_SLEEP_DISABLE()   (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_FSMCLPEN))
+#define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE()  (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_QSPILPEN))
+#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F413xx || STM32F423xx */
+
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable
+  * @brief  Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
+  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
+  * @{
+  */
+#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM2LPEN))
+#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM3LPEN))
+#define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM4LPEN))                                        
+#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM6LPEN))
+#define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM7LPEN))
+#define __HAL_RCC_TIM12_CLK_SLEEP_ENABLE()   (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM12LPEN))
+#define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE()   (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM13LPEN))
+#define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE()   (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM14LPEN))
+#if defined(STM32F413xx) || defined(STM32F423xx)
+#define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE()   (RCC->APB1LPENR |= (RCC_APB1LPENR_LPTIM1LPEN))
+#endif /* STM32F413xx || STM32F423xx */                                        
+#define __HAL_RCC_RTCAPB_CLK_SLEEP_ENABLE()  (RCC->APB1LPENR |= (RCC_APB1LPENR_RTCAPBLPEN))
+#define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI3LPEN))                                       
+#define __HAL_RCC_USART3_CLK_SLEEP_ENABLE()  (RCC->APB1LPENR |= (RCC_APB1LPENR_USART3LPEN))
+#if defined(STM32F413xx) || defined(STM32F423xx)
+#define __HAL_RCC_UART4_CLK_SLEEP_ENABLE()   (RCC->APB1LPENR |= (RCC_APB1LPENR_UART4LPEN))
+#define __HAL_RCC_UART5_CLK_SLEEP_ENABLE()   (RCC->APB1LPENR |= (RCC_APB1LPENR_UART5LPEN))
+#endif /* STM32F413xx || STM32F423xx */                                        
+#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C3LPEN))                                        
+#define __HAL_RCC_FMPI2C1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_FMPI2C1LPEN))
+#define __HAL_RCC_CAN1_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN1LPEN))
+#define __HAL_RCC_CAN2_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN2LPEN))
+#if defined(STM32F413xx) || defined(STM32F423xx)
+#define __HAL_RCC_CAN3_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN3LPEN))
+#define __HAL_RCC_DAC_CLK_SLEEP_ENABLE()     (RCC->APB1LPENR |= (RCC_APB1LPENR_DACLPEN))
+#define __HAL_RCC_UART7_CLK_SLEEP_ENABLE()   (RCC->APB1LPENR |= (RCC_APB1LPENR_UART7LPEN))
+#define __HAL_RCC_UART8_CLK_SLEEP_ENABLE()   (RCC->APB1LPENR |= (RCC_APB1LPENR_UART8LPEN))                                        
+#endif /* STM32F413xx || STM32F423xx */                                        
+
+#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN))
+#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN))
+#define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN))
+#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN))
+#define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN))
+#define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE()  (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM12LPEN))
+#define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE()  (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM13LPEN))
+#define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE()  (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM14LPEN))
+#if defined(STM32F413xx) || defined(STM32F423xx)
+#define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE()  (RCC->APB1LPENR &= ~(RCC_APB1LPENR_LPTIM1LPEN))
+#endif /* STM32F413xx || STM32F423xx */                                        
+#define __HAL_RCC_RTCAPB_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_RTCAPBLPEN))
+#define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN))                                        
+#define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN))
+#if defined(STM32F413xx) || defined(STM32F423xx)
+#define __HAL_RCC_UART4_CLK_SLEEP_DISABLE()  (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN))
+#define __HAL_RCC_UART5_CLK_SLEEP_DISABLE()  (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN))
+#endif /* STM32F413xx || STM32F423xx */                                
+#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN))                                        
+#define __HAL_RCC_FMPI2C1_CLK_SLEEP_DISABLE()(RCC->APB1LPENR &= ~(RCC_APB1LPENR_FMPI2C1LPEN))
+#define __HAL_RCC_CAN1_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN1LPEN))
+#define __HAL_RCC_CAN2_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN2LPEN))
+#if defined(STM32F413xx) || defined(STM32F423xx)
+#define __HAL_RCC_CAN3_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN3LPEN))
+#define __HAL_RCC_DAC_CLK_SLEEP_DISABLE()    (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN))
+#define __HAL_RCC_UART7_CLK_SLEEP_DISABLE()  (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART7LPEN))
+#define __HAL_RCC_UART8_CLK_SLEEP_DISABLE()  (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART8LPEN))                                        
+#endif /* STM32F413xx || STM32F423xx */                                     
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable
+  * @brief  Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
+  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
+  * @{
+  */
+#define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE()    (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM8LPEN))
+#if defined(STM32F413xx) || defined(STM32F423xx)
+#define __HAL_RCC_UART9_CLK_SLEEP_ENABLE()   (RCC->APB2LPENR |= (RCC_APB2LPENR_UART9LPEN))
+#define __HAL_RCC_UART10_CLK_SLEEP_ENABLE()  (RCC->APB2LPENR |= (RCC_APB2LPENR_UART10LPEN))                                        
+#endif /* STM32F413xx || STM32F423xx */                                        
+#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE()    (RCC->APB2LPENR |= (RCC_APB2LPENR_SDIOLPEN))
+#define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE()    (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI4LPEN))  
+#define __HAL_RCC_EXTIT_CLK_SLEEP_ENABLE()   (RCC->APB2LPENR |= (RCC_APB2LPENR_EXTITLPEN)) 
+#define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE()   (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM10LPEN))                                        
+#define __HAL_RCC_SPI5_CLK_SLEEP_ENABLE()    (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI5LPEN))
+#if defined(STM32F413xx) || defined(STM32F423xx)
+#define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE()    (RCC->APB2LPENR |= (RCC_APB2LPENR_SAI1LPEN))
+#endif /* STM32F413xx || STM32F423xx */                                        
+#define __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE()  (RCC->APB2LPENR |= (RCC_APB2LPENR_DFSDM1LPEN))
+#if defined(STM32F413xx) || defined(STM32F423xx)
+#define __HAL_RCC_DFSDM2_CLK_SLEEP_ENABLE()  (RCC->APB2LPENR |= (RCC_APB2LPENR_DFSDM2LPEN))
+#endif /* STM32F413xx || STM32F423xx */
+                                        
+#define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE()    (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM8LPEN))
+#if defined(STM32F413xx) || defined(STM32F423xx)
+#define __HAL_RCC_UART9_CLK_SLEEP_DISABLE()   (RCC->APB2LPENR &= ~(RCC_APB2LPENR_UART9LPEN))
+#define __HAL_RCC_UART10_CLK_SLEEP_DISABLE()  (RCC->APB2LPENR &= ~(RCC_APB2LPENR_UART10LPEN))                                        
+#endif /* STM32F413xx || STM32F423xx */                                        
+#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE()    (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN))
+#define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE()    (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN))
+#define __HAL_RCC_EXTIT_CLK_SLEEP_DISABLE()   (RCC->APB2LPENR &= ~(RCC_APB2LPENR_EXTITLPEN))
+#define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE()   (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN))    
+#define __HAL_RCC_SPI5_CLK_SLEEP_DISABLE()    (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI5LPEN))
+#if defined(STM32F413xx) || defined(STM32F423xx)
+#define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE()    (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI1LPEN))
+#endif /* STM32F413xx || STM32F423xx */                                        
+#define __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE()  (RCC->APB2LPENR &= ~(RCC_APB2LPENR_DFSDM1LPEN))
+#if defined(STM32F413xx) || defined(STM32F423xx)
+#define __HAL_RCC_DFSDM2_CLK_SLEEP_DISABLE()  (RCC->APB2LPENR &= ~(RCC_APB2LPENR_DFSDM2LPEN))
+#endif /* STM32F413xx || STM32F423xx */                                        
+/**
+  * @}
+  */
+#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */
+/*----------------------------------------------------------------------------*/
+
+/*------------------------------- PLL Configuration --------------------------*/
+#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F446xx) ||\
+    defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
+    defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
+/** @brief  Macro to configure the main PLL clock source, multiplication and division factors.
+  * @note   This function must be used only when the main PLL is disabled.
+  * @param  __RCC_PLLSource__ specifies the PLL entry clock source.
+  *         This parameter can be one of the following values:
+  *            @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
+  *            @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
+  * @note   This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S.  
+  * @param  __PLLM__ specifies the division factor for PLL VCO input clock
+  *         This parameter must be a number between Min_Data = 2 and Max_Data = 63.
+  * @note   You have to set the PLLM parameter correctly to ensure that the VCO input
+  *         frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
+  *         of 2 MHz to limit PLL jitter.
+  * @param  __PLLN__ specifies the multiplication factor for PLL VCO output clock
+  *         This parameter must be a number between Min_Data = 50 and Max_Data = 432.
+  * @note   You have to set the PLLN parameter correctly to ensure that the VCO
+  *         output frequency is between 100 and 432 MHz.
+  *   
+  * @param  __PLLP__ specifies the division factor for main system clock (SYSCLK)
+  *         This parameter must be a number in the range {2, 4, 6, or 8}.
+  *           
+  * @param  __PLLQ__ specifies the division factor for OTG FS, SDIO and RNG clocks
+  *         This parameter must be a number between Min_Data = 2 and Max_Data = 15.
+  * @note   If the USB OTG FS is used in your application, you have to set the
+  *         PLLQ parameter correctly to have 48 MHz clock for the USB. However,
+  *         the SDIO and RNG need a frequency lower than or equal to 48 MHz to work
+  *         correctly.
+  *     
+  * @param  __PLLR__ PLL division factor for I2S, SAI, SYSTEM, SPDIFRX clocks.
+  *         This parameter must be a number between Min_Data = 2 and Max_Data = 7.
+  * @note   This parameter is only available in STM32F446xx/STM32F469xx/STM32F479xx/
+            STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx/STM32F413xx/STM32F423xx devices.
+  *      
+  */
+#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__,__PLLR__)  \
+                            (RCC->PLLCFGR = ((__RCC_PLLSource__) | (__PLLM__)                   | \
+                            ((__PLLN__) << RCC_PLLCFGR_PLLN_Pos)                      | \
+                            ((((__PLLP__) >> 1U) -1U) << RCC_PLLCFGR_PLLP_Pos)          | \
+                            ((__PLLQ__) << RCC_PLLCFGR_PLLQ_Pos)                      | \
+                            ((__PLLR__) << RCC_PLLCFGR_PLLR_Pos)))
+#else
+/** @brief  Macro to configure the main PLL clock source, multiplication and division factors.
+  * @note   This function must be used only when the main PLL is disabled.
+  * @param  __RCC_PLLSource__ specifies the PLL entry clock source.
+  *         This parameter can be one of the following values:
+  *            @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
+  *            @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
+  * @note   This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S.  
+  * @param  __PLLM__ specifies the division factor for PLL VCO input clock
+  *         This parameter must be a number between Min_Data = 2 and Max_Data = 63.
+  * @note   You have to set the PLLM parameter correctly to ensure that the VCO input
+  *         frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
+  *         of 2 MHz to limit PLL jitter.
+  * @param  __PLLN__ specifies the multiplication factor for PLL VCO output clock
+  *         This parameter must be a number between Min_Data = 50 and Max_Data = 432
+  *         Except for STM32F411xE devices where Min_Data = 192.
+  * @note   You have to set the PLLN parameter correctly to ensure that the VCO
+  *         output frequency is between 100 and 432 MHz, Except for STM32F411xE devices
+  *         where frequency is between 192 and 432 MHz.
+  * @param  __PLLP__ specifies the division factor for main system clock (SYSCLK)
+  *         This parameter must be a number in the range {2, 4, 6, or 8}.
+  *           
+  * @param  __PLLQ__ specifies the division factor for OTG FS, SDIO and RNG clocks
+  *         This parameter must be a number between Min_Data = 2 and Max_Data = 15.
+  * @note   If the USB OTG FS is used in your application, you have to set the
+  *         PLLQ parameter correctly to have 48 MHz clock for the USB. However,
+  *         the SDIO and RNG need a frequency lower than or equal to 48 MHz to work
+  *         correctly.
+  *      
+  */
+#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__)     \
+                            (RCC->PLLCFGR = (0x20000000U | (__RCC_PLLSource__) | (__PLLM__)| \
+                            ((__PLLN__) << RCC_PLLCFGR_PLLN_Pos)                | \
+                            ((((__PLLP__) >> 1U) -1U) << RCC_PLLCFGR_PLLP_Pos)    | \
+                            ((__PLLQ__) << RCC_PLLCFGR_PLLQ_Pos)))
+ #endif /* STM32F410xx || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */
+/*----------------------------------------------------------------------------*/
+                             
+/*----------------------------PLLI2S Configuration ---------------------------*/
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \
+    defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
+    defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \
+    defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
+    defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
+
+/** @brief Macros to enable or disable the PLLI2S. 
+  * @note  The PLLI2S is disabled by hardware when entering STOP and STANDBY modes.
+  */
+#define __HAL_RCC_PLLI2S_ENABLE() (*(__IO uint32_t *) RCC_CR_PLLI2SON_BB = ENABLE)
+#define __HAL_RCC_PLLI2S_DISABLE() (*(__IO uint32_t *) RCC_CR_PLLI2SON_BB = DISABLE)
+
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||
+          STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || 
+          STM32F412Rx || STM32F412Cx */
+#if defined(STM32F446xx)
+/** @brief  Macro to configure the PLLI2S clock multiplication and division factors .
+  * @note   This macro must be used only when the PLLI2S is disabled.
+  * @note   PLLI2S clock source is common with the main PLL (configured in 
+  *         HAL_RCC_ClockConfig() API).
+  * @param  __PLLI2SM__ specifies the division factor for PLLI2S VCO input clock
+  *         This parameter must be a number between Min_Data = 2 and Max_Data = 63.
+  * @note   You have to set the PLLI2SM parameter correctly to ensure that the VCO input
+  *         frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
+  *         of 1 MHz to limit PLLI2S jitter.
+  *
+  * @param  __PLLI2SN__ specifies the multiplication factor for PLLI2S VCO output clock
+  *         This parameter must be a number between Min_Data = 50 and Max_Data = 432.
+  * @note   You have to set the PLLI2SN parameter correctly to ensure that the VCO 
+  *         output frequency is between Min_Data = 100 and Max_Data = 432 MHz.
+  *
+  * @param  __PLLI2SP__ specifies division factor for SPDIFRX Clock.
+  *         This parameter must be a number in the range {2, 4, 6, or 8}.
+  * @note   the PLLI2SP parameter is only available with STM32F446xx Devices
+  *                 
+  * @param  __PLLI2SR__ specifies the division factor for I2S clock
+  *         This parameter must be a number between Min_Data = 2 and Max_Data = 7.
+  * @note   You have to set the PLLI2SR parameter correctly to not exceed 192 MHz
+  *         on the I2S clock frequency.
+  *   
+  * @param  __PLLI2SQ__ specifies the division factor for SAI clock
+  *         This parameter must be a number between Min_Data = 2 and Max_Data = 15.
+  */
+#define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SM__, __PLLI2SN__, __PLLI2SP__, __PLLI2SQ__, __PLLI2SR__)    \
+                               (RCC->PLLI2SCFGR = ((__PLLI2SM__)                                   |\
+                               ((__PLLI2SN__) << RCC_PLLI2SCFGR_PLLI2SN_Pos)             |\
+                               ((((__PLLI2SP__) >> 1U) -1U) << RCC_PLLI2SCFGR_PLLI2SP_Pos) |\
+                               ((__PLLI2SQ__) << RCC_PLLI2SCFGR_PLLI2SQ_Pos)             |\
+                               ((__PLLI2SR__) << RCC_PLLI2SCFGR_PLLI2SR_Pos)))
+#elif defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) ||\
+      defined(STM32F413xx) || defined(STM32F423xx)
+/** @brief  Macro to configure the PLLI2S clock multiplication and division factors .
+  * @note   This macro must be used only when the PLLI2S is disabled.
+  * @note   PLLI2S clock source is common with the main PLL (configured in 
+  *         HAL_RCC_ClockConfig() API).
+  * @param  __PLLI2SM__ specifies the division factor for PLLI2S VCO input clock
+  *         This parameter must be a number between Min_Data = 2 and Max_Data = 63.
+  * @note   You have to set the PLLI2SM parameter correctly to ensure that the VCO input
+  *         frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
+  *         of 1 MHz to limit PLLI2S jitter.
+  *
+  * @param  __PLLI2SN__ specifies the multiplication factor for PLLI2S VCO output clock
+  *         This parameter must be a number between Min_Data = 50 and Max_Data = 432.
+  * @note   You have to set the PLLI2SN parameter correctly to ensure that the VCO 
+  *         output frequency is between Min_Data = 100 and Max_Data = 432 MHz.
+  *
+  * @param  __PLLI2SR__ specifies the division factor for I2S clock
+  *         This parameter must be a number between Min_Data = 2 and Max_Data = 7.
+  * @note   You have to set the PLLI2SR parameter correctly to not exceed 192 MHz
+  *         on the I2S clock frequency.
+  *
+  * @param  __PLLI2SQ__ specifies the division factor for SAI clock
+  *         This parameter must be a number between Min_Data = 2 and Max_Data = 15.
+  */
+#define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SM__, __PLLI2SN__, __PLLI2SQ__, __PLLI2SR__)    \
+                               (RCC->PLLI2SCFGR = ((__PLLI2SM__)                                   |\
+                               ((__PLLI2SN__) << RCC_PLLI2SCFGR_PLLI2SN_Pos)             |\
+                               ((__PLLI2SQ__) << RCC_PLLI2SCFGR_PLLI2SQ_Pos)             |\
+                               ((__PLLI2SR__) << RCC_PLLI2SCFGR_PLLI2SR_Pos)))
+#else
+/** @brief  Macro to configure the PLLI2S clock multiplication and division factors .
+  * @note   This macro must be used only when the PLLI2S is disabled.
+  * @note   PLLI2S clock source is common with the main PLL (configured in 
+  *         HAL_RCC_ClockConfig() API).
+  * @param  __PLLI2SN__ specifies the multiplication factor for PLLI2S VCO output clock
+  *         This parameter must be a number between Min_Data = 50 and Max_Data = 432.
+  * @note   You have to set the PLLI2SN parameter correctly to ensure that the VCO 
+  *         output frequency is between Min_Data = 100 and Max_Data = 432 MHz.
+  *
+  * @param  __PLLI2SR__ specifies the division factor for I2S clock
+  *         This parameter must be a number between Min_Data = 2 and Max_Data = 7.
+  * @note   You have to set the PLLI2SR parameter correctly to not exceed 192 MHz
+  *         on the I2S clock frequency.
+  *
+  */
+#define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SN__, __PLLI2SR__)                                                    \
+                               (RCC->PLLI2SCFGR = (((__PLLI2SN__) << RCC_PLLI2SCFGR_PLLI2SN_Pos)  |\
+                               ((__PLLI2SR__) << RCC_PLLI2SCFGR_PLLI2SR_Pos)))
+#endif /* STM32F446xx */
+
+#if defined(STM32F411xE)
+/** @brief  Macro to configure the PLLI2S clock multiplication and division factors .
+  * @note   This macro must be used only when the PLLI2S is disabled.
+  * @note   This macro must be used only when the PLLI2S is disabled.
+  * @note   PLLI2S clock source is common with the main PLL (configured in 
+  *         HAL_RCC_ClockConfig() API).
+  * @param  __PLLI2SM__ specifies the division factor for PLLI2S VCO input clock
+  *         This parameter must be a number between Min_Data = 2 and Max_Data = 63.
+  * @note   The PLLI2SM parameter is only used with STM32F411xE/STM32F410xx Devices
+  * @note   You have to set the PLLI2SM parameter correctly to ensure that the VCO input
+  *         frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
+  *         of 2 MHz to limit PLLI2S jitter.    
+  * @param  __PLLI2SN__ specifies the multiplication factor for PLLI2S VCO output clock
+  *         This parameter must be a number between Min_Data = 192 and Max_Data = 432.
+  * @note   You have to set the PLLI2SN parameter correctly to ensure that the VCO 
+  *         output frequency is between Min_Data = 192 and Max_Data = 432 MHz.
+  * @param  __PLLI2SR__ specifies the division factor for I2S clock
+  *         This parameter must be a number between Min_Data = 2 and Max_Data = 7.
+  * @note   You have to set the PLLI2SR parameter correctly to not exceed 192 MHz
+  *         on the I2S clock frequency.
+  */
+#define __HAL_RCC_PLLI2S_I2SCLK_CONFIG(__PLLI2SM__, __PLLI2SN__, __PLLI2SR__) (RCC->PLLI2SCFGR = ((__PLLI2SM__)                                                       |\
+                                                                                                  ((__PLLI2SN__) << RCC_PLLI2SCFGR_PLLI2SN_Pos)             |\
+                                                                                                  ((__PLLI2SR__) << RCC_PLLI2SCFGR_PLLI2SR_Pos)))
+#endif /* STM32F411xE */
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
+/** @brief  Macro used by the SAI HAL driver to configure the PLLI2S clock multiplication and division factors.
+  * @note   This macro must be used only when the PLLI2S is disabled.
+  * @note   PLLI2S clock source is common with the main PLL (configured in 
+  *         HAL_RCC_ClockConfig() API)             
+  * @param  __PLLI2SN__ specifies the multiplication factor for PLLI2S VCO output clock.
+  *         This parameter must be a number between Min_Data = 50 and Max_Data = 432.
+  * @note   You have to set the PLLI2SN parameter correctly to ensure that the VCO 
+  *         output frequency is between Min_Data = 100 and Max_Data = 432 MHz.
+  * @param  __PLLI2SQ__ specifies the division factor for SAI1 clock.
+  *         This parameter must be a number between Min_Data = 2 and Max_Data = 15. 
+  * @note   the PLLI2SQ parameter is only available with STM32F427xx/437xx/429xx/439xx/469xx/479xx 
+  *         Devices and can be configured using the __HAL_RCC_PLLI2S_PLLSAICLK_CONFIG() macro
+  * @param  __PLLI2SR__ specifies the division factor for I2S clock
+  *         This parameter must be a number between Min_Data = 2 and Max_Data = 7.
+  * @note   You have to set the PLLI2SR parameter correctly to not exceed 192 MHz
+  *         on the I2S clock frequency.
+  */
+#define __HAL_RCC_PLLI2S_SAICLK_CONFIG(__PLLI2SN__, __PLLI2SQ__, __PLLI2SR__) (RCC->PLLI2SCFGR = ((__PLLI2SN__) << 6U)  |\
+                                                                                                 ((__PLLI2SQ__) << 24U) |\
+                                                                                                 ((__PLLI2SR__) << 28U))
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */   
+/*----------------------------------------------------------------------------*/
+
+/*------------------------------ PLLSAI Configuration ------------------------*/
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
+/** @brief Macros to Enable or Disable the PLLISAI. 
+  * @note  The PLLSAI is only available with STM32F429x/439x Devices.
+  * @note  The PLLSAI is disabled by hardware when entering STOP and STANDBY modes. 
+  */
+#define __HAL_RCC_PLLSAI_ENABLE() (*(__IO uint32_t *) RCC_CR_PLLSAION_BB = ENABLE)
+#define __HAL_RCC_PLLSAI_DISABLE() (*(__IO uint32_t *) RCC_CR_PLLSAION_BB = DISABLE)
+
+#if defined(STM32F446xx)
+/** @brief  Macro to configure the PLLSAI clock multiplication and division factors.
+  *
+  * @param  __PLLSAIM__ specifies the division factor for PLLSAI VCO input clock
+  *         This parameter must be a number between Min_Data = 2 and Max_Data = 63.
+  * @note   You have to set the PLLSAIM parameter correctly to ensure that the VCO input
+  *         frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
+  *         of 1 MHz to limit PLLI2S jitter.
+  * @note   The PLLSAIM parameter is only used with STM32F446xx Devices
+  *             
+  * @param  __PLLSAIN__ specifies the multiplication factor for PLLSAI VCO output clock.
+  *         This parameter must be a number between Min_Data = 50 and Max_Data = 432.
+  * @note   You have to set the PLLSAIN parameter correctly to ensure that the VCO 
+  *         output frequency is between Min_Data = 100 and Max_Data = 432 MHz.
+  *
+  * @param  __PLLSAIP__ specifies division factor for OTG FS, SDIO and RNG clocks.
+  *         This parameter must be a number in the range {2, 4, 6, or 8}.
+  * @note   the PLLSAIP parameter is only available with STM32F446xx Devices
+  *                 
+  * @param  __PLLSAIQ__ specifies the division factor for SAI clock
+  *         This parameter must be a number between Min_Data = 2 and Max_Data = 15.
+  *           
+  * @param  __PLLSAIR__ specifies the division factor for LTDC clock
+  *         This parameter must be a number between Min_Data = 2 and Max_Data = 7.
+  * @note   the PLLI2SR parameter is only available with STM32F427/437/429/439xx Devices  
+  */
+#define __HAL_RCC_PLLSAI_CONFIG(__PLLSAIM__, __PLLSAIN__, __PLLSAIP__, __PLLSAIQ__, __PLLSAIR__)     \
+                               (RCC->PLLSAICFGR = ((__PLLSAIM__)                                   | \
+                               ((__PLLSAIN__) << RCC_PLLSAICFGR_PLLSAIN_Pos)             | \
+                               ((((__PLLSAIP__) >> 1U) -1U) << RCC_PLLSAICFGR_PLLSAIP_Pos) | \
+                               ((__PLLSAIQ__) << RCC_PLLSAICFGR_PLLSAIQ_Pos))) 
+#endif /* STM32F446xx */
+                                 
+#if defined(STM32F469xx) || defined(STM32F479xx)
+/** @brief  Macro to configure the PLLSAI clock multiplication and division factors.
+  *             
+  * @param  __PLLSAIN__ specifies the multiplication factor for PLLSAI VCO output clock.
+  *         This parameter must be a number between Min_Data = 50 and Max_Data = 432.
+  * @note   You have to set the PLLSAIN parameter correctly to ensure that the VCO 
+  *         output frequency is between Min_Data = 100 and Max_Data = 432 MHz.
+  *
+  * @param  __PLLSAIP__ specifies division factor for SDIO and CLK48 clocks.
+  *         This parameter must be a number in the range {2, 4, 6, or 8}.
+  *                 
+  * @param  __PLLSAIQ__ specifies the division factor for SAI clock
+  *         This parameter must be a number between Min_Data = 2 and Max_Data = 15.
+  *           
+  * @param  __PLLSAIR__ specifies the division factor for LTDC clock
+  *         This parameter must be a number between Min_Data = 2 and Max_Data = 7.  
+  */
+#define __HAL_RCC_PLLSAI_CONFIG(__PLLSAIN__, __PLLSAIP__, __PLLSAIQ__, __PLLSAIR__) \
+                               (RCC->PLLSAICFGR = (((__PLLSAIN__) << RCC_PLLSAICFGR_PLLSAIN_Pos)             |\
+                                                   ((((__PLLSAIP__) >> 1U) -1U) << RCC_PLLSAICFGR_PLLSAIP_Pos) |\
+                                                   ((__PLLSAIQ__) << RCC_PLLSAICFGR_PLLSAIQ_Pos)             |\
+                                                   ((__PLLSAIR__) << RCC_PLLSAICFGR_PLLSAIR_Pos)))
+#endif /* STM32F469xx || STM32F479xx */                                 
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
+/** @brief  Macro to configure the PLLSAI clock multiplication and division factors.
+  *             
+  * @param  __PLLSAIN__ specifies the multiplication factor for PLLSAI VCO output clock.
+  *         This parameter must be a number between Min_Data = 50 and Max_Data = 432.
+  * @note   You have to set the PLLSAIN parameter correctly to ensure that the VCO 
+  *         output frequency is between Min_Data = 100 and Max_Data = 432 MHz.
+  *
+  * @param  __PLLSAIQ__ specifies the division factor for SAI clock
+  *         This parameter must be a number between Min_Data = 2 and Max_Data = 15.
+  *           
+  * @param  __PLLSAIR__ specifies the division factor for LTDC clock
+  *         This parameter must be a number between Min_Data = 2 and Max_Data = 7.
+  * @note   the PLLI2SR parameter is only available with STM32F427/437/429/439xx Devices  
+  */
+#define __HAL_RCC_PLLSAI_CONFIG(__PLLSAIN__, __PLLSAIQ__, __PLLSAIR__)                                        \
+                               (RCC->PLLSAICFGR = (((__PLLSAIN__) << RCC_PLLSAICFGR_PLLSAIN_Pos)  | \
+                               ((__PLLSAIQ__) << RCC_PLLSAICFGR_PLLSAIQ_Pos)                      | \
+                               ((__PLLSAIR__) << RCC_PLLSAICFGR_PLLSAIR_Pos)))
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
+/*----------------------------------------------------------------------------*/
+
+/*------------------- PLLSAI/PLLI2S Dividers Configuration -------------------*/
+#if defined(STM32F413xx) || defined(STM32F423xx)
+/** @brief  Macro to configure the SAI clock Divider coming from PLLI2S.
+  * @note   This function must be called before enabling the PLLI2S.
+  * @param  __PLLI2SDivR__ specifies the PLLI2S division factor for SAI1 clock.
+  *          This parameter must be a number between 1 and 32.
+  *          SAI1 clock frequency = f(PLLI2SR) / __PLLI2SDivR__ 
+  */
+#define __HAL_RCC_PLLI2S_PLLSAICLKDIVR_CONFIG(__PLLI2SDivR__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLI2SDIVR, (__PLLI2SDivR__)-1U))
+
+/** @brief  Macro to configure the SAI clock Divider coming from PLL.
+  * @param  __PLLDivR__ specifies the PLL division factor for SAI1 clock.
+  *          This parameter must be a number between 1 and 32.
+  *          SAI1 clock frequency = f(PLLR) / __PLLDivR__ 
+  */
+#define __HAL_RCC_PLL_PLLSAICLKDIVR_CONFIG(__PLLDivR__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLDIVR, ((__PLLDivR__)-1U)<<8U))                                 
+#endif /* STM32F413xx || STM32F423xx */  
+                                 
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)  || defined(STM32F446xx) ||\
+    defined(STM32F469xx) || defined(STM32F479xx)
+/** @brief  Macro to configure the SAI clock Divider coming from PLLI2S.
+  * @note   This function must be called before enabling the PLLI2S.
+  * @param  __PLLI2SDivQ__ specifies the PLLI2S division factor for SAI1 clock.
+  *          This parameter must be a number between 1 and 32.
+  *          SAI1 clock frequency = f(PLLI2SQ) / __PLLI2SDivQ__ 
+  */
+#define __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(__PLLI2SDivQ__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLI2SDIVQ, (__PLLI2SDivQ__)-1U))
+
+/** @brief  Macro to configure the SAI clock Divider coming from PLLSAI.
+  * @note   This function must be called before enabling the PLLSAI.
+  * @param  __PLLSAIDivQ__ specifies the PLLSAI division factor for SAI1 clock .
+  *         This parameter must be a number between Min_Data = 1 and Max_Data = 32.
+  *         SAI1 clock frequency = f(PLLSAIQ) / __PLLSAIDivQ__  
+  */
+#define __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(__PLLSAIDivQ__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLSAIDIVQ, ((__PLLSAIDivQ__)-1U)<<8U))
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
+/** @brief  Macro to configure the LTDC clock Divider coming from PLLSAI.
+  * 
+  * @note   The LTDC peripheral is only available with STM32F427/437/429/439/469/479xx Devices.
+  * @note   This function must be called before enabling the PLLSAI. 
+  * @param  __PLLSAIDivR__ specifies the PLLSAI division factor for LTDC clock .
+  *          This parameter must be a number between Min_Data = 2 and Max_Data = 16.
+  *          LTDC clock frequency = f(PLLSAIR) / __PLLSAIDivR__ 
+  */
+#define __HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG(__PLLSAIDivR__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLSAIDIVR, (__PLLSAIDivR__)))
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
+/*----------------------------------------------------------------------------*/
+
+/*------------------------- Peripheral Clock selection -----------------------*/
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
+    defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
+    defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F469xx) ||\
+    defined(STM32F479xx)
+/** @brief  Macro to configure the I2S clock source (I2SCLK).
+  * @note   This function must be called before enabling the I2S APB clock.
+  * @param  __SOURCE__ specifies the I2S clock source.
+  *         This parameter can be one of the following values:
+  *            @arg RCC_I2SCLKSOURCE_PLLI2S: PLLI2S clock used as I2S clock source.
+  *            @arg RCC_I2SCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin
+  *                                       used as I2S clock source.
+  */
+#define __HAL_RCC_I2S_CONFIG(__SOURCE__) (*(__IO uint32_t *) RCC_CFGR_I2SSRC_BB = (__SOURCE__))
+
+
+/** @brief  Macro to get the I2S clock source (I2SCLK).
+  * @retval The clock source can be one of the following values:
+  *            @arg @ref RCC_I2SCLKSOURCE_PLLI2S: PLLI2S clock used as I2S clock source.
+  *            @arg @ref RCC_I2SCLKSOURCE_EXT External clock mapped on the I2S_CKIN pin
+  *                                        used as I2S clock source
+  */
+#define __HAL_RCC_GET_I2S_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_I2SSRC)))
+#endif /* STM32F40xxx || STM32F41xxx || STM32F42xxx || STM32F43xxx || STM32F469xx || STM32F479xx */
+                                 
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
+                                 
+/** @brief  Macro to configure SAI1BlockA clock source selection.
+  * @note   The SAI peripheral is only available with STM32F427/437/429/439/469/479xx Devices.      
+  * @note   This function must be called before enabling PLLSAI, PLLI2S and  
+  *         the SAI clock.
+  * @param  __SOURCE__ specifies the SAI Block A clock source.
+  *         This parameter can be one of the following values:
+  *            @arg RCC_SAIACLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used 
+  *                                           as SAI1 Block A clock. 
+  *            @arg RCC_SAIACLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used 
+  *                                           as SAI1 Block A clock.
+  *            @arg RCC_SAIACLKSOURCE_Ext: External clock mapped on the I2S_CKIN pin
+  *                                        used as SAI1 Block A clock.
+  */
+#define __HAL_RCC_SAI_BLOCKACLKSOURCE_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI1ASRC, (__SOURCE__)))
+
+/** @brief  Macro to configure SAI1BlockB clock source selection.
+  * @note   The SAI peripheral is only available with STM32F427/437/429/439/469/479xx Devices.
+  * @note   This function must be called before enabling PLLSAI, PLLI2S and  
+  *         the SAI clock.
+  * @param  __SOURCE__ specifies the SAI Block B clock source.
+  *         This parameter can be one of the following values:
+  *            @arg RCC_SAIBCLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used 
+  *                                           as SAI1 Block B clock. 
+  *            @arg RCC_SAIBCLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used 
+  *                                           as SAI1 Block B clock. 
+  *            @arg RCC_SAIBCLKSOURCE_Ext: External clock mapped on the I2S_CKIN pin
+  *                                        used as SAI1 Block B clock.
+  */
+#define __HAL_RCC_SAI_BLOCKBCLKSOURCE_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI1BSRC, (__SOURCE__)))
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
+
+#if defined(STM32F446xx)
+/** @brief  Macro to configure SAI1 clock source selection.
+  * @note   This configuration is only available with STM32F446xx Devices.
+  * @note   This function must be called before enabling PLL, PLLSAI, PLLI2S and  
+  *         the SAI clock.
+  * @param  __SOURCE__ specifies the SAI1 clock source.
+  *         This parameter can be one of the following values:
+  *            @arg RCC_SAI1CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used as SAI1 clock. 
+  *            @arg RCC_SAI1CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used as SAI1 clock.
+  *            @arg RCC_SAI1CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SAI1 clock.  
+  *            @arg RCC_SAI1CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as SAI1 clock.
+  */
+#define __HAL_RCC_SAI1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI1SRC, (__SOURCE__)))
+
+/** @brief  Macro to Get SAI1 clock source selection.
+  * @note   This configuration is only available with STM32F446xx Devices.      
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_SAI1CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used as SAI1 clock. 
+  *            @arg RCC_SAI1CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used as SAI1 clock.
+  *            @arg RCC_SAI1CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SAI1 clock.  
+  *            @arg RCC_SAI1CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as SAI1 clock.
+  */
+#define __HAL_RCC_GET_SAI1_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_SAI1SRC))
+
+/** @brief  Macro to configure SAI2 clock source selection.
+  * @note   This configuration is only available with STM32F446xx Devices.      
+  * @note   This function must be called before enabling PLL, PLLSAI, PLLI2S and  
+  *         the SAI clock.
+  * @param  __SOURCE__ specifies the SAI2 clock source.
+  *         This parameter can be one of the following values:
+  *            @arg RCC_SAI2CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used as SAI2 clock. 
+  *            @arg RCC_SAI2CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used as SAI2 clock.
+  *            @arg RCC_SAI2CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SAI2 clock.  
+  *            @arg RCC_SAI2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL Source clock used as SAI2 clock.
+  */
+#define __HAL_RCC_SAI2_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI2SRC, (__SOURCE__)))
+
+/** @brief  Macro to Get SAI2 clock source selection.
+  * @note   This configuration is only available with STM32F446xx Devices.      
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_SAI2CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used as SAI2 clock. 
+  *            @arg RCC_SAI2CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used as SAI2 clock.
+  *            @arg RCC_SAI2CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SAI2 clock.  
+  *            @arg RCC_SAI2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL Source clock used as SAI2 clock.
+  */
+#define __HAL_RCC_GET_SAI2_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_SAI2SRC))
+
+/** @brief  Macro to configure I2S APB1 clock source selection.
+  * @note   This function must be called before enabling PLL, PLLI2S and the I2S clock.
+  * @param  __SOURCE__ specifies the I2S APB1 clock source.
+  *         This parameter can be one of the following values:
+  *            @arg RCC_I2SAPB1CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR used as I2S clock. 
+  *            @arg RCC_I2SAPB1CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as I2S APB1 clock.
+  *            @arg RCC_I2SAPB1CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as I2S APB1 clock.  
+  *            @arg RCC_I2SAPB1CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.
+  */
+#define __HAL_RCC_I2S_APB1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_I2S1SRC, (__SOURCE__)))
+
+/** @brief  Macro to Get I2S APB1 clock source selection.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_I2SAPB1CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR used as I2S clock. 
+  *            @arg RCC_I2SAPB1CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as I2S APB1 clock.
+  *            @arg RCC_I2SAPB1CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as I2S APB1 clock.  
+  *            @arg RCC_I2SAPB1CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.
+  */
+#define __HAL_RCC_GET_I2S_APB1_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_I2S1SRC))
+
+/** @brief  Macro to configure I2S APB2 clock source selection.
+  * @note   This function must be called before enabling PLL, PLLI2S and the I2S clock.
+  * @param  __SOURCE__ specifies the SAI Block A clock source.
+  *         This parameter can be one of the following values:
+  *            @arg RCC_I2SAPB2CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR used as I2S clock. 
+  *            @arg RCC_I2SAPB2CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as I2S APB2 clock.
+  *            @arg RCC_I2SAPB2CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as I2S APB2 clock.  
+  *            @arg RCC_I2SAPB2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.
+  */
+#define __HAL_RCC_I2S_APB2_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_I2S2SRC, (__SOURCE__)))
+
+/** @brief  Macro to Get I2S APB2 clock source selection.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_I2SAPB2CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR used as I2S clock. 
+  *            @arg RCC_I2SAPB2CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as I2S APB2 clock.
+  *            @arg RCC_I2SAPB2CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as I2S APB2 clock.  
+  *            @arg RCC_I2SAPB2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.
+  */
+#define __HAL_RCC_GET_I2S_APB2_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_I2S2SRC))
+
+/** @brief  Macro to configure the CEC clock.
+  * @param  __SOURCE__ specifies the CEC clock source.
+  *         This parameter can be one of the following values:
+  *            @arg RCC_CECCLKSOURCE_HSI: HSI selected as CEC clock
+  *            @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock
+  */
+#define __HAL_RCC_CEC_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CECSEL, (uint32_t)(__SOURCE__)))
+
+/** @brief  Macro to Get the CEC clock.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_CECCLKSOURCE_HSI488: HSI selected as CEC clock
+  *            @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock
+  */
+#define __HAL_RCC_GET_CEC_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CECSEL))
+
+/** @brief  Macro to configure the FMPI2C1 clock.
+  * @param  __SOURCE__ specifies the FMPI2C1 clock source.
+  *         This parameter can be one of the following values:
+  *            @arg RCC_FMPI2C1CLKSOURCE_PCLK1: PCLK1 selected as FMPI2C1 clock
+  *            @arg RCC_FMPI2C1CLKSOURCE_SYSCLK: SYS clock selected as FMPI2C1 clock
+  *            @arg RCC_FMPI2C1CLKSOURCE_HSI: HSI selected as FMPI2C1 clock
+  */
+#define __HAL_RCC_FMPI2C1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL, (uint32_t)(__SOURCE__)))
+
+/** @brief  Macro to Get the FMPI2C1 clock.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_FMPI2C1CLKSOURCE_PCLK1: PCLK1 selected as FMPI2C1 clock
+  *            @arg RCC_FMPI2C1CLKSOURCE_SYSCLK: SYS clock selected as FMPI2C1 clock
+  *            @arg RCC_FMPI2C1CLKSOURCE_HSI: HSI selected as FMPI2C1 clock
+  */
+#define __HAL_RCC_GET_FMPI2C1_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL))
+
+/** @brief  Macro to configure the CLK48 clock.
+  * @param  __SOURCE__ specifies the CLK48 clock source.
+  *         This parameter can be one of the following values:
+  *            @arg RCC_CLK48CLKSOURCE_PLLQ: PLL VCO Output divided by PLLQ used as CLK48 clock. 
+  *            @arg RCC_CLK48CLKSOURCE_PLLSAIP: PLLSAI VCO Output divided by PLLSAIP used as CLK48 clock. 
+  */
+#define __HAL_RCC_CLK48_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL, (uint32_t)(__SOURCE__)))
+
+/** @brief  Macro to Get the CLK48 clock.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_CLK48CLKSOURCE_PLLQ: PLL VCO Output divided by PLLQ used as CLK48 clock. 
+  *            @arg RCC_CLK48CLKSOURCE_PLLSAIP: PLLSAI VCO Output divided by PLLSAIP used as CLK48 clock. 
+  */
+#define __HAL_RCC_GET_CLK48_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL))
+
+/** @brief  Macro to configure the SDIO clock.
+  * @param  __SOURCE__ specifies the SDIO clock source.
+  *         This parameter can be one of the following values:
+  *            @arg RCC_SDIOCLKSOURCE_CLK48: CLK48 output used as SDIO clock. 
+  *            @arg RCC_SDIOCLKSOURCE_SYSCLK: System clock output used as SDIO clock. 
+  */
+#define __HAL_RCC_SDIO_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_SDIOSEL, (uint32_t)(__SOURCE__)))
+
+/** @brief  Macro to Get the SDIO clock.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_SDIOCLKSOURCE_CLK48: CLK48 output used as SDIO clock. 
+  *            @arg RCC_SDIOCLKSOURCE_SYSCLK: System clock output used as SDIO clock. 
+  */
+#define __HAL_RCC_GET_SDIO_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_SDIOSEL))
+
+/** @brief  Macro to configure the SPDIFRX clock.
+  * @param  __SOURCE__ specifies the SPDIFRX clock source.
+  *         This parameter can be one of the following values:
+  *            @arg RCC_SPDIFRXCLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SPDIFRX clock.  
+  *            @arg RCC_SPDIFRXCLKSOURCE_PLLI2SP: PLLI2S VCO Output divided by PLLI2SP used as SPDIFRX clock. 
+  */
+#define __HAL_RCC_SPDIFRX_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_SPDIFRXSEL, (uint32_t)(__SOURCE__)))
+
+/** @brief  Macro to Get the SPDIFRX clock.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_SPDIFRXCLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SPDIFRX clock.  
+  *            @arg RCC_SPDIFRXCLKSOURCE_PLLI2SP: PLLI2S VCO Output divided by PLLI2SP used as SPDIFRX clock. 
+  */
+#define __HAL_RCC_GET_SPDIFRX_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_SPDIFRXSEL))
+#endif /* STM32F446xx */
+      
+#if defined(STM32F469xx) || defined(STM32F479xx)
+      
+/** @brief  Macro to configure the CLK48 clock.
+  * @param  __SOURCE__ specifies the CLK48 clock source.
+  *         This parameter can be one of the following values:
+  *            @arg RCC_CLK48CLKSOURCE_PLLQ: PLL VCO Output divided by PLLQ used as CLK48 clock. 
+  *            @arg RCC_CLK48CLKSOURCE_PLLSAIP: PLLSAI VCO Output divided by PLLSAIP used as CLK48 clock. 
+  */
+#define __HAL_RCC_CLK48_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CK48MSEL, (uint32_t)(__SOURCE__)))
+
+/** @brief  Macro to Get the CLK48 clock.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_CLK48CLKSOURCE_PLLQ: PLL VCO Output divided by PLLQ used as CLK48 clock. 
+  *            @arg RCC_CLK48CLKSOURCE_PLLSAIP: PLLSAI VCO Output divided by PLLSAIP used as CLK48 clock. 
+  */
+#define __HAL_RCC_GET_CLK48_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_CK48MSEL))
+
+/** @brief  Macro to configure the SDIO clock.
+  * @param  __SOURCE__ specifies the SDIO clock source.
+  *         This parameter can be one of the following values:
+  *            @arg RCC_SDIOCLKSOURCE_CLK48: CLK48 output used as SDIO clock. 
+  *            @arg RCC_SDIOCLKSOURCE_SYSCLK: System clock output used as SDIO clock. 
+  */
+#define __HAL_RCC_SDIO_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SDIOSEL, (uint32_t)(__SOURCE__)))
+
+/** @brief  Macro to Get the SDIO clock.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_SDIOCLKSOURCE_CLK48: CLK48 output used as SDIO clock. 
+  *            @arg RCC_SDIOCLKSOURCE_SYSCLK: System clock output used as SDIO clock. 
+  */
+#define __HAL_RCC_GET_SDIO_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_SDIOSEL))  
+      
+/** @brief  Macro to configure the DSI clock.
+  * @param  __SOURCE__ specifies the DSI clock source.
+  *         This parameter can be one of the following values:
+  *            @arg RCC_DSICLKSOURCE_PLLR: PLLR output used as DSI clock. 
+  *            @arg RCC_DSICLKSOURCE_DSIPHY: DSI-PHY output used as DSI clock. 
+  */
+#define __HAL_RCC_DSI_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_DSISEL, (uint32_t)(__SOURCE__)))
+
+/** @brief  Macro to Get the DSI clock.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_DSICLKSOURCE_PLLR: PLLR output used as DSI clock. 
+  *            @arg RCC_DSICLKSOURCE_DSIPHY: DSI-PHY output used as DSI clock. 
+  */
+#define __HAL_RCC_GET_DSI_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_DSISEL))       
+      
+#endif /* STM32F469xx || STM32F479xx */
+
+#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) ||\
+    defined(STM32F413xx) || defined(STM32F423xx)
+ /** @brief  Macro to configure the DFSDM1 clock.
+  * @param  __DFSDM1_CLKSOURCE__ specifies the DFSDM1 clock source.
+  *         This parameter can be one of the following values:
+  *            @arg RCC_DFSDM1CLKSOURCE_PCLK2: PCLK2 clock used as kernel clock. 
+  *            @arg RCC_DFSDM1CLKSOURCE_SYSCLK: System clock used as kernel clock.
+  * @retval None
+  */
+#define __HAL_RCC_DFSDM1_CONFIG(__DFSDM1_CLKSOURCE__)  MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM1SEL, (__DFSDM1_CLKSOURCE__))
+
+/** @brief  Macro to get the DFSDM1 clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_DFSDM1CLKSOURCE_PCLK2: PCLK2 clock used as kernel clock. 
+  *            @arg RCC_DFSDM1CLKSOURCE_SYSCLK: System clock used as kernel clock.
+  */
+#define __HAL_RCC_GET_DFSDM1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM1SEL)))
+
+/** @brief  Macro to configure DFSDM1 Audio clock source selection.
+  * @note   This configuration is only available with STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx/
+            STM32F413xx/STM32F423xx Devices.
+  * @param  __SOURCE__ specifies the DFSDM1 Audio clock source.
+  *         This parameter can be one of the following values:
+  *            @arg RCC_DFSDM1AUDIOCLKSOURCE_I2S1: CK_I2S_PCLK1 selected as audio clock
+  *            @arg RCC_DFSDM1AUDIOCLKSOURCE_I2S2: CK_I2S_PCLK2 selected as audio clock
+  */
+#define __HAL_RCC_DFSDM1AUDIO_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM1ASEL, (__SOURCE__)))
+
+/** @brief  Macro to Get DFSDM1 Audio clock source selection.
+  * @note   This configuration is only available with STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx/
+            STM32F413xx/STM32F423xx Devices.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_DFSDM1AUDIOCLKSOURCE_I2S1: CK_I2S_PCLK1 selected as audio clock
+  *            @arg RCC_DFSDM1AUDIOCLKSOURCE_I2S2: CK_I2S_PCLK2 selected as audio clock
+  */
+#define __HAL_RCC_GET_DFSDM1AUDIO_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM1ASEL))
+
+#if defined(STM32F413xx) || defined(STM32F423xx)
+ /** @brief  Macro to configure the DFSDM2 clock.
+  * @param  __DFSDM2_CLKSOURCE__ specifies the DFSDM1 clock source.
+  *         This parameter can be one of the following values:
+  *            @arg RCC_DFSDM2CLKSOURCE_PCLK2: PCLK2 clock used as kernel clock. 
+  *            @arg RCC_DFSDM2CLKSOURCE_SYSCLK: System clock used as kernel clock.
+  * @retval None
+  */
+#define __HAL_RCC_DFSDM2_CONFIG(__DFSDM2_CLKSOURCE__)  MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM1SEL, (__DFSDM2_CLKSOURCE__))
+
+/** @brief  Macro to get the DFSDM2 clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_DFSDM2CLKSOURCE_PCLK2: PCLK2 clock used as kernel clock. 
+  *            @arg RCC_DFSDM2CLKSOURCE_SYSCLK: System clock used as kernel clock.
+  */
+#define __HAL_RCC_GET_DFSDM2_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM1SEL)))
+
+/** @brief  Macro to configure DFSDM1 Audio clock source selection.
+  * @note   This configuration is only available with STM32F413xx/STM32F423xx Devices.
+  * @param  __SOURCE__ specifies the DFSDM2 Audio clock source.
+  *         This parameter can be one of the following values:
+  *            @arg RCC_DFSDM2AUDIOCLKSOURCE_I2S1: CK_I2S_PCLK1 selected as audio clock
+  *            @arg RCC_DFSDM2AUDIOCLKSOURCE_I2S2: CK_I2S_PCLK2 selected as audio clock
+  */
+#define __HAL_RCC_DFSDM2AUDIO_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM2ASEL, (__SOURCE__)))
+
+/** @brief  Macro to Get DFSDM2 Audio clock source selection.
+  * @note   This configuration is only available with STM32F413xx/STM32F423xx Devices.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_DFSDM2AUDIOCLKSOURCE_I2S1: CK_I2S_PCLK1 selected as audio clock
+  *            @arg RCC_DFSDM2AUDIOCLKSOURCE_I2S2: CK_I2S_PCLK2 selected as audio clock
+  */
+#define __HAL_RCC_GET_DFSDM2AUDIO_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM2ASEL))
+      
+/** @brief  Macro to configure SAI1BlockA clock source selection.
+  * @note   The SAI peripheral is only available with STM32F413xx/STM32F423xx Devices.      
+  * @note   This function must be called before enabling PLLSAI, PLLI2S and  
+  *         the SAI clock.
+  * @param  __SOURCE__ specifies the SAI Block A clock source.
+  *         This parameter can be one of the following values:
+  *            @arg RCC_SAIACLKSOURCE_PLLI2SR: PLLI2S_R clock divided (R2) used as SAI1 Block A clock.
+  *            @arg RCC_SAIACLKSOURCE_EXT: External clock mapped on the I2S_CKIN pinused as SAI1 Block A clock.
+  *            @arg RCC_SAIACLKSOURCE_PLLR: PLL_R clock divided (R1) used as SAI1 Block A clock.
+  *            @arg RCC_SAIACLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.
+  */
+#define __HAL_RCC_SAI_BLOCKACLKSOURCE_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI1ASRC, (__SOURCE__)))
+      
+/** @brief  Macro to Get SAI1 BlockA clock source selection.
+  * @note   This configuration is only available with STM32F413xx/STM32F423xx Devices.      
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_SAIACLKSOURCE_PLLI2SR: PLLI2S_R clock divided (R2) used as SAI1 Block A clock.
+  *            @arg RCC_SAIACLKSOURCE_EXT: External clock mapped on the I2S_CKIN pinused as SAI1 Block A clock.
+  *            @arg RCC_SAIACLKSOURCE_PLLR: PLL_R clock divided (R1) used as SAI1 Block A clock.
+  *            @arg RCC_SAIACLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.
+  */
+#define __HAL_RCC_GET_SAI_BLOCKA_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_SAI1ASRC))
+
+/** @brief  Macro to configure SAI1 BlockB clock source selection.
+  * @note   The SAI peripheral is only available with STM32F413xx/STM32F423xx Devices.
+  * @note   This function must be called before enabling PLLSAI, PLLI2S and  
+  *         the SAI clock.
+  * @param  __SOURCE__ specifies the SAI Block B clock source.
+  *         This parameter can be one of the following values:
+  *            @arg RCC_SAIBCLKSOURCE_PLLI2SR: PLLI2S_R clock divided (R2) used as SAI1 Block A clock.
+  *            @arg RCC_SAIBCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as SAI1 Block A clock.
+  *            @arg RCC_SAIBCLKSOURCE_PLLR: PLL_R clock divided (R1) used as SAI1 Block A clock.
+  *            @arg RCC_SAIBCLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.
+  */
+#define __HAL_RCC_SAI_BLOCKBCLKSOURCE_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI1BSRC, (__SOURCE__)))
+      
+/** @brief  Macro to Get SAI1 BlockB clock source selection.
+  * @note   This configuration is only available with STM32F413xx/STM32F423xx Devices.      
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_SAIBCLKSOURCE_PLLI2SR: PLLI2S_R clock divided (R2) used as SAI1 Block A clock.
+  *            @arg RCC_SAIBCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as SAI1 Block A clock.
+  *            @arg RCC_SAIBCLKSOURCE_PLLR: PLL_R clock divided (R1) used as SAI1 Block A clock.
+  *            @arg RCC_SAIBCLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.
+  */
+#define __HAL_RCC_GET_SAI_BLOCKB_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_SAI1BSRC))
+
+/** @brief  Macro to configure the LPTIM1 clock.
+  * @param  __SOURCE__ specifies the LPTIM1 clock source.
+  *         This parameter can be one of the following values:
+  *            @arg RCC_LPTIM1CLKSOURCE_PCLK1: PCLK selected as LPTIM1 clock
+  *            @arg RCC_LPTIM1CLKSOURCE_HSI: HSI clock selected as LPTIM1 clock
+  *            @arg RCC_LPTIM1CLKSOURCE_LSI: LSI selected as LPTIM1 clock
+  *            @arg RCC_LPTIM1CLKSOURCE_LSE: LSE selected as LPTIM1 clock
+  */
+#define __HAL_RCC_LPTIM1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL, (uint32_t)(__SOURCE__)))
+
+/** @brief  Macro to Get the LPTIM1 clock.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_LPTIM1CLKSOURCE_PCLK1: PCLK selected as LPTIM1 clock
+  *            @arg RCC_LPTIM1CLKSOURCE_HSI: HSI clock selected as LPTIM1 clock
+  *            @arg RCC_LPTIM1CLKSOURCE_LSI: LSI selected as LPTIM1 clock
+  *            @arg RCC_LPTIM1CLKSOURCE_LSE: LSE selected as LPTIM1 clock
+  */
+#define __HAL_RCC_GET_LPTIM1_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL))      
+#endif /* STM32F413xx || STM32F423xx */
+      
+/** @brief  Macro to configure I2S APB1 clock source selection.
+  * @param  __SOURCE__ specifies the I2S APB1 clock source.
+  *         This parameter can be one of the following values:
+  *            @arg RCC_I2SAPB1CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR.
+  *            @arg RCC_I2SAPB1CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin.
+  *            @arg RCC_I2SAPB1CLKSOURCE_PLLR: PLL VCO Output divided by PLLR.
+  *            @arg RCC_I2SAPB1CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.
+  */
+#define __HAL_RCC_I2S_APB1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_I2S1SRC, (__SOURCE__)))
+
+/** @brief  Macro to Get I2S APB1 clock source selection.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_I2SAPB1CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR.
+  *            @arg RCC_I2SAPB1CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin.
+  *            @arg RCC_I2SAPB1CLKSOURCE_PLLR: PLL VCO Output divided by PLLR.
+  *            @arg RCC_I2SAPB1CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.
+  */
+#define __HAL_RCC_GET_I2S_APB1_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_I2S1SRC))
+
+/** @brief  Macro to configure I2S APB2 clock source selection.
+  * @param  __SOURCE__ specifies the I2S APB2 clock source.
+  *         This parameter can be one of the following values:
+  *            @arg RCC_I2SAPB2CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR.
+  *            @arg RCC_I2SAPB2CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin.
+  *            @arg RCC_I2SAPB2CLKSOURCE_PLLR: PLL VCO Output divided by PLLR.
+  *            @arg RCC_I2SAPB2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.
+  */
+#define __HAL_RCC_I2S_APB2_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_I2S2SRC, (__SOURCE__)))
+
+/** @brief  Macro to Get I2S APB2 clock source selection.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_I2SAPB2CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR.
+  *            @arg RCC_I2SAPB2CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin.
+  *            @arg RCC_I2SAPB2CLKSOURCE_PLLR: PLL VCO Output divided by PLLR.
+  *            @arg RCC_I2SAPB2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.
+  */
+#define __HAL_RCC_GET_I2S_APB2_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_I2S2SRC))
+
+/** @brief  Macro to configure the PLL I2S clock source (PLLI2SCLK).
+  * @note   This macro must be called before enabling the I2S APB clock.
+  * @param  __SOURCE__ specifies the I2S clock source.
+  *         This parameter can be one of the following values:
+  *            @arg RCC_PLLI2SCLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.
+  *            @arg RCC_PLLI2SCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin
+  *                                       used as I2S clock source.
+  */
+#define __HAL_RCC_PLL_I2S_CONFIG(__SOURCE__) (*(__IO uint32_t *) RCC_PLLI2SCFGR_PLLI2SSRC_BB = (__SOURCE__))
+      
+/** @brief  Macro to configure the FMPI2C1 clock.
+  * @param  __SOURCE__ specifies the FMPI2C1 clock source.
+  *         This parameter can be one of the following values:
+  *            @arg RCC_FMPI2C1CLKSOURCE_PCLK1: PCLK1 selected as FMPI2C1 clock
+  *            @arg RCC_FMPI2C1CLKSOURCE_SYSCLK: SYS clock selected as FMPI2C1 clock
+  *            @arg RCC_FMPI2C1CLKSOURCE_HSI: HSI selected as FMPI2C1 clock
+  */
+#define __HAL_RCC_FMPI2C1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL, (uint32_t)(__SOURCE__)))
+
+/** @brief  Macro to Get the FMPI2C1 clock.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_FMPI2C1CLKSOURCE_PCLK1: PCLK1 selected as FMPI2C1 clock
+  *            @arg RCC_FMPI2C1CLKSOURCE_SYSCLK: SYS clock selected as FMPI2C1 clock
+  *            @arg RCC_FMPI2C1CLKSOURCE_HSI: HSI selected as FMPI2C1 clock
+  */
+#define __HAL_RCC_GET_FMPI2C1_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL))
+
+/** @brief  Macro to configure the CLK48 clock.
+  * @param  __SOURCE__ specifies the CLK48 clock source.
+  *         This parameter can be one of the following values:
+  *            @arg RCC_CLK48CLKSOURCE_PLLQ: PLL VCO Output divided by PLLQ used as CLK48 clock. 
+  *            @arg RCC_CLK48CLKSOURCE_PLLI2SQ: PLLI2S VCO Output divided by PLLI2SQ used as CLK48 clock.
+  */
+#define __HAL_RCC_CLK48_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL, (uint32_t)(__SOURCE__)))
+
+/** @brief  Macro to Get the CLK48 clock.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_CLK48CLKSOURCE_PLLQ: PLL VCO Output divided by PLLQ used as CLK48 clock. 
+  *            @arg RCC_CLK48CLKSOURCE_PLLI2SQ: PLLI2S VCO Output divided by PLLI2SQ used as CLK48 clock
+  */
+#define __HAL_RCC_GET_CLK48_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL))
+
+/** @brief  Macro to configure the SDIO clock.
+  * @param  __SOURCE__ specifies the SDIO clock source.
+  *         This parameter can be one of the following values:
+  *            @arg RCC_SDIOCLKSOURCE_CLK48: CLK48 output used as SDIO clock. 
+  *            @arg RCC_SDIOCLKSOURCE_SYSCLK: System clock output used as SDIO clock. 
+  */
+#define __HAL_RCC_SDIO_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_SDIOSEL, (uint32_t)(__SOURCE__)))
+
+/** @brief  Macro to Get the SDIO clock.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_SDIOCLKSOURCE_CLK48: CLK48 output used as SDIO clock. 
+  *            @arg RCC_SDIOCLKSOURCE_SYSCLK: System clock output used as SDIO clock. 
+  */
+#define __HAL_RCC_GET_SDIO_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_SDIOSEL))
+
+#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */
+
+#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
+/** @brief  Macro to configure I2S clock source selection.
+  * @param  __SOURCE__ specifies the I2S clock source.
+  *         This parameter can be one of the following values:
+  *            @arg RCC_I2SAPBCLKSOURCE_PLLR: PLL VCO output clock divided by PLLR.
+  *            @arg RCC_I2SAPBCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin.
+  *            @arg RCC_I2SAPBCLKSOURCE_PLLSRC: HSI/HSE depends on PLLSRC.
+  */
+#define __HAL_RCC_I2S_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_I2SSRC, (__SOURCE__)))
+
+/** @brief  Macro to Get I2S clock source selection.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_I2SAPBCLKSOURCE_PLLR: PLL VCO output clock divided by PLLR.
+  *            @arg RCC_I2SAPBCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin.
+  *            @arg RCC_I2SAPBCLKSOURCE_PLLSRC: HSI/HSE depends on PLLSRC.
+  */
+#define __HAL_RCC_GET_I2S_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_I2SSRC))
+
+/** @brief  Macro to configure the FMPI2C1 clock.
+  * @param  __SOURCE__ specifies the FMPI2C1 clock source.
+  *         This parameter can be one of the following values:
+  *            @arg RCC_FMPI2C1CLKSOURCE_PCLK1: PCLK1 selected as FMPI2C1 clock
+  *            @arg RCC_FMPI2C1CLKSOURCE_SYSCLK: SYS clock selected as FMPI2C1 clock
+  *            @arg RCC_FMPI2C1CLKSOURCE_HSI: HSI selected as FMPI2C1 clock
+  */
+#define __HAL_RCC_FMPI2C1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL, (uint32_t)(__SOURCE__)))
+
+/** @brief  Macro to Get the FMPI2C1 clock.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_FMPI2C1CLKSOURCE_PCLK1: PCLK1 selected as FMPI2C1 clock
+  *            @arg RCC_FMPI2C1CLKSOURCE_SYSCLK: SYS clock selected as FMPI2C1 clock
+  *            @arg RCC_FMPI2C1CLKSOURCE_HSI: HSI selected as FMPI2C1 clock
+  */
+#define __HAL_RCC_GET_FMPI2C1_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL))
+
+/** @brief  Macro to configure the LPTIM1 clock.
+  * @param  __SOURCE__ specifies the LPTIM1 clock source.
+  *         This parameter can be one of the following values:
+  *            @arg RCC_LPTIM1CLKSOURCE_PCLK1: PCLK1 selected as LPTIM1 clock
+  *            @arg RCC_LPTIM1CLKSOURCE_HSI: HSI clock selected as LPTIM1 clock
+  *            @arg RCC_LPTIM1CLKSOURCE_LSI: LSI selected as LPTIM1 clock
+  *            @arg RCC_LPTIM1CLKSOURCE_LSE: LSE selected as LPTIM1 clock
+  */
+#define __HAL_RCC_LPTIM1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL, (uint32_t)(__SOURCE__)))
+
+/** @brief  Macro to Get the LPTIM1 clock.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_LPTIM1CLKSOURCE_PCLK1: PCLK1 selected as LPTIM1 clock
+  *            @arg RCC_LPTIM1CLKSOURCE_HSI: HSI clock selected as LPTIM1 clock
+  *            @arg RCC_LPTIM1CLKSOURCE_LSI: LSI selected as LPTIM1 clock
+  *            @arg RCC_LPTIM1CLKSOURCE_LSE: LSE selected as LPTIM1 clock
+  */
+#define __HAL_RCC_GET_LPTIM1_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL))
+#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
+      
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
+    defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) ||\
+    defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F469xx) ||\
+    defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) ||\
+    defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
+/** @brief  Macro to configure the Timers clocks prescalers 
+  * @note   This feature is only available with STM32F429x/439x Devices.  
+  * @param  __PRESC__  specifies the Timers clocks prescalers selection
+  *         This parameter can be one of the following values:
+  *            @arg RCC_TIMPRES_DESACTIVATED: The Timers kernels clocks prescaler is 
+  *                 equal to HPRE if PPREx is corresponding to division by 1 or 2, 
+  *                 else it is equal to [(HPRE * PPREx) / 2] if PPREx is corresponding to 
+  *                 division by 4 or more.       
+  *            @arg RCC_TIMPRES_ACTIVATED: The Timers kernels clocks prescaler is 
+  *                 equal to HPRE if PPREx is corresponding to division by 1, 2 or 4, 
+  *                 else it is equal to [(HPRE * PPREx) / 4] if PPREx is corresponding 
+  *                 to division by 8 or more.
+  */     
+#define __HAL_RCC_TIMCLKPRESCALER(__PRESC__) (*(__IO uint32_t *) RCC_DCKCFGR_TIMPRE_BB = (__PRESC__))
+
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx) || STM32F401xC || STM32F401xE || STM32F410xx || STM32F411xE ||\
+          STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx  || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx ||\
+          STM32F423xx */
+
+/*----------------------------------------------------------------------------*/
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
+/** @brief Enable PLLSAI_RDY interrupt.
+  */
+#define __HAL_RCC_PLLSAI_ENABLE_IT() (RCC->CIR |= (RCC_CIR_PLLSAIRDYIE))
+
+/** @brief Disable PLLSAI_RDY interrupt.
+  */
+#define __HAL_RCC_PLLSAI_DISABLE_IT() (RCC->CIR &= ~(RCC_CIR_PLLSAIRDYIE))
+
+/** @brief Clear the PLLSAI RDY interrupt pending bits.
+  */
+#define __HAL_RCC_PLLSAI_CLEAR_IT() (RCC->CIR |= (RCC_CIR_PLLSAIRDYF))
+
+/** @brief Check the PLLSAI RDY interrupt has occurred or not.
+  * @retval The new state (TRUE or FALSE).
+  */
+#define __HAL_RCC_PLLSAI_GET_IT() ((RCC->CIR & (RCC_CIR_PLLSAIRDYIE)) == (RCC_CIR_PLLSAIRDYIE))
+
+/** @brief  Check PLLSAI RDY flag is set or not.
+  * @retval The new state (TRUE or FALSE).
+  */
+#define __HAL_RCC_PLLSAI_GET_FLAG() ((RCC->CR & (RCC_CR_PLLSAIRDY)) == (RCC_CR_PLLSAIRDY))
+
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
+
+#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
+/** @brief  Macros to enable or disable the RCC MCO1 feature.
+  */
+#define __HAL_RCC_MCO1_ENABLE() (*(__IO uint32_t *) RCC_CFGR_MCO1EN_BB = ENABLE)
+#define __HAL_RCC_MCO1_DISABLE() (*(__IO uint32_t *) RCC_CFGR_MCO1EN_BB = DISABLE)
+
+/** @brief  Macros to enable or disable the RCC MCO2 feature.
+  */
+#define __HAL_RCC_MCO2_ENABLE() (*(__IO uint32_t *) RCC_CFGR_MCO2EN_BB = ENABLE)
+#define __HAL_RCC_MCO2_DISABLE() (*(__IO uint32_t *) RCC_CFGR_MCO2EN_BB = DISABLE)
+
+#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup RCCEx_Exported_Functions
+  *  @{
+  */
+
+/** @addtogroup RCCEx_Exported_Functions_Group1
+  *  @{
+  */
+HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit);
+void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit);
+
+uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk);
+
+#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F411xE) ||\
+    defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) ||\
+    defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) ||\
+    defined(STM32F423xx)
+void HAL_RCCEx_SelectLSEMode(uint8_t Mode);
+#endif /* STM32F410xx || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */
+#if defined(RCC_PLLI2S_SUPPORT)
+HAL_StatusTypeDef HAL_RCCEx_EnablePLLI2S(RCC_PLLI2SInitTypeDef  *PLLI2SInit);
+HAL_StatusTypeDef HAL_RCCEx_DisablePLLI2S(void);
+#endif /* RCC_PLLI2S_SUPPORT */
+#if defined(RCC_PLLSAI_SUPPORT)
+HAL_StatusTypeDef HAL_RCCEx_EnablePLLSAI(RCC_PLLSAIInitTypeDef  *PLLSAIInit);
+HAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI(void);
+#endif /* RCC_PLLSAI_SUPPORT */
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup RCCEx_Private_Constants RCCEx Private Constants
+  * @{
+  */
+
+/** @defgroup RCCEx_BitAddress_AliasRegion RCC BitAddress AliasRegion
+  * @brief RCC registers bit address in the alias region
+  * @{
+  */
+/* --- CR Register ---*/  
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
+    defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
+/* Alias word address of PLLSAION bit */
+#define RCC_PLLSAION_BIT_NUMBER       0x1CU
+#define RCC_CR_PLLSAION_BB            (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32U) + (RCC_PLLSAION_BIT_NUMBER * 4U))
+
+#define PLLSAI_TIMEOUT_VALUE          2U  /* Timeout value fixed to 2 ms  */
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
+
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \
+    defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
+    defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \
+    defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
+    defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
+/* Alias word address of PLLI2SON bit */
+#define RCC_PLLI2SON_BIT_NUMBER    0x1AU
+#define RCC_CR_PLLI2SON_BB         (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32U) + (RCC_PLLI2SON_BIT_NUMBER * 4U))
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||
+          STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx ||
+          STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */
+
+/* --- DCKCFGR Register ---*/
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
+    defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F401xC) ||\
+    defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F469xx) ||\
+    defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) ||\
+    defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
+/* Alias word address of TIMPRE bit */
+#define RCC_DCKCFGR_OFFSET            (RCC_OFFSET + 0x8CU)
+#define RCC_TIMPRE_BIT_NUMBER          0x18U
+#define RCC_DCKCFGR_TIMPRE_BB         (PERIPH_BB_BASE + (RCC_DCKCFGR_OFFSET * 32U) + (RCC_TIMPRE_BIT_NUMBER * 4U))
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F410xx || STM32F401xC ||\
+          STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx ||\
+          STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */
+
+/* --- CFGR Register ---*/
+#define RCC_CFGR_OFFSET            (RCC_OFFSET + 0x08U)
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \
+    defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
+    defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \
+    defined(STM32F469xx) || defined(STM32F479xx)
+/* Alias word address of I2SSRC bit */
+#define RCC_I2SSRC_BIT_NUMBER      0x17U
+#define RCC_CFGR_I2SSRC_BB         (PERIPH_BB_BASE + (RCC_CFGR_OFFSET * 32U) + (RCC_I2SSRC_BIT_NUMBER * 4U))
+      
+#define PLLI2S_TIMEOUT_VALUE       2U  /* Timeout value fixed to 2 ms  */
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||
+          STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx */
+      
+#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) ||\
+    defined(STM32F413xx) || defined(STM32F423xx)
+/* --- PLLI2SCFGR Register ---*/
+#define RCC_PLLI2SCFGR_OFFSET         (RCC_OFFSET + 0x84U)
+/* Alias word address of PLLI2SSRC bit */
+#define RCC_PLLI2SSRC_BIT_NUMBER      0x16U
+#define RCC_PLLI2SCFGR_PLLI2SSRC_BB         (PERIPH_BB_BASE + (RCC_PLLI2SCFGR_OFFSET * 32U) + (RCC_PLLI2SSRC_BIT_NUMBER * 4U))
+      
+#define PLLI2S_TIMEOUT_VALUE          2U  /* Timeout value fixed to 2 ms */
+#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx | STM32F423xx */
+
+#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
+/* Alias word address of MCO1EN bit */
+#define RCC_MCO1EN_BIT_NUMBER      0x8U
+#define RCC_CFGR_MCO1EN_BB         (PERIPH_BB_BASE + (RCC_CFGR_OFFSET * 32U) + (RCC_MCO1EN_BIT_NUMBER * 4U))
+
+/* Alias word address of MCO2EN bit */
+#define RCC_MCO2EN_BIT_NUMBER      0x9U
+#define RCC_CFGR_MCO2EN_BB         (PERIPH_BB_BASE + (RCC_CFGR_OFFSET * 32U) + (RCC_MCO2EN_BIT_NUMBER * 4U))
+#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
+
+#define PLL_TIMEOUT_VALUE          2U  /* 2 ms */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup RCCEx_Private_Macros RCCEx Private Macros
+  * @{
+  */
+/** @defgroup RCCEx_IS_RCC_Definitions RCC Private macros to check input parameters
+  * @{
+  */
+#define IS_RCC_PLLN_VALUE(VALUE) ((50U <= (VALUE)) && ((VALUE) <= 432U))
+#define IS_RCC_PLLI2SN_VALUE(VALUE) ((50U <= (VALUE)) && ((VALUE) <= 432U))
+      
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
+#define IS_RCC_PERIPHCLOCK(SELECTION) ((1U <= (SELECTION)) && ((SELECTION) <= 0x0000007FU))
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx) 
+#define IS_RCC_PERIPHCLOCK(SELECTION) ((1U <= (SELECTION)) && ((SELECTION) <= 0x00000007U))
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
+
+#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) 
+#define IS_RCC_PERIPHCLOCK(SELECTION) ((1U <= (SELECTION)) && ((SELECTION) <= 0x0000000FU))
+#endif /* STM32F401xC || STM32F401xE || STM32F411xE */
+
+#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
+#define IS_RCC_PERIPHCLOCK(SELECTION) ((1U <= (SELECTION)) && ((SELECTION) <= 0x0000001FU))
+#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
+
+#if defined(STM32F446xx)
+#define IS_RCC_PERIPHCLOCK(SELECTION) ((1U <= (SELECTION)) && ((SELECTION) <= 0x00000FFFU))
+#endif /* STM32F446xx */
+
+#if defined(STM32F469xx) || defined(STM32F479xx)
+#define IS_RCC_PERIPHCLOCK(SELECTION) ((1U <= (SELECTION)) && ((SELECTION) <= 0x000001FFU))
+#endif /* STM32F469xx || STM32F479xx */
+
+#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx)
+#define IS_RCC_PERIPHCLOCK(SELECTION) ((1U <= (SELECTION)) && ((SELECTION) <= 0x000003FFU))
+#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */
+      
+#if defined(STM32F413xx) || defined(STM32F423xx)
+#define IS_RCC_PERIPHCLOCK(SELECTION) ((1U <= (SELECTION)) && ((SELECTION) <= 0x00007FFFU))
+#endif /* STM32F413xx || STM32F423xx */
+      
+#define IS_RCC_PLLI2SR_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 7U))
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) ||\
+    defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
+#define IS_RCC_PLLI2SQ_VALUE(VALUE)     ((2U <= (VALUE)) && ((VALUE) <= 15U))
+
+#define IS_RCC_PLLSAIN_VALUE(VALUE)     ((50U <= (VALUE)) && ((VALUE) <= 432U))
+
+#define IS_RCC_PLLSAIQ_VALUE(VALUE)     ((2U <= (VALUE)) && ((VALUE) <= 15U))
+
+#define IS_RCC_PLLSAIR_VALUE(VALUE)     ((2U <= (VALUE)) && ((VALUE) <= 7U))
+
+#define IS_RCC_PLLSAI_DIVQ_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 32U))
+
+#define IS_RCC_PLLI2S_DIVQ_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 32U))
+
+#define IS_RCC_PLLSAI_DIVR_VALUE(VALUE) (((VALUE) == RCC_PLLSAIDIVR_2)  ||\
+                                         ((VALUE) == RCC_PLLSAIDIVR_4)  ||\
+                                         ((VALUE) == RCC_PLLSAIDIVR_8)  ||\
+                                         ((VALUE) == RCC_PLLSAIDIVR_16))
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
+
+#if defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
+    defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
+#define IS_RCC_PLLI2SM_VALUE(VALUE)   ((2U <= (VALUE)) && ((VALUE) <= 63U))
+ 
+#define IS_RCC_LSE_MODE(MODE)           (((MODE) == RCC_LSE_LOWPOWER_MODE) ||\
+                                         ((MODE) == RCC_LSE_HIGHDRIVE_MODE))
+#endif /* STM32F411xE || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx  */
+
+#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
+#define IS_RCC_PLLR_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 7U))
+
+#define IS_RCC_LSE_MODE(MODE)           (((MODE) == RCC_LSE_LOWPOWER_MODE) ||\
+                                         ((MODE) == RCC_LSE_HIGHDRIVE_MODE))
+
+#define IS_RCC_FMPI2C1CLKSOURCE(SOURCE)   (((SOURCE) == RCC_FMPI2C1CLKSOURCE_PCLK1)    ||\
+                                           ((SOURCE) == RCC_FMPI2C1CLKSOURCE_SYSCLK) ||\
+                                           ((SOURCE) == RCC_FMPI2C1CLKSOURCE_HSI))
+
+#define IS_RCC_LPTIM1CLKSOURCE(SOURCE)   (((SOURCE) == RCC_LPTIM1CLKSOURCE_PCLK1) ||\
+                                          ((SOURCE) == RCC_LPTIM1CLKSOURCE_HSI) ||\
+                                          ((SOURCE) == RCC_LPTIM1CLKSOURCE_LSI) ||\
+                                          ((SOURCE) == RCC_LPTIM1CLKSOURCE_LSE))
+
+#define IS_RCC_I2SAPBCLKSOURCE(SOURCE)      (((SOURCE) == RCC_I2SAPBCLKSOURCE_PLLR)    ||\
+                                             ((SOURCE) == RCC_I2SAPBCLKSOURCE_EXT)    ||\
+                                             ((SOURCE) == RCC_I2SAPBCLKSOURCE_PLLSRC))
+#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
+
+#if defined(STM32F446xx)
+#define IS_RCC_PLLR_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 7U))
+  
+#define IS_RCC_PLLI2SP_VALUE(VALUE)       (((VALUE) == RCC_PLLI2SP_DIV2) ||\
+                                           ((VALUE) == RCC_PLLI2SP_DIV4) ||\
+                                           ((VALUE) == RCC_PLLI2SP_DIV6) ||\
+                                           ((VALUE) == RCC_PLLI2SP_DIV8))
+
+#define IS_RCC_PLLSAIM_VALUE(VALUE)       ((VALUE) <= 63U)
+  
+#define IS_RCC_PLLSAIP_VALUE(VALUE)       (((VALUE) == RCC_PLLSAIP_DIV2) ||\
+                                           ((VALUE) == RCC_PLLSAIP_DIV4) ||\
+                                           ((VALUE) == RCC_PLLSAIP_DIV6) ||\
+                                           ((VALUE) == RCC_PLLSAIP_DIV8))
+
+#define IS_RCC_SAI1CLKSOURCE(SOURCE)      (((SOURCE) == RCC_SAI1CLKSOURCE_PLLSAI) ||\
+                                           ((SOURCE) == RCC_SAI1CLKSOURCE_PLLI2S) ||\
+                                           ((SOURCE) == RCC_SAI1CLKSOURCE_PLLR)   ||\
+                                           ((SOURCE) == RCC_SAI1CLKSOURCE_EXT))
+
+#define IS_RCC_SAI2CLKSOURCE(SOURCE)      (((SOURCE) == RCC_SAI2CLKSOURCE_PLLSAI) ||\
+                                           ((SOURCE) == RCC_SAI2CLKSOURCE_PLLI2S) ||\
+                                           ((SOURCE) == RCC_SAI2CLKSOURCE_PLLR)   ||\
+                                           ((SOURCE) == RCC_SAI2CLKSOURCE_PLLSRC))
+ 
+#define IS_RCC_I2SAPB1CLKSOURCE(SOURCE)   (((SOURCE) == RCC_I2SAPB1CLKSOURCE_PLLI2S) ||\
+                                           ((SOURCE) == RCC_I2SAPB1CLKSOURCE_EXT)    ||\
+                                           ((SOURCE) == RCC_I2SAPB1CLKSOURCE_PLLR)   ||\
+                                           ((SOURCE) == RCC_I2SAPB1CLKSOURCE_PLLSRC))
+                                              
+ #define IS_RCC_I2SAPB2CLKSOURCE(SOURCE)  (((SOURCE) == RCC_I2SAPB2CLKSOURCE_PLLI2S) ||\
+                                           ((SOURCE) == RCC_I2SAPB2CLKSOURCE_EXT)    ||\
+                                           ((SOURCE) == RCC_I2SAPB2CLKSOURCE_PLLR)   ||\
+                                           ((SOURCE) == RCC_I2SAPB2CLKSOURCE_PLLSRC))
+
+#define IS_RCC_FMPI2C1CLKSOURCE(SOURCE)   (((SOURCE) == RCC_FMPI2C1CLKSOURCE_PCLK1)    ||\
+                                           ((SOURCE) == RCC_FMPI2C1CLKSOURCE_SYSCLK) ||\
+                                           ((SOURCE) == RCC_FMPI2C1CLKSOURCE_HSI))
+
+#define IS_RCC_CECCLKSOURCE(SOURCE)       (((SOURCE) == RCC_CECCLKSOURCE_HSI)   ||\
+                                           ((SOURCE) == RCC_CECCLKSOURCE_LSE))
+
+#define IS_RCC_CLK48CLKSOURCE(SOURCE)      (((SOURCE) == RCC_CLK48CLKSOURCE_PLLQ) ||\
+                                            ((SOURCE) == RCC_CLK48CLKSOURCE_PLLSAIP))
+
+#define IS_RCC_SDIOCLKSOURCE(SOURCE)      (((SOURCE) == RCC_SDIOCLKSOURCE_CLK48) ||\
+                                           ((SOURCE) == RCC_SDIOCLKSOURCE_SYSCLK))
+
+#define IS_RCC_SPDIFRXCLKSOURCE(SOURCE)   (((SOURCE) == RCC_SPDIFRXCLKSOURCE_PLLR) ||\
+                                           ((SOURCE) == RCC_SPDIFRXCLKSOURCE_PLLI2SP))  
+#endif /* STM32F446xx */
+
+#if defined(STM32F469xx) || defined(STM32F479xx)
+#define IS_RCC_PLLR_VALUE(VALUE)            ((2U <= (VALUE)) && ((VALUE) <= 7U))
+
+#define IS_RCC_PLLSAIP_VALUE(VALUE)         (((VALUE) == RCC_PLLSAIP_DIV2) ||\
+                                             ((VALUE) == RCC_PLLSAIP_DIV4) ||\
+                                             ((VALUE) == RCC_PLLSAIP_DIV6) ||\
+                                             ((VALUE) == RCC_PLLSAIP_DIV8))
+ 
+#define IS_RCC_CLK48CLKSOURCE(SOURCE)        (((SOURCE) == RCC_CLK48CLKSOURCE_PLLQ) ||\
+                                              ((SOURCE) == RCC_CLK48CLKSOURCE_PLLSAIP))
+
+#define IS_RCC_SDIOCLKSOURCE(SOURCE)        (((SOURCE) == RCC_SDIOCLKSOURCE_CLK48) ||\
+                                             ((SOURCE) == RCC_SDIOCLKSOURCE_SYSCLK))
+
+#define IS_RCC_DSIBYTELANECLKSOURCE(SOURCE) (((SOURCE) == RCC_DSICLKSOURCE_PLLR)  ||\
+                                             ((SOURCE) == RCC_DSICLKSOURCE_DSIPHY))
+
+#define IS_RCC_LSE_MODE(MODE)               (((MODE) == RCC_LSE_LOWPOWER_MODE) ||\
+                                             ((MODE) == RCC_LSE_HIGHDRIVE_MODE))
+#endif /* STM32F469xx || STM32F479xx */
+
+#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) ||\
+    defined(STM32F413xx) || defined(STM32F423xx)
+#define IS_RCC_PLLI2SQ_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 15U))
+    
+#define IS_RCC_PLLR_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 7U))
+
+#define IS_RCC_PLLI2SCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_PLLI2SCLKSOURCE_PLLSRC) || \
+                                            ((__SOURCE__) == RCC_PLLI2SCLKSOURCE_EXT))
+ 
+#define IS_RCC_I2SAPB1CLKSOURCE(SOURCE)   (((SOURCE) == RCC_I2SAPB1CLKSOURCE_PLLI2S) ||\
+                                           ((SOURCE) == RCC_I2SAPB1CLKSOURCE_EXT)    ||\
+                                           ((SOURCE) == RCC_I2SAPB1CLKSOURCE_PLLR)   ||\
+                                           ((SOURCE) == RCC_I2SAPB1CLKSOURCE_PLLSRC))
+                                              
+ #define IS_RCC_I2SAPB2CLKSOURCE(SOURCE)  (((SOURCE) == RCC_I2SAPB2CLKSOURCE_PLLI2S) ||\
+                                           ((SOURCE) == RCC_I2SAPB2CLKSOURCE_EXT)    ||\
+                                           ((SOURCE) == RCC_I2SAPB2CLKSOURCE_PLLR)   ||\
+                                           ((SOURCE) == RCC_I2SAPB2CLKSOURCE_PLLSRC))
+
+#define IS_RCC_FMPI2C1CLKSOURCE(SOURCE)   (((SOURCE) == RCC_FMPI2C1CLKSOURCE_PCLK1)    ||\
+                                           ((SOURCE) == RCC_FMPI2C1CLKSOURCE_SYSCLK) ||\
+                                           ((SOURCE) == RCC_FMPI2C1CLKSOURCE_HSI))
+
+#define IS_RCC_CLK48CLKSOURCE(SOURCE)      (((SOURCE) == RCC_CLK48CLKSOURCE_PLLQ) ||\
+                                            ((SOURCE) == RCC_CLK48CLKSOURCE_PLLI2SQ))
+
+#define IS_RCC_SDIOCLKSOURCE(SOURCE)      (((SOURCE) == RCC_SDIOCLKSOURCE_CLK48) ||\
+                                           ((SOURCE) == RCC_SDIOCLKSOURCE_SYSCLK))
+
+#define IS_RCC_DFSDM1CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_DFSDM1CLKSOURCE_PCLK2) || \
+                                            ((__SOURCE__) == RCC_DFSDM1CLKSOURCE_SYSCLK))
+
+#define IS_RCC_DFSDM1AUDIOCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_DFSDM1AUDIOCLKSOURCE_I2S1) || \
+                                                 ((__SOURCE__) == RCC_DFSDM1AUDIOCLKSOURCE_I2S2))
+
+#if defined(STM32F413xx) || defined(STM32F423xx)
+#define IS_RCC_DFSDM2CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_DFSDM2CLKSOURCE_PCLK2) || \
+                                            ((__SOURCE__) == RCC_DFSDM2CLKSOURCE_SYSCLK))
+
+#define IS_RCC_DFSDM2AUDIOCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_DFSDM2AUDIOCLKSOURCE_I2S1) || \
+                                                 ((__SOURCE__) == RCC_DFSDM2AUDIOCLKSOURCE_I2S2))
+
+#define IS_RCC_LPTIM1CLKSOURCE(SOURCE)   (((SOURCE) == RCC_LPTIM1CLKSOURCE_PCLK1) ||\
+                                          ((SOURCE) == RCC_LPTIM1CLKSOURCE_HSI)  ||\
+                                          ((SOURCE) == RCC_LPTIM1CLKSOURCE_LSI)  ||\
+                                          ((SOURCE) == RCC_LPTIM1CLKSOURCE_LSE))
+
+#define IS_RCC_SAIACLKSOURCE(SOURCE)     (((SOURCE) == RCC_SAIACLKSOURCE_PLLI2SR) ||\
+                                          ((SOURCE) == RCC_SAIACLKSOURCE_EXT)     ||\
+                                          ((SOURCE) == RCC_SAIACLKSOURCE_PLLR)    ||\
+                                          ((SOURCE) == RCC_SAIACLKSOURCE_PLLSRC))
+
+#define IS_RCC_SAIBCLKSOURCE(SOURCE)     (((SOURCE) == RCC_SAIBCLKSOURCE_PLLI2SR) ||\
+                                          ((SOURCE) == RCC_SAIBCLKSOURCE_EXT)     ||\
+                                          ((SOURCE) == RCC_SAIBCLKSOURCE_PLLR)    ||\
+                                          ((SOURCE) == RCC_SAIBCLKSOURCE_PLLSRC))
+
+#define IS_RCC_PLL_DIVR_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 32U))
+
+#define IS_RCC_PLLI2S_DIVR_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 32U))
+
+#endif /* STM32F413xx || STM32F423xx */
+#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */
+
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \
+    defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
+    defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \
+    defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
+    defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx)
+      
+#define IS_RCC_MCO2SOURCE(SOURCE) (((SOURCE) == RCC_MCO2SOURCE_SYSCLK) || ((SOURCE) == RCC_MCO2SOURCE_PLLI2SCLK)|| \
+                                   ((SOURCE) == RCC_MCO2SOURCE_HSE)    || ((SOURCE) == RCC_MCO2SOURCE_PLLCLK))
+
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||
+          STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || \
+          STM32F412Rx */
+
+#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)      
+#define IS_RCC_MCO2SOURCE(SOURCE) (((SOURCE) == RCC_MCO2SOURCE_SYSCLK) || ((SOURCE) == RCC_MCO2SOURCE_I2SCLK)|| \
+                                   ((SOURCE) == RCC_MCO2SOURCE_HSE)    || ((SOURCE) == RCC_MCO2SOURCE_PLLCLK))
+#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */  
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_RCC_EX_H */
+
diff --git a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_sai.h b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_sai.h
new file mode 100644
index 0000000..db26e88
--- /dev/null
+++ b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_sai.h
@@ -0,0 +1,895 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hal_sai.h
+  * @author  MCD Application Team
+  * @brief   Header file of SAI HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_SAI_H
+#define __STM32F4xx_HAL_SAI_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+  * @{
+  */
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
+    defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F413xx) || \
+    defined(STM32F423xx)
+
+/** @addtogroup SAI
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup SAI_Exported_Types SAI Exported Types
+  * @{
+  */
+
+/**
+  * @brief  HAL State structures definition
+  */
+typedef enum
+{
+  HAL_SAI_STATE_RESET      = 0x00U,  /*!< SAI not yet initialized or disabled                */
+  HAL_SAI_STATE_READY      = 0x01U,  /*!< SAI initialized and ready for use                  */
+  HAL_SAI_STATE_BUSY       = 0x02U,  /*!< SAI internal process is ongoing                    */
+  HAL_SAI_STATE_BUSY_TX    = 0x12U,  /*!< Data transmission process is ongoing               */
+  HAL_SAI_STATE_BUSY_RX    = 0x22U,  /*!< Data reception process is ongoing                  */
+  HAL_SAI_STATE_TIMEOUT    = 0x03U,  /*!< SAI timeout state                                  */
+  HAL_SAI_STATE_ERROR      = 0x04U   /*!< SAI error state                                    */
+} HAL_SAI_StateTypeDef;
+
+/**
+  * @brief  SAI Callback prototype
+  */
+typedef void (*SAIcallback)(void);
+
+/** @defgroup SAI_Init_Structure_definition SAI Init Structure definition
+  * @brief  SAI Init Structure definition
+  * @{
+  */
+typedef struct
+{
+  uint32_t AudioMode;           /*!< Specifies the SAI Block audio Mode.
+                                     This parameter can be a value of @ref SAI_Block_Mode                      */
+
+  uint32_t Synchro;             /*!< Specifies SAI Block synchronization
+                                     This parameter can be a value of @ref SAI_Block_Synchronization           */
+
+  uint32_t SynchroExt;          /*!< Specifies SAI external output synchronization, this setup is common
+                                     for BlockA and BlockB
+                                     This parameter can be a value of @ref SAI_Block_SyncExt
+                                     @note: If both audio blocks of same SAI are used, this parameter has
+                                            to be set to the same value for each audio block                   */
+
+  uint32_t OutputDrive;         /*!< Specifies when SAI Block outputs are driven.
+                                     This parameter can be a value of @ref SAI_Block_Output_Drive
+                                     @note this value has to be set before enabling the audio block
+                                     but after the audio block configuration.                                  */
+
+  uint32_t NoDivider;           /*!< Specifies whether master clock will be divided or not.
+                                     This parameter can be a value of @ref SAI_Block_NoDivider
+                                     @note  If bit NODIV in the SAI_xCR1 register is cleared, the frame length
+                                            should be aligned to a number equal to a power of 2, from 8 to 256.
+                                            If bit NODIV in the SAI_xCR1 register is set, the frame length can
+                                            take any of the values without constraint since the input clock of
+                                            the audio block should be equal to the bit clock.
+                                             There is no MCLK_x clock which can be output.                     */
+
+  uint32_t FIFOThreshold;       /*!< Specifies SAI Block FIFO threshold.
+                                     This parameter can be a value of @ref SAI_Block_Fifo_Threshold            */
+
+  uint32_t ClockSource;         /*!< Specifies the SAI Block x Clock source.
+                                     This parameter is not used for STM32F446xx devices.                       */
+
+  uint32_t AudioFrequency;      /*!< Specifies the audio frequency sampling.
+                                     This parameter can be a value of @ref SAI_Audio_Frequency                 */
+
+  uint32_t Mckdiv;              /*!< Specifies the master clock divider.
+                                     This parameter must be a number between Min_Data = 0 and Max_Data = 15.
+                                     @note This parameter is used only if AudioFrequency is set to
+                                           SAI_AUDIO_FREQUENCY_MCKDIV otherwise it is internally computed. */
+
+  uint32_t MonoStereoMode;      /*!< Specifies if the mono or stereo mode is selected.
+                                     This parameter can be a value of @ref SAI_Mono_Stereo_Mode                */
+
+  uint32_t CompandingMode;      /*!< Specifies the companding mode type.
+                                     This parameter can be a value of @ref SAI_Block_Companding_Mode           */
+
+  uint32_t TriState;            /*!< Specifies the companding mode type.
+                                     This parameter can be a value of @ref SAI_TRIState_Management             */
+
+  /* This part of the structure is automatically filled if your are using the high level initialisation
+     function HAL_SAI_InitProtocol                                                                             */
+
+  uint32_t Protocol;        /*!< Specifies the SAI Block protocol.
+                                 This parameter can be a value of @ref SAI_Block_Protocol                      */
+
+  uint32_t DataSize;        /*!< Specifies the SAI Block data size.
+                                 This parameter can be a value of @ref SAI_Block_Data_Size                     */
+
+  uint32_t FirstBit;        /*!< Specifies whether data transfers start from MSB or LSB bit.
+                                 This parameter can be a value of @ref SAI_Block_MSB_LSB_transmission          */
+
+  uint32_t ClockStrobing;   /*!< Specifies the SAI Block clock strobing edge sensitivity.
+                                 This parameter can be a value of @ref SAI_Block_Clock_Strobing                */
+} SAI_InitTypeDef;
+/**
+  * @}
+  */
+
+/** @defgroup SAI_Frame_Structure_definition SAI Frame Structure definition
+  * @brief  SAI Frame Init structure definition
+  * @note   For SPDIF and AC97 protocol, these parameters are not used (set by hardware).
+  * @{
+  */
+typedef struct
+{
+  uint32_t FrameLength;         /*!< Specifies the Frame length, the number of SCK clocks for each audio frame.
+                                     This parameter must be a number between Min_Data = 8 and Max_Data = 256.
+                                     @note  If master clock MCLK_x pin is declared as an output, the frame length
+                                            should be aligned to a number equal to power of 2 in order to keep
+                                            in an audio frame, an integer number of MCLK pulses by bit Clock. */
+
+  uint32_t ActiveFrameLength;  /*!< Specifies the Frame synchronization active level length.
+                                    This Parameter specifies the length in number of bit clock (SCK + 1)
+                                    of the active level of FS signal in audio frame.
+                                    This parameter must be a number between Min_Data = 1 and Max_Data = 128   */
+
+  uint32_t FSDefinition;       /*!< Specifies the Frame synchronization definition.
+                                    This parameter can be a value of @ref SAI_Block_FS_Definition             */
+
+  uint32_t FSPolarity;         /*!< Specifies the Frame synchronization Polarity.
+                                    This parameter can be a value of @ref SAI_Block_FS_Polarity               */
+
+  uint32_t FSOffset;           /*!< Specifies the Frame synchronization Offset.
+                                    This parameter can be a value of @ref SAI_Block_FS_Offset                 */
+} SAI_FrameInitTypeDef;
+/**
+  * @}
+  */
+
+/** @defgroup SAI_Slot_Structure_definition SAI Slot Structure definition
+  * @brief   SAI Block Slot Init Structure definition
+  * @note    For SPDIF protocol, these parameters are not used (set by hardware).
+  * @note    For AC97 protocol, only SlotActive parameter is used (the others are set by hardware).
+  * @{
+  */
+typedef struct
+{
+  uint32_t FirstBitOffset;  /*!< Specifies the position of first data transfer bit in the slot.
+                                 This parameter must be a number between Min_Data = 0 and Max_Data = 24 */
+
+  uint32_t SlotSize;        /*!< Specifies the Slot Size.
+                                 This parameter can be a value of @ref SAI_Block_Slot_Size              */
+
+  uint32_t SlotNumber;      /*!< Specifies the number of slot in the audio frame.
+                                 This parameter must be a number between Min_Data = 1 and Max_Data = 16 */
+
+  uint32_t SlotActive;      /*!< Specifies the slots in audio frame that will be activated.
+                                 This parameter can be a value of @ref SAI_Block_Slot_Active            */
+} SAI_SlotInitTypeDef;
+/**
+  * @}
+  */
+
+/** @defgroup SAI_Handle_Structure_definition SAI Handle Structure definition
+  * @brief  SAI handle Structure definition
+  * @{
+  */
+typedef struct __SAI_HandleTypeDef
+{
+  SAI_Block_TypeDef         *Instance;  /*!< SAI Blockx registers base address        */
+
+  SAI_InitTypeDef           Init;       /*!< SAI communication parameters             */
+
+  SAI_FrameInitTypeDef      FrameInit;  /*!< SAI Frame configuration parameters       */
+
+  SAI_SlotInitTypeDef       SlotInit;   /*!< SAI Slot configuration parameters        */
+
+  uint8_t                  *pBuffPtr;  /*!< Pointer to SAI transfer Buffer            */
+
+  uint16_t                  XferSize;  /*!< SAI transfer size                         */
+
+  uint16_t                  XferCount; /*!< SAI transfer counter                      */
+
+  DMA_HandleTypeDef         *hdmatx;     /*!< SAI Tx DMA handle parameters            */
+
+  DMA_HandleTypeDef         *hdmarx;     /*!< SAI Rx DMA handle parameters            */
+
+  SAIcallback               mutecallback;/*!< SAI mute callback                       */
+
+  void (*InterruptServiceRoutine)(struct __SAI_HandleTypeDef *hsai); /* function pointer for IRQ handler   */
+
+  HAL_LockTypeDef           Lock;        /*!< SAI locking object                      */
+
+  __IO HAL_SAI_StateTypeDef State;       /*!< SAI communication state                 */
+
+  __IO uint32_t             ErrorCode;    /*!< SAI Error code */
+
+#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
+  void (*RxCpltCallback)(struct __SAI_HandleTypeDef *hsai);      /*!< SAI receive complete callback */
+  void (*RxHalfCpltCallback)(struct __SAI_HandleTypeDef *hsai);  /*!< SAI receive half complete callback */
+  void (*TxCpltCallback)(struct __SAI_HandleTypeDef *hsai);      /*!< SAI transmit complete callback */
+  void (*TxHalfCpltCallback)(struct __SAI_HandleTypeDef *hsai);  /*!< SAI transmit half complete callback */
+  void (*ErrorCallback)(struct __SAI_HandleTypeDef *hsai);       /*!< SAI error callback */
+  void (*MspInitCallback)(struct __SAI_HandleTypeDef *hsai);     /*!< SAI MSP init callback */
+  void (*MspDeInitCallback)(struct __SAI_HandleTypeDef *hsai);   /*!< SAI MSP de-init callback */
+#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */
+} SAI_HandleTypeDef;
+/**
+  * @}
+  */
+
+#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
+/**
+  * @brief  SAI callback ID enumeration definition
+  */
+typedef enum
+{
+  HAL_SAI_RX_COMPLETE_CB_ID       = 0x00U, /*!< SAI receive complete callback ID */
+  HAL_SAI_RX_HALFCOMPLETE_CB_ID   = 0x01U, /*!< SAI receive half complete callback ID */
+  HAL_SAI_TX_COMPLETE_CB_ID       = 0x02U, /*!< SAI transmit complete callback ID */
+  HAL_SAI_TX_HALFCOMPLETE_CB_ID   = 0x03U, /*!< SAI transmit half complete callback ID */
+  HAL_SAI_ERROR_CB_ID             = 0x04U, /*!< SAI error callback ID */
+  HAL_SAI_MSPINIT_CB_ID           = 0x05U, /*!< SAI MSP init callback ID */
+  HAL_SAI_MSPDEINIT_CB_ID         = 0x06U  /*!< SAI MSP de-init callback ID */
+} HAL_SAI_CallbackIDTypeDef;
+
+/**
+  * @brief  SAI callback pointer definition
+  */
+typedef void (*pSAI_CallbackTypeDef)(SAI_HandleTypeDef *hsai);
+#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup SAI_Exported_Constants SAI Exported Constants
+  * @{
+  */
+
+/** @defgroup SAI_Error_Code SAI Error Code
+  * @{
+  */
+#define HAL_SAI_ERROR_NONE    0x00000000U  /*!< No error                                    */
+#define HAL_SAI_ERROR_OVR     0x00000001U  /*!< Overrun Error                               */
+#define HAL_SAI_ERROR_UDR     0x00000002U  /*!< Underrun error                              */
+#define HAL_SAI_ERROR_AFSDET  0x00000004U  /*!< Anticipated Frame synchronisation detection */
+#define HAL_SAI_ERROR_LFSDET  0x00000008U  /*!< Late Frame synchronisation detection        */
+#define HAL_SAI_ERROR_CNREADY 0x00000010U  /*!< codec not ready                             */
+#define HAL_SAI_ERROR_WCKCFG  0x00000020U  /*!< Wrong clock configuration                   */
+#define HAL_SAI_ERROR_TIMEOUT 0x00000040U  /*!< Timeout error                               */
+#define HAL_SAI_ERROR_DMA     0x00000080U  /*!< DMA error                                   */
+#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
+#define HAL_SAI_ERROR_INVALID_CALLBACK   0x00000100U  /*!< Invalid callback error */
+#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */
+/**
+  * @}
+  */
+
+/** @defgroup SAI_Block_SyncExt SAI External synchronisation
+  * @{
+  */
+#define SAI_SYNCEXT_DISABLE          0U
+#define SAI_SYNCEXT_OUTBLOCKA_ENABLE 1U
+#define SAI_SYNCEXT_OUTBLOCKB_ENABLE 2U
+/**
+  * @}
+  */
+
+/** @defgroup SAI_Protocol SAI Supported protocol
+  * @{
+  */
+#define SAI_I2S_STANDARD      0U
+#define SAI_I2S_MSBJUSTIFIED  1U
+#define SAI_I2S_LSBJUSTIFIED  2U
+#define SAI_PCM_LONG          3U
+#define SAI_PCM_SHORT         4U
+/**
+  * @}
+  */
+
+/** @defgroup SAI_Protocol_DataSize SAI protocol data size
+  * @{
+  */
+#define SAI_PROTOCOL_DATASIZE_16BIT         0U
+#define SAI_PROTOCOL_DATASIZE_16BITEXTENDED 1U
+#define SAI_PROTOCOL_DATASIZE_24BIT         2U
+#define SAI_PROTOCOL_DATASIZE_32BIT         3U
+/**
+  * @}
+  */
+
+/** @defgroup SAI_Audio_Frequency SAI Audio Frequency
+  * @{
+  */
+#define SAI_AUDIO_FREQUENCY_192K          192000U
+#define SAI_AUDIO_FREQUENCY_96K           96000U
+#define SAI_AUDIO_FREQUENCY_48K           48000U
+#define SAI_AUDIO_FREQUENCY_44K           44100U
+#define SAI_AUDIO_FREQUENCY_32K           32000U
+#define SAI_AUDIO_FREQUENCY_22K           22050U
+#define SAI_AUDIO_FREQUENCY_16K           16000U
+#define SAI_AUDIO_FREQUENCY_11K           11025U
+#define SAI_AUDIO_FREQUENCY_8K            8000U
+#define SAI_AUDIO_FREQUENCY_MCKDIV        0U
+/**
+  * @}
+  */
+
+/** @defgroup SAI_Block_Mode SAI Block Mode
+  * @{
+  */
+#define SAI_MODEMASTER_TX         0x00000000U
+#define SAI_MODEMASTER_RX         ((uint32_t)SAI_xCR1_MODE_0)
+#define SAI_MODESLAVE_TX          ((uint32_t)SAI_xCR1_MODE_1)
+#define SAI_MODESLAVE_RX          ((uint32_t)(SAI_xCR1_MODE_1 | SAI_xCR1_MODE_0))
+/**
+  * @}
+  */
+
+/** @defgroup SAI_Block_Protocol SAI Block Protocol
+  * @{
+  */
+#define SAI_FREE_PROTOCOL                 0x00000000U
+#define SAI_SPDIF_PROTOCOL                ((uint32_t)SAI_xCR1_PRTCFG_0)
+#define SAI_AC97_PROTOCOL                 ((uint32_t)SAI_xCR1_PRTCFG_1)
+/**
+  * @}
+  */
+
+/** @defgroup SAI_Block_Data_Size SAI Block Data Size
+  * @{
+  */
+#define SAI_DATASIZE_8                   ((uint32_t)SAI_xCR1_DS_1)
+#define SAI_DATASIZE_10                  ((uint32_t)(SAI_xCR1_DS_1 | SAI_xCR1_DS_0))
+#define SAI_DATASIZE_16                  ((uint32_t)SAI_xCR1_DS_2)
+#define SAI_DATASIZE_20                  ((uint32_t)(SAI_xCR1_DS_2 | SAI_xCR1_DS_0))
+#define SAI_DATASIZE_24                  ((uint32_t)(SAI_xCR1_DS_2 | SAI_xCR1_DS_1))
+#define SAI_DATASIZE_32                  ((uint32_t)(SAI_xCR1_DS_2 | SAI_xCR1_DS_1 | SAI_xCR1_DS_0))
+/**
+  * @}
+  */
+
+/** @defgroup SAI_Block_MSB_LSB_transmission SAI Block MSB LSB transmission
+  * @{
+  */
+#define SAI_FIRSTBIT_MSB                  0x00000000U
+#define SAI_FIRSTBIT_LSB                  ((uint32_t)SAI_xCR1_LSBFIRST)
+/**
+  * @}
+  */
+
+/** @defgroup SAI_Block_Clock_Strobing SAI Block Clock Strobing
+  * @{
+  */
+#define SAI_CLOCKSTROBING_FALLINGEDGE     0U
+#define SAI_CLOCKSTROBING_RISINGEDGE      1U
+/**
+  * @}
+  */
+
+/** @defgroup SAI_Block_Synchronization SAI Block Synchronization
+  * @{
+  */
+#define SAI_ASYNCHRONOUS                  0U /*!< Asynchronous                             */
+#define SAI_SYNCHRONOUS                   1U /*!< Synchronous with other block of same SAI */
+#define SAI_SYNCHRONOUS_EXT_SAI1          2U /*!< Synchronous with other SAI, SAI1         */
+#define SAI_SYNCHRONOUS_EXT_SAI2          3U /*!< Synchronous with other SAI, SAI2         */
+/**
+  * @}
+  */
+
+/** @defgroup SAI_Block_Output_Drive SAI Block Output Drive
+  * @{
+  */
+#define SAI_OUTPUTDRIVE_DISABLE          0x00000000U
+#define SAI_OUTPUTDRIVE_ENABLE           ((uint32_t)SAI_xCR1_OUTDRIV)
+/**
+  * @}
+  */
+
+/** @defgroup SAI_Block_NoDivider SAI Block NoDivider
+  * @{
+  */
+#define SAI_MASTERDIVIDER_ENABLE         0x00000000U
+#define SAI_MASTERDIVIDER_DISABLE        ((uint32_t)SAI_xCR1_NODIV)
+/**
+  * @}
+  */
+
+/** @defgroup SAI_Block_FS_Definition SAI Block FS Definition
+  * @{
+  */
+#define SAI_FS_STARTFRAME                 0x00000000U
+#define SAI_FS_CHANNEL_IDENTIFICATION     ((uint32_t)SAI_xFRCR_FSDEF)
+/**
+  * @}
+  */
+
+/** @defgroup SAI_Block_FS_Polarity SAI Block FS Polarity
+  * @{
+  */
+#define SAI_FS_ACTIVE_LOW                  0x00000000U
+#define SAI_FS_ACTIVE_HIGH                 ((uint32_t)SAI_xFRCR_FSPOL)
+/**
+  * @}
+  */
+
+/** @defgroup SAI_Block_FS_Offset SAI Block FS Offset
+  * @{
+  */
+#define SAI_FS_FIRSTBIT                   0x00000000U
+#define SAI_FS_BEFOREFIRSTBIT             ((uint32_t)SAI_xFRCR_FSOFF)
+/**
+  * @}
+  */
+
+/** @defgroup SAI_Block_Slot_Size SAI Block Slot Size
+  * @{
+  */
+#define SAI_SLOTSIZE_DATASIZE             0x00000000U
+#define SAI_SLOTSIZE_16B                  ((uint32_t)SAI_xSLOTR_SLOTSZ_0)
+#define SAI_SLOTSIZE_32B                  ((uint32_t)SAI_xSLOTR_SLOTSZ_1)
+/**
+  * @}
+  */
+
+/** @defgroup SAI_Block_Slot_Active SAI Block Slot Active
+  * @{
+  */
+#define SAI_SLOT_NOTACTIVE           0x00000000U
+#define SAI_SLOTACTIVE_0             0x00000001U
+#define SAI_SLOTACTIVE_1             0x00000002U
+#define SAI_SLOTACTIVE_2             0x00000004U
+#define SAI_SLOTACTIVE_3             0x00000008U
+#define SAI_SLOTACTIVE_4             0x00000010U
+#define SAI_SLOTACTIVE_5             0x00000020U
+#define SAI_SLOTACTIVE_6             0x00000040U
+#define SAI_SLOTACTIVE_7             0x00000080U
+#define SAI_SLOTACTIVE_8             0x00000100U
+#define SAI_SLOTACTIVE_9             0x00000200U
+#define SAI_SLOTACTIVE_10            0x00000400U
+#define SAI_SLOTACTIVE_11            0x00000800U
+#define SAI_SLOTACTIVE_12            0x00001000U
+#define SAI_SLOTACTIVE_13            0x00002000U
+#define SAI_SLOTACTIVE_14            0x00004000U
+#define SAI_SLOTACTIVE_15            0x00008000U
+#define SAI_SLOTACTIVE_ALL           0x0000FFFFU
+/**
+  * @}
+  */
+
+/** @defgroup SAI_Mono_Stereo_Mode SAI Mono Stereo Mode
+  * @{
+  */
+#define SAI_STEREOMODE                    0x00000000U
+#define SAI_MONOMODE                      ((uint32_t)SAI_xCR1_MONO)
+/**
+  * @}
+  */
+
+/** @defgroup SAI_TRIState_Management SAI TRIState Management
+  * @{
+  */
+#define SAI_OUTPUT_NOTRELEASED              0x00000000U
+#define SAI_OUTPUT_RELEASED                 ((uint32_t)SAI_xCR2_TRIS)
+/**
+  * @}
+  */
+
+/** @defgroup SAI_Block_Fifo_Threshold SAI Block Fifo Threshold
+  * @{
+  */
+#define SAI_FIFOTHRESHOLD_EMPTY  0x00000000U
+#define SAI_FIFOTHRESHOLD_1QF    ((uint32_t)(SAI_xCR2_FTH_0))
+#define SAI_FIFOTHRESHOLD_HF     ((uint32_t)(SAI_xCR2_FTH_1))
+#define SAI_FIFOTHRESHOLD_3QF    ((uint32_t)(SAI_xCR2_FTH_1 | SAI_xCR2_FTH_0))
+#define SAI_FIFOTHRESHOLD_FULL   ((uint32_t)(SAI_xCR2_FTH_2))
+/**
+  * @}
+  */
+
+/** @defgroup SAI_Block_Companding_Mode SAI Block Companding Mode
+  * @{
+  */
+#define SAI_NOCOMPANDING                 0x00000000U
+#define SAI_ULAW_1CPL_COMPANDING         ((uint32_t)(SAI_xCR2_COMP_1))
+#define SAI_ALAW_1CPL_COMPANDING         ((uint32_t)(SAI_xCR2_COMP_1 | SAI_xCR2_COMP_0))
+#define SAI_ULAW_2CPL_COMPANDING         ((uint32_t)(SAI_xCR2_COMP_1 | SAI_xCR2_CPL))
+#define SAI_ALAW_2CPL_COMPANDING         ((uint32_t)(SAI_xCR2_COMP_1 | SAI_xCR2_COMP_0 | SAI_xCR2_CPL))
+/**
+  * @}
+  */
+
+/** @defgroup SAI_Block_Mute_Value SAI Block Mute Value
+  * @{
+  */
+#define SAI_ZERO_VALUE                      0x00000000U
+#define SAI_LAST_SENT_VALUE                 ((uint32_t)SAI_xCR2_MUTEVAL)
+/**
+  * @}
+  */
+
+/** @defgroup SAI_Block_Interrupts_Definition SAI Block Interrupts Definition
+  * @{
+  */
+#define SAI_IT_OVRUDR                     ((uint32_t)SAI_xIMR_OVRUDRIE)
+#define SAI_IT_MUTEDET                    ((uint32_t)SAI_xIMR_MUTEDETIE)
+#define SAI_IT_WCKCFG                     ((uint32_t)SAI_xIMR_WCKCFGIE)
+#define SAI_IT_FREQ                       ((uint32_t)SAI_xIMR_FREQIE)
+#define SAI_IT_CNRDY                      ((uint32_t)SAI_xIMR_CNRDYIE)
+#define SAI_IT_AFSDET                     ((uint32_t)SAI_xIMR_AFSDETIE)
+#define SAI_IT_LFSDET                     ((uint32_t)SAI_xIMR_LFSDETIE)
+/**
+  * @}
+  */
+
+/** @defgroup SAI_Block_Flags_Definition  SAI Block Flags Definition
+  * @{
+  */
+#define SAI_FLAG_OVRUDR                   ((uint32_t)SAI_xSR_OVRUDR)
+#define SAI_FLAG_MUTEDET                  ((uint32_t)SAI_xSR_MUTEDET)
+#define SAI_FLAG_WCKCFG                   ((uint32_t)SAI_xSR_WCKCFG)
+#define SAI_FLAG_FREQ                     ((uint32_t)SAI_xSR_FREQ)
+#define SAI_FLAG_CNRDY                    ((uint32_t)SAI_xSR_CNRDY)
+#define SAI_FLAG_AFSDET                   ((uint32_t)SAI_xSR_AFSDET)
+#define SAI_FLAG_LFSDET                   ((uint32_t)SAI_xSR_LFSDET)
+/**
+  * @}
+  */
+
+/** @defgroup SAI_Block_Fifo_Status_Level   SAI Block Fifo Status Level
+  * @{
+  */
+#define SAI_FIFOSTATUS_EMPTY              0x00000000U
+#define SAI_FIFOSTATUS_LESS1QUARTERFULL   0x00010000U
+#define SAI_FIFOSTATUS_1QUARTERFULL       0x00020000U
+#define SAI_FIFOSTATUS_HALFFULL           0x00030000U
+#define SAI_FIFOSTATUS_3QUARTERFULL       0x00040000U
+#define SAI_FIFOSTATUS_FULL               0x00050000U
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup SAI_Exported_Macros SAI Exported Macros
+  * @brief macros to handle interrupts and specific configurations
+  * @{
+  */
+
+/** @brief Reset SAI handle state
+  * @param  __HANDLE__ specifies the SAI Handle.
+  * @retval None
+  */
+#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
+#define __HAL_SAI_RESET_HANDLE_STATE(__HANDLE__) do{                                            \
+                                                     (__HANDLE__)->State = HAL_SAI_STATE_RESET; \
+                                                     (__HANDLE__)->MspInitCallback = NULL;      \
+                                                     (__HANDLE__)->MspDeInitCallback = NULL;    \
+                                                   } while(0U)
+#else
+#define __HAL_SAI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SAI_STATE_RESET)
+#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */
+
+/** @brief  Enable or disable the specified SAI interrupts.
+  * @param  __HANDLE__ specifies the SAI Handle.
+  * @param  __INTERRUPT__ specifies the interrupt source to enable or disable.
+  *         This parameter can be one of the following values:
+  *            @arg SAI_IT_OVRUDR: Overrun underrun interrupt enable
+  *            @arg SAI_IT_MUTEDET: Mute detection interrupt enable
+  *            @arg SAI_IT_WCKCFG: Wrong Clock Configuration interrupt enable
+  *            @arg SAI_IT_FREQ: FIFO request interrupt enable
+  *            @arg SAI_IT_CNRDY: Codec not ready interrupt enable
+  *            @arg SAI_IT_AFSDET: Anticipated frame synchronization detection interrupt enable
+  *            @arg SAI_IT_LFSDET: Late frame synchronization detection interrupt enable
+  * @retval None
+  */
+#define __HAL_SAI_ENABLE_IT(__HANDLE__, __INTERRUPT__)   ((__HANDLE__)->Instance->IMR |= (__INTERRUPT__))
+#define __HAL_SAI_DISABLE_IT(__HANDLE__, __INTERRUPT__)  ((__HANDLE__)->Instance->IMR &= (~(__INTERRUPT__)))
+
+/** @brief  Check if the specified SAI interrupt source is enabled or disabled.
+  * @param  __HANDLE__ specifies the SAI Handle.
+  *         This parameter can be SAI where x: 1, 2, or 3 to select the SAI peripheral.
+  * @param  __INTERRUPT__ specifies the SAI interrupt source to check.
+  *         This parameter can be one of the following values:
+  *            @arg SAI_IT_OVRUDR: Overrun underrun interrupt enable
+  *            @arg SAI_IT_MUTEDET: Mute detection interrupt enable
+  *            @arg SAI_IT_WCKCFG: Wrong Clock Configuration interrupt enable
+  *            @arg SAI_IT_FREQ: FIFO request interrupt enable
+  *            @arg SAI_IT_CNRDY: Codec not ready interrupt enable
+  *            @arg SAI_IT_AFSDET: Anticipated frame synchronization detection interrupt enable
+  *            @arg SAI_IT_LFSDET: Late frame synchronization detection interrupt enable
+  * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
+  */
+#define __HAL_SAI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IMR & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
+
+/** @brief  Check whether the specified SAI flag is set or not.
+  * @param  __HANDLE__ specifies the SAI Handle.
+  * @param  __FLAG__ specifies the flag to check.
+  *         This parameter can be one of the following values:
+  *            @arg SAI_FLAG_OVRUDR: Overrun underrun flag.
+  *            @arg SAI_FLAG_MUTEDET: Mute detection flag.
+  *            @arg SAI_FLAG_WCKCFG: Wrong Clock Configuration flag.
+  *            @arg SAI_FLAG_FREQ: FIFO request flag.
+  *            @arg SAI_FLAG_CNRDY: Codec not ready flag.
+  *            @arg SAI_FLAG_AFSDET: Anticipated frame synchronization detection flag.
+  *            @arg SAI_FLAG_LFSDET: Late frame synchronization detection flag.
+  * @retval The new state of __FLAG__ (TRUE or FALSE).
+  */
+#define __HAL_SAI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
+
+/** @brief  Clear the specified SAI pending flag.
+  * @param  __HANDLE__ specifies the SAI Handle.
+  * @param  __FLAG__ specifies the flag to check.
+  *          This parameter can be any combination of the following values:
+  *            @arg SAI_FLAG_OVRUDR: Clear Overrun underrun
+  *            @arg SAI_FLAG_MUTEDET: Clear Mute detection
+  *            @arg SAI_FLAG_WCKCFG: Clear Wrong Clock Configuration
+  *            @arg SAI_FLAG_FREQ: Clear FIFO request
+  *            @arg SAI_FLAG_CNRDY: Clear Codec not ready
+  *            @arg SAI_FLAG_AFSDET: Clear Anticipated frame synchronization detection
+  *            @arg SAI_FLAG_LFSDET: Clear Late frame synchronization detection
+  * @retval None
+  */
+#define __HAL_SAI_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->CLRFR = (__FLAG__))
+
+/** @brief  Enable SAI
+  * @param  __HANDLE__ specifies the SAI Handle.
+  * @retval None
+  */
+#define __HAL_SAI_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |=  SAI_xCR1_SAIEN)
+
+/** @brief  Disable SAI
+  * @param  __HANDLE__ specifies the SAI Handle.
+  * @retval None
+  */
+#define __HAL_SAI_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &=  ~SAI_xCR1_SAIEN)
+
+/**
+  * @}
+  */
+
+/* Include HAL SAI Extension module */
+#include "stm32f4xx_hal_sai_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup SAI_Exported_Functions
+  * @{
+  */
+
+/* Initialization/de-initialization functions  **********************************/
+/** @addtogroup SAI_Exported_Functions_Group1
+  * @{
+  */
+HAL_StatusTypeDef HAL_SAI_InitProtocol(SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot);
+HAL_StatusTypeDef HAL_SAI_Init(SAI_HandleTypeDef *hsai);
+HAL_StatusTypeDef HAL_SAI_DeInit(SAI_HandleTypeDef *hsai);
+void HAL_SAI_MspInit(SAI_HandleTypeDef *hsai);
+void HAL_SAI_MspDeInit(SAI_HandleTypeDef *hsai);
+
+#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
+/* SAI callbacks register/unregister functions ********************************/
+HAL_StatusTypeDef HAL_SAI_RegisterCallback(SAI_HandleTypeDef        *hsai,
+                                           HAL_SAI_CallbackIDTypeDef CallbackID,
+                                           pSAI_CallbackTypeDef      pCallback);
+HAL_StatusTypeDef HAL_SAI_UnRegisterCallback(SAI_HandleTypeDef        *hsai,
+                                             HAL_SAI_CallbackIDTypeDef CallbackID);
+#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */
+/**
+  * @}
+  */
+
+/* I/O operation functions  *****************************************************/
+/** @addtogroup SAI_Exported_Functions_Group2
+  * @{
+  */
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_SAI_Transmit(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_SAI_Receive(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_SAI_Transmit_IT(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_SAI_Receive_IT(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size);
+
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_SAI_Transmit_DMA(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_SAI_Receive_DMA(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_SAI_DMAPause(SAI_HandleTypeDef *hsai);
+HAL_StatusTypeDef HAL_SAI_DMAResume(SAI_HandleTypeDef *hsai);
+HAL_StatusTypeDef HAL_SAI_DMAStop(SAI_HandleTypeDef *hsai);
+
+/* Abort function */
+HAL_StatusTypeDef HAL_SAI_Abort(SAI_HandleTypeDef *hsai);
+
+/* Mute management */
+HAL_StatusTypeDef HAL_SAI_EnableTxMuteMode(SAI_HandleTypeDef *hsai, uint16_t val);
+HAL_StatusTypeDef HAL_SAI_DisableTxMuteMode(SAI_HandleTypeDef *hsai);
+HAL_StatusTypeDef HAL_SAI_EnableRxMuteMode(SAI_HandleTypeDef *hsai, SAIcallback callback, uint16_t counter);
+HAL_StatusTypeDef HAL_SAI_DisableRxMuteMode(SAI_HandleTypeDef *hsai);
+
+/* SAI IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */
+void HAL_SAI_IRQHandler(SAI_HandleTypeDef *hsai);
+void HAL_SAI_TxHalfCpltCallback(SAI_HandleTypeDef *hsai);
+void HAL_SAI_TxCpltCallback(SAI_HandleTypeDef *hsai);
+void HAL_SAI_RxHalfCpltCallback(SAI_HandleTypeDef *hsai);
+void HAL_SAI_RxCpltCallback(SAI_HandleTypeDef *hsai);
+void HAL_SAI_ErrorCallback(SAI_HandleTypeDef *hsai);
+/**
+  * @}
+  */
+
+/** @addtogroup SAI_Exported_Functions_Group3
+  * @{
+  */
+/* Peripheral State functions  ************************************************/
+HAL_SAI_StateTypeDef HAL_SAI_GetState(SAI_HandleTypeDef *hsai);
+uint32_t HAL_SAI_GetError(SAI_HandleTypeDef *hsai);
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @addtogroup SAI_Private_Macros
+  * @{
+  */
+#define IS_SAI_BLOCK_SYNCEXT(STATE)   (((STATE) == SAI_SYNCEXT_DISABLE)           ||\
+                                       ((STATE) == SAI_SYNCEXT_OUTBLOCKA_ENABLE)  ||\
+                                       ((STATE) == SAI_SYNCEXT_OUTBLOCKB_ENABLE))
+
+#define IS_SAI_SUPPORTED_PROTOCOL(PROTOCOL)   (((PROTOCOL) == SAI_I2S_STANDARD)     ||\
+                                               ((PROTOCOL) == SAI_I2S_MSBJUSTIFIED) ||\
+                                               ((PROTOCOL) == SAI_I2S_LSBJUSTIFIED) ||\
+                                               ((PROTOCOL) == SAI_PCM_LONG)         ||\
+                                               ((PROTOCOL) == SAI_PCM_SHORT))
+
+#define IS_SAI_PROTOCOL_DATASIZE(DATASIZE)   (((DATASIZE) == SAI_PROTOCOL_DATASIZE_16BIT)         ||\
+                                              ((DATASIZE) == SAI_PROTOCOL_DATASIZE_16BITEXTENDED) ||\
+                                              ((DATASIZE) == SAI_PROTOCOL_DATASIZE_24BIT)         ||\
+                                              ((DATASIZE) == SAI_PROTOCOL_DATASIZE_32BIT))
+
+#define IS_SAI_AUDIO_FREQUENCY(AUDIO) (((AUDIO) == SAI_AUDIO_FREQUENCY_192K) || ((AUDIO) == SAI_AUDIO_FREQUENCY_96K) || \
+                                       ((AUDIO) == SAI_AUDIO_FREQUENCY_48K)  || ((AUDIO) == SAI_AUDIO_FREQUENCY_44K) || \
+                                       ((AUDIO) == SAI_AUDIO_FREQUENCY_32K)  || ((AUDIO) == SAI_AUDIO_FREQUENCY_22K) || \
+                                       ((AUDIO) == SAI_AUDIO_FREQUENCY_16K)  || ((AUDIO) == SAI_AUDIO_FREQUENCY_11K) || \
+                                       ((AUDIO) == SAI_AUDIO_FREQUENCY_8K)   || ((AUDIO) == SAI_AUDIO_FREQUENCY_MCKDIV))
+
+#define IS_SAI_BLOCK_MODE(MODE)    (((MODE) == SAI_MODEMASTER_TX) || \
+                                    ((MODE) == SAI_MODEMASTER_RX) || \
+                                    ((MODE) == SAI_MODESLAVE_TX)  || \
+                                    ((MODE) == SAI_MODESLAVE_RX))
+
+#define IS_SAI_BLOCK_PROTOCOL(PROTOCOL) (((PROTOCOL) == SAI_FREE_PROTOCOL)  || \
+                                         ((PROTOCOL) == SAI_AC97_PROTOCOL)  || \
+                                         ((PROTOCOL) == SAI_SPDIF_PROTOCOL))
+
+#define IS_SAI_BLOCK_DATASIZE(DATASIZE) (((DATASIZE) == SAI_DATASIZE_8)  || \
+                                         ((DATASIZE) == SAI_DATASIZE_10) || \
+                                         ((DATASIZE) == SAI_DATASIZE_16) || \
+                                         ((DATASIZE) == SAI_DATASIZE_20) || \
+                                         ((DATASIZE) == SAI_DATASIZE_24) || \
+                                         ((DATASIZE) == SAI_DATASIZE_32))
+
+#define IS_SAI_BLOCK_FIRST_BIT(BIT) (((BIT) == SAI_FIRSTBIT_MSB) || \
+                                     ((BIT) == SAI_FIRSTBIT_LSB))
+
+#define IS_SAI_BLOCK_CLOCK_STROBING(CLOCK) (((CLOCK) == SAI_CLOCKSTROBING_FALLINGEDGE) || \
+                                            ((CLOCK) == SAI_CLOCKSTROBING_RISINGEDGE))
+
+#define IS_SAI_BLOCK_SYNCHRO(SYNCHRO) (((SYNCHRO) == SAI_ASYNCHRONOUS)         || \
+                                       ((SYNCHRO) == SAI_SYNCHRONOUS)          || \
+                                       ((SYNCHRO) == SAI_SYNCHRONOUS_EXT_SAI1) ||\
+                                       ((SYNCHRO) == SAI_SYNCHRONOUS_EXT_SAI2))
+
+#define IS_SAI_BLOCK_OUTPUT_DRIVE(DRIVE) (((DRIVE) == SAI_OUTPUTDRIVE_DISABLE) || \
+                                          ((DRIVE) == SAI_OUTPUTDRIVE_ENABLE))
+
+#define IS_SAI_BLOCK_NODIVIDER(NODIVIDER) (((NODIVIDER) == SAI_MASTERDIVIDER_ENABLE) || \
+                                           ((NODIVIDER) == SAI_MASTERDIVIDER_DISABLE))
+
+#define IS_SAI_BLOCK_MUTE_COUNTER(COUNTER) ((COUNTER) <= 63U)
+
+#define IS_SAI_BLOCK_MUTE_VALUE(VALUE)    (((VALUE) == SAI_ZERO_VALUE)     || \
+                                           ((VALUE) == SAI_LAST_SENT_VALUE))
+
+#define IS_SAI_BLOCK_COMPANDING_MODE(MODE)    (((MODE) == SAI_NOCOMPANDING)         || \
+                                               ((MODE) == SAI_ULAW_1CPL_COMPANDING) || \
+                                               ((MODE) == SAI_ALAW_1CPL_COMPANDING) || \
+                                               ((MODE) == SAI_ULAW_2CPL_COMPANDING) || \
+                                               ((MODE) == SAI_ALAW_2CPL_COMPANDING))
+
+#define IS_SAI_BLOCK_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == SAI_FIFOTHRESHOLD_EMPTY)   || \
+                                                ((THRESHOLD) == SAI_FIFOTHRESHOLD_1QF)     || \
+                                                ((THRESHOLD) == SAI_FIFOTHRESHOLD_HF)      || \
+                                                ((THRESHOLD) == SAI_FIFOTHRESHOLD_3QF)     || \
+                                                ((THRESHOLD) == SAI_FIFOTHRESHOLD_FULL))
+
+#define IS_SAI_BLOCK_TRISTATE_MANAGEMENT(STATE) (((STATE) == SAI_OUTPUT_NOTRELEASED) ||\
+                                                 ((STATE) == SAI_OUTPUT_RELEASED))
+
+#define IS_SAI_MONO_STEREO_MODE(MODE) (((MODE) == SAI_MONOMODE) ||\
+                                       ((MODE) == SAI_STEREOMODE))
+
+#define IS_SAI_SLOT_ACTIVE(ACTIVE)  ((ACTIVE) <= SAI_SLOTACTIVE_ALL)
+
+#define IS_SAI_BLOCK_SLOT_NUMBER(NUMBER) ((1U <= (NUMBER)) && ((NUMBER) <= 16U))
+
+#define IS_SAI_BLOCK_SLOT_SIZE(SIZE) (((SIZE) == SAI_SLOTSIZE_DATASIZE) || \
+                                      ((SIZE) == SAI_SLOTSIZE_16B)      || \
+                                      ((SIZE) == SAI_SLOTSIZE_32B))
+
+#define IS_SAI_BLOCK_FIRSTBIT_OFFSET(OFFSET) ((OFFSET) <= 24U)
+
+#define IS_SAI_BLOCK_FS_OFFSET(OFFSET) (((OFFSET) == SAI_FS_FIRSTBIT) || \
+                                        ((OFFSET) == SAI_FS_BEFOREFIRSTBIT))
+
+#define IS_SAI_BLOCK_FS_POLARITY(POLARITY) (((POLARITY) == SAI_FS_ACTIVE_LOW) || \
+                                            ((POLARITY) == SAI_FS_ACTIVE_HIGH))
+
+#define IS_SAI_BLOCK_FS_DEFINITION(DEFINITION) (((DEFINITION) == SAI_FS_STARTFRAME) || \
+                                                ((DEFINITION) == SAI_FS_CHANNEL_IDENTIFICATION))
+
+#define IS_SAI_BLOCK_MASTER_DIVIDER(DIVIDER) ((DIVIDER) <= 15U)
+
+#define IS_SAI_BLOCK_FRAME_LENGTH(LENGTH) ((8U <= (LENGTH)) && ((LENGTH) <= 256U))
+
+#define IS_SAI_BLOCK_ACTIVE_FRAME(LENGTH) ((1U <= (LENGTH)) && ((LENGTH) <= 128U))
+
+/**
+  * @}
+  */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup SAI_Private_Functions SAI Private Functions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx || STM32F413xx || STM32F423xx  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_SAI_H */
+
diff --git a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_sai_ex.h b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_sai_ex.h
new file mode 100644
index 0000000..8831e6f
--- /dev/null
+++ b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_sai_ex.h
@@ -0,0 +1,114 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hal_sai_ex.h
+  * @author  MCD Application Team
+  * @brief   Header file of SAI Extension HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_SAI_EX_H
+#define __STM32F4xx_HAL_SAI_EX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup SAIEx
+  * @{
+  */
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
+    defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F413xx) || \
+    defined(STM32F423xx)
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup SAI_Clock_Source  SAI Clock Source
+  * @{
+  */
+#if defined(STM32F413xx) || defined(STM32F423xx)
+#define SAI_CLKSOURCE_PLLI2S             0x00000000U
+#define SAI_CLKSOURCE_EXT                0x00100000U
+#define SAI_CLKSOURCE_PLLR               0x00200000U
+#define SAI_CLKSOURCE_HS                 0x00300000U
+#else
+#define SAI_CLKSOURCE_PLLSAI             0x00000000U
+#define SAI_CLKSOURCE_PLLI2S             0x00100000U
+#define SAI_CLKSOURCE_EXT                0x00200000U
+#define SAI_CLKSOURCE_NA                 0x00400000U /*!< No applicable for STM32F446xx */
+#endif
+
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup SAIEx_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup SAIEx_Exported_Functions_Group1
+  * @{
+  */
+
+/* Extended features functions ************************************************/
+void SAI_BlockSynchroConfig(SAI_HandleTypeDef *hsai);
+uint32_t SAI_GetInputClock(SAI_HandleTypeDef *hsai);
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+#if defined(STM32F413xx) || defined(STM32F423xx)
+#define IS_SAI_CLK_SOURCE(SOURCE) (((SOURCE) == SAI_CLKSOURCE_PLLI2S) ||\
+                                   ((SOURCE) == SAI_CLKSOURCE_EXT)||\
+                                   ((SOURCE) == SAI_CLKSOURCE_PLLR)||\
+                                   ((SOURCE) == SAI_CLKSOURCE_HS))
+#else
+#define IS_SAI_CLK_SOURCE(SOURCE) (((SOURCE) == SAI_CLKSOURCE_PLLSAI) ||\
+                                   ((SOURCE) == SAI_CLKSOURCE_EXT)||\
+                                   ((SOURCE) == SAI_CLKSOURCE_PLLI2S)||\
+                                   ((SOURCE) == SAI_CLKSOURCE_NA))
+#endif
+/* Private functions ---------------------------------------------------------*/
+
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx || STM32F413xx || STM32F423xx */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_SAI_EX_H */
+
diff --git a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_sd.h b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_sd.h
new file mode 100644
index 0000000..05ecc89
--- /dev/null
+++ b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_sd.h
@@ -0,0 +1,758 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hal_sd.h
+  * @author  MCD Application Team
+  * @brief   Header file of SD HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2016 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */ 
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32F4xx_HAL_SD_H
+#define STM32F4xx_HAL_SD_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if defined(SDIO)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_ll_sdmmc.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup SD SD
+  * @brief SD HAL module driver
+  * @{
+  */ 
+
+/* Exported types ------------------------------------------------------------*/ 
+/** @defgroup SD_Exported_Types SD Exported Types
+  * @{
+  */
+
+/** @defgroup SD_Exported_Types_Group1 SD State enumeration structure
+  * @{
+  */   
+typedef enum
+{
+  HAL_SD_STATE_RESET                  = 0x00000000U,  /*!< SD not yet initialized or disabled  */
+  HAL_SD_STATE_READY                  = 0x00000001U,  /*!< SD initialized and ready for use    */
+  HAL_SD_STATE_TIMEOUT                = 0x00000002U,  /*!< SD Timeout state                    */
+  HAL_SD_STATE_BUSY                   = 0x00000003U,  /*!< SD process ongoing                  */
+  HAL_SD_STATE_PROGRAMMING            = 0x00000004U,  /*!< SD Programming State                */
+  HAL_SD_STATE_RECEIVING              = 0x00000005U,  /*!< SD Receiving State                  */
+  HAL_SD_STATE_TRANSFER               = 0x00000006U,  /*!< SD Transfer State                  */
+  HAL_SD_STATE_ERROR                  = 0x0000000FU   /*!< SD is in error state                */
+}HAL_SD_StateTypeDef;
+/** 
+  * @}
+  */
+
+/** @defgroup SD_Exported_Types_Group2 SD Card State enumeration structure
+  * @{
+  */   
+typedef uint32_t HAL_SD_CardStateTypeDef;
+
+#define HAL_SD_CARD_READY          0x00000001U  /*!< Card state is ready                     */
+#define HAL_SD_CARD_IDENTIFICATION 0x00000002U  /*!< Card is in identification state         */
+#define HAL_SD_CARD_STANDBY        0x00000003U  /*!< Card is in standby state                */
+#define HAL_SD_CARD_TRANSFER       0x00000004U  /*!< Card is in transfer state               */
+#define HAL_SD_CARD_SENDING        0x00000005U  /*!< Card is sending an operation            */
+#define HAL_SD_CARD_RECEIVING      0x00000006U  /*!< Card is receiving operation information */
+#define HAL_SD_CARD_PROGRAMMING    0x00000007U  /*!< Card is in programming state            */
+#define HAL_SD_CARD_DISCONNECTED   0x00000008U  /*!< Card is disconnected                    */
+#define HAL_SD_CARD_ERROR          0x000000FFU  /*!< Card response Error                     */
+/** 
+  * @}
+  */
+
+/** @defgroup SD_Exported_Types_Group3 SD Handle Structure definition   
+  * @{
+  */
+#define SD_InitTypeDef      SDIO_InitTypeDef 
+#define SD_TypeDef          SDIO_TypeDef
+
+/** 
+  * @brief  SD Card Information Structure definition
+  */ 
+typedef struct
+{
+  uint32_t CardType;                     /*!< Specifies the card Type                         */
+  
+  uint32_t CardVersion;                  /*!< Specifies the card version                      */
+
+  uint32_t Class;                        /*!< Specifies the class of the card class           */
+
+  uint32_t RelCardAdd;                   /*!< Specifies the Relative Card Address             */
+  
+  uint32_t BlockNbr;                     /*!< Specifies the Card Capacity in blocks           */
+
+  uint32_t BlockSize;                    /*!< Specifies one block size in bytes               */
+  
+  uint32_t LogBlockNbr;                  /*!< Specifies the Card logical Capacity in blocks   */
+
+  uint32_t LogBlockSize;                 /*!< Specifies logical block size in bytes           */
+
+}HAL_SD_CardInfoTypeDef;
+
+/** 
+  * @brief  SD handle Structure definition
+  */ 
+#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
+typedef struct __SD_HandleTypeDef
+#else
+typedef struct
+#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
+{
+  SD_TypeDef                   *Instance;        /*!< SD registers base address           */
+  
+  SD_InitTypeDef               Init;             /*!< SD required parameters              */
+  
+  HAL_LockTypeDef              Lock;             /*!< SD locking object                   */
+  
+  uint8_t                      *pTxBuffPtr;      /*!< Pointer to SD Tx transfer Buffer    */
+
+  uint32_t                     TxXferSize;       /*!< SD Tx Transfer size                 */
+
+  uint8_t                      *pRxBuffPtr;      /*!< Pointer to SD Rx transfer Buffer    */
+
+  uint32_t                     RxXferSize;       /*!< SD Rx Transfer size                 */
+  
+  __IO uint32_t                Context;          /*!< SD transfer context                 */
+ 
+  __IO HAL_SD_StateTypeDef     State;            /*!< SD card State                       */
+  
+  __IO uint32_t                ErrorCode;        /*!< SD Card Error codes                 */  
+ 
+  DMA_HandleTypeDef            *hdmatx;          /*!< SD Tx DMA handle parameters         */
+
+  DMA_HandleTypeDef            *hdmarx;          /*!< SD Rx DMA handle parameters         */
+  
+  HAL_SD_CardInfoTypeDef       SdCard;           /*!< SD Card information                 */
+  
+  uint32_t                     CSD[4];           /*!< SD card specific data table         */
+  
+  uint32_t                     CID[4];           /*!< SD card identification number table */
+  
+#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
+  void (* TxCpltCallback)                 (struct __SD_HandleTypeDef *hsd);
+  void (* RxCpltCallback)                 (struct __SD_HandleTypeDef *hsd);
+  void (* ErrorCallback)                  (struct __SD_HandleTypeDef *hsd);
+  void (* AbortCpltCallback)              (struct __SD_HandleTypeDef *hsd);
+
+  void (* MspInitCallback)                (struct __SD_HandleTypeDef *hsd);
+  void (* MspDeInitCallback)              (struct __SD_HandleTypeDef *hsd);
+#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
+}SD_HandleTypeDef;
+
+/** 
+  * @}
+  */
+
+/** @defgroup SD_Exported_Types_Group4 Card Specific Data: CSD Register 
+  * @{
+  */
+typedef struct
+{
+  __IO uint8_t  CSDStruct;            /*!< CSD structure                         */
+  __IO uint8_t  SysSpecVersion;       /*!< System specification version          */
+  __IO uint8_t  Reserved1;            /*!< Reserved                              */
+  __IO uint8_t  TAAC;                 /*!< Data read access time 1               */
+  __IO uint8_t  NSAC;                 /*!< Data read access time 2 in CLK cycles */
+  __IO uint8_t  MaxBusClkFrec;        /*!< Max. bus clock frequency              */
+  __IO uint16_t CardComdClasses;      /*!< Card command classes                  */
+  __IO uint8_t  RdBlockLen;           /*!< Max. read data block length           */
+  __IO uint8_t  PartBlockRead;        /*!< Partial blocks for read allowed       */
+  __IO uint8_t  WrBlockMisalign;      /*!< Write block misalignment              */
+  __IO uint8_t  RdBlockMisalign;      /*!< Read block misalignment               */
+  __IO uint8_t  DSRImpl;              /*!< DSR implemented                       */
+  __IO uint8_t  Reserved2;            /*!< Reserved                              */
+  __IO uint32_t DeviceSize;           /*!< Device Size                           */
+  __IO uint8_t  MaxRdCurrentVDDMin;   /*!< Max. read current @ VDD min           */
+  __IO uint8_t  MaxRdCurrentVDDMax;   /*!< Max. read current @ VDD max           */
+  __IO uint8_t  MaxWrCurrentVDDMin;   /*!< Max. write current @ VDD min          */
+  __IO uint8_t  MaxWrCurrentVDDMax;   /*!< Max. write current @ VDD max          */
+  __IO uint8_t  DeviceSizeMul;        /*!< Device size multiplier                */
+  __IO uint8_t  EraseGrSize;          /*!< Erase group size                      */
+  __IO uint8_t  EraseGrMul;           /*!< Erase group size multiplier           */
+  __IO uint8_t  WrProtectGrSize;      /*!< Write protect group size              */
+  __IO uint8_t  WrProtectGrEnable;    /*!< Write protect group enable            */
+  __IO uint8_t  ManDeflECC;           /*!< Manufacturer default ECC              */
+  __IO uint8_t  WrSpeedFact;          /*!< Write speed factor                    */
+  __IO uint8_t  MaxWrBlockLen;        /*!< Max. write data block length          */
+  __IO uint8_t  WriteBlockPaPartial;  /*!< Partial blocks for write allowed      */
+  __IO uint8_t  Reserved3;            /*!< Reserved                              */
+  __IO uint8_t  ContentProtectAppli;  /*!< Content protection application        */
+  __IO uint8_t  FileFormatGroup;      /*!< File format group                     */
+  __IO uint8_t  CopyFlag;             /*!< Copy flag (OTP)                       */
+  __IO uint8_t  PermWrProtect;        /*!< Permanent write protection            */
+  __IO uint8_t  TempWrProtect;        /*!< Temporary write protection            */
+  __IO uint8_t  FileFormat;           /*!< File format                           */
+  __IO uint8_t  ECC;                  /*!< ECC code                              */
+  __IO uint8_t  CSD_CRC;              /*!< CSD CRC                               */
+  __IO uint8_t  Reserved4;            /*!< Always 1                              */
+}HAL_SD_CardCSDTypeDef;
+/** 
+  * @}
+  */
+
+/** @defgroup SD_Exported_Types_Group5 Card Identification Data: CID Register
+  * @{
+  */
+typedef struct
+{
+  __IO uint8_t  ManufacturerID;  /*!< Manufacturer ID       */
+  __IO uint16_t OEM_AppliID;     /*!< OEM/Application ID    */
+  __IO uint32_t ProdName1;       /*!< Product Name part1    */
+  __IO uint8_t  ProdName2;       /*!< Product Name part2    */
+  __IO uint8_t  ProdRev;         /*!< Product Revision      */
+  __IO uint32_t ProdSN;          /*!< Product Serial Number */
+  __IO uint8_t  Reserved1;       /*!< Reserved1             */
+  __IO uint16_t ManufactDate;    /*!< Manufacturing Date    */
+  __IO uint8_t  CID_CRC;         /*!< CID CRC               */
+  __IO uint8_t  Reserved2;       /*!< Always 1              */
+
+}HAL_SD_CardCIDTypeDef;
+/** 
+  * @}
+  */
+
+/** @defgroup SD_Exported_Types_Group6 SD Card Status returned by ACMD13 
+  * @{
+  */
+typedef struct
+{
+  __IO uint8_t  DataBusWidth;           /*!< Shows the currently defined data bus width                 */
+  __IO uint8_t  SecuredMode;            /*!< Card is in secured mode of operation                       */
+  __IO uint16_t CardType;               /*!< Carries information about card type                        */
+  __IO uint32_t ProtectedAreaSize;      /*!< Carries information about the capacity of protected area   */
+  __IO uint8_t  SpeedClass;             /*!< Carries information about the speed class of the card      */
+  __IO uint8_t  PerformanceMove;        /*!< Carries information about the card's performance move      */
+  __IO uint8_t  AllocationUnitSize;     /*!< Carries information about the card's allocation unit size  */
+  __IO uint16_t EraseSize;              /*!< Determines the number of AUs to be erased in one operation */
+  __IO uint8_t  EraseTimeout;           /*!< Determines the timeout for any number of AU erase          */
+  __IO uint8_t  EraseOffset;            /*!< Carries information about the erase offset                 */
+
+}HAL_SD_CardStatusTypeDef;
+/** 
+  * @}
+  */
+
+#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
+/** @defgroup SD_Exported_Types_Group7 SD Callback ID enumeration definition 
+  * @{
+  */
+typedef enum
+{
+  HAL_SD_TX_CPLT_CB_ID                 = 0x00U,  /*!< SD Tx Complete Callback ID                     */
+  HAL_SD_RX_CPLT_CB_ID                 = 0x01U,  /*!< SD Rx Complete Callback ID                     */
+  HAL_SD_ERROR_CB_ID                   = 0x02U,  /*!< SD Error Callback ID                           */
+  HAL_SD_ABORT_CB_ID                   = 0x03U,  /*!< SD Abort Callback ID                           */
+
+  HAL_SD_MSP_INIT_CB_ID                = 0x10U,  /*!< SD MspInit Callback ID                         */
+  HAL_SD_MSP_DEINIT_CB_ID              = 0x11U   /*!< SD MspDeInit Callback ID                       */
+}HAL_SD_CallbackIDTypeDef;
+/** 
+  * @}
+  */
+
+/** @defgroup SD_Exported_Types_Group8 SD Callback pointer definition 
+  * @{
+  */
+typedef void (*pSD_CallbackTypeDef)           (SD_HandleTypeDef *hsd);
+/** 
+  * @}
+  */
+#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
+/** 
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup SD_Exported_Constants Exported Constants
+  * @{
+  */
+
+#define BLOCKSIZE   512U /*!< Block size is 512 bytes */
+
+/** @defgroup SD_Exported_Constansts_Group1 SD Error status enumeration Structure definition 
+  * @{
+  */  
+#define HAL_SD_ERROR_NONE                     SDMMC_ERROR_NONE                    /*!< No error                                                      */
+#define HAL_SD_ERROR_CMD_CRC_FAIL             SDMMC_ERROR_CMD_CRC_FAIL            /*!< Command response received (but CRC check failed)              */
+#define HAL_SD_ERROR_DATA_CRC_FAIL            SDMMC_ERROR_DATA_CRC_FAIL           /*!< Data block sent/received (CRC check failed)                   */
+#define HAL_SD_ERROR_CMD_RSP_TIMEOUT          SDMMC_ERROR_CMD_RSP_TIMEOUT         /*!< Command response timeout                                      */
+#define HAL_SD_ERROR_DATA_TIMEOUT             SDMMC_ERROR_DATA_TIMEOUT            /*!< Data timeout                                                  */
+#define HAL_SD_ERROR_TX_UNDERRUN              SDMMC_ERROR_TX_UNDERRUN             /*!< Transmit FIFO underrun                                        */
+#define HAL_SD_ERROR_RX_OVERRUN               SDMMC_ERROR_RX_OVERRUN              /*!< Receive FIFO overrun                                          */
+#define HAL_SD_ERROR_ADDR_MISALIGNED          SDMMC_ERROR_ADDR_MISALIGNED         /*!< Misaligned address                                            */
+#define HAL_SD_ERROR_BLOCK_LEN_ERR            SDMMC_ERROR_BLOCK_LEN_ERR           /*!< Transferred block length is not allowed for the card or the 
+                                                                                       number of transferred bytes does not match the block length   */
+#define HAL_SD_ERROR_ERASE_SEQ_ERR            SDMMC_ERROR_ERASE_SEQ_ERR           /*!< An error in the sequence of erase command occurs              */
+#define HAL_SD_ERROR_BAD_ERASE_PARAM          SDMMC_ERROR_BAD_ERASE_PARAM         /*!< An invalid selection for erase groups                         */
+#define HAL_SD_ERROR_WRITE_PROT_VIOLATION     SDMMC_ERROR_WRITE_PROT_VIOLATION    /*!< Attempt to program a write protect block                      */
+#define HAL_SD_ERROR_LOCK_UNLOCK_FAILED       SDMMC_ERROR_LOCK_UNLOCK_FAILED      /*!< Sequence or password error has been detected in unlock 
+                                                                                       command or if there was an attempt to access a locked card    */
+#define HAL_SD_ERROR_COM_CRC_FAILED           SDMMC_ERROR_COM_CRC_FAILED          /*!< CRC check of the previous command failed                      */
+#define HAL_SD_ERROR_ILLEGAL_CMD              SDMMC_ERROR_ILLEGAL_CMD             /*!< Command is not legal for the card state                       */
+#define HAL_SD_ERROR_CARD_ECC_FAILED          SDMMC_ERROR_CARD_ECC_FAILED         /*!< Card internal ECC was applied but failed to correct the data  */
+#define HAL_SD_ERROR_CC_ERR                   SDMMC_ERROR_CC_ERR                  /*!< Internal card controller error                                */
+#define HAL_SD_ERROR_GENERAL_UNKNOWN_ERR      SDMMC_ERROR_GENERAL_UNKNOWN_ERR     /*!< General or unknown error                                      */
+#define HAL_SD_ERROR_STREAM_READ_UNDERRUN     SDMMC_ERROR_STREAM_READ_UNDERRUN    /*!< The card could not sustain data reading in stream rmode       */
+#define HAL_SD_ERROR_STREAM_WRITE_OVERRUN     SDMMC_ERROR_STREAM_WRITE_OVERRUN    /*!< The card could not sustain data programming in stream mode    */
+#define HAL_SD_ERROR_CID_CSD_OVERWRITE        SDMMC_ERROR_CID_CSD_OVERWRITE       /*!< CID/CSD overwrite error                                       */
+#define HAL_SD_ERROR_WP_ERASE_SKIP            SDMMC_ERROR_WP_ERASE_SKIP           /*!< Only partial address space was erased                         */
+#define HAL_SD_ERROR_CARD_ECC_DISABLED        SDMMC_ERROR_CARD_ECC_DISABLED       /*!< Command has been executed without using internal ECC          */
+#define HAL_SD_ERROR_ERASE_RESET              SDMMC_ERROR_ERASE_RESET             /*!< Erase sequence was cleared before executing because an out 
+                                                                                       of erase sequence command was received                        */
+#define HAL_SD_ERROR_AKE_SEQ_ERR              SDMMC_ERROR_AKE_SEQ_ERR             /*!< Error in sequence of authentication                           */
+#define HAL_SD_ERROR_INVALID_VOLTRANGE        SDMMC_ERROR_INVALID_VOLTRANGE       /*!< Error in case of invalid voltage range                        */        
+#define HAL_SD_ERROR_ADDR_OUT_OF_RANGE        SDMMC_ERROR_ADDR_OUT_OF_RANGE       /*!< Error when addressed block is out of range                    */        
+#define HAL_SD_ERROR_REQUEST_NOT_APPLICABLE   SDMMC_ERROR_REQUEST_NOT_APPLICABLE  /*!< Error when command request is not applicable                  */  
+#define HAL_SD_ERROR_PARAM                    SDMMC_ERROR_INVALID_PARAMETER       /*!< the used parameter is not valid                               */  
+#define HAL_SD_ERROR_UNSUPPORTED_FEATURE      SDMMC_ERROR_UNSUPPORTED_FEATURE     /*!< Error when feature is not insupported                         */
+#define HAL_SD_ERROR_BUSY                     SDMMC_ERROR_BUSY                    /*!< Error when transfer process is busy                           */ 
+#define HAL_SD_ERROR_DMA                      SDMMC_ERROR_DMA                     /*!< Error while DMA transfer                                      */
+#define HAL_SD_ERROR_TIMEOUT                  SDMMC_ERROR_TIMEOUT                 /*!< Timeout error                                                 */
+                                                
+#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
+#define HAL_SD_ERROR_INVALID_CALLBACK         SDMMC_ERROR_INVALID_PARAMETER       /*!< Invalid callback error                                        */
+#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
+/** 
+  * @}
+  */
+ 
+/** @defgroup SD_Exported_Constansts_Group2 SD context enumeration
+  * @{
+  */ 
+#define SD_CONTEXT_NONE                            0x00000000U   /*!< None                             */
+#define SD_CONTEXT_READ_SINGLE_BLOCK               0x00000001U   /*!< Read single block operation      */
+#define SD_CONTEXT_READ_MULTIPLE_BLOCK             0x00000002U   /*!< Read multiple blocks operation   */
+#define SD_CONTEXT_WRITE_SINGLE_BLOCK              0x00000010U   /*!< Write single block operation     */
+#define SD_CONTEXT_WRITE_MULTIPLE_BLOCK            0x00000020U   /*!< Write multiple blocks operation  */
+#define SD_CONTEXT_IT                              0x00000008U   /*!< Process in Interrupt mode        */
+#define SD_CONTEXT_DMA                             0x00000080U   /*!< Process in DMA mode              */
+
+/**
+  * @}
+  */
+
+/** @defgroup SD_Exported_Constansts_Group3 SD Supported Memory Cards
+  * @{
+  */
+#define CARD_SDSC                  0x00000000U  /*!< SD Standard Capacity <2Go                          */
+#define CARD_SDHC_SDXC             0x00000001U  /*!< SD High Capacity <32Go, SD Extended Capacity <2To  */
+#define CARD_SECURED               0x00000003U
+    
+/**
+  * @}
+  */
+
+/** @defgroup SD_Exported_Constansts_Group4 SD Supported Version
+  * @{
+  */
+#define CARD_V1_X                  0x00000000U
+#define CARD_V2_X                  0x00000001U
+/**
+  * @}
+  */
+      
+/**
+  * @}
+  */
+  
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup SD_Exported_macros SD Exported Macros
+ *  @brief macros to handle interrupts and specific clock configurations
+ * @{
+ */
+/** @brief Reset SD handle state.
+  * @param  __HANDLE__ : SD handle.
+  * @retval None
+  */
+#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
+#define __HAL_SD_RESET_HANDLE_STATE(__HANDLE__)           do {                                              \
+                                                               (__HANDLE__)->State = HAL_SD_STATE_RESET; \
+                                                               (__HANDLE__)->MspInitCallback = NULL;       \
+                                                               (__HANDLE__)->MspDeInitCallback = NULL;     \
+                                                             } while(0)
+#else
+#define __HAL_SD_RESET_HANDLE_STATE(__HANDLE__)           ((__HANDLE__)->State = HAL_SD_STATE_RESET)
+#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
+ 
+/**
+  * @brief  Enable the SD device.
+  * @retval None
+  */ 
+#define __HAL_SD_ENABLE(__HANDLE__) __SDIO_ENABLE((__HANDLE__)->Instance)
+
+/**
+  * @brief  Disable the SD device.
+  * @retval None
+  */
+#define __HAL_SD_DISABLE(__HANDLE__) __SDIO_DISABLE((__HANDLE__)->Instance)
+
+/**
+  * @brief  Enable the SDMMC DMA transfer.
+  * @retval None
+  */ 
+#define __HAL_SD_DMA_ENABLE(__HANDLE__) __SDIO_DMA_ENABLE((__HANDLE__)->Instance)
+
+/**
+  * @brief  Disable the SDMMC DMA transfer.
+  * @retval None
+  */
+#define __HAL_SD_DMA_DISABLE(__HANDLE__)  __SDIO_DMA_DISABLE((__HANDLE__)->Instance)
+ 
+/**
+  * @brief  Enable the SD device interrupt.
+  * @param  __HANDLE__: SD Handle  
+  * @param  __INTERRUPT__: specifies the SDMMC interrupt sources to be enabled.
+  *         This parameter can be one or a combination of the following values:
+  *            @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
+  *            @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
+  *            @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
+  *            @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
+  *            @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
+  *            @arg SDIO_IT_RXOVERR:  Received FIFO overrun error interrupt
+  *            @arg SDIO_IT_CMDREND:  Command response received (CRC check passed) interrupt
+  *            @arg SDIO_IT_CMDSENT:  Command sent (no response required) interrupt
+  *            @arg SDIO_IT_DATAEND:  Data end (data counter, DATACOUNT, is zero) interrupt
+  *            @arg SDIO_IT_DBCKEND:  Data block sent/received (CRC check passed) interrupt
+  *            @arg SDIO_IT_CMDACT:   Command transfer in progress interrupt
+  *            @arg SDIO_IT_TXACT:    Data transmit in progress interrupt
+  *            @arg SDIO_IT_RXACT:    Data receive in progress interrupt
+  *            @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
+  *            @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
+  *            @arg SDIO_IT_TXFIFOF:  Transmit FIFO full interrupt
+  *            @arg SDIO_IT_RXFIFOF:  Receive FIFO full interrupt
+  *            @arg SDIO_IT_TXFIFOE:  Transmit FIFO empty interrupt
+  *            @arg SDIO_IT_RXFIFOE:  Receive FIFO empty interrupt
+  *            @arg SDIO_IT_TXDAVL:   Data available in transmit FIFO interrupt
+  *            @arg SDIO_IT_RXDAVL:   Data available in receive FIFO interrupt
+  *            @arg SDIO_IT_SDIOIT:   SDIO interrupt received interrupt
+  * @retval None
+  */
+#define __HAL_SD_ENABLE_IT(__HANDLE__, __INTERRUPT__) __SDIO_ENABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__))
+
+/**
+  * @brief  Disable the SD device interrupt.
+  * @param  __HANDLE__: SD Handle   
+  * @param  __INTERRUPT__: specifies the SDMMC interrupt sources to be disabled.
+  *          This parameter can be one or a combination of the following values:
+  *            @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
+  *            @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
+  *            @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
+  *            @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
+  *            @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
+  *            @arg SDIO_IT_RXOVERR:  Received FIFO overrun error interrupt
+  *            @arg SDIO_IT_CMDREND:  Command response received (CRC check passed) interrupt
+  *            @arg SDIO_IT_CMDSENT:  Command sent (no response required) interrupt
+  *            @arg SDIO_IT_DATAEND:  Data end (data counter, DATACOUNT, is zero) interrupt
+  *            @arg SDIO_IT_DBCKEND:  Data block sent/received (CRC check passed) interrupt
+  *            @arg SDIO_IT_CMDACT:   Command transfer in progress interrupt
+  *            @arg SDIO_IT_TXACT:    Data transmit in progress interrupt
+  *            @arg SDIO_IT_RXACT:    Data receive in progress interrupt
+  *            @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
+  *            @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
+  *            @arg SDIO_IT_TXFIFOF:  Transmit FIFO full interrupt
+  *            @arg SDIO_IT_RXFIFOF:  Receive FIFO full interrupt
+  *            @arg SDIO_IT_TXFIFOE:  Transmit FIFO empty interrupt
+  *            @arg SDIO_IT_RXFIFOE:  Receive FIFO empty interrupt
+  *            @arg SDIO_IT_TXDAVL:   Data available in transmit FIFO interrupt
+  *            @arg SDIO_IT_RXDAVL:   Data available in receive FIFO interrupt
+  *            @arg SDIO_IT_SDIOIT:   SDIO interrupt received interrupt   
+  * @retval None
+  */
+#define __HAL_SD_DISABLE_IT(__HANDLE__, __INTERRUPT__) __SDIO_DISABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__))
+
+/**
+  * @brief  Check whether the specified SD flag is set or not. 
+  * @param  __HANDLE__: SD Handle   
+  * @param  __FLAG__: specifies the flag to check. 
+  *          This parameter can be one of the following values:
+  *            @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)
+  *            @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
+  *            @arg SDIO_FLAG_CTIMEOUT: Command response timeout
+  *            @arg SDIO_FLAG_DTIMEOUT: Data timeout
+  *            @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error
+  *            @arg SDIO_FLAG_RXOVERR:  Received FIFO overrun error
+  *            @arg SDIO_FLAG_CMDREND:  Command response received (CRC check passed)
+  *            @arg SDIO_FLAG_CMDSENT:  Command sent (no response required)
+  *            @arg SDIO_FLAG_DATAEND:  Data end (data counter, DATACOUNT, is zero)
+  *            @arg SDIO_FLAG_DBCKEND:  Data block sent/received (CRC check passed)
+  *            @arg SDIO_FLAG_CMDACT:   Command transfer in progress
+  *            @arg SDIO_FLAG_TXACT:    Data transmit in progress
+  *            @arg SDIO_FLAG_RXACT:    Data receive in progress
+  *            @arg SDIO_FLAG_TXFIFOHE: Transmit FIFO Half Empty
+  *            @arg SDIO_FLAG_RXFIFOHF: Receive FIFO Half Full
+  *            @arg SDIO_FLAG_TXFIFOF:  Transmit FIFO full
+  *            @arg SDIO_FLAG_RXFIFOF:  Receive FIFO full
+  *            @arg SDIO_FLAG_TXFIFOE:  Transmit FIFO empty
+  *            @arg SDIO_FLAG_RXFIFOE:  Receive FIFO empty
+  *            @arg SDIO_FLAG_TXDAVL:   Data available in transmit FIFO
+  *            @arg SDIO_FLAG_RXDAVL:   Data available in receive FIFO
+  *            @arg SDIO_FLAG_SDIOIT:   SDIO interrupt received
+  * @retval The new state of SD FLAG (SET or RESET).
+  */
+#define __HAL_SD_GET_FLAG(__HANDLE__, __FLAG__) __SDIO_GET_FLAG((__HANDLE__)->Instance, (__FLAG__))
+
+/**
+  * @brief  Clear the SD's pending flags.
+  * @param  __HANDLE__: SD Handle  
+  * @param  __FLAG__: specifies the flag to clear.  
+  *          This parameter can be one or a combination of the following values:
+  *            @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)
+  *            @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
+  *            @arg SDIO_FLAG_CTIMEOUT: Command response timeout
+  *            @arg SDIO_FLAG_DTIMEOUT: Data timeout
+  *            @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error
+  *            @arg SDIO_FLAG_RXOVERR:  Received FIFO overrun error
+  *            @arg SDIO_FLAG_CMDREND:  Command response received (CRC check passed)
+  *            @arg SDIO_FLAG_CMDSENT:  Command sent (no response required)
+  *            @arg SDIO_FLAG_DATAEND:  Data end (data counter, DATACOUNT, is zero)
+  *            @arg SDIO_FLAG_DBCKEND:  Data block sent/received (CRC check passed)
+  *            @arg SDIO_FLAG_SDIOIT:   SDIO interrupt received
+  * @retval None
+  */
+#define __HAL_SD_CLEAR_FLAG(__HANDLE__, __FLAG__) __SDIO_CLEAR_FLAG((__HANDLE__)->Instance, (__FLAG__))
+
+/**
+  * @brief  Check whether the specified SD interrupt has occurred or not.
+  * @param  __HANDLE__: SD Handle   
+  * @param  __INTERRUPT__: specifies the SDMMC interrupt source to check. 
+  *          This parameter can be one of the following values:
+  *            @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
+  *            @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
+  *            @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
+  *            @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
+  *            @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
+  *            @arg SDIO_IT_RXOVERR:  Received FIFO overrun error interrupt
+  *            @arg SDIO_IT_CMDREND:  Command response received (CRC check passed) interrupt
+  *            @arg SDIO_IT_CMDSENT:  Command sent (no response required) interrupt
+  *            @arg SDIO_IT_DATAEND:  Data end (data counter, DATACOUNT, is zero) interrupt
+  *            @arg SDIO_IT_DBCKEND:  Data block sent/received (CRC check passed) interrupt
+  *            @arg SDIO_IT_CMDACT:   Command transfer in progress interrupt
+  *            @arg SDIO_IT_TXACT:    Data transmit in progress interrupt
+  *            @arg SDIO_IT_RXACT:    Data receive in progress interrupt
+  *            @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
+  *            @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
+  *            @arg SDIO_IT_TXFIFOF:  Transmit FIFO full interrupt
+  *            @arg SDIO_IT_RXFIFOF:  Receive FIFO full interrupt
+  *            @arg SDIO_IT_TXFIFOE:  Transmit FIFO empty interrupt
+  *            @arg SDIO_IT_RXFIFOE:  Receive FIFO empty interrupt
+  *            @arg SDIO_IT_TXDAVL:   Data available in transmit FIFO interrupt
+  *            @arg SDIO_IT_RXDAVL:   Data available in receive FIFO interrupt
+  *            @arg SDIO_IT_SDIOIT:   SDIO interrupt received interrupt
+  * @retval The new state of SD IT (SET or RESET).
+  */
+#define __HAL_SD_GET_IT(__HANDLE__, __INTERRUPT__) __SDIO_GET_IT((__HANDLE__)->Instance, (__INTERRUPT__))
+
+/**
+  * @brief  Clear the SD's interrupt pending bits.
+  * @param  __HANDLE__: SD Handle
+  * @param  __INTERRUPT__: specifies the interrupt pending bit to clear. 
+  *          This parameter can be one or a combination of the following values:
+  *            @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
+  *            @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
+  *            @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
+  *            @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
+  *            @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
+  *            @arg SDIO_IT_RXOVERR:  Received FIFO overrun error interrupt
+  *            @arg SDIO_IT_CMDREND:  Command response received (CRC check passed) interrupt
+  *            @arg SDIO_IT_CMDSENT:  Command sent (no response required) interrupt
+  *            @arg SDIO_IT_DATAEND:  Data end (data counter, DATACOUNT, is zero) interrupt
+  *            @arg SDIO_IT_SDIOIT:   SDIO interrupt received interrupt
+  * @retval None
+  */
+#define __HAL_SD_CLEAR_IT(__HANDLE__, __INTERRUPT__) __SDIO_CLEAR_IT((__HANDLE__)->Instance, (__INTERRUPT__))
+
+/**
+  * @}
+  */
+  
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup SD_Exported_Functions SD Exported Functions
+  * @{
+  */
+  
+/** @defgroup SD_Exported_Functions_Group1 Initialization and de-initialization functions
+  * @{
+  */
+HAL_StatusTypeDef HAL_SD_Init(SD_HandleTypeDef *hsd);
+HAL_StatusTypeDef HAL_SD_InitCard(SD_HandleTypeDef *hsd);
+HAL_StatusTypeDef HAL_SD_DeInit (SD_HandleTypeDef *hsd);
+void HAL_SD_MspInit(SD_HandleTypeDef *hsd);
+void HAL_SD_MspDeInit(SD_HandleTypeDef *hsd);
+/**
+  * @}
+  */
+  
+/** @defgroup SD_Exported_Functions_Group2 Input and Output operation functions
+  * @{
+  */
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout);
+HAL_StatusTypeDef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout);
+HAL_StatusTypeDef HAL_SD_Erase(SD_HandleTypeDef *hsd, uint32_t BlockStartAdd, uint32_t BlockEndAdd);
+/* Non-Blocking mode: IT */
+HAL_StatusTypeDef HAL_SD_ReadBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks);
+HAL_StatusTypeDef HAL_SD_WriteBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks);
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_SD_ReadBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks);
+HAL_StatusTypeDef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks);
+
+void HAL_SD_IRQHandler(SD_HandleTypeDef *hsd);
+
+/* Callback in non blocking modes (DMA) */
+void HAL_SD_TxCpltCallback(SD_HandleTypeDef *hsd);
+void HAL_SD_RxCpltCallback(SD_HandleTypeDef *hsd);
+void HAL_SD_ErrorCallback(SD_HandleTypeDef *hsd);
+void HAL_SD_AbortCallback(SD_HandleTypeDef *hsd);
+
+#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
+/* SD callback registering/unregistering */
+HAL_StatusTypeDef HAL_SD_RegisterCallback  (SD_HandleTypeDef *hsd, HAL_SD_CallbackIDTypeDef CallbackId, pSD_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_SD_UnRegisterCallback(SD_HandleTypeDef *hsd, HAL_SD_CallbackIDTypeDef CallbackId);
+#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+  
+/** @defgroup SD_Exported_Functions_Group3 Peripheral Control functions
+  * @{
+  */
+HAL_StatusTypeDef HAL_SD_ConfigWideBusOperation(SD_HandleTypeDef *hsd, uint32_t WideMode);
+/**
+  * @}
+  */
+
+/** @defgroup SD_Exported_Functions_Group4 SD card related functions
+  * @{
+  */
+HAL_StatusTypeDef       HAL_SD_SendSDStatus(SD_HandleTypeDef *hsd, uint32_t *pSDstatus);
+HAL_SD_CardStateTypeDef HAL_SD_GetCardState(SD_HandleTypeDef *hsd);
+HAL_StatusTypeDef       HAL_SD_GetCardCID(SD_HandleTypeDef *hsd, HAL_SD_CardCIDTypeDef *pCID);
+HAL_StatusTypeDef       HAL_SD_GetCardCSD(SD_HandleTypeDef *hsd, HAL_SD_CardCSDTypeDef *pCSD);
+HAL_StatusTypeDef       HAL_SD_GetCardStatus(SD_HandleTypeDef *hsd, HAL_SD_CardStatusTypeDef *pStatus);
+HAL_StatusTypeDef       HAL_SD_GetCardInfo(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypeDef *pCardInfo);
+/**
+  * @}
+  */
+
+/** @defgroup SD_Exported_Functions_Group5 Peripheral State and Errors functions
+  * @{
+  */
+HAL_SD_StateTypeDef HAL_SD_GetState(SD_HandleTypeDef *hsd);
+uint32_t HAL_SD_GetError(SD_HandleTypeDef *hsd);
+/**
+  * @}
+  */
+
+/** @defgroup SD_Exported_Functions_Group6 Perioheral Abort management
+  * @{
+  */
+HAL_StatusTypeDef HAL_SD_Abort(SD_HandleTypeDef *hsd);
+HAL_StatusTypeDef HAL_SD_Abort_IT(SD_HandleTypeDef *hsd);
+/**
+  * @}
+  */
+    
+/* Private types -------------------------------------------------------------*/
+/** @defgroup SD_Private_Types SD Private Types
+  * @{
+  */
+
+/**
+  * @}
+  */ 
+
+/* Private defines -----------------------------------------------------------*/
+/** @defgroup SD_Private_Defines SD Private Defines
+  * @{
+  */
+
+/**
+  * @}
+  */ 
+          
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup SD_Private_Variables SD Private Variables
+  * @{
+  */
+
+/**
+  * @}
+  */ 
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup SD_Private_Constants SD Private Constants
+  * @{
+  */
+
+/**
+  * @}
+  */ 
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup SD_Private_Macros SD Private Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Private functions prototypes ----------------------------------------------*/
+/** @defgroup SD_Private_Functions_Prototypes SD Private Functions Prototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup SD_Private_Functions SD Private Functions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* SDIO */
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* STM32F4xx_HAL_SD_H */ 
diff --git a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_sdram.h b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_sdram.h
new file mode 100644
index 0000000..1cfc229
--- /dev/null
+++ b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_sdram.h
@@ -0,0 +1,238 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hal_sdram.h
+  * @author  MCD Application Team
+  * @brief   Header file of SDRAM HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2016 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32F4xx_HAL_SDRAM_H
+#define STM32F4xx_HAL_SDRAM_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if defined(FMC_Bank5_6)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_ll_fmc.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup SDRAM
+  * @{
+  */
+
+/* Exported typedef ----------------------------------------------------------*/
+
+/** @defgroup SDRAM_Exported_Types SDRAM Exported Types
+  * @{
+  */
+
+/**
+  * @brief  HAL SDRAM State structure definition
+  */
+typedef enum
+{
+  HAL_SDRAM_STATE_RESET             = 0x00U,  /*!< SDRAM not yet initialized or disabled */
+  HAL_SDRAM_STATE_READY             = 0x01U,  /*!< SDRAM initialized and ready for use   */
+  HAL_SDRAM_STATE_BUSY              = 0x02U,  /*!< SDRAM internal process is ongoing     */
+  HAL_SDRAM_STATE_ERROR             = 0x03U,  /*!< SDRAM error state                     */
+  HAL_SDRAM_STATE_WRITE_PROTECTED   = 0x04U,  /*!< SDRAM device write protected          */
+  HAL_SDRAM_STATE_PRECHARGED        = 0x05U   /*!< SDRAM device precharged               */
+
+} HAL_SDRAM_StateTypeDef;
+
+/**
+  * @brief  SDRAM handle Structure definition
+  */
+#if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1)
+typedef struct __SDRAM_HandleTypeDef
+#else
+typedef struct
+#endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS  */
+{
+  FMC_SDRAM_TypeDef             *Instance;  /*!< Register base address                 */
+
+  FMC_SDRAM_InitTypeDef         Init;       /*!< SDRAM device configuration parameters */
+
+  __IO HAL_SDRAM_StateTypeDef   State;      /*!< SDRAM access state                    */
+
+  HAL_LockTypeDef               Lock;       /*!< SDRAM locking object                  */
+
+  DMA_HandleTypeDef             *hdma;      /*!< Pointer DMA handler                   */
+
+#if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1)
+  void (* MspInitCallback)(struct __SDRAM_HandleTypeDef *hsdram);               /*!< SDRAM Msp Init callback              */
+  void (* MspDeInitCallback)(struct __SDRAM_HandleTypeDef *hsdram);             /*!< SDRAM Msp DeInit callback            */
+  void (* RefreshErrorCallback)(struct __SDRAM_HandleTypeDef *hsdram);          /*!< SDRAM Refresh Error callback         */
+  void (* DmaXferCpltCallback)(DMA_HandleTypeDef *hdma);                        /*!< SDRAM DMA Xfer Complete callback     */
+  void (* DmaXferErrorCallback)(DMA_HandleTypeDef *hdma);                       /*!< SDRAM DMA Xfer Error callback        */
+#endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */
+} SDRAM_HandleTypeDef;
+
+#if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1)
+/**
+  * @brief  HAL SDRAM Callback ID enumeration definition
+  */
+typedef enum
+{
+  HAL_SDRAM_MSP_INIT_CB_ID       = 0x00U,  /*!< SDRAM MspInit Callback ID           */
+  HAL_SDRAM_MSP_DEINIT_CB_ID     = 0x01U,  /*!< SDRAM MspDeInit Callback ID         */
+  HAL_SDRAM_REFRESH_ERR_CB_ID    = 0x02U,  /*!< SDRAM Refresh Error Callback ID     */
+  HAL_SDRAM_DMA_XFER_CPLT_CB_ID  = 0x03U,  /*!< SDRAM DMA Xfer Complete Callback ID */
+  HAL_SDRAM_DMA_XFER_ERR_CB_ID   = 0x04U   /*!< SDRAM DMA Xfer Error Callback ID    */
+} HAL_SDRAM_CallbackIDTypeDef;
+
+/**
+  * @brief  HAL SDRAM Callback pointer definition
+  */
+typedef void (*pSDRAM_CallbackTypeDef)(SDRAM_HandleTypeDef *hsdram);
+typedef void (*pSDRAM_DmaCallbackTypeDef)(DMA_HandleTypeDef *hdma);
+#endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+
+/** @defgroup SDRAM_Exported_Macros SDRAM Exported Macros
+  * @{
+  */
+
+/** @brief Reset SDRAM handle state
+  * @param  __HANDLE__ specifies the SDRAM handle.
+  * @retval None
+  */
+#if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1)
+#define __HAL_SDRAM_RESET_HANDLE_STATE(__HANDLE__)        do {                                               \
+                                                               (__HANDLE__)->State = HAL_SDRAM_STATE_RESET;  \
+                                                               (__HANDLE__)->MspInitCallback = NULL;         \
+                                                               (__HANDLE__)->MspDeInitCallback = NULL;       \
+                                                             } while(0)
+#else
+#define __HAL_SDRAM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SDRAM_STATE_RESET)
+#endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @addtogroup SDRAM_Exported_Functions SDRAM Exported Functions
+  * @{
+  */
+
+/** @addtogroup SDRAM_Exported_Functions_Group1
+  * @{
+  */
+
+/* Initialization/de-initialization functions *********************************/
+HAL_StatusTypeDef HAL_SDRAM_Init(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_TimingTypeDef *Timing);
+HAL_StatusTypeDef HAL_SDRAM_DeInit(SDRAM_HandleTypeDef *hsdram);
+void HAL_SDRAM_MspInit(SDRAM_HandleTypeDef *hsdram);
+void HAL_SDRAM_MspDeInit(SDRAM_HandleTypeDef *hsdram);
+
+void HAL_SDRAM_IRQHandler(SDRAM_HandleTypeDef *hsdram);
+void HAL_SDRAM_RefreshErrorCallback(SDRAM_HandleTypeDef *hsdram);
+void HAL_SDRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma);
+void HAL_SDRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma);
+
+/**
+  * @}
+  */
+
+/** @addtogroup SDRAM_Exported_Functions_Group2
+  * @{
+  */
+/* I/O operation functions ****************************************************/
+HAL_StatusTypeDef HAL_SDRAM_Read_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pDstBuffer,
+                                    uint32_t BufferSize);
+HAL_StatusTypeDef HAL_SDRAM_Write_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pSrcBuffer,
+                                     uint32_t BufferSize);
+HAL_StatusTypeDef HAL_SDRAM_Read_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pDstBuffer,
+                                     uint32_t BufferSize);
+HAL_StatusTypeDef HAL_SDRAM_Write_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pSrcBuffer,
+                                      uint32_t BufferSize);
+HAL_StatusTypeDef HAL_SDRAM_Read_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pDstBuffer,
+                                     uint32_t BufferSize);
+HAL_StatusTypeDef HAL_SDRAM_Write_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer,
+                                      uint32_t BufferSize);
+
+HAL_StatusTypeDef HAL_SDRAM_Read_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pDstBuffer,
+                                     uint32_t BufferSize);
+HAL_StatusTypeDef HAL_SDRAM_Write_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer,
+                                      uint32_t BufferSize);
+
+#if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1)
+/* SDRAM callback registering/unregistering */
+HAL_StatusTypeDef HAL_SDRAM_RegisterCallback(SDRAM_HandleTypeDef *hsdram, HAL_SDRAM_CallbackIDTypeDef CallbackId,
+                                             pSDRAM_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_SDRAM_UnRegisterCallback(SDRAM_HandleTypeDef *hsdram, HAL_SDRAM_CallbackIDTypeDef CallbackId);
+HAL_StatusTypeDef HAL_SDRAM_RegisterDmaCallback(SDRAM_HandleTypeDef *hsdram, HAL_SDRAM_CallbackIDTypeDef CallbackId,
+                                                pSDRAM_DmaCallbackTypeDef pCallback);
+#endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+
+/** @addtogroup SDRAM_Exported_Functions_Group3
+  * @{
+  */
+/* SDRAM Control functions  *****************************************************/
+HAL_StatusTypeDef HAL_SDRAM_WriteProtection_Enable(SDRAM_HandleTypeDef *hsdram);
+HAL_StatusTypeDef HAL_SDRAM_WriteProtection_Disable(SDRAM_HandleTypeDef *hsdram);
+HAL_StatusTypeDef HAL_SDRAM_SendCommand(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_CommandTypeDef *Command,
+                                        uint32_t Timeout);
+HAL_StatusTypeDef HAL_SDRAM_ProgramRefreshRate(SDRAM_HandleTypeDef *hsdram, uint32_t RefreshRate);
+HAL_StatusTypeDef HAL_SDRAM_SetAutoRefreshNumber(SDRAM_HandleTypeDef *hsdram, uint32_t AutoRefreshNumber);
+uint32_t          HAL_SDRAM_GetModeStatus(SDRAM_HandleTypeDef *hsdram);
+
+/**
+  * @}
+  */
+
+/** @addtogroup SDRAM_Exported_Functions_Group4
+  * @{
+  */
+/* SDRAM State functions ********************************************************/
+HAL_SDRAM_StateTypeDef  HAL_SDRAM_GetState(SDRAM_HandleTypeDef *hsdram);
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* FMC_Bank5_6 */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32F4xx_HAL_SDRAM_H */
diff --git a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h
new file mode 100644
index 0000000..e3cc450
--- /dev/null
+++ b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h
@@ -0,0 +1,2146 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hal_tim.h
+  * @author  MCD Application Team
+  * @brief   Header file of TIM HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2016 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32F4xx_HAL_TIM_H
+#define STM32F4xx_HAL_TIM_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup TIM
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup TIM_Exported_Types TIM Exported Types
+  * @{
+  */
+
+/**
+  * @brief  TIM Time base Configuration Structure definition
+  */
+typedef struct
+{
+  uint32_t Prescaler;         /*!< Specifies the prescaler value used to divide the TIM clock.
+                                   This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
+
+  uint32_t CounterMode;       /*!< Specifies the counter mode.
+                                   This parameter can be a value of @ref TIM_Counter_Mode */
+
+  uint32_t Period;            /*!< Specifies the period value to be loaded into the active
+                                   Auto-Reload Register at the next update event.
+                                   This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF.  */
+
+  uint32_t ClockDivision;     /*!< Specifies the clock division.
+                                   This parameter can be a value of @ref TIM_ClockDivision */
+
+  uint32_t RepetitionCounter;  /*!< Specifies the repetition counter value. Each time the RCR downcounter
+                                    reaches zero, an update event is generated and counting restarts
+                                    from the RCR value (N).
+                                    This means in PWM mode that (N+1) corresponds to:
+                                        - the number of PWM periods in edge-aligned mode
+                                        - the number of half PWM period in center-aligned mode
+                                     GP timers: this parameter must be a number between Min_Data = 0x00 and
+                                     Max_Data = 0xFF.
+                                     Advanced timers: this parameter must be a number between Min_Data = 0x0000 and
+                                     Max_Data = 0xFFFF. */
+
+  uint32_t AutoReloadPreload;  /*!< Specifies the auto-reload preload.
+                                   This parameter can be a value of @ref TIM_AutoReloadPreload */
+} TIM_Base_InitTypeDef;
+
+/**
+  * @brief  TIM Output Compare Configuration Structure definition
+  */
+typedef struct
+{
+  uint32_t OCMode;        /*!< Specifies the TIM mode.
+                               This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
+
+  uint32_t Pulse;         /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
+                               This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
+
+  uint32_t OCPolarity;    /*!< Specifies the output polarity.
+                               This parameter can be a value of @ref TIM_Output_Compare_Polarity */
+
+  uint32_t OCNPolarity;   /*!< Specifies the complementary output polarity.
+                               This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
+                               @note This parameter is valid only for timer instances supporting break feature. */
+
+  uint32_t OCFastMode;    /*!< Specifies the Fast mode state.
+                               This parameter can be a value of @ref TIM_Output_Fast_State
+                               @note This parameter is valid only in PWM1 and PWM2 mode. */
+
+
+  uint32_t OCIdleState;   /*!< Specifies the TIM Output Compare pin state during Idle state.
+                               This parameter can be a value of @ref TIM_Output_Compare_Idle_State
+                               @note This parameter is valid only for timer instances supporting break feature. */
+
+  uint32_t OCNIdleState;  /*!< Specifies the TIM Output Compare pin state during Idle state.
+                               This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
+                               @note This parameter is valid only for timer instances supporting break feature. */
+} TIM_OC_InitTypeDef;
+
+/**
+  * @brief  TIM One Pulse Mode Configuration Structure definition
+  */
+typedef struct
+{
+  uint32_t OCMode;        /*!< Specifies the TIM mode.
+                               This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
+
+  uint32_t Pulse;         /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
+                               This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
+
+  uint32_t OCPolarity;    /*!< Specifies the output polarity.
+                               This parameter can be a value of @ref TIM_Output_Compare_Polarity */
+
+  uint32_t OCNPolarity;   /*!< Specifies the complementary output polarity.
+                               This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
+                               @note This parameter is valid only for timer instances supporting break feature. */
+
+  uint32_t OCIdleState;   /*!< Specifies the TIM Output Compare pin state during Idle state.
+                               This parameter can be a value of @ref TIM_Output_Compare_Idle_State
+                               @note This parameter is valid only for timer instances supporting break feature. */
+
+  uint32_t OCNIdleState;  /*!< Specifies the TIM Output Compare pin state during Idle state.
+                               This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
+                               @note This parameter is valid only for timer instances supporting break feature. */
+
+  uint32_t ICPolarity;    /*!< Specifies the active edge of the input signal.
+                               This parameter can be a value of @ref TIM_Input_Capture_Polarity */
+
+  uint32_t ICSelection;   /*!< Specifies the input.
+                              This parameter can be a value of @ref TIM_Input_Capture_Selection */
+
+  uint32_t ICFilter;      /*!< Specifies the input capture filter.
+                              This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
+} TIM_OnePulse_InitTypeDef;
+
+/**
+  * @brief  TIM Input Capture Configuration Structure definition
+  */
+typedef struct
+{
+  uint32_t  ICPolarity;  /*!< Specifies the active edge of the input signal.
+                              This parameter can be a value of @ref TIM_Input_Capture_Polarity */
+
+  uint32_t ICSelection;  /*!< Specifies the input.
+                              This parameter can be a value of @ref TIM_Input_Capture_Selection */
+
+  uint32_t ICPrescaler;  /*!< Specifies the Input Capture Prescaler.
+                              This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
+
+  uint32_t ICFilter;     /*!< Specifies the input capture filter.
+                              This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
+} TIM_IC_InitTypeDef;
+
+/**
+  * @brief  TIM Encoder Configuration Structure definition
+  */
+typedef struct
+{
+  uint32_t EncoderMode;   /*!< Specifies the active edge of the input signal.
+                               This parameter can be a value of @ref TIM_Encoder_Mode */
+
+  uint32_t IC1Polarity;   /*!< Specifies the active edge of the input signal.
+                               This parameter can be a value of @ref TIM_Encoder_Input_Polarity */
+
+  uint32_t IC1Selection;  /*!< Specifies the input.
+                               This parameter can be a value of @ref TIM_Input_Capture_Selection */
+
+  uint32_t IC1Prescaler;  /*!< Specifies the Input Capture Prescaler.
+                               This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
+
+  uint32_t IC1Filter;     /*!< Specifies the input capture filter.
+                               This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
+
+  uint32_t IC2Polarity;   /*!< Specifies the active edge of the input signal.
+                               This parameter can be a value of @ref TIM_Encoder_Input_Polarity */
+
+  uint32_t IC2Selection;  /*!< Specifies the input.
+                              This parameter can be a value of @ref TIM_Input_Capture_Selection */
+
+  uint32_t IC2Prescaler;  /*!< Specifies the Input Capture Prescaler.
+                               This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
+
+  uint32_t IC2Filter;     /*!< Specifies the input capture filter.
+                               This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
+} TIM_Encoder_InitTypeDef;
+
+/**
+  * @brief  Clock Configuration Handle Structure definition
+  */
+typedef struct
+{
+  uint32_t ClockSource;     /*!< TIM clock sources
+                                 This parameter can be a value of @ref TIM_Clock_Source */
+  uint32_t ClockPolarity;   /*!< TIM clock polarity
+                                 This parameter can be a value of @ref TIM_Clock_Polarity */
+  uint32_t ClockPrescaler;  /*!< TIM clock prescaler
+                                 This parameter can be a value of @ref TIM_Clock_Prescaler */
+  uint32_t ClockFilter;     /*!< TIM clock filter
+                                 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
+} TIM_ClockConfigTypeDef;
+
+/**
+  * @brief  TIM Clear Input Configuration Handle Structure definition
+  */
+typedef struct
+{
+  uint32_t ClearInputState;      /*!< TIM clear Input state
+                                      This parameter can be ENABLE or DISABLE */
+  uint32_t ClearInputSource;     /*!< TIM clear Input sources
+                                      This parameter can be a value of @ref TIM_ClearInput_Source */
+  uint32_t ClearInputPolarity;   /*!< TIM Clear Input polarity
+                                      This parameter can be a value of @ref TIM_ClearInput_Polarity */
+  uint32_t ClearInputPrescaler;  /*!< TIM Clear Input prescaler
+                                      This parameter must be 0: When OCRef clear feature is used with ETR source,
+                                      ETR prescaler must be off */
+  uint32_t ClearInputFilter;     /*!< TIM Clear Input filter
+                                      This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
+} TIM_ClearInputConfigTypeDef;
+
+/**
+  * @brief  TIM Master configuration Structure definition
+  */
+typedef struct
+{
+  uint32_t  MasterOutputTrigger;   /*!< Trigger output (TRGO) selection
+                                        This parameter can be a value of @ref TIM_Master_Mode_Selection */
+  uint32_t  MasterSlaveMode;       /*!< Master/slave mode selection
+                                        This parameter can be a value of @ref TIM_Master_Slave_Mode
+                                        @note When the Master/slave mode is enabled, the effect of
+                                        an event on the trigger input (TRGI) is delayed to allow a
+                                        perfect synchronization between the current timer and its
+                                        slaves (through TRGO). It is not mandatory in case of timer
+                                        synchronization mode. */
+} TIM_MasterConfigTypeDef;
+
+/**
+  * @brief  TIM Slave configuration Structure definition
+  */
+typedef struct
+{
+  uint32_t  SlaveMode;         /*!< Slave mode selection
+                                    This parameter can be a value of @ref TIM_Slave_Mode */
+  uint32_t  InputTrigger;      /*!< Input Trigger source
+                                    This parameter can be a value of @ref TIM_Trigger_Selection */
+  uint32_t  TriggerPolarity;   /*!< Input Trigger polarity
+                                    This parameter can be a value of @ref TIM_Trigger_Polarity */
+  uint32_t  TriggerPrescaler;  /*!< Input trigger prescaler
+                                    This parameter can be a value of @ref TIM_Trigger_Prescaler */
+  uint32_t  TriggerFilter;     /*!< Input trigger filter
+                                    This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF  */
+
+} TIM_SlaveConfigTypeDef;
+
+/**
+  * @brief  TIM Break input(s) and Dead time configuration Structure definition
+  * @note   2 break inputs can be configured (BKIN and BKIN2) with configurable
+  *        filter and polarity.
+  */
+typedef struct
+{
+  uint32_t OffStateRunMode;      /*!< TIM off state in run mode, This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */
+
+  uint32_t OffStateIDLEMode;     /*!< TIM off state in IDLE mode, This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */
+
+  uint32_t LockLevel;            /*!< TIM Lock level, This parameter can be a value of @ref TIM_Lock_level */
+
+  uint32_t DeadTime;             /*!< TIM dead Time, This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF */
+
+  uint32_t BreakState;           /*!< TIM Break State, This parameter can be a value of @ref TIM_Break_Input_enable_disable */
+
+  uint32_t BreakPolarity;        /*!< TIM Break input polarity, This parameter can be a value of @ref TIM_Break_Polarity */
+
+  uint32_t BreakFilter;          /*!< Specifies the break input filter.This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
+
+  uint32_t AutomaticOutput;      /*!< TIM Automatic Output Enable state, This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */
+
+} TIM_BreakDeadTimeConfigTypeDef;
+
+/**
+  * @brief  HAL State structures definition
+  */
+typedef enum
+{
+  HAL_TIM_STATE_RESET             = 0x00U,    /*!< Peripheral not yet initialized or disabled  */
+  HAL_TIM_STATE_READY             = 0x01U,    /*!< Peripheral Initialized and ready for use    */
+  HAL_TIM_STATE_BUSY              = 0x02U,    /*!< An internal process is ongoing              */
+  HAL_TIM_STATE_TIMEOUT           = 0x03U,    /*!< Timeout state                               */
+  HAL_TIM_STATE_ERROR             = 0x04U     /*!< Reception process is ongoing                */
+} HAL_TIM_StateTypeDef;
+
+/**
+  * @brief  TIM Channel States definition
+  */
+typedef enum
+{
+  HAL_TIM_CHANNEL_STATE_RESET             = 0x00U,    /*!< TIM Channel initial state                         */
+  HAL_TIM_CHANNEL_STATE_READY             = 0x01U,    /*!< TIM Channel ready for use                         */
+  HAL_TIM_CHANNEL_STATE_BUSY              = 0x02U,    /*!< An internal process is ongoing on the TIM channel */
+} HAL_TIM_ChannelStateTypeDef;
+
+/**
+  * @brief  DMA Burst States definition
+  */
+typedef enum
+{
+  HAL_DMA_BURST_STATE_RESET             = 0x00U,    /*!< DMA Burst initial state */
+  HAL_DMA_BURST_STATE_READY             = 0x01U,    /*!< DMA Burst ready for use */
+  HAL_DMA_BURST_STATE_BUSY              = 0x02U,    /*!< Ongoing DMA Burst       */
+} HAL_TIM_DMABurstStateTypeDef;
+
+/**
+  * @brief  HAL Active channel structures definition
+  */
+typedef enum
+{
+  HAL_TIM_ACTIVE_CHANNEL_1        = 0x01U,    /*!< The active channel is 1     */
+  HAL_TIM_ACTIVE_CHANNEL_2        = 0x02U,    /*!< The active channel is 2     */
+  HAL_TIM_ACTIVE_CHANNEL_3        = 0x04U,    /*!< The active channel is 3     */
+  HAL_TIM_ACTIVE_CHANNEL_4        = 0x08U,    /*!< The active channel is 4     */
+  HAL_TIM_ACTIVE_CHANNEL_CLEARED  = 0x00U     /*!< All active channels cleared */
+} HAL_TIM_ActiveChannel;
+
+/**
+  * @brief  TIM Time Base Handle Structure definition
+  */
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+typedef struct __TIM_HandleTypeDef
+#else
+typedef struct
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+{
+  TIM_TypeDef                        *Instance;         /*!< Register base address                             */
+  TIM_Base_InitTypeDef               Init;              /*!< TIM Time Base required parameters                 */
+  HAL_TIM_ActiveChannel              Channel;           /*!< Active channel                                    */
+  DMA_HandleTypeDef                  *hdma[7];          /*!< DMA Handlers array
+                                                             This array is accessed by a @ref DMA_Handle_index */
+  HAL_LockTypeDef                    Lock;              /*!< Locking object                                    */
+  __IO HAL_TIM_StateTypeDef          State;             /*!< TIM operation state                               */
+  __IO HAL_TIM_ChannelStateTypeDef   ChannelState[4];   /*!< TIM channel operation state                       */
+  __IO HAL_TIM_ChannelStateTypeDef   ChannelNState[4];  /*!< TIM complementary channel operation state         */
+  __IO HAL_TIM_DMABurstStateTypeDef  DMABurstState;     /*!< DMA burst operation state                         */
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+  void (* Base_MspInitCallback)(struct __TIM_HandleTypeDef *htim);              /*!< TIM Base Msp Init Callback                              */
+  void (* Base_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim);            /*!< TIM Base Msp DeInit Callback                            */
+  void (* IC_MspInitCallback)(struct __TIM_HandleTypeDef *htim);                /*!< TIM IC Msp Init Callback                                */
+  void (* IC_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim);              /*!< TIM IC Msp DeInit Callback                              */
+  void (* OC_MspInitCallback)(struct __TIM_HandleTypeDef *htim);                /*!< TIM OC Msp Init Callback                                */
+  void (* OC_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim);              /*!< TIM OC Msp DeInit Callback                              */
+  void (* PWM_MspInitCallback)(struct __TIM_HandleTypeDef *htim);               /*!< TIM PWM Msp Init Callback                               */
+  void (* PWM_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim);             /*!< TIM PWM Msp DeInit Callback                             */
+  void (* OnePulse_MspInitCallback)(struct __TIM_HandleTypeDef *htim);          /*!< TIM One Pulse Msp Init Callback                         */
+  void (* OnePulse_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim);        /*!< TIM One Pulse Msp DeInit Callback                       */
+  void (* Encoder_MspInitCallback)(struct __TIM_HandleTypeDef *htim);           /*!< TIM Encoder Msp Init Callback                           */
+  void (* Encoder_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim);         /*!< TIM Encoder Msp DeInit Callback                         */
+  void (* HallSensor_MspInitCallback)(struct __TIM_HandleTypeDef *htim);        /*!< TIM Hall Sensor Msp Init Callback                       */
+  void (* HallSensor_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim);      /*!< TIM Hall Sensor Msp DeInit Callback                     */
+  void (* PeriodElapsedCallback)(struct __TIM_HandleTypeDef *htim);             /*!< TIM Period Elapsed Callback                             */
+  void (* PeriodElapsedHalfCpltCallback)(struct __TIM_HandleTypeDef *htim);     /*!< TIM Period Elapsed half complete Callback               */
+  void (* TriggerCallback)(struct __TIM_HandleTypeDef *htim);                   /*!< TIM Trigger Callback                                    */
+  void (* TriggerHalfCpltCallback)(struct __TIM_HandleTypeDef *htim);           /*!< TIM Trigger half complete Callback                      */
+  void (* IC_CaptureCallback)(struct __TIM_HandleTypeDef *htim);                /*!< TIM Input Capture Callback                              */
+  void (* IC_CaptureHalfCpltCallback)(struct __TIM_HandleTypeDef *htim);        /*!< TIM Input Capture half complete Callback                */
+  void (* OC_DelayElapsedCallback)(struct __TIM_HandleTypeDef *htim);           /*!< TIM Output Compare Delay Elapsed Callback               */
+  void (* PWM_PulseFinishedCallback)(struct __TIM_HandleTypeDef *htim);         /*!< TIM PWM Pulse Finished Callback                         */
+  void (* PWM_PulseFinishedHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Pulse Finished half complete Callback           */
+  void (* ErrorCallback)(struct __TIM_HandleTypeDef *htim);                     /*!< TIM Error Callback                                      */
+  void (* CommutationCallback)(struct __TIM_HandleTypeDef *htim);               /*!< TIM Commutation Callback                                */
+  void (* CommutationHalfCpltCallback)(struct __TIM_HandleTypeDef *htim);       /*!< TIM Commutation half complete Callback                  */
+  void (* BreakCallback)(struct __TIM_HandleTypeDef *htim);                     /*!< TIM Break Callback                                      */
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+} TIM_HandleTypeDef;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+/**
+  * @brief  HAL TIM Callback ID enumeration definition
+  */
+typedef enum
+{
+  HAL_TIM_BASE_MSPINIT_CB_ID              = 0x00U   /*!< TIM Base MspInit Callback ID                              */
+  , HAL_TIM_BASE_MSPDEINIT_CB_ID          = 0x01U   /*!< TIM Base MspDeInit Callback ID                            */
+  , HAL_TIM_IC_MSPINIT_CB_ID              = 0x02U   /*!< TIM IC MspInit Callback ID                                */
+  , HAL_TIM_IC_MSPDEINIT_CB_ID            = 0x03U   /*!< TIM IC MspDeInit Callback ID                              */
+  , HAL_TIM_OC_MSPINIT_CB_ID              = 0x04U   /*!< TIM OC MspInit Callback ID                                */
+  , HAL_TIM_OC_MSPDEINIT_CB_ID            = 0x05U   /*!< TIM OC MspDeInit Callback ID                              */
+  , HAL_TIM_PWM_MSPINIT_CB_ID             = 0x06U   /*!< TIM PWM MspInit Callback ID                               */
+  , HAL_TIM_PWM_MSPDEINIT_CB_ID           = 0x07U   /*!< TIM PWM MspDeInit Callback ID                             */
+  , HAL_TIM_ONE_PULSE_MSPINIT_CB_ID       = 0x08U   /*!< TIM One Pulse MspInit Callback ID                         */
+  , HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID     = 0x09U   /*!< TIM One Pulse MspDeInit Callback ID                       */
+  , HAL_TIM_ENCODER_MSPINIT_CB_ID         = 0x0AU   /*!< TIM Encoder MspInit Callback ID                           */
+  , HAL_TIM_ENCODER_MSPDEINIT_CB_ID       = 0x0BU   /*!< TIM Encoder MspDeInit Callback ID                         */
+  , HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID     = 0x0CU   /*!< TIM Hall Sensor MspDeInit Callback ID                     */
+  , HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID   = 0x0DU   /*!< TIM Hall Sensor MspDeInit Callback ID                     */
+  , HAL_TIM_PERIOD_ELAPSED_CB_ID          = 0x0EU   /*!< TIM Period Elapsed Callback ID                             */
+  , HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID     = 0x0FU   /*!< TIM Period Elapsed half complete Callback ID               */
+  , HAL_TIM_TRIGGER_CB_ID                 = 0x10U   /*!< TIM Trigger Callback ID                                    */
+  , HAL_TIM_TRIGGER_HALF_CB_ID            = 0x11U   /*!< TIM Trigger half complete Callback ID                      */
+
+  , HAL_TIM_IC_CAPTURE_CB_ID              = 0x12U   /*!< TIM Input Capture Callback ID                              */
+  , HAL_TIM_IC_CAPTURE_HALF_CB_ID         = 0x13U   /*!< TIM Input Capture half complete Callback ID                */
+  , HAL_TIM_OC_DELAY_ELAPSED_CB_ID        = 0x14U   /*!< TIM Output Compare Delay Elapsed Callback ID               */
+  , HAL_TIM_PWM_PULSE_FINISHED_CB_ID      = 0x15U   /*!< TIM PWM Pulse Finished Callback ID           */
+  , HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID = 0x16U   /*!< TIM PWM Pulse Finished half complete Callback ID           */
+  , HAL_TIM_ERROR_CB_ID                   = 0x17U   /*!< TIM Error Callback ID                                      */
+  , HAL_TIM_COMMUTATION_CB_ID             = 0x18U   /*!< TIM Commutation Callback ID                                */
+  , HAL_TIM_COMMUTATION_HALF_CB_ID        = 0x19U   /*!< TIM Commutation half complete Callback ID                  */
+  , HAL_TIM_BREAK_CB_ID                   = 0x1AU   /*!< TIM Break Callback ID                                      */
+} HAL_TIM_CallbackIDTypeDef;
+
+/**
+  * @brief  HAL TIM Callback pointer definition
+  */
+typedef  void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim);  /*!< pointer to the TIM callback function */
+
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+/* End of exported types -----------------------------------------------------*/
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup TIM_Exported_Constants TIM Exported Constants
+  * @{
+  */
+
+/** @defgroup TIM_ClearInput_Source TIM Clear Input Source
+  * @{
+  */
+#define TIM_CLEARINPUTSOURCE_NONE           0x00000000U   /*!< OCREF_CLR is disabled */
+#define TIM_CLEARINPUTSOURCE_ETR            0x00000001U   /*!< OCREF_CLR is connected to ETRF input */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_DMA_Base_address TIM DMA Base Address
+  * @{
+  */
+#define TIM_DMABASE_CR1                    0x00000000U
+#define TIM_DMABASE_CR2                    0x00000001U
+#define TIM_DMABASE_SMCR                   0x00000002U
+#define TIM_DMABASE_DIER                   0x00000003U
+#define TIM_DMABASE_SR                     0x00000004U
+#define TIM_DMABASE_EGR                    0x00000005U
+#define TIM_DMABASE_CCMR1                  0x00000006U
+#define TIM_DMABASE_CCMR2                  0x00000007U
+#define TIM_DMABASE_CCER                   0x00000008U
+#define TIM_DMABASE_CNT                    0x00000009U
+#define TIM_DMABASE_PSC                    0x0000000AU
+#define TIM_DMABASE_ARR                    0x0000000BU
+#define TIM_DMABASE_RCR                    0x0000000CU
+#define TIM_DMABASE_CCR1                   0x0000000DU
+#define TIM_DMABASE_CCR2                   0x0000000EU
+#define TIM_DMABASE_CCR3                   0x0000000FU
+#define TIM_DMABASE_CCR4                   0x00000010U
+#define TIM_DMABASE_BDTR                   0x00000011U
+#define TIM_DMABASE_DCR                    0x00000012U
+#define TIM_DMABASE_DMAR                   0x00000013U
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Event_Source TIM Event Source
+  * @{
+  */
+#define TIM_EVENTSOURCE_UPDATE              TIM_EGR_UG     /*!< Reinitialize the counter and generates an update of the registers */
+#define TIM_EVENTSOURCE_CC1                 TIM_EGR_CC1G   /*!< A capture/compare event is generated on channel 1 */
+#define TIM_EVENTSOURCE_CC2                 TIM_EGR_CC2G   /*!< A capture/compare event is generated on channel 2 */
+#define TIM_EVENTSOURCE_CC3                 TIM_EGR_CC3G   /*!< A capture/compare event is generated on channel 3 */
+#define TIM_EVENTSOURCE_CC4                 TIM_EGR_CC4G   /*!< A capture/compare event is generated on channel 4 */
+#define TIM_EVENTSOURCE_COM                 TIM_EGR_COMG   /*!< A commutation event is generated */
+#define TIM_EVENTSOURCE_TRIGGER             TIM_EGR_TG     /*!< A trigger event is generated */
+#define TIM_EVENTSOURCE_BREAK               TIM_EGR_BG     /*!< A break event is generated */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Input_Channel_Polarity TIM Input Channel polarity
+  * @{
+  */
+#define  TIM_INPUTCHANNELPOLARITY_RISING      0x00000000U                       /*!< Polarity for TIx source */
+#define  TIM_INPUTCHANNELPOLARITY_FALLING     TIM_CCER_CC1P                     /*!< Polarity for TIx source */
+#define  TIM_INPUTCHANNELPOLARITY_BOTHEDGE    (TIM_CCER_CC1P | TIM_CCER_CC1NP)  /*!< Polarity for TIx source */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_ETR_Polarity TIM ETR Polarity
+  * @{
+  */
+#define TIM_ETRPOLARITY_INVERTED              TIM_SMCR_ETP                      /*!< Polarity for ETR source */
+#define TIM_ETRPOLARITY_NONINVERTED           0x00000000U                       /*!< Polarity for ETR source */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_ETR_Prescaler TIM ETR Prescaler
+  * @{
+  */
+#define TIM_ETRPRESCALER_DIV1                 0x00000000U                       /*!< No prescaler is used */
+#define TIM_ETRPRESCALER_DIV2                 TIM_SMCR_ETPS_0                   /*!< ETR input source is divided by 2 */
+#define TIM_ETRPRESCALER_DIV4                 TIM_SMCR_ETPS_1                   /*!< ETR input source is divided by 4 */
+#define TIM_ETRPRESCALER_DIV8                 TIM_SMCR_ETPS                     /*!< ETR input source is divided by 8 */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Counter_Mode TIM Counter Mode
+  * @{
+  */
+#define TIM_COUNTERMODE_UP                 0x00000000U                          /*!< Counter used as up-counter   */
+#define TIM_COUNTERMODE_DOWN               TIM_CR1_DIR                          /*!< Counter used as down-counter */
+#define TIM_COUNTERMODE_CENTERALIGNED1     TIM_CR1_CMS_0                        /*!< Center-aligned mode 1        */
+#define TIM_COUNTERMODE_CENTERALIGNED2     TIM_CR1_CMS_1                        /*!< Center-aligned mode 2        */
+#define TIM_COUNTERMODE_CENTERALIGNED3     TIM_CR1_CMS                          /*!< Center-aligned mode 3        */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_ClockDivision TIM Clock Division
+  * @{
+  */
+#define TIM_CLOCKDIVISION_DIV1             0x00000000U                          /*!< Clock division: tDTS=tCK_INT   */
+#define TIM_CLOCKDIVISION_DIV2             TIM_CR1_CKD_0                        /*!< Clock division: tDTS=2*tCK_INT */
+#define TIM_CLOCKDIVISION_DIV4             TIM_CR1_CKD_1                        /*!< Clock division: tDTS=4*tCK_INT */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Output_Compare_State TIM Output Compare State
+  * @{
+  */
+#define TIM_OUTPUTSTATE_DISABLE            0x00000000U                          /*!< Capture/Compare 1 output disabled */
+#define TIM_OUTPUTSTATE_ENABLE             TIM_CCER_CC1E                        /*!< Capture/Compare 1 output enabled */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_AutoReloadPreload TIM Auto-Reload Preload
+  * @{
+  */
+#define TIM_AUTORELOAD_PRELOAD_DISABLE                0x00000000U               /*!< TIMx_ARR register is not buffered */
+#define TIM_AUTORELOAD_PRELOAD_ENABLE                 TIM_CR1_ARPE              /*!< TIMx_ARR register is buffered */
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Output_Fast_State TIM Output Fast State
+  * @{
+  */
+#define TIM_OCFAST_DISABLE                 0x00000000U                          /*!< Output Compare fast disable */
+#define TIM_OCFAST_ENABLE                  TIM_CCMR1_OC1FE                      /*!< Output Compare fast enable  */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Output_Compare_N_State TIM Complementary Output Compare State
+  * @{
+  */
+#define TIM_OUTPUTNSTATE_DISABLE           0x00000000U                          /*!< OCxN is disabled  */
+#define TIM_OUTPUTNSTATE_ENABLE            TIM_CCER_CC1NE                       /*!< OCxN is enabled   */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Output_Compare_Polarity TIM Output Compare Polarity
+  * @{
+  */
+#define TIM_OCPOLARITY_HIGH                0x00000000U                          /*!< Capture/Compare output polarity  */
+#define TIM_OCPOLARITY_LOW                 TIM_CCER_CC1P                        /*!< Capture/Compare output polarity  */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Output_Compare_N_Polarity TIM Complementary Output Compare Polarity
+  * @{
+  */
+#define TIM_OCNPOLARITY_HIGH               0x00000000U                          /*!< Capture/Compare complementary output polarity */
+#define TIM_OCNPOLARITY_LOW                TIM_CCER_CC1NP                       /*!< Capture/Compare complementary output polarity */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Output_Compare_Idle_State TIM Output Compare Idle State
+  * @{
+  */
+#define TIM_OCIDLESTATE_SET                TIM_CR2_OIS1                         /*!< Output Idle state: OCx=1 when MOE=0 */
+#define TIM_OCIDLESTATE_RESET              0x00000000U                          /*!< Output Idle state: OCx=0 when MOE=0 */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Output_Compare_N_Idle_State TIM Complementary Output Compare Idle State
+  * @{
+  */
+#define TIM_OCNIDLESTATE_SET               TIM_CR2_OIS1N                        /*!< Complementary output Idle state: OCxN=1 when MOE=0 */
+#define TIM_OCNIDLESTATE_RESET             0x00000000U                          /*!< Complementary output Idle state: OCxN=0 when MOE=0 */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Input_Capture_Polarity TIM Input Capture Polarity
+  * @{
+  */
+#define  TIM_ICPOLARITY_RISING             TIM_INPUTCHANNELPOLARITY_RISING      /*!< Capture triggered by rising edge on timer input                  */
+#define  TIM_ICPOLARITY_FALLING            TIM_INPUTCHANNELPOLARITY_FALLING     /*!< Capture triggered by falling edge on timer input                 */
+#define  TIM_ICPOLARITY_BOTHEDGE           TIM_INPUTCHANNELPOLARITY_BOTHEDGE    /*!< Capture triggered by both rising and falling edges on timer input*/
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Encoder_Input_Polarity TIM Encoder Input Polarity
+  * @{
+  */
+#define  TIM_ENCODERINPUTPOLARITY_RISING   TIM_INPUTCHANNELPOLARITY_RISING      /*!< Encoder input with rising edge polarity  */
+#define  TIM_ENCODERINPUTPOLARITY_FALLING  TIM_INPUTCHANNELPOLARITY_FALLING     /*!< Encoder input with falling edge polarity */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection
+  * @{
+  */
+#define TIM_ICSELECTION_DIRECTTI           TIM_CCMR1_CC1S_0                     /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to IC1, IC2, IC3 or IC4, respectively */
+#define TIM_ICSELECTION_INDIRECTTI         TIM_CCMR1_CC1S_1                     /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to IC2, IC1, IC4 or IC3, respectively */
+#define TIM_ICSELECTION_TRC                TIM_CCMR1_CC1S                       /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Input_Capture_Prescaler TIM Input Capture Prescaler
+  * @{
+  */
+#define TIM_ICPSC_DIV1                     0x00000000U                          /*!< Capture performed each time an edge is detected on the capture input */
+#define TIM_ICPSC_DIV2                     TIM_CCMR1_IC1PSC_0                   /*!< Capture performed once every 2 events                                */
+#define TIM_ICPSC_DIV4                     TIM_CCMR1_IC1PSC_1                   /*!< Capture performed once every 4 events                                */
+#define TIM_ICPSC_DIV8                     TIM_CCMR1_IC1PSC                     /*!< Capture performed once every 8 events                                */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_One_Pulse_Mode TIM One Pulse Mode
+  * @{
+  */
+#define TIM_OPMODE_SINGLE                  TIM_CR1_OPM                          /*!< Counter stops counting at the next update event */
+#define TIM_OPMODE_REPETITIVE              0x00000000U                          /*!< Counter is not stopped at update event          */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Encoder_Mode TIM Encoder Mode
+  * @{
+  */
+#define TIM_ENCODERMODE_TI1                      TIM_SMCR_SMS_0                                                      /*!< Quadrature encoder mode 1, x2 mode, counts up/down on TI1FP1 edge depending on TI2FP2 level  */
+#define TIM_ENCODERMODE_TI2                      TIM_SMCR_SMS_1                                                      /*!< Quadrature encoder mode 2, x2 mode, counts up/down on TI2FP2 edge depending on TI1FP1 level. */
+#define TIM_ENCODERMODE_TI12                     (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)                                   /*!< Quadrature encoder mode 3, x4 mode, counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input. */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Interrupt_definition TIM interrupt Definition
+  * @{
+  */
+#define TIM_IT_UPDATE                      TIM_DIER_UIE                         /*!< Update interrupt            */
+#define TIM_IT_CC1                         TIM_DIER_CC1IE                       /*!< Capture/Compare 1 interrupt */
+#define TIM_IT_CC2                         TIM_DIER_CC2IE                       /*!< Capture/Compare 2 interrupt */
+#define TIM_IT_CC3                         TIM_DIER_CC3IE                       /*!< Capture/Compare 3 interrupt */
+#define TIM_IT_CC4                         TIM_DIER_CC4IE                       /*!< Capture/Compare 4 interrupt */
+#define TIM_IT_COM                         TIM_DIER_COMIE                       /*!< Commutation interrupt       */
+#define TIM_IT_TRIGGER                     TIM_DIER_TIE                         /*!< Trigger interrupt           */
+#define TIM_IT_BREAK                       TIM_DIER_BIE                         /*!< Break interrupt             */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Commutation_Source  TIM Commutation Source
+  * @{
+  */
+#define TIM_COMMUTATION_TRGI              TIM_CR2_CCUS                          /*!< When Capture/compare control bits are preloaded, they are updated by setting the COMG bit or when an rising edge occurs on trigger input */
+#define TIM_COMMUTATION_SOFTWARE          0x00000000U                           /*!< When Capture/compare control bits are preloaded, they are updated by setting the COMG bit */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_DMA_sources TIM DMA Sources
+  * @{
+  */
+#define TIM_DMA_UPDATE                     TIM_DIER_UDE                         /*!< DMA request is triggered by the update event */
+#define TIM_DMA_CC1                        TIM_DIER_CC1DE                       /*!< DMA request is triggered by the capture/compare macth 1 event */
+#define TIM_DMA_CC2                        TIM_DIER_CC2DE                       /*!< DMA request is triggered by the capture/compare macth 2 event event */
+#define TIM_DMA_CC3                        TIM_DIER_CC3DE                       /*!< DMA request is triggered by the capture/compare macth 3 event event */
+#define TIM_DMA_CC4                        TIM_DIER_CC4DE                       /*!< DMA request is triggered by the capture/compare macth 4 event event */
+#define TIM_DMA_COM                        TIM_DIER_COMDE                       /*!< DMA request is triggered by the commutation event */
+#define TIM_DMA_TRIGGER                    TIM_DIER_TDE                         /*!< DMA request is triggered by the trigger event */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_CC_DMA_Request CCx DMA request selection
+  * @{
+  */
+#define TIM_CCDMAREQUEST_CC                 0x00000000U                         /*!< CCx DMA request sent when capture or compare match event occurs */
+#define TIM_CCDMAREQUEST_UPDATE             TIM_CR2_CCDS                        /*!< CCx DMA requests sent when update event occurs */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Flag_definition TIM Flag Definition
+  * @{
+  */
+#define TIM_FLAG_UPDATE                    TIM_SR_UIF                           /*!< Update interrupt flag         */
+#define TIM_FLAG_CC1                       TIM_SR_CC1IF                         /*!< Capture/Compare 1 interrupt flag */
+#define TIM_FLAG_CC2                       TIM_SR_CC2IF                         /*!< Capture/Compare 2 interrupt flag */
+#define TIM_FLAG_CC3                       TIM_SR_CC3IF                         /*!< Capture/Compare 3 interrupt flag */
+#define TIM_FLAG_CC4                       TIM_SR_CC4IF                         /*!< Capture/Compare 4 interrupt flag */
+#define TIM_FLAG_COM                       TIM_SR_COMIF                         /*!< Commutation interrupt flag    */
+#define TIM_FLAG_TRIGGER                   TIM_SR_TIF                           /*!< Trigger interrupt flag        */
+#define TIM_FLAG_BREAK                     TIM_SR_BIF                           /*!< Break interrupt flag          */
+#define TIM_FLAG_CC1OF                     TIM_SR_CC1OF                         /*!< Capture 1 overcapture flag    */
+#define TIM_FLAG_CC2OF                     TIM_SR_CC2OF                         /*!< Capture 2 overcapture flag    */
+#define TIM_FLAG_CC3OF                     TIM_SR_CC3OF                         /*!< Capture 3 overcapture flag    */
+#define TIM_FLAG_CC4OF                     TIM_SR_CC4OF                         /*!< Capture 4 overcapture flag    */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Channel TIM Channel
+  * @{
+  */
+#define TIM_CHANNEL_1                      0x00000000U                          /*!< Capture/compare channel 1 identifier      */
+#define TIM_CHANNEL_2                      0x00000004U                          /*!< Capture/compare channel 2 identifier      */
+#define TIM_CHANNEL_3                      0x00000008U                          /*!< Capture/compare channel 3 identifier      */
+#define TIM_CHANNEL_4                      0x0000000CU                          /*!< Capture/compare channel 4 identifier      */
+#define TIM_CHANNEL_ALL                    0x0000003CU                          /*!< Global Capture/compare channel identifier  */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Clock_Source TIM Clock Source
+  * @{
+  */
+#define TIM_CLOCKSOURCE_INTERNAL    TIM_SMCR_ETPS_0      /*!< Internal clock source                                 */
+#define TIM_CLOCKSOURCE_ETRMODE1    TIM_TS_ETRF          /*!< External clock source mode 1 (ETRF)                   */
+#define TIM_CLOCKSOURCE_ETRMODE2    TIM_SMCR_ETPS_1      /*!< External clock source mode 2                          */
+#define TIM_CLOCKSOURCE_TI1ED       TIM_TS_TI1F_ED       /*!< External clock source mode 1 (TTI1FP1 + edge detect.) */
+#define TIM_CLOCKSOURCE_TI1         TIM_TS_TI1FP1        /*!< External clock source mode 1 (TTI1FP1)                */
+#define TIM_CLOCKSOURCE_TI2         TIM_TS_TI2FP2        /*!< External clock source mode 1 (TTI2FP2)                */
+#define TIM_CLOCKSOURCE_ITR0        TIM_TS_ITR0          /*!< External clock source mode 1 (ITR0)                   */
+#define TIM_CLOCKSOURCE_ITR1        TIM_TS_ITR1          /*!< External clock source mode 1 (ITR1)                   */
+#define TIM_CLOCKSOURCE_ITR2        TIM_TS_ITR2          /*!< External clock source mode 1 (ITR2)                   */
+#define TIM_CLOCKSOURCE_ITR3        TIM_TS_ITR3          /*!< External clock source mode 1 (ITR3)                   */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Clock_Polarity TIM Clock Polarity
+  * @{
+  */
+#define TIM_CLOCKPOLARITY_INVERTED           TIM_ETRPOLARITY_INVERTED           /*!< Polarity for ETRx clock sources */
+#define TIM_CLOCKPOLARITY_NONINVERTED        TIM_ETRPOLARITY_NONINVERTED        /*!< Polarity for ETRx clock sources */
+#define TIM_CLOCKPOLARITY_RISING             TIM_INPUTCHANNELPOLARITY_RISING    /*!< Polarity for TIx clock sources */
+#define TIM_CLOCKPOLARITY_FALLING            TIM_INPUTCHANNELPOLARITY_FALLING   /*!< Polarity for TIx clock sources */
+#define TIM_CLOCKPOLARITY_BOTHEDGE           TIM_INPUTCHANNELPOLARITY_BOTHEDGE  /*!< Polarity for TIx clock sources */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Clock_Prescaler TIM Clock Prescaler
+  * @{
+  */
+#define TIM_CLOCKPRESCALER_DIV1                 TIM_ETRPRESCALER_DIV1           /*!< No prescaler is used                                                     */
+#define TIM_CLOCKPRESCALER_DIV2                 TIM_ETRPRESCALER_DIV2           /*!< Prescaler for External ETR Clock: Capture performed once every 2 events. */
+#define TIM_CLOCKPRESCALER_DIV4                 TIM_ETRPRESCALER_DIV4           /*!< Prescaler for External ETR Clock: Capture performed once every 4 events. */
+#define TIM_CLOCKPRESCALER_DIV8                 TIM_ETRPRESCALER_DIV8           /*!< Prescaler for External ETR Clock: Capture performed once every 8 events. */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_ClearInput_Polarity TIM Clear Input Polarity
+  * @{
+  */
+#define TIM_CLEARINPUTPOLARITY_INVERTED           TIM_ETRPOLARITY_INVERTED      /*!< Polarity for ETRx pin */
+#define TIM_CLEARINPUTPOLARITY_NONINVERTED        TIM_ETRPOLARITY_NONINVERTED   /*!< Polarity for ETRx pin */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_ClearInput_Prescaler TIM Clear Input Prescaler
+  * @{
+  */
+#define TIM_CLEARINPUTPRESCALER_DIV1              TIM_ETRPRESCALER_DIV1         /*!< No prescaler is used                                                   */
+#define TIM_CLEARINPUTPRESCALER_DIV2              TIM_ETRPRESCALER_DIV2         /*!< Prescaler for External ETR pin: Capture performed once every 2 events. */
+#define TIM_CLEARINPUTPRESCALER_DIV4              TIM_ETRPRESCALER_DIV4         /*!< Prescaler for External ETR pin: Capture performed once every 4 events. */
+#define TIM_CLEARINPUTPRESCALER_DIV8              TIM_ETRPRESCALER_DIV8         /*!< Prescaler for External ETR pin: Capture performed once every 8 events. */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state TIM OSSR OffState Selection for Run mode state
+  * @{
+  */
+#define TIM_OSSR_ENABLE                          TIM_BDTR_OSSR                  /*!< When inactive, OC/OCN outputs are enabled (still controlled by the timer)           */
+#define TIM_OSSR_DISABLE                         0x00000000U                    /*!< When inactive, OC/OCN outputs are disabled (not controlled any longer by the timer) */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state TIM OSSI OffState Selection for Idle mode state
+  * @{
+  */
+#define TIM_OSSI_ENABLE                          TIM_BDTR_OSSI                  /*!< When inactive, OC/OCN outputs are enabled (still controlled by the timer)           */
+#define TIM_OSSI_DISABLE                         0x00000000U                    /*!< When inactive, OC/OCN outputs are disabled (not controlled any longer by the timer) */
+/**
+  * @}
+  */
+/** @defgroup TIM_Lock_level  TIM Lock level
+  * @{
+  */
+#define TIM_LOCKLEVEL_OFF                  0x00000000U                          /*!< LOCK OFF     */
+#define TIM_LOCKLEVEL_1                    TIM_BDTR_LOCK_0                      /*!< LOCK Level 1 */
+#define TIM_LOCKLEVEL_2                    TIM_BDTR_LOCK_1                      /*!< LOCK Level 2 */
+#define TIM_LOCKLEVEL_3                    TIM_BDTR_LOCK                        /*!< LOCK Level 3 */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Break_Input_enable_disable TIM Break Input Enable
+  * @{
+  */
+#define TIM_BREAK_ENABLE                   TIM_BDTR_BKE                         /*!< Break input BRK is enabled  */
+#define TIM_BREAK_DISABLE                  0x00000000U                          /*!< Break input BRK is disabled */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Break_Polarity TIM Break Input Polarity
+  * @{
+  */
+#define TIM_BREAKPOLARITY_LOW              0x00000000U                          /*!< Break input BRK is active low  */
+#define TIM_BREAKPOLARITY_HIGH             TIM_BDTR_BKP                         /*!< Break input BRK is active high */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_AOE_Bit_Set_Reset TIM Automatic Output Enable
+  * @{
+  */
+#define TIM_AUTOMATICOUTPUT_DISABLE        0x00000000U                          /*!< MOE can be set only by software */
+#define TIM_AUTOMATICOUTPUT_ENABLE         TIM_BDTR_AOE                         /*!< MOE can be set by software or automatically at the next update event (if none of the break inputs BRK and BRK2 is active) */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection
+  * @{
+  */
+#define TIM_TRGO_RESET            0x00000000U                                      /*!< TIMx_EGR.UG bit is used as trigger output (TRGO)              */
+#define TIM_TRGO_ENABLE           TIM_CR2_MMS_0                                    /*!< TIMx_CR1.CEN bit is used as trigger output (TRGO)             */
+#define TIM_TRGO_UPDATE           TIM_CR2_MMS_1                                    /*!< Update event is used as trigger output (TRGO)                 */
+#define TIM_TRGO_OC1              (TIM_CR2_MMS_1 | TIM_CR2_MMS_0)                  /*!< Capture or a compare match 1 is used as trigger output (TRGO) */
+#define TIM_TRGO_OC1REF           TIM_CR2_MMS_2                                    /*!< OC1REF signal is used as trigger output (TRGO)                */
+#define TIM_TRGO_OC2REF           (TIM_CR2_MMS_2 | TIM_CR2_MMS_0)                  /*!< OC2REF signal is used as trigger output(TRGO)                 */
+#define TIM_TRGO_OC3REF           (TIM_CR2_MMS_2 | TIM_CR2_MMS_1)                  /*!< OC3REF signal is used as trigger output(TRGO)                 */
+#define TIM_TRGO_OC4REF           (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0)  /*!< OC4REF signal is used as trigger output(TRGO)                 */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Master_Slave_Mode TIM Master/Slave Mode
+  * @{
+  */
+#define TIM_MASTERSLAVEMODE_ENABLE         TIM_SMCR_MSM                         /*!< No action */
+#define TIM_MASTERSLAVEMODE_DISABLE        0x00000000U                          /*!< Master/slave mode is selected */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Slave_Mode TIM Slave mode
+  * @{
+  */
+#define TIM_SLAVEMODE_DISABLE                0x00000000U                                        /*!< Slave mode disabled           */
+#define TIM_SLAVEMODE_RESET                  TIM_SMCR_SMS_2                                     /*!< Reset Mode                    */
+#define TIM_SLAVEMODE_GATED                  (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0)                  /*!< Gated Mode                    */
+#define TIM_SLAVEMODE_TRIGGER                (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1)                  /*!< Trigger Mode                  */
+#define TIM_SLAVEMODE_EXTERNAL1              (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< External Clock Mode 1         */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Output_Compare_and_PWM_modes TIM Output Compare and PWM Modes
+  * @{
+  */
+#define TIM_OCMODE_TIMING                   0x00000000U                                              /*!< Frozen                                 */
+#define TIM_OCMODE_ACTIVE                   TIM_CCMR1_OC1M_0                                         /*!< Set channel to active level on match   */
+#define TIM_OCMODE_INACTIVE                 TIM_CCMR1_OC1M_1                                         /*!< Set channel to inactive level on match */
+#define TIM_OCMODE_TOGGLE                   (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0)                    /*!< Toggle                                 */
+#define TIM_OCMODE_PWM1                     (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1)                    /*!< PWM mode 1                             */
+#define TIM_OCMODE_PWM2                     (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!< PWM mode 2                             */
+#define TIM_OCMODE_FORCED_ACTIVE            (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0)                    /*!< Force active level                     */
+#define TIM_OCMODE_FORCED_INACTIVE          TIM_CCMR1_OC1M_2                                         /*!< Force inactive level                   */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Trigger_Selection TIM Trigger Selection
+  * @{
+  */
+#define TIM_TS_ITR0          0x00000000U                                                       /*!< Internal Trigger 0 (ITR0)              */
+#define TIM_TS_ITR1          TIM_SMCR_TS_0                                                     /*!< Internal Trigger 1 (ITR1)              */
+#define TIM_TS_ITR2          TIM_SMCR_TS_1                                                     /*!< Internal Trigger 2 (ITR2)              */
+#define TIM_TS_ITR3          (TIM_SMCR_TS_0 | TIM_SMCR_TS_1)                                   /*!< Internal Trigger 3 (ITR3)              */
+#define TIM_TS_TI1F_ED       TIM_SMCR_TS_2                                                     /*!< TI1 Edge Detector (TI1F_ED)            */
+#define TIM_TS_TI1FP1        (TIM_SMCR_TS_0 | TIM_SMCR_TS_2)                                   /*!< Filtered Timer Input 1 (TI1FP1)        */
+#define TIM_TS_TI2FP2        (TIM_SMCR_TS_1 | TIM_SMCR_TS_2)                                   /*!< Filtered Timer Input 2 (TI2FP2)        */
+#define TIM_TS_ETRF          (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_2)                   /*!< Filtered External Trigger input (ETRF) */
+#define TIM_TS_NONE          0x0000FFFFU                                                       /*!< No trigger selected                    */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Trigger_Polarity TIM Trigger Polarity
+  * @{
+  */
+#define TIM_TRIGGERPOLARITY_INVERTED           TIM_ETRPOLARITY_INVERTED               /*!< Polarity for ETRx trigger sources             */
+#define TIM_TRIGGERPOLARITY_NONINVERTED        TIM_ETRPOLARITY_NONINVERTED            /*!< Polarity for ETRx trigger sources             */
+#define TIM_TRIGGERPOLARITY_RISING             TIM_INPUTCHANNELPOLARITY_RISING        /*!< Polarity for TIxFPx or TI1_ED trigger sources */
+#define TIM_TRIGGERPOLARITY_FALLING            TIM_INPUTCHANNELPOLARITY_FALLING       /*!< Polarity for TIxFPx or TI1_ED trigger sources */
+#define TIM_TRIGGERPOLARITY_BOTHEDGE           TIM_INPUTCHANNELPOLARITY_BOTHEDGE      /*!< Polarity for TIxFPx or TI1_ED trigger sources */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Trigger_Prescaler TIM Trigger Prescaler
+  * @{
+  */
+#define TIM_TRIGGERPRESCALER_DIV1             TIM_ETRPRESCALER_DIV1             /*!< No prescaler is used                                                       */
+#define TIM_TRIGGERPRESCALER_DIV2             TIM_ETRPRESCALER_DIV2             /*!< Prescaler for External ETR Trigger: Capture performed once every 2 events. */
+#define TIM_TRIGGERPRESCALER_DIV4             TIM_ETRPRESCALER_DIV4             /*!< Prescaler for External ETR Trigger: Capture performed once every 4 events. */
+#define TIM_TRIGGERPRESCALER_DIV8             TIM_ETRPRESCALER_DIV8             /*!< Prescaler for External ETR Trigger: Capture performed once every 8 events. */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_TI1_Selection TIM TI1 Input Selection
+  * @{
+  */
+#define TIM_TI1SELECTION_CH1               0x00000000U                          /*!< The TIMx_CH1 pin is connected to TI1 input */
+#define TIM_TI1SELECTION_XORCOMBINATION    TIM_CR2_TI1S                         /*!< The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination) */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length
+  * @{
+  */
+#define TIM_DMABURSTLENGTH_1TRANSFER       0x00000000U                          /*!< The transfer is done to 1 register starting from TIMx_CR1 + TIMx_DCR.DBA   */
+#define TIM_DMABURSTLENGTH_2TRANSFERS      0x00000100U                          /*!< The transfer is done to 2 registers starting from TIMx_CR1 + TIMx_DCR.DBA  */
+#define TIM_DMABURSTLENGTH_3TRANSFERS      0x00000200U                          /*!< The transfer is done to 3 registers starting from TIMx_CR1 + TIMx_DCR.DBA  */
+#define TIM_DMABURSTLENGTH_4TRANSFERS      0x00000300U                          /*!< The transfer is done to 4 registers starting from TIMx_CR1 + TIMx_DCR.DBA  */
+#define TIM_DMABURSTLENGTH_5TRANSFERS      0x00000400U                          /*!< The transfer is done to 5 registers starting from TIMx_CR1 + TIMx_DCR.DBA  */
+#define TIM_DMABURSTLENGTH_6TRANSFERS      0x00000500U                          /*!< The transfer is done to 6 registers starting from TIMx_CR1 + TIMx_DCR.DBA  */
+#define TIM_DMABURSTLENGTH_7TRANSFERS      0x00000600U                          /*!< The transfer is done to 7 registers starting from TIMx_CR1 + TIMx_DCR.DBA  */
+#define TIM_DMABURSTLENGTH_8TRANSFERS      0x00000700U                          /*!< The transfer is done to 8 registers starting from TIMx_CR1 + TIMx_DCR.DBA  */
+#define TIM_DMABURSTLENGTH_9TRANSFERS      0x00000800U                          /*!< The transfer is done to 9 registers starting from TIMx_CR1 + TIMx_DCR.DBA  */
+#define TIM_DMABURSTLENGTH_10TRANSFERS     0x00000900U                          /*!< The transfer is done to 10 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_11TRANSFERS     0x00000A00U                          /*!< The transfer is done to 11 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_12TRANSFERS     0x00000B00U                          /*!< The transfer is done to 12 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_13TRANSFERS     0x00000C00U                          /*!< The transfer is done to 13 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_14TRANSFERS     0x00000D00U                          /*!< The transfer is done to 14 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_15TRANSFERS     0x00000E00U                          /*!< The transfer is done to 15 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_16TRANSFERS     0x00000F00U                          /*!< The transfer is done to 16 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_17TRANSFERS     0x00001000U                          /*!< The transfer is done to 17 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_18TRANSFERS     0x00001100U                          /*!< The transfer is done to 18 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_Handle_index TIM DMA Handle Index
+  * @{
+  */
+#define TIM_DMA_ID_UPDATE                ((uint16_t) 0x0000)       /*!< Index of the DMA handle used for Update DMA requests */
+#define TIM_DMA_ID_CC1                   ((uint16_t) 0x0001)       /*!< Index of the DMA handle used for Capture/Compare 1 DMA requests */
+#define TIM_DMA_ID_CC2                   ((uint16_t) 0x0002)       /*!< Index of the DMA handle used for Capture/Compare 2 DMA requests */
+#define TIM_DMA_ID_CC3                   ((uint16_t) 0x0003)       /*!< Index of the DMA handle used for Capture/Compare 3 DMA requests */
+#define TIM_DMA_ID_CC4                   ((uint16_t) 0x0004)       /*!< Index of the DMA handle used for Capture/Compare 4 DMA requests */
+#define TIM_DMA_ID_COMMUTATION           ((uint16_t) 0x0005)       /*!< Index of the DMA handle used for Commutation DMA requests */
+#define TIM_DMA_ID_TRIGGER               ((uint16_t) 0x0006)       /*!< Index of the DMA handle used for Trigger DMA requests */
+/**
+  * @}
+  */
+
+/** @defgroup Channel_CC_State TIM Capture/Compare Channel State
+  * @{
+  */
+#define TIM_CCx_ENABLE                   0x00000001U                            /*!< Input or output channel is enabled */
+#define TIM_CCx_DISABLE                  0x00000000U                            /*!< Input or output channel is disabled */
+#define TIM_CCxN_ENABLE                  0x00000004U                            /*!< Complementary output channel is enabled */
+#define TIM_CCxN_DISABLE                 0x00000000U                            /*!< Complementary output channel is enabled */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+/* End of exported constants -------------------------------------------------*/
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup TIM_Exported_Macros TIM Exported Macros
+  * @{
+  */
+
+/** @brief  Reset TIM handle state.
+  * @param  __HANDLE__ TIM handle.
+  * @retval None
+  */
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do {                                                               \
+                                                      (__HANDLE__)->State            = HAL_TIM_STATE_RESET;         \
+                                                      (__HANDLE__)->ChannelState[0]  = HAL_TIM_CHANNEL_STATE_RESET; \
+                                                      (__HANDLE__)->ChannelState[1]  = HAL_TIM_CHANNEL_STATE_RESET; \
+                                                      (__HANDLE__)->ChannelState[2]  = HAL_TIM_CHANNEL_STATE_RESET; \
+                                                      (__HANDLE__)->ChannelState[3]  = HAL_TIM_CHANNEL_STATE_RESET; \
+                                                      (__HANDLE__)->ChannelNState[0] = HAL_TIM_CHANNEL_STATE_RESET; \
+                                                      (__HANDLE__)->ChannelNState[1] = HAL_TIM_CHANNEL_STATE_RESET; \
+                                                      (__HANDLE__)->ChannelNState[2] = HAL_TIM_CHANNEL_STATE_RESET; \
+                                                      (__HANDLE__)->ChannelNState[3] = HAL_TIM_CHANNEL_STATE_RESET; \
+                                                      (__HANDLE__)->DMABurstState    = HAL_DMA_BURST_STATE_RESET;   \
+                                                      (__HANDLE__)->Base_MspInitCallback         = NULL;            \
+                                                      (__HANDLE__)->Base_MspDeInitCallback       = NULL;            \
+                                                      (__HANDLE__)->IC_MspInitCallback           = NULL;            \
+                                                      (__HANDLE__)->IC_MspDeInitCallback         = NULL;            \
+                                                      (__HANDLE__)->OC_MspInitCallback           = NULL;            \
+                                                      (__HANDLE__)->OC_MspDeInitCallback         = NULL;            \
+                                                      (__HANDLE__)->PWM_MspInitCallback          = NULL;            \
+                                                      (__HANDLE__)->PWM_MspDeInitCallback        = NULL;            \
+                                                      (__HANDLE__)->OnePulse_MspInitCallback     = NULL;            \
+                                                      (__HANDLE__)->OnePulse_MspDeInitCallback   = NULL;            \
+                                                      (__HANDLE__)->Encoder_MspInitCallback      = NULL;            \
+                                                      (__HANDLE__)->Encoder_MspDeInitCallback    = NULL;            \
+                                                      (__HANDLE__)->HallSensor_MspInitCallback   = NULL;            \
+                                                      (__HANDLE__)->HallSensor_MspDeInitCallback = NULL;            \
+                                                     } while(0)
+#else
+#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do {                                                               \
+                                                      (__HANDLE__)->State            = HAL_TIM_STATE_RESET;         \
+                                                      (__HANDLE__)->ChannelState[0]  = HAL_TIM_CHANNEL_STATE_RESET; \
+                                                      (__HANDLE__)->ChannelState[1]  = HAL_TIM_CHANNEL_STATE_RESET; \
+                                                      (__HANDLE__)->ChannelState[2]  = HAL_TIM_CHANNEL_STATE_RESET; \
+                                                      (__HANDLE__)->ChannelState[3]  = HAL_TIM_CHANNEL_STATE_RESET; \
+                                                      (__HANDLE__)->ChannelNState[0] = HAL_TIM_CHANNEL_STATE_RESET; \
+                                                      (__HANDLE__)->ChannelNState[1] = HAL_TIM_CHANNEL_STATE_RESET; \
+                                                      (__HANDLE__)->ChannelNState[2] = HAL_TIM_CHANNEL_STATE_RESET; \
+                                                      (__HANDLE__)->ChannelNState[3] = HAL_TIM_CHANNEL_STATE_RESET; \
+                                                      (__HANDLE__)->DMABurstState    = HAL_DMA_BURST_STATE_RESET;   \
+                                                     } while(0)
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+/**
+  * @brief  Enable the TIM peripheral.
+  * @param  __HANDLE__ TIM handle
+  * @retval None
+  */
+#define __HAL_TIM_ENABLE(__HANDLE__)                 ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN))
+
+/**
+  * @brief  Enable the TIM main Output.
+  * @param  __HANDLE__ TIM handle
+  * @retval None
+  */
+#define __HAL_TIM_MOE_ENABLE(__HANDLE__)             ((__HANDLE__)->Instance->BDTR|=(TIM_BDTR_MOE))
+
+/**
+  * @brief  Disable the TIM peripheral.
+  * @param  __HANDLE__ TIM handle
+  * @retval None
+  */
+#define __HAL_TIM_DISABLE(__HANDLE__) \
+  do { \
+    if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \
+    { \
+      if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \
+      { \
+        (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \
+      } \
+    } \
+  } while(0)
+
+/**
+  * @brief  Disable the TIM main Output.
+  * @param  __HANDLE__ TIM handle
+  * @retval None
+  * @note The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN channels have been
+  *       disabled
+  */
+#define __HAL_TIM_MOE_DISABLE(__HANDLE__) \
+  do { \
+    if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \
+    { \
+      if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \
+      { \
+        (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \
+      } \
+    } \
+  } while(0)
+
+/**
+  * @brief  Disable the TIM main Output.
+  * @param  __HANDLE__ TIM handle
+  * @retval None
+  * @note The Main Output Enable of a timer instance is disabled unconditionally
+  */
+#define __HAL_TIM_MOE_DISABLE_UNCONDITIONALLY(__HANDLE__)  (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE)
+
+/** @brief  Enable the specified TIM interrupt.
+  * @param  __HANDLE__ specifies the TIM Handle.
+  * @param  __INTERRUPT__ specifies the TIM interrupt source to enable.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_IT_UPDATE: Update interrupt
+  *            @arg TIM_IT_CC1:   Capture/Compare 1 interrupt
+  *            @arg TIM_IT_CC2:  Capture/Compare 2 interrupt
+  *            @arg TIM_IT_CC3:  Capture/Compare 3 interrupt
+  *            @arg TIM_IT_CC4:  Capture/Compare 4 interrupt
+  *            @arg TIM_IT_COM:   Commutation interrupt
+  *            @arg TIM_IT_TRIGGER: Trigger interrupt
+  *            @arg TIM_IT_BREAK: Break interrupt
+  * @retval None
+  */
+#define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__)    ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__))
+
+/** @brief  Disable the specified TIM interrupt.
+  * @param  __HANDLE__ specifies the TIM Handle.
+  * @param  __INTERRUPT__ specifies the TIM interrupt source to disable.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_IT_UPDATE: Update interrupt
+  *            @arg TIM_IT_CC1:   Capture/Compare 1 interrupt
+  *            @arg TIM_IT_CC2:  Capture/Compare 2 interrupt
+  *            @arg TIM_IT_CC3:  Capture/Compare 3 interrupt
+  *            @arg TIM_IT_CC4:  Capture/Compare 4 interrupt
+  *            @arg TIM_IT_COM:   Commutation interrupt
+  *            @arg TIM_IT_TRIGGER: Trigger interrupt
+  *            @arg TIM_IT_BREAK: Break interrupt
+  * @retval None
+  */
+#define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__)   ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__))
+
+/** @brief  Enable the specified DMA request.
+  * @param  __HANDLE__ specifies the TIM Handle.
+  * @param  __DMA__ specifies the TIM DMA request to enable.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_DMA_UPDATE: Update DMA request
+  *            @arg TIM_DMA_CC1:   Capture/Compare 1 DMA request
+  *            @arg TIM_DMA_CC2:  Capture/Compare 2 DMA request
+  *            @arg TIM_DMA_CC3:  Capture/Compare 3 DMA request
+  *            @arg TIM_DMA_CC4:  Capture/Compare 4 DMA request
+  *            @arg TIM_DMA_COM:   Commutation DMA request
+  *            @arg TIM_DMA_TRIGGER: Trigger DMA request
+  * @retval None
+  */
+#define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__)         ((__HANDLE__)->Instance->DIER |= (__DMA__))
+
+/** @brief  Disable the specified DMA request.
+  * @param  __HANDLE__ specifies the TIM Handle.
+  * @param  __DMA__ specifies the TIM DMA request to disable.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_DMA_UPDATE: Update DMA request
+  *            @arg TIM_DMA_CC1:   Capture/Compare 1 DMA request
+  *            @arg TIM_DMA_CC2:  Capture/Compare 2 DMA request
+  *            @arg TIM_DMA_CC3:  Capture/Compare 3 DMA request
+  *            @arg TIM_DMA_CC4:  Capture/Compare 4 DMA request
+  *            @arg TIM_DMA_COM:   Commutation DMA request
+  *            @arg TIM_DMA_TRIGGER: Trigger DMA request
+  * @retval None
+  */
+#define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__)        ((__HANDLE__)->Instance->DIER &= ~(__DMA__))
+
+/** @brief  Check whether the specified TIM interrupt flag is set or not.
+  * @param  __HANDLE__ specifies the TIM Handle.
+  * @param  __FLAG__ specifies the TIM interrupt flag to check.
+  *        This parameter can be one of the following values:
+  *            @arg TIM_FLAG_UPDATE: Update interrupt flag
+  *            @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag
+  *            @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag
+  *            @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag
+  *            @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag
+  *            @arg TIM_FLAG_COM:  Commutation interrupt flag
+  *            @arg TIM_FLAG_TRIGGER: Trigger interrupt flag
+  *            @arg TIM_FLAG_BREAK: Break interrupt flag
+  *            @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag
+  *            @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag
+  *            @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag
+  *            @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag
+  * @retval The new state of __FLAG__ (TRUE or FALSE).
+  */
+#define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__)          (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__))
+
+/** @brief  Clear the specified TIM interrupt flag.
+  * @param  __HANDLE__ specifies the TIM Handle.
+  * @param  __FLAG__ specifies the TIM interrupt flag to clear.
+  *        This parameter can be one of the following values:
+  *            @arg TIM_FLAG_UPDATE: Update interrupt flag
+  *            @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag
+  *            @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag
+  *            @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag
+  *            @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag
+  *            @arg TIM_FLAG_COM:  Commutation interrupt flag
+  *            @arg TIM_FLAG_TRIGGER: Trigger interrupt flag
+  *            @arg TIM_FLAG_BREAK: Break interrupt flag
+  *            @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag
+  *            @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag
+  *            @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag
+  *            @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag
+  * @retval The new state of __FLAG__ (TRUE or FALSE).
+  */
+#define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__)        ((__HANDLE__)->Instance->SR = ~(__FLAG__))
+
+/**
+  * @brief  Check whether the specified TIM interrupt source is enabled or not.
+  * @param  __HANDLE__ TIM handle
+  * @param  __INTERRUPT__ specifies the TIM interrupt source to check.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_IT_UPDATE: Update interrupt
+  *            @arg TIM_IT_CC1:   Capture/Compare 1 interrupt
+  *            @arg TIM_IT_CC2:  Capture/Compare 2 interrupt
+  *            @arg TIM_IT_CC3:  Capture/Compare 3 interrupt
+  *            @arg TIM_IT_CC4:  Capture/Compare 4 interrupt
+  *            @arg TIM_IT_COM:   Commutation interrupt
+  *            @arg TIM_IT_TRIGGER: Trigger interrupt
+  *            @arg TIM_IT_BREAK: Break interrupt
+  * @retval The state of TIM_IT (SET or RESET).
+  */
+#define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) \
+                                                             == (__INTERRUPT__)) ? SET : RESET)
+
+/** @brief Clear the TIM interrupt pending bits.
+  * @param  __HANDLE__ TIM handle
+  * @param  __INTERRUPT__ specifies the interrupt pending bit to clear.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_IT_UPDATE: Update interrupt
+  *            @arg TIM_IT_CC1:   Capture/Compare 1 interrupt
+  *            @arg TIM_IT_CC2:  Capture/Compare 2 interrupt
+  *            @arg TIM_IT_CC3:  Capture/Compare 3 interrupt
+  *            @arg TIM_IT_CC4:  Capture/Compare 4 interrupt
+  *            @arg TIM_IT_COM:   Commutation interrupt
+  *            @arg TIM_IT_TRIGGER: Trigger interrupt
+  *            @arg TIM_IT_BREAK: Break interrupt
+  * @retval None
+  */
+#define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__)      ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__))
+
+/**
+  * @brief  Indicates whether or not the TIM Counter is used as downcounter.
+  * @param  __HANDLE__ TIM handle.
+  * @retval False (Counter used as upcounter) or True (Counter used as downcounter)
+  * @note This macro is particularly useful to get the counting mode when the timer operates in Center-aligned mode
+  *       or Encoder mode.
+  */
+#define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__)    (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR))
+
+/**
+  * @brief  Set the TIM Prescaler on runtime.
+  * @param  __HANDLE__ TIM handle.
+  * @param  __PRESC__ specifies the Prescaler new value.
+  * @retval None
+  */
+#define __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__)       ((__HANDLE__)->Instance->PSC = (__PRESC__))
+
+/**
+  * @brief  Set the TIM Counter Register value on runtime.
+  * @param  __HANDLE__ TIM handle.
+  * @param  __COUNTER__ specifies the Counter register new value.
+  * @retval None
+  */
+#define __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__)  ((__HANDLE__)->Instance->CNT = (__COUNTER__))
+
+/**
+  * @brief  Get the TIM Counter Register value on runtime.
+  * @param  __HANDLE__ TIM handle.
+  * @retval 16-bit or 32-bit value of the timer counter register (TIMx_CNT)
+  */
+#define __HAL_TIM_GET_COUNTER(__HANDLE__)  ((__HANDLE__)->Instance->CNT)
+
+/**
+  * @brief  Set the TIM Autoreload Register value on runtime without calling another time any Init function.
+  * @param  __HANDLE__ TIM handle.
+  * @param  __AUTORELOAD__ specifies the Counter register new value.
+  * @retval None
+  */
+#define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \
+  do{                                                    \
+    (__HANDLE__)->Instance->ARR = (__AUTORELOAD__);  \
+    (__HANDLE__)->Init.Period = (__AUTORELOAD__);    \
+  } while(0)
+
+/**
+  * @brief  Get the TIM Autoreload Register value on runtime.
+  * @param  __HANDLE__ TIM handle.
+  * @retval 16-bit or 32-bit value of the timer auto-reload register(TIMx_ARR)
+  */
+#define __HAL_TIM_GET_AUTORELOAD(__HANDLE__)  ((__HANDLE__)->Instance->ARR)
+
+/**
+  * @brief  Set the TIM Clock Division value on runtime without calling another time any Init function.
+  * @param  __HANDLE__ TIM handle.
+  * @param  __CKD__ specifies the clock division value.
+  *          This parameter can be one of the following value:
+  *            @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT
+  *            @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT
+  *            @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT
+  * @retval None
+  */
+#define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \
+  do{                                                   \
+    (__HANDLE__)->Instance->CR1 &= (~TIM_CR1_CKD);  \
+    (__HANDLE__)->Instance->CR1 |= (__CKD__);       \
+    (__HANDLE__)->Init.ClockDivision = (__CKD__);   \
+  } while(0)
+
+/**
+  * @brief  Get the TIM Clock Division value on runtime.
+  * @param  __HANDLE__ TIM handle.
+  * @retval The clock division can be one of the following values:
+  *            @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT
+  *            @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT
+  *            @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT
+  */
+#define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__)  ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)
+
+/**
+  * @brief  Set the TIM Input Capture prescaler on runtime without calling another time HAL_TIM_IC_ConfigChannel()
+  *         function.
+  * @param  __HANDLE__ TIM handle.
+  * @param  __CHANNEL__ TIM Channels to be configured.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @param  __ICPSC__ specifies the Input Capture4 prescaler new value.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ICPSC_DIV1: no prescaler
+  *            @arg TIM_ICPSC_DIV2: capture is done once every 2 events
+  *            @arg TIM_ICPSC_DIV4: capture is done once every 4 events
+  *            @arg TIM_ICPSC_DIV8: capture is done once every 8 events
+  * @retval None
+  */
+#define __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__) \
+  do{                                                    \
+    TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__));  \
+    TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \
+  } while(0)
+
+/**
+  * @brief  Get the TIM Input Capture prescaler on runtime.
+  * @param  __HANDLE__ TIM handle.
+  * @param  __CHANNEL__ TIM Channels to be configured.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: get input capture 1 prescaler value
+  *            @arg TIM_CHANNEL_2: get input capture 2 prescaler value
+  *            @arg TIM_CHANNEL_3: get input capture 3 prescaler value
+  *            @arg TIM_CHANNEL_4: get input capture 4 prescaler value
+  * @retval The input capture prescaler can be one of the following values:
+  *            @arg TIM_ICPSC_DIV1: no prescaler
+  *            @arg TIM_ICPSC_DIV2: capture is done once every 2 events
+  *            @arg TIM_ICPSC_DIV4: capture is done once every 4 events
+  *            @arg TIM_ICPSC_DIV8: capture is done once every 8 events
+  */
+#define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__)  \
+  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\
+   ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8U) :\
+   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\
+   (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8U)
+
+/**
+  * @brief  Set the TIM Capture Compare Register value on runtime without calling another time ConfigChannel function.
+  * @param  __HANDLE__ TIM handle.
+  * @param  __CHANNEL__ TIM Channels to be configured.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @param  __COMPARE__ specifies the Capture Compare register new value.
+  * @retval None
+  */
+#define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \
+  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1 = (__COMPARE__)) :\
+   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2 = (__COMPARE__)) :\
+   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3 = (__COMPARE__)) :\
+   ((__HANDLE__)->Instance->CCR4 = (__COMPARE__)))
+
+/**
+  * @brief  Get the TIM Capture Compare Register value on runtime.
+  * @param  __HANDLE__ TIM handle.
+  * @param  __CHANNEL__ TIM Channel associated with the capture compare register
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: get capture/compare 1 register value
+  *            @arg TIM_CHANNEL_2: get capture/compare 2 register value
+  *            @arg TIM_CHANNEL_3: get capture/compare 3 register value
+  *            @arg TIM_CHANNEL_4: get capture/compare 4 register value
+  * @retval 16-bit or 32-bit value of the capture/compare register (TIMx_CCRy)
+  */
+#define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \
+  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1) :\
+   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2) :\
+   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3) :\
+   ((__HANDLE__)->Instance->CCR4))
+
+/**
+  * @brief  Set the TIM Output compare preload.
+  * @param  __HANDLE__ TIM handle.
+  * @param  __CHANNEL__ TIM Channels to be configured.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @retval None
+  */
+#define __HAL_TIM_ENABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__)    \
+  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1PE) :\
+   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2PE) :\
+   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3PE) :\
+   ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4PE))
+
+/**
+  * @brief  Reset the TIM Output compare preload.
+  * @param  __HANDLE__ TIM handle.
+  * @param  __CHANNEL__ TIM Channels to be configured.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @retval None
+  */
+#define __HAL_TIM_DISABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__)    \
+  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1PE) :\
+   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2PE) :\
+   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3PE) :\
+   ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4PE))
+
+/**
+  * @brief  Enable fast mode for a given channel.
+  * @param  __HANDLE__ TIM handle.
+  * @param  __CHANNEL__ TIM Channels to be configured.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @note  When fast mode is enabled an active edge on the trigger input acts
+  *        like a compare match on CCx output. Delay to sample the trigger
+  *        input and to activate CCx output is reduced to 3 clock cycles.
+  * @note  Fast mode acts only if the channel is configured in PWM1 or PWM2 mode.
+  * @retval None
+  */
+#define __HAL_TIM_ENABLE_OCxFAST(__HANDLE__, __CHANNEL__)    \
+  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1FE) :\
+   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2FE) :\
+   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3FE) :\
+   ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4FE))
+
+/**
+  * @brief  Disable fast mode for a given channel.
+  * @param  __HANDLE__ TIM handle.
+  * @param  __CHANNEL__ TIM Channels to be configured.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @note  When fast mode is disabled CCx output behaves normally depending
+  *        on counter and CCRx values even when the trigger is ON. The minimum
+  *        delay to activate CCx output when an active edge occurs on the
+  *        trigger input is 5 clock cycles.
+  * @retval None
+  */
+#define __HAL_TIM_DISABLE_OCxFAST(__HANDLE__, __CHANNEL__)    \
+  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE) :\
+   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE) :\
+   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE) :\
+   ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE))
+
+/**
+  * @brief  Set the Update Request Source (URS) bit of the TIMx_CR1 register.
+  * @param  __HANDLE__ TIM handle.
+  * @note  When the URS bit of the TIMx_CR1 register is set, only counter
+  *        overflow/underflow generates an update interrupt or DMA request (if
+  *        enabled)
+  * @retval None
+  */
+#define __HAL_TIM_URS_ENABLE(__HANDLE__)  ((__HANDLE__)->Instance->CR1|= TIM_CR1_URS)
+
+/**
+  * @brief  Reset the Update Request Source (URS) bit of the TIMx_CR1 register.
+  * @param  __HANDLE__ TIM handle.
+  * @note  When the URS bit of the TIMx_CR1 register is reset, any of the
+  *        following events generate an update interrupt or DMA request (if
+  *        enabled):
+  *           _ Counter overflow underflow
+  *           _ Setting the UG bit
+  *           _ Update generation through the slave mode controller
+  * @retval None
+  */
+#define __HAL_TIM_URS_DISABLE(__HANDLE__)  ((__HANDLE__)->Instance->CR1&=~TIM_CR1_URS)
+
+/**
+  * @brief  Set the TIM Capture x input polarity on runtime.
+  * @param  __HANDLE__ TIM handle.
+  * @param  __CHANNEL__ TIM Channels to be configured.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @param  __POLARITY__ Polarity for TIx source
+  *            @arg TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge
+  *            @arg TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge
+  *            @arg TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge
+  * @retval None
+  */
+#define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__)    \
+  do{                                                                     \
+    TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__));               \
+    TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \
+  }while(0)
+
+/** @brief  Select the Capture/compare DMA request source.
+  * @param  __HANDLE__ specifies the TIM Handle.
+  * @param  __CCDMA__ specifies Capture/compare DMA request source
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CCDMAREQUEST_CC: CCx DMA request generated on Capture/Compare event
+  *            @arg TIM_CCDMAREQUEST_UPDATE: CCx DMA request generated on Update event
+  * @retval None
+  */
+#define __HAL_TIM_SELECT_CCDMAREQUEST(__HANDLE__, __CCDMA__)    \
+  MODIFY_REG((__HANDLE__)->Instance->CR2, TIM_CR2_CCDS, (__CCDMA__))
+
+/**
+  * @}
+  */
+/* End of exported macros ----------------------------------------------------*/
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup TIM_Private_Constants TIM Private Constants
+  * @{
+  */
+/* The counter of a timer instance is disabled only if all the CCx and CCxN
+   channels have been disabled */
+#define TIM_CCER_CCxE_MASK  ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E))
+#define TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE))
+/**
+  * @}
+  */
+/* End of private constants --------------------------------------------------*/
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup TIM_Private_Macros TIM Private Macros
+  * @{
+  */
+#define IS_TIM_CLEARINPUT_SOURCE(__MODE__)  (((__MODE__) == TIM_CLEARINPUTSOURCE_NONE)      || \
+                                             ((__MODE__) == TIM_CLEARINPUTSOURCE_ETR))
+
+#define IS_TIM_DMA_BASE(__BASE__) (((__BASE__) == TIM_DMABASE_CR1)   || \
+                                   ((__BASE__) == TIM_DMABASE_CR2)   || \
+                                   ((__BASE__) == TIM_DMABASE_SMCR)  || \
+                                   ((__BASE__) == TIM_DMABASE_DIER)  || \
+                                   ((__BASE__) == TIM_DMABASE_SR)    || \
+                                   ((__BASE__) == TIM_DMABASE_EGR)   || \
+                                   ((__BASE__) == TIM_DMABASE_CCMR1) || \
+                                   ((__BASE__) == TIM_DMABASE_CCMR2) || \
+                                   ((__BASE__) == TIM_DMABASE_CCER)  || \
+                                   ((__BASE__) == TIM_DMABASE_CNT)   || \
+                                   ((__BASE__) == TIM_DMABASE_PSC)   || \
+                                   ((__BASE__) == TIM_DMABASE_ARR)   || \
+                                   ((__BASE__) == TIM_DMABASE_RCR)   || \
+                                   ((__BASE__) == TIM_DMABASE_CCR1)  || \
+                                   ((__BASE__) == TIM_DMABASE_CCR2)  || \
+                                   ((__BASE__) == TIM_DMABASE_CCR3)  || \
+                                   ((__BASE__) == TIM_DMABASE_CCR4)  || \
+                                   ((__BASE__) == TIM_DMABASE_BDTR))
+
+#define IS_TIM_EVENT_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFFFF00U) == 0x00000000U) && ((__SOURCE__) != 0x00000000U))
+
+#define IS_TIM_COUNTER_MODE(__MODE__)      (((__MODE__) == TIM_COUNTERMODE_UP)              || \
+                                            ((__MODE__) == TIM_COUNTERMODE_DOWN)            || \
+                                            ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED1)  || \
+                                            ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED2)  || \
+                                            ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED3))
+
+#define IS_TIM_CLOCKDIVISION_DIV(__DIV__)  (((__DIV__) == TIM_CLOCKDIVISION_DIV1) || \
+                                            ((__DIV__) == TIM_CLOCKDIVISION_DIV2) || \
+                                            ((__DIV__) == TIM_CLOCKDIVISION_DIV4))
+
+#define IS_TIM_AUTORELOAD_PRELOAD(PRELOAD) (((PRELOAD) == TIM_AUTORELOAD_PRELOAD_DISABLE) || \
+                                            ((PRELOAD) == TIM_AUTORELOAD_PRELOAD_ENABLE))
+
+#define IS_TIM_FAST_STATE(__STATE__)       (((__STATE__) == TIM_OCFAST_DISABLE) || \
+                                            ((__STATE__) == TIM_OCFAST_ENABLE))
+
+#define IS_TIM_OC_POLARITY(__POLARITY__)   (((__POLARITY__) == TIM_OCPOLARITY_HIGH) || \
+                                            ((__POLARITY__) == TIM_OCPOLARITY_LOW))
+
+#define IS_TIM_OCN_POLARITY(__POLARITY__)  (((__POLARITY__) == TIM_OCNPOLARITY_HIGH) || \
+                                            ((__POLARITY__) == TIM_OCNPOLARITY_LOW))
+
+#define IS_TIM_OCIDLE_STATE(__STATE__)     (((__STATE__) == TIM_OCIDLESTATE_SET) || \
+                                            ((__STATE__) == TIM_OCIDLESTATE_RESET))
+
+#define IS_TIM_OCNIDLE_STATE(__STATE__)    (((__STATE__) == TIM_OCNIDLESTATE_SET) || \
+                                            ((__STATE__) == TIM_OCNIDLESTATE_RESET))
+
+#define IS_TIM_ENCODERINPUT_POLARITY(__POLARITY__)   (((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_RISING)   || \
+                                                      ((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_FALLING))
+
+#define IS_TIM_IC_POLARITY(__POLARITY__)   (((__POLARITY__) == TIM_ICPOLARITY_RISING)   || \
+                                            ((__POLARITY__) == TIM_ICPOLARITY_FALLING)  || \
+                                            ((__POLARITY__) == TIM_ICPOLARITY_BOTHEDGE))
+
+#define IS_TIM_IC_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_ICSELECTION_DIRECTTI) || \
+                                            ((__SELECTION__) == TIM_ICSELECTION_INDIRECTTI) || \
+                                            ((__SELECTION__) == TIM_ICSELECTION_TRC))
+
+#define IS_TIM_IC_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_ICPSC_DIV1) || \
+                                            ((__PRESCALER__) == TIM_ICPSC_DIV2) || \
+                                            ((__PRESCALER__) == TIM_ICPSC_DIV4) || \
+                                            ((__PRESCALER__) == TIM_ICPSC_DIV8))
+
+#define IS_TIM_OPM_MODE(__MODE__)          (((__MODE__) == TIM_OPMODE_SINGLE) || \
+                                            ((__MODE__) == TIM_OPMODE_REPETITIVE))
+
+#define IS_TIM_ENCODER_MODE(__MODE__)      (((__MODE__) == TIM_ENCODERMODE_TI1) || \
+                                            ((__MODE__) == TIM_ENCODERMODE_TI2) || \
+                                            ((__MODE__) == TIM_ENCODERMODE_TI12))
+
+#define IS_TIM_DMA_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFF80FFU) == 0x00000000U) && ((__SOURCE__) != 0x00000000U))
+
+#define IS_TIM_CHANNELS(__CHANNEL__)       (((__CHANNEL__) == TIM_CHANNEL_1) || \
+                                            ((__CHANNEL__) == TIM_CHANNEL_2) || \
+                                            ((__CHANNEL__) == TIM_CHANNEL_3) || \
+                                            ((__CHANNEL__) == TIM_CHANNEL_4) || \
+                                            ((__CHANNEL__) == TIM_CHANNEL_ALL))
+
+#define IS_TIM_OPM_CHANNELS(__CHANNEL__)   (((__CHANNEL__) == TIM_CHANNEL_1) || \
+                                            ((__CHANNEL__) == TIM_CHANNEL_2))
+
+#define IS_TIM_COMPLEMENTARY_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \
+                                                    ((__CHANNEL__) == TIM_CHANNEL_2) || \
+                                                    ((__CHANNEL__) == TIM_CHANNEL_3))
+
+#define IS_TIM_CLOCKSOURCE(__CLOCK__) (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \
+                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \
+                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \
+                                       ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED)    || \
+                                       ((__CLOCK__) == TIM_CLOCKSOURCE_TI1)      || \
+                                       ((__CLOCK__) == TIM_CLOCKSOURCE_TI2)      || \
+                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0)     || \
+                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1)     || \
+                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2)     || \
+                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3))
+
+#define IS_TIM_CLOCKPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLOCKPOLARITY_INVERTED)    || \
+                                            ((__POLARITY__) == TIM_CLOCKPOLARITY_NONINVERTED) || \
+                                            ((__POLARITY__) == TIM_CLOCKPOLARITY_RISING)      || \
+                                            ((__POLARITY__) == TIM_CLOCKPOLARITY_FALLING)     || \
+                                            ((__POLARITY__) == TIM_CLOCKPOLARITY_BOTHEDGE))
+
+#define IS_TIM_CLOCKPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV1) || \
+                                              ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV2) || \
+                                              ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV4) || \
+                                              ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV8))
+
+#define IS_TIM_CLOCKFILTER(__ICFILTER__)      ((__ICFILTER__) <= 0xFU)
+
+#define IS_TIM_CLEARINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLEARINPUTPOLARITY_INVERTED) || \
+                                                  ((__POLARITY__) == TIM_CLEARINPUTPOLARITY_NONINVERTED))
+
+#define IS_TIM_CLEARINPUT_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV1) || \
+                                                    ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV2) || \
+                                                    ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV4) || \
+                                                    ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV8))
+
+#define IS_TIM_CLEARINPUT_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
+
+#define IS_TIM_OSSR_STATE(__STATE__)       (((__STATE__) == TIM_OSSR_ENABLE) || \
+                                            ((__STATE__) == TIM_OSSR_DISABLE))
+
+#define IS_TIM_OSSI_STATE(__STATE__)       (((__STATE__) == TIM_OSSI_ENABLE) || \
+                                            ((__STATE__) == TIM_OSSI_DISABLE))
+
+#define IS_TIM_LOCK_LEVEL(__LEVEL__)       (((__LEVEL__) == TIM_LOCKLEVEL_OFF) || \
+                                            ((__LEVEL__) == TIM_LOCKLEVEL_1)   || \
+                                            ((__LEVEL__) == TIM_LOCKLEVEL_2)   || \
+                                            ((__LEVEL__) == TIM_LOCKLEVEL_3))
+
+#define IS_TIM_BREAK_FILTER(__BRKFILTER__) ((__BRKFILTER__) <= 0xFUL)
+
+
+#define IS_TIM_BREAK_STATE(__STATE__)      (((__STATE__) == TIM_BREAK_ENABLE) || \
+                                            ((__STATE__) == TIM_BREAK_DISABLE))
+
+#define IS_TIM_BREAK_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAKPOLARITY_LOW) || \
+                                             ((__POLARITY__) == TIM_BREAKPOLARITY_HIGH))
+
+#define IS_TIM_AUTOMATIC_OUTPUT_STATE(__STATE__) (((__STATE__) == TIM_AUTOMATICOUTPUT_ENABLE) || \
+                                                  ((__STATE__) == TIM_AUTOMATICOUTPUT_DISABLE))
+
+#define IS_TIM_TRGO_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO_RESET)  || \
+                                        ((__SOURCE__) == TIM_TRGO_ENABLE) || \
+                                        ((__SOURCE__) == TIM_TRGO_UPDATE) || \
+                                        ((__SOURCE__) == TIM_TRGO_OC1)    || \
+                                        ((__SOURCE__) == TIM_TRGO_OC1REF) || \
+                                        ((__SOURCE__) == TIM_TRGO_OC2REF) || \
+                                        ((__SOURCE__) == TIM_TRGO_OC3REF) || \
+                                        ((__SOURCE__) == TIM_TRGO_OC4REF))
+
+#define IS_TIM_MSM_STATE(__STATE__)      (((__STATE__) == TIM_MASTERSLAVEMODE_ENABLE) || \
+                                          ((__STATE__) == TIM_MASTERSLAVEMODE_DISABLE))
+
+#define IS_TIM_SLAVE_MODE(__MODE__) (((__MODE__) == TIM_SLAVEMODE_DISABLE)   || \
+                                     ((__MODE__) == TIM_SLAVEMODE_RESET)     || \
+                                     ((__MODE__) == TIM_SLAVEMODE_GATED)     || \
+                                     ((__MODE__) == TIM_SLAVEMODE_TRIGGER)   || \
+                                     ((__MODE__) == TIM_SLAVEMODE_EXTERNAL1))
+
+#define IS_TIM_PWM_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_PWM1)               || \
+                                   ((__MODE__) == TIM_OCMODE_PWM2))
+
+#define IS_TIM_OC_MODE(__MODE__)  (((__MODE__) == TIM_OCMODE_TIMING)             || \
+                                   ((__MODE__) == TIM_OCMODE_ACTIVE)             || \
+                                   ((__MODE__) == TIM_OCMODE_INACTIVE)           || \
+                                   ((__MODE__) == TIM_OCMODE_TOGGLE)             || \
+                                   ((__MODE__) == TIM_OCMODE_FORCED_ACTIVE)      || \
+                                   ((__MODE__) == TIM_OCMODE_FORCED_INACTIVE))
+
+#define IS_TIM_TRIGGER_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0)    || \
+                                                 ((__SELECTION__) == TIM_TS_ITR1)    || \
+                                                 ((__SELECTION__) == TIM_TS_ITR2)    || \
+                                                 ((__SELECTION__) == TIM_TS_ITR3)    || \
+                                                 ((__SELECTION__) == TIM_TS_TI1F_ED) || \
+                                                 ((__SELECTION__) == TIM_TS_TI1FP1)  || \
+                                                 ((__SELECTION__) == TIM_TS_TI2FP2)  || \
+                                                 ((__SELECTION__) == TIM_TS_ETRF))
+
+#define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \
+                                                               ((__SELECTION__) == TIM_TS_ITR1) || \
+                                                               ((__SELECTION__) == TIM_TS_ITR2) || \
+                                                               ((__SELECTION__) == TIM_TS_ITR3) || \
+                                                               ((__SELECTION__) == TIM_TS_NONE))
+
+#define IS_TIM_TRIGGERPOLARITY(__POLARITY__)   (((__POLARITY__) == TIM_TRIGGERPOLARITY_INVERTED   ) || \
+                                                ((__POLARITY__) == TIM_TRIGGERPOLARITY_NONINVERTED) || \
+                                                ((__POLARITY__) == TIM_TRIGGERPOLARITY_RISING     ) || \
+                                                ((__POLARITY__) == TIM_TRIGGERPOLARITY_FALLING    ) || \
+                                                ((__POLARITY__) == TIM_TRIGGERPOLARITY_BOTHEDGE   ))
+
+#define IS_TIM_TRIGGERPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV1) || \
+                                                ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV2) || \
+                                                ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV4) || \
+                                                ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV8))
+
+#define IS_TIM_TRIGGERFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
+
+#define IS_TIM_TI1SELECTION(__TI1SELECTION__)  (((__TI1SELECTION__) == TIM_TI1SELECTION_CH1) || \
+                                                ((__TI1SELECTION__) == TIM_TI1SELECTION_XORCOMBINATION))
+
+#define IS_TIM_DMA_LENGTH(__LENGTH__)      (((__LENGTH__) == TIM_DMABURSTLENGTH_1TRANSFER)   || \
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_2TRANSFERS)  || \
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_3TRANSFERS)  || \
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_4TRANSFERS)  || \
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_5TRANSFERS)  || \
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_6TRANSFERS)  || \
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_7TRANSFERS)  || \
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_8TRANSFERS)  || \
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_9TRANSFERS)  || \
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_10TRANSFERS) || \
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_11TRANSFERS) || \
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_12TRANSFERS) || \
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_13TRANSFERS) || \
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_14TRANSFERS) || \
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_15TRANSFERS) || \
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_16TRANSFERS) || \
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_17TRANSFERS) || \
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_18TRANSFERS))
+
+#define IS_TIM_DMA_DATA_LENGTH(LENGTH) (((LENGTH) >= 0x1U) && ((LENGTH) < 0x10000U))
+
+#define IS_TIM_IC_FILTER(__ICFILTER__)   ((__ICFILTER__) <= 0xFU)
+
+#define IS_TIM_DEADTIME(__DEADTIME__)    ((__DEADTIME__) <= 0xFFU)
+
+#define IS_TIM_SLAVEMODE_TRIGGER_ENABLED(__TRIGGER__) ((__TRIGGER__) == TIM_SLAVEMODE_TRIGGER)
+
+#define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \
+  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\
+   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8U)) :\
+   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\
+   ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8U)))
+
+#define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \
+  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC) :\
+   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC) :\
+   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC) :\
+   ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC))
+
+#define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
+  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\
+   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4U)) :\
+   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8U)) :\
+   ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12U))))
+
+#define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \
+  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\
+   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\
+   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\
+   ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP)))
+
+#define TIM_CHANNEL_STATE_GET(__HANDLE__, __CHANNEL__)\
+  (((__CHANNEL__) == TIM_CHANNEL_1) ? (__HANDLE__)->ChannelState[0] :\
+   ((__CHANNEL__) == TIM_CHANNEL_2) ? (__HANDLE__)->ChannelState[1] :\
+   ((__CHANNEL__) == TIM_CHANNEL_3) ? (__HANDLE__)->ChannelState[2] :\
+   (__HANDLE__)->ChannelState[3])
+
+#define TIM_CHANNEL_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__) \
+  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->ChannelState[0] = (__CHANNEL_STATE__)) :\
+   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->ChannelState[1] = (__CHANNEL_STATE__)) :\
+   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->ChannelState[2] = (__CHANNEL_STATE__)) :\
+   ((__HANDLE__)->ChannelState[3] = (__CHANNEL_STATE__)))
+
+#define TIM_CHANNEL_STATE_SET_ALL(__HANDLE__,  __CHANNEL_STATE__) do { \
+                                                                       (__HANDLE__)->ChannelState[0]  = (__CHANNEL_STATE__);  \
+                                                                       (__HANDLE__)->ChannelState[1]  = (__CHANNEL_STATE__);  \
+                                                                       (__HANDLE__)->ChannelState[2]  = (__CHANNEL_STATE__);  \
+                                                                       (__HANDLE__)->ChannelState[3]  = (__CHANNEL_STATE__);  \
+                                                                     } while(0)
+
+#define TIM_CHANNEL_N_STATE_GET(__HANDLE__, __CHANNEL__)\
+  (((__CHANNEL__) == TIM_CHANNEL_1) ? (__HANDLE__)->ChannelNState[0] :\
+   ((__CHANNEL__) == TIM_CHANNEL_2) ? (__HANDLE__)->ChannelNState[1] :\
+   ((__CHANNEL__) == TIM_CHANNEL_3) ? (__HANDLE__)->ChannelNState[2] :\
+   (__HANDLE__)->ChannelNState[3])
+
+#define TIM_CHANNEL_N_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__) \
+  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->ChannelNState[0] = (__CHANNEL_STATE__)) :\
+   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->ChannelNState[1] = (__CHANNEL_STATE__)) :\
+   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->ChannelNState[2] = (__CHANNEL_STATE__)) :\
+   ((__HANDLE__)->ChannelNState[3] = (__CHANNEL_STATE__)))
+
+#define TIM_CHANNEL_N_STATE_SET_ALL(__HANDLE__,  __CHANNEL_STATE__) do { \
+                                                                         (__HANDLE__)->ChannelNState[0] = \
+                                                                         (__CHANNEL_STATE__);  \
+                                                                         (__HANDLE__)->ChannelNState[1] = \
+                                                                         (__CHANNEL_STATE__);  \
+                                                                         (__HANDLE__)->ChannelNState[2] = \
+                                                                         (__CHANNEL_STATE__);  \
+                                                                         (__HANDLE__)->ChannelNState[3] = \
+                                                                         (__CHANNEL_STATE__);  \
+                                                                       } while(0)
+
+/**
+  * @}
+  */
+/* End of private macros -----------------------------------------------------*/
+
+/* Include TIM HAL Extended module */
+#include "stm32f4xx_hal_tim_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup TIM_Exported_Functions TIM Exported Functions
+  * @{
+  */
+
+/** @addtogroup TIM_Exported_Functions_Group1 TIM Time Base functions
+  *  @brief   Time Base functions
+  * @{
+  */
+/* Time Base functions ********************************************************/
+HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim);
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim);
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim);
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length);
+HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim);
+/**
+  * @}
+  */
+
+/** @addtogroup TIM_Exported_Functions_Group2 TIM Output Compare functions
+  *  @brief   TIM Output Compare functions
+  * @{
+  */
+/* Timer Output Compare functions *********************************************/
+HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim);
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
+HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
+/**
+  * @}
+  */
+
+/** @addtogroup TIM_Exported_Functions_Group3 TIM PWM functions
+  *  @brief   TIM PWM functions
+  * @{
+  */
+/* Timer PWM functions ********************************************************/
+HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim);
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
+HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
+/**
+  * @}
+  */
+
+/** @addtogroup TIM_Exported_Functions_Group4 TIM Input Capture functions
+  *  @brief   TIM Input Capture functions
+  * @{
+  */
+/* Timer Input Capture functions **********************************************/
+HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim);
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
+HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
+/**
+  * @}
+  */
+
+/** @addtogroup TIM_Exported_Functions_Group5 TIM One Pulse functions
+  *  @brief   TIM One Pulse functions
+  * @{
+  */
+/* Timer One Pulse functions **************************************************/
+HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode);
+HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim);
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
+HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
+HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
+/**
+  * @}
+  */
+
+/** @addtogroup TIM_Exported_Functions_Group6 TIM Encoder functions
+  *  @brief   TIM Encoder functions
+  * @{
+  */
+/* Timer Encoder functions ****************************************************/
+HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim,  TIM_Encoder_InitTypeDef *sConfig);
+HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim);
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1,
+                                            uint32_t *pData2, uint16_t Length);
+HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
+/**
+  * @}
+  */
+
+/** @addtogroup TIM_Exported_Functions_Group7 TIM IRQ handler management
+  *  @brief   IRQ handler management
+  * @{
+  */
+/* Interrupt Handler functions  ***********************************************/
+void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim);
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Exported_Functions_Group8 TIM Peripheral Control functions
+  *  @brief   Peripheral Control functions
+  * @{
+  */
+/* Control functions  *********************************************************/
+HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef *sConfig, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig,
+                                                 uint32_t OutputChannel,  uint32_t InputChannel);
+HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef *sClearInputConfig,
+                                           uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig);
+HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection);
+HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig);
+HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig);
+HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
+                                              uint32_t BurstRequestSrc, uint32_t  *BurstBuffer, uint32_t  BurstLength);
+HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
+                                                   uint32_t BurstRequestSrc, uint32_t *BurstBuffer,
+                                                   uint32_t BurstLength,  uint32_t DataLength);
+HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
+HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
+                                             uint32_t BurstRequestSrc, uint32_t  *BurstBuffer, uint32_t  BurstLength);
+HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
+                                                  uint32_t BurstRequestSrc, uint32_t  *BurstBuffer,
+                                                  uint32_t  BurstLength, uint32_t  DataLength);
+HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
+HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource);
+uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel);
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions
+  *  @brief   TIM Callbacks functions
+  * @{
+  */
+/* Callback in non blocking modes (Interrupt and DMA) *************************/
+void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim);
+void HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef *htim);
+void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim);
+void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim);
+void HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef *htim);
+void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim);
+void HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef *htim);
+void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim);
+void HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef *htim);
+void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim);
+
+/* Callbacks Register/UnRegister functions  ***********************************/
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID,
+                                           pTIM_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Exported_Functions_Group10 TIM Peripheral State functions
+  *  @brief  Peripheral State functions
+  * @{
+  */
+/* Peripheral State functions  ************************************************/
+HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim);
+HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim);
+HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim);
+HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim);
+HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim);
+HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim);
+
+/* Peripheral Channel state functions  ************************************************/
+HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(TIM_HandleTypeDef *htim);
+HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(TIM_HandleTypeDef *htim,  uint32_t Channel);
+HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(TIM_HandleTypeDef *htim);
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+/* End of exported functions -------------------------------------------------*/
+
+/* Private functions----------------------------------------------------------*/
+/** @defgroup TIM_Private_Functions TIM Private Functions
+  * @{
+  */
+void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure);
+void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter);
+void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
+void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler,
+                       uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter);
+
+void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma);
+void TIM_DMAError(DMA_HandleTypeDef *hdma);
+void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma);
+void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma);
+void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState);
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+void TIM_ResetCallback(TIM_HandleTypeDef *htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+/* End of private functions --------------------------------------------------*/
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32F4xx_HAL_TIM_H */
diff --git a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h
new file mode 100644
index 0000000..a43611b
--- /dev/null
+++ b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h
@@ -0,0 +1,354 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hal_tim_ex.h
+  * @author  MCD Application Team
+  * @brief   Header file of TIM HAL Extended module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2016 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32F4xx_HAL_TIM_EX_H
+#define STM32F4xx_HAL_TIM_EX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup TIMEx
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup TIMEx_Exported_Types TIM Extended Exported Types
+  * @{
+  */
+
+/**
+  * @brief  TIM Hall sensor Configuration Structure definition
+  */
+
+typedef struct
+{
+  uint32_t IC1Polarity;         /*!< Specifies the active edge of the input signal.
+                                     This parameter can be a value of @ref TIM_Input_Capture_Polarity */
+
+  uint32_t IC1Prescaler;        /*!< Specifies the Input Capture Prescaler.
+                                     This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
+
+  uint32_t IC1Filter;           /*!< Specifies the input capture filter.
+                                     This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
+
+  uint32_t Commutation_Delay;   /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
+                                     This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
+} TIM_HallSensor_InitTypeDef;
+/**
+  * @}
+  */
+/* End of exported types -----------------------------------------------------*/
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup TIMEx_Exported_Constants TIM Extended Exported Constants
+  * @{
+  */
+
+/** @defgroup TIMEx_Remap TIM Extended Remapping
+  * @{
+  */
+#if defined (TIM2)
+#if defined(TIM8)
+#define TIM_TIM2_TIM8_TRGO                     0x00000000U                              /*!< TIM2 ITR1 is connected to TIM8 TRGO */
+#else
+#define TIM_TIM2_ETH_PTP                       TIM_OR_ITR1_RMP_0                        /*!< TIM2 ITR1 is connected to PTP trigger output */
+#endif /*  TIM8 */
+#define TIM_TIM2_USBFS_SOF                     TIM_OR_ITR1_RMP_1                        /*!< TIM2 ITR1 is connected to OTG FS SOF */
+#define TIM_TIM2_USBHS_SOF                     (TIM_OR_ITR1_RMP_1 | TIM_OR_ITR1_RMP_0)  /*!< TIM2 ITR1 is connected to OTG HS SOF */
+#endif /* TIM2 */
+
+#define TIM_TIM5_GPIO                          0x00000000U                              /*!< TIM5 TI4 is connected to GPIO */
+#define TIM_TIM5_LSI                           TIM_OR_TI4_RMP_0                         /*!< TIM5 TI4 is connected to LSI */
+#define TIM_TIM5_LSE                           TIM_OR_TI4_RMP_1                         /*!< TIM5 TI4 is connected to LSE */
+#define TIM_TIM5_RTC                           (TIM_OR_TI4_RMP_1 | TIM_OR_TI4_RMP_0)    /*!< TIM5 TI4 is connected to the RTC wakeup interrupt */
+
+#define TIM_TIM11_GPIO                         0x00000000U                              /*!< TIM11 TI1 is connected to GPIO */
+#define TIM_TIM11_HSE                          TIM_OR_TI1_RMP_1                         /*!< TIM11 TI1 is connected to HSE_RTC clock */
+#if defined(SPDIFRX)
+#define TIM_TIM11_SPDIFRX                      TIM_OR_TI1_RMP_0                         /*!< TIM11 TI1 is connected to SPDIFRX_FRAME_SYNC */
+#endif /* SPDIFRX*/
+
+#if defined(LPTIM_OR_TIM1_ITR2_RMP) && defined(LPTIM_OR_TIM5_ITR1_RMP) && defined(LPTIM_OR_TIM5_ITR1_RMP)
+#define LPTIM_REMAP_MASK                       0x10000000U
+
+#define TIM_TIM9_TIM3_TRGO                     LPTIM_REMAP_MASK                             /*!< TIM9 ITR1 is connected to TIM3 TRGO */
+#define TIM_TIM9_LPTIM                         (LPTIM_REMAP_MASK | LPTIM_OR_TIM9_ITR1_RMP)  /*!< TIM9 ITR1 is connected to LPTIM1 output */
+
+#define TIM_TIM5_TIM3_TRGO                     LPTIM_REMAP_MASK                             /*!< TIM5 ITR1 is connected to TIM3 TRGO */
+#define TIM_TIM5_LPTIM                         (LPTIM_REMAP_MASK | LPTIM_OR_TIM5_ITR1_RMP)  /*!< TIM5 ITR1 is connected to LPTIM1 output */
+
+#define TIM_TIM1_TIM3_TRGO                     LPTIM_REMAP_MASK                             /*!< TIM1 ITR2 is connected to TIM3 TRGO */
+#define TIM_TIM1_LPTIM                         (LPTIM_REMAP_MASK | LPTIM_OR_TIM1_ITR2_RMP)  /*!< TIM1 ITR2 is connected to LPTIM1 output */
+#endif /* LPTIM_OR_TIM1_ITR2_RMP &&  LPTIM_OR_TIM5_ITR1_RMP && LPTIM_OR_TIM5_ITR1_RMP */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+/* End of exported constants -------------------------------------------------*/
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup TIMEx_Exported_Macros TIM Extended Exported Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+/* End of exported macro -----------------------------------------------------*/
+
+/* Private macro -------------------------------------------------------------*/
+/** @defgroup TIMEx_Private_Macros TIM Extended Private Macros
+  * @{
+  */
+#if defined(SPDIFRX)
+#define IS_TIM_REMAP(INSTANCE, TIM_REMAP)                                 \
+  ((((INSTANCE) == TIM2)  && (((TIM_REMAP) == TIM_TIM2_TIM8_TRGO)      || \
+                              ((TIM_REMAP) == TIM_TIM2_USBFS_SOF)      || \
+                              ((TIM_REMAP) == TIM_TIM2_USBHS_SOF)))    || \
+   (((INSTANCE) == TIM5)  && (((TIM_REMAP) == TIM_TIM5_GPIO)           || \
+                              ((TIM_REMAP) == TIM_TIM5_LSI)            || \
+                              ((TIM_REMAP) == TIM_TIM5_LSE)            || \
+                              ((TIM_REMAP) == TIM_TIM5_RTC)))          || \
+   (((INSTANCE) == TIM11) && (((TIM_REMAP) == TIM_TIM11_GPIO)          || \
+                              ((TIM_REMAP) == TIM_TIM11_SPDIFRX)       || \
+                              ((TIM_REMAP) == TIM_TIM11_HSE))))
+#elif defined(TIM2)
+#if defined(LPTIM_OR_TIM1_ITR2_RMP) && defined(LPTIM_OR_TIM5_ITR1_RMP) && defined(LPTIM_OR_TIM5_ITR1_RMP)
+#define IS_TIM_REMAP(INSTANCE, TIM_REMAP)                                 \
+  ((((INSTANCE) == TIM2)  && (((TIM_REMAP) == TIM_TIM2_TIM8_TRGO)      || \
+                              ((TIM_REMAP) == TIM_TIM2_USBFS_SOF)      || \
+                              ((TIM_REMAP) == TIM_TIM2_USBHS_SOF)))    || \
+   (((INSTANCE) == TIM5)  && (((TIM_REMAP) == TIM_TIM5_GPIO)           || \
+                              ((TIM_REMAP) == TIM_TIM5_LSI)            || \
+                              ((TIM_REMAP) == TIM_TIM5_LSE)            || \
+                              ((TIM_REMAP) == TIM_TIM5_RTC)))          || \
+   (((INSTANCE) == TIM11) && (((TIM_REMAP) == TIM_TIM11_GPIO)          || \
+                              ((TIM_REMAP) == TIM_TIM11_HSE)))         || \
+   (((INSTANCE) == TIM1)  && (((TIM_REMAP) == TIM_TIM1_TIM3_TRGO)      || \
+                              ((TIM_REMAP) == TIM_TIM1_LPTIM)))        || \
+   (((INSTANCE) == TIM5)  && (((TIM_REMAP) == TIM_TIM5_TIM3_TRGO)      || \
+                              ((TIM_REMAP) == TIM_TIM5_LPTIM)))        || \
+   (((INSTANCE) == TIM9)  && (((TIM_REMAP) == TIM_TIM9_TIM3_TRGO)      || \
+                              ((TIM_REMAP) == TIM_TIM9_LPTIM))))
+#elif defined(TIM8)
+#define IS_TIM_REMAP(INSTANCE, TIM_REMAP)                                 \
+  ((((INSTANCE) == TIM2)  && (((TIM_REMAP) == TIM_TIM2_TIM8_TRGO)      || \
+                              ((TIM_REMAP) == TIM_TIM2_USBFS_SOF)      || \
+                              ((TIM_REMAP) == TIM_TIM2_USBHS_SOF)))    || \
+   (((INSTANCE) == TIM5)  && (((TIM_REMAP) == TIM_TIM5_GPIO)           || \
+                              ((TIM_REMAP) == TIM_TIM5_LSI)            || \
+                              ((TIM_REMAP) == TIM_TIM5_LSE)            || \
+                              ((TIM_REMAP) == TIM_TIM5_RTC)))          || \
+   (((INSTANCE) == TIM11) && (((TIM_REMAP) == TIM_TIM11_GPIO)          || \
+                              ((TIM_REMAP) == TIM_TIM11_HSE))))
+#else
+#define IS_TIM_REMAP(INSTANCE, TIM_REMAP)                                 \
+  ((((INSTANCE) == TIM2)  && (((TIM_REMAP) == TIM_TIM2_ETH_PTP)        || \
+                              ((TIM_REMAP) == TIM_TIM2_USBFS_SOF)      || \
+                              ((TIM_REMAP) == TIM_TIM2_USBHS_SOF)))    || \
+   (((INSTANCE) == TIM5)  && (((TIM_REMAP) == TIM_TIM5_GPIO)           || \
+                              ((TIM_REMAP) == TIM_TIM5_LSI)            || \
+                              ((TIM_REMAP) == TIM_TIM5_LSE)            || \
+                              ((TIM_REMAP) == TIM_TIM5_RTC)))          || \
+   (((INSTANCE) == TIM11) && (((TIM_REMAP) == TIM_TIM11_GPIO)          || \
+                              ((TIM_REMAP) == TIM_TIM11_HSE))))
+#endif /* LPTIM_OR_TIM1_ITR2_RMP &&  LPTIM_OR_TIM5_ITR1_RMP && LPTIM_OR_TIM5_ITR1_RMP */
+#else
+#define IS_TIM_REMAP(INSTANCE, TIM_REMAP)                                 \
+  ((((INSTANCE) == TIM5)  && (((TIM_REMAP) == TIM_TIM5_GPIO)           || \
+                              ((TIM_REMAP) == TIM_TIM5_LSI)            || \
+                              ((TIM_REMAP) == TIM_TIM5_LSE)            || \
+                              ((TIM_REMAP) == TIM_TIM5_RTC)))          || \
+   (((INSTANCE) == TIM11) && (((TIM_REMAP) == TIM_TIM11_GPIO)          || \
+                              ((TIM_REMAP) == TIM_TIM11_HSE))))
+#endif /* SPDIFRX */
+
+/**
+  * @}
+  */
+/* End of private macro ------------------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup TIMEx_Exported_Functions TIM Extended Exported Functions
+  * @{
+  */
+
+/** @addtogroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions
+  *  @brief    Timer Hall Sensor functions
+  * @{
+  */
+/*  Timer Hall Sensor functions  **********************************************/
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef *sConfig);
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim);
+
+void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim);
+void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim);
+
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim);
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim);
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length);
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim);
+/**
+  * @}
+  */
+
+/** @addtogroup TIMEx_Exported_Functions_Group2 Extended Timer Complementary Output Compare functions
+  *  @brief   Timer Complementary Output Compare functions
+  * @{
+  */
+/*  Timer Complementary Output Compare functions  *****************************/
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
+
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
+HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
+/**
+  * @}
+  */
+
+/** @addtogroup TIMEx_Exported_Functions_Group3 Extended Timer Complementary PWM functions
+  *  @brief    Timer Complementary PWM functions
+  * @{
+  */
+/*  Timer Complementary PWM functions  ****************************************/
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
+
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
+/**
+  * @}
+  */
+
+/** @addtogroup TIMEx_Exported_Functions_Group4 Extended Timer Complementary One Pulse functions
+  *  @brief    Timer Complementary One Pulse functions
+  * @{
+  */
+/*  Timer Complementary One Pulse functions  **********************************/
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
+
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
+/**
+  * @}
+  */
+
+/** @addtogroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions
+  *  @brief    Peripheral Control functions
+  * @{
+  */
+/* Extended Control functions  ************************************************/
+HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t  InputTrigger,
+                                              uint32_t  CommutationSource);
+HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32_t  InputTrigger,
+                                                 uint32_t  CommutationSource);
+HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint32_t  InputTrigger,
+                                                  uint32_t  CommutationSource);
+HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
+                                                        TIM_MasterConfigTypeDef *sMasterConfig);
+HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,
+                                                TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig);
+HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap);
+/**
+  * @}
+  */
+
+/** @addtogroup TIMEx_Exported_Functions_Group6 Extended Callbacks functions
+  * @brief    Extended Callbacks functions
+  * @{
+  */
+/* Extended Callback **********************************************************/
+void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim);
+void HAL_TIMEx_CommutHalfCpltCallback(TIM_HandleTypeDef *htim);
+void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim);
+/**
+  * @}
+  */
+
+/** @addtogroup TIMEx_Exported_Functions_Group7 Extended Peripheral State functions
+  * @brief    Extended Peripheral State functions
+  * @{
+  */
+/* Extended Peripheral State functions  ***************************************/
+HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim);
+HAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState(TIM_HandleTypeDef *htim,  uint32_t ChannelN);
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+/* End of exported functions -------------------------------------------------*/
+
+/* Private functions----------------------------------------------------------*/
+/** @addtogroup TIMEx_Private_Functions TIM Extended Private Functions
+  * @{
+  */
+void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma);
+void TIMEx_DMACommutationHalfCplt(DMA_HandleTypeDef *hdma);
+/**
+  * @}
+  */
+/* End of private functions --------------------------------------------------*/
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* STM32F4xx_HAL_TIM_EX_H */
diff --git a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h
new file mode 100644
index 0000000..543ebcc
--- /dev/null
+++ b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h
@@ -0,0 +1,884 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hal_uart.h
+  * @author  MCD Application Team
+  * @brief   Header file of UART HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2016 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_UART_H
+#define __STM32F4xx_HAL_UART_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup UART
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup UART_Exported_Types UART Exported Types
+  * @{
+  */
+
+/**
+  * @brief UART Init Structure definition
+  */
+typedef struct
+{
+  uint32_t BaudRate;                  /*!< This member configures the UART communication baud rate.
+                                           The baud rate is computed using the following formula:
+                                           - IntegerDivider = ((PCLKx) / (8 * (OVR8+1) * (huart->Init.BaudRate)))
+                                           - FractionalDivider = ((IntegerDivider - ((uint32_t) IntegerDivider)) * 8 * (OVR8+1)) + 0.5
+                                           Where OVR8 is the "oversampling by 8 mode" configuration bit in the CR1 register. */
+
+  uint32_t WordLength;                /*!< Specifies the number of data bits transmitted or received in a frame.
+                                           This parameter can be a value of @ref UART_Word_Length */
+
+  uint32_t StopBits;                  /*!< Specifies the number of stop bits transmitted.
+                                           This parameter can be a value of @ref UART_Stop_Bits */
+
+  uint32_t Parity;                    /*!< Specifies the parity mode.
+                                           This parameter can be a value of @ref UART_Parity
+                                           @note When parity is enabled, the computed parity is inserted
+                                                 at the MSB position of the transmitted data (9th bit when
+                                                 the word length is set to 9 data bits; 8th bit when the
+                                                 word length is set to 8 data bits). */
+
+  uint32_t Mode;                      /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.
+                                           This parameter can be a value of @ref UART_Mode */
+
+  uint32_t HwFlowCtl;                 /*!< Specifies whether the hardware flow control mode is enabled or disabled.
+                                           This parameter can be a value of @ref UART_Hardware_Flow_Control */
+
+  uint32_t OverSampling;              /*!< Specifies whether the Over sampling 8 is enabled or disabled, to achieve higher speed (up to fPCLK/8).
+                                           This parameter can be a value of @ref UART_Over_Sampling */
+} UART_InitTypeDef;
+
+/**
+  * @brief HAL UART State structures definition
+  * @note  HAL UART State value is a combination of 2 different substates: gState and RxState.
+  *        - gState contains UART state information related to global Handle management
+  *          and also information related to Tx operations.
+  *          gState value coding follow below described bitmap :
+  *          b7-b6  Error information
+  *             00 : No Error
+  *             01 : (Not Used)
+  *             10 : Timeout
+  *             11 : Error
+  *          b5     Peripheral initialization status
+  *             0  : Reset (Peripheral not initialized)
+  *             1  : Init done (Peripheral initialized. HAL UART Init function already called)
+  *          b4-b3  (not used)
+  *             xx : Should be set to 00
+  *          b2     Intrinsic process state
+  *             0  : Ready
+  *             1  : Busy (Peripheral busy with some configuration or internal operations)
+  *          b1     (not used)
+  *             x  : Should be set to 0
+  *          b0     Tx state
+  *             0  : Ready (no Tx operation ongoing)
+  *             1  : Busy (Tx operation ongoing)
+  *        - RxState contains information related to Rx operations.
+  *          RxState value coding follow below described bitmap :
+  *          b7-b6  (not used)
+  *             xx : Should be set to 00
+  *          b5     Peripheral initialization status
+  *             0  : Reset (Peripheral not initialized)
+  *             1  : Init done (Peripheral initialized)
+  *          b4-b2  (not used)
+  *            xxx : Should be set to 000
+  *          b1     Rx state
+  *             0  : Ready (no Rx operation ongoing)
+  *             1  : Busy (Rx operation ongoing)
+  *          b0     (not used)
+  *             x  : Should be set to 0.
+  */
+typedef enum
+{
+  HAL_UART_STATE_RESET             = 0x00U,    /*!< Peripheral is not yet Initialized
+                                                   Value is allowed for gState and RxState */
+  HAL_UART_STATE_READY             = 0x20U,    /*!< Peripheral Initialized and ready for use
+                                                   Value is allowed for gState and RxState */
+  HAL_UART_STATE_BUSY              = 0x24U,    /*!< an internal process is ongoing
+                                                   Value is allowed for gState only */
+  HAL_UART_STATE_BUSY_TX           = 0x21U,    /*!< Data Transmission process is ongoing
+                                                   Value is allowed for gState only */
+  HAL_UART_STATE_BUSY_RX           = 0x22U,    /*!< Data Reception process is ongoing
+                                                   Value is allowed for RxState only */
+  HAL_UART_STATE_BUSY_TX_RX        = 0x23U,    /*!< Data Transmission and Reception process is ongoing
+                                                   Not to be used for neither gState nor RxState.
+                                                   Value is result of combination (Or) between gState and RxState values */
+  HAL_UART_STATE_TIMEOUT           = 0xA0U,    /*!< Timeout state
+                                                   Value is allowed for gState only */
+  HAL_UART_STATE_ERROR             = 0xE0U     /*!< Error
+                                                   Value is allowed for gState only */
+} HAL_UART_StateTypeDef;
+
+/**
+  * @brief HAL UART Reception type definition
+  * @note  HAL UART Reception type value aims to identify which type of Reception is ongoing.
+  *        It is expected to admit following values :
+  *           HAL_UART_RECEPTION_STANDARD         = 0x00U,
+  *           HAL_UART_RECEPTION_TOIDLE           = 0x01U,
+  */
+typedef uint32_t HAL_UART_RxTypeTypeDef;
+
+/**
+  * @brief  UART handle Structure definition
+  */
+typedef struct __UART_HandleTypeDef
+{
+  USART_TypeDef                 *Instance;        /*!< UART registers base address        */
+
+  UART_InitTypeDef              Init;             /*!< UART communication parameters      */
+
+  const uint8_t                 *pTxBuffPtr;      /*!< Pointer to UART Tx transfer Buffer */
+
+  uint16_t                      TxXferSize;       /*!< UART Tx Transfer size              */
+
+  __IO uint16_t                 TxXferCount;      /*!< UART Tx Transfer Counter           */
+
+  uint8_t                       *pRxBuffPtr;      /*!< Pointer to UART Rx transfer Buffer */
+
+  uint16_t                      RxXferSize;       /*!< UART Rx Transfer size              */
+
+  __IO uint16_t                 RxXferCount;      /*!< UART Rx Transfer Counter           */
+
+  __IO HAL_UART_RxTypeTypeDef ReceptionType;      /*!< Type of ongoing reception          */
+
+  DMA_HandleTypeDef             *hdmatx;          /*!< UART Tx DMA Handle parameters      */
+
+  DMA_HandleTypeDef             *hdmarx;          /*!< UART Rx DMA Handle parameters      */
+
+  HAL_LockTypeDef               Lock;             /*!< Locking object                     */
+
+  __IO HAL_UART_StateTypeDef    gState;           /*!< UART state information related to global Handle management
+                                                       and also related to Tx operations.
+                                                       This parameter can be a value of @ref HAL_UART_StateTypeDef */
+
+  __IO HAL_UART_StateTypeDef    RxState;          /*!< UART state information related to Rx operations.
+                                                       This parameter can be a value of @ref HAL_UART_StateTypeDef */
+
+  __IO uint32_t                 ErrorCode;        /*!< UART Error code                    */
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+  void (* TxHalfCpltCallback)(struct __UART_HandleTypeDef *huart);        /*!< UART Tx Half Complete Callback        */
+  void (* TxCpltCallback)(struct __UART_HandleTypeDef *huart);            /*!< UART Tx Complete Callback             */
+  void (* RxHalfCpltCallback)(struct __UART_HandleTypeDef *huart);        /*!< UART Rx Half Complete Callback        */
+  void (* RxCpltCallback)(struct __UART_HandleTypeDef *huart);            /*!< UART Rx Complete Callback             */
+  void (* ErrorCallback)(struct __UART_HandleTypeDef *huart);             /*!< UART Error Callback                   */
+  void (* AbortCpltCallback)(struct __UART_HandleTypeDef *huart);         /*!< UART Abort Complete Callback          */
+  void (* AbortTransmitCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Abort Transmit Complete Callback */
+  void (* AbortReceiveCpltCallback)(struct __UART_HandleTypeDef *huart);  /*!< UART Abort Receive Complete Callback  */
+  void (* WakeupCallback)(struct __UART_HandleTypeDef *huart);            /*!< UART Wakeup Callback                  */
+  void (* RxEventCallback)(struct __UART_HandleTypeDef *huart, uint16_t Pos); /*!< UART Reception Event Callback     */
+
+  void (* MspInitCallback)(struct __UART_HandleTypeDef *huart);           /*!< UART Msp Init callback                */
+  void (* MspDeInitCallback)(struct __UART_HandleTypeDef *huart);         /*!< UART Msp DeInit callback              */
+#endif  /* USE_HAL_UART_REGISTER_CALLBACKS */
+
+} UART_HandleTypeDef;
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+/**
+  * @brief  HAL UART Callback ID enumeration definition
+  */
+typedef enum
+{
+  HAL_UART_TX_HALFCOMPLETE_CB_ID         = 0x00U,    /*!< UART Tx Half Complete Callback ID        */
+  HAL_UART_TX_COMPLETE_CB_ID             = 0x01U,    /*!< UART Tx Complete Callback ID             */
+  HAL_UART_RX_HALFCOMPLETE_CB_ID         = 0x02U,    /*!< UART Rx Half Complete Callback ID        */
+  HAL_UART_RX_COMPLETE_CB_ID             = 0x03U,    /*!< UART Rx Complete Callback ID             */
+  HAL_UART_ERROR_CB_ID                   = 0x04U,    /*!< UART Error Callback ID                   */
+  HAL_UART_ABORT_COMPLETE_CB_ID          = 0x05U,    /*!< UART Abort Complete Callback ID          */
+  HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID = 0x06U,    /*!< UART Abort Transmit Complete Callback ID */
+  HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID  = 0x07U,    /*!< UART Abort Receive Complete Callback ID  */
+  HAL_UART_WAKEUP_CB_ID                  = 0x08U,    /*!< UART Wakeup Callback ID                  */
+
+  HAL_UART_MSPINIT_CB_ID                 = 0x0BU,    /*!< UART MspInit callback ID                 */
+  HAL_UART_MSPDEINIT_CB_ID               = 0x0CU     /*!< UART MspDeInit callback ID               */
+
+} HAL_UART_CallbackIDTypeDef;
+
+/**
+  * @brief  HAL UART Callback pointer definition
+  */
+typedef  void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart);  /*!< pointer to an UART callback function */
+typedef  void (*pUART_RxEventCallbackTypeDef)(struct __UART_HandleTypeDef *huart, uint16_t Pos);   /*!< pointer to a UART Rx Event specific callback function */
+
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup UART_Exported_Constants UART Exported Constants
+  * @{
+  */
+
+/** @defgroup UART_Error_Code UART Error Code
+  * @{
+  */
+#define HAL_UART_ERROR_NONE              0x00000000U   /*!< No error            */
+#define HAL_UART_ERROR_PE                0x00000001U   /*!< Parity error        */
+#define HAL_UART_ERROR_NE                0x00000002U   /*!< Noise error         */
+#define HAL_UART_ERROR_FE                0x00000004U   /*!< Frame error         */
+#define HAL_UART_ERROR_ORE               0x00000008U   /*!< Overrun error       */
+#define HAL_UART_ERROR_DMA               0x00000010U   /*!< DMA transfer error  */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+#define  HAL_UART_ERROR_INVALID_CALLBACK 0x00000020U   /*!< Invalid Callback error  */
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+/**
+  * @}
+  */
+
+/** @defgroup UART_Word_Length UART Word Length
+  * @{
+  */
+#define UART_WORDLENGTH_8B                  0x00000000U
+#define UART_WORDLENGTH_9B                  ((uint32_t)USART_CR1_M)
+/**
+  * @}
+  */
+
+/** @defgroup UART_Stop_Bits UART Number of Stop Bits
+  * @{
+  */
+#define UART_STOPBITS_1                     0x00000000U
+#define UART_STOPBITS_2                     ((uint32_t)USART_CR2_STOP_1)
+/**
+  * @}
+  */
+
+/** @defgroup UART_Parity UART Parity
+  * @{
+  */
+#define UART_PARITY_NONE                    0x00000000U
+#define UART_PARITY_EVEN                    ((uint32_t)USART_CR1_PCE)
+#define UART_PARITY_ODD                     ((uint32_t)(USART_CR1_PCE | USART_CR1_PS))
+/**
+  * @}
+  */
+
+/** @defgroup UART_Hardware_Flow_Control UART Hardware Flow Control
+  * @{
+  */
+#define UART_HWCONTROL_NONE                  0x00000000U
+#define UART_HWCONTROL_RTS                   ((uint32_t)USART_CR3_RTSE)
+#define UART_HWCONTROL_CTS                   ((uint32_t)USART_CR3_CTSE)
+#define UART_HWCONTROL_RTS_CTS               ((uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE))
+/**
+  * @}
+  */
+
+/** @defgroup UART_Mode UART Transfer Mode
+  * @{
+  */
+#define UART_MODE_RX                        ((uint32_t)USART_CR1_RE)
+#define UART_MODE_TX                        ((uint32_t)USART_CR1_TE)
+#define UART_MODE_TX_RX                     ((uint32_t)(USART_CR1_TE | USART_CR1_RE))
+/**
+  * @}
+  */
+
+/** @defgroup UART_State UART State
+  * @{
+  */
+#define UART_STATE_DISABLE                  0x00000000U
+#define UART_STATE_ENABLE                   ((uint32_t)USART_CR1_UE)
+/**
+  * @}
+  */
+
+/** @defgroup UART_Over_Sampling UART Over Sampling
+  * @{
+  */
+#define UART_OVERSAMPLING_16                    0x00000000U
+#define UART_OVERSAMPLING_8                     ((uint32_t)USART_CR1_OVER8)
+/**
+  * @}
+  */
+
+/** @defgroup UART_LIN_Break_Detection_Length  UART LIN Break Detection Length
+  * @{
+  */
+#define UART_LINBREAKDETECTLENGTH_10B      0x00000000U
+#define UART_LINBREAKDETECTLENGTH_11B      ((uint32_t)USART_CR2_LBDL)
+/**
+  * @}
+  */
+
+/** @defgroup UART_WakeUp_functions  UART Wakeup Functions
+  * @{
+  */
+#define UART_WAKEUPMETHOD_IDLELINE                0x00000000U
+#define UART_WAKEUPMETHOD_ADDRESSMARK             ((uint32_t)USART_CR1_WAKE)
+/**
+  * @}
+  */
+
+/** @defgroup UART_Flags   UART FLags
+  *        Elements values convention: 0xXXXX
+  *           - 0xXXXX  : Flag mask in the SR register
+  * @{
+  */
+#define UART_FLAG_CTS                       ((uint32_t)USART_SR_CTS)
+#define UART_FLAG_LBD                       ((uint32_t)USART_SR_LBD)
+#define UART_FLAG_TXE                       ((uint32_t)USART_SR_TXE)
+#define UART_FLAG_TC                        ((uint32_t)USART_SR_TC)
+#define UART_FLAG_RXNE                      ((uint32_t)USART_SR_RXNE)
+#define UART_FLAG_IDLE                      ((uint32_t)USART_SR_IDLE)
+#define UART_FLAG_ORE                       ((uint32_t)USART_SR_ORE)
+#define UART_FLAG_NE                        ((uint32_t)USART_SR_NE)
+#define UART_FLAG_FE                        ((uint32_t)USART_SR_FE)
+#define UART_FLAG_PE                        ((uint32_t)USART_SR_PE)
+/**
+  * @}
+  */
+
+/** @defgroup UART_Interrupt_definition  UART Interrupt Definitions
+  *        Elements values convention: 0xY000XXXX
+  *           - XXXX  : Interrupt mask (16 bits) in the Y register
+  *           - Y  : Interrupt source register (2bits)
+  *                   - 0001: CR1 register
+  *                   - 0010: CR2 register
+  *                   - 0011: CR3 register
+  * @{
+  */
+
+#define UART_IT_PE                       ((uint32_t)(UART_CR1_REG_INDEX << 28U | USART_CR1_PEIE))
+#define UART_IT_TXE                      ((uint32_t)(UART_CR1_REG_INDEX << 28U | USART_CR1_TXEIE))
+#define UART_IT_TC                       ((uint32_t)(UART_CR1_REG_INDEX << 28U | USART_CR1_TCIE))
+#define UART_IT_RXNE                     ((uint32_t)(UART_CR1_REG_INDEX << 28U | USART_CR1_RXNEIE))
+#define UART_IT_IDLE                     ((uint32_t)(UART_CR1_REG_INDEX << 28U | USART_CR1_IDLEIE))
+
+#define UART_IT_LBD                      ((uint32_t)(UART_CR2_REG_INDEX << 28U | USART_CR2_LBDIE))
+
+#define UART_IT_CTS                      ((uint32_t)(UART_CR3_REG_INDEX << 28U | USART_CR3_CTSIE))
+#define UART_IT_ERR                      ((uint32_t)(UART_CR3_REG_INDEX << 28U | USART_CR3_EIE))
+/**
+  * @}
+  */
+
+/** @defgroup UART_RECEPTION_TYPE_Values  UART Reception type values
+  * @{
+  */
+#define HAL_UART_RECEPTION_STANDARD          (0x00000000U)             /*!< Standard reception                       */
+#define HAL_UART_RECEPTION_TOIDLE            (0x00000001U)             /*!< Reception till completion or IDLE event  */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup UART_Exported_Macros UART Exported Macros
+  * @{
+  */
+
+/** @brief Reset UART handle gstate & RxState
+  * @param  __HANDLE__ specifies the UART Handle.
+  *         UART Handle selects the USARTx or UARTy peripheral
+  *         (USART,UART availability and x,y values depending on device).
+  * @retval None
+  */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+#define __HAL_UART_RESET_HANDLE_STATE(__HANDLE__)  do{                                                   \
+                                                       (__HANDLE__)->gState = HAL_UART_STATE_RESET;      \
+                                                       (__HANDLE__)->RxState = HAL_UART_STATE_RESET;     \
+                                                       (__HANDLE__)->MspInitCallback = NULL;             \
+                                                       (__HANDLE__)->MspDeInitCallback = NULL;           \
+                                                     } while(0U)
+#else
+#define __HAL_UART_RESET_HANDLE_STATE(__HANDLE__)  do{                                                   \
+                                                       (__HANDLE__)->gState = HAL_UART_STATE_RESET;      \
+                                                       (__HANDLE__)->RxState = HAL_UART_STATE_RESET;     \
+                                                     } while(0U)
+#endif /*USE_HAL_UART_REGISTER_CALLBACKS */
+
+/** @brief  Flushes the UART DR register
+  * @param  __HANDLE__ specifies the UART Handle.
+  *         UART Handle selects the USARTx or UARTy peripheral
+  *         (USART,UART availability and x,y values depending on device).
+  */
+#define __HAL_UART_FLUSH_DRREGISTER(__HANDLE__) ((__HANDLE__)->Instance->DR)
+
+/** @brief  Checks whether the specified UART flag is set or not.
+  * @param  __HANDLE__ specifies the UART Handle.
+  *         UART Handle selects the USARTx or UARTy peripheral
+  *         (USART,UART availability and x,y values depending on device).
+  * @param  __FLAG__ specifies the flag to check.
+  *        This parameter can be one of the following values:
+  *            @arg UART_FLAG_CTS:  CTS Change flag (not available for UART4 and UART5)
+  *            @arg UART_FLAG_LBD:  LIN Break detection flag
+  *            @arg UART_FLAG_TXE:  Transmit data register empty flag
+  *            @arg UART_FLAG_TC:   Transmission Complete flag
+  *            @arg UART_FLAG_RXNE: Receive data register not empty flag
+  *            @arg UART_FLAG_IDLE: Idle Line detection flag
+  *            @arg UART_FLAG_ORE:  Overrun Error flag
+  *            @arg UART_FLAG_NE:   Noise Error flag
+  *            @arg UART_FLAG_FE:   Framing Error flag
+  *            @arg UART_FLAG_PE:   Parity Error flag
+  * @retval The new state of __FLAG__ (TRUE or FALSE).
+  */
+#define __HAL_UART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
+
+/** @brief  Clears the specified UART pending flag.
+  * @param  __HANDLE__ specifies the UART Handle.
+  *         UART Handle selects the USARTx or UARTy peripheral
+  *         (USART,UART availability and x,y values depending on device).
+  * @param  __FLAG__ specifies the flag to check.
+  *          This parameter can be any combination of the following values:
+  *            @arg UART_FLAG_CTS:  CTS Change flag (not available for UART4 and UART5).
+  *            @arg UART_FLAG_LBD:  LIN Break detection flag.
+  *            @arg UART_FLAG_TC:   Transmission Complete flag.
+  *            @arg UART_FLAG_RXNE: Receive data register not empty flag.
+  *
+  * @note   PE (Parity error), FE (Framing error), NE (Noise error), ORE (Overrun
+  *          error) and IDLE (Idle line detected) flags are cleared by software
+  *          sequence: a read operation to USART_SR register followed by a read
+  *          operation to USART_DR register.
+  * @note   RXNE flag can be also cleared by a read to the USART_DR register.
+  * @note   TC flag can be also cleared by software sequence: a read operation to
+  *          USART_SR register followed by a write operation to USART_DR register.
+  * @note   TXE flag is cleared only by a write to the USART_DR register.
+  *
+  * @retval None
+  */
+#define __HAL_UART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
+
+/** @brief  Clears the UART PE pending flag.
+  * @param  __HANDLE__ specifies the UART Handle.
+  *         UART Handle selects the USARTx or UARTy peripheral
+  *         (USART,UART availability and x,y values depending on device).
+  * @retval None
+  */
+#define __HAL_UART_CLEAR_PEFLAG(__HANDLE__)     \
+  do{                                           \
+    __IO uint32_t tmpreg = 0x00U;               \
+    tmpreg = (__HANDLE__)->Instance->SR;        \
+    tmpreg = (__HANDLE__)->Instance->DR;        \
+    UNUSED(tmpreg);                             \
+  } while(0U)
+
+/** @brief  Clears the UART FE pending flag.
+  * @param  __HANDLE__ specifies the UART Handle.
+  *         UART Handle selects the USARTx or UARTy peripheral
+  *         (USART,UART availability and x,y values depending on device).
+  * @retval None
+  */
+#define __HAL_UART_CLEAR_FEFLAG(__HANDLE__) __HAL_UART_CLEAR_PEFLAG(__HANDLE__)
+
+/** @brief  Clears the UART NE pending flag.
+  * @param  __HANDLE__ specifies the UART Handle.
+  *         UART Handle selects the USARTx or UARTy peripheral
+  *         (USART,UART availability and x,y values depending on device).
+  * @retval None
+  */
+#define __HAL_UART_CLEAR_NEFLAG(__HANDLE__) __HAL_UART_CLEAR_PEFLAG(__HANDLE__)
+
+/** @brief  Clears the UART ORE pending flag.
+  * @param  __HANDLE__ specifies the UART Handle.
+  *         UART Handle selects the USARTx or UARTy peripheral
+  *         (USART,UART availability and x,y values depending on device).
+  * @retval None
+  */
+#define __HAL_UART_CLEAR_OREFLAG(__HANDLE__) __HAL_UART_CLEAR_PEFLAG(__HANDLE__)
+
+/** @brief  Clears the UART IDLE pending flag.
+  * @param  __HANDLE__ specifies the UART Handle.
+  *         UART Handle selects the USARTx or UARTy peripheral
+  *         (USART,UART availability and x,y values depending on device).
+  * @retval None
+  */
+#define __HAL_UART_CLEAR_IDLEFLAG(__HANDLE__) __HAL_UART_CLEAR_PEFLAG(__HANDLE__)
+
+/** @brief  Enable the specified UART interrupt.
+  * @param  __HANDLE__ specifies the UART Handle.
+  *         UART Handle selects the USARTx or UARTy peripheral
+  *         (USART,UART availability and x,y values depending on device).
+  * @param  __INTERRUPT__ specifies the UART interrupt source to enable.
+  *          This parameter can be one of the following values:
+  *            @arg UART_IT_CTS:  CTS change interrupt
+  *            @arg UART_IT_LBD:  LIN Break detection interrupt
+  *            @arg UART_IT_TXE:  Transmit Data Register empty interrupt
+  *            @arg UART_IT_TC:   Transmission complete interrupt
+  *            @arg UART_IT_RXNE: Receive Data register not empty interrupt
+  *            @arg UART_IT_IDLE: Idle line detection interrupt
+  *            @arg UART_IT_PE:   Parity Error interrupt
+  *            @arg UART_IT_ERR:  Error interrupt(Frame error, noise error, overrun error)
+  * @retval None
+  */
+#define __HAL_UART_ENABLE_IT(__HANDLE__, __INTERRUPT__)   ((((__INTERRUPT__) >> 28U) == UART_CR1_REG_INDEX)? ((__HANDLE__)->Instance->CR1 |= ((__INTERRUPT__) & UART_IT_MASK)): \
+                                                           (((__INTERRUPT__) >> 28U) == UART_CR2_REG_INDEX)? ((__HANDLE__)->Instance->CR2 |= ((__INTERRUPT__) & UART_IT_MASK)): \
+                                                           ((__HANDLE__)->Instance->CR3 |= ((__INTERRUPT__) & UART_IT_MASK)))
+
+/** @brief  Disable the specified UART interrupt.
+  * @param  __HANDLE__ specifies the UART Handle.
+  *         UART Handle selects the USARTx or UARTy peripheral
+  *         (USART,UART availability and x,y values depending on device).
+  * @param  __INTERRUPT__ specifies the UART interrupt source to disable.
+  *          This parameter can be one of the following values:
+  *            @arg UART_IT_CTS:  CTS change interrupt
+  *            @arg UART_IT_LBD:  LIN Break detection interrupt
+  *            @arg UART_IT_TXE:  Transmit Data Register empty interrupt
+  *            @arg UART_IT_TC:   Transmission complete interrupt
+  *            @arg UART_IT_RXNE: Receive Data register not empty interrupt
+  *            @arg UART_IT_IDLE: Idle line detection interrupt
+  *            @arg UART_IT_PE:   Parity Error interrupt
+  *            @arg UART_IT_ERR:  Error interrupt(Frame error, noise error, overrun error)
+  * @retval None
+  */
+#define __HAL_UART_DISABLE_IT(__HANDLE__, __INTERRUPT__)  ((((__INTERRUPT__) >> 28U) == UART_CR1_REG_INDEX)? ((__HANDLE__)->Instance->CR1 &= ~((__INTERRUPT__) & UART_IT_MASK)): \
+                                                           (((__INTERRUPT__) >> 28U) == UART_CR2_REG_INDEX)? ((__HANDLE__)->Instance->CR2 &= ~((__INTERRUPT__) & UART_IT_MASK)): \
+                                                           ((__HANDLE__)->Instance->CR3 &= ~ ((__INTERRUPT__) & UART_IT_MASK)))
+
+/** @brief  Checks whether the specified UART interrupt source is enabled or not.
+  * @param  __HANDLE__ specifies the UART Handle.
+  *         UART Handle selects the USARTx or UARTy peripheral
+  *         (USART,UART availability and x,y values depending on device).
+  * @param  __IT__ specifies the UART interrupt source to check.
+  *          This parameter can be one of the following values:
+  *            @arg UART_IT_CTS: CTS change interrupt (not available for UART4 and UART5)
+  *            @arg UART_IT_LBD: LIN Break detection interrupt
+  *            @arg UART_IT_TXE: Transmit Data Register empty interrupt
+  *            @arg UART_IT_TC:  Transmission complete interrupt
+  *            @arg UART_IT_RXNE: Receive Data register not empty interrupt
+  *            @arg UART_IT_IDLE: Idle line detection interrupt
+  *            @arg UART_IT_ERR: Error interrupt
+  * @retval The new state of __IT__ (TRUE or FALSE).
+  */
+#define __HAL_UART_GET_IT_SOURCE(__HANDLE__, __IT__) (((((__IT__) >> 28U) == UART_CR1_REG_INDEX)? (__HANDLE__)->Instance->CR1:(((((uint32_t)(__IT__)) >> 28U) == UART_CR2_REG_INDEX)? \
+                                                       (__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & (((uint32_t)(__IT__)) & UART_IT_MASK))
+
+/** @brief  Enable CTS flow control
+  * @note   This macro allows to enable CTS hardware flow control for a given UART instance,
+  *         without need to call HAL_UART_Init() function.
+  *         As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
+  * @note   As macro is expected to be used for modifying CTS Hw flow control feature activation, without need
+  *         for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
+  *           - UART instance should have already been initialised (through call of HAL_UART_Init() )
+  *           - macro could only be called when corresponding UART instance is disabled (i.e __HAL_UART_DISABLE(__HANDLE__))
+  *             and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)).
+  * @param  __HANDLE__ specifies the UART Handle.
+  *         The Handle Instance can be any USARTx (supporting the HW Flow control feature).
+  *         It is used to select the USART peripheral (USART availability and x value depending on device).
+  * @retval None
+  */
+#define __HAL_UART_HWCONTROL_CTS_ENABLE(__HANDLE__)        \
+  do{                                                      \
+    ATOMIC_SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE);  \
+    (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_CTSE;        \
+  } while(0U)
+
+/** @brief  Disable CTS flow control
+  * @note   This macro allows to disable CTS hardware flow control for a given UART instance,
+  *         without need to call HAL_UART_Init() function.
+  *         As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
+  * @note   As macro is expected to be used for modifying CTS Hw flow control feature activation, without need
+  *         for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
+  *           - UART instance should have already been initialised (through call of HAL_UART_Init() )
+  *           - macro could only be called when corresponding UART instance is disabled (i.e __HAL_UART_DISABLE(__HANDLE__))
+  *             and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)).
+  * @param  __HANDLE__ specifies the UART Handle.
+  *         The Handle Instance can be any USARTx (supporting the HW Flow control feature).
+  *         It is used to select the USART peripheral (USART availability and x value depending on device).
+  * @retval None
+  */
+#define __HAL_UART_HWCONTROL_CTS_DISABLE(__HANDLE__)        \
+  do{                                                       \
+    ATOMIC_CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \
+    (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_CTSE);      \
+  } while(0U)
+
+/** @brief  Enable RTS flow control
+  *         This macro allows to enable RTS hardware flow control for a given UART instance,
+  *         without need to call HAL_UART_Init() function.
+  *         As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
+  * @note   As macro is expected to be used for modifying RTS Hw flow control feature activation, without need
+  *         for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
+  *           - UART instance should have already been initialised (through call of HAL_UART_Init() )
+  *           - macro could only be called when corresponding UART instance is disabled (i.e __HAL_UART_DISABLE(__HANDLE__))
+  *             and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)).
+  * @param  __HANDLE__ specifies the UART Handle.
+  *         The Handle Instance can be any USARTx (supporting the HW Flow control feature).
+  *         It is used to select the USART peripheral (USART availability and x value depending on device).
+  * @retval None
+  */
+#define __HAL_UART_HWCONTROL_RTS_ENABLE(__HANDLE__)       \
+  do{                                                     \
+    ATOMIC_SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE); \
+    (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_RTSE;       \
+  } while(0U)
+
+/** @brief  Disable RTS flow control
+  *         This macro allows to disable RTS hardware flow control for a given UART instance,
+  *         without need to call HAL_UART_Init() function.
+  *         As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
+  * @note   As macro is expected to be used for modifying RTS Hw flow control feature activation, without need
+  *         for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
+  *           - UART instance should have already been initialised (through call of HAL_UART_Init() )
+  *           - macro could only be called when corresponding UART instance is disabled (i.e __HAL_UART_DISABLE(__HANDLE__))
+  *             and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)).
+  * @param  __HANDLE__ specifies the UART Handle.
+  *         The Handle Instance can be any USARTx (supporting the HW Flow control feature).
+  *         It is used to select the USART peripheral (USART availability and x value depending on device).
+  * @retval None
+  */
+#define __HAL_UART_HWCONTROL_RTS_DISABLE(__HANDLE__)       \
+  do{                                                      \
+    ATOMIC_CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE);\
+    (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_RTSE);     \
+  } while(0U)
+
+/** @brief  Macro to enable the UART's one bit sample method
+  * @param  __HANDLE__ specifies the UART Handle.
+  * @retval None
+  */
+#define __HAL_UART_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
+
+/** @brief  Macro to disable the UART's one bit sample method
+  * @param  __HANDLE__ specifies the UART Handle.
+  * @retval None
+  */
+#define __HAL_UART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3\
+                                                       &= (uint16_t)~((uint16_t)USART_CR3_ONEBIT))
+
+/** @brief  Enable UART
+  * @param  __HANDLE__ specifies the UART Handle.
+  * @retval None
+  */
+#define __HAL_UART_ENABLE(__HANDLE__)               ((__HANDLE__)->Instance->CR1 |=  USART_CR1_UE)
+
+/** @brief  Disable UART
+  * @param  __HANDLE__ specifies the UART Handle.
+  * @retval None
+  */
+#define __HAL_UART_DISABLE(__HANDLE__)              ((__HANDLE__)->Instance->CR1 &=  ~USART_CR1_UE)
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup UART_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup UART_Exported_Functions_Group1 Initialization and de-initialization functions
+  * @{
+  */
+
+/* Initialization/de-initialization functions  **********************************/
+HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLength);
+HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod);
+HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart);
+void HAL_UART_MspInit(UART_HandleTypeDef *huart);
+void HAL_UART_MspDeInit(UART_HandleTypeDef *huart);
+
+/* Callbacks Register/UnRegister functions  ***********************************/
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+HAL_StatusTypeDef HAL_UART_RegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID,
+                                            pUART_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_UART_UnRegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID);
+
+HAL_StatusTypeDef HAL_UART_RegisterRxEventCallback(UART_HandleTypeDef *huart, pUART_RxEventCallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_UART_UnRegisterRxEventCallback(UART_HandleTypeDef *huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+
+/** @addtogroup UART_Exported_Functions_Group2 IO operation functions
+  * @{
+  */
+
+/* IO operation functions *******************************************************/
+HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart);
+
+HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint16_t *RxLen,
+                                           uint32_t Timeout);
+HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
+
+/* Transfer Abort functions */
+HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_UART_AbortReceive(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart);
+
+void HAL_UART_IRQHandler(UART_HandleTypeDef *huart);
+void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart);
+void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart);
+void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart);
+void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart);
+void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart);
+void HAL_UART_AbortCpltCallback(UART_HandleTypeDef *huart);
+void HAL_UART_AbortTransmitCpltCallback(UART_HandleTypeDef *huart);
+void HAL_UART_AbortReceiveCpltCallback(UART_HandleTypeDef *huart);
+
+void HAL_UARTEx_RxEventCallback(UART_HandleTypeDef *huart, uint16_t Size);
+
+/**
+  * @}
+  */
+
+/** @addtogroup UART_Exported_Functions_Group3
+  * @{
+  */
+/* Peripheral Control functions  ************************************************/
+HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_MultiProcessor_ExitMuteMode(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart);
+/**
+  * @}
+  */
+
+/** @addtogroup UART_Exported_Functions_Group4
+  * @{
+  */
+/* Peripheral State functions  **************************************************/
+HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart);
+uint32_t              HAL_UART_GetError(UART_HandleTypeDef *huart);
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup UART_Private_Constants UART Private Constants
+  * @{
+  */
+/** @brief UART interruptions flag mask
+  *
+  */
+#define UART_IT_MASK                     0x0000FFFFU
+
+#define UART_CR1_REG_INDEX               1U
+#define UART_CR2_REG_INDEX               2U
+#define UART_CR3_REG_INDEX               3U
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup UART_Private_Macros UART Private Macros
+  * @{
+  */
+#define IS_UART_WORD_LENGTH(LENGTH) (((LENGTH) == UART_WORDLENGTH_8B) || \
+                                     ((LENGTH) == UART_WORDLENGTH_9B))
+#define IS_UART_LIN_WORD_LENGTH(LENGTH) (((LENGTH) == UART_WORDLENGTH_8B))
+#define IS_UART_STOPBITS(STOPBITS) (((STOPBITS) == UART_STOPBITS_1) || \
+                                    ((STOPBITS) == UART_STOPBITS_2))
+#define IS_UART_PARITY(PARITY) (((PARITY) == UART_PARITY_NONE) || \
+                                ((PARITY) == UART_PARITY_EVEN) || \
+                                ((PARITY) == UART_PARITY_ODD))
+#define IS_UART_HARDWARE_FLOW_CONTROL(CONTROL)\
+                              (((CONTROL) == UART_HWCONTROL_NONE) || \
+                               ((CONTROL) == UART_HWCONTROL_RTS) || \
+                               ((CONTROL) == UART_HWCONTROL_CTS) || \
+                               ((CONTROL) == UART_HWCONTROL_RTS_CTS))
+#define IS_UART_MODE(MODE) ((((MODE) & 0x0000FFF3U) == 0x00U) && ((MODE) != 0x00U))
+#define IS_UART_STATE(STATE) (((STATE) == UART_STATE_DISABLE) || \
+                              ((STATE) == UART_STATE_ENABLE))
+#define IS_UART_OVERSAMPLING(SAMPLING) (((SAMPLING) == UART_OVERSAMPLING_16) || \
+                                        ((SAMPLING) == UART_OVERSAMPLING_8))
+#define IS_UART_LIN_OVERSAMPLING(SAMPLING) (((SAMPLING) == UART_OVERSAMPLING_16))
+#define IS_UART_LIN_BREAK_DETECT_LENGTH(LENGTH) (((LENGTH) == UART_LINBREAKDETECTLENGTH_10B) || \
+                                                 ((LENGTH) == UART_LINBREAKDETECTLENGTH_11B))
+#define IS_UART_WAKEUPMETHOD(WAKEUP) (((WAKEUP) == UART_WAKEUPMETHOD_IDLELINE) || \
+                                      ((WAKEUP) == UART_WAKEUPMETHOD_ADDRESSMARK))
+#define IS_UART_BAUDRATE(BAUDRATE) ((BAUDRATE) <= 10500000U)
+#define IS_UART_ADDRESS(ADDRESS) ((ADDRESS) <= 0x0FU)
+
+#define UART_DIV_SAMPLING16(_PCLK_, _BAUD_)            ((uint32_t)((((uint64_t)(_PCLK_))*25U)/(4U*((uint64_t)(_BAUD_)))))
+#define UART_DIVMANT_SAMPLING16(_PCLK_, _BAUD_)        (UART_DIV_SAMPLING16((_PCLK_), (_BAUD_))/100U)
+#define UART_DIVFRAQ_SAMPLING16(_PCLK_, _BAUD_)        ((((UART_DIV_SAMPLING16((_PCLK_), (_BAUD_)) - (UART_DIVMANT_SAMPLING16((_PCLK_), (_BAUD_)) * 100U)) * 16U)\
+                                                         + 50U) / 100U)
+/* UART BRR = mantissa + overflow + fraction
+            = (UART DIVMANT << 4) + (UART DIVFRAQ & 0xF0) + (UART DIVFRAQ & 0x0FU) */
+#define UART_BRR_SAMPLING16(_PCLK_, _BAUD_)            ((UART_DIVMANT_SAMPLING16((_PCLK_), (_BAUD_)) << 4U) + \
+                                                        (UART_DIVFRAQ_SAMPLING16((_PCLK_), (_BAUD_)) & 0xF0U) + \
+                                                        (UART_DIVFRAQ_SAMPLING16((_PCLK_), (_BAUD_)) & 0x0FU))
+
+#define UART_DIV_SAMPLING8(_PCLK_, _BAUD_)             ((uint32_t)((((uint64_t)(_PCLK_))*25U)/(2U*((uint64_t)(_BAUD_)))))
+#define UART_DIVMANT_SAMPLING8(_PCLK_, _BAUD_)         (UART_DIV_SAMPLING8((_PCLK_), (_BAUD_))/100U)
+#define UART_DIVFRAQ_SAMPLING8(_PCLK_, _BAUD_)         ((((UART_DIV_SAMPLING8((_PCLK_), (_BAUD_)) - (UART_DIVMANT_SAMPLING8((_PCLK_), (_BAUD_)) * 100U)) * 8U)\
+                                                         + 50U) / 100U)
+/* UART BRR = mantissa + overflow + fraction
+            = (UART DIVMANT << 4) + ((UART DIVFRAQ & 0xF8) << 1) + (UART DIVFRAQ & 0x07U) */
+#define UART_BRR_SAMPLING8(_PCLK_, _BAUD_)             ((UART_DIVMANT_SAMPLING8((_PCLK_), (_BAUD_)) << 4U) + \
+                                                        ((UART_DIVFRAQ_SAMPLING8((_PCLK_), (_BAUD_)) & 0xF8U) << 1U) + \
+                                                        (UART_DIVFRAQ_SAMPLING8((_PCLK_), (_BAUD_)) & 0x07U))
+
+/**
+  * @}
+  */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup UART_Private_Functions UART Private Functions
+  * @{
+  */
+
+HAL_StatusTypeDef UART_Start_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef UART_Start_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_UART_H */
+
diff --git a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_bus.h b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_bus.h
new file mode 100644
index 0000000..460edfc
--- /dev/null
+++ b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_bus.h
@@ -0,0 +1,2105 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_ll_bus.h
+  * @author  MCD Application Team
+  * @brief   Header file of BUS LL module.
+
+  @verbatim
+                      ##### RCC Limitations #####
+  ==============================================================================
+    [..]
+      A delay between an RCC peripheral clock enable and the effective peripheral
+      enabling should be taken into account in order to manage the peripheral read/write
+      from/to registers.
+      (+) This delay depends on the peripheral mapping.
+        (++) AHB & APB peripherals, 1 dummy read is necessary
+
+    [..]
+      Workarounds:
+      (#) For AHB & APB peripherals, a dummy read to the peripheral register has been
+          inserted in each LL_{BUS}_GRP{x}_EnableClock() function.
+
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file in
+  * the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_LL_BUS_H
+#define __STM32F4xx_LL_BUS_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx.h"
+
+/** @addtogroup STM32F4xx_LL_Driver
+  * @{
+  */
+
+#if defined(RCC)
+
+/** @defgroup BUS_LL BUS
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup BUS_LL_Exported_Constants BUS Exported Constants
+  * @{
+  */
+
+/** @defgroup BUS_LL_EC_AHB1_GRP1_PERIPH  AHB1 GRP1 PERIPH
+  * @{
+  */
+#define LL_AHB1_GRP1_PERIPH_ALL             0xFFFFFFFFU
+#define LL_AHB1_GRP1_PERIPH_GPIOA           RCC_AHB1ENR_GPIOAEN
+#define LL_AHB1_GRP1_PERIPH_GPIOB           RCC_AHB1ENR_GPIOBEN
+#define LL_AHB1_GRP1_PERIPH_GPIOC           RCC_AHB1ENR_GPIOCEN
+#if defined(GPIOD)
+#define LL_AHB1_GRP1_PERIPH_GPIOD           RCC_AHB1ENR_GPIODEN
+#endif /* GPIOD */
+#if defined(GPIOE)
+#define LL_AHB1_GRP1_PERIPH_GPIOE           RCC_AHB1ENR_GPIOEEN
+#endif /* GPIOE */
+#if defined(GPIOF)
+#define LL_AHB1_GRP1_PERIPH_GPIOF           RCC_AHB1ENR_GPIOFEN
+#endif /* GPIOF */
+#if defined(GPIOG)
+#define LL_AHB1_GRP1_PERIPH_GPIOG           RCC_AHB1ENR_GPIOGEN
+#endif /* GPIOG */
+#if defined(GPIOH)
+#define LL_AHB1_GRP1_PERIPH_GPIOH           RCC_AHB1ENR_GPIOHEN
+#endif /* GPIOH */
+#if defined(GPIOI)
+#define LL_AHB1_GRP1_PERIPH_GPIOI           RCC_AHB1ENR_GPIOIEN
+#endif /* GPIOI */
+#if defined(GPIOJ)
+#define LL_AHB1_GRP1_PERIPH_GPIOJ           RCC_AHB1ENR_GPIOJEN
+#endif /* GPIOJ */
+#if defined(GPIOK)
+#define LL_AHB1_GRP1_PERIPH_GPIOK           RCC_AHB1ENR_GPIOKEN
+#endif /* GPIOK */
+#define LL_AHB1_GRP1_PERIPH_CRC             RCC_AHB1ENR_CRCEN
+#if defined(RCC_AHB1ENR_BKPSRAMEN)
+#define LL_AHB1_GRP1_PERIPH_BKPSRAM         RCC_AHB1ENR_BKPSRAMEN
+#endif /* RCC_AHB1ENR_BKPSRAMEN */
+#if defined(RCC_AHB1ENR_CCMDATARAMEN)
+#define LL_AHB1_GRP1_PERIPH_CCMDATARAM      RCC_AHB1ENR_CCMDATARAMEN
+#endif /* RCC_AHB1ENR_CCMDATARAMEN */
+#define LL_AHB1_GRP1_PERIPH_DMA1            RCC_AHB1ENR_DMA1EN
+#define LL_AHB1_GRP1_PERIPH_DMA2            RCC_AHB1ENR_DMA2EN
+#if defined(RCC_AHB1ENR_RNGEN)
+#define LL_AHB1_GRP1_PERIPH_RNG             RCC_AHB1ENR_RNGEN
+#endif /* RCC_AHB1ENR_RNGEN */
+#if defined(DMA2D)
+#define LL_AHB1_GRP1_PERIPH_DMA2D           RCC_AHB1ENR_DMA2DEN
+#endif /* DMA2D */
+#if defined(ETH)
+#define LL_AHB1_GRP1_PERIPH_ETHMAC          RCC_AHB1ENR_ETHMACEN
+#define LL_AHB1_GRP1_PERIPH_ETHMACTX        RCC_AHB1ENR_ETHMACTXEN
+#define LL_AHB1_GRP1_PERIPH_ETHMACRX        RCC_AHB1ENR_ETHMACRXEN
+#define LL_AHB1_GRP1_PERIPH_ETHMACPTP       RCC_AHB1ENR_ETHMACPTPEN
+#endif /* ETH */
+#if defined(USB_OTG_HS)
+#define LL_AHB1_GRP1_PERIPH_OTGHS           RCC_AHB1ENR_OTGHSEN
+#define LL_AHB1_GRP1_PERIPH_OTGHSULPI       RCC_AHB1ENR_OTGHSULPIEN
+#endif /* USB_OTG_HS */
+#define LL_AHB1_GRP1_PERIPH_FLITF           RCC_AHB1LPENR_FLITFLPEN
+#define LL_AHB1_GRP1_PERIPH_SRAM1           RCC_AHB1LPENR_SRAM1LPEN
+#if defined(RCC_AHB1LPENR_SRAM2LPEN)
+#define LL_AHB1_GRP1_PERIPH_SRAM2           RCC_AHB1LPENR_SRAM2LPEN
+#endif /* RCC_AHB1LPENR_SRAM2LPEN */
+#if defined(RCC_AHB1LPENR_SRAM3LPEN)
+#define LL_AHB1_GRP1_PERIPH_SRAM3           RCC_AHB1LPENR_SRAM3LPEN
+#endif /* RCC_AHB1LPENR_SRAM3LPEN */
+/**
+  * @}
+  */
+
+#if defined(RCC_AHB2_SUPPORT)
+/** @defgroup BUS_LL_EC_AHB2_GRP1_PERIPH  AHB2 GRP1 PERIPH
+  * @{
+  */
+#define LL_AHB2_GRP1_PERIPH_ALL            0xFFFFFFFFU
+#if defined(DCMI)
+#define LL_AHB2_GRP1_PERIPH_DCMI           RCC_AHB2ENR_DCMIEN
+#endif /* DCMI */
+#if defined(CRYP)
+#define LL_AHB2_GRP1_PERIPH_CRYP           RCC_AHB2ENR_CRYPEN
+#endif /* CRYP */
+#if defined(AES)
+#define LL_AHB2_GRP1_PERIPH_AES            RCC_AHB2ENR_AESEN
+#endif /* AES */
+#if defined(HASH)
+#define LL_AHB2_GRP1_PERIPH_HASH           RCC_AHB2ENR_HASHEN
+#endif /* HASH */
+#if defined(RCC_AHB2ENR_RNGEN)
+#define LL_AHB2_GRP1_PERIPH_RNG            RCC_AHB2ENR_RNGEN
+#endif /* RCC_AHB2ENR_RNGEN */
+#if defined(USB_OTG_FS)
+#define LL_AHB2_GRP1_PERIPH_OTGFS          RCC_AHB2ENR_OTGFSEN
+#endif /* USB_OTG_FS */
+/**
+  * @}
+  */
+#endif /* RCC_AHB2_SUPPORT */
+
+#if defined(RCC_AHB3_SUPPORT)
+/** @defgroup BUS_LL_EC_AHB3_GRP1_PERIPH  AHB3 GRP1 PERIPH
+  * @{
+  */
+#define LL_AHB3_GRP1_PERIPH_ALL            0xFFFFFFFFU
+#if defined(FSMC_Bank1)
+#define LL_AHB3_GRP1_PERIPH_FSMC           RCC_AHB3ENR_FSMCEN
+#endif /* FSMC_Bank1 */
+#if defined(FMC_Bank1)
+#define LL_AHB3_GRP1_PERIPH_FMC            RCC_AHB3ENR_FMCEN
+#endif /* FMC_Bank1 */
+#if defined(QUADSPI)
+#define LL_AHB3_GRP1_PERIPH_QSPI           RCC_AHB3ENR_QSPIEN
+#endif /* QUADSPI */
+/**
+  * @}
+  */
+#endif /* RCC_AHB3_SUPPORT */
+
+/** @defgroup BUS_LL_EC_APB1_GRP1_PERIPH  APB1 GRP1 PERIPH
+  * @{
+  */
+#define LL_APB1_GRP1_PERIPH_ALL            0xFFFFFFFFU
+#if defined(TIM2)
+#define LL_APB1_GRP1_PERIPH_TIM2           RCC_APB1ENR_TIM2EN
+#endif /* TIM2 */
+#if defined(TIM3)
+#define LL_APB1_GRP1_PERIPH_TIM3           RCC_APB1ENR_TIM3EN
+#endif /* TIM3 */
+#if defined(TIM4)
+#define LL_APB1_GRP1_PERIPH_TIM4           RCC_APB1ENR_TIM4EN
+#endif /* TIM4 */
+#define LL_APB1_GRP1_PERIPH_TIM5           RCC_APB1ENR_TIM5EN
+#if defined(TIM6)
+#define LL_APB1_GRP1_PERIPH_TIM6           RCC_APB1ENR_TIM6EN
+#endif /* TIM6 */
+#if defined(TIM7)
+#define LL_APB1_GRP1_PERIPH_TIM7           RCC_APB1ENR_TIM7EN
+#endif /* TIM7 */
+#if defined(TIM12)
+#define LL_APB1_GRP1_PERIPH_TIM12          RCC_APB1ENR_TIM12EN
+#endif /* TIM12 */
+#if defined(TIM13)
+#define LL_APB1_GRP1_PERIPH_TIM13          RCC_APB1ENR_TIM13EN
+#endif /* TIM13 */
+#if defined(TIM14)
+#define LL_APB1_GRP1_PERIPH_TIM14          RCC_APB1ENR_TIM14EN
+#endif /* TIM14 */
+#if defined(LPTIM1)
+#define LL_APB1_GRP1_PERIPH_LPTIM1         RCC_APB1ENR_LPTIM1EN
+#endif /* LPTIM1 */
+#if defined(RCC_APB1ENR_RTCAPBEN)
+#define LL_APB1_GRP1_PERIPH_RTCAPB         RCC_APB1ENR_RTCAPBEN
+#endif /* RCC_APB1ENR_RTCAPBEN */
+#define LL_APB1_GRP1_PERIPH_WWDG           RCC_APB1ENR_WWDGEN
+#if defined(SPI2)
+#define LL_APB1_GRP1_PERIPH_SPI2           RCC_APB1ENR_SPI2EN
+#endif /* SPI2 */
+#if defined(SPI3)
+#define LL_APB1_GRP1_PERIPH_SPI3           RCC_APB1ENR_SPI3EN
+#endif /* SPI3 */
+#if defined(SPDIFRX)
+#define LL_APB1_GRP1_PERIPH_SPDIFRX        RCC_APB1ENR_SPDIFRXEN
+#endif /* SPDIFRX */
+#define LL_APB1_GRP1_PERIPH_USART2         RCC_APB1ENR_USART2EN
+#if defined(USART3)
+#define LL_APB1_GRP1_PERIPH_USART3         RCC_APB1ENR_USART3EN
+#endif /* USART3 */
+#if defined(UART4)
+#define LL_APB1_GRP1_PERIPH_UART4          RCC_APB1ENR_UART4EN
+#endif /* UART4 */
+#if defined(UART5)
+#define LL_APB1_GRP1_PERIPH_UART5          RCC_APB1ENR_UART5EN
+#endif /* UART5 */
+#define LL_APB1_GRP1_PERIPH_I2C1           RCC_APB1ENR_I2C1EN
+#define LL_APB1_GRP1_PERIPH_I2C2           RCC_APB1ENR_I2C2EN
+#if defined(I2C3)
+#define LL_APB1_GRP1_PERIPH_I2C3           RCC_APB1ENR_I2C3EN
+#endif /* I2C3 */
+#if defined(FMPI2C1)
+#define LL_APB1_GRP1_PERIPH_FMPI2C1        RCC_APB1ENR_FMPI2C1EN
+#endif /* FMPI2C1 */
+#if defined(CAN1)
+#define LL_APB1_GRP1_PERIPH_CAN1           RCC_APB1ENR_CAN1EN
+#endif /* CAN1 */
+#if defined(CAN2)
+#define LL_APB1_GRP1_PERIPH_CAN2           RCC_APB1ENR_CAN2EN
+#endif /* CAN2 */
+#if defined(CAN3)
+#define LL_APB1_GRP1_PERIPH_CAN3           RCC_APB1ENR_CAN3EN
+#endif /* CAN3 */
+#if defined(CEC)
+#define LL_APB1_GRP1_PERIPH_CEC            RCC_APB1ENR_CECEN
+#endif /* CEC */
+#define LL_APB1_GRP1_PERIPH_PWR            RCC_APB1ENR_PWREN
+#if defined(DAC1)
+#define LL_APB1_GRP1_PERIPH_DAC1           RCC_APB1ENR_DACEN
+#endif /* DAC1 */
+#if defined(UART7)
+#define LL_APB1_GRP1_PERIPH_UART7          RCC_APB1ENR_UART7EN
+#endif /* UART7 */
+#if defined(UART8)
+#define LL_APB1_GRP1_PERIPH_UART8          RCC_APB1ENR_UART8EN
+#endif /* UART8 */
+/**
+  * @}
+  */
+
+/** @defgroup BUS_LL_EC_APB2_GRP1_PERIPH  APB2 GRP1 PERIPH
+  * @{
+  */
+#define LL_APB2_GRP1_PERIPH_ALL          0xFFFFFFFFU
+#define LL_APB2_GRP1_PERIPH_TIM1         RCC_APB2ENR_TIM1EN
+#if defined(TIM8)
+#define LL_APB2_GRP1_PERIPH_TIM8         RCC_APB2ENR_TIM8EN
+#endif /* TIM8 */
+#define LL_APB2_GRP1_PERIPH_USART1       RCC_APB2ENR_USART1EN
+#if defined(USART6)
+#define LL_APB2_GRP1_PERIPH_USART6       RCC_APB2ENR_USART6EN
+#endif /* USART6 */
+#if defined(UART9)
+#define LL_APB2_GRP1_PERIPH_UART9        RCC_APB2ENR_UART9EN
+#endif /* UART9 */
+#if defined(UART10)
+#define LL_APB2_GRP1_PERIPH_UART10       RCC_APB2ENR_UART10EN
+#endif /* UART10 */
+#define LL_APB2_GRP1_PERIPH_ADC1         RCC_APB2ENR_ADC1EN
+#if defined(ADC2)
+#define LL_APB2_GRP1_PERIPH_ADC2         RCC_APB2ENR_ADC2EN
+#endif /* ADC2 */
+#if defined(ADC3)
+#define LL_APB2_GRP1_PERIPH_ADC3         RCC_APB2ENR_ADC3EN
+#endif /* ADC3 */
+#if defined(SDIO)
+#define LL_APB2_GRP1_PERIPH_SDIO         RCC_APB2ENR_SDIOEN
+#endif /* SDIO */
+#define LL_APB2_GRP1_PERIPH_SPI1         RCC_APB2ENR_SPI1EN
+#if defined(SPI4)
+#define LL_APB2_GRP1_PERIPH_SPI4         RCC_APB2ENR_SPI4EN
+#endif /* SPI4 */
+#define LL_APB2_GRP1_PERIPH_SYSCFG       RCC_APB2ENR_SYSCFGEN
+#if defined(RCC_APB2ENR_EXTITEN)
+#define LL_APB2_GRP1_PERIPH_EXTI         RCC_APB2ENR_EXTITEN
+#endif /* RCC_APB2ENR_EXTITEN */
+#define LL_APB2_GRP1_PERIPH_TIM9         RCC_APB2ENR_TIM9EN
+#if defined(TIM10)
+#define LL_APB2_GRP1_PERIPH_TIM10        RCC_APB2ENR_TIM10EN
+#endif /* TIM10 */
+#define LL_APB2_GRP1_PERIPH_TIM11        RCC_APB2ENR_TIM11EN
+#if defined(SPI5)
+#define LL_APB2_GRP1_PERIPH_SPI5         RCC_APB2ENR_SPI5EN
+#endif /* SPI5 */
+#if defined(SPI6)
+#define LL_APB2_GRP1_PERIPH_SPI6         RCC_APB2ENR_SPI6EN
+#endif /* SPI6 */
+#if defined(SAI1)
+#define LL_APB2_GRP1_PERIPH_SAI1         RCC_APB2ENR_SAI1EN
+#endif /* SAI1 */
+#if defined(SAI2)
+#define LL_APB2_GRP1_PERIPH_SAI2         RCC_APB2ENR_SAI2EN
+#endif /* SAI2 */
+#if defined(LTDC)
+#define LL_APB2_GRP1_PERIPH_LTDC         RCC_APB2ENR_LTDCEN
+#endif /* LTDC */
+#if defined(DSI)
+#define LL_APB2_GRP1_PERIPH_DSI          RCC_APB2ENR_DSIEN
+#endif /* DSI */
+#if defined(DFSDM1_Channel0)
+#define LL_APB2_GRP1_PERIPH_DFSDM1       RCC_APB2ENR_DFSDM1EN
+#endif /* DFSDM1_Channel0 */
+#if defined(DFSDM2_Channel0)
+#define LL_APB2_GRP1_PERIPH_DFSDM2       RCC_APB2ENR_DFSDM2EN
+#endif /* DFSDM2_Channel0 */
+#define LL_APB2_GRP1_PERIPH_ADC          RCC_APB2RSTR_ADCRST
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup BUS_LL_Exported_Functions BUS Exported Functions
+  * @{
+  */
+
+/** @defgroup BUS_LL_EF_AHB1 AHB1
+  * @{
+  */
+
+/**
+  * @brief  Enable AHB1 peripherals clock.
+  * @rmtoll AHB1ENR      GPIOAEN            LL_AHB1_GRP1_EnableClock\n
+  *         AHB1ENR      GPIOBEN            LL_AHB1_GRP1_EnableClock\n
+  *         AHB1ENR      GPIOCEN            LL_AHB1_GRP1_EnableClock\n
+  *         AHB1ENR      GPIODEN            LL_AHB1_GRP1_EnableClock\n
+  *         AHB1ENR      GPIOEEN            LL_AHB1_GRP1_EnableClock\n
+  *         AHB1ENR      GPIOFEN            LL_AHB1_GRP1_EnableClock\n
+  *         AHB1ENR      GPIOGEN            LL_AHB1_GRP1_EnableClock\n
+  *         AHB1ENR      GPIOHEN            LL_AHB1_GRP1_EnableClock\n
+  *         AHB1ENR      GPIOIEN            LL_AHB1_GRP1_EnableClock\n
+  *         AHB1ENR      GPIOJEN            LL_AHB1_GRP1_EnableClock\n
+  *         AHB1ENR      GPIOKEN            LL_AHB1_GRP1_EnableClock\n
+  *         AHB1ENR      CRCEN              LL_AHB1_GRP1_EnableClock\n
+  *         AHB1ENR      BKPSRAMEN          LL_AHB1_GRP1_EnableClock\n
+  *         AHB1ENR      CCMDATARAMEN       LL_AHB1_GRP1_EnableClock\n
+  *         AHB1ENR      DMA1EN             LL_AHB1_GRP1_EnableClock\n
+  *         AHB1ENR      DMA2EN             LL_AHB1_GRP1_EnableClock\n
+  *         AHB1ENR      RNGEN              LL_AHB1_GRP1_EnableClock\n
+  *         AHB1ENR      DMA2DEN            LL_AHB1_GRP1_EnableClock\n
+  *         AHB1ENR      ETHMACEN           LL_AHB1_GRP1_EnableClock\n
+  *         AHB1ENR      ETHMACTXEN         LL_AHB1_GRP1_EnableClock\n
+  *         AHB1ENR      ETHMACRXEN         LL_AHB1_GRP1_EnableClock\n
+  *         AHB1ENR      ETHMACPTPEN        LL_AHB1_GRP1_EnableClock\n
+  *         AHB1ENR      OTGHSEN            LL_AHB1_GRP1_EnableClock\n
+  *         AHB1ENR      OTGHSULPIEN        LL_AHB1_GRP1_EnableClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_CCMDATARAM (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC->AHB1ENR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC->AHB1ENR, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Check if AHB1 peripheral clock is enabled or not
+  * @rmtoll AHB1ENR      GPIOAEN            LL_AHB1_GRP1_IsEnabledClock\n
+  *         AHB1ENR      GPIOBEN            LL_AHB1_GRP1_IsEnabledClock\n
+  *         AHB1ENR      GPIOCEN            LL_AHB1_GRP1_IsEnabledClock\n
+  *         AHB1ENR      GPIODEN            LL_AHB1_GRP1_IsEnabledClock\n
+  *         AHB1ENR      GPIOEEN            LL_AHB1_GRP1_IsEnabledClock\n
+  *         AHB1ENR      GPIOFEN            LL_AHB1_GRP1_IsEnabledClock\n
+  *         AHB1ENR      GPIOGEN            LL_AHB1_GRP1_IsEnabledClock\n
+  *         AHB1ENR      GPIOHEN            LL_AHB1_GRP1_IsEnabledClock\n
+  *         AHB1ENR      GPIOIEN            LL_AHB1_GRP1_IsEnabledClock\n
+  *         AHB1ENR      GPIOJEN            LL_AHB1_GRP1_IsEnabledClock\n
+  *         AHB1ENR      GPIOKEN            LL_AHB1_GRP1_IsEnabledClock\n
+  *         AHB1ENR      CRCEN              LL_AHB1_GRP1_IsEnabledClock\n
+  *         AHB1ENR      BKPSRAMEN          LL_AHB1_GRP1_IsEnabledClock\n
+  *         AHB1ENR      CCMDATARAMEN       LL_AHB1_GRP1_IsEnabledClock\n
+  *         AHB1ENR      DMA1EN             LL_AHB1_GRP1_IsEnabledClock\n
+  *         AHB1ENR      DMA2EN             LL_AHB1_GRP1_IsEnabledClock\n
+  *         AHB1ENR      RNGEN              LL_AHB1_GRP1_IsEnabledClock\n
+  *         AHB1ENR      DMA2DEN            LL_AHB1_GRP1_IsEnabledClock\n
+  *         AHB1ENR      ETHMACEN           LL_AHB1_GRP1_IsEnabledClock\n
+  *         AHB1ENR      ETHMACTXEN         LL_AHB1_GRP1_IsEnabledClock\n
+  *         AHB1ENR      ETHMACRXEN         LL_AHB1_GRP1_IsEnabledClock\n
+  *         AHB1ENR      ETHMACPTPEN        LL_AHB1_GRP1_IsEnabledClock\n
+  *         AHB1ENR      OTGHSEN            LL_AHB1_GRP1_IsEnabledClock\n
+  *         AHB1ENR      OTGHSULPIEN        LL_AHB1_GRP1_IsEnabledClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_CCMDATARAM (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval State of Periphs (1 or 0).
+*/
+__STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs)
+{
+  return (READ_BIT(RCC->AHB1ENR, Periphs) == Periphs);
+}
+
+/**
+  * @brief  Disable AHB1 peripherals clock.
+  * @rmtoll AHB1ENR      GPIOAEN            LL_AHB1_GRP1_DisableClock\n
+  *         AHB1ENR      GPIOBEN            LL_AHB1_GRP1_DisableClock\n
+  *         AHB1ENR      GPIOCEN            LL_AHB1_GRP1_DisableClock\n
+  *         AHB1ENR      GPIODEN            LL_AHB1_GRP1_DisableClock\n
+  *         AHB1ENR      GPIOEEN            LL_AHB1_GRP1_DisableClock\n
+  *         AHB1ENR      GPIOFEN            LL_AHB1_GRP1_DisableClock\n
+  *         AHB1ENR      GPIOGEN            LL_AHB1_GRP1_DisableClock\n
+  *         AHB1ENR      GPIOHEN            LL_AHB1_GRP1_DisableClock\n
+  *         AHB1ENR      GPIOIEN            LL_AHB1_GRP1_DisableClock\n
+  *         AHB1ENR      GPIOJEN            LL_AHB1_GRP1_DisableClock\n
+  *         AHB1ENR      GPIOKEN            LL_AHB1_GRP1_DisableClock\n
+  *         AHB1ENR      CRCEN              LL_AHB1_GRP1_DisableClock\n
+  *         AHB1ENR      BKPSRAMEN          LL_AHB1_GRP1_DisableClock\n
+  *         AHB1ENR      CCMDATARAMEN       LL_AHB1_GRP1_DisableClock\n
+  *         AHB1ENR      DMA1EN             LL_AHB1_GRP1_DisableClock\n
+  *         AHB1ENR      DMA2EN             LL_AHB1_GRP1_DisableClock\n
+  *         AHB1ENR      RNGEN              LL_AHB1_GRP1_DisableClock\n
+  *         AHB1ENR      DMA2DEN            LL_AHB1_GRP1_DisableClock\n
+  *         AHB1ENR      ETHMACEN           LL_AHB1_GRP1_DisableClock\n
+  *         AHB1ENR      ETHMACTXEN         LL_AHB1_GRP1_DisableClock\n
+  *         AHB1ENR      ETHMACRXEN         LL_AHB1_GRP1_DisableClock\n
+  *         AHB1ENR      ETHMACPTPEN        LL_AHB1_GRP1_DisableClock\n
+  *         AHB1ENR      OTGHSEN            LL_AHB1_GRP1_DisableClock\n
+  *         AHB1ENR      OTGHSULPIEN        LL_AHB1_GRP1_DisableClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_CCMDATARAM (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC->AHB1ENR, Periphs);
+}
+
+/**
+  * @brief  Force AHB1 peripherals reset.
+  * @rmtoll AHB1RSTR     GPIOARST      LL_AHB1_GRP1_ForceReset\n
+  *         AHB1RSTR     GPIOBRST      LL_AHB1_GRP1_ForceReset\n
+  *         AHB1RSTR     GPIOCRST      LL_AHB1_GRP1_ForceReset\n
+  *         AHB1RSTR     GPIODRST      LL_AHB1_GRP1_ForceReset\n
+  *         AHB1RSTR     GPIOERST      LL_AHB1_GRP1_ForceReset\n
+  *         AHB1RSTR     GPIOFRST      LL_AHB1_GRP1_ForceReset\n
+  *         AHB1RSTR     GPIOGRST      LL_AHB1_GRP1_ForceReset\n
+  *         AHB1RSTR     GPIOHRST      LL_AHB1_GRP1_ForceReset\n
+  *         AHB1RSTR     GPIOIRST      LL_AHB1_GRP1_ForceReset\n
+  *         AHB1RSTR     GPIOJRST      LL_AHB1_GRP1_ForceReset\n
+  *         AHB1RSTR     GPIOKRST      LL_AHB1_GRP1_ForceReset\n
+  *         AHB1RSTR     CRCRST        LL_AHB1_GRP1_ForceReset\n
+  *         AHB1RSTR     DMA1RST       LL_AHB1_GRP1_ForceReset\n
+  *         AHB1RSTR     DMA2RST       LL_AHB1_GRP1_ForceReset\n
+  *         AHB1RSTR     RNGRST        LL_AHB1_GRP1_ForceReset\n
+  *         AHB1RSTR     DMA2DRST      LL_AHB1_GRP1_ForceReset\n
+  *         AHB1RSTR     ETHMACRST     LL_AHB1_GRP1_ForceReset\n
+  *         AHB1RSTR     OTGHSRST      LL_AHB1_GRP1_ForceReset
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ALL
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs)
+{
+  SET_BIT(RCC->AHB1RSTR, Periphs);
+}
+
+/**
+  * @brief  Release AHB1 peripherals reset.
+  * @rmtoll AHB1RSTR     GPIOARST      LL_AHB1_GRP1_ReleaseReset\n
+  *         AHB1RSTR     GPIOBRST      LL_AHB1_GRP1_ReleaseReset\n
+  *         AHB1RSTR     GPIOCRST      LL_AHB1_GRP1_ReleaseReset\n
+  *         AHB1RSTR     GPIODRST      LL_AHB1_GRP1_ReleaseReset\n
+  *         AHB1RSTR     GPIOERST      LL_AHB1_GRP1_ReleaseReset\n
+  *         AHB1RSTR     GPIOFRST      LL_AHB1_GRP1_ReleaseReset\n
+  *         AHB1RSTR     GPIOGRST      LL_AHB1_GRP1_ReleaseReset\n
+  *         AHB1RSTR     GPIOHRST      LL_AHB1_GRP1_ReleaseReset\n
+  *         AHB1RSTR     GPIOIRST      LL_AHB1_GRP1_ReleaseReset\n
+  *         AHB1RSTR     GPIOJRST      LL_AHB1_GRP1_ReleaseReset\n
+  *         AHB1RSTR     GPIOKRST      LL_AHB1_GRP1_ReleaseReset\n
+  *         AHB1RSTR     CRCRST        LL_AHB1_GRP1_ReleaseReset\n
+  *         AHB1RSTR     DMA1RST       LL_AHB1_GRP1_ReleaseReset\n
+  *         AHB1RSTR     DMA2RST       LL_AHB1_GRP1_ReleaseReset\n
+  *         AHB1RSTR     RNGRST        LL_AHB1_GRP1_ReleaseReset\n
+  *         AHB1RSTR     DMA2DRST      LL_AHB1_GRP1_ReleaseReset\n
+  *         AHB1RSTR     ETHMACRST     LL_AHB1_GRP1_ReleaseReset\n
+  *         AHB1RSTR     OTGHSRST      LL_AHB1_GRP1_ReleaseReset
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ALL
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC->AHB1RSTR, Periphs);
+}
+
+/**
+  * @brief  Enable AHB1 peripheral clocks in low-power mode
+  * @rmtoll AHB1LPENR    GPIOALPEN      LL_AHB1_GRP1_EnableClockLowPower\n
+  *         AHB1LPENR    GPIOBLPEN      LL_AHB1_GRP1_EnableClockLowPower\n
+  *         AHB1LPENR    GPIOCLPEN      LL_AHB1_GRP1_EnableClockLowPower\n
+  *         AHB1LPENR    GPIODLPEN      LL_AHB1_GRP1_EnableClockLowPower\n
+  *         AHB1LPENR    GPIOELPEN      LL_AHB1_GRP1_EnableClockLowPower\n
+  *         AHB1LPENR    GPIOFLPEN      LL_AHB1_GRP1_EnableClockLowPower\n
+  *         AHB1LPENR    GPIOGLPEN      LL_AHB1_GRP1_EnableClockLowPower\n
+  *         AHB1LPENR    GPIOHLPEN      LL_AHB1_GRP1_EnableClockLowPower\n
+  *         AHB1LPENR    GPIOILPEN      LL_AHB1_GRP1_EnableClockLowPower\n
+  *         AHB1LPENR    GPIOJLPEN      LL_AHB1_GRP1_EnableClockLowPower\n
+  *         AHB1LPENR    GPIOKLPEN      LL_AHB1_GRP1_EnableClockLowPower\n
+  *         AHB1LPENR    CRCLPEN        LL_AHB1_GRP1_EnableClockLowPower\n
+  *         AHB1LPENR    BKPSRAMLPEN    LL_AHB1_GRP1_EnableClockLowPower\n
+  *         AHB1LPENR    FLITFLPEN      LL_AHB1_GRP1_EnableClockLowPower\n
+  *         AHB1LPENR    SRAM1LPEN      LL_AHB1_GRP1_EnableClockLowPower\n
+  *         AHB1LPENR    SRAM2LPEN      LL_AHB1_GRP1_EnableClockLowPower\n
+  *         AHB1LPENR    SRAM3LPEN      LL_AHB1_GRP1_EnableClockLowPower\n
+  *         AHB1LPENR    BKPSRAMLPEN    LL_AHB1_GRP1_EnableClockLowPower\n
+  *         AHB1LPENR    DMA1LPEN       LL_AHB1_GRP1_EnableClockLowPower\n
+  *         AHB1LPENR    DMA2LPEN       LL_AHB1_GRP1_EnableClockLowPower\n
+  *         AHB1LPENR    DMA2DLPEN      LL_AHB1_GRP1_EnableClockLowPower\n
+  *         AHB1LPENR    RNGLPEN        LL_AHB1_GRP1_EnableClockLowPower\n
+  *         AHB1LPENR    ETHMACLPEN     LL_AHB1_GRP1_EnableClockLowPower\n
+  *         AHB1LPENR    ETHMACTXLPEN   LL_AHB1_GRP1_EnableClockLowPower\n
+  *         AHB1LPENR    ETHMACRXLPEN   LL_AHB1_GRP1_EnableClockLowPower\n
+  *         AHB1LPENR    ETHMACPTPLPEN  LL_AHB1_GRP1_EnableClockLowPower\n
+  *         AHB1LPENR    OTGHSLPEN      LL_AHB1_GRP1_EnableClockLowPower\n
+  *         AHB1LPENR    OTGHSULPILPEN  LL_AHB1_GRP1_EnableClockLowPower
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_FLITF
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_SRAM2 (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_SRAM3 (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_AHB1_GRP1_EnableClockLowPower(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC->AHB1LPENR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC->AHB1LPENR, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Disable AHB1 peripheral clocks in low-power mode
+  * @rmtoll AHB1LPENR    GPIOALPEN      LL_AHB1_GRP1_DisableClockLowPower\n
+  *         AHB1LPENR    GPIOBLPEN      LL_AHB1_GRP1_DisableClockLowPower\n
+  *         AHB1LPENR    GPIOCLPEN      LL_AHB1_GRP1_DisableClockLowPower\n
+  *         AHB1LPENR    GPIODLPEN      LL_AHB1_GRP1_DisableClockLowPower\n
+  *         AHB1LPENR    GPIOELPEN      LL_AHB1_GRP1_DisableClockLowPower\n
+  *         AHB1LPENR    GPIOFLPEN      LL_AHB1_GRP1_DisableClockLowPower\n
+  *         AHB1LPENR    GPIOGLPEN      LL_AHB1_GRP1_DisableClockLowPower\n
+  *         AHB1LPENR    GPIOHLPEN      LL_AHB1_GRP1_DisableClockLowPower\n
+  *         AHB1LPENR    GPIOILPEN      LL_AHB1_GRP1_DisableClockLowPower\n
+  *         AHB1LPENR    GPIOJLPEN      LL_AHB1_GRP1_DisableClockLowPower\n
+  *         AHB1LPENR    GPIOKLPEN      LL_AHB1_GRP1_DisableClockLowPower\n
+  *         AHB1LPENR    CRCLPEN        LL_AHB1_GRP1_DisableClockLowPower\n
+  *         AHB1LPENR    BKPSRAMLPEN    LL_AHB1_GRP1_DisableClockLowPower\n
+  *         AHB1LPENR    FLITFLPEN      LL_AHB1_GRP1_DisableClockLowPower\n
+  *         AHB1LPENR    SRAM1LPEN      LL_AHB1_GRP1_DisableClockLowPower\n
+  *         AHB1LPENR    SRAM2LPEN      LL_AHB1_GRP1_DisableClockLowPower\n
+  *         AHB1LPENR    SRAM3LPEN      LL_AHB1_GRP1_DisableClockLowPower\n
+  *         AHB1LPENR    BKPSRAMLPEN    LL_AHB1_GRP1_DisableClockLowPower\n
+  *         AHB1LPENR    DMA1LPEN       LL_AHB1_GRP1_DisableClockLowPower\n
+  *         AHB1LPENR    DMA2LPEN       LL_AHB1_GRP1_DisableClockLowPower\n
+  *         AHB1LPENR    DMA2DLPEN      LL_AHB1_GRP1_DisableClockLowPower\n
+  *         AHB1LPENR    RNGLPEN        LL_AHB1_GRP1_DisableClockLowPower\n
+  *         AHB1LPENR    ETHMACLPEN     LL_AHB1_GRP1_DisableClockLowPower\n
+  *         AHB1LPENR    ETHMACTXLPEN   LL_AHB1_GRP1_DisableClockLowPower\n
+  *         AHB1LPENR    ETHMACRXLPEN   LL_AHB1_GRP1_DisableClockLowPower\n
+  *         AHB1LPENR    ETHMACPTPLPEN  LL_AHB1_GRP1_DisableClockLowPower\n
+  *         AHB1LPENR    OTGHSLPEN      LL_AHB1_GRP1_DisableClockLowPower\n
+  *         AHB1LPENR    OTGHSULPILPEN  LL_AHB1_GRP1_DisableClockLowPower
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_FLITF
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_SRAM2 (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_SRAM3 (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_AHB1_GRP1_DisableClockLowPower(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC->AHB1LPENR, Periphs);
+}
+
+/**
+  * @}
+  */
+
+#if defined(RCC_AHB2_SUPPORT)
+/** @defgroup BUS_LL_EF_AHB2 AHB2
+  * @{
+  */
+
+/**
+  * @brief  Enable AHB2 peripherals clock.
+  * @rmtoll AHB2ENR      DCMIEN       LL_AHB2_GRP1_EnableClock\n
+  *         AHB2ENR      CRYPEN       LL_AHB2_GRP1_EnableClock\n
+  *         AHB2ENR      AESEN        LL_AHB2_GRP1_EnableClock\n
+  *         AHB2ENR      HASHEN       LL_AHB2_GRP1_EnableClock\n
+  *         AHB2ENR      RNGEN        LL_AHB2_GRP1_EnableClock\n
+  *         AHB2ENR      OTGFSEN      LL_AHB2_GRP1_EnableClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_AES  (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_AHB2_GRP1_EnableClock(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC->AHB2ENR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC->AHB2ENR, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Check if AHB2 peripheral clock is enabled or not
+  * @rmtoll AHB2ENR      DCMIEN       LL_AHB2_GRP1_IsEnabledClock\n
+  *         AHB2ENR      CRYPEN       LL_AHB2_GRP1_IsEnabledClock\n
+  *         AHB2ENR      AESEN        LL_AHB2_GRP1_IsEnabledClock\n
+  *         AHB2ENR      HASHEN       LL_AHB2_GRP1_IsEnabledClock\n
+  *         AHB2ENR      RNGEN        LL_AHB2_GRP1_IsEnabledClock\n
+  *         AHB2ENR      OTGFSEN      LL_AHB2_GRP1_IsEnabledClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_AES  (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval State of Periphs (1 or 0).
+*/
+__STATIC_INLINE uint32_t LL_AHB2_GRP1_IsEnabledClock(uint32_t Periphs)
+{
+  return (READ_BIT(RCC->AHB2ENR, Periphs) == Periphs);
+}
+
+/**
+  * @brief  Disable AHB2 peripherals clock.
+  * @rmtoll AHB2ENR      DCMIEN       LL_AHB2_GRP1_DisableClock\n
+  *         AHB2ENR      CRYPEN       LL_AHB2_GRP1_DisableClock\n
+  *         AHB2ENR      AESEN        LL_AHB2_GRP1_DisableClock\n
+  *         AHB2ENR      HASHEN       LL_AHB2_GRP1_DisableClock\n
+  *         AHB2ENR      RNGEN        LL_AHB2_GRP1_DisableClock\n
+  *         AHB2ENR      OTGFSEN      LL_AHB2_GRP1_DisableClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_AES  (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_AHB2_GRP1_DisableClock(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC->AHB2ENR, Periphs);
+}
+
+/**
+  * @brief  Force AHB2 peripherals reset.
+  * @rmtoll AHB2RSTR     DCMIRST      LL_AHB2_GRP1_ForceReset\n
+  *         AHB2RSTR     CRYPRST      LL_AHB2_GRP1_ForceReset\n
+  *         AHB2RSTR     AESRST       LL_AHB2_GRP1_ForceReset\n
+  *         AHB2RSTR     HASHRST      LL_AHB2_GRP1_ForceReset\n
+  *         AHB2RSTR     RNGRST       LL_AHB2_GRP1_ForceReset\n
+  *         AHB2RSTR     OTGFSRST     LL_AHB2_GRP1_ForceReset
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_ALL
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_AES  (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_AHB2_GRP1_ForceReset(uint32_t Periphs)
+{
+  SET_BIT(RCC->AHB2RSTR, Periphs);
+}
+
+/**
+  * @brief  Release AHB2 peripherals reset.
+  * @rmtoll AHB2RSTR     DCMIRST      LL_AHB2_GRP1_ReleaseReset\n
+  *         AHB2RSTR     CRYPRST      LL_AHB2_GRP1_ReleaseReset\n
+  *         AHB2RSTR     AESRST       LL_AHB2_GRP1_ReleaseReset\n
+  *         AHB2RSTR     HASHRST      LL_AHB2_GRP1_ReleaseReset\n
+  *         AHB2RSTR     RNGRST       LL_AHB2_GRP1_ReleaseReset\n
+  *         AHB2RSTR     OTGFSRST     LL_AHB2_GRP1_ReleaseReset
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_ALL
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_AES  (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_AHB2_GRP1_ReleaseReset(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC->AHB2RSTR, Periphs);
+}
+
+/**
+  * @brief  Enable AHB2 peripheral clocks in low-power mode
+  * @rmtoll AHB2LPENR    DCMILPEN     LL_AHB2_GRP1_EnableClockLowPower\n
+  *         AHB2LPENR    CRYPLPEN     LL_AHB2_GRP1_EnableClockLowPower\n
+  *         AHB2LPENR    AESLPEN      LL_AHB2_GRP1_EnableClockLowPower\n
+  *         AHB2LPENR    HASHLPEN     LL_AHB2_GRP1_EnableClockLowPower\n
+  *         AHB2LPENR    RNGLPEN      LL_AHB2_GRP1_EnableClockLowPower\n
+  *         AHB2LPENR    OTGFSLPEN    LL_AHB2_GRP1_EnableClockLowPower
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_AES  (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_AHB2_GRP1_EnableClockLowPower(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC->AHB2LPENR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC->AHB2LPENR, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Disable AHB2 peripheral clocks in low-power mode
+  * @rmtoll AHB2LPENR    DCMILPEN     LL_AHB2_GRP1_DisableClockLowPower\n
+  *         AHB2LPENR    CRYPLPEN     LL_AHB2_GRP1_DisableClockLowPower\n
+  *         AHB2LPENR    AESLPEN      LL_AHB2_GRP1_DisableClockLowPower\n
+  *         AHB2LPENR    HASHLPEN     LL_AHB2_GRP1_DisableClockLowPower\n
+  *         AHB2LPENR    RNGLPEN      LL_AHB2_GRP1_DisableClockLowPower\n
+  *         AHB2LPENR    OTGFSLPEN    LL_AHB2_GRP1_DisableClockLowPower
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_AES  (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_AHB2_GRP1_DisableClockLowPower(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC->AHB2LPENR, Periphs);
+}
+
+/**
+  * @}
+  */
+#endif /* RCC_AHB2_SUPPORT */
+
+#if defined(RCC_AHB3_SUPPORT)
+/** @defgroup BUS_LL_EF_AHB3 AHB3
+  * @{
+  */
+
+/**
+  * @brief  Enable AHB3 peripherals clock.
+  * @rmtoll AHB3ENR      FMCEN         LL_AHB3_GRP1_EnableClock\n
+  *         AHB3ENR      FSMCEN        LL_AHB3_GRP1_EnableClock\n
+  *         AHB3ENR      QSPIEN        LL_AHB3_GRP1_EnableClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_FSMC (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_AHB3_GRP1_EnableClock(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC->AHB3ENR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC->AHB3ENR, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Check if AHB3 peripheral clock is enabled or not
+  * @rmtoll AHB3ENR      FMCEN         LL_AHB3_GRP1_IsEnabledClock\n
+  *         AHB3ENR      FSMCEN        LL_AHB3_GRP1_IsEnabledClock\n
+  *         AHB3ENR      QSPIEN        LL_AHB3_GRP1_IsEnabledClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_FSMC (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval State of Periphs (1 or 0).
+*/
+__STATIC_INLINE uint32_t LL_AHB3_GRP1_IsEnabledClock(uint32_t Periphs)
+{
+  return (READ_BIT(RCC->AHB3ENR, Periphs) == Periphs);
+}
+
+/**
+  * @brief  Disable AHB3 peripherals clock.
+  * @rmtoll AHB3ENR      FMCEN         LL_AHB3_GRP1_DisableClock\n
+  *         AHB3ENR      FSMCEN        LL_AHB3_GRP1_DisableClock\n
+  *         AHB3ENR      QSPIEN        LL_AHB3_GRP1_DisableClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_FSMC (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_AHB3_GRP1_DisableClock(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC->AHB3ENR, Periphs);
+}
+
+/**
+  * @brief  Force AHB3 peripherals reset.
+  * @rmtoll AHB3RSTR     FMCRST        LL_AHB3_GRP1_ForceReset\n
+  *         AHB3RSTR     FSMCRST       LL_AHB3_GRP1_ForceReset\n
+  *         AHB3RSTR     QSPIRST       LL_AHB3_GRP1_ForceReset
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_ALL
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_FSMC (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_AHB3_GRP1_ForceReset(uint32_t Periphs)
+{
+  SET_BIT(RCC->AHB3RSTR, Periphs);
+}
+
+/**
+  * @brief  Release AHB3 peripherals reset.
+  * @rmtoll AHB3RSTR     FMCRST        LL_AHB3_GRP1_ReleaseReset\n
+  *         AHB3RSTR     FSMCRST       LL_AHB3_GRP1_ReleaseReset\n
+  *         AHB3RSTR     QSPIRST       LL_AHB3_GRP1_ReleaseReset
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_ALL
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_FSMC (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_AHB3_GRP1_ReleaseReset(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC->AHB3RSTR, Periphs);
+}
+
+/**
+  * @brief  Enable AHB3 peripheral clocks in low-power mode
+  * @rmtoll AHB3LPENR    FMCLPEN       LL_AHB3_GRP1_EnableClockLowPower\n
+  *         AHB3LPENR    FSMCLPEN      LL_AHB3_GRP1_EnableClockLowPower\n
+  *         AHB3LPENR    QSPILPEN      LL_AHB3_GRP1_EnableClockLowPower
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_FSMC (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_AHB3_GRP1_EnableClockLowPower(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC->AHB3LPENR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC->AHB3LPENR, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Disable AHB3 peripheral clocks in low-power mode
+  * @rmtoll AHB3LPENR    FMCLPEN       LL_AHB3_GRP1_DisableClockLowPower\n
+  *         AHB3LPENR    FSMCLPEN      LL_AHB3_GRP1_DisableClockLowPower\n
+  *         AHB3LPENR    QSPILPEN      LL_AHB3_GRP1_DisableClockLowPower
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_FSMC (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_AHB3_GRP1_DisableClockLowPower(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC->AHB3LPENR, Periphs);
+}
+
+/**
+  * @}
+  */
+#endif /* RCC_AHB3_SUPPORT */
+
+/** @defgroup BUS_LL_EF_APB1 APB1
+  * @{
+  */
+
+/**
+  * @brief  Enable APB1 peripherals clock.
+  * @rmtoll APB1ENR     TIM2EN        LL_APB1_GRP1_EnableClock\n
+  *         APB1ENR     TIM3EN        LL_APB1_GRP1_EnableClock\n
+  *         APB1ENR     TIM4EN        LL_APB1_GRP1_EnableClock\n
+  *         APB1ENR     TIM5EN        LL_APB1_GRP1_EnableClock\n
+  *         APB1ENR     TIM6EN        LL_APB1_GRP1_EnableClock\n
+  *         APB1ENR     TIM7EN        LL_APB1_GRP1_EnableClock\n
+  *         APB1ENR     TIM12EN       LL_APB1_GRP1_EnableClock\n
+  *         APB1ENR     TIM13EN       LL_APB1_GRP1_EnableClock\n
+  *         APB1ENR     TIM14EN       LL_APB1_GRP1_EnableClock\n
+  *         APB1ENR     LPTIM1EN      LL_APB1_GRP1_EnableClock\n
+  *         APB1ENR     WWDGEN        LL_APB1_GRP1_EnableClock\n
+  *         APB1ENR     SPI2EN        LL_APB1_GRP1_EnableClock\n
+  *         APB1ENR     SPI3EN        LL_APB1_GRP1_EnableClock\n
+  *         APB1ENR     SPDIFRXEN     LL_APB1_GRP1_EnableClock\n
+  *         APB1ENR     USART2EN      LL_APB1_GRP1_EnableClock\n
+  *         APB1ENR     USART3EN      LL_APB1_GRP1_EnableClock\n
+  *         APB1ENR     UART4EN       LL_APB1_GRP1_EnableClock\n
+  *         APB1ENR     UART5EN       LL_APB1_GRP1_EnableClock\n
+  *         APB1ENR     I2C1EN        LL_APB1_GRP1_EnableClock\n
+  *         APB1ENR     I2C2EN        LL_APB1_GRP1_EnableClock\n
+  *         APB1ENR     I2C3EN        LL_APB1_GRP1_EnableClock\n
+  *         APB1ENR     FMPI2C1EN     LL_APB1_GRP1_EnableClock\n
+  *         APB1ENR     CAN1EN        LL_APB1_GRP1_EnableClock\n
+  *         APB1ENR     CAN2EN        LL_APB1_GRP1_EnableClock\n
+  *         APB1ENR     CAN3EN        LL_APB1_GRP1_EnableClock\n
+  *         APB1ENR     CECEN         LL_APB1_GRP1_EnableClock\n
+  *         APB1ENR     PWREN         LL_APB1_GRP1_EnableClock\n
+  *         APB1ENR     DACEN         LL_APB1_GRP1_EnableClock\n
+  *         APB1ENR     UART7EN       LL_APB1_GRP1_EnableClock\n
+  *         APB1ENR     UART8EN       LL_APB1_GRP1_EnableClock\n
+  *         APB1ENR     RTCAPBEN      LL_APB1_GRP1_EnableClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_FMPI2C1 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_CAN1 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_CEC  (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_PWR
+  *         @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART7 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART8 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC->APB1ENR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC->APB1ENR, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Check if APB1 peripheral clock is enabled or not
+  * @rmtoll APB1ENR     TIM2EN        LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1ENR     TIM3EN        LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1ENR     TIM4EN        LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1ENR     TIM5EN        LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1ENR     TIM6EN        LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1ENR     TIM7EN        LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1ENR     TIM12EN       LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1ENR     TIM13EN       LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1ENR     TIM14EN       LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1ENR     LPTIM1EN      LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1ENR     WWDGEN        LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1ENR     SPI2EN        LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1ENR     SPI3EN        LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1ENR     SPDIFRXEN     LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1ENR     USART2EN      LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1ENR     USART3EN      LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1ENR     UART4EN       LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1ENR     UART5EN       LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1ENR     I2C1EN        LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1ENR     I2C2EN        LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1ENR     I2C3EN        LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1ENR     FMPI2C1EN     LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1ENR     CAN1EN        LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1ENR     CAN2EN        LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1ENR     CAN3EN        LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1ENR     CECEN         LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1ENR     PWREN         LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1ENR     DACEN         LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1ENR     UART7EN       LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1ENR     UART8EN       LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1ENR     RTCAPBEN      LL_APB1_GRP1_IsEnabledClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_FMPI2C1 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_CAN1 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_PWR
+  *         @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART7 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART8 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval State of Periphs (1 or 0).
+*/
+__STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs)
+{
+  return (READ_BIT(RCC->APB1ENR, Periphs) == Periphs);
+}
+
+/**
+  * @brief  Disable APB1 peripherals clock.
+  * @rmtoll APB1ENR     TIM2EN        LL_APB1_GRP1_DisableClock\n
+  *         APB1ENR     TIM3EN        LL_APB1_GRP1_DisableClock\n
+  *         APB1ENR     TIM4EN        LL_APB1_GRP1_DisableClock\n
+  *         APB1ENR     TIM5EN        LL_APB1_GRP1_DisableClock\n
+  *         APB1ENR     TIM6EN        LL_APB1_GRP1_DisableClock\n
+  *         APB1ENR     TIM7EN        LL_APB1_GRP1_DisableClock\n
+  *         APB1ENR     TIM12EN       LL_APB1_GRP1_DisableClock\n
+  *         APB1ENR     TIM13EN       LL_APB1_GRP1_DisableClock\n
+  *         APB1ENR     TIM14EN       LL_APB1_GRP1_DisableClock\n
+  *         APB1ENR     LPTIM1EN      LL_APB1_GRP1_DisableClock\n
+  *         APB1ENR     WWDGEN        LL_APB1_GRP1_DisableClock\n
+  *         APB1ENR     SPI2EN        LL_APB1_GRP1_DisableClock\n
+  *         APB1ENR     SPI3EN        LL_APB1_GRP1_DisableClock\n
+  *         APB1ENR     SPDIFRXEN     LL_APB1_GRP1_DisableClock\n
+  *         APB1ENR     USART2EN      LL_APB1_GRP1_DisableClock\n
+  *         APB1ENR     USART3EN      LL_APB1_GRP1_DisableClock\n
+  *         APB1ENR     UART4EN       LL_APB1_GRP1_DisableClock\n
+  *         APB1ENR     UART5EN       LL_APB1_GRP1_DisableClock\n
+  *         APB1ENR     I2C1EN        LL_APB1_GRP1_DisableClock\n
+  *         APB1ENR     I2C2EN        LL_APB1_GRP1_DisableClock\n
+  *         APB1ENR     I2C3EN        LL_APB1_GRP1_DisableClock\n
+  *         APB1ENR     FMPI2C1EN     LL_APB1_GRP1_DisableClock\n
+  *         APB1ENR     CAN1EN        LL_APB1_GRP1_DisableClock\n
+  *         APB1ENR     CAN2EN        LL_APB1_GRP1_DisableClock\n
+  *         APB1ENR     CAN3EN        LL_APB1_GRP1_DisableClock\n
+  *         APB1ENR     CECEN         LL_APB1_GRP1_DisableClock\n
+  *         APB1ENR     PWREN         LL_APB1_GRP1_DisableClock\n
+  *         APB1ENR     DACEN         LL_APB1_GRP1_DisableClock\n
+  *         APB1ENR     UART7EN       LL_APB1_GRP1_DisableClock\n
+  *         APB1ENR     UART8EN       LL_APB1_GRP1_DisableClock\n
+  *         APB1ENR     RTCAPBEN      LL_APB1_GRP1_DisableClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_FMPI2C1 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_CAN1 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_PWR
+  *         @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART7 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART8 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_APB1_GRP1_DisableClock(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC->APB1ENR, Periphs);
+}
+
+/**
+  * @brief  Force APB1 peripherals reset.
+  * @rmtoll APB1RSTR     TIM2RST        LL_APB1_GRP1_ForceReset\n
+  *         APB1RSTR     TIM3RST        LL_APB1_GRP1_ForceReset\n
+  *         APB1RSTR     TIM4RST        LL_APB1_GRP1_ForceReset\n
+  *         APB1RSTR     TIM5RST        LL_APB1_GRP1_ForceReset\n
+  *         APB1RSTR     TIM6RST        LL_APB1_GRP1_ForceReset\n
+  *         APB1RSTR     TIM7RST        LL_APB1_GRP1_ForceReset\n
+  *         APB1RSTR     TIM12RST       LL_APB1_GRP1_ForceReset\n
+  *         APB1RSTR     TIM13RST       LL_APB1_GRP1_ForceReset\n
+  *         APB1RSTR     TIM14RST       LL_APB1_GRP1_ForceReset\n
+  *         APB1RSTR     LPTIM1RST      LL_APB1_GRP1_ForceReset\n
+  *         APB1RSTR     WWDGRST        LL_APB1_GRP1_ForceReset\n
+  *         APB1RSTR     SPI2RST        LL_APB1_GRP1_ForceReset\n
+  *         APB1RSTR     SPI3RST        LL_APB1_GRP1_ForceReset\n
+  *         APB1RSTR     SPDIFRXRST     LL_APB1_GRP1_ForceReset\n
+  *         APB1RSTR     USART2RST      LL_APB1_GRP1_ForceReset\n
+  *         APB1RSTR     USART3RST      LL_APB1_GRP1_ForceReset\n
+  *         APB1RSTR     UART4RST       LL_APB1_GRP1_ForceReset\n
+  *         APB1RSTR     UART5RST       LL_APB1_GRP1_ForceReset\n
+  *         APB1RSTR     I2C1RST        LL_APB1_GRP1_ForceReset\n
+  *         APB1RSTR     I2C2RST        LL_APB1_GRP1_ForceReset\n
+  *         APB1RSTR     I2C3RST        LL_APB1_GRP1_ForceReset\n
+  *         APB1RSTR     FMPI2C1RST     LL_APB1_GRP1_ForceReset\n
+  *         APB1RSTR     CAN1RST        LL_APB1_GRP1_ForceReset\n
+  *         APB1RSTR     CAN2RST        LL_APB1_GRP1_ForceReset\n
+  *         APB1RSTR     CAN3RST        LL_APB1_GRP1_ForceReset\n
+  *         APB1RSTR     CECRST         LL_APB1_GRP1_ForceReset\n
+  *         APB1RSTR     PWRRST         LL_APB1_GRP1_ForceReset\n
+  *         APB1RSTR     DACRST         LL_APB1_GRP1_ForceReset\n
+  *         APB1RSTR     UART7RST       LL_APB1_GRP1_ForceReset\n
+  *         APB1RSTR     UART8RST       LL_APB1_GRP1_ForceReset
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_FMPI2C1 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_CAN1 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_PWR
+  *         @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART7 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART8 (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_APB1_GRP1_ForceReset(uint32_t Periphs)
+{
+  SET_BIT(RCC->APB1RSTR, Periphs);
+}
+
+/**
+  * @brief  Release APB1 peripherals reset.
+  * @rmtoll APB1RSTR     TIM2RST        LL_APB1_GRP1_ReleaseReset\n
+  *         APB1RSTR     TIM3RST        LL_APB1_GRP1_ReleaseReset\n
+  *         APB1RSTR     TIM4RST        LL_APB1_GRP1_ReleaseReset\n
+  *         APB1RSTR     TIM5RST        LL_APB1_GRP1_ReleaseReset\n
+  *         APB1RSTR     TIM6RST        LL_APB1_GRP1_ReleaseReset\n
+  *         APB1RSTR     TIM7RST        LL_APB1_GRP1_ReleaseReset\n
+  *         APB1RSTR     TIM12RST       LL_APB1_GRP1_ReleaseReset\n
+  *         APB1RSTR     TIM13RST       LL_APB1_GRP1_ReleaseReset\n
+  *         APB1RSTR     TIM14RST       LL_APB1_GRP1_ReleaseReset\n
+  *         APB1RSTR     LPTIM1RST      LL_APB1_GRP1_ReleaseReset\n
+  *         APB1RSTR     WWDGRST        LL_APB1_GRP1_ReleaseReset\n
+  *         APB1RSTR     SPI2RST        LL_APB1_GRP1_ReleaseReset\n
+  *         APB1RSTR     SPI3RST        LL_APB1_GRP1_ReleaseReset\n
+  *         APB1RSTR     SPDIFRXRST     LL_APB1_GRP1_ReleaseReset\n
+  *         APB1RSTR     USART2RST      LL_APB1_GRP1_ReleaseReset\n
+  *         APB1RSTR     USART3RST      LL_APB1_GRP1_ReleaseReset\n
+  *         APB1RSTR     UART4RST       LL_APB1_GRP1_ReleaseReset\n
+  *         APB1RSTR     UART5RST       LL_APB1_GRP1_ReleaseReset\n
+  *         APB1RSTR     I2C1RST        LL_APB1_GRP1_ReleaseReset\n
+  *         APB1RSTR     I2C2RST        LL_APB1_GRP1_ReleaseReset\n
+  *         APB1RSTR     I2C3RST        LL_APB1_GRP1_ReleaseReset\n
+  *         APB1RSTR     FMPI2C1RST     LL_APB1_GRP1_ReleaseReset\n
+  *         APB1RSTR     CAN1RST        LL_APB1_GRP1_ReleaseReset\n
+  *         APB1RSTR     CAN2RST        LL_APB1_GRP1_ReleaseReset\n
+  *         APB1RSTR     CAN3RST        LL_APB1_GRP1_ReleaseReset\n
+  *         APB1RSTR     CECRST         LL_APB1_GRP1_ReleaseReset\n
+  *         APB1RSTR     PWRRST         LL_APB1_GRP1_ReleaseReset\n
+  *         APB1RSTR     DACRST         LL_APB1_GRP1_ReleaseReset\n
+  *         APB1RSTR     UART7RST       LL_APB1_GRP1_ReleaseReset\n
+  *         APB1RSTR     UART8RST       LL_APB1_GRP1_ReleaseReset
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_FMPI2C1 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_CAN1 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_PWR
+  *         @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART7 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART8 (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_APB1_GRP1_ReleaseReset(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC->APB1RSTR, Periphs);
+}
+
+/**
+  * @brief  Enable APB1 peripheral clocks in low-power mode
+  * @rmtoll APB1LPENR     TIM2LPEN        LL_APB1_GRP1_EnableClockLowPower\n
+  *         APB1LPENR     TIM3LPEN        LL_APB1_GRP1_EnableClockLowPower\n
+  *         APB1LPENR     TIM4LPEN        LL_APB1_GRP1_EnableClockLowPower\n
+  *         APB1LPENR     TIM5LPEN        LL_APB1_GRP1_EnableClockLowPower\n
+  *         APB1LPENR     TIM6LPEN        LL_APB1_GRP1_EnableClockLowPower\n
+  *         APB1LPENR     TIM7LPEN        LL_APB1_GRP1_EnableClockLowPower\n
+  *         APB1LPENR     TIM12LPEN       LL_APB1_GRP1_EnableClockLowPower\n
+  *         APB1LPENR     TIM13LPEN       LL_APB1_GRP1_EnableClockLowPower\n
+  *         APB1LPENR     TIM14LPEN       LL_APB1_GRP1_EnableClockLowPower\n
+  *         APB1LPENR     LPTIM1LPEN      LL_APB1_GRP1_EnableClockLowPower\n
+  *         APB1LPENR     WWDGLPEN        LL_APB1_GRP1_EnableClockLowPower\n
+  *         APB1LPENR     SPI2LPEN        LL_APB1_GRP1_EnableClockLowPower\n
+  *         APB1LPENR     SPI3LPEN        LL_APB1_GRP1_EnableClockLowPower\n
+  *         APB1LPENR     SPDIFRXLPEN     LL_APB1_GRP1_EnableClockLowPower\n
+  *         APB1LPENR     USART2LPEN      LL_APB1_GRP1_EnableClockLowPower\n
+  *         APB1LPENR     USART3LPEN      LL_APB1_GRP1_EnableClockLowPower\n
+  *         APB1LPENR     UART4LPEN       LL_APB1_GRP1_EnableClockLowPower\n
+  *         APB1LPENR     UART5LPEN       LL_APB1_GRP1_EnableClockLowPower\n
+  *         APB1LPENR     I2C1LPEN        LL_APB1_GRP1_EnableClockLowPower\n
+  *         APB1LPENR     I2C2LPEN        LL_APB1_GRP1_EnableClockLowPower\n
+  *         APB1LPENR     I2C3LPEN        LL_APB1_GRP1_EnableClockLowPower\n
+  *         APB1LPENR     FMPI2C1LPEN     LL_APB1_GRP1_EnableClockLowPower\n
+  *         APB1LPENR     CAN1LPEN        LL_APB1_GRP1_EnableClockLowPower\n
+  *         APB1LPENR     CAN2LPEN        LL_APB1_GRP1_EnableClockLowPower\n
+  *         APB1LPENR     CAN3LPEN        LL_APB1_GRP1_EnableClockLowPower\n
+  *         APB1LPENR     CECLPEN         LL_APB1_GRP1_EnableClockLowPower\n
+  *         APB1LPENR     PWRLPEN         LL_APB1_GRP1_EnableClockLowPower\n
+  *         APB1LPENR     DACLPEN         LL_APB1_GRP1_EnableClockLowPower\n
+  *         APB1LPENR     UART7LPEN       LL_APB1_GRP1_EnableClockLowPower\n
+  *         APB1LPENR     UART8LPEN       LL_APB1_GRP1_EnableClockLowPower\n
+  *         APB1LPENR     RTCAPBLPEN      LL_APB1_GRP1_EnableClockLowPower
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_FMPI2C1 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_CAN1 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_PWR
+  *         @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART7 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART8 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_APB1_GRP1_EnableClockLowPower(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC->APB1LPENR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC->APB1LPENR, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Disable APB1 peripheral clocks in low-power mode
+  * @rmtoll APB1LPENR     TIM2LPEN        LL_APB1_GRP1_DisableClockLowPower\n
+  *         APB1LPENR     TIM3LPEN        LL_APB1_GRP1_DisableClockLowPower\n
+  *         APB1LPENR     TIM4LPEN        LL_APB1_GRP1_DisableClockLowPower\n
+  *         APB1LPENR     TIM5LPEN        LL_APB1_GRP1_DisableClockLowPower\n
+  *         APB1LPENR     TIM6LPEN        LL_APB1_GRP1_DisableClockLowPower\n
+  *         APB1LPENR     TIM7LPEN        LL_APB1_GRP1_DisableClockLowPower\n
+  *         APB1LPENR     TIM12LPEN       LL_APB1_GRP1_DisableClockLowPower\n
+  *         APB1LPENR     TIM13LPEN       LL_APB1_GRP1_DisableClockLowPower\n
+  *         APB1LPENR     TIM14LPEN       LL_APB1_GRP1_DisableClockLowPower\n
+  *         APB1LPENR     LPTIM1LPEN      LL_APB1_GRP1_DisableClockLowPower\n
+  *         APB1LPENR     WWDGLPEN        LL_APB1_GRP1_DisableClockLowPower\n
+  *         APB1LPENR     SPI2LPEN        LL_APB1_GRP1_DisableClockLowPower\n
+  *         APB1LPENR     SPI3LPEN        LL_APB1_GRP1_DisableClockLowPower\n
+  *         APB1LPENR     SPDIFRXLPEN     LL_APB1_GRP1_DisableClockLowPower\n
+  *         APB1LPENR     USART2LPEN      LL_APB1_GRP1_DisableClockLowPower\n
+  *         APB1LPENR     USART3LPEN      LL_APB1_GRP1_DisableClockLowPower\n
+  *         APB1LPENR     UART4LPEN       LL_APB1_GRP1_DisableClockLowPower\n
+  *         APB1LPENR     UART5LPEN       LL_APB1_GRP1_DisableClockLowPower\n
+  *         APB1LPENR     I2C1LPEN        LL_APB1_GRP1_DisableClockLowPower\n
+  *         APB1LPENR     I2C2LPEN        LL_APB1_GRP1_DisableClockLowPower\n
+  *         APB1LPENR     I2C3LPEN        LL_APB1_GRP1_DisableClockLowPower\n
+  *         APB1LPENR     FMPI2C1LPEN     LL_APB1_GRP1_DisableClockLowPower\n
+  *         APB1LPENR     CAN1LPEN        LL_APB1_GRP1_DisableClockLowPower\n
+  *         APB1LPENR     CAN2LPEN        LL_APB1_GRP1_DisableClockLowPower\n
+  *         APB1LPENR     CAN3LPEN        LL_APB1_GRP1_DisableClockLowPower\n
+  *         APB1LPENR     CECLPEN         LL_APB1_GRP1_DisableClockLowPower\n
+  *         APB1LPENR     PWRLPEN         LL_APB1_GRP1_DisableClockLowPower\n
+  *         APB1LPENR     DACLPEN         LL_APB1_GRP1_DisableClockLowPower\n
+  *         APB1LPENR     UART7LPEN       LL_APB1_GRP1_DisableClockLowPower\n
+  *         APB1LPENR     UART8LPEN       LL_APB1_GRP1_DisableClockLowPower\n
+  *         APB1LPENR     RTCAPBLPEN      LL_APB1_GRP1_DisableClockLowPower
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_FMPI2C1 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_CAN1 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_PWR
+  *         @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART7 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART8 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_APB1_GRP1_DisableClockLowPower(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC->APB1LPENR, Periphs);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup BUS_LL_EF_APB2 APB2
+  * @{
+  */
+
+/**
+  * @brief  Enable APB2 peripherals clock.
+  * @rmtoll APB2ENR     TIM1EN        LL_APB2_GRP1_EnableClock\n
+  *         APB2ENR     TIM8EN        LL_APB2_GRP1_EnableClock\n
+  *         APB2ENR     USART1EN      LL_APB2_GRP1_EnableClock\n
+  *         APB2ENR     USART6EN      LL_APB2_GRP1_EnableClock\n
+  *         APB2ENR     UART9EN       LL_APB2_GRP1_EnableClock\n
+  *         APB2ENR     UART10EN      LL_APB2_GRP1_EnableClock\n
+  *         APB2ENR     ADC1EN        LL_APB2_GRP1_EnableClock\n
+  *         APB2ENR     ADC2EN        LL_APB2_GRP1_EnableClock\n
+  *         APB2ENR     ADC3EN        LL_APB2_GRP1_EnableClock\n
+  *         APB2ENR     SDIOEN        LL_APB2_GRP1_EnableClock\n
+  *         APB2ENR     SPI1EN        LL_APB2_GRP1_EnableClock\n
+  *         APB2ENR     SPI4EN        LL_APB2_GRP1_EnableClock\n
+  *         APB2ENR     SYSCFGEN      LL_APB2_GRP1_EnableClock\n
+  *         APB2ENR     EXTITEN       LL_APB2_GRP1_EnableClock\n
+  *         APB2ENR     TIM9EN        LL_APB2_GRP1_EnableClock\n
+  *         APB2ENR     TIM10EN       LL_APB2_GRP1_EnableClock\n
+  *         APB2ENR     TIM11EN       LL_APB2_GRP1_EnableClock\n
+  *         APB2ENR     SPI5EN        LL_APB2_GRP1_EnableClock\n
+  *         APB2ENR     SPI6EN        LL_APB2_GRP1_EnableClock\n
+  *         APB2ENR     SAI1EN        LL_APB2_GRP1_EnableClock\n
+  *         APB2ENR     SAI2EN        LL_APB2_GRP1_EnableClock\n
+  *         APB2ENR     LTDCEN        LL_APB2_GRP1_EnableClock\n
+  *         APB2ENR     DSIEN         LL_APB2_GRP1_EnableClock\n
+  *         APB2ENR     DFSDM1EN      LL_APB2_GRP1_EnableClock\n
+  *         APB2ENR     DFSDM2EN      LL_APB2_GRP1_EnableClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART6 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_UART10 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_ADC1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_ADC2 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_ADC3 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SDIO (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
+  *         @arg @ref LL_APB2_GRP1_PERIPH_EXTI (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM9
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM10 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM11
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI5 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_DSI  (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM2 (*)
+
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_APB2_GRP1_EnableClock(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC->APB2ENR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC->APB2ENR, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Check if APB2 peripheral clock is enabled or not
+  * @rmtoll APB2ENR     TIM1EN        LL_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR     TIM8EN        LL_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR     USART1EN      LL_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR     USART6EN      LL_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR     UART9EN       LL_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR     UART10EN      LL_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR     ADC1EN        LL_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR     ADC2EN        LL_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR     ADC3EN        LL_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR     SDIOEN        LL_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR     SPI1EN        LL_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR     SPI4EN        LL_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR     SYSCFGEN      LL_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR     EXTITEN       LL_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR     TIM9EN        LL_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR     TIM10EN       LL_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR     TIM11EN       LL_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR     SPI5EN        LL_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR     SPI6EN        LL_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR     SAI1EN        LL_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR     SAI2EN        LL_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR     LTDCEN        LL_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR     DSIEN         LL_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR     DFSDM1EN      LL_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR     DFSDM2EN      LL_APB2_GRP1_IsEnabledClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART6 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_UART10 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_ADC1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_ADC2 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_ADC3 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SDIO (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
+  *         @arg @ref LL_APB2_GRP1_PERIPH_EXTI (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM9
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM10 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM11
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI5 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_DSI  (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM2 (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval State of Periphs (1 or 0).
+*/
+__STATIC_INLINE uint32_t LL_APB2_GRP1_IsEnabledClock(uint32_t Periphs)
+{
+  return (READ_BIT(RCC->APB2ENR, Periphs) == Periphs);
+}
+
+/**
+  * @brief  Disable APB2 peripherals clock.
+  * @rmtoll APB2ENR     TIM1EN        LL_APB2_GRP1_DisableClock\n
+  *         APB2ENR     TIM8EN        LL_APB2_GRP1_DisableClock\n
+  *         APB2ENR     USART1EN      LL_APB2_GRP1_DisableClock\n
+  *         APB2ENR     USART6EN      LL_APB2_GRP1_DisableClock\n
+  *         APB2ENR     UART9EN       LL_APB2_GRP1_DisableClock\n
+  *         APB2ENR     UART10EN      LL_APB2_GRP1_DisableClock\n
+  *         APB2ENR     ADC1EN        LL_APB2_GRP1_DisableClock\n
+  *         APB2ENR     ADC2EN        LL_APB2_GRP1_DisableClock\n
+  *         APB2ENR     ADC3EN        LL_APB2_GRP1_DisableClock\n
+  *         APB2ENR     SDIOEN        LL_APB2_GRP1_DisableClock\n
+  *         APB2ENR     SPI1EN        LL_APB2_GRP1_DisableClock\n
+  *         APB2ENR     SPI4EN        LL_APB2_GRP1_DisableClock\n
+  *         APB2ENR     SYSCFGEN      LL_APB2_GRP1_DisableClock\n
+  *         APB2ENR     EXTITEN       LL_APB2_GRP1_DisableClock\n
+  *         APB2ENR     TIM9EN        LL_APB2_GRP1_DisableClock\n
+  *         APB2ENR     TIM10EN       LL_APB2_GRP1_DisableClock\n
+  *         APB2ENR     TIM11EN       LL_APB2_GRP1_DisableClock\n
+  *         APB2ENR     SPI5EN        LL_APB2_GRP1_DisableClock\n
+  *         APB2ENR     SPI6EN        LL_APB2_GRP1_DisableClock\n
+  *         APB2ENR     SAI1EN        LL_APB2_GRP1_DisableClock\n
+  *         APB2ENR     SAI2EN        LL_APB2_GRP1_DisableClock\n
+  *         APB2ENR     LTDCEN        LL_APB2_GRP1_DisableClock\n
+  *         APB2ENR     DSIEN         LL_APB2_GRP1_DisableClock\n
+  *         APB2ENR     DFSDM1EN      LL_APB2_GRP1_DisableClock\n
+  *         APB2ENR     DFSDM2EN      LL_APB2_GRP1_DisableClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART6 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_UART10 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_ADC1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_ADC2 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_ADC3 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SDIO (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
+  *         @arg @ref LL_APB2_GRP1_PERIPH_EXTI (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM9
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM10 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM11
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI5 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_DSI  (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM2 (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_APB2_GRP1_DisableClock(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC->APB2ENR, Periphs);
+}
+
+/**
+  * @brief  Force APB2 peripherals reset.
+  * @rmtoll APB2RSTR     TIM1RST        LL_APB2_GRP1_ForceReset\n
+  *         APB2RSTR     TIM8RST        LL_APB2_GRP1_ForceReset\n
+  *         APB2RSTR     USART1RST      LL_APB2_GRP1_ForceReset\n
+  *         APB2RSTR     USART6RST      LL_APB2_GRP1_ForceReset\n
+  *         APB2RSTR     UART9RST       LL_APB2_GRP1_ForceReset\n
+  *         APB2RSTR     UART10RST      LL_APB2_GRP1_ForceReset\n
+  *         APB2RSTR     ADCRST         LL_APB2_GRP1_ForceReset\n
+  *         APB2RSTR     SDIORST        LL_APB2_GRP1_ForceReset\n
+  *         APB2RSTR     SPI1RST        LL_APB2_GRP1_ForceReset\n
+  *         APB2RSTR     SPI4RST        LL_APB2_GRP1_ForceReset\n
+  *         APB2RSTR     SYSCFGRST      LL_APB2_GRP1_ForceReset\n
+  *         APB2RSTR     TIM9RST        LL_APB2_GRP1_ForceReset\n
+  *         APB2RSTR     TIM10RST       LL_APB2_GRP1_ForceReset\n
+  *         APB2RSTR     TIM11RST       LL_APB2_GRP1_ForceReset\n
+  *         APB2RSTR     SPI5RST        LL_APB2_GRP1_ForceReset\n
+  *         APB2RSTR     SPI6RST        LL_APB2_GRP1_ForceReset\n
+  *         APB2RSTR     SAI1RST        LL_APB2_GRP1_ForceReset\n
+  *         APB2RSTR     SAI2RST        LL_APB2_GRP1_ForceReset\n
+  *         APB2RSTR     LTDCRST        LL_APB2_GRP1_ForceReset\n
+  *         APB2RSTR     DSIRST         LL_APB2_GRP1_ForceReset\n
+  *         APB2RSTR     DFSDM1RST      LL_APB2_GRP1_ForceReset\n
+  *         APB2RSTR     DFSDM2RST      LL_APB2_GRP1_ForceReset
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB2_GRP1_PERIPH_ALL
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART6 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_UART10 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_ADC
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SDIO (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM9
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM10 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM11
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI5 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_DSI  (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM2 (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_APB2_GRP1_ForceReset(uint32_t Periphs)
+{
+  SET_BIT(RCC->APB2RSTR, Periphs);
+}
+
+/**
+  * @brief  Release APB2 peripherals reset.
+  * @rmtoll APB2RSTR     TIM1RST        LL_APB2_GRP1_ReleaseReset\n
+  *         APB2RSTR     TIM8RST        LL_APB2_GRP1_ReleaseReset\n
+  *         APB2RSTR     USART1RST      LL_APB2_GRP1_ReleaseReset\n
+  *         APB2RSTR     USART6RST      LL_APB2_GRP1_ReleaseReset\n
+  *         APB2RSTR     UART9RST       LL_APB2_GRP1_ReleaseReset\n
+  *         APB2RSTR     UART10RST      LL_APB2_GRP1_ReleaseReset\n
+  *         APB2RSTR     ADCRST         LL_APB2_GRP1_ReleaseReset\n
+  *         APB2RSTR     SDIORST        LL_APB2_GRP1_ReleaseReset\n
+  *         APB2RSTR     SPI1RST        LL_APB2_GRP1_ReleaseReset\n
+  *         APB2RSTR     SPI4RST        LL_APB2_GRP1_ReleaseReset\n
+  *         APB2RSTR     SYSCFGRST      LL_APB2_GRP1_ReleaseReset\n
+  *         APB2RSTR     TIM9RST        LL_APB2_GRP1_ReleaseReset\n
+  *         APB2RSTR     TIM10RST       LL_APB2_GRP1_ReleaseReset\n
+  *         APB2RSTR     TIM11RST       LL_APB2_GRP1_ReleaseReset\n
+  *         APB2RSTR     SPI5RST        LL_APB2_GRP1_ReleaseReset\n
+  *         APB2RSTR     SPI6RST        LL_APB2_GRP1_ReleaseReset\n
+  *         APB2RSTR     SAI1RST        LL_APB2_GRP1_ReleaseReset\n
+  *         APB2RSTR     SAI2RST        LL_APB2_GRP1_ReleaseReset\n
+  *         APB2RSTR     LTDCRST        LL_APB2_GRP1_ReleaseReset\n
+  *         APB2RSTR     DSIRST         LL_APB2_GRP1_ReleaseReset\n
+  *         APB2RSTR     DFSDM1RST      LL_APB2_GRP1_ReleaseReset\n
+  *         APB2RSTR     DFSDM2RST      LL_APB2_GRP1_ReleaseReset
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB2_GRP1_PERIPH_ALL
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART6 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_UART10 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_ADC
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SDIO (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
+  *         @arg @ref LL_APB2_GRP1_PERIPH_EXTI (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM9
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM10 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM11
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI5 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_DSI  (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM2 (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_APB2_GRP1_ReleaseReset(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC->APB2RSTR, Periphs);
+}
+
+/**
+  * @brief  Enable APB2 peripheral clocks in low-power mode
+  * @rmtoll APB2LPENR     TIM1LPEN        LL_APB2_GRP1_EnableClockLowPower\n
+  *         APB2LPENR     TIM8LPEN        LL_APB2_GRP1_EnableClockLowPower\n
+  *         APB2LPENR     USART1LPEN      LL_APB2_GRP1_EnableClockLowPower\n
+  *         APB2LPENR     USART6LPEN      LL_APB2_GRP1_EnableClockLowPower\n
+  *         APB2LPENR     UART9LPEN       LL_APB2_GRP1_EnableClockLowPower\n
+  *         APB2LPENR     UART10LPEN      LL_APB2_GRP1_EnableClockLowPower\n
+  *         APB2LPENR     ADC1LPEN        LL_APB2_GRP1_EnableClockLowPower\n
+  *         APB2LPENR     ADC2LPEN        LL_APB2_GRP1_EnableClockLowPower\n
+  *         APB2LPENR     ADC3LPEN        LL_APB2_GRP1_EnableClockLowPower\n
+  *         APB2LPENR     SDIOLPEN        LL_APB2_GRP1_EnableClockLowPower\n
+  *         APB2LPENR     SPI1LPEN        LL_APB2_GRP1_EnableClockLowPower\n
+  *         APB2LPENR     SPI4LPEN        LL_APB2_GRP1_EnableClockLowPower\n
+  *         APB2LPENR     SYSCFGLPEN      LL_APB2_GRP1_EnableClockLowPower\n
+  *         APB2LPENR     EXTITLPEN       LL_APB2_GRP1_EnableClockLowPower\n
+  *         APB2LPENR     TIM9LPEN        LL_APB2_GRP1_EnableClockLowPower\n
+  *         APB2LPENR     TIM10LPEN       LL_APB2_GRP1_EnableClockLowPower\n
+  *         APB2LPENR     TIM11LPEN       LL_APB2_GRP1_EnableClockLowPower\n
+  *         APB2LPENR     SPI5LPEN        LL_APB2_GRP1_EnableClockLowPower\n
+  *         APB2LPENR     SPI6LPEN        LL_APB2_GRP1_EnableClockLowPower\n
+  *         APB2LPENR     SAI1LPEN        LL_APB2_GRP1_EnableClockLowPower\n
+  *         APB2LPENR     SAI2LPEN        LL_APB2_GRP1_EnableClockLowPower\n
+  *         APB2LPENR     LTDCLPEN        LL_APB2_GRP1_EnableClockLowPower\n
+  *         APB2LPENR     DSILPEN         LL_APB2_GRP1_EnableClockLowPower\n
+  *         APB2LPENR     DFSDM1LPEN      LL_APB2_GRP1_EnableClockLowPower\n
+  *         APB2LPENR     DSILPEN         LL_APB2_GRP1_EnableClockLowPower\n
+  *         APB2LPENR     DFSDM2LPEN      LL_APB2_GRP1_EnableClockLowPower
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART6 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_UART10 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_ADC1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_ADC2 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_ADC3 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SDIO (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
+  *         @arg @ref LL_APB2_GRP1_PERIPH_EXTI (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM9
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM10 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM11
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI5 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_DSI  (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM2 (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_APB2_GRP1_EnableClockLowPower(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC->APB2LPENR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC->APB2LPENR, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Disable APB2 peripheral clocks in low-power mode
+  * @rmtoll APB2LPENR     TIM1LPEN        LL_APB2_GRP1_DisableClockLowPower\n
+  *         APB2LPENR     TIM8LPEN        LL_APB2_GRP1_DisableClockLowPower\n
+  *         APB2LPENR     USART1LPEN      LL_APB2_GRP1_DisableClockLowPower\n
+  *         APB2LPENR     USART6LPEN      LL_APB2_GRP1_DisableClockLowPower\n
+  *         APB2LPENR     UART9LPEN       LL_APB2_GRP1_DisableClockLowPower\n
+  *         APB2LPENR     UART10LPEN      LL_APB2_GRP1_DisableClockLowPower\n
+  *         APB2LPENR     ADC1LPEN        LL_APB2_GRP1_DisableClockLowPower\n
+  *         APB2LPENR     ADC2LPEN        LL_APB2_GRP1_DisableClockLowPower\n
+  *         APB2LPENR     ADC3LPEN        LL_APB2_GRP1_DisableClockLowPower\n
+  *         APB2LPENR     SDIOLPEN        LL_APB2_GRP1_DisableClockLowPower\n
+  *         APB2LPENR     SPI1LPEN        LL_APB2_GRP1_DisableClockLowPower\n
+  *         APB2LPENR     SPI4LPEN        LL_APB2_GRP1_DisableClockLowPower\n
+  *         APB2LPENR     SYSCFGLPEN      LL_APB2_GRP1_DisableClockLowPower\n
+  *         APB2LPENR     EXTITLPEN       LL_APB2_GRP1_DisableClockLowPower\n
+  *         APB2LPENR     TIM9LPEN        LL_APB2_GRP1_DisableClockLowPower\n
+  *         APB2LPENR     TIM10LPEN       LL_APB2_GRP1_DisableClockLowPower\n
+  *         APB2LPENR     TIM11LPEN       LL_APB2_GRP1_DisableClockLowPower\n
+  *         APB2LPENR     SPI5LPEN        LL_APB2_GRP1_DisableClockLowPower\n
+  *         APB2LPENR     SPI6LPEN        LL_APB2_GRP1_DisableClockLowPower\n
+  *         APB2LPENR     SAI1LPEN        LL_APB2_GRP1_DisableClockLowPower\n
+  *         APB2LPENR     SAI2LPEN        LL_APB2_GRP1_DisableClockLowPower\n
+  *         APB2LPENR     LTDCLPEN        LL_APB2_GRP1_DisableClockLowPower\n
+  *         APB2LPENR     DSILPEN         LL_APB2_GRP1_DisableClockLowPower\n
+  *         APB2LPENR     DFSDM1LPEN      LL_APB2_GRP1_DisableClockLowPower\n
+  *         APB2LPENR     DSILPEN         LL_APB2_GRP1_DisableClockLowPower\n
+  *         APB2LPENR     DFSDM2LPEN      LL_APB2_GRP1_DisableClockLowPower
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART6 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_UART10 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_ADC1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_ADC2 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_ADC3 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SDIO (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
+  *         @arg @ref LL_APB2_GRP1_PERIPH_EXTI (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM9
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM10 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM11
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI5 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_DSI  (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM2 (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_APB2_GRP1_DisableClockLowPower(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC->APB2LPENR, Periphs);
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* defined(RCC) */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_LL_BUS_H */
+
diff --git a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_cortex.h b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_cortex.h
new file mode 100644
index 0000000..4b11b73
--- /dev/null
+++ b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_cortex.h
@@ -0,0 +1,637 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_ll_cortex.h
+  * @author  MCD Application Team
+  * @brief   Header file of CORTEX LL module.
+  @verbatim
+  ==============================================================================
+                     ##### How to use this driver #####
+  ==============================================================================
+    [..]
+    The LL CORTEX driver contains a set of generic APIs that can be
+    used by user:
+      (+) SYSTICK configuration used by LL_mDelay and LL_Init1msTick
+          functions
+      (+) Low power mode configuration (SCB register of Cortex-MCU)
+      (+) MPU API to configure and enable regions
+          (MPU services provided only on some devices)
+      (+) API to access to MCU info (CPUID register)
+      (+) API to enable fault handler (SHCSR accesses)
+
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file in
+  * the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_LL_CORTEX_H
+#define __STM32F4xx_LL_CORTEX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx.h"
+
+/** @addtogroup STM32F4xx_LL_Driver
+  * @{
+  */
+
+/** @defgroup CORTEX_LL CORTEX
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+
+/* Private constants ---------------------------------------------------------*/
+
+/* Private macros ------------------------------------------------------------*/
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup CORTEX_LL_Exported_Constants CORTEX Exported Constants
+  * @{
+  */
+
+/** @defgroup CORTEX_LL_EC_CLKSOURCE_HCLK SYSTICK Clock Source
+  * @{
+  */
+#define LL_SYSTICK_CLKSOURCE_HCLK_DIV8     0x00000000U                 /*!< AHB clock divided by 8 selected as SysTick clock source.*/
+#define LL_SYSTICK_CLKSOURCE_HCLK          SysTick_CTRL_CLKSOURCE_Msk  /*!< AHB clock selected as SysTick clock source. */
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_LL_EC_FAULT Handler Fault type
+  * @{
+  */
+#define LL_HANDLER_FAULT_USG               SCB_SHCSR_USGFAULTENA_Msk              /*!< Usage fault */
+#define LL_HANDLER_FAULT_BUS               SCB_SHCSR_BUSFAULTENA_Msk              /*!< Bus fault */
+#define LL_HANDLER_FAULT_MEM               SCB_SHCSR_MEMFAULTENA_Msk              /*!< Memory management fault */
+/**
+  * @}
+  */
+
+#if __MPU_PRESENT
+
+/** @defgroup CORTEX_LL_EC_CTRL_HFNMI_PRIVDEF MPU Control
+  * @{
+  */
+#define LL_MPU_CTRL_HFNMI_PRIVDEF_NONE     0x00000000U                                       /*!< Disable NMI and privileged SW access */
+#define LL_MPU_CTRL_HARDFAULT_NMI          MPU_CTRL_HFNMIENA_Msk                             /*!< Enables the operation of MPU during hard fault, NMI, and FAULTMASK handlers */
+#define LL_MPU_CTRL_PRIVILEGED_DEFAULT     MPU_CTRL_PRIVDEFENA_Msk                           /*!< Enable privileged software access to default memory map */
+#define LL_MPU_CTRL_HFNMI_PRIVDEF          (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk) /*!< Enable NMI and privileged SW access */
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_LL_EC_REGION MPU Region Number
+  * @{
+  */
+#define LL_MPU_REGION_NUMBER0              0x00U /*!< REGION Number 0 */
+#define LL_MPU_REGION_NUMBER1              0x01U /*!< REGION Number 1 */
+#define LL_MPU_REGION_NUMBER2              0x02U /*!< REGION Number 2 */
+#define LL_MPU_REGION_NUMBER3              0x03U /*!< REGION Number 3 */
+#define LL_MPU_REGION_NUMBER4              0x04U /*!< REGION Number 4 */
+#define LL_MPU_REGION_NUMBER5              0x05U /*!< REGION Number 5 */
+#define LL_MPU_REGION_NUMBER6              0x06U /*!< REGION Number 6 */
+#define LL_MPU_REGION_NUMBER7              0x07U /*!< REGION Number 7 */
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_LL_EC_REGION_SIZE MPU Region Size
+  * @{
+  */
+#define LL_MPU_REGION_SIZE_32B             (0x04U << MPU_RASR_SIZE_Pos) /*!< 32B Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_64B             (0x05U << MPU_RASR_SIZE_Pos) /*!< 64B Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_128B            (0x06U << MPU_RASR_SIZE_Pos) /*!< 128B Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_256B            (0x07U << MPU_RASR_SIZE_Pos) /*!< 256B Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_512B            (0x08U << MPU_RASR_SIZE_Pos) /*!< 512B Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_1KB             (0x09U << MPU_RASR_SIZE_Pos) /*!< 1KB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_2KB             (0x0AU << MPU_RASR_SIZE_Pos) /*!< 2KB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_4KB             (0x0BU << MPU_RASR_SIZE_Pos) /*!< 4KB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_8KB             (0x0CU << MPU_RASR_SIZE_Pos) /*!< 8KB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_16KB            (0x0DU << MPU_RASR_SIZE_Pos) /*!< 16KB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_32KB            (0x0EU << MPU_RASR_SIZE_Pos) /*!< 32KB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_64KB            (0x0FU << MPU_RASR_SIZE_Pos) /*!< 64KB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_128KB           (0x10U << MPU_RASR_SIZE_Pos) /*!< 128KB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_256KB           (0x11U << MPU_RASR_SIZE_Pos) /*!< 256KB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_512KB           (0x12U << MPU_RASR_SIZE_Pos) /*!< 512KB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_1MB             (0x13U << MPU_RASR_SIZE_Pos) /*!< 1MB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_2MB             (0x14U << MPU_RASR_SIZE_Pos) /*!< 2MB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_4MB             (0x15U << MPU_RASR_SIZE_Pos) /*!< 4MB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_8MB             (0x16U << MPU_RASR_SIZE_Pos) /*!< 8MB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_16MB            (0x17U << MPU_RASR_SIZE_Pos) /*!< 16MB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_32MB            (0x18U << MPU_RASR_SIZE_Pos) /*!< 32MB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_64MB            (0x19U << MPU_RASR_SIZE_Pos) /*!< 64MB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_128MB           (0x1AU << MPU_RASR_SIZE_Pos) /*!< 128MB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_256MB           (0x1BU << MPU_RASR_SIZE_Pos) /*!< 256MB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_512MB           (0x1CU << MPU_RASR_SIZE_Pos) /*!< 512MB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_1GB             (0x1DU << MPU_RASR_SIZE_Pos) /*!< 1GB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_2GB             (0x1EU << MPU_RASR_SIZE_Pos) /*!< 2GB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_4GB             (0x1FU << MPU_RASR_SIZE_Pos) /*!< 4GB Size of the MPU protection region */
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_LL_EC_REGION_PRIVILEDGES MPU Region Privileges
+  * @{
+  */
+#define LL_MPU_REGION_NO_ACCESS            (0x00U << MPU_RASR_AP_Pos) /*!< No access*/
+#define LL_MPU_REGION_PRIV_RW              (0x01U << MPU_RASR_AP_Pos) /*!< RW privileged (privileged access only)*/
+#define LL_MPU_REGION_PRIV_RW_URO          (0x02U << MPU_RASR_AP_Pos) /*!< RW privileged - RO user (Write in a user program generates a fault) */
+#define LL_MPU_REGION_FULL_ACCESS          (0x03U << MPU_RASR_AP_Pos) /*!< RW privileged & user (Full access) */
+#define LL_MPU_REGION_PRIV_RO              (0x05U << MPU_RASR_AP_Pos) /*!< RO privileged (privileged read only)*/
+#define LL_MPU_REGION_PRIV_RO_URO          (0x06U << MPU_RASR_AP_Pos) /*!< RO privileged & user (read only) */
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_LL_EC_TEX MPU TEX Level
+  * @{
+  */
+#define LL_MPU_TEX_LEVEL0                  (0x00U << MPU_RASR_TEX_Pos) /*!< b000 for TEX bits */
+#define LL_MPU_TEX_LEVEL1                  (0x01U << MPU_RASR_TEX_Pos) /*!< b001 for TEX bits */
+#define LL_MPU_TEX_LEVEL2                  (0x02U << MPU_RASR_TEX_Pos) /*!< b010 for TEX bits */
+#define LL_MPU_TEX_LEVEL4                  (0x04U << MPU_RASR_TEX_Pos) /*!< b100 for TEX bits */
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_LL_EC_INSTRUCTION_ACCESS MPU Instruction Access
+  * @{
+  */
+#define LL_MPU_INSTRUCTION_ACCESS_ENABLE   0x00U            /*!< Instruction fetches enabled */
+#define LL_MPU_INSTRUCTION_ACCESS_DISABLE  MPU_RASR_XN_Msk  /*!< Instruction fetches disabled*/
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_LL_EC_SHAREABLE_ACCESS MPU Shareable Access
+  * @{
+  */
+#define LL_MPU_ACCESS_SHAREABLE            MPU_RASR_S_Msk   /*!< Shareable memory attribute */
+#define LL_MPU_ACCESS_NOT_SHAREABLE        0x00U            /*!< Not Shareable memory attribute */
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_LL_EC_CACHEABLE_ACCESS MPU Cacheable Access
+  * @{
+  */
+#define LL_MPU_ACCESS_CACHEABLE            MPU_RASR_C_Msk   /*!< Cacheable memory attribute */
+#define LL_MPU_ACCESS_NOT_CACHEABLE        0x00U            /*!< Not Cacheable memory attribute */
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_LL_EC_BUFFERABLE_ACCESS MPU Bufferable Access
+  * @{
+  */
+#define LL_MPU_ACCESS_BUFFERABLE           MPU_RASR_B_Msk   /*!< Bufferable memory attribute */
+#define LL_MPU_ACCESS_NOT_BUFFERABLE       0x00U            /*!< Not Bufferable memory attribute */
+/**
+  * @}
+  */
+#endif /* __MPU_PRESENT */
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup CORTEX_LL_Exported_Functions CORTEX Exported Functions
+  * @{
+  */
+
+/** @defgroup CORTEX_LL_EF_SYSTICK SYSTICK
+  * @{
+  */
+
+/**
+  * @brief  This function checks if the Systick counter flag is active or not.
+  * @note   It can be used in timeout function on application side.
+  * @rmtoll STK_CTRL     COUNTFLAG     LL_SYSTICK_IsActiveCounterFlag
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SYSTICK_IsActiveCounterFlag(void)
+{
+  return ((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == (SysTick_CTRL_COUNTFLAG_Msk));
+}
+
+/**
+  * @brief  Configures the SysTick clock source
+  * @rmtoll STK_CTRL     CLKSOURCE     LL_SYSTICK_SetClkSource
+  * @param  Source This parameter can be one of the following values:
+  *         @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8
+  *         @arg @ref LL_SYSTICK_CLKSOURCE_HCLK
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSTICK_SetClkSource(uint32_t Source)
+{
+  if (Source == LL_SYSTICK_CLKSOURCE_HCLK)
+  {
+    SET_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
+  }
+  else
+  {
+    CLEAR_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
+  }
+}
+
+/**
+  * @brief  Get the SysTick clock source
+  * @rmtoll STK_CTRL     CLKSOURCE     LL_SYSTICK_GetClkSource
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8
+  *         @arg @ref LL_SYSTICK_CLKSOURCE_HCLK
+  */
+__STATIC_INLINE uint32_t LL_SYSTICK_GetClkSource(void)
+{
+  return READ_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
+}
+
+/**
+  * @brief  Enable SysTick exception request
+  * @rmtoll STK_CTRL     TICKINT       LL_SYSTICK_EnableIT
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSTICK_EnableIT(void)
+{
+  SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
+}
+
+/**
+  * @brief  Disable SysTick exception request
+  * @rmtoll STK_CTRL     TICKINT       LL_SYSTICK_DisableIT
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSTICK_DisableIT(void)
+{
+  CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
+}
+
+/**
+  * @brief  Checks if the SYSTICK interrupt is enabled or disabled.
+  * @rmtoll STK_CTRL     TICKINT       LL_SYSTICK_IsEnabledIT
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SYSTICK_IsEnabledIT(void)
+{
+  return (READ_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk) == (SysTick_CTRL_TICKINT_Msk));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_LL_EF_LOW_POWER_MODE LOW POWER MODE
+  * @{
+  */
+
+/**
+  * @brief  Processor uses sleep as its low power mode
+  * @rmtoll SCB_SCR      SLEEPDEEP     LL_LPM_EnableSleep
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPM_EnableSleep(void)
+{
+  /* Clear SLEEPDEEP bit of Cortex System Control Register */
+  CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
+}
+
+/**
+  * @brief  Processor uses deep sleep as its low power mode
+  * @rmtoll SCB_SCR      SLEEPDEEP     LL_LPM_EnableDeepSleep
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPM_EnableDeepSleep(void)
+{
+  /* Set SLEEPDEEP bit of Cortex System Control Register */
+  SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
+}
+
+/**
+  * @brief  Configures sleep-on-exit when returning from Handler mode to Thread mode.
+  * @note   Setting this bit to 1 enables an interrupt-driven application to avoid returning to an
+  *         empty main application.
+  * @rmtoll SCB_SCR      SLEEPONEXIT   LL_LPM_EnableSleepOnExit
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPM_EnableSleepOnExit(void)
+{
+  /* Set SLEEPONEXIT bit of Cortex System Control Register */
+  SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
+}
+
+/**
+  * @brief  Do not sleep when returning to Thread mode.
+  * @rmtoll SCB_SCR      SLEEPONEXIT   LL_LPM_DisableSleepOnExit
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPM_DisableSleepOnExit(void)
+{
+  /* Clear SLEEPONEXIT bit of Cortex System Control Register */
+  CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
+}
+
+/**
+  * @brief  Enabled events and all interrupts, including disabled interrupts, can wakeup the
+  *         processor.
+  * @rmtoll SCB_SCR      SEVEONPEND    LL_LPM_EnableEventOnPend
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPM_EnableEventOnPend(void)
+{
+  /* Set SEVEONPEND bit of Cortex System Control Register */
+  SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
+}
+
+/**
+  * @brief  Only enabled interrupts or events can wakeup the processor, disabled interrupts are
+  *         excluded
+  * @rmtoll SCB_SCR      SEVEONPEND    LL_LPM_DisableEventOnPend
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPM_DisableEventOnPend(void)
+{
+  /* Clear SEVEONPEND bit of Cortex System Control Register */
+  CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_LL_EF_HANDLER HANDLER
+  * @{
+  */
+
+/**
+  * @brief  Enable a fault in System handler control register (SHCSR)
+  * @rmtoll SCB_SHCSR    MEMFAULTENA   LL_HANDLER_EnableFault
+  * @param  Fault This parameter can be a combination of the following values:
+  *         @arg @ref LL_HANDLER_FAULT_USG
+  *         @arg @ref LL_HANDLER_FAULT_BUS
+  *         @arg @ref LL_HANDLER_FAULT_MEM
+  * @retval None
+  */
+__STATIC_INLINE void LL_HANDLER_EnableFault(uint32_t Fault)
+{
+  /* Enable the system handler fault */
+  SET_BIT(SCB->SHCSR, Fault);
+}
+
+/**
+  * @brief  Disable a fault in System handler control register (SHCSR)
+  * @rmtoll SCB_SHCSR    MEMFAULTENA   LL_HANDLER_DisableFault
+  * @param  Fault This parameter can be a combination of the following values:
+  *         @arg @ref LL_HANDLER_FAULT_USG
+  *         @arg @ref LL_HANDLER_FAULT_BUS
+  *         @arg @ref LL_HANDLER_FAULT_MEM
+  * @retval None
+  */
+__STATIC_INLINE void LL_HANDLER_DisableFault(uint32_t Fault)
+{
+  /* Disable the system handler fault */
+  CLEAR_BIT(SCB->SHCSR, Fault);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_LL_EF_MCU_INFO MCU INFO
+  * @{
+  */
+
+/**
+  * @brief  Get Implementer code
+  * @rmtoll SCB_CPUID    IMPLEMENTER   LL_CPUID_GetImplementer
+  * @retval Value should be equal to 0x41 for ARM
+  */
+__STATIC_INLINE uint32_t LL_CPUID_GetImplementer(void)
+{
+  return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_IMPLEMENTER_Msk) >> SCB_CPUID_IMPLEMENTER_Pos);
+}
+
+/**
+  * @brief  Get Variant number (The r value in the rnpn product revision identifier)
+  * @rmtoll SCB_CPUID    VARIANT       LL_CPUID_GetVariant
+  * @retval Value between 0 and 255 (0x0: revision 0)
+  */
+__STATIC_INLINE uint32_t LL_CPUID_GetVariant(void)
+{
+  return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_VARIANT_Msk) >> SCB_CPUID_VARIANT_Pos);
+}
+
+/**
+  * @brief  Get Constant number
+  * @rmtoll SCB_CPUID    ARCHITECTURE  LL_CPUID_GetConstant
+  * @retval Value should be equal to 0xF for Cortex-M4 devices
+  */
+__STATIC_INLINE uint32_t LL_CPUID_GetConstant(void)
+{
+  return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_ARCHITECTURE_Msk) >> SCB_CPUID_ARCHITECTURE_Pos);
+}
+
+/**
+  * @brief  Get Part number
+  * @rmtoll SCB_CPUID    PARTNO        LL_CPUID_GetParNo
+  * @retval Value should be equal to 0xC24 for Cortex-M4
+  */
+__STATIC_INLINE uint32_t LL_CPUID_GetParNo(void)
+{
+  return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_PARTNO_Msk) >> SCB_CPUID_PARTNO_Pos);
+}
+
+/**
+  * @brief  Get Revision number (The p value in the rnpn product revision identifier, indicates patch release)
+  * @rmtoll SCB_CPUID    REVISION      LL_CPUID_GetRevision
+  * @retval Value between 0 and 255 (0x1: patch 1)
+  */
+__STATIC_INLINE uint32_t LL_CPUID_GetRevision(void)
+{
+  return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_REVISION_Msk) >> SCB_CPUID_REVISION_Pos);
+}
+
+/**
+  * @}
+  */
+
+#if __MPU_PRESENT
+/** @defgroup CORTEX_LL_EF_MPU MPU
+  * @{
+  */
+
+/**
+  * @brief  Enable MPU with input options
+  * @rmtoll MPU_CTRL     ENABLE        LL_MPU_Enable
+  * @param  Options This parameter can be one of the following values:
+  *         @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF_NONE
+  *         @arg @ref LL_MPU_CTRL_HARDFAULT_NMI
+  *         @arg @ref LL_MPU_CTRL_PRIVILEGED_DEFAULT
+  *         @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF
+  * @retval None
+  */
+__STATIC_INLINE void LL_MPU_Enable(uint32_t Options)
+{
+  /* Enable the MPU*/
+  WRITE_REG(MPU->CTRL, (MPU_CTRL_ENABLE_Msk | Options));
+  /* Ensure MPU settings take effects */
+  __DSB();
+  /* Sequence instruction fetches using update settings */
+  __ISB();
+}
+
+/**
+  * @brief  Disable MPU
+  * @rmtoll MPU_CTRL     ENABLE        LL_MPU_Disable
+  * @retval None
+  */
+__STATIC_INLINE void LL_MPU_Disable(void)
+{
+  /* Make sure outstanding transfers are done */
+  __DMB();
+  /* Disable MPU*/
+  WRITE_REG(MPU->CTRL, 0U);
+}
+
+/**
+  * @brief  Check if MPU is enabled or not
+  * @rmtoll MPU_CTRL     ENABLE        LL_MPU_IsEnabled
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_MPU_IsEnabled(void)
+{
+  return (READ_BIT(MPU->CTRL, MPU_CTRL_ENABLE_Msk) == (MPU_CTRL_ENABLE_Msk));
+}
+
+/**
+  * @brief  Enable a MPU region
+  * @rmtoll MPU_RASR     ENABLE        LL_MPU_EnableRegion
+  * @param  Region This parameter can be one of the following values:
+  *         @arg @ref LL_MPU_REGION_NUMBER0
+  *         @arg @ref LL_MPU_REGION_NUMBER1
+  *         @arg @ref LL_MPU_REGION_NUMBER2
+  *         @arg @ref LL_MPU_REGION_NUMBER3
+  *         @arg @ref LL_MPU_REGION_NUMBER4
+  *         @arg @ref LL_MPU_REGION_NUMBER5
+  *         @arg @ref LL_MPU_REGION_NUMBER6
+  *         @arg @ref LL_MPU_REGION_NUMBER7
+  * @retval None
+  */
+__STATIC_INLINE void LL_MPU_EnableRegion(uint32_t Region)
+{
+  /* Set Region number */
+  WRITE_REG(MPU->RNR, Region);
+  /* Enable the MPU region */
+  SET_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
+}
+
+/**
+  * @brief  Configure and enable a region
+  * @rmtoll MPU_RNR      REGION        LL_MPU_ConfigRegion\n
+  *         MPU_RBAR     REGION        LL_MPU_ConfigRegion\n
+  *         MPU_RBAR     ADDR          LL_MPU_ConfigRegion\n
+  *         MPU_RASR     XN            LL_MPU_ConfigRegion\n
+  *         MPU_RASR     AP            LL_MPU_ConfigRegion\n
+  *         MPU_RASR     S             LL_MPU_ConfigRegion\n
+  *         MPU_RASR     C             LL_MPU_ConfigRegion\n
+  *         MPU_RASR     B             LL_MPU_ConfigRegion\n
+  *         MPU_RASR     SIZE          LL_MPU_ConfigRegion
+  * @param  Region This parameter can be one of the following values:
+  *         @arg @ref LL_MPU_REGION_NUMBER0
+  *         @arg @ref LL_MPU_REGION_NUMBER1
+  *         @arg @ref LL_MPU_REGION_NUMBER2
+  *         @arg @ref LL_MPU_REGION_NUMBER3
+  *         @arg @ref LL_MPU_REGION_NUMBER4
+  *         @arg @ref LL_MPU_REGION_NUMBER5
+  *         @arg @ref LL_MPU_REGION_NUMBER6
+  *         @arg @ref LL_MPU_REGION_NUMBER7
+  * @param  Address Value of region base address
+  * @param  SubRegionDisable Sub-region disable value between Min_Data = 0x00 and Max_Data = 0xFF
+  * @param  Attributes This parameter can be a combination of the following values:
+  *         @arg @ref LL_MPU_REGION_SIZE_32B or @ref LL_MPU_REGION_SIZE_64B or @ref LL_MPU_REGION_SIZE_128B or @ref LL_MPU_REGION_SIZE_256B or @ref LL_MPU_REGION_SIZE_512B
+  *           or @ref LL_MPU_REGION_SIZE_1KB or @ref LL_MPU_REGION_SIZE_2KB or @ref LL_MPU_REGION_SIZE_4KB or @ref LL_MPU_REGION_SIZE_8KB or @ref LL_MPU_REGION_SIZE_16KB
+  *           or @ref LL_MPU_REGION_SIZE_32KB or @ref LL_MPU_REGION_SIZE_64KB or @ref LL_MPU_REGION_SIZE_128KB or @ref LL_MPU_REGION_SIZE_256KB or @ref LL_MPU_REGION_SIZE_512KB
+  *           or @ref LL_MPU_REGION_SIZE_1MB or @ref LL_MPU_REGION_SIZE_2MB or @ref LL_MPU_REGION_SIZE_4MB or @ref LL_MPU_REGION_SIZE_8MB or @ref LL_MPU_REGION_SIZE_16MB
+  *           or @ref LL_MPU_REGION_SIZE_32MB or @ref LL_MPU_REGION_SIZE_64MB or @ref LL_MPU_REGION_SIZE_128MB or @ref LL_MPU_REGION_SIZE_256MB or @ref LL_MPU_REGION_SIZE_512MB
+  *           or @ref LL_MPU_REGION_SIZE_1GB or @ref LL_MPU_REGION_SIZE_2GB or @ref LL_MPU_REGION_SIZE_4GB
+  *         @arg @ref LL_MPU_REGION_NO_ACCESS or @ref LL_MPU_REGION_PRIV_RW or @ref LL_MPU_REGION_PRIV_RW_URO or @ref LL_MPU_REGION_FULL_ACCESS
+  *           or @ref LL_MPU_REGION_PRIV_RO or @ref LL_MPU_REGION_PRIV_RO_URO
+  *         @arg @ref LL_MPU_TEX_LEVEL0 or @ref LL_MPU_TEX_LEVEL1 or @ref LL_MPU_TEX_LEVEL2 or @ref LL_MPU_TEX_LEVEL4
+  *         @arg @ref LL_MPU_INSTRUCTION_ACCESS_ENABLE or  @ref LL_MPU_INSTRUCTION_ACCESS_DISABLE
+  *         @arg @ref LL_MPU_ACCESS_SHAREABLE or @ref LL_MPU_ACCESS_NOT_SHAREABLE
+  *         @arg @ref LL_MPU_ACCESS_CACHEABLE or @ref LL_MPU_ACCESS_NOT_CACHEABLE
+  *         @arg @ref LL_MPU_ACCESS_BUFFERABLE or @ref LL_MPU_ACCESS_NOT_BUFFERABLE
+  * @retval None
+  */
+__STATIC_INLINE void LL_MPU_ConfigRegion(uint32_t Region, uint32_t SubRegionDisable, uint32_t Address, uint32_t Attributes)
+{
+  /* Set Region number */
+  WRITE_REG(MPU->RNR, Region);
+  /* Set base address */
+  WRITE_REG(MPU->RBAR, (Address & 0xFFFFFFE0U));
+  /* Configure MPU */
+  WRITE_REG(MPU->RASR, (MPU_RASR_ENABLE_Msk | Attributes | SubRegionDisable << MPU_RASR_SRD_Pos));
+}
+
+/**
+  * @brief  Disable a region
+  * @rmtoll MPU_RNR      REGION        LL_MPU_DisableRegion\n
+  *         MPU_RASR     ENABLE        LL_MPU_DisableRegion
+  * @param  Region This parameter can be one of the following values:
+  *         @arg @ref LL_MPU_REGION_NUMBER0
+  *         @arg @ref LL_MPU_REGION_NUMBER1
+  *         @arg @ref LL_MPU_REGION_NUMBER2
+  *         @arg @ref LL_MPU_REGION_NUMBER3
+  *         @arg @ref LL_MPU_REGION_NUMBER4
+  *         @arg @ref LL_MPU_REGION_NUMBER5
+  *         @arg @ref LL_MPU_REGION_NUMBER6
+  *         @arg @ref LL_MPU_REGION_NUMBER7
+  * @retval None
+  */
+__STATIC_INLINE void LL_MPU_DisableRegion(uint32_t Region)
+{
+  /* Set Region number */
+  WRITE_REG(MPU->RNR, Region);
+  /* Disable the MPU region */
+  CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
+}
+
+/**
+  * @}
+  */
+
+#endif /* __MPU_PRESENT */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_LL_CORTEX_H */
+
diff --git a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_crc.h b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_crc.h
new file mode 100644
index 0000000..e3f81ab
--- /dev/null
+++ b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_crc.h
@@ -0,0 +1,201 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_ll_crc.h
+  * @author  MCD Application Team
+  * @brief   Header file of CRC LL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2016 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32F4xx_LL_CRC_H
+#define STM32F4xx_LL_CRC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx.h"
+
+/** @addtogroup STM32F4xx_LL_Driver
+  * @{
+  */
+
+#if defined(CRC)
+
+/** @defgroup CRC_LL CRC
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup CRC_LL_Exported_Constants CRC Exported Constants
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup CRC_LL_Exported_Macros CRC Exported Macros
+  * @{
+  */
+
+/** @defgroup CRC_LL_EM_WRITE_READ Common Write and read registers Macros
+  * @{
+  */
+
+/**
+  * @brief  Write a value in CRC register
+  * @param  __INSTANCE__ CRC Instance
+  * @param  __REG__ Register to be written
+  * @param  __VALUE__ Value to be written in the register
+  * @retval None
+  */
+#define LL_CRC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, __VALUE__)
+
+/**
+  * @brief  Read a value in CRC register
+  * @param  __INSTANCE__ CRC Instance
+  * @param  __REG__ Register to be read
+  * @retval Register value
+  */
+#define LL_CRC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup CRC_LL_Exported_Functions CRC Exported Functions
+  * @{
+  */
+
+/** @defgroup CRC_LL_EF_Configuration CRC Configuration functions
+  * @{
+  */
+
+/**
+  * @brief  Reset the CRC calculation unit.
+  * @note   If Programmable Initial CRC value feature
+  *         is available, also set the Data Register to the value stored in the
+  *         CRC_INIT register, otherwise, reset Data Register to its default value.
+  * @rmtoll CR           RESET         LL_CRC_ResetCRCCalculationUnit
+  * @param  CRCx CRC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_CRC_ResetCRCCalculationUnit(CRC_TypeDef *CRCx)
+{
+  SET_BIT(CRCx->CR, CRC_CR_RESET);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup CRC_LL_EF_Data_Management Data_Management
+  * @{
+  */
+
+/**
+  * @brief  Write given 32-bit data to the CRC calculator
+  * @rmtoll DR           DR            LL_CRC_FeedData32
+  * @param  CRCx CRC Instance
+  * @param  InData value to be provided to CRC calculator between between Min_Data=0 and Max_Data=0xFFFFFFFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_CRC_FeedData32(CRC_TypeDef *CRCx, uint32_t InData)
+{
+  WRITE_REG(CRCx->DR, InData);
+}
+
+/**
+  * @brief  Return current CRC calculation result. 32 bits value is returned.
+  * @rmtoll DR           DR            LL_CRC_ReadData32
+  * @param  CRCx CRC Instance
+  * @retval Current CRC calculation result as stored in CRC_DR register (32 bits).
+  */
+__STATIC_INLINE uint32_t LL_CRC_ReadData32(CRC_TypeDef *CRCx)
+{
+  return (uint32_t)(READ_REG(CRCx->DR));
+}
+
+/**
+  * @brief  Return data stored in the Independent Data(IDR) register.
+  * @note   This register can be used as a temporary storage location for one byte.
+  * @rmtoll IDR          IDR           LL_CRC_Read_IDR
+  * @param  CRCx CRC Instance
+  * @retval Value stored in CRC_IDR register (General-purpose 8-bit data register).
+  */
+__STATIC_INLINE uint32_t LL_CRC_Read_IDR(CRC_TypeDef *CRCx)
+{
+  return (uint32_t)(READ_REG(CRCx->IDR));
+}
+
+/**
+  * @brief  Store data in the Independent Data(IDR) register.
+  * @note   This register can be used as a temporary storage location for one byte.
+  * @rmtoll IDR          IDR           LL_CRC_Write_IDR
+  * @param  CRCx CRC Instance
+  * @param  InData value to be stored in CRC_IDR register (8-bit) between Min_Data=0 and Max_Data=0xFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_CRC_Write_IDR(CRC_TypeDef *CRCx, uint32_t InData)
+{
+  *((uint8_t __IO *)(&CRCx->IDR)) = (uint8_t) InData;
+}
+/**
+  * @}
+  */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup CRC_LL_EF_Init Initialization and de-initialization functions
+  * @{
+  */
+
+ErrorStatus LL_CRC_DeInit(CRC_TypeDef *CRCx);
+
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* defined(CRC) */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32F4xx_LL_CRC_H */
diff --git a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_dma.h b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_dma.h
new file mode 100644
index 0000000..c04ac76
--- /dev/null
+++ b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_dma.h
@@ -0,0 +1,2868 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_ll_dma.h
+  * @author  MCD Application Team
+  * @brief   Header file of DMA LL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file in
+  * the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_LL_DMA_H
+#define __STM32F4xx_LL_DMA_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx.h"
+
+/** @addtogroup STM32F4xx_LL_Driver
+  * @{
+  */
+
+#if defined (DMA1) || defined (DMA2)
+
+/** @defgroup DMA_LL DMA
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup DMA_LL_Private_Variables DMA Private Variables
+  * @{
+  */
+/* Array used to get the DMA stream register offset versus stream index LL_DMA_STREAM_x */
+static const uint8_t STREAM_OFFSET_TAB[] =
+{
+  (uint8_t)(DMA1_Stream0_BASE - DMA1_BASE),
+  (uint8_t)(DMA1_Stream1_BASE - DMA1_BASE),
+  (uint8_t)(DMA1_Stream2_BASE - DMA1_BASE),
+  (uint8_t)(DMA1_Stream3_BASE - DMA1_BASE),
+  (uint8_t)(DMA1_Stream4_BASE - DMA1_BASE),
+  (uint8_t)(DMA1_Stream5_BASE - DMA1_BASE),
+  (uint8_t)(DMA1_Stream6_BASE - DMA1_BASE),
+  (uint8_t)(DMA1_Stream7_BASE - DMA1_BASE)
+};
+
+/**
+  * @}
+  */
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup DMA_LL_Private_Constants DMA Private Constants
+  * @{
+  */
+/**
+  * @}
+  */
+
+
+/* Private macros ------------------------------------------------------------*/
+/* Exported types ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup DMA_LL_ES_INIT DMA Exported Init structure
+  * @{
+  */
+typedef struct
+{
+  uint32_t PeriphOrM2MSrcAddress;  /*!< Specifies the peripheral base address for DMA transfer
+                                        or as Source base address in case of memory to memory transfer direction.
+
+                                        This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
+
+  uint32_t MemoryOrM2MDstAddress;  /*!< Specifies the memory base address for DMA transfer
+                                        or as Destination base address in case of memory to memory transfer direction.
+
+                                        This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
+
+  uint32_t Direction;              /*!< Specifies if the data will be transferred from memory to peripheral,
+                                        from memory to memory or from peripheral to memory.
+                                        This parameter can be a value of @ref DMA_LL_EC_DIRECTION
+
+                                        This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataTransferDirection(). */
+
+  uint32_t Mode;                   /*!< Specifies the normal or circular operation mode.
+                                        This parameter can be a value of @ref DMA_LL_EC_MODE
+                                        @note The circular buffer mode cannot be used if the memory to memory
+                                              data transfer direction is configured on the selected Stream
+
+                                        This feature can be modified afterwards using unitary function @ref LL_DMA_SetMode(). */
+
+  uint32_t PeriphOrM2MSrcIncMode;  /*!< Specifies whether the Peripheral address or Source address in case of memory to memory transfer direction
+                                        is incremented or not.
+                                        This parameter can be a value of @ref DMA_LL_EC_PERIPH
+
+                                        This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphIncMode(). */
+
+  uint32_t MemoryOrM2MDstIncMode;  /*!< Specifies whether the Memory address or Destination address in case of memory to memory transfer direction
+                                        is incremented or not.
+                                        This parameter can be a value of @ref DMA_LL_EC_MEMORY
+
+                                        This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemoryIncMode(). */
+
+  uint32_t PeriphOrM2MSrcDataSize; /*!< Specifies the Peripheral data size alignment or Source data size alignment (byte, half word, word)
+                                        in case of memory to memory transfer direction.
+                                        This parameter can be a value of @ref DMA_LL_EC_PDATAALIGN
+
+                                        This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphSize(). */
+
+  uint32_t MemoryOrM2MDstDataSize; /*!< Specifies the Memory data size alignment or Destination data size alignment (byte, half word, word)
+                                        in case of memory to memory transfer direction.
+                                        This parameter can be a value of @ref DMA_LL_EC_MDATAALIGN
+
+                                        This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemorySize(). */
+
+  uint32_t NbData;                 /*!< Specifies the number of data to transfer, in data unit.
+                                        The data unit is equal to the source buffer configuration set in PeripheralSize
+                                        or MemorySize parameters depending in the transfer direction.
+                                        This parameter must be a value between Min_Data = 0 and Max_Data = 0x0000FFFF
+
+                                        This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataLength(). */
+
+  uint32_t Channel;                /*!< Specifies the peripheral channel.
+                                        This parameter can be a value of @ref DMA_LL_EC_CHANNEL
+
+                                        This feature can be modified afterwards using unitary function @ref LL_DMA_SetChannelSelection(). */
+
+  uint32_t Priority;               /*!< Specifies the channel priority level.
+                                        This parameter can be a value of @ref DMA_LL_EC_PRIORITY
+
+                                        This feature can be modified afterwards using unitary function @ref LL_DMA_SetStreamPriorityLevel(). */
+                                        
+  uint32_t FIFOMode;               /*!< Specifies if the FIFO mode or Direct mode will be used for the specified stream.
+                                        This parameter can be a value of @ref DMA_LL_FIFOMODE
+                                        @note The Direct mode (FIFO mode disabled) cannot be used if the 
+                                        memory-to-memory data transfer is configured on the selected stream
+
+                                        This feature can be modified afterwards using unitary functions @ref LL_DMA_EnableFifoMode() or @ref LL_DMA_EnableFifoMode() . */
+
+  uint32_t FIFOThreshold;          /*!< Specifies the FIFO threshold level.
+                                        This parameter can be a value of @ref DMA_LL_EC_FIFOTHRESHOLD
+
+                                        This feature can be modified afterwards using unitary function @ref LL_DMA_SetFIFOThreshold(). */
+
+  uint32_t MemBurst;               /*!< Specifies the Burst transfer configuration for the memory transfers. 
+                                        It specifies the amount of data to be transferred in a single non interruptible
+                                        transaction.
+                                        This parameter can be a value of @ref DMA_LL_EC_MBURST 
+                                        @note The burst mode is possible only if the address Increment mode is enabled. 
+
+                                        This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemoryBurstxfer(). */
+
+  uint32_t PeriphBurst;            /*!< Specifies the Burst transfer configuration for the peripheral transfers. 
+                                        It specifies the amount of data to be transferred in a single non interruptible 
+                                        transaction. 
+                                        This parameter can be a value of @ref DMA_LL_EC_PBURST
+                                        @note The burst mode is possible only if the address Increment mode is enabled. 
+
+                                        This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphBurstxfer(). */
+
+} LL_DMA_InitTypeDef;
+/**
+  * @}
+  */
+#endif /*USE_FULL_LL_DRIVER*/
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup DMA_LL_Exported_Constants DMA Exported Constants
+  * @{
+  */
+
+/** @defgroup DMA_LL_EC_STREAM STREAM
+  * @{
+  */
+#define LL_DMA_STREAM_0                   0x00000000U
+#define LL_DMA_STREAM_1                   0x00000001U
+#define LL_DMA_STREAM_2                   0x00000002U
+#define LL_DMA_STREAM_3                   0x00000003U
+#define LL_DMA_STREAM_4                   0x00000004U
+#define LL_DMA_STREAM_5                   0x00000005U
+#define LL_DMA_STREAM_6                   0x00000006U
+#define LL_DMA_STREAM_7                   0x00000007U
+#define LL_DMA_STREAM_ALL                 0xFFFF0000U
+/**
+  * @}
+  */
+
+/** @defgroup DMA_LL_EC_DIRECTION DIRECTION
+  * @{
+  */
+#define LL_DMA_DIRECTION_PERIPH_TO_MEMORY 0x00000000U               /*!< Peripheral to memory direction */
+#define LL_DMA_DIRECTION_MEMORY_TO_PERIPH DMA_SxCR_DIR_0            /*!< Memory to peripheral direction */
+#define LL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_SxCR_DIR_1            /*!< Memory to memory direction     */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_LL_EC_MODE MODE
+  * @{
+  */
+#define LL_DMA_MODE_NORMAL                0x00000000U               /*!< Normal Mode                  */
+#define LL_DMA_MODE_CIRCULAR              DMA_SxCR_CIRC             /*!< Circular Mode                */
+#define LL_DMA_MODE_PFCTRL                DMA_SxCR_PFCTRL           /*!< Peripheral flow control mode */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_LL_EC_DOUBLEBUFFER_MODE DOUBLEBUFFER MODE
+  * @{
+  */
+#define LL_DMA_DOUBLEBUFFER_MODE_DISABLE  0x00000000U               /*!< Disable double buffering mode */
+#define LL_DMA_DOUBLEBUFFER_MODE_ENABLE   DMA_SxCR_DBM              /*!< Enable double buffering mode  */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_LL_EC_PERIPH PERIPH
+  * @{
+  */
+#define LL_DMA_PERIPH_NOINCREMENT         0x00000000U               /*!< Peripheral increment mode Disable */
+#define LL_DMA_PERIPH_INCREMENT           DMA_SxCR_PINC             /*!< Peripheral increment mode Enable  */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_LL_EC_MEMORY MEMORY
+  * @{
+  */
+#define LL_DMA_MEMORY_NOINCREMENT         0x00000000U               /*!< Memory increment mode Disable */
+#define LL_DMA_MEMORY_INCREMENT           DMA_SxCR_MINC             /*!< Memory increment mode Enable  */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_LL_EC_PDATAALIGN PDATAALIGN
+  * @{
+  */
+#define LL_DMA_PDATAALIGN_BYTE            0x00000000U               /*!< Peripheral data alignment : Byte     */
+#define LL_DMA_PDATAALIGN_HALFWORD        DMA_SxCR_PSIZE_0          /*!< Peripheral data alignment : HalfWord */
+#define LL_DMA_PDATAALIGN_WORD            DMA_SxCR_PSIZE_1          /*!< Peripheral data alignment : Word     */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_LL_EC_MDATAALIGN MDATAALIGN
+  * @{
+  */
+#define LL_DMA_MDATAALIGN_BYTE            0x00000000U               /*!< Memory data alignment : Byte     */
+#define LL_DMA_MDATAALIGN_HALFWORD        DMA_SxCR_MSIZE_0          /*!< Memory data alignment : HalfWord */
+#define LL_DMA_MDATAALIGN_WORD            DMA_SxCR_MSIZE_1          /*!< Memory data alignment : Word     */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_LL_EC_OFFSETSIZE OFFSETSIZE
+  * @{
+  */
+#define LL_DMA_OFFSETSIZE_PSIZE           0x00000000U               /*!< Peripheral increment offset size is linked to the PSIZE */
+#define LL_DMA_OFFSETSIZE_FIXEDTO4        DMA_SxCR_PINCOS           /*!< Peripheral increment offset size is fixed to 4 (32-bit alignment) */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_LL_EC_PRIORITY PRIORITY
+  * @{
+  */
+#define LL_DMA_PRIORITY_LOW               0x00000000U               /*!< Priority level : Low       */
+#define LL_DMA_PRIORITY_MEDIUM            DMA_SxCR_PL_0             /*!< Priority level : Medium    */
+#define LL_DMA_PRIORITY_HIGH              DMA_SxCR_PL_1             /*!< Priority level : High      */
+#define LL_DMA_PRIORITY_VERYHIGH          DMA_SxCR_PL               /*!< Priority level : Very_High */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_LL_EC_CHANNEL CHANNEL
+  * @{
+  */
+#define LL_DMA_CHANNEL_0                  0x00000000U                                                                   /* Select Channel0 of DMA Instance */
+#define LL_DMA_CHANNEL_1                  DMA_SxCR_CHSEL_0                                                              /* Select Channel1 of DMA Instance */
+#define LL_DMA_CHANNEL_2                  DMA_SxCR_CHSEL_1                                                              /* Select Channel2 of DMA Instance */
+#define LL_DMA_CHANNEL_3                  (DMA_SxCR_CHSEL_0 | DMA_SxCR_CHSEL_1)                                         /* Select Channel3 of DMA Instance */
+#define LL_DMA_CHANNEL_4                  DMA_SxCR_CHSEL_2                                                              /* Select Channel4 of DMA Instance */
+#define LL_DMA_CHANNEL_5                  (DMA_SxCR_CHSEL_2 | DMA_SxCR_CHSEL_0)                                         /* Select Channel5 of DMA Instance */
+#define LL_DMA_CHANNEL_6                  (DMA_SxCR_CHSEL_2 | DMA_SxCR_CHSEL_1)                                         /* Select Channel6 of DMA Instance */
+#define LL_DMA_CHANNEL_7                  (DMA_SxCR_CHSEL_2 | DMA_SxCR_CHSEL_1 | DMA_SxCR_CHSEL_0)                      /* Select Channel7 of DMA Instance */
+#if defined (DMA_SxCR_CHSEL_3)
+#define LL_DMA_CHANNEL_8                  DMA_SxCR_CHSEL_3                                                              /* Select Channel8 of DMA Instance */
+#define LL_DMA_CHANNEL_9                  (DMA_SxCR_CHSEL_3 | DMA_SxCR_CHSEL_0)                                         /* Select Channel9 of DMA Instance */
+#define LL_DMA_CHANNEL_10                 (DMA_SxCR_CHSEL_3 | DMA_SxCR_CHSEL_1)                                         /* Select Channel10 of DMA Instance */
+#define LL_DMA_CHANNEL_11                 (DMA_SxCR_CHSEL_3 | DMA_SxCR_CHSEL_1 | DMA_SxCR_CHSEL_0)                      /* Select Channel11 of DMA Instance */
+#define LL_DMA_CHANNEL_12                 (DMA_SxCR_CHSEL_3 | DMA_SxCR_CHSEL_2)                                         /* Select Channel12 of DMA Instance */
+#define LL_DMA_CHANNEL_13                 (DMA_SxCR_CHSEL_3 | DMA_SxCR_CHSEL_2 | DMA_SxCR_CHSEL_0)                      /* Select Channel13 of DMA Instance */
+#define LL_DMA_CHANNEL_14                 (DMA_SxCR_CHSEL_3 | DMA_SxCR_CHSEL_2 | DMA_SxCR_CHSEL_1)                      /* Select Channel14 of DMA Instance */
+#define LL_DMA_CHANNEL_15                 (DMA_SxCR_CHSEL_3 | DMA_SxCR_CHSEL_2 | DMA_SxCR_CHSEL_1 | DMA_SxCR_CHSEL_0)   /* Select Channel15 of DMA Instance */
+#endif /* DMA_SxCR_CHSEL_3 */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_LL_EC_MBURST MBURST
+  * @{
+  */
+#define LL_DMA_MBURST_SINGLE              0x00000000U                             /*!< Memory burst single transfer configuration */
+#define LL_DMA_MBURST_INC4                DMA_SxCR_MBURST_0                       /*!< Memory burst of 4 beats transfer configuration */
+#define LL_DMA_MBURST_INC8                DMA_SxCR_MBURST_1                       /*!< Memory burst of 8 beats transfer configuration */
+#define LL_DMA_MBURST_INC16               (DMA_SxCR_MBURST_0 | DMA_SxCR_MBURST_1) /*!< Memory burst of 16 beats transfer configuration */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_LL_EC_PBURST PBURST
+  * @{
+  */
+#define LL_DMA_PBURST_SINGLE              0x00000000U                             /*!< Peripheral burst single transfer configuration */
+#define LL_DMA_PBURST_INC4                DMA_SxCR_PBURST_0                       /*!< Peripheral burst of 4 beats transfer configuration */
+#define LL_DMA_PBURST_INC8                DMA_SxCR_PBURST_1                       /*!< Peripheral burst of 8 beats transfer configuration */
+#define LL_DMA_PBURST_INC16               (DMA_SxCR_PBURST_0 | DMA_SxCR_PBURST_1) /*!< Peripheral burst of 16 beats transfer configuration */
+/**
+  * @}
+  */
+  
+/** @defgroup DMA_LL_FIFOMODE DMA_LL_FIFOMODE
+  * @{
+  */
+#define LL_DMA_FIFOMODE_DISABLE           0x00000000U                             /*!< FIFO mode disable (direct mode is enabled) */
+#define LL_DMA_FIFOMODE_ENABLE            DMA_SxFCR_DMDIS                         /*!< FIFO mode enable  */
+/**
+  * @}
+  */  
+
+/** @defgroup DMA_LL_EC_FIFOSTATUS_0 FIFOSTATUS 0
+  * @{
+  */
+#define LL_DMA_FIFOSTATUS_0_25            0x00000000U                             /*!< 0 < fifo_level < 1/4    */
+#define LL_DMA_FIFOSTATUS_25_50           DMA_SxFCR_FS_0                          /*!< 1/4 < fifo_level < 1/2  */
+#define LL_DMA_FIFOSTATUS_50_75           DMA_SxFCR_FS_1                          /*!< 1/2 < fifo_level < 3/4  */
+#define LL_DMA_FIFOSTATUS_75_100          (DMA_SxFCR_FS_1 | DMA_SxFCR_FS_0)       /*!< 3/4 < fifo_level < full */
+#define LL_DMA_FIFOSTATUS_EMPTY           DMA_SxFCR_FS_2                          /*!< FIFO is empty           */
+#define LL_DMA_FIFOSTATUS_FULL            (DMA_SxFCR_FS_2 | DMA_SxFCR_FS_0)       /*!< FIFO is full            */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_LL_EC_FIFOTHRESHOLD FIFOTHRESHOLD
+  * @{
+  */
+#define LL_DMA_FIFOTHRESHOLD_1_4          0x00000000U                             /*!< FIFO threshold 1 quart full configuration  */
+#define LL_DMA_FIFOTHRESHOLD_1_2          DMA_SxFCR_FTH_0                         /*!< FIFO threshold half full configuration     */
+#define LL_DMA_FIFOTHRESHOLD_3_4          DMA_SxFCR_FTH_1                         /*!< FIFO threshold 3 quarts full configuration */
+#define LL_DMA_FIFOTHRESHOLD_FULL         DMA_SxFCR_FTH                           /*!< FIFO threshold full configuration          */
+/**
+  * @}
+  */
+    
+/** @defgroup DMA_LL_EC_CURRENTTARGETMEM CURRENTTARGETMEM
+  * @{
+  */
+#define LL_DMA_CURRENTTARGETMEM0          0x00000000U                             /*!< Set CurrentTarget Memory to Memory 0  */
+#define LL_DMA_CURRENTTARGETMEM1          DMA_SxCR_CT                             /*!< Set CurrentTarget Memory to Memory 1  */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup DMA_LL_Exported_Macros DMA Exported Macros
+  * @{
+  */
+
+/** @defgroup DMA_LL_EM_WRITE_READ Common Write and read registers macros
+  * @{
+  */
+/**
+  * @brief  Write a value in DMA register
+  * @param  __INSTANCE__ DMA Instance
+  * @param  __REG__ Register to be written
+  * @param  __VALUE__ Value to be written in the register
+  * @retval None
+  */
+#define LL_DMA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
+
+/**
+  * @brief  Read a value in DMA register
+  * @param  __INSTANCE__ DMA Instance
+  * @param  __REG__ Register to be read
+  * @retval Register value
+  */
+#define LL_DMA_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+/**
+  * @}
+  */
+
+/** @defgroup DMA_LL_EM_CONVERT_DMAxCHANNELy Convert DMAxStreamy
+  * @{
+  */
+/**
+  * @brief  Convert DMAx_Streamy into DMAx
+  * @param  __STREAM_INSTANCE__ DMAx_Streamy
+  * @retval DMAx
+  */
+#define __LL_DMA_GET_INSTANCE(__STREAM_INSTANCE__)   \
+(((uint32_t)(__STREAM_INSTANCE__) > ((uint32_t)DMA1_Stream7)) ?  DMA2 : DMA1)
+
+/**
+  * @brief  Convert DMAx_Streamy into LL_DMA_STREAM_y
+  * @param  __STREAM_INSTANCE__ DMAx_Streamy
+  * @retval LL_DMA_CHANNEL_y
+  */
+#define __LL_DMA_GET_STREAM(__STREAM_INSTANCE__)   \
+(((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream0)) ? LL_DMA_STREAM_0 : \
+ ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream0)) ? LL_DMA_STREAM_0 : \
+ ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream1)) ? LL_DMA_STREAM_1 : \
+ ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream1)) ? LL_DMA_STREAM_1 : \
+ ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream2)) ? LL_DMA_STREAM_2 : \
+ ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream2)) ? LL_DMA_STREAM_2 : \
+ ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream3)) ? LL_DMA_STREAM_3 : \
+ ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream3)) ? LL_DMA_STREAM_3 : \
+ ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream4)) ? LL_DMA_STREAM_4 : \
+ ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream4)) ? LL_DMA_STREAM_4 : \
+ ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream5)) ? LL_DMA_STREAM_5 : \
+ ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream5)) ? LL_DMA_STREAM_5 : \
+ ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream6)) ? LL_DMA_STREAM_6 : \
+ ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream6)) ? LL_DMA_STREAM_6 : \
+ LL_DMA_STREAM_7)
+
+/**
+  * @brief  Convert DMA Instance DMAx and LL_DMA_STREAM_y into DMAx_Streamy
+  * @param  __DMA_INSTANCE__ DMAx
+  * @param  __STREAM__ LL_DMA_STREAM_y
+  * @retval DMAx_Streamy
+  */
+#define __LL_DMA_GET_STREAM_INSTANCE(__DMA_INSTANCE__, __STREAM__)   \
+((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_0))) ? DMA1_Stream0 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_0))) ? DMA2_Stream0 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_1))) ? DMA1_Stream1 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_1))) ? DMA2_Stream1 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_2))) ? DMA1_Stream2 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_2))) ? DMA2_Stream2 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_3))) ? DMA1_Stream3 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_3))) ? DMA2_Stream3 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_4))) ? DMA1_Stream4 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_4))) ? DMA2_Stream4 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_5))) ? DMA1_Stream5 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_5))) ? DMA2_Stream5 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_6))) ? DMA1_Stream6 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_6))) ? DMA2_Stream6 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_7))) ? DMA1_Stream7 : \
+ DMA2_Stream7)
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+
+/* Exported functions --------------------------------------------------------*/
+ /** @defgroup DMA_LL_Exported_Functions DMA Exported Functions
+  * @{
+  */
+
+/** @defgroup DMA_LL_EF_Configuration Configuration
+  * @{
+  */
+/**
+  * @brief Enable DMA stream.
+  * @rmtoll CR          EN            LL_DMA_EnableStream
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_EnableStream(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_EN);
+}
+
+/**
+  * @brief Disable DMA stream.
+  * @rmtoll CR          EN            LL_DMA_DisableStream
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_DisableStream(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_EN);
+}
+
+/**
+  * @brief Check if DMA stream is enabled or disabled.
+  * @rmtoll CR          EN            LL_DMA_IsEnabledStream
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsEnabledStream(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_EN) == (DMA_SxCR_EN));
+}
+
+/**
+  * @brief  Configure all parameters linked to DMA transfer.
+  * @rmtoll CR          DIR           LL_DMA_ConfigTransfer\n
+  *         CR          CIRC          LL_DMA_ConfigTransfer\n
+  *         CR          PINC          LL_DMA_ConfigTransfer\n
+  *         CR          MINC          LL_DMA_ConfigTransfer\n
+  *         CR          PSIZE         LL_DMA_ConfigTransfer\n
+  *         CR          MSIZE         LL_DMA_ConfigTransfer\n
+  *         CR          PL            LL_DMA_ConfigTransfer\n
+  *         CR          PFCTRL        LL_DMA_ConfigTransfer
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @param  Configuration This parameter must be a combination of all the following values:
+  *         @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY or @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH or @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
+  *         @arg @ref LL_DMA_MODE_NORMAL or @ref LL_DMA_MODE_CIRCULAR  or @ref LL_DMA_MODE_PFCTRL
+  *         @arg @ref LL_DMA_PERIPH_INCREMENT or @ref LL_DMA_PERIPH_NOINCREMENT
+  *         @arg @ref LL_DMA_MEMORY_INCREMENT or @ref LL_DMA_MEMORY_NOINCREMENT
+  *         @arg @ref LL_DMA_PDATAALIGN_BYTE or @ref LL_DMA_PDATAALIGN_HALFWORD or @ref LL_DMA_PDATAALIGN_WORD
+  *         @arg @ref LL_DMA_MDATAALIGN_BYTE or @ref LL_DMA_MDATAALIGN_HALFWORD or @ref LL_DMA_MDATAALIGN_WORD
+  *         @arg @ref LL_DMA_PRIORITY_LOW or @ref LL_DMA_PRIORITY_MEDIUM or @ref LL_DMA_PRIORITY_HIGH or @ref LL_DMA_PRIORITY_VERYHIGH
+  *@retval None
+  */
+__STATIC_INLINE void LL_DMA_ConfigTransfer(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Configuration)
+{
+  MODIFY_REG(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR,
+             DMA_SxCR_DIR | DMA_SxCR_CIRC | DMA_SxCR_PINC | DMA_SxCR_MINC | DMA_SxCR_PSIZE | DMA_SxCR_MSIZE | DMA_SxCR_PL | DMA_SxCR_PFCTRL,
+             Configuration);
+}
+
+/**
+  * @brief Set Data transfer direction (read from peripheral or from memory).
+  * @rmtoll CR          DIR           LL_DMA_SetDataTransferDirection
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @param  Direction This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
+  *         @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
+  *         @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_SetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t  Direction)
+{
+  MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_DIR, Direction);
+}
+
+/**
+  * @brief Get Data transfer direction (read from peripheral or from memory).
+  * @rmtoll CR          DIR           LL_DMA_GetDataTransferDirection
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
+  *         @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
+  *         @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
+  */
+__STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_DIR));
+}
+
+/**
+  * @brief Set DMA mode normal, circular or peripheral flow control.
+  * @rmtoll CR          CIRC           LL_DMA_SetMode\n
+  *         CR          PFCTRL         LL_DMA_SetMode
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @param  Mode This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_MODE_NORMAL
+  *         @arg @ref LL_DMA_MODE_CIRCULAR
+  *         @arg @ref LL_DMA_MODE_PFCTRL
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_SetMode(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Mode)
+{
+  MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_CIRC | DMA_SxCR_PFCTRL, Mode);
+}
+
+/**
+  * @brief Get DMA mode normal, circular or peripheral flow control.
+  * @rmtoll CR          CIRC           LL_DMA_GetMode\n
+  *         CR          PFCTRL         LL_DMA_GetMode
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DMA_MODE_NORMAL
+  *         @arg @ref LL_DMA_MODE_CIRCULAR
+  *         @arg @ref LL_DMA_MODE_PFCTRL
+  */
+__STATIC_INLINE uint32_t LL_DMA_GetMode(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_CIRC | DMA_SxCR_PFCTRL));
+}
+
+/**
+  * @brief Set Peripheral increment mode.
+  * @rmtoll CR          PINC           LL_DMA_SetPeriphIncMode
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @param  IncrementMode This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_PERIPH_NOINCREMENT
+  *         @arg @ref LL_DMA_PERIPH_INCREMENT
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_SetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t IncrementMode)
+{
+  MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PINC, IncrementMode);
+}
+
+/**
+  * @brief Get Peripheral increment mode.
+  * @rmtoll CR          PINC           LL_DMA_GetPeriphIncMode
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DMA_PERIPH_NOINCREMENT
+  *         @arg @ref LL_DMA_PERIPH_INCREMENT
+  */
+__STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PINC));
+}
+
+/**
+  * @brief Set Memory increment mode.
+  * @rmtoll CR          MINC           LL_DMA_SetMemoryIncMode
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @param  IncrementMode This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_MEMORY_NOINCREMENT
+  *         @arg @ref LL_DMA_MEMORY_INCREMENT
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_SetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t IncrementMode)
+{
+  MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_MINC, IncrementMode);
+}
+
+/**
+  * @brief Get Memory increment mode.
+  * @rmtoll CR          MINC           LL_DMA_GetMemoryIncMode
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DMA_MEMORY_NOINCREMENT
+  *         @arg @ref LL_DMA_MEMORY_INCREMENT
+  */
+__STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_MINC));
+}
+
+/**
+  * @brief Set Peripheral size.
+  * @rmtoll CR          PSIZE           LL_DMA_SetPeriphSize
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @param  Size This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_PDATAALIGN_BYTE
+  *         @arg @ref LL_DMA_PDATAALIGN_HALFWORD
+  *         @arg @ref LL_DMA_PDATAALIGN_WORD
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_SetPeriphSize(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t  Size)
+{
+  MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PSIZE, Size);
+}
+
+/**
+  * @brief Get Peripheral size.
+  * @rmtoll CR          PSIZE           LL_DMA_GetPeriphSize
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DMA_PDATAALIGN_BYTE
+  *         @arg @ref LL_DMA_PDATAALIGN_HALFWORD
+  *         @arg @ref LL_DMA_PDATAALIGN_WORD
+  */
+__STATIC_INLINE uint32_t LL_DMA_GetPeriphSize(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PSIZE));
+}
+
+/**
+  * @brief Set Memory size.
+  * @rmtoll CR          MSIZE           LL_DMA_SetMemorySize
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @param  Size This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_MDATAALIGN_BYTE
+  *         @arg @ref LL_DMA_MDATAALIGN_HALFWORD
+  *         @arg @ref LL_DMA_MDATAALIGN_WORD
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_SetMemorySize(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t  Size)
+{
+  MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_MSIZE, Size);
+}
+
+/**
+  * @brief Get Memory size.
+  * @rmtoll CR          MSIZE           LL_DMA_GetMemorySize
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DMA_MDATAALIGN_BYTE
+  *         @arg @ref LL_DMA_MDATAALIGN_HALFWORD
+  *         @arg @ref LL_DMA_MDATAALIGN_WORD
+  */
+__STATIC_INLINE uint32_t LL_DMA_GetMemorySize(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_MSIZE));
+}
+
+/**
+  * @brief Set Peripheral increment offset size.
+  * @rmtoll CR          PINCOS           LL_DMA_SetIncOffsetSize
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @param  OffsetSize This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_OFFSETSIZE_PSIZE
+  *         @arg @ref LL_DMA_OFFSETSIZE_FIXEDTO4
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_SetIncOffsetSize(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t OffsetSize)
+{
+  MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PINCOS, OffsetSize);
+}
+
+/**
+  * @brief Get Peripheral increment offset size.
+  * @rmtoll CR          PINCOS           LL_DMA_GetIncOffsetSize
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DMA_OFFSETSIZE_PSIZE
+  *         @arg @ref LL_DMA_OFFSETSIZE_FIXEDTO4
+  */
+__STATIC_INLINE uint32_t LL_DMA_GetIncOffsetSize(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PINCOS));
+}
+
+/**
+  * @brief Set Stream priority level.
+  * @rmtoll CR          PL           LL_DMA_SetStreamPriorityLevel
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @param  Priority This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_PRIORITY_LOW
+  *         @arg @ref LL_DMA_PRIORITY_MEDIUM
+  *         @arg @ref LL_DMA_PRIORITY_HIGH
+  *         @arg @ref LL_DMA_PRIORITY_VERYHIGH
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_SetStreamPriorityLevel(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t  Priority)
+{
+  MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PL, Priority);
+}
+
+/**
+  * @brief Get Stream priority level.
+  * @rmtoll CR          PL           LL_DMA_GetStreamPriorityLevel
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DMA_PRIORITY_LOW
+  *         @arg @ref LL_DMA_PRIORITY_MEDIUM
+  *         @arg @ref LL_DMA_PRIORITY_HIGH
+  *         @arg @ref LL_DMA_PRIORITY_VERYHIGH
+  */
+__STATIC_INLINE uint32_t LL_DMA_GetStreamPriorityLevel(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PL));
+}
+
+/**
+  * @brief Set Number of data to transfer.
+  * @rmtoll NDTR          NDT           LL_DMA_SetDataLength
+  * @note   This action has no effect if
+  *         stream is enabled.
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @param  NbData Between 0 to 0xFFFFFFFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_SetDataLength(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t NbData)
+{
+  MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->NDTR, DMA_SxNDT, NbData);
+}
+
+/**
+  * @brief Get Number of data to transfer.
+  * @rmtoll NDTR          NDT           LL_DMA_GetDataLength
+  * @note   Once the stream is enabled, the return value indicate the
+  *         remaining bytes to be transmitted.
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval Between 0 to 0xFFFFFFFF
+  */
+__STATIC_INLINE uint32_t LL_DMA_GetDataLength(DMA_TypeDef* DMAx, uint32_t Stream)
+{
+  return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->NDTR, DMA_SxNDT));
+}
+
+/**
+  * @brief Select Channel number associated to the Stream.
+  * @rmtoll CR          CHSEL           LL_DMA_SetChannelSelection
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_0
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_SetChannelSelection(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Channel)
+{
+  MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_CHSEL, Channel);
+}
+
+/**
+  * @brief Get the Channel number associated to the Stream.
+  * @rmtoll CR          CHSEL           LL_DMA_GetChannelSelection
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_0
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  */
+__STATIC_INLINE uint32_t LL_DMA_GetChannelSelection(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_CHSEL));
+}
+
+/**
+  * @brief Set Memory burst transfer configuration.
+  * @rmtoll CR          MBURST           LL_DMA_SetMemoryBurstxfer
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @param  Mburst This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_MBURST_SINGLE
+  *         @arg @ref LL_DMA_MBURST_INC4
+  *         @arg @ref LL_DMA_MBURST_INC8
+  *         @arg @ref LL_DMA_MBURST_INC16
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_SetMemoryBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Mburst)
+{
+  MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_MBURST, Mburst);
+}
+
+/**
+  * @brief Get Memory burst transfer configuration.
+  * @rmtoll CR          MBURST           LL_DMA_GetMemoryBurstxfer
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DMA_MBURST_SINGLE
+  *         @arg @ref LL_DMA_MBURST_INC4
+  *         @arg @ref LL_DMA_MBURST_INC8
+  *         @arg @ref LL_DMA_MBURST_INC16
+  */
+__STATIC_INLINE uint32_t LL_DMA_GetMemoryBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_MBURST));
+}
+
+/**
+  * @brief Set  Peripheral burst transfer configuration.
+  * @rmtoll CR          PBURST           LL_DMA_SetPeriphBurstxfer
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @param  Pburst This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_PBURST_SINGLE
+  *         @arg @ref LL_DMA_PBURST_INC4
+  *         @arg @ref LL_DMA_PBURST_INC8
+  *         @arg @ref LL_DMA_PBURST_INC16
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_SetPeriphBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Pburst)
+{
+  MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PBURST, Pburst);
+}
+
+/**
+  * @brief Get Peripheral burst transfer configuration.
+  * @rmtoll CR          PBURST           LL_DMA_GetPeriphBurstxfer
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DMA_PBURST_SINGLE
+  *         @arg @ref LL_DMA_PBURST_INC4
+  *         @arg @ref LL_DMA_PBURST_INC8
+  *         @arg @ref LL_DMA_PBURST_INC16
+  */
+__STATIC_INLINE uint32_t LL_DMA_GetPeriphBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PBURST));
+}
+
+/**
+  * @brief Set Current target (only in double buffer mode) to Memory 1 or Memory 0.
+  * @rmtoll CR          CT           LL_DMA_SetCurrentTargetMem 
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @param CurrentMemory This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CURRENTTARGETMEM0
+  *         @arg @ref LL_DMA_CURRENTTARGETMEM1
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_SetCurrentTargetMem(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t CurrentMemory)
+{
+   MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_CT, CurrentMemory);
+}
+
+/**
+  * @brief Set Current target (only in double buffer mode) to Memory 1 or Memory 0.
+  * @rmtoll CR          CT           LL_DMA_GetCurrentTargetMem 
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DMA_CURRENTTARGETMEM0
+  *         @arg @ref LL_DMA_CURRENTTARGETMEM1
+  */
+__STATIC_INLINE uint32_t LL_DMA_GetCurrentTargetMem(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_CT));
+}
+
+/**
+  * @brief Enable the double buffer mode.
+  * @rmtoll CR          DBM           LL_DMA_EnableDoubleBufferMode
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_EnableDoubleBufferMode(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_DBM);
+}
+
+/**
+  * @brief Disable the double buffer mode.
+  * @rmtoll CR          DBM           LL_DMA_DisableDoubleBufferMode 
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_DisableDoubleBufferMode(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_DBM);
+}
+
+/**
+  * @brief Get FIFO status.
+  * @rmtoll FCR          FS          LL_DMA_GetFIFOStatus
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DMA_FIFOSTATUS_0_25
+  *         @arg @ref LL_DMA_FIFOSTATUS_25_50
+  *         @arg @ref LL_DMA_FIFOSTATUS_50_75
+  *         @arg @ref LL_DMA_FIFOSTATUS_75_100
+  *         @arg @ref LL_DMA_FIFOSTATUS_EMPTY
+  *         @arg @ref LL_DMA_FIFOSTATUS_FULL
+  */
+__STATIC_INLINE uint32_t LL_DMA_GetFIFOStatus(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FS));
+}
+
+/**
+  * @brief Disable Fifo mode.
+  * @rmtoll FCR          DMDIS          LL_DMA_DisableFifoMode
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_DisableFifoMode(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_DMDIS);
+}
+
+/**
+  * @brief Enable Fifo mode.
+  * @rmtoll FCR          DMDIS          LL_DMA_EnableFifoMode 
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_EnableFifoMode(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_DMDIS);
+}
+
+/**
+  * @brief Select FIFO threshold.
+  * @rmtoll FCR         FTH          LL_DMA_SetFIFOThreshold
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @param  Threshold This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_FIFOTHRESHOLD_1_4
+  *         @arg @ref LL_DMA_FIFOTHRESHOLD_1_2
+  *         @arg @ref LL_DMA_FIFOTHRESHOLD_3_4
+  *         @arg @ref LL_DMA_FIFOTHRESHOLD_FULL
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_SetFIFOThreshold(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Threshold)
+{
+  MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FTH, Threshold);
+}
+
+/**
+  * @brief Get FIFO threshold.
+  * @rmtoll FCR         FTH          LL_DMA_GetFIFOThreshold
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DMA_FIFOTHRESHOLD_1_4
+  *         @arg @ref LL_DMA_FIFOTHRESHOLD_1_2
+  *         @arg @ref LL_DMA_FIFOTHRESHOLD_3_4
+  *         @arg @ref LL_DMA_FIFOTHRESHOLD_FULL
+  */
+__STATIC_INLINE uint32_t LL_DMA_GetFIFOThreshold(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FTH));
+}
+
+/**
+  * @brief Configure the FIFO .
+  * @rmtoll FCR         FTH          LL_DMA_ConfigFifo\n
+  *         FCR         DMDIS        LL_DMA_ConfigFifo
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @param  FifoMode This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_FIFOMODE_ENABLE
+  *         @arg @ref LL_DMA_FIFOMODE_DISABLE
+  * @param  FifoThreshold This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_FIFOTHRESHOLD_1_4
+  *         @arg @ref LL_DMA_FIFOTHRESHOLD_1_2
+  *         @arg @ref LL_DMA_FIFOTHRESHOLD_3_4
+  *         @arg @ref LL_DMA_FIFOTHRESHOLD_FULL
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ConfigFifo(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t FifoMode, uint32_t FifoThreshold)
+{
+  MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FTH|DMA_SxFCR_DMDIS, FifoMode|FifoThreshold);
+}
+
+/**
+  * @brief Configure the Source and Destination addresses.
+  * @note   This API must not be called when the DMA stream is enabled.
+  * @rmtoll M0AR        M0A         LL_DMA_ConfigAddresses\n 
+  *         PAR         PA          LL_DMA_ConfigAddresses
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @param  SrcAddress Between 0 to 0xFFFFFFFF
+  * @param  DstAddress Between 0 to 0xFFFFFFFF
+  * @param  Direction This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
+  *         @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
+  *         @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ConfigAddresses(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t SrcAddress, uint32_t DstAddress, uint32_t Direction)
+{
+  /* Direction Memory to Periph */
+  if (Direction == LL_DMA_DIRECTION_MEMORY_TO_PERIPH)
+  {
+    WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR, SrcAddress);
+    WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR, DstAddress);
+  }
+  /* Direction Periph to Memory and Memory to Memory */
+  else
+  {
+    WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR, SrcAddress);
+    WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR, DstAddress);
+  }
+}
+
+/**
+  * @brief  Set the Memory address.
+  * @rmtoll M0AR        M0A         LL_DMA_SetMemoryAddress
+  * @note   Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
+  * @note   This API must not be called when the DMA channel is enabled.
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @param  MemoryAddress Between 0 to 0xFFFFFFFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_SetMemoryAddress(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t MemoryAddress)
+{
+  WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR, MemoryAddress);
+}
+
+/**
+  * @brief  Set the Peripheral address.
+  * @rmtoll PAR        PA         LL_DMA_SetPeriphAddress
+  * @note   Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
+  * @note   This API must not be called when the DMA channel is enabled.
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @param  PeriphAddress Between 0 to 0xFFFFFFFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_SetPeriphAddress(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t PeriphAddress)
+{
+  WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR, PeriphAddress);
+}
+
+/**
+  * @brief  Get the Memory address.
+  * @rmtoll M0AR        M0A         LL_DMA_GetMemoryAddress
+  * @note   Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval Between 0 to 0xFFFFFFFF
+  */
+__STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(DMA_TypeDef* DMAx, uint32_t Stream)
+{
+  return (READ_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR));
+}
+
+/**
+  * @brief  Get the Peripheral address.
+  * @rmtoll PAR        PA         LL_DMA_GetPeriphAddress
+  * @note   Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval Between 0 to 0xFFFFFFFF
+  */
+__STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(DMA_TypeDef* DMAx, uint32_t Stream)
+{
+  return (READ_REG(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR));
+}
+
+/**
+  * @brief  Set the Memory to Memory Source address.
+  * @rmtoll PAR        PA         LL_DMA_SetM2MSrcAddress
+  * @note   Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
+  * @note   This API must not be called when the DMA channel is enabled.
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @param  MemoryAddress Between 0 to 0xFFFFFFFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_SetM2MSrcAddress(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t MemoryAddress)
+{
+  WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR, MemoryAddress);
+}
+
+/**
+  * @brief  Set the Memory to Memory Destination address.
+  * @rmtoll M0AR        M0A         LL_DMA_SetM2MDstAddress
+  * @note   Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
+  * @note   This API must not be called when the DMA channel is enabled.
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @param  MemoryAddress Between 0 to 0xFFFFFFFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_SetM2MDstAddress(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t MemoryAddress)
+  {
+    WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR, MemoryAddress);
+  }
+
+/**
+  * @brief  Get the Memory to Memory Source address.
+  * @rmtoll PAR        PA         LL_DMA_GetM2MSrcAddress
+  * @note   Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval Between 0 to 0xFFFFFFFF
+  */
+__STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(DMA_TypeDef* DMAx, uint32_t Stream)
+  {
+   return (READ_REG(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR));
+  }
+
+/**
+  * @brief  Get the Memory to Memory Destination address.
+  * @rmtoll M0AR        M0A         LL_DMA_GetM2MDstAddress
+  * @note   Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval Between 0 to 0xFFFFFFFF
+  */
+__STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(DMA_TypeDef* DMAx, uint32_t Stream)
+{
+ return (READ_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR));
+}
+
+/**
+  * @brief Set Memory 1 address (used in case of Double buffer mode).
+  * @rmtoll M1AR        M1A         LL_DMA_SetMemory1Address
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @param  Address Between 0 to 0xFFFFFFFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_SetMemory1Address(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Address)
+{
+  MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M1AR, DMA_SxM1AR_M1A, Address);
+}
+
+/**
+  * @brief Get Memory 1 address (used in case of Double buffer mode).
+  * @rmtoll M1AR        M1A         LL_DMA_GetMemory1Address
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval Between 0 to 0xFFFFFFFF
+  */
+__STATIC_INLINE uint32_t LL_DMA_GetMemory1Address(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  return (((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M1AR);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup DMA_LL_EF_FLAG_Management FLAG_Management
+  * @{
+  */
+
+/**
+  * @brief Get Stream 0 half transfer flag.
+  * @rmtoll LISR  HTIF0    LL_DMA_IsActiveFlag_HT0
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT0(DMA_TypeDef *DMAx)
+{
+  return (READ_BIT(DMAx->LISR ,DMA_LISR_HTIF0)==(DMA_LISR_HTIF0));
+}
+
+/**
+  * @brief Get Stream 1 half transfer flag.
+  * @rmtoll LISR  HTIF1    LL_DMA_IsActiveFlag_HT1
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT1(DMA_TypeDef *DMAx)
+{
+  return (READ_BIT(DMAx->LISR ,DMA_LISR_HTIF1)==(DMA_LISR_HTIF1));
+}
+
+/**
+  * @brief Get Stream 2 half transfer flag.
+  * @rmtoll LISR  HTIF2    LL_DMA_IsActiveFlag_HT2
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT2(DMA_TypeDef *DMAx)
+{
+  return (READ_BIT(DMAx->LISR ,DMA_LISR_HTIF2)==(DMA_LISR_HTIF2));
+}
+
+/**
+  * @brief Get Stream 3 half transfer flag.
+  * @rmtoll LISR  HTIF3    LL_DMA_IsActiveFlag_HT3
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT3(DMA_TypeDef *DMAx)
+{
+  return (READ_BIT(DMAx->LISR ,DMA_LISR_HTIF3)==(DMA_LISR_HTIF3));
+}
+
+/**
+  * @brief Get Stream 4 half transfer flag.
+  * @rmtoll HISR  HTIF4    LL_DMA_IsActiveFlag_HT4
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT4(DMA_TypeDef *DMAx)
+{
+  return (READ_BIT(DMAx->HISR ,DMA_HISR_HTIF4)==(DMA_HISR_HTIF4));
+}
+
+/**
+  * @brief Get Stream 5 half transfer flag.
+  * @rmtoll HISR  HTIF0    LL_DMA_IsActiveFlag_HT5
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT5(DMA_TypeDef *DMAx)
+{
+  return (READ_BIT(DMAx->HISR ,DMA_HISR_HTIF5)==(DMA_HISR_HTIF5));
+}
+
+/**
+  * @brief Get Stream 6 half transfer flag.
+  * @rmtoll HISR  HTIF6    LL_DMA_IsActiveFlag_HT6
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT6(DMA_TypeDef *DMAx)
+{
+  return (READ_BIT(DMAx->HISR ,DMA_HISR_HTIF6)==(DMA_HISR_HTIF6));
+}
+
+/**
+  * @brief Get Stream 7 half transfer flag.
+  * @rmtoll HISR  HTIF7    LL_DMA_IsActiveFlag_HT7
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT7(DMA_TypeDef *DMAx)
+{
+  return (READ_BIT(DMAx->HISR ,DMA_HISR_HTIF7)==(DMA_HISR_HTIF7));
+} 
+
+/**
+  * @brief Get Stream 0 transfer complete flag.
+  * @rmtoll LISR  TCIF0    LL_DMA_IsActiveFlag_TC0
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC0(DMA_TypeDef *DMAx)
+{
+  return (READ_BIT(DMAx->LISR ,DMA_LISR_TCIF0)==(DMA_LISR_TCIF0));
+}
+
+/**
+  * @brief Get Stream 1 transfer complete flag.
+  * @rmtoll LISR  TCIF1    LL_DMA_IsActiveFlag_TC1
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC1(DMA_TypeDef *DMAx)
+{
+  return (READ_BIT(DMAx->LISR ,DMA_LISR_TCIF1)==(DMA_LISR_TCIF1));
+}
+
+/**
+  * @brief Get Stream 2 transfer complete flag.
+  * @rmtoll LISR  TCIF2    LL_DMA_IsActiveFlag_TC2
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC2(DMA_TypeDef *DMAx)
+{
+  return (READ_BIT(DMAx->LISR ,DMA_LISR_TCIF2)==(DMA_LISR_TCIF2));
+}
+
+/**
+  * @brief Get Stream 3 transfer complete flag.
+  * @rmtoll LISR  TCIF3    LL_DMA_IsActiveFlag_TC3
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC3(DMA_TypeDef *DMAx)
+{
+  return (READ_BIT(DMAx->LISR ,DMA_LISR_TCIF3)==(DMA_LISR_TCIF3));
+}
+
+/**
+  * @brief Get Stream 4 transfer complete flag.
+  * @rmtoll HISR  TCIF4    LL_DMA_IsActiveFlag_TC4
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC4(DMA_TypeDef *DMAx)
+{
+  return (READ_BIT(DMAx->HISR ,DMA_HISR_TCIF4)==(DMA_HISR_TCIF4));
+}
+
+/**
+  * @brief Get Stream 5 transfer complete flag.
+  * @rmtoll HISR  TCIF0    LL_DMA_IsActiveFlag_TC5
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC5(DMA_TypeDef *DMAx)
+{
+  return (READ_BIT(DMAx->HISR ,DMA_HISR_TCIF5)==(DMA_HISR_TCIF5));
+}
+
+/**
+  * @brief Get Stream 6 transfer complete flag.
+  * @rmtoll HISR  TCIF6    LL_DMA_IsActiveFlag_TC6
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC6(DMA_TypeDef *DMAx)
+{
+  return (READ_BIT(DMAx->HISR ,DMA_HISR_TCIF6)==(DMA_HISR_TCIF6));
+}
+
+/**
+  * @brief Get Stream 7 transfer complete flag.
+  * @rmtoll HISR  TCIF7    LL_DMA_IsActiveFlag_TC7
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC7(DMA_TypeDef *DMAx)
+{
+  return (READ_BIT(DMAx->HISR ,DMA_HISR_TCIF7)==(DMA_HISR_TCIF7));
+} 
+
+/**
+  * @brief Get Stream 0 transfer error flag.
+  * @rmtoll LISR  TEIF0    LL_DMA_IsActiveFlag_TE0
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE0(DMA_TypeDef *DMAx)
+{
+  return (READ_BIT(DMAx->LISR ,DMA_LISR_TEIF0)==(DMA_LISR_TEIF0));
+}
+
+/**
+  * @brief Get Stream 1 transfer error flag.
+  * @rmtoll LISR  TEIF1    LL_DMA_IsActiveFlag_TE1
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE1(DMA_TypeDef *DMAx)
+{
+  return (READ_BIT(DMAx->LISR ,DMA_LISR_TEIF1)==(DMA_LISR_TEIF1));
+}
+
+/**
+  * @brief Get Stream 2 transfer error flag.
+  * @rmtoll LISR  TEIF2    LL_DMA_IsActiveFlag_TE2
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE2(DMA_TypeDef *DMAx)
+{
+  return (READ_BIT(DMAx->LISR ,DMA_LISR_TEIF2)==(DMA_LISR_TEIF2));
+}
+
+/**
+  * @brief Get Stream 3 transfer error flag.
+  * @rmtoll LISR  TEIF3    LL_DMA_IsActiveFlag_TE3
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE3(DMA_TypeDef *DMAx)
+{
+  return (READ_BIT(DMAx->LISR ,DMA_LISR_TEIF3)==(DMA_LISR_TEIF3));
+}
+
+/**
+  * @brief Get Stream 4 transfer error flag.
+  * @rmtoll HISR  TEIF4    LL_DMA_IsActiveFlag_TE4
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE4(DMA_TypeDef *DMAx)
+{
+  return (READ_BIT(DMAx->HISR ,DMA_HISR_TEIF4)==(DMA_HISR_TEIF4));
+}
+
+/**
+  * @brief Get Stream 5 transfer error flag.
+  * @rmtoll HISR  TEIF0    LL_DMA_IsActiveFlag_TE5
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE5(DMA_TypeDef *DMAx)
+{
+  return (READ_BIT(DMAx->HISR ,DMA_HISR_TEIF5)==(DMA_HISR_TEIF5));
+}
+
+/**
+  * @brief Get Stream 6 transfer error flag.
+  * @rmtoll HISR  TEIF6    LL_DMA_IsActiveFlag_TE6
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE6(DMA_TypeDef *DMAx)
+{
+  return (READ_BIT(DMAx->HISR ,DMA_HISR_TEIF6)==(DMA_HISR_TEIF6));
+}
+
+/**
+  * @brief Get Stream 7 transfer error flag.
+  * @rmtoll HISR  TEIF7    LL_DMA_IsActiveFlag_TE7
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE7(DMA_TypeDef *DMAx)
+{
+  return (READ_BIT(DMAx->HISR ,DMA_HISR_TEIF7)==(DMA_HISR_TEIF7));
+} 
+
+/**
+  * @brief Get Stream 0 direct mode error flag.
+  * @rmtoll LISR  DMEIF0    LL_DMA_IsActiveFlag_DME0
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME0(DMA_TypeDef *DMAx)
+{
+  return (READ_BIT(DMAx->LISR ,DMA_LISR_DMEIF0)==(DMA_LISR_DMEIF0));
+}
+
+/**
+  * @brief Get Stream 1 direct mode error flag.
+  * @rmtoll LISR  DMEIF1    LL_DMA_IsActiveFlag_DME1
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME1(DMA_TypeDef *DMAx)
+{
+  return (READ_BIT(DMAx->LISR ,DMA_LISR_DMEIF1)==(DMA_LISR_DMEIF1));
+}
+
+/**
+  * @brief Get Stream 2 direct mode error flag.
+  * @rmtoll LISR  DMEIF2    LL_DMA_IsActiveFlag_DME2
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME2(DMA_TypeDef *DMAx)
+{
+  return (READ_BIT(DMAx->LISR ,DMA_LISR_DMEIF2)==(DMA_LISR_DMEIF2));
+}
+
+/**
+  * @brief Get Stream 3 direct mode error flag.
+  * @rmtoll LISR  DMEIF3    LL_DMA_IsActiveFlag_DME3
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME3(DMA_TypeDef *DMAx)
+{
+  return (READ_BIT(DMAx->LISR ,DMA_LISR_DMEIF3)==(DMA_LISR_DMEIF3));
+}
+
+/**
+  * @brief Get Stream 4 direct mode error flag.
+  * @rmtoll HISR  DMEIF4    LL_DMA_IsActiveFlag_DME4
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME4(DMA_TypeDef *DMAx)
+{
+  return (READ_BIT(DMAx->HISR ,DMA_HISR_DMEIF4)==(DMA_HISR_DMEIF4));
+}
+
+/**
+  * @brief Get Stream 5 direct mode error flag.
+  * @rmtoll HISR  DMEIF0    LL_DMA_IsActiveFlag_DME5
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME5(DMA_TypeDef *DMAx)
+{
+  return (READ_BIT(DMAx->HISR ,DMA_HISR_DMEIF5)==(DMA_HISR_DMEIF5));
+}
+
+/**
+  * @brief Get Stream 6 direct mode error flag.
+  * @rmtoll HISR  DMEIF6    LL_DMA_IsActiveFlag_DME6
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME6(DMA_TypeDef *DMAx)
+{
+  return (READ_BIT(DMAx->HISR ,DMA_HISR_DMEIF6)==(DMA_HISR_DMEIF6));
+}
+
+/**
+  * @brief Get Stream 7 direct mode error flag.
+  * @rmtoll HISR  DMEIF7    LL_DMA_IsActiveFlag_DME7
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME7(DMA_TypeDef *DMAx)
+{
+  return (READ_BIT(DMAx->HISR ,DMA_HISR_DMEIF7)==(DMA_HISR_DMEIF7));
+}
+
+/**
+  * @brief Get Stream 0 FIFO error flag.
+  * @rmtoll LISR  FEIF0    LL_DMA_IsActiveFlag_FE0
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE0(DMA_TypeDef *DMAx)
+{
+  return (READ_BIT(DMAx->LISR ,DMA_LISR_FEIF0)==(DMA_LISR_FEIF0));
+}
+
+/**
+  * @brief Get Stream 1 FIFO error flag.
+  * @rmtoll LISR  FEIF1    LL_DMA_IsActiveFlag_FE1
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE1(DMA_TypeDef *DMAx)
+{
+  return (READ_BIT(DMAx->LISR ,DMA_LISR_FEIF1)==(DMA_LISR_FEIF1));
+}
+
+/**
+  * @brief Get Stream 2 FIFO error flag.
+  * @rmtoll LISR  FEIF2    LL_DMA_IsActiveFlag_FE2
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE2(DMA_TypeDef *DMAx)
+{
+  return (READ_BIT(DMAx->LISR ,DMA_LISR_FEIF2)==(DMA_LISR_FEIF2));
+}
+
+/**
+  * @brief Get Stream 3 FIFO error flag.
+  * @rmtoll LISR  FEIF3    LL_DMA_IsActiveFlag_FE3
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE3(DMA_TypeDef *DMAx)
+{
+  return (READ_BIT(DMAx->LISR ,DMA_LISR_FEIF3)==(DMA_LISR_FEIF3));
+}
+
+/**
+  * @brief Get Stream 4 FIFO error flag.
+  * @rmtoll HISR  FEIF4    LL_DMA_IsActiveFlag_FE4
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE4(DMA_TypeDef *DMAx)
+{
+  return (READ_BIT(DMAx->HISR ,DMA_HISR_FEIF4)==(DMA_HISR_FEIF4));
+}
+
+/**
+  * @brief Get Stream 5 FIFO error flag.
+  * @rmtoll HISR  FEIF0    LL_DMA_IsActiveFlag_FE5
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE5(DMA_TypeDef *DMAx)
+{
+  return (READ_BIT(DMAx->HISR ,DMA_HISR_FEIF5)==(DMA_HISR_FEIF5));
+}
+
+/**
+  * @brief Get Stream 6 FIFO error flag.
+  * @rmtoll HISR  FEIF6    LL_DMA_IsActiveFlag_FE6
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE6(DMA_TypeDef *DMAx)
+{
+  return (READ_BIT(DMAx->HISR ,DMA_HISR_FEIF6)==(DMA_HISR_FEIF6));
+}
+
+/**
+  * @brief Get Stream 7 FIFO error flag.
+  * @rmtoll HISR  FEIF7    LL_DMA_IsActiveFlag_FE7
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE7(DMA_TypeDef *DMAx)
+{
+  return (READ_BIT(DMAx->HISR ,DMA_HISR_FEIF7)==(DMA_HISR_FEIF7));
+}
+
+/**
+  * @brief Clear Stream 0 half transfer flag.
+  * @rmtoll LIFCR  CHTIF0    LL_DMA_ClearFlag_HT0
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_HT0(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CHTIF0);
+}
+
+/**
+  * @brief Clear Stream 1 half transfer flag.
+  * @rmtoll LIFCR  CHTIF1    LL_DMA_ClearFlag_HT1
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_HT1(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CHTIF1);
+}
+
+/**
+  * @brief Clear Stream 2 half transfer flag.
+  * @rmtoll LIFCR  CHTIF2    LL_DMA_ClearFlag_HT2
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_HT2(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CHTIF2);
+}
+
+/**
+  * @brief Clear Stream 3 half transfer flag.
+  * @rmtoll LIFCR  CHTIF3    LL_DMA_ClearFlag_HT3
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_HT3(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CHTIF3);
+}
+
+/**
+  * @brief Clear Stream 4 half transfer flag.
+  * @rmtoll HIFCR  CHTIF4    LL_DMA_ClearFlag_HT4
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_HT4(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CHTIF4);
+}
+
+/**
+  * @brief Clear Stream 5 half transfer flag.
+  * @rmtoll HIFCR  CHTIF5    LL_DMA_ClearFlag_HT5
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_HT5(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CHTIF5);
+}
+
+/**
+  * @brief Clear Stream 6 half transfer flag.
+  * @rmtoll HIFCR  CHTIF6    LL_DMA_ClearFlag_HT6
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_HT6(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CHTIF6);
+}
+
+/**
+  * @brief Clear Stream 7 half transfer flag.
+  * @rmtoll HIFCR  CHTIF7    LL_DMA_ClearFlag_HT7
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_HT7(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CHTIF7);
+}
+
+/**
+  * @brief Clear Stream 0 transfer complete flag.
+  * @rmtoll LIFCR  CTCIF0    LL_DMA_ClearFlag_TC0
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_TC0(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTCIF0);
+}
+
+/**
+  * @brief Clear Stream 1 transfer complete flag.
+  * @rmtoll LIFCR  CTCIF1    LL_DMA_ClearFlag_TC1
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_TC1(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTCIF1);
+}
+
+/**
+  * @brief Clear Stream 2 transfer complete flag.
+  * @rmtoll LIFCR  CTCIF2    LL_DMA_ClearFlag_TC2
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_TC2(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTCIF2);
+}
+
+/**
+  * @brief Clear Stream 3 transfer complete flag.
+  * @rmtoll LIFCR  CTCIF3    LL_DMA_ClearFlag_TC3
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_TC3(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTCIF3);
+}
+
+/**
+  * @brief Clear Stream 4 transfer complete flag.
+  * @rmtoll HIFCR  CTCIF4    LL_DMA_ClearFlag_TC4
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_TC4(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTCIF4);
+}
+
+/**
+  * @brief Clear Stream 5 transfer complete flag.
+  * @rmtoll HIFCR  CTCIF5    LL_DMA_ClearFlag_TC5
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_TC5(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTCIF5);
+}
+
+/**
+  * @brief Clear Stream 6 transfer complete flag.
+  * @rmtoll HIFCR  CTCIF6    LL_DMA_ClearFlag_TC6
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_TC6(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTCIF6);
+}
+
+/**
+  * @brief Clear Stream 7 transfer complete flag.
+  * @rmtoll HIFCR  CTCIF7    LL_DMA_ClearFlag_TC7
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_TC7(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTCIF7);
+}
+
+/**
+  * @brief Clear Stream 0 transfer error flag.
+  * @rmtoll LIFCR  CTEIF0    LL_DMA_ClearFlag_TE0
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_TE0(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTEIF0);
+}
+
+/**
+  * @brief Clear Stream 1 transfer error flag.
+  * @rmtoll LIFCR  CTEIF1    LL_DMA_ClearFlag_TE1
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_TE1(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTEIF1);
+}
+
+/**
+  * @brief Clear Stream 2 transfer error flag.
+  * @rmtoll LIFCR  CTEIF2    LL_DMA_ClearFlag_TE2
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_TE2(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTEIF2);
+}
+
+/**
+  * @brief Clear Stream 3 transfer error flag.
+  * @rmtoll LIFCR  CTEIF3    LL_DMA_ClearFlag_TE3
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_TE3(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTEIF3);
+}
+
+/**
+  * @brief Clear Stream 4 transfer error flag.
+  * @rmtoll HIFCR  CTEIF4    LL_DMA_ClearFlag_TE4
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_TE4(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTEIF4);
+}
+
+/**
+  * @brief Clear Stream 5 transfer error flag.
+  * @rmtoll HIFCR  CTEIF5    LL_DMA_ClearFlag_TE5
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_TE5(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTEIF5);
+}
+
+/**
+  * @brief Clear Stream 6 transfer error flag.
+  * @rmtoll HIFCR  CTEIF6    LL_DMA_ClearFlag_TE6
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_TE6(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTEIF6);
+}
+
+/**
+  * @brief Clear Stream 7 transfer error flag.
+  * @rmtoll HIFCR  CTEIF7    LL_DMA_ClearFlag_TE7
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_TE7(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTEIF7);
+}
+
+/**
+  * @brief Clear Stream 0 direct mode error flag.
+  * @rmtoll LIFCR  CDMEIF0    LL_DMA_ClearFlag_DME0
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_DME0(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CDMEIF0);
+}
+
+/**
+  * @brief Clear Stream 1 direct mode error flag.
+  * @rmtoll LIFCR  CDMEIF1    LL_DMA_ClearFlag_DME1
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_DME1(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CDMEIF1);
+}
+
+/**
+  * @brief Clear Stream 2 direct mode error flag.
+  * @rmtoll LIFCR  CDMEIF2    LL_DMA_ClearFlag_DME2
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_DME2(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CDMEIF2);
+}
+
+/**
+  * @brief Clear Stream 3 direct mode error flag.
+  * @rmtoll LIFCR  CDMEIF3    LL_DMA_ClearFlag_DME3
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_DME3(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CDMEIF3);
+}
+
+/**
+  * @brief Clear Stream 4 direct mode error flag.
+  * @rmtoll HIFCR  CDMEIF4    LL_DMA_ClearFlag_DME4
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_DME4(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CDMEIF4);
+}
+
+/**
+  * @brief Clear Stream 5 direct mode error flag.
+  * @rmtoll HIFCR  CDMEIF5    LL_DMA_ClearFlag_DME5
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_DME5(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CDMEIF5);
+}
+
+/**
+  * @brief Clear Stream 6 direct mode error flag.
+  * @rmtoll HIFCR  CDMEIF6    LL_DMA_ClearFlag_DME6
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_DME6(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CDMEIF6);
+}
+
+/**
+  * @brief Clear Stream 7 direct mode error flag.
+  * @rmtoll HIFCR  CDMEIF7    LL_DMA_ClearFlag_DME7
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_DME7(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CDMEIF7);
+}
+
+/**
+  * @brief Clear Stream 0 FIFO error flag.
+  * @rmtoll LIFCR  CFEIF0    LL_DMA_ClearFlag_FE0
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_FE0(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CFEIF0);
+}
+
+/**
+  * @brief Clear Stream 1 FIFO error flag.
+  * @rmtoll LIFCR  CFEIF1    LL_DMA_ClearFlag_FE1
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_FE1(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CFEIF1);
+}
+
+/**
+  * @brief Clear Stream 2 FIFO error flag.
+  * @rmtoll LIFCR  CFEIF2    LL_DMA_ClearFlag_FE2
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_FE2(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CFEIF2);
+}
+
+/**
+  * @brief Clear Stream 3 FIFO error flag.
+  * @rmtoll LIFCR  CFEIF3    LL_DMA_ClearFlag_FE3
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_FE3(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CFEIF3);
+}
+
+/**
+  * @brief Clear Stream 4 FIFO error flag.
+  * @rmtoll HIFCR  CFEIF4    LL_DMA_ClearFlag_FE4
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_FE4(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CFEIF4);
+}
+
+/**
+  * @brief Clear Stream 5 FIFO error flag.
+  * @rmtoll HIFCR  CFEIF5    LL_DMA_ClearFlag_FE5
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_FE5(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CFEIF5);
+}
+
+/**
+  * @brief Clear Stream 6 FIFO error flag.
+  * @rmtoll HIFCR  CFEIF6    LL_DMA_ClearFlag_FE6
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_FE6(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CFEIF6);
+}
+
+/**
+  * @brief Clear Stream 7 FIFO error flag.
+  * @rmtoll HIFCR  CFEIF7    LL_DMA_ClearFlag_FE7
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_FE7(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CFEIF7);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup DMA_LL_EF_IT_Management IT_Management
+  * @{
+  */
+
+/**
+  * @brief Enable Half transfer interrupt.
+  * @rmtoll CR        HTIE         LL_DMA_EnableIT_HT
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_EnableIT_HT(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_HTIE);
+}
+
+/**
+  * @brief Enable Transfer error interrupt.
+  * @rmtoll CR        TEIE         LL_DMA_EnableIT_TE
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_EnableIT_TE(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_TEIE);
+}
+
+/**
+  * @brief Enable Transfer complete interrupt.
+  * @rmtoll CR        TCIE         LL_DMA_EnableIT_TC
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_EnableIT_TC(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_TCIE);
+}
+
+/**
+  * @brief Enable Direct mode error interrupt.
+  * @rmtoll CR        DMEIE         LL_DMA_EnableIT_DME
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_EnableIT_DME(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_DMEIE);
+}
+
+/**
+  * @brief Enable FIFO error interrupt.
+  * @rmtoll FCR        FEIE         LL_DMA_EnableIT_FE
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_EnableIT_FE(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FEIE);
+}
+
+/**
+  * @brief Disable Half transfer interrupt.
+  * @rmtoll CR        HTIE         LL_DMA_DisableIT_HT
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_DisableIT_HT(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_HTIE);
+}
+
+/**
+  * @brief Disable Transfer error interrupt.
+  * @rmtoll CR        TEIE         LL_DMA_DisableIT_TE
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_DisableIT_TE(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_TEIE);
+}
+
+/**
+  * @brief Disable Transfer complete interrupt.
+  * @rmtoll CR        TCIE         LL_DMA_DisableIT_TC
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_DisableIT_TC(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_TCIE);
+}
+
+/**
+  * @brief Disable Direct mode error interrupt.
+  * @rmtoll CR        DMEIE         LL_DMA_DisableIT_DME
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_DisableIT_DME(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_DMEIE);
+}
+
+/**
+  * @brief Disable FIFO error interrupt.
+  * @rmtoll FCR        FEIE         LL_DMA_DisableIT_FE
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_DisableIT_FE(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FEIE);
+}
+
+/**
+  * @brief Check if Half transfer interrupt is enabled.
+  * @rmtoll CR        HTIE         LL_DMA_IsEnabledIT_HT
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_HTIE) == DMA_SxCR_HTIE);
+}
+
+/**
+  * @brief Check if Transfer error nterrup is enabled.
+  * @rmtoll CR        TEIE         LL_DMA_IsEnabledIT_TE
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TE(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_TEIE) == DMA_SxCR_TEIE);
+}
+
+/**
+  * @brief Check if Transfer complete interrupt is enabled.
+  * @rmtoll CR        TCIE         LL_DMA_IsEnabledIT_TC
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_TCIE) == DMA_SxCR_TCIE);
+}
+
+/**
+  * @brief Check if Direct mode error interrupt is enabled.
+  * @rmtoll CR        DMEIE         LL_DMA_IsEnabledIT_DME
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_DME(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_DMEIE) == DMA_SxCR_DMEIE);
+}
+
+/**
+  * @brief Check if FIFO error interrupt is enabled.
+  * @rmtoll FCR        FEIE         LL_DMA_IsEnabledIT_FE
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_FE(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FEIE) == DMA_SxFCR_FEIE);
+}
+
+/**
+  * @}
+  */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup DMA_LL_EF_Init Initialization and de-initialization functions
+  * @{
+  */
+
+uint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Stream, LL_DMA_InitTypeDef *DMA_InitStruct);
+uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Stream);
+void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct);
+
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* DMA1 || DMA2 */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_LL_DMA_H */
+
diff --git a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_dma2d.h b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_dma2d.h
new file mode 100644
index 0000000..967ac02
--- /dev/null
+++ b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_dma2d.h
@@ -0,0 +1,1901 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_ll_dma2d.h
+  * @author  MCD Application Team
+  * @brief   Header file of DMA2D LL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2016 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32F4xx_LL_DMA2D_H
+#define STM32F4xx_LL_DMA2D_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx.h"
+
+/** @addtogroup STM32F4xx_LL_Driver
+  * @{
+  */
+
+#if defined (DMA2D)
+
+/** @defgroup DMA2D_LL DMA2D
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup DMA2D_LL_Private_Macros DMA2D Private Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+#endif /*USE_FULL_LL_DRIVER*/
+
+/* Exported types ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup DMA2D_LL_ES_Init_Struct DMA2D Exported Init structures
+  * @{
+  */
+
+/**
+  * @brief LL DMA2D Init Structure Definition
+  */
+typedef struct
+{
+  uint32_t Mode;                 /*!< Specifies the DMA2D transfer mode.
+                                      - This parameter can be one value of @ref DMA2D_LL_EC_MODE.
+
+                                      This parameter can be modified afterwards,
+                                      using unitary function @ref LL_DMA2D_SetMode(). */
+
+  uint32_t ColorMode;            /*!< Specifies the color format of the output image.
+                                      - This parameter can be one value of @ref DMA2D_LL_EC_OUTPUT_COLOR_MODE.
+
+                                      This parameter can be modified afterwards using,
+                                      unitary function @ref LL_DMA2D_SetOutputColorMode(). */
+
+  uint32_t OutputBlue;           /*!< Specifies the Blue value of the output image.
+                                      - This parameter must be a number between:
+                                        Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
+                                      - This parameter must be a number between:
+                                        Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected.
+                                      - This parameter must be a number between:
+                                        Min_Data = 0x00 and Max_Data = 0x1F if RGB565 color mode is selected.
+                                      - This parameter must be a number between:
+                                        Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected.
+                                      - This parameter must be a number between:
+                                        Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
+
+                                      This parameter can be modified afterwards,
+                                      using unitary function @ref LL_DMA2D_SetOutputColor() or configuration
+                                      function @ref LL_DMA2D_ConfigOutputColor(). */
+
+  uint32_t OutputGreen;          /*!< Specifies the Green value of the output image.
+                                      - This parameter must be a number between:
+                                        Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
+                                      - This parameter must be a number between:
+                                        Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected.
+                                      - This parameter must be a number between:
+                                        Min_Data = 0x00 and Max_Data = 0x3F if RGB565 color mode is selected.
+                                      - This parameter must be a number between:
+                                        Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected.
+                                      - This parameter must be a number between:
+                                        Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
+
+                                      This parameter can be modified afterwards
+                                      using unitary function @ref LL_DMA2D_SetOutputColor() or configuration
+                                      function @ref LL_DMA2D_ConfigOutputColor(). */
+
+  uint32_t OutputRed;            /*!< Specifies the Red value of the output image.
+                                      - This parameter must be a number between:
+                                        Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
+                                      - This parameter must be a number between:
+                                        Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected.
+                                      - This parameter must be a number between:
+                                        Min_Data = 0x00 and Max_Data = 0x1F if RGB565 color mode is selected.
+                                      - This parameter must be a number between:
+                                        Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected.
+                                      - This parameter must be a number between:
+                                        Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
+
+                                      This parameter can be modified afterwards
+                                      using unitary function @ref LL_DMA2D_SetOutputColor() or configuration
+                                      function @ref LL_DMA2D_ConfigOutputColor(). */
+
+  uint32_t OutputAlpha;          /*!< Specifies the Alpha channel of the output image.
+                                      - This parameter must be a number between:
+                                        Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
+                                      - This parameter must be a number between:
+                                        Min_Data = 0x00 and Max_Data = 0x01 if ARGB1555 color mode is selected.
+                                      - This parameter must be a number between:
+                                        Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
+                                      - This parameter is not considered if RGB888 or RGB565 color mode is selected.
+
+                                      This parameter can be modified afterwards using,
+                                      unitary function @ref LL_DMA2D_SetOutputColor() or configuration
+                                      function @ref LL_DMA2D_ConfigOutputColor(). */
+
+  uint32_t OutputMemoryAddress;  /*!< Specifies the memory address.
+                                      - This parameter must be a number between:
+                                        Min_Data = 0x0000 and Max_Data = 0xFFFFFFFF.
+
+                                      This parameter can be modified afterwards,
+                                      using unitary function @ref LL_DMA2D_SetOutputMemAddr(). */
+
+
+
+  uint32_t LineOffset;           /*!< Specifies the output line offset value.
+                                      - This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF.
+
+                                      This parameter can be modified afterwards,
+                                      using unitary function @ref LL_DMA2D_SetLineOffset(). */
+
+  uint32_t NbrOfLines;           /*!< Specifies the number of lines of the area to be transferred.
+                                      - This parameter must be a number between:
+                                        Min_Data = 0x0000 and Max_Data = 0xFFFF.
+
+                                      This parameter can be modified afterwards,
+                                      using unitary function @ref LL_DMA2D_SetNbrOfLines(). */
+
+  uint32_t NbrOfPixelsPerLines;  /*!< Specifies the number of pixels per lines of the area to be transferred.
+                                      - This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF.
+
+                                      This parameter can be modified afterwards using,
+                                      unitary function @ref LL_DMA2D_SetNbrOfPixelsPerLines(). */
+
+
+} LL_DMA2D_InitTypeDef;
+
+/**
+  * @brief LL DMA2D Layer Configuration Structure Definition
+  */
+typedef struct
+{
+  uint32_t MemoryAddress;        /*!< Specifies the foreground or background memory address.
+                                      - This parameter must be a number between:
+                                        Min_Data = 0x0000 and Max_Data = 0xFFFFFFFF.
+
+                                      This parameter can be modified afterwards using unitary functions
+                                      - @ref LL_DMA2D_FGND_SetMemAddr() for foreground layer,
+                                      - @ref LL_DMA2D_BGND_SetMemAddr() for background layer. */
+
+  uint32_t LineOffset;           /*!< Specifies the foreground or background line offset value.
+                                      - This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF.
+
+                                      This parameter can be modified afterwards using unitary functions
+                                      - @ref LL_DMA2D_FGND_SetLineOffset() for foreground layer,
+                                      - @ref LL_DMA2D_BGND_SetLineOffset() for background layer. */
+
+  uint32_t ColorMode;            /*!< Specifies the foreground or background color mode.
+                                      - This parameter can be one value of @ref DMA2D_LL_EC_INPUT_COLOR_MODE.
+
+                                      This parameter can be modified afterwards using unitary functions
+                                      - @ref LL_DMA2D_FGND_SetColorMode() for foreground layer,
+                                      - @ref LL_DMA2D_BGND_SetColorMode() for background layer. */
+
+  uint32_t CLUTColorMode;        /*!< Specifies the foreground or background CLUT color mode.
+                                       - This parameter can be one value of @ref DMA2D_LL_EC_CLUT_COLOR_MODE.
+
+                                      This parameter can be modified afterwards using unitary functions
+                                      - @ref LL_DMA2D_FGND_SetCLUTColorMode() for foreground layer,
+                                      - @ref LL_DMA2D_BGND_SetCLUTColorMode() for background layer. */
+
+  uint32_t CLUTSize;             /*!< Specifies the foreground or background CLUT size.
+                                      - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
+
+                                      This parameter can be modified afterwards using unitary functions
+                                      - @ref LL_DMA2D_FGND_SetCLUTSize() for foreground layer,
+                                      - @ref LL_DMA2D_BGND_SetCLUTSize() for background layer. */
+
+  uint32_t AlphaMode;            /*!< Specifies the foreground or background alpha mode.
+                                       - This parameter can be one value of @ref DMA2D_LL_EC_ALPHA_MODE.
+
+                                      This parameter can be modified afterwards using unitary functions
+                                      - @ref LL_DMA2D_FGND_SetAlphaMode() for foreground layer,
+                                      - @ref LL_DMA2D_BGND_SetAlphaMode() for background layer. */
+
+  uint32_t Alpha;                /*!< Specifies the foreground or background Alpha value.
+                                      - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
+
+                                      This parameter can be modified afterwards using unitary functions
+                                      - @ref LL_DMA2D_FGND_SetAlpha() for foreground layer,
+                                      - @ref LL_DMA2D_BGND_SetAlpha() for background layer. */
+
+  uint32_t Blue;                 /*!< Specifies the foreground or background Blue color value.
+                                      - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
+
+                                      This parameter can be modified afterwards using unitary functions
+                                      - @ref LL_DMA2D_FGND_SetBlueColor() for foreground layer,
+                                      - @ref LL_DMA2D_BGND_SetBlueColor() for background layer. */
+
+  uint32_t Green;                /*!< Specifies the foreground or background Green color value.
+                                      - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
+
+                                      This parameter can be modified afterwards using unitary functions
+                                      - @ref LL_DMA2D_FGND_SetGreenColor() for foreground layer,
+                                      - @ref LL_DMA2D_BGND_SetGreenColor() for background layer. */
+
+  uint32_t Red;                  /*!< Specifies the foreground or background Red color value.
+                                      - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
+
+                                      This parameter can be modified afterwards using unitary functions
+                                      - @ref LL_DMA2D_FGND_SetRedColor() for foreground layer,
+                                      - @ref LL_DMA2D_BGND_SetRedColor() for background layer. */
+
+  uint32_t CLUTMemoryAddress;    /*!< Specifies the foreground or background CLUT memory address.
+                                      - This parameter must be a number between:
+                                        Min_Data = 0x0000 and Max_Data = 0xFFFFFFFF.
+
+                                      This parameter can be modified afterwards using unitary functions
+                                      - @ref LL_DMA2D_FGND_SetCLUTMemAddr() for foreground layer,
+                                      - @ref LL_DMA2D_BGND_SetCLUTMemAddr() for background layer. */
+
+
+
+} LL_DMA2D_LayerCfgTypeDef;
+
+/**
+  * @brief LL DMA2D Output Color Structure Definition
+  */
+typedef struct
+{
+  uint32_t ColorMode;            /*!< Specifies the color format of the output image.
+                                      - This parameter can be one value of @ref DMA2D_LL_EC_OUTPUT_COLOR_MODE.
+
+                                      This parameter can be modified afterwards using
+                    unitary function @ref LL_DMA2D_SetOutputColorMode(). */
+
+  uint32_t OutputBlue;           /*!< Specifies the Blue value of the output image.
+                                      - This parameter must be a number between:
+                                        Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
+                                      - This parameter must be a number between:
+                                        Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected.
+                                      - This parameter must be a number between:
+                                        Min_Data = 0x00 and Max_Data = 0x1F if RGB565 color mode is selected.
+                                      - This parameter must be a number between:
+                                        Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected.
+                                      - This parameter must be a number between:
+                                        Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
+
+                                      This parameter can be modified afterwards using,
+                                      unitary function @ref LL_DMA2D_SetOutputColor() or configuration
+                                      function @ref LL_DMA2D_ConfigOutputColor(). */
+
+  uint32_t OutputGreen;          /*!< Specifies the Green value of the output image.
+                                      - This parameter must be a number between:
+                                        Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
+                                      - This parameter must be a number between
+                                        Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected.
+                                      - This parameter must be a number between:
+                                        Min_Data = 0x00 and Max_Data = 0x3F if RGB565 color mode is selected.
+                                      - This parameter must be a number between:
+                                        Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected.
+                                      - This parameter must be a number between:
+                                        Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
+
+                                      This parameter can be modified afterwards,
+                                      using unitary function @ref LL_DMA2D_SetOutputColor() or configuration
+                                      function @ref LL_DMA2D_ConfigOutputColor(). */
+
+  uint32_t OutputRed;            /*!< Specifies the Red value of the output image.
+                                      - This parameter must be a number between:
+                                        Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
+                                      - This parameter must be a number between:
+                                        Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected.
+                                      - This parameter must be a number between:
+                                        Min_Data = 0x00 and Max_Data = 0x1F if RGB565 color mode is selected.
+                                      - This parameter must be a number between:
+                                        Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected.
+                                      - This parameter must be a number between:
+                                        Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
+
+                                      This parameter can be modified afterwards,
+                                      using unitary function @ref LL_DMA2D_SetOutputColor() or configuration
+                                      function @ref LL_DMA2D_ConfigOutputColor(). */
+
+  uint32_t OutputAlpha;          /*!< Specifies the Alpha channel of the output image.
+                                      - This parameter must be a number between:
+                                        Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
+                                      - This parameter must be a number between:
+                                        Min_Data = 0x00 and Max_Data = 0x01 if ARGB1555 color mode is selected.
+                                      - This parameter must be a number between:
+                                        Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
+                                      - This parameter is not considered if RGB888 or RGB565 color mode is selected.
+
+                                      This parameter can be modified afterwards,
+                                      using unitary function @ref LL_DMA2D_SetOutputColor() or configuration
+                                      function @ref LL_DMA2D_ConfigOutputColor(). */
+
+} LL_DMA2D_ColorTypeDef;
+
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup DMA2D_LL_Exported_Constants DMA2D Exported Constants
+  * @{
+  */
+
+/** @defgroup DMA2D_LL_EC_GET_FLAG Get Flags Defines
+  * @brief    Flags defines which can be used with LL_DMA2D_ReadReg function
+  * @{
+  */
+#define LL_DMA2D_FLAG_CEIF          DMA2D_ISR_CEIF     /*!< Configuration Error Interrupt Flag */
+#define LL_DMA2D_FLAG_CTCIF         DMA2D_ISR_CTCIF    /*!< CLUT Transfer Complete Interrupt Flag */
+#define LL_DMA2D_FLAG_CAEIF         DMA2D_ISR_CAEIF    /*!< CLUT Access Error Interrupt Flag */
+#define LL_DMA2D_FLAG_TWIF          DMA2D_ISR_TWIF     /*!< Transfer Watermark Interrupt Flag */
+#define LL_DMA2D_FLAG_TCIF          DMA2D_ISR_TCIF     /*!< Transfer Complete Interrupt Flag */
+#define LL_DMA2D_FLAG_TEIF          DMA2D_ISR_TEIF     /*!< Transfer Error Interrupt Flag */
+/**
+  * @}
+  */
+
+/** @defgroup DMA2D_LL_EC_IT IT Defines
+  * @brief    IT defines which can be used with LL_DMA2D_ReadReg and  LL_DMA2D_WriteReg functions
+  * @{
+  */
+#define LL_DMA2D_IT_CEIE             DMA2D_CR_CEIE    /*!< Configuration Error Interrupt */
+#define LL_DMA2D_IT_CTCIE            DMA2D_CR_CTCIE   /*!< CLUT Transfer Complete Interrupt */
+#define LL_DMA2D_IT_CAEIE            DMA2D_CR_CAEIE   /*!< CLUT Access Error Interrupt */
+#define LL_DMA2D_IT_TWIE             DMA2D_CR_TWIE    /*!< Transfer Watermark Interrupt */
+#define LL_DMA2D_IT_TCIE             DMA2D_CR_TCIE    /*!< Transfer Complete Interrupt */
+#define LL_DMA2D_IT_TEIE             DMA2D_CR_TEIE    /*!< Transfer Error Interrupt */
+/**
+  * @}
+  */
+
+/** @defgroup DMA2D_LL_EC_MODE Mode
+  * @{
+  */
+#define LL_DMA2D_MODE_M2M                       0x00000000U                       /*!< DMA2D memory to memory transfer mode */
+#define LL_DMA2D_MODE_M2M_PFC                   DMA2D_CR_MODE_0                   /*!< DMA2D memory to memory with pixel format conversion transfer mode */
+#define LL_DMA2D_MODE_M2M_BLEND                 DMA2D_CR_MODE_1                   /*!< DMA2D memory to memory with blending transfer mode */
+#define LL_DMA2D_MODE_R2M                       DMA2D_CR_MODE                     /*!< DMA2D register to memory transfer mode */
+/**
+  * @}
+  */
+
+/** @defgroup DMA2D_LL_EC_OUTPUT_COLOR_MODE Output Color Mode
+  * @{
+  */
+#define LL_DMA2D_OUTPUT_MODE_ARGB8888     0x00000000U                           /*!< ARGB8888 */
+#define LL_DMA2D_OUTPUT_MODE_RGB888       DMA2D_OPFCCR_CM_0                     /*!< RGB888   */
+#define LL_DMA2D_OUTPUT_MODE_RGB565       DMA2D_OPFCCR_CM_1                     /*!< RGB565   */
+#define LL_DMA2D_OUTPUT_MODE_ARGB1555     (DMA2D_OPFCCR_CM_0|DMA2D_OPFCCR_CM_1) /*!< ARGB1555 */
+#define LL_DMA2D_OUTPUT_MODE_ARGB4444     DMA2D_OPFCCR_CM_2                     /*!< ARGB4444 */
+/**
+  * @}
+  */
+
+/** @defgroup DMA2D_LL_EC_INPUT_COLOR_MODE Input Color Mode
+  * @{
+  */
+#define LL_DMA2D_INPUT_MODE_ARGB8888      0x00000000U                                                /*!< ARGB8888 */
+#define LL_DMA2D_INPUT_MODE_RGB888        DMA2D_FGPFCCR_CM_0                                         /*!< RGB888   */
+#define LL_DMA2D_INPUT_MODE_RGB565        DMA2D_FGPFCCR_CM_1                                         /*!< RGB565   */
+#define LL_DMA2D_INPUT_MODE_ARGB1555      (DMA2D_FGPFCCR_CM_0|DMA2D_FGPFCCR_CM_1)                    /*!< ARGB1555 */
+#define LL_DMA2D_INPUT_MODE_ARGB4444      DMA2D_FGPFCCR_CM_2                                         /*!< ARGB4444 */
+#define LL_DMA2D_INPUT_MODE_L8            (DMA2D_FGPFCCR_CM_0|DMA2D_FGPFCCR_CM_2)                    /*!< L8       */
+#define LL_DMA2D_INPUT_MODE_AL44          (DMA2D_FGPFCCR_CM_1|DMA2D_FGPFCCR_CM_2)                    /*!< AL44     */
+#define LL_DMA2D_INPUT_MODE_AL88          (DMA2D_FGPFCCR_CM_0|DMA2D_FGPFCCR_CM_1|DMA2D_FGPFCCR_CM_2) /*!< AL88     */
+#define LL_DMA2D_INPUT_MODE_L4            DMA2D_FGPFCCR_CM_3                                         /*!< L4       */
+#define LL_DMA2D_INPUT_MODE_A8            (DMA2D_FGPFCCR_CM_0|DMA2D_FGPFCCR_CM_3)                    /*!< A8       */
+#define LL_DMA2D_INPUT_MODE_A4            (DMA2D_FGPFCCR_CM_1|DMA2D_FGPFCCR_CM_3)                    /*!< A4       */
+/**
+  * @}
+  */
+
+/** @defgroup DMA2D_LL_EC_ALPHA_MODE Alpha Mode
+  * @{
+  */
+#define LL_DMA2D_ALPHA_MODE_NO_MODIF       0x00000000U             /*!< No modification of the alpha channel value */
+#define LL_DMA2D_ALPHA_MODE_REPLACE        DMA2D_FGPFCCR_AM_0      /*!< Replace original alpha channel value by
+                                                                        programmed alpha value                     */
+#define LL_DMA2D_ALPHA_MODE_COMBINE        DMA2D_FGPFCCR_AM_1      /*!< Replace original alpha channel value by
+                                                                        programmed alpha value with,
+                                                                        original alpha channel value               */
+/**
+  * @}
+  */
+
+
+
+
+/** @defgroup DMA2D_LL_EC_CLUT_COLOR_MODE CLUT Color Mode
+  * @{
+  */
+#define LL_DMA2D_CLUT_COLOR_MODE_ARGB8888          0x00000000U                     /*!< ARGB8888 */
+#define LL_DMA2D_CLUT_COLOR_MODE_RGB888            DMA2D_FGPFCCR_CCM               /*!< RGB888   */
+/**
+  * @}
+  */
+
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup DMA2D_LL_Exported_Macros DMA2D Exported Macros
+  * @{
+  */
+
+/** @defgroup DMA2D_LL_EM_WRITE_READ Common Write and read registers Macros
+  * @{
+  */
+
+/**
+  * @brief  Write a value in DMA2D register.
+  * @param  __INSTANCE__ DMA2D Instance
+  * @param  __REG__ Register to be written
+  * @param  __VALUE__ Value to be written in the register
+  * @retval None
+  */
+#define LL_DMA2D_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))
+
+/**
+  * @brief  Read a value in DMA2D register.
+  * @param  __INSTANCE__ DMA2D Instance
+  * @param  __REG__ Register to be read
+  * @retval Register value
+  */
+#define LL_DMA2D_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__)
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup DMA2D_LL_Exported_Functions DMA2D Exported Functions
+  * @{
+  */
+
+/** @defgroup DMA2D_LL_EF_Configuration Configuration Functions
+  * @{
+  */
+
+/**
+  * @brief  Start a DMA2D transfer.
+  * @rmtoll CR          START            LL_DMA2D_Start
+  * @param  DMA2Dx DMA2D Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA2D_Start(DMA2D_TypeDef *DMA2Dx)
+{
+  SET_BIT(DMA2Dx->CR, DMA2D_CR_START);
+}
+
+/**
+  * @brief  Indicate if a DMA2D transfer is ongoing.
+  * @rmtoll CR          START            LL_DMA2D_IsTransferOngoing
+  * @param  DMA2Dx DMA2D Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA2D_IsTransferOngoing(DMA2D_TypeDef *DMA2Dx)
+{
+  return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_START) == (DMA2D_CR_START)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Suspend DMA2D transfer.
+  * @note   This API can be used to suspend automatic foreground or background CLUT loading.
+  * @rmtoll CR          SUSP            LL_DMA2D_Suspend
+  * @param  DMA2Dx DMA2D Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA2D_Suspend(DMA2D_TypeDef *DMA2Dx)
+{
+  MODIFY_REG(DMA2Dx->CR, DMA2D_CR_SUSP | DMA2D_CR_START, DMA2D_CR_SUSP);
+}
+
+/**
+  * @brief  Resume DMA2D transfer.
+  * @note   This API can be used to resume automatic foreground or background CLUT loading.
+  * @rmtoll CR          SUSP            LL_DMA2D_Resume
+  * @param  DMA2Dx DMA2D Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA2D_Resume(DMA2D_TypeDef *DMA2Dx)
+{
+  CLEAR_BIT(DMA2Dx->CR, DMA2D_CR_SUSP | DMA2D_CR_START);
+}
+
+/**
+  * @brief  Indicate if DMA2D transfer is suspended.
+  * @note   This API can be used to indicate whether or not automatic foreground or
+  *         background CLUT loading is suspended.
+  * @rmtoll CR          SUSP            LL_DMA2D_IsSuspended
+  * @param  DMA2Dx DMA2D Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA2D_IsSuspended(DMA2D_TypeDef *DMA2Dx)
+{
+  return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_SUSP) == (DMA2D_CR_SUSP)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Abort DMA2D transfer.
+  * @note   This API can be used to abort automatic foreground or background CLUT loading.
+  * @rmtoll CR          ABORT            LL_DMA2D_Abort
+  * @param  DMA2Dx DMA2D Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA2D_Abort(DMA2D_TypeDef *DMA2Dx)
+{
+  MODIFY_REG(DMA2Dx->CR, DMA2D_CR_ABORT | DMA2D_CR_START, DMA2D_CR_ABORT);
+}
+
+/**
+  * @brief  Indicate if DMA2D transfer is aborted.
+  * @note   This API can be used to indicate whether or not automatic foreground or
+  *         background CLUT loading is aborted.
+  * @rmtoll CR          ABORT            LL_DMA2D_IsAborted
+  * @param  DMA2Dx DMA2D Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA2D_IsAborted(DMA2D_TypeDef *DMA2Dx)
+{
+  return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_ABORT) == (DMA2D_CR_ABORT)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Set DMA2D mode.
+  * @rmtoll CR          MODE          LL_DMA2D_SetMode
+  * @param  DMA2Dx DMA2D Instance
+  * @param  Mode This parameter can be one of the following values:
+  *         @arg @ref LL_DMA2D_MODE_M2M
+  *         @arg @ref LL_DMA2D_MODE_M2M_PFC
+  *         @arg @ref LL_DMA2D_MODE_M2M_BLEND
+  *         @arg @ref LL_DMA2D_MODE_R2M
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA2D_SetMode(DMA2D_TypeDef *DMA2Dx, uint32_t Mode)
+{
+  MODIFY_REG(DMA2Dx->CR, DMA2D_CR_MODE, Mode);
+}
+
+/**
+  * @brief  Return DMA2D mode
+  * @rmtoll CR          MODE         LL_DMA2D_GetMode
+  * @param  DMA2Dx DMA2D Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DMA2D_MODE_M2M
+  *         @arg @ref LL_DMA2D_MODE_M2M_PFC
+  *         @arg @ref LL_DMA2D_MODE_M2M_BLEND
+  *         @arg @ref LL_DMA2D_MODE_R2M
+  */
+__STATIC_INLINE uint32_t LL_DMA2D_GetMode(DMA2D_TypeDef *DMA2Dx)
+{
+  return (uint32_t)(READ_BIT(DMA2Dx->CR, DMA2D_CR_MODE));
+}
+
+/**
+  * @brief  Set DMA2D output color mode.
+  * @rmtoll OPFCCR          CM          LL_DMA2D_SetOutputColorMode
+  * @param  DMA2Dx DMA2D Instance
+  * @param  ColorMode This parameter can be one of the following values:
+  *         @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB8888
+  *         @arg @ref LL_DMA2D_OUTPUT_MODE_RGB888
+  *         @arg @ref LL_DMA2D_OUTPUT_MODE_RGB565
+  *         @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB1555
+  *         @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB4444
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA2D_SetOutputColorMode(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode)
+{
+  MODIFY_REG(DMA2Dx->OPFCCR, DMA2D_OPFCCR_CM, ColorMode);
+}
+
+/**
+  * @brief  Return DMA2D output color mode.
+  * @rmtoll OPFCCR          CM         LL_DMA2D_GetOutputColorMode
+  * @param  DMA2Dx DMA2D Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB8888
+  *         @arg @ref LL_DMA2D_OUTPUT_MODE_RGB888
+  *         @arg @ref LL_DMA2D_OUTPUT_MODE_RGB565
+  *         @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB1555
+  *         @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB4444
+  */
+__STATIC_INLINE uint32_t LL_DMA2D_GetOutputColorMode(DMA2D_TypeDef *DMA2Dx)
+{
+  return (uint32_t)(READ_BIT(DMA2Dx->OPFCCR, DMA2D_OPFCCR_CM));
+}
+
+
+
+
+/**
+  * @brief  Set DMA2D line offset, expressed on 14 bits ([13:0] bits).
+  * @rmtoll OOR          LO          LL_DMA2D_SetLineOffset
+  * @param  DMA2Dx DMA2D Instance
+  * @param  LineOffset Value between Min_Data=0 and Max_Data=0x3FFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA2D_SetLineOffset(DMA2D_TypeDef *DMA2Dx, uint32_t LineOffset)
+{
+  MODIFY_REG(DMA2Dx->OOR, DMA2D_OOR_LO, LineOffset);
+}
+
+/**
+  * @brief  Return DMA2D line offset, expressed on 14 bits ([13:0] bits).
+  * @rmtoll OOR          LO         LL_DMA2D_GetLineOffset
+  * @param  DMA2Dx DMA2D Instance
+  * @retval Line offset value between Min_Data=0 and Max_Data=0x3FFF
+  */
+__STATIC_INLINE uint32_t LL_DMA2D_GetLineOffset(DMA2D_TypeDef *DMA2Dx)
+{
+  return (uint32_t)(READ_BIT(DMA2Dx->OOR, DMA2D_OOR_LO));
+}
+
+/**
+  * @brief  Set DMA2D number of pixels per lines, expressed on 14 bits ([13:0] bits).
+  * @rmtoll NLR          PL          LL_DMA2D_SetNbrOfPixelsPerLines
+  * @param  DMA2Dx DMA2D Instance
+  * @param  NbrOfPixelsPerLines Value between Min_Data=0 and Max_Data=0x3FFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA2D_SetNbrOfPixelsPerLines(DMA2D_TypeDef *DMA2Dx, uint32_t NbrOfPixelsPerLines)
+{
+  MODIFY_REG(DMA2Dx->NLR, DMA2D_NLR_PL, (NbrOfPixelsPerLines << DMA2D_NLR_PL_Pos));
+}
+
+/**
+  * @brief  Return DMA2D number of pixels per lines, expressed on 14 bits ([13:0] bits)
+  * @rmtoll NLR          PL          LL_DMA2D_GetNbrOfPixelsPerLines
+  * @param  DMA2Dx DMA2D Instance
+  * @retval Number of pixels per lines value between Min_Data=0 and Max_Data=0x3FFF
+  */
+__STATIC_INLINE uint32_t LL_DMA2D_GetNbrOfPixelsPerLines(DMA2D_TypeDef *DMA2Dx)
+{
+  return (uint32_t)(READ_BIT(DMA2Dx->NLR, DMA2D_NLR_PL) >> DMA2D_NLR_PL_Pos);
+}
+
+/**
+  * @brief  Set DMA2D number of lines, expressed on 16 bits ([15:0] bits).
+  * @rmtoll NLR          NL          LL_DMA2D_SetNbrOfLines
+  * @param  DMA2Dx DMA2D Instance
+  * @param  NbrOfLines Value between Min_Data=0 and Max_Data=0xFFFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA2D_SetNbrOfLines(DMA2D_TypeDef *DMA2Dx, uint32_t NbrOfLines)
+{
+  MODIFY_REG(DMA2Dx->NLR, DMA2D_NLR_NL, NbrOfLines);
+}
+
+/**
+  * @brief  Return DMA2D number of lines, expressed on 16 bits ([15:0] bits).
+  * @rmtoll NLR          NL          LL_DMA2D_GetNbrOfLines
+  * @param  DMA2Dx DMA2D Instance
+  * @retval Number of lines value between Min_Data=0 and Max_Data=0xFFFF
+  */
+__STATIC_INLINE uint32_t LL_DMA2D_GetNbrOfLines(DMA2D_TypeDef *DMA2Dx)
+{
+  return (uint32_t)(READ_BIT(DMA2Dx->NLR, DMA2D_NLR_NL));
+}
+
+/**
+  * @brief  Set DMA2D output memory address, expressed on 32 bits ([31:0] bits).
+  * @rmtoll OMAR          MA          LL_DMA2D_SetOutputMemAddr
+  * @param  DMA2Dx DMA2D Instance
+  * @param  OutputMemoryAddress Value between Min_Data=0 and Max_Data=0xFFFFFFFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA2D_SetOutputMemAddr(DMA2D_TypeDef *DMA2Dx, uint32_t OutputMemoryAddress)
+{
+  LL_DMA2D_WriteReg(DMA2Dx, OMAR, OutputMemoryAddress);
+}
+
+/**
+  * @brief  Get DMA2D output memory address, expressed on 32 bits ([31:0] bits).
+  * @rmtoll OMAR          MA          LL_DMA2D_GetOutputMemAddr
+  * @param  DMA2Dx DMA2D Instance
+  * @retval Output memory address value between Min_Data=0 and Max_Data=0xFFFFFFFF
+  */
+__STATIC_INLINE uint32_t LL_DMA2D_GetOutputMemAddr(DMA2D_TypeDef *DMA2Dx)
+{
+  return (uint32_t)(LL_DMA2D_ReadReg(DMA2Dx, OMAR));
+}
+
+/**
+  * @brief  Set DMA2D output color, expressed on 32 bits ([31:0] bits).
+  * @note   Output color format depends on output color mode, ARGB8888, RGB888,
+  *         RGB565, ARGB1555 or ARGB4444.
+  * @note LL_DMA2D_ConfigOutputColor() API may be used instead if colors values formatting
+  *       with respect to color mode is not done by the user code.
+  * @rmtoll OCOLR        BLUE        LL_DMA2D_SetOutputColor\n
+  *         OCOLR        GREEN       LL_DMA2D_SetOutputColor\n
+  *         OCOLR        RED         LL_DMA2D_SetOutputColor\n
+  *         OCOLR        ALPHA       LL_DMA2D_SetOutputColor
+  * @param  DMA2Dx DMA2D Instance
+  * @param  OutputColor Value between Min_Data=0 and Max_Data=0xFFFFFFFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA2D_SetOutputColor(DMA2D_TypeDef *DMA2Dx, uint32_t OutputColor)
+{
+  MODIFY_REG(DMA2Dx->OCOLR, (DMA2D_OCOLR_BLUE_1 | DMA2D_OCOLR_GREEN_1 | DMA2D_OCOLR_RED_1 | DMA2D_OCOLR_ALPHA_1), \
+             OutputColor);
+}
+
+/**
+  * @brief  Get DMA2D output color, expressed on 32 bits ([31:0] bits).
+  * @note   Alpha channel and red, green, blue color values must be retrieved from the returned
+  *         value based on the output color mode (ARGB8888, RGB888,  RGB565, ARGB1555 or ARGB4444)
+  *         as set by @ref LL_DMA2D_SetOutputColorMode.
+  * @rmtoll OCOLR        BLUE        LL_DMA2D_GetOutputColor\n
+  *         OCOLR        GREEN       LL_DMA2D_GetOutputColor\n
+  *         OCOLR        RED         LL_DMA2D_GetOutputColor\n
+  *         OCOLR        ALPHA       LL_DMA2D_GetOutputColor
+  * @param  DMA2Dx DMA2D Instance
+  * @retval Output color value between Min_Data=0 and Max_Data=0xFFFFFFFF
+  */
+__STATIC_INLINE uint32_t LL_DMA2D_GetOutputColor(DMA2D_TypeDef *DMA2Dx)
+{
+  return (uint32_t)(READ_BIT(DMA2Dx->OCOLR, \
+                             (DMA2D_OCOLR_BLUE_1 | DMA2D_OCOLR_GREEN_1 | DMA2D_OCOLR_RED_1 | DMA2D_OCOLR_ALPHA_1)));
+}
+
+/**
+  * @brief  Set DMA2D line watermark, expressed on 16 bits ([15:0] bits).
+  * @rmtoll LWR          LW          LL_DMA2D_SetLineWatermark
+  * @param  DMA2Dx DMA2D Instance
+  * @param  LineWatermark Value between Min_Data=0 and Max_Data=0xFFFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA2D_SetLineWatermark(DMA2D_TypeDef *DMA2Dx, uint32_t LineWatermark)
+{
+  MODIFY_REG(DMA2Dx->LWR, DMA2D_LWR_LW, LineWatermark);
+}
+
+/**
+  * @brief  Return DMA2D line watermark, expressed on 16 bits ([15:0] bits).
+  * @rmtoll LWR          LW          LL_DMA2D_GetLineWatermark
+  * @param  DMA2Dx DMA2D Instance
+  * @retval Line watermark value between Min_Data=0 and Max_Data=0xFFFF
+  */
+__STATIC_INLINE uint32_t LL_DMA2D_GetLineWatermark(DMA2D_TypeDef *DMA2Dx)
+{
+  return (uint32_t)(READ_BIT(DMA2Dx->LWR, DMA2D_LWR_LW));
+}
+
+/**
+  * @brief  Set DMA2D dead time, expressed on 8 bits ([7:0] bits).
+  * @rmtoll AMTCR          DT          LL_DMA2D_SetDeadTime
+  * @param  DMA2Dx DMA2D Instance
+  * @param  DeadTime Value between Min_Data=0 and Max_Data=0xFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA2D_SetDeadTime(DMA2D_TypeDef *DMA2Dx, uint32_t DeadTime)
+{
+  MODIFY_REG(DMA2Dx->AMTCR, DMA2D_AMTCR_DT, (DeadTime << DMA2D_AMTCR_DT_Pos));
+}
+
+/**
+  * @brief  Return DMA2D dead time, expressed on 8 bits ([7:0] bits).
+  * @rmtoll AMTCR          DT          LL_DMA2D_GetDeadTime
+  * @param  DMA2Dx DMA2D Instance
+  * @retval Dead time value between Min_Data=0 and Max_Data=0xFF
+  */
+__STATIC_INLINE uint32_t LL_DMA2D_GetDeadTime(DMA2D_TypeDef *DMA2Dx)
+{
+  return (uint32_t)(READ_BIT(DMA2Dx->AMTCR, DMA2D_AMTCR_DT) >> DMA2D_AMTCR_DT_Pos);
+}
+
+/**
+  * @brief  Enable DMA2D dead time functionality.
+  * @rmtoll AMTCR          EN            LL_DMA2D_EnableDeadTime
+  * @param  DMA2Dx DMA2D Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA2D_EnableDeadTime(DMA2D_TypeDef *DMA2Dx)
+{
+  SET_BIT(DMA2Dx->AMTCR, DMA2D_AMTCR_EN);
+}
+
+/**
+  * @brief  Disable DMA2D dead time functionality.
+  * @rmtoll AMTCR          EN            LL_DMA2D_DisableDeadTime
+  * @param  DMA2Dx DMA2D Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA2D_DisableDeadTime(DMA2D_TypeDef *DMA2Dx)
+{
+  CLEAR_BIT(DMA2Dx->AMTCR, DMA2D_AMTCR_EN);
+}
+
+/**
+  * @brief  Indicate if DMA2D dead time functionality is enabled.
+  * @rmtoll AMTCR          EN            LL_DMA2D_IsEnabledDeadTime
+  * @param  DMA2Dx DMA2D Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledDeadTime(DMA2D_TypeDef *DMA2Dx)
+{
+  return ((READ_BIT(DMA2Dx->AMTCR, DMA2D_AMTCR_EN) == (DMA2D_AMTCR_EN)) ? 1UL : 0UL);
+}
+
+/** @defgroup DMA2D_LL_EF_FGND_Configuration Foreground Configuration Functions
+  * @{
+  */
+
+/**
+  * @brief  Set DMA2D foreground memory address, expressed on 32 bits ([31:0] bits).
+  * @rmtoll FGMAR          MA          LL_DMA2D_FGND_SetMemAddr
+  * @param  DMA2Dx DMA2D Instance
+  * @param  MemoryAddress Value between Min_Data=0 and Max_Data=0xFFFFFFFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA2D_FGND_SetMemAddr(DMA2D_TypeDef *DMA2Dx, uint32_t MemoryAddress)
+{
+  LL_DMA2D_WriteReg(DMA2Dx, FGMAR, MemoryAddress);
+}
+
+/**
+  * @brief  Get DMA2D foreground memory address, expressed on 32 bits ([31:0] bits).
+  * @rmtoll FGMAR          MA          LL_DMA2D_FGND_GetMemAddr
+  * @param  DMA2Dx DMA2D Instance
+  * @retval Foreground memory address value between Min_Data=0 and Max_Data=0xFFFFFFFF
+  */
+__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetMemAddr(DMA2D_TypeDef *DMA2Dx)
+{
+  return (uint32_t)(LL_DMA2D_ReadReg(DMA2Dx, FGMAR));
+}
+
+/**
+  * @brief  Enable DMA2D foreground CLUT loading.
+  * @rmtoll FGPFCCR          START            LL_DMA2D_FGND_EnableCLUTLoad
+  * @param  DMA2Dx DMA2D Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA2D_FGND_EnableCLUTLoad(DMA2D_TypeDef *DMA2Dx)
+{
+  SET_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_START);
+}
+
+/**
+  * @brief  Indicate if DMA2D foreground CLUT loading is enabled.
+  * @rmtoll FGPFCCR          START            LL_DMA2D_FGND_IsEnabledCLUTLoad
+  * @param  DMA2Dx DMA2D Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA2D_FGND_IsEnabledCLUTLoad(DMA2D_TypeDef *DMA2Dx)
+{
+  return ((READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_START) == (DMA2D_FGPFCCR_START)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Set DMA2D foreground color mode.
+  * @rmtoll FGPFCCR          CM          LL_DMA2D_FGND_SetColorMode
+  * @param  DMA2Dx DMA2D Instance
+  * @param  ColorMode This parameter can be one of the following values:
+  *         @arg @ref LL_DMA2D_INPUT_MODE_ARGB8888
+  *         @arg @ref LL_DMA2D_INPUT_MODE_RGB888
+  *         @arg @ref LL_DMA2D_INPUT_MODE_RGB565
+  *         @arg @ref LL_DMA2D_INPUT_MODE_ARGB1555
+  *         @arg @ref LL_DMA2D_INPUT_MODE_ARGB4444
+  *         @arg @ref LL_DMA2D_INPUT_MODE_L8
+  *         @arg @ref LL_DMA2D_INPUT_MODE_AL44
+  *         @arg @ref LL_DMA2D_INPUT_MODE_AL88
+  *         @arg @ref LL_DMA2D_INPUT_MODE_L4
+  *         @arg @ref LL_DMA2D_INPUT_MODE_A8
+  *         @arg @ref LL_DMA2D_INPUT_MODE_A4
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA2D_FGND_SetColorMode(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode)
+{
+  MODIFY_REG(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CM, ColorMode);
+}
+
+/**
+  * @brief  Return DMA2D foreground color mode.
+  * @rmtoll FGPFCCR          CM         LL_DMA2D_FGND_GetColorMode
+  * @param  DMA2Dx DMA2D Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DMA2D_INPUT_MODE_ARGB8888
+  *         @arg @ref LL_DMA2D_INPUT_MODE_RGB888
+  *         @arg @ref LL_DMA2D_INPUT_MODE_RGB565
+  *         @arg @ref LL_DMA2D_INPUT_MODE_ARGB1555
+  *         @arg @ref LL_DMA2D_INPUT_MODE_ARGB4444
+  *         @arg @ref LL_DMA2D_INPUT_MODE_L8
+  *         @arg @ref LL_DMA2D_INPUT_MODE_AL44
+  *         @arg @ref LL_DMA2D_INPUT_MODE_AL88
+  *         @arg @ref LL_DMA2D_INPUT_MODE_L4
+  *         @arg @ref LL_DMA2D_INPUT_MODE_A8
+  *         @arg @ref LL_DMA2D_INPUT_MODE_A4
+  */
+__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetColorMode(DMA2D_TypeDef *DMA2Dx)
+{
+  return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CM));
+}
+
+/**
+  * @brief  Set DMA2D foreground alpha mode.
+  * @rmtoll FGPFCCR          AM          LL_DMA2D_FGND_SetAlphaMode
+  * @param  DMA2Dx DMA2D Instance
+  * @param  AphaMode This parameter can be one of the following values:
+  *         @arg @ref LL_DMA2D_ALPHA_MODE_NO_MODIF
+  *         @arg @ref LL_DMA2D_ALPHA_MODE_REPLACE
+  *         @arg @ref LL_DMA2D_ALPHA_MODE_COMBINE
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA2D_FGND_SetAlphaMode(DMA2D_TypeDef *DMA2Dx, uint32_t AphaMode)
+{
+  MODIFY_REG(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_AM, AphaMode);
+}
+
+/**
+  * @brief  Return DMA2D foreground alpha mode.
+  * @rmtoll FGPFCCR          AM         LL_DMA2D_FGND_GetAlphaMode
+  * @param  DMA2Dx DMA2D Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DMA2D_ALPHA_MODE_NO_MODIF
+  *         @arg @ref LL_DMA2D_ALPHA_MODE_REPLACE
+  *         @arg @ref LL_DMA2D_ALPHA_MODE_COMBINE
+  */
+__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetAlphaMode(DMA2D_TypeDef *DMA2Dx)
+{
+  return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_AM));
+}
+
+/**
+  * @brief  Set DMA2D foreground alpha value, expressed on 8 bits ([7:0] bits).
+  * @rmtoll FGPFCCR          ALPHA          LL_DMA2D_FGND_SetAlpha
+  * @param  DMA2Dx DMA2D Instance
+  * @param  Alpha Value between Min_Data=0 and Max_Data=0xFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA2D_FGND_SetAlpha(DMA2D_TypeDef *DMA2Dx, uint32_t Alpha)
+{
+  MODIFY_REG(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_ALPHA, (Alpha << DMA2D_FGPFCCR_ALPHA_Pos));
+}
+
+/**
+  * @brief  Return DMA2D foreground alpha value, expressed on 8 bits ([7:0] bits).
+  * @rmtoll FGPFCCR          ALPHA         LL_DMA2D_FGND_GetAlpha
+  * @param  DMA2Dx DMA2D Instance
+  * @retval Alpha value between Min_Data=0 and Max_Data=0xFF
+  */
+__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetAlpha(DMA2D_TypeDef *DMA2Dx)
+{
+  return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_ALPHA) >> DMA2D_FGPFCCR_ALPHA_Pos);
+}
+
+
+/**
+  * @brief  Set DMA2D foreground line offset, expressed on 14 bits ([13:0] bits).
+  * @rmtoll FGOR          LO          LL_DMA2D_FGND_SetLineOffset
+  * @param  DMA2Dx DMA2D Instance
+  * @param  LineOffset Value between Min_Data=0 and Max_Data=0x3FF
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA2D_FGND_SetLineOffset(DMA2D_TypeDef *DMA2Dx, uint32_t LineOffset)
+{
+  MODIFY_REG(DMA2Dx->FGOR, DMA2D_FGOR_LO, LineOffset);
+}
+
+/**
+  * @brief  Return DMA2D foreground line offset, expressed on 14 bits ([13:0] bits).
+  * @rmtoll FGOR          LO         LL_DMA2D_FGND_GetLineOffset
+  * @param  DMA2Dx DMA2D Instance
+  * @retval Foreground line offset value between Min_Data=0 and Max_Data=0x3FF
+  */
+__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetLineOffset(DMA2D_TypeDef *DMA2Dx)
+{
+  return (uint32_t)(READ_BIT(DMA2Dx->FGOR, DMA2D_FGOR_LO));
+}
+
+/**
+  * @brief  Set DMA2D foreground color values, expressed on 24 bits ([23:0] bits).
+  * @rmtoll FGCOLR          RED          LL_DMA2D_FGND_SetColor
+  * @rmtoll FGCOLR          GREEN        LL_DMA2D_FGND_SetColor
+  * @rmtoll FGCOLR          BLUE         LL_DMA2D_FGND_SetColor
+  * @param  DMA2Dx DMA2D Instance
+  * @param  Red   Value between Min_Data=0 and Max_Data=0xFF
+  * @param  Green Value between Min_Data=0 and Max_Data=0xFF
+  * @param  Blue  Value between Min_Data=0 and Max_Data=0xFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA2D_FGND_SetColor(DMA2D_TypeDef *DMA2Dx, uint32_t Red, uint32_t Green, uint32_t Blue)
+{
+  MODIFY_REG(DMA2Dx->FGCOLR, (DMA2D_FGCOLR_RED | DMA2D_FGCOLR_GREEN | DMA2D_FGCOLR_BLUE), \
+             ((Red << DMA2D_FGCOLR_RED_Pos) | (Green << DMA2D_FGCOLR_GREEN_Pos) | Blue));
+}
+
+/**
+  * @brief  Set DMA2D foreground red color value, expressed on 8 bits ([7:0] bits).
+  * @rmtoll FGCOLR          RED          LL_DMA2D_FGND_SetRedColor
+  * @param  DMA2Dx DMA2D Instance
+  * @param  Red Value between Min_Data=0 and Max_Data=0xFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA2D_FGND_SetRedColor(DMA2D_TypeDef *DMA2Dx, uint32_t Red)
+{
+  MODIFY_REG(DMA2Dx->FGCOLR, DMA2D_FGCOLR_RED, (Red << DMA2D_FGCOLR_RED_Pos));
+}
+
+/**
+  * @brief  Return DMA2D foreground red color value, expressed on 8 bits ([7:0] bits).
+  * @rmtoll FGCOLR          RED         LL_DMA2D_FGND_GetRedColor
+  * @param  DMA2Dx DMA2D Instance
+  * @retval Red color value between Min_Data=0 and Max_Data=0xFF
+  */
+__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetRedColor(DMA2D_TypeDef *DMA2Dx)
+{
+  return (uint32_t)(READ_BIT(DMA2Dx->FGCOLR, DMA2D_FGCOLR_RED) >> DMA2D_FGCOLR_RED_Pos);
+}
+
+/**
+  * @brief  Set DMA2D foreground green color value, expressed on 8 bits ([7:0] bits).
+  * @rmtoll FGCOLR          GREEN          LL_DMA2D_FGND_SetGreenColor
+  * @param  DMA2Dx DMA2D Instance
+  * @param  Green Value between Min_Data=0 and Max_Data=0xFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA2D_FGND_SetGreenColor(DMA2D_TypeDef *DMA2Dx, uint32_t Green)
+{
+  MODIFY_REG(DMA2Dx->FGCOLR, DMA2D_FGCOLR_GREEN, (Green << DMA2D_FGCOLR_GREEN_Pos));
+}
+
+/**
+  * @brief  Return DMA2D foreground green color value, expressed on 8 bits ([7:0] bits).
+  * @rmtoll FGCOLR          GREEN         LL_DMA2D_FGND_GetGreenColor
+  * @param  DMA2Dx DMA2D Instance
+  * @retval Green color value between Min_Data=0 and Max_Data=0xFF
+  */
+__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetGreenColor(DMA2D_TypeDef *DMA2Dx)
+{
+  return (uint32_t)(READ_BIT(DMA2Dx->FGCOLR, DMA2D_FGCOLR_GREEN) >> DMA2D_FGCOLR_GREEN_Pos);
+}
+
+/**
+  * @brief  Set DMA2D foreground blue color value, expressed on 8 bits ([7:0] bits).
+  * @rmtoll FGCOLR          BLUE          LL_DMA2D_FGND_SetBlueColor
+  * @param  DMA2Dx DMA2D Instance
+  * @param  Blue Value between Min_Data=0 and Max_Data=0xFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA2D_FGND_SetBlueColor(DMA2D_TypeDef *DMA2Dx, uint32_t Blue)
+{
+  MODIFY_REG(DMA2Dx->FGCOLR, DMA2D_FGCOLR_BLUE, Blue);
+}
+
+/**
+  * @brief  Return DMA2D foreground blue color value, expressed on 8 bits ([7:0] bits).
+  * @rmtoll FGCOLR          BLUE         LL_DMA2D_FGND_GetBlueColor
+  * @param  DMA2Dx DMA2D Instance
+  * @retval Blue color value between Min_Data=0 and Max_Data=0xFF
+  */
+__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetBlueColor(DMA2D_TypeDef *DMA2Dx)
+{
+  return (uint32_t)(READ_BIT(DMA2Dx->FGCOLR, DMA2D_FGCOLR_BLUE));
+}
+
+/**
+  * @brief  Set DMA2D foreground CLUT memory address, expressed on 32 bits ([31:0] bits).
+  * @rmtoll FGCMAR          MA          LL_DMA2D_FGND_SetCLUTMemAddr
+  * @param  DMA2Dx DMA2D Instance
+  * @param  CLUTMemoryAddress Value between Min_Data=0 and Max_Data=0xFFFFFFFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA2D_FGND_SetCLUTMemAddr(DMA2D_TypeDef *DMA2Dx, uint32_t CLUTMemoryAddress)
+{
+  LL_DMA2D_WriteReg(DMA2Dx, FGCMAR, CLUTMemoryAddress);
+}
+
+/**
+  * @brief  Get DMA2D foreground CLUT memory address, expressed on 32 bits ([31:0] bits).
+  * @rmtoll FGCMAR          MA          LL_DMA2D_FGND_GetCLUTMemAddr
+  * @param  DMA2Dx DMA2D Instance
+  * @retval Foreground CLUT memory address value between Min_Data=0 and Max_Data=0xFFFFFFFF
+  */
+__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetCLUTMemAddr(DMA2D_TypeDef *DMA2Dx)
+{
+  return (uint32_t)(LL_DMA2D_ReadReg(DMA2Dx, FGCMAR));
+}
+
+/**
+  * @brief  Set DMA2D foreground CLUT size, expressed on 8 bits ([7:0] bits).
+  * @rmtoll FGPFCCR          CS          LL_DMA2D_FGND_SetCLUTSize
+  * @param  DMA2Dx DMA2D Instance
+  * @param  CLUTSize Value between Min_Data=0 and Max_Data=0xFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA2D_FGND_SetCLUTSize(DMA2D_TypeDef *DMA2Dx, uint32_t CLUTSize)
+{
+  MODIFY_REG(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CS, (CLUTSize << DMA2D_FGPFCCR_CS_Pos));
+}
+
+/**
+  * @brief  Get DMA2D foreground CLUT size, expressed on 8 bits ([7:0] bits).
+  * @rmtoll FGPFCCR          CS          LL_DMA2D_FGND_GetCLUTSize
+  * @param  DMA2Dx DMA2D Instance
+  * @retval Foreground CLUT size value between Min_Data=0 and Max_Data=0xFF
+  */
+__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetCLUTSize(DMA2D_TypeDef *DMA2Dx)
+{
+  return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CS) >> DMA2D_FGPFCCR_CS_Pos);
+}
+
+/**
+  * @brief  Set DMA2D foreground CLUT color mode.
+  * @rmtoll FGPFCCR          CCM          LL_DMA2D_FGND_SetCLUTColorMode
+  * @param  DMA2Dx DMA2D Instance
+  * @param  CLUTColorMode This parameter can be one of the following values:
+  *         @arg @ref LL_DMA2D_CLUT_COLOR_MODE_ARGB8888
+  *         @arg @ref LL_DMA2D_CLUT_COLOR_MODE_RGB888
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA2D_FGND_SetCLUTColorMode(DMA2D_TypeDef *DMA2Dx, uint32_t CLUTColorMode)
+{
+  MODIFY_REG(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CCM, CLUTColorMode);
+}
+
+/**
+  * @brief  Return DMA2D foreground CLUT color mode.
+  * @rmtoll FGPFCCR          CCM         LL_DMA2D_FGND_GetCLUTColorMode
+  * @param  DMA2Dx DMA2D Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DMA2D_CLUT_COLOR_MODE_ARGB8888
+  *         @arg @ref LL_DMA2D_CLUT_COLOR_MODE_RGB888
+  */
+__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetCLUTColorMode(DMA2D_TypeDef *DMA2Dx)
+{
+  return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CCM));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup DMA2D_LL_EF_BGND_Configuration Background Configuration Functions
+  * @{
+  */
+
+/**
+  * @brief  Set DMA2D background memory address, expressed on 32 bits ([31:0] bits).
+  * @rmtoll BGMAR          MA          LL_DMA2D_BGND_SetMemAddr
+  * @param  DMA2Dx DMA2D Instance
+  * @param  MemoryAddress Value between Min_Data=0 and Max_Data=0xFFFFFFFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA2D_BGND_SetMemAddr(DMA2D_TypeDef *DMA2Dx, uint32_t MemoryAddress)
+{
+  LL_DMA2D_WriteReg(DMA2Dx, BGMAR, MemoryAddress);
+}
+
+/**
+  * @brief  Get DMA2D background memory address, expressed on 32 bits ([31:0] bits).
+  * @rmtoll BGMAR          MA          LL_DMA2D_BGND_GetMemAddr
+  * @param  DMA2Dx DMA2D Instance
+  * @retval Background memory address value between Min_Data=0 and Max_Data=0xFFFFFFFF
+  */
+__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetMemAddr(DMA2D_TypeDef *DMA2Dx)
+{
+  return (uint32_t)(LL_DMA2D_ReadReg(DMA2Dx, BGMAR));
+}
+
+/**
+  * @brief  Enable DMA2D background CLUT loading.
+  * @rmtoll BGPFCCR          START            LL_DMA2D_BGND_EnableCLUTLoad
+  * @param  DMA2Dx DMA2D Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA2D_BGND_EnableCLUTLoad(DMA2D_TypeDef *DMA2Dx)
+{
+  SET_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_START);
+}
+
+/**
+  * @brief  Indicate if DMA2D background CLUT loading is enabled.
+  * @rmtoll BGPFCCR          START            LL_DMA2D_BGND_IsEnabledCLUTLoad
+  * @param  DMA2Dx DMA2D Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA2D_BGND_IsEnabledCLUTLoad(DMA2D_TypeDef *DMA2Dx)
+{
+  return ((READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_START) == (DMA2D_BGPFCCR_START)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Set DMA2D background color mode.
+  * @rmtoll BGPFCCR          CM          LL_DMA2D_BGND_SetColorMode
+  * @param  DMA2Dx DMA2D Instance
+  * @param  ColorMode This parameter can be one of the following values:
+  *         @arg @ref LL_DMA2D_INPUT_MODE_ARGB8888
+  *         @arg @ref LL_DMA2D_INPUT_MODE_RGB888
+  *         @arg @ref LL_DMA2D_INPUT_MODE_RGB565
+  *         @arg @ref LL_DMA2D_INPUT_MODE_ARGB1555
+  *         @arg @ref LL_DMA2D_INPUT_MODE_ARGB4444
+  *         @arg @ref LL_DMA2D_INPUT_MODE_L8
+  *         @arg @ref LL_DMA2D_INPUT_MODE_AL44
+  *         @arg @ref LL_DMA2D_INPUT_MODE_AL88
+  *         @arg @ref LL_DMA2D_INPUT_MODE_L4
+  *         @arg @ref LL_DMA2D_INPUT_MODE_A8
+  *         @arg @ref LL_DMA2D_INPUT_MODE_A4
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA2D_BGND_SetColorMode(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode)
+{
+  MODIFY_REG(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_CM, ColorMode);
+}
+
+/**
+  * @brief  Return DMA2D background color mode.
+  * @rmtoll BGPFCCR          CM          LL_DMA2D_BGND_GetColorMode
+  * @param  DMA2Dx DMA2D Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DMA2D_INPUT_MODE_ARGB8888
+  *         @arg @ref LL_DMA2D_INPUT_MODE_RGB888
+  *         @arg @ref LL_DMA2D_INPUT_MODE_RGB565
+  *         @arg @ref LL_DMA2D_INPUT_MODE_ARGB1555
+  *         @arg @ref LL_DMA2D_INPUT_MODE_ARGB4444
+  *         @arg @ref LL_DMA2D_INPUT_MODE_L8
+  *         @arg @ref LL_DMA2D_INPUT_MODE_AL44
+  *         @arg @ref LL_DMA2D_INPUT_MODE_AL88
+  *         @arg @ref LL_DMA2D_INPUT_MODE_L4
+  *         @arg @ref LL_DMA2D_INPUT_MODE_A8
+  *         @arg @ref LL_DMA2D_INPUT_MODE_A4
+  */
+__STATIC_INLINE uint32_t  LL_DMA2D_BGND_GetColorMode(DMA2D_TypeDef *DMA2Dx)
+{
+  return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_CM));
+}
+
+/**
+  * @brief  Set DMA2D background alpha mode.
+  * @rmtoll BGPFCCR          AM         LL_DMA2D_BGND_SetAlphaMode
+  * @param  DMA2Dx DMA2D Instance
+  * @param  AphaMode This parameter can be one of the following values:
+  *         @arg @ref LL_DMA2D_ALPHA_MODE_NO_MODIF
+  *         @arg @ref LL_DMA2D_ALPHA_MODE_REPLACE
+  *         @arg @ref LL_DMA2D_ALPHA_MODE_COMBINE
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA2D_BGND_SetAlphaMode(DMA2D_TypeDef *DMA2Dx, uint32_t AphaMode)
+{
+  MODIFY_REG(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_AM, AphaMode);
+}
+
+/**
+  * @brief  Return DMA2D background alpha mode.
+  * @rmtoll BGPFCCR          AM          LL_DMA2D_BGND_GetAlphaMode
+  * @param  DMA2Dx DMA2D Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DMA2D_ALPHA_MODE_NO_MODIF
+  *         @arg @ref LL_DMA2D_ALPHA_MODE_REPLACE
+  *         @arg @ref LL_DMA2D_ALPHA_MODE_COMBINE
+  */
+__STATIC_INLINE uint32_t  LL_DMA2D_BGND_GetAlphaMode(DMA2D_TypeDef *DMA2Dx)
+{
+  return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_AM));
+}
+
+/**
+  * @brief  Set DMA2D background alpha value, expressed on 8 bits ([7:0] bits).
+  * @rmtoll BGPFCCR          ALPHA         LL_DMA2D_BGND_SetAlpha
+  * @param  DMA2Dx DMA2D Instance
+  * @param  Alpha Value between Min_Data=0 and Max_Data=0xFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA2D_BGND_SetAlpha(DMA2D_TypeDef *DMA2Dx, uint32_t Alpha)
+{
+  MODIFY_REG(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_ALPHA, (Alpha << DMA2D_BGPFCCR_ALPHA_Pos));
+}
+
+/**
+  * @brief  Return DMA2D background alpha value, expressed on 8 bits ([7:0] bits).
+  * @rmtoll BGPFCCR          ALPHA          LL_DMA2D_BGND_GetAlpha
+  * @param  DMA2Dx DMA2D Instance
+  * @retval Alpha value between Min_Data=0 and Max_Data=0xFF
+  */
+__STATIC_INLINE uint32_t  LL_DMA2D_BGND_GetAlpha(DMA2D_TypeDef *DMA2Dx)
+{
+  return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_ALPHA) >> DMA2D_BGPFCCR_ALPHA_Pos);
+}
+
+
+/**
+  * @brief  Set DMA2D background line offset, expressed on 14 bits ([13:0] bits).
+  * @rmtoll BGOR          LO         LL_DMA2D_BGND_SetLineOffset
+  * @param  DMA2Dx DMA2D Instance
+  * @param  LineOffset Value between Min_Data=0 and Max_Data=0x3FF
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA2D_BGND_SetLineOffset(DMA2D_TypeDef *DMA2Dx, uint32_t LineOffset)
+{
+  MODIFY_REG(DMA2Dx->BGOR, DMA2D_BGOR_LO, LineOffset);
+}
+
+/**
+  * @brief  Return DMA2D background line offset, expressed on 14 bits ([13:0] bits).
+  * @rmtoll BGOR          LO          LL_DMA2D_BGND_GetLineOffset
+  * @param  DMA2Dx DMA2D Instance
+  * @retval Background line offset value between Min_Data=0 and Max_Data=0x3FF
+  */
+__STATIC_INLINE uint32_t  LL_DMA2D_BGND_GetLineOffset(DMA2D_TypeDef *DMA2Dx)
+{
+  return (uint32_t)(READ_BIT(DMA2Dx->BGOR, DMA2D_BGOR_LO));
+}
+
+/**
+  * @brief  Set DMA2D background color values, expressed on 24 bits ([23:0] bits).
+  * @rmtoll BGCOLR          RED          LL_DMA2D_BGND_SetColor
+  * @rmtoll BGCOLR          GREEN        LL_DMA2D_BGND_SetColor
+  * @rmtoll BGCOLR          BLUE         LL_DMA2D_BGND_SetColor
+  * @param  DMA2Dx DMA2D Instance
+  * @param  Red   Value between Min_Data=0 and Max_Data=0xFF
+  * @param  Green Value between Min_Data=0 and Max_Data=0xFF
+  * @param  Blue  Value between Min_Data=0 and Max_Data=0xFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA2D_BGND_SetColor(DMA2D_TypeDef *DMA2Dx, uint32_t Red, uint32_t Green, uint32_t Blue)
+{
+  MODIFY_REG(DMA2Dx->BGCOLR, (DMA2D_BGCOLR_RED | DMA2D_BGCOLR_GREEN | DMA2D_BGCOLR_BLUE), \
+             ((Red << DMA2D_BGCOLR_RED_Pos) | (Green << DMA2D_BGCOLR_GREEN_Pos) | Blue));
+}
+
+/**
+  * @brief  Set DMA2D background red color value, expressed on 8 bits ([7:0] bits).
+  * @rmtoll BGCOLR          RED         LL_DMA2D_BGND_SetRedColor
+  * @param  DMA2Dx DMA2D Instance
+  * @param  Red Value between Min_Data=0 and Max_Data=0xFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA2D_BGND_SetRedColor(DMA2D_TypeDef *DMA2Dx, uint32_t Red)
+{
+  MODIFY_REG(DMA2Dx->BGCOLR, DMA2D_BGCOLR_RED, (Red << DMA2D_BGCOLR_RED_Pos));
+}
+
+/**
+  * @brief  Return DMA2D background red color value, expressed on 8 bits ([7:0] bits).
+  * @rmtoll BGCOLR          RED          LL_DMA2D_BGND_GetRedColor
+  * @param  DMA2Dx DMA2D Instance
+  * @retval Red color value between Min_Data=0 and Max_Data=0xFF
+  */
+__STATIC_INLINE uint32_t  LL_DMA2D_BGND_GetRedColor(DMA2D_TypeDef *DMA2Dx)
+{
+  return (uint32_t)(READ_BIT(DMA2Dx->BGCOLR, DMA2D_BGCOLR_RED) >> DMA2D_BGCOLR_RED_Pos);
+}
+
+/**
+  * @brief  Set DMA2D background green color value, expressed on 8 bits ([7:0] bits).
+  * @rmtoll BGCOLR          GREEN         LL_DMA2D_BGND_SetGreenColor
+  * @param  DMA2Dx DMA2D Instance
+  * @param  Green Value between Min_Data=0 and Max_Data=0xFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA2D_BGND_SetGreenColor(DMA2D_TypeDef *DMA2Dx, uint32_t Green)
+{
+  MODIFY_REG(DMA2Dx->BGCOLR, DMA2D_BGCOLR_GREEN, (Green << DMA2D_BGCOLR_GREEN_Pos));
+}
+
+/**
+  * @brief  Return DMA2D background green color value, expressed on 8 bits ([7:0] bits).
+  * @rmtoll BGCOLR          GREEN          LL_DMA2D_BGND_GetGreenColor
+  * @param  DMA2Dx DMA2D Instance
+  * @retval Green color value between Min_Data=0 and Max_Data=0xFF
+  */
+__STATIC_INLINE uint32_t  LL_DMA2D_BGND_GetGreenColor(DMA2D_TypeDef *DMA2Dx)
+{
+  return (uint32_t)(READ_BIT(DMA2Dx->BGCOLR, DMA2D_BGCOLR_GREEN) >> DMA2D_BGCOLR_GREEN_Pos);
+}
+
+/**
+  * @brief  Set DMA2D background blue color value, expressed on 8 bits ([7:0] bits).
+  * @rmtoll BGCOLR          BLUE         LL_DMA2D_BGND_SetBlueColor
+  * @param  DMA2Dx DMA2D Instance
+  * @param  Blue Value between Min_Data=0 and Max_Data=0xFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA2D_BGND_SetBlueColor(DMA2D_TypeDef *DMA2Dx, uint32_t Blue)
+{
+  MODIFY_REG(DMA2Dx->BGCOLR, DMA2D_BGCOLR_BLUE, Blue);
+}
+
+/**
+  * @brief  Return DMA2D background blue color value, expressed on 8 bits ([7:0] bits).
+  * @rmtoll BGCOLR          BLUE          LL_DMA2D_BGND_GetBlueColor
+  * @param  DMA2Dx DMA2D Instance
+  * @retval Blue color value between Min_Data=0 and Max_Data=0xFF
+  */
+__STATIC_INLINE uint32_t  LL_DMA2D_BGND_GetBlueColor(DMA2D_TypeDef *DMA2Dx)
+{
+  return (uint32_t)(READ_BIT(DMA2Dx->BGCOLR, DMA2D_BGCOLR_BLUE));
+}
+
+/**
+  * @brief  Set DMA2D background CLUT memory address, expressed on 32 bits ([31:0] bits).
+  * @rmtoll BGCMAR          MA         LL_DMA2D_BGND_SetCLUTMemAddr
+  * @param  DMA2Dx DMA2D Instance
+  * @param  CLUTMemoryAddress Value between Min_Data=0 and Max_Data=0xFFFFFFFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA2D_BGND_SetCLUTMemAddr(DMA2D_TypeDef *DMA2Dx, uint32_t CLUTMemoryAddress)
+{
+  LL_DMA2D_WriteReg(DMA2Dx, BGCMAR, CLUTMemoryAddress);
+}
+
+/**
+  * @brief  Get DMA2D background CLUT memory address, expressed on 32 bits ([31:0] bits).
+  * @rmtoll BGCMAR          MA           LL_DMA2D_BGND_GetCLUTMemAddr
+  * @param  DMA2Dx DMA2D Instance
+  * @retval Background CLUT memory address value between Min_Data=0 and Max_Data=0xFFFFFFFF
+  */
+__STATIC_INLINE uint32_t  LL_DMA2D_BGND_GetCLUTMemAddr(DMA2D_TypeDef *DMA2Dx)
+{
+  return (uint32_t)(LL_DMA2D_ReadReg(DMA2Dx, BGCMAR));
+}
+
+/**
+  * @brief  Set DMA2D background CLUT size, expressed on 8 bits ([7:0] bits).
+  * @rmtoll BGPFCCR          CS         LL_DMA2D_BGND_SetCLUTSize
+  * @param  DMA2Dx DMA2D Instance
+  * @param  CLUTSize Value between Min_Data=0 and Max_Data=0xFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA2D_BGND_SetCLUTSize(DMA2D_TypeDef *DMA2Dx, uint32_t CLUTSize)
+{
+  MODIFY_REG(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_CS, (CLUTSize << DMA2D_BGPFCCR_CS_Pos));
+}
+
+/**
+  * @brief  Get DMA2D background CLUT size, expressed on 8 bits ([7:0] bits).
+  * @rmtoll BGPFCCR          CS           LL_DMA2D_BGND_GetCLUTSize
+  * @param  DMA2Dx DMA2D Instance
+  * @retval Background CLUT size value between Min_Data=0 and Max_Data=0xFF
+  */
+__STATIC_INLINE uint32_t  LL_DMA2D_BGND_GetCLUTSize(DMA2D_TypeDef *DMA2Dx)
+{
+  return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_CS) >> DMA2D_BGPFCCR_CS_Pos);
+}
+
+/**
+  * @brief  Set DMA2D background CLUT color mode.
+  * @rmtoll BGPFCCR          CCM         LL_DMA2D_BGND_SetCLUTColorMode
+  * @param  DMA2Dx DMA2D Instance
+  * @param  CLUTColorMode This parameter can be one of the following values:
+  *         @arg @ref LL_DMA2D_CLUT_COLOR_MODE_ARGB8888
+  *         @arg @ref LL_DMA2D_CLUT_COLOR_MODE_RGB888
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA2D_BGND_SetCLUTColorMode(DMA2D_TypeDef *DMA2Dx, uint32_t CLUTColorMode)
+{
+  MODIFY_REG(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_CCM, CLUTColorMode);
+}
+
+/**
+  * @brief  Return DMA2D background CLUT color mode.
+  * @rmtoll BGPFCCR          CCM          LL_DMA2D_BGND_GetCLUTColorMode
+  * @param  DMA2Dx DMA2D Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DMA2D_CLUT_COLOR_MODE_ARGB8888
+  *         @arg @ref LL_DMA2D_CLUT_COLOR_MODE_RGB888
+  */
+__STATIC_INLINE uint32_t  LL_DMA2D_BGND_GetCLUTColorMode(DMA2D_TypeDef *DMA2Dx)
+{
+  return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_CCM));
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+
+/** @defgroup DMA2D_LL_EF_FLAG_MANAGEMENT Flag Management
+  * @{
+  */
+
+/**
+  * @brief  Check if the DMA2D Configuration Error Interrupt Flag is set or not
+  * @rmtoll ISR          CEIF            LL_DMA2D_IsActiveFlag_CE
+  * @param  DMA2Dx DMA2D Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_CE(DMA2D_TypeDef *DMA2Dx)
+{
+  return ((READ_BIT(DMA2Dx->ISR, DMA2D_ISR_CEIF) == (DMA2D_ISR_CEIF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the DMA2D CLUT Transfer Complete Interrupt Flag is set or not
+  * @rmtoll ISR          CTCIF            LL_DMA2D_IsActiveFlag_CTC
+  * @param  DMA2Dx DMA2D Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_CTC(DMA2D_TypeDef *DMA2Dx)
+{
+  return ((READ_BIT(DMA2Dx->ISR, DMA2D_ISR_CTCIF) == (DMA2D_ISR_CTCIF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the DMA2D CLUT Access Error Interrupt Flag is set or not
+  * @rmtoll ISR          CAEIF            LL_DMA2D_IsActiveFlag_CAE
+  * @param  DMA2Dx DMA2D Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_CAE(DMA2D_TypeDef *DMA2Dx)
+{
+  return ((READ_BIT(DMA2Dx->ISR, DMA2D_ISR_CAEIF) == (DMA2D_ISR_CAEIF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the DMA2D Transfer Watermark Interrupt Flag is set or not
+  * @rmtoll ISR          TWIF            LL_DMA2D_IsActiveFlag_TW
+  * @param  DMA2Dx DMA2D Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_TW(DMA2D_TypeDef *DMA2Dx)
+{
+  return ((READ_BIT(DMA2Dx->ISR, DMA2D_ISR_TWIF) == (DMA2D_ISR_TWIF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the DMA2D Transfer Complete Interrupt Flag is set or not
+  * @rmtoll ISR          TCIF            LL_DMA2D_IsActiveFlag_TC
+  * @param  DMA2Dx DMA2D Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_TC(DMA2D_TypeDef *DMA2Dx)
+{
+  return ((READ_BIT(DMA2Dx->ISR, DMA2D_ISR_TCIF) == (DMA2D_ISR_TCIF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the DMA2D Transfer Error Interrupt Flag is set or not
+  * @rmtoll ISR          TEIF            LL_DMA2D_IsActiveFlag_TE
+  * @param  DMA2Dx DMA2D Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_TE(DMA2D_TypeDef *DMA2Dx)
+{
+  return ((READ_BIT(DMA2Dx->ISR, DMA2D_ISR_TEIF) == (DMA2D_ISR_TEIF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Clear DMA2D Configuration Error Interrupt Flag
+  * @rmtoll IFCR          CCEIF          LL_DMA2D_ClearFlag_CE
+  * @param  DMA2Dx DMA2D Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA2D_ClearFlag_CE(DMA2D_TypeDef *DMA2Dx)
+{
+  WRITE_REG(DMA2Dx->IFCR, DMA2D_IFCR_CCEIF);
+}
+
+/**
+  * @brief  Clear DMA2D CLUT Transfer Complete Interrupt Flag
+  * @rmtoll IFCR          CCTCIF          LL_DMA2D_ClearFlag_CTC
+  * @param  DMA2Dx DMA2D Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA2D_ClearFlag_CTC(DMA2D_TypeDef *DMA2Dx)
+{
+  WRITE_REG(DMA2Dx->IFCR, DMA2D_IFCR_CCTCIF);
+}
+
+/**
+  * @brief  Clear DMA2D CLUT Access Error Interrupt Flag
+  * @rmtoll IFCR          CAECIF          LL_DMA2D_ClearFlag_CAE
+  * @param  DMA2Dx DMA2D Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA2D_ClearFlag_CAE(DMA2D_TypeDef *DMA2Dx)
+{
+  WRITE_REG(DMA2Dx->IFCR, DMA2D_IFCR_CAECIF);
+}
+
+/**
+  * @brief  Clear DMA2D Transfer Watermark Interrupt Flag
+  * @rmtoll IFCR          CTWIF          LL_DMA2D_ClearFlag_TW
+  * @param  DMA2Dx DMA2D Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA2D_ClearFlag_TW(DMA2D_TypeDef *DMA2Dx)
+{
+  WRITE_REG(DMA2Dx->IFCR, DMA2D_IFCR_CTWIF);
+}
+
+/**
+  * @brief  Clear DMA2D Transfer Complete Interrupt Flag
+  * @rmtoll IFCR          CTCIF          LL_DMA2D_ClearFlag_TC
+  * @param  DMA2Dx DMA2D Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA2D_ClearFlag_TC(DMA2D_TypeDef *DMA2Dx)
+{
+  WRITE_REG(DMA2Dx->IFCR, DMA2D_IFCR_CTCIF);
+}
+
+/**
+  * @brief  Clear DMA2D Transfer Error Interrupt Flag
+  * @rmtoll IFCR          CTEIF          LL_DMA2D_ClearFlag_TE
+  * @param  DMA2Dx DMA2D Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA2D_ClearFlag_TE(DMA2D_TypeDef *DMA2Dx)
+{
+  WRITE_REG(DMA2Dx->IFCR, DMA2D_IFCR_CTEIF);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup DMA2D_LL_EF_IT_MANAGEMENT Interruption Management
+  * @{
+  */
+
+/**
+  * @brief  Enable Configuration Error Interrupt
+  * @rmtoll CR          CEIE        LL_DMA2D_EnableIT_CE
+  * @param  DMA2Dx DMA2D Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA2D_EnableIT_CE(DMA2D_TypeDef *DMA2Dx)
+{
+  SET_BIT(DMA2Dx->CR, DMA2D_CR_CEIE);
+}
+
+/**
+  * @brief  Enable CLUT Transfer Complete Interrupt
+  * @rmtoll CR          CTCIE        LL_DMA2D_EnableIT_CTC
+  * @param  DMA2Dx DMA2D Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA2D_EnableIT_CTC(DMA2D_TypeDef *DMA2Dx)
+{
+  SET_BIT(DMA2Dx->CR, DMA2D_CR_CTCIE);
+}
+
+/**
+  * @brief  Enable CLUT Access Error Interrupt
+  * @rmtoll CR          CAEIE        LL_DMA2D_EnableIT_CAE
+  * @param  DMA2Dx DMA2D Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA2D_EnableIT_CAE(DMA2D_TypeDef *DMA2Dx)
+{
+  SET_BIT(DMA2Dx->CR, DMA2D_CR_CAEIE);
+}
+
+/**
+  * @brief  Enable Transfer Watermark Interrupt
+  * @rmtoll CR          TWIE        LL_DMA2D_EnableIT_TW
+  * @param  DMA2Dx DMA2D Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA2D_EnableIT_TW(DMA2D_TypeDef *DMA2Dx)
+{
+  SET_BIT(DMA2Dx->CR, DMA2D_CR_TWIE);
+}
+
+/**
+  * @brief  Enable Transfer Complete Interrupt
+  * @rmtoll CR          TCIE        LL_DMA2D_EnableIT_TC
+  * @param  DMA2Dx DMA2D Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA2D_EnableIT_TC(DMA2D_TypeDef *DMA2Dx)
+{
+  SET_BIT(DMA2Dx->CR, DMA2D_CR_TCIE);
+}
+
+/**
+  * @brief  Enable Transfer Error Interrupt
+  * @rmtoll CR          TEIE        LL_DMA2D_EnableIT_TE
+  * @param  DMA2Dx DMA2D Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA2D_EnableIT_TE(DMA2D_TypeDef *DMA2Dx)
+{
+  SET_BIT(DMA2Dx->CR, DMA2D_CR_TEIE);
+}
+
+/**
+  * @brief  Disable Configuration Error Interrupt
+  * @rmtoll CR          CEIE        LL_DMA2D_DisableIT_CE
+  * @param  DMA2Dx DMA2D Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA2D_DisableIT_CE(DMA2D_TypeDef *DMA2Dx)
+{
+  CLEAR_BIT(DMA2Dx->CR, DMA2D_CR_CEIE);
+}
+
+/**
+  * @brief  Disable CLUT Transfer Complete Interrupt
+  * @rmtoll CR          CTCIE        LL_DMA2D_DisableIT_CTC
+  * @param  DMA2Dx DMA2D Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA2D_DisableIT_CTC(DMA2D_TypeDef *DMA2Dx)
+{
+  CLEAR_BIT(DMA2Dx->CR, DMA2D_CR_CTCIE);
+}
+
+/**
+  * @brief  Disable CLUT Access Error Interrupt
+  * @rmtoll CR          CAEIE        LL_DMA2D_DisableIT_CAE
+  * @param  DMA2Dx DMA2D Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA2D_DisableIT_CAE(DMA2D_TypeDef *DMA2Dx)
+{
+  CLEAR_BIT(DMA2Dx->CR, DMA2D_CR_CAEIE);
+}
+
+/**
+  * @brief  Disable Transfer Watermark Interrupt
+  * @rmtoll CR          TWIE        LL_DMA2D_DisableIT_TW
+  * @param  DMA2Dx DMA2D Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA2D_DisableIT_TW(DMA2D_TypeDef *DMA2Dx)
+{
+  CLEAR_BIT(DMA2Dx->CR, DMA2D_CR_TWIE);
+}
+
+/**
+  * @brief  Disable Transfer Complete Interrupt
+  * @rmtoll CR          TCIE        LL_DMA2D_DisableIT_TC
+  * @param  DMA2Dx DMA2D Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA2D_DisableIT_TC(DMA2D_TypeDef *DMA2Dx)
+{
+  CLEAR_BIT(DMA2Dx->CR, DMA2D_CR_TCIE);
+}
+
+/**
+  * @brief  Disable Transfer Error Interrupt
+  * @rmtoll CR          TEIE        LL_DMA2D_DisableIT_TE
+  * @param  DMA2Dx DMA2D Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA2D_DisableIT_TE(DMA2D_TypeDef *DMA2Dx)
+{
+  CLEAR_BIT(DMA2Dx->CR, DMA2D_CR_TEIE);
+}
+
+/**
+  * @brief  Check if the DMA2D Configuration Error interrupt source is enabled or disabled.
+  * @rmtoll CR          CEIE        LL_DMA2D_IsEnabledIT_CE
+  * @param  DMA2Dx DMA2D Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_CE(DMA2D_TypeDef *DMA2Dx)
+{
+  return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_CEIE) == (DMA2D_CR_CEIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the DMA2D CLUT Transfer Complete interrupt source is enabled or disabled.
+  * @rmtoll CR          CTCIE        LL_DMA2D_IsEnabledIT_CTC
+  * @param  DMA2Dx DMA2D Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_CTC(DMA2D_TypeDef *DMA2Dx)
+{
+  return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_CTCIE) == (DMA2D_CR_CTCIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the DMA2D CLUT Access Error interrupt source is enabled or disabled.
+  * @rmtoll CR          CAEIE        LL_DMA2D_IsEnabledIT_CAE
+  * @param  DMA2Dx DMA2D Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_CAE(DMA2D_TypeDef *DMA2Dx)
+{
+  return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_CAEIE) == (DMA2D_CR_CAEIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the DMA2D Transfer Watermark interrupt source is enabled or disabled.
+  * @rmtoll CR          TWIE        LL_DMA2D_IsEnabledIT_TW
+  * @param  DMA2Dx DMA2D Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_TW(DMA2D_TypeDef *DMA2Dx)
+{
+  return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_TWIE) == (DMA2D_CR_TWIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the DMA2D Transfer Complete interrupt source is enabled or disabled.
+  * @rmtoll CR          TCIE        LL_DMA2D_IsEnabledIT_TC
+  * @param  DMA2Dx DMA2D Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_TC(DMA2D_TypeDef *DMA2Dx)
+{
+  return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_TCIE) == (DMA2D_CR_TCIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the DMA2D Transfer Error interrupt source is enabled or disabled.
+  * @rmtoll CR          TEIE        LL_DMA2D_IsEnabledIT_TE
+  * @param  DMA2Dx DMA2D Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_TE(DMA2D_TypeDef *DMA2Dx)
+{
+  return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_TEIE) == (DMA2D_CR_TEIE)) ? 1UL : 0UL);
+}
+
+
+
+/**
+  * @}
+  */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup DMA2D_LL_EF_Init_Functions Initialization and De-initialization Functions
+  * @{
+  */
+
+ErrorStatus LL_DMA2D_DeInit(DMA2D_TypeDef *DMA2Dx);
+ErrorStatus LL_DMA2D_Init(DMA2D_TypeDef *DMA2Dx, LL_DMA2D_InitTypeDef *DMA2D_InitStruct);
+void LL_DMA2D_StructInit(LL_DMA2D_InitTypeDef *DMA2D_InitStruct);
+void LL_DMA2D_ConfigLayer(DMA2D_TypeDef *DMA2Dx, LL_DMA2D_LayerCfgTypeDef *DMA2D_LayerCfg, uint32_t LayerIdx);
+void LL_DMA2D_LayerCfgStructInit(LL_DMA2D_LayerCfgTypeDef *DMA2D_LayerCfg);
+void LL_DMA2D_ConfigOutputColor(DMA2D_TypeDef *DMA2Dx, LL_DMA2D_ColorTypeDef *DMA2D_ColorStruct);
+uint32_t LL_DMA2D_GetOutputBlueColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode);
+uint32_t LL_DMA2D_GetOutputGreenColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode);
+uint32_t LL_DMA2D_GetOutputRedColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode);
+uint32_t LL_DMA2D_GetOutputAlphaColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode);
+void LL_DMA2D_ConfigSize(DMA2D_TypeDef *DMA2Dx, uint32_t NbrOfLines, uint32_t NbrOfPixelsPerLines);
+
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* defined (DMA2D) */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32F4xx_LL_DMA2D_H */
diff --git a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_exti.h b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_exti.h
new file mode 100644
index 0000000..bef8894
--- /dev/null
+++ b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_exti.h
@@ -0,0 +1,954 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_ll_exti.h
+  * @author  MCD Application Team
+  * @brief   Header file of EXTI LL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2016 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_LL_EXTI_H
+#define __STM32F4xx_LL_EXTI_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx.h"
+
+/** @addtogroup STM32F4xx_LL_Driver
+  * @{
+  */
+
+#if defined (EXTI)
+
+/** @defgroup EXTI_LL EXTI
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private Macros ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup EXTI_LL_Private_Macros EXTI Private Macros
+  * @{
+  */
+/**
+  * @}
+  */
+#endif /*USE_FULL_LL_DRIVER*/
+/* Exported types ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup EXTI_LL_ES_INIT EXTI Exported Init structure
+  * @{
+  */
+typedef struct
+{
+
+  uint32_t Line_0_31;           /*!< Specifies the EXTI lines to be enabled or disabled for Lines in range 0 to 31
+                                     This parameter can be any combination of @ref EXTI_LL_EC_LINE */
+
+  FunctionalState LineCommand;  /*!< Specifies the new state of the selected EXTI lines.
+                                     This parameter can be set either to ENABLE or DISABLE */
+
+  uint8_t Mode;                 /*!< Specifies the mode for the EXTI lines.
+                                     This parameter can be a value of @ref EXTI_LL_EC_MODE. */
+
+  uint8_t Trigger;              /*!< Specifies the trigger signal active edge for the EXTI lines.
+                                     This parameter can be a value of @ref EXTI_LL_EC_TRIGGER. */
+} LL_EXTI_InitTypeDef;
+
+/**
+  * @}
+  */
+#endif /*USE_FULL_LL_DRIVER*/
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup EXTI_LL_Exported_Constants EXTI Exported Constants
+  * @{
+  */
+
+/** @defgroup EXTI_LL_EC_LINE LINE
+  * @{
+  */
+#define LL_EXTI_LINE_0                 EXTI_IMR_IM0           /*!< Extended line 0 */
+#define LL_EXTI_LINE_1                 EXTI_IMR_IM1           /*!< Extended line 1 */
+#define LL_EXTI_LINE_2                 EXTI_IMR_IM2           /*!< Extended line 2 */
+#define LL_EXTI_LINE_3                 EXTI_IMR_IM3           /*!< Extended line 3 */
+#define LL_EXTI_LINE_4                 EXTI_IMR_IM4           /*!< Extended line 4 */
+#define LL_EXTI_LINE_5                 EXTI_IMR_IM5           /*!< Extended line 5 */
+#define LL_EXTI_LINE_6                 EXTI_IMR_IM6           /*!< Extended line 6 */
+#define LL_EXTI_LINE_7                 EXTI_IMR_IM7           /*!< Extended line 7 */
+#define LL_EXTI_LINE_8                 EXTI_IMR_IM8           /*!< Extended line 8 */
+#define LL_EXTI_LINE_9                 EXTI_IMR_IM9           /*!< Extended line 9 */
+#define LL_EXTI_LINE_10                EXTI_IMR_IM10          /*!< Extended line 10 */
+#define LL_EXTI_LINE_11                EXTI_IMR_IM11          /*!< Extended line 11 */
+#define LL_EXTI_LINE_12                EXTI_IMR_IM12          /*!< Extended line 12 */
+#define LL_EXTI_LINE_13                EXTI_IMR_IM13          /*!< Extended line 13 */
+#define LL_EXTI_LINE_14                EXTI_IMR_IM14          /*!< Extended line 14 */
+#define LL_EXTI_LINE_15                EXTI_IMR_IM15          /*!< Extended line 15 */
+#if defined(EXTI_IMR_IM16)
+#define LL_EXTI_LINE_16                EXTI_IMR_IM16          /*!< Extended line 16 */
+#endif
+#define LL_EXTI_LINE_17                EXTI_IMR_IM17          /*!< Extended line 17 */
+#if defined(EXTI_IMR_IM18)
+#define LL_EXTI_LINE_18                EXTI_IMR_IM18          /*!< Extended line 18 */
+#endif
+#define LL_EXTI_LINE_19                EXTI_IMR_IM19          /*!< Extended line 19 */
+#if defined(EXTI_IMR_IM20)
+#define LL_EXTI_LINE_20                EXTI_IMR_IM20          /*!< Extended line 20 */
+#endif
+#if defined(EXTI_IMR_IM21)
+#define LL_EXTI_LINE_21                EXTI_IMR_IM21          /*!< Extended line 21 */
+#endif
+#if defined(EXTI_IMR_IM22)
+#define LL_EXTI_LINE_22                EXTI_IMR_IM22          /*!< Extended line 22 */
+#endif
+#if defined(EXTI_IMR_IM23)
+#define LL_EXTI_LINE_23                EXTI_IMR_IM23          /*!< Extended line 23 */
+#endif
+#if defined(EXTI_IMR_IM24)
+#define LL_EXTI_LINE_24                EXTI_IMR_IM24          /*!< Extended line 24 */
+#endif
+#if defined(EXTI_IMR_IM25)
+#define LL_EXTI_LINE_25                EXTI_IMR_IM25          /*!< Extended line 25 */
+#endif
+#if defined(EXTI_IMR_IM26)
+#define LL_EXTI_LINE_26                EXTI_IMR_IM26          /*!< Extended line 26 */
+#endif
+#if defined(EXTI_IMR_IM27)
+#define LL_EXTI_LINE_27                EXTI_IMR_IM27          /*!< Extended line 27 */
+#endif
+#if defined(EXTI_IMR_IM28)
+#define LL_EXTI_LINE_28                EXTI_IMR_IM28          /*!< Extended line 28 */
+#endif
+#if defined(EXTI_IMR_IM29)
+#define LL_EXTI_LINE_29                EXTI_IMR_IM29          /*!< Extended line 29 */
+#endif
+#if defined(EXTI_IMR_IM30)
+#define LL_EXTI_LINE_30                EXTI_IMR_IM30          /*!< Extended line 30 */
+#endif
+#if defined(EXTI_IMR_IM31)
+#define LL_EXTI_LINE_31                EXTI_IMR_IM31          /*!< Extended line 31 */
+#endif
+#define LL_EXTI_LINE_ALL_0_31          EXTI_IMR_IM            /*!< All Extended line not reserved*/
+
+
+#define LL_EXTI_LINE_ALL               ((uint32_t)0xFFFFFFFFU)  /*!< All Extended line */
+
+#if defined(USE_FULL_LL_DRIVER)
+#define LL_EXTI_LINE_NONE              ((uint32_t)0x00000000U)  /*!< None Extended line */
+#endif /*USE_FULL_LL_DRIVER*/
+
+/**
+  * @}
+  */
+#if defined(USE_FULL_LL_DRIVER)
+
+/** @defgroup EXTI_LL_EC_MODE Mode
+  * @{
+  */
+#define LL_EXTI_MODE_IT                 ((uint8_t)0x00U) /*!< Interrupt Mode */
+#define LL_EXTI_MODE_EVENT              ((uint8_t)0x01U) /*!< Event Mode */
+#define LL_EXTI_MODE_IT_EVENT           ((uint8_t)0x02U) /*!< Interrupt & Event Mode */
+/**
+  * @}
+  */
+
+/** @defgroup EXTI_LL_EC_TRIGGER Edge Trigger
+  * @{
+  */
+#define LL_EXTI_TRIGGER_NONE            ((uint8_t)0x00U) /*!< No Trigger Mode */
+#define LL_EXTI_TRIGGER_RISING          ((uint8_t)0x01U) /*!< Trigger Rising Mode */
+#define LL_EXTI_TRIGGER_FALLING         ((uint8_t)0x02U) /*!< Trigger Falling Mode */
+#define LL_EXTI_TRIGGER_RISING_FALLING  ((uint8_t)0x03U) /*!< Trigger Rising & Falling Mode */
+
+/**
+  * @}
+  */
+
+
+#endif /*USE_FULL_LL_DRIVER*/
+
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup EXTI_LL_Exported_Macros EXTI Exported Macros
+  * @{
+  */
+
+/** @defgroup EXTI_LL_EM_WRITE_READ Common Write and read registers Macros
+  * @{
+  */
+
+/**
+  * @brief  Write a value in EXTI register
+  * @param  __REG__ Register to be written
+  * @param  __VALUE__ Value to be written in the register
+  * @retval None
+  */
+#define LL_EXTI_WriteReg(__REG__, __VALUE__) WRITE_REG(EXTI->__REG__, (__VALUE__))
+
+/**
+  * @brief  Read a value in EXTI register
+  * @param  __REG__ Register to be read
+  * @retval Register value
+  */
+#define LL_EXTI_ReadReg(__REG__) READ_REG(EXTI->__REG__)
+/**
+  * @}
+  */
+
+
+/**
+  * @}
+  */
+
+
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup EXTI_LL_Exported_Functions EXTI Exported Functions
+ * @{
+ */
+/** @defgroup EXTI_LL_EF_IT_Management IT_Management
+  * @{
+  */
+
+/**
+  * @brief  Enable ExtiLine Interrupt request for Lines in range 0 to 31
+  * @note The reset value for the direct or internal lines (see RM)
+  *       is set to 1 in order to enable the interrupt by default.
+  *       Bits are set automatically at Power on.
+  * @rmtoll IMR         IMx           LL_EXTI_EnableIT_0_31
+  * @param  ExtiLine This parameter can be one of the following values:
+  *         @arg @ref LL_EXTI_LINE_0
+  *         @arg @ref LL_EXTI_LINE_1
+  *         @arg @ref LL_EXTI_LINE_2
+  *         @arg @ref LL_EXTI_LINE_3
+  *         @arg @ref LL_EXTI_LINE_4
+  *         @arg @ref LL_EXTI_LINE_5
+  *         @arg @ref LL_EXTI_LINE_6
+  *         @arg @ref LL_EXTI_LINE_7
+  *         @arg @ref LL_EXTI_LINE_8
+  *         @arg @ref LL_EXTI_LINE_9
+  *         @arg @ref LL_EXTI_LINE_10
+  *         @arg @ref LL_EXTI_LINE_11
+  *         @arg @ref LL_EXTI_LINE_12
+  *         @arg @ref LL_EXTI_LINE_13
+  *         @arg @ref LL_EXTI_LINE_14
+  *         @arg @ref LL_EXTI_LINE_15
+  *         @arg @ref LL_EXTI_LINE_16
+  *         @arg @ref LL_EXTI_LINE_17
+  *         @arg @ref LL_EXTI_LINE_18
+  *         @arg @ref LL_EXTI_LINE_19(*)
+  *         @arg @ref LL_EXTI_LINE_20(*)
+  *         @arg @ref LL_EXTI_LINE_21
+  *         @arg @ref LL_EXTI_LINE_22
+  *         @arg @ref LL_EXTI_LINE_23(*)
+  *         @arg @ref LL_EXTI_LINE_ALL_0_31
+  * @note   (*): Available in some devices
+  * @note   Please check each device line mapping for EXTI Line availability
+  * @retval None
+  */
+__STATIC_INLINE void LL_EXTI_EnableIT_0_31(uint32_t ExtiLine)
+{
+  SET_BIT(EXTI->IMR, ExtiLine);
+}
+
+/**
+  * @brief  Disable ExtiLine Interrupt request for Lines in range 0 to 31
+  * @note The reset value for the direct or internal lines (see RM)
+  *       is set to 1 in order to enable the interrupt by default.
+  *       Bits are set automatically at Power on.
+  * @rmtoll IMR         IMx           LL_EXTI_DisableIT_0_31
+  * @param  ExtiLine This parameter can be one of the following values:
+  *         @arg @ref LL_EXTI_LINE_0
+  *         @arg @ref LL_EXTI_LINE_1
+  *         @arg @ref LL_EXTI_LINE_2
+  *         @arg @ref LL_EXTI_LINE_3
+  *         @arg @ref LL_EXTI_LINE_4
+  *         @arg @ref LL_EXTI_LINE_5
+  *         @arg @ref LL_EXTI_LINE_6
+  *         @arg @ref LL_EXTI_LINE_7
+  *         @arg @ref LL_EXTI_LINE_8
+  *         @arg @ref LL_EXTI_LINE_9
+  *         @arg @ref LL_EXTI_LINE_10
+  *         @arg @ref LL_EXTI_LINE_11
+  *         @arg @ref LL_EXTI_LINE_12
+  *         @arg @ref LL_EXTI_LINE_13
+  *         @arg @ref LL_EXTI_LINE_14
+  *         @arg @ref LL_EXTI_LINE_15
+  *         @arg @ref LL_EXTI_LINE_16
+  *         @arg @ref LL_EXTI_LINE_17
+  *         @arg @ref LL_EXTI_LINE_18
+  *         @arg @ref LL_EXTI_LINE_19(*)
+  *         @arg @ref LL_EXTI_LINE_20(*)
+  *         @arg @ref LL_EXTI_LINE_21
+  *         @arg @ref LL_EXTI_LINE_22
+  *         @arg @ref LL_EXTI_LINE_23(*)
+  *         @arg @ref LL_EXTI_LINE_ALL_0_31
+  * @note   (*): Available in some devices
+  * @note   Please check each device line mapping for EXTI Line availability
+  * @retval None
+  */
+__STATIC_INLINE void LL_EXTI_DisableIT_0_31(uint32_t ExtiLine)
+{
+  CLEAR_BIT(EXTI->IMR, ExtiLine);
+}
+
+
+/**
+  * @brief  Indicate if ExtiLine Interrupt request is enabled for Lines in range 0 to 31
+  * @note The reset value for the direct or internal lines (see RM)
+  *       is set to 1 in order to enable the interrupt by default.
+  *       Bits are set automatically at Power on.
+  * @rmtoll IMR         IMx           LL_EXTI_IsEnabledIT_0_31
+  * @param  ExtiLine This parameter can be one of the following values:
+  *         @arg @ref LL_EXTI_LINE_0
+  *         @arg @ref LL_EXTI_LINE_1
+  *         @arg @ref LL_EXTI_LINE_2
+  *         @arg @ref LL_EXTI_LINE_3
+  *         @arg @ref LL_EXTI_LINE_4
+  *         @arg @ref LL_EXTI_LINE_5
+  *         @arg @ref LL_EXTI_LINE_6
+  *         @arg @ref LL_EXTI_LINE_7
+  *         @arg @ref LL_EXTI_LINE_8
+  *         @arg @ref LL_EXTI_LINE_9
+  *         @arg @ref LL_EXTI_LINE_10
+  *         @arg @ref LL_EXTI_LINE_11
+  *         @arg @ref LL_EXTI_LINE_12
+  *         @arg @ref LL_EXTI_LINE_13
+  *         @arg @ref LL_EXTI_LINE_14
+  *         @arg @ref LL_EXTI_LINE_15
+  *         @arg @ref LL_EXTI_LINE_16
+  *         @arg @ref LL_EXTI_LINE_17
+  *         @arg @ref LL_EXTI_LINE_18
+  *         @arg @ref LL_EXTI_LINE_19(*)
+  *         @arg @ref LL_EXTI_LINE_20(*)
+  *         @arg @ref LL_EXTI_LINE_21
+  *         @arg @ref LL_EXTI_LINE_22
+  *         @arg @ref LL_EXTI_LINE_23(*)
+  *         @arg @ref LL_EXTI_LINE_ALL_0_31
+  * @note   (*): Available in some devices
+  * @note   Please check each device line mapping for EXTI Line availability
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_EXTI_IsEnabledIT_0_31(uint32_t ExtiLine)
+{
+  return (READ_BIT(EXTI->IMR, ExtiLine) == (ExtiLine));
+}
+
+
+/**
+  * @}
+  */
+
+/** @defgroup EXTI_LL_EF_Event_Management Event_Management
+  * @{
+  */
+
+/**
+  * @brief  Enable ExtiLine Event request for Lines in range 0 to 31
+  * @rmtoll EMR         EMx           LL_EXTI_EnableEvent_0_31
+  * @param  ExtiLine This parameter can be one of the following values:
+  *         @arg @ref LL_EXTI_LINE_0
+  *         @arg @ref LL_EXTI_LINE_1
+  *         @arg @ref LL_EXTI_LINE_2
+  *         @arg @ref LL_EXTI_LINE_3
+  *         @arg @ref LL_EXTI_LINE_4
+  *         @arg @ref LL_EXTI_LINE_5
+  *         @arg @ref LL_EXTI_LINE_6
+  *         @arg @ref LL_EXTI_LINE_7
+  *         @arg @ref LL_EXTI_LINE_8
+  *         @arg @ref LL_EXTI_LINE_9
+  *         @arg @ref LL_EXTI_LINE_10
+  *         @arg @ref LL_EXTI_LINE_11
+  *         @arg @ref LL_EXTI_LINE_12
+  *         @arg @ref LL_EXTI_LINE_13
+  *         @arg @ref LL_EXTI_LINE_14
+  *         @arg @ref LL_EXTI_LINE_15
+  *         @arg @ref LL_EXTI_LINE_16
+  *         @arg @ref LL_EXTI_LINE_17
+  *         @arg @ref LL_EXTI_LINE_18
+  *         @arg @ref LL_EXTI_LINE_19(*)
+  *         @arg @ref LL_EXTI_LINE_20(*)
+  *         @arg @ref LL_EXTI_LINE_21
+  *         @arg @ref LL_EXTI_LINE_22
+  *         @arg @ref LL_EXTI_LINE_23(*)
+  *         @arg @ref LL_EXTI_LINE_ALL_0_31
+  * @note   (*): Available in some devices
+  * @note   Please check each device line mapping for EXTI Line availability
+  * @retval None
+  */
+__STATIC_INLINE void LL_EXTI_EnableEvent_0_31(uint32_t ExtiLine)
+{
+  SET_BIT(EXTI->EMR, ExtiLine);
+
+}
+
+
+/**
+  * @brief  Disable ExtiLine Event request for Lines in range 0 to 31
+  * @rmtoll EMR         EMx           LL_EXTI_DisableEvent_0_31
+  * @param  ExtiLine This parameter can be one of the following values:
+  *         @arg @ref LL_EXTI_LINE_0
+  *         @arg @ref LL_EXTI_LINE_1
+  *         @arg @ref LL_EXTI_LINE_2
+  *         @arg @ref LL_EXTI_LINE_3
+  *         @arg @ref LL_EXTI_LINE_4
+  *         @arg @ref LL_EXTI_LINE_5
+  *         @arg @ref LL_EXTI_LINE_6
+  *         @arg @ref LL_EXTI_LINE_7
+  *         @arg @ref LL_EXTI_LINE_8
+  *         @arg @ref LL_EXTI_LINE_9
+  *         @arg @ref LL_EXTI_LINE_10
+  *         @arg @ref LL_EXTI_LINE_11
+  *         @arg @ref LL_EXTI_LINE_12
+  *         @arg @ref LL_EXTI_LINE_13
+  *         @arg @ref LL_EXTI_LINE_14
+  *         @arg @ref LL_EXTI_LINE_15
+  *         @arg @ref LL_EXTI_LINE_16
+  *         @arg @ref LL_EXTI_LINE_17
+  *         @arg @ref LL_EXTI_LINE_18
+  *         @arg @ref LL_EXTI_LINE_19(*)
+  *         @arg @ref LL_EXTI_LINE_20(*)
+  *         @arg @ref LL_EXTI_LINE_21
+  *         @arg @ref LL_EXTI_LINE_22
+  *         @arg @ref LL_EXTI_LINE_23(*)
+  *         @arg @ref LL_EXTI_LINE_ALL_0_31
+  * @note   (*): Available in some devices
+  * @note   Please check each device line mapping for EXTI Line availability
+  * @retval None
+  */
+__STATIC_INLINE void LL_EXTI_DisableEvent_0_31(uint32_t ExtiLine)
+{
+  CLEAR_BIT(EXTI->EMR, ExtiLine);
+}
+
+
+/**
+  * @brief  Indicate if ExtiLine Event request is enabled for Lines in range 0 to 31
+  * @rmtoll EMR         EMx           LL_EXTI_IsEnabledEvent_0_31
+  * @param  ExtiLine This parameter can be one of the following values:
+  *         @arg @ref LL_EXTI_LINE_0
+  *         @arg @ref LL_EXTI_LINE_1
+  *         @arg @ref LL_EXTI_LINE_2
+  *         @arg @ref LL_EXTI_LINE_3
+  *         @arg @ref LL_EXTI_LINE_4
+  *         @arg @ref LL_EXTI_LINE_5
+  *         @arg @ref LL_EXTI_LINE_6
+  *         @arg @ref LL_EXTI_LINE_7
+  *         @arg @ref LL_EXTI_LINE_8
+  *         @arg @ref LL_EXTI_LINE_9
+  *         @arg @ref LL_EXTI_LINE_10
+  *         @arg @ref LL_EXTI_LINE_11
+  *         @arg @ref LL_EXTI_LINE_12
+  *         @arg @ref LL_EXTI_LINE_13
+  *         @arg @ref LL_EXTI_LINE_14
+  *         @arg @ref LL_EXTI_LINE_15
+  *         @arg @ref LL_EXTI_LINE_16
+  *         @arg @ref LL_EXTI_LINE_17
+  *         @arg @ref LL_EXTI_LINE_18
+  *         @arg @ref LL_EXTI_LINE_19(*)
+  *         @arg @ref LL_EXTI_LINE_20(*)
+  *         @arg @ref LL_EXTI_LINE_21
+  *         @arg @ref LL_EXTI_LINE_22
+  *         @arg @ref LL_EXTI_LINE_23(*)
+  *         @arg @ref LL_EXTI_LINE_ALL_0_31
+  * @note   (*): Available in some devices
+  * @note   Please check each device line mapping for EXTI Line availability
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_EXTI_IsEnabledEvent_0_31(uint32_t ExtiLine)
+{
+  return (READ_BIT(EXTI->EMR, ExtiLine) == (ExtiLine));
+
+}
+
+
+/**
+  * @}
+  */
+
+/** @defgroup EXTI_LL_EF_Rising_Trigger_Management Rising_Trigger_Management
+  * @{
+  */
+
+/**
+  * @brief  Enable ExtiLine Rising Edge Trigger for Lines in range 0 to 31
+  * @note The configurable wakeup lines are edge-triggered. No glitch must be
+  *       generated on these lines. If a rising edge on a configurable interrupt
+  *       line occurs during a write operation in the EXTI_RTSR register, the
+  *       pending bit is not set.
+  *       Rising and falling edge triggers can be set for
+  *       the same interrupt line. In this case, both generate a trigger
+  *       condition.
+  * @rmtoll RTSR        RTx           LL_EXTI_EnableRisingTrig_0_31
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_0
+  *         @arg @ref LL_EXTI_LINE_1
+  *         @arg @ref LL_EXTI_LINE_2
+  *         @arg @ref LL_EXTI_LINE_3
+  *         @arg @ref LL_EXTI_LINE_4
+  *         @arg @ref LL_EXTI_LINE_5
+  *         @arg @ref LL_EXTI_LINE_6
+  *         @arg @ref LL_EXTI_LINE_7
+  *         @arg @ref LL_EXTI_LINE_8
+  *         @arg @ref LL_EXTI_LINE_9
+  *         @arg @ref LL_EXTI_LINE_10
+  *         @arg @ref LL_EXTI_LINE_11
+  *         @arg @ref LL_EXTI_LINE_12
+  *         @arg @ref LL_EXTI_LINE_13
+  *         @arg @ref LL_EXTI_LINE_14
+  *         @arg @ref LL_EXTI_LINE_15
+  *         @arg @ref LL_EXTI_LINE_16
+  *         @arg @ref LL_EXTI_LINE_18
+  *         @arg @ref LL_EXTI_LINE_19(*)
+  *         @arg @ref LL_EXTI_LINE_20(*)
+  *         @arg @ref LL_EXTI_LINE_21
+  *         @arg @ref LL_EXTI_LINE_22
+  * @note   (*): Available in some devices
+  * @note   Please check each device line mapping for EXTI Line availability
+  * @retval None
+  */
+__STATIC_INLINE void LL_EXTI_EnableRisingTrig_0_31(uint32_t ExtiLine)
+{
+  SET_BIT(EXTI->RTSR, ExtiLine);
+
+}
+
+
+/**
+  * @brief  Disable ExtiLine Rising Edge Trigger for Lines in range 0 to 31
+  * @note The configurable wakeup lines are edge-triggered. No glitch must be
+  *       generated on these lines. If a rising edge on a configurable interrupt
+  *       line occurs during a write operation in the EXTI_RTSR register, the
+  *       pending bit is not set.
+  *       Rising and falling edge triggers can be set for
+  *       the same interrupt line. In this case, both generate a trigger
+  *       condition.
+  * @rmtoll RTSR        RTx           LL_EXTI_DisableRisingTrig_0_31
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_0
+  *         @arg @ref LL_EXTI_LINE_1
+  *         @arg @ref LL_EXTI_LINE_2
+  *         @arg @ref LL_EXTI_LINE_3
+  *         @arg @ref LL_EXTI_LINE_4
+  *         @arg @ref LL_EXTI_LINE_5
+  *         @arg @ref LL_EXTI_LINE_6
+  *         @arg @ref LL_EXTI_LINE_7
+  *         @arg @ref LL_EXTI_LINE_8
+  *         @arg @ref LL_EXTI_LINE_9
+  *         @arg @ref LL_EXTI_LINE_10
+  *         @arg @ref LL_EXTI_LINE_11
+  *         @arg @ref LL_EXTI_LINE_12
+  *         @arg @ref LL_EXTI_LINE_13
+  *         @arg @ref LL_EXTI_LINE_14
+  *         @arg @ref LL_EXTI_LINE_15
+  *         @arg @ref LL_EXTI_LINE_16
+  *         @arg @ref LL_EXTI_LINE_18
+  *         @arg @ref LL_EXTI_LINE_19(*)
+  *         @arg @ref LL_EXTI_LINE_20(*)
+  *         @arg @ref LL_EXTI_LINE_21
+  *         @arg @ref LL_EXTI_LINE_22
+  * @note   (*): Available in some devices
+  * @note   Please check each device line mapping for EXTI Line availability
+  * @retval None
+  */
+__STATIC_INLINE void LL_EXTI_DisableRisingTrig_0_31(uint32_t ExtiLine)
+{
+  CLEAR_BIT(EXTI->RTSR, ExtiLine);
+
+}
+
+
+/**
+  * @brief  Check if rising edge trigger is enabled for Lines in range 0 to 31
+  * @rmtoll RTSR        RTx           LL_EXTI_IsEnabledRisingTrig_0_31
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_0
+  *         @arg @ref LL_EXTI_LINE_1
+  *         @arg @ref LL_EXTI_LINE_2
+  *         @arg @ref LL_EXTI_LINE_3
+  *         @arg @ref LL_EXTI_LINE_4
+  *         @arg @ref LL_EXTI_LINE_5
+  *         @arg @ref LL_EXTI_LINE_6
+  *         @arg @ref LL_EXTI_LINE_7
+  *         @arg @ref LL_EXTI_LINE_8
+  *         @arg @ref LL_EXTI_LINE_9
+  *         @arg @ref LL_EXTI_LINE_10
+  *         @arg @ref LL_EXTI_LINE_11
+  *         @arg @ref LL_EXTI_LINE_12
+  *         @arg @ref LL_EXTI_LINE_13
+  *         @arg @ref LL_EXTI_LINE_14
+  *         @arg @ref LL_EXTI_LINE_15
+  *         @arg @ref LL_EXTI_LINE_16
+  *         @arg @ref LL_EXTI_LINE_18
+  *         @arg @ref LL_EXTI_LINE_19(*)
+  *         @arg @ref LL_EXTI_LINE_20(*)
+  *         @arg @ref LL_EXTI_LINE_21
+  *         @arg @ref LL_EXTI_LINE_22
+  * @note   (*): Available in some devices
+  * @note   Please check each device line mapping for EXTI Line availability
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_EXTI_IsEnabledRisingTrig_0_31(uint32_t ExtiLine)
+{
+  return (READ_BIT(EXTI->RTSR, ExtiLine) == (ExtiLine));
+}
+
+
+/**
+  * @}
+  */
+
+/** @defgroup EXTI_LL_EF_Falling_Trigger_Management Falling_Trigger_Management
+  * @{
+  */
+
+/**
+  * @brief  Enable ExtiLine Falling Edge Trigger for Lines in range 0 to 31
+  * @note The configurable wakeup lines are edge-triggered. No glitch must be
+  *       generated on these lines. If a falling edge on a configurable interrupt
+  *       line occurs during a write operation in the EXTI_FTSR register, the
+  *       pending bit is not set.
+  *       Rising and falling edge triggers can be set for
+  *       the same interrupt line. In this case, both generate a trigger
+  *       condition.
+  * @rmtoll FTSR        FTx           LL_EXTI_EnableFallingTrig_0_31
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_0
+  *         @arg @ref LL_EXTI_LINE_1
+  *         @arg @ref LL_EXTI_LINE_2
+  *         @arg @ref LL_EXTI_LINE_3
+  *         @arg @ref LL_EXTI_LINE_4
+  *         @arg @ref LL_EXTI_LINE_5
+  *         @arg @ref LL_EXTI_LINE_6
+  *         @arg @ref LL_EXTI_LINE_7
+  *         @arg @ref LL_EXTI_LINE_8
+  *         @arg @ref LL_EXTI_LINE_9
+  *         @arg @ref LL_EXTI_LINE_10
+  *         @arg @ref LL_EXTI_LINE_11
+  *         @arg @ref LL_EXTI_LINE_12
+  *         @arg @ref LL_EXTI_LINE_13
+  *         @arg @ref LL_EXTI_LINE_14
+  *         @arg @ref LL_EXTI_LINE_15
+  *         @arg @ref LL_EXTI_LINE_16
+  *         @arg @ref LL_EXTI_LINE_18
+  *         @arg @ref LL_EXTI_LINE_19(*)
+  *         @arg @ref LL_EXTI_LINE_20(*)
+  *         @arg @ref LL_EXTI_LINE_21
+  *         @arg @ref LL_EXTI_LINE_22
+  * @note   (*): Available in some devices
+  * @note   Please check each device line mapping for EXTI Line availability
+  * @retval None
+  */
+__STATIC_INLINE void LL_EXTI_EnableFallingTrig_0_31(uint32_t ExtiLine)
+{
+  SET_BIT(EXTI->FTSR, ExtiLine);
+}
+
+
+/**
+  * @brief  Disable ExtiLine Falling Edge Trigger for Lines in range 0 to 31
+  * @note The configurable wakeup lines are edge-triggered. No glitch must be
+  *       generated on these lines. If a Falling edge on a configurable interrupt
+  *       line occurs during a write operation in the EXTI_FTSR register, the
+  *       pending bit is not set.
+  *       Rising and falling edge triggers can be set for the same interrupt line.
+  *       In this case, both generate a trigger condition.
+  * @rmtoll FTSR        FTx           LL_EXTI_DisableFallingTrig_0_31
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_0
+  *         @arg @ref LL_EXTI_LINE_1
+  *         @arg @ref LL_EXTI_LINE_2
+  *         @arg @ref LL_EXTI_LINE_3
+  *         @arg @ref LL_EXTI_LINE_4
+  *         @arg @ref LL_EXTI_LINE_5
+  *         @arg @ref LL_EXTI_LINE_6
+  *         @arg @ref LL_EXTI_LINE_7
+  *         @arg @ref LL_EXTI_LINE_8
+  *         @arg @ref LL_EXTI_LINE_9
+  *         @arg @ref LL_EXTI_LINE_10
+  *         @arg @ref LL_EXTI_LINE_11
+  *         @arg @ref LL_EXTI_LINE_12
+  *         @arg @ref LL_EXTI_LINE_13
+  *         @arg @ref LL_EXTI_LINE_14
+  *         @arg @ref LL_EXTI_LINE_15
+  *         @arg @ref LL_EXTI_LINE_16
+  *         @arg @ref LL_EXTI_LINE_18
+  *         @arg @ref LL_EXTI_LINE_19(*)
+  *         @arg @ref LL_EXTI_LINE_20(*)
+  *         @arg @ref LL_EXTI_LINE_21
+  *         @arg @ref LL_EXTI_LINE_22
+  * @note   (*): Available in some devices
+  * @note   Please check each device line mapping for EXTI Line availability
+  * @retval None
+  */
+__STATIC_INLINE void LL_EXTI_DisableFallingTrig_0_31(uint32_t ExtiLine)
+{
+  CLEAR_BIT(EXTI->FTSR, ExtiLine);
+}
+
+
+/**
+  * @brief  Check if falling edge trigger is enabled for Lines in range 0 to 31
+  * @rmtoll FTSR        FTx           LL_EXTI_IsEnabledFallingTrig_0_31
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_0
+  *         @arg @ref LL_EXTI_LINE_1
+  *         @arg @ref LL_EXTI_LINE_2
+  *         @arg @ref LL_EXTI_LINE_3
+  *         @arg @ref LL_EXTI_LINE_4
+  *         @arg @ref LL_EXTI_LINE_5
+  *         @arg @ref LL_EXTI_LINE_6
+  *         @arg @ref LL_EXTI_LINE_7
+  *         @arg @ref LL_EXTI_LINE_8
+  *         @arg @ref LL_EXTI_LINE_9
+  *         @arg @ref LL_EXTI_LINE_10
+  *         @arg @ref LL_EXTI_LINE_11
+  *         @arg @ref LL_EXTI_LINE_12
+  *         @arg @ref LL_EXTI_LINE_13
+  *         @arg @ref LL_EXTI_LINE_14
+  *         @arg @ref LL_EXTI_LINE_15
+  *         @arg @ref LL_EXTI_LINE_16
+  *         @arg @ref LL_EXTI_LINE_18
+  *         @arg @ref LL_EXTI_LINE_19(*)
+  *         @arg @ref LL_EXTI_LINE_20(*)
+  *         @arg @ref LL_EXTI_LINE_21
+  *         @arg @ref LL_EXTI_LINE_22
+  * @note   (*): Available in some devices
+  * @note   Please check each device line mapping for EXTI Line availability
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_EXTI_IsEnabledFallingTrig_0_31(uint32_t ExtiLine)
+{
+  return (READ_BIT(EXTI->FTSR, ExtiLine) == (ExtiLine));
+}
+
+
+/**
+  * @}
+  */
+
+/** @defgroup EXTI_LL_EF_Software_Interrupt_Management Software_Interrupt_Management
+  * @{
+  */
+
+/**
+  * @brief  Generate a software Interrupt Event for Lines in range 0 to 31
+  * @note If the interrupt is enabled on this line in the EXTI_IMR, writing a 1 to
+  *       this bit when it is at '0' sets the corresponding pending bit in EXTI_PR
+  *       resulting in an interrupt request generation.
+  *       This bit is cleared by clearing the corresponding bit in the EXTI_PR
+  *       register (by writing a 1 into the bit)
+  * @rmtoll SWIER       SWIx          LL_EXTI_GenerateSWI_0_31
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_0
+  *         @arg @ref LL_EXTI_LINE_1
+  *         @arg @ref LL_EXTI_LINE_2
+  *         @arg @ref LL_EXTI_LINE_3
+  *         @arg @ref LL_EXTI_LINE_4
+  *         @arg @ref LL_EXTI_LINE_5
+  *         @arg @ref LL_EXTI_LINE_6
+  *         @arg @ref LL_EXTI_LINE_7
+  *         @arg @ref LL_EXTI_LINE_8
+  *         @arg @ref LL_EXTI_LINE_9
+  *         @arg @ref LL_EXTI_LINE_10
+  *         @arg @ref LL_EXTI_LINE_11
+  *         @arg @ref LL_EXTI_LINE_12
+  *         @arg @ref LL_EXTI_LINE_13
+  *         @arg @ref LL_EXTI_LINE_14
+  *         @arg @ref LL_EXTI_LINE_15
+  *         @arg @ref LL_EXTI_LINE_16
+  *         @arg @ref LL_EXTI_LINE_18
+  *         @arg @ref LL_EXTI_LINE_19(*)
+  *         @arg @ref LL_EXTI_LINE_20(*)
+  *         @arg @ref LL_EXTI_LINE_21
+  *         @arg @ref LL_EXTI_LINE_22
+  * @note   (*): Available in some devices
+  * @note   Please check each device line mapping for EXTI Line availability
+  * @retval None
+  */
+__STATIC_INLINE void LL_EXTI_GenerateSWI_0_31(uint32_t ExtiLine)
+{
+  SET_BIT(EXTI->SWIER, ExtiLine);
+}
+
+
+/**
+  * @}
+  */
+
+/** @defgroup EXTI_LL_EF_Flag_Management Flag_Management
+  * @{
+  */
+
+/**
+  * @brief  Check if the ExtLine Flag is set or not for Lines in range 0 to 31
+  * @note This bit is set when the selected edge event arrives on the interrupt
+  *       line. This bit is cleared by writing a 1 to the bit.
+  * @rmtoll PR          PIFx           LL_EXTI_IsActiveFlag_0_31
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_0
+  *         @arg @ref LL_EXTI_LINE_1
+  *         @arg @ref LL_EXTI_LINE_2
+  *         @arg @ref LL_EXTI_LINE_3
+  *         @arg @ref LL_EXTI_LINE_4
+  *         @arg @ref LL_EXTI_LINE_5
+  *         @arg @ref LL_EXTI_LINE_6
+  *         @arg @ref LL_EXTI_LINE_7
+  *         @arg @ref LL_EXTI_LINE_8
+  *         @arg @ref LL_EXTI_LINE_9
+  *         @arg @ref LL_EXTI_LINE_10
+  *         @arg @ref LL_EXTI_LINE_11
+  *         @arg @ref LL_EXTI_LINE_12
+  *         @arg @ref LL_EXTI_LINE_13
+  *         @arg @ref LL_EXTI_LINE_14
+  *         @arg @ref LL_EXTI_LINE_15
+  *         @arg @ref LL_EXTI_LINE_16
+  *         @arg @ref LL_EXTI_LINE_18
+  *         @arg @ref LL_EXTI_LINE_19(*)
+  *         @arg @ref LL_EXTI_LINE_20(*)
+  *         @arg @ref LL_EXTI_LINE_21
+  *         @arg @ref LL_EXTI_LINE_22
+  * @note   (*): Available in some devices
+  * @note   Please check each device line mapping for EXTI Line availability
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_EXTI_IsActiveFlag_0_31(uint32_t ExtiLine)
+{
+  return (READ_BIT(EXTI->PR, ExtiLine) == (ExtiLine));
+}
+
+
+/**
+  * @brief  Read ExtLine Combination Flag for Lines in range 0 to 31
+  * @note This bit is set when the selected edge event arrives on the interrupt
+  *       line. This bit is cleared by writing a 1 to the bit.
+  * @rmtoll PR          PIFx           LL_EXTI_ReadFlag_0_31
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_0
+  *         @arg @ref LL_EXTI_LINE_1
+  *         @arg @ref LL_EXTI_LINE_2
+  *         @arg @ref LL_EXTI_LINE_3
+  *         @arg @ref LL_EXTI_LINE_4
+  *         @arg @ref LL_EXTI_LINE_5
+  *         @arg @ref LL_EXTI_LINE_6
+  *         @arg @ref LL_EXTI_LINE_7
+  *         @arg @ref LL_EXTI_LINE_8
+  *         @arg @ref LL_EXTI_LINE_9
+  *         @arg @ref LL_EXTI_LINE_10
+  *         @arg @ref LL_EXTI_LINE_11
+  *         @arg @ref LL_EXTI_LINE_12
+  *         @arg @ref LL_EXTI_LINE_13
+  *         @arg @ref LL_EXTI_LINE_14
+  *         @arg @ref LL_EXTI_LINE_15
+  *         @arg @ref LL_EXTI_LINE_16
+  *         @arg @ref LL_EXTI_LINE_18
+  *         @arg @ref LL_EXTI_LINE_19(*)
+  *         @arg @ref LL_EXTI_LINE_20(*)
+  *         @arg @ref LL_EXTI_LINE_21
+  *         @arg @ref LL_EXTI_LINE_22
+  * @note   (*): Available in some devices
+  * @note   Please check each device line mapping for EXTI Line availability
+  * @retval @note This bit is set when the selected edge event arrives on the interrupt
+  */
+__STATIC_INLINE uint32_t LL_EXTI_ReadFlag_0_31(uint32_t ExtiLine)
+{
+  return (uint32_t)(READ_BIT(EXTI->PR, ExtiLine));
+}
+
+
+/**
+  * @brief  Clear ExtLine Flags  for Lines in range 0 to 31
+  * @note This bit is set when the selected edge event arrives on the interrupt
+  *       line. This bit is cleared by writing a 1 to the bit.
+  * @rmtoll PR          PIFx           LL_EXTI_ClearFlag_0_31
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_0
+  *         @arg @ref LL_EXTI_LINE_1
+  *         @arg @ref LL_EXTI_LINE_2
+  *         @arg @ref LL_EXTI_LINE_3
+  *         @arg @ref LL_EXTI_LINE_4
+  *         @arg @ref LL_EXTI_LINE_5
+  *         @arg @ref LL_EXTI_LINE_6
+  *         @arg @ref LL_EXTI_LINE_7
+  *         @arg @ref LL_EXTI_LINE_8
+  *         @arg @ref LL_EXTI_LINE_9
+  *         @arg @ref LL_EXTI_LINE_10
+  *         @arg @ref LL_EXTI_LINE_11
+  *         @arg @ref LL_EXTI_LINE_12
+  *         @arg @ref LL_EXTI_LINE_13
+  *         @arg @ref LL_EXTI_LINE_14
+  *         @arg @ref LL_EXTI_LINE_15
+  *         @arg @ref LL_EXTI_LINE_16
+  *         @arg @ref LL_EXTI_LINE_18
+  *         @arg @ref LL_EXTI_LINE_19(*)
+  *         @arg @ref LL_EXTI_LINE_20(*)
+  *         @arg @ref LL_EXTI_LINE_21
+  *         @arg @ref LL_EXTI_LINE_22
+  * @note   (*): Available in some devices
+  * @note   Please check each device line mapping for EXTI Line availability
+  * @retval None
+  */
+__STATIC_INLINE void LL_EXTI_ClearFlag_0_31(uint32_t ExtiLine)
+{
+  WRITE_REG(EXTI->PR, ExtiLine);
+}
+
+
+/**
+  * @}
+  */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup EXTI_LL_EF_Init Initialization and de-initialization functions
+  * @{
+  */
+
+uint32_t LL_EXTI_Init(LL_EXTI_InitTypeDef *EXTI_InitStruct);
+uint32_t LL_EXTI_DeInit(void);
+void LL_EXTI_StructInit(LL_EXTI_InitTypeDef *EXTI_InitStruct);
+
+
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* EXTI */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_LL_EXTI_H */
+
diff --git a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_fmc.h b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_fmc.h
new file mode 100644
index 0000000..d95990d
--- /dev/null
+++ b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_fmc.h
@@ -0,0 +1,1416 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_ll_fmc.h
+  * @author  MCD Application Team
+  * @brief   Header file of FMC HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2016 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32F4xx_LL_FMC_H
+#define STM32F4xx_LL_FMC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup FMC_LL
+  * @{
+  */
+
+/** @addtogroup FMC_LL_Private_Macros
+  * @{
+  */
+#if defined(FMC_Bank1)
+
+#define IS_FMC_NORSRAM_BANK(__BANK__) (((__BANK__) == FMC_NORSRAM_BANK1) || \
+                                       ((__BANK__) == FMC_NORSRAM_BANK2) || \
+                                       ((__BANK__) == FMC_NORSRAM_BANK3) || \
+                                       ((__BANK__) == FMC_NORSRAM_BANK4))
+#define IS_FMC_MUX(__MUX__) (((__MUX__) == FMC_DATA_ADDRESS_MUX_DISABLE) || \
+                             ((__MUX__) == FMC_DATA_ADDRESS_MUX_ENABLE))
+#define IS_FMC_MEMORY(__MEMORY__) (((__MEMORY__) == FMC_MEMORY_TYPE_SRAM) || \
+                                   ((__MEMORY__) == FMC_MEMORY_TYPE_PSRAM)|| \
+                                   ((__MEMORY__) == FMC_MEMORY_TYPE_NOR))
+#define IS_FMC_NORSRAM_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_8)  || \
+                                                ((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_16) || \
+                                                ((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_32))
+#define IS_FMC_PAGESIZE(__SIZE__) (((__SIZE__) == FMC_PAGE_SIZE_NONE) || \
+                                   ((__SIZE__) == FMC_PAGE_SIZE_128) || \
+                                   ((__SIZE__) == FMC_PAGE_SIZE_256) || \
+                                   ((__SIZE__) == FMC_PAGE_SIZE_512) || \
+                                   ((__SIZE__) == FMC_PAGE_SIZE_1024))
+#if defined(FMC_BCR1_WFDIS)
+#define IS_FMC_WRITE_FIFO(__FIFO__) (((__FIFO__) == FMC_WRITE_FIFO_DISABLE) || \
+                                     ((__FIFO__) == FMC_WRITE_FIFO_ENABLE))
+#endif /* FMC_BCR1_WFDIS */
+#define IS_FMC_ACCESS_MODE(__MODE__) (((__MODE__) == FMC_ACCESS_MODE_A) || \
+                                      ((__MODE__) == FMC_ACCESS_MODE_B) || \
+                                      ((__MODE__) == FMC_ACCESS_MODE_C) || \
+                                      ((__MODE__) == FMC_ACCESS_MODE_D))
+#define IS_FMC_BURSTMODE(__STATE__) (((__STATE__) == FMC_BURST_ACCESS_MODE_DISABLE) || \
+                                     ((__STATE__) == FMC_BURST_ACCESS_MODE_ENABLE))
+#define IS_FMC_WAIT_POLARITY(__POLARITY__) (((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_LOW) || \
+                                            ((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_HIGH))
+#define IS_FMC_WRAP_MODE(__MODE__) (((__MODE__) == FMC_WRAP_MODE_DISABLE) || \
+                                             ((__MODE__) == FMC_WRAP_MODE_ENABLE))
+#define IS_FMC_WAIT_SIGNAL_ACTIVE(__ACTIVE__) (((__ACTIVE__) == FMC_WAIT_TIMING_BEFORE_WS) || \
+                                               ((__ACTIVE__) == FMC_WAIT_TIMING_DURING_WS))
+#define IS_FMC_WRITE_OPERATION(__OPERATION__) (((__OPERATION__) == FMC_WRITE_OPERATION_DISABLE) || \
+                                               ((__OPERATION__) == FMC_WRITE_OPERATION_ENABLE))
+#define IS_FMC_WAITE_SIGNAL(__SIGNAL__) (((__SIGNAL__) == FMC_WAIT_SIGNAL_DISABLE) || \
+                                         ((__SIGNAL__) == FMC_WAIT_SIGNAL_ENABLE))
+#define IS_FMC_EXTENDED_MODE(__MODE__) (((__MODE__) == FMC_EXTENDED_MODE_DISABLE) || \
+                                        ((__MODE__) == FMC_EXTENDED_MODE_ENABLE))
+#define IS_FMC_ASYNWAIT(__STATE__) (((__STATE__) == FMC_ASYNCHRONOUS_WAIT_DISABLE) || \
+                                    ((__STATE__) == FMC_ASYNCHRONOUS_WAIT_ENABLE))
+#define IS_FMC_DATA_LATENCY(__LATENCY__) (((__LATENCY__) > 1U) && ((__LATENCY__) <= 17U))
+#define IS_FMC_WRITE_BURST(__BURST__) (((__BURST__) == FMC_WRITE_BURST_DISABLE) || \
+                                       ((__BURST__) == FMC_WRITE_BURST_ENABLE))
+#define IS_FMC_CONTINOUS_CLOCK(__CCLOCK__) (((__CCLOCK__) == FMC_CONTINUOUS_CLOCK_SYNC_ONLY) || \
+                                            ((__CCLOCK__) == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC))
+#define IS_FMC_ADDRESS_SETUP_TIME(__TIME__) ((__TIME__) <= 15U)
+#define IS_FMC_ADDRESS_HOLD_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 15U))
+#define IS_FMC_DATASETUP_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 255U))
+#define IS_FMC_DATAHOLD_DURATION(__DATAHOLD__) ((__DATAHOLD__) <= 3U)
+#define IS_FMC_TURNAROUND_TIME(__TIME__) ((__TIME__) <= 15U)
+#define IS_FMC_CLK_DIV(__DIV__) (((__DIV__) > 1U) && ((__DIV__) <= 16U))
+#define IS_FMC_NORSRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NORSRAM_DEVICE)
+#define IS_FMC_NORSRAM_EXTENDED_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NORSRAM_EXTENDED_DEVICE)
+
+#endif /* FMC_Bank1 */
+#if  (defined(FMC_Bank3) || defined(FMC_Bank2_3))
+
+#if defined(FMC_Bank2_3)
+#define IS_FMC_NAND_BANK(__BANK__) (((__BANK__) == FMC_NAND_BANK2) || \
+                                            ((__BANK__) == FMC_NAND_BANK3))
+#else
+#define IS_FMC_NAND_BANK(__BANK__) ((__BANK__) == FMC_NAND_BANK3)
+#endif /* FMC_Bank2_3 */                                            
+#define IS_FMC_WAIT_FEATURE(__FEATURE__) (((__FEATURE__) == FMC_NAND_PCC_WAIT_FEATURE_DISABLE) || \
+                                                   ((__FEATURE__) == FMC_NAND_PCC_WAIT_FEATURE_ENABLE))
+#define IS_FMC_NAND_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FMC_NAND_PCC_MEM_BUS_WIDTH_8) || \
+                                                      ((__WIDTH__) == FMC_NAND_PCC_MEM_BUS_WIDTH_16))
+#define IS_FMC_ECC_STATE(__STATE__) (((__STATE__) == FMC_NAND_ECC_DISABLE) || \
+                                     ((__STATE__) == FMC_NAND_ECC_ENABLE))
+
+#define IS_FMC_ECCPAGE_SIZE(__SIZE__) (((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_256BYTE)  || \
+                                       ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_512BYTE)  || \
+                                       ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_1024BYTE) || \
+                                       ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_2048BYTE) || \
+                                       ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_4096BYTE) || \
+                                       ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_8192BYTE))
+#define IS_FMC_TCLR_TIME(__TIME__) ((__TIME__) <= 255U)
+#define IS_FMC_TAR_TIME(__TIME__) ((__TIME__) <= 255U)
+#define IS_FMC_SETUP_TIME(__TIME__) ((__TIME__) <= 254U)
+#define IS_FMC_WAIT_TIME(__TIME__) ((__TIME__) <= 254U)
+#define IS_FMC_HOLD_TIME(__TIME__) ((__TIME__) <= 254U)
+#define IS_FMC_HIZ_TIME(__TIME__) ((__TIME__) <= 254U)
+#define IS_FMC_NAND_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NAND_DEVICE)
+
+#endif /* FMC_Bank3) || defined(FMC_Bank2_3 */
+#if defined(FMC_Bank4)
+#define IS_FMC_PCCARD_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_PCCARD_DEVICE)
+
+#endif /* FMC_Bank4 */
+#if defined(FMC_Bank5_6)
+
+#define IS_FMC_SDMEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FMC_SDRAM_MEM_BUS_WIDTH_8)  || \
+                                          ((__WIDTH__) == FMC_SDRAM_MEM_BUS_WIDTH_16) || \
+                                          ((__WIDTH__) == FMC_SDRAM_MEM_BUS_WIDTH_32))
+#define IS_FMC_WRITE_PROTECTION(__WRITE__) (((__WRITE__) == FMC_SDRAM_WRITE_PROTECTION_DISABLE) || \
+                                            ((__WRITE__) == FMC_SDRAM_WRITE_PROTECTION_ENABLE))
+#define IS_FMC_SDCLOCK_PERIOD(__PERIOD__) (((__PERIOD__) == FMC_SDRAM_CLOCK_DISABLE)  || \
+                                           ((__PERIOD__) == FMC_SDRAM_CLOCK_PERIOD_2) || \
+                                           ((__PERIOD__) == FMC_SDRAM_CLOCK_PERIOD_3))
+#define IS_FMC_READ_BURST(__RBURST__) (((__RBURST__) == FMC_SDRAM_RBURST_DISABLE) || \
+                                       ((__RBURST__) == FMC_SDRAM_RBURST_ENABLE))
+#define IS_FMC_READPIPE_DELAY(__DELAY__) (((__DELAY__) == FMC_SDRAM_RPIPE_DELAY_0) || \
+                                          ((__DELAY__) == FMC_SDRAM_RPIPE_DELAY_1) || \
+                                          ((__DELAY__) == FMC_SDRAM_RPIPE_DELAY_2))
+#define IS_FMC_COMMAND_MODE(__COMMAND__) (((__COMMAND__) == FMC_SDRAM_CMD_NORMAL_MODE)      || \
+                                          ((__COMMAND__) == FMC_SDRAM_CMD_CLK_ENABLE)       || \
+                                          ((__COMMAND__) == FMC_SDRAM_CMD_PALL)             || \
+                                          ((__COMMAND__) == FMC_SDRAM_CMD_AUTOREFRESH_MODE) || \
+                                          ((__COMMAND__) == FMC_SDRAM_CMD_LOAD_MODE)        || \
+                                          ((__COMMAND__) == FMC_SDRAM_CMD_SELFREFRESH_MODE) || \
+                                          ((__COMMAND__) == FMC_SDRAM_CMD_POWERDOWN_MODE))
+#define IS_FMC_COMMAND_TARGET(__TARGET__) (((__TARGET__) == FMC_SDRAM_CMD_TARGET_BANK1) || \
+                                           ((__TARGET__) == FMC_SDRAM_CMD_TARGET_BANK2) || \
+                                           ((__TARGET__) == FMC_SDRAM_CMD_TARGET_BANK1_2))
+#define IS_FMC_LOADTOACTIVE_DELAY(__DELAY__) (((__DELAY__) > 0U) && ((__DELAY__) <= 16U))
+#define IS_FMC_EXITSELFREFRESH_DELAY(__DELAY__) (((__DELAY__) > 0U) && ((__DELAY__) <= 16U))
+#define IS_FMC_SELFREFRESH_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 16U))
+#define IS_FMC_ROWCYCLE_DELAY(__DELAY__) (((__DELAY__) > 0U) && ((__DELAY__) <= 16U))
+#define IS_FMC_WRITE_RECOVERY_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 16U))
+#define IS_FMC_RP_DELAY(__DELAY__) (((__DELAY__) > 0U) && ((__DELAY__) <= 16U))
+#define IS_FMC_RCD_DELAY(__DELAY__) (((__DELAY__) > 0U) && ((__DELAY__) <= 16U))
+#define IS_FMC_AUTOREFRESH_NUMBER(__NUMBER__) (((__NUMBER__) > 0U) && ((__NUMBER__) <= 15U))
+#define IS_FMC_MODE_REGISTER(__CONTENT__) ((__CONTENT__) <= 8191U)
+#define IS_FMC_REFRESH_RATE(__RATE__) ((__RATE__) <= 8191U)
+#define IS_FMC_SDRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_SDRAM_DEVICE)
+#define IS_FMC_SDRAM_BANK(__BANK__) (((__BANK__) == FMC_SDRAM_BANK1) || \
+                                     ((__BANK__) == FMC_SDRAM_BANK2))
+#define IS_FMC_COLUMNBITS_NUMBER(__COLUMN__) (((__COLUMN__) == FMC_SDRAM_COLUMN_BITS_NUM_8)  || \
+                                              ((__COLUMN__) == FMC_SDRAM_COLUMN_BITS_NUM_9)  || \
+                                              ((__COLUMN__) == FMC_SDRAM_COLUMN_BITS_NUM_10) || \
+                                              ((__COLUMN__) == FMC_SDRAM_COLUMN_BITS_NUM_11))
+#define IS_FMC_ROWBITS_NUMBER(__ROW__) (((__ROW__) == FMC_SDRAM_ROW_BITS_NUM_11) || \
+                                        ((__ROW__) == FMC_SDRAM_ROW_BITS_NUM_12) || \
+                                        ((__ROW__) == FMC_SDRAM_ROW_BITS_NUM_13))
+#define IS_FMC_INTERNALBANK_NUMBER(__NUMBER__) (((__NUMBER__) == FMC_SDRAM_INTERN_BANKS_NUM_2) || \
+                                                ((__NUMBER__) == FMC_SDRAM_INTERN_BANKS_NUM_4))
+#define IS_FMC_CAS_LATENCY(__LATENCY__) (((__LATENCY__) == FMC_SDRAM_CAS_LATENCY_1) || \
+                                         ((__LATENCY__) == FMC_SDRAM_CAS_LATENCY_2) || \
+                                         ((__LATENCY__) == FMC_SDRAM_CAS_LATENCY_3))
+
+#endif /* FMC_Bank5_6 */
+
+/**
+  * @}
+  */
+
+/* Exported typedef ----------------------------------------------------------*/
+
+/** @defgroup FMC_LL_Exported_typedef FMC Low Layer Exported Types
+  * @{
+  */
+
+#if defined(FMC_Bank1)
+#define FMC_NORSRAM_TypeDef            FMC_Bank1_TypeDef
+#define FMC_NORSRAM_EXTENDED_TypeDef   FMC_Bank1E_TypeDef
+#endif /* FMC_Bank1 */
+#if defined(FMC_Bank2_3)
+#define FMC_NAND_TypeDef               FMC_Bank2_3_TypeDef
+#else
+#define FMC_NAND_TypeDef               FMC_Bank3_TypeDef
+#endif /* FMC_Bank2_3 */
+#if defined(FMC_Bank4)
+#define FMC_PCCARD_TypeDef             FMC_Bank4_TypeDef
+#endif /* FMC_Bank4 */
+#if defined(FMC_Bank5_6)
+#define FMC_SDRAM_TypeDef              FMC_Bank5_6_TypeDef
+#endif /* FMC_Bank5_6 */
+
+#if defined(FMC_Bank1)
+#define FMC_NORSRAM_DEVICE             FMC_Bank1
+#define FMC_NORSRAM_EXTENDED_DEVICE    FMC_Bank1E
+#endif /* FMC_Bank1 */
+#if defined(FMC_Bank2_3)
+#define FMC_NAND_DEVICE                FMC_Bank2_3
+#else
+#define FMC_NAND_DEVICE                FMC_Bank3
+#endif /* FMC_Bank2_3 */
+#if defined(FMC_Bank4)
+#define FMC_PCCARD_DEVICE              FMC_Bank4
+#endif /* FMC_Bank4 */
+#if defined(FMC_Bank5_6)
+#define FMC_SDRAM_DEVICE               FMC_Bank5_6
+#endif /* FMC_Bank5_6 */
+
+#if defined(FMC_Bank1)
+/**
+  * @brief  FMC NORSRAM Configuration Structure definition
+  */
+typedef struct
+{
+  uint32_t NSBank;                       /*!< Specifies the NORSRAM memory device that will be used.
+                                              This parameter can be a value of @ref FMC_NORSRAM_Bank                  */
+
+  uint32_t DataAddressMux;               /*!< Specifies whether the address and data values are
+                                              multiplexed on the data bus or not.
+                                              This parameter can be a value of @ref FMC_Data_Address_Bus_Multiplexing */
+
+  uint32_t MemoryType;                   /*!< Specifies the type of external memory attached to
+                                              the corresponding memory device.
+                                              This parameter can be a value of @ref FMC_Memory_Type                   */
+
+  uint32_t MemoryDataWidth;              /*!< Specifies the external memory device width.
+                                              This parameter can be a value of @ref FMC_NORSRAM_Data_Width            */
+
+  uint32_t BurstAccessMode;              /*!< Enables or disables the burst access mode for Flash memory,
+                                              valid only with synchronous burst Flash memories.
+                                              This parameter can be a value of @ref FMC_Burst_Access_Mode             */
+
+  uint32_t WaitSignalPolarity;           /*!< Specifies the wait signal polarity, valid only when accessing
+                                              the Flash memory in burst mode.
+                                              This parameter can be a value of @ref FMC_Wait_Signal_Polarity          */
+
+  uint32_t WrapMode;                     /*!< Enables or disables the Wrapped burst access mode for Flash
+                                              memory, valid only when accessing Flash memories in burst mode.
+                                              This parameter can be a value of @ref FMC_Wrap_Mode
+                                              This mode is not available for the STM32F446/467/479xx devices          */
+
+  uint32_t WaitSignalActive;             /*!< Specifies if the wait signal is asserted by the memory one
+                                              clock cycle before the wait state or during the wait state,
+                                              valid only when accessing memories in burst mode.
+                                              This parameter can be a value of @ref FMC_Wait_Timing                   */
+
+  uint32_t WriteOperation;               /*!< Enables or disables the write operation in the selected device by the FMC.
+                                              This parameter can be a value of @ref FMC_Write_Operation               */
+
+  uint32_t WaitSignal;                   /*!< Enables or disables the wait state insertion via wait
+                                              signal, valid for Flash memory access in burst mode.
+                                              This parameter can be a value of @ref FMC_Wait_Signal                   */
+
+  uint32_t ExtendedMode;                 /*!< Enables or disables the extended mode.
+                                              This parameter can be a value of @ref FMC_Extended_Mode                 */
+
+  uint32_t AsynchronousWait;             /*!< Enables or disables wait signal during asynchronous transfers,
+                                              valid only with asynchronous Flash memories.
+                                              This parameter can be a value of @ref FMC_AsynchronousWait              */
+
+  uint32_t WriteBurst;                   /*!< Enables or disables the write burst operation.
+                                              This parameter can be a value of @ref FMC_Write_Burst                   */
+
+  uint32_t ContinuousClock;              /*!< Enables or disables the FMC clock output to external memory devices.
+                                              This parameter is only enabled through the FMC_BCR1 register,
+                                              and don't care through FMC_BCR2..4 registers.
+                                              This parameter can be a value of @ref FMC_Continous_Clock               */
+
+  uint32_t WriteFifo;                    /*!< Enables or disables the write FIFO used by the FMC controller.
+                                              This parameter is only enabled through the FMC_BCR1 register,
+                                              and don't care through FMC_BCR2..4 registers.
+                                              This parameter can be a value of @ref FMC_Write_FIFO
+                                              This mode is available only for the STM32F446/469/479xx devices         */
+
+  uint32_t PageSize;                     /*!< Specifies the memory page size.
+                                              This parameter can be a value of @ref FMC_Page_Size                     */
+} FMC_NORSRAM_InitTypeDef;
+
+/**
+  * @brief  FMC NORSRAM Timing parameters structure definition
+  */
+typedef struct
+{
+  uint32_t AddressSetupTime;             /*!< Defines the number of HCLK cycles to configure
+                                              the duration of the address setup time.
+                                              This parameter can be a value between Min_Data = 0 and Max_Data = 15.
+                                              @note This parameter is not used with synchronous NOR Flash memories.   */
+
+  uint32_t AddressHoldTime;              /*!< Defines the number of HCLK cycles to configure
+                                              the duration of the address hold time.
+                                              This parameter can be a value between Min_Data = 1 and Max_Data = 15.
+                                              @note This parameter is not used with synchronous NOR Flash memories.   */
+
+  uint32_t DataSetupTime;                /*!< Defines the number of HCLK cycles to configure
+                                              the duration of the data setup time.
+                                              This parameter can be a value between Min_Data = 1 and Max_Data = 255.
+                                              @note This parameter is used for SRAMs, ROMs and asynchronous multiplexed
+                                              NOR Flash memories.                                                     */
+
+  uint32_t BusTurnAroundDuration;        /*!< Defines the number of HCLK cycles to configure
+                                              the duration of the bus turnaround.
+                                              This parameter can be a value between Min_Data = 0 and Max_Data = 15.
+                                              @note This parameter is only used for multiplexed NOR Flash memories.   */
+
+  uint32_t CLKDivision;                  /*!< Defines the period of CLK clock output signal, expressed in number of
+                                              HCLK cycles. This parameter can be a value between Min_Data = 2 and
+                                              Max_Data = 16.
+                                              @note This parameter is not used for asynchronous NOR Flash, SRAM or ROM
+                                              accesses.                                                               */
+
+  uint32_t DataLatency;                  /*!< Defines the number of memory clock cycles to issue
+                                              to the memory before getting the first data.
+                                              The parameter value depends on the memory type as shown below:
+                                              - It must be set to 0 in case of a CRAM
+                                              - It is don't care in asynchronous NOR, SRAM or ROM accesses
+                                              - It may assume a value between Min_Data = 2 and Max_Data = 17
+                                                in NOR Flash memories with synchronous burst mode enable              */
+
+  uint32_t AccessMode;                   /*!< Specifies the asynchronous access mode.
+                                              This parameter can be a value of @ref FMC_Access_Mode                   */
+} FMC_NORSRAM_TimingTypeDef;
+#endif /* FMC_Bank1 */
+
+#if defined(FMC_Bank3) || defined(FMC_Bank2_3)
+/**
+  * @brief  FMC NAND Configuration Structure definition
+  */
+typedef struct
+{
+  uint32_t NandBank;               /*!< Specifies the NAND memory device that will be used.
+                                        This parameter can be a value of @ref FMC_NAND_Bank                  */
+
+  uint32_t Waitfeature;            /*!< Enables or disables the Wait feature for the NAND Memory device.
+                                        This parameter can be any value of @ref FMC_Wait_feature             */
+
+  uint32_t MemoryDataWidth;        /*!< Specifies the external memory device width.
+                                        This parameter can be any value of @ref FMC_NAND_Data_Width          */
+
+  uint32_t EccComputation;         /*!< Enables or disables the ECC computation.
+                                        This parameter can be any value of @ref FMC_ECC                      */
+
+  uint32_t ECCPageSize;            /*!< Defines the page size for the extended ECC.
+                                        This parameter can be any value of @ref FMC_ECC_Page_Size            */
+
+  uint32_t TCLRSetupTime;          /*!< Defines the number of HCLK cycles to configure the
+                                        delay between CLE low and RE low.
+                                        This parameter can be a value between Min_Data = 0 and Max_Data = 255  */
+
+  uint32_t TARSetupTime;           /*!< Defines the number of HCLK cycles to configure the
+                                        delay between ALE low and RE low.
+                                        This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
+} FMC_NAND_InitTypeDef;
+#endif
+
+#if defined(FMC_Bank3) || defined(FMC_Bank2_3) || defined(FMC_Bank4)
+/**
+  * @brief  FMC NAND Timing parameters structure definition
+  */
+typedef struct
+{
+  uint32_t SetupTime;            /*!< Defines the number of HCLK cycles to setup address before
+                                      the command assertion for NAND-Flash read or write access
+                                      to common/Attribute or I/O memory space (depending on
+                                      the memory space timing to be configured).
+                                      This parameter can be a value between Min_Data = 0 and Max_Data = 254    */
+
+  uint32_t WaitSetupTime;        /*!< Defines the minimum number of HCLK cycles to assert the
+                                      command for NAND-Flash read or write access to
+                                      common/Attribute or I/O memory space (depending on the
+                                      memory space timing to be configured).
+                                      This parameter can be a number between Min_Data = 0 and Max_Data = 254   */
+
+  uint32_t HoldSetupTime;        /*!< Defines the number of HCLK clock cycles to hold address
+                                      (and data for write access) after the command de-assertion
+                                      for NAND-Flash read or write access to common/Attribute
+                                      or I/O memory space (depending on the memory space timing
+                                      to be configured).
+                                      This parameter can be a number between Min_Data = 0 and Max_Data = 254   */
+
+  uint32_t HiZSetupTime;         /*!< Defines the number of HCLK clock cycles during which the
+                                      data bus is kept in HiZ after the start of a NAND-Flash
+                                      write access to common/Attribute or I/O memory space (depending
+                                      on the memory space timing to be configured).
+                                      This parameter can be a number between Min_Data = 0 and Max_Data = 254   */
+} FMC_NAND_PCC_TimingTypeDef;
+#endif /* FMC_Bank3 || FMC_Bank2_3 */
+
+#if defined(FMC_Bank4)
+/**
+  * @brief FMC PCCARD Configuration Structure definition
+  */
+typedef struct
+{
+  uint32_t Waitfeature;            /*!< Enables or disables the Wait feature for the PCCARD Memory device.
+                                        This parameter can be any value of @ref FMC_Wait_feature      */
+
+  uint32_t TCLRSetupTime;          /*!< Defines the number of HCLK cycles to configure the
+                                        delay between CLE low and RE low.
+                                        This parameter can be a value between Min_Data = 0 and Max_Data = 255  */
+
+  uint32_t TARSetupTime;           /*!< Defines the number of HCLK cycles to configure the
+                                        delay between ALE low and RE low.
+                                        This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
+}FMC_PCCARD_InitTypeDef;
+#endif /* FMC_Bank4 */
+
+#if defined(FMC_Bank5_6)
+/**
+  * @brief  FMC SDRAM Configuration Structure definition
+  */
+typedef struct
+{
+  uint32_t SDBank;                      /*!< Specifies the SDRAM memory device that will be used.
+                                             This parameter can be a value of @ref FMC_SDRAM_Bank                */
+
+  uint32_t ColumnBitsNumber;            /*!< Defines the number of bits of column address.
+                                             This parameter can be a value of @ref FMC_SDRAM_Column_Bits_number. */
+
+  uint32_t RowBitsNumber;               /*!< Defines the number of bits of column address.
+                                             This parameter can be a value of @ref FMC_SDRAM_Row_Bits_number.    */
+
+  uint32_t MemoryDataWidth;             /*!< Defines the memory device width.
+                                             This parameter can be a value of @ref FMC_SDRAM_Memory_Bus_Width.   */
+
+  uint32_t InternalBankNumber;          /*!< Defines the number of the device's internal banks.
+                                             This parameter can be of @ref FMC_SDRAM_Internal_Banks_Number.      */
+
+  uint32_t CASLatency;                  /*!< Defines the SDRAM CAS latency in number of memory clock cycles.
+                                             This parameter can be a value of @ref FMC_SDRAM_CAS_Latency.        */
+
+  uint32_t WriteProtection;             /*!< Enables the SDRAM device to be accessed in write mode.
+                                             This parameter can be a value of @ref FMC_SDRAM_Write_Protection.   */
+
+  uint32_t SDClockPeriod;               /*!< Define the SDRAM Clock Period for both SDRAM devices and they allow
+                                             to disable the clock before changing frequency.
+                                             This parameter can be a value of @ref FMC_SDRAM_Clock_Period.       */
+
+  uint32_t ReadBurst;                   /*!< This bit enable the SDRAM controller to anticipate the next read
+                                             commands during the CAS latency and stores data in the Read FIFO.
+                                             This parameter can be a value of @ref FMC_SDRAM_Read_Burst.         */
+
+  uint32_t ReadPipeDelay;               /*!< Define the delay in system clock cycles on read data path.
+                                             This parameter can be a value of @ref FMC_SDRAM_Read_Pipe_Delay.    */
+} FMC_SDRAM_InitTypeDef;
+
+/**
+  * @brief FMC SDRAM Timing parameters structure definition
+  */
+typedef struct
+{
+  uint32_t LoadToActiveDelay;            /*!< Defines the delay between a Load Mode Register command and
+                                              an active or Refresh command in number of memory clock cycles.
+                                              This parameter can be a value between Min_Data = 1 and Max_Data = 16  */
+
+  uint32_t ExitSelfRefreshDelay;         /*!< Defines the delay from releasing the self refresh command to
+                                              issuing the Activate command in number of memory clock cycles.
+                                              This parameter can be a value between Min_Data = 1 and Max_Data = 16  */
+
+  uint32_t SelfRefreshTime;              /*!< Defines the minimum Self Refresh period in number of memory clock
+                                              cycles.
+                                              This parameter can be a value between Min_Data = 1 and Max_Data = 16  */
+
+  uint32_t RowCycleDelay;                /*!< Defines the delay between the Refresh command and the Activate command
+                                              and the delay between two consecutive Refresh commands in number of
+                                              memory clock cycles.
+                                              This parameter can be a value between Min_Data = 1 and Max_Data = 16  */
+
+  uint32_t WriteRecoveryTime;            /*!< Defines the Write recovery Time in number of memory clock cycles.
+                                              This parameter can be a value between Min_Data = 1 and Max_Data = 16  */
+
+  uint32_t RPDelay;                      /*!< Defines the delay between a Precharge Command and an other command
+                                              in number of memory clock cycles.
+                                              This parameter can be a value between Min_Data = 1 and Max_Data = 16  */
+
+  uint32_t RCDDelay;                     /*!< Defines the delay between the Activate Command and a Read/Write
+                                              command in number of memory clock cycles.
+                                              This parameter can be a value between Min_Data = 1 and Max_Data = 16  */
+} FMC_SDRAM_TimingTypeDef;
+
+/**
+  * @brief SDRAM command parameters structure definition
+  */
+typedef struct
+{
+  uint32_t CommandMode;                  /*!< Defines the command issued to the SDRAM device.
+                                              This parameter can be a value of @ref FMC_SDRAM_Command_Mode.          */
+
+  uint32_t CommandTarget;                /*!< Defines which device (1 or 2) the command will be issued to.
+                                              This parameter can be a value of @ref FMC_SDRAM_Command_Target.        */
+
+  uint32_t AutoRefreshNumber;            /*!< Defines the number of consecutive auto refresh command issued
+                                              in auto refresh mode.
+                                              This parameter can be a value between Min_Data = 1 and Max_Data = 15   */
+
+  uint32_t ModeRegisterDefinition;       /*!< Defines the SDRAM Mode register content                                */
+} FMC_SDRAM_CommandTypeDef;
+#endif /* FMC_Bank5_6 */
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+/** @addtogroup FMC_LL_Exported_Constants FMC Low Layer Exported Constants
+  * @{
+  */
+#if defined(FMC_Bank1)
+
+/** @defgroup FMC_LL_NOR_SRAM_Controller FMC NOR/SRAM Controller
+  * @{
+  */
+
+/** @defgroup FMC_NORSRAM_Bank FMC NOR/SRAM Bank
+  * @{
+  */
+#define FMC_NORSRAM_BANK1                       (0x00000000U)
+#define FMC_NORSRAM_BANK2                       (0x00000002U)
+#define FMC_NORSRAM_BANK3                       (0x00000004U)
+#define FMC_NORSRAM_BANK4                       (0x00000006U)
+/**
+  * @}
+  */
+
+/** @defgroup FMC_Data_Address_Bus_Multiplexing FMC Data Address Bus Multiplexing
+  * @{
+  */
+#define FMC_DATA_ADDRESS_MUX_DISABLE            (0x00000000U)
+#define FMC_DATA_ADDRESS_MUX_ENABLE             (0x00000002U)
+/**
+  * @}
+  */
+
+/** @defgroup FMC_Memory_Type FMC Memory Type
+  * @{
+  */
+#define FMC_MEMORY_TYPE_SRAM                    (0x00000000U)
+#define FMC_MEMORY_TYPE_PSRAM                   (0x00000004U)
+#define FMC_MEMORY_TYPE_NOR                     (0x00000008U)
+/**
+  * @}
+  */
+
+/** @defgroup FMC_NORSRAM_Data_Width FMC NORSRAM Data Width
+  * @{
+  */
+#define FMC_NORSRAM_MEM_BUS_WIDTH_8             (0x00000000U)
+#define FMC_NORSRAM_MEM_BUS_WIDTH_16            (0x00000010U)
+#define FMC_NORSRAM_MEM_BUS_WIDTH_32            (0x00000020U)
+/**
+  * @}
+  */
+
+/** @defgroup FMC_NORSRAM_Flash_Access FMC NOR/SRAM Flash Access
+  * @{
+  */
+#define FMC_NORSRAM_FLASH_ACCESS_ENABLE         (0x00000040U)
+#define FMC_NORSRAM_FLASH_ACCESS_DISABLE        (0x00000000U)
+/**
+  * @}
+  */
+
+/** @defgroup FMC_Burst_Access_Mode FMC Burst Access Mode
+  * @{
+  */
+#define FMC_BURST_ACCESS_MODE_DISABLE           (0x00000000U)
+#define FMC_BURST_ACCESS_MODE_ENABLE            (0x00000100U)
+/**
+  * @}
+  */
+
+/** @defgroup FMC_Wait_Signal_Polarity FMC Wait Signal Polarity
+  * @{
+  */
+#define FMC_WAIT_SIGNAL_POLARITY_LOW            (0x00000000U)
+#define FMC_WAIT_SIGNAL_POLARITY_HIGH           (0x00000200U)
+/**
+  * @}
+  */
+
+/** @defgroup FMC_Wrap_Mode FMC Wrap Mode
+  * @note This mode is not available for the STM32F446/469/479xx devices
+  * @{
+  */
+#define FMC_WRAP_MODE_DISABLE                   (0x00000000U)
+#define FMC_WRAP_MODE_ENABLE                    (0x00000400U)
+/**
+  * @}
+  */
+
+/** @defgroup FMC_Wait_Timing FMC Wait Timing
+  * @{
+  */
+#define FMC_WAIT_TIMING_BEFORE_WS               (0x00000000U)
+#define FMC_WAIT_TIMING_DURING_WS               (0x00000800U)
+/**
+  * @}
+  */
+
+/** @defgroup FMC_Write_Operation FMC Write Operation
+  * @{
+  */
+#define FMC_WRITE_OPERATION_DISABLE             (0x00000000U)
+#define FMC_WRITE_OPERATION_ENABLE              (0x00001000U)
+/**
+  * @}
+  */
+
+/** @defgroup FMC_Wait_Signal FMC Wait Signal
+  * @{
+  */
+#define FMC_WAIT_SIGNAL_DISABLE                 (0x00000000U)
+#define FMC_WAIT_SIGNAL_ENABLE                  (0x00002000U)
+/**
+  * @}
+  */
+
+/** @defgroup FMC_Extended_Mode FMC Extended Mode
+  * @{
+  */
+#define FMC_EXTENDED_MODE_DISABLE               (0x00000000U)
+#define FMC_EXTENDED_MODE_ENABLE                (0x00004000U)
+/**
+  * @}
+  */
+
+/** @defgroup FMC_AsynchronousWait FMC Asynchronous Wait
+  * @{
+  */
+#define FMC_ASYNCHRONOUS_WAIT_DISABLE           (0x00000000U)
+#define FMC_ASYNCHRONOUS_WAIT_ENABLE            (0x00008000U)
+/**
+  * @}
+  */
+
+/** @defgroup FMC_Page_Size FMC Page Size
+  * @{
+  */
+#define FMC_PAGE_SIZE_NONE                      (0x00000000U)
+#define FMC_PAGE_SIZE_128                       FMC_BCR1_CPSIZE_0
+#define FMC_PAGE_SIZE_256                       FMC_BCR1_CPSIZE_1
+#define FMC_PAGE_SIZE_512                       (FMC_BCR1_CPSIZE_0\
+                                                 | FMC_BCR1_CPSIZE_1)
+#define FMC_PAGE_SIZE_1024                      FMC_BCR1_CPSIZE_2
+/**
+  * @}
+  */
+
+/** @defgroup FMC_Write_Burst FMC Write Burst
+  * @{
+  */
+#define FMC_WRITE_BURST_DISABLE                 (0x00000000U)
+#define FMC_WRITE_BURST_ENABLE                  (0x00080000U)
+/**
+  * @}
+  */
+
+/** @defgroup FMC_Continous_Clock FMC Continuous Clock
+  * @{
+  */
+#define FMC_CONTINUOUS_CLOCK_SYNC_ONLY          (0x00000000U)
+#define FMC_CONTINUOUS_CLOCK_SYNC_ASYNC         (0x00100000U)
+/**
+  * @}
+  */
+
+#if defined(FMC_BCR1_WFDIS)
+/** @defgroup FMC_Write_FIFO FMC Write FIFO
+  * @note  These values are available only for the STM32F446/469/479xx devices.
+  * @{
+  */
+#define FMC_WRITE_FIFO_DISABLE                  FMC_BCR1_WFDIS
+#define FMC_WRITE_FIFO_ENABLE                   (0x00000000U)
+#endif /* FMC_BCR1_WFDIS */
+/**
+  * @}
+  */
+
+/** @defgroup FMC_Access_Mode FMC Access Mode
+  * @{
+  */
+#define FMC_ACCESS_MODE_A                       (0x00000000U)
+#define FMC_ACCESS_MODE_B                       (0x10000000U)
+#define FMC_ACCESS_MODE_C                       (0x20000000U)
+#define FMC_ACCESS_MODE_D                       (0x30000000U)
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+#endif /* FMC_Bank1 */
+
+#if defined(FMC_Bank3) || defined(FMC_Bank2_3) || defined(FMC_Bank4)
+
+/** @defgroup FMC_LL_NAND_Controller FMC NAND Controller
+  * @{
+  */
+/** @defgroup FMC_NAND_Bank FMC NAND Bank
+  * @{
+  */
+#if defined(FMC_Bank2_3)
+#define FMC_NAND_BANK2                          (0x00000010U)
+#endif
+#define FMC_NAND_BANK3                          (0x00000100U)
+/**
+  * @}
+  */
+
+/** @defgroup FMC_Wait_feature FMC Wait feature
+  * @{
+  */
+#define FMC_NAND_PCC_WAIT_FEATURE_DISABLE       (0x00000000U)
+#define FMC_NAND_PCC_WAIT_FEATURE_ENABLE        (0x00000002U)
+/**
+  * @}
+  */
+
+/** @defgroup FMC_PCR_Memory_Type FMC PCR Memory Type
+  * @{
+  */
+#if defined(FMC_Bank4)
+#define FMC_PCR_MEMORY_TYPE_PCCARD              (0x00000000U)
+#endif /* FMC_Bank4 */
+#define FMC_PCR_MEMORY_TYPE_NAND                (0x00000008U)
+/**
+  * @}
+  */
+
+/** @defgroup FMC_NAND_Data_Width FMC NAND Data Width
+  * @{
+  */
+#define FMC_NAND_PCC_MEM_BUS_WIDTH_8            (0x00000000U)
+#define FMC_NAND_PCC_MEM_BUS_WIDTH_16           (0x00000010U)
+/**
+  * @}
+  */
+
+/** @defgroup FMC_ECC FMC ECC
+  * @{
+  */
+#define FMC_NAND_ECC_DISABLE                    (0x00000000U)
+#define FMC_NAND_ECC_ENABLE                     (0x00000040U)
+/**
+  * @}
+  */
+
+/** @defgroup FMC_ECC_Page_Size FMC ECC Page Size
+  * @{
+  */
+#define FMC_NAND_ECC_PAGE_SIZE_256BYTE          (0x00000000U)
+#define FMC_NAND_ECC_PAGE_SIZE_512BYTE          (0x00020000U)
+#define FMC_NAND_ECC_PAGE_SIZE_1024BYTE         (0x00040000U)
+#define FMC_NAND_ECC_PAGE_SIZE_2048BYTE         (0x00060000U)
+#define FMC_NAND_ECC_PAGE_SIZE_4096BYTE         (0x00080000U)
+#define FMC_NAND_ECC_PAGE_SIZE_8192BYTE         (0x000A0000U)
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+#endif /* FMC_Bank3 || FMC_Bank2_3 || FMC_Bank4 */
+
+#if defined(FMC_Bank5_6)
+/** @defgroup FMC_LL_SDRAM_Controller FMC SDRAM Controller
+  * @{
+  */
+/** @defgroup FMC_SDRAM_Bank FMC SDRAM Bank
+  * @{
+  */
+#define FMC_SDRAM_BANK1                         (0x00000000U)
+#define FMC_SDRAM_BANK2                         (0x00000001U)
+/**
+  * @}
+  */
+
+/** @defgroup FMC_SDRAM_Column_Bits_number FMC SDRAM Column Bits number
+  * @{
+  */
+#define FMC_SDRAM_COLUMN_BITS_NUM_8             (0x00000000U)
+#define FMC_SDRAM_COLUMN_BITS_NUM_9             (0x00000001U)
+#define FMC_SDRAM_COLUMN_BITS_NUM_10            (0x00000002U)
+#define FMC_SDRAM_COLUMN_BITS_NUM_11            (0x00000003U)
+/**
+  * @}
+  */
+
+/** @defgroup FMC_SDRAM_Row_Bits_number FMC SDRAM Row Bits number
+  * @{
+  */
+#define FMC_SDRAM_ROW_BITS_NUM_11               (0x00000000U)
+#define FMC_SDRAM_ROW_BITS_NUM_12               (0x00000004U)
+#define FMC_SDRAM_ROW_BITS_NUM_13               (0x00000008U)
+/**
+  * @}
+  */
+
+/** @defgroup FMC_SDRAM_Memory_Bus_Width FMC SDRAM Memory Bus Width
+  * @{
+  */
+#define FMC_SDRAM_MEM_BUS_WIDTH_8               (0x00000000U)
+#define FMC_SDRAM_MEM_BUS_WIDTH_16              (0x00000010U)
+#define FMC_SDRAM_MEM_BUS_WIDTH_32              (0x00000020U)
+/**
+  * @}
+  */
+
+/** @defgroup FMC_SDRAM_Internal_Banks_Number FMC SDRAM Internal Banks Number
+  * @{
+  */
+#define FMC_SDRAM_INTERN_BANKS_NUM_2            (0x00000000U)
+#define FMC_SDRAM_INTERN_BANKS_NUM_4            (0x00000040U)
+/**
+  * @}
+  */
+
+/** @defgroup FMC_SDRAM_CAS_Latency FMC SDRAM CAS Latency
+  * @{
+  */
+#define FMC_SDRAM_CAS_LATENCY_1                 (0x00000080U)
+#define FMC_SDRAM_CAS_LATENCY_2                 (0x00000100U)
+#define FMC_SDRAM_CAS_LATENCY_3                 (0x00000180U)
+/**
+  * @}
+  */
+
+/** @defgroup FMC_SDRAM_Write_Protection FMC SDRAM Write Protection
+  * @{
+  */
+#define FMC_SDRAM_WRITE_PROTECTION_DISABLE      (0x00000000U)
+#define FMC_SDRAM_WRITE_PROTECTION_ENABLE       (0x00000200U)
+/**
+  * @}
+  */
+
+/** @defgroup FMC_SDRAM_Clock_Period FMC SDRAM Clock Period
+  * @{
+  */
+#define FMC_SDRAM_CLOCK_DISABLE                 (0x00000000U)
+#define FMC_SDRAM_CLOCK_PERIOD_2                (0x00000800U)
+#define FMC_SDRAM_CLOCK_PERIOD_3                (0x00000C00U)
+/**
+  * @}
+  */
+
+/** @defgroup FMC_SDRAM_Read_Burst FMC SDRAM Read Burst
+  * @{
+  */
+#define FMC_SDRAM_RBURST_DISABLE                (0x00000000U)
+#define FMC_SDRAM_RBURST_ENABLE                 (0x00001000U)
+/**
+  * @}
+  */
+
+/** @defgroup FMC_SDRAM_Read_Pipe_Delay FMC SDRAM Read Pipe Delay
+  * @{
+  */
+#define FMC_SDRAM_RPIPE_DELAY_0                 (0x00000000U)
+#define FMC_SDRAM_RPIPE_DELAY_1                 (0x00002000U)
+#define FMC_SDRAM_RPIPE_DELAY_2                 (0x00004000U)
+/**
+  * @}
+  */
+
+/** @defgroup FMC_SDRAM_Command_Mode FMC SDRAM Command Mode
+  * @{
+  */
+#define FMC_SDRAM_CMD_NORMAL_MODE               (0x00000000U)
+#define FMC_SDRAM_CMD_CLK_ENABLE                (0x00000001U)
+#define FMC_SDRAM_CMD_PALL                      (0x00000002U)
+#define FMC_SDRAM_CMD_AUTOREFRESH_MODE          (0x00000003U)
+#define FMC_SDRAM_CMD_LOAD_MODE                 (0x00000004U)
+#define FMC_SDRAM_CMD_SELFREFRESH_MODE          (0x00000005U)
+#define FMC_SDRAM_CMD_POWERDOWN_MODE            (0x00000006U)
+/**
+  * @}
+  */
+
+/** @defgroup FMC_SDRAM_Command_Target FMC SDRAM Command Target
+  * @{
+  */
+#define FMC_SDRAM_CMD_TARGET_BANK2              FMC_SDCMR_CTB2
+#define FMC_SDRAM_CMD_TARGET_BANK1              FMC_SDCMR_CTB1
+#define FMC_SDRAM_CMD_TARGET_BANK1_2            (0x00000018U)
+/**
+  * @}
+  */
+
+/** @defgroup FMC_SDRAM_Mode_Status FMC SDRAM Mode Status
+  * @{
+  */
+#define FMC_SDRAM_NORMAL_MODE                   (0x00000000U)
+#define FMC_SDRAM_SELF_REFRESH_MODE             FMC_SDSR_MODES1_0
+#define FMC_SDRAM_POWER_DOWN_MODE               FMC_SDSR_MODES1_1
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* FMC_Bank5_6 */
+
+/** @defgroup FMC_LL_Interrupt_definition FMC Low Layer Interrupt definition
+  * @{
+  */
+#if defined(FMC_Bank3) || defined(FMC_Bank2_3) || defined(FMC_Bank4)
+#define FMC_IT_RISING_EDGE                      (0x00000008U)
+#define FMC_IT_LEVEL                            (0x00000010U)
+#define FMC_IT_FALLING_EDGE                     (0x00000020U)
+#endif /* FMC_Bank3 || FMC_Bank2_3 || FMC_Bank4 */
+#if defined(FMC_Bank5_6)
+#define FMC_IT_REFRESH_ERROR                    (0x00004000U)
+#endif /* FMC_Bank5_6 */
+/**
+  * @}
+  */
+
+/** @defgroup FMC_LL_Flag_definition FMC Low Layer Flag definition
+  * @{
+  */
+#if defined(FMC_Bank3) || defined(FMC_Bank2_3) || defined(FMC_Bank4)
+#define FMC_FLAG_RISING_EDGE                    (0x00000001U)
+#define FMC_FLAG_LEVEL                          (0x00000002U)
+#define FMC_FLAG_FALLING_EDGE                   (0x00000004U)
+#define FMC_FLAG_FEMPT                          (0x00000040U)
+#endif /* FMC_Bank3 || FMC_Bank2_3 || FMC_Bank4 */
+#if defined(FMC_Bank5_6)
+#define FMC_SDRAM_FLAG_REFRESH_IT               FMC_SDSR_RE
+#define FMC_SDRAM_FLAG_BUSY                     FMC_SDSR_BUSY
+#define FMC_SDRAM_FLAG_REFRESH_ERROR            FMC_SDRTR_CRE
+#endif /* FMC_Bank5_6 */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private macro -------------------------------------------------------------*/
+/** @defgroup FMC_LL_Private_Macros FMC_LL  Private Macros
+  * @{
+  */
+#if defined(FMC_Bank1)
+/** @defgroup FMC_LL_NOR_Macros FMC NOR/SRAM Macros
+  * @brief macros to handle NOR device enable/disable and read/write operations
+  * @{
+  */
+
+/**
+  * @brief  Enable the NORSRAM device access.
+  * @param  __INSTANCE__ FMC_NORSRAM Instance
+  * @param  __BANK__ FMC_NORSRAM Bank
+  * @retval None
+  */
+#define __FMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__)  ((__INSTANCE__)->BTCR[(__BANK__)]\
+                                                       |= FMC_BCR1_MBKEN)
+
+/**
+  * @brief  Disable the NORSRAM device access.
+  * @param  __INSTANCE__ FMC_NORSRAM Instance
+  * @param  __BANK__ FMC_NORSRAM Bank
+  * @retval None
+  */
+#define __FMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)]\
+                                                       &= ~FMC_BCR1_MBKEN)
+
+/**
+  * @}
+  */
+#endif /* FMC_Bank1 */
+
+#if defined(FMC_Bank3) || defined(FMC_Bank2_3)
+/** @defgroup FMC_LL_NAND_Macros FMC NAND Macros
+  *  @brief macros to handle NAND device enable/disable
+  *  @{
+  */
+
+/**
+  * @brief  Enable the NAND device access.
+  * @param  __INSTANCE__ FMC_NAND Instance
+  * @param  __BANK__     FMC_NAND Bank
+  * @retval None
+  */
+#if defined(FMC_Bank2_3)
+#if defined (FMC_PCR_PBKEN)
+#define __FMC_NAND_ENABLE(__INSTANCE__)  ((__INSTANCE__)->PCR |= FMC_PCR_PBKEN)
+#else
+#define __FMC_NAND_ENABLE(__INSTANCE__, __BANK__)  (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->PCR2 |= FMC_PCR2_PBKEN): \
+                                                             ((__INSTANCE__)->PCR3 |= FMC_PCR3_PBKEN))
+#endif /* FMC_PCR_PBKEN */
+#else
+#define __FMC_NAND_ENABLE(__INSTANCE__)  ((__INSTANCE__)->PCR |= FMC_PCR_PBKEN)
+#endif /* FMC_Bank2_3 */
+
+/**
+  * @brief  Disable the NAND device access.
+  * @param  __INSTANCE__ FMC_NAND Instance
+  * @param  __BANK__     FMC_NAND Bank
+  * @retval None
+  */
+#if defined(FMC_Bank2_3)
+#if  defined (FMC_PCR_PBKEN)
+#define __FMC_NAND_DISABLE(__INSTANCE__, __BANK__) CLEAR_BIT((__INSTANCE__)->PCR, FMC_PCR_PBKEN)
+#else
+#define __FMC_NAND_DISABLE(__INSTANCE__, __BANK__) (((__BANK__) == FMC_NAND_BANK2)? CLEAR_BIT((__INSTANCE__)->PCR2, FMC_PCR2_PBKEN): \
+                                                             CLEAR_BIT((__INSTANCE__)->PCR3, FMC_PCR3_PBKEN))
+#endif /* FMC_PCR_PBKEN */
+#else
+#define __FMC_NAND_DISABLE(__INSTANCE__, __BANK__) CLEAR_BIT((__INSTANCE__)->PCR, FMC_PCR_PBKEN)
+#endif /* FMC_Bank2_3 */
+
+/**
+  * @}
+  */
+#endif /* FMC_Bank3 || FMC_Bank2_3 */
+
+#if defined(FMC_Bank4)
+/** @defgroup FMC_LL_PCCARD_Macros FMC PCCARD Macros
+  *  @brief macros to handle PCCARD read/write operations
+  *  @{
+  */
+/**
+  * @brief  Enable the PCCARD device access.
+  * @param  __INSTANCE__ FMC_PCCARD Instance
+  * @retval None
+  */
+#define __FMC_PCCARD_ENABLE(__INSTANCE__)  ((__INSTANCE__)->PCR4 |= FMC_PCR4_PBKEN)
+
+/**
+  * @brief  Disable the PCCARD device access.
+  * @param  __INSTANCE__ FMC_PCCARD Instance
+  * @retval None
+  */
+#define __FMC_PCCARD_DISABLE(__INSTANCE__) ((__INSTANCE__)->PCR4 &= ~FMC_PCR4_PBKEN)
+/**
+  * @}
+  */
+
+#endif
+#if defined(FMC_Bank3) || defined(FMC_Bank2_3)
+/** @defgroup FMC_LL_NAND_Interrupt FMC NAND Interrupt
+  * @brief macros to handle NAND interrupts
+  * @{
+  */
+
+/**
+  * @brief  Enable the NAND device interrupt.
+  * @param  __INSTANCE__  FMC_NAND instance
+  * @param  __BANK__     FMC_NAND Bank
+  * @param  __INTERRUPT__ FMC_NAND interrupt
+  *         This parameter can be any combination of the following values:
+  *            @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
+  *            @arg FMC_IT_LEVEL: Interrupt level.
+  *            @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
+  * @retval None
+  */
+#if defined(FMC_Bank2_3)
+#define __FMC_NAND_ENABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__)  (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->SR2 |= (__INTERRUPT__)): \
+                                                                               ((__INSTANCE__)->SR3 |= (__INTERRUPT__)))
+#else
+#define __FMC_NAND_ENABLE_IT(__INSTANCE__, __INTERRUPT__)  ((__INSTANCE__)->SR |= (__INTERRUPT__))
+#endif /* FMC_Bank2_3 */
+
+/**
+  * @brief  Disable the NAND device interrupt.
+  * @param  __INSTANCE__  FMC_NAND Instance
+  * @param  __BANK__     FMC_NAND Bank
+  * @param  __INTERRUPT__ FMC_NAND interrupt
+  *         This parameter can be any combination of the following values:
+  *            @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
+  *            @arg FMC_IT_LEVEL: Interrupt level.
+  *            @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
+  * @retval None
+  */
+#if defined(FMC_Bank2_3)
+#define __FMC_NAND_DISABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__)  (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->SR2 &= ~(__INTERRUPT__)): \
+                                                                                ((__INSTANCE__)->SR3 &= ~(__INTERRUPT__)))
+#else
+#define __FMC_NAND_DISABLE_IT(__INSTANCE__, __INTERRUPT__)  ((__INSTANCE__)->SR &= ~(__INTERRUPT__))
+#endif /* FMC_Bank2_3 */
+
+/**
+  * @brief  Get flag status of the NAND device.
+  * @param  __INSTANCE__ FMC_NAND Instance
+  * @param  __BANK__     FMC_NAND Bank
+  * @param  __FLAG__     FMC_NAND flag
+  *         This parameter can be any combination of the following values:
+  *            @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
+  *            @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
+  *            @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
+  *            @arg FMC_FLAG_FEMPT: FIFO empty flag.
+  * @retval The state of FLAG (SET or RESET).
+  */
+#if defined(FMC_Bank2_3)
+#define __FMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__)  (((__BANK__) == FMC_NAND_BANK2)? (((__INSTANCE__)->SR2 &(__FLAG__)) == (__FLAG__)): \
+                                                                         (((__INSTANCE__)->SR3 &(__FLAG__)) == (__FLAG__)))
+#else
+#define __FMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__)  (((__INSTANCE__)->SR &(__FLAG__)) == (__FLAG__))
+#endif /* FMC_Bank2_3 */
+
+/**
+  * @brief  Clear flag status of the NAND device.
+  * @param  __INSTANCE__ FMC_NAND Instance
+  * @param  __BANK__     FMC_NAND Bank
+  * @param  __FLAG__     FMC_NAND flag
+  *         This parameter can be any combination of the following values:
+  *            @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
+  *            @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
+  *            @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
+  *            @arg FMC_FLAG_FEMPT: FIFO empty flag.
+  * @retval None
+  */
+#if defined(FMC_Bank2_3)
+#define __FMC_NAND_CLEAR_FLAG(__INSTANCE__, __BANK__, __FLAG__)  (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->SR2 &= ~(__FLAG__)): \
+                                                                           ((__INSTANCE__)->SR3 &= ~(__FLAG__)))
+#else
+#define __FMC_NAND_CLEAR_FLAG(__INSTANCE__, __FLAG__)  ((__INSTANCE__)->SR &= ~(__FLAG__))
+#endif /* FMC_Bank2_3 */
+
+/**
+  * @}
+  */
+#endif /* FMC_Bank3) || defined(FMC_Bank2_3 */
+
+#if defined(FMC_Bank4)
+/** @defgroup FMC_LL_PCCARD_Interrupt FMC PCCARD Interrupt
+  * @brief macros to handle PCCARD interrupts
+  * @{
+  */
+
+/**
+  * @brief  Enable the PCCARD device interrupt.
+  * @param  __INSTANCE__ FMC_PCCARD instance
+  * @param  __INTERRUPT__ FMC_PCCARD interrupt
+  *         This parameter can be any combination of the following values:
+  *            @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
+  *            @arg FMC_IT_LEVEL: Interrupt level.
+  *            @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
+  * @retval None
+  */
+#define __FMC_PCCARD_ENABLE_IT(__INSTANCE__, __INTERRUPT__)  ((__INSTANCE__)->SR4 |= (__INTERRUPT__))
+
+/**
+  * @brief  Disable the PCCARD device interrupt.
+  * @param  __INSTANCE__ FMC_PCCARD instance
+  * @param  __INTERRUPT__ FMC_PCCARD interrupt
+  *         This parameter can be any combination of the following values:
+  *            @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
+  *            @arg FMC_IT_LEVEL: Interrupt level.
+  *            @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
+  * @retval None
+  */
+#define __FMC_PCCARD_DISABLE_IT(__INSTANCE__, __INTERRUPT__)  ((__INSTANCE__)->SR4 &= ~(__INTERRUPT__))
+
+/**
+  * @brief  Get flag status of the PCCARD device.
+  * @param  __INSTANCE__ FMC_PCCARD instance
+  * @param  __FLAG__ FMC_PCCARD flag
+  *         This parameter can be any combination of the following values:
+  *            @arg  FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
+  *            @arg  FMC_FLAG_LEVEL: Interrupt level edge flag.
+  *            @arg  FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
+  *            @arg  FMC_FLAG_FEMPT: FIFO empty flag.
+  * @retval The state of FLAG (SET or RESET).
+  */
+#define __FMC_PCCARD_GET_FLAG(__INSTANCE__, __FLAG__)  (((__INSTANCE__)->SR4 &(__FLAG__)) == (__FLAG__))
+
+/**
+  * @brief  Clear flag status of the PCCARD device.
+  * @param  __INSTANCE__ FMC_PCCARD instance
+  * @param  __FLAG__ FMC_PCCARD flag
+  *         This parameter can be any combination of the following values:
+  *            @arg  FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
+  *            @arg  FMC_FLAG_LEVEL: Interrupt level edge flag.
+  *            @arg  FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
+  *            @arg  FMC_FLAG_FEMPT: FIFO empty flag.
+  * @retval None
+  */
+#define __FMC_PCCARD_CLEAR_FLAG(__INSTANCE__, __FLAG__)  ((__INSTANCE__)->SR4 &= ~(__FLAG__))
+
+/**
+  * @}
+  */
+#endif
+
+#if defined(FMC_Bank5_6)
+/** @defgroup FMC_LL_SDRAM_Interrupt FMC SDRAM Interrupt
+  * @brief macros to handle SDRAM interrupts
+  * @{
+  */
+
+/**
+  * @brief  Enable the SDRAM device interrupt.
+  * @param  __INSTANCE__  FMC_SDRAM instance
+  * @param  __INTERRUPT__ FMC_SDRAM interrupt
+  *         This parameter can be any combination of the following values:
+  *            @arg FMC_IT_REFRESH_ERROR: Interrupt refresh error
+  * @retval None
+  */
+#define __FMC_SDRAM_ENABLE_IT(__INSTANCE__, __INTERRUPT__)  ((__INSTANCE__)->SDRTR |= (__INTERRUPT__))
+
+/**
+  * @brief  Disable the SDRAM device interrupt.
+  * @param  __INSTANCE__  FMC_SDRAM instance
+  * @param  __INTERRUPT__ FMC_SDRAM interrupt
+  *         This parameter can be any combination of the following values:
+  *            @arg FMC_IT_REFRESH_ERROR: Interrupt refresh error
+  * @retval None
+  */
+#define __FMC_SDRAM_DISABLE_IT(__INSTANCE__, __INTERRUPT__)  ((__INSTANCE__)->SDRTR &= ~(__INTERRUPT__))
+
+/**
+  * @brief  Get flag status of the SDRAM device.
+  * @param  __INSTANCE__ FMC_SDRAM instance
+  * @param  __FLAG__     FMC_SDRAM flag
+  *         This parameter can be any combination of the following values:
+  *            @arg FMC_SDRAM_FLAG_REFRESH_IT: Interrupt refresh error.
+  *            @arg FMC_SDRAM_FLAG_BUSY: SDRAM busy flag.
+  *            @arg FMC_SDRAM_FLAG_REFRESH_ERROR: Refresh error flag.
+  * @retval The state of FLAG (SET or RESET).
+  */
+#define __FMC_SDRAM_GET_FLAG(__INSTANCE__, __FLAG__)  (((__INSTANCE__)->SDSR &(__FLAG__)) == (__FLAG__))
+
+/**
+  * @brief  Clear flag status of the SDRAM device.
+  * @param  __INSTANCE__ FMC_SDRAM instance
+  * @param  __FLAG__     FMC_SDRAM flag
+  *         This parameter can be any combination of the following values:
+  *           @arg FMC_SDRAM_FLAG_REFRESH_ERROR
+  * @retval None
+  */
+#define __FMC_SDRAM_CLEAR_FLAG(__INSTANCE__, __FLAG__)  ((__INSTANCE__)->SDRTR |= (__FLAG__))
+
+/**
+  * @}
+  */
+#endif /* FMC_Bank5_6 */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup FMC_LL_Private_Functions FMC LL Private Functions
+  *  @{
+  */
+
+#if defined(FMC_Bank1)
+/** @defgroup FMC_LL_NORSRAM  NOR SRAM
+  *  @{
+  */
+/** @defgroup FMC_LL_NORSRAM_Private_Functions_Group1 NOR SRAM Initialization/de-initialization functions
+  *  @{
+  */
+HAL_StatusTypeDef  FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device,
+                                    FMC_NORSRAM_InitTypeDef *Init);
+HAL_StatusTypeDef  FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device,
+                                           FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank);
+HAL_StatusTypeDef  FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device,
+                                                    FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank,
+                                                    uint32_t ExtendedMode);
+HAL_StatusTypeDef  FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device,
+                                      FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank);
+/**
+  * @}
+  */
+
+/** @defgroup FMC_LL_NORSRAM_Private_Functions_Group2 NOR SRAM Control functions
+  *  @{
+  */
+HAL_StatusTypeDef  FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank);
+HAL_StatusTypeDef  FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank);
+/**
+  * @}
+  */
+/**
+  * @}
+  */
+#endif /* FMC_Bank1 */
+
+#if defined(FMC_Bank3) || defined(FMC_Bank2_3)
+/** @defgroup FMC_LL_NAND NAND
+  *  @{
+  */
+/** @defgroup FMC_LL_NAND_Private_Functions_Group1 NAND Initialization/de-initialization functions
+  *  @{
+  */
+HAL_StatusTypeDef  FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef *Init);
+HAL_StatusTypeDef  FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device,
+                                                    FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
+HAL_StatusTypeDef  FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device,
+                                                       FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
+HAL_StatusTypeDef  FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank);
+/**
+  * @}
+  */
+
+/** @defgroup FMC_LL_NAND_Private_Functions_Group2 NAND Control functions
+  *  @{
+  */
+HAL_StatusTypeDef  FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank);
+HAL_StatusTypeDef  FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank);
+HAL_StatusTypeDef  FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank,
+                                   uint32_t Timeout);
+/**
+  * @}
+  */
+/**
+  * @}
+  */
+#endif /* FMC_Bank3) || defined(FMC_Bank2_3 */
+
+#if defined(FMC_Bank4)
+/** @defgroup FMC_LL_PCCARD PCCARD
+  *  @{
+  */
+/** @defgroup FMC_LL_PCCARD_Private_Functions_Group1 PCCARD Initialization/de-initialization functions
+  *  @{
+  */
+HAL_StatusTypeDef  FMC_PCCARD_Init(FMC_PCCARD_TypeDef *Device, FMC_PCCARD_InitTypeDef *Init);
+HAL_StatusTypeDef  FMC_PCCARD_CommonSpace_Timing_Init(FMC_PCCARD_TypeDef *Device,
+                                                               FMC_NAND_PCC_TimingTypeDef *Timing);
+HAL_StatusTypeDef  FMC_PCCARD_AttributeSpace_Timing_Init(FMC_PCCARD_TypeDef *Device,
+                                                                  FMC_NAND_PCC_TimingTypeDef *Timing);
+HAL_StatusTypeDef  FMC_PCCARD_IOSpace_Timing_Init(FMC_PCCARD_TypeDef *Device,
+                                                           FMC_NAND_PCC_TimingTypeDef *Timing);
+HAL_StatusTypeDef  FMC_PCCARD_DeInit(FMC_PCCARD_TypeDef *Device);
+/**
+  * @}
+  */
+/**
+  * @}
+  */
+#endif /* FMC_Bank4 */
+
+#if defined(FMC_Bank5_6)
+/** @defgroup FMC_LL_SDRAM SDRAM
+  *  @{
+  */
+/** @defgroup FMC_LL_SDRAM_Private_Functions_Group1 SDRAM Initialization/de-initialization functions
+  *  @{
+  */
+HAL_StatusTypeDef  FMC_SDRAM_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_InitTypeDef *Init);
+HAL_StatusTypeDef  FMC_SDRAM_Timing_Init(FMC_SDRAM_TypeDef *Device,
+                                         FMC_SDRAM_TimingTypeDef *Timing, uint32_t Bank);
+HAL_StatusTypeDef  FMC_SDRAM_DeInit(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
+/**
+  * @}
+  */
+
+/** @defgroup FMC_LL_SDRAM_Private_Functions_Group2 SDRAM Control functions
+  *  @{
+  */
+HAL_StatusTypeDef  FMC_SDRAM_WriteProtection_Enable(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
+HAL_StatusTypeDef  FMC_SDRAM_WriteProtection_Disable(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
+HAL_StatusTypeDef  FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef *Device,
+                                         FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout);
+HAL_StatusTypeDef  FMC_SDRAM_ProgramRefreshRate(FMC_SDRAM_TypeDef *Device, uint32_t RefreshRate);
+HAL_StatusTypeDef  FMC_SDRAM_SetAutoRefreshNumber(FMC_SDRAM_TypeDef *Device,
+                                                  uint32_t AutoRefreshNumber);
+uint32_t           FMC_SDRAM_GetModeStatus(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
+/**
+  * @}
+  */
+/**
+  * @}
+  */
+#endif /* FMC_Bank5_6 */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32F4xx_LL_FMC_H */
diff --git a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_gpio.h b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_gpio.h
new file mode 100644
index 0000000..9d5b34c
--- /dev/null
+++ b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_gpio.h
@@ -0,0 +1,981 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_ll_gpio.h
+  * @author  MCD Application Team
+  * @brief   Header file of GPIO LL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_LL_GPIO_H
+#define __STM32F4xx_LL_GPIO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx.h"
+
+/** @addtogroup STM32F4xx_LL_Driver
+  * @{
+  */
+
+#if defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) || defined (GPIOG) || defined (GPIOH) || defined (GPIOI) || defined (GPIOJ) || defined (GPIOK)
+
+/** @defgroup GPIO_LL GPIO
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup GPIO_LL_Private_Macros GPIO Private Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+#endif /*USE_FULL_LL_DRIVER*/
+
+/* Exported types ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup GPIO_LL_ES_INIT GPIO Exported Init structures
+  * @{
+  */
+
+/**
+  * @brief LL GPIO Init Structure definition
+  */
+typedef struct
+{
+  uint32_t Pin;          /*!< Specifies the GPIO pins to be configured.
+                              This parameter can be any value of @ref GPIO_LL_EC_PIN */
+
+  uint32_t Mode;         /*!< Specifies the operating mode for the selected pins.
+                              This parameter can be a value of @ref GPIO_LL_EC_MODE.
+
+                              GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinMode().*/
+
+  uint32_t Speed;        /*!< Specifies the speed for the selected pins.
+                              This parameter can be a value of @ref GPIO_LL_EC_SPEED.
+
+                              GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinSpeed().*/
+
+  uint32_t OutputType;   /*!< Specifies the operating output type for the selected pins.
+                              This parameter can be a value of @ref GPIO_LL_EC_OUTPUT.
+
+                              GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinOutputType().*/
+
+  uint32_t Pull;         /*!< Specifies the operating Pull-up/Pull down for the selected pins.
+                              This parameter can be a value of @ref GPIO_LL_EC_PULL.
+
+                              GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinPull().*/
+
+  uint32_t Alternate;    /*!< Specifies the Peripheral to be connected to the selected pins.
+                              This parameter can be a value of @ref GPIO_LL_EC_AF.
+
+                              GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetAFPin_0_7() and LL_GPIO_SetAFPin_8_15().*/
+} LL_GPIO_InitTypeDef;
+
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup GPIO_LL_Exported_Constants GPIO Exported Constants
+  * @{
+  */
+
+/** @defgroup GPIO_LL_EC_PIN PIN
+  * @{
+  */
+#define LL_GPIO_PIN_0                      GPIO_BSRR_BS_0 /*!< Select pin 0 */
+#define LL_GPIO_PIN_1                      GPIO_BSRR_BS_1 /*!< Select pin 1 */
+#define LL_GPIO_PIN_2                      GPIO_BSRR_BS_2 /*!< Select pin 2 */
+#define LL_GPIO_PIN_3                      GPIO_BSRR_BS_3 /*!< Select pin 3 */
+#define LL_GPIO_PIN_4                      GPIO_BSRR_BS_4 /*!< Select pin 4 */
+#define LL_GPIO_PIN_5                      GPIO_BSRR_BS_5 /*!< Select pin 5 */
+#define LL_GPIO_PIN_6                      GPIO_BSRR_BS_6 /*!< Select pin 6 */
+#define LL_GPIO_PIN_7                      GPIO_BSRR_BS_7 /*!< Select pin 7 */
+#define LL_GPIO_PIN_8                      GPIO_BSRR_BS_8 /*!< Select pin 8 */
+#define LL_GPIO_PIN_9                      GPIO_BSRR_BS_9 /*!< Select pin 9 */
+#define LL_GPIO_PIN_10                     GPIO_BSRR_BS_10 /*!< Select pin 10 */
+#define LL_GPIO_PIN_11                     GPIO_BSRR_BS_11 /*!< Select pin 11 */
+#define LL_GPIO_PIN_12                     GPIO_BSRR_BS_12 /*!< Select pin 12 */
+#define LL_GPIO_PIN_13                     GPIO_BSRR_BS_13 /*!< Select pin 13 */
+#define LL_GPIO_PIN_14                     GPIO_BSRR_BS_14 /*!< Select pin 14 */
+#define LL_GPIO_PIN_15                     GPIO_BSRR_BS_15 /*!< Select pin 15 */
+#define LL_GPIO_PIN_ALL                    (GPIO_BSRR_BS_0 | GPIO_BSRR_BS_1  | GPIO_BSRR_BS_2  | \
+                                           GPIO_BSRR_BS_3  | GPIO_BSRR_BS_4  | GPIO_BSRR_BS_5  | \
+                                           GPIO_BSRR_BS_6  | GPIO_BSRR_BS_7  | GPIO_BSRR_BS_8  | \
+                                           GPIO_BSRR_BS_9  | GPIO_BSRR_BS_10 | GPIO_BSRR_BS_11 | \
+                                           GPIO_BSRR_BS_12 | GPIO_BSRR_BS_13 | GPIO_BSRR_BS_14 | \
+                                           GPIO_BSRR_BS_15) /*!< Select all pins */
+/**
+  * @}
+  */
+
+/** @defgroup GPIO_LL_EC_MODE Mode
+  * @{
+  */
+#define LL_GPIO_MODE_INPUT                 (0x00000000U) /*!< Select input mode */
+#define LL_GPIO_MODE_OUTPUT                GPIO_MODER_MODER0_0  /*!< Select output mode */
+#define LL_GPIO_MODE_ALTERNATE             GPIO_MODER_MODER0_1  /*!< Select alternate function mode */
+#define LL_GPIO_MODE_ANALOG                GPIO_MODER_MODER0    /*!< Select analog mode */
+/**
+  * @}
+  */
+
+/** @defgroup GPIO_LL_EC_OUTPUT Output Type
+  * @{
+  */
+#define LL_GPIO_OUTPUT_PUSHPULL            (0x00000000U) /*!< Select push-pull as output type */
+#define LL_GPIO_OUTPUT_OPENDRAIN           GPIO_OTYPER_OT_0 /*!< Select open-drain as output type */
+/**
+  * @}
+  */
+
+/** @defgroup GPIO_LL_EC_SPEED Output Speed
+  * @{
+  */
+#define LL_GPIO_SPEED_FREQ_LOW             (0x00000000U) /*!< Select I/O low output speed    */
+#define LL_GPIO_SPEED_FREQ_MEDIUM          GPIO_OSPEEDER_OSPEEDR0_0 /*!< Select I/O medium output speed */
+#define LL_GPIO_SPEED_FREQ_HIGH            GPIO_OSPEEDER_OSPEEDR0_1 /*!< Select I/O fast output speed   */
+#define LL_GPIO_SPEED_FREQ_VERY_HIGH       GPIO_OSPEEDER_OSPEEDR0   /*!< Select I/O high output speed   */
+/**
+  * @}
+  */
+
+/** @defgroup GPIO_LL_EC_PULL Pull Up Pull Down
+  * @{
+  */
+#define LL_GPIO_PULL_NO                    (0x00000000U) /*!< Select I/O no pull */
+#define LL_GPIO_PULL_UP                    GPIO_PUPDR_PUPDR0_0 /*!< Select I/O pull up */
+#define LL_GPIO_PULL_DOWN                  GPIO_PUPDR_PUPDR0_1 /*!< Select I/O pull down */
+/**
+  * @}
+  */
+
+/** @defgroup GPIO_LL_EC_AF Alternate Function
+  * @{
+  */
+#define LL_GPIO_AF_0                       (0x0000000U) /*!< Select alternate function 0 */
+#define LL_GPIO_AF_1                       (0x0000001U) /*!< Select alternate function 1 */
+#define LL_GPIO_AF_2                       (0x0000002U) /*!< Select alternate function 2 */
+#define LL_GPIO_AF_3                       (0x0000003U) /*!< Select alternate function 3 */
+#define LL_GPIO_AF_4                       (0x0000004U) /*!< Select alternate function 4 */
+#define LL_GPIO_AF_5                       (0x0000005U) /*!< Select alternate function 5 */
+#define LL_GPIO_AF_6                       (0x0000006U) /*!< Select alternate function 6 */
+#define LL_GPIO_AF_7                       (0x0000007U) /*!< Select alternate function 7 */
+#define LL_GPIO_AF_8                       (0x0000008U) /*!< Select alternate function 8 */
+#define LL_GPIO_AF_9                       (0x0000009U) /*!< Select alternate function 9 */
+#define LL_GPIO_AF_10                      (0x000000AU) /*!< Select alternate function 10 */
+#define LL_GPIO_AF_11                      (0x000000BU) /*!< Select alternate function 11 */
+#define LL_GPIO_AF_12                      (0x000000CU) /*!< Select alternate function 12 */
+#define LL_GPIO_AF_13                      (0x000000DU) /*!< Select alternate function 13 */
+#define LL_GPIO_AF_14                      (0x000000EU) /*!< Select alternate function 14 */
+#define LL_GPIO_AF_15                      (0x000000FU) /*!< Select alternate function 15 */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup GPIO_LL_Exported_Macros GPIO Exported Macros
+  * @{
+  */
+
+/** @defgroup GPIO_LL_EM_WRITE_READ Common Write and read registers Macros
+  * @{
+  */
+
+/**
+  * @brief  Write a value in GPIO register
+  * @param  __INSTANCE__ GPIO Instance
+  * @param  __REG__ Register to be written
+  * @param  __VALUE__ Value to be written in the register
+  * @retval None
+  */
+#define LL_GPIO_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
+
+/**
+  * @brief  Read a value in GPIO register
+  * @param  __INSTANCE__ GPIO Instance
+  * @param  __REG__ Register to be read
+  * @retval Register value
+  */
+#define LL_GPIO_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup GPIO_LL_Exported_Functions GPIO Exported Functions
+  * @{
+  */
+
+/** @defgroup GPIO_LL_EF_Port_Configuration Port Configuration
+  * @{
+  */
+
+/**
+  * @brief  Configure gpio mode for a dedicated pin on dedicated port.
+  * @note   I/O mode can be Input mode, General purpose output, Alternate function mode or Analog.
+  * @note   Warning: only one pin can be passed as parameter.
+  * @rmtoll MODER        MODEy         LL_GPIO_SetPinMode
+  * @param  GPIOx GPIO Port
+  * @param  Pin This parameter can be one of the following values:
+  *         @arg @ref LL_GPIO_PIN_0
+  *         @arg @ref LL_GPIO_PIN_1
+  *         @arg @ref LL_GPIO_PIN_2
+  *         @arg @ref LL_GPIO_PIN_3
+  *         @arg @ref LL_GPIO_PIN_4
+  *         @arg @ref LL_GPIO_PIN_5
+  *         @arg @ref LL_GPIO_PIN_6
+  *         @arg @ref LL_GPIO_PIN_7
+  *         @arg @ref LL_GPIO_PIN_8
+  *         @arg @ref LL_GPIO_PIN_9
+  *         @arg @ref LL_GPIO_PIN_10
+  *         @arg @ref LL_GPIO_PIN_11
+  *         @arg @ref LL_GPIO_PIN_12
+  *         @arg @ref LL_GPIO_PIN_13
+  *         @arg @ref LL_GPIO_PIN_14
+  *         @arg @ref LL_GPIO_PIN_15
+  * @param  Mode This parameter can be one of the following values:
+  *         @arg @ref LL_GPIO_MODE_INPUT
+  *         @arg @ref LL_GPIO_MODE_OUTPUT
+  *         @arg @ref LL_GPIO_MODE_ALTERNATE
+  *         @arg @ref LL_GPIO_MODE_ANALOG
+  * @retval None
+  */
+__STATIC_INLINE void LL_GPIO_SetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Mode)
+{
+  MODIFY_REG(GPIOx->MODER, (GPIO_MODER_MODER0 << (POSITION_VAL(Pin) * 2U)), (Mode << (POSITION_VAL(Pin) * 2U)));
+}
+
+/**
+  * @brief  Return gpio mode for a dedicated pin on dedicated port.
+  * @note   I/O mode can be Input mode, General purpose output, Alternate function mode or Analog.
+  * @note   Warning: only one pin can be passed as parameter.
+  * @rmtoll MODER        MODEy         LL_GPIO_GetPinMode
+  * @param  GPIOx GPIO Port
+  * @param  Pin This parameter can be one of the following values:
+  *         @arg @ref LL_GPIO_PIN_0
+  *         @arg @ref LL_GPIO_PIN_1
+  *         @arg @ref LL_GPIO_PIN_2
+  *         @arg @ref LL_GPIO_PIN_3
+  *         @arg @ref LL_GPIO_PIN_4
+  *         @arg @ref LL_GPIO_PIN_5
+  *         @arg @ref LL_GPIO_PIN_6
+  *         @arg @ref LL_GPIO_PIN_7
+  *         @arg @ref LL_GPIO_PIN_8
+  *         @arg @ref LL_GPIO_PIN_9
+  *         @arg @ref LL_GPIO_PIN_10
+  *         @arg @ref LL_GPIO_PIN_11
+  *         @arg @ref LL_GPIO_PIN_12
+  *         @arg @ref LL_GPIO_PIN_13
+  *         @arg @ref LL_GPIO_PIN_14
+  *         @arg @ref LL_GPIO_PIN_15
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_GPIO_MODE_INPUT
+  *         @arg @ref LL_GPIO_MODE_OUTPUT
+  *         @arg @ref LL_GPIO_MODE_ALTERNATE
+  *         @arg @ref LL_GPIO_MODE_ANALOG
+  */
+__STATIC_INLINE uint32_t LL_GPIO_GetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin)
+{
+  return (uint32_t)(READ_BIT(GPIOx->MODER,
+                             (GPIO_MODER_MODER0 << (POSITION_VAL(Pin) * 2U))) >> (POSITION_VAL(Pin) * 2U));
+}
+
+/**
+  * @brief  Configure gpio output type for several pins on dedicated port.
+  * @note   Output type as to be set when gpio pin is in output or
+  *         alternate modes. Possible type are Push-pull or Open-drain.
+  * @rmtoll OTYPER       OTy           LL_GPIO_SetPinOutputType
+  * @param  GPIOx GPIO Port
+  * @param  PinMask This parameter can be a combination of the following values:
+  *         @arg @ref LL_GPIO_PIN_0
+  *         @arg @ref LL_GPIO_PIN_1
+  *         @arg @ref LL_GPIO_PIN_2
+  *         @arg @ref LL_GPIO_PIN_3
+  *         @arg @ref LL_GPIO_PIN_4
+  *         @arg @ref LL_GPIO_PIN_5
+  *         @arg @ref LL_GPIO_PIN_6
+  *         @arg @ref LL_GPIO_PIN_7
+  *         @arg @ref LL_GPIO_PIN_8
+  *         @arg @ref LL_GPIO_PIN_9
+  *         @arg @ref LL_GPIO_PIN_10
+  *         @arg @ref LL_GPIO_PIN_11
+  *         @arg @ref LL_GPIO_PIN_12
+  *         @arg @ref LL_GPIO_PIN_13
+  *         @arg @ref LL_GPIO_PIN_14
+  *         @arg @ref LL_GPIO_PIN_15
+  *         @arg @ref LL_GPIO_PIN_ALL
+  * @param  OutputType This parameter can be one of the following values:
+  *         @arg @ref LL_GPIO_OUTPUT_PUSHPULL
+  *         @arg @ref LL_GPIO_OUTPUT_OPENDRAIN
+  * @retval None
+  */
+__STATIC_INLINE void LL_GPIO_SetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t PinMask, uint32_t OutputType)
+{
+  MODIFY_REG(GPIOx->OTYPER, PinMask, (PinMask * OutputType));
+}
+
+/**
+  * @brief  Return gpio output type for several pins on dedicated port.
+  * @note   Output type as to be set when gpio pin is in output or
+  *         alternate modes. Possible type are Push-pull or Open-drain.
+  * @note   Warning: only one pin can be passed as parameter.
+  * @rmtoll OTYPER       OTy           LL_GPIO_GetPinOutputType
+  * @param  GPIOx GPIO Port
+  * @param  Pin This parameter can be one of the following values:
+  *         @arg @ref LL_GPIO_PIN_0
+  *         @arg @ref LL_GPIO_PIN_1
+  *         @arg @ref LL_GPIO_PIN_2
+  *         @arg @ref LL_GPIO_PIN_3
+  *         @arg @ref LL_GPIO_PIN_4
+  *         @arg @ref LL_GPIO_PIN_5
+  *         @arg @ref LL_GPIO_PIN_6
+  *         @arg @ref LL_GPIO_PIN_7
+  *         @arg @ref LL_GPIO_PIN_8
+  *         @arg @ref LL_GPIO_PIN_9
+  *         @arg @ref LL_GPIO_PIN_10
+  *         @arg @ref LL_GPIO_PIN_11
+  *         @arg @ref LL_GPIO_PIN_12
+  *         @arg @ref LL_GPIO_PIN_13
+  *         @arg @ref LL_GPIO_PIN_14
+  *         @arg @ref LL_GPIO_PIN_15
+  *         @arg @ref LL_GPIO_PIN_ALL
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_GPIO_OUTPUT_PUSHPULL
+  *         @arg @ref LL_GPIO_OUTPUT_OPENDRAIN
+  */
+__STATIC_INLINE uint32_t LL_GPIO_GetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t Pin)
+{
+  return (uint32_t)(READ_BIT(GPIOx->OTYPER, Pin) >> POSITION_VAL(Pin));
+}
+
+/**
+  * @brief  Configure gpio speed for a dedicated pin on dedicated port.
+  * @note   I/O speed can be Low, Medium, Fast or High speed.
+  * @note   Warning: only one pin can be passed as parameter.
+  * @note   Refer to datasheet for frequency specifications and the power
+  *         supply and load conditions for each speed.
+  * @rmtoll OSPEEDR      OSPEEDy       LL_GPIO_SetPinSpeed
+  * @param  GPIOx GPIO Port
+  * @param  Pin This parameter can be one of the following values:
+  *         @arg @ref LL_GPIO_PIN_0
+  *         @arg @ref LL_GPIO_PIN_1
+  *         @arg @ref LL_GPIO_PIN_2
+  *         @arg @ref LL_GPIO_PIN_3
+  *         @arg @ref LL_GPIO_PIN_4
+  *         @arg @ref LL_GPIO_PIN_5
+  *         @arg @ref LL_GPIO_PIN_6
+  *         @arg @ref LL_GPIO_PIN_7
+  *         @arg @ref LL_GPIO_PIN_8
+  *         @arg @ref LL_GPIO_PIN_9
+  *         @arg @ref LL_GPIO_PIN_10
+  *         @arg @ref LL_GPIO_PIN_11
+  *         @arg @ref LL_GPIO_PIN_12
+  *         @arg @ref LL_GPIO_PIN_13
+  *         @arg @ref LL_GPIO_PIN_14
+  *         @arg @ref LL_GPIO_PIN_15
+  * @param  Speed This parameter can be one of the following values:
+  *         @arg @ref LL_GPIO_SPEED_FREQ_LOW
+  *         @arg @ref LL_GPIO_SPEED_FREQ_MEDIUM
+  *         @arg @ref LL_GPIO_SPEED_FREQ_HIGH
+  *         @arg @ref LL_GPIO_SPEED_FREQ_VERY_HIGH
+  * @retval None
+  */
+__STATIC_INLINE void LL_GPIO_SetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t  Speed)
+{
+  MODIFY_REG(GPIOx->OSPEEDR, (GPIO_OSPEEDER_OSPEEDR0 << (POSITION_VAL(Pin) * 2U)),
+             (Speed << (POSITION_VAL(Pin) * 2U)));
+}
+
+/**
+  * @brief  Return gpio speed for a dedicated pin on dedicated port.
+  * @note   I/O speed can be Low, Medium, Fast or High speed.
+  * @note   Warning: only one pin can be passed as parameter.
+  * @note   Refer to datasheet for frequency specifications and the power
+  *         supply and load conditions for each speed.
+  * @rmtoll OSPEEDR      OSPEEDy       LL_GPIO_GetPinSpeed
+  * @param  GPIOx GPIO Port
+  * @param  Pin This parameter can be one of the following values:
+  *         @arg @ref LL_GPIO_PIN_0
+  *         @arg @ref LL_GPIO_PIN_1
+  *         @arg @ref LL_GPIO_PIN_2
+  *         @arg @ref LL_GPIO_PIN_3
+  *         @arg @ref LL_GPIO_PIN_4
+  *         @arg @ref LL_GPIO_PIN_5
+  *         @arg @ref LL_GPIO_PIN_6
+  *         @arg @ref LL_GPIO_PIN_7
+  *         @arg @ref LL_GPIO_PIN_8
+  *         @arg @ref LL_GPIO_PIN_9
+  *         @arg @ref LL_GPIO_PIN_10
+  *         @arg @ref LL_GPIO_PIN_11
+  *         @arg @ref LL_GPIO_PIN_12
+  *         @arg @ref LL_GPIO_PIN_13
+  *         @arg @ref LL_GPIO_PIN_14
+  *         @arg @ref LL_GPIO_PIN_15
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_GPIO_SPEED_FREQ_LOW
+  *         @arg @ref LL_GPIO_SPEED_FREQ_MEDIUM
+  *         @arg @ref LL_GPIO_SPEED_FREQ_HIGH
+  *         @arg @ref LL_GPIO_SPEED_FREQ_VERY_HIGH
+  */
+__STATIC_INLINE uint32_t LL_GPIO_GetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin)
+{
+  return (uint32_t)(READ_BIT(GPIOx->OSPEEDR,
+                             (GPIO_OSPEEDER_OSPEEDR0 << (POSITION_VAL(Pin) * 2U))) >> (POSITION_VAL(Pin) * 2U));
+}
+
+/**
+  * @brief  Configure gpio pull-up or pull-down for a dedicated pin on a dedicated port.
+  * @note   Warning: only one pin can be passed as parameter.
+  * @rmtoll PUPDR        PUPDy         LL_GPIO_SetPinPull
+  * @param  GPIOx GPIO Port
+  * @param  Pin This parameter can be one of the following values:
+  *         @arg @ref LL_GPIO_PIN_0
+  *         @arg @ref LL_GPIO_PIN_1
+  *         @arg @ref LL_GPIO_PIN_2
+  *         @arg @ref LL_GPIO_PIN_3
+  *         @arg @ref LL_GPIO_PIN_4
+  *         @arg @ref LL_GPIO_PIN_5
+  *         @arg @ref LL_GPIO_PIN_6
+  *         @arg @ref LL_GPIO_PIN_7
+  *         @arg @ref LL_GPIO_PIN_8
+  *         @arg @ref LL_GPIO_PIN_9
+  *         @arg @ref LL_GPIO_PIN_10
+  *         @arg @ref LL_GPIO_PIN_11
+  *         @arg @ref LL_GPIO_PIN_12
+  *         @arg @ref LL_GPIO_PIN_13
+  *         @arg @ref LL_GPIO_PIN_14
+  *         @arg @ref LL_GPIO_PIN_15
+  * @param  Pull This parameter can be one of the following values:
+  *         @arg @ref LL_GPIO_PULL_NO
+  *         @arg @ref LL_GPIO_PULL_UP
+  *         @arg @ref LL_GPIO_PULL_DOWN
+  * @retval None
+  */
+__STATIC_INLINE void LL_GPIO_SetPinPull(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Pull)
+{
+  MODIFY_REG(GPIOx->PUPDR, (GPIO_PUPDR_PUPDR0 << (POSITION_VAL(Pin) * 2U)), (Pull << (POSITION_VAL(Pin) * 2U)));
+}
+
+/**
+  * @brief  Return gpio pull-up or pull-down for a dedicated pin on a dedicated port
+  * @note   Warning: only one pin can be passed as parameter.
+  * @rmtoll PUPDR        PUPDy         LL_GPIO_GetPinPull
+  * @param  GPIOx GPIO Port
+  * @param  Pin This parameter can be one of the following values:
+  *         @arg @ref LL_GPIO_PIN_0
+  *         @arg @ref LL_GPIO_PIN_1
+  *         @arg @ref LL_GPIO_PIN_2
+  *         @arg @ref LL_GPIO_PIN_3
+  *         @arg @ref LL_GPIO_PIN_4
+  *         @arg @ref LL_GPIO_PIN_5
+  *         @arg @ref LL_GPIO_PIN_6
+  *         @arg @ref LL_GPIO_PIN_7
+  *         @arg @ref LL_GPIO_PIN_8
+  *         @arg @ref LL_GPIO_PIN_9
+  *         @arg @ref LL_GPIO_PIN_10
+  *         @arg @ref LL_GPIO_PIN_11
+  *         @arg @ref LL_GPIO_PIN_12
+  *         @arg @ref LL_GPIO_PIN_13
+  *         @arg @ref LL_GPIO_PIN_14
+  *         @arg @ref LL_GPIO_PIN_15
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_GPIO_PULL_NO
+  *         @arg @ref LL_GPIO_PULL_UP
+  *         @arg @ref LL_GPIO_PULL_DOWN
+  */
+__STATIC_INLINE uint32_t LL_GPIO_GetPinPull(GPIO_TypeDef *GPIOx, uint32_t Pin)
+{
+  return (uint32_t)(READ_BIT(GPIOx->PUPDR,
+                             (GPIO_PUPDR_PUPDR0 << (POSITION_VAL(Pin) * 2U))) >> (POSITION_VAL(Pin) * 2U));
+}
+
+/**
+  * @brief  Configure gpio alternate function of a dedicated pin from 0 to 7 for a dedicated port.
+  * @note   Possible values are from AF0 to AF15 depending on target.
+  * @note   Warning: only one pin can be passed as parameter.
+  * @rmtoll AFRL         AFSELy        LL_GPIO_SetAFPin_0_7
+  * @param  GPIOx GPIO Port
+  * @param  Pin This parameter can be one of the following values:
+  *         @arg @ref LL_GPIO_PIN_0
+  *         @arg @ref LL_GPIO_PIN_1
+  *         @arg @ref LL_GPIO_PIN_2
+  *         @arg @ref LL_GPIO_PIN_3
+  *         @arg @ref LL_GPIO_PIN_4
+  *         @arg @ref LL_GPIO_PIN_5
+  *         @arg @ref LL_GPIO_PIN_6
+  *         @arg @ref LL_GPIO_PIN_7
+  * @param  Alternate This parameter can be one of the following values:
+  *         @arg @ref LL_GPIO_AF_0
+  *         @arg @ref LL_GPIO_AF_1
+  *         @arg @ref LL_GPIO_AF_2
+  *         @arg @ref LL_GPIO_AF_3
+  *         @arg @ref LL_GPIO_AF_4
+  *         @arg @ref LL_GPIO_AF_5
+  *         @arg @ref LL_GPIO_AF_6
+  *         @arg @ref LL_GPIO_AF_7
+  *         @arg @ref LL_GPIO_AF_8
+  *         @arg @ref LL_GPIO_AF_9
+  *         @arg @ref LL_GPIO_AF_10
+  *         @arg @ref LL_GPIO_AF_11
+  *         @arg @ref LL_GPIO_AF_12
+  *         @arg @ref LL_GPIO_AF_13
+  *         @arg @ref LL_GPIO_AF_14
+  *         @arg @ref LL_GPIO_AF_15
+  * @retval None
+  */
+__STATIC_INLINE void LL_GPIO_SetAFPin_0_7(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Alternate)
+{
+  MODIFY_REG(GPIOx->AFR[0], (GPIO_AFRL_AFSEL0 << (POSITION_VAL(Pin) * 4U)),
+             (Alternate << (POSITION_VAL(Pin) * 4U)));
+}
+
+/**
+  * @brief  Return gpio alternate function of a dedicated pin from 0 to 7 for a dedicated port.
+  * @rmtoll AFRL         AFSELy        LL_GPIO_GetAFPin_0_7
+  * @param  GPIOx GPIO Port
+  * @param  Pin This parameter can be one of the following values:
+  *         @arg @ref LL_GPIO_PIN_0
+  *         @arg @ref LL_GPIO_PIN_1
+  *         @arg @ref LL_GPIO_PIN_2
+  *         @arg @ref LL_GPIO_PIN_3
+  *         @arg @ref LL_GPIO_PIN_4
+  *         @arg @ref LL_GPIO_PIN_5
+  *         @arg @ref LL_GPIO_PIN_6
+  *         @arg @ref LL_GPIO_PIN_7
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_GPIO_AF_0
+  *         @arg @ref LL_GPIO_AF_1
+  *         @arg @ref LL_GPIO_AF_2
+  *         @arg @ref LL_GPIO_AF_3
+  *         @arg @ref LL_GPIO_AF_4
+  *         @arg @ref LL_GPIO_AF_5
+  *         @arg @ref LL_GPIO_AF_6
+  *         @arg @ref LL_GPIO_AF_7
+  *         @arg @ref LL_GPIO_AF_8
+  *         @arg @ref LL_GPIO_AF_9
+  *         @arg @ref LL_GPIO_AF_10
+  *         @arg @ref LL_GPIO_AF_11
+  *         @arg @ref LL_GPIO_AF_12
+  *         @arg @ref LL_GPIO_AF_13
+  *         @arg @ref LL_GPIO_AF_14
+  *         @arg @ref LL_GPIO_AF_15
+  */
+__STATIC_INLINE uint32_t LL_GPIO_GetAFPin_0_7(GPIO_TypeDef *GPIOx, uint32_t Pin)
+{
+  return (uint32_t)(READ_BIT(GPIOx->AFR[0],
+                             (GPIO_AFRL_AFSEL0 << (POSITION_VAL(Pin) * 4U))) >> (POSITION_VAL(Pin) * 4U));
+}
+
+/**
+  * @brief  Configure gpio alternate function of a dedicated pin from 8 to 15 for a dedicated port.
+  * @note   Possible values are from AF0 to AF15 depending on target.
+  * @note   Warning: only one pin can be passed as parameter.
+  * @rmtoll AFRH         AFSELy        LL_GPIO_SetAFPin_8_15
+  * @param  GPIOx GPIO Port
+  * @param  Pin This parameter can be one of the following values:
+  *         @arg @ref LL_GPIO_PIN_8
+  *         @arg @ref LL_GPIO_PIN_9
+  *         @arg @ref LL_GPIO_PIN_10
+  *         @arg @ref LL_GPIO_PIN_11
+  *         @arg @ref LL_GPIO_PIN_12
+  *         @arg @ref LL_GPIO_PIN_13
+  *         @arg @ref LL_GPIO_PIN_14
+  *         @arg @ref LL_GPIO_PIN_15
+  * @param  Alternate This parameter can be one of the following values:
+  *         @arg @ref LL_GPIO_AF_0
+  *         @arg @ref LL_GPIO_AF_1
+  *         @arg @ref LL_GPIO_AF_2
+  *         @arg @ref LL_GPIO_AF_3
+  *         @arg @ref LL_GPIO_AF_4
+  *         @arg @ref LL_GPIO_AF_5
+  *         @arg @ref LL_GPIO_AF_6
+  *         @arg @ref LL_GPIO_AF_7
+  *         @arg @ref LL_GPIO_AF_8
+  *         @arg @ref LL_GPIO_AF_9
+  *         @arg @ref LL_GPIO_AF_10
+  *         @arg @ref LL_GPIO_AF_11
+  *         @arg @ref LL_GPIO_AF_12
+  *         @arg @ref LL_GPIO_AF_13
+  *         @arg @ref LL_GPIO_AF_14
+  *         @arg @ref LL_GPIO_AF_15
+  * @retval None
+  */
+__STATIC_INLINE void LL_GPIO_SetAFPin_8_15(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Alternate)
+{
+  MODIFY_REG(GPIOx->AFR[1], (GPIO_AFRH_AFSEL8 << (POSITION_VAL(Pin >> 8U) * 4U)),
+             (Alternate << (POSITION_VAL(Pin >> 8U) * 4U)));
+}
+
+/**
+  * @brief  Return gpio alternate function of a dedicated pin from 8 to 15 for a dedicated port.
+  * @note   Possible values are from AF0 to AF15 depending on target.
+  * @rmtoll AFRH         AFSELy        LL_GPIO_GetAFPin_8_15
+  * @param  GPIOx GPIO Port
+  * @param  Pin This parameter can be one of the following values:
+  *         @arg @ref LL_GPIO_PIN_8
+  *         @arg @ref LL_GPIO_PIN_9
+  *         @arg @ref LL_GPIO_PIN_10
+  *         @arg @ref LL_GPIO_PIN_11
+  *         @arg @ref LL_GPIO_PIN_12
+  *         @arg @ref LL_GPIO_PIN_13
+  *         @arg @ref LL_GPIO_PIN_14
+  *         @arg @ref LL_GPIO_PIN_15
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_GPIO_AF_0
+  *         @arg @ref LL_GPIO_AF_1
+  *         @arg @ref LL_GPIO_AF_2
+  *         @arg @ref LL_GPIO_AF_3
+  *         @arg @ref LL_GPIO_AF_4
+  *         @arg @ref LL_GPIO_AF_5
+  *         @arg @ref LL_GPIO_AF_6
+  *         @arg @ref LL_GPIO_AF_7
+  *         @arg @ref LL_GPIO_AF_8
+  *         @arg @ref LL_GPIO_AF_9
+  *         @arg @ref LL_GPIO_AF_10
+  *         @arg @ref LL_GPIO_AF_11
+  *         @arg @ref LL_GPIO_AF_12
+  *         @arg @ref LL_GPIO_AF_13
+  *         @arg @ref LL_GPIO_AF_14
+  *         @arg @ref LL_GPIO_AF_15
+  */
+__STATIC_INLINE uint32_t LL_GPIO_GetAFPin_8_15(GPIO_TypeDef *GPIOx, uint32_t Pin)
+{
+  return (uint32_t)(READ_BIT(GPIOx->AFR[1],
+                             (GPIO_AFRH_AFSEL8 << (POSITION_VAL(Pin >> 8U) * 4U))) >> (POSITION_VAL(Pin >> 8U) * 4U));
+}
+
+
+/**
+  * @brief  Lock configuration of several pins for a dedicated port.
+  * @note   When the lock sequence has been applied on a port bit, the
+  *         value of this port bit can no longer be modified until the
+  *         next reset.
+  * @note   Each lock bit freezes a specific configuration register
+  *         (control and alternate function registers).
+  * @rmtoll LCKR         LCKK          LL_GPIO_LockPin
+  * @param  GPIOx GPIO Port
+  * @param  PinMask This parameter can be a combination of the following values:
+  *         @arg @ref LL_GPIO_PIN_0
+  *         @arg @ref LL_GPIO_PIN_1
+  *         @arg @ref LL_GPIO_PIN_2
+  *         @arg @ref LL_GPIO_PIN_3
+  *         @arg @ref LL_GPIO_PIN_4
+  *         @arg @ref LL_GPIO_PIN_5
+  *         @arg @ref LL_GPIO_PIN_6
+  *         @arg @ref LL_GPIO_PIN_7
+  *         @arg @ref LL_GPIO_PIN_8
+  *         @arg @ref LL_GPIO_PIN_9
+  *         @arg @ref LL_GPIO_PIN_10
+  *         @arg @ref LL_GPIO_PIN_11
+  *         @arg @ref LL_GPIO_PIN_12
+  *         @arg @ref LL_GPIO_PIN_13
+  *         @arg @ref LL_GPIO_PIN_14
+  *         @arg @ref LL_GPIO_PIN_15
+  *         @arg @ref LL_GPIO_PIN_ALL
+  * @retval None
+  */
+__STATIC_INLINE void LL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
+{
+  __IO uint32_t temp;
+  WRITE_REG(GPIOx->LCKR, GPIO_LCKR_LCKK | PinMask);
+  WRITE_REG(GPIOx->LCKR, PinMask);
+  WRITE_REG(GPIOx->LCKR, GPIO_LCKR_LCKK | PinMask);
+  temp = READ_REG(GPIOx->LCKR);
+  (void) temp;
+}
+
+/**
+  * @brief  Return 1 if all pins passed as parameter, of a dedicated port, are locked. else Return 0.
+  * @rmtoll LCKR         LCKy          LL_GPIO_IsPinLocked
+  * @param  GPIOx GPIO Port
+  * @param  PinMask This parameter can be a combination of the following values:
+  *         @arg @ref LL_GPIO_PIN_0
+  *         @arg @ref LL_GPIO_PIN_1
+  *         @arg @ref LL_GPIO_PIN_2
+  *         @arg @ref LL_GPIO_PIN_3
+  *         @arg @ref LL_GPIO_PIN_4
+  *         @arg @ref LL_GPIO_PIN_5
+  *         @arg @ref LL_GPIO_PIN_6
+  *         @arg @ref LL_GPIO_PIN_7
+  *         @arg @ref LL_GPIO_PIN_8
+  *         @arg @ref LL_GPIO_PIN_9
+  *         @arg @ref LL_GPIO_PIN_10
+  *         @arg @ref LL_GPIO_PIN_11
+  *         @arg @ref LL_GPIO_PIN_12
+  *         @arg @ref LL_GPIO_PIN_13
+  *         @arg @ref LL_GPIO_PIN_14
+  *         @arg @ref LL_GPIO_PIN_15
+  *         @arg @ref LL_GPIO_PIN_ALL
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_GPIO_IsPinLocked(GPIO_TypeDef *GPIOx, uint32_t PinMask)
+{
+  return (READ_BIT(GPIOx->LCKR, PinMask) == (PinMask));
+}
+
+/**
+  * @brief  Return 1 if one of the pin of a dedicated port is locked. else return 0.
+  * @rmtoll LCKR         LCKK          LL_GPIO_IsAnyPinLocked
+  * @param  GPIOx GPIO Port
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_GPIO_IsAnyPinLocked(GPIO_TypeDef *GPIOx)
+{
+  return (READ_BIT(GPIOx->LCKR, GPIO_LCKR_LCKK) == (GPIO_LCKR_LCKK));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup GPIO_LL_EF_Data_Access Data Access
+  * @{
+  */
+
+/**
+  * @brief  Return full input data register value for a dedicated port.
+  * @rmtoll IDR          IDy           LL_GPIO_ReadInputPort
+  * @param  GPIOx GPIO Port
+  * @retval Input data register value of port
+  */
+__STATIC_INLINE uint32_t LL_GPIO_ReadInputPort(GPIO_TypeDef *GPIOx)
+{
+  return (uint32_t)(READ_REG(GPIOx->IDR));
+}
+
+/**
+  * @brief  Return if input data level for several pins of dedicated port is high or low.
+  * @rmtoll IDR          IDy           LL_GPIO_IsInputPinSet
+  * @param  GPIOx GPIO Port
+  * @param  PinMask This parameter can be a combination of the following values:
+  *         @arg @ref LL_GPIO_PIN_0
+  *         @arg @ref LL_GPIO_PIN_1
+  *         @arg @ref LL_GPIO_PIN_2
+  *         @arg @ref LL_GPIO_PIN_3
+  *         @arg @ref LL_GPIO_PIN_4
+  *         @arg @ref LL_GPIO_PIN_5
+  *         @arg @ref LL_GPIO_PIN_6
+  *         @arg @ref LL_GPIO_PIN_7
+  *         @arg @ref LL_GPIO_PIN_8
+  *         @arg @ref LL_GPIO_PIN_9
+  *         @arg @ref LL_GPIO_PIN_10
+  *         @arg @ref LL_GPIO_PIN_11
+  *         @arg @ref LL_GPIO_PIN_12
+  *         @arg @ref LL_GPIO_PIN_13
+  *         @arg @ref LL_GPIO_PIN_14
+  *         @arg @ref LL_GPIO_PIN_15
+  *         @arg @ref LL_GPIO_PIN_ALL
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_GPIO_IsInputPinSet(GPIO_TypeDef *GPIOx, uint32_t PinMask)
+{
+  return (READ_BIT(GPIOx->IDR, PinMask) == (PinMask));
+}
+
+/**
+  * @brief  Write output data register for the port.
+  * @rmtoll ODR          ODy           LL_GPIO_WriteOutputPort
+  * @param  GPIOx GPIO Port
+  * @param  PortValue Level value for each pin of the port
+  * @retval None
+  */
+__STATIC_INLINE void LL_GPIO_WriteOutputPort(GPIO_TypeDef *GPIOx, uint32_t PortValue)
+{
+  WRITE_REG(GPIOx->ODR, PortValue);
+}
+
+/**
+  * @brief  Return full output data register value for a dedicated port.
+  * @rmtoll ODR          ODy           LL_GPIO_ReadOutputPort
+  * @param  GPIOx GPIO Port
+  * @retval Output data register value of port
+  */
+__STATIC_INLINE uint32_t LL_GPIO_ReadOutputPort(GPIO_TypeDef *GPIOx)
+{
+  return (uint32_t)(READ_REG(GPIOx->ODR));
+}
+
+/**
+  * @brief  Return if input data level for several pins of dedicated port is high or low.
+  * @rmtoll ODR          ODy           LL_GPIO_IsOutputPinSet
+  * @param  GPIOx GPIO Port
+  * @param  PinMask This parameter can be a combination of the following values:
+  *         @arg @ref LL_GPIO_PIN_0
+  *         @arg @ref LL_GPIO_PIN_1
+  *         @arg @ref LL_GPIO_PIN_2
+  *         @arg @ref LL_GPIO_PIN_3
+  *         @arg @ref LL_GPIO_PIN_4
+  *         @arg @ref LL_GPIO_PIN_5
+  *         @arg @ref LL_GPIO_PIN_6
+  *         @arg @ref LL_GPIO_PIN_7
+  *         @arg @ref LL_GPIO_PIN_8
+  *         @arg @ref LL_GPIO_PIN_9
+  *         @arg @ref LL_GPIO_PIN_10
+  *         @arg @ref LL_GPIO_PIN_11
+  *         @arg @ref LL_GPIO_PIN_12
+  *         @arg @ref LL_GPIO_PIN_13
+  *         @arg @ref LL_GPIO_PIN_14
+  *         @arg @ref LL_GPIO_PIN_15
+  *         @arg @ref LL_GPIO_PIN_ALL
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_GPIO_IsOutputPinSet(GPIO_TypeDef *GPIOx, uint32_t PinMask)
+{
+  return (READ_BIT(GPIOx->ODR, PinMask) == (PinMask));
+}
+
+/**
+  * @brief  Set several pins to high level on dedicated gpio port.
+  * @rmtoll BSRR         BSy           LL_GPIO_SetOutputPin
+  * @param  GPIOx GPIO Port
+  * @param  PinMask This parameter can be a combination of the following values:
+  *         @arg @ref LL_GPIO_PIN_0
+  *         @arg @ref LL_GPIO_PIN_1
+  *         @arg @ref LL_GPIO_PIN_2
+  *         @arg @ref LL_GPIO_PIN_3
+  *         @arg @ref LL_GPIO_PIN_4
+  *         @arg @ref LL_GPIO_PIN_5
+  *         @arg @ref LL_GPIO_PIN_6
+  *         @arg @ref LL_GPIO_PIN_7
+  *         @arg @ref LL_GPIO_PIN_8
+  *         @arg @ref LL_GPIO_PIN_9
+  *         @arg @ref LL_GPIO_PIN_10
+  *         @arg @ref LL_GPIO_PIN_11
+  *         @arg @ref LL_GPIO_PIN_12
+  *         @arg @ref LL_GPIO_PIN_13
+  *         @arg @ref LL_GPIO_PIN_14
+  *         @arg @ref LL_GPIO_PIN_15
+  *         @arg @ref LL_GPIO_PIN_ALL
+  * @retval None
+  */
+__STATIC_INLINE void LL_GPIO_SetOutputPin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
+{
+  WRITE_REG(GPIOx->BSRR, PinMask);
+}
+
+/**
+  * @brief  Set several pins to low level on dedicated gpio port.
+  * @rmtoll BSRR         BRy           LL_GPIO_ResetOutputPin
+  * @param  GPIOx GPIO Port
+  * @param  PinMask This parameter can be a combination of the following values:
+  *         @arg @ref LL_GPIO_PIN_0
+  *         @arg @ref LL_GPIO_PIN_1
+  *         @arg @ref LL_GPIO_PIN_2
+  *         @arg @ref LL_GPIO_PIN_3
+  *         @arg @ref LL_GPIO_PIN_4
+  *         @arg @ref LL_GPIO_PIN_5
+  *         @arg @ref LL_GPIO_PIN_6
+  *         @arg @ref LL_GPIO_PIN_7
+  *         @arg @ref LL_GPIO_PIN_8
+  *         @arg @ref LL_GPIO_PIN_9
+  *         @arg @ref LL_GPIO_PIN_10
+  *         @arg @ref LL_GPIO_PIN_11
+  *         @arg @ref LL_GPIO_PIN_12
+  *         @arg @ref LL_GPIO_PIN_13
+  *         @arg @ref LL_GPIO_PIN_14
+  *         @arg @ref LL_GPIO_PIN_15
+  *         @arg @ref LL_GPIO_PIN_ALL
+  * @retval None
+  */
+__STATIC_INLINE void LL_GPIO_ResetOutputPin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
+{
+  WRITE_REG(GPIOx->BSRR, (PinMask << 16));
+}
+
+/**
+  * @brief  Toggle data value for several pin of dedicated port.
+  * @rmtoll ODR          ODy           LL_GPIO_TogglePin
+  * @param  GPIOx GPIO Port
+  * @param  PinMask This parameter can be a combination of the following values:
+  *         @arg @ref LL_GPIO_PIN_0
+  *         @arg @ref LL_GPIO_PIN_1
+  *         @arg @ref LL_GPIO_PIN_2
+  *         @arg @ref LL_GPIO_PIN_3
+  *         @arg @ref LL_GPIO_PIN_4
+  *         @arg @ref LL_GPIO_PIN_5
+  *         @arg @ref LL_GPIO_PIN_6
+  *         @arg @ref LL_GPIO_PIN_7
+  *         @arg @ref LL_GPIO_PIN_8
+  *         @arg @ref LL_GPIO_PIN_9
+  *         @arg @ref LL_GPIO_PIN_10
+  *         @arg @ref LL_GPIO_PIN_11
+  *         @arg @ref LL_GPIO_PIN_12
+  *         @arg @ref LL_GPIO_PIN_13
+  *         @arg @ref LL_GPIO_PIN_14
+  *         @arg @ref LL_GPIO_PIN_15
+  *         @arg @ref LL_GPIO_PIN_ALL
+  * @retval None
+  */
+__STATIC_INLINE void LL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
+{
+  uint32_t odr = READ_REG(GPIOx->ODR);
+  WRITE_REG(GPIOx->BSRR, ((odr & PinMask) << 16u) | (~odr & PinMask));
+}
+
+/**
+  * @}
+  */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup GPIO_LL_EF_Init Initialization and de-initialization functions
+  * @{
+  */
+
+ErrorStatus LL_GPIO_DeInit(GPIO_TypeDef *GPIOx);
+ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStruct);
+void        LL_GPIO_StructInit(LL_GPIO_InitTypeDef *GPIO_InitStruct);
+
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) || defined (GPIOG) || defined (GPIOH) || defined (GPIOI) || defined (GPIOJ) || defined (GPIOK) */
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_LL_GPIO_H */
+
diff --git a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_i2c.h b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_i2c.h
new file mode 100644
index 0000000..2ef20f7
--- /dev/null
+++ b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_i2c.h
@@ -0,0 +1,1890 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_ll_i2c.h
+  * @author  MCD Application Team
+  * @brief   Header file of I2C LL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2016 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_LL_I2C_H
+#define __STM32F4xx_LL_I2C_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx.h"
+
+/** @addtogroup STM32F4xx_LL_Driver
+  * @{
+  */
+
+#if defined (I2C1) || defined (I2C2) || defined (I2C3)
+
+/** @defgroup I2C_LL I2C
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup I2C_LL_Private_Constants I2C Private Constants
+  * @{
+  */
+
+/* Defines used to perform compute and check in the macros */
+#define LL_I2C_MAX_SPEED_STANDARD           100000U
+#define LL_I2C_MAX_SPEED_FAST               400000U
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup I2C_LL_Private_Macros I2C Private Macros
+  * @{
+  */
+/**
+  * @}
+  */
+#endif /*USE_FULL_LL_DRIVER*/
+
+/* Exported types ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup I2C_LL_ES_INIT I2C Exported Init structure
+  * @{
+  */
+typedef struct
+{
+  uint32_t PeripheralMode;      /*!< Specifies the peripheral mode.
+                                     This parameter can be a value of @ref I2C_LL_EC_PERIPHERAL_MODE
+
+                                     This feature can be modified afterwards using unitary function @ref LL_I2C_SetMode(). */
+
+  uint32_t ClockSpeed;          /*!< Specifies the clock frequency.
+                                     This parameter must be set to a value lower than 400kHz (in Hz)
+
+                                     This feature can be modified afterwards using unitary function @ref LL_I2C_SetClockPeriod()
+                                     or @ref LL_I2C_SetDutyCycle() or @ref LL_I2C_SetClockSpeedMode() or @ref LL_I2C_ConfigSpeed(). */
+
+  uint32_t DutyCycle;           /*!< Specifies the I2C fast mode duty cycle.
+                                     This parameter can be a value of @ref I2C_LL_EC_DUTYCYCLE
+
+                                     This feature can be modified afterwards using unitary function @ref LL_I2C_SetDutyCycle(). */
+
+#if  defined(I2C_FLTR_ANOFF)&&defined(I2C_FLTR_DNF)
+  uint32_t AnalogFilter;        /*!< Enables or disables analog noise filter.
+                                     This parameter can be a value of @ref I2C_LL_EC_ANALOGFILTER_SELECTION
+
+                                     This feature can be modified afterwards using unitary functions @ref LL_I2C_EnableAnalogFilter() or LL_I2C_DisableAnalogFilter(). */
+
+  uint32_t DigitalFilter;       /*!< Configures the digital noise filter.
+                                     This parameter can be a number between Min_Data = 0x00 and Max_Data = 0x0F
+
+                                     This feature can be modified afterwards using unitary function @ref LL_I2C_SetDigitalFilter(). */
+
+#endif
+  uint32_t OwnAddress1;         /*!< Specifies the device own address 1.
+                                     This parameter must be a value between Min_Data = 0x00 and Max_Data = 0x3FF
+
+                                     This feature can be modified afterwards using unitary function @ref LL_I2C_SetOwnAddress1(). */
+
+  uint32_t TypeAcknowledge;     /*!< Specifies the ACKnowledge or Non ACKnowledge condition after the address receive match code or next received byte.
+                                     This parameter can be a value of @ref I2C_LL_EC_I2C_ACKNOWLEDGE
+
+                                     This feature can be modified afterwards using unitary function @ref LL_I2C_AcknowledgeNextData(). */
+
+  uint32_t OwnAddrSize;         /*!< Specifies the device own address 1 size (7-bit or 10-bit).
+                                     This parameter can be a value of @ref I2C_LL_EC_OWNADDRESS1
+
+                                     This feature can be modified afterwards using unitary function @ref LL_I2C_SetOwnAddress1(). */
+} LL_I2C_InitTypeDef;
+/**
+  * @}
+  */
+#endif /*USE_FULL_LL_DRIVER*/
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup I2C_LL_Exported_Constants I2C Exported Constants
+  * @{
+  */
+
+/** @defgroup I2C_LL_EC_GET_FLAG Get Flags Defines
+  * @brief    Flags defines which can be used with LL_I2C_ReadReg function
+  * @{
+  */
+#define LL_I2C_SR1_SB                       I2C_SR1_SB              /*!< Start Bit (master mode)                   */
+#define LL_I2C_SR1_ADDR                     I2C_SR1_ADDR            /*!< Address sent (master mode) or
+                                                                         Address matched flag (slave mode)         */
+#define LL_I2C_SR1_BTF                      I2C_SR1_BTF             /*!< Byte Transfer Finished flag               */
+#define LL_I2C_SR1_ADD10                    I2C_SR1_ADD10           /*!< 10-bit header sent (master mode)          */
+#define LL_I2C_SR1_STOPF                    I2C_SR1_STOPF           /*!< Stop detection flag (slave mode)          */
+#define LL_I2C_SR1_RXNE                     I2C_SR1_RXNE            /*!< Data register not empty (receivers)       */
+#define LL_I2C_SR1_TXE                      I2C_SR1_TXE             /*!< Data register empty (transmitters)        */
+#define LL_I2C_SR1_BERR                     I2C_SR1_BERR            /*!< Bus error                                 */
+#define LL_I2C_SR1_ARLO                     I2C_SR1_ARLO            /*!< Arbitration lost                          */
+#define LL_I2C_SR1_AF                       I2C_SR1_AF              /*!< Acknowledge failure flag                  */
+#define LL_I2C_SR1_OVR                      I2C_SR1_OVR             /*!< Overrun/Underrun                          */
+#define LL_I2C_SR1_PECERR                   I2C_ISR_PECERR          /*!< PEC Error in reception (SMBus mode)       */
+#define LL_I2C_SR1_TIMEOUT                  I2C_ISR_TIMEOUT         /*!< Timeout detection flag (SMBus mode)       */
+#define LL_I2C_SR1_SMALERT                  I2C_ISR_SMALERT         /*!< SMBus alert (SMBus mode)                  */
+#define LL_I2C_SR2_MSL                      I2C_SR2_MSL             /*!< Master/Slave flag                         */
+#define LL_I2C_SR2_BUSY                     I2C_SR2_BUSY            /*!< Bus busy flag                             */
+#define LL_I2C_SR2_TRA                      I2C_SR2_TRA             /*!< Transmitter/receiver direction            */
+#define LL_I2C_SR2_GENCALL                  I2C_SR2_GENCALL         /*!< General call address (Slave mode)         */
+#define LL_I2C_SR2_SMBDEFAULT               I2C_SR2_SMBDEFAULT      /*!< SMBus Device default address (Slave mode) */
+#define LL_I2C_SR2_SMBHOST                  I2C_SR2_SMBHOST         /*!< SMBus Host address (Slave mode)           */
+#define LL_I2C_SR2_DUALF                    I2C_SR2_DUALF           /*!< Dual flag  (Slave mode)                   */
+/**
+  * @}
+  */
+
+/** @defgroup I2C_LL_EC_IT IT Defines
+  * @brief    IT defines which can be used with LL_I2C_ReadReg and  LL_I2C_WriteReg functions
+  * @{
+  */
+#define LL_I2C_CR2_ITEVTEN                  I2C_CR2_ITEVTEN         /*!< Events interrupts enable */
+#define LL_I2C_CR2_ITBUFEN                  I2C_CR2_ITBUFEN         /*!< Buffer interrupts enable */
+#define LL_I2C_CR2_ITERREN                  I2C_CR2_ITERREN         /*!< Error interrupts enable  */
+/**
+  * @}
+  */
+
+#if defined(I2C_FLTR_ANOFF)
+/** @defgroup I2C_LL_EC_ANALOGFILTER_SELECTION  Analog Filter Selection
+  * @{
+  */
+#define LL_I2C_ANALOGFILTER_ENABLE          0x00000000U             /*!< Analog filter is enabled. */
+#define LL_I2C_ANALOGFILTER_DISABLE         I2C_FLTR_ANOFF          /*!< Analog filter is disabled.*/
+/**
+  * @}
+  */
+
+#endif
+/** @defgroup I2C_LL_EC_OWNADDRESS1 Own Address 1 Length
+  * @{
+  */
+#define LL_I2C_OWNADDRESS1_7BIT             0x00004000U                                /*!< Own address 1 is a 7-bit address.   */
+#define LL_I2C_OWNADDRESS1_10BIT            (uint32_t)(I2C_OAR1_ADDMODE | 0x00004000U) /*!< Own address 1 is a 10-bit address.  */
+/**
+  * @}
+  */
+
+/** @defgroup I2C_LL_EC_DUTYCYCLE Fast Mode Duty Cycle
+  * @{
+  */
+#define LL_I2C_DUTYCYCLE_2                  0x00000000U             /*!< I2C fast mode Tlow/Thigh = 2        */
+#define LL_I2C_DUTYCYCLE_16_9               I2C_CCR_DUTY            /*!< I2C fast mode Tlow/Thigh = 16/9     */
+/**
+  * @}
+  */
+
+/** @defgroup I2C_LL_EC_CLOCK_SPEED_MODE Master Clock Speed Mode
+  * @{
+  */
+#define LL_I2C_CLOCK_SPEED_STANDARD_MODE    0x00000000U             /*!< Master clock speed range is standard mode */
+#define LL_I2C_CLOCK_SPEED_FAST_MODE        I2C_CCR_FS              /*!< Master clock speed range is fast mode     */
+/**
+  * @}
+  */
+
+/** @defgroup I2C_LL_EC_PERIPHERAL_MODE Peripheral Mode
+  * @{
+  */
+#define LL_I2C_MODE_I2C                     0x00000000U                                                 /*!< I2C Master or Slave mode                                    */
+#define LL_I2C_MODE_SMBUS_HOST              (uint32_t)(I2C_CR1_SMBUS | I2C_CR1_SMBTYPE | I2C_CR1_ENARP) /*!< SMBus Host address acknowledge                              */
+#define LL_I2C_MODE_SMBUS_DEVICE            I2C_CR1_SMBUS                                               /*!< SMBus Device default mode (Default address not acknowledge) */
+#define LL_I2C_MODE_SMBUS_DEVICE_ARP        (uint32_t)(I2C_CR1_SMBUS | I2C_CR1_ENARP)                   /*!< SMBus Device Default address acknowledge                    */
+/**
+  * @}
+  */
+
+/** @defgroup I2C_LL_EC_I2C_ACKNOWLEDGE Acknowledge Generation
+  * @{
+  */
+#define LL_I2C_ACK                          I2C_CR1_ACK             /*!< ACK is sent after current received byte. */
+#define LL_I2C_NACK                         0x00000000U             /*!< NACK is sent after current received byte.*/
+/**
+  * @}
+  */
+
+/** @defgroup I2C_LL_EC_DIRECTION Read Write Direction
+  * @{
+  */
+#define LL_I2C_DIRECTION_WRITE              I2C_SR2_TRA             /*!< Bus is in write transfer */
+#define LL_I2C_DIRECTION_READ               0x00000000U             /*!< Bus is in read transfer  */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup I2C_LL_Exported_Macros I2C Exported Macros
+  * @{
+  */
+
+/** @defgroup I2C_LL_EM_WRITE_READ Common Write and read registers Macros
+  * @{
+  */
+
+/**
+  * @brief  Write a value in I2C register
+  * @param  __INSTANCE__ I2C Instance
+  * @param  __REG__ Register to be written
+  * @param  __VALUE__ Value to be written in the register
+  * @retval None
+  */
+#define LL_I2C_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
+
+/**
+  * @brief  Read a value in I2C register
+  * @param  __INSTANCE__ I2C Instance
+  * @param  __REG__ Register to be read
+  * @retval Register value
+  */
+#define LL_I2C_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+/**
+  * @}
+  */
+
+/** @defgroup I2C_LL_EM_Exported_Macros_Helper Exported_Macros_Helper
+  * @{
+  */
+
+/**
+  * @brief  Convert Peripheral Clock Frequency in Mhz.
+  * @param  __PCLK__ This parameter must be a value of peripheral clock (in Hz).
+  * @retval Value of peripheral clock (in Mhz)
+  */
+#define __LL_I2C_FREQ_HZ_TO_MHZ(__PCLK__)                               (uint32_t)((__PCLK__)/1000000U)
+
+/**
+  * @brief  Convert Peripheral Clock Frequency in Hz.
+  * @param  __PCLK__ This parameter must be a value of peripheral clock (in Mhz).
+  * @retval Value of peripheral clock (in Hz)
+  */
+#define __LL_I2C_FREQ_MHZ_TO_HZ(__PCLK__)                               (uint32_t)((__PCLK__)*1000000U)
+
+/**
+  * @brief  Compute I2C Clock rising time.
+  * @param  __FREQRANGE__ This parameter must be a value of peripheral clock (in Mhz).
+  * @param  __SPEED__ This parameter must be a value lower than 400kHz (in Hz).
+  * @retval Value between Min_Data=0x02 and Max_Data=0x3F
+  */
+#define __LL_I2C_RISE_TIME(__FREQRANGE__, __SPEED__)                    (uint32_t)(((__SPEED__) <= LL_I2C_MAX_SPEED_STANDARD) ? ((__FREQRANGE__) + 1U) : ((((__FREQRANGE__) * 300U) / 1000U) + 1U))
+
+/**
+  * @brief  Compute Speed clock range to a Clock Control Register (I2C_CCR_CCR) value.
+  * @param  __PCLK__ This parameter must be a value of peripheral clock (in Hz).
+  * @param  __SPEED__ This parameter must be a value lower than 400kHz (in Hz).
+  * @param  __DUTYCYCLE__ This parameter can be one of the following values:
+  *         @arg @ref LL_I2C_DUTYCYCLE_2
+  *         @arg @ref LL_I2C_DUTYCYCLE_16_9
+  * @retval Value between Min_Data=0x004 and Max_Data=0xFFF, except in FAST DUTY mode where Min_Data=0x001.
+  */
+#define __LL_I2C_SPEED_TO_CCR(__PCLK__, __SPEED__, __DUTYCYCLE__)       (uint32_t)(((__SPEED__) <= LL_I2C_MAX_SPEED_STANDARD)? \
+                                                                                  (__LL_I2C_SPEED_STANDARD_TO_CCR((__PCLK__), (__SPEED__))) : \
+                                                                                  (__LL_I2C_SPEED_FAST_TO_CCR((__PCLK__), (__SPEED__), (__DUTYCYCLE__))))
+
+/**
+  * @brief  Compute Speed Standard clock range to a Clock Control Register (I2C_CCR_CCR) value.
+  * @param  __PCLK__ This parameter must be a value of peripheral clock (in Hz).
+  * @param  __SPEED__ This parameter must be a value lower than 100kHz (in Hz).
+  * @retval Value between Min_Data=0x004 and Max_Data=0xFFF.
+  */
+#define __LL_I2C_SPEED_STANDARD_TO_CCR(__PCLK__, __SPEED__)             (uint32_t)(((((__PCLK__)/((__SPEED__) << 1U)) & I2C_CCR_CCR) < 4U)? 4U:((__PCLK__) / ((__SPEED__) << 1U)))
+
+/**
+  * @brief  Compute Speed Fast clock range to a Clock Control Register (I2C_CCR_CCR) value.
+  * @param  __PCLK__ This parameter must be a value of peripheral clock (in Hz).
+  * @param  __SPEED__ This parameter must be a value between Min_Data=100Khz and Max_Data=400Khz (in Hz).
+  * @param  __DUTYCYCLE__ This parameter can be one of the following values:
+  *         @arg @ref LL_I2C_DUTYCYCLE_2
+  *         @arg @ref LL_I2C_DUTYCYCLE_16_9
+  * @retval Value between Min_Data=0x001 and Max_Data=0xFFF
+  */
+#define __LL_I2C_SPEED_FAST_TO_CCR(__PCLK__, __SPEED__, __DUTYCYCLE__)  (uint32_t)(((__DUTYCYCLE__) == LL_I2C_DUTYCYCLE_2)? \
+                                                                            (((((__PCLK__) / ((__SPEED__) * 3U)) & I2C_CCR_CCR) == 0U)? 1U:((__PCLK__) / ((__SPEED__) * 3U))) : \
+                                                                            (((((__PCLK__) / ((__SPEED__) * 25U)) & I2C_CCR_CCR) == 0U)? 1U:((__PCLK__) / ((__SPEED__) * 25U))))
+
+/**
+  * @brief  Get the Least significant bits of a 10-Bits address.
+  * @param  __ADDRESS__ This parameter must be a value of a 10-Bits slave address.
+  * @retval Value between Min_Data=0x00 and Max_Data=0xFF
+  */
+#define __LL_I2C_10BIT_ADDRESS(__ADDRESS__)                             ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FF))))
+
+/**
+  * @brief  Convert a 10-Bits address to a 10-Bits header with Write direction.
+  * @param  __ADDRESS__ This parameter must be a value of a 10-Bits slave address.
+  * @retval Value between Min_Data=0xF0 and Max_Data=0xF6
+  */
+#define __LL_I2C_10BIT_HEADER_WRITE(__ADDRESS__)                        ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0x0300))) >> 7) | (uint16_t)(0xF0))))
+
+/**
+  * @brief  Convert a 10-Bits address to a 10-Bits header with Read direction.
+  * @param  __ADDRESS__ This parameter must be a value of a 10-Bits slave address.
+  * @retval Value between Min_Data=0xF1 and Max_Data=0xF7
+  */
+#define __LL_I2C_10BIT_HEADER_READ(__ADDRESS__)                         ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0x0300))) >> 7) | (uint16_t)(0xF1))))
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup I2C_LL_Exported_Functions I2C Exported Functions
+  * @{
+  */
+
+/** @defgroup I2C_LL_EF_Configuration Configuration
+  * @{
+  */
+
+/**
+  * @brief  Enable I2C peripheral (PE = 1).
+  * @rmtoll CR1          PE            LL_I2C_Enable
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_Enable(I2C_TypeDef *I2Cx)
+{
+  SET_BIT(I2Cx->CR1, I2C_CR1_PE);
+}
+
+/**
+  * @brief  Disable I2C peripheral (PE = 0).
+  * @rmtoll CR1          PE            LL_I2C_Disable
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_Disable(I2C_TypeDef *I2Cx)
+{
+  CLEAR_BIT(I2Cx->CR1, I2C_CR1_PE);
+}
+
+/**
+  * @brief  Check if the I2C peripheral is enabled or disabled.
+  * @rmtoll CR1          PE            LL_I2C_IsEnabled
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabled(I2C_TypeDef *I2Cx)
+{
+  return (READ_BIT(I2Cx->CR1, I2C_CR1_PE) == (I2C_CR1_PE));
+}
+
+#if  defined(I2C_FLTR_ANOFF)&&defined(I2C_FLTR_DNF)
+/**
+  * @brief  Configure Noise Filters (Analog and Digital).
+  * @note   If the analog filter is also enabled, the digital filter is added to analog filter.
+  *         The filters can only be programmed when the I2C is disabled (PE = 0).
+  * @rmtoll FLTR         ANOFF         LL_I2C_ConfigFilters\n
+  *         FLTR         DNF           LL_I2C_ConfigFilters
+  * @param  I2Cx I2C Instance.
+  * @param  AnalogFilter This parameter can be one of the following values:
+  *         @arg @ref LL_I2C_ANALOGFILTER_ENABLE
+  *         @arg @ref LL_I2C_ANALOGFILTER_DISABLE
+  * @param  DigitalFilter This parameter must be a value between Min_Data=0x00 (Digital filter disabled) and Max_Data=0x0F (Digital filter enabled and filtering capability up to 15*TPCLK1)
+  *               This parameter is used to configure the digital noise filter on SDA and SCL input. The digital filter will suppress the spikes with a length of up to DNF[3:0]*TPCLK1.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_ConfigFilters(I2C_TypeDef *I2Cx, uint32_t AnalogFilter, uint32_t DigitalFilter)
+{
+  MODIFY_REG(I2Cx->FLTR, I2C_FLTR_ANOFF | I2C_FLTR_DNF, AnalogFilter | DigitalFilter);
+}
+#endif
+#if defined(I2C_FLTR_DNF)
+
+/**
+  * @brief  Configure Digital Noise Filter.
+  * @note   If the analog filter is also enabled, the digital filter is added to analog filter.
+  *         This filter can only be programmed when the I2C is disabled (PE = 0).
+  * @rmtoll FLTR         DNF           LL_I2C_SetDigitalFilter
+  * @param  I2Cx I2C Instance.
+  * @param  DigitalFilter This parameter must be a value between Min_Data=0x00 (Digital filter disabled) and Max_Data=0x0F (Digital filter enabled and filtering capability up to 15*TPCLK1)
+  *               This parameter is used to configure the digital noise filter on SDA and SCL input. The digital filter will suppress the spikes with a length of up to DNF[3:0]*TPCLK1.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_SetDigitalFilter(I2C_TypeDef *I2Cx, uint32_t DigitalFilter)
+{
+  MODIFY_REG(I2Cx->FLTR, I2C_FLTR_DNF, DigitalFilter);
+}
+
+/**
+  * @brief  Get the current Digital Noise Filter configuration.
+  * @rmtoll FLTR         DNF           LL_I2C_GetDigitalFilter
+  * @param  I2Cx I2C Instance.
+  * @retval Value between Min_Data=0x0 and Max_Data=0xF
+  */
+__STATIC_INLINE uint32_t LL_I2C_GetDigitalFilter(I2C_TypeDef *I2Cx)
+{
+  return (uint32_t)(READ_BIT(I2Cx->FLTR, I2C_FLTR_DNF));
+}
+#endif
+#if defined(I2C_FLTR_ANOFF)
+
+/**
+  * @brief  Enable Analog Noise Filter.
+  * @note   This filter can only be programmed when the I2C is disabled (PE = 0).
+  * @rmtoll FLTR         ANOFF         LL_I2C_EnableAnalogFilter
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_EnableAnalogFilter(I2C_TypeDef *I2Cx)
+{
+  CLEAR_BIT(I2Cx->FLTR, I2C_FLTR_ANOFF);
+}
+
+/**
+  * @brief  Disable Analog Noise Filter.
+  * @note   This filter can only be programmed when the I2C is disabled (PE = 0).
+  * @rmtoll FLTR         ANOFF         LL_I2C_DisableAnalogFilter
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_DisableAnalogFilter(I2C_TypeDef *I2Cx)
+{
+  SET_BIT(I2Cx->FLTR, I2C_FLTR_ANOFF);
+}
+
+/**
+  * @brief  Check if Analog Noise Filter is enabled or disabled.
+  * @rmtoll FLTR         ANOFF         LL_I2C_IsEnabledAnalogFilter
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledAnalogFilter(I2C_TypeDef *I2Cx)
+{
+  return (READ_BIT(I2Cx->FLTR, I2C_FLTR_ANOFF) == (I2C_FLTR_ANOFF));
+}
+#endif
+
+/**
+  * @brief  Enable DMA transmission requests.
+  * @rmtoll CR2          DMAEN         LL_I2C_EnableDMAReq_TX
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_EnableDMAReq_TX(I2C_TypeDef *I2Cx)
+{
+  SET_BIT(I2Cx->CR2, I2C_CR2_DMAEN);
+}
+
+/**
+  * @brief  Disable DMA transmission requests.
+  * @rmtoll CR2          DMAEN         LL_I2C_DisableDMAReq_TX
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_DisableDMAReq_TX(I2C_TypeDef *I2Cx)
+{
+  CLEAR_BIT(I2Cx->CR2, I2C_CR2_DMAEN);
+}
+
+/**
+  * @brief  Check if DMA transmission requests are enabled or disabled.
+  * @rmtoll CR2          DMAEN         LL_I2C_IsEnabledDMAReq_TX
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_TX(I2C_TypeDef *I2Cx)
+{
+  return (READ_BIT(I2Cx->CR2, I2C_CR2_DMAEN) == (I2C_CR2_DMAEN));
+}
+
+/**
+  * @brief  Enable DMA reception requests.
+  * @rmtoll CR2          DMAEN         LL_I2C_EnableDMAReq_RX
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_EnableDMAReq_RX(I2C_TypeDef *I2Cx)
+{
+  SET_BIT(I2Cx->CR2, I2C_CR2_DMAEN);
+}
+
+/**
+  * @brief  Disable DMA reception requests.
+  * @rmtoll CR2          DMAEN         LL_I2C_DisableDMAReq_RX
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_DisableDMAReq_RX(I2C_TypeDef *I2Cx)
+{
+  CLEAR_BIT(I2Cx->CR2, I2C_CR2_DMAEN);
+}
+
+/**
+  * @brief  Check if DMA reception requests are enabled or disabled.
+  * @rmtoll CR2          DMAEN         LL_I2C_IsEnabledDMAReq_RX
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_RX(I2C_TypeDef *I2Cx)
+{
+  return (READ_BIT(I2Cx->CR2, I2C_CR2_DMAEN) == (I2C_CR2_DMAEN));
+}
+
+/**
+  * @brief  Get the data register address used for DMA transfer.
+  * @rmtoll DR           DR            LL_I2C_DMA_GetRegAddr
+  * @param  I2Cx I2C Instance.
+  * @retval Address of data register
+  */
+__STATIC_INLINE uint32_t LL_I2C_DMA_GetRegAddr(I2C_TypeDef *I2Cx)
+{
+  return (uint32_t) & (I2Cx->DR);
+}
+
+/**
+  * @brief  Enable Clock stretching.
+  * @note   This bit can only be programmed when the I2C is disabled (PE = 0).
+  * @rmtoll CR1          NOSTRETCH     LL_I2C_EnableClockStretching
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_EnableClockStretching(I2C_TypeDef *I2Cx)
+{
+  CLEAR_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH);
+}
+
+/**
+  * @brief  Disable Clock stretching.
+  * @note   This bit can only be programmed when the I2C is disabled (PE = 0).
+  * @rmtoll CR1          NOSTRETCH     LL_I2C_DisableClockStretching
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_DisableClockStretching(I2C_TypeDef *I2Cx)
+{
+  SET_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH);
+}
+
+/**
+  * @brief  Check if Clock stretching is enabled or disabled.
+  * @rmtoll CR1          NOSTRETCH     LL_I2C_IsEnabledClockStretching
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledClockStretching(I2C_TypeDef *I2Cx)
+{
+  return (READ_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH) != (I2C_CR1_NOSTRETCH));
+}
+
+/**
+  * @brief  Enable General Call.
+  * @note   When enabled the Address 0x00 is ACKed.
+  * @rmtoll CR1          ENGC          LL_I2C_EnableGeneralCall
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_EnableGeneralCall(I2C_TypeDef *I2Cx)
+{
+  SET_BIT(I2Cx->CR1, I2C_CR1_ENGC);
+}
+
+/**
+  * @brief  Disable General Call.
+  * @note   When disabled the Address 0x00 is NACKed.
+  * @rmtoll CR1          ENGC          LL_I2C_DisableGeneralCall
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_DisableGeneralCall(I2C_TypeDef *I2Cx)
+{
+  CLEAR_BIT(I2Cx->CR1, I2C_CR1_ENGC);
+}
+
+/**
+  * @brief  Check if General Call is enabled or disabled.
+  * @rmtoll CR1          ENGC          LL_I2C_IsEnabledGeneralCall
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledGeneralCall(I2C_TypeDef *I2Cx)
+{
+  return (READ_BIT(I2Cx->CR1, I2C_CR1_ENGC) == (I2C_CR1_ENGC));
+}
+
+/**
+  * @brief  Set the Own Address1.
+  * @rmtoll OAR1         ADD0          LL_I2C_SetOwnAddress1\n
+  *         OAR1         ADD1_7        LL_I2C_SetOwnAddress1\n
+  *         OAR1         ADD8_9        LL_I2C_SetOwnAddress1\n
+  *         OAR1         ADDMODE       LL_I2C_SetOwnAddress1
+  * @param  I2Cx I2C Instance.
+  * @param  OwnAddress1 This parameter must be a value between Min_Data=0 and Max_Data=0x3FF.
+  * @param  OwnAddrSize This parameter can be one of the following values:
+  *         @arg @ref LL_I2C_OWNADDRESS1_7BIT
+  *         @arg @ref LL_I2C_OWNADDRESS1_10BIT
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_SetOwnAddress1(I2C_TypeDef *I2Cx, uint32_t OwnAddress1, uint32_t OwnAddrSize)
+{
+  MODIFY_REG(I2Cx->OAR1, I2C_OAR1_ADD0 | I2C_OAR1_ADD1_7 | I2C_OAR1_ADD8_9 | I2C_OAR1_ADDMODE, OwnAddress1 | OwnAddrSize);
+}
+
+/**
+  * @brief  Set the 7bits Own Address2.
+  * @note   This action has no effect if own address2 is enabled.
+  * @rmtoll OAR2         ADD2          LL_I2C_SetOwnAddress2
+  * @param  I2Cx I2C Instance.
+  * @param  OwnAddress2 This parameter must be a value between Min_Data=0 and Max_Data=0x7F.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_SetOwnAddress2(I2C_TypeDef *I2Cx, uint32_t OwnAddress2)
+{
+  MODIFY_REG(I2Cx->OAR2, I2C_OAR2_ADD2, OwnAddress2);
+}
+
+/**
+  * @brief  Enable acknowledge on Own Address2 match address.
+  * @rmtoll OAR2         ENDUAL        LL_I2C_EnableOwnAddress2
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_EnableOwnAddress2(I2C_TypeDef *I2Cx)
+{
+  SET_BIT(I2Cx->OAR2, I2C_OAR2_ENDUAL);
+}
+
+/**
+  * @brief  Disable  acknowledge on Own Address2 match address.
+  * @rmtoll OAR2         ENDUAL        LL_I2C_DisableOwnAddress2
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_DisableOwnAddress2(I2C_TypeDef *I2Cx)
+{
+  CLEAR_BIT(I2Cx->OAR2, I2C_OAR2_ENDUAL);
+}
+
+/**
+  * @brief  Check if Own Address1 acknowledge is enabled or disabled.
+  * @rmtoll OAR2         ENDUAL        LL_I2C_IsEnabledOwnAddress2
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress2(I2C_TypeDef *I2Cx)
+{
+  return (READ_BIT(I2Cx->OAR2, I2C_OAR2_ENDUAL) == (I2C_OAR2_ENDUAL));
+}
+
+/**
+  * @brief  Configure the Peripheral clock frequency.
+  * @rmtoll CR2          FREQ          LL_I2C_SetPeriphClock
+  * @param  I2Cx I2C Instance.
+  * @param  PeriphClock Peripheral Clock (in Hz)
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_SetPeriphClock(I2C_TypeDef *I2Cx, uint32_t PeriphClock)
+{
+  MODIFY_REG(I2Cx->CR2, I2C_CR2_FREQ, __LL_I2C_FREQ_HZ_TO_MHZ(PeriphClock));
+}
+
+/**
+  * @brief  Get the Peripheral clock frequency.
+  * @rmtoll CR2          FREQ          LL_I2C_GetPeriphClock
+  * @param  I2Cx I2C Instance.
+  * @retval Value of Peripheral Clock (in Hz)
+  */
+__STATIC_INLINE uint32_t LL_I2C_GetPeriphClock(I2C_TypeDef *I2Cx)
+{
+  return (uint32_t)(__LL_I2C_FREQ_MHZ_TO_HZ(READ_BIT(I2Cx->CR2, I2C_CR2_FREQ)));
+}
+
+/**
+  * @brief  Configure the Duty cycle (Fast mode only).
+  * @rmtoll CCR          DUTY          LL_I2C_SetDutyCycle
+  * @param  I2Cx I2C Instance.
+  * @param  DutyCycle This parameter can be one of the following values:
+  *         @arg @ref LL_I2C_DUTYCYCLE_2
+  *         @arg @ref LL_I2C_DUTYCYCLE_16_9
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_SetDutyCycle(I2C_TypeDef *I2Cx, uint32_t DutyCycle)
+{
+  MODIFY_REG(I2Cx->CCR, I2C_CCR_DUTY, DutyCycle);
+}
+
+/**
+  * @brief  Get the Duty cycle (Fast mode only).
+  * @rmtoll CCR          DUTY          LL_I2C_GetDutyCycle
+  * @param  I2Cx I2C Instance.
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_I2C_DUTYCYCLE_2
+  *         @arg @ref LL_I2C_DUTYCYCLE_16_9
+  */
+__STATIC_INLINE uint32_t LL_I2C_GetDutyCycle(I2C_TypeDef *I2Cx)
+{
+  return (uint32_t)(READ_BIT(I2Cx->CCR, I2C_CCR_DUTY));
+}
+
+/**
+  * @brief  Configure the I2C master clock speed mode.
+  * @rmtoll CCR          FS            LL_I2C_SetClockSpeedMode
+  * @param  I2Cx I2C Instance.
+  * @param  ClockSpeedMode This parameter can be one of the following values:
+  *         @arg @ref LL_I2C_CLOCK_SPEED_STANDARD_MODE
+  *         @arg @ref LL_I2C_CLOCK_SPEED_FAST_MODE
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_SetClockSpeedMode(I2C_TypeDef *I2Cx, uint32_t ClockSpeedMode)
+{
+  MODIFY_REG(I2Cx->CCR, I2C_CCR_FS, ClockSpeedMode);
+}
+
+/**
+  * @brief  Get the the I2C master speed mode.
+  * @rmtoll CCR          FS            LL_I2C_GetClockSpeedMode
+  * @param  I2Cx I2C Instance.
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_I2C_CLOCK_SPEED_STANDARD_MODE
+  *         @arg @ref LL_I2C_CLOCK_SPEED_FAST_MODE
+  */
+__STATIC_INLINE uint32_t LL_I2C_GetClockSpeedMode(I2C_TypeDef *I2Cx)
+{
+  return (uint32_t)(READ_BIT(I2Cx->CCR, I2C_CCR_FS));
+}
+
+/**
+  * @brief  Configure the SCL, SDA rising time.
+  * @note   This bit can only be programmed when the I2C is disabled (PE = 0).
+  * @rmtoll TRISE        TRISE         LL_I2C_SetRiseTime
+  * @param  I2Cx I2C Instance.
+  * @param  RiseTime This parameter must be a value between Min_Data=0x02 and Max_Data=0x3F.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_SetRiseTime(I2C_TypeDef *I2Cx, uint32_t RiseTime)
+{
+  MODIFY_REG(I2Cx->TRISE, I2C_TRISE_TRISE, RiseTime);
+}
+
+/**
+  * @brief  Get the SCL, SDA rising time.
+  * @rmtoll TRISE        TRISE         LL_I2C_GetRiseTime
+  * @param  I2Cx I2C Instance.
+  * @retval Value between Min_Data=0x02 and Max_Data=0x3F
+  */
+__STATIC_INLINE uint32_t LL_I2C_GetRiseTime(I2C_TypeDef *I2Cx)
+{
+  return (uint32_t)(READ_BIT(I2Cx->TRISE, I2C_TRISE_TRISE));
+}
+
+/**
+  * @brief  Configure the SCL high and low period.
+  * @note   This bit can only be programmed when the I2C is disabled (PE = 0).
+  * @rmtoll CCR          CCR           LL_I2C_SetClockPeriod
+  * @param  I2Cx I2C Instance.
+  * @param  ClockPeriod This parameter must be a value between Min_Data=0x004 and Max_Data=0xFFF, except in FAST DUTY mode where Min_Data=0x001.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_SetClockPeriod(I2C_TypeDef *I2Cx, uint32_t ClockPeriod)
+{
+  MODIFY_REG(I2Cx->CCR, I2C_CCR_CCR, ClockPeriod);
+}
+
+/**
+  * @brief  Get the SCL high and low period.
+  * @rmtoll CCR          CCR           LL_I2C_GetClockPeriod
+  * @param  I2Cx I2C Instance.
+  * @retval Value between Min_Data=0x004 and Max_Data=0xFFF, except in FAST DUTY mode where Min_Data=0x001.
+  */
+__STATIC_INLINE uint32_t LL_I2C_GetClockPeriod(I2C_TypeDef *I2Cx)
+{
+  return (uint32_t)(READ_BIT(I2Cx->CCR, I2C_CCR_CCR));
+}
+
+/**
+  * @brief  Configure the SCL speed.
+  * @note   This bit can only be programmed when the I2C is disabled (PE = 0).
+  * @rmtoll CR2          FREQ          LL_I2C_ConfigSpeed\n
+  *         TRISE        TRISE         LL_I2C_ConfigSpeed\n
+  *         CCR          FS            LL_I2C_ConfigSpeed\n
+  *         CCR          DUTY          LL_I2C_ConfigSpeed\n
+  *         CCR          CCR           LL_I2C_ConfigSpeed
+  * @param  I2Cx I2C Instance.
+  * @param  PeriphClock Peripheral Clock (in Hz)
+  * @param  ClockSpeed This parameter must be a value lower than 400kHz (in Hz).
+  * @param  DutyCycle This parameter can be one of the following values:
+  *         @arg @ref LL_I2C_DUTYCYCLE_2
+  *         @arg @ref LL_I2C_DUTYCYCLE_16_9
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_ConfigSpeed(I2C_TypeDef *I2Cx, uint32_t PeriphClock, uint32_t ClockSpeed,
+                                        uint32_t DutyCycle)
+{
+  uint32_t freqrange = 0x0U;
+  uint32_t clockconfig = 0x0U;
+
+  /* Compute frequency range */
+  freqrange = __LL_I2C_FREQ_HZ_TO_MHZ(PeriphClock);
+
+  /* Configure I2Cx: Frequency range register */
+  MODIFY_REG(I2Cx->CR2, I2C_CR2_FREQ, freqrange);
+
+  /* Configure I2Cx: Rise Time register */
+  MODIFY_REG(I2Cx->TRISE, I2C_TRISE_TRISE, __LL_I2C_RISE_TIME(freqrange, ClockSpeed));
+
+  /* Configure Speed mode, Duty Cycle and Clock control register value */
+  if (ClockSpeed > LL_I2C_MAX_SPEED_STANDARD)
+  {
+    /* Set Speed mode at fast and duty cycle for Clock Speed request in fast clock range */
+    clockconfig = LL_I2C_CLOCK_SPEED_FAST_MODE                                          | \
+                  __LL_I2C_SPEED_FAST_TO_CCR(PeriphClock, ClockSpeed, DutyCycle)        | \
+                  DutyCycle;
+  }
+  else
+  {
+    /* Set Speed mode at standard for Clock Speed request in standard clock range */
+    clockconfig = LL_I2C_CLOCK_SPEED_STANDARD_MODE                                      | \
+                  __LL_I2C_SPEED_STANDARD_TO_CCR(PeriphClock, ClockSpeed);
+  }
+
+  /* Configure I2Cx: Clock control register */
+  MODIFY_REG(I2Cx->CCR, (I2C_CCR_FS | I2C_CCR_DUTY | I2C_CCR_CCR), clockconfig);
+}
+
+/**
+  * @brief  Configure peripheral mode.
+  * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+  *         SMBus feature is supported by the I2Cx Instance.
+  * @rmtoll CR1          SMBUS         LL_I2C_SetMode\n
+  *         CR1          SMBTYPE       LL_I2C_SetMode\n
+  *         CR1          ENARP         LL_I2C_SetMode
+  * @param  I2Cx I2C Instance.
+  * @param  PeripheralMode This parameter can be one of the following values:
+  *         @arg @ref LL_I2C_MODE_I2C
+  *         @arg @ref LL_I2C_MODE_SMBUS_HOST
+  *         @arg @ref LL_I2C_MODE_SMBUS_DEVICE
+  *         @arg @ref LL_I2C_MODE_SMBUS_DEVICE_ARP
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_SetMode(I2C_TypeDef *I2Cx, uint32_t PeripheralMode)
+{
+  MODIFY_REG(I2Cx->CR1, I2C_CR1_SMBUS | I2C_CR1_SMBTYPE | I2C_CR1_ENARP, PeripheralMode);
+}
+
+/**
+  * @brief  Get peripheral mode.
+  * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+  *         SMBus feature is supported by the I2Cx Instance.
+  * @rmtoll CR1          SMBUS         LL_I2C_GetMode\n
+  *         CR1          SMBTYPE       LL_I2C_GetMode\n
+  *         CR1          ENARP         LL_I2C_GetMode
+  * @param  I2Cx I2C Instance.
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_I2C_MODE_I2C
+  *         @arg @ref LL_I2C_MODE_SMBUS_HOST
+  *         @arg @ref LL_I2C_MODE_SMBUS_DEVICE
+  *         @arg @ref LL_I2C_MODE_SMBUS_DEVICE_ARP
+  */
+__STATIC_INLINE uint32_t LL_I2C_GetMode(I2C_TypeDef *I2Cx)
+{
+  return (uint32_t)(READ_BIT(I2Cx->CR1, I2C_CR1_SMBUS | I2C_CR1_SMBTYPE | I2C_CR1_ENARP));
+}
+
+/**
+  * @brief  Enable SMBus alert (Host or Device mode)
+  * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+  *         SMBus feature is supported by the I2Cx Instance.
+  * @note   SMBus Device mode:
+  *         - SMBus Alert pin is drived low and
+  *           Alert Response Address Header acknowledge is enabled.
+  *         SMBus Host mode:
+  *         - SMBus Alert pin management is supported.
+  * @rmtoll CR1          ALERT         LL_I2C_EnableSMBusAlert
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_EnableSMBusAlert(I2C_TypeDef *I2Cx)
+{
+  SET_BIT(I2Cx->CR1, I2C_CR1_ALERT);
+}
+
+/**
+  * @brief  Disable SMBus alert (Host or Device mode)
+  * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+  *         SMBus feature is supported by the I2Cx Instance.
+  * @note   SMBus Device mode:
+  *         - SMBus Alert pin is not drived (can be used as a standard GPIO) and
+  *           Alert Response Address Header acknowledge is disabled.
+  *         SMBus Host mode:
+  *         - SMBus Alert pin management is not supported.
+  * @rmtoll CR1          ALERT         LL_I2C_DisableSMBusAlert
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_DisableSMBusAlert(I2C_TypeDef *I2Cx)
+{
+  CLEAR_BIT(I2Cx->CR1, I2C_CR1_ALERT);
+}
+
+/**
+  * @brief  Check if SMBus alert (Host or Device mode) is enabled or disabled.
+  * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+  *         SMBus feature is supported by the I2Cx Instance.
+  * @rmtoll CR1          ALERT         LL_I2C_IsEnabledSMBusAlert
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusAlert(I2C_TypeDef *I2Cx)
+{
+  return (READ_BIT(I2Cx->CR1, I2C_CR1_ALERT) == (I2C_CR1_ALERT));
+}
+
+/**
+  * @brief  Enable SMBus Packet Error Calculation (PEC).
+  * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+  *         SMBus feature is supported by the I2Cx Instance.
+  * @rmtoll CR1          ENPEC         LL_I2C_EnableSMBusPEC
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_EnableSMBusPEC(I2C_TypeDef *I2Cx)
+{
+  SET_BIT(I2Cx->CR1, I2C_CR1_ENPEC);
+}
+
+/**
+  * @brief  Disable SMBus Packet Error Calculation (PEC).
+  * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+  *         SMBus feature is supported by the I2Cx Instance.
+  * @rmtoll CR1          ENPEC         LL_I2C_DisableSMBusPEC
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_DisableSMBusPEC(I2C_TypeDef *I2Cx)
+{
+  CLEAR_BIT(I2Cx->CR1, I2C_CR1_ENPEC);
+}
+
+/**
+  * @brief  Check if SMBus Packet Error Calculation (PEC) is enabled or disabled.
+  * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+  *         SMBus feature is supported by the I2Cx Instance.
+  * @rmtoll CR1          ENPEC         LL_I2C_IsEnabledSMBusPEC
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPEC(I2C_TypeDef *I2Cx)
+{
+  return (READ_BIT(I2Cx->CR1, I2C_CR1_ENPEC) == (I2C_CR1_ENPEC));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup I2C_LL_EF_IT_Management IT_Management
+  * @{
+  */
+
+/**
+  * @brief  Enable TXE interrupt.
+  * @rmtoll CR2          ITEVTEN       LL_I2C_EnableIT_TX\n
+  *         CR2          ITBUFEN       LL_I2C_EnableIT_TX
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_EnableIT_TX(I2C_TypeDef *I2Cx)
+{
+  SET_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN | I2C_CR2_ITBUFEN);
+}
+
+/**
+  * @brief  Disable TXE interrupt.
+  * @rmtoll CR2          ITEVTEN       LL_I2C_DisableIT_TX\n
+  *         CR2          ITBUFEN       LL_I2C_DisableIT_TX
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_DisableIT_TX(I2C_TypeDef *I2Cx)
+{
+  CLEAR_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN | I2C_CR2_ITBUFEN);
+}
+
+/**
+  * @brief  Check if the TXE Interrupt is enabled or disabled.
+  * @rmtoll CR2          ITEVTEN       LL_I2C_IsEnabledIT_TX\n
+  *         CR2          ITBUFEN       LL_I2C_IsEnabledIT_TX
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TX(I2C_TypeDef *I2Cx)
+{
+  return (READ_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN | I2C_CR2_ITBUFEN) == (I2C_CR2_ITEVTEN | I2C_CR2_ITBUFEN));
+}
+
+/**
+  * @brief  Enable RXNE interrupt.
+  * @rmtoll CR2          ITEVTEN       LL_I2C_EnableIT_RX\n
+  *         CR2          ITBUFEN       LL_I2C_EnableIT_RX
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_EnableIT_RX(I2C_TypeDef *I2Cx)
+{
+  SET_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN | I2C_CR2_ITBUFEN);
+}
+
+/**
+  * @brief  Disable RXNE interrupt.
+  * @rmtoll CR2          ITEVTEN       LL_I2C_DisableIT_RX\n
+  *         CR2          ITBUFEN       LL_I2C_DisableIT_RX
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_DisableIT_RX(I2C_TypeDef *I2Cx)
+{
+  CLEAR_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN | I2C_CR2_ITBUFEN);
+}
+
+/**
+  * @brief  Check if the RXNE Interrupt is enabled or disabled.
+  * @rmtoll CR2          ITEVTEN       LL_I2C_IsEnabledIT_RX\n
+  *         CR2          ITBUFEN       LL_I2C_IsEnabledIT_RX
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_RX(I2C_TypeDef *I2Cx)
+{
+  return (READ_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN | I2C_CR2_ITBUFEN) == (I2C_CR2_ITEVTEN | I2C_CR2_ITBUFEN));
+}
+
+/**
+  * @brief  Enable Events interrupts.
+  * @note   Any of these events will generate interrupt :
+  *         Start Bit (SB)
+  *         Address sent, Address matched (ADDR)
+  *         10-bit header sent (ADD10)
+  *         Stop detection  (STOPF)
+  *         Byte transfer finished (BTF)
+  *
+  * @note   Any of these events will generate interrupt if Buffer interrupts are enabled too(using unitary function @ref LL_I2C_EnableIT_BUF()) :
+  *         Receive buffer not empty (RXNE)
+  *         Transmit buffer empty (TXE)
+  * @rmtoll CR2          ITEVTEN       LL_I2C_EnableIT_EVT
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_EnableIT_EVT(I2C_TypeDef *I2Cx)
+{
+  SET_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN);
+}
+
+/**
+  * @brief  Disable Events interrupts.
+  * @note   Any of these events will generate interrupt :
+  *         Start Bit (SB)
+  *         Address sent, Address matched (ADDR)
+  *         10-bit header sent (ADD10)
+  *         Stop detection  (STOPF)
+  *         Byte transfer finished (BTF)
+  *         Receive buffer not empty (RXNE)
+  *         Transmit buffer empty (TXE)
+  * @rmtoll CR2          ITEVTEN       LL_I2C_DisableIT_EVT
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_DisableIT_EVT(I2C_TypeDef *I2Cx)
+{
+  CLEAR_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN);
+}
+
+/**
+  * @brief  Check if Events interrupts are enabled or disabled.
+  * @rmtoll CR2          ITEVTEN       LL_I2C_IsEnabledIT_EVT
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_EVT(I2C_TypeDef *I2Cx)
+{
+  return (READ_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN) == (I2C_CR2_ITEVTEN));
+}
+
+/**
+  * @brief  Enable Buffer interrupts.
+  * @note   Any of these Buffer events will generate interrupt if Events interrupts are enabled too(using unitary function @ref LL_I2C_EnableIT_EVT()) :
+  *         Receive buffer not empty (RXNE)
+  *         Transmit buffer empty (TXE)
+  * @rmtoll CR2          ITBUFEN       LL_I2C_EnableIT_BUF
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_EnableIT_BUF(I2C_TypeDef *I2Cx)
+{
+  SET_BIT(I2Cx->CR2, I2C_CR2_ITBUFEN);
+}
+
+/**
+  * @brief  Disable Buffer interrupts.
+  * @note   Any of these Buffer events will generate interrupt :
+  *         Receive buffer not empty (RXNE)
+  *         Transmit buffer empty (TXE)
+  * @rmtoll CR2          ITBUFEN       LL_I2C_DisableIT_BUF
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_DisableIT_BUF(I2C_TypeDef *I2Cx)
+{
+  CLEAR_BIT(I2Cx->CR2, I2C_CR2_ITBUFEN);
+}
+
+/**
+  * @brief  Check if Buffer interrupts are enabled or disabled.
+  * @rmtoll CR2          ITBUFEN       LL_I2C_IsEnabledIT_BUF
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_BUF(I2C_TypeDef *I2Cx)
+{
+  return (READ_BIT(I2Cx->CR2, I2C_CR2_ITBUFEN) == (I2C_CR2_ITBUFEN));
+}
+
+/**
+  * @brief  Enable Error interrupts.
+  * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+  *         SMBus feature is supported by the I2Cx Instance.
+  * @note   Any of these errors will generate interrupt :
+  *         Bus Error detection (BERR)
+  *         Arbitration Loss (ARLO)
+  *         Acknowledge Failure(AF)
+  *         Overrun/Underrun (OVR)
+  *         SMBus Timeout detection (TIMEOUT)
+  *         SMBus PEC error detection (PECERR)
+  *         SMBus Alert pin event detection (SMBALERT)
+  * @rmtoll CR2          ITERREN       LL_I2C_EnableIT_ERR
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_EnableIT_ERR(I2C_TypeDef *I2Cx)
+{
+  SET_BIT(I2Cx->CR2, I2C_CR2_ITERREN);
+}
+
+/**
+  * @brief  Disable Error interrupts.
+  * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+  *         SMBus feature is supported by the I2Cx Instance.
+  * @note   Any of these errors will generate interrupt :
+  *         Bus Error detection (BERR)
+  *         Arbitration Loss (ARLO)
+  *         Acknowledge Failure(AF)
+  *         Overrun/Underrun (OVR)
+  *         SMBus Timeout detection (TIMEOUT)
+  *         SMBus PEC error detection (PECERR)
+  *         SMBus Alert pin event detection (SMBALERT)
+  * @rmtoll CR2          ITERREN       LL_I2C_DisableIT_ERR
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_DisableIT_ERR(I2C_TypeDef *I2Cx)
+{
+  CLEAR_BIT(I2Cx->CR2, I2C_CR2_ITERREN);
+}
+
+/**
+  * @brief  Check if Error interrupts are enabled or disabled.
+  * @rmtoll CR2          ITERREN       LL_I2C_IsEnabledIT_ERR
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ERR(I2C_TypeDef *I2Cx)
+{
+  return (READ_BIT(I2Cx->CR2, I2C_CR2_ITERREN) == (I2C_CR2_ITERREN));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup I2C_LL_EF_FLAG_management FLAG_management
+  * @{
+  */
+
+/**
+  * @brief  Indicate the status of Transmit data register empty flag.
+  * @note   RESET: When next data is written in Transmit data register.
+  *         SET: When Transmit data register is empty.
+  * @rmtoll SR1          TXE           LL_I2C_IsActiveFlag_TXE
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXE(I2C_TypeDef *I2Cx)
+{
+  return (READ_BIT(I2Cx->SR1, I2C_SR1_TXE) == (I2C_SR1_TXE));
+}
+
+/**
+  * @brief  Indicate the status of Byte Transfer Finished flag.
+  *         RESET: When Data byte transfer not done.
+  *         SET: When Data byte transfer succeeded.
+  * @rmtoll SR1          BTF           LL_I2C_IsActiveFlag_BTF
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BTF(I2C_TypeDef *I2Cx)
+{
+  return (READ_BIT(I2Cx->SR1, I2C_SR1_BTF) == (I2C_SR1_BTF));
+}
+
+/**
+  * @brief  Indicate the status of Receive data register not empty flag.
+  * @note   RESET: When Receive data register is read.
+  *         SET: When the received data is copied in Receive data register.
+  * @rmtoll SR1          RXNE          LL_I2C_IsActiveFlag_RXNE
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_RXNE(I2C_TypeDef *I2Cx)
+{
+  return (READ_BIT(I2Cx->SR1, I2C_SR1_RXNE) == (I2C_SR1_RXNE));
+}
+
+/**
+  * @brief  Indicate the status of Start Bit (master mode).
+  * @note   RESET: When No Start condition.
+  *         SET: When Start condition is generated.
+  * @rmtoll SR1          SB            LL_I2C_IsActiveFlag_SB
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_SB(I2C_TypeDef *I2Cx)
+{
+  return (READ_BIT(I2Cx->SR1, I2C_SR1_SB) == (I2C_SR1_SB));
+}
+
+/**
+  * @brief  Indicate the status of Address sent (master mode) or Address matched flag (slave mode).
+  * @note   RESET: Clear default value.
+  *         SET: When the address is fully sent (master mode) or when the received slave address matched with one of the enabled slave address (slave mode).
+  * @rmtoll SR1          ADDR          LL_I2C_IsActiveFlag_ADDR
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ADDR(I2C_TypeDef *I2Cx)
+{
+  return (READ_BIT(I2Cx->SR1, I2C_SR1_ADDR) == (I2C_SR1_ADDR));
+}
+
+/**
+  * @brief  Indicate the status of 10-bit header sent (master mode).
+  * @note   RESET: When no ADD10 event occurred.
+  *         SET: When the master has sent the first address byte (header).
+  * @rmtoll SR1          ADD10         LL_I2C_IsActiveFlag_ADD10
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ADD10(I2C_TypeDef *I2Cx)
+{
+  return (READ_BIT(I2Cx->SR1, I2C_SR1_ADD10) == (I2C_SR1_ADD10));
+}
+
+/**
+  * @brief  Indicate the status of Acknowledge failure flag.
+  * @note   RESET: No acknowledge failure.
+  *         SET: When an acknowledge failure is received after a byte transmission.
+  * @rmtoll SR1          AF            LL_I2C_IsActiveFlag_AF
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_AF(I2C_TypeDef *I2Cx)
+{
+  return (READ_BIT(I2Cx->SR1, I2C_SR1_AF) == (I2C_SR1_AF));
+}
+
+/**
+  * @brief  Indicate the status of Stop detection flag (slave mode).
+  * @note   RESET: Clear default value.
+  *         SET: When a Stop condition is detected.
+  * @rmtoll SR1          STOPF         LL_I2C_IsActiveFlag_STOP
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_STOP(I2C_TypeDef *I2Cx)
+{
+  return (READ_BIT(I2Cx->SR1, I2C_SR1_STOPF) == (I2C_SR1_STOPF));
+}
+
+/**
+  * @brief  Indicate the status of Bus error flag.
+  * @note   RESET: Clear default value.
+  *         SET: When a misplaced Start or Stop condition is detected.
+  * @rmtoll SR1          BERR          LL_I2C_IsActiveFlag_BERR
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BERR(I2C_TypeDef *I2Cx)
+{
+  return (READ_BIT(I2Cx->SR1, I2C_SR1_BERR) == (I2C_SR1_BERR));
+}
+
+/**
+  * @brief  Indicate the status of Arbitration lost flag.
+  * @note   RESET: Clear default value.
+  *         SET: When arbitration lost.
+  * @rmtoll SR1          ARLO          LL_I2C_IsActiveFlag_ARLO
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ARLO(I2C_TypeDef *I2Cx)
+{
+  return (READ_BIT(I2Cx->SR1, I2C_SR1_ARLO) == (I2C_SR1_ARLO));
+}
+
+/**
+  * @brief  Indicate the status of Overrun/Underrun flag.
+  * @note   RESET: Clear default value.
+  *         SET: When an overrun/underrun error occurs (Clock Stretching Disabled).
+  * @rmtoll SR1          OVR           LL_I2C_IsActiveFlag_OVR
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_OVR(I2C_TypeDef *I2Cx)
+{
+  return (READ_BIT(I2Cx->SR1, I2C_SR1_OVR) == (I2C_SR1_OVR));
+}
+
+/**
+  * @brief  Indicate the status of SMBus PEC error flag in reception.
+  * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+  *         SMBus feature is supported by the I2Cx Instance.
+  * @rmtoll SR1          PECERR        LL_I2C_IsActiveSMBusFlag_PECERR
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_PECERR(I2C_TypeDef *I2Cx)
+{
+  return (READ_BIT(I2Cx->SR1, I2C_SR1_PECERR) == (I2C_SR1_PECERR));
+}
+
+/**
+  * @brief  Indicate the status of SMBus Timeout detection flag.
+  * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+  *         SMBus feature is supported by the I2Cx Instance.
+  * @rmtoll SR1          TIMEOUT       LL_I2C_IsActiveSMBusFlag_TIMEOUT
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_TIMEOUT(I2C_TypeDef *I2Cx)
+{
+  return (READ_BIT(I2Cx->SR1, I2C_SR1_TIMEOUT) == (I2C_SR1_TIMEOUT));
+}
+
+/**
+  * @brief  Indicate the status of SMBus alert flag.
+  * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+  *         SMBus feature is supported by the I2Cx Instance.
+  * @rmtoll SR1          SMBALERT      LL_I2C_IsActiveSMBusFlag_ALERT
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_ALERT(I2C_TypeDef *I2Cx)
+{
+  return (READ_BIT(I2Cx->SR1, I2C_SR1_SMBALERT) == (I2C_SR1_SMBALERT));
+}
+
+/**
+  * @brief  Indicate the status of Bus Busy flag.
+  * @note   RESET: Clear default value.
+  *         SET: When a Start condition is detected.
+  * @rmtoll SR2          BUSY          LL_I2C_IsActiveFlag_BUSY
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BUSY(I2C_TypeDef *I2Cx)
+{
+  return (READ_BIT(I2Cx->SR2, I2C_SR2_BUSY) == (I2C_SR2_BUSY));
+}
+
+/**
+  * @brief  Indicate the status of Dual flag.
+  * @note   RESET: Received address matched with OAR1.
+  *         SET: Received address matched with OAR2.
+  * @rmtoll SR2          DUALF         LL_I2C_IsActiveFlag_DUAL
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_DUAL(I2C_TypeDef *I2Cx)
+{
+  return (READ_BIT(I2Cx->SR2, I2C_SR2_DUALF) == (I2C_SR2_DUALF));
+}
+
+/**
+  * @brief  Indicate the status of SMBus Host address reception (Slave mode).
+  * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+  *         SMBus feature is supported by the I2Cx Instance.
+  * @note   RESET: No SMBus Host address
+  *         SET: SMBus Host address received.
+  * @note   This status is cleared by hardware after a STOP condition or repeated START condition.
+  * @rmtoll SR2          SMBHOST       LL_I2C_IsActiveSMBusFlag_SMBHOST
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_SMBHOST(I2C_TypeDef *I2Cx)
+{
+  return (READ_BIT(I2Cx->SR2, I2C_SR2_SMBHOST) == (I2C_SR2_SMBHOST));
+}
+
+/**
+  * @brief  Indicate the status of SMBus Device default address reception (Slave mode).
+  * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+  *         SMBus feature is supported by the I2Cx Instance.
+  * @note   RESET: No SMBus Device default address
+  *         SET: SMBus Device default address received.
+  * @note   This status is cleared by hardware after a STOP condition or repeated START condition.
+  * @rmtoll SR2          SMBDEFAULT    LL_I2C_IsActiveSMBusFlag_SMBDEFAULT
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_SMBDEFAULT(I2C_TypeDef *I2Cx)
+{
+  return (READ_BIT(I2Cx->SR2, I2C_SR2_SMBDEFAULT) == (I2C_SR2_SMBDEFAULT));
+}
+
+/**
+  * @brief  Indicate the status of General call address reception (Slave mode).
+  * @note   RESET: No General call address
+  *         SET: General call address received.
+  * @note   This status is cleared by hardware after a STOP condition or repeated START condition.
+  * @rmtoll SR2          GENCALL       LL_I2C_IsActiveFlag_GENCALL
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_GENCALL(I2C_TypeDef *I2Cx)
+{
+  return (READ_BIT(I2Cx->SR2, I2C_SR2_GENCALL) == (I2C_SR2_GENCALL));
+}
+
+/**
+  * @brief  Indicate the status of Master/Slave flag.
+  * @note   RESET: Slave Mode.
+  *         SET: Master Mode.
+  * @rmtoll SR2          MSL           LL_I2C_IsActiveFlag_MSL
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_MSL(I2C_TypeDef *I2Cx)
+{
+  return (READ_BIT(I2Cx->SR2, I2C_SR2_MSL) == (I2C_SR2_MSL));
+}
+
+/**
+  * @brief  Clear Address Matched flag.
+  * @note   Clearing this flag is done by a read access to the I2Cx_SR1
+  *         register followed by a read access to the I2Cx_SR2 register.
+  * @rmtoll SR1          ADDR          LL_I2C_ClearFlag_ADDR
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_ClearFlag_ADDR(I2C_TypeDef *I2Cx)
+{
+  __IO uint32_t tmpreg;
+  tmpreg = I2Cx->SR1;
+  (void) tmpreg;
+  tmpreg = I2Cx->SR2;
+  (void) tmpreg;
+}
+
+/**
+  * @brief  Clear Acknowledge failure flag.
+  * @rmtoll SR1          AF            LL_I2C_ClearFlag_AF
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_ClearFlag_AF(I2C_TypeDef *I2Cx)
+{
+  CLEAR_BIT(I2Cx->SR1, I2C_SR1_AF);
+}
+
+/**
+  * @brief  Clear Stop detection flag.
+  * @note   Clearing this flag is done by a read access to the I2Cx_SR1
+  *         register followed by a write access to I2Cx_CR1 register.
+  * @rmtoll SR1          STOPF         LL_I2C_ClearFlag_STOP\n
+  *         CR1          PE            LL_I2C_ClearFlag_STOP
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_ClearFlag_STOP(I2C_TypeDef *I2Cx)
+{
+  __IO uint32_t tmpreg;
+  tmpreg = I2Cx->SR1;
+  (void) tmpreg;
+  SET_BIT(I2Cx->CR1, I2C_CR1_PE);
+}
+
+/**
+  * @brief  Clear Bus error flag.
+  * @rmtoll SR1          BERR          LL_I2C_ClearFlag_BERR
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_ClearFlag_BERR(I2C_TypeDef *I2Cx)
+{
+  CLEAR_BIT(I2Cx->SR1, I2C_SR1_BERR);
+}
+
+/**
+  * @brief  Clear Arbitration lost flag.
+  * @rmtoll SR1          ARLO          LL_I2C_ClearFlag_ARLO
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_ClearFlag_ARLO(I2C_TypeDef *I2Cx)
+{
+  CLEAR_BIT(I2Cx->SR1, I2C_SR1_ARLO);
+}
+
+/**
+  * @brief  Clear Overrun/Underrun flag.
+  * @rmtoll SR1          OVR           LL_I2C_ClearFlag_OVR
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_ClearFlag_OVR(I2C_TypeDef *I2Cx)
+{
+  CLEAR_BIT(I2Cx->SR1, I2C_SR1_OVR);
+}
+
+/**
+  * @brief  Clear SMBus PEC error flag.
+  * @rmtoll SR1          PECERR        LL_I2C_ClearSMBusFlag_PECERR
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_ClearSMBusFlag_PECERR(I2C_TypeDef *I2Cx)
+{
+  CLEAR_BIT(I2Cx->SR1, I2C_SR1_PECERR);
+}
+
+/**
+  * @brief  Clear SMBus Timeout detection flag.
+  * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+  *         SMBus feature is supported by the I2Cx Instance.
+  * @rmtoll SR1          TIMEOUT       LL_I2C_ClearSMBusFlag_TIMEOUT
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_ClearSMBusFlag_TIMEOUT(I2C_TypeDef *I2Cx)
+{
+  CLEAR_BIT(I2Cx->SR1, I2C_SR1_TIMEOUT);
+}
+
+/**
+  * @brief  Clear SMBus Alert flag.
+  * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+  *         SMBus feature is supported by the I2Cx Instance.
+  * @rmtoll SR1          SMBALERT      LL_I2C_ClearSMBusFlag_ALERT
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_ClearSMBusFlag_ALERT(I2C_TypeDef *I2Cx)
+{
+  CLEAR_BIT(I2Cx->SR1, I2C_SR1_SMBALERT);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup I2C_LL_EF_Data_Management Data_Management
+  * @{
+  */
+
+/**
+  * @brief  Enable Reset of I2C peripheral.
+  * @rmtoll CR1          SWRST         LL_I2C_EnableReset
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_EnableReset(I2C_TypeDef *I2Cx)
+{
+  SET_BIT(I2Cx->CR1, I2C_CR1_SWRST);
+}
+
+/**
+  * @brief  Disable Reset of I2C peripheral.
+  * @rmtoll CR1          SWRST         LL_I2C_DisableReset
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_DisableReset(I2C_TypeDef *I2Cx)
+{
+  CLEAR_BIT(I2Cx->CR1, I2C_CR1_SWRST);
+}
+
+/**
+  * @brief  Check if the I2C peripheral is under reset state or not.
+  * @rmtoll CR1          SWRST         LL_I2C_IsResetEnabled
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsResetEnabled(I2C_TypeDef *I2Cx)
+{
+  return (READ_BIT(I2Cx->CR1, I2C_CR1_SWRST) == (I2C_CR1_SWRST));
+}
+
+/**
+  * @brief  Prepare the generation of a ACKnowledge or Non ACKnowledge condition after the address receive match code or next received byte.
+  * @note   Usage in Slave or Master mode.
+  * @rmtoll CR1          ACK           LL_I2C_AcknowledgeNextData
+  * @param  I2Cx I2C Instance.
+  * @param  TypeAcknowledge This parameter can be one of the following values:
+  *         @arg @ref LL_I2C_ACK
+  *         @arg @ref LL_I2C_NACK
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_AcknowledgeNextData(I2C_TypeDef *I2Cx, uint32_t TypeAcknowledge)
+{
+  MODIFY_REG(I2Cx->CR1, I2C_CR1_ACK, TypeAcknowledge);
+}
+
+/**
+  * @brief  Generate a START or RESTART condition
+  * @note   The START bit can be set even if bus is BUSY or I2C is in slave mode.
+  *         This action has no effect when RELOAD is set.
+  * @rmtoll CR1          START         LL_I2C_GenerateStartCondition
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_GenerateStartCondition(I2C_TypeDef *I2Cx)
+{
+  SET_BIT(I2Cx->CR1, I2C_CR1_START);
+}
+
+/**
+  * @brief  Generate a STOP condition after the current byte transfer (master mode).
+  * @rmtoll CR1          STOP          LL_I2C_GenerateStopCondition
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_GenerateStopCondition(I2C_TypeDef *I2Cx)
+{
+  SET_BIT(I2Cx->CR1, I2C_CR1_STOP);
+}
+
+/**
+  * @brief  Enable bit POS (master/host mode).
+  * @note   In that case, the ACK bit controls the (N)ACK of the next byte received or the PEC bit indicates that the next byte in shift register is a PEC.
+  * @rmtoll CR1          POS           LL_I2C_EnableBitPOS
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_EnableBitPOS(I2C_TypeDef *I2Cx)
+{
+  SET_BIT(I2Cx->CR1, I2C_CR1_POS);
+}
+
+/**
+  * @brief  Disable bit POS (master/host mode).
+  * @note   In that case, the ACK bit controls the (N)ACK of the current byte received or the PEC bit indicates that the current byte in shift register is a PEC.
+  * @rmtoll CR1          POS           LL_I2C_DisableBitPOS
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_DisableBitPOS(I2C_TypeDef *I2Cx)
+{
+  CLEAR_BIT(I2Cx->CR1, I2C_CR1_POS);
+}
+
+/**
+  * @brief  Check if bit POS  is enabled or disabled.
+  * @rmtoll CR1          POS           LL_I2C_IsEnabledBitPOS
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledBitPOS(I2C_TypeDef *I2Cx)
+{
+  return (READ_BIT(I2Cx->CR1, I2C_CR1_POS) == (I2C_CR1_POS));
+}
+
+/**
+  * @brief  Indicate the value of transfer direction.
+  * @note   RESET: Bus is in read transfer (peripheral point of view).
+  *         SET: Bus is in write transfer (peripheral point of view).
+  * @rmtoll SR2          TRA           LL_I2C_GetTransferDirection
+  * @param  I2Cx I2C Instance.
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_I2C_DIRECTION_WRITE
+  *         @arg @ref LL_I2C_DIRECTION_READ
+  */
+__STATIC_INLINE uint32_t LL_I2C_GetTransferDirection(I2C_TypeDef *I2Cx)
+{
+  return (uint32_t)(READ_BIT(I2Cx->SR2, I2C_SR2_TRA));
+}
+
+/**
+  * @brief  Enable DMA last transfer.
+  * @note   This action mean that next DMA EOT is the last transfer.
+  * @rmtoll CR2          LAST          LL_I2C_EnableLastDMA
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_EnableLastDMA(I2C_TypeDef *I2Cx)
+{
+  SET_BIT(I2Cx->CR2, I2C_CR2_LAST);
+}
+
+/**
+  * @brief  Disable DMA last transfer.
+  * @note   This action mean that next DMA EOT is not the last transfer.
+  * @rmtoll CR2          LAST          LL_I2C_DisableLastDMA
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_DisableLastDMA(I2C_TypeDef *I2Cx)
+{
+  CLEAR_BIT(I2Cx->CR2, I2C_CR2_LAST);
+}
+
+/**
+  * @brief  Check if DMA last transfer is enabled or disabled.
+  * @rmtoll CR2          LAST          LL_I2C_IsEnabledLastDMA
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledLastDMA(I2C_TypeDef *I2Cx)
+{
+  return (READ_BIT(I2Cx->CR2, I2C_CR2_LAST) == (I2C_CR2_LAST));
+}
+
+/**
+  * @brief  Enable transfer or internal comparison of the SMBus Packet Error byte (transmission or reception mode).
+  * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+  *         SMBus feature is supported by the I2Cx Instance.
+  * @note   This feature is cleared by hardware when the PEC byte is transferred or compared,
+  *         or by a START or STOP condition, it is also cleared by software.
+  * @rmtoll CR1          PEC           LL_I2C_EnableSMBusPECCompare
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_EnableSMBusPECCompare(I2C_TypeDef *I2Cx)
+{
+  SET_BIT(I2Cx->CR1, I2C_CR1_PEC);
+}
+
+/**
+  * @brief  Disable transfer or internal comparison of the SMBus Packet Error byte (transmission or reception mode).
+  * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+  *         SMBus feature is supported by the I2Cx Instance.
+  * @rmtoll CR1          PEC           LL_I2C_DisableSMBusPECCompare
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_DisableSMBusPECCompare(I2C_TypeDef *I2Cx)
+{
+  CLEAR_BIT(I2Cx->CR1, I2C_CR1_PEC);
+}
+
+/**
+  * @brief  Check if the SMBus Packet Error byte transfer or internal comparison is requested or not.
+  * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+  *         SMBus feature is supported by the I2Cx Instance.
+  * @rmtoll CR1          PEC           LL_I2C_IsEnabledSMBusPECCompare
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPECCompare(I2C_TypeDef *I2Cx)
+{
+  return (READ_BIT(I2Cx->CR1, I2C_CR1_PEC) == (I2C_CR1_PEC));
+}
+
+/**
+  * @brief  Get the SMBus Packet Error byte calculated.
+  * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+  *         SMBus feature is supported by the I2Cx Instance.
+  * @rmtoll SR2          PEC           LL_I2C_GetSMBusPEC
+  * @param  I2Cx I2C Instance.
+  * @retval Value between Min_Data=0x00 and Max_Data=0xFF
+  */
+__STATIC_INLINE uint32_t LL_I2C_GetSMBusPEC(I2C_TypeDef *I2Cx)
+{
+  return (uint32_t)(READ_BIT(I2Cx->SR2, I2C_SR2_PEC) >> I2C_SR2_PEC_Pos);
+}
+
+/**
+  * @brief  Read Receive Data register.
+  * @rmtoll DR           DR            LL_I2C_ReceiveData8
+  * @param  I2Cx I2C Instance.
+  * @retval Value between Min_Data=0x0 and Max_Data=0xFF
+  */
+__STATIC_INLINE uint8_t LL_I2C_ReceiveData8(I2C_TypeDef *I2Cx)
+{
+  return (uint8_t)(READ_BIT(I2Cx->DR, I2C_DR_DR));
+}
+
+/**
+  * @brief  Write in Transmit Data Register .
+  * @rmtoll DR           DR            LL_I2C_TransmitData8
+  * @param  I2Cx I2C Instance.
+  * @param  Data Value between Min_Data=0x0 and Max_Data=0xFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_TransmitData8(I2C_TypeDef *I2Cx, uint8_t Data)
+{
+  MODIFY_REG(I2Cx->DR, I2C_DR_DR, Data);
+}
+
+/**
+  * @}
+  */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup I2C_LL_EF_Init Initialization and de-initialization functions
+  * @{
+  */
+
+uint32_t LL_I2C_Init(I2C_TypeDef *I2Cx, LL_I2C_InitTypeDef *I2C_InitStruct);
+uint32_t LL_I2C_DeInit(I2C_TypeDef *I2Cx);
+void LL_I2C_StructInit(LL_I2C_InitTypeDef *I2C_InitStruct);
+
+
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* I2C1 || I2C2 || I2C3 */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_LL_I2C_H */
+
diff --git a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_pwr.h b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_pwr.h
new file mode 100644
index 0000000..f40e079
--- /dev/null
+++ b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_pwr.h
@@ -0,0 +1,985 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_ll_pwr.h
+  * @author  MCD Application Team
+  * @brief   Header file of PWR LL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file in
+  * the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_LL_PWR_H
+#define __STM32F4xx_LL_PWR_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx.h"
+
+/** @addtogroup STM32F4xx_LL_Driver
+  * @{
+  */
+
+#if defined(PWR)
+
+/** @defgroup PWR_LL PWR
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup PWR_LL_Exported_Constants PWR Exported Constants
+  * @{
+  */
+
+/** @defgroup PWR_LL_EC_CLEAR_FLAG Clear Flags Defines
+  * @brief    Flags defines which can be used with LL_PWR_WriteReg function
+  * @{
+  */
+#define LL_PWR_CR_CSBF                     PWR_CR_CSBF            /*!< Clear standby flag */
+#define LL_PWR_CR_CWUF                     PWR_CR_CWUF            /*!< Clear wakeup flag */
+/**
+  * @}
+  */
+
+/** @defgroup PWR_LL_EC_GET_FLAG Get Flags Defines
+  * @brief    Flags defines which can be used with LL_PWR_ReadReg function
+  * @{
+  */
+#define LL_PWR_CSR_WUF                     PWR_CSR_WUF            /*!< Wakeup flag */
+#define LL_PWR_CSR_SBF                     PWR_CSR_SBF            /*!< Standby flag */
+#define LL_PWR_CSR_PVDO                    PWR_CSR_PVDO           /*!< Power voltage detector output flag */
+#define LL_PWR_CSR_VOS                     PWR_CSR_VOSRDY            /*!< Voltage scaling select flag */
+#if defined(PWR_CSR_EWUP)
+#define LL_PWR_CSR_EWUP1                   PWR_CSR_EWUP           /*!< Enable WKUP pin */
+#elif defined(PWR_CSR_EWUP1)
+#define LL_PWR_CSR_EWUP1                   PWR_CSR_EWUP1          /*!< Enable WKUP pin 1 */
+#endif /* PWR_CSR_EWUP */
+#if defined(PWR_CSR_EWUP2)
+#define LL_PWR_CSR_EWUP2                   PWR_CSR_EWUP2          /*!< Enable WKUP pin 2 */
+#endif /* PWR_CSR_EWUP2 */
+#if defined(PWR_CSR_EWUP3)
+#define LL_PWR_CSR_EWUP3                   PWR_CSR_EWUP3          /*!< Enable WKUP pin 3 */
+#endif /* PWR_CSR_EWUP3 */
+/**
+  * @}
+  */
+
+/** @defgroup PWR_LL_EC_REGU_VOLTAGE Regulator Voltage
+  * @{
+  */
+#if defined(PWR_CR_VOS_0)
+#define LL_PWR_REGU_VOLTAGE_SCALE3         (PWR_CR_VOS_0)
+#define LL_PWR_REGU_VOLTAGE_SCALE2         (PWR_CR_VOS_1)
+#define LL_PWR_REGU_VOLTAGE_SCALE1         (PWR_CR_VOS_0 | PWR_CR_VOS_1) /* The SCALE1 is not available for STM32F401xx devices */
+#else
+#define LL_PWR_REGU_VOLTAGE_SCALE1         (PWR_CR_VOS)
+#define LL_PWR_REGU_VOLTAGE_SCALE2         0x00000000U
+#endif /* PWR_CR_VOS_0 */
+/**
+  * @}
+  */
+
+/** @defgroup PWR_LL_EC_MODE_PWR Mode Power
+  * @{
+  */
+#define LL_PWR_MODE_STOP_MAINREGU             0x00000000U                    /*!< Enter Stop mode when the CPU enters deepsleep */
+#define LL_PWR_MODE_STOP_LPREGU               (PWR_CR_LPDS)                  /*!< Enter Stop mode (with low power Regulator ON) when the CPU enters deepsleep */
+#if defined(PWR_CR_MRUDS) && defined(PWR_CR_LPUDS) && defined(PWR_CR_FPDS)
+#define LL_PWR_MODE_STOP_MAINREGU_UNDERDRIVE  (PWR_CR_MRUDS | PWR_CR_FPDS)                 /*!< Enter Stop mode (with main Regulator in under-drive mode) when the CPU enters deepsleep */
+#define LL_PWR_MODE_STOP_LPREGU_UNDERDRIVE    (PWR_CR_LPDS | PWR_CR_LPUDS | PWR_CR_FPDS)   /*!< Enter Stop mode (with low power Regulator in under-drive mode) when the CPU enters deepsleep */
+#endif /* PWR_CR_MRUDS && PWR_CR_LPUDS && PWR_CR_FPDS */
+#if defined(PWR_CR_MRLVDS) && defined(PWR_CR_LPLVDS) && defined(PWR_CR_FPDS)
+#define LL_PWR_MODE_STOP_MAINREGU_DEEPSLEEP  (PWR_CR_MRLVDS | PWR_CR_FPDS)                 /*!< Enter Stop mode (with main Regulator in Deep Sleep mode) when the CPU enters deepsleep */
+#define LL_PWR_MODE_STOP_LPREGU_DEEPSLEEP    (PWR_CR_LPDS | PWR_CR_LPLVDS | PWR_CR_FPDS)   /*!< Enter Stop mode (with low power Regulator in Deep Sleep mode) when the CPU enters deepsleep */
+#endif /* PWR_CR_MRLVDS && PWR_CR_LPLVDS && PWR_CR_FPDS */
+#define LL_PWR_MODE_STANDBY                   (PWR_CR_PDDS)                  /*!< Enter Standby mode when the CPU enters deepsleep */
+/**
+  * @}
+  */
+
+/** @defgroup PWR_LL_EC_REGU_MODE_DS_MODE  Regulator Mode In Deep Sleep Mode
+ * @{
+ */
+#define LL_PWR_REGU_DSMODE_MAIN        0x00000000U           /*!< Voltage Regulator in main mode during deepsleep mode */
+#define LL_PWR_REGU_DSMODE_LOW_POWER   (PWR_CR_LPDS)         /*!< Voltage Regulator in low-power mode during deepsleep mode */
+/**
+  * @}
+  */
+
+/** @defgroup PWR_LL_EC_PVDLEVEL Power Voltage Detector Level
+  * @{
+  */
+#define LL_PWR_PVDLEVEL_0                  (PWR_CR_PLS_LEV0)      /*!< Voltage threshold detected by PVD 2.2 V */
+#define LL_PWR_PVDLEVEL_1                  (PWR_CR_PLS_LEV1)      /*!< Voltage threshold detected by PVD 2.3 V */
+#define LL_PWR_PVDLEVEL_2                  (PWR_CR_PLS_LEV2)      /*!< Voltage threshold detected by PVD 2.4 V */
+#define LL_PWR_PVDLEVEL_3                  (PWR_CR_PLS_LEV3)      /*!< Voltage threshold detected by PVD 2.5 V */
+#define LL_PWR_PVDLEVEL_4                  (PWR_CR_PLS_LEV4)      /*!< Voltage threshold detected by PVD 2.6 V */
+#define LL_PWR_PVDLEVEL_5                  (PWR_CR_PLS_LEV5)      /*!< Voltage threshold detected by PVD 2.7 V */
+#define LL_PWR_PVDLEVEL_6                  (PWR_CR_PLS_LEV6)      /*!< Voltage threshold detected by PVD 2.8 V */
+#define LL_PWR_PVDLEVEL_7                  (PWR_CR_PLS_LEV7)      /*!< Voltage threshold detected by PVD 2.9 V */
+/**
+  * @}
+  */
+/** @defgroup PWR_LL_EC_WAKEUP_PIN  Wakeup Pins
+  * @{
+  */
+#if defined(PWR_CSR_EWUP)
+#define LL_PWR_WAKEUP_PIN1                 (PWR_CSR_EWUP)         /*!< WKUP pin : PA0 */
+#endif /* PWR_CSR_EWUP */
+#if defined(PWR_CSR_EWUP1)
+#define LL_PWR_WAKEUP_PIN1                 (PWR_CSR_EWUP1)        /*!< WKUP pin 1 : PA0 */
+#endif /* PWR_CSR_EWUP1 */
+#if defined(PWR_CSR_EWUP2)
+#define LL_PWR_WAKEUP_PIN2                 (PWR_CSR_EWUP2)        /*!< WKUP pin 2 : PC0 or PC13 according to device */
+#endif /* PWR_CSR_EWUP2 */
+#if defined(PWR_CSR_EWUP3)
+#define LL_PWR_WAKEUP_PIN3                 (PWR_CSR_EWUP3)        /*!< WKUP pin 3 : PC1 */
+#endif /* PWR_CSR_EWUP3 */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup PWR_LL_Exported_Macros PWR Exported Macros
+  * @{
+  */
+
+/** @defgroup PWR_LL_EM_WRITE_READ Common write and read registers Macros
+  * @{
+  */
+
+/**
+  * @brief  Write a value in PWR register
+  * @param  __REG__ Register to be written
+  * @param  __VALUE__ Value to be written in the register
+  * @retval None
+  */
+#define LL_PWR_WriteReg(__REG__, __VALUE__) WRITE_REG(PWR->__REG__, (__VALUE__))
+
+/**
+  * @brief  Read a value in PWR register
+  * @param  __REG__ Register to be read
+  * @retval Register value
+  */
+#define LL_PWR_ReadReg(__REG__) READ_REG(PWR->__REG__)
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup PWR_LL_Exported_Functions PWR Exported Functions
+  * @{
+  */
+
+/** @defgroup PWR_LL_EF_Configuration Configuration
+  * @{
+  */
+#if defined(PWR_CR_FISSR)
+/**
+  * @brief  Enable FLASH interface STOP while system Run is ON
+  * @rmtoll CR    FISSR       LL_PWR_EnableFLASHInterfaceSTOP
+  * @note  This mode is enabled only with STOP low power mode.
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_EnableFLASHInterfaceSTOP(void)
+{
+  SET_BIT(PWR->CR, PWR_CR_FISSR);
+}
+
+/**
+  * @brief  Disable FLASH Interface STOP while system Run is ON
+  * @rmtoll CR    FISSR       LL_PWR_DisableFLASHInterfaceSTOP
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_DisableFLASHInterfaceSTOP(void)
+{
+  CLEAR_BIT(PWR->CR, PWR_CR_FISSR);
+}
+
+/**
+  * @brief  Check if FLASH Interface STOP while system Run feature is enabled
+  * @rmtoll CR    FISSR       LL_PWR_IsEnabledFLASHInterfaceSTOP
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledFLASHInterfaceSTOP(void)
+{
+  return (READ_BIT(PWR->CR, PWR_CR_FISSR) == (PWR_CR_FISSR));
+}
+#endif /* PWR_CR_FISSR */
+
+#if defined(PWR_CR_FMSSR)
+/**
+  * @brief  Enable FLASH Memory STOP while system Run is ON
+  * @rmtoll CR    FMSSR       LL_PWR_EnableFLASHMemorySTOP
+  * @note  This mode is enabled only with STOP low power mode.
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_EnableFLASHMemorySTOP(void)
+{
+  SET_BIT(PWR->CR, PWR_CR_FMSSR);
+}
+
+/**
+  * @brief  Disable FLASH Memory STOP while system Run is ON
+  * @rmtoll CR    FMSSR       LL_PWR_DisableFLASHMemorySTOP
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_DisableFLASHMemorySTOP(void)
+{
+  CLEAR_BIT(PWR->CR, PWR_CR_FMSSR);
+}
+
+/**
+  * @brief  Check if FLASH Memory STOP while system Run feature is enabled
+  * @rmtoll CR    FMSSR       LL_PWR_IsEnabledFLASHMemorySTOP
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledFLASHMemorySTOP(void)
+{
+  return (READ_BIT(PWR->CR, PWR_CR_FMSSR) == (PWR_CR_FMSSR));
+}
+#endif /* PWR_CR_FMSSR */
+#if defined(PWR_CR_UDEN)
+/**
+  * @brief  Enable Under Drive Mode
+  * @rmtoll CR    UDEN       LL_PWR_EnableUnderDriveMode
+  * @note  This mode is enabled only with STOP low power mode.
+  *        In this mode, the 1.2V domain is preserved in reduced leakage mode. This 
+  *        mode is only available when the main Regulator or the low power Regulator 
+  *        is in low voltage mode.      
+  * @note  If the Under-drive mode was enabled, it is automatically disabled after 
+  *        exiting Stop mode. 
+  *        When the voltage Regulator operates in Under-drive mode, an additional  
+  *        startup delay is induced when waking up from Stop mode.
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_EnableUnderDriveMode(void)
+{
+  SET_BIT(PWR->CR, PWR_CR_UDEN);
+}
+
+/**
+  * @brief  Disable Under Drive Mode
+  * @rmtoll CR    UDEN       LL_PWR_DisableUnderDriveMode
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_DisableUnderDriveMode(void)
+{
+  CLEAR_BIT(PWR->CR, PWR_CR_UDEN);
+}
+
+/**
+  * @brief  Check if Under Drive Mode is enabled
+  * @rmtoll CR    UDEN       LL_PWR_IsEnabledUnderDriveMode
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledUnderDriveMode(void)
+{
+  return (READ_BIT(PWR->CR, PWR_CR_UDEN) == (PWR_CR_UDEN));
+}
+#endif /* PWR_CR_UDEN */
+
+#if defined(PWR_CR_ODSWEN)
+/**
+  * @brief  Enable Over drive switching
+  * @rmtoll CR    ODSWEN       LL_PWR_EnableOverDriveSwitching
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_EnableOverDriveSwitching(void)
+{
+  SET_BIT(PWR->CR, PWR_CR_ODSWEN);
+}
+
+/**
+  * @brief  Disable Over drive switching
+  * @rmtoll CR    ODSWEN       LL_PWR_DisableOverDriveSwitching
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_DisableOverDriveSwitching(void)
+{
+  CLEAR_BIT(PWR->CR, PWR_CR_ODSWEN);
+}
+
+/**
+  * @brief  Check if Over drive switching is enabled
+  * @rmtoll CR    ODSWEN       LL_PWR_IsEnabledOverDriveSwitching
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledOverDriveSwitching(void)
+{
+  return (READ_BIT(PWR->CR, PWR_CR_ODSWEN) == (PWR_CR_ODSWEN));
+}
+#endif /* PWR_CR_ODSWEN */
+#if defined(PWR_CR_ODEN)
+/**
+  * @brief  Enable Over drive Mode
+  * @rmtoll CR    ODEN       LL_PWR_EnableOverDriveMode
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_EnableOverDriveMode(void)
+{
+  SET_BIT(PWR->CR, PWR_CR_ODEN);
+}
+
+/**
+  * @brief  Disable Over drive Mode
+  * @rmtoll CR    ODEN       LL_PWR_DisableOverDriveMode
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_DisableOverDriveMode(void)
+{
+  CLEAR_BIT(PWR->CR, PWR_CR_ODEN);
+}
+
+/**
+  * @brief  Check if Over drive switching is enabled
+  * @rmtoll CR    ODEN       LL_PWR_IsEnabledOverDriveMode
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledOverDriveMode(void)
+{
+  return (READ_BIT(PWR->CR, PWR_CR_ODEN) == (PWR_CR_ODEN));
+}
+#endif /* PWR_CR_ODEN */
+#if defined(PWR_CR_MRUDS)
+/**
+  * @brief  Enable Main Regulator in deepsleep under-drive Mode
+  * @rmtoll CR    MRUDS       LL_PWR_EnableMainRegulatorDeepSleepUDMode
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_EnableMainRegulatorDeepSleepUDMode(void)
+{
+  SET_BIT(PWR->CR, PWR_CR_MRUDS);
+}
+
+/**
+  * @brief  Disable Main Regulator in deepsleep under-drive Mode
+  * @rmtoll CR    MRUDS       LL_PWR_DisableMainRegulatorDeepSleepUDMode
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_DisableMainRegulatorDeepSleepUDMode(void)
+{
+  CLEAR_BIT(PWR->CR, PWR_CR_MRUDS);
+}
+
+/**
+  * @brief  Check if Main Regulator in deepsleep under-drive Mode is enabled
+  * @rmtoll CR    MRUDS       LL_PWR_IsEnabledMainRegulatorDeepSleepUDMode
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledMainRegulatorDeepSleepUDMode(void)
+{
+  return (READ_BIT(PWR->CR, PWR_CR_MRUDS) == (PWR_CR_MRUDS));
+}
+#endif /* PWR_CR_MRUDS */
+
+#if defined(PWR_CR_LPUDS)
+/**
+  * @brief  Enable Low Power Regulator in deepsleep under-drive Mode
+  * @rmtoll CR    LPUDS       LL_PWR_EnableLowPowerRegulatorDeepSleepUDMode
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_EnableLowPowerRegulatorDeepSleepUDMode(void)
+{
+  SET_BIT(PWR->CR, PWR_CR_LPUDS);
+}
+
+/**
+  * @brief  Disable Low Power Regulator in deepsleep under-drive Mode
+  * @rmtoll CR    LPUDS       LL_PWR_DisableLowPowerRegulatorDeepSleepUDMode
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_DisableLowPowerRegulatorDeepSleepUDMode(void)
+{
+  CLEAR_BIT(PWR->CR, PWR_CR_LPUDS);
+}
+
+/**
+  * @brief  Check if Low Power Regulator in deepsleep under-drive Mode is enabled
+  * @rmtoll CR    LPUDS       LL_PWR_IsEnabledLowPowerRegulatorDeepSleepUDMode
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledLowPowerRegulatorDeepSleepUDMode(void)
+{
+  return (READ_BIT(PWR->CR, PWR_CR_LPUDS) == (PWR_CR_LPUDS));
+}
+#endif /* PWR_CR_LPUDS */
+
+#if defined(PWR_CR_MRLVDS)
+/**
+  * @brief  Enable Main Regulator low voltage Mode
+  * @rmtoll CR    MRLVDS       LL_PWR_EnableMainRegulatorLowVoltageMode
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_EnableMainRegulatorLowVoltageMode(void)
+{
+  SET_BIT(PWR->CR, PWR_CR_MRLVDS);
+}
+
+/**
+  * @brief  Disable Main Regulator low voltage Mode
+  * @rmtoll CR    MRLVDS       LL_PWR_DisableMainRegulatorLowVoltageMode
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_DisableMainRegulatorLowVoltageMode(void)
+{
+  CLEAR_BIT(PWR->CR, PWR_CR_MRLVDS);
+}
+
+/**
+  * @brief  Check if Main Regulator low voltage Mode is enabled
+  * @rmtoll CR    MRLVDS       LL_PWR_IsEnabledMainRegulatorLowVoltageMode
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledMainRegulatorLowVoltageMode(void)
+{
+  return (READ_BIT(PWR->CR, PWR_CR_MRLVDS) == (PWR_CR_MRLVDS));
+}
+#endif /* PWR_CR_MRLVDS */
+
+#if defined(PWR_CR_LPLVDS)
+/**
+  * @brief  Enable Low Power Regulator low voltage Mode
+  * @rmtoll CR    LPLVDS       LL_PWR_EnableLowPowerRegulatorLowVoltageMode
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_EnableLowPowerRegulatorLowVoltageMode(void)
+{
+  SET_BIT(PWR->CR, PWR_CR_LPLVDS);
+}
+
+/**
+  * @brief  Disable Low Power Regulator low voltage Mode
+  * @rmtoll CR    LPLVDS       LL_PWR_DisableLowPowerRegulatorLowVoltageMode
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_DisableLowPowerRegulatorLowVoltageMode(void)
+{
+  CLEAR_BIT(PWR->CR, PWR_CR_LPLVDS);
+}
+
+/**
+  * @brief  Check if Low Power Regulator low voltage Mode is enabled
+  * @rmtoll CR    LPLVDS       LL_PWR_IsEnabledLowPowerRegulatorLowVoltageMode
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledLowPowerRegulatorLowVoltageMode(void)
+{
+  return (READ_BIT(PWR->CR, PWR_CR_LPLVDS) == (PWR_CR_LPLVDS));
+}
+#endif /* PWR_CR_LPLVDS */
+/**
+  * @brief  Set the main internal Regulator output voltage
+  * @rmtoll CR    VOS       LL_PWR_SetRegulVoltageScaling
+  * @param  VoltageScaling This parameter can be one of the following values:
+  *         @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1 (*)
+  *         @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2
+  *         @arg @ref LL_PWR_REGU_VOLTAGE_SCALE3
+  *         (*) LL_PWR_REGU_VOLTAGE_SCALE1 is not available for STM32F401xx devices
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_SetRegulVoltageScaling(uint32_t VoltageScaling)
+{
+  MODIFY_REG(PWR->CR, PWR_CR_VOS, VoltageScaling);
+}
+
+/**
+  * @brief  Get the main internal Regulator output voltage
+  * @rmtoll CR    VOS       LL_PWR_GetRegulVoltageScaling
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1 (*)
+  *         @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2
+  *         @arg @ref LL_PWR_REGU_VOLTAGE_SCALE3
+  *         (*) LL_PWR_REGU_VOLTAGE_SCALE1 is not available for STM32F401xx devices
+  */
+__STATIC_INLINE uint32_t LL_PWR_GetRegulVoltageScaling(void)
+{
+  return (uint32_t)(READ_BIT(PWR->CR, PWR_CR_VOS));
+}
+/**
+  * @brief  Enable the Flash Power Down in Stop Mode
+  * @rmtoll CR    FPDS       LL_PWR_EnableFlashPowerDown
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_EnableFlashPowerDown(void)
+{
+  SET_BIT(PWR->CR, PWR_CR_FPDS);
+}
+
+/**
+  * @brief  Disable the Flash Power Down in Stop Mode
+  * @rmtoll CR    FPDS       LL_PWR_DisableFlashPowerDown
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_DisableFlashPowerDown(void)
+{
+  CLEAR_BIT(PWR->CR, PWR_CR_FPDS);
+}
+
+/**
+  * @brief  Check if the Flash Power Down in Stop Mode is enabled
+  * @rmtoll CR    FPDS       LL_PWR_IsEnabledFlashPowerDown
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledFlashPowerDown(void)
+{
+  return (READ_BIT(PWR->CR, PWR_CR_FPDS) == (PWR_CR_FPDS));
+}
+
+/**
+  * @brief  Enable access to the backup domain
+  * @rmtoll CR    DBP       LL_PWR_EnableBkUpAccess
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_EnableBkUpAccess(void)
+{
+  SET_BIT(PWR->CR, PWR_CR_DBP);
+}
+
+/**
+  * @brief  Disable access to the backup domain
+  * @rmtoll CR    DBP       LL_PWR_DisableBkUpAccess
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_DisableBkUpAccess(void)
+{
+  CLEAR_BIT(PWR->CR, PWR_CR_DBP);
+}
+
+/**
+  * @brief  Check if the backup domain is enabled
+  * @rmtoll CR    DBP       LL_PWR_IsEnabledBkUpAccess
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpAccess(void)
+{
+  return (READ_BIT(PWR->CR, PWR_CR_DBP) == (PWR_CR_DBP));
+}
+/**
+  * @brief  Enable the backup Regulator
+  * @rmtoll CSR    BRE       LL_PWR_EnableBkUpRegulator
+  * @note The BRE bit of the PWR_CSR register is protected against parasitic write access.
+  * The LL_PWR_EnableBkUpAccess() must be called before using this API.
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_EnableBkUpRegulator(void)
+{
+  SET_BIT(PWR->CSR, PWR_CSR_BRE);
+}
+
+/**
+  * @brief  Disable the backup Regulator
+  * @rmtoll CSR    BRE       LL_PWR_DisableBkUpRegulator
+  * @note The BRE bit of the PWR_CSR register is protected against parasitic write access.
+  * The LL_PWR_EnableBkUpAccess() must be called before using this API.
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_DisableBkUpRegulator(void)
+{
+  CLEAR_BIT(PWR->CSR, PWR_CSR_BRE);
+}
+
+/**
+  * @brief  Check if the backup Regulator is enabled
+  * @rmtoll CSR    BRE       LL_PWR_IsEnabledBkUpRegulator
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpRegulator(void)
+{
+  return (READ_BIT(PWR->CSR, PWR_CSR_BRE) == (PWR_CSR_BRE));
+}
+
+/**
+  * @brief  Set voltage Regulator mode during deep sleep mode
+  * @rmtoll CR    LPDS         LL_PWR_SetRegulModeDS
+  * @param  RegulMode This parameter can be one of the following values:
+  *         @arg @ref LL_PWR_REGU_DSMODE_MAIN
+  *         @arg @ref LL_PWR_REGU_DSMODE_LOW_POWER
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_SetRegulModeDS(uint32_t RegulMode)
+{
+  MODIFY_REG(PWR->CR, PWR_CR_LPDS, RegulMode);
+}
+
+/**
+  * @brief  Get voltage Regulator mode during deep sleep mode
+  * @rmtoll CR    LPDS         LL_PWR_GetRegulModeDS
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_PWR_REGU_DSMODE_MAIN
+  *         @arg @ref LL_PWR_REGU_DSMODE_LOW_POWER
+  */
+__STATIC_INLINE uint32_t LL_PWR_GetRegulModeDS(void)
+{
+  return (uint32_t)(READ_BIT(PWR->CR, PWR_CR_LPDS));
+}
+
+/**
+  * @brief  Set Power Down mode when CPU enters deepsleep
+  * @rmtoll CR    PDDS         LL_PWR_SetPowerMode\n
+  * @rmtoll CR    MRUDS        LL_PWR_SetPowerMode\n
+  * @rmtoll CR    LPUDS        LL_PWR_SetPowerMode\n
+  * @rmtoll CR    FPDS         LL_PWR_SetPowerMode\n
+  * @rmtoll CR    MRLVDS       LL_PWR_SetPowerMode\n
+  * @rmtoll CR    LPlVDS       LL_PWR_SetPowerMode\n
+  * @rmtoll CR    FPDS         LL_PWR_SetPowerMode\n
+  * @rmtoll CR    LPDS         LL_PWR_SetPowerMode
+  * @param  PDMode This parameter can be one of the following values:
+  *         @arg @ref LL_PWR_MODE_STOP_MAINREGU
+  *         @arg @ref LL_PWR_MODE_STOP_LPREGU
+  *         @arg @ref LL_PWR_MODE_STOP_MAINREGU_UNDERDRIVE (*)
+  *         @arg @ref LL_PWR_MODE_STOP_LPREGU_UNDERDRIVE (*)
+  *         @arg @ref LL_PWR_MODE_STOP_MAINREGU_DEEPSLEEP (*)
+  *         @arg @ref LL_PWR_MODE_STOP_LPREGU_DEEPSLEEP (*)
+  *
+  *         (*) not available on all devices
+  *         @arg @ref LL_PWR_MODE_STANDBY
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_SetPowerMode(uint32_t PDMode)
+{
+#if defined(PWR_CR_MRUDS) && defined(PWR_CR_LPUDS) && defined(PWR_CR_FPDS)
+  MODIFY_REG(PWR->CR, (PWR_CR_PDDS | PWR_CR_LPDS | PWR_CR_FPDS | PWR_CR_LPUDS | PWR_CR_MRUDS), PDMode);
+#elif defined(PWR_CR_MRLVDS) && defined(PWR_CR_LPLVDS) && defined(PWR_CR_FPDS)
+  MODIFY_REG(PWR->CR, (PWR_CR_PDDS | PWR_CR_LPDS | PWR_CR_FPDS | PWR_CR_LPLVDS | PWR_CR_MRLVDS), PDMode);
+#else
+  MODIFY_REG(PWR->CR, (PWR_CR_PDDS| PWR_CR_LPDS), PDMode);
+#endif /* PWR_CR_MRUDS && PWR_CR_LPUDS && PWR_CR_FPDS */
+}
+
+/**
+  * @brief  Get Power Down mode when CPU enters deepsleep
+  * @rmtoll CR    PDDS         LL_PWR_GetPowerMode\n
+  * @rmtoll CR    MRUDS        LL_PWR_GetPowerMode\n
+  * @rmtoll CR    LPUDS        LL_PWR_GetPowerMode\n
+  * @rmtoll CR    FPDS         LL_PWR_GetPowerMode\n
+  * @rmtoll CR    MRLVDS       LL_PWR_GetPowerMode\n
+  * @rmtoll CR    LPLVDS       LL_PWR_GetPowerMode\n
+  * @rmtoll CR    FPDS         LL_PWR_GetPowerMode\n
+  * @rmtoll CR    LPDS         LL_PWR_GetPowerMode
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_PWR_MODE_STOP_MAINREGU
+  *         @arg @ref LL_PWR_MODE_STOP_LPREGU
+  *         @arg @ref LL_PWR_MODE_STOP_MAINREGU_UNDERDRIVE (*)
+  *         @arg @ref LL_PWR_MODE_STOP_LPREGU_UNDERDRIVE (*)
+  *         @arg @ref LL_PWR_MODE_STOP_MAINREGU_DEEPSLEEP (*)
+  *         @arg @ref LL_PWR_MODE_STOP_LPREGU_DEEPSLEEP (*)
+  *
+  *         (*) not available on all devices
+  *         @arg @ref LL_PWR_MODE_STANDBY
+  */
+__STATIC_INLINE uint32_t LL_PWR_GetPowerMode(void)
+{
+#if defined(PWR_CR_MRUDS) && defined(PWR_CR_LPUDS) && defined(PWR_CR_FPDS)
+  return (uint32_t)(READ_BIT(PWR->CR, (PWR_CR_PDDS | PWR_CR_LPDS | PWR_CR_FPDS | PWR_CR_LPUDS | PWR_CR_MRUDS)));
+#elif defined(PWR_CR_MRLVDS) && defined(PWR_CR_LPLVDS) && defined(PWR_CR_FPDS)
+  return (uint32_t)(READ_BIT(PWR->CR, (PWR_CR_PDDS | PWR_CR_LPDS | PWR_CR_FPDS | PWR_CR_LPLVDS | PWR_CR_MRLVDS)));
+#else
+  return (uint32_t)(READ_BIT(PWR->CR, (PWR_CR_PDDS| PWR_CR_LPDS)));
+#endif /* PWR_CR_MRUDS && PWR_CR_LPUDS && PWR_CR_FPDS */
+}
+
+/**
+  * @brief  Configure the voltage threshold detected by the Power Voltage Detector
+  * @rmtoll CR    PLS       LL_PWR_SetPVDLevel
+  * @param  PVDLevel This parameter can be one of the following values:
+  *         @arg @ref LL_PWR_PVDLEVEL_0
+  *         @arg @ref LL_PWR_PVDLEVEL_1
+  *         @arg @ref LL_PWR_PVDLEVEL_2
+  *         @arg @ref LL_PWR_PVDLEVEL_3
+  *         @arg @ref LL_PWR_PVDLEVEL_4
+  *         @arg @ref LL_PWR_PVDLEVEL_5
+  *         @arg @ref LL_PWR_PVDLEVEL_6
+  *         @arg @ref LL_PWR_PVDLEVEL_7
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_SetPVDLevel(uint32_t PVDLevel)
+{
+  MODIFY_REG(PWR->CR, PWR_CR_PLS, PVDLevel);
+}
+
+/**
+  * @brief  Get the voltage threshold detection
+  * @rmtoll CR    PLS       LL_PWR_GetPVDLevel
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_PWR_PVDLEVEL_0
+  *         @arg @ref LL_PWR_PVDLEVEL_1
+  *         @arg @ref LL_PWR_PVDLEVEL_2
+  *         @arg @ref LL_PWR_PVDLEVEL_3
+  *         @arg @ref LL_PWR_PVDLEVEL_4
+  *         @arg @ref LL_PWR_PVDLEVEL_5
+  *         @arg @ref LL_PWR_PVDLEVEL_6
+  *         @arg @ref LL_PWR_PVDLEVEL_7
+  */
+__STATIC_INLINE uint32_t LL_PWR_GetPVDLevel(void)
+{
+  return (uint32_t)(READ_BIT(PWR->CR, PWR_CR_PLS));
+}
+
+/**
+  * @brief  Enable Power Voltage Detector
+  * @rmtoll CR    PVDE       LL_PWR_EnablePVD
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_EnablePVD(void)
+{
+  SET_BIT(PWR->CR, PWR_CR_PVDE);
+}
+
+/**
+  * @brief  Disable Power Voltage Detector
+  * @rmtoll CR    PVDE       LL_PWR_DisablePVD
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_DisablePVD(void)
+{
+  CLEAR_BIT(PWR->CR, PWR_CR_PVDE);
+}
+
+/**
+  * @brief  Check if Power Voltage Detector is enabled
+  * @rmtoll CR    PVDE       LL_PWR_IsEnabledPVD
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledPVD(void)
+{
+  return (READ_BIT(PWR->CR, PWR_CR_PVDE) == (PWR_CR_PVDE));
+}
+
+/**
+  * @brief  Enable the WakeUp PINx functionality
+  * @rmtoll CSR   EWUP        LL_PWR_EnableWakeUpPin\n
+  * @rmtoll CSR   EWUP1       LL_PWR_EnableWakeUpPin\n
+  * @rmtoll CSR   EWUP2       LL_PWR_EnableWakeUpPin\n
+  * @rmtoll CSR   EWUP3       LL_PWR_EnableWakeUpPin
+  * @param  WakeUpPin This parameter can be one of the following values:
+  *         @arg @ref LL_PWR_WAKEUP_PIN1
+  *         @arg @ref LL_PWR_WAKEUP_PIN2 (*)
+  *         @arg @ref LL_PWR_WAKEUP_PIN3 (*)
+  *
+  *         (*) not available on all devices
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_EnableWakeUpPin(uint32_t WakeUpPin)
+{
+  SET_BIT(PWR->CSR, WakeUpPin);
+}
+
+/**
+  * @brief  Disable the WakeUp PINx functionality
+  * @rmtoll CSR   EWUP        LL_PWR_DisableWakeUpPin\n
+  * @rmtoll CSR   EWUP1       LL_PWR_DisableWakeUpPin\n
+  * @rmtoll CSR   EWUP2       LL_PWR_DisableWakeUpPin\n
+  * @rmtoll CSR   EWUP3       LL_PWR_DisableWakeUpPin
+  * @param  WakeUpPin This parameter can be one of the following values:
+  *         @arg @ref LL_PWR_WAKEUP_PIN1
+  *         @arg @ref LL_PWR_WAKEUP_PIN2 (*)
+  *         @arg @ref LL_PWR_WAKEUP_PIN3 (*)
+  *
+  *         (*) not available on all devices
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_DisableWakeUpPin(uint32_t WakeUpPin)
+{
+  CLEAR_BIT(PWR->CSR, WakeUpPin);
+}
+
+/**
+  * @brief  Check if the WakeUp PINx functionality is enabled
+  * @rmtoll CSR   EWUP        LL_PWR_IsEnabledWakeUpPin\n
+  * @rmtoll CSR   EWUP1       LL_PWR_IsEnabledWakeUpPin\n
+  * @rmtoll CSR   EWUP2       LL_PWR_IsEnabledWakeUpPin\n
+  * @rmtoll CSR   EWUP3       LL_PWR_IsEnabledWakeUpPin
+  * @param  WakeUpPin This parameter can be one of the following values:
+  *         @arg @ref LL_PWR_WAKEUP_PIN1
+  *         @arg @ref LL_PWR_WAKEUP_PIN2 (*)
+  *         @arg @ref LL_PWR_WAKEUP_PIN3 (*)
+  *
+  *         (*) not available on all devices
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledWakeUpPin(uint32_t WakeUpPin)
+{
+  return (READ_BIT(PWR->CSR, WakeUpPin) == (WakeUpPin));
+}
+
+
+/**
+  * @}
+  */
+
+/** @defgroup PWR_LL_EF_FLAG_Management FLAG_Management
+  * @{
+  */
+
+/**
+  * @brief  Get Wake-up Flag
+  * @rmtoll CSR   WUF       LL_PWR_IsActiveFlag_WU
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU(void)
+{
+  return (READ_BIT(PWR->CSR, PWR_CSR_WUF) == (PWR_CSR_WUF));
+}
+
+/**
+  * @brief  Get Standby Flag
+  * @rmtoll CSR   SBF       LL_PWR_IsActiveFlag_SB
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_SB(void)
+{
+  return (READ_BIT(PWR->CSR, PWR_CSR_SBF) == (PWR_CSR_SBF));
+}
+
+/**
+  * @brief  Get Backup Regulator ready Flag
+  * @rmtoll CSR   BRR       LL_PWR_IsActiveFlag_BRR
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_BRR(void)
+{
+  return (READ_BIT(PWR->CSR, PWR_CSR_BRR) == (PWR_CSR_BRR));
+}
+/**
+  * @brief  Indicate whether VDD voltage is below the selected PVD threshold
+  * @rmtoll CSR   PVDO       LL_PWR_IsActiveFlag_PVDO
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVDO(void)
+{
+  return (READ_BIT(PWR->CSR, PWR_CSR_PVDO) == (PWR_CSR_PVDO));
+}
+
+/**
+  * @brief  Indicate whether the Regulator is ready in the selected voltage range or if its output voltage is still changing to the required voltage level
+  * @rmtoll CSR   VOS       LL_PWR_IsActiveFlag_VOS
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VOS(void)
+{
+  return (READ_BIT(PWR->CSR, LL_PWR_CSR_VOS) == (LL_PWR_CSR_VOS));
+}
+#if defined(PWR_CR_ODEN)
+/**
+  * @brief  Indicate whether the Over-Drive mode is ready or not
+  * @rmtoll CSR   ODRDY       LL_PWR_IsActiveFlag_OD
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_OD(void)
+{
+  return (READ_BIT(PWR->CSR, PWR_CSR_ODRDY) == (PWR_CSR_ODRDY));
+}
+#endif /* PWR_CR_ODEN */
+
+#if defined(PWR_CR_ODSWEN)
+/**
+  * @brief  Indicate whether the Over-Drive mode switching is ready or not
+  * @rmtoll CSR   ODSWRDY       LL_PWR_IsActiveFlag_ODSW
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_ODSW(void)
+{
+  return (READ_BIT(PWR->CSR, PWR_CSR_ODSWRDY) == (PWR_CSR_ODSWRDY));
+}
+#endif /* PWR_CR_ODSWEN */
+
+#if defined(PWR_CR_UDEN)
+/**
+  * @brief  Indicate whether the Under-Drive mode is ready or not
+  * @rmtoll CSR   UDRDY       LL_PWR_IsActiveFlag_UD
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_UD(void)
+{
+  return (READ_BIT(PWR->CSR, PWR_CSR_UDRDY) == (PWR_CSR_UDRDY));
+}
+#endif /* PWR_CR_UDEN */
+/**
+  * @brief  Clear Standby Flag
+  * @rmtoll CR   CSBF       LL_PWR_ClearFlag_SB
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_ClearFlag_SB(void)
+{
+  SET_BIT(PWR->CR, PWR_CR_CSBF);
+}
+
+/**
+  * @brief  Clear Wake-up Flags
+  * @rmtoll CR   CWUF       LL_PWR_ClearFlag_WU
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_ClearFlag_WU(void)
+{
+  SET_BIT(PWR->CR, PWR_CR_CWUF);
+}
+#if defined(PWR_CSR_UDRDY)
+/**
+  * @brief  Clear Under-Drive ready Flag
+  * @rmtoll CSR          UDRDY         LL_PWR_ClearFlag_UD
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_ClearFlag_UD(void)
+{
+  WRITE_REG(PWR->CSR, PWR_CSR_UDRDY);
+}
+#endif /* PWR_CSR_UDRDY */
+
+/**
+  * @}
+  */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup PWR_LL_EF_Init De-initialization function
+  * @{
+  */
+ErrorStatus LL_PWR_DeInit(void);
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* defined(PWR) */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_LL_PWR_H */
diff --git a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_rcc.h b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_rcc.h
new file mode 100644
index 0000000..1f2a91d
--- /dev/null
+++ b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_rcc.h
@@ -0,0 +1,7096 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_ll_rcc.h
+  * @author  MCD Application Team
+  * @brief   Header file of RCC LL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file in
+  * the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_LL_RCC_H
+#define __STM32F4xx_LL_RCC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx.h"
+
+/** @addtogroup STM32F4xx_LL_Driver
+  * @{
+  */
+
+#if defined(RCC)
+
+/** @defgroup RCC_LL RCC
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup RCC_LL_Private_Variables RCC Private Variables
+  * @{
+  */
+
+#if defined(RCC_DCKCFGR_PLLSAIDIVR)
+static const uint8_t aRCC_PLLSAIDIVRPrescTable[4] = {2, 4, 8, 16};
+#endif /* RCC_DCKCFGR_PLLSAIDIVR */
+
+/**
+  * @}
+  */
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup RCC_LL_Private_Macros RCC Private Macros
+  * @{
+  */
+/**
+  * @}
+  */
+#endif /*USE_FULL_LL_DRIVER*/
+/* Exported types ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup RCC_LL_Exported_Types RCC Exported Types
+  * @{
+  */
+
+/** @defgroup LL_ES_CLOCK_FREQ Clocks Frequency Structure
+  * @{
+  */
+
+/**
+  * @brief  RCC Clocks Frequency Structure
+  */
+typedef struct
+{
+  uint32_t SYSCLK_Frequency;        /*!< SYSCLK clock frequency */
+  uint32_t HCLK_Frequency;          /*!< HCLK clock frequency */
+  uint32_t PCLK1_Frequency;         /*!< PCLK1 clock frequency */
+  uint32_t PCLK2_Frequency;         /*!< PCLK2 clock frequency */
+} LL_RCC_ClocksTypeDef;
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup RCC_LL_Exported_Constants RCC Exported Constants
+  * @{
+  */
+
+/** @defgroup RCC_LL_EC_OSC_VALUES Oscillator Values adaptation
+  * @brief    Defines used to adapt values of different oscillators
+  * @note     These values could be modified in the user environment according to 
+  *           HW set-up.
+  * @{
+  */
+#if !defined  (HSE_VALUE)
+#define HSE_VALUE    25000000U  /*!< Value of the HSE oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (HSI_VALUE)
+#define HSI_VALUE    16000000U  /*!< Value of the HSI oscillator in Hz */
+#endif /* HSI_VALUE */
+
+#if !defined  (LSE_VALUE)
+#define LSE_VALUE    32768U     /*!< Value of the LSE oscillator in Hz */
+#endif /* LSE_VALUE */
+
+#if !defined  (LSI_VALUE)
+#define LSI_VALUE    32000U     /*!< Value of the LSI oscillator in Hz */
+#endif /* LSI_VALUE */
+
+#if !defined  (EXTERNAL_CLOCK_VALUE)
+#define EXTERNAL_CLOCK_VALUE    12288000U /*!< Value of the I2S_CKIN external oscillator in Hz */
+#endif /* EXTERNAL_CLOCK_VALUE */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_CLEAR_FLAG Clear Flags Defines
+  * @brief    Flags defines which can be used with LL_RCC_WriteReg function
+  * @{
+  */
+#define LL_RCC_CIR_LSIRDYC                RCC_CIR_LSIRDYC     /*!< LSI Ready Interrupt Clear */
+#define LL_RCC_CIR_LSERDYC                RCC_CIR_LSERDYC     /*!< LSE Ready Interrupt Clear */
+#define LL_RCC_CIR_HSIRDYC                RCC_CIR_HSIRDYC     /*!< HSI Ready Interrupt Clear */
+#define LL_RCC_CIR_HSERDYC                RCC_CIR_HSERDYC     /*!< HSE Ready Interrupt Clear */
+#define LL_RCC_CIR_PLLRDYC                RCC_CIR_PLLRDYC     /*!< PLL Ready Interrupt Clear */
+#if defined(RCC_PLLI2S_SUPPORT)
+#define LL_RCC_CIR_PLLI2SRDYC             RCC_CIR_PLLI2SRDYC  /*!< PLLI2S Ready Interrupt Clear */
+#endif /* RCC_PLLI2S_SUPPORT */
+#if defined(RCC_PLLSAI_SUPPORT)
+#define LL_RCC_CIR_PLLSAIRDYC             RCC_CIR_PLLSAIRDYC  /*!< PLLSAI Ready Interrupt Clear */
+#endif /* RCC_PLLSAI_SUPPORT */
+#define LL_RCC_CIR_CSSC                   RCC_CIR_CSSC        /*!< Clock Security System Interrupt Clear */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_GET_FLAG Get Flags Defines
+  * @brief    Flags defines which can be used with LL_RCC_ReadReg function
+  * @{
+  */
+#define LL_RCC_CIR_LSIRDYF                RCC_CIR_LSIRDYF     /*!< LSI Ready Interrupt flag */
+#define LL_RCC_CIR_LSERDYF                RCC_CIR_LSERDYF     /*!< LSE Ready Interrupt flag */
+#define LL_RCC_CIR_HSIRDYF                RCC_CIR_HSIRDYF     /*!< HSI Ready Interrupt flag */
+#define LL_RCC_CIR_HSERDYF                RCC_CIR_HSERDYF     /*!< HSE Ready Interrupt flag */
+#define LL_RCC_CIR_PLLRDYF                RCC_CIR_PLLRDYF     /*!< PLL Ready Interrupt flag */
+#if defined(RCC_PLLI2S_SUPPORT)
+#define LL_RCC_CIR_PLLI2SRDYF             RCC_CIR_PLLI2SRDYF  /*!< PLLI2S Ready Interrupt flag */
+#endif /* RCC_PLLI2S_SUPPORT */
+#if defined(RCC_PLLSAI_SUPPORT)
+#define LL_RCC_CIR_PLLSAIRDYF             RCC_CIR_PLLSAIRDYF  /*!< PLLSAI Ready Interrupt flag */
+#endif /* RCC_PLLSAI_SUPPORT */
+#define LL_RCC_CIR_CSSF                   RCC_CIR_CSSF        /*!< Clock Security System Interrupt flag */
+#define LL_RCC_CSR_LPWRRSTF                RCC_CSR_LPWRRSTF   /*!< Low-Power reset flag */
+#define LL_RCC_CSR_PINRSTF                 RCC_CSR_PINRSTF    /*!< PIN reset flag */
+#define LL_RCC_CSR_PORRSTF                 RCC_CSR_PORRSTF    /*!< POR/PDR reset flag */
+#define LL_RCC_CSR_SFTRSTF                 RCC_CSR_SFTRSTF    /*!< Software Reset flag */
+#define LL_RCC_CSR_IWDGRSTF                RCC_CSR_IWDGRSTF   /*!< Independent Watchdog reset flag */
+#define LL_RCC_CSR_WWDGRSTF                RCC_CSR_WWDGRSTF   /*!< Window watchdog reset flag */
+#if defined(RCC_CSR_BORRSTF)
+#define LL_RCC_CSR_BORRSTF                 RCC_CSR_BORRSTF    /*!< BOR reset flag */
+#endif /* RCC_CSR_BORRSTF */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_IT IT Defines
+  * @brief    IT defines which can be used with LL_RCC_ReadReg and  LL_RCC_WriteReg functions
+  * @{
+  */
+#define LL_RCC_CIR_LSIRDYIE               RCC_CIR_LSIRDYIE      /*!< LSI Ready Interrupt Enable */
+#define LL_RCC_CIR_LSERDYIE               RCC_CIR_LSERDYIE      /*!< LSE Ready Interrupt Enable */
+#define LL_RCC_CIR_HSIRDYIE               RCC_CIR_HSIRDYIE      /*!< HSI Ready Interrupt Enable */
+#define LL_RCC_CIR_HSERDYIE               RCC_CIR_HSERDYIE      /*!< HSE Ready Interrupt Enable */
+#define LL_RCC_CIR_PLLRDYIE               RCC_CIR_PLLRDYIE      /*!< PLL Ready Interrupt Enable */
+#if defined(RCC_PLLI2S_SUPPORT)
+#define LL_RCC_CIR_PLLI2SRDYIE            RCC_CIR_PLLI2SRDYIE   /*!< PLLI2S Ready Interrupt Enable */
+#endif /* RCC_PLLI2S_SUPPORT */
+#if defined(RCC_PLLSAI_SUPPORT)
+#define LL_RCC_CIR_PLLSAIRDYIE            RCC_CIR_PLLSAIRDYIE   /*!< PLLSAI Ready Interrupt Enable */
+#endif /* RCC_PLLSAI_SUPPORT */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_SYS_CLKSOURCE  System clock switch
+  * @{
+  */
+#define LL_RCC_SYS_CLKSOURCE_HSI           RCC_CFGR_SW_HSI    /*!< HSI selection as system clock */
+#define LL_RCC_SYS_CLKSOURCE_HSE           RCC_CFGR_SW_HSE    /*!< HSE selection as system clock */
+#define LL_RCC_SYS_CLKSOURCE_PLL           RCC_CFGR_SW_PLL    /*!< PLL selection as system clock */
+#if defined(RCC_CFGR_SW_PLLR)
+#define LL_RCC_SYS_CLKSOURCE_PLLR          RCC_CFGR_SW_PLLR   /*!< PLLR selection as system clock */
+#endif /* RCC_CFGR_SW_PLLR */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_SYS_CLKSOURCE_STATUS  System clock switch status
+  * @{
+  */
+#define LL_RCC_SYS_CLKSOURCE_STATUS_HSI    RCC_CFGR_SWS_HSI   /*!< HSI used as system clock */
+#define LL_RCC_SYS_CLKSOURCE_STATUS_HSE    RCC_CFGR_SWS_HSE   /*!< HSE used as system clock */
+#define LL_RCC_SYS_CLKSOURCE_STATUS_PLL    RCC_CFGR_SWS_PLL   /*!< PLL used as system clock */
+#if defined(RCC_PLLR_SYSCLK_SUPPORT)
+#define LL_RCC_SYS_CLKSOURCE_STATUS_PLLR   RCC_CFGR_SWS_PLLR  /*!< PLLR used as system clock */
+#endif /* RCC_PLLR_SYSCLK_SUPPORT */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_SYSCLK_DIV  AHB prescaler
+  * @{
+  */
+#define LL_RCC_SYSCLK_DIV_1                RCC_CFGR_HPRE_DIV1   /*!< SYSCLK not divided */
+#define LL_RCC_SYSCLK_DIV_2                RCC_CFGR_HPRE_DIV2   /*!< SYSCLK divided by 2 */
+#define LL_RCC_SYSCLK_DIV_4                RCC_CFGR_HPRE_DIV4   /*!< SYSCLK divided by 4 */
+#define LL_RCC_SYSCLK_DIV_8                RCC_CFGR_HPRE_DIV8   /*!< SYSCLK divided by 8 */
+#define LL_RCC_SYSCLK_DIV_16               RCC_CFGR_HPRE_DIV16  /*!< SYSCLK divided by 16 */
+#define LL_RCC_SYSCLK_DIV_64               RCC_CFGR_HPRE_DIV64  /*!< SYSCLK divided by 64 */
+#define LL_RCC_SYSCLK_DIV_128              RCC_CFGR_HPRE_DIV128 /*!< SYSCLK divided by 128 */
+#define LL_RCC_SYSCLK_DIV_256              RCC_CFGR_HPRE_DIV256 /*!< SYSCLK divided by 256 */
+#define LL_RCC_SYSCLK_DIV_512              RCC_CFGR_HPRE_DIV512 /*!< SYSCLK divided by 512 */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_APB1_DIV  APB low-speed prescaler (APB1)
+  * @{
+  */
+#define LL_RCC_APB1_DIV_1                  RCC_CFGR_PPRE1_DIV1  /*!< HCLK not divided */
+#define LL_RCC_APB1_DIV_2                  RCC_CFGR_PPRE1_DIV2  /*!< HCLK divided by 2 */
+#define LL_RCC_APB1_DIV_4                  RCC_CFGR_PPRE1_DIV4  /*!< HCLK divided by 4 */
+#define LL_RCC_APB1_DIV_8                  RCC_CFGR_PPRE1_DIV8  /*!< HCLK divided by 8 */
+#define LL_RCC_APB1_DIV_16                 RCC_CFGR_PPRE1_DIV16 /*!< HCLK divided by 16 */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_APB2_DIV  APB high-speed prescaler (APB2)
+  * @{
+  */
+#define LL_RCC_APB2_DIV_1                  RCC_CFGR_PPRE2_DIV1  /*!< HCLK not divided */
+#define LL_RCC_APB2_DIV_2                  RCC_CFGR_PPRE2_DIV2  /*!< HCLK divided by 2 */
+#define LL_RCC_APB2_DIV_4                  RCC_CFGR_PPRE2_DIV4  /*!< HCLK divided by 4 */
+#define LL_RCC_APB2_DIV_8                  RCC_CFGR_PPRE2_DIV8  /*!< HCLK divided by 8 */
+#define LL_RCC_APB2_DIV_16                 RCC_CFGR_PPRE2_DIV16 /*!< HCLK divided by 16 */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_MCOxSOURCE  MCO source selection
+  * @{
+  */
+#define LL_RCC_MCO1SOURCE_HSI              (uint32_t)(RCC_CFGR_MCO1|0x00000000U)                    /*!< HSI selection as MCO1 source */
+#define LL_RCC_MCO1SOURCE_LSE              (uint32_t)(RCC_CFGR_MCO1|(RCC_CFGR_MCO1_0 >> 16U))       /*!< LSE selection as MCO1 source */
+#define LL_RCC_MCO1SOURCE_HSE              (uint32_t)(RCC_CFGR_MCO1|(RCC_CFGR_MCO1_1 >> 16U))       /*!< HSE selection as MCO1 source */
+#define LL_RCC_MCO1SOURCE_PLLCLK           (uint32_t)(RCC_CFGR_MCO1|((RCC_CFGR_MCO1_1|RCC_CFGR_MCO1_0) >> 16U))       /*!< PLLCLK selection as MCO1 source */
+#if defined(RCC_CFGR_MCO2)
+#define LL_RCC_MCO2SOURCE_SYSCLK           (uint32_t)(RCC_CFGR_MCO2|0x00000000U)                    /*!< SYSCLK selection as MCO2 source */
+#define LL_RCC_MCO2SOURCE_PLLI2S           (uint32_t)(RCC_CFGR_MCO2|(RCC_CFGR_MCO2_0 >> 16U))       /*!< PLLI2S selection as MCO2 source */
+#define LL_RCC_MCO2SOURCE_HSE              (uint32_t)(RCC_CFGR_MCO2|(RCC_CFGR_MCO2_1 >> 16U))       /*!< HSE selection as MCO2 source */
+#define LL_RCC_MCO2SOURCE_PLLCLK           (uint32_t)(RCC_CFGR_MCO2|((RCC_CFGR_MCO2_1|RCC_CFGR_MCO2_0) >> 16U))       /*!< PLLCLK selection as MCO2 source */
+#endif /* RCC_CFGR_MCO2 */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_MCOx_DIV  MCO prescaler
+  * @{
+  */
+#define LL_RCC_MCO1_DIV_1                  (uint32_t)(RCC_CFGR_MCO1PRE|0x00000000U)                       /*!< MCO1 not divided */
+#define LL_RCC_MCO1_DIV_2                  (uint32_t)(RCC_CFGR_MCO1PRE|(RCC_CFGR_MCO1PRE_2 >> 16U))       /*!< MCO1 divided by 2 */
+#define LL_RCC_MCO1_DIV_3                  (uint32_t)(RCC_CFGR_MCO1PRE|((RCC_CFGR_MCO1PRE_2|RCC_CFGR_MCO1PRE_0) >> 16U))       /*!< MCO1 divided by 3 */
+#define LL_RCC_MCO1_DIV_4                  (uint32_t)(RCC_CFGR_MCO1PRE|((RCC_CFGR_MCO1PRE_2|RCC_CFGR_MCO1PRE_1) >> 16U))       /*!< MCO1 divided by 4 */
+#define LL_RCC_MCO1_DIV_5                  (uint32_t)(RCC_CFGR_MCO1PRE|(RCC_CFGR_MCO1PRE >> 16U))         /*!< MCO1 divided by 5 */
+#if defined(RCC_CFGR_MCO2PRE)
+#define LL_RCC_MCO2_DIV_1                  (uint32_t)(RCC_CFGR_MCO2PRE|0x00000000U)                       /*!< MCO2 not divided */
+#define LL_RCC_MCO2_DIV_2                  (uint32_t)(RCC_CFGR_MCO2PRE|(RCC_CFGR_MCO2PRE_2 >> 16U))       /*!< MCO2 divided by 2 */
+#define LL_RCC_MCO2_DIV_3                  (uint32_t)(RCC_CFGR_MCO2PRE|((RCC_CFGR_MCO2PRE_2|RCC_CFGR_MCO2PRE_0) >> 16U))       /*!< MCO2 divided by 3 */
+#define LL_RCC_MCO2_DIV_4                  (uint32_t)(RCC_CFGR_MCO2PRE|((RCC_CFGR_MCO2PRE_2|RCC_CFGR_MCO2PRE_1) >> 16U))       /*!< MCO2 divided by 4 */
+#define LL_RCC_MCO2_DIV_5                  (uint32_t)(RCC_CFGR_MCO2PRE|(RCC_CFGR_MCO2PRE >> 16U))         /*!< MCO2 divided by 5 */
+#endif /* RCC_CFGR_MCO2PRE */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_RTC_HSEDIV  HSE prescaler for RTC clock
+  * @{
+  */
+#define LL_RCC_RTC_NOCLOCK                  0x00000000U             /*!< HSE not divided */
+#define LL_RCC_RTC_HSE_DIV_2                RCC_CFGR_RTCPRE_1       /*!< HSE clock divided by 2 */
+#define LL_RCC_RTC_HSE_DIV_3                (RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)       /*!< HSE clock divided by 3 */
+#define LL_RCC_RTC_HSE_DIV_4                RCC_CFGR_RTCPRE_2       /*!< HSE clock divided by 4 */
+#define LL_RCC_RTC_HSE_DIV_5                (RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0)       /*!< HSE clock divided by 5 */
+#define LL_RCC_RTC_HSE_DIV_6                (RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1)       /*!< HSE clock divided by 6 */
+#define LL_RCC_RTC_HSE_DIV_7                (RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)       /*!< HSE clock divided by 7 */
+#define LL_RCC_RTC_HSE_DIV_8                RCC_CFGR_RTCPRE_3       /*!< HSE clock divided by 8 */
+#define LL_RCC_RTC_HSE_DIV_9                (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_0)       /*!< HSE clock divided by 9 */
+#define LL_RCC_RTC_HSE_DIV_10               (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1)       /*!< HSE clock divided by 10 */
+#define LL_RCC_RTC_HSE_DIV_11               (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)       /*!< HSE clock divided by 11 */
+#define LL_RCC_RTC_HSE_DIV_12               (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2)       /*!< HSE clock divided by 12 */
+#define LL_RCC_RTC_HSE_DIV_13               (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0)       /*!< HSE clock divided by 13 */
+#define LL_RCC_RTC_HSE_DIV_14               (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1)       /*!< HSE clock divided by 14 */
+#define LL_RCC_RTC_HSE_DIV_15               (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)       /*!< HSE clock divided by 15 */
+#define LL_RCC_RTC_HSE_DIV_16               RCC_CFGR_RTCPRE_4       /*!< HSE clock divided by 16 */
+#define LL_RCC_RTC_HSE_DIV_17               (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_0)       /*!< HSE clock divided by 17 */
+#define LL_RCC_RTC_HSE_DIV_18               (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_1)       /*!< HSE clock divided by 18 */
+#define LL_RCC_RTC_HSE_DIV_19               (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)       /*!< HSE clock divided by 19 */
+#define LL_RCC_RTC_HSE_DIV_20               (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2)       /*!< HSE clock divided by 20 */
+#define LL_RCC_RTC_HSE_DIV_21               (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0)       /*!< HSE clock divided by 21 */
+#define LL_RCC_RTC_HSE_DIV_22               (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1)       /*!< HSE clock divided by 22 */
+#define LL_RCC_RTC_HSE_DIV_23               (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)       /*!< HSE clock divided by 23 */
+#define LL_RCC_RTC_HSE_DIV_24               (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3)       /*!< HSE clock divided by 24 */
+#define LL_RCC_RTC_HSE_DIV_25               (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_0)       /*!< HSE clock divided by 25 */
+#define LL_RCC_RTC_HSE_DIV_26               (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1)       /*!< HSE clock divided by 26 */
+#define LL_RCC_RTC_HSE_DIV_27               (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)       /*!< HSE clock divided by 27 */
+#define LL_RCC_RTC_HSE_DIV_28               (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2)       /*!< HSE clock divided by 28 */
+#define LL_RCC_RTC_HSE_DIV_29               (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0)       /*!< HSE clock divided by 29 */
+#define LL_RCC_RTC_HSE_DIV_30               (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1)       /*!< HSE clock divided by 30 */
+#define LL_RCC_RTC_HSE_DIV_31               (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)       /*!< HSE clock divided by 31 */
+/**
+  * @}
+  */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup RCC_LL_EC_PERIPH_FREQUENCY Peripheral clock frequency
+  * @{
+  */
+#define LL_RCC_PERIPH_FREQUENCY_NO         0x00000000U                 /*!< No clock enabled for the peripheral            */
+#define LL_RCC_PERIPH_FREQUENCY_NA         0xFFFFFFFFU                 /*!< Frequency cannot be provided as external clock */
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+#if defined(FMPI2C1)
+/** @defgroup RCC_LL_EC_FMPI2C1_CLKSOURCE  Peripheral FMPI2C clock source selection
+  * @{
+  */
+#define LL_RCC_FMPI2C1_CLKSOURCE_PCLK1        0x00000000U               /*!< PCLK1 clock used as FMPI2C1 clock source */
+#define LL_RCC_FMPI2C1_CLKSOURCE_SYSCLK       RCC_DCKCFGR2_FMPI2C1SEL_0 /*!< SYSCLK clock used as FMPI2C1 clock source */
+#define LL_RCC_FMPI2C1_CLKSOURCE_HSI          RCC_DCKCFGR2_FMPI2C1SEL_1 /*!< HSI clock used as FMPI2C1 clock source */
+/**
+  * @}
+  */
+#endif /* FMPI2C1 */
+
+#if defined(LPTIM1)
+/** @defgroup RCC_LL_EC_LPTIM1_CLKSOURCE  Peripheral LPTIM clock source selection
+  * @{
+  */
+#define LL_RCC_LPTIM1_CLKSOURCE_PCLK1       0x00000000U                 /*!< PCLK1 clock used as LPTIM1 clock */
+#define LL_RCC_LPTIM1_CLKSOURCE_HSI         RCC_DCKCFGR2_LPTIM1SEL_0    /*!< LSI oscillator clock used as LPTIM1 clock */
+#define LL_RCC_LPTIM1_CLKSOURCE_LSI         RCC_DCKCFGR2_LPTIM1SEL_1    /*!< HSI oscillator clock used as LPTIM1 clock */
+#define LL_RCC_LPTIM1_CLKSOURCE_LSE         (uint32_t)(RCC_DCKCFGR2_LPTIM1SEL_1 | RCC_DCKCFGR2_LPTIM1SEL_0)      /*!< LSE oscillator clock used as LPTIM1 clock */
+/**
+  * @}
+  */
+#endif /* LPTIM1 */
+
+#if defined(SAI1)
+/** @defgroup RCC_LL_EC_SAIx_CLKSOURCE  Peripheral SAI clock source selection
+  * @{
+  */
+#if defined(RCC_DCKCFGR_SAI1SRC)
+#define LL_RCC_SAI1_CLKSOURCE_PLLSAI       (uint32_t)(RCC_DCKCFGR_SAI1SRC | 0x00000000U)                     /*!< PLLSAI clock used as SAI1 clock source */
+#define LL_RCC_SAI1_CLKSOURCE_PLLI2S       (uint32_t)(RCC_DCKCFGR_SAI1SRC | (RCC_DCKCFGR_SAI1SRC_0 >> 16))   /*!< PLLI2S clock used as SAI1 clock source */
+#define LL_RCC_SAI1_CLKSOURCE_PLL          (uint32_t)(RCC_DCKCFGR_SAI1SRC | (RCC_DCKCFGR_SAI1SRC_1 >> 16))   /*!< PLL clock used as SAI1 clock source */
+#define LL_RCC_SAI1_CLKSOURCE_PIN          (uint32_t)(RCC_DCKCFGR_SAI1SRC | (RCC_DCKCFGR_SAI1SRC >> 16))     /*!< External pin clock used as SAI1 clock source */
+#endif /* RCC_DCKCFGR_SAI1SRC */
+#if defined(RCC_DCKCFGR_SAI2SRC)
+#define LL_RCC_SAI2_CLKSOURCE_PLLSAI       (uint32_t)(RCC_DCKCFGR_SAI2SRC | 0x00000000U)                     /*!< PLLSAI clock used as SAI2 clock source */
+#define LL_RCC_SAI2_CLKSOURCE_PLLI2S       (uint32_t)(RCC_DCKCFGR_SAI2SRC | (RCC_DCKCFGR_SAI2SRC_0 >> 16))   /*!< PLLI2S clock used as SAI2 clock source */
+#define LL_RCC_SAI2_CLKSOURCE_PLL          (uint32_t)(RCC_DCKCFGR_SAI2SRC | (RCC_DCKCFGR_SAI2SRC_1 >> 16))   /*!< PLL clock used as SAI2 clock source */
+#define LL_RCC_SAI2_CLKSOURCE_PLLSRC       (uint32_t)(RCC_DCKCFGR_SAI2SRC | (RCC_DCKCFGR_SAI2SRC >> 16))     /*!< PLL Main clock used as SAI2 clock source */
+#endif /* RCC_DCKCFGR_SAI2SRC */
+#if defined(RCC_DCKCFGR_SAI1ASRC)
+#if defined(RCC_SAI1A_PLLSOURCE_SUPPORT)
+#define LL_RCC_SAI1_A_CLKSOURCE_PLLI2S     (uint32_t)(RCC_DCKCFGR_SAI1ASRC | 0x00000000U)                    /*!< PLLI2S clock used as SAI1 block A clock source */
+#define LL_RCC_SAI1_A_CLKSOURCE_PIN        (uint32_t)(RCC_DCKCFGR_SAI1ASRC | (RCC_DCKCFGR_SAI1ASRC_0 >> 16)) /*!< External pin used as SAI1 block A clock source */
+#define LL_RCC_SAI1_A_CLKSOURCE_PLL        (uint32_t)(RCC_DCKCFGR_SAI1ASRC | (RCC_DCKCFGR_SAI1ASRC_1 >> 16)) /*!< PLL clock used as SAI1 block A clock source */
+#define LL_RCC_SAI1_A_CLKSOURCE_PLLSRC     (uint32_t)(RCC_DCKCFGR_SAI1ASRC | (RCC_DCKCFGR_SAI1ASRC >> 16))   /*!< PLL Main clock used as SAI1 block A clock source */
+#else
+#define LL_RCC_SAI1_A_CLKSOURCE_PLLSAI     (uint32_t)(RCC_DCKCFGR_SAI1ASRC | 0x00000000U)                    /*!< PLLSAI clock used as SAI1 block A clock source */
+#define LL_RCC_SAI1_A_CLKSOURCE_PLLI2S     (uint32_t)(RCC_DCKCFGR_SAI1ASRC | (RCC_DCKCFGR_SAI1ASRC_0 >> 16)) /*!< PLLI2S clock used as SAI1 block A clock source */
+#define LL_RCC_SAI1_A_CLKSOURCE_PIN        (uint32_t)(RCC_DCKCFGR_SAI1ASRC | (RCC_DCKCFGR_SAI1ASRC_1 >> 16)) /*!< External pin clock used as SAI1 block A clock source */
+#endif /* RCC_SAI1A_PLLSOURCE_SUPPORT */
+#endif /* RCC_DCKCFGR_SAI1ASRC */
+#if defined(RCC_DCKCFGR_SAI1BSRC)
+#if defined(RCC_SAI1B_PLLSOURCE_SUPPORT)
+#define LL_RCC_SAI1_B_CLKSOURCE_PLLI2S     (uint32_t)(RCC_DCKCFGR_SAI1BSRC | 0x00000000U)                    /*!< PLLI2S clock used as SAI1 block B clock source */
+#define LL_RCC_SAI1_B_CLKSOURCE_PIN        (uint32_t)(RCC_DCKCFGR_SAI1BSRC | (RCC_DCKCFGR_SAI1BSRC_0 >> 16)) /*!< External pin used as SAI1 block B clock source */
+#define LL_RCC_SAI1_B_CLKSOURCE_PLL        (uint32_t)(RCC_DCKCFGR_SAI1BSRC | (RCC_DCKCFGR_SAI1BSRC_1 >> 16)) /*!< PLL clock used as SAI1 block B clock source */
+#define LL_RCC_SAI1_B_CLKSOURCE_PLLSRC     (uint32_t)(RCC_DCKCFGR_SAI1BSRC | (RCC_DCKCFGR_SAI1BSRC >> 16))   /*!< PLL Main clock used as SAI1 block B clock source */
+#else
+#define LL_RCC_SAI1_B_CLKSOURCE_PLLSAI     (uint32_t)(RCC_DCKCFGR_SAI1BSRC | 0x00000000U)                    /*!< PLLSAI clock used as SAI1 block B clock source */
+#define LL_RCC_SAI1_B_CLKSOURCE_PLLI2S     (uint32_t)(RCC_DCKCFGR_SAI1BSRC | (RCC_DCKCFGR_SAI1BSRC_0 >> 16)) /*!< PLLI2S clock used as SAI1 block B clock source */
+#define LL_RCC_SAI1_B_CLKSOURCE_PIN        (uint32_t)(RCC_DCKCFGR_SAI1BSRC | (RCC_DCKCFGR_SAI1BSRC_1 >> 16)) /*!< External pin clock used as SAI1 block B clock source */
+#endif /* RCC_SAI1B_PLLSOURCE_SUPPORT */
+#endif /* RCC_DCKCFGR_SAI1BSRC */
+/**
+  * @}
+  */
+#endif /* SAI1 */
+
+#if defined(RCC_DCKCFGR_SDIOSEL) || defined(RCC_DCKCFGR2_SDIOSEL)
+/** @defgroup RCC_LL_EC_SDIOx_CLKSOURCE  Peripheral SDIO clock source selection
+  * @{
+  */
+#define LL_RCC_SDIO_CLKSOURCE_PLL48CLK       0x00000000U                 /*!< PLL 48M domain clock used as SDIO clock */
+#if defined(RCC_DCKCFGR_SDIOSEL)
+#define LL_RCC_SDIO_CLKSOURCE_SYSCLK         RCC_DCKCFGR_SDIOSEL         /*!< System clock clock used as SDIO clock */
+#else
+#define LL_RCC_SDIO_CLKSOURCE_SYSCLK         RCC_DCKCFGR2_SDIOSEL        /*!< System clock clock used as SDIO clock */
+#endif /* RCC_DCKCFGR_SDIOSEL */
+/**
+  * @}
+  */
+#endif /* RCC_DCKCFGR_SDIOSEL || RCC_DCKCFGR2_SDIOSEL */
+
+#if defined(DSI)
+/** @defgroup RCC_LL_EC_DSI_CLKSOURCE  Peripheral DSI clock source selection
+  * @{
+  */
+#define LL_RCC_DSI_CLKSOURCE_PHY          0x00000000U                       /*!< DSI-PHY clock used as DSI byte lane clock source */
+#define LL_RCC_DSI_CLKSOURCE_PLL          RCC_DCKCFGR_DSISEL                /*!< PLL clock used as DSI byte lane clock source */
+/**
+  * @}
+  */
+#endif /* DSI */
+
+#if defined(CEC)
+/** @defgroup RCC_LL_EC_CEC_CLKSOURCE  Peripheral CEC clock source selection
+  * @{
+  */
+#define LL_RCC_CEC_CLKSOURCE_HSI_DIV488    0x00000000U                /*!< HSI oscillator clock divided by 488 used as CEC clock */
+#define LL_RCC_CEC_CLKSOURCE_LSE           RCC_DCKCFGR2_CECSEL        /*!< LSE oscillator clock used as CEC clock */
+/**
+  * @}
+  */
+#endif /* CEC */
+
+/** @defgroup RCC_LL_EC_I2S1_CLKSOURCE  Peripheral I2S clock source selection
+  * @{
+  */
+#if defined(RCC_CFGR_I2SSRC)
+#define LL_RCC_I2S1_CLKSOURCE_PLLI2S     0x00000000U                /*!< I2S oscillator clock used as I2S1 clock */
+#define LL_RCC_I2S1_CLKSOURCE_PIN        RCC_CFGR_I2SSRC            /*!< External pin clock used as I2S1 clock */
+#endif /* RCC_CFGR_I2SSRC */
+#if defined(RCC_DCKCFGR_I2SSRC)
+#define LL_RCC_I2S1_CLKSOURCE_PLL        (uint32_t)(RCC_DCKCFGR_I2SSRC | 0x00000000U)                    /*!< PLL clock used as I2S1 clock source */
+#define LL_RCC_I2S1_CLKSOURCE_PIN        (uint32_t)(RCC_DCKCFGR_I2SSRC | (RCC_DCKCFGR_I2SSRC_0 >> 16))   /*!< External pin used as I2S1 clock source */
+#define LL_RCC_I2S1_CLKSOURCE_PLLSRC     (uint32_t)(RCC_DCKCFGR_I2SSRC | (RCC_DCKCFGR_I2SSRC_1 >> 16))   /*!< PLL Main clock used as I2S1 clock source */
+#endif /* RCC_DCKCFGR_I2SSRC */
+#if defined(RCC_DCKCFGR_I2S1SRC)
+#define LL_RCC_I2S1_CLKSOURCE_PLLI2S     (uint32_t)(RCC_DCKCFGR_I2S1SRC | 0x00000000U)                   /*!< PLLI2S clock used as I2S1 clock source */
+#define LL_RCC_I2S1_CLKSOURCE_PIN        (uint32_t)(RCC_DCKCFGR_I2S1SRC | (RCC_DCKCFGR_I2S1SRC_0 >> 16)) /*!< External pin used as I2S1 clock source */
+#define LL_RCC_I2S1_CLKSOURCE_PLL        (uint32_t)(RCC_DCKCFGR_I2S1SRC | (RCC_DCKCFGR_I2S1SRC_1 >> 16)) /*!< PLL clock used as I2S1 clock source */
+#define LL_RCC_I2S1_CLKSOURCE_PLLSRC     (uint32_t)(RCC_DCKCFGR_I2S1SRC | (RCC_DCKCFGR_I2S1SRC >> 16))   /*!< PLL Main clock used as I2S1 clock source */
+#endif /* RCC_DCKCFGR_I2S1SRC */
+#if defined(RCC_DCKCFGR_I2S2SRC)
+#define LL_RCC_I2S2_CLKSOURCE_PLLI2S     (uint32_t)(RCC_DCKCFGR_I2S2SRC | 0x00000000U)                   /*!< PLLI2S clock used as I2S2 clock source */
+#define LL_RCC_I2S2_CLKSOURCE_PIN        (uint32_t)(RCC_DCKCFGR_I2S2SRC | (RCC_DCKCFGR_I2S2SRC_0 >> 16)) /*!< External pin used as I2S2 clock source */
+#define LL_RCC_I2S2_CLKSOURCE_PLL        (uint32_t)(RCC_DCKCFGR_I2S2SRC | (RCC_DCKCFGR_I2S2SRC_1 >> 16)) /*!< PLL clock used as I2S2 clock source */
+#define LL_RCC_I2S2_CLKSOURCE_PLLSRC     (uint32_t)(RCC_DCKCFGR_I2S2SRC | (RCC_DCKCFGR_I2S2SRC >> 16))   /*!< PLL Main clock used as I2S2 clock source */
+#endif /* RCC_DCKCFGR_I2S2SRC */
+/**
+  * @}
+  */
+
+#if defined(RCC_DCKCFGR_CK48MSEL) || defined(RCC_DCKCFGR2_CK48MSEL)
+/** @defgroup RCC_LL_EC_CK48M_CLKSOURCE  Peripheral 48Mhz domain clock source selection
+  * @{
+  */
+#if defined(RCC_DCKCFGR_CK48MSEL)
+#define LL_RCC_CK48M_CLKSOURCE_PLL         0x00000000U                /*!< PLL oscillator clock used as 48Mhz domain clock */
+#define LL_RCC_CK48M_CLKSOURCE_PLLSAI      RCC_DCKCFGR_CK48MSEL       /*!< PLLSAI oscillator clock used as 48Mhz domain clock */
+#endif /* RCC_DCKCFGR_CK48MSEL */
+#if defined(RCC_DCKCFGR2_CK48MSEL)
+#define LL_RCC_CK48M_CLKSOURCE_PLL         0x00000000U                /*!< PLL oscillator clock used as 48Mhz domain clock */
+#if defined(RCC_PLLSAI_SUPPORT)
+#define LL_RCC_CK48M_CLKSOURCE_PLLSAI      RCC_DCKCFGR2_CK48MSEL      /*!< PLLSAI oscillator clock used as 48Mhz domain clock */
+#endif /* RCC_PLLSAI_SUPPORT */
+#if defined(RCC_PLLI2SCFGR_PLLI2SQ) && !defined(RCC_DCKCFGR_PLLI2SDIVQ)
+#define LL_RCC_CK48M_CLKSOURCE_PLLI2S      RCC_DCKCFGR2_CK48MSEL      /*!< PLLI2S oscillator clock used as 48Mhz domain clock */
+#endif /* RCC_PLLI2SCFGR_PLLI2SQ && !RCC_DCKCFGR_PLLI2SDIVQ */
+#endif /* RCC_DCKCFGR2_CK48MSEL */
+/**
+  * @}
+  */
+
+#if defined(RNG)
+/** @defgroup RCC_LL_EC_RNG_CLKSOURCE  Peripheral RNG clock source selection
+  * @{
+  */
+#define LL_RCC_RNG_CLKSOURCE_PLL          LL_RCC_CK48M_CLKSOURCE_PLL        /*!< PLL clock used as RNG clock source */
+#if defined(RCC_PLLSAI_SUPPORT)
+#define LL_RCC_RNG_CLKSOURCE_PLLSAI       LL_RCC_CK48M_CLKSOURCE_PLLSAI     /*!< PLLSAI clock used as RNG clock source */
+#endif /* RCC_PLLSAI_SUPPORT */
+#if defined(RCC_PLLI2SCFGR_PLLI2SQ) && !defined(RCC_DCKCFGR_PLLI2SDIVQ)
+#define LL_RCC_RNG_CLKSOURCE_PLLI2S       LL_RCC_CK48M_CLKSOURCE_PLLI2S     /*!< PLLI2S clock used as RNG clock source */
+#endif /* RCC_PLLI2SCFGR_PLLI2SQ && !RCC_DCKCFGR_PLLI2SDIVQ */
+/**
+  * @}
+  */
+#endif /* RNG */
+
+#if defined(USB_OTG_FS) || defined(USB_OTG_HS)
+/** @defgroup RCC_LL_EC_USB_CLKSOURCE  Peripheral USB clock source selection
+  * @{
+  */
+#define LL_RCC_USB_CLKSOURCE_PLL          LL_RCC_CK48M_CLKSOURCE_PLL        /*!< PLL clock used as USB clock source */
+#if defined(RCC_PLLSAI_SUPPORT)
+#define LL_RCC_USB_CLKSOURCE_PLLSAI       LL_RCC_CK48M_CLKSOURCE_PLLSAI     /*!< PLLSAI clock used as USB clock source */
+#endif /* RCC_PLLSAI_SUPPORT */
+#if defined(RCC_PLLI2SCFGR_PLLI2SQ) && !defined(RCC_DCKCFGR_PLLI2SDIVQ)
+#define LL_RCC_USB_CLKSOURCE_PLLI2S       LL_RCC_CK48M_CLKSOURCE_PLLI2S     /*!< PLLI2S clock used as USB clock source */
+#endif /* RCC_PLLI2SCFGR_PLLI2SQ && !RCC_DCKCFGR_PLLI2SDIVQ */
+/**
+  * @}
+  */
+#endif /* USB_OTG_FS || USB_OTG_HS */
+
+#endif /* RCC_DCKCFGR_CK48MSEL || RCC_DCKCFGR2_CK48MSEL */
+
+#if defined(DFSDM1_Channel0) || defined(DFSDM2_Channel0)
+/** @defgroup RCC_LL_EC_DFSDM1_AUDIO_CLKSOURCE  Peripheral DFSDM Audio clock source selection
+  * @{
+  */
+#define LL_RCC_DFSDM1_AUDIO_CLKSOURCE_I2S1     (uint32_t)(RCC_DCKCFGR_CKDFSDM1ASEL | 0x00000000U)                      /*!< I2S1 clock used as DFSDM1 Audio clock source */
+#define LL_RCC_DFSDM1_AUDIO_CLKSOURCE_I2S2     (uint32_t)(RCC_DCKCFGR_CKDFSDM1ASEL | (RCC_DCKCFGR_CKDFSDM1ASEL << 16)) /*!< I2S2 clock used as DFSDM1 Audio clock source */
+#if defined(DFSDM2_Channel0)
+#define LL_RCC_DFSDM2_AUDIO_CLKSOURCE_I2S1     (uint32_t)(RCC_DCKCFGR_CKDFSDM2ASEL | 0x00000000U)                      /*!< I2S1 clock used as DFSDM2 Audio clock source */
+#define LL_RCC_DFSDM2_AUDIO_CLKSOURCE_I2S2     (uint32_t)(RCC_DCKCFGR_CKDFSDM2ASEL | (RCC_DCKCFGR_CKDFSDM2ASEL << 16)) /*!< I2S2 clock used as DFSDM2 Audio clock source */
+#endif /* DFSDM2_Channel0 */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_DFSDM1_CLKSOURCE  Peripheral DFSDM clock source selection
+  * @{
+  */
+#define LL_RCC_DFSDM1_CLKSOURCE_PCLK2          0x00000000U                /*!< PCLK2 clock used as DFSDM1 clock */
+#define LL_RCC_DFSDM1_CLKSOURCE_SYSCLK         RCC_DCKCFGR_CKDFSDM1SEL    /*!< System clock used as DFSDM1 clock */
+#if defined(DFSDM2_Channel0)
+#define LL_RCC_DFSDM2_CLKSOURCE_PCLK2          0x00000000U                /*!< PCLK2 clock used as DFSDM2 clock */
+#define LL_RCC_DFSDM2_CLKSOURCE_SYSCLK         RCC_DCKCFGR_CKDFSDM1SEL    /*!< System clock used as DFSDM2 clock */
+#endif /* DFSDM2_Channel0 */
+/**
+  * @}
+  */
+#endif /* DFSDM1_Channel0 || DFSDM2_Channel0 */
+
+#if defined(FMPI2C1)
+/** @defgroup RCC_LL_EC_FMPI2C1  Peripheral FMPI2C get clock source
+  * @{
+  */
+#define LL_RCC_FMPI2C1_CLKSOURCE              RCC_DCKCFGR2_FMPI2C1SEL  /*!< FMPI2C1 Clock source selection */
+/**
+  * @}
+  */
+#endif /* FMPI2C1 */
+
+#if defined(SPDIFRX)
+/** @defgroup RCC_LL_EC_SPDIFRX_CLKSOURCE  Peripheral SPDIFRX clock source selection
+  * @{
+  */
+#define LL_RCC_SPDIFRX1_CLKSOURCE_PLL          0x00000000U             /*!< PLL clock used as SPDIFRX clock source */
+#define LL_RCC_SPDIFRX1_CLKSOURCE_PLLI2S       RCC_DCKCFGR2_SPDIFRXSEL /*!< PLLI2S clock used as SPDIFRX clock source */
+/**
+  * @}
+  */
+#endif /* SPDIFRX */
+
+#if defined(LPTIM1)
+/** @defgroup RCC_LL_EC_LPTIM1  Peripheral LPTIM get clock source
+  * @{
+  */
+#define LL_RCC_LPTIM1_CLKSOURCE            RCC_DCKCFGR2_LPTIM1SEL /*!< LPTIM1 Clock source selection */
+/**
+  * @}
+  */
+#endif /* LPTIM1 */
+
+#if defined(SAI1)
+/** @defgroup RCC_LL_EC_SAIx  Peripheral SAI get clock source
+  * @{
+  */
+#if defined(RCC_DCKCFGR_SAI1ASRC)
+#define LL_RCC_SAI1_A_CLKSOURCE            RCC_DCKCFGR_SAI1ASRC /*!< SAI1 block A Clock source selection */
+#endif /* RCC_DCKCFGR_SAI1ASRC */
+#if defined(RCC_DCKCFGR_SAI1BSRC)
+#define LL_RCC_SAI1_B_CLKSOURCE            RCC_DCKCFGR_SAI1BSRC /*!< SAI1 block B Clock source selection */
+#endif /* RCC_DCKCFGR_SAI1BSRC */
+#if defined(RCC_DCKCFGR_SAI1SRC)
+#define LL_RCC_SAI1_CLKSOURCE              RCC_DCKCFGR_SAI1SRC  /*!< SAI1 Clock source selection */
+#endif /* RCC_DCKCFGR_SAI1SRC */
+#if defined(RCC_DCKCFGR_SAI2SRC)
+#define LL_RCC_SAI2_CLKSOURCE              RCC_DCKCFGR_SAI2SRC  /*!< SAI2 Clock source selection */
+#endif /* RCC_DCKCFGR_SAI2SRC */
+/**
+  * @}
+  */
+#endif /* SAI1 */
+
+#if defined(SDIO)
+/** @defgroup RCC_LL_EC_SDIOx  Peripheral SDIO get clock source
+  * @{
+  */
+#if defined(RCC_DCKCFGR_SDIOSEL)
+#define LL_RCC_SDIO_CLKSOURCE            RCC_DCKCFGR_SDIOSEL   /*!< SDIO Clock source selection */
+#elif defined(RCC_DCKCFGR2_SDIOSEL)
+#define LL_RCC_SDIO_CLKSOURCE            RCC_DCKCFGR2_SDIOSEL  /*!< SDIO Clock source selection */
+#else
+#define LL_RCC_SDIO_CLKSOURCE            RCC_PLLCFGR_PLLQ      /*!< SDIO Clock source selection */
+#endif
+/**
+  * @}
+  */
+#endif /* SDIO */
+
+#if defined(RCC_DCKCFGR_CK48MSEL) || defined(RCC_DCKCFGR2_CK48MSEL)
+/** @defgroup RCC_LL_EC_CK48M  Peripheral CK48M get clock source
+  * @{
+  */
+#if defined(RCC_DCKCFGR_CK48MSEL)
+#define LL_RCC_CK48M_CLKSOURCE             RCC_DCKCFGR_CK48MSEL  /*!< CK48M Domain clock source selection */
+#endif /* RCC_DCKCFGR_CK48MSEL */
+#if defined(RCC_DCKCFGR2_CK48MSEL)
+#define LL_RCC_CK48M_CLKSOURCE             RCC_DCKCFGR2_CK48MSEL /*!< CK48M Domain clock source selection */
+#endif /* RCC_DCKCFGR_CK48MSEL */
+/**
+  * @}
+  */
+#endif /* RCC_DCKCFGR_CK48MSEL || RCC_DCKCFGR2_CK48MSEL */
+
+#if defined(RNG)
+/** @defgroup RCC_LL_EC_RNG  Peripheral RNG get clock source
+  * @{
+  */
+#if defined(RCC_DCKCFGR_CK48MSEL) || defined(RCC_DCKCFGR2_CK48MSEL)
+#define LL_RCC_RNG_CLKSOURCE               LL_RCC_CK48M_CLKSOURCE /*!< RNG Clock source selection */
+#else
+#define LL_RCC_RNG_CLKSOURCE               RCC_PLLCFGR_PLLQ       /*!< RNG Clock source selection */
+#endif /* RCC_DCKCFGR_CK48MSEL || RCC_DCKCFGR2_CK48MSEL */
+/**
+  * @}
+  */
+#endif /* RNG */
+
+#if defined(USB_OTG_FS) || defined(USB_OTG_HS)
+/** @defgroup RCC_LL_EC_USB  Peripheral USB get clock source
+  * @{
+  */
+#if defined(RCC_DCKCFGR_CK48MSEL) || defined(RCC_DCKCFGR2_CK48MSEL)
+#define LL_RCC_USB_CLKSOURCE               LL_RCC_CK48M_CLKSOURCE /*!< USB Clock source selection */
+#else
+#define LL_RCC_USB_CLKSOURCE               RCC_PLLCFGR_PLLQ       /*!< USB Clock source selection */
+#endif /* RCC_DCKCFGR_CK48MSEL || RCC_DCKCFGR2_CK48MSEL */
+/**
+  * @}
+  */
+#endif /* USB_OTG_FS || USB_OTG_HS */
+
+#if defined(CEC)
+/** @defgroup RCC_LL_EC_CEC  Peripheral CEC get clock source
+  * @{
+  */
+#define LL_RCC_CEC_CLKSOURCE               RCC_DCKCFGR2_CECSEL /*!< CEC Clock source selection */
+/**
+  * @}
+  */
+#endif /* CEC */
+
+/** @defgroup RCC_LL_EC_I2S1  Peripheral I2S get clock source
+  * @{
+  */
+#if defined(RCC_CFGR_I2SSRC)
+#define LL_RCC_I2S1_CLKSOURCE              RCC_CFGR_I2SSRC     /*!< I2S1 Clock source selection */
+#endif /* RCC_CFGR_I2SSRC */
+#if defined(RCC_DCKCFGR_I2SSRC)
+#define LL_RCC_I2S1_CLKSOURCE              RCC_DCKCFGR_I2SSRC  /*!< I2S1 Clock source selection */
+#endif /* RCC_DCKCFGR_I2SSRC */
+#if defined(RCC_DCKCFGR_I2S1SRC)
+#define LL_RCC_I2S1_CLKSOURCE              RCC_DCKCFGR_I2S1SRC /*!< I2S1 Clock source selection */
+#endif /* RCC_DCKCFGR_I2S1SRC */
+#if defined(RCC_DCKCFGR_I2S2SRC)
+#define LL_RCC_I2S2_CLKSOURCE              RCC_DCKCFGR_I2S2SRC /*!< I2S2 Clock source selection */
+#endif /* RCC_DCKCFGR_I2S2SRC */
+/**
+  * @}
+  */
+
+#if defined(DFSDM1_Channel0) || defined(DFSDM2_Channel0)
+/** @defgroup RCC_LL_EC_DFSDM_AUDIO  Peripheral DFSDM Audio get clock source
+  * @{
+  */
+#define LL_RCC_DFSDM1_AUDIO_CLKSOURCE      RCC_DCKCFGR_CKDFSDM1ASEL /*!< DFSDM1 Audio Clock source selection */
+#if defined(DFSDM2_Channel0)
+#define LL_RCC_DFSDM2_AUDIO_CLKSOURCE      RCC_DCKCFGR_CKDFSDM2ASEL /*!< DFSDM2 Audio Clock source selection */
+#endif /* DFSDM2_Channel0 */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_DFSDM  Peripheral DFSDM get clock source
+  * @{
+  */
+#define LL_RCC_DFSDM1_CLKSOURCE            RCC_DCKCFGR_CKDFSDM1SEL /*!< DFSDM1 Clock source selection */
+#if defined(DFSDM2_Channel0)
+#define LL_RCC_DFSDM2_CLKSOURCE            RCC_DCKCFGR_CKDFSDM1SEL /*!< DFSDM2 Clock source selection */
+#endif /* DFSDM2_Channel0 */
+/**
+  * @}
+  */
+#endif /* DFSDM1_Channel0 || DFSDM2_Channel0 */
+
+#if defined(SPDIFRX)
+/** @defgroup RCC_LL_EC_SPDIFRX  Peripheral SPDIFRX get clock source
+  * @{
+  */
+#define LL_RCC_SPDIFRX1_CLKSOURCE          RCC_DCKCFGR2_SPDIFRXSEL /*!< SPDIFRX Clock source selection */
+/**
+  * @}
+  */
+#endif /* SPDIFRX */
+
+#if defined(DSI)
+/** @defgroup RCC_LL_EC_DSI  Peripheral DSI get clock source
+  * @{
+  */
+#define LL_RCC_DSI_CLKSOURCE               RCC_DCKCFGR_DSISEL /*!< DSI Clock source selection */
+/**
+  * @}
+  */
+#endif /* DSI */
+
+#if defined(LTDC)
+/** @defgroup RCC_LL_EC_LTDC  Peripheral LTDC get clock source
+  * @{
+  */
+#define LL_RCC_LTDC_CLKSOURCE              RCC_DCKCFGR_PLLSAIDIVR /*!< LTDC Clock source selection */
+/**
+  * @}
+  */
+#endif /* LTDC */
+
+
+/** @defgroup RCC_LL_EC_RTC_CLKSOURCE  RTC clock source selection
+  * @{
+  */
+#define LL_RCC_RTC_CLKSOURCE_NONE          0x00000000U                   /*!< No clock used as RTC clock */
+#define LL_RCC_RTC_CLKSOURCE_LSE           RCC_BDCR_RTCSEL_0       /*!< LSE oscillator clock used as RTC clock */
+#define LL_RCC_RTC_CLKSOURCE_LSI           RCC_BDCR_RTCSEL_1       /*!< LSI oscillator clock used as RTC clock */
+#define LL_RCC_RTC_CLKSOURCE_HSE           RCC_BDCR_RTCSEL         /*!< HSE oscillator clock divided by HSE prescaler used as RTC clock */
+/**
+  * @}
+  */
+
+#if defined(RCC_DCKCFGR_TIMPRE)
+/** @defgroup RCC_LL_EC_TIM_CLKPRESCALER  Timers clocks prescalers selection
+  * @{
+  */
+#define LL_RCC_TIM_PRESCALER_TWICE          0x00000000U                  /*!< Timers clock to twice PCLK */
+#define LL_RCC_TIM_PRESCALER_FOUR_TIMES     RCC_DCKCFGR_TIMPRE          /*!< Timers clock to four time PCLK */
+/**
+  * @}
+  */
+#endif /* RCC_DCKCFGR_TIMPRE */
+
+/** @defgroup RCC_LL_EC_PLLSOURCE  PLL, PLLI2S and PLLSAI entry clock source
+  * @{
+  */
+#define LL_RCC_PLLSOURCE_HSI               RCC_PLLCFGR_PLLSRC_HSI  /*!< HSI16 clock selected as PLL entry clock source */
+#define LL_RCC_PLLSOURCE_HSE               RCC_PLLCFGR_PLLSRC_HSE  /*!< HSE clock selected as PLL entry clock source */
+#if defined(RCC_PLLI2SCFGR_PLLI2SSRC)
+#define LL_RCC_PLLI2SSOURCE_PIN            (RCC_PLLI2SCFGR_PLLI2SSRC | 0x80U)  /*!< I2S External pin input clock selected as PLLI2S entry clock source */
+#endif /* RCC_PLLI2SCFGR_PLLI2SSRC */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_PLLM_DIV  PLL, PLLI2S and PLLSAI division factor
+  * @{
+  */
+#define LL_RCC_PLLM_DIV_2                  (RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 2 */
+#define LL_RCC_PLLM_DIV_3                  (RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 3 */
+#define LL_RCC_PLLM_DIV_4                  (RCC_PLLCFGR_PLLM_2) /*!< PLL, PLLI2S and PLLSAI division factor by 4 */
+#define LL_RCC_PLLM_DIV_5                  (RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 5 */
+#define LL_RCC_PLLM_DIV_6                  (RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 6 */
+#define LL_RCC_PLLM_DIV_7                  (RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 7 */
+#define LL_RCC_PLLM_DIV_8                  (RCC_PLLCFGR_PLLM_3) /*!< PLL, PLLI2S and PLLSAI division factor by 8 */
+#define LL_RCC_PLLM_DIV_9                  (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 9 */
+#define LL_RCC_PLLM_DIV_10                 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 10 */
+#define LL_RCC_PLLM_DIV_11                 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 11 */
+#define LL_RCC_PLLM_DIV_12                 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2) /*!< PLL, PLLI2S and PLLSAI division factor by 12 */
+#define LL_RCC_PLLM_DIV_13                 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 13 */
+#define LL_RCC_PLLM_DIV_14                 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 14 */
+#define LL_RCC_PLLM_DIV_15                 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 15 */
+#define LL_RCC_PLLM_DIV_16                 (RCC_PLLCFGR_PLLM_4) /*!< PLL, PLLI2S and PLLSAI division factor by 16 */
+#define LL_RCC_PLLM_DIV_17                 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 17 */
+#define LL_RCC_PLLM_DIV_18                 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 18 */
+#define LL_RCC_PLLM_DIV_19                 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 19 */
+#define LL_RCC_PLLM_DIV_20                 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2) /*!< PLL, PLLI2S and PLLSAI division factor by 20 */
+#define LL_RCC_PLLM_DIV_21                 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 21 */
+#define LL_RCC_PLLM_DIV_22                 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 22 */
+#define LL_RCC_PLLM_DIV_23                 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 23 */
+#define LL_RCC_PLLM_DIV_24                 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3) /*!< PLL, PLLI2S and PLLSAI division factor by 24 */
+#define LL_RCC_PLLM_DIV_25                 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 25 */
+#define LL_RCC_PLLM_DIV_26                 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 26 */
+#define LL_RCC_PLLM_DIV_27                 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 27 */
+#define LL_RCC_PLLM_DIV_28                 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2) /*!< PLL, PLLI2S and PLLSAI division factor by 28 */
+#define LL_RCC_PLLM_DIV_29                 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 29 */
+#define LL_RCC_PLLM_DIV_30                 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 30 */
+#define LL_RCC_PLLM_DIV_31                 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 31 */
+#define LL_RCC_PLLM_DIV_32                 (RCC_PLLCFGR_PLLM_5) /*!< PLL, PLLI2S and PLLSAI division factor by 32 */
+#define LL_RCC_PLLM_DIV_33                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 33 */
+#define LL_RCC_PLLM_DIV_34                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 34 */
+#define LL_RCC_PLLM_DIV_35                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 35 */
+#define LL_RCC_PLLM_DIV_36                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_2) /*!< PLL, PLLI2S and PLLSAI division factor by 36 */
+#define LL_RCC_PLLM_DIV_37                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 37 */
+#define LL_RCC_PLLM_DIV_38                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 38 */
+#define LL_RCC_PLLM_DIV_39                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 39 */
+#define LL_RCC_PLLM_DIV_40                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3) /*!< PLL, PLLI2S and PLLSAI division factor by 40 */
+#define LL_RCC_PLLM_DIV_41                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 41 */
+#define LL_RCC_PLLM_DIV_42                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 42 */
+#define LL_RCC_PLLM_DIV_43                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 43 */
+#define LL_RCC_PLLM_DIV_44                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2) /*!< PLL, PLLI2S and PLLSAI division factor by 44 */
+#define LL_RCC_PLLM_DIV_45                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 45 */
+#define LL_RCC_PLLM_DIV_46                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 46 */
+#define LL_RCC_PLLM_DIV_47                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 47 */
+#define LL_RCC_PLLM_DIV_48                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4) /*!< PLL, PLLI2S and PLLSAI division factor by 48 */
+#define LL_RCC_PLLM_DIV_49                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 49 */
+#define LL_RCC_PLLM_DIV_50                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 50 */
+#define LL_RCC_PLLM_DIV_51                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 51 */
+#define LL_RCC_PLLM_DIV_52                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2) /*!< PLL, PLLI2S and PLLSAI division factor by 52 */
+#define LL_RCC_PLLM_DIV_53                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 53 */
+#define LL_RCC_PLLM_DIV_54                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 54 */
+#define LL_RCC_PLLM_DIV_55                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 55 */
+#define LL_RCC_PLLM_DIV_56                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3) /*!< PLL, PLLI2S and PLLSAI division factor by 56 */
+#define LL_RCC_PLLM_DIV_57                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 57 */
+#define LL_RCC_PLLM_DIV_58                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 58 */
+#define LL_RCC_PLLM_DIV_59                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 59 */
+#define LL_RCC_PLLM_DIV_60                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2) /*!< PLL, PLLI2S and PLLSAI division factor by 60 */
+#define LL_RCC_PLLM_DIV_61                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 61 */
+#define LL_RCC_PLLM_DIV_62                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 62 */
+#define LL_RCC_PLLM_DIV_63                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 63 */
+/**
+  * @}
+  */
+
+#if defined(RCC_PLLCFGR_PLLR)
+/** @defgroup RCC_LL_EC_PLLR_DIV  PLL division factor (PLLR)
+  * @{
+  */
+#define LL_RCC_PLLR_DIV_2                  (RCC_PLLCFGR_PLLR_1)                     /*!< Main PLL division factor for PLLCLK (system clock) by 2 */
+#define LL_RCC_PLLR_DIV_3                  (RCC_PLLCFGR_PLLR_1|RCC_PLLCFGR_PLLR_0)  /*!< Main PLL division factor for PLLCLK (system clock) by 3 */
+#define LL_RCC_PLLR_DIV_4                  (RCC_PLLCFGR_PLLR_2)                     /*!< Main PLL division factor for PLLCLK (system clock) by 4 */
+#define LL_RCC_PLLR_DIV_5                  (RCC_PLLCFGR_PLLR_2|RCC_PLLCFGR_PLLR_0)  /*!< Main PLL division factor for PLLCLK (system clock) by 5 */
+#define LL_RCC_PLLR_DIV_6                  (RCC_PLLCFGR_PLLR_2|RCC_PLLCFGR_PLLR_1)  /*!< Main PLL division factor for PLLCLK (system clock) by 6 */
+#define LL_RCC_PLLR_DIV_7                  (RCC_PLLCFGR_PLLR)                       /*!< Main PLL division factor for PLLCLK (system clock) by 7 */
+/**
+  * @}
+  */
+#endif /* RCC_PLLCFGR_PLLR */
+
+#if defined(RCC_DCKCFGR_PLLDIVR)
+/** @defgroup RCC_LL_EC_PLLDIVR  PLLDIVR division factor (PLLDIVR)
+  * @{
+  */
+#define LL_RCC_PLLDIVR_DIV_1           (RCC_DCKCFGR_PLLDIVR_0)        /*!< PLL division factor for PLLDIVR output by 1 */
+#define LL_RCC_PLLDIVR_DIV_2           (RCC_DCKCFGR_PLLDIVR_1)        /*!< PLL division factor for PLLDIVR output by 2 */
+#define LL_RCC_PLLDIVR_DIV_3           (RCC_DCKCFGR_PLLDIVR_1 | RCC_DCKCFGR_PLLDIVR_0)        /*!< PLL division factor for PLLDIVR output by 3 */
+#define LL_RCC_PLLDIVR_DIV_4           (RCC_DCKCFGR_PLLDIVR_2)        /*!< PLL division factor for PLLDIVR output by 4 */
+#define LL_RCC_PLLDIVR_DIV_5           (RCC_DCKCFGR_PLLDIVR_2 | RCC_DCKCFGR_PLLDIVR_0)        /*!< PLL division factor for PLLDIVR output by 5 */
+#define LL_RCC_PLLDIVR_DIV_6           (RCC_DCKCFGR_PLLDIVR_2 | RCC_DCKCFGR_PLLDIVR_1)        /*!< PLL division factor for PLLDIVR output by 6 */
+#define LL_RCC_PLLDIVR_DIV_7           (RCC_DCKCFGR_PLLDIVR_2 | RCC_DCKCFGR_PLLDIVR_1 | RCC_DCKCFGR_PLLDIVR_0)        /*!< PLL division factor for PLLDIVR output by 7 */
+#define LL_RCC_PLLDIVR_DIV_8           (RCC_DCKCFGR_PLLDIVR_3)        /*!< PLL division factor for PLLDIVR output by 8 */
+#define LL_RCC_PLLDIVR_DIV_9           (RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_0)        /*!< PLL division factor for PLLDIVR output by 9 */
+#define LL_RCC_PLLDIVR_DIV_10          (RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_1)        /*!< PLL division factor for PLLDIVR output by 10 */
+#define LL_RCC_PLLDIVR_DIV_11          (RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_1 | RCC_DCKCFGR_PLLDIVR_0)        /*!< PLL division factor for PLLDIVR output by 11 */
+#define LL_RCC_PLLDIVR_DIV_12          (RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_2)        /*!< PLL division factor for PLLDIVR output by 12 */
+#define LL_RCC_PLLDIVR_DIV_13          (RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_2 | RCC_DCKCFGR_PLLDIVR_0)        /*!< PLL division factor for PLLDIVR output by 13 */
+#define LL_RCC_PLLDIVR_DIV_14          (RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_2 | RCC_DCKCFGR_PLLDIVR_1)        /*!< PLL division factor for PLLDIVR output by 14 */
+#define LL_RCC_PLLDIVR_DIV_15          (RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_2 | RCC_DCKCFGR_PLLDIVR_1 | RCC_DCKCFGR_PLLDIVR_0)        /*!< PLL division factor for PLLDIVR output by 15 */
+#define LL_RCC_PLLDIVR_DIV_16          (RCC_DCKCFGR_PLLDIVR_4)             /*!< PLL division factor for PLLDIVR output by 16 */
+#define LL_RCC_PLLDIVR_DIV_17          (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_0)        /*!< PLL division factor for PLLDIVR output by 17 */
+#define LL_RCC_PLLDIVR_DIV_18          (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_1)        /*!< PLL division factor for PLLDIVR output by 18 */
+#define LL_RCC_PLLDIVR_DIV_19          (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_1 | RCC_DCKCFGR_PLLDIVR_0)        /*!< PLL division factor for PLLDIVR output by 19 */
+#define LL_RCC_PLLDIVR_DIV_20          (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_2)        /*!< PLL division factor for PLLDIVR output by 20 */
+#define LL_RCC_PLLDIVR_DIV_21          (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_2 | RCC_DCKCFGR_PLLDIVR_0)        /*!< PLL division factor for PLLDIVR output by 21 */
+#define LL_RCC_PLLDIVR_DIV_22          (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_2 | RCC_DCKCFGR_PLLDIVR_1)        /*!< PLL division factor for PLLDIVR output by 22 */
+#define LL_RCC_PLLDIVR_DIV_23          (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_2 | RCC_DCKCFGR_PLLDIVR_1 | RCC_DCKCFGR_PLLDIVR_0)        /*!< PLL division factor for PLLDIVR output by 23 */
+#define LL_RCC_PLLDIVR_DIV_24          (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_3)        /*!< PLL division factor for PLLDIVR output by 24 */
+#define LL_RCC_PLLDIVR_DIV_25          (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_0)        /*!< PLL division factor for PLLDIVR output by 25 */
+#define LL_RCC_PLLDIVR_DIV_26          (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_1)        /*!< PLL division factor for PLLDIVR output by 26 */
+#define LL_RCC_PLLDIVR_DIV_27          (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_1 | RCC_DCKCFGR_PLLDIVR_0)        /*!< PLL division factor for PLLDIVR output by 27 */
+#define LL_RCC_PLLDIVR_DIV_28          (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_2)        /*!< PLL division factor for PLLDIVR output by 28 */
+#define LL_RCC_PLLDIVR_DIV_29          (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_2 | RCC_DCKCFGR_PLLDIVR_0)        /*!< PLL division factor for PLLDIVR output by 29 */
+#define LL_RCC_PLLDIVR_DIV_30          (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_2 | RCC_DCKCFGR_PLLDIVR_1)        /*!< PLL division factor for PLLDIVR output by 30 */
+#define LL_RCC_PLLDIVR_DIV_31          (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_2 | RCC_DCKCFGR_PLLDIVR_1 | RCC_DCKCFGR_PLLDIVR_0)        /*!< PLL division factor for PLLDIVR output by 31 */
+/**
+  * @}
+  */
+#endif /* RCC_DCKCFGR_PLLDIVR */
+
+/** @defgroup RCC_LL_EC_PLLP_DIV  PLL division factor (PLLP)
+  * @{
+  */
+#define LL_RCC_PLLP_DIV_2                  0x00000000U            /*!< Main PLL division factor for PLLP output by 2 */
+#define LL_RCC_PLLP_DIV_4                  RCC_PLLCFGR_PLLP_0     /*!< Main PLL division factor for PLLP output by 4 */
+#define LL_RCC_PLLP_DIV_6                  RCC_PLLCFGR_PLLP_1     /*!< Main PLL division factor for PLLP output by 6 */
+#define LL_RCC_PLLP_DIV_8                  (RCC_PLLCFGR_PLLP_1 | RCC_PLLCFGR_PLLP_0)   /*!< Main PLL division factor for PLLP output by 8 */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_PLLQ_DIV  PLL division factor (PLLQ)
+  * @{
+  */
+#define LL_RCC_PLLQ_DIV_2                  RCC_PLLCFGR_PLLQ_1                      /*!< Main PLL division factor for PLLQ output by 2 */
+#define LL_RCC_PLLQ_DIV_3                  (RCC_PLLCFGR_PLLQ_1|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 3 */
+#define LL_RCC_PLLQ_DIV_4                  RCC_PLLCFGR_PLLQ_2                      /*!< Main PLL division factor for PLLQ output by 4 */
+#define LL_RCC_PLLQ_DIV_5                  (RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 5 */
+#define LL_RCC_PLLQ_DIV_6                  (RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_1) /*!< Main PLL division factor for PLLQ output by 6 */
+#define LL_RCC_PLLQ_DIV_7                  (RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_1|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 7 */
+#define LL_RCC_PLLQ_DIV_8                  RCC_PLLCFGR_PLLQ_3                      /*!< Main PLL division factor for PLLQ output by 8 */
+#define LL_RCC_PLLQ_DIV_9                  (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 9 */
+#define LL_RCC_PLLQ_DIV_10                 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_1) /*!< Main PLL division factor for PLLQ output by 10 */
+#define LL_RCC_PLLQ_DIV_11                 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_1|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 11 */
+#define LL_RCC_PLLQ_DIV_12                 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_2) /*!< Main PLL division factor for PLLQ output by 12 */
+#define LL_RCC_PLLQ_DIV_13                 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 13 */
+#define LL_RCC_PLLQ_DIV_14                 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_1) /*!< Main PLL division factor for PLLQ output by 14 */
+#define LL_RCC_PLLQ_DIV_15                 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_1|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 15 */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_PLL_SPRE_SEL  PLL Spread Spectrum Selection
+  * @{
+  */
+#define LL_RCC_SPREAD_SELECT_CENTER        0x00000000U                   /*!< PLL center spread spectrum selection */
+#define LL_RCC_SPREAD_SELECT_DOWN          RCC_SSCGR_SPREADSEL           /*!< PLL down spread spectrum selection */
+/**
+  * @}
+  */
+
+#if defined(RCC_PLLI2S_SUPPORT)
+/** @defgroup RCC_LL_EC_PLLI2SM  PLLI2SM division factor (PLLI2SM)
+  * @{
+  */
+#if defined(RCC_PLLI2SCFGR_PLLI2SM)
+#define LL_RCC_PLLI2SM_DIV_2             (RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 2 */
+#define LL_RCC_PLLI2SM_DIV_3             (RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 3 */
+#define LL_RCC_PLLI2SM_DIV_4             (RCC_PLLI2SCFGR_PLLI2SM_2) /*!< PLLI2S division factor for PLLI2SM output by 4 */
+#define LL_RCC_PLLI2SM_DIV_5             (RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 5 */
+#define LL_RCC_PLLI2SM_DIV_6             (RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 6 */
+#define LL_RCC_PLLI2SM_DIV_7             (RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 7 */
+#define LL_RCC_PLLI2SM_DIV_8             (RCC_PLLI2SCFGR_PLLI2SM_3) /*!< PLLI2S division factor for PLLI2SM output by 8 */
+#define LL_RCC_PLLI2SM_DIV_9             (RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 9 */
+#define LL_RCC_PLLI2SM_DIV_10            (RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 10 */
+#define LL_RCC_PLLI2SM_DIV_11            (RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 11 */
+#define LL_RCC_PLLI2SM_DIV_12            (RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2) /*!< PLLI2S division factor for PLLI2SM output by 12 */
+#define LL_RCC_PLLI2SM_DIV_13            (RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 13 */
+#define LL_RCC_PLLI2SM_DIV_14            (RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 14 */
+#define LL_RCC_PLLI2SM_DIV_15            (RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 15 */
+#define LL_RCC_PLLI2SM_DIV_16            (RCC_PLLI2SCFGR_PLLI2SM_4) /*!< PLLI2S division factor for PLLI2SM output by 16 */
+#define LL_RCC_PLLI2SM_DIV_17            (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 17 */
+#define LL_RCC_PLLI2SM_DIV_18            (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 18 */
+#define LL_RCC_PLLI2SM_DIV_19            (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 19 */
+#define LL_RCC_PLLI2SM_DIV_20            (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_2) /*!< PLLI2S division factor for PLLI2SM output by 20 */
+#define LL_RCC_PLLI2SM_DIV_21            (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 21 */
+#define LL_RCC_PLLI2SM_DIV_22            (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 22 */
+#define LL_RCC_PLLI2SM_DIV_23            (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 23 */
+#define LL_RCC_PLLI2SM_DIV_24            (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3) /*!< PLLI2S division factor for PLLI2SM output by 24 */
+#define LL_RCC_PLLI2SM_DIV_25            (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 25 */
+#define LL_RCC_PLLI2SM_DIV_26            (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 26 */
+#define LL_RCC_PLLI2SM_DIV_27            (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 27 */
+#define LL_RCC_PLLI2SM_DIV_28            (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2) /*!< PLLI2S division factor for PLLI2SM output by 28 */
+#define LL_RCC_PLLI2SM_DIV_29            (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 29 */
+#define LL_RCC_PLLI2SM_DIV_30            (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 30 */
+#define LL_RCC_PLLI2SM_DIV_31            (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 31 */
+#define LL_RCC_PLLI2SM_DIV_32            (RCC_PLLI2SCFGR_PLLI2SM_5) /*!< PLLI2S division factor for PLLI2SM output by 32 */
+#define LL_RCC_PLLI2SM_DIV_33            (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 33 */
+#define LL_RCC_PLLI2SM_DIV_34            (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 34 */
+#define LL_RCC_PLLI2SM_DIV_35            (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 35 */
+#define LL_RCC_PLLI2SM_DIV_36            (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_2) /*!< PLLI2S division factor for PLLI2SM output by 36 */
+#define LL_RCC_PLLI2SM_DIV_37            (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 37 */
+#define LL_RCC_PLLI2SM_DIV_38            (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 38 */
+#define LL_RCC_PLLI2SM_DIV_39            (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 39 */
+#define LL_RCC_PLLI2SM_DIV_40            (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_3) /*!< PLLI2S division factor for PLLI2SM output by 40 */
+#define LL_RCC_PLLI2SM_DIV_41            (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 41 */
+#define LL_RCC_PLLI2SM_DIV_42            (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 42 */
+#define LL_RCC_PLLI2SM_DIV_43            (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 43 */
+#define LL_RCC_PLLI2SM_DIV_44            (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2) /*!< PLLI2S division factor for PLLI2SM output by 44 */
+#define LL_RCC_PLLI2SM_DIV_45            (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 45 */
+#define LL_RCC_PLLI2SM_DIV_46            (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 46 */
+#define LL_RCC_PLLI2SM_DIV_47            (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 47 */
+#define LL_RCC_PLLI2SM_DIV_48            (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4) /*!< PLLI2S division factor for PLLI2SM output by 48 */
+#define LL_RCC_PLLI2SM_DIV_49            (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 49 */
+#define LL_RCC_PLLI2SM_DIV_50            (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 50 */
+#define LL_RCC_PLLI2SM_DIV_51            (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 51 */
+#define LL_RCC_PLLI2SM_DIV_52            (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_2) /*!< PLLI2S division factor for PLLI2SM output by 52 */
+#define LL_RCC_PLLI2SM_DIV_53            (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 53 */
+#define LL_RCC_PLLI2SM_DIV_54            (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 54 */
+#define LL_RCC_PLLI2SM_DIV_55            (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 55 */
+#define LL_RCC_PLLI2SM_DIV_56            (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3) /*!< PLLI2S division factor for PLLI2SM output by 56 */
+#define LL_RCC_PLLI2SM_DIV_57            (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 57 */
+#define LL_RCC_PLLI2SM_DIV_58            (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 58 */
+#define LL_RCC_PLLI2SM_DIV_59            (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 59 */
+#define LL_RCC_PLLI2SM_DIV_60            (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2) /*!< PLLI2S division factor for PLLI2SM output by 60 */
+#define LL_RCC_PLLI2SM_DIV_61            (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 61 */
+#define LL_RCC_PLLI2SM_DIV_62            (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 62 */
+#define LL_RCC_PLLI2SM_DIV_63            (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 63 */
+#else
+#define LL_RCC_PLLI2SM_DIV_2              LL_RCC_PLLM_DIV_2      /*!< PLLI2S division factor for PLLI2SM output by 2 */
+#define LL_RCC_PLLI2SM_DIV_3              LL_RCC_PLLM_DIV_3      /*!< PLLI2S division factor for PLLI2SM output by 3 */
+#define LL_RCC_PLLI2SM_DIV_4              LL_RCC_PLLM_DIV_4      /*!< PLLI2S division factor for PLLI2SM output by 4 */
+#define LL_RCC_PLLI2SM_DIV_5              LL_RCC_PLLM_DIV_5      /*!< PLLI2S division factor for PLLI2SM output by 5 */
+#define LL_RCC_PLLI2SM_DIV_6              LL_RCC_PLLM_DIV_6      /*!< PLLI2S division factor for PLLI2SM output by 6 */
+#define LL_RCC_PLLI2SM_DIV_7              LL_RCC_PLLM_DIV_7      /*!< PLLI2S division factor for PLLI2SM output by 7 */
+#define LL_RCC_PLLI2SM_DIV_8              LL_RCC_PLLM_DIV_8      /*!< PLLI2S division factor for PLLI2SM output by 8 */
+#define LL_RCC_PLLI2SM_DIV_9              LL_RCC_PLLM_DIV_9      /*!< PLLI2S division factor for PLLI2SM output by 9 */
+#define LL_RCC_PLLI2SM_DIV_10             LL_RCC_PLLM_DIV_10     /*!< PLLI2S division factor for PLLI2SM output by 10 */
+#define LL_RCC_PLLI2SM_DIV_11             LL_RCC_PLLM_DIV_11     /*!< PLLI2S division factor for PLLI2SM output by 11 */
+#define LL_RCC_PLLI2SM_DIV_12             LL_RCC_PLLM_DIV_12     /*!< PLLI2S division factor for PLLI2SM output by 12 */
+#define LL_RCC_PLLI2SM_DIV_13             LL_RCC_PLLM_DIV_13     /*!< PLLI2S division factor for PLLI2SM output by 13 */
+#define LL_RCC_PLLI2SM_DIV_14             LL_RCC_PLLM_DIV_14     /*!< PLLI2S division factor for PLLI2SM output by 14 */
+#define LL_RCC_PLLI2SM_DIV_15             LL_RCC_PLLM_DIV_15     /*!< PLLI2S division factor for PLLI2SM output by 15 */
+#define LL_RCC_PLLI2SM_DIV_16             LL_RCC_PLLM_DIV_16     /*!< PLLI2S division factor for PLLI2SM output by 16 */
+#define LL_RCC_PLLI2SM_DIV_17             LL_RCC_PLLM_DIV_17     /*!< PLLI2S division factor for PLLI2SM output by 17 */
+#define LL_RCC_PLLI2SM_DIV_18             LL_RCC_PLLM_DIV_18     /*!< PLLI2S division factor for PLLI2SM output by 18 */
+#define LL_RCC_PLLI2SM_DIV_19             LL_RCC_PLLM_DIV_19     /*!< PLLI2S division factor for PLLI2SM output by 19 */
+#define LL_RCC_PLLI2SM_DIV_20             LL_RCC_PLLM_DIV_20     /*!< PLLI2S division factor for PLLI2SM output by 20 */
+#define LL_RCC_PLLI2SM_DIV_21             LL_RCC_PLLM_DIV_21     /*!< PLLI2S division factor for PLLI2SM output by 21 */
+#define LL_RCC_PLLI2SM_DIV_22             LL_RCC_PLLM_DIV_22     /*!< PLLI2S division factor for PLLI2SM output by 22 */
+#define LL_RCC_PLLI2SM_DIV_23             LL_RCC_PLLM_DIV_23     /*!< PLLI2S division factor for PLLI2SM output by 23 */
+#define LL_RCC_PLLI2SM_DIV_24             LL_RCC_PLLM_DIV_24     /*!< PLLI2S division factor for PLLI2SM output by 24 */
+#define LL_RCC_PLLI2SM_DIV_25             LL_RCC_PLLM_DIV_25     /*!< PLLI2S division factor for PLLI2SM output by 25 */
+#define LL_RCC_PLLI2SM_DIV_26             LL_RCC_PLLM_DIV_26     /*!< PLLI2S division factor for PLLI2SM output by 26 */
+#define LL_RCC_PLLI2SM_DIV_27             LL_RCC_PLLM_DIV_27     /*!< PLLI2S division factor for PLLI2SM output by 27 */
+#define LL_RCC_PLLI2SM_DIV_28             LL_RCC_PLLM_DIV_28     /*!< PLLI2S division factor for PLLI2SM output by 28 */
+#define LL_RCC_PLLI2SM_DIV_29             LL_RCC_PLLM_DIV_29     /*!< PLLI2S division factor for PLLI2SM output by 29 */
+#define LL_RCC_PLLI2SM_DIV_30             LL_RCC_PLLM_DIV_30     /*!< PLLI2S division factor for PLLI2SM output by 30 */
+#define LL_RCC_PLLI2SM_DIV_31             LL_RCC_PLLM_DIV_31     /*!< PLLI2S division factor for PLLI2SM output by 31 */
+#define LL_RCC_PLLI2SM_DIV_32             LL_RCC_PLLM_DIV_32     /*!< PLLI2S division factor for PLLI2SM output by 32 */
+#define LL_RCC_PLLI2SM_DIV_33             LL_RCC_PLLM_DIV_33     /*!< PLLI2S division factor for PLLI2SM output by 33 */
+#define LL_RCC_PLLI2SM_DIV_34             LL_RCC_PLLM_DIV_34     /*!< PLLI2S division factor for PLLI2SM output by 34 */
+#define LL_RCC_PLLI2SM_DIV_35             LL_RCC_PLLM_DIV_35     /*!< PLLI2S division factor for PLLI2SM output by 35 */
+#define LL_RCC_PLLI2SM_DIV_36             LL_RCC_PLLM_DIV_36     /*!< PLLI2S division factor for PLLI2SM output by 36 */
+#define LL_RCC_PLLI2SM_DIV_37             LL_RCC_PLLM_DIV_37     /*!< PLLI2S division factor for PLLI2SM output by 37 */
+#define LL_RCC_PLLI2SM_DIV_38             LL_RCC_PLLM_DIV_38     /*!< PLLI2S division factor for PLLI2SM output by 38 */
+#define LL_RCC_PLLI2SM_DIV_39             LL_RCC_PLLM_DIV_39     /*!< PLLI2S division factor for PLLI2SM output by 39 */
+#define LL_RCC_PLLI2SM_DIV_40             LL_RCC_PLLM_DIV_40     /*!< PLLI2S division factor for PLLI2SM output by 40 */
+#define LL_RCC_PLLI2SM_DIV_41             LL_RCC_PLLM_DIV_41     /*!< PLLI2S division factor for PLLI2SM output by 41 */
+#define LL_RCC_PLLI2SM_DIV_42             LL_RCC_PLLM_DIV_42     /*!< PLLI2S division factor for PLLI2SM output by 42 */
+#define LL_RCC_PLLI2SM_DIV_43             LL_RCC_PLLM_DIV_43     /*!< PLLI2S division factor for PLLI2SM output by 43 */
+#define LL_RCC_PLLI2SM_DIV_44             LL_RCC_PLLM_DIV_44     /*!< PLLI2S division factor for PLLI2SM output by 44 */
+#define LL_RCC_PLLI2SM_DIV_45             LL_RCC_PLLM_DIV_45     /*!< PLLI2S division factor for PLLI2SM output by 45 */
+#define LL_RCC_PLLI2SM_DIV_46             LL_RCC_PLLM_DIV_46     /*!< PLLI2S division factor for PLLI2SM output by 46 */
+#define LL_RCC_PLLI2SM_DIV_47             LL_RCC_PLLM_DIV_47     /*!< PLLI2S division factor for PLLI2SM output by 47 */
+#define LL_RCC_PLLI2SM_DIV_48             LL_RCC_PLLM_DIV_48     /*!< PLLI2S division factor for PLLI2SM output by 48 */
+#define LL_RCC_PLLI2SM_DIV_49             LL_RCC_PLLM_DIV_49     /*!< PLLI2S division factor for PLLI2SM output by 49 */
+#define LL_RCC_PLLI2SM_DIV_50             LL_RCC_PLLM_DIV_50     /*!< PLLI2S division factor for PLLI2SM output by 50 */
+#define LL_RCC_PLLI2SM_DIV_51             LL_RCC_PLLM_DIV_51     /*!< PLLI2S division factor for PLLI2SM output by 51 */
+#define LL_RCC_PLLI2SM_DIV_52             LL_RCC_PLLM_DIV_52     /*!< PLLI2S division factor for PLLI2SM output by 52 */
+#define LL_RCC_PLLI2SM_DIV_53             LL_RCC_PLLM_DIV_53     /*!< PLLI2S division factor for PLLI2SM output by 53 */
+#define LL_RCC_PLLI2SM_DIV_54             LL_RCC_PLLM_DIV_54     /*!< PLLI2S division factor for PLLI2SM output by 54 */
+#define LL_RCC_PLLI2SM_DIV_55             LL_RCC_PLLM_DIV_55     /*!< PLLI2S division factor for PLLI2SM output by 55 */
+#define LL_RCC_PLLI2SM_DIV_56             LL_RCC_PLLM_DIV_56     /*!< PLLI2S division factor for PLLI2SM output by 56 */
+#define LL_RCC_PLLI2SM_DIV_57             LL_RCC_PLLM_DIV_57     /*!< PLLI2S division factor for PLLI2SM output by 57 */
+#define LL_RCC_PLLI2SM_DIV_58             LL_RCC_PLLM_DIV_58     /*!< PLLI2S division factor for PLLI2SM output by 58 */
+#define LL_RCC_PLLI2SM_DIV_59             LL_RCC_PLLM_DIV_59     /*!< PLLI2S division factor for PLLI2SM output by 59 */
+#define LL_RCC_PLLI2SM_DIV_60             LL_RCC_PLLM_DIV_60     /*!< PLLI2S division factor for PLLI2SM output by 60 */
+#define LL_RCC_PLLI2SM_DIV_61             LL_RCC_PLLM_DIV_61     /*!< PLLI2S division factor for PLLI2SM output by 61 */
+#define LL_RCC_PLLI2SM_DIV_62             LL_RCC_PLLM_DIV_62     /*!< PLLI2S division factor for PLLI2SM output by 62 */
+#define LL_RCC_PLLI2SM_DIV_63             LL_RCC_PLLM_DIV_63     /*!< PLLI2S division factor for PLLI2SM output by 63 */
+#endif /* RCC_PLLI2SCFGR_PLLI2SM */
+/**
+  * @}
+  */
+
+#if defined(RCC_PLLI2SCFGR_PLLI2SQ)
+/** @defgroup RCC_LL_EC_PLLI2SQ  PLLI2SQ division factor (PLLI2SQ)
+  * @{
+  */
+#define LL_RCC_PLLI2SQ_DIV_2              RCC_PLLI2SCFGR_PLLI2SQ_1        /*!< PLLI2S division factor for PLLI2SQ output by 2 */
+#define LL_RCC_PLLI2SQ_DIV_3              (RCC_PLLI2SCFGR_PLLI2SQ_1 | RCC_PLLI2SCFGR_PLLI2SQ_0)        /*!< PLLI2S division factor for PLLI2SQ output by 3 */
+#define LL_RCC_PLLI2SQ_DIV_4              RCC_PLLI2SCFGR_PLLI2SQ_2        /*!< PLLI2S division factor for PLLI2SQ output by 4 */
+#define LL_RCC_PLLI2SQ_DIV_5              (RCC_PLLI2SCFGR_PLLI2SQ_2 | RCC_PLLI2SCFGR_PLLI2SQ_0)        /*!< PLLI2S division factor for PLLI2SQ output by 5 */
+#define LL_RCC_PLLI2SQ_DIV_6              (RCC_PLLI2SCFGR_PLLI2SQ_2 | RCC_PLLI2SCFGR_PLLI2SQ_1)        /*!< PLLI2S division factor for PLLI2SQ output by 6 */
+#define LL_RCC_PLLI2SQ_DIV_7              (RCC_PLLI2SCFGR_PLLI2SQ_2 | RCC_PLLI2SCFGR_PLLI2SQ_1 | RCC_PLLI2SCFGR_PLLI2SQ_0)        /*!< PLLI2S division factor for PLLI2SQ output by 7 */
+#define LL_RCC_PLLI2SQ_DIV_8              RCC_PLLI2SCFGR_PLLI2SQ_3        /*!< PLLI2S division factor for PLLI2SQ output by 8 */
+#define LL_RCC_PLLI2SQ_DIV_9              (RCC_PLLI2SCFGR_PLLI2SQ_3 | RCC_PLLI2SCFGR_PLLI2SQ_0)        /*!< PLLI2S division factor for PLLI2SQ output by 9 */
+#define LL_RCC_PLLI2SQ_DIV_10             (RCC_PLLI2SCFGR_PLLI2SQ_3 | RCC_PLLI2SCFGR_PLLI2SQ_1)        /*!< PLLI2S division factor for PLLI2SQ output by 10 */
+#define LL_RCC_PLLI2SQ_DIV_11             (RCC_PLLI2SCFGR_PLLI2SQ_3 | RCC_PLLI2SCFGR_PLLI2SQ_1 | RCC_PLLI2SCFGR_PLLI2SQ_0)        /*!< PLLI2S division factor for PLLI2SQ output by 11 */
+#define LL_RCC_PLLI2SQ_DIV_12             (RCC_PLLI2SCFGR_PLLI2SQ_3 | RCC_PLLI2SCFGR_PLLI2SQ_2)        /*!< PLLI2S division factor for PLLI2SQ output by 12 */
+#define LL_RCC_PLLI2SQ_DIV_13             (RCC_PLLI2SCFGR_PLLI2SQ_3 | RCC_PLLI2SCFGR_PLLI2SQ_2 | RCC_PLLI2SCFGR_PLLI2SQ_0)        /*!< PLLI2S division factor for PLLI2SQ output by 13 */
+#define LL_RCC_PLLI2SQ_DIV_14             (RCC_PLLI2SCFGR_PLLI2SQ_3 | RCC_PLLI2SCFGR_PLLI2SQ_2 | RCC_PLLI2SCFGR_PLLI2SQ_1)        /*!< PLLI2S division factor for PLLI2SQ output by 14 */
+#define LL_RCC_PLLI2SQ_DIV_15             (RCC_PLLI2SCFGR_PLLI2SQ_3 | RCC_PLLI2SCFGR_PLLI2SQ_2 | RCC_PLLI2SCFGR_PLLI2SQ_1 | RCC_PLLI2SCFGR_PLLI2SQ_0)        /*!< PLLI2S division factor for PLLI2SQ output by 15 */
+/**
+  * @}
+  */
+#endif /* RCC_PLLI2SCFGR_PLLI2SQ */
+
+#if defined(RCC_DCKCFGR_PLLI2SDIVQ)
+/** @defgroup RCC_LL_EC_PLLI2SDIVQ  PLLI2SDIVQ division factor (PLLI2SDIVQ)
+  * @{
+  */
+#define LL_RCC_PLLI2SDIVQ_DIV_1           0x00000000U                        /*!< PLLI2S division factor for PLLI2SDIVQ output by 1 */
+#define LL_RCC_PLLI2SDIVQ_DIV_2           RCC_DCKCFGR_PLLI2SDIVQ_0          /*!< PLLI2S division factor for PLLI2SDIVQ output by 2 */
+#define LL_RCC_PLLI2SDIVQ_DIV_3           RCC_DCKCFGR_PLLI2SDIVQ_1          /*!< PLLI2S division factor for PLLI2SDIVQ output by 3 */
+#define LL_RCC_PLLI2SDIVQ_DIV_4           (RCC_DCKCFGR_PLLI2SDIVQ_1 | RCC_DCKCFGR_PLLI2SDIVQ_0)        /*!< PLLI2S division factor for PLLI2SDIVQ output by 4 */
+#define LL_RCC_PLLI2SDIVQ_DIV_5           RCC_DCKCFGR_PLLI2SDIVQ_2          /*!< PLLI2S division factor for PLLI2SDIVQ output by 5 */
+#define LL_RCC_PLLI2SDIVQ_DIV_6           (RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_0)        /*!< PLLI2S division factor for PLLI2SDIVQ output by 6 */
+#define LL_RCC_PLLI2SDIVQ_DIV_7           (RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_1)        /*!< PLLI2S division factor for PLLI2SDIVQ output by 7 */
+#define LL_RCC_PLLI2SDIVQ_DIV_8           (RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_1 | RCC_DCKCFGR_PLLI2SDIVQ_0)        /*!< PLLI2S division factor for PLLI2SDIVQ output by 8 */
+#define LL_RCC_PLLI2SDIVQ_DIV_9           RCC_DCKCFGR_PLLI2SDIVQ_3          /*!< PLLI2S division factor for PLLI2SDIVQ output by 9 */
+#define LL_RCC_PLLI2SDIVQ_DIV_10          (RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_0)        /*!< PLLI2S division factor for PLLI2SDIVQ output by 10 */
+#define LL_RCC_PLLI2SDIVQ_DIV_11          (RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_1)        /*!< PLLI2S division factor for PLLI2SDIVQ output by 11 */
+#define LL_RCC_PLLI2SDIVQ_DIV_12          (RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_1 | RCC_DCKCFGR_PLLI2SDIVQ_0)        /*!< PLLI2S division factor for PLLI2SDIVQ output by 12 */
+#define LL_RCC_PLLI2SDIVQ_DIV_13          (RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_2)        /*!< PLLI2S division factor for PLLI2SDIVQ output by 13 */
+#define LL_RCC_PLLI2SDIVQ_DIV_14          (RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_0)        /*!< PLLI2S division factor for PLLI2SDIVQ output by 14 */
+#define LL_RCC_PLLI2SDIVQ_DIV_15          (RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_1)        /*!< PLLI2S division factor for PLLI2SDIVQ output by 15 */
+#define LL_RCC_PLLI2SDIVQ_DIV_16          (RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_1 | RCC_DCKCFGR_PLLI2SDIVQ_0)        /*!< PLLI2S division factor for PLLI2SDIVQ output by 16 */
+#define LL_RCC_PLLI2SDIVQ_DIV_17          RCC_DCKCFGR_PLLI2SDIVQ_4          /*!< PLLI2S division factor for PLLI2SDIVQ output by 17 */
+#define LL_RCC_PLLI2SDIVQ_DIV_18          (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_0)        /*!< PLLI2S division factor for PLLI2SDIVQ output by 18 */
+#define LL_RCC_PLLI2SDIVQ_DIV_19          (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_1)        /*!< PLLI2S division factor for PLLI2SDIVQ output by 19 */
+#define LL_RCC_PLLI2SDIVQ_DIV_20          (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_1 | RCC_DCKCFGR_PLLI2SDIVQ_0)        /*!< PLLI2S division factor for PLLI2SDIVQ output by 20 */
+#define LL_RCC_PLLI2SDIVQ_DIV_21          (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_2)        /*!< PLLI2S division factor for PLLI2SDIVQ output by 21 */
+#define LL_RCC_PLLI2SDIVQ_DIV_22          (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_0)        /*!< PLLI2S division factor for PLLI2SDIVQ output by 22 */
+#define LL_RCC_PLLI2SDIVQ_DIV_23          (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_1)        /*!< PLLI2S division factor for PLLI2SDIVQ output by 23 */
+#define LL_RCC_PLLI2SDIVQ_DIV_24          (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_1 | RCC_DCKCFGR_PLLI2SDIVQ_0)        /*!< PLLI2S division factor for PLLI2SDIVQ output by 24 */
+#define LL_RCC_PLLI2SDIVQ_DIV_25          (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_3)        /*!< PLLI2S division factor for PLLI2SDIVQ output by 25 */
+#define LL_RCC_PLLI2SDIVQ_DIV_26          (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_0)        /*!< PLLI2S division factor for PLLI2SDIVQ output by 26 */
+#define LL_RCC_PLLI2SDIVQ_DIV_27          (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_1)        /*!< PLLI2S division factor for PLLI2SDIVQ output by 27 */
+#define LL_RCC_PLLI2SDIVQ_DIV_28          (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_1 | RCC_DCKCFGR_PLLI2SDIVQ_0)        /*!< PLLI2S division factor for PLLI2SDIVQ output by 28 */
+#define LL_RCC_PLLI2SDIVQ_DIV_29          (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_2)        /*!< PLLI2S division factor for PLLI2SDIVQ output by 29 */
+#define LL_RCC_PLLI2SDIVQ_DIV_30          (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_0)        /*!< PLLI2S division factor for PLLI2SDIVQ output by 30 */
+#define LL_RCC_PLLI2SDIVQ_DIV_31          (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_1)        /*!< PLLI2S division factor for PLLI2SDIVQ output by 31 */
+#define LL_RCC_PLLI2SDIVQ_DIV_32          (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_1 | RCC_DCKCFGR_PLLI2SDIVQ_0)        /*!< PLLI2S division factor for PLLI2SDIVQ output by 32 */
+/**
+  * @}
+  */
+#endif /* RCC_DCKCFGR_PLLI2SDIVQ */
+
+#if defined(RCC_DCKCFGR_PLLI2SDIVR)
+/** @defgroup RCC_LL_EC_PLLI2SDIVR  PLLI2SDIVR division factor (PLLI2SDIVR)
+  * @{
+  */
+#define LL_RCC_PLLI2SDIVR_DIV_1           (RCC_DCKCFGR_PLLI2SDIVR_0)        /*!< PLLI2S division factor for PLLI2SDIVR output by 1 */
+#define LL_RCC_PLLI2SDIVR_DIV_2           (RCC_DCKCFGR_PLLI2SDIVR_1)        /*!< PLLI2S division factor for PLLI2SDIVR output by 2 */
+#define LL_RCC_PLLI2SDIVR_DIV_3           (RCC_DCKCFGR_PLLI2SDIVR_1 | RCC_DCKCFGR_PLLI2SDIVR_0)        /*!< PLLI2S division factor for PLLI2SDIVR output by 3 */
+#define LL_RCC_PLLI2SDIVR_DIV_4           (RCC_DCKCFGR_PLLI2SDIVR_2)        /*!< PLLI2S division factor for PLLI2SDIVR output by 4 */
+#define LL_RCC_PLLI2SDIVR_DIV_5           (RCC_DCKCFGR_PLLI2SDIVR_2 | RCC_DCKCFGR_PLLI2SDIVR_0)        /*!< PLLI2S division factor for PLLI2SDIVR output by 5 */
+#define LL_RCC_PLLI2SDIVR_DIV_6           (RCC_DCKCFGR_PLLI2SDIVR_2 | RCC_DCKCFGR_PLLI2SDIVR_1)        /*!< PLLI2S division factor for PLLI2SDIVR output by 6 */
+#define LL_RCC_PLLI2SDIVR_DIV_7           (RCC_DCKCFGR_PLLI2SDIVR_2 | RCC_DCKCFGR_PLLI2SDIVR_1 | RCC_DCKCFGR_PLLI2SDIVR_0)        /*!< PLLI2S division factor for PLLI2SDIVR output by 7 */
+#define LL_RCC_PLLI2SDIVR_DIV_8           (RCC_DCKCFGR_PLLI2SDIVR_3)        /*!< PLLI2S division factor for PLLI2SDIVR output by 8 */
+#define LL_RCC_PLLI2SDIVR_DIV_9           (RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_0)        /*!< PLLI2S division factor for PLLI2SDIVR output by 9 */
+#define LL_RCC_PLLI2SDIVR_DIV_10          (RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_1)        /*!< PLLI2S division factor for PLLI2SDIVR output by 10 */
+#define LL_RCC_PLLI2SDIVR_DIV_11          (RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_1 | RCC_DCKCFGR_PLLI2SDIVR_0)        /*!< PLLI2S division factor for PLLI2SDIVR output by 11 */
+#define LL_RCC_PLLI2SDIVR_DIV_12          (RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_2)        /*!< PLLI2S division factor for PLLI2SDIVR output by 12 */
+#define LL_RCC_PLLI2SDIVR_DIV_13          (RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_2 | RCC_DCKCFGR_PLLI2SDIVR_0)        /*!< PLLI2S division factor for PLLI2SDIVR output by 13 */
+#define LL_RCC_PLLI2SDIVR_DIV_14          (RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_2 | RCC_DCKCFGR_PLLI2SDIVR_1)        /*!< PLLI2S division factor for PLLI2SDIVR output by 14 */
+#define LL_RCC_PLLI2SDIVR_DIV_15          (RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_2 | RCC_DCKCFGR_PLLI2SDIVR_1 | RCC_DCKCFGR_PLLI2SDIVR_0)        /*!< PLLI2S division factor for PLLI2SDIVR output by 15 */
+#define LL_RCC_PLLI2SDIVR_DIV_16          (RCC_DCKCFGR_PLLI2SDIVR_4)             /*!< PLLI2S division factor for PLLI2SDIVR output by 16 */
+#define LL_RCC_PLLI2SDIVR_DIV_17          (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_0)        /*!< PLLI2S division factor for PLLI2SDIVR output by 17 */
+#define LL_RCC_PLLI2SDIVR_DIV_18          (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_1)        /*!< PLLI2S division factor for PLLI2SDIVR output by 18 */
+#define LL_RCC_PLLI2SDIVR_DIV_19          (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_1 | RCC_DCKCFGR_PLLI2SDIVR_0)        /*!< PLLI2S division factor for PLLI2SDIVR output by 19 */
+#define LL_RCC_PLLI2SDIVR_DIV_20          (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_2)        /*!< PLLI2S division factor for PLLI2SDIVR output by 20 */
+#define LL_RCC_PLLI2SDIVR_DIV_21          (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_2 | RCC_DCKCFGR_PLLI2SDIVR_0)        /*!< PLLI2S division factor for PLLI2SDIVR output by 21 */
+#define LL_RCC_PLLI2SDIVR_DIV_22          (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_2 | RCC_DCKCFGR_PLLI2SDIVR_1)        /*!< PLLI2S division factor for PLLI2SDIVR output by 22 */
+#define LL_RCC_PLLI2SDIVR_DIV_23          (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_2 | RCC_DCKCFGR_PLLI2SDIVR_1 | RCC_DCKCFGR_PLLI2SDIVR_0)        /*!< PLLI2S division factor for PLLI2SDIVR output by 23 */
+#define LL_RCC_PLLI2SDIVR_DIV_24          (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_3)        /*!< PLLI2S division factor for PLLI2SDIVR output by 24 */
+#define LL_RCC_PLLI2SDIVR_DIV_25          (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_0)        /*!< PLLI2S division factor for PLLI2SDIVR output by 25 */
+#define LL_RCC_PLLI2SDIVR_DIV_26          (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_1)        /*!< PLLI2S division factor for PLLI2SDIVR output by 26 */
+#define LL_RCC_PLLI2SDIVR_DIV_27          (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_1 | RCC_DCKCFGR_PLLI2SDIVR_0)        /*!< PLLI2S division factor for PLLI2SDIVR output by 27 */
+#define LL_RCC_PLLI2SDIVR_DIV_28          (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_2)        /*!< PLLI2S division factor for PLLI2SDIVR output by 28 */
+#define LL_RCC_PLLI2SDIVR_DIV_29          (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_2 | RCC_DCKCFGR_PLLI2SDIVR_0)        /*!< PLLI2S division factor for PLLI2SDIVR output by 29 */
+#define LL_RCC_PLLI2SDIVR_DIV_30          (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_2 | RCC_DCKCFGR_PLLI2SDIVR_1)        /*!< PLLI2S division factor for PLLI2SDIVR output by 30 */
+#define LL_RCC_PLLI2SDIVR_DIV_31          (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_2 | RCC_DCKCFGR_PLLI2SDIVR_1 | RCC_DCKCFGR_PLLI2SDIVR_0)        /*!< PLLI2S division factor for PLLI2SDIVR output by 31 */
+/**
+  * @}
+  */
+#endif /* RCC_DCKCFGR_PLLI2SDIVR */
+
+/** @defgroup RCC_LL_EC_PLLI2SR  PLLI2SR division factor (PLLI2SR)
+  * @{
+  */
+#define LL_RCC_PLLI2SR_DIV_2              RCC_PLLI2SCFGR_PLLI2SR_1                                     /*!< PLLI2S division factor for PLLI2SR output by 2 */
+#define LL_RCC_PLLI2SR_DIV_3              (RCC_PLLI2SCFGR_PLLI2SR_1 | RCC_PLLI2SCFGR_PLLI2SR_0)        /*!< PLLI2S division factor for PLLI2SR output by 3 */
+#define LL_RCC_PLLI2SR_DIV_4              RCC_PLLI2SCFGR_PLLI2SR_2                                     /*!< PLLI2S division factor for PLLI2SR output by 4 */
+#define LL_RCC_PLLI2SR_DIV_5              (RCC_PLLI2SCFGR_PLLI2SR_2 | RCC_PLLI2SCFGR_PLLI2SR_0)        /*!< PLLI2S division factor for PLLI2SR output by 5 */
+#define LL_RCC_PLLI2SR_DIV_6              (RCC_PLLI2SCFGR_PLLI2SR_2 | RCC_PLLI2SCFGR_PLLI2SR_1)        /*!< PLLI2S division factor for PLLI2SR output by 6 */
+#define LL_RCC_PLLI2SR_DIV_7              (RCC_PLLI2SCFGR_PLLI2SR_2 | RCC_PLLI2SCFGR_PLLI2SR_1 | RCC_PLLI2SCFGR_PLLI2SR_0)        /*!< PLLI2S division factor for PLLI2SR output by 7 */
+/**
+  * @}
+  */
+
+#if defined(RCC_PLLI2SCFGR_PLLI2SP)
+/** @defgroup RCC_LL_EC_PLLI2SP  PLLI2SP division factor (PLLI2SP)
+  * @{
+  */
+#define LL_RCC_PLLI2SP_DIV_2              0x00000000U            /*!< PLLI2S division factor for PLLI2SP output by 2 */
+#define LL_RCC_PLLI2SP_DIV_4              RCC_PLLI2SCFGR_PLLI2SP_0        /*!< PLLI2S division factor for PLLI2SP output by 4 */
+#define LL_RCC_PLLI2SP_DIV_6              RCC_PLLI2SCFGR_PLLI2SP_1        /*!< PLLI2S division factor for PLLI2SP output by 6 */
+#define LL_RCC_PLLI2SP_DIV_8              (RCC_PLLI2SCFGR_PLLI2SP_1 | RCC_PLLI2SCFGR_PLLI2SP_0)        /*!< PLLI2S division factor for PLLI2SP output by 8 */
+/**
+  * @}
+  */
+#endif /* RCC_PLLI2SCFGR_PLLI2SP */
+#endif /* RCC_PLLI2S_SUPPORT */
+
+#if defined(RCC_PLLSAI_SUPPORT)
+/** @defgroup RCC_LL_EC_PLLSAIM  PLLSAIM division factor (PLLSAIM or PLLM)
+  * @{
+  */
+#if defined(RCC_PLLSAICFGR_PLLSAIM)
+#define LL_RCC_PLLSAIM_DIV_2             (RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 2 */
+#define LL_RCC_PLLSAIM_DIV_3             (RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 3 */
+#define LL_RCC_PLLSAIM_DIV_4             (RCC_PLLSAICFGR_PLLSAIM_2) /*!< PLLSAI division factor for PLLSAIM output by 4 */
+#define LL_RCC_PLLSAIM_DIV_5             (RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 5 */
+#define LL_RCC_PLLSAIM_DIV_6             (RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 6 */
+#define LL_RCC_PLLSAIM_DIV_7             (RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 7 */
+#define LL_RCC_PLLSAIM_DIV_8             (RCC_PLLSAICFGR_PLLSAIM_3) /*!< PLLSAI division factor for PLLSAIM output by 8 */
+#define LL_RCC_PLLSAIM_DIV_9             (RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 9 */
+#define LL_RCC_PLLSAIM_DIV_10            (RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 10 */
+#define LL_RCC_PLLSAIM_DIV_11            (RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 11 */
+#define LL_RCC_PLLSAIM_DIV_12            (RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2) /*!< PLLSAI division factor for PLLSAIM output by 12 */
+#define LL_RCC_PLLSAIM_DIV_13            (RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 13 */
+#define LL_RCC_PLLSAIM_DIV_14            (RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 14 */
+#define LL_RCC_PLLSAIM_DIV_15            (RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 15 */
+#define LL_RCC_PLLSAIM_DIV_16            (RCC_PLLSAICFGR_PLLSAIM_4) /*!< PLLSAI division factor for PLLSAIM output by 16 */
+#define LL_RCC_PLLSAIM_DIV_17            (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 17 */
+#define LL_RCC_PLLSAIM_DIV_18            (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 18 */
+#define LL_RCC_PLLSAIM_DIV_19            (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 19 */
+#define LL_RCC_PLLSAIM_DIV_20            (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_2) /*!< PLLSAI division factor for PLLSAIM output by 20 */
+#define LL_RCC_PLLSAIM_DIV_21            (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 21 */
+#define LL_RCC_PLLSAIM_DIV_22            (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 22 */
+#define LL_RCC_PLLSAIM_DIV_23            (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 23 */
+#define LL_RCC_PLLSAIM_DIV_24            (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3) /*!< PLLSAI division factor for PLLSAIM output by 24 */
+#define LL_RCC_PLLSAIM_DIV_25            (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 25 */
+#define LL_RCC_PLLSAIM_DIV_26            (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 26 */
+#define LL_RCC_PLLSAIM_DIV_27            (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 27 */
+#define LL_RCC_PLLSAIM_DIV_28            (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2) /*!< PLLSAI division factor for PLLSAIM output by 28 */
+#define LL_RCC_PLLSAIM_DIV_29            (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 29 */
+#define LL_RCC_PLLSAIM_DIV_30            (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 30 */
+#define LL_RCC_PLLSAIM_DIV_31            (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 31 */
+#define LL_RCC_PLLSAIM_DIV_32            (RCC_PLLSAICFGR_PLLSAIM_5) /*!< PLLSAI division factor for PLLSAIM output by 32 */
+#define LL_RCC_PLLSAIM_DIV_33            (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 33 */
+#define LL_RCC_PLLSAIM_DIV_34            (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 34 */
+#define LL_RCC_PLLSAIM_DIV_35            (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 35 */
+#define LL_RCC_PLLSAIM_DIV_36            (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_2) /*!< PLLSAI division factor for PLLSAIM output by 36 */
+#define LL_RCC_PLLSAIM_DIV_37            (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 37 */
+#define LL_RCC_PLLSAIM_DIV_38            (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 38 */
+#define LL_RCC_PLLSAIM_DIV_39            (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 39 */
+#define LL_RCC_PLLSAIM_DIV_40            (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_3) /*!< PLLSAI division factor for PLLSAIM output by 40 */
+#define LL_RCC_PLLSAIM_DIV_41            (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 41 */
+#define LL_RCC_PLLSAIM_DIV_42            (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 42 */
+#define LL_RCC_PLLSAIM_DIV_43            (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 43 */
+#define LL_RCC_PLLSAIM_DIV_44            (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2) /*!< PLLSAI division factor for PLLSAIM output by 44 */
+#define LL_RCC_PLLSAIM_DIV_45            (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 45 */
+#define LL_RCC_PLLSAIM_DIV_46            (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 46 */
+#define LL_RCC_PLLSAIM_DIV_47            (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 47 */
+#define LL_RCC_PLLSAIM_DIV_48            (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4) /*!< PLLSAI division factor for PLLSAIM output by 48 */
+#define LL_RCC_PLLSAIM_DIV_49            (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 49 */
+#define LL_RCC_PLLSAIM_DIV_50            (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 50 */
+#define LL_RCC_PLLSAIM_DIV_51            (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 51 */
+#define LL_RCC_PLLSAIM_DIV_52            (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_2) /*!< PLLSAI division factor for PLLSAIM output by 52 */
+#define LL_RCC_PLLSAIM_DIV_53            (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 53 */
+#define LL_RCC_PLLSAIM_DIV_54            (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 54 */
+#define LL_RCC_PLLSAIM_DIV_55            (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 55 */
+#define LL_RCC_PLLSAIM_DIV_56            (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3) /*!< PLLSAI division factor for PLLSAIM output by 56 */
+#define LL_RCC_PLLSAIM_DIV_57            (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 57 */
+#define LL_RCC_PLLSAIM_DIV_58            (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 58 */
+#define LL_RCC_PLLSAIM_DIV_59            (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 59 */
+#define LL_RCC_PLLSAIM_DIV_60            (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2) /*!< PLLSAI division factor for PLLSAIM output by 60 */
+#define LL_RCC_PLLSAIM_DIV_61            (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 61 */
+#define LL_RCC_PLLSAIM_DIV_62            (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 62 */
+#define LL_RCC_PLLSAIM_DIV_63            (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 63 */
+#else
+#define LL_RCC_PLLSAIM_DIV_2              LL_RCC_PLLM_DIV_2      /*!< PLLSAI division factor for PLLSAIM output by 2 */
+#define LL_RCC_PLLSAIM_DIV_3              LL_RCC_PLLM_DIV_3      /*!< PLLSAI division factor for PLLSAIM output by 3 */
+#define LL_RCC_PLLSAIM_DIV_4              LL_RCC_PLLM_DIV_4      /*!< PLLSAI division factor for PLLSAIM output by 4 */
+#define LL_RCC_PLLSAIM_DIV_5              LL_RCC_PLLM_DIV_5      /*!< PLLSAI division factor for PLLSAIM output by 5 */
+#define LL_RCC_PLLSAIM_DIV_6              LL_RCC_PLLM_DIV_6      /*!< PLLSAI division factor for PLLSAIM output by 6 */
+#define LL_RCC_PLLSAIM_DIV_7              LL_RCC_PLLM_DIV_7      /*!< PLLSAI division factor for PLLSAIM output by 7 */
+#define LL_RCC_PLLSAIM_DIV_8              LL_RCC_PLLM_DIV_8      /*!< PLLSAI division factor for PLLSAIM output by 8 */
+#define LL_RCC_PLLSAIM_DIV_9              LL_RCC_PLLM_DIV_9      /*!< PLLSAI division factor for PLLSAIM output by 9 */
+#define LL_RCC_PLLSAIM_DIV_10             LL_RCC_PLLM_DIV_10     /*!< PLLSAI division factor for PLLSAIM output by 10 */
+#define LL_RCC_PLLSAIM_DIV_11             LL_RCC_PLLM_DIV_11     /*!< PLLSAI division factor for PLLSAIM output by 11 */
+#define LL_RCC_PLLSAIM_DIV_12             LL_RCC_PLLM_DIV_12     /*!< PLLSAI division factor for PLLSAIM output by 12 */
+#define LL_RCC_PLLSAIM_DIV_13             LL_RCC_PLLM_DIV_13     /*!< PLLSAI division factor for PLLSAIM output by 13 */
+#define LL_RCC_PLLSAIM_DIV_14             LL_RCC_PLLM_DIV_14     /*!< PLLSAI division factor for PLLSAIM output by 14 */
+#define LL_RCC_PLLSAIM_DIV_15             LL_RCC_PLLM_DIV_15     /*!< PLLSAI division factor for PLLSAIM output by 15 */
+#define LL_RCC_PLLSAIM_DIV_16             LL_RCC_PLLM_DIV_16     /*!< PLLSAI division factor for PLLSAIM output by 16 */
+#define LL_RCC_PLLSAIM_DIV_17             LL_RCC_PLLM_DIV_17     /*!< PLLSAI division factor for PLLSAIM output by 17 */
+#define LL_RCC_PLLSAIM_DIV_18             LL_RCC_PLLM_DIV_18     /*!< PLLSAI division factor for PLLSAIM output by 18 */
+#define LL_RCC_PLLSAIM_DIV_19             LL_RCC_PLLM_DIV_19     /*!< PLLSAI division factor for PLLSAIM output by 19 */
+#define LL_RCC_PLLSAIM_DIV_20             LL_RCC_PLLM_DIV_20     /*!< PLLSAI division factor for PLLSAIM output by 20 */
+#define LL_RCC_PLLSAIM_DIV_21             LL_RCC_PLLM_DIV_21     /*!< PLLSAI division factor for PLLSAIM output by 21 */
+#define LL_RCC_PLLSAIM_DIV_22             LL_RCC_PLLM_DIV_22     /*!< PLLSAI division factor for PLLSAIM output by 22 */
+#define LL_RCC_PLLSAIM_DIV_23             LL_RCC_PLLM_DIV_23     /*!< PLLSAI division factor for PLLSAIM output by 23 */
+#define LL_RCC_PLLSAIM_DIV_24             LL_RCC_PLLM_DIV_24     /*!< PLLSAI division factor for PLLSAIM output by 24 */
+#define LL_RCC_PLLSAIM_DIV_25             LL_RCC_PLLM_DIV_25     /*!< PLLSAI division factor for PLLSAIM output by 25 */
+#define LL_RCC_PLLSAIM_DIV_26             LL_RCC_PLLM_DIV_26     /*!< PLLSAI division factor for PLLSAIM output by 26 */
+#define LL_RCC_PLLSAIM_DIV_27             LL_RCC_PLLM_DIV_27     /*!< PLLSAI division factor for PLLSAIM output by 27 */
+#define LL_RCC_PLLSAIM_DIV_28             LL_RCC_PLLM_DIV_28     /*!< PLLSAI division factor for PLLSAIM output by 28 */
+#define LL_RCC_PLLSAIM_DIV_29             LL_RCC_PLLM_DIV_29     /*!< PLLSAI division factor for PLLSAIM output by 29 */
+#define LL_RCC_PLLSAIM_DIV_30             LL_RCC_PLLM_DIV_30     /*!< PLLSAI division factor for PLLSAIM output by 30 */
+#define LL_RCC_PLLSAIM_DIV_31             LL_RCC_PLLM_DIV_31     /*!< PLLSAI division factor for PLLSAIM output by 31 */
+#define LL_RCC_PLLSAIM_DIV_32             LL_RCC_PLLM_DIV_32     /*!< PLLSAI division factor for PLLSAIM output by 32 */
+#define LL_RCC_PLLSAIM_DIV_33             LL_RCC_PLLM_DIV_33     /*!< PLLSAI division factor for PLLSAIM output by 33 */
+#define LL_RCC_PLLSAIM_DIV_34             LL_RCC_PLLM_DIV_34     /*!< PLLSAI division factor for PLLSAIM output by 34 */
+#define LL_RCC_PLLSAIM_DIV_35             LL_RCC_PLLM_DIV_35     /*!< PLLSAI division factor for PLLSAIM output by 35 */
+#define LL_RCC_PLLSAIM_DIV_36             LL_RCC_PLLM_DIV_36     /*!< PLLSAI division factor for PLLSAIM output by 36 */
+#define LL_RCC_PLLSAIM_DIV_37             LL_RCC_PLLM_DIV_37     /*!< PLLSAI division factor for PLLSAIM output by 37 */
+#define LL_RCC_PLLSAIM_DIV_38             LL_RCC_PLLM_DIV_38     /*!< PLLSAI division factor for PLLSAIM output by 38 */
+#define LL_RCC_PLLSAIM_DIV_39             LL_RCC_PLLM_DIV_39     /*!< PLLSAI division factor for PLLSAIM output by 39 */
+#define LL_RCC_PLLSAIM_DIV_40             LL_RCC_PLLM_DIV_40     /*!< PLLSAI division factor for PLLSAIM output by 40 */
+#define LL_RCC_PLLSAIM_DIV_41             LL_RCC_PLLM_DIV_41     /*!< PLLSAI division factor for PLLSAIM output by 41 */
+#define LL_RCC_PLLSAIM_DIV_42             LL_RCC_PLLM_DIV_42     /*!< PLLSAI division factor for PLLSAIM output by 42 */
+#define LL_RCC_PLLSAIM_DIV_43             LL_RCC_PLLM_DIV_43     /*!< PLLSAI division factor for PLLSAIM output by 43 */
+#define LL_RCC_PLLSAIM_DIV_44             LL_RCC_PLLM_DIV_44     /*!< PLLSAI division factor for PLLSAIM output by 44 */
+#define LL_RCC_PLLSAIM_DIV_45             LL_RCC_PLLM_DIV_45     /*!< PLLSAI division factor for PLLSAIM output by 45 */
+#define LL_RCC_PLLSAIM_DIV_46             LL_RCC_PLLM_DIV_46     /*!< PLLSAI division factor for PLLSAIM output by 46 */
+#define LL_RCC_PLLSAIM_DIV_47             LL_RCC_PLLM_DIV_47     /*!< PLLSAI division factor for PLLSAIM output by 47 */
+#define LL_RCC_PLLSAIM_DIV_48             LL_RCC_PLLM_DIV_48     /*!< PLLSAI division factor for PLLSAIM output by 48 */
+#define LL_RCC_PLLSAIM_DIV_49             LL_RCC_PLLM_DIV_49     /*!< PLLSAI division factor for PLLSAIM output by 49 */
+#define LL_RCC_PLLSAIM_DIV_50             LL_RCC_PLLM_DIV_50     /*!< PLLSAI division factor for PLLSAIM output by 50 */
+#define LL_RCC_PLLSAIM_DIV_51             LL_RCC_PLLM_DIV_51     /*!< PLLSAI division factor for PLLSAIM output by 51 */
+#define LL_RCC_PLLSAIM_DIV_52             LL_RCC_PLLM_DIV_52     /*!< PLLSAI division factor for PLLSAIM output by 52 */
+#define LL_RCC_PLLSAIM_DIV_53             LL_RCC_PLLM_DIV_53     /*!< PLLSAI division factor for PLLSAIM output by 53 */
+#define LL_RCC_PLLSAIM_DIV_54             LL_RCC_PLLM_DIV_54     /*!< PLLSAI division factor for PLLSAIM output by 54 */
+#define LL_RCC_PLLSAIM_DIV_55             LL_RCC_PLLM_DIV_55     /*!< PLLSAI division factor for PLLSAIM output by 55 */
+#define LL_RCC_PLLSAIM_DIV_56             LL_RCC_PLLM_DIV_56     /*!< PLLSAI division factor for PLLSAIM output by 56 */
+#define LL_RCC_PLLSAIM_DIV_57             LL_RCC_PLLM_DIV_57     /*!< PLLSAI division factor for PLLSAIM output by 57 */
+#define LL_RCC_PLLSAIM_DIV_58             LL_RCC_PLLM_DIV_58     /*!< PLLSAI division factor for PLLSAIM output by 58 */
+#define LL_RCC_PLLSAIM_DIV_59             LL_RCC_PLLM_DIV_59     /*!< PLLSAI division factor for PLLSAIM output by 59 */
+#define LL_RCC_PLLSAIM_DIV_60             LL_RCC_PLLM_DIV_60     /*!< PLLSAI division factor for PLLSAIM output by 60 */
+#define LL_RCC_PLLSAIM_DIV_61             LL_RCC_PLLM_DIV_61     /*!< PLLSAI division factor for PLLSAIM output by 61 */
+#define LL_RCC_PLLSAIM_DIV_62             LL_RCC_PLLM_DIV_62     /*!< PLLSAI division factor for PLLSAIM output by 62 */
+#define LL_RCC_PLLSAIM_DIV_63             LL_RCC_PLLM_DIV_63     /*!< PLLSAI division factor for PLLSAIM output by 63 */
+#endif /* RCC_PLLSAICFGR_PLLSAIM */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_PLLSAIQ  PLLSAIQ division factor (PLLSAIQ)
+  * @{
+  */
+#define LL_RCC_PLLSAIQ_DIV_2              RCC_PLLSAICFGR_PLLSAIQ_1        /*!< PLLSAI division factor for PLLSAIQ output by 2 */
+#define LL_RCC_PLLSAIQ_DIV_3              (RCC_PLLSAICFGR_PLLSAIQ_1 | RCC_PLLSAICFGR_PLLSAIQ_0)        /*!< PLLSAI division factor for PLLSAIQ output by 3 */
+#define LL_RCC_PLLSAIQ_DIV_4              RCC_PLLSAICFGR_PLLSAIQ_2        /*!< PLLSAI division factor for PLLSAIQ output by 4 */
+#define LL_RCC_PLLSAIQ_DIV_5              (RCC_PLLSAICFGR_PLLSAIQ_2 | RCC_PLLSAICFGR_PLLSAIQ_0)        /*!< PLLSAI division factor for PLLSAIQ output by 5 */
+#define LL_RCC_PLLSAIQ_DIV_6              (RCC_PLLSAICFGR_PLLSAIQ_2 | RCC_PLLSAICFGR_PLLSAIQ_1)        /*!< PLLSAI division factor for PLLSAIQ output by 6 */
+#define LL_RCC_PLLSAIQ_DIV_7              (RCC_PLLSAICFGR_PLLSAIQ_2 | RCC_PLLSAICFGR_PLLSAIQ_1 | RCC_PLLSAICFGR_PLLSAIQ_0)        /*!< PLLSAI division factor for PLLSAIQ output by 7 */
+#define LL_RCC_PLLSAIQ_DIV_8              RCC_PLLSAICFGR_PLLSAIQ_3        /*!< PLLSAI division factor for PLLSAIQ output by 8 */
+#define LL_RCC_PLLSAIQ_DIV_9              (RCC_PLLSAICFGR_PLLSAIQ_3 | RCC_PLLSAICFGR_PLLSAIQ_0)        /*!< PLLSAI division factor for PLLSAIQ output by 9 */
+#define LL_RCC_PLLSAIQ_DIV_10             (RCC_PLLSAICFGR_PLLSAIQ_3 | RCC_PLLSAICFGR_PLLSAIQ_1)        /*!< PLLSAI division factor for PLLSAIQ output by 10 */
+#define LL_RCC_PLLSAIQ_DIV_11             (RCC_PLLSAICFGR_PLLSAIQ_3 | RCC_PLLSAICFGR_PLLSAIQ_1 | RCC_PLLSAICFGR_PLLSAIQ_0)        /*!< PLLSAI division factor for PLLSAIQ output by 11 */
+#define LL_RCC_PLLSAIQ_DIV_12             (RCC_PLLSAICFGR_PLLSAIQ_3 | RCC_PLLSAICFGR_PLLSAIQ_2)        /*!< PLLSAI division factor for PLLSAIQ output by 12 */
+#define LL_RCC_PLLSAIQ_DIV_13             (RCC_PLLSAICFGR_PLLSAIQ_3 | RCC_PLLSAICFGR_PLLSAIQ_2 | RCC_PLLSAICFGR_PLLSAIQ_0)        /*!< PLLSAI division factor for PLLSAIQ output by 13 */
+#define LL_RCC_PLLSAIQ_DIV_14             (RCC_PLLSAICFGR_PLLSAIQ_3 | RCC_PLLSAICFGR_PLLSAIQ_2 | RCC_PLLSAICFGR_PLLSAIQ_1)        /*!< PLLSAI division factor for PLLSAIQ output by 14 */
+#define LL_RCC_PLLSAIQ_DIV_15             (RCC_PLLSAICFGR_PLLSAIQ_3 | RCC_PLLSAICFGR_PLLSAIQ_2 | RCC_PLLSAICFGR_PLLSAIQ_1 | RCC_PLLSAICFGR_PLLSAIQ_0)        /*!< PLLSAI division factor for PLLSAIQ output by 15 */
+/**
+  * @}
+  */
+
+#if defined(RCC_DCKCFGR_PLLSAIDIVQ)
+/** @defgroup RCC_LL_EC_PLLSAIDIVQ  PLLSAIDIVQ division factor (PLLSAIDIVQ)
+  * @{
+  */
+#define LL_RCC_PLLSAIDIVQ_DIV_1           0x00000000U               /*!< PLLSAI division factor for PLLSAIDIVQ output by 1 */
+#define LL_RCC_PLLSAIDIVQ_DIV_2           RCC_DCKCFGR_PLLSAIDIVQ_0          /*!< PLLSAI division factor for PLLSAIDIVQ output by 2 */
+#define LL_RCC_PLLSAIDIVQ_DIV_3           RCC_DCKCFGR_PLLSAIDIVQ_1          /*!< PLLSAI division factor for PLLSAIDIVQ output by 3 */
+#define LL_RCC_PLLSAIDIVQ_DIV_4           (RCC_DCKCFGR_PLLSAIDIVQ_1 | RCC_DCKCFGR_PLLSAIDIVQ_0)        /*!< PLLSAI division factor for PLLSAIDIVQ output by 4 */
+#define LL_RCC_PLLSAIDIVQ_DIV_5           RCC_DCKCFGR_PLLSAIDIVQ_2          /*!< PLLSAI division factor for PLLSAIDIVQ output by 5 */
+#define LL_RCC_PLLSAIDIVQ_DIV_6           (RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_0)        /*!< PLLSAI division factor for PLLSAIDIVQ output by 6 */
+#define LL_RCC_PLLSAIDIVQ_DIV_7           (RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_1)        /*!< PLLSAI division factor for PLLSAIDIVQ output by 7 */
+#define LL_RCC_PLLSAIDIVQ_DIV_8           (RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_1 | RCC_DCKCFGR_PLLSAIDIVQ_0)        /*!< PLLSAI division factor for PLLSAIDIVQ output by 8 */
+#define LL_RCC_PLLSAIDIVQ_DIV_9           RCC_DCKCFGR_PLLSAIDIVQ_3          /*!< PLLSAI division factor for PLLSAIDIVQ output by 9 */
+#define LL_RCC_PLLSAIDIVQ_DIV_10          (RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_0)        /*!< PLLSAI division factor for PLLSAIDIVQ output by 10 */
+#define LL_RCC_PLLSAIDIVQ_DIV_11          (RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_1)        /*!< PLLSAI division factor for PLLSAIDIVQ output by 11 */
+#define LL_RCC_PLLSAIDIVQ_DIV_12          (RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_1 | RCC_DCKCFGR_PLLSAIDIVQ_0)        /*!< PLLSAI division factor for PLLSAIDIVQ output by 12 */
+#define LL_RCC_PLLSAIDIVQ_DIV_13          (RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_2)        /*!< PLLSAI division factor for PLLSAIDIVQ output by 13 */
+#define LL_RCC_PLLSAIDIVQ_DIV_14          (RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_0)        /*!< PLLSAI division factor for PLLSAIDIVQ output by 14 */
+#define LL_RCC_PLLSAIDIVQ_DIV_15          (RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_1)        /*!< PLLSAI division factor for PLLSAIDIVQ output by 15 */
+#define LL_RCC_PLLSAIDIVQ_DIV_16          (RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_1 | RCC_DCKCFGR_PLLSAIDIVQ_0)        /*!< PLLSAI division factor for PLLSAIDIVQ output by 16 */
+#define LL_RCC_PLLSAIDIVQ_DIV_17          RCC_DCKCFGR_PLLSAIDIVQ_4         /*!< PLLSAI division factor for PLLSAIDIVQ output by 17 */
+#define LL_RCC_PLLSAIDIVQ_DIV_18          (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_0)        /*!< PLLSAI division factor for PLLSAIDIVQ output by 18 */
+#define LL_RCC_PLLSAIDIVQ_DIV_19          (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_1)        /*!< PLLSAI division factor for PLLSAIDIVQ output by 19 */
+#define LL_RCC_PLLSAIDIVQ_DIV_20          (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_1 | RCC_DCKCFGR_PLLSAIDIVQ_0)        /*!< PLLSAI division factor for PLLSAIDIVQ output by 20 */
+#define LL_RCC_PLLSAIDIVQ_DIV_21          (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_2)        /*!< PLLSAI division factor for PLLSAIDIVQ output by 21 */
+#define LL_RCC_PLLSAIDIVQ_DIV_22          (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_0)        /*!< PLLSAI division factor for PLLSAIDIVQ output by 22 */
+#define LL_RCC_PLLSAIDIVQ_DIV_23          (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_1)        /*!< PLLSAI division factor for PLLSAIDIVQ output by 23 */
+#define LL_RCC_PLLSAIDIVQ_DIV_24          (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_1 | RCC_DCKCFGR_PLLSAIDIVQ_0)        /*!< PLLSAI division factor for PLLSAIDIVQ output by 24 */
+#define LL_RCC_PLLSAIDIVQ_DIV_25          (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_3)        /*!< PLLSAI division factor for PLLSAIDIVQ output by 25 */
+#define LL_RCC_PLLSAIDIVQ_DIV_26          (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_0)        /*!< PLLSAI division factor for PLLSAIDIVQ output by 26 */
+#define LL_RCC_PLLSAIDIVQ_DIV_27          (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_1)        /*!< PLLSAI division factor for PLLSAIDIVQ output by 27 */
+#define LL_RCC_PLLSAIDIVQ_DIV_28          (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_1 | RCC_DCKCFGR_PLLSAIDIVQ_0)        /*!< PLLSAI division factor for PLLSAIDIVQ output by 28 */
+#define LL_RCC_PLLSAIDIVQ_DIV_29          (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_2)        /*!< PLLSAI division factor for PLLSAIDIVQ output by 29 */
+#define LL_RCC_PLLSAIDIVQ_DIV_30          (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_0)        /*!< PLLSAI division factor for PLLSAIDIVQ output by 30 */
+#define LL_RCC_PLLSAIDIVQ_DIV_31          (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_1)        /*!< PLLSAI division factor for PLLSAIDIVQ output by 31 */
+#define LL_RCC_PLLSAIDIVQ_DIV_32          (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_1 | RCC_DCKCFGR_PLLSAIDIVQ_0)        /*!< PLLSAI division factor for PLLSAIDIVQ output by 32 */
+/**
+  * @}
+  */
+#endif /* RCC_DCKCFGR_PLLSAIDIVQ */
+
+#if defined(RCC_PLLSAICFGR_PLLSAIR)
+/** @defgroup RCC_LL_EC_PLLSAIR  PLLSAIR division factor (PLLSAIR)
+  * @{
+  */
+#define LL_RCC_PLLSAIR_DIV_2              RCC_PLLSAICFGR_PLLSAIR_1                                     /*!< PLLSAI division factor for PLLSAIR output by 2 */
+#define LL_RCC_PLLSAIR_DIV_3              (RCC_PLLSAICFGR_PLLSAIR_1 | RCC_PLLSAICFGR_PLLSAIR_0)        /*!< PLLSAI division factor for PLLSAIR output by 3 */
+#define LL_RCC_PLLSAIR_DIV_4              RCC_PLLSAICFGR_PLLSAIR_2                                     /*!< PLLSAI division factor for PLLSAIR output by 4 */
+#define LL_RCC_PLLSAIR_DIV_5              (RCC_PLLSAICFGR_PLLSAIR_2 | RCC_PLLSAICFGR_PLLSAIR_0)        /*!< PLLSAI division factor for PLLSAIR output by 5 */
+#define LL_RCC_PLLSAIR_DIV_6              (RCC_PLLSAICFGR_PLLSAIR_2 | RCC_PLLSAICFGR_PLLSAIR_1)        /*!< PLLSAI division factor for PLLSAIR output by 6 */
+#define LL_RCC_PLLSAIR_DIV_7              (RCC_PLLSAICFGR_PLLSAIR_2 | RCC_PLLSAICFGR_PLLSAIR_1 | RCC_PLLSAICFGR_PLLSAIR_0)        /*!< PLLSAI division factor for PLLSAIR output by 7 */
+/**
+  * @}
+  */
+#endif /* RCC_PLLSAICFGR_PLLSAIR */
+
+#if defined(RCC_DCKCFGR_PLLSAIDIVR)
+/** @defgroup RCC_LL_EC_PLLSAIDIVR  PLLSAIDIVR division factor (PLLSAIDIVR)
+  * @{
+  */
+#define LL_RCC_PLLSAIDIVR_DIV_2           0x00000000U             /*!< PLLSAI division factor for PLLSAIDIVR output by 2 */
+#define LL_RCC_PLLSAIDIVR_DIV_4           RCC_DCKCFGR_PLLSAIDIVR_0        /*!< PLLSAI division factor for PLLSAIDIVR output by 4 */
+#define LL_RCC_PLLSAIDIVR_DIV_8           RCC_DCKCFGR_PLLSAIDIVR_1        /*!< PLLSAI division factor for PLLSAIDIVR output by 8 */
+#define LL_RCC_PLLSAIDIVR_DIV_16          (RCC_DCKCFGR_PLLSAIDIVR_1 | RCC_DCKCFGR_PLLSAIDIVR_0)        /*!< PLLSAI division factor for PLLSAIDIVR output by 16 */
+/**
+  * @}
+  */
+#endif /* RCC_DCKCFGR_PLLSAIDIVR */
+
+#if defined(RCC_PLLSAICFGR_PLLSAIP)
+/** @defgroup RCC_LL_EC_PLLSAIP  PLLSAIP division factor (PLLSAIP)
+  * @{
+  */
+#define LL_RCC_PLLSAIP_DIV_2              0x00000000U               /*!< PLLSAI division factor for PLLSAIP output by 2 */
+#define LL_RCC_PLLSAIP_DIV_4              RCC_PLLSAICFGR_PLLSAIP_0        /*!< PLLSAI division factor for PLLSAIP output by 4 */
+#define LL_RCC_PLLSAIP_DIV_6              RCC_PLLSAICFGR_PLLSAIP_1        /*!< PLLSAI division factor for PLLSAIP output by 6 */
+#define LL_RCC_PLLSAIP_DIV_8              (RCC_PLLSAICFGR_PLLSAIP_1 | RCC_PLLSAICFGR_PLLSAIP_0)        /*!< PLLSAI division factor for PLLSAIP output by 8 */
+/**
+  * @}
+  */
+#endif /* RCC_PLLSAICFGR_PLLSAIP */
+#endif /* RCC_PLLSAI_SUPPORT */
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup RCC_LL_Exported_Macros RCC Exported Macros
+  * @{
+  */
+
+/** @defgroup RCC_LL_EM_WRITE_READ Common Write and read registers Macros
+  * @{
+  */
+
+/**
+  * @brief  Write a value in RCC register
+  * @param  __REG__ Register to be written
+  * @param  __VALUE__ Value to be written in the register
+  * @retval None
+  */
+#define LL_RCC_WriteReg(__REG__, __VALUE__) WRITE_REG(RCC->__REG__, (__VALUE__))
+
+/**
+  * @brief  Read a value in RCC register
+  * @param  __REG__ Register to be read
+  * @retval Register value
+  */
+#define LL_RCC_ReadReg(__REG__) READ_REG(RCC->__REG__)
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EM_CALC_FREQ Calculate frequencies
+  * @{
+  */
+
+/**
+  * @brief  Helper macro to calculate the PLLCLK frequency on system domain
+  * @note ex: @ref __LL_RCC_CALC_PLLCLK_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
+  *             @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetP ());
+  * @param  __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
+  * @param  __PLLM__ This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLM_DIV_2
+  *         @arg @ref LL_RCC_PLLM_DIV_3
+  *         @arg @ref LL_RCC_PLLM_DIV_4
+  *         @arg @ref LL_RCC_PLLM_DIV_5
+  *         @arg @ref LL_RCC_PLLM_DIV_6
+  *         @arg @ref LL_RCC_PLLM_DIV_7
+  *         @arg @ref LL_RCC_PLLM_DIV_8
+  *         @arg @ref LL_RCC_PLLM_DIV_9
+  *         @arg @ref LL_RCC_PLLM_DIV_10
+  *         @arg @ref LL_RCC_PLLM_DIV_11
+  *         @arg @ref LL_RCC_PLLM_DIV_12
+  *         @arg @ref LL_RCC_PLLM_DIV_13
+  *         @arg @ref LL_RCC_PLLM_DIV_14
+  *         @arg @ref LL_RCC_PLLM_DIV_15
+  *         @arg @ref LL_RCC_PLLM_DIV_16
+  *         @arg @ref LL_RCC_PLLM_DIV_17
+  *         @arg @ref LL_RCC_PLLM_DIV_18
+  *         @arg @ref LL_RCC_PLLM_DIV_19
+  *         @arg @ref LL_RCC_PLLM_DIV_20
+  *         @arg @ref LL_RCC_PLLM_DIV_21
+  *         @arg @ref LL_RCC_PLLM_DIV_22
+  *         @arg @ref LL_RCC_PLLM_DIV_23
+  *         @arg @ref LL_RCC_PLLM_DIV_24
+  *         @arg @ref LL_RCC_PLLM_DIV_25
+  *         @arg @ref LL_RCC_PLLM_DIV_26
+  *         @arg @ref LL_RCC_PLLM_DIV_27
+  *         @arg @ref LL_RCC_PLLM_DIV_28
+  *         @arg @ref LL_RCC_PLLM_DIV_29
+  *         @arg @ref LL_RCC_PLLM_DIV_30
+  *         @arg @ref LL_RCC_PLLM_DIV_31
+  *         @arg @ref LL_RCC_PLLM_DIV_32
+  *         @arg @ref LL_RCC_PLLM_DIV_33
+  *         @arg @ref LL_RCC_PLLM_DIV_34
+  *         @arg @ref LL_RCC_PLLM_DIV_35
+  *         @arg @ref LL_RCC_PLLM_DIV_36
+  *         @arg @ref LL_RCC_PLLM_DIV_37
+  *         @arg @ref LL_RCC_PLLM_DIV_38
+  *         @arg @ref LL_RCC_PLLM_DIV_39
+  *         @arg @ref LL_RCC_PLLM_DIV_40
+  *         @arg @ref LL_RCC_PLLM_DIV_41
+  *         @arg @ref LL_RCC_PLLM_DIV_42
+  *         @arg @ref LL_RCC_PLLM_DIV_43
+  *         @arg @ref LL_RCC_PLLM_DIV_44
+  *         @arg @ref LL_RCC_PLLM_DIV_45
+  *         @arg @ref LL_RCC_PLLM_DIV_46
+  *         @arg @ref LL_RCC_PLLM_DIV_47
+  *         @arg @ref LL_RCC_PLLM_DIV_48
+  *         @arg @ref LL_RCC_PLLM_DIV_49
+  *         @arg @ref LL_RCC_PLLM_DIV_50
+  *         @arg @ref LL_RCC_PLLM_DIV_51
+  *         @arg @ref LL_RCC_PLLM_DIV_52
+  *         @arg @ref LL_RCC_PLLM_DIV_53
+  *         @arg @ref LL_RCC_PLLM_DIV_54
+  *         @arg @ref LL_RCC_PLLM_DIV_55
+  *         @arg @ref LL_RCC_PLLM_DIV_56
+  *         @arg @ref LL_RCC_PLLM_DIV_57
+  *         @arg @ref LL_RCC_PLLM_DIV_58
+  *         @arg @ref LL_RCC_PLLM_DIV_59
+  *         @arg @ref LL_RCC_PLLM_DIV_60
+  *         @arg @ref LL_RCC_PLLM_DIV_61
+  *         @arg @ref LL_RCC_PLLM_DIV_62
+  *         @arg @ref LL_RCC_PLLM_DIV_63
+  * @param  __PLLN__ Between 50/192(*) and 432
+  *
+  *         (*) value not defined in all devices.
+  * @param  __PLLP__ This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLP_DIV_2
+  *         @arg @ref LL_RCC_PLLP_DIV_4
+  *         @arg @ref LL_RCC_PLLP_DIV_6
+  *         @arg @ref LL_RCC_PLLP_DIV_8
+  * @retval PLL clock frequency (in Hz)
+  */
+#define __LL_RCC_CALC_PLLCLK_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLP__) ((__INPUTFREQ__) / (__PLLM__) * (__PLLN__) / \
+                   ((((__PLLP__) >> RCC_PLLCFGR_PLLP_Pos ) + 1U) * 2U))
+
+#if defined(RCC_PLLR_SYSCLK_SUPPORT)
+/**
+  * @brief  Helper macro to calculate the PLLRCLK frequency on system domain
+  * @note ex: @ref __LL_RCC_CALC_PLLRCLK_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
+  *             @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetR ());
+  * @param  __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
+  * @param  __PLLM__ This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLM_DIV_2
+  *         @arg @ref LL_RCC_PLLM_DIV_3
+  *         @arg @ref LL_RCC_PLLM_DIV_4
+  *         @arg @ref LL_RCC_PLLM_DIV_5
+  *         @arg @ref LL_RCC_PLLM_DIV_6
+  *         @arg @ref LL_RCC_PLLM_DIV_7
+  *         @arg @ref LL_RCC_PLLM_DIV_8
+  *         @arg @ref LL_RCC_PLLM_DIV_9
+  *         @arg @ref LL_RCC_PLLM_DIV_10
+  *         @arg @ref LL_RCC_PLLM_DIV_11
+  *         @arg @ref LL_RCC_PLLM_DIV_12
+  *         @arg @ref LL_RCC_PLLM_DIV_13
+  *         @arg @ref LL_RCC_PLLM_DIV_14
+  *         @arg @ref LL_RCC_PLLM_DIV_15
+  *         @arg @ref LL_RCC_PLLM_DIV_16
+  *         @arg @ref LL_RCC_PLLM_DIV_17
+  *         @arg @ref LL_RCC_PLLM_DIV_18
+  *         @arg @ref LL_RCC_PLLM_DIV_19
+  *         @arg @ref LL_RCC_PLLM_DIV_20
+  *         @arg @ref LL_RCC_PLLM_DIV_21
+  *         @arg @ref LL_RCC_PLLM_DIV_22
+  *         @arg @ref LL_RCC_PLLM_DIV_23
+  *         @arg @ref LL_RCC_PLLM_DIV_24
+  *         @arg @ref LL_RCC_PLLM_DIV_25
+  *         @arg @ref LL_RCC_PLLM_DIV_26
+  *         @arg @ref LL_RCC_PLLM_DIV_27
+  *         @arg @ref LL_RCC_PLLM_DIV_28
+  *         @arg @ref LL_RCC_PLLM_DIV_29
+  *         @arg @ref LL_RCC_PLLM_DIV_30
+  *         @arg @ref LL_RCC_PLLM_DIV_31
+  *         @arg @ref LL_RCC_PLLM_DIV_32
+  *         @arg @ref LL_RCC_PLLM_DIV_33
+  *         @arg @ref LL_RCC_PLLM_DIV_34
+  *         @arg @ref LL_RCC_PLLM_DIV_35
+  *         @arg @ref LL_RCC_PLLM_DIV_36
+  *         @arg @ref LL_RCC_PLLM_DIV_37
+  *         @arg @ref LL_RCC_PLLM_DIV_38
+  *         @arg @ref LL_RCC_PLLM_DIV_39
+  *         @arg @ref LL_RCC_PLLM_DIV_40
+  *         @arg @ref LL_RCC_PLLM_DIV_41
+  *         @arg @ref LL_RCC_PLLM_DIV_42
+  *         @arg @ref LL_RCC_PLLM_DIV_43
+  *         @arg @ref LL_RCC_PLLM_DIV_44
+  *         @arg @ref LL_RCC_PLLM_DIV_45
+  *         @arg @ref LL_RCC_PLLM_DIV_46
+  *         @arg @ref LL_RCC_PLLM_DIV_47
+  *         @arg @ref LL_RCC_PLLM_DIV_48
+  *         @arg @ref LL_RCC_PLLM_DIV_49
+  *         @arg @ref LL_RCC_PLLM_DIV_50
+  *         @arg @ref LL_RCC_PLLM_DIV_51
+  *         @arg @ref LL_RCC_PLLM_DIV_52
+  *         @arg @ref LL_RCC_PLLM_DIV_53
+  *         @arg @ref LL_RCC_PLLM_DIV_54
+  *         @arg @ref LL_RCC_PLLM_DIV_55
+  *         @arg @ref LL_RCC_PLLM_DIV_56
+  *         @arg @ref LL_RCC_PLLM_DIV_57
+  *         @arg @ref LL_RCC_PLLM_DIV_58
+  *         @arg @ref LL_RCC_PLLM_DIV_59
+  *         @arg @ref LL_RCC_PLLM_DIV_60
+  *         @arg @ref LL_RCC_PLLM_DIV_61
+  *         @arg @ref LL_RCC_PLLM_DIV_62
+  *         @arg @ref LL_RCC_PLLM_DIV_63
+  * @param  __PLLN__ Between 50 and 432
+  * @param  __PLLR__ This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLR_DIV_2
+  *         @arg @ref LL_RCC_PLLR_DIV_3
+  *         @arg @ref LL_RCC_PLLR_DIV_4
+  *         @arg @ref LL_RCC_PLLR_DIV_5
+  *         @arg @ref LL_RCC_PLLR_DIV_6
+  *         @arg @ref LL_RCC_PLLR_DIV_7
+  * @retval PLL clock frequency (in Hz)
+  */
+#define __LL_RCC_CALC_PLLRCLK_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLR__) ((__INPUTFREQ__) / (__PLLM__) * (__PLLN__) / \
+                   ((__PLLR__) >> RCC_PLLCFGR_PLLR_Pos ))
+
+#endif /* RCC_PLLR_SYSCLK_SUPPORT */
+
+/**
+  * @brief  Helper macro to calculate the PLLCLK frequency used on 48M domain
+  * @note ex: @ref __LL_RCC_CALC_PLLCLK_48M_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
+  *             @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetQ ());
+  * @param  __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
+  * @param  __PLLM__ This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLM_DIV_2
+  *         @arg @ref LL_RCC_PLLM_DIV_3
+  *         @arg @ref LL_RCC_PLLM_DIV_4
+  *         @arg @ref LL_RCC_PLLM_DIV_5
+  *         @arg @ref LL_RCC_PLLM_DIV_6
+  *         @arg @ref LL_RCC_PLLM_DIV_7
+  *         @arg @ref LL_RCC_PLLM_DIV_8
+  *         @arg @ref LL_RCC_PLLM_DIV_9
+  *         @arg @ref LL_RCC_PLLM_DIV_10
+  *         @arg @ref LL_RCC_PLLM_DIV_11
+  *         @arg @ref LL_RCC_PLLM_DIV_12
+  *         @arg @ref LL_RCC_PLLM_DIV_13
+  *         @arg @ref LL_RCC_PLLM_DIV_14
+  *         @arg @ref LL_RCC_PLLM_DIV_15
+  *         @arg @ref LL_RCC_PLLM_DIV_16
+  *         @arg @ref LL_RCC_PLLM_DIV_17
+  *         @arg @ref LL_RCC_PLLM_DIV_18
+  *         @arg @ref LL_RCC_PLLM_DIV_19
+  *         @arg @ref LL_RCC_PLLM_DIV_20
+  *         @arg @ref LL_RCC_PLLM_DIV_21
+  *         @arg @ref LL_RCC_PLLM_DIV_22
+  *         @arg @ref LL_RCC_PLLM_DIV_23
+  *         @arg @ref LL_RCC_PLLM_DIV_24
+  *         @arg @ref LL_RCC_PLLM_DIV_25
+  *         @arg @ref LL_RCC_PLLM_DIV_26
+  *         @arg @ref LL_RCC_PLLM_DIV_27
+  *         @arg @ref LL_RCC_PLLM_DIV_28
+  *         @arg @ref LL_RCC_PLLM_DIV_29
+  *         @arg @ref LL_RCC_PLLM_DIV_30
+  *         @arg @ref LL_RCC_PLLM_DIV_31
+  *         @arg @ref LL_RCC_PLLM_DIV_32
+  *         @arg @ref LL_RCC_PLLM_DIV_33
+  *         @arg @ref LL_RCC_PLLM_DIV_34
+  *         @arg @ref LL_RCC_PLLM_DIV_35
+  *         @arg @ref LL_RCC_PLLM_DIV_36
+  *         @arg @ref LL_RCC_PLLM_DIV_37
+  *         @arg @ref LL_RCC_PLLM_DIV_38
+  *         @arg @ref LL_RCC_PLLM_DIV_39
+  *         @arg @ref LL_RCC_PLLM_DIV_40
+  *         @arg @ref LL_RCC_PLLM_DIV_41
+  *         @arg @ref LL_RCC_PLLM_DIV_42
+  *         @arg @ref LL_RCC_PLLM_DIV_43
+  *         @arg @ref LL_RCC_PLLM_DIV_44
+  *         @arg @ref LL_RCC_PLLM_DIV_45
+  *         @arg @ref LL_RCC_PLLM_DIV_46
+  *         @arg @ref LL_RCC_PLLM_DIV_47
+  *         @arg @ref LL_RCC_PLLM_DIV_48
+  *         @arg @ref LL_RCC_PLLM_DIV_49
+  *         @arg @ref LL_RCC_PLLM_DIV_50
+  *         @arg @ref LL_RCC_PLLM_DIV_51
+  *         @arg @ref LL_RCC_PLLM_DIV_52
+  *         @arg @ref LL_RCC_PLLM_DIV_53
+  *         @arg @ref LL_RCC_PLLM_DIV_54
+  *         @arg @ref LL_RCC_PLLM_DIV_55
+  *         @arg @ref LL_RCC_PLLM_DIV_56
+  *         @arg @ref LL_RCC_PLLM_DIV_57
+  *         @arg @ref LL_RCC_PLLM_DIV_58
+  *         @arg @ref LL_RCC_PLLM_DIV_59
+  *         @arg @ref LL_RCC_PLLM_DIV_60
+  *         @arg @ref LL_RCC_PLLM_DIV_61
+  *         @arg @ref LL_RCC_PLLM_DIV_62
+  *         @arg @ref LL_RCC_PLLM_DIV_63
+  * @param  __PLLN__ Between 50/192(*) and 432
+  *
+  *         (*) value not defined in all devices.
+  * @param  __PLLQ__ This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLQ_DIV_2
+  *         @arg @ref LL_RCC_PLLQ_DIV_3
+  *         @arg @ref LL_RCC_PLLQ_DIV_4
+  *         @arg @ref LL_RCC_PLLQ_DIV_5
+  *         @arg @ref LL_RCC_PLLQ_DIV_6
+  *         @arg @ref LL_RCC_PLLQ_DIV_7
+  *         @arg @ref LL_RCC_PLLQ_DIV_8
+  *         @arg @ref LL_RCC_PLLQ_DIV_9
+  *         @arg @ref LL_RCC_PLLQ_DIV_10
+  *         @arg @ref LL_RCC_PLLQ_DIV_11
+  *         @arg @ref LL_RCC_PLLQ_DIV_12
+  *         @arg @ref LL_RCC_PLLQ_DIV_13
+  *         @arg @ref LL_RCC_PLLQ_DIV_14
+  *         @arg @ref LL_RCC_PLLQ_DIV_15
+  * @retval PLL clock frequency (in Hz)
+  */
+#define __LL_RCC_CALC_PLLCLK_48M_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLQ__) ((__INPUTFREQ__) / (__PLLM__) * (__PLLN__) / \
+                   ((__PLLQ__) >> RCC_PLLCFGR_PLLQ_Pos ))
+
+#if defined(DSI)
+/**
+  * @brief  Helper macro to calculate the PLLCLK frequency used on DSI
+  * @note ex: @ref __LL_RCC_CALC_PLLCLK_DSI_FREQ (HSE_VALUE, @ref LL_RCC_PLL_GetDivider (),
+  *             @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetR ());
+  * @param  __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
+  * @param  __PLLM__ This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLM_DIV_2
+  *         @arg @ref LL_RCC_PLLM_DIV_3
+  *         @arg @ref LL_RCC_PLLM_DIV_4
+  *         @arg @ref LL_RCC_PLLM_DIV_5
+  *         @arg @ref LL_RCC_PLLM_DIV_6
+  *         @arg @ref LL_RCC_PLLM_DIV_7
+  *         @arg @ref LL_RCC_PLLM_DIV_8
+  *         @arg @ref LL_RCC_PLLM_DIV_9
+  *         @arg @ref LL_RCC_PLLM_DIV_10
+  *         @arg @ref LL_RCC_PLLM_DIV_11
+  *         @arg @ref LL_RCC_PLLM_DIV_12
+  *         @arg @ref LL_RCC_PLLM_DIV_13
+  *         @arg @ref LL_RCC_PLLM_DIV_14
+  *         @arg @ref LL_RCC_PLLM_DIV_15
+  *         @arg @ref LL_RCC_PLLM_DIV_16
+  *         @arg @ref LL_RCC_PLLM_DIV_17
+  *         @arg @ref LL_RCC_PLLM_DIV_18
+  *         @arg @ref LL_RCC_PLLM_DIV_19
+  *         @arg @ref LL_RCC_PLLM_DIV_20
+  *         @arg @ref LL_RCC_PLLM_DIV_21
+  *         @arg @ref LL_RCC_PLLM_DIV_22
+  *         @arg @ref LL_RCC_PLLM_DIV_23
+  *         @arg @ref LL_RCC_PLLM_DIV_24
+  *         @arg @ref LL_RCC_PLLM_DIV_25
+  *         @arg @ref LL_RCC_PLLM_DIV_26
+  *         @arg @ref LL_RCC_PLLM_DIV_27
+  *         @arg @ref LL_RCC_PLLM_DIV_28
+  *         @arg @ref LL_RCC_PLLM_DIV_29
+  *         @arg @ref LL_RCC_PLLM_DIV_30
+  *         @arg @ref LL_RCC_PLLM_DIV_31
+  *         @arg @ref LL_RCC_PLLM_DIV_32
+  *         @arg @ref LL_RCC_PLLM_DIV_33
+  *         @arg @ref LL_RCC_PLLM_DIV_34
+  *         @arg @ref LL_RCC_PLLM_DIV_35
+  *         @arg @ref LL_RCC_PLLM_DIV_36
+  *         @arg @ref LL_RCC_PLLM_DIV_37
+  *         @arg @ref LL_RCC_PLLM_DIV_38
+  *         @arg @ref LL_RCC_PLLM_DIV_39
+  *         @arg @ref LL_RCC_PLLM_DIV_40
+  *         @arg @ref LL_RCC_PLLM_DIV_41
+  *         @arg @ref LL_RCC_PLLM_DIV_42
+  *         @arg @ref LL_RCC_PLLM_DIV_43
+  *         @arg @ref LL_RCC_PLLM_DIV_44
+  *         @arg @ref LL_RCC_PLLM_DIV_45
+  *         @arg @ref LL_RCC_PLLM_DIV_46
+  *         @arg @ref LL_RCC_PLLM_DIV_47
+  *         @arg @ref LL_RCC_PLLM_DIV_48
+  *         @arg @ref LL_RCC_PLLM_DIV_49
+  *         @arg @ref LL_RCC_PLLM_DIV_50
+  *         @arg @ref LL_RCC_PLLM_DIV_51
+  *         @arg @ref LL_RCC_PLLM_DIV_52
+  *         @arg @ref LL_RCC_PLLM_DIV_53
+  *         @arg @ref LL_RCC_PLLM_DIV_54
+  *         @arg @ref LL_RCC_PLLM_DIV_55
+  *         @arg @ref LL_RCC_PLLM_DIV_56
+  *         @arg @ref LL_RCC_PLLM_DIV_57
+  *         @arg @ref LL_RCC_PLLM_DIV_58
+  *         @arg @ref LL_RCC_PLLM_DIV_59
+  *         @arg @ref LL_RCC_PLLM_DIV_60
+  *         @arg @ref LL_RCC_PLLM_DIV_61
+  *         @arg @ref LL_RCC_PLLM_DIV_62
+  *         @arg @ref LL_RCC_PLLM_DIV_63
+  * @param  __PLLN__ Between 50 and 432
+  * @param  __PLLR__ This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLR_DIV_2
+  *         @arg @ref LL_RCC_PLLR_DIV_3
+  *         @arg @ref LL_RCC_PLLR_DIV_4
+  *         @arg @ref LL_RCC_PLLR_DIV_5
+  *         @arg @ref LL_RCC_PLLR_DIV_6
+  *         @arg @ref LL_RCC_PLLR_DIV_7
+  * @retval PLL clock frequency (in Hz)
+  */
+#define __LL_RCC_CALC_PLLCLK_DSI_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLR__) ((__INPUTFREQ__) / (__PLLM__) * (__PLLN__) / \
+                   ((__PLLR__) >> RCC_PLLCFGR_PLLR_Pos ))
+#endif /* DSI */
+
+#if defined(RCC_PLLR_I2S_CLKSOURCE_SUPPORT)
+/**
+  * @brief  Helper macro to calculate the PLLCLK frequency used on I2S
+  * @note ex: @ref __LL_RCC_CALC_PLLCLK_I2S_FREQ (HSE_VALUE, @ref LL_RCC_PLL_GetDivider (),
+  *             @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetR ());
+  * @param  __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
+  * @param  __PLLM__ This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLM_DIV_2
+  *         @arg @ref LL_RCC_PLLM_DIV_3
+  *         @arg @ref LL_RCC_PLLM_DIV_4
+  *         @arg @ref LL_RCC_PLLM_DIV_5
+  *         @arg @ref LL_RCC_PLLM_DIV_6
+  *         @arg @ref LL_RCC_PLLM_DIV_7
+  *         @arg @ref LL_RCC_PLLM_DIV_8
+  *         @arg @ref LL_RCC_PLLM_DIV_9
+  *         @arg @ref LL_RCC_PLLM_DIV_10
+  *         @arg @ref LL_RCC_PLLM_DIV_11
+  *         @arg @ref LL_RCC_PLLM_DIV_12
+  *         @arg @ref LL_RCC_PLLM_DIV_13
+  *         @arg @ref LL_RCC_PLLM_DIV_14
+  *         @arg @ref LL_RCC_PLLM_DIV_15
+  *         @arg @ref LL_RCC_PLLM_DIV_16
+  *         @arg @ref LL_RCC_PLLM_DIV_17
+  *         @arg @ref LL_RCC_PLLM_DIV_18
+  *         @arg @ref LL_RCC_PLLM_DIV_19
+  *         @arg @ref LL_RCC_PLLM_DIV_20
+  *         @arg @ref LL_RCC_PLLM_DIV_21
+  *         @arg @ref LL_RCC_PLLM_DIV_22
+  *         @arg @ref LL_RCC_PLLM_DIV_23
+  *         @arg @ref LL_RCC_PLLM_DIV_24
+  *         @arg @ref LL_RCC_PLLM_DIV_25
+  *         @arg @ref LL_RCC_PLLM_DIV_26
+  *         @arg @ref LL_RCC_PLLM_DIV_27
+  *         @arg @ref LL_RCC_PLLM_DIV_28
+  *         @arg @ref LL_RCC_PLLM_DIV_29
+  *         @arg @ref LL_RCC_PLLM_DIV_30
+  *         @arg @ref LL_RCC_PLLM_DIV_31
+  *         @arg @ref LL_RCC_PLLM_DIV_32
+  *         @arg @ref LL_RCC_PLLM_DIV_33
+  *         @arg @ref LL_RCC_PLLM_DIV_34
+  *         @arg @ref LL_RCC_PLLM_DIV_35
+  *         @arg @ref LL_RCC_PLLM_DIV_36
+  *         @arg @ref LL_RCC_PLLM_DIV_37
+  *         @arg @ref LL_RCC_PLLM_DIV_38
+  *         @arg @ref LL_RCC_PLLM_DIV_39
+  *         @arg @ref LL_RCC_PLLM_DIV_40
+  *         @arg @ref LL_RCC_PLLM_DIV_41
+  *         @arg @ref LL_RCC_PLLM_DIV_42
+  *         @arg @ref LL_RCC_PLLM_DIV_43
+  *         @arg @ref LL_RCC_PLLM_DIV_44
+  *         @arg @ref LL_RCC_PLLM_DIV_45
+  *         @arg @ref LL_RCC_PLLM_DIV_46
+  *         @arg @ref LL_RCC_PLLM_DIV_47
+  *         @arg @ref LL_RCC_PLLM_DIV_48
+  *         @arg @ref LL_RCC_PLLM_DIV_49
+  *         @arg @ref LL_RCC_PLLM_DIV_50
+  *         @arg @ref LL_RCC_PLLM_DIV_51
+  *         @arg @ref LL_RCC_PLLM_DIV_52
+  *         @arg @ref LL_RCC_PLLM_DIV_53
+  *         @arg @ref LL_RCC_PLLM_DIV_54
+  *         @arg @ref LL_RCC_PLLM_DIV_55
+  *         @arg @ref LL_RCC_PLLM_DIV_56
+  *         @arg @ref LL_RCC_PLLM_DIV_57
+  *         @arg @ref LL_RCC_PLLM_DIV_58
+  *         @arg @ref LL_RCC_PLLM_DIV_59
+  *         @arg @ref LL_RCC_PLLM_DIV_60
+  *         @arg @ref LL_RCC_PLLM_DIV_61
+  *         @arg @ref LL_RCC_PLLM_DIV_62
+  *         @arg @ref LL_RCC_PLLM_DIV_63
+  * @param  __PLLN__ Between 50 and 432
+  * @param  __PLLR__ This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLR_DIV_2
+  *         @arg @ref LL_RCC_PLLR_DIV_3
+  *         @arg @ref LL_RCC_PLLR_DIV_4
+  *         @arg @ref LL_RCC_PLLR_DIV_5
+  *         @arg @ref LL_RCC_PLLR_DIV_6
+  *         @arg @ref LL_RCC_PLLR_DIV_7
+  * @retval PLL clock frequency (in Hz)
+  */
+#define __LL_RCC_CALC_PLLCLK_I2S_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLR__) ((__INPUTFREQ__) / (__PLLM__) * (__PLLN__) / \
+                   ((__PLLR__) >> RCC_PLLCFGR_PLLR_Pos ))
+#endif /* RCC_PLLR_I2S_CLKSOURCE_SUPPORT */
+
+#if defined(SPDIFRX)
+/**
+  * @brief  Helper macro to calculate the PLLCLK frequency used on SPDIFRX
+  * @note ex: @ref __LL_RCC_CALC_PLLCLK_SPDIFRX_FREQ (HSE_VALUE, @ref LL_RCC_PLL_GetDivider (),
+  *             @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetR ());
+  * @param  __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
+  * @param  __PLLM__ This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLM_DIV_2
+  *         @arg @ref LL_RCC_PLLM_DIV_3
+  *         @arg @ref LL_RCC_PLLM_DIV_4
+  *         @arg @ref LL_RCC_PLLM_DIV_5
+  *         @arg @ref LL_RCC_PLLM_DIV_6
+  *         @arg @ref LL_RCC_PLLM_DIV_7
+  *         @arg @ref LL_RCC_PLLM_DIV_8
+  *         @arg @ref LL_RCC_PLLM_DIV_9
+  *         @arg @ref LL_RCC_PLLM_DIV_10
+  *         @arg @ref LL_RCC_PLLM_DIV_11
+  *         @arg @ref LL_RCC_PLLM_DIV_12
+  *         @arg @ref LL_RCC_PLLM_DIV_13
+  *         @arg @ref LL_RCC_PLLM_DIV_14
+  *         @arg @ref LL_RCC_PLLM_DIV_15
+  *         @arg @ref LL_RCC_PLLM_DIV_16
+  *         @arg @ref LL_RCC_PLLM_DIV_17
+  *         @arg @ref LL_RCC_PLLM_DIV_18
+  *         @arg @ref LL_RCC_PLLM_DIV_19
+  *         @arg @ref LL_RCC_PLLM_DIV_20
+  *         @arg @ref LL_RCC_PLLM_DIV_21
+  *         @arg @ref LL_RCC_PLLM_DIV_22
+  *         @arg @ref LL_RCC_PLLM_DIV_23
+  *         @arg @ref LL_RCC_PLLM_DIV_24
+  *         @arg @ref LL_RCC_PLLM_DIV_25
+  *         @arg @ref LL_RCC_PLLM_DIV_26
+  *         @arg @ref LL_RCC_PLLM_DIV_27
+  *         @arg @ref LL_RCC_PLLM_DIV_28
+  *         @arg @ref LL_RCC_PLLM_DIV_29
+  *         @arg @ref LL_RCC_PLLM_DIV_30
+  *         @arg @ref LL_RCC_PLLM_DIV_31
+  *         @arg @ref LL_RCC_PLLM_DIV_32
+  *         @arg @ref LL_RCC_PLLM_DIV_33
+  *         @arg @ref LL_RCC_PLLM_DIV_34
+  *         @arg @ref LL_RCC_PLLM_DIV_35
+  *         @arg @ref LL_RCC_PLLM_DIV_36
+  *         @arg @ref LL_RCC_PLLM_DIV_37
+  *         @arg @ref LL_RCC_PLLM_DIV_38
+  *         @arg @ref LL_RCC_PLLM_DIV_39
+  *         @arg @ref LL_RCC_PLLM_DIV_40
+  *         @arg @ref LL_RCC_PLLM_DIV_41
+  *         @arg @ref LL_RCC_PLLM_DIV_42
+  *         @arg @ref LL_RCC_PLLM_DIV_43
+  *         @arg @ref LL_RCC_PLLM_DIV_44
+  *         @arg @ref LL_RCC_PLLM_DIV_45
+  *         @arg @ref LL_RCC_PLLM_DIV_46
+  *         @arg @ref LL_RCC_PLLM_DIV_47
+  *         @arg @ref LL_RCC_PLLM_DIV_48
+  *         @arg @ref LL_RCC_PLLM_DIV_49
+  *         @arg @ref LL_RCC_PLLM_DIV_50
+  *         @arg @ref LL_RCC_PLLM_DIV_51
+  *         @arg @ref LL_RCC_PLLM_DIV_52
+  *         @arg @ref LL_RCC_PLLM_DIV_53
+  *         @arg @ref LL_RCC_PLLM_DIV_54
+  *         @arg @ref LL_RCC_PLLM_DIV_55
+  *         @arg @ref LL_RCC_PLLM_DIV_56
+  *         @arg @ref LL_RCC_PLLM_DIV_57
+  *         @arg @ref LL_RCC_PLLM_DIV_58
+  *         @arg @ref LL_RCC_PLLM_DIV_59
+  *         @arg @ref LL_RCC_PLLM_DIV_60
+  *         @arg @ref LL_RCC_PLLM_DIV_61
+  *         @arg @ref LL_RCC_PLLM_DIV_62
+  *         @arg @ref LL_RCC_PLLM_DIV_63
+  * @param  __PLLN__ Between 50 and 432
+  * @param  __PLLR__ This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLR_DIV_2
+  *         @arg @ref LL_RCC_PLLR_DIV_3
+  *         @arg @ref LL_RCC_PLLR_DIV_4
+  *         @arg @ref LL_RCC_PLLR_DIV_5
+  *         @arg @ref LL_RCC_PLLR_DIV_6
+  *         @arg @ref LL_RCC_PLLR_DIV_7
+  * @retval PLL clock frequency (in Hz)
+  */
+#define __LL_RCC_CALC_PLLCLK_SPDIFRX_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLR__) ((__INPUTFREQ__) / (__PLLM__) * (__PLLN__) / \
+                   ((__PLLR__) >> RCC_PLLCFGR_PLLR_Pos ))
+#endif /* SPDIFRX */
+
+#if defined(RCC_PLLCFGR_PLLR)
+#if defined(SAI1)
+/**
+  * @brief  Helper macro to calculate the PLLCLK frequency used on SAI
+  * @note ex: @ref __LL_RCC_CALC_PLLCLK_SAI_FREQ (HSE_VALUE, @ref LL_RCC_PLL_GetDivider (),
+  *             @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetR (), @ref LL_RCC_PLL_GetDIVR ());
+  * @param  __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
+  * @param  __PLLM__ This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLM_DIV_2
+  *         @arg @ref LL_RCC_PLLM_DIV_3
+  *         @arg @ref LL_RCC_PLLM_DIV_4
+  *         @arg @ref LL_RCC_PLLM_DIV_5
+  *         @arg @ref LL_RCC_PLLM_DIV_6
+  *         @arg @ref LL_RCC_PLLM_DIV_7
+  *         @arg @ref LL_RCC_PLLM_DIV_8
+  *         @arg @ref LL_RCC_PLLM_DIV_9
+  *         @arg @ref LL_RCC_PLLM_DIV_10
+  *         @arg @ref LL_RCC_PLLM_DIV_11
+  *         @arg @ref LL_RCC_PLLM_DIV_12
+  *         @arg @ref LL_RCC_PLLM_DIV_13
+  *         @arg @ref LL_RCC_PLLM_DIV_14
+  *         @arg @ref LL_RCC_PLLM_DIV_15
+  *         @arg @ref LL_RCC_PLLM_DIV_16
+  *         @arg @ref LL_RCC_PLLM_DIV_17
+  *         @arg @ref LL_RCC_PLLM_DIV_18
+  *         @arg @ref LL_RCC_PLLM_DIV_19
+  *         @arg @ref LL_RCC_PLLM_DIV_20
+  *         @arg @ref LL_RCC_PLLM_DIV_21
+  *         @arg @ref LL_RCC_PLLM_DIV_22
+  *         @arg @ref LL_RCC_PLLM_DIV_23
+  *         @arg @ref LL_RCC_PLLM_DIV_24
+  *         @arg @ref LL_RCC_PLLM_DIV_25
+  *         @arg @ref LL_RCC_PLLM_DIV_26
+  *         @arg @ref LL_RCC_PLLM_DIV_27
+  *         @arg @ref LL_RCC_PLLM_DIV_28
+  *         @arg @ref LL_RCC_PLLM_DIV_29
+  *         @arg @ref LL_RCC_PLLM_DIV_30
+  *         @arg @ref LL_RCC_PLLM_DIV_31
+  *         @arg @ref LL_RCC_PLLM_DIV_32
+  *         @arg @ref LL_RCC_PLLM_DIV_33
+  *         @arg @ref LL_RCC_PLLM_DIV_34
+  *         @arg @ref LL_RCC_PLLM_DIV_35
+  *         @arg @ref LL_RCC_PLLM_DIV_36
+  *         @arg @ref LL_RCC_PLLM_DIV_37
+  *         @arg @ref LL_RCC_PLLM_DIV_38
+  *         @arg @ref LL_RCC_PLLM_DIV_39
+  *         @arg @ref LL_RCC_PLLM_DIV_40
+  *         @arg @ref LL_RCC_PLLM_DIV_41
+  *         @arg @ref LL_RCC_PLLM_DIV_42
+  *         @arg @ref LL_RCC_PLLM_DIV_43
+  *         @arg @ref LL_RCC_PLLM_DIV_44
+  *         @arg @ref LL_RCC_PLLM_DIV_45
+  *         @arg @ref LL_RCC_PLLM_DIV_46
+  *         @arg @ref LL_RCC_PLLM_DIV_47
+  *         @arg @ref LL_RCC_PLLM_DIV_48
+  *         @arg @ref LL_RCC_PLLM_DIV_49
+  *         @arg @ref LL_RCC_PLLM_DIV_50
+  *         @arg @ref LL_RCC_PLLM_DIV_51
+  *         @arg @ref LL_RCC_PLLM_DIV_52
+  *         @arg @ref LL_RCC_PLLM_DIV_53
+  *         @arg @ref LL_RCC_PLLM_DIV_54
+  *         @arg @ref LL_RCC_PLLM_DIV_55
+  *         @arg @ref LL_RCC_PLLM_DIV_56
+  *         @arg @ref LL_RCC_PLLM_DIV_57
+  *         @arg @ref LL_RCC_PLLM_DIV_58
+  *         @arg @ref LL_RCC_PLLM_DIV_59
+  *         @arg @ref LL_RCC_PLLM_DIV_60
+  *         @arg @ref LL_RCC_PLLM_DIV_61
+  *         @arg @ref LL_RCC_PLLM_DIV_62
+  *         @arg @ref LL_RCC_PLLM_DIV_63
+  * @param  __PLLN__ Between 50 and 432
+  * @param  __PLLR__ This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLR_DIV_2
+  *         @arg @ref LL_RCC_PLLR_DIV_3
+  *         @arg @ref LL_RCC_PLLR_DIV_4
+  *         @arg @ref LL_RCC_PLLR_DIV_5
+  *         @arg @ref LL_RCC_PLLR_DIV_6
+  *         @arg @ref LL_RCC_PLLR_DIV_7
+  * @param  __PLLDIVR__ This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLDIVR_DIV_1 (*)
+  *         @arg @ref LL_RCC_PLLDIVR_DIV_2 (*)
+  *         @arg @ref LL_RCC_PLLDIVR_DIV_3 (*)
+  *         @arg @ref LL_RCC_PLLDIVR_DIV_4 (*)
+  *         @arg @ref LL_RCC_PLLDIVR_DIV_5 (*)
+  *         @arg @ref LL_RCC_PLLDIVR_DIV_6 (*)
+  *         @arg @ref LL_RCC_PLLDIVR_DIV_7 (*)
+  *         @arg @ref LL_RCC_PLLDIVR_DIV_8 (*)
+  *         @arg @ref LL_RCC_PLLDIVR_DIV_9 (*)
+  *         @arg @ref LL_RCC_PLLDIVR_DIV_10 (*)
+  *         @arg @ref LL_RCC_PLLDIVR_DIV_11 (*)
+  *         @arg @ref LL_RCC_PLLDIVR_DIV_12 (*)
+  *         @arg @ref LL_RCC_PLLDIVR_DIV_13 (*)
+  *         @arg @ref LL_RCC_PLLDIVR_DIV_14 (*)
+  *         @arg @ref LL_RCC_PLLDIVR_DIV_15 (*)
+  *         @arg @ref LL_RCC_PLLDIVR_DIV_16 (*)
+  *         @arg @ref LL_RCC_PLLDIVR_DIV_17 (*)
+  *         @arg @ref LL_RCC_PLLDIVR_DIV_18 (*)
+  *         @arg @ref LL_RCC_PLLDIVR_DIV_19 (*)
+  *         @arg @ref LL_RCC_PLLDIVR_DIV_20 (*)
+  *         @arg @ref LL_RCC_PLLDIVR_DIV_21 (*)
+  *         @arg @ref LL_RCC_PLLDIVR_DIV_22 (*)
+  *         @arg @ref LL_RCC_PLLDIVR_DIV_23 (*)
+  *         @arg @ref LL_RCC_PLLDIVR_DIV_24 (*)
+  *         @arg @ref LL_RCC_PLLDIVR_DIV_25 (*)
+  *         @arg @ref LL_RCC_PLLDIVR_DIV_26 (*)
+  *         @arg @ref LL_RCC_PLLDIVR_DIV_27 (*)
+  *         @arg @ref LL_RCC_PLLDIVR_DIV_28 (*)
+  *         @arg @ref LL_RCC_PLLDIVR_DIV_29 (*)
+  *         @arg @ref LL_RCC_PLLDIVR_DIV_30 (*)
+  *         @arg @ref LL_RCC_PLLDIVR_DIV_31 (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval PLL clock frequency (in Hz)
+  */
+#if defined(RCC_DCKCFGR_PLLDIVR)
+#define __LL_RCC_CALC_PLLCLK_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLR__, __PLLDIVR__) (((__INPUTFREQ__) / (__PLLM__) * (__PLLN__) / \
+                   ((__PLLR__) >> RCC_PLLCFGR_PLLR_Pos )) / ((__PLLDIVR__) >> RCC_DCKCFGR_PLLDIVR_Pos ))
+#else
+#define __LL_RCC_CALC_PLLCLK_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLR__) ((__INPUTFREQ__) / (__PLLM__) * (__PLLN__) / \
+                   ((__PLLR__) >> RCC_PLLCFGR_PLLR_Pos ))
+#endif /* RCC_DCKCFGR_PLLDIVR */
+#endif /* SAI1 */
+#endif /* RCC_PLLCFGR_PLLR */
+
+#if defined(RCC_PLLSAI_SUPPORT)
+/**
+  * @brief  Helper macro to calculate the PLLSAI frequency used for SAI domain
+  * @note ex: @ref __LL_RCC_CALC_PLLSAI_SAI_FREQ (HSE_VALUE,@ref LL_RCC_PLLSAI_GetDivider (),
+  *             @ref LL_RCC_PLLSAI_GetN (), @ref LL_RCC_PLLSAI_GetQ (), @ref LL_RCC_PLLSAI_GetDIVQ ());
+  * @param  __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
+  * @param  __PLLM__ This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_2
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_3
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_4
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_5
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_6
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_7
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_8
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_9
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_10
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_11
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_12
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_13
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_14
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_15
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_16
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_17
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_18
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_19
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_20
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_21
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_22
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_23
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_24
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_25
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_26
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_27
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_28
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_29
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_30
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_31
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_32
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_33
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_34
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_35
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_36
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_37
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_38
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_39
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_40
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_41
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_42
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_43
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_44
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_45
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_46
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_47
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_48
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_49
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_50
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_51
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_52
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_53
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_54
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_55
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_56
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_57
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_58
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_59
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_60
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_61
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_62
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_63
+  * @param  __PLLSAIN__ Between 49/50(*) and 432
+  *
+  *         (*) value not defined in all devices.
+  * @param  __PLLSAIQ__ This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLSAIQ_DIV_2
+  *         @arg @ref LL_RCC_PLLSAIQ_DIV_3
+  *         @arg @ref LL_RCC_PLLSAIQ_DIV_4
+  *         @arg @ref LL_RCC_PLLSAIQ_DIV_5
+  *         @arg @ref LL_RCC_PLLSAIQ_DIV_6
+  *         @arg @ref LL_RCC_PLLSAIQ_DIV_7
+  *         @arg @ref LL_RCC_PLLSAIQ_DIV_8
+  *         @arg @ref LL_RCC_PLLSAIQ_DIV_9
+  *         @arg @ref LL_RCC_PLLSAIQ_DIV_10
+  *         @arg @ref LL_RCC_PLLSAIQ_DIV_11
+  *         @arg @ref LL_RCC_PLLSAIQ_DIV_12
+  *         @arg @ref LL_RCC_PLLSAIQ_DIV_13
+  *         @arg @ref LL_RCC_PLLSAIQ_DIV_14
+  *         @arg @ref LL_RCC_PLLSAIQ_DIV_15
+  * @param  __PLLSAIDIVQ__ This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_1
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_2
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_3
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_4
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_5
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_6
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_7
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_8
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_9
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_10
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_11
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_12
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_13
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_14
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_15
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_16
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_17
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_18
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_19
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_20
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_21
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_22
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_23
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_24
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_25
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_26
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_27
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_28
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_29
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_30
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_31
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_32
+  * @retval PLLSAI clock frequency (in Hz)
+  */
+#define __LL_RCC_CALC_PLLSAI_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAIN__, __PLLSAIQ__, __PLLSAIDIVQ__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLSAIN__) / \
+                   (((__PLLSAIQ__) >> RCC_PLLSAICFGR_PLLSAIQ_Pos) * (((__PLLSAIDIVQ__) >> RCC_DCKCFGR_PLLSAIDIVQ_Pos) + 1U)))
+
+#if defined(RCC_PLLSAICFGR_PLLSAIP)
+/**
+  * @brief  Helper macro to calculate the PLLSAI frequency used on 48Mhz domain
+  * @note ex: @ref __LL_RCC_CALC_PLLSAI_48M_FREQ (HSE_VALUE,@ref LL_RCC_PLLSAI_GetDivider (),
+  *             @ref LL_RCC_PLLSAI_GetN (), @ref LL_RCC_PLLSAI_GetP ());
+  * @param  __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
+  * @param  __PLLM__ This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_2
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_3
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_4
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_5
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_6
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_7
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_8
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_9
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_10
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_11
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_12
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_13
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_14
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_15
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_16
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_17
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_18
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_19
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_20
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_21
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_22
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_23
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_24
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_25
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_26
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_27
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_28
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_29
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_30
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_31
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_32
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_33
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_34
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_35
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_36
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_37
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_38
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_39
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_40
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_41
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_42
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_43
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_44
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_45
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_46
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_47
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_48
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_49
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_50
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_51
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_52
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_53
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_54
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_55
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_56
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_57
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_58
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_59
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_60
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_61
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_62
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_63
+  * @param  __PLLSAIN__ Between 50 and 432
+  * @param  __PLLSAIP__ This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLSAIP_DIV_2
+  *         @arg @ref LL_RCC_PLLSAIP_DIV_4
+  *         @arg @ref LL_RCC_PLLSAIP_DIV_6
+  *         @arg @ref LL_RCC_PLLSAIP_DIV_8
+  * @retval PLLSAI clock frequency (in Hz)
+  */
+#define __LL_RCC_CALC_PLLSAI_48M_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAIN__, __PLLSAIP__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLSAIN__) / \
+                   ((((__PLLSAIP__) >> RCC_PLLSAICFGR_PLLSAIP_Pos) + 1U) * 2U))
+#endif /* RCC_PLLSAICFGR_PLLSAIP */
+
+#if defined(LTDC)
+/**
+  * @brief  Helper macro to calculate the PLLSAI frequency used for LTDC domain
+  * @note ex: @ref __LL_RCC_CALC_PLLSAI_LTDC_FREQ (HSE_VALUE,@ref LL_RCC_PLLSAI_GetDivider (),
+  *             @ref LL_RCC_PLLSAI_GetN (), @ref LL_RCC_PLLSAI_GetR (), @ref LL_RCC_PLLSAI_GetDIVR ());
+  * @param  __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
+  * @param  __PLLM__ This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_2
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_3
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_4
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_5
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_6
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_7
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_8
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_9
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_10
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_11
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_12
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_13
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_14
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_15
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_16
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_17
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_18
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_19
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_20
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_21
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_22
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_23
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_24
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_25
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_26
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_27
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_28
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_29
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_30
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_31
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_32
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_33
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_34
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_35
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_36
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_37
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_38
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_39
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_40
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_41
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_42
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_43
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_44
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_45
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_46
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_47
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_48
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_49
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_50
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_51
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_52
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_53
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_54
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_55
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_56
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_57
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_58
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_59
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_60
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_61
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_62
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_63
+  * @param  __PLLSAIN__ Between 49/50(*) and 432
+  *
+  *         (*) value not defined in all devices.
+  * @param  __PLLSAIR__ This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLSAIR_DIV_2
+  *         @arg @ref LL_RCC_PLLSAIR_DIV_3
+  *         @arg @ref LL_RCC_PLLSAIR_DIV_4
+  *         @arg @ref LL_RCC_PLLSAIR_DIV_5
+  *         @arg @ref LL_RCC_PLLSAIR_DIV_6
+  *         @arg @ref LL_RCC_PLLSAIR_DIV_7
+  * @param  __PLLSAIDIVR__ This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLSAIDIVR_DIV_2
+  *         @arg @ref LL_RCC_PLLSAIDIVR_DIV_4
+  *         @arg @ref LL_RCC_PLLSAIDIVR_DIV_8
+  *         @arg @ref LL_RCC_PLLSAIDIVR_DIV_16
+  * @retval PLLSAI clock frequency (in Hz)
+  */
+#define __LL_RCC_CALC_PLLSAI_LTDC_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAIN__, __PLLSAIR__, __PLLSAIDIVR__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLSAIN__) / \
+                   (((__PLLSAIR__) >> RCC_PLLSAICFGR_PLLSAIR_Pos) * (aRCC_PLLSAIDIVRPrescTable[(__PLLSAIDIVR__) >> RCC_DCKCFGR_PLLSAIDIVR_Pos])))
+#endif /* LTDC */
+#endif /* RCC_PLLSAI_SUPPORT */
+
+#if defined(RCC_PLLI2S_SUPPORT)
+#if defined(RCC_DCKCFGR_PLLI2SDIVQ) || defined(RCC_DCKCFGR_PLLI2SDIVR)
+/**
+  * @brief  Helper macro to calculate the PLLI2S frequency used for SAI domain
+  * @note ex: @ref __LL_RCC_CALC_PLLI2S_SAI_FREQ (HSE_VALUE,@ref LL_RCC_PLLI2S_GetDivider (),
+  *             @ref LL_RCC_PLLI2S_GetN (), @ref LL_RCC_PLLI2S_GetQ (), @ref LL_RCC_PLLI2S_GetDIVQ ());
+  * @param  __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
+  * @param  __PLLM__ This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_2
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_3
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_4
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_5
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_6
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_7
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_8
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_9
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_10
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_11
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_12
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_13
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_14
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_15
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_16
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_17
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_18
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_19
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_20
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_21
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_22
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_23
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_24
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_25
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_26
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_27
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_28
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_29
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_30
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_31
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_32
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_33
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_34
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_35
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_36
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_37
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_38
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_39
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_40
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_41
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_42
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_43
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_44
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_45
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_46
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_47
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_48
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_49
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_50
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_51
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_52
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_53
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_54
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_55
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_56
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_57
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_58
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_59
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_60
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_61
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_62
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_63
+  * @param  __PLLI2SN__ Between 50/192(*) and 432
+  *
+  *         (*) value not defined in all devices.
+  * @param  __PLLI2SQ_R__ This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLI2SQ_DIV_2 (*)
+  *         @arg @ref LL_RCC_PLLI2SQ_DIV_3 (*)
+  *         @arg @ref LL_RCC_PLLI2SQ_DIV_4 (*)
+  *         @arg @ref LL_RCC_PLLI2SQ_DIV_5 (*)
+  *         @arg @ref LL_RCC_PLLI2SQ_DIV_6 (*)
+  *         @arg @ref LL_RCC_PLLI2SQ_DIV_7 (*)
+  *         @arg @ref LL_RCC_PLLI2SQ_DIV_8 (*)
+  *         @arg @ref LL_RCC_PLLI2SQ_DIV_9 (*)
+  *         @arg @ref LL_RCC_PLLI2SQ_DIV_10 (*)
+  *         @arg @ref LL_RCC_PLLI2SQ_DIV_11 (*)
+  *         @arg @ref LL_RCC_PLLI2SQ_DIV_12 (*)
+  *         @arg @ref LL_RCC_PLLI2SQ_DIV_13 (*)
+  *         @arg @ref LL_RCC_PLLI2SQ_DIV_14 (*)
+  *         @arg @ref LL_RCC_PLLI2SQ_DIV_15 (*)
+  *         @arg @ref LL_RCC_PLLI2SR_DIV_2 (*)
+  *         @arg @ref LL_RCC_PLLI2SR_DIV_3 (*)
+  *         @arg @ref LL_RCC_PLLI2SR_DIV_4 (*)
+  *         @arg @ref LL_RCC_PLLI2SR_DIV_5 (*)
+  *         @arg @ref LL_RCC_PLLI2SR_DIV_6 (*)
+  *         @arg @ref LL_RCC_PLLI2SR_DIV_7 (*)
+  *
+  *         (*) value not defined in all devices.
+  * @param  __PLLI2SDIVQ_R__ This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_1 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_2 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_3 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_4 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_5 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_6 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_7 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_8 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_9 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_10 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_11 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_12 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_13 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_14 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_15 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_16 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_17 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_18 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_19 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_20 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_21 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_22 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_23 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_24 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_25 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_26 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_27 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_28 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_29 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_30 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_31 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_32 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_1 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_2 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_3 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_4 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_5 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_6 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_7 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_8 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_9 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_10 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_11 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_12 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_13 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_14 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_15 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_16 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_17 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_18 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_19 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_20 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_21 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_22 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_23 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_24 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_25 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_26 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_27 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_28 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_29 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_30 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_31 (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval PLLI2S clock frequency (in Hz)
+  */
+#if defined(RCC_DCKCFGR_PLLI2SDIVQ)
+#define __LL_RCC_CALC_PLLI2S_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLI2SN__, __PLLI2SQ_R__, __PLLI2SDIVQ_R__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLI2SN__) / \
+                   (((__PLLI2SQ_R__) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos) * (((__PLLI2SDIVQ_R__) >> RCC_DCKCFGR_PLLI2SDIVQ_Pos) + 1U)))
+#else
+#define __LL_RCC_CALC_PLLI2S_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLI2SN__, __PLLI2SQ_R__, __PLLI2SDIVQ_R__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLI2SN__) / \
+                   (((__PLLI2SQ_R__) >> RCC_PLLI2SCFGR_PLLI2SR_Pos) * ((__PLLI2SDIVQ_R__) >> RCC_DCKCFGR_PLLI2SDIVR_Pos)))
+
+#endif /* RCC_DCKCFGR_PLLI2SDIVQ */
+#endif /* RCC_DCKCFGR_PLLI2SDIVQ || RCC_DCKCFGR_PLLI2SDIVR */
+
+#if defined(SPDIFRX)
+/**
+  * @brief  Helper macro to calculate the PLLI2S frequency used on SPDIFRX domain
+  * @note ex: @ref __LL_RCC_CALC_PLLI2S_SPDIFRX_FREQ (HSE_VALUE,@ref LL_RCC_PLLI2S_GetDivider (),
+  *             @ref LL_RCC_PLLI2S_GetN (), @ref LL_RCC_PLLI2S_GetP ());
+  * @param  __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
+  * @param  __PLLM__ This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_2
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_3
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_4
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_5
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_6
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_7
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_8
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_9
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_10
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_11
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_12
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_13
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_14
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_15
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_16
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_17
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_18
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_19
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_20
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_21
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_22
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_23
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_24
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_25
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_26
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_27
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_28
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_29
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_30
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_31
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_32
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_33
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_34
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_35
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_36
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_37
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_38
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_39
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_40
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_41
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_42
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_43
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_44
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_45
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_46
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_47
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_48
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_49
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_50
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_51
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_52
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_53
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_54
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_55
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_56
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_57
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_58
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_59
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_60
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_61
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_62
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_63
+  * @param  __PLLI2SN__ Between 50 and 432
+  * @param  __PLLI2SP__ This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLI2SP_DIV_2
+  *         @arg @ref LL_RCC_PLLI2SP_DIV_4
+  *         @arg @ref LL_RCC_PLLI2SP_DIV_6
+  *         @arg @ref LL_RCC_PLLI2SP_DIV_8
+  * @retval PLLI2S clock frequency (in Hz)
+  */
+#define __LL_RCC_CALC_PLLI2S_SPDIFRX_FREQ(__INPUTFREQ__, __PLLM__, __PLLI2SN__, __PLLI2SP__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLI2SN__) / \
+                   ((((__PLLI2SP__) >> RCC_PLLI2SCFGR_PLLI2SP_Pos) + 1U) * 2U))
+
+#endif /* SPDIFRX */
+
+/**
+  * @brief  Helper macro to calculate the PLLI2S frequency used for I2S domain
+  * @note ex: @ref __LL_RCC_CALC_PLLI2S_I2S_FREQ (HSE_VALUE,@ref LL_RCC_PLLI2S_GetDivider (),
+  *             @ref LL_RCC_PLLI2S_GetN (), @ref LL_RCC_PLLI2S_GetR ());
+  * @param  __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
+  * @param  __PLLM__ This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_2
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_3
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_4
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_5
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_6
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_7
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_8
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_9
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_10
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_11
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_12
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_13
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_14
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_15
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_16
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_17
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_18
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_19
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_20
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_21
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_22
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_23
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_24
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_25
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_26
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_27
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_28
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_29
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_30
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_31
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_32
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_33
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_34
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_35
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_36
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_37
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_38
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_39
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_40
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_41
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_42
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_43
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_44
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_45
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_46
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_47
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_48
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_49
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_50
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_51
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_52
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_53
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_54
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_55
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_56
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_57
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_58
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_59
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_60
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_61
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_62
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_63
+  * @param  __PLLI2SN__ Between 50/192(*) and 432
+  *
+  *         (*) value not defined in all devices.
+  * @param  __PLLI2SR__ This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLI2SR_DIV_2
+  *         @arg @ref LL_RCC_PLLI2SR_DIV_3
+  *         @arg @ref LL_RCC_PLLI2SR_DIV_4
+  *         @arg @ref LL_RCC_PLLI2SR_DIV_5
+  *         @arg @ref LL_RCC_PLLI2SR_DIV_6
+  *         @arg @ref LL_RCC_PLLI2SR_DIV_7
+  * @retval PLLI2S clock frequency (in Hz)
+  */
+#define __LL_RCC_CALC_PLLI2S_I2S_FREQ(__INPUTFREQ__, __PLLM__, __PLLI2SN__, __PLLI2SR__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLI2SN__) / \
+                   ((__PLLI2SR__) >> RCC_PLLI2SCFGR_PLLI2SR_Pos))
+
+#if defined(RCC_PLLI2SCFGR_PLLI2SQ) && !defined(RCC_DCKCFGR_PLLI2SDIVQ)
+/**
+  * @brief  Helper macro to calculate the PLLI2S frequency used for 48Mhz domain
+  * @note ex: @ref __LL_RCC_CALC_PLLI2S_48M_FREQ (HSE_VALUE,@ref LL_RCC_PLLI2S_GetDivider (),
+  *             @ref LL_RCC_PLLI2S_GetN (), @ref LL_RCC_PLLI2S_GetQ ());
+  * @param  __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
+  * @param  __PLLM__ This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_2
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_3
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_4
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_5
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_6
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_7
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_8
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_9
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_10
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_11
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_12
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_13
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_14
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_15
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_16
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_17
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_18
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_19
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_20
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_21
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_22
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_23
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_24
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_25
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_26
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_27
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_28
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_29
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_30
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_31
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_32
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_33
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_34
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_35
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_36
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_37
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_38
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_39
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_40
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_41
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_42
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_43
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_44
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_45
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_46
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_47
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_48
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_49
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_50
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_51
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_52
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_53
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_54
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_55
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_56
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_57
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_58
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_59
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_60
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_61
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_62
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_63
+  * @param  __PLLI2SN__ Between 50 and 432
+  * @param  __PLLI2SQ__ This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLI2SQ_DIV_2
+  *         @arg @ref LL_RCC_PLLI2SQ_DIV_3
+  *         @arg @ref LL_RCC_PLLI2SQ_DIV_4
+  *         @arg @ref LL_RCC_PLLI2SQ_DIV_5
+  *         @arg @ref LL_RCC_PLLI2SQ_DIV_6
+  *         @arg @ref LL_RCC_PLLI2SQ_DIV_7
+  *         @arg @ref LL_RCC_PLLI2SQ_DIV_8
+  *         @arg @ref LL_RCC_PLLI2SQ_DIV_9
+  *         @arg @ref LL_RCC_PLLI2SQ_DIV_10
+  *         @arg @ref LL_RCC_PLLI2SQ_DIV_11
+  *         @arg @ref LL_RCC_PLLI2SQ_DIV_12
+  *         @arg @ref LL_RCC_PLLI2SQ_DIV_13
+  *         @arg @ref LL_RCC_PLLI2SQ_DIV_14
+  *         @arg @ref LL_RCC_PLLI2SQ_DIV_15
+  * @retval PLLI2S clock frequency (in Hz)
+  */
+#define __LL_RCC_CALC_PLLI2S_48M_FREQ(__INPUTFREQ__, __PLLM__, __PLLI2SN__, __PLLI2SQ__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLI2SN__) / \
+                   ((__PLLI2SQ__) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos))
+
+#endif /* RCC_PLLI2SCFGR_PLLI2SQ && !RCC_DCKCFGR_PLLI2SDIVQ */
+#endif /* RCC_PLLI2S_SUPPORT */
+
+/**
+  * @brief  Helper macro to calculate the HCLK frequency
+  * @param  __SYSCLKFREQ__ SYSCLK frequency (based on HSE/HSI/PLLCLK)
+  * @param  __AHBPRESCALER__ This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_SYSCLK_DIV_1
+  *         @arg @ref LL_RCC_SYSCLK_DIV_2
+  *         @arg @ref LL_RCC_SYSCLK_DIV_4
+  *         @arg @ref LL_RCC_SYSCLK_DIV_8
+  *         @arg @ref LL_RCC_SYSCLK_DIV_16
+  *         @arg @ref LL_RCC_SYSCLK_DIV_64
+  *         @arg @ref LL_RCC_SYSCLK_DIV_128
+  *         @arg @ref LL_RCC_SYSCLK_DIV_256
+  *         @arg @ref LL_RCC_SYSCLK_DIV_512
+  * @retval HCLK clock frequency (in Hz)
+  */
+#define __LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__, __AHBPRESCALER__) ((__SYSCLKFREQ__) >> AHBPrescTable[((__AHBPRESCALER__) & RCC_CFGR_HPRE) >>  RCC_CFGR_HPRE_Pos])
+
+/**
+  * @brief  Helper macro to calculate the PCLK1 frequency (ABP1)
+  * @param  __HCLKFREQ__ HCLK frequency
+  * @param  __APB1PRESCALER__ This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_APB1_DIV_1
+  *         @arg @ref LL_RCC_APB1_DIV_2
+  *         @arg @ref LL_RCC_APB1_DIV_4
+  *         @arg @ref LL_RCC_APB1_DIV_8
+  *         @arg @ref LL_RCC_APB1_DIV_16
+  * @retval PCLK1 clock frequency (in Hz)
+  */
+#define __LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB1PRESCALER__) >>  RCC_CFGR_PPRE1_Pos])
+
+/**
+  * @brief  Helper macro to calculate the PCLK2 frequency (ABP2)
+  * @param  __HCLKFREQ__ HCLK frequency
+  * @param  __APB2PRESCALER__ This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_APB2_DIV_1
+  *         @arg @ref LL_RCC_APB2_DIV_2
+  *         @arg @ref LL_RCC_APB2_DIV_4
+  *         @arg @ref LL_RCC_APB2_DIV_8
+  *         @arg @ref LL_RCC_APB2_DIV_16
+  * @retval PCLK2 clock frequency (in Hz)
+  */
+#define __LL_RCC_CALC_PCLK2_FREQ(__HCLKFREQ__, __APB2PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB2PRESCALER__) >>  RCC_CFGR_PPRE2_Pos])
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup RCC_LL_Exported_Functions RCC Exported Functions
+  * @{
+  */
+
+/** @defgroup RCC_LL_EF_HSE HSE
+  * @{
+  */
+
+/**
+  * @brief  Enable the Clock Security System.
+  * @rmtoll CR           CSSON         LL_RCC_HSE_EnableCSS
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_HSE_EnableCSS(void)
+{
+  SET_BIT(RCC->CR, RCC_CR_CSSON);
+}
+
+/**
+  * @brief  Enable HSE external oscillator (HSE Bypass)
+  * @rmtoll CR           HSEBYP        LL_RCC_HSE_EnableBypass
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_HSE_EnableBypass(void)
+{
+  SET_BIT(RCC->CR, RCC_CR_HSEBYP);
+}
+
+/**
+  * @brief  Disable HSE external oscillator (HSE Bypass)
+  * @rmtoll CR           HSEBYP        LL_RCC_HSE_DisableBypass
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_HSE_DisableBypass(void)
+{
+  CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
+}
+
+/**
+  * @brief  Enable HSE crystal oscillator (HSE ON)
+  * @rmtoll CR           HSEON         LL_RCC_HSE_Enable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_HSE_Enable(void)
+{
+  SET_BIT(RCC->CR, RCC_CR_HSEON);
+}
+
+/**
+  * @brief  Disable HSE crystal oscillator (HSE ON)
+  * @rmtoll CR           HSEON         LL_RCC_HSE_Disable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_HSE_Disable(void)
+{
+  CLEAR_BIT(RCC->CR, RCC_CR_HSEON);
+}
+
+/**
+  * @brief  Check if HSE oscillator Ready
+  * @rmtoll CR           HSERDY        LL_RCC_HSE_IsReady
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_HSE_IsReady(void)
+{
+  return (READ_BIT(RCC->CR, RCC_CR_HSERDY) == (RCC_CR_HSERDY));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EF_HSI HSI
+  * @{
+  */
+
+/**
+  * @brief  Enable HSI oscillator
+  * @rmtoll CR           HSION         LL_RCC_HSI_Enable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_HSI_Enable(void)
+{
+  SET_BIT(RCC->CR, RCC_CR_HSION);
+}
+
+/**
+  * @brief  Disable HSI oscillator
+  * @rmtoll CR           HSION         LL_RCC_HSI_Disable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_HSI_Disable(void)
+{
+  CLEAR_BIT(RCC->CR, RCC_CR_HSION);
+}
+
+/**
+  * @brief  Check if HSI clock is ready
+  * @rmtoll CR           HSIRDY        LL_RCC_HSI_IsReady
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_HSI_IsReady(void)
+{
+  return (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == (RCC_CR_HSIRDY));
+}
+
+/**
+  * @brief  Get HSI Calibration value
+  * @note When HSITRIM is written, HSICAL is updated with the sum of
+  *       HSITRIM and the factory trim value
+  * @rmtoll CR        HSICAL        LL_RCC_HSI_GetCalibration
+  * @retval Between Min_Data = 0x00 and Max_Data = 0xFF
+  */
+__STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibration(void)
+{
+  return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSICAL) >> RCC_CR_HSICAL_Pos);
+}
+
+/**
+  * @brief  Set HSI Calibration trimming
+  * @note user-programmable trimming value that is added to the HSICAL
+  * @note Default value is 16, which, when added to the HSICAL value,
+  *       should trim the HSI to 16 MHz +/- 1 %
+  * @rmtoll CR        HSITRIM       LL_RCC_HSI_SetCalibTrimming
+  * @param  Value Between Min_Data = 0 and Max_Data = 31
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_HSI_SetCalibTrimming(uint32_t Value)
+{
+  MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, Value << RCC_CR_HSITRIM_Pos);
+}
+
+/**
+  * @brief  Get HSI Calibration trimming
+  * @rmtoll CR        HSITRIM       LL_RCC_HSI_GetCalibTrimming
+  * @retval Between Min_Data = 0 and Max_Data = 31
+  */
+__STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibTrimming(void)
+{
+  return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSITRIM) >> RCC_CR_HSITRIM_Pos);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EF_LSE LSE
+  * @{
+  */
+
+/**
+  * @brief  Enable  Low Speed External (LSE) crystal.
+  * @rmtoll BDCR         LSEON         LL_RCC_LSE_Enable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_LSE_Enable(void)
+{
+  SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);
+}
+
+/**
+  * @brief  Disable  Low Speed External (LSE) crystal.
+  * @rmtoll BDCR         LSEON         LL_RCC_LSE_Disable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_LSE_Disable(void)
+{
+  CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);
+}
+
+/**
+  * @brief  Enable external clock source (LSE bypass).
+  * @rmtoll BDCR         LSEBYP        LL_RCC_LSE_EnableBypass
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_LSE_EnableBypass(void)
+{
+  SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
+}
+
+/**
+  * @brief  Disable external clock source (LSE bypass).
+  * @rmtoll BDCR         LSEBYP        LL_RCC_LSE_DisableBypass
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_LSE_DisableBypass(void)
+{
+  CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
+}
+
+/**
+  * @brief  Check if LSE oscillator Ready
+  * @rmtoll BDCR         LSERDY        LL_RCC_LSE_IsReady
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_LSE_IsReady(void)
+{
+  return (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == (RCC_BDCR_LSERDY));
+}
+
+#if defined(RCC_BDCR_LSEMOD)
+/**
+  * @brief  Enable LSE high drive mode.
+  * @note LSE high drive mode can be enabled only when the LSE clock is disabled
+  * @rmtoll BDCR         LSEMOD      LL_RCC_LSE_EnableHighDriveMode
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_LSE_EnableHighDriveMode(void)
+{
+  SET_BIT(RCC->BDCR, RCC_BDCR_LSEMOD);
+}
+
+/**
+  * @brief  Disable LSE high drive mode.
+  * @note LSE high drive mode can be disabled only when the LSE clock is disabled
+  * @rmtoll BDCR         LSEMOD      LL_RCC_LSE_DisableHighDriveMode
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_LSE_DisableHighDriveMode(void)
+{
+  CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEMOD);
+}
+#endif /* RCC_BDCR_LSEMOD */
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EF_LSI LSI
+  * @{
+  */
+
+/**
+  * @brief  Enable LSI Oscillator
+  * @rmtoll CSR          LSION         LL_RCC_LSI_Enable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_LSI_Enable(void)
+{
+  SET_BIT(RCC->CSR, RCC_CSR_LSION);
+}
+
+/**
+  * @brief  Disable LSI Oscillator
+  * @rmtoll CSR          LSION         LL_RCC_LSI_Disable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_LSI_Disable(void)
+{
+  CLEAR_BIT(RCC->CSR, RCC_CSR_LSION);
+}
+
+/**
+  * @brief  Check if LSI is Ready
+  * @rmtoll CSR          LSIRDY        LL_RCC_LSI_IsReady
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_LSI_IsReady(void)
+{
+  return (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == (RCC_CSR_LSIRDY));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EF_System System
+  * @{
+  */
+
+/**
+  * @brief  Configure the system clock source
+  * @rmtoll CFGR         SW            LL_RCC_SetSysClkSource
+  * @param  Source This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_SYS_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_SYS_CLKSOURCE_HSE
+  *         @arg @ref LL_RCC_SYS_CLKSOURCE_PLL
+  *         @arg @ref LL_RCC_SYS_CLKSOURCE_PLLR (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetSysClkSource(uint32_t Source)
+{
+  MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, Source);
+}
+
+/**
+  * @brief  Get the system clock source
+  * @rmtoll CFGR         SWS           LL_RCC_GetSysClkSource
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSI
+  *         @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSE
+  *         @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_PLL
+  *         @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_PLLR (*)
+  *
+  *         (*) value not defined in all devices.
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetSysClkSource(void)
+{
+  return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS));
+}
+
+/**
+  * @brief  Set AHB prescaler
+  * @rmtoll CFGR         HPRE          LL_RCC_SetAHBPrescaler
+  * @param  Prescaler This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_SYSCLK_DIV_1
+  *         @arg @ref LL_RCC_SYSCLK_DIV_2
+  *         @arg @ref LL_RCC_SYSCLK_DIV_4
+  *         @arg @ref LL_RCC_SYSCLK_DIV_8
+  *         @arg @ref LL_RCC_SYSCLK_DIV_16
+  *         @arg @ref LL_RCC_SYSCLK_DIV_64
+  *         @arg @ref LL_RCC_SYSCLK_DIV_128
+  *         @arg @ref LL_RCC_SYSCLK_DIV_256
+  *         @arg @ref LL_RCC_SYSCLK_DIV_512
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetAHBPrescaler(uint32_t Prescaler)
+{
+  MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, Prescaler);
+}
+
+/**
+  * @brief  Set APB1 prescaler
+  * @rmtoll CFGR         PPRE1         LL_RCC_SetAPB1Prescaler
+  * @param  Prescaler This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_APB1_DIV_1
+  *         @arg @ref LL_RCC_APB1_DIV_2
+  *         @arg @ref LL_RCC_APB1_DIV_4
+  *         @arg @ref LL_RCC_APB1_DIV_8
+  *         @arg @ref LL_RCC_APB1_DIV_16
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetAPB1Prescaler(uint32_t Prescaler)
+{
+  MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, Prescaler);
+}
+
+/**
+  * @brief  Set APB2 prescaler
+  * @rmtoll CFGR         PPRE2         LL_RCC_SetAPB2Prescaler
+  * @param  Prescaler This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_APB2_DIV_1
+  *         @arg @ref LL_RCC_APB2_DIV_2
+  *         @arg @ref LL_RCC_APB2_DIV_4
+  *         @arg @ref LL_RCC_APB2_DIV_8
+  *         @arg @ref LL_RCC_APB2_DIV_16
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetAPB2Prescaler(uint32_t Prescaler)
+{
+  MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, Prescaler);
+}
+
+/**
+  * @brief  Get AHB prescaler
+  * @rmtoll CFGR         HPRE          LL_RCC_GetAHBPrescaler
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_SYSCLK_DIV_1
+  *         @arg @ref LL_RCC_SYSCLK_DIV_2
+  *         @arg @ref LL_RCC_SYSCLK_DIV_4
+  *         @arg @ref LL_RCC_SYSCLK_DIV_8
+  *         @arg @ref LL_RCC_SYSCLK_DIV_16
+  *         @arg @ref LL_RCC_SYSCLK_DIV_64
+  *         @arg @ref LL_RCC_SYSCLK_DIV_128
+  *         @arg @ref LL_RCC_SYSCLK_DIV_256
+  *         @arg @ref LL_RCC_SYSCLK_DIV_512
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetAHBPrescaler(void)
+{
+  return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_HPRE));
+}
+
+/**
+  * @brief  Get APB1 prescaler
+  * @rmtoll CFGR         PPRE1         LL_RCC_GetAPB1Prescaler
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_APB1_DIV_1
+  *         @arg @ref LL_RCC_APB1_DIV_2
+  *         @arg @ref LL_RCC_APB1_DIV_4
+  *         @arg @ref LL_RCC_APB1_DIV_8
+  *         @arg @ref LL_RCC_APB1_DIV_16
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetAPB1Prescaler(void)
+{
+  return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1));
+}
+
+/**
+  * @brief  Get APB2 prescaler
+  * @rmtoll CFGR         PPRE2         LL_RCC_GetAPB2Prescaler
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_APB2_DIV_1
+  *         @arg @ref LL_RCC_APB2_DIV_2
+  *         @arg @ref LL_RCC_APB2_DIV_4
+  *         @arg @ref LL_RCC_APB2_DIV_8
+  *         @arg @ref LL_RCC_APB2_DIV_16
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetAPB2Prescaler(void)
+{
+  return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EF_MCO MCO
+  * @{
+  */
+
+#if defined(RCC_CFGR_MCO1EN)
+/**
+  * @brief  Enable MCO1 output
+  * @rmtoll CFGR           RCC_CFGR_MCO1EN         LL_RCC_MCO1_Enable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_MCO1_Enable(void)
+{
+  SET_BIT(RCC->CFGR, RCC_CFGR_MCO1EN);
+}
+
+/**
+  * @brief  Disable MCO1 output
+  * @rmtoll CFGR           RCC_CFGR_MCO1EN         LL_RCC_MCO1_Disable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_MCO1_Disable(void)
+{
+  CLEAR_BIT(RCC->CFGR, RCC_CFGR_MCO1EN);
+}
+#endif /* RCC_CFGR_MCO1EN */
+
+#if defined(RCC_CFGR_MCO2EN)
+/**
+  * @brief  Enable MCO2 output
+  * @rmtoll CFGR           RCC_CFGR_MCO2EN         LL_RCC_MCO2_Enable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_MCO2_Enable(void)
+{
+  SET_BIT(RCC->CFGR, RCC_CFGR_MCO2EN);
+}
+
+/**
+  * @brief  Disable MCO2 output
+  * @rmtoll CFGR           RCC_CFGR_MCO2EN         LL_RCC_MCO2_Disable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_MCO2_Disable(void)
+{
+  CLEAR_BIT(RCC->CFGR, RCC_CFGR_MCO2EN);
+}
+#endif /* RCC_CFGR_MCO2EN */
+
+/**
+  * @brief  Configure MCOx
+  * @rmtoll CFGR         MCO1          LL_RCC_ConfigMCO\n
+  *         CFGR         MCO1PRE       LL_RCC_ConfigMCO\n
+  *         CFGR         MCO2          LL_RCC_ConfigMCO\n
+  *         CFGR         MCO2PRE       LL_RCC_ConfigMCO
+  * @param  MCOxSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_MCO1SOURCE_HSI
+  *         @arg @ref LL_RCC_MCO1SOURCE_LSE
+  *         @arg @ref LL_RCC_MCO1SOURCE_HSE
+  *         @arg @ref LL_RCC_MCO1SOURCE_PLLCLK
+  *         @arg @ref LL_RCC_MCO2SOURCE_SYSCLK
+  *         @arg @ref LL_RCC_MCO2SOURCE_PLLI2S
+  *         @arg @ref LL_RCC_MCO2SOURCE_HSE
+  *         @arg @ref LL_RCC_MCO2SOURCE_PLLCLK
+  * @param  MCOxPrescaler This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_MCO1_DIV_1
+  *         @arg @ref LL_RCC_MCO1_DIV_2
+  *         @arg @ref LL_RCC_MCO1_DIV_3
+  *         @arg @ref LL_RCC_MCO1_DIV_4
+  *         @arg @ref LL_RCC_MCO1_DIV_5
+  *         @arg @ref LL_RCC_MCO2_DIV_1
+  *         @arg @ref LL_RCC_MCO2_DIV_2
+  *         @arg @ref LL_RCC_MCO2_DIV_3
+  *         @arg @ref LL_RCC_MCO2_DIV_4
+  *         @arg @ref LL_RCC_MCO2_DIV_5
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_ConfigMCO(uint32_t MCOxSource, uint32_t MCOxPrescaler)
+{
+  MODIFY_REG(RCC->CFGR, (MCOxSource & 0xFFFF0000U) | (MCOxPrescaler & 0xFFFF0000U),  (MCOxSource << 16U) | (MCOxPrescaler << 16U));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EF_Peripheral_Clock_Source Peripheral Clock Source
+  * @{
+  */
+#if defined(FMPI2C1)
+/**
+  * @brief  Configure FMPI2C clock source
+  * @rmtoll DCKCFGR2        FMPI2C1SEL       LL_RCC_SetFMPI2CClockSource
+  * @param  FMPI2CxSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_FMPI2C1_CLKSOURCE_PCLK1
+  *         @arg @ref LL_RCC_FMPI2C1_CLKSOURCE_SYSCLK
+  *         @arg @ref LL_RCC_FMPI2C1_CLKSOURCE_HSI
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetFMPI2CClockSource(uint32_t FMPI2CxSource)
+{
+  MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL, FMPI2CxSource);
+}
+#endif /* FMPI2C1 */
+
+#if defined(LPTIM1)
+/**
+  * @brief  Configure LPTIMx clock source
+  * @rmtoll DCKCFGR2        LPTIM1SEL     LL_RCC_SetLPTIMClockSource
+  * @param  LPTIMxSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1
+  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI
+  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetLPTIMClockSource(uint32_t LPTIMxSource)
+{
+  MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL, LPTIMxSource);
+}
+#endif /* LPTIM1 */
+
+#if defined(SAI1)
+/**
+  * @brief  Configure SAIx clock source
+  * @rmtoll DCKCFGR        SAI1SRC       LL_RCC_SetSAIClockSource\n
+  *         DCKCFGR        SAI2SRC       LL_RCC_SetSAIClockSource\n
+  *         DCKCFGR        SAI1ASRC      LL_RCC_SetSAIClockSource\n
+  *         DCKCFGR        SAI1BSRC      LL_RCC_SetSAIClockSource
+  * @param  SAIxSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLSAI (*)
+  *         @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLI2S (*)
+  *         @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL (*)
+  *         @arg @ref LL_RCC_SAI1_CLKSOURCE_PIN (*)
+  *         @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLSAI (*)
+  *         @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLI2S (*)
+  *         @arg @ref LL_RCC_SAI2_CLKSOURCE_PLL  (*)
+  *         @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLSRC (*)
+  *         @arg @ref LL_RCC_SAI1_A_CLKSOURCE_PLLSAI (*)
+  *         @arg @ref LL_RCC_SAI1_A_CLKSOURCE_PLLI2S (*)
+  *         @arg @ref LL_RCC_SAI1_A_CLKSOURCE_PIN (*)
+  *         @arg @ref LL_RCC_SAI1_A_CLKSOURCE_PLL (*)
+  *         @arg @ref LL_RCC_SAI1_A_CLKSOURCE_PLLSRC (*)
+  *         @arg @ref LL_RCC_SAI1_B_CLKSOURCE_PLLSAI (*)
+  *         @arg @ref LL_RCC_SAI1_B_CLKSOURCE_PLLI2S (*)
+  *         @arg @ref LL_RCC_SAI1_B_CLKSOURCE_PIN (*)
+  *         @arg @ref LL_RCC_SAI1_B_CLKSOURCE_PLL  (*)
+  *         @arg @ref LL_RCC_SAI1_B_CLKSOURCE_PLLSRC (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetSAIClockSource(uint32_t SAIxSource)
+{
+  MODIFY_REG(RCC->DCKCFGR, (SAIxSource & 0xFFFF0000U), (SAIxSource << 16U));
+}
+#endif /* SAI1 */
+
+#if defined(RCC_DCKCFGR_SDIOSEL) || defined(RCC_DCKCFGR2_SDIOSEL)
+/**
+  * @brief  Configure SDIO clock source
+  * @rmtoll DCKCFGR         SDIOSEL      LL_RCC_SetSDIOClockSource\n
+  *         DCKCFGR2        SDIOSEL      LL_RCC_SetSDIOClockSource
+  * @param  SDIOxSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_SDIO_CLKSOURCE_PLL48CLK
+  *         @arg @ref LL_RCC_SDIO_CLKSOURCE_SYSCLK
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetSDIOClockSource(uint32_t SDIOxSource)
+{
+#if defined(RCC_DCKCFGR_SDIOSEL)
+  MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SDIOSEL, SDIOxSource);
+#else
+  MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_SDIOSEL, SDIOxSource);
+#endif /* RCC_DCKCFGR_SDIOSEL */
+}
+#endif /* RCC_DCKCFGR_SDIOSEL || RCC_DCKCFGR2_SDIOSEL */
+
+#if defined(RCC_DCKCFGR_CK48MSEL) || defined(RCC_DCKCFGR2_CK48MSEL)
+/**
+  * @brief  Configure 48Mhz domain clock source
+  * @rmtoll DCKCFGR         CK48MSEL      LL_RCC_SetCK48MClockSource\n
+  *         DCKCFGR2        CK48MSEL      LL_RCC_SetCK48MClockSource
+  * @param  CK48MxSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_CK48M_CLKSOURCE_PLL
+  *         @arg @ref LL_RCC_CK48M_CLKSOURCE_PLLSAI (*)
+  *         @arg @ref LL_RCC_CK48M_CLKSOURCE_PLLI2S (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetCK48MClockSource(uint32_t CK48MxSource)
+{
+#if defined(RCC_DCKCFGR_CK48MSEL)
+  MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CK48MSEL, CK48MxSource);
+#else
+  MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL, CK48MxSource);
+#endif /* RCC_DCKCFGR_CK48MSEL */
+}
+
+#if defined(RNG)
+/**
+  * @brief  Configure RNG clock source
+  * @rmtoll DCKCFGR         CK48MSEL      LL_RCC_SetRNGClockSource\n
+  *         DCKCFGR2        CK48MSEL      LL_RCC_SetRNGClockSource
+  * @param  RNGxSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_RNG_CLKSOURCE_PLL
+  *         @arg @ref LL_RCC_RNG_CLKSOURCE_PLLSAI (*)
+  *         @arg @ref LL_RCC_RNG_CLKSOURCE_PLLI2S (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetRNGClockSource(uint32_t RNGxSource)
+{
+#if defined(RCC_DCKCFGR_CK48MSEL)
+  MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CK48MSEL, RNGxSource);
+#else
+  MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL, RNGxSource);
+#endif /* RCC_DCKCFGR_CK48MSEL */
+}
+#endif /* RNG */
+
+#if defined(USB_OTG_FS) || defined(USB_OTG_HS)
+/**
+  * @brief  Configure USB clock source
+  * @rmtoll DCKCFGR         CK48MSEL      LL_RCC_SetUSBClockSource\n
+  *         DCKCFGR2        CK48MSEL      LL_RCC_SetUSBClockSource
+  * @param  USBxSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_USB_CLKSOURCE_PLL
+  *         @arg @ref LL_RCC_USB_CLKSOURCE_PLLSAI (*)
+  *         @arg @ref LL_RCC_USB_CLKSOURCE_PLLI2S (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetUSBClockSource(uint32_t USBxSource)
+{
+#if defined(RCC_DCKCFGR_CK48MSEL)
+  MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CK48MSEL, USBxSource);
+#else
+  MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL, USBxSource);
+#endif /* RCC_DCKCFGR_CK48MSEL */
+}
+#endif /* USB_OTG_FS || USB_OTG_HS */
+#endif /* RCC_DCKCFGR_CK48MSEL || RCC_DCKCFGR2_CK48MSEL */
+
+#if defined(CEC)
+/**
+  * @brief  Configure CEC clock source
+  * @rmtoll DCKCFGR2         CECSEL        LL_RCC_SetCECClockSource
+  * @param  Source This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_CEC_CLKSOURCE_HSI_DIV488
+  *         @arg @ref LL_RCC_CEC_CLKSOURCE_LSE
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetCECClockSource(uint32_t Source)
+{
+  MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CECSEL, Source);
+}
+#endif /* CEC */
+
+/**
+  * @brief  Configure I2S clock source
+  * @rmtoll CFGR         I2SSRC        LL_RCC_SetI2SClockSource\n
+  *         DCKCFGR      I2SSRC        LL_RCC_SetI2SClockSource\n
+  *         DCKCFGR      I2S1SRC       LL_RCC_SetI2SClockSource\n
+  *         DCKCFGR      I2S2SRC       LL_RCC_SetI2SClockSource
+  * @param  Source This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_I2S1_CLKSOURCE_PLLI2S (*)
+  *         @arg @ref LL_RCC_I2S1_CLKSOURCE_PIN
+  *         @arg @ref LL_RCC_I2S1_CLKSOURCE_PLL (*)
+  *         @arg @ref LL_RCC_I2S1_CLKSOURCE_PLLSRC (*)
+  *         @arg @ref LL_RCC_I2S2_CLKSOURCE_PLLI2S (*)
+  *         @arg @ref LL_RCC_I2S2_CLKSOURCE_PIN (*)
+  *         @arg @ref LL_RCC_I2S2_CLKSOURCE_PLL (*)
+  *         @arg @ref LL_RCC_I2S2_CLKSOURCE_PLLSRC (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetI2SClockSource(uint32_t Source)
+{
+#if defined(RCC_CFGR_I2SSRC)
+  MODIFY_REG(RCC->CFGR, RCC_CFGR_I2SSRC, Source);
+#else
+  MODIFY_REG(RCC->DCKCFGR, (Source & 0xFFFF0000U), (Source << 16U));
+#endif /* RCC_CFGR_I2SSRC */
+}
+
+#if defined(DSI)
+/**
+  * @brief  Configure DSI clock source
+  * @rmtoll DCKCFGR         DSISEL        LL_RCC_SetDSIClockSource
+  * @param  Source This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_DSI_CLKSOURCE_PHY
+  *         @arg @ref LL_RCC_DSI_CLKSOURCE_PLL
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetDSIClockSource(uint32_t Source)
+{
+  MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_DSISEL, Source);
+}
+#endif /* DSI */
+
+#if defined(DFSDM1_Channel0)
+/**
+  * @brief  Configure DFSDM Audio clock source
+  * @rmtoll DCKCFGR          CKDFSDM1ASEL        LL_RCC_SetDFSDMAudioClockSource\n
+  *         DCKCFGR          CKDFSDM2ASEL        LL_RCC_SetDFSDMAudioClockSource
+  * @param  Source This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE_I2S1
+  *         @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE_I2S2
+  *         @arg @ref LL_RCC_DFSDM2_AUDIO_CLKSOURCE_I2S1 (*)
+  *         @arg @ref LL_RCC_DFSDM2_AUDIO_CLKSOURCE_I2S2 (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetDFSDMAudioClockSource(uint32_t Source)
+{
+  MODIFY_REG(RCC->DCKCFGR, (Source & 0x0000FFFFU), (Source >> 16U));
+}
+
+/**
+  * @brief  Configure DFSDM Kernel clock source
+  * @rmtoll DCKCFGR         CKDFSDM1SEL        LL_RCC_SetDFSDMClockSource
+  * @param  Source This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_DFSDM1_CLKSOURCE_PCLK2
+  *         @arg @ref LL_RCC_DFSDM1_CLKSOURCE_SYSCLK
+  *         @arg @ref LL_RCC_DFSDM2_CLKSOURCE_PCLK2 (*)
+  *         @arg @ref LL_RCC_DFSDM2_CLKSOURCE_SYSCLK (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetDFSDMClockSource(uint32_t Source)
+{
+  MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM1SEL, Source);
+}
+#endif /* DFSDM1_Channel0 */
+
+#if defined(SPDIFRX)
+/**
+  * @brief  Configure SPDIFRX clock source
+  * @rmtoll DCKCFGR2         SPDIFRXSEL      LL_RCC_SetSPDIFRXClockSource
+  * @param  SPDIFRXxSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_SPDIFRX1_CLKSOURCE_PLL
+  *         @arg @ref LL_RCC_SPDIFRX1_CLKSOURCE_PLLI2S
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetSPDIFRXClockSource(uint32_t SPDIFRXxSource)
+{
+  MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_SPDIFRXSEL, SPDIFRXxSource);
+}
+#endif /* SPDIFRX */
+
+#if defined(FMPI2C1)
+/**
+  * @brief  Get FMPI2C clock source
+  * @rmtoll DCKCFGR2        FMPI2C1SEL       LL_RCC_GetFMPI2CClockSource
+  * @param  FMPI2Cx This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_FMPI2C1_CLKSOURCE
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_FMPI2C1_CLKSOURCE_PCLK1
+  *         @arg @ref LL_RCC_FMPI2C1_CLKSOURCE_SYSCLK
+  *         @arg @ref LL_RCC_FMPI2C1_CLKSOURCE_HSI
+ */
+__STATIC_INLINE uint32_t LL_RCC_GetFMPI2CClockSource(uint32_t FMPI2Cx)
+{
+  return (uint32_t)(READ_BIT(RCC->DCKCFGR2, FMPI2Cx));
+}
+#endif /* FMPI2C1 */
+
+#if defined(LPTIM1)
+/**
+  * @brief  Get LPTIMx clock source
+  * @rmtoll DCKCFGR2        LPTIM1SEL     LL_RCC_GetLPTIMClockSource
+  * @param  LPTIMx This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1
+  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI
+  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetLPTIMClockSource(uint32_t LPTIMx)
+{
+  return (uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL));
+}
+#endif /* LPTIM1 */
+
+#if defined(SAI1)
+/**
+  * @brief  Get SAIx clock source
+  * @rmtoll DCKCFGR         SAI1SEL       LL_RCC_GetSAIClockSource\n
+  *         DCKCFGR         SAI2SEL       LL_RCC_GetSAIClockSource\n
+  *         DCKCFGR         SAI1ASRC      LL_RCC_GetSAIClockSource\n
+  *         DCKCFGR         SAI1BSRC      LL_RCC_GetSAIClockSource
+  * @param  SAIx This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_SAI1_CLKSOURCE (*)
+  *         @arg @ref LL_RCC_SAI2_CLKSOURCE (*)
+  *         @arg @ref LL_RCC_SAI1_A_CLKSOURCE (*)
+  *         @arg @ref LL_RCC_SAI1_B_CLKSOURCE (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLSAI (*)
+  *         @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLI2S (*)
+  *         @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL (*)
+  *         @arg @ref LL_RCC_SAI1_CLKSOURCE_PIN (*)
+  *         @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLSAI (*)
+  *         @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLI2S (*)
+  *         @arg @ref LL_RCC_SAI2_CLKSOURCE_PLL  (*)
+  *         @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLSRC (*)
+  *         @arg @ref LL_RCC_SAI1_A_CLKSOURCE_PLLSAI (*)
+  *         @arg @ref LL_RCC_SAI1_A_CLKSOURCE_PLLI2S (*)
+  *         @arg @ref LL_RCC_SAI1_A_CLKSOURCE_PIN (*)
+  *         @arg @ref LL_RCC_SAI1_A_CLKSOURCE_PLL (*)
+  *         @arg @ref LL_RCC_SAI1_A_CLKSOURCE_PLLSRC (*)
+  *         @arg @ref LL_RCC_SAI1_B_CLKSOURCE_PLLSAI (*)
+  *         @arg @ref LL_RCC_SAI1_B_CLKSOURCE_PLLI2S (*)
+  *         @arg @ref LL_RCC_SAI1_B_CLKSOURCE_PIN (*)
+  *         @arg @ref LL_RCC_SAI1_B_CLKSOURCE_PLL  (*)
+  *         @arg @ref LL_RCC_SAI1_B_CLKSOURCE_PLLSRC (*)
+  *
+  *         (*) value not defined in all devices.
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetSAIClockSource(uint32_t SAIx)
+{
+  return (uint32_t)(READ_BIT(RCC->DCKCFGR, SAIx) >> 16U | SAIx);
+}
+#endif /* SAI1 */
+
+#if defined(RCC_DCKCFGR_SDIOSEL) || defined(RCC_DCKCFGR2_SDIOSEL)
+/**
+  * @brief  Get SDIOx clock source
+  * @rmtoll DCKCFGR        SDIOSEL      LL_RCC_GetSDIOClockSource\n
+  *         DCKCFGR2       SDIOSEL      LL_RCC_GetSDIOClockSource
+  * @param  SDIOx This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_SDIO_CLKSOURCE
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_SDIO_CLKSOURCE_PLL48CLK
+  *         @arg @ref LL_RCC_SDIO_CLKSOURCE_SYSCLK
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetSDIOClockSource(uint32_t SDIOx)
+{
+#if defined(RCC_DCKCFGR_SDIOSEL)
+  return (uint32_t)(READ_BIT(RCC->DCKCFGR, SDIOx));
+#else
+  return (uint32_t)(READ_BIT(RCC->DCKCFGR2, SDIOx));
+#endif /* RCC_DCKCFGR_SDIOSEL */
+}
+#endif /* RCC_DCKCFGR_SDIOSEL || RCC_DCKCFGR2_SDIOSEL */
+
+#if defined(RCC_DCKCFGR_CK48MSEL) || defined(RCC_DCKCFGR2_CK48MSEL)
+/**
+  * @brief  Get 48Mhz domain clock source
+  * @rmtoll DCKCFGR         CK48MSEL      LL_RCC_GetCK48MClockSource\n
+  *         DCKCFGR2        CK48MSEL      LL_RCC_GetCK48MClockSource
+  * @param  CK48Mx This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_CK48M_CLKSOURCE
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_CK48M_CLKSOURCE_PLL
+  *         @arg @ref LL_RCC_CK48M_CLKSOURCE_PLLSAI (*)
+  *         @arg @ref LL_RCC_CK48M_CLKSOURCE_PLLI2S (*)
+  *
+  *         (*) value not defined in all devices.
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetCK48MClockSource(uint32_t CK48Mx)
+{
+#if defined(RCC_DCKCFGR_CK48MSEL)
+  return (uint32_t)(READ_BIT(RCC->DCKCFGR, CK48Mx));
+#else
+  return (uint32_t)(READ_BIT(RCC->DCKCFGR2, CK48Mx));
+#endif /* RCC_DCKCFGR_CK48MSEL */
+}
+
+#if defined(RNG)
+/**
+  * @brief  Get RNGx clock source
+  * @rmtoll DCKCFGR         CK48MSEL      LL_RCC_GetRNGClockSource\n
+  *         DCKCFGR2        CK48MSEL      LL_RCC_GetRNGClockSource
+  * @param  RNGx This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_RNG_CLKSOURCE
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_RNG_CLKSOURCE_PLL
+  *         @arg @ref LL_RCC_RNG_CLKSOURCE_PLLSAI (*)
+  *         @arg @ref LL_RCC_RNG_CLKSOURCE_PLLI2S (*)
+  *
+  *         (*) value not defined in all devices.
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetRNGClockSource(uint32_t RNGx)
+{
+#if defined(RCC_DCKCFGR_CK48MSEL)
+  return (uint32_t)(READ_BIT(RCC->DCKCFGR, RNGx));
+#else
+  return (uint32_t)(READ_BIT(RCC->DCKCFGR2, RNGx));
+#endif /* RCC_DCKCFGR_CK48MSEL */
+}
+#endif /* RNG */
+
+#if defined(USB_OTG_FS) || defined(USB_OTG_HS)
+/**
+  * @brief  Get USBx clock source
+  * @rmtoll DCKCFGR         CK48MSEL      LL_RCC_GetUSBClockSource\n
+  *         DCKCFGR2        CK48MSEL      LL_RCC_GetUSBClockSource
+  * @param  USBx This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_USB_CLKSOURCE
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_USB_CLKSOURCE_PLL
+  *         @arg @ref LL_RCC_USB_CLKSOURCE_PLLSAI (*)
+  *         @arg @ref LL_RCC_USB_CLKSOURCE_PLLI2S (*)
+  *
+  *         (*) value not defined in all devices.
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetUSBClockSource(uint32_t USBx)
+{
+#if defined(RCC_DCKCFGR_CK48MSEL)
+  return (uint32_t)(READ_BIT(RCC->DCKCFGR, USBx));
+#else
+  return (uint32_t)(READ_BIT(RCC->DCKCFGR2, USBx));
+#endif /* RCC_DCKCFGR_CK48MSEL */
+}
+#endif /* USB_OTG_FS || USB_OTG_HS */
+#endif /* RCC_DCKCFGR_CK48MSEL || RCC_DCKCFGR2_CK48MSEL */
+
+#if defined(CEC)
+/**
+  * @brief  Get CEC Clock Source
+  * @rmtoll DCKCFGR2         CECSEL        LL_RCC_GetCECClockSource
+  * @param  CECx This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_CEC_CLKSOURCE
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_CEC_CLKSOURCE_HSI_DIV488
+  *         @arg @ref LL_RCC_CEC_CLKSOURCE_LSE
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetCECClockSource(uint32_t CECx)
+{
+  return (uint32_t)(READ_BIT(RCC->DCKCFGR2, CECx));
+}
+#endif /* CEC */
+
+/**
+  * @brief  Get I2S Clock Source
+  * @rmtoll CFGR         I2SSRC        LL_RCC_GetI2SClockSource\n
+  *         DCKCFGR      I2SSRC        LL_RCC_GetI2SClockSource\n
+  *         DCKCFGR      I2S1SRC       LL_RCC_GetI2SClockSource\n
+  *         DCKCFGR      I2S2SRC       LL_RCC_GetI2SClockSource
+  * @param  I2Sx This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_I2S1_CLKSOURCE
+  *         @arg @ref LL_RCC_I2S2_CLKSOURCE (*)
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_I2S1_CLKSOURCE_PLLI2S (*)
+  *         @arg @ref LL_RCC_I2S1_CLKSOURCE_PIN
+  *         @arg @ref LL_RCC_I2S1_CLKSOURCE_PLL (*)
+  *         @arg @ref LL_RCC_I2S1_CLKSOURCE_PLLSRC (*)
+  *         @arg @ref LL_RCC_I2S2_CLKSOURCE_PLLI2S (*)
+  *         @arg @ref LL_RCC_I2S2_CLKSOURCE_PIN (*)
+  *         @arg @ref LL_RCC_I2S2_CLKSOURCE_PLL (*)
+  *         @arg @ref LL_RCC_I2S2_CLKSOURCE_PLLSRC (*)
+  *
+  *         (*) value not defined in all devices.
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetI2SClockSource(uint32_t I2Sx)
+{
+#if defined(RCC_CFGR_I2SSRC)
+  return (uint32_t)(READ_BIT(RCC->CFGR, I2Sx));
+#else
+  return (uint32_t)(READ_BIT(RCC->DCKCFGR, I2Sx) >> 16U | I2Sx);
+#endif /* RCC_CFGR_I2SSRC */
+}
+
+#if defined(DFSDM1_Channel0)
+/**
+  * @brief  Get DFSDM Audio Clock Source
+  * @rmtoll DCKCFGR          CKDFSDM1ASEL        LL_RCC_GetDFSDMAudioClockSource\n
+  *         DCKCFGR          CKDFSDM2ASEL        LL_RCC_GetDFSDMAudioClockSource
+  * @param  DFSDMx This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE
+  *         @arg @ref LL_RCC_DFSDM2_AUDIO_CLKSOURCE (*)
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE_I2S1
+  *         @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE_I2S2
+  *         @arg @ref LL_RCC_DFSDM2_AUDIO_CLKSOURCE_I2S1 (*)
+  *         @arg @ref LL_RCC_DFSDM2_AUDIO_CLKSOURCE_I2S2 (*)
+  *
+  *         (*) value not defined in all devices.
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetDFSDMAudioClockSource(uint32_t DFSDMx)
+{
+  return (uint32_t)(READ_BIT(RCC->DCKCFGR, DFSDMx) << 16U | DFSDMx);
+}
+
+/**
+  * @brief  Get DFSDM Audio Clock Source
+  * @rmtoll DCKCFGR         CKDFSDM1SEL        LL_RCC_GetDFSDMClockSource
+  * @param  DFSDMx This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_DFSDM1_CLKSOURCE
+  *         @arg @ref LL_RCC_DFSDM2_CLKSOURCE (*)
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_DFSDM1_CLKSOURCE_PCLK2
+  *         @arg @ref LL_RCC_DFSDM1_CLKSOURCE_SYSCLK
+  *         @arg @ref LL_RCC_DFSDM2_CLKSOURCE_PCLK2 (*)
+  *         @arg @ref LL_RCC_DFSDM2_CLKSOURCE_SYSCLK (*)
+  *
+  *         (*) value not defined in all devices.
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetDFSDMClockSource(uint32_t DFSDMx)
+{
+  return (uint32_t)(READ_BIT(RCC->DCKCFGR, DFSDMx));
+}
+#endif /* DFSDM1_Channel0 */
+
+#if defined(SPDIFRX)
+/**
+  * @brief  Get SPDIFRX clock source
+  * @rmtoll DCKCFGR2         SPDIFRXSEL      LL_RCC_GetSPDIFRXClockSource
+  * @param  SPDIFRXx This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_SPDIFRX1_CLKSOURCE
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_SPDIFRX1_CLKSOURCE_PLL
+  *         @arg @ref LL_RCC_SPDIFRX1_CLKSOURCE_PLLI2S
+  *
+  *         (*) value not defined in all devices.
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetSPDIFRXClockSource(uint32_t SPDIFRXx)
+{
+  return (uint32_t)(READ_BIT(RCC->DCKCFGR2, SPDIFRXx));
+}
+#endif /* SPDIFRX */
+
+#if defined(DSI)
+/**
+  * @brief  Get DSI Clock Source
+  * @rmtoll DCKCFGR         DSISEL        LL_RCC_GetDSIClockSource
+  * @param  DSIx This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_DSI_CLKSOURCE
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_DSI_CLKSOURCE_PHY
+  *         @arg @ref LL_RCC_DSI_CLKSOURCE_PLL
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetDSIClockSource(uint32_t DSIx)
+{
+  return (uint32_t)(READ_BIT(RCC->DCKCFGR, DSIx));
+}
+#endif /* DSI */
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EF_RTC RTC
+  * @{
+  */
+
+/**
+  * @brief  Set RTC Clock Source
+  * @note Once the RTC clock source has been selected, it cannot be changed anymore unless
+  *       the Backup domain is reset, or unless a failure is detected on LSE (LSECSSD is
+  *       set). The BDRST bit can be used to reset them.
+  * @rmtoll BDCR         RTCSEL        LL_RCC_SetRTCClockSource
+  * @param  Source This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_RTC_CLKSOURCE_NONE
+  *         @arg @ref LL_RCC_RTC_CLKSOURCE_LSE
+  *         @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
+  *         @arg @ref LL_RCC_RTC_CLKSOURCE_HSE
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetRTCClockSource(uint32_t Source)
+{
+  MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, Source);
+}
+
+/**
+  * @brief  Get RTC Clock Source
+  * @rmtoll BDCR         RTCSEL        LL_RCC_GetRTCClockSource
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_RTC_CLKSOURCE_NONE
+  *         @arg @ref LL_RCC_RTC_CLKSOURCE_LSE
+  *         @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
+  *         @arg @ref LL_RCC_RTC_CLKSOURCE_HSE
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetRTCClockSource(void)
+{
+  return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL));
+}
+
+/**
+  * @brief  Enable RTC
+  * @rmtoll BDCR         RTCEN         LL_RCC_EnableRTC
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_EnableRTC(void)
+{
+  SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN);
+}
+
+/**
+  * @brief  Disable RTC
+  * @rmtoll BDCR         RTCEN         LL_RCC_DisableRTC
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_DisableRTC(void)
+{
+  CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN);
+}
+
+/**
+  * @brief  Check if RTC has been enabled or not
+  * @rmtoll BDCR         RTCEN         LL_RCC_IsEnabledRTC
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsEnabledRTC(void)
+{
+  return (READ_BIT(RCC->BDCR, RCC_BDCR_RTCEN) == (RCC_BDCR_RTCEN));
+}
+
+/**
+  * @brief  Force the Backup domain reset
+  * @rmtoll BDCR         BDRST         LL_RCC_ForceBackupDomainReset
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_ForceBackupDomainReset(void)
+{
+  SET_BIT(RCC->BDCR, RCC_BDCR_BDRST);
+}
+
+/**
+  * @brief  Release the Backup domain reset
+  * @rmtoll BDCR         BDRST         LL_RCC_ReleaseBackupDomainReset
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_ReleaseBackupDomainReset(void)
+{
+  CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST);
+}
+
+/**
+  * @brief  Set HSE Prescalers for RTC Clock
+  * @rmtoll CFGR         RTCPRE        LL_RCC_SetRTC_HSEPrescaler
+  * @param  Prescaler This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_RTC_NOCLOCK
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_2
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_3
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_4
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_5
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_6
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_7
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_8
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_9
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_10
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_11
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_12
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_13
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_14
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_15
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_16
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_17
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_18
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_19
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_20
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_21
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_22
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_23
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_24
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_25
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_26
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_27
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_28
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_29
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_30
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_31
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetRTC_HSEPrescaler(uint32_t Prescaler)
+{
+  MODIFY_REG(RCC->CFGR, RCC_CFGR_RTCPRE, Prescaler);
+}
+
+/**
+  * @brief  Get HSE Prescalers for RTC Clock
+  * @rmtoll CFGR         RTCPRE        LL_RCC_GetRTC_HSEPrescaler
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_RTC_NOCLOCK
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_2
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_3
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_4
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_5
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_6
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_7
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_8
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_9
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_10
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_11
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_12
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_13
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_14
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_15
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_16
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_17
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_18
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_19
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_20
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_21
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_22
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_23
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_24
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_25
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_26
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_27
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_28
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_29
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_30
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_31
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetRTC_HSEPrescaler(void)
+{
+  return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_RTCPRE));
+}
+
+/**
+  * @}
+  */
+
+#if defined(RCC_DCKCFGR_TIMPRE)
+/** @defgroup RCC_LL_EF_TIM_CLOCK_PRESCALER TIM
+  * @{
+  */
+
+/**
+  * @brief  Set Timers Clock Prescalers
+  * @rmtoll DCKCFGR         TIMPRE        LL_RCC_SetTIMPrescaler
+  * @param  Prescaler This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_TIM_PRESCALER_TWICE
+  *         @arg @ref LL_RCC_TIM_PRESCALER_FOUR_TIMES
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetTIMPrescaler(uint32_t Prescaler)
+{
+  MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_TIMPRE, Prescaler);
+}
+
+/**
+  * @brief  Get Timers Clock Prescalers
+  * @rmtoll DCKCFGR         TIMPRE        LL_RCC_GetTIMPrescaler
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_TIM_PRESCALER_TWICE
+  *         @arg @ref LL_RCC_TIM_PRESCALER_FOUR_TIMES
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetTIMPrescaler(void)
+{
+  return (uint32_t)(READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_TIMPRE));
+}
+
+/**
+  * @}
+  */
+#endif /* RCC_DCKCFGR_TIMPRE */
+
+/** @defgroup RCC_LL_EF_PLL PLL
+  * @{
+  */
+
+/**
+  * @brief  Enable PLL
+  * @rmtoll CR           PLLON         LL_RCC_PLL_Enable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL_Enable(void)
+{
+  SET_BIT(RCC->CR, RCC_CR_PLLON);
+}
+
+/**
+  * @brief  Disable PLL
+  * @note Cannot be disabled if the PLL clock is used as the system clock
+  * @rmtoll CR           PLLON         LL_RCC_PLL_Disable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL_Disable(void)
+{
+  CLEAR_BIT(RCC->CR, RCC_CR_PLLON);
+}
+
+/**
+  * @brief  Check if PLL Ready
+  * @rmtoll CR           PLLRDY        LL_RCC_PLL_IsReady
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLL_IsReady(void)
+{
+  return (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == (RCC_CR_PLLRDY));
+}
+
+/**
+  * @brief  Configure PLL used for SYSCLK Domain
+  * @note PLL Source and PLLM Divider can be written only when PLL,
+  *       PLLI2S and PLLSAI(*) are disabled
+  * @note PLLN/PLLP can be written only when PLL is disabled
+  * @rmtoll PLLCFGR      PLLSRC        LL_RCC_PLL_ConfigDomain_SYS\n
+  *         PLLCFGR      PLLM          LL_RCC_PLL_ConfigDomain_SYS\n
+  *         PLLCFGR      PLLN          LL_RCC_PLL_ConfigDomain_SYS\n
+  *         PLLCFGR      PLLR          LL_RCC_PLL_ConfigDomain_SYS\n
+  *         PLLCFGR      PLLP          LL_RCC_PLL_ConfigDomain_SYS
+  * @param  Source This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLSOURCE_HSI
+  *         @arg @ref LL_RCC_PLLSOURCE_HSE
+  * @param  PLLM This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLM_DIV_2
+  *         @arg @ref LL_RCC_PLLM_DIV_3
+  *         @arg @ref LL_RCC_PLLM_DIV_4
+  *         @arg @ref LL_RCC_PLLM_DIV_5
+  *         @arg @ref LL_RCC_PLLM_DIV_6
+  *         @arg @ref LL_RCC_PLLM_DIV_7
+  *         @arg @ref LL_RCC_PLLM_DIV_8
+  *         @arg @ref LL_RCC_PLLM_DIV_9
+  *         @arg @ref LL_RCC_PLLM_DIV_10
+  *         @arg @ref LL_RCC_PLLM_DIV_11
+  *         @arg @ref LL_RCC_PLLM_DIV_12
+  *         @arg @ref LL_RCC_PLLM_DIV_13
+  *         @arg @ref LL_RCC_PLLM_DIV_14
+  *         @arg @ref LL_RCC_PLLM_DIV_15
+  *         @arg @ref LL_RCC_PLLM_DIV_16
+  *         @arg @ref LL_RCC_PLLM_DIV_17
+  *         @arg @ref LL_RCC_PLLM_DIV_18
+  *         @arg @ref LL_RCC_PLLM_DIV_19
+  *         @arg @ref LL_RCC_PLLM_DIV_20
+  *         @arg @ref LL_RCC_PLLM_DIV_21
+  *         @arg @ref LL_RCC_PLLM_DIV_22
+  *         @arg @ref LL_RCC_PLLM_DIV_23
+  *         @arg @ref LL_RCC_PLLM_DIV_24
+  *         @arg @ref LL_RCC_PLLM_DIV_25
+  *         @arg @ref LL_RCC_PLLM_DIV_26
+  *         @arg @ref LL_RCC_PLLM_DIV_27
+  *         @arg @ref LL_RCC_PLLM_DIV_28
+  *         @arg @ref LL_RCC_PLLM_DIV_29
+  *         @arg @ref LL_RCC_PLLM_DIV_30
+  *         @arg @ref LL_RCC_PLLM_DIV_31
+  *         @arg @ref LL_RCC_PLLM_DIV_32
+  *         @arg @ref LL_RCC_PLLM_DIV_33
+  *         @arg @ref LL_RCC_PLLM_DIV_34
+  *         @arg @ref LL_RCC_PLLM_DIV_35
+  *         @arg @ref LL_RCC_PLLM_DIV_36
+  *         @arg @ref LL_RCC_PLLM_DIV_37
+  *         @arg @ref LL_RCC_PLLM_DIV_38
+  *         @arg @ref LL_RCC_PLLM_DIV_39
+  *         @arg @ref LL_RCC_PLLM_DIV_40
+  *         @arg @ref LL_RCC_PLLM_DIV_41
+  *         @arg @ref LL_RCC_PLLM_DIV_42
+  *         @arg @ref LL_RCC_PLLM_DIV_43
+  *         @arg @ref LL_RCC_PLLM_DIV_44
+  *         @arg @ref LL_RCC_PLLM_DIV_45
+  *         @arg @ref LL_RCC_PLLM_DIV_46
+  *         @arg @ref LL_RCC_PLLM_DIV_47
+  *         @arg @ref LL_RCC_PLLM_DIV_48
+  *         @arg @ref LL_RCC_PLLM_DIV_49
+  *         @arg @ref LL_RCC_PLLM_DIV_50
+  *         @arg @ref LL_RCC_PLLM_DIV_51
+  *         @arg @ref LL_RCC_PLLM_DIV_52
+  *         @arg @ref LL_RCC_PLLM_DIV_53
+  *         @arg @ref LL_RCC_PLLM_DIV_54
+  *         @arg @ref LL_RCC_PLLM_DIV_55
+  *         @arg @ref LL_RCC_PLLM_DIV_56
+  *         @arg @ref LL_RCC_PLLM_DIV_57
+  *         @arg @ref LL_RCC_PLLM_DIV_58
+  *         @arg @ref LL_RCC_PLLM_DIV_59
+  *         @arg @ref LL_RCC_PLLM_DIV_60
+  *         @arg @ref LL_RCC_PLLM_DIV_61
+  *         @arg @ref LL_RCC_PLLM_DIV_62
+  *         @arg @ref LL_RCC_PLLM_DIV_63
+  * @param  PLLN Between 50/192(*) and 432
+  *
+  *         (*) value not defined in all devices.
+  * @param  PLLP_R This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLP_DIV_2
+  *         @arg @ref LL_RCC_PLLP_DIV_4
+  *         @arg @ref LL_RCC_PLLP_DIV_6
+  *         @arg @ref LL_RCC_PLLP_DIV_8
+  *         @arg @ref LL_RCC_PLLR_DIV_2 (*)
+  *         @arg @ref LL_RCC_PLLR_DIV_3 (*)
+  *         @arg @ref LL_RCC_PLLR_DIV_4 (*)
+  *         @arg @ref LL_RCC_PLLR_DIV_5 (*)
+  *         @arg @ref LL_RCC_PLLR_DIV_6 (*)
+  *         @arg @ref LL_RCC_PLLR_DIV_7 (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SYS(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP_R)
+{
+  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN,
+             Source | PLLM | PLLN << RCC_PLLCFGR_PLLN_Pos);
+  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLP, PLLP_R);
+#if defined(RCC_PLLR_SYSCLK_SUPPORT)
+  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLR, PLLP_R);
+#endif /* RCC_PLLR_SYSCLK_SUPPORT */
+}
+
+/**
+  * @brief  Configure PLL used for 48Mhz domain clock
+  * @note PLL Source and PLLM Divider can be written only when PLL,
+  *       PLLI2S and PLLSAI(*) are disabled
+  * @note PLLN/PLLQ can be written only when PLL is disabled
+  * @note This  can be selected for USB, RNG, SDIO
+  * @rmtoll PLLCFGR      PLLSRC        LL_RCC_PLL_ConfigDomain_48M\n
+  *         PLLCFGR      PLLM          LL_RCC_PLL_ConfigDomain_48M\n
+  *         PLLCFGR      PLLN          LL_RCC_PLL_ConfigDomain_48M\n
+  *         PLLCFGR      PLLQ          LL_RCC_PLL_ConfigDomain_48M
+  * @param  Source This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLSOURCE_HSI
+  *         @arg @ref LL_RCC_PLLSOURCE_HSE
+  * @param  PLLM This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLM_DIV_2
+  *         @arg @ref LL_RCC_PLLM_DIV_3
+  *         @arg @ref LL_RCC_PLLM_DIV_4
+  *         @arg @ref LL_RCC_PLLM_DIV_5
+  *         @arg @ref LL_RCC_PLLM_DIV_6
+  *         @arg @ref LL_RCC_PLLM_DIV_7
+  *         @arg @ref LL_RCC_PLLM_DIV_8
+  *         @arg @ref LL_RCC_PLLM_DIV_9
+  *         @arg @ref LL_RCC_PLLM_DIV_10
+  *         @arg @ref LL_RCC_PLLM_DIV_11
+  *         @arg @ref LL_RCC_PLLM_DIV_12
+  *         @arg @ref LL_RCC_PLLM_DIV_13
+  *         @arg @ref LL_RCC_PLLM_DIV_14
+  *         @arg @ref LL_RCC_PLLM_DIV_15
+  *         @arg @ref LL_RCC_PLLM_DIV_16
+  *         @arg @ref LL_RCC_PLLM_DIV_17
+  *         @arg @ref LL_RCC_PLLM_DIV_18
+  *         @arg @ref LL_RCC_PLLM_DIV_19
+  *         @arg @ref LL_RCC_PLLM_DIV_20
+  *         @arg @ref LL_RCC_PLLM_DIV_21
+  *         @arg @ref LL_RCC_PLLM_DIV_22
+  *         @arg @ref LL_RCC_PLLM_DIV_23
+  *         @arg @ref LL_RCC_PLLM_DIV_24
+  *         @arg @ref LL_RCC_PLLM_DIV_25
+  *         @arg @ref LL_RCC_PLLM_DIV_26
+  *         @arg @ref LL_RCC_PLLM_DIV_27
+  *         @arg @ref LL_RCC_PLLM_DIV_28
+  *         @arg @ref LL_RCC_PLLM_DIV_29
+  *         @arg @ref LL_RCC_PLLM_DIV_30
+  *         @arg @ref LL_RCC_PLLM_DIV_31
+  *         @arg @ref LL_RCC_PLLM_DIV_32
+  *         @arg @ref LL_RCC_PLLM_DIV_33
+  *         @arg @ref LL_RCC_PLLM_DIV_34
+  *         @arg @ref LL_RCC_PLLM_DIV_35
+  *         @arg @ref LL_RCC_PLLM_DIV_36
+  *         @arg @ref LL_RCC_PLLM_DIV_37
+  *         @arg @ref LL_RCC_PLLM_DIV_38
+  *         @arg @ref LL_RCC_PLLM_DIV_39
+  *         @arg @ref LL_RCC_PLLM_DIV_40
+  *         @arg @ref LL_RCC_PLLM_DIV_41
+  *         @arg @ref LL_RCC_PLLM_DIV_42
+  *         @arg @ref LL_RCC_PLLM_DIV_43
+  *         @arg @ref LL_RCC_PLLM_DIV_44
+  *         @arg @ref LL_RCC_PLLM_DIV_45
+  *         @arg @ref LL_RCC_PLLM_DIV_46
+  *         @arg @ref LL_RCC_PLLM_DIV_47
+  *         @arg @ref LL_RCC_PLLM_DIV_48
+  *         @arg @ref LL_RCC_PLLM_DIV_49
+  *         @arg @ref LL_RCC_PLLM_DIV_50
+  *         @arg @ref LL_RCC_PLLM_DIV_51
+  *         @arg @ref LL_RCC_PLLM_DIV_52
+  *         @arg @ref LL_RCC_PLLM_DIV_53
+  *         @arg @ref LL_RCC_PLLM_DIV_54
+  *         @arg @ref LL_RCC_PLLM_DIV_55
+  *         @arg @ref LL_RCC_PLLM_DIV_56
+  *         @arg @ref LL_RCC_PLLM_DIV_57
+  *         @arg @ref LL_RCC_PLLM_DIV_58
+  *         @arg @ref LL_RCC_PLLM_DIV_59
+  *         @arg @ref LL_RCC_PLLM_DIV_60
+  *         @arg @ref LL_RCC_PLLM_DIV_61
+  *         @arg @ref LL_RCC_PLLM_DIV_62
+  *         @arg @ref LL_RCC_PLLM_DIV_63
+  * @param  PLLN Between 50/192(*) and 432
+  *
+  *         (*) value not defined in all devices.
+  * @param  PLLQ This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLQ_DIV_2
+  *         @arg @ref LL_RCC_PLLQ_DIV_3
+  *         @arg @ref LL_RCC_PLLQ_DIV_4
+  *         @arg @ref LL_RCC_PLLQ_DIV_5
+  *         @arg @ref LL_RCC_PLLQ_DIV_6
+  *         @arg @ref LL_RCC_PLLQ_DIV_7
+  *         @arg @ref LL_RCC_PLLQ_DIV_8
+  *         @arg @ref LL_RCC_PLLQ_DIV_9
+  *         @arg @ref LL_RCC_PLLQ_DIV_10
+  *         @arg @ref LL_RCC_PLLQ_DIV_11
+  *         @arg @ref LL_RCC_PLLQ_DIV_12
+  *         @arg @ref LL_RCC_PLLQ_DIV_13
+  *         @arg @ref LL_RCC_PLLQ_DIV_14
+  *         @arg @ref LL_RCC_PLLQ_DIV_15
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_48M(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ)
+{
+  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLQ,
+             Source | PLLM | PLLN << RCC_PLLCFGR_PLLN_Pos | PLLQ);
+}
+
+#if defined(DSI)
+/**
+  * @brief  Configure PLL used for DSI clock
+  * @note PLL Source and PLLM Divider can be written only when PLL,
+  *       PLLI2S and PLLSAI are disabled
+  * @note PLLN/PLLR can be written only when PLL is disabled
+  * @note This  can be selected for DSI
+  * @rmtoll PLLCFGR      PLLSRC        LL_RCC_PLL_ConfigDomain_DSI\n
+  *         PLLCFGR      PLLM          LL_RCC_PLL_ConfigDomain_DSI\n
+  *         PLLCFGR      PLLN          LL_RCC_PLL_ConfigDomain_DSI\n
+  *         PLLCFGR      PLLR          LL_RCC_PLL_ConfigDomain_DSI
+  * @param  Source This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLSOURCE_HSI
+  *         @arg @ref LL_RCC_PLLSOURCE_HSE
+  * @param  PLLM This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLM_DIV_2
+  *         @arg @ref LL_RCC_PLLM_DIV_3
+  *         @arg @ref LL_RCC_PLLM_DIV_4
+  *         @arg @ref LL_RCC_PLLM_DIV_5
+  *         @arg @ref LL_RCC_PLLM_DIV_6
+  *         @arg @ref LL_RCC_PLLM_DIV_7
+  *         @arg @ref LL_RCC_PLLM_DIV_8
+  *         @arg @ref LL_RCC_PLLM_DIV_9
+  *         @arg @ref LL_RCC_PLLM_DIV_10
+  *         @arg @ref LL_RCC_PLLM_DIV_11
+  *         @arg @ref LL_RCC_PLLM_DIV_12
+  *         @arg @ref LL_RCC_PLLM_DIV_13
+  *         @arg @ref LL_RCC_PLLM_DIV_14
+  *         @arg @ref LL_RCC_PLLM_DIV_15
+  *         @arg @ref LL_RCC_PLLM_DIV_16
+  *         @arg @ref LL_RCC_PLLM_DIV_17
+  *         @arg @ref LL_RCC_PLLM_DIV_18
+  *         @arg @ref LL_RCC_PLLM_DIV_19
+  *         @arg @ref LL_RCC_PLLM_DIV_20
+  *         @arg @ref LL_RCC_PLLM_DIV_21
+  *         @arg @ref LL_RCC_PLLM_DIV_22
+  *         @arg @ref LL_RCC_PLLM_DIV_23
+  *         @arg @ref LL_RCC_PLLM_DIV_24
+  *         @arg @ref LL_RCC_PLLM_DIV_25
+  *         @arg @ref LL_RCC_PLLM_DIV_26
+  *         @arg @ref LL_RCC_PLLM_DIV_27
+  *         @arg @ref LL_RCC_PLLM_DIV_28
+  *         @arg @ref LL_RCC_PLLM_DIV_29
+  *         @arg @ref LL_RCC_PLLM_DIV_30
+  *         @arg @ref LL_RCC_PLLM_DIV_31
+  *         @arg @ref LL_RCC_PLLM_DIV_32
+  *         @arg @ref LL_RCC_PLLM_DIV_33
+  *         @arg @ref LL_RCC_PLLM_DIV_34
+  *         @arg @ref LL_RCC_PLLM_DIV_35
+  *         @arg @ref LL_RCC_PLLM_DIV_36
+  *         @arg @ref LL_RCC_PLLM_DIV_37
+  *         @arg @ref LL_RCC_PLLM_DIV_38
+  *         @arg @ref LL_RCC_PLLM_DIV_39
+  *         @arg @ref LL_RCC_PLLM_DIV_40
+  *         @arg @ref LL_RCC_PLLM_DIV_41
+  *         @arg @ref LL_RCC_PLLM_DIV_42
+  *         @arg @ref LL_RCC_PLLM_DIV_43
+  *         @arg @ref LL_RCC_PLLM_DIV_44
+  *         @arg @ref LL_RCC_PLLM_DIV_45
+  *         @arg @ref LL_RCC_PLLM_DIV_46
+  *         @arg @ref LL_RCC_PLLM_DIV_47
+  *         @arg @ref LL_RCC_PLLM_DIV_48
+  *         @arg @ref LL_RCC_PLLM_DIV_49
+  *         @arg @ref LL_RCC_PLLM_DIV_50
+  *         @arg @ref LL_RCC_PLLM_DIV_51
+  *         @arg @ref LL_RCC_PLLM_DIV_52
+  *         @arg @ref LL_RCC_PLLM_DIV_53
+  *         @arg @ref LL_RCC_PLLM_DIV_54
+  *         @arg @ref LL_RCC_PLLM_DIV_55
+  *         @arg @ref LL_RCC_PLLM_DIV_56
+  *         @arg @ref LL_RCC_PLLM_DIV_57
+  *         @arg @ref LL_RCC_PLLM_DIV_58
+  *         @arg @ref LL_RCC_PLLM_DIV_59
+  *         @arg @ref LL_RCC_PLLM_DIV_60
+  *         @arg @ref LL_RCC_PLLM_DIV_61
+  *         @arg @ref LL_RCC_PLLM_DIV_62
+  *         @arg @ref LL_RCC_PLLM_DIV_63
+  * @param  PLLN Between 50 and 432
+  * @param  PLLR This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLR_DIV_2
+  *         @arg @ref LL_RCC_PLLR_DIV_3
+  *         @arg @ref LL_RCC_PLLR_DIV_4
+  *         @arg @ref LL_RCC_PLLR_DIV_5
+  *         @arg @ref LL_RCC_PLLR_DIV_6
+  *         @arg @ref LL_RCC_PLLR_DIV_7
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_DSI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)
+{
+  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLR,
+             Source | PLLM | PLLN << RCC_PLLCFGR_PLLN_Pos | PLLR);
+}
+#endif /* DSI */
+
+#if defined(RCC_PLLR_I2S_CLKSOURCE_SUPPORT)
+/**
+  * @brief  Configure PLL used for I2S clock
+  * @note PLL Source and PLLM Divider can be written only when PLL,
+  *       PLLI2S and PLLSAI are disabled
+  * @note PLLN/PLLR can be written only when PLL is disabled
+  * @note This  can be selected for I2S
+  * @rmtoll PLLCFGR      PLLSRC        LL_RCC_PLL_ConfigDomain_I2S\n
+  *         PLLCFGR      PLLM          LL_RCC_PLL_ConfigDomain_I2S\n
+  *         PLLCFGR      PLLN          LL_RCC_PLL_ConfigDomain_I2S\n
+  *         PLLCFGR      PLLR          LL_RCC_PLL_ConfigDomain_I2S
+  * @param  Source This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLSOURCE_HSI
+  *         @arg @ref LL_RCC_PLLSOURCE_HSE
+  * @param  PLLM This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLM_DIV_2
+  *         @arg @ref LL_RCC_PLLM_DIV_3
+  *         @arg @ref LL_RCC_PLLM_DIV_4
+  *         @arg @ref LL_RCC_PLLM_DIV_5
+  *         @arg @ref LL_RCC_PLLM_DIV_6
+  *         @arg @ref LL_RCC_PLLM_DIV_7
+  *         @arg @ref LL_RCC_PLLM_DIV_8
+  *         @arg @ref LL_RCC_PLLM_DIV_9
+  *         @arg @ref LL_RCC_PLLM_DIV_10
+  *         @arg @ref LL_RCC_PLLM_DIV_11
+  *         @arg @ref LL_RCC_PLLM_DIV_12
+  *         @arg @ref LL_RCC_PLLM_DIV_13
+  *         @arg @ref LL_RCC_PLLM_DIV_14
+  *         @arg @ref LL_RCC_PLLM_DIV_15
+  *         @arg @ref LL_RCC_PLLM_DIV_16
+  *         @arg @ref LL_RCC_PLLM_DIV_17
+  *         @arg @ref LL_RCC_PLLM_DIV_18
+  *         @arg @ref LL_RCC_PLLM_DIV_19
+  *         @arg @ref LL_RCC_PLLM_DIV_20
+  *         @arg @ref LL_RCC_PLLM_DIV_21
+  *         @arg @ref LL_RCC_PLLM_DIV_22
+  *         @arg @ref LL_RCC_PLLM_DIV_23
+  *         @arg @ref LL_RCC_PLLM_DIV_24
+  *         @arg @ref LL_RCC_PLLM_DIV_25
+  *         @arg @ref LL_RCC_PLLM_DIV_26
+  *         @arg @ref LL_RCC_PLLM_DIV_27
+  *         @arg @ref LL_RCC_PLLM_DIV_28
+  *         @arg @ref LL_RCC_PLLM_DIV_29
+  *         @arg @ref LL_RCC_PLLM_DIV_30
+  *         @arg @ref LL_RCC_PLLM_DIV_31
+  *         @arg @ref LL_RCC_PLLM_DIV_32
+  *         @arg @ref LL_RCC_PLLM_DIV_33
+  *         @arg @ref LL_RCC_PLLM_DIV_34
+  *         @arg @ref LL_RCC_PLLM_DIV_35
+  *         @arg @ref LL_RCC_PLLM_DIV_36
+  *         @arg @ref LL_RCC_PLLM_DIV_37
+  *         @arg @ref LL_RCC_PLLM_DIV_38
+  *         @arg @ref LL_RCC_PLLM_DIV_39
+  *         @arg @ref LL_RCC_PLLM_DIV_40
+  *         @arg @ref LL_RCC_PLLM_DIV_41
+  *         @arg @ref LL_RCC_PLLM_DIV_42
+  *         @arg @ref LL_RCC_PLLM_DIV_43
+  *         @arg @ref LL_RCC_PLLM_DIV_44
+  *         @arg @ref LL_RCC_PLLM_DIV_45
+  *         @arg @ref LL_RCC_PLLM_DIV_46
+  *         @arg @ref LL_RCC_PLLM_DIV_47
+  *         @arg @ref LL_RCC_PLLM_DIV_48
+  *         @arg @ref LL_RCC_PLLM_DIV_49
+  *         @arg @ref LL_RCC_PLLM_DIV_50
+  *         @arg @ref LL_RCC_PLLM_DIV_51
+  *         @arg @ref LL_RCC_PLLM_DIV_52
+  *         @arg @ref LL_RCC_PLLM_DIV_53
+  *         @arg @ref LL_RCC_PLLM_DIV_54
+  *         @arg @ref LL_RCC_PLLM_DIV_55
+  *         @arg @ref LL_RCC_PLLM_DIV_56
+  *         @arg @ref LL_RCC_PLLM_DIV_57
+  *         @arg @ref LL_RCC_PLLM_DIV_58
+  *         @arg @ref LL_RCC_PLLM_DIV_59
+  *         @arg @ref LL_RCC_PLLM_DIV_60
+  *         @arg @ref LL_RCC_PLLM_DIV_61
+  *         @arg @ref LL_RCC_PLLM_DIV_62
+  *         @arg @ref LL_RCC_PLLM_DIV_63
+  * @param  PLLN Between 50 and 432
+  * @param  PLLR This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLR_DIV_2
+  *         @arg @ref LL_RCC_PLLR_DIV_3
+  *         @arg @ref LL_RCC_PLLR_DIV_4
+  *         @arg @ref LL_RCC_PLLR_DIV_5
+  *         @arg @ref LL_RCC_PLLR_DIV_6
+  *         @arg @ref LL_RCC_PLLR_DIV_7
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_I2S(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)
+{
+  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLR,
+             Source | PLLM | PLLN << RCC_PLLCFGR_PLLN_Pos | PLLR);
+}
+#endif /* RCC_PLLR_I2S_CLKSOURCE_SUPPORT */
+
+#if defined(SPDIFRX)
+/**
+  * @brief  Configure PLL used for SPDIFRX clock
+  * @note PLL Source and PLLM Divider can be written only when PLL,
+  *       PLLI2S and PLLSAI are disabled
+  * @note PLLN/PLLR can be written only when PLL is disabled
+  * @note This  can be selected for SPDIFRX
+  * @rmtoll PLLCFGR      PLLSRC        LL_RCC_PLL_ConfigDomain_SPDIFRX\n
+  *         PLLCFGR      PLLM          LL_RCC_PLL_ConfigDomain_SPDIFRX\n
+  *         PLLCFGR      PLLN          LL_RCC_PLL_ConfigDomain_SPDIFRX\n
+  *         PLLCFGR      PLLR          LL_RCC_PLL_ConfigDomain_SPDIFRX
+  * @param  Source This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLSOURCE_HSI
+  *         @arg @ref LL_RCC_PLLSOURCE_HSE
+  * @param  PLLM This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLM_DIV_2
+  *         @arg @ref LL_RCC_PLLM_DIV_3
+  *         @arg @ref LL_RCC_PLLM_DIV_4
+  *         @arg @ref LL_RCC_PLLM_DIV_5
+  *         @arg @ref LL_RCC_PLLM_DIV_6
+  *         @arg @ref LL_RCC_PLLM_DIV_7
+  *         @arg @ref LL_RCC_PLLM_DIV_8
+  *         @arg @ref LL_RCC_PLLM_DIV_9
+  *         @arg @ref LL_RCC_PLLM_DIV_10
+  *         @arg @ref LL_RCC_PLLM_DIV_11
+  *         @arg @ref LL_RCC_PLLM_DIV_12
+  *         @arg @ref LL_RCC_PLLM_DIV_13
+  *         @arg @ref LL_RCC_PLLM_DIV_14
+  *         @arg @ref LL_RCC_PLLM_DIV_15
+  *         @arg @ref LL_RCC_PLLM_DIV_16
+  *         @arg @ref LL_RCC_PLLM_DIV_17
+  *         @arg @ref LL_RCC_PLLM_DIV_18
+  *         @arg @ref LL_RCC_PLLM_DIV_19
+  *         @arg @ref LL_RCC_PLLM_DIV_20
+  *         @arg @ref LL_RCC_PLLM_DIV_21
+  *         @arg @ref LL_RCC_PLLM_DIV_22
+  *         @arg @ref LL_RCC_PLLM_DIV_23
+  *         @arg @ref LL_RCC_PLLM_DIV_24
+  *         @arg @ref LL_RCC_PLLM_DIV_25
+  *         @arg @ref LL_RCC_PLLM_DIV_26
+  *         @arg @ref LL_RCC_PLLM_DIV_27
+  *         @arg @ref LL_RCC_PLLM_DIV_28
+  *         @arg @ref LL_RCC_PLLM_DIV_29
+  *         @arg @ref LL_RCC_PLLM_DIV_30
+  *         @arg @ref LL_RCC_PLLM_DIV_31
+  *         @arg @ref LL_RCC_PLLM_DIV_32
+  *         @arg @ref LL_RCC_PLLM_DIV_33
+  *         @arg @ref LL_RCC_PLLM_DIV_34
+  *         @arg @ref LL_RCC_PLLM_DIV_35
+  *         @arg @ref LL_RCC_PLLM_DIV_36
+  *         @arg @ref LL_RCC_PLLM_DIV_37
+  *         @arg @ref LL_RCC_PLLM_DIV_38
+  *         @arg @ref LL_RCC_PLLM_DIV_39
+  *         @arg @ref LL_RCC_PLLM_DIV_40
+  *         @arg @ref LL_RCC_PLLM_DIV_41
+  *         @arg @ref LL_RCC_PLLM_DIV_42
+  *         @arg @ref LL_RCC_PLLM_DIV_43
+  *         @arg @ref LL_RCC_PLLM_DIV_44
+  *         @arg @ref LL_RCC_PLLM_DIV_45
+  *         @arg @ref LL_RCC_PLLM_DIV_46
+  *         @arg @ref LL_RCC_PLLM_DIV_47
+  *         @arg @ref LL_RCC_PLLM_DIV_48
+  *         @arg @ref LL_RCC_PLLM_DIV_49
+  *         @arg @ref LL_RCC_PLLM_DIV_50
+  *         @arg @ref LL_RCC_PLLM_DIV_51
+  *         @arg @ref LL_RCC_PLLM_DIV_52
+  *         @arg @ref LL_RCC_PLLM_DIV_53
+  *         @arg @ref LL_RCC_PLLM_DIV_54
+  *         @arg @ref LL_RCC_PLLM_DIV_55
+  *         @arg @ref LL_RCC_PLLM_DIV_56
+  *         @arg @ref LL_RCC_PLLM_DIV_57
+  *         @arg @ref LL_RCC_PLLM_DIV_58
+  *         @arg @ref LL_RCC_PLLM_DIV_59
+  *         @arg @ref LL_RCC_PLLM_DIV_60
+  *         @arg @ref LL_RCC_PLLM_DIV_61
+  *         @arg @ref LL_RCC_PLLM_DIV_62
+  *         @arg @ref LL_RCC_PLLM_DIV_63
+  * @param  PLLN Between 50 and 432
+  * @param  PLLR This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLR_DIV_2
+  *         @arg @ref LL_RCC_PLLR_DIV_3
+  *         @arg @ref LL_RCC_PLLR_DIV_4
+  *         @arg @ref LL_RCC_PLLR_DIV_5
+  *         @arg @ref LL_RCC_PLLR_DIV_6
+  *         @arg @ref LL_RCC_PLLR_DIV_7
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SPDIFRX(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)
+{
+  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLR,
+             Source | PLLM | PLLN << RCC_PLLCFGR_PLLN_Pos | PLLR);
+}
+#endif /* SPDIFRX */
+
+#if defined(RCC_PLLCFGR_PLLR)
+#if defined(SAI1)
+/**
+  * @brief  Configure PLL used for SAI clock
+  * @note PLL Source and PLLM Divider can be written only when PLL,
+  *       PLLI2S and PLLSAI are disabled
+  * @note PLLN/PLLR can be written only when PLL is disabled
+  * @note This  can be selected for SAI
+  * @rmtoll PLLCFGR      PLLSRC        LL_RCC_PLL_ConfigDomain_SAI\n
+  *         PLLCFGR      PLLM          LL_RCC_PLL_ConfigDomain_SAI\n
+  *         PLLCFGR      PLLN          LL_RCC_PLL_ConfigDomain_SAI\n
+  *         PLLCFGR      PLLR          LL_RCC_PLL_ConfigDomain_SAI\n
+  *         DCKCFGR      PLLDIVR       LL_RCC_PLL_ConfigDomain_SAI
+  * @param  Source This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLSOURCE_HSI
+  *         @arg @ref LL_RCC_PLLSOURCE_HSE
+  * @param  PLLM This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLM_DIV_2
+  *         @arg @ref LL_RCC_PLLM_DIV_3
+  *         @arg @ref LL_RCC_PLLM_DIV_4
+  *         @arg @ref LL_RCC_PLLM_DIV_5
+  *         @arg @ref LL_RCC_PLLM_DIV_6
+  *         @arg @ref LL_RCC_PLLM_DIV_7
+  *         @arg @ref LL_RCC_PLLM_DIV_8
+  *         @arg @ref LL_RCC_PLLM_DIV_9
+  *         @arg @ref LL_RCC_PLLM_DIV_10
+  *         @arg @ref LL_RCC_PLLM_DIV_11
+  *         @arg @ref LL_RCC_PLLM_DIV_12
+  *         @arg @ref LL_RCC_PLLM_DIV_13
+  *         @arg @ref LL_RCC_PLLM_DIV_14
+  *         @arg @ref LL_RCC_PLLM_DIV_15
+  *         @arg @ref LL_RCC_PLLM_DIV_16
+  *         @arg @ref LL_RCC_PLLM_DIV_17
+  *         @arg @ref LL_RCC_PLLM_DIV_18
+  *         @arg @ref LL_RCC_PLLM_DIV_19
+  *         @arg @ref LL_RCC_PLLM_DIV_20
+  *         @arg @ref LL_RCC_PLLM_DIV_21
+  *         @arg @ref LL_RCC_PLLM_DIV_22
+  *         @arg @ref LL_RCC_PLLM_DIV_23
+  *         @arg @ref LL_RCC_PLLM_DIV_24
+  *         @arg @ref LL_RCC_PLLM_DIV_25
+  *         @arg @ref LL_RCC_PLLM_DIV_26
+  *         @arg @ref LL_RCC_PLLM_DIV_27
+  *         @arg @ref LL_RCC_PLLM_DIV_28
+  *         @arg @ref LL_RCC_PLLM_DIV_29
+  *         @arg @ref LL_RCC_PLLM_DIV_30
+  *         @arg @ref LL_RCC_PLLM_DIV_31
+  *         @arg @ref LL_RCC_PLLM_DIV_32
+  *         @arg @ref LL_RCC_PLLM_DIV_33
+  *         @arg @ref LL_RCC_PLLM_DIV_34
+  *         @arg @ref LL_RCC_PLLM_DIV_35
+  *         @arg @ref LL_RCC_PLLM_DIV_36
+  *         @arg @ref LL_RCC_PLLM_DIV_37
+  *         @arg @ref LL_RCC_PLLM_DIV_38
+  *         @arg @ref LL_RCC_PLLM_DIV_39
+  *         @arg @ref LL_RCC_PLLM_DIV_40
+  *         @arg @ref LL_RCC_PLLM_DIV_41
+  *         @arg @ref LL_RCC_PLLM_DIV_42
+  *         @arg @ref LL_RCC_PLLM_DIV_43
+  *         @arg @ref LL_RCC_PLLM_DIV_44
+  *         @arg @ref LL_RCC_PLLM_DIV_45
+  *         @arg @ref LL_RCC_PLLM_DIV_46
+  *         @arg @ref LL_RCC_PLLM_DIV_47
+  *         @arg @ref LL_RCC_PLLM_DIV_48
+  *         @arg @ref LL_RCC_PLLM_DIV_49
+  *         @arg @ref LL_RCC_PLLM_DIV_50
+  *         @arg @ref LL_RCC_PLLM_DIV_51
+  *         @arg @ref LL_RCC_PLLM_DIV_52
+  *         @arg @ref LL_RCC_PLLM_DIV_53
+  *         @arg @ref LL_RCC_PLLM_DIV_54
+  *         @arg @ref LL_RCC_PLLM_DIV_55
+  *         @arg @ref LL_RCC_PLLM_DIV_56
+  *         @arg @ref LL_RCC_PLLM_DIV_57
+  *         @arg @ref LL_RCC_PLLM_DIV_58
+  *         @arg @ref LL_RCC_PLLM_DIV_59
+  *         @arg @ref LL_RCC_PLLM_DIV_60
+  *         @arg @ref LL_RCC_PLLM_DIV_61
+  *         @arg @ref LL_RCC_PLLM_DIV_62
+  *         @arg @ref LL_RCC_PLLM_DIV_63
+  * @param  PLLN Between 50 and 432
+  * @param  PLLR This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLR_DIV_2
+  *         @arg @ref LL_RCC_PLLR_DIV_3
+  *         @arg @ref LL_RCC_PLLR_DIV_4
+  *         @arg @ref LL_RCC_PLLR_DIV_5
+  *         @arg @ref LL_RCC_PLLR_DIV_6
+  *         @arg @ref LL_RCC_PLLR_DIV_7
+  * @param  PLLDIVR This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLDIVR_DIV_1 (*)
+  *         @arg @ref LL_RCC_PLLDIVR_DIV_2 (*)
+  *         @arg @ref LL_RCC_PLLDIVR_DIV_3 (*)
+  *         @arg @ref LL_RCC_PLLDIVR_DIV_4 (*)
+  *         @arg @ref LL_RCC_PLLDIVR_DIV_5 (*)
+  *         @arg @ref LL_RCC_PLLDIVR_DIV_6 (*)
+  *         @arg @ref LL_RCC_PLLDIVR_DIV_7 (*)
+  *         @arg @ref LL_RCC_PLLDIVR_DIV_8 (*)
+  *         @arg @ref LL_RCC_PLLDIVR_DIV_9 (*)
+  *         @arg @ref LL_RCC_PLLDIVR_DIV_10 (*)
+  *         @arg @ref LL_RCC_PLLDIVR_DIV_11 (*)
+  *         @arg @ref LL_RCC_PLLDIVR_DIV_12 (*)
+  *         @arg @ref LL_RCC_PLLDIVR_DIV_13 (*)
+  *         @arg @ref LL_RCC_PLLDIVR_DIV_14 (*)
+  *         @arg @ref LL_RCC_PLLDIVR_DIV_15 (*)
+  *         @arg @ref LL_RCC_PLLDIVR_DIV_16 (*)
+  *         @arg @ref LL_RCC_PLLDIVR_DIV_17 (*)
+  *         @arg @ref LL_RCC_PLLDIVR_DIV_18 (*)
+  *         @arg @ref LL_RCC_PLLDIVR_DIV_19 (*)
+  *         @arg @ref LL_RCC_PLLDIVR_DIV_20 (*)
+  *         @arg @ref LL_RCC_PLLDIVR_DIV_21 (*)
+  *         @arg @ref LL_RCC_PLLDIVR_DIV_22 (*)
+  *         @arg @ref LL_RCC_PLLDIVR_DIV_23 (*)
+  *         @arg @ref LL_RCC_PLLDIVR_DIV_24 (*)
+  *         @arg @ref LL_RCC_PLLDIVR_DIV_25 (*)
+  *         @arg @ref LL_RCC_PLLDIVR_DIV_26 (*)
+  *         @arg @ref LL_RCC_PLLDIVR_DIV_27 (*)
+  *         @arg @ref LL_RCC_PLLDIVR_DIV_28 (*)
+  *         @arg @ref LL_RCC_PLLDIVR_DIV_29 (*)
+  *         @arg @ref LL_RCC_PLLDIVR_DIV_30 (*)
+  *         @arg @ref LL_RCC_PLLDIVR_DIV_31 (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+  */
+#if defined(RCC_DCKCFGR_PLLDIVR)
+__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR, uint32_t PLLDIVR)
+#else
+__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)
+#endif /* RCC_DCKCFGR_PLLDIVR */
+{
+  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLR,
+             Source | PLLM | PLLN << RCC_PLLCFGR_PLLN_Pos | PLLR);
+#if defined(RCC_DCKCFGR_PLLDIVR)
+  MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLDIVR, PLLDIVR);
+#endif /* RCC_DCKCFGR_PLLDIVR */
+}
+#endif /* SAI1 */
+#endif /* RCC_PLLCFGR_PLLR */
+
+/**
+  * @brief  Configure PLL clock source
+  * @rmtoll PLLCFGR      PLLSRC        LL_RCC_PLL_SetMainSource
+  * @param PLLSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLSOURCE_HSI
+  *         @arg @ref LL_RCC_PLLSOURCE_HSE
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL_SetMainSource(uint32_t PLLSource)
+{
+  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, PLLSource);
+}
+
+/**
+  * @brief  Get the oscillator used as PLL clock source.
+  * @rmtoll PLLCFGR      PLLSRC        LL_RCC_PLL_GetMainSource
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_PLLSOURCE_HSI
+  *         @arg @ref LL_RCC_PLLSOURCE_HSE
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLL_GetMainSource(void)
+{
+  return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC));
+}
+
+/**
+  * @brief  Get Main PLL multiplication factor for VCO
+  * @rmtoll PLLCFGR      PLLN          LL_RCC_PLL_GetN
+  * @retval Between 50/192(*) and 432
+  *
+  *         (*) value not defined in all devices.
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLL_GetN(void)
+{
+  return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >>  RCC_PLLCFGR_PLLN_Pos);
+}
+
+/**
+  * @brief  Get Main PLL division factor for PLLP 
+  * @rmtoll PLLCFGR      PLLP       LL_RCC_PLL_GetP
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_PLLP_DIV_2
+  *         @arg @ref LL_RCC_PLLP_DIV_4
+  *         @arg @ref LL_RCC_PLLP_DIV_6
+  *         @arg @ref LL_RCC_PLLP_DIV_8
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLL_GetP(void)
+{
+  return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLP));
+}
+
+/**
+  * @brief  Get Main PLL division factor for PLLQ
+  * @note used for PLL48MCLK selected for USB, RNG, SDIO (48 MHz clock)
+  * @rmtoll PLLCFGR      PLLQ          LL_RCC_PLL_GetQ
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_PLLQ_DIV_2
+  *         @arg @ref LL_RCC_PLLQ_DIV_3
+  *         @arg @ref LL_RCC_PLLQ_DIV_4
+  *         @arg @ref LL_RCC_PLLQ_DIV_5
+  *         @arg @ref LL_RCC_PLLQ_DIV_6
+  *         @arg @ref LL_RCC_PLLQ_DIV_7
+  *         @arg @ref LL_RCC_PLLQ_DIV_8
+  *         @arg @ref LL_RCC_PLLQ_DIV_9
+  *         @arg @ref LL_RCC_PLLQ_DIV_10
+  *         @arg @ref LL_RCC_PLLQ_DIV_11
+  *         @arg @ref LL_RCC_PLLQ_DIV_12
+  *         @arg @ref LL_RCC_PLLQ_DIV_13
+  *         @arg @ref LL_RCC_PLLQ_DIV_14
+  *         @arg @ref LL_RCC_PLLQ_DIV_15
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLL_GetQ(void)
+{
+  return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ));
+}
+
+#if defined(RCC_PLLCFGR_PLLR)
+/**
+  * @brief  Get Main PLL division factor for PLLR
+  * @note used for PLLCLK (system clock)
+  * @rmtoll PLLCFGR      PLLR          LL_RCC_PLL_GetR
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_PLLR_DIV_2
+  *         @arg @ref LL_RCC_PLLR_DIV_3
+  *         @arg @ref LL_RCC_PLLR_DIV_4
+  *         @arg @ref LL_RCC_PLLR_DIV_5
+  *         @arg @ref LL_RCC_PLLR_DIV_6
+  *         @arg @ref LL_RCC_PLLR_DIV_7
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLL_GetR(void)
+{
+  return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR));
+}
+#endif /* RCC_PLLCFGR_PLLR */
+
+#if defined(RCC_DCKCFGR_PLLDIVR)
+/**
+  * @brief  Get Main PLL division factor for PLLDIVR
+  * @note used for PLLSAICLK (SAI1 and SAI2 clock)
+  * @rmtoll DCKCFGR      PLLDIVR          LL_RCC_PLL_GetDIVR
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_PLLDIVR_DIV_1
+  *         @arg @ref LL_RCC_PLLDIVR_DIV_2
+  *         @arg @ref LL_RCC_PLLDIVR_DIV_3
+  *         @arg @ref LL_RCC_PLLDIVR_DIV_4
+  *         @arg @ref LL_RCC_PLLDIVR_DIV_5
+  *         @arg @ref LL_RCC_PLLDIVR_DIV_6
+  *         @arg @ref LL_RCC_PLLDIVR_DIV_7
+  *         @arg @ref LL_RCC_PLLDIVR_DIV_8
+  *         @arg @ref LL_RCC_PLLDIVR_DIV_9
+  *         @arg @ref LL_RCC_PLLDIVR_DIV_10
+  *         @arg @ref LL_RCC_PLLDIVR_DIV_11
+  *         @arg @ref LL_RCC_PLLDIVR_DIV_12
+  *         @arg @ref LL_RCC_PLLDIVR_DIV_13
+  *         @arg @ref LL_RCC_PLLDIVR_DIV_14
+  *         @arg @ref LL_RCC_PLLDIVR_DIV_15
+  *         @arg @ref LL_RCC_PLLDIVR_DIV_16
+  *         @arg @ref LL_RCC_PLLDIVR_DIV_17
+  *         @arg @ref LL_RCC_PLLDIVR_DIV_18
+  *         @arg @ref LL_RCC_PLLDIVR_DIV_19
+  *         @arg @ref LL_RCC_PLLDIVR_DIV_20
+  *         @arg @ref LL_RCC_PLLDIVR_DIV_21
+  *         @arg @ref LL_RCC_PLLDIVR_DIV_22
+  *         @arg @ref LL_RCC_PLLDIVR_DIV_23
+  *         @arg @ref LL_RCC_PLLDIVR_DIV_24
+  *         @arg @ref LL_RCC_PLLDIVR_DIV_25
+  *         @arg @ref LL_RCC_PLLDIVR_DIV_26
+  *         @arg @ref LL_RCC_PLLDIVR_DIV_27
+  *         @arg @ref LL_RCC_PLLDIVR_DIV_28
+  *         @arg @ref LL_RCC_PLLDIVR_DIV_29
+  *         @arg @ref LL_RCC_PLLDIVR_DIV_30
+  *         @arg @ref LL_RCC_PLLDIVR_DIV_31
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLL_GetDIVR(void)
+{
+  return (uint32_t)(READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_PLLDIVR));
+}
+#endif /* RCC_DCKCFGR_PLLDIVR */
+
+/**
+  * @brief  Get Division factor for the main PLL and other PLL
+  * @rmtoll PLLCFGR      PLLM          LL_RCC_PLL_GetDivider
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_PLLM_DIV_2
+  *         @arg @ref LL_RCC_PLLM_DIV_3
+  *         @arg @ref LL_RCC_PLLM_DIV_4
+  *         @arg @ref LL_RCC_PLLM_DIV_5
+  *         @arg @ref LL_RCC_PLLM_DIV_6
+  *         @arg @ref LL_RCC_PLLM_DIV_7
+  *         @arg @ref LL_RCC_PLLM_DIV_8
+  *         @arg @ref LL_RCC_PLLM_DIV_9
+  *         @arg @ref LL_RCC_PLLM_DIV_10
+  *         @arg @ref LL_RCC_PLLM_DIV_11
+  *         @arg @ref LL_RCC_PLLM_DIV_12
+  *         @arg @ref LL_RCC_PLLM_DIV_13
+  *         @arg @ref LL_RCC_PLLM_DIV_14
+  *         @arg @ref LL_RCC_PLLM_DIV_15
+  *         @arg @ref LL_RCC_PLLM_DIV_16
+  *         @arg @ref LL_RCC_PLLM_DIV_17
+  *         @arg @ref LL_RCC_PLLM_DIV_18
+  *         @arg @ref LL_RCC_PLLM_DIV_19
+  *         @arg @ref LL_RCC_PLLM_DIV_20
+  *         @arg @ref LL_RCC_PLLM_DIV_21
+  *         @arg @ref LL_RCC_PLLM_DIV_22
+  *         @arg @ref LL_RCC_PLLM_DIV_23
+  *         @arg @ref LL_RCC_PLLM_DIV_24
+  *         @arg @ref LL_RCC_PLLM_DIV_25
+  *         @arg @ref LL_RCC_PLLM_DIV_26
+  *         @arg @ref LL_RCC_PLLM_DIV_27
+  *         @arg @ref LL_RCC_PLLM_DIV_28
+  *         @arg @ref LL_RCC_PLLM_DIV_29
+  *         @arg @ref LL_RCC_PLLM_DIV_30
+  *         @arg @ref LL_RCC_PLLM_DIV_31
+  *         @arg @ref LL_RCC_PLLM_DIV_32
+  *         @arg @ref LL_RCC_PLLM_DIV_33
+  *         @arg @ref LL_RCC_PLLM_DIV_34
+  *         @arg @ref LL_RCC_PLLM_DIV_35
+  *         @arg @ref LL_RCC_PLLM_DIV_36
+  *         @arg @ref LL_RCC_PLLM_DIV_37
+  *         @arg @ref LL_RCC_PLLM_DIV_38
+  *         @arg @ref LL_RCC_PLLM_DIV_39
+  *         @arg @ref LL_RCC_PLLM_DIV_40
+  *         @arg @ref LL_RCC_PLLM_DIV_41
+  *         @arg @ref LL_RCC_PLLM_DIV_42
+  *         @arg @ref LL_RCC_PLLM_DIV_43
+  *         @arg @ref LL_RCC_PLLM_DIV_44
+  *         @arg @ref LL_RCC_PLLM_DIV_45
+  *         @arg @ref LL_RCC_PLLM_DIV_46
+  *         @arg @ref LL_RCC_PLLM_DIV_47
+  *         @arg @ref LL_RCC_PLLM_DIV_48
+  *         @arg @ref LL_RCC_PLLM_DIV_49
+  *         @arg @ref LL_RCC_PLLM_DIV_50
+  *         @arg @ref LL_RCC_PLLM_DIV_51
+  *         @arg @ref LL_RCC_PLLM_DIV_52
+  *         @arg @ref LL_RCC_PLLM_DIV_53
+  *         @arg @ref LL_RCC_PLLM_DIV_54
+  *         @arg @ref LL_RCC_PLLM_DIV_55
+  *         @arg @ref LL_RCC_PLLM_DIV_56
+  *         @arg @ref LL_RCC_PLLM_DIV_57
+  *         @arg @ref LL_RCC_PLLM_DIV_58
+  *         @arg @ref LL_RCC_PLLM_DIV_59
+  *         @arg @ref LL_RCC_PLLM_DIV_60
+  *         @arg @ref LL_RCC_PLLM_DIV_61
+  *         @arg @ref LL_RCC_PLLM_DIV_62
+  *         @arg @ref LL_RCC_PLLM_DIV_63
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLL_GetDivider(void)
+{
+  return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM));
+}
+
+/**
+  * @brief  Configure Spread Spectrum used for PLL
+  * @note These bits must be written before enabling PLL
+  * @rmtoll SSCGR        MODPER        LL_RCC_PLL_ConfigSpreadSpectrum\n
+  *         SSCGR        INCSTEP       LL_RCC_PLL_ConfigSpreadSpectrum\n
+  *         SSCGR        SPREADSEL     LL_RCC_PLL_ConfigSpreadSpectrum
+  * @param  Mod Between Min_Data=0 and Max_Data=8191
+  * @param  Inc Between Min_Data=0 and Max_Data=32767
+  * @param  Sel This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_SPREAD_SELECT_CENTER
+  *         @arg @ref LL_RCC_SPREAD_SELECT_DOWN
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL_ConfigSpreadSpectrum(uint32_t Mod, uint32_t Inc, uint32_t Sel)
+{
+  MODIFY_REG(RCC->SSCGR, RCC_SSCGR_MODPER | RCC_SSCGR_INCSTEP | RCC_SSCGR_SPREADSEL, Mod | (Inc << RCC_SSCGR_INCSTEP_Pos) | Sel);
+}
+
+/**
+  * @brief  Get Spread Spectrum Modulation Period for PLL
+  * @rmtoll SSCGR         MODPER        LL_RCC_PLL_GetPeriodModulation
+  * @retval Between Min_Data=0 and Max_Data=8191
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLL_GetPeriodModulation(void)
+{
+  return (uint32_t)(READ_BIT(RCC->SSCGR, RCC_SSCGR_MODPER));
+}
+
+/**
+  * @brief  Get Spread Spectrum Incrementation Step for PLL
+  * @note Must be written before enabling PLL
+  * @rmtoll SSCGR         INCSTEP        LL_RCC_PLL_GetStepIncrementation
+  * @retval Between Min_Data=0 and Max_Data=32767
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLL_GetStepIncrementation(void)
+{
+  return (uint32_t)(READ_BIT(RCC->SSCGR, RCC_SSCGR_INCSTEP) >> RCC_SSCGR_INCSTEP_Pos);
+}
+
+/**
+  * @brief  Get Spread Spectrum Selection for PLL
+  * @note Must be written before enabling PLL
+  * @rmtoll SSCGR         SPREADSEL        LL_RCC_PLL_GetSpreadSelection
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_SPREAD_SELECT_CENTER
+  *         @arg @ref LL_RCC_SPREAD_SELECT_DOWN
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLL_GetSpreadSelection(void)
+{
+  return (uint32_t)(READ_BIT(RCC->SSCGR, RCC_SSCGR_SPREADSEL));
+}
+
+/**
+  * @brief  Enable Spread Spectrum for PLL.
+  * @rmtoll SSCGR         SSCGEN         LL_RCC_PLL_SpreadSpectrum_Enable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL_SpreadSpectrum_Enable(void)
+{
+  SET_BIT(RCC->SSCGR, RCC_SSCGR_SSCGEN);
+}
+
+/**
+  * @brief  Disable Spread Spectrum for PLL.
+  * @rmtoll SSCGR         SSCGEN         LL_RCC_PLL_SpreadSpectrum_Disable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL_SpreadSpectrum_Disable(void)
+{
+  CLEAR_BIT(RCC->SSCGR, RCC_SSCGR_SSCGEN);
+}
+
+/**
+  * @}
+  */
+
+#if defined(RCC_PLLI2S_SUPPORT)
+/** @defgroup RCC_LL_EF_PLLI2S PLLI2S
+  * @{
+  */
+
+/**
+  * @brief  Enable PLLI2S
+  * @rmtoll CR           PLLI2SON     LL_RCC_PLLI2S_Enable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLLI2S_Enable(void)
+{
+  SET_BIT(RCC->CR, RCC_CR_PLLI2SON);
+}
+
+/**
+  * @brief  Disable PLLI2S
+  * @rmtoll CR           PLLI2SON     LL_RCC_PLLI2S_Disable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLLI2S_Disable(void)
+{
+  CLEAR_BIT(RCC->CR, RCC_CR_PLLI2SON);
+}
+
+/**
+  * @brief  Check if PLLI2S Ready
+  * @rmtoll CR           PLLI2SRDY    LL_RCC_PLLI2S_IsReady
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLLI2S_IsReady(void)
+{
+  return (READ_BIT(RCC->CR, RCC_CR_PLLI2SRDY) == (RCC_CR_PLLI2SRDY));
+}
+
+#if (defined(RCC_DCKCFGR_PLLI2SDIVQ) || defined(RCC_DCKCFGR_PLLI2SDIVR))
+/**
+  * @brief  Configure PLLI2S used for SAI domain clock
+  * @note PLL Source and PLLM Divider can be written only when PLL,
+  *       PLLI2S and PLLSAI(*) are disabled
+  * @note PLLN/PLLQ/PLLR can be written only when PLLI2S is disabled
+  * @note This can be selected for SAI
+  * @rmtoll PLLCFGR      PLLSRC        LL_RCC_PLLI2S_ConfigDomain_SAI\n
+  *         PLLI2SCFGR   PLLI2SSRC     LL_RCC_PLLI2S_ConfigDomain_SAI\n
+  *         PLLCFGR      PLLM          LL_RCC_PLLI2S_ConfigDomain_SAI\n
+  *         PLLI2SCFGR   PLLI2SM       LL_RCC_PLLI2S_ConfigDomain_SAI\n
+  *         PLLI2SCFGR   PLLI2SN       LL_RCC_PLLI2S_ConfigDomain_SAI\n
+  *         PLLI2SCFGR   PLLI2SQ       LL_RCC_PLLI2S_ConfigDomain_SAI\n
+  *         PLLI2SCFGR   PLLI2SR       LL_RCC_PLLI2S_ConfigDomain_SAI\n
+  *         DCKCFGR      PLLI2SDIVQ    LL_RCC_PLLI2S_ConfigDomain_SAI\n
+  *         DCKCFGR      PLLI2SDIVR    LL_RCC_PLLI2S_ConfigDomain_SAI
+  * @param  Source This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLSOURCE_HSI
+  *         @arg @ref LL_RCC_PLLSOURCE_HSE
+  *         @arg @ref LL_RCC_PLLI2SSOURCE_PIN (*)
+  *
+  *         (*) value not defined in all devices.
+  * @param  PLLM This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_2
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_3
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_4
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_5
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_6
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_7
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_8
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_9
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_10
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_11
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_12
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_13
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_14
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_15
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_16
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_17
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_18
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_19
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_20
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_21
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_22
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_23
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_24
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_25
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_26
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_27
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_28
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_29
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_30
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_31
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_32
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_33
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_34
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_35
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_36
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_37
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_38
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_39
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_40
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_41
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_42
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_43
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_44
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_45
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_46
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_47
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_48
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_49
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_50
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_51
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_52
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_53
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_54
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_55
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_56
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_57
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_58
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_59
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_60
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_61
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_62
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_63
+  * @param  PLLN Between 50/192(*) and 432
+  *
+  *         (*) value not defined in all devices.
+  * @param  PLLQ_R This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLI2SQ_DIV_2 (*)
+  *         @arg @ref LL_RCC_PLLI2SQ_DIV_3 (*)
+  *         @arg @ref LL_RCC_PLLI2SQ_DIV_4 (*)
+  *         @arg @ref LL_RCC_PLLI2SQ_DIV_5 (*)
+  *         @arg @ref LL_RCC_PLLI2SQ_DIV_6 (*)
+  *         @arg @ref LL_RCC_PLLI2SQ_DIV_7 (*)
+  *         @arg @ref LL_RCC_PLLI2SQ_DIV_8 (*)
+  *         @arg @ref LL_RCC_PLLI2SQ_DIV_9 (*)
+  *         @arg @ref LL_RCC_PLLI2SQ_DIV_10 (*)
+  *         @arg @ref LL_RCC_PLLI2SQ_DIV_11 (*)
+  *         @arg @ref LL_RCC_PLLI2SQ_DIV_12 (*)
+  *         @arg @ref LL_RCC_PLLI2SQ_DIV_13 (*)
+  *         @arg @ref LL_RCC_PLLI2SQ_DIV_14 (*)
+  *         @arg @ref LL_RCC_PLLI2SQ_DIV_15 (*)
+  *         @arg @ref LL_RCC_PLLI2SR_DIV_2 (*)
+  *         @arg @ref LL_RCC_PLLI2SR_DIV_3 (*)
+  *         @arg @ref LL_RCC_PLLI2SR_DIV_4 (*)
+  *         @arg @ref LL_RCC_PLLI2SR_DIV_5 (*)
+  *         @arg @ref LL_RCC_PLLI2SR_DIV_6 (*)
+  *         @arg @ref LL_RCC_PLLI2SR_DIV_7 (*)
+  *
+  *         (*) value not defined in all devices.
+  * @param  PLLDIVQ_R This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_1 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_2 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_3 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_4 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_5 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_6 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_7 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_8 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_9 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_10 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_11 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_12 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_13 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_14 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_15 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_16 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_17 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_18 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_19 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_20 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_21 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_22 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_23 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_24 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_25 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_26 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_27 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_28 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_29 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_30 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_31 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_32 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_1 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_2 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_3 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_4 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_5 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_6 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_7 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_8 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_9 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_10 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_11 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_12 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_13 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_14 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_15 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_16 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_17 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_18 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_19 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_20 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_21 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_22 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_23 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_24 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_25 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_26 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_27 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_28 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_29 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_30 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_31 (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLLI2S_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ_R, uint32_t PLLDIVQ_R)
+{
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&RCC->PLLCFGR) + (Source & 0x80U)));
+  MODIFY_REG(*pReg, RCC_PLLCFGR_PLLSRC, (Source & (~0x80U)));
+#if defined(RCC_PLLI2SCFGR_PLLI2SM)
+  MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SM, PLLM);
+#else
+  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, PLLM);
+#endif /* RCC_PLLI2SCFGR_PLLI2SM */
+  MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SN, PLLN << RCC_PLLI2SCFGR_PLLI2SN_Pos);
+#if defined(RCC_DCKCFGR_PLLI2SDIVQ)
+  MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SQ, PLLQ_R);
+  MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLI2SDIVQ, PLLDIVQ_R);
+#else
+  MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SR, PLLQ_R);
+  MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLI2SDIVR, PLLDIVQ_R);
+#endif /* RCC_DCKCFGR_PLLI2SDIVQ */
+}
+#endif /* RCC_DCKCFGR_PLLI2SDIVQ && RCC_DCKCFGR_PLLI2SDIVR */
+
+#if defined(RCC_PLLI2SCFGR_PLLI2SQ) && !defined(RCC_DCKCFGR_PLLI2SDIVQ)
+/**
+  * @brief  Configure PLLI2S used for 48Mhz domain clock
+  * @note PLL Source and PLLM Divider can be written only when PLL,
+  *       PLLI2S and PLLSAI(*) are disabled
+  * @note PLLN/PLLQ can be written only when PLLI2S is disabled
+  * @note This can be selected for RNG, USB, SDIO
+  * @rmtoll PLLCFGR      PLLSRC        LL_RCC_PLLI2S_ConfigDomain_48M\n
+  *         PLLI2SCFGR   PLLI2SSRC     LL_RCC_PLLI2S_ConfigDomain_48M\n
+  *         PLLCFGR      PLLM          LL_RCC_PLLI2S_ConfigDomain_48M\n
+  *         PLLI2SCFGR   PLLI2SM       LL_RCC_PLLI2S_ConfigDomain_48M\n
+  *         PLLI2SCFGR   PLLI2SN       LL_RCC_PLLI2S_ConfigDomain_48M\n
+  *         PLLI2SCFGR   PLLI2SQ       LL_RCC_PLLI2S_ConfigDomain_48M
+  * @param  Source This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLSOURCE_HSI
+  *         @arg @ref LL_RCC_PLLSOURCE_HSE
+  *         @arg @ref LL_RCC_PLLI2SSOURCE_PIN (*)
+  *
+  *         (*) value not defined in all devices.
+  * @param  PLLM This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_2
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_3
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_4
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_5
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_6
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_7
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_8
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_9
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_10
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_11
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_12
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_13
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_14
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_15
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_16
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_17
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_18
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_19
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_20
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_21
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_22
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_23
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_24
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_25
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_26
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_27
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_28
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_29
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_30
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_31
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_32
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_33
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_34
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_35
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_36
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_37
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_38
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_39
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_40
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_41
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_42
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_43
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_44
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_45
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_46
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_47
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_48
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_49
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_50
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_51
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_52
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_53
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_54
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_55
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_56
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_57
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_58
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_59
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_60
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_61
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_62
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_63
+  * @param  PLLN Between 50 and 432
+  * @param  PLLQ This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLI2SQ_DIV_2
+  *         @arg @ref LL_RCC_PLLI2SQ_DIV_3
+  *         @arg @ref LL_RCC_PLLI2SQ_DIV_4
+  *         @arg @ref LL_RCC_PLLI2SQ_DIV_5
+  *         @arg @ref LL_RCC_PLLI2SQ_DIV_6
+  *         @arg @ref LL_RCC_PLLI2SQ_DIV_7
+  *         @arg @ref LL_RCC_PLLI2SQ_DIV_8
+  *         @arg @ref LL_RCC_PLLI2SQ_DIV_9
+  *         @arg @ref LL_RCC_PLLI2SQ_DIV_10
+  *         @arg @ref LL_RCC_PLLI2SQ_DIV_11
+  *         @arg @ref LL_RCC_PLLI2SQ_DIV_12
+  *         @arg @ref LL_RCC_PLLI2SQ_DIV_13
+  *         @arg @ref LL_RCC_PLLI2SQ_DIV_14
+  *         @arg @ref LL_RCC_PLLI2SQ_DIV_15
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLLI2S_ConfigDomain_48M(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ)
+{
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&RCC->PLLCFGR) + (Source & 0x80U)));
+  MODIFY_REG(*pReg, RCC_PLLCFGR_PLLSRC, (Source & (~0x80U)));
+#if defined(RCC_PLLI2SCFGR_PLLI2SM)
+  MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SM, PLLM);
+#else
+  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, PLLM);
+#endif /* RCC_PLLI2SCFGR_PLLI2SM */
+  MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SN | RCC_PLLI2SCFGR_PLLI2SQ, PLLN << RCC_PLLI2SCFGR_PLLI2SN_Pos | PLLQ);
+}
+#endif /* RCC_PLLI2SCFGR_PLLI2SQ && !RCC_DCKCFGR_PLLI2SDIVQ */
+
+#if defined(SPDIFRX)
+/**
+  * @brief Configure PLLI2S used for SPDIFRX domain clock
+  * @note PLL Source and PLLM Divider can be written only when PLL,
+  *       PLLI2S and PLLSAI(*) are disabled
+  * @note PLLN/PLLP can be written only when PLLI2S is disabled
+  * @note This  can be selected for SPDIFRX
+  * @rmtoll PLLCFGR      PLLSRC        LL_RCC_PLLI2S_ConfigDomain_SPDIFRX\n
+  *         PLLCFGR      PLLM          LL_RCC_PLLI2S_ConfigDomain_SPDIFRX\n
+  *         PLLI2SCFGR   PLLI2SM       LL_RCC_PLLI2S_ConfigDomain_SPDIFRX\n
+  *         PLLI2SCFGR   PLLI2SN       LL_RCC_PLLI2S_ConfigDomain_SPDIFRX\n
+  *         PLLI2SCFGR   PLLI2SP       LL_RCC_PLLI2S_ConfigDomain_SPDIFRX
+  * @param  Source This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLSOURCE_HSI
+  *         @arg @ref LL_RCC_PLLSOURCE_HSE
+  * @param  PLLM This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_2
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_3
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_4
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_5
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_6
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_7
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_8
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_9
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_10
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_11
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_12
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_13
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_14
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_15
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_16
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_17
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_18
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_19
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_20
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_21
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_22
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_23
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_24
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_25
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_26
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_27
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_28
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_29
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_30
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_31
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_32
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_33
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_34
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_35
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_36
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_37
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_38
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_39
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_40
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_41
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_42
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_43
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_44
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_45
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_46
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_47
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_48
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_49
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_50
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_51
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_52
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_53
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_54
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_55
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_56
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_57
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_58
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_59
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_60
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_61
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_62
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_63
+  * @param  PLLN Between 50 and 432
+  * @param  PLLP This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLI2SP_DIV_2
+  *         @arg @ref LL_RCC_PLLI2SP_DIV_4
+  *         @arg @ref LL_RCC_PLLI2SP_DIV_6
+  *         @arg @ref LL_RCC_PLLI2SP_DIV_8
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLLI2S_ConfigDomain_SPDIFRX(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP)
+{
+  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, Source);
+#if defined(RCC_PLLI2SCFGR_PLLI2SM)
+  MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SM, PLLM);
+#else
+  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, PLLM);
+#endif /* RCC_PLLI2SCFGR_PLLI2SM */
+  MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SN | RCC_PLLI2SCFGR_PLLI2SP, PLLN << RCC_PLLI2SCFGR_PLLI2SN_Pos | PLLP);
+}
+#endif /* SPDIFRX */
+
+/**
+  * @brief  Configure PLLI2S used for I2S1 domain clock
+  * @note PLL Source and PLLM Divider can be written only when PLL,
+  *       PLLI2S and PLLSAI(*) are disabled
+  * @note PLLN/PLLR can be written only when PLLI2S is disabled
+  * @note This  can be selected for I2S
+  * @rmtoll PLLCFGR      PLLSRC        LL_RCC_PLLI2S_ConfigDomain_I2S\n
+  *         PLLCFGR      PLLM          LL_RCC_PLLI2S_ConfigDomain_I2S\n
+  *         PLLI2SCFGR   PLLI2SSRC     LL_RCC_PLLI2S_ConfigDomain_I2S\n
+  *         PLLI2SCFGR   PLLI2SM       LL_RCC_PLLI2S_ConfigDomain_I2S\n
+  *         PLLI2SCFGR   PLLI2SN       LL_RCC_PLLI2S_ConfigDomain_I2S\n
+  *         PLLI2SCFGR   PLLI2SR       LL_RCC_PLLI2S_ConfigDomain_I2S
+  * @param  Source This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLSOURCE_HSI
+  *         @arg @ref LL_RCC_PLLSOURCE_HSE
+  *         @arg @ref LL_RCC_PLLI2SSOURCE_PIN (*)
+  *
+  *         (*) value not defined in all devices.
+  * @param  PLLM This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_2
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_3
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_4
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_5
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_6
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_7
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_8
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_9
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_10
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_11
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_12
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_13
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_14
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_15
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_16
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_17
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_18
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_19
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_20
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_21
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_22
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_23
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_24
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_25
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_26
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_27
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_28
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_29
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_30
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_31
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_32
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_33
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_34
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_35
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_36
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_37
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_38
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_39
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_40
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_41
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_42
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_43
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_44
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_45
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_46
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_47
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_48
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_49
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_50
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_51
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_52
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_53
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_54
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_55
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_56
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_57
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_58
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_59
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_60
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_61
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_62
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_63
+  * @param  PLLN Between 50/192(*) and 432
+  *
+  *         (*) value not defined in all devices.
+  * @param  PLLR This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLI2SR_DIV_2
+  *         @arg @ref LL_RCC_PLLI2SR_DIV_3
+  *         @arg @ref LL_RCC_PLLI2SR_DIV_4
+  *         @arg @ref LL_RCC_PLLI2SR_DIV_5
+  *         @arg @ref LL_RCC_PLLI2SR_DIV_6
+  *         @arg @ref LL_RCC_PLLI2SR_DIV_7
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLLI2S_ConfigDomain_I2S(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)
+{
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&RCC->PLLCFGR) + (Source & 0x80U)));
+  MODIFY_REG(*pReg, RCC_PLLCFGR_PLLSRC, (Source & (~0x80U)));
+#if defined(RCC_PLLI2SCFGR_PLLI2SM)
+  MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SM, PLLM);
+#else
+  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, PLLM);
+#endif /* RCC_PLLI2SCFGR_PLLI2SM */
+  MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SN | RCC_PLLI2SCFGR_PLLI2SR, PLLN << RCC_PLLI2SCFGR_PLLI2SN_Pos | PLLR);
+}
+
+/**
+  * @brief  Get I2SPLL multiplication factor for VCO
+  * @rmtoll PLLI2SCFGR  PLLI2SN      LL_RCC_PLLI2S_GetN
+  * @retval Between 50/192(*) and 432
+  *
+  *         (*) value not defined in all devices.
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetN(void)
+{
+  return (uint32_t)(READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SN) >> RCC_PLLI2SCFGR_PLLI2SN_Pos);
+}
+
+#if defined(RCC_PLLI2SCFGR_PLLI2SQ)
+/**
+  * @brief  Get I2SPLL division factor for PLLI2SQ
+  * @rmtoll PLLI2SCFGR  PLLI2SQ      LL_RCC_PLLI2S_GetQ
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_PLLI2SQ_DIV_2
+  *         @arg @ref LL_RCC_PLLI2SQ_DIV_3
+  *         @arg @ref LL_RCC_PLLI2SQ_DIV_4
+  *         @arg @ref LL_RCC_PLLI2SQ_DIV_5
+  *         @arg @ref LL_RCC_PLLI2SQ_DIV_6
+  *         @arg @ref LL_RCC_PLLI2SQ_DIV_7
+  *         @arg @ref LL_RCC_PLLI2SQ_DIV_8
+  *         @arg @ref LL_RCC_PLLI2SQ_DIV_9
+  *         @arg @ref LL_RCC_PLLI2SQ_DIV_10
+  *         @arg @ref LL_RCC_PLLI2SQ_DIV_11
+  *         @arg @ref LL_RCC_PLLI2SQ_DIV_12
+  *         @arg @ref LL_RCC_PLLI2SQ_DIV_13
+  *         @arg @ref LL_RCC_PLLI2SQ_DIV_14
+  *         @arg @ref LL_RCC_PLLI2SQ_DIV_15
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetQ(void)
+{
+  return (uint32_t)(READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SQ));
+}
+#endif /* RCC_PLLI2SCFGR_PLLI2SQ */
+
+/**
+  * @brief  Get I2SPLL division factor for PLLI2SR
+  * @note used for PLLI2SCLK (I2S clock)
+  * @rmtoll PLLI2SCFGR  PLLI2SR      LL_RCC_PLLI2S_GetR
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_PLLI2SR_DIV_2
+  *         @arg @ref LL_RCC_PLLI2SR_DIV_3
+  *         @arg @ref LL_RCC_PLLI2SR_DIV_4
+  *         @arg @ref LL_RCC_PLLI2SR_DIV_5
+  *         @arg @ref LL_RCC_PLLI2SR_DIV_6
+  *         @arg @ref LL_RCC_PLLI2SR_DIV_7
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetR(void)
+{
+  return (uint32_t)(READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SR));
+}
+
+#if defined(RCC_PLLI2SCFGR_PLLI2SP)
+/**
+  * @brief  Get I2SPLL division factor for PLLI2SP
+  * @note used for PLLSPDIFRXCLK (SPDIFRX clock)
+  * @rmtoll PLLI2SCFGR  PLLI2SP      LL_RCC_PLLI2S_GetP
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_PLLI2SP_DIV_2
+  *         @arg @ref LL_RCC_PLLI2SP_DIV_4
+  *         @arg @ref LL_RCC_PLLI2SP_DIV_6
+  *         @arg @ref LL_RCC_PLLI2SP_DIV_8
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetP(void)
+{
+  return (uint32_t)(READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SP));
+}
+#endif /* RCC_PLLI2SCFGR_PLLI2SP */
+
+#if defined(RCC_DCKCFGR_PLLI2SDIVQ)
+/**
+  * @brief  Get I2SPLL division factor for PLLI2SDIVQ
+  * @note used PLLSAICLK selected (SAI clock)
+  * @rmtoll DCKCFGR   PLLI2SDIVQ      LL_RCC_PLLI2S_GetDIVQ
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_1
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_2
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_3
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_4
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_5
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_6
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_7
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_8
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_9
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_10
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_11
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_12
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_13
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_14
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_15
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_16
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_17
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_18
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_19
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_20
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_21
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_22
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_23
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_24
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_25
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_26
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_27
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_28
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_29
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_30
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_31
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_32
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetDIVQ(void)
+{
+  return (uint32_t)(READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_PLLI2SDIVQ));
+}
+#endif /* RCC_DCKCFGR_PLLI2SDIVQ */
+
+#if defined(RCC_DCKCFGR_PLLI2SDIVR)
+/**
+  * @brief  Get I2SPLL division factor for PLLI2SDIVR
+  * @note used PLLSAICLK selected (SAI clock)
+  * @rmtoll DCKCFGR   PLLI2SDIVR      LL_RCC_PLLI2S_GetDIVR
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_1
+  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_2
+  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_3
+  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_4
+  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_5
+  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_6
+  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_7
+  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_8
+  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_9
+  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_10
+  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_11
+  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_12
+  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_13
+  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_14
+  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_15
+  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_16
+  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_17
+  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_18
+  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_19
+  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_20
+  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_21
+  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_22
+  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_23
+  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_24
+  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_25
+  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_26
+  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_27
+  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_28
+  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_29
+  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_30
+  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_31
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetDIVR(void)
+{
+  return (uint32_t)(READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_PLLI2SDIVR));
+}
+#endif /* RCC_DCKCFGR_PLLI2SDIVR */
+
+/**
+  * @brief  Get division factor for PLLI2S input clock
+  * @rmtoll PLLCFGR      PLLM          LL_RCC_PLLI2S_GetDivider\n
+  *         PLLI2SCFGR   PLLI2SM       LL_RCC_PLLI2S_GetDivider
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_2
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_3
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_4
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_5
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_6
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_7
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_8
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_9
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_10
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_11
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_12
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_13
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_14
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_15
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_16
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_17
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_18
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_19
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_20
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_21
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_22
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_23
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_24
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_25
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_26
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_27
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_28
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_29
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_30
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_31
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_32
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_33
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_34
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_35
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_36
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_37
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_38
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_39
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_40
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_41
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_42
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_43
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_44
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_45
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_46
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_47
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_48
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_49
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_50
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_51
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_52
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_53
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_54
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_55
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_56
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_57
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_58
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_59
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_60
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_61
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_62
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_63
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetDivider(void)
+{
+#if defined(RCC_PLLI2SCFGR_PLLI2SM)
+  return (uint32_t)(READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SM));
+#else
+  return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM));
+#endif /* RCC_PLLI2SCFGR_PLLI2SM */
+}
+
+/**
+  * @brief  Get the oscillator used as PLL clock source.
+  * @rmtoll PLLCFGR      PLLSRC        LL_RCC_PLLI2S_GetMainSource\n
+  *         PLLI2SCFGR   PLLI2SSRC     LL_RCC_PLLI2S_GetMainSource
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_PLLSOURCE_HSI
+  *         @arg @ref LL_RCC_PLLSOURCE_HSE
+  *         @arg @ref LL_RCC_PLLI2SSOURCE_PIN (*)
+  *
+  *         (*) value not defined in all devices.
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetMainSource(void)
+{
+#if defined(RCC_PLLI2SCFGR_PLLI2SSRC)
+  uint32_t pllsrc = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC);
+  uint32_t plli2sssrc0 = READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SSRC);
+  uint32_t plli2sssrc1 = READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SSRC) >> 15U;
+  return (uint32_t)(pllsrc | plli2sssrc0 | plli2sssrc1);
+#else
+  return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC));
+#endif /* RCC_PLLI2SCFGR_PLLI2SSRC */
+}
+
+/**
+  * @}
+  */
+#endif /* RCC_PLLI2S_SUPPORT */
+
+#if defined(RCC_PLLSAI_SUPPORT)
+/** @defgroup RCC_LL_EF_PLLSAI PLLSAI
+  * @{
+  */
+
+/**
+  * @brief  Enable PLLSAI
+  * @rmtoll CR           PLLSAION     LL_RCC_PLLSAI_Enable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLLSAI_Enable(void)
+{
+  SET_BIT(RCC->CR, RCC_CR_PLLSAION);
+}
+
+/**
+  * @brief  Disable PLLSAI
+  * @rmtoll CR           PLLSAION     LL_RCC_PLLSAI_Disable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLLSAI_Disable(void)
+{
+  CLEAR_BIT(RCC->CR, RCC_CR_PLLSAION);
+}
+
+/**
+  * @brief  Check if PLLSAI Ready
+  * @rmtoll CR           PLLSAIRDY    LL_RCC_PLLSAI_IsReady
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLLSAI_IsReady(void)
+{
+  return (READ_BIT(RCC->CR, RCC_CR_PLLSAIRDY) == (RCC_CR_PLLSAIRDY));
+}
+
+/**
+  * @brief  Configure PLLSAI used for SAI domain clock
+  * @note PLL Source and PLLM Divider can be written only when PLL,
+  *       PLLI2S and PLLSAI(*) are disabled
+  * @note PLLN/PLLQ can be written only when PLLSAI is disabled
+  * @note This can be selected for SAI
+  * @rmtoll PLLCFGR      PLLSRC        LL_RCC_PLLSAI_ConfigDomain_SAI\n
+  *         PLLCFGR      PLLM          LL_RCC_PLLSAI_ConfigDomain_SAI\n
+  *         PLLSAICFGR   PLLSAIM       LL_RCC_PLLSAI_ConfigDomain_SAI\n
+  *         PLLSAICFGR   PLLSAIN       LL_RCC_PLLSAI_ConfigDomain_SAI\n
+  *         PLLSAICFGR   PLLSAIQ       LL_RCC_PLLSAI_ConfigDomain_SAI\n
+  *         DCKCFGR      PLLSAIDIVQ    LL_RCC_PLLSAI_ConfigDomain_SAI
+  * @param  Source This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLSOURCE_HSI
+  *         @arg @ref LL_RCC_PLLSOURCE_HSE
+  * @param  PLLM This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_2
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_3
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_4
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_5
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_6
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_7
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_8
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_9
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_10
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_11
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_12
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_13
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_14
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_15
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_16
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_17
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_18
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_19
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_20
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_21
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_22
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_23
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_24
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_25
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_26
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_27
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_28
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_29
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_30
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_31
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_32
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_33
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_34
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_35
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_36
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_37
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_38
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_39
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_40
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_41
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_42
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_43
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_44
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_45
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_46
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_47
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_48
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_49
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_50
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_51
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_52
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_53
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_54
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_55
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_56
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_57
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_58
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_59
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_60
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_61
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_62
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_63
+  * @param  PLLN Between 49/50(*) and 432
+  *
+  *         (*) value not defined in all devices.
+  * @param  PLLQ This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLSAIQ_DIV_2
+  *         @arg @ref LL_RCC_PLLSAIQ_DIV_3
+  *         @arg @ref LL_RCC_PLLSAIQ_DIV_4
+  *         @arg @ref LL_RCC_PLLSAIQ_DIV_5
+  *         @arg @ref LL_RCC_PLLSAIQ_DIV_6
+  *         @arg @ref LL_RCC_PLLSAIQ_DIV_7
+  *         @arg @ref LL_RCC_PLLSAIQ_DIV_8
+  *         @arg @ref LL_RCC_PLLSAIQ_DIV_9
+  *         @arg @ref LL_RCC_PLLSAIQ_DIV_10
+  *         @arg @ref LL_RCC_PLLSAIQ_DIV_11
+  *         @arg @ref LL_RCC_PLLSAIQ_DIV_12
+  *         @arg @ref LL_RCC_PLLSAIQ_DIV_13
+  *         @arg @ref LL_RCC_PLLSAIQ_DIV_14
+  *         @arg @ref LL_RCC_PLLSAIQ_DIV_15
+  * @param  PLLDIVQ This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_1
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_2
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_3
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_4
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_5
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_6
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_7
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_8
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_9
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_10
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_11
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_12
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_13
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_14
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_15
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_16
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_17
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_18
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_19
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_20
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_21
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_22
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_23
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_24
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_25
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_26
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_27
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_28
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_29
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_30
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_31
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_32
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLLSAI_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ, uint32_t PLLDIVQ)
+{
+  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, Source);
+#if defined(RCC_PLLSAICFGR_PLLSAIM)
+  MODIFY_REG(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIM, PLLM);
+#else
+  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, PLLM);
+#endif /* RCC_PLLSAICFGR_PLLSAIM */
+  MODIFY_REG(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIN | RCC_PLLSAICFGR_PLLSAIQ, PLLN << RCC_PLLSAICFGR_PLLSAIN_Pos | PLLQ);
+  MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLSAIDIVQ, PLLDIVQ);
+}
+
+#if defined(RCC_PLLSAICFGR_PLLSAIP)
+/**
+  * @brief Configure PLLSAI used for 48Mhz domain clock
+  * @note PLL Source and PLLM Divider can be written only when PLL,
+  *       PLLI2S and PLLSAI(*) are disabled
+  * @note PLLN/PLLP can be written only when PLLSAI is disabled
+  * @note This  can be selected for USB, RNG, SDIO
+  * @rmtoll PLLCFGR      PLLSRC        LL_RCC_PLLSAI_ConfigDomain_48M\n
+  *         PLLCFGR      PLLM          LL_RCC_PLLSAI_ConfigDomain_48M\n
+  *         PLLSAICFGR   PLLSAIM       LL_RCC_PLLSAI_ConfigDomain_48M\n
+  *         PLLSAICFGR   PLLSAIN       LL_RCC_PLLSAI_ConfigDomain_48M\n
+  *         PLLSAICFGR   PLLSAIP       LL_RCC_PLLSAI_ConfigDomain_48M
+  * @param  Source This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLSOURCE_HSI
+  *         @arg @ref LL_RCC_PLLSOURCE_HSE
+  * @param  PLLM This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_2
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_3
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_4
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_5
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_6
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_7
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_8
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_9
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_10
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_11
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_12
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_13
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_14
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_15
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_16
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_17
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_18
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_19
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_20
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_21
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_22
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_23
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_24
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_25
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_26
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_27
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_28
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_29
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_30
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_31
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_32
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_33
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_34
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_35
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_36
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_37
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_38
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_39
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_40
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_41
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_42
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_43
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_44
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_45
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_46
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_47
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_48
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_49
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_50
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_51
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_52
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_53
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_54
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_55
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_56
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_57
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_58
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_59
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_60
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_61
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_62
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_63
+  * @param  PLLN Between 50 and 432
+  * @param  PLLP This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLSAIP_DIV_2
+  *         @arg @ref LL_RCC_PLLSAIP_DIV_4
+  *         @arg @ref LL_RCC_PLLSAIP_DIV_6
+  *         @arg @ref LL_RCC_PLLSAIP_DIV_8
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLLSAI_ConfigDomain_48M(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP)
+{
+  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, Source);
+#if defined(RCC_PLLSAICFGR_PLLSAIM)
+  MODIFY_REG(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIM, PLLM);
+#else
+  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, PLLM);
+#endif /* RCC_PLLSAICFGR_PLLSAIM */
+  MODIFY_REG(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIN | RCC_PLLSAICFGR_PLLSAIP, PLLN << RCC_PLLSAICFGR_PLLSAIN_Pos | PLLP);
+}
+#endif /* RCC_PLLSAICFGR_PLLSAIP */
+
+#if defined(LTDC)
+/**
+  * @brief  Configure PLLSAI used for LTDC domain clock
+  * @note PLL Source and PLLM Divider can be written only when PLL,
+  *       PLLI2S and PLLSAI(*) are disabled
+  * @note PLLN/PLLR can be written only when PLLSAI is disabled
+  * @note This  can be selected for LTDC
+  * @rmtoll PLLCFGR      PLLSRC        LL_RCC_PLLSAI_ConfigDomain_LTDC\n
+  *         PLLCFGR      PLLM          LL_RCC_PLLSAI_ConfigDomain_LTDC\n
+  *         PLLSAICFGR   PLLSAIN       LL_RCC_PLLSAI_ConfigDomain_LTDC\n
+  *         PLLSAICFGR   PLLSAIR       LL_RCC_PLLSAI_ConfigDomain_LTDC\n
+  *         DCKCFGR      PLLSAIDIVR    LL_RCC_PLLSAI_ConfigDomain_LTDC
+  * @param  Source This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLSOURCE_HSI
+  *         @arg @ref LL_RCC_PLLSOURCE_HSE
+  * @param  PLLM This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_2
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_3
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_4
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_5
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_6
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_7
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_8
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_9
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_10
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_11
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_12
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_13
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_14
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_15
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_16
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_17
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_18
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_19
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_20
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_21
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_22
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_23
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_24
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_25
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_26
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_27
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_28
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_29
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_30
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_31
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_32
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_33
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_34
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_35
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_36
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_37
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_38
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_39
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_40
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_41
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_42
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_43
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_44
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_45
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_46
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_47
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_48
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_49
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_50
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_51
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_52
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_53
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_54
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_55
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_56
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_57
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_58
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_59
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_60
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_61
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_62
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_63
+  * @param  PLLN Between 49/50(*) and 432
+  *
+  *         (*) value not defined in all devices.
+  * @param  PLLR This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLSAIR_DIV_2
+  *         @arg @ref LL_RCC_PLLSAIR_DIV_3
+  *         @arg @ref LL_RCC_PLLSAIR_DIV_4
+  *         @arg @ref LL_RCC_PLLSAIR_DIV_5
+  *         @arg @ref LL_RCC_PLLSAIR_DIV_6
+  *         @arg @ref LL_RCC_PLLSAIR_DIV_7
+  * @param  PLLDIVR This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLSAIDIVR_DIV_2
+  *         @arg @ref LL_RCC_PLLSAIDIVR_DIV_4
+  *         @arg @ref LL_RCC_PLLSAIDIVR_DIV_8
+  *         @arg @ref LL_RCC_PLLSAIDIVR_DIV_16
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLLSAI_ConfigDomain_LTDC(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR, uint32_t PLLDIVR)
+{
+  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, Source | PLLM);
+  MODIFY_REG(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIN | RCC_PLLSAICFGR_PLLSAIR, PLLN << RCC_PLLSAICFGR_PLLSAIN_Pos | PLLR);
+  MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLSAIDIVR, PLLDIVR);
+}
+#endif /* LTDC */
+
+/**
+  * @brief  Get division factor for PLLSAI input clock
+  * @rmtoll PLLCFGR      PLLM          LL_RCC_PLLSAI_GetDivider\n
+  *         PLLSAICFGR   PLLSAIM       LL_RCC_PLLSAI_GetDivider
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_2
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_3
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_4
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_5
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_6
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_7
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_8
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_9
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_10
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_11
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_12
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_13
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_14
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_15
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_16
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_17
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_18
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_19
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_20
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_21
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_22
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_23
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_24
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_25
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_26
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_27
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_28
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_29
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_30
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_31
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_32
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_33
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_34
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_35
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_36
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_37
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_38
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_39
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_40
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_41
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_42
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_43
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_44
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_45
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_46
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_47
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_48
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_49
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_50
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_51
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_52
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_53
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_54
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_55
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_56
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_57
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_58
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_59
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_60
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_61
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_62
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_63
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetDivider(void)
+{
+#if defined(RCC_PLLSAICFGR_PLLSAIM)
+  return (uint32_t)(READ_BIT(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIM));
+#else
+  return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM));
+#endif /* RCC_PLLSAICFGR_PLLSAIM */
+}
+
+/**
+  * @brief  Get SAIPLL multiplication factor for VCO
+  * @rmtoll PLLSAICFGR  PLLSAIN      LL_RCC_PLLSAI_GetN
+  * @retval Between 49/50(*) and 432
+  *
+  *         (*) value not defined in all devices.
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetN(void)
+{
+  return (uint32_t)(READ_BIT(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIN) >> RCC_PLLSAICFGR_PLLSAIN_Pos);
+}
+
+/**
+  * @brief  Get SAIPLL division factor for PLLSAIQ
+  * @rmtoll PLLSAICFGR  PLLSAIQ      LL_RCC_PLLSAI_GetQ
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_PLLSAIQ_DIV_2
+  *         @arg @ref LL_RCC_PLLSAIQ_DIV_3
+  *         @arg @ref LL_RCC_PLLSAIQ_DIV_4
+  *         @arg @ref LL_RCC_PLLSAIQ_DIV_5
+  *         @arg @ref LL_RCC_PLLSAIQ_DIV_6
+  *         @arg @ref LL_RCC_PLLSAIQ_DIV_7
+  *         @arg @ref LL_RCC_PLLSAIQ_DIV_8
+  *         @arg @ref LL_RCC_PLLSAIQ_DIV_9
+  *         @arg @ref LL_RCC_PLLSAIQ_DIV_10
+  *         @arg @ref LL_RCC_PLLSAIQ_DIV_11
+  *         @arg @ref LL_RCC_PLLSAIQ_DIV_12
+  *         @arg @ref LL_RCC_PLLSAIQ_DIV_13
+  *         @arg @ref LL_RCC_PLLSAIQ_DIV_14
+  *         @arg @ref LL_RCC_PLLSAIQ_DIV_15
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetQ(void)
+{
+  return (uint32_t)(READ_BIT(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIQ));
+}
+
+#if defined(RCC_PLLSAICFGR_PLLSAIR)
+/**
+  * @brief  Get SAIPLL division factor for PLLSAIR
+  * @note used for PLLSAICLK (SAI clock)
+  * @rmtoll PLLSAICFGR  PLLSAIR      LL_RCC_PLLSAI_GetR
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_PLLSAIR_DIV_2
+  *         @arg @ref LL_RCC_PLLSAIR_DIV_3
+  *         @arg @ref LL_RCC_PLLSAIR_DIV_4
+  *         @arg @ref LL_RCC_PLLSAIR_DIV_5
+  *         @arg @ref LL_RCC_PLLSAIR_DIV_6
+  *         @arg @ref LL_RCC_PLLSAIR_DIV_7
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetR(void)
+{
+  return (uint32_t)(READ_BIT(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIR));
+}
+#endif /* RCC_PLLSAICFGR_PLLSAIR */
+
+#if defined(RCC_PLLSAICFGR_PLLSAIP)
+/**
+  * @brief  Get SAIPLL division factor for PLLSAIP
+  * @note used for PLL48MCLK (48M domain clock)
+  * @rmtoll PLLSAICFGR  PLLSAIP      LL_RCC_PLLSAI_GetP
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_PLLSAIP_DIV_2
+  *         @arg @ref LL_RCC_PLLSAIP_DIV_4
+  *         @arg @ref LL_RCC_PLLSAIP_DIV_6
+  *         @arg @ref LL_RCC_PLLSAIP_DIV_8
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetP(void)
+{
+  return (uint32_t)(READ_BIT(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIP));
+}
+#endif /* RCC_PLLSAICFGR_PLLSAIP */
+
+/**
+  * @brief  Get SAIPLL division factor for PLLSAIDIVQ
+  * @note used PLLSAICLK selected (SAI clock)
+  * @rmtoll DCKCFGR   PLLSAIDIVQ      LL_RCC_PLLSAI_GetDIVQ
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_1
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_2
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_3
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_4
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_5
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_6
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_7
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_8
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_9
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_10
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_11
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_12
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_13
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_14
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_15
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_16
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_17
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_18
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_19
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_20
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_21
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_22
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_23
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_24
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_25
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_26
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_27
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_28
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_29
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_30
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_31
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_32
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetDIVQ(void)
+{
+  return (uint32_t)(READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_PLLSAIDIVQ));
+}
+
+#if defined(RCC_DCKCFGR_PLLSAIDIVR)
+/**
+  * @brief  Get SAIPLL division factor for PLLSAIDIVR
+  * @note used for LTDC domain clock
+  * @rmtoll DCKCFGR  PLLSAIDIVR      LL_RCC_PLLSAI_GetDIVR
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_PLLSAIDIVR_DIV_2
+  *         @arg @ref LL_RCC_PLLSAIDIVR_DIV_4
+  *         @arg @ref LL_RCC_PLLSAIDIVR_DIV_8
+  *         @arg @ref LL_RCC_PLLSAIDIVR_DIV_16
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetDIVR(void)
+{
+  return (uint32_t)(READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_PLLSAIDIVR));
+}
+#endif /* RCC_DCKCFGR_PLLSAIDIVR */
+
+/**
+  * @}
+  */
+#endif /* RCC_PLLSAI_SUPPORT */
+
+/** @defgroup RCC_LL_EF_FLAG_Management FLAG Management
+  * @{
+  */
+
+/**
+  * @brief  Clear LSI ready interrupt flag
+  * @rmtoll CIR         LSIRDYC       LL_RCC_ClearFlag_LSIRDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_ClearFlag_LSIRDY(void)
+{
+  SET_BIT(RCC->CIR, RCC_CIR_LSIRDYC);
+}
+
+/**
+  * @brief  Clear LSE ready interrupt flag
+  * @rmtoll CIR         LSERDYC       LL_RCC_ClearFlag_LSERDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_ClearFlag_LSERDY(void)
+{
+  SET_BIT(RCC->CIR, RCC_CIR_LSERDYC);
+}
+
+/**
+  * @brief  Clear HSI ready interrupt flag
+  * @rmtoll CIR         HSIRDYC       LL_RCC_ClearFlag_HSIRDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_ClearFlag_HSIRDY(void)
+{
+  SET_BIT(RCC->CIR, RCC_CIR_HSIRDYC);
+}
+
+/**
+  * @brief  Clear HSE ready interrupt flag
+  * @rmtoll CIR         HSERDYC       LL_RCC_ClearFlag_HSERDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_ClearFlag_HSERDY(void)
+{
+  SET_BIT(RCC->CIR, RCC_CIR_HSERDYC);
+}
+
+/**
+  * @brief  Clear PLL ready interrupt flag
+  * @rmtoll CIR         PLLRDYC       LL_RCC_ClearFlag_PLLRDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_ClearFlag_PLLRDY(void)
+{
+  SET_BIT(RCC->CIR, RCC_CIR_PLLRDYC);
+}
+
+#if defined(RCC_PLLI2S_SUPPORT)
+/**
+  * @brief  Clear PLLI2S ready interrupt flag
+  * @rmtoll CIR         PLLI2SRDYC   LL_RCC_ClearFlag_PLLI2SRDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_ClearFlag_PLLI2SRDY(void)
+{
+  SET_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYC);
+}
+
+#endif /* RCC_PLLI2S_SUPPORT */
+
+#if defined(RCC_PLLSAI_SUPPORT)
+/**
+  * @brief  Clear PLLSAI ready interrupt flag
+  * @rmtoll CIR         PLLSAIRDYC   LL_RCC_ClearFlag_PLLSAIRDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_ClearFlag_PLLSAIRDY(void)
+{
+  SET_BIT(RCC->CIR, RCC_CIR_PLLSAIRDYC);
+}
+
+#endif /* RCC_PLLSAI_SUPPORT */
+
+/**
+  * @brief  Clear Clock security system interrupt flag
+  * @rmtoll CIR         CSSC          LL_RCC_ClearFlag_HSECSS
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_ClearFlag_HSECSS(void)
+{
+  SET_BIT(RCC->CIR, RCC_CIR_CSSC);
+}
+
+/**
+  * @brief  Check if LSI ready interrupt occurred or not
+  * @rmtoll CIR         LSIRDYF       LL_RCC_IsActiveFlag_LSIRDY
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSIRDY(void)
+{
+  return (READ_BIT(RCC->CIR, RCC_CIR_LSIRDYF) == (RCC_CIR_LSIRDYF));
+}
+
+/**
+  * @brief  Check if LSE ready interrupt occurred or not
+  * @rmtoll CIR         LSERDYF       LL_RCC_IsActiveFlag_LSERDY
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSERDY(void)
+{
+  return (READ_BIT(RCC->CIR, RCC_CIR_LSERDYF) == (RCC_CIR_LSERDYF));
+}
+
+/**
+  * @brief  Check if HSI ready interrupt occurred or not
+  * @rmtoll CIR         HSIRDYF       LL_RCC_IsActiveFlag_HSIRDY
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSIRDY(void)
+{
+  return (READ_BIT(RCC->CIR, RCC_CIR_HSIRDYF) == (RCC_CIR_HSIRDYF));
+}
+
+/**
+  * @brief  Check if HSE ready interrupt occurred or not
+  * @rmtoll CIR         HSERDYF       LL_RCC_IsActiveFlag_HSERDY
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSERDY(void)
+{
+  return (READ_BIT(RCC->CIR, RCC_CIR_HSERDYF) == (RCC_CIR_HSERDYF));
+}
+
+/**
+  * @brief  Check if PLL ready interrupt occurred or not
+  * @rmtoll CIR         PLLRDYF       LL_RCC_IsActiveFlag_PLLRDY
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLRDY(void)
+{
+  return (READ_BIT(RCC->CIR, RCC_CIR_PLLRDYF) == (RCC_CIR_PLLRDYF));
+}
+
+#if defined(RCC_PLLI2S_SUPPORT)
+/**
+  * @brief  Check if PLLI2S ready interrupt occurred or not
+  * @rmtoll CIR         PLLI2SRDYF   LL_RCC_IsActiveFlag_PLLI2SRDY
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLI2SRDY(void)
+{
+  return (READ_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYF) == (RCC_CIR_PLLI2SRDYF));
+}
+#endif /* RCC_PLLI2S_SUPPORT */
+
+#if defined(RCC_PLLSAI_SUPPORT)
+/**
+  * @brief  Check if PLLSAI ready interrupt occurred or not
+  * @rmtoll CIR         PLLSAIRDYF   LL_RCC_IsActiveFlag_PLLSAIRDY
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLSAIRDY(void)
+{
+  return (READ_BIT(RCC->CIR, RCC_CIR_PLLSAIRDYF) == (RCC_CIR_PLLSAIRDYF));
+}
+#endif /* RCC_PLLSAI_SUPPORT */
+
+/**
+  * @brief  Check if Clock security system interrupt occurred or not
+  * @rmtoll CIR         CSSF          LL_RCC_IsActiveFlag_HSECSS
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSECSS(void)
+{
+  return (READ_BIT(RCC->CIR, RCC_CIR_CSSF) == (RCC_CIR_CSSF));
+}
+
+/**
+  * @brief  Check if RCC flag Independent Watchdog reset is set or not.
+  * @rmtoll CSR          IWDGRSTF      LL_RCC_IsActiveFlag_IWDGRST
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_IWDGRST(void)
+{
+  return (READ_BIT(RCC->CSR, RCC_CSR_IWDGRSTF) == (RCC_CSR_IWDGRSTF));
+}
+
+/**
+  * @brief  Check if RCC flag Low Power reset is set or not.
+  * @rmtoll CSR          LPWRRSTF      LL_RCC_IsActiveFlag_LPWRRST
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LPWRRST(void)
+{
+  return (READ_BIT(RCC->CSR, RCC_CSR_LPWRRSTF) == (RCC_CSR_LPWRRSTF));
+}
+
+/**
+  * @brief  Check if RCC flag Pin reset is set or not.
+  * @rmtoll CSR          PINRSTF       LL_RCC_IsActiveFlag_PINRST
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PINRST(void)
+{
+  return (READ_BIT(RCC->CSR, RCC_CSR_PINRSTF) == (RCC_CSR_PINRSTF));
+}
+
+/**
+  * @brief  Check if RCC flag POR/PDR reset is set or not.
+  * @rmtoll CSR          PORRSTF       LL_RCC_IsActiveFlag_PORRST
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PORRST(void)
+{
+  return (READ_BIT(RCC->CSR, RCC_CSR_PORRSTF) == (RCC_CSR_PORRSTF));
+}
+
+/**
+  * @brief  Check if RCC flag Software reset is set or not.
+  * @rmtoll CSR          SFTRSTF       LL_RCC_IsActiveFlag_SFTRST
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SFTRST(void)
+{
+  return (READ_BIT(RCC->CSR, RCC_CSR_SFTRSTF) == (RCC_CSR_SFTRSTF));
+}
+
+/**
+  * @brief  Check if RCC flag Window Watchdog reset is set or not.
+  * @rmtoll CSR          WWDGRSTF      LL_RCC_IsActiveFlag_WWDGRST
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_WWDGRST(void)
+{
+  return (READ_BIT(RCC->CSR, RCC_CSR_WWDGRSTF) == (RCC_CSR_WWDGRSTF));
+}
+
+#if defined(RCC_CSR_BORRSTF)
+/**
+  * @brief  Check if RCC flag BOR reset is set or not.
+  * @rmtoll CSR          BORRSTF       LL_RCC_IsActiveFlag_BORRST
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_BORRST(void)
+{
+  return (READ_BIT(RCC->CSR, RCC_CSR_BORRSTF) == (RCC_CSR_BORRSTF));
+}
+#endif /* RCC_CSR_BORRSTF */
+
+/**
+  * @brief  Set RMVF bit to clear the reset flags.
+  * @rmtoll CSR          RMVF          LL_RCC_ClearResetFlags
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_ClearResetFlags(void)
+{
+  SET_BIT(RCC->CSR, RCC_CSR_RMVF);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EF_IT_Management IT Management
+  * @{
+  */
+
+/**
+  * @brief  Enable LSI ready interrupt
+  * @rmtoll CIR         LSIRDYIE      LL_RCC_EnableIT_LSIRDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_EnableIT_LSIRDY(void)
+{
+  SET_BIT(RCC->CIR, RCC_CIR_LSIRDYIE);
+}
+
+/**
+  * @brief  Enable LSE ready interrupt
+  * @rmtoll CIR         LSERDYIE      LL_RCC_EnableIT_LSERDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_EnableIT_LSERDY(void)
+{
+  SET_BIT(RCC->CIR, RCC_CIR_LSERDYIE);
+}
+
+/**
+  * @brief  Enable HSI ready interrupt
+  * @rmtoll CIR         HSIRDYIE      LL_RCC_EnableIT_HSIRDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_EnableIT_HSIRDY(void)
+{
+  SET_BIT(RCC->CIR, RCC_CIR_HSIRDYIE);
+}
+
+/**
+  * @brief  Enable HSE ready interrupt
+  * @rmtoll CIR         HSERDYIE      LL_RCC_EnableIT_HSERDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_EnableIT_HSERDY(void)
+{
+  SET_BIT(RCC->CIR, RCC_CIR_HSERDYIE);
+}
+
+/**
+  * @brief  Enable PLL ready interrupt
+  * @rmtoll CIR         PLLRDYIE      LL_RCC_EnableIT_PLLRDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_EnableIT_PLLRDY(void)
+{
+  SET_BIT(RCC->CIR, RCC_CIR_PLLRDYIE);
+}
+
+#if defined(RCC_PLLI2S_SUPPORT)
+/**
+  * @brief  Enable PLLI2S ready interrupt
+  * @rmtoll CIR         PLLI2SRDYIE  LL_RCC_EnableIT_PLLI2SRDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_EnableIT_PLLI2SRDY(void)
+{
+  SET_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYIE);
+}
+#endif /* RCC_PLLI2S_SUPPORT */
+
+#if defined(RCC_PLLSAI_SUPPORT)
+/**
+  * @brief  Enable PLLSAI ready interrupt
+  * @rmtoll CIR         PLLSAIRDYIE  LL_RCC_EnableIT_PLLSAIRDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_EnableIT_PLLSAIRDY(void)
+{
+  SET_BIT(RCC->CIR, RCC_CIR_PLLSAIRDYIE);
+}
+#endif /* RCC_PLLSAI_SUPPORT */
+
+/**
+  * @brief  Disable LSI ready interrupt
+  * @rmtoll CIR         LSIRDYIE      LL_RCC_DisableIT_LSIRDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_DisableIT_LSIRDY(void)
+{
+  CLEAR_BIT(RCC->CIR, RCC_CIR_LSIRDYIE);
+}
+
+/**
+  * @brief  Disable LSE ready interrupt
+  * @rmtoll CIR         LSERDYIE      LL_RCC_DisableIT_LSERDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_DisableIT_LSERDY(void)
+{
+  CLEAR_BIT(RCC->CIR, RCC_CIR_LSERDYIE);
+}
+
+/**
+  * @brief  Disable HSI ready interrupt
+  * @rmtoll CIR         HSIRDYIE      LL_RCC_DisableIT_HSIRDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_DisableIT_HSIRDY(void)
+{
+  CLEAR_BIT(RCC->CIR, RCC_CIR_HSIRDYIE);
+}
+
+/**
+  * @brief  Disable HSE ready interrupt
+  * @rmtoll CIR         HSERDYIE      LL_RCC_DisableIT_HSERDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_DisableIT_HSERDY(void)
+{
+  CLEAR_BIT(RCC->CIR, RCC_CIR_HSERDYIE);
+}
+
+/**
+  * @brief  Disable PLL ready interrupt
+  * @rmtoll CIR         PLLRDYIE      LL_RCC_DisableIT_PLLRDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_DisableIT_PLLRDY(void)
+{
+  CLEAR_BIT(RCC->CIR, RCC_CIR_PLLRDYIE);
+}
+
+#if defined(RCC_PLLI2S_SUPPORT)
+/**
+  * @brief  Disable PLLI2S ready interrupt
+  * @rmtoll CIR         PLLI2SRDYIE  LL_RCC_DisableIT_PLLI2SRDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_DisableIT_PLLI2SRDY(void)
+{
+  CLEAR_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYIE);
+}
+
+#endif /* RCC_PLLI2S_SUPPORT */
+
+#if defined(RCC_PLLSAI_SUPPORT)
+/**
+  * @brief  Disable PLLSAI ready interrupt
+  * @rmtoll CIR         PLLSAIRDYIE  LL_RCC_DisableIT_PLLSAIRDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_DisableIT_PLLSAIRDY(void)
+{
+  CLEAR_BIT(RCC->CIR, RCC_CIR_PLLSAIRDYIE);
+}
+#endif /* RCC_PLLSAI_SUPPORT */
+
+/**
+  * @brief  Checks if LSI ready interrupt source is enabled or disabled.
+  * @rmtoll CIR         LSIRDYIE      LL_RCC_IsEnabledIT_LSIRDY
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSIRDY(void)
+{
+  return (READ_BIT(RCC->CIR, RCC_CIR_LSIRDYIE) == (RCC_CIR_LSIRDYIE));
+}
+
+/**
+  * @brief  Checks if LSE ready interrupt source is enabled or disabled.
+  * @rmtoll CIR         LSERDYIE      LL_RCC_IsEnabledIT_LSERDY
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSERDY(void)
+{
+  return (READ_BIT(RCC->CIR, RCC_CIR_LSERDYIE) == (RCC_CIR_LSERDYIE));
+}
+
+/**
+  * @brief  Checks if HSI ready interrupt source is enabled or disabled.
+  * @rmtoll CIR         HSIRDYIE      LL_RCC_IsEnabledIT_HSIRDY
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSIRDY(void)
+{
+  return (READ_BIT(RCC->CIR, RCC_CIR_HSIRDYIE) == (RCC_CIR_HSIRDYIE));
+}
+
+/**
+  * @brief  Checks if HSE ready interrupt source is enabled or disabled.
+  * @rmtoll CIR         HSERDYIE      LL_RCC_IsEnabledIT_HSERDY
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSERDY(void)
+{
+  return (READ_BIT(RCC->CIR, RCC_CIR_HSERDYIE) == (RCC_CIR_HSERDYIE));
+}
+
+/**
+  * @brief  Checks if PLL ready interrupt source is enabled or disabled.
+  * @rmtoll CIR         PLLRDYIE      LL_RCC_IsEnabledIT_PLLRDY
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLRDY(void)
+{
+  return (READ_BIT(RCC->CIR, RCC_CIR_PLLRDYIE) == (RCC_CIR_PLLRDYIE));
+}
+
+#if defined(RCC_PLLI2S_SUPPORT)
+/**
+  * @brief  Checks if PLLI2S ready interrupt source is enabled or disabled.
+  * @rmtoll CIR         PLLI2SRDYIE  LL_RCC_IsEnabledIT_PLLI2SRDY
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLI2SRDY(void)
+{
+  return (READ_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYIE) == (RCC_CIR_PLLI2SRDYIE));
+}
+
+#endif /* RCC_PLLI2S_SUPPORT */
+
+#if defined(RCC_PLLSAI_SUPPORT)
+/**
+  * @brief  Checks if PLLSAI ready interrupt source is enabled or disabled.
+  * @rmtoll CIR         PLLSAIRDYIE  LL_RCC_IsEnabledIT_PLLSAIRDY
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLSAIRDY(void)
+{
+  return (READ_BIT(RCC->CIR, RCC_CIR_PLLSAIRDYIE) == (RCC_CIR_PLLSAIRDYIE));
+}
+#endif /* RCC_PLLSAI_SUPPORT */
+
+/**
+  * @}
+  */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup RCC_LL_EF_Init De-initialization function
+  * @{
+  */
+ErrorStatus LL_RCC_DeInit(void);
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EF_Get_Freq Get system and peripherals clocks frequency functions
+  * @{
+  */
+void        LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks);
+#if defined(FMPI2C1)
+uint32_t LL_RCC_GetFMPI2CClockFreq(uint32_t FMPI2CxSource);
+#endif /* FMPI2C1 */
+#if defined(LPTIM1)
+uint32_t    LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource);
+#endif /* LPTIM1 */
+#if defined(SAI1)
+uint32_t    LL_RCC_GetSAIClockFreq(uint32_t SAIxSource);
+#endif /* SAI1 */
+#if defined(SDIO)
+uint32_t    LL_RCC_GetSDIOClockFreq(uint32_t SDIOxSource);
+#endif /* SDIO */
+#if defined(RNG)
+uint32_t    LL_RCC_GetRNGClockFreq(uint32_t RNGxSource);
+#endif /* RNG */
+#if defined(USB_OTG_FS) || defined(USB_OTG_HS)
+uint32_t    LL_RCC_GetUSBClockFreq(uint32_t USBxSource);
+#endif /* USB_OTG_FS || USB_OTG_HS */
+#if defined(DFSDM1_Channel0)
+uint32_t    LL_RCC_GetDFSDMClockFreq(uint32_t DFSDMxSource);
+uint32_t    LL_RCC_GetDFSDMAudioClockFreq(uint32_t DFSDMxSource);
+#endif /* DFSDM1_Channel0 */
+uint32_t    LL_RCC_GetI2SClockFreq(uint32_t I2SxSource);
+#if defined(CEC)
+uint32_t    LL_RCC_GetCECClockFreq(uint32_t CECxSource);
+#endif /* CEC */
+#if defined(LTDC)
+uint32_t    LL_RCC_GetLTDCClockFreq(uint32_t LTDCxSource);
+#endif /* LTDC */
+#if defined(SPDIFRX)
+uint32_t    LL_RCC_GetSPDIFRXClockFreq(uint32_t SPDIFRXxSource);
+#endif /* SPDIFRX */
+#if defined(DSI)
+uint32_t    LL_RCC_GetDSIClockFreq(uint32_t DSIxSource);
+#endif /* DSI */
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* defined(RCC) */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_LL_RCC_H */
+
diff --git a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_sdmmc.h b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_sdmmc.h
new file mode 100644
index 0000000..110ed30
--- /dev/null
+++ b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_sdmmc.h
@@ -0,0 +1,1141 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_ll_sdmmc.h
+  * @author  MCD Application Team
+  * @brief   Header file of SDMMC HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2016 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */ 
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32F4xx_LL_SDMMC_H
+#define STM32F4xx_LL_SDMMC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if defined(SDIO)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_Driver
+  * @{
+  */
+
+/** @addtogroup SDMMC_LL
+  * @{
+  */ 
+
+/* Exported types ------------------------------------------------------------*/ 
+/** @defgroup SDMMC_LL_Exported_Types SDMMC_LL Exported Types
+  * @{
+  */
+  
+/** 
+  * @brief  SDMMC Configuration Structure definition  
+  */
+typedef struct
+{
+  uint32_t ClockEdge;            /*!< Specifies the clock transition on which the bit capture is made.
+                                      This parameter can be a value of @ref SDMMC_LL_Clock_Edge                 */
+
+  uint32_t ClockBypass;          /*!< Specifies whether the SDMMC Clock divider bypass is
+                                      enabled or disabled.
+                                      This parameter can be a value of @ref SDMMC_LL_Clock_Bypass               */
+
+  uint32_t ClockPowerSave;       /*!< Specifies whether SDMMC Clock output is enabled or
+                                      disabled when the bus is idle.
+                                      This parameter can be a value of @ref SDMMC_LL_Clock_Power_Save           */
+
+  uint32_t BusWide;              /*!< Specifies the SDMMC bus width.
+                                      This parameter can be a value of @ref SDMMC_LL_Bus_Wide                   */
+
+  uint32_t HardwareFlowControl;  /*!< Specifies whether the SDMMC hardware flow control is enabled or disabled.
+                                      This parameter can be a value of @ref SDMMC_LL_Hardware_Flow_Control      */
+
+  uint32_t ClockDiv;             /*!< Specifies the clock frequency of the SDMMC controller.
+                                      This parameter can be a value between Min_Data = 0 and Max_Data = 255 */  
+  
+}SDIO_InitTypeDef;
+  
+
+/** 
+  * @brief  SDMMC Command Control structure 
+  */
+typedef struct                                                                                            
+{
+  uint32_t Argument;            /*!< Specifies the SDMMC command argument which is sent
+                                     to a card as part of a command message. If a command
+                                     contains an argument, it must be loaded into this register
+                                     before writing the command to the command register.              */
+
+  uint32_t CmdIndex;            /*!< Specifies the SDMMC command index. It must be Min_Data = 0 and 
+                                     Max_Data = 64                                                    */
+
+  uint32_t Response;            /*!< Specifies the SDMMC response type.
+                                     This parameter can be a value of @ref SDMMC_LL_Response_Type         */
+
+  uint32_t WaitForInterrupt;    /*!< Specifies whether SDMMC wait for interrupt request is 
+                                     enabled or disabled.
+                                     This parameter can be a value of @ref SDMMC_LL_Wait_Interrupt_State  */
+
+  uint32_t CPSM;                /*!< Specifies whether SDMMC Command path state machine (CPSM)
+                                     is enabled or disabled.
+                                     This parameter can be a value of @ref SDMMC_LL_CPSM_State            */
+}SDIO_CmdInitTypeDef;
+
+
+/** 
+  * @brief  SDMMC Data Control structure 
+  */
+typedef struct
+{
+  uint32_t DataTimeOut;         /*!< Specifies the data timeout period in card bus clock periods.  */
+
+  uint32_t DataLength;          /*!< Specifies the number of data bytes to be transferred.         */
+ 
+  uint32_t DataBlockSize;       /*!< Specifies the data block size for block transfer.
+                                     This parameter can be a value of @ref SDMMC_LL_Data_Block_Size    */
+ 
+  uint32_t TransferDir;         /*!< Specifies the data transfer direction, whether the transfer
+                                     is a read or write.
+                                     This parameter can be a value of @ref SDMMC_LL_Transfer_Direction */
+ 
+  uint32_t TransferMode;        /*!< Specifies whether data transfer is in stream or block mode.
+                                     This parameter can be a value of @ref SDMMC_LL_Transfer_Type      */
+ 
+  uint32_t DPSM;                /*!< Specifies whether SDMMC Data path state machine (DPSM)
+                                     is enabled or disabled.
+                                     This parameter can be a value of @ref SDMMC_LL_DPSM_State         */
+}SDIO_DataInitTypeDef;
+
+/**
+  * @}
+  */
+  
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup SDMMC_LL_Exported_Constants SDMMC_LL Exported Constants
+  * @{
+  */
+#define SDMMC_ERROR_NONE                                0x00000000U    /*!< No error                                                      */
+#define SDMMC_ERROR_CMD_CRC_FAIL                        0x00000001U    /*!< Command response received (but CRC check failed)              */
+#define SDMMC_ERROR_DATA_CRC_FAIL                       0x00000002U    /*!< Data block sent/received (CRC check failed)                   */
+#define SDMMC_ERROR_CMD_RSP_TIMEOUT                     0x00000004U    /*!< Command response timeout                                      */
+#define SDMMC_ERROR_DATA_TIMEOUT                        0x00000008U    /*!< Data timeout                                                  */
+#define SDMMC_ERROR_TX_UNDERRUN                         0x00000010U    /*!< Transmit FIFO underrun                                        */
+#define SDMMC_ERROR_RX_OVERRUN                          0x00000020U    /*!< Receive FIFO overrun                                          */
+#define SDMMC_ERROR_ADDR_MISALIGNED                     0x00000040U    /*!< Misaligned address                                            */
+#define SDMMC_ERROR_BLOCK_LEN_ERR                       0x00000080U    /*!< Transferred block length is not allowed for the card or the
+                                                                            number of transferred bytes does not match the block length   */
+#define SDMMC_ERROR_ERASE_SEQ_ERR                       0x00000100U    /*!< An error in the sequence of erase command occurs              */
+#define SDMMC_ERROR_BAD_ERASE_PARAM                     0x00000200U    /*!< An invalid selection for erase groups                         */
+#define SDMMC_ERROR_WRITE_PROT_VIOLATION                0x00000400U    /*!< Attempt to program a write protect block                      */
+#define SDMMC_ERROR_LOCK_UNLOCK_FAILED                  0x00000800U    /*!< Sequence or password error has been detected in unlock
+                                                                            command or if there was an attempt to access a locked card    */
+#define SDMMC_ERROR_COM_CRC_FAILED                      0x00001000U    /*!< CRC check of the previous command failed                      */
+#define SDMMC_ERROR_ILLEGAL_CMD                         0x00002000U    /*!< Command is not legal for the card state                       */
+#define SDMMC_ERROR_CARD_ECC_FAILED                     0x00004000U    /*!< Card internal ECC was applied but failed to correct the data  */
+#define SDMMC_ERROR_CC_ERR                              0x00008000U    /*!< Internal card controller error                                */
+#define SDMMC_ERROR_GENERAL_UNKNOWN_ERR                 0x00010000U    /*!< General or unknown error                                      */
+#define SDMMC_ERROR_STREAM_READ_UNDERRUN                0x00020000U    /*!< The card could not sustain data reading in stream rmode       */
+#define SDMMC_ERROR_STREAM_WRITE_OVERRUN                0x00040000U    /*!< The card could not sustain data programming in stream mode    */
+#define SDMMC_ERROR_CID_CSD_OVERWRITE                   0x00080000U    /*!< CID/CSD overwrite error                                       */
+#define SDMMC_ERROR_WP_ERASE_SKIP                       0x00100000U    /*!< Only partial address space was erased                         */
+#define SDMMC_ERROR_CARD_ECC_DISABLED                   0x00200000U    /*!< Command has been executed without using internal ECC          */
+#define SDMMC_ERROR_ERASE_RESET                         0x00400000U    /*!< Erase sequence was cleared before executing because an out
+                                                                            of erase sequence command was received                        */
+#define SDMMC_ERROR_AKE_SEQ_ERR                         0x00800000U    /*!< Error in sequence of authentication                           */
+#define SDMMC_ERROR_INVALID_VOLTRANGE                   0x01000000U    /*!< Error in case of invalid voltage range                        */
+#define SDMMC_ERROR_ADDR_OUT_OF_RANGE                   0x02000000U    /*!< Error when addressed block is out of range                    */
+#define SDMMC_ERROR_REQUEST_NOT_APPLICABLE              0x04000000U    /*!< Error when command request is not applicable                  */
+#define SDMMC_ERROR_INVALID_PARAMETER                   0x08000000U    /*!< the used parameter is not valid                               */
+#define SDMMC_ERROR_UNSUPPORTED_FEATURE                 0x10000000U    /*!< Error when feature is not insupported                         */
+#define SDMMC_ERROR_BUSY                                0x20000000U    /*!< Error when transfer process is busy                           */
+#define SDMMC_ERROR_DMA                                 0x40000000U    /*!< Error while DMA transfer                                      */
+#define SDMMC_ERROR_TIMEOUT                             0x80000000U    /*!< Timeout error                                                 */
+
+/** 
+  * @brief SDMMC Commands Index 
+  */
+#define SDMMC_CMD_GO_IDLE_STATE                                 0U    /*!< Resets the SD memory card.                                                               */
+#define SDMMC_CMD_SEND_OP_COND                                  1U    /*!< Sends host capacity support information and activates the card's initialization process. */
+#define SDMMC_CMD_ALL_SEND_CID                                  2U    /*!< Asks any card connected to the host to send the CID numbers on the CMD line.             */
+#define SDMMC_CMD_SET_REL_ADDR                                  3U    /*!< Asks the card to publish a new relative address (RCA).                                   */
+#define SDMMC_CMD_SET_DSR                                       4U    /*!< Programs the DSR of all cards.                                                           */
+#define SDMMC_CMD_SDMMC_SEN_OP_COND                             5U    /*!< Sends host capacity support information (HCS) and asks the accessed card to send its
+                                                                           operating condition register (OCR) content in the response on the CMD line.              */
+#define SDMMC_CMD_HS_SWITCH                                     6U    /*!< Checks switchable function (mode 0) and switch card function (mode 1).                   */
+#define SDMMC_CMD_SEL_DESEL_CARD                                7U    /*!< Selects the card by its own relative address and gets deselected by any other address    */
+#define SDMMC_CMD_HS_SEND_EXT_CSD                               8U    /*!< Sends SD Memory Card interface condition, which includes host supply voltage information
+                                                                           and asks the card whether card supports voltage.                                         */
+#define SDMMC_CMD_SEND_CSD                                      9U    /*!< Addressed card sends its card specific data (CSD) on the CMD line.                       */
+#define SDMMC_CMD_SEND_CID                                      10U   /*!< Addressed card sends its card identification (CID) on the CMD line.                      */
+#define SDMMC_CMD_READ_DAT_UNTIL_STOP                           11U   /*!< SD card doesn't support it.                                                              */
+#define SDMMC_CMD_STOP_TRANSMISSION                             12U   /*!< Forces the card to stop transmission.                                                    */
+#define SDMMC_CMD_SEND_STATUS                                   13U   /*!< Addressed card sends its status register.                                                */
+#define SDMMC_CMD_HS_BUSTEST_READ                               14U   /*!< Reserved                                                                                 */
+#define SDMMC_CMD_GO_INACTIVE_STATE                             15U   /*!< Sends an addressed card into the inactive state.                                         */
+#define SDMMC_CMD_SET_BLOCKLEN                                  16U   /*!< Sets the block length (in bytes for SDSC) for all following block commands
+                                                                           (read, write, lock). Default block length is fixed to 512 Bytes. Not effective 
+                                                                           for SDHS and SDXC.                                                                       */
+#define SDMMC_CMD_READ_SINGLE_BLOCK                             17U   /*!< Reads single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of
+                                                                           fixed 512 bytes in case of SDHC and SDXC.                                                */
+#define SDMMC_CMD_READ_MULT_BLOCK                               18U   /*!< Continuously transfers data blocks from card to host until interrupted by
+                                                                           STOP_TRANSMISSION command.                                                               */
+#define SDMMC_CMD_HS_BUSTEST_WRITE                              19U   /*!< 64 bytes tuning pattern is sent for SDR50 and SDR104.                                    */
+#define SDMMC_CMD_WRITE_DAT_UNTIL_STOP                          20U   /*!< Speed class control command.                                                             */
+#define SDMMC_CMD_SET_BLOCK_COUNT                               23U   /*!< Specify block count for CMD18 and CMD25.                                                 */
+#define SDMMC_CMD_WRITE_SINGLE_BLOCK                            24U   /*!< Writes single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of
+                                                                           fixed 512 bytes in case of SDHC and SDXC.                                                */
+#define SDMMC_CMD_WRITE_MULT_BLOCK                              25U   /*!< Continuously writes blocks of data until a STOP_TRANSMISSION follows.                    */
+#define SDMMC_CMD_PROG_CID                                      26U   /*!< Reserved for manufacturers.                                                              */
+#define SDMMC_CMD_PROG_CSD                                      27U   /*!< Programming of the programmable bits of the CSD.                                         */
+#define SDMMC_CMD_SET_WRITE_PROT                                28U   /*!< Sets the write protection bit of the addressed group.                                    */
+#define SDMMC_CMD_CLR_WRITE_PROT                                29U   /*!< Clears the write protection bit of the addressed group.                                  */
+#define SDMMC_CMD_SEND_WRITE_PROT                               30U   /*!< Asks the card to send the status of the write protection bits.                           */
+#define SDMMC_CMD_SD_ERASE_GRP_START                            32U   /*!< Sets the address of the first write block to be erased. (For SD card only).              */
+#define SDMMC_CMD_SD_ERASE_GRP_END                              33U   /*!< Sets the address of the last write block of the continuous range to be erased.           */
+#define SDMMC_CMD_ERASE_GRP_START                               35U   /*!< Sets the address of the first write block to be erased. Reserved for each command
+                                                                           system set by switch function command (CMD6).                                            */
+#define SDMMC_CMD_ERASE_GRP_END                                 36U   /*!< Sets the address of the last write block of the continuous range to be erased.
+                                                                           Reserved for each command system set by switch function command (CMD6).                  */
+#define SDMMC_CMD_ERASE                                         38U   /*!< Reserved for SD security applications.                                                   */
+#define SDMMC_CMD_FAST_IO                                       39U   /*!< SD card doesn't support it (Reserved).                                                   */
+#define SDMMC_CMD_GO_IRQ_STATE                                  40U   /*!< SD card doesn't support it (Reserved).                                                   */
+#define SDMMC_CMD_LOCK_UNLOCK                                   42U   /*!< Sets/resets the password or lock/unlock the card. The size of the data block is set by
+                                                                           the SET_BLOCK_LEN command.                                                               */
+#define SDMMC_CMD_APP_CMD                                       55U   /*!< Indicates to the card that the next command is an application specific command rather
+                                                                           than a standard command.                                                                 */
+#define SDMMC_CMD_GEN_CMD                                       56U   /*!< Used either to transfer a data block to the card or to get a data block from the card
+                                                                           for general purpose/application specific commands.                                       */
+#define SDMMC_CMD_NO_CMD                                        64U   /*!< No command                                                                               */
+
+/** 
+  * @brief Following commands are SD Card Specific commands.
+  *        SDMMC_APP_CMD should be sent before sending these commands. 
+  */
+#define SDMMC_CMD_APP_SD_SET_BUSWIDTH                           6U    /*!< (ACMD6) Defines the data bus width to be used for data transfer. The allowed data bus
+                                                                            widths are given in SCR register.                                                       */
+#define SDMMC_CMD_SD_APP_STATUS                                 13U   /*!< (ACMD13) Sends the SD status.                                                            */
+#define SDMMC_CMD_SD_APP_SEND_NUM_WRITE_BLOCKS                  22U   /*!< (ACMD22) Sends the number of the written (without errors) write blocks. Responds with
+                                                                           32bit+CRC data block.                                                                    */
+#define SDMMC_CMD_SD_APP_OP_COND                                41U   /*!< (ACMD41) Sends host capacity support information (HCS) and asks the accessed card to
+                                                                           send its operating condition register (OCR) content in the response on the CMD line.     */
+#define SDMMC_CMD_SD_APP_SET_CLR_CARD_DETECT                    42U   /*!< (ACMD42) Connect/Disconnect the 50 KOhm pull-up resistor on CD/DAT3 (pin 1) of the card  */
+#define SDMMC_CMD_SD_APP_SEND_SCR                               51U   /*!< Reads the SD Configuration Register (SCR).                                               */
+#define SDMMC_CMD_SDMMC_RW_DIRECT                               52U   /*!< For SD I/O card only, reserved for security specification.                               */
+#define SDMMC_CMD_SDMMC_RW_EXTENDED                             53U   /*!< For SD I/O card only, reserved for security specification.                               */
+
+/** 
+  * @brief Following commands are SD Card Specific security commands.
+  *        SDMMC_CMD_APP_CMD should be sent before sending these commands. 
+  */
+#define SDMMC_CMD_SD_APP_GET_MKB                                43U
+#define SDMMC_CMD_SD_APP_GET_MID                                44U
+#define SDMMC_CMD_SD_APP_SET_CER_RN1                            45U
+#define SDMMC_CMD_SD_APP_GET_CER_RN2                            46U
+#define SDMMC_CMD_SD_APP_SET_CER_RES2                           47U
+#define SDMMC_CMD_SD_APP_GET_CER_RES1                           48U
+#define SDMMC_CMD_SD_APP_SECURE_READ_MULTIPLE_BLOCK             18U
+#define SDMMC_CMD_SD_APP_SECURE_WRITE_MULTIPLE_BLOCK            25U
+#define SDMMC_CMD_SD_APP_SECURE_ERASE                           38U
+#define SDMMC_CMD_SD_APP_CHANGE_SECURE_AREA                     49U
+#define SDMMC_CMD_SD_APP_SECURE_WRITE_MKB                       48U
+
+/** 
+  * @brief  Masks for errors Card Status R1 (OCR Register) 
+  */
+#define SDMMC_OCR_ADDR_OUT_OF_RANGE                   0x80000000U
+#define SDMMC_OCR_ADDR_MISALIGNED                     0x40000000U
+#define SDMMC_OCR_BLOCK_LEN_ERR                       0x20000000U
+#define SDMMC_OCR_ERASE_SEQ_ERR                       0x10000000U
+#define SDMMC_OCR_BAD_ERASE_PARAM                     0x08000000U
+#define SDMMC_OCR_WRITE_PROT_VIOLATION                0x04000000U
+#define SDMMC_OCR_LOCK_UNLOCK_FAILED                  0x01000000U
+#define SDMMC_OCR_COM_CRC_FAILED                      0x00800000U
+#define SDMMC_OCR_ILLEGAL_CMD                         0x00400000U
+#define SDMMC_OCR_CARD_ECC_FAILED                     0x00200000U
+#define SDMMC_OCR_CC_ERROR                            0x00100000U
+#define SDMMC_OCR_GENERAL_UNKNOWN_ERROR               0x00080000U
+#define SDMMC_OCR_STREAM_READ_UNDERRUN                0x00040000U
+#define SDMMC_OCR_STREAM_WRITE_OVERRUN                0x00020000U
+#define SDMMC_OCR_CID_CSD_OVERWRITE                   0x00010000U
+#define SDMMC_OCR_WP_ERASE_SKIP                       0x00008000U
+#define SDMMC_OCR_CARD_ECC_DISABLED                   0x00004000U
+#define SDMMC_OCR_ERASE_RESET                         0x00002000U
+#define SDMMC_OCR_AKE_SEQ_ERROR                       0x00000008U
+#define SDMMC_OCR_ERRORBITS                           0xFDFFE008U
+
+/** 
+  * @brief  Masks for R6 Response 
+  */
+#define SDMMC_R6_GENERAL_UNKNOWN_ERROR                0x00002000U
+#define SDMMC_R6_ILLEGAL_CMD                          0x00004000U
+#define SDMMC_R6_COM_CRC_FAILED                       0x00008000U
+
+#define SDMMC_VOLTAGE_WINDOW_SD                       0x80100000U
+#define SDMMC_HIGH_CAPACITY                           0x40000000U
+#define SDMMC_STD_CAPACITY                            0x00000000U
+#define SDMMC_CHECK_PATTERN                           0x000001AAU
+#define SD_SWITCH_1_8V_CAPACITY                       0x01000000U
+
+#define SDMMC_MAX_VOLT_TRIAL                          0x0000FFFFU
+
+#define SDMMC_MAX_TRIAL                               0x0000FFFFU
+
+#define SDMMC_ALLZERO                                 0x00000000U
+
+#define SDMMC_WIDE_BUS_SUPPORT                        0x00040000U
+#define SDMMC_SINGLE_BUS_SUPPORT                      0x00010000U
+#define SDMMC_CARD_LOCKED                             0x02000000U
+
+#ifndef SDMMC_DATATIMEOUT
+#define SDMMC_DATATIMEOUT                             0xFFFFFFFFU
+#endif /* SDMMC_DATATIMEOUT */
+
+#define SDMMC_0TO7BITS                                0x000000FFU
+#define SDMMC_8TO15BITS                               0x0000FF00U
+#define SDMMC_16TO23BITS                              0x00FF0000U
+#define SDMMC_24TO31BITS                              0xFF000000U
+#define SDMMC_MAX_DATA_LENGTH                         0x01FFFFFFU
+
+#define SDMMC_HALFFIFO                                0x00000008U
+#define SDMMC_HALFFIFOBYTES                           0x00000020U
+
+/** 
+  * @brief  Command Class supported
+  */
+#define SDIO_CCCC_ERASE                       0x00000020U
+
+#define SDIO_CMDTIMEOUT                       5000U         /* Command send and response timeout */
+#define SDIO_MAXERASETIMEOUT                  63000U        /* Max erase Timeout 63 s            */
+#define SDIO_STOPTRANSFERTIMEOUT              100000000U    /* Timeout for STOP TRANSMISSION command */
+
+/** @defgroup SDIO_LL_Clock_Edge Clock Edge
+  * @{
+  */
+#define SDIO_CLOCK_EDGE_RISING               0x00000000U
+#define SDIO_CLOCK_EDGE_FALLING              SDIO_CLKCR_NEGEDGE
+
+#define IS_SDIO_CLOCK_EDGE(EDGE) (((EDGE) == SDIO_CLOCK_EDGE_RISING) || \
+                                          ((EDGE) == SDIO_CLOCK_EDGE_FALLING))
+/**
+  * @}
+  */
+
+/** @defgroup SDIO_LL_Clock_Bypass Clock Bypass
+  * @{
+  */
+#define SDIO_CLOCK_BYPASS_DISABLE             0x00000000U
+#define SDIO_CLOCK_BYPASS_ENABLE              SDIO_CLKCR_BYPASS   
+
+#define IS_SDIO_CLOCK_BYPASS(BYPASS) (((BYPASS) == SDIO_CLOCK_BYPASS_DISABLE) || \
+                                              ((BYPASS) == SDIO_CLOCK_BYPASS_ENABLE))
+/**
+  * @}
+  */ 
+
+/** @defgroup SDIO_LL_Clock_Power_Save Clock Power Saving
+  * @{
+  */
+#define SDIO_CLOCK_POWER_SAVE_DISABLE         0x00000000U
+#define SDIO_CLOCK_POWER_SAVE_ENABLE          SDIO_CLKCR_PWRSAV
+
+#define IS_SDIO_CLOCK_POWER_SAVE(SAVE) (((SAVE) == SDIO_CLOCK_POWER_SAVE_DISABLE) || \
+                                                ((SAVE) == SDIO_CLOCK_POWER_SAVE_ENABLE))
+/**
+  * @}
+  */
+
+/** @defgroup SDIO_LL_Bus_Wide Bus Width
+  * @{
+  */
+#define SDIO_BUS_WIDE_1B                      0x00000000U
+#define SDIO_BUS_WIDE_4B                      SDIO_CLKCR_WIDBUS_0
+#define SDIO_BUS_WIDE_8B                      SDIO_CLKCR_WIDBUS_1
+
+#define IS_SDIO_BUS_WIDE(WIDE) (((WIDE) == SDIO_BUS_WIDE_1B) || \
+                                        ((WIDE) == SDIO_BUS_WIDE_4B) || \
+                                        ((WIDE) == SDIO_BUS_WIDE_8B))
+/**
+  * @}
+  */
+
+/** @defgroup SDIO_LL_Hardware_Flow_Control Hardware Flow Control
+  * @{
+  */
+#define SDIO_HARDWARE_FLOW_CONTROL_DISABLE    0x00000000U
+#define SDIO_HARDWARE_FLOW_CONTROL_ENABLE     SDIO_CLKCR_HWFC_EN
+
+#define IS_SDIO_HARDWARE_FLOW_CONTROL(CONTROL) (((CONTROL) == SDIO_HARDWARE_FLOW_CONTROL_DISABLE) || \
+                                                        ((CONTROL) == SDIO_HARDWARE_FLOW_CONTROL_ENABLE))
+/**
+  * @}
+  */
+  
+/** @defgroup SDIO_LL_Clock_Division Clock Division
+  * @{
+  */
+#define IS_SDIO_CLKDIV(DIV)   ((DIV) <= 0xFFU)
+/**
+  * @}
+  */  
+    
+/** @defgroup SDIO_LL_Command_Index Command Index
+  * @{
+  */
+#define IS_SDIO_CMD_INDEX(INDEX)            ((INDEX) < 0x40U)
+/**
+  * @}
+  */
+
+/** @defgroup SDIO_LL_Response_Type Response Type
+  * @{
+  */
+#define SDIO_RESPONSE_NO                    0x00000000U
+#define SDIO_RESPONSE_SHORT                 SDIO_CMD_WAITRESP_0
+#define SDIO_RESPONSE_LONG                  SDIO_CMD_WAITRESP
+
+#define IS_SDIO_RESPONSE(RESPONSE) (((RESPONSE) == SDIO_RESPONSE_NO)    || \
+                                            ((RESPONSE) == SDIO_RESPONSE_SHORT) || \
+                                            ((RESPONSE) == SDIO_RESPONSE_LONG))
+/**
+  * @}
+  */
+
+/** @defgroup SDIO_LL_Wait_Interrupt_State Wait Interrupt
+  * @{
+  */
+#define SDIO_WAIT_NO                        0x00000000U
+#define SDIO_WAIT_IT                        SDIO_CMD_WAITINT 
+#define SDIO_WAIT_PEND                      SDIO_CMD_WAITPEND
+
+#define IS_SDIO_WAIT(WAIT) (((WAIT) == SDIO_WAIT_NO) || \
+                                    ((WAIT) == SDIO_WAIT_IT) || \
+                                    ((WAIT) == SDIO_WAIT_PEND))
+/**
+  * @}
+  */
+
+/** @defgroup SDIO_LL_CPSM_State CPSM State
+  * @{
+  */
+#define SDIO_CPSM_DISABLE                   0x00000000U
+#define SDIO_CPSM_ENABLE                    SDIO_CMD_CPSMEN
+
+#define IS_SDIO_CPSM(CPSM) (((CPSM) == SDIO_CPSM_DISABLE) || \
+                                    ((CPSM) == SDIO_CPSM_ENABLE))
+/**
+  * @}
+  */  
+
+/** @defgroup SDIO_LL_Response_Registers Response Register
+  * @{
+  */
+#define SDIO_RESP1                          0x00000000U
+#define SDIO_RESP2                          0x00000004U
+#define SDIO_RESP3                          0x00000008U
+#define SDIO_RESP4                          0x0000000CU
+
+#define IS_SDIO_RESP(RESP) (((RESP) == SDIO_RESP1) || \
+                                    ((RESP) == SDIO_RESP2) || \
+                                    ((RESP) == SDIO_RESP3) || \
+                                    ((RESP) == SDIO_RESP4))
+/**
+  * @}
+  */
+
+/** @defgroup SDIO_LL_Data_Length Data Length
+  * @{
+  */
+#define IS_SDIO_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFFU)
+/**
+  * @}
+  */
+
+/** @defgroup SDIO_LL_Data_Block_Size  Data Block Size
+  * @{
+  */
+#define SDIO_DATABLOCK_SIZE_1B               0x00000000U
+#define SDIO_DATABLOCK_SIZE_2B               SDIO_DCTRL_DBLOCKSIZE_0
+#define SDIO_DATABLOCK_SIZE_4B               SDIO_DCTRL_DBLOCKSIZE_1
+#define SDIO_DATABLOCK_SIZE_8B               (SDIO_DCTRL_DBLOCKSIZE_0|SDIO_DCTRL_DBLOCKSIZE_1)
+#define SDIO_DATABLOCK_SIZE_16B              SDIO_DCTRL_DBLOCKSIZE_2
+#define SDIO_DATABLOCK_SIZE_32B              (SDIO_DCTRL_DBLOCKSIZE_0|SDIO_DCTRL_DBLOCKSIZE_2)
+#define SDIO_DATABLOCK_SIZE_64B              (SDIO_DCTRL_DBLOCKSIZE_1|SDIO_DCTRL_DBLOCKSIZE_2)
+#define SDIO_DATABLOCK_SIZE_128B             (SDIO_DCTRL_DBLOCKSIZE_0|SDIO_DCTRL_DBLOCKSIZE_1|SDIO_DCTRL_DBLOCKSIZE_2)
+#define SDIO_DATABLOCK_SIZE_256B             SDIO_DCTRL_DBLOCKSIZE_3
+#define SDIO_DATABLOCK_SIZE_512B             (SDIO_DCTRL_DBLOCKSIZE_0|SDIO_DCTRL_DBLOCKSIZE_3)
+#define SDIO_DATABLOCK_SIZE_1024B            (SDIO_DCTRL_DBLOCKSIZE_1|SDIO_DCTRL_DBLOCKSIZE_3)
+#define SDIO_DATABLOCK_SIZE_2048B            (SDIO_DCTRL_DBLOCKSIZE_0|SDIO_DCTRL_DBLOCKSIZE_1|SDIO_DCTRL_DBLOCKSIZE_3) 
+#define SDIO_DATABLOCK_SIZE_4096B            (SDIO_DCTRL_DBLOCKSIZE_2|SDIO_DCTRL_DBLOCKSIZE_3)
+#define SDIO_DATABLOCK_SIZE_8192B            (SDIO_DCTRL_DBLOCKSIZE_0|SDIO_DCTRL_DBLOCKSIZE_2|SDIO_DCTRL_DBLOCKSIZE_3)
+#define SDIO_DATABLOCK_SIZE_16384B           (SDIO_DCTRL_DBLOCKSIZE_1|SDIO_DCTRL_DBLOCKSIZE_2|SDIO_DCTRL_DBLOCKSIZE_3)
+
+#define IS_SDIO_BLOCK_SIZE(SIZE) (((SIZE) == SDIO_DATABLOCK_SIZE_1B)    || \
+                                          ((SIZE) == SDIO_DATABLOCK_SIZE_2B)    || \
+                                          ((SIZE) == SDIO_DATABLOCK_SIZE_4B)    || \
+                                          ((SIZE) == SDIO_DATABLOCK_SIZE_8B)    || \
+                                          ((SIZE) == SDIO_DATABLOCK_SIZE_16B)   || \
+                                          ((SIZE) == SDIO_DATABLOCK_SIZE_32B)   || \
+                                          ((SIZE) == SDIO_DATABLOCK_SIZE_64B)   || \
+                                          ((SIZE) == SDIO_DATABLOCK_SIZE_128B)  || \
+                                          ((SIZE) == SDIO_DATABLOCK_SIZE_256B)  || \
+                                          ((SIZE) == SDIO_DATABLOCK_SIZE_512B)  || \
+                                          ((SIZE) == SDIO_DATABLOCK_SIZE_1024B) || \
+                                          ((SIZE) == SDIO_DATABLOCK_SIZE_2048B) || \
+                                          ((SIZE) == SDIO_DATABLOCK_SIZE_4096B) || \
+                                          ((SIZE) == SDIO_DATABLOCK_SIZE_8192B) || \
+                                          ((SIZE) == SDIO_DATABLOCK_SIZE_16384B)) 
+/**
+  * @}
+  */
+
+/** @defgroup SDIO_LL_Transfer_Direction Transfer Direction
+  * @{
+  */
+#define SDIO_TRANSFER_DIR_TO_CARD            0x00000000U
+#define SDIO_TRANSFER_DIR_TO_SDIO    SDIO_DCTRL_DTDIR
+
+#define IS_SDIO_TRANSFER_DIR(DIR) (((DIR) == SDIO_TRANSFER_DIR_TO_CARD) || \
+                                           ((DIR) == SDIO_TRANSFER_DIR_TO_SDIO))
+/**
+  * @}
+  */
+
+/** @defgroup SDIO_LL_Transfer_Type Transfer Type
+  * @{
+  */
+#define SDIO_TRANSFER_MODE_BLOCK             0x00000000U
+#define SDIO_TRANSFER_MODE_STREAM            SDIO_DCTRL_DTMODE
+
+#define IS_SDIO_TRANSFER_MODE(MODE) (((MODE) == SDIO_TRANSFER_MODE_BLOCK) || \
+                                             ((MODE) == SDIO_TRANSFER_MODE_STREAM))
+/**
+  * @}
+  */
+
+/** @defgroup SDIO_LL_DPSM_State DPSM State
+  * @{
+  */
+#define SDIO_DPSM_DISABLE                    0x00000000U
+#define SDIO_DPSM_ENABLE                     SDIO_DCTRL_DTEN
+
+#define IS_SDIO_DPSM(DPSM) (((DPSM) == SDIO_DPSM_DISABLE) ||\
+                                    ((DPSM) == SDIO_DPSM_ENABLE))
+/**
+  * @}
+  */
+  
+/** @defgroup SDIO_LL_Read_Wait_Mode Read Wait Mode
+  * @{
+  */
+#define SDIO_READ_WAIT_MODE_DATA2                0x00000000U
+#define SDIO_READ_WAIT_MODE_CLK                  (SDIO_DCTRL_RWMOD)
+
+#define IS_SDIO_READWAIT_MODE(MODE) (((MODE) == SDIO_READ_WAIT_MODE_CLK) || \
+                                             ((MODE) == SDIO_READ_WAIT_MODE_DATA2))
+/**
+  * @}
+  */  
+
+/** @defgroup SDIO_LL_Interrupt_sources Interrupt Sources
+  * @{
+  */
+#define SDIO_IT_CCRCFAIL                    SDIO_MASK_CCRCFAILIE
+#define SDIO_IT_DCRCFAIL                    SDIO_MASK_DCRCFAILIE
+#define SDIO_IT_CTIMEOUT                    SDIO_MASK_CTIMEOUTIE
+#define SDIO_IT_DTIMEOUT                    SDIO_MASK_DTIMEOUTIE
+#define SDIO_IT_TXUNDERR                    SDIO_MASK_TXUNDERRIE
+#define SDIO_IT_RXOVERR                     SDIO_MASK_RXOVERRIE
+#define SDIO_IT_CMDREND                     SDIO_MASK_CMDRENDIE
+#define SDIO_IT_CMDSENT                     SDIO_MASK_CMDSENTIE
+#define SDIO_IT_DATAEND                     SDIO_MASK_DATAENDIE
+#if defined(SDIO_STA_STBITERR)
+#define SDIO_IT_STBITERR                    SDIO_MASK_STBITERRIE
+#endif
+#define SDIO_IT_DBCKEND                     SDIO_MASK_DBCKENDIE
+#define SDIO_IT_CMDACT                      SDIO_MASK_CMDACTIE
+#define SDIO_IT_TXACT                       SDIO_MASK_TXACTIE
+#define SDIO_IT_RXACT                       SDIO_MASK_RXACTIE
+#define SDIO_IT_TXFIFOHE                    SDIO_MASK_TXFIFOHEIE
+#define SDIO_IT_RXFIFOHF                    SDIO_MASK_RXFIFOHFIE
+#define SDIO_IT_TXFIFOF                     SDIO_MASK_TXFIFOFIE
+#define SDIO_IT_RXFIFOF                     SDIO_MASK_RXFIFOFIE
+#define SDIO_IT_TXFIFOE                     SDIO_MASK_TXFIFOEIE
+#define SDIO_IT_RXFIFOE                     SDIO_MASK_RXFIFOEIE
+#define SDIO_IT_TXDAVL                      SDIO_MASK_TXDAVLIE
+#define SDIO_IT_RXDAVL                      SDIO_MASK_RXDAVLIE
+#define SDIO_IT_SDIOIT                      SDIO_MASK_SDIOITIE
+#if defined(SDIO_CMD_CEATACMD)
+#define SDIO_IT_CEATAEND                    SDIO_MASK_CEATAENDIE
+#endif
+/**
+  * @}
+  */ 
+
+/** @defgroup SDIO_LL_Flags Flags
+  * @{
+  */
+#define SDIO_FLAG_CCRCFAIL                  SDIO_STA_CCRCFAIL
+#define SDIO_FLAG_DCRCFAIL                  SDIO_STA_DCRCFAIL
+#define SDIO_FLAG_CTIMEOUT                  SDIO_STA_CTIMEOUT
+#define SDIO_FLAG_DTIMEOUT                  SDIO_STA_DTIMEOUT
+#define SDIO_FLAG_TXUNDERR                  SDIO_STA_TXUNDERR
+#define SDIO_FLAG_RXOVERR                   SDIO_STA_RXOVERR
+#define SDIO_FLAG_CMDREND                   SDIO_STA_CMDREND
+#define SDIO_FLAG_CMDSENT                   SDIO_STA_CMDSENT
+#define SDIO_FLAG_DATAEND                   SDIO_STA_DATAEND
+#if defined(SDIO_STA_STBITERR)
+#define SDIO_FLAG_STBITERR                  SDIO_STA_STBITERR
+#endif
+#define SDIO_FLAG_DBCKEND                   SDIO_STA_DBCKEND
+#define SDIO_FLAG_CMDACT                    SDIO_STA_CMDACT
+#define SDIO_FLAG_TXACT                     SDIO_STA_TXACT
+#define SDIO_FLAG_RXACT                     SDIO_STA_RXACT
+#define SDIO_FLAG_TXFIFOHE                  SDIO_STA_TXFIFOHE
+#define SDIO_FLAG_RXFIFOHF                  SDIO_STA_RXFIFOHF
+#define SDIO_FLAG_TXFIFOF                   SDIO_STA_TXFIFOF
+#define SDIO_FLAG_RXFIFOF                   SDIO_STA_RXFIFOF
+#define SDIO_FLAG_TXFIFOE                   SDIO_STA_TXFIFOE
+#define SDIO_FLAG_RXFIFOE                   SDIO_STA_RXFIFOE
+#define SDIO_FLAG_TXDAVL                    SDIO_STA_TXDAVL
+#define SDIO_FLAG_RXDAVL                    SDIO_STA_RXDAVL
+#define SDIO_FLAG_SDIOIT                    SDIO_STA_SDIOIT
+#if defined(SDIO_CMD_CEATACMD)
+#define SDIO_FLAG_CEATAEND                  SDIO_STA_CEATAEND
+#endif
+#define SDIO_STATIC_FLAGS                   ((uint32_t)(SDIO_FLAG_CCRCFAIL | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_CTIMEOUT |\
+                                                         SDIO_FLAG_DTIMEOUT | SDIO_FLAG_TXUNDERR | SDIO_FLAG_RXOVERR  |\
+                                                         SDIO_FLAG_CMDREND  | SDIO_FLAG_CMDSENT  | SDIO_FLAG_DATAEND  |\
+                                                         SDIO_FLAG_DBCKEND | SDIO_FLAG_SDIOIT))  
+
+#define SDIO_STATIC_CMD_FLAGS               ((uint32_t)(SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CTIMEOUT | SDIO_FLAG_CMDREND |\
+                                                         SDIO_FLAG_CMDSENT))
+
+#define SDIO_STATIC_DATA_FLAGS              ((uint32_t)(SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_TXUNDERR |\
+                                                         SDIO_FLAG_RXOVERR  | SDIO_FLAG_DATAEND  | SDIO_FLAG_DBCKEND))
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+  
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup SDIO_LL_Exported_macros SDIO_LL Exported Macros
+  * @{
+  */
+
+/** @defgroup SDMMC_LL_Alias_Region Bit Address in the alias region
+  * @{
+  */
+/* ------------ SDIO registers bit address in the alias region -------------- */
+#define SDIO_OFFSET               (SDIO_BASE - PERIPH_BASE)
+
+/* --- CLKCR Register ---*/
+/* Alias word address of CLKEN bit */
+#define CLKCR_OFFSET              (SDIO_OFFSET + 0x04U)
+#define CLKEN_BITNUMBER           0x08U
+#define CLKCR_CLKEN_BB            (PERIPH_BB_BASE + (CLKCR_OFFSET * 32U) + (CLKEN_BITNUMBER * 4U))
+
+/* --- CMD Register ---*/
+/* Alias word address of SDIOSUSPEND bit */
+#define CMD_OFFSET                (SDIO_OFFSET + 0x0CU)
+#define SDIOSUSPEND_BITNUMBER     0x0BU
+#define CMD_SDIOSUSPEND_BB        (PERIPH_BB_BASE + (CMD_OFFSET * 32U) + (SDIOSUSPEND_BITNUMBER * 4U))
+
+/* Alias word address of ENCMDCOMPL bit */
+#define ENCMDCOMPL_BITNUMBER      0x0CU
+#define CMD_ENCMDCOMPL_BB         (PERIPH_BB_BASE + (CMD_OFFSET * 32U) + (ENCMDCOMPL_BITNUMBER * 4U))
+
+/* Alias word address of NIEN bit */
+#define NIEN_BITNUMBER            0x0DU
+#define CMD_NIEN_BB               (PERIPH_BB_BASE + (CMD_OFFSET * 32U) + (NIEN_BITNUMBER * 4U))
+
+/* Alias word address of ATACMD bit */
+#define ATACMD_BITNUMBER          0x0EU
+#define CMD_ATACMD_BB             (PERIPH_BB_BASE + (CMD_OFFSET * 32U) + (ATACMD_BITNUMBER * 4U))
+
+/* --- DCTRL Register ---*/
+/* Alias word address of DMAEN bit */
+#define DCTRL_OFFSET              (SDIO_OFFSET + 0x2CU)
+#define DMAEN_BITNUMBER           0x03U
+#define DCTRL_DMAEN_BB            (PERIPH_BB_BASE + (DCTRL_OFFSET * 32U) + (DMAEN_BITNUMBER * 4U))
+
+/* Alias word address of RWSTART bit */
+#define RWSTART_BITNUMBER         0x08U
+#define DCTRL_RWSTART_BB          (PERIPH_BB_BASE + (DCTRL_OFFSET * 32U) + (RWSTART_BITNUMBER * 4U))
+
+/* Alias word address of RWSTOP bit */
+#define RWSTOP_BITNUMBER          0x09U
+#define DCTRL_RWSTOP_BB           (PERIPH_BB_BASE + (DCTRL_OFFSET * 32U) + (RWSTOP_BITNUMBER * 4U))
+
+/* Alias word address of RWMOD bit */
+#define RWMOD_BITNUMBER           0x0AU
+#define DCTRL_RWMOD_BB            (PERIPH_BB_BASE + (DCTRL_OFFSET * 32U) + (RWMOD_BITNUMBER * 4U))
+
+/* Alias word address of SDIOEN bit */
+#define SDIOEN_BITNUMBER          0x0BU
+#define DCTRL_SDIOEN_BB           (PERIPH_BB_BASE + (DCTRL_OFFSET * 32U) + (SDIOEN_BITNUMBER * 4U))
+/**
+  * @}
+  */
+
+/** @defgroup SDIO_LL_Register Bits And Addresses Definitions
+  * @brief SDIO_LL registers bit address in the alias region
+  * @{
+  */
+/* ---------------------- SDIO registers bit mask --------------------------- */
+/* --- CLKCR Register ---*/
+/* CLKCR register clear mask */ 
+#define CLKCR_CLEAR_MASK         ((uint32_t)(SDIO_CLKCR_CLKDIV  | SDIO_CLKCR_PWRSAV |\
+                                             SDIO_CLKCR_BYPASS  | SDIO_CLKCR_WIDBUS |\
+                                             SDIO_CLKCR_NEGEDGE | SDIO_CLKCR_HWFC_EN))
+
+/* --- DCTRL Register ---*/
+/* SDIO DCTRL Clear Mask */
+#define DCTRL_CLEAR_MASK         ((uint32_t)(SDIO_DCTRL_DTEN    | SDIO_DCTRL_DTDIR |\
+                                             SDIO_DCTRL_DTMODE  | SDIO_DCTRL_DBLOCKSIZE))
+
+/* --- CMD Register ---*/
+/* CMD Register clear mask */
+#define CMD_CLEAR_MASK           ((uint32_t)(SDIO_CMD_CMDINDEX | SDIO_CMD_WAITRESP |\
+                                             SDIO_CMD_WAITINT  | SDIO_CMD_WAITPEND |\
+                                             SDIO_CMD_CPSMEN   | SDIO_CMD_SDIOSUSPEND))
+
+/* SDIO Initialization Frequency (400KHz max) */
+#define SDIO_INIT_CLK_DIV     ((uint8_t)0x76)    /* 48MHz / (SDMMC_INIT_CLK_DIV + 2) < 400KHz */
+
+/* SDIO Data Transfer Frequency (25MHz max) */
+#define SDIO_TRANSFER_CLK_DIV ((uint8_t)0x0)     /* 48MHz / (SDMMC_TRANSFER_CLK_DIV + 2) < 25MHz */
+/**
+  * @}
+  */
+
+/** @defgroup SDIO_LL_Interrupt_Clock Interrupt And Clock Configuration
+ *  @brief macros to handle interrupts and specific clock configurations
+ * @{
+ */
+ 
+/**
+  * @brief  Enable the SDIO device.
+  * @param  __INSTANCE__: SDIO Instance  
+  * @retval None
+  */
+#define __SDIO_ENABLE(__INSTANCE__)  (*(__IO uint32_t *)CLKCR_CLKEN_BB = ENABLE)
+
+/**
+  * @brief  Disable the SDIO device.
+  * @param  __INSTANCE__: SDIO Instance  
+  * @retval None
+  */
+#define __SDIO_DISABLE(__INSTANCE__)  (*(__IO uint32_t *)CLKCR_CLKEN_BB = DISABLE)
+
+/**
+  * @brief  Enable the SDIO DMA transfer.
+  * @param  __INSTANCE__: SDIO Instance  
+  * @retval None
+  */
+#define __SDIO_DMA_ENABLE(__INSTANCE__)  (*(__IO uint32_t *)DCTRL_DMAEN_BB = ENABLE)
+
+/**
+  * @brief  Disable the SDIO DMA transfer.
+  * @param  __INSTANCE__: SDIO Instance   
+  * @retval None
+  */
+#define __SDIO_DMA_DISABLE(__INSTANCE__)  (*(__IO uint32_t *)DCTRL_DMAEN_BB = DISABLE)
+ 
+/**
+  * @brief  Enable the SDIO device interrupt.
+  * @param  __INSTANCE__ : Pointer to SDIO register base  
+  * @param  __INTERRUPT__ : specifies the SDIO interrupt sources to be enabled.
+  *         This parameter can be one or a combination of the following values:
+  *            @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
+  *            @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
+  *            @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
+  *            @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
+  *            @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
+  *            @arg SDIO_IT_RXOVERR:  Received FIFO overrun error interrupt
+  *            @arg SDIO_IT_CMDREND:  Command response received (CRC check passed) interrupt
+  *            @arg SDIO_IT_CMDSENT:  Command sent (no response required) interrupt
+  *            @arg SDIO_IT_DATAEND:  Data end (data counter, DATACOUNT, is zero) interrupt
+  *            @arg SDIO_IT_DBCKEND:  Data block sent/received (CRC check passed) interrupt
+  *            @arg SDIO_IT_CMDACT:   Command transfer in progress interrupt
+  *            @arg SDIO_IT_TXACT:    Data transmit in progress interrupt
+  *            @arg SDIO_IT_RXACT:    Data receive in progress interrupt
+  *            @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
+  *            @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
+  *            @arg SDIO_IT_TXFIFOF:  Transmit FIFO full interrupt
+  *            @arg SDIO_IT_RXFIFOF:  Receive FIFO full interrupt
+  *            @arg SDIO_IT_TXFIFOE:  Transmit FIFO empty interrupt
+  *            @arg SDIO_IT_RXFIFOE:  Receive FIFO empty interrupt
+  *            @arg SDIO_IT_TXDAVL:   Data available in transmit FIFO interrupt
+  *            @arg SDIO_IT_RXDAVL:   Data available in receive FIFO interrupt
+  *            @arg SDIO_IT_SDIOIT:   SDIO interrupt received interrupt 
+  * @retval None
+  */
+#define __SDIO_ENABLE_IT(__INSTANCE__, __INTERRUPT__)  ((__INSTANCE__)->MASK |= (__INTERRUPT__))
+
+/**
+  * @brief  Disable the SDIO device interrupt.
+  * @param  __INSTANCE__ : Pointer to SDIO register base   
+  * @param  __INTERRUPT__ : specifies the SDIO interrupt sources to be disabled.
+  *          This parameter can be one or a combination of the following values:
+  *            @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
+  *            @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
+  *            @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
+  *            @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
+  *            @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
+  *            @arg SDIO_IT_RXOVERR:  Received FIFO overrun error interrupt
+  *            @arg SDIO_IT_CMDREND:  Command response received (CRC check passed) interrupt
+  *            @arg SDIO_IT_CMDSENT:  Command sent (no response required) interrupt
+  *            @arg SDIO_IT_DATAEND:  Data end (data counter, DATACOUNT, is zero) interrupt
+  *            @arg SDIO_IT_DBCKEND:  Data block sent/received (CRC check passed) interrupt
+  *            @arg SDIO_IT_CMDACT:   Command transfer in progress interrupt
+  *            @arg SDIO_IT_TXACT:    Data transmit in progress interrupt
+  *            @arg SDIO_IT_RXACT:    Data receive in progress interrupt
+  *            @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
+  *            @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
+  *            @arg SDIO_IT_TXFIFOF:  Transmit FIFO full interrupt
+  *            @arg SDIO_IT_RXFIFOF:  Receive FIFO full interrupt
+  *            @arg SDIO_IT_TXFIFOE:  Transmit FIFO empty interrupt
+  *            @arg SDIO_IT_RXFIFOE:  Receive FIFO empty interrupt
+  *            @arg SDIO_IT_TXDAVL:   Data available in transmit FIFO interrupt
+  *            @arg SDIO_IT_RXDAVL:   Data available in receive FIFO interrupt
+  *            @arg SDIO_IT_SDIOIT:   SDIO interrupt received interrupt   
+  * @retval None
+  */
+#define __SDIO_DISABLE_IT(__INSTANCE__, __INTERRUPT__)  ((__INSTANCE__)->MASK &= ~(__INTERRUPT__))
+
+/**
+  * @brief  Checks whether the specified SDIO flag is set or not. 
+  * @param  __INSTANCE__ : Pointer to SDIO register base   
+  * @param  __FLAG__: specifies the flag to check. 
+  *          This parameter can be one of the following values:
+  *            @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)
+  *            @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
+  *            @arg SDIO_FLAG_CTIMEOUT: Command response timeout
+  *            @arg SDIO_FLAG_DTIMEOUT: Data timeout
+  *            @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error
+  *            @arg SDIO_FLAG_RXOVERR:  Received FIFO overrun error
+  *            @arg SDIO_FLAG_CMDREND:  Command response received (CRC check passed)
+  *            @arg SDIO_FLAG_CMDSENT:  Command sent (no response required)
+  *            @arg SDIO_FLAG_DATAEND:  Data end (data counter, DATACOUNT, is zero)
+  *            @arg SDIO_FLAG_DBCKEND:  Data block sent/received (CRC check passed)
+  *            @arg SDIO_FLAG_CMDACT:   Command transfer in progress
+  *            @arg SDIO_FLAG_TXACT:    Data transmit in progress
+  *            @arg SDIO_FLAG_RXACT:    Data receive in progress
+  *            @arg SDIO_FLAG_TXFIFOHE: Transmit FIFO Half Empty
+  *            @arg SDIO_FLAG_RXFIFOHF: Receive FIFO Half Full
+  *            @arg SDIO_FLAG_TXFIFOF:  Transmit FIFO full
+  *            @arg SDIO_FLAG_RXFIFOF:  Receive FIFO full
+  *            @arg SDIO_FLAG_TXFIFOE:  Transmit FIFO empty
+  *            @arg SDIO_FLAG_RXFIFOE:  Receive FIFO empty
+  *            @arg SDIO_FLAG_TXDAVL:   Data available in transmit FIFO
+  *            @arg SDIO_FLAG_RXDAVL:   Data available in receive FIFO
+  *            @arg SDIO_FLAG_SDIOIT:   SDIO interrupt received
+  * @retval The new state of SDIO_FLAG (SET or RESET).
+  */
+#define __SDIO_GET_FLAG(__INSTANCE__, __FLAG__)  (((__INSTANCE__)->STA &(__FLAG__)) != 0U)
+
+
+/**
+  * @brief  Clears the SDIO pending flags.
+  * @param  __INSTANCE__ : Pointer to SDIO register base  
+  * @param  __FLAG__: specifies the flag to clear.  
+  *          This parameter can be one or a combination of the following values:
+  *            @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)
+  *            @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
+  *            @arg SDIO_FLAG_CTIMEOUT: Command response timeout
+  *            @arg SDIO_FLAG_DTIMEOUT: Data timeout
+  *            @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error
+  *            @arg SDIO_FLAG_RXOVERR:  Received FIFO overrun error
+  *            @arg SDIO_FLAG_CMDREND:  Command response received (CRC check passed)
+  *            @arg SDIO_FLAG_CMDSENT:  Command sent (no response required)
+  *            @arg SDIO_FLAG_DATAEND:  Data end (data counter, DATACOUNT, is zero)
+  *            @arg SDIO_FLAG_DBCKEND:  Data block sent/received (CRC check passed)
+  *            @arg SDIO_FLAG_SDIOIT:   SDIO interrupt received
+  * @retval None
+  */
+#define __SDIO_CLEAR_FLAG(__INSTANCE__, __FLAG__)  ((__INSTANCE__)->ICR = (__FLAG__))
+
+/**
+  * @brief  Checks whether the specified SDIO interrupt has occurred or not.
+  * @param  __INSTANCE__ : Pointer to SDIO register base   
+  * @param  __INTERRUPT__: specifies the SDIO interrupt source to check. 
+  *          This parameter can be one of the following values:
+  *            @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
+  *            @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
+  *            @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
+  *            @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
+  *            @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
+  *            @arg SDIO_IT_RXOVERR:  Received FIFO overrun error interrupt
+  *            @arg SDIO_IT_CMDREND:  Command response received (CRC check passed) interrupt
+  *            @arg SDIO_IT_CMDSENT:  Command sent (no response required) interrupt
+  *            @arg SDIO_IT_DATAEND:  Data end (data counter, DATACOUNT, is zero) interrupt
+  *            @arg SDIO_IT_DBCKEND:  Data block sent/received (CRC check passed) interrupt
+  *            @arg SDIO_IT_CMDACT:   Command transfer in progress interrupt
+  *            @arg SDIO_IT_TXACT:    Data transmit in progress interrupt
+  *            @arg SDIO_IT_RXACT:    Data receive in progress interrupt
+  *            @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
+  *            @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
+  *            @arg SDIO_IT_TXFIFOF:  Transmit FIFO full interrupt
+  *            @arg SDIO_IT_RXFIFOF:  Receive FIFO full interrupt
+  *            @arg SDIO_IT_TXFIFOE:  Transmit FIFO empty interrupt
+  *            @arg SDIO_IT_RXFIFOE:  Receive FIFO empty interrupt
+  *            @arg SDIO_IT_TXDAVL:   Data available in transmit FIFO interrupt
+  *            @arg SDIO_IT_RXDAVL:   Data available in receive FIFO interrupt
+  *            @arg SDIO_IT_SDIOIT:   SDIO interrupt received interrupt
+  * @retval The new state of SDIO_IT (SET or RESET).
+  */
+#define __SDIO_GET_IT  (__INSTANCE__, __INTERRUPT__)  (((__INSTANCE__)->STA &(__INTERRUPT__)) == (__INTERRUPT__))
+
+/**
+  * @brief  Clears the SDIO's interrupt pending bits.
+  * @param  __INSTANCE__ : Pointer to SDIO register base 
+  * @param  __INTERRUPT__: specifies the interrupt pending bit to clear. 
+  *          This parameter can be one or a combination of the following values:
+  *            @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
+  *            @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
+  *            @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
+  *            @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
+  *            @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
+  *            @arg SDIO_IT_RXOVERR:  Received FIFO overrun error interrupt
+  *            @arg SDIO_IT_CMDREND:  Command response received (CRC check passed) interrupt
+  *            @arg SDIO_IT_CMDSENT:  Command sent (no response required) interrupt
+  *            @arg SDIO_IT_DATAEND:  Data end (data counter, DATACOUNT, is zero) interrupt
+  *            @arg SDIO_IT_SDIOIT:   SDIO interrupt received interrupt
+  * @retval None
+  */
+#define __SDIO_CLEAR_IT(__INSTANCE__, __INTERRUPT__)  ((__INSTANCE__)->ICR = (__INTERRUPT__))
+
+/**
+  * @brief  Enable Start the SD I/O Read Wait operation.
+  * @param  __INSTANCE__ : Pointer to SDIO register base  
+  * @retval None
+  */
+#define __SDIO_START_READWAIT_ENABLE(__INSTANCE__)  (*(__IO uint32_t *) DCTRL_RWSTART_BB = ENABLE)
+
+/**
+  * @brief  Disable Start the SD I/O Read Wait operations.
+  * @param  __INSTANCE__ : Pointer to SDIO register base   
+  * @retval None
+  */
+#define __SDIO_START_READWAIT_DISABLE(__INSTANCE__)  (*(__IO uint32_t *) DCTRL_RWSTART_BB = DISABLE)
+
+/**
+  * @brief  Enable Start the SD I/O Read Wait operation.
+  * @param  __INSTANCE__ : Pointer to SDIO register base   
+  * @retval None
+  */
+#define __SDIO_STOP_READWAIT_ENABLE(__INSTANCE__)  (*(__IO uint32_t *) DCTRL_RWSTOP_BB = ENABLE)
+
+/**
+  * @brief  Disable Stop the SD I/O Read Wait operations.
+  * @param  __INSTANCE__ : Pointer to SDIO register base  
+  * @retval None
+  */
+#define __SDIO_STOP_READWAIT_DISABLE(__INSTANCE__)  (*(__IO uint32_t *) DCTRL_RWSTOP_BB = DISABLE)
+
+/**
+  * @brief  Enable the SD I/O Mode Operation.
+  * @param  __INSTANCE__ : Pointer to SDIO register base   
+  * @retval None
+  */
+#define __SDIO_OPERATION_ENABLE(__INSTANCE__)  (*(__IO uint32_t *) DCTRL_SDIOEN_BB = ENABLE)
+
+/**
+  * @brief  Disable the SD I/O Mode Operation.
+  * @param  __INSTANCE__ : Pointer to SDIO register base 
+  * @retval None
+  */
+#define __SDIO_OPERATION_DISABLE(__INSTANCE__)  (*(__IO uint32_t *) DCTRL_SDIOEN_BB = DISABLE)
+
+/**
+  * @brief  Enable the SD I/O Suspend command sending.
+  * @param  __INSTANCE__ : Pointer to SDIO register base  
+  * @retval None
+  */
+#define __SDIO_SUSPEND_CMD_ENABLE(__INSTANCE__)  (*(__IO uint32_t *) CMD_SDIOSUSPEND_BB = ENABLE)
+
+/**
+  * @brief  Disable the SD I/O Suspend command sending.
+  * @param  __INSTANCE__ : Pointer to SDIO register base  
+  * @retval None
+  */
+#define __SDIO_SUSPEND_CMD_DISABLE(__INSTANCE__)  (*(__IO uint32_t *) CMD_SDIOSUSPEND_BB = DISABLE)
+
+#if defined(SDIO_CMD_CEATACMD)
+/**
+  * @brief  Enable the command completion signal.
+  * @retval None
+  */    
+#define __SDIO_CEATA_CMD_COMPLETION_ENABLE()   (*(__IO uint32_t *) CMD_ENCMDCOMPL_BB = ENABLE)
+
+/**
+  * @brief  Disable the command completion signal.
+  * @retval None
+  */  
+#define __SDIO_CEATA_CMD_COMPLETION_DISABLE()   (*(__IO uint32_t *) CMD_ENCMDCOMPL_BB = DISABLE)
+
+/**
+  * @brief  Enable the CE-ATA interrupt.
+  * @retval None
+  */    
+#define __SDIO_CEATA_ENABLE_IT()   (*(__IO uint32_t *) CMD_NIEN_BB = (uint32_t)0U)
+
+/**
+  * @brief  Disable the CE-ATA interrupt.
+  * @retval None
+  */  
+#define __SDIO_CEATA_DISABLE_IT()   (*(__IO uint32_t *) CMD_NIEN_BB = (uint32_t)1U)
+
+/**
+  * @brief  Enable send CE-ATA command (CMD61).
+  * @retval None
+  */  
+#define __SDIO_CEATA_SENDCMD_ENABLE()   (*(__IO uint32_t *) CMD_ATACMD_BB = ENABLE)
+
+/**
+  * @brief  Disable send CE-ATA command (CMD61).
+  * @retval None
+  */  
+#define __SDIO_CEATA_SENDCMD_DISABLE()   (*(__IO uint32_t *) CMD_ATACMD_BB = DISABLE)
+   
+#endif
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */  
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup SDMMC_LL_Exported_Functions
+  * @{
+  */
+  
+/* Initialization/de-initialization functions  **********************************/
+/** @addtogroup HAL_SDMMC_LL_Group1
+  * @{
+  */
+HAL_StatusTypeDef SDIO_Init(SDIO_TypeDef *SDIOx, SDIO_InitTypeDef Init);
+/**
+  * @}
+  */
+  
+/* I/O operation functions  *****************************************************/
+/** @addtogroup HAL_SDMMC_LL_Group2
+  * @{
+  */
+uint32_t          SDIO_ReadFIFO(SDIO_TypeDef *SDIOx);
+HAL_StatusTypeDef SDIO_WriteFIFO(SDIO_TypeDef *SDIOx, uint32_t *pWriteData);
+/**
+  * @}
+  */
+  
+/* Peripheral Control functions  ************************************************/
+/** @addtogroup HAL_SDMMC_LL_Group3
+  * @{
+  */
+HAL_StatusTypeDef SDIO_PowerState_ON(SDIO_TypeDef *SDIOx);
+HAL_StatusTypeDef SDIO_PowerState_OFF(SDIO_TypeDef *SDIOx);
+uint32_t          SDIO_GetPowerState(SDIO_TypeDef *SDIOx);
+
+/* Command path state machine (CPSM) management functions */
+HAL_StatusTypeDef SDIO_SendCommand(SDIO_TypeDef *SDIOx, SDIO_CmdInitTypeDef *Command);
+uint8_t           SDIO_GetCommandResponse(SDIO_TypeDef *SDIOx);
+uint32_t          SDIO_GetResponse(SDIO_TypeDef *SDIOx, uint32_t Response);
+
+/* Data path state machine (DPSM) management functions */
+HAL_StatusTypeDef SDIO_ConfigData(SDIO_TypeDef *SDIOx, SDIO_DataInitTypeDef* Data);
+uint32_t          SDIO_GetDataCounter(SDIO_TypeDef *SDIOx);
+uint32_t          SDIO_GetFIFOCount(SDIO_TypeDef *SDIOx);
+
+/* SDMMC Cards mode management functions */
+HAL_StatusTypeDef SDIO_SetSDMMCReadWaitMode(SDIO_TypeDef *SDIOx, uint32_t SDIO_ReadWaitMode);
+/**
+  * @}
+  */
+
+/* SDMMC Commands management functions */
+/** @addtogroup HAL_SDMMC_LL_Group4
+  * @{
+  */
+uint32_t SDMMC_CmdBlockLength(SDIO_TypeDef *SDIOx, uint32_t BlockSize);
+uint32_t SDMMC_CmdReadSingleBlock(SDIO_TypeDef *SDIOx, uint32_t ReadAdd);
+uint32_t SDMMC_CmdReadMultiBlock(SDIO_TypeDef *SDIOx, uint32_t ReadAdd);
+uint32_t SDMMC_CmdWriteSingleBlock(SDIO_TypeDef *SDIOx, uint32_t WriteAdd);
+uint32_t SDMMC_CmdWriteMultiBlock(SDIO_TypeDef *SDIOx, uint32_t WriteAdd);
+uint32_t SDMMC_CmdEraseStartAdd(SDIO_TypeDef *SDIOx, uint32_t StartAdd);
+uint32_t SDMMC_CmdSDEraseStartAdd(SDIO_TypeDef *SDIOx, uint32_t StartAdd);
+uint32_t SDMMC_CmdEraseEndAdd(SDIO_TypeDef *SDIOx, uint32_t EndAdd);
+uint32_t SDMMC_CmdSDEraseEndAdd(SDIO_TypeDef *SDIOx, uint32_t EndAdd);
+uint32_t SDMMC_CmdErase(SDIO_TypeDef *SDIOx);
+uint32_t SDMMC_CmdStopTransfer(SDIO_TypeDef *SDIOx);
+uint32_t SDMMC_CmdSelDesel(SDIO_TypeDef *SDIOx, uint64_t Addr);
+uint32_t SDMMC_CmdGoIdleState(SDIO_TypeDef *SDIOx);
+uint32_t SDMMC_CmdOperCond(SDIO_TypeDef *SDIOx);
+uint32_t SDMMC_CmdAppCommand(SDIO_TypeDef *SDIOx, uint32_t Argument);
+uint32_t SDMMC_CmdAppOperCommand(SDIO_TypeDef *SDIOx, uint32_t Argument);
+uint32_t SDMMC_CmdBusWidth(SDIO_TypeDef *SDIOx, uint32_t BusWidth);
+uint32_t SDMMC_CmdSendSCR(SDIO_TypeDef *SDIOx);
+uint32_t SDMMC_CmdSendCID(SDIO_TypeDef *SDIOx);
+uint32_t SDMMC_CmdSendCSD(SDIO_TypeDef *SDIOx, uint32_t Argument);
+uint32_t SDMMC_CmdSetRelAdd(SDIO_TypeDef *SDIOx, uint16_t *pRCA);
+uint32_t SDMMC_CmdSetRelAddMmc(SDIO_TypeDef *SDIOx, uint16_t RCA);
+uint32_t SDMMC_CmdSendStatus(SDIO_TypeDef *SDIOx, uint32_t Argument);
+uint32_t SDMMC_CmdStatusRegister(SDIO_TypeDef *SDIOx);
+uint32_t SDMMC_CmdOpCondition(SDIO_TypeDef *SDIOx, uint32_t Argument);
+uint32_t SDMMC_CmdSwitch(SDIO_TypeDef *SDIOx, uint32_t Argument);
+uint32_t SDMMC_CmdSendEXTCSD(SDIO_TypeDef *SDIOx, uint32_t Argument);
+/**
+  * @}
+  */
+
+/* SDMMC Responses management functions *****************************************/
+/** @addtogroup HAL_SDMMC_LL_Group5
+  * @{
+  */
+uint32_t SDMMC_GetCmdResp1(SDIO_TypeDef *SDIOx, uint8_t SD_CMD, uint32_t Timeout);
+uint32_t SDMMC_GetCmdResp2(SDIO_TypeDef *SDIOx);
+uint32_t SDMMC_GetCmdResp3(SDIO_TypeDef *SDIOx);
+uint32_t SDMMC_GetCmdResp6(SDIO_TypeDef *SDIOx, uint8_t SD_CMD, uint16_t *pRCA);
+uint32_t SDMMC_GetCmdResp7(SDIO_TypeDef *SDIOx);
+/**
+  * @}
+  */
+  
+/**
+  * @}
+  */
+  
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */
+
+#endif /* SDIO */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32F4xx_LL_SDMMC_H */
diff --git a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_system.h b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_system.h
new file mode 100644
index 0000000..48bcc1a
--- /dev/null
+++ b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_system.h
@@ -0,0 +1,1711 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_ll_system.h
+  * @author  MCD Application Team
+  * @brief   Header file of SYSTEM LL module.
+  *
+  ******************************************************************************
+  * @attention
+  *
+  *Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  @verbatim
+  ==============================================================================
+                     ##### How to use this driver #####
+  ==============================================================================
+    [..]
+    The LL SYSTEM driver contains a set of generic APIs that can be
+    used by user:
+      (+) Some of the FLASH features need to be handled in the SYSTEM file.
+      (+) Access to DBGCMU registers
+      (+) Access to SYSCFG registers
+
+  @endverbatim
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_LL_SYSTEM_H
+#define __STM32F4xx_LL_SYSTEM_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx.h"
+
+/** @addtogroup STM32F4xx_LL_Driver
+  * @{
+  */
+
+#if defined (FLASH) || defined (SYSCFG) || defined (DBGMCU)
+
+/** @defgroup SYSTEM_LL SYSTEM
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup SYSTEM_LL_Private_Constants SYSTEM Private Constants
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup SYSTEM_LL_Exported_Constants SYSTEM Exported Constants
+  * @{
+  */
+
+/** @defgroup SYSTEM_LL_EC_REMAP SYSCFG REMAP
+* @{
+*/
+#define LL_SYSCFG_REMAP_FLASH              (uint32_t)0x00000000                                  /*!< Main Flash memory mapped at 0x00000000              */
+#define LL_SYSCFG_REMAP_SYSTEMFLASH        SYSCFG_MEMRMP_MEM_MODE_0                              /*!< System Flash memory mapped at 0x00000000            */
+#if defined(FSMC_Bank1)
+#define LL_SYSCFG_REMAP_FSMC               SYSCFG_MEMRMP_MEM_MODE_1                              /*!< FSMC(NOR/PSRAM 1 and 2) mapped at 0x00000000        */
+#endif /* FSMC_Bank1 */
+#if defined(FMC_Bank1)
+#define LL_SYSCFG_REMAP_FMC                SYSCFG_MEMRMP_MEM_MODE_1                              /*!< FMC(NOR/PSRAM 1 and 2) mapped at 0x00000000         */
+#define LL_SYSCFG_REMAP_SDRAM              SYSCFG_MEMRMP_MEM_MODE_2                              /*!< FMC/SDRAM mapped at 0x00000000                      */
+#endif /* FMC_Bank1 */
+#define LL_SYSCFG_REMAP_SRAM               (SYSCFG_MEMRMP_MEM_MODE_1 | SYSCFG_MEMRMP_MEM_MODE_0) /*!< SRAM1 mapped at 0x00000000                          */
+
+/**
+  * @}
+  */
+
+#if defined(SYSCFG_PMC_MII_RMII_SEL)
+ /** @defgroup SYSTEM_LL_EC_PMC SYSCFG PMC
+* @{
+*/
+#define LL_SYSCFG_PMC_ETHMII               (uint32_t)0x00000000                                /*!< ETH Media MII interface */
+#define LL_SYSCFG_PMC_ETHRMII              (uint32_t)SYSCFG_PMC_MII_RMII_SEL                   /*!< ETH Media RMII interface */
+
+/**
+  * @}
+  */
+#endif /* SYSCFG_PMC_MII_RMII_SEL */
+
+
+
+#if defined(SYSCFG_MEMRMP_UFB_MODE)
+/** @defgroup SYSTEM_LL_EC_BANKMODE SYSCFG BANK MODE
+  * @{
+  */
+#define LL_SYSCFG_BANKMODE_BANK1          (uint32_t)0x00000000       /*!< Flash Bank 1 base address mapped at 0x0800 0000 (AXI) and 0x0020 0000 (TCM)
+                                                                      and Flash Bank 2 base address mapped at 0x0810 0000 (AXI) and 0x0030 0000 (TCM)*/
+#define LL_SYSCFG_BANKMODE_BANK2          SYSCFG_MEMRMP_UFB_MODE     /*!< Flash Bank 2 base address mapped at 0x0800 0000 (AXI) and 0x0020 0000(TCM)
+                                                                      and Flash Bank 1 base address mapped at 0x0810 0000 (AXI) and 0x0030 0000(TCM) */
+/**
+  * @}
+  */
+#endif /* SYSCFG_MEMRMP_UFB_MODE */
+/** @defgroup SYSTEM_LL_EC_I2C_FASTMODEPLUS SYSCFG I2C FASTMODEPLUS
+  * @{
+  */ 
+#if defined(SYSCFG_CFGR_FMPI2C1_SCL)
+#define LL_SYSCFG_I2C_FASTMODEPLUS_SCL         SYSCFG_CFGR_FMPI2C1_SCL   /*!< Enable Fast Mode Plus on FMPI2C_SCL pin */
+#define LL_SYSCFG_I2C_FASTMODEPLUS_SDA         SYSCFG_CFGR_FMPI2C1_SDA   /*!< Enable Fast Mode Plus on FMPI2C_SDA pin*/
+#endif /* SYSCFG_CFGR_FMPI2C1_SCL */
+/**
+  * @}
+  */
+
+/** @defgroup SYSTEM_LL_EC_EXTI_PORT SYSCFG EXTI PORT
+  * @{
+  */
+#define LL_SYSCFG_EXTI_PORTA               (uint32_t)0               /*!< EXTI PORT A                        */
+#define LL_SYSCFG_EXTI_PORTB               (uint32_t)1               /*!< EXTI PORT B                        */
+#define LL_SYSCFG_EXTI_PORTC               (uint32_t)2               /*!< EXTI PORT C                        */
+#define LL_SYSCFG_EXTI_PORTD               (uint32_t)3               /*!< EXTI PORT D                        */
+#define LL_SYSCFG_EXTI_PORTE               (uint32_t)4               /*!< EXTI PORT E                        */
+#if defined(GPIOF)
+#define LL_SYSCFG_EXTI_PORTF               (uint32_t)5               /*!< EXTI PORT F                        */
+#endif /* GPIOF */
+#if defined(GPIOG)
+#define LL_SYSCFG_EXTI_PORTG               (uint32_t)6               /*!< EXTI PORT G                        */
+#endif /* GPIOG */
+#define LL_SYSCFG_EXTI_PORTH               (uint32_t)7               /*!< EXTI PORT H                        */
+#if defined(GPIOI)
+#define LL_SYSCFG_EXTI_PORTI               (uint32_t)8               /*!< EXTI PORT I                        */
+#endif /* GPIOI */
+#if defined(GPIOJ)
+#define LL_SYSCFG_EXTI_PORTJ               (uint32_t)9               /*!< EXTI PORT J                        */
+#endif /* GPIOJ */
+#if defined(GPIOK)
+#define LL_SYSCFG_EXTI_PORTK               (uint32_t)10              /*!< EXTI PORT k                        */
+#endif /* GPIOK */
+/**
+  * @}
+  */
+
+/** @defgroup SYSTEM_LL_EC_EXTI_LINE SYSCFG EXTI LINE
+  * @{
+  */
+#define LL_SYSCFG_EXTI_LINE0               (uint32_t)(0x000FU << 16 | 0)  /*!< EXTI_POSITION_0  | EXTICR[0] */
+#define LL_SYSCFG_EXTI_LINE1               (uint32_t)(0x00F0U << 16 | 0)  /*!< EXTI_POSITION_4  | EXTICR[0] */
+#define LL_SYSCFG_EXTI_LINE2               (uint32_t)(0x0F00U << 16 | 0)  /*!< EXTI_POSITION_8  | EXTICR[0] */
+#define LL_SYSCFG_EXTI_LINE3               (uint32_t)(0xF000U << 16 | 0)  /*!< EXTI_POSITION_12 | EXTICR[0] */
+#define LL_SYSCFG_EXTI_LINE4               (uint32_t)(0x000FU << 16 | 1)  /*!< EXTI_POSITION_0  | EXTICR[1] */
+#define LL_SYSCFG_EXTI_LINE5               (uint32_t)(0x00F0U << 16 | 1)  /*!< EXTI_POSITION_4  | EXTICR[1] */
+#define LL_SYSCFG_EXTI_LINE6               (uint32_t)(0x0F00U << 16 | 1)  /*!< EXTI_POSITION_8  | EXTICR[1] */
+#define LL_SYSCFG_EXTI_LINE7               (uint32_t)(0xF000U << 16 | 1)  /*!< EXTI_POSITION_12 | EXTICR[1] */
+#define LL_SYSCFG_EXTI_LINE8               (uint32_t)(0x000FU << 16 | 2)  /*!< EXTI_POSITION_0  | EXTICR[2] */
+#define LL_SYSCFG_EXTI_LINE9               (uint32_t)(0x00F0U << 16 | 2)  /*!< EXTI_POSITION_4  | EXTICR[2] */
+#define LL_SYSCFG_EXTI_LINE10              (uint32_t)(0x0F00U << 16 | 2)  /*!< EXTI_POSITION_8  | EXTICR[2] */
+#define LL_SYSCFG_EXTI_LINE11              (uint32_t)(0xF000U << 16 | 2)  /*!< EXTI_POSITION_12 | EXTICR[2] */
+#define LL_SYSCFG_EXTI_LINE12              (uint32_t)(0x000FU << 16 | 3)  /*!< EXTI_POSITION_0  | EXTICR[3] */
+#define LL_SYSCFG_EXTI_LINE13              (uint32_t)(0x00F0U << 16 | 3)  /*!< EXTI_POSITION_4  | EXTICR[3] */
+#define LL_SYSCFG_EXTI_LINE14              (uint32_t)(0x0F00U << 16 | 3)  /*!< EXTI_POSITION_8  | EXTICR[3] */
+#define LL_SYSCFG_EXTI_LINE15              (uint32_t)(0xF000U << 16 | 3)  /*!< EXTI_POSITION_12 | EXTICR[3] */
+/**
+  * @}
+  */
+
+/** @defgroup SYSTEM_LL_EC_TIMBREAK SYSCFG TIMER BREAK
+  * @{
+  */
+#if defined(SYSCFG_CFGR2_LOCKUP_LOCK)
+#define LL_SYSCFG_TIMBREAK_LOCKUP          SYSCFG_CFGR2_LOCKUP_LOCK   /*!< Enables and locks the LOCKUP output of CortexM4 
+                                                                      with Break Input of TIM1/8                                    */
+#define LL_SYSCFG_TIMBREAK_PVD             SYSCFG_CFGR2_PVD_LOCK      /*!< Enables and locks the PVD connection with TIM1/8 Break Input 
+                                                                      and also the PVDE and PLS bits of the Power Control Interface  */
+#endif /* SYSCFG_CFGR2_CLL */
+/**
+  * @}
+  */
+
+#if defined(SYSCFG_MCHDLYCR_BSCKSEL)
+/** @defgroup SYSTEM_LL_DFSDM_BitStream_ClockSource SYSCFG MCHDLY BCKKSEL
+  * @{
+  */
+#define LL_SYSCFG_BITSTREAM_CLOCK_TIM2OC1          (uint32_t)0x00000000
+#define LL_SYSCFG_BITSTREAM_CLOCK_DFSDM2           SYSCFG_MCHDLYCR_BSCKSEL
+/**
+  * @}
+  */
+/** @defgroup SYSTEM_LL_DFSDM_MCHDLYEN              SYSCFG MCHDLY MCHDLYEN
+  * @{
+  */  
+#define LL_SYSCFG_DFSDM1_MCHDLYEN                  SYSCFG_MCHDLYCR_MCHDLY1EN
+#define LL_SYSCFG_DFSDM2_MCHDLYEN                  SYSCFG_MCHDLYCR_MCHDLY2EN
+/**
+  * @}
+  */
+/** @defgroup SYSTEM_LL_DFSDM_DataIn0_Source       SYSCFG MCHDLY DFSDMD0SEL
+  * @{
+  */
+#define LL_SYSCFG_DFSDM1_DataIn0                   SYSCFG_MCHDLYCR_DFSDM1D0SEL
+#define LL_SYSCFG_DFSDM2_DataIn0                   SYSCFG_MCHDLYCR_DFSDM2D0SEL
+
+#define LL_SYSCFG_DFSDM1_DataIn0_PAD               (uint32_t)((SYSCFG_MCHDLYCR_DFSDM1D0SEL << 16) | 0x00000000)
+#define LL_SYSCFG_DFSDM1_DataIn0_DM                (uint32_t)((SYSCFG_MCHDLYCR_DFSDM1D0SEL << 16) | SYSCFG_MCHDLYCR_DFSDM1D0SEL)
+#define LL_SYSCFG_DFSDM2_DataIn0_PAD               (uint32_t)((SYSCFG_MCHDLYCR_DFSDM2D0SEL << 16) | 0x00000000)
+#define LL_SYSCFG_DFSDM2_DataIn0_DM                (uint32_t)((SYSCFG_MCHDLYCR_DFSDM2D0SEL << 16) | SYSCFG_MCHDLYCR_DFSDM2D0SEL)
+/**
+  * @}
+  */
+/** @defgroup SYSTEM_LL_DFSDM_DataIn2_Source       SYSCFG MCHDLY DFSDMD2SEL
+  * @{
+  */   
+#define LL_SYSCFG_DFSDM1_DataIn2                   SYSCFG_MCHDLYCR_DFSDM1D2SEL
+#define LL_SYSCFG_DFSDM2_DataIn2                   SYSCFG_MCHDLYCR_DFSDM2D2SEL
+
+#define LL_SYSCFG_DFSDM1_DataIn2_PAD               (uint32_t)((SYSCFG_MCHDLYCR_DFSDM1D2SEL << 16) | 0x00000000)
+#define LL_SYSCFG_DFSDM1_DataIn2_DM                (uint32_t)((SYSCFG_MCHDLYCR_DFSDM1D2SEL << 16) | SYSCFG_MCHDLYCR_DFSDM1D2SEL)
+#define LL_SYSCFG_DFSDM2_DataIn2_PAD               (uint32_t)((SYSCFG_MCHDLYCR_DFSDM2D2SEL << 16) | 0x00000000)
+#define LL_SYSCFG_DFSDM2_DataIn2_DM                (uint32_t)((SYSCFG_MCHDLYCR_DFSDM2D2SEL << 16) | SYSCFG_MCHDLYCR_DFSDM2D2SEL)
+/**
+  * @}
+  */
+/** @defgroup SYSTEM_LL_DFSDM1_TIM4OC2_BitstreamDistribution  SYSCFG MCHDLY DFSDM1CK02SEL
+  * @{
+  */ 
+#define LL_SYSCFG_DFSDM1_TIM4OC2_CLKIN0           (uint32_t)0x00000000
+#define LL_SYSCFG_DFSDM1_TIM4OC2_CLKIN2           SYSCFG_MCHDLYCR_DFSDM1CK02SEL
+/**
+  * @}
+  */
+/** @defgroup SYSTEM_LL_DFSDM1_TIM4OC1_BitstreamDistribution  SYSCFG MCHDLY DFSDM1CK13SEL
+  * @{
+  */ 
+#define LL_SYSCFG_DFSDM1_TIM4OC1_CLKIN1           (uint32_t)0x00000000
+#define LL_SYSCFG_DFSDM1_TIM4OC1_CLKIN3           SYSCFG_MCHDLYCR_DFSDM1CK13SEL
+/**
+  * @}
+  */
+/** @defgroup SYSTEM_LL_DFSDM1_CLKIN_SourceSelection SYSCFG MCHDLY DFSDMCFG
+  * @{
+  */
+#define LL_SYSCFG_DFSDM1_CKIN_PAD                 (uint32_t)0x00000000
+#define LL_SYSCFG_DFSDM1_CKIN_DM                  SYSCFG_MCHDLYCR_DFSDM1CFG
+/**
+  * @}
+  */
+/** @defgroup SYSTEM_LL_DFSDM1_CLKOUT_SourceSelection SYSCFG MCHDLY DFSDM1CKOSEL
+  * @{
+  */ 
+#define LL_SYSCFG_DFSDM1_CKOUT                    (uint32_t)0x00000000
+#define LL_SYSCFG_DFSDM1_CKOUT_M27                SYSCFG_MCHDLYCR_DFSDM1CKOSEL
+/**
+  * @}
+  */
+
+/** @defgroup SYSTEM_LL_DFSDM2_DataIn4_SourceSelection SYSCFG MCHDLY DFSDM2D4SEL
+  * @{
+  */ 
+#define LL_SYSCFG_DFSDM2_DataIn4_PAD              (uint32_t)0x00000000
+#define LL_SYSCFG_DFSDM2_DataIn4_DM               SYSCFG_MCHDLYCR_DFSDM2D4SEL
+/**
+  * @}
+  */
+/** @defgroup SYSTEM_LL_DFSDM2_DataIn6_SourceSelection SYSCFG MCHDLY DFSDM2D6SEL
+  * @{
+  */ 
+#define LL_SYSCFG_DFSDM2_DataIn6_PAD              (uint32_t)0x00000000
+#define LL_SYSCFG_DFSDM2_DataIn6_DM               SYSCFG_MCHDLYCR_DFSDM2D6SEL
+/**
+  * @}
+  */
+/** @defgroup SYSTEM_LL_DFSDM2_TIM3OC4_BitstreamDistribution  SYSCFG MCHDLY DFSDM2CK04SEL
+  * @{
+  */ 
+#define LL_SYSCFG_DFSDM2_TIM3OC4_CLKIN0           (uint32_t)0x00000000
+#define LL_SYSCFG_DFSDM2_TIM3OC4_CLKIN4           SYSCFG_MCHDLYCR_DFSDM2CK04SEL
+/**
+  * @}
+  */
+/** @defgroup SYSTEM_LL_DFSDM2_TIM3OC3_BitstreamDistribution  SYSCFG MCHDLY DFSDM2CK15SEL
+  * @{
+  */ 
+#define LL_SYSCFG_DFSDM2_TIM3OC3_CLKIN1           (uint32_t)0x00000000
+#define LL_SYSCFG_DFSDM2_TIM3OC3_CLKIN5           SYSCFG_MCHDLYCR_DFSDM2CK15SEL
+/**
+  * @}
+  */
+/** @defgroup SYSTEM_LL_DFSDM2_TIM3OC2_BitstreamDistribution  SYSCFG MCHDLY DFSDM2CK26SEL
+  * @{
+  */ 
+#define LL_SYSCFG_DFSDM2_TIM3OC2_CLKIN2           (uint32_t)0x00000000
+#define LL_SYSCFG_DFSDM2_TIM3OC2_CLKIN6           SYSCFG_MCHDLYCR_DFSDM2CK26SEL
+/**
+  * @}
+  */
+/** @defgroup SYSTEM_LL_DFSDM2_TIM3OC1_BitstreamDistribution  SYSCFG MCHDLY DFSDM2CK37SEL
+  * @{
+  */ 
+#define LL_SYSCFG_DFSDM2_TIM3OC1_CLKIN3           (uint32_t)0x00000000
+#define LL_SYSCFG_DFSDM2_TIM3OC1_CLKIN7           SYSCFG_MCHDLYCR_DFSDM2CK37SEL
+/**
+  * @}
+  */
+/** @defgroup SYSTEM_LL_DFSDM2_CLKIN_SourceSelection SYSCFG MCHDLY DFSDM2CFG
+  * @{
+  */ 
+#define LL_SYSCFG_DFSDM2_CKIN_PAD                 (uint32_t)0x00000000
+#define LL_SYSCFG_DFSDM2_CKIN_DM                  SYSCFG_MCHDLYCR_DFSDM2CFG
+/**
+  * @}
+  */
+/** @defgroup SYSTEM_LL_DFSDM2_CLKOUT_SourceSelection SYSCFG MCHDLY DFSDM2CKOSEL
+  * @{
+  */ 
+#define LL_SYSCFG_DFSDM2_CKOUT                    (uint32_t)0x00000000
+#define LL_SYSCFG_DFSDM2_CKOUT_M27                SYSCFG_MCHDLYCR_DFSDM2CKOSEL
+/**
+  * @}
+  */ 
+#endif /* SYSCFG_MCHDLYCR_BSCKSEL */  
+
+/** @defgroup SYSTEM_LL_EC_TRACE DBGMCU TRACE Pin Assignment
+  * @{
+  */
+#define LL_DBGMCU_TRACE_NONE               0x00000000U                                     /*!< TRACE pins not assigned (default state) */
+#define LL_DBGMCU_TRACE_ASYNCH             DBGMCU_CR_TRACE_IOEN                            /*!< TRACE pin assignment for Asynchronous Mode */
+#define LL_DBGMCU_TRACE_SYNCH_SIZE1        (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_0) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 1 */
+#define LL_DBGMCU_TRACE_SYNCH_SIZE2        (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_1) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 2 */
+#define LL_DBGMCU_TRACE_SYNCH_SIZE4        (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE)   /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 4 */
+/**
+  * @}
+  */
+
+/** @defgroup SYSTEM_LL_EC_APB1_GRP1_STOP_IP DBGMCU APB1 GRP1 STOP IP
+  * @{
+  */
+#if defined(DBGMCU_APB1_FZ_DBG_TIM2_STOP)
+#define LL_DBGMCU_APB1_GRP1_TIM2_STOP      DBGMCU_APB1_FZ_DBG_TIM2_STOP          /*!< TIM2 counter stopped when core is halted */
+#endif /* DBGMCU_APB1_FZ_DBG_TIM2_STOP */
+#if defined(DBGMCU_APB1_FZ_DBG_TIM3_STOP)
+#define LL_DBGMCU_APB1_GRP1_TIM3_STOP      DBGMCU_APB1_FZ_DBG_TIM3_STOP          /*!< TIM3 counter stopped when core is halted */
+#endif /* DBGMCU_APB1_FZ_DBG_TIM3_STOP */
+#if defined(DBGMCU_APB1_FZ_DBG_TIM4_STOP)
+#define LL_DBGMCU_APB1_GRP1_TIM4_STOP      DBGMCU_APB1_FZ_DBG_TIM4_STOP          /*!< TIM4 counter stopped when core is halted */
+#endif /* DBGMCU_APB1_FZ_DBG_TIM4_STOP */
+#define LL_DBGMCU_APB1_GRP1_TIM5_STOP      DBGMCU_APB1_FZ_DBG_TIM5_STOP          /*!< TIM5 counter stopped when core is halted */
+#if defined(DBGMCU_APB1_FZ_DBG_TIM6_STOP)
+#define LL_DBGMCU_APB1_GRP1_TIM6_STOP      DBGMCU_APB1_FZ_DBG_TIM6_STOP          /*!< TIM6 counter stopped when core is halted */
+#endif /* DBGMCU_APB1_FZ_DBG_TIM6_STOP */
+#if defined(DBGMCU_APB1_FZ_DBG_TIM7_STOP)
+#define LL_DBGMCU_APB1_GRP1_TIM7_STOP      DBGMCU_APB1_FZ_DBG_TIM7_STOP          /*!< TIM7 counter stopped when core is halted */
+#endif /* DBGMCU_APB1_FZ_DBG_TIM7_STOP */
+#if defined(DBGMCU_APB1_FZ_DBG_TIM12_STOP)
+#define LL_DBGMCU_APB1_GRP1_TIM12_STOP     DBGMCU_APB1_FZ_DBG_TIM12_STOP         /*!< TIM12 counter stopped when core is halted */
+#endif /* DBGMCU_APB1_FZ_DBG_TIM12_STOP */
+#if defined(DBGMCU_APB1_FZ_DBG_TIM13_STOP)
+#define LL_DBGMCU_APB1_GRP1_TIM13_STOP     DBGMCU_APB1_FZ_DBG_TIM13_STOP         /*!< TIM13 counter stopped when core is halted */
+#endif /* DBGMCU_APB1_FZ_DBG_TIM13_STOP */
+#if defined(DBGMCU_APB1_FZ_DBG_TIM14_STOP)
+#define LL_DBGMCU_APB1_GRP1_TIM14_STOP     DBGMCU_APB1_FZ_DBG_TIM14_STOP         /*!< TIM14 counter stopped when core is halted */
+#endif /* DBGMCU_APB1_FZ_DBG_TIM14_STOP */
+#if defined(DBGMCU_APB1_FZ_DBG_LPTIM_STOP)
+#define LL_DBGMCU_APB1_GRP1_LPTIM_STOP     DBGMCU_APB1_FZ_DBG_LPTIM_STOP         /*!< LPTIM counter stopped when core is halted */
+#endif /* DBGMCU_APB1_FZ_DBG_LPTIM_STOP */
+#define LL_DBGMCU_APB1_GRP1_RTC_STOP       DBGMCU_APB1_FZ_DBG_RTC_STOP           /*!< RTC counter stopped when core is halted */
+#define LL_DBGMCU_APB1_GRP1_WWDG_STOP      DBGMCU_APB1_FZ_DBG_WWDG_STOP          /*!< Debug Window Watchdog stopped when Core is halted */
+#define LL_DBGMCU_APB1_GRP1_IWDG_STOP      DBGMCU_APB1_FZ_DBG_IWDG_STOP          /*!< Debug Independent Watchdog stopped when Core is halted */
+#define LL_DBGMCU_APB1_GRP1_I2C1_STOP      DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT /*!< I2C1 SMBUS timeout mode stopped when Core is halted */
+#define LL_DBGMCU_APB1_GRP1_I2C2_STOP      DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT /*!< I2C2 SMBUS timeout mode stopped when Core is halted */
+#if defined(DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT)
+#define LL_DBGMCU_APB1_GRP1_I2C3_STOP      DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT /*!< I2C3 SMBUS timeout mode stopped when Core is halted */
+#endif /* DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT */
+#if defined(DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT)
+#define LL_DBGMCU_APB1_GRP1_I2C4_STOP      DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT /*!< I2C4 SMBUS timeout mode stopped when Core is halted */
+#endif /* DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT */
+#if defined(DBGMCU_APB1_FZ_DBG_CAN1_STOP)
+#define LL_DBGMCU_APB1_GRP1_CAN1_STOP      DBGMCU_APB1_FZ_DBG_CAN1_STOP          /*!< CAN1 debug stopped when Core is halted  */
+#endif /* DBGMCU_APB1_FZ_DBG_CAN1_STOP */
+#if defined(DBGMCU_APB1_FZ_DBG_CAN2_STOP)
+#define LL_DBGMCU_APB1_GRP1_CAN2_STOP      DBGMCU_APB1_FZ_DBG_CAN2_STOP          /*!< CAN2 debug stopped when Core is halted  */
+#endif /* DBGMCU_APB1_FZ_DBG_CAN2_STOP */
+#if defined(DBGMCU_APB1_FZ_DBG_CAN3_STOP)
+#define LL_DBGMCU_APB1_GRP1_CAN3_STOP      DBGMCU_APB1_FZ_DBG_CAN3_STOP          /*!< CAN3 debug stopped when Core is halted  */
+#endif /* DBGMCU_APB1_FZ_DBG_CAN3_STOP */
+/**
+  * @}
+  */
+
+/** @defgroup SYSTEM_LL_EC_APB2_GRP1_STOP_IP DBGMCU APB2 GRP1 STOP IP
+  * @{
+  */
+#define LL_DBGMCU_APB2_GRP1_TIM1_STOP      DBGMCU_APB2_FZ_DBG_TIM1_STOP   /*!< TIM1 counter stopped when core is halted */
+#if defined(DBGMCU_APB2_FZ_DBG_TIM8_STOP)
+#define LL_DBGMCU_APB2_GRP1_TIM8_STOP      DBGMCU_APB2_FZ_DBG_TIM8_STOP   /*!< TIM8 counter stopped when core is halted */
+#endif /* DBGMCU_APB2_FZ_DBG_TIM8_STOP */
+#define LL_DBGMCU_APB2_GRP1_TIM9_STOP      DBGMCU_APB2_FZ_DBG_TIM9_STOP   /*!< TIM9 counter stopped when core is halted */
+#if defined(DBGMCU_APB2_FZ_DBG_TIM10_STOP)
+#define LL_DBGMCU_APB2_GRP1_TIM10_STOP     DBGMCU_APB2_FZ_DBG_TIM10_STOP   /*!< TIM10 counter stopped when core is halted */
+#endif /* DBGMCU_APB2_FZ_DBG_TIM10_STOP */
+#define LL_DBGMCU_APB2_GRP1_TIM11_STOP     DBGMCU_APB2_FZ_DBG_TIM11_STOP   /*!< TIM11 counter stopped when core is halted */
+/**
+  * @}
+  */
+
+/** @defgroup SYSTEM_LL_EC_LATENCY FLASH LATENCY
+  * @{
+  */
+#define LL_FLASH_LATENCY_0                 FLASH_ACR_LATENCY_0WS   /*!< FLASH Zero wait state */
+#define LL_FLASH_LATENCY_1                 FLASH_ACR_LATENCY_1WS   /*!< FLASH One wait state */
+#define LL_FLASH_LATENCY_2                 FLASH_ACR_LATENCY_2WS   /*!< FLASH Two wait states */
+#define LL_FLASH_LATENCY_3                 FLASH_ACR_LATENCY_3WS   /*!< FLASH Three wait states */
+#define LL_FLASH_LATENCY_4                 FLASH_ACR_LATENCY_4WS   /*!< FLASH Four wait states */
+#define LL_FLASH_LATENCY_5                 FLASH_ACR_LATENCY_5WS   /*!< FLASH five wait state */
+#define LL_FLASH_LATENCY_6                 FLASH_ACR_LATENCY_6WS   /*!< FLASH six wait state */
+#define LL_FLASH_LATENCY_7                 FLASH_ACR_LATENCY_7WS   /*!< FLASH seven wait states */
+#define LL_FLASH_LATENCY_8                 FLASH_ACR_LATENCY_8WS   /*!< FLASH eight wait states */
+#define LL_FLASH_LATENCY_9                 FLASH_ACR_LATENCY_9WS   /*!< FLASH nine wait states */
+#define LL_FLASH_LATENCY_10                FLASH_ACR_LATENCY_10WS   /*!< FLASH ten wait states */
+#define LL_FLASH_LATENCY_11                FLASH_ACR_LATENCY_11WS   /*!< FLASH eleven wait states */
+#define LL_FLASH_LATENCY_12                FLASH_ACR_LATENCY_12WS   /*!< FLASH twelve wait states */
+#define LL_FLASH_LATENCY_13                FLASH_ACR_LATENCY_13WS   /*!< FLASH thirteen wait states */
+#define LL_FLASH_LATENCY_14                FLASH_ACR_LATENCY_14WS   /*!< FLASH fourteen wait states */
+#define LL_FLASH_LATENCY_15                FLASH_ACR_LATENCY_15WS   /*!< FLASH fifteen wait states */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup SYSTEM_LL_Exported_Functions SYSTEM Exported Functions
+  * @{
+  */
+
+/** @defgroup SYSTEM_LL_EF_SYSCFG SYSCFG
+  * @{
+  */
+/**
+  * @brief  Set memory mapping at address 0x00000000
+  * @rmtoll SYSCFG_MEMRMP MEM_MODE      LL_SYSCFG_SetRemapMemory
+  * @param  Memory This parameter can be one of the following values:
+  *         @arg @ref LL_SYSCFG_REMAP_FLASH
+  *         @arg @ref LL_SYSCFG_REMAP_SYSTEMFLASH
+  *         @arg @ref LL_SYSCFG_REMAP_SRAM
+  *         @arg @ref LL_SYSCFG_REMAP_FSMC (*)
+  *         @arg @ref LL_SYSCFG_REMAP_FMC (*)
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_SetRemapMemory(uint32_t Memory)
+{
+  MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, Memory);
+}
+
+/**
+  * @brief  Get memory mapping at address 0x00000000
+  * @rmtoll SYSCFG_MEMRMP MEM_MODE      LL_SYSCFG_GetRemapMemory
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_SYSCFG_REMAP_FLASH
+  *         @arg @ref LL_SYSCFG_REMAP_SYSTEMFLASH
+  *         @arg @ref LL_SYSCFG_REMAP_SRAM
+  *         @arg @ref LL_SYSCFG_REMAP_FSMC (*)
+  *         @arg @ref LL_SYSCFG_REMAP_FMC (*)
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_GetRemapMemory(void)
+{
+  return (uint32_t)(READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE));
+}
+
+#if defined(SYSCFG_MEMRMP_SWP_FMC)
+/**
+  * @brief  Enables the FMC Memory Mapping Swapping
+  * @rmtoll SYSCFG_MEMRMP SWP_FMC      LL_SYSCFG_EnableFMCMemorySwapping
+  * @note   SDRAM is accessible at 0x60000000 and NOR/RAM 
+  *         is accessible at 0xC0000000   
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_EnableFMCMemorySwapping(void)
+{
+  SET_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_SWP_FMC_0);
+}
+
+/**
+  * @brief  Disables the FMC Memory Mapping Swapping
+  * @rmtoll SYSCFG_MEMRMP SWP_FMC      LL_SYSCFG_DisableFMCMemorySwapping
+  * @note   SDRAM is accessible at 0xC0000000 (default mapping)  
+  *         and NOR/RAM is accessible at 0x60000000 (default mapping)
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_DisableFMCMemorySwapping(void)
+{
+  CLEAR_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_SWP_FMC);
+}
+
+#endif /* SYSCFG_MEMRMP_SWP_FMC */
+/**
+  * @brief  Enables the Compensation cell Power Down
+  * @rmtoll SYSCFG_CMPCR CMP_PD      LL_SYSCFG_EnableCompensationCell
+  * @note   The I/O compensation cell can be used only when the device supply
+  *         voltage ranges from 2.4 to 3.6 V
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_EnableCompensationCell(void)
+{
+  SET_BIT(SYSCFG->CMPCR, SYSCFG_CMPCR_CMP_PD);
+}
+
+/**
+  * @brief  Disables the Compensation cell Power Down
+  * @rmtoll SYSCFG_CMPCR CMP_PD      LL_SYSCFG_DisableCompensationCell
+  * @note   The I/O compensation cell can be used only when the device supply
+  *         voltage ranges from 2.4 to 3.6 V
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_DisableCompensationCell(void)
+{
+  CLEAR_BIT(SYSCFG->CMPCR, SYSCFG_CMPCR_CMP_PD);
+}
+
+/**
+  * @brief  Get Compensation Cell ready Flag
+  * @rmtoll SYSCFG_CMPCR READY  LL_SYSCFG_IsActiveFlag_CMPCR
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_CMPCR(void)
+{
+  return (READ_BIT(SYSCFG->CMPCR, SYSCFG_CMPCR_READY) == (SYSCFG_CMPCR_READY));
+}
+
+#if defined(SYSCFG_PMC_MII_RMII_SEL)
+/**
+  * @brief  Select Ethernet PHY interface 
+  * @rmtoll SYSCFG_PMC MII_RMII_SEL       LL_SYSCFG_SetPHYInterface
+  * @param  Interface This parameter can be one of the following values:
+  *         @arg @ref LL_SYSCFG_PMC_ETHMII
+  *         @arg @ref LL_SYSCFG_PMC_ETHRMII
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_SetPHYInterface(uint32_t Interface)
+{
+  MODIFY_REG(SYSCFG->PMC, SYSCFG_PMC_MII_RMII_SEL, Interface);
+}
+
+/**
+  * @brief  Get Ethernet PHY interface 
+  * @rmtoll SYSCFG_PMC MII_RMII_SEL       LL_SYSCFG_GetPHYInterface
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_SYSCFG_PMC_ETHMII
+  *         @arg @ref LL_SYSCFG_PMC_ETHRMII
+  * @retval None
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_GetPHYInterface(void)
+{
+  return (uint32_t)(READ_BIT(SYSCFG->PMC, SYSCFG_PMC_MII_RMII_SEL));
+}
+#endif /* SYSCFG_PMC_MII_RMII_SEL */
+ 
+
+
+#if defined(SYSCFG_MEMRMP_UFB_MODE)
+/**
+  * @brief  Select Flash bank mode (Bank flashed at 0x08000000)
+  * @rmtoll SYSCFG_MEMRMP UFB_MODE       LL_SYSCFG_SetFlashBankMode
+  * @param  Bank This parameter can be one of the following values:
+  *         @arg @ref LL_SYSCFG_BANKMODE_BANK1
+  *         @arg @ref LL_SYSCFG_BANKMODE_BANK2
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_SetFlashBankMode(uint32_t Bank)
+{ 
+  MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_UFB_MODE, Bank);
+}
+
+/**
+  * @brief  Get Flash bank mode (Bank flashed at 0x08000000)
+  * @rmtoll SYSCFG_MEMRMP UFB_MODE       LL_SYSCFG_GetFlashBankMode
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_SYSCFG_BANKMODE_BANK1
+  *         @arg @ref LL_SYSCFG_BANKMODE_BANK2
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_GetFlashBankMode(void)
+{
+  return (uint32_t)(READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_UFB_MODE));
+}
+#endif /* SYSCFG_MEMRMP_UFB_MODE */
+
+#if defined(SYSCFG_CFGR_FMPI2C1_SCL)
+/**
+  * @brief  Enable the I2C fast mode plus driving capability.
+  * @rmtoll SYSCFG_CFGR FMPI2C1_SCL   LL_SYSCFG_EnableFastModePlus\n
+  *         SYSCFG_CFGR FMPI2C1_SDA   LL_SYSCFG_EnableFastModePlus
+  * @param  ConfigFastModePlus This parameter can be a combination of the following values:
+  *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_SCL
+  *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_SDA
+  *         (*) value not defined in all devices
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_EnableFastModePlus(uint32_t ConfigFastModePlus)
+{
+  SET_BIT(SYSCFG->CFGR, ConfigFastModePlus);
+}
+
+/**
+  * @brief  Disable the I2C fast mode plus driving capability.
+  * @rmtoll SYSCFG_CFGR FMPI2C1_SCL  LL_SYSCFG_DisableFastModePlus\n
+  *         SYSCFG_CFGR FMPI2C1_SDA  LL_SYSCFG_DisableFastModePlus\n
+  * @param  ConfigFastModePlus This parameter can be a combination of the following values:
+  *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_SCL
+  *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_SDA
+  *         (*) value not defined in all devices
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_DisableFastModePlus(uint32_t ConfigFastModePlus)
+{
+  CLEAR_BIT(SYSCFG->CFGR, ConfigFastModePlus);
+}
+#endif /* SYSCFG_CFGR_FMPI2C1_SCL */
+
+/**
+  * @brief  Configure source input for the EXTI external interrupt.
+  * @rmtoll SYSCFG_EXTICR1 EXTIx         LL_SYSCFG_SetEXTISource\n
+  *         SYSCFG_EXTICR2 EXTIx         LL_SYSCFG_SetEXTISource\n
+  *         SYSCFG_EXTICR3 EXTIx         LL_SYSCFG_SetEXTISource\n
+  *         SYSCFG_EXTICR4 EXTIx         LL_SYSCFG_SetEXTISource
+  * @param  Port This parameter can be one of the following values:
+  *         @arg @ref LL_SYSCFG_EXTI_PORTA
+  *         @arg @ref LL_SYSCFG_EXTI_PORTB
+  *         @arg @ref LL_SYSCFG_EXTI_PORTC
+  *         @arg @ref LL_SYSCFG_EXTI_PORTD
+  *         @arg @ref LL_SYSCFG_EXTI_PORTE
+  *         @arg @ref LL_SYSCFG_EXTI_PORTF (*)
+  *         @arg @ref LL_SYSCFG_EXTI_PORTG (*)
+  *         @arg @ref LL_SYSCFG_EXTI_PORTH
+  *
+  *         (*) value not defined in all devices
+  * @param  Line This parameter can be one of the following values:
+  *         @arg @ref LL_SYSCFG_EXTI_LINE0
+  *         @arg @ref LL_SYSCFG_EXTI_LINE1
+  *         @arg @ref LL_SYSCFG_EXTI_LINE2
+  *         @arg @ref LL_SYSCFG_EXTI_LINE3
+  *         @arg @ref LL_SYSCFG_EXTI_LINE4
+  *         @arg @ref LL_SYSCFG_EXTI_LINE5
+  *         @arg @ref LL_SYSCFG_EXTI_LINE6
+  *         @arg @ref LL_SYSCFG_EXTI_LINE7
+  *         @arg @ref LL_SYSCFG_EXTI_LINE8
+  *         @arg @ref LL_SYSCFG_EXTI_LINE9
+  *         @arg @ref LL_SYSCFG_EXTI_LINE10
+  *         @arg @ref LL_SYSCFG_EXTI_LINE11
+  *         @arg @ref LL_SYSCFG_EXTI_LINE12
+  *         @arg @ref LL_SYSCFG_EXTI_LINE13
+  *         @arg @ref LL_SYSCFG_EXTI_LINE14
+  *         @arg @ref LL_SYSCFG_EXTI_LINE15
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_SetEXTISource(uint32_t Port, uint32_t Line)
+{
+  MODIFY_REG(SYSCFG->EXTICR[Line & 0xFF], (Line >> 16), Port << POSITION_VAL((Line >> 16)));
+}
+
+/**
+  * @brief  Get the configured defined for specific EXTI Line
+  * @rmtoll SYSCFG_EXTICR1 EXTIx         LL_SYSCFG_GetEXTISource\n
+  *         SYSCFG_EXTICR2 EXTIx         LL_SYSCFG_GetEXTISource\n
+  *         SYSCFG_EXTICR3 EXTIx         LL_SYSCFG_GetEXTISource\n
+  *         SYSCFG_EXTICR4 EXTIx         LL_SYSCFG_GetEXTISource
+  * @param  Line This parameter can be one of the following values:
+  *         @arg @ref LL_SYSCFG_EXTI_LINE0
+  *         @arg @ref LL_SYSCFG_EXTI_LINE1
+  *         @arg @ref LL_SYSCFG_EXTI_LINE2
+  *         @arg @ref LL_SYSCFG_EXTI_LINE3
+  *         @arg @ref LL_SYSCFG_EXTI_LINE4
+  *         @arg @ref LL_SYSCFG_EXTI_LINE5
+  *         @arg @ref LL_SYSCFG_EXTI_LINE6
+  *         @arg @ref LL_SYSCFG_EXTI_LINE7
+  *         @arg @ref LL_SYSCFG_EXTI_LINE8
+  *         @arg @ref LL_SYSCFG_EXTI_LINE9
+  *         @arg @ref LL_SYSCFG_EXTI_LINE10
+  *         @arg @ref LL_SYSCFG_EXTI_LINE11
+  *         @arg @ref LL_SYSCFG_EXTI_LINE12
+  *         @arg @ref LL_SYSCFG_EXTI_LINE13
+  *         @arg @ref LL_SYSCFG_EXTI_LINE14
+  *         @arg @ref LL_SYSCFG_EXTI_LINE15
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_SYSCFG_EXTI_PORTA
+  *         @arg @ref LL_SYSCFG_EXTI_PORTB
+  *         @arg @ref LL_SYSCFG_EXTI_PORTC
+  *         @arg @ref LL_SYSCFG_EXTI_PORTD
+  *         @arg @ref LL_SYSCFG_EXTI_PORTE
+  *         @arg @ref LL_SYSCFG_EXTI_PORTF (*)
+  *         @arg @ref LL_SYSCFG_EXTI_PORTG (*)
+  *         @arg @ref LL_SYSCFG_EXTI_PORTH
+  *         (*) value not defined in all devices
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_GetEXTISource(uint32_t Line)
+{
+  return (uint32_t)(READ_BIT(SYSCFG->EXTICR[Line & 0xFF], (Line >> 16)) >> POSITION_VAL(Line >> 16));
+}
+
+#if defined(SYSCFG_CFGR2_LOCKUP_LOCK)
+/**
+  * @brief  Set connections to TIM1/8 break inputs
+  * @rmtoll SYSCFG_CFGR2 LockUp Lock           LL_SYSCFG_SetTIMBreakInputs \n
+  *         SYSCFG_CFGR2 PVD Lock              LL_SYSCFG_SetTIMBreakInputs
+  * @param  Break This parameter can be a combination of the following values:
+  *         @arg @ref LL_SYSCFG_TIMBREAK_LOCKUP
+  *         @arg @ref LL_SYSCFG_TIMBREAK_PVD
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_SetTIMBreakInputs(uint32_t Break)
+{
+  MODIFY_REG(SYSCFG->CFGR2, SYSCFG_CFGR2_LOCKUP_LOCK | SYSCFG_CFGR2_PVD_LOCK, Break);
+}
+
+/**
+  * @brief  Get connections to TIM1/8 Break inputs
+  * @rmtoll SYSCFG_CFGR2 LockUp Lock           LL_SYSCFG_SetTIMBreakInputs \n
+  *         SYSCFG_CFGR2 PVD Lock              LL_SYSCFG_SetTIMBreakInputs
+  * @retval Returned value can be can be a combination of the following values:
+  *         @arg @ref LL_SYSCFG_TIMBREAK_LOCKUP
+  *         @arg @ref LL_SYSCFG_TIMBREAK_PVD
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_GetTIMBreakInputs(void)
+{   
+  return (uint32_t)(READ_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_LOCKUP_LOCK | SYSCFG_CFGR2_PVD_LOCK));
+}
+#endif /* SYSCFG_CFGR2_LOCKUP_LOCK */
+#if defined(SYSCFG_MCHDLYCR_BSCKSEL)
+/**
+  * @brief  Select the DFSDM2 or TIM2_OC1 as clock source for the bitstream clock.
+  * @rmtoll SYSCFG_MCHDLYCR BSCKSEL        LL_SYSCFG_DFSDM_SetBitstreamClockSourceSelection
+  * @param  ClockSource This parameter can be one of the following values:
+  *         @arg @ref LL_SYSCFG_BITSTREAM_CLOCK_DFSDM2
+  *         @arg @ref LL_SYSCFG_BITSTREAM_CLOCK_TIM2OC1
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_DFSDM_SetBitstreamClockSourceSelection(uint32_t ClockSource)
+{
+  MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_BSCKSEL, ClockSource);
+}
+/**
+  * @brief  Get the DFSDM2 or TIM2_OC1 as clock source for the bitstream clock.
+  * @rmtoll SYSCFG_MCHDLYCR BSCKSEL       LL_SYSCFG_DFSDM_GetBitstreamClockSourceSelection
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_SYSCFG_BITSTREAM_CLOCK_DFSDM2
+  *         @arg @ref LL_SYSCFG_BITSTREAM_CLOCK_TIM2OC1
+  * @retval None
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM_GetBitstreamClockSourceSelection(void)
+{
+  return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_BSCKSEL));
+}
+/**
+  * @brief  Enables the DFSDM1 or DFSDM2 Delay clock
+  * @rmtoll SYSCFG_MCHDLYCR MCHDLYEN      LL_SYSCFG_DFSDM_EnableDelayClock
+  * @param MCHDLY This parameter can be one of the following values
+  *         @arg @ref LL_SYSCFG_DFSDM1_MCHDLYEN
+  *         @arg @ref LL_SYSCFG_DFSDM2_MCHDLYEN
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_DFSDM_EnableDelayClock(uint32_t MCHDLY)
+{
+  SET_BIT(SYSCFG->MCHDLYCR, MCHDLY);
+}
+
+/**
+  * @brief  Disables the DFSDM1 or the DFSDM2 Delay clock
+  * @rmtoll SYSCFG_MCHDLYCR MCHDLY1EN      LL_SYSCFG_DFSDM1_DisableDelayClock
+  * @param MCHDLY This parameter can be one of the following values
+  *         @arg @ref LL_SYSCFG_DFSDM1_MCHDLYEN
+  *         @arg @ref LL_SYSCFG_DFSDM2_MCHDLYEN
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_DFSDM_DisableDelayClock(uint32_t MCHDLY)
+{
+  CLEAR_BIT(SYSCFG->MCHDLYCR, MCHDLY);
+}
+
+/**
+  * @brief  Select the source for DFSDM1 or DFSDM2 DatIn0 
+  * @rmtoll SYSCFG_MCHDLYCR DFSDMD0SEL        LL_SYSCFG_DFSDM_SetDataIn0Source
+  * @param  Source This parameter can be one of the following values:
+  *         @arg @ref LL_SYSCFG_DFSDM1_DataIn0_PAD
+  *         @arg @ref LL_SYSCFG_DFSDM1_DataIn0_DM
+  *         @arg @ref LL_SYSCFG_DFSDM2_DataIn0_PAD
+  *         @arg @ref LL_SYSCFG_DFSDM2_DataIn0_DM
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_DFSDM_SetDataIn0Source(uint32_t Source)
+{
+  MODIFY_REG(SYSCFG->MCHDLYCR, (Source >> 16), (Source & 0x0000FFFF));
+}
+/**
+  * @brief  Get the source for DFSDM1 or DFSDM2 DatIn0.
+  * @rmtoll SYSCFG_MCHDLYCR DFSDMD0SEL       LL_SYSCFG_DFSDM_GetDataIn0Source
+  * @param  Source This parameter can be one of the following values:
+  *         @arg @ref LL_SYSCFG_DFSDM1_DataIn0
+  *         @arg @ref LL_SYSCFG_DFSDM2_DataIn0
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_SYSCFG_DFSDM1_DataIn0_PAD
+  *         @arg @ref LL_SYSCFG_DFSDM1_DataIn0_DM
+  *         @arg @ref LL_SYSCFG_DFSDM2_DataIn0_PAD
+  *         @arg @ref LL_SYSCFG_DFSDM2_DataIn0_DM
+  * @retval None
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM_GetDataIn0Source(uint32_t Source)
+{
+  return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, Source));
+}
+/**
+  * @brief  Select the source for DFSDM1 or DFSDM2 DatIn2 
+  * @rmtoll SYSCFG_MCHDLYCR DFSDMD2SEL        LL_SYSCFG_DFSDM_SetDataIn2Source
+  * @param  Source This parameter can be one of the following values:
+  *         @arg @ref LL_SYSCFG_DFSDM1_DataIn2_PAD
+  *         @arg @ref LL_SYSCFG_DFSDM1_DataIn2_DM
+  *         @arg @ref LL_SYSCFG_DFSDM2_DataIn2_PAD
+  *         @arg @ref LL_SYSCFG_DFSDM2_DataIn2_DM
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_DFSDM_SetDataIn2Source(uint32_t Source)
+{
+  MODIFY_REG(SYSCFG->MCHDLYCR, (Source >> 16), (Source & 0x0000FFFF));
+}
+/**
+  * @brief  Get the source for DFSDM1 or DFSDM2 DatIn2.
+  * @rmtoll SYSCFG_MCHDLYCR DFSDMD2SEL       LL_SYSCFG_DFSDM_GetDataIn2Source
+  * @param  Source This parameter can be one of the following values:
+  *         @arg @ref LL_SYSCFG_DFSDM1_DataIn2
+  *         @arg @ref LL_SYSCFG_DFSDM2_DataIn2
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_SYSCFG_DFSDM1_DataIn2_PAD
+  *         @arg @ref LL_SYSCFG_DFSDM1_DataIn2_DM
+  *         @arg @ref LL_SYSCFG_DFSDM2_DataIn2_PAD
+  *         @arg @ref LL_SYSCFG_DFSDM2_DataIn2_DM
+  * @retval None
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM_GetDataIn2Source(uint32_t Source)
+{
+  return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, Source));
+}
+
+/**
+  * @brief  Select the distribution of the bitsream lock gated by TIM4 OC2 
+  * @rmtoll SYSCFG_MCHDLYCR DFSDM1CK02SEL        LL_SYSCFG_DFSDM1_SetTIM4OC2BitStreamDistribution
+  * @param  Source This parameter can be one of the following values:
+  *         @arg @ref LL_SYSCFG_DFSDM1_TIM4OC2_CLKIN0
+  *         @arg @ref LL_SYSCFG_DFSDM1_TIM4OC2_CLKIN2
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_DFSDM1_SetTIM4OC2BitStreamDistribution(uint32_t Source)
+{
+  MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM1CK02SEL, Source);
+}
+/**
+  * @brief  Get the distribution of the bitsream lock gated by TIM4 OC2 
+  * @rmtoll SYSCFG_MCHDLYCR DFSDM1D2SEL       LL_SYSCFG_DFSDM1_GetTIM4OC2BitStreamDistribution
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_SYSCFG_DFSDM1_TIM4OC2_CLKIN0
+  *         @arg @ref LL_SYSCFG_DFSDM1_TIM4OC2_CLKIN2
+  * @retval None
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM1_GetTIM4OC2BitStreamDistribution(void)
+{
+  return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM1CK02SEL));
+}
+
+/**
+  * @brief  Select the distribution of the bitsream lock gated by TIM4 OC1 
+  * @rmtoll SYSCFG_MCHDLYCR DFSDM1CK13SEL        LL_SYSCFG_DFSDM1_SetTIM4OC1BitStreamDistribution
+  * @param  Source This parameter can be one of the following values:
+  *         @arg @ref LL_SYSCFG_DFSDM1_TIM4OC1_CLKIN1
+  *         @arg @ref LL_SYSCFG_DFSDM1_TIM4OC1_CLKIN3
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_DFSDM1_SetTIM4OC1BitStreamDistribution(uint32_t Source)
+{
+  MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM1CK13SEL, Source);
+}
+/**
+  * @brief  Get the distribution of the bitsream lock gated by TIM4 OC1 
+  * @rmtoll SYSCFG_MCHDLYCR DFSDM1D2SEL       LL_SYSCFG_DFSDM1_GetTIM4OC1BitStreamDistribution
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_SYSCFG_DFSDM1_TIM4OC1_CLKIN1
+  *         @arg @ref LL_SYSCFG_DFSDM1_TIM4OC1_CLKIN3
+  * @retval None
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM1_GetTIM4OC1BitStreamDistribution(void)
+{
+  return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM1CK13SEL));
+}
+
+/**
+  * @brief  Select the DFSDM1 Clock In 
+  * @rmtoll SYSCFG_MCHDLYCR DFSDM1CFG        LL_SYSCFG_DFSDM1_SetClockInSourceSelection
+  * @param  ClockSource This parameter can be one of the following values:
+  *         @arg @ref LL_SYSCFG_DFSDM1_CKIN_PAD
+  *         @arg @ref LL_SYSCFG_DFSDM1_CKIN_DM
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_DFSDM1_SetClockInSourceSelection(uint32_t ClockSource)
+{
+  MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM1CFG, ClockSource);
+}
+/**
+  * @brief  GET the DFSDM1 Clock In
+  * @rmtoll SYSCFG_MCHDLYCR DFSDM1CFG       LL_SYSCFG_DFSDM1_GetClockInSourceSelection
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_SYSCFG_DFSDM1_CKIN_PAD
+  *         @arg @ref LL_SYSCFG_DFSDM1_CKIN_DM
+  * @retval None
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM1_GetClockInSourceSelection(void)
+{
+  return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM1CFG));
+}
+
+/**
+  * @brief  Select the DFSDM1 Clock Out 
+  * @rmtoll SYSCFG_MCHDLYCR DFSDM1CKOSEL        LL_SYSCFG_DFSDM1_SetClockOutSourceSelection
+  * @param  ClockSource This parameter can be one of the following values:
+  *         @arg @ref LL_SYSCFG_DFSDM1_CKOUT
+  *         @arg @ref LL_SYSCFG_DFSDM1_CKOUT_M27
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_DFSDM1_SetClockOutSourceSelection(uint32_t ClockSource)
+{
+  MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM1CKOSEL, ClockSource);
+}
+/**
+  * @brief  GET the DFSDM1 Clock Out
+  * @rmtoll SYSCFG_MCHDLYCR DFSDM1CKOSEL       LL_SYSCFG_DFSDM1_GetClockOutSourceSelection
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_SYSCFG_DFSDM1_CKOUT
+  *         @arg @ref LL_SYSCFG_DFSDM1_CKOUT_M27
+  * @retval None
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM1_GetClockOutSourceSelection(void)
+{
+  return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM1CKOSEL));
+}
+
+/**
+  * @brief  Enables the DFSDM2 Delay clock
+  * @rmtoll SYSCFG_MCHDLYCR MCHDLY2EN      LL_SYSCFG_DFSDM2_EnableDelayClock
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_DFSDM2_EnableDelayClock(void)
+{
+  SET_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_MCHDLY2EN);
+}
+
+/**
+  * @brief  Disables the DFSDM2 Delay clock
+  * @rmtoll SYSCFG_MCHDLYCR MCHDLY2EN      LL_SYSCFG_DFSDM2_DisableDelayClock
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_DFSDM2_DisableDelayClock(void)
+{
+  CLEAR_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_MCHDLY2EN);
+}
+/**
+  * @brief  Select the source for DFSDM2 DatIn0 
+  * @rmtoll SYSCFG_MCHDLYCR DFSDM2D0SEL        LL_SYSCFG_DFSDM2_SetDataIn0Source
+  * @param  Source This parameter can be one of the following values:
+  *         @arg @ref LL_SYSCFG_DFSDM2_DataIn0_PAD
+  *         @arg @ref LL_SYSCFG_DFSDM2_DataIn0_DM
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_DFSDM2_SetDataIn0Source(uint32_t Source)
+{
+  MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2D0SEL, Source);
+}
+/**
+  * @brief  Get the source for DFSDM2 DatIn0.
+  * @rmtoll SYSCFG_MCHDLYCR DFSDM2D0SEL       LL_SYSCFG_DFSDM2_GetDataIn0Source
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_SYSCFG_DFSDM2_DataIn0_PAD
+  *         @arg @ref LL_SYSCFG_DFSDM2_DataIn0_DM
+  * @retval None
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM2_GetDataIn0Source(void)
+{
+  return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2D0SEL));
+}
+
+/**
+  * @brief  Select the source for DFSDM2 DatIn2 
+  * @rmtoll SYSCFG_MCHDLYCR DFSDM2D2SEL        LL_SYSCFG_DFSDM2_SetDataIn2Source
+  * @param  Source This parameter can be one of the following values:
+  *         @arg @ref LL_SYSCFG_DFSDM2_DataIn2_PAD
+  *         @arg @ref LL_SYSCFG_DFSDM2_DataIn2_DM
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_DFSDM2_SetDataIn2Source(uint32_t Source)
+{
+  MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2D2SEL, Source);
+}
+/**
+  * @brief  Get the source for DFSDM2 DatIn2.
+  * @rmtoll SYSCFG_MCHDLYCR DFSDM2D2SEL       LL_SYSCFG_DFSDM2_GetDataIn2Source
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_SYSCFG_DFSDM2_DataIn2_PAD
+  *         @arg @ref LL_SYSCFG_DFSDM2_DataIn2_DM
+  * @retval None
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM2_GetDataIn2Source(void)
+{
+  return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2D2SEL));
+}
+
+/**
+  * @brief  Select the source for DFSDM2 DatIn4 
+  * @rmtoll SYSCFG_MCHDLYCR DFSDM2D4SEL        LL_SYSCFG_DFSDM2_SetDataIn4Source
+  * @param  Source This parameter can be one of the following values:
+  *         @arg @ref LL_SYSCFG_DFSDM2_DataIn4_PAD
+  *         @arg @ref LL_SYSCFG_DFSDM2_DataIn4_DM
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_DFSDM2_SetDataIn4Source(uint32_t Source)
+{
+  MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2D4SEL, Source);
+}
+/**
+  * @brief  Get the source for DFSDM2 DatIn4.
+  * @rmtoll SYSCFG_MCHDLYCR DFSDM2D4SEL       LL_SYSCFG_DFSDM2_GetDataIn4Source
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_SYSCFG_DFSDM2_DataIn4_PAD
+  *         @arg @ref LL_SYSCFG_DFSDM2_DataIn4_DM
+  * @retval None
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM2_GetDataIn4Source(void)
+{
+  return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2D4SEL));
+}
+
+/**
+  * @brief  Select the source for DFSDM2 DatIn6 
+  * @rmtoll SYSCFG_MCHDLYCR DFSDM2D6SEL        LL_SYSCFG_DFSDM2_SetDataIn6Source
+  * @param  Source This parameter can be one of the following values:
+  *         @arg @ref LL_SYSCFG_DFSDM2_DataIn6_PAD
+  *         @arg @ref LL_SYSCFG_DFSDM2_DataIn6_DM
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_DFSDM2_SetDataIn6Source(uint32_t Source)
+{
+  MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2D6SEL, Source);
+}
+/**
+  * @brief  Get the source for DFSDM2 DatIn6.
+  * @rmtoll SYSCFG_MCHDLYCR DFSDM2D6SEL       LL_SYSCFG_DFSDM2_GetDataIn6Source
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_SYSCFG_DFSDM2_DataIn6_PAD
+  *         @arg @ref LL_SYSCFG_DFSDM2_DataIn6_DM
+  * @retval None
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM2_GetDataIn6Source(void)
+{
+  return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2D6SEL));
+}
+
+/**
+  * @brief  Select the distribution of the bitsream lock gated by TIM3 OC4 
+  * @rmtoll SYSCFG_MCHDLYCR DFSDM2CK04SEL        LL_SYSCFG_DFSDM2_SetTIM3OC4BitStreamDistribution
+  * @param  Source This parameter can be one of the following values:
+  *         @arg @ref LL_SYSCFG_DFSDM2_TIM3OC4_CLKIN0
+  *         @arg @ref LL_SYSCFG_DFSDM2_TIM3OC4_CLKIN4
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_DFSDM2_SetTIM3OC4BitStreamDistribution(uint32_t Source)
+{
+  MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2CK04SEL, Source);
+}
+/**
+  * @brief  Get the distribution of the bitsream lock gated by TIM3 OC4 
+  * @rmtoll SYSCFG_MCHDLYCR DFSDM2CK04SEL       LL_SYSCFG_DFSDM2_GetTIM3OC4BitStreamDistribution
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_SYSCFG_DFSDM2_TIM3OC4_CLKIN0
+  *         @arg @ref LL_SYSCFG_DFSDM2_TIM3OC4_CLKIN4
+  * @retval None
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM2_GetTIM3OC4BitStreamDistribution(void)
+{
+  return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2CK04SEL));
+}
+
+/**
+  * @brief  Select the distribution of the bitsream lock gated by TIM3 OC3 
+  * @rmtoll SYSCFG_MCHDLYCR DFSDM2CK15SEL        LL_SYSCFG_DFSDM2_SetTIM3OC3BitStreamDistribution
+  * @param  Source This parameter can be one of the following values:
+  *         @arg @ref LL_SYSCFG_DFSDM2_TIM3OC3_CLKIN1
+  *         @arg @ref LL_SYSCFG_DFSDM2_TIM3OC3_CLKIN5
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_DFSDM2_SetTIM3OC3BitStreamDistribution(uint32_t Source)
+{
+  MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2CK15SEL, Source);
+}
+/**
+  * @brief  Get the distribution of the bitsream lock gated by TIM3 OC4 
+  * @rmtoll SYSCFG_MCHDLYCR DFSDM2CK04SEL       LL_SYSCFG_DFSDM2_GetTIM3OC3BitStreamDistribution
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_SYSCFG_DFSDM2_TIM3OC3_CLKIN1
+  *         @arg @ref LL_SYSCFG_DFSDM2_TIM3OC3_CLKIN5
+  * @retval None
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM2_GetTIM3OC3BitStreamDistribution(void)
+{
+  return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2CK15SEL));
+}
+
+/**
+  * @brief  Select the distribution of the bitsream lock gated by TIM3 OC2 
+  * @rmtoll SYSCFG_MCHDLYCR DFSDM2CK26SEL        LL_SYSCFG_DFSDM2_SetTIM3OC2BitStreamDistribution
+  * @param  Source This parameter can be one of the following values:
+  *         @arg @ref LL_SYSCFG_DFSDM2_TIM3OC2_CLKIN2
+  *         @arg @ref LL_SYSCFG_DFSDM2_TIM3OC2_CLKIN6
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_DFSDM2_SetTIM3OC2BitStreamDistribution(uint32_t Source)
+{
+  MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2CK26SEL, Source);
+}
+/**
+  * @brief  Get the distribution of the bitsream lock gated by TIM3 OC2 
+  * @rmtoll SYSCFG_MCHDLYCR DFSDM2CK04SEL       LL_SYSCFG_DFSDM2_GetTIM3OC2BitStreamDistribution
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_SYSCFG_DFSDM2_TIM3OC2_CLKIN2
+  *         @arg @ref LL_SYSCFG_DFSDM2_TIM3OC2_CLKIN6
+  * @retval None
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM2_GetTIM3OC2BitStreamDistribution(void)
+{
+  return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2CK26SEL));
+}
+
+/**
+  * @brief  Select the distribution of the bitsream lock gated by TIM3 OC1 
+  * @rmtoll SYSCFG_MCHDLYCR DFSDM2CK37SEL        LL_SYSCFG_DFSDM2_SetTIM3OC1BitStreamDistribution
+  * @param  Source This parameter can be one of the following values:
+  *         @arg @ref LL_SYSCFG_DFSDM2_TIM3OC1_CLKIN3
+  *         @arg @ref LL_SYSCFG_DFSDM2_TIM3OC1_CLKIN7
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_DFSDM2_SetTIM3OC1BitStreamDistribution(uint32_t Source)
+{
+  MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2CK37SEL, Source);
+}
+/**
+  * @brief  Get the distribution of the bitsream lock gated by TIM3 OC1 
+  * @rmtoll SYSCFG_MCHDLYCR DFSDM2CK37SEL       LL_SYSCFG_DFSDM2_GetTIM3OC1BitStreamDistribution
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_SYSCFG_DFSDM2_TIM3OC1_CLKIN3
+  *         @arg @ref LL_SYSCFG_DFSDM2_TIM3OC1_CLKIN7
+  * @retval None
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM2_GetTIM3OC1BitStreamDistribution(void)
+{
+  return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2CK37SEL));
+}
+
+/**
+  * @brief  Select the DFSDM2 Clock In 
+  * @rmtoll SYSCFG_MCHDLYCR DFSDM2CFG        LL_SYSCFG_DFSDM2_SetClockInSourceSelection
+  * @param  ClockSource This parameter can be one of the following values:
+  *         @arg @ref LL_SYSCFG_DFSDM2_CKIN_PAD
+  *         @arg @ref LL_SYSCFG_DFSDM2_CKIN_DM
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_DFSDM2_SetClockInSourceSelection(uint32_t ClockSource)
+{
+  MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2CFG, ClockSource);
+}
+/**
+  * @brief  GET the DFSDM2 Clock In
+  * @rmtoll SYSCFG_MCHDLYCR DFSDM2CFG       LL_SYSCFG_DFSDM2_GetClockInSourceSelection
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_SYSCFG_DFSDM2_CKIN_PAD
+  *         @arg @ref LL_SYSCFG_DFSDM2_CKIN_DM
+  * @retval None
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM2_GetClockInSourceSelection(void)
+{
+  return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2CFG));
+}
+
+/**
+  * @brief  Select the DFSDM2 Clock Out 
+  * @rmtoll SYSCFG_MCHDLYCR DFSDM2CKOSEL        LL_SYSCFG_DFSDM2_SetClockOutSourceSelection
+  * @param  ClockSource This parameter can be one of the following values:
+  *         @arg @ref LL_SYSCFG_DFSDM2_CKOUT
+  *         @arg @ref LL_SYSCFG_DFSDM2_CKOUT_M27
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_DFSDM2_SetClockOutSourceSelection(uint32_t ClockSource)
+{
+  MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2CKOSEL, ClockSource);
+}
+/**
+  * @brief  GET the DFSDM2 Clock Out
+  * @rmtoll SYSCFG_MCHDLYCR DFSDM2CKOSEL       LL_SYSCFG_DFSDM2_GetClockOutSourceSelection
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_SYSCFG_DFSDM2_CKOUT
+  *         @arg @ref LL_SYSCFG_DFSDM2_CKOUT_M27
+  * @retval None
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM2_GetClockOutSourceSelection(void)
+{
+  return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2CKOSEL));
+}
+
+#endif /* SYSCFG_MCHDLYCR_BSCKSEL */
+/**
+  * @}
+  */
+
+
+/** @defgroup SYSTEM_LL_EF_DBGMCU DBGMCU
+  * @{
+  */
+
+/**
+  * @brief  Return the device identifier
+  * @note For STM32F405/407xx and STM32F415/417xx devices, the device ID is 0x413
+  * @note For STM32F42xxx and STM32F43xxx devices, the device ID is 0x419
+  * @note For STM32F401xx devices, the device ID is 0x423
+  * @note For STM32F401xx devices, the device ID is 0x433
+  * @note For STM32F411xx devices, the device ID is 0x431
+  * @note For STM32F410xx devices, the device ID is 0x458
+  * @note For STM32F412xx devices, the device ID is 0x441
+  * @note For STM32F413xx and STM32423xx devices, the device ID is 0x463
+  * @note For STM32F446xx devices, the device ID is 0x421
+  * @note For STM32F469xx and STM32F479xx devices, the device ID is 0x434
+  * @rmtoll DBGMCU_IDCODE DEV_ID        LL_DBGMCU_GetDeviceID
+  * @retval Values between Min_Data=0x00 and Max_Data=0xFFF
+  */
+__STATIC_INLINE uint32_t LL_DBGMCU_GetDeviceID(void)
+{
+  return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_DEV_ID));
+}
+
+/**
+  * @brief  Return the device revision identifier
+  * @note This field indicates the revision of the device.
+          For example, it is read as RevA -> 0x1000, Cat 2 revZ -> 0x1001, rev1 -> 0x1003, rev2 ->0x1007, revY -> 0x100F for STM32F405/407xx and STM32F415/417xx devices
+          For example, it is read as RevA -> 0x1000, Cat 2 revY -> 0x1003, rev1 -> 0x1007, rev3 ->0x2001 for STM32F42xxx and STM32F43xxx devices
+          For example, it is read as RevZ -> 0x1000, Cat 2 revA -> 0x1001 for STM32F401xB/C devices
+          For example, it is read as RevA -> 0x1000, Cat 2 revZ -> 0x1001 for STM32F401xD/E devices
+          For example, it is read as RevA -> 0x1000 for STM32F411xx,STM32F413/423xx,STM32F469/423xx, STM32F446xx and STM32F410xx devices
+          For example, it is read as RevZ -> 0x1001, Cat 2 revB -> 0x2000, revC -> 0x3000 for STM32F412xx devices
+  * @rmtoll DBGMCU_IDCODE REV_ID        LL_DBGMCU_GetRevisionID
+  * @retval Values between Min_Data=0x00 and Max_Data=0xFFFF
+  */
+__STATIC_INLINE uint32_t LL_DBGMCU_GetRevisionID(void)
+{
+  return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_REV_ID) >> DBGMCU_IDCODE_REV_ID_Pos);
+}
+
+/**
+  * @brief  Enable the Debug Module during SLEEP mode
+  * @rmtoll DBGMCU_CR    DBG_SLEEP     LL_DBGMCU_EnableDBGSleepMode
+  * @retval None
+  */
+__STATIC_INLINE void LL_DBGMCU_EnableDBGSleepMode(void)
+{
+  SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
+}
+
+/**
+  * @brief  Disable the Debug Module during SLEEP mode
+  * @rmtoll DBGMCU_CR    DBG_SLEEP     LL_DBGMCU_DisableDBGSleepMode
+  * @retval None
+  */
+__STATIC_INLINE void LL_DBGMCU_DisableDBGSleepMode(void)
+{
+  CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
+}
+
+/**
+  * @brief  Enable the Debug Module during STOP mode
+  * @rmtoll DBGMCU_CR    DBG_STOP      LL_DBGMCU_EnableDBGStopMode
+  * @retval None
+  */
+__STATIC_INLINE void LL_DBGMCU_EnableDBGStopMode(void)
+{
+  SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
+}
+
+/**
+  * @brief  Disable the Debug Module during STOP mode
+  * @rmtoll DBGMCU_CR    DBG_STOP      LL_DBGMCU_DisableDBGStopMode
+  * @retval None
+  */
+__STATIC_INLINE void LL_DBGMCU_DisableDBGStopMode(void)
+{
+  CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
+}
+
+/**
+  * @brief  Enable the Debug Module during STANDBY mode
+  * @rmtoll DBGMCU_CR    DBG_STANDBY   LL_DBGMCU_EnableDBGStandbyMode
+  * @retval None
+  */
+__STATIC_INLINE void LL_DBGMCU_EnableDBGStandbyMode(void)
+{
+  SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
+}
+
+/**
+  * @brief  Disable the Debug Module during STANDBY mode
+  * @rmtoll DBGMCU_CR    DBG_STANDBY   LL_DBGMCU_DisableDBGStandbyMode
+  * @retval None
+  */
+__STATIC_INLINE void LL_DBGMCU_DisableDBGStandbyMode(void)
+{
+  CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
+}
+
+/**
+  * @brief  Set Trace pin assignment control
+  * @rmtoll DBGMCU_CR    TRACE_IOEN    LL_DBGMCU_SetTracePinAssignment\n
+  *         DBGMCU_CR    TRACE_MODE    LL_DBGMCU_SetTracePinAssignment
+  * @param  PinAssignment This parameter can be one of the following values:
+  *         @arg @ref LL_DBGMCU_TRACE_NONE
+  *         @arg @ref LL_DBGMCU_TRACE_ASYNCH
+  *         @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE1
+  *         @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE2
+  *         @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE4
+  * @retval None
+  */
+__STATIC_INLINE void LL_DBGMCU_SetTracePinAssignment(uint32_t PinAssignment)
+{
+  MODIFY_REG(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE, PinAssignment);
+}
+
+/**
+  * @brief  Get Trace pin assignment control
+  * @rmtoll DBGMCU_CR    TRACE_IOEN    LL_DBGMCU_GetTracePinAssignment\n
+  *         DBGMCU_CR    TRACE_MODE    LL_DBGMCU_GetTracePinAssignment
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DBGMCU_TRACE_NONE
+  *         @arg @ref LL_DBGMCU_TRACE_ASYNCH
+  *         @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE1
+  *         @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE2
+  *         @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE4
+  */
+__STATIC_INLINE uint32_t LL_DBGMCU_GetTracePinAssignment(void)
+{
+  return (uint32_t)(READ_BIT(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE));
+}
+
+/**
+  * @brief  Freeze APB1 peripherals (group1 peripherals)
+  * @rmtoll DBGMCU_APB1_FZ      DBG_TIM2_STOP           LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+  *         DBGMCU_APB1_FZ      DBG_TIM3_STOP           LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+  *         DBGMCU_APB1_FZ      DBG_TIM4_STOP           LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+  *         DBGMCU_APB1_FZ      DBG_TIM5_STOP           LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+  *         DBGMCU_APB1_FZ      DBG_TIM6_STOP           LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+  *         DBGMCU_APB1_FZ      DBG_TIM7_STOP           LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+  *         DBGMCU_APB1_FZ      DBG_TIM12_STOP          LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+  *         DBGMCU_APB1_FZ      DBG_TIM13_STOP          LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+  *         DBGMCU_APB1_FZ      DBG_TIM14_STOP          LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+  *         DBGMCU_APB1_FZ      DBG_LPTIM_STOP          LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+  *         DBGMCU_APB1_FZ      DBG_RTC_STOP            LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+  *         DBGMCU_APB1_FZ      DBG_WWDG_STOP           LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+  *         DBGMCU_APB1_FZ      DBG_IWDG_STOP           LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+  *         DBGMCU_APB1_FZ      DBG_I2C1_SMBUS_TIMEOUT  LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+  *         DBGMCU_APB1_FZ      DBG_I2C2_SMBUS_TIMEOUT  LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+  *         DBGMCU_APB1_FZ      DBG_I2C3_SMBUS_TIMEOUT  LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+  *         DBGMCU_APB1_FZ      DBG_I2C4_SMBUS_TIMEOUT  LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+  *         DBGMCU_APB1_FZ      DBG_CAN1_STOP           LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+  *         DBGMCU_APB1_FZ      DBG_CAN2_STOP           LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+  *         DBGMCU_APB1_FZ      DBG_CAN3_STOP           LL_DBGMCU_APB1_GRP1_FreezePeriph
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP (*)
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP (*)
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP (*)
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP 
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP (*)
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP (*)
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM12_STOP (*)
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM13_STOP (*)
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM14_STOP (*)
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_LPTIM_STOP (*)
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_I2C3_STOP (*)
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_I2C4_STOP (*)
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_CAN1_STOP (*)
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_CAN2_STOP (*)
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_CAN3_STOP (*)
+  *         
+  *         (*) value not defined in all devices.
+  * @retval None
+  */
+__STATIC_INLINE void LL_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs)
+{
+  SET_BIT(DBGMCU->APB1FZ, Periphs);
+}
+
+/**
+  * @brief  Unfreeze APB1 peripherals (group1 peripherals)
+  * @rmtoll DBGMCU_APB1_FZ      DBG_TIM2_STOP           LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
+  *         DBGMCU_APB1_FZ      DBG_TIM3_STOP           LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
+  *         DBGMCU_APB1_FZ      DBG_TIM4_STOP           LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
+  *         DBGMCU_APB1_FZ      DBG_TIM5_STOP           LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
+  *         DBGMCU_APB1_FZ      DBG_TIM6_STOP           LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
+  *         DBGMCU_APB1_FZ      DBG_TIM7_STOP           LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
+  *         DBGMCU_APB1_FZ      DBG_TIM12_STOP          LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
+  *         DBGMCU_APB1_FZ      DBG_TIM13_STOP          LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
+  *         DBGMCU_APB1_FZ      DBG_TIM14_STOP          LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
+  *         DBGMCU_APB1_FZ      DBG_LPTIM_STOP         LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
+  *         DBGMCU_APB1_FZ      DBG_RTC_STOP            LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
+  *         DBGMCU_APB1_FZ      DBG_WWDG_STOP           LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
+  *         DBGMCU_APB1_FZ      DBG_IWDG_STOP           LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
+  *         DBGMCU_APB1_FZ      DBG_I2C1_SMBUS_TIMEOUT  LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
+  *         DBGMCU_APB1_FZ      DBG_I2C2_SMBUS_TIMEOUT  LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
+  *         DBGMCU_APB1_FZ      DBG_I2C3_SMBUS_TIMEOUT  LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
+  *         DBGMCU_APB1_FZ      DBG_I2C4_SMBUS_TIMEOUT  LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
+  *         DBGMCU_APB1_FZ      DBG_CAN1_STOP           LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
+  *         DBGMCU_APB1_FZ      DBG_CAN2_STOP           LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
+  *         DBGMCU_APB1_FZ      DBG_CAN3_STOP           LL_DBGMCU_APB1_GRP1_UnFreezePeriph
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP (*)
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP (*)
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP (*)
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP 
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP (*)
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP (*)
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM12_STOP (*)
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM13_STOP (*)
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM14_STOP (*)
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_LPTIM_STOP (*)
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_I2C3_STOP (*)
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_I2C4_STOP (*)
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_CAN1_STOP (*)
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_CAN2_STOP (*)
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_CAN3_STOP (*)
+  *         
+  *         (*) value not defined in all devices.
+  * @retval None
+  */
+__STATIC_INLINE void LL_DBGMCU_APB1_GRP1_UnFreezePeriph(uint32_t Periphs)
+{
+  CLEAR_BIT(DBGMCU->APB1FZ, Periphs);
+}
+
+/**
+  * @brief  Freeze APB2 peripherals
+  * @rmtoll DBGMCU_APB2_FZ      DBG_TIM1_STOP    LL_DBGMCU_APB2_GRP1_FreezePeriph\n
+  *         DBGMCU_APB2_FZ      DBG_TIM8_STOP    LL_DBGMCU_APB2_GRP1_FreezePeriph\n
+  *         DBGMCU_APB2_FZ      DBG_TIM9_STOP    LL_DBGMCU_APB2_GRP1_FreezePeriph\n
+  *         DBGMCU_APB2_FZ      DBG_TIM10_STOP   LL_DBGMCU_APB2_GRP1_FreezePeriph\n
+  *         DBGMCU_APB2_FZ      DBG_TIM11_STOP   LL_DBGMCU_APB2_GRP1_FreezePeriph
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP
+  *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP (*)
+  *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM9_STOP (*)
+  *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM10_STOP (*)
+  *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM11_STOP (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+  */
+__STATIC_INLINE void LL_DBGMCU_APB2_GRP1_FreezePeriph(uint32_t Periphs)
+{
+  SET_BIT(DBGMCU->APB2FZ, Periphs);
+}
+
+/**
+  * @brief  Unfreeze APB2 peripherals
+  * @rmtoll DBGMCU_APB2_FZ      DBG_TIM1_STOP    LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n
+  *         DBGMCU_APB2_FZ      DBG_TIM8_STOP    LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n
+  *         DBGMCU_APB2_FZ      DBG_TIM9_STOP    LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n
+  *         DBGMCU_APB2_FZ      DBG_TIM10_STOP   LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n
+  *         DBGMCU_APB2_FZ      DBG_TIM11_STOP   LL_DBGMCU_APB2_GRP1_UnFreezePeriph
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP
+  *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP (*)
+  *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM9_STOP (*)
+  *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM10_STOP (*)
+  *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM11_STOP (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+  */
+__STATIC_INLINE void LL_DBGMCU_APB2_GRP1_UnFreezePeriph(uint32_t Periphs)
+{
+  CLEAR_BIT(DBGMCU->APB2FZ, Periphs);
+}
+/**
+  * @}
+  */
+
+/** @defgroup SYSTEM_LL_EF_FLASH FLASH
+  * @{
+  */
+
+/**
+  * @brief  Set FLASH Latency
+  * @rmtoll FLASH_ACR    LATENCY       LL_FLASH_SetLatency
+  * @param  Latency This parameter can be one of the following values:
+  *         @arg @ref LL_FLASH_LATENCY_0
+  *         @arg @ref LL_FLASH_LATENCY_1
+  *         @arg @ref LL_FLASH_LATENCY_2
+  *         @arg @ref LL_FLASH_LATENCY_3
+  *         @arg @ref LL_FLASH_LATENCY_4
+  *         @arg @ref LL_FLASH_LATENCY_5
+  *         @arg @ref LL_FLASH_LATENCY_6
+  *         @arg @ref LL_FLASH_LATENCY_7
+  *         @arg @ref LL_FLASH_LATENCY_8
+  *         @arg @ref LL_FLASH_LATENCY_9
+  *         @arg @ref LL_FLASH_LATENCY_10
+  *         @arg @ref LL_FLASH_LATENCY_11
+  *         @arg @ref LL_FLASH_LATENCY_12
+  *         @arg @ref LL_FLASH_LATENCY_13
+  *         @arg @ref LL_FLASH_LATENCY_14
+  *         @arg @ref LL_FLASH_LATENCY_15
+  * @retval None
+  */
+__STATIC_INLINE void LL_FLASH_SetLatency(uint32_t Latency)
+{
+  MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, Latency);
+}
+
+/**
+  * @brief  Get FLASH Latency
+  * @rmtoll FLASH_ACR    LATENCY       LL_FLASH_GetLatency
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_FLASH_LATENCY_0
+  *         @arg @ref LL_FLASH_LATENCY_1
+  *         @arg @ref LL_FLASH_LATENCY_2
+  *         @arg @ref LL_FLASH_LATENCY_3
+  *         @arg @ref LL_FLASH_LATENCY_4
+  *         @arg @ref LL_FLASH_LATENCY_5
+  *         @arg @ref LL_FLASH_LATENCY_6
+  *         @arg @ref LL_FLASH_LATENCY_7
+  *         @arg @ref LL_FLASH_LATENCY_8
+  *         @arg @ref LL_FLASH_LATENCY_9
+  *         @arg @ref LL_FLASH_LATENCY_10
+  *         @arg @ref LL_FLASH_LATENCY_11
+  *         @arg @ref LL_FLASH_LATENCY_12
+  *         @arg @ref LL_FLASH_LATENCY_13
+  *         @arg @ref LL_FLASH_LATENCY_14
+  *         @arg @ref LL_FLASH_LATENCY_15
+  */
+__STATIC_INLINE uint32_t LL_FLASH_GetLatency(void)
+{
+  return (uint32_t)(READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY));
+}
+
+/**
+  * @brief  Enable Prefetch
+  * @rmtoll FLASH_ACR    PRFTEN        LL_FLASH_EnablePrefetch
+  * @retval None
+  */
+__STATIC_INLINE void LL_FLASH_EnablePrefetch(void)
+{
+  SET_BIT(FLASH->ACR, FLASH_ACR_PRFTEN);
+}
+
+/**
+  * @brief  Disable Prefetch
+  * @rmtoll FLASH_ACR    PRFTEN        LL_FLASH_DisablePrefetch
+  * @retval None
+  */
+__STATIC_INLINE void LL_FLASH_DisablePrefetch(void)
+{
+  CLEAR_BIT(FLASH->ACR, FLASH_ACR_PRFTEN);
+}
+
+/**
+  * @brief  Check if Prefetch buffer is enabled
+  * @rmtoll FLASH_ACR    PRFTEN        LL_FLASH_IsPrefetchEnabled
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_FLASH_IsPrefetchEnabled(void)
+{
+  return (READ_BIT(FLASH->ACR, FLASH_ACR_PRFTEN) == (FLASH_ACR_PRFTEN));
+}
+
+/**
+  * @brief  Enable Instruction cache
+  * @rmtoll FLASH_ACR    ICEN          LL_FLASH_EnableInstCache
+  * @retval None
+  */
+__STATIC_INLINE void LL_FLASH_EnableInstCache(void)
+{
+  SET_BIT(FLASH->ACR, FLASH_ACR_ICEN);
+}
+
+/**
+  * @brief  Disable Instruction cache
+  * @rmtoll FLASH_ACR    ICEN          LL_FLASH_DisableInstCache
+  * @retval None
+  */
+__STATIC_INLINE void LL_FLASH_DisableInstCache(void)
+{
+  CLEAR_BIT(FLASH->ACR, FLASH_ACR_ICEN);
+}
+
+/**
+  * @brief  Enable Data cache
+  * @rmtoll FLASH_ACR    DCEN          LL_FLASH_EnableDataCache
+  * @retval None
+  */
+__STATIC_INLINE void LL_FLASH_EnableDataCache(void)
+{
+  SET_BIT(FLASH->ACR, FLASH_ACR_DCEN);
+}
+
+/**
+  * @brief  Disable Data cache
+  * @rmtoll FLASH_ACR    DCEN          LL_FLASH_DisableDataCache
+  * @retval None
+  */
+__STATIC_INLINE void LL_FLASH_DisableDataCache(void)
+{
+  CLEAR_BIT(FLASH->ACR, FLASH_ACR_DCEN);
+}
+
+/**
+  * @brief  Enable Instruction cache reset
+  * @note  bit can be written only when the instruction cache is disabled
+  * @rmtoll FLASH_ACR    ICRST         LL_FLASH_EnableInstCacheReset
+  * @retval None
+  */
+__STATIC_INLINE void LL_FLASH_EnableInstCacheReset(void)
+{
+  SET_BIT(FLASH->ACR, FLASH_ACR_ICRST);
+}
+
+/**
+  * @brief  Disable Instruction cache reset
+  * @rmtoll FLASH_ACR    ICRST         LL_FLASH_DisableInstCacheReset
+  * @retval None
+  */
+__STATIC_INLINE void LL_FLASH_DisableInstCacheReset(void)
+{
+  CLEAR_BIT(FLASH->ACR, FLASH_ACR_ICRST);
+}
+
+/**
+  * @brief  Enable Data cache reset
+  * @note bit can be written only when the data cache is disabled
+  * @rmtoll FLASH_ACR    DCRST         LL_FLASH_EnableDataCacheReset
+  * @retval None
+  */
+__STATIC_INLINE void LL_FLASH_EnableDataCacheReset(void)
+{
+  SET_BIT(FLASH->ACR, FLASH_ACR_DCRST);
+}
+
+/**
+  * @brief  Disable Data cache reset
+  * @rmtoll FLASH_ACR    DCRST         LL_FLASH_DisableDataCacheReset
+  * @retval None
+  */
+__STATIC_INLINE void LL_FLASH_DisableDataCacheReset(void)
+{
+  CLEAR_BIT(FLASH->ACR, FLASH_ACR_DCRST);
+}
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* defined (FLASH) || defined (SYSCFG) || defined (DBGMCU) */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_LL_SYSTEM_H */
+
+
diff --git a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_tim.h b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_tim.h
new file mode 100644
index 0000000..cf6ca38
--- /dev/null
+++ b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_tim.h
@@ -0,0 +1,4093 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_ll_tim.h
+  * @author  MCD Application Team
+  * @brief   Header file of TIM LL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2016 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_LL_TIM_H
+#define __STM32F4xx_LL_TIM_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx.h"
+
+/** @addtogroup STM32F4xx_LL_Driver
+  * @{
+  */
+
+#if defined (TIM1) || defined (TIM2) || defined (TIM3) || defined (TIM4) || defined (TIM5) || defined (TIM6) || defined (TIM7) || defined (TIM8) || defined (TIM9) || defined (TIM10) || defined (TIM11) || defined (TIM12) || defined (TIM13) || defined (TIM14)
+
+/** @defgroup TIM_LL TIM
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup TIM_LL_Private_Variables TIM Private Variables
+  * @{
+  */
+static const uint8_t OFFSET_TAB_CCMRx[] =
+{
+  0x00U,   /* 0: TIMx_CH1  */
+  0x00U,   /* 1: TIMx_CH1N */
+  0x00U,   /* 2: TIMx_CH2  */
+  0x00U,   /* 3: TIMx_CH2N */
+  0x04U,   /* 4: TIMx_CH3  */
+  0x04U,   /* 5: TIMx_CH3N */
+  0x04U    /* 6: TIMx_CH4  */
+};
+
+static const uint8_t SHIFT_TAB_OCxx[] =
+{
+  0U,            /* 0: OC1M, OC1FE, OC1PE */
+  0U,            /* 1: - NA */
+  8U,            /* 2: OC2M, OC2FE, OC2PE */
+  0U,            /* 3: - NA */
+  0U,            /* 4: OC3M, OC3FE, OC3PE */
+  0U,            /* 5: - NA */
+  8U             /* 6: OC4M, OC4FE, OC4PE */
+};
+
+static const uint8_t SHIFT_TAB_ICxx[] =
+{
+  0U,            /* 0: CC1S, IC1PSC, IC1F */
+  0U,            /* 1: - NA */
+  8U,            /* 2: CC2S, IC2PSC, IC2F */
+  0U,            /* 3: - NA */
+  0U,            /* 4: CC3S, IC3PSC, IC3F */
+  0U,            /* 5: - NA */
+  8U             /* 6: CC4S, IC4PSC, IC4F */
+};
+
+static const uint8_t SHIFT_TAB_CCxP[] =
+{
+  0U,            /* 0: CC1P */
+  2U,            /* 1: CC1NP */
+  4U,            /* 2: CC2P */
+  6U,            /* 3: CC2NP */
+  8U,            /* 4: CC3P */
+  10U,           /* 5: CC3NP */
+  12U            /* 6: CC4P */
+};
+
+static const uint8_t SHIFT_TAB_OISx[] =
+{
+  0U,            /* 0: OIS1 */
+  1U,            /* 1: OIS1N */
+  2U,            /* 2: OIS2 */
+  3U,            /* 3: OIS2N */
+  4U,            /* 4: OIS3 */
+  5U,            /* 5: OIS3N */
+  6U             /* 6: OIS4 */
+};
+/**
+  * @}
+  */
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup TIM_LL_Private_Constants TIM Private Constants
+  * @{
+  */
+
+
+/* Remap mask definitions */
+#define TIMx_OR_RMP_SHIFT  16U
+#define TIMx_OR_RMP_MASK   0x0000FFFFU
+#define TIM2_OR_RMP_MASK   (TIM_OR_ITR1_RMP << TIMx_OR_RMP_SHIFT)
+#define TIM5_OR_RMP_MASK   (TIM_OR_TI4_RMP << TIMx_OR_RMP_SHIFT)
+#define TIM11_OR_RMP_MASK  (TIM_OR_TI1_RMP << TIMx_OR_RMP_SHIFT)
+
+/* Mask used to set the TDG[x:0] of the DTG bits of the TIMx_BDTR register */
+#define DT_DELAY_1 ((uint8_t)0x7F)
+#define DT_DELAY_2 ((uint8_t)0x3F)
+#define DT_DELAY_3 ((uint8_t)0x1F)
+#define DT_DELAY_4 ((uint8_t)0x1F)
+
+/* Mask used to set the DTG[7:5] bits of the DTG bits of the TIMx_BDTR register */
+#define DT_RANGE_1 ((uint8_t)0x00)
+#define DT_RANGE_2 ((uint8_t)0x80)
+#define DT_RANGE_3 ((uint8_t)0xC0)
+#define DT_RANGE_4 ((uint8_t)0xE0)
+
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup TIM_LL_Private_Macros TIM Private Macros
+  * @{
+  */
+/** @brief  Convert channel id into channel index.
+  * @param  __CHANNEL__ This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH1N
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH2N
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH3N
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  * @retval none
+  */
+#define TIM_GET_CHANNEL_INDEX( __CHANNEL__) \
+  (((__CHANNEL__) == LL_TIM_CHANNEL_CH1) ? 0U :\
+   ((__CHANNEL__) == LL_TIM_CHANNEL_CH1N) ? 1U :\
+   ((__CHANNEL__) == LL_TIM_CHANNEL_CH2) ? 2U :\
+   ((__CHANNEL__) == LL_TIM_CHANNEL_CH2N) ? 3U :\
+   ((__CHANNEL__) == LL_TIM_CHANNEL_CH3) ? 4U :\
+   ((__CHANNEL__) == LL_TIM_CHANNEL_CH3N) ? 5U : 6U)
+
+/** @brief  Calculate the deadtime sampling period(in ps).
+  * @param  __TIMCLK__ timer input clock frequency (in Hz).
+  * @param  __CKD__ This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CLOCKDIVISION_DIV1
+  *         @arg @ref LL_TIM_CLOCKDIVISION_DIV2
+  *         @arg @ref LL_TIM_CLOCKDIVISION_DIV4
+  * @retval none
+  */
+#define TIM_CALC_DTS(__TIMCLK__, __CKD__)                                                        \
+  (((__CKD__) == LL_TIM_CLOCKDIVISION_DIV1) ? ((uint64_t)1000000000000U/(__TIMCLK__))         : \
+   ((__CKD__) == LL_TIM_CLOCKDIVISION_DIV2) ? ((uint64_t)1000000000000U/((__TIMCLK__) >> 1U)) : \
+   ((uint64_t)1000000000000U/((__TIMCLK__) >> 2U)))
+/**
+  * @}
+  */
+
+
+/* Exported types ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup TIM_LL_ES_INIT TIM Exported Init structure
+  * @{
+  */
+
+/**
+  * @brief  TIM Time Base configuration structure definition.
+  */
+typedef struct
+{
+  uint16_t Prescaler;         /*!< Specifies the prescaler value used to divide the TIM clock.
+                                   This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
+
+                                   This feature can be modified afterwards using unitary function
+                                   @ref LL_TIM_SetPrescaler().*/
+
+  uint32_t CounterMode;       /*!< Specifies the counter mode.
+                                   This parameter can be a value of @ref TIM_LL_EC_COUNTERMODE.
+
+                                   This feature can be modified afterwards using unitary function
+                                   @ref LL_TIM_SetCounterMode().*/
+
+  uint32_t Autoreload;        /*!< Specifies the auto reload value to be loaded into the active
+                                   Auto-Reload Register at the next update event.
+                                   This parameter must be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
+                                   Some timer instances may support 32 bits counters. In that case this parameter must
+                                   be a number between 0x0000 and 0xFFFFFFFF.
+
+                                   This feature can be modified afterwards using unitary function
+                                   @ref LL_TIM_SetAutoReload().*/
+
+  uint32_t ClockDivision;     /*!< Specifies the clock division.
+                                   This parameter can be a value of @ref TIM_LL_EC_CLOCKDIVISION.
+
+                                   This feature can be modified afterwards using unitary function
+                                   @ref LL_TIM_SetClockDivision().*/
+
+  uint32_t RepetitionCounter;  /*!< Specifies the repetition counter value. Each time the RCR downcounter
+                                   reaches zero, an update event is generated and counting restarts
+                                   from the RCR value (N).
+                                   This means in PWM mode that (N+1) corresponds to:
+                                      - the number of PWM periods in edge-aligned mode
+                                      - the number of half PWM period in center-aligned mode
+                                   GP timers: this parameter must be a number between Min_Data = 0x00 and
+                                   Max_Data = 0xFF.
+                                   Advanced timers: this parameter must be a number between Min_Data = 0x0000 and
+                                   Max_Data = 0xFFFF.
+
+                                   This feature can be modified afterwards using unitary function
+                                   @ref LL_TIM_SetRepetitionCounter().*/
+} LL_TIM_InitTypeDef;
+
+/**
+  * @brief  TIM Output Compare configuration structure definition.
+  */
+typedef struct
+{
+  uint32_t OCMode;        /*!< Specifies the output mode.
+                               This parameter can be a value of @ref TIM_LL_EC_OCMODE.
+
+                               This feature can be modified afterwards using unitary function
+                               @ref LL_TIM_OC_SetMode().*/
+
+  uint32_t OCState;       /*!< Specifies the TIM Output Compare state.
+                               This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
+
+                               This feature can be modified afterwards using unitary functions
+                               @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
+
+  uint32_t OCNState;      /*!< Specifies the TIM complementary Output Compare state.
+                               This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
+
+                               This feature can be modified afterwards using unitary functions
+                               @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
+
+  uint32_t CompareValue;  /*!< Specifies the Compare value to be loaded into the Capture Compare Register.
+                               This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
+
+                               This feature can be modified afterwards using unitary function
+                               LL_TIM_OC_SetCompareCHx (x=1..6).*/
+
+  uint32_t OCPolarity;    /*!< Specifies the output polarity.
+                               This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
+
+                               This feature can be modified afterwards using unitary function
+                               @ref LL_TIM_OC_SetPolarity().*/
+
+  uint32_t OCNPolarity;   /*!< Specifies the complementary output polarity.
+                               This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
+
+                               This feature can be modified afterwards using unitary function
+                               @ref LL_TIM_OC_SetPolarity().*/
+
+
+  uint32_t OCIdleState;   /*!< Specifies the TIM Output Compare pin state during Idle state.
+                               This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE.
+
+                               This feature can be modified afterwards using unitary function
+                               @ref LL_TIM_OC_SetIdleState().*/
+
+  uint32_t OCNIdleState;  /*!< Specifies the TIM Output Compare pin state during Idle state.
+                               This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE.
+
+                               This feature can be modified afterwards using unitary function
+                               @ref LL_TIM_OC_SetIdleState().*/
+} LL_TIM_OC_InitTypeDef;
+
+/**
+  * @brief  TIM Input Capture configuration structure definition.
+  */
+
+typedef struct
+{
+
+  uint32_t ICPolarity;    /*!< Specifies the active edge of the input signal.
+                               This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
+
+                               This feature can be modified afterwards using unitary function
+                               @ref LL_TIM_IC_SetPolarity().*/
+
+  uint32_t ICActiveInput; /*!< Specifies the input.
+                               This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
+
+                               This feature can be modified afterwards using unitary function
+                               @ref LL_TIM_IC_SetActiveInput().*/
+
+  uint32_t ICPrescaler;   /*!< Specifies the Input Capture Prescaler.
+                               This parameter can be a value of @ref TIM_LL_EC_ICPSC.
+
+                               This feature can be modified afterwards using unitary function
+                               @ref LL_TIM_IC_SetPrescaler().*/
+
+  uint32_t ICFilter;      /*!< Specifies the input capture filter.
+                               This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
+
+                               This feature can be modified afterwards using unitary function
+                               @ref LL_TIM_IC_SetFilter().*/
+} LL_TIM_IC_InitTypeDef;
+
+
+/**
+  * @brief  TIM Encoder interface configuration structure definition.
+  */
+typedef struct
+{
+  uint32_t EncoderMode;     /*!< Specifies the encoder resolution (x2 or x4).
+                                 This parameter can be a value of @ref TIM_LL_EC_ENCODERMODE.
+
+                                 This feature can be modified afterwards using unitary function
+                                 @ref LL_TIM_SetEncoderMode().*/
+
+  uint32_t IC1Polarity;     /*!< Specifies the active edge of TI1 input.
+                                 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
+
+                                 This feature can be modified afterwards using unitary function
+                                 @ref LL_TIM_IC_SetPolarity().*/
+
+  uint32_t IC1ActiveInput;  /*!< Specifies the TI1 input source
+                                 This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
+
+                                 This feature can be modified afterwards using unitary function
+                                 @ref LL_TIM_IC_SetActiveInput().*/
+
+  uint32_t IC1Prescaler;    /*!< Specifies the TI1 input prescaler value.
+                                 This parameter can be a value of @ref TIM_LL_EC_ICPSC.
+
+                                 This feature can be modified afterwards using unitary function
+                                 @ref LL_TIM_IC_SetPrescaler().*/
+
+  uint32_t IC1Filter;       /*!< Specifies the TI1 input filter.
+                                 This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
+
+                                 This feature can be modified afterwards using unitary function
+                                 @ref LL_TIM_IC_SetFilter().*/
+
+  uint32_t IC2Polarity;      /*!< Specifies the active edge of TI2 input.
+                                 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
+
+                                 This feature can be modified afterwards using unitary function
+                                 @ref LL_TIM_IC_SetPolarity().*/
+
+  uint32_t IC2ActiveInput;  /*!< Specifies the TI2 input source
+                                 This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
+
+                                 This feature can be modified afterwards using unitary function
+                                 @ref LL_TIM_IC_SetActiveInput().*/
+
+  uint32_t IC2Prescaler;    /*!< Specifies the TI2 input prescaler value.
+                                 This parameter can be a value of @ref TIM_LL_EC_ICPSC.
+
+                                 This feature can be modified afterwards using unitary function
+                                 @ref LL_TIM_IC_SetPrescaler().*/
+
+  uint32_t IC2Filter;       /*!< Specifies the TI2 input filter.
+                                 This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
+
+                                 This feature can be modified afterwards using unitary function
+                                 @ref LL_TIM_IC_SetFilter().*/
+
+} LL_TIM_ENCODER_InitTypeDef;
+
+/**
+  * @brief  TIM Hall sensor interface configuration structure definition.
+  */
+typedef struct
+{
+
+  uint32_t IC1Polarity;        /*!< Specifies the active edge of TI1 input.
+                                    This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
+
+                                    This feature can be modified afterwards using unitary function
+                                    @ref LL_TIM_IC_SetPolarity().*/
+
+  uint32_t IC1Prescaler;       /*!< Specifies the TI1 input prescaler value.
+                                    Prescaler must be set to get a maximum counter period longer than the
+                                    time interval between 2 consecutive changes on the Hall inputs.
+                                    This parameter can be a value of @ref TIM_LL_EC_ICPSC.
+
+                                    This feature can be modified afterwards using unitary function
+                                    @ref LL_TIM_IC_SetPrescaler().*/
+
+  uint32_t IC1Filter;          /*!< Specifies the TI1 input filter.
+                                    This parameter can be a value of
+                                    @ref TIM_LL_EC_IC_FILTER.
+
+                                    This feature can be modified afterwards using unitary function
+                                    @ref LL_TIM_IC_SetFilter().*/
+
+  uint32_t CommutationDelay;   /*!< Specifies the compare value to be loaded into the Capture Compare Register.
+                                    A positive pulse (TRGO event) is generated with a programmable delay every time
+                                    a change occurs on the Hall inputs.
+                                    This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF.
+
+                                    This feature can be modified afterwards using unitary function
+                                    @ref LL_TIM_OC_SetCompareCH2().*/
+} LL_TIM_HALLSENSOR_InitTypeDef;
+
+/**
+  * @brief  BDTR (Break and Dead Time) structure definition
+  */
+typedef struct
+{
+  uint32_t OSSRState;            /*!< Specifies the Off-State selection used in Run mode.
+                                      This parameter can be a value of @ref TIM_LL_EC_OSSR
+
+                                      This feature can be modified afterwards using unitary function
+                                      @ref LL_TIM_SetOffStates()
+
+                                      @note This bit-field cannot be modified as long as LOCK level 2 has been
+                                       programmed. */
+
+  uint32_t OSSIState;            /*!< Specifies the Off-State used in Idle state.
+                                      This parameter can be a value of @ref TIM_LL_EC_OSSI
+
+                                      This feature can be modified afterwards using unitary function
+                                      @ref LL_TIM_SetOffStates()
+
+                                      @note This bit-field cannot be modified as long as LOCK level 2 has been
+                                      programmed. */
+
+  uint32_t LockLevel;            /*!< Specifies the LOCK level parameters.
+                                      This parameter can be a value of @ref TIM_LL_EC_LOCKLEVEL
+
+                                      @note The LOCK bits can be written only once after the reset. Once the TIMx_BDTR
+                                      register has been written, their content is frozen until the next reset.*/
+
+  uint8_t DeadTime;              /*!< Specifies the delay time between the switching-off and the
+                                      switching-on of the outputs.
+                                      This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF.
+
+                                      This feature can be modified afterwards using unitary function
+                                      @ref LL_TIM_OC_SetDeadTime()
+
+                                      @note This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been
+                                       programmed. */
+
+  uint16_t BreakState;           /*!< Specifies whether the TIM Break input is enabled or not.
+                                      This parameter can be a value of @ref TIM_LL_EC_BREAK_ENABLE
+
+                                      This feature can be modified afterwards using unitary functions
+                                      @ref LL_TIM_EnableBRK() or @ref LL_TIM_DisableBRK()
+
+                                      @note This bit-field can not be modified as long as LOCK level 1 has been
+                                      programmed. */
+
+  uint32_t BreakPolarity;        /*!< Specifies the TIM Break Input pin polarity.
+                                      This parameter can be a value of @ref TIM_LL_EC_BREAK_POLARITY
+
+                                      This feature can be modified afterwards using unitary function
+                                      @ref LL_TIM_ConfigBRK()
+
+                                      @note This bit-field can not be modified as long as LOCK level 1 has been
+                                      programmed. */
+
+  uint32_t AutomaticOutput;      /*!< Specifies whether the TIM Automatic Output feature is enabled or not.
+                                      This parameter can be a value of @ref TIM_LL_EC_AUTOMATICOUTPUT_ENABLE
+
+                                      This feature can be modified afterwards using unitary functions
+                                      @ref LL_TIM_EnableAutomaticOutput() or @ref LL_TIM_DisableAutomaticOutput()
+
+                                      @note This bit-field can not be modified as long as LOCK level 1 has been
+                                      programmed. */
+} LL_TIM_BDTR_InitTypeDef;
+
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup TIM_LL_Exported_Constants TIM Exported Constants
+  * @{
+  */
+
+/** @defgroup TIM_LL_EC_GET_FLAG Get Flags Defines
+  * @brief    Flags defines which can be used with LL_TIM_ReadReg function.
+  * @{
+  */
+#define LL_TIM_SR_UIF                          TIM_SR_UIF           /*!< Update interrupt flag */
+#define LL_TIM_SR_CC1IF                        TIM_SR_CC1IF         /*!< Capture/compare 1 interrupt flag */
+#define LL_TIM_SR_CC2IF                        TIM_SR_CC2IF         /*!< Capture/compare 2 interrupt flag */
+#define LL_TIM_SR_CC3IF                        TIM_SR_CC3IF         /*!< Capture/compare 3 interrupt flag */
+#define LL_TIM_SR_CC4IF                        TIM_SR_CC4IF         /*!< Capture/compare 4 interrupt flag */
+#define LL_TIM_SR_COMIF                        TIM_SR_COMIF         /*!< COM interrupt flag */
+#define LL_TIM_SR_TIF                          TIM_SR_TIF           /*!< Trigger interrupt flag */
+#define LL_TIM_SR_BIF                          TIM_SR_BIF           /*!< Break interrupt flag */
+#define LL_TIM_SR_CC1OF                        TIM_SR_CC1OF         /*!< Capture/Compare 1 overcapture flag */
+#define LL_TIM_SR_CC2OF                        TIM_SR_CC2OF         /*!< Capture/Compare 2 overcapture flag */
+#define LL_TIM_SR_CC3OF                        TIM_SR_CC3OF         /*!< Capture/Compare 3 overcapture flag */
+#define LL_TIM_SR_CC4OF                        TIM_SR_CC4OF         /*!< Capture/Compare 4 overcapture flag */
+/**
+  * @}
+  */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup TIM_LL_EC_BREAK_ENABLE Break Enable
+  * @{
+  */
+#define LL_TIM_BREAK_DISABLE            0x00000000U             /*!< Break function disabled */
+#define LL_TIM_BREAK_ENABLE             TIM_BDTR_BKE            /*!< Break function enabled */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_AUTOMATICOUTPUT_ENABLE Automatic output enable
+  * @{
+  */
+#define LL_TIM_AUTOMATICOUTPUT_DISABLE         0x00000000U             /*!< MOE can be set only by software */
+#define LL_TIM_AUTOMATICOUTPUT_ENABLE          TIM_BDTR_AOE            /*!< MOE can be set by software or automatically at the next update event */
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/** @defgroup TIM_LL_EC_IT IT Defines
+  * @brief    IT defines which can be used with LL_TIM_ReadReg and  LL_TIM_WriteReg functions.
+  * @{
+  */
+#define LL_TIM_DIER_UIE                        TIM_DIER_UIE         /*!< Update interrupt enable */
+#define LL_TIM_DIER_CC1IE                      TIM_DIER_CC1IE       /*!< Capture/compare 1 interrupt enable */
+#define LL_TIM_DIER_CC2IE                      TIM_DIER_CC2IE       /*!< Capture/compare 2 interrupt enable */
+#define LL_TIM_DIER_CC3IE                      TIM_DIER_CC3IE       /*!< Capture/compare 3 interrupt enable */
+#define LL_TIM_DIER_CC4IE                      TIM_DIER_CC4IE       /*!< Capture/compare 4 interrupt enable */
+#define LL_TIM_DIER_COMIE                      TIM_DIER_COMIE       /*!< COM interrupt enable */
+#define LL_TIM_DIER_TIE                        TIM_DIER_TIE         /*!< Trigger interrupt enable */
+#define LL_TIM_DIER_BIE                        TIM_DIER_BIE         /*!< Break interrupt enable */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_UPDATESOURCE Update Source
+  * @{
+  */
+#define LL_TIM_UPDATESOURCE_REGULAR            0x00000000U          /*!< Counter overflow/underflow, Setting the UG bit or Update generation through the slave mode controller generates an update request */
+#define LL_TIM_UPDATESOURCE_COUNTER            TIM_CR1_URS          /*!< Only counter overflow/underflow generates an update request */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_ONEPULSEMODE One Pulse Mode
+  * @{
+  */
+#define LL_TIM_ONEPULSEMODE_SINGLE             TIM_CR1_OPM          /*!< Counter stops counting at the next update event */
+#define LL_TIM_ONEPULSEMODE_REPETITIVE         0x00000000U          /*!< Counter is not stopped at update event */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_COUNTERMODE Counter Mode
+  * @{
+  */
+#define LL_TIM_COUNTERMODE_UP                  0x00000000U          /*!<Counter used as upcounter */
+#define LL_TIM_COUNTERMODE_DOWN                TIM_CR1_DIR          /*!< Counter used as downcounter */
+#define LL_TIM_COUNTERMODE_CENTER_DOWN         TIM_CR1_CMS_0        /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels  are set only when the counter is counting down. */
+#define LL_TIM_COUNTERMODE_CENTER_UP           TIM_CR1_CMS_1        /*!<The counter counts up and down alternatively. Output compare interrupt flags of output channels  are set only when the counter is counting up */
+#define LL_TIM_COUNTERMODE_CENTER_UP_DOWN      TIM_CR1_CMS          /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels  are set only when the counter is counting up or down. */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_CLOCKDIVISION Clock Division
+  * @{
+  */
+#define LL_TIM_CLOCKDIVISION_DIV1              0x00000000U          /*!< tDTS=tCK_INT */
+#define LL_TIM_CLOCKDIVISION_DIV2              TIM_CR1_CKD_0        /*!< tDTS=2*tCK_INT */
+#define LL_TIM_CLOCKDIVISION_DIV4              TIM_CR1_CKD_1        /*!< tDTS=4*tCK_INT */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_COUNTERDIRECTION Counter Direction
+  * @{
+  */
+#define LL_TIM_COUNTERDIRECTION_UP             0x00000000U          /*!< Timer counter counts up */
+#define LL_TIM_COUNTERDIRECTION_DOWN           TIM_CR1_DIR          /*!< Timer counter counts down */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_CCUPDATESOURCE Capture Compare  Update Source
+  * @{
+  */
+#define LL_TIM_CCUPDATESOURCE_COMG_ONLY        0x00000000U          /*!< Capture/compare control bits are updated by setting the COMG bit only */
+#define LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI    TIM_CR2_CCUS         /*!< Capture/compare control bits are updated by setting the COMG bit or when a rising edge occurs on trigger input (TRGI) */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_CCDMAREQUEST Capture Compare DMA Request
+  * @{
+  */
+#define LL_TIM_CCDMAREQUEST_CC                 0x00000000U          /*!< CCx DMA request sent when CCx event occurs */
+#define LL_TIM_CCDMAREQUEST_UPDATE             TIM_CR2_CCDS         /*!< CCx DMA requests sent when update event occurs */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_LOCKLEVEL Lock Level
+  * @{
+  */
+#define LL_TIM_LOCKLEVEL_OFF                   0x00000000U          /*!< LOCK OFF - No bit is write protected */
+#define LL_TIM_LOCKLEVEL_1                     TIM_BDTR_LOCK_0      /*!< LOCK Level 1 */
+#define LL_TIM_LOCKLEVEL_2                     TIM_BDTR_LOCK_1      /*!< LOCK Level 2 */
+#define LL_TIM_LOCKLEVEL_3                     TIM_BDTR_LOCK        /*!< LOCK Level 3 */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_CHANNEL Channel
+  * @{
+  */
+#define LL_TIM_CHANNEL_CH1                     TIM_CCER_CC1E     /*!< Timer input/output channel 1 */
+#define LL_TIM_CHANNEL_CH1N                    TIM_CCER_CC1NE    /*!< Timer complementary output channel 1 */
+#define LL_TIM_CHANNEL_CH2                     TIM_CCER_CC2E     /*!< Timer input/output channel 2 */
+#define LL_TIM_CHANNEL_CH2N                    TIM_CCER_CC2NE    /*!< Timer complementary output channel 2 */
+#define LL_TIM_CHANNEL_CH3                     TIM_CCER_CC3E     /*!< Timer input/output channel 3 */
+#define LL_TIM_CHANNEL_CH3N                    TIM_CCER_CC3NE    /*!< Timer complementary output channel 3 */
+#define LL_TIM_CHANNEL_CH4                     TIM_CCER_CC4E     /*!< Timer input/output channel 4 */
+/**
+  * @}
+  */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup TIM_LL_EC_OCSTATE Output Configuration State
+  * @{
+  */
+#define LL_TIM_OCSTATE_DISABLE                 0x00000000U             /*!< OCx is not active */
+#define LL_TIM_OCSTATE_ENABLE                  TIM_CCER_CC1E           /*!< OCx signal is output on the corresponding output pin */
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/** @defgroup TIM_LL_EC_OCMODE Output Configuration Mode
+  * @{
+  */
+#define LL_TIM_OCMODE_FROZEN                   0x00000000U                                              /*!<The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the output channel level */
+#define LL_TIM_OCMODE_ACTIVE                   TIM_CCMR1_OC1M_0                                         /*!<OCyREF is forced high on compare match*/
+#define LL_TIM_OCMODE_INACTIVE                 TIM_CCMR1_OC1M_1                                         /*!<OCyREF is forced low on compare match*/
+#define LL_TIM_OCMODE_TOGGLE                   (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0)                    /*!<OCyREF toggles on compare match*/
+#define LL_TIM_OCMODE_FORCED_INACTIVE          TIM_CCMR1_OC1M_2                                         /*!<OCyREF is forced low*/
+#define LL_TIM_OCMODE_FORCED_ACTIVE            (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0)                    /*!<OCyREF is forced high*/
+#define LL_TIM_OCMODE_PWM1                     (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1)                    /*!<In upcounting, channel y is active as long as TIMx_CNT<TIMx_CCRy else inactive.  In downcounting, channel y is inactive as long as TIMx_CNT>TIMx_CCRy else active.*/
+#define LL_TIM_OCMODE_PWM2                     (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!<In upcounting, channel y is inactive as long as TIMx_CNT<TIMx_CCRy else active.  In downcounting, channel y is active as long as TIMx_CNT>TIMx_CCRy else inactive*/
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_OCPOLARITY Output Configuration Polarity
+  * @{
+  */
+#define LL_TIM_OCPOLARITY_HIGH                 0x00000000U                 /*!< OCxactive high*/
+#define LL_TIM_OCPOLARITY_LOW                  TIM_CCER_CC1P               /*!< OCxactive low*/
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_OCIDLESTATE Output Configuration Idle State
+  * @{
+  */
+#define LL_TIM_OCIDLESTATE_LOW                 0x00000000U             /*!<OCx=0 (after a dead-time if OC is implemented) when MOE=0*/
+#define LL_TIM_OCIDLESTATE_HIGH                TIM_CR2_OIS1            /*!<OCx=1 (after a dead-time if OC is implemented) when MOE=0*/
+/**
+  * @}
+  */
+
+
+/** @defgroup TIM_LL_EC_ACTIVEINPUT Active Input Selection
+  * @{
+  */
+#define LL_TIM_ACTIVEINPUT_DIRECTTI            (TIM_CCMR1_CC1S_0 << 16U) /*!< ICx is mapped on TIx */
+#define LL_TIM_ACTIVEINPUT_INDIRECTTI          (TIM_CCMR1_CC1S_1 << 16U) /*!< ICx is mapped on TIy */
+#define LL_TIM_ACTIVEINPUT_TRC                 (TIM_CCMR1_CC1S << 16U)   /*!< ICx is mapped on TRC */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_ICPSC Input Configuration Prescaler
+  * @{
+  */
+#define LL_TIM_ICPSC_DIV1                      0x00000000U                    /*!< No prescaler, capture is done each time an edge is detected on the capture input */
+#define LL_TIM_ICPSC_DIV2                      (TIM_CCMR1_IC1PSC_0 << 16U)    /*!< Capture is done once every 2 events */
+#define LL_TIM_ICPSC_DIV4                      (TIM_CCMR1_IC1PSC_1 << 16U)    /*!< Capture is done once every 4 events */
+#define LL_TIM_ICPSC_DIV8                      (TIM_CCMR1_IC1PSC << 16U)      /*!< Capture is done once every 8 events */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_IC_FILTER Input Configuration Filter
+  * @{
+  */
+#define LL_TIM_IC_FILTER_FDIV1                 0x00000000U                                                        /*!< No filter, sampling is done at fDTS */
+#define LL_TIM_IC_FILTER_FDIV1_N2              (TIM_CCMR1_IC1F_0 << 16U)                                          /*!< fSAMPLING=fCK_INT, N=2 */
+#define LL_TIM_IC_FILTER_FDIV1_N4              (TIM_CCMR1_IC1F_1 << 16U)                                          /*!< fSAMPLING=fCK_INT, N=4 */
+#define LL_TIM_IC_FILTER_FDIV1_N8              ((TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U)                     /*!< fSAMPLING=fCK_INT, N=8 */
+#define LL_TIM_IC_FILTER_FDIV2_N6              (TIM_CCMR1_IC1F_2 << 16U)                                          /*!< fSAMPLING=fDTS/2, N=6 */
+#define LL_TIM_IC_FILTER_FDIV2_N8              ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U)                     /*!< fSAMPLING=fDTS/2, N=8 */
+#define LL_TIM_IC_FILTER_FDIV4_N6              ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U)                     /*!< fSAMPLING=fDTS/4, N=6 */
+#define LL_TIM_IC_FILTER_FDIV4_N8              ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U)  /*!< fSAMPLING=fDTS/4, N=8 */
+#define LL_TIM_IC_FILTER_FDIV8_N6              (TIM_CCMR1_IC1F_3 << 16U)                                          /*!< fSAMPLING=fDTS/8, N=6 */
+#define LL_TIM_IC_FILTER_FDIV8_N8              ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_0) << 16U)                     /*!< fSAMPLING=fDTS/8, N=8 */
+#define LL_TIM_IC_FILTER_FDIV16_N5             ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1) << 16U)                     /*!< fSAMPLING=fDTS/16, N=5 */
+#define LL_TIM_IC_FILTER_FDIV16_N6             ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U)  /*!< fSAMPLING=fDTS/16, N=6 */
+#define LL_TIM_IC_FILTER_FDIV16_N8             ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2) << 16U)                     /*!< fSAMPLING=fDTS/16, N=8 */
+#define LL_TIM_IC_FILTER_FDIV32_N5             ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U)  /*!< fSAMPLING=fDTS/32, N=5 */
+#define LL_TIM_IC_FILTER_FDIV32_N6             ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U)  /*!< fSAMPLING=fDTS/32, N=6 */
+#define LL_TIM_IC_FILTER_FDIV32_N8             (TIM_CCMR1_IC1F << 16U)                                            /*!< fSAMPLING=fDTS/32, N=8 */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_IC_POLARITY Input Configuration Polarity
+  * @{
+  */
+#define LL_TIM_IC_POLARITY_RISING              0x00000000U                      /*!< The circuit is sensitive to TIxFP1 rising edge, TIxFP1 is not inverted */
+#define LL_TIM_IC_POLARITY_FALLING             TIM_CCER_CC1P                    /*!< The circuit is sensitive to TIxFP1 falling edge, TIxFP1 is inverted */
+#define LL_TIM_IC_POLARITY_BOTHEDGE            (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< The circuit is sensitive to both TIxFP1 rising and falling edges, TIxFP1 is not inverted */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_CLOCKSOURCE Clock Source
+  * @{
+  */
+#define LL_TIM_CLOCKSOURCE_INTERNAL            0x00000000U                                          /*!< The timer is clocked by the internal clock provided from the RCC */
+#define LL_TIM_CLOCKSOURCE_EXT_MODE1           (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)   /*!< Counter counts at each rising or falling edge on a selected input*/
+#define LL_TIM_CLOCKSOURCE_EXT_MODE2           TIM_SMCR_ECE                                         /*!< Counter counts at each rising or falling edge on the external trigger input ETR */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_ENCODERMODE Encoder Mode
+  * @{
+  */
+#define LL_TIM_ENCODERMODE_X2_TI1                     TIM_SMCR_SMS_0                                                     /*!< Quadrature encoder mode 1, x2 mode - Counter counts up/down on TI1FP1 edge depending on TI2FP2 level */
+#define LL_TIM_ENCODERMODE_X2_TI2                     TIM_SMCR_SMS_1                                                     /*!< Quadrature encoder mode 2, x2 mode - Counter counts up/down on TI2FP2 edge depending on TI1FP1 level */
+#define LL_TIM_ENCODERMODE_X4_TI12                   (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)                                   /*!< Quadrature encoder mode 3, x4 mode - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_TRGO Trigger Output
+  * @{
+  */
+#define LL_TIM_TRGO_RESET                      0x00000000U                                     /*!< UG bit from the TIMx_EGR register is used as trigger output */
+#define LL_TIM_TRGO_ENABLE                     TIM_CR2_MMS_0                                   /*!< Counter Enable signal (CNT_EN) is used as trigger output */
+#define LL_TIM_TRGO_UPDATE                     TIM_CR2_MMS_1                                   /*!< Update event is used as trigger output */
+#define LL_TIM_TRGO_CC1IF                      (TIM_CR2_MMS_1 | TIM_CR2_MMS_0)                 /*!< CC1 capture or a compare match is used as trigger output */
+#define LL_TIM_TRGO_OC1REF                     TIM_CR2_MMS_2                                   /*!< OC1REF signal is used as trigger output */
+#define LL_TIM_TRGO_OC2REF                     (TIM_CR2_MMS_2 | TIM_CR2_MMS_0)                 /*!< OC2REF signal is used as trigger output */
+#define LL_TIM_TRGO_OC3REF                     (TIM_CR2_MMS_2 | TIM_CR2_MMS_1)                 /*!< OC3REF signal is used as trigger output */
+#define LL_TIM_TRGO_OC4REF                     (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< OC4REF signal is used as trigger output */
+/**
+  * @}
+  */
+
+
+/** @defgroup TIM_LL_EC_SLAVEMODE Slave Mode
+  * @{
+  */
+#define LL_TIM_SLAVEMODE_DISABLED              0x00000000U                         /*!< Slave mode disabled */
+#define LL_TIM_SLAVEMODE_RESET                 TIM_SMCR_SMS_2                      /*!< Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter */
+#define LL_TIM_SLAVEMODE_GATED                 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0)   /*!< Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high */
+#define LL_TIM_SLAVEMODE_TRIGGER               (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1)   /*!< Trigger Mode - The counter starts at a rising edge of the trigger TRGI */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_TS Trigger Selection
+  * @{
+  */
+#define LL_TIM_TS_ITR0                         0x00000000U                                                     /*!< Internal Trigger 0 (ITR0) is used as trigger input */
+#define LL_TIM_TS_ITR1                         TIM_SMCR_TS_0                                                   /*!< Internal Trigger 1 (ITR1) is used as trigger input */
+#define LL_TIM_TS_ITR2                         TIM_SMCR_TS_1                                                   /*!< Internal Trigger 2 (ITR2) is used as trigger input */
+#define LL_TIM_TS_ITR3                         (TIM_SMCR_TS_0 | TIM_SMCR_TS_1)                                 /*!< Internal Trigger 3 (ITR3) is used as trigger input */
+#define LL_TIM_TS_TI1F_ED                      TIM_SMCR_TS_2                                                   /*!< TI1 Edge Detector (TI1F_ED) is used as trigger input */
+#define LL_TIM_TS_TI1FP1                       (TIM_SMCR_TS_2 | TIM_SMCR_TS_0)                                 /*!< Filtered Timer Input 1 (TI1FP1) is used as trigger input */
+#define LL_TIM_TS_TI2FP2                       (TIM_SMCR_TS_2 | TIM_SMCR_TS_1)                                 /*!< Filtered Timer Input 2 (TI12P2) is used as trigger input */
+#define LL_TIM_TS_ETRF                         (TIM_SMCR_TS_2 | TIM_SMCR_TS_1 | TIM_SMCR_TS_0)                 /*!< Filtered external Trigger (ETRF) is used as trigger input */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_ETR_POLARITY External Trigger Polarity
+  * @{
+  */
+#define LL_TIM_ETR_POLARITY_NONINVERTED        0x00000000U             /*!< ETR is non-inverted, active at high level or rising edge */
+#define LL_TIM_ETR_POLARITY_INVERTED           TIM_SMCR_ETP            /*!< ETR is inverted, active at low level or falling edge */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_ETR_PRESCALER External Trigger Prescaler
+  * @{
+  */
+#define LL_TIM_ETR_PRESCALER_DIV1              0x00000000U             /*!< ETR prescaler OFF */
+#define LL_TIM_ETR_PRESCALER_DIV2              TIM_SMCR_ETPS_0         /*!< ETR frequency is divided by 2 */
+#define LL_TIM_ETR_PRESCALER_DIV4              TIM_SMCR_ETPS_1         /*!< ETR frequency is divided by 4 */
+#define LL_TIM_ETR_PRESCALER_DIV8              TIM_SMCR_ETPS           /*!< ETR frequency is divided by 8 */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_ETR_FILTER External Trigger Filter
+  * @{
+  */
+#define LL_TIM_ETR_FILTER_FDIV1                0x00000000U                                          /*!< No filter, sampling is done at fDTS */
+#define LL_TIM_ETR_FILTER_FDIV1_N2             TIM_SMCR_ETF_0                                       /*!< fSAMPLING=fCK_INT, N=2 */
+#define LL_TIM_ETR_FILTER_FDIV1_N4             TIM_SMCR_ETF_1                                       /*!< fSAMPLING=fCK_INT, N=4 */
+#define LL_TIM_ETR_FILTER_FDIV1_N8             (TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0)                    /*!< fSAMPLING=fCK_INT, N=8 */
+#define LL_TIM_ETR_FILTER_FDIV2_N6             TIM_SMCR_ETF_2                                       /*!< fSAMPLING=fDTS/2, N=6 */
+#define LL_TIM_ETR_FILTER_FDIV2_N8             (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0)                    /*!< fSAMPLING=fDTS/2, N=8 */
+#define LL_TIM_ETR_FILTER_FDIV4_N6             (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1)                    /*!< fSAMPLING=fDTS/4, N=6 */
+#define LL_TIM_ETR_FILTER_FDIV4_N8             (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0)   /*!< fSAMPLING=fDTS/4, N=8 */
+#define LL_TIM_ETR_FILTER_FDIV8_N6             TIM_SMCR_ETF_3                                       /*!< fSAMPLING=fDTS/8, N=8 */
+#define LL_TIM_ETR_FILTER_FDIV8_N8             (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_0)                    /*!< fSAMPLING=fDTS/16, N=5 */
+#define LL_TIM_ETR_FILTER_FDIV16_N5            (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1)                    /*!< fSAMPLING=fDTS/16, N=6 */
+#define LL_TIM_ETR_FILTER_FDIV16_N6            (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0)   /*!< fSAMPLING=fDTS/16, N=8 */
+#define LL_TIM_ETR_FILTER_FDIV16_N8            (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2)                    /*!< fSAMPLING=fDTS/16, N=5 */
+#define LL_TIM_ETR_FILTER_FDIV32_N5            (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0)   /*!< fSAMPLING=fDTS/32, N=5 */
+#define LL_TIM_ETR_FILTER_FDIV32_N6            (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1)   /*!< fSAMPLING=fDTS/32, N=6 */
+#define LL_TIM_ETR_FILTER_FDIV32_N8            TIM_SMCR_ETF                                         /*!< fSAMPLING=fDTS/32, N=8 */
+/**
+  * @}
+  */
+
+
+/** @defgroup TIM_LL_EC_BREAK_POLARITY break polarity
+  * @{
+  */
+#define LL_TIM_BREAK_POLARITY_LOW              0x00000000U               /*!< Break input BRK is active low */
+#define LL_TIM_BREAK_POLARITY_HIGH             TIM_BDTR_BKP              /*!< Break input BRK is active high */
+/**
+  * @}
+  */
+
+
+
+
+/** @defgroup TIM_LL_EC_OSSI OSSI
+  * @{
+  */
+#define LL_TIM_OSSI_DISABLE                    0x00000000U             /*!< When inactive, OCx/OCxN outputs are disabled */
+#define LL_TIM_OSSI_ENABLE                     TIM_BDTR_OSSI           /*!< When inactive, OxC/OCxN outputs are first forced with their inactive level then forced to their idle level after the deadtime */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_OSSR OSSR
+  * @{
+  */
+#define LL_TIM_OSSR_DISABLE                    0x00000000U             /*!< When inactive, OCx/OCxN outputs are disabled */
+#define LL_TIM_OSSR_ENABLE                     TIM_BDTR_OSSR           /*!< When inactive, OC/OCN outputs are enabled with their inactive level as soon as CCxE=1 or CCxNE=1 */
+/**
+  * @}
+  */
+
+
+/** @defgroup TIM_LL_EC_DMABURST_BASEADDR DMA Burst Base Address
+  * @{
+  */
+#define LL_TIM_DMABURST_BASEADDR_CR1           0x00000000U                                                      /*!< TIMx_CR1 register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_CR2           TIM_DCR_DBA_0                                                    /*!< TIMx_CR2 register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_SMCR          TIM_DCR_DBA_1                                                    /*!< TIMx_SMCR register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_DIER          (TIM_DCR_DBA_1 |  TIM_DCR_DBA_0)                                 /*!< TIMx_DIER register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_SR            TIM_DCR_DBA_2                                                    /*!< TIMx_SR register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_EGR           (TIM_DCR_DBA_2 | TIM_DCR_DBA_0)                                  /*!< TIMx_EGR register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_CCMR1         (TIM_DCR_DBA_2 | TIM_DCR_DBA_1)                                  /*!< TIMx_CCMR1 register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_CCMR2         (TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0)                  /*!< TIMx_CCMR2 register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_CCER          TIM_DCR_DBA_3                                                    /*!< TIMx_CCER register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_CNT           (TIM_DCR_DBA_3 | TIM_DCR_DBA_0)                                  /*!< TIMx_CNT register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_PSC           (TIM_DCR_DBA_3 | TIM_DCR_DBA_1)                                  /*!< TIMx_PSC register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_ARR           (TIM_DCR_DBA_3 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0)                  /*!< TIMx_ARR register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_RCR           (TIM_DCR_DBA_3 | TIM_DCR_DBA_2)                                  /*!< TIMx_RCR register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_CCR1          (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0)                  /*!< TIMx_CCR1 register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_CCR2          (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1)                  /*!< TIMx_CCR2 register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_CCR3          (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0)  /*!< TIMx_CCR3 register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_CCR4          TIM_DCR_DBA_4                                                    /*!< TIMx_CCR4 register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_BDTR          (TIM_DCR_DBA_4 | TIM_DCR_DBA_0)                                  /*!< TIMx_BDTR register is the DMA base address for DMA burst */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_DMABURST_LENGTH DMA Burst Length
+  * @{
+  */
+#define LL_TIM_DMABURST_LENGTH_1TRANSFER       0x00000000U                                                     /*!< Transfer is done to 1 register starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_2TRANSFERS      TIM_DCR_DBL_0                                                   /*!< Transfer is done to 2 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_3TRANSFERS      TIM_DCR_DBL_1                                                   /*!< Transfer is done to 3 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_4TRANSFERS      (TIM_DCR_DBL_1 |  TIM_DCR_DBL_0)                                /*!< Transfer is done to 4 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_5TRANSFERS      TIM_DCR_DBL_2                                                   /*!< Transfer is done to 5 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_6TRANSFERS      (TIM_DCR_DBL_2 | TIM_DCR_DBL_0)                                 /*!< Transfer is done to 6 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_7TRANSFERS      (TIM_DCR_DBL_2 | TIM_DCR_DBL_1)                                 /*!< Transfer is done to 7 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_8TRANSFERS      (TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0)                 /*!< Transfer is done to 1 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_9TRANSFERS      TIM_DCR_DBL_3                                                   /*!< Transfer is done to 9 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_10TRANSFERS     (TIM_DCR_DBL_3 | TIM_DCR_DBL_0)                                 /*!< Transfer is done to 10 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_11TRANSFERS     (TIM_DCR_DBL_3 | TIM_DCR_DBL_1)                                 /*!< Transfer is done to 11 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_12TRANSFERS     (TIM_DCR_DBL_3 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0)                 /*!< Transfer is done to 12 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_13TRANSFERS     (TIM_DCR_DBL_3 | TIM_DCR_DBL_2)                                 /*!< Transfer is done to 13 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_14TRANSFERS     (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_0)                 /*!< Transfer is done to 14 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_15TRANSFERS     (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1)                 /*!< Transfer is done to 15 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_16TRANSFERS     (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 16 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_17TRANSFERS     TIM_DCR_DBL_4                                                   /*!< Transfer is done to 17 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_18TRANSFERS     (TIM_DCR_DBL_4 |  TIM_DCR_DBL_0)                                /*!< Transfer is done to 18 registers starting from the DMA burst base address */
+/**
+  * @}
+  */
+
+
+/** @defgroup TIM_LL_EC_TIM2_ITR1_RMP_TIM8  TIM2 Internal Trigger1 Remap TIM8
+  * @{
+  */
+#define LL_TIM_TIM2_ITR1_RMP_TIM8_TRGO    TIM2_OR_RMP_MASK                        /*!< TIM2_ITR1 is connected to TIM8_TRGO */
+#define LL_TIM_TIM2_ITR1_RMP_ETH_PTP      (TIM_OR_ITR1_RMP_0 | TIM2_OR_RMP_MASK)  /*!< TIM2_ITR1 is connected to ETH_PTP */
+#define LL_TIM_TIM2_ITR1_RMP_OTG_FS_SOF   (TIM_OR_ITR1_RMP_1 | TIM2_OR_RMP_MASK)  /*!< TIM2_ITR1 is connected to OTG_FS SOF */
+#define LL_TIM_TIM2_ITR1_RMP_OTG_HS_SOF   (TIM_OR_ITR1_RMP | TIM2_OR_RMP_MASK)    /*!< TIM2_ITR1 is connected to OTG_HS SOF */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_TIM5_TI4_RMP  TIM5 External Input Ch4 Remap
+  * @{
+  */
+#define LL_TIM_TIM5_TI4_RMP_GPIO        TIM5_OR_RMP_MASK                         /*!< TIM5 channel 4 is connected to GPIO */
+#define LL_TIM_TIM5_TI4_RMP_LSI         (TIM_OR_TI4_RMP_0 | TIM5_OR_RMP_MASK)    /*!< TIM5 channel 4 is connected to LSI internal clock */
+#define LL_TIM_TIM5_TI4_RMP_LSE         (TIM_OR_TI4_RMP_1 | TIM5_OR_RMP_MASK)    /*!< TIM5 channel 4 is connected to LSE */
+#define LL_TIM_TIM5_TI4_RMP_RTC         (TIM_OR_TI4_RMP | TIM5_OR_RMP_MASK)      /*!< TIM5 channel 4 is connected to RTC wakeup interrupt */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_TIM11_TI1_RMP  TIM11 External Input Capture 1 Remap
+  * @{
+  */
+#define LL_TIM_TIM11_TI1_RMP_GPIO        TIM11_OR_RMP_MASK                          /*!< TIM11 channel 1 is connected to GPIO */
+#if defined(SPDIFRX)
+#define LL_TIM_TIM11_TI1_RMP_SPDIFRX     (TIM_OR_TI1_RMP_0 | TIM11_OR_RMP_MASK)     /*!< TIM11 channel 1 is connected to SPDIFRX */
+
+/* Legacy define */
+#define  LL_TIM_TIM11_TI1_RMP_GPIO1      LL_TIM_TIM11_TI1_RMP_SPDIFRX               /*!< Legacy define for LL_TIM_TIM11_TI1_RMP_SPDIFRX */
+
+#else
+#define LL_TIM_TIM11_TI1_RMP_GPIO1       (TIM_OR_TI1_RMP_0 | TIM11_OR_RMP_MASK)     /*!< TIM11 channel 1 is connected to GPIO */
+#endif /* SPDIFRX */
+#define LL_TIM_TIM11_TI1_RMP_GPIO2       (TIM_OR_TI1_RMP   | TIM11_OR_RMP_MASK)     /*!< TIM11 channel 1 is connected to GPIO */
+#define LL_TIM_TIM11_TI1_RMP_HSE_RTC     (TIM_OR_TI1_RMP_1 | TIM11_OR_RMP_MASK)     /*!< TIM11 channel 1 is connected to HSE_RTC */
+/**
+  * @}
+  */
+#if defined(LPTIM_OR_TIM1_ITR2_RMP) && defined(LPTIM_OR_TIM5_ITR1_RMP) && defined(LPTIM_OR_TIM9_ITR1_RMP)
+
+#define LL_TIM_LPTIM_REMAP_MASK           0x10000000U
+
+#define LL_TIM_TIM9_ITR1_RMP_TIM3_TRGO    LL_TIM_LPTIM_REMAP_MASK                              /*!< TIM9_ITR1 is connected to TIM3 TRGO */
+#define LL_TIM_TIM9_ITR1_RMP_LPTIM       (LL_TIM_LPTIM_REMAP_MASK | LPTIM_OR_TIM9_ITR1_RMP)    /*!< TIM9_ITR1 is connected to LPTIM1 output */
+
+#define LL_TIM_TIM5_ITR1_RMP_TIM3_TRGO    LL_TIM_LPTIM_REMAP_MASK                              /*!< TIM5_ITR1 is connected to TIM3 TRGO */
+#define LL_TIM_TIM5_ITR1_RMP_LPTIM       (LL_TIM_LPTIM_REMAP_MASK | LPTIM_OR_TIM5_ITR1_RMP)    /*!< TIM5_ITR1 is connected to LPTIM1 output */
+
+#define LL_TIM_TIM1_ITR2_RMP_TIM3_TRGO    LL_TIM_LPTIM_REMAP_MASK                              /*!< TIM1_ITR2 is connected to TIM3 TRGO */
+#define LL_TIM_TIM1_ITR2_RMP_LPTIM       (LL_TIM_LPTIM_REMAP_MASK | LPTIM_OR_TIM1_ITR2_RMP)    /*!< TIM1_ITR2 is connected to LPTIM1 output */
+
+#endif /* LPTIM_OR_TIM1_ITR2_RMP &&  LPTIM_OR_TIM5_ITR1_RMP && LPTIM_OR_TIM9_ITR1_RMP */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup TIM_LL_Exported_Macros TIM Exported Macros
+  * @{
+  */
+
+/** @defgroup TIM_LL_EM_WRITE_READ Common Write and read registers Macros
+  * @{
+  */
+/**
+  * @brief  Write a value in TIM register.
+  * @param  __INSTANCE__ TIM Instance
+  * @param  __REG__ Register to be written
+  * @param  __VALUE__ Value to be written in the register
+  * @retval None
+  */
+#define LL_TIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))
+
+/**
+  * @brief  Read a value in TIM register.
+  * @param  __INSTANCE__ TIM Instance
+  * @param  __REG__ Register to be read
+  * @retval Register value
+  */
+#define LL_TIM_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__)
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EM_Exported_Macros Exported_Macros
+  * @{
+  */
+
+/**
+  * @brief  HELPER macro calculating DTG[0:7] in the TIMx_BDTR register to achieve the requested dead time duration.
+  * @note ex: @ref __LL_TIM_CALC_DEADTIME (80000000, @ref LL_TIM_GetClockDivision (), 120);
+  * @param  __TIMCLK__ timer input clock frequency (in Hz)
+  * @param  __CKD__ This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CLOCKDIVISION_DIV1
+  *         @arg @ref LL_TIM_CLOCKDIVISION_DIV2
+  *         @arg @ref LL_TIM_CLOCKDIVISION_DIV4
+  * @param  __DT__ deadtime duration (in ns)
+  * @retval DTG[0:7]
+  */
+#define __LL_TIM_CALC_DEADTIME(__TIMCLK__, __CKD__, __DT__)  \
+  ( (((uint64_t)((__DT__)*1000U)) < ((DT_DELAY_1+1U) * TIM_CALC_DTS((__TIMCLK__), (__CKD__))))    ?  \
+    (uint8_t)(((uint64_t)((__DT__)*1000U) / TIM_CALC_DTS((__TIMCLK__), (__CKD__)))  & DT_DELAY_1) :      \
+    (((uint64_t)((__DT__)*1000U)) < ((64U + (DT_DELAY_2+1U)) * 2U * TIM_CALC_DTS((__TIMCLK__), (__CKD__))))  ?  \
+    (uint8_t)(DT_RANGE_2 | ((uint8_t)((uint8_t)((((uint64_t)((__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__),   \
+                                                 (__CKD__))) >> 1U) - (uint8_t) 64) & DT_DELAY_2)) :\
+    (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_3+1U)) * 8U * TIM_CALC_DTS((__TIMCLK__), (__CKD__))))  ?  \
+    (uint8_t)(DT_RANGE_3 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__),  \
+                                                 (__CKD__))) >> 3U) - (uint8_t) 32) & DT_DELAY_3)) :\
+    (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_4+1U)) * 16U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ?  \
+    (uint8_t)(DT_RANGE_4 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__),  \
+                                                 (__CKD__))) >> 4U) - (uint8_t) 32) & DT_DELAY_4)) :\
+    0U)
+
+/**
+  * @brief  HELPER macro calculating the prescaler value to achieve the required counter clock frequency.
+  * @note ex: @ref __LL_TIM_CALC_PSC (80000000, 1000000);
+  * @param  __TIMCLK__ timer input clock frequency (in Hz)
+  * @param  __CNTCLK__ counter clock frequency (in Hz)
+  * @retval Prescaler value  (between Min_Data=0 and Max_Data=65535)
+  */
+#define __LL_TIM_CALC_PSC(__TIMCLK__, __CNTCLK__)   \
+  (((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)((((__TIMCLK__) + (__CNTCLK__)/2U)/(__CNTCLK__)) - 1U) : 0U)
+
+/**
+  * @brief  HELPER macro calculating the auto-reload value to achieve the required output signal frequency.
+  * @note ex: @ref __LL_TIM_CALC_ARR (1000000, @ref LL_TIM_GetPrescaler (), 10000);
+  * @param  __TIMCLK__ timer input clock frequency (in Hz)
+  * @param  __PSC__ prescaler
+  * @param  __FREQ__ output signal frequency (in Hz)
+  * @retval  Auto-reload value  (between Min_Data=0 and Max_Data=65535)
+  */
+#define __LL_TIM_CALC_ARR(__TIMCLK__, __PSC__, __FREQ__) \
+  ((((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? (((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1U))) - 1U) : 0U)
+
+/**
+  * @brief  HELPER macro calculating the compare value required to achieve the required timer output compare
+  *         active/inactive delay.
+  * @note ex: @ref __LL_TIM_CALC_DELAY (1000000, @ref LL_TIM_GetPrescaler (), 10);
+  * @param  __TIMCLK__ timer input clock frequency (in Hz)
+  * @param  __PSC__ prescaler
+  * @param  __DELAY__ timer output compare active/inactive delay (in us)
+  * @retval Compare value  (between Min_Data=0 and Max_Data=65535)
+  */
+#define __LL_TIM_CALC_DELAY(__TIMCLK__, __PSC__, __DELAY__)  \
+  ((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__)) \
+              / ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U))))
+
+/**
+  * @brief  HELPER macro calculating the auto-reload value to achieve the required pulse duration
+  *         (when the timer operates in one pulse mode).
+  * @note ex: @ref __LL_TIM_CALC_PULSE (1000000, @ref LL_TIM_GetPrescaler (), 10, 20);
+  * @param  __TIMCLK__ timer input clock frequency (in Hz)
+  * @param  __PSC__ prescaler
+  * @param  __DELAY__ timer output compare active/inactive delay (in us)
+  * @param  __PULSE__ pulse duration (in us)
+  * @retval Auto-reload value  (between Min_Data=0 and Max_Data=65535)
+  */
+#define __LL_TIM_CALC_PULSE(__TIMCLK__, __PSC__, __DELAY__, __PULSE__)  \
+  ((uint32_t)(__LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__PULSE__)) \
+              + __LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__DELAY__))))
+
+/**
+  * @brief  HELPER macro retrieving the ratio of the input capture prescaler
+  * @note ex: @ref __LL_TIM_GET_ICPSC_RATIO (@ref LL_TIM_IC_GetPrescaler ());
+  * @param  __ICPSC__ This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_ICPSC_DIV1
+  *         @arg @ref LL_TIM_ICPSC_DIV2
+  *         @arg @ref LL_TIM_ICPSC_DIV4
+  *         @arg @ref LL_TIM_ICPSC_DIV8
+  * @retval Input capture prescaler ratio (1, 2, 4 or 8)
+  */
+#define __LL_TIM_GET_ICPSC_RATIO(__ICPSC__)  \
+  ((uint32_t)(0x01U << (((__ICPSC__) >> 16U) >> TIM_CCMR1_IC1PSC_Pos)))
+
+
+/**
+  * @}
+  */
+
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup TIM_LL_Exported_Functions TIM Exported Functions
+  * @{
+  */
+
+/** @defgroup TIM_LL_EF_Time_Base Time Base configuration
+  * @{
+  */
+/**
+  * @brief  Enable timer counter.
+  * @rmtoll CR1          CEN           LL_TIM_EnableCounter
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableCounter(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->CR1, TIM_CR1_CEN);
+}
+
+/**
+  * @brief  Disable timer counter.
+  * @rmtoll CR1          CEN           LL_TIM_DisableCounter
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableCounter(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->CR1, TIM_CR1_CEN);
+}
+
+/**
+  * @brief  Indicates whether the timer counter is enabled.
+  * @rmtoll CR1          CEN           LL_TIM_IsEnabledCounter
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledCounter(TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->CR1, TIM_CR1_CEN) == (TIM_CR1_CEN)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable update event generation.
+  * @rmtoll CR1          UDIS          LL_TIM_EnableUpdateEvent
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableUpdateEvent(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->CR1, TIM_CR1_UDIS);
+}
+
+/**
+  * @brief  Disable update event generation.
+  * @rmtoll CR1          UDIS          LL_TIM_DisableUpdateEvent
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableUpdateEvent(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->CR1, TIM_CR1_UDIS);
+}
+
+/**
+  * @brief  Indicates whether update event generation is enabled.
+  * @rmtoll CR1          UDIS          LL_TIM_IsEnabledUpdateEvent
+  * @param  TIMx Timer instance
+  * @retval Inverted state of bit (0 or 1).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledUpdateEvent(TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->CR1, TIM_CR1_UDIS) == (uint32_t)RESET) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Set update event source
+  * @note Update event source set to LL_TIM_UPDATESOURCE_REGULAR: any of the following events
+  *       generate an update interrupt or DMA request if enabled:
+  *        - Counter overflow/underflow
+  *        - Setting the UG bit
+  *        - Update generation through the slave mode controller
+  * @note Update event source set to LL_TIM_UPDATESOURCE_COUNTER: only counter
+  *       overflow/underflow generates an update interrupt or DMA request if enabled.
+  * @rmtoll CR1          URS           LL_TIM_SetUpdateSource
+  * @param  TIMx Timer instance
+  * @param  UpdateSource This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_UPDATESOURCE_REGULAR
+  *         @arg @ref LL_TIM_UPDATESOURCE_COUNTER
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_SetUpdateSource(TIM_TypeDef *TIMx, uint32_t UpdateSource)
+{
+  MODIFY_REG(TIMx->CR1, TIM_CR1_URS, UpdateSource);
+}
+
+/**
+  * @brief  Get actual event update source
+  * @rmtoll CR1          URS           LL_TIM_GetUpdateSource
+  * @param  TIMx Timer instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_TIM_UPDATESOURCE_REGULAR
+  *         @arg @ref LL_TIM_UPDATESOURCE_COUNTER
+  */
+__STATIC_INLINE uint32_t LL_TIM_GetUpdateSource(TIM_TypeDef *TIMx)
+{
+  return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_URS));
+}
+
+/**
+  * @brief  Set one pulse mode (one shot v.s. repetitive).
+  * @rmtoll CR1          OPM           LL_TIM_SetOnePulseMode
+  * @param  TIMx Timer instance
+  * @param  OnePulseMode This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
+  *         @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_SetOnePulseMode(TIM_TypeDef *TIMx, uint32_t OnePulseMode)
+{
+  MODIFY_REG(TIMx->CR1, TIM_CR1_OPM, OnePulseMode);
+}
+
+/**
+  * @brief  Get actual one pulse mode.
+  * @rmtoll CR1          OPM           LL_TIM_GetOnePulseMode
+  * @param  TIMx Timer instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
+  *         @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
+  */
+__STATIC_INLINE uint32_t LL_TIM_GetOnePulseMode(TIM_TypeDef *TIMx)
+{
+  return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_OPM));
+}
+
+/**
+  * @brief  Set the timer counter counting mode.
+  * @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
+  *       check whether or not the counter mode selection feature is supported
+  *       by a timer instance.
+  * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
+  *       requires a timer reset to avoid unexpected direction
+  *       due to DIR bit readonly in center aligned mode.
+  * @rmtoll CR1          DIR           LL_TIM_SetCounterMode\n
+  *         CR1          CMS           LL_TIM_SetCounterMode
+  * @param  TIMx Timer instance
+  * @param  CounterMode This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_COUNTERMODE_UP
+  *         @arg @ref LL_TIM_COUNTERMODE_DOWN
+  *         @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
+  *         @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
+  *         @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_SetCounterMode(TIM_TypeDef *TIMx, uint32_t CounterMode)
+{
+  MODIFY_REG(TIMx->CR1, (TIM_CR1_DIR | TIM_CR1_CMS), CounterMode);
+}
+
+/**
+  * @brief  Get actual counter mode.
+  * @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
+  *       check whether or not the counter mode selection feature is supported
+  *       by a timer instance.
+  * @rmtoll CR1          DIR           LL_TIM_GetCounterMode\n
+  *         CR1          CMS           LL_TIM_GetCounterMode
+  * @param  TIMx Timer instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_TIM_COUNTERMODE_UP
+  *         @arg @ref LL_TIM_COUNTERMODE_DOWN
+  *         @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
+  *         @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
+  *         @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
+  */
+__STATIC_INLINE uint32_t LL_TIM_GetCounterMode(TIM_TypeDef *TIMx)
+{
+  uint32_t counter_mode;
+
+  counter_mode = (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CMS));
+
+  if (counter_mode == 0U)
+  {
+    counter_mode = (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR));
+  }
+
+  return counter_mode;
+}
+
+/**
+  * @brief  Enable auto-reload (ARR) preload.
+  * @rmtoll CR1          ARPE          LL_TIM_EnableARRPreload
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableARRPreload(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->CR1, TIM_CR1_ARPE);
+}
+
+/**
+  * @brief  Disable auto-reload (ARR) preload.
+  * @rmtoll CR1          ARPE          LL_TIM_DisableARRPreload
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableARRPreload(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->CR1, TIM_CR1_ARPE);
+}
+
+/**
+  * @brief  Indicates whether auto-reload (ARR) preload is enabled.
+  * @rmtoll CR1          ARPE          LL_TIM_IsEnabledARRPreload
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledARRPreload(TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->CR1, TIM_CR1_ARPE) == (TIM_CR1_ARPE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Set the division ratio between the timer clock  and the sampling clock used by the dead-time generators
+  *         (when supported) and the digital filters.
+  * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
+  *       whether or not the clock division feature is supported by the timer
+  *       instance.
+  * @rmtoll CR1          CKD           LL_TIM_SetClockDivision
+  * @param  TIMx Timer instance
+  * @param  ClockDivision This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CLOCKDIVISION_DIV1
+  *         @arg @ref LL_TIM_CLOCKDIVISION_DIV2
+  *         @arg @ref LL_TIM_CLOCKDIVISION_DIV4
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_SetClockDivision(TIM_TypeDef *TIMx, uint32_t ClockDivision)
+{
+  MODIFY_REG(TIMx->CR1, TIM_CR1_CKD, ClockDivision);
+}
+
+/**
+  * @brief  Get the actual division ratio between the timer clock  and the sampling clock used by the dead-time
+  *         generators (when supported) and the digital filters.
+  * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
+  *       whether or not the clock division feature is supported by the timer
+  *       instance.
+  * @rmtoll CR1          CKD           LL_TIM_GetClockDivision
+  * @param  TIMx Timer instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_TIM_CLOCKDIVISION_DIV1
+  *         @arg @ref LL_TIM_CLOCKDIVISION_DIV2
+  *         @arg @ref LL_TIM_CLOCKDIVISION_DIV4
+  */
+__STATIC_INLINE uint32_t LL_TIM_GetClockDivision(TIM_TypeDef *TIMx)
+{
+  return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CKD));
+}
+
+/**
+  * @brief  Set the counter value.
+  * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports a 32 bits counter.
+  * @rmtoll CNT          CNT           LL_TIM_SetCounter
+  * @param  TIMx Timer instance
+  * @param  Counter Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF)
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_SetCounter(TIM_TypeDef *TIMx, uint32_t Counter)
+{
+  WRITE_REG(TIMx->CNT, Counter);
+}
+
+/**
+  * @brief  Get the counter value.
+  * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports a 32 bits counter.
+  * @rmtoll CNT          CNT           LL_TIM_GetCounter
+  * @param  TIMx Timer instance
+  * @retval Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF)
+  */
+__STATIC_INLINE uint32_t LL_TIM_GetCounter(TIM_TypeDef *TIMx)
+{
+  return (uint32_t)(READ_REG(TIMx->CNT));
+}
+
+/**
+  * @brief  Get the current direction of the counter
+  * @rmtoll CR1          DIR           LL_TIM_GetDirection
+  * @param  TIMx Timer instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_TIM_COUNTERDIRECTION_UP
+  *         @arg @ref LL_TIM_COUNTERDIRECTION_DOWN
+  */
+__STATIC_INLINE uint32_t LL_TIM_GetDirection(TIM_TypeDef *TIMx)
+{
+  return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR));
+}
+
+/**
+  * @brief  Set the prescaler value.
+  * @note The counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1).
+  * @note The prescaler can be changed on the fly as this control register is buffered. The new
+  *       prescaler ratio is taken into account at the next update event.
+  * @note Helper macro @ref __LL_TIM_CALC_PSC can be used to calculate the Prescaler parameter
+  * @rmtoll PSC          PSC           LL_TIM_SetPrescaler
+  * @param  TIMx Timer instance
+  * @param  Prescaler between Min_Data=0 and Max_Data=65535
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Prescaler)
+{
+  WRITE_REG(TIMx->PSC, Prescaler);
+}
+
+/**
+  * @brief  Get the prescaler value.
+  * @rmtoll PSC          PSC           LL_TIM_GetPrescaler
+  * @param  TIMx Timer instance
+  * @retval  Prescaler value between Min_Data=0 and Max_Data=65535
+  */
+__STATIC_INLINE uint32_t LL_TIM_GetPrescaler(TIM_TypeDef *TIMx)
+{
+  return (uint32_t)(READ_REG(TIMx->PSC));
+}
+
+/**
+  * @brief  Set the auto-reload value.
+  * @note The counter is blocked while the auto-reload value is null.
+  * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports a 32 bits counter.
+  * @note Helper macro @ref __LL_TIM_CALC_ARR can be used to calculate the AutoReload parameter
+  * @rmtoll ARR          ARR           LL_TIM_SetAutoReload
+  * @param  TIMx Timer instance
+  * @param  AutoReload between Min_Data=0 and Max_Data=65535
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_SetAutoReload(TIM_TypeDef *TIMx, uint32_t AutoReload)
+{
+  WRITE_REG(TIMx->ARR, AutoReload);
+}
+
+/**
+  * @brief  Get the auto-reload value.
+  * @rmtoll ARR          ARR           LL_TIM_GetAutoReload
+  * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports a 32 bits counter.
+  * @param  TIMx Timer instance
+  * @retval Auto-reload value
+  */
+__STATIC_INLINE uint32_t LL_TIM_GetAutoReload(TIM_TypeDef *TIMx)
+{
+  return (uint32_t)(READ_REG(TIMx->ARR));
+}
+
+/**
+  * @brief  Set the repetition counter value.
+  * @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports a repetition counter.
+  * @rmtoll RCR          REP           LL_TIM_SetRepetitionCounter
+  * @param  TIMx Timer instance
+  * @param  RepetitionCounter between Min_Data=0 and Max_Data=255 or 65535 for advanced timer.
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_SetRepetitionCounter(TIM_TypeDef *TIMx, uint32_t RepetitionCounter)
+{
+  WRITE_REG(TIMx->RCR, RepetitionCounter);
+}
+
+/**
+  * @brief  Get the repetition counter value.
+  * @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports a repetition counter.
+  * @rmtoll RCR          REP           LL_TIM_GetRepetitionCounter
+  * @param  TIMx Timer instance
+  * @retval Repetition counter value
+  */
+__STATIC_INLINE uint32_t LL_TIM_GetRepetitionCounter(TIM_TypeDef *TIMx)
+{
+  return (uint32_t)(READ_REG(TIMx->RCR));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EF_Capture_Compare Capture Compare configuration
+  * @{
+  */
+/**
+  * @brief  Enable  the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
+  * @note CCxE, CCxNE and OCxM bits are preloaded, after having been written,
+  *       they are updated only when a commutation event (COM) occurs.
+  * @note Only on channels that have a complementary output.
+  * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance is able to generate a commutation event.
+  * @rmtoll CR2          CCPC          LL_TIM_CC_EnablePreload
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_CC_EnablePreload(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->CR2, TIM_CR2_CCPC);
+}
+
+/**
+  * @brief  Disable  the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
+  * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance is able to generate a commutation event.
+  * @rmtoll CR2          CCPC          LL_TIM_CC_DisablePreload
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_CC_DisablePreload(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->CR2, TIM_CR2_CCPC);
+}
+
+/**
+  * @brief  Set the updated source of the capture/compare control bits (CCxE, CCxNE and OCxM).
+  * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance is able to generate a commutation event.
+  * @rmtoll CR2          CCUS          LL_TIM_CC_SetUpdate
+  * @param  TIMx Timer instance
+  * @param  CCUpdateSource This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CCUPDATESOURCE_COMG_ONLY
+  *         @arg @ref LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_CC_SetUpdate(TIM_TypeDef *TIMx, uint32_t CCUpdateSource)
+{
+  MODIFY_REG(TIMx->CR2, TIM_CR2_CCUS, CCUpdateSource);
+}
+
+/**
+  * @brief  Set the trigger of the capture/compare DMA request.
+  * @rmtoll CR2          CCDS          LL_TIM_CC_SetDMAReqTrigger
+  * @param  TIMx Timer instance
+  * @param  DMAReqTrigger This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CCDMAREQUEST_CC
+  *         @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_CC_SetDMAReqTrigger(TIM_TypeDef *TIMx, uint32_t DMAReqTrigger)
+{
+  MODIFY_REG(TIMx->CR2, TIM_CR2_CCDS, DMAReqTrigger);
+}
+
+/**
+  * @brief  Get actual trigger of the capture/compare DMA request.
+  * @rmtoll CR2          CCDS          LL_TIM_CC_GetDMAReqTrigger
+  * @param  TIMx Timer instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_TIM_CCDMAREQUEST_CC
+  *         @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
+  */
+__STATIC_INLINE uint32_t LL_TIM_CC_GetDMAReqTrigger(TIM_TypeDef *TIMx)
+{
+  return (uint32_t)(READ_BIT(TIMx->CR2, TIM_CR2_CCDS));
+}
+
+/**
+  * @brief  Set the lock level to freeze the
+  *         configuration of several capture/compare parameters.
+  * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+  *       the lock mechanism is supported by a timer instance.
+  * @rmtoll BDTR         LOCK          LL_TIM_CC_SetLockLevel
+  * @param  TIMx Timer instance
+  * @param  LockLevel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_LOCKLEVEL_OFF
+  *         @arg @ref LL_TIM_LOCKLEVEL_1
+  *         @arg @ref LL_TIM_LOCKLEVEL_2
+  *         @arg @ref LL_TIM_LOCKLEVEL_3
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_CC_SetLockLevel(TIM_TypeDef *TIMx, uint32_t LockLevel)
+{
+  MODIFY_REG(TIMx->BDTR, TIM_BDTR_LOCK, LockLevel);
+}
+
+/**
+  * @brief  Enable capture/compare channels.
+  * @rmtoll CCER         CC1E          LL_TIM_CC_EnableChannel\n
+  *         CCER         CC1NE         LL_TIM_CC_EnableChannel\n
+  *         CCER         CC2E          LL_TIM_CC_EnableChannel\n
+  *         CCER         CC2NE         LL_TIM_CC_EnableChannel\n
+  *         CCER         CC3E          LL_TIM_CC_EnableChannel\n
+  *         CCER         CC3NE         LL_TIM_CC_EnableChannel\n
+  *         CCER         CC4E          LL_TIM_CC_EnableChannel
+  * @param  TIMx Timer instance
+  * @param  Channels This parameter can be a combination of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH1N
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH2N
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH3N
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_CC_EnableChannel(TIM_TypeDef *TIMx, uint32_t Channels)
+{
+  SET_BIT(TIMx->CCER, Channels);
+}
+
+/**
+  * @brief  Disable capture/compare channels.
+  * @rmtoll CCER         CC1E          LL_TIM_CC_DisableChannel\n
+  *         CCER         CC1NE         LL_TIM_CC_DisableChannel\n
+  *         CCER         CC2E          LL_TIM_CC_DisableChannel\n
+  *         CCER         CC2NE         LL_TIM_CC_DisableChannel\n
+  *         CCER         CC3E          LL_TIM_CC_DisableChannel\n
+  *         CCER         CC3NE         LL_TIM_CC_DisableChannel\n
+  *         CCER         CC4E          LL_TIM_CC_DisableChannel
+  * @param  TIMx Timer instance
+  * @param  Channels This parameter can be a combination of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH1N
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH2N
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH3N
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_CC_DisableChannel(TIM_TypeDef *TIMx, uint32_t Channels)
+{
+  CLEAR_BIT(TIMx->CCER, Channels);
+}
+
+/**
+  * @brief  Indicate whether channel(s) is(are) enabled.
+  * @rmtoll CCER         CC1E          LL_TIM_CC_IsEnabledChannel\n
+  *         CCER         CC1NE         LL_TIM_CC_IsEnabledChannel\n
+  *         CCER         CC2E          LL_TIM_CC_IsEnabledChannel\n
+  *         CCER         CC2NE         LL_TIM_CC_IsEnabledChannel\n
+  *         CCER         CC3E          LL_TIM_CC_IsEnabledChannel\n
+  *         CCER         CC3NE         LL_TIM_CC_IsEnabledChannel\n
+  *         CCER         CC4E          LL_TIM_CC_IsEnabledChannel
+  * @param  TIMx Timer instance
+  * @param  Channels This parameter can be a combination of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH1N
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH2N
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH3N
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledChannel(TIM_TypeDef *TIMx, uint32_t Channels)
+{
+  return ((READ_BIT(TIMx->CCER, Channels) == (Channels)) ? 1UL : 0UL);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EF_Output_Channel Output channel configuration
+  * @{
+  */
+/**
+  * @brief  Configure an output channel.
+  * @rmtoll CCMR1        CC1S          LL_TIM_OC_ConfigOutput\n
+  *         CCMR1        CC2S          LL_TIM_OC_ConfigOutput\n
+  *         CCMR2        CC3S          LL_TIM_OC_ConfigOutput\n
+  *         CCMR2        CC4S          LL_TIM_OC_ConfigOutput\n
+  *         CCER         CC1P          LL_TIM_OC_ConfigOutput\n
+  *         CCER         CC2P          LL_TIM_OC_ConfigOutput\n
+  *         CCER         CC3P          LL_TIM_OC_ConfigOutput\n
+  *         CCER         CC4P          LL_TIM_OC_ConfigOutput\n
+  *         CR2          OIS1          LL_TIM_OC_ConfigOutput\n
+  *         CR2          OIS2          LL_TIM_OC_ConfigOutput\n
+  *         CR2          OIS3          LL_TIM_OC_ConfigOutput\n
+  *         CR2          OIS4          LL_TIM_OC_ConfigOutput
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  * @param  Configuration This parameter must be a combination of all the following values:
+  *         @arg @ref LL_TIM_OCPOLARITY_HIGH or @ref LL_TIM_OCPOLARITY_LOW
+  *         @arg @ref LL_TIM_OCIDLESTATE_LOW or @ref LL_TIM_OCIDLESTATE_HIGH
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+  CLEAR_BIT(*pReg, (TIM_CCMR1_CC1S << SHIFT_TAB_OCxx[iChannel]));
+  MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]),
+             (Configuration & TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]);
+  MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]),
+             (Configuration & TIM_CR2_OIS1) << SHIFT_TAB_OISx[iChannel]);
+}
+
+/**
+  * @brief  Define the behavior of the output reference signal OCxREF from which
+  *         OCx and OCxN (when relevant) are derived.
+  * @rmtoll CCMR1        OC1M          LL_TIM_OC_SetMode\n
+  *         CCMR1        OC2M          LL_TIM_OC_SetMode\n
+  *         CCMR2        OC3M          LL_TIM_OC_SetMode\n
+  *         CCMR2        OC4M          LL_TIM_OC_SetMode
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  * @param  Mode This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_OCMODE_FROZEN
+  *         @arg @ref LL_TIM_OCMODE_ACTIVE
+  *         @arg @ref LL_TIM_OCMODE_INACTIVE
+  *         @arg @ref LL_TIM_OCMODE_TOGGLE
+  *         @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
+  *         @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
+  *         @arg @ref LL_TIM_OCMODE_PWM1
+  *         @arg @ref LL_TIM_OCMODE_PWM2
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Mode)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+  MODIFY_REG(*pReg, ((TIM_CCMR1_OC1M  | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel]), Mode << SHIFT_TAB_OCxx[iChannel]);
+}
+
+/**
+  * @brief  Get the output compare mode of an output channel.
+  * @rmtoll CCMR1        OC1M          LL_TIM_OC_GetMode\n
+  *         CCMR1        OC2M          LL_TIM_OC_GetMode\n
+  *         CCMR2        OC3M          LL_TIM_OC_GetMode\n
+  *         CCMR2        OC4M          LL_TIM_OC_GetMode
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_TIM_OCMODE_FROZEN
+  *         @arg @ref LL_TIM_OCMODE_ACTIVE
+  *         @arg @ref LL_TIM_OCMODE_INACTIVE
+  *         @arg @ref LL_TIM_OCMODE_TOGGLE
+  *         @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
+  *         @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
+  *         @arg @ref LL_TIM_OCMODE_PWM1
+  *         @arg @ref LL_TIM_OCMODE_PWM2
+  */
+__STATIC_INLINE uint32_t LL_TIM_OC_GetMode(TIM_TypeDef *TIMx, uint32_t Channel)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+  return (READ_BIT(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel])) >> SHIFT_TAB_OCxx[iChannel]);
+}
+
+/**
+  * @brief  Set the polarity of an output channel.
+  * @rmtoll CCER         CC1P          LL_TIM_OC_SetPolarity\n
+  *         CCER         CC1NP         LL_TIM_OC_SetPolarity\n
+  *         CCER         CC2P          LL_TIM_OC_SetPolarity\n
+  *         CCER         CC2NP         LL_TIM_OC_SetPolarity\n
+  *         CCER         CC3P          LL_TIM_OC_SetPolarity\n
+  *         CCER         CC3NP         LL_TIM_OC_SetPolarity\n
+  *         CCER         CC4P          LL_TIM_OC_SetPolarity
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH1N
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH2N
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH3N
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  * @param  Polarity This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_OCPOLARITY_HIGH
+  *         @arg @ref LL_TIM_OCPOLARITY_LOW
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_OC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Polarity)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]),  Polarity << SHIFT_TAB_CCxP[iChannel]);
+}
+
+/**
+  * @brief  Get the polarity of an output channel.
+  * @rmtoll CCER         CC1P          LL_TIM_OC_GetPolarity\n
+  *         CCER         CC1NP         LL_TIM_OC_GetPolarity\n
+  *         CCER         CC2P          LL_TIM_OC_GetPolarity\n
+  *         CCER         CC2NP         LL_TIM_OC_GetPolarity\n
+  *         CCER         CC3P          LL_TIM_OC_GetPolarity\n
+  *         CCER         CC3NP         LL_TIM_OC_GetPolarity\n
+  *         CCER         CC4P          LL_TIM_OC_GetPolarity
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH1N
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH2N
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH3N
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_TIM_OCPOLARITY_HIGH
+  *         @arg @ref LL_TIM_OCPOLARITY_LOW
+  */
+__STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  return (READ_BIT(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel])) >> SHIFT_TAB_CCxP[iChannel]);
+}
+
+/**
+  * @brief  Set the IDLE state of an output channel
+  * @note This function is significant only for the timer instances
+  *       supporting the break feature. Macro IS_TIM_BREAK_INSTANCE(TIMx)
+  *       can be used to check whether or not a timer instance provides
+  *       a break input.
+  * @rmtoll CR2         OIS1          LL_TIM_OC_SetIdleState\n
+  *         CR2         OIS1N         LL_TIM_OC_SetIdleState\n
+  *         CR2         OIS2          LL_TIM_OC_SetIdleState\n
+  *         CR2         OIS2N         LL_TIM_OC_SetIdleState\n
+  *         CR2         OIS3          LL_TIM_OC_SetIdleState\n
+  *         CR2         OIS3N         LL_TIM_OC_SetIdleState\n
+  *         CR2         OIS4          LL_TIM_OC_SetIdleState
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH1N
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH2N
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH3N
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  * @param  IdleState This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_OCIDLESTATE_LOW
+  *         @arg @ref LL_TIM_OCIDLESTATE_HIGH
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_OC_SetIdleState(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t IdleState)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]),  IdleState << SHIFT_TAB_OISx[iChannel]);
+}
+
+/**
+  * @brief  Get the IDLE state of an output channel
+  * @rmtoll CR2         OIS1          LL_TIM_OC_GetIdleState\n
+  *         CR2         OIS1N         LL_TIM_OC_GetIdleState\n
+  *         CR2         OIS2          LL_TIM_OC_GetIdleState\n
+  *         CR2         OIS2N         LL_TIM_OC_GetIdleState\n
+  *         CR2         OIS3          LL_TIM_OC_GetIdleState\n
+  *         CR2         OIS3N         LL_TIM_OC_GetIdleState\n
+  *         CR2         OIS4          LL_TIM_OC_GetIdleState
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH1N
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH2N
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH3N
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_TIM_OCIDLESTATE_LOW
+  *         @arg @ref LL_TIM_OCIDLESTATE_HIGH
+  */
+__STATIC_INLINE uint32_t LL_TIM_OC_GetIdleState(TIM_TypeDef *TIMx, uint32_t Channel)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  return (READ_BIT(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel])) >> SHIFT_TAB_OISx[iChannel]);
+}
+
+/**
+  * @brief  Enable fast mode for the output channel.
+  * @note Acts only if the channel is configured in PWM1 or PWM2 mode.
+  * @rmtoll CCMR1        OC1FE          LL_TIM_OC_EnableFast\n
+  *         CCMR1        OC2FE          LL_TIM_OC_EnableFast\n
+  *         CCMR2        OC3FE          LL_TIM_OC_EnableFast\n
+  *         CCMR2        OC4FE          LL_TIM_OC_EnableFast
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_OC_EnableFast(TIM_TypeDef *TIMx, uint32_t Channel)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+  SET_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
+
+}
+
+/**
+  * @brief  Disable fast mode for the output channel.
+  * @rmtoll CCMR1        OC1FE          LL_TIM_OC_DisableFast\n
+  *         CCMR1        OC2FE          LL_TIM_OC_DisableFast\n
+  *         CCMR2        OC3FE          LL_TIM_OC_DisableFast\n
+  *         CCMR2        OC4FE          LL_TIM_OC_DisableFast
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_OC_DisableFast(TIM_TypeDef *TIMx, uint32_t Channel)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+  CLEAR_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
+
+}
+
+/**
+  * @brief  Indicates whether fast mode is enabled for the output channel.
+  * @rmtoll CCMR1        OC1FE          LL_TIM_OC_IsEnabledFast\n
+  *         CCMR1        OC2FE          LL_TIM_OC_IsEnabledFast\n
+  *         CCMR2        OC3FE          LL_TIM_OC_IsEnabledFast\n
+  *         CCMR2        OC4FE          LL_TIM_OC_IsEnabledFast\n
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(TIM_TypeDef *TIMx, uint32_t Channel)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+  uint32_t bitfield = TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel];
+  return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable compare register (TIMx_CCRx) preload for the output channel.
+  * @rmtoll CCMR1        OC1PE          LL_TIM_OC_EnablePreload\n
+  *         CCMR1        OC2PE          LL_TIM_OC_EnablePreload\n
+  *         CCMR2        OC3PE          LL_TIM_OC_EnablePreload\n
+  *         CCMR2        OC4PE          LL_TIM_OC_EnablePreload
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_OC_EnablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+  SET_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
+}
+
+/**
+  * @brief  Disable compare register (TIMx_CCRx) preload for the output channel.
+  * @rmtoll CCMR1        OC1PE          LL_TIM_OC_DisablePreload\n
+  *         CCMR1        OC2PE          LL_TIM_OC_DisablePreload\n
+  *         CCMR2        OC3PE          LL_TIM_OC_DisablePreload\n
+  *         CCMR2        OC4PE          LL_TIM_OC_DisablePreload
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_OC_DisablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+  CLEAR_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
+}
+
+/**
+  * @brief  Indicates whether compare register (TIMx_CCRx) preload is enabled for the output channel.
+  * @rmtoll CCMR1        OC1PE          LL_TIM_OC_IsEnabledPreload\n
+  *         CCMR1        OC2PE          LL_TIM_OC_IsEnabledPreload\n
+  *         CCMR2        OC3PE          LL_TIM_OC_IsEnabledPreload\n
+  *         CCMR2        OC4PE          LL_TIM_OC_IsEnabledPreload\n
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(TIM_TypeDef *TIMx, uint32_t Channel)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+  uint32_t bitfield = TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel];
+  return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable clearing the output channel on an external event.
+  * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
+  * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
+  *       or not a timer instance can clear the OCxREF signal on an external event.
+  * @rmtoll CCMR1        OC1CE          LL_TIM_OC_EnableClear\n
+  *         CCMR1        OC2CE          LL_TIM_OC_EnableClear\n
+  *         CCMR2        OC3CE          LL_TIM_OC_EnableClear\n
+  *         CCMR2        OC4CE          LL_TIM_OC_EnableClear
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_OC_EnableClear(TIM_TypeDef *TIMx, uint32_t Channel)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+  SET_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
+}
+
+/**
+  * @brief  Disable clearing the output channel on an external event.
+  * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
+  *       or not a timer instance can clear the OCxREF signal on an external event.
+  * @rmtoll CCMR1        OC1CE          LL_TIM_OC_DisableClear\n
+  *         CCMR1        OC2CE          LL_TIM_OC_DisableClear\n
+  *         CCMR2        OC3CE          LL_TIM_OC_DisableClear\n
+  *         CCMR2        OC4CE          LL_TIM_OC_DisableClear
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_OC_DisableClear(TIM_TypeDef *TIMx, uint32_t Channel)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+  CLEAR_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
+}
+
+/**
+  * @brief  Indicates clearing the output channel on an external event is enabled for the output channel.
+  * @note This function enables clearing the output channel on an external event.
+  * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
+  * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
+  *       or not a timer instance can clear the OCxREF signal on an external event.
+  * @rmtoll CCMR1        OC1CE          LL_TIM_OC_IsEnabledClear\n
+  *         CCMR1        OC2CE          LL_TIM_OC_IsEnabledClear\n
+  *         CCMR2        OC3CE          LL_TIM_OC_IsEnabledClear\n
+  *         CCMR2        OC4CE          LL_TIM_OC_IsEnabledClear\n
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(TIM_TypeDef *TIMx, uint32_t Channel)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+  uint32_t bitfield = TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel];
+  return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Set the dead-time delay (delay inserted between the rising edge of the OCxREF signal and the rising edge of
+  *         the Ocx and OCxN signals).
+  * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+  *       dead-time insertion feature is supported by a timer instance.
+  * @note Helper macro @ref __LL_TIM_CALC_DEADTIME can be used to calculate the DeadTime parameter
+  * @rmtoll BDTR         DTG           LL_TIM_OC_SetDeadTime
+  * @param  TIMx Timer instance
+  * @param  DeadTime between Min_Data=0 and Max_Data=255
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_OC_SetDeadTime(TIM_TypeDef *TIMx, uint32_t DeadTime)
+{
+  MODIFY_REG(TIMx->BDTR, TIM_BDTR_DTG, DeadTime);
+}
+
+/**
+  * @brief  Set compare value for output channel 1 (TIMx_CCR1).
+  * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
+  * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports a 32 bits counter.
+  * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
+  *       output channel 1 is supported by a timer instance.
+  * @rmtoll CCR1         CCR1          LL_TIM_OC_SetCompareCH1
+  * @param  TIMx Timer instance
+  * @param  CompareValue between Min_Data=0 and Max_Data=65535
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_OC_SetCompareCH1(TIM_TypeDef *TIMx, uint32_t CompareValue)
+{
+  WRITE_REG(TIMx->CCR1, CompareValue);
+}
+
+/**
+  * @brief  Set compare value for output channel 2 (TIMx_CCR2).
+  * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
+  * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports a 32 bits counter.
+  * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
+  *       output channel 2 is supported by a timer instance.
+  * @rmtoll CCR2         CCR2          LL_TIM_OC_SetCompareCH2
+  * @param  TIMx Timer instance
+  * @param  CompareValue between Min_Data=0 and Max_Data=65535
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_OC_SetCompareCH2(TIM_TypeDef *TIMx, uint32_t CompareValue)
+{
+  WRITE_REG(TIMx->CCR2, CompareValue);
+}
+
+/**
+  * @brief  Set compare value for output channel 3 (TIMx_CCR3).
+  * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
+  * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports a 32 bits counter.
+  * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
+  *       output channel is supported by a timer instance.
+  * @rmtoll CCR3         CCR3          LL_TIM_OC_SetCompareCH3
+  * @param  TIMx Timer instance
+  * @param  CompareValue between Min_Data=0 and Max_Data=65535
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_OC_SetCompareCH3(TIM_TypeDef *TIMx, uint32_t CompareValue)
+{
+  WRITE_REG(TIMx->CCR3, CompareValue);
+}
+
+/**
+  * @brief  Set compare value for output channel 4 (TIMx_CCR4).
+  * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
+  * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports a 32 bits counter.
+  * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
+  *       output channel 4 is supported by a timer instance.
+  * @rmtoll CCR4         CCR4          LL_TIM_OC_SetCompareCH4
+  * @param  TIMx Timer instance
+  * @param  CompareValue between Min_Data=0 and Max_Data=65535
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_OC_SetCompareCH4(TIM_TypeDef *TIMx, uint32_t CompareValue)
+{
+  WRITE_REG(TIMx->CCR4, CompareValue);
+}
+
+/**
+  * @brief  Get compare value (TIMx_CCR1) set for  output channel 1.
+  * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
+  * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports a 32 bits counter.
+  * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
+  *       output channel 1 is supported by a timer instance.
+  * @rmtoll CCR1         CCR1          LL_TIM_OC_GetCompareCH1
+  * @param  TIMx Timer instance
+  * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
+  */
+__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH1(TIM_TypeDef *TIMx)
+{
+  return (uint32_t)(READ_REG(TIMx->CCR1));
+}
+
+/**
+  * @brief  Get compare value (TIMx_CCR2) set for  output channel 2.
+  * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
+  * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports a 32 bits counter.
+  * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
+  *       output channel 2 is supported by a timer instance.
+  * @rmtoll CCR2         CCR2          LL_TIM_OC_GetCompareCH2
+  * @param  TIMx Timer instance
+  * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
+  */
+__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH2(TIM_TypeDef *TIMx)
+{
+  return (uint32_t)(READ_REG(TIMx->CCR2));
+}
+
+/**
+  * @brief  Get compare value (TIMx_CCR3) set for  output channel 3.
+  * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
+  * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports a 32 bits counter.
+  * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
+  *       output channel 3 is supported by a timer instance.
+  * @rmtoll CCR3         CCR3          LL_TIM_OC_GetCompareCH3
+  * @param  TIMx Timer instance
+  * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
+  */
+__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH3(TIM_TypeDef *TIMx)
+{
+  return (uint32_t)(READ_REG(TIMx->CCR3));
+}
+
+/**
+  * @brief  Get compare value (TIMx_CCR4) set for  output channel 4.
+  * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
+  * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports a 32 bits counter.
+  * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
+  *       output channel 4 is supported by a timer instance.
+  * @rmtoll CCR4         CCR4          LL_TIM_OC_GetCompareCH4
+  * @param  TIMx Timer instance
+  * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
+  */
+__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH4(TIM_TypeDef *TIMx)
+{
+  return (uint32_t)(READ_REG(TIMx->CCR4));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EF_Input_Channel Input channel configuration
+  * @{
+  */
+/**
+  * @brief  Configure input channel.
+  * @rmtoll CCMR1        CC1S          LL_TIM_IC_Config\n
+  *         CCMR1        IC1PSC        LL_TIM_IC_Config\n
+  *         CCMR1        IC1F          LL_TIM_IC_Config\n
+  *         CCMR1        CC2S          LL_TIM_IC_Config\n
+  *         CCMR1        IC2PSC        LL_TIM_IC_Config\n
+  *         CCMR1        IC2F          LL_TIM_IC_Config\n
+  *         CCMR2        CC3S          LL_TIM_IC_Config\n
+  *         CCMR2        IC3PSC        LL_TIM_IC_Config\n
+  *         CCMR2        IC3F          LL_TIM_IC_Config\n
+  *         CCMR2        CC4S          LL_TIM_IC_Config\n
+  *         CCMR2        IC4PSC        LL_TIM_IC_Config\n
+  *         CCMR2        IC4F          LL_TIM_IC_Config\n
+  *         CCER         CC1P          LL_TIM_IC_Config\n
+  *         CCER         CC1NP         LL_TIM_IC_Config\n
+  *         CCER         CC2P          LL_TIM_IC_Config\n
+  *         CCER         CC2NP         LL_TIM_IC_Config\n
+  *         CCER         CC3P          LL_TIM_IC_Config\n
+  *         CCER         CC3NP         LL_TIM_IC_Config\n
+  *         CCER         CC4P          LL_TIM_IC_Config\n
+  *         CCER         CC4NP         LL_TIM_IC_Config
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  * @param  Configuration This parameter must be a combination of all the following values:
+  *         @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI or @ref LL_TIM_ACTIVEINPUT_INDIRECTTI or @ref LL_TIM_ACTIVEINPUT_TRC
+  *         @arg @ref LL_TIM_ICPSC_DIV1 or ... or @ref LL_TIM_ICPSC_DIV8
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV1 or ... or @ref LL_TIM_IC_FILTER_FDIV32_N8
+  *         @arg @ref LL_TIM_IC_POLARITY_RISING or @ref LL_TIM_IC_POLARITY_FALLING or @ref LL_TIM_IC_POLARITY_BOTHEDGE
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+  MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]),
+             ((Configuration >> 16U) & (TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S))                \
+             << SHIFT_TAB_ICxx[iChannel]);
+  MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
+             (Configuration & (TIM_CCER_CC1NP | TIM_CCER_CC1P)) << SHIFT_TAB_CCxP[iChannel]);
+}
+
+/**
+  * @brief  Set the active input.
+  * @rmtoll CCMR1        CC1S          LL_TIM_IC_SetActiveInput\n
+  *         CCMR1        CC2S          LL_TIM_IC_SetActiveInput\n
+  *         CCMR2        CC3S          LL_TIM_IC_SetActiveInput\n
+  *         CCMR2        CC4S          LL_TIM_IC_SetActiveInput
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  * @param  ICActiveInput This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
+  *         @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
+  *         @arg @ref LL_TIM_ACTIVEINPUT_TRC
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_IC_SetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICActiveInput)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+  MODIFY_REG(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), (ICActiveInput >> 16U) << SHIFT_TAB_ICxx[iChannel]);
+}
+
+/**
+  * @brief  Get the current active input.
+  * @rmtoll CCMR1        CC1S          LL_TIM_IC_GetActiveInput\n
+  *         CCMR1        CC2S          LL_TIM_IC_GetActiveInput\n
+  *         CCMR2        CC3S          LL_TIM_IC_GetActiveInput\n
+  *         CCMR2        CC4S          LL_TIM_IC_GetActiveInput
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
+  *         @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
+  *         @arg @ref LL_TIM_ACTIVEINPUT_TRC
+  */
+__STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+  return ((READ_BIT(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
+}
+
+/**
+  * @brief  Set the prescaler of input channel.
+  * @rmtoll CCMR1        IC1PSC        LL_TIM_IC_SetPrescaler\n
+  *         CCMR1        IC2PSC        LL_TIM_IC_SetPrescaler\n
+  *         CCMR2        IC3PSC        LL_TIM_IC_SetPrescaler\n
+  *         CCMR2        IC4PSC        LL_TIM_IC_SetPrescaler
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  * @param  ICPrescaler This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_ICPSC_DIV1
+  *         @arg @ref LL_TIM_ICPSC_DIV2
+  *         @arg @ref LL_TIM_ICPSC_DIV4
+  *         @arg @ref LL_TIM_ICPSC_DIV8
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_IC_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPrescaler)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+  MODIFY_REG(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel]), (ICPrescaler >> 16U) << SHIFT_TAB_ICxx[iChannel]);
+}
+
+/**
+  * @brief  Get the current prescaler value acting on an  input channel.
+  * @rmtoll CCMR1        IC1PSC        LL_TIM_IC_GetPrescaler\n
+  *         CCMR1        IC2PSC        LL_TIM_IC_GetPrescaler\n
+  *         CCMR2        IC3PSC        LL_TIM_IC_GetPrescaler\n
+  *         CCMR2        IC4PSC        LL_TIM_IC_GetPrescaler
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_TIM_ICPSC_DIV1
+  *         @arg @ref LL_TIM_ICPSC_DIV2
+  *         @arg @ref LL_TIM_ICPSC_DIV4
+  *         @arg @ref LL_TIM_ICPSC_DIV8
+  */
+__STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+  return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
+}
+
+/**
+  * @brief  Set the input filter duration.
+  * @rmtoll CCMR1        IC1F          LL_TIM_IC_SetFilter\n
+  *         CCMR1        IC2F          LL_TIM_IC_SetFilter\n
+  *         CCMR2        IC3F          LL_TIM_IC_SetFilter\n
+  *         CCMR2        IC4F          LL_TIM_IC_SetFilter
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  * @param  ICFilter This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV1
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_IC_SetFilter(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICFilter)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+  MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel]), (ICFilter >> 16U) << SHIFT_TAB_ICxx[iChannel]);
+}
+
+/**
+  * @brief  Get the input filter duration.
+  * @rmtoll CCMR1        IC1F          LL_TIM_IC_GetFilter\n
+  *         CCMR1        IC2F          LL_TIM_IC_GetFilter\n
+  *         CCMR2        IC3F          LL_TIM_IC_GetFilter\n
+  *         CCMR2        IC4F          LL_TIM_IC_GetFilter
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV1
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
+  */
+__STATIC_INLINE uint32_t LL_TIM_IC_GetFilter(TIM_TypeDef *TIMx, uint32_t Channel)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+  return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
+}
+
+/**
+  * @brief  Set the input channel polarity.
+  * @rmtoll CCER         CC1P          LL_TIM_IC_SetPolarity\n
+  *         CCER         CC1NP         LL_TIM_IC_SetPolarity\n
+  *         CCER         CC2P          LL_TIM_IC_SetPolarity\n
+  *         CCER         CC2NP         LL_TIM_IC_SetPolarity\n
+  *         CCER         CC3P          LL_TIM_IC_SetPolarity\n
+  *         CCER         CC3NP         LL_TIM_IC_SetPolarity\n
+  *         CCER         CC4P          LL_TIM_IC_SetPolarity\n
+  *         CCER         CC4NP         LL_TIM_IC_SetPolarity
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  * @param  ICPolarity This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_IC_POLARITY_RISING
+  *         @arg @ref LL_TIM_IC_POLARITY_FALLING
+  *         @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_IC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPolarity)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
+             ICPolarity << SHIFT_TAB_CCxP[iChannel]);
+}
+
+/**
+  * @brief  Get the current input channel polarity.
+  * @rmtoll CCER         CC1P          LL_TIM_IC_GetPolarity\n
+  *         CCER         CC1NP         LL_TIM_IC_GetPolarity\n
+  *         CCER         CC2P          LL_TIM_IC_GetPolarity\n
+  *         CCER         CC2NP         LL_TIM_IC_GetPolarity\n
+  *         CCER         CC3P          LL_TIM_IC_GetPolarity\n
+  *         CCER         CC3NP         LL_TIM_IC_GetPolarity\n
+  *         CCER         CC4P          LL_TIM_IC_GetPolarity\n
+  *         CCER         CC4NP         LL_TIM_IC_GetPolarity
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_TIM_IC_POLARITY_RISING
+  *         @arg @ref LL_TIM_IC_POLARITY_FALLING
+  *         @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE
+  */
+__STATIC_INLINE uint32_t LL_TIM_IC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  return (READ_BIT(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel])) >>
+          SHIFT_TAB_CCxP[iChannel]);
+}
+
+/**
+  * @brief  Connect the TIMx_CH1, CH2 and CH3 pins  to the TI1 input (XOR combination).
+  * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides an XOR input.
+  * @rmtoll CR2          TI1S          LL_TIM_IC_EnableXORCombination
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_IC_EnableXORCombination(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->CR2, TIM_CR2_TI1S);
+}
+
+/**
+  * @brief  Disconnect the TIMx_CH1, CH2 and CH3 pins  from the TI1 input.
+  * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides an XOR input.
+  * @rmtoll CR2          TI1S          LL_TIM_IC_DisableXORCombination
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_IC_DisableXORCombination(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->CR2, TIM_CR2_TI1S);
+}
+
+/**
+  * @brief  Indicates whether the TIMx_CH1, CH2 and CH3 pins are connectected to the TI1 input.
+  * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
+  * a timer instance provides an XOR input.
+  * @rmtoll CR2          TI1S          LL_TIM_IC_IsEnabledXORCombination
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IC_IsEnabledXORCombination(TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->CR2, TIM_CR2_TI1S) == (TIM_CR2_TI1S)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get captured value for input channel 1.
+  * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
+  * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports a 32 bits counter.
+  * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
+  *       input channel 1 is supported by a timer instance.
+  * @rmtoll CCR1         CCR1          LL_TIM_IC_GetCaptureCH1
+  * @param  TIMx Timer instance
+  * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
+  */
+__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH1(TIM_TypeDef *TIMx)
+{
+  return (uint32_t)(READ_REG(TIMx->CCR1));
+}
+
+/**
+  * @brief  Get captured value for input channel 2.
+  * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
+  * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports a 32 bits counter.
+  * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
+  *       input channel 2 is supported by a timer instance.
+  * @rmtoll CCR2         CCR2          LL_TIM_IC_GetCaptureCH2
+  * @param  TIMx Timer instance
+  * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
+  */
+__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH2(TIM_TypeDef *TIMx)
+{
+  return (uint32_t)(READ_REG(TIMx->CCR2));
+}
+
+/**
+  * @brief  Get captured value for input channel 3.
+  * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
+  * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports a 32 bits counter.
+  * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
+  *       input channel 3 is supported by a timer instance.
+  * @rmtoll CCR3         CCR3          LL_TIM_IC_GetCaptureCH3
+  * @param  TIMx Timer instance
+  * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
+  */
+__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH3(TIM_TypeDef *TIMx)
+{
+  return (uint32_t)(READ_REG(TIMx->CCR3));
+}
+
+/**
+  * @brief  Get captured value for input channel 4.
+  * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
+  * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports a 32 bits counter.
+  * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
+  *       input channel 4 is supported by a timer instance.
+  * @rmtoll CCR4         CCR4          LL_TIM_IC_GetCaptureCH4
+  * @param  TIMx Timer instance
+  * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
+  */
+__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH4(TIM_TypeDef *TIMx)
+{
+  return (uint32_t)(READ_REG(TIMx->CCR4));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EF_Clock_Selection Counter clock selection
+  * @{
+  */
+/**
+  * @brief  Enable external clock mode 2.
+  * @note When external clock mode 2 is enabled the counter is clocked by any active edge on the ETRF signal.
+  * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports external clock mode2.
+  * @rmtoll SMCR         ECE           LL_TIM_EnableExternalClock
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableExternalClock(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->SMCR, TIM_SMCR_ECE);
+}
+
+/**
+  * @brief  Disable external clock mode 2.
+  * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports external clock mode2.
+  * @rmtoll SMCR         ECE           LL_TIM_DisableExternalClock
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableExternalClock(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->SMCR, TIM_SMCR_ECE);
+}
+
+/**
+  * @brief  Indicate whether external clock mode 2 is enabled.
+  * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports external clock mode2.
+  * @rmtoll SMCR         ECE           LL_TIM_IsEnabledExternalClock
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledExternalClock(TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->SMCR, TIM_SMCR_ECE) == (TIM_SMCR_ECE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Set the clock source of the counter clock.
+  * @note when selected clock source is external clock mode 1, the timer input
+  *       the external clock is applied is selected by calling the @ref LL_TIM_SetTriggerInput()
+  *       function. This timer input must be configured by calling
+  *       the @ref LL_TIM_IC_Config() function.
+  * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports external clock mode1.
+  * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports external clock mode2.
+  * @rmtoll SMCR         SMS           LL_TIM_SetClockSource\n
+  *         SMCR         ECE           LL_TIM_SetClockSource
+  * @param  TIMx Timer instance
+  * @param  ClockSource This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CLOCKSOURCE_INTERNAL
+  *         @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE1
+  *         @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE2
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_SetClockSource(TIM_TypeDef *TIMx, uint32_t ClockSource)
+{
+  MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS | TIM_SMCR_ECE, ClockSource);
+}
+
+/**
+  * @brief  Set the encoder interface mode.
+  * @note Macro IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports the encoder mode.
+  * @rmtoll SMCR         SMS           LL_TIM_SetEncoderMode
+  * @param  TIMx Timer instance
+  * @param  EncoderMode This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_ENCODERMODE_X2_TI1
+  *         @arg @ref LL_TIM_ENCODERMODE_X2_TI2
+  *         @arg @ref LL_TIM_ENCODERMODE_X4_TI12
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_SetEncoderMode(TIM_TypeDef *TIMx, uint32_t EncoderMode)
+{
+  MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, EncoderMode);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EF_Timer_Synchronization Timer synchronisation configuration
+  * @{
+  */
+/**
+  * @brief  Set the trigger output (TRGO) used for timer synchronization .
+  * @note Macro IS_TIM_MASTER_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance can operate as a master timer.
+  * @rmtoll CR2          MMS           LL_TIM_SetTriggerOutput
+  * @param  TIMx Timer instance
+  * @param  TimerSynchronization This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_TRGO_RESET
+  *         @arg @ref LL_TIM_TRGO_ENABLE
+  *         @arg @ref LL_TIM_TRGO_UPDATE
+  *         @arg @ref LL_TIM_TRGO_CC1IF
+  *         @arg @ref LL_TIM_TRGO_OC1REF
+  *         @arg @ref LL_TIM_TRGO_OC2REF
+  *         @arg @ref LL_TIM_TRGO_OC3REF
+  *         @arg @ref LL_TIM_TRGO_OC4REF
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_SetTriggerOutput(TIM_TypeDef *TIMx, uint32_t TimerSynchronization)
+{
+  MODIFY_REG(TIMx->CR2, TIM_CR2_MMS, TimerSynchronization);
+}
+
+/**
+  * @brief  Set the synchronization mode of a slave timer.
+  * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance can operate as a slave timer.
+  * @rmtoll SMCR         SMS           LL_TIM_SetSlaveMode
+  * @param  TIMx Timer instance
+  * @param  SlaveMode This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_SLAVEMODE_DISABLED
+  *         @arg @ref LL_TIM_SLAVEMODE_RESET
+  *         @arg @ref LL_TIM_SLAVEMODE_GATED
+  *         @arg @ref LL_TIM_SLAVEMODE_TRIGGER
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_SetSlaveMode(TIM_TypeDef *TIMx, uint32_t SlaveMode)
+{
+  MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, SlaveMode);
+}
+
+/**
+  * @brief  Set the selects the trigger input to be used to synchronize the counter.
+  * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance can operate as a slave timer.
+  * @rmtoll SMCR         TS            LL_TIM_SetTriggerInput
+  * @param  TIMx Timer instance
+  * @param  TriggerInput This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_TS_ITR0
+  *         @arg @ref LL_TIM_TS_ITR1
+  *         @arg @ref LL_TIM_TS_ITR2
+  *         @arg @ref LL_TIM_TS_ITR3
+  *         @arg @ref LL_TIM_TS_TI1F_ED
+  *         @arg @ref LL_TIM_TS_TI1FP1
+  *         @arg @ref LL_TIM_TS_TI2FP2
+  *         @arg @ref LL_TIM_TS_ETRF
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_SetTriggerInput(TIM_TypeDef *TIMx, uint32_t TriggerInput)
+{
+  MODIFY_REG(TIMx->SMCR, TIM_SMCR_TS, TriggerInput);
+}
+
+/**
+  * @brief  Enable the Master/Slave mode.
+  * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance can operate as a slave timer.
+  * @rmtoll SMCR         MSM           LL_TIM_EnableMasterSlaveMode
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableMasterSlaveMode(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->SMCR, TIM_SMCR_MSM);
+}
+
+/**
+  * @brief  Disable the Master/Slave mode.
+  * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance can operate as a slave timer.
+  * @rmtoll SMCR         MSM           LL_TIM_DisableMasterSlaveMode
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableMasterSlaveMode(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->SMCR, TIM_SMCR_MSM);
+}
+
+/**
+  * @brief Indicates whether the Master/Slave mode is enabled.
+  * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
+  * a timer instance can operate as a slave timer.
+  * @rmtoll SMCR         MSM           LL_TIM_IsEnabledMasterSlaveMode
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledMasterSlaveMode(TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->SMCR, TIM_SMCR_MSM) == (TIM_SMCR_MSM)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Configure the external trigger (ETR) input.
+  * @note Macro IS_TIM_ETR_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides an external trigger input.
+  * @rmtoll SMCR         ETP           LL_TIM_ConfigETR\n
+  *         SMCR         ETPS          LL_TIM_ConfigETR\n
+  *         SMCR         ETF           LL_TIM_ConfigETR
+  * @param  TIMx Timer instance
+  * @param  ETRPolarity This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_ETR_POLARITY_NONINVERTED
+  *         @arg @ref LL_TIM_ETR_POLARITY_INVERTED
+  * @param  ETRPrescaler This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_ETR_PRESCALER_DIV1
+  *         @arg @ref LL_TIM_ETR_PRESCALER_DIV2
+  *         @arg @ref LL_TIM_ETR_PRESCALER_DIV4
+  *         @arg @ref LL_TIM_ETR_PRESCALER_DIV8
+  * @param  ETRFilter This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_ETR_FILTER_FDIV1
+  *         @arg @ref LL_TIM_ETR_FILTER_FDIV1_N2
+  *         @arg @ref LL_TIM_ETR_FILTER_FDIV1_N4
+  *         @arg @ref LL_TIM_ETR_FILTER_FDIV1_N8
+  *         @arg @ref LL_TIM_ETR_FILTER_FDIV2_N6
+  *         @arg @ref LL_TIM_ETR_FILTER_FDIV2_N8
+  *         @arg @ref LL_TIM_ETR_FILTER_FDIV4_N6
+  *         @arg @ref LL_TIM_ETR_FILTER_FDIV4_N8
+  *         @arg @ref LL_TIM_ETR_FILTER_FDIV8_N6
+  *         @arg @ref LL_TIM_ETR_FILTER_FDIV8_N8
+  *         @arg @ref LL_TIM_ETR_FILTER_FDIV16_N5
+  *         @arg @ref LL_TIM_ETR_FILTER_FDIV16_N6
+  *         @arg @ref LL_TIM_ETR_FILTER_FDIV16_N8
+  *         @arg @ref LL_TIM_ETR_FILTER_FDIV32_N5
+  *         @arg @ref LL_TIM_ETR_FILTER_FDIV32_N6
+  *         @arg @ref LL_TIM_ETR_FILTER_FDIV32_N8
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_ConfigETR(TIM_TypeDef *TIMx, uint32_t ETRPolarity, uint32_t ETRPrescaler,
+                                      uint32_t ETRFilter)
+{
+  MODIFY_REG(TIMx->SMCR, TIM_SMCR_ETP | TIM_SMCR_ETPS | TIM_SMCR_ETF, ETRPolarity | ETRPrescaler | ETRFilter);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EF_Break_Function Break function configuration
+  * @{
+  */
+/**
+  * @brief  Enable the break function.
+  * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides a break input.
+  * @rmtoll BDTR         BKE           LL_TIM_EnableBRK
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableBRK(TIM_TypeDef *TIMx)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(TIMx->BDTR, TIM_BDTR_BKE);
+  /* Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. */
+  tmpreg = READ_REG(TIMx->BDTR);
+  (void)(tmpreg);
+}
+
+/**
+  * @brief  Disable the break function.
+  * @rmtoll BDTR         BKE           LL_TIM_DisableBRK
+  * @param  TIMx Timer instance
+  * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides a break input.
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableBRK(TIM_TypeDef *TIMx)
+{
+  __IO uint32_t tmpreg;
+  CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BKE);
+  /* Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. */
+  tmpreg = READ_REG(TIMx->BDTR);
+  (void)(tmpreg);
+}
+
+/**
+  * @brief  Configure the break input.
+  * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides a break input.
+  * @rmtoll BDTR         BKP           LL_TIM_ConfigBRK
+  * @param  TIMx Timer instance
+  * @param  BreakPolarity This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_BREAK_POLARITY_LOW
+  *         @arg @ref LL_TIM_BREAK_POLARITY_HIGH
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_ConfigBRK(TIM_TypeDef *TIMx, uint32_t BreakPolarity)
+{
+  __IO uint32_t tmpreg;
+  MODIFY_REG(TIMx->BDTR, TIM_BDTR_BKP, BreakPolarity);
+  /* Note: Any write operation to BKP bit takes a delay of 1 APB clock cycle to become effective. */
+  tmpreg = READ_REG(TIMx->BDTR);
+  (void)(tmpreg);
+}
+
+/**
+  * @brief  Select the outputs off state (enabled v.s. disabled) in Idle and Run modes.
+  * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides a break input.
+  * @rmtoll BDTR         OSSI          LL_TIM_SetOffStates\n
+  *         BDTR         OSSR          LL_TIM_SetOffStates
+  * @param  TIMx Timer instance
+  * @param  OffStateIdle This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_OSSI_DISABLE
+  *         @arg @ref LL_TIM_OSSI_ENABLE
+  * @param  OffStateRun This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_OSSR_DISABLE
+  *         @arg @ref LL_TIM_OSSR_ENABLE
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_SetOffStates(TIM_TypeDef *TIMx, uint32_t OffStateIdle, uint32_t OffStateRun)
+{
+  MODIFY_REG(TIMx->BDTR, TIM_BDTR_OSSI | TIM_BDTR_OSSR, OffStateIdle | OffStateRun);
+}
+
+/**
+  * @brief  Enable automatic output (MOE can be set by software or automatically when a break input is active).
+  * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides a break input.
+  * @rmtoll BDTR         AOE           LL_TIM_EnableAutomaticOutput
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableAutomaticOutput(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->BDTR, TIM_BDTR_AOE);
+}
+
+/**
+  * @brief  Disable automatic output (MOE can be set only by software).
+  * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides a break input.
+  * @rmtoll BDTR         AOE           LL_TIM_DisableAutomaticOutput
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableAutomaticOutput(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->BDTR, TIM_BDTR_AOE);
+}
+
+/**
+  * @brief  Indicate whether automatic output is enabled.
+  * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides a break input.
+  * @rmtoll BDTR         AOE           LL_TIM_IsEnabledAutomaticOutput
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledAutomaticOutput(TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->BDTR, TIM_BDTR_AOE) == (TIM_BDTR_AOE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable the outputs (set the MOE bit in TIMx_BDTR register).
+  * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by
+  *       software and is reset in case of break or break2 event
+  * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides a break input.
+  * @rmtoll BDTR         MOE           LL_TIM_EnableAllOutputs
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableAllOutputs(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->BDTR, TIM_BDTR_MOE);
+}
+
+/**
+  * @brief  Disable the outputs (reset the MOE bit in TIMx_BDTR register).
+  * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by
+  *       software and is reset in case of break or break2 event.
+  * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides a break input.
+  * @rmtoll BDTR         MOE           LL_TIM_DisableAllOutputs
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableAllOutputs(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->BDTR, TIM_BDTR_MOE);
+}
+
+/**
+  * @brief  Indicates whether outputs are enabled.
+  * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides a break input.
+  * @rmtoll BDTR         MOE           LL_TIM_IsEnabledAllOutputs
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledAllOutputs(TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->BDTR, TIM_BDTR_MOE) == (TIM_BDTR_MOE)) ? 1UL : 0UL);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EF_DMA_Burst_Mode DMA burst mode configuration
+  * @{
+  */
+/**
+  * @brief  Configures the timer DMA burst feature.
+  * @note Macro IS_TIM_DMABURST_INSTANCE(TIMx) can be used to check whether or
+  *       not a timer instance supports the DMA burst mode.
+  * @rmtoll DCR          DBL           LL_TIM_ConfigDMABurst\n
+  *         DCR          DBA           LL_TIM_ConfigDMABurst
+  * @param  TIMx Timer instance
+  * @param  DMABurstBaseAddress This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_CR1
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_CR2
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_SMCR
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_DIER
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_SR
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_EGR
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR1
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR2
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCER
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_CNT
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_PSC
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_ARR
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_RCR
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCR1
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCR2
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCR3
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCR4
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_BDTR
+  * @param  DMABurstLength This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_DMABURST_LENGTH_1TRANSFER
+  *         @arg @ref LL_TIM_DMABURST_LENGTH_2TRANSFERS
+  *         @arg @ref LL_TIM_DMABURST_LENGTH_3TRANSFERS
+  *         @arg @ref LL_TIM_DMABURST_LENGTH_4TRANSFERS
+  *         @arg @ref LL_TIM_DMABURST_LENGTH_5TRANSFERS
+  *         @arg @ref LL_TIM_DMABURST_LENGTH_6TRANSFERS
+  *         @arg @ref LL_TIM_DMABURST_LENGTH_7TRANSFERS
+  *         @arg @ref LL_TIM_DMABURST_LENGTH_8TRANSFERS
+  *         @arg @ref LL_TIM_DMABURST_LENGTH_9TRANSFERS
+  *         @arg @ref LL_TIM_DMABURST_LENGTH_10TRANSFERS
+  *         @arg @ref LL_TIM_DMABURST_LENGTH_11TRANSFERS
+  *         @arg @ref LL_TIM_DMABURST_LENGTH_12TRANSFERS
+  *         @arg @ref LL_TIM_DMABURST_LENGTH_13TRANSFERS
+  *         @arg @ref LL_TIM_DMABURST_LENGTH_14TRANSFERS
+  *         @arg @ref LL_TIM_DMABURST_LENGTH_15TRANSFERS
+  *         @arg @ref LL_TIM_DMABURST_LENGTH_16TRANSFERS
+  *         @arg @ref LL_TIM_DMABURST_LENGTH_17TRANSFERS
+  *         @arg @ref LL_TIM_DMABURST_LENGTH_18TRANSFERS
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_ConfigDMABurst(TIM_TypeDef *TIMx, uint32_t DMABurstBaseAddress, uint32_t DMABurstLength)
+{
+  MODIFY_REG(TIMx->DCR, (TIM_DCR_DBL | TIM_DCR_DBA), (DMABurstBaseAddress | DMABurstLength));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EF_Timer_Inputs_Remapping Timer input remapping
+  * @{
+  */
+/**
+  * @brief  Remap TIM inputs (input channel, internal/external triggers).
+  * @note Macro IS_TIM_REMAP_INSTANCE(TIMx) can be used to check whether or not
+  *       a some timer inputs can be remapped.
+  * @rmtoll TIM1_OR     ITR2_RMP          LL_TIM_SetRemap\n
+  *         TIM2_OR     ITR1_RMP          LL_TIM_SetRemap\n
+  *         TIM5_OR     ITR1_RMP          LL_TIM_SetRemap\n
+  *         TIM5_OR     TI4_RMP           LL_TIM_SetRemap\n
+  *         TIM9_OR     ITR1_RMP          LL_TIM_SetRemap\n
+  *         TIM11_OR    TI1_RMP           LL_TIM_SetRemap\n
+  *         LPTIM1_OR   OR                LL_TIM_SetRemap
+  * @param  TIMx Timer instance
+  * @param  Remap Remap param depends on the TIMx. Description available only
+  *         in CHM version of the User Manual (not in .pdf).
+  *         Otherwise see Reference Manual description of OR registers.
+  *
+  *         Below description summarizes "Timer Instance" and "Remap" param combinations:
+  *
+  *         TIM1: one of the following values
+  *
+  *            ITR2_RMP can be one of the following values
+  *            @arg @ref LL_TIM_TIM1_ITR2_RMP_TIM3_TRGO (*)
+  *            @arg @ref LL_TIM_TIM1_ITR2_RMP_LPTIM (*)
+  *
+  *         TIM2: one of the following values
+  *
+  *            ITR1_RMP can be one of the following values
+  *            @arg @ref LL_TIM_TIM2_ITR1_RMP_TIM8_TRGO
+  *            @arg @ref LL_TIM_TIM2_ITR1_RMP_OTG_FS_SOF
+  *            @arg @ref LL_TIM_TIM2_ITR1_RMP_OTG_HS_SOF
+  *
+  *         TIM5: one of the following values
+  *
+  *            @arg @ref LL_TIM_TIM5_TI4_RMP_GPIO
+  *            @arg @ref LL_TIM_TIM5_TI4_RMP_LSI
+  *            @arg @ref LL_TIM_TIM5_TI4_RMP_LSE
+  *            @arg @ref LL_TIM_TIM5_TI4_RMP_RTC
+  *            @arg @ref LL_TIM_TIM5_ITR1_RMP_TIM3_TRGO (*)
+  *            @arg @ref LL_TIM_TIM5_ITR1_RMP_LPTIM (*)
+  *
+  *         TIM9: one of the following values
+  *
+  *            ITR1_RMP can be one of the following values
+  *            @arg @ref LL_TIM_TIM9_ITR1_RMP_TIM3_TRGO (*)
+  *            @arg @ref LL_TIM_TIM9_ITR1_RMP_LPTIM (*)
+  *
+  *         TIM11: one of the following values
+  *
+  *            @arg @ref LL_TIM_TIM11_TI1_RMP_GPIO
+  *            @arg @ref LL_TIM_TIM11_TI1_RMP_GPIO1 (*)
+  *            @arg @ref LL_TIM_TIM11_TI1_RMP_HSE_RTC
+  *            @arg @ref LL_TIM_TIM11_TI1_RMP_GPIO2
+  *            @arg @ref LL_TIM_TIM11_TI1_RMP_SPDIFRX (*)
+  *
+  *         (*)  Value not defined in all devices. \n
+  *
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_SetRemap(TIM_TypeDef *TIMx, uint32_t Remap)
+{
+#if defined(LPTIM_OR_TIM1_ITR2_RMP) && defined(LPTIM_OR_TIM5_ITR1_RMP) && defined(LPTIM_OR_TIM9_ITR1_RMP)
+  if ((Remap & LL_TIM_LPTIM_REMAP_MASK) == LL_TIM_LPTIM_REMAP_MASK)
+  {
+    /* Connect TIMx internal trigger to LPTIM1 output */
+    SET_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN);
+    MODIFY_REG(LPTIM1->OR,
+               (LPTIM_OR_TIM1_ITR2_RMP | LPTIM_OR_TIM5_ITR1_RMP | LPTIM_OR_TIM9_ITR1_RMP),
+               Remap & ~(LL_TIM_LPTIM_REMAP_MASK));
+  }
+  else
+  {
+    MODIFY_REG(TIMx->OR, (Remap >> TIMx_OR_RMP_SHIFT), (Remap & TIMx_OR_RMP_MASK));
+  }
+#else
+  MODIFY_REG(TIMx->OR, (Remap >> TIMx_OR_RMP_SHIFT), (Remap & TIMx_OR_RMP_MASK));
+#endif /* LPTIM_OR_TIM1_ITR2_RMP &&  LPTIM_OR_TIM5_ITR1_RMP && LPTIM_OR_TIM9_ITR1_RMP */
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EF_FLAG_Management FLAG-Management
+  * @{
+  */
+/**
+  * @brief  Clear the update interrupt flag (UIF).
+  * @rmtoll SR           UIF           LL_TIM_ClearFlag_UPDATE
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_ClearFlag_UPDATE(TIM_TypeDef *TIMx)
+{
+  WRITE_REG(TIMx->SR, ~(TIM_SR_UIF));
+}
+
+/**
+  * @brief  Indicate whether update interrupt flag (UIF) is set (update interrupt is pending).
+  * @rmtoll SR           UIF           LL_TIM_IsActiveFlag_UPDATE
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_UPDATE(TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->SR, TIM_SR_UIF) == (TIM_SR_UIF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Clear the Capture/Compare 1 interrupt flag (CC1F).
+  * @rmtoll SR           CC1IF         LL_TIM_ClearFlag_CC1
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_ClearFlag_CC1(TIM_TypeDef *TIMx)
+{
+  WRITE_REG(TIMx->SR, ~(TIM_SR_CC1IF));
+}
+
+/**
+  * @brief  Indicate whether Capture/Compare 1 interrupt flag (CC1F) is set (Capture/Compare 1 interrupt is pending).
+  * @rmtoll SR           CC1IF         LL_TIM_IsActiveFlag_CC1
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1(TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->SR, TIM_SR_CC1IF) == (TIM_SR_CC1IF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Clear the Capture/Compare 2 interrupt flag (CC2F).
+  * @rmtoll SR           CC2IF         LL_TIM_ClearFlag_CC2
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_ClearFlag_CC2(TIM_TypeDef *TIMx)
+{
+  WRITE_REG(TIMx->SR, ~(TIM_SR_CC2IF));
+}
+
+/**
+  * @brief  Indicate whether Capture/Compare 2 interrupt flag (CC2F) is set (Capture/Compare 2 interrupt is pending).
+  * @rmtoll SR           CC2IF         LL_TIM_IsActiveFlag_CC2
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2(TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->SR, TIM_SR_CC2IF) == (TIM_SR_CC2IF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Clear the Capture/Compare 3 interrupt flag (CC3F).
+  * @rmtoll SR           CC3IF         LL_TIM_ClearFlag_CC3
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_ClearFlag_CC3(TIM_TypeDef *TIMx)
+{
+  WRITE_REG(TIMx->SR, ~(TIM_SR_CC3IF));
+}
+
+/**
+  * @brief  Indicate whether Capture/Compare 3 interrupt flag (CC3F) is set (Capture/Compare 3 interrupt is pending).
+  * @rmtoll SR           CC3IF         LL_TIM_IsActiveFlag_CC3
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3(TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->SR, TIM_SR_CC3IF) == (TIM_SR_CC3IF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Clear the Capture/Compare 4 interrupt flag (CC4F).
+  * @rmtoll SR           CC4IF         LL_TIM_ClearFlag_CC4
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_ClearFlag_CC4(TIM_TypeDef *TIMx)
+{
+  WRITE_REG(TIMx->SR, ~(TIM_SR_CC4IF));
+}
+
+/**
+  * @brief  Indicate whether Capture/Compare 4 interrupt flag (CC4F) is set (Capture/Compare 4 interrupt is pending).
+  * @rmtoll SR           CC4IF         LL_TIM_IsActiveFlag_CC4
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4(TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->SR, TIM_SR_CC4IF) == (TIM_SR_CC4IF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Clear the commutation interrupt flag (COMIF).
+  * @rmtoll SR           COMIF         LL_TIM_ClearFlag_COM
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_ClearFlag_COM(TIM_TypeDef *TIMx)
+{
+  WRITE_REG(TIMx->SR, ~(TIM_SR_COMIF));
+}
+
+/**
+  * @brief  Indicate whether commutation interrupt flag (COMIF) is set (commutation interrupt is pending).
+  * @rmtoll SR           COMIF         LL_TIM_IsActiveFlag_COM
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_COM(TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->SR, TIM_SR_COMIF) == (TIM_SR_COMIF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Clear the trigger interrupt flag (TIF).
+  * @rmtoll SR           TIF           LL_TIM_ClearFlag_TRIG
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_ClearFlag_TRIG(TIM_TypeDef *TIMx)
+{
+  WRITE_REG(TIMx->SR, ~(TIM_SR_TIF));
+}
+
+/**
+  * @brief  Indicate whether trigger interrupt flag (TIF) is set (trigger interrupt is pending).
+  * @rmtoll SR           TIF           LL_TIM_IsActiveFlag_TRIG
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TRIG(TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->SR, TIM_SR_TIF) == (TIM_SR_TIF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Clear the break interrupt flag (BIF).
+  * @rmtoll SR           BIF           LL_TIM_ClearFlag_BRK
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_ClearFlag_BRK(TIM_TypeDef *TIMx)
+{
+  WRITE_REG(TIMx->SR, ~(TIM_SR_BIF));
+}
+
+/**
+  * @brief  Indicate whether break interrupt flag (BIF) is set (break interrupt is pending).
+  * @rmtoll SR           BIF           LL_TIM_IsActiveFlag_BRK
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK(TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->SR, TIM_SR_BIF) == (TIM_SR_BIF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Clear the Capture/Compare 1 over-capture interrupt flag (CC1OF).
+  * @rmtoll SR           CC1OF         LL_TIM_ClearFlag_CC1OVR
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_ClearFlag_CC1OVR(TIM_TypeDef *TIMx)
+{
+  WRITE_REG(TIMx->SR, ~(TIM_SR_CC1OF));
+}
+
+/**
+  * @brief  Indicate whether Capture/Compare 1 over-capture interrupt flag (CC1OF) is set
+  *         (Capture/Compare 1 interrupt is pending).
+  * @rmtoll SR           CC1OF         LL_TIM_IsActiveFlag_CC1OVR
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1OVR(TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->SR, TIM_SR_CC1OF) == (TIM_SR_CC1OF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Clear the Capture/Compare 2 over-capture interrupt flag (CC2OF).
+  * @rmtoll SR           CC2OF         LL_TIM_ClearFlag_CC2OVR
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_ClearFlag_CC2OVR(TIM_TypeDef *TIMx)
+{
+  WRITE_REG(TIMx->SR, ~(TIM_SR_CC2OF));
+}
+
+/**
+  * @brief  Indicate whether Capture/Compare 2 over-capture interrupt flag (CC2OF) is set
+  *         (Capture/Compare 2 over-capture interrupt is pending).
+  * @rmtoll SR           CC2OF         LL_TIM_IsActiveFlag_CC2OVR
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2OVR(TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->SR, TIM_SR_CC2OF) == (TIM_SR_CC2OF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Clear the Capture/Compare 3 over-capture interrupt flag (CC3OF).
+  * @rmtoll SR           CC3OF         LL_TIM_ClearFlag_CC3OVR
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_ClearFlag_CC3OVR(TIM_TypeDef *TIMx)
+{
+  WRITE_REG(TIMx->SR, ~(TIM_SR_CC3OF));
+}
+
+/**
+  * @brief  Indicate whether Capture/Compare 3 over-capture interrupt flag (CC3OF) is set
+  *         (Capture/Compare 3 over-capture interrupt is pending).
+  * @rmtoll SR           CC3OF         LL_TIM_IsActiveFlag_CC3OVR
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3OVR(TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->SR, TIM_SR_CC3OF) == (TIM_SR_CC3OF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Clear the Capture/Compare 4 over-capture interrupt flag (CC4OF).
+  * @rmtoll SR           CC4OF         LL_TIM_ClearFlag_CC4OVR
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_ClearFlag_CC4OVR(TIM_TypeDef *TIMx)
+{
+  WRITE_REG(TIMx->SR, ~(TIM_SR_CC4OF));
+}
+
+/**
+  * @brief  Indicate whether Capture/Compare 4 over-capture interrupt flag (CC4OF) is set
+  *         (Capture/Compare 4 over-capture interrupt is pending).
+  * @rmtoll SR           CC4OF         LL_TIM_IsActiveFlag_CC4OVR
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4OVR(TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->SR, TIM_SR_CC4OF) == (TIM_SR_CC4OF)) ? 1UL : 0UL);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EF_IT_Management IT-Management
+  * @{
+  */
+/**
+  * @brief  Enable update interrupt (UIE).
+  * @rmtoll DIER         UIE           LL_TIM_EnableIT_UPDATE
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableIT_UPDATE(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->DIER, TIM_DIER_UIE);
+}
+
+/**
+  * @brief  Disable update interrupt (UIE).
+  * @rmtoll DIER         UIE           LL_TIM_DisableIT_UPDATE
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableIT_UPDATE(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->DIER, TIM_DIER_UIE);
+}
+
+/**
+  * @brief  Indicates whether the update interrupt (UIE) is enabled.
+  * @rmtoll DIER         UIE           LL_TIM_IsEnabledIT_UPDATE
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_UPDATE(TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->DIER, TIM_DIER_UIE) == (TIM_DIER_UIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable capture/compare 1 interrupt (CC1IE).
+  * @rmtoll DIER         CC1IE         LL_TIM_EnableIT_CC1
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableIT_CC1(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->DIER, TIM_DIER_CC1IE);
+}
+
+/**
+  * @brief  Disable capture/compare 1  interrupt (CC1IE).
+  * @rmtoll DIER         CC1IE         LL_TIM_DisableIT_CC1
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableIT_CC1(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1IE);
+}
+
+/**
+  * @brief  Indicates whether the capture/compare 1 interrupt (CC1IE) is enabled.
+  * @rmtoll DIER         CC1IE         LL_TIM_IsEnabledIT_CC1
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC1(TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1IE) == (TIM_DIER_CC1IE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable capture/compare 2 interrupt (CC2IE).
+  * @rmtoll DIER         CC2IE         LL_TIM_EnableIT_CC2
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableIT_CC2(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->DIER, TIM_DIER_CC2IE);
+}
+
+/**
+  * @brief  Disable capture/compare 2  interrupt (CC2IE).
+  * @rmtoll DIER         CC2IE         LL_TIM_DisableIT_CC2
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableIT_CC2(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2IE);
+}
+
+/**
+  * @brief  Indicates whether the capture/compare 2 interrupt (CC2IE) is enabled.
+  * @rmtoll DIER         CC2IE         LL_TIM_IsEnabledIT_CC2
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC2(TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2IE) == (TIM_DIER_CC2IE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable capture/compare 3 interrupt (CC3IE).
+  * @rmtoll DIER         CC3IE         LL_TIM_EnableIT_CC3
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableIT_CC3(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->DIER, TIM_DIER_CC3IE);
+}
+
+/**
+  * @brief  Disable capture/compare 3  interrupt (CC3IE).
+  * @rmtoll DIER         CC3IE         LL_TIM_DisableIT_CC3
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableIT_CC3(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3IE);
+}
+
+/**
+  * @brief  Indicates whether the capture/compare 3 interrupt (CC3IE) is enabled.
+  * @rmtoll DIER         CC3IE         LL_TIM_IsEnabledIT_CC3
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC3(TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3IE) == (TIM_DIER_CC3IE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable capture/compare 4 interrupt (CC4IE).
+  * @rmtoll DIER         CC4IE         LL_TIM_EnableIT_CC4
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableIT_CC4(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->DIER, TIM_DIER_CC4IE);
+}
+
+/**
+  * @brief  Disable capture/compare 4  interrupt (CC4IE).
+  * @rmtoll DIER         CC4IE         LL_TIM_DisableIT_CC4
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableIT_CC4(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4IE);
+}
+
+/**
+  * @brief  Indicates whether the capture/compare 4 interrupt (CC4IE) is enabled.
+  * @rmtoll DIER         CC4IE         LL_TIM_IsEnabledIT_CC4
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC4(TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4IE) == (TIM_DIER_CC4IE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable commutation interrupt (COMIE).
+  * @rmtoll DIER         COMIE         LL_TIM_EnableIT_COM
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableIT_COM(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->DIER, TIM_DIER_COMIE);
+}
+
+/**
+  * @brief  Disable commutation interrupt (COMIE).
+  * @rmtoll DIER         COMIE         LL_TIM_DisableIT_COM
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableIT_COM(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->DIER, TIM_DIER_COMIE);
+}
+
+/**
+  * @brief  Indicates whether the commutation interrupt (COMIE) is enabled.
+  * @rmtoll DIER         COMIE         LL_TIM_IsEnabledIT_COM
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_COM(TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->DIER, TIM_DIER_COMIE) == (TIM_DIER_COMIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable trigger interrupt (TIE).
+  * @rmtoll DIER         TIE           LL_TIM_EnableIT_TRIG
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableIT_TRIG(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->DIER, TIM_DIER_TIE);
+}
+
+/**
+  * @brief  Disable trigger interrupt (TIE).
+  * @rmtoll DIER         TIE           LL_TIM_DisableIT_TRIG
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableIT_TRIG(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->DIER, TIM_DIER_TIE);
+}
+
+/**
+  * @brief  Indicates whether the trigger interrupt (TIE) is enabled.
+  * @rmtoll DIER         TIE           LL_TIM_IsEnabledIT_TRIG
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_TRIG(TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->DIER, TIM_DIER_TIE) == (TIM_DIER_TIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable break interrupt (BIE).
+  * @rmtoll DIER         BIE           LL_TIM_EnableIT_BRK
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableIT_BRK(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->DIER, TIM_DIER_BIE);
+}
+
+/**
+  * @brief  Disable break interrupt (BIE).
+  * @rmtoll DIER         BIE           LL_TIM_DisableIT_BRK
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableIT_BRK(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->DIER, TIM_DIER_BIE);
+}
+
+/**
+  * @brief  Indicates whether the break interrupt (BIE) is enabled.
+  * @rmtoll DIER         BIE           LL_TIM_IsEnabledIT_BRK
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_BRK(TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->DIER, TIM_DIER_BIE) == (TIM_DIER_BIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EF_DMA_Management DMA Management
+  * @{
+  */
+/**
+  * @brief  Enable update DMA request (UDE).
+  * @rmtoll DIER         UDE           LL_TIM_EnableDMAReq_UPDATE
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableDMAReq_UPDATE(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->DIER, TIM_DIER_UDE);
+}
+
+/**
+  * @brief  Disable update DMA request (UDE).
+  * @rmtoll DIER         UDE           LL_TIM_DisableDMAReq_UPDATE
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableDMAReq_UPDATE(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->DIER, TIM_DIER_UDE);
+}
+
+/**
+  * @brief  Indicates whether the update DMA request  (UDE) is enabled.
+  * @rmtoll DIER         UDE           LL_TIM_IsEnabledDMAReq_UPDATE
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_UPDATE(TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->DIER, TIM_DIER_UDE) == (TIM_DIER_UDE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable capture/compare 1 DMA request (CC1DE).
+  * @rmtoll DIER         CC1DE         LL_TIM_EnableDMAReq_CC1
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableDMAReq_CC1(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->DIER, TIM_DIER_CC1DE);
+}
+
+/**
+  * @brief  Disable capture/compare 1  DMA request (CC1DE).
+  * @rmtoll DIER         CC1DE         LL_TIM_DisableDMAReq_CC1
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableDMAReq_CC1(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1DE);
+}
+
+/**
+  * @brief  Indicates whether the capture/compare 1 DMA request (CC1DE) is enabled.
+  * @rmtoll DIER         CC1DE         LL_TIM_IsEnabledDMAReq_CC1
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC1(TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1DE) == (TIM_DIER_CC1DE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable capture/compare 2 DMA request (CC2DE).
+  * @rmtoll DIER         CC2DE         LL_TIM_EnableDMAReq_CC2
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableDMAReq_CC2(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->DIER, TIM_DIER_CC2DE);
+}
+
+/**
+  * @brief  Disable capture/compare 2  DMA request (CC2DE).
+  * @rmtoll DIER         CC2DE         LL_TIM_DisableDMAReq_CC2
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableDMAReq_CC2(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2DE);
+}
+
+/**
+  * @brief  Indicates whether the capture/compare 2 DMA request (CC2DE) is enabled.
+  * @rmtoll DIER         CC2DE         LL_TIM_IsEnabledDMAReq_CC2
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC2(TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2DE) == (TIM_DIER_CC2DE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable capture/compare 3 DMA request (CC3DE).
+  * @rmtoll DIER         CC3DE         LL_TIM_EnableDMAReq_CC3
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableDMAReq_CC3(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->DIER, TIM_DIER_CC3DE);
+}
+
+/**
+  * @brief  Disable capture/compare 3  DMA request (CC3DE).
+  * @rmtoll DIER         CC3DE         LL_TIM_DisableDMAReq_CC3
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableDMAReq_CC3(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3DE);
+}
+
+/**
+  * @brief  Indicates whether the capture/compare 3 DMA request (CC3DE) is enabled.
+  * @rmtoll DIER         CC3DE         LL_TIM_IsEnabledDMAReq_CC3
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC3(TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3DE) == (TIM_DIER_CC3DE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable capture/compare 4 DMA request (CC4DE).
+  * @rmtoll DIER         CC4DE         LL_TIM_EnableDMAReq_CC4
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableDMAReq_CC4(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->DIER, TIM_DIER_CC4DE);
+}
+
+/**
+  * @brief  Disable capture/compare 4  DMA request (CC4DE).
+  * @rmtoll DIER         CC4DE         LL_TIM_DisableDMAReq_CC4
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableDMAReq_CC4(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4DE);
+}
+
+/**
+  * @brief  Indicates whether the capture/compare 4 DMA request (CC4DE) is enabled.
+  * @rmtoll DIER         CC4DE         LL_TIM_IsEnabledDMAReq_CC4
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC4(TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4DE) == (TIM_DIER_CC4DE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable commutation DMA request (COMDE).
+  * @rmtoll DIER         COMDE         LL_TIM_EnableDMAReq_COM
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableDMAReq_COM(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->DIER, TIM_DIER_COMDE);
+}
+
+/**
+  * @brief  Disable commutation DMA request (COMDE).
+  * @rmtoll DIER         COMDE         LL_TIM_DisableDMAReq_COM
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableDMAReq_COM(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->DIER, TIM_DIER_COMDE);
+}
+
+/**
+  * @brief  Indicates whether the commutation DMA request (COMDE) is enabled.
+  * @rmtoll DIER         COMDE         LL_TIM_IsEnabledDMAReq_COM
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_COM(TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->DIER, TIM_DIER_COMDE) == (TIM_DIER_COMDE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable trigger interrupt (TDE).
+  * @rmtoll DIER         TDE           LL_TIM_EnableDMAReq_TRIG
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableDMAReq_TRIG(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->DIER, TIM_DIER_TDE);
+}
+
+/**
+  * @brief  Disable trigger interrupt (TDE).
+  * @rmtoll DIER         TDE           LL_TIM_DisableDMAReq_TRIG
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableDMAReq_TRIG(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->DIER, TIM_DIER_TDE);
+}
+
+/**
+  * @brief  Indicates whether the trigger interrupt (TDE) is enabled.
+  * @rmtoll DIER         TDE           LL_TIM_IsEnabledDMAReq_TRIG
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_TRIG(TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->DIER, TIM_DIER_TDE) == (TIM_DIER_TDE)) ? 1UL : 0UL);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EF_EVENT_Management EVENT-Management
+  * @{
+  */
+/**
+  * @brief  Generate an update event.
+  * @rmtoll EGR          UG            LL_TIM_GenerateEvent_UPDATE
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_GenerateEvent_UPDATE(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->EGR, TIM_EGR_UG);
+}
+
+/**
+  * @brief  Generate Capture/Compare 1 event.
+  * @rmtoll EGR          CC1G          LL_TIM_GenerateEvent_CC1
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_GenerateEvent_CC1(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->EGR, TIM_EGR_CC1G);
+}
+
+/**
+  * @brief  Generate Capture/Compare 2 event.
+  * @rmtoll EGR          CC2G          LL_TIM_GenerateEvent_CC2
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_GenerateEvent_CC2(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->EGR, TIM_EGR_CC2G);
+}
+
+/**
+  * @brief  Generate Capture/Compare 3 event.
+  * @rmtoll EGR          CC3G          LL_TIM_GenerateEvent_CC3
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_GenerateEvent_CC3(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->EGR, TIM_EGR_CC3G);
+}
+
+/**
+  * @brief  Generate Capture/Compare 4 event.
+  * @rmtoll EGR          CC4G          LL_TIM_GenerateEvent_CC4
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_GenerateEvent_CC4(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->EGR, TIM_EGR_CC4G);
+}
+
+/**
+  * @brief  Generate commutation event.
+  * @rmtoll EGR          COMG          LL_TIM_GenerateEvent_COM
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_GenerateEvent_COM(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->EGR, TIM_EGR_COMG);
+}
+
+/**
+  * @brief  Generate trigger event.
+  * @rmtoll EGR          TG            LL_TIM_GenerateEvent_TRIG
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_GenerateEvent_TRIG(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->EGR, TIM_EGR_TG);
+}
+
+/**
+  * @brief  Generate break event.
+  * @rmtoll EGR          BG            LL_TIM_GenerateEvent_BRK
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_GenerateEvent_BRK(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->EGR, TIM_EGR_BG);
+}
+
+/**
+  * @}
+  */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup TIM_LL_EF_Init Initialisation and deinitialisation functions
+  * @{
+  */
+
+ErrorStatus LL_TIM_DeInit(TIM_TypeDef *TIMx);
+void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct);
+ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, LL_TIM_InitTypeDef *TIM_InitStruct);
+void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct);
+ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct);
+void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
+ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct);
+void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct);
+ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct);
+void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct);
+ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct);
+void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct);
+ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct);
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* TIM1 || TIM2 || TIM3 || TIM4 || TIM5 || TIM6 || TIM7 || TIM8 || TIM9 || TIM10 || TIM11 || TIM12 || TIM13 || TIM14 */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_LL_TIM_H */
diff --git a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usart.h b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usart.h
new file mode 100644
index 0000000..64f59b0
--- /dev/null
+++ b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usart.h
@@ -0,0 +1,2521 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_ll_usart.h
+  * @author  MCD Application Team
+  * @brief   Header file of USART LL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2016 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_LL_USART_H
+#define __STM32F4xx_LL_USART_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx.h"
+
+/** @addtogroup STM32F4xx_LL_Driver
+  * @{
+  */
+
+#if defined (USART1) || defined (USART2) || defined (USART3) || defined (USART6) || defined (UART4) || defined (UART5) || defined (UART7) || defined (UART8) || defined (UART9) || defined (UART10)
+
+/** @defgroup USART_LL USART
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup USART_LL_Private_Constants USART Private Constants
+  * @{
+  */
+
+/* Defines used for the bit position in the register and perform offsets*/
+#define USART_POSITION_GTPR_GT                  USART_GTPR_GT_Pos
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup USART_LL_Private_Macros USART Private Macros
+  * @{
+  */
+/**
+  * @}
+  */
+#endif /*USE_FULL_LL_DRIVER*/
+
+/* Exported types ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup USART_LL_ES_INIT USART Exported Init structures
+  * @{
+  */
+
+/**
+  * @brief LL USART Init Structure definition
+  */
+typedef struct
+{
+  uint32_t BaudRate;                  /*!< This field defines expected Usart communication baud rate.
+
+                                           This feature can be modified afterwards using unitary function @ref LL_USART_SetBaudRate().*/
+
+  uint32_t DataWidth;                 /*!< Specifies the number of data bits transmitted or received in a frame.
+                                           This parameter can be a value of @ref USART_LL_EC_DATAWIDTH.
+
+                                           This feature can be modified afterwards using unitary function @ref LL_USART_SetDataWidth().*/
+
+  uint32_t StopBits;                  /*!< Specifies the number of stop bits transmitted.
+                                           This parameter can be a value of @ref USART_LL_EC_STOPBITS.
+
+                                           This feature can be modified afterwards using unitary function @ref LL_USART_SetStopBitsLength().*/
+
+  uint32_t Parity;                    /*!< Specifies the parity mode.
+                                           This parameter can be a value of @ref USART_LL_EC_PARITY.
+
+                                           This feature can be modified afterwards using unitary function @ref LL_USART_SetParity().*/
+
+  uint32_t TransferDirection;         /*!< Specifies whether the Receive and/or Transmit mode is enabled or disabled.
+                                           This parameter can be a value of @ref USART_LL_EC_DIRECTION.
+
+                                           This feature can be modified afterwards using unitary function @ref LL_USART_SetTransferDirection().*/
+
+  uint32_t HardwareFlowControl;       /*!< Specifies whether the hardware flow control mode is enabled or disabled.
+                                           This parameter can be a value of @ref USART_LL_EC_HWCONTROL.
+
+                                           This feature can be modified afterwards using unitary function @ref LL_USART_SetHWFlowCtrl().*/
+
+  uint32_t OverSampling;              /*!< Specifies whether USART oversampling mode is 16 or 8.
+                                           This parameter can be a value of @ref USART_LL_EC_OVERSAMPLING.
+
+                                           This feature can be modified afterwards using unitary function @ref LL_USART_SetOverSampling().*/
+
+} LL_USART_InitTypeDef;
+
+/**
+  * @brief LL USART Clock Init Structure definition
+  */
+typedef struct
+{
+  uint32_t ClockOutput;               /*!< Specifies whether the USART clock is enabled or disabled.
+                                           This parameter can be a value of @ref USART_LL_EC_CLOCK.
+
+                                           USART HW configuration can be modified afterwards using unitary functions
+                                           @ref LL_USART_EnableSCLKOutput() or @ref LL_USART_DisableSCLKOutput().
+                                           For more details, refer to description of this function. */
+
+  uint32_t ClockPolarity;             /*!< Specifies the steady state of the serial clock.
+                                           This parameter can be a value of @ref USART_LL_EC_POLARITY.
+
+                                           USART HW configuration can be modified afterwards using unitary functions @ref LL_USART_SetClockPolarity().
+                                           For more details, refer to description of this function. */
+
+  uint32_t ClockPhase;                /*!< Specifies the clock transition on which the bit capture is made.
+                                           This parameter can be a value of @ref USART_LL_EC_PHASE.
+
+                                           USART HW configuration can be modified afterwards using unitary functions @ref LL_USART_SetClockPhase().
+                                           For more details, refer to description of this function. */
+
+  uint32_t LastBitClockPulse;         /*!< Specifies whether the clock pulse corresponding to the last transmitted
+                                           data bit (MSB) has to be output on the SCLK pin in synchronous mode.
+                                           This parameter can be a value of @ref USART_LL_EC_LASTCLKPULSE.
+
+                                           USART HW configuration can be modified afterwards using unitary functions @ref LL_USART_SetLastClkPulseOutput().
+                                           For more details, refer to description of this function. */
+
+} LL_USART_ClockInitTypeDef;
+
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup USART_LL_Exported_Constants USART Exported Constants
+  * @{
+  */
+
+/** @defgroup USART_LL_EC_GET_FLAG Get Flags Defines
+  * @brief    Flags defines which can be used with LL_USART_ReadReg function
+  * @{
+  */
+#define LL_USART_SR_PE                          USART_SR_PE                   /*!< Parity error flag */
+#define LL_USART_SR_FE                          USART_SR_FE                   /*!< Framing error flag */
+#define LL_USART_SR_NE                          USART_SR_NE                   /*!< Noise detected flag */
+#define LL_USART_SR_ORE                         USART_SR_ORE                  /*!< Overrun error flag */
+#define LL_USART_SR_IDLE                        USART_SR_IDLE                 /*!< Idle line detected flag */
+#define LL_USART_SR_RXNE                        USART_SR_RXNE                 /*!< Read data register not empty flag */
+#define LL_USART_SR_TC                          USART_SR_TC                   /*!< Transmission complete flag */
+#define LL_USART_SR_TXE                         USART_SR_TXE                  /*!< Transmit data register empty flag */
+#define LL_USART_SR_LBD                         USART_SR_LBD                  /*!< LIN break detection flag */
+#define LL_USART_SR_CTS                         USART_SR_CTS                  /*!< CTS flag */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_IT IT Defines
+  * @brief    IT defines which can be used with LL_USART_ReadReg and  LL_USART_WriteReg functions
+  * @{
+  */
+#define LL_USART_CR1_IDLEIE                     USART_CR1_IDLEIE              /*!< IDLE interrupt enable */
+#define LL_USART_CR1_RXNEIE                     USART_CR1_RXNEIE              /*!< Read data register not empty interrupt enable */
+#define LL_USART_CR1_TCIE                       USART_CR1_TCIE                /*!< Transmission complete interrupt enable */
+#define LL_USART_CR1_TXEIE                      USART_CR1_TXEIE               /*!< Transmit data register empty interrupt enable */
+#define LL_USART_CR1_PEIE                       USART_CR1_PEIE                /*!< Parity error */
+#define LL_USART_CR2_LBDIE                      USART_CR2_LBDIE               /*!< LIN break detection interrupt enable */
+#define LL_USART_CR3_EIE                        USART_CR3_EIE                 /*!< Error interrupt enable */
+#define LL_USART_CR3_CTSIE                      USART_CR3_CTSIE               /*!< CTS interrupt enable */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_DIRECTION Communication Direction
+  * @{
+  */
+#define LL_USART_DIRECTION_NONE                 0x00000000U                        /*!< Transmitter and Receiver are disabled */
+#define LL_USART_DIRECTION_RX                   USART_CR1_RE                       /*!< Transmitter is disabled and Receiver is enabled */
+#define LL_USART_DIRECTION_TX                   USART_CR1_TE                       /*!< Transmitter is enabled and Receiver is disabled */
+#define LL_USART_DIRECTION_TX_RX                (USART_CR1_TE |USART_CR1_RE)       /*!< Transmitter and Receiver are enabled */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_PARITY Parity Control
+  * @{
+  */
+#define LL_USART_PARITY_NONE                    0x00000000U                          /*!< Parity control disabled */
+#define LL_USART_PARITY_EVEN                    USART_CR1_PCE                        /*!< Parity control enabled and Even Parity is selected */
+#define LL_USART_PARITY_ODD                     (USART_CR1_PCE | USART_CR1_PS)       /*!< Parity control enabled and Odd Parity is selected */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_WAKEUP Wakeup
+  * @{
+  */
+#define LL_USART_WAKEUP_IDLELINE                0x00000000U           /*!<  USART wake up from Mute mode on Idle Line */
+#define LL_USART_WAKEUP_ADDRESSMARK             USART_CR1_WAKE        /*!<  USART wake up from Mute mode on Address Mark */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_DATAWIDTH Datawidth
+  * @{
+  */
+#define LL_USART_DATAWIDTH_8B                   0x00000000U             /*!< 8 bits word length : Start bit, 8 data bits, n stop bits */
+#define LL_USART_DATAWIDTH_9B                   USART_CR1_M             /*!< 9 bits word length : Start bit, 9 data bits, n stop bits */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_OVERSAMPLING Oversampling
+  * @{
+  */
+#define LL_USART_OVERSAMPLING_16                0x00000000U            /*!< Oversampling by 16 */
+#define LL_USART_OVERSAMPLING_8                 USART_CR1_OVER8        /*!< Oversampling by 8 */
+/**
+  * @}
+  */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup USART_LL_EC_CLOCK Clock Signal
+  * @{
+  */
+
+#define LL_USART_CLOCK_DISABLE                  0x00000000U            /*!< Clock signal not provided */
+#define LL_USART_CLOCK_ENABLE                   USART_CR2_CLKEN        /*!< Clock signal provided */
+/**
+  * @}
+  */
+#endif /*USE_FULL_LL_DRIVER*/
+
+/** @defgroup USART_LL_EC_LASTCLKPULSE Last Clock Pulse
+  * @{
+  */
+#define LL_USART_LASTCLKPULSE_NO_OUTPUT         0x00000000U           /*!< The clock pulse of the last data bit is not output to the SCLK pin */
+#define LL_USART_LASTCLKPULSE_OUTPUT            USART_CR2_LBCL        /*!< The clock pulse of the last data bit is output to the SCLK pin */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_PHASE Clock Phase
+  * @{
+  */
+#define LL_USART_PHASE_1EDGE                    0x00000000U           /*!< The first clock transition is the first data capture edge */
+#define LL_USART_PHASE_2EDGE                    USART_CR2_CPHA        /*!< The second clock transition is the first data capture edge */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_POLARITY Clock Polarity
+  * @{
+  */
+#define LL_USART_POLARITY_LOW                   0x00000000U           /*!< Steady low value on SCLK pin outside transmission window*/
+#define LL_USART_POLARITY_HIGH                  USART_CR2_CPOL        /*!< Steady high value on SCLK pin outside transmission window */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_STOPBITS Stop Bits
+  * @{
+  */
+#define LL_USART_STOPBITS_0_5                   USART_CR2_STOP_0                           /*!< 0.5 stop bit */
+#define LL_USART_STOPBITS_1                     0x00000000U                                /*!< 1 stop bit */
+#define LL_USART_STOPBITS_1_5                   (USART_CR2_STOP_0 | USART_CR2_STOP_1)      /*!< 1.5 stop bits */
+#define LL_USART_STOPBITS_2                     USART_CR2_STOP_1                           /*!< 2 stop bits */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_HWCONTROL Hardware Control
+  * @{
+  */
+#define LL_USART_HWCONTROL_NONE                 0x00000000U                          /*!< CTS and RTS hardware flow control disabled */
+#define LL_USART_HWCONTROL_RTS                  USART_CR3_RTSE                       /*!< RTS output enabled, data is only requested when there is space in the receive buffer */
+#define LL_USART_HWCONTROL_CTS                  USART_CR3_CTSE                       /*!< CTS mode enabled, data is only transmitted when the nCTS input is asserted (tied to 0) */
+#define LL_USART_HWCONTROL_RTS_CTS              (USART_CR3_RTSE | USART_CR3_CTSE)    /*!< CTS and RTS hardware flow control enabled */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_IRDA_POWER IrDA Power
+  * @{
+  */
+#define LL_USART_IRDA_POWER_NORMAL              0x00000000U           /*!< IrDA normal power mode */
+#define LL_USART_IRDA_POWER_LOW                 USART_CR3_IRLP        /*!< IrDA low power mode */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_LINBREAK_DETECT LIN Break Detection Length
+  * @{
+  */
+#define LL_USART_LINBREAK_DETECT_10B            0x00000000U           /*!< 10-bit break detection method selected */
+#define LL_USART_LINBREAK_DETECT_11B            USART_CR2_LBDL        /*!< 11-bit break detection method selected */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup USART_LL_Exported_Macros USART Exported Macros
+  * @{
+  */
+
+/** @defgroup USART_LL_EM_WRITE_READ Common Write and read registers Macros
+  * @{
+  */
+
+/**
+  * @brief  Write a value in USART register
+  * @param  __INSTANCE__ USART Instance
+  * @param  __REG__ Register to be written
+  * @param  __VALUE__ Value to be written in the register
+  * @retval None
+  */
+#define LL_USART_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
+
+/**
+  * @brief  Read a value in USART register
+  * @param  __INSTANCE__ USART Instance
+  * @param  __REG__ Register to be read
+  * @retval Register value
+  */
+#define LL_USART_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EM_Exported_Macros_Helper Exported_Macros_Helper
+  * @{
+  */
+
+/**
+  * @brief  Compute USARTDIV value according to Peripheral Clock and
+  *         expected Baud Rate in 8 bits sampling mode (32 bits value of USARTDIV is returned)
+  * @param  __PERIPHCLK__ Peripheral Clock frequency used for USART instance
+  * @param  __BAUDRATE__ Baud rate value to achieve
+  * @retval USARTDIV value to be used for BRR register filling in OverSampling_8 case
+  */
+#define __LL_USART_DIV_SAMPLING8_100(__PERIPHCLK__, __BAUDRATE__)      ((uint32_t)((((uint64_t)(__PERIPHCLK__))*25)/(2*((uint64_t)(__BAUDRATE__)))))
+#define __LL_USART_DIVMANT_SAMPLING8(__PERIPHCLK__, __BAUDRATE__)      (__LL_USART_DIV_SAMPLING8_100((__PERIPHCLK__), (__BAUDRATE__))/100)
+#define __LL_USART_DIVFRAQ_SAMPLING8(__PERIPHCLK__, __BAUDRATE__)      ((((__LL_USART_DIV_SAMPLING8_100((__PERIPHCLK__), (__BAUDRATE__)) - (__LL_USART_DIVMANT_SAMPLING8((__PERIPHCLK__), (__BAUDRATE__)) * 100)) * 8)\
+                                                                         + 50) / 100)
+/* UART BRR = mantissa + overflow + fraction
+            = (UART DIVMANT << 4) + ((UART DIVFRAQ & 0xF8) << 1) + (UART DIVFRAQ & 0x07) */
+#define __LL_USART_DIV_SAMPLING8(__PERIPHCLK__, __BAUDRATE__)             (((__LL_USART_DIVMANT_SAMPLING8((__PERIPHCLK__), (__BAUDRATE__)) << 4) + \
+                                                                            ((__LL_USART_DIVFRAQ_SAMPLING8((__PERIPHCLK__), (__BAUDRATE__)) & 0xF8) << 1)) + \
+                                                                           (__LL_USART_DIVFRAQ_SAMPLING8((__PERIPHCLK__), (__BAUDRATE__)) & 0x07))
+
+/**
+  * @brief  Compute USARTDIV value according to Peripheral Clock and
+  *         expected Baud Rate in 16 bits sampling mode (32 bits value of USARTDIV is returned)
+  * @param  __PERIPHCLK__ Peripheral Clock frequency used for USART instance
+  * @param  __BAUDRATE__ Baud rate value to achieve
+  * @retval USARTDIV value to be used for BRR register filling in OverSampling_16 case
+  */
+#define __LL_USART_DIV_SAMPLING16_100(__PERIPHCLK__, __BAUDRATE__)     ((uint32_t)((((uint64_t)(__PERIPHCLK__))*25)/(4*((uint64_t)(__BAUDRATE__)))))
+#define __LL_USART_DIVMANT_SAMPLING16(__PERIPHCLK__, __BAUDRATE__)     (__LL_USART_DIV_SAMPLING16_100((__PERIPHCLK__), (__BAUDRATE__))/100)
+#define __LL_USART_DIVFRAQ_SAMPLING16(__PERIPHCLK__, __BAUDRATE__)     ((((__LL_USART_DIV_SAMPLING16_100((__PERIPHCLK__), (__BAUDRATE__)) - (__LL_USART_DIVMANT_SAMPLING16((__PERIPHCLK__), (__BAUDRATE__)) * 100)) * 16)\
+                                                                         + 50) / 100)
+/* USART BRR = mantissa + overflow + fraction
+            = (USART DIVMANT << 4) + (USART DIVFRAQ & 0xF0) + (USART DIVFRAQ & 0x0F) */
+#define __LL_USART_DIV_SAMPLING16(__PERIPHCLK__, __BAUDRATE__)            (((__LL_USART_DIVMANT_SAMPLING16((__PERIPHCLK__), (__BAUDRATE__)) << 4) + \
+                                                                            (__LL_USART_DIVFRAQ_SAMPLING16((__PERIPHCLK__), (__BAUDRATE__)) & 0xF0)) + \
+                                                                           (__LL_USART_DIVFRAQ_SAMPLING16((__PERIPHCLK__), (__BAUDRATE__)) & 0x0F))
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup USART_LL_Exported_Functions USART Exported Functions
+  * @{
+  */
+
+/** @defgroup USART_LL_EF_Configuration Configuration functions
+  * @{
+  */
+
+/**
+  * @brief  USART Enable
+  * @rmtoll CR1          UE            LL_USART_Enable
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_Enable(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR1, USART_CR1_UE);
+}
+
+/**
+  * @brief  USART Disable (all USART prescalers and outputs are disabled)
+  * @note   When USART is disabled, USART prescalers and outputs are stopped immediately,
+  *         and current operations are discarded. The configuration of the USART is kept, but all the status
+  *         flags, in the USARTx_SR are set to their default values.
+  * @rmtoll CR1          UE            LL_USART_Disable
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_Disable(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR1, USART_CR1_UE);
+}
+
+/**
+  * @brief  Indicate if USART is enabled
+  * @rmtoll CR1          UE            LL_USART_IsEnabled
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabled(USART_TypeDef *USARTx)
+{
+  return (READ_BIT(USARTx->CR1, USART_CR1_UE) == (USART_CR1_UE));
+}
+
+/**
+  * @brief  Receiver Enable (Receiver is enabled and begins searching for a start bit)
+  * @rmtoll CR1          RE            LL_USART_EnableDirectionRx
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableDirectionRx(USART_TypeDef *USARTx)
+{
+  ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_RE);
+}
+
+/**
+  * @brief  Receiver Disable
+  * @rmtoll CR1          RE            LL_USART_DisableDirectionRx
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableDirectionRx(USART_TypeDef *USARTx)
+{
+  ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_RE);
+}
+
+/**
+  * @brief  Transmitter Enable
+  * @rmtoll CR1          TE            LL_USART_EnableDirectionTx
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableDirectionTx(USART_TypeDef *USARTx)
+{
+  ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_TE);
+}
+
+/**
+  * @brief  Transmitter Disable
+  * @rmtoll CR1          TE            LL_USART_DisableDirectionTx
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableDirectionTx(USART_TypeDef *USARTx)
+{
+  ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_TE);
+}
+
+/**
+  * @brief  Configure simultaneously enabled/disabled states
+  *         of Transmitter and Receiver
+  * @rmtoll CR1          RE            LL_USART_SetTransferDirection\n
+  *         CR1          TE            LL_USART_SetTransferDirection
+  * @param  USARTx USART Instance
+  * @param  TransferDirection This parameter can be one of the following values:
+  *         @arg @ref LL_USART_DIRECTION_NONE
+  *         @arg @ref LL_USART_DIRECTION_RX
+  *         @arg @ref LL_USART_DIRECTION_TX
+  *         @arg @ref LL_USART_DIRECTION_TX_RX
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetTransferDirection(USART_TypeDef *USARTx, uint32_t TransferDirection)
+{
+  ATOMIC_MODIFY_REG(USARTx->CR1, USART_CR1_RE | USART_CR1_TE, TransferDirection);
+}
+
+/**
+  * @brief  Return enabled/disabled states of Transmitter and Receiver
+  * @rmtoll CR1          RE            LL_USART_GetTransferDirection\n
+  *         CR1          TE            LL_USART_GetTransferDirection
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_DIRECTION_NONE
+  *         @arg @ref LL_USART_DIRECTION_RX
+  *         @arg @ref LL_USART_DIRECTION_TX
+  *         @arg @ref LL_USART_DIRECTION_TX_RX
+  */
+__STATIC_INLINE uint32_t LL_USART_GetTransferDirection(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_RE | USART_CR1_TE));
+}
+
+/**
+  * @brief  Configure Parity (enabled/disabled and parity mode if enabled).
+  * @note   This function selects if hardware parity control (generation and detection) is enabled or disabled.
+  *         When the parity control is enabled (Odd or Even), computed parity bit is inserted at the MSB position
+  *         (9th or 8th bit depending on data width) and parity is checked on the received data.
+  * @rmtoll CR1          PS            LL_USART_SetParity\n
+  *         CR1          PCE           LL_USART_SetParity
+  * @param  USARTx USART Instance
+  * @param  Parity This parameter can be one of the following values:
+  *         @arg @ref LL_USART_PARITY_NONE
+  *         @arg @ref LL_USART_PARITY_EVEN
+  *         @arg @ref LL_USART_PARITY_ODD
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetParity(USART_TypeDef *USARTx, uint32_t Parity)
+{
+  MODIFY_REG(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE, Parity);
+}
+
+/**
+  * @brief  Return Parity configuration (enabled/disabled and parity mode if enabled)
+  * @rmtoll CR1          PS            LL_USART_GetParity\n
+  *         CR1          PCE           LL_USART_GetParity
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_PARITY_NONE
+  *         @arg @ref LL_USART_PARITY_EVEN
+  *         @arg @ref LL_USART_PARITY_ODD
+  */
+__STATIC_INLINE uint32_t LL_USART_GetParity(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE));
+}
+
+/**
+  * @brief  Set Receiver Wake Up method from Mute mode.
+  * @rmtoll CR1          WAKE          LL_USART_SetWakeUpMethod
+  * @param  USARTx USART Instance
+  * @param  Method This parameter can be one of the following values:
+  *         @arg @ref LL_USART_WAKEUP_IDLELINE
+  *         @arg @ref LL_USART_WAKEUP_ADDRESSMARK
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetWakeUpMethod(USART_TypeDef *USARTx, uint32_t Method)
+{
+  MODIFY_REG(USARTx->CR1, USART_CR1_WAKE, Method);
+}
+
+/**
+  * @brief  Return Receiver Wake Up method from Mute mode
+  * @rmtoll CR1          WAKE          LL_USART_GetWakeUpMethod
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_WAKEUP_IDLELINE
+  *         @arg @ref LL_USART_WAKEUP_ADDRESSMARK
+  */
+__STATIC_INLINE uint32_t LL_USART_GetWakeUpMethod(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_WAKE));
+}
+
+/**
+  * @brief  Set Word length (i.e. nb of data bits, excluding start and stop bits)
+  * @rmtoll CR1          M             LL_USART_SetDataWidth
+  * @param  USARTx USART Instance
+  * @param  DataWidth This parameter can be one of the following values:
+  *         @arg @ref LL_USART_DATAWIDTH_8B
+  *         @arg @ref LL_USART_DATAWIDTH_9B
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetDataWidth(USART_TypeDef *USARTx, uint32_t DataWidth)
+{
+  MODIFY_REG(USARTx->CR1, USART_CR1_M, DataWidth);
+}
+
+/**
+  * @brief  Return Word length (i.e. nb of data bits, excluding start and stop bits)
+  * @rmtoll CR1          M             LL_USART_GetDataWidth
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_DATAWIDTH_8B
+  *         @arg @ref LL_USART_DATAWIDTH_9B
+  */
+__STATIC_INLINE uint32_t LL_USART_GetDataWidth(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_M));
+}
+
+/**
+  * @brief  Set Oversampling to 8-bit or 16-bit mode
+  * @rmtoll CR1          OVER8         LL_USART_SetOverSampling
+  * @param  USARTx USART Instance
+  * @param  OverSampling This parameter can be one of the following values:
+  *         @arg @ref LL_USART_OVERSAMPLING_16
+  *         @arg @ref LL_USART_OVERSAMPLING_8
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetOverSampling(USART_TypeDef *USARTx, uint32_t OverSampling)
+{
+  MODIFY_REG(USARTx->CR1, USART_CR1_OVER8, OverSampling);
+}
+
+/**
+  * @brief  Return Oversampling mode
+  * @rmtoll CR1          OVER8         LL_USART_GetOverSampling
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_OVERSAMPLING_16
+  *         @arg @ref LL_USART_OVERSAMPLING_8
+  */
+__STATIC_INLINE uint32_t LL_USART_GetOverSampling(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_OVER8));
+}
+
+/**
+  * @brief  Configure if Clock pulse of the last data bit is output to the SCLK pin or not
+  * @note   Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
+  *         Synchronous mode is supported by the USARTx instance.
+  * @rmtoll CR2          LBCL          LL_USART_SetLastClkPulseOutput
+  * @param  USARTx USART Instance
+  * @param  LastBitClockPulse This parameter can be one of the following values:
+  *         @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT
+  *         @arg @ref LL_USART_LASTCLKPULSE_OUTPUT
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetLastClkPulseOutput(USART_TypeDef *USARTx, uint32_t LastBitClockPulse)
+{
+  MODIFY_REG(USARTx->CR2, USART_CR2_LBCL, LastBitClockPulse);
+}
+
+/**
+  * @brief  Retrieve Clock pulse of the last data bit output configuration
+  *         (Last bit Clock pulse output to the SCLK pin or not)
+  * @note   Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
+  *         Synchronous mode is supported by the USARTx instance.
+  * @rmtoll CR2          LBCL          LL_USART_GetLastClkPulseOutput
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT
+  *         @arg @ref LL_USART_LASTCLKPULSE_OUTPUT
+  */
+__STATIC_INLINE uint32_t LL_USART_GetLastClkPulseOutput(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_LBCL));
+}
+
+/**
+  * @brief  Select the phase of the clock output on the SCLK pin in synchronous mode
+  * @note   Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
+  *         Synchronous mode is supported by the USARTx instance.
+  * @rmtoll CR2          CPHA          LL_USART_SetClockPhase
+  * @param  USARTx USART Instance
+  * @param  ClockPhase This parameter can be one of the following values:
+  *         @arg @ref LL_USART_PHASE_1EDGE
+  *         @arg @ref LL_USART_PHASE_2EDGE
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetClockPhase(USART_TypeDef *USARTx, uint32_t ClockPhase)
+{
+  MODIFY_REG(USARTx->CR2, USART_CR2_CPHA, ClockPhase);
+}
+
+/**
+  * @brief  Return phase of the clock output on the SCLK pin in synchronous mode
+  * @note   Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
+  *         Synchronous mode is supported by the USARTx instance.
+  * @rmtoll CR2          CPHA          LL_USART_GetClockPhase
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_PHASE_1EDGE
+  *         @arg @ref LL_USART_PHASE_2EDGE
+  */
+__STATIC_INLINE uint32_t LL_USART_GetClockPhase(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_CPHA));
+}
+
+/**
+  * @brief  Select the polarity of the clock output on the SCLK pin in synchronous mode
+  * @note   Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
+  *         Synchronous mode is supported by the USARTx instance.
+  * @rmtoll CR2          CPOL          LL_USART_SetClockPolarity
+  * @param  USARTx USART Instance
+  * @param  ClockPolarity This parameter can be one of the following values:
+  *         @arg @ref LL_USART_POLARITY_LOW
+  *         @arg @ref LL_USART_POLARITY_HIGH
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetClockPolarity(USART_TypeDef *USARTx, uint32_t ClockPolarity)
+{
+  MODIFY_REG(USARTx->CR2, USART_CR2_CPOL, ClockPolarity);
+}
+
+/**
+  * @brief  Return polarity of the clock output on the SCLK pin in synchronous mode
+  * @note   Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
+  *         Synchronous mode is supported by the USARTx instance.
+  * @rmtoll CR2          CPOL          LL_USART_GetClockPolarity
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_POLARITY_LOW
+  *         @arg @ref LL_USART_POLARITY_HIGH
+  */
+__STATIC_INLINE uint32_t LL_USART_GetClockPolarity(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_CPOL));
+}
+
+/**
+  * @brief  Configure Clock signal format (Phase Polarity and choice about output of last bit clock pulse)
+  * @note   Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
+  *         Synchronous mode is supported by the USARTx instance.
+  * @note   Call of this function is equivalent to following function call sequence :
+  *         - Clock Phase configuration using @ref LL_USART_SetClockPhase() function
+  *         - Clock Polarity configuration using @ref LL_USART_SetClockPolarity() function
+  *         - Output of Last bit Clock pulse configuration using @ref LL_USART_SetLastClkPulseOutput() function
+  * @rmtoll CR2          CPHA          LL_USART_ConfigClock\n
+  *         CR2          CPOL          LL_USART_ConfigClock\n
+  *         CR2          LBCL          LL_USART_ConfigClock
+  * @param  USARTx USART Instance
+  * @param  Phase This parameter can be one of the following values:
+  *         @arg @ref LL_USART_PHASE_1EDGE
+  *         @arg @ref LL_USART_PHASE_2EDGE
+  * @param  Polarity This parameter can be one of the following values:
+  *         @arg @ref LL_USART_POLARITY_LOW
+  *         @arg @ref LL_USART_POLARITY_HIGH
+  * @param  LBCPOutput This parameter can be one of the following values:
+  *         @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT
+  *         @arg @ref LL_USART_LASTCLKPULSE_OUTPUT
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ConfigClock(USART_TypeDef *USARTx, uint32_t Phase, uint32_t Polarity, uint32_t LBCPOutput)
+{
+  MODIFY_REG(USARTx->CR2, USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_LBCL, Phase | Polarity | LBCPOutput);
+}
+
+/**
+  * @brief  Enable Clock output on SCLK pin
+  * @note   Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
+  *         Synchronous mode is supported by the USARTx instance.
+  * @rmtoll CR2          CLKEN         LL_USART_EnableSCLKOutput
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableSCLKOutput(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR2, USART_CR2_CLKEN);
+}
+
+/**
+  * @brief  Disable Clock output on SCLK pin
+  * @note   Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
+  *         Synchronous mode is supported by the USARTx instance.
+  * @rmtoll CR2          CLKEN         LL_USART_DisableSCLKOutput
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableSCLKOutput(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR2, USART_CR2_CLKEN);
+}
+
+/**
+  * @brief  Indicate if Clock output on SCLK pin is enabled
+  * @note   Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
+  *         Synchronous mode is supported by the USARTx instance.
+  * @rmtoll CR2          CLKEN         LL_USART_IsEnabledSCLKOutput
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledSCLKOutput(USART_TypeDef *USARTx)
+{
+  return (READ_BIT(USARTx->CR2, USART_CR2_CLKEN) == (USART_CR2_CLKEN));
+}
+
+/**
+  * @brief  Set the length of the stop bits
+  * @rmtoll CR2          STOP          LL_USART_SetStopBitsLength
+  * @param  USARTx USART Instance
+  * @param  StopBits This parameter can be one of the following values:
+  *         @arg @ref LL_USART_STOPBITS_0_5
+  *         @arg @ref LL_USART_STOPBITS_1
+  *         @arg @ref LL_USART_STOPBITS_1_5
+  *         @arg @ref LL_USART_STOPBITS_2
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetStopBitsLength(USART_TypeDef *USARTx, uint32_t StopBits)
+{
+  MODIFY_REG(USARTx->CR2, USART_CR2_STOP, StopBits);
+}
+
+/**
+  * @brief  Retrieve the length of the stop bits
+  * @rmtoll CR2          STOP          LL_USART_GetStopBitsLength
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_STOPBITS_0_5
+  *         @arg @ref LL_USART_STOPBITS_1
+  *         @arg @ref LL_USART_STOPBITS_1_5
+  *         @arg @ref LL_USART_STOPBITS_2
+  */
+__STATIC_INLINE uint32_t LL_USART_GetStopBitsLength(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_STOP));
+}
+
+/**
+  * @brief  Configure Character frame format (Datawidth, Parity control, Stop Bits)
+  * @note   Call of this function is equivalent to following function call sequence :
+  *         - Data Width configuration using @ref LL_USART_SetDataWidth() function
+  *         - Parity Control and mode configuration using @ref LL_USART_SetParity() function
+  *         - Stop bits configuration using @ref LL_USART_SetStopBitsLength() function
+  * @rmtoll CR1          PS            LL_USART_ConfigCharacter\n
+  *         CR1          PCE           LL_USART_ConfigCharacter\n
+  *         CR1          M             LL_USART_ConfigCharacter\n
+  *         CR2          STOP          LL_USART_ConfigCharacter
+  * @param  USARTx USART Instance
+  * @param  DataWidth This parameter can be one of the following values:
+  *         @arg @ref LL_USART_DATAWIDTH_8B
+  *         @arg @ref LL_USART_DATAWIDTH_9B
+  * @param  Parity This parameter can be one of the following values:
+  *         @arg @ref LL_USART_PARITY_NONE
+  *         @arg @ref LL_USART_PARITY_EVEN
+  *         @arg @ref LL_USART_PARITY_ODD
+  * @param  StopBits This parameter can be one of the following values:
+  *         @arg @ref LL_USART_STOPBITS_0_5
+  *         @arg @ref LL_USART_STOPBITS_1
+  *         @arg @ref LL_USART_STOPBITS_1_5
+  *         @arg @ref LL_USART_STOPBITS_2
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ConfigCharacter(USART_TypeDef *USARTx, uint32_t DataWidth, uint32_t Parity,
+                                              uint32_t StopBits)
+{
+  MODIFY_REG(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE | USART_CR1_M, Parity | DataWidth);
+  MODIFY_REG(USARTx->CR2, USART_CR2_STOP, StopBits);
+}
+
+/**
+  * @brief  Set Address of the USART node.
+  * @note   This is used in multiprocessor communication during Mute mode or Stop mode,
+  *         for wake up with address mark detection.
+  * @rmtoll CR2          ADD           LL_USART_SetNodeAddress
+  * @param  USARTx USART Instance
+  * @param  NodeAddress 4 bit Address of the USART node.
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetNodeAddress(USART_TypeDef *USARTx, uint32_t NodeAddress)
+{
+  MODIFY_REG(USARTx->CR2, USART_CR2_ADD, (NodeAddress & USART_CR2_ADD));
+}
+
+/**
+  * @brief  Return 4 bit Address of the USART node as set in ADD field of CR2.
+  * @note   only 4bits (b3-b0) of returned value are relevant (b31-b4 are not relevant)
+  * @rmtoll CR2          ADD           LL_USART_GetNodeAddress
+  * @param  USARTx USART Instance
+  * @retval Address of the USART node (Value between Min_Data=0 and Max_Data=255)
+  */
+__STATIC_INLINE uint32_t LL_USART_GetNodeAddress(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ADD));
+}
+
+/**
+  * @brief  Enable RTS HW Flow Control
+  * @note   Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+  *         Hardware Flow control feature is supported by the USARTx instance.
+  * @rmtoll CR3          RTSE          LL_USART_EnableRTSHWFlowCtrl
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableRTSHWFlowCtrl(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR3, USART_CR3_RTSE);
+}
+
+/**
+  * @brief  Disable RTS HW Flow Control
+  * @note   Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+  *         Hardware Flow control feature is supported by the USARTx instance.
+  * @rmtoll CR3          RTSE          LL_USART_DisableRTSHWFlowCtrl
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableRTSHWFlowCtrl(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR3, USART_CR3_RTSE);
+}
+
+/**
+  * @brief  Enable CTS HW Flow Control
+  * @note   Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+  *         Hardware Flow control feature is supported by the USARTx instance.
+  * @rmtoll CR3          CTSE          LL_USART_EnableCTSHWFlowCtrl
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableCTSHWFlowCtrl(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR3, USART_CR3_CTSE);
+}
+
+/**
+  * @brief  Disable CTS HW Flow Control
+  * @note   Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+  *         Hardware Flow control feature is supported by the USARTx instance.
+  * @rmtoll CR3          CTSE          LL_USART_DisableCTSHWFlowCtrl
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableCTSHWFlowCtrl(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR3, USART_CR3_CTSE);
+}
+
+/**
+  * @brief  Configure HW Flow Control mode (both CTS and RTS)
+  * @note   Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+  *         Hardware Flow control feature is supported by the USARTx instance.
+  * @rmtoll CR3          RTSE          LL_USART_SetHWFlowCtrl\n
+  *         CR3          CTSE          LL_USART_SetHWFlowCtrl
+  * @param  USARTx USART Instance
+  * @param  HardwareFlowControl This parameter can be one of the following values:
+  *         @arg @ref LL_USART_HWCONTROL_NONE
+  *         @arg @ref LL_USART_HWCONTROL_RTS
+  *         @arg @ref LL_USART_HWCONTROL_CTS
+  *         @arg @ref LL_USART_HWCONTROL_RTS_CTS
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetHWFlowCtrl(USART_TypeDef *USARTx, uint32_t HardwareFlowControl)
+{
+  MODIFY_REG(USARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE, HardwareFlowControl);
+}
+
+/**
+  * @brief  Return HW Flow Control configuration (both CTS and RTS)
+  * @note   Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+  *         Hardware Flow control feature is supported by the USARTx instance.
+  * @rmtoll CR3          RTSE          LL_USART_GetHWFlowCtrl\n
+  *         CR3          CTSE          LL_USART_GetHWFlowCtrl
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_HWCONTROL_NONE
+  *         @arg @ref LL_USART_HWCONTROL_RTS
+  *         @arg @ref LL_USART_HWCONTROL_CTS
+  *         @arg @ref LL_USART_HWCONTROL_RTS_CTS
+  */
+__STATIC_INLINE uint32_t LL_USART_GetHWFlowCtrl(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE));
+}
+
+/**
+  * @brief  Enable One bit sampling method
+  * @rmtoll CR3          ONEBIT        LL_USART_EnableOneBitSamp
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableOneBitSamp(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR3, USART_CR3_ONEBIT);
+}
+
+/**
+  * @brief  Disable One bit sampling method
+  * @rmtoll CR3          ONEBIT        LL_USART_DisableOneBitSamp
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableOneBitSamp(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR3, USART_CR3_ONEBIT);
+}
+
+/**
+  * @brief  Indicate if One bit sampling method is enabled
+  * @rmtoll CR3          ONEBIT        LL_USART_IsEnabledOneBitSamp
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledOneBitSamp(USART_TypeDef *USARTx)
+{
+  return (READ_BIT(USARTx->CR3, USART_CR3_ONEBIT) == (USART_CR3_ONEBIT));
+}
+
+/**
+  * @brief  Configure USART BRR register for achieving expected Baud Rate value.
+  * @note   Compute and set USARTDIV value in BRR Register (full BRR content)
+  *         according to used Peripheral Clock, Oversampling mode, and expected Baud Rate values
+  * @note   Peripheral clock and Baud rate values provided as function parameters should be valid
+  *         (Baud rate value != 0)
+  * @rmtoll BRR          BRR           LL_USART_SetBaudRate
+  * @param  USARTx USART Instance
+  * @param  PeriphClk Peripheral Clock
+  * @param  OverSampling This parameter can be one of the following values:
+  *         @arg @ref LL_USART_OVERSAMPLING_16
+  *         @arg @ref LL_USART_OVERSAMPLING_8
+  * @param  BaudRate Baud Rate
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetBaudRate(USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t OverSampling,
+                                          uint32_t BaudRate)
+{
+  if (OverSampling == LL_USART_OVERSAMPLING_8)
+  {
+    USARTx->BRR = (uint16_t)(__LL_USART_DIV_SAMPLING8(PeriphClk, BaudRate));
+  }
+  else
+  {
+    USARTx->BRR = (uint16_t)(__LL_USART_DIV_SAMPLING16(PeriphClk, BaudRate));
+  }
+}
+
+/**
+  * @brief  Return current Baud Rate value, according to USARTDIV present in BRR register
+  *         (full BRR content), and to used Peripheral Clock and Oversampling mode values
+  * @note   In case of non-initialized or invalid value stored in BRR register, value 0 will be returned.
+  * @rmtoll BRR          BRR           LL_USART_GetBaudRate
+  * @param  USARTx USART Instance
+  * @param  PeriphClk Peripheral Clock
+  * @param  OverSampling This parameter can be one of the following values:
+  *         @arg @ref LL_USART_OVERSAMPLING_16
+  *         @arg @ref LL_USART_OVERSAMPLING_8
+  * @retval Baud Rate
+  */
+__STATIC_INLINE uint32_t LL_USART_GetBaudRate(USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t OverSampling)
+{
+  uint32_t usartdiv = 0x0U;
+  uint32_t brrresult = 0x0U;
+
+  usartdiv = USARTx->BRR;
+
+  if (OverSampling == LL_USART_OVERSAMPLING_8)
+  {
+    if ((usartdiv & 0xFFF7U) != 0U)
+    {
+      usartdiv = (uint16_t)((usartdiv & 0xFFF0U) | ((usartdiv & 0x0007U) << 1U)) ;
+      brrresult = (PeriphClk * 2U) / usartdiv;
+    }
+  }
+  else
+  {
+    if ((usartdiv & 0xFFFFU) != 0U)
+    {
+      brrresult = PeriphClk / usartdiv;
+    }
+  }
+  return (brrresult);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EF_Configuration_IRDA Configuration functions related to Irda feature
+  * @{
+  */
+
+/**
+  * @brief  Enable IrDA mode
+  * @note   Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
+  *         IrDA feature is supported by the USARTx instance.
+  * @rmtoll CR3          IREN          LL_USART_EnableIrda
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableIrda(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR3, USART_CR3_IREN);
+}
+
+/**
+  * @brief  Disable IrDA mode
+  * @note   Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
+  *         IrDA feature is supported by the USARTx instance.
+  * @rmtoll CR3          IREN          LL_USART_DisableIrda
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableIrda(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR3, USART_CR3_IREN);
+}
+
+/**
+  * @brief  Indicate if IrDA mode is enabled
+  * @note   Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
+  *         IrDA feature is supported by the USARTx instance.
+  * @rmtoll CR3          IREN          LL_USART_IsEnabledIrda
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIrda(USART_TypeDef *USARTx)
+{
+  return (READ_BIT(USARTx->CR3, USART_CR3_IREN) == (USART_CR3_IREN));
+}
+
+/**
+  * @brief  Configure IrDA Power Mode (Normal or Low Power)
+  * @note   Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
+  *         IrDA feature is supported by the USARTx instance.
+  * @rmtoll CR3          IRLP          LL_USART_SetIrdaPowerMode
+  * @param  USARTx USART Instance
+  * @param  PowerMode This parameter can be one of the following values:
+  *         @arg @ref LL_USART_IRDA_POWER_NORMAL
+  *         @arg @ref LL_USART_IRDA_POWER_LOW
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetIrdaPowerMode(USART_TypeDef *USARTx, uint32_t PowerMode)
+{
+  MODIFY_REG(USARTx->CR3, USART_CR3_IRLP, PowerMode);
+}
+
+/**
+  * @brief  Retrieve IrDA Power Mode configuration (Normal or Low Power)
+  * @note   Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
+  *         IrDA feature is supported by the USARTx instance.
+  * @rmtoll CR3          IRLP          LL_USART_GetIrdaPowerMode
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_IRDA_POWER_NORMAL
+  *         @arg @ref LL_USART_PHASE_2EDGE
+  */
+__STATIC_INLINE uint32_t LL_USART_GetIrdaPowerMode(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_IRLP));
+}
+
+/**
+  * @brief  Set Irda prescaler value, used for dividing the USART clock source
+  *         to achieve the Irda Low Power frequency (8 bits value)
+  * @note   Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
+  *         IrDA feature is supported by the USARTx instance.
+  * @rmtoll GTPR         PSC           LL_USART_SetIrdaPrescaler
+  * @param  USARTx USART Instance
+  * @param  PrescalerValue Value between Min_Data=0x00 and Max_Data=0xFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetIrdaPrescaler(USART_TypeDef *USARTx, uint32_t PrescalerValue)
+{
+  MODIFY_REG(USARTx->GTPR, USART_GTPR_PSC, PrescalerValue);
+}
+
+/**
+  * @brief  Return Irda prescaler value, used for dividing the USART clock source
+  *         to achieve the Irda Low Power frequency (8 bits value)
+  * @note   Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
+  *         IrDA feature is supported by the USARTx instance.
+  * @rmtoll GTPR         PSC           LL_USART_GetIrdaPrescaler
+  * @param  USARTx USART Instance
+  * @retval Irda prescaler value (Value between Min_Data=0x00 and Max_Data=0xFF)
+  */
+__STATIC_INLINE uint32_t LL_USART_GetIrdaPrescaler(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_PSC));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EF_Configuration_Smartcard Configuration functions related to Smartcard feature
+  * @{
+  */
+
+/**
+  * @brief  Enable Smartcard NACK transmission
+  * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @rmtoll CR3          NACK          LL_USART_EnableSmartcardNACK
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableSmartcardNACK(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR3, USART_CR3_NACK);
+}
+
+/**
+  * @brief  Disable Smartcard NACK transmission
+  * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @rmtoll CR3          NACK          LL_USART_DisableSmartcardNACK
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableSmartcardNACK(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR3, USART_CR3_NACK);
+}
+
+/**
+  * @brief  Indicate if Smartcard NACK transmission is enabled
+  * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @rmtoll CR3          NACK          LL_USART_IsEnabledSmartcardNACK
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcardNACK(USART_TypeDef *USARTx)
+{
+  return (READ_BIT(USARTx->CR3, USART_CR3_NACK) == (USART_CR3_NACK));
+}
+
+/**
+  * @brief  Enable Smartcard mode
+  * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @rmtoll CR3          SCEN          LL_USART_EnableSmartcard
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableSmartcard(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR3, USART_CR3_SCEN);
+}
+
+/**
+  * @brief  Disable Smartcard mode
+  * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @rmtoll CR3          SCEN          LL_USART_DisableSmartcard
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableSmartcard(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR3, USART_CR3_SCEN);
+}
+
+/**
+  * @brief  Indicate if Smartcard mode is enabled
+  * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @rmtoll CR3          SCEN          LL_USART_IsEnabledSmartcard
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcard(USART_TypeDef *USARTx)
+{
+  return (READ_BIT(USARTx->CR3, USART_CR3_SCEN) == (USART_CR3_SCEN));
+}
+
+/**
+  * @brief  Set Smartcard prescaler value, used for dividing the USART clock
+  *         source to provide the SMARTCARD Clock (5 bits value)
+  * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @rmtoll GTPR         PSC           LL_USART_SetSmartcardPrescaler
+  * @param  USARTx USART Instance
+  * @param  PrescalerValue Value between Min_Data=0 and Max_Data=31
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetSmartcardPrescaler(USART_TypeDef *USARTx, uint32_t PrescalerValue)
+{
+  MODIFY_REG(USARTx->GTPR, USART_GTPR_PSC, PrescalerValue);
+}
+
+/**
+  * @brief  Return Smartcard prescaler value, used for dividing the USART clock
+  *         source to provide the SMARTCARD Clock (5 bits value)
+  * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @rmtoll GTPR         PSC           LL_USART_GetSmartcardPrescaler
+  * @param  USARTx USART Instance
+  * @retval Smartcard prescaler value (Value between Min_Data=0 and Max_Data=31)
+  */
+__STATIC_INLINE uint32_t LL_USART_GetSmartcardPrescaler(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_PSC));
+}
+
+/**
+  * @brief  Set Smartcard Guard time value, expressed in nb of baud clocks periods
+  *         (GT[7:0] bits : Guard time value)
+  * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @rmtoll GTPR         GT            LL_USART_SetSmartcardGuardTime
+  * @param  USARTx USART Instance
+  * @param  GuardTime Value between Min_Data=0x00 and Max_Data=0xFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetSmartcardGuardTime(USART_TypeDef *USARTx, uint32_t GuardTime)
+{
+  MODIFY_REG(USARTx->GTPR, USART_GTPR_GT, GuardTime << USART_POSITION_GTPR_GT);
+}
+
+/**
+  * @brief  Return Smartcard Guard time value, expressed in nb of baud clocks periods
+  *         (GT[7:0] bits : Guard time value)
+  * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @rmtoll GTPR         GT            LL_USART_GetSmartcardGuardTime
+  * @param  USARTx USART Instance
+  * @retval Smartcard Guard time value (Value between Min_Data=0x00 and Max_Data=0xFF)
+  */
+__STATIC_INLINE uint32_t LL_USART_GetSmartcardGuardTime(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_GT) >> USART_POSITION_GTPR_GT);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EF_Configuration_HalfDuplex Configuration functions related to Half Duplex feature
+  * @{
+  */
+
+/**
+  * @brief  Enable Single Wire Half-Duplex mode
+  * @note   Macro @ref IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not
+  *         Half-Duplex mode is supported by the USARTx instance.
+  * @rmtoll CR3          HDSEL         LL_USART_EnableHalfDuplex
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableHalfDuplex(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR3, USART_CR3_HDSEL);
+}
+
+/**
+  * @brief  Disable Single Wire Half-Duplex mode
+  * @note   Macro @ref IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not
+  *         Half-Duplex mode is supported by the USARTx instance.
+  * @rmtoll CR3          HDSEL         LL_USART_DisableHalfDuplex
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableHalfDuplex(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR3, USART_CR3_HDSEL);
+}
+
+/**
+  * @brief  Indicate if Single Wire Half-Duplex mode is enabled
+  * @note   Macro @ref IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not
+  *         Half-Duplex mode is supported by the USARTx instance.
+  * @rmtoll CR3          HDSEL         LL_USART_IsEnabledHalfDuplex
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledHalfDuplex(USART_TypeDef *USARTx)
+{
+  return (READ_BIT(USARTx->CR3, USART_CR3_HDSEL) == (USART_CR3_HDSEL));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EF_Configuration_LIN Configuration functions related to LIN feature
+  * @{
+  */
+
+/**
+  * @brief  Set LIN Break Detection Length
+  * @note   Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+  *         LIN feature is supported by the USARTx instance.
+  * @rmtoll CR2          LBDL          LL_USART_SetLINBrkDetectionLen
+  * @param  USARTx USART Instance
+  * @param  LINBDLength This parameter can be one of the following values:
+  *         @arg @ref LL_USART_LINBREAK_DETECT_10B
+  *         @arg @ref LL_USART_LINBREAK_DETECT_11B
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetLINBrkDetectionLen(USART_TypeDef *USARTx, uint32_t LINBDLength)
+{
+  MODIFY_REG(USARTx->CR2, USART_CR2_LBDL, LINBDLength);
+}
+
+/**
+  * @brief  Return LIN Break Detection Length
+  * @note   Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+  *         LIN feature is supported by the USARTx instance.
+  * @rmtoll CR2          LBDL          LL_USART_GetLINBrkDetectionLen
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_LINBREAK_DETECT_10B
+  *         @arg @ref LL_USART_LINBREAK_DETECT_11B
+  */
+__STATIC_INLINE uint32_t LL_USART_GetLINBrkDetectionLen(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_LBDL));
+}
+
+/**
+  * @brief  Enable LIN mode
+  * @note   Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+  *         LIN feature is supported by the USARTx instance.
+  * @rmtoll CR2          LINEN         LL_USART_EnableLIN
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableLIN(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR2, USART_CR2_LINEN);
+}
+
+/**
+  * @brief  Disable LIN mode
+  * @note   Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+  *         LIN feature is supported by the USARTx instance.
+  * @rmtoll CR2          LINEN         LL_USART_DisableLIN
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableLIN(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR2, USART_CR2_LINEN);
+}
+
+/**
+  * @brief  Indicate if LIN mode is enabled
+  * @note   Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+  *         LIN feature is supported by the USARTx instance.
+  * @rmtoll CR2          LINEN         LL_USART_IsEnabledLIN
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledLIN(USART_TypeDef *USARTx)
+{
+  return (READ_BIT(USARTx->CR2, USART_CR2_LINEN) == (USART_CR2_LINEN));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EF_AdvancedConfiguration Advanced Configurations services
+  * @{
+  */
+
+/**
+  * @brief  Perform basic configuration of USART for enabling use in Asynchronous Mode (UART)
+  * @note   In UART mode, the following bits must be kept cleared:
+  *           - LINEN bit in the USART_CR2 register,
+  *           - CLKEN bit in the USART_CR2 register,
+  *           - SCEN bit in the USART_CR3 register,
+  *           - IREN bit in the USART_CR3 register,
+  *           - HDSEL bit in the USART_CR3 register.
+  * @note   Call of this function is equivalent to following function call sequence :
+  *         - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
+  *         - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function
+  *         - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
+  *         - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
+  *         - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
+  * @note   Other remaining configurations items related to Asynchronous Mode
+  *         (as Baud Rate, Word length, Parity, ...) should be set using
+  *         dedicated functions
+  * @rmtoll CR2          LINEN         LL_USART_ConfigAsyncMode\n
+  *         CR2          CLKEN         LL_USART_ConfigAsyncMode\n
+  *         CR3          SCEN          LL_USART_ConfigAsyncMode\n
+  *         CR3          IREN          LL_USART_ConfigAsyncMode\n
+  *         CR3          HDSEL         LL_USART_ConfigAsyncMode
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ConfigAsyncMode(USART_TypeDef *USARTx)
+{
+  /* In Asynchronous mode, the following bits must be kept cleared:
+  - LINEN, CLKEN bits in the USART_CR2 register,
+  - SCEN, IREN and HDSEL bits in the USART_CR3 register.*/
+  CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
+  CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN | USART_CR3_HDSEL));
+}
+
+/**
+  * @brief  Perform basic configuration of USART for enabling use in Synchronous Mode
+  * @note   In Synchronous mode, the following bits must be kept cleared:
+  *           - LINEN bit in the USART_CR2 register,
+  *           - SCEN bit in the USART_CR3 register,
+  *           - IREN bit in the USART_CR3 register,
+  *           - HDSEL bit in the USART_CR3 register.
+  *         This function also sets the USART in Synchronous mode.
+  * @note   Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
+  *         Synchronous mode is supported by the USARTx instance.
+  * @note   Call of this function is equivalent to following function call sequence :
+  *         - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
+  *         - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
+  *         - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
+  *         - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
+  *         - Set CLKEN in CR2 using @ref LL_USART_EnableSCLKOutput() function
+  * @note   Other remaining configurations items related to Synchronous Mode
+  *         (as Baud Rate, Word length, Parity, Clock Polarity, ...) should be set using
+  *         dedicated functions
+  * @rmtoll CR2          LINEN         LL_USART_ConfigSyncMode\n
+  *         CR2          CLKEN         LL_USART_ConfigSyncMode\n
+  *         CR3          SCEN          LL_USART_ConfigSyncMode\n
+  *         CR3          IREN          LL_USART_ConfigSyncMode\n
+  *         CR3          HDSEL         LL_USART_ConfigSyncMode
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ConfigSyncMode(USART_TypeDef *USARTx)
+{
+  /* In Synchronous mode, the following bits must be kept cleared:
+  - LINEN bit in the USART_CR2 register,
+  - SCEN, IREN and HDSEL bits in the USART_CR3 register.*/
+  CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN));
+  CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN | USART_CR3_HDSEL));
+  /* set the UART/USART in Synchronous mode */
+  SET_BIT(USARTx->CR2, USART_CR2_CLKEN);
+}
+
+/**
+  * @brief  Perform basic configuration of USART for enabling use in LIN Mode
+  * @note   In LIN mode, the following bits must be kept cleared:
+  *           - STOP and CLKEN bits in the USART_CR2 register,
+  *           - SCEN bit in the USART_CR3 register,
+  *           - IREN bit in the USART_CR3 register,
+  *           - HDSEL bit in the USART_CR3 register.
+  *         This function also set the UART/USART in LIN mode.
+  * @note   Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+  *         LIN feature is supported by the USARTx instance.
+  * @note   Call of this function is equivalent to following function call sequence :
+  *         - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function
+  *         - Clear STOP in CR2 using @ref LL_USART_SetStopBitsLength() function
+  *         - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
+  *         - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
+  *         - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
+  *         - Set LINEN in CR2 using @ref LL_USART_EnableLIN() function
+  * @note   Other remaining configurations items related to LIN Mode
+  *         (as Baud Rate, Word length, LIN Break Detection Length, ...) should be set using
+  *         dedicated functions
+  * @rmtoll CR2          CLKEN         LL_USART_ConfigLINMode\n
+  *         CR2          STOP          LL_USART_ConfigLINMode\n
+  *         CR2          LINEN         LL_USART_ConfigLINMode\n
+  *         CR3          IREN          LL_USART_ConfigLINMode\n
+  *         CR3          SCEN          LL_USART_ConfigLINMode\n
+  *         CR3          HDSEL         LL_USART_ConfigLINMode
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ConfigLINMode(USART_TypeDef *USARTx)
+{
+  /* In LIN mode, the following bits must be kept cleared:
+  - STOP and CLKEN bits in the USART_CR2 register,
+  - IREN, SCEN and HDSEL bits in the USART_CR3 register.*/
+  CLEAR_BIT(USARTx->CR2, (USART_CR2_CLKEN | USART_CR2_STOP));
+  CLEAR_BIT(USARTx->CR3, (USART_CR3_IREN | USART_CR3_SCEN | USART_CR3_HDSEL));
+  /* Set the UART/USART in LIN mode */
+  SET_BIT(USARTx->CR2, USART_CR2_LINEN);
+}
+
+/**
+  * @brief  Perform basic configuration of USART for enabling use in Half Duplex Mode
+  * @note   In Half Duplex mode, the following bits must be kept cleared:
+  *           - LINEN bit in the USART_CR2 register,
+  *           - CLKEN bit in the USART_CR2 register,
+  *           - SCEN bit in the USART_CR3 register,
+  *           - IREN bit in the USART_CR3 register,
+  *         This function also sets the UART/USART in Half Duplex mode.
+  * @note   Macro @ref IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not
+  *         Half-Duplex mode is supported by the USARTx instance.
+  * @note   Call of this function is equivalent to following function call sequence :
+  *         - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
+  *         - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function
+  *         - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
+  *         - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
+  *         - Set HDSEL in CR3 using @ref LL_USART_EnableHalfDuplex() function
+  * @note   Other remaining configurations items related to Half Duplex Mode
+  *         (as Baud Rate, Word length, Parity, ...) should be set using
+  *         dedicated functions
+  * @rmtoll CR2          LINEN         LL_USART_ConfigHalfDuplexMode\n
+  *         CR2          CLKEN         LL_USART_ConfigHalfDuplexMode\n
+  *         CR3          HDSEL         LL_USART_ConfigHalfDuplexMode\n
+  *         CR3          SCEN          LL_USART_ConfigHalfDuplexMode\n
+  *         CR3          IREN          LL_USART_ConfigHalfDuplexMode
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ConfigHalfDuplexMode(USART_TypeDef *USARTx)
+{
+  /* In Half Duplex mode, the following bits must be kept cleared:
+  - LINEN and CLKEN bits in the USART_CR2 register,
+  - SCEN and IREN bits in the USART_CR3 register.*/
+  CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
+  CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN));
+  /* set the UART/USART in Half Duplex mode */
+  SET_BIT(USARTx->CR3, USART_CR3_HDSEL);
+}
+
+/**
+  * @brief  Perform basic configuration of USART for enabling use in Smartcard Mode
+  * @note   In Smartcard mode, the following bits must be kept cleared:
+  *           - LINEN bit in the USART_CR2 register,
+  *           - IREN bit in the USART_CR3 register,
+  *           - HDSEL bit in the USART_CR3 register.
+  *         This function also configures Stop bits to 1.5 bits and
+  *         sets the USART in Smartcard mode (SCEN bit).
+  *         Clock Output is also enabled (CLKEN).
+  * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @note   Call of this function is equivalent to following function call sequence :
+  *         - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
+  *         - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
+  *         - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
+  *         - Configure STOP in CR2 using @ref LL_USART_SetStopBitsLength() function
+  *         - Set CLKEN in CR2 using @ref LL_USART_EnableSCLKOutput() function
+  *         - Set SCEN in CR3 using @ref LL_USART_EnableSmartcard() function
+  * @note   Other remaining configurations items related to Smartcard Mode
+  *         (as Baud Rate, Word length, Parity, ...) should be set using
+  *         dedicated functions
+  * @rmtoll CR2          LINEN         LL_USART_ConfigSmartcardMode\n
+  *         CR2          STOP          LL_USART_ConfigSmartcardMode\n
+  *         CR2          CLKEN         LL_USART_ConfigSmartcardMode\n
+  *         CR3          HDSEL         LL_USART_ConfigSmartcardMode\n
+  *         CR3          SCEN          LL_USART_ConfigSmartcardMode
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ConfigSmartcardMode(USART_TypeDef *USARTx)
+{
+  /* In Smartcard mode, the following bits must be kept cleared:
+  - LINEN bit in the USART_CR2 register,
+  - IREN and HDSEL bits in the USART_CR3 register.*/
+  CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN));
+  CLEAR_BIT(USARTx->CR3, (USART_CR3_IREN | USART_CR3_HDSEL));
+  /* Configure Stop bits to 1.5 bits */
+  /* Synchronous mode is activated by default */
+  SET_BIT(USARTx->CR2, (USART_CR2_STOP_0 | USART_CR2_STOP_1 | USART_CR2_CLKEN));
+  /* set the UART/USART in Smartcard mode */
+  SET_BIT(USARTx->CR3, USART_CR3_SCEN);
+}
+
+/**
+  * @brief  Perform basic configuration of USART for enabling use in Irda Mode
+  * @note   In IRDA mode, the following bits must be kept cleared:
+  *           - LINEN bit in the USART_CR2 register,
+  *           - STOP and CLKEN bits in the USART_CR2 register,
+  *           - SCEN bit in the USART_CR3 register,
+  *           - HDSEL bit in the USART_CR3 register.
+  *         This function also sets the UART/USART in IRDA mode (IREN bit).
+  * @note   Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
+  *         IrDA feature is supported by the USARTx instance.
+  * @note   Call of this function is equivalent to following function call sequence :
+  *         - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
+  *         - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function
+  *         - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
+  *         - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
+  *         - Configure STOP in CR2 using @ref LL_USART_SetStopBitsLength() function
+  *         - Set IREN in CR3 using @ref LL_USART_EnableIrda() function
+  * @note   Other remaining configurations items related to Irda Mode
+  *         (as Baud Rate, Word length, Power mode, ...) should be set using
+  *         dedicated functions
+  * @rmtoll CR2          LINEN         LL_USART_ConfigIrdaMode\n
+  *         CR2          CLKEN         LL_USART_ConfigIrdaMode\n
+  *         CR2          STOP          LL_USART_ConfigIrdaMode\n
+  *         CR3          SCEN          LL_USART_ConfigIrdaMode\n
+  *         CR3          HDSEL         LL_USART_ConfigIrdaMode\n
+  *         CR3          IREN          LL_USART_ConfigIrdaMode
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ConfigIrdaMode(USART_TypeDef *USARTx)
+{
+  /* In IRDA mode, the following bits must be kept cleared:
+  - LINEN, STOP and CLKEN bits in the USART_CR2 register,
+  - SCEN and HDSEL bits in the USART_CR3 register.*/
+  CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN | USART_CR2_STOP));
+  CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL));
+  /* set the UART/USART in IRDA mode */
+  SET_BIT(USARTx->CR3, USART_CR3_IREN);
+}
+
+/**
+  * @brief  Perform basic configuration of USART for enabling use in Multi processor Mode
+  *         (several USARTs connected in a network, one of the USARTs can be the master,
+  *         its TX output connected to the RX inputs of the other slaves USARTs).
+  * @note   In MultiProcessor mode, the following bits must be kept cleared:
+  *           - LINEN bit in the USART_CR2 register,
+  *           - CLKEN bit in the USART_CR2 register,
+  *           - SCEN bit in the USART_CR3 register,
+  *           - IREN bit in the USART_CR3 register,
+  *           - HDSEL bit in the USART_CR3 register.
+  * @note   Call of this function is equivalent to following function call sequence :
+  *         - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
+  *         - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function
+  *         - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
+  *         - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
+  *         - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
+  * @note   Other remaining configurations items related to Multi processor Mode
+  *         (as Baud Rate, Wake Up Method, Node address, ...) should be set using
+  *         dedicated functions
+  * @rmtoll CR2          LINEN         LL_USART_ConfigMultiProcessMode\n
+  *         CR2          CLKEN         LL_USART_ConfigMultiProcessMode\n
+  *         CR3          SCEN          LL_USART_ConfigMultiProcessMode\n
+  *         CR3          HDSEL         LL_USART_ConfigMultiProcessMode\n
+  *         CR3          IREN          LL_USART_ConfigMultiProcessMode
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ConfigMultiProcessMode(USART_TypeDef *USARTx)
+{
+  /* In Multi Processor mode, the following bits must be kept cleared:
+  - LINEN and CLKEN bits in the USART_CR2 register,
+  - IREN, SCEN and HDSEL bits in the USART_CR3 register.*/
+  CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
+  CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EF_FLAG_Management FLAG_Management
+  * @{
+  */
+
+/**
+  * @brief  Check if the USART Parity Error Flag is set or not
+  * @rmtoll SR           PE            LL_USART_IsActiveFlag_PE
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_PE(USART_TypeDef *USARTx)
+{
+  return (READ_BIT(USARTx->SR, USART_SR_PE) == (USART_SR_PE));
+}
+
+/**
+  * @brief  Check if the USART Framing Error Flag is set or not
+  * @rmtoll SR           FE            LL_USART_IsActiveFlag_FE
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_FE(USART_TypeDef *USARTx)
+{
+  return (READ_BIT(USARTx->SR, USART_SR_FE) == (USART_SR_FE));
+}
+
+/**
+  * @brief  Check if the USART Noise error detected Flag is set or not
+  * @rmtoll SR           NF            LL_USART_IsActiveFlag_NE
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_NE(USART_TypeDef *USARTx)
+{
+  return (READ_BIT(USARTx->SR, USART_SR_NE) == (USART_SR_NE));
+}
+
+/**
+  * @brief  Check if the USART OverRun Error Flag is set or not
+  * @rmtoll SR           ORE           LL_USART_IsActiveFlag_ORE
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ORE(USART_TypeDef *USARTx)
+{
+  return (READ_BIT(USARTx->SR, USART_SR_ORE) == (USART_SR_ORE));
+}
+
+/**
+  * @brief  Check if the USART IDLE line detected Flag is set or not
+  * @rmtoll SR           IDLE          LL_USART_IsActiveFlag_IDLE
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_IDLE(USART_TypeDef *USARTx)
+{
+  return (READ_BIT(USARTx->SR, USART_SR_IDLE) == (USART_SR_IDLE));
+}
+
+/**
+  * @brief  Check if the USART Read Data Register Not Empty Flag is set or not
+  * @rmtoll SR           RXNE          LL_USART_IsActiveFlag_RXNE
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXNE(USART_TypeDef *USARTx)
+{
+  return (READ_BIT(USARTx->SR, USART_SR_RXNE) == (USART_SR_RXNE));
+}
+
+/**
+  * @brief  Check if the USART Transmission Complete Flag is set or not
+  * @rmtoll SR           TC            LL_USART_IsActiveFlag_TC
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TC(USART_TypeDef *USARTx)
+{
+  return (READ_BIT(USARTx->SR, USART_SR_TC) == (USART_SR_TC));
+}
+
+/**
+  * @brief  Check if the USART Transmit Data Register Empty Flag is set or not
+  * @rmtoll SR           TXE           LL_USART_IsActiveFlag_TXE
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXE(USART_TypeDef *USARTx)
+{
+  return (READ_BIT(USARTx->SR, USART_SR_TXE) == (USART_SR_TXE));
+}
+
+/**
+  * @brief  Check if the USART LIN Break Detection Flag is set or not
+  * @note   Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+  *         LIN feature is supported by the USARTx instance.
+  * @rmtoll SR           LBD           LL_USART_IsActiveFlag_LBD
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_LBD(USART_TypeDef *USARTx)
+{
+  return (READ_BIT(USARTx->SR, USART_SR_LBD) == (USART_SR_LBD));
+}
+
+/**
+  * @brief  Check if the USART CTS Flag is set or not
+  * @note   Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+  *         Hardware Flow control feature is supported by the USARTx instance.
+  * @rmtoll SR           CTS           LL_USART_IsActiveFlag_nCTS
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_nCTS(USART_TypeDef *USARTx)
+{
+  return (READ_BIT(USARTx->SR, USART_SR_CTS) == (USART_SR_CTS));
+}
+
+/**
+  * @brief  Check if the USART Send Break Flag is set or not
+  * @rmtoll CR1          SBK           LL_USART_IsActiveFlag_SBK
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_SBK(USART_TypeDef *USARTx)
+{
+  return (READ_BIT(USARTx->CR1, USART_CR1_SBK) == (USART_CR1_SBK));
+}
+
+/**
+  * @brief  Check if the USART Receive Wake Up from mute mode Flag is set or not
+  * @rmtoll CR1          RWU           LL_USART_IsActiveFlag_RWU
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RWU(USART_TypeDef *USARTx)
+{
+  return (READ_BIT(USARTx->CR1, USART_CR1_RWU) == (USART_CR1_RWU));
+}
+
+/**
+  * @brief  Clear Parity Error Flag
+  * @note   Clearing this flag is done by a read access to the USARTx_SR
+  *         register followed by a read access to the USARTx_DR register.
+  * @note   Please also consider that when clearing this flag, other flags as
+  *         NE, FE, ORE, IDLE would also be cleared.
+  * @rmtoll SR           PE            LL_USART_ClearFlag_PE
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ClearFlag_PE(USART_TypeDef *USARTx)
+{
+  __IO uint32_t tmpreg;
+  tmpreg = USARTx->SR;
+  (void) tmpreg;
+  tmpreg = USARTx->DR;
+  (void) tmpreg;
+}
+
+/**
+  * @brief  Clear Framing Error Flag
+  * @note   Clearing this flag is done by a read access to the USARTx_SR
+  *         register followed by a read access to the USARTx_DR register.
+  * @note   Please also consider that when clearing this flag, other flags as
+  *         PE, NE, ORE, IDLE would also be cleared.
+  * @rmtoll SR           FE            LL_USART_ClearFlag_FE
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ClearFlag_FE(USART_TypeDef *USARTx)
+{
+  __IO uint32_t tmpreg;
+  tmpreg = USARTx->SR;
+  (void) tmpreg;
+  tmpreg = USARTx->DR;
+  (void) tmpreg;
+}
+
+/**
+  * @brief  Clear Noise detected Flag
+  * @note   Clearing this flag is done by a read access to the USARTx_SR
+  *         register followed by a read access to the USARTx_DR register.
+  * @note   Please also consider that when clearing this flag, other flags as
+  *         PE, FE, ORE, IDLE would also be cleared.
+  * @rmtoll SR           NF            LL_USART_ClearFlag_NE
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ClearFlag_NE(USART_TypeDef *USARTx)
+{
+  __IO uint32_t tmpreg;
+  tmpreg = USARTx->SR;
+  (void) tmpreg;
+  tmpreg = USARTx->DR;
+  (void) tmpreg;
+}
+
+/**
+  * @brief  Clear OverRun Error Flag
+  * @note   Clearing this flag is done by a read access to the USARTx_SR
+  *         register followed by a read access to the USARTx_DR register.
+  * @note   Please also consider that when clearing this flag, other flags as
+  *         PE, NE, FE, IDLE would also be cleared.
+  * @rmtoll SR           ORE           LL_USART_ClearFlag_ORE
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ClearFlag_ORE(USART_TypeDef *USARTx)
+{
+  __IO uint32_t tmpreg;
+  tmpreg = USARTx->SR;
+  (void) tmpreg;
+  tmpreg = USARTx->DR;
+  (void) tmpreg;
+}
+
+/**
+  * @brief  Clear IDLE line detected Flag
+  * @note   Clearing this flag is done by a read access to the USARTx_SR
+  *         register followed by a read access to the USARTx_DR register.
+  * @note   Please also consider that when clearing this flag, other flags as
+  *         PE, NE, FE, ORE would also be cleared.
+  * @rmtoll SR           IDLE          LL_USART_ClearFlag_IDLE
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ClearFlag_IDLE(USART_TypeDef *USARTx)
+{
+  __IO uint32_t tmpreg;
+  tmpreg = USARTx->SR;
+  (void) tmpreg;
+  tmpreg = USARTx->DR;
+  (void) tmpreg;
+}
+
+/**
+  * @brief  Clear Transmission Complete Flag
+  * @rmtoll SR           TC            LL_USART_ClearFlag_TC
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ClearFlag_TC(USART_TypeDef *USARTx)
+{
+  WRITE_REG(USARTx->SR, ~(USART_SR_TC));
+}
+
+/**
+  * @brief  Clear RX Not Empty Flag
+  * @rmtoll SR           RXNE          LL_USART_ClearFlag_RXNE
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ClearFlag_RXNE(USART_TypeDef *USARTx)
+{
+  WRITE_REG(USARTx->SR, ~(USART_SR_RXNE));
+}
+
+/**
+  * @brief  Clear LIN Break Detection Flag
+  * @note   Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+  *         LIN feature is supported by the USARTx instance.
+  * @rmtoll SR           LBD           LL_USART_ClearFlag_LBD
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ClearFlag_LBD(USART_TypeDef *USARTx)
+{
+  WRITE_REG(USARTx->SR, ~(USART_SR_LBD));
+}
+
+/**
+  * @brief  Clear CTS Interrupt Flag
+  * @note   Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+  *         Hardware Flow control feature is supported by the USARTx instance.
+  * @rmtoll SR           CTS           LL_USART_ClearFlag_nCTS
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ClearFlag_nCTS(USART_TypeDef *USARTx)
+{
+  WRITE_REG(USARTx->SR, ~(USART_SR_CTS));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EF_IT_Management IT_Management
+  * @{
+  */
+
+/**
+  * @brief  Enable IDLE Interrupt
+  * @rmtoll CR1          IDLEIE        LL_USART_EnableIT_IDLE
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableIT_IDLE(USART_TypeDef *USARTx)
+{
+  ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_IDLEIE);
+}
+
+/**
+  * @brief  Enable RX Not Empty Interrupt
+  * @rmtoll CR1          RXNEIE        LL_USART_EnableIT_RXNE
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableIT_RXNE(USART_TypeDef *USARTx)
+{
+  ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_RXNEIE);
+}
+
+/**
+  * @brief  Enable Transmission Complete Interrupt
+  * @rmtoll CR1          TCIE          LL_USART_EnableIT_TC
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableIT_TC(USART_TypeDef *USARTx)
+{
+  ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_TCIE);
+}
+
+/**
+  * @brief  Enable TX Empty Interrupt
+  * @rmtoll CR1          TXEIE         LL_USART_EnableIT_TXE
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableIT_TXE(USART_TypeDef *USARTx)
+{
+  ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_TXEIE);
+}
+
+/**
+  * @brief  Enable Parity Error Interrupt
+  * @rmtoll CR1          PEIE          LL_USART_EnableIT_PE
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableIT_PE(USART_TypeDef *USARTx)
+{
+  ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_PEIE);
+}
+
+/**
+  * @brief  Enable LIN Break Detection Interrupt
+  * @note   Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+  *         LIN feature is supported by the USARTx instance.
+  * @rmtoll CR2          LBDIE         LL_USART_EnableIT_LBD
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableIT_LBD(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR2, USART_CR2_LBDIE);
+}
+
+/**
+  * @brief  Enable Error Interrupt
+  * @note   When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing
+  *         error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the USARTx_SR register).
+  *           0: Interrupt is inhibited
+  *           1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the USARTx_SR register.
+  * @rmtoll CR3          EIE           LL_USART_EnableIT_ERROR
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableIT_ERROR(USART_TypeDef *USARTx)
+{
+  ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_EIE);
+}
+
+/**
+  * @brief  Enable CTS Interrupt
+  * @note   Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+  *         Hardware Flow control feature is supported by the USARTx instance.
+  * @rmtoll CR3          CTSIE         LL_USART_EnableIT_CTS
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableIT_CTS(USART_TypeDef *USARTx)
+{
+  ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_CTSIE);
+}
+
+/**
+  * @brief  Disable IDLE Interrupt
+  * @rmtoll CR1          IDLEIE        LL_USART_DisableIT_IDLE
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableIT_IDLE(USART_TypeDef *USARTx)
+{
+  ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_IDLEIE);
+}
+
+/**
+  * @brief  Disable RX Not Empty Interrupt
+  * @rmtoll CR1          RXNEIE        LL_USART_DisableIT_RXNE
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableIT_RXNE(USART_TypeDef *USARTx)
+{
+  ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_RXNEIE);
+}
+
+/**
+  * @brief  Disable Transmission Complete Interrupt
+  * @rmtoll CR1          TCIE          LL_USART_DisableIT_TC
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableIT_TC(USART_TypeDef *USARTx)
+{
+  ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_TCIE);
+}
+
+/**
+  * @brief  Disable TX Empty Interrupt
+  * @rmtoll CR1          TXEIE         LL_USART_DisableIT_TXE
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableIT_TXE(USART_TypeDef *USARTx)
+{
+  ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_TXEIE);
+}
+
+/**
+  * @brief  Disable Parity Error Interrupt
+  * @rmtoll CR1          PEIE          LL_USART_DisableIT_PE
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableIT_PE(USART_TypeDef *USARTx)
+{
+  ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_PEIE);
+}
+
+/**
+  * @brief  Disable LIN Break Detection Interrupt
+  * @note   Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+  *         LIN feature is supported by the USARTx instance.
+  * @rmtoll CR2          LBDIE         LL_USART_DisableIT_LBD
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableIT_LBD(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR2, USART_CR2_LBDIE);
+}
+
+/**
+  * @brief  Disable Error Interrupt
+  * @note   When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing
+  *         error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the USARTx_SR register).
+  *           0: Interrupt is inhibited
+  *           1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the USARTx_SR register.
+  * @rmtoll CR3          EIE           LL_USART_DisableIT_ERROR
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableIT_ERROR(USART_TypeDef *USARTx)
+{
+  ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_EIE);
+}
+
+/**
+  * @brief  Disable CTS Interrupt
+  * @note   Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+  *         Hardware Flow control feature is supported by the USARTx instance.
+  * @rmtoll CR3          CTSIE         LL_USART_DisableIT_CTS
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableIT_CTS(USART_TypeDef *USARTx)
+{
+  ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_CTSIE);
+}
+
+/**
+  * @brief  Check if the USART IDLE Interrupt  source is enabled or disabled.
+  * @rmtoll CR1          IDLEIE        LL_USART_IsEnabledIT_IDLE
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_IDLE(USART_TypeDef *USARTx)
+{
+  return (READ_BIT(USARTx->CR1, USART_CR1_IDLEIE) == (USART_CR1_IDLEIE));
+}
+
+/**
+  * @brief  Check if the USART RX Not Empty Interrupt is enabled or disabled.
+  * @rmtoll CR1          RXNEIE        LL_USART_IsEnabledIT_RXNE
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXNE(USART_TypeDef *USARTx)
+{
+  return (READ_BIT(USARTx->CR1, USART_CR1_RXNEIE) == (USART_CR1_RXNEIE));
+}
+
+/**
+  * @brief  Check if the USART Transmission Complete Interrupt is enabled or disabled.
+  * @rmtoll CR1          TCIE          LL_USART_IsEnabledIT_TC
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TC(USART_TypeDef *USARTx)
+{
+  return (READ_BIT(USARTx->CR1, USART_CR1_TCIE) == (USART_CR1_TCIE));
+}
+
+/**
+  * @brief  Check if the USART TX Empty Interrupt is enabled or disabled.
+  * @rmtoll CR1          TXEIE         LL_USART_IsEnabledIT_TXE
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXE(USART_TypeDef *USARTx)
+{
+  return (READ_BIT(USARTx->CR1, USART_CR1_TXEIE) == (USART_CR1_TXEIE));
+}
+
+/**
+  * @brief  Check if the USART Parity Error Interrupt is enabled or disabled.
+  * @rmtoll CR1          PEIE          LL_USART_IsEnabledIT_PE
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_PE(USART_TypeDef *USARTx)
+{
+  return (READ_BIT(USARTx->CR1, USART_CR1_PEIE) == (USART_CR1_PEIE));
+}
+
+/**
+  * @brief  Check if the USART LIN Break Detection Interrupt is enabled or disabled.
+  * @note   Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+  *         LIN feature is supported by the USARTx instance.
+  * @rmtoll CR2          LBDIE         LL_USART_IsEnabledIT_LBD
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_LBD(USART_TypeDef *USARTx)
+{
+  return (READ_BIT(USARTx->CR2, USART_CR2_LBDIE) == (USART_CR2_LBDIE));
+}
+
+/**
+  * @brief  Check if the USART Error Interrupt is enabled or disabled.
+  * @rmtoll CR3          EIE           LL_USART_IsEnabledIT_ERROR
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_ERROR(USART_TypeDef *USARTx)
+{
+  return (READ_BIT(USARTx->CR3, USART_CR3_EIE) == (USART_CR3_EIE));
+}
+
+/**
+  * @brief  Check if the USART CTS Interrupt is enabled or disabled.
+  * @note   Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+  *         Hardware Flow control feature is supported by the USARTx instance.
+  * @rmtoll CR3          CTSIE         LL_USART_IsEnabledIT_CTS
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_CTS(USART_TypeDef *USARTx)
+{
+  return (READ_BIT(USARTx->CR3, USART_CR3_CTSIE) == (USART_CR3_CTSIE));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EF_DMA_Management DMA_Management
+  * @{
+  */
+
+/**
+  * @brief  Enable DMA Mode for reception
+  * @rmtoll CR3          DMAR          LL_USART_EnableDMAReq_RX
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableDMAReq_RX(USART_TypeDef *USARTx)
+{
+  ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_DMAR);
+}
+
+/**
+  * @brief  Disable DMA Mode for reception
+  * @rmtoll CR3          DMAR          LL_USART_DisableDMAReq_RX
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableDMAReq_RX(USART_TypeDef *USARTx)
+{
+  ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_DMAR);
+}
+
+/**
+  * @brief  Check if DMA Mode is enabled for reception
+  * @rmtoll CR3          DMAR          LL_USART_IsEnabledDMAReq_RX
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_RX(USART_TypeDef *USARTx)
+{
+  return (READ_BIT(USARTx->CR3, USART_CR3_DMAR) == (USART_CR3_DMAR));
+}
+
+/**
+  * @brief  Enable DMA Mode for transmission
+  * @rmtoll CR3          DMAT          LL_USART_EnableDMAReq_TX
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableDMAReq_TX(USART_TypeDef *USARTx)
+{
+  ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_DMAT);
+}
+
+/**
+  * @brief  Disable DMA Mode for transmission
+  * @rmtoll CR3          DMAT          LL_USART_DisableDMAReq_TX
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableDMAReq_TX(USART_TypeDef *USARTx)
+{
+  ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_DMAT);
+}
+
+/**
+  * @brief  Check if DMA Mode is enabled for transmission
+  * @rmtoll CR3          DMAT          LL_USART_IsEnabledDMAReq_TX
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_TX(USART_TypeDef *USARTx)
+{
+  return (READ_BIT(USARTx->CR3, USART_CR3_DMAT) == (USART_CR3_DMAT));
+}
+
+/**
+  * @brief  Get the data register address used for DMA transfer
+  * @rmtoll DR           DR            LL_USART_DMA_GetRegAddr
+  * @note   Address of Data Register is valid for both Transmit and Receive transfers.
+  * @param  USARTx USART Instance
+  * @retval Address of data register
+  */
+__STATIC_INLINE uint32_t LL_USART_DMA_GetRegAddr(USART_TypeDef *USARTx)
+{
+  /* return address of DR register */
+  return ((uint32_t) &(USARTx->DR));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EF_Data_Management Data_Management
+  * @{
+  */
+
+/**
+  * @brief  Read Receiver Data register (Receive Data value, 8 bits)
+  * @rmtoll DR           DR            LL_USART_ReceiveData8
+  * @param  USARTx USART Instance
+  * @retval Value between Min_Data=0x00 and Max_Data=0xFF
+  */
+__STATIC_INLINE uint8_t LL_USART_ReceiveData8(USART_TypeDef *USARTx)
+{
+  return (uint8_t)(READ_BIT(USARTx->DR, USART_DR_DR));
+}
+
+/**
+  * @brief  Read Receiver Data register (Receive Data value, 9 bits)
+  * @rmtoll DR           DR            LL_USART_ReceiveData9
+  * @param  USARTx USART Instance
+  * @retval Value between Min_Data=0x00 and Max_Data=0x1FF
+  */
+__STATIC_INLINE uint16_t LL_USART_ReceiveData9(USART_TypeDef *USARTx)
+{
+  return (uint16_t)(READ_BIT(USARTx->DR, USART_DR_DR));
+}
+
+/**
+  * @brief  Write in Transmitter Data Register (Transmit Data value, 8 bits)
+  * @rmtoll DR           DR            LL_USART_TransmitData8
+  * @param  USARTx USART Instance
+  * @param  Value between Min_Data=0x00 and Max_Data=0xFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_TransmitData8(USART_TypeDef *USARTx, uint8_t Value)
+{
+  USARTx->DR = Value;
+}
+
+/**
+  * @brief  Write in Transmitter Data Register (Transmit Data value, 9 bits)
+  * @rmtoll DR           DR            LL_USART_TransmitData9
+  * @param  USARTx USART Instance
+  * @param  Value between Min_Data=0x00 and Max_Data=0x1FF
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_TransmitData9(USART_TypeDef *USARTx, uint16_t Value)
+{
+  USARTx->DR = Value & 0x1FFU;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EF_Execution Execution
+  * @{
+  */
+
+/**
+  * @brief  Request Break sending
+  * @rmtoll CR1          SBK           LL_USART_RequestBreakSending
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_RequestBreakSending(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR1, USART_CR1_SBK);
+}
+
+/**
+  * @brief  Put USART in Mute mode
+  * @rmtoll CR1          RWU           LL_USART_RequestEnterMuteMode
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_RequestEnterMuteMode(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR1, USART_CR1_RWU);
+}
+
+/**
+  * @brief  Put USART in Active mode
+  * @rmtoll CR1          RWU           LL_USART_RequestExitMuteMode
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_RequestExitMuteMode(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR1, USART_CR1_RWU);
+}
+
+/**
+  * @}
+  */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup USART_LL_EF_Init Initialization and de-initialization functions
+  * @{
+  */
+ErrorStatus LL_USART_DeInit(USART_TypeDef *USARTx);
+ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, LL_USART_InitTypeDef *USART_InitStruct);
+void        LL_USART_StructInit(LL_USART_InitTypeDef *USART_InitStruct);
+ErrorStatus LL_USART_ClockInit(USART_TypeDef *USARTx, LL_USART_ClockInitTypeDef *USART_ClockInitStruct);
+void        LL_USART_ClockStructInit(LL_USART_ClockInitTypeDef *USART_ClockInitStruct);
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* USART1 || USART2 || USART3 || USART6 || UART4 || UART5 || UART7 || UART8 || UART9 || UART10 */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_LL_USART_H */
+
diff --git a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usb.h b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usb.h
new file mode 100644
index 0000000..a50d49d
--- /dev/null
+++ b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usb.h
@@ -0,0 +1,536 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_ll_usb.h
+  * @author  MCD Application Team
+  * @brief   Header file of USB Low Layer HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2016 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32F4xx_LL_USB_H
+#define STM32F4xx_LL_USB_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
+/** @addtogroup STM32F4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup USB_LL
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+
+/**
+  * @brief  USB Mode definition
+  */
+#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
+
+typedef enum
+{
+  USB_DEVICE_MODE  = 0,
+  USB_HOST_MODE    = 1,
+  USB_DRD_MODE     = 2
+} USB_OTG_ModeTypeDef;
+
+/**
+  * @brief  URB States definition
+  */
+typedef enum
+{
+  URB_IDLE = 0,
+  URB_DONE,
+  URB_NOTREADY,
+  URB_NYET,
+  URB_ERROR,
+  URB_STALL
+} USB_OTG_URBStateTypeDef;
+
+/**
+  * @brief  Host channel States  definition
+  */
+typedef enum
+{
+  HC_IDLE = 0,
+  HC_XFRC,
+  HC_HALTED,
+  HC_NAK,
+  HC_NYET,
+  HC_STALL,
+  HC_XACTERR,
+  HC_BBLERR,
+  HC_DATATGLERR
+} USB_OTG_HCStateTypeDef;
+
+
+/**
+  * @brief  USB Instance Initialization Structure definition
+  */
+typedef struct
+{
+  uint32_t dev_endpoints;           /*!< Device Endpoints number.
+                                         This parameter depends on the used USB core.
+                                         This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
+
+  uint32_t Host_channels;           /*!< Host Channels number.
+                                         This parameter Depends on the used USB core.
+                                         This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
+
+  uint32_t speed;                   /*!< USB Core speed.
+                                         This parameter can be any value of @ref PCD_Speed/HCD_Speed
+                                                                                 (HCD_SPEED_xxx, HCD_SPEED_xxx) */
+
+  uint32_t dma_enable;              /*!< Enable or disable of the USB embedded DMA used only for OTG HS.        */
+
+  uint32_t ep0_mps;                 /*!< Set the Endpoint 0 Max Packet size.                                    */
+
+  uint32_t phy_itface;              /*!< Select the used PHY interface.
+                                         This parameter can be any value of @ref PCD_PHY_Module/HCD_PHY_Module  */
+
+  uint32_t Sof_enable;              /*!< Enable or disable the output of the SOF signal.                        */
+
+  uint32_t low_power_enable;        /*!< Enable or disable the low power mode.                                  */
+
+  uint32_t lpm_enable;              /*!< Enable or disable Link Power Management.                               */
+
+  uint32_t battery_charging_enable; /*!< Enable or disable Battery charging.                                    */
+
+  uint32_t vbus_sensing_enable;     /*!< Enable or disable the VBUS Sensing feature.                            */
+
+  uint32_t use_dedicated_ep1;       /*!< Enable or disable the use of the dedicated EP1 interrupt.              */
+
+  uint32_t use_external_vbus;       /*!< Enable or disable the use of the external VBUS.                        */
+
+} USB_OTG_CfgTypeDef;
+
+typedef struct
+{
+  uint8_t   num;                  /*!< Endpoint number
+                                       This parameter must be a number between Min_Data = 1 and Max_Data = 15   */
+
+  uint8_t   is_in;                /*!< Endpoint direction
+                                       This parameter must be a number between Min_Data = 0 and Max_Data = 1    */
+
+  uint8_t   is_stall;             /*!< Endpoint stall condition
+                                       This parameter must be a number between Min_Data = 0 and Max_Data = 1    */
+
+  uint8_t   is_iso_incomplete;    /*!< Endpoint isoc condition
+                                       This parameter must be a number between Min_Data = 0 and Max_Data = 1    */
+
+  uint8_t   type;                 /*!< Endpoint type
+                                       This parameter can be any value of @ref USB_LL_EP_Type                   */
+
+  uint8_t   data_pid_start;       /*!< Initial data PID
+                                       This parameter must be a number between Min_Data = 0 and Max_Data = 1    */
+
+  uint8_t   even_odd_frame;       /*!< IFrame parity
+                                       This parameter must be a number between Min_Data = 0 and Max_Data = 1    */
+
+  uint16_t  tx_fifo_num;          /*!< Transmission FIFO number
+                                       This parameter must be a number between Min_Data = 1 and Max_Data = 15   */
+
+  uint32_t  maxpacket;            /*!< Endpoint Max packet size
+                                       This parameter must be a number between Min_Data = 0 and Max_Data = 64KB */
+
+  uint8_t   *xfer_buff;           /*!< Pointer to transfer buffer                                               */
+
+  uint32_t  dma_addr;             /*!< 32 bits aligned transfer buffer address                                  */
+
+  uint32_t  xfer_len;             /*!< Current transfer length                                                  */
+
+  uint32_t  xfer_size;            /*!< requested transfer size                                                  */
+
+  uint32_t  xfer_count;           /*!< Partial transfer length in case of multi packet transfer                 */
+} USB_OTG_EPTypeDef;
+
+typedef struct
+{
+  uint8_t   dev_addr;           /*!< USB device address.
+                                     This parameter must be a number between Min_Data = 1 and Max_Data = 255    */
+
+  uint8_t   ch_num;             /*!< Host channel number.
+                                     This parameter must be a number between Min_Data = 1 and Max_Data = 15     */
+
+  uint8_t   ep_num;             /*!< Endpoint number.
+                                     This parameter must be a number between Min_Data = 1 and Max_Data = 15     */
+
+  uint8_t   ep_is_in;           /*!< Endpoint direction
+                                     This parameter must be a number between Min_Data = 0 and Max_Data = 1      */
+
+  uint8_t   speed;              /*!< USB Host Channel speed.
+                                     This parameter can be any value of @ref HCD_Device_Speed:
+                                                                             (HCD_DEVICE_SPEED_xxx)             */
+
+  uint8_t   do_ping;            /*!< Enable or disable the use of the PING protocol for HS mode.                */
+
+  uint8_t   process_ping;       /*!< Execute the PING protocol for HS mode.                                     */
+
+  uint8_t   ep_type;            /*!< Endpoint Type.
+                                     This parameter can be any value of @ref USB_LL_EP_Type                     */
+
+  uint16_t  max_packet;         /*!< Endpoint Max packet size.
+                                     This parameter must be a number between Min_Data = 0 and Max_Data = 64KB   */
+
+  uint8_t   data_pid;           /*!< Initial data PID.
+                                     This parameter must be a number between Min_Data = 0 and Max_Data = 1      */
+
+  uint8_t   *xfer_buff;         /*!< Pointer to transfer buffer.                                                */
+
+  uint32_t  XferSize;             /*!< OTG Channel transfer size.                                               */
+
+  uint32_t  xfer_len;           /*!< Current transfer length.                                                   */
+
+  uint32_t  xfer_count;         /*!< Partial transfer length in case of multi packet transfer.                  */
+
+  uint8_t   toggle_in;          /*!< IN transfer current toggle flag.
+                                     This parameter must be a number between Min_Data = 0 and Max_Data = 1      */
+
+  uint8_t   toggle_out;         /*!< OUT transfer current toggle flag
+                                     This parameter must be a number between Min_Data = 0 and Max_Data = 1      */
+
+  uint32_t  dma_addr;           /*!< 32 bits aligned transfer buffer address.                                   */
+
+  uint32_t  ErrCnt;             /*!< Host channel error count.                                                  */
+
+  USB_OTG_URBStateTypeDef urb_state;  /*!< URB state.
+                                            This parameter can be any value of @ref USB_OTG_URBStateTypeDef */
+
+  USB_OTG_HCStateTypeDef state;       /*!< Host Channel state.
+                                            This parameter can be any value of @ref USB_OTG_HCStateTypeDef  */
+} USB_OTG_HCTypeDef;
+#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
+
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup PCD_Exported_Constants PCD Exported Constants
+  * @{
+  */
+
+#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
+/** @defgroup USB_OTG_CORE VERSION ID
+  * @{
+  */
+#define USB_OTG_CORE_ID_300A          0x4F54300AU
+#define USB_OTG_CORE_ID_310A          0x4F54310AU
+/**
+  * @}
+  */
+
+/** @defgroup USB_Core_Mode_ USB Core Mode
+  * @{
+  */
+#define USB_OTG_MODE_DEVICE                    0U
+#define USB_OTG_MODE_HOST                      1U
+#define USB_OTG_MODE_DRD                       2U
+/**
+  * @}
+  */
+
+/** @defgroup USB_LL Device Speed
+  * @{
+  */
+#define USBD_HS_SPEED                          0U
+#define USBD_HSINFS_SPEED                      1U
+#define USBH_HS_SPEED                          0U
+#define USBD_FS_SPEED                          2U
+#define USBH_FSLS_SPEED                        1U
+/**
+  * @}
+  */
+
+/** @defgroup USB_LL_Core_Speed USB Low Layer Core Speed
+  * @{
+  */
+#define USB_OTG_SPEED_HIGH                     0U
+#define USB_OTG_SPEED_HIGH_IN_FULL             1U
+#define USB_OTG_SPEED_FULL                     3U
+/**
+  * @}
+  */
+
+/** @defgroup USB_LL_Core_PHY USB Low Layer Core PHY
+  * @{
+  */
+#define USB_OTG_ULPI_PHY                       1U
+#define USB_OTG_EMBEDDED_PHY                   2U
+/**
+  * @}
+  */
+
+/** @defgroup USB_LL_Turnaround_Timeout Turnaround Timeout Value
+  * @{
+  */
+#ifndef USBD_HS_TRDT_VALUE
+#define USBD_HS_TRDT_VALUE                     9U
+#endif /* USBD_HS_TRDT_VALUE */
+#ifndef USBD_FS_TRDT_VALUE
+#define USBD_FS_TRDT_VALUE                     5U
+#define USBD_DEFAULT_TRDT_VALUE                9U
+#endif /* USBD_HS_TRDT_VALUE */
+/**
+  * @}
+  */
+
+/** @defgroup USB_LL_Core_MPS USB Low Layer Core MPS
+  * @{
+  */
+#define USB_OTG_HS_MAX_PACKET_SIZE           512U
+#define USB_OTG_FS_MAX_PACKET_SIZE            64U
+#define USB_OTG_MAX_EP0_SIZE                  64U
+/**
+  * @}
+  */
+
+/** @defgroup USB_LL_Core_PHY_Frequency USB Low Layer Core PHY Frequency
+  * @{
+  */
+#define DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ     (0U << 1)
+#define DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ     (1U << 1)
+#define DSTS_ENUMSPD_FS_PHY_48MHZ              (3U << 1)
+/**
+  * @}
+  */
+
+/** @defgroup USB_LL_CORE_Frame_Interval USB Low Layer Core Frame Interval
+  * @{
+  */
+#define DCFG_FRAME_INTERVAL_80                 0U
+#define DCFG_FRAME_INTERVAL_85                 1U
+#define DCFG_FRAME_INTERVAL_90                 2U
+#define DCFG_FRAME_INTERVAL_95                 3U
+/**
+  * @}
+  */
+
+/** @defgroup USB_LL_EP0_MPS USB Low Layer EP0 MPS
+  * @{
+  */
+#define EP_MPS_64                              0U
+#define EP_MPS_32                              1U
+#define EP_MPS_16                              2U
+#define EP_MPS_8                               3U
+/**
+  * @}
+  */
+
+/** @defgroup USB_LL_EP_Speed USB Low Layer EP Speed
+  * @{
+  */
+#define EP_SPEED_LOW                           0U
+#define EP_SPEED_FULL                          1U
+#define EP_SPEED_HIGH                          2U
+/**
+  * @}
+  */
+
+/** @defgroup USB_LL_EP_Type USB Low Layer EP Type
+  * @{
+  */
+#define EP_TYPE_CTRL                           0U
+#define EP_TYPE_ISOC                           1U
+#define EP_TYPE_BULK                           2U
+#define EP_TYPE_INTR                           3U
+#define EP_TYPE_MSK                            3U
+/**
+  * @}
+  */
+
+/** @defgroup USB_LL_STS_Defines USB Low Layer STS Defines
+  * @{
+  */
+#define STS_GOUT_NAK                           1U
+#define STS_DATA_UPDT                          2U
+#define STS_XFER_COMP                          3U
+#define STS_SETUP_COMP                         4U
+#define STS_SETUP_UPDT                         6U
+/**
+  * @}
+  */
+
+/** @defgroup USB_LL_HCFG_SPEED_Defines USB Low Layer HCFG Speed Defines
+  * @{
+  */
+#define HCFG_30_60_MHZ                         0U
+#define HCFG_48_MHZ                            1U
+#define HCFG_6_MHZ                             2U
+/**
+  * @}
+  */
+
+/** @defgroup USB_LL_HPRT0_PRTSPD_SPEED_Defines USB Low Layer HPRT0 PRTSPD Speed Defines
+  * @{
+  */
+#define HPRT0_PRTSPD_HIGH_SPEED                0U
+#define HPRT0_PRTSPD_FULL_SPEED                1U
+#define HPRT0_PRTSPD_LOW_SPEED                 2U
+/**
+  * @}
+  */
+
+#define HCCHAR_CTRL                            0U
+#define HCCHAR_ISOC                            1U
+#define HCCHAR_BULK                            2U
+#define HCCHAR_INTR                            3U
+
+#define HC_PID_DATA0                           0U
+#define HC_PID_DATA2                           1U
+#define HC_PID_DATA1                           2U
+#define HC_PID_SETUP                           3U
+
+#define GRXSTS_PKTSTS_IN                       2U
+#define GRXSTS_PKTSTS_IN_XFER_COMP             3U
+#define GRXSTS_PKTSTS_DATA_TOGGLE_ERR          5U
+#define GRXSTS_PKTSTS_CH_HALTED                7U
+
+#define TEST_J                                 1U
+#define TEST_K                                 2U
+#define TEST_SE0_NAK                           3U
+#define TEST_PACKET                            4U
+#define TEST_FORCE_EN                          5U
+
+#define USBx_PCGCCTL    *(__IO uint32_t *)((uint32_t)USBx_BASE + USB_OTG_PCGCCTL_BASE)
+#define USBx_HPRT0      *(__IO uint32_t *)((uint32_t)USBx_BASE + USB_OTG_HOST_PORT_BASE)
+
+#define USBx_DEVICE     ((USB_OTG_DeviceTypeDef *)(USBx_BASE + USB_OTG_DEVICE_BASE))
+#define USBx_INEP(i)    ((USB_OTG_INEndpointTypeDef *)(USBx_BASE\
+                                                       + USB_OTG_IN_ENDPOINT_BASE + ((i) * USB_OTG_EP_REG_SIZE)))
+
+#define USBx_OUTEP(i)   ((USB_OTG_OUTEndpointTypeDef *)(USBx_BASE\
+                                                        + USB_OTG_OUT_ENDPOINT_BASE + ((i) * USB_OTG_EP_REG_SIZE)))
+
+#define USBx_DFIFO(i)   *(__IO uint32_t *)(USBx_BASE + USB_OTG_FIFO_BASE + ((i) * USB_OTG_FIFO_SIZE))
+
+#define USBx_HOST       ((USB_OTG_HostTypeDef *)(USBx_BASE + USB_OTG_HOST_BASE))
+#define USBx_HC(i)      ((USB_OTG_HostChannelTypeDef *)(USBx_BASE\
+                                                        + USB_OTG_HOST_CHANNEL_BASE\
+                                                        + ((i) * USB_OTG_HOST_CHANNEL_SIZE)))
+
+#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
+
+#define EP_ADDR_MSK                            0xFU
+
+#ifndef USE_USB_DOUBLE_BUFFER
+#define USE_USB_DOUBLE_BUFFER                  1U
+#endif /* USE_USB_DOUBLE_BUFFER */
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup USB_LL_Exported_Macros USB Low Layer Exported Macros
+  * @{
+  */
+#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
+#define USB_MASK_INTERRUPT(__INSTANCE__, __INTERRUPT__)     ((__INSTANCE__)->GINTMSK &= ~(__INTERRUPT__))
+#define USB_UNMASK_INTERRUPT(__INSTANCE__, __INTERRUPT__)   ((__INSTANCE__)->GINTMSK |= (__INTERRUPT__))
+
+#define CLEAR_IN_EP_INTR(__EPNUM__, __INTERRUPT__)          (USBx_INEP(__EPNUM__)->DIEPINT = (__INTERRUPT__))
+#define CLEAR_OUT_EP_INTR(__EPNUM__, __INTERRUPT__)         (USBx_OUTEP(__EPNUM__)->DOEPINT = (__INTERRUPT__))
+#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup USB_LL_Exported_Functions USB Low Layer Exported Functions
+  * @{
+  */
+#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
+HAL_StatusTypeDef USB_CoreInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg);
+HAL_StatusTypeDef USB_DevInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg);
+HAL_StatusTypeDef USB_EnableGlobalInt(USB_OTG_GlobalTypeDef *USBx);
+HAL_StatusTypeDef USB_DisableGlobalInt(USB_OTG_GlobalTypeDef *USBx);
+HAL_StatusTypeDef USB_SetTurnaroundTime(USB_OTG_GlobalTypeDef *USBx, uint32_t hclk, uint8_t speed);
+HAL_StatusTypeDef USB_SetCurrentMode(USB_OTG_GlobalTypeDef *USBx, USB_OTG_ModeTypeDef mode);
+HAL_StatusTypeDef USB_SetDevSpeed(USB_OTG_GlobalTypeDef *USBx, uint8_t speed);
+HAL_StatusTypeDef USB_FlushRxFifo(USB_OTG_GlobalTypeDef *USBx);
+HAL_StatusTypeDef USB_FlushTxFifo(USB_OTG_GlobalTypeDef *USBx, uint32_t num);
+HAL_StatusTypeDef USB_ActivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
+HAL_StatusTypeDef USB_DeactivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
+HAL_StatusTypeDef USB_ActivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
+HAL_StatusTypeDef USB_DeactivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
+HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep, uint8_t dma);
+HAL_StatusTypeDef USB_EP0StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep, uint8_t dma);
+HAL_StatusTypeDef USB_WritePacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *src,
+                                  uint8_t ch_ep_num, uint16_t len, uint8_t dma);
+
+void             *USB_ReadPacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len);
+HAL_StatusTypeDef USB_EPSetStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
+HAL_StatusTypeDef USB_EPClearStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
+HAL_StatusTypeDef USB_EPStopXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
+HAL_StatusTypeDef USB_SetDevAddress(USB_OTG_GlobalTypeDef *USBx, uint8_t address);
+HAL_StatusTypeDef USB_DevConnect(USB_OTG_GlobalTypeDef *USBx);
+HAL_StatusTypeDef USB_DevDisconnect(USB_OTG_GlobalTypeDef *USBx);
+HAL_StatusTypeDef USB_StopDevice(USB_OTG_GlobalTypeDef *USBx);
+HAL_StatusTypeDef USB_ActivateSetup(USB_OTG_GlobalTypeDef *USBx);
+HAL_StatusTypeDef USB_EP0_OutStart(USB_OTG_GlobalTypeDef *USBx, uint8_t dma, uint8_t *psetup);
+uint8_t           USB_GetDevSpeed(USB_OTG_GlobalTypeDef *USBx);
+uint32_t          USB_GetMode(USB_OTG_GlobalTypeDef *USBx);
+uint32_t          USB_ReadInterrupts(USB_OTG_GlobalTypeDef *USBx);
+uint32_t          USB_ReadDevAllOutEpInterrupt(USB_OTG_GlobalTypeDef *USBx);
+uint32_t          USB_ReadDevOutEPInterrupt(USB_OTG_GlobalTypeDef *USBx, uint8_t epnum);
+uint32_t          USB_ReadDevAllInEpInterrupt(USB_OTG_GlobalTypeDef *USBx);
+uint32_t          USB_ReadDevInEPInterrupt(USB_OTG_GlobalTypeDef *USBx, uint8_t epnum);
+void              USB_ClearInterrupts(USB_OTG_GlobalTypeDef *USBx, uint32_t interrupt);
+
+HAL_StatusTypeDef USB_HostInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg);
+HAL_StatusTypeDef USB_InitFSLSPClkSel(USB_OTG_GlobalTypeDef *USBx, uint8_t freq);
+HAL_StatusTypeDef USB_ResetPort(USB_OTG_GlobalTypeDef *USBx);
+HAL_StatusTypeDef USB_DriveVbus(USB_OTG_GlobalTypeDef *USBx, uint8_t state);
+uint32_t          USB_GetHostSpeed(USB_OTG_GlobalTypeDef *USBx);
+uint32_t          USB_GetCurrentFrame(USB_OTG_GlobalTypeDef *USBx);
+HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num,
+                              uint8_t epnum, uint8_t dev_address, uint8_t speed,
+                              uint8_t ep_type, uint16_t mps);
+HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx,
+                                   USB_OTG_HCTypeDef *hc, uint8_t dma);
+
+uint32_t          USB_HC_ReadInterrupt(USB_OTG_GlobalTypeDef *USBx);
+HAL_StatusTypeDef USB_HC_Halt(USB_OTG_GlobalTypeDef *USBx, uint8_t hc_num);
+HAL_StatusTypeDef USB_DoPing(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num);
+HAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx);
+HAL_StatusTypeDef USB_ActivateRemoteWakeup(USB_OTG_GlobalTypeDef *USBx);
+HAL_StatusTypeDef USB_DeActivateRemoteWakeup(USB_OTG_GlobalTypeDef *USBx);
+#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+
+#endif /* STM32F4xx_LL_USB_H */
diff --git a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_utils.h b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_utils.h
new file mode 100644
index 0000000..8b6cdfe
--- /dev/null
+++ b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_utils.h
@@ -0,0 +1,307 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_ll_utils.h
+  * @author  MCD Application Team
+  * @brief   Header file of UTILS LL module.
+  @verbatim
+  ==============================================================================
+                     ##### How to use this driver #####
+  ==============================================================================
+    [..]
+    The LL UTILS driver contains a set of generic APIs that can be
+    used by user:
+      (+) Device electronic signature
+      (+) Timing functions
+      (+) PLL configuration functions
+
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_LL_UTILS_H
+#define __STM32F4xx_LL_UTILS_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx.h"
+
+/** @addtogroup STM32F4xx_LL_Driver
+  * @{
+  */
+
+/** @defgroup UTILS_LL UTILS
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup UTILS_LL_Private_Constants UTILS Private Constants
+  * @{
+  */
+
+/* Max delay can be used in LL_mDelay */
+#define LL_MAX_DELAY                  0xFFFFFFFFU
+
+/**
+ * @brief Unique device ID register base address
+ */
+#define UID_BASE_ADDRESS              UID_BASE
+
+/**
+ * @brief Flash size data register base address
+ */
+#define FLASHSIZE_BASE_ADDRESS        FLASHSIZE_BASE
+
+/**
+ * @brief Package data register base address
+ */
+#define PACKAGE_BASE_ADDRESS          PACKAGE_BASE
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup UTILS_LL_Private_Macros UTILS Private Macros
+  * @{
+  */
+/**
+  * @}
+  */
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup UTILS_LL_ES_INIT UTILS Exported structures
+  * @{
+  */
+/**
+  * @brief  UTILS PLL structure definition
+  */
+typedef struct
+{
+  uint32_t PLLM;   /*!< Division factor for PLL VCO input clock.
+                        This parameter can be a value of @ref RCC_LL_EC_PLLM_DIV
+
+                        This feature can be modified afterwards using unitary function
+                        @ref LL_RCC_PLL_ConfigDomain_SYS(). */
+
+  uint32_t PLLN;   /*!< Multiplication factor for PLL VCO output clock.
+                        This parameter must be a number between Min_Data = @ref RCC_PLLN_MIN_VALUE
+                        and Max_Data = @ref RCC_PLLN_MIN_VALUE
+
+                        This feature can be modified afterwards using unitary function
+                        @ref LL_RCC_PLL_ConfigDomain_SYS(). */
+
+  uint32_t PLLP;   /*!< Division for the main system clock.
+                        This parameter can be a value of @ref RCC_LL_EC_PLLP_DIV
+
+                        This feature can be modified afterwards using unitary function
+                        @ref LL_RCC_PLL_ConfigDomain_SYS(). */
+} LL_UTILS_PLLInitTypeDef;
+
+/**
+  * @brief  UTILS System, AHB and APB buses clock configuration structure definition
+  */
+typedef struct
+{
+  uint32_t AHBCLKDivider;         /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
+                                       This parameter can be a value of @ref RCC_LL_EC_SYSCLK_DIV
+
+                                       This feature can be modified afterwards using unitary function
+                                       @ref LL_RCC_SetAHBPrescaler(). */
+
+  uint32_t APB1CLKDivider;        /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
+                                       This parameter can be a value of @ref RCC_LL_EC_APB1_DIV
+
+                                       This feature can be modified afterwards using unitary function
+                                       @ref LL_RCC_SetAPB1Prescaler(). */
+
+  uint32_t APB2CLKDivider;        /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).
+                                       This parameter can be a value of @ref RCC_LL_EC_APB2_DIV
+
+                                       This feature can be modified afterwards using unitary function
+                                       @ref LL_RCC_SetAPB2Prescaler(). */
+
+} LL_UTILS_ClkInitTypeDef;
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup UTILS_LL_Exported_Constants UTILS Exported Constants
+  * @{
+  */
+
+/** @defgroup UTILS_EC_HSE_BYPASS HSE Bypass activation
+  * @{
+  */
+#define LL_UTILS_HSEBYPASS_OFF        0x00000000U       /*!< HSE Bypass is not enabled                */
+#define LL_UTILS_HSEBYPASS_ON         0x00000001U       /*!< HSE Bypass is enabled                    */
+/**
+  * @}
+  */
+
+/** @defgroup UTILS_EC_PACKAGETYPE PACKAGE TYPE
+  * @{
+  */
+#define LL_UTILS_PACKAGETYPE_WLCSP36_UFQFPN48_LQFP64                        0x00000000U /*!< WLCSP36 or UFQFPN48 or LQFP64 package type                         */
+#define LL_UTILS_PACKAGETYPE_WLCSP168_FBGA169_LQFP100_LQFP64_UFQFPN48       0x00000100U /*!< WLCSP168 or FBGA169 or LQFP100 or LQFP64 or UFQFPN48 package type  */
+#define LL_UTILS_PACKAGETYPE_WLCSP64_WLCSP81_LQFP176_UFBGA176               0x00000200U /*!< WLCSP64 or WLCSP81 or LQFP176 or UFBGA176 package type             */
+#define LL_UTILS_PACKAGETYPE_LQFP144_UFBGA144_UFBGA144_UFBGA100             0x00000300U /*!< LQFP144 or UFBGA144 or UFBGA144 or UFBGA100 package type           */
+#define LL_UTILS_PACKAGETYPE_LQFP100_LQFP208_TFBGA216                       0x00000400U /*!< LQFP100 or LQFP208 or TFBGA216 package type                        */
+#define LL_UTILS_PACKAGETYPE_LQFP208_TFBGA216                               0x00000500U /*!< LQFP208 or TFBGA216 package type                                   */
+#define LL_UTILS_PACKAGETYPE_TQFP64_UFBGA144_LQFP144                        0x00000700U /*!< TQFP64 or UFBGA144 or LQFP144 package type                         */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup UTILS_LL_Exported_Functions UTILS Exported Functions
+  * @{
+  */
+
+/** @defgroup UTILS_EF_DEVICE_ELECTRONIC_SIGNATURE DEVICE ELECTRONIC SIGNATURE
+  * @{
+  */
+
+/**
+  * @brief  Get Word0 of the unique device identifier (UID based on 96 bits)
+  * @retval UID[31:0]
+  */
+__STATIC_INLINE uint32_t LL_GetUID_Word0(void)
+{
+  return (uint32_t)(READ_REG(*((uint32_t *)UID_BASE_ADDRESS)));
+}
+
+/**
+  * @brief  Get Word1 of the unique device identifier (UID based on 96 bits)
+  * @retval UID[63:32]
+  */
+__STATIC_INLINE uint32_t LL_GetUID_Word1(void)
+{
+  return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 4U))));
+}
+
+/**
+  * @brief  Get Word2 of the unique device identifier (UID based on 96 bits)
+  * @retval UID[95:64]
+  */
+__STATIC_INLINE uint32_t LL_GetUID_Word2(void)
+{
+  return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 8U))));
+}
+
+/**
+  * @brief  Get Flash memory size
+  * @note   This bitfield indicates the size of the device Flash memory expressed in
+  *         Kbytes. As an example, 0x040 corresponds to 64 Kbytes.
+  * @retval FLASH_SIZE[15:0]: Flash memory size
+  */
+__STATIC_INLINE uint32_t LL_GetFlashSize(void)
+{
+  return (uint32_t)(READ_REG(*((uint32_t *)FLASHSIZE_BASE_ADDRESS)) & 0xFFFF);
+}
+
+/**
+  * @brief  Get Package type
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_UTILS_PACKAGETYPE_WLCSP36_UFQFPN48_LQFP64 (*)
+  *         @arg @ref LL_UTILS_PACKAGETYPE_WLCSP168_FBGA169_LQFP100_LQFP64_UFQFPN48 (*)
+  *         @arg @ref LL_UTILS_PACKAGETYPE_WLCSP64_WLCSP81_LQFP176_UFBGA176 (*)
+  *         @arg @ref LL_UTILS_PACKAGETYPE_LQFP144_UFBGA144_UFBGA144_UFBGA100 (*)
+  *         @arg @ref LL_UTILS_PACKAGETYPE_LQFP100_LQFP208_TFBGA216 (*)
+  *         @arg @ref LL_UTILS_PACKAGETYPE_LQFP208_TFBGA216 (*)
+  *         @arg @ref LL_UTILS_PACKAGETYPE_TQFP64_UFBGA144_LQFP144 (*)
+  * 
+  *         (*) value not defined in all devices.
+  */
+__STATIC_INLINE uint32_t LL_GetPackageType(void)
+{
+  return (uint32_t)(READ_REG(*((uint32_t *)PACKAGE_BASE_ADDRESS)) & 0x0700U);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup UTILS_LL_EF_DELAY DELAY
+  * @{
+  */
+
+/**
+  * @brief  This function configures the Cortex-M SysTick source of the time base.
+  * @param  HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro)
+  * @note   When a RTOS is used, it is recommended to avoid changing the SysTick
+  *         configuration by calling this function, for a delay use rather osDelay RTOS service.
+  * @param  Ticks Number of ticks
+  * @retval None
+  */
+__STATIC_INLINE void LL_InitTick(uint32_t HCLKFrequency, uint32_t Ticks)
+{
+  /* Configure the SysTick to have interrupt in 1ms time base */
+  SysTick->LOAD  = (uint32_t)((HCLKFrequency / Ticks) - 1UL);  /* set reload register */
+  SysTick->VAL   = 0UL;                                       /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_ENABLE_Msk;                   /* Enable the Systick Timer */
+}
+
+void        LL_Init1msTick(uint32_t HCLKFrequency);
+void        LL_mDelay(uint32_t Delay);
+
+/**
+  * @}
+  */
+
+/** @defgroup UTILS_EF_SYSTEM SYSTEM
+  * @{
+  */
+
+void        LL_SetSystemCoreClock(uint32_t HCLKFrequency);
+ErrorStatus LL_SetFlashLatency(uint32_t HCLK_Frequency);
+ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,
+                                         LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
+ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypass,
+                                         LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_LL_UTILS_H */
diff --git a/Drivers/STM32F4xx_HAL_Driver/LICENSE.txt b/Drivers/STM32F4xx_HAL_Driver/LICENSE.txt
new file mode 100644
index 0000000..b40364c
--- /dev/null
+++ b/Drivers/STM32F4xx_HAL_Driver/LICENSE.txt
@@ -0,0 +1,6 @@
+This software component is provided to you as part of a software package and
+applicable license terms are in the  Package_license file. If you received this
+software component outside of a package or without applicable license terms,
+the terms of the BSD-3-Clause license shall apply. 
+You may obtain a copy of the BSD-3-Clause at:
+https://opensource.org/licenses/BSD-3-Clause
diff --git a/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c
new file mode 100644
index 0000000..c467c6a
--- /dev/null
+++ b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c
@@ -0,0 +1,615 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hal.c
+  * @author  MCD Application Team
+  * @brief   HAL module driver.
+  *          This is the common part of the HAL initialization
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  @verbatim
+  ==============================================================================
+                     ##### How to use this driver #####
+  ==============================================================================
+    [..]
+    The common HAL driver contains a set of generic and common APIs that can be
+    used by the PPP peripheral drivers and the user to start using the HAL. 
+    [..]
+    The HAL contains two APIs' categories: 
+         (+) Common HAL APIs
+         (+) Services HAL APIs
+
+  @endverbatim
+  ******************************************************************************
+  */ 
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup HAL HAL
+  * @brief HAL module driver.
+  * @{
+  */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @addtogroup HAL_Private_Constants
+  * @{
+  */
+/**
+  * @brief STM32F4xx HAL Driver version number V1.8.0
+  */
+#define __STM32F4xx_HAL_VERSION_MAIN   (0x01U) /*!< [31:24] main version */
+#define __STM32F4xx_HAL_VERSION_SUB1   (0x08U) /*!< [23:16] sub1 version */
+#define __STM32F4xx_HAL_VERSION_SUB2   (0x00U) /*!< [15:8]  sub2 version */
+#define __STM32F4xx_HAL_VERSION_RC     (0x00U) /*!< [7:0]  release candidate */ 
+#define __STM32F4xx_HAL_VERSION         ((__STM32F4xx_HAL_VERSION_MAIN << 24U)\
+                                        |(__STM32F4xx_HAL_VERSION_SUB1 << 16U)\
+                                        |(__STM32F4xx_HAL_VERSION_SUB2 << 8U )\
+                                        |(__STM32F4xx_HAL_VERSION_RC))
+                                        
+#define IDCODE_DEVID_MASK    0x00000FFFU
+
+/* ------------ RCC registers bit address in the alias region ----------- */
+#define SYSCFG_OFFSET             (SYSCFG_BASE - PERIPH_BASE)
+/* ---  MEMRMP Register ---*/ 
+/* Alias word address of UFB_MODE bit */ 
+#define MEMRMP_OFFSET             SYSCFG_OFFSET 
+#define UFB_MODE_BIT_NUMBER       SYSCFG_MEMRMP_UFB_MODE_Pos
+#define UFB_MODE_BB               (uint32_t)(PERIPH_BB_BASE + (MEMRMP_OFFSET * 32U) + (UFB_MODE_BIT_NUMBER * 4U)) 
+
+/* ---  CMPCR Register ---*/ 
+/* Alias word address of CMP_PD bit */ 
+#define CMPCR_OFFSET              (SYSCFG_OFFSET + 0x20U) 
+#define CMP_PD_BIT_NUMBER         SYSCFG_CMPCR_CMP_PD_Pos
+#define CMPCR_CMP_PD_BB           (uint32_t)(PERIPH_BB_BASE + (CMPCR_OFFSET * 32U) + (CMP_PD_BIT_NUMBER * 4U))
+
+/* ---  MCHDLYCR Register ---*/ 
+/* Alias word address of BSCKSEL bit */ 
+#define MCHDLYCR_OFFSET            (SYSCFG_OFFSET + 0x30U) 
+#define BSCKSEL_BIT_NUMBER         SYSCFG_MCHDLYCR_BSCKSEL_Pos
+#define MCHDLYCR_BSCKSEL_BB        (uint32_t)(PERIPH_BB_BASE + (MCHDLYCR_OFFSET * 32U) + (BSCKSEL_BIT_NUMBER * 4U))
+/**
+  * @}
+  */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/** @addtogroup HAL_Private_Variables
+  * @{
+  */
+__IO uint32_t uwTick;
+uint32_t uwTickPrio   = (1UL << __NVIC_PRIO_BITS); /* Invalid PRIO */
+HAL_TickFreqTypeDef uwTickFreq = HAL_TICK_FREQ_DEFAULT;  /* 1KHz */
+/**
+  * @}
+  */
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup HAL_Exported_Functions HAL Exported Functions
+  * @{
+  */
+
+/** @defgroup HAL_Exported_Functions_Group1 Initialization and de-initialization Functions 
+ *  @brief    Initialization and de-initialization functions
+ *
+@verbatim    
+ ===============================================================================
+              ##### Initialization and Configuration functions #####
+ ===============================================================================
+    [..]  This section provides functions allowing to:
+      (+) Initializes the Flash interface the NVIC allocation and initial clock 
+          configuration. It initializes the systick also when timeout is needed 
+          and the backup domain when enabled.
+      (+) De-Initializes common part of the HAL.
+      (+) Configure the time base source to have 1ms time base with a dedicated 
+          Tick interrupt priority. 
+        (++) SysTick timer is used by default as source of time base, but user
+             can eventually implement his proper time base source (a general purpose 
+             timer for example or other time source), keeping in mind that Time base 
+             duration should be kept 1ms since PPP_TIMEOUT_VALUEs are defined and 
+             handled in milliseconds basis.
+        (++) Time base configuration function (HAL_InitTick ()) is called automatically 
+             at the beginning of the program after reset by HAL_Init() or at any time 
+             when clock is configured, by HAL_RCC_ClockConfig(). 
+        (++) Source of time base is configured  to generate interrupts at regular 
+             time intervals. Care must be taken if HAL_Delay() is called from a 
+             peripheral ISR process, the Tick interrupt line must have higher priority 
+            (numerically lower) than the peripheral interrupt. Otherwise the caller 
+            ISR process will be blocked. 
+       (++) functions affecting time base configurations are declared as __weak  
+             to make  override possible  in case of other  implementations in user file.
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  This function is used to initialize the HAL Library; it must be the first 
+  *         instruction to be executed in the main program (before to call any other
+  *         HAL function), it performs the following:
+  *           Configure the Flash prefetch, instruction and Data caches.
+  *           Configures the SysTick to generate an interrupt each 1 millisecond,
+  *           which is clocked by the HSI (at this stage, the clock is not yet
+  *           configured and thus the system is running from the internal HSI at 16 MHz).
+  *           Set NVIC Group Priority to 4.
+  *           Calls the HAL_MspInit() callback function defined in user file 
+  *           "stm32f4xx_hal_msp.c" to do the global low level hardware initialization 
+  *            
+  * @note   SysTick is used as time base for the HAL_Delay() function, the application
+  *         need to ensure that the SysTick time base is always set to 1 millisecond
+  *         to have correct HAL operation.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_Init(void)
+{
+  /* Configure Flash prefetch, Instruction cache, Data cache */ 
+#if (INSTRUCTION_CACHE_ENABLE != 0U)
+  __HAL_FLASH_INSTRUCTION_CACHE_ENABLE();
+#endif /* INSTRUCTION_CACHE_ENABLE */
+
+#if (DATA_CACHE_ENABLE != 0U)
+  __HAL_FLASH_DATA_CACHE_ENABLE();
+#endif /* DATA_CACHE_ENABLE */
+
+#if (PREFETCH_ENABLE != 0U)
+  __HAL_FLASH_PREFETCH_BUFFER_ENABLE();
+#endif /* PREFETCH_ENABLE */
+
+  /* Set Interrupt Group Priority */
+  HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
+
+  /* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */
+  HAL_InitTick(TICK_INT_PRIORITY);
+
+  /* Init the low level hardware */
+  HAL_MspInit();
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  This function de-Initializes common part of the HAL and stops the systick.
+  *         This function is optional.   
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DeInit(void)
+{
+  /* Reset of all peripherals */
+  __HAL_RCC_APB1_FORCE_RESET();
+  __HAL_RCC_APB1_RELEASE_RESET();
+
+  __HAL_RCC_APB2_FORCE_RESET();
+  __HAL_RCC_APB2_RELEASE_RESET();
+
+  __HAL_RCC_AHB1_FORCE_RESET();
+  __HAL_RCC_AHB1_RELEASE_RESET();
+
+  __HAL_RCC_AHB2_FORCE_RESET();
+  __HAL_RCC_AHB2_RELEASE_RESET();
+
+  __HAL_RCC_AHB3_FORCE_RESET();
+  __HAL_RCC_AHB3_RELEASE_RESET();
+
+  /* De-Init the low level hardware */
+  HAL_MspDeInit();
+    
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initialize the MSP.
+  * @retval None
+  */
+__weak void HAL_MspInit(void)
+{
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_MspInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  DeInitializes the MSP.
+  * @retval None
+  */
+__weak void HAL_MspDeInit(void)
+{
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_MspDeInit could be implemented in the user file
+   */ 
+}
+
+/**
+  * @brief This function configures the source of the time base.
+  *        The time source is configured  to have 1ms time base with a dedicated 
+  *        Tick interrupt priority.
+  * @note This function is called  automatically at the beginning of program after
+  *       reset by HAL_Init() or at any time when clock is reconfigured  by HAL_RCC_ClockConfig().
+  * @note In the default implementation, SysTick timer is the source of time base. 
+  *       It is used to generate interrupts at regular time intervals. 
+  *       Care must be taken if HAL_Delay() is called from a peripheral ISR process, 
+  *       The SysTick interrupt must have higher priority (numerically lower)
+  *       than the peripheral interrupt. Otherwise the caller ISR process will be blocked.
+  *       The function is declared as __weak  to be overwritten  in case of other
+  *       implementation  in user file.
+  * @param TickPriority Tick interrupt priority.
+  * @retval HAL status
+  */
+__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
+{
+  /* Configure the SysTick to have interrupt in 1ms time basis*/
+  if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Configure the SysTick IRQ priority */
+  if (TickPriority < (1UL << __NVIC_PRIO_BITS))
+  {
+    HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);
+    uwTickPrio = TickPriority;
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_Exported_Functions_Group2 HAL Control functions 
+ *  @brief    HAL Control functions
+ *
+@verbatim
+ ===============================================================================
+                      ##### HAL Control functions #####
+ ===============================================================================
+    [..]  This section provides functions allowing to:
+      (+) Provide a tick value in millisecond
+      (+) Provide a blocking delay in millisecond
+      (+) Suspend the time base source interrupt
+      (+) Resume the time base source interrupt
+      (+) Get the HAL API driver version
+      (+) Get the device identifier
+      (+) Get the device revision identifier
+      (+) Enable/Disable Debug module during SLEEP mode
+      (+) Enable/Disable Debug module during STOP mode
+      (+) Enable/Disable Debug module during STANDBY mode
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief This function is called to increment  a global variable "uwTick"
+  *        used as application time base.
+  * @note In the default implementation, this variable is incremented each 1ms
+  *       in SysTick ISR.
+ * @note This function is declared as __weak to be overwritten in case of other 
+  *      implementations in user file.
+  * @retval None
+  */
+__weak void HAL_IncTick(void)
+{
+  uwTick += uwTickFreq;
+}
+
+/**
+  * @brief Provides a tick value in millisecond.
+  * @note This function is declared as __weak to be overwritten in case of other 
+  *       implementations in user file.
+  * @retval tick value
+  */
+__weak uint32_t HAL_GetTick(void)
+{
+  return uwTick;
+}
+
+/**
+  * @brief This function returns a tick priority.
+  * @retval tick priority
+  */
+uint32_t HAL_GetTickPrio(void)
+{
+  return uwTickPrio;
+}
+
+/**
+  * @brief Set new tick Freq.
+  * @retval Status
+  */
+HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq)
+{
+  HAL_StatusTypeDef status  = HAL_OK;
+  HAL_TickFreqTypeDef prevTickFreq;
+
+  assert_param(IS_TICKFREQ(Freq));
+
+  if (uwTickFreq != Freq)
+  {
+    /* Back up uwTickFreq frequency */
+    prevTickFreq = uwTickFreq;
+
+    /* Update uwTickFreq global variable used by HAL_InitTick() */
+    uwTickFreq = Freq;
+
+    /* Apply the new tick Freq  */
+    status = HAL_InitTick(uwTickPrio);
+
+    if (status != HAL_OK)
+    {
+      /* Restore previous tick frequency */
+      uwTickFreq = prevTickFreq;
+    }
+  }
+
+  return status;
+}
+
+/**
+  * @brief Return tick frequency.
+  * @retval tick period in Hz
+  */
+HAL_TickFreqTypeDef HAL_GetTickFreq(void)
+{
+  return uwTickFreq;
+}
+
+/**
+  * @brief This function provides minimum delay (in milliseconds) based 
+  *        on variable incremented.
+  * @note In the default implementation , SysTick timer is the source of time base.
+  *       It is used to generate interrupts at regular time intervals where uwTick
+  *       is incremented.
+  * @note This function is declared as __weak to be overwritten in case of other
+  *       implementations in user file.
+  * @param Delay specifies the delay time length, in milliseconds.
+  * @retval None
+  */
+__weak void HAL_Delay(uint32_t Delay)
+{
+  uint32_t tickstart = HAL_GetTick();
+  uint32_t wait = Delay;
+
+  /* Add a freq to guarantee minimum wait */
+  if (wait < HAL_MAX_DELAY)
+  {
+    wait += (uint32_t)(uwTickFreq);
+  }
+
+  while((HAL_GetTick() - tickstart) < wait)
+  {
+  }
+}
+
+/**
+  * @brief Suspend Tick increment.
+  * @note In the default implementation , SysTick timer is the source of time base. It is
+  *       used to generate interrupts at regular time intervals. Once HAL_SuspendTick()
+  *       is called, the SysTick interrupt will be disabled and so Tick increment 
+  *       is suspended.
+  * @note This function is declared as __weak to be overwritten in case of other
+  *       implementations in user file.
+  * @retval None
+  */
+__weak void HAL_SuspendTick(void)
+{
+  /* Disable SysTick Interrupt */
+  SysTick->CTRL &= ~SysTick_CTRL_TICKINT_Msk;
+}
+
+/**
+  * @brief Resume Tick increment.
+  * @note In the default implementation , SysTick timer is the source of time base. It is
+  *       used to generate interrupts at regular time intervals. Once HAL_ResumeTick()
+  *       is called, the SysTick interrupt will be enabled and so Tick increment 
+  *       is resumed.
+  * @note This function is declared as __weak to be overwritten in case of other
+  *       implementations in user file.
+  * @retval None
+  */
+__weak void HAL_ResumeTick(void)
+{
+  /* Enable SysTick Interrupt */
+  SysTick->CTRL  |= SysTick_CTRL_TICKINT_Msk;
+}
+
+/**
+  * @brief  Returns the HAL revision
+  * @retval version : 0xXYZR (8bits for each decimal, R for RC)
+  */
+uint32_t HAL_GetHalVersion(void)
+{
+  return __STM32F4xx_HAL_VERSION;
+}
+
+/**
+  * @brief  Returns the device revision identifier.
+  * @retval Device revision identifier
+  */
+uint32_t HAL_GetREVID(void)
+{
+  return((DBGMCU->IDCODE) >> 16U);
+}
+
+/**
+  * @brief  Returns the device identifier.
+  * @retval Device identifier
+  */
+uint32_t HAL_GetDEVID(void)
+{
+  return((DBGMCU->IDCODE) & IDCODE_DEVID_MASK);
+}
+
+/**
+  * @brief  Enable the Debug Module during SLEEP mode
+  * @retval None
+  */
+void HAL_DBGMCU_EnableDBGSleepMode(void)
+{
+  SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
+}
+
+/**
+  * @brief  Disable the Debug Module during SLEEP mode
+  * @retval None
+  */
+void HAL_DBGMCU_DisableDBGSleepMode(void)
+{
+  CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
+}
+
+/**
+  * @brief  Enable the Debug Module during STOP mode
+  * @retval None
+  */
+void HAL_DBGMCU_EnableDBGStopMode(void)
+{
+  SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
+}
+
+/**
+  * @brief  Disable the Debug Module during STOP mode
+  * @retval None
+  */
+void HAL_DBGMCU_DisableDBGStopMode(void)
+{
+  CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
+}
+
+/**
+  * @brief  Enable the Debug Module during STANDBY mode
+  * @retval None
+  */
+void HAL_DBGMCU_EnableDBGStandbyMode(void)
+{
+  SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
+}
+
+/**
+  * @brief  Disable the Debug Module during STANDBY mode
+  * @retval None
+  */
+void HAL_DBGMCU_DisableDBGStandbyMode(void)
+{
+  CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
+}
+
+/**
+  * @brief  Enables the I/O Compensation Cell.
+  * @note   The I/O compensation cell can be used only when the device supply
+  *         voltage ranges from 2.4 to 3.6 V.  
+  * @retval None
+  */
+void HAL_EnableCompensationCell(void)
+{
+  *(__IO uint32_t *)CMPCR_CMP_PD_BB = (uint32_t)ENABLE;
+}
+
+/**
+  * @brief  Power-down the I/O Compensation Cell.
+  * @note   The I/O compensation cell can be used only when the device supply
+  *         voltage ranges from 2.4 to 3.6 V.  
+  * @retval None
+  */
+void HAL_DisableCompensationCell(void)
+{
+  *(__IO uint32_t *)CMPCR_CMP_PD_BB = (uint32_t)DISABLE;
+}
+
+/**
+  * @brief  Returns first word of the unique device identifier (UID based on 96 bits)
+  * @retval Device identifier
+  */
+uint32_t HAL_GetUIDw0(void)
+{
+  return (READ_REG(*((uint32_t *)UID_BASE)));
+}
+
+/**
+  * @brief  Returns second word of the unique device identifier (UID based on 96 bits)
+  * @retval Device identifier
+  */
+uint32_t HAL_GetUIDw1(void)
+{
+  return (READ_REG(*((uint32_t *)(UID_BASE + 4U))));
+}
+
+/**
+  * @brief  Returns third word of the unique device identifier (UID based on 96 bits)
+  * @retval Device identifier
+  */
+uint32_t HAL_GetUIDw2(void)
+{
+  return (READ_REG(*((uint32_t *)(UID_BASE + 8U))));
+}
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) ||\
+    defined(STM32F469xx) || defined(STM32F479xx)
+/**
+  * @brief  Enables the Internal FLASH Bank Swapping.
+  *   
+  * @note   This function can be used only for STM32F42xxx/43xxx/469xx/479xx devices. 
+  *
+  * @note   Flash Bank2 mapped at 0x08000000 (and aliased @0x00000000) 
+  *         and Flash Bank1 mapped at 0x08100000 (and aliased at 0x00100000)   
+  *
+  * @retval None
+  */
+void HAL_EnableMemorySwappingBank(void)
+{
+  *(__IO uint32_t *)UFB_MODE_BB = (uint32_t)ENABLE;
+}
+
+/**
+  * @brief  Disables the Internal FLASH Bank Swapping.
+  *   
+  * @note   This function can be used only for STM32F42xxx/43xxx/469xx/479xx devices. 
+  *
+  * @note   The default state : Flash Bank1 mapped at 0x08000000 (and aliased @0x00000000) 
+  *         and Flash Bank2 mapped at 0x08100000 (and aliased at 0x00100000) 
+  *           
+  * @retval None
+  */
+void HAL_DisableMemorySwappingBank(void)
+{
+  *(__IO uint32_t *)UFB_MODE_BB = (uint32_t)DISABLE;
+}
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+
diff --git a/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c
new file mode 100644
index 0000000..5970852
--- /dev/null
+++ b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c
@@ -0,0 +1,502 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hal_cortex.c
+  * @author  MCD Application Team
+  * @brief   CORTEX HAL module driver.
+  *          This file provides firmware functions to manage the following 
+  *          functionalities of the CORTEX:
+  *           + Initialization and de-initialization functions
+  *           + Peripheral Control functions 
+  *
+  @verbatim  
+  ==============================================================================
+                        ##### How to use this driver #####
+  ==============================================================================
+
+    [..]  
+    *** How to configure Interrupts using CORTEX HAL driver ***
+    ===========================================================
+    [..]     
+    This section provides functions allowing to configure the NVIC interrupts (IRQ).
+    The Cortex-M4 exceptions are managed by CMSIS functions.
+   
+    (#) Configure the NVIC Priority Grouping using HAL_NVIC_SetPriorityGrouping()
+        function according to the following table.
+    (#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority(). 
+    (#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ().
+    (#) please refer to programming manual for details in how to configure priority. 
+      
+     -@- When the NVIC_PRIORITYGROUP_0 is selected, IRQ preemption is no more possible. 
+         The pending IRQ priority will be managed only by the sub priority.
+   
+     -@- IRQ priority order (sorted by highest to lowest priority):
+        (+@) Lowest preemption priority
+        (+@) Lowest sub priority
+        (+@) Lowest hardware priority (IRQ number)
+ 
+    [..]  
+    *** How to configure Systick using CORTEX HAL driver ***
+    ========================================================
+    [..]
+    Setup SysTick Timer for time base.
+           
+   (+) The HAL_SYSTICK_Config() function calls the SysTick_Config() function which
+       is a CMSIS function that:
+        (++) Configures the SysTick Reload register with value passed as function parameter.
+        (++) Configures the SysTick IRQ priority to the lowest value 0x0F.
+        (++) Resets the SysTick Counter register.
+        (++) Configures the SysTick Counter clock source to be Core Clock Source (HCLK).
+        (++) Enables the SysTick Interrupt.
+        (++) Starts the SysTick Counter.
+    
+   (+) You can change the SysTick Clock source to be HCLK_Div8 by calling the macro
+       __HAL_CORTEX_SYSTICKCLK_CONFIG(SYSTICK_CLKSOURCE_HCLK_DIV8) just after the
+       HAL_SYSTICK_Config() function call. The __HAL_CORTEX_SYSTICKCLK_CONFIG() macro is defined
+       inside the stm32f4xx_hal_cortex.h file.
+
+   (+) You can change the SysTick IRQ priority by calling the
+       HAL_NVIC_SetPriority(SysTick_IRQn,...) function just after the HAL_SYSTICK_Config() function 
+       call. The HAL_NVIC_SetPriority() call the NVIC_SetPriority() function which is a CMSIS function.
+
+   (+) To adjust the SysTick time base, use the following formula:
+                            
+       Reload Value = SysTick Counter Clock (Hz) x  Desired Time base (s)
+       (++) Reload Value is the parameter to be passed for HAL_SYSTICK_Config() function
+       (++) Reload Value should not exceed 0xFFFFFF
+   
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file in
+  * the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup CORTEX CORTEX
+  * @brief CORTEX HAL module driver
+  * @{
+  */
+
+#ifdef HAL_CORTEX_MODULE_ENABLED
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup CORTEX_Exported_Functions CORTEX Exported Functions
+  * @{
+  */
+
+
+/** @defgroup CORTEX_Exported_Functions_Group1 Initialization and de-initialization functions
+ *  @brief    Initialization and Configuration functions 
+ *
+@verbatim    
+  ==============================================================================
+              ##### Initialization and de-initialization functions #####
+  ==============================================================================
+    [..]
+      This section provides the CORTEX HAL driver functions allowing to configure Interrupts
+      Systick functionalities 
+
+@endverbatim
+  * @{
+  */
+
+
+/**
+  * @brief  Sets the priority grouping field (preemption priority and subpriority)
+  *         using the required unlock sequence.
+  * @param  PriorityGroup The priority grouping bits length. 
+  *         This parameter can be one of the following values:
+  *         @arg NVIC_PRIORITYGROUP_0: 0 bits for preemption priority
+  *                                    4 bits for subpriority
+  *         @arg NVIC_PRIORITYGROUP_1: 1 bits for preemption priority
+  *                                    3 bits for subpriority
+  *         @arg NVIC_PRIORITYGROUP_2: 2 bits for preemption priority
+  *                                    2 bits for subpriority
+  *         @arg NVIC_PRIORITYGROUP_3: 3 bits for preemption priority
+  *                                    1 bits for subpriority
+  *         @arg NVIC_PRIORITYGROUP_4: 4 bits for preemption priority
+  *                                    0 bits for subpriority
+  * @note   When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible. 
+  *         The pending IRQ priority will be managed only by the subpriority. 
+  * @retval None
+  */
+void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+  /* Check the parameters */
+  assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
+  
+  /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
+  NVIC_SetPriorityGrouping(PriorityGroup);
+}
+
+/**
+  * @brief  Sets the priority of an interrupt.
+  * @param  IRQn External interrupt number.
+  *         This parameter can be an enumerator of IRQn_Type enumeration
+  *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f4xxxx.h))
+  * @param  PreemptPriority The preemption priority for the IRQn channel.
+  *         This parameter can be a value between 0 and 15
+  *         A lower priority value indicates a higher priority 
+  * @param  SubPriority the subpriority level for the IRQ channel.
+  *         This parameter can be a value between 0 and 15
+  *         A lower priority value indicates a higher priority.          
+  * @retval None
+  */
+void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
+{ 
+  uint32_t prioritygroup = 0x00U;
+  
+  /* Check the parameters */
+  assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
+  assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
+  
+  prioritygroup = NVIC_GetPriorityGrouping();
+  
+  NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
+}
+
+/**
+  * @brief  Enables a device specific interrupt in the NVIC interrupt controller.
+  * @note   To configure interrupts priority correctly, the NVIC_PriorityGroupConfig()
+  *         function should be called before. 
+  * @param  IRQn External interrupt number.
+  *         This parameter can be an enumerator of IRQn_Type enumeration
+  *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f4xxxx.h))
+  * @retval None
+  */
+void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  /* Check the parameters */
+  assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
+  
+  /* Enable interrupt */
+  NVIC_EnableIRQ(IRQn);
+}
+
+/**
+  * @brief  Disables a device specific interrupt in the NVIC interrupt controller.
+  * @param  IRQn External interrupt number.
+  *         This parameter can be an enumerator of IRQn_Type enumeration
+  *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f4xxxx.h))
+  * @retval None
+  */
+void HAL_NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  /* Check the parameters */
+  assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
+  
+  /* Disable interrupt */
+  NVIC_DisableIRQ(IRQn);
+}
+
+/**
+  * @brief  Initiates a system reset request to reset the MCU.
+  * @retval None
+  */
+void HAL_NVIC_SystemReset(void)
+{
+  /* System Reset */
+  NVIC_SystemReset();
+}
+
+/**
+  * @brief  Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+  *         Counter is in free running mode to generate periodic interrupts.
+  * @param  TicksNumb Specifies the ticks Number of ticks between two interrupts.
+  * @retval status:  - 0  Function succeeded.
+  *                  - 1  Function failed.
+  */
+uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
+{
+   return SysTick_Config(TicksNumb);
+}
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_Exported_Functions_Group2 Peripheral Control functions
+ *  @brief   Cortex control functions 
+ *
+@verbatim   
+  ==============================================================================
+                      ##### Peripheral Control functions #####
+  ==============================================================================  
+    [..]
+      This subsection provides a set of functions allowing to control the CORTEX
+      (NVIC, SYSTICK, MPU) functionalities. 
+ 
+      
+@endverbatim
+  * @{
+  */
+
+#if (__MPU_PRESENT == 1U)
+/**
+  * @brief  Disables the MPU
+  * @retval None
+  */
+void HAL_MPU_Disable(void)
+{
+  /* Make sure outstanding transfers are done */
+  __DMB();
+
+  /* Disable fault exceptions */
+  SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
+  
+  /* Disable the MPU and clear the control register*/
+  MPU->CTRL = 0U;
+}
+
+/**
+  * @brief  Enable the MPU.
+  * @param  MPU_Control Specifies the control mode of the MPU during hard fault, 
+  *          NMI, FAULTMASK and privileged access to the default memory 
+  *          This parameter can be one of the following values:
+  *            @arg MPU_HFNMI_PRIVDEF_NONE
+  *            @arg MPU_HARDFAULT_NMI
+  *            @arg MPU_PRIVILEGED_DEFAULT
+  *            @arg MPU_HFNMI_PRIVDEF
+  * @retval None
+  */
+void HAL_MPU_Enable(uint32_t MPU_Control)
+{
+  /* Enable the MPU */
+  MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
+  
+  /* Enable fault exceptions */
+  SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
+  
+  /* Ensure MPU setting take effects */
+  __DSB();
+  __ISB();
+}
+
+/**
+  * @brief  Initializes and configures the Region and the memory to be protected.
+  * @param  MPU_Init Pointer to a MPU_Region_InitTypeDef structure that contains
+  *                the initialization and configuration information.
+  * @retval None
+  */
+void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init)
+{
+  /* Check the parameters */
+  assert_param(IS_MPU_REGION_NUMBER(MPU_Init->Number));
+  assert_param(IS_MPU_REGION_ENABLE(MPU_Init->Enable));
+
+  /* Set the Region number */
+  MPU->RNR = MPU_Init->Number;
+
+  if ((MPU_Init->Enable) != RESET)
+  {
+    /* Check the parameters */
+    assert_param(IS_MPU_INSTRUCTION_ACCESS(MPU_Init->DisableExec));
+    assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(MPU_Init->AccessPermission));
+    assert_param(IS_MPU_TEX_LEVEL(MPU_Init->TypeExtField));
+    assert_param(IS_MPU_ACCESS_SHAREABLE(MPU_Init->IsShareable));
+    assert_param(IS_MPU_ACCESS_CACHEABLE(MPU_Init->IsCacheable));
+    assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable));
+    assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable));
+    assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size));
+    
+    MPU->RBAR = MPU_Init->BaseAddress;
+    MPU->RASR = ((uint32_t)MPU_Init->DisableExec             << MPU_RASR_XN_Pos)   |
+                ((uint32_t)MPU_Init->AccessPermission        << MPU_RASR_AP_Pos)   |
+                ((uint32_t)MPU_Init->TypeExtField            << MPU_RASR_TEX_Pos)  |
+                ((uint32_t)MPU_Init->IsShareable             << MPU_RASR_S_Pos)    |
+                ((uint32_t)MPU_Init->IsCacheable             << MPU_RASR_C_Pos)    |
+                ((uint32_t)MPU_Init->IsBufferable            << MPU_RASR_B_Pos)    |
+                ((uint32_t)MPU_Init->SubRegionDisable        << MPU_RASR_SRD_Pos)  |
+                ((uint32_t)MPU_Init->Size                    << MPU_RASR_SIZE_Pos) |
+                ((uint32_t)MPU_Init->Enable                  << MPU_RASR_ENABLE_Pos);
+  }
+  else
+  {
+    MPU->RBAR = 0x00U;
+    MPU->RASR = 0x00U;
+  }
+}
+#endif /* __MPU_PRESENT */
+
+/**
+  * @brief  Gets the priority grouping field from the NVIC Interrupt Controller.
+  * @retval Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field)
+  */
+uint32_t HAL_NVIC_GetPriorityGrouping(void)
+{
+  /* Get the PRIGROUP[10:8] field value */
+  return NVIC_GetPriorityGrouping();
+}
+
+/**
+  * @brief  Gets the priority of an interrupt.
+  * @param  IRQn External interrupt number.
+  *         This parameter can be an enumerator of IRQn_Type enumeration
+  *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f4xxxx.h))
+  * @param   PriorityGroup the priority grouping bits length.
+  *         This parameter can be one of the following values:
+  *           @arg NVIC_PRIORITYGROUP_0: 0 bits for preemption priority
+  *                                      4 bits for subpriority
+  *           @arg NVIC_PRIORITYGROUP_1: 1 bits for preemption priority
+  *                                      3 bits for subpriority
+  *           @arg NVIC_PRIORITYGROUP_2: 2 bits for preemption priority
+  *                                      2 bits for subpriority
+  *           @arg NVIC_PRIORITYGROUP_3: 3 bits for preemption priority
+  *                                      1 bits for subpriority
+  *           @arg NVIC_PRIORITYGROUP_4: 4 bits for preemption priority
+  *                                      0 bits for subpriority
+  * @param  pPreemptPriority Pointer on the Preemptive priority value (starting from 0).
+  * @param  pSubPriority Pointer on the Subpriority value (starting from 0).
+  * @retval None
+  */
+void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint32_t *pSubPriority)
+{
+  /* Check the parameters */
+  assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
+ /* Get priority for Cortex-M system or device specific interrupts */
+  NVIC_DecodePriority(NVIC_GetPriority(IRQn), PriorityGroup, pPreemptPriority, pSubPriority);
+}
+
+/**
+  * @brief  Sets Pending bit of an external interrupt.
+  * @param  IRQn External interrupt number
+  *         This parameter can be an enumerator of IRQn_Type enumeration
+  *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f4xxxx.h))
+  * @retval None
+  */
+void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  /* Check the parameters */
+  assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
+  
+  /* Set interrupt pending */
+  NVIC_SetPendingIRQ(IRQn);
+}
+
+/**
+  * @brief  Gets Pending Interrupt (reads the pending register in the NVIC 
+  *         and returns the pending bit for the specified interrupt).
+  * @param  IRQn External interrupt number.
+  *          This parameter can be an enumerator of IRQn_Type enumeration
+  *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f4xxxx.h))
+  * @retval status: - 0  Interrupt status is not pending.
+  *                 - 1  Interrupt status is pending.
+  */
+uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  /* Check the parameters */
+  assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
+  
+  /* Return 1 if pending else 0 */
+  return NVIC_GetPendingIRQ(IRQn);
+}
+
+/**
+  * @brief  Clears the pending bit of an external interrupt.
+  * @param  IRQn External interrupt number.
+  *         This parameter can be an enumerator of IRQn_Type enumeration
+  *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f4xxxx.h))
+  * @retval None
+  */
+void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  /* Check the parameters */
+  assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
+  
+  /* Clear pending interrupt */
+  NVIC_ClearPendingIRQ(IRQn);
+}
+
+/**
+  * @brief Gets active interrupt ( reads the active register in NVIC and returns the active bit).
+  * @param IRQn External interrupt number
+  *         This parameter can be an enumerator of IRQn_Type enumeration
+  *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f4xxxx.h))
+  * @retval status: - 0  Interrupt status is not pending.
+  *                 - 1  Interrupt status is pending.
+  */
+uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn)
+{
+  /* Check the parameters */
+  assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
+  
+  /* Return 1 if active else 0 */
+  return NVIC_GetActive(IRQn);
+}
+
+/**
+  * @brief  Configures the SysTick clock source.
+  * @param  CLKSource specifies the SysTick clock source.
+  *          This parameter can be one of the following values:
+  *             @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source.
+  *             @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source.
+  * @retval None
+  */
+void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource)
+{
+  /* Check the parameters */
+  assert_param(IS_SYSTICK_CLK_SOURCE(CLKSource));
+  if (CLKSource == SYSTICK_CLKSOURCE_HCLK)
+  {
+    SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK;
+  }
+  else
+  {
+    SysTick->CTRL &= ~SYSTICK_CLKSOURCE_HCLK;
+  }
+}
+
+/**
+  * @brief  This function handles SYSTICK interrupt request.
+  * @retval None
+  */
+void HAL_SYSTICK_IRQHandler(void)
+{
+  HAL_SYSTICK_Callback();
+}
+
+/**
+  * @brief  SYSTICK callback.
+  * @retval None
+  */
+__weak void HAL_SYSTICK_Callback(void)
+{
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_SYSTICK_Callback could be implemented in the user file
+   */
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* HAL_CORTEX_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
diff --git a/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_crc.c b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_crc.c
new file mode 100644
index 0000000..1d0faf1
--- /dev/null
+++ b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_crc.c
@@ -0,0 +1,328 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hal_crc.c
+  * @author  MCD Application Team
+  * @brief   CRC HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the Cyclic Redundancy Check (CRC) peripheral:
+  *           + Initialization and de-initialization functions
+  *           + Peripheral Control functions
+  *           + Peripheral State functions
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2016 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  @verbatim
+ ===============================================================================
+                     ##### How to use this driver #####
+ ===============================================================================
+    [..]
+         (+) Enable CRC AHB clock using __HAL_RCC_CRC_CLK_ENABLE();
+         (+) Initialize CRC calculator
+             (++) specify generating polynomial (peripheral default or non-default one)
+             (++) specify initialization value (peripheral default or non-default one)
+             (++) specify input data format
+             (++) specify input or output data inversion mode if any
+         (+) Use HAL_CRC_Accumulate() function to compute the CRC value of the
+             input data buffer starting with the previously computed CRC as
+             initialization value
+         (+) Use HAL_CRC_Calculate() function to compute the CRC value of the
+             input data buffer starting with the defined initialization value
+             (default or non-default) to initiate CRC calculation
+
+  @endverbatim
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup CRC CRC
+  * @brief CRC HAL module driver.
+  * @{
+  */
+
+#ifdef HAL_CRC_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup CRC_Exported_Functions CRC Exported Functions
+  * @{
+  */
+
+/** @defgroup CRC_Exported_Functions_Group1 Initialization and de-initialization functions
+  *  @brief    Initialization and Configuration functions.
+  *
+@verbatim
+ ===============================================================================
+            ##### Initialization and de-initialization functions #####
+ ===============================================================================
+    [..]  This section provides functions allowing to:
+      (+) Initialize the CRC according to the specified parameters
+          in the CRC_InitTypeDef and create the associated handle
+      (+) DeInitialize the CRC peripheral
+      (+) Initialize the CRC MSP (MCU Specific Package)
+      (+) DeInitialize the CRC MSP
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initialize the CRC according to the specified
+  *         parameters in the CRC_InitTypeDef and create the associated handle.
+  * @param  hcrc CRC handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc)
+{
+  /* Check the CRC handle allocation */
+  if (hcrc == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_CRC_ALL_INSTANCE(hcrc->Instance));
+
+  if (hcrc->State == HAL_CRC_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    hcrc->Lock = HAL_UNLOCKED;
+    /* Init the low level hardware */
+    HAL_CRC_MspInit(hcrc);
+  }
+
+  /* Change CRC peripheral state */
+  hcrc->State = HAL_CRC_STATE_READY;
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  DeInitialize the CRC peripheral.
+  * @param  hcrc CRC handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_CRC_DeInit(CRC_HandleTypeDef *hcrc)
+{
+  /* Check the CRC handle allocation */
+  if (hcrc == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_CRC_ALL_INSTANCE(hcrc->Instance));
+
+  /* Check the CRC peripheral state */
+  if (hcrc->State == HAL_CRC_STATE_BUSY)
+  {
+    return HAL_BUSY;
+  }
+
+  /* Change CRC peripheral state */
+  hcrc->State = HAL_CRC_STATE_BUSY;
+
+  /* Reset CRC calculation unit */
+  __HAL_CRC_DR_RESET(hcrc);
+
+  /* Reset IDR register content */
+  CLEAR_BIT(hcrc->Instance->IDR, CRC_IDR_IDR);
+
+  /* DeInit the low level hardware */
+  HAL_CRC_MspDeInit(hcrc);
+
+  /* Change CRC peripheral state */
+  hcrc->State = HAL_CRC_STATE_RESET;
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hcrc);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the CRC MSP.
+  * @param  hcrc CRC handle
+  * @retval None
+  */
+__weak void HAL_CRC_MspInit(CRC_HandleTypeDef *hcrc)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hcrc);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_CRC_MspInit can be implemented in the user file
+   */
+}
+
+/**
+  * @brief  DeInitialize the CRC MSP.
+  * @param  hcrc CRC handle
+  * @retval None
+  */
+__weak void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hcrc);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_CRC_MspDeInit can be implemented in the user file
+   */
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup CRC_Exported_Functions_Group2 Peripheral Control functions
+  *  @brief    management functions.
+  *
+@verbatim
+ ===============================================================================
+                      ##### Peripheral Control functions #####
+ ===============================================================================
+    [..]  This section provides functions allowing to:
+      (+) compute the 32-bit CRC value of a 32-bit data buffer
+          using combination of the previous CRC value and the new one.
+
+       [..]  or
+
+      (+) compute the 32-bit CRC value of a 32-bit data buffer
+          independently of the previous CRC value.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Compute the 32-bit CRC value of a 32-bit data buffer
+  *         starting with the previously computed CRC as initialization value.
+  * @param  hcrc CRC handle
+  * @param  pBuffer pointer to the input data buffer.
+  * @param  BufferLength input data buffer length (number of uint32_t words).
+  * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)
+  */
+uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength)
+{
+  uint32_t index;      /* CRC input data buffer index */
+  uint32_t temp = 0U;  /* CRC output (read from hcrc->Instance->DR register) */
+
+  /* Change CRC peripheral state */
+  hcrc->State = HAL_CRC_STATE_BUSY;
+
+  /* Enter Data to the CRC calculator */
+  for (index = 0U; index < BufferLength; index++)
+  {
+    hcrc->Instance->DR = pBuffer[index];
+  }
+  temp = hcrc->Instance->DR;
+
+  /* Change CRC peripheral state */
+  hcrc->State = HAL_CRC_STATE_READY;
+
+  /* Return the CRC computed value */
+  return temp;
+}
+
+/**
+  * @brief  Compute the 32-bit CRC value of a 32-bit data buffer
+  *         starting with hcrc->Instance->INIT as initialization value.
+  * @param  hcrc CRC handle
+  * @param  pBuffer pointer to the input data buffer.
+  * @param  BufferLength input data buffer length (number of uint32_t words).
+  * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)
+  */
+uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength)
+{
+  uint32_t index;      /* CRC input data buffer index */
+  uint32_t temp = 0U;  /* CRC output (read from hcrc->Instance->DR register) */
+
+  /* Change CRC peripheral state */
+  hcrc->State = HAL_CRC_STATE_BUSY;
+
+  /* Reset CRC Calculation Unit (hcrc->Instance->INIT is
+  *  written in hcrc->Instance->DR) */
+  __HAL_CRC_DR_RESET(hcrc);
+
+  /* Enter 32-bit input data to the CRC calculator */
+  for (index = 0U; index < BufferLength; index++)
+  {
+    hcrc->Instance->DR = pBuffer[index];
+  }
+  temp = hcrc->Instance->DR;
+
+  /* Change CRC peripheral state */
+  hcrc->State = HAL_CRC_STATE_READY;
+
+  /* Return the CRC computed value */
+  return temp;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup CRC_Exported_Functions_Group3 Peripheral State functions
+  *  @brief    Peripheral State functions.
+  *
+@verbatim
+ ===============================================================================
+                      ##### Peripheral State functions #####
+ ===============================================================================
+    [..]
+    This subsection permits to get in run-time the status of the peripheral.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Return the CRC handle state.
+  * @param  hcrc CRC handle
+  * @retval HAL state
+  */
+HAL_CRC_StateTypeDef HAL_CRC_GetState(CRC_HandleTypeDef *hcrc)
+{
+  /* Return CRC handle state */
+  return hcrc->State;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+
+#endif /* HAL_CRC_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
diff --git a/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c
new file mode 100644
index 0000000..2bc5f27
--- /dev/null
+++ b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c
@@ -0,0 +1,1305 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hal_dma.c
+  * @author  MCD Application Team
+  * @brief   DMA HAL module driver.
+  *    
+  *          This file provides firmware functions to manage the following 
+  *          functionalities of the Direct Memory Access (DMA) peripheral:
+  *           + Initialization and de-initialization functions
+  *           + IO operation functions
+  *           + Peripheral State and errors functions
+  @verbatim     
+  ==============================================================================
+                        ##### How to use this driver #####
+  ==============================================================================
+  [..]
+   (#) Enable and configure the peripheral to be connected to the DMA Stream
+       (except for internal SRAM/FLASH memories: no initialization is 
+       necessary) please refer to Reference manual for connection between peripherals
+       and DMA requests.
+
+   (#) For a given Stream, program the required configuration through the following parameters:
+       Transfer Direction, Source and Destination data formats, 
+       Circular, Normal or peripheral flow control mode, Stream Priority level, 
+       Source and Destination Increment mode, FIFO mode and its Threshold (if needed), 
+       Burst mode for Source and/or Destination (if needed) using HAL_DMA_Init() function.
+
+   -@-   Prior to HAL_DMA_Init() the clock must be enabled for DMA through the following macros:
+         __HAL_RCC_DMA1_CLK_ENABLE() or __HAL_RCC_DMA2_CLK_ENABLE().
+
+     *** Polling mode IO operation ***
+     =================================
+    [..]
+          (+) Use HAL_DMA_Start() to start DMA transfer after the configuration of Source 
+              address and destination address and the Length of data to be transferred.
+          (+) Use HAL_DMA_PollForTransfer() to poll for the end of current transfer, in this  
+              case a fixed Timeout can be configured by User depending from his application.
+          (+) Use HAL_DMA_Abort() function to abort the current transfer.
+
+     *** Interrupt mode IO operation ***
+     ===================================
+    [..]
+          (+) Configure the DMA interrupt priority using HAL_NVIC_SetPriority()
+          (+) Enable the DMA IRQ handler using HAL_NVIC_EnableIRQ() 
+          (+) Use HAL_DMA_Start_IT() to start DMA transfer after the configuration of  
+              Source address and destination address and the Length of data to be transferred. In this 
+              case the DMA interrupt is configured 
+          (+) Use HAL_DMA_IRQHandler() called under DMA_IRQHandler() Interrupt subroutine
+          (+) At the end of data transfer HAL_DMA_IRQHandler() function is executed and user can 
+              add his own function by customization of function pointer XferCpltCallback and 
+              XferErrorCallback (i.e a member of DMA handle structure).
+    [..]
+     (#) Use HAL_DMA_GetState() function to return the DMA state and HAL_DMA_GetError() in case of error 
+         detection.
+
+     (#) Use HAL_DMA_Abort_IT() function to abort the current transfer
+
+     -@-   In Memory-to-Memory transfer mode, Circular mode is not allowed.
+
+     -@-   The FIFO is used mainly to reduce bus usage and to allow data packing/unpacking: it is
+           possible to set different Data Sizes for the Peripheral and the Memory (ie. you can set
+           Half-Word data size for the peripheral to access its data register and set Word data size
+           for the Memory to gain in access time. Each two half words will be packed and written in
+           a single access to a Word in the Memory).
+
+     -@-   When FIFO is disabled, it is not allowed to configure different Data Sizes for Source
+           and Destination. In this case the Peripheral Data Size will be applied to both Source
+           and Destination.
+
+     *** DMA HAL driver macros list ***
+     =============================================
+     [..]
+       Below the list of most used macros in DMA HAL driver.
+       
+      (+) __HAL_DMA_ENABLE: Enable the specified DMA Stream.
+      (+) __HAL_DMA_DISABLE: Disable the specified DMA Stream.
+      (+) __HAL_DMA_GET_IT_SOURCE: Check whether the specified DMA Stream interrupt has occurred or not. 
+
+     [..]
+      (@) You can refer to the DMA HAL driver header file for more useful macros
+
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file in
+  * the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */ 
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup DMA DMA
+  * @brief DMA HAL module driver
+  * @{
+  */
+
+#ifdef HAL_DMA_MODULE_ENABLED
+
+/* Private types -------------------------------------------------------------*/
+typedef struct
+{
+  __IO uint32_t ISR;   /*!< DMA interrupt status register */
+  __IO uint32_t Reserved0;
+  __IO uint32_t IFCR;  /*!< DMA interrupt flag clear register */
+} DMA_Base_Registers;
+
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @addtogroup DMA_Private_Constants
+ * @{
+ */
+ #define HAL_TIMEOUT_DMA_ABORT    5U  /* 5 ms */
+/**
+  * @}
+  */
+/* Private macros ------------------------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+/** @addtogroup DMA_Private_Functions
+  * @{
+  */
+static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
+static uint32_t DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma);
+static HAL_StatusTypeDef DMA_CheckFifoParam(DMA_HandleTypeDef *hdma);
+
+/**
+  * @}
+  */  
+
+/* Exported functions ---------------------------------------------------------*/
+/** @addtogroup DMA_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup DMA_Exported_Functions_Group1
+  *
+@verbatim
+ ===============================================================================
+             ##### Initialization and de-initialization functions  #####
+ ===============================================================================
+    [..]
+    This section provides functions allowing to initialize the DMA Stream source
+    and destination addresses, incrementation and data sizes, transfer direction, 
+    circular/normal mode selection, memory-to-memory mode selection and Stream priority value.
+    [..]
+    The HAL_DMA_Init() function follows the DMA configuration procedures as described in
+    reference manual.
+
+@endverbatim
+  * @{
+  */
+  
+/**
+  * @brief  Initialize the DMA according to the specified
+  *         parameters in the DMA_InitTypeDef and create the associated handle.
+  * @param  hdma Pointer to a DMA_HandleTypeDef structure that contains
+  *               the configuration information for the specified DMA Stream.  
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
+{
+  uint32_t tmp = 0U;
+  uint32_t tickstart = HAL_GetTick();
+  DMA_Base_Registers *regs;
+
+  /* Check the DMA peripheral state */
+  if(hdma == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_DMA_STREAM_ALL_INSTANCE(hdma->Instance));
+  assert_param(IS_DMA_CHANNEL(hdma->Init.Channel));
+  assert_param(IS_DMA_DIRECTION(hdma->Init.Direction));
+  assert_param(IS_DMA_PERIPHERAL_INC_STATE(hdma->Init.PeriphInc));
+  assert_param(IS_DMA_MEMORY_INC_STATE(hdma->Init.MemInc));
+  assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(hdma->Init.PeriphDataAlignment));
+  assert_param(IS_DMA_MEMORY_DATA_SIZE(hdma->Init.MemDataAlignment));
+  assert_param(IS_DMA_MODE(hdma->Init.Mode));
+  assert_param(IS_DMA_PRIORITY(hdma->Init.Priority));
+  assert_param(IS_DMA_FIFO_MODE_STATE(hdma->Init.FIFOMode));
+  /* Check the memory burst, peripheral burst and FIFO threshold parameters only
+     when FIFO mode is enabled */
+  if(hdma->Init.FIFOMode != DMA_FIFOMODE_DISABLE)
+  {
+    assert_param(IS_DMA_FIFO_THRESHOLD(hdma->Init.FIFOThreshold));
+    assert_param(IS_DMA_MEMORY_BURST(hdma->Init.MemBurst));
+    assert_param(IS_DMA_PERIPHERAL_BURST(hdma->Init.PeriphBurst));
+  }
+
+  /* Change DMA peripheral state */
+  hdma->State = HAL_DMA_STATE_BUSY;
+
+  /* Allocate lock resource */
+  __HAL_UNLOCK(hdma);
+  
+  /* Disable the peripheral */
+  __HAL_DMA_DISABLE(hdma);
+  
+  /* Check if the DMA Stream is effectively disabled */
+  while((hdma->Instance->CR & DMA_SxCR_EN) != RESET)
+  {
+    /* Check for the Timeout */
+    if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DMA_ABORT)
+    {
+      /* Update error code */
+      hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT;
+      
+      /* Change the DMA state */
+      hdma->State = HAL_DMA_STATE_TIMEOUT;
+      
+      return HAL_TIMEOUT;
+    }
+  }
+  
+  /* Get the CR register value */
+  tmp = hdma->Instance->CR;
+
+  /* Clear CHSEL, MBURST, PBURST, PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR, CT and DBM bits */
+  tmp &= ((uint32_t)~(DMA_SxCR_CHSEL | DMA_SxCR_MBURST | DMA_SxCR_PBURST | \
+                      DMA_SxCR_PL    | DMA_SxCR_MSIZE  | DMA_SxCR_PSIZE  | \
+                      DMA_SxCR_MINC  | DMA_SxCR_PINC   | DMA_SxCR_CIRC   | \
+                      DMA_SxCR_DIR   | DMA_SxCR_CT     | DMA_SxCR_DBM));
+
+  /* Prepare the DMA Stream configuration */
+  tmp |=  hdma->Init.Channel             | hdma->Init.Direction        |
+          hdma->Init.PeriphInc           | hdma->Init.MemInc           |
+          hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment |
+          hdma->Init.Mode                | hdma->Init.Priority;
+
+  /* the Memory burst and peripheral burst are not used when the FIFO is disabled */
+  if(hdma->Init.FIFOMode == DMA_FIFOMODE_ENABLE)
+  {
+    /* Get memory burst and peripheral burst */
+    tmp |=  hdma->Init.MemBurst | hdma->Init.PeriphBurst;
+  }
+  
+  /* Write to DMA Stream CR register */
+  hdma->Instance->CR = tmp;  
+
+  /* Get the FCR register value */
+  tmp = hdma->Instance->FCR;
+
+  /* Clear Direct mode and FIFO threshold bits */
+  tmp &= (uint32_t)~(DMA_SxFCR_DMDIS | DMA_SxFCR_FTH);
+
+  /* Prepare the DMA Stream FIFO configuration */
+  tmp |= hdma->Init.FIFOMode;
+
+  /* The FIFO threshold is not used when the FIFO mode is disabled */
+  if(hdma->Init.FIFOMode == DMA_FIFOMODE_ENABLE)
+  {
+    /* Get the FIFO threshold */
+    tmp |= hdma->Init.FIFOThreshold;
+    
+    /* Check compatibility between FIFO threshold level and size of the memory burst */
+    /* for INCR4, INCR8, INCR16 bursts */
+    if (hdma->Init.MemBurst != DMA_MBURST_SINGLE)
+    {
+      if (DMA_CheckFifoParam(hdma) != HAL_OK)
+      {
+        /* Update error code */
+        hdma->ErrorCode = HAL_DMA_ERROR_PARAM;
+        
+        /* Change the DMA state */
+        hdma->State = HAL_DMA_STATE_READY;
+        
+        return HAL_ERROR; 
+      }
+    }
+  }
+  
+  /* Write to DMA Stream FCR */
+  hdma->Instance->FCR = tmp;
+
+  /* Initialize StreamBaseAddress and StreamIndex parameters to be used to calculate
+     DMA steam Base Address needed by HAL_DMA_IRQHandler() and HAL_DMA_PollForTransfer() */
+  regs = (DMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma);
+  
+  /* Clear all interrupt flags */
+  regs->IFCR = 0x3FU << hdma->StreamIndex;
+
+  /* Initialize the error code */
+  hdma->ErrorCode = HAL_DMA_ERROR_NONE;
+                                                                                     
+  /* Initialize the DMA state */
+  hdma->State = HAL_DMA_STATE_READY;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  DeInitializes the DMA peripheral 
+  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
+  *               the configuration information for the specified DMA Stream.  
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma)
+{
+  DMA_Base_Registers *regs;
+
+  /* Check the DMA peripheral state */
+  if(hdma == NULL)
+  {
+    return HAL_ERROR;
+  }
+  
+  /* Check the DMA peripheral state */
+  if(hdma->State == HAL_DMA_STATE_BUSY)
+  {
+    /* Return error status */
+    return HAL_BUSY;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_DMA_STREAM_ALL_INSTANCE(hdma->Instance));
+
+  /* Disable the selected DMA Streamx */
+  __HAL_DMA_DISABLE(hdma);
+
+  /* Reset DMA Streamx control register */
+  hdma->Instance->CR   = 0U;
+
+  /* Reset DMA Streamx number of data to transfer register */
+  hdma->Instance->NDTR = 0U;
+
+  /* Reset DMA Streamx peripheral address register */
+  hdma->Instance->PAR  = 0U;
+
+  /* Reset DMA Streamx memory 0 address register */
+  hdma->Instance->M0AR = 0U;
+  
+  /* Reset DMA Streamx memory 1 address register */
+  hdma->Instance->M1AR = 0U;
+  
+  /* Reset DMA Streamx FIFO control register */
+  hdma->Instance->FCR  = 0x00000021U;
+  
+  /* Get DMA steam Base Address */  
+  regs = (DMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma);
+  
+  /* Clean all callbacks */
+  hdma->XferCpltCallback = NULL;
+  hdma->XferHalfCpltCallback = NULL;
+  hdma->XferM1CpltCallback = NULL;
+  hdma->XferM1HalfCpltCallback = NULL;
+  hdma->XferErrorCallback = NULL;
+  hdma->XferAbortCallback = NULL;
+
+  /* Clear all interrupt flags at correct offset within the register */
+  regs->IFCR = 0x3FU << hdma->StreamIndex;
+
+  /* Reset the error code */
+  hdma->ErrorCode = HAL_DMA_ERROR_NONE;
+
+  /* Reset the DMA state */
+  hdma->State = HAL_DMA_STATE_RESET;
+
+  /* Release Lock */
+  __HAL_UNLOCK(hdma);
+
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/** @addtogroup DMA_Exported_Functions_Group2
+  *
+@verbatim   
+ ===============================================================================
+                      #####  IO operation functions  #####
+ ===============================================================================
+    [..]  This section provides functions allowing to:
+      (+) Configure the source, destination address and data length and Start DMA transfer
+      (+) Configure the source, destination address and data length and 
+          Start DMA transfer with interrupt
+      (+) Abort DMA transfer
+      (+) Poll for transfer complete
+      (+) Handle DMA interrupt request  
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Starts the DMA Transfer.
+  * @param  hdma       pointer to a DMA_HandleTypeDef structure that contains
+  *                     the configuration information for the specified DMA Stream.
+  * @param  SrcAddress The source memory Buffer address
+  * @param  DstAddress The destination memory Buffer address
+  * @param  DataLength The length of data to be transferred from source to destination
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  
+  /* Check the parameters */
+  assert_param(IS_DMA_BUFFER_SIZE(DataLength));
+
+  /* Process locked */
+  __HAL_LOCK(hdma);
+
+  if(HAL_DMA_STATE_READY == hdma->State)
+  {
+    /* Change DMA peripheral state */
+    hdma->State = HAL_DMA_STATE_BUSY;
+    
+    /* Initialize the error code */
+    hdma->ErrorCode = HAL_DMA_ERROR_NONE;
+    
+    /* Configure the source, destination address and the data length */
+    DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
+
+    /* Enable the Peripheral */
+    __HAL_DMA_ENABLE(hdma);
+  }
+  else
+  {
+    /* Process unlocked */
+    __HAL_UNLOCK(hdma);
+    
+    /* Return error status */
+    status = HAL_BUSY;
+  } 
+  return status; 
+}
+
+/**
+  * @brief  Start the DMA Transfer with interrupt enabled.
+  * @param  hdma       pointer to a DMA_HandleTypeDef structure that contains
+  *                     the configuration information for the specified DMA Stream.  
+  * @param  SrcAddress The source memory Buffer address
+  * @param  DstAddress The destination memory Buffer address
+  * @param  DataLength The length of data to be transferred from source to destination
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* calculate DMA base and stream number */
+  DMA_Base_Registers *regs = (DMA_Base_Registers *)hdma->StreamBaseAddress;
+  
+  /* Check the parameters */
+  assert_param(IS_DMA_BUFFER_SIZE(DataLength));
+ 
+  /* Process locked */
+  __HAL_LOCK(hdma);
+  
+  if(HAL_DMA_STATE_READY == hdma->State)
+  {
+    /* Change DMA peripheral state */
+    hdma->State = HAL_DMA_STATE_BUSY;
+    
+    /* Initialize the error code */
+    hdma->ErrorCode = HAL_DMA_ERROR_NONE;
+    
+    /* Configure the source, destination address and the data length */
+    DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
+    
+    /* Clear all interrupt flags at correct offset within the register */
+    regs->IFCR = 0x3FU << hdma->StreamIndex;
+    
+    /* Enable Common interrupts*/
+    hdma->Instance->CR  |= DMA_IT_TC | DMA_IT_TE | DMA_IT_DME;
+    
+    if(hdma->XferHalfCpltCallback != NULL)
+    {
+      hdma->Instance->CR  |= DMA_IT_HT;
+    }
+    
+    /* Enable the Peripheral */
+    __HAL_DMA_ENABLE(hdma);
+  }
+  else
+  {
+    /* Process unlocked */
+    __HAL_UNLOCK(hdma);	  
+    
+    /* Return error status */
+    status = HAL_BUSY;
+  }
+  
+  return status;
+}
+
+/**
+  * @brief  Aborts the DMA Transfer.
+  * @param  hdma   pointer to a DMA_HandleTypeDef structure that contains
+  *                 the configuration information for the specified DMA Stream.
+  *                   
+  * @note  After disabling a DMA Stream, a check for wait until the DMA Stream is 
+  *        effectively disabled is added. If a Stream is disabled 
+  *        while a data transfer is ongoing, the current data will be transferred
+  *        and the Stream will be effectively disabled only after the transfer of
+  *        this single data is finished.  
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma)
+{
+  /* calculate DMA base and stream number */
+  DMA_Base_Registers *regs = (DMA_Base_Registers *)hdma->StreamBaseAddress;
+  
+  uint32_t tickstart = HAL_GetTick();
+  
+  if(hdma->State != HAL_DMA_STATE_BUSY)
+  {
+    hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
+    
+    /* Process Unlocked */
+    __HAL_UNLOCK(hdma);
+    
+    return HAL_ERROR;
+  }
+  else
+  {
+    /* Disable all the transfer interrupts */
+    hdma->Instance->CR  &= ~(DMA_IT_TC | DMA_IT_TE | DMA_IT_DME);
+    hdma->Instance->FCR &= ~(DMA_IT_FE);
+    
+    if((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL))
+    {
+      hdma->Instance->CR  &= ~(DMA_IT_HT);
+    }
+    
+    /* Disable the stream */
+    __HAL_DMA_DISABLE(hdma);
+    
+    /* Check if the DMA Stream is effectively disabled */
+    while((hdma->Instance->CR & DMA_SxCR_EN) != RESET)
+    {
+      /* Check for the Timeout */
+      if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DMA_ABORT)
+      {
+        /* Update error code */
+        hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT;
+        
+        /* Change the DMA state */
+        hdma->State = HAL_DMA_STATE_TIMEOUT;
+        
+        /* Process Unlocked */
+        __HAL_UNLOCK(hdma);
+        
+        return HAL_TIMEOUT;
+      }
+    }
+    
+    /* Clear all interrupt flags at correct offset within the register */
+    regs->IFCR = 0x3FU << hdma->StreamIndex;
+    
+    /* Change the DMA state*/
+    hdma->State = HAL_DMA_STATE_READY;
+    
+    /* Process Unlocked */
+    __HAL_UNLOCK(hdma);
+  }
+  return HAL_OK;
+}
+
+/**
+  * @brief  Aborts the DMA Transfer in Interrupt mode.
+  * @param  hdma   pointer to a DMA_HandleTypeDef structure that contains
+  *                 the configuration information for the specified DMA Stream.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma)
+{
+  if(hdma->State != HAL_DMA_STATE_BUSY)
+  {
+    hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
+    return HAL_ERROR;
+  }
+  else
+  {
+    /* Set Abort State  */
+    hdma->State = HAL_DMA_STATE_ABORT;
+    
+    /* Disable the stream */
+    __HAL_DMA_DISABLE(hdma);
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Polling for transfer complete.
+  * @param  hdma          pointer to a DMA_HandleTypeDef structure that contains
+  *                        the configuration information for the specified DMA Stream.
+  * @param  CompleteLevel Specifies the DMA level complete.
+  * @note   The polling mode is kept in this version for legacy. it is recommended to use the IT model instead.
+  *         This model could be used for debug purpose.
+  * @note   The HAL_DMA_PollForTransfer API cannot be used in circular and double buffering mode (automatic circular mode). 
+  * @param  Timeout       Timeout duration.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout)
+{
+  HAL_StatusTypeDef status = HAL_OK; 
+  uint32_t mask_cpltlevel;
+  uint32_t tickstart = HAL_GetTick(); 
+  uint32_t tmpisr;
+  
+  /* calculate DMA base and stream number */
+  DMA_Base_Registers *regs;
+
+  if(HAL_DMA_STATE_BUSY != hdma->State)
+  {
+    /* No transfer ongoing */
+    hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
+    __HAL_UNLOCK(hdma);
+    return HAL_ERROR;
+  }
+
+  /* Polling mode not supported in circular mode and double buffering mode */
+  if ((hdma->Instance->CR & DMA_SxCR_CIRC) != RESET)
+  {
+    hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED;
+    return HAL_ERROR;
+  }
+  
+  /* Get the level transfer complete flag */
+  if(CompleteLevel == HAL_DMA_FULL_TRANSFER)
+  {
+    /* Transfer Complete flag */
+    mask_cpltlevel = DMA_FLAG_TCIF0_4 << hdma->StreamIndex;
+  }
+  else
+  {
+    /* Half Transfer Complete flag */
+    mask_cpltlevel = DMA_FLAG_HTIF0_4 << hdma->StreamIndex;
+  }
+  
+  regs = (DMA_Base_Registers *)hdma->StreamBaseAddress;
+  tmpisr = regs->ISR;
+  
+  while(((tmpisr & mask_cpltlevel) == RESET) && ((hdma->ErrorCode & HAL_DMA_ERROR_TE) == RESET))
+  {
+    /* Check for the Timeout (Not applicable in circular mode)*/
+    if(Timeout != HAL_MAX_DELAY)
+    {
+      if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
+      {
+        /* Update error code */
+        hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT;
+        
+        /* Change the DMA state */
+        hdma->State = HAL_DMA_STATE_READY;
+        
+        /* Process Unlocked */
+        __HAL_UNLOCK(hdma);
+        
+        return HAL_TIMEOUT;
+      }
+    }
+
+    /* Get the ISR register value */
+    tmpisr = regs->ISR;
+
+    if((tmpisr & (DMA_FLAG_TEIF0_4 << hdma->StreamIndex)) != RESET)
+    {
+      /* Update error code */
+      hdma->ErrorCode |= HAL_DMA_ERROR_TE;
+      
+      /* Clear the transfer error flag */
+      regs->IFCR = DMA_FLAG_TEIF0_4 << hdma->StreamIndex;
+    }
+    
+    if((tmpisr & (DMA_FLAG_FEIF0_4 << hdma->StreamIndex)) != RESET)
+    {
+      /* Update error code */
+      hdma->ErrorCode |= HAL_DMA_ERROR_FE;
+      
+      /* Clear the FIFO error flag */
+      regs->IFCR = DMA_FLAG_FEIF0_4 << hdma->StreamIndex;
+    }
+    
+    if((tmpisr & (DMA_FLAG_DMEIF0_4 << hdma->StreamIndex)) != RESET)
+    {
+      /* Update error code */
+      hdma->ErrorCode |= HAL_DMA_ERROR_DME;
+      
+      /* Clear the Direct Mode error flag */
+      regs->IFCR = DMA_FLAG_DMEIF0_4 << hdma->StreamIndex;
+    }
+  }
+  
+  if(hdma->ErrorCode != HAL_DMA_ERROR_NONE)
+  {
+    if((hdma->ErrorCode & HAL_DMA_ERROR_TE) != RESET)
+    {
+      HAL_DMA_Abort(hdma);
+    
+      /* Clear the half transfer and transfer complete flags */
+      regs->IFCR = (DMA_FLAG_HTIF0_4 | DMA_FLAG_TCIF0_4) << hdma->StreamIndex;
+    
+      /* Change the DMA state */
+      hdma->State= HAL_DMA_STATE_READY;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hdma);
+
+      return HAL_ERROR;
+   }
+  }
+  
+  /* Get the level transfer complete flag */
+  if(CompleteLevel == HAL_DMA_FULL_TRANSFER)
+  {
+    /* Clear the half transfer and transfer complete flags */
+    regs->IFCR = (DMA_FLAG_HTIF0_4 | DMA_FLAG_TCIF0_4) << hdma->StreamIndex;
+    
+    hdma->State = HAL_DMA_STATE_READY;
+    
+    /* Process Unlocked */
+    __HAL_UNLOCK(hdma);
+  }
+  else
+  {
+    /* Clear the half transfer and transfer complete flags */
+    regs->IFCR = (DMA_FLAG_HTIF0_4) << hdma->StreamIndex;
+  }
+  
+  return status;
+}
+
+/**
+  * @brief  Handles DMA interrupt request.
+  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
+  *               the configuration information for the specified DMA Stream.  
+  * @retval None
+  */
+void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
+{
+  uint32_t tmpisr;
+  __IO uint32_t count = 0U;
+  uint32_t timeout = SystemCoreClock / 9600U;
+
+  /* calculate DMA base and stream number */
+  DMA_Base_Registers *regs = (DMA_Base_Registers *)hdma->StreamBaseAddress;
+
+  tmpisr = regs->ISR;
+
+  /* Transfer Error Interrupt management ***************************************/
+  if ((tmpisr & (DMA_FLAG_TEIF0_4 << hdma->StreamIndex)) != RESET)
+  {
+    if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TE) != RESET)
+    {
+      /* Disable the transfer error interrupt */
+      hdma->Instance->CR  &= ~(DMA_IT_TE);
+      
+      /* Clear the transfer error flag */
+      regs->IFCR = DMA_FLAG_TEIF0_4 << hdma->StreamIndex;
+      
+      /* Update error code */
+      hdma->ErrorCode |= HAL_DMA_ERROR_TE;
+    }
+  }
+  /* FIFO Error Interrupt management ******************************************/
+  if ((tmpisr & (DMA_FLAG_FEIF0_4 << hdma->StreamIndex)) != RESET)
+  {
+    if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_FE) != RESET)
+    {
+      /* Clear the FIFO error flag */
+      regs->IFCR = DMA_FLAG_FEIF0_4 << hdma->StreamIndex;
+
+      /* Update error code */
+      hdma->ErrorCode |= HAL_DMA_ERROR_FE;
+    }
+  }
+  /* Direct Mode Error Interrupt management ***********************************/
+  if ((tmpisr & (DMA_FLAG_DMEIF0_4 << hdma->StreamIndex)) != RESET)
+  {
+    if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_DME) != RESET)
+    {
+      /* Clear the direct mode error flag */
+      regs->IFCR = DMA_FLAG_DMEIF0_4 << hdma->StreamIndex;
+
+      /* Update error code */
+      hdma->ErrorCode |= HAL_DMA_ERROR_DME;
+    }
+  }
+  /* Half Transfer Complete Interrupt management ******************************/
+  if ((tmpisr & (DMA_FLAG_HTIF0_4 << hdma->StreamIndex)) != RESET)
+  {
+    if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_HT) != RESET)
+    {
+      /* Clear the half transfer complete flag */
+      regs->IFCR = DMA_FLAG_HTIF0_4 << hdma->StreamIndex;
+      
+      /* Multi_Buffering mode enabled */
+      if(((hdma->Instance->CR) & (uint32_t)(DMA_SxCR_DBM)) != RESET)
+      {
+        /* Current memory buffer used is Memory 0 */
+        if((hdma->Instance->CR & DMA_SxCR_CT) == RESET)
+        {
+          if(hdma->XferHalfCpltCallback != NULL)
+          {
+            /* Half transfer callback */
+            hdma->XferHalfCpltCallback(hdma);
+          }
+        }
+        /* Current memory buffer used is Memory 1 */
+        else
+        {
+          if(hdma->XferM1HalfCpltCallback != NULL)
+          {
+            /* Half transfer callback */
+            hdma->XferM1HalfCpltCallback(hdma);
+          }
+        }
+      }
+      else
+      {
+        /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */
+        if((hdma->Instance->CR & DMA_SxCR_CIRC) == RESET)
+        {
+          /* Disable the half transfer interrupt */
+          hdma->Instance->CR  &= ~(DMA_IT_HT);
+        }
+        
+        if(hdma->XferHalfCpltCallback != NULL)
+        {
+          /* Half transfer callback */
+          hdma->XferHalfCpltCallback(hdma);
+        }
+      }
+    }
+  }
+  /* Transfer Complete Interrupt management ***********************************/
+  if ((tmpisr & (DMA_FLAG_TCIF0_4 << hdma->StreamIndex)) != RESET)
+  {
+    if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TC) != RESET)
+    {
+      /* Clear the transfer complete flag */
+      regs->IFCR = DMA_FLAG_TCIF0_4 << hdma->StreamIndex;
+      
+      if(HAL_DMA_STATE_ABORT == hdma->State)
+      {
+        /* Disable all the transfer interrupts */
+        hdma->Instance->CR  &= ~(DMA_IT_TC | DMA_IT_TE | DMA_IT_DME);
+        hdma->Instance->FCR &= ~(DMA_IT_FE);
+        
+        if((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL))
+        {
+          hdma->Instance->CR  &= ~(DMA_IT_HT);
+        }
+
+        /* Clear all interrupt flags at correct offset within the register */
+        regs->IFCR = 0x3FU << hdma->StreamIndex;
+
+        /* Change the DMA state */
+        hdma->State = HAL_DMA_STATE_READY;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hdma);
+
+        if(hdma->XferAbortCallback != NULL)
+        {
+          hdma->XferAbortCallback(hdma);
+        }
+        return;
+      }
+
+      if(((hdma->Instance->CR) & (uint32_t)(DMA_SxCR_DBM)) != RESET)
+      {
+        /* Current memory buffer used is Memory 0 */
+        if((hdma->Instance->CR & DMA_SxCR_CT) == RESET)
+        {
+          if(hdma->XferM1CpltCallback != NULL)
+          {
+            /* Transfer complete Callback for memory1 */
+            hdma->XferM1CpltCallback(hdma);
+          }
+        }
+        /* Current memory buffer used is Memory 1 */
+        else
+        {
+          if(hdma->XferCpltCallback != NULL)
+          {
+            /* Transfer complete Callback for memory0 */
+            hdma->XferCpltCallback(hdma);
+          }
+        }
+      }
+      /* Disable the transfer complete interrupt if the DMA mode is not CIRCULAR */
+      else
+      {
+        if((hdma->Instance->CR & DMA_SxCR_CIRC) == RESET)
+        {
+          /* Disable the transfer complete interrupt */
+          hdma->Instance->CR  &= ~(DMA_IT_TC);
+
+          /* Change the DMA state */
+          hdma->State = HAL_DMA_STATE_READY;
+
+          /* Process Unlocked */
+          __HAL_UNLOCK(hdma);
+        }
+
+        if(hdma->XferCpltCallback != NULL)
+        {
+          /* Transfer complete callback */
+          hdma->XferCpltCallback(hdma);
+        }
+      }
+    }
+  }
+  
+  /* manage error case */
+  if(hdma->ErrorCode != HAL_DMA_ERROR_NONE)
+  {
+    if((hdma->ErrorCode & HAL_DMA_ERROR_TE) != RESET)
+    {
+      hdma->State = HAL_DMA_STATE_ABORT;
+
+      /* Disable the stream */
+      __HAL_DMA_DISABLE(hdma);
+
+      do
+      {
+        if (++count > timeout)
+        {
+          break;
+        }
+      }
+      while((hdma->Instance->CR & DMA_SxCR_EN) != RESET);
+
+      /* Change the DMA state */
+      hdma->State = HAL_DMA_STATE_READY;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hdma);
+    }
+
+    if(hdma->XferErrorCallback != NULL)
+    {
+      /* Transfer error callback */
+      hdma->XferErrorCallback(hdma);
+    }
+  }
+}
+
+/**
+  * @brief  Register callbacks
+  * @param  hdma                 pointer to a DMA_HandleTypeDef structure that contains
+  *                               the configuration information for the specified DMA Stream.
+  * @param  CallbackID           User Callback identifier
+  *                               a DMA_HandleTypeDef structure as parameter.
+  * @param  pCallback            pointer to private callback function which has pointer to 
+  *                               a DMA_HandleTypeDef structure as parameter.
+  * @retval HAL status
+  */                      
+HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)(DMA_HandleTypeDef *_hdma))
+{
+
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Process locked */
+  __HAL_LOCK(hdma);
+
+  if(HAL_DMA_STATE_READY == hdma->State)
+  {
+    switch (CallbackID)
+    {
+    case  HAL_DMA_XFER_CPLT_CB_ID:
+      hdma->XferCpltCallback = pCallback;
+      break;
+
+    case  HAL_DMA_XFER_HALFCPLT_CB_ID:
+      hdma->XferHalfCpltCallback = pCallback;
+      break;
+
+    case  HAL_DMA_XFER_M1CPLT_CB_ID:
+      hdma->XferM1CpltCallback = pCallback;
+      break;
+
+    case  HAL_DMA_XFER_M1HALFCPLT_CB_ID:
+      hdma->XferM1HalfCpltCallback = pCallback;
+      break;
+
+    case  HAL_DMA_XFER_ERROR_CB_ID:
+      hdma->XferErrorCallback = pCallback;
+      break;
+
+    case  HAL_DMA_XFER_ABORT_CB_ID:
+      hdma->XferAbortCallback = pCallback;
+      break;
+
+    default:
+      /* Return error status */
+      status =  HAL_ERROR;
+      break;
+    }
+  }
+  else
+  {
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(hdma);
+  
+  return status;
+}
+
+/**
+  * @brief  UnRegister callbacks
+  * @param  hdma                 pointer to a DMA_HandleTypeDef structure that contains
+  *                               the configuration information for the specified DMA Stream.
+  * @param  CallbackID           User Callback identifier
+  *                               a HAL_DMA_CallbackIDTypeDef ENUM as parameter.
+  * @retval HAL status
+  */              
+HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  
+  /* Process locked */
+  __HAL_LOCK(hdma);
+  
+  if(HAL_DMA_STATE_READY == hdma->State)
+  {
+    switch (CallbackID)
+    {
+    case  HAL_DMA_XFER_CPLT_CB_ID:
+      hdma->XferCpltCallback = NULL;
+      break;
+      
+    case  HAL_DMA_XFER_HALFCPLT_CB_ID:
+      hdma->XferHalfCpltCallback = NULL;
+      break;
+      
+    case  HAL_DMA_XFER_M1CPLT_CB_ID:
+      hdma->XferM1CpltCallback = NULL;
+      break;
+      
+    case  HAL_DMA_XFER_M1HALFCPLT_CB_ID:
+      hdma->XferM1HalfCpltCallback = NULL;
+      break;
+      
+    case  HAL_DMA_XFER_ERROR_CB_ID:
+      hdma->XferErrorCallback = NULL;
+      break;
+      
+    case  HAL_DMA_XFER_ABORT_CB_ID:
+      hdma->XferAbortCallback = NULL;
+      break; 
+      
+    case   HAL_DMA_XFER_ALL_CB_ID:
+      hdma->XferCpltCallback = NULL;
+      hdma->XferHalfCpltCallback = NULL;
+      hdma->XferM1CpltCallback = NULL;
+      hdma->XferM1HalfCpltCallback = NULL;
+      hdma->XferErrorCallback = NULL;
+      hdma->XferAbortCallback = NULL;
+      break; 
+      
+    default:
+      status = HAL_ERROR;
+      break;
+    }
+  }
+  else
+  {
+    status = HAL_ERROR;
+  }
+  
+  /* Release Lock */
+  __HAL_UNLOCK(hdma);
+  
+  return status;
+}
+
+/**
+  * @}
+  */
+
+/** @addtogroup DMA_Exported_Functions_Group3
+  *
+@verbatim
+ ===============================================================================
+                    ##### State and Errors functions #####
+ ===============================================================================
+    [..]
+    This subsection provides functions allowing to
+      (+) Check the DMA state
+      (+) Get error code
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Returns the DMA state.
+  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
+  *               the configuration information for the specified DMA Stream.
+  * @retval HAL state
+  */
+HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma)
+{
+  return hdma->State;
+}
+
+/**
+  * @brief  Return the DMA error code
+  * @param  hdma  pointer to a DMA_HandleTypeDef structure that contains
+  *              the configuration information for the specified DMA Stream.
+  * @retval DMA Error Code
+  */
+uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma)
+{
+  return hdma->ErrorCode;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup DMA_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Sets the DMA Transfer parameter.
+  * @param  hdma       pointer to a DMA_HandleTypeDef structure that contains
+  *                     the configuration information for the specified DMA Stream.
+  * @param  SrcAddress The source memory Buffer address
+  * @param  DstAddress The destination memory Buffer address
+  * @param  DataLength The length of data to be transferred from source to destination
+  * @retval HAL status
+  */
+static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
+{
+  /* Clear DBM bit */
+  hdma->Instance->CR &= (uint32_t)(~DMA_SxCR_DBM);
+
+  /* Configure DMA Stream data length */
+  hdma->Instance->NDTR = DataLength;
+
+  /* Memory to Peripheral */
+  if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)
+  {
+    /* Configure DMA Stream destination address */
+    hdma->Instance->PAR = DstAddress;
+
+    /* Configure DMA Stream source address */
+    hdma->Instance->M0AR = SrcAddress;
+  }
+  /* Peripheral to Memory */
+  else
+  {
+    /* Configure DMA Stream source address */
+    hdma->Instance->PAR = SrcAddress;
+
+    /* Configure DMA Stream destination address */
+    hdma->Instance->M0AR = DstAddress;
+  }
+}
+
+/**
+  * @brief  Returns the DMA Stream base address depending on stream number
+  * @param  hdma       pointer to a DMA_HandleTypeDef structure that contains
+  *                     the configuration information for the specified DMA Stream. 
+  * @retval Stream base address
+  */
+static uint32_t DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma)
+{
+  uint32_t stream_number = (((uint32_t)hdma->Instance & 0xFFU) - 16U) / 24U;
+  
+  /* lookup table for necessary bitshift of flags within status registers */
+  static const uint8_t flagBitshiftOffset[8U] = {0U, 6U, 16U, 22U, 0U, 6U, 16U, 22U};
+  hdma->StreamIndex = flagBitshiftOffset[stream_number];
+  
+  if (stream_number > 3U)
+  {
+    /* return pointer to HISR and HIFCR */
+    hdma->StreamBaseAddress = (((uint32_t)hdma->Instance & (uint32_t)(~0x3FFU)) + 4U);
+  }
+  else
+  {
+    /* return pointer to LISR and LIFCR */
+    hdma->StreamBaseAddress = ((uint32_t)hdma->Instance & (uint32_t)(~0x3FFU));
+  }
+  
+  return hdma->StreamBaseAddress;
+}
+
+/**
+  * @brief  Check compatibility between FIFO threshold level and size of the memory burst
+  * @param  hdma       pointer to a DMA_HandleTypeDef structure that contains
+  *                     the configuration information for the specified DMA Stream. 
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef DMA_CheckFifoParam(DMA_HandleTypeDef *hdma)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  uint32_t tmp = hdma->Init.FIFOThreshold;
+  
+  /* Memory Data size equal to Byte */
+  if(hdma->Init.MemDataAlignment == DMA_MDATAALIGN_BYTE)
+  {
+    switch (tmp)
+    {
+    case DMA_FIFO_THRESHOLD_1QUARTERFULL:
+    case DMA_FIFO_THRESHOLD_3QUARTERSFULL:
+      if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1)
+      {
+        status = HAL_ERROR;
+      }
+      break;
+    case DMA_FIFO_THRESHOLD_HALFFULL:
+      if (hdma->Init.MemBurst == DMA_MBURST_INC16)
+      {
+        status = HAL_ERROR;
+      }
+      break;
+    case DMA_FIFO_THRESHOLD_FULL:
+      break;
+    default:
+      break;
+    }
+  }
+  
+  /* Memory Data size equal to Half-Word */
+  else if (hdma->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)
+  {
+    switch (tmp)
+    {
+    case DMA_FIFO_THRESHOLD_1QUARTERFULL:
+    case DMA_FIFO_THRESHOLD_3QUARTERSFULL:
+      status = HAL_ERROR;
+      break;
+    case DMA_FIFO_THRESHOLD_HALFFULL:
+      if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1)
+      {
+        status = HAL_ERROR;
+      }
+      break;
+    case DMA_FIFO_THRESHOLD_FULL:
+      if (hdma->Init.MemBurst == DMA_MBURST_INC16)
+      {
+        status = HAL_ERROR;
+      }
+      break;   
+    default:
+      break;
+    }
+  }
+  
+  /* Memory Data size equal to Word */
+  else
+  {
+    switch (tmp)
+    {
+    case DMA_FIFO_THRESHOLD_1QUARTERFULL:
+    case DMA_FIFO_THRESHOLD_HALFFULL:
+    case DMA_FIFO_THRESHOLD_3QUARTERSFULL:
+      status = HAL_ERROR;
+      break;
+    case DMA_FIFO_THRESHOLD_FULL:
+      if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1)
+      {
+        status = HAL_ERROR;
+      }
+      break;
+    default:
+      break;
+    }
+  } 
+  
+  return status; 
+}
+
+/**
+  * @}
+  */
+
+#endif /* HAL_DMA_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
diff --git a/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma2d.c b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma2d.c
new file mode 100644
index 0000000..f06683f
--- /dev/null
+++ b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma2d.c
@@ -0,0 +1,2126 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hal_dma2d.c
+  * @author  MCD Application Team
+  * @brief   DMA2D HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the DMA2D peripheral:
+  *           + Initialization and de-initialization functions
+  *           + IO operation functions
+  *           + Peripheral Control functions
+  *           + Peripheral State and Errors functions
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2016 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  @verbatim
+  ==============================================================================
+                        ##### How to use this driver #####
+  ==============================================================================
+    [..]
+      (#) Program the required configuration through the following parameters:
+          the transfer mode, the output color mode and the output offset using
+          HAL_DMA2D_Init() function.
+
+      (#) Program the required configuration through the following parameters:
+          the input color mode, the input color, the input alpha value, the alpha mode,
+          the red/blue swap mode, the inverted alpha mode and the input offset using
+          HAL_DMA2D_ConfigLayer() function for foreground or/and background layer.
+
+     *** Polling mode IO operation ***
+     =================================
+    [..]
+       (#) Configure pdata parameter (explained hereafter), destination and data length
+           and enable the transfer using HAL_DMA2D_Start().
+       (#) Wait for end of transfer using HAL_DMA2D_PollForTransfer(), at this stage
+           user can specify the value of timeout according to his end application.
+
+     *** Interrupt mode IO operation ***
+     ===================================
+     [..]
+       (#) Configure pdata parameter, destination and data length and enable
+           the transfer using HAL_DMA2D_Start_IT().
+       (#) Use HAL_DMA2D_IRQHandler() called under DMA2D_IRQHandler() interrupt subroutine.
+       (#) At the end of data transfer HAL_DMA2D_IRQHandler() function is executed and user can
+           add his own function by customization of function pointer XferCpltCallback (member
+           of DMA2D handle structure).
+       (#) In case of error, the HAL_DMA2D_IRQHandler() function calls the callback
+           XferErrorCallback.
+
+         -@-   In Register-to-Memory transfer mode, pdata parameter is the register
+               color, in Memory-to-memory or Memory-to-Memory with pixel format
+               conversion pdata is the source address.
+
+         -@-   Configure the foreground source address, the background source address,
+               the destination and data length then Enable the transfer using
+               HAL_DMA2D_BlendingStart() in polling mode and HAL_DMA2D_BlendingStart_IT()
+               in interrupt mode.
+
+         -@-   HAL_DMA2D_BlendingStart() and HAL_DMA2D_BlendingStart_IT() functions
+               are used if the memory to memory with blending transfer mode is selected.
+
+      (#) Optionally, configure and enable the CLUT using HAL_DMA2D_CLUTLoad() in polling
+          mode or HAL_DMA2D_CLUTLoad_IT() in interrupt mode.
+
+      (#) Optionally, configure the line watermark in using the API HAL_DMA2D_ProgramLineEvent().
+
+      (#) Optionally, configure the dead time value in the AHB clock cycle inserted between two
+          consecutive accesses on the AHB master port in using the API HAL_DMA2D_ConfigDeadTime()
+          and enable/disable the functionality  with the APIs HAL_DMA2D_EnableDeadTime() or
+          HAL_DMA2D_DisableDeadTime().
+
+      (#) The transfer can be suspended, resumed and aborted using the following
+          functions: HAL_DMA2D_Suspend(), HAL_DMA2D_Resume(), HAL_DMA2D_Abort().
+
+      (#) The CLUT loading can be suspended, resumed and aborted using the following
+          functions: HAL_DMA2D_CLUTLoading_Suspend(), HAL_DMA2D_CLUTLoading_Resume(),
+          HAL_DMA2D_CLUTLoading_Abort().
+
+      (#) To control the DMA2D state, use the following function: HAL_DMA2D_GetState().
+
+      (#) To read the DMA2D error code, use the following function: HAL_DMA2D_GetError().
+
+     *** DMA2D HAL driver macros list ***
+     =============================================
+     [..]
+       Below the list of most used macros in DMA2D HAL driver :
+
+      (+) __HAL_DMA2D_ENABLE: Enable the DMA2D peripheral.
+      (+) __HAL_DMA2D_GET_FLAG: Get the DMA2D pending flags.
+      (+) __HAL_DMA2D_CLEAR_FLAG: Clear the DMA2D pending flags.
+      (+) __HAL_DMA2D_ENABLE_IT: Enable the specified DMA2D interrupts.
+      (+) __HAL_DMA2D_DISABLE_IT: Disable the specified DMA2D interrupts.
+      (+) __HAL_DMA2D_GET_IT_SOURCE: Check whether the specified DMA2D interrupt is enabled or not.
+
+     *** Callback registration ***
+     ===================================
+     [..]
+      (#) The compilation define  USE_HAL_DMA2D_REGISTER_CALLBACKS when set to 1
+          allows the user to configure dynamically the driver callbacks.
+          Use function @ref HAL_DMA2D_RegisterCallback() to register a user callback.
+
+      (#) Function @ref HAL_DMA2D_RegisterCallback() allows to register following callbacks:
+            (+) XferCpltCallback : callback for transfer complete.
+            (+) XferErrorCallback : callback for transfer error.
+            (+) LineEventCallback : callback for line event.
+            (+) CLUTLoadingCpltCallback : callback for CLUT loading completion.
+            (+) MspInitCallback    : DMA2D MspInit.
+            (+) MspDeInitCallback  : DMA2D MspDeInit.
+          This function takes as parameters the HAL peripheral handle, the Callback ID
+          and a pointer to the user callback function.
+
+      (#) Use function @ref HAL_DMA2D_UnRegisterCallback() to reset a callback to the default
+          weak (surcharged) function.
+          @ref HAL_DMA2D_UnRegisterCallback() takes as parameters the HAL peripheral handle,
+          and the Callback ID.
+          This function allows to reset following callbacks:
+            (+) XferCpltCallback : callback for transfer complete.
+            (+) XferErrorCallback : callback for transfer error.
+            (+) LineEventCallback : callback for line event.
+            (+) CLUTLoadingCpltCallback : callback for CLUT loading completion.
+            (+) MspInitCallback    : DMA2D MspInit.
+            (+) MspDeInitCallback  : DMA2D MspDeInit.
+
+      (#) By default, after the @ref HAL_DMA2D_Init and if the state is HAL_DMA2D_STATE_RESET
+          all callbacks are reset to the corresponding legacy weak (surcharged) functions:
+          examples @ref HAL_DMA2D_LineEventCallback(), @ref HAL_DMA2D_CLUTLoadingCpltCallback()
+          Exception done for MspInit and MspDeInit callbacks that are respectively
+          reset to the legacy weak (surcharged) functions in the @ref HAL_DMA2D_Init
+          and @ref HAL_DMA2D_DeInit only when these callbacks are null (not registered beforehand)
+          If not, MspInit or MspDeInit are not null, the @ref HAL_DMA2D_Init and @ref HAL_DMA2D_DeInit
+          keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
+
+          Exception as well for Transfer Completion and Transfer Error callbacks that are not defined
+          as weak (surcharged) functions. They must be defined by the user to be resorted to.
+
+          Callbacks can be registered/unregistered in READY state only.
+          Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
+          in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
+          during the Init/DeInit.
+          In that case first register the MspInit/MspDeInit user callbacks
+          using @ref HAL_DMA2D_RegisterCallback before calling @ref HAL_DMA2D_DeInit
+          or @ref HAL_DMA2D_Init function.
+
+          When The compilation define USE_HAL_DMA2D_REGISTER_CALLBACKS is set to 0 or
+          not defined, the callback registering feature is not available
+          and weak (surcharged) callbacks are used.
+
+     [..]
+      (@) You can refer to the DMA2D HAL driver header file for more useful macros
+
+  @endverbatim
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal.h"
+
+#ifdef HAL_DMA2D_MODULE_ENABLED
+#if defined (DMA2D)
+
+/** @addtogroup STM32F4xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup DMA2D  DMA2D
+  * @brief DMA2D HAL module driver
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @defgroup DMA2D_Private_Constants DMA2D Private Constants
+  * @{
+  */
+
+/** @defgroup DMA2D_TimeOut DMA2D Time Out
+  * @{
+  */
+#define DMA2D_TIMEOUT_ABORT           (1000U)  /*!<  1s  */
+#define DMA2D_TIMEOUT_SUSPEND         (1000U)  /*!<  1s  */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @addtogroup DMA2D_Private_Functions DMA2D Private Functions
+  * @{
+  */
+static void DMA2D_SetConfig(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width,
+                            uint32_t Height);
+/**
+  * @}
+  */
+
+/* Private functions ---------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup DMA2D_Exported_Functions DMA2D Exported Functions
+  * @{
+  */
+
+/** @defgroup DMA2D_Exported_Functions_Group1 Initialization and de-initialization functions
+  *  @brief   Initialization and Configuration functions
+  *
+@verbatim
+ ===============================================================================
+                ##### Initialization and Configuration functions #####
+ ===============================================================================
+    [..]  This section provides functions allowing to:
+      (+) Initialize and configure the DMA2D
+      (+) De-initialize the DMA2D
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initialize the DMA2D according to the specified
+  *         parameters in the DMA2D_InitTypeDef and create the associated handle.
+  * @param  hdma2d pointer to a DMA2D_HandleTypeDef structure that contains
+  *                 the configuration information for the DMA2D.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMA2D_Init(DMA2D_HandleTypeDef *hdma2d)
+{
+  /* Check the DMA2D peripheral state */
+  if (hdma2d == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_DMA2D_ALL_INSTANCE(hdma2d->Instance));
+  assert_param(IS_DMA2D_MODE(hdma2d->Init.Mode));
+  assert_param(IS_DMA2D_CMODE(hdma2d->Init.ColorMode));
+  assert_param(IS_DMA2D_OFFSET(hdma2d->Init.OutputOffset));
+
+#if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
+  if (hdma2d->State == HAL_DMA2D_STATE_RESET)
+  {
+    /* Reset Callback pointers in HAL_DMA2D_STATE_RESET only */
+    hdma2d->LineEventCallback       = HAL_DMA2D_LineEventCallback;
+    hdma2d->CLUTLoadingCpltCallback = HAL_DMA2D_CLUTLoadingCpltCallback;
+    if (hdma2d->MspInitCallback == NULL)
+    {
+      hdma2d->MspInitCallback = HAL_DMA2D_MspInit;
+    }
+
+    /* Init the low level hardware */
+    hdma2d->MspInitCallback(hdma2d);
+  }
+#else
+  if (hdma2d->State == HAL_DMA2D_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    hdma2d->Lock = HAL_UNLOCKED;
+    /* Init the low level hardware */
+    HAL_DMA2D_MspInit(hdma2d);
+  }
+#endif /* (USE_HAL_DMA2D_REGISTER_CALLBACKS) */
+
+  /* Change DMA2D peripheral state */
+  hdma2d->State = HAL_DMA2D_STATE_BUSY;
+
+  /* DMA2D CR register configuration -------------------------------------------*/
+  MODIFY_REG(hdma2d->Instance->CR, DMA2D_CR_MODE, hdma2d->Init.Mode);
+
+  /* DMA2D OPFCCR register configuration ---------------------------------------*/
+  MODIFY_REG(hdma2d->Instance->OPFCCR, DMA2D_OPFCCR_CM, hdma2d->Init.ColorMode);
+
+  /* DMA2D OOR register configuration ------------------------------------------*/
+  MODIFY_REG(hdma2d->Instance->OOR, DMA2D_OOR_LO, hdma2d->Init.OutputOffset);
+
+
+  /* Update error code */
+  hdma2d->ErrorCode = HAL_DMA2D_ERROR_NONE;
+
+  /* Initialize the DMA2D state*/
+  hdma2d->State  = HAL_DMA2D_STATE_READY;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Deinitializes the DMA2D peripheral registers to their default reset
+  *         values.
+  * @param  hdma2d pointer to a DMA2D_HandleTypeDef structure that contains
+  *                 the configuration information for the DMA2D.
+  * @retval None
+  */
+
+HAL_StatusTypeDef HAL_DMA2D_DeInit(DMA2D_HandleTypeDef *hdma2d)
+{
+
+  /* Check the DMA2D peripheral state */
+  if (hdma2d == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Before aborting any DMA2D transfer or CLUT loading, check
+     first whether or not DMA2D clock is enabled */
+  if (__HAL_RCC_DMA2D_IS_CLK_ENABLED())
+  {
+    /* Abort DMA2D transfer if any */
+    if ((hdma2d->Instance->CR & DMA2D_CR_START) == DMA2D_CR_START)
+    {
+      if (HAL_DMA2D_Abort(hdma2d) != HAL_OK)
+      {
+        /* Issue when aborting DMA2D transfer */
+        return HAL_ERROR;
+      }
+    }
+    else
+    {
+      /* Abort background CLUT loading if any */
+      if ((hdma2d->Instance->BGPFCCR & DMA2D_BGPFCCR_START) == DMA2D_BGPFCCR_START)
+      {
+        if (HAL_DMA2D_CLUTLoading_Abort(hdma2d, 0U) != HAL_OK)
+        {
+          /* Issue when aborting background CLUT loading */
+          return HAL_ERROR;
+        }
+      }
+      else
+      {
+        /* Abort foreground CLUT loading if any */
+        if ((hdma2d->Instance->FGPFCCR & DMA2D_FGPFCCR_START) == DMA2D_FGPFCCR_START)
+        {
+          if (HAL_DMA2D_CLUTLoading_Abort(hdma2d, 1U) != HAL_OK)
+          {
+            /* Issue when aborting foreground CLUT loading */
+            return HAL_ERROR;
+          }
+        }
+      }
+    }
+  }
+
+  /* Reset DMA2D control registers*/
+  hdma2d->Instance->CR       =    0U;
+  hdma2d->Instance->IFCR     = 0x3FU;
+  hdma2d->Instance->FGOR     =    0U;
+  hdma2d->Instance->BGOR     =    0U;
+  hdma2d->Instance->FGPFCCR  =    0U;
+  hdma2d->Instance->BGPFCCR  =    0U;
+  hdma2d->Instance->OPFCCR   =    0U;
+
+#if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
+
+  if (hdma2d->MspDeInitCallback == NULL)
+  {
+    hdma2d->MspDeInitCallback = HAL_DMA2D_MspDeInit;
+  }
+
+  /* DeInit the low level hardware */
+  hdma2d->MspDeInitCallback(hdma2d);
+
+#else
+  /* Carry on with de-initialization of low level hardware */
+  HAL_DMA2D_MspDeInit(hdma2d);
+#endif /* (USE_HAL_DMA2D_REGISTER_CALLBACKS) */
+
+  /* Update error code */
+  hdma2d->ErrorCode = HAL_DMA2D_ERROR_NONE;
+
+  /* Initialize the DMA2D state*/
+  hdma2d->State  = HAL_DMA2D_STATE_RESET;
+
+  /* Release Lock */
+  __HAL_UNLOCK(hdma2d);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the DMA2D MSP.
+  * @param  hdma2d pointer to a DMA2D_HandleTypeDef structure that contains
+  *                 the configuration information for the DMA2D.
+  * @retval None
+  */
+__weak void HAL_DMA2D_MspInit(DMA2D_HandleTypeDef *hdma2d)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hdma2d);
+
+  /* NOTE : This function should not be modified; when the callback is needed,
+            the HAL_DMA2D_MspInit can be implemented in the user file.
+   */
+}
+
+/**
+  * @brief  DeInitializes the DMA2D MSP.
+  * @param  hdma2d pointer to a DMA2D_HandleTypeDef structure that contains
+  *                 the configuration information for the DMA2D.
+  * @retval None
+  */
+__weak void HAL_DMA2D_MspDeInit(DMA2D_HandleTypeDef *hdma2d)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hdma2d);
+
+  /* NOTE : This function should not be modified; when the callback is needed,
+            the HAL_DMA2D_MspDeInit can be implemented in the user file.
+   */
+}
+
+#if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
+/**
+  * @brief  Register a User DMA2D Callback
+  *         To be used instead of the weak (surcharged) predefined callback
+  * @param hdma2d DMA2D handle
+  * @param CallbackID ID of the callback to be registered
+  *        This parameter can be one of the following values:
+  *          @arg @ref HAL_DMA2D_TRANSFERCOMPLETE_CB_ID DMA2D transfer complete Callback ID
+  *          @arg @ref HAL_DMA2D_TRANSFERERROR_CB_ID DMA2D transfer error Callback ID
+  *          @arg @ref HAL_DMA2D_LINEEVENT_CB_ID DMA2D line event Callback ID
+  *          @arg @ref HAL_DMA2D_CLUTLOADINGCPLT_CB_ID DMA2D CLUT loading completion Callback ID
+  *          @arg @ref HAL_DMA2D_MSPINIT_CB_ID DMA2D MspInit callback ID
+  *          @arg @ref HAL_DMA2D_MSPDEINIT_CB_ID DMA2D MspDeInit callback ID
+  * @param pCallback pointer to the Callback function
+  * @note No weak predefined callbacks are defined for HAL_DMA2D_TRANSFERCOMPLETE_CB_ID or HAL_DMA2D_TRANSFERERROR_CB_ID
+  * @retval status
+  */
+HAL_StatusTypeDef HAL_DMA2D_RegisterCallback(DMA2D_HandleTypeDef *hdma2d, HAL_DMA2D_CallbackIDTypeDef CallbackID,
+                                             pDMA2D_CallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    /* Update the error code */
+    hdma2d->ErrorCode |= HAL_DMA2D_ERROR_INVALID_CALLBACK;
+    return HAL_ERROR;
+  }
+  /* Process locked */
+  __HAL_LOCK(hdma2d);
+
+  if (HAL_DMA2D_STATE_READY == hdma2d->State)
+  {
+    switch (CallbackID)
+    {
+      case HAL_DMA2D_TRANSFERCOMPLETE_CB_ID :
+        hdma2d->XferCpltCallback = pCallback;
+        break;
+
+      case HAL_DMA2D_TRANSFERERROR_CB_ID :
+        hdma2d->XferErrorCallback = pCallback;
+        break;
+
+      case HAL_DMA2D_LINEEVENT_CB_ID :
+        hdma2d->LineEventCallback = pCallback;
+        break;
+
+      case HAL_DMA2D_CLUTLOADINGCPLT_CB_ID :
+        hdma2d->CLUTLoadingCpltCallback = pCallback;
+        break;
+
+      case HAL_DMA2D_MSPINIT_CB_ID :
+        hdma2d->MspInitCallback = pCallback;
+        break;
+
+      case HAL_DMA2D_MSPDEINIT_CB_ID :
+        hdma2d->MspDeInitCallback = pCallback;
+        break;
+
+      default :
+        /* Update the error code */
+        hdma2d->ErrorCode |= HAL_DMA2D_ERROR_INVALID_CALLBACK;
+        /* update return status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else if (HAL_DMA2D_STATE_RESET == hdma2d->State)
+  {
+    switch (CallbackID)
+    {
+      case HAL_DMA2D_MSPINIT_CB_ID :
+        hdma2d->MspInitCallback = pCallback;
+        break;
+
+      case HAL_DMA2D_MSPDEINIT_CB_ID :
+        hdma2d->MspDeInitCallback = pCallback;
+        break;
+
+      default :
+        /* Update the error code */
+        hdma2d->ErrorCode |= HAL_DMA2D_ERROR_INVALID_CALLBACK;
+        /* update return status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    /* Update the error code */
+    hdma2d->ErrorCode |= HAL_DMA2D_ERROR_INVALID_CALLBACK;
+    /* update return status */
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(hdma2d);
+  return status;
+}
+
+/**
+  * @brief  Unregister a DMA2D Callback
+  *         DMA2D Callback is redirected to the weak (surcharged) predefined callback
+  * @param hdma2d DMA2D handle
+  * @param CallbackID ID of the callback to be unregistered
+  *        This parameter can be one of the following values:
+  *          @arg @ref HAL_DMA2D_TRANSFERCOMPLETE_CB_ID DMA2D transfer complete Callback ID
+  *          @arg @ref HAL_DMA2D_TRANSFERERROR_CB_ID DMA2D transfer error Callback ID
+  *          @arg @ref HAL_DMA2D_LINEEVENT_CB_ID DMA2D line event Callback ID
+  *          @arg @ref HAL_DMA2D_CLUTLOADINGCPLT_CB_ID DMA2D CLUT loading completion Callback ID
+  *          @arg @ref HAL_DMA2D_MSPINIT_CB_ID DMA2D MspInit callback ID
+  *          @arg @ref HAL_DMA2D_MSPDEINIT_CB_ID DMA2D MspDeInit callback ID
+  * @note No weak predefined callbacks are defined for HAL_DMA2D_TRANSFERCOMPLETE_CB_ID or HAL_DMA2D_TRANSFERERROR_CB_ID
+  * @retval status
+  */
+HAL_StatusTypeDef HAL_DMA2D_UnRegisterCallback(DMA2D_HandleTypeDef *hdma2d, HAL_DMA2D_CallbackIDTypeDef CallbackID)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Process locked */
+  __HAL_LOCK(hdma2d);
+
+  if (HAL_DMA2D_STATE_READY == hdma2d->State)
+  {
+    switch (CallbackID)
+    {
+      case HAL_DMA2D_TRANSFERCOMPLETE_CB_ID :
+        hdma2d->XferCpltCallback = NULL;
+        break;
+
+      case HAL_DMA2D_TRANSFERERROR_CB_ID :
+        hdma2d->XferErrorCallback = NULL;
+        break;
+
+      case HAL_DMA2D_LINEEVENT_CB_ID :
+        hdma2d->LineEventCallback = HAL_DMA2D_LineEventCallback;
+        break;
+
+      case HAL_DMA2D_CLUTLOADINGCPLT_CB_ID :
+        hdma2d->CLUTLoadingCpltCallback = HAL_DMA2D_CLUTLoadingCpltCallback;
+        break;
+
+      case HAL_DMA2D_MSPINIT_CB_ID :
+        hdma2d->MspInitCallback = HAL_DMA2D_MspInit; /* Legacy weak (surcharged) Msp Init */
+        break;
+
+      case HAL_DMA2D_MSPDEINIT_CB_ID :
+        hdma2d->MspDeInitCallback = HAL_DMA2D_MspDeInit; /* Legacy weak (surcharged) Msp DeInit */
+        break;
+
+      default :
+        /* Update the error code */
+        hdma2d->ErrorCode |= HAL_DMA2D_ERROR_INVALID_CALLBACK;
+        /* update return status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else if (HAL_DMA2D_STATE_RESET == hdma2d->State)
+  {
+    switch (CallbackID)
+    {
+      case HAL_DMA2D_MSPINIT_CB_ID :
+        hdma2d->MspInitCallback = HAL_DMA2D_MspInit;   /* Legacy weak (surcharged) Msp Init */
+        break;
+
+      case HAL_DMA2D_MSPDEINIT_CB_ID :
+        hdma2d->MspDeInitCallback = HAL_DMA2D_MspDeInit;  /* Legacy weak (surcharged) Msp DeInit */
+        break;
+
+      default :
+        /* Update the error code */
+        hdma2d->ErrorCode |= HAL_DMA2D_ERROR_INVALID_CALLBACK;
+        /* update return status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    /* Update the error code */
+    hdma2d->ErrorCode |= HAL_DMA2D_ERROR_INVALID_CALLBACK;
+    /* update return status */
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(hdma2d);
+  return status;
+}
+#endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+
+
+/** @defgroup DMA2D_Exported_Functions_Group2 IO operation functions
+  *  @brief   IO operation functions
+  *
+@verbatim
+ ===============================================================================
+                      #####  IO operation functions  #####
+ ===============================================================================
+    [..]  This section provides functions allowing to:
+      (+) Configure the pdata, destination address and data size then
+          start the DMA2D transfer.
+      (+) Configure the source for foreground and background, destination address
+          and data size then start a MultiBuffer DMA2D transfer.
+      (+) Configure the pdata, destination address and data size then
+          start the DMA2D transfer with interrupt.
+      (+) Configure the source for foreground and background, destination address
+          and data size then start a MultiBuffer DMA2D transfer with interrupt.
+      (+) Abort DMA2D transfer.
+      (+) Suspend DMA2D transfer.
+      (+) Resume DMA2D transfer.
+      (+) Enable CLUT transfer.
+      (+) Configure CLUT loading then start transfer in polling mode.
+      (+) Configure CLUT loading then start transfer in interrupt mode.
+      (+) Abort DMA2D CLUT loading.
+      (+) Suspend DMA2D CLUT loading.
+      (+) Resume DMA2D CLUT loading.
+      (+) Poll for transfer complete.
+      (+) handle DMA2D interrupt request.
+      (+) Transfer watermark callback.
+      (+) CLUT Transfer Complete callback.
+
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Start the DMA2D Transfer.
+  * @param  hdma2d     Pointer to a DMA2D_HandleTypeDef structure that contains
+  *                     the configuration information for the DMA2D.
+  * @param  pdata      Configure the source memory Buffer address if
+  *                     Memory-to-Memory or Memory-to-Memory with pixel format
+  *                     conversion mode is selected, or configure
+  *                     the color value if Register-to-Memory mode is selected.
+  * @param  DstAddress The destination memory Buffer address.
+  * @param  Width      The width of data to be transferred from source
+  *                    to destination (expressed in number of pixels per line).
+  * @param  Height     The height of data to be transferred from source to destination (expressed in number of lines).
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMA2D_Start(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width,
+                                  uint32_t Height)
+{
+  /* Check the parameters */
+  assert_param(IS_DMA2D_LINE(Height));
+  assert_param(IS_DMA2D_PIXEL(Width));
+
+  /* Process locked */
+  __HAL_LOCK(hdma2d);
+
+  /* Change DMA2D peripheral state */
+  hdma2d->State = HAL_DMA2D_STATE_BUSY;
+
+  /* Configure the source, destination address and the data size */
+  DMA2D_SetConfig(hdma2d, pdata, DstAddress, Width, Height);
+
+  /* Enable the Peripheral */
+  __HAL_DMA2D_ENABLE(hdma2d);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Start the DMA2D Transfer with interrupt enabled.
+  * @param  hdma2d     Pointer to a DMA2D_HandleTypeDef structure that contains
+  *                     the configuration information for the DMA2D.
+  * @param  pdata      Configure the source memory Buffer address if
+  *                     the Memory-to-Memory or Memory-to-Memory with pixel format
+  *                     conversion mode is selected, or configure
+  *                     the color value if Register-to-Memory mode is selected.
+  * @param  DstAddress The destination memory Buffer address.
+  * @param  Width      The width of data to be transferred from source
+  *                    to destination (expressed in number of pixels per line).
+  * @param  Height     The height of data to be transferred from source to destination (expressed in number of lines).
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMA2D_Start_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width,
+                                     uint32_t Height)
+{
+  /* Check the parameters */
+  assert_param(IS_DMA2D_LINE(Height));
+  assert_param(IS_DMA2D_PIXEL(Width));
+
+  /* Process locked */
+  __HAL_LOCK(hdma2d);
+
+  /* Change DMA2D peripheral state */
+  hdma2d->State = HAL_DMA2D_STATE_BUSY;
+
+  /* Configure the source, destination address and the data size */
+  DMA2D_SetConfig(hdma2d, pdata, DstAddress, Width, Height);
+
+  /* Enable the transfer complete, transfer error and configuration error interrupts */
+  __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_TC | DMA2D_IT_TE | DMA2D_IT_CE);
+
+  /* Enable the Peripheral */
+  __HAL_DMA2D_ENABLE(hdma2d);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Start the multi-source DMA2D Transfer.
+  * @param  hdma2d      Pointer to a DMA2D_HandleTypeDef structure that contains
+  *                      the configuration information for the DMA2D.
+  * @param  SrcAddress1 The source memory Buffer address for the foreground layer.
+  * @param  SrcAddress2 The source memory Buffer address for the background layer.
+  * @param  DstAddress  The destination memory Buffer address.
+  * @param  Width       The width of data to be transferred from source
+  *                     to destination (expressed in number of pixels per line).
+  * @param  Height      The height of data to be transferred from source to destination (expressed in number of lines).
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMA2D_BlendingStart(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t  SrcAddress2,
+                                          uint32_t DstAddress, uint32_t Width,  uint32_t Height)
+{
+  /* Check the parameters */
+  assert_param(IS_DMA2D_LINE(Height));
+  assert_param(IS_DMA2D_PIXEL(Width));
+
+  /* Process locked */
+  __HAL_LOCK(hdma2d);
+
+  /* Change DMA2D peripheral state */
+  hdma2d->State = HAL_DMA2D_STATE_BUSY;
+
+  /* Configure DMA2D Stream source2 address */
+  WRITE_REG(hdma2d->Instance->BGMAR, SrcAddress2);
+
+  /* Configure the source, destination address and the data size */
+  DMA2D_SetConfig(hdma2d, SrcAddress1, DstAddress, Width, Height);
+
+  /* Enable the Peripheral */
+  __HAL_DMA2D_ENABLE(hdma2d);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Start the multi-source DMA2D Transfer with interrupt enabled.
+  * @param  hdma2d     Pointer to a DMA2D_HandleTypeDef structure that contains
+  *                     the configuration information for the DMA2D.
+  * @param  SrcAddress1 The source memory Buffer address for the foreground layer.
+  * @param  SrcAddress2 The source memory Buffer address for the background layer.
+  * @param  DstAddress  The destination memory Buffer address.
+  * @param  Width       The width of data to be transferred from source
+  *                     to destination (expressed in number of pixels per line).
+  * @param  Height      The height of data to be transferred from source to destination (expressed in number of lines).
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMA2D_BlendingStart_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t  SrcAddress2,
+                                             uint32_t DstAddress, uint32_t Width,  uint32_t Height)
+{
+  /* Check the parameters */
+  assert_param(IS_DMA2D_LINE(Height));
+  assert_param(IS_DMA2D_PIXEL(Width));
+
+  /* Process locked */
+  __HAL_LOCK(hdma2d);
+
+  /* Change DMA2D peripheral state */
+  hdma2d->State = HAL_DMA2D_STATE_BUSY;
+
+  /* Configure DMA2D Stream source2 address */
+  WRITE_REG(hdma2d->Instance->BGMAR, SrcAddress2);
+
+  /* Configure the source, destination address and the data size */
+  DMA2D_SetConfig(hdma2d, SrcAddress1, DstAddress, Width, Height);
+
+  /* Enable the transfer complete, transfer error and configuration error interrupts */
+  __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_TC | DMA2D_IT_TE | DMA2D_IT_CE);
+
+  /* Enable the Peripheral */
+  __HAL_DMA2D_ENABLE(hdma2d);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Abort the DMA2D Transfer.
+  * @param  hdma2d  pointer to a DMA2D_HandleTypeDef structure that contains
+  *                  the configuration information for the DMA2D.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMA2D_Abort(DMA2D_HandleTypeDef *hdma2d)
+{
+  uint32_t tickstart;
+
+  /* Abort the DMA2D transfer */
+  /* START bit is reset to make sure not to set it again, in the event the HW clears it
+     between the register read and the register write by the CPU (writing 0 has no
+     effect on START bitvalue) */
+  MODIFY_REG(hdma2d->Instance->CR, DMA2D_CR_ABORT | DMA2D_CR_START, DMA2D_CR_ABORT);
+
+  /* Get tick */
+  tickstart = HAL_GetTick();
+
+  /* Check if the DMA2D is effectively disabled */
+  while ((hdma2d->Instance->CR & DMA2D_CR_START) != 0U)
+  {
+    if ((HAL_GetTick() - tickstart) > DMA2D_TIMEOUT_ABORT)
+    {
+      /* Update error code */
+      hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;
+
+      /* Change the DMA2D state */
+      hdma2d->State = HAL_DMA2D_STATE_TIMEOUT;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hdma2d);
+
+      return HAL_TIMEOUT;
+    }
+  }
+
+  /* Disable the Transfer Complete, Transfer Error and Configuration Error interrupts */
+  __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TC | DMA2D_IT_TE | DMA2D_IT_CE);
+
+  /* Change the DMA2D state*/
+  hdma2d->State = HAL_DMA2D_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hdma2d);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Suspend the DMA2D Transfer.
+  * @param  hdma2d pointer to a DMA2D_HandleTypeDef structure that contains
+  *                 the configuration information for the DMA2D.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMA2D_Suspend(DMA2D_HandleTypeDef *hdma2d)
+{
+  uint32_t tickstart;
+
+  /* Suspend the DMA2D transfer */
+  /* START bit is reset to make sure not to set it again, in the event the HW clears it
+     between the register read and the register write by the CPU (writing 0 has no
+     effect on START bitvalue). */
+  MODIFY_REG(hdma2d->Instance->CR, DMA2D_CR_SUSP | DMA2D_CR_START, DMA2D_CR_SUSP);
+
+  /* Get tick */
+  tickstart = HAL_GetTick();
+
+  /* Check if the DMA2D is effectively suspended */
+  while ((hdma2d->Instance->CR & (DMA2D_CR_SUSP | DMA2D_CR_START)) == DMA2D_CR_START)
+  {
+    if ((HAL_GetTick() - tickstart) > DMA2D_TIMEOUT_SUSPEND)
+    {
+      /* Update error code */
+      hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;
+
+      /* Change the DMA2D state */
+      hdma2d->State = HAL_DMA2D_STATE_TIMEOUT;
+
+      return HAL_TIMEOUT;
+    }
+  }
+
+  /* Check whether or not a transfer is actually suspended and change the DMA2D state accordingly */
+  if ((hdma2d->Instance->CR & DMA2D_CR_START) != 0U)
+  {
+    hdma2d->State = HAL_DMA2D_STATE_SUSPEND;
+  }
+  else
+  {
+    /* Make sure SUSP bit is cleared since it is meaningless
+       when no transfer is on-going */
+    CLEAR_BIT(hdma2d->Instance->CR, DMA2D_CR_SUSP);
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Resume the DMA2D Transfer.
+  * @param  hdma2d pointer to a DMA2D_HandleTypeDef structure that contains
+  *                 the configuration information for the DMA2D.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMA2D_Resume(DMA2D_HandleTypeDef *hdma2d)
+{
+  /* Check the SUSP and START bits */
+  if ((hdma2d->Instance->CR & (DMA2D_CR_SUSP | DMA2D_CR_START)) == (DMA2D_CR_SUSP | DMA2D_CR_START))
+  {
+    /* Ongoing transfer is suspended: change the DMA2D state before resuming */
+    hdma2d->State = HAL_DMA2D_STATE_BUSY;
+  }
+
+  /* Resume the DMA2D transfer */
+  /* START bit is reset to make sure not to set it again, in the event the HW clears it
+     between the register read and the register write by the CPU (writing 0 has no
+     effect on START bitvalue). */
+  CLEAR_BIT(hdma2d->Instance->CR, (DMA2D_CR_SUSP | DMA2D_CR_START));
+
+  return HAL_OK;
+}
+
+
+/**
+  * @brief  Enable the DMA2D CLUT Transfer.
+  * @param  hdma2d   Pointer to a DMA2D_HandleTypeDef structure that contains
+  *                   the configuration information for the DMA2D.
+  * @param  LayerIdx DMA2D Layer index.
+  *                   This parameter can be one of the following values:
+  *                   DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1)
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMA2D_EnableCLUT(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
+{
+  /* Check the parameters */
+  assert_param(IS_DMA2D_LAYER(LayerIdx));
+
+  /* Process locked */
+  __HAL_LOCK(hdma2d);
+
+  /* Change DMA2D peripheral state */
+  hdma2d->State = HAL_DMA2D_STATE_BUSY;
+
+  if (LayerIdx == DMA2D_BACKGROUND_LAYER)
+  {
+    /* Enable the background CLUT loading */
+    SET_BIT(hdma2d->Instance->BGPFCCR, DMA2D_BGPFCCR_START);
+  }
+  else
+  {
+    /* Enable the foreground CLUT loading */
+    SET_BIT(hdma2d->Instance->FGPFCCR, DMA2D_FGPFCCR_START);
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Start DMA2D CLUT Loading.
+  * @param  hdma2d   Pointer to a DMA2D_HandleTypeDef structure that contains
+  *                   the configuration information for the DMA2D.
+  * @param  CLUTCfg  Pointer to a DMA2D_CLUTCfgTypeDef structure that contains
+  *                   the configuration information for the color look up table.
+  * @param  LayerIdx DMA2D Layer index.
+  *                   This parameter can be one of the following values:
+  *                   DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1)
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMA2D_CLUTStartLoad(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef *CLUTCfg, uint32_t LayerIdx)
+{
+  /* Check the parameters */
+  assert_param(IS_DMA2D_LAYER(LayerIdx));
+  assert_param(IS_DMA2D_CLUT_CM(CLUTCfg->CLUTColorMode));
+  assert_param(IS_DMA2D_CLUT_SIZE(CLUTCfg->Size));
+
+  /* Process locked */
+  __HAL_LOCK(hdma2d);
+
+  /* Change DMA2D peripheral state */
+  hdma2d->State = HAL_DMA2D_STATE_BUSY;
+
+  /* Configure the CLUT of the background DMA2D layer */
+  if (LayerIdx == DMA2D_BACKGROUND_LAYER)
+  {
+    /* Write background CLUT memory address */
+    WRITE_REG(hdma2d->Instance->BGCMAR, (uint32_t)CLUTCfg->pCLUT);
+
+    /* Write background CLUT size and CLUT color mode */
+    MODIFY_REG(hdma2d->Instance->BGPFCCR, (DMA2D_BGPFCCR_CS | DMA2D_BGPFCCR_CCM),
+               ((CLUTCfg->Size << DMA2D_BGPFCCR_CS_Pos) | (CLUTCfg->CLUTColorMode << DMA2D_BGPFCCR_CCM_Pos)));
+
+    /* Enable the CLUT loading for the background */
+    SET_BIT(hdma2d->Instance->BGPFCCR, DMA2D_BGPFCCR_START);
+  }
+  /* Configure the CLUT of the foreground DMA2D layer */
+  else
+  {
+    /* Write foreground CLUT memory address */
+    WRITE_REG(hdma2d->Instance->FGCMAR, (uint32_t)CLUTCfg->pCLUT);
+
+    /* Write foreground CLUT size and CLUT color mode */
+    MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM),
+               ((CLUTCfg->Size << DMA2D_FGPFCCR_CS_Pos) | (CLUTCfg->CLUTColorMode << DMA2D_FGPFCCR_CCM_Pos)));
+
+    /* Enable the CLUT loading for the foreground */
+    SET_BIT(hdma2d->Instance->FGPFCCR, DMA2D_FGPFCCR_START);
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Start DMA2D CLUT Loading with interrupt enabled.
+  * @param  hdma2d   Pointer to a DMA2D_HandleTypeDef structure that contains
+  *                   the configuration information for the DMA2D.
+  * @param  CLUTCfg  Pointer to a DMA2D_CLUTCfgTypeDef structure that contains
+  *                   the configuration information for the color look up table.
+  * @param  LayerIdx DMA2D Layer index.
+  *                   This parameter can be one of the following values:
+  *                   DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1)
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMA2D_CLUTStartLoad_IT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef *CLUTCfg,
+                                             uint32_t LayerIdx)
+{
+  /* Check the parameters */
+  assert_param(IS_DMA2D_LAYER(LayerIdx));
+  assert_param(IS_DMA2D_CLUT_CM(CLUTCfg->CLUTColorMode));
+  assert_param(IS_DMA2D_CLUT_SIZE(CLUTCfg->Size));
+
+  /* Process locked */
+  __HAL_LOCK(hdma2d);
+
+  /* Change DMA2D peripheral state */
+  hdma2d->State = HAL_DMA2D_STATE_BUSY;
+
+  /* Configure the CLUT of the background DMA2D layer */
+  if (LayerIdx == DMA2D_BACKGROUND_LAYER)
+  {
+    /* Write background CLUT memory address */
+    WRITE_REG(hdma2d->Instance->BGCMAR, (uint32_t)CLUTCfg->pCLUT);
+
+    /* Write background CLUT size and CLUT color mode */
+    MODIFY_REG(hdma2d->Instance->BGPFCCR, (DMA2D_BGPFCCR_CS | DMA2D_BGPFCCR_CCM),
+               ((CLUTCfg->Size << DMA2D_BGPFCCR_CS_Pos) | (CLUTCfg->CLUTColorMode << DMA2D_BGPFCCR_CCM_Pos)));
+
+    /* Enable the CLUT Transfer Complete, transfer Error, configuration Error and CLUT Access Error interrupts */
+    __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_CTC | DMA2D_IT_TE | DMA2D_IT_CE | DMA2D_IT_CAE);
+
+    /* Enable the CLUT loading for the background */
+    SET_BIT(hdma2d->Instance->BGPFCCR, DMA2D_BGPFCCR_START);
+  }
+  /* Configure the CLUT of the foreground DMA2D layer */
+  else
+  {
+    /* Write foreground CLUT memory address */
+    WRITE_REG(hdma2d->Instance->FGCMAR, (uint32_t)CLUTCfg->pCLUT);
+
+    /* Write foreground CLUT size and CLUT color mode */
+    MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM),
+               ((CLUTCfg->Size << DMA2D_FGPFCCR_CS_Pos) | (CLUTCfg->CLUTColorMode << DMA2D_FGPFCCR_CCM_Pos)));
+
+    /* Enable the CLUT Transfer Complete, transfer Error, configuration Error and CLUT Access Error interrupts */
+    __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_CTC | DMA2D_IT_TE | DMA2D_IT_CE | DMA2D_IT_CAE);
+
+    /* Enable the CLUT loading for the foreground */
+    SET_BIT(hdma2d->Instance->FGPFCCR, DMA2D_FGPFCCR_START);
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Start DMA2D CLUT Loading.
+  * @param  hdma2d   Pointer to a DMA2D_HandleTypeDef structure that contains
+  *                   the configuration information for the DMA2D.
+  * @param  CLUTCfg  Pointer to a DMA2D_CLUTCfgTypeDef structure that contains
+  *                   the configuration information for the color look up table.
+  * @param  LayerIdx DMA2D Layer index.
+  *                   This parameter can be one of the following values:
+  *                   DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1)
+  * @note API obsolete and maintained for compatibility with legacy. User is
+  *      invited to resort to HAL_DMA2D_CLUTStartLoad() instead to benefit from
+  *      code compactness, code size and improved heap usage.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMA2D_CLUTLoad(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx)
+{
+  /* Check the parameters */
+  assert_param(IS_DMA2D_LAYER(LayerIdx));
+  assert_param(IS_DMA2D_CLUT_CM(CLUTCfg.CLUTColorMode));
+  assert_param(IS_DMA2D_CLUT_SIZE(CLUTCfg.Size));
+
+  /* Process locked */
+  __HAL_LOCK(hdma2d);
+
+  /* Change DMA2D peripheral state */
+  hdma2d->State = HAL_DMA2D_STATE_BUSY;
+
+  /* Configure the CLUT of the background DMA2D layer */
+  if (LayerIdx == DMA2D_BACKGROUND_LAYER)
+  {
+    /* Write background CLUT memory address */
+    WRITE_REG(hdma2d->Instance->BGCMAR, (uint32_t)CLUTCfg.pCLUT);
+
+    /* Write background CLUT size and CLUT color mode */
+    MODIFY_REG(hdma2d->Instance->BGPFCCR, (DMA2D_BGPFCCR_CS | DMA2D_BGPFCCR_CCM),
+               ((CLUTCfg.Size << DMA2D_BGPFCCR_CS_Pos) | (CLUTCfg.CLUTColorMode << DMA2D_BGPFCCR_CCM_Pos)));
+
+    /* Enable the CLUT loading for the background */
+    SET_BIT(hdma2d->Instance->BGPFCCR, DMA2D_BGPFCCR_START);
+  }
+  /* Configure the CLUT of the foreground DMA2D layer */
+  else
+  {
+    /* Write foreground CLUT memory address */
+    WRITE_REG(hdma2d->Instance->FGCMAR, (uint32_t)CLUTCfg.pCLUT);
+
+    /* Write foreground CLUT size and CLUT color mode */
+    MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM),
+               ((CLUTCfg.Size << DMA2D_FGPFCCR_CS_Pos) | (CLUTCfg.CLUTColorMode << DMA2D_FGPFCCR_CCM_Pos)));
+
+    /* Enable the CLUT loading for the foreground */
+    SET_BIT(hdma2d->Instance->FGPFCCR, DMA2D_FGPFCCR_START);
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Start DMA2D CLUT Loading with interrupt enabled.
+  * @param  hdma2d   Pointer to a DMA2D_HandleTypeDef structure that contains
+  *                   the configuration information for the DMA2D.
+  * @param  CLUTCfg  Pointer to a DMA2D_CLUTCfgTypeDef structure that contains
+  *                   the configuration information for the color look up table.
+  * @param  LayerIdx DMA2D Layer index.
+  *                   This parameter can be one of the following values:
+  *                   DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1)
+  * @note API obsolete and maintained for compatibility with legacy. User is
+  *      invited to resort to HAL_DMA2D_CLUTStartLoad_IT() instead to benefit
+  *      from code compactness, code size and improved heap usage.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMA2D_CLUTLoad_IT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx)
+{
+  /* Check the parameters */
+  assert_param(IS_DMA2D_LAYER(LayerIdx));
+  assert_param(IS_DMA2D_CLUT_CM(CLUTCfg.CLUTColorMode));
+  assert_param(IS_DMA2D_CLUT_SIZE(CLUTCfg.Size));
+
+  /* Process locked */
+  __HAL_LOCK(hdma2d);
+
+  /* Change DMA2D peripheral state */
+  hdma2d->State = HAL_DMA2D_STATE_BUSY;
+
+  /* Configure the CLUT of the background DMA2D layer */
+  if (LayerIdx == DMA2D_BACKGROUND_LAYER)
+  {
+    /* Write background CLUT memory address */
+    WRITE_REG(hdma2d->Instance->BGCMAR, (uint32_t)CLUTCfg.pCLUT);
+
+    /* Write background CLUT size and CLUT color mode */
+    MODIFY_REG(hdma2d->Instance->BGPFCCR, (DMA2D_BGPFCCR_CS | DMA2D_BGPFCCR_CCM),
+               ((CLUTCfg.Size << DMA2D_BGPFCCR_CS_Pos) | (CLUTCfg.CLUTColorMode << DMA2D_BGPFCCR_CCM_Pos)));
+
+    /* Enable the CLUT Transfer Complete, transfer Error, configuration Error and CLUT Access Error interrupts */
+    __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_CTC | DMA2D_IT_TE | DMA2D_IT_CE | DMA2D_IT_CAE);
+
+    /* Enable the CLUT loading for the background */
+    SET_BIT(hdma2d->Instance->BGPFCCR, DMA2D_BGPFCCR_START);
+  }
+  /* Configure the CLUT of the foreground DMA2D layer */
+  else
+  {
+    /* Write foreground CLUT memory address */
+    WRITE_REG(hdma2d->Instance->FGCMAR, (uint32_t)CLUTCfg.pCLUT);
+
+    /* Write foreground CLUT size and CLUT color mode */
+    MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM),
+               ((CLUTCfg.Size << DMA2D_FGPFCCR_CS_Pos) | (CLUTCfg.CLUTColorMode << DMA2D_FGPFCCR_CCM_Pos)));
+
+    /* Enable the CLUT Transfer Complete, transfer Error, configuration Error and CLUT Access Error interrupts */
+    __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_CTC | DMA2D_IT_TE | DMA2D_IT_CE | DMA2D_IT_CAE);
+
+    /* Enable the CLUT loading for the foreground */
+    SET_BIT(hdma2d->Instance->FGPFCCR, DMA2D_FGPFCCR_START);
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Abort the DMA2D CLUT loading.
+  * @param  hdma2d  Pointer to a DMA2D_HandleTypeDef structure that contains
+  *                  the configuration information for the DMA2D.
+  * @param  LayerIdx DMA2D Layer index.
+  *                   This parameter can be one of the following values:
+  *                   DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1)
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Abort(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
+{
+  uint32_t tickstart;
+  const __IO uint32_t *reg =  &(hdma2d->Instance->BGPFCCR);  /* by default, point at background register */
+
+  /* Abort the CLUT loading */
+  SET_BIT(hdma2d->Instance->CR, DMA2D_CR_ABORT);
+
+  /* If foreground CLUT loading is considered, update local variables */
+  if (LayerIdx == DMA2D_FOREGROUND_LAYER)
+  {
+    reg  = &(hdma2d->Instance->FGPFCCR);
+  }
+
+
+  /* Get tick */
+  tickstart = HAL_GetTick();
+
+  /* Check if the CLUT loading is aborted */
+  while ((*reg & DMA2D_BGPFCCR_START) != 0U)
+  {
+    if ((HAL_GetTick() - tickstart) > DMA2D_TIMEOUT_ABORT)
+    {
+      /* Update error code */
+      hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;
+
+      /* Change the DMA2D state */
+      hdma2d->State = HAL_DMA2D_STATE_TIMEOUT;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hdma2d);
+
+      return HAL_TIMEOUT;
+    }
+  }
+
+  /* Disable the CLUT Transfer Complete, Transfer Error, Configuration Error and CLUT Access Error interrupts */
+  __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_CTC | DMA2D_IT_TE | DMA2D_IT_CE | DMA2D_IT_CAE);
+
+  /* Change the DMA2D state*/
+  hdma2d->State = HAL_DMA2D_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hdma2d);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Suspend the DMA2D CLUT loading.
+  * @param  hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains
+  *                 the configuration information for the DMA2D.
+  * @param  LayerIdx DMA2D Layer index.
+  *                   This parameter can be one of the following values:
+  *                   DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1)
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Suspend(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
+{
+  uint32_t tickstart;
+  uint32_t loadsuspended;
+  const __IO uint32_t *reg =  &(hdma2d->Instance->BGPFCCR);  /* by default, point at background register */
+
+  /* Suspend the CLUT loading */
+  SET_BIT(hdma2d->Instance->CR, DMA2D_CR_SUSP);
+
+  /* If foreground CLUT loading is considered, update local variables */
+  if (LayerIdx == DMA2D_FOREGROUND_LAYER)
+  {
+    reg  = &(hdma2d->Instance->FGPFCCR);
+  }
+
+  /* Get tick */
+  tickstart = HAL_GetTick();
+
+  /* Check if the CLUT loading is suspended */
+  /* 1st condition: Suspend Check */
+  loadsuspended = ((hdma2d->Instance->CR & DMA2D_CR_SUSP) == DMA2D_CR_SUSP) ? 1UL : 0UL;
+  /* 2nd condition: Not Start Check */
+  loadsuspended |= ((*reg & DMA2D_BGPFCCR_START) != DMA2D_BGPFCCR_START) ? 1UL : 0UL;
+  while (loadsuspended == 0UL)
+  {
+    if ((HAL_GetTick() - tickstart) > DMA2D_TIMEOUT_SUSPEND)
+    {
+      /* Update error code */
+      hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;
+
+      /* Change the DMA2D state */
+      hdma2d->State = HAL_DMA2D_STATE_TIMEOUT;
+
+      return HAL_TIMEOUT;
+    }
+    /* 1st condition: Suspend Check */
+    loadsuspended = ((hdma2d->Instance->CR & DMA2D_CR_SUSP) == DMA2D_CR_SUSP) ? 1UL : 0UL;
+    /* 2nd condition: Not Start Check */
+    loadsuspended |= ((*reg & DMA2D_BGPFCCR_START) != DMA2D_BGPFCCR_START) ? 1UL : 0UL;
+  }
+
+  /* Check whether or not a transfer is actually suspended and change the DMA2D state accordingly */
+  if ((*reg & DMA2D_BGPFCCR_START) != 0U)
+  {
+    hdma2d->State = HAL_DMA2D_STATE_SUSPEND;
+  }
+  else
+  {
+    /* Make sure SUSP bit is cleared since it is meaningless
+       when no transfer is on-going */
+    CLEAR_BIT(hdma2d->Instance->CR, DMA2D_CR_SUSP);
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Resume the DMA2D CLUT loading.
+  * @param  hdma2d pointer to a DMA2D_HandleTypeDef structure that contains
+  *                 the configuration information for the DMA2D.
+  * @param  LayerIdx DMA2D Layer index.
+  *                   This parameter can be one of the following values:
+  *                   DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1)
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Resume(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
+{
+  /* Check the SUSP and START bits for background or foreground CLUT loading */
+  if (LayerIdx == DMA2D_BACKGROUND_LAYER)
+  {
+    /* Background CLUT loading suspension check */
+    if ((hdma2d->Instance->CR & DMA2D_CR_SUSP) == DMA2D_CR_SUSP)
+    {
+      if ((hdma2d->Instance->BGPFCCR & DMA2D_BGPFCCR_START) == DMA2D_BGPFCCR_START)
+      {
+        /* Ongoing CLUT loading is suspended: change the DMA2D state before resuming */
+        hdma2d->State = HAL_DMA2D_STATE_BUSY;
+      }
+    }
+  }
+  else
+  {
+    /* Foreground CLUT loading suspension check */
+    if ((hdma2d->Instance->CR & DMA2D_CR_SUSP) == DMA2D_CR_SUSP)
+    {
+      if ((hdma2d->Instance->FGPFCCR & DMA2D_FGPFCCR_START) == DMA2D_FGPFCCR_START)
+      {
+        /* Ongoing CLUT loading is suspended: change the DMA2D state before resuming */
+        hdma2d->State = HAL_DMA2D_STATE_BUSY;
+      }
+    }
+  }
+
+  /* Resume the CLUT loading */
+  CLEAR_BIT(hdma2d->Instance->CR, DMA2D_CR_SUSP);
+
+  return HAL_OK;
+}
+
+
+/**
+
+  * @brief  Polling for transfer complete or CLUT loading.
+  * @param  hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains
+  *                 the configuration information for the DMA2D.
+  * @param  Timeout Timeout duration
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMA2D_PollForTransfer(DMA2D_HandleTypeDef *hdma2d, uint32_t Timeout)
+{
+  uint32_t tickstart;
+  uint32_t layer_start;
+  __IO uint32_t isrflags = 0x0U;
+
+  /* Polling for DMA2D transfer */
+  if ((hdma2d->Instance->CR & DMA2D_CR_START) != 0U)
+  {
+    /* Get tick */
+    tickstart = HAL_GetTick();
+
+    while (__HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_TC) == 0U)
+    {
+      isrflags = READ_REG(hdma2d->Instance->ISR);
+      if ((isrflags & (DMA2D_FLAG_CE | DMA2D_FLAG_TE)) != 0U)
+      {
+        if ((isrflags & DMA2D_FLAG_CE) != 0U)
+        {
+          hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CE;
+        }
+        if ((isrflags & DMA2D_FLAG_TE) != 0U)
+        {
+          hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TE;
+        }
+        /* Clear the transfer and configuration error flags */
+        __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CE | DMA2D_FLAG_TE);
+
+        /* Change DMA2D state */
+        hdma2d->State = HAL_DMA2D_STATE_ERROR;
+
+        /* Process unlocked */
+        __HAL_UNLOCK(hdma2d);
+
+        return HAL_ERROR;
+      }
+      /* Check for the Timeout */
+      if (Timeout != HAL_MAX_DELAY)
+      {
+        if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
+        {
+          /* Update error code */
+          hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;
+
+          /* Change the DMA2D state */
+          hdma2d->State = HAL_DMA2D_STATE_TIMEOUT;
+
+          /* Process unlocked */
+          __HAL_UNLOCK(hdma2d);
+
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+  }
+  /* Polling for CLUT loading (foreground or background) */
+  layer_start = hdma2d->Instance->FGPFCCR & DMA2D_FGPFCCR_START;
+  layer_start |= hdma2d->Instance->BGPFCCR & DMA2D_BGPFCCR_START;
+  if (layer_start != 0U)
+  {
+    /* Get tick */
+    tickstart = HAL_GetTick();
+
+    while (__HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_CTC) == 0U)
+    {
+      isrflags = READ_REG(hdma2d->Instance->ISR);
+      if ((isrflags & (DMA2D_FLAG_CAE | DMA2D_FLAG_CE | DMA2D_FLAG_TE)) != 0U)
+      {
+        if ((isrflags & DMA2D_FLAG_CAE) != 0U)
+        {
+          hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CAE;
+        }
+        if ((isrflags & DMA2D_FLAG_CE) != 0U)
+        {
+          hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CE;
+        }
+        if ((isrflags & DMA2D_FLAG_TE) != 0U)
+        {
+          hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TE;
+        }
+        /* Clear the CLUT Access Error, Configuration Error and Transfer Error flags */
+        __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CAE | DMA2D_FLAG_CE | DMA2D_FLAG_TE);
+
+        /* Change DMA2D state */
+        hdma2d->State = HAL_DMA2D_STATE_ERROR;
+
+        /* Process unlocked */
+        __HAL_UNLOCK(hdma2d);
+
+        return HAL_ERROR;
+      }
+      /* Check for the Timeout */
+      if (Timeout != HAL_MAX_DELAY)
+      {
+        if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
+        {
+          /* Update error code */
+          hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;
+
+          /* Change the DMA2D state */
+          hdma2d->State = HAL_DMA2D_STATE_TIMEOUT;
+
+          /* Process unlocked */
+          __HAL_UNLOCK(hdma2d);
+
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+  }
+
+  /* Clear the transfer complete and CLUT loading flags */
+  __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TC | DMA2D_FLAG_CTC);
+
+  /* Change DMA2D state */
+  hdma2d->State = HAL_DMA2D_STATE_READY;
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hdma2d);
+
+  return HAL_OK;
+}
+/**
+  * @brief  Handle DMA2D interrupt request.
+  * @param  hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains
+  *                 the configuration information for the DMA2D.
+  * @retval HAL status
+  */
+void HAL_DMA2D_IRQHandler(DMA2D_HandleTypeDef *hdma2d)
+{
+  uint32_t isrflags = READ_REG(hdma2d->Instance->ISR);
+  uint32_t crflags = READ_REG(hdma2d->Instance->CR);
+
+  /* Transfer Error Interrupt management ***************************************/
+  if ((isrflags & DMA2D_FLAG_TE) != 0U)
+  {
+    if ((crflags & DMA2D_IT_TE) != 0U)
+    {
+      /* Disable the transfer Error interrupt */
+      __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TE);
+
+      /* Update error code */
+      hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TE;
+
+      /* Clear the transfer error flag */
+      __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TE);
+
+      /* Change DMA2D state */
+      hdma2d->State = HAL_DMA2D_STATE_ERROR;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hdma2d);
+
+      if (hdma2d->XferErrorCallback != NULL)
+      {
+        /* Transfer error Callback */
+        hdma2d->XferErrorCallback(hdma2d);
+      }
+    }
+  }
+  /* Configuration Error Interrupt management **********************************/
+  if ((isrflags & DMA2D_FLAG_CE) != 0U)
+  {
+    if ((crflags & DMA2D_IT_CE) != 0U)
+    {
+      /* Disable the Configuration Error interrupt */
+      __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_CE);
+
+      /* Clear the Configuration error flag */
+      __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CE);
+
+      /* Update error code */
+      hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CE;
+
+      /* Change DMA2D state */
+      hdma2d->State = HAL_DMA2D_STATE_ERROR;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hdma2d);
+
+      if (hdma2d->XferErrorCallback != NULL)
+      {
+        /* Transfer error Callback */
+        hdma2d->XferErrorCallback(hdma2d);
+      }
+    }
+  }
+  /* CLUT access Error Interrupt management ***********************************/
+  if ((isrflags & DMA2D_FLAG_CAE) != 0U)
+  {
+    if ((crflags & DMA2D_IT_CAE) != 0U)
+    {
+      /* Disable the CLUT access error interrupt */
+      __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_CAE);
+
+      /* Clear the CLUT access error flag */
+      __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CAE);
+
+      /* Update error code */
+      hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CAE;
+
+      /* Change DMA2D state */
+      hdma2d->State = HAL_DMA2D_STATE_ERROR;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hdma2d);
+
+      if (hdma2d->XferErrorCallback != NULL)
+      {
+        /* Transfer error Callback */
+        hdma2d->XferErrorCallback(hdma2d);
+      }
+    }
+  }
+  /* Transfer watermark Interrupt management **********************************/
+  if ((isrflags & DMA2D_FLAG_TW) != 0U)
+  {
+    if ((crflags & DMA2D_IT_TW) != 0U)
+    {
+      /* Disable the transfer watermark interrupt */
+      __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TW);
+
+      /* Clear the transfer watermark flag */
+      __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TW);
+
+      /* Transfer watermark Callback */
+#if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
+      hdma2d->LineEventCallback(hdma2d);
+#else
+      HAL_DMA2D_LineEventCallback(hdma2d);
+#endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */
+
+    }
+  }
+  /* Transfer Complete Interrupt management ************************************/
+  if ((isrflags & DMA2D_FLAG_TC) != 0U)
+  {
+    if ((crflags & DMA2D_IT_TC) != 0U)
+    {
+      /* Disable the transfer complete interrupt */
+      __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TC);
+
+      /* Clear the transfer complete flag */
+      __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TC);
+
+      /* Update error code */
+      hdma2d->ErrorCode |= HAL_DMA2D_ERROR_NONE;
+
+      /* Change DMA2D state */
+      hdma2d->State = HAL_DMA2D_STATE_READY;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hdma2d);
+
+      if (hdma2d->XferCpltCallback != NULL)
+      {
+        /* Transfer complete Callback */
+        hdma2d->XferCpltCallback(hdma2d);
+      }
+    }
+  }
+  /* CLUT Transfer Complete Interrupt management ******************************/
+  if ((isrflags & DMA2D_FLAG_CTC) != 0U)
+  {
+    if ((crflags & DMA2D_IT_CTC) != 0U)
+    {
+      /* Disable the CLUT transfer complete interrupt */
+      __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_CTC);
+
+      /* Clear the CLUT transfer complete flag */
+      __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CTC);
+
+      /* Update error code */
+      hdma2d->ErrorCode |= HAL_DMA2D_ERROR_NONE;
+
+      /* Change DMA2D state */
+      hdma2d->State = HAL_DMA2D_STATE_READY;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hdma2d);
+
+      /* CLUT Transfer complete Callback */
+#if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
+      hdma2d->CLUTLoadingCpltCallback(hdma2d);
+#else
+      HAL_DMA2D_CLUTLoadingCpltCallback(hdma2d);
+#endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */
+    }
+  }
+
+}
+
+/**
+  * @brief  Transfer watermark callback.
+  * @param  hdma2d pointer to a DMA2D_HandleTypeDef structure that contains
+  *                 the configuration information for the DMA2D.
+  * @retval None
+  */
+__weak void HAL_DMA2D_LineEventCallback(DMA2D_HandleTypeDef *hdma2d)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hdma2d);
+
+  /* NOTE : This function should not be modified; when the callback is needed,
+            the HAL_DMA2D_LineEventCallback can be implemented in the user file.
+   */
+}
+
+/**
+  * @brief  CLUT Transfer Complete callback.
+  * @param  hdma2d pointer to a DMA2D_HandleTypeDef structure that contains
+  *                 the configuration information for the DMA2D.
+  * @retval None
+  */
+__weak void HAL_DMA2D_CLUTLoadingCpltCallback(DMA2D_HandleTypeDef *hdma2d)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hdma2d);
+
+  /* NOTE : This function should not be modified; when the callback is needed,
+            the HAL_DMA2D_CLUTLoadingCpltCallback can be implemented in the user file.
+   */
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup DMA2D_Exported_Functions_Group3 Peripheral Control functions
+  *  @brief    Peripheral Control functions
+  *
+@verbatim
+ ===============================================================================
+                    ##### Peripheral Control functions #####
+ ===============================================================================
+    [..]  This section provides functions allowing to:
+      (+) Configure the DMA2D foreground or background layer parameters.
+      (+) Configure the DMA2D CLUT transfer.
+      (+) Configure the line watermark
+      (+) Configure the dead time value.
+      (+) Enable or disable the dead time value functionality.
+
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Configure the DMA2D Layer according to the specified
+  *         parameters in the DMA2D_HandleTypeDef.
+  * @param  hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains
+  *                 the configuration information for the DMA2D.
+  * @param  LayerIdx DMA2D Layer index.
+  *                   This parameter can be one of the following values:
+  *                   DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1)
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMA2D_ConfigLayer(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
+{
+  DMA2D_LayerCfgTypeDef *pLayerCfg;
+  uint32_t regMask;
+  uint32_t regValue;
+
+  /* Check the parameters */
+  assert_param(IS_DMA2D_LAYER(LayerIdx));
+  assert_param(IS_DMA2D_OFFSET(hdma2d->LayerCfg[LayerIdx].InputOffset));
+  if (hdma2d->Init.Mode != DMA2D_R2M)
+  {
+    assert_param(IS_DMA2D_INPUT_COLOR_MODE(hdma2d->LayerCfg[LayerIdx].InputColorMode));
+    if (hdma2d->Init.Mode != DMA2D_M2M)
+    {
+      assert_param(IS_DMA2D_ALPHA_MODE(hdma2d->LayerCfg[LayerIdx].AlphaMode));
+    }
+  }
+
+  /* Process locked */
+  __HAL_LOCK(hdma2d);
+
+  /* Change DMA2D peripheral state */
+  hdma2d->State = HAL_DMA2D_STATE_BUSY;
+
+  pLayerCfg = &hdma2d->LayerCfg[LayerIdx];
+
+  /* Prepare the value to be written to the BGPFCCR or FGPFCCR register */
+  regValue = pLayerCfg->InputColorMode | (pLayerCfg->AlphaMode << DMA2D_BGPFCCR_AM_Pos);
+  regMask  = DMA2D_BGPFCCR_CM | DMA2D_BGPFCCR_AM | DMA2D_BGPFCCR_ALPHA;
+
+
+  if ((pLayerCfg->InputColorMode == DMA2D_INPUT_A4) || (pLayerCfg->InputColorMode == DMA2D_INPUT_A8))
+  {
+    regValue |= (pLayerCfg->InputAlpha & DMA2D_BGPFCCR_ALPHA);
+  }
+  else
+  {
+    regValue |= (pLayerCfg->InputAlpha << DMA2D_BGPFCCR_ALPHA_Pos);
+  }
+
+  /* Configure the background DMA2D layer */
+  if (LayerIdx == DMA2D_BACKGROUND_LAYER)
+  {
+    /* Write DMA2D BGPFCCR register */
+    MODIFY_REG(hdma2d->Instance->BGPFCCR, regMask, regValue);
+
+    /* DMA2D BGOR register configuration -------------------------------------*/
+    WRITE_REG(hdma2d->Instance->BGOR, pLayerCfg->InputOffset);
+
+    /* DMA2D BGCOLR register configuration -------------------------------------*/
+    if ((pLayerCfg->InputColorMode == DMA2D_INPUT_A4) || (pLayerCfg->InputColorMode == DMA2D_INPUT_A8))
+    {
+      WRITE_REG(hdma2d->Instance->BGCOLR, pLayerCfg->InputAlpha & (DMA2D_BGCOLR_BLUE | DMA2D_BGCOLR_GREEN | \
+                                                                   DMA2D_BGCOLR_RED));
+    }
+  }
+  /* Configure the foreground DMA2D layer */
+  else
+  {
+
+
+    /* Write DMA2D FGPFCCR register */
+    MODIFY_REG(hdma2d->Instance->FGPFCCR, regMask, regValue);
+
+    /* DMA2D FGOR register configuration -------------------------------------*/
+    WRITE_REG(hdma2d->Instance->FGOR, pLayerCfg->InputOffset);
+
+    /* DMA2D FGCOLR register configuration -------------------------------------*/
+    if ((pLayerCfg->InputColorMode == DMA2D_INPUT_A4) || (pLayerCfg->InputColorMode == DMA2D_INPUT_A8))
+    {
+      WRITE_REG(hdma2d->Instance->FGCOLR, pLayerCfg->InputAlpha & (DMA2D_FGCOLR_BLUE | DMA2D_FGCOLR_GREEN | \
+                                                                   DMA2D_FGCOLR_RED));
+    }
+  }
+  /* Initialize the DMA2D state*/
+  hdma2d->State = HAL_DMA2D_STATE_READY;
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hdma2d);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Configure the DMA2D CLUT Transfer.
+  * @param  hdma2d   Pointer to a DMA2D_HandleTypeDef structure that contains
+  *                   the configuration information for the DMA2D.
+  * @param  CLUTCfg  Pointer to a DMA2D_CLUTCfgTypeDef structure that contains
+  *                   the configuration information for the color look up table.
+  * @param  LayerIdx DMA2D Layer index.
+  *                   This parameter can be one of the following values:
+  *                   DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1)
+  * @note API obsolete and maintained for compatibility with legacy. User is invited
+  *      to resort to HAL_DMA2D_CLUTStartLoad() instead to benefit from code compactness,
+  *      code size and improved heap usage.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMA2D_ConfigCLUT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx)
+{
+  /* Check the parameters */
+  assert_param(IS_DMA2D_LAYER(LayerIdx));
+  assert_param(IS_DMA2D_CLUT_CM(CLUTCfg.CLUTColorMode));
+  assert_param(IS_DMA2D_CLUT_SIZE(CLUTCfg.Size));
+
+  /* Process locked */
+  __HAL_LOCK(hdma2d);
+
+  /* Change DMA2D peripheral state */
+  hdma2d->State = HAL_DMA2D_STATE_BUSY;
+
+  /* Configure the CLUT of the background DMA2D layer */
+  if (LayerIdx == DMA2D_BACKGROUND_LAYER)
+  {
+    /* Write background CLUT memory address */
+    WRITE_REG(hdma2d->Instance->BGCMAR, (uint32_t)CLUTCfg.pCLUT);
+
+    /* Write background CLUT size and CLUT color mode */
+    MODIFY_REG(hdma2d->Instance->BGPFCCR, (DMA2D_BGPFCCR_CS | DMA2D_BGPFCCR_CCM),
+               ((CLUTCfg.Size << DMA2D_BGPFCCR_CS_Pos) | (CLUTCfg.CLUTColorMode << DMA2D_BGPFCCR_CCM_Pos)));
+  }
+  /* Configure the CLUT of the foreground DMA2D layer */
+  else
+  {
+    /* Write foreground CLUT memory address */
+    WRITE_REG(hdma2d->Instance->FGCMAR, (uint32_t)CLUTCfg.pCLUT);
+
+    /* Write foreground CLUT size and CLUT color mode */
+    MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM),
+               ((CLUTCfg.Size << DMA2D_FGPFCCR_CS_Pos) | (CLUTCfg.CLUTColorMode << DMA2D_FGPFCCR_CCM_Pos)));
+  }
+
+  /* Set the DMA2D state to Ready*/
+  hdma2d->State = HAL_DMA2D_STATE_READY;
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hdma2d);
+
+  return HAL_OK;
+}
+
+
+/**
+  * @brief  Configure the line watermark.
+  * @param  hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains
+  *                 the configuration information for the DMA2D.
+  * @param  Line   Line Watermark configuration (maximum 16-bit long value expected).
+  * @note   HAL_DMA2D_ProgramLineEvent() API enables the transfer watermark interrupt.
+  * @note   The transfer watermark interrupt is disabled once it has occurred.
+  * @retval HAL status
+  */
+
+HAL_StatusTypeDef HAL_DMA2D_ProgramLineEvent(DMA2D_HandleTypeDef *hdma2d, uint32_t Line)
+{
+  /* Check the parameters */
+  if (Line > DMA2D_LWR_LW)
+  {
+    return HAL_ERROR;
+  }
+  else
+  {
+    /* Process locked */
+    __HAL_LOCK(hdma2d);
+
+    /* Change DMA2D peripheral state */
+    hdma2d->State = HAL_DMA2D_STATE_BUSY;
+
+    /* Sets the Line watermark configuration */
+    WRITE_REG(hdma2d->Instance->LWR, Line);
+
+    /* Enable the Line interrupt */
+    __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_TW);
+
+    /* Initialize the DMA2D state*/
+    hdma2d->State = HAL_DMA2D_STATE_READY;
+
+    /* Process unlocked */
+    __HAL_UNLOCK(hdma2d);
+
+    return HAL_OK;
+  }
+}
+
+/**
+  * @brief Enable DMA2D dead time feature.
+  * @param hdma2d DMA2D handle.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMA2D_EnableDeadTime(DMA2D_HandleTypeDef *hdma2d)
+{
+  /* Process Locked */
+  __HAL_LOCK(hdma2d);
+
+  hdma2d->State = HAL_DMA2D_STATE_BUSY;
+
+  /* Set DMA2D_AMTCR EN bit */
+  SET_BIT(hdma2d->Instance->AMTCR, DMA2D_AMTCR_EN);
+
+  hdma2d->State = HAL_DMA2D_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hdma2d);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief Disable DMA2D dead time feature.
+  * @param hdma2d DMA2D handle.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMA2D_DisableDeadTime(DMA2D_HandleTypeDef *hdma2d)
+{
+  /* Process Locked */
+  __HAL_LOCK(hdma2d);
+
+  hdma2d->State = HAL_DMA2D_STATE_BUSY;
+
+  /* Clear DMA2D_AMTCR EN bit */
+  CLEAR_BIT(hdma2d->Instance->AMTCR, DMA2D_AMTCR_EN);
+
+  hdma2d->State = HAL_DMA2D_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hdma2d);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief Configure dead time.
+  * @note The dead time value represents the guaranteed minimum number of cycles between
+  *       two consecutive transactions on the AHB bus.
+  * @param hdma2d DMA2D handle.
+  * @param DeadTime dead time value.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMA2D_ConfigDeadTime(DMA2D_HandleTypeDef *hdma2d, uint8_t DeadTime)
+{
+  /* Process Locked */
+  __HAL_LOCK(hdma2d);
+
+  hdma2d->State = HAL_DMA2D_STATE_BUSY;
+
+  /* Set DMA2D_AMTCR DT field */
+  MODIFY_REG(hdma2d->Instance->AMTCR, DMA2D_AMTCR_DT, (((uint32_t) DeadTime) << DMA2D_AMTCR_DT_Pos));
+
+  hdma2d->State = HAL_DMA2D_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hdma2d);
+
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+
+/** @defgroup DMA2D_Exported_Functions_Group4 Peripheral State and Error functions
+  *  @brief    Peripheral State functions
+  *
+@verbatim
+ ===============================================================================
+                  ##### Peripheral State and Errors functions #####
+ ===============================================================================
+    [..]
+    This subsection provides functions allowing to:
+      (+) Get the DMA2D state
+      (+) Get the DMA2D error code
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Return the DMA2D state
+  * @param  hdma2d pointer to a DMA2D_HandleTypeDef structure that contains
+  *                 the configuration information for the DMA2D.
+  * @retval HAL state
+  */
+HAL_DMA2D_StateTypeDef HAL_DMA2D_GetState(DMA2D_HandleTypeDef *hdma2d)
+{
+  return hdma2d->State;
+}
+
+/**
+  * @brief  Return the DMA2D error code
+  * @param  hdma2d  pointer to a DMA2D_HandleTypeDef structure that contains
+  *               the configuration information for DMA2D.
+  * @retval DMA2D Error Code
+  */
+uint32_t HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d)
+{
+  return hdma2d->ErrorCode;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+
+/** @defgroup DMA2D_Private_Functions DMA2D Private Functions
+  * @{
+  */
+
+/**
+  * @brief  Set the DMA2D transfer parameters.
+  * @param  hdma2d     Pointer to a DMA2D_HandleTypeDef structure that contains
+  *                     the configuration information for the specified DMA2D.
+  * @param  pdata      The source memory Buffer address
+  * @param  DstAddress The destination memory Buffer address
+  * @param  Width      The width of data to be transferred from source to destination.
+  * @param  Height     The height of data to be transferred from source to destination.
+  * @retval HAL status
+  */
+static void DMA2D_SetConfig(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width,
+                            uint32_t Height)
+{
+  uint32_t tmp;
+  uint32_t tmp1;
+  uint32_t tmp2;
+  uint32_t tmp3;
+  uint32_t tmp4;
+
+  /* Configure DMA2D data size */
+  MODIFY_REG(hdma2d->Instance->NLR, (DMA2D_NLR_NL | DMA2D_NLR_PL), (Height | (Width << DMA2D_NLR_PL_Pos)));
+
+  /* Configure DMA2D destination address */
+  WRITE_REG(hdma2d->Instance->OMAR, DstAddress);
+
+  /* Register to memory DMA2D mode selected */
+  if (hdma2d->Init.Mode == DMA2D_R2M)
+  {
+    tmp1 = pdata & DMA2D_OCOLR_ALPHA_1;
+    tmp2 = pdata & DMA2D_OCOLR_RED_1;
+    tmp3 = pdata & DMA2D_OCOLR_GREEN_1;
+    tmp4 = pdata & DMA2D_OCOLR_BLUE_1;
+
+    /* Prepare the value to be written to the OCOLR register according to the color mode */
+    if (hdma2d->Init.ColorMode == DMA2D_OUTPUT_ARGB8888)
+    {
+      tmp = (tmp3 | tmp2 | tmp1 | tmp4);
+    }
+    else if (hdma2d->Init.ColorMode == DMA2D_OUTPUT_RGB888)
+    {
+      tmp = (tmp3 | tmp2 | tmp4);
+    }
+    else if (hdma2d->Init.ColorMode == DMA2D_OUTPUT_RGB565)
+    {
+      tmp2 = (tmp2 >> 19U);
+      tmp3 = (tmp3 >> 10U);
+      tmp4 = (tmp4 >> 3U);
+      tmp  = ((tmp3 << 5U) | (tmp2 << 11U) | tmp4);
+    }
+    else if (hdma2d->Init.ColorMode == DMA2D_OUTPUT_ARGB1555)
+    {
+      tmp1 = (tmp1 >> 31U);
+      tmp2 = (tmp2 >> 19U);
+      tmp3 = (tmp3 >> 11U);
+      tmp4 = (tmp4 >> 3U);
+      tmp  = ((tmp3 << 5U) | (tmp2 << 10U) | (tmp1 << 15U) | tmp4);
+    }
+    else /* Dhdma2d->Init.ColorMode = DMA2D_OUTPUT_ARGB4444 */
+    {
+      tmp1 = (tmp1 >> 28U);
+      tmp2 = (tmp2 >> 20U);
+      tmp3 = (tmp3 >> 12U);
+      tmp4 = (tmp4 >> 4U);
+      tmp  = ((tmp3 << 4U) | (tmp2 << 8U) | (tmp1 << 12U) | tmp4);
+    }
+    /* Write to DMA2D OCOLR register */
+    WRITE_REG(hdma2d->Instance->OCOLR, tmp);
+  }
+  else /* M2M, M2M_PFC or M2M_Blending DMA2D Mode */
+  {
+    /* Configure DMA2D source address */
+    WRITE_REG(hdma2d->Instance->FGMAR, pdata);
+  }
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+#endif /* DMA2D */
+#endif /* HAL_DMA2D_MODULE_ENABLED */
diff --git a/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c
new file mode 100644
index 0000000..d38cfcd
--- /dev/null
+++ b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c
@@ -0,0 +1,313 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hal_dma_ex.c
+  * @author  MCD Application Team
+  * @brief   DMA Extension HAL module driver
+  *         This file provides firmware functions to manage the following 
+  *         functionalities of the DMA Extension peripheral:
+  *           + Extended features functions
+  *
+  @verbatim
+  ==============================================================================
+                        ##### How to use this driver #####
+  ==============================================================================
+  [..]
+  The DMA Extension HAL driver can be used as follows:
+   (#) Start a multi buffer transfer using the HAL_DMA_MultiBufferStart() function
+       for polling mode or HAL_DMA_MultiBufferStart_IT() for interrupt mode.
+                   
+     -@-  In Memory-to-Memory transfer mode, Multi (Double) Buffer mode is not allowed.
+     -@-  When Multi (Double) Buffer mode is enabled the, transfer is circular by default.
+     -@-  In Multi (Double) buffer mode, it is possible to update the base address for 
+          the AHB memory port on the fly (DMA_SxM0AR or DMA_SxM1AR) when the stream is enabled. 
+  
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file in
+  * the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup DMAEx DMAEx
+  * @brief DMA Extended HAL module driver
+  * @{
+  */
+
+#ifdef HAL_DMA_MODULE_ENABLED
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private Constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+/** @addtogroup DMAEx_Private_Functions
+  * @{
+  */
+static void DMA_MultiBufferSetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
+/**
+  * @}
+  */
+
+/* Exported functions ---------------------------------------------------------*/
+
+/** @addtogroup DMAEx_Exported_Functions
+  * @{
+  */
+
+
+/** @addtogroup DMAEx_Exported_Functions_Group1
+  *
+@verbatim   
+ ===============================================================================
+                #####  Extended features functions  #####
+ ===============================================================================  
+    [..]  This section provides functions allowing to:
+      (+) Configure the source, destination address and data length and 
+          Start MultiBuffer DMA transfer
+      (+) Configure the source, destination address and data length and 
+          Start MultiBuffer DMA transfer with interrupt
+      (+) Change on the fly the memory0 or memory1 address.
+      
+@endverbatim
+  * @{
+  */
+
+
+/**
+  * @brief  Starts the multi_buffer DMA Transfer.
+  * @param  hdma       pointer to a DMA_HandleTypeDef structure that contains
+  *                     the configuration information for the specified DMA Stream.  
+  * @param  SrcAddress The source memory Buffer address
+  * @param  DstAddress The destination memory Buffer address
+  * @param  SecondMemAddress The second memory Buffer address in case of multi buffer Transfer  
+  * @param  DataLength The length of data to be transferred from source to destination
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  
+  /* Check the parameters */
+  assert_param(IS_DMA_BUFFER_SIZE(DataLength));
+  
+  /* Memory-to-memory transfer not supported in double buffering mode */
+  if (hdma->Init.Direction == DMA_MEMORY_TO_MEMORY)
+  {
+    hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED;
+    status = HAL_ERROR;
+  }
+  else
+  {
+    /* Process Locked */
+    __HAL_LOCK(hdma);
+    
+    if(HAL_DMA_STATE_READY == hdma->State)
+    {
+      /* Change DMA peripheral state */
+      hdma->State = HAL_DMA_STATE_BUSY; 
+      
+      /* Enable the double buffer mode */
+      hdma->Instance->CR |= (uint32_t)DMA_SxCR_DBM;
+      
+      /* Configure DMA Stream destination address */
+      hdma->Instance->M1AR = SecondMemAddress;
+      
+      /* Configure the source, destination address and the data length */
+      DMA_MultiBufferSetConfig(hdma, SrcAddress, DstAddress, DataLength);
+      
+      /* Enable the peripheral */
+      __HAL_DMA_ENABLE(hdma);
+    }
+    else
+    {
+      /* Return error status */
+      status = HAL_BUSY;
+    }
+  }
+  return status;
+}
+
+/**
+  * @brief  Starts the multi_buffer DMA Transfer with interrupt enabled.
+  * @param  hdma       pointer to a DMA_HandleTypeDef structure that contains
+  *                     the configuration information for the specified DMA Stream.  
+  * @param  SrcAddress The source memory Buffer address
+  * @param  DstAddress The destination memory Buffer address
+  * @param  SecondMemAddress The second memory Buffer address in case of multi buffer Transfer  
+  * @param  DataLength The length of data to be transferred from source to destination
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  
+  /* Check the parameters */
+  assert_param(IS_DMA_BUFFER_SIZE(DataLength));
+  
+  /* Memory-to-memory transfer not supported in double buffering mode */
+  if (hdma->Init.Direction == DMA_MEMORY_TO_MEMORY)
+  {
+    hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED;
+    return HAL_ERROR;
+  }
+  
+  /* Check callback functions */
+  if ((NULL == hdma->XferCpltCallback) || (NULL == hdma->XferM1CpltCallback) || (NULL == hdma->XferErrorCallback))
+  {
+    hdma->ErrorCode = HAL_DMA_ERROR_PARAM;
+    return HAL_ERROR;
+  }
+  
+  /* Process locked */
+  __HAL_LOCK(hdma);
+  
+  if(HAL_DMA_STATE_READY == hdma->State)
+  {
+    /* Change DMA peripheral state */
+    hdma->State = HAL_DMA_STATE_BUSY;
+    
+    /* Initialize the error code */
+    hdma->ErrorCode = HAL_DMA_ERROR_NONE;
+    
+    /* Enable the Double buffer mode */
+    hdma->Instance->CR |= (uint32_t)DMA_SxCR_DBM;
+    
+    /* Configure DMA Stream destination address */
+    hdma->Instance->M1AR = SecondMemAddress;
+    
+    /* Configure the source, destination address and the data length */
+    DMA_MultiBufferSetConfig(hdma, SrcAddress, DstAddress, DataLength); 
+    
+    /* Clear all flags */
+    __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma));
+    __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
+    __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma));
+    __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma));
+    __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma));
+
+    /* Enable Common interrupts*/
+    hdma->Instance->CR  |= DMA_IT_TC | DMA_IT_TE | DMA_IT_DME;
+    hdma->Instance->FCR |= DMA_IT_FE;
+    
+    if((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL))
+    {
+      hdma->Instance->CR  |= DMA_IT_HT;
+    }
+    
+    /* Enable the peripheral */
+    __HAL_DMA_ENABLE(hdma); 
+  }
+  else
+  {     
+    /* Process unlocked */
+    __HAL_UNLOCK(hdma);	  
+    
+    /* Return error status */
+    status = HAL_BUSY;
+  }  
+  return status; 
+}
+
+/**
+  * @brief  Change the memory0 or memory1 address on the fly.
+  * @param  hdma       pointer to a DMA_HandleTypeDef structure that contains
+  *                     the configuration information for the specified DMA Stream.  
+  * @param  Address    The new address
+  * @param  memory     the memory to be changed, This parameter can be one of 
+  *                     the following values:
+  *                      MEMORY0 /
+  *                      MEMORY1
+  * @note   The MEMORY0 address can be changed only when the current transfer use
+  *         MEMORY1 and the MEMORY1 address can be changed only when the current 
+  *         transfer use MEMORY0.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMAEx_ChangeMemory(DMA_HandleTypeDef *hdma, uint32_t Address, HAL_DMA_MemoryTypeDef memory)
+{
+  if(memory == MEMORY0)
+  {
+    /* change the memory0 address */
+    hdma->Instance->M0AR = Address;
+  }
+  else
+  {
+    /* change the memory1 address */
+    hdma->Instance->M1AR = Address;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup DMAEx_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Set the DMA Transfer parameter.
+  * @param  hdma       pointer to a DMA_HandleTypeDef structure that contains
+  *                     the configuration information for the specified DMA Stream.  
+  * @param  SrcAddress The source memory Buffer address
+  * @param  DstAddress The destination memory Buffer address
+  * @param  DataLength The length of data to be transferred from source to destination
+  * @retval HAL status
+  */
+static void DMA_MultiBufferSetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
+{  
+  /* Configure DMA Stream data length */
+  hdma->Instance->NDTR = DataLength;
+  
+  /* Peripheral to Memory */
+  if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)
+  {   
+    /* Configure DMA Stream destination address */
+    hdma->Instance->PAR = DstAddress;
+    
+    /* Configure DMA Stream source address */
+    hdma->Instance->M0AR = SrcAddress;
+  }
+  /* Memory to Peripheral */
+  else
+  {
+    /* Configure DMA Stream source address */
+    hdma->Instance->PAR = SrcAddress;
+    
+    /* Configure DMA Stream destination address */
+    hdma->Instance->M0AR = DstAddress;
+  }
+}
+
+/**
+  * @}
+  */
+
+#endif /* HAL_DMA_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
diff --git a/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dsi.c b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dsi.c
new file mode 100644
index 0000000..17c1fd7
--- /dev/null
+++ b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dsi.c
@@ -0,0 +1,2760 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hal_dsi.c
+  * @author  MCD Application Team
+  * @brief   DSI HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the DSI peripheral:
+  *           + Initialization and de-initialization functions
+  *           + IO operation functions
+  *           + Peripheral Control functions
+  *           + Peripheral State and Errors functions
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2016 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  @verbatim
+  ==============================================================================
+                        ##### How to use this driver #####
+  ==============================================================================
+  [..]
+    The DSI HAL driver can be used as follows:
+
+    (#) Declare a DSI_HandleTypeDef handle structure, for example: DSI_HandleTypeDef  hdsi;
+
+    (#) Initialize the DSI low level resources by implementing the HAL_DSI_MspInit() API:
+        (##) Enable the DSI interface clock
+        (##) NVIC configuration if you need to use interrupt process
+            (+++) Configure the DSI interrupt priority
+            (+++) Enable the NVIC DSI IRQ Channel
+
+    (#) Initialize the DSI Host peripheral, the required PLL parameters, number of lances and
+        TX Escape clock divider by calling the HAL_DSI_Init() API which calls HAL_DSI_MspInit().
+
+    *** Configuration ***
+    =========================
+    [..]
+    (#) Use HAL_DSI_ConfigAdaptedCommandMode() function to configure the DSI host in adapted
+        command mode.
+
+    (#) When operating in video mode , use HAL_DSI_ConfigVideoMode() to configure the DSI host.
+
+    (#) Function HAL_DSI_ConfigCommand() is used to configure the DSI commands behavior in low power mode.
+
+    (#) To configure the DSI PHY timings parameters, use function HAL_DSI_ConfigPhyTimer().
+
+    (#) The DSI Host can be started/stopped using respectively functions HAL_DSI_Start() and HAL_DSI_Stop().
+        Functions HAL_DSI_ShortWrite(), HAL_DSI_LongWrite() and HAL_DSI_Read() allows respectively
+        to write DSI short packets, long packets and to read DSI packets.
+
+    (#) The DSI Host Offers two Low power modes :
+        (++) Low Power Mode on data lanes only: Only DSI data lanes are shut down.
+            It is possible to enter/exit from this mode using respectively functions HAL_DSI_EnterULPMData()
+            and HAL_DSI_ExitULPMData()
+
+        (++) Low Power Mode on data and clock lanes : All DSI lanes are shut down including data and clock lanes.
+            It is possible to enter/exit from this mode using respectively functions HAL_DSI_EnterULPM()
+            and HAL_DSI_ExitULPM()
+
+    (#) To control DSI state you can use the following function: HAL_DSI_GetState()
+
+    *** Error management ***
+    ========================
+    [..]
+    (#) User can select the DSI errors to be reported/monitored using function HAL_DSI_ConfigErrorMonitor()
+        When an error occurs, the callback HAL_DSI_ErrorCallback() is asserted and then user can retrieve
+        the error code by calling function HAL_DSI_GetError()
+
+    *** DSI HAL driver macros list ***
+    =============================================
+    [..]
+       Below the list of most used macros in DSI HAL driver.
+
+      (+) __HAL_DSI_ENABLE: Enable the DSI Host.
+      (+) __HAL_DSI_DISABLE: Disable the DSI Host.
+      (+) __HAL_DSI_WRAPPER_ENABLE: Enables the DSI wrapper.
+      (+) __HAL_DSI_WRAPPER_DISABLE: Disable the DSI wrapper.
+      (+) __HAL_DSI_PLL_ENABLE: Enables the DSI PLL.
+      (+) __HAL_DSI_PLL_DISABLE: Disables the DSI PLL.
+      (+) __HAL_DSI_REG_ENABLE: Enables the DSI regulator.
+      (+) __HAL_DSI_REG_DISABLE: Disables the DSI regulator.
+      (+) __HAL_DSI_GET_FLAG: Get the DSI pending flags.
+      (+) __HAL_DSI_CLEAR_FLAG: Clears the DSI pending flags.
+      (+) __HAL_DSI_ENABLE_IT: Enables the specified DSI interrupts.
+      (+) __HAL_DSI_DISABLE_IT: Disables the specified DSI interrupts.
+      (+) __HAL_DSI_GET_IT_SOURCE: Checks whether the specified DSI interrupt source is enabled or not.
+
+    [..]
+      (@) You can refer to the DSI HAL driver header file for more useful macros
+
+    *** Callback registration ***
+    =============================================
+    [..]
+    The compilation define  USE_HAL_DSI_REGISTER_CALLBACKS when set to 1
+    allows the user to configure dynamically the driver callbacks.
+    Use Function HAL_DSI_RegisterCallback() to register a callback.
+
+    [..]
+    Function HAL_DSI_RegisterCallback() allows to register following callbacks:
+      (+) TearingEffectCallback : DSI Tearing Effect Callback.
+      (+) EndOfRefreshCallback  : DSI End Of Refresh Callback.
+      (+) ErrorCallback         : DSI Error Callback
+      (+) MspInitCallback       : DSI MspInit.
+      (+) MspDeInitCallback     : DSI MspDeInit.
+    [..]
+    This function takes as parameters the HAL peripheral handle, the callback ID
+    and a pointer to the user callback function.
+
+    [..]
+    Use function HAL_DSI_UnRegisterCallback() to reset a callback to the default
+    weak function.
+    HAL_DSI_UnRegisterCallback takes as parameters the HAL peripheral handle,
+    and the callback ID.
+    [..]
+    This function allows to reset following callbacks:
+      (+) TearingEffectCallback : DSI Tearing Effect Callback.
+      (+) EndOfRefreshCallback  : DSI End Of Refresh Callback.
+      (+) ErrorCallback         : DSI Error Callback
+      (+) MspInitCallback       : DSI MspInit.
+      (+) MspDeInitCallback     : DSI MspDeInit.
+
+    [..]
+    By default, after the HAL_DSI_Init and when the state is HAL_DSI_STATE_RESET
+    all callbacks are set to the corresponding weak functions:
+    examples HAL_DSI_TearingEffectCallback(), HAL_DSI_EndOfRefreshCallback().
+    Exception done for MspInit and MspDeInit functions that are respectively
+    reset to the legacy weak (surcharged) functions in the HAL_DSI_Init()
+    and HAL_DSI_DeInit() only when these callbacks are null (not registered beforehand).
+    If not, MspInit or MspDeInit are not null, the HAL_DSI_Init() and HAL_DSI_DeInit()
+    keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
+
+    [..]
+    Callbacks can be registered/unregistered in HAL_DSI_STATE_READY state only.
+    Exception done MspInit/MspDeInit that can be registered/unregistered
+    in HAL_DSI_STATE_READY or HAL_DSI_STATE_RESET state,
+    thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
+    In that case first register the MspInit/MspDeInit user callbacks
+    using HAL_DSI_RegisterCallback() before calling HAL_DSI_DeInit()
+    or HAL_DSI_Init() function.
+
+    [..]
+    When The compilation define USE_HAL_DSI_REGISTER_CALLBACKS is set to 0 or
+    not defined, the callback registration feature is not available and all callbacks
+    are set to the corresponding weak functions.
+
+  @endverbatim
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+  * @{
+  */
+
+#ifdef HAL_DSI_MODULE_ENABLED
+
+#if defined(DSI)
+
+/** @addtogroup DSI
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private defines -----------------------------------------------------------*/
+/** @addtogroup DSI_Private_Constants
+  * @{
+  */
+#define DSI_TIMEOUT_VALUE ((uint32_t)1000U)  /* 1s */
+
+#define DSI_ERROR_ACK_MASK (DSI_ISR0_AE0 | DSI_ISR0_AE1 | DSI_ISR0_AE2 | DSI_ISR0_AE3 | \
+                            DSI_ISR0_AE4 | DSI_ISR0_AE5 | DSI_ISR0_AE6 | DSI_ISR0_AE7 | \
+                            DSI_ISR0_AE8 | DSI_ISR0_AE9 | DSI_ISR0_AE10 | DSI_ISR0_AE11 | \
+                            DSI_ISR0_AE12 | DSI_ISR0_AE13 | DSI_ISR0_AE14 | DSI_ISR0_AE15)
+#define DSI_ERROR_PHY_MASK (DSI_ISR0_PE0 | DSI_ISR0_PE1 | DSI_ISR0_PE2 | DSI_ISR0_PE3 | DSI_ISR0_PE4)
+#define DSI_ERROR_TX_MASK  DSI_ISR1_TOHSTX
+#define DSI_ERROR_RX_MASK  DSI_ISR1_TOLPRX
+#define DSI_ERROR_ECC_MASK (DSI_ISR1_ECCSE | DSI_ISR1_ECCME)
+#define DSI_ERROR_CRC_MASK DSI_ISR1_CRCE
+#define DSI_ERROR_PSE_MASK DSI_ISR1_PSE
+#define DSI_ERROR_EOT_MASK DSI_ISR1_EOTPE
+#define DSI_ERROR_OVF_MASK DSI_ISR1_LPWRE
+#define DSI_ERROR_GEN_MASK (DSI_ISR1_GCWRE | DSI_ISR1_GPWRE | DSI_ISR1_GPTXE | DSI_ISR1_GPRDE | DSI_ISR1_GPRXE)
+/**
+  * @}
+  */
+
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+static void DSI_ConfigPacketHeader(DSI_TypeDef *DSIx, uint32_t ChannelID, uint32_t DataType, uint32_t Data0,
+                                   uint32_t Data1);
+
+static HAL_StatusTypeDef DSI_ShortWrite(DSI_HandleTypeDef *hdsi,
+                                        uint32_t ChannelID,
+                                        uint32_t Mode,
+                                        uint32_t Param1,
+                                        uint32_t Param2);
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup DSI_Private_Functions DSI Private Functions
+  * @{
+  */
+/**
+  * @brief  Generic DSI packet header configuration
+  * @param  DSIx  Pointer to DSI register base
+  * @param  ChannelID Virtual channel ID of the header packet
+  * @param  DataType  Packet data type of the header packet
+  *                   This parameter can be any value of :
+  *                      @arg DSI_SHORT_WRITE_PKT_Data_Type
+  *                      @arg DSI_LONG_WRITE_PKT_Data_Type
+  *                      @arg DSI_SHORT_READ_PKT_Data_Type
+  *                      @arg DSI_MAX_RETURN_PKT_SIZE
+  * @param  Data0  Word count LSB
+  * @param  Data1  Word count MSB
+  * @retval None
+  */
+static void DSI_ConfigPacketHeader(DSI_TypeDef *DSIx,
+                                   uint32_t ChannelID,
+                                   uint32_t DataType,
+                                   uint32_t Data0,
+                                   uint32_t Data1)
+{
+  /* Update the DSI packet header with new information */
+  DSIx->GHCR = (DataType | (ChannelID << 6U) | (Data0 << 8U) | (Data1 << 16U));
+}
+
+/**
+  * @brief  write short DCS or short Generic command
+  * @param  hdsi  pointer to a DSI_HandleTypeDef structure that contains
+  *               the configuration information for the DSI.
+  * @param  ChannelID  Virtual channel ID.
+  * @param  Mode  DSI short packet data type.
+  *               This parameter can be any value of @arg DSI_SHORT_WRITE_PKT_Data_Type.
+  * @param  Param1  DSC command or first generic parameter.
+  *                 This parameter can be any value of @arg DSI_DCS_Command or a
+  *                 generic command code.
+  * @param  Param2  DSC parameter or second generic parameter.
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef DSI_ShortWrite(DSI_HandleTypeDef *hdsi,
+                                        uint32_t ChannelID,
+                                        uint32_t Mode,
+                                        uint32_t Param1,
+                                        uint32_t Param2)
+{
+  uint32_t tickstart;
+
+  /* Get tick */
+  tickstart = HAL_GetTick();
+
+  /* Wait for Command FIFO Empty */
+  while ((hdsi->Instance->GPSR & DSI_GPSR_CMDFE) == 0U)
+  {
+    /* Check for the Timeout */
+    if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE)
+    {
+      return HAL_TIMEOUT;
+    }
+  }
+
+  /* Configure the packet to send a short DCS command with 0 or 1 parameter */
+  /* Update the DSI packet header with new information */
+  hdsi->Instance->GHCR = (Mode | (ChannelID << 6U) | (Param1 << 8U) | (Param2 << 16U));
+
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup DSI_Exported_Functions
+  * @{
+  */
+
+/** @defgroup DSI_Group1 Initialization and Configuration functions
+  *  @brief   Initialization and Configuration functions
+  *
+@verbatim
+ ===============================================================================
+                ##### Initialization and Configuration functions #####
+ ===============================================================================
+    [..]  This section provides functions allowing to:
+      (+) Initialize and configure the DSI
+      (+) De-initialize the DSI
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initializes the DSI according to the specified
+  *         parameters in the DSI_InitTypeDef and create the associated handle.
+  * @param  hdsi  pointer to a DSI_HandleTypeDef structure that contains
+  *               the configuration information for the DSI.
+  * @param  PLLInit  pointer to a DSI_PLLInitTypeDef structure that contains
+  *                  the PLL Clock structure definition for the DSI.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DSI_Init(DSI_HandleTypeDef *hdsi, DSI_PLLInitTypeDef *PLLInit)
+{
+  uint32_t tickstart;
+  uint32_t unitIntervalx4;
+  uint32_t tempIDF;
+
+  /* Check the DSI handle allocation */
+  if (hdsi == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check function parameters */
+  assert_param(IS_DSI_PLL_NDIV(PLLInit->PLLNDIV));
+  assert_param(IS_DSI_PLL_IDF(PLLInit->PLLIDF));
+  assert_param(IS_DSI_PLL_ODF(PLLInit->PLLODF));
+  assert_param(IS_DSI_AUTO_CLKLANE_CONTROL(hdsi->Init.AutomaticClockLaneControl));
+  assert_param(IS_DSI_NUMBER_OF_LANES(hdsi->Init.NumberOfLanes));
+
+#if (USE_HAL_DSI_REGISTER_CALLBACKS == 1)
+  if (hdsi->State == HAL_DSI_STATE_RESET)
+  {
+    /* Reset the DSI callback to the legacy weak callbacks */
+    hdsi->TearingEffectCallback = HAL_DSI_TearingEffectCallback; /* Legacy weak TearingEffectCallback */
+    hdsi->EndOfRefreshCallback  = HAL_DSI_EndOfRefreshCallback;  /* Legacy weak EndOfRefreshCallback  */
+    hdsi->ErrorCallback         = HAL_DSI_ErrorCallback;         /* Legacy weak ErrorCallback         */
+
+    if (hdsi->MspInitCallback == NULL)
+    {
+      hdsi->MspInitCallback = HAL_DSI_MspInit;
+    }
+    /* Initialize the low level hardware */
+    hdsi->MspInitCallback(hdsi);
+  }
+#else
+  if (hdsi->State == HAL_DSI_STATE_RESET)
+  {
+    /* Initialize the low level hardware */
+    HAL_DSI_MspInit(hdsi);
+  }
+#endif /* USE_HAL_DSI_REGISTER_CALLBACKS */
+
+  /* Change DSI peripheral state */
+  hdsi->State = HAL_DSI_STATE_BUSY;
+
+  /**************** Turn on the regulator and enable the DSI PLL ****************/
+
+  /* Enable the regulator */
+  __HAL_DSI_REG_ENABLE(hdsi);
+
+  /* Get tick */
+  tickstart = HAL_GetTick();
+
+  /* Wait until the regulator is ready */
+  while (__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_RRS) == 0U)
+  {
+    /* Check for the Timeout */
+    if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE)
+    {
+      return HAL_TIMEOUT;
+    }
+  }
+
+  /* Set the PLL division factors */
+  hdsi->Instance->WRPCR &= ~(DSI_WRPCR_PLL_NDIV | DSI_WRPCR_PLL_IDF | DSI_WRPCR_PLL_ODF);
+  hdsi->Instance->WRPCR |= (((PLLInit->PLLNDIV) << DSI_WRPCR_PLL_NDIV_Pos) | \
+                            ((PLLInit->PLLIDF) << DSI_WRPCR_PLL_IDF_Pos) | \
+                            ((PLLInit->PLLODF) << DSI_WRPCR_PLL_ODF_Pos));
+
+  /* Enable the DSI PLL */
+  __HAL_DSI_PLL_ENABLE(hdsi);
+
+  /* Requires min of 400us delay before reading the PLLLS flag */
+  /* 1ms delay is inserted that is the minimum HAL delay granularity */
+  HAL_Delay(1);
+
+  /* Get tick */
+  tickstart = HAL_GetTick();
+
+  /* Wait for the lock of the PLL */
+  while (__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_PLLLS) == 0U)
+  {
+    /* Check for the Timeout */
+    if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE)
+    {
+      return HAL_TIMEOUT;
+    }
+  }
+
+  /*************************** Set the PHY parameters ***************************/
+
+  /* D-PHY clock and digital enable*/
+  hdsi->Instance->PCTLR |= (DSI_PCTLR_CKE | DSI_PCTLR_DEN);
+
+  /* Clock lane configuration */
+  hdsi->Instance->CLCR &= ~(DSI_CLCR_DPCC | DSI_CLCR_ACR);
+  hdsi->Instance->CLCR |= (DSI_CLCR_DPCC | hdsi->Init.AutomaticClockLaneControl);
+
+  /* Configure the number of active data lanes */
+  hdsi->Instance->PCONFR &= ~DSI_PCONFR_NL;
+  hdsi->Instance->PCONFR |= hdsi->Init.NumberOfLanes;
+
+  /************************ Set the DSI clock parameters ************************/
+
+  /* Set the TX escape clock division factor */
+  hdsi->Instance->CCR &= ~DSI_CCR_TXECKDIV;
+  hdsi->Instance->CCR |= hdsi->Init.TXEscapeCkdiv;
+
+  /* Calculate the bit period in high-speed mode in unit of 0.25 ns (UIX4) */
+  /* The equation is : UIX4 = IntegerPart( (1000/F_PHY_Mhz) * 4 )          */
+  /* Where : F_PHY_Mhz = (NDIV * HSE_Mhz) / (IDF * ODF)                    */
+  tempIDF = (PLLInit->PLLIDF > 0U) ? PLLInit->PLLIDF : 1U;
+  unitIntervalx4 = (4000000U * tempIDF * ((1UL << (0x3U & PLLInit->PLLODF)))) / ((HSE_VALUE / 1000U) * PLLInit->PLLNDIV);
+
+  /* Set the bit period in high-speed mode */
+  hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_UIX4;
+  hdsi->Instance->WPCR[0U] |= unitIntervalx4;
+
+  /****************************** Error management *****************************/
+
+  /* Disable all error interrupts and reset the Error Mask */
+  hdsi->Instance->IER[0U] = 0U;
+  hdsi->Instance->IER[1U] = 0U;
+  hdsi->ErrorMsk = 0U;
+
+  /* Initialize the error code */
+  hdsi->ErrorCode = HAL_DSI_ERROR_NONE;
+
+  /* Initialize the DSI state*/
+  hdsi->State = HAL_DSI_STATE_READY;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  De-initializes the DSI peripheral registers to their default reset
+  *         values.
+  * @param  hdsi  pointer to a DSI_HandleTypeDef structure that contains
+  *               the configuration information for the DSI.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DSI_DeInit(DSI_HandleTypeDef *hdsi)
+{
+  /* Check the DSI handle allocation */
+  if (hdsi == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Change DSI peripheral state */
+  hdsi->State = HAL_DSI_STATE_BUSY;
+
+  /* Disable the DSI wrapper */
+  __HAL_DSI_WRAPPER_DISABLE(hdsi);
+
+  /* Disable the DSI host */
+  __HAL_DSI_DISABLE(hdsi);
+
+  /* D-PHY clock and digital disable */
+  hdsi->Instance->PCTLR &= ~(DSI_PCTLR_CKE | DSI_PCTLR_DEN);
+
+  /* Turn off the DSI PLL */
+  __HAL_DSI_PLL_DISABLE(hdsi);
+
+  /* Disable the regulator */
+  __HAL_DSI_REG_DISABLE(hdsi);
+
+#if (USE_HAL_DSI_REGISTER_CALLBACKS == 1)
+  if (hdsi->MspDeInitCallback == NULL)
+  {
+    hdsi->MspDeInitCallback = HAL_DSI_MspDeInit;
+  }
+  /* DeInit the low level hardware */
+  hdsi->MspDeInitCallback(hdsi);
+#else
+  /* DeInit the low level hardware */
+  HAL_DSI_MspDeInit(hdsi);
+#endif /* USE_HAL_DSI_REGISTER_CALLBACKS */
+
+  /* Initialize the error code */
+  hdsi->ErrorCode = HAL_DSI_ERROR_NONE;
+
+  /* Initialize the DSI state*/
+  hdsi->State = HAL_DSI_STATE_RESET;
+
+  /* Release Lock */
+  __HAL_UNLOCK(hdsi);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Enable the error monitor flags
+  * @param  hdsi  pointer to a DSI_HandleTypeDef structure that contains
+  *               the configuration information for the DSI.
+  * @param  ActiveErrors  indicates which error interrupts will be enabled.
+  *                      This parameter can be any combination of @arg DSI_Error_Data_Type.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DSI_ConfigErrorMonitor(DSI_HandleTypeDef *hdsi, uint32_t ActiveErrors)
+{
+  /* Process locked */
+  __HAL_LOCK(hdsi);
+
+  hdsi->Instance->IER[0U] = 0U;
+  hdsi->Instance->IER[1U] = 0U;
+
+  /* Store active errors to the handle */
+  hdsi->ErrorMsk = ActiveErrors;
+
+  if ((ActiveErrors & HAL_DSI_ERROR_ACK) != 0U)
+  {
+    /* Enable the interrupt generation on selected errors */
+    hdsi->Instance->IER[0U] |= DSI_ERROR_ACK_MASK;
+  }
+
+  if ((ActiveErrors & HAL_DSI_ERROR_PHY) != 0U)
+  {
+    /* Enable the interrupt generation on selected errors */
+    hdsi->Instance->IER[0U] |= DSI_ERROR_PHY_MASK;
+  }
+
+  if ((ActiveErrors & HAL_DSI_ERROR_TX) != 0U)
+  {
+    /* Enable the interrupt generation on selected errors */
+    hdsi->Instance->IER[1U] |= DSI_ERROR_TX_MASK;
+  }
+
+  if ((ActiveErrors & HAL_DSI_ERROR_RX) != 0U)
+  {
+    /* Enable the interrupt generation on selected errors */
+    hdsi->Instance->IER[1U] |= DSI_ERROR_RX_MASK;
+  }
+
+  if ((ActiveErrors & HAL_DSI_ERROR_ECC) != 0U)
+  {
+    /* Enable the interrupt generation on selected errors */
+    hdsi->Instance->IER[1U] |= DSI_ERROR_ECC_MASK;
+  }
+
+  if ((ActiveErrors & HAL_DSI_ERROR_CRC) != 0U)
+  {
+    /* Enable the interrupt generation on selected errors */
+    hdsi->Instance->IER[1U] |= DSI_ERROR_CRC_MASK;
+  }
+
+  if ((ActiveErrors & HAL_DSI_ERROR_PSE) != 0U)
+  {
+    /* Enable the interrupt generation on selected errors */
+    hdsi->Instance->IER[1U] |= DSI_ERROR_PSE_MASK;
+  }
+
+  if ((ActiveErrors & HAL_DSI_ERROR_EOT) != 0U)
+  {
+    /* Enable the interrupt generation on selected errors */
+    hdsi->Instance->IER[1U] |= DSI_ERROR_EOT_MASK;
+  }
+
+  if ((ActiveErrors & HAL_DSI_ERROR_OVF) != 0U)
+  {
+    /* Enable the interrupt generation on selected errors */
+    hdsi->Instance->IER[1U] |= DSI_ERROR_OVF_MASK;
+  }
+
+  if ((ActiveErrors & HAL_DSI_ERROR_GEN) != 0U)
+  {
+    /* Enable the interrupt generation on selected errors */
+    hdsi->Instance->IER[1U] |= DSI_ERROR_GEN_MASK;
+  }
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hdsi);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the DSI MSP.
+  * @param  hdsi  pointer to a DSI_HandleTypeDef structure that contains
+  *               the configuration information for the DSI.
+  * @retval None
+  */
+__weak void HAL_DSI_MspInit(DSI_HandleTypeDef *hdsi)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hdsi);
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_DSI_MspInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  De-initializes the DSI MSP.
+  * @param  hdsi  pointer to a DSI_HandleTypeDef structure that contains
+  *               the configuration information for the DSI.
+  * @retval None
+  */
+__weak void HAL_DSI_MspDeInit(DSI_HandleTypeDef *hdsi)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hdsi);
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_DSI_MspDeInit could be implemented in the user file
+   */
+}
+
+#if (USE_HAL_DSI_REGISTER_CALLBACKS == 1)
+/**
+  * @brief  Register a User DSI Callback
+  *         To be used instead of the weak predefined callback
+  * @param hdsi dsi handle
+  * @param CallbackID ID of the callback to be registered
+  *        This parameter can be one of the following values:
+  *          @arg HAL_DSI_TEARING_EFFECT_CB_ID Tearing Effect Callback ID
+  *          @arg HAL_DSI_ENDOF_REFRESH_CB_ID End Of Refresh Callback ID
+  *          @arg HAL_DSI_ERROR_CB_ID Error Callback ID
+  *          @arg HAL_DSI_MSPINIT_CB_ID MspInit callback ID
+  *          @arg HAL_DSI_MSPDEINIT_CB_ID MspDeInit callback ID
+  * @param pCallback pointer to the Callback function
+  * @retval status
+  */
+HAL_StatusTypeDef HAL_DSI_RegisterCallback(DSI_HandleTypeDef *hdsi, HAL_DSI_CallbackIDTypeDef CallbackID,
+                                           pDSI_CallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    /* Update the error code */
+    hdsi->ErrorCode |= HAL_DSI_ERROR_INVALID_CALLBACK;
+
+    return HAL_ERROR;
+  }
+  /* Process locked */
+  __HAL_LOCK(hdsi);
+
+  if (hdsi->State == HAL_DSI_STATE_READY)
+  {
+    switch (CallbackID)
+    {
+      case HAL_DSI_TEARING_EFFECT_CB_ID :
+        hdsi->TearingEffectCallback = pCallback;
+        break;
+
+      case HAL_DSI_ENDOF_REFRESH_CB_ID :
+        hdsi->EndOfRefreshCallback = pCallback;
+        break;
+
+      case HAL_DSI_ERROR_CB_ID :
+        hdsi->ErrorCallback = pCallback;
+        break;
+
+      case HAL_DSI_MSPINIT_CB_ID :
+        hdsi->MspInitCallback = pCallback;
+        break;
+
+      case HAL_DSI_MSPDEINIT_CB_ID :
+        hdsi->MspDeInitCallback = pCallback;
+        break;
+
+      default :
+        /* Update the error code */
+        hdsi->ErrorCode |= HAL_DSI_ERROR_INVALID_CALLBACK;
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else if (hdsi->State == HAL_DSI_STATE_RESET)
+  {
+    switch (CallbackID)
+    {
+      case HAL_DSI_MSPINIT_CB_ID :
+        hdsi->MspInitCallback = pCallback;
+        break;
+
+      case HAL_DSI_MSPDEINIT_CB_ID :
+        hdsi->MspDeInitCallback = pCallback;
+        break;
+
+      default :
+        /* Update the error code */
+        hdsi->ErrorCode |= HAL_DSI_ERROR_INVALID_CALLBACK;
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    /* Update the error code */
+    hdsi->ErrorCode |= HAL_DSI_ERROR_INVALID_CALLBACK;
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(hdsi);
+
+  return status;
+}
+
+/**
+  * @brief  Unregister a DSI Callback
+  *         DSI callback is redirected to the weak predefined callback
+  * @param hdsi dsi handle
+  * @param CallbackID ID of the callback to be unregistered
+  *        This parameter can be one of the following values:
+  *          @arg HAL_DSI_TEARING_EFFECT_CB_ID Tearing Effect Callback ID
+  *          @arg HAL_DSI_ENDOF_REFRESH_CB_ID End Of Refresh Callback ID
+  *          @arg HAL_DSI_ERROR_CB_ID Error Callback ID
+  *          @arg HAL_DSI_MSPINIT_CB_ID MspInit callback ID
+  *          @arg HAL_DSI_MSPDEINIT_CB_ID MspDeInit callback ID
+  * @retval status
+  */
+HAL_StatusTypeDef HAL_DSI_UnRegisterCallback(DSI_HandleTypeDef *hdsi, HAL_DSI_CallbackIDTypeDef CallbackID)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Process locked */
+  __HAL_LOCK(hdsi);
+
+  if (hdsi->State == HAL_DSI_STATE_READY)
+  {
+    switch (CallbackID)
+    {
+      case HAL_DSI_TEARING_EFFECT_CB_ID :
+        hdsi->TearingEffectCallback = HAL_DSI_TearingEffectCallback; /* Legacy weak TearingEffectCallback */
+        break;
+
+      case HAL_DSI_ENDOF_REFRESH_CB_ID :
+        hdsi->EndOfRefreshCallback = HAL_DSI_EndOfRefreshCallback;   /* Legacy weak EndOfRefreshCallback  */
+        break;
+
+      case HAL_DSI_ERROR_CB_ID :
+        hdsi->ErrorCallback        = HAL_DSI_ErrorCallback;          /* Legacy weak ErrorCallback        */
+        break;
+
+      case HAL_DSI_MSPINIT_CB_ID :
+        hdsi->MspInitCallback = HAL_DSI_MspInit;                     /* Legacy weak MspInit Callback     */
+        break;
+
+      case HAL_DSI_MSPDEINIT_CB_ID :
+        hdsi->MspDeInitCallback = HAL_DSI_MspDeInit;                 /* Legacy weak MspDeInit Callback   */
+        break;
+
+      default :
+        /* Update the error code */
+        hdsi->ErrorCode |= HAL_DSI_ERROR_INVALID_CALLBACK;
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else if (hdsi->State == HAL_DSI_STATE_RESET)
+  {
+    switch (CallbackID)
+    {
+      case HAL_DSI_MSPINIT_CB_ID :
+        hdsi->MspInitCallback = HAL_DSI_MspInit;                  /* Legacy weak MspInit Callback   */
+        break;
+
+      case HAL_DSI_MSPDEINIT_CB_ID :
+        hdsi->MspDeInitCallback = HAL_DSI_MspDeInit;              /* Legacy weak MspDeInit Callback */
+        break;
+
+      default :
+        /* Update the error code */
+        hdsi->ErrorCode |= HAL_DSI_ERROR_INVALID_CALLBACK;
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    /* Update the error code */
+    hdsi->ErrorCode |= HAL_DSI_ERROR_INVALID_CALLBACK;
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(hdsi);
+
+  return status;
+}
+#endif /* USE_HAL_DSI_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+
+/** @defgroup DSI_Group2 IO operation functions
+  *  @brief    IO operation functions
+  *
+@verbatim
+ ===============================================================================
+                      #####  IO operation functions  #####
+ ===============================================================================
+    [..]  This section provides function allowing to:
+      (+) Handle DSI interrupt request
+
+@endverbatim
+  * @{
+  */
+/**
+  * @brief  Handles DSI interrupt request.
+  * @param  hdsi  pointer to a DSI_HandleTypeDef structure that contains
+  *               the configuration information for the DSI.
+  * @retval HAL status
+  */
+void HAL_DSI_IRQHandler(DSI_HandleTypeDef *hdsi)
+{
+  uint32_t ErrorStatus0;
+  uint32_t ErrorStatus1;
+
+  /* Tearing Effect Interrupt management ***************************************/
+  if (__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_TE) != 0U)
+  {
+    if (__HAL_DSI_GET_IT_SOURCE(hdsi, DSI_IT_TE) != 0U)
+    {
+      /* Clear the Tearing Effect Interrupt Flag */
+      __HAL_DSI_CLEAR_FLAG(hdsi, DSI_FLAG_TE);
+
+      /* Tearing Effect Callback */
+#if (USE_HAL_DSI_REGISTER_CALLBACKS == 1)
+      /*Call registered Tearing Effect callback */
+      hdsi->TearingEffectCallback(hdsi);
+#else
+      /*Call legacy Tearing Effect callback*/
+      HAL_DSI_TearingEffectCallback(hdsi);
+#endif /* USE_HAL_DSI_REGISTER_CALLBACKS */
+    }
+  }
+
+  /* End of Refresh Interrupt management ***************************************/
+  if (__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_ER) != 0U)
+  {
+    if (__HAL_DSI_GET_IT_SOURCE(hdsi, DSI_IT_ER) != 0U)
+    {
+      /* Clear the End of Refresh Interrupt Flag */
+      __HAL_DSI_CLEAR_FLAG(hdsi, DSI_FLAG_ER);
+
+      /* End of Refresh Callback */
+#if (USE_HAL_DSI_REGISTER_CALLBACKS == 1)
+      /*Call registered End of refresh callback */
+      hdsi->EndOfRefreshCallback(hdsi);
+#else
+      /*Call Legacy End of refresh callback */
+      HAL_DSI_EndOfRefreshCallback(hdsi);
+#endif /* USE_HAL_DSI_REGISTER_CALLBACKS */
+    }
+  }
+
+  /* Error Interrupts management ***********************************************/
+  if (hdsi->ErrorMsk != 0U)
+  {
+    ErrorStatus0 = hdsi->Instance->ISR[0U];
+    ErrorStatus0 &= hdsi->Instance->IER[0U];
+    ErrorStatus1 = hdsi->Instance->ISR[1U];
+    ErrorStatus1 &= hdsi->Instance->IER[1U];
+
+    if ((ErrorStatus0 & DSI_ERROR_ACK_MASK) != 0U)
+    {
+      hdsi->ErrorCode |= HAL_DSI_ERROR_ACK;
+    }
+
+    if ((ErrorStatus0 & DSI_ERROR_PHY_MASK) != 0U)
+    {
+      hdsi->ErrorCode |= HAL_DSI_ERROR_PHY;
+    }
+
+    if ((ErrorStatus1 & DSI_ERROR_TX_MASK) != 0U)
+    {
+      hdsi->ErrorCode |= HAL_DSI_ERROR_TX;
+    }
+
+    if ((ErrorStatus1 & DSI_ERROR_RX_MASK) != 0U)
+    {
+      hdsi->ErrorCode |= HAL_DSI_ERROR_RX;
+    }
+
+    if ((ErrorStatus1 & DSI_ERROR_ECC_MASK) != 0U)
+    {
+      hdsi->ErrorCode |= HAL_DSI_ERROR_ECC;
+    }
+
+    if ((ErrorStatus1 & DSI_ERROR_CRC_MASK) != 0U)
+    {
+      hdsi->ErrorCode |= HAL_DSI_ERROR_CRC;
+    }
+
+    if ((ErrorStatus1 & DSI_ERROR_PSE_MASK) != 0U)
+    {
+      hdsi->ErrorCode |= HAL_DSI_ERROR_PSE;
+    }
+
+    if ((ErrorStatus1 & DSI_ERROR_EOT_MASK) != 0U)
+    {
+      hdsi->ErrorCode |= HAL_DSI_ERROR_EOT;
+    }
+
+    if ((ErrorStatus1 & DSI_ERROR_OVF_MASK) != 0U)
+    {
+      hdsi->ErrorCode |= HAL_DSI_ERROR_OVF;
+    }
+
+    if ((ErrorStatus1 & DSI_ERROR_GEN_MASK) != 0U)
+    {
+      hdsi->ErrorCode |= HAL_DSI_ERROR_GEN;
+    }
+
+    /* Check only selected errors */
+    if (hdsi->ErrorCode != HAL_DSI_ERROR_NONE)
+    {
+      /* DSI error interrupt callback */
+#if (USE_HAL_DSI_REGISTER_CALLBACKS == 1)
+      /*Call registered Error callback */
+      hdsi->ErrorCallback(hdsi);
+#else
+      /*Call Legacy Error callback */
+      HAL_DSI_ErrorCallback(hdsi);
+#endif /* USE_HAL_DSI_REGISTER_CALLBACKS */
+    }
+  }
+}
+
+/**
+  * @brief  Tearing Effect DSI callback.
+  * @param  hdsi  pointer to a DSI_HandleTypeDef structure that contains
+  *               the configuration information for the DSI.
+  * @retval None
+  */
+__weak void HAL_DSI_TearingEffectCallback(DSI_HandleTypeDef *hdsi)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hdsi);
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_DSI_TearingEffectCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  End of Refresh DSI callback.
+  * @param  hdsi  pointer to a DSI_HandleTypeDef structure that contains
+  *               the configuration information for the DSI.
+  * @retval None
+  */
+__weak void HAL_DSI_EndOfRefreshCallback(DSI_HandleTypeDef *hdsi)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hdsi);
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_DSI_EndOfRefreshCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Operation Error DSI callback.
+  * @param  hdsi  pointer to a DSI_HandleTypeDef structure that contains
+  *               the configuration information for the DSI.
+  * @retval None
+  */
+__weak void HAL_DSI_ErrorCallback(DSI_HandleTypeDef *hdsi)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hdsi);
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_DSI_ErrorCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup DSI_Group3 Peripheral Control functions
+  *  @brief    Peripheral Control functions
+  *
+@verbatim
+ ===============================================================================
+                    ##### Peripheral Control functions #####
+ ===============================================================================
+    [..]  This section provides functions allowing to:
+      (+) Configure the Generic interface read-back Virtual Channel ID
+      (+) Select video mode and configure the corresponding parameters
+      (+) Configure command transmission mode: High-speed or Low-power
+      (+) Configure the flow control
+      (+) Configure the DSI PHY timer
+      (+) Configure the DSI HOST timeout
+      (+) Configure the DSI HOST timeout
+      (+) Start/Stop the DSI module
+      (+) Refresh the display in command mode
+      (+) Controls the display color mode in Video mode
+      (+) Control the display shutdown in Video mode
+      (+) write short DCS or short Generic command
+      (+) write long DCS or long Generic command
+      (+) Read command (DCS or generic)
+      (+) Enter/Exit the Ultra Low Power Mode on data only (D-PHY PLL running)
+      (+) Enter/Exit the Ultra Low Power Mode on data only and clock (D-PHY PLL turned off)
+      (+) Start/Stop test pattern generation
+      (+) Slew-Rate And Delay Tuning
+      (+) Low-Power Reception Filter Tuning
+      (+) Activate an additional current path on all lanes to meet the SDDTx parameter
+      (+) Custom lane pins configuration
+      (+) Set custom timing for the PHY
+      (+) Force the Clock/Data Lane in TX Stop Mode
+      (+) Force LP Receiver in Low-Power Mode
+      (+) Force Data Lanes in RX Mode after a BTA
+      (+) Enable a pull-down on the lanes to prevent from floating states when unused
+      (+) Switch off the contention detection on data lanes
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Configure the Generic interface read-back Virtual Channel ID.
+  * @param  hdsi  pointer to a DSI_HandleTypeDef structure that contains
+  *               the configuration information for the DSI.
+  * @param  VirtualChannelID  Virtual channel ID
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DSI_SetGenericVCID(DSI_HandleTypeDef *hdsi, uint32_t VirtualChannelID)
+{
+  /* Process locked */
+  __HAL_LOCK(hdsi);
+
+  /* Update the GVCID register */
+  hdsi->Instance->GVCIDR &= ~DSI_GVCIDR_VCID;
+  hdsi->Instance->GVCIDR |= VirtualChannelID;
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hdsi);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Select video mode and configure the corresponding parameters
+  * @param  hdsi  pointer to a DSI_HandleTypeDef structure that contains
+  *               the configuration information for the DSI.
+  * @param  VidCfg pointer to a DSI_VidCfgTypeDef structure that contains
+  *                the DSI video mode configuration parameters
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DSI_ConfigVideoMode(DSI_HandleTypeDef *hdsi, DSI_VidCfgTypeDef *VidCfg)
+{
+  /* Process locked */
+  __HAL_LOCK(hdsi);
+
+  /* Check the parameters */
+  assert_param(IS_DSI_COLOR_CODING(VidCfg->ColorCoding));
+  assert_param(IS_DSI_VIDEO_MODE_TYPE(VidCfg->Mode));
+  assert_param(IS_DSI_LP_COMMAND(VidCfg->LPCommandEnable));
+  assert_param(IS_DSI_LP_HFP(VidCfg->LPHorizontalFrontPorchEnable));
+  assert_param(IS_DSI_LP_HBP(VidCfg->LPHorizontalBackPorchEnable));
+  assert_param(IS_DSI_LP_VACTIVE(VidCfg->LPVerticalActiveEnable));
+  assert_param(IS_DSI_LP_VFP(VidCfg->LPVerticalFrontPorchEnable));
+  assert_param(IS_DSI_LP_VBP(VidCfg->LPVerticalBackPorchEnable));
+  assert_param(IS_DSI_LP_VSYNC(VidCfg->LPVerticalSyncActiveEnable));
+  assert_param(IS_DSI_FBTAA(VidCfg->FrameBTAAcknowledgeEnable));
+  assert_param(IS_DSI_DE_POLARITY(VidCfg->DEPolarity));
+  assert_param(IS_DSI_VSYNC_POLARITY(VidCfg->VSPolarity));
+  assert_param(IS_DSI_HSYNC_POLARITY(VidCfg->HSPolarity));
+  /* Check the LooselyPacked variant only in 18-bit mode */
+  if (VidCfg->ColorCoding == DSI_RGB666)
+  {
+    assert_param(IS_DSI_LOOSELY_PACKED(VidCfg->LooselyPacked));
+  }
+
+  /* Select video mode by resetting CMDM and DSIM bits */
+  hdsi->Instance->MCR &= ~DSI_MCR_CMDM;
+  hdsi->Instance->WCFGR &= ~DSI_WCFGR_DSIM;
+
+  /* Configure the video mode transmission type */
+  hdsi->Instance->VMCR &= ~DSI_VMCR_VMT;
+  hdsi->Instance->VMCR |= VidCfg->Mode;
+
+  /* Configure the video packet size */
+  hdsi->Instance->VPCR &= ~DSI_VPCR_VPSIZE;
+  hdsi->Instance->VPCR |= VidCfg->PacketSize;
+
+  /* Set the chunks number to be transmitted through the DSI link */
+  hdsi->Instance->VCCR &= ~DSI_VCCR_NUMC;
+  hdsi->Instance->VCCR |= VidCfg->NumberOfChunks;
+
+  /* Set the size of the null packet */
+  hdsi->Instance->VNPCR &= ~DSI_VNPCR_NPSIZE;
+  hdsi->Instance->VNPCR |= VidCfg->NullPacketSize;
+
+  /* Select the virtual channel for the LTDC interface traffic */
+  hdsi->Instance->LVCIDR &= ~DSI_LVCIDR_VCID;
+  hdsi->Instance->LVCIDR |= VidCfg->VirtualChannelID;
+
+  /* Configure the polarity of control signals */
+  hdsi->Instance->LPCR &= ~(DSI_LPCR_DEP | DSI_LPCR_VSP | DSI_LPCR_HSP);
+  hdsi->Instance->LPCR |= (VidCfg->DEPolarity | VidCfg->VSPolarity | VidCfg->HSPolarity);
+
+  /* Select the color coding for the host */
+  hdsi->Instance->LCOLCR &= ~DSI_LCOLCR_COLC;
+  hdsi->Instance->LCOLCR |= VidCfg->ColorCoding;
+
+  /* Select the color coding for the wrapper */
+  hdsi->Instance->WCFGR &= ~DSI_WCFGR_COLMUX;
+  hdsi->Instance->WCFGR |= ((VidCfg->ColorCoding) << 1U);
+
+  /* Enable/disable the loosely packed variant to 18-bit configuration */
+  if (VidCfg->ColorCoding == DSI_RGB666)
+  {
+    hdsi->Instance->LCOLCR &= ~DSI_LCOLCR_LPE;
+    hdsi->Instance->LCOLCR |= VidCfg->LooselyPacked;
+  }
+
+  /* Set the Horizontal Synchronization Active (HSA) in lane byte clock cycles */
+  hdsi->Instance->VHSACR &= ~DSI_VHSACR_HSA;
+  hdsi->Instance->VHSACR |= VidCfg->HorizontalSyncActive;
+
+  /* Set the Horizontal Back Porch (HBP) in lane byte clock cycles */
+  hdsi->Instance->VHBPCR &= ~DSI_VHBPCR_HBP;
+  hdsi->Instance->VHBPCR |= VidCfg->HorizontalBackPorch;
+
+  /* Set the total line time (HLINE=HSA+HBP+HACT+HFP) in lane byte clock cycles */
+  hdsi->Instance->VLCR &= ~DSI_VLCR_HLINE;
+  hdsi->Instance->VLCR |= VidCfg->HorizontalLine;
+
+  /* Set the Vertical Synchronization Active (VSA) */
+  hdsi->Instance->VVSACR &= ~DSI_VVSACR_VSA;
+  hdsi->Instance->VVSACR |= VidCfg->VerticalSyncActive;
+
+  /* Set the Vertical Back Porch (VBP)*/
+  hdsi->Instance->VVBPCR &= ~DSI_VVBPCR_VBP;
+  hdsi->Instance->VVBPCR |= VidCfg->VerticalBackPorch;
+
+  /* Set the Vertical Front Porch (VFP)*/
+  hdsi->Instance->VVFPCR &= ~DSI_VVFPCR_VFP;
+  hdsi->Instance->VVFPCR |= VidCfg->VerticalFrontPorch;
+
+  /* Set the Vertical Active period*/
+  hdsi->Instance->VVACR &= ~DSI_VVACR_VA;
+  hdsi->Instance->VVACR |= VidCfg->VerticalActive;
+
+  /* Configure the command transmission mode */
+  hdsi->Instance->VMCR &= ~DSI_VMCR_LPCE;
+  hdsi->Instance->VMCR |= VidCfg->LPCommandEnable;
+
+  /* Low power largest packet size */
+  hdsi->Instance->LPMCR &= ~DSI_LPMCR_LPSIZE;
+  hdsi->Instance->LPMCR |= ((VidCfg->LPLargestPacketSize) << 16U);
+
+  /* Low power VACT largest packet size */
+  hdsi->Instance->LPMCR &= ~DSI_LPMCR_VLPSIZE;
+  hdsi->Instance->LPMCR |= VidCfg->LPVACTLargestPacketSize;
+
+  /* Enable LP transition in HFP period */
+  hdsi->Instance->VMCR &= ~DSI_VMCR_LPHFPE;
+  hdsi->Instance->VMCR |= VidCfg->LPHorizontalFrontPorchEnable;
+
+  /* Enable LP transition in HBP period */
+  hdsi->Instance->VMCR &= ~DSI_VMCR_LPHBPE;
+  hdsi->Instance->VMCR |= VidCfg->LPHorizontalBackPorchEnable;
+
+  /* Enable LP transition in VACT period */
+  hdsi->Instance->VMCR &= ~DSI_VMCR_LPVAE;
+  hdsi->Instance->VMCR |= VidCfg->LPVerticalActiveEnable;
+
+  /* Enable LP transition in VFP period */
+  hdsi->Instance->VMCR &= ~DSI_VMCR_LPVFPE;
+  hdsi->Instance->VMCR |= VidCfg->LPVerticalFrontPorchEnable;
+
+  /* Enable LP transition in VBP period */
+  hdsi->Instance->VMCR &= ~DSI_VMCR_LPVBPE;
+  hdsi->Instance->VMCR |= VidCfg->LPVerticalBackPorchEnable;
+
+  /* Enable LP transition in vertical sync period */
+  hdsi->Instance->VMCR &= ~DSI_VMCR_LPVSAE;
+  hdsi->Instance->VMCR |= VidCfg->LPVerticalSyncActiveEnable;
+
+  /* Enable the request for an acknowledge response at the end of a frame */
+  hdsi->Instance->VMCR &= ~DSI_VMCR_FBTAAE;
+  hdsi->Instance->VMCR |= VidCfg->FrameBTAAcknowledgeEnable;
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hdsi);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Select adapted command mode and configure the corresponding parameters
+  * @param  hdsi  pointer to a DSI_HandleTypeDef structure that contains
+  *               the configuration information for the DSI.
+  * @param  CmdCfg  pointer to a DSI_CmdCfgTypeDef structure that contains
+  *                 the DSI command mode configuration parameters
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DSI_ConfigAdaptedCommandMode(DSI_HandleTypeDef *hdsi, DSI_CmdCfgTypeDef *CmdCfg)
+{
+  /* Process locked */
+  __HAL_LOCK(hdsi);
+
+  /* Check the parameters */
+  assert_param(IS_DSI_COLOR_CODING(CmdCfg->ColorCoding));
+  assert_param(IS_DSI_TE_SOURCE(CmdCfg->TearingEffectSource));
+  assert_param(IS_DSI_TE_POLARITY(CmdCfg->TearingEffectPolarity));
+  assert_param(IS_DSI_AUTOMATIC_REFRESH(CmdCfg->AutomaticRefresh));
+  assert_param(IS_DSI_VS_POLARITY(CmdCfg->VSyncPol));
+  assert_param(IS_DSI_TE_ACK_REQUEST(CmdCfg->TEAcknowledgeRequest));
+  assert_param(IS_DSI_DE_POLARITY(CmdCfg->DEPolarity));
+  assert_param(IS_DSI_VSYNC_POLARITY(CmdCfg->VSPolarity));
+  assert_param(IS_DSI_HSYNC_POLARITY(CmdCfg->HSPolarity));
+
+  /* Select command mode by setting CMDM and DSIM bits */
+  hdsi->Instance->MCR |= DSI_MCR_CMDM;
+  hdsi->Instance->WCFGR &= ~DSI_WCFGR_DSIM;
+  hdsi->Instance->WCFGR |= DSI_WCFGR_DSIM;
+
+  /* Select the virtual channel for the LTDC interface traffic */
+  hdsi->Instance->LVCIDR &= ~DSI_LVCIDR_VCID;
+  hdsi->Instance->LVCIDR |= CmdCfg->VirtualChannelID;
+
+  /* Configure the polarity of control signals */
+  hdsi->Instance->LPCR &= ~(DSI_LPCR_DEP | DSI_LPCR_VSP | DSI_LPCR_HSP);
+  hdsi->Instance->LPCR |= (CmdCfg->DEPolarity | CmdCfg->VSPolarity | CmdCfg->HSPolarity);
+
+  /* Select the color coding for the host */
+  hdsi->Instance->LCOLCR &= ~DSI_LCOLCR_COLC;
+  hdsi->Instance->LCOLCR |= CmdCfg->ColorCoding;
+
+  /* Select the color coding for the wrapper */
+  hdsi->Instance->WCFGR &= ~DSI_WCFGR_COLMUX;
+  hdsi->Instance->WCFGR |= ((CmdCfg->ColorCoding) << 1U);
+
+  /* Configure the maximum allowed size for write memory command */
+  hdsi->Instance->LCCR &= ~DSI_LCCR_CMDSIZE;
+  hdsi->Instance->LCCR |= CmdCfg->CommandSize;
+
+  /* Configure the tearing effect source and polarity and select the refresh mode */
+  hdsi->Instance->WCFGR &= ~(DSI_WCFGR_TESRC | DSI_WCFGR_TEPOL | DSI_WCFGR_AR | DSI_WCFGR_VSPOL);
+  hdsi->Instance->WCFGR |= (CmdCfg->TearingEffectSource | CmdCfg->TearingEffectPolarity | CmdCfg->AutomaticRefresh |
+                            CmdCfg->VSyncPol);
+
+  /* Configure the tearing effect acknowledge request */
+  hdsi->Instance->CMCR &= ~DSI_CMCR_TEARE;
+  hdsi->Instance->CMCR |= CmdCfg->TEAcknowledgeRequest;
+
+  /* Enable the Tearing Effect interrupt */
+  __HAL_DSI_ENABLE_IT(hdsi, DSI_IT_TE);
+
+  /* Enable the End of Refresh interrupt */
+  __HAL_DSI_ENABLE_IT(hdsi, DSI_IT_ER);
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hdsi);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Configure command transmission mode: High-speed or Low-power
+  *         and enable/disable acknowledge request after packet transmission
+  * @param  hdsi  pointer to a DSI_HandleTypeDef structure that contains
+  *               the configuration information for the DSI.
+  * @param  LPCmd  pointer to a DSI_LPCmdTypeDef structure that contains
+  *                the DSI command transmission mode configuration parameters
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DSI_ConfigCommand(DSI_HandleTypeDef *hdsi, DSI_LPCmdTypeDef *LPCmd)
+{
+  /* Process locked */
+  __HAL_LOCK(hdsi);
+
+  assert_param(IS_DSI_LP_GSW0P(LPCmd->LPGenShortWriteNoP));
+  assert_param(IS_DSI_LP_GSW1P(LPCmd->LPGenShortWriteOneP));
+  assert_param(IS_DSI_LP_GSW2P(LPCmd->LPGenShortWriteTwoP));
+  assert_param(IS_DSI_LP_GSR0P(LPCmd->LPGenShortReadNoP));
+  assert_param(IS_DSI_LP_GSR1P(LPCmd->LPGenShortReadOneP));
+  assert_param(IS_DSI_LP_GSR2P(LPCmd->LPGenShortReadTwoP));
+  assert_param(IS_DSI_LP_GLW(LPCmd->LPGenLongWrite));
+  assert_param(IS_DSI_LP_DSW0P(LPCmd->LPDcsShortWriteNoP));
+  assert_param(IS_DSI_LP_DSW1P(LPCmd->LPDcsShortWriteOneP));
+  assert_param(IS_DSI_LP_DSR0P(LPCmd->LPDcsShortReadNoP));
+  assert_param(IS_DSI_LP_DLW(LPCmd->LPDcsLongWrite));
+  assert_param(IS_DSI_LP_MRDP(LPCmd->LPMaxReadPacket));
+  assert_param(IS_DSI_ACK_REQUEST(LPCmd->AcknowledgeRequest));
+
+  /* Select High-speed or Low-power for command transmission */
+  hdsi->Instance->CMCR &= ~(DSI_CMCR_GSW0TX | \
+                            DSI_CMCR_GSW1TX | \
+                            DSI_CMCR_GSW2TX | \
+                            DSI_CMCR_GSR0TX | \
+                            DSI_CMCR_GSR1TX | \
+                            DSI_CMCR_GSR2TX | \
+                            DSI_CMCR_GLWTX  | \
+                            DSI_CMCR_DSW0TX | \
+                            DSI_CMCR_DSW1TX | \
+                            DSI_CMCR_DSR0TX | \
+                            DSI_CMCR_DLWTX  | \
+                            DSI_CMCR_MRDPS);
+  hdsi->Instance->CMCR |= (LPCmd->LPGenShortWriteNoP  | \
+                           LPCmd->LPGenShortWriteOneP | \
+                           LPCmd->LPGenShortWriteTwoP | \
+                           LPCmd->LPGenShortReadNoP   | \
+                           LPCmd->LPGenShortReadOneP  | \
+                           LPCmd->LPGenShortReadTwoP  | \
+                           LPCmd->LPGenLongWrite      | \
+                           LPCmd->LPDcsShortWriteNoP  | \
+                           LPCmd->LPDcsShortWriteOneP | \
+                           LPCmd->LPDcsShortReadNoP   | \
+                           LPCmd->LPDcsLongWrite      | \
+                           LPCmd->LPMaxReadPacket);
+
+  /* Configure the acknowledge request after each packet transmission */
+  hdsi->Instance->CMCR &= ~DSI_CMCR_ARE;
+  hdsi->Instance->CMCR |= LPCmd->AcknowledgeRequest;
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hdsi);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Configure the flow control parameters
+  * @param  hdsi  pointer to a DSI_HandleTypeDef structure that contains
+  *               the configuration information for the DSI.
+  * @param  FlowControl  flow control feature(s) to be enabled.
+  *                      This parameter can be any combination of @arg DSI_FlowControl.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DSI_ConfigFlowControl(DSI_HandleTypeDef *hdsi, uint32_t FlowControl)
+{
+  /* Process locked */
+  __HAL_LOCK(hdsi);
+
+  /* Check the parameters */
+  assert_param(IS_DSI_FLOW_CONTROL(FlowControl));
+
+  /* Set the DSI Host Protocol Configuration Register */
+  hdsi->Instance->PCR &= ~DSI_FLOW_CONTROL_ALL;
+  hdsi->Instance->PCR |= FlowControl;
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hdsi);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Configure the DSI PHY timer parameters
+  * @param  hdsi  pointer to a DSI_HandleTypeDef structure that contains
+  *               the configuration information for the DSI.
+  * @param  PhyTimers  DSI_PHY_TimerTypeDef structure that contains
+  *                    the DSI PHY timing parameters
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DSI_ConfigPhyTimer(DSI_HandleTypeDef *hdsi, DSI_PHY_TimerTypeDef *PhyTimers)
+{
+  uint32_t maxTime;
+  /* Process locked */
+  __HAL_LOCK(hdsi);
+
+  maxTime = (PhyTimers->ClockLaneLP2HSTime > PhyTimers->ClockLaneHS2LPTime) ? PhyTimers->ClockLaneLP2HSTime :
+            PhyTimers->ClockLaneHS2LPTime;
+
+  /* Clock lane timer configuration */
+
+  /* In Automatic Clock Lane control mode, the DSI Host can turn off the clock lane between two
+     High-Speed transmission.
+     To do so, the DSI Host calculates the time required for the clock lane to change from HighSpeed
+     to Low-Power and from Low-Power to High-Speed.
+     This timings are configured by the HS2LP_TIME and LP2HS_TIME in the DSI Host Clock Lane Timer Configuration
+     Register (DSI_CLTCR).
+     But the DSI Host is not calculating LP2HS_TIME + HS2LP_TIME but 2 x HS2LP_TIME.
+
+     Workaround : Configure HS2LP_TIME and LP2HS_TIME with the same value being the max of HS2LP_TIME or LP2HS_TIME.
+    */
+  hdsi->Instance->CLTCR &= ~(DSI_CLTCR_LP2HS_TIME | DSI_CLTCR_HS2LP_TIME);
+  hdsi->Instance->CLTCR |= (maxTime | ((maxTime) << 16U));
+
+  /* Data lane timer configuration */
+  hdsi->Instance->DLTCR &= ~(DSI_DLTCR_MRD_TIME | DSI_DLTCR_LP2HS_TIME | DSI_DLTCR_HS2LP_TIME);
+  hdsi->Instance->DLTCR |= (PhyTimers->DataLaneMaxReadTime | ((PhyTimers->DataLaneLP2HSTime) << 16U) | ((
+                              PhyTimers->DataLaneHS2LPTime) << 24U));
+
+  /* Configure the wait period to request HS transmission after a stop state */
+  hdsi->Instance->PCONFR &= ~DSI_PCONFR_SW_TIME;
+  hdsi->Instance->PCONFR |= ((PhyTimers->StopWaitTime) << 8U);
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hdsi);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Configure the DSI HOST timeout parameters
+  * @param  hdsi  pointer to a DSI_HandleTypeDef structure that contains
+  *               the configuration information for the DSI.
+  * @param  HostTimeouts  DSI_HOST_TimeoutTypeDef structure that contains
+  *                       the DSI host timeout parameters
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DSI_ConfigHostTimeouts(DSI_HandleTypeDef *hdsi, DSI_HOST_TimeoutTypeDef *HostTimeouts)
+{
+  /* Process locked */
+  __HAL_LOCK(hdsi);
+
+  /* Set the timeout clock division factor */
+  hdsi->Instance->CCR &= ~DSI_CCR_TOCKDIV;
+  hdsi->Instance->CCR |= ((HostTimeouts->TimeoutCkdiv) << 8U);
+
+  /* High-speed transmission timeout */
+  hdsi->Instance->TCCR[0U] &= ~DSI_TCCR0_HSTX_TOCNT;
+  hdsi->Instance->TCCR[0U] |= ((HostTimeouts->HighSpeedTransmissionTimeout) << 16U);
+
+  /* Low-power reception timeout */
+  hdsi->Instance->TCCR[0U] &= ~DSI_TCCR0_LPRX_TOCNT;
+  hdsi->Instance->TCCR[0U] |= HostTimeouts->LowPowerReceptionTimeout;
+
+  /* High-speed read timeout */
+  hdsi->Instance->TCCR[1U] &= ~DSI_TCCR1_HSRD_TOCNT;
+  hdsi->Instance->TCCR[1U] |= HostTimeouts->HighSpeedReadTimeout;
+
+  /* Low-power read timeout */
+  hdsi->Instance->TCCR[2U] &= ~DSI_TCCR2_LPRD_TOCNT;
+  hdsi->Instance->TCCR[2U] |= HostTimeouts->LowPowerReadTimeout;
+
+  /* High-speed write timeout */
+  hdsi->Instance->TCCR[3U] &= ~DSI_TCCR3_HSWR_TOCNT;
+  hdsi->Instance->TCCR[3U] |= HostTimeouts->HighSpeedWriteTimeout;
+
+  /* High-speed write presp mode */
+  hdsi->Instance->TCCR[3U] &= ~DSI_TCCR3_PM;
+  hdsi->Instance->TCCR[3U] |= HostTimeouts->HighSpeedWritePrespMode;
+
+  /* Low-speed write timeout */
+  hdsi->Instance->TCCR[4U] &= ~DSI_TCCR4_LPWR_TOCNT;
+  hdsi->Instance->TCCR[4U] |= HostTimeouts->LowPowerWriteTimeout;
+
+  /* BTA timeout */
+  hdsi->Instance->TCCR[5U] &= ~DSI_TCCR5_BTA_TOCNT;
+  hdsi->Instance->TCCR[5U] |= HostTimeouts->BTATimeout;
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hdsi);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Start the DSI module
+  * @param  hdsi  pointer to a DSI_HandleTypeDef structure that contains
+  *               the configuration information for the DSI.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DSI_Start(DSI_HandleTypeDef *hdsi)
+{
+  /* Process locked */
+  __HAL_LOCK(hdsi);
+
+  /* Enable the DSI host */
+  __HAL_DSI_ENABLE(hdsi);
+
+  /* Enable the DSI wrapper */
+  __HAL_DSI_WRAPPER_ENABLE(hdsi);
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hdsi);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stop the DSI module
+  * @param  hdsi  pointer to a DSI_HandleTypeDef structure that contains
+  *               the configuration information for the DSI.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DSI_Stop(DSI_HandleTypeDef *hdsi)
+{
+  /* Process locked */
+  __HAL_LOCK(hdsi);
+
+  /* Disable the DSI host */
+  __HAL_DSI_DISABLE(hdsi);
+
+  /* Disable the DSI wrapper */
+  __HAL_DSI_WRAPPER_DISABLE(hdsi);
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hdsi);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Refresh the display in command mode
+  * @param  hdsi  pointer to a DSI_HandleTypeDef structure that contains
+  *               the configuration information for the DSI.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DSI_Refresh(DSI_HandleTypeDef *hdsi)
+{
+  /* Process locked */
+  __HAL_LOCK(hdsi);
+
+  /* Update the display */
+  hdsi->Instance->WCR |= DSI_WCR_LTDCEN;
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hdsi);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Controls the display color mode in Video mode
+  * @param  hdsi  pointer to a DSI_HandleTypeDef structure that contains
+  *               the configuration information for the DSI.
+  * @param  ColorMode  Color mode (full or 8-colors).
+  *                    This parameter can be any value of @arg DSI_Color_Mode
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DSI_ColorMode(DSI_HandleTypeDef *hdsi, uint32_t ColorMode)
+{
+  /* Process locked */
+  __HAL_LOCK(hdsi);
+
+  /* Check the parameters */
+  assert_param(IS_DSI_COLOR_MODE(ColorMode));
+
+  /* Update the display color mode */
+  hdsi->Instance->WCR &= ~DSI_WCR_COLM;
+  hdsi->Instance->WCR |= ColorMode;
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hdsi);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Control the display shutdown in Video mode
+  * @param  hdsi  pointer to a DSI_HandleTypeDef structure that contains
+  *               the configuration information for the DSI.
+  * @param  Shutdown  Shut-down (Display-ON or Display-OFF).
+  *                   This parameter can be any value of @arg DSI_ShutDown
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DSI_Shutdown(DSI_HandleTypeDef *hdsi, uint32_t Shutdown)
+{
+  /* Process locked */
+  __HAL_LOCK(hdsi);
+
+  /* Check the parameters */
+  assert_param(IS_DSI_SHUT_DOWN(Shutdown));
+
+  /* Update the display Shutdown */
+  hdsi->Instance->WCR &= ~DSI_WCR_SHTDN;
+  hdsi->Instance->WCR |= Shutdown;
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hdsi);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  write short DCS or short Generic command
+  * @param  hdsi  pointer to a DSI_HandleTypeDef structure that contains
+  *               the configuration information for the DSI.
+  * @param  ChannelID  Virtual channel ID.
+  * @param  Mode  DSI short packet data type.
+  *               This parameter can be any value of @arg DSI_SHORT_WRITE_PKT_Data_Type.
+  * @param  Param1  DSC command or first generic parameter.
+  *                 This parameter can be any value of @arg DSI_DCS_Command or a
+  *                 generic command code.
+  * @param  Param2  DSC parameter or second generic parameter.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DSI_ShortWrite(DSI_HandleTypeDef *hdsi,
+                                     uint32_t ChannelID,
+                                     uint32_t Mode,
+                                     uint32_t Param1,
+                                     uint32_t Param2)
+{
+  HAL_StatusTypeDef status;
+  /* Check the parameters */
+  assert_param(IS_DSI_SHORT_WRITE_PACKET_TYPE(Mode));
+
+  /* Process locked */
+  __HAL_LOCK(hdsi);
+
+  status = DSI_ShortWrite(hdsi, ChannelID, Mode, Param1, Param2);
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hdsi);
+
+  return status;
+}
+
+/**
+  * @brief  write long DCS or long Generic command
+  * @param  hdsi  pointer to a DSI_HandleTypeDef structure that contains
+  *               the configuration information for the DSI.
+  * @param  ChannelID  Virtual channel ID.
+  * @param  Mode  DSI long packet data type.
+  *               This parameter can be any value of @arg DSI_LONG_WRITE_PKT_Data_Type.
+  * @param  NbParams  Number of parameters.
+  * @param  Param1  DSC command or first generic parameter.
+  *                 This parameter can be any value of @arg DSI_DCS_Command or a
+  *                 generic command code
+  * @param  ParametersTable  Pointer to parameter values table.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DSI_LongWrite(DSI_HandleTypeDef *hdsi,
+                                    uint32_t ChannelID,
+                                    uint32_t Mode,
+                                    uint32_t NbParams,
+                                    uint32_t Param1,
+                                    uint8_t *ParametersTable)
+{
+  uint32_t uicounter;
+  uint32_t nbBytes;
+  uint32_t count;
+  uint32_t tickstart;
+  uint32_t fifoword;
+  uint8_t *pparams = ParametersTable;
+
+  /* Process locked */
+  __HAL_LOCK(hdsi);
+
+  /* Check the parameters */
+  assert_param(IS_DSI_LONG_WRITE_PACKET_TYPE(Mode));
+
+  /* Get tick */
+  tickstart = HAL_GetTick();
+
+  /* Wait for Command FIFO Empty */
+  while ((hdsi->Instance->GPSR & DSI_GPSR_CMDFE) == 0U)
+  {
+    /* Check for the Timeout */
+    if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE)
+    {
+      /* Process Unlocked */
+      __HAL_UNLOCK(hdsi);
+
+      return HAL_TIMEOUT;
+    }
+  }
+
+  /* Set the DCS code on payload byte 1, and the other parameters on the write FIFO command*/
+  fifoword = Param1;
+  nbBytes = (NbParams < 3U) ? NbParams : 3U;
+
+  for (count = 0U; count < nbBytes; count++)
+  {
+    fifoword |= (((uint32_t)(*(pparams + count))) << (8U + (8U * count)));
+  }
+  hdsi->Instance->GPDR = fifoword;
+
+  uicounter = NbParams - nbBytes;
+  pparams += nbBytes;
+  /* Set the Next parameters on the write FIFO command*/
+  while (uicounter != 0U)
+  {
+    nbBytes = (uicounter < 4U) ? uicounter : 4U;
+    fifoword = 0U;
+    for (count = 0U; count < nbBytes; count++)
+    {
+      fifoword |= (((uint32_t)(*(pparams + count))) << (8U * count));
+    }
+    hdsi->Instance->GPDR = fifoword;
+
+    uicounter -= nbBytes;
+    pparams += nbBytes;
+  }
+
+  /* Configure the packet to send a long DCS command */
+  DSI_ConfigPacketHeader(hdsi->Instance,
+                         ChannelID,
+                         Mode,
+                         ((NbParams + 1U) & 0x00FFU),
+                         (((NbParams + 1U) & 0xFF00U) >> 8U));
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hdsi);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Read command (DCS or generic)
+  * @param  hdsi  pointer to a DSI_HandleTypeDef structure that contains
+  *               the configuration information for the DSI.
+  * @param  ChannelNbr  Virtual channel ID
+  * @param  Array pointer to a buffer to store the payload of a read back operation.
+  * @param  Size  Data size to be read (in byte).
+  * @param  Mode  DSI read packet data type.
+  *               This parameter can be any value of @arg DSI_SHORT_READ_PKT_Data_Type.
+  * @param  DCSCmd  DCS get/read command.
+  * @param  ParametersTable  Pointer to parameter values table.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DSI_Read(DSI_HandleTypeDef *hdsi,
+                               uint32_t ChannelNbr,
+                               uint8_t *Array,
+                               uint32_t Size,
+                               uint32_t Mode,
+                               uint32_t DCSCmd,
+                               uint8_t *ParametersTable)
+{
+  uint32_t tickstart;
+  uint8_t *pdata = Array;
+  uint32_t datasize = Size;
+  uint32_t fifoword;
+  uint32_t nbbytes;
+  uint32_t count;
+
+  /* Process locked */
+  __HAL_LOCK(hdsi);
+
+  /* Check the parameters */
+  assert_param(IS_DSI_READ_PACKET_TYPE(Mode));
+
+  if (datasize > 2U)
+  {
+    /* set max return packet size */
+    if (DSI_ShortWrite(hdsi, ChannelNbr, DSI_MAX_RETURN_PKT_SIZE, ((datasize) & 0xFFU),
+                       (((datasize) >> 8U) & 0xFFU)) != HAL_OK)
+    {
+      /* Process Unlocked */
+      __HAL_UNLOCK(hdsi);
+
+      return HAL_ERROR;
+    }
+  }
+
+  /* Configure the packet to read command */
+  if (Mode == DSI_DCS_SHORT_PKT_READ)
+  {
+    DSI_ConfigPacketHeader(hdsi->Instance, ChannelNbr, Mode, DCSCmd, 0U);
+  }
+  else if (Mode == DSI_GEN_SHORT_PKT_READ_P0)
+  {
+    DSI_ConfigPacketHeader(hdsi->Instance, ChannelNbr, Mode, 0U, 0U);
+  }
+  else if (Mode == DSI_GEN_SHORT_PKT_READ_P1)
+  {
+    DSI_ConfigPacketHeader(hdsi->Instance, ChannelNbr, Mode, ParametersTable[0U], 0U);
+  }
+  else if (Mode == DSI_GEN_SHORT_PKT_READ_P2)
+  {
+    DSI_ConfigPacketHeader(hdsi->Instance, ChannelNbr, Mode, ParametersTable[0U], ParametersTable[1U]);
+  }
+  else
+  {
+    /* Process Unlocked */
+    __HAL_UNLOCK(hdsi);
+
+    return HAL_ERROR;
+  }
+
+  /* Get tick */
+  tickstart = HAL_GetTick();
+
+  /* If DSI fifo is not empty, read requested bytes */
+  while (((int32_t)(datasize)) > 0)
+  {
+    if ((hdsi->Instance->GPSR & DSI_GPSR_PRDFE) == 0U)
+    {
+      fifoword = hdsi->Instance->GPDR;
+      nbbytes = (datasize < 4U) ? datasize : 4U;
+
+      for (count = 0U; count < nbbytes; count++)
+      {
+        *pdata = (uint8_t)(fifoword >> (8U * count));
+        pdata++;
+        datasize--;
+      }
+    }
+
+    /* Check for the Timeout */
+    if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE)
+    {
+      /* Process Unlocked */
+      __HAL_UNLOCK(hdsi);
+
+      return HAL_TIMEOUT;
+    }
+
+    /* Software workaround to avoid HAL_TIMEOUT when a DSI read command is   */
+    /* issued to the panel and the read data is not captured by the DSI Host */
+    /* which returns Packet Size Error.                                      */
+    /* Need to ensure that the Read command has finished before checking PSE */
+    if ((hdsi->Instance->GPSR & DSI_GPSR_RCB) == 0U)
+    {
+      if ((hdsi->Instance->ISR[1U] & DSI_ISR1_PSE) == DSI_ISR1_PSE)
+      {
+        /* Process Unlocked */
+        __HAL_UNLOCK(hdsi);
+
+        return HAL_ERROR;
+      }
+    }
+  }
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hdsi);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Enter the ULPM (Ultra Low Power Mode) with the D-PHY PLL running
+  *         (only data lanes are in ULPM)
+  * @param  hdsi  pointer to a DSI_HandleTypeDef structure that contains
+  *               the configuration information for the DSI.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DSI_EnterULPMData(DSI_HandleTypeDef *hdsi)
+{
+  uint32_t tickstart;
+
+  /* Process locked */
+  __HAL_LOCK(hdsi);
+
+  /* ULPS Request on Data Lanes */
+  hdsi->Instance->PUCR |= DSI_PUCR_URDL;
+
+  /* Get tick */
+  tickstart = HAL_GetTick();
+
+  /* Wait until the D-PHY active lanes enter into ULPM */
+  if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE)
+  {
+    while ((hdsi->Instance->PSR & DSI_PSR_UAN0) != 0U)
+    {
+      /* Check for the Timeout */
+      if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE)
+      {
+        /* Process Unlocked */
+        __HAL_UNLOCK(hdsi);
+
+        return HAL_TIMEOUT;
+      }
+    }
+  }
+  else if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_TWO_DATA_LANES)
+  {
+    while ((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UAN1)) != 0U)
+    {
+      /* Check for the Timeout */
+      if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE)
+      {
+        /* Process Unlocked */
+        __HAL_UNLOCK(hdsi);
+
+        return HAL_TIMEOUT;
+      }
+    }
+  }
+  else
+  {
+    /* Process unlocked */
+    __HAL_UNLOCK(hdsi);
+
+    return HAL_ERROR;
+  }
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hdsi);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Exit the ULPM (Ultra Low Power Mode) with the D-PHY PLL running
+  *         (only data lanes are in ULPM)
+  * @param  hdsi  pointer to a DSI_HandleTypeDef structure that contains
+  *               the configuration information for the DSI.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DSI_ExitULPMData(DSI_HandleTypeDef *hdsi)
+{
+  uint32_t tickstart;
+
+  /* Process locked */
+  __HAL_LOCK(hdsi);
+
+  /* Exit ULPS on Data Lanes */
+  hdsi->Instance->PUCR |= DSI_PUCR_UEDL;
+
+  /* Get tick */
+  tickstart = HAL_GetTick();
+
+  /* Wait until all active lanes exit ULPM */
+  if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE)
+  {
+    while ((hdsi->Instance->PSR & DSI_PSR_UAN0) != DSI_PSR_UAN0)
+    {
+      /* Check for the Timeout */
+      if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE)
+      {
+        /* Process Unlocked */
+        __HAL_UNLOCK(hdsi);
+
+        return HAL_TIMEOUT;
+      }
+    }
+  }
+  else if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_TWO_DATA_LANES)
+  {
+    while ((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UAN1)) != (DSI_PSR_UAN0 | DSI_PSR_UAN1))
+    {
+      /* Check for the Timeout */
+      if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE)
+      {
+        /* Process Unlocked */
+        __HAL_UNLOCK(hdsi);
+
+        return HAL_TIMEOUT;
+      }
+    }
+  }
+  else
+  {
+    /* Process unlocked */
+    __HAL_UNLOCK(hdsi);
+
+    return HAL_ERROR;
+  }
+
+  /* wait for 1 ms*/
+  HAL_Delay(1U);
+
+  /* De-assert the ULPM requests and the ULPM exit bits */
+  hdsi->Instance->PUCR = 0U;
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hdsi);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Enter the ULPM (Ultra Low Power Mode) with the D-PHY PLL turned off
+  *         (both data and clock lanes are in ULPM)
+  * @param  hdsi  pointer to a DSI_HandleTypeDef structure that contains
+  *               the configuration information for the DSI.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DSI_EnterULPM(DSI_HandleTypeDef *hdsi)
+{
+  uint32_t tickstart;
+
+  /* Process locked */
+  __HAL_LOCK(hdsi);
+
+  /* Clock lane configuration: no more HS request */
+  hdsi->Instance->CLCR &= ~DSI_CLCR_DPCC;
+
+  /* Use system PLL as byte lane clock source before stopping DSIPHY clock source */
+  __HAL_RCC_DSI_CONFIG(RCC_DSICLKSOURCE_PLLR);
+
+  /* ULPS Request on Clock and Data Lanes */
+  hdsi->Instance->PUCR |= (DSI_PUCR_URCL | DSI_PUCR_URDL);
+
+  /* Get tick */
+  tickstart = HAL_GetTick();
+
+  /* Wait until all active lanes exit ULPM */
+  if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE)
+  {
+    while ((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UANC)) != 0U)
+    {
+      /* Check for the Timeout */
+      if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE)
+      {
+        /* Process Unlocked */
+        __HAL_UNLOCK(hdsi);
+
+        return HAL_TIMEOUT;
+      }
+    }
+  }
+  else if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_TWO_DATA_LANES)
+  {
+    while ((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UAN1 | DSI_PSR_UANC)) != 0U)
+    {
+      /* Check for the Timeout */
+      if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE)
+      {
+        /* Process Unlocked */
+        __HAL_UNLOCK(hdsi);
+
+        return HAL_TIMEOUT;
+      }
+    }
+  }
+  else
+  {
+    /* Process unlocked */
+    __HAL_UNLOCK(hdsi);
+
+    return HAL_ERROR;
+  }
+
+  /* Turn off the DSI PLL */
+  __HAL_DSI_PLL_DISABLE(hdsi);
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hdsi);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Exit the ULPM (Ultra Low Power Mode) with the D-PHY PLL turned off
+  *         (both data and clock lanes are in ULPM)
+  * @param  hdsi  pointer to a DSI_HandleTypeDef structure that contains
+  *               the configuration information for the DSI.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DSI_ExitULPM(DSI_HandleTypeDef *hdsi)
+{
+  uint32_t tickstart;
+
+  /* Process locked */
+  __HAL_LOCK(hdsi);
+
+  /* Turn on the DSI PLL */
+  __HAL_DSI_PLL_ENABLE(hdsi);
+
+  /* Get tick */
+  tickstart = HAL_GetTick();
+
+  /* Wait for the lock of the PLL */
+  while (__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_PLLLS) == 0U)
+  {
+    /* Check for the Timeout */
+    if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE)
+    {
+      /* Process Unlocked */
+      __HAL_UNLOCK(hdsi);
+
+      return HAL_TIMEOUT;
+    }
+  }
+
+  /* Exit ULPS on Clock and Data Lanes */
+  hdsi->Instance->PUCR |= (DSI_PUCR_UECL | DSI_PUCR_UEDL);
+
+  /* Get tick */
+  tickstart = HAL_GetTick();
+
+  /* Wait until all active lanes exit ULPM */
+  if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE)
+  {
+    while ((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UANC)) != (DSI_PSR_UAN0 | DSI_PSR_UANC))
+    {
+      /* Check for the Timeout */
+      if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE)
+      {
+        /* Process Unlocked */
+        __HAL_UNLOCK(hdsi);
+
+        return HAL_TIMEOUT;
+      }
+    }
+  }
+  else if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_TWO_DATA_LANES)
+  {
+    while ((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UAN1 | DSI_PSR_UANC)) != (DSI_PSR_UAN0 | DSI_PSR_UAN1 |
+                                                                                    DSI_PSR_UANC))
+    {
+      /* Check for the Timeout */
+      if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE)
+      {
+        /* Process Unlocked */
+        __HAL_UNLOCK(hdsi);
+
+        return HAL_TIMEOUT;
+      }
+    }
+  }
+  else
+  {
+    /* Process unlocked */
+    __HAL_UNLOCK(hdsi);
+
+    return HAL_ERROR;
+  }
+
+  /* wait for 1 ms */
+  HAL_Delay(1U);
+
+  /* De-assert the ULPM requests and the ULPM exit bits */
+  hdsi->Instance->PUCR = 0U;
+
+  /* Switch the lane byte clock source in the RCC from system PLL to D-PHY */
+  __HAL_RCC_DSI_CONFIG(RCC_DSICLKSOURCE_DSIPHY);
+
+  /* Restore clock lane configuration to HS */
+  hdsi->Instance->CLCR |= DSI_CLCR_DPCC;
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hdsi);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Start test pattern generation
+  * @param  hdsi  pointer to a DSI_HandleTypeDef structure that contains
+  *               the configuration information for the DSI.
+  * @param  Mode  Pattern generator mode
+  *          This parameter can be one of the following values:
+  *           0 : Color bars (horizontal or vertical)
+  *           1 : BER pattern (vertical only)
+  * @param  Orientation  Pattern generator orientation
+  *          This parameter can be one of the following values:
+  *           0 : Vertical color bars
+  *           1 : Horizontal color bars
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DSI_PatternGeneratorStart(DSI_HandleTypeDef *hdsi, uint32_t Mode, uint32_t Orientation)
+{
+  /* Process locked */
+  __HAL_LOCK(hdsi);
+
+  /* Configure pattern generator mode and orientation */
+  hdsi->Instance->VMCR &= ~(DSI_VMCR_PGM | DSI_VMCR_PGO);
+  hdsi->Instance->VMCR |= ((Mode << 20U) | (Orientation << 24U));
+
+  /* Enable pattern generator by setting PGE bit */
+  hdsi->Instance->VMCR |= DSI_VMCR_PGE;
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hdsi);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stop test pattern generation
+  * @param  hdsi  pointer to a DSI_HandleTypeDef structure that contains
+  *               the configuration information for the DSI.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DSI_PatternGeneratorStop(DSI_HandleTypeDef *hdsi)
+{
+  /* Process locked */
+  __HAL_LOCK(hdsi);
+
+  /* Disable pattern generator by clearing PGE bit */
+  hdsi->Instance->VMCR &= ~DSI_VMCR_PGE;
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hdsi);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Set Slew-Rate And Delay Tuning
+  * @param  hdsi  pointer to a DSI_HandleTypeDef structure that contains
+  *               the configuration information for the DSI.
+  * @param  CommDelay  Communication delay to be adjusted.
+  *                    This parameter can be any value of @arg DSI_Communication_Delay
+  * @param  Lane  select between clock or data lanes.
+  *               This parameter can be any value of @arg DSI_Lane_Group
+  * @param  Value  Custom value of the slew-rate or delay
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DSI_SetSlewRateAndDelayTuning(DSI_HandleTypeDef *hdsi, uint32_t CommDelay, uint32_t Lane,
+                                                    uint32_t Value)
+{
+  /* Process locked */
+  __HAL_LOCK(hdsi);
+
+  /* Check function parameters */
+  assert_param(IS_DSI_COMMUNICATION_DELAY(CommDelay));
+  assert_param(IS_DSI_LANE_GROUP(Lane));
+
+  switch (CommDelay)
+  {
+    case DSI_SLEW_RATE_HSTX:
+      if (Lane == DSI_CLOCK_LANE)
+      {
+        /* High-Speed Transmission Slew Rate Control on Clock Lane */
+        hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_HSTXSRCCL;
+        hdsi->Instance->WPCR[1U] |= Value << 16U;
+      }
+      else if (Lane == DSI_DATA_LANES)
+      {
+        /* High-Speed Transmission Slew Rate Control on Data Lanes */
+        hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_HSTXSRCDL;
+        hdsi->Instance->WPCR[1U] |= Value << 18U;
+      }
+      else
+      {
+        /* Process unlocked */
+        __HAL_UNLOCK(hdsi);
+
+        return HAL_ERROR;
+      }
+      break;
+    case DSI_SLEW_RATE_LPTX:
+      if (Lane == DSI_CLOCK_LANE)
+      {
+        /* Low-Power transmission Slew Rate Compensation on Clock Lane */
+        hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_LPSRCCL;
+        hdsi->Instance->WPCR[1U] |= Value << 6U;
+      }
+      else if (Lane == DSI_DATA_LANES)
+      {
+        /* Low-Power transmission Slew Rate Compensation on Data Lanes */
+        hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_LPSRCDL;
+        hdsi->Instance->WPCR[1U] |= Value << 8U;
+      }
+      else
+      {
+        /* Process unlocked */
+        __HAL_UNLOCK(hdsi);
+
+        return HAL_ERROR;
+      }
+      break;
+    case DSI_HS_DELAY:
+      if (Lane == DSI_CLOCK_LANE)
+      {
+        /* High-Speed Transmission Delay on Clock Lane */
+        hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_HSTXDCL;
+        hdsi->Instance->WPCR[1U] |= Value;
+      }
+      else if (Lane == DSI_DATA_LANES)
+      {
+        /* High-Speed Transmission Delay on Data Lanes */
+        hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_HSTXDDL;
+        hdsi->Instance->WPCR[1U] |= Value << 2U;
+      }
+      else
+      {
+        /* Process unlocked */
+        __HAL_UNLOCK(hdsi);
+
+        return HAL_ERROR;
+      }
+      break;
+    default:
+      break;
+  }
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hdsi);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Low-Power Reception Filter Tuning
+  * @param  hdsi  pointer to a DSI_HandleTypeDef structure that contains
+  *               the configuration information for the DSI.
+  * @param  Frequency  cutoff frequency of low-pass filter at the input of LPRX
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DSI_SetLowPowerRXFilter(DSI_HandleTypeDef *hdsi, uint32_t Frequency)
+{
+  /* Process locked */
+  __HAL_LOCK(hdsi);
+
+  /* Low-Power RX low-pass Filtering Tuning */
+  hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_LPRXFT;
+  hdsi->Instance->WPCR[1U] |= Frequency << 25U;
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hdsi);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Activate an additional current path on all lanes to meet the SDDTx parameter
+  *         defined in the MIPI D-PHY specification
+  * @param  hdsi  pointer to a DSI_HandleTypeDef structure that contains
+  *               the configuration information for the DSI.
+  * @param  State  ENABLE or DISABLE
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DSI_SetSDD(DSI_HandleTypeDef *hdsi, FunctionalState State)
+{
+  /* Process locked */
+  __HAL_LOCK(hdsi);
+
+  /* Check function parameters */
+  assert_param(IS_FUNCTIONAL_STATE(State));
+
+  /* Activate/Disactivate additional current path on all lanes */
+  hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_SDDC;
+  hdsi->Instance->WPCR[1U] |= ((uint32_t)State << 12U);
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hdsi);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Custom lane pins configuration
+  * @param  hdsi  pointer to a DSI_HandleTypeDef structure that contains
+  *               the configuration information for the DSI.
+  * @param  CustomLane  Function to be applied on selected lane.
+  *                     This parameter can be any value of @arg DSI_CustomLane
+  * @param  Lane  select between clock or data lane 0 or data lane 1.
+  *               This parameter can be any value of @arg DSI_Lane_Select
+  * @param  State  ENABLE or DISABLE
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DSI_SetLanePinsConfiguration(DSI_HandleTypeDef *hdsi, uint32_t CustomLane, uint32_t Lane,
+                                                   FunctionalState State)
+{
+  /* Process locked */
+  __HAL_LOCK(hdsi);
+
+  /* Check function parameters */
+  assert_param(IS_DSI_CUSTOM_LANE(CustomLane));
+  assert_param(IS_DSI_LANE(Lane));
+  assert_param(IS_FUNCTIONAL_STATE(State));
+
+  switch (CustomLane)
+  {
+    case DSI_SWAP_LANE_PINS:
+      if (Lane == DSI_CLK_LANE)
+      {
+        /* Swap pins on clock lane */
+        hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_SWCL;
+        hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 6U);
+      }
+      else if (Lane == DSI_DATA_LANE0)
+      {
+        /* Swap pins on data lane 0 */
+        hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_SWDL0;
+        hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 7U);
+      }
+      else if (Lane == DSI_DATA_LANE1)
+      {
+        /* Swap pins on data lane 1 */
+        hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_SWDL1;
+        hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 8U);
+      }
+      else
+      {
+        /* Process unlocked */
+        __HAL_UNLOCK(hdsi);
+
+        return HAL_ERROR;
+      }
+      break;
+    case DSI_INVERT_HS_SIGNAL:
+      if (Lane == DSI_CLK_LANE)
+      {
+        /* Invert HS signal on clock lane */
+        hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_HSICL;
+        hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 9U);
+      }
+      else if (Lane == DSI_DATA_LANE0)
+      {
+        /* Invert HS signal on data lane 0 */
+        hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_HSIDL0;
+        hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 10U);
+      }
+      else if (Lane == DSI_DATA_LANE1)
+      {
+        /* Invert HS signal on data lane 1 */
+        hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_HSIDL1;
+        hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 11U);
+      }
+      else
+      {
+        /* Process unlocked */
+        __HAL_UNLOCK(hdsi);
+
+        return HAL_ERROR;
+      }
+      break;
+    default:
+      break;
+  }
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hdsi);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Set custom timing for the PHY
+  * @param  hdsi  pointer to a DSI_HandleTypeDef structure that contains
+  *               the configuration information for the DSI.
+  * @param  Timing  PHY timing to be adjusted.
+  *                 This parameter can be any value of @arg DSI_PHY_Timing
+  * @param  State  ENABLE or DISABLE
+  * @param  Value  Custom value of the timing
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DSI_SetPHYTimings(DSI_HandleTypeDef *hdsi, uint32_t Timing, FunctionalState State, uint32_t Value)
+{
+  /* Process locked */
+  __HAL_LOCK(hdsi);
+
+  /* Check function parameters */
+  assert_param(IS_DSI_PHY_TIMING(Timing));
+  assert_param(IS_FUNCTIONAL_STATE(State));
+
+  switch (Timing)
+  {
+    case DSI_TCLK_POST:
+      /* Enable/Disable custom timing setting */
+      hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_TCLKPOSTEN;
+      hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 27U);
+
+      if (State != DISABLE)
+      {
+        /* Set custom value */
+        hdsi->Instance->WPCR[4U] &= ~DSI_WPCR4_TCLKPOST;
+        hdsi->Instance->WPCR[4U] |= Value & DSI_WPCR4_TCLKPOST;
+      }
+
+      break;
+    case DSI_TLPX_CLK:
+      /* Enable/Disable custom timing setting */
+      hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_TLPXCEN;
+      hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 26U);
+
+      if (State != DISABLE)
+      {
+        /* Set custom value */
+        hdsi->Instance->WPCR[3U] &= ~DSI_WPCR3_TLPXC;
+        hdsi->Instance->WPCR[3U] |= (Value << 24U) & DSI_WPCR3_TLPXC;
+      }
+
+      break;
+    case DSI_THS_EXIT:
+      /* Enable/Disable custom timing setting */
+      hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_THSEXITEN;
+      hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 25U);
+
+      if (State != DISABLE)
+      {
+        /* Set custom value */
+        hdsi->Instance->WPCR[3U] &= ~DSI_WPCR3_THSEXIT;
+        hdsi->Instance->WPCR[3U] |= (Value << 16U) & DSI_WPCR3_THSEXIT;
+      }
+
+      break;
+    case DSI_TLPX_DATA:
+      /* Enable/Disable custom timing setting */
+      hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_TLPXDEN;
+      hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 24U);
+
+      if (State != DISABLE)
+      {
+        /* Set custom value */
+        hdsi->Instance->WPCR[3U] &= ~DSI_WPCR3_TLPXD;
+        hdsi->Instance->WPCR[3U] |= (Value << 8U) & DSI_WPCR3_TLPXD;
+      }
+
+      break;
+    case DSI_THS_ZERO:
+      /* Enable/Disable custom timing setting */
+      hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_THSZEROEN;
+      hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 23U);
+
+      if (State != DISABLE)
+      {
+        /* Set custom value */
+        hdsi->Instance->WPCR[3U] &= ~DSI_WPCR3_THSZERO;
+        hdsi->Instance->WPCR[3U] |= Value & DSI_WPCR3_THSZERO;
+      }
+
+      break;
+    case DSI_THS_TRAIL:
+      /* Enable/Disable custom timing setting */
+      hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_THSTRAILEN;
+      hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 22U);
+
+      if (State != DISABLE)
+      {
+        /* Set custom value */
+        hdsi->Instance->WPCR[2U] &= ~DSI_WPCR2_THSTRAIL;
+        hdsi->Instance->WPCR[2U] |= (Value << 24U) & DSI_WPCR2_THSTRAIL;
+      }
+
+      break;
+    case DSI_THS_PREPARE:
+      /* Enable/Disable custom timing setting */
+      hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_THSPREPEN;
+      hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 21U);
+
+      if (State != DISABLE)
+      {
+        /* Set custom value */
+        hdsi->Instance->WPCR[2U] &= ~DSI_WPCR2_THSPREP;
+        hdsi->Instance->WPCR[2U] |= (Value << 16U) & DSI_WPCR2_THSPREP;
+      }
+
+      break;
+    case DSI_TCLK_ZERO:
+      /* Enable/Disable custom timing setting */
+      hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_TCLKZEROEN;
+      hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 20U);
+
+      if (State != DISABLE)
+      {
+        /* Set custom value */
+        hdsi->Instance->WPCR[2U] &= ~DSI_WPCR2_TCLKZERO;
+        hdsi->Instance->WPCR[2U] |= (Value << 8U) & DSI_WPCR2_TCLKZERO;
+      }
+
+      break;
+    case DSI_TCLK_PREPARE:
+      /* Enable/Disable custom timing setting */
+      hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_TCLKPREPEN;
+      hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 19U);
+
+      if (State != DISABLE)
+      {
+        /* Set custom value */
+        hdsi->Instance->WPCR[2U] &= ~DSI_WPCR2_TCLKPREP;
+        hdsi->Instance->WPCR[2U] |= Value & DSI_WPCR2_TCLKPREP;
+      }
+
+      break;
+    default:
+      break;
+  }
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hdsi);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Force the Clock/Data Lane in TX Stop Mode
+  * @param  hdsi  pointer to a DSI_HandleTypeDef structure that contains
+  *               the configuration information for the DSI.
+  * @param  Lane  select between clock or data lanes.
+  *               This parameter can be any value of @arg DSI_Lane_Group
+  * @param  State  ENABLE or DISABLE
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DSI_ForceTXStopMode(DSI_HandleTypeDef *hdsi, uint32_t Lane, FunctionalState State)
+{
+  /* Process locked */
+  __HAL_LOCK(hdsi);
+
+  /* Check function parameters */
+  assert_param(IS_DSI_LANE_GROUP(Lane));
+  assert_param(IS_FUNCTIONAL_STATE(State));
+
+  if (Lane == DSI_CLOCK_LANE)
+  {
+    /* Force/Unforce the Clock Lane in TX Stop Mode */
+    hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_FTXSMCL;
+    hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 12U);
+  }
+  else if (Lane == DSI_DATA_LANES)
+  {
+    /* Force/Unforce the Data Lanes in TX Stop Mode */
+    hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_FTXSMDL;
+    hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 13U);
+  }
+  else
+  {
+    /* Process unlocked */
+    __HAL_UNLOCK(hdsi);
+
+    return HAL_ERROR;
+  }
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hdsi);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Force LP Receiver in Low-Power Mode
+  * @param  hdsi  pointer to a DSI_HandleTypeDef structure that contains
+  *               the configuration information for the DSI.
+  * @param  State  ENABLE or DISABLE
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DSI_ForceRXLowPower(DSI_HandleTypeDef *hdsi, FunctionalState State)
+{
+  /* Process locked */
+  __HAL_LOCK(hdsi);
+
+  /* Check function parameters */
+  assert_param(IS_FUNCTIONAL_STATE(State));
+
+  /* Force/Unforce LP Receiver in Low-Power Mode */
+  hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_FLPRXLPM;
+  hdsi->Instance->WPCR[1U] |= ((uint32_t)State << 22U);
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hdsi);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Force Data Lanes in RX Mode after a BTA
+  * @param  hdsi  pointer to a DSI_HandleTypeDef structure that contains
+  *               the configuration information for the DSI.
+  * @param  State  ENABLE or DISABLE
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DSI_ForceDataLanesInRX(DSI_HandleTypeDef *hdsi, FunctionalState State)
+{
+  /* Process locked */
+  __HAL_LOCK(hdsi);
+
+  /* Check function parameters */
+  assert_param(IS_FUNCTIONAL_STATE(State));
+
+  /* Force Data Lanes in RX Mode */
+  hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_TDDL;
+  hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 16U);
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hdsi);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Enable a pull-down on the lanes to prevent from floating states when unused
+  * @param  hdsi  pointer to a DSI_HandleTypeDef structure that contains
+  *               the configuration information for the DSI.
+  * @param  State  ENABLE or DISABLE
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DSI_SetPullDown(DSI_HandleTypeDef *hdsi, FunctionalState State)
+{
+  /* Process locked */
+  __HAL_LOCK(hdsi);
+
+  /* Check function parameters */
+  assert_param(IS_FUNCTIONAL_STATE(State));
+
+  /* Enable/Disable pull-down on lanes */
+  hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_PDEN;
+  hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 18U);
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hdsi);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Switch off the contention detection on data lanes
+  * @param  hdsi  pointer to a DSI_HandleTypeDef structure that contains
+  *               the configuration information for the DSI.
+  * @param  State  ENABLE or DISABLE
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DSI_SetContentionDetectionOff(DSI_HandleTypeDef *hdsi, FunctionalState State)
+{
+  /* Process locked */
+  __HAL_LOCK(hdsi);
+
+  /* Check function parameters */
+  assert_param(IS_FUNCTIONAL_STATE(State));
+
+  /* Contention Detection on Data Lanes OFF */
+  hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_CDOFFDL;
+  hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 14U);
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hdsi);
+
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup DSI_Group4 Peripheral State and Errors functions
+  *  @brief    Peripheral State and Errors functions
+  *
+@verbatim
+ ===============================================================================
+                  ##### Peripheral State and Errors functions #####
+ ===============================================================================
+    [..]
+    This subsection provides functions allowing to
+      (+) Check the DSI state.
+      (+) Get error code.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Return the DSI state
+  * @param  hdsi  pointer to a DSI_HandleTypeDef structure that contains
+  *               the configuration information for the DSI.
+  * @retval HAL state
+  */
+HAL_DSI_StateTypeDef HAL_DSI_GetState(DSI_HandleTypeDef *hdsi)
+{
+  return hdsi->State;
+}
+
+/**
+  * @brief  Return the DSI error code
+  * @param  hdsi  pointer to a DSI_HandleTypeDef structure that contains
+  *               the configuration information for the DSI.
+  * @retval DSI Error Code
+  */
+uint32_t HAL_DSI_GetError(DSI_HandleTypeDef *hdsi)
+{
+  /* Get the error code */
+  return hdsi->ErrorCode;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* DSI */
+
+#endif /* HAL_DSI_MODULE_ENABLED */
+
+/**
+  * @}
+  */
diff --git a/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c
new file mode 100644
index 0000000..f0eff70
--- /dev/null
+++ b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c
@@ -0,0 +1,547 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hal_exti.c
+  * @author  MCD Application Team
+  * @brief   EXTI HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the Extended Interrupts and events controller (EXTI) peripheral:
+  *           + Initialization and de-initialization functions
+  *           + IO operation functions
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2018 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  @verbatim
+  ==============================================================================
+                    ##### EXTI Peripheral features #####
+  ==============================================================================
+  [..]
+    (+) Each Exti line can be configured within this driver.
+
+    (+) Exti line can be configured in 3 different modes
+        (++) Interrupt
+        (++) Event
+        (++) Both of them
+
+    (+) Configurable Exti lines can be configured with 3 different triggers
+        (++) Rising
+        (++) Falling
+        (++) Both of them
+
+    (+) When set in interrupt mode, configurable Exti lines have two different
+        interrupts pending registers which allow to distinguish which transition
+        occurs:
+        (++) Rising edge pending interrupt
+        (++) Falling
+
+    (+) Exti lines 0 to 15 are linked to gpio pin number 0 to 15. Gpio port can
+        be selected through multiplexer.
+
+                     ##### How to use this driver #####
+  ==============================================================================
+  [..]
+
+    (#) Configure the EXTI line using HAL_EXTI_SetConfigLine().
+        (++) Choose the interrupt line number by setting "Line" member from
+             EXTI_ConfigTypeDef structure.
+        (++) Configure the interrupt and/or event mode using "Mode" member from
+             EXTI_ConfigTypeDef structure.
+        (++) For configurable lines, configure rising and/or falling trigger
+             "Trigger" member from EXTI_ConfigTypeDef structure.
+        (++) For Exti lines linked to gpio, choose gpio port using "GPIOSel"
+             member from GPIO_InitTypeDef structure.
+
+    (#) Get current Exti configuration of a dedicated line using
+        HAL_EXTI_GetConfigLine().
+        (++) Provide exiting handle as parameter.
+        (++) Provide pointer on EXTI_ConfigTypeDef structure as second parameter.
+
+    (#) Clear Exti configuration of a dedicated line using HAL_EXTI_GetConfigLine().
+        (++) Provide exiting handle as parameter.
+
+    (#) Register callback to treat Exti interrupts using HAL_EXTI_RegisterCallback().
+        (++) Provide exiting handle as first parameter.
+        (++) Provide which callback will be registered using one value from
+             EXTI_CallbackIDTypeDef.
+        (++) Provide callback function pointer.
+
+    (#) Get interrupt pending bit using HAL_EXTI_GetPending().
+
+    (#) Clear interrupt pending bit using HAL_EXTI_GetPending().
+
+    (#) Generate software interrupt using HAL_EXTI_GenerateSWI().
+
+  @endverbatim
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup EXTI
+  * @{
+  */
+/** MISRA C:2012 deviation rule has been granted for following rule:
+  * Rule-18.1_b - Medium: Array `EXTICR' 1st subscript interval [0,7] may be out
+  * of bounds [0,3] in following API :
+  * HAL_EXTI_SetConfigLine
+  * HAL_EXTI_GetConfigLine
+  * HAL_EXTI_ClearConfigLine
+  */
+
+#ifdef HAL_EXTI_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private defines -----------------------------------------------------------*/
+/** @defgroup EXTI_Private_Constants EXTI Private Constants
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @addtogroup EXTI_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup EXTI_Exported_Functions_Group1
+  *  @brief    Configuration functions
+  *
+@verbatim
+ ===============================================================================
+              ##### Configuration functions #####
+ ===============================================================================
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Set configuration of a dedicated Exti line.
+  * @param  hexti Exti handle.
+  * @param  pExtiConfig Pointer on EXTI configuration to be set.
+  * @retval HAL Status.
+  */
+HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig)
+{
+  uint32_t regval;
+  uint32_t linepos;
+  uint32_t maskline;
+
+  /* Check null pointer */
+  if ((hexti == NULL) || (pExtiConfig == NULL))
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check parameters */
+  assert_param(IS_EXTI_LINE(pExtiConfig->Line));
+  assert_param(IS_EXTI_MODE(pExtiConfig->Mode));
+
+  /* Assign line number to handle */
+  hexti->Line = pExtiConfig->Line;
+
+  /* Compute line mask */
+  linepos = (pExtiConfig->Line & EXTI_PIN_MASK);
+  maskline = (1uL << linepos);
+
+  /* Configure triggers for configurable lines */
+  if ((pExtiConfig->Line & EXTI_CONFIG) != 0x00u)
+  {
+    assert_param(IS_EXTI_TRIGGER(pExtiConfig->Trigger));
+
+    /* Configure rising trigger */
+    /* Mask or set line */
+    if ((pExtiConfig->Trigger & EXTI_TRIGGER_RISING) != 0x00u)
+    {
+      EXTI->RTSR |= maskline;
+    }
+    else
+    {
+      EXTI->RTSR &= ~maskline;
+    }
+
+    /* Configure falling trigger */
+    /* Mask or set line */
+    if ((pExtiConfig->Trigger & EXTI_TRIGGER_FALLING) != 0x00u)
+    {
+      EXTI->FTSR |= maskline;
+    }
+    else
+    {
+      EXTI->FTSR &= ~maskline;
+    }
+
+
+    /* Configure gpio port selection in case of gpio exti line */
+    if ((pExtiConfig->Line & EXTI_GPIO) == EXTI_GPIO)
+    {
+      assert_param(IS_EXTI_GPIO_PORT(pExtiConfig->GPIOSel));
+      assert_param(IS_EXTI_GPIO_PIN(linepos));
+
+      regval = SYSCFG->EXTICR[linepos >> 2u];
+      regval &= ~(SYSCFG_EXTICR1_EXTI0 << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u)));
+      regval |= (pExtiConfig->GPIOSel << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u)));
+      SYSCFG->EXTICR[linepos >> 2u] = regval;
+    }
+  }
+
+  /* Configure interrupt mode : read current mode */
+  /* Mask or set line */
+  if ((pExtiConfig->Mode & EXTI_MODE_INTERRUPT) != 0x00u)
+  {
+    EXTI->IMR |= maskline;
+  }
+  else
+  {
+    EXTI->IMR &= ~maskline;
+  }
+
+  /* Configure event mode : read current mode */
+  /* Mask or set line */
+  if ((pExtiConfig->Mode & EXTI_MODE_EVENT) != 0x00u)
+  {
+    EXTI->EMR |= maskline;
+  }
+  else
+  {
+    EXTI->EMR &= ~maskline;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Get configuration of a dedicated Exti line.
+  * @param  hexti Exti handle.
+  * @param  pExtiConfig Pointer on structure to store Exti configuration.
+  * @retval HAL Status.
+  */
+HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig)
+{
+  uint32_t regval;
+  uint32_t linepos;
+  uint32_t maskline;
+
+  /* Check null pointer */
+  if ((hexti == NULL) || (pExtiConfig == NULL))
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameter */
+  assert_param(IS_EXTI_LINE(hexti->Line));
+
+  /* Store handle line number to configuration structure */
+  pExtiConfig->Line = hexti->Line;
+
+  /* Compute line mask */
+  linepos = (pExtiConfig->Line & EXTI_PIN_MASK);
+  maskline = (1uL << linepos);
+
+  /* 1] Get core mode : interrupt */
+
+  /* Check if selected line is enable */
+  if ((EXTI->IMR & maskline) != 0x00u)
+  {
+    pExtiConfig->Mode = EXTI_MODE_INTERRUPT;
+  }
+  else
+  {
+    pExtiConfig->Mode = EXTI_MODE_NONE;
+  }
+
+  /* Get event mode */
+  /* Check if selected line is enable */
+  if ((EXTI->EMR & maskline) != 0x00u)
+  {
+    pExtiConfig->Mode |= EXTI_MODE_EVENT;
+  }
+
+  /* Get default Trigger and GPIOSel configuration */
+  pExtiConfig->Trigger = EXTI_TRIGGER_NONE;
+  pExtiConfig->GPIOSel = 0x00u;
+
+  /* 2] Get trigger for configurable lines : rising */
+  if ((pExtiConfig->Line & EXTI_CONFIG) != 0x00u)
+  {
+    /* Check if configuration of selected line is enable */
+    if ((EXTI->RTSR & maskline) != 0x00u)
+    {
+      pExtiConfig->Trigger = EXTI_TRIGGER_RISING;
+    }
+
+    /* Get falling configuration */
+    /* Check if configuration of selected line is enable */
+    if ((EXTI->FTSR & maskline) != 0x00u)
+    {
+      pExtiConfig->Trigger |= EXTI_TRIGGER_FALLING;
+    }
+
+    /* Get Gpio port selection for gpio lines */
+    if ((pExtiConfig->Line & EXTI_GPIO) == EXTI_GPIO)
+    {
+      assert_param(IS_EXTI_GPIO_PIN(linepos));
+
+      regval = (SYSCFG->EXTICR[linepos >> 2u] << 16u );
+      pExtiConfig->GPIOSel = ((regval << (SYSCFG_EXTICR1_EXTI1_Pos * (3uL - (linepos & 0x03u)))) >> 28u);
+    }
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Clear whole configuration of a dedicated Exti line.
+  * @param  hexti Exti handle.
+  * @retval HAL Status.
+  */
+HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(EXTI_HandleTypeDef *hexti)
+{
+  uint32_t regval;
+  uint32_t linepos;
+  uint32_t maskline;
+
+  /* Check null pointer */
+  if (hexti == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameter */
+  assert_param(IS_EXTI_LINE(hexti->Line));
+
+  /* compute line mask */
+  linepos = (hexti->Line & EXTI_PIN_MASK);
+  maskline = (1uL << linepos);
+
+  /* 1] Clear interrupt mode */
+  EXTI->IMR = (EXTI->IMR & ~maskline);
+
+  /* 2] Clear event mode */
+  EXTI->EMR = (EXTI->EMR & ~maskline);
+
+  /* 3] Clear triggers in case of configurable lines */
+  if ((hexti->Line & EXTI_CONFIG) != 0x00u)
+  {
+    EXTI->RTSR = (EXTI->RTSR & ~maskline);
+    EXTI->FTSR = (EXTI->FTSR & ~maskline);
+
+    /* Get Gpio port selection for gpio lines */
+    if ((hexti->Line & EXTI_GPIO) == EXTI_GPIO)
+    {
+      assert_param(IS_EXTI_GPIO_PIN(linepos));
+
+      regval = SYSCFG->EXTICR[linepos >> 2u];
+      regval &= ~(SYSCFG_EXTICR1_EXTI0 << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u)));
+      SYSCFG->EXTICR[linepos >> 2u] = regval;
+    }
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Register callback for a dedicated Exti line.
+  * @param  hexti Exti handle.
+  * @param  CallbackID User callback identifier.
+  *         This parameter can be one of @arg @ref EXTI_CallbackIDTypeDef values.
+  * @param  pPendingCbfn function pointer to be stored as callback.
+  * @retval HAL Status.
+  */
+HAL_StatusTypeDef HAL_EXTI_RegisterCallback(EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef CallbackID, void (*pPendingCbfn)(void))
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  switch (CallbackID)
+  {
+    case  HAL_EXTI_COMMON_CB_ID:
+      hexti->PendingCallback = pPendingCbfn;
+      break;
+
+    default:
+      status = HAL_ERROR;
+      break;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Store line number as handle private field.
+  * @param  hexti Exti handle.
+  * @param  ExtiLine Exti line number.
+  *         This parameter can be from 0 to @ref EXTI_LINE_NB.
+  * @retval HAL Status.
+  */
+HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLine)
+{
+  /* Check the parameters */
+  assert_param(IS_EXTI_LINE(ExtiLine));
+
+  /* Check null pointer */
+  if (hexti == NULL)
+  {
+    return HAL_ERROR;
+  }
+  else
+  {
+    /* Store line number as handle private field */
+    hexti->Line = ExtiLine;
+
+    return HAL_OK;
+  }
+}
+
+/**
+  * @}
+  */
+
+/** @addtogroup EXTI_Exported_Functions_Group2
+  *  @brief EXTI IO functions.
+  *
+@verbatim
+ ===============================================================================
+                       ##### IO operation functions #####
+ ===============================================================================
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Handle EXTI interrupt request.
+  * @param  hexti Exti handle.
+  * @retval none.
+  */
+void HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *hexti)
+{
+  uint32_t regval;
+  uint32_t maskline;
+
+  /* Compute line mask */
+  maskline = (1uL << (hexti->Line & EXTI_PIN_MASK));
+
+  /* Get pending bit  */
+  regval = (EXTI->PR & maskline);
+  if (regval != 0x00u)
+  {
+    /* Clear pending bit */
+    EXTI->PR = maskline;
+
+    /* Call callback */
+    if (hexti->PendingCallback != NULL)
+    {
+      hexti->PendingCallback();
+    }
+  }
+}
+
+/**
+  * @brief  Get interrupt pending bit of a dedicated line.
+  * @param  hexti Exti handle.
+  * @param  Edge Specify which pending edge as to be checked.
+  *         This parameter can be one of the following values:
+  *           @arg @ref EXTI_TRIGGER_RISING_FALLING
+  *         This parameter is kept for compatibility with other series.
+  * @retval 1 if interrupt is pending else 0.
+  */
+uint32_t HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge)
+{
+  uint32_t regval;
+  uint32_t linepos;
+  uint32_t maskline;
+
+  /* Check parameters */
+  assert_param(IS_EXTI_LINE(hexti->Line));
+  assert_param(IS_EXTI_CONFIG_LINE(hexti->Line));
+  assert_param(IS_EXTI_PENDING_EDGE(Edge));
+
+  /* Compute line mask */
+  linepos = (hexti->Line & EXTI_PIN_MASK);
+  maskline = (1uL << linepos);
+
+  /* return 1 if bit is set else 0 */
+  regval = ((EXTI->PR & maskline) >> linepos);
+  return regval;
+}
+
+/**
+  * @brief  Clear interrupt pending bit of a dedicated line.
+  * @param  hexti Exti handle.
+  * @param  Edge Specify which pending edge as to be clear.
+  *         This parameter can be one of the following values:
+  *           @arg @ref EXTI_TRIGGER_RISING_FALLING
+  *         This parameter is kept for compatibility with other series.
+  * @retval None.
+  */
+void HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge)
+{
+  uint32_t maskline;
+
+  /* Check parameters */
+  assert_param(IS_EXTI_LINE(hexti->Line));
+  assert_param(IS_EXTI_CONFIG_LINE(hexti->Line));
+  assert_param(IS_EXTI_PENDING_EDGE(Edge));
+
+  /* Compute line mask */
+  maskline = (1uL << (hexti->Line & EXTI_PIN_MASK));
+
+  /* Clear Pending bit */
+  EXTI->PR =  maskline;
+}
+
+/**
+  * @brief  Generate a software interrupt for a dedicated line.
+  * @param  hexti Exti handle.
+  * @retval None.
+  */
+void HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti)
+{
+  uint32_t maskline;
+
+  /* Check parameters */
+  assert_param(IS_EXTI_LINE(hexti->Line));
+  assert_param(IS_EXTI_CONFIG_LINE(hexti->Line));
+
+  /* Compute line mask */
+  maskline = (1uL << (hexti->Line & EXTI_PIN_MASK));
+
+  /* Generate Software interrupt */
+  EXTI->SWIER = maskline;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* HAL_EXTI_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
diff --git a/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c
new file mode 100644
index 0000000..d18f66f
--- /dev/null
+++ b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c
@@ -0,0 +1,775 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hal_flash.c
+  * @author  MCD Application Team
+  * @brief   FLASH HAL module driver.
+  *          This file provides firmware functions to manage the following 
+  *          functionalities of the internal FLASH memory:
+  *           + Program operations functions
+  *           + Memory Control functions 
+  *           + Peripheral Errors functions
+  *         
+  @verbatim
+  ==============================================================================
+                        ##### FLASH peripheral features #####
+  ==============================================================================
+           
+  [..] The Flash memory interface manages CPU AHB I-Code and D-Code accesses 
+       to the Flash memory. It implements the erase and program Flash memory operations 
+       and the read and write protection mechanisms.
+      
+  [..] The Flash memory interface accelerates code execution with a system of instruction
+       prefetch and cache lines. 
+
+  [..] The FLASH main features are:
+      (+) Flash memory read operations
+      (+) Flash memory program/erase operations
+      (+) Read / write protections
+      (+) Prefetch on I-Code
+      (+) 64 cache lines of 128 bits on I-Code
+      (+) 8 cache lines of 128 bits on D-Code
+      
+      
+                     ##### How to use this driver #####
+  ==============================================================================
+    [..]                             
+      This driver provides functions and macros to configure and program the FLASH 
+      memory of all STM32F4xx devices.
+    
+      (#) FLASH Memory IO Programming functions: 
+           (++) Lock and Unlock the FLASH interface using HAL_FLASH_Unlock() and 
+                HAL_FLASH_Lock() functions
+           (++) Program functions: byte, half word, word and double word
+           (++) There Two modes of programming :
+            (+++) Polling mode using HAL_FLASH_Program() function
+            (+++) Interrupt mode using HAL_FLASH_Program_IT() function
+    
+      (#) Interrupts and flags management functions : 
+           (++) Handle FLASH interrupts by calling HAL_FLASH_IRQHandler()
+           (++) Wait for last FLASH operation according to its status
+           (++) Get error flag status by calling HAL_SetErrorCode()          
+
+    [..] 
+      In addition to these functions, this driver includes a set of macros allowing
+      to handle the following operations:
+       (+) Set the latency
+       (+) Enable/Disable the prefetch buffer
+       (+) Enable/Disable the Instruction cache and the Data cache
+       (+) Reset the Instruction cache and the Data cache
+       (+) Enable/Disable the FLASH interrupts
+       (+) Monitor the FLASH flags status
+          
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file in
+  * the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  ******************************************************************************
+  */ 
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup FLASH FLASH
+  * @brief FLASH HAL module driver
+  * @{
+  */
+
+#ifdef HAL_FLASH_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @addtogroup FLASH_Private_Constants
+  * @{
+  */
+#define FLASH_TIMEOUT_VALUE       50000U /* 50 s */
+/**
+  * @}
+  */         
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/** @addtogroup FLASH_Private_Variables
+  * @{
+  */
+/* Variable used for Erase sectors under interruption */
+FLASH_ProcessTypeDef pFlash;
+/**
+  * @}
+  */
+
+/* Private function prototypes -----------------------------------------------*/
+/** @addtogroup FLASH_Private_Functions
+  * @{
+  */
+/* Program operations */
+static void   FLASH_Program_DoubleWord(uint32_t Address, uint64_t Data);
+static void   FLASH_Program_Word(uint32_t Address, uint32_t Data);
+static void   FLASH_Program_HalfWord(uint32_t Address, uint16_t Data);
+static void   FLASH_Program_Byte(uint32_t Address, uint8_t Data);
+static void   FLASH_SetErrorCode(void);
+
+HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout);
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup FLASH_Exported_Functions FLASH Exported Functions
+  * @{
+  */
+  
+/** @defgroup FLASH_Exported_Functions_Group1 Programming operation functions 
+ *  @brief   Programming operation functions 
+ *
+@verbatim   
+ ===============================================================================
+                  ##### Programming operation functions #####
+ ===============================================================================  
+    [..]
+    This subsection provides a set of functions allowing to manage the FLASH 
+    program operations.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Program byte, halfword, word or double word at a specified address
+  * @param  TypeProgram  Indicate the way to program at a specified address.
+  *                           This parameter can be a value of @ref FLASH_Type_Program
+  * @param  Address  specifies the address to be programmed.
+  * @param  Data specifies the data to be programmed
+  * 
+  * @retval HAL_StatusTypeDef HAL Status
+  */
+HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data)
+{
+  HAL_StatusTypeDef status = HAL_ERROR;
+  
+  /* Process Locked */
+  __HAL_LOCK(&pFlash);
+  
+  /* Check the parameters */
+  assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram));
+  
+  /* Wait for last operation to be completed */
+  status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+  
+  if(status == HAL_OK)
+  {
+    if(TypeProgram == FLASH_TYPEPROGRAM_BYTE)
+    {
+      /*Program byte (8-bit) at a specified address.*/
+      FLASH_Program_Byte(Address, (uint8_t) Data);
+    }
+    else if(TypeProgram == FLASH_TYPEPROGRAM_HALFWORD)
+    {
+      /*Program halfword (16-bit) at a specified address.*/
+      FLASH_Program_HalfWord(Address, (uint16_t) Data);
+    }
+    else if(TypeProgram == FLASH_TYPEPROGRAM_WORD)
+    {
+      /*Program word (32-bit) at a specified address.*/
+      FLASH_Program_Word(Address, (uint32_t) Data);
+    }
+    else
+    {
+      /*Program double word (64-bit) at a specified address.*/
+      FLASH_Program_DoubleWord(Address, Data);
+    }
+    
+    /* Wait for last operation to be completed */
+    status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+    
+    /* If the program operation is completed, disable the PG Bit */
+    FLASH->CR &= (~FLASH_CR_PG);  
+  }
+  
+  /* Process Unlocked */
+  __HAL_UNLOCK(&pFlash);
+  
+  return status;
+}
+
+/**
+  * @brief   Program byte, halfword, word or double word at a specified address  with interrupt enabled.
+  * @param  TypeProgram  Indicate the way to program at a specified address.
+  *                           This parameter can be a value of @ref FLASH_Type_Program
+  * @param  Address  specifies the address to be programmed.
+  * @param  Data specifies the data to be programmed
+  * 
+  * @retval HAL Status
+  */
+HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  
+  /* Process Locked */
+  __HAL_LOCK(&pFlash);
+
+  /* Check the parameters */
+  assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram));
+
+  /* Enable End of FLASH Operation interrupt */
+  __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP);
+  
+  /* Enable Error source interrupt */
+  __HAL_FLASH_ENABLE_IT(FLASH_IT_ERR);
+
+  pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAM;
+  pFlash.Address = Address;
+
+  if(TypeProgram == FLASH_TYPEPROGRAM_BYTE)
+  {
+    /*Program byte (8-bit) at a specified address.*/
+      FLASH_Program_Byte(Address, (uint8_t) Data);
+  }
+  else if(TypeProgram == FLASH_TYPEPROGRAM_HALFWORD)
+  {
+    /*Program halfword (16-bit) at a specified address.*/
+    FLASH_Program_HalfWord(Address, (uint16_t) Data);
+  }
+  else if(TypeProgram == FLASH_TYPEPROGRAM_WORD)
+  {
+    /*Program word (32-bit) at a specified address.*/
+    FLASH_Program_Word(Address, (uint32_t) Data);
+  }
+  else
+  {
+    /*Program double word (64-bit) at a specified address.*/
+    FLASH_Program_DoubleWord(Address, Data);
+  }
+
+  return status;
+}
+
+/**
+  * @brief This function handles FLASH interrupt request.
+  * @retval None
+  */
+void HAL_FLASH_IRQHandler(void)
+{
+  uint32_t addresstmp = 0U;
+  
+  /* Check FLASH operation error flags */
+#if defined(FLASH_SR_RDERR) 
+  if(__HAL_FLASH_GET_FLAG((FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR | FLASH_FLAG_PGAERR | \
+    FLASH_FLAG_PGPERR | FLASH_FLAG_PGSERR | FLASH_FLAG_RDERR)) != RESET)
+#else
+  if(__HAL_FLASH_GET_FLAG((FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR | FLASH_FLAG_PGAERR | \
+    FLASH_FLAG_PGPERR | FLASH_FLAG_PGSERR)) != RESET)
+#endif /* FLASH_SR_RDERR */
+  {
+    if(pFlash.ProcedureOnGoing == FLASH_PROC_SECTERASE)
+    {
+      /*return the faulty sector*/
+      addresstmp = pFlash.Sector;
+      pFlash.Sector = 0xFFFFFFFFU;
+    }
+    else if(pFlash.ProcedureOnGoing == FLASH_PROC_MASSERASE)
+    {
+      /*return the faulty bank*/
+      addresstmp = pFlash.Bank;
+    }
+    else
+    {
+      /*return the faulty address*/
+      addresstmp = pFlash.Address;
+    }
+    
+    /*Save the Error code*/
+    FLASH_SetErrorCode();
+    
+    /* FLASH error interrupt user callback */
+    HAL_FLASH_OperationErrorCallback(addresstmp);
+    
+    /*Stop the procedure ongoing*/
+    pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
+  }
+  
+  /* Check FLASH End of Operation flag  */
+  if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP) != RESET)
+  {
+    /* Clear FLASH End of Operation pending bit */
+    __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP);
+    
+    if(pFlash.ProcedureOnGoing == FLASH_PROC_SECTERASE)
+    {
+      /*Nb of sector to erased can be decreased*/
+      pFlash.NbSectorsToErase--;
+      
+      /* Check if there are still sectors to erase*/
+      if(pFlash.NbSectorsToErase != 0U)
+      {
+        addresstmp = pFlash.Sector;
+        /*Indicate user which sector has been erased*/
+        HAL_FLASH_EndOfOperationCallback(addresstmp);
+        
+        /*Increment sector number*/
+        pFlash.Sector++;
+        addresstmp = pFlash.Sector;
+        FLASH_Erase_Sector(addresstmp, pFlash.VoltageForErase);
+      }
+      else
+      {
+        /*No more sectors to Erase, user callback can be called.*/
+        /*Reset Sector and stop Erase sectors procedure*/
+        pFlash.Sector = addresstmp = 0xFFFFFFFFU;
+        pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
+        
+        /* Flush the caches to be sure of the data consistency */
+        FLASH_FlushCaches() ;
+                
+        /* FLASH EOP interrupt user callback */
+        HAL_FLASH_EndOfOperationCallback(addresstmp);
+      }
+    }
+    else 
+    {
+      if(pFlash.ProcedureOnGoing == FLASH_PROC_MASSERASE) 
+      {
+        /* MassErase ended. Return the selected bank */
+        /* Flush the caches to be sure of the data consistency */
+        FLASH_FlushCaches() ;
+
+        /* FLASH EOP interrupt user callback */
+        HAL_FLASH_EndOfOperationCallback(pFlash.Bank);
+      }
+      else
+      {
+        /*Program ended. Return the selected address*/
+        /* FLASH EOP interrupt user callback */
+        HAL_FLASH_EndOfOperationCallback(pFlash.Address);
+      }
+      pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
+    }
+  }
+  
+  if(pFlash.ProcedureOnGoing == FLASH_PROC_NONE)
+  {
+    /* Operation is completed, disable the PG, SER, SNB and MER Bits */
+    CLEAR_BIT(FLASH->CR, (FLASH_CR_PG | FLASH_CR_SER | FLASH_CR_SNB | FLASH_MER_BIT));
+
+    /* Disable End of FLASH Operation interrupt */
+    __HAL_FLASH_DISABLE_IT(FLASH_IT_EOP);
+    
+    /* Disable Error source interrupt */
+    __HAL_FLASH_DISABLE_IT(FLASH_IT_ERR);
+    
+    /* Process Unlocked */
+    __HAL_UNLOCK(&pFlash);
+  }
+}
+
+/**
+  * @brief  FLASH end of operation interrupt callback
+  * @param  ReturnValue The value saved in this parameter depends on the ongoing procedure
+  *                  Mass Erase: Bank number which has been requested to erase
+  *                  Sectors Erase: Sector which has been erased 
+  *                    (if 0xFFFFFFFFU, it means that all the selected sectors have been erased)
+  *                  Program: Address which was selected for data program
+  * @retval None
+  */
+__weak void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(ReturnValue);
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_FLASH_EndOfOperationCallback could be implemented in the user file
+   */ 
+}
+
+/**
+  * @brief  FLASH operation error interrupt callback
+  * @param  ReturnValue The value saved in this parameter depends on the ongoing procedure
+  *                 Mass Erase: Bank number which has been requested to erase
+  *                 Sectors Erase: Sector number which returned an error
+  *                 Program: Address which was selected for data program
+  * @retval None
+  */
+__weak void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(ReturnValue);
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_FLASH_OperationErrorCallback could be implemented in the user file
+   */ 
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup FLASH_Exported_Functions_Group2 Peripheral Control functions 
+ *  @brief   management functions 
+ *
+@verbatim   
+ ===============================================================================
+                      ##### Peripheral Control functions #####
+ ===============================================================================  
+    [..]
+    This subsection provides a set of functions allowing to control the FLASH 
+    memory operations.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Unlock the FLASH control register access
+  * @retval HAL Status
+  */
+HAL_StatusTypeDef HAL_FLASH_Unlock(void)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if(READ_BIT(FLASH->CR, FLASH_CR_LOCK) != RESET)
+  {
+    /* Authorize the FLASH Registers access */
+    WRITE_REG(FLASH->KEYR, FLASH_KEY1);
+    WRITE_REG(FLASH->KEYR, FLASH_KEY2);
+
+    /* Verify Flash is unlocked */
+    if(READ_BIT(FLASH->CR, FLASH_CR_LOCK) != RESET)
+    {
+      status = HAL_ERROR;
+    }
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Locks the FLASH control register access
+  * @retval HAL Status
+  */
+HAL_StatusTypeDef HAL_FLASH_Lock(void)
+{
+  /* Set the LOCK Bit to lock the FLASH Registers access */
+  FLASH->CR |= FLASH_CR_LOCK;
+  
+  return HAL_OK;  
+}
+
+/**
+  * @brief  Unlock the FLASH Option Control Registers access.
+  * @retval HAL Status
+  */
+HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void)
+{
+  if((FLASH->OPTCR & FLASH_OPTCR_OPTLOCK) != RESET)
+  {
+    /* Authorizes the Option Byte register programming */
+    FLASH->OPTKEYR = FLASH_OPT_KEY1;
+    FLASH->OPTKEYR = FLASH_OPT_KEY2;
+  }
+  else
+  {
+    return HAL_ERROR;
+  }  
+  
+  return HAL_OK;  
+}
+
+/**
+  * @brief  Lock the FLASH Option Control Registers access.
+  * @retval HAL Status 
+  */
+HAL_StatusTypeDef HAL_FLASH_OB_Lock(void)
+{
+  /* Set the OPTLOCK Bit to lock the FLASH Option Byte Registers access */
+  FLASH->OPTCR |= FLASH_OPTCR_OPTLOCK;
+  
+  return HAL_OK;  
+}
+
+/**
+  * @brief  Launch the option byte loading.
+  * @retval HAL Status
+  */
+HAL_StatusTypeDef HAL_FLASH_OB_Launch(void)
+{
+  /* Set the OPTSTRT bit in OPTCR register */
+  *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS |= FLASH_OPTCR_OPTSTRT;
+
+  /* Wait for last operation to be completed */
+  return(FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE)); 
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup FLASH_Exported_Functions_Group3 Peripheral State and Errors functions 
+ *  @brief   Peripheral Errors functions 
+ *
+@verbatim   
+ ===============================================================================
+                ##### Peripheral Errors functions #####
+ ===============================================================================  
+    [..]
+    This subsection permits to get in run-time Errors of the FLASH peripheral.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Get the specific FLASH error flag.
+  * @retval FLASH_ErrorCode: The returned value can be a combination of:
+  *            @arg HAL_FLASH_ERROR_RD: FLASH Read Protection error flag (PCROP)
+  *            @arg HAL_FLASH_ERROR_PGS: FLASH Programming Sequence error flag 
+  *            @arg HAL_FLASH_ERROR_PGP: FLASH Programming Parallelism error flag  
+  *            @arg HAL_FLASH_ERROR_PGA: FLASH Programming Alignment error flag
+  *            @arg HAL_FLASH_ERROR_WRP: FLASH Write protected error flag
+  *            @arg HAL_FLASH_ERROR_OPERATION: FLASH operation Error flag 
+  */
+uint32_t HAL_FLASH_GetError(void)
+{ 
+   return pFlash.ErrorCode;
+}  
+  
+/**
+  * @}
+  */    
+
+/**
+  * @brief  Wait for a FLASH operation to complete.
+  * @param  Timeout maximum flash operationtimeout
+  * @retval HAL Status
+  */
+HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout)
+{ 
+  uint32_t tickstart = 0U;
+  
+  /* Clear Error Code */
+  pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
+  
+  /* Wait for the FLASH operation to complete by polling on BUSY flag to be reset.
+     Even if the FLASH operation fails, the BUSY flag will be reset and an error
+     flag will be set */
+  /* Get tick */
+  tickstart = HAL_GetTick();
+
+  while(__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY) != RESET) 
+  { 
+    if(Timeout != HAL_MAX_DELAY)
+    {
+      if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
+      {
+        return HAL_TIMEOUT;
+      }
+    } 
+  }
+
+  /* Check FLASH End of Operation flag  */
+  if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP) != RESET)
+  {
+    /* Clear FLASH End of Operation pending bit */
+    __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP);
+  }
+#if defined(FLASH_SR_RDERR)  
+  if(__HAL_FLASH_GET_FLAG((FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR | FLASH_FLAG_PGAERR | \
+                           FLASH_FLAG_PGPERR | FLASH_FLAG_PGSERR | FLASH_FLAG_RDERR)) != RESET)
+#else
+  if(__HAL_FLASH_GET_FLAG((FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR | FLASH_FLAG_PGAERR | \
+                           FLASH_FLAG_PGPERR | FLASH_FLAG_PGSERR)) != RESET)
+#endif /* FLASH_SR_RDERR */
+  {
+    /*Save the error code*/
+    FLASH_SetErrorCode();
+    return HAL_ERROR;
+  }
+
+  /* If there is no error flag set */
+  return HAL_OK;
+  
+}  
+
+/**
+  * @brief  Program a double word (64-bit) at a specified address.
+  * @note   This function must be used when the device voltage range is from
+  *         2.7V to 3.6V and Vpp in the range 7V to 9V.
+  *
+  * @note   If an erase and a program operations are requested simultaneously,    
+  *         the erase operation is performed before the program one.
+  *  
+  * @param  Address specifies the address to be programmed.
+  * @param  Data specifies the data to be programmed.
+  * @retval None
+  */
+static void FLASH_Program_DoubleWord(uint32_t Address, uint64_t Data)
+{
+  /* Check the parameters */
+  assert_param(IS_FLASH_ADDRESS(Address));
+  
+  /* If the previous operation is completed, proceed to program the new data */
+  CLEAR_BIT(FLASH->CR, FLASH_CR_PSIZE);
+  FLASH->CR |= FLASH_PSIZE_DOUBLE_WORD;
+  FLASH->CR |= FLASH_CR_PG;
+
+  /* Program first word */
+  *(__IO uint32_t*)Address = (uint32_t)Data;
+
+  /* Barrier to ensure programming is performed in 2 steps, in right order
+    (independently of compiler optimization behavior) */
+  __ISB();
+
+  /* Program second word */
+  *(__IO uint32_t*)(Address+4) = (uint32_t)(Data >> 32);
+}
+
+
+/**
+  * @brief  Program word (32-bit) at a specified address.
+  * @note   This function must be used when the device voltage range is from
+  *         2.7V to 3.6V.
+  *
+  * @note   If an erase and a program operations are requested simultaneously,    
+  *         the erase operation is performed before the program one.
+  *  
+  * @param  Address specifies the address to be programmed.
+  * @param  Data specifies the data to be programmed.
+  * @retval None
+  */
+static void FLASH_Program_Word(uint32_t Address, uint32_t Data)
+{
+  /* Check the parameters */
+  assert_param(IS_FLASH_ADDRESS(Address));
+  
+  /* If the previous operation is completed, proceed to program the new data */
+  CLEAR_BIT(FLASH->CR, FLASH_CR_PSIZE);
+  FLASH->CR |= FLASH_PSIZE_WORD;
+  FLASH->CR |= FLASH_CR_PG;
+
+  *(__IO uint32_t*)Address = Data;
+}
+
+/**
+  * @brief  Program a half-word (16-bit) at a specified address.
+  * @note   This function must be used when the device voltage range is from
+  *         2.1V to 3.6V.
+  *
+  * @note   If an erase and a program operations are requested simultaneously,    
+  *         the erase operation is performed before the program one.
+  *  
+  * @param  Address specifies the address to be programmed.
+  * @param  Data specifies the data to be programmed.
+  * @retval None
+  */
+static void FLASH_Program_HalfWord(uint32_t Address, uint16_t Data)
+{
+  /* Check the parameters */
+  assert_param(IS_FLASH_ADDRESS(Address));
+  
+  /* If the previous operation is completed, proceed to program the new data */
+  CLEAR_BIT(FLASH->CR, FLASH_CR_PSIZE);
+  FLASH->CR |= FLASH_PSIZE_HALF_WORD;
+  FLASH->CR |= FLASH_CR_PG;
+
+  *(__IO uint16_t*)Address = Data;
+}
+
+/**
+  * @brief  Program byte (8-bit) at a specified address.
+  * @note   This function must be used when the device voltage range is from
+  *         1.8V to 3.6V.
+  *
+  * @note   If an erase and a program operations are requested simultaneously,    
+  *         the erase operation is performed before the program one.
+  *  
+  * @param  Address specifies the address to be programmed.
+  * @param  Data specifies the data to be programmed.
+  * @retval None
+  */
+static void FLASH_Program_Byte(uint32_t Address, uint8_t Data)
+{
+  /* Check the parameters */
+  assert_param(IS_FLASH_ADDRESS(Address));
+  
+  /* If the previous operation is completed, proceed to program the new data */
+  CLEAR_BIT(FLASH->CR, FLASH_CR_PSIZE);
+  FLASH->CR |= FLASH_PSIZE_BYTE;
+  FLASH->CR |= FLASH_CR_PG;
+
+  *(__IO uint8_t*)Address = Data;
+}
+
+/**
+  * @brief  Set the specific FLASH error flag.
+  * @retval None
+  */
+static void FLASH_SetErrorCode(void)
+{ 
+  if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) != RESET)
+  {
+   pFlash.ErrorCode |= HAL_FLASH_ERROR_WRP;
+   
+   /* Clear FLASH write protection error pending bit */
+   __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_WRPERR);
+  }
+  
+  if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGAERR) != RESET)
+  {
+   pFlash.ErrorCode |= HAL_FLASH_ERROR_PGA;
+   
+   /* Clear FLASH Programming alignment error pending bit */
+   __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_PGAERR);
+  }
+  
+  if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGPERR) != RESET)
+  {
+    pFlash.ErrorCode |= HAL_FLASH_ERROR_PGP;
+    
+    /* Clear FLASH Programming parallelism error pending bit */
+    __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_PGPERR);
+  }
+  
+  if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGSERR) != RESET)
+  {
+    pFlash.ErrorCode |= HAL_FLASH_ERROR_PGS;
+    
+    /* Clear FLASH Programming sequence error pending bit */
+    __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_PGSERR);
+  }
+#if defined(FLASH_SR_RDERR) 
+  if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_RDERR) != RESET)
+  {
+    pFlash.ErrorCode |= HAL_FLASH_ERROR_RD;
+    
+    /* Clear FLASH Proprietary readout protection error pending bit */
+    __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_RDERR);
+  }
+#endif /* FLASH_SR_RDERR */  
+  if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPERR) != RESET)
+  {
+    pFlash.ErrorCode |= HAL_FLASH_ERROR_OPERATION;
+    
+    /* Clear FLASH Operation error pending bit */
+    __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_OPERR);
+  }
+}
+
+/**
+  * @}
+  */
+
+#endif /* HAL_FLASH_MODULE_ENABLED */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
diff --git a/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c
new file mode 100644
index 0000000..abff6d7
--- /dev/null
+++ b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c
@@ -0,0 +1,1347 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hal_flash_ex.c
+  * @author  MCD Application Team
+  * @brief   Extended FLASH HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the FLASH extension peripheral:
+  *           + Extended programming operations functions
+  *
+  @verbatim
+  ==============================================================================
+                   ##### Flash Extension features #####
+  ==============================================================================
+
+  [..] Comparing to other previous devices, the FLASH interface for STM32F427xx/437xx and
+       STM32F429xx/439xx devices contains the following additional features
+
+       (+) Capacity up to 2 Mbyte with dual bank architecture supporting read-while-write
+           capability (RWW)
+       (+) Dual bank memory organization
+       (+) PCROP protection for all banks
+
+                      ##### How to use this driver #####
+  ==============================================================================
+  [..] This driver provides functions to configure and program the FLASH memory
+       of all STM32F427xx/437xx, STM32F429xx/439xx, STM32F469xx/479xx and STM32F446xx
+       devices. It includes
+      (#) FLASH Memory Erase functions:
+           (++) Lock and Unlock the FLASH interface using HAL_FLASH_Unlock() and
+                HAL_FLASH_Lock() functions
+           (++) Erase function: Erase sector, erase all sectors
+           (++) There are two modes of erase :
+             (+++) Polling Mode using HAL_FLASHEx_Erase()
+             (+++) Interrupt Mode using HAL_FLASHEx_Erase_IT()
+
+      (#) Option Bytes Programming functions: Use HAL_FLASHEx_OBProgram() to :
+           (++) Set/Reset the write protection
+           (++) Set the Read protection Level
+           (++) Set the BOR level
+           (++) Program the user Option Bytes
+      (#) Advanced Option Bytes Programming functions: Use HAL_FLASHEx_AdvOBProgram() to :
+       (++) Extended space (bank 2) erase function
+       (++) Full FLASH space (2 Mo) erase (bank 1 and bank 2)
+       (++) Dual Boot activation
+       (++) Write protection configuration for bank 2
+       (++) PCROP protection configuration and control for both banks
+
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file in
+  * the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup FLASHEx FLASHEx
+  * @brief FLASH HAL Extension module driver
+  * @{
+  */
+
+#ifdef HAL_FLASH_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @addtogroup FLASHEx_Private_Constants
+  * @{
+  */
+#define FLASH_TIMEOUT_VALUE       50000U /* 50 s */
+/**
+  * @}
+  */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/** @addtogroup FLASHEx_Private_Variables
+  * @{
+  */
+extern FLASH_ProcessTypeDef pFlash;
+/**
+  * @}
+  */
+
+/* Private function prototypes -----------------------------------------------*/
+/** @addtogroup FLASHEx_Private_Functions
+  * @{
+  */
+/* Option bytes control */
+static void               FLASH_MassErase(uint8_t VoltageRange, uint32_t Banks);
+static HAL_StatusTypeDef  FLASH_OB_EnableWRP(uint32_t WRPSector, uint32_t Banks);
+static HAL_StatusTypeDef  FLASH_OB_DisableWRP(uint32_t WRPSector, uint32_t Banks);
+static HAL_StatusTypeDef  FLASH_OB_RDP_LevelConfig(uint8_t Level);
+static HAL_StatusTypeDef  FLASH_OB_UserConfig(uint8_t Iwdg, uint8_t Stop, uint8_t Stdby);
+static HAL_StatusTypeDef  FLASH_OB_BOR_LevelConfig(uint8_t Level);
+static uint8_t            FLASH_OB_GetUser(void);
+static uint16_t           FLASH_OB_GetWRP(void);
+static uint8_t            FLASH_OB_GetRDP(void);
+static uint8_t            FLASH_OB_GetBOR(void);
+
+#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F411xE) ||\
+    defined(STM32F446xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) ||\
+    defined(STM32F423xx)
+static HAL_StatusTypeDef  FLASH_OB_EnablePCROP(uint32_t Sector);
+static HAL_StatusTypeDef  FLASH_OB_DisablePCROP(uint32_t Sector);
+#endif /* STM32F401xC || STM32F401xE || STM32F410xx || STM32F411xE || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx
+          STM32F413xx || STM32F423xx */
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
+static HAL_StatusTypeDef FLASH_OB_EnablePCROP(uint32_t SectorBank1, uint32_t SectorBank2, uint32_t Banks);
+static HAL_StatusTypeDef FLASH_OB_DisablePCROP(uint32_t SectorBank1, uint32_t SectorBank2, uint32_t Banks);
+static HAL_StatusTypeDef FLASH_OB_BootConfig(uint8_t BootConfig);
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
+
+extern HAL_StatusTypeDef         FLASH_WaitForLastOperation(uint32_t Timeout);
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup FLASHEx_Exported_Functions FLASHEx Exported Functions
+  * @{
+  */
+
+/** @defgroup FLASHEx_Exported_Functions_Group1 Extended IO operation functions
+ *  @brief   Extended IO operation functions
+ *
+@verbatim
+ ===============================================================================
+                ##### Extended programming operation functions #####
+ ===============================================================================
+    [..]
+    This subsection provides a set of functions allowing to manage the Extension FLASH
+    programming operations.
+
+@endverbatim
+  * @{
+  */
+/**
+  * @brief  Perform a mass erase or erase the specified FLASH memory sectors
+  * @param[in]  pEraseInit pointer to an FLASH_EraseInitTypeDef structure that
+  *         contains the configuration information for the erasing.
+  *
+  * @param[out]  SectorError pointer to variable  that
+  *         contains the configuration information on faulty sector in case of error
+  *         (0xFFFFFFFFU means that all the sectors have been correctly erased)
+  *
+  * @retval HAL Status
+  */
+HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *SectorError)
+{
+  HAL_StatusTypeDef status = HAL_ERROR;
+  uint32_t index = 0U;
+
+  /* Process Locked */
+  __HAL_LOCK(&pFlash);
+
+  /* Check the parameters */
+  assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase));
+
+  /* Wait for last operation to be completed */
+  status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+
+  if (status == HAL_OK)
+  {
+    /*Initialization of SectorError variable*/
+    *SectorError = 0xFFFFFFFFU;
+
+    if (pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE)
+    {
+      /*Mass erase to be done*/
+      FLASH_MassErase((uint8_t) pEraseInit->VoltageRange, pEraseInit->Banks);
+
+      /* Wait for last operation to be completed */
+      status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+
+      /* if the erase operation is completed, disable the MER Bit */
+      FLASH->CR &= (~FLASH_MER_BIT);
+    }
+    else
+    {
+      /* Check the parameters */
+      assert_param(IS_FLASH_NBSECTORS(pEraseInit->NbSectors + pEraseInit->Sector));
+
+      /* Erase by sector by sector to be done*/
+      for (index = pEraseInit->Sector; index < (pEraseInit->NbSectors + pEraseInit->Sector); index++)
+      {
+        FLASH_Erase_Sector(index, (uint8_t) pEraseInit->VoltageRange);
+
+        /* Wait for last operation to be completed */
+        status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+
+        /* If the erase operation is completed, disable the SER and SNB Bits */
+        CLEAR_BIT(FLASH->CR, (FLASH_CR_SER | FLASH_CR_SNB));
+
+        if (status != HAL_OK)
+        {
+          /* In case of error, stop erase procedure and return the faulty sector*/
+          *SectorError = index;
+          break;
+        }
+      }
+    }
+    /* Flush the caches to be sure of the data consistency */
+    FLASH_FlushCaches();
+  }
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(&pFlash);
+
+  return status;
+}
+
+/**
+  * @brief  Perform a mass erase or erase the specified FLASH memory sectors  with interrupt enabled
+  * @param  pEraseInit pointer to an FLASH_EraseInitTypeDef structure that
+  *         contains the configuration information for the erasing.
+  *
+  * @retval HAL Status
+  */
+HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Process Locked */
+  __HAL_LOCK(&pFlash);
+
+  /* Check the parameters */
+  assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase));
+
+  /* Enable End of FLASH Operation interrupt */
+  __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP);
+
+  /* Enable Error source interrupt */
+  __HAL_FLASH_ENABLE_IT(FLASH_IT_ERR);
+
+  /* Clear pending flags (if any) */
+  __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP    | FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR | \
+                         FLASH_FLAG_PGAERR | FLASH_FLAG_PGPERR | FLASH_FLAG_PGSERR);
+
+  if (pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE)
+  {
+    /*Mass erase to be done*/
+    pFlash.ProcedureOnGoing = FLASH_PROC_MASSERASE;
+    pFlash.Bank = pEraseInit->Banks;
+    FLASH_MassErase((uint8_t) pEraseInit->VoltageRange, pEraseInit->Banks);
+  }
+  else
+  {
+    /* Erase by sector to be done*/
+
+    /* Check the parameters */
+    assert_param(IS_FLASH_NBSECTORS(pEraseInit->NbSectors + pEraseInit->Sector));
+
+    pFlash.ProcedureOnGoing = FLASH_PROC_SECTERASE;
+    pFlash.NbSectorsToErase = pEraseInit->NbSectors;
+    pFlash.Sector = pEraseInit->Sector;
+    pFlash.VoltageForErase = (uint8_t)pEraseInit->VoltageRange;
+
+    /*Erase 1st sector and wait for IT*/
+    FLASH_Erase_Sector(pEraseInit->Sector, pEraseInit->VoltageRange);
+  }
+
+  return status;
+}
+
+/**
+  * @brief   Program option bytes
+  * @param  pOBInit pointer to an FLASH_OBInitStruct structure that
+  *         contains the configuration information for the programming.
+  *
+  * @retval HAL Status
+  */
+HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit)
+{
+  HAL_StatusTypeDef status = HAL_ERROR;
+
+  /* Process Locked */
+  __HAL_LOCK(&pFlash);
+
+  /* Check the parameters */
+  assert_param(IS_OPTIONBYTE(pOBInit->OptionType));
+
+  /*Write protection configuration*/
+  if ((pOBInit->OptionType & OPTIONBYTE_WRP) == OPTIONBYTE_WRP)
+  {
+    assert_param(IS_WRPSTATE(pOBInit->WRPState));
+    if (pOBInit->WRPState == OB_WRPSTATE_ENABLE)
+    {
+      /*Enable of Write protection on the selected Sector*/
+      status = FLASH_OB_EnableWRP(pOBInit->WRPSector, pOBInit->Banks);
+    }
+    else
+    {
+      /*Disable of Write protection on the selected Sector*/
+      status = FLASH_OB_DisableWRP(pOBInit->WRPSector, pOBInit->Banks);
+    }
+  }
+
+  /*Read protection configuration*/
+  if ((pOBInit->OptionType & OPTIONBYTE_RDP) == OPTIONBYTE_RDP)
+  {
+    status = FLASH_OB_RDP_LevelConfig(pOBInit->RDPLevel);
+  }
+
+  /*USER  configuration*/
+  if ((pOBInit->OptionType & OPTIONBYTE_USER) == OPTIONBYTE_USER)
+  {
+    status = FLASH_OB_UserConfig(pOBInit->USERConfig & OB_IWDG_SW,
+                                 pOBInit->USERConfig & OB_STOP_NO_RST,
+                                 pOBInit->USERConfig & OB_STDBY_NO_RST);
+  }
+
+  /*BOR Level  configuration*/
+  if ((pOBInit->OptionType & OPTIONBYTE_BOR) == OPTIONBYTE_BOR)
+  {
+    status = FLASH_OB_BOR_LevelConfig(pOBInit->BORLevel);
+  }
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(&pFlash);
+
+  return status;
+}
+
+/**
+  * @brief   Get the Option byte configuration
+  * @param  pOBInit pointer to an FLASH_OBInitStruct structure that
+  *         contains the configuration information for the programming.
+  *
+  * @retval None
+  */
+void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit)
+{
+  pOBInit->OptionType = OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER | OPTIONBYTE_BOR;
+
+  /*Get WRP*/
+  pOBInit->WRPSector = (uint32_t)FLASH_OB_GetWRP();
+
+  /*Get RDP Level*/
+  pOBInit->RDPLevel = (uint32_t)FLASH_OB_GetRDP();
+
+  /*Get USER*/
+  pOBInit->USERConfig = (uint8_t)FLASH_OB_GetUser();
+
+  /*Get BOR Level*/
+  pOBInit->BORLevel = (uint32_t)FLASH_OB_GetBOR();
+}
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
+    defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) ||\
+    defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F469xx) ||\
+    defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) ||\
+    defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
+/**
+  * @brief   Program option bytes
+  * @param  pAdvOBInit pointer to an FLASH_AdvOBProgramInitTypeDef structure that
+  *         contains the configuration information for the programming.
+  *
+  * @retval HAL Status
+  */
+HAL_StatusTypeDef HAL_FLASHEx_AdvOBProgram(FLASH_AdvOBProgramInitTypeDef *pAdvOBInit)
+{
+  HAL_StatusTypeDef status = HAL_ERROR;
+
+  /* Check the parameters */
+  assert_param(IS_OBEX(pAdvOBInit->OptionType));
+
+  /*Program PCROP option byte*/
+  if (((pAdvOBInit->OptionType) & OPTIONBYTE_PCROP) == OPTIONBYTE_PCROP)
+  {
+    /* Check the parameters */
+    assert_param(IS_PCROPSTATE(pAdvOBInit->PCROPState));
+    if ((pAdvOBInit->PCROPState) == OB_PCROP_STATE_ENABLE)
+    {
+      /*Enable of Write protection on the selected Sector*/
+#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) ||\
+    defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) ||\
+    defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
+      status = FLASH_OB_EnablePCROP(pAdvOBInit->Sectors);
+#else  /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx || STM32F469xx || STM32F479xx */
+      status = FLASH_OB_EnablePCROP(pAdvOBInit->SectorsBank1, pAdvOBInit->SectorsBank2, pAdvOBInit->Banks);
+#endif /* STM32F401xC || STM32F401xE || STM32F410xx || STM32F411xE || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx ||
+          STM32F413xx || STM32F423xx */
+    }
+    else
+    {
+      /*Disable of Write protection on the selected Sector*/
+#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) ||\
+    defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) ||\
+    defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
+      status = FLASH_OB_DisablePCROP(pAdvOBInit->Sectors);
+#else /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx || STM32F469xx || STM32F479xx */
+      status = FLASH_OB_DisablePCROP(pAdvOBInit->SectorsBank1, pAdvOBInit->SectorsBank2, pAdvOBInit->Banks);
+#endif /* STM32F401xC || STM32F401xE || STM32F410xx || STM32F411xE || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx ||
+          STM32F413xx || STM32F423xx */
+    }
+  }
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
+  /*Program BOOT config option byte*/
+  if (((pAdvOBInit->OptionType) & OPTIONBYTE_BOOTCONFIG) == OPTIONBYTE_BOOTCONFIG)
+  {
+    status = FLASH_OB_BootConfig(pAdvOBInit->BootConfig);
+  }
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
+
+  return status;
+}
+
+/**
+  * @brief   Get the OBEX byte configuration
+  * @param  pAdvOBInit pointer to an FLASH_AdvOBProgramInitTypeDef structure that
+  *         contains the configuration information for the programming.
+  *
+  * @retval None
+  */
+void HAL_FLASHEx_AdvOBGetConfig(FLASH_AdvOBProgramInitTypeDef *pAdvOBInit)
+{
+#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) ||\
+    defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) ||\
+    defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
+  /*Get Sector*/
+  pAdvOBInit->Sectors = (*(__IO uint16_t *)(OPTCR_BYTE2_ADDRESS));
+#else  /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx || STM32F469xx || STM32F479xx */
+  /*Get Sector for Bank1*/
+  pAdvOBInit->SectorsBank1 = (*(__IO uint16_t *)(OPTCR_BYTE2_ADDRESS));
+
+  /*Get Sector for Bank2*/
+  pAdvOBInit->SectorsBank2 = (*(__IO uint16_t *)(OPTCR1_BYTE2_ADDRESS));
+
+  /*Get Boot config OB*/
+  pAdvOBInit->BootConfig = *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS;
+#endif /* STM32F401xC || STM32F401xE || STM32F410xx || STM32F411xE || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx ||
+          STM32F413xx || STM32F423xx */
+}
+
+/**
+  * @brief  Select the Protection Mode
+  *
+  * @note   After PCROP activated Option Byte modification NOT POSSIBLE! excepted
+  *         Global Read Out Protection modification (from level1 to level0)
+  * @note   Once SPRMOD bit is active unprotection of a protected sector is not possible
+  * @note   Read a protected sector will set RDERR Flag and write a protected sector will set WRPERR Flag
+  * @note   This function can be used only for STM32F42xxx/STM32F43xxx/STM32F401xx/STM32F411xx/STM32F446xx/
+  *         STM32F469xx/STM32F479xx/STM32F412xx/STM32F413xx devices.
+  *
+  * @retval HAL Status
+  */
+HAL_StatusTypeDef HAL_FLASHEx_OB_SelectPCROP(void)
+{
+  uint8_t optiontmp = 0xFF;
+
+  /* Mask SPRMOD bit */
+  optiontmp = (uint8_t)((*(__IO uint8_t *)OPTCR_BYTE3_ADDRESS) & (uint8_t)0x7F);
+
+  /* Update Option Byte */
+  *(__IO uint8_t *)OPTCR_BYTE3_ADDRESS = (uint8_t)(OB_PCROP_SELECTED | optiontmp);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Deselect the Protection Mode
+  *
+  * @note   After PCROP activated Option Byte modification NOT POSSIBLE! excepted
+  *         Global Read Out Protection modification (from level1 to level0)
+  * @note   Once SPRMOD bit is active unprotection of a protected sector is not possible
+  * @note   Read a protected sector will set RDERR Flag and write a protected sector will set WRPERR Flag
+  * @note   This function can be used only for STM32F42xxx/STM32F43xxx/STM32F401xx/STM32F411xx/STM32F446xx/
+  *         STM32F469xx/STM32F479xx/STM32F412xx/STM32F413xx devices.
+  *
+  * @retval HAL Status
+  */
+HAL_StatusTypeDef HAL_FLASHEx_OB_DeSelectPCROP(void)
+{
+  uint8_t optiontmp = 0xFF;
+
+  /* Mask SPRMOD bit */
+  optiontmp = (uint8_t)((*(__IO uint8_t *)OPTCR_BYTE3_ADDRESS) & (uint8_t)0x7F);
+
+  /* Update Option Byte */
+  *(__IO uint8_t *)OPTCR_BYTE3_ADDRESS = (uint8_t)(OB_PCROP_DESELECTED | optiontmp);
+
+  return HAL_OK;
+}
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F401xC || STM32F401xE || STM32F410xx ||\
+          STM32F411xE || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx ||
+          STM32F413xx || STM32F423xx */
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
+/**
+  * @brief  Returns the FLASH Write Protection Option Bytes value for Bank 2
+  * @note   This function can be used only for STM32F42xxx/STM32F43xxx/STM32F469xx/STM32F479xx devices.
+  * @retval The FLASH Write Protection  Option Bytes value
+  */
+uint16_t HAL_FLASHEx_OB_GetBank2WRP(void)
+{
+  /* Return the FLASH write protection Register value */
+  return (*(__IO uint16_t *)(OPTCR1_BYTE2_ADDRESS));
+}
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
+
+/**
+  * @}
+  */
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
+/**
+  * @brief  Full erase of FLASH memory sectors
+  * @param  VoltageRange The device voltage range which defines the erase parallelism.
+  *          This parameter can be one of the following values:
+  *            @arg FLASH_VOLTAGE_RANGE_1: when the device voltage range is 1.8V to 2.1V,
+  *                                  the operation will be done by byte (8-bit)
+  *            @arg FLASH_VOLTAGE_RANGE_2: when the device voltage range is 2.1V to 2.7V,
+  *                                  the operation will be done by half word (16-bit)
+  *            @arg FLASH_VOLTAGE_RANGE_3: when the device voltage range is 2.7V to 3.6V,
+  *                                  the operation will be done by word (32-bit)
+  *            @arg FLASH_VOLTAGE_RANGE_4: when the device voltage range is 2.7V to 3.6V + External Vpp,
+  *                                  the operation will be done by double word (64-bit)
+  *
+  * @param  Banks Banks to be erased
+  *          This parameter can be one of the following values:
+  *            @arg FLASH_BANK_1: Bank1 to be erased
+  *            @arg FLASH_BANK_2: Bank2 to be erased
+  *            @arg FLASH_BANK_BOTH: Bank1 and Bank2 to be erased
+  *
+  * @retval HAL Status
+  */
+static void FLASH_MassErase(uint8_t VoltageRange, uint32_t Banks)
+{
+  /* Check the parameters */
+  assert_param(IS_VOLTAGERANGE(VoltageRange));
+  assert_param(IS_FLASH_BANK(Banks));
+
+  /* if the previous operation is completed, proceed to erase all sectors */
+  CLEAR_BIT(FLASH->CR, FLASH_CR_PSIZE);
+
+  if (Banks == FLASH_BANK_BOTH)
+  {
+    /* bank1 & bank2 will be erased*/
+    FLASH->CR |= FLASH_MER_BIT;
+  }
+  else if (Banks == FLASH_BANK_1)
+  {
+    /*Only bank1 will be erased*/
+    FLASH->CR |= FLASH_CR_MER1;
+  }
+  else
+  {
+    /*Only bank2 will be erased*/
+    FLASH->CR |= FLASH_CR_MER2;
+  }
+  FLASH->CR |= FLASH_CR_STRT | ((uint32_t)VoltageRange << 8U);
+}
+
+/**
+  * @brief  Erase the specified FLASH memory sector
+  * @param  Sector FLASH sector to erase
+  *         The value of this parameter depend on device used within the same series
+  * @param  VoltageRange The device voltage range which defines the erase parallelism.
+  *          This parameter can be one of the following values:
+  *            @arg FLASH_VOLTAGE_RANGE_1: when the device voltage range is 1.8V to 2.1V,
+  *                                  the operation will be done by byte (8-bit)
+  *            @arg FLASH_VOLTAGE_RANGE_2: when the device voltage range is 2.1V to 2.7V,
+  *                                  the operation will be done by half word (16-bit)
+  *            @arg FLASH_VOLTAGE_RANGE_3: when the device voltage range is 2.7V to 3.6V,
+  *                                  the operation will be done by word (32-bit)
+  *            @arg FLASH_VOLTAGE_RANGE_4: when the device voltage range is 2.7V to 3.6V + External Vpp,
+  *                                  the operation will be done by double word (64-bit)
+  *
+  * @retval None
+  */
+void FLASH_Erase_Sector(uint32_t Sector, uint8_t VoltageRange)
+{
+  uint32_t tmp_psize = 0U;
+
+  /* Check the parameters */
+  assert_param(IS_FLASH_SECTOR(Sector));
+  assert_param(IS_VOLTAGERANGE(VoltageRange));
+
+  if (VoltageRange == FLASH_VOLTAGE_RANGE_1)
+  {
+    tmp_psize = FLASH_PSIZE_BYTE;
+  }
+  else if (VoltageRange == FLASH_VOLTAGE_RANGE_2)
+  {
+    tmp_psize = FLASH_PSIZE_HALF_WORD;
+  }
+  else if (VoltageRange == FLASH_VOLTAGE_RANGE_3)
+  {
+    tmp_psize = FLASH_PSIZE_WORD;
+  }
+  else
+  {
+    tmp_psize = FLASH_PSIZE_DOUBLE_WORD;
+  }
+
+  /* Need to add offset of 4 when sector higher than FLASH_SECTOR_11 */
+  if (Sector > FLASH_SECTOR_11)
+  {
+    Sector += 4U;
+  }
+  /* If the previous operation is completed, proceed to erase the sector */
+  CLEAR_BIT(FLASH->CR, FLASH_CR_PSIZE);
+  FLASH->CR |= tmp_psize;
+  CLEAR_BIT(FLASH->CR, FLASH_CR_SNB);
+  FLASH->CR |= FLASH_CR_SER | (Sector << FLASH_CR_SNB_Pos);
+  FLASH->CR |= FLASH_CR_STRT;
+}
+
+/**
+  * @brief  Enable the write protection of the desired bank1 or bank 2 sectors
+  *
+  * @note   When the memory read protection level is selected (RDP level = 1),
+  *         it is not possible to program or erase the flash sector i if CortexM4
+  *         debug features are connected or boot code is executed in RAM, even if nWRPi = 1
+  * @note   Active value of nWRPi bits is inverted when PCROP mode is active (SPRMOD =1).
+  *
+  * @param  WRPSector specifies the sector(s) to be write protected.
+  *          This parameter can be one of the following values:
+  *            @arg WRPSector: A value between OB_WRP_SECTOR_0 and OB_WRP_SECTOR_23
+  *            @arg OB_WRP_SECTOR_All
+  * @note   BANK2 starts from OB_WRP_SECTOR_12
+  *
+  * @param  Banks Enable write protection on all the sectors for the specific bank
+  *          This parameter can be one of the following values:
+  *            @arg FLASH_BANK_1: WRP on all sectors of bank1
+  *            @arg FLASH_BANK_2: WRP on all sectors of bank2
+  *            @arg FLASH_BANK_BOTH: WRP on all sectors of bank1 & bank2
+  *
+  * @retval HAL FLASH State
+  */
+static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WRPSector, uint32_t Banks)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the parameters */
+  assert_param(IS_OB_WRP_SECTOR(WRPSector));
+  assert_param(IS_FLASH_BANK(Banks));
+
+  /* Wait for last operation to be completed */
+  status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+
+  if (status == HAL_OK)
+  {
+    if (((WRPSector == OB_WRP_SECTOR_All) && ((Banks == FLASH_BANK_1) || (Banks == FLASH_BANK_BOTH))) ||
+        (WRPSector < OB_WRP_SECTOR_12))
+    {
+      if (WRPSector == OB_WRP_SECTOR_All)
+      {
+        /*Write protection on all sector of BANK1*/
+        *(__IO uint16_t *)OPTCR_BYTE2_ADDRESS &= (~(WRPSector >> 12));
+      }
+      else
+      {
+        /*Write protection done on sectors of BANK1*/
+        *(__IO uint16_t *)OPTCR_BYTE2_ADDRESS &= (~WRPSector);
+      }
+    }
+    else
+    {
+      /*Write protection done on sectors of BANK2*/
+      *(__IO uint16_t *)OPTCR1_BYTE2_ADDRESS &= (~(WRPSector >> 12));
+    }
+
+    /*Write protection on all sector of BANK2*/
+    if ((WRPSector == OB_WRP_SECTOR_All) && (Banks == FLASH_BANK_BOTH))
+    {
+      /* Wait for last operation to be completed */
+      status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+
+      if (status == HAL_OK)
+      {
+        *(__IO uint16_t *)OPTCR1_BYTE2_ADDRESS &= (~(WRPSector >> 12));
+      }
+    }
+
+  }
+  return status;
+}
+
+/**
+  * @brief  Disable the write protection of the desired bank1 or bank 2 sectors
+  *
+  * @note   When the memory read protection level is selected (RDP level = 1),
+  *         it is not possible to program or erase the flash sector i if CortexM4
+  *         debug features are connected or boot code is executed in RAM, even if nWRPi = 1
+  * @note   Active value of nWRPi bits is inverted when PCROP mode is active (SPRMOD =1).
+  *
+  * @param  WRPSector specifies the sector(s) to be write protected.
+  *          This parameter can be one of the following values:
+  *            @arg WRPSector: A value between OB_WRP_SECTOR_0 and OB_WRP_SECTOR_23
+  *            @arg OB_WRP_Sector_All
+  * @note   BANK2 starts from OB_WRP_SECTOR_12
+  *
+  * @param  Banks Disable write protection on all the sectors for the specific bank
+  *          This parameter can be one of the following values:
+  *            @arg FLASH_BANK_1: Bank1 to be erased
+  *            @arg FLASH_BANK_2: Bank2 to be erased
+  *            @arg FLASH_BANK_BOTH: Bank1 and Bank2 to be erased
+  *
+  * @retval HAL Status
+  */
+static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WRPSector, uint32_t Banks)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the parameters */
+  assert_param(IS_OB_WRP_SECTOR(WRPSector));
+  assert_param(IS_FLASH_BANK(Banks));
+
+  /* Wait for last operation to be completed */
+  status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+
+  if (status == HAL_OK)
+  {
+    if (((WRPSector == OB_WRP_SECTOR_All) && ((Banks == FLASH_BANK_1) || (Banks == FLASH_BANK_BOTH))) ||
+        (WRPSector < OB_WRP_SECTOR_12))
+    {
+      if (WRPSector == OB_WRP_SECTOR_All)
+      {
+        /*Write protection on all sector of BANK1*/
+        *(__IO uint16_t *)OPTCR_BYTE2_ADDRESS |= (uint16_t)(WRPSector >> 12);
+      }
+      else
+      {
+        /*Write protection done on sectors of BANK1*/
+        *(__IO uint16_t *)OPTCR_BYTE2_ADDRESS |= (uint16_t)WRPSector;
+      }
+    }
+    else
+    {
+      /*Write protection done on sectors of BANK2*/
+      *(__IO uint16_t *)OPTCR1_BYTE2_ADDRESS |= (uint16_t)(WRPSector >> 12);
+    }
+
+    /*Write protection on all sector  of BANK2*/
+    if ((WRPSector == OB_WRP_SECTOR_All) && (Banks == FLASH_BANK_BOTH))
+    {
+      /* Wait for last operation to be completed */
+      status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+
+      if (status == HAL_OK)
+      {
+        *(__IO uint16_t *)OPTCR1_BYTE2_ADDRESS |= (uint16_t)(WRPSector >> 12);
+      }
+    }
+
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Configure the Dual Bank Boot.
+  *
+  * @note   This function can be used only for STM32F42xxx/43xxx devices.
+  *
+  * @param  BootConfig specifies the Dual Bank Boot Option byte.
+  *          This parameter can be one of the following values:
+  *            @arg OB_Dual_BootEnabled: Dual Bank Boot Enable
+  *            @arg OB_Dual_BootDisabled: Dual Bank Boot Disabled
+  * @retval None
+  */
+static HAL_StatusTypeDef FLASH_OB_BootConfig(uint8_t BootConfig)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the parameters */
+  assert_param(IS_OB_BOOT(BootConfig));
+
+  /* Wait for last operation to be completed */
+  status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+
+  if (status == HAL_OK)
+  {
+    /* Set Dual Bank Boot */
+    *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS &= (~FLASH_OPTCR_BFB2);
+    *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS |= BootConfig;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Enable the read/write protection (PCROP) of the desired
+  *         sectors of Bank 1 and/or Bank 2.
+  * @note   This function can be used only for STM32F42xxx/43xxx devices.
+  * @param  SectorBank1 Specifies the sector(s) to be read/write protected or unprotected for bank1.
+  *          This parameter can be one of the following values:
+  *            @arg OB_PCROP: A value between OB_PCROP_SECTOR_0 and OB_PCROP_SECTOR_11
+  *            @arg OB_PCROP_SECTOR__All
+  * @param  SectorBank2 Specifies the sector(s) to be read/write protected or unprotected for bank2.
+  *          This parameter can be one of the following values:
+  *            @arg OB_PCROP: A value between OB_PCROP_SECTOR_12 and OB_PCROP_SECTOR_23
+  *            @arg OB_PCROP_SECTOR__All
+  * @param  Banks Enable PCROP protection on all the sectors for the specific bank
+  *          This parameter can be one of the following values:
+  *            @arg FLASH_BANK_1: WRP on all sectors of bank1
+  *            @arg FLASH_BANK_2: WRP on all sectors of bank2
+  *            @arg FLASH_BANK_BOTH: WRP on all sectors of bank1 & bank2
+  *
+  * @retval HAL Status
+  */
+static HAL_StatusTypeDef FLASH_OB_EnablePCROP(uint32_t SectorBank1, uint32_t SectorBank2, uint32_t Banks)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  assert_param(IS_FLASH_BANK(Banks));
+
+  /* Wait for last operation to be completed */
+  status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+
+  if (status == HAL_OK)
+  {
+    if ((Banks == FLASH_BANK_1) || (Banks == FLASH_BANK_BOTH))
+    {
+      assert_param(IS_OB_PCROP(SectorBank1));
+      /*Write protection done on sectors of BANK1*/
+      *(__IO uint16_t *)OPTCR_BYTE2_ADDRESS |= (uint16_t)SectorBank1;
+    }
+    else
+    {
+      assert_param(IS_OB_PCROP(SectorBank2));
+      /*Write protection done on sectors of BANK2*/
+      *(__IO uint16_t *)OPTCR1_BYTE2_ADDRESS |= (uint16_t)SectorBank2;
+    }
+
+    /*Write protection on all sector  of BANK2*/
+    if (Banks == FLASH_BANK_BOTH)
+    {
+      assert_param(IS_OB_PCROP(SectorBank2));
+      /* Wait for last operation to be completed */
+      status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+
+      if (status == HAL_OK)
+      {
+        /*Write protection done on sectors of BANK2*/
+        *(__IO uint16_t *)OPTCR1_BYTE2_ADDRESS |= (uint16_t)SectorBank2;
+      }
+    }
+
+  }
+
+  return status;
+}
+
+
+/**
+  * @brief  Disable the read/write protection (PCROP) of the desired
+  *         sectors  of Bank 1 and/or Bank 2.
+  * @note   This function can be used only for STM32F42xxx/43xxx devices.
+  * @param  SectorBank1 specifies the sector(s) to be read/write protected or unprotected for bank1.
+  *          This parameter can be one of the following values:
+  *            @arg OB_PCROP: A value between OB_PCROP_SECTOR_0 and OB_PCROP_SECTOR_11
+  *            @arg OB_PCROP_SECTOR__All
+  * @param  SectorBank2 Specifies the sector(s) to be read/write protected or unprotected for bank2.
+  *          This parameter can be one of the following values:
+  *            @arg OB_PCROP: A value between OB_PCROP_SECTOR_12 and OB_PCROP_SECTOR_23
+  *            @arg OB_PCROP_SECTOR__All
+  * @param  Banks Disable PCROP protection on all the sectors for the specific bank
+  *          This parameter can be one of the following values:
+  *            @arg FLASH_BANK_1: WRP on all sectors of bank1
+  *            @arg FLASH_BANK_2: WRP on all sectors of bank2
+  *            @arg FLASH_BANK_BOTH: WRP on all sectors of bank1 & bank2
+  *
+  * @retval HAL Status
+  */
+static HAL_StatusTypeDef FLASH_OB_DisablePCROP(uint32_t SectorBank1, uint32_t SectorBank2, uint32_t Banks)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the parameters */
+  assert_param(IS_FLASH_BANK(Banks));
+
+  /* Wait for last operation to be completed */
+  status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+
+  if (status == HAL_OK)
+  {
+    if ((Banks == FLASH_BANK_1) || (Banks == FLASH_BANK_BOTH))
+    {
+      assert_param(IS_OB_PCROP(SectorBank1));
+      /*Write protection done on sectors of BANK1*/
+      *(__IO uint16_t *)OPTCR_BYTE2_ADDRESS &= (~SectorBank1);
+    }
+    else
+    {
+      /*Write protection done on sectors of BANK2*/
+      assert_param(IS_OB_PCROP(SectorBank2));
+      *(__IO uint16_t *)OPTCR1_BYTE2_ADDRESS &= (~SectorBank2);
+    }
+
+    /*Write protection on all sector  of BANK2*/
+    if (Banks == FLASH_BANK_BOTH)
+    {
+      assert_param(IS_OB_PCROP(SectorBank2));
+      /* Wait for last operation to be completed */
+      status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+
+      if (status == HAL_OK)
+      {
+        /*Write protection done on sectors of BANK2*/
+        *(__IO uint16_t *)OPTCR1_BYTE2_ADDRESS &= (~SectorBank2);
+      }
+    }
+
+  }
+
+  return status;
+
+}
+
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
+
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
+    defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) ||\
+    defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F412Zx) ||\
+    defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) ||\
+    defined(STM32F423xx)
+/**
+  * @brief  Mass erase of FLASH memory
+  * @param  VoltageRange The device voltage range which defines the erase parallelism.
+  *          This parameter can be one of the following values:
+  *            @arg FLASH_VOLTAGE_RANGE_1: when the device voltage range is 1.8V to 2.1V,
+  *                                  the operation will be done by byte (8-bit)
+  *            @arg FLASH_VOLTAGE_RANGE_2: when the device voltage range is 2.1V to 2.7V,
+  *                                  the operation will be done by half word (16-bit)
+  *            @arg FLASH_VOLTAGE_RANGE_3: when the device voltage range is 2.7V to 3.6V,
+  *                                  the operation will be done by word (32-bit)
+  *            @arg FLASH_VOLTAGE_RANGE_4: when the device voltage range is 2.7V to 3.6V + External Vpp,
+  *                                  the operation will be done by double word (64-bit)
+  *
+  * @param  Banks Banks to be erased
+  *          This parameter can be one of the following values:
+  *            @arg FLASH_BANK_1: Bank1 to be erased
+  *
+  * @retval None
+  */
+static void FLASH_MassErase(uint8_t VoltageRange, uint32_t Banks)
+{
+  /* Check the parameters */
+  assert_param(IS_VOLTAGERANGE(VoltageRange));
+  assert_param(IS_FLASH_BANK(Banks));
+
+  /* If the previous operation is completed, proceed to erase all sectors */
+  CLEAR_BIT(FLASH->CR, FLASH_CR_PSIZE);
+  FLASH->CR |= FLASH_CR_MER;
+  FLASH->CR |= FLASH_CR_STRT | ((uint32_t)VoltageRange << 8U);
+}
+
+/**
+  * @brief  Erase the specified FLASH memory sector
+  * @param  Sector FLASH sector to erase
+  *         The value of this parameter depend on device used within the same series
+  * @param  VoltageRange The device voltage range which defines the erase parallelism.
+  *          This parameter can be one of the following values:
+  *            @arg FLASH_VOLTAGE_RANGE_1: when the device voltage range is 1.8V to 2.1V,
+  *                                  the operation will be done by byte (8-bit)
+  *            @arg FLASH_VOLTAGE_RANGE_2: when the device voltage range is 2.1V to 2.7V,
+  *                                  the operation will be done by half word (16-bit)
+  *            @arg FLASH_VOLTAGE_RANGE_3: when the device voltage range is 2.7V to 3.6V,
+  *                                  the operation will be done by word (32-bit)
+  *            @arg FLASH_VOLTAGE_RANGE_4: when the device voltage range is 2.7V to 3.6V + External Vpp,
+  *                                  the operation will be done by double word (64-bit)
+  *
+  * @retval None
+  */
+void FLASH_Erase_Sector(uint32_t Sector, uint8_t VoltageRange)
+{
+  uint32_t tmp_psize = 0U;
+
+  /* Check the parameters */
+  assert_param(IS_FLASH_SECTOR(Sector));
+  assert_param(IS_VOLTAGERANGE(VoltageRange));
+
+  if (VoltageRange == FLASH_VOLTAGE_RANGE_1)
+  {
+    tmp_psize = FLASH_PSIZE_BYTE;
+  }
+  else if (VoltageRange == FLASH_VOLTAGE_RANGE_2)
+  {
+    tmp_psize = FLASH_PSIZE_HALF_WORD;
+  }
+  else if (VoltageRange == FLASH_VOLTAGE_RANGE_3)
+  {
+    tmp_psize = FLASH_PSIZE_WORD;
+  }
+  else
+  {
+    tmp_psize = FLASH_PSIZE_DOUBLE_WORD;
+  }
+
+  /* If the previous operation is completed, proceed to erase the sector */
+  CLEAR_BIT(FLASH->CR, FLASH_CR_PSIZE);
+  FLASH->CR |= tmp_psize;
+  CLEAR_BIT(FLASH->CR, FLASH_CR_SNB);
+  FLASH->CR |= FLASH_CR_SER | (Sector << FLASH_CR_SNB_Pos);
+  FLASH->CR |= FLASH_CR_STRT;
+}
+
+/**
+  * @brief  Enable the write protection of the desired bank 1 sectors
+  *
+  * @note   When the memory read protection level is selected (RDP level = 1),
+  *         it is not possible to program or erase the flash sector i if CortexM4
+  *         debug features are connected or boot code is executed in RAM, even if nWRPi = 1
+  * @note   Active value of nWRPi bits is inverted when PCROP mode is active (SPRMOD =1).
+  *
+  * @param  WRPSector specifies the sector(s) to be write protected.
+  *         The value of this parameter depend on device used within the same series
+  *
+  * @param  Banks Enable write protection on all the sectors for the specific bank
+  *          This parameter can be one of the following values:
+  *            @arg FLASH_BANK_1: WRP on all sectors of bank1
+  *
+  * @retval HAL Status
+  */
+static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WRPSector, uint32_t Banks)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the parameters */
+  assert_param(IS_OB_WRP_SECTOR(WRPSector));
+  assert_param(IS_FLASH_BANK(Banks));
+
+  /* Wait for last operation to be completed */
+  status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+
+  if (status == HAL_OK)
+  {
+    *(__IO uint16_t *)OPTCR_BYTE2_ADDRESS &= (~WRPSector);
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Disable the write protection of the desired bank 1 sectors
+  *
+  * @note   When the memory read protection level is selected (RDP level = 1),
+  *         it is not possible to program or erase the flash sector i if CortexM4
+  *         debug features are connected or boot code is executed in RAM, even if nWRPi = 1
+  * @note   Active value of nWRPi bits is inverted when PCROP mode is active (SPRMOD =1).
+  *
+  * @param  WRPSector specifies the sector(s) to be write protected.
+  *         The value of this parameter depend on device used within the same series
+  *
+  * @param  Banks Enable write protection on all the sectors for the specific bank
+  *          This parameter can be one of the following values:
+  *            @arg FLASH_BANK_1: WRP on all sectors of bank1
+  *
+  * @retval HAL Status
+  */
+static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WRPSector, uint32_t Banks)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the parameters */
+  assert_param(IS_OB_WRP_SECTOR(WRPSector));
+  assert_param(IS_FLASH_BANK(Banks));
+
+  /* Wait for last operation to be completed */
+  status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+
+  if (status == HAL_OK)
+  {
+    *(__IO uint16_t *)OPTCR_BYTE2_ADDRESS |= (uint16_t)WRPSector;
+  }
+
+  return status;
+}
+#endif /* STM32F40xxx || STM32F41xxx || STM32F401xx || STM32F410xx || STM32F411xE || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx
+          STM32F413xx || STM32F423xx */
+
+#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) ||\
+    defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) ||\
+    defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
+/**
+  * @brief  Enable the read/write protection (PCROP) of the desired sectors.
+  * @note   This function can be used only for STM32F401xx devices.
+  * @param  Sector specifies the sector(s) to be read/write protected or unprotected.
+  *          This parameter can be one of the following values:
+  *            @arg OB_PCROP: A value between OB_PCROP_Sector0 and OB_PCROP_Sector5
+  *            @arg OB_PCROP_Sector_All
+  * @retval HAL Status
+  */
+static HAL_StatusTypeDef FLASH_OB_EnablePCROP(uint32_t Sector)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the parameters */
+  assert_param(IS_OB_PCROP(Sector));
+
+  /* Wait for last operation to be completed */
+  status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+
+  if (status == HAL_OK)
+  {
+    *(__IO uint16_t *)OPTCR_BYTE2_ADDRESS |= (uint16_t)Sector;
+  }
+
+  return status;
+}
+
+
+/**
+  * @brief  Disable the read/write protection (PCROP) of the desired sectors.
+  * @note   This function can be used only for STM32F401xx devices.
+  * @param  Sector specifies the sector(s) to be read/write protected or unprotected.
+  *          This parameter can be one of the following values:
+  *            @arg OB_PCROP: A value between OB_PCROP_Sector0 and OB_PCROP_Sector5
+  *            @arg OB_PCROP_Sector_All
+  * @retval HAL Status
+  */
+static HAL_StatusTypeDef FLASH_OB_DisablePCROP(uint32_t Sector)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the parameters */
+  assert_param(IS_OB_PCROP(Sector));
+
+  /* Wait for last operation to be completed */
+  status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+
+  if (status == HAL_OK)
+  {
+    *(__IO uint16_t *)OPTCR_BYTE2_ADDRESS &= (~Sector);
+  }
+
+  return status;
+
+}
+#endif /* STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx
+          STM32F413xx || STM32F423xx */
+
+/**
+  * @brief  Set the read protection level.
+  * @param  Level specifies the read protection level.
+  *          This parameter can be one of the following values:
+  *            @arg OB_RDP_LEVEL_0: No protection
+  *            @arg OB_RDP_LEVEL_1: Read protection of the memory
+  *            @arg OB_RDP_LEVEL_2: Full chip protection
+  *
+  * @note WARNING: When enabling OB_RDP level 2 it's no more possible to go back to level 1 or 0
+  *
+  * @retval HAL Status
+  */
+static HAL_StatusTypeDef FLASH_OB_RDP_LevelConfig(uint8_t Level)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the parameters */
+  assert_param(IS_OB_RDP_LEVEL(Level));
+
+  /* Wait for last operation to be completed */
+  status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+
+  if (status == HAL_OK)
+  {
+    *(__IO uint8_t *)OPTCR_BYTE1_ADDRESS = Level;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Program the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY.
+  * @param  Iwdg Selects the IWDG mode
+  *          This parameter can be one of the following values:
+  *            @arg OB_IWDG_SW: Software IWDG selected
+  *            @arg OB_IWDG_HW: Hardware IWDG selected
+  * @param  Stop Reset event when entering STOP mode.
+  *          This parameter  can be one of the following values:
+  *            @arg OB_STOP_NO_RST: No reset generated when entering in STOP
+  *            @arg OB_STOP_RST: Reset generated when entering in STOP
+  * @param  Stdby Reset event when entering Standby mode.
+  *          This parameter  can be one of the following values:
+  *            @arg OB_STDBY_NO_RST: No reset generated when entering in STANDBY
+  *            @arg OB_STDBY_RST: Reset generated when entering in STANDBY
+  * @retval HAL Status
+  */
+static HAL_StatusTypeDef FLASH_OB_UserConfig(uint8_t Iwdg, uint8_t Stop, uint8_t Stdby)
+{
+  uint8_t optiontmp = 0xFF;
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the parameters */
+  assert_param(IS_OB_IWDG_SOURCE(Iwdg));
+  assert_param(IS_OB_STOP_SOURCE(Stop));
+  assert_param(IS_OB_STDBY_SOURCE(Stdby));
+
+  /* Wait for last operation to be completed */
+  status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+
+  if (status == HAL_OK)
+  {
+    /* Mask OPTLOCK, OPTSTRT, BOR_LEV and BFB2 bits */
+    optiontmp = (uint8_t)((*(__IO uint8_t *)OPTCR_BYTE0_ADDRESS) & (uint8_t)0x1F);
+
+    /* Update User Option Byte */
+    *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS = Iwdg | (uint8_t)(Stdby | (uint8_t)(Stop | ((uint8_t)optiontmp)));
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Set the BOR Level.
+  * @param  Level specifies the Option Bytes BOR Reset Level.
+  *          This parameter can be one of the following values:
+  *            @arg OB_BOR_LEVEL3: Supply voltage ranges from 2.7 to 3.6 V
+  *            @arg OB_BOR_LEVEL2: Supply voltage ranges from 2.4 to 2.7 V
+  *            @arg OB_BOR_LEVEL1: Supply voltage ranges from 2.1 to 2.4 V
+  *            @arg OB_BOR_OFF: Supply voltage ranges from 1.62 to 2.1 V
+  * @retval HAL Status
+  */
+static HAL_StatusTypeDef FLASH_OB_BOR_LevelConfig(uint8_t Level)
+{
+  /* Check the parameters */
+  assert_param(IS_OB_BOR_LEVEL(Level));
+
+  /* Set the BOR Level */
+  *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS &= (~FLASH_OPTCR_BOR_LEV);
+  *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS |= Level;
+
+  return HAL_OK;
+
+}
+
+/**
+  * @brief  Return the FLASH User Option Byte value.
+  * @retval uint8_t FLASH User Option Bytes values: IWDG_SW(Bit0), RST_STOP(Bit1)
+  *         and RST_STDBY(Bit2).
+  */
+static uint8_t FLASH_OB_GetUser(void)
+{
+  /* Return the User Option Byte */
+  return ((uint8_t)(FLASH->OPTCR & 0xE0));
+}
+
+/**
+  * @brief  Return the FLASH Write Protection Option Bytes value.
+  * @retval uint16_t FLASH Write Protection Option Bytes value
+  */
+static uint16_t FLASH_OB_GetWRP(void)
+{
+  /* Return the FLASH write protection Register value */
+  return (*(__IO uint16_t *)(OPTCR_BYTE2_ADDRESS));
+}
+
+/**
+  * @brief  Returns the FLASH Read Protection level.
+  * @retval FLASH ReadOut Protection Status:
+  *         This parameter can be one of the following values:
+  *            @arg OB_RDP_LEVEL_0: No protection
+  *            @arg OB_RDP_LEVEL_1: Read protection of the memory
+  *            @arg OB_RDP_LEVEL_2: Full chip protection
+  */
+static uint8_t FLASH_OB_GetRDP(void)
+{
+  uint8_t readstatus = OB_RDP_LEVEL_0;
+
+  if (*(__IO uint8_t *)(OPTCR_BYTE1_ADDRESS) == (uint8_t)OB_RDP_LEVEL_2)
+  {
+    readstatus = OB_RDP_LEVEL_2;
+  }
+  else if (*(__IO uint8_t *)(OPTCR_BYTE1_ADDRESS) == (uint8_t)OB_RDP_LEVEL_0)
+  {
+    readstatus = OB_RDP_LEVEL_0;
+  }
+  else
+  {
+    readstatus = OB_RDP_LEVEL_1;
+  }
+
+  return readstatus;
+}
+
+/**
+  * @brief  Returns the FLASH BOR level.
+  * @retval uint8_t The FLASH BOR level:
+  *           - OB_BOR_LEVEL3: Supply voltage ranges from 2.7 to 3.6 V
+  *           - OB_BOR_LEVEL2: Supply voltage ranges from 2.4 to 2.7 V
+  *           - OB_BOR_LEVEL1: Supply voltage ranges from 2.1 to 2.4 V
+  *           - OB_BOR_OFF   : Supply voltage ranges from 1.62 to 2.1 V
+  */
+static uint8_t FLASH_OB_GetBOR(void)
+{
+  /* Return the FLASH BOR level */
+  return (uint8_t)(*(__IO uint8_t *)(OPTCR_BYTE0_ADDRESS) & (uint8_t)0x0C);
+}
+
+/**
+  * @brief  Flush the instruction and data caches
+  * @retval None
+  */
+void FLASH_FlushCaches(void)
+{
+  /* Flush instruction cache  */
+  if (READ_BIT(FLASH->ACR, FLASH_ACR_ICEN) != RESET)
+  {
+    /* Disable instruction cache  */
+    __HAL_FLASH_INSTRUCTION_CACHE_DISABLE();
+    /* Reset instruction cache */
+    __HAL_FLASH_INSTRUCTION_CACHE_RESET();
+    /* Enable instruction cache */
+    __HAL_FLASH_INSTRUCTION_CACHE_ENABLE();
+  }
+
+  /* Flush data cache */
+  if (READ_BIT(FLASH->ACR, FLASH_ACR_DCEN) != RESET)
+  {
+    /* Disable data cache  */
+    __HAL_FLASH_DATA_CACHE_DISABLE();
+    /* Reset data cache */
+    __HAL_FLASH_DATA_CACHE_RESET();
+    /* Enable data cache */
+    __HAL_FLASH_DATA_CACHE_ENABLE();
+  }
+}
+
+/**
+  * @}
+  */
+
+#endif /* HAL_FLASH_MODULE_ENABLED */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
diff --git a/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c
new file mode 100644
index 0000000..fdc5a4c
--- /dev/null
+++ b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c
@@ -0,0 +1,172 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hal_flash_ramfunc.c
+  * @author  MCD Application Team
+  * @brief   FLASH RAMFUNC module driver.
+  *          This file provides a FLASH firmware functions which should be 
+  *          executed from internal SRAM
+  *            + Stop/Start the flash interface while System Run
+  *            + Enable/Disable the flash sleep while System Run
+  @verbatim
+  ==============================================================================
+                    ##### APIs executed from Internal RAM #####
+  ==============================================================================
+  [..]
+    *** ARM Compiler ***
+    --------------------
+    [..] RAM functions are defined using the toolchain options. 
+         Functions that are be executed in RAM should reside in a separate
+         source module. Using the 'Options for File' dialog you can simply change
+         the 'Code / Const' area of a module to a memory space in physical RAM.
+         Available memory areas are declared in the 'Target' tab of the 
+         Options for Target' dialog.
+
+    *** ICCARM Compiler ***
+    -----------------------
+    [..] RAM functions are defined using a specific toolchain keyword "__ramfunc".
+
+    *** GNU Compiler ***
+    --------------------
+    [..] RAM functions are defined using a specific toolchain attribute
+         "__attribute__((section(".RamFunc")))".
+  
+  @endverbatim         
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file in
+  * the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  ******************************************************************************
+  */ 
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup FLASH_RAMFUNC FLASH RAMFUNC
+  * @brief FLASH functions executed from RAM
+  * @{
+  */
+#ifdef HAL_FLASH_MODULE_ENABLED
+#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
+    defined(STM32F412Rx) || defined(STM32F412Cx)
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup FLASH_RAMFUNC_Exported_Functions FLASH RAMFUNC Exported Functions
+  * @{
+  */
+
+/** @defgroup FLASH_RAMFUNC_Exported_Functions_Group1 Peripheral features functions executed from internal RAM 
+  *  @brief Peripheral Extended features functions 
+  *
+@verbatim   
+
+ ===============================================================================
+                      ##### ramfunc functions #####
+ ===============================================================================  
+    [..]
+    This subsection provides a set of functions that should be executed from RAM 
+    transfers.
+    
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief Stop the flash interface while System Run
+  * @note  This mode is only available for STM32F41xxx/STM32F446xx devices. 
+  * @note  This mode couldn't be set while executing with the flash itself. 
+  *        It should be done with specific routine executed from RAM.     
+  * @retval HAL status
+  */
+__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_StopFlashInterfaceClk(void)
+{
+  /* Enable Power ctrl clock */
+  __HAL_RCC_PWR_CLK_ENABLE();
+  /* Stop the flash interface while System Run */  
+  SET_BIT(PWR->CR, PWR_CR_FISSR);
+   
+  return HAL_OK;
+}
+
+/**
+  * @brief Start the flash interface while System Run
+  * @note  This mode is only available for STM32F411xx/STM32F446xx devices. 
+  * @note  This mode couldn't be set while executing with the flash itself. 
+  *        It should be done with specific routine executed from RAM.     
+  * @retval HAL status
+  */
+__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_StartFlashInterfaceClk(void)
+{
+  /* Enable Power ctrl clock */
+  __HAL_RCC_PWR_CLK_ENABLE();
+  /* Start the flash interface while System Run */
+  CLEAR_BIT(PWR->CR, PWR_CR_FISSR);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief Enable the flash sleep while System Run
+  * @note  This mode is only available for STM32F41xxx/STM32F446xx devices. 
+  * @note  This mode could n't be set while executing with the flash itself. 
+  *        It should be done with specific routine executed from RAM.     
+  * @retval HAL status
+  */
+__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_EnableFlashSleepMode(void)
+{
+  /* Enable Power ctrl clock */
+  __HAL_RCC_PWR_CLK_ENABLE();
+  /* Enable the flash sleep while System Run */
+  SET_BIT(PWR->CR, PWR_CR_FMSSR);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief Disable the flash sleep while System Run
+  * @note  This mode is only available for STM32F41xxx/STM32F446xx devices. 
+  * @note  This mode couldn't be set while executing with the flash itself. 
+  *        It should be done with specific routine executed from RAM.     
+  * @retval HAL status
+  */
+__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_DisableFlashSleepMode(void)
+{
+  /* Enable Power ctrl clock */
+  __HAL_RCC_PWR_CLK_ENABLE();
+  /* Disable the flash sleep while System Run */
+  CLEAR_BIT(PWR->CR, PWR_CR_FMSSR);
+  
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* STM32F410xx || STM32F411xE || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */
+#endif /* HAL_FLASH_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
diff --git a/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c
new file mode 100644
index 0000000..184fe58
--- /dev/null
+++ b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c
@@ -0,0 +1,533 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hal_gpio.c
+  * @author  MCD Application Team
+  * @brief   GPIO HAL module driver.
+  *          This file provides firmware functions to manage the following 
+  *          functionalities of the General Purpose Input/Output (GPIO) peripheral:
+  *           + Initialization and de-initialization functions
+  *           + IO operation functions
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  @verbatim
+  ==============================================================================
+                    ##### GPIO Peripheral features #####
+  ==============================================================================
+  [..] 
+  Subject to the specific hardware characteristics of each I/O port listed in the datasheet, each
+  port bit of the General Purpose IO (GPIO) Ports, can be individually configured by software
+  in several modes:
+  (+) Input mode 
+  (+) Analog mode
+  (+) Output mode
+  (+) Alternate function mode
+  (+) External interrupt/event lines
+
+  [..]  
+  During and just after reset, the alternate functions and external interrupt  
+  lines are not active and the I/O ports are configured in input floating mode.
+  
+  [..]   
+  All GPIO pins have weak internal pull-up and pull-down resistors, which can be 
+  activated or not.
+
+  [..]
+  In Output or Alternate mode, each IO can be configured on open-drain or push-pull
+  type and the IO speed can be selected depending on the VDD value.
+
+  [..]  
+  All ports have external interrupt/event capability. To use external interrupt 
+  lines, the port must be configured in input mode. All available GPIO pins are 
+  connected to the 16 external interrupt/event lines from EXTI0 to EXTI15.
+  
+  [..]
+  The external interrupt/event controller consists of up to 23 edge detectors 
+  (16 lines are connected to GPIO) for generating event/interrupt requests (each 
+  input line can be independently configured to select the type (interrupt or event) 
+  and the corresponding trigger event (rising or falling or both). Each line can 
+  also be masked independently. 
+
+                     ##### How to use this driver #####
+  ==============================================================================  
+  [..]
+    (#) Enable the GPIO AHB clock using the following function: __HAL_RCC_GPIOx_CLK_ENABLE(). 
+
+    (#) Configure the GPIO pin(s) using HAL_GPIO_Init().
+        (++) Configure the IO mode using "Mode" member from GPIO_InitTypeDef structure
+        (++) Activate Pull-up, Pull-down resistor using "Pull" member from GPIO_InitTypeDef 
+             structure.
+        (++) In case of Output or alternate function mode selection: the speed is 
+             configured through "Speed" member from GPIO_InitTypeDef structure.
+        (++) In alternate mode is selection, the alternate function connected to the IO
+             is configured through "Alternate" member from GPIO_InitTypeDef structure.
+        (++) Analog mode is required when a pin is to be used as ADC channel 
+             or DAC output.
+        (++) In case of external interrupt/event selection the "Mode" member from 
+             GPIO_InitTypeDef structure select the type (interrupt or event) and 
+             the corresponding trigger event (rising or falling or both).
+
+    (#) In case of external interrupt/event mode selection, configure NVIC IRQ priority 
+        mapped to the EXTI line using HAL_NVIC_SetPriority() and enable it using
+        HAL_NVIC_EnableIRQ().
+         
+    (#) To get the level of a pin configured in input mode use HAL_GPIO_ReadPin().
+            
+    (#) To set/reset the level of a pin configured in output mode use 
+        HAL_GPIO_WritePin()/HAL_GPIO_TogglePin().
+    
+    (#) To lock pin configuration until next reset use HAL_GPIO_LockPin().
+
+                 
+    (#) During and just after reset, the alternate functions are not 
+        active and the GPIO pins are configured in input floating mode (except JTAG
+        pins).
+  
+    (#) The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as general purpose 
+        (PC14 and PC15, respectively) when the LSE oscillator is off. The LSE has 
+        priority over the GPIO function.
+  
+    (#) The HSE oscillator pins OSC_IN/OSC_OUT can be used as 
+        general purpose PH0 and PH1, respectively, when the HSE oscillator is off. 
+        The HSE has priority over the GPIO function.
+  
+  @endverbatim
+  ******************************************************************************
+  */ 
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup GPIO GPIO
+  * @brief GPIO HAL module driver
+  * @{
+  */
+
+#ifdef HAL_GPIO_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @addtogroup GPIO_Private_Constants GPIO Private Constants
+  * @{
+  */
+
+#define GPIO_NUMBER           16U
+/**
+  * @}
+  */
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup GPIO_Exported_Functions GPIO Exported Functions
+  * @{
+  */
+
+/** @defgroup GPIO_Exported_Functions_Group1 Initialization and de-initialization functions
+  *  @brief    Initialization and Configuration functions
+  *
+@verbatim    
+ ===============================================================================
+              ##### Initialization and de-initialization functions #####
+ ===============================================================================
+  [..]
+    This section provides functions allowing to initialize and de-initialize the GPIOs
+    to be ready for use.
+ 
+@endverbatim
+  * @{
+  */
+
+
+/**
+  * @brief  Initializes the GPIOx peripheral according to the specified parameters in the GPIO_Init.
+  * @param  GPIOx where x can be (A..K) to select the GPIO peripheral for STM32F429X device or
+  *                      x can be (A..I) to select the GPIO peripheral for STM32F40XX and STM32F427X devices.
+  * @param  GPIO_Init pointer to a GPIO_InitTypeDef structure that contains
+  *         the configuration information for the specified GPIO peripheral.
+  * @retval None
+  */
+void HAL_GPIO_Init(GPIO_TypeDef  *GPIOx, GPIO_InitTypeDef *GPIO_Init)
+{
+  uint32_t position;
+  uint32_t ioposition = 0x00U;
+  uint32_t iocurrent = 0x00U;
+  uint32_t temp = 0x00U;
+
+  /* Check the parameters */
+  assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
+  assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
+  assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
+
+  /* Configure the port pins */
+  for(position = 0U; position < GPIO_NUMBER; position++)
+  {
+    /* Get the IO position */
+    ioposition = 0x01U << position;
+    /* Get the current IO position */
+    iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition;
+
+    if(iocurrent == ioposition)
+    {
+      /*--------------------- GPIO Mode Configuration ------------------------*/
+      /* In case of Output or Alternate function mode selection */
+      if(((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || \
+          (GPIO_Init->Mode & GPIO_MODE) == MODE_AF)
+      {
+        /* Check the Speed parameter */
+        assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
+        /* Configure the IO Speed */
+        temp = GPIOx->OSPEEDR; 
+        temp &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2U));
+        temp |= (GPIO_Init->Speed << (position * 2U));
+        GPIOx->OSPEEDR = temp;
+
+        /* Configure the IO Output Type */
+        temp = GPIOx->OTYPER;
+        temp &= ~(GPIO_OTYPER_OT_0 << position) ;
+        temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position);
+        GPIOx->OTYPER = temp;
+       }
+
+      if((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG)
+      {
+        /* Check the parameters */
+        assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
+        
+        /* Activate the Pull-up or Pull down resistor for the current IO */
+        temp = GPIOx->PUPDR;
+        temp &= ~(GPIO_PUPDR_PUPDR0 << (position * 2U));
+        temp |= ((GPIO_Init->Pull) << (position * 2U));
+        GPIOx->PUPDR = temp;
+      }
+
+      /* In case of Alternate function mode selection */
+      if((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)
+      {
+        /* Check the Alternate function parameter */
+        assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
+        /* Configure Alternate function mapped with the current IO */
+        temp = GPIOx->AFR[position >> 3U];
+        temp &= ~(0xFU << ((uint32_t)(position & 0x07U) * 4U)) ;
+        temp |= ((uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & 0x07U) * 4U));
+        GPIOx->AFR[position >> 3U] = temp;
+      }
+
+      /* Configure IO Direction mode (Input, Output, Alternate or Analog) */
+      temp = GPIOx->MODER;
+      temp &= ~(GPIO_MODER_MODER0 << (position * 2U));
+      temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2U));
+      GPIOx->MODER = temp;
+
+      /*--------------------- EXTI Mode Configuration ------------------------*/
+      /* Configure the External Interrupt or event for the current IO */
+      if((GPIO_Init->Mode & EXTI_MODE) != 0x00U)
+      {
+        /* Enable SYSCFG Clock */
+        __HAL_RCC_SYSCFG_CLK_ENABLE();
+
+        temp = SYSCFG->EXTICR[position >> 2U];
+        temp &= ~(0x0FU << (4U * (position & 0x03U)));
+        temp |= ((uint32_t)(GPIO_GET_INDEX(GPIOx)) << (4U * (position & 0x03U)));
+        SYSCFG->EXTICR[position >> 2U] = temp;
+
+        /* Clear Rising Falling edge configuration */
+        temp = EXTI->RTSR;
+        temp &= ~((uint32_t)iocurrent);
+        if((GPIO_Init->Mode & TRIGGER_RISING) != 0x00U)
+        {
+          temp |= iocurrent;
+        }
+        EXTI->RTSR = temp;
+
+        temp = EXTI->FTSR;
+        temp &= ~((uint32_t)iocurrent);
+        if((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00U)
+        {
+          temp |= iocurrent;
+        }
+        EXTI->FTSR = temp;
+
+        temp = EXTI->EMR;
+        temp &= ~((uint32_t)iocurrent);
+        if((GPIO_Init->Mode & EXTI_EVT) != 0x00U)
+        {
+          temp |= iocurrent;
+        }
+        EXTI->EMR = temp;
+
+        /* Clear EXTI line configuration */
+        temp = EXTI->IMR;
+        temp &= ~((uint32_t)iocurrent);
+        if((GPIO_Init->Mode & EXTI_IT) != 0x00U)
+        {
+          temp |= iocurrent;
+        }
+        EXTI->IMR = temp;
+      }
+    }
+  }
+}
+
+/**
+  * @brief  De-initializes the GPIOx peripheral registers to their default reset values.
+  * @param  GPIOx where x can be (A..K) to select the GPIO peripheral for STM32F429X device or
+  *                      x can be (A..I) to select the GPIO peripheral for STM32F40XX and STM32F427X devices.
+  * @param  GPIO_Pin specifies the port bit to be written.
+  *          This parameter can be one of GPIO_PIN_x where x can be (0..15).
+  * @retval None
+  */
+void HAL_GPIO_DeInit(GPIO_TypeDef  *GPIOx, uint32_t GPIO_Pin)
+{
+  uint32_t position;
+  uint32_t ioposition = 0x00U;
+  uint32_t iocurrent = 0x00U;
+  uint32_t tmp = 0x00U;
+
+  /* Check the parameters */
+  assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
+  
+  /* Configure the port pins */
+  for(position = 0U; position < GPIO_NUMBER; position++)
+  {
+    /* Get the IO position */
+    ioposition = 0x01U << position;
+    /* Get the current IO position */
+    iocurrent = (GPIO_Pin) & ioposition;
+
+    if(iocurrent == ioposition)
+    {
+      /*------------------------- EXTI Mode Configuration --------------------*/
+      tmp = SYSCFG->EXTICR[position >> 2U];
+      tmp &= (0x0FU << (4U * (position & 0x03U)));
+      if(tmp == ((uint32_t)(GPIO_GET_INDEX(GPIOx)) << (4U * (position & 0x03U))))
+      {
+        /* Clear EXTI line configuration */
+        EXTI->IMR &= ~((uint32_t)iocurrent);
+        EXTI->EMR &= ~((uint32_t)iocurrent);
+        
+        /* Clear Rising Falling edge configuration */
+        EXTI->FTSR &= ~((uint32_t)iocurrent);
+        EXTI->RTSR &= ~((uint32_t)iocurrent);
+
+        /* Configure the External Interrupt or event for the current IO */
+        tmp = 0x0FU << (4U * (position & 0x03U));
+        SYSCFG->EXTICR[position >> 2U] &= ~tmp;
+      }
+
+      /*------------------------- GPIO Mode Configuration --------------------*/
+      /* Configure IO Direction in Input Floating Mode */
+      GPIOx->MODER &= ~(GPIO_MODER_MODER0 << (position * 2U));
+
+      /* Configure the default Alternate Function in current IO */
+      GPIOx->AFR[position >> 3U] &= ~(0xFU << ((uint32_t)(position & 0x07U) * 4U)) ;
+
+      /* Deactivate the Pull-up and Pull-down resistor for the current IO */
+      GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPDR0 << (position * 2U));
+
+      /* Configure the default value IO Output Type */
+      GPIOx->OTYPER  &= ~(GPIO_OTYPER_OT_0 << position) ;
+
+      /* Configure the default value for IO Speed */
+      GPIOx->OSPEEDR &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2U));
+    }
+  }
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup GPIO_Exported_Functions_Group2 IO operation functions 
+  *  @brief   GPIO Read and Write
+  *
+@verbatim
+ ===============================================================================
+                       ##### IO operation functions #####
+ ===============================================================================
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Reads the specified input port pin.
+  * @param  GPIOx where x can be (A..K) to select the GPIO peripheral for STM32F429X device or
+  *                      x can be (A..I) to select the GPIO peripheral for STM32F40XX and STM32F427X devices.
+  * @param  GPIO_Pin specifies the port bit to read.
+  *         This parameter can be GPIO_PIN_x where x can be (0..15).
+  * @retval The input port pin value.
+  */
+GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
+{
+  GPIO_PinState bitstatus;
+
+  /* Check the parameters */
+  assert_param(IS_GPIO_PIN(GPIO_Pin));
+
+  if((GPIOx->IDR & GPIO_Pin) != (uint32_t)GPIO_PIN_RESET)
+  {
+    bitstatus = GPIO_PIN_SET;
+  }
+  else
+  {
+    bitstatus = GPIO_PIN_RESET;
+  }
+  return bitstatus;
+}
+
+/**
+  * @brief  Sets or clears the selected data port bit.
+  *
+  * @note   This function uses GPIOx_BSRR register to allow atomic read/modify
+  *         accesses. In this way, there is no risk of an IRQ occurring between
+  *         the read and the modify access.
+  *
+  * @param  GPIOx where x can be (A..K) to select the GPIO peripheral for STM32F429X device or
+  *                      x can be (A..I) to select the GPIO peripheral for STM32F40XX and STM32F427X devices.
+  * @param  GPIO_Pin specifies the port bit to be written.
+  *          This parameter can be one of GPIO_PIN_x where x can be (0..15).
+  * @param  PinState specifies the value to be written to the selected bit.
+  *          This parameter can be one of the GPIO_PinState enum values:
+  *            @arg GPIO_PIN_RESET: to clear the port pin
+  *            @arg GPIO_PIN_SET: to set the port pin
+  * @retval None
+  */
+void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
+{
+  /* Check the parameters */
+  assert_param(IS_GPIO_PIN(GPIO_Pin));
+  assert_param(IS_GPIO_PIN_ACTION(PinState));
+
+  if(PinState != GPIO_PIN_RESET)
+  {
+    GPIOx->BSRR = GPIO_Pin;
+  }
+  else
+  {
+    GPIOx->BSRR = (uint32_t)GPIO_Pin << 16U;
+  }
+}
+
+/**
+  * @brief  Toggles the specified GPIO pins.
+  * @param  GPIOx Where x can be (A..K) to select the GPIO peripheral for STM32F429X device or
+  *                      x can be (A..I) to select the GPIO peripheral for STM32F40XX and STM32F427X devices.
+  * @param  GPIO_Pin Specifies the pins to be toggled.
+  * @retval None
+  */
+void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
+{
+  uint32_t odr;
+
+  /* Check the parameters */
+  assert_param(IS_GPIO_PIN(GPIO_Pin));
+
+  /* get current Output Data Register value */
+  odr = GPIOx->ODR;
+
+  /* Set selected pins that were at low level, and reset ones that were high */
+  GPIOx->BSRR = ((odr & GPIO_Pin) << GPIO_NUMBER) | (~odr & GPIO_Pin);
+}
+
+/**
+  * @brief  Locks GPIO Pins configuration registers.
+  * @note   The locked registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR,
+  *         GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH.
+  * @note   The configuration of the locked GPIO pins can no longer be modified
+  *         until the next reset.
+  * @param  GPIOx where x can be (A..F) to select the GPIO peripheral for STM32F4 family
+  * @param  GPIO_Pin specifies the port bit to be locked.
+  *         This parameter can be any combination of GPIO_PIN_x where x can be (0..15).
+  * @retval None
+  */
+HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
+{
+  __IO uint32_t tmp = GPIO_LCKR_LCKK;
+
+  /* Check the parameters */
+  assert_param(IS_GPIO_PIN(GPIO_Pin));
+
+  /* Apply lock key write sequence */
+  tmp |= GPIO_Pin;
+  /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */
+  GPIOx->LCKR = tmp;
+  /* Reset LCKx bit(s): LCKK='0' + LCK[15-0] */
+  GPIOx->LCKR = GPIO_Pin;
+  /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */
+  GPIOx->LCKR = tmp;
+  /* Read LCKR register. This read is mandatory to complete key lock sequence */
+  tmp = GPIOx->LCKR;
+
+  /* Read again in order to confirm lock is active */
+ if((GPIOx->LCKR & GPIO_LCKR_LCKK) != RESET)
+  {
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  This function handles EXTI interrupt request.
+  * @param  GPIO_Pin Specifies the pins connected EXTI line
+  * @retval None
+  */
+void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin)
+{
+  /* EXTI line interrupt detected */
+  if(__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != RESET)
+  {
+    __HAL_GPIO_EXTI_CLEAR_IT(GPIO_Pin);
+    HAL_GPIO_EXTI_Callback(GPIO_Pin);
+  }
+}
+
+/**
+  * @brief  EXTI line detection callbacks.
+  * @param  GPIO_Pin Specifies the pins connected EXTI line
+  * @retval None
+  */
+__weak void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(GPIO_Pin);
+  /* NOTE: This function Should not be modified, when the callback is needed,
+           the HAL_GPIO_EXTI_Callback could be implemented in the user file
+   */
+}
+
+/**
+  * @}
+  */
+
+
+/**
+  * @}
+  */
+
+#endif /* HAL_GPIO_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
diff --git a/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_hcd.c b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_hcd.c
new file mode 100644
index 0000000..5f9503e
--- /dev/null
+++ b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_hcd.c
@@ -0,0 +1,1728 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hal_hcd.c
+  * @author  MCD Application Team
+  * @brief   HCD HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the USB Peripheral Controller:
+  *           + Initialization and de-initialization functions
+  *           + IO operation functions
+  *           + Peripheral Control functions
+  *           + Peripheral State functions
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2016 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  @verbatim
+  ==============================================================================
+                    ##### How to use this driver #####
+  ==============================================================================
+  [..]
+    (#)Declare a HCD_HandleTypeDef handle structure, for example:
+       HCD_HandleTypeDef  hhcd;
+
+    (#)Fill parameters of Init structure in HCD handle
+
+    (#)Call HAL_HCD_Init() API to initialize the HCD peripheral (Core, Host core, ...)
+
+    (#)Initialize the HCD low level resources through the HAL_HCD_MspInit() API:
+        (##) Enable the HCD/USB Low Level interface clock using the following macros
+             (+++) __HAL_RCC_USB_OTG_FS_CLK_ENABLE();
+             (+++) __HAL_RCC_USB_OTG_HS_CLK_ENABLE(); (For High Speed Mode)
+             (+++) __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE(); (For High Speed Mode)
+
+        (##) Initialize the related GPIO clocks
+        (##) Configure HCD pin-out
+        (##) Configure HCD NVIC interrupt
+
+    (#)Associate the Upper USB Host stack to the HAL HCD Driver:
+        (##) hhcd.pData = phost;
+
+    (#)Enable HCD transmission and reception:
+        (##) HAL_HCD_Start();
+
+  @endverbatim
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+  * @{
+  */
+
+#ifdef HAL_HCD_MODULE_ENABLED
+#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
+
+/** @defgroup HCD HCD
+  * @brief HCD HAL module driver
+  * @{
+  */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @defgroup HCD_Private_Functions HCD Private Functions
+  * @{
+  */
+static void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum);
+static void HCD_HC_OUT_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum);
+static void HCD_RXQLVL_IRQHandler(HCD_HandleTypeDef *hhcd);
+static void HCD_Port_IRQHandler(HCD_HandleTypeDef *hhcd);
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup HCD_Exported_Functions HCD Exported Functions
+  * @{
+  */
+
+/** @defgroup HCD_Exported_Functions_Group1 Initialization and de-initialization functions
+  *  @brief    Initialization and Configuration functions
+  *
+@verbatim
+ ===============================================================================
+          ##### Initialization and de-initialization functions #####
+ ===============================================================================
+    [..]  This section provides functions allowing to:
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initialize the host driver.
+  * @param  hhcd HCD handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_HCD_Init(HCD_HandleTypeDef *hhcd)
+{
+  USB_OTG_GlobalTypeDef *USBx;
+
+  /* Check the HCD handle allocation */
+  if (hhcd == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_HCD_ALL_INSTANCE(hhcd->Instance));
+
+  USBx = hhcd->Instance;
+
+  if (hhcd->State == HAL_HCD_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    hhcd->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
+    hhcd->SOFCallback = HAL_HCD_SOF_Callback;
+    hhcd->ConnectCallback = HAL_HCD_Connect_Callback;
+    hhcd->DisconnectCallback = HAL_HCD_Disconnect_Callback;
+    hhcd->PortEnabledCallback = HAL_HCD_PortEnabled_Callback;
+    hhcd->PortDisabledCallback = HAL_HCD_PortDisabled_Callback;
+    hhcd->HC_NotifyURBChangeCallback = HAL_HCD_HC_NotifyURBChange_Callback;
+
+    if (hhcd->MspInitCallback == NULL)
+    {
+      hhcd->MspInitCallback = HAL_HCD_MspInit;
+    }
+
+    /* Init the low level hardware */
+    hhcd->MspInitCallback(hhcd);
+#else
+    /* Init the low level hardware : GPIO, CLOCK, NVIC... */
+    HAL_HCD_MspInit(hhcd);
+#endif /* (USE_HAL_HCD_REGISTER_CALLBACKS) */
+  }
+
+  hhcd->State = HAL_HCD_STATE_BUSY;
+
+  /* Disable DMA mode for FS instance */
+  if ((USBx->CID & (0x1U << 8)) == 0U)
+  {
+    hhcd->Init.dma_enable = 0U;
+  }
+
+  /* Disable the Interrupts */
+  __HAL_HCD_DISABLE(hhcd);
+
+  /* Init the Core (common init.) */
+  (void)USB_CoreInit(hhcd->Instance, hhcd->Init);
+
+  /* Force Host Mode*/
+  (void)USB_SetCurrentMode(hhcd->Instance, USB_HOST_MODE);
+
+  /* Init Host */
+  (void)USB_HostInit(hhcd->Instance, hhcd->Init);
+
+  hhcd->State = HAL_HCD_STATE_READY;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initialize a host channel.
+  * @param  hhcd HCD handle
+  * @param  ch_num Channel number.
+  *         This parameter can be a value from 1 to 15
+  * @param  epnum Endpoint number.
+  *          This parameter can be a value from 1 to 15
+  * @param  dev_address Current device address
+  *          This parameter can be a value from 0 to 255
+  * @param  speed Current device speed.
+  *          This parameter can be one of these values:
+  *            HCD_DEVICE_SPEED_HIGH: High speed mode,
+  *            HCD_DEVICE_SPEED_FULL: Full speed mode,
+  *            HCD_DEVICE_SPEED_LOW: Low speed mode
+  * @param  ep_type Endpoint Type.
+  *          This parameter can be one of these values:
+  *            EP_TYPE_CTRL: Control type,
+  *            EP_TYPE_ISOC: Isochronous type,
+  *            EP_TYPE_BULK: Bulk type,
+  *            EP_TYPE_INTR: Interrupt type
+  * @param  mps Max Packet Size.
+  *          This parameter can be a value from 0 to32K
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_HCD_HC_Init(HCD_HandleTypeDef *hhcd,
+                                  uint8_t ch_num,
+                                  uint8_t epnum,
+                                  uint8_t dev_address,
+                                  uint8_t speed,
+                                  uint8_t ep_type,
+                                  uint16_t mps)
+{
+  HAL_StatusTypeDef status;
+
+  __HAL_LOCK(hhcd);
+  hhcd->hc[ch_num].do_ping = 0U;
+  hhcd->hc[ch_num].dev_addr = dev_address;
+  hhcd->hc[ch_num].max_packet = mps;
+  hhcd->hc[ch_num].ch_num = ch_num;
+  hhcd->hc[ch_num].ep_type = ep_type;
+  hhcd->hc[ch_num].ep_num = epnum & 0x7FU;
+
+  if ((epnum & 0x80U) == 0x80U)
+  {
+    hhcd->hc[ch_num].ep_is_in = 1U;
+  }
+  else
+  {
+    hhcd->hc[ch_num].ep_is_in = 0U;
+  }
+
+  hhcd->hc[ch_num].speed = speed;
+
+  status =  USB_HC_Init(hhcd->Instance,
+                        ch_num,
+                        epnum,
+                        dev_address,
+                        speed,
+                        ep_type,
+                        mps);
+  __HAL_UNLOCK(hhcd);
+
+  return status;
+}
+
+/**
+  * @brief  Halt a host channel.
+  * @param  hhcd HCD handle
+  * @param  ch_num Channel number.
+  *         This parameter can be a value from 1 to 15
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_HCD_HC_Halt(HCD_HandleTypeDef *hhcd, uint8_t ch_num)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  __HAL_LOCK(hhcd);
+  (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
+  __HAL_UNLOCK(hhcd);
+
+  return status;
+}
+
+/**
+  * @brief  DeInitialize the host driver.
+  * @param  hhcd HCD handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_HCD_DeInit(HCD_HandleTypeDef *hhcd)
+{
+  /* Check the HCD handle allocation */
+  if (hhcd == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  hhcd->State = HAL_HCD_STATE_BUSY;
+
+#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
+  if (hhcd->MspDeInitCallback == NULL)
+  {
+    hhcd->MspDeInitCallback = HAL_HCD_MspDeInit; /* Legacy weak MspDeInit  */
+  }
+
+  /* DeInit the low level hardware */
+  hhcd->MspDeInitCallback(hhcd);
+#else
+  /* DeInit the low level hardware: CLOCK, NVIC.*/
+  HAL_HCD_MspDeInit(hhcd);
+#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
+
+  __HAL_HCD_DISABLE(hhcd);
+
+  hhcd->State = HAL_HCD_STATE_RESET;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initialize the HCD MSP.
+  * @param  hhcd HCD handle
+  * @retval None
+  */
+__weak void  HAL_HCD_MspInit(HCD_HandleTypeDef *hhcd)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hhcd);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_HCD_MspInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  DeInitialize the HCD MSP.
+  * @param  hhcd HCD handle
+  * @retval None
+  */
+__weak void  HAL_HCD_MspDeInit(HCD_HandleTypeDef *hhcd)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hhcd);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_HCD_MspDeInit could be implemented in the user file
+   */
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup HCD_Exported_Functions_Group2 Input and Output operation functions
+  *  @brief   HCD IO operation functions
+  *
+@verbatim
+ ===============================================================================
+                      ##### IO operation functions #####
+ ===============================================================================
+ [..] This subsection provides a set of functions allowing to manage the USB Host Data
+    Transfer
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Submit a new URB for processing.
+  * @param  hhcd HCD handle
+  * @param  ch_num Channel number.
+  *         This parameter can be a value from 1 to 15
+  * @param  direction Channel number.
+  *          This parameter can be one of these values:
+  *           0 : Output / 1 : Input
+  * @param  ep_type Endpoint Type.
+  *          This parameter can be one of these values:
+  *            EP_TYPE_CTRL: Control type/
+  *            EP_TYPE_ISOC: Isochronous type/
+  *            EP_TYPE_BULK: Bulk type/
+  *            EP_TYPE_INTR: Interrupt type/
+  * @param  token Endpoint Type.
+  *          This parameter can be one of these values:
+  *            0: HC_PID_SETUP / 1: HC_PID_DATA1
+  * @param  pbuff pointer to URB data
+  * @param  length Length of URB data
+  * @param  do_ping activate do ping protocol (for high speed only).
+  *          This parameter can be one of these values:
+  *           0 : do ping inactive / 1 : do ping active
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_HCD_HC_SubmitRequest(HCD_HandleTypeDef *hhcd,
+                                           uint8_t ch_num,
+                                           uint8_t direction,
+                                           uint8_t ep_type,
+                                           uint8_t token,
+                                           uint8_t *pbuff,
+                                           uint16_t length,
+                                           uint8_t do_ping)
+{
+  hhcd->hc[ch_num].ep_is_in = direction;
+  hhcd->hc[ch_num].ep_type  = ep_type;
+
+  if (token == 0U)
+  {
+    hhcd->hc[ch_num].data_pid = HC_PID_SETUP;
+    hhcd->hc[ch_num].do_ping = do_ping;
+  }
+  else
+  {
+    hhcd->hc[ch_num].data_pid = HC_PID_DATA1;
+  }
+
+  /* Manage Data Toggle */
+  switch (ep_type)
+  {
+    case EP_TYPE_CTRL:
+      if ((token == 1U) && (direction == 0U)) /*send data */
+      {
+        if (length == 0U)
+        {
+          /* For Status OUT stage, Length==0, Status Out PID = 1 */
+          hhcd->hc[ch_num].toggle_out = 1U;
+        }
+
+        /* Set the Data Toggle bit as per the Flag */
+        if (hhcd->hc[ch_num].toggle_out == 0U)
+        {
+          /* Put the PID 0 */
+          hhcd->hc[ch_num].data_pid = HC_PID_DATA0;
+        }
+        else
+        {
+          /* Put the PID 1 */
+          hhcd->hc[ch_num].data_pid = HC_PID_DATA1;
+        }
+      }
+      break;
+
+    case EP_TYPE_BULK:
+      if (direction == 0U)
+      {
+        /* Set the Data Toggle bit as per the Flag */
+        if (hhcd->hc[ch_num].toggle_out == 0U)
+        {
+          /* Put the PID 0 */
+          hhcd->hc[ch_num].data_pid = HC_PID_DATA0;
+        }
+        else
+        {
+          /* Put the PID 1 */
+          hhcd->hc[ch_num].data_pid = HC_PID_DATA1;
+        }
+      }
+      else
+      {
+        if (hhcd->hc[ch_num].toggle_in == 0U)
+        {
+          hhcd->hc[ch_num].data_pid = HC_PID_DATA0;
+        }
+        else
+        {
+          hhcd->hc[ch_num].data_pid = HC_PID_DATA1;
+        }
+      }
+
+      break;
+    case EP_TYPE_INTR:
+      if (direction == 0U)
+      {
+        /* Set the Data Toggle bit as per the Flag */
+        if (hhcd->hc[ch_num].toggle_out == 0U)
+        {
+          /* Put the PID 0 */
+          hhcd->hc[ch_num].data_pid = HC_PID_DATA0;
+        }
+        else
+        {
+          /* Put the PID 1 */
+          hhcd->hc[ch_num].data_pid = HC_PID_DATA1;
+        }
+      }
+      else
+      {
+        if (hhcd->hc[ch_num].toggle_in == 0U)
+        {
+          hhcd->hc[ch_num].data_pid = HC_PID_DATA0;
+        }
+        else
+        {
+          hhcd->hc[ch_num].data_pid = HC_PID_DATA1;
+        }
+      }
+      break;
+
+    case EP_TYPE_ISOC:
+      hhcd->hc[ch_num].data_pid = HC_PID_DATA0;
+      break;
+
+    default:
+      break;
+  }
+
+  hhcd->hc[ch_num].xfer_buff = pbuff;
+  hhcd->hc[ch_num].xfer_len  = length;
+  hhcd->hc[ch_num].urb_state = URB_IDLE;
+  hhcd->hc[ch_num].xfer_count = 0U;
+  hhcd->hc[ch_num].ch_num = ch_num;
+  hhcd->hc[ch_num].state = HC_IDLE;
+
+  return USB_HC_StartXfer(hhcd->Instance, &hhcd->hc[ch_num], (uint8_t)hhcd->Init.dma_enable);
+}
+
+/**
+  * @brief  Handle HCD interrupt request.
+  * @param  hhcd HCD handle
+  * @retval None
+  */
+void HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd)
+{
+  USB_OTG_GlobalTypeDef *USBx = hhcd->Instance;
+  uint32_t USBx_BASE = (uint32_t)USBx;
+  uint32_t i;
+  uint32_t interrupt;
+
+  /* Ensure that we are in device mode */
+  if (USB_GetMode(hhcd->Instance) == USB_OTG_MODE_HOST)
+  {
+    /* Avoid spurious interrupt */
+    if (__HAL_HCD_IS_INVALID_INTERRUPT(hhcd))
+    {
+      return;
+    }
+
+    if (__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT))
+    {
+      /* Incorrect mode, acknowledge the interrupt */
+      __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT);
+    }
+
+    if (__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_IISOIXFR))
+    {
+      /* Incorrect mode, acknowledge the interrupt */
+      __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_IISOIXFR);
+    }
+
+    if (__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_PTXFE))
+    {
+      /* Incorrect mode, acknowledge the interrupt */
+      __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_PTXFE);
+    }
+
+    if (__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_MMIS))
+    {
+      /* Incorrect mode, acknowledge the interrupt */
+      __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_MMIS);
+    }
+
+    /* Handle Host Disconnect Interrupts */
+    if (__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_DISCINT))
+    {
+      __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_DISCINT);
+
+      if ((USBx_HPRT0 & USB_OTG_HPRT_PCSTS) == 0U)
+      {
+        /* Flush USB Fifo */
+        (void)USB_FlushTxFifo(USBx, 0x10U);
+        (void)USB_FlushRxFifo(USBx);
+
+        /* Restore FS Clock */
+        (void)USB_InitFSLSPClkSel(hhcd->Instance, HCFG_48_MHZ);
+
+        /* Handle Host Port Disconnect Interrupt */
+#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
+        hhcd->DisconnectCallback(hhcd);
+#else
+        HAL_HCD_Disconnect_Callback(hhcd);
+#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
+      }
+    }
+
+    /* Handle Host Port Interrupts */
+    if (__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_HPRTINT))
+    {
+      HCD_Port_IRQHandler(hhcd);
+    }
+
+    /* Handle Host SOF Interrupt */
+    if (__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_SOF))
+    {
+#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
+      hhcd->SOFCallback(hhcd);
+#else
+      HAL_HCD_SOF_Callback(hhcd);
+#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
+
+      __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_SOF);
+    }
+
+    /* Handle Rx Queue Level Interrupts */
+    if ((__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_RXFLVL)) != 0U)
+    {
+      USB_MASK_INTERRUPT(hhcd->Instance, USB_OTG_GINTSTS_RXFLVL);
+
+      HCD_RXQLVL_IRQHandler(hhcd);
+
+      USB_UNMASK_INTERRUPT(hhcd->Instance, USB_OTG_GINTSTS_RXFLVL);
+    }
+
+    /* Handle Host channel Interrupt */
+    if (__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_HCINT))
+    {
+      interrupt = USB_HC_ReadInterrupt(hhcd->Instance);
+      for (i = 0U; i < hhcd->Init.Host_channels; i++)
+      {
+        if ((interrupt & (1UL << (i & 0xFU))) != 0U)
+        {
+          if ((USBx_HC(i)->HCCHAR & USB_OTG_HCCHAR_EPDIR) == USB_OTG_HCCHAR_EPDIR)
+          {
+            HCD_HC_IN_IRQHandler(hhcd, (uint8_t)i);
+          }
+          else
+          {
+            HCD_HC_OUT_IRQHandler(hhcd, (uint8_t)i);
+          }
+        }
+      }
+      __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_HCINT);
+    }
+  }
+}
+
+
+/**
+  * @brief  Handles HCD Wakeup interrupt request.
+  * @param  hhcd HCD handle
+  * @retval HAL status
+  */
+void HAL_HCD_WKUP_IRQHandler(HCD_HandleTypeDef *hhcd)
+{
+  UNUSED(hhcd);
+}
+
+
+/**
+  * @brief  SOF callback.
+  * @param  hhcd HCD handle
+  * @retval None
+  */
+__weak void HAL_HCD_SOF_Callback(HCD_HandleTypeDef *hhcd)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hhcd);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_HCD_SOF_Callback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief Connection Event callback.
+  * @param  hhcd HCD handle
+  * @retval None
+  */
+__weak void HAL_HCD_Connect_Callback(HCD_HandleTypeDef *hhcd)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hhcd);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_HCD_Connect_Callback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Disconnection Event callback.
+  * @param  hhcd HCD handle
+  * @retval None
+  */
+__weak void HAL_HCD_Disconnect_Callback(HCD_HandleTypeDef *hhcd)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hhcd);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_HCD_Disconnect_Callback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Port Enabled  Event callback.
+  * @param  hhcd HCD handle
+  * @retval None
+  */
+__weak void HAL_HCD_PortEnabled_Callback(HCD_HandleTypeDef *hhcd)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hhcd);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_HCD_Disconnect_Callback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Port Disabled  Event callback.
+  * @param  hhcd HCD handle
+  * @retval None
+  */
+__weak void HAL_HCD_PortDisabled_Callback(HCD_HandleTypeDef *hhcd)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hhcd);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_HCD_Disconnect_Callback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Notify URB state change callback.
+  * @param  hhcd HCD handle
+  * @param  chnum Channel number.
+  *         This parameter can be a value from 1 to 15
+  * @param  urb_state:
+  *          This parameter can be one of these values:
+  *            URB_IDLE/
+  *            URB_DONE/
+  *            URB_NOTREADY/
+  *            URB_NYET/
+  *            URB_ERROR/
+  *            URB_STALL/
+  * @retval None
+  */
+__weak void HAL_HCD_HC_NotifyURBChange_Callback(HCD_HandleTypeDef *hhcd, uint8_t chnum, HCD_URBStateTypeDef urb_state)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hhcd);
+  UNUSED(chnum);
+  UNUSED(urb_state);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_HCD_HC_NotifyURBChange_Callback could be implemented in the user file
+   */
+}
+
+#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
+/**
+  * @brief  Register a User USB HCD Callback
+  *         To be used instead of the weak predefined callback
+  * @param  hhcd USB HCD handle
+  * @param  CallbackID ID of the callback to be registered
+  *         This parameter can be one of the following values:
+  *          @arg @ref HAL_HCD_SOF_CB_ID USB HCD SOF callback ID
+  *          @arg @ref HAL_HCD_CONNECT_CB_ID USB HCD Connect callback ID
+  *          @arg @ref HAL_HCD_DISCONNECT_CB_ID OTG HCD Disconnect callback ID
+  *          @arg @ref HAL_HCD_PORT_ENABLED_CB_ID USB HCD Port Enable callback ID
+  *          @arg @ref HAL_HCD_PORT_DISABLED_CB_ID USB HCD Port Disable callback ID
+  *          @arg @ref HAL_HCD_MSPINIT_CB_ID MspDeInit callback ID
+  *          @arg @ref HAL_HCD_MSPDEINIT_CB_ID MspDeInit callback ID
+  * @param  pCallback pointer to the Callback function
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_HCD_RegisterCallback(HCD_HandleTypeDef *hhcd,
+                                           HAL_HCD_CallbackIDTypeDef CallbackID,
+                                           pHCD_CallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    /* Update the error code */
+    hhcd->ErrorCode |= HAL_HCD_ERROR_INVALID_CALLBACK;
+    return HAL_ERROR;
+  }
+  /* Process locked */
+  __HAL_LOCK(hhcd);
+
+  if (hhcd->State == HAL_HCD_STATE_READY)
+  {
+    switch (CallbackID)
+    {
+      case HAL_HCD_SOF_CB_ID :
+        hhcd->SOFCallback = pCallback;
+        break;
+
+      case HAL_HCD_CONNECT_CB_ID :
+        hhcd->ConnectCallback = pCallback;
+        break;
+
+      case HAL_HCD_DISCONNECT_CB_ID :
+        hhcd->DisconnectCallback = pCallback;
+        break;
+
+      case HAL_HCD_PORT_ENABLED_CB_ID :
+        hhcd->PortEnabledCallback = pCallback;
+        break;
+
+      case HAL_HCD_PORT_DISABLED_CB_ID :
+        hhcd->PortDisabledCallback = pCallback;
+        break;
+
+      case HAL_HCD_MSPINIT_CB_ID :
+        hhcd->MspInitCallback = pCallback;
+        break;
+
+      case HAL_HCD_MSPDEINIT_CB_ID :
+        hhcd->MspDeInitCallback = pCallback;
+        break;
+
+      default :
+        /* Update the error code */
+        hhcd->ErrorCode |= HAL_HCD_ERROR_INVALID_CALLBACK;
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else if (hhcd->State == HAL_HCD_STATE_RESET)
+  {
+    switch (CallbackID)
+    {
+      case HAL_HCD_MSPINIT_CB_ID :
+        hhcd->MspInitCallback = pCallback;
+        break;
+
+      case HAL_HCD_MSPDEINIT_CB_ID :
+        hhcd->MspDeInitCallback = pCallback;
+        break;
+
+      default :
+        /* Update the error code */
+        hhcd->ErrorCode |= HAL_HCD_ERROR_INVALID_CALLBACK;
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    /* Update the error code */
+    hhcd->ErrorCode |= HAL_HCD_ERROR_INVALID_CALLBACK;
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(hhcd);
+  return status;
+}
+
+/**
+  * @brief  Unregister an USB HCD Callback
+  *         USB HCD callback is redirected to the weak predefined callback
+  * @param  hhcd USB HCD handle
+  * @param  CallbackID ID of the callback to be unregistered
+  *         This parameter can be one of the following values:
+  *          @arg @ref HAL_HCD_SOF_CB_ID USB HCD SOF callback ID
+  *          @arg @ref HAL_HCD_CONNECT_CB_ID USB HCD Connect callback ID
+  *          @arg @ref HAL_HCD_DISCONNECT_CB_ID OTG HCD Disconnect callback ID
+  *          @arg @ref HAL_HCD_PORT_ENABLED_CB_ID USB HCD Port Enabled callback ID
+  *          @arg @ref HAL_HCD_PORT_DISABLED_CB_ID USB HCD Port Disabled callback ID
+  *          @arg @ref HAL_HCD_MSPINIT_CB_ID MspDeInit callback ID
+  *          @arg @ref HAL_HCD_MSPDEINIT_CB_ID MspDeInit callback ID
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_HCD_UnRegisterCallback(HCD_HandleTypeDef *hhcd, HAL_HCD_CallbackIDTypeDef CallbackID)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Process locked */
+  __HAL_LOCK(hhcd);
+
+  /* Setup Legacy weak Callbacks  */
+  if (hhcd->State == HAL_HCD_STATE_READY)
+  {
+    switch (CallbackID)
+    {
+      case HAL_HCD_SOF_CB_ID :
+        hhcd->SOFCallback = HAL_HCD_SOF_Callback;
+        break;
+
+      case HAL_HCD_CONNECT_CB_ID :
+        hhcd->ConnectCallback = HAL_HCD_Connect_Callback;
+        break;
+
+      case HAL_HCD_DISCONNECT_CB_ID :
+        hhcd->DisconnectCallback = HAL_HCD_Disconnect_Callback;
+        break;
+
+      case HAL_HCD_PORT_ENABLED_CB_ID :
+        hhcd->PortEnabledCallback = HAL_HCD_PortEnabled_Callback;
+        break;
+
+      case HAL_HCD_PORT_DISABLED_CB_ID :
+        hhcd->PortDisabledCallback = HAL_HCD_PortDisabled_Callback;
+        break;
+
+      case HAL_HCD_MSPINIT_CB_ID :
+        hhcd->MspInitCallback = HAL_HCD_MspInit;
+        break;
+
+      case HAL_HCD_MSPDEINIT_CB_ID :
+        hhcd->MspDeInitCallback = HAL_HCD_MspDeInit;
+        break;
+
+      default :
+        /* Update the error code */
+        hhcd->ErrorCode |= HAL_HCD_ERROR_INVALID_CALLBACK;
+
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else if (hhcd->State == HAL_HCD_STATE_RESET)
+  {
+    switch (CallbackID)
+    {
+      case HAL_HCD_MSPINIT_CB_ID :
+        hhcd->MspInitCallback = HAL_HCD_MspInit;
+        break;
+
+      case HAL_HCD_MSPDEINIT_CB_ID :
+        hhcd->MspDeInitCallback = HAL_HCD_MspDeInit;
+        break;
+
+      default :
+        /* Update the error code */
+        hhcd->ErrorCode |= HAL_HCD_ERROR_INVALID_CALLBACK;
+
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    /* Update the error code */
+    hhcd->ErrorCode |= HAL_HCD_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(hhcd);
+  return status;
+}
+
+/**
+  * @brief  Register USB HCD Host Channel Notify URB Change Callback
+  *         To be used instead of the weak HAL_HCD_HC_NotifyURBChange_Callback() predefined callback
+  * @param  hhcd HCD handle
+  * @param  pCallback pointer to the USB HCD Host Channel Notify URB Change Callback function
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_HCD_RegisterHC_NotifyURBChangeCallback(HCD_HandleTypeDef *hhcd,
+                                                             pHCD_HC_NotifyURBChangeCallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    /* Update the error code */
+    hhcd->ErrorCode |= HAL_HCD_ERROR_INVALID_CALLBACK;
+
+    return HAL_ERROR;
+  }
+
+  /* Process locked */
+  __HAL_LOCK(hhcd);
+
+  if (hhcd->State == HAL_HCD_STATE_READY)
+  {
+    hhcd->HC_NotifyURBChangeCallback = pCallback;
+  }
+  else
+  {
+    /* Update the error code */
+    hhcd->ErrorCode |= HAL_HCD_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(hhcd);
+
+  return status;
+}
+
+/**
+  * @brief  Unregister the USB HCD Host Channel Notify URB Change Callback
+  *         USB HCD Host Channel Notify URB Change Callback is redirected
+  *         to the weak HAL_HCD_HC_NotifyURBChange_Callback() predefined callback
+  * @param  hhcd HCD handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_HCD_UnRegisterHC_NotifyURBChangeCallback(HCD_HandleTypeDef *hhcd)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Process locked */
+  __HAL_LOCK(hhcd);
+
+  if (hhcd->State == HAL_HCD_STATE_READY)
+  {
+    hhcd->HC_NotifyURBChangeCallback = HAL_HCD_HC_NotifyURBChange_Callback; /* Legacy weak DataOutStageCallback  */
+  }
+  else
+  {
+    /* Update the error code */
+    hhcd->ErrorCode |= HAL_HCD_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(hhcd);
+
+  return status;
+}
+#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+
+/** @defgroup HCD_Exported_Functions_Group3 Peripheral Control functions
+  *  @brief   Management functions
+  *
+@verbatim
+ ===============================================================================
+                      ##### Peripheral Control functions #####
+ ===============================================================================
+    [..]
+    This subsection provides a set of functions allowing to control the HCD data
+    transfers.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Start the host driver.
+  * @param  hhcd HCD handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_HCD_Start(HCD_HandleTypeDef *hhcd)
+{
+  __HAL_LOCK(hhcd);
+  /* Enable port power */
+  (void)USB_DriveVbus(hhcd->Instance, 1U);
+
+  /* Enable global interrupt */
+  __HAL_HCD_ENABLE(hhcd);
+  __HAL_UNLOCK(hhcd);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stop the host driver.
+  * @param  hhcd HCD handle
+  * @retval HAL status
+  */
+
+HAL_StatusTypeDef HAL_HCD_Stop(HCD_HandleTypeDef *hhcd)
+{
+  __HAL_LOCK(hhcd);
+  (void)USB_StopHost(hhcd->Instance);
+  __HAL_UNLOCK(hhcd);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Reset the host port.
+  * @param  hhcd HCD handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_HCD_ResetPort(HCD_HandleTypeDef *hhcd)
+{
+  return (USB_ResetPort(hhcd->Instance));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup HCD_Exported_Functions_Group4 Peripheral State functions
+  *  @brief   Peripheral State functions
+  *
+@verbatim
+ ===============================================================================
+                      ##### Peripheral State functions #####
+ ===============================================================================
+    [..]
+    This subsection permits to get in run-time the status of the peripheral
+    and the data flow.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Return the HCD handle state.
+  * @param  hhcd HCD handle
+  * @retval HAL state
+  */
+HCD_StateTypeDef HAL_HCD_GetState(HCD_HandleTypeDef *hhcd)
+{
+  return hhcd->State;
+}
+
+/**
+  * @brief  Return  URB state for a channel.
+  * @param  hhcd HCD handle
+  * @param  chnum Channel number.
+  *         This parameter can be a value from 1 to 15
+  * @retval URB state.
+  *          This parameter can be one of these values:
+  *            URB_IDLE/
+  *            URB_DONE/
+  *            URB_NOTREADY/
+  *            URB_NYET/
+  *            URB_ERROR/
+  *            URB_STALL
+  */
+HCD_URBStateTypeDef HAL_HCD_HC_GetURBState(HCD_HandleTypeDef *hhcd, uint8_t chnum)
+{
+  return hhcd->hc[chnum].urb_state;
+}
+
+
+/**
+  * @brief  Return the last host transfer size.
+  * @param  hhcd HCD handle
+  * @param  chnum Channel number.
+  *         This parameter can be a value from 1 to 15
+  * @retval last transfer size in byte
+  */
+uint32_t HAL_HCD_HC_GetXferCount(HCD_HandleTypeDef *hhcd, uint8_t chnum)
+{
+  return hhcd->hc[chnum].xfer_count;
+}
+
+/**
+  * @brief  Return the Host Channel state.
+  * @param  hhcd HCD handle
+  * @param  chnum Channel number.
+  *         This parameter can be a value from 1 to 15
+  * @retval Host channel state
+  *          This parameter can be one of these values:
+  *            HC_IDLE/
+  *            HC_XFRC/
+  *            HC_HALTED/
+  *            HC_NYET/
+  *            HC_NAK/
+  *            HC_STALL/
+  *            HC_XACTERR/
+  *            HC_BBLERR/
+  *            HC_DATATGLERR
+  */
+HCD_HCStateTypeDef  HAL_HCD_HC_GetState(HCD_HandleTypeDef *hhcd, uint8_t chnum)
+{
+  return hhcd->hc[chnum].state;
+}
+
+/**
+  * @brief  Return the current Host frame number.
+  * @param  hhcd HCD handle
+  * @retval Current Host frame number
+  */
+uint32_t HAL_HCD_GetCurrentFrame(HCD_HandleTypeDef *hhcd)
+{
+  return (USB_GetCurrentFrame(hhcd->Instance));
+}
+
+/**
+  * @brief  Return the Host enumeration speed.
+  * @param  hhcd HCD handle
+  * @retval Enumeration speed
+  */
+uint32_t HAL_HCD_GetCurrentSpeed(HCD_HandleTypeDef *hhcd)
+{
+  return (USB_GetHostSpeed(hhcd->Instance));
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup HCD_Private_Functions
+  * @{
+  */
+/**
+  * @brief  Handle Host Channel IN interrupt requests.
+  * @param  hhcd HCD handle
+  * @param  chnum Channel number.
+  *         This parameter can be a value from 1 to 15
+  * @retval none
+  */
+static void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum)
+{
+  USB_OTG_GlobalTypeDef *USBx = hhcd->Instance;
+  uint32_t USBx_BASE = (uint32_t)USBx;
+  uint32_t ch_num = (uint32_t)chnum;
+
+  uint32_t tmpreg;
+
+  if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_AHBERR) == USB_OTG_HCINT_AHBERR)
+  {
+    __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_AHBERR);
+    hhcd->hc[ch_num].state = HC_XACTERR;
+    (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
+  }
+  else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_BBERR) == USB_OTG_HCINT_BBERR)
+  {
+    __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_BBERR);
+    hhcd->hc[ch_num].state = HC_BBLERR;
+    (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
+  }
+  else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_ACK) == USB_OTG_HCINT_ACK)
+  {
+    __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_ACK);
+  }
+  else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_STALL) == USB_OTG_HCINT_STALL)
+  {
+    __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_STALL);
+    hhcd->hc[ch_num].state = HC_STALL;
+    (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
+  }
+  else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_DTERR) == USB_OTG_HCINT_DTERR)
+  {
+    __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_DTERR);
+    hhcd->hc[ch_num].state = HC_DATATGLERR;
+    (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
+  }
+  else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_TXERR) == USB_OTG_HCINT_TXERR)
+  {
+    __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_TXERR);
+    hhcd->hc[ch_num].state = HC_XACTERR;
+    (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
+  }
+  else
+  {
+    /* ... */
+  }
+
+  if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_FRMOR) == USB_OTG_HCINT_FRMOR)
+  {
+    (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
+    __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_FRMOR);
+  }
+  else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_XFRC) == USB_OTG_HCINT_XFRC)
+  {
+    if (hhcd->Init.dma_enable != 0U)
+    {
+      hhcd->hc[ch_num].xfer_count = hhcd->hc[ch_num].XferSize - \
+                                    (USBx_HC(ch_num)->HCTSIZ & USB_OTG_HCTSIZ_XFRSIZ);
+    }
+
+    hhcd->hc[ch_num].state = HC_XFRC;
+    hhcd->hc[ch_num].ErrCnt = 0U;
+    __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_XFRC);
+
+    if ((hhcd->hc[ch_num].ep_type == EP_TYPE_CTRL) ||
+        (hhcd->hc[ch_num].ep_type == EP_TYPE_BULK))
+    {
+      (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
+      __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_NAK);
+    }
+    else if ((hhcd->hc[ch_num].ep_type == EP_TYPE_INTR) ||
+             (hhcd->hc[ch_num].ep_type == EP_TYPE_ISOC))
+    {
+      USBx_HC(ch_num)->HCCHAR |= USB_OTG_HCCHAR_ODDFRM;
+      hhcd->hc[ch_num].urb_state = URB_DONE;
+
+#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
+      hhcd->HC_NotifyURBChangeCallback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num].urb_state);
+#else
+      HAL_HCD_HC_NotifyURBChange_Callback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num].urb_state);
+#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
+    }
+    else
+    {
+      /* ... */
+    }
+
+    if (hhcd->Init.dma_enable == 1U)
+    {
+      if (((hhcd->hc[ch_num].XferSize / hhcd->hc[ch_num].max_packet) & 1U) != 0U)
+      {
+        hhcd->hc[ch_num].toggle_in ^= 1U;
+      }
+    }
+    else
+    {
+      hhcd->hc[ch_num].toggle_in ^= 1U;
+    }
+  }
+  else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_CHH) == USB_OTG_HCINT_CHH)
+  {
+    if (hhcd->hc[ch_num].state == HC_XFRC)
+    {
+      hhcd->hc[ch_num].urb_state = URB_DONE;
+    }
+    else if (hhcd->hc[ch_num].state == HC_STALL)
+    {
+      hhcd->hc[ch_num].urb_state = URB_STALL;
+    }
+    else if ((hhcd->hc[ch_num].state == HC_XACTERR) ||
+             (hhcd->hc[ch_num].state == HC_DATATGLERR))
+    {
+      hhcd->hc[ch_num].ErrCnt++;
+      if (hhcd->hc[ch_num].ErrCnt > 2U)
+      {
+        hhcd->hc[ch_num].ErrCnt = 0U;
+        hhcd->hc[ch_num].urb_state = URB_ERROR;
+      }
+      else
+      {
+        hhcd->hc[ch_num].urb_state = URB_NOTREADY;
+
+        /* re-activate the channel */
+        tmpreg = USBx_HC(ch_num)->HCCHAR;
+        tmpreg &= ~USB_OTG_HCCHAR_CHDIS;
+        tmpreg |= USB_OTG_HCCHAR_CHENA;
+        USBx_HC(ch_num)->HCCHAR = tmpreg;
+      }
+    }
+    else if (hhcd->hc[ch_num].state == HC_NAK)
+    {
+      hhcd->hc[ch_num].urb_state  = URB_NOTREADY;
+
+      /* re-activate the channel */
+      tmpreg = USBx_HC(ch_num)->HCCHAR;
+      tmpreg &= ~USB_OTG_HCCHAR_CHDIS;
+      tmpreg |= USB_OTG_HCCHAR_CHENA;
+      USBx_HC(ch_num)->HCCHAR = tmpreg;
+    }
+    else if (hhcd->hc[ch_num].state == HC_BBLERR)
+    {
+      hhcd->hc[ch_num].ErrCnt++;
+      hhcd->hc[ch_num].urb_state = URB_ERROR;
+    }
+    else
+    {
+      /* ... */
+    }
+    __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_CHH);
+
+#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
+    hhcd->HC_NotifyURBChangeCallback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num].urb_state);
+#else
+    HAL_HCD_HC_NotifyURBChange_Callback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num].urb_state);
+#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
+  }
+  else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_NAK) == USB_OTG_HCINT_NAK)
+  {
+    if (hhcd->hc[ch_num].ep_type == EP_TYPE_INTR)
+    {
+      hhcd->hc[ch_num].ErrCnt = 0U;
+      (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
+    }
+    else if ((hhcd->hc[ch_num].ep_type == EP_TYPE_CTRL) ||
+             (hhcd->hc[ch_num].ep_type == EP_TYPE_BULK))
+    {
+      hhcd->hc[ch_num].ErrCnt = 0U;
+
+      if (hhcd->Init.dma_enable == 0U)
+      {
+        hhcd->hc[ch_num].state = HC_NAK;
+        (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
+      }
+    }
+    else
+    {
+      /* ... */
+    }
+    __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_NAK);
+  }
+  else
+  {
+    /* ... */
+  }
+}
+
+/**
+  * @brief  Handle Host Channel OUT interrupt requests.
+  * @param  hhcd HCD handle
+  * @param  chnum Channel number.
+  *         This parameter can be a value from 1 to 15
+  * @retval none
+  */
+static void HCD_HC_OUT_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum)
+{
+  USB_OTG_GlobalTypeDef *USBx = hhcd->Instance;
+  uint32_t USBx_BASE = (uint32_t)USBx;
+  uint32_t ch_num = (uint32_t)chnum;
+  uint32_t tmpreg;
+  uint32_t num_packets;
+
+  if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_AHBERR) == USB_OTG_HCINT_AHBERR)
+  {
+    __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_AHBERR);
+    hhcd->hc[ch_num].state = HC_XACTERR;
+    (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
+  }
+  else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_ACK) == USB_OTG_HCINT_ACK)
+  {
+    __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_ACK);
+
+    if (hhcd->hc[ch_num].do_ping == 1U)
+    {
+      hhcd->hc[ch_num].do_ping = 0U;
+      hhcd->hc[ch_num].urb_state = URB_NOTREADY;
+      (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
+    }
+  }
+  else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_FRMOR) == USB_OTG_HCINT_FRMOR)
+  {
+    __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_FRMOR);
+    (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
+  }
+  else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_XFRC) == USB_OTG_HCINT_XFRC)
+  {
+    hhcd->hc[ch_num].ErrCnt = 0U;
+
+    /* transaction completed with NYET state, update do ping state */
+    if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_NYET) == USB_OTG_HCINT_NYET)
+    {
+      hhcd->hc[ch_num].do_ping = 1U;
+      __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_NYET);
+    }
+    __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_XFRC);
+    hhcd->hc[ch_num].state = HC_XFRC;
+    (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
+  }
+  else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_NYET) == USB_OTG_HCINT_NYET)
+  {
+    hhcd->hc[ch_num].state = HC_NYET;
+    hhcd->hc[ch_num].do_ping = 1U;
+    hhcd->hc[ch_num].ErrCnt = 0U;
+    (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
+    __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_NYET);
+  }
+  else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_STALL) == USB_OTG_HCINT_STALL)
+  {
+    __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_STALL);
+    hhcd->hc[ch_num].state = HC_STALL;
+    (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
+  }
+  else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_NAK) == USB_OTG_HCINT_NAK)
+  {
+    hhcd->hc[ch_num].ErrCnt = 0U;
+    hhcd->hc[ch_num].state = HC_NAK;
+
+    if (hhcd->hc[ch_num].do_ping == 0U)
+    {
+      if (hhcd->hc[ch_num].speed == HCD_DEVICE_SPEED_HIGH)
+      {
+        hhcd->hc[ch_num].do_ping = 1U;
+      }
+    }
+
+    (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
+    __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_NAK);
+  }
+  else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_TXERR) == USB_OTG_HCINT_TXERR)
+  {
+    if (hhcd->Init.dma_enable == 0U)
+    {
+      hhcd->hc[ch_num].state = HC_XACTERR;
+      (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
+    }
+    else
+    {
+      hhcd->hc[ch_num].ErrCnt++;
+      if (hhcd->hc[ch_num].ErrCnt > 2U)
+      {
+        hhcd->hc[ch_num].ErrCnt = 0U;
+        hhcd->hc[ch_num].urb_state = URB_ERROR;
+
+#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
+        hhcd->HC_NotifyURBChangeCallback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num].urb_state);
+#else
+        HAL_HCD_HC_NotifyURBChange_Callback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num].urb_state);
+#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
+      }
+      else
+      {
+        hhcd->hc[ch_num].urb_state = URB_NOTREADY;
+      }
+    }
+    __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_TXERR);
+  }
+  else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_DTERR) == USB_OTG_HCINT_DTERR)
+  {
+    hhcd->hc[ch_num].state = HC_DATATGLERR;
+    (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
+    __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_DTERR);
+  }
+  else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_CHH) == USB_OTG_HCINT_CHH)
+  {
+    if (hhcd->hc[ch_num].state == HC_XFRC)
+    {
+      hhcd->hc[ch_num].urb_state  = URB_DONE;
+      if ((hhcd->hc[ch_num].ep_type == EP_TYPE_BULK) ||
+          (hhcd->hc[ch_num].ep_type == EP_TYPE_INTR))
+      {
+        if (hhcd->Init.dma_enable == 0U)
+        {
+          hhcd->hc[ch_num].toggle_out ^= 1U;
+        }
+
+        if ((hhcd->Init.dma_enable == 1U) && (hhcd->hc[ch_num].xfer_len > 0U))
+        {
+          num_packets = (hhcd->hc[ch_num].xfer_len + hhcd->hc[ch_num].max_packet - 1U) / hhcd->hc[ch_num].max_packet;
+
+          if ((num_packets & 1U) != 0U)
+          {
+            hhcd->hc[ch_num].toggle_out ^= 1U;
+          }
+        }
+      }
+    }
+    else if (hhcd->hc[ch_num].state == HC_NAK)
+    {
+      hhcd->hc[ch_num].urb_state = URB_NOTREADY;
+    }
+    else if (hhcd->hc[ch_num].state == HC_NYET)
+    {
+      hhcd->hc[ch_num].urb_state  = URB_NOTREADY;
+    }
+    else if (hhcd->hc[ch_num].state == HC_STALL)
+    {
+      hhcd->hc[ch_num].urb_state  = URB_STALL;
+    }
+    else if ((hhcd->hc[ch_num].state == HC_XACTERR) ||
+             (hhcd->hc[ch_num].state == HC_DATATGLERR))
+    {
+      hhcd->hc[ch_num].ErrCnt++;
+      if (hhcd->hc[ch_num].ErrCnt > 2U)
+      {
+        hhcd->hc[ch_num].ErrCnt = 0U;
+        hhcd->hc[ch_num].urb_state = URB_ERROR;
+      }
+      else
+      {
+        hhcd->hc[ch_num].urb_state = URB_NOTREADY;
+
+        /* re-activate the channel  */
+        tmpreg = USBx_HC(ch_num)->HCCHAR;
+        tmpreg &= ~USB_OTG_HCCHAR_CHDIS;
+        tmpreg |= USB_OTG_HCCHAR_CHENA;
+        USBx_HC(ch_num)->HCCHAR = tmpreg;
+      }
+    }
+    else
+    {
+      /* ... */
+    }
+
+    __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_CHH);
+
+#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
+    hhcd->HC_NotifyURBChangeCallback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num].urb_state);
+#else
+    HAL_HCD_HC_NotifyURBChange_Callback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num].urb_state);
+#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
+  }
+  else
+  {
+    /* ... */
+  }
+}
+
+/**
+  * @brief  Handle Rx Queue Level interrupt requests.
+  * @param  hhcd HCD handle
+  * @retval none
+  */
+static void HCD_RXQLVL_IRQHandler(HCD_HandleTypeDef *hhcd)
+{
+  USB_OTG_GlobalTypeDef *USBx = hhcd->Instance;
+  uint32_t USBx_BASE = (uint32_t)USBx;
+  uint32_t pktsts;
+  uint32_t pktcnt;
+  uint32_t GrxstspReg;
+  uint32_t xferSizePktCnt;
+  uint32_t tmpreg;
+  uint32_t ch_num;
+
+  GrxstspReg = hhcd->Instance->GRXSTSP;
+  ch_num = GrxstspReg & USB_OTG_GRXSTSP_EPNUM;
+  pktsts = (GrxstspReg & USB_OTG_GRXSTSP_PKTSTS) >> 17;
+  pktcnt = (GrxstspReg & USB_OTG_GRXSTSP_BCNT) >> 4;
+
+  switch (pktsts)
+  {
+    case GRXSTS_PKTSTS_IN:
+      /* Read the data into the host buffer. */
+      if ((pktcnt > 0U) && (hhcd->hc[ch_num].xfer_buff != (void *)0))
+      {
+        if ((hhcd->hc[ch_num].xfer_count + pktcnt) <= hhcd->hc[ch_num].xfer_len)
+        {
+          (void)USB_ReadPacket(hhcd->Instance,
+                               hhcd->hc[ch_num].xfer_buff, (uint16_t)pktcnt);
+
+          /* manage multiple Xfer */
+          hhcd->hc[ch_num].xfer_buff += pktcnt;
+          hhcd->hc[ch_num].xfer_count += pktcnt;
+
+          /* get transfer size packet count */
+          xferSizePktCnt = (USBx_HC(ch_num)->HCTSIZ & USB_OTG_HCTSIZ_PKTCNT) >> 19;
+
+          if ((hhcd->hc[ch_num].max_packet == pktcnt) && (xferSizePktCnt > 0U))
+          {
+            /* re-activate the channel when more packets are expected */
+            tmpreg = USBx_HC(ch_num)->HCCHAR;
+            tmpreg &= ~USB_OTG_HCCHAR_CHDIS;
+            tmpreg |= USB_OTG_HCCHAR_CHENA;
+            USBx_HC(ch_num)->HCCHAR = tmpreg;
+            hhcd->hc[ch_num].toggle_in ^= 1U;
+          }
+        }
+        else
+        {
+          hhcd->hc[ch_num].urb_state = URB_ERROR;
+        }
+      }
+      break;
+
+    case GRXSTS_PKTSTS_DATA_TOGGLE_ERR:
+      break;
+
+    case GRXSTS_PKTSTS_IN_XFER_COMP:
+    case GRXSTS_PKTSTS_CH_HALTED:
+    default:
+      break;
+  }
+}
+
+/**
+  * @brief  Handle Host Port interrupt requests.
+  * @param  hhcd HCD handle
+  * @retval None
+  */
+static void HCD_Port_IRQHandler(HCD_HandleTypeDef *hhcd)
+{
+  USB_OTG_GlobalTypeDef *USBx = hhcd->Instance;
+  uint32_t USBx_BASE = (uint32_t)USBx;
+  __IO uint32_t hprt0;
+  __IO uint32_t hprt0_dup;
+
+  /* Handle Host Port Interrupts */
+  hprt0 = USBx_HPRT0;
+  hprt0_dup = USBx_HPRT0;
+
+  hprt0_dup &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET | \
+                 USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG);
+
+  /* Check whether Port Connect detected */
+  if ((hprt0 & USB_OTG_HPRT_PCDET) == USB_OTG_HPRT_PCDET)
+  {
+    if ((hprt0 & USB_OTG_HPRT_PCSTS) == USB_OTG_HPRT_PCSTS)
+    {
+#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
+      hhcd->ConnectCallback(hhcd);
+#else
+      HAL_HCD_Connect_Callback(hhcd);
+#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
+    }
+    hprt0_dup |= USB_OTG_HPRT_PCDET;
+  }
+
+  /* Check whether Port Enable Changed */
+  if ((hprt0 & USB_OTG_HPRT_PENCHNG) == USB_OTG_HPRT_PENCHNG)
+  {
+    hprt0_dup |= USB_OTG_HPRT_PENCHNG;
+
+    if ((hprt0 & USB_OTG_HPRT_PENA) == USB_OTG_HPRT_PENA)
+    {
+      if (hhcd->Init.phy_itface  == USB_OTG_EMBEDDED_PHY)
+      {
+        if ((hprt0 & USB_OTG_HPRT_PSPD) == (HPRT0_PRTSPD_LOW_SPEED << 17))
+        {
+          (void)USB_InitFSLSPClkSel(hhcd->Instance, HCFG_6_MHZ);
+        }
+        else
+        {
+          (void)USB_InitFSLSPClkSel(hhcd->Instance, HCFG_48_MHZ);
+        }
+      }
+      else
+      {
+        if (hhcd->Init.speed == HCD_SPEED_FULL)
+        {
+          USBx_HOST->HFIR = 60000U;
+        }
+      }
+#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
+      hhcd->PortEnabledCallback(hhcd);
+#else
+      HAL_HCD_PortEnabled_Callback(hhcd);
+#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
+
+    }
+    else
+    {
+#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
+      hhcd->PortDisabledCallback(hhcd);
+#else
+      HAL_HCD_PortDisabled_Callback(hhcd);
+#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
+    }
+  }
+
+  /* Check for an overcurrent */
+  if ((hprt0 & USB_OTG_HPRT_POCCHNG) == USB_OTG_HPRT_POCCHNG)
+  {
+    hprt0_dup |= USB_OTG_HPRT_POCCHNG;
+  }
+
+  /* Clear Port Interrupts */
+  USBx_HPRT0 = hprt0_dup;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
+#endif /* HAL_HCD_MODULE_ENABLED */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
diff --git a/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c
new file mode 100644
index 0000000..44487dc
--- /dev/null
+++ b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c
@@ -0,0 +1,7524 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hal_i2c.c
+  * @author  MCD Application Team
+  * @brief   I2C HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the Inter Integrated Circuit (I2C) peripheral:
+  *           + Initialization and de-initialization functions
+  *           + IO operation functions
+  *           + Peripheral State, Mode and Error functions
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2016 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  @verbatim
+  ==============================================================================
+                        ##### How to use this driver #####
+  ==============================================================================
+  [..]
+    The I2C HAL driver can be used as follows:
+
+    (#) Declare a I2C_HandleTypeDef handle structure, for example:
+        I2C_HandleTypeDef  hi2c;
+
+    (#)Initialize the I2C low level resources by implementing the HAL_I2C_MspInit() API:
+        (##) Enable the I2Cx interface clock
+        (##) I2C pins configuration
+            (+++) Enable the clock for the I2C GPIOs
+            (+++) Configure I2C pins as alternate function open-drain
+        (##) NVIC configuration if you need to use interrupt process
+            (+++) Configure the I2Cx interrupt priority
+            (+++) Enable the NVIC I2C IRQ Channel
+        (##) DMA Configuration if you need to use DMA process
+            (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive stream
+            (+++) Enable the DMAx interface clock using
+            (+++) Configure the DMA handle parameters
+            (+++) Configure the DMA Tx or Rx stream
+            (+++) Associate the initialized DMA handle to the hi2c DMA Tx or Rx handle
+            (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on
+                  the DMA Tx or Rx stream
+
+    (#) Configure the Communication Speed, Duty cycle, Addressing mode, Own Address1,
+        Dual Addressing mode, Own Address2, General call and Nostretch mode in the hi2c Init structure.
+
+    (#) Initialize the I2C registers by calling the HAL_I2C_Init(), configures also the low level Hardware
+        (GPIO, CLOCK, NVIC...etc) by calling the customized HAL_I2C_MspInit() API.
+
+    (#) To check if target device is ready for communication, use the function HAL_I2C_IsDeviceReady()
+
+    (#) For I2C IO and IO MEM operations, three operation modes are available within this driver :
+
+    *** Polling mode IO operation ***
+    =================================
+    [..]
+      (+) Transmit in master mode an amount of data in blocking mode using HAL_I2C_Master_Transmit()
+      (+) Receive in master mode an amount of data in blocking mode using HAL_I2C_Master_Receive()
+      (+) Transmit in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Transmit()
+      (+) Receive in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Receive()
+
+    *** Polling mode IO MEM operation ***
+    =====================================
+    [..]
+      (+) Write an amount of data in blocking mode to a specific memory address using HAL_I2C_Mem_Write()
+      (+) Read an amount of data in blocking mode from a specific memory address using HAL_I2C_Mem_Read()
+
+
+    *** Interrupt mode IO operation ***
+    ===================================
+    [..]
+      (+) Transmit in master mode an amount of data in non-blocking mode using HAL_I2C_Master_Transmit_IT()
+      (+) At transmission end of transfer, HAL_I2C_MasterTxCpltCallback() is executed and user can
+           add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback()
+      (+) Receive in master mode an amount of data in non-blocking mode using HAL_I2C_Master_Receive_IT()
+      (+) At reception end of transfer, HAL_I2C_MasterRxCpltCallback() is executed and user can
+           add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback()
+      (+) Transmit in slave mode an amount of data in non-blocking mode using HAL_I2C_Slave_Transmit_IT()
+      (+) At transmission end of transfer, HAL_I2C_SlaveTxCpltCallback() is executed and user can
+           add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback()
+      (+) Receive in slave mode an amount of data in non-blocking mode using HAL_I2C_Slave_Receive_IT()
+      (+) At reception end of transfer, HAL_I2C_SlaveRxCpltCallback() is executed and user can
+           add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback()
+      (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
+           add his own code by customization of function pointer HAL_I2C_ErrorCallback()
+      (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
+      (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can
+           add his own code by customization of function pointer HAL_I2C_AbortCpltCallback()
+
+    *** Interrupt mode or DMA mode IO sequential operation ***
+    ==========================================================
+    [..]
+      (@) These interfaces allow to manage a sequential transfer with a repeated start condition
+          when a direction change during transfer
+    [..]
+      (+) A specific option field manage the different steps of a sequential transfer
+      (+) Option field values are defined through I2C_XferOptions_definition and are listed below:
+      (++) I2C_FIRST_AND_LAST_FRAME: No sequential usage, functional is same as associated interfaces in no sequential mode
+      (++) I2C_FIRST_FRAME: Sequential usage, this option allow to manage a sequence with start condition, address
+                            and data to transfer without a final stop condition
+      (++) I2C_FIRST_AND_NEXT_FRAME: Sequential usage (Master only), this option allow to manage a sequence with start condition, address
+                            and data to transfer without a final stop condition, an then permit a call the same master sequential interface
+                            several times (like HAL_I2C_Master_Seq_Transmit_IT() then HAL_I2C_Master_Seq_Transmit_IT()
+                            or HAL_I2C_Master_Seq_Transmit_DMA() then HAL_I2C_Master_Seq_Transmit_DMA())
+      (++) I2C_NEXT_FRAME: Sequential usage, this option allow to manage a sequence with a restart condition, address
+                            and with new data to transfer if the direction change or manage only the new data to transfer
+                            if no direction change and without a final stop condition in both cases
+      (++) I2C_LAST_FRAME: Sequential usage, this option allow to manage a sequance with a restart condition, address
+                            and with new data to transfer if the direction change or manage only the new data to transfer
+                            if no direction change and with a final stop condition in both cases
+      (++) I2C_LAST_FRAME_NO_STOP: Sequential usage (Master only), this option allow to manage a restart condition after several call of the same master sequential
+                            interface several times (link with option I2C_FIRST_AND_NEXT_FRAME).
+                            Usage can, transfer several bytes one by one using HAL_I2C_Master_Seq_Transmit_IT(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME)
+                              or HAL_I2C_Master_Seq_Receive_IT(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME)
+                              or HAL_I2C_Master_Seq_Transmit_DMA(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME)
+                              or HAL_I2C_Master_Seq_Receive_DMA(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME).
+                            Then usage of this option I2C_LAST_FRAME_NO_STOP at the last Transmit or Receive sequence permit to call the opposite interface Receive or Transmit
+                              without stopping the communication and so generate a restart condition.
+      (++) I2C_OTHER_FRAME: Sequential usage (Master only), this option allow to manage a restart condition after each call of the same master sequential
+                            interface.
+                            Usage can, transfer several bytes one by one with a restart with slave address between each bytes using HAL_I2C_Master_Seq_Transmit_IT(option I2C_FIRST_FRAME then I2C_OTHER_FRAME)
+                              or HAL_I2C_Master_Seq_Receive_IT(option I2C_FIRST_FRAME then I2C_OTHER_FRAME)
+                              or HAL_I2C_Master_Seq_Transmit_DMA(option I2C_FIRST_FRAME then I2C_OTHER_FRAME)
+                              or HAL_I2C_Master_Seq_Receive_DMA(option I2C_FIRST_FRAME then I2C_OTHER_FRAME).
+                            Then usage of this option I2C_OTHER_AND_LAST_FRAME at the last frame to help automatic generation of STOP condition.
+
+      (+) Different sequential I2C interfaces are listed below:
+      (++) Sequential transmit in master I2C mode an amount of data in non-blocking mode using HAL_I2C_Master_Seq_Transmit_IT()
+            or using HAL_I2C_Master_Seq_Transmit_DMA()
+      (+++) At transmission end of current frame transfer, HAL_I2C_MasterTxCpltCallback() is executed and user can
+           add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback()
+      (++) Sequential receive in master I2C mode an amount of data in non-blocking mode using HAL_I2C_Master_Seq_Receive_IT()
+            or using HAL_I2C_Master_Seq_Receive_DMA()
+      (+++) At reception end of current frame transfer, HAL_I2C_MasterRxCpltCallback() is executed and user can
+           add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback()
+      (++) Abort a master IT or DMA I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
+      (+++) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can
+           add his own code by customization of function pointer HAL_I2C_AbortCpltCallback()
+      (++) Enable/disable the Address listen mode in slave I2C mode using HAL_I2C_EnableListen_IT() HAL_I2C_DisableListen_IT()
+      (+++) When address slave I2C match, HAL_I2C_AddrCallback() is executed and user can
+           add his own code to check the Address Match Code and the transmission direction request by master (Write/Read).
+      (+++) At Listen mode end HAL_I2C_ListenCpltCallback() is executed and user can
+           add his own code by customization of function pointer HAL_I2C_ListenCpltCallback()
+      (++) Sequential transmit in slave I2C mode an amount of data in non-blocking mode using HAL_I2C_Slave_Seq_Transmit_IT()
+            or using HAL_I2C_Slave_Seq_Transmit_DMA()
+      (+++) At transmission end of current frame transfer, HAL_I2C_SlaveTxCpltCallback() is executed and user can
+           add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback()
+      (++) Sequential receive in slave I2C mode an amount of data in non-blocking mode using HAL_I2C_Slave_Seq_Receive_IT()
+            or using HAL_I2C_Slave_Seq_Receive_DMA()
+      (+++) At reception end of current frame transfer, HAL_I2C_SlaveRxCpltCallback() is executed and user can
+           add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback()
+      (++) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
+           add his own code by customization of function pointer HAL_I2C_ErrorCallback()
+
+    *** Interrupt mode IO MEM operation ***
+    =======================================
+    [..]
+      (+) Write an amount of data in non-blocking mode with Interrupt to a specific memory address using
+          HAL_I2C_Mem_Write_IT()
+      (+) At Memory end of write transfer, HAL_I2C_MemTxCpltCallback() is executed and user can
+           add his own code by customization of function pointer HAL_I2C_MemTxCpltCallback()
+      (+) Read an amount of data in non-blocking mode with Interrupt from a specific memory address using
+          HAL_I2C_Mem_Read_IT()
+      (+) At Memory end of read transfer, HAL_I2C_MemRxCpltCallback() is executed and user can
+           add his own code by customization of function pointer HAL_I2C_MemRxCpltCallback()
+      (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
+           add his own code by customization of function pointer HAL_I2C_ErrorCallback()
+
+    *** DMA mode IO operation ***
+    ==============================
+    [..]
+      (+) Transmit in master mode an amount of data in non-blocking mode (DMA) using
+          HAL_I2C_Master_Transmit_DMA()
+      (+) At transmission end of transfer, HAL_I2C_MasterTxCpltCallback() is executed and user can
+           add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback()
+      (+) Receive in master mode an amount of data in non-blocking mode (DMA) using
+          HAL_I2C_Master_Receive_DMA()
+      (+) At reception end of transfer, HAL_I2C_MasterRxCpltCallback() is executed and user can
+           add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback()
+      (+) Transmit in slave mode an amount of data in non-blocking mode (DMA) using
+          HAL_I2C_Slave_Transmit_DMA()
+      (+) At transmission end of transfer, HAL_I2C_SlaveTxCpltCallback() is executed and user can
+           add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback()
+      (+) Receive in slave mode an amount of data in non-blocking mode (DMA) using
+          HAL_I2C_Slave_Receive_DMA()
+      (+) At reception end of transfer, HAL_I2C_SlaveRxCpltCallback() is executed and user can
+           add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback()
+      (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
+           add his own code by customization of function pointer HAL_I2C_ErrorCallback()
+      (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
+      (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can
+           add his own code by customization of function pointer HAL_I2C_AbortCpltCallback()
+
+    *** DMA mode IO MEM operation ***
+    =================================
+    [..]
+      (+) Write an amount of data in non-blocking mode with DMA to a specific memory address using
+          HAL_I2C_Mem_Write_DMA()
+      (+) At Memory end of write transfer, HAL_I2C_MemTxCpltCallback() is executed and user can
+           add his own code by customization of function pointer HAL_I2C_MemTxCpltCallback()
+      (+) Read an amount of data in non-blocking mode with DMA from a specific memory address using
+          HAL_I2C_Mem_Read_DMA()
+      (+) At Memory end of read transfer, HAL_I2C_MemRxCpltCallback() is executed and user can
+           add his own code by customization of function pointer HAL_I2C_MemRxCpltCallback()
+      (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
+           add his own code by customization of function pointer HAL_I2C_ErrorCallback()
+
+
+     *** I2C HAL driver macros list ***
+     ==================================
+     [..]
+       Below the list of most used macros in I2C HAL driver.
+
+      (+) __HAL_I2C_ENABLE:     Enable the I2C peripheral
+      (+) __HAL_I2C_DISABLE:    Disable the I2C peripheral
+      (+) __HAL_I2C_GET_FLAG:   Checks whether the specified I2C flag is set or not
+      (+) __HAL_I2C_CLEAR_FLAG: Clear the specified I2C pending flag
+      (+) __HAL_I2C_ENABLE_IT:  Enable the specified I2C interrupt
+      (+) __HAL_I2C_DISABLE_IT: Disable the specified I2C interrupt
+
+     *** Callback registration ***
+     =============================================
+    [..]
+     The compilation flag USE_HAL_I2C_REGISTER_CALLBACKS when set to 1
+     allows the user to configure dynamically the driver callbacks.
+     Use Functions HAL_I2C_RegisterCallback() or HAL_I2C_RegisterAddrCallback()
+     to register an interrupt callback.
+    [..]
+     Function HAL_I2C_RegisterCallback() allows to register following callbacks:
+       (+) MasterTxCpltCallback : callback for Master transmission end of transfer.
+       (+) MasterRxCpltCallback : callback for Master reception end of transfer.
+       (+) SlaveTxCpltCallback  : callback for Slave transmission end of transfer.
+       (+) SlaveRxCpltCallback  : callback for Slave reception end of transfer.
+       (+) ListenCpltCallback   : callback for end of listen mode.
+       (+) MemTxCpltCallback    : callback for Memory transmission end of transfer.
+       (+) MemRxCpltCallback    : callback for Memory reception end of transfer.
+       (+) ErrorCallback        : callback for error detection.
+       (+) AbortCpltCallback    : callback for abort completion process.
+       (+) MspInitCallback      : callback for Msp Init.
+       (+) MspDeInitCallback    : callback for Msp DeInit.
+     This function takes as parameters the HAL peripheral handle, the Callback ID
+     and a pointer to the user callback function.
+    [..]
+     For specific callback AddrCallback use dedicated register callbacks : HAL_I2C_RegisterAddrCallback().
+    [..]
+     Use function HAL_I2C_UnRegisterCallback to reset a callback to the default
+     weak function.
+     HAL_I2C_UnRegisterCallback takes as parameters the HAL peripheral handle,
+     and the Callback ID.
+     This function allows to reset following callbacks:
+       (+) MasterTxCpltCallback : callback for Master transmission end of transfer.
+       (+) MasterRxCpltCallback : callback for Master reception end of transfer.
+       (+) SlaveTxCpltCallback  : callback for Slave transmission end of transfer.
+       (+) SlaveRxCpltCallback  : callback for Slave reception end of transfer.
+       (+) ListenCpltCallback   : callback for end of listen mode.
+       (+) MemTxCpltCallback    : callback for Memory transmission end of transfer.
+       (+) MemRxCpltCallback    : callback for Memory reception end of transfer.
+       (+) ErrorCallback        : callback for error detection.
+       (+) AbortCpltCallback    : callback for abort completion process.
+       (+) MspInitCallback      : callback for Msp Init.
+       (+) MspDeInitCallback    : callback for Msp DeInit.
+    [..]
+     For callback AddrCallback use dedicated register callbacks : HAL_I2C_UnRegisterAddrCallback().
+    [..]
+     By default, after the HAL_I2C_Init() and when the state is HAL_I2C_STATE_RESET
+     all callbacks are set to the corresponding weak functions:
+     examples HAL_I2C_MasterTxCpltCallback(), HAL_I2C_MasterRxCpltCallback().
+     Exception done for MspInit and MspDeInit functions that are
+     reset to the legacy weak functions in the HAL_I2C_Init()/ HAL_I2C_DeInit() only when
+     these callbacks are null (not registered beforehand).
+     If MspInit or MspDeInit are not null, the HAL_I2C_Init()/ HAL_I2C_DeInit()
+     keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
+    [..]
+     Callbacks can be registered/unregistered in HAL_I2C_STATE_READY state only.
+     Exception done MspInit/MspDeInit functions that can be registered/unregistered
+     in HAL_I2C_STATE_READY or HAL_I2C_STATE_RESET state,
+     thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
+     Then, the user first registers the MspInit/MspDeInit user callbacks
+     using HAL_I2C_RegisterCallback() before calling HAL_I2C_DeInit()
+     or HAL_I2C_Init() function.
+    [..]
+     When the compilation flag USE_HAL_I2C_REGISTER_CALLBACKS is set to 0 or
+     not defined, the callback registration feature is not available and all callbacks
+     are set to the corresponding weak functions.
+
+
+
+     [..]
+       (@) You can refer to the I2C HAL driver header file for more useful macros
+
+  @endverbatim
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup I2C I2C
+  * @brief I2C HAL module driver
+  * @{
+  */
+
+#ifdef HAL_I2C_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @addtogroup I2C_Private_Define
+  * @{
+  */
+#define I2C_TIMEOUT_FLAG          35U         /*!< Timeout 35 ms             */
+#define I2C_TIMEOUT_BUSY_FLAG     25U         /*!< Timeout 25 ms             */
+#define I2C_TIMEOUT_STOP_FLAG     5U          /*!< Timeout 5 ms              */
+#define I2C_NO_OPTION_FRAME       0xFFFF0000U /*!< XferOptions default value */
+
+/* Private define for @ref PreviousState usage */
+#define I2C_STATE_MSK             ((uint32_t)((uint32_t)((uint32_t)HAL_I2C_STATE_BUSY_TX | (uint32_t)HAL_I2C_STATE_BUSY_RX) & (uint32_t)(~((uint32_t)HAL_I2C_STATE_READY)))) /*!< Mask State define, keep only RX and TX bits            */
+#define I2C_STATE_NONE            ((uint32_t)(HAL_I2C_MODE_NONE))                                                        /*!< Default Value                                          */
+#define I2C_STATE_MASTER_BUSY_TX  ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_MASTER))            /*!< Master Busy TX, combinaison of State LSB and Mode enum */
+#define I2C_STATE_MASTER_BUSY_RX  ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_MASTER))            /*!< Master Busy RX, combinaison of State LSB and Mode enum */
+#define I2C_STATE_SLAVE_BUSY_TX   ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_SLAVE))             /*!< Slave Busy TX, combinaison of State LSB and Mode enum  */
+#define I2C_STATE_SLAVE_BUSY_RX   ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_SLAVE))             /*!< Slave Busy RX, combinaison of State LSB and Mode enum  */
+
+/**
+  * @}
+  */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+
+/** @defgroup I2C_Private_Functions I2C Private Functions
+  * @{
+  */
+/* Private functions to handle DMA transfer */
+static void I2C_DMAXferCplt(DMA_HandleTypeDef *hdma);
+static void I2C_DMAError(DMA_HandleTypeDef *hdma);
+static void I2C_DMAAbort(DMA_HandleTypeDef *hdma);
+
+static void I2C_ITError(I2C_HandleTypeDef *hi2c);
+
+static HAL_StatusTypeDef I2C_MasterRequestWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout, uint32_t Tickstart);
+static HAL_StatusTypeDef I2C_MasterRequestRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout, uint32_t Tickstart);
+static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart);
+static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart);
+
+/* Private functions to handle flags during polling transfer */
+static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart);
+static HAL_StatusTypeDef I2C_WaitOnMasterAddressFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, uint32_t Timeout, uint32_t Tickstart);
+static HAL_StatusTypeDef I2C_WaitOnTXEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);
+static HAL_StatusTypeDef I2C_WaitOnBTFFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);
+static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);
+static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);
+static HAL_StatusTypeDef I2C_WaitOnSTOPRequestThroughIT(I2C_HandleTypeDef *hi2c);
+static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c);
+
+/* Private functions for I2C transfer IRQ handler */
+static void I2C_MasterTransmit_TXE(I2C_HandleTypeDef *hi2c);
+static void I2C_MasterTransmit_BTF(I2C_HandleTypeDef *hi2c);
+static void I2C_MasterReceive_RXNE(I2C_HandleTypeDef *hi2c);
+static void I2C_MasterReceive_BTF(I2C_HandleTypeDef *hi2c);
+static void I2C_Master_SB(I2C_HandleTypeDef *hi2c);
+static void I2C_Master_ADD10(I2C_HandleTypeDef *hi2c);
+static void I2C_Master_ADDR(I2C_HandleTypeDef *hi2c);
+
+static void I2C_SlaveTransmit_TXE(I2C_HandleTypeDef *hi2c);
+static void I2C_SlaveTransmit_BTF(I2C_HandleTypeDef *hi2c);
+static void I2C_SlaveReceive_RXNE(I2C_HandleTypeDef *hi2c);
+static void I2C_SlaveReceive_BTF(I2C_HandleTypeDef *hi2c);
+static void I2C_Slave_ADDR(I2C_HandleTypeDef *hi2c, uint32_t IT2Flags);
+static void I2C_Slave_STOPF(I2C_HandleTypeDef *hi2c);
+static void I2C_Slave_AF(I2C_HandleTypeDef *hi2c);
+
+static void I2C_MemoryTransmit_TXE_BTF(I2C_HandleTypeDef *hi2c);
+
+/* Private function to Convert Specific options */
+static void I2C_ConvertOtherXferOptions(I2C_HandleTypeDef *hi2c);
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup I2C_Exported_Functions I2C Exported Functions
+  * @{
+  */
+
+/** @defgroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions
+ *  @brief    Initialization and Configuration functions
+ *
+@verbatim
+ ===============================================================================
+              ##### Initialization and de-initialization functions #####
+ ===============================================================================
+    [..]  This subsection provides a set of functions allowing to initialize and
+          deinitialize the I2Cx peripheral:
+
+      (+) User must Implement HAL_I2C_MspInit() function in which he configures
+          all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC).
+
+      (+) Call the function HAL_I2C_Init() to configure the selected device with
+          the selected configuration:
+        (++) Communication Speed
+        (++) Duty cycle
+        (++) Addressing mode
+        (++) Own Address 1
+        (++) Dual Addressing mode
+        (++) Own Address 2
+        (++) General call mode
+        (++) Nostretch mode
+
+      (+) Call the function HAL_I2C_DeInit() to restore the default configuration
+          of the selected I2Cx peripheral.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initializes the I2C according to the specified parameters
+  *         in the I2C_InitTypeDef and initialize the associated handle.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c)
+{
+  uint32_t freqrange;
+  uint32_t pclk1;
+
+  /* Check the I2C handle allocation */
+  if (hi2c == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
+  assert_param(IS_I2C_CLOCK_SPEED(hi2c->Init.ClockSpeed));
+  assert_param(IS_I2C_DUTY_CYCLE(hi2c->Init.DutyCycle));
+  assert_param(IS_I2C_OWN_ADDRESS1(hi2c->Init.OwnAddress1));
+  assert_param(IS_I2C_ADDRESSING_MODE(hi2c->Init.AddressingMode));
+  assert_param(IS_I2C_DUAL_ADDRESS(hi2c->Init.DualAddressMode));
+  assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2));
+  assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode));
+  assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode));
+
+  if (hi2c->State == HAL_I2C_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    hi2c->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+    /* Init the I2C Callback settings */
+    hi2c->MasterTxCpltCallback = HAL_I2C_MasterTxCpltCallback; /* Legacy weak MasterTxCpltCallback */
+    hi2c->MasterRxCpltCallback = HAL_I2C_MasterRxCpltCallback; /* Legacy weak MasterRxCpltCallback */
+    hi2c->SlaveTxCpltCallback  = HAL_I2C_SlaveTxCpltCallback;  /* Legacy weak SlaveTxCpltCallback  */
+    hi2c->SlaveRxCpltCallback  = HAL_I2C_SlaveRxCpltCallback;  /* Legacy weak SlaveRxCpltCallback  */
+    hi2c->ListenCpltCallback   = HAL_I2C_ListenCpltCallback;   /* Legacy weak ListenCpltCallback   */
+    hi2c->MemTxCpltCallback    = HAL_I2C_MemTxCpltCallback;    /* Legacy weak MemTxCpltCallback    */
+    hi2c->MemRxCpltCallback    = HAL_I2C_MemRxCpltCallback;    /* Legacy weak MemRxCpltCallback    */
+    hi2c->ErrorCallback        = HAL_I2C_ErrorCallback;        /* Legacy weak ErrorCallback        */
+    hi2c->AbortCpltCallback    = HAL_I2C_AbortCpltCallback;    /* Legacy weak AbortCpltCallback    */
+    hi2c->AddrCallback         = HAL_I2C_AddrCallback;         /* Legacy weak AddrCallback         */
+
+    if (hi2c->MspInitCallback == NULL)
+    {
+      hi2c->MspInitCallback = HAL_I2C_MspInit; /* Legacy weak MspInit  */
+    }
+
+    /* Init the low level hardware : GPIO, CLOCK, NVIC */
+    hi2c->MspInitCallback(hi2c);
+#else
+    /* Init the low level hardware : GPIO, CLOCK, NVIC */
+    HAL_I2C_MspInit(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+  }
+
+  hi2c->State = HAL_I2C_STATE_BUSY;
+
+  /* Disable the selected I2C peripheral */
+  __HAL_I2C_DISABLE(hi2c);
+
+  /*Reset I2C*/
+  hi2c->Instance->CR1 |= I2C_CR1_SWRST;
+  hi2c->Instance->CR1 &= ~I2C_CR1_SWRST;
+
+  /* Get PCLK1 frequency */
+  pclk1 = HAL_RCC_GetPCLK1Freq();
+
+  /* Check the minimum allowed PCLK1 frequency */
+  if (I2C_MIN_PCLK_FREQ(pclk1, hi2c->Init.ClockSpeed) == 1U)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Calculate frequency range */
+  freqrange = I2C_FREQRANGE(pclk1);
+
+  /*---------------------------- I2Cx CR2 Configuration ----------------------*/
+  /* Configure I2Cx: Frequency range */
+  MODIFY_REG(hi2c->Instance->CR2, I2C_CR2_FREQ, freqrange);
+
+  /*---------------------------- I2Cx TRISE Configuration --------------------*/
+  /* Configure I2Cx: Rise Time */
+  MODIFY_REG(hi2c->Instance->TRISE, I2C_TRISE_TRISE, I2C_RISE_TIME(freqrange, hi2c->Init.ClockSpeed));
+
+  /*---------------------------- I2Cx CCR Configuration ----------------------*/
+  /* Configure I2Cx: Speed */
+  MODIFY_REG(hi2c->Instance->CCR, (I2C_CCR_FS | I2C_CCR_DUTY | I2C_CCR_CCR), I2C_SPEED(pclk1, hi2c->Init.ClockSpeed, hi2c->Init.DutyCycle));
+
+  /*---------------------------- I2Cx CR1 Configuration ----------------------*/
+  /* Configure I2Cx: Generalcall and NoStretch mode */
+  MODIFY_REG(hi2c->Instance->CR1, (I2C_CR1_ENGC | I2C_CR1_NOSTRETCH), (hi2c->Init.GeneralCallMode | hi2c->Init.NoStretchMode));
+
+  /*---------------------------- I2Cx OAR1 Configuration ---------------------*/
+  /* Configure I2Cx: Own Address1 and addressing mode */
+  MODIFY_REG(hi2c->Instance->OAR1, (I2C_OAR1_ADDMODE | I2C_OAR1_ADD8_9 | I2C_OAR1_ADD1_7 | I2C_OAR1_ADD0), (hi2c->Init.AddressingMode | hi2c->Init.OwnAddress1));
+
+  /*---------------------------- I2Cx OAR2 Configuration ---------------------*/
+  /* Configure I2Cx: Dual mode and Own Address2 */
+  MODIFY_REG(hi2c->Instance->OAR2, (I2C_OAR2_ENDUAL | I2C_OAR2_ADD2), (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2));
+
+  /* Enable the selected I2C peripheral */
+  __HAL_I2C_ENABLE(hi2c);
+
+  hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+  hi2c->State = HAL_I2C_STATE_READY;
+  hi2c->PreviousState = I2C_STATE_NONE;
+  hi2c->Mode = HAL_I2C_MODE_NONE;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  DeInitialize the I2C peripheral.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *         the configuration information for the specified I2C.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c)
+{
+  /* Check the I2C handle allocation */
+  if (hi2c == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
+
+  hi2c->State = HAL_I2C_STATE_BUSY;
+
+  /* Disable the I2C Peripheral Clock */
+  __HAL_I2C_DISABLE(hi2c);
+
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+  if (hi2c->MspDeInitCallback == NULL)
+  {
+    hi2c->MspDeInitCallback = HAL_I2C_MspDeInit; /* Legacy weak MspDeInit  */
+  }
+
+  /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
+  hi2c->MspDeInitCallback(hi2c);
+#else
+  /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
+  HAL_I2C_MspDeInit(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+
+  hi2c->ErrorCode     = HAL_I2C_ERROR_NONE;
+  hi2c->State         = HAL_I2C_STATE_RESET;
+  hi2c->PreviousState = I2C_STATE_NONE;
+  hi2c->Mode          = HAL_I2C_MODE_NONE;
+
+  /* Release Lock */
+  __HAL_UNLOCK(hi2c);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initialize the I2C MSP.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *         the configuration information for the specified I2C.
+  * @retval None
+  */
+__weak void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hi2c);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_I2C_MspInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  DeInitialize the I2C MSP.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *         the configuration information for the specified I2C.
+  * @retval None
+  */
+__weak void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hi2c);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_I2C_MspDeInit could be implemented in the user file
+   */
+}
+
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+/**
+  * @brief  Register a User I2C Callback
+  *         To be used instead of the weak predefined callback
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  CallbackID ID of the callback to be registered
+  *         This parameter can be one of the following values:
+  *          @arg @ref HAL_I2C_MASTER_TX_COMPLETE_CB_ID Master Tx Transfer completed callback ID
+  *          @arg @ref HAL_I2C_MASTER_RX_COMPLETE_CB_ID Master Rx Transfer completed callback ID
+  *          @arg @ref HAL_I2C_SLAVE_TX_COMPLETE_CB_ID Slave Tx Transfer completed callback ID
+  *          @arg @ref HAL_I2C_SLAVE_RX_COMPLETE_CB_ID Slave Rx Transfer completed callback ID
+  *          @arg @ref HAL_I2C_LISTEN_COMPLETE_CB_ID Listen Complete callback ID
+  *          @arg @ref HAL_I2C_MEM_TX_COMPLETE_CB_ID Memory Tx Transfer callback ID
+  *          @arg @ref HAL_I2C_MEM_RX_COMPLETE_CB_ID Memory Rx Transfer completed callback ID
+  *          @arg @ref HAL_I2C_ERROR_CB_ID Error callback ID
+  *          @arg @ref HAL_I2C_ABORT_CB_ID Abort callback ID
+  *          @arg @ref HAL_I2C_MSPINIT_CB_ID MspInit callback ID
+  *          @arg @ref HAL_I2C_MSPDEINIT_CB_ID MspDeInit callback ID
+  * @param  pCallback pointer to the Callback function
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_RegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID, pI2C_CallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    /* Update the error code */
+    hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
+
+    return HAL_ERROR;
+  }
+  /* Process locked */
+  __HAL_LOCK(hi2c);
+
+  if (HAL_I2C_STATE_READY == hi2c->State)
+  {
+    switch (CallbackID)
+    {
+      case HAL_I2C_MASTER_TX_COMPLETE_CB_ID :
+        hi2c->MasterTxCpltCallback = pCallback;
+        break;
+
+      case HAL_I2C_MASTER_RX_COMPLETE_CB_ID :
+        hi2c->MasterRxCpltCallback = pCallback;
+        break;
+
+      case HAL_I2C_SLAVE_TX_COMPLETE_CB_ID :
+        hi2c->SlaveTxCpltCallback = pCallback;
+        break;
+
+      case HAL_I2C_SLAVE_RX_COMPLETE_CB_ID :
+        hi2c->SlaveRxCpltCallback = pCallback;
+        break;
+
+      case HAL_I2C_LISTEN_COMPLETE_CB_ID :
+        hi2c->ListenCpltCallback = pCallback;
+        break;
+
+      case HAL_I2C_MEM_TX_COMPLETE_CB_ID :
+        hi2c->MemTxCpltCallback = pCallback;
+        break;
+
+      case HAL_I2C_MEM_RX_COMPLETE_CB_ID :
+        hi2c->MemRxCpltCallback = pCallback;
+        break;
+
+      case HAL_I2C_ERROR_CB_ID :
+        hi2c->ErrorCallback = pCallback;
+        break;
+
+      case HAL_I2C_ABORT_CB_ID :
+        hi2c->AbortCpltCallback = pCallback;
+        break;
+
+      case HAL_I2C_MSPINIT_CB_ID :
+        hi2c->MspInitCallback = pCallback;
+        break;
+
+      case HAL_I2C_MSPDEINIT_CB_ID :
+        hi2c->MspDeInitCallback = pCallback;
+        break;
+
+      default :
+        /* Update the error code */
+        hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
+
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else if (HAL_I2C_STATE_RESET == hi2c->State)
+  {
+    switch (CallbackID)
+    {
+      case HAL_I2C_MSPINIT_CB_ID :
+        hi2c->MspInitCallback = pCallback;
+        break;
+
+      case HAL_I2C_MSPDEINIT_CB_ID :
+        hi2c->MspDeInitCallback = pCallback;
+        break;
+
+      default :
+        /* Update the error code */
+        hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
+
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    /* Update the error code */
+    hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(hi2c);
+  return status;
+}
+
+/**
+  * @brief  Unregister an I2C Callback
+  *         I2C callback is redirected to the weak predefined callback
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  CallbackID ID of the callback to be unregistered
+  *         This parameter can be one of the following values:
+  *         This parameter can be one of the following values:
+  *          @arg @ref HAL_I2C_MASTER_TX_COMPLETE_CB_ID Master Tx Transfer completed callback ID
+  *          @arg @ref HAL_I2C_MASTER_RX_COMPLETE_CB_ID Master Rx Transfer completed callback ID
+  *          @arg @ref HAL_I2C_SLAVE_TX_COMPLETE_CB_ID Slave Tx Transfer completed callback ID
+  *          @arg @ref HAL_I2C_SLAVE_RX_COMPLETE_CB_ID Slave Rx Transfer completed callback ID
+  *          @arg @ref HAL_I2C_LISTEN_COMPLETE_CB_ID Listen Complete callback ID
+  *          @arg @ref HAL_I2C_MEM_TX_COMPLETE_CB_ID Memory Tx Transfer callback ID
+  *          @arg @ref HAL_I2C_MEM_RX_COMPLETE_CB_ID Memory Rx Transfer completed callback ID
+  *          @arg @ref HAL_I2C_ERROR_CB_ID Error callback ID
+  *          @arg @ref HAL_I2C_ABORT_CB_ID Abort callback ID
+  *          @arg @ref HAL_I2C_MSPINIT_CB_ID MspInit callback ID
+  *          @arg @ref HAL_I2C_MSPDEINIT_CB_ID MspDeInit callback ID
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_UnRegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Process locked */
+  __HAL_LOCK(hi2c);
+
+  if (HAL_I2C_STATE_READY == hi2c->State)
+  {
+    switch (CallbackID)
+    {
+      case HAL_I2C_MASTER_TX_COMPLETE_CB_ID :
+        hi2c->MasterTxCpltCallback = HAL_I2C_MasterTxCpltCallback; /* Legacy weak MasterTxCpltCallback */
+        break;
+
+      case HAL_I2C_MASTER_RX_COMPLETE_CB_ID :
+        hi2c->MasterRxCpltCallback = HAL_I2C_MasterRxCpltCallback; /* Legacy weak MasterRxCpltCallback */
+        break;
+
+      case HAL_I2C_SLAVE_TX_COMPLETE_CB_ID :
+        hi2c->SlaveTxCpltCallback = HAL_I2C_SlaveTxCpltCallback;   /* Legacy weak SlaveTxCpltCallback  */
+        break;
+
+      case HAL_I2C_SLAVE_RX_COMPLETE_CB_ID :
+        hi2c->SlaveRxCpltCallback = HAL_I2C_SlaveRxCpltCallback;   /* Legacy weak SlaveRxCpltCallback  */
+        break;
+
+      case HAL_I2C_LISTEN_COMPLETE_CB_ID :
+        hi2c->ListenCpltCallback = HAL_I2C_ListenCpltCallback;     /* Legacy weak ListenCpltCallback   */
+        break;
+
+      case HAL_I2C_MEM_TX_COMPLETE_CB_ID :
+        hi2c->MemTxCpltCallback = HAL_I2C_MemTxCpltCallback;       /* Legacy weak MemTxCpltCallback    */
+        break;
+
+      case HAL_I2C_MEM_RX_COMPLETE_CB_ID :
+        hi2c->MemRxCpltCallback = HAL_I2C_MemRxCpltCallback;       /* Legacy weak MemRxCpltCallback    */
+        break;
+
+      case HAL_I2C_ERROR_CB_ID :
+        hi2c->ErrorCallback = HAL_I2C_ErrorCallback;               /* Legacy weak ErrorCallback        */
+        break;
+
+      case HAL_I2C_ABORT_CB_ID :
+        hi2c->AbortCpltCallback = HAL_I2C_AbortCpltCallback;       /* Legacy weak AbortCpltCallback    */
+        break;
+
+      case HAL_I2C_MSPINIT_CB_ID :
+        hi2c->MspInitCallback = HAL_I2C_MspInit;                   /* Legacy weak MspInit              */
+        break;
+
+      case HAL_I2C_MSPDEINIT_CB_ID :
+        hi2c->MspDeInitCallback = HAL_I2C_MspDeInit;               /* Legacy weak MspDeInit            */
+        break;
+
+      default :
+        /* Update the error code */
+        hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
+
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else if (HAL_I2C_STATE_RESET == hi2c->State)
+  {
+    switch (CallbackID)
+    {
+      case HAL_I2C_MSPINIT_CB_ID :
+        hi2c->MspInitCallback = HAL_I2C_MspInit;                   /* Legacy weak MspInit              */
+        break;
+
+      case HAL_I2C_MSPDEINIT_CB_ID :
+        hi2c->MspDeInitCallback = HAL_I2C_MspDeInit;               /* Legacy weak MspDeInit            */
+        break;
+
+      default :
+        /* Update the error code */
+        hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
+
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    /* Update the error code */
+    hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(hi2c);
+  return status;
+}
+
+/**
+  * @brief  Register the Slave Address Match I2C Callback
+  *         To be used instead of the weak HAL_I2C_AddrCallback() predefined callback
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  pCallback pointer to the Address Match Callback function
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_RegisterAddrCallback(I2C_HandleTypeDef *hi2c, pI2C_AddrCallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    /* Update the error code */
+    hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
+
+    return HAL_ERROR;
+  }
+  /* Process locked */
+  __HAL_LOCK(hi2c);
+
+  if (HAL_I2C_STATE_READY == hi2c->State)
+  {
+    hi2c->AddrCallback = pCallback;
+  }
+  else
+  {
+    /* Update the error code */
+    hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(hi2c);
+  return status;
+}
+
+/**
+  * @brief  UnRegister the Slave Address Match I2C Callback
+  *         Info Ready I2C Callback is redirected to the weak HAL_I2C_AddrCallback() predefined callback
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef *hi2c)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Process locked */
+  __HAL_LOCK(hi2c);
+
+  if (HAL_I2C_STATE_READY == hi2c->State)
+  {
+    hi2c->AddrCallback = HAL_I2C_AddrCallback; /* Legacy weak AddrCallback  */
+  }
+  else
+  {
+    /* Update the error code */
+    hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(hi2c);
+  return status;
+}
+
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+
+/** @defgroup I2C_Exported_Functions_Group2 Input and Output operation functions
+ *  @brief   Data transfers functions
+ *
+@verbatim
+ ===============================================================================
+                      ##### IO operation functions #####
+ ===============================================================================
+    [..]
+    This subsection provides a set of functions allowing to manage the I2C data
+    transfers.
+
+    (#) There are two modes of transfer:
+       (++) Blocking mode : The communication is performed in the polling mode.
+            The status of all data processing is returned by the same function
+            after finishing transfer.
+       (++) No-Blocking mode : The communication is performed using Interrupts
+            or DMA. These functions return the status of the transfer startup.
+            The end of the data processing will be indicated through the
+            dedicated I2C IRQ when using Interrupt mode or the DMA IRQ when
+            using DMA mode.
+
+    (#) Blocking mode functions are :
+        (++) HAL_I2C_Master_Transmit()
+        (++) HAL_I2C_Master_Receive()
+        (++) HAL_I2C_Slave_Transmit()
+        (++) HAL_I2C_Slave_Receive()
+        (++) HAL_I2C_Mem_Write()
+        (++) HAL_I2C_Mem_Read()
+        (++) HAL_I2C_IsDeviceReady()
+
+    (#) No-Blocking mode functions with Interrupt are :
+        (++) HAL_I2C_Master_Transmit_IT()
+        (++) HAL_I2C_Master_Receive_IT()
+        (++) HAL_I2C_Slave_Transmit_IT()
+        (++) HAL_I2C_Slave_Receive_IT()
+        (++) HAL_I2C_Mem_Write_IT()
+        (++) HAL_I2C_Mem_Read_IT()
+        (++) HAL_I2C_Master_Seq_Transmit_IT()
+        (++) HAL_I2C_Master_Seq_Receive_IT()
+        (++) HAL_I2C_Slave_Seq_Transmit_IT()
+        (++) HAL_I2C_Slave_Seq_Receive_IT()
+        (++) HAL_I2C_EnableListen_IT()
+        (++) HAL_I2C_DisableListen_IT()
+        (++) HAL_I2C_Master_Abort_IT()
+
+    (#) No-Blocking mode functions with DMA are :
+        (++) HAL_I2C_Master_Transmit_DMA()
+        (++) HAL_I2C_Master_Receive_DMA()
+        (++) HAL_I2C_Slave_Transmit_DMA()
+        (++) HAL_I2C_Slave_Receive_DMA()
+        (++) HAL_I2C_Mem_Write_DMA()
+        (++) HAL_I2C_Mem_Read_DMA()
+        (++) HAL_I2C_Master_Seq_Transmit_DMA()
+        (++) HAL_I2C_Master_Seq_Receive_DMA()
+        (++) HAL_I2C_Slave_Seq_Transmit_DMA()
+        (++) HAL_I2C_Slave_Seq_Receive_DMA()
+
+    (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
+        (++) HAL_I2C_MasterTxCpltCallback()
+        (++) HAL_I2C_MasterRxCpltCallback()
+        (++) HAL_I2C_SlaveTxCpltCallback()
+        (++) HAL_I2C_SlaveRxCpltCallback()
+        (++) HAL_I2C_MemTxCpltCallback()
+        (++) HAL_I2C_MemRxCpltCallback()
+        (++) HAL_I2C_AddrCallback()
+        (++) HAL_I2C_ListenCpltCallback()
+        (++) HAL_I2C_ErrorCallback()
+        (++) HAL_I2C_AbortCpltCallback()
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Transmits in master mode an amount of data in blocking mode.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shifted to the left before calling the interface
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @param  Timeout Timeout duration
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+  /* Init tickstart for timeout management*/
+  uint32_t tickstart = HAL_GetTick();
+
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    /* Wait until BUSY flag is reset */
+    if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK)
+    {
+      return HAL_BUSY;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    /* Check if the I2C is already enabled */
+    if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
+    {
+      /* Enable I2C peripheral */
+      __HAL_I2C_ENABLE(hi2c);
+    }
+
+    /* Disable Pos */
+    CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
+
+    hi2c->State       = HAL_I2C_STATE_BUSY_TX;
+    hi2c->Mode        = HAL_I2C_MODE_MASTER;
+    hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr    = pData;
+    hi2c->XferCount   = Size;
+    hi2c->XferSize    = hi2c->XferCount;
+    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+
+    /* Send Slave Address */
+    if (I2C_MasterRequestWrite(hi2c, DevAddress, Timeout, tickstart) != HAL_OK)
+    {
+      return HAL_ERROR;
+    }
+
+    /* Clear ADDR flag */
+    __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
+
+    while (hi2c->XferSize > 0U)
+    {
+      /* Wait until TXE flag is set */
+      if (I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+      {
+        if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+        {
+          /* Generate Stop */
+          SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
+        }
+        return HAL_ERROR;
+      }
+
+      /* Write data to DR */
+      hi2c->Instance->DR = *hi2c->pBuffPtr;
+
+      /* Increment Buffer pointer */
+      hi2c->pBuffPtr++;
+
+      /* Update counter */
+      hi2c->XferCount--;
+      hi2c->XferSize--;
+
+      if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (hi2c->XferSize != 0U))
+      {
+        /* Write data to DR */
+        hi2c->Instance->DR = *hi2c->pBuffPtr;
+
+        /* Increment Buffer pointer */
+        hi2c->pBuffPtr++;
+
+        /* Update counter */
+        hi2c->XferCount--;
+        hi2c->XferSize--;
+      }
+
+      /* Wait until BTF flag is set */
+      if (I2C_WaitOnBTFFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+      {
+        if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+        {
+          /* Generate Stop */
+          SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
+        }
+        return HAL_ERROR;
+      }
+    }
+
+    /* Generate Stop */
+    SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
+
+    hi2c->State = HAL_I2C_STATE_READY;
+    hi2c->Mode = HAL_I2C_MODE_NONE;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Receives in master mode an amount of data in blocking mode.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shifted to the left before calling the interface
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @param  Timeout Timeout duration
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+  /* Init tickstart for timeout management*/
+  uint32_t tickstart = HAL_GetTick();
+
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    /* Wait until BUSY flag is reset */
+    if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK)
+    {
+      return HAL_BUSY;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    /* Check if the I2C is already enabled */
+    if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
+    {
+      /* Enable I2C peripheral */
+      __HAL_I2C_ENABLE(hi2c);
+    }
+
+    /* Disable Pos */
+    CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
+
+    hi2c->State       = HAL_I2C_STATE_BUSY_RX;
+    hi2c->Mode        = HAL_I2C_MODE_MASTER;
+    hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr    = pData;
+    hi2c->XferCount   = Size;
+    hi2c->XferSize    = hi2c->XferCount;
+    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+
+    /* Send Slave Address */
+    if (I2C_MasterRequestRead(hi2c, DevAddress, Timeout, tickstart) != HAL_OK)
+    {
+      return HAL_ERROR;
+    }
+
+    if (hi2c->XferSize == 0U)
+    {
+      /* Clear ADDR flag */
+      __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
+
+      /* Generate Stop */
+      SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
+    }
+    else if (hi2c->XferSize == 1U)
+    {
+      /* Disable Acknowledge */
+      CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
+
+      /* Clear ADDR flag */
+      __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
+
+      /* Generate Stop */
+      SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
+    }
+    else if (hi2c->XferSize == 2U)
+    {
+      /* Disable Acknowledge */
+      CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
+
+      /* Enable Pos */
+      SET_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
+
+      /* Clear ADDR flag */
+      __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
+    }
+    else
+    {
+      /* Enable Acknowledge */
+      SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
+
+      /* Clear ADDR flag */
+      __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
+    }
+
+    while (hi2c->XferSize > 0U)
+    {
+      if (hi2c->XferSize <= 3U)
+      {
+        /* One byte */
+        if (hi2c->XferSize == 1U)
+        {
+          /* Wait until RXNE flag is set */
+          if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+          {
+            return HAL_ERROR;
+          }
+
+          /* Read data from DR */
+          *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
+
+          /* Increment Buffer pointer */
+          hi2c->pBuffPtr++;
+
+          /* Update counter */
+          hi2c->XferSize--;
+          hi2c->XferCount--;
+        }
+        /* Two bytes */
+        else if (hi2c->XferSize == 2U)
+        {
+          /* Wait until BTF flag is set */
+          if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK)
+          {
+            return HAL_ERROR;
+          }
+
+          /* Generate Stop */
+          SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
+
+          /* Read data from DR */
+          *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
+
+          /* Increment Buffer pointer */
+          hi2c->pBuffPtr++;
+
+          /* Update counter */
+          hi2c->XferSize--;
+          hi2c->XferCount--;
+
+          /* Read data from DR */
+          *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
+
+          /* Increment Buffer pointer */
+          hi2c->pBuffPtr++;
+
+          /* Update counter */
+          hi2c->XferSize--;
+          hi2c->XferCount--;
+        }
+        /* 3 Last bytes */
+        else
+        {
+          /* Wait until BTF flag is set */
+          if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK)
+          {
+            return HAL_ERROR;
+          }
+
+          /* Disable Acknowledge */
+          CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
+
+          /* Read data from DR */
+          *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
+
+          /* Increment Buffer pointer */
+          hi2c->pBuffPtr++;
+
+          /* Update counter */
+          hi2c->XferSize--;
+          hi2c->XferCount--;
+
+          /* Wait until BTF flag is set */
+          if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK)
+          {
+            return HAL_ERROR;
+          }
+
+          /* Generate Stop */
+          SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
+
+          /* Read data from DR */
+          *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
+
+          /* Increment Buffer pointer */
+          hi2c->pBuffPtr++;
+
+          /* Update counter */
+          hi2c->XferSize--;
+          hi2c->XferCount--;
+
+          /* Read data from DR */
+          *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
+
+          /* Increment Buffer pointer */
+          hi2c->pBuffPtr++;
+
+          /* Update counter */
+          hi2c->XferSize--;
+          hi2c->XferCount--;
+        }
+      }
+      else
+      {
+        /* Wait until RXNE flag is set */
+        if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+        {
+          return HAL_ERROR;
+        }
+
+        /* Read data from DR */
+        *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
+
+        /* Increment Buffer pointer */
+        hi2c->pBuffPtr++;
+
+        /* Update counter */
+        hi2c->XferSize--;
+        hi2c->XferCount--;
+
+        if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET)
+        {
+          /* Read data from DR */
+          *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
+
+          /* Increment Buffer pointer */
+          hi2c->pBuffPtr++;
+
+          /* Update counter */
+          hi2c->XferSize--;
+          hi2c->XferCount--;
+        }
+      }
+    }
+
+    hi2c->State = HAL_I2C_STATE_READY;
+    hi2c->Mode = HAL_I2C_MODE_NONE;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Transmits in slave mode an amount of data in blocking mode.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @param  Timeout Timeout duration
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+  /* Init tickstart for timeout management*/
+  uint32_t tickstart = HAL_GetTick();
+
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    if ((pData == NULL) || (Size == 0U))
+    {
+      return  HAL_ERROR;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    /* Check if the I2C is already enabled */
+    if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
+    {
+      /* Enable I2C peripheral */
+      __HAL_I2C_ENABLE(hi2c);
+    }
+
+    /* Disable Pos */
+    CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
+
+    hi2c->State       = HAL_I2C_STATE_BUSY_TX;
+    hi2c->Mode        = HAL_I2C_MODE_SLAVE;
+    hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr    = pData;
+    hi2c->XferCount   = Size;
+    hi2c->XferSize    = hi2c->XferCount;
+    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+
+    /* Enable Address Acknowledge */
+    SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
+
+    /* Wait until ADDR flag is set */
+    if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
+    {
+      return HAL_ERROR;
+    }
+
+    /* Clear ADDR flag */
+    __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
+
+    /* If 10bit addressing mode is selected */
+    if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
+    {
+      /* Wait until ADDR flag is set */
+      if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
+
+      /* Clear ADDR flag */
+      __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
+    }
+
+    while (hi2c->XferSize > 0U)
+    {
+      /* Wait until TXE flag is set */
+      if (I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+      {
+        /* Disable Address Acknowledge */
+        CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
+
+        return HAL_ERROR;
+      }
+
+      /* Write data to DR */
+      hi2c->Instance->DR = *hi2c->pBuffPtr;
+
+      /* Increment Buffer pointer */
+      hi2c->pBuffPtr++;
+
+      /* Update counter */
+      hi2c->XferCount--;
+      hi2c->XferSize--;
+
+      if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (hi2c->XferSize != 0U))
+      {
+        /* Write data to DR */
+        hi2c->Instance->DR = *hi2c->pBuffPtr;
+
+        /* Increment Buffer pointer */
+        hi2c->pBuffPtr++;
+
+        /* Update counter */
+        hi2c->XferCount--;
+        hi2c->XferSize--;
+      }
+    }
+
+    /* Wait until AF flag is set */
+    if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_AF, RESET, Timeout, tickstart) != HAL_OK)
+    {
+      return HAL_ERROR;
+    }
+
+    /* Clear AF flag */
+    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+
+    /* Disable Address Acknowledge */
+    CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
+
+    hi2c->State = HAL_I2C_STATE_READY;
+    hi2c->Mode = HAL_I2C_MODE_NONE;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Receive in slave mode an amount of data in blocking mode
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *         the configuration information for the specified I2C.
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @param  Timeout Timeout duration
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+  /* Init tickstart for timeout management*/
+  uint32_t tickstart = HAL_GetTick();
+
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    if ((pData == NULL) || (Size == (uint16_t)0))
+    {
+      return HAL_ERROR;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    /* Check if the I2C is already enabled */
+    if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
+    {
+      /* Enable I2C peripheral */
+      __HAL_I2C_ENABLE(hi2c);
+    }
+
+    /* Disable Pos */
+    CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
+
+    hi2c->State       = HAL_I2C_STATE_BUSY_RX;
+    hi2c->Mode        = HAL_I2C_MODE_SLAVE;
+    hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr    = pData;
+    hi2c->XferCount   = Size;
+    hi2c->XferSize    = hi2c->XferCount;
+    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+
+    /* Enable Address Acknowledge */
+    SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
+
+    /* Wait until ADDR flag is set */
+    if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
+    {
+      return HAL_ERROR;
+    }
+
+    /* Clear ADDR flag */
+    __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
+
+    while (hi2c->XferSize > 0U)
+    {
+      /* Wait until RXNE flag is set */
+      if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+      {
+        /* Disable Address Acknowledge */
+        CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
+
+        return HAL_ERROR;
+      }
+
+      /* Read data from DR */
+      *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
+
+      /* Increment Buffer pointer */
+      hi2c->pBuffPtr++;
+
+      /* Update counter */
+      hi2c->XferSize--;
+      hi2c->XferCount--;
+
+      if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (hi2c->XferSize != 0U))
+      {
+        /* Read data from DR */
+        *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
+
+        /* Increment Buffer pointer */
+        hi2c->pBuffPtr++;
+
+        /* Update counter */
+        hi2c->XferSize--;
+        hi2c->XferCount--;
+      }
+    }
+
+    /* Wait until STOP flag is set */
+    if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+    {
+      /* Disable Address Acknowledge */
+      CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
+
+      return HAL_ERROR;
+    }
+
+    /* Clear STOP flag */
+    __HAL_I2C_CLEAR_STOPFLAG(hi2c);
+
+    /* Disable Address Acknowledge */
+    CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
+
+    hi2c->State = HAL_I2C_STATE_READY;
+    hi2c->Mode = HAL_I2C_MODE_NONE;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Transmit in master mode an amount of data in non-blocking mode with Interrupt
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shifted to the left before calling the interface
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
+{
+  __IO uint32_t count = 0U;
+
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    /* Wait until BUSY flag is reset */
+    count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U);
+    do
+    {
+      count--;
+      if (count == 0U)
+      {
+        hi2c->PreviousState       = I2C_STATE_NONE;
+        hi2c->State               = HAL_I2C_STATE_READY;
+        hi2c->Mode                = HAL_I2C_MODE_NONE;
+        hi2c->ErrorCode           |= HAL_I2C_ERROR_TIMEOUT;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+
+        return HAL_ERROR;
+      }
+    }
+    while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
+
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    /* Check if the I2C is already enabled */
+    if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
+    {
+      /* Enable I2C peripheral */
+      __HAL_I2C_ENABLE(hi2c);
+    }
+
+    /* Disable Pos */
+    CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
+
+    hi2c->State     = HAL_I2C_STATE_BUSY_TX;
+    hi2c->Mode      = HAL_I2C_MODE_MASTER;
+    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr    = pData;
+    hi2c->XferCount   = Size;
+    hi2c->XferSize    = hi2c->XferCount;
+    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+    hi2c->Devaddress  = DevAddress;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    /* Note : The I2C interrupts must be enabled after unlocking current process
+              to avoid the risk of I2C interrupt handle execution before current
+              process unlock */
+    /* Enable EVT, BUF and ERR interrupt */
+    __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
+
+    /* Generate Start */
+    SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Receive in master mode an amount of data in non-blocking mode with Interrupt
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shifted to the left before calling the interface
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
+{
+  __IO uint32_t count = 0U;
+
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    /* Wait until BUSY flag is reset */
+    count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U);
+    do
+    {
+      count--;
+      if (count == 0U)
+      {
+        hi2c->PreviousState       = I2C_STATE_NONE;
+        hi2c->State               = HAL_I2C_STATE_READY;
+        hi2c->Mode                = HAL_I2C_MODE_NONE;
+        hi2c->ErrorCode           |= HAL_I2C_ERROR_TIMEOUT;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+
+        return HAL_ERROR;
+      }
+    }
+    while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
+
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    /* Check if the I2C is already enabled */
+    if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
+    {
+      /* Enable I2C peripheral */
+      __HAL_I2C_ENABLE(hi2c);
+    }
+
+    /* Disable Pos */
+    CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
+
+    hi2c->State     = HAL_I2C_STATE_BUSY_RX;
+    hi2c->Mode      = HAL_I2C_MODE_MASTER;
+    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr    = pData;
+    hi2c->XferCount   = Size;
+    hi2c->XferSize    = hi2c->XferCount;
+    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+    hi2c->Devaddress  = DevAddress;
+
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    /* Note : The I2C interrupts must be enabled after unlocking current process
+    to avoid the risk of I2C interrupt handle execution before current
+    process unlock */
+
+    /* Enable EVT, BUF and ERR interrupt */
+    __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
+
+    /* Enable Acknowledge */
+    SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
+
+    /* Generate Start */
+    SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Transmit in slave mode an amount of data in non-blocking mode with Interrupt
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *         the configuration information for the specified I2C.
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
+{
+
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    if ((pData == NULL) || (Size == 0U))
+    {
+      return  HAL_ERROR;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    /* Check if the I2C is already enabled */
+    if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
+    {
+      /* Enable I2C peripheral */
+      __HAL_I2C_ENABLE(hi2c);
+    }
+
+    /* Disable Pos */
+    CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
+
+    hi2c->State     = HAL_I2C_STATE_BUSY_TX;
+    hi2c->Mode      = HAL_I2C_MODE_SLAVE;
+    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr    = pData;
+    hi2c->XferCount   = Size;
+    hi2c->XferSize    = hi2c->XferCount;
+    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+
+    /* Enable Address Acknowledge */
+    SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    /* Note : The I2C interrupts must be enabled after unlocking current process
+              to avoid the risk of I2C interrupt handle execution before current
+              process unlock */
+
+    /* Enable EVT, BUF and ERR interrupt */
+    __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Receive in slave mode an amount of data in non-blocking mode with Interrupt
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
+{
+
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    if ((pData == NULL) || (Size == 0U))
+    {
+      return  HAL_ERROR;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    /* Check if the I2C is already enabled */
+    if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
+    {
+      /* Enable I2C peripheral */
+      __HAL_I2C_ENABLE(hi2c);
+    }
+
+    /* Disable Pos */
+    CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
+
+    hi2c->State     = HAL_I2C_STATE_BUSY_RX;
+    hi2c->Mode      = HAL_I2C_MODE_SLAVE;
+    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr    = pData;
+    hi2c->XferCount   = Size;
+    hi2c->XferSize    = hi2c->XferCount;
+    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+
+    /* Enable Address Acknowledge */
+    SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    /* Note : The I2C interrupts must be enabled after unlocking current process
+              to avoid the risk of I2C interrupt handle execution before current
+              process unlock */
+
+    /* Enable EVT, BUF and ERR interrupt */
+    __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Transmit in master mode an amount of data in non-blocking mode with DMA
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shifted to the left before calling the interface
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
+{
+  __IO uint32_t count = 0U;
+  HAL_StatusTypeDef dmaxferstatus;
+
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    /* Wait until BUSY flag is reset */
+    count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U);
+    do
+    {
+      count--;
+      if (count == 0U)
+      {
+        hi2c->PreviousState       = I2C_STATE_NONE;
+        hi2c->State               = HAL_I2C_STATE_READY;
+        hi2c->Mode                = HAL_I2C_MODE_NONE;
+        hi2c->ErrorCode           |= HAL_I2C_ERROR_TIMEOUT;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+
+        return HAL_ERROR;
+      }
+    }
+    while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
+
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    /* Check if the I2C is already enabled */
+    if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
+    {
+      /* Enable I2C peripheral */
+      __HAL_I2C_ENABLE(hi2c);
+    }
+
+    /* Disable Pos */
+    CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
+
+    hi2c->State     = HAL_I2C_STATE_BUSY_TX;
+    hi2c->Mode      = HAL_I2C_MODE_MASTER;
+    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr    = pData;
+    hi2c->XferCount   = Size;
+    hi2c->XferSize    = hi2c->XferCount;
+    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+    hi2c->Devaddress  = DevAddress;
+
+    if (hi2c->XferSize > 0U)
+    {
+      if (hi2c->hdmatx != NULL)
+      {
+        /* Set the I2C DMA transfer complete callback */
+        hi2c->hdmatx->XferCpltCallback = I2C_DMAXferCplt;
+
+        /* Set the DMA error callback */
+        hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
+
+        /* Set the unused DMA callbacks to NULL */
+        hi2c->hdmatx->XferHalfCpltCallback = NULL;
+        hi2c->hdmatx->XferM1CpltCallback = NULL;
+        hi2c->hdmatx->XferM1HalfCpltCallback = NULL;
+        hi2c->hdmatx->XferAbortCallback = NULL;
+
+        /* Enable the DMA stream */
+        dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->DR, hi2c->XferSize);
+      }
+      else
+      {
+        /* Update I2C state */
+        hi2c->State     = HAL_I2C_STATE_READY;
+        hi2c->Mode      = HAL_I2C_MODE_NONE;
+
+        /* Update I2C error code */
+        hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+
+        return HAL_ERROR;
+      }
+
+      if (dmaxferstatus == HAL_OK)
+      {
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+
+        /* Note : The I2C interrupts must be enabled after unlocking current process
+        to avoid the risk of I2C interrupt handle execution before current
+        process unlock */
+
+        /* Enable EVT and ERR interrupt */
+        __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
+
+        /* Enable DMA Request */
+        SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
+
+        /* Enable Acknowledge */
+        SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
+
+        /* Generate Start */
+        SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
+      }
+      else
+      {
+        /* Update I2C state */
+        hi2c->State     = HAL_I2C_STATE_READY;
+        hi2c->Mode      = HAL_I2C_MODE_NONE;
+
+        /* Update I2C error code */
+        hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+
+        return HAL_ERROR;
+      }
+    }
+    else
+    {
+      /* Enable Acknowledge */
+      SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
+
+      /* Generate Start */
+      SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      /* Note : The I2C interrupts must be enabled after unlocking current process
+      to avoid the risk of I2C interrupt handle execution before current
+      process unlock */
+
+      /* Enable EVT, BUF and ERR interrupt */
+      __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
+    }
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Receive in master mode an amount of data in non-blocking mode with DMA
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shifted to the left before calling the interface
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
+{
+  __IO uint32_t count = 0U;
+  HAL_StatusTypeDef dmaxferstatus;
+
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    /* Wait until BUSY flag is reset */
+    count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U);
+    do
+    {
+      count--;
+      if (count == 0U)
+      {
+        hi2c->PreviousState       = I2C_STATE_NONE;
+        hi2c->State               = HAL_I2C_STATE_READY;
+        hi2c->Mode                = HAL_I2C_MODE_NONE;
+        hi2c->ErrorCode           |= HAL_I2C_ERROR_TIMEOUT;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+
+        return HAL_ERROR;
+      }
+    }
+    while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
+
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    /* Check if the I2C is already enabled */
+    if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
+    {
+      /* Enable I2C peripheral */
+      __HAL_I2C_ENABLE(hi2c);
+    }
+
+    /* Disable Pos */
+    CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
+
+    hi2c->State     = HAL_I2C_STATE_BUSY_RX;
+    hi2c->Mode      = HAL_I2C_MODE_MASTER;
+    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr    = pData;
+    hi2c->XferCount   = Size;
+    hi2c->XferSize    = hi2c->XferCount;
+    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+    hi2c->Devaddress  = DevAddress;
+
+    if (hi2c->XferSize > 0U)
+    {
+      if (hi2c->hdmarx != NULL)
+      {
+        /* Set the I2C DMA transfer complete callback */
+        hi2c->hdmarx->XferCpltCallback = I2C_DMAXferCplt;
+
+        /* Set the DMA error callback */
+        hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
+
+        /* Set the unused DMA callbacks to NULL */
+        hi2c->hdmarx->XferHalfCpltCallback = NULL;
+        hi2c->hdmarx->XferM1CpltCallback = NULL;
+        hi2c->hdmarx->XferM1HalfCpltCallback = NULL;
+        hi2c->hdmarx->XferAbortCallback = NULL;
+
+        /* Enable the DMA stream */
+        dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize);
+      }
+      else
+      {
+        /* Update I2C state */
+        hi2c->State     = HAL_I2C_STATE_READY;
+        hi2c->Mode      = HAL_I2C_MODE_NONE;
+
+        /* Update I2C error code */
+        hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+
+        return HAL_ERROR;
+      }
+
+      if (dmaxferstatus == HAL_OK)
+      {
+        /* Enable Acknowledge */
+        SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
+
+        /* Generate Start */
+        SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+
+        /* Note : The I2C interrupts must be enabled after unlocking current process
+        to avoid the risk of I2C interrupt handle execution before current
+        process unlock */
+
+        /* Enable EVT and ERR interrupt */
+        __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
+
+        /* Enable DMA Request */
+        SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
+      }
+      else
+      {
+        /* Update I2C state */
+        hi2c->State     = HAL_I2C_STATE_READY;
+        hi2c->Mode      = HAL_I2C_MODE_NONE;
+
+        /* Update I2C error code */
+        hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+
+        return HAL_ERROR;
+      }
+    }
+    else
+    {
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      /* Note : The I2C interrupts must be enabled after unlocking current process
+      to avoid the risk of I2C interrupt handle execution before current
+      process unlock */
+
+      /* Enable EVT, BUF and ERR interrupt */
+      __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
+
+      /* Enable Acknowledge */
+      SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
+
+      /* Generate Start */
+      SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
+    }
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Transmit in slave mode an amount of data in non-blocking mode with DMA
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
+{
+  HAL_StatusTypeDef dmaxferstatus;
+
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    if ((pData == NULL) || (Size == 0U))
+    {
+      return  HAL_ERROR;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    /* Check if the I2C is already enabled */
+    if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
+    {
+      /* Enable I2C peripheral */
+      __HAL_I2C_ENABLE(hi2c);
+    }
+
+    /* Disable Pos */
+    CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
+
+    hi2c->State     = HAL_I2C_STATE_BUSY_TX;
+    hi2c->Mode      = HAL_I2C_MODE_SLAVE;
+    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr    = pData;
+    hi2c->XferCount   = Size;
+    hi2c->XferSize    = hi2c->XferCount;
+    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+
+    if (hi2c->hdmatx != NULL)
+    {
+      /* Set the I2C DMA transfer complete callback */
+      hi2c->hdmatx->XferCpltCallback = I2C_DMAXferCplt;
+
+      /* Set the DMA error callback */
+      hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
+
+      /* Set the unused DMA callbacks to NULL */
+      hi2c->hdmatx->XferHalfCpltCallback = NULL;
+      hi2c->hdmatx->XferM1CpltCallback = NULL;
+      hi2c->hdmatx->XferM1HalfCpltCallback = NULL;
+      hi2c->hdmatx->XferAbortCallback = NULL;
+
+      /* Enable the DMA stream */
+      dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->DR, hi2c->XferSize);
+    }
+    else
+    {
+      /* Update I2C state */
+      hi2c->State     = HAL_I2C_STATE_LISTEN;
+      hi2c->Mode      = HAL_I2C_MODE_NONE;
+
+      /* Update I2C error code */
+      hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      return HAL_ERROR;
+    }
+
+    if (dmaxferstatus == HAL_OK)
+    {
+      /* Enable Address Acknowledge */
+      SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      /* Note : The I2C interrupts must be enabled after unlocking current process
+      to avoid the risk of I2C interrupt handle execution before current
+      process unlock */
+      /* Enable EVT and ERR interrupt */
+      __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
+
+      /* Enable DMA Request */
+      hi2c->Instance->CR2 |= I2C_CR2_DMAEN;
+
+      return HAL_OK;
+    }
+    else
+    {
+      /* Update I2C state */
+      hi2c->State     = HAL_I2C_STATE_READY;
+      hi2c->Mode      = HAL_I2C_MODE_NONE;
+
+      /* Update I2C error code */
+      hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      return HAL_ERROR;
+    }
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Receive in slave mode an amount of data in non-blocking mode with DMA
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
+{
+  HAL_StatusTypeDef dmaxferstatus;
+
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    if ((pData == NULL) || (Size == 0U))
+    {
+      return  HAL_ERROR;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    /* Check if the I2C is already enabled */
+    if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
+    {
+      /* Enable I2C peripheral */
+      __HAL_I2C_ENABLE(hi2c);
+    }
+
+    /* Disable Pos */
+    CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
+
+    hi2c->State     = HAL_I2C_STATE_BUSY_RX;
+    hi2c->Mode      = HAL_I2C_MODE_SLAVE;
+    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr    = pData;
+    hi2c->XferCount   = Size;
+    hi2c->XferSize    = hi2c->XferCount;
+    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+
+    if (hi2c->hdmarx != NULL)
+    {
+      /* Set the I2C DMA transfer complete callback */
+      hi2c->hdmarx->XferCpltCallback = I2C_DMAXferCplt;
+
+      /* Set the DMA error callback */
+      hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
+
+      /* Set the unused DMA callbacks to NULL */
+      hi2c->hdmarx->XferHalfCpltCallback = NULL;
+      hi2c->hdmarx->XferM1CpltCallback = NULL;
+      hi2c->hdmarx->XferM1HalfCpltCallback = NULL;
+      hi2c->hdmarx->XferAbortCallback = NULL;
+
+      /* Enable the DMA stream */
+      dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize);
+    }
+    else
+    {
+      /* Update I2C state */
+      hi2c->State     = HAL_I2C_STATE_LISTEN;
+      hi2c->Mode      = HAL_I2C_MODE_NONE;
+
+      /* Update I2C error code */
+      hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      return HAL_ERROR;
+    }
+
+    if (dmaxferstatus == HAL_OK)
+    {
+      /* Enable Address Acknowledge */
+      SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      /* Note : The I2C interrupts must be enabled after unlocking current process
+      to avoid the risk of I2C interrupt handle execution before current
+      process unlock */
+      /* Enable EVT and ERR interrupt */
+      __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
+
+      /* Enable DMA Request */
+      SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
+
+      return HAL_OK;
+    }
+    else
+    {
+      /* Update I2C state */
+      hi2c->State     = HAL_I2C_STATE_READY;
+      hi2c->Mode      = HAL_I2C_MODE_NONE;
+
+      /* Update I2C error code */
+      hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      return HAL_ERROR;
+    }
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Write an amount of data in blocking mode to a specific memory address
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shifted to the left before calling the interface
+  * @param  MemAddress Internal memory address
+  * @param  MemAddSize Size of internal memory address
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @param  Timeout Timeout duration
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+  /* Init tickstart for timeout management*/
+  uint32_t tickstart = HAL_GetTick();
+
+  /* Check the parameters */
+  assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
+
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    /* Wait until BUSY flag is reset */
+    if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK)
+    {
+      return HAL_BUSY;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    /* Check if the I2C is already enabled */
+    if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
+    {
+      /* Enable I2C peripheral */
+      __HAL_I2C_ENABLE(hi2c);
+    }
+
+    /* Disable Pos */
+    CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
+
+    hi2c->State     = HAL_I2C_STATE_BUSY_TX;
+    hi2c->Mode      = HAL_I2C_MODE_MEM;
+    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr    = pData;
+    hi2c->XferCount   = Size;
+    hi2c->XferSize    = hi2c->XferCount;
+    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+
+    /* Send Slave Address and Memory Address */
+    if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK)
+    {
+      return HAL_ERROR;
+    }
+
+    while (hi2c->XferSize > 0U)
+    {
+      /* Wait until TXE flag is set */
+      if (I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+      {
+        if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+        {
+          /* Generate Stop */
+          SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
+        }
+        return HAL_ERROR;
+      }
+
+      /* Write data to DR */
+      hi2c->Instance->DR = *hi2c->pBuffPtr;
+
+      /* Increment Buffer pointer */
+      hi2c->pBuffPtr++;
+
+      /* Update counter */
+      hi2c->XferSize--;
+      hi2c->XferCount--;
+
+      if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (hi2c->XferSize != 0U))
+      {
+        /* Write data to DR */
+        hi2c->Instance->DR = *hi2c->pBuffPtr;
+
+        /* Increment Buffer pointer */
+        hi2c->pBuffPtr++;
+
+        /* Update counter */
+        hi2c->XferSize--;
+        hi2c->XferCount--;
+      }
+    }
+
+    /* Wait until BTF flag is set */
+    if (I2C_WaitOnBTFFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+    {
+      if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+      {
+        /* Generate Stop */
+        SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
+      }
+      return HAL_ERROR;
+    }
+
+    /* Generate Stop */
+    SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
+
+    hi2c->State = HAL_I2C_STATE_READY;
+    hi2c->Mode = HAL_I2C_MODE_NONE;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Read an amount of data in blocking mode from a specific memory address
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shifted to the left before calling the interface
+  * @param  MemAddress Internal memory address
+  * @param  MemAddSize Size of internal memory address
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @param  Timeout Timeout duration
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+  /* Init tickstart for timeout management*/
+  uint32_t tickstart = HAL_GetTick();
+
+  /* Check the parameters */
+  assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
+
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    /* Wait until BUSY flag is reset */
+    if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK)
+    {
+      return HAL_BUSY;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    /* Check if the I2C is already enabled */
+    if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
+    {
+      /* Enable I2C peripheral */
+      __HAL_I2C_ENABLE(hi2c);
+    }
+
+    /* Disable Pos */
+    CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
+
+    hi2c->State     = HAL_I2C_STATE_BUSY_RX;
+    hi2c->Mode      = HAL_I2C_MODE_MEM;
+    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr    = pData;
+    hi2c->XferCount   = Size;
+    hi2c->XferSize    = hi2c->XferCount;
+    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+
+    /* Send Slave Address and Memory Address */
+    if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK)
+    {
+      return HAL_ERROR;
+    }
+
+    if (hi2c->XferSize == 0U)
+    {
+      /* Clear ADDR flag */
+      __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
+
+      /* Generate Stop */
+      SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
+    }
+    else if (hi2c->XferSize == 1U)
+    {
+      /* Disable Acknowledge */
+      CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
+
+      /* Clear ADDR flag */
+      __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
+
+      /* Generate Stop */
+      SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
+    }
+    else if (hi2c->XferSize == 2U)
+    {
+      /* Disable Acknowledge */
+      CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
+
+      /* Enable Pos */
+      SET_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
+
+      /* Clear ADDR flag */
+      __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
+    }
+    else
+    {
+      /* Clear ADDR flag */
+      __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
+    }
+
+    while (hi2c->XferSize > 0U)
+    {
+      if (hi2c->XferSize <= 3U)
+      {
+        /* One byte */
+        if (hi2c->XferSize == 1U)
+        {
+          /* Wait until RXNE flag is set */
+          if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+          {
+            return HAL_ERROR;
+          }
+
+          /* Read data from DR */
+          *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
+
+          /* Increment Buffer pointer */
+          hi2c->pBuffPtr++;
+
+          /* Update counter */
+          hi2c->XferSize--;
+          hi2c->XferCount--;
+        }
+        /* Two bytes */
+        else if (hi2c->XferSize == 2U)
+        {
+          /* Wait until BTF flag is set */
+          if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK)
+          {
+            return HAL_ERROR;
+          }
+
+          /* Generate Stop */
+          SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
+
+          /* Read data from DR */
+          *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
+
+          /* Increment Buffer pointer */
+          hi2c->pBuffPtr++;
+
+          /* Update counter */
+          hi2c->XferSize--;
+          hi2c->XferCount--;
+
+          /* Read data from DR */
+          *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
+
+          /* Increment Buffer pointer */
+          hi2c->pBuffPtr++;
+
+          /* Update counter */
+          hi2c->XferSize--;
+          hi2c->XferCount--;
+        }
+        /* 3 Last bytes */
+        else
+        {
+          /* Wait until BTF flag is set */
+          if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK)
+          {
+            return HAL_ERROR;
+          }
+
+          /* Disable Acknowledge */
+          CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
+
+          /* Read data from DR */
+          *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
+
+          /* Increment Buffer pointer */
+          hi2c->pBuffPtr++;
+
+          /* Update counter */
+          hi2c->XferSize--;
+          hi2c->XferCount--;
+
+          /* Wait until BTF flag is set */
+          if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK)
+          {
+            return HAL_ERROR;
+          }
+
+          /* Generate Stop */
+          SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
+
+          /* Read data from DR */
+          *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
+
+          /* Increment Buffer pointer */
+          hi2c->pBuffPtr++;
+
+          /* Update counter */
+          hi2c->XferSize--;
+          hi2c->XferCount--;
+
+          /* Read data from DR */
+          *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
+
+          /* Increment Buffer pointer */
+          hi2c->pBuffPtr++;
+
+          /* Update counter */
+          hi2c->XferSize--;
+          hi2c->XferCount--;
+        }
+      }
+      else
+      {
+        /* Wait until RXNE flag is set */
+        if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+        {
+          return HAL_ERROR;
+        }
+
+        /* Read data from DR */
+        *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
+
+        /* Increment Buffer pointer */
+        hi2c->pBuffPtr++;
+
+        /* Update counter */
+        hi2c->XferSize--;
+        hi2c->XferCount--;
+
+        if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET)
+        {
+          /* Read data from DR */
+          *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
+
+          /* Increment Buffer pointer */
+          hi2c->pBuffPtr++;
+
+          /* Update counter */
+          hi2c->XferSize--;
+          hi2c->XferCount--;
+        }
+      }
+    }
+
+    hi2c->State = HAL_I2C_STATE_READY;
+    hi2c->Mode = HAL_I2C_MODE_NONE;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Write an amount of data in non-blocking mode with Interrupt to a specific memory address
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shifted to the left before calling the interface
+  * @param  MemAddress Internal memory address
+  * @param  MemAddSize Size of internal memory address
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
+{
+  __IO uint32_t count = 0U;
+
+  /* Check the parameters */
+  assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
+
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    /* Wait until BUSY flag is reset */
+    count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U);
+    do
+    {
+      count--;
+      if (count == 0U)
+      {
+        hi2c->PreviousState       = I2C_STATE_NONE;
+        hi2c->State               = HAL_I2C_STATE_READY;
+        hi2c->Mode                = HAL_I2C_MODE_NONE;
+        hi2c->ErrorCode           |= HAL_I2C_ERROR_TIMEOUT;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+
+        return HAL_ERROR;
+      }
+    }
+    while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
+
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    /* Check if the I2C is already enabled */
+    if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
+    {
+      /* Enable I2C peripheral */
+      __HAL_I2C_ENABLE(hi2c);
+    }
+
+    /* Disable Pos */
+    CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
+
+    hi2c->State     = HAL_I2C_STATE_BUSY_TX;
+    hi2c->Mode      = HAL_I2C_MODE_MEM;
+    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr    = pData;
+    hi2c->XferCount   = Size;
+    hi2c->XferSize    = hi2c->XferCount;
+    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+    hi2c->Devaddress  = DevAddress;
+    hi2c->Memaddress  = MemAddress;
+    hi2c->MemaddSize  = MemAddSize;
+    hi2c->EventCount  = 0U;
+
+    /* Generate Start */
+    SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    /* Note : The I2C interrupts must be enabled after unlocking current process
+    to avoid the risk of I2C interrupt handle execution before current
+    process unlock */
+
+    /* Enable EVT, BUF and ERR interrupt */
+    __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Read an amount of data in non-blocking mode with Interrupt from a specific memory address
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  DevAddress Target device address
+  * @param  MemAddress Internal memory address
+  * @param  MemAddSize Size of internal memory address
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
+{
+  __IO uint32_t count = 0U;
+
+  /* Check the parameters */
+  assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
+
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    /* Wait until BUSY flag is reset */
+    count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U);
+    do
+    {
+      count--;
+      if (count == 0U)
+      {
+        hi2c->PreviousState       = I2C_STATE_NONE;
+        hi2c->State               = HAL_I2C_STATE_READY;
+        hi2c->Mode                = HAL_I2C_MODE_NONE;
+        hi2c->ErrorCode           |= HAL_I2C_ERROR_TIMEOUT;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+
+        return HAL_ERROR;
+      }
+    }
+    while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
+
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    /* Check if the I2C is already enabled */
+    if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
+    {
+      /* Enable I2C peripheral */
+      __HAL_I2C_ENABLE(hi2c);
+    }
+
+    /* Disable Pos */
+    CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
+
+    hi2c->State     = HAL_I2C_STATE_BUSY_RX;
+    hi2c->Mode      = HAL_I2C_MODE_MEM;
+    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr    = pData;
+    hi2c->XferCount   = Size;
+    hi2c->XferSize    = hi2c->XferCount;
+    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+    hi2c->Devaddress  = DevAddress;
+    hi2c->Memaddress  = MemAddress;
+    hi2c->MemaddSize  = MemAddSize;
+    hi2c->EventCount  = 0U;
+
+    /* Enable Acknowledge */
+    SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
+
+    /* Generate Start */
+    SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    if (hi2c->XferSize > 0U)
+    {
+      /* Note : The I2C interrupts must be enabled after unlocking current process
+      to avoid the risk of I2C interrupt handle execution before current
+      process unlock */
+
+      /* Enable EVT, BUF and ERR interrupt */
+      __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
+    }
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Write an amount of data in non-blocking mode with DMA to a specific memory address
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shifted to the left before calling the interface
+  * @param  MemAddress Internal memory address
+  * @param  MemAddSize Size of internal memory address
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
+{
+  __IO uint32_t count = 0U;
+  HAL_StatusTypeDef dmaxferstatus;
+
+  /* Init tickstart for timeout management*/
+  uint32_t tickstart = HAL_GetTick();
+
+  /* Check the parameters */
+  assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
+
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    /* Wait until BUSY flag is reset */
+    count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U);
+    do
+    {
+      count--;
+      if (count == 0U)
+      {
+        hi2c->PreviousState       = I2C_STATE_NONE;
+        hi2c->State               = HAL_I2C_STATE_READY;
+        hi2c->Mode                = HAL_I2C_MODE_NONE;
+        hi2c->ErrorCode           |= HAL_I2C_ERROR_TIMEOUT;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+
+        return HAL_ERROR;
+      }
+    }
+    while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
+
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    /* Check if the I2C is already enabled */
+    if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
+    {
+      /* Enable I2C peripheral */
+      __HAL_I2C_ENABLE(hi2c);
+    }
+
+    /* Disable Pos */
+    CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
+
+    hi2c->State     = HAL_I2C_STATE_BUSY_TX;
+    hi2c->Mode      = HAL_I2C_MODE_MEM;
+    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr    = pData;
+    hi2c->XferCount   = Size;
+    hi2c->XferSize    = hi2c->XferCount;
+    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+    hi2c->Devaddress  = DevAddress;
+    hi2c->Memaddress  = MemAddress;
+    hi2c->MemaddSize  = MemAddSize;
+    hi2c->EventCount  = 0U;
+
+    if (hi2c->XferSize > 0U)
+    {
+      if (hi2c->hdmatx != NULL)
+      {
+        /* Set the I2C DMA transfer complete callback */
+        hi2c->hdmatx->XferCpltCallback = I2C_DMAXferCplt;
+
+        /* Set the DMA error callback */
+        hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
+
+        /* Set the unused DMA callbacks to NULL */
+        hi2c->hdmatx->XferHalfCpltCallback = NULL;
+        hi2c->hdmatx->XferM1CpltCallback = NULL;
+        hi2c->hdmatx->XferM1HalfCpltCallback = NULL;
+        hi2c->hdmatx->XferAbortCallback = NULL;
+
+        /* Enable the DMA stream */
+        dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->DR, hi2c->XferSize);
+      }
+      else
+      {
+        /* Update I2C state */
+        hi2c->State     = HAL_I2C_STATE_READY;
+        hi2c->Mode      = HAL_I2C_MODE_NONE;
+
+        /* Update I2C error code */
+        hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+
+        return HAL_ERROR;
+      }
+
+      if (dmaxferstatus == HAL_OK)
+      {
+        /* Send Slave Address and Memory Address */
+        if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
+        {
+          /* Abort the ongoing DMA */
+          dmaxferstatus = HAL_DMA_Abort_IT(hi2c->hdmatx);
+
+          /* Prevent unused argument(s) compilation and MISRA warning */
+          UNUSED(dmaxferstatus);
+
+          /* Set the unused I2C DMA transfer complete callback to NULL */
+          hi2c->hdmatx->XferCpltCallback = NULL;
+
+          /* Disable Acknowledge */
+          CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
+
+          hi2c->XferSize = 0U;
+          hi2c->XferCount = 0U;
+
+          /* Disable I2C peripheral to prevent dummy data in buffer */
+          __HAL_I2C_DISABLE(hi2c);
+
+          return HAL_ERROR;
+        }
+
+        /* Clear ADDR flag */
+        __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+
+        /* Note : The I2C interrupts must be enabled after unlocking current process
+        to avoid the risk of I2C interrupt handle execution before current
+        process unlock */
+        /* Enable ERR interrupt */
+        __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_ERR);
+
+        /* Enable DMA Request */
+        SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
+
+        return HAL_OK;
+      }
+      else
+      {
+        /* Update I2C state */
+        hi2c->State     = HAL_I2C_STATE_READY;
+        hi2c->Mode      = HAL_I2C_MODE_NONE;
+
+        /* Update I2C error code */
+        hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+
+        return HAL_ERROR;
+      }
+    }
+    else
+    {
+      /* Update I2C state */
+      hi2c->State     = HAL_I2C_STATE_READY;
+      hi2c->Mode      = HAL_I2C_MODE_NONE;
+
+      /* Update I2C error code */
+      hi2c->ErrorCode |= HAL_I2C_ERROR_SIZE;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      return HAL_ERROR;
+    }
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Reads an amount of data in non-blocking mode with DMA from a specific memory address.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shifted to the left before calling the interface
+  * @param  MemAddress Internal memory address
+  * @param  MemAddSize Size of internal memory address
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be read
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
+{
+  /* Init tickstart for timeout management*/
+  uint32_t tickstart = HAL_GetTick();
+  __IO uint32_t count = 0U;
+  HAL_StatusTypeDef dmaxferstatus;
+
+  /* Check the parameters */
+  assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
+
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    /* Wait until BUSY flag is reset */
+    count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U);
+    do
+    {
+      count--;
+      if (count == 0U)
+      {
+        hi2c->PreviousState       = I2C_STATE_NONE;
+        hi2c->State               = HAL_I2C_STATE_READY;
+        hi2c->Mode                = HAL_I2C_MODE_NONE;
+        hi2c->ErrorCode           |= HAL_I2C_ERROR_TIMEOUT;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+
+        return HAL_ERROR;
+      }
+    }
+    while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
+
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    /* Check if the I2C is already enabled */
+    if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
+    {
+      /* Enable I2C peripheral */
+      __HAL_I2C_ENABLE(hi2c);
+    }
+
+    /* Disable Pos */
+    CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
+
+    hi2c->State     = HAL_I2C_STATE_BUSY_RX;
+    hi2c->Mode      = HAL_I2C_MODE_MEM;
+    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr    = pData;
+    hi2c->XferCount   = Size;
+    hi2c->XferSize    = hi2c->XferCount;
+    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+    hi2c->Devaddress  = DevAddress;
+    hi2c->Memaddress  = MemAddress;
+    hi2c->MemaddSize  = MemAddSize;
+    hi2c->EventCount  = 0U;
+
+    if (hi2c->XferSize > 0U)
+    {
+      if (hi2c->hdmarx != NULL)
+      {
+        /* Set the I2C DMA transfer complete callback */
+        hi2c->hdmarx->XferCpltCallback = I2C_DMAXferCplt;
+
+        /* Set the DMA error callback */
+        hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
+
+        /* Set the unused DMA callbacks to NULL */
+        hi2c->hdmarx->XferHalfCpltCallback = NULL;
+        hi2c->hdmarx->XferM1CpltCallback = NULL;
+        hi2c->hdmarx->XferM1HalfCpltCallback = NULL;
+        hi2c->hdmarx->XferAbortCallback = NULL;
+
+        /* Enable the DMA stream */
+        dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize);
+      }
+      else
+      {
+        /* Update I2C state */
+        hi2c->State     = HAL_I2C_STATE_READY;
+        hi2c->Mode      = HAL_I2C_MODE_NONE;
+
+        /* Update I2C error code */
+        hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+
+        return HAL_ERROR;
+      }
+
+      if (dmaxferstatus == HAL_OK)
+      {
+        /* Send Slave Address and Memory Address */
+        if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
+        {
+          /* Abort the ongoing DMA */
+          dmaxferstatus = HAL_DMA_Abort_IT(hi2c->hdmarx);
+
+          /* Prevent unused argument(s) compilation and MISRA warning */
+          UNUSED(dmaxferstatus);
+
+          /* Set the unused I2C DMA transfer complete callback to NULL */
+          hi2c->hdmarx->XferCpltCallback = NULL;
+
+          /* Disable Acknowledge */
+          CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
+
+          hi2c->XferSize = 0U;
+          hi2c->XferCount = 0U;
+
+          /* Disable I2C peripheral to prevent dummy data in buffer */
+          __HAL_I2C_DISABLE(hi2c);
+
+          return HAL_ERROR;
+        }
+
+        if (hi2c->XferSize == 1U)
+        {
+          /* Disable Acknowledge */
+          CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
+        }
+        else
+        {
+          /* Enable Last DMA bit */
+          SET_BIT(hi2c->Instance->CR2, I2C_CR2_LAST);
+        }
+
+        /* Clear ADDR flag */
+        __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+
+        /* Note : The I2C interrupts must be enabled after unlocking current process
+        to avoid the risk of I2C interrupt handle execution before current
+        process unlock */
+        /* Enable ERR interrupt */
+        __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_ERR);
+
+        /* Enable DMA Request */
+        hi2c->Instance->CR2 |= I2C_CR2_DMAEN;
+      }
+      else
+      {
+        /* Update I2C state */
+        hi2c->State     = HAL_I2C_STATE_READY;
+        hi2c->Mode      = HAL_I2C_MODE_NONE;
+
+        /* Update I2C error code */
+        hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+
+        return HAL_ERROR;
+      }
+    }
+    else
+    {
+      /* Send Slave Address and Memory Address */
+      if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
+
+      /* Clear ADDR flag */
+      __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
+
+      /* Generate Stop */
+      SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
+
+      hi2c->State = HAL_I2C_STATE_READY;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+    }
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Checks if target device is ready for communication.
+  * @note   This function is used with Memory devices
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shifted to the left before calling the interface
+  * @param  Trials Number of trials
+  * @param  Timeout Timeout duration
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout)
+{
+  /* Get tick */
+  uint32_t tickstart = HAL_GetTick();
+  uint32_t I2C_Trials = 0U;
+  FlagStatus tmp1;
+  FlagStatus tmp2;
+
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    /* Wait until BUSY flag is reset */
+    if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK)
+    {
+      return HAL_BUSY;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    /* Check if the I2C is already enabled */
+    if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
+    {
+      /* Enable I2C peripheral */
+      __HAL_I2C_ENABLE(hi2c);
+    }
+
+    /* Disable Pos */
+    CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
+
+    hi2c->State = HAL_I2C_STATE_BUSY;
+    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+
+    do
+    {
+      /* Generate Start */
+      SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
+
+      /* Wait until SB flag is set */
+      if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, tickstart) != HAL_OK)
+      {
+        if (READ_BIT(hi2c->Instance->CR1, I2C_CR1_START) == I2C_CR1_START)
+        {
+          hi2c->ErrorCode = HAL_I2C_WRONG_START;
+        }
+        return HAL_TIMEOUT;
+      }
+
+      /* Send slave address */
+      hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(DevAddress);
+
+      /* Wait until ADDR or AF flag are set */
+      /* Get tick */
+      tickstart = HAL_GetTick();
+
+      tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR);
+      tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF);
+      while ((hi2c->State != HAL_I2C_STATE_TIMEOUT) && (tmp1 == RESET) && (tmp2 == RESET))
+      {
+        if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
+        {
+          hi2c->State = HAL_I2C_STATE_TIMEOUT;
+        }
+        tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR);
+        tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF);
+      }
+
+      hi2c->State = HAL_I2C_STATE_READY;
+
+      /* Check if the ADDR flag has been set */
+      if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR) == SET)
+      {
+        /* Generate Stop */
+        SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
+
+        /* Clear ADDR Flag */
+        __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
+
+        /* Wait until BUSY flag is reset */
+        if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK)
+        {
+          return HAL_ERROR;
+        }
+
+        hi2c->State = HAL_I2C_STATE_READY;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+
+        return HAL_OK;
+      }
+      else
+      {
+        /* Generate Stop */
+        SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
+
+        /* Clear AF Flag */
+        __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+
+        /* Wait until BUSY flag is reset */
+        if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK)
+        {
+          return HAL_ERROR;
+        }
+      }
+
+      /* Increment Trials */
+      I2C_Trials++;
+    }
+    while (I2C_Trials < Trials);
+
+    hi2c->State = HAL_I2C_STATE_READY;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    return HAL_ERROR;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Sequential transmit in master I2C mode an amount of data in non-blocking mode with Interrupt.
+  * @note   This interface allow to manage repeated start condition when a direction change during transfer
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *         the configuration information for the specified I2C.
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shifted to the left before calling the interface
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @param  XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
+{
+  __IO uint32_t Prev_State = 0x00U;
+  __IO uint32_t count      = 0x00U;
+
+  /* Check the parameters */
+  assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
+
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    /* Check Busy Flag only if FIRST call of Master interface */
+    if ((READ_BIT(hi2c->Instance->CR1, I2C_CR1_STOP) == I2C_CR1_STOP) || (XferOptions == I2C_FIRST_AND_LAST_FRAME) || (XferOptions == I2C_FIRST_FRAME))
+    {
+      /* Wait until BUSY flag is reset */
+      count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U);
+      do
+      {
+        count--;
+        if (count == 0U)
+        {
+          hi2c->PreviousState       = I2C_STATE_NONE;
+          hi2c->State               = HAL_I2C_STATE_READY;
+          hi2c->Mode                = HAL_I2C_MODE_NONE;
+          hi2c->ErrorCode           |= HAL_I2C_ERROR_TIMEOUT;
+
+          /* Process Unlocked */
+          __HAL_UNLOCK(hi2c);
+
+          return HAL_ERROR;
+        }
+      }
+      while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    /* Check if the I2C is already enabled */
+    if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
+    {
+      /* Enable I2C peripheral */
+      __HAL_I2C_ENABLE(hi2c);
+    }
+
+    /* Disable Pos */
+    CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
+
+    hi2c->State     = HAL_I2C_STATE_BUSY_TX;
+    hi2c->Mode      = HAL_I2C_MODE_MASTER;
+    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr    = pData;
+    hi2c->XferCount   = Size;
+    hi2c->XferSize    = hi2c->XferCount;
+    hi2c->XferOptions = XferOptions;
+    hi2c->Devaddress  = DevAddress;
+
+    Prev_State = hi2c->PreviousState;
+
+    /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */
+    /* Mean Previous state is same as current state */
+    if ((Prev_State != I2C_STATE_MASTER_BUSY_TX) || (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 1))
+    {
+      /* Generate Start */
+      SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
+    }
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    /* Note : The I2C interrupts must be enabled after unlocking current process
+    to avoid the risk of I2C interrupt handle execution before current
+    process unlock */
+
+    /* Enable EVT, BUF and ERR interrupt */
+    __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Sequential transmit in master I2C mode an amount of data in non-blocking mode with DMA.
+  * @note   This interface allow to manage repeated start condition when a direction change during transfer
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *         the configuration information for the specified I2C.
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shifted to the left before calling the interface
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @param  XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
+{
+  __IO uint32_t Prev_State = 0x00U;
+  __IO uint32_t count      = 0x00U;
+  HAL_StatusTypeDef dmaxferstatus;
+
+  /* Check the parameters */
+  assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
+
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    /* Check Busy Flag only if FIRST call of Master interface */
+    if ((READ_BIT(hi2c->Instance->CR1, I2C_CR1_STOP) == I2C_CR1_STOP) || (XferOptions == I2C_FIRST_AND_LAST_FRAME) || (XferOptions == I2C_FIRST_FRAME))
+    {
+      /* Wait until BUSY flag is reset */
+      count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U);
+      do
+      {
+        count--;
+        if (count == 0U)
+        {
+          hi2c->PreviousState       = I2C_STATE_NONE;
+          hi2c->State               = HAL_I2C_STATE_READY;
+          hi2c->Mode                = HAL_I2C_MODE_NONE;
+          hi2c->ErrorCode           |= HAL_I2C_ERROR_TIMEOUT;
+
+          /* Process Unlocked */
+          __HAL_UNLOCK(hi2c);
+
+          return HAL_ERROR;
+        }
+      }
+      while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    /* Check if the I2C is already enabled */
+    if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
+    {
+      /* Enable I2C peripheral */
+      __HAL_I2C_ENABLE(hi2c);
+    }
+
+    /* Disable Pos */
+    CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
+
+    hi2c->State     = HAL_I2C_STATE_BUSY_TX;
+    hi2c->Mode      = HAL_I2C_MODE_MASTER;
+    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr    = pData;
+    hi2c->XferCount   = Size;
+    hi2c->XferSize    = hi2c->XferCount;
+    hi2c->XferOptions = XferOptions;
+    hi2c->Devaddress  = DevAddress;
+
+    Prev_State = hi2c->PreviousState;
+
+    if (hi2c->XferSize > 0U)
+    {
+      if (hi2c->hdmatx != NULL)
+      {
+        /* Set the I2C DMA transfer complete callback */
+        hi2c->hdmatx->XferCpltCallback = I2C_DMAXferCplt;
+
+        /* Set the DMA error callback */
+        hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
+
+        /* Set the unused DMA callbacks to NULL */
+        hi2c->hdmatx->XferHalfCpltCallback = NULL;
+        hi2c->hdmatx->XferAbortCallback = NULL;
+
+        /* Enable the DMA stream */
+        dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->DR, hi2c->XferSize);
+      }
+      else
+      {
+        /* Update I2C state */
+        hi2c->State     = HAL_I2C_STATE_READY;
+        hi2c->Mode      = HAL_I2C_MODE_NONE;
+
+        /* Update I2C error code */
+        hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+
+        return HAL_ERROR;
+      }
+
+      if (dmaxferstatus == HAL_OK)
+      {
+        /* Enable Acknowledge */
+        SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
+
+        /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */
+        /* Mean Previous state is same as current state */
+        if ((Prev_State != I2C_STATE_MASTER_BUSY_TX) || (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 1))
+        {
+          /* Generate Start */
+          SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
+        }
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+
+        /* Note : The I2C interrupts must be enabled after unlocking current process
+        to avoid the risk of I2C interrupt handle execution before current
+        process unlock */
+
+        /* If XferOptions is not associated to a new frame, mean no start bit is request, enable directly the DMA request */
+        /* In other cases, DMA request is enabled after Slave address treatment in IRQHandler */
+        if ((XferOptions == I2C_NEXT_FRAME) || (XferOptions == I2C_LAST_FRAME) || (XferOptions == I2C_LAST_FRAME_NO_STOP))
+        {
+          /* Enable DMA Request */
+          SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
+        }
+
+        /* Enable EVT and ERR interrupt */
+        __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
+      }
+      else
+      {
+        /* Update I2C state */
+        hi2c->State     = HAL_I2C_STATE_READY;
+        hi2c->Mode      = HAL_I2C_MODE_NONE;
+
+        /* Update I2C error code */
+        hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+
+        return HAL_ERROR;
+      }
+    }
+    else
+    {
+      /* Enable Acknowledge */
+      SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
+
+      /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */
+      /* Mean Previous state is same as current state */
+      if ((Prev_State != I2C_STATE_MASTER_BUSY_TX) || (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 1))
+      {
+        /* Generate Start */
+        SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
+      }
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      /* Note : The I2C interrupts must be enabled after unlocking current process
+      to avoid the risk of I2C interrupt handle execution before current
+      process unlock */
+
+      /* Enable EVT, BUF and ERR interrupt */
+      __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
+    }
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Sequential receive in master I2C mode an amount of data in non-blocking mode with Interrupt
+  * @note   This interface allow to manage repeated start condition when a direction change during transfer
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *         the configuration information for the specified I2C.
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shifted to the left before calling the interface
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @param  XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
+{
+  __IO uint32_t Prev_State = 0x00U;
+  __IO uint32_t count = 0U;
+  uint32_t enableIT = (I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
+
+  /* Check the parameters */
+  assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
+
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    /* Check Busy Flag only if FIRST call of Master interface */
+    if ((READ_BIT(hi2c->Instance->CR1, I2C_CR1_STOP) == I2C_CR1_STOP) || (XferOptions == I2C_FIRST_AND_LAST_FRAME) || (XferOptions == I2C_FIRST_FRAME))
+    {
+      /* Wait until BUSY flag is reset */
+      count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U);
+      do
+      {
+        count--;
+        if (count == 0U)
+        {
+          hi2c->PreviousState       = I2C_STATE_NONE;
+          hi2c->State               = HAL_I2C_STATE_READY;
+          hi2c->Mode                = HAL_I2C_MODE_NONE;
+          hi2c->ErrorCode           |= HAL_I2C_ERROR_TIMEOUT;
+
+          /* Process Unlocked */
+          __HAL_UNLOCK(hi2c);
+
+          return HAL_ERROR;
+        }
+      }
+      while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    /* Check if the I2C is already enabled */
+    if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
+    {
+      /* Enable I2C peripheral */
+      __HAL_I2C_ENABLE(hi2c);
+    }
+
+    /* Disable Pos */
+    CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
+
+    hi2c->State     = HAL_I2C_STATE_BUSY_RX;
+    hi2c->Mode      = HAL_I2C_MODE_MASTER;
+    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr    = pData;
+    hi2c->XferCount   = Size;
+    hi2c->XferSize    = hi2c->XferCount;
+    hi2c->XferOptions = XferOptions;
+    hi2c->Devaddress  = DevAddress;
+
+    Prev_State = hi2c->PreviousState;
+
+    if ((hi2c->XferCount == 2U) && ((XferOptions == I2C_LAST_FRAME) || (XferOptions == I2C_LAST_FRAME_NO_STOP)))
+    {
+      if (Prev_State == I2C_STATE_MASTER_BUSY_RX)
+      {
+        /* Disable Acknowledge */
+        CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
+
+        /* Enable Pos */
+        SET_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
+
+        /* Remove Enabling of IT_BUF, mean RXNE treatment, treat the 2 bytes through BTF */
+        enableIT &= ~I2C_IT_BUF;
+      }
+      else
+      {
+        /* Enable Acknowledge */
+        SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
+      }
+    }
+    else
+    {
+      /* Enable Acknowledge */
+      SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
+    }
+
+    /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */
+    /* Mean Previous state is same as current state */
+    if ((Prev_State != I2C_STATE_MASTER_BUSY_RX) || (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 1))
+    {
+      /* Generate Start */
+      SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
+    }
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    /* Note : The I2C interrupts must be enabled after unlocking current process
+    to avoid the risk of I2C interrupt handle execution before current
+    process unlock */
+
+    /* Enable interrupts */
+    __HAL_I2C_ENABLE_IT(hi2c, enableIT);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Sequential receive in master mode an amount of data in non-blocking mode with DMA
+  * @note   This interface allow to manage repeated start condition when a direction change during transfer
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *         the configuration information for the specified I2C.
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shifted to the left before calling the interface
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @param  XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
+{
+  __IO uint32_t Prev_State = 0x00U;
+  __IO uint32_t count = 0U;
+  uint32_t enableIT = (I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
+  HAL_StatusTypeDef dmaxferstatus;
+
+  /* Check the parameters */
+  assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
+
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    /* Check Busy Flag only if FIRST call of Master interface */
+    if ((READ_BIT(hi2c->Instance->CR1, I2C_CR1_STOP) == I2C_CR1_STOP) || (XferOptions == I2C_FIRST_AND_LAST_FRAME) || (XferOptions == I2C_FIRST_FRAME))
+    {
+      /* Wait until BUSY flag is reset */
+      count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U);
+      do
+      {
+        count--;
+        if (count == 0U)
+        {
+          hi2c->PreviousState       = I2C_STATE_NONE;
+          hi2c->State               = HAL_I2C_STATE_READY;
+          hi2c->Mode                = HAL_I2C_MODE_NONE;
+          hi2c->ErrorCode           |= HAL_I2C_ERROR_TIMEOUT;
+
+          /* Process Unlocked */
+          __HAL_UNLOCK(hi2c);
+
+          return HAL_ERROR;
+        }
+      }
+      while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    /* Check if the I2C is already enabled */
+    if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
+    {
+      /* Enable I2C peripheral */
+      __HAL_I2C_ENABLE(hi2c);
+    }
+
+    /* Disable Pos */
+    CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
+
+    /* Clear Last DMA bit */
+    CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_LAST);
+
+    hi2c->State     = HAL_I2C_STATE_BUSY_RX;
+    hi2c->Mode      = HAL_I2C_MODE_MASTER;
+    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr    = pData;
+    hi2c->XferCount   = Size;
+    hi2c->XferSize    = hi2c->XferCount;
+    hi2c->XferOptions = XferOptions;
+    hi2c->Devaddress  = DevAddress;
+
+    Prev_State = hi2c->PreviousState;
+
+    if (hi2c->XferSize > 0U)
+    {
+      if ((hi2c->XferCount == 2U) && ((XferOptions == I2C_LAST_FRAME) || (XferOptions == I2C_LAST_FRAME_NO_STOP)))
+      {
+        if (Prev_State == I2C_STATE_MASTER_BUSY_RX)
+        {
+          /* Disable Acknowledge */
+          CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
+
+          /* Enable Pos */
+          SET_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
+
+          /* Enable Last DMA bit */
+          SET_BIT(hi2c->Instance->CR2, I2C_CR2_LAST);
+        }
+        else
+        {
+          /* Enable Acknowledge */
+          SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
+        }
+      }
+      else
+      {
+        /* Enable Acknowledge */
+        SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
+
+        if ((XferOptions == I2C_LAST_FRAME) || (XferOptions == I2C_OTHER_AND_LAST_FRAME) || (XferOptions == I2C_LAST_FRAME_NO_STOP))
+        {
+          /* Enable Last DMA bit */
+          SET_BIT(hi2c->Instance->CR2, I2C_CR2_LAST);
+        }
+      }
+      if (hi2c->hdmarx != NULL)
+      {
+        /* Set the I2C DMA transfer complete callback */
+        hi2c->hdmarx->XferCpltCallback = I2C_DMAXferCplt;
+
+        /* Set the DMA error callback */
+        hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
+
+        /* Set the unused DMA callbacks to NULL */
+        hi2c->hdmarx->XferHalfCpltCallback = NULL;
+        hi2c->hdmarx->XferAbortCallback = NULL;
+
+        /* Enable the DMA stream */
+        dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize);
+      }
+      else
+      {
+        /* Update I2C state */
+        hi2c->State     = HAL_I2C_STATE_READY;
+        hi2c->Mode      = HAL_I2C_MODE_NONE;
+
+        /* Update I2C error code */
+        hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+
+        return HAL_ERROR;
+      }
+      if (dmaxferstatus == HAL_OK)
+      {
+        /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */
+        /* Mean Previous state is same as current state */
+        if ((Prev_State != I2C_STATE_MASTER_BUSY_RX) || (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 1))
+        {
+          /* Generate Start */
+          SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
+
+          /* Update interrupt for only EVT and ERR */
+          enableIT = (I2C_IT_EVT | I2C_IT_ERR);
+        }
+        else
+        {
+          /* Update interrupt for only ERR */
+          enableIT = I2C_IT_ERR;
+        }
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+
+        /* Note : The I2C interrupts must be enabled after unlocking current process
+        to avoid the risk of I2C interrupt handle execution before current
+        process unlock */
+
+        /* If XferOptions is not associated to a new frame, mean no start bit is request, enable directly the DMA request */
+        /* In other cases, DMA request is enabled after Slave address treatment in IRQHandler */
+        if ((XferOptions == I2C_NEXT_FRAME) || (XferOptions == I2C_LAST_FRAME) || (XferOptions == I2C_LAST_FRAME_NO_STOP))
+        {
+          /* Enable DMA Request */
+          SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
+        }
+
+        /* Enable EVT and ERR interrupt */
+        __HAL_I2C_ENABLE_IT(hi2c, enableIT);
+      }
+      else
+      {
+        /* Update I2C state */
+        hi2c->State     = HAL_I2C_STATE_READY;
+        hi2c->Mode      = HAL_I2C_MODE_NONE;
+
+        /* Update I2C error code */
+        hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+
+        return HAL_ERROR;
+      }
+    }
+    else
+    {
+      /* Enable Acknowledge */
+      SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
+
+      /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */
+      /* Mean Previous state is same as current state */
+      if ((Prev_State != I2C_STATE_MASTER_BUSY_RX) || (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 1))
+      {
+        /* Generate Start */
+        SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
+      }
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      /* Note : The I2C interrupts must be enabled after unlocking current process
+      to avoid the risk of I2C interrupt handle execution before current
+      process unlock */
+
+      /* Enable interrupts */
+      __HAL_I2C_ENABLE_IT(hi2c, enableIT);
+    }
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Sequential transmit in slave mode an amount of data in non-blocking mode with Interrupt
+  * @note   This interface allow to manage repeated start condition when a direction change during transfer
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *         the configuration information for the specified I2C.
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @param  XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
+
+  if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
+  {
+    if ((pData == NULL) || (Size == 0U))
+    {
+      return  HAL_ERROR;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    /* Check if the I2C is already enabled */
+    if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
+    {
+      /* Enable I2C peripheral */
+      __HAL_I2C_ENABLE(hi2c);
+    }
+
+    /* Disable Pos */
+    CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
+
+    hi2c->State     = HAL_I2C_STATE_BUSY_TX_LISTEN;
+    hi2c->Mode      = HAL_I2C_MODE_SLAVE;
+    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr    = pData;
+    hi2c->XferCount   = Size;
+    hi2c->XferSize    = hi2c->XferCount;
+    hi2c->XferOptions = XferOptions;
+
+    /* Clear ADDR flag */
+    __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    /* Note : The I2C interrupts must be enabled after unlocking current process
+              to avoid the risk of I2C interrupt handle execution before current
+              process unlock */
+
+    /* Enable EVT, BUF and ERR interrupt */
+    __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Sequential transmit in slave mode an amount of data in non-blocking mode with DMA
+  * @note   This interface allow to manage repeated start condition when a direction change during transfer
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *         the configuration information for the specified I2C.
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @param  XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
+{
+  HAL_StatusTypeDef dmaxferstatus;
+
+  /* Check the parameters */
+  assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
+
+  if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
+  {
+    if ((pData == NULL) || (Size == 0U))
+    {
+      return  HAL_ERROR;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
+    __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
+
+    /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */
+    /* and then toggle the HAL slave RX state to TX state */
+    if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)
+    {
+      if ((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN)
+      {
+        /* Abort DMA Xfer if any */
+        if (hi2c->hdmarx != NULL)
+        {
+          CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
+
+          /* Set the I2C DMA Abort callback :
+           will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
+          hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;
+
+          /* Abort DMA RX */
+          if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
+          {
+            /* Call Directly XferAbortCallback function in case of error */
+            hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
+          }
+        }
+      }
+    }
+    else if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)
+    {
+      if ((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN)
+      {
+        CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
+
+        /* Abort DMA Xfer if any */
+        if (hi2c->hdmatx != NULL)
+        {
+          /* Set the I2C DMA Abort callback :
+           will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
+          hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;
+
+          /* Abort DMA TX */
+          if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
+          {
+            /* Call Directly XferAbortCallback function in case of error */
+            hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
+          }
+        }
+      }
+    }
+    else
+    {
+      /* Nothing to do */
+    }
+
+    /* Check if the I2C is already enabled */
+    if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
+    {
+      /* Enable I2C peripheral */
+      __HAL_I2C_ENABLE(hi2c);
+    }
+
+    /* Disable Pos */
+    CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
+
+    hi2c->State     = HAL_I2C_STATE_BUSY_TX_LISTEN;
+    hi2c->Mode      = HAL_I2C_MODE_SLAVE;
+    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr    = pData;
+    hi2c->XferCount   = Size;
+    hi2c->XferSize    = hi2c->XferCount;
+    hi2c->XferOptions = XferOptions;
+
+    if (hi2c->hdmatx != NULL)
+    {
+      /* Set the I2C DMA transfer complete callback */
+      hi2c->hdmatx->XferCpltCallback = I2C_DMAXferCplt;
+
+      /* Set the DMA error callback */
+      hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
+
+      /* Set the unused DMA callbacks to NULL */
+      hi2c->hdmatx->XferHalfCpltCallback = NULL;
+      hi2c->hdmatx->XferAbortCallback = NULL;
+
+      /* Enable the DMA stream */
+      dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->DR, hi2c->XferSize);
+    }
+    else
+    {
+      /* Update I2C state */
+      hi2c->State     = HAL_I2C_STATE_LISTEN;
+      hi2c->Mode      = HAL_I2C_MODE_NONE;
+
+      /* Update I2C error code */
+      hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      return HAL_ERROR;
+    }
+
+    if (dmaxferstatus == HAL_OK)
+    {
+      /* Enable Address Acknowledge */
+      SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
+
+      /* Clear ADDR flag */
+      __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      /* Note : The I2C interrupts must be enabled after unlocking current process
+      to avoid the risk of I2C interrupt handle execution before current
+      process unlock */
+      /* Enable EVT and ERR interrupt */
+      __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
+
+      /* Enable DMA Request */
+      hi2c->Instance->CR2 |= I2C_CR2_DMAEN;
+
+      return HAL_OK;
+    }
+    else
+    {
+      /* Update I2C state */
+      hi2c->State     = HAL_I2C_STATE_READY;
+      hi2c->Mode      = HAL_I2C_MODE_NONE;
+
+      /* Update I2C error code */
+      hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      return HAL_ERROR;
+    }
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Sequential receive in slave mode an amount of data in non-blocking mode with Interrupt
+  * @note   This interface allow to manage repeated start condition when a direction change during transfer
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *         the configuration information for the specified I2C.
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @param  XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
+
+  if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
+  {
+    if ((pData == NULL) || (Size == 0U))
+    {
+      return  HAL_ERROR;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    /* Check if the I2C is already enabled */
+    if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
+    {
+      /* Enable I2C peripheral */
+      __HAL_I2C_ENABLE(hi2c);
+    }
+
+    /* Disable Pos */
+    CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
+
+    hi2c->State     = HAL_I2C_STATE_BUSY_RX_LISTEN;
+    hi2c->Mode      = HAL_I2C_MODE_SLAVE;
+    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr    = pData;
+    hi2c->XferCount   = Size;
+    hi2c->XferSize    = hi2c->XferCount;
+    hi2c->XferOptions = XferOptions;
+
+    /* Clear ADDR flag */
+    __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    /* Note : The I2C interrupts must be enabled after unlocking current process
+              to avoid the risk of I2C interrupt handle execution before current
+              process unlock */
+
+    /* Enable EVT, BUF and ERR interrupt */
+    __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Sequential receive in slave mode an amount of data in non-blocking mode with DMA
+  * @note   This interface allow to manage repeated start condition when a direction change during transfer
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *         the configuration information for the specified I2C.
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @param  XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
+{
+  HAL_StatusTypeDef dmaxferstatus;
+
+  /* Check the parameters */
+  assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
+
+  if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
+  {
+    if ((pData == NULL) || (Size == 0U))
+    {
+      return  HAL_ERROR;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
+    __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
+
+    /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */
+    /* and then toggle the HAL slave RX state to TX state */
+    if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)
+    {
+      if ((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN)
+      {
+        /* Abort DMA Xfer if any */
+        if (hi2c->hdmarx != NULL)
+        {
+          CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
+
+          /* Set the I2C DMA Abort callback :
+           will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
+          hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;
+
+          /* Abort DMA RX */
+          if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
+          {
+            /* Call Directly XferAbortCallback function in case of error */
+            hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
+          }
+        }
+      }
+    }
+    else if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)
+    {
+      if ((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN)
+      {
+        CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
+
+        /* Abort DMA Xfer if any */
+        if (hi2c->hdmatx != NULL)
+        {
+          /* Set the I2C DMA Abort callback :
+           will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
+          hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;
+
+          /* Abort DMA TX */
+          if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
+          {
+            /* Call Directly XferAbortCallback function in case of error */
+            hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
+          }
+        }
+      }
+    }
+    else
+    {
+      /* Nothing to do */
+    }
+
+    /* Check if the I2C is already enabled */
+    if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
+    {
+      /* Enable I2C peripheral */
+      __HAL_I2C_ENABLE(hi2c);
+    }
+
+    /* Disable Pos */
+    CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
+
+    hi2c->State     = HAL_I2C_STATE_BUSY_RX_LISTEN;
+    hi2c->Mode      = HAL_I2C_MODE_SLAVE;
+    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr    = pData;
+    hi2c->XferCount   = Size;
+    hi2c->XferSize    = hi2c->XferCount;
+    hi2c->XferOptions = XferOptions;
+
+    if (hi2c->hdmarx != NULL)
+    {
+      /* Set the I2C DMA transfer complete callback */
+      hi2c->hdmarx->XferCpltCallback = I2C_DMAXferCplt;
+
+      /* Set the DMA error callback */
+      hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
+
+      /* Set the unused DMA callbacks to NULL */
+      hi2c->hdmarx->XferHalfCpltCallback = NULL;
+      hi2c->hdmarx->XferAbortCallback = NULL;
+
+      /* Enable the DMA stream */
+      dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize);
+    }
+    else
+    {
+      /* Update I2C state */
+      hi2c->State     = HAL_I2C_STATE_LISTEN;
+      hi2c->Mode      = HAL_I2C_MODE_NONE;
+
+      /* Update I2C error code */
+      hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      return HAL_ERROR;
+    }
+
+    if (dmaxferstatus == HAL_OK)
+    {
+      /* Enable Address Acknowledge */
+      SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
+
+      /* Clear ADDR flag */
+      __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      /* Enable DMA Request */
+      SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
+
+      /* Note : The I2C interrupts must be enabled after unlocking current process
+      to avoid the risk of I2C interrupt handle execution before current
+      process unlock */
+      /* Enable EVT and ERR interrupt */
+      __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
+
+      return HAL_OK;
+    }
+    else
+    {
+      /* Update I2C state */
+      hi2c->State     = HAL_I2C_STATE_READY;
+      hi2c->Mode      = HAL_I2C_MODE_NONE;
+
+      /* Update I2C error code */
+      hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      return HAL_ERROR;
+    }
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Enable the Address listen mode with Interrupt.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c)
+{
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    hi2c->State = HAL_I2C_STATE_LISTEN;
+
+    /* Check if the I2C is already enabled */
+    if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
+    {
+      /* Enable I2C peripheral */
+      __HAL_I2C_ENABLE(hi2c);
+    }
+
+    /* Enable Address Acknowledge */
+    SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
+
+    /* Enable EVT and ERR interrupt */
+    __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Disable the Address listen mode with Interrupt.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c)
+{
+  /* Declaration of tmp to prevent undefined behavior of volatile usage */
+  uint32_t tmp;
+
+  /* Disable Address listen mode only if a transfer is not ongoing */
+  if (hi2c->State == HAL_I2C_STATE_LISTEN)
+  {
+    tmp = (uint32_t)(hi2c->State) & I2C_STATE_MSK;
+    hi2c->PreviousState = tmp | (uint32_t)(hi2c->Mode);
+    hi2c->State = HAL_I2C_STATE_READY;
+    hi2c->Mode = HAL_I2C_MODE_NONE;
+
+    /* Disable Address Acknowledge */
+    CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
+
+    /* Disable EVT and ERR interrupt */
+    __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Abort a master I2C IT or DMA process communication with Interrupt.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *         the configuration information for the specified I2C.
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shifted to the left before calling the interface
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress)
+{
+  /* Declaration of temporary variables to prevent undefined behavior of volatile usage */
+  HAL_I2C_ModeTypeDef CurrentMode   = hi2c->Mode;
+
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(DevAddress);
+
+  /* Abort Master transfer during Receive or Transmit process    */
+  if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET) && (CurrentMode == HAL_I2C_MODE_MASTER))
+  {
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    hi2c->PreviousState = I2C_STATE_NONE;
+    hi2c->State = HAL_I2C_STATE_ABORT;
+
+    /* Disable Acknowledge */
+    CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
+
+    /* Generate Stop */
+    SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
+
+    hi2c->XferCount = 0U;
+
+    /* Disable EVT, BUF and ERR interrupt */
+    __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    /* Call the corresponding callback to inform upper layer of End of Transfer */
+    I2C_ITError(hi2c);
+
+    return HAL_OK;
+  }
+  else
+  {
+    /* Wrong usage of abort function */
+    /* This function should be used only in case of abort monitored by master device */
+    /* Or periphal is not in busy state, mean there is no active sequence to be abort */
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
+ * @{
+ */
+
+/**
+  * @brief  This function handles I2C event interrupt request.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @retval None
+  */
+void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c)
+{
+  uint32_t sr1itflags;
+  uint32_t sr2itflags               = 0U;
+  uint32_t itsources                = READ_REG(hi2c->Instance->CR2);
+  uint32_t CurrentXferOptions       = hi2c->XferOptions;
+  HAL_I2C_ModeTypeDef CurrentMode   = hi2c->Mode;
+  HAL_I2C_StateTypeDef CurrentState = hi2c->State;
+
+  /* Master or Memory mode selected */
+  if ((CurrentMode == HAL_I2C_MODE_MASTER) || (CurrentMode == HAL_I2C_MODE_MEM))
+  {
+    sr2itflags   = READ_REG(hi2c->Instance->SR2);
+    sr1itflags   = READ_REG(hi2c->Instance->SR1);
+
+    /* Exit IRQ event until Start Bit detected in case of Other frame requested */
+    if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_SB) == RESET) && (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(CurrentXferOptions) == 1U))
+    {
+      return;
+    }
+
+    /* SB Set ----------------------------------------------------------------*/
+    if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_SB) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_EVT) != RESET))
+    {
+      /* Convert OTHER_xxx XferOptions if any */
+      I2C_ConvertOtherXferOptions(hi2c);
+
+      I2C_Master_SB(hi2c);
+    }
+    /* ADD10 Set -------------------------------------------------------------*/
+    else if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_ADD10) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_EVT) != RESET))
+    {
+      I2C_Master_ADD10(hi2c);
+    }
+    /* ADDR Set --------------------------------------------------------------*/
+    else if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_ADDR) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_EVT) != RESET))
+    {
+      I2C_Master_ADDR(hi2c);
+    }
+    /* I2C in mode Transmitter -----------------------------------------------*/
+    else if (I2C_CHECK_FLAG(sr2itflags, I2C_FLAG_TRA) != RESET)
+    {
+      /* Do not check buffer and BTF flag if a Xfer DMA is on going */
+      if (READ_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN) != I2C_CR2_DMAEN)
+      {
+        /* TXE set and BTF reset -----------------------------------------------*/
+        if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_TXE) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_BUF) != RESET) && (I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_BTF) == RESET))
+        {
+          I2C_MasterTransmit_TXE(hi2c);
+        }
+        /* BTF set -------------------------------------------------------------*/
+        else if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_BTF) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_EVT) != RESET))
+        {
+          if (CurrentState == HAL_I2C_STATE_BUSY_TX)
+          {
+            I2C_MasterTransmit_BTF(hi2c);
+          }
+          else /* HAL_I2C_MODE_MEM */
+          {
+            if (CurrentMode == HAL_I2C_MODE_MEM)
+            {
+              I2C_MemoryTransmit_TXE_BTF(hi2c);
+            }
+          }
+        }
+        else
+        {
+          /* Do nothing */
+        }
+      }
+    }
+    /* I2C in mode Receiver --------------------------------------------------*/
+    else
+    {
+      /* Do not check buffer and BTF flag if a Xfer DMA is on going */
+      if (READ_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN) != I2C_CR2_DMAEN)
+      {
+        /* RXNE set and BTF reset -----------------------------------------------*/
+        if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_RXNE) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_BUF) != RESET) && (I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_BTF) == RESET))
+        {
+          I2C_MasterReceive_RXNE(hi2c);
+        }
+        /* BTF set -------------------------------------------------------------*/
+        else if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_BTF) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_EVT) != RESET))
+        {
+          I2C_MasterReceive_BTF(hi2c);
+        }
+        else
+        {
+          /* Do nothing */
+        }
+      }
+    }
+  }
+  /* Slave mode selected */
+  else
+  {
+    /* If an error is detected, read only SR1 register to prevent */
+    /* a clear of ADDR flags by reading SR2 after reading SR1 in Error treatment */
+    if (hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
+    {
+      sr1itflags   = READ_REG(hi2c->Instance->SR1);
+    }
+    else
+    {
+      sr2itflags   = READ_REG(hi2c->Instance->SR2);
+      sr1itflags   = READ_REG(hi2c->Instance->SR1);
+    }
+
+    /* ADDR set --------------------------------------------------------------*/
+    if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_ADDR) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_EVT) != RESET))
+    {
+      /* Now time to read SR2, this will clear ADDR flag automatically */
+      if (hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
+      {
+        sr2itflags   = READ_REG(hi2c->Instance->SR2);
+      }
+      I2C_Slave_ADDR(hi2c, sr2itflags);
+    }
+    /* STOPF set --------------------------------------------------------------*/
+    else if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_STOPF) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_EVT) != RESET))
+    {
+      I2C_Slave_STOPF(hi2c);
+    }
+    /* I2C in mode Transmitter -----------------------------------------------*/
+    else if ((CurrentState == HAL_I2C_STATE_BUSY_TX) || (CurrentState == HAL_I2C_STATE_BUSY_TX_LISTEN))
+    {
+      /* TXE set and BTF reset -----------------------------------------------*/
+      if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_TXE) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_BUF) != RESET) && (I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_BTF) == RESET))
+      {
+        I2C_SlaveTransmit_TXE(hi2c);
+      }
+      /* BTF set -------------------------------------------------------------*/
+      else if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_BTF) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_EVT) != RESET))
+      {
+        I2C_SlaveTransmit_BTF(hi2c);
+      }
+      else
+      {
+        /* Do nothing */
+      }
+    }
+    /* I2C in mode Receiver --------------------------------------------------*/
+    else
+    {
+      /* RXNE set and BTF reset ----------------------------------------------*/
+      if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_RXNE) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_BUF) != RESET) && (I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_BTF) == RESET))
+      {
+        I2C_SlaveReceive_RXNE(hi2c);
+      }
+      /* BTF set -------------------------------------------------------------*/
+      else if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_BTF) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_EVT) != RESET))
+      {
+        I2C_SlaveReceive_BTF(hi2c);
+      }
+      else
+      {
+        /* Do nothing */
+      }
+    }
+  }
+}
+
+/**
+  * @brief  This function handles I2C error interrupt request.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @retval None
+  */
+void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c)
+{
+  HAL_I2C_ModeTypeDef tmp1;
+  uint32_t tmp2;
+  HAL_I2C_StateTypeDef tmp3;
+  uint32_t tmp4;
+  uint32_t sr1itflags = READ_REG(hi2c->Instance->SR1);
+  uint32_t itsources  = READ_REG(hi2c->Instance->CR2);
+  uint32_t error      = HAL_I2C_ERROR_NONE;
+  HAL_I2C_ModeTypeDef CurrentMode   = hi2c->Mode;
+
+  /* I2C Bus error interrupt occurred ----------------------------------------*/
+  if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_BERR) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERR) != RESET))
+  {
+    error |= HAL_I2C_ERROR_BERR;
+
+    /* Clear BERR flag */
+    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_BERR);
+  }
+
+  /* I2C Arbitration Lost error interrupt occurred ---------------------------*/
+  if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_ARLO) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERR) != RESET))
+  {
+    error |= HAL_I2C_ERROR_ARLO;
+
+    /* Clear ARLO flag */
+    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ARLO);
+  }
+
+  /* I2C Acknowledge failure error interrupt occurred ------------------------*/
+  if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_AF) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERR) != RESET))
+  {
+    tmp1 = CurrentMode;
+    tmp2 = hi2c->XferCount;
+    tmp3 = hi2c->State;
+    tmp4 = hi2c->PreviousState;
+    if ((tmp1 == HAL_I2C_MODE_SLAVE) && (tmp2 == 0U) && \
+        ((tmp3 == HAL_I2C_STATE_BUSY_TX) || (tmp3 == HAL_I2C_STATE_BUSY_TX_LISTEN) || \
+         ((tmp3 == HAL_I2C_STATE_LISTEN) && (tmp4 == I2C_STATE_SLAVE_BUSY_TX))))
+    {
+      I2C_Slave_AF(hi2c);
+    }
+    else
+    {
+      /* Clear AF flag */
+      __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+
+      error |= HAL_I2C_ERROR_AF;
+
+      /* Do not generate a STOP in case of Slave receive non acknowledge during transfer (mean not at the end of transfer) */
+      if ((CurrentMode == HAL_I2C_MODE_MASTER) || (CurrentMode == HAL_I2C_MODE_MEM))
+      {
+        /* Generate Stop */
+        SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
+      }
+    }
+  }
+
+  /* I2C Over-Run/Under-Run interrupt occurred -------------------------------*/
+  if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_OVR) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERR) != RESET))
+  {
+    error |= HAL_I2C_ERROR_OVR;
+    /* Clear OVR flag */
+    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_OVR);
+  }
+
+  /* Call the Error Callback in case of Error detected -----------------------*/
+  if (error != HAL_I2C_ERROR_NONE)
+  {
+    hi2c->ErrorCode |= error;
+    I2C_ITError(hi2c);
+  }
+}
+
+/**
+  * @brief  Master Tx Transfer completed callback.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @retval None
+  */
+__weak void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hi2c);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_I2C_MasterTxCpltCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Master Rx Transfer completed callback.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @retval None
+  */
+__weak void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hi2c);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_I2C_MasterRxCpltCallback could be implemented in the user file
+   */
+}
+
+/** @brief  Slave Tx Transfer completed callback.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @retval None
+  */
+__weak void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hi2c);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_I2C_SlaveTxCpltCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Slave Rx Transfer completed callback.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @retval None
+  */
+__weak void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hi2c);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_I2C_SlaveRxCpltCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Slave Address Match callback.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  TransferDirection Master request Transfer Direction (Write/Read), value of @ref I2C_XferDirection_definition
+  * @param  AddrMatchCode Address Match Code
+  * @retval None
+  */
+__weak void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hi2c);
+  UNUSED(TransferDirection);
+  UNUSED(AddrMatchCode);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_I2C_AddrCallback() could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Listen Complete callback.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @retval None
+  */
+__weak void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hi2c);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_I2C_ListenCpltCallback() could be implemented in the user file
+  */
+}
+
+/**
+  * @brief  Memory Tx Transfer completed callback.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @retval None
+  */
+__weak void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hi2c);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_I2C_MemTxCpltCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Memory Rx Transfer completed callback.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @retval None
+  */
+__weak void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hi2c);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_I2C_MemRxCpltCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  I2C error callback.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @retval None
+  */
+__weak void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hi2c);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_I2C_ErrorCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  I2C abort callback.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @retval None
+  */
+__weak void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hi2c);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_I2C_AbortCpltCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions
+ *  @brief   Peripheral State, Mode and Error functions
+  *
+@verbatim
+ ===============================================================================
+            ##### Peripheral State, Mode and Error functions #####
+ ===============================================================================
+    [..]
+    This subsection permit to get in run-time the status of the peripheral
+    and the data flow.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Return the I2C handle state.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @retval HAL state
+  */
+HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c)
+{
+  /* Return I2C handle state */
+  return hi2c->State;
+}
+
+/**
+  * @brief  Returns the I2C Master, Slave, Memory or no mode.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *         the configuration information for I2C module
+  * @retval HAL mode
+  */
+HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c)
+{
+  return hi2c->Mode;
+}
+
+/**
+  * @brief  Return the I2C error code.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *              the configuration information for the specified I2C.
+  * @retval I2C Error Code
+  */
+uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c)
+{
+  return hi2c->ErrorCode;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup I2C_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Handle TXE flag for Master
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *         the configuration information for I2C module
+  * @retval None
+  */
+static void I2C_MasterTransmit_TXE(I2C_HandleTypeDef *hi2c)
+{
+  /* Declaration of temporary variables to prevent undefined behavior of volatile usage */
+  HAL_I2C_StateTypeDef CurrentState = hi2c->State;
+  HAL_I2C_ModeTypeDef CurrentMode   = hi2c->Mode;
+  uint32_t CurrentXferOptions       = hi2c->XferOptions;
+
+  if ((hi2c->XferSize == 0U) && (CurrentState == HAL_I2C_STATE_BUSY_TX))
+  {
+    /* Call TxCpltCallback() directly if no stop mode is set */
+    if ((CurrentXferOptions != I2C_FIRST_AND_LAST_FRAME) && (CurrentXferOptions != I2C_LAST_FRAME) && (CurrentXferOptions != I2C_NO_OPTION_FRAME))
+    {
+      __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
+
+      hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX;
+      hi2c->Mode = HAL_I2C_MODE_NONE;
+      hi2c->State = HAL_I2C_STATE_READY;
+
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+      hi2c->MasterTxCpltCallback(hi2c);
+#else
+      HAL_I2C_MasterTxCpltCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+    }
+    else /* Generate Stop condition then Call TxCpltCallback() */
+    {
+      /* Disable EVT, BUF and ERR interrupt */
+      __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
+
+      /* Generate Stop */
+      SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
+
+      hi2c->PreviousState = I2C_STATE_NONE;
+      hi2c->State = HAL_I2C_STATE_READY;
+
+      if (hi2c->Mode == HAL_I2C_MODE_MEM)
+      {
+        hi2c->Mode = HAL_I2C_MODE_NONE;
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+        hi2c->MemTxCpltCallback(hi2c);
+#else
+        HAL_I2C_MemTxCpltCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+      }
+      else
+      {
+        hi2c->Mode = HAL_I2C_MODE_NONE;
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+        hi2c->MasterTxCpltCallback(hi2c);
+#else
+        HAL_I2C_MasterTxCpltCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+      }
+    }
+  }
+  else if ((CurrentState == HAL_I2C_STATE_BUSY_TX) || \
+           ((CurrentMode == HAL_I2C_MODE_MEM) && (CurrentState == HAL_I2C_STATE_BUSY_RX)))
+  {
+    if (hi2c->XferCount == 0U)
+    {
+      /* Disable BUF interrupt */
+      __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF);
+    }
+    else
+    {
+      if (hi2c->Mode == HAL_I2C_MODE_MEM)
+      {
+        I2C_MemoryTransmit_TXE_BTF(hi2c);
+      }
+      else
+      {
+        /* Write data to DR */
+        hi2c->Instance->DR = *hi2c->pBuffPtr;
+
+        /* Increment Buffer pointer */
+        hi2c->pBuffPtr++;
+
+        /* Update counter */
+        hi2c->XferCount--;
+      }
+    }
+  }
+  else
+  {
+    /* Do nothing */
+  }
+}
+
+/**
+  * @brief  Handle BTF flag for Master transmitter
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *         the configuration information for I2C module
+  * @retval None
+  */
+static void I2C_MasterTransmit_BTF(I2C_HandleTypeDef *hi2c)
+{
+  /* Declaration of temporary variables to prevent undefined behavior of volatile usage */
+  uint32_t CurrentXferOptions = hi2c->XferOptions;
+
+  if (hi2c->State == HAL_I2C_STATE_BUSY_TX)
+  {
+    if (hi2c->XferCount != 0U)
+    {
+      /* Write data to DR */
+      hi2c->Instance->DR = *hi2c->pBuffPtr;
+
+      /* Increment Buffer pointer */
+      hi2c->pBuffPtr++;
+
+      /* Update counter */
+      hi2c->XferCount--;
+    }
+    else
+    {
+      /* Call TxCpltCallback() directly if no stop mode is set */
+      if ((CurrentXferOptions != I2C_FIRST_AND_LAST_FRAME) && (CurrentXferOptions != I2C_LAST_FRAME) && (CurrentXferOptions != I2C_NO_OPTION_FRAME))
+      {
+        __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
+
+        hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX;
+        hi2c->Mode = HAL_I2C_MODE_NONE;
+        hi2c->State = HAL_I2C_STATE_READY;
+
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+        hi2c->MasterTxCpltCallback(hi2c);
+#else
+        HAL_I2C_MasterTxCpltCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+      }
+      else /* Generate Stop condition then Call TxCpltCallback() */
+      {
+        /* Disable EVT, BUF and ERR interrupt */
+        __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
+
+        /* Generate Stop */
+        SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
+
+        hi2c->PreviousState = I2C_STATE_NONE;
+        hi2c->State = HAL_I2C_STATE_READY;
+        if (hi2c->Mode == HAL_I2C_MODE_MEM)
+        {
+          hi2c->Mode = HAL_I2C_MODE_NONE;
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+          hi2c->MemTxCpltCallback(hi2c);
+#else
+          HAL_I2C_MemTxCpltCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+        }
+        else
+        {
+          hi2c->Mode = HAL_I2C_MODE_NONE;
+
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+          hi2c->MasterTxCpltCallback(hi2c);
+#else
+          HAL_I2C_MasterTxCpltCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+        }
+      }
+    }
+  }
+  else
+  {
+    /* Do nothing */
+  }
+}
+
+/**
+  * @brief  Handle TXE and BTF flag for Memory transmitter
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *         the configuration information for I2C module
+  * @retval None
+  */
+static void I2C_MemoryTransmit_TXE_BTF(I2C_HandleTypeDef *hi2c)
+{
+  /* Declaration of temporary variables to prevent undefined behavior of volatile usage */
+  HAL_I2C_StateTypeDef CurrentState = hi2c->State;
+
+  if (hi2c->EventCount == 0U)
+  {
+    /* If Memory address size is 8Bit */
+    if (hi2c->MemaddSize == I2C_MEMADD_SIZE_8BIT)
+    {
+      /* Send Memory Address */
+      hi2c->Instance->DR = I2C_MEM_ADD_LSB(hi2c->Memaddress);
+
+      hi2c->EventCount += 2U;
+    }
+    /* If Memory address size is 16Bit */
+    else
+    {
+      /* Send MSB of Memory Address */
+      hi2c->Instance->DR = I2C_MEM_ADD_MSB(hi2c->Memaddress);
+
+      hi2c->EventCount++;
+    }
+  }
+  else if (hi2c->EventCount == 1U)
+  {
+    /* Send LSB of Memory Address */
+    hi2c->Instance->DR = I2C_MEM_ADD_LSB(hi2c->Memaddress);
+
+    hi2c->EventCount++;
+  }
+  else if (hi2c->EventCount == 2U)
+  {
+    if (CurrentState == HAL_I2C_STATE_BUSY_RX)
+    {
+      /* Generate Restart */
+      hi2c->Instance->CR1 |= I2C_CR1_START;
+
+      hi2c->EventCount++;
+    }
+    else if ((hi2c->XferCount > 0U) && (CurrentState == HAL_I2C_STATE_BUSY_TX))
+    {
+      /* Write data to DR */
+      hi2c->Instance->DR = *hi2c->pBuffPtr;
+
+      /* Increment Buffer pointer */
+      hi2c->pBuffPtr++;
+
+      /* Update counter */
+      hi2c->XferCount--;
+    }
+    else if ((hi2c->XferCount == 0U) && (CurrentState == HAL_I2C_STATE_BUSY_TX))
+    {
+      /* Generate Stop condition then Call TxCpltCallback() */
+      /* Disable EVT, BUF and ERR interrupt */
+      __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
+
+      /* Generate Stop */
+      SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
+
+      hi2c->PreviousState = I2C_STATE_NONE;
+      hi2c->State = HAL_I2C_STATE_READY;
+      hi2c->Mode = HAL_I2C_MODE_NONE;
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+      hi2c->MemTxCpltCallback(hi2c);
+#else
+      HAL_I2C_MemTxCpltCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+    }
+    else
+    {
+      /* Do nothing */
+    }
+  }
+  else
+  {
+    /* Do nothing */
+  }
+}
+
+/**
+  * @brief  Handle RXNE flag for Master
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *         the configuration information for I2C module
+  * @retval None
+  */
+static void I2C_MasterReceive_RXNE(I2C_HandleTypeDef *hi2c)
+{
+  if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
+  {
+    uint32_t tmp;
+
+    tmp = hi2c->XferCount;
+    if (tmp > 3U)
+    {
+      /* Read data from DR */
+      *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
+
+      /* Increment Buffer pointer */
+      hi2c->pBuffPtr++;
+
+      /* Update counter */
+      hi2c->XferCount--;
+
+      if (hi2c->XferCount == (uint16_t)3)
+      {
+        /* Disable BUF interrupt, this help to treat correctly the last 4 bytes
+        on BTF subroutine */
+        /* Disable BUF interrupt */
+        __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF);
+      }
+    }
+    else if ((hi2c->XferOptions != I2C_FIRST_AND_NEXT_FRAME) && ((tmp == 1U) || (tmp == 0U)))
+    {
+      if (I2C_WaitOnSTOPRequestThroughIT(hi2c) == HAL_OK)
+      {
+        /* Disable Acknowledge */
+        CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
+
+        /* Disable EVT, BUF and ERR interrupt */
+        __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
+
+        /* Read data from DR */
+        *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
+
+        /* Increment Buffer pointer */
+        hi2c->pBuffPtr++;
+
+        /* Update counter */
+        hi2c->XferCount--;
+
+        hi2c->State = HAL_I2C_STATE_READY;
+
+        if (hi2c->Mode == HAL_I2C_MODE_MEM)
+        {
+          hi2c->Mode = HAL_I2C_MODE_NONE;
+          hi2c->PreviousState = I2C_STATE_NONE;
+
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+          hi2c->MemRxCpltCallback(hi2c);
+#else
+          HAL_I2C_MemRxCpltCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+        }
+        else
+        {
+          hi2c->Mode = HAL_I2C_MODE_NONE;
+          hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;
+
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+          hi2c->MasterRxCpltCallback(hi2c);
+#else
+          HAL_I2C_MasterRxCpltCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+        }
+      }
+      else
+      {
+        /* Disable EVT, BUF and ERR interrupt */
+        __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
+
+        /* Read data from DR */
+        *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
+
+        /* Increment Buffer pointer */
+        hi2c->pBuffPtr++;
+
+        /* Update counter */
+        hi2c->XferCount--;
+
+        hi2c->State = HAL_I2C_STATE_READY;
+        hi2c->Mode = HAL_I2C_MODE_NONE;
+
+        /* Call user error callback */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+        hi2c->ErrorCallback(hi2c);
+#else
+        HAL_I2C_ErrorCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+      }
+    }
+    else
+    {
+      /* Disable BUF interrupt, this help to treat correctly the last 2 bytes
+         on BTF subroutine if there is a reception delay between N-1 and N byte */
+      __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF);
+    }
+  }
+}
+
+/**
+  * @brief  Handle BTF flag for Master receiver
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *         the configuration information for I2C module
+  * @retval None
+  */
+static void I2C_MasterReceive_BTF(I2C_HandleTypeDef *hi2c)
+{
+  /* Declaration of temporary variables to prevent undefined behavior of volatile usage */
+  uint32_t CurrentXferOptions = hi2c->XferOptions;
+
+  if (hi2c->XferCount == 4U)
+  {
+    /* Disable BUF interrupt, this help to treat correctly the last 2 bytes
+       on BTF subroutine if there is a reception delay between N-1 and N byte */
+    __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF);
+
+    /* Read data from DR */
+    *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
+
+    /* Increment Buffer pointer */
+    hi2c->pBuffPtr++;
+
+    /* Update counter */
+    hi2c->XferCount--;
+  }
+  else if (hi2c->XferCount == 3U)
+  {
+    /* Disable BUF interrupt, this help to treat correctly the last 2 bytes
+       on BTF subroutine if there is a reception delay between N-1 and N byte */
+    __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF);
+
+    if ((CurrentXferOptions != I2C_NEXT_FRAME) && (CurrentXferOptions != I2C_FIRST_AND_NEXT_FRAME))
+    {
+      /* Disable Acknowledge */
+      CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
+    }
+
+    /* Read data from DR */
+    *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
+
+    /* Increment Buffer pointer */
+    hi2c->pBuffPtr++;
+
+    /* Update counter */
+    hi2c->XferCount--;
+  }
+  else if (hi2c->XferCount == 2U)
+  {
+    /* Prepare next transfer or stop current transfer */
+    if ((CurrentXferOptions == I2C_FIRST_FRAME) || (CurrentXferOptions == I2C_LAST_FRAME_NO_STOP))
+    {
+      /* Disable Acknowledge */
+      CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
+    }
+    else if ((CurrentXferOptions == I2C_NEXT_FRAME) || (CurrentXferOptions == I2C_FIRST_AND_NEXT_FRAME))
+    {
+      /* Enable Acknowledge */
+      SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
+    }
+    else if (CurrentXferOptions != I2C_LAST_FRAME_NO_STOP)
+    {
+      /* Generate Stop */
+      SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
+    }
+    else
+    {
+      /* Do nothing */
+    }
+
+    /* Read data from DR */
+    *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
+
+    /* Increment Buffer pointer */
+    hi2c->pBuffPtr++;
+
+    /* Update counter */
+    hi2c->XferCount--;
+
+    /* Read data from DR */
+    *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
+
+    /* Increment Buffer pointer */
+    hi2c->pBuffPtr++;
+
+    /* Update counter */
+    hi2c->XferCount--;
+
+    /* Disable EVT and ERR interrupt */
+    __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
+
+    hi2c->State = HAL_I2C_STATE_READY;
+    if (hi2c->Mode == HAL_I2C_MODE_MEM)
+    {
+      hi2c->Mode = HAL_I2C_MODE_NONE;
+      hi2c->PreviousState = I2C_STATE_NONE;
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+      hi2c->MemRxCpltCallback(hi2c);
+#else
+      HAL_I2C_MemRxCpltCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+    }
+    else
+    {
+      hi2c->Mode = HAL_I2C_MODE_NONE;
+      hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+      hi2c->MasterRxCpltCallback(hi2c);
+#else
+      HAL_I2C_MasterRxCpltCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+    }
+  }
+  else
+  {
+    /* Read data from DR */
+    *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
+
+    /* Increment Buffer pointer */
+    hi2c->pBuffPtr++;
+
+    /* Update counter */
+    hi2c->XferCount--;
+  }
+}
+
+/**
+  * @brief  Handle SB flag for Master
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *         the configuration information for I2C module
+  * @retval None
+  */
+static void I2C_Master_SB(I2C_HandleTypeDef *hi2c)
+{
+  if (hi2c->Mode == HAL_I2C_MODE_MEM)
+  {
+    if (hi2c->EventCount == 0U)
+    {
+      /* Send slave address */
+      hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(hi2c->Devaddress);
+    }
+    else
+    {
+      hi2c->Instance->DR = I2C_7BIT_ADD_READ(hi2c->Devaddress);
+    }
+  }
+  else
+  {
+    if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT)
+    {
+      /* Send slave 7 Bits address */
+      if (hi2c->State == HAL_I2C_STATE_BUSY_TX)
+      {
+        hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(hi2c->Devaddress);
+      }
+      else
+      {
+        hi2c->Instance->DR = I2C_7BIT_ADD_READ(hi2c->Devaddress);
+      }
+
+      if (((hi2c->hdmatx != NULL) && (hi2c->hdmatx->XferCpltCallback != NULL))
+          || ((hi2c->hdmarx != NULL) && (hi2c->hdmarx->XferCpltCallback != NULL)))
+      {
+        /* Enable DMA Request */
+        SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
+      }
+    }
+    else
+    {
+      if (hi2c->EventCount == 0U)
+      {
+        /* Send header of slave address */
+        hi2c->Instance->DR = I2C_10BIT_HEADER_WRITE(hi2c->Devaddress);
+      }
+      else if (hi2c->EventCount == 1U)
+      {
+        /* Send header of slave address */
+        hi2c->Instance->DR = I2C_10BIT_HEADER_READ(hi2c->Devaddress);
+      }
+      else
+      {
+        /* Do nothing */
+      }
+    }
+  }
+}
+
+/**
+  * @brief  Handle ADD10 flag for Master
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *         the configuration information for I2C module
+  * @retval None
+  */
+static void I2C_Master_ADD10(I2C_HandleTypeDef *hi2c)
+{
+  /* Send slave address */
+  hi2c->Instance->DR = I2C_10BIT_ADDRESS(hi2c->Devaddress);
+
+  if (((hi2c->hdmatx != NULL) && (hi2c->hdmatx->XferCpltCallback != NULL))
+      || ((hi2c->hdmarx != NULL) && (hi2c->hdmarx->XferCpltCallback != NULL)))
+  {
+    /* Enable DMA Request */
+    SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
+  }
+}
+
+/**
+  * @brief  Handle ADDR flag for Master
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *         the configuration information for I2C module
+  * @retval None
+  */
+static void I2C_Master_ADDR(I2C_HandleTypeDef *hi2c)
+{
+  /* Declaration of temporary variable to prevent undefined behavior of volatile usage */
+  HAL_I2C_ModeTypeDef CurrentMode       = hi2c->Mode;
+  uint32_t CurrentXferOptions           = hi2c->XferOptions;
+  uint32_t Prev_State                   = hi2c->PreviousState;
+
+  if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
+  {
+    if ((hi2c->EventCount == 0U) && (CurrentMode == HAL_I2C_MODE_MEM))
+    {
+      /* Clear ADDR flag */
+      __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
+    }
+    else if ((hi2c->EventCount == 0U) && (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT))
+    {
+      /* Clear ADDR flag */
+      __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
+
+      /* Generate Restart */
+      SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
+
+      hi2c->EventCount++;
+    }
+    else
+    {
+      if (hi2c->XferCount == 0U)
+      {
+        /* Clear ADDR flag */
+        __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
+
+        /* Generate Stop */
+        SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
+      }
+      else if (hi2c->XferCount == 1U)
+      {
+        if (CurrentXferOptions == I2C_NO_OPTION_FRAME)
+        {
+          /* Disable Acknowledge */
+          CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
+
+          if ((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN)
+          {
+            /* Disable Acknowledge */
+            CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
+
+            /* Clear ADDR flag */
+            __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
+          }
+          else
+          {
+            /* Clear ADDR flag */
+            __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
+
+            /* Generate Stop */
+            SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
+          }
+        }
+        /* Prepare next transfer or stop current transfer */
+        else if ((CurrentXferOptions != I2C_FIRST_AND_LAST_FRAME) && (CurrentXferOptions != I2C_LAST_FRAME) \
+                 && ((Prev_State != I2C_STATE_MASTER_BUSY_RX) || (CurrentXferOptions == I2C_FIRST_FRAME)))
+        {
+          if ((CurrentXferOptions != I2C_NEXT_FRAME) && (CurrentXferOptions != I2C_FIRST_AND_NEXT_FRAME) && (CurrentXferOptions != I2C_LAST_FRAME_NO_STOP))
+          {
+            /* Disable Acknowledge */
+            CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
+          }
+          else
+          {
+            /* Enable Acknowledge */
+            SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
+          }
+
+          /* Clear ADDR flag */
+          __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
+        }
+        else
+        {
+          /* Disable Acknowledge */
+          CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
+
+          /* Clear ADDR flag */
+          __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
+
+          /* Generate Stop */
+          SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
+        }
+      }
+      else if (hi2c->XferCount == 2U)
+      {
+        if ((CurrentXferOptions != I2C_NEXT_FRAME) && (CurrentXferOptions != I2C_FIRST_AND_NEXT_FRAME) && (CurrentXferOptions != I2C_LAST_FRAME_NO_STOP))
+        {
+          /* Disable Acknowledge */
+          CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
+
+          /* Enable Pos */
+          SET_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
+        }
+        else
+        {
+          /* Enable Acknowledge */
+          SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
+        }
+
+        if (((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN) && ((CurrentXferOptions == I2C_NO_OPTION_FRAME) || (CurrentXferOptions == I2C_FIRST_FRAME) || (CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_LAST_FRAME_NO_STOP) || (CurrentXferOptions == I2C_LAST_FRAME)))
+        {
+          /* Enable Last DMA bit */
+          SET_BIT(hi2c->Instance->CR2, I2C_CR2_LAST);
+        }
+
+        /* Clear ADDR flag */
+        __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
+      }
+      else
+      {
+        /* Enable Acknowledge */
+        SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
+
+        if (((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN) && ((CurrentXferOptions == I2C_NO_OPTION_FRAME) || (CurrentXferOptions == I2C_FIRST_FRAME) || (CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_LAST_FRAME_NO_STOP) || (CurrentXferOptions == I2C_LAST_FRAME)))
+        {
+          /* Enable Last DMA bit */
+          SET_BIT(hi2c->Instance->CR2, I2C_CR2_LAST);
+        }
+
+        /* Clear ADDR flag */
+        __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
+      }
+
+      /* Reset Event counter  */
+      hi2c->EventCount = 0U;
+    }
+  }
+  else
+  {
+    /* Clear ADDR flag */
+    __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
+  }
+}
+
+/**
+  * @brief  Handle TXE flag for Slave
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *         the configuration information for I2C module
+  * @retval None
+  */
+static void I2C_SlaveTransmit_TXE(I2C_HandleTypeDef *hi2c)
+{
+  /* Declaration of temporary variables to prevent undefined behavior of volatile usage */
+  HAL_I2C_StateTypeDef CurrentState = hi2c->State;
+
+  if (hi2c->XferCount != 0U)
+  {
+    /* Write data to DR */
+    hi2c->Instance->DR = *hi2c->pBuffPtr;
+
+    /* Increment Buffer pointer */
+    hi2c->pBuffPtr++;
+
+    /* Update counter */
+    hi2c->XferCount--;
+
+    if ((hi2c->XferCount == 0U) && (CurrentState == HAL_I2C_STATE_BUSY_TX_LISTEN))
+    {
+      /* Last Byte is received, disable Interrupt */
+      __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF);
+
+      /* Set state at HAL_I2C_STATE_LISTEN */
+      hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX;
+      hi2c->State = HAL_I2C_STATE_LISTEN;
+
+      /* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+      hi2c->SlaveTxCpltCallback(hi2c);
+#else
+      HAL_I2C_SlaveTxCpltCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+    }
+  }
+}
+
+/**
+  * @brief  Handle BTF flag for Slave transmitter
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *         the configuration information for I2C module
+  * @retval None
+  */
+static void I2C_SlaveTransmit_BTF(I2C_HandleTypeDef *hi2c)
+{
+  if (hi2c->XferCount != 0U)
+  {
+    /* Write data to DR */
+    hi2c->Instance->DR = *hi2c->pBuffPtr;
+
+    /* Increment Buffer pointer */
+    hi2c->pBuffPtr++;
+
+    /* Update counter */
+    hi2c->XferCount--;
+  }
+}
+
+/**
+  * @brief  Handle RXNE flag for Slave
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *         the configuration information for I2C module
+  * @retval None
+  */
+static void I2C_SlaveReceive_RXNE(I2C_HandleTypeDef *hi2c)
+{
+  /* Declaration of temporary variables to prevent undefined behavior of volatile usage */
+  HAL_I2C_StateTypeDef CurrentState = hi2c->State;
+
+  if (hi2c->XferCount != 0U)
+  {
+    /* Read data from DR */
+    *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
+
+    /* Increment Buffer pointer */
+    hi2c->pBuffPtr++;
+
+    /* Update counter */
+    hi2c->XferCount--;
+
+    if ((hi2c->XferCount == 0U) && (CurrentState == HAL_I2C_STATE_BUSY_RX_LISTEN))
+    {
+      /* Last Byte is received, disable Interrupt */
+      __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF);
+
+      /* Set state at HAL_I2C_STATE_LISTEN */
+      hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX;
+      hi2c->State = HAL_I2C_STATE_LISTEN;
+
+      /* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+      hi2c->SlaveRxCpltCallback(hi2c);
+#else
+      HAL_I2C_SlaveRxCpltCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+    }
+  }
+}
+
+/**
+  * @brief  Handle BTF flag for Slave receiver
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *         the configuration information for I2C module
+  * @retval None
+  */
+static void I2C_SlaveReceive_BTF(I2C_HandleTypeDef *hi2c)
+{
+  if (hi2c->XferCount != 0U)
+  {
+    /* Read data from DR */
+    *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
+
+    /* Increment Buffer pointer */
+    hi2c->pBuffPtr++;
+
+    /* Update counter */
+    hi2c->XferCount--;
+  }
+}
+
+/**
+  * @brief  Handle ADD flag for Slave
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *         the configuration information for I2C module
+  * @param  IT2Flags Interrupt2 flags to handle.
+  * @retval None
+  */
+static void I2C_Slave_ADDR(I2C_HandleTypeDef *hi2c, uint32_t IT2Flags)
+{
+  uint8_t TransferDirection = I2C_DIRECTION_RECEIVE;
+  uint16_t SlaveAddrCode;
+
+  if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
+  {
+    /* Disable BUF interrupt, BUF enabling is manage through slave specific interface */
+    __HAL_I2C_DISABLE_IT(hi2c, (I2C_IT_BUF));
+
+    /* Transfer Direction requested by Master */
+    if (I2C_CHECK_FLAG(IT2Flags, I2C_FLAG_TRA) == RESET)
+    {
+      TransferDirection = I2C_DIRECTION_TRANSMIT;
+    }
+
+    if (I2C_CHECK_FLAG(IT2Flags, I2C_FLAG_DUALF) == RESET)
+    {
+      SlaveAddrCode = (uint16_t)hi2c->Init.OwnAddress1;
+    }
+    else
+    {
+      SlaveAddrCode = (uint16_t)hi2c->Init.OwnAddress2;
+    }
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    /* Call Slave Addr callback */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+    hi2c->AddrCallback(hi2c, TransferDirection, SlaveAddrCode);
+#else
+    HAL_I2C_AddrCallback(hi2c, TransferDirection, SlaveAddrCode);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+  }
+  else
+  {
+    /* Clear ADDR flag */
+    __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+  }
+}
+
+/**
+  * @brief  Handle STOPF flag for Slave
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *         the configuration information for I2C module
+  * @retval None
+  */
+static void I2C_Slave_STOPF(I2C_HandleTypeDef *hi2c)
+{
+  /* Declaration of temporary variable to prevent undefined behavior of volatile usage */
+  HAL_I2C_StateTypeDef CurrentState = hi2c->State;
+
+  /* Disable EVT, BUF and ERR interrupt */
+  __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
+
+  /* Clear STOPF flag */
+  __HAL_I2C_CLEAR_STOPFLAG(hi2c);
+
+  /* Disable Acknowledge */
+  CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
+
+  /* If a DMA is ongoing, Update handle size context */
+  if ((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN)
+  {
+    if ((CurrentState == HAL_I2C_STATE_BUSY_RX) || (CurrentState == HAL_I2C_STATE_BUSY_RX_LISTEN))
+    {
+      hi2c->XferCount = (uint16_t)(__HAL_DMA_GET_COUNTER(hi2c->hdmarx));
+
+      if (hi2c->XferCount != 0U)
+      {
+        /* Set ErrorCode corresponding to a Non-Acknowledge */
+        hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
+      }
+
+      /* Disable, stop the current DMA */
+      CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
+
+      /* Abort DMA Xfer if any */
+      if (HAL_DMA_GetState(hi2c->hdmarx) != HAL_DMA_STATE_READY)
+      {
+        /* Set the I2C DMA Abort callback :
+        will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
+        hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;
+
+        /* Abort DMA RX */
+        if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
+        {
+          /* Call Directly XferAbortCallback function in case of error */
+          hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
+        }
+      }
+    }
+    else
+    {
+      hi2c->XferCount = (uint16_t)(__HAL_DMA_GET_COUNTER(hi2c->hdmatx));
+
+      if (hi2c->XferCount != 0U)
+      {
+        /* Set ErrorCode corresponding to a Non-Acknowledge */
+        hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
+      }
+
+      /* Disable, stop the current DMA */
+      CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
+
+      /* Abort DMA Xfer if any */
+      if (HAL_DMA_GetState(hi2c->hdmatx) != HAL_DMA_STATE_READY)
+      {
+        /* Set the I2C DMA Abort callback :
+        will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
+        hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;
+
+        /* Abort DMA TX */
+        if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
+        {
+          /* Call Directly XferAbortCallback function in case of error */
+          hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
+        }
+      }
+    }
+  }
+
+  /* All data are not transferred, so set error code accordingly */
+  if (hi2c->XferCount != 0U)
+  {
+    /* Store Last receive data if any */
+    if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET)
+    {
+      /* Read data from DR */
+      *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
+
+      /* Increment Buffer pointer */
+      hi2c->pBuffPtr++;
+
+      /* Update counter */
+      hi2c->XferCount--;
+    }
+
+    /* Store Last receive data if any */
+    if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET)
+    {
+      /* Read data from DR */
+      *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
+
+      /* Increment Buffer pointer */
+      hi2c->pBuffPtr++;
+
+      /* Update counter */
+      hi2c->XferCount--;
+    }
+
+    if (hi2c->XferCount != 0U)
+    {
+      /* Set ErrorCode corresponding to a Non-Acknowledge */
+      hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
+    }
+  }
+
+  if (hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
+  {
+    /* Call the corresponding callback to inform upper layer of End of Transfer */
+    I2C_ITError(hi2c);
+  }
+  else
+  {
+    if (CurrentState == HAL_I2C_STATE_BUSY_RX_LISTEN)
+    {
+      /* Set state at HAL_I2C_STATE_LISTEN */
+      hi2c->PreviousState = I2C_STATE_NONE;
+      hi2c->State = HAL_I2C_STATE_LISTEN;
+
+      /* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+      hi2c->SlaveRxCpltCallback(hi2c);
+#else
+      HAL_I2C_SlaveRxCpltCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+    }
+
+    if (hi2c->State == HAL_I2C_STATE_LISTEN)
+    {
+      hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+      hi2c->PreviousState = I2C_STATE_NONE;
+      hi2c->State = HAL_I2C_STATE_READY;
+      hi2c->Mode = HAL_I2C_MODE_NONE;
+
+      /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+      hi2c->ListenCpltCallback(hi2c);
+#else
+      HAL_I2C_ListenCpltCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+    }
+    else
+    {
+      if ((hi2c->PreviousState  == I2C_STATE_SLAVE_BUSY_RX) || (CurrentState == HAL_I2C_STATE_BUSY_RX))
+      {
+        hi2c->PreviousState = I2C_STATE_NONE;
+        hi2c->State = HAL_I2C_STATE_READY;
+        hi2c->Mode = HAL_I2C_MODE_NONE;
+
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+        hi2c->SlaveRxCpltCallback(hi2c);
+#else
+        HAL_I2C_SlaveRxCpltCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+      }
+    }
+  }
+}
+
+/**
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *         the configuration information for I2C module
+  * @retval None
+  */
+static void I2C_Slave_AF(I2C_HandleTypeDef *hi2c)
+{
+  /* Declaration of temporary variables to prevent undefined behavior of volatile usage */
+  HAL_I2C_StateTypeDef CurrentState = hi2c->State;
+  uint32_t CurrentXferOptions       = hi2c->XferOptions;
+
+  if (((CurrentXferOptions ==  I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_LAST_FRAME)) && \
+      (CurrentState == HAL_I2C_STATE_LISTEN))
+  {
+    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+
+    /* Disable EVT, BUF and ERR interrupt */
+    __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
+
+    /* Clear AF flag */
+    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+
+    /* Disable Acknowledge */
+    CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
+
+    hi2c->PreviousState = I2C_STATE_NONE;
+    hi2c->State         = HAL_I2C_STATE_READY;
+    hi2c->Mode          = HAL_I2C_MODE_NONE;
+
+    /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+    hi2c->ListenCpltCallback(hi2c);
+#else
+    HAL_I2C_ListenCpltCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+  }
+  else if (CurrentState == HAL_I2C_STATE_BUSY_TX)
+  {
+    hi2c->XferOptions   = I2C_NO_OPTION_FRAME;
+    hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX;
+    hi2c->State         = HAL_I2C_STATE_READY;
+    hi2c->Mode          = HAL_I2C_MODE_NONE;
+
+    /* Disable EVT, BUF and ERR interrupt */
+    __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
+
+    /* Clear AF flag */
+    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+
+    /* Disable Acknowledge */
+    CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
+
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+    hi2c->SlaveTxCpltCallback(hi2c);
+#else
+    HAL_I2C_SlaveTxCpltCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+  }
+  else
+  {
+    /* Clear AF flag only */
+    /* State Listen, but XferOptions == FIRST or NEXT */
+    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+  }
+}
+
+/**
+  * @brief  I2C interrupts error process
+  * @param  hi2c I2C handle.
+  * @retval None
+  */
+static void I2C_ITError(I2C_HandleTypeDef *hi2c)
+{
+  /* Declaration of temporary variable to prevent undefined behavior of volatile usage */
+  HAL_I2C_StateTypeDef CurrentState = hi2c->State;
+  HAL_I2C_ModeTypeDef CurrentMode = hi2c->Mode;
+  uint32_t CurrentError;
+
+  if (((CurrentMode == HAL_I2C_MODE_MASTER) || (CurrentMode == HAL_I2C_MODE_MEM)) && (CurrentState == HAL_I2C_STATE_BUSY_RX))
+  {
+    /* Disable Pos bit in I2C CR1 when error occurred in Master/Mem Receive IT Process */
+    hi2c->Instance->CR1 &= ~I2C_CR1_POS;
+  }
+
+  if (((uint32_t)CurrentState & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
+  {
+    /* keep HAL_I2C_STATE_LISTEN */
+    hi2c->PreviousState = I2C_STATE_NONE;
+    hi2c->State = HAL_I2C_STATE_LISTEN;
+  }
+  else
+  {
+    /* If state is an abort treatment on going, don't change state */
+    /* This change will be do later */
+    if ((READ_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN) != I2C_CR2_DMAEN) && (CurrentState != HAL_I2C_STATE_ABORT))
+    {
+      hi2c->State = HAL_I2C_STATE_READY;
+      hi2c->Mode = HAL_I2C_MODE_NONE;
+    }
+    hi2c->PreviousState = I2C_STATE_NONE;
+  }
+
+  /* Abort DMA transfer */
+  if (READ_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN) == I2C_CR2_DMAEN)
+  {
+    hi2c->Instance->CR2 &= ~I2C_CR2_DMAEN;
+
+    if (hi2c->hdmatx->State != HAL_DMA_STATE_READY)
+    {
+      /* Set the DMA Abort callback :
+      will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
+      hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;
+
+      if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
+      {
+        /* Disable I2C peripheral to prevent dummy data in buffer */
+        __HAL_I2C_DISABLE(hi2c);
+
+        hi2c->State = HAL_I2C_STATE_READY;
+
+        /* Call Directly XferAbortCallback function in case of error */
+        hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
+      }
+    }
+    else
+    {
+      /* Set the DMA Abort callback :
+      will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
+      hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;
+
+      if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
+      {
+        /* Store Last receive data if any */
+        if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET)
+        {
+          /* Read data from DR */
+          *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
+
+          /* Increment Buffer pointer */
+          hi2c->pBuffPtr++;
+        }
+
+        /* Disable I2C peripheral to prevent dummy data in buffer */
+        __HAL_I2C_DISABLE(hi2c);
+
+        hi2c->State = HAL_I2C_STATE_READY;
+
+        /* Call Directly hi2c->hdmarx->XferAbortCallback function in case of error */
+        hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
+      }
+    }
+  }
+  else if (hi2c->State == HAL_I2C_STATE_ABORT)
+  {
+    hi2c->State = HAL_I2C_STATE_READY;
+    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+    /* Store Last receive data if any */
+    if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET)
+    {
+      /* Read data from DR */
+      *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
+
+      /* Increment Buffer pointer */
+      hi2c->pBuffPtr++;
+    }
+
+    /* Disable I2C peripheral to prevent dummy data in buffer */
+    __HAL_I2C_DISABLE(hi2c);
+
+    /* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+    hi2c->AbortCpltCallback(hi2c);
+#else
+    HAL_I2C_AbortCpltCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+  }
+  else
+  {
+    /* Store Last receive data if any */
+    if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET)
+    {
+      /* Read data from DR */
+      *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
+
+      /* Increment Buffer pointer */
+      hi2c->pBuffPtr++;
+    }
+
+    /* Call user error callback */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+    hi2c->ErrorCallback(hi2c);
+#else
+    HAL_I2C_ErrorCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+  }
+
+  /* STOP Flag is not set after a NACK reception, BusError, ArbitrationLost, OverRun */
+  CurrentError = hi2c->ErrorCode;
+
+  if (((CurrentError & HAL_I2C_ERROR_BERR) == HAL_I2C_ERROR_BERR) || \
+      ((CurrentError & HAL_I2C_ERROR_ARLO) == HAL_I2C_ERROR_ARLO) || \
+      ((CurrentError & HAL_I2C_ERROR_AF) == HAL_I2C_ERROR_AF)     || \
+      ((CurrentError & HAL_I2C_ERROR_OVR) == HAL_I2C_ERROR_OVR))
+  {
+    /* Disable EVT, BUF and ERR interrupt */
+    __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
+  }
+
+  /* So may inform upper layer that listen phase is stopped */
+  /* during NACK error treatment */
+  CurrentState = hi2c->State;
+  if (((hi2c->ErrorCode & HAL_I2C_ERROR_AF) == HAL_I2C_ERROR_AF) && (CurrentState == HAL_I2C_STATE_LISTEN))
+  {
+    hi2c->XferOptions   = I2C_NO_OPTION_FRAME;
+    hi2c->PreviousState = I2C_STATE_NONE;
+    hi2c->State         = HAL_I2C_STATE_READY;
+    hi2c->Mode          = HAL_I2C_MODE_NONE;
+
+    /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+    hi2c->ListenCpltCallback(hi2c);
+#else
+    HAL_I2C_ListenCpltCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+  }
+}
+
+/**
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *         the configuration information for I2C module
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shifted to the left before calling the interface
+  * @param  Timeout Timeout duration
+  * @param  Tickstart Tick start value
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef I2C_MasterRequestWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout, uint32_t Tickstart)
+{
+  /* Declaration of temporary variable to prevent undefined behavior of volatile usage */
+  uint32_t CurrentXferOptions = hi2c->XferOptions;
+
+  /* Generate Start condition if first transfer */
+  if ((CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_FIRST_FRAME) || (CurrentXferOptions == I2C_NO_OPTION_FRAME))
+  {
+    /* Generate Start */
+    SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
+  }
+  else if (hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX)
+  {
+    /* Generate ReStart */
+    SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
+  }
+  else
+  {
+    /* Do nothing */
+  }
+
+  /* Wait until SB flag is set */
+  if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK)
+  {
+    if (READ_BIT(hi2c->Instance->CR1, I2C_CR1_START) == I2C_CR1_START)
+    {
+      hi2c->ErrorCode = HAL_I2C_WRONG_START;
+    }
+    return HAL_TIMEOUT;
+  }
+
+  if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT)
+  {
+    /* Send slave address */
+    hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(DevAddress);
+  }
+  else
+  {
+    /* Send header of slave address */
+    hi2c->Instance->DR = I2C_10BIT_HEADER_WRITE(DevAddress);
+
+    /* Wait until ADD10 flag is set */
+    if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADD10, Timeout, Tickstart) != HAL_OK)
+    {
+      return HAL_ERROR;
+    }
+
+    /* Send slave address */
+    hi2c->Instance->DR = I2C_10BIT_ADDRESS(DevAddress);
+  }
+
+  /* Wait until ADDR flag is set */
+  if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK)
+  {
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Master sends target device address for read request.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *         the configuration information for I2C module
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shifted to the left before calling the interface
+  * @param  Timeout Timeout duration
+  * @param  Tickstart Tick start value
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef I2C_MasterRequestRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout, uint32_t Tickstart)
+{
+  /* Declaration of temporary variable to prevent undefined behavior of volatile usage */
+  uint32_t CurrentXferOptions = hi2c->XferOptions;
+
+  /* Enable Acknowledge */
+  SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
+
+  /* Generate Start condition if first transfer */
+  if ((CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_FIRST_FRAME)  || (CurrentXferOptions == I2C_NO_OPTION_FRAME))
+  {
+    /* Generate Start */
+    SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
+  }
+  else if (hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX)
+  {
+    /* Generate ReStart */
+    SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
+  }
+  else
+  {
+    /* Do nothing */
+  }
+
+  /* Wait until SB flag is set */
+  if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK)
+  {
+    if (READ_BIT(hi2c->Instance->CR1, I2C_CR1_START) == I2C_CR1_START)
+    {
+      hi2c->ErrorCode = HAL_I2C_WRONG_START;
+    }
+    return HAL_TIMEOUT;
+  }
+
+  if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT)
+  {
+    /* Send slave address */
+    hi2c->Instance->DR = I2C_7BIT_ADD_READ(DevAddress);
+  }
+  else
+  {
+    /* Send header of slave address */
+    hi2c->Instance->DR = I2C_10BIT_HEADER_WRITE(DevAddress);
+
+    /* Wait until ADD10 flag is set */
+    if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADD10, Timeout, Tickstart) != HAL_OK)
+    {
+      return HAL_ERROR;
+    }
+
+    /* Send slave address */
+    hi2c->Instance->DR = I2C_10BIT_ADDRESS(DevAddress);
+
+    /* Wait until ADDR flag is set */
+    if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK)
+    {
+      return HAL_ERROR;
+    }
+
+    /* Clear ADDR flag */
+    __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
+
+    /* Generate Restart */
+    SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
+
+    /* Wait until SB flag is set */
+    if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK)
+    {
+      if (READ_BIT(hi2c->Instance->CR1, I2C_CR1_START) == I2C_CR1_START)
+      {
+        hi2c->ErrorCode = HAL_I2C_WRONG_START;
+      }
+      return HAL_TIMEOUT;
+    }
+
+    /* Send header of slave address */
+    hi2c->Instance->DR = I2C_10BIT_HEADER_READ(DevAddress);
+  }
+
+  /* Wait until ADDR flag is set */
+  if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK)
+  {
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Master sends target device address followed by internal memory address for write request.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *         the configuration information for I2C module
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shifted to the left before calling the interface
+  * @param  MemAddress Internal memory address
+  * @param  MemAddSize Size of internal memory address
+  * @param  Timeout Timeout duration
+  * @param  Tickstart Tick start value
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart)
+{
+  /* Generate Start */
+  SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
+
+  /* Wait until SB flag is set */
+  if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK)
+  {
+    if (READ_BIT(hi2c->Instance->CR1, I2C_CR1_START) == I2C_CR1_START)
+    {
+      hi2c->ErrorCode = HAL_I2C_WRONG_START;
+    }
+    return HAL_TIMEOUT;
+  }
+
+  /* Send slave address */
+  hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(DevAddress);
+
+  /* Wait until ADDR flag is set */
+  if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Clear ADDR flag */
+  __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
+
+  /* Wait until TXE flag is set */
+  if (I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
+  {
+    if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+    {
+      /* Generate Stop */
+      SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
+    }
+    return HAL_ERROR;
+  }
+
+  /* If Memory address size is 8Bit */
+  if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
+  {
+    /* Send Memory Address */
+    hi2c->Instance->DR = I2C_MEM_ADD_LSB(MemAddress);
+  }
+  /* If Memory address size is 16Bit */
+  else
+  {
+    /* Send MSB of Memory Address */
+    hi2c->Instance->DR = I2C_MEM_ADD_MSB(MemAddress);
+
+    /* Wait until TXE flag is set */
+    if (I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
+    {
+      if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+      {
+        /* Generate Stop */
+        SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
+      }
+      return HAL_ERROR;
+    }
+
+    /* Send LSB of Memory Address */
+    hi2c->Instance->DR = I2C_MEM_ADD_LSB(MemAddress);
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Master sends target device address followed by internal memory address for read request.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *         the configuration information for I2C module
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shifted to the left before calling the interface
+  * @param  MemAddress Internal memory address
+  * @param  MemAddSize Size of internal memory address
+  * @param  Timeout Timeout duration
+  * @param  Tickstart Tick start value
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart)
+{
+  /* Enable Acknowledge */
+  SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
+
+  /* Generate Start */
+  SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
+
+  /* Wait until SB flag is set */
+  if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK)
+  {
+    if (READ_BIT(hi2c->Instance->CR1, I2C_CR1_START) == I2C_CR1_START)
+    {
+      hi2c->ErrorCode = HAL_I2C_WRONG_START;
+    }
+    return HAL_TIMEOUT;
+  }
+
+  /* Send slave address */
+  hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(DevAddress);
+
+  /* Wait until ADDR flag is set */
+  if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Clear ADDR flag */
+  __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
+
+  /* Wait until TXE flag is set */
+  if (I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
+  {
+    if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+    {
+      /* Generate Stop */
+      SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
+    }
+    return HAL_ERROR;
+  }
+
+  /* If Memory address size is 8Bit */
+  if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
+  {
+    /* Send Memory Address */
+    hi2c->Instance->DR = I2C_MEM_ADD_LSB(MemAddress);
+  }
+  /* If Memory address size is 16Bit */
+  else
+  {
+    /* Send MSB of Memory Address */
+    hi2c->Instance->DR = I2C_MEM_ADD_MSB(MemAddress);
+
+    /* Wait until TXE flag is set */
+    if (I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
+    {
+      if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+      {
+        /* Generate Stop */
+        SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
+      }
+      return HAL_ERROR;
+    }
+
+    /* Send LSB of Memory Address */
+    hi2c->Instance->DR = I2C_MEM_ADD_LSB(MemAddress);
+  }
+
+  /* Wait until TXE flag is set */
+  if (I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
+  {
+    if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+    {
+      /* Generate Stop */
+      SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
+    }
+    return HAL_ERROR;
+  }
+
+  /* Generate Restart */
+  SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
+
+  /* Wait until SB flag is set */
+  if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK)
+  {
+    if (READ_BIT(hi2c->Instance->CR1, I2C_CR1_START) == I2C_CR1_START)
+    {
+      hi2c->ErrorCode = HAL_I2C_WRONG_START;
+    }
+    return HAL_TIMEOUT;
+  }
+
+  /* Send slave address */
+  hi2c->Instance->DR = I2C_7BIT_ADD_READ(DevAddress);
+
+  /* Wait until ADDR flag is set */
+  if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK)
+  {
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  DMA I2C process complete callback.
+  * @param  hdma DMA handle
+  * @retval None
+  */
+static void I2C_DMAXferCplt(DMA_HandleTypeDef *hdma)
+{
+  I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-11.5 */
+
+  /* Declaration of temporary variable to prevent undefined behavior of volatile usage */
+  HAL_I2C_StateTypeDef CurrentState = hi2c->State;
+  HAL_I2C_ModeTypeDef CurrentMode   = hi2c->Mode;
+  uint32_t CurrentXferOptions       = hi2c->XferOptions;
+
+  /* Disable EVT and ERR interrupt */
+  __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
+
+  /* Clear Complete callback */
+  if (hi2c->hdmatx != NULL)
+  {
+    hi2c->hdmatx->XferCpltCallback = NULL;
+  }
+  if (hi2c->hdmarx != NULL)
+  {
+    hi2c->hdmarx->XferCpltCallback = NULL;
+  }
+
+  if ((((uint32_t)CurrentState & (uint32_t)HAL_I2C_STATE_BUSY_TX) == (uint32_t)HAL_I2C_STATE_BUSY_TX) || ((((uint32_t)CurrentState & (uint32_t)HAL_I2C_STATE_BUSY_RX) == (uint32_t)HAL_I2C_STATE_BUSY_RX) && (CurrentMode == HAL_I2C_MODE_SLAVE)))
+  {
+    /* Disable DMA Request */
+    CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
+
+    hi2c->XferCount = 0U;
+
+    if (CurrentState == HAL_I2C_STATE_BUSY_TX_LISTEN)
+    {
+      /* Set state at HAL_I2C_STATE_LISTEN */
+      hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX;
+      hi2c->State = HAL_I2C_STATE_LISTEN;
+
+      /* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+      hi2c->SlaveTxCpltCallback(hi2c);
+#else
+      HAL_I2C_SlaveTxCpltCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+    }
+    else if (CurrentState == HAL_I2C_STATE_BUSY_RX_LISTEN)
+    {
+      /* Set state at HAL_I2C_STATE_LISTEN */
+      hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX;
+      hi2c->State = HAL_I2C_STATE_LISTEN;
+
+      /* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+      hi2c->SlaveRxCpltCallback(hi2c);
+#else
+      HAL_I2C_SlaveRxCpltCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+    }
+    else
+    {
+      /* Do nothing */
+    }
+
+    /* Enable EVT and ERR interrupt to treat end of transfer in IRQ handler */
+    __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
+  }
+  /* Check current Mode, in case of treatment DMA handler have been preempted by a prior interrupt */
+  else if (hi2c->Mode != HAL_I2C_MODE_NONE)
+  {
+    if (hi2c->XferCount == (uint16_t)1)
+    {
+      /* Disable Acknowledge */
+      CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
+    }
+
+    /* Disable EVT and ERR interrupt */
+    __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
+
+    /* Prepare next transfer or stop current transfer */
+    if ((CurrentXferOptions == I2C_NO_OPTION_FRAME) || (CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_OTHER_AND_LAST_FRAME) || (CurrentXferOptions == I2C_LAST_FRAME))
+    {
+      /* Generate Stop */
+      SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
+    }
+
+    /* Disable Last DMA */
+    CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_LAST);
+
+    /* Disable DMA Request */
+    CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
+
+    hi2c->XferCount = 0U;
+
+    /* Check if Errors has been detected during transfer */
+    if (hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
+    {
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+      hi2c->ErrorCallback(hi2c);
+#else
+      HAL_I2C_ErrorCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+    }
+    else
+    {
+      hi2c->State = HAL_I2C_STATE_READY;
+
+      if (hi2c->Mode == HAL_I2C_MODE_MEM)
+      {
+        hi2c->Mode = HAL_I2C_MODE_NONE;
+        hi2c->PreviousState = I2C_STATE_NONE;
+
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+        hi2c->MemRxCpltCallback(hi2c);
+#else
+        HAL_I2C_MemRxCpltCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+      }
+      else
+      {
+        hi2c->Mode = HAL_I2C_MODE_NONE;
+        hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;
+
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+        hi2c->MasterRxCpltCallback(hi2c);
+#else
+        HAL_I2C_MasterRxCpltCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+      }
+    }
+  }
+  else
+  {
+    /* Do nothing */
+  }
+}
+
+/**
+  * @brief  DMA I2C communication error callback.
+  * @param  hdma DMA handle
+  * @retval None
+  */
+static void I2C_DMAError(DMA_HandleTypeDef *hdma)
+{
+  I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-11.5 */
+
+  /* Clear Complete callback */
+  if (hi2c->hdmatx != NULL)
+  {
+    hi2c->hdmatx->XferCpltCallback = NULL;
+  }
+  if (hi2c->hdmarx != NULL)
+  {
+    hi2c->hdmarx->XferCpltCallback = NULL;
+  }
+
+  /* Ignore DMA FIFO error */
+  if (HAL_DMA_GetError(hdma) != HAL_DMA_ERROR_FE)
+  {
+    /* Disable Acknowledge */
+    hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
+
+    hi2c->XferCount = 0U;
+
+    hi2c->State = HAL_I2C_STATE_READY;
+    hi2c->Mode = HAL_I2C_MODE_NONE;
+
+    hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
+
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+    hi2c->ErrorCallback(hi2c);
+#else
+    HAL_I2C_ErrorCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+  }
+}
+
+/**
+  * @brief DMA I2C communication abort callback
+  *        (To be called at end of DMA Abort procedure).
+  * @param hdma DMA handle.
+  * @retval None
+  */
+static void I2C_DMAAbort(DMA_HandleTypeDef *hdma)
+{
+  __IO uint32_t count = 0U;
+  I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-11.5 */
+
+  /* Declaration of temporary variable to prevent undefined behavior of volatile usage */
+  HAL_I2C_StateTypeDef CurrentState = hi2c->State;
+
+  /* During abort treatment, check that there is no pending STOP request */
+  /* Wait until STOP flag is reset */
+  count = I2C_TIMEOUT_FLAG * (SystemCoreClock / 25U / 1000U);
+  do
+  {
+    if (count == 0U)
+    {
+      hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
+      break;
+    }
+    count--;
+  }
+  while (READ_BIT(hi2c->Instance->CR1, I2C_CR1_STOP) == I2C_CR1_STOP);
+
+  /* Clear Complete callback */
+  if (hi2c->hdmatx != NULL)
+  {
+    hi2c->hdmatx->XferCpltCallback = NULL;
+  }
+  if (hi2c->hdmarx != NULL)
+  {
+    hi2c->hdmarx->XferCpltCallback = NULL;
+  }
+
+  /* Disable Acknowledge */
+  CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
+
+  hi2c->XferCount = 0U;
+
+  /* Reset XferAbortCallback */
+  if (hi2c->hdmatx != NULL)
+  {
+    hi2c->hdmatx->XferAbortCallback = NULL;
+  }
+  if (hi2c->hdmarx != NULL)
+  {
+    hi2c->hdmarx->XferAbortCallback = NULL;
+  }
+
+  /* Disable I2C peripheral to prevent dummy data in buffer */
+  __HAL_I2C_DISABLE(hi2c);
+
+  /* Check if come from abort from user */
+  if (hi2c->State == HAL_I2C_STATE_ABORT)
+  {
+    hi2c->State         = HAL_I2C_STATE_READY;
+    hi2c->Mode          = HAL_I2C_MODE_NONE;
+    hi2c->ErrorCode     = HAL_I2C_ERROR_NONE;
+
+    /* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+    hi2c->AbortCpltCallback(hi2c);
+#else
+    HAL_I2C_AbortCpltCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+  }
+  else
+  {
+    if (((uint32_t)CurrentState & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
+    {
+      /* Renable I2C peripheral */
+      __HAL_I2C_ENABLE(hi2c);
+
+      /* Enable Acknowledge */
+      SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
+
+      /* keep HAL_I2C_STATE_LISTEN */
+      hi2c->PreviousState = I2C_STATE_NONE;
+      hi2c->State = HAL_I2C_STATE_LISTEN;
+    }
+    else
+    {
+      hi2c->State = HAL_I2C_STATE_READY;
+      hi2c->Mode = HAL_I2C_MODE_NONE;
+    }
+
+    /* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+    hi2c->ErrorCallback(hi2c);
+#else
+    HAL_I2C_ErrorCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+  }
+}
+
+/**
+  * @brief  This function handles I2C Communication Timeout.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *         the configuration information for I2C module
+  * @param  Flag specifies the I2C flag to check.
+  * @param  Status The new Flag status (SET or RESET).
+  * @param  Timeout Timeout duration
+  * @param  Tickstart Tick start value
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart)
+{
+  /* Wait until flag is set */
+  while (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status)
+  {
+    /* Check for the Timeout */
+    if (Timeout != HAL_MAX_DELAY)
+    {
+      if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
+      {
+        hi2c->PreviousState     = I2C_STATE_NONE;
+        hi2c->State             = HAL_I2C_STATE_READY;
+        hi2c->Mode              = HAL_I2C_MODE_NONE;
+        hi2c->ErrorCode         |= HAL_I2C_ERROR_TIMEOUT;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+
+        return HAL_ERROR;
+      }
+    }
+  }
+  return HAL_OK;
+}
+
+/**
+  * @brief  This function handles I2C Communication Timeout for Master addressing phase.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *         the configuration information for I2C module
+  * @param  Flag specifies the I2C flag to check.
+  * @param  Timeout Timeout duration
+  * @param  Tickstart Tick start value
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef I2C_WaitOnMasterAddressFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, uint32_t Timeout, uint32_t Tickstart)
+{
+  while (__HAL_I2C_GET_FLAG(hi2c, Flag) == RESET)
+  {
+    if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)
+    {
+      /* Generate Stop */
+      SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
+
+      /* Clear AF Flag */
+      __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+
+      hi2c->PreviousState       = I2C_STATE_NONE;
+      hi2c->State               = HAL_I2C_STATE_READY;
+      hi2c->Mode                = HAL_I2C_MODE_NONE;
+      hi2c->ErrorCode           |= HAL_I2C_ERROR_AF;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      return HAL_ERROR;
+    }
+
+    /* Check for the Timeout */
+    if (Timeout != HAL_MAX_DELAY)
+    {
+      if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
+      {
+        hi2c->PreviousState       = I2C_STATE_NONE;
+        hi2c->State               = HAL_I2C_STATE_READY;
+        hi2c->Mode                = HAL_I2C_MODE_NONE;
+        hi2c->ErrorCode           |= HAL_I2C_ERROR_TIMEOUT;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+
+        return HAL_ERROR;
+      }
+    }
+  }
+  return HAL_OK;
+}
+
+/**
+  * @brief  This function handles I2C Communication Timeout for specific usage of TXE flag.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  Timeout Timeout duration
+  * @param  Tickstart Tick start value
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef I2C_WaitOnTXEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
+{
+  while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET)
+  {
+    /* Check if a NACK is detected */
+    if (I2C_IsAcknowledgeFailed(hi2c) != HAL_OK)
+    {
+      return HAL_ERROR;
+    }
+
+    /* Check for the Timeout */
+    if (Timeout != HAL_MAX_DELAY)
+    {
+      if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
+      {
+        hi2c->PreviousState       = I2C_STATE_NONE;
+        hi2c->State               = HAL_I2C_STATE_READY;
+        hi2c->Mode                = HAL_I2C_MODE_NONE;
+        hi2c->ErrorCode           |= HAL_I2C_ERROR_TIMEOUT;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+
+        return HAL_ERROR;
+      }
+    }
+  }
+  return HAL_OK;
+}
+
+/**
+  * @brief  This function handles I2C Communication Timeout for specific usage of BTF flag.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  Timeout Timeout duration
+  * @param  Tickstart Tick start value
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef I2C_WaitOnBTFFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
+{
+  while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == RESET)
+  {
+    /* Check if a NACK is detected */
+    if (I2C_IsAcknowledgeFailed(hi2c) != HAL_OK)
+    {
+      return HAL_ERROR;
+    }
+
+    /* Check for the Timeout */
+    if (Timeout != HAL_MAX_DELAY)
+    {
+      if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
+      {
+        hi2c->PreviousState       = I2C_STATE_NONE;
+        hi2c->State               = HAL_I2C_STATE_READY;
+        hi2c->Mode                = HAL_I2C_MODE_NONE;
+        hi2c->ErrorCode           |= HAL_I2C_ERROR_TIMEOUT;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+
+        return HAL_ERROR;
+      }
+    }
+  }
+  return HAL_OK;
+}
+
+/**
+  * @brief  This function handles I2C Communication Timeout for specific usage of STOP flag.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  Timeout Timeout duration
+  * @param  Tickstart Tick start value
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
+{
+  while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
+  {
+    /* Check if a NACK is detected */
+    if (I2C_IsAcknowledgeFailed(hi2c) != HAL_OK)
+    {
+      return HAL_ERROR;
+    }
+
+    /* Check for the Timeout */
+    if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
+    {
+      hi2c->PreviousState       = I2C_STATE_NONE;
+      hi2c->State               = HAL_I2C_STATE_READY;
+      hi2c->Mode                = HAL_I2C_MODE_NONE;
+      hi2c->ErrorCode           |= HAL_I2C_ERROR_TIMEOUT;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      return HAL_ERROR;
+    }
+  }
+  return HAL_OK;
+}
+
+/**
+  * @brief  This function handles I2C Communication Timeout for specific usage of STOP request through Interrupt.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef I2C_WaitOnSTOPRequestThroughIT(I2C_HandleTypeDef *hi2c)
+{
+  __IO uint32_t count = 0U;
+
+  /* Wait until STOP flag is reset */
+  count = I2C_TIMEOUT_STOP_FLAG * (SystemCoreClock / 25U / 1000U);
+  do
+  {
+    count--;
+    if (count == 0U)
+    {
+      hi2c->ErrorCode           |= HAL_I2C_ERROR_TIMEOUT;
+
+      return HAL_ERROR;
+    }
+  }
+  while (READ_BIT(hi2c->Instance->CR1, I2C_CR1_STOP) == I2C_CR1_STOP);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  This function handles I2C Communication Timeout for specific usage of RXNE flag.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  Timeout Timeout duration
+  * @param  Tickstart Tick start value
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
+{
+
+  while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET)
+  {
+    /* Check if a STOPF is detected */
+    if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET)
+    {
+      /* Clear STOP Flag */
+      __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+
+      hi2c->PreviousState       = I2C_STATE_NONE;
+      hi2c->State               = HAL_I2C_STATE_READY;
+      hi2c->Mode                = HAL_I2C_MODE_NONE;
+      hi2c->ErrorCode           |= HAL_I2C_ERROR_NONE;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      return HAL_ERROR;
+    }
+
+    /* Check for the Timeout */
+    if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
+    {
+      hi2c->PreviousState       = I2C_STATE_NONE;
+      hi2c->State               = HAL_I2C_STATE_READY;
+      hi2c->Mode                = HAL_I2C_MODE_NONE;
+      hi2c->ErrorCode           |= HAL_I2C_ERROR_TIMEOUT;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      return HAL_ERROR;
+    }
+  }
+  return HAL_OK;
+}
+
+/**
+  * @brief  This function handles Acknowledge failed detection during an I2C Communication.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c)
+{
+  if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)
+  {
+    /* Clear NACKF Flag */
+    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+
+    hi2c->PreviousState       = I2C_STATE_NONE;
+    hi2c->State               = HAL_I2C_STATE_READY;
+    hi2c->Mode                = HAL_I2C_MODE_NONE;
+    hi2c->ErrorCode           |= HAL_I2C_ERROR_AF;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    return HAL_ERROR;
+  }
+  return HAL_OK;
+}
+
+/**
+  * @brief  Convert I2Cx OTHER_xxx XferOptions to functional XferOptions.
+  * @param  hi2c I2C handle.
+  * @retval None
+  */
+static void I2C_ConvertOtherXferOptions(I2C_HandleTypeDef *hi2c)
+{
+  /* if user set XferOptions to I2C_OTHER_FRAME            */
+  /* it request implicitly to generate a restart condition */
+  /* set XferOptions to I2C_FIRST_FRAME                    */
+  if (hi2c->XferOptions == I2C_OTHER_FRAME)
+  {
+    hi2c->XferOptions = I2C_FIRST_FRAME;
+  }
+  /* else if user set XferOptions to I2C_OTHER_AND_LAST_FRAME */
+  /* it request implicitly to generate a restart condition    */
+  /* then generate a stop condition at the end of transfer    */
+  /* set XferOptions to I2C_FIRST_AND_LAST_FRAME              */
+  else if (hi2c->XferOptions == I2C_OTHER_AND_LAST_FRAME)
+  {
+    hi2c->XferOptions = I2C_FIRST_AND_LAST_FRAME;
+  }
+  else
+  {
+    /* Nothing to do */
+  }
+}
+
+/**
+  * @}
+  */
+
+#endif /* HAL_I2C_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
diff --git a/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c_ex.c b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c_ex.c
new file mode 100644
index 0000000..351f4fd
--- /dev/null
+++ b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c_ex.c
@@ -0,0 +1,182 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hal_i2c_ex.c
+  * @author  MCD Application Team
+  * @brief   I2C Extension HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of I2C extension peripheral:
+  *           + Extension features functions
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2016 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  @verbatim
+  ==============================================================================
+               ##### I2C peripheral extension features  #####
+  ==============================================================================
+
+  [..] Comparing to other previous devices, the I2C interface for STM32F427xx/437xx/
+       429xx/439xx devices contains the following additional features :
+
+       (+) Possibility to disable or enable Analog Noise Filter
+       (+) Use of a configured Digital Noise Filter
+
+                     ##### How to use this driver #####
+  ==============================================================================
+  [..] This driver provides functions to configure Noise Filter
+    (#) Configure I2C Analog noise filter using the function HAL_I2C_AnalogFilter_Config()
+    (#) Configure I2C Digital noise filter using the function HAL_I2C_DigitalFilter_Config()
+
+  @endverbatim
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup I2CEx I2CEx
+  * @brief I2C HAL module driver
+  * @{
+  */
+
+#ifdef HAL_I2C_MODULE_ENABLED
+
+#if  defined(I2C_FLTR_ANOFF)&&defined(I2C_FLTR_DNF)
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup I2CEx_Exported_Functions I2C Exported Functions
+  * @{
+  */
+
+
+/** @defgroup I2CEx_Exported_Functions_Group1 Extension features functions
+ *  @brief   Extension features functions
+ *
+@verbatim
+ ===============================================================================
+                      ##### Extension features functions #####
+ ===============================================================================
+    [..] This section provides functions allowing to:
+      (+) Configure Noise Filters
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Configures I2C Analog noise filter.
+  * @param  hi2c pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2Cx peripheral.
+  * @param  AnalogFilter new state of the Analog filter.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
+  assert_param(IS_I2C_ANALOG_FILTER(AnalogFilter));
+
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    hi2c->State = HAL_I2C_STATE_BUSY;
+
+    /* Disable the selected I2C peripheral */
+    __HAL_I2C_DISABLE(hi2c);
+
+    /* Reset I2Cx ANOFF bit */
+    hi2c->Instance->FLTR &= ~(I2C_FLTR_ANOFF);
+
+    /* Disable the analog filter */
+    hi2c->Instance->FLTR |= AnalogFilter;
+
+    __HAL_I2C_ENABLE(hi2c);
+
+    hi2c->State = HAL_I2C_STATE_READY;
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Configures I2C Digital noise filter.
+  * @param  hi2c pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2Cx peripheral.
+  * @param  DigitalFilter Coefficient of digital noise filter between 0x00 and 0x0F.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter)
+{
+  uint16_t tmpreg = 0;
+
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
+  assert_param(IS_I2C_DIGITAL_FILTER(DigitalFilter));
+
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    hi2c->State = HAL_I2C_STATE_BUSY;
+
+    /* Disable the selected I2C peripheral */
+    __HAL_I2C_DISABLE(hi2c);
+
+    /* Get the old register value */
+    tmpreg = hi2c->Instance->FLTR;
+
+    /* Reset I2Cx DNF bit [3:0] */
+    tmpreg &= ~(I2C_FLTR_DNF);
+
+    /* Set I2Cx DNF coefficient */
+    tmpreg |= DigitalFilter;
+
+    /* Store the new register value */
+    hi2c->Instance->FLTR = tmpreg;
+
+    __HAL_I2C_ENABLE(hi2c);
+
+    hi2c->State = HAL_I2C_STATE_READY;
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+#endif
+
+#endif /* HAL_I2C_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
diff --git a/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_ltdc.c b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_ltdc.c
new file mode 100644
index 0000000..e350629
--- /dev/null
+++ b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_ltdc.c
@@ -0,0 +1,2215 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hal_ltdc.c
+  * @author  MCD Application Team
+  * @brief   LTDC HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the LTDC peripheral:
+  *           + Initialization and de-initialization functions
+  *           + IO operation functions
+  *           + Peripheral Control functions
+  *           + Peripheral State and Errors functions
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2016 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  @verbatim
+  ==============================================================================
+                        ##### How to use this driver #####
+  ==============================================================================
+     [..]
+     The LTDC HAL driver can be used as follows:
+
+     (#) Declare a LTDC_HandleTypeDef handle structure, for example: LTDC_HandleTypeDef  hltdc;
+
+     (#) Initialize the LTDC low level resources by implementing the HAL_LTDC_MspInit() API:
+         (##) Enable the LTDC interface clock
+         (##) NVIC configuration if you need to use interrupt process
+             (+++) Configure the LTDC interrupt priority
+             (+++) Enable the NVIC LTDC IRQ Channel
+
+     (#) Initialize the required configuration through the following parameters:
+         the LTDC timing, the horizontal and vertical polarity, the pixel clock polarity,
+         Data Enable polarity and the LTDC background color value using HAL_LTDC_Init() function
+
+     *** Configuration ***
+     =========================
+     [..]
+     (#) Program the required configuration through the following parameters:
+         the pixel format, the blending factors, input alpha value, the window size
+         and the image size using HAL_LTDC_ConfigLayer() function for foreground
+         or/and background layer.
+
+     (#) Optionally, configure and enable the CLUT using HAL_LTDC_ConfigCLUT() and
+         HAL_LTDC_EnableCLUT functions.
+
+     (#) Optionally, enable the Dither using HAL_LTDC_EnableDither().
+
+     (#) Optionally, configure and enable the Color keying using HAL_LTDC_ConfigColorKeying()
+         and HAL_LTDC_EnableColorKeying functions.
+
+     (#) Optionally, configure LineInterrupt using HAL_LTDC_ProgramLineEvent()
+         function
+
+     (#) If needed, reconfigure and change the pixel format value, the alpha value
+         value, the window size, the window position and the layer start address
+         for foreground or/and background layer using respectively the following
+         functions: HAL_LTDC_SetPixelFormat(), HAL_LTDC_SetAlpha(), HAL_LTDC_SetWindowSize(),
+         HAL_LTDC_SetWindowPosition() and HAL_LTDC_SetAddress().
+
+     (#) Variant functions with _NoReload suffix allows to set the LTDC configuration/settings without immediate reload.
+         This is useful in case when the program requires to modify serval LTDC settings (on one or both layers)
+         then applying(reload) these settings in one shot by calling the function HAL_LTDC_Reload().
+
+         After calling the _NoReload functions to set different color/format/layer settings,
+         the program shall call the function HAL_LTDC_Reload() to apply(reload) these settings.
+         Function HAL_LTDC_Reload() can be called with the parameter ReloadType set to LTDC_RELOAD_IMMEDIATE if
+         an immediate reload is required.
+         Function HAL_LTDC_Reload() can be called with the parameter ReloadType set to LTDC_RELOAD_VERTICAL_BLANKING if
+         the reload should be done in the next vertical blanking period,
+         this option allows to avoid display flicker by applying the new settings during the vertical blanking period.
+
+
+     (#) To control LTDC state you can use the following function: HAL_LTDC_GetState()
+
+     *** LTDC HAL driver macros list ***
+     =============================================
+     [..]
+       Below the list of most used macros in LTDC HAL driver.
+
+      (+) __HAL_LTDC_ENABLE: Enable the LTDC.
+      (+) __HAL_LTDC_DISABLE: Disable the LTDC.
+      (+) __HAL_LTDC_LAYER_ENABLE: Enable an LTDC Layer.
+      (+) __HAL_LTDC_LAYER_DISABLE: Disable an LTDC Layer.
+      (+) __HAL_LTDC_RELOAD_IMMEDIATE_CONFIG: Reload  Layer Configuration.
+      (+) __HAL_LTDC_GET_FLAG: Get the LTDC pending flags.
+      (+) __HAL_LTDC_CLEAR_FLAG: Clear the LTDC pending flags.
+      (+) __HAL_LTDC_ENABLE_IT: Enable the specified LTDC interrupts.
+      (+) __HAL_LTDC_DISABLE_IT: Disable the specified LTDC interrupts.
+      (+) __HAL_LTDC_GET_IT_SOURCE: Check whether the specified LTDC interrupt has occurred or not.
+
+     [..]
+       (@) You can refer to the LTDC HAL driver header file for more useful macros
+
+
+     *** Callback registration ***
+     =============================================
+     [..]
+     The compilation define  USE_HAL_LTDC_REGISTER_CALLBACKS when set to 1
+     allows the user to configure dynamically the driver callbacks.
+     Use function HAL_LTDC_RegisterCallback() to register a callback.
+
+    [..]
+    Function HAL_LTDC_RegisterCallback() allows to register following callbacks:
+      (+) LineEventCallback   : LTDC Line Event Callback.
+      (+) ReloadEventCallback : LTDC Reload Event Callback.
+      (+) ErrorCallback       : LTDC Error Callback
+      (+) MspInitCallback     : LTDC MspInit.
+      (+) MspDeInitCallback   : LTDC MspDeInit.
+    [..]
+    This function takes as parameters the HAL peripheral handle, the callback ID
+    and a pointer to the user callback function.
+
+    [..]
+    Use function HAL_LTDC_UnRegisterCallback() to reset a callback to the default
+    weak function.
+    HAL_LTDC_UnRegisterCallback() takes as parameters the HAL peripheral handle
+    and the callback ID.
+    [..]
+    This function allows to reset following callbacks:
+      (+) LineEventCallback   : LTDC Line Event Callback
+      (+) ReloadEventCallback : LTDC Reload Event Callback
+      (+) ErrorCallback       : LTDC Error Callback
+      (+) MspInitCallback     : LTDC MspInit
+      (+) MspDeInitCallback   : LTDC MspDeInit.
+
+    [..]
+    By default, after the HAL_LTDC_Init and when the state is HAL_LTDC_STATE_RESET
+    all callbacks are set to the corresponding weak functions:
+    examples HAL_LTDC_LineEventCallback(), HAL_LTDC_ErrorCallback().
+    Exception done for MspInit and MspDeInit functions that are
+    reset to the legacy weak (surcharged) functions in the HAL_LTDC_Init() and HAL_LTDC_DeInit()
+    only when these callbacks are null (not registered beforehand).
+    If not, MspInit or MspDeInit are not null, the HAL_LTDC_Init() and HAL_LTDC_DeInit()
+    keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
+
+    [..]
+    Callbacks can be registered/unregistered in HAL_LTDC_STATE_READY state only.
+    Exception done MspInit/MspDeInit that can be registered/unregistered
+    in HAL_LTDC_STATE_READY or HAL_LTDC_STATE_RESET state,
+    thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
+    In that case first register the MspInit/MspDeInit user callbacks
+    using HAL_LTDC_RegisterCallback() before calling HAL_LTDC_DeInit()
+    or HAL_LTDC_Init() function.
+
+    [..]
+    When the compilation define USE_HAL_LTDC_REGISTER_CALLBACKS is set to 0 or
+    not defined, the callback registration feature is not available and all callbacks
+    are set to the corresponding weak functions.
+
+  @endverbatim
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+  * @{
+  */
+
+#ifdef HAL_LTDC_MODULE_ENABLED
+
+#if defined (LTDC)
+
+/** @defgroup LTDC LTDC
+  * @brief LTDC HAL module driver
+  * @{
+  */
+
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+#define LTDC_TIMEOUT_VALUE ((uint32_t)100U)  /* 100ms */
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+static void LTDC_SetConfig(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg, uint32_t LayerIdx);
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup LTDC_Exported_Functions LTDC Exported Functions
+  * @{
+  */
+
+/** @defgroup LTDC_Exported_Functions_Group1 Initialization and Configuration functions
+  *  @brief   Initialization and Configuration functions
+  *
+@verbatim
+ ===============================================================================
+                ##### Initialization and Configuration functions #####
+ ===============================================================================
+    [..]  This section provides functions allowing to:
+      (+) Initialize and configure the LTDC
+      (+) De-initialize the LTDC
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initialize the LTDC according to the specified parameters in the LTDC_InitTypeDef.
+  * @param  hltdc  pointer to a LTDC_HandleTypeDef structure that contains
+  *                the configuration information for the LTDC.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_LTDC_Init(LTDC_HandleTypeDef *hltdc)
+{
+  uint32_t tmp;
+  uint32_t tmp1;
+
+  /* Check the LTDC peripheral state */
+  if (hltdc == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check function parameters */
+  assert_param(IS_LTDC_ALL_INSTANCE(hltdc->Instance));
+  assert_param(IS_LTDC_HSYNC(hltdc->Init.HorizontalSync));
+  assert_param(IS_LTDC_VSYNC(hltdc->Init.VerticalSync));
+  assert_param(IS_LTDC_AHBP(hltdc->Init.AccumulatedHBP));
+  assert_param(IS_LTDC_AVBP(hltdc->Init.AccumulatedVBP));
+  assert_param(IS_LTDC_AAH(hltdc->Init.AccumulatedActiveH));
+  assert_param(IS_LTDC_AAW(hltdc->Init.AccumulatedActiveW));
+  assert_param(IS_LTDC_TOTALH(hltdc->Init.TotalHeigh));
+  assert_param(IS_LTDC_TOTALW(hltdc->Init.TotalWidth));
+  assert_param(IS_LTDC_HSPOL(hltdc->Init.HSPolarity));
+  assert_param(IS_LTDC_VSPOL(hltdc->Init.VSPolarity));
+  assert_param(IS_LTDC_DEPOL(hltdc->Init.DEPolarity));
+  assert_param(IS_LTDC_PCPOL(hltdc->Init.PCPolarity));
+
+#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1)
+  if (hltdc->State == HAL_LTDC_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    hltdc->Lock = HAL_UNLOCKED;
+
+    /* Reset the LTDC callback to the legacy weak callbacks */
+    hltdc->LineEventCallback   = HAL_LTDC_LineEventCallback;    /* Legacy weak LineEventCallback    */
+    hltdc->ReloadEventCallback = HAL_LTDC_ReloadEventCallback;  /* Legacy weak ReloadEventCallback  */
+    hltdc->ErrorCallback       = HAL_LTDC_ErrorCallback;        /* Legacy weak ErrorCallback        */
+
+    if (hltdc->MspInitCallback == NULL)
+    {
+      hltdc->MspInitCallback = HAL_LTDC_MspInit;
+    }
+    /* Init the low level hardware */
+    hltdc->MspInitCallback(hltdc);
+  }
+#else
+  if (hltdc->State == HAL_LTDC_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    hltdc->Lock = HAL_UNLOCKED;
+    /* Init the low level hardware */
+    HAL_LTDC_MspInit(hltdc);
+  }
+#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */
+
+  /* Change LTDC peripheral state */
+  hltdc->State = HAL_LTDC_STATE_BUSY;
+
+  /* Configure the HS, VS, DE and PC polarity */
+  hltdc->Instance->GCR &= ~(LTDC_GCR_HSPOL | LTDC_GCR_VSPOL | LTDC_GCR_DEPOL | LTDC_GCR_PCPOL);
+  hltdc->Instance->GCR |= (uint32_t)(hltdc->Init.HSPolarity | hltdc->Init.VSPolarity | \
+                                     hltdc->Init.DEPolarity | hltdc->Init.PCPolarity);
+
+  /* Set Synchronization size */
+  hltdc->Instance->SSCR &= ~(LTDC_SSCR_VSH | LTDC_SSCR_HSW);
+  tmp = (hltdc->Init.HorizontalSync << 16U);
+  hltdc->Instance->SSCR |= (tmp | hltdc->Init.VerticalSync);
+
+  /* Set Accumulated Back porch */
+  hltdc->Instance->BPCR &= ~(LTDC_BPCR_AVBP | LTDC_BPCR_AHBP);
+  tmp = (hltdc->Init.AccumulatedHBP << 16U);
+  hltdc->Instance->BPCR |= (tmp | hltdc->Init.AccumulatedVBP);
+
+  /* Set Accumulated Active Width */
+  hltdc->Instance->AWCR &= ~(LTDC_AWCR_AAH | LTDC_AWCR_AAW);
+  tmp = (hltdc->Init.AccumulatedActiveW << 16U);
+  hltdc->Instance->AWCR |= (tmp | hltdc->Init.AccumulatedActiveH);
+
+  /* Set Total Width */
+  hltdc->Instance->TWCR &= ~(LTDC_TWCR_TOTALH | LTDC_TWCR_TOTALW);
+  tmp = (hltdc->Init.TotalWidth << 16U);
+  hltdc->Instance->TWCR |= (tmp | hltdc->Init.TotalHeigh);
+
+  /* Set the background color value */
+  tmp = ((uint32_t)(hltdc->Init.Backcolor.Green) << 8U);
+  tmp1 = ((uint32_t)(hltdc->Init.Backcolor.Red) << 16U);
+  hltdc->Instance->BCCR &= ~(LTDC_BCCR_BCBLUE | LTDC_BCCR_BCGREEN | LTDC_BCCR_BCRED);
+  hltdc->Instance->BCCR |= (tmp1 | tmp | hltdc->Init.Backcolor.Blue);
+
+  /* Enable the Transfer Error and FIFO underrun interrupts */
+  __HAL_LTDC_ENABLE_IT(hltdc, LTDC_IT_TE | LTDC_IT_FU);
+
+  /* Enable LTDC by setting LTDCEN bit */
+  __HAL_LTDC_ENABLE(hltdc);
+
+  /* Initialize the error code */
+  hltdc->ErrorCode = HAL_LTDC_ERROR_NONE;
+
+  /* Initialize the LTDC state*/
+  hltdc->State = HAL_LTDC_STATE_READY;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  De-initialize the LTDC peripheral.
+  * @param  hltdc  pointer to a LTDC_HandleTypeDef structure that contains
+  *                the configuration information for the LTDC.
+  * @retval None
+  */
+
+HAL_StatusTypeDef HAL_LTDC_DeInit(LTDC_HandleTypeDef *hltdc)
+{
+  uint32_t tickstart;
+
+  /* Check the LTDC peripheral state */
+  if (hltdc == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check function parameters */
+  assert_param(IS_LTDC_ALL_INSTANCE(hltdc->Instance));
+
+  /* Disable LTDC Layer 1 */
+  __HAL_LTDC_LAYER_DISABLE(hltdc, LTDC_LAYER_1);
+
+#if defined(LTDC_Layer2_BASE)
+  /* Disable LTDC Layer 2 */
+  __HAL_LTDC_LAYER_DISABLE(hltdc, LTDC_LAYER_2);
+#endif /* LTDC_Layer2_BASE */
+
+  /* Reload during vertical blanking period */
+  __HAL_LTDC_VERTICAL_BLANKING_RELOAD_CONFIG(hltdc);
+
+  /* Get tick */
+  tickstart = HAL_GetTick();
+
+  /* Wait for VSYNC Interrupt */
+  while (READ_BIT(hltdc->Instance->CDSR, LTDC_CDSR_VSYNCS) == 0U)
+  {
+    /* Check for the Timeout */
+    if ((HAL_GetTick() - tickstart) > LTDC_TIMEOUT_VALUE)
+    {
+      break;
+    }
+  }
+
+  /* Disable LTDC  */
+  __HAL_LTDC_DISABLE(hltdc);
+
+#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1)
+  if (hltdc->MspDeInitCallback == NULL)
+  {
+    hltdc->MspDeInitCallback = HAL_LTDC_MspDeInit;
+  }
+  /* DeInit the low level hardware */
+  hltdc->MspDeInitCallback(hltdc);
+#else
+  /* DeInit the low level hardware */
+  HAL_LTDC_MspDeInit(hltdc);
+#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */
+
+  /* Initialize the error code */
+  hltdc->ErrorCode = HAL_LTDC_ERROR_NONE;
+
+  /* Initialize the LTDC state*/
+  hltdc->State = HAL_LTDC_STATE_RESET;
+
+  /* Release Lock */
+  __HAL_UNLOCK(hltdc);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initialize the LTDC MSP.
+  * @param  hltdc  pointer to a LTDC_HandleTypeDef structure that contains
+  *                the configuration information for the LTDC.
+  * @retval None
+  */
+__weak void HAL_LTDC_MspInit(LTDC_HandleTypeDef *hltdc)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hltdc);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_LTDC_MspInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  De-initialize the LTDC MSP.
+  * @param  hltdc  pointer to a LTDC_HandleTypeDef structure that contains
+  *                the configuration information for the LTDC.
+  * @retval None
+  */
+__weak void HAL_LTDC_MspDeInit(LTDC_HandleTypeDef *hltdc)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hltdc);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_LTDC_MspDeInit could be implemented in the user file
+   */
+}
+
+#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1)
+/**
+  * @brief  Register a User LTDC Callback
+  *         To be used instead of the weak predefined callback
+  * @param hltdc ltdc handle
+  * @param CallbackID ID of the callback to be registered
+  *        This parameter can be one of the following values:
+  *          @arg @ref HAL_LTDC_LINE_EVENT_CB_ID Line Event Callback ID
+  *          @arg @ref HAL_LTDC_RELOAD_EVENT_CB_ID Reload Event Callback ID
+  *          @arg @ref HAL_LTDC_ERROR_CB_ID Error Callback ID
+  *          @arg @ref HAL_LTDC_MSPINIT_CB_ID MspInit callback ID
+  *          @arg @ref HAL_LTDC_MSPDEINIT_CB_ID MspDeInit callback ID
+  * @param pCallback pointer to the Callback function
+  * @retval status
+  */
+HAL_StatusTypeDef HAL_LTDC_RegisterCallback(LTDC_HandleTypeDef *hltdc, HAL_LTDC_CallbackIDTypeDef CallbackID,
+                                            pLTDC_CallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    /* Update the error code */
+    hltdc->ErrorCode |= HAL_LTDC_ERROR_INVALID_CALLBACK;
+
+    return HAL_ERROR;
+  }
+  /* Process locked */
+  __HAL_LOCK(hltdc);
+
+  if (hltdc->State == HAL_LTDC_STATE_READY)
+  {
+    switch (CallbackID)
+    {
+      case HAL_LTDC_LINE_EVENT_CB_ID :
+        hltdc->LineEventCallback = pCallback;
+        break;
+
+      case HAL_LTDC_RELOAD_EVENT_CB_ID :
+        hltdc->ReloadEventCallback = pCallback;
+        break;
+
+      case HAL_LTDC_ERROR_CB_ID :
+        hltdc->ErrorCallback = pCallback;
+        break;
+
+      case HAL_LTDC_MSPINIT_CB_ID :
+        hltdc->MspInitCallback = pCallback;
+        break;
+
+      case HAL_LTDC_MSPDEINIT_CB_ID :
+        hltdc->MspDeInitCallback = pCallback;
+        break;
+
+      default :
+        /* Update the error code */
+        hltdc->ErrorCode |= HAL_LTDC_ERROR_INVALID_CALLBACK;
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else if (hltdc->State == HAL_LTDC_STATE_RESET)
+  {
+    switch (CallbackID)
+    {
+      case HAL_LTDC_MSPINIT_CB_ID :
+        hltdc->MspInitCallback = pCallback;
+        break;
+
+      case HAL_LTDC_MSPDEINIT_CB_ID :
+        hltdc->MspDeInitCallback = pCallback;
+        break;
+
+      default :
+        /* Update the error code */
+        hltdc->ErrorCode |= HAL_LTDC_ERROR_INVALID_CALLBACK;
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    /* Update the error code */
+    hltdc->ErrorCode |= HAL_LTDC_ERROR_INVALID_CALLBACK;
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(hltdc);
+
+  return status;
+}
+
+/**
+  * @brief  Unregister an LTDC Callback
+  *         LTDC callback is redirected to the weak predefined callback
+  * @param hltdc ltdc handle
+  * @param CallbackID ID of the callback to be unregistered
+  *        This parameter can be one of the following values:
+  *          @arg @ref HAL_LTDC_LINE_EVENT_CB_ID Line Event Callback ID
+  *          @arg @ref HAL_LTDC_RELOAD_EVENT_CB_ID Reload Event Callback ID
+  *          @arg @ref HAL_LTDC_ERROR_CB_ID Error Callback ID
+  *          @arg @ref HAL_LTDC_MSPINIT_CB_ID MspInit callback ID
+  *          @arg @ref HAL_LTDC_MSPDEINIT_CB_ID MspDeInit callback ID
+  * @retval status
+  */
+HAL_StatusTypeDef HAL_LTDC_UnRegisterCallback(LTDC_HandleTypeDef *hltdc, HAL_LTDC_CallbackIDTypeDef CallbackID)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Process locked */
+  __HAL_LOCK(hltdc);
+
+  if (hltdc->State == HAL_LTDC_STATE_READY)
+  {
+    switch (CallbackID)
+    {
+      case HAL_LTDC_LINE_EVENT_CB_ID :
+        hltdc->LineEventCallback = HAL_LTDC_LineEventCallback;      /* Legacy weak LineEventCallback    */
+        break;
+
+      case HAL_LTDC_RELOAD_EVENT_CB_ID :
+        hltdc->ReloadEventCallback = HAL_LTDC_ReloadEventCallback;  /* Legacy weak ReloadEventCallback  */
+        break;
+
+      case HAL_LTDC_ERROR_CB_ID :
+        hltdc->ErrorCallback       = HAL_LTDC_ErrorCallback;        /* Legacy weak ErrorCallback        */
+        break;
+
+      case HAL_LTDC_MSPINIT_CB_ID :
+        hltdc->MspInitCallback = HAL_LTDC_MspInit;                  /* Legcay weak MspInit Callback     */
+        break;
+
+      case HAL_LTDC_MSPDEINIT_CB_ID :
+        hltdc->MspDeInitCallback = HAL_LTDC_MspDeInit;              /* Legcay weak MspDeInit Callback     */
+        break;
+
+      default :
+        /* Update the error code */
+        hltdc->ErrorCode |= HAL_LTDC_ERROR_INVALID_CALLBACK;
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else if (hltdc->State == HAL_LTDC_STATE_RESET)
+  {
+    switch (CallbackID)
+    {
+      case HAL_LTDC_MSPINIT_CB_ID :
+        hltdc->MspInitCallback = HAL_LTDC_MspInit;                  /* Legcay weak MspInit Callback     */
+        break;
+
+      case HAL_LTDC_MSPDEINIT_CB_ID :
+        hltdc->MspDeInitCallback = HAL_LTDC_MspDeInit;              /* Legcay weak MspDeInit Callback     */
+        break;
+
+      default :
+        /* Update the error code */
+        hltdc->ErrorCode |= HAL_LTDC_ERROR_INVALID_CALLBACK;
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    /* Update the error code */
+    hltdc->ErrorCode |= HAL_LTDC_ERROR_INVALID_CALLBACK;
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(hltdc);
+
+  return status;
+}
+#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+
+/** @defgroup LTDC_Exported_Functions_Group2 IO operation functions
+  *  @brief   IO operation functions
+  *
+@verbatim
+ ===============================================================================
+                      #####  IO operation functions  #####
+ ===============================================================================
+    [..]  This section provides function allowing to:
+      (+) Handle LTDC interrupt request
+
+@endverbatim
+  * @{
+  */
+/**
+  * @brief  Handle LTDC interrupt request.
+  * @param  hltdc  pointer to a LTDC_HandleTypeDef structure that contains
+  *                the configuration information for the LTDC.
+  * @retval HAL status
+  */
+void HAL_LTDC_IRQHandler(LTDC_HandleTypeDef *hltdc)
+{
+  uint32_t isrflags  = READ_REG(hltdc->Instance->ISR);
+  uint32_t itsources = READ_REG(hltdc->Instance->IER);
+
+  /* Transfer Error Interrupt management ***************************************/
+  if (((isrflags & LTDC_ISR_TERRIF) != 0U) && ((itsources & LTDC_IER_TERRIE) != 0U))
+  {
+    /* Disable the transfer Error interrupt */
+    __HAL_LTDC_DISABLE_IT(hltdc, LTDC_IT_TE);
+
+    /* Clear the transfer error flag */
+    __HAL_LTDC_CLEAR_FLAG(hltdc, LTDC_FLAG_TE);
+
+    /* Update error code */
+    hltdc->ErrorCode |= HAL_LTDC_ERROR_TE;
+
+    /* Change LTDC state */
+    hltdc->State = HAL_LTDC_STATE_ERROR;
+
+    /* Process unlocked */
+    __HAL_UNLOCK(hltdc);
+
+    /* Transfer error Callback */
+#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1)
+    /*Call registered error callback*/
+    hltdc->ErrorCallback(hltdc);
+#else
+    /* Call legacy error callback*/
+    HAL_LTDC_ErrorCallback(hltdc);
+#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */
+  }
+
+  /* FIFO underrun Interrupt management ***************************************/
+  if (((isrflags & LTDC_ISR_FUIF) != 0U) && ((itsources & LTDC_IER_FUIE) != 0U))
+  {
+    /* Disable the FIFO underrun interrupt */
+    __HAL_LTDC_DISABLE_IT(hltdc, LTDC_IT_FU);
+
+    /* Clear the FIFO underrun flag */
+    __HAL_LTDC_CLEAR_FLAG(hltdc, LTDC_FLAG_FU);
+
+    /* Update error code */
+    hltdc->ErrorCode |= HAL_LTDC_ERROR_FU;
+
+    /* Change LTDC state */
+    hltdc->State = HAL_LTDC_STATE_ERROR;
+
+    /* Process unlocked */
+    __HAL_UNLOCK(hltdc);
+
+    /* Transfer error Callback */
+#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1)
+    /*Call registered error callback*/
+    hltdc->ErrorCallback(hltdc);
+#else
+    /* Call legacy error callback*/
+    HAL_LTDC_ErrorCallback(hltdc);
+#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */
+  }
+
+  /* Line Interrupt management ************************************************/
+  if (((isrflags & LTDC_ISR_LIF) != 0U) && ((itsources & LTDC_IER_LIE) != 0U))
+  {
+    /* Disable the Line interrupt */
+    __HAL_LTDC_DISABLE_IT(hltdc, LTDC_IT_LI);
+
+    /* Clear the Line interrupt flag */
+    __HAL_LTDC_CLEAR_FLAG(hltdc, LTDC_FLAG_LI);
+
+    /* Change LTDC state */
+    hltdc->State = HAL_LTDC_STATE_READY;
+
+    /* Process unlocked */
+    __HAL_UNLOCK(hltdc);
+
+    /* Line interrupt Callback */
+#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1)
+    /*Call registered Line Event callback */
+    hltdc->LineEventCallback(hltdc);
+#else
+    /*Call Legacy Line Event callback */
+    HAL_LTDC_LineEventCallback(hltdc);
+#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */
+  }
+
+  /* Register reload Interrupt management ***************************************/
+  if (((isrflags & LTDC_ISR_RRIF) != 0U) && ((itsources & LTDC_IER_RRIE) != 0U))
+  {
+    /* Disable the register reload interrupt */
+    __HAL_LTDC_DISABLE_IT(hltdc, LTDC_IT_RR);
+
+    /* Clear the register reload flag */
+    __HAL_LTDC_CLEAR_FLAG(hltdc, LTDC_FLAG_RR);
+
+    /* Change LTDC state */
+    hltdc->State = HAL_LTDC_STATE_READY;
+
+    /* Process unlocked */
+    __HAL_UNLOCK(hltdc);
+
+    /* Reload interrupt Callback */
+#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1)
+    /*Call registered reload Event callback */
+    hltdc->ReloadEventCallback(hltdc);
+#else
+    /*Call Legacy Reload Event callback */
+    HAL_LTDC_ReloadEventCallback(hltdc);
+#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */
+  }
+}
+
+/**
+  * @brief  Error LTDC callback.
+  * @param  hltdc  pointer to a LTDC_HandleTypeDef structure that contains
+  *                the configuration information for the LTDC.
+  * @retval None
+  */
+__weak void HAL_LTDC_ErrorCallback(LTDC_HandleTypeDef *hltdc)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hltdc);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_LTDC_ErrorCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Line Event callback.
+  * @param  hltdc  pointer to a LTDC_HandleTypeDef structure that contains
+  *                the configuration information for the LTDC.
+  * @retval None
+  */
+__weak void HAL_LTDC_LineEventCallback(LTDC_HandleTypeDef *hltdc)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hltdc);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_LTDC_LineEventCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Reload Event callback.
+  * @param  hltdc  pointer to a LTDC_HandleTypeDef structure that contains
+  *                the configuration information for the LTDC.
+  * @retval None
+  */
+__weak void HAL_LTDC_ReloadEventCallback(LTDC_HandleTypeDef *hltdc)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hltdc);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_LTDC_ReloadEvenCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup LTDC_Exported_Functions_Group3 Peripheral Control functions
+  *  @brief    Peripheral Control functions
+  *
+@verbatim
+ ===============================================================================
+                    ##### Peripheral Control functions #####
+ ===============================================================================
+    [..]  This section provides functions allowing to:
+      (+) Configure the LTDC foreground or/and background parameters.
+      (+) Set the active layer.
+      (+) Configure the color keying.
+      (+) Configure the C-LUT.
+      (+) Enable / Disable the color keying.
+      (+) Enable / Disable the C-LUT.
+      (+) Update the layer position.
+      (+) Update the layer size.
+      (+) Update pixel format on the fly.
+      (+) Update transparency on the fly.
+      (+) Update address on the fly.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Configure the LTDC Layer according to the specified
+  *         parameters in the LTDC_InitTypeDef and create the associated handle.
+  * @param  hltdc      pointer to a LTDC_HandleTypeDef structure that contains
+  *                    the configuration information for the LTDC.
+  * @param  pLayerCfg  pointer to a LTDC_LayerCfgTypeDef structure that contains
+  *                    the configuration information for the Layer.
+  * @param  LayerIdx  LTDC Layer index.
+  *                    This parameter can be one of the following values:
+  *                    LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_LTDC_ConfigLayer(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg, uint32_t LayerIdx)
+{
+  /* Check the parameters */
+  assert_param(IS_LTDC_LAYER(LayerIdx));
+  assert_param(IS_LTDC_HCONFIGST(pLayerCfg->WindowX0));
+  assert_param(IS_LTDC_HCONFIGSP(pLayerCfg->WindowX1));
+  assert_param(IS_LTDC_VCONFIGST(pLayerCfg->WindowY0));
+  assert_param(IS_LTDC_VCONFIGSP(pLayerCfg->WindowY1));
+  assert_param(IS_LTDC_PIXEL_FORMAT(pLayerCfg->PixelFormat));
+  assert_param(IS_LTDC_ALPHA(pLayerCfg->Alpha));
+  assert_param(IS_LTDC_ALPHA(pLayerCfg->Alpha0));
+  assert_param(IS_LTDC_BLENDING_FACTOR1(pLayerCfg->BlendingFactor1));
+  assert_param(IS_LTDC_BLENDING_FACTOR2(pLayerCfg->BlendingFactor2));
+  assert_param(IS_LTDC_CFBLL(pLayerCfg->ImageWidth));
+  assert_param(IS_LTDC_CFBLNBR(pLayerCfg->ImageHeight));
+
+  /* Process locked */
+  __HAL_LOCK(hltdc);
+
+  /* Change LTDC peripheral state */
+  hltdc->State = HAL_LTDC_STATE_BUSY;
+
+  /* Copy new layer configuration into handle structure */
+  hltdc->LayerCfg[LayerIdx] = *pLayerCfg;
+
+  /* Configure the LTDC Layer */
+  LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx);
+
+  /* Set the Immediate Reload type */
+  hltdc->Instance->SRCR = LTDC_SRCR_IMR;
+
+  /* Initialize the LTDC state*/
+  hltdc->State  = HAL_LTDC_STATE_READY;
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hltdc);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Configure the color keying.
+  * @param  hltdc     pointer to a LTDC_HandleTypeDef structure that contains
+  *                   the configuration information for the LTDC.
+  * @param  RGBValue  the color key value
+  * @param  LayerIdx  LTDC Layer index.
+  *                   This parameter can be one of the following values:
+  *                   LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_LTDC_ConfigColorKeying(LTDC_HandleTypeDef *hltdc, uint32_t RGBValue, uint32_t LayerIdx)
+{
+  /* Check the parameters */
+  assert_param(IS_LTDC_LAYER(LayerIdx));
+
+  /* Process locked */
+  __HAL_LOCK(hltdc);
+
+  /* Change LTDC peripheral state */
+  hltdc->State = HAL_LTDC_STATE_BUSY;
+
+  /* Configure the default color values */
+  LTDC_LAYER(hltdc, LayerIdx)->CKCR &=  ~(LTDC_LxCKCR_CKBLUE | LTDC_LxCKCR_CKGREEN | LTDC_LxCKCR_CKRED);
+  LTDC_LAYER(hltdc, LayerIdx)->CKCR  = RGBValue;
+
+  /* Set the Immediate Reload type */
+  hltdc->Instance->SRCR = LTDC_SRCR_IMR;
+
+  /* Change the LTDC state*/
+  hltdc->State = HAL_LTDC_STATE_READY;
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hltdc);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Load the color lookup table.
+  * @param  hltdc     pointer to a LTDC_HandleTypeDef structure that contains
+  *                   the configuration information for the LTDC.
+  * @param  pCLUT     pointer to the color lookup table address.
+  * @param  CLUTSize  the color lookup table size.
+  * @param  LayerIdx  LTDC Layer index.
+  *                   This parameter can be one of the following values:
+  *                   LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_LTDC_ConfigCLUT(LTDC_HandleTypeDef *hltdc, uint32_t *pCLUT, uint32_t CLUTSize, uint32_t LayerIdx)
+{
+  uint32_t tmp;
+  uint32_t counter;
+  uint32_t *pcolorlut = pCLUT;
+  /* Check the parameters */
+  assert_param(IS_LTDC_LAYER(LayerIdx));
+
+  /* Process locked */
+  __HAL_LOCK(hltdc);
+
+  /* Change LTDC peripheral state */
+  hltdc->State = HAL_LTDC_STATE_BUSY;
+
+  for (counter = 0U; (counter < CLUTSize); counter++)
+  {
+    if (hltdc->LayerCfg[LayerIdx].PixelFormat == LTDC_PIXEL_FORMAT_AL44)
+    {
+      tmp  = (((counter + (16U * counter)) << 24U) | ((uint32_t)(*pcolorlut) & 0xFFU) | \
+              ((uint32_t)(*pcolorlut) & 0xFF00U) | ((uint32_t)(*pcolorlut) & 0xFF0000U));
+    }
+    else
+    {
+      tmp  = ((counter << 24U) | ((uint32_t)(*pcolorlut) & 0xFFU) | \
+              ((uint32_t)(*pcolorlut) & 0xFF00U) | ((uint32_t)(*pcolorlut) & 0xFF0000U));
+    }
+
+    pcolorlut++;
+
+    /* Specifies the C-LUT address and RGB value */
+    LTDC_LAYER(hltdc, LayerIdx)->CLUTWR  = tmp;
+  }
+
+  /* Change the LTDC state*/
+  hltdc->State = HAL_LTDC_STATE_READY;
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hltdc);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Enable the color keying.
+  * @param  hltdc     pointer to a LTDC_HandleTypeDef structure that contains
+  *                   the configuration information for the LTDC.
+  * @param  LayerIdx  LTDC Layer index.
+  *                   This parameter can be one of the following values:
+  *                   LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
+  * @retval  HAL status
+  */
+HAL_StatusTypeDef HAL_LTDC_EnableColorKeying(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx)
+{
+  /* Check the parameters */
+  assert_param(IS_LTDC_LAYER(LayerIdx));
+
+  /* Process locked */
+  __HAL_LOCK(hltdc);
+
+  /* Change LTDC peripheral state */
+  hltdc->State = HAL_LTDC_STATE_BUSY;
+
+  /* Enable LTDC color keying by setting COLKEN bit */
+  LTDC_LAYER(hltdc, LayerIdx)->CR |= (uint32_t)LTDC_LxCR_COLKEN;
+
+  /* Set the Immediate Reload type */
+  hltdc->Instance->SRCR = LTDC_SRCR_IMR;
+
+  /* Change the LTDC state*/
+  hltdc->State = HAL_LTDC_STATE_READY;
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hltdc);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Disable the color keying.
+  * @param  hltdc     pointer to a LTDC_HandleTypeDef structure that contains
+  *                   the configuration information for the LTDC.
+  * @param  LayerIdx  LTDC Layer index.
+  *                   This parameter can be one of the following values:
+  *                   LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
+  * @retval  HAL status
+  */
+HAL_StatusTypeDef HAL_LTDC_DisableColorKeying(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx)
+{
+  /* Check the parameters */
+  assert_param(IS_LTDC_LAYER(LayerIdx));
+
+  /* Process locked */
+  __HAL_LOCK(hltdc);
+
+  /* Change LTDC peripheral state */
+  hltdc->State = HAL_LTDC_STATE_BUSY;
+
+  /* Disable LTDC color keying by setting COLKEN bit */
+  LTDC_LAYER(hltdc, LayerIdx)->CR &= ~(uint32_t)LTDC_LxCR_COLKEN;
+
+  /* Set the Immediate Reload type */
+  hltdc->Instance->SRCR = LTDC_SRCR_IMR;
+
+  /* Change the LTDC state*/
+  hltdc->State = HAL_LTDC_STATE_READY;
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hltdc);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Enable the color lookup table.
+  * @param  hltdc     pointer to a LTDC_HandleTypeDef structure that contains
+  *                   the configuration information for the LTDC.
+  * @param  LayerIdx  LTDC Layer index.
+  *                   This parameter can be one of the following values:
+  *                   LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
+  * @retval  HAL status
+  */
+HAL_StatusTypeDef HAL_LTDC_EnableCLUT(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx)
+{
+  /* Check the parameters */
+  assert_param(IS_LTDC_LAYER(LayerIdx));
+
+  /* Process locked */
+  __HAL_LOCK(hltdc);
+
+  /* Change LTDC peripheral state */
+  hltdc->State = HAL_LTDC_STATE_BUSY;
+
+  /* Enable LTDC color lookup table by setting CLUTEN bit */
+  LTDC_LAYER(hltdc, LayerIdx)->CR |= (uint32_t)LTDC_LxCR_CLUTEN;
+
+  /* Set the Immediate Reload type */
+  hltdc->Instance->SRCR = LTDC_SRCR_IMR;
+
+  /* Change the LTDC state*/
+  hltdc->State = HAL_LTDC_STATE_READY;
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hltdc);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Disable the color lookup table.
+  * @param  hltdc     pointer to a LTDC_HandleTypeDef structure that contains
+  *                   the configuration information for the LTDC.
+  * @param  LayerIdx  LTDC Layer index.
+  *                   This parameter can be one of the following values:
+  *                   LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
+  * @retval  HAL status
+  */
+HAL_StatusTypeDef HAL_LTDC_DisableCLUT(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx)
+{
+  /* Check the parameters */
+  assert_param(IS_LTDC_LAYER(LayerIdx));
+
+  /* Process locked */
+  __HAL_LOCK(hltdc);
+
+  /* Change LTDC peripheral state */
+  hltdc->State = HAL_LTDC_STATE_BUSY;
+
+  /* Disable LTDC color lookup table by setting CLUTEN bit */
+  LTDC_LAYER(hltdc, LayerIdx)->CR &= ~(uint32_t)LTDC_LxCR_CLUTEN;
+
+  /* Set the Immediate Reload type */
+  hltdc->Instance->SRCR = LTDC_SRCR_IMR;
+
+  /* Change the LTDC state*/
+  hltdc->State = HAL_LTDC_STATE_READY;
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hltdc);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Enable Dither.
+  * @param  hltdc  pointer to a LTDC_HandleTypeDef structure that contains
+  *                the configuration information for the LTDC.
+  * @retval  HAL status
+  */
+
+HAL_StatusTypeDef HAL_LTDC_EnableDither(LTDC_HandleTypeDef *hltdc)
+{
+  /* Process locked */
+  __HAL_LOCK(hltdc);
+
+  /* Change LTDC peripheral state */
+  hltdc->State = HAL_LTDC_STATE_BUSY;
+
+  /* Enable Dither by setting DTEN bit */
+  LTDC->GCR |= (uint32_t)LTDC_GCR_DEN;
+
+  /* Change the LTDC state*/
+  hltdc->State = HAL_LTDC_STATE_READY;
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hltdc);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Disable Dither.
+  * @param  hltdc  pointer to a LTDC_HandleTypeDef structure that contains
+  *                the configuration information for the LTDC.
+  * @retval  HAL status
+  */
+
+HAL_StatusTypeDef HAL_LTDC_DisableDither(LTDC_HandleTypeDef *hltdc)
+{
+  /* Process locked */
+  __HAL_LOCK(hltdc);
+
+  /* Change LTDC peripheral state */
+  hltdc->State = HAL_LTDC_STATE_BUSY;
+
+  /* Disable Dither by setting DTEN bit */
+  LTDC->GCR &= ~(uint32_t)LTDC_GCR_DEN;
+
+  /* Change the LTDC state*/
+  hltdc->State = HAL_LTDC_STATE_READY;
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hltdc);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Set the LTDC window size.
+  * @param  hltdc     pointer to a LTDC_HandleTypeDef structure that contains
+  *                   the configuration information for the LTDC.
+  * @param  XSize     LTDC Pixel per line
+  * @param  YSize     LTDC Line number
+  * @param  LayerIdx  LTDC Layer index.
+  *                   This parameter can be one of the following values:
+  *                   LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
+  * @retval  HAL status
+  */
+HAL_StatusTypeDef HAL_LTDC_SetWindowSize(LTDC_HandleTypeDef *hltdc, uint32_t XSize, uint32_t YSize, uint32_t LayerIdx)
+{
+  LTDC_LayerCfgTypeDef *pLayerCfg;
+
+  /* Check the parameters (Layers parameters)*/
+  assert_param(IS_LTDC_LAYER(LayerIdx));
+  assert_param(IS_LTDC_CFBLL(XSize));
+  assert_param(IS_LTDC_CFBLNBR(YSize));
+
+  /* Process locked */
+  __HAL_LOCK(hltdc);
+
+  /* Change LTDC peripheral state */
+  hltdc->State = HAL_LTDC_STATE_BUSY;
+
+  /* Get layer configuration from handle structure */
+  pLayerCfg = &hltdc->LayerCfg[LayerIdx];
+
+  /* update horizontal stop */
+  pLayerCfg->WindowX1 = XSize + pLayerCfg->WindowX0;
+
+  /* update vertical stop */
+  pLayerCfg->WindowY1 = YSize + pLayerCfg->WindowY0;
+
+  /* Reconfigures the color frame buffer pitch in byte */
+  pLayerCfg->ImageWidth = XSize;
+
+  /* Reconfigures the frame buffer line number */
+  pLayerCfg->ImageHeight = YSize;
+
+  /* Set LTDC parameters */
+  LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx);
+
+  /* Set the Immediate Reload type */
+  hltdc->Instance->SRCR = LTDC_SRCR_IMR;
+
+  /* Change the LTDC state*/
+  hltdc->State = HAL_LTDC_STATE_READY;
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hltdc);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Set the LTDC window position.
+  * @param  hltdc     pointer to a LTDC_HandleTypeDef structure that contains
+  *                   the configuration information for the LTDC.
+  * @param  X0        LTDC window X offset
+  * @param  Y0        LTDC window Y offset
+  * @param  LayerIdx  LTDC Layer index.
+  *                         This parameter can be one of the following values:
+  *                         LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
+  * @retval  HAL status
+  */
+HAL_StatusTypeDef HAL_LTDC_SetWindowPosition(LTDC_HandleTypeDef *hltdc, uint32_t X0, uint32_t Y0, uint32_t LayerIdx)
+{
+  LTDC_LayerCfgTypeDef *pLayerCfg;
+
+  /* Check the parameters */
+  assert_param(IS_LTDC_LAYER(LayerIdx));
+  assert_param(IS_LTDC_CFBLL(X0));
+  assert_param(IS_LTDC_CFBLNBR(Y0));
+
+  /* Process locked */
+  __HAL_LOCK(hltdc);
+
+  /* Change LTDC peripheral state */
+  hltdc->State = HAL_LTDC_STATE_BUSY;
+
+  /* Get layer configuration from handle structure */
+  pLayerCfg = &hltdc->LayerCfg[LayerIdx];
+
+  /* update horizontal start/stop */
+  pLayerCfg->WindowX0 = X0;
+  pLayerCfg->WindowX1 = X0 + pLayerCfg->ImageWidth;
+
+  /* update vertical start/stop */
+  pLayerCfg->WindowY0 = Y0;
+  pLayerCfg->WindowY1 = Y0 + pLayerCfg->ImageHeight;
+
+  /* Set LTDC parameters */
+  LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx);
+
+  /* Set the Immediate Reload type */
+  hltdc->Instance->SRCR = LTDC_SRCR_IMR;
+
+  /* Change the LTDC state*/
+  hltdc->State = HAL_LTDC_STATE_READY;
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hltdc);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Reconfigure the pixel format.
+  * @param  hltdc        pointer to a LTDC_HandleTypeDef structure that contains
+  *                      the configuration information for the LTDC.
+  * @param  Pixelformat  new pixel format value.
+  * @param  LayerIdx     LTDC Layer index.
+  *                      This parameter can be one of the following values:
+  *                      LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1).
+  * @retval  HAL status
+  */
+HAL_StatusTypeDef HAL_LTDC_SetPixelFormat(LTDC_HandleTypeDef *hltdc, uint32_t Pixelformat, uint32_t LayerIdx)
+{
+  LTDC_LayerCfgTypeDef *pLayerCfg;
+
+  /* Check the parameters */
+  assert_param(IS_LTDC_PIXEL_FORMAT(Pixelformat));
+  assert_param(IS_LTDC_LAYER(LayerIdx));
+
+  /* Process locked */
+  __HAL_LOCK(hltdc);
+
+  /* Change LTDC peripheral state */
+  hltdc->State = HAL_LTDC_STATE_BUSY;
+
+  /* Get layer configuration from handle structure */
+  pLayerCfg = &hltdc->LayerCfg[LayerIdx];
+
+  /* Reconfigure the pixel format */
+  pLayerCfg->PixelFormat = Pixelformat;
+
+  /* Set LTDC parameters */
+  LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx);
+
+  /* Set the Immediate Reload type */
+  hltdc->Instance->SRCR = LTDC_SRCR_IMR;
+
+  /* Change the LTDC state*/
+  hltdc->State = HAL_LTDC_STATE_READY;
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hltdc);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Reconfigure the layer alpha value.
+  * @param  hltdc     pointer to a LTDC_HandleTypeDef structure that contains
+  *                   the configuration information for the LTDC.
+  * @param  Alpha     new alpha value.
+  * @param  LayerIdx  LTDC Layer index.
+  *                   This parameter can be one of the following values:
+  *                   LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
+  * @retval  HAL status
+  */
+HAL_StatusTypeDef HAL_LTDC_SetAlpha(LTDC_HandleTypeDef *hltdc, uint32_t Alpha, uint32_t LayerIdx)
+{
+  LTDC_LayerCfgTypeDef *pLayerCfg;
+
+  /* Check the parameters */
+  assert_param(IS_LTDC_ALPHA(Alpha));
+  assert_param(IS_LTDC_LAYER(LayerIdx));
+
+  /* Process locked */
+  __HAL_LOCK(hltdc);
+
+  /* Change LTDC peripheral state */
+  hltdc->State = HAL_LTDC_STATE_BUSY;
+
+  /* Get layer configuration from handle structure */
+  pLayerCfg = &hltdc->LayerCfg[LayerIdx];
+
+  /* Reconfigure the Alpha value */
+  pLayerCfg->Alpha = Alpha;
+
+  /* Set LTDC parameters */
+  LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx);
+
+  /* Set the Immediate Reload type */
+  hltdc->Instance->SRCR = LTDC_SRCR_IMR;
+
+  /* Change the LTDC state*/
+  hltdc->State = HAL_LTDC_STATE_READY;
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hltdc);
+
+  return HAL_OK;
+}
+/**
+  * @brief  Reconfigure the frame buffer Address.
+  * @param  hltdc     pointer to a LTDC_HandleTypeDef structure that contains
+  *                   the configuration information for the LTDC.
+  * @param  Address   new address value.
+  * @param  LayerIdx  LTDC Layer index.
+  *                   This parameter can be one of the following values:
+  *                   LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1).
+  * @retval  HAL status
+  */
+HAL_StatusTypeDef HAL_LTDC_SetAddress(LTDC_HandleTypeDef *hltdc, uint32_t Address, uint32_t LayerIdx)
+{
+  LTDC_LayerCfgTypeDef *pLayerCfg;
+
+  /* Check the parameters */
+  assert_param(IS_LTDC_LAYER(LayerIdx));
+
+  /* Process locked */
+  __HAL_LOCK(hltdc);
+
+  /* Change LTDC peripheral state */
+  hltdc->State = HAL_LTDC_STATE_BUSY;
+
+  /* Get layer configuration from handle structure */
+  pLayerCfg = &hltdc->LayerCfg[LayerIdx];
+
+  /* Reconfigure the Address */
+  pLayerCfg->FBStartAdress = Address;
+
+  /* Set LTDC parameters */
+  LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx);
+
+  /* Set the Immediate Reload type */
+  hltdc->Instance->SRCR = LTDC_SRCR_IMR;
+
+  /* Change the LTDC state*/
+  hltdc->State = HAL_LTDC_STATE_READY;
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hltdc);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Function used to reconfigure the pitch for specific cases where the attached LayerIdx buffer have a width
+  *         that is larger than the one intended to be displayed on screen. Example of a buffer 800x480 attached to
+  *         layer for which we want to read and display on screen only a portion 320x240 taken in the center
+  *         of the buffer.
+  *         The pitch in pixels will be in that case 800 pixels and not 320 pixels as initially configured by previous
+  *         call to HAL_LTDC_ConfigLayer().
+  * @note   This function should be called only after a previous call to HAL_LTDC_ConfigLayer() to modify the default
+  *         pitch configured by HAL_LTDC_ConfigLayer() when required (refer to example described just above).
+  * @param  hltdc              pointer to a LTDC_HandleTypeDef structure that contains
+  *                            the configuration information for the LTDC.
+  * @param  LinePitchInPixels  New line pitch in pixels to configure for LTDC layer 'LayerIdx'.
+  * @param  LayerIdx           LTDC layer index concerned by the modification of line pitch.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_LTDC_SetPitch(LTDC_HandleTypeDef *hltdc, uint32_t LinePitchInPixels, uint32_t LayerIdx)
+{
+  uint32_t tmp;
+  uint32_t pitchUpdate;
+  uint32_t pixelFormat;
+
+  /* Check the parameters */
+  assert_param(IS_LTDC_LAYER(LayerIdx));
+
+  /* Process locked */
+  __HAL_LOCK(hltdc);
+
+  /* Change LTDC peripheral state */
+  hltdc->State = HAL_LTDC_STATE_BUSY;
+
+  /* get LayerIdx used pixel format */
+  pixelFormat = hltdc->LayerCfg[LayerIdx].PixelFormat;
+
+  if (pixelFormat == LTDC_PIXEL_FORMAT_ARGB8888)
+  {
+    tmp = 4U;
+  }
+  else if (pixelFormat == LTDC_PIXEL_FORMAT_RGB888)
+  {
+    tmp = 3U;
+  }
+  else if ((pixelFormat == LTDC_PIXEL_FORMAT_ARGB4444) || \
+           (pixelFormat == LTDC_PIXEL_FORMAT_RGB565)   || \
+           (pixelFormat == LTDC_PIXEL_FORMAT_ARGB1555) || \
+           (pixelFormat == LTDC_PIXEL_FORMAT_AL88))
+  {
+    tmp = 2U;
+  }
+  else
+  {
+    tmp = 1U;
+  }
+
+  pitchUpdate = ((LinePitchInPixels * tmp) << 16U);
+
+  /* Clear previously set standard pitch */
+  LTDC_LAYER(hltdc, LayerIdx)->CFBLR &= ~LTDC_LxCFBLR_CFBP;
+
+  /* Set the Reload type as immediate update of LTDC pitch configured above */
+  LTDC->SRCR |= LTDC_SRCR_IMR;
+
+  /* Set new line pitch value */
+  LTDC_LAYER(hltdc, LayerIdx)->CFBLR |= pitchUpdate;
+
+  /* Set the Reload type as immediate update of LTDC pitch configured above */
+  LTDC->SRCR |= LTDC_SRCR_IMR;
+
+  /* Change the LTDC state*/
+  hltdc->State = HAL_LTDC_STATE_READY;
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hltdc);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Define the position of the line interrupt.
+  * @param  hltdc   pointer to a LTDC_HandleTypeDef structure that contains
+  *                 the configuration information for the LTDC.
+  * @param  Line    Line Interrupt Position.
+  * @note   User application may resort to HAL_LTDC_LineEventCallback() at line interrupt generation.
+  * @retval  HAL status
+  */
+HAL_StatusTypeDef HAL_LTDC_ProgramLineEvent(LTDC_HandleTypeDef *hltdc, uint32_t Line)
+{
+  /* Check the parameters */
+  assert_param(IS_LTDC_LIPOS(Line));
+
+  /* Process locked */
+  __HAL_LOCK(hltdc);
+
+  /* Change LTDC peripheral state */
+  hltdc->State = HAL_LTDC_STATE_BUSY;
+
+  /* Disable the Line interrupt */
+  __HAL_LTDC_DISABLE_IT(hltdc, LTDC_IT_LI);
+
+  /* Set the Line Interrupt position */
+  LTDC->LIPCR = (uint32_t)Line;
+
+  /* Enable the Line interrupt */
+  __HAL_LTDC_ENABLE_IT(hltdc, LTDC_IT_LI);
+
+  /* Change the LTDC state*/
+  hltdc->State = HAL_LTDC_STATE_READY;
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hltdc);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Reload LTDC Layers configuration.
+  * @param  hltdc      pointer to a LTDC_HandleTypeDef structure that contains
+  *                    the configuration information for the LTDC.
+  * @param  ReloadType This parameter can be one of the following values :
+  *                      LTDC_RELOAD_IMMEDIATE : Immediate Reload
+  *                      LTDC_RELOAD_VERTICAL_BLANKING  : Reload in the next Vertical Blanking
+  * @note   User application may resort to HAL_LTDC_ReloadEventCallback() at reload interrupt generation.
+  * @retval  HAL status
+  */
+HAL_StatusTypeDef  HAL_LTDC_Reload(LTDC_HandleTypeDef *hltdc, uint32_t ReloadType)
+{
+  /* Check the parameters */
+  assert_param(IS_LTDC_RELOAD(ReloadType));
+
+  /* Process locked */
+  __HAL_LOCK(hltdc);
+
+  /* Change LTDC peripheral state */
+  hltdc->State = HAL_LTDC_STATE_BUSY;
+
+  /* Enable the Reload interrupt */
+  __HAL_LTDC_ENABLE_IT(hltdc, LTDC_IT_RR);
+
+  /* Apply Reload type */
+  hltdc->Instance->SRCR = ReloadType;
+
+  /* Change the LTDC state*/
+  hltdc->State = HAL_LTDC_STATE_READY;
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hltdc);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Configure the LTDC Layer according to the specified without reloading
+  *         parameters in the LTDC_InitTypeDef and create the associated handle.
+  *         Variant of the function HAL_LTDC_ConfigLayer without immediate reload.
+  * @param  hltdc      pointer to a LTDC_HandleTypeDef structure that contains
+  *                    the configuration information for the LTDC.
+  * @param  pLayerCfg  pointer to a LTDC_LayerCfgTypeDef structure that contains
+  *                    the configuration information for the Layer.
+  * @param  LayerIdx   LTDC Layer index.
+  *                    This parameter can be one of the following values:
+  *                    LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_LTDC_ConfigLayer_NoReload(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg,
+                                                uint32_t LayerIdx)
+{
+  /* Check the parameters */
+  assert_param(IS_LTDC_LAYER(LayerIdx));
+  assert_param(IS_LTDC_HCONFIGST(pLayerCfg->WindowX0));
+  assert_param(IS_LTDC_HCONFIGSP(pLayerCfg->WindowX1));
+  assert_param(IS_LTDC_VCONFIGST(pLayerCfg->WindowY0));
+  assert_param(IS_LTDC_VCONFIGSP(pLayerCfg->WindowY1));
+  assert_param(IS_LTDC_PIXEL_FORMAT(pLayerCfg->PixelFormat));
+  assert_param(IS_LTDC_ALPHA(pLayerCfg->Alpha));
+  assert_param(IS_LTDC_ALPHA(pLayerCfg->Alpha0));
+  assert_param(IS_LTDC_BLENDING_FACTOR1(pLayerCfg->BlendingFactor1));
+  assert_param(IS_LTDC_BLENDING_FACTOR2(pLayerCfg->BlendingFactor2));
+  assert_param(IS_LTDC_CFBLL(pLayerCfg->ImageWidth));
+  assert_param(IS_LTDC_CFBLNBR(pLayerCfg->ImageHeight));
+
+  /* Process locked */
+  __HAL_LOCK(hltdc);
+
+  /* Change LTDC peripheral state */
+  hltdc->State = HAL_LTDC_STATE_BUSY;
+
+  /* Copy new layer configuration into handle structure */
+  hltdc->LayerCfg[LayerIdx] = *pLayerCfg;
+
+  /* Configure the LTDC Layer */
+  LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx);
+
+  /* Initialize the LTDC state*/
+  hltdc->State  = HAL_LTDC_STATE_READY;
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hltdc);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Set the LTDC window size without reloading.
+  *         Variant of the function HAL_LTDC_SetWindowSize without immediate reload.
+  * @param  hltdc     pointer to a LTDC_HandleTypeDef structure that contains
+  *                   the configuration information for the LTDC.
+  * @param  XSize     LTDC Pixel per line
+  * @param  YSize     LTDC Line number
+  * @param  LayerIdx  LTDC Layer index.
+  *                   This parameter can be one of the following values:
+  *                   LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
+  * @retval  HAL status
+  */
+HAL_StatusTypeDef HAL_LTDC_SetWindowSize_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t XSize, uint32_t YSize,
+                                                  uint32_t LayerIdx)
+{
+  LTDC_LayerCfgTypeDef *pLayerCfg;
+
+  /* Check the parameters (Layers parameters)*/
+  assert_param(IS_LTDC_LAYER(LayerIdx));
+  assert_param(IS_LTDC_CFBLL(XSize));
+  assert_param(IS_LTDC_CFBLNBR(YSize));
+
+  /* Process locked */
+  __HAL_LOCK(hltdc);
+
+  /* Change LTDC peripheral state */
+  hltdc->State = HAL_LTDC_STATE_BUSY;
+
+  /* Get layer configuration from handle structure */
+  pLayerCfg = &hltdc->LayerCfg[LayerIdx];
+
+  /* update horizontal stop */
+  pLayerCfg->WindowX1 = XSize + pLayerCfg->WindowX0;
+
+  /* update vertical stop */
+  pLayerCfg->WindowY1 = YSize + pLayerCfg->WindowY0;
+
+  /* Reconfigures the color frame buffer pitch in byte */
+  pLayerCfg->ImageWidth = XSize;
+
+  /* Reconfigures the frame buffer line number */
+  pLayerCfg->ImageHeight = YSize;
+
+  /* Set LTDC parameters */
+  LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx);
+
+  /* Change the LTDC state*/
+  hltdc->State = HAL_LTDC_STATE_READY;
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hltdc);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Set the LTDC window position without reloading.
+  *         Variant of the function HAL_LTDC_SetWindowPosition without immediate reload.
+  * @param  hltdc     pointer to a LTDC_HandleTypeDef structure that contains
+  *                   the configuration information for the LTDC.
+  * @param  X0        LTDC window X offset
+  * @param  Y0        LTDC window Y offset
+  * @param  LayerIdx  LTDC Layer index.
+  *                         This parameter can be one of the following values:
+  *                         LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
+  * @retval  HAL status
+  */
+HAL_StatusTypeDef HAL_LTDC_SetWindowPosition_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t X0, uint32_t Y0,
+                                                      uint32_t LayerIdx)
+{
+  LTDC_LayerCfgTypeDef *pLayerCfg;
+
+  /* Check the parameters */
+  assert_param(IS_LTDC_LAYER(LayerIdx));
+  assert_param(IS_LTDC_CFBLL(X0));
+  assert_param(IS_LTDC_CFBLNBR(Y0));
+
+  /* Process locked */
+  __HAL_LOCK(hltdc);
+
+  /* Change LTDC peripheral state */
+  hltdc->State = HAL_LTDC_STATE_BUSY;
+
+  /* Get layer configuration from handle structure */
+  pLayerCfg = &hltdc->LayerCfg[LayerIdx];
+
+  /* update horizontal start/stop */
+  pLayerCfg->WindowX0 = X0;
+  pLayerCfg->WindowX1 = X0 + pLayerCfg->ImageWidth;
+
+  /* update vertical start/stop */
+  pLayerCfg->WindowY0 = Y0;
+  pLayerCfg->WindowY1 = Y0 + pLayerCfg->ImageHeight;
+
+  /* Set LTDC parameters */
+  LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx);
+
+  /* Change the LTDC state*/
+  hltdc->State = HAL_LTDC_STATE_READY;
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hltdc);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Reconfigure the pixel format without reloading.
+  *         Variant of the function HAL_LTDC_SetPixelFormat without immediate reload.
+  * @param  hltdc        pointer to a LTDC_HandleTypeDfef structure that contains
+  *                      the configuration information for the LTDC.
+  * @param  Pixelformat  new pixel format value.
+  * @param  LayerIdx     LTDC Layer index.
+  *                      This parameter can be one of the following values:
+  *                      LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1).
+  * @retval  HAL status
+  */
+HAL_StatusTypeDef HAL_LTDC_SetPixelFormat_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t Pixelformat, uint32_t LayerIdx)
+{
+  LTDC_LayerCfgTypeDef *pLayerCfg;
+
+  /* Check the parameters */
+  assert_param(IS_LTDC_PIXEL_FORMAT(Pixelformat));
+  assert_param(IS_LTDC_LAYER(LayerIdx));
+
+  /* Process locked */
+  __HAL_LOCK(hltdc);
+
+  /* Change LTDC peripheral state */
+  hltdc->State = HAL_LTDC_STATE_BUSY;
+
+  /* Get layer configuration from handle structure */
+  pLayerCfg = &hltdc->LayerCfg[LayerIdx];
+
+  /* Reconfigure the pixel format */
+  pLayerCfg->PixelFormat = Pixelformat;
+
+  /* Set LTDC parameters */
+  LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx);
+
+  /* Change the LTDC state*/
+  hltdc->State = HAL_LTDC_STATE_READY;
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hltdc);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Reconfigure the layer alpha value without reloading.
+  *         Variant of the function HAL_LTDC_SetAlpha without immediate reload.
+  * @param  hltdc     pointer to a LTDC_HandleTypeDef structure that contains
+  *                   the configuration information for the LTDC.
+  * @param  Alpha     new alpha value.
+  * @param  LayerIdx  LTDC Layer index.
+  *                   This parameter can be one of the following values:
+  *                   LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
+  * @retval  HAL status
+  */
+HAL_StatusTypeDef HAL_LTDC_SetAlpha_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t Alpha, uint32_t LayerIdx)
+{
+  LTDC_LayerCfgTypeDef *pLayerCfg;
+
+  /* Check the parameters */
+  assert_param(IS_LTDC_ALPHA(Alpha));
+  assert_param(IS_LTDC_LAYER(LayerIdx));
+
+  /* Process locked */
+  __HAL_LOCK(hltdc);
+
+  /* Change LTDC peripheral state */
+  hltdc->State = HAL_LTDC_STATE_BUSY;
+
+  /* Get layer configuration from handle structure */
+  pLayerCfg = &hltdc->LayerCfg[LayerIdx];
+
+  /* Reconfigure the Alpha value */
+  pLayerCfg->Alpha = Alpha;
+
+  /* Set LTDC parameters */
+  LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx);
+
+  /* Change the LTDC state*/
+  hltdc->State = HAL_LTDC_STATE_READY;
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hltdc);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Reconfigure the frame buffer Address without reloading.
+  *         Variant of the function HAL_LTDC_SetAddress without immediate reload.
+  * @param  hltdc     pointer to a LTDC_HandleTypeDef structure that contains
+  *                   the configuration information for the LTDC.
+  * @param  Address   new address value.
+  * @param  LayerIdx  LTDC Layer index.
+  *                   This parameter can be one of the following values:
+  *                   LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1).
+  * @retval  HAL status
+  */
+HAL_StatusTypeDef HAL_LTDC_SetAddress_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t Address, uint32_t LayerIdx)
+{
+  LTDC_LayerCfgTypeDef *pLayerCfg;
+
+  /* Check the parameters */
+  assert_param(IS_LTDC_LAYER(LayerIdx));
+
+  /* Process locked */
+  __HAL_LOCK(hltdc);
+
+  /* Change LTDC peripheral state */
+  hltdc->State = HAL_LTDC_STATE_BUSY;
+
+  /* Get layer configuration from handle structure */
+  pLayerCfg = &hltdc->LayerCfg[LayerIdx];
+
+  /* Reconfigure the Address */
+  pLayerCfg->FBStartAdress = Address;
+
+  /* Set LTDC parameters */
+  LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx);
+
+  /* Change the LTDC state*/
+  hltdc->State = HAL_LTDC_STATE_READY;
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hltdc);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Function used to reconfigure the pitch for specific cases where the attached LayerIdx buffer have a width
+  *         that is larger than the one intended to be displayed on screen. Example of a buffer 800x480 attached to
+  *         layer for which we want to read and display on screen only a portion 320x240 taken in the center
+  *         of the buffer.
+  *         The pitch in pixels will be in that case 800 pixels and not 320 pixels as initially configured by
+  *         previous call to HAL_LTDC_ConfigLayer().
+  * @note   This function should be called only after a previous call to HAL_LTDC_ConfigLayer() to modify the default
+  *         pitch configured by HAL_LTDC_ConfigLayer() when required (refer to example described just above).
+  *         Variant of the function HAL_LTDC_SetPitch without immediate reload.
+  * @param  hltdc              pointer to a LTDC_HandleTypeDef structure that contains
+  *                            the configuration information for the LTDC.
+  * @param  LinePitchInPixels  New line pitch in pixels to configure for LTDC layer 'LayerIdx'.
+  * @param  LayerIdx           LTDC layer index concerned by the modification of line pitch.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_LTDC_SetPitch_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LinePitchInPixels, uint32_t LayerIdx)
+{
+  uint32_t tmp;
+  uint32_t pitchUpdate;
+  uint32_t pixelFormat;
+
+  /* Check the parameters */
+  assert_param(IS_LTDC_LAYER(LayerIdx));
+
+  /* Process locked */
+  __HAL_LOCK(hltdc);
+
+  /* Change LTDC peripheral state */
+  hltdc->State = HAL_LTDC_STATE_BUSY;
+
+  /* get LayerIdx used pixel format */
+  pixelFormat = hltdc->LayerCfg[LayerIdx].PixelFormat;
+
+  if (pixelFormat == LTDC_PIXEL_FORMAT_ARGB8888)
+  {
+    tmp = 4U;
+  }
+  else if (pixelFormat == LTDC_PIXEL_FORMAT_RGB888)
+  {
+    tmp = 3U;
+  }
+  else if ((pixelFormat == LTDC_PIXEL_FORMAT_ARGB4444) || \
+           (pixelFormat == LTDC_PIXEL_FORMAT_RGB565)   || \
+           (pixelFormat == LTDC_PIXEL_FORMAT_ARGB1555) || \
+           (pixelFormat == LTDC_PIXEL_FORMAT_AL88))
+  {
+    tmp = 2U;
+  }
+  else
+  {
+    tmp = 1U;
+  }
+
+  pitchUpdate = ((LinePitchInPixels * tmp) << 16U);
+
+  /* Clear previously set standard pitch */
+  LTDC_LAYER(hltdc, LayerIdx)->CFBLR &= ~LTDC_LxCFBLR_CFBP;
+
+  /* Set new line pitch value */
+  LTDC_LAYER(hltdc, LayerIdx)->CFBLR |= pitchUpdate;
+
+  /* Change the LTDC state*/
+  hltdc->State = HAL_LTDC_STATE_READY;
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hltdc);
+
+  return HAL_OK;
+}
+
+
+/**
+  * @brief  Configure the color keying without reloading.
+  *         Variant of the function HAL_LTDC_ConfigColorKeying without immediate reload.
+  * @param  hltdc     pointer to a LTDC_HandleTypeDef structure that contains
+  *                   the configuration information for the LTDC.
+  * @param  RGBValue the color key value
+  * @param  LayerIdx  LTDC Layer index.
+  *                   This parameter can be one of the following values:
+  *                   LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_LTDC_ConfigColorKeying_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t RGBValue, uint32_t LayerIdx)
+{
+  /* Check the parameters */
+  assert_param(IS_LTDC_LAYER(LayerIdx));
+
+  /* Process locked */
+  __HAL_LOCK(hltdc);
+
+  /* Change LTDC peripheral state */
+  hltdc->State = HAL_LTDC_STATE_BUSY;
+
+  /* Configure the default color values */
+  LTDC_LAYER(hltdc, LayerIdx)->CKCR &=  ~(LTDC_LxCKCR_CKBLUE | LTDC_LxCKCR_CKGREEN | LTDC_LxCKCR_CKRED);
+  LTDC_LAYER(hltdc, LayerIdx)->CKCR  = RGBValue;
+
+  /* Change the LTDC state*/
+  hltdc->State = HAL_LTDC_STATE_READY;
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hltdc);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Enable the color keying without reloading.
+  *         Variant of the function HAL_LTDC_EnableColorKeying without immediate reload.
+  * @param  hltdc     pointer to a LTDC_HandleTypeDef structure that contains
+  *                   the configuration information for the LTDC.
+  * @param  LayerIdx  LTDC Layer index.
+  *                   This parameter can be one of the following values:
+  *                   LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
+  * @retval  HAL status
+  */
+HAL_StatusTypeDef HAL_LTDC_EnableColorKeying_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx)
+{
+  /* Check the parameters */
+  assert_param(IS_LTDC_LAYER(LayerIdx));
+
+  /* Process locked */
+  __HAL_LOCK(hltdc);
+
+  /* Change LTDC peripheral state */
+  hltdc->State = HAL_LTDC_STATE_BUSY;
+
+  /* Enable LTDC color keying by setting COLKEN bit */
+  LTDC_LAYER(hltdc, LayerIdx)->CR |= (uint32_t)LTDC_LxCR_COLKEN;
+
+  /* Change the LTDC state*/
+  hltdc->State = HAL_LTDC_STATE_READY;
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hltdc);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Disable the color keying without reloading.
+  *         Variant of the function HAL_LTDC_DisableColorKeying without immediate reload.
+  * @param  hltdc     pointer to a LTDC_HandleTypeDef structure that contains
+  *                   the configuration information for the LTDC.
+  * @param  LayerIdx  LTDC Layer index.
+  *                   This parameter can be one of the following values:
+  *                   LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
+  * @retval  HAL status
+  */
+HAL_StatusTypeDef HAL_LTDC_DisableColorKeying_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx)
+{
+  /* Check the parameters */
+  assert_param(IS_LTDC_LAYER(LayerIdx));
+
+  /* Process locked */
+  __HAL_LOCK(hltdc);
+
+  /* Change LTDC peripheral state */
+  hltdc->State = HAL_LTDC_STATE_BUSY;
+
+  /* Disable LTDC color keying by setting COLKEN bit */
+  LTDC_LAYER(hltdc, LayerIdx)->CR &= ~(uint32_t)LTDC_LxCR_COLKEN;
+
+  /* Change the LTDC state*/
+  hltdc->State = HAL_LTDC_STATE_READY;
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hltdc);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Enable the color lookup table without reloading.
+  *         Variant of the function HAL_LTDC_EnableCLUT without immediate reload.
+  * @param  hltdc     pointer to a LTDC_HandleTypeDef structure that contains
+  *                   the configuration information for the LTDC.
+  * @param  LayerIdx  LTDC Layer index.
+  *                   This parameter can be one of the following values:
+  *                   LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
+  * @retval  HAL status
+  */
+HAL_StatusTypeDef HAL_LTDC_EnableCLUT_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx)
+{
+  /* Check the parameters */
+  assert_param(IS_LTDC_LAYER(LayerIdx));
+
+  /* Process locked */
+  __HAL_LOCK(hltdc);
+
+  /* Change LTDC peripheral state */
+  hltdc->State = HAL_LTDC_STATE_BUSY;
+
+  /* Disable LTDC color lookup table by setting CLUTEN bit */
+  LTDC_LAYER(hltdc, LayerIdx)->CR |= (uint32_t)LTDC_LxCR_CLUTEN;
+
+  /* Change the LTDC state*/
+  hltdc->State = HAL_LTDC_STATE_READY;
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hltdc);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Disable the color lookup table without reloading.
+  *         Variant of the function HAL_LTDC_DisableCLUT without immediate reload.
+  * @param  hltdc     pointer to a LTDC_HandleTypeDef structure that contains
+  *                   the configuration information for the LTDC.
+  * @param  LayerIdx  LTDC Layer index.
+  *                   This parameter can be one of the following values:
+  *                   LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
+  * @retval  HAL status
+  */
+HAL_StatusTypeDef HAL_LTDC_DisableCLUT_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx)
+{
+  /* Check the parameters */
+  assert_param(IS_LTDC_LAYER(LayerIdx));
+
+  /* Process locked */
+  __HAL_LOCK(hltdc);
+
+  /* Change LTDC peripheral state */
+  hltdc->State = HAL_LTDC_STATE_BUSY;
+
+  /* Disable LTDC color lookup table by setting CLUTEN bit */
+  LTDC_LAYER(hltdc, LayerIdx)->CR &= ~(uint32_t)LTDC_LxCR_CLUTEN;
+
+  /* Change the LTDC state*/
+  hltdc->State = HAL_LTDC_STATE_READY;
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hltdc);
+
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup LTDC_Exported_Functions_Group4 Peripheral State and Errors functions
+  *  @brief    Peripheral State and Errors functions
+  *
+@verbatim
+ ===============================================================================
+                  ##### Peripheral State and Errors functions #####
+ ===============================================================================
+    [..]
+    This subsection provides functions allowing to
+      (+) Check the LTDC handle state.
+      (+) Get the LTDC handle error code.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Return the LTDC handle state.
+  * @param  hltdc  pointer to a LTDC_HandleTypeDef structure that contains
+  *                the configuration information for the LTDC.
+  * @retval HAL state
+  */
+HAL_LTDC_StateTypeDef HAL_LTDC_GetState(LTDC_HandleTypeDef *hltdc)
+{
+  return hltdc->State;
+}
+
+/**
+  * @brief  Return the LTDC handle error code.
+  * @param  hltdc  pointer to a LTDC_HandleTypeDef structure that contains
+  *               the configuration information for the LTDC.
+  * @retval LTDC Error Code
+  */
+uint32_t HAL_LTDC_GetError(LTDC_HandleTypeDef *hltdc)
+{
+  return hltdc->ErrorCode;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup LTDC_Private_Functions LTDC Private Functions
+  * @{
+  */
+
+/**
+  * @brief  Configure the LTDC peripheral
+  * @param  hltdc     Pointer to a LTDC_HandleTypeDef structure that contains
+  *                   the configuration information for the LTDC.
+  * @param  pLayerCfg Pointer LTDC Layer Configuration structure
+  * @param  LayerIdx  LTDC Layer index.
+  *                   This parameter can be one of the following values: LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
+  * @retval None
+  */
+static void LTDC_SetConfig(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg, uint32_t LayerIdx)
+{
+  uint32_t tmp;
+  uint32_t tmp1;
+  uint32_t tmp2;
+
+  /* Configure the horizontal start and stop position */
+  tmp = ((pLayerCfg->WindowX1 + ((hltdc->Instance->BPCR & LTDC_BPCR_AHBP) >> 16U)) << 16U);
+  LTDC_LAYER(hltdc, LayerIdx)->WHPCR &= ~(LTDC_LxWHPCR_WHSTPOS | LTDC_LxWHPCR_WHSPPOS);
+  LTDC_LAYER(hltdc, LayerIdx)->WHPCR = ((pLayerCfg->WindowX0 + \
+                                         ((hltdc->Instance->BPCR & LTDC_BPCR_AHBP) >> 16U) + 1U) | tmp);
+
+  /* Configure the vertical start and stop position */
+  tmp = ((pLayerCfg->WindowY1 + (hltdc->Instance->BPCR & LTDC_BPCR_AVBP)) << 16U);
+  LTDC_LAYER(hltdc, LayerIdx)->WVPCR &= ~(LTDC_LxWVPCR_WVSTPOS | LTDC_LxWVPCR_WVSPPOS);
+  LTDC_LAYER(hltdc, LayerIdx)->WVPCR  = ((pLayerCfg->WindowY0 + (hltdc->Instance->BPCR & LTDC_BPCR_AVBP) + 1U) | tmp);
+
+  /* Specifies the pixel format */
+  LTDC_LAYER(hltdc, LayerIdx)->PFCR &= ~(LTDC_LxPFCR_PF);
+  LTDC_LAYER(hltdc, LayerIdx)->PFCR = (pLayerCfg->PixelFormat);
+
+  /* Configure the default color values */
+  tmp = ((uint32_t)(pLayerCfg->Backcolor.Green) << 8U);
+  tmp1 = ((uint32_t)(pLayerCfg->Backcolor.Red) << 16U);
+  tmp2 = (pLayerCfg->Alpha0 << 24U);
+  LTDC_LAYER(hltdc, LayerIdx)->DCCR &= ~(LTDC_LxDCCR_DCBLUE | LTDC_LxDCCR_DCGREEN | LTDC_LxDCCR_DCRED |
+                                         LTDC_LxDCCR_DCALPHA);
+  LTDC_LAYER(hltdc, LayerIdx)->DCCR = (pLayerCfg->Backcolor.Blue | tmp | tmp1 | tmp2);
+
+  /* Specifies the constant alpha value */
+  LTDC_LAYER(hltdc, LayerIdx)->CACR &= ~(LTDC_LxCACR_CONSTA);
+  LTDC_LAYER(hltdc, LayerIdx)->CACR = (pLayerCfg->Alpha);
+
+  /* Specifies the blending factors */
+  LTDC_LAYER(hltdc, LayerIdx)->BFCR &= ~(LTDC_LxBFCR_BF2 | LTDC_LxBFCR_BF1);
+  LTDC_LAYER(hltdc, LayerIdx)->BFCR = (pLayerCfg->BlendingFactor1 | pLayerCfg->BlendingFactor2);
+
+  /* Configure the color frame buffer start address */
+  LTDC_LAYER(hltdc, LayerIdx)->CFBAR &= ~(LTDC_LxCFBAR_CFBADD);
+  LTDC_LAYER(hltdc, LayerIdx)->CFBAR = (pLayerCfg->FBStartAdress);
+
+  if (pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_ARGB8888)
+  {
+    tmp = 4U;
+  }
+  else if (pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_RGB888)
+  {
+    tmp = 3U;
+  }
+  else if ((pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_ARGB4444) || \
+           (pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_RGB565)   || \
+           (pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_ARGB1555) || \
+           (pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_AL88))
+  {
+    tmp = 2U;
+  }
+  else
+  {
+    tmp = 1U;
+  }
+
+  /* Configure the color frame buffer pitch in byte */
+  LTDC_LAYER(hltdc, LayerIdx)->CFBLR  &= ~(LTDC_LxCFBLR_CFBLL | LTDC_LxCFBLR_CFBP);
+  LTDC_LAYER(hltdc, LayerIdx)->CFBLR  = (((pLayerCfg->ImageWidth * tmp) << 16U) | \
+                                         (((pLayerCfg->WindowX1 - pLayerCfg->WindowX0) * tmp)  + 3U));
+  /* Configure the frame buffer line number */
+  LTDC_LAYER(hltdc, LayerIdx)->CFBLNR  &= ~(LTDC_LxCFBLNR_CFBLNBR);
+  LTDC_LAYER(hltdc, LayerIdx)->CFBLNR  = (pLayerCfg->ImageHeight);
+
+  /* Enable LTDC_Layer by setting LEN bit */
+  LTDC_LAYER(hltdc, LayerIdx)->CR |= (uint32_t)LTDC_LxCR_LEN;
+}
+
+/**
+  * @}
+  */
+
+
+/**
+  * @}
+  */
+
+#endif /* LTDC */
+
+#endif /* HAL_LTDC_MODULE_ENABLED */
+
+/**
+  * @}
+  */
+
diff --git a/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_ltdc_ex.c b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_ltdc_ex.c
new file mode 100644
index 0000000..eda523f
--- /dev/null
+++ b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_ltdc_ex.c
@@ -0,0 +1,151 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hal_ltdc_ex.c
+  * @author  MCD Application Team
+  * @brief   LTDC Extension HAL module driver.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2016 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+  * @{
+  */
+
+#if defined(HAL_LTDC_MODULE_ENABLED) && defined(HAL_DSI_MODULE_ENABLED)
+
+#if defined (LTDC) && defined (DSI)
+
+/** @defgroup LTDCEx LTDCEx
+  * @brief LTDC HAL module driver
+  * @{
+  */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup LTDCEx_Exported_Functions LTDC Extended Exported Functions
+  * @{
+  */
+
+/** @defgroup LTDCEx_Exported_Functions_Group1 Initialization and Configuration functions
+  *  @brief   Initialization and Configuration functions
+  *
+@verbatim
+ ===============================================================================
+                ##### Initialization and Configuration functions #####
+ ===============================================================================
+    [..]  This section provides functions allowing to:
+      (+) Initialize and configure the LTDC
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Retrieve common parameters from DSI Video mode configuration structure
+  * @param  hltdc   pointer to a LTDC_HandleTypeDef structure that contains
+  *                 the configuration information for the LTDC.
+  * @param  VidCfg  pointer to a DSI_VidCfgTypeDef structure that contains
+  *                 the DSI video mode configuration parameters
+  * @note   The implementation of this function is taking into account the LTDC
+  *         polarities inversion as described in the current LTDC specification
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_LTDCEx_StructInitFromVideoConfig(LTDC_HandleTypeDef *hltdc, DSI_VidCfgTypeDef *VidCfg)
+{
+  /* Retrieve signal polarities from DSI */
+
+  /* The following polarity is inverted:
+                     LTDC_DEPOLARITY_AL <-> LTDC_DEPOLARITY_AH */
+
+  /* Note 1 : Code in line w/ Current LTDC specification */
+  hltdc->Init.DEPolarity = (VidCfg->DEPolarity == \
+                            DSI_DATA_ENABLE_ACTIVE_HIGH) ? LTDC_DEPOLARITY_AL : LTDC_DEPOLARITY_AH;
+  hltdc->Init.VSPolarity = (VidCfg->VSPolarity == DSI_VSYNC_ACTIVE_HIGH) ? LTDC_VSPOLARITY_AH : LTDC_VSPOLARITY_AL;
+  hltdc->Init.HSPolarity = (VidCfg->HSPolarity == DSI_HSYNC_ACTIVE_HIGH) ? LTDC_HSPOLARITY_AH : LTDC_HSPOLARITY_AL;
+
+  /* Note 2: Code to be used in case LTDC polarities inversion updated in the specification */
+  /* hltdc->Init.DEPolarity = VidCfg->DEPolarity << 29;
+     hltdc->Init.VSPolarity = VidCfg->VSPolarity << 29;
+     hltdc->Init.HSPolarity = VidCfg->HSPolarity << 29; */
+
+  /* Retrieve vertical timing parameters from DSI */
+  hltdc->Init.VerticalSync       = VidCfg->VerticalSyncActive - 1U;
+  hltdc->Init.AccumulatedVBP     = VidCfg->VerticalSyncActive + VidCfg->VerticalBackPorch - 1U;
+  hltdc->Init.AccumulatedActiveH = VidCfg->VerticalSyncActive + VidCfg->VerticalBackPorch + \
+                                   VidCfg->VerticalActive - 1U;
+  hltdc->Init.TotalHeigh         = VidCfg->VerticalSyncActive + VidCfg->VerticalBackPorch + \
+                                   VidCfg->VerticalActive + VidCfg->VerticalFrontPorch - 1U;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Retrieve common parameters from DSI Adapted command mode configuration structure
+  * @param  hltdc   pointer to a LTDC_HandleTypeDef structure that contains
+  *                 the configuration information for the LTDC.
+  * @param  CmdCfg  pointer to a DSI_CmdCfgTypeDef structure that contains
+  *                 the DSI command mode configuration parameters
+  * @note   The implementation of this function is taking into account the LTDC
+  *         polarities inversion as described in the current LTDC specification
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_LTDCEx_StructInitFromAdaptedCommandConfig(LTDC_HandleTypeDef *hltdc, DSI_CmdCfgTypeDef *CmdCfg)
+{
+  /* Retrieve signal polarities from DSI */
+
+  /* The following polarities are inverted:
+                     LTDC_DEPOLARITY_AL <-> LTDC_DEPOLARITY_AH
+                     LTDC_VSPOLARITY_AL <-> LTDC_VSPOLARITY_AH
+                     LTDC_HSPOLARITY_AL <-> LTDC_HSPOLARITY_AH)*/
+
+  /* Note 1 : Code in line w/ Current LTDC specification */
+  hltdc->Init.DEPolarity = (CmdCfg->DEPolarity == \
+                            DSI_DATA_ENABLE_ACTIVE_HIGH) ? LTDC_DEPOLARITY_AL : LTDC_DEPOLARITY_AH;
+  hltdc->Init.VSPolarity = (CmdCfg->VSPolarity == DSI_VSYNC_ACTIVE_HIGH) ? LTDC_VSPOLARITY_AL : LTDC_VSPOLARITY_AH;
+  hltdc->Init.HSPolarity = (CmdCfg->HSPolarity == DSI_HSYNC_ACTIVE_HIGH) ? LTDC_HSPOLARITY_AL : LTDC_HSPOLARITY_AH;
+
+  /* Note 2: Code to be used in case LTDC polarities inversion updated in the specification */
+  /* hltdc->Init.DEPolarity = CmdCfg->DEPolarity << 29;
+     hltdc->Init.VSPolarity = CmdCfg->VSPolarity << 29;
+     hltdc->Init.HSPolarity = CmdCfg->HSPolarity << 29; */
+
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* LTDC && DSI */
+
+#endif /* HAL_LTCD_MODULE_ENABLED && HAL_DSI_MODULE_ENABLED */
+
+/**
+  * @}
+  */
+
diff --git a/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c
new file mode 100644
index 0000000..bf60fc0
--- /dev/null
+++ b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c
@@ -0,0 +1,571 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hal_pwr.c
+  * @author  MCD Application Team
+  * @brief   PWR HAL module driver.
+  *          This file provides firmware functions to manage the following 
+  *          functionalities of the Power Controller (PWR) peripheral:
+  *           + Initialization and de-initialization functions
+  *           + Peripheral Control functions 
+  *         
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file in
+  * the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  ******************************************************************************
+  */ 
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup PWR PWR
+  * @brief PWR HAL module driver
+  * @{
+  */
+
+#ifdef HAL_PWR_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @addtogroup PWR_Private_Constants
+  * @{
+  */
+  
+/** @defgroup PWR_PVD_Mode_Mask PWR PVD Mode Mask
+  * @{
+  */     
+#define PVD_MODE_IT               0x00010000U
+#define PVD_MODE_EVT              0x00020000U
+#define PVD_RISING_EDGE           0x00000001U
+#define PVD_FALLING_EDGE          0x00000002U
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */    
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup PWR_Exported_Functions PWR Exported Functions
+  * @{
+  */
+
+/** @defgroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions 
+  *  @brief    Initialization and de-initialization functions
+  *
+@verbatim
+ ===============================================================================
+              ##### Initialization and de-initialization functions #####
+ ===============================================================================
+    [..]
+      After reset, the backup domain (RTC registers, RTC backup data 
+      registers and backup SRAM) is protected against possible unwanted 
+      write accesses. 
+      To enable access to the RTC Domain and RTC registers, proceed as follows:
+        (+) Enable the Power Controller (PWR) APB1 interface clock using the
+            __HAL_RCC_PWR_CLK_ENABLE() macro.
+        (+) Enable access to RTC domain using the HAL_PWR_EnableBkUpAccess() function.
+ 
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief Deinitializes the HAL PWR peripheral registers to their default reset values.
+  * @retval None
+  */
+void HAL_PWR_DeInit(void)
+{
+  __HAL_RCC_PWR_FORCE_RESET();
+  __HAL_RCC_PWR_RELEASE_RESET();
+}
+
+/**
+  * @brief Enables access to the backup domain (RTC registers, RTC 
+  *         backup data registers and backup SRAM).
+  * @note If the HSE divided by 2, 3, ..31 is used as the RTC clock, the 
+  *         Backup Domain Access should be kept enabled.
+  * @note The following sequence is required to bypass the delay between
+  *         DBP bit programming and the effective enabling  of the backup domain.
+  *         Please check the Errata Sheet for more details under "Possible delay
+  *         in backup domain protection disabling/enabling after programming the
+  *         DBP bit" section.
+  * @retval None
+  */
+void HAL_PWR_EnableBkUpAccess(void)
+{
+  __IO uint32_t dummyread;
+  *(__IO uint32_t *) CR_DBP_BB = (uint32_t)ENABLE;
+  dummyread = PWR->CR;
+  UNUSED(dummyread);
+}
+
+/**
+  * @brief Disables access to the backup domain (RTC registers, RTC 
+  *         backup data registers and backup SRAM).
+  * @note If the HSE divided by 2, 3, ..31 is used as the RTC clock, the 
+  *         Backup Domain Access should be kept enabled.
+  * @note The following sequence is required to bypass the delay between
+  *         DBP bit programming and the effective disabling  of the backup domain.
+  *         Please check the Errata Sheet for more details under "Possible delay
+  *         in backup domain protection disabling/enabling after programming the
+  *         DBP bit" section.
+  * @retval None
+  */
+void HAL_PWR_DisableBkUpAccess(void)
+{
+  __IO uint32_t dummyread;
+  *(__IO uint32_t *) CR_DBP_BB = (uint32_t)DISABLE;
+  dummyread = PWR->CR;
+  UNUSED(dummyread);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup PWR_Exported_Functions_Group2 Peripheral Control functions 
+  *  @brief Low Power modes configuration functions 
+  *
+@verbatim
+
+ ===============================================================================
+                 ##### Peripheral Control functions #####
+ ===============================================================================
+     
+    *** PVD configuration ***
+    =========================
+    [..]
+      (+) The PVD is used to monitor the VDD power supply by comparing it to a 
+          threshold selected by the PVD Level (PLS[2:0] bits in the PWR_CR).
+      (+) A PVDO flag is available to indicate if VDD/VDDA is higher or lower 
+          than the PVD threshold. This event is internally connected to the EXTI 
+          line16 and can generate an interrupt if enabled. This is done through
+          __HAL_PWR_PVD_EXTI_ENABLE_IT() macro.
+      (+) The PVD is stopped in Standby mode.
+
+    *** Wake-up pin configuration ***
+    ================================
+    [..]
+      (+) Wake-up pin is used to wake up the system from Standby mode. This pin is 
+          forced in input pull-down configuration and is active on rising edges.
+      (+) There is one Wake-up pin: Wake-up Pin 1 on PA.00.
+	   (++) For STM32F446xx there are two Wake-Up pins: Pin1 on PA.00 and Pin2 on PC.13
+           (++) For STM32F410xx/STM32F412xx/STM32F413xx/STM32F423xx  there are three Wake-Up pins: Pin1 on PA.00, Pin2 on PC.00 and Pin3 on PC.01 
+
+    *** Low Power modes configuration ***
+    =====================================
+    [..]
+      The devices feature 3 low-power modes:
+      (+) Sleep mode: Cortex-M4 core stopped, peripherals kept running.
+      (+) Stop mode: all clocks are stopped, regulator running, regulator 
+          in low power mode
+      (+) Standby mode: 1.2V domain powered off.
+   
+   *** Sleep mode ***
+   ==================
+    [..]
+      (+) Entry:
+        The Sleep mode is entered by using the HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON, PWR_SLEEPENTRY_WFI)
+              functions with
+          (++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
+          (++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction
+      
+      -@@- The Regulator parameter is not used for the STM32F4 family 
+              and is kept as parameter just to maintain compatibility with the 
+              lower power families (STM32L).
+      (+) Exit:
+        Any peripheral interrupt acknowledged by the nested vectored interrupt 
+              controller (NVIC) can wake up the device from Sleep mode.
+
+   *** Stop mode ***
+   =================
+    [..]
+      In Stop mode, all clocks in the 1.2V domain are stopped, the PLL, the HSI,
+      and the HSE RC oscillators are disabled. Internal SRAM and register contents 
+      are preserved.
+      The voltage regulator can be configured either in normal or low-power mode.
+      To minimize the consumption In Stop mode, FLASH can be powered off before 
+      entering the Stop mode using the HAL_PWREx_EnableFlashPowerDown() function.
+      It can be switched on again by software after exiting the Stop mode using
+      the HAL_PWREx_DisableFlashPowerDown() function. 
+
+      (+) Entry:
+         The Stop mode is entered using the HAL_PWR_EnterSTOPMode(PWR_MAINREGULATOR_ON) 
+             function with:
+          (++) Main regulator ON.
+          (++) Low Power regulator ON.
+      (+) Exit:
+        Any EXTI Line (Internal or External) configured in Interrupt/Event mode.
+
+   *** Standby mode ***
+   ====================
+    [..]
+    (+)
+      The Standby mode allows to achieve the lowest power consumption. It is based 
+      on the Cortex-M4 deep sleep mode, with the voltage regulator disabled. 
+      The 1.2V domain is consequently powered off. The PLL, the HSI oscillator and 
+      the HSE oscillator are also switched off. SRAM and register contents are lost 
+      except for the RTC registers, RTC backup registers, backup SRAM and Standby 
+      circuitry.
+   
+      The voltage regulator is OFF.
+      
+      (++) Entry:
+        (+++) The Standby mode is entered using the HAL_PWR_EnterSTANDBYMode() function.
+      (++) Exit:
+        (+++) WKUP pin rising edge, RTC alarm (Alarm A and Alarm B), RTC wake-up,
+             tamper event, time-stamp event, external reset in NRST pin, IWDG reset.
+
+   *** Auto-wake-up (AWU) from low-power mode ***
+   =============================================
+    [..]
+    
+     (+) The MCU can be woken up from low-power mode by an RTC Alarm event, an RTC 
+      Wake-up event, a tamper event or a time-stamp event, without depending on 
+      an external interrupt (Auto-wake-up mode).
+
+      (+) RTC auto-wake-up (AWU) from the Stop and Standby modes
+       
+        (++) To wake up from the Stop mode with an RTC alarm event, it is necessary to 
+              configure the RTC to generate the RTC alarm using the HAL_RTC_SetAlarm_IT() function.
+
+        (++) To wake up from the Stop mode with an RTC Tamper or time stamp event, it 
+             is necessary to configure the RTC to detect the tamper or time stamp event using the
+                HAL_RTCEx_SetTimeStamp_IT() or HAL_RTCEx_SetTamper_IT() functions.
+                  
+        (++) To wake up from the Stop mode with an RTC Wake-up event, it is necessary to
+              configure the RTC to generate the RTC Wake-up event using the HAL_RTCEx_SetWakeUpTimer_IT() function.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD).
+  * @param sConfigPVD pointer to an PWR_PVDTypeDef structure that contains the configuration
+  *        information for the PVD.
+  * @note Refer to the electrical characteristics of your device datasheet for
+  *         more details about the voltage threshold corresponding to each 
+  *         detection level.
+  * @retval None
+  */
+void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD)
+{
+  /* Check the parameters */
+  assert_param(IS_PWR_PVD_LEVEL(sConfigPVD->PVDLevel));
+  assert_param(IS_PWR_PVD_MODE(sConfigPVD->Mode));
+  
+  /* Set PLS[7:5] bits according to PVDLevel value */
+  MODIFY_REG(PWR->CR, PWR_CR_PLS, sConfigPVD->PVDLevel);
+  
+  /* Clear any previous config. Keep it clear if no event or IT mode is selected */
+  __HAL_PWR_PVD_EXTI_DISABLE_EVENT();
+  __HAL_PWR_PVD_EXTI_DISABLE_IT();
+  __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();
+  __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); 
+
+  /* Configure interrupt mode */
+  if((sConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT)
+  {
+    __HAL_PWR_PVD_EXTI_ENABLE_IT();
+  }
+  
+  /* Configure event mode */
+  if((sConfigPVD->Mode & PVD_MODE_EVT) == PVD_MODE_EVT)
+  {
+    __HAL_PWR_PVD_EXTI_ENABLE_EVENT();
+  }
+  
+  /* Configure the edge */
+  if((sConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE)
+  {
+    __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();
+  }
+  
+  if((sConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE)
+  {
+    __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();
+  }
+}
+
+/**
+  * @brief Enables the Power Voltage Detector(PVD).
+  * @retval None
+  */
+void HAL_PWR_EnablePVD(void)
+{
+  *(__IO uint32_t *) CR_PVDE_BB = (uint32_t)ENABLE;
+}
+
+/**
+  * @brief Disables the Power Voltage Detector(PVD).
+  * @retval None
+  */
+void HAL_PWR_DisablePVD(void)
+{
+  *(__IO uint32_t *) CR_PVDE_BB = (uint32_t)DISABLE;
+}
+
+/**
+  * @brief Enables the Wake-up PINx functionality.
+  * @param WakeUpPinx Specifies the Power Wake-Up pin to enable.
+  *         This parameter can be one of the following values:
+  *           @arg PWR_WAKEUP_PIN1
+  *           @arg PWR_WAKEUP_PIN2 available only on STM32F410xx/STM32F446xx/STM32F412xx/STM32F413xx/STM32F423xx devices
+  *           @arg PWR_WAKEUP_PIN3 available only on STM32F410xx/STM32F412xx/STM32F413xx/STM32F423xx devices
+  * @retval None
+  */
+void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx)
+{
+  /* Check the parameter */
+  assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx));
+
+  /* Enable the wake up pin */
+  SET_BIT(PWR->CSR, WakeUpPinx);
+}
+
+/**
+  * @brief Disables the Wake-up PINx functionality.
+  * @param WakeUpPinx Specifies the Power Wake-Up pin to disable.
+  *         This parameter can be one of the following values:
+  *           @arg PWR_WAKEUP_PIN1
+  *           @arg PWR_WAKEUP_PIN2 available only on STM32F410xx/STM32F446xx/STM32F412xx/STM32F413xx/STM32F423xx devices
+  *           @arg PWR_WAKEUP_PIN3 available only on STM32F410xx/STM32F412xx/STM32F413xx/STM32F423xx devices
+  * @retval None
+  */
+void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx)
+{
+  /* Check the parameter */
+  assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx));  
+
+  /* Disable the wake up pin */
+  CLEAR_BIT(PWR->CSR, WakeUpPinx);
+}
+  
+/**
+  * @brief Enters Sleep mode.
+  *   
+  * @note In Sleep mode, all I/O pins keep the same state as in Run mode.
+  * 
+  * @note In Sleep mode, the systick is stopped to avoid exit from this mode with
+  *       systick interrupt when used as time base for Timeout 
+  *                
+  * @param Regulator Specifies the regulator state in SLEEP mode.
+  *            This parameter can be one of the following values:
+  *            @arg PWR_MAINREGULATOR_ON: SLEEP mode with regulator ON
+  *            @arg PWR_LOWPOWERREGULATOR_ON: SLEEP mode with low power regulator ON
+  * @note This parameter is not used for the STM32F4 family and is kept as parameter
+  *       just to maintain compatibility with the lower power families.
+  * @param SLEEPEntry Specifies if SLEEP mode in entered with WFI or WFE instruction.
+  *          This parameter can be one of the following values:
+  *            @arg PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
+  *            @arg PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction
+  * @retval None
+  */
+void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry)
+{
+  /* Check the parameters */
+  assert_param(IS_PWR_REGULATOR(Regulator));
+  assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry));
+
+  /* Clear SLEEPDEEP bit of Cortex System Control Register */
+  CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
+
+  /* Select SLEEP mode entry -------------------------------------------------*/
+  if(SLEEPEntry == PWR_SLEEPENTRY_WFI)
+  {   
+    /* Request Wait For Interrupt */
+    __WFI();
+  }
+  else
+  {
+    /* Request Wait For Event */
+    __SEV();
+    __WFE();
+    __WFE();
+  }
+}
+
+/**
+  * @brief Enters Stop mode. 
+  * @note In Stop mode, all I/O pins keep the same state as in Run mode.
+  * @note When exiting Stop mode by issuing an interrupt or a wake-up event, 
+  *         the HSI RC oscillator is selected as system clock.
+  * @note When the voltage regulator operates in low power mode, an additional 
+  *         startup delay is incurred when waking up from Stop mode. 
+  *         By keeping the internal regulator ON during Stop mode, the consumption 
+  *         is higher although the startup time is reduced.    
+  * @param Regulator Specifies the regulator state in Stop mode.
+  *          This parameter can be one of the following values:
+  *            @arg PWR_MAINREGULATOR_ON: Stop mode with regulator ON
+  *            @arg PWR_LOWPOWERREGULATOR_ON: Stop mode with low power regulator ON
+  * @param STOPEntry Specifies if Stop mode in entered with WFI or WFE instruction.
+  *          This parameter can be one of the following values:
+  *            @arg PWR_STOPENTRY_WFI: Enter Stop mode with WFI instruction
+  *            @arg PWR_STOPENTRY_WFE: Enter Stop mode with WFE instruction
+  * @retval None
+  */
+void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry)
+{
+  /* Check the parameters */
+  assert_param(IS_PWR_REGULATOR(Regulator));
+  assert_param(IS_PWR_STOP_ENTRY(STOPEntry));
+  
+  /* Select the regulator state in Stop mode: Set PDDS and LPDS bits according to PWR_Regulator value */
+  MODIFY_REG(PWR->CR, (PWR_CR_PDDS | PWR_CR_LPDS), Regulator);
+  
+  /* Set SLEEPDEEP bit of Cortex System Control Register */
+  SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
+  
+  /* Select Stop mode entry --------------------------------------------------*/
+  if(STOPEntry == PWR_STOPENTRY_WFI)
+  {   
+    /* Request Wait For Interrupt */
+    __WFI();
+  }
+  else
+  {
+    /* Request Wait For Event */
+    __SEV();
+    __WFE();
+    __WFE();
+  }
+  /* Reset SLEEPDEEP bit of Cortex System Control Register */
+  CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));  
+}
+
+/**
+  * @brief Enters Standby mode.
+  * @note In Standby mode, all I/O pins are high impedance except for:
+  *          - Reset pad (still available) 
+  *          - RTC_AF1 pin (PC13) if configured for tamper, time-stamp, RTC 
+  *            Alarm out, or RTC clock calibration out.
+  *          - RTC_AF2 pin (PI8) if configured for tamper or time-stamp.  
+  *          - WKUP pin 1 (PA0) if enabled.       
+  * @retval None
+  */
+void HAL_PWR_EnterSTANDBYMode(void)
+{
+  /* Select Standby mode */
+  SET_BIT(PWR->CR, PWR_CR_PDDS);
+
+  /* Set SLEEPDEEP bit of Cortex System Control Register */
+  SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
+  
+  /* This option is used to ensure that store operations are completed */
+#if defined ( __CC_ARM)
+  __force_stores();
+#endif
+  /* Request Wait For Interrupt */
+  __WFI();
+}
+
+/**
+  * @brief This function handles the PWR PVD interrupt request.
+  * @note This API should be called under the PVD_IRQHandler().
+  * @retval None
+  */
+void HAL_PWR_PVD_IRQHandler(void)
+{
+  /* Check PWR Exti flag */
+  if(__HAL_PWR_PVD_EXTI_GET_FLAG() != RESET)
+  {
+    /* PWR PVD interrupt user callback */
+    HAL_PWR_PVDCallback();
+    
+    /* Clear PWR Exti pending bit */
+    __HAL_PWR_PVD_EXTI_CLEAR_FLAG();
+  }
+}
+
+/**
+  * @brief  PWR PVD interrupt callback
+  * @retval None
+  */
+__weak void HAL_PWR_PVDCallback(void)
+{
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_PWR_PVDCallback could be implemented in the user file
+   */ 
+}
+
+/**
+  * @brief Indicates Sleep-On-Exit when returning from Handler mode to Thread mode. 
+  * @note Set SLEEPONEXIT bit of SCR register. When this bit is set, the processor 
+  *       re-enters SLEEP mode when an interruption handling is over.
+  *       Setting this bit is useful when the processor is expected to run only on
+  *       interruptions handling.         
+  * @retval None
+  */
+void HAL_PWR_EnableSleepOnExit(void)
+{
+  /* Set SLEEPONEXIT bit of Cortex System Control Register */
+  SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
+}
+
+/**
+  * @brief Disables Sleep-On-Exit feature when returning from Handler mode to Thread mode. 
+  * @note Clears SLEEPONEXIT bit of SCR register. When this bit is set, the processor 
+  *       re-enters SLEEP mode when an interruption handling is over.          
+  * @retval None
+  */
+void HAL_PWR_DisableSleepOnExit(void)
+{
+  /* Clear SLEEPONEXIT bit of Cortex System Control Register */
+  CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
+}
+
+/**
+  * @brief Enables CORTEX M4 SEVONPEND bit. 
+  * @note Sets SEVONPEND bit of SCR register. When this bit is set, this causes 
+  *       WFE to wake up when an interrupt moves from inactive to pended.
+  * @retval None
+  */
+void HAL_PWR_EnableSEVOnPend(void)
+{
+  /* Set SEVONPEND bit of Cortex System Control Register */
+  SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
+}
+
+/**
+  * @brief Disables CORTEX M4 SEVONPEND bit. 
+  * @note Clears SEVONPEND bit of SCR register. When this bit is set, this causes 
+  *       WFE to wake up when an interrupt moves from inactive to pended.         
+  * @retval None
+  */
+void HAL_PWR_DisableSEVOnPend(void)
+{
+  /* Clear SEVONPEND bit of Cortex System Control Register */
+  CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
+}
+
+/**
+  * @}
+  */
+  
+/**
+  * @}
+  */
+
+#endif /* HAL_PWR_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
diff --git a/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c
new file mode 100644
index 0000000..1acca55
--- /dev/null
+++ b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c
@@ -0,0 +1,600 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hal_pwr_ex.c
+  * @author  MCD Application Team
+  * @brief   Extended PWR HAL module driver.
+  *          This file provides firmware functions to manage the following 
+  *          functionalities of PWR extension peripheral:           
+  *           + Peripheral Extended features functions
+  *         
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file in
+  * the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  ******************************************************************************
+  */ 
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup PWREx PWREx
+  * @brief PWR HAL module driver
+  * @{
+  */
+
+#ifdef HAL_PWR_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @addtogroup PWREx_Private_Constants
+  * @{
+  */    
+#define PWR_OVERDRIVE_TIMEOUT_VALUE  1000U
+#define PWR_UDERDRIVE_TIMEOUT_VALUE  1000U
+#define PWR_BKPREG_TIMEOUT_VALUE     1000U
+#define PWR_VOSRDY_TIMEOUT_VALUE     1000U
+/**
+  * @}
+  */
+
+   
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup PWREx_Exported_Functions PWREx Exported Functions
+  *  @{
+  */
+
+/** @defgroup PWREx_Exported_Functions_Group1 Peripheral Extended features functions 
+  *  @brief Peripheral Extended features functions 
+  *
+@verbatim   
+
+ ===============================================================================
+                 ##### Peripheral extended features functions #####
+ ===============================================================================
+
+    *** Main and Backup Regulators configuration ***
+    ================================================
+    [..] 
+      (+) The backup domain includes 4 Kbytes of backup SRAM accessible only from 
+          the CPU, and address in 32-bit, 16-bit or 8-bit mode. Its content is 
+          retained even in Standby or VBAT mode when the low power backup regulator
+          is enabled. It can be considered as an internal EEPROM when VBAT is 
+          always present. You can use the HAL_PWREx_EnableBkUpReg() function to 
+          enable the low power backup regulator. 
+
+      (+) When the backup domain is supplied by VDD (analog switch connected to VDD) 
+          the backup SRAM is powered from VDD which replaces the VBAT power supply to 
+          save battery life.
+
+      (+) The backup SRAM is not mass erased by a tamper event. It is read 
+          protected to prevent confidential data, such as cryptographic private 
+          key, from being accessed. The backup SRAM can be erased only through 
+          the Flash interface when a protection level change from level 1 to 
+          level 0 is requested. 
+      -@- Refer to the description of Read protection (RDP) in the Flash 
+          programming manual.
+
+      (+) The main internal regulator can be configured to have a tradeoff between 
+          performance and power consumption when the device does not operate at 
+          the maximum frequency. This is done through __HAL_PWR_MAINREGULATORMODE_CONFIG() 
+          macro which configure VOS bit in PWR_CR register
+          
+        Refer to the product datasheets for more details.
+
+    *** FLASH Power Down configuration ****
+    =======================================
+    [..] 
+      (+) By setting the FPDS bit in the PWR_CR register by using the 
+          HAL_PWREx_EnableFlashPowerDown() function, the Flash memory also enters power 
+          down mode when the device enters Stop mode. When the Flash memory 
+          is in power down mode, an additional startup delay is incurred when 
+          waking up from Stop mode.
+          
+           (+) For STM32F42xxx/43xxx/446xx/469xx/479xx Devices, the scale can be modified only when the PLL 
+           is OFF and the HSI or HSE clock source is selected as system clock. 
+           The new value programmed is active only when the PLL is ON.
+           When the PLL is OFF, the voltage scale 3 is automatically selected. 
+        Refer to the datasheets for more details.
+
+    *** Over-Drive and Under-Drive configuration ****
+    =================================================
+    [..]         
+       (+) For STM32F42xxx/43xxx/446xx/469xx/479xx Devices, in Run mode: the main regulator has
+           2 operating modes available:
+        (++) Normal mode: The CPU and core logic operate at maximum frequency at a given 
+             voltage scaling (scale 1, scale 2 or scale 3)
+        (++) Over-drive mode: This mode allows the CPU and the core logic to operate at a 
+            higher frequency than the normal mode for a given voltage scaling (scale 1,  
+            scale 2 or scale 3). This mode is enabled through HAL_PWREx_EnableOverDrive() function and
+            disabled by HAL_PWREx_DisableOverDrive() function, to enter or exit from Over-drive mode please follow 
+            the sequence described in Reference manual.
+             
+       (+) For STM32F42xxx/43xxx/446xx/469xx/479xx Devices, in Stop mode: the main regulator or low power regulator 
+           supplies a low power voltage to the 1.2V domain, thus preserving the content of registers 
+           and internal SRAM. 2 operating modes are available:
+         (++) Normal mode: the 1.2V domain is preserved in nominal leakage mode. This mode is only 
+              available when the main regulator or the low power regulator is used in Scale 3 or 
+              low voltage mode.
+         (++) Under-drive mode: the 1.2V domain is preserved in reduced leakage mode. This mode is only
+              available when the main regulator or the low power regulator is in low voltage mode.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief Enables the Backup Regulator.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PWREx_EnableBkUpReg(void)
+{
+  uint32_t tickstart = 0U;
+
+  *(__IO uint32_t *) CSR_BRE_BB = (uint32_t)ENABLE;
+
+  /* Get tick */
+  tickstart = HAL_GetTick();
+
+  /* Wait till Backup regulator ready flag is set */  
+  while(__HAL_PWR_GET_FLAG(PWR_FLAG_BRR) == RESET)
+  {
+    if((HAL_GetTick() - tickstart ) > PWR_BKPREG_TIMEOUT_VALUE)
+    {
+      return HAL_TIMEOUT;
+    } 
+  }
+  return HAL_OK;
+}
+
+/**
+  * @brief Disables the Backup Regulator.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PWREx_DisableBkUpReg(void)
+{
+  uint32_t tickstart = 0U;
+
+  *(__IO uint32_t *) CSR_BRE_BB = (uint32_t)DISABLE;
+
+  /* Get tick */
+  tickstart = HAL_GetTick();
+
+  /* Wait till Backup regulator ready flag is set */  
+  while(__HAL_PWR_GET_FLAG(PWR_FLAG_BRR) != RESET)
+  {
+    if((HAL_GetTick() - tickstart ) > PWR_BKPREG_TIMEOUT_VALUE)
+    {
+      return HAL_TIMEOUT;
+    } 
+  }
+  return HAL_OK;
+}
+
+/**
+  * @brief Enables the Flash Power Down in Stop mode.
+  * @retval None
+  */
+void HAL_PWREx_EnableFlashPowerDown(void)
+{
+  *(__IO uint32_t *) CR_FPDS_BB = (uint32_t)ENABLE;
+}
+
+/**
+  * @brief Disables the Flash Power Down in Stop mode.
+  * @retval None
+  */
+void HAL_PWREx_DisableFlashPowerDown(void)
+{
+  *(__IO uint32_t *) CR_FPDS_BB = (uint32_t)DISABLE;
+}
+
+/**
+  * @brief Return Voltage Scaling Range.
+  * @retval The configured scale for the regulator voltage(VOS bit field).
+  *         The returned value can be one of the following:
+  *            - @arg PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output Scale 1 mode
+  *            - @arg PWR_REGULATOR_VOLTAGE_SCALE2: Regulator voltage output Scale 2 mode
+  *            - @arg PWR_REGULATOR_VOLTAGE_SCALE3: Regulator voltage output Scale 3 mode
+  */  
+uint32_t HAL_PWREx_GetVoltageRange(void)
+{
+  return (PWR->CR & PWR_CR_VOS);
+}
+
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
+/**
+  * @brief Configures the main internal regulator output voltage.
+  * @param  VoltageScaling specifies the regulator output voltage to achieve
+  *         a tradeoff between performance and power consumption.
+  *          This parameter can be one of the following values:
+  *            @arg PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output range 1 mode,
+  *                                               the maximum value of fHCLK = 168 MHz.
+  *            @arg PWR_REGULATOR_VOLTAGE_SCALE2: Regulator voltage output range 2 mode,
+  *                                               the maximum value of fHCLK = 144 MHz.
+  * @note  When moving from Range 1 to Range 2, the system frequency must be decreased to
+  *        a value below 144 MHz before calling HAL_PWREx_ConfigVoltageScaling() API.
+  *        When moving from Range 2 to Range 1, the system frequency can be increased to
+  *        a value up to 168 MHz after calling HAL_PWREx_ConfigVoltageScaling() API.
+  * @retval HAL Status
+  */
+HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling)
+{
+  uint32_t tickstart = 0U;
+  
+  assert_param(IS_PWR_VOLTAGE_SCALING_RANGE(VoltageScaling));
+  
+  /* Enable PWR RCC Clock Peripheral */
+  __HAL_RCC_PWR_CLK_ENABLE();
+  
+  /* Set Range */
+  __HAL_PWR_VOLTAGESCALING_CONFIG(VoltageScaling);
+  
+  /* Get Start Tick*/
+  tickstart = HAL_GetTick();
+  while((__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY) == RESET))
+  {
+    if((HAL_GetTick() - tickstart ) > PWR_VOSRDY_TIMEOUT_VALUE)
+    {
+      return HAL_TIMEOUT;
+    } 
+  }
+
+  return HAL_OK;
+}
+
+#elif defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
+      defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) || \
+      defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F469xx) || \
+      defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || \
+      defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
+/**
+  * @brief Configures the main internal regulator output voltage.
+  * @param  VoltageScaling specifies the regulator output voltage to achieve
+  *         a tradeoff between performance and power consumption.
+  *          This parameter can be one of the following values:
+  *            @arg PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output range 1 mode,
+  *                                               the maximum value of fHCLK is 168 MHz. It can be extended to
+  *                                               180 MHz by activating the over-drive mode.
+  *            @arg PWR_REGULATOR_VOLTAGE_SCALE2: Regulator voltage output range 2 mode,
+  *                                               the maximum value of fHCLK is 144 MHz. It can be extended to,                
+  *                                               168 MHz by activating the over-drive mode.
+  *            @arg PWR_REGULATOR_VOLTAGE_SCALE3: Regulator voltage output range 3 mode,
+  *                                               the maximum value of fHCLK is 120 MHz.
+  * @note To update the system clock frequency(SYSCLK):
+  *        - Set the HSI or HSE as system clock frequency using the HAL_RCC_ClockConfig().
+  *        - Call the HAL_RCC_OscConfig() to configure the PLL.
+  *        - Call HAL_PWREx_ConfigVoltageScaling() API to adjust the voltage scale.
+  *        - Set the new system clock frequency using the HAL_RCC_ClockConfig().
+  * @note The scale can be modified only when the HSI or HSE clock source is selected 
+  *        as system clock source, otherwise the API returns HAL_ERROR.  
+  * @note When the PLL is OFF, the voltage scale 3 is automatically selected and the VOS bits
+  *       value in the PWR_CR1 register are not taken in account.
+  * @note This API forces the PLL state ON to allow the possibility to configure the voltage scale 1 or 2.
+  * @note The new voltage scale is active only when the PLL is ON.  
+  * @retval HAL Status
+  */
+HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling)
+{
+  uint32_t tickstart = 0U;
+  
+  assert_param(IS_PWR_VOLTAGE_SCALING_RANGE(VoltageScaling));
+  
+  /* Enable PWR RCC Clock Peripheral */
+  __HAL_RCC_PWR_CLK_ENABLE();
+  
+  /* Check if the PLL is used as system clock or not */
+  if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL)
+  {
+    /* Disable the main PLL */
+    __HAL_RCC_PLL_DISABLE();
+    
+    /* Get Start Tick */
+    tickstart = HAL_GetTick();    
+    /* Wait till PLL is disabled */  
+    while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
+    {
+      if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
+      {
+        return HAL_TIMEOUT;
+      }
+    }
+    
+    /* Set Range */
+    __HAL_PWR_VOLTAGESCALING_CONFIG(VoltageScaling);
+    
+    /* Enable the main PLL */
+    __HAL_RCC_PLL_ENABLE();
+    
+    /* Get Start Tick */
+    tickstart = HAL_GetTick();
+    /* Wait till PLL is ready */  
+    while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
+    {
+      if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
+      {
+        return HAL_TIMEOUT;
+      } 
+    }
+    
+    /* Get Start Tick */
+    tickstart = HAL_GetTick();
+    while((__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY) == RESET))
+    {
+      if((HAL_GetTick() - tickstart ) > PWR_VOSRDY_TIMEOUT_VALUE)
+      {
+        return HAL_TIMEOUT;
+      } 
+    }
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
+
+#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) ||\
+    defined(STM32F411xE) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) ||\
+    defined(STM32F413xx) || defined(STM32F423xx)
+/**
+  * @brief Enables Main Regulator low voltage mode.
+  * @note  This mode is only available for STM32F401xx/STM32F410xx/STM32F411xx/STM32F412Zx/STM32F412Rx/STM32F412Vx/STM32F412Cx/
+  *        STM32F413xx/STM32F423xx devices.   
+  * @retval None
+  */
+void HAL_PWREx_EnableMainRegulatorLowVoltage(void)
+{
+  *(__IO uint32_t *) CR_MRLVDS_BB = (uint32_t)ENABLE;
+}
+
+/**
+  * @brief Disables Main Regulator low voltage mode.
+  * @note  This mode is only available for STM32F401xx/STM32F410xx/STM32F411xx/STM32F412Zx/STM32F412Rx/STM32F412Vx/STM32F412Cx/
+  *        STM32F413xx/STM32F423xxdevices. 
+  * @retval None
+  */
+void HAL_PWREx_DisableMainRegulatorLowVoltage(void)
+{
+  *(__IO uint32_t *) CR_MRLVDS_BB = (uint32_t)DISABLE;
+}
+
+/**
+  * @brief Enables Low Power Regulator low voltage mode.
+  * @note  This mode is only available for STM32F401xx/STM32F410xx/STM32F411xx/STM32F412Zx/STM32F412Rx/STM32F412Vx/STM32F412Cx/
+  *        STM32F413xx/STM32F423xx devices.   
+  * @retval None
+  */
+void HAL_PWREx_EnableLowRegulatorLowVoltage(void)
+{
+  *(__IO uint32_t *) CR_LPLVDS_BB = (uint32_t)ENABLE;
+}
+
+/**
+  * @brief Disables Low Power Regulator low voltage mode.
+  * @note  This mode is only available for STM32F401xx/STM32F410xx/STM32F411xx/STM32F412Zx/STM32F412Rx/STM32F412Vx/STM32F412Cx/
+  *        STM32F413xx/STM32F423xx  devices.   
+  * @retval None
+  */
+void HAL_PWREx_DisableLowRegulatorLowVoltage(void)
+{
+  *(__IO uint32_t *) CR_LPLVDS_BB = (uint32_t)DISABLE;
+}
+
+#endif /* STM32F401xC || STM32F401xE || STM32F410xx || STM32F411xE || STM32F412Zx || STM32F412Rx || STM32F412Vx || STM32F412Cx ||
+          STM32F413xx || STM32F423xx */
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
+    defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
+/**
+  * @brief  Activates the Over-Drive mode.
+  * @note   This function can be used only for STM32F42xx/STM32F43xx/STM32F446xx/STM32F469xx/STM32F479xx devices.
+  *         This mode allows the CPU and the core logic to operate at a higher frequency
+  *         than the normal mode for a given voltage scaling (scale 1, scale 2 or scale 3).   
+  * @note   It is recommended to enter or exit Over-drive mode when the application is not running 
+  *         critical tasks and when the system clock source is either HSI or HSE. 
+  *         During the Over-drive switch activation, no peripheral clocks should be enabled.   
+  *         The peripheral clocks must be enabled once the Over-drive mode is activated.   
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PWREx_EnableOverDrive(void)
+{
+  uint32_t tickstart = 0U;
+
+  __HAL_RCC_PWR_CLK_ENABLE();
+  
+  /* Enable the Over-drive to extend the clock frequency to 180 Mhz */
+  __HAL_PWR_OVERDRIVE_ENABLE();
+
+  /* Get tick */
+  tickstart = HAL_GetTick();
+
+  while(!__HAL_PWR_GET_FLAG(PWR_FLAG_ODRDY))
+  {
+    if((HAL_GetTick() - tickstart) > PWR_OVERDRIVE_TIMEOUT_VALUE)
+    {
+      return HAL_TIMEOUT;
+    }
+  }
+  
+  /* Enable the Over-drive switch */
+  __HAL_PWR_OVERDRIVESWITCHING_ENABLE();
+
+  /* Get tick */
+  tickstart = HAL_GetTick();
+
+  while(!__HAL_PWR_GET_FLAG(PWR_FLAG_ODSWRDY))
+  {
+    if((HAL_GetTick() - tickstart ) > PWR_OVERDRIVE_TIMEOUT_VALUE)
+    {
+      return HAL_TIMEOUT;
+    }
+  } 
+  return HAL_OK;
+}
+
+/**
+  * @brief  Deactivates the Over-Drive mode.
+  * @note   This function can be used only for STM32F42xx/STM32F43xx/STM32F446xx/STM32F469xx/STM32F479xx devices.
+  *         This mode allows the CPU and the core logic to operate at a higher frequency
+  *         than the normal mode for a given voltage scaling (scale 1, scale 2 or scale 3).    
+  * @note   It is recommended to enter or exit Over-drive mode when the application is not running 
+  *         critical tasks and when the system clock source is either HSI or HSE. 
+  *         During the Over-drive switch activation, no peripheral clocks should be enabled.   
+  *         The peripheral clocks must be enabled once the Over-drive mode is activated.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PWREx_DisableOverDrive(void)
+{
+  uint32_t tickstart = 0U;
+  
+  __HAL_RCC_PWR_CLK_ENABLE();
+    
+  /* Disable the Over-drive switch */
+  __HAL_PWR_OVERDRIVESWITCHING_DISABLE();
+  
+  /* Get tick */
+  tickstart = HAL_GetTick();
+ 
+  while(__HAL_PWR_GET_FLAG(PWR_FLAG_ODSWRDY))
+  {
+    if((HAL_GetTick() - tickstart) > PWR_OVERDRIVE_TIMEOUT_VALUE)
+    {
+      return HAL_TIMEOUT;
+    }
+  } 
+  
+  /* Disable the Over-drive */
+  __HAL_PWR_OVERDRIVE_DISABLE();
+
+  /* Get tick */
+  tickstart = HAL_GetTick();
+
+  while(__HAL_PWR_GET_FLAG(PWR_FLAG_ODRDY))
+  {
+    if((HAL_GetTick() - tickstart) > PWR_OVERDRIVE_TIMEOUT_VALUE)
+    {
+      return HAL_TIMEOUT;
+    }
+  }
+  
+  return HAL_OK;
+}
+
+/**
+  * @brief  Enters in Under-Drive STOP mode.
+  *  
+  * @note   This mode is only available for STM32F42xxx/STM32F43xxx/STM32F446xx/STM32F469xx/STM32F479xx devices.
+  * 
+  * @note    This mode can be selected only when the Under-Drive is already active 
+  *   
+  * @note    This mode is enabled only with STOP low power mode.
+  *          In this mode, the 1.2V domain is preserved in reduced leakage mode. This 
+  *          mode is only available when the main regulator or the low power regulator 
+  *          is in low voltage mode
+  *        
+  * @note   If the Under-drive mode was enabled, it is automatically disabled after 
+  *         exiting Stop mode. 
+  *         When the voltage regulator operates in Under-drive mode, an additional  
+  *         startup delay is induced when waking up from Stop mode.
+  *                    
+  * @note   In Stop mode, all I/O pins keep the same state as in Run mode.
+  *   
+  * @note   When exiting Stop mode by issuing an interrupt or a wake-up event, 
+  *         the HSI RC oscillator is selected as system clock.
+  *           
+  * @note   When the voltage regulator operates in low power mode, an additional 
+  *         startup delay is incurred when waking up from Stop mode. 
+  *         By keeping the internal regulator ON during Stop mode, the consumption 
+  *         is higher although the startup time is reduced.
+  *     
+  * @param  Regulator specifies the regulator state in STOP mode.
+  *          This parameter can be one of the following values:
+  *            @arg PWR_MAINREGULATOR_UNDERDRIVE_ON:  Main Regulator in under-drive mode 
+  *                 and Flash memory in power-down when the device is in Stop under-drive mode
+  *            @arg PWR_LOWPOWERREGULATOR_UNDERDRIVE_ON:  Low Power Regulator in under-drive mode 
+  *                and Flash memory in power-down when the device is in Stop under-drive mode
+  * @param  STOPEntry specifies if STOP mode in entered with WFI or WFE instruction.
+  *          This parameter can be one of the following values:
+  *            @arg PWR_SLEEPENTRY_WFI: enter STOP mode with WFI instruction
+  *            @arg PWR_SLEEPENTRY_WFE: enter STOP mode with WFE instruction
+  * @retval None
+  */
+HAL_StatusTypeDef HAL_PWREx_EnterUnderDriveSTOPMode(uint32_t Regulator, uint8_t STOPEntry)
+{
+  uint32_t tmpreg1 = 0U;
+
+  /* Check the parameters */
+  assert_param(IS_PWR_REGULATOR_UNDERDRIVE(Regulator));
+  assert_param(IS_PWR_STOP_ENTRY(STOPEntry));
+  
+  /* Enable Power ctrl clock */
+  __HAL_RCC_PWR_CLK_ENABLE();
+  /* Enable the Under-drive Mode ---------------------------------------------*/
+  /* Clear Under-drive flag */
+  __HAL_PWR_CLEAR_ODRUDR_FLAG();
+  
+  /* Enable the Under-drive */ 
+  __HAL_PWR_UNDERDRIVE_ENABLE();
+
+  /* Select the regulator state in STOP mode ---------------------------------*/
+  tmpreg1 = PWR->CR;
+  /* Clear PDDS, LPDS, MRLUDS and LPLUDS bits */
+  tmpreg1 &= (uint32_t)~(PWR_CR_PDDS | PWR_CR_LPDS | PWR_CR_LPUDS | PWR_CR_MRUDS);
+  
+  /* Set LPDS, MRLUDS and LPLUDS bits according to PWR_Regulator value */
+  tmpreg1 |= Regulator;
+  
+  /* Store the new value */
+  PWR->CR = tmpreg1;
+  
+  /* Set SLEEPDEEP bit of Cortex System Control Register */
+  SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
+  
+  /* Select STOP mode entry --------------------------------------------------*/
+  if(STOPEntry == PWR_SLEEPENTRY_WFI)
+  {   
+    /* Request Wait For Interrupt */
+    __WFI();
+  }
+  else
+  {
+    /* Request Wait For Event */
+    __WFE();
+  }
+  /* Reset SLEEPDEEP bit of Cortex System Control Register */
+  SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
+
+  return HAL_OK;  
+}
+
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* HAL_PWR_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
diff --git a/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_qspi.c b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_qspi.c
new file mode 100644
index 0000000..637e5e0
--- /dev/null
+++ b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_qspi.c
@@ -0,0 +1,2915 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hal_qspi.c
+  * @author  MCD Application Team
+  * @brief   QSPI HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the QuadSPI interface (QSPI).
+  *           + Initialization and de-initialization functions
+  *           + Indirect functional mode management
+  *           + Memory-mapped functional mode management
+  *           + Auto-polling functional mode management
+  *           + Interrupts and flags management
+  *           + DMA channel configuration for indirect functional mode
+  *           + Errors management and abort functionality
+  *
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2016 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  @verbatim
+ ===============================================================================
+                        ##### How to use this driver #####
+ ===============================================================================
+  [..]
+    *** Initialization ***
+    ======================
+    [..]
+      (#) As prerequisite, fill in the HAL_QSPI_MspInit() :
+        (++) Enable QuadSPI clock interface with __HAL_RCC_QSPI_CLK_ENABLE().
+        (++) Reset QuadSPI Peripheral with __HAL_RCC_QSPI_FORCE_RESET() and __HAL_RCC_QSPI_RELEASE_RESET().
+        (++) Enable the clocks for the QuadSPI GPIOS with __HAL_RCC_GPIOx_CLK_ENABLE().
+        (++) Configure these QuadSPI pins in alternate mode using HAL_GPIO_Init().
+        (++) If interrupt mode is used, enable and configure QuadSPI global
+            interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ().
+        (++) If DMA mode is used, enable the clocks for the QuadSPI DMA channel
+            with __HAL_RCC_DMAx_CLK_ENABLE(), configure DMA with HAL_DMA_Init(),
+            link it with QuadSPI handle using __HAL_LINKDMA(), enable and configure
+            DMA channel global interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ().
+      (#) Configure the flash size, the clock prescaler, the fifo threshold, the
+          clock mode, the sample shifting and the CS high time using the HAL_QSPI_Init() function.
+
+    *** Indirect functional mode ***
+    ================================
+    [..]
+      (#) Configure the command sequence using the HAL_QSPI_Command() or HAL_QSPI_Command_IT()
+          functions :
+         (++) Instruction phase : the mode used and if present the instruction opcode.
+         (++) Address phase : the mode used and if present the size and the address value.
+         (++) Alternate-bytes phase : the mode used and if present the size and the alternate
+             bytes values.
+         (++) Dummy-cycles phase : the number of dummy cycles (mode used is same as data phase).
+         (++) Data phase : the mode used and if present the number of bytes.
+         (++) Double Data Rate (DDR) mode : the activation (or not) of this mode and the delay
+             if activated.
+         (++) Sending Instruction Only Once (SIOO) mode : the activation (or not) of this mode.
+      (#) If no data is required for the command, it is sent directly to the memory :
+         (++) In polling mode, the output of the function is done when the transfer is complete.
+         (++) In interrupt mode, HAL_QSPI_CmdCpltCallback() will be called when the transfer is complete.
+      (#) For the indirect write mode, use HAL_QSPI_Transmit(), HAL_QSPI_Transmit_DMA() or
+          HAL_QSPI_Transmit_IT() after the command configuration :
+         (++) In polling mode, the output of the function is done when the transfer is complete.
+         (++) In interrupt mode, HAL_QSPI_FifoThresholdCallback() will be called when the fifo threshold
+             is reached and HAL_QSPI_TxCpltCallback() will be called when the transfer is complete.
+         (++) In DMA mode, HAL_QSPI_TxHalfCpltCallback() will be called at the half transfer and
+             HAL_QSPI_TxCpltCallback() will be called when the transfer is complete.
+      (#) For the indirect read mode, use HAL_QSPI_Receive(), HAL_QSPI_Receive_DMA() or
+          HAL_QSPI_Receive_IT() after the command configuration :
+         (++) In polling mode, the output of the function is done when the transfer is complete.
+         (++) In interrupt mode, HAL_QSPI_FifoThresholdCallback() will be called when the fifo threshold
+             is reached and HAL_QSPI_RxCpltCallback() will be called when the transfer is complete.
+         (++) In DMA mode, HAL_QSPI_RxHalfCpltCallback() will be called at the half transfer and
+             HAL_QSPI_RxCpltCallback() will be called when the transfer is complete.
+
+    *** Auto-polling functional mode ***
+    ====================================
+    [..]
+      (#) Configure the command sequence and the auto-polling functional mode using the
+          HAL_QSPI_AutoPolling() or HAL_QSPI_AutoPolling_IT() functions :
+         (++) Instruction phase : the mode used and if present the instruction opcode.
+         (++) Address phase : the mode used and if present the size and the address value.
+         (++) Alternate-bytes phase : the mode used and if present the size and the alternate
+             bytes values.
+         (++) Dummy-cycles phase : the number of dummy cycles (mode used is same as data phase).
+         (++) Data phase : the mode used.
+         (++) Double Data Rate (DDR) mode : the activation (or not) of this mode and the delay
+             if activated.
+         (++) Sending Instruction Only Once (SIOO) mode : the activation (or not) of this mode.
+         (++) The size of the status bytes, the match value, the mask used, the match mode (OR/AND),
+             the polling interval and the automatic stop activation.
+      (#) After the configuration :
+         (++) In polling mode, the output of the function is done when the status match is reached. The
+             automatic stop is activated to avoid an infinite loop.
+         (++) In interrupt mode, HAL_QSPI_StatusMatchCallback() will be called each time the status match is reached.
+
+    *** Memory-mapped functional mode ***
+    =====================================
+    [..]
+      (#) Configure the command sequence and the memory-mapped functional mode using the
+          HAL_QSPI_MemoryMapped() functions :
+         (++) Instruction phase : the mode used and if present the instruction opcode.
+         (++) Address phase : the mode used and the size.
+         (++) Alternate-bytes phase : the mode used and if present the size and the alternate
+             bytes values.
+         (++) Dummy-cycles phase : the number of dummy cycles (mode used is same as data phase).
+         (++) Data phase : the mode used.
+         (++) Double Data Rate (DDR) mode : the activation (or not) of this mode and the delay
+             if activated.
+         (++) Sending Instruction Only Once (SIOO) mode : the activation (or not) of this mode.
+         (++) The timeout activation and the timeout period.
+      (#) After the configuration, the QuadSPI will be used as soon as an access on the AHB is done on
+          the address range. HAL_QSPI_TimeOutCallback() will be called when the timeout expires.
+
+    *** Errors management and abort functionality ***
+    =================================================
+    [..]
+      (#) HAL_QSPI_GetError() function gives the error raised during the last operation.
+      (#) HAL_QSPI_Abort() and HAL_QSPI_Abort_IT() functions aborts any on-going operation and
+          flushes the fifo :
+         (++) In polling mode, the output of the function is done when the transfer
+              complete bit is set and the busy bit cleared.
+         (++) In interrupt mode, HAL_QSPI_AbortCpltCallback() will be called when
+              the transfer complete bit is set.
+
+    *** Control functions ***
+    =========================
+    [..]
+      (#) HAL_QSPI_GetState() function gives the current state of the HAL QuadSPI driver.
+      (#) HAL_QSPI_SetTimeout() function configures the timeout value used in the driver.
+      (#) HAL_QSPI_SetFifoThreshold() function configures the threshold on the Fifo of the QSPI IP.
+      (#) HAL_QSPI_GetFifoThreshold() function gives the current of the Fifo's threshold
+      (#) HAL_QSPI_SetFlashID() function configures the index of the flash memory to be accessed.
+
+    *** Callback registration ***
+    =============================================
+    [..]
+      The compilation define  USE_HAL_QSPI_REGISTER_CALLBACKS when set to 1
+      allows the user to configure dynamically the driver callbacks.
+
+      Use Functions HAL_QSPI_RegisterCallback() to register a user callback,
+      it allows to register following callbacks:
+        (+) ErrorCallback : callback when error occurs.
+        (+) AbortCpltCallback : callback when abort is completed.
+        (+) FifoThresholdCallback : callback when the fifo threshold is reached.
+        (+) CmdCpltCallback : callback when a command without data is completed.
+        (+) RxCpltCallback : callback when a reception transfer is completed.
+        (+) TxCpltCallback : callback when a transmission transfer is completed.
+        (+) RxHalfCpltCallback : callback when half of the reception transfer is completed.
+        (+) TxHalfCpltCallback : callback when half of the transmission transfer is completed.
+        (+) StatusMatchCallback : callback when a status match occurs.
+        (+) TimeOutCallback : callback when the timeout perioed expires.
+        (+) MspInitCallback    : QSPI MspInit.
+        (+) MspDeInitCallback  : QSPI MspDeInit.
+      This function takes as parameters the HAL peripheral handle, the Callback ID
+      and a pointer to the user callback function.
+
+      Use function HAL_QSPI_UnRegisterCallback() to reset a callback to the default
+      weak (surcharged) function. It allows to reset following callbacks:
+        (+) ErrorCallback : callback when error occurs.
+        (+) AbortCpltCallback : callback when abort is completed.
+        (+) FifoThresholdCallback : callback when the fifo threshold is reached.
+        (+) CmdCpltCallback : callback when a command without data is completed.
+        (+) RxCpltCallback : callback when a reception transfer is completed.
+        (+) TxCpltCallback : callback when a transmission transfer is completed.
+        (+) RxHalfCpltCallback : callback when half of the reception transfer is completed.
+        (+) TxHalfCpltCallback : callback when half of the transmission transfer is completed.
+        (+) StatusMatchCallback : callback when a status match occurs.
+        (+) TimeOutCallback : callback when the timeout perioed expires.
+        (+) MspInitCallback    : QSPI MspInit.
+        (+) MspDeInitCallback  : QSPI MspDeInit.
+      This function) takes as parameters the HAL peripheral handle and the Callback ID.
+
+      By default, after the HAL_QSPI_Init and if the state is HAL_QSPI_STATE_RESET
+      all callbacks are reset to the corresponding legacy weak (surcharged) functions.
+      Exception done for MspInit and MspDeInit callbacks that are respectively
+      reset to the legacy weak (surcharged) functions in the HAL_QSPI_Init
+      and  HAL_QSPI_DeInit only when these callbacks are null (not registered beforehand).
+      If not, MspInit or MspDeInit are not null, the HAL_QSPI_Init and HAL_QSPI_DeInit
+      keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
+
+      Callbacks can be registered/unregistered in READY state only.
+      Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
+      in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
+      during the Init/DeInit.
+      In that case first register the MspInit/MspDeInit user callbacks
+      using HAL_QSPI_RegisterCallback before calling HAL_QSPI_DeInit
+      or HAL_QSPI_Init function.
+
+      When The compilation define USE_HAL_QSPI_REGISTER_CALLBACKS is set to 0 or
+      not defined, the callback registering feature is not available
+      and weak (surcharged) callbacks are used.
+
+    *** Workarounds linked to Silicon Limitation ***
+    ====================================================
+    [..]
+      (#) Workarounds Implemented inside HAL Driver
+         (++) Extra data written in the FIFO at the end of a read transfer
+
+  @endverbatim
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal.h"
+
+#if defined(QUADSPI)
+
+/** @addtogroup STM32F4xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup QSPI QSPI
+  * @brief QSPI HAL module driver
+  * @{
+  */
+#ifdef HAL_QSPI_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+
+/* Private define ------------------------------------------------------------*/
+/** @defgroup QSPI_Private_Constants QSPI Private Constants
+  * @{
+  */
+#define QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE 0x00000000U                     /*!<Indirect write mode*/
+#define QSPI_FUNCTIONAL_MODE_INDIRECT_READ  ((uint32_t)QUADSPI_CCR_FMODE_0) /*!<Indirect read mode*/
+#define QSPI_FUNCTIONAL_MODE_AUTO_POLLING   ((uint32_t)QUADSPI_CCR_FMODE_1) /*!<Automatic polling mode*/
+#define QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED  ((uint32_t)QUADSPI_CCR_FMODE)   /*!<Memory-mapped mode*/
+/**
+  * @}
+  */
+
+/* Private macro -------------------------------------------------------------*/
+/** @defgroup QSPI_Private_Macros QSPI Private Macros
+  * @{
+  */
+#define IS_QSPI_FUNCTIONAL_MODE(MODE) (((MODE) == QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE) || \
+                                       ((MODE) == QSPI_FUNCTIONAL_MODE_INDIRECT_READ)  || \
+                                       ((MODE) == QSPI_FUNCTIONAL_MODE_AUTO_POLLING)   || \
+                                       ((MODE) == QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED))
+/**
+  * @}
+  */
+
+/* Private variables ---------------------------------------------------------*/
+
+/* Private function prototypes -----------------------------------------------*/
+static void QSPI_DMARxCplt(DMA_HandleTypeDef *hdma);
+static void QSPI_DMATxCplt(DMA_HandleTypeDef *hdma);
+static void QSPI_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
+static void QSPI_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
+static void QSPI_DMAError(DMA_HandleTypeDef *hdma);
+static void QSPI_DMAAbortCplt(DMA_HandleTypeDef *hdma);
+static HAL_StatusTypeDef QSPI_WaitFlagStateUntilTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Flag, FlagStatus State, uint32_t Tickstart, uint32_t Timeout);
+static HAL_StatusTypeDef QSPI_WaitFlagStateUntilTimeout_CPUCycle(QSPI_HandleTypeDef *hqspi, uint32_t Flag, FlagStatus State, uint32_t Timeout);
+static void QSPI_Config(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t FunctionalMode);
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup QSPI_Exported_Functions QSPI Exported Functions
+  * @{
+  */
+
+/** @defgroup QSPI_Exported_Functions_Group1 Initialization/de-initialization functions
+  *  @brief    Initialization and Configuration functions
+  *
+@verbatim
+===============================================================================
+            ##### Initialization and Configuration functions #####
+ ===============================================================================
+    [..]
+    This subsection provides a set of functions allowing to :
+      (+) Initialize the QuadSPI.
+      (+) De-initialize the QuadSPI.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief Initialize the QSPI mode according to the specified parameters
+  *        in the QSPI_InitTypeDef and initialize the associated handle.
+  * @param hqspi QSPI handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_QSPI_Init(QSPI_HandleTypeDef *hqspi)
+{
+  HAL_StatusTypeDef status;
+  uint32_t tickstart = HAL_GetTick();
+
+  /* Check the QSPI handle allocation */
+  if(hqspi == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_QSPI_ALL_INSTANCE(hqspi->Instance));
+  assert_param(IS_QSPI_CLOCK_PRESCALER(hqspi->Init.ClockPrescaler));
+  assert_param(IS_QSPI_FIFO_THRESHOLD(hqspi->Init.FifoThreshold));
+  assert_param(IS_QSPI_SSHIFT(hqspi->Init.SampleShifting));
+  assert_param(IS_QSPI_FLASH_SIZE(hqspi->Init.FlashSize));
+  assert_param(IS_QSPI_CS_HIGH_TIME(hqspi->Init.ChipSelectHighTime));
+  assert_param(IS_QSPI_CLOCK_MODE(hqspi->Init.ClockMode));
+  assert_param(IS_QSPI_DUAL_FLASH_MODE(hqspi->Init.DualFlash));
+
+  if (hqspi->Init.DualFlash != QSPI_DUALFLASH_ENABLE )
+  {
+    assert_param(IS_QSPI_FLASH_ID(hqspi->Init.FlashID));
+  }
+
+  if(hqspi->State == HAL_QSPI_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    hqspi->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
+    /* Reset Callback pointers in HAL_QSPI_STATE_RESET only */
+    hqspi->ErrorCallback         = HAL_QSPI_ErrorCallback;
+    hqspi->AbortCpltCallback     = HAL_QSPI_AbortCpltCallback;
+    hqspi->FifoThresholdCallback = HAL_QSPI_FifoThresholdCallback;
+    hqspi->CmdCpltCallback       = HAL_QSPI_CmdCpltCallback;
+    hqspi->RxCpltCallback        = HAL_QSPI_RxCpltCallback;
+    hqspi->TxCpltCallback        = HAL_QSPI_TxCpltCallback;
+    hqspi->RxHalfCpltCallback    = HAL_QSPI_RxHalfCpltCallback;
+    hqspi->TxHalfCpltCallback    = HAL_QSPI_TxHalfCpltCallback;
+    hqspi->StatusMatchCallback   = HAL_QSPI_StatusMatchCallback;
+    hqspi->TimeOutCallback       = HAL_QSPI_TimeOutCallback;
+
+    if(hqspi->MspInitCallback == NULL)
+    {
+      hqspi->MspInitCallback = HAL_QSPI_MspInit;
+    }
+
+    /* Init the low level hardware */
+    hqspi->MspInitCallback(hqspi);
+#else
+    /* Init the low level hardware : GPIO, CLOCK */
+    HAL_QSPI_MspInit(hqspi);
+#endif
+
+    /* Configure the default timeout for the QSPI memory access */
+    HAL_QSPI_SetTimeout(hqspi, HAL_QSPI_TIMEOUT_DEFAULT_VALUE);
+  }
+
+  /* Configure QSPI FIFO Threshold */
+  MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_FTHRES,
+             ((hqspi->Init.FifoThreshold - 1U) << QUADSPI_CR_FTHRES_Pos));
+
+  /* Wait till BUSY flag reset */
+  status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout);
+
+  if(status == HAL_OK)
+  {
+    /* Configure QSPI Clock Prescaler and Sample Shift */
+    MODIFY_REG(hqspi->Instance->CR, (QUADSPI_CR_PRESCALER | QUADSPI_CR_SSHIFT | QUADSPI_CR_FSEL | QUADSPI_CR_DFM),
+               ((hqspi->Init.ClockPrescaler << QUADSPI_CR_PRESCALER_Pos) |
+                hqspi->Init.SampleShifting  | hqspi->Init.FlashID | hqspi->Init.DualFlash));
+
+    /* Configure QSPI Flash Size, CS High Time and Clock Mode */
+    MODIFY_REG(hqspi->Instance->DCR, (QUADSPI_DCR_FSIZE | QUADSPI_DCR_CSHT | QUADSPI_DCR_CKMODE),
+               ((hqspi->Init.FlashSize << QUADSPI_DCR_FSIZE_Pos) |
+                hqspi->Init.ChipSelectHighTime | hqspi->Init.ClockMode));
+
+    /* Enable the QSPI peripheral */
+    __HAL_QSPI_ENABLE(hqspi);
+
+    /* Set QSPI error code to none */
+    hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
+
+    /* Initialize the QSPI state */
+    hqspi->State = HAL_QSPI_STATE_READY;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(hqspi);
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief De-Initialize the QSPI peripheral.
+  * @param hqspi QSPI handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_QSPI_DeInit(QSPI_HandleTypeDef *hqspi)
+{
+  /* Check the QSPI handle allocation */
+  if(hqspi == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Disable the QSPI Peripheral Clock */
+  __HAL_QSPI_DISABLE(hqspi);
+
+#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
+  if(hqspi->MspDeInitCallback == NULL)
+  {
+    hqspi->MspDeInitCallback = HAL_QSPI_MspDeInit;
+  }
+
+  /* DeInit the low level hardware */
+  hqspi->MspDeInitCallback(hqspi);
+#else
+  /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
+  HAL_QSPI_MspDeInit(hqspi);
+#endif
+
+  /* Set QSPI error code to none */
+  hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
+
+  /* Initialize the QSPI state */
+  hqspi->State = HAL_QSPI_STATE_RESET;
+
+  /* Release Lock */
+  __HAL_UNLOCK(hqspi);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief Initialize the QSPI MSP.
+  * @param hqspi QSPI handle
+  * @retval None
+  */
+__weak void HAL_QSPI_MspInit(QSPI_HandleTypeDef *hqspi)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hqspi);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_QSPI_MspInit can be implemented in the user file
+   */
+}
+
+/**
+  * @brief DeInitialize the QSPI MSP.
+  * @param hqspi QSPI handle
+  * @retval None
+  */
+__weak void HAL_QSPI_MspDeInit(QSPI_HandleTypeDef *hqspi)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hqspi);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_QSPI_MspDeInit can be implemented in the user file
+   */
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup QSPI_Exported_Functions_Group2 Input and Output operation functions
+  *  @brief QSPI Transmit/Receive functions
+  *
+@verbatim
+ ===============================================================================
+                      ##### IO operation functions #####
+ ===============================================================================
+    [..]
+    This subsection provides a set of functions allowing to :
+      (+) Handle the interrupts.
+      (+) Handle the command sequence.
+      (+) Transmit data in blocking, interrupt or DMA mode.
+      (+) Receive data in blocking, interrupt or DMA mode.
+      (+) Manage the auto-polling functional mode.
+      (+) Manage the memory-mapped functional mode.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief Handle QSPI interrupt request.
+  * @param hqspi QSPI handle
+  * @retval None
+  */
+void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi)
+{
+  __IO uint32_t *data_reg;
+  uint32_t flag = READ_REG(hqspi->Instance->SR);
+  uint32_t itsource = READ_REG(hqspi->Instance->CR);
+
+  /* QSPI Fifo Threshold interrupt occurred ----------------------------------*/
+  if(((flag & QSPI_FLAG_FT) != 0U) && ((itsource & QSPI_IT_FT) != 0U))
+  {
+    data_reg = &hqspi->Instance->DR;
+
+    if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_TX)
+    {
+      /* Transmission process */
+      while(__HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_FT) != RESET)
+      {
+        if (hqspi->TxXferCount > 0U)
+        {
+          /* Fill the FIFO until the threshold is reached */
+          *((__IO uint8_t *)data_reg) = *hqspi->pTxBuffPtr;
+          hqspi->pTxBuffPtr++;
+          hqspi->TxXferCount--;
+        }
+        else
+        {
+          /* No more data available for the transfer */
+          /* Disable the QSPI FIFO Threshold Interrupt */
+          __HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_FT);
+          break;
+        }
+      }
+    }
+    else if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_RX)
+    {
+      /* Receiving Process */
+      while(__HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_FT) != RESET)
+      {
+        if (hqspi->RxXferCount > 0U)
+        {
+          /* Read the FIFO until the threshold is reached */
+          *hqspi->pRxBuffPtr = *((__IO uint8_t *)data_reg);
+          hqspi->pRxBuffPtr++;
+          hqspi->RxXferCount--;
+        }
+        else
+        {
+          /* All data have been received for the transfer */
+          /* Disable the QSPI FIFO Threshold Interrupt */
+          __HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_FT);
+          break;
+        }
+      }
+    }
+    else
+    {
+      /* Nothing to do */
+    }
+
+    /* FIFO Threshold callback */
+#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
+    hqspi->FifoThresholdCallback(hqspi);
+#else
+    HAL_QSPI_FifoThresholdCallback(hqspi);
+#endif
+  }
+
+  /* QSPI Transfer Complete interrupt occurred -------------------------------*/
+  else if(((flag & QSPI_FLAG_TC) != 0U) && ((itsource & QSPI_IT_TC) != 0U))
+  {
+    /* Clear interrupt */
+    WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_TC);
+
+    /* Disable the QSPI FIFO Threshold, Transfer Error and Transfer complete Interrupts */
+    __HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_TC | QSPI_IT_TE | QSPI_IT_FT);
+
+    /* Transfer complete callback */
+    if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_TX)
+    {
+      if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN) != 0U)
+      {
+        /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */
+        CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
+
+        /* Disable the DMA channel */
+        __HAL_DMA_DISABLE(hqspi->hdma);
+      }
+
+      /* Clear Busy bit */
+      HAL_QSPI_Abort_IT(hqspi);
+
+      /* Change state of QSPI */
+      hqspi->State = HAL_QSPI_STATE_READY;
+
+      /* TX Complete callback */
+#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
+      hqspi->TxCpltCallback(hqspi);
+#else
+      HAL_QSPI_TxCpltCallback(hqspi);
+#endif
+    }
+    else if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_RX)
+    {
+      if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN) != 0U)
+      {
+        /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */
+        CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
+
+        /* Disable the DMA channel */
+        __HAL_DMA_DISABLE(hqspi->hdma);
+      }
+      else
+      {
+        data_reg = &hqspi->Instance->DR;
+        while(READ_BIT(hqspi->Instance->SR, QUADSPI_SR_FLEVEL) != 0U)
+        {
+          if (hqspi->RxXferCount > 0U)
+          {
+            /* Read the last data received in the FIFO until it is empty */
+            *hqspi->pRxBuffPtr = *((__IO uint8_t *)data_reg);
+            hqspi->pRxBuffPtr++;
+            hqspi->RxXferCount--;
+          }
+          else
+          {
+            /* All data have been received for the transfer */
+            break;
+          }
+        }
+      }
+
+      /* Workaround - Extra data written in the FIFO at the end of a read transfer */
+      HAL_QSPI_Abort_IT(hqspi);
+
+      /* Change state of QSPI */
+      hqspi->State = HAL_QSPI_STATE_READY;
+
+      /* RX Complete callback */
+#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
+      hqspi->RxCpltCallback(hqspi);
+#else
+      HAL_QSPI_RxCpltCallback(hqspi);
+#endif
+    }
+    else if(hqspi->State == HAL_QSPI_STATE_BUSY)
+    {
+      /* Change state of QSPI */
+      hqspi->State = HAL_QSPI_STATE_READY;
+
+      /* Command Complete callback */
+#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
+      hqspi->CmdCpltCallback(hqspi);
+#else
+      HAL_QSPI_CmdCpltCallback(hqspi);
+#endif
+    }
+    else if(hqspi->State == HAL_QSPI_STATE_ABORT)
+    {
+      /* Reset functional mode configuration to indirect write mode by default */
+      CLEAR_BIT(hqspi->Instance->CCR, QUADSPI_CCR_FMODE);
+
+      /* Change state of QSPI */
+      hqspi->State = HAL_QSPI_STATE_READY;
+
+      if (hqspi->ErrorCode == HAL_QSPI_ERROR_NONE)
+      {
+        /* Abort called by the user */
+
+        /* Abort Complete callback */
+#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
+        hqspi->AbortCpltCallback(hqspi);
+#else
+        HAL_QSPI_AbortCpltCallback(hqspi);
+#endif
+      }
+      else
+      {
+        /* Abort due to an error (eg :  DMA error) */
+
+        /* Error callback */
+#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
+        hqspi->ErrorCallback(hqspi);
+#else
+        HAL_QSPI_ErrorCallback(hqspi);
+#endif
+      }
+    }
+    else
+    {
+     /* Nothing to do */
+    }
+  }
+
+  /* QSPI Status Match interrupt occurred ------------------------------------*/
+  else if(((flag & QSPI_FLAG_SM) != 0U) && ((itsource & QSPI_IT_SM) != 0U))
+  {
+    /* Clear interrupt */
+    WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_SM);
+
+    /* Check if the automatic poll mode stop is activated */
+    if(READ_BIT(hqspi->Instance->CR, QUADSPI_CR_APMS) != 0U)
+    {
+      /* Disable the QSPI Transfer Error and Status Match Interrupts */
+      __HAL_QSPI_DISABLE_IT(hqspi, (QSPI_IT_SM | QSPI_IT_TE));
+
+      /* Change state of QSPI */
+      hqspi->State = HAL_QSPI_STATE_READY;
+    }
+
+    /* Status match callback */
+#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
+    hqspi->StatusMatchCallback(hqspi);
+#else
+    HAL_QSPI_StatusMatchCallback(hqspi);
+#endif
+  }
+
+  /* QSPI Transfer Error interrupt occurred ----------------------------------*/
+  else if(((flag & QSPI_FLAG_TE) != 0U) && ((itsource & QSPI_IT_TE) != 0U))
+  {
+    /* Clear interrupt */
+    WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_TE);
+
+    /* Disable all the QSPI Interrupts */
+    __HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_SM | QSPI_IT_TC | QSPI_IT_TE | QSPI_IT_FT);
+
+    /* Set error code */
+    hqspi->ErrorCode |= HAL_QSPI_ERROR_TRANSFER;
+
+    if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN) != 0U)
+    {
+      /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */
+      CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
+
+      /* Disable the DMA channel */
+      hqspi->hdma->XferAbortCallback = QSPI_DMAAbortCplt;
+      if (HAL_DMA_Abort_IT(hqspi->hdma) != HAL_OK)
+      {
+        /* Set error code to DMA */
+        hqspi->ErrorCode |= HAL_QSPI_ERROR_DMA;
+
+        /* Change state of QSPI */
+        hqspi->State = HAL_QSPI_STATE_READY;
+
+        /* Error callback */
+#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
+        hqspi->ErrorCallback(hqspi);
+#else
+        HAL_QSPI_ErrorCallback(hqspi);
+#endif
+      }
+    }
+    else
+    {
+      /* Change state of QSPI */
+      hqspi->State = HAL_QSPI_STATE_READY;
+
+      /* Error callback */
+#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
+      hqspi->ErrorCallback(hqspi);
+#else
+      HAL_QSPI_ErrorCallback(hqspi);
+#endif
+    }
+  }
+
+  /* QSPI Timeout interrupt occurred -----------------------------------------*/
+  else if(((flag & QSPI_FLAG_TO) != 0U) && ((itsource & QSPI_IT_TO) != 0U))
+  {
+    /* Clear interrupt */
+    WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_TO);
+
+    /* Timeout callback */
+#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
+    hqspi->TimeOutCallback(hqspi);
+#else
+    HAL_QSPI_TimeOutCallback(hqspi);
+#endif
+  }
+
+   else
+  {
+   /* Nothing to do */
+  }
+}
+
+/**
+  * @brief Set the command configuration.
+  * @param hqspi QSPI handle
+  * @param cmd : structure that contains the command configuration information
+  * @param Timeout Timeout duration
+  * @note   This function is used only in Indirect Read or Write Modes
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_QSPI_Command(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t Timeout)
+{
+  HAL_StatusTypeDef status;
+  uint32_t tickstart = HAL_GetTick();
+
+  /* Check the parameters */
+  assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));
+  if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
+  {
+    assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction));
+  }
+
+  assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode));
+  if (cmd->AddressMode != QSPI_ADDRESS_NONE)
+  {
+    assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize));
+  }
+
+  assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode));
+  if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
+  {
+    assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize));
+  }
+
+  assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles));
+  assert_param(IS_QSPI_DATA_MODE(cmd->DataMode));
+
+  assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode));
+  assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle));
+  assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));
+
+  /* Process locked */
+  __HAL_LOCK(hqspi);
+
+  if(hqspi->State == HAL_QSPI_STATE_READY)
+  {
+    hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
+
+    /* Update QSPI state */
+    hqspi->State = HAL_QSPI_STATE_BUSY;
+
+    /* Wait till BUSY flag reset */
+    status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, Timeout);
+
+    if (status == HAL_OK)
+    {
+      /* Call the configuration function */
+      QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
+
+      if (cmd->DataMode == QSPI_DATA_NONE)
+      {
+        /* When there is no data phase, the transfer start as soon as the configuration is done
+        so wait until TC flag is set to go back in idle state */
+        status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, tickstart, Timeout);
+
+        if (status == HAL_OK)
+        {
+          __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
+
+          /* Update QSPI state */
+          hqspi->State = HAL_QSPI_STATE_READY;
+        }
+      }
+      else
+      {
+        /* Update QSPI state */
+        hqspi->State = HAL_QSPI_STATE_READY;
+      }
+    }
+  }
+  else
+  {
+    status = HAL_BUSY;
+  }
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hqspi);
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief Set the command configuration in interrupt mode.
+  * @param hqspi QSPI handle
+  * @param cmd structure that contains the command configuration information
+  * @note   This function is used only in Indirect Read or Write Modes
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_QSPI_Command_IT(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd)
+{
+  HAL_StatusTypeDef status;
+
+  /* Check the parameters */
+  assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));
+  if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
+  {
+    assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction));
+  }
+
+  assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode));
+  if (cmd->AddressMode != QSPI_ADDRESS_NONE)
+  {
+    assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize));
+  }
+
+  assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode));
+  if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
+  {
+    assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize));
+  }
+
+  assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles));
+  assert_param(IS_QSPI_DATA_MODE(cmd->DataMode));
+
+  assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode));
+  assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle));
+  assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));
+
+  /* Process locked */
+  __HAL_LOCK(hqspi);
+
+  if(hqspi->State == HAL_QSPI_STATE_READY)
+  {
+    hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
+
+    /* Update QSPI state */
+    hqspi->State = HAL_QSPI_STATE_BUSY;
+
+    /* Wait till BUSY flag reset */
+    status = QSPI_WaitFlagStateUntilTimeout_CPUCycle(hqspi, QSPI_FLAG_BUSY, RESET, hqspi->Timeout);	
+
+    if (status == HAL_OK)
+    {
+      if (cmd->DataMode == QSPI_DATA_NONE)
+      {
+        /* Clear interrupt */
+        __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TE | QSPI_FLAG_TC);
+      }
+
+      /* Call the configuration function */
+      QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
+
+      if (cmd->DataMode == QSPI_DATA_NONE)
+      {
+        /* When there is no data phase, the transfer start as soon as the configuration is done
+        so activate TC and TE interrupts */
+        /* Process unlocked */
+        __HAL_UNLOCK(hqspi);
+
+        /* Enable the QSPI Transfer Error Interrupt */
+        __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE | QSPI_IT_TC);
+      }
+      else
+      {
+        /* Update QSPI state */
+        hqspi->State = HAL_QSPI_STATE_READY;
+
+        /* Process unlocked */
+        __HAL_UNLOCK(hqspi);
+      }
+    }
+    else
+    {
+      /* Process unlocked */
+      __HAL_UNLOCK(hqspi);
+    }
+  }
+  else
+  {
+    status = HAL_BUSY;
+
+    /* Process unlocked */
+    __HAL_UNLOCK(hqspi);
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief Transmit an amount of data in blocking mode.
+  * @param hqspi QSPI handle
+  * @param pData pointer to data buffer
+  * @param Timeout Timeout duration
+  * @note   This function is used only in Indirect Write Mode
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_QSPI_Transmit(QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  uint32_t tickstart = HAL_GetTick();
+  __IO uint32_t *data_reg = &hqspi->Instance->DR;
+
+  /* Process locked */
+  __HAL_LOCK(hqspi);
+
+  if(hqspi->State == HAL_QSPI_STATE_READY)
+  {
+    hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
+
+    if(pData != NULL )
+    {
+      /* Update state */
+      hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_TX;
+
+      /* Configure counters and size of the handle */
+      hqspi->TxXferCount = READ_REG(hqspi->Instance->DLR) + 1U;
+      hqspi->TxXferSize = READ_REG(hqspi->Instance->DLR) + 1U;
+      hqspi->pTxBuffPtr = pData;
+
+      /* Configure QSPI: CCR register with functional as indirect write */
+      MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
+
+      while(hqspi->TxXferCount > 0U)
+      {
+        /* Wait until FT flag is set to send data */
+        status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_FT, SET, tickstart, Timeout);
+
+        if (status != HAL_OK)
+        {
+          break;
+        }
+
+        *((__IO uint8_t *)data_reg) = *hqspi->pTxBuffPtr;
+        hqspi->pTxBuffPtr++;
+        hqspi->TxXferCount--;
+      }
+
+      if (status == HAL_OK)
+      {
+        /* Wait until TC flag is set to go back in idle state */
+        status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, tickstart, Timeout);
+
+        if (status == HAL_OK)
+        {
+          /* Clear Transfer Complete bit */
+          __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
+
+          /* Clear Busy bit */
+          status = HAL_QSPI_Abort(hqspi);
+        }
+      }
+
+      /* Update QSPI state */
+      hqspi->State = HAL_QSPI_STATE_READY;
+    }
+    else
+    {
+      hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;
+      status = HAL_ERROR;
+    }
+  }
+  else
+  {
+    status = HAL_BUSY;
+  }
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hqspi);
+
+  return status;
+}
+
+
+/**
+  * @brief Receive an amount of data in blocking mode.
+  * @param hqspi QSPI handle
+  * @param pData pointer to data buffer
+  * @param Timeout Timeout duration
+  * @note   This function is used only in Indirect Read Mode
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_QSPI_Receive(QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  uint32_t tickstart = HAL_GetTick();
+  uint32_t addr_reg = READ_REG(hqspi->Instance->AR);
+  __IO uint32_t *data_reg = &hqspi->Instance->DR;
+
+  /* Process locked */
+  __HAL_LOCK(hqspi);
+
+  if(hqspi->State == HAL_QSPI_STATE_READY)
+  {
+    hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
+
+    if(pData != NULL )
+    {
+      /* Update state */
+      hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_RX;
+
+      /* Configure counters and size of the handle */
+      hqspi->RxXferCount = READ_REG(hqspi->Instance->DLR) + 1U;
+      hqspi->RxXferSize = READ_REG(hqspi->Instance->DLR) + 1U;
+      hqspi->pRxBuffPtr = pData;
+
+      /* Configure QSPI: CCR register with functional as indirect read */
+      MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ);
+
+      /* Start the transfer by re-writing the address in AR register */
+      WRITE_REG(hqspi->Instance->AR, addr_reg);
+
+      while(hqspi->RxXferCount > 0U)
+      {
+        /* Wait until FT or TC flag is set to read received data */
+        status = QSPI_WaitFlagStateUntilTimeout(hqspi, (QSPI_FLAG_FT | QSPI_FLAG_TC), SET, tickstart, Timeout);
+
+        if  (status != HAL_OK)
+        {
+          break;
+        }
+
+        *hqspi->pRxBuffPtr = *((__IO uint8_t *)data_reg);
+        hqspi->pRxBuffPtr++;
+        hqspi->RxXferCount--;
+      }
+
+      if (status == HAL_OK)
+      {
+        /* Wait until TC flag is set to go back in idle state */
+        status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, tickstart, Timeout);
+
+        if  (status == HAL_OK)
+        {
+          /* Clear Transfer Complete bit */
+          __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
+
+          /* Workaround - Extra data written in the FIFO at the end of a read transfer */
+          status = HAL_QSPI_Abort(hqspi);
+        }
+      }
+
+      /* Update QSPI state */
+      hqspi->State = HAL_QSPI_STATE_READY;
+    }
+    else
+    {
+      hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;
+      status = HAL_ERROR;
+    }
+  }
+  else
+  {
+    status = HAL_BUSY;
+  }
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hqspi);
+
+  return status;
+}
+
+/**
+  * @brief  Send an amount of data in non-blocking mode with interrupt.
+  * @param  hqspi QSPI handle
+  * @param  pData pointer to data buffer
+  * @note   This function is used only in Indirect Write Mode
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_QSPI_Transmit_IT(QSPI_HandleTypeDef *hqspi, uint8_t *pData)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Process locked */
+  __HAL_LOCK(hqspi);
+
+  if(hqspi->State == HAL_QSPI_STATE_READY)
+  {
+    hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
+
+    if(pData != NULL )
+    {
+      /* Update state */
+      hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_TX;
+
+      /* Configure counters and size of the handle */
+      hqspi->TxXferCount = READ_REG(hqspi->Instance->DLR) + 1U;
+      hqspi->TxXferSize = READ_REG(hqspi->Instance->DLR) + 1U;
+      hqspi->pTxBuffPtr = pData;
+
+      /* Clear interrupt */
+      __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TE | QSPI_FLAG_TC);
+
+      /* Configure QSPI: CCR register with functional as indirect write */
+      MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
+
+      /* Process unlocked */
+      __HAL_UNLOCK(hqspi);
+
+      /* Enable the QSPI transfer error, FIFO threshold and transfer complete Interrupts */
+      __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE | QSPI_IT_FT | QSPI_IT_TC);
+    }
+    else
+    {
+      hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;
+      status = HAL_ERROR;
+
+      /* Process unlocked */
+      __HAL_UNLOCK(hqspi);
+    }
+  }
+  else
+  {
+    status = HAL_BUSY;
+
+    /* Process unlocked */
+    __HAL_UNLOCK(hqspi);
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Receive an amount of data in non-blocking mode with interrupt.
+  * @param  hqspi QSPI handle
+  * @param  pData pointer to data buffer
+  * @note   This function is used only in Indirect Read Mode
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_QSPI_Receive_IT(QSPI_HandleTypeDef *hqspi, uint8_t *pData)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  uint32_t addr_reg = READ_REG(hqspi->Instance->AR);
+
+  /* Process locked */
+  __HAL_LOCK(hqspi);
+
+  if(hqspi->State == HAL_QSPI_STATE_READY)
+  {
+    hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
+
+    if(pData != NULL )
+    {
+      /* Update state */
+      hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_RX;
+
+      /* Configure counters and size of the handle */
+      hqspi->RxXferCount = READ_REG(hqspi->Instance->DLR) + 1U;
+      hqspi->RxXferSize = READ_REG(hqspi->Instance->DLR) + 1U;
+      hqspi->pRxBuffPtr = pData;
+
+      /* Clear interrupt */
+      __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TE | QSPI_FLAG_TC);
+
+      /* Configure QSPI: CCR register with functional as indirect read */
+      MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ);
+
+      /* Start the transfer by re-writing the address in AR register */
+      WRITE_REG(hqspi->Instance->AR, addr_reg);
+
+      /* Process unlocked */
+      __HAL_UNLOCK(hqspi);
+
+      /* Enable the QSPI transfer error, FIFO threshold and transfer complete Interrupts */
+      __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE | QSPI_IT_FT | QSPI_IT_TC);
+    }
+    else
+    {
+      hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;
+      status = HAL_ERROR;
+
+      /* Process unlocked */
+      __HAL_UNLOCK(hqspi);
+    }
+  }
+  else
+  {
+    status = HAL_BUSY;
+
+    /* Process unlocked */
+    __HAL_UNLOCK(hqspi);
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Send an amount of data in non-blocking mode with DMA.
+  * @param  hqspi QSPI handle
+  * @param  pData pointer to data buffer
+  * @note   This function is used only in Indirect Write Mode
+  * @note   If DMA peripheral access is configured as halfword, the number
+  *         of data and the fifo threshold should be aligned on halfword
+  * @note   If DMA peripheral access is configured as word, the number
+  *         of data and the fifo threshold should be aligned on word
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_QSPI_Transmit_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pData)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  uint32_t data_size = (READ_REG(hqspi->Instance->DLR) + 1U);
+
+  /* Process locked */
+  __HAL_LOCK(hqspi);
+
+  if(hqspi->State == HAL_QSPI_STATE_READY)
+  {
+    /* Clear the error code */
+    hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
+
+    if(pData != NULL )
+    {
+      /* Configure counters of the handle */
+      if (hqspi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_BYTE)
+      {
+        hqspi->TxXferCount = data_size;
+      }
+      else if (hqspi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_HALFWORD)
+      {
+        if (((data_size % 2U) != 0U) || ((hqspi->Init.FifoThreshold % 2U) != 0U))
+        {
+          /* The number of data or the fifo threshold is not aligned on halfword
+          => no transfer possible with DMA peripheral access configured as halfword */
+          hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;
+          status = HAL_ERROR;
+
+          /* Process unlocked */
+          __HAL_UNLOCK(hqspi);
+        }
+        else
+        {
+          hqspi->TxXferCount = (data_size >> 1U);
+        }
+      }
+      else if (hqspi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_WORD)
+      {
+        if (((data_size % 4U) != 0U) || ((hqspi->Init.FifoThreshold % 4U) != 0U))
+        {
+          /* The number of data or the fifo threshold is not aligned on word
+          => no transfer possible with DMA peripheral access configured as word */
+          hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;
+          status = HAL_ERROR;
+
+          /* Process unlocked */
+          __HAL_UNLOCK(hqspi);
+        }
+        else
+        {
+          hqspi->TxXferCount = (data_size >> 2U);
+        }
+      }
+      else
+      {
+        /* Nothing to do */
+      }
+
+      if (status == HAL_OK)
+      {
+        /* Update state */
+        hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_TX;
+
+        /* Clear interrupt */
+        __HAL_QSPI_CLEAR_FLAG(hqspi, (QSPI_FLAG_TE | QSPI_FLAG_TC));
+
+        /* Configure size and pointer of the handle */
+        hqspi->TxXferSize = hqspi->TxXferCount;
+        hqspi->pTxBuffPtr = pData;
+
+        /* Configure QSPI: CCR register with functional mode as indirect write */
+        MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
+
+        /* Set the QSPI DMA transfer complete callback */
+        hqspi->hdma->XferCpltCallback = QSPI_DMATxCplt;
+
+        /* Set the QSPI DMA Half transfer complete callback */
+        hqspi->hdma->XferHalfCpltCallback = QSPI_DMATxHalfCplt;
+
+        /* Set the DMA error callback */
+        hqspi->hdma->XferErrorCallback = QSPI_DMAError;
+
+        /* Clear the DMA abort callback */
+        hqspi->hdma->XferAbortCallback = NULL;
+
+#if defined (QSPI1_V2_1L)
+        /* Bug "ES0305 section 2.1.8 In some specific cases, DMA2 data corruption occurs when managing
+           AHB and APB2 peripherals in a concurrent way" Workaround Implementation:
+           Change the following configuration of DMA peripheral
+             - Enable peripheral increment
+             - Disable memory increment
+             - Set DMA direction as peripheral to memory mode */
+
+        /* Enable peripheral increment mode of the DMA */
+        hqspi->hdma->Init.PeriphInc = DMA_PINC_ENABLE;
+
+        /* Disable memory increment mode of the DMA */
+        hqspi->hdma->Init.MemInc = DMA_MINC_DISABLE;
+
+        /* Update peripheral/memory increment mode bits */
+        MODIFY_REG(hqspi->hdma->Instance->CR, (DMA_SxCR_MINC | DMA_SxCR_PINC), (hqspi->hdma->Init.MemInc | hqspi->hdma->Init.PeriphInc));
+
+        /* Configure the direction of the DMA */
+        hqspi->hdma->Init.Direction = DMA_PERIPH_TO_MEMORY;
+#else
+        /* Configure the direction of the DMA */
+        hqspi->hdma->Init.Direction = DMA_MEMORY_TO_PERIPH;
+#endif /* QSPI1_V2_1L */
+
+        /* Update direction mode bit */
+        MODIFY_REG(hqspi->hdma->Instance->CR, DMA_SxCR_DIR, hqspi->hdma->Init.Direction);
+
+        /* Enable the QSPI transmit DMA Channel */
+        if (HAL_DMA_Start_IT(hqspi->hdma, (uint32_t)pData, (uint32_t)&hqspi->Instance->DR, hqspi->TxXferSize) == HAL_OK)
+        {
+          /* Process unlocked */
+          __HAL_UNLOCK(hqspi);
+
+          /* Enable the QSPI transfer error Interrupt */
+          __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE);
+
+          /* Enable the DMA transfer by setting the DMAEN bit in the QSPI CR register */
+          SET_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
+        }
+        else
+        {
+          status = HAL_ERROR;
+          hqspi->ErrorCode |= HAL_QSPI_ERROR_DMA;
+          hqspi->State = HAL_QSPI_STATE_READY;
+
+          /* Process unlocked */
+          __HAL_UNLOCK(hqspi);
+        }
+     }
+    }
+    else
+    {
+      hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;
+      status = HAL_ERROR;
+
+      /* Process unlocked */
+      __HAL_UNLOCK(hqspi);
+    }
+  }
+  else
+  {
+    status = HAL_BUSY;
+
+    /* Process unlocked */
+    __HAL_UNLOCK(hqspi);
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Receive an amount of data in non-blocking mode with DMA.
+  * @param  hqspi QSPI handle
+  * @param  pData pointer to data buffer.
+  * @note   This function is used only in Indirect Read Mode
+  * @note   If DMA peripheral access is configured as halfword, the number
+  *         of data and the fifo threshold should be aligned on halfword
+  * @note   If DMA peripheral access is configured as word, the number
+  *         of data and the fifo threshold should be aligned on word
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_QSPI_Receive_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pData)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  uint32_t addr_reg = READ_REG(hqspi->Instance->AR);
+  uint32_t data_size = (READ_REG(hqspi->Instance->DLR) + 1U);
+
+  /* Process locked */
+  __HAL_LOCK(hqspi);
+
+  if(hqspi->State == HAL_QSPI_STATE_READY)
+  {
+    /* Clear the error code */
+    hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
+
+    if(pData != NULL )
+    {
+      /* Configure counters of the handle */
+      if (hqspi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_BYTE)
+      {
+        hqspi->RxXferCount = data_size;
+      }
+      else if (hqspi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_HALFWORD)
+      {
+        if (((data_size % 2U) != 0U) || ((hqspi->Init.FifoThreshold % 2U) != 0U))
+        {
+          /* The number of data or the fifo threshold is not aligned on halfword
+             => no transfer possible with DMA peripheral access configured as halfword */
+          hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;
+          status = HAL_ERROR;
+
+          /* Process unlocked */
+          __HAL_UNLOCK(hqspi);
+        }
+        else
+        {
+          hqspi->RxXferCount = (data_size >> 1U);
+        }
+      }
+      else if (hqspi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_WORD)
+      {
+        if (((data_size % 4U) != 0U) || ((hqspi->Init.FifoThreshold % 4U) != 0U))
+        {
+          /* The number of data or the fifo threshold is not aligned on word
+             => no transfer possible with DMA peripheral access configured as word */
+          hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;
+          status = HAL_ERROR;
+
+          /* Process unlocked */
+          __HAL_UNLOCK(hqspi);
+        }
+        else
+        {
+          hqspi->RxXferCount = (data_size >> 2U);
+        }
+      }
+      else
+      {
+        /* Nothing to do */
+      }
+
+      if (status == HAL_OK)
+      {
+        /* Update state */
+        hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_RX;
+
+        /* Clear interrupt */
+        __HAL_QSPI_CLEAR_FLAG(hqspi, (QSPI_FLAG_TE | QSPI_FLAG_TC));
+
+        /* Configure size and pointer of the handle */
+        hqspi->RxXferSize = hqspi->RxXferCount;
+        hqspi->pRxBuffPtr = pData;
+
+        /* Set the QSPI DMA transfer complete callback */
+        hqspi->hdma->XferCpltCallback = QSPI_DMARxCplt;
+
+        /* Set the QSPI DMA Half transfer complete callback */
+        hqspi->hdma->XferHalfCpltCallback = QSPI_DMARxHalfCplt;
+
+        /* Set the DMA error callback */
+        hqspi->hdma->XferErrorCallback = QSPI_DMAError;
+
+        /* Clear the DMA abort callback */
+        hqspi->hdma->XferAbortCallback = NULL;
+
+#if defined (QSPI1_V2_1L)
+      /* Bug "ES0305 section 2.1.8 In some specific cases, DMA2 data corruption occurs when managing
+         AHB and APB2 peripherals in a concurrent way" Workaround Implementation:
+         Change the following configuration of DMA peripheral
+           - Enable peripheral increment
+           - Disable memory increment
+           - Set DMA direction as memory to peripheral mode
+           - 4 Extra words (32-bits) are added for read operation to guarantee
+              the last data is transferred from DMA FIFO to RAM memory */
+
+        /* Enable peripheral increment of the DMA */
+        hqspi->hdma->Init.PeriphInc = DMA_PINC_ENABLE;
+
+        /* Disable memory increment of the DMA */
+        hqspi->hdma->Init.MemInc = DMA_MINC_DISABLE;
+
+        /* Update peripheral/memory increment mode bits */
+        MODIFY_REG(hqspi->hdma->Instance->CR, (DMA_SxCR_MINC | DMA_SxCR_PINC), (hqspi->hdma->Init.MemInc | hqspi->hdma->Init.PeriphInc));
+
+        /* Configure the direction of the DMA */
+        hqspi->hdma->Init.Direction = DMA_MEMORY_TO_PERIPH;
+
+        /* 4 Extra words (32-bits) are needed for read operation to guarantee
+        the last data is transferred from DMA FIFO to RAM memory */
+        WRITE_REG(hqspi->Instance->DLR, (data_size - 1U + 16U));
+
+        /* Update direction mode bit */
+        MODIFY_REG(hqspi->hdma->Instance->CR, DMA_SxCR_DIR, hqspi->hdma->Init.Direction);
+
+        /* Configure QSPI: CCR register with functional as indirect read */
+        MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ);
+
+        /* Start the transfer by re-writing the address in AR register */
+        WRITE_REG(hqspi->Instance->AR, addr_reg);
+
+        /* Enable the DMA Channel */
+        if(HAL_DMA_Start_IT(hqspi->hdma, (uint32_t)&hqspi->Instance->DR, (uint32_t)pData, hqspi->RxXferSize) == HAL_OK)
+        {
+          /* Enable the DMA transfer by setting the DMAEN bit in the QSPI CR register */
+          SET_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
+
+          /* Process unlocked */
+          __HAL_UNLOCK(hqspi);
+
+          /* Enable the QSPI transfer error Interrupt */
+          __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE);
+        }
+        else
+        {
+          status = HAL_ERROR;
+          hqspi->ErrorCode |= HAL_QSPI_ERROR_DMA;
+          hqspi->State = HAL_QSPI_STATE_READY;
+
+          /* Process unlocked */
+          __HAL_UNLOCK(hqspi);
+        }
+#else
+        /* Configure the direction of the DMA */
+        hqspi->hdma->Init.Direction = DMA_PERIPH_TO_MEMORY;
+
+        /* Update direction mode bit */
+        MODIFY_REG(hqspi->hdma->Instance->CR, DMA_SxCR_DIR, hqspi->hdma->Init.Direction);
+
+        /* Enable the DMA Channel */
+        if(HAL_DMA_Start_IT(hqspi->hdma, (uint32_t)&hqspi->Instance->DR, (uint32_t)pData, hqspi->RxXferSize)== HAL_OK)
+        {
+          /* Configure QSPI: CCR register with functional as indirect read */
+          MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ);
+
+          /* Start the transfer by re-writing the address in AR register */
+          WRITE_REG(hqspi->Instance->AR, addr_reg);
+
+          /* Process unlocked */
+          __HAL_UNLOCK(hqspi);
+
+          /* Enable the QSPI transfer error Interrupt */
+          __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE);
+
+          /* Enable the DMA transfer by setting the DMAEN bit in the QSPI CR register */
+          SET_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
+        }
+        else
+        {
+          status = HAL_ERROR;
+          hqspi->ErrorCode |= HAL_QSPI_ERROR_DMA;
+          hqspi->State = HAL_QSPI_STATE_READY;
+
+          /* Process unlocked */
+          __HAL_UNLOCK(hqspi);
+        }
+#endif /* QSPI1_V2_1L */
+      }
+    }
+    else
+    {
+      hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;
+      status = HAL_ERROR;
+
+      /* Process unlocked */
+      __HAL_UNLOCK(hqspi);
+    }
+  }
+  else
+  {
+    status = HAL_BUSY;
+
+    /* Process unlocked */
+    __HAL_UNLOCK(hqspi);
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Configure the QSPI Automatic Polling Mode in blocking mode.
+  * @param  hqspi QSPI handle
+  * @param  cmd structure that contains the command configuration information.
+  * @param  cfg structure that contains the polling configuration information.
+  * @param  Timeout Timeout duration
+  * @note   This function is used only in Automatic Polling Mode
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_QSPI_AutoPolling(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg, uint32_t Timeout)
+{
+  HAL_StatusTypeDef status;
+  uint32_t tickstart = HAL_GetTick();
+
+  /* Check the parameters */
+  assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));
+  if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
+  {
+    assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction));
+  }
+
+  assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode));
+  if (cmd->AddressMode != QSPI_ADDRESS_NONE)
+  {
+    assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize));
+  }
+
+  assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode));
+  if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
+  {
+    assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize));
+  }
+
+  assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles));
+  assert_param(IS_QSPI_DATA_MODE(cmd->DataMode));
+
+  assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode));
+  assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle));
+  assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));
+
+  assert_param(IS_QSPI_INTERVAL(cfg->Interval));
+  assert_param(IS_QSPI_STATUS_BYTES_SIZE(cfg->StatusBytesSize));
+  assert_param(IS_QSPI_MATCH_MODE(cfg->MatchMode));
+
+  /* Process locked */
+  __HAL_LOCK(hqspi);
+
+  if(hqspi->State == HAL_QSPI_STATE_READY)
+  {
+    hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
+
+    /* Update state */
+    hqspi->State = HAL_QSPI_STATE_BUSY_AUTO_POLLING;
+
+    /* Wait till BUSY flag reset */
+    status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, Timeout);
+
+    if (status == HAL_OK)
+    {
+      /* Configure QSPI: PSMAR register with the status match value */
+      WRITE_REG(hqspi->Instance->PSMAR, cfg->Match);
+
+      /* Configure QSPI: PSMKR register with the status mask value */
+      WRITE_REG(hqspi->Instance->PSMKR, cfg->Mask);
+
+      /* Configure QSPI: PIR register with the interval value */
+      WRITE_REG(hqspi->Instance->PIR, cfg->Interval);
+
+      /* Configure QSPI: CR register with Match mode and Automatic stop enabled
+      (otherwise there will be an infinite loop in blocking mode) */
+      MODIFY_REG(hqspi->Instance->CR, (QUADSPI_CR_PMM | QUADSPI_CR_APMS),
+               (cfg->MatchMode | QSPI_AUTOMATIC_STOP_ENABLE));
+
+      /* Call the configuration function */
+      cmd->NbData = cfg->StatusBytesSize;
+      QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_AUTO_POLLING);
+
+      /* Wait until SM flag is set to go back in idle state */
+      status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_SM, SET, tickstart, Timeout);
+
+      if (status == HAL_OK)
+      {
+        __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_SM);
+
+        /* Update state */
+        hqspi->State = HAL_QSPI_STATE_READY;
+      }
+    }
+  }
+  else
+  {
+    status = HAL_BUSY;
+  }
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hqspi);
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  Configure the QSPI Automatic Polling Mode in non-blocking mode.
+  * @param  hqspi QSPI handle
+  * @param  cmd structure that contains the command configuration information.
+  * @param  cfg structure that contains the polling configuration information.
+  * @note   This function is used only in Automatic Polling Mode
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_QSPI_AutoPolling_IT(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg)
+{
+  HAL_StatusTypeDef status;
+
+  /* Check the parameters */
+  assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));
+  if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
+  {
+    assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction));
+  }
+
+  assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode));
+  if (cmd->AddressMode != QSPI_ADDRESS_NONE)
+  {
+    assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize));
+  }
+
+  assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode));
+  if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
+  {
+    assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize));
+  }
+
+  assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles));
+  assert_param(IS_QSPI_DATA_MODE(cmd->DataMode));
+
+  assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode));
+  assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle));
+  assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));
+
+  assert_param(IS_QSPI_INTERVAL(cfg->Interval));
+  assert_param(IS_QSPI_STATUS_BYTES_SIZE(cfg->StatusBytesSize));
+  assert_param(IS_QSPI_MATCH_MODE(cfg->MatchMode));
+  assert_param(IS_QSPI_AUTOMATIC_STOP(cfg->AutomaticStop));
+
+  /* Process locked */
+  __HAL_LOCK(hqspi);
+
+  if(hqspi->State == HAL_QSPI_STATE_READY)
+  {
+    hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
+
+    /* Update state */
+    hqspi->State = HAL_QSPI_STATE_BUSY_AUTO_POLLING;
+
+    /* Wait till BUSY flag reset */
+    status = QSPI_WaitFlagStateUntilTimeout_CPUCycle(hqspi, QSPI_FLAG_BUSY, RESET, hqspi->Timeout);	
+
+    if (status == HAL_OK)
+    {
+      /* Configure QSPI: PSMAR register with the status match value */
+      WRITE_REG(hqspi->Instance->PSMAR, cfg->Match);
+
+      /* Configure QSPI: PSMKR register with the status mask value */
+      WRITE_REG(hqspi->Instance->PSMKR, cfg->Mask);
+
+      /* Configure QSPI: PIR register with the interval value */
+      WRITE_REG(hqspi->Instance->PIR, cfg->Interval);
+
+      /* Configure QSPI: CR register with Match mode and Automatic stop mode */
+      MODIFY_REG(hqspi->Instance->CR, (QUADSPI_CR_PMM | QUADSPI_CR_APMS),
+               (cfg->MatchMode | cfg->AutomaticStop));
+
+      /* Clear interrupt */
+      __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TE | QSPI_FLAG_SM);
+
+      /* Call the configuration function */
+      cmd->NbData = cfg->StatusBytesSize;
+      QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_AUTO_POLLING);
+
+      /* Process unlocked */
+      __HAL_UNLOCK(hqspi);
+
+      /* Enable the QSPI Transfer Error and status match Interrupt */
+      __HAL_QSPI_ENABLE_IT(hqspi, (QSPI_IT_SM | QSPI_IT_TE));
+
+    }
+    else
+    {
+      /* Process unlocked */
+      __HAL_UNLOCK(hqspi);
+    }
+  }
+  else
+  {
+    status = HAL_BUSY;
+
+    /* Process unlocked */
+    __HAL_UNLOCK(hqspi);
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  Configure the Memory Mapped mode.
+  * @param  hqspi QSPI handle
+  * @param  cmd structure that contains the command configuration information.
+  * @param  cfg structure that contains the memory mapped configuration information.
+  * @note   This function is used only in Memory mapped Mode
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_QSPI_MemoryMapped(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_MemoryMappedTypeDef *cfg)
+{
+  HAL_StatusTypeDef status;
+  uint32_t tickstart = HAL_GetTick();
+
+  /* Check the parameters */
+  assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));
+  if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
+  {
+  assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction));
+  }
+
+  assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode));
+  if (cmd->AddressMode != QSPI_ADDRESS_NONE)
+  {
+    assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize));
+  }
+
+  assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode));
+  if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
+  {
+    assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize));
+  }
+
+  assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles));
+  assert_param(IS_QSPI_DATA_MODE(cmd->DataMode));
+
+  assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode));
+  assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle));
+  assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));
+
+  assert_param(IS_QSPI_TIMEOUT_ACTIVATION(cfg->TimeOutActivation));
+
+  /* Process locked */
+  __HAL_LOCK(hqspi);
+
+  if(hqspi->State == HAL_QSPI_STATE_READY)
+  {
+    hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
+
+    /* Update state */
+    hqspi->State = HAL_QSPI_STATE_BUSY_MEM_MAPPED;
+
+    /* Wait till BUSY flag reset */
+    status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout);
+
+    if (status == HAL_OK)
+    {
+      /* Configure QSPI: CR register with timeout counter enable */
+    MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_TCEN, cfg->TimeOutActivation);
+
+    if (cfg->TimeOutActivation == QSPI_TIMEOUT_COUNTER_ENABLE)
+      {
+        assert_param(IS_QSPI_TIMEOUT_PERIOD(cfg->TimeOutPeriod));
+
+        /* Configure QSPI: LPTR register with the low-power timeout value */
+        WRITE_REG(hqspi->Instance->LPTR, cfg->TimeOutPeriod);
+
+        /* Clear interrupt */
+        __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TO);
+
+        /* Enable the QSPI TimeOut Interrupt */
+        __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TO);
+      }
+
+      /* Call the configuration function */
+      QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED);
+    }
+  }
+  else
+  {
+    status = HAL_BUSY;
+  }
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hqspi);
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  Transfer Error callback.
+  * @param  hqspi QSPI handle
+  * @retval None
+  */
+__weak void HAL_QSPI_ErrorCallback(QSPI_HandleTypeDef *hqspi)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hqspi);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_QSPI_ErrorCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Abort completed callback.
+  * @param  hqspi QSPI handle
+  * @retval None
+  */
+__weak void HAL_QSPI_AbortCpltCallback(QSPI_HandleTypeDef *hqspi)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hqspi);
+
+  /* NOTE: This function should not be modified, when the callback is needed,
+           the HAL_QSPI_AbortCpltCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Command completed callback.
+  * @param  hqspi QSPI handle
+  * @retval None
+  */
+__weak void HAL_QSPI_CmdCpltCallback(QSPI_HandleTypeDef *hqspi)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hqspi);
+
+  /* NOTE: This function should not be modified, when the callback is needed,
+           the HAL_QSPI_CmdCpltCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Rx Transfer completed callback.
+  * @param  hqspi QSPI handle
+  * @retval None
+  */
+__weak void HAL_QSPI_RxCpltCallback(QSPI_HandleTypeDef *hqspi)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hqspi);
+
+  /* NOTE: This function should not be modified, when the callback is needed,
+           the HAL_QSPI_RxCpltCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Tx Transfer completed callback.
+  * @param  hqspi QSPI handle
+  * @retval None
+  */
+__weak void HAL_QSPI_TxCpltCallback(QSPI_HandleTypeDef *hqspi)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hqspi);
+
+  /* NOTE: This function should not be modified, when the callback is needed,
+           the HAL_QSPI_TxCpltCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Rx Half Transfer completed callback.
+  * @param  hqspi QSPI handle
+  * @retval None
+  */
+__weak void HAL_QSPI_RxHalfCpltCallback(QSPI_HandleTypeDef *hqspi)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hqspi);
+
+  /* NOTE: This function should not be modified, when the callback is needed,
+           the HAL_QSPI_RxHalfCpltCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Tx Half Transfer completed callback.
+  * @param  hqspi QSPI handle
+  * @retval None
+  */
+__weak void HAL_QSPI_TxHalfCpltCallback(QSPI_HandleTypeDef *hqspi)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hqspi);
+
+  /* NOTE: This function should not be modified, when the callback is needed,
+           the HAL_QSPI_TxHalfCpltCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  FIFO Threshold callback.
+  * @param  hqspi QSPI handle
+  * @retval None
+  */
+__weak void HAL_QSPI_FifoThresholdCallback(QSPI_HandleTypeDef *hqspi)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hqspi);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_QSPI_FIFOThresholdCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Status Match callback.
+  * @param  hqspi QSPI handle
+  * @retval None
+  */
+__weak void HAL_QSPI_StatusMatchCallback(QSPI_HandleTypeDef *hqspi)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hqspi);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_QSPI_StatusMatchCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Timeout callback.
+  * @param  hqspi QSPI handle
+  * @retval None
+  */
+__weak void HAL_QSPI_TimeOutCallback(QSPI_HandleTypeDef *hqspi)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hqspi);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_QSPI_TimeOutCallback could be implemented in the user file
+   */
+}
+#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
+/**
+  * @brief  Register a User QSPI Callback
+  *         To be used instead of the weak (surcharged) predefined callback
+  * @param hqspi QSPI handle
+  * @param CallbackId ID of the callback to be registered
+  *        This parameter can be one of the following values:
+  *          @arg @ref HAL_QSPI_ERROR_CB_ID          QSPI Error Callback ID
+  *          @arg @ref HAL_QSPI_ABORT_CB_ID          QSPI Abort Callback ID
+  *          @arg @ref HAL_QSPI_FIFO_THRESHOLD_CB_ID QSPI FIFO Threshold Callback ID
+  *          @arg @ref HAL_QSPI_CMD_CPLT_CB_ID       QSPI Command Complete Callback ID
+  *          @arg @ref HAL_QSPI_RX_CPLT_CB_ID        QSPI Rx Complete Callback ID
+  *          @arg @ref HAL_QSPI_TX_CPLT_CB_ID        QSPI Tx Complete Callback ID
+  *          @arg @ref HAL_QSPI_RX_HALF_CPLT_CB_ID   QSPI Rx Half Complete Callback ID
+  *          @arg @ref HAL_QSPI_TX_HALF_CPLT_CB_ID   QSPI Tx Half Complete Callback ID
+  *          @arg @ref HAL_QSPI_STATUS_MATCH_CB_ID   QSPI Status Match Callback ID
+  *          @arg @ref HAL_QSPI_TIMEOUT_CB_ID        QSPI Timeout Callback ID
+  *          @arg @ref HAL_QSPI_MSP_INIT_CB_ID       QSPI MspInit callback ID
+  *          @arg @ref HAL_QSPI_MSP_DEINIT_CB_ID     QSPI MspDeInit callback ID
+  * @param pCallback pointer to the Callback function
+  * @retval status
+  */
+HAL_StatusTypeDef HAL_QSPI_RegisterCallback (QSPI_HandleTypeDef *hqspi, HAL_QSPI_CallbackIDTypeDef CallbackId, pQSPI_CallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if(pCallback == NULL)
+  {
+    /* Update the error code */
+    hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_CALLBACK;
+    return HAL_ERROR;
+  }
+
+  /* Process locked */
+  __HAL_LOCK(hqspi);
+
+  if(hqspi->State == HAL_QSPI_STATE_READY)
+  {
+    switch (CallbackId)
+    {
+    case  HAL_QSPI_ERROR_CB_ID :
+      hqspi->ErrorCallback = pCallback;
+      break;
+    case HAL_QSPI_ABORT_CB_ID :
+      hqspi->AbortCpltCallback = pCallback;
+      break;
+    case HAL_QSPI_FIFO_THRESHOLD_CB_ID :
+      hqspi->FifoThresholdCallback = pCallback;
+      break;
+    case HAL_QSPI_CMD_CPLT_CB_ID :
+      hqspi->CmdCpltCallback = pCallback;
+      break;
+    case HAL_QSPI_RX_CPLT_CB_ID :
+      hqspi->RxCpltCallback = pCallback;
+      break;
+    case HAL_QSPI_TX_CPLT_CB_ID :
+      hqspi->TxCpltCallback = pCallback;
+      break;
+    case HAL_QSPI_RX_HALF_CPLT_CB_ID :
+      hqspi->RxHalfCpltCallback = pCallback;
+      break;
+    case HAL_QSPI_TX_HALF_CPLT_CB_ID :
+      hqspi->TxHalfCpltCallback = pCallback;
+      break;
+    case HAL_QSPI_STATUS_MATCH_CB_ID :
+      hqspi->StatusMatchCallback = pCallback;
+      break;
+    case HAL_QSPI_TIMEOUT_CB_ID :
+      hqspi->TimeOutCallback = pCallback;
+      break;
+    case HAL_QSPI_MSP_INIT_CB_ID :
+      hqspi->MspInitCallback = pCallback;
+      break;
+    case HAL_QSPI_MSP_DEINIT_CB_ID :
+      hqspi->MspDeInitCallback = pCallback;
+      break;
+    default :
+      /* Update the error code */
+      hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_CALLBACK;
+      /* update return status */
+      status =  HAL_ERROR;
+      break;
+    }
+  }
+  else if (hqspi->State == HAL_QSPI_STATE_RESET)
+  {
+    switch (CallbackId)
+    {
+    case HAL_QSPI_MSP_INIT_CB_ID :
+      hqspi->MspInitCallback = pCallback;
+      break;
+    case HAL_QSPI_MSP_DEINIT_CB_ID :
+      hqspi->MspDeInitCallback = pCallback;
+      break;
+    default :
+      /* Update the error code */
+      hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_CALLBACK;
+      /* update return status */
+      status =  HAL_ERROR;
+      break;
+    }
+  }
+  else
+  {
+    /* Update the error code */
+    hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_CALLBACK;
+    /* update return status */
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(hqspi);
+  return status;
+}
+
+/**
+  * @brief  Unregister a User QSPI Callback
+  *         QSPI Callback is redirected to the weak (surcharged) predefined callback
+  * @param hqspi QSPI handle
+  * @param CallbackId ID of the callback to be unregistered
+  *        This parameter can be one of the following values:
+  *          @arg @ref HAL_QSPI_ERROR_CB_ID          QSPI Error Callback ID
+  *          @arg @ref HAL_QSPI_ABORT_CB_ID          QSPI Abort Callback ID
+  *          @arg @ref HAL_QSPI_FIFO_THRESHOLD_CB_ID QSPI FIFO Threshold Callback ID
+  *          @arg @ref HAL_QSPI_CMD_CPLT_CB_ID       QSPI Command Complete Callback ID
+  *          @arg @ref HAL_QSPI_RX_CPLT_CB_ID        QSPI Rx Complete Callback ID
+  *          @arg @ref HAL_QSPI_TX_CPLT_CB_ID        QSPI Tx Complete Callback ID
+  *          @arg @ref HAL_QSPI_RX_HALF_CPLT_CB_ID   QSPI Rx Half Complete Callback ID
+  *          @arg @ref HAL_QSPI_TX_HALF_CPLT_CB_ID   QSPI Tx Half Complete Callback ID
+  *          @arg @ref HAL_QSPI_STATUS_MATCH_CB_ID   QSPI Status Match Callback ID
+  *          @arg @ref HAL_QSPI_TIMEOUT_CB_ID        QSPI Timeout Callback ID
+  *          @arg @ref HAL_QSPI_MSP_INIT_CB_ID       QSPI MspInit callback ID
+  *          @arg @ref HAL_QSPI_MSP_DEINIT_CB_ID     QSPI MspDeInit callback ID
+  * @retval status
+  */
+HAL_StatusTypeDef HAL_QSPI_UnRegisterCallback (QSPI_HandleTypeDef *hqspi, HAL_QSPI_CallbackIDTypeDef CallbackId)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Process locked */
+  __HAL_LOCK(hqspi);
+
+  if(hqspi->State == HAL_QSPI_STATE_READY)
+  {
+    switch (CallbackId)
+    {
+    case  HAL_QSPI_ERROR_CB_ID :
+      hqspi->ErrorCallback = HAL_QSPI_ErrorCallback;
+      break;
+    case HAL_QSPI_ABORT_CB_ID :
+      hqspi->AbortCpltCallback = HAL_QSPI_AbortCpltCallback;
+      break;
+    case HAL_QSPI_FIFO_THRESHOLD_CB_ID :
+      hqspi->FifoThresholdCallback = HAL_QSPI_FifoThresholdCallback;
+      break;
+    case HAL_QSPI_CMD_CPLT_CB_ID :
+      hqspi->CmdCpltCallback = HAL_QSPI_CmdCpltCallback;
+      break;
+    case HAL_QSPI_RX_CPLT_CB_ID :
+      hqspi->RxCpltCallback = HAL_QSPI_RxCpltCallback;
+      break;
+    case HAL_QSPI_TX_CPLT_CB_ID :
+      hqspi->TxCpltCallback = HAL_QSPI_TxCpltCallback;
+      break;
+    case HAL_QSPI_RX_HALF_CPLT_CB_ID :
+      hqspi->RxHalfCpltCallback = HAL_QSPI_RxHalfCpltCallback;
+      break;
+    case HAL_QSPI_TX_HALF_CPLT_CB_ID :
+      hqspi->TxHalfCpltCallback = HAL_QSPI_TxHalfCpltCallback;
+      break;
+    case HAL_QSPI_STATUS_MATCH_CB_ID :
+      hqspi->StatusMatchCallback = HAL_QSPI_StatusMatchCallback;
+      break;
+    case HAL_QSPI_TIMEOUT_CB_ID :
+      hqspi->TimeOutCallback = HAL_QSPI_TimeOutCallback;
+      break;
+    case HAL_QSPI_MSP_INIT_CB_ID :
+      hqspi->MspInitCallback = HAL_QSPI_MspInit;
+      break;
+    case HAL_QSPI_MSP_DEINIT_CB_ID :
+      hqspi->MspDeInitCallback = HAL_QSPI_MspDeInit;
+      break;
+    default :
+      /* Update the error code */
+      hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_CALLBACK;
+      /* update return status */
+      status =  HAL_ERROR;
+      break;
+    }
+  }
+  else if (hqspi->State == HAL_QSPI_STATE_RESET)
+  {
+    switch (CallbackId)
+    {
+    case HAL_QSPI_MSP_INIT_CB_ID :
+      hqspi->MspInitCallback = HAL_QSPI_MspInit;
+      break;
+    case HAL_QSPI_MSP_DEINIT_CB_ID :
+      hqspi->MspDeInitCallback = HAL_QSPI_MspDeInit;
+      break;
+    default :
+      /* Update the error code */
+      hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_CALLBACK;
+      /* update return status */
+      status =  HAL_ERROR;
+      break;
+    }
+  }
+  else
+  {
+    /* Update the error code */
+    hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_CALLBACK;
+    /* update return status */
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(hqspi);
+  return status;
+}
+#endif
+
+/**
+  * @}
+  */
+
+/** @defgroup QSPI_Exported_Functions_Group3 Peripheral Control and State functions
+  *  @brief   QSPI control and State functions
+  *
+@verbatim
+ ===============================================================================
+                  ##### Peripheral Control and State functions #####
+ ===============================================================================
+    [..]
+    This subsection provides a set of functions allowing to :
+      (+) Check in run-time the state of the driver.
+      (+) Check the error code set during last operation.
+      (+) Abort any operation.
+
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Return the QSPI handle state.
+  * @param  hqspi QSPI handle
+  * @retval HAL state
+  */
+HAL_QSPI_StateTypeDef HAL_QSPI_GetState(QSPI_HandleTypeDef *hqspi)
+{
+  /* Return QSPI handle state */
+  return hqspi->State;
+}
+
+/**
+* @brief  Return the QSPI error code.
+* @param  hqspi QSPI handle
+* @retval QSPI Error Code
+*/
+uint32_t HAL_QSPI_GetError(QSPI_HandleTypeDef *hqspi)
+{
+  return hqspi->ErrorCode;
+}
+
+/**
+* @brief  Abort the current transmission.
+* @param  hqspi QSPI handle
+* @retval HAL status
+*/
+HAL_StatusTypeDef HAL_QSPI_Abort(QSPI_HandleTypeDef *hqspi)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  uint32_t tickstart = HAL_GetTick();
+
+  /* Check if the state is in one of the busy states */
+  if (((uint32_t)hqspi->State & 0x2U) != 0U)
+  {
+    /* Process unlocked */
+    __HAL_UNLOCK(hqspi);
+
+    if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN) != 0U)
+    {
+      /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */
+      CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
+
+      /* Abort DMA channel */
+      status = HAL_DMA_Abort(hqspi->hdma);
+      if(status != HAL_OK)
+      {
+        hqspi->ErrorCode |= HAL_QSPI_ERROR_DMA;
+      }
+    }
+
+    if (__HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_BUSY) != RESET)
+    {
+      /* Configure QSPI: CR register with Abort request */
+      SET_BIT(hqspi->Instance->CR, QUADSPI_CR_ABORT);
+      
+      /* Wait until TC flag is set to go back in idle state */
+      status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, tickstart, hqspi->Timeout);
+      
+      if (status == HAL_OK)
+      {
+        __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
+        
+        /* Wait until BUSY flag is reset */
+        status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout);
+      }
+
+      if (status == HAL_OK)
+      {
+        /* Reset functional mode configuration to indirect write mode by default */
+        CLEAR_BIT(hqspi->Instance->CCR, QUADSPI_CCR_FMODE);
+        
+        /* Update state */
+        hqspi->State = HAL_QSPI_STATE_READY;
+      }
+    }
+    else
+    {
+      /* Update state */
+      hqspi->State = HAL_QSPI_STATE_READY;
+    }
+  }
+
+  return status;
+}
+
+/**
+* @brief  Abort the current transmission (non-blocking function)
+* @param  hqspi QSPI handle
+* @retval HAL status
+*/
+HAL_StatusTypeDef HAL_QSPI_Abort_IT(QSPI_HandleTypeDef *hqspi)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check if the state is in one of the busy states */
+  if (((uint32_t)hqspi->State & 0x2U) != 0U)
+  {
+    /* Process unlocked */
+    __HAL_UNLOCK(hqspi);
+
+    /* Update QSPI state */
+    hqspi->State = HAL_QSPI_STATE_ABORT;
+
+    /* Disable all interrupts */
+    __HAL_QSPI_DISABLE_IT(hqspi, (QSPI_IT_TO | QSPI_IT_SM | QSPI_IT_FT | QSPI_IT_TC | QSPI_IT_TE));
+
+    if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN) != 0U)
+    {
+      /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */
+      CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
+
+      /* Abort DMA channel */
+      hqspi->hdma->XferAbortCallback = QSPI_DMAAbortCplt;
+      if (HAL_DMA_Abort_IT(hqspi->hdma) != HAL_OK)
+      {
+        /* Change state of QSPI */
+        hqspi->State = HAL_QSPI_STATE_READY;
+
+        /* Abort Complete callback */
+#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
+        hqspi->AbortCpltCallback(hqspi);
+#else
+        HAL_QSPI_AbortCpltCallback(hqspi);
+#endif
+      }
+    }
+    else
+    {
+      if (__HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_BUSY) != RESET)
+      {
+        /* Clear interrupt */
+        __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
+        
+        /* Enable the QSPI Transfer Complete Interrupt */
+        __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TC);
+        
+        /* Configure QSPI: CR register with Abort request */
+        SET_BIT(hqspi->Instance->CR, QUADSPI_CR_ABORT);
+      }    
+      else
+      {
+        /* Change state of QSPI */
+        hqspi->State = HAL_QSPI_STATE_READY;
+      }
+    }
+  }
+  return status;
+}
+
+/** @brief Set QSPI timeout.
+  * @param  hqspi QSPI handle.
+  * @param  Timeout Timeout for the QSPI memory access.
+  * @retval None
+  */
+void HAL_QSPI_SetTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Timeout)
+{
+  hqspi->Timeout = Timeout;
+}
+
+/** @brief Set QSPI Fifo threshold.
+  * @param  hqspi QSPI handle.
+  * @param  Threshold Threshold of the Fifo (value between 1 and 16).
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_QSPI_SetFifoThreshold(QSPI_HandleTypeDef *hqspi, uint32_t Threshold)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Process locked */
+  __HAL_LOCK(hqspi);
+
+  if(hqspi->State == HAL_QSPI_STATE_READY)
+  {
+    /* Synchronize init structure with new FIFO threshold value */
+    hqspi->Init.FifoThreshold = Threshold;
+
+    /* Configure QSPI FIFO Threshold */
+    MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_FTHRES,
+               ((hqspi->Init.FifoThreshold - 1U) << QUADSPI_CR_FTHRES_Pos));
+  }
+  else
+  {
+    status = HAL_BUSY;
+  }
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hqspi);
+
+  /* Return function status */
+  return status;
+}
+
+/** @brief Get QSPI Fifo threshold.
+  * @param  hqspi QSPI handle.
+  * @retval Fifo threshold (value between 1 and 16)
+  */
+uint32_t HAL_QSPI_GetFifoThreshold(QSPI_HandleTypeDef *hqspi)
+{
+  return ((READ_BIT(hqspi->Instance->CR, QUADSPI_CR_FTHRES) >> QUADSPI_CR_FTHRES_Pos) + 1U);
+}
+
+/** @brief  Set FlashID.
+  * @param  hqspi QSPI handle.
+  * @param  FlashID Index of the flash memory to be accessed.
+  *                   This parameter can be a value of @ref QSPI_Flash_Select.
+  * @note   The FlashID is ignored when dual flash mode is enabled.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_QSPI_SetFlashID(QSPI_HandleTypeDef *hqspi, uint32_t FlashID)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the parameter */
+  assert_param(IS_QSPI_FLASH_ID(FlashID));
+
+  /* Process locked */
+  __HAL_LOCK(hqspi);
+
+  if(hqspi->State == HAL_QSPI_STATE_READY)
+  {
+    /* Synchronize init structure with new FlashID value */
+    hqspi->Init.FlashID = FlashID;
+
+    /* Configure QSPI FlashID */
+    MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_FSEL, FlashID);
+  }
+  else
+  {
+    status = HAL_BUSY;
+  }
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hqspi);
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup QSPI_Private_Functions QSPI Private Functions
+  * @{
+  */
+
+/**
+  * @brief  DMA QSPI receive process complete callback.
+  * @param  hdma DMA handle
+  * @retval None
+  */
+static void QSPI_DMARxCplt(DMA_HandleTypeDef *hdma)
+{
+  QSPI_HandleTypeDef* hqspi = (QSPI_HandleTypeDef*)(hdma->Parent);
+  hqspi->RxXferCount = 0U;
+
+  /* Enable the QSPI transfer complete Interrupt */
+  __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TC);
+}
+
+/**
+  * @brief  DMA QSPI transmit process complete callback.
+  * @param  hdma DMA handle
+  * @retval None
+  */
+static void QSPI_DMATxCplt(DMA_HandleTypeDef *hdma)
+{
+  QSPI_HandleTypeDef* hqspi = (QSPI_HandleTypeDef*)(hdma->Parent);
+  hqspi->TxXferCount = 0U;
+
+  /* Enable the QSPI transfer complete Interrupt */
+  __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TC);
+}
+
+/**
+  * @brief  DMA QSPI receive process half complete callback.
+  * @param  hdma DMA handle
+  * @retval None
+  */
+static void QSPI_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
+{
+  QSPI_HandleTypeDef* hqspi = (QSPI_HandleTypeDef*)(hdma->Parent);
+
+#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
+  hqspi->RxHalfCpltCallback(hqspi);
+#else
+  HAL_QSPI_RxHalfCpltCallback(hqspi);
+#endif
+}
+
+/**
+  * @brief  DMA QSPI transmit process half complete callback.
+  * @param  hdma DMA handle
+  * @retval None
+  */
+static void QSPI_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
+{
+  QSPI_HandleTypeDef* hqspi = (QSPI_HandleTypeDef*)(hdma->Parent);
+
+#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
+  hqspi->TxHalfCpltCallback(hqspi);
+#else
+  HAL_QSPI_TxHalfCpltCallback(hqspi);
+#endif
+}
+
+/**
+  * @brief  DMA QSPI communication error callback.
+  * @param  hdma DMA handle
+  * @retval None
+  */
+static void QSPI_DMAError(DMA_HandleTypeDef *hdma)
+{
+  QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )(hdma->Parent);
+
+  /* if DMA error is FIFO error ignore it */
+  if(HAL_DMA_GetError(hdma) != HAL_DMA_ERROR_FE)
+  {
+  hqspi->RxXferCount = 0U;
+  hqspi->TxXferCount = 0U;
+  hqspi->ErrorCode   |= HAL_QSPI_ERROR_DMA;
+
+  /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */
+  CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
+
+  /* Abort the QSPI */
+  (void)HAL_QSPI_Abort_IT(hqspi);
+
+  }
+}
+
+/**
+  * @brief  DMA QSPI abort complete callback.
+  * @param  hdma DMA handle
+  * @retval None
+  */
+static void QSPI_DMAAbortCplt(DMA_HandleTypeDef *hdma)
+{
+  QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )(hdma->Parent);
+
+  hqspi->RxXferCount = 0U;
+  hqspi->TxXferCount = 0U;
+
+  if(hqspi->State == HAL_QSPI_STATE_ABORT)
+  {
+    /* DMA Abort called by QSPI abort */
+    /* Clear interrupt */
+    __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
+
+    /* Enable the QSPI Transfer Complete Interrupt */
+    __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TC);
+
+    /* Configure QSPI: CR register with Abort request */
+    SET_BIT(hqspi->Instance->CR, QUADSPI_CR_ABORT);
+  }
+  else
+  {
+    /* DMA Abort called due to a transfer error interrupt */
+    /* Change state of QSPI */
+    hqspi->State = HAL_QSPI_STATE_READY;
+
+    /* Error callback */
+#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
+    hqspi->ErrorCallback(hqspi);
+#else
+    HAL_QSPI_ErrorCallback(hqspi);
+#endif
+  }
+}
+
+/**
+  * @brief  Wait for a flag state until timeout.
+  * @param  hqspi QSPI handle
+  * @param  Flag Flag checked
+  * @param  State Value of the flag expected
+  * @param  Tickstart Tick start value
+  * @param  Timeout Duration of the timeout
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef QSPI_WaitFlagStateUntilTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Flag,
+                                                        FlagStatus State, uint32_t Tickstart, uint32_t Timeout)
+{
+  /* Wait until flag is in expected state */
+  while((__HAL_QSPI_GET_FLAG(hqspi, Flag)) != State)
+  {
+    /* Check for the Timeout */
+    if (Timeout != HAL_MAX_DELAY)
+    {
+      if(((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
+      {
+        hqspi->State     = HAL_QSPI_STATE_ERROR;
+        hqspi->ErrorCode |= HAL_QSPI_ERROR_TIMEOUT;
+
+        return HAL_ERROR;
+      }
+    }
+  }
+  return HAL_OK;
+}
+
+/**
+  * @brief  Wait for a flag state until timeout using CPU cycle.
+  * @param  hqspi : QSPI handle
+  * @param  Flag : Flag checked
+  * @param  State : Value of the flag expected
+  * @param  Timeout : Duration of the timeout
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef QSPI_WaitFlagStateUntilTimeout_CPUCycle(QSPI_HandleTypeDef *hqspi, uint32_t Flag, FlagStatus State, uint32_t Timeout)
+{ 
+  __IO uint32_t count = Timeout * (SystemCoreClock / 16U / 1000U);
+   do
+   {
+     if (count-- == 0U)
+     {
+       hqspi->State     = HAL_QSPI_STATE_ERROR;
+       hqspi->ErrorCode |= HAL_QSPI_ERROR_TIMEOUT;
+       return HAL_TIMEOUT;
+     }
+   }
+   while ((__HAL_QSPI_GET_FLAG(hqspi, Flag)) != State);
+   
+   return HAL_OK;   
+}
+
+/**
+  * @brief  Configure the communication registers.
+  * @param  hqspi QSPI handle
+  * @param  cmd structure that contains the command configuration information
+  * @param  FunctionalMode functional mode to configured
+  *           This parameter can be one of the following values:
+  *            @arg QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE: Indirect write mode
+  *            @arg QSPI_FUNCTIONAL_MODE_INDIRECT_READ: Indirect read mode
+  *            @arg QSPI_FUNCTIONAL_MODE_AUTO_POLLING: Automatic polling mode
+  *            @arg QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED: Memory-mapped mode
+  * @retval None
+  */
+static void QSPI_Config(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t FunctionalMode)
+{
+  assert_param(IS_QSPI_FUNCTIONAL_MODE(FunctionalMode));
+
+  if ((cmd->DataMode != QSPI_DATA_NONE) && (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED))
+  {
+    /* Configure QSPI: DLR register with the number of data to read or write */
+    WRITE_REG(hqspi->Instance->DLR, (cmd->NbData - 1U));
+  }
+
+  if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
+  {
+    if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
+    {
+      /* Configure QSPI: ABR register with alternate bytes value */
+      WRITE_REG(hqspi->Instance->ABR, cmd->AlternateBytes);
+
+      if (cmd->AddressMode != QSPI_ADDRESS_NONE)
+      {
+        /*---- Command with instruction, address and alternate bytes ----*/
+        /* Configure QSPI: CCR register with all communications parameters */
+        WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
+                                         cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) |
+                                         cmd->AlternateBytesSize | cmd->AlternateByteMode |
+                                         cmd->AddressSize | cmd->AddressMode | cmd->InstructionMode |
+                                         cmd->Instruction | FunctionalMode));
+
+        if (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED)
+        {
+          /* Configure QSPI: AR register with address value */
+          WRITE_REG(hqspi->Instance->AR, cmd->Address);
+        }
+      }
+      else
+      {
+        /*---- Command with instruction and alternate bytes ----*/
+        /* Configure QSPI: CCR register with all communications parameters */
+        WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
+                                         cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) |
+                                         cmd->AlternateBytesSize | cmd->AlternateByteMode |
+                                         cmd->AddressMode | cmd->InstructionMode |
+                                         cmd->Instruction | FunctionalMode));
+      }
+    }
+    else
+    {
+      if (cmd->AddressMode != QSPI_ADDRESS_NONE)
+      {
+        /*---- Command with instruction and address ----*/
+        /* Configure QSPI: CCR register with all communications parameters */
+        WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
+                                         cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) |
+                                         cmd->AlternateByteMode | cmd->AddressSize | cmd->AddressMode |
+                                         cmd->InstructionMode | cmd->Instruction | FunctionalMode));
+
+        if (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED)
+        {
+          /* Configure QSPI: AR register with address value */
+          WRITE_REG(hqspi->Instance->AR, cmd->Address);
+        }
+      }
+      else
+      {
+        /*---- Command with only instruction ----*/
+        /* Configure QSPI: CCR register with all communications parameters */
+        WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
+                                         cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) |
+                                         cmd->AlternateByteMode | cmd->AddressMode |
+                                         cmd->InstructionMode | cmd->Instruction | FunctionalMode));
+      }
+    }
+  }
+  else
+  {
+    if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
+    {
+      /* Configure QSPI: ABR register with alternate bytes value */
+      WRITE_REG(hqspi->Instance->ABR, cmd->AlternateBytes);
+
+      if (cmd->AddressMode != QSPI_ADDRESS_NONE)
+      {
+        /*---- Command with address and alternate bytes ----*/
+        /* Configure QSPI: CCR register with all communications parameters */
+        WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
+                                         cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) |
+                                         cmd->AlternateBytesSize | cmd->AlternateByteMode |
+                                         cmd->AddressSize | cmd->AddressMode |
+                                         cmd->InstructionMode | FunctionalMode));
+
+        if (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED)
+        {
+          /* Configure QSPI: AR register with address value */
+          WRITE_REG(hqspi->Instance->AR, cmd->Address);
+        }
+      }
+      else
+      {
+        /*---- Command with only alternate bytes ----*/
+        /* Configure QSPI: CCR register with all communications parameters */
+        WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
+                                         cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) |
+                                         cmd->AlternateBytesSize | cmd->AlternateByteMode |
+                                         cmd->AddressMode | cmd->InstructionMode | FunctionalMode));
+      }
+    }
+    else
+    {
+      if (cmd->AddressMode != QSPI_ADDRESS_NONE)
+      {
+        /*---- Command with only address ----*/
+        /* Configure QSPI: CCR register with all communications parameters */
+        WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
+                                         cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) |
+                                         cmd->AlternateByteMode | cmd->AddressSize |
+                                         cmd->AddressMode | cmd->InstructionMode | FunctionalMode));
+
+        if (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED)
+        {
+          /* Configure QSPI: AR register with address value */
+          WRITE_REG(hqspi->Instance->AR, cmd->Address);
+        }
+      }
+      else
+      {
+        /*---- Command with only data phase ----*/
+        if (cmd->DataMode != QSPI_DATA_NONE)
+        {
+          /* Configure QSPI: CCR register with all communications parameters */
+          WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
+                                           cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) |
+                                           cmd->AlternateByteMode | cmd->AddressMode |
+                                           cmd->InstructionMode | FunctionalMode));
+        }
+      }
+    }
+  }
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* HAL_QSPI_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* defined(QUADSPI) */
diff --git a/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c
new file mode 100644
index 0000000..79364b6
--- /dev/null
+++ b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c
@@ -0,0 +1,1122 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hal_rcc.c
+  * @author  MCD Application Team
+  * @brief   RCC HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the Reset and Clock Control (RCC) peripheral:
+  *           + Initialization and de-initialization functions
+  *           + Peripheral Control functions
+  *
+  @verbatim
+  ==============================================================================
+                      ##### RCC specific features #####
+  ==============================================================================
+    [..]
+      After reset the device is running from Internal High Speed oscillator
+      (HSI 16MHz) with Flash 0 wait state, Flash prefetch buffer, D-Cache
+      and I-Cache are disabled, and all peripherals are off except internal
+      SRAM, Flash and JTAG.
+      (+) There is no prescaler on High speed (AHB) and Low speed (APB) busses;
+          all peripherals mapped on these busses are running at HSI speed.
+      (+) The clock for all peripherals is switched off, except the SRAM and FLASH.
+      (+) All GPIOs are in input floating state, except the JTAG pins which
+          are assigned to be used for debug purpose.
+
+    [..]
+      Once the device started from reset, the user application has to:
+      (+) Configure the clock source to be used to drive the System clock
+          (if the application needs higher frequency/performance)
+      (+) Configure the System clock frequency and Flash settings
+      (+) Configure the AHB and APB busses prescalers
+      (+) Enable the clock for the peripheral(s) to be used
+      (+) Configure the clock source(s) for peripherals which clocks are not
+          derived from the System clock (I2S, RTC, ADC, USB OTG FS/SDIO/RNG)
+
+                      ##### RCC Limitations #####
+  ==============================================================================
+    [..]
+      A delay between an RCC peripheral clock enable and the effective peripheral
+      enabling should be taken into account in order to manage the peripheral read/write
+      from/to registers.
+      (+) This delay depends on the peripheral mapping.
+      (+) If peripheral is mapped on AHB: the delay is 2 AHB clock cycle
+          after the clock enable bit is set on the hardware register
+      (+) If peripheral is mapped on APB: the delay is 2 APB clock cycle
+          after the clock enable bit is set on the hardware register
+
+    [..]
+      Implemented Workaround:
+      (+) For AHB & APB peripherals, a dummy read to the peripheral register has been
+          inserted in each __HAL_RCC_PPP_CLK_ENABLE() macro.
+
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file in
+  * the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup RCC RCC
+  * @brief RCC HAL module driver
+  * @{
+  */
+
+#ifdef HAL_RCC_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @addtogroup RCC_Private_Constants
+  * @{
+  */
+
+/* Private macro -------------------------------------------------------------*/
+#define __MCO1_CLK_ENABLE()   __HAL_RCC_GPIOA_CLK_ENABLE()
+#define MCO1_GPIO_PORT        GPIOA
+#define MCO1_PIN              GPIO_PIN_8
+
+#define __MCO2_CLK_ENABLE()   __HAL_RCC_GPIOC_CLK_ENABLE()
+#define MCO2_GPIO_PORT         GPIOC
+#define MCO2_PIN               GPIO_PIN_9
+/**
+  * @}
+  */
+
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup RCC_Private_Variables RCC Private Variables
+  * @{
+  */
+/**
+  * @}
+  */
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup RCC_Exported_Functions RCC Exported Functions
+  *  @{
+  */
+
+/** @defgroup RCC_Exported_Functions_Group1 Initialization and de-initialization functions
+ *  @brief    Initialization and Configuration functions
+ *
+@verbatim
+ ===============================================================================
+           ##### Initialization and de-initialization functions #####
+ ===============================================================================
+    [..]
+      This section provides functions allowing to configure the internal/external oscillators
+      (HSE, HSI, LSE, LSI, PLL, CSS and MCO) and the System busses clocks (SYSCLK, AHB, APB1
+       and APB2).
+
+    [..] Internal/external clock and PLL configuration
+         (#) HSI (high-speed internal), 16 MHz factory-trimmed RC used directly or through
+             the PLL as System clock source.
+
+         (#) LSI (low-speed internal), 32 KHz low consumption RC used as IWDG and/or RTC
+             clock source.
+
+         (#) HSE (high-speed external), 4 to 26 MHz crystal oscillator used directly or
+             through the PLL as System clock source. Can be used also as RTC clock source.
+
+         (#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source.
+
+         (#) PLL (clocked by HSI or HSE), featuring two different output clocks:
+           (++) The first output is used to generate the high speed system clock (up to 168 MHz)
+           (++) The second output is used to generate the clock for the USB OTG FS (48 MHz),
+                the random analog generator (<=48 MHz) and the SDIO (<= 48 MHz).
+
+         (#) CSS (Clock security system), once enable using the macro __HAL_RCC_CSS_ENABLE()
+             and if a HSE clock failure occurs(HSE used directly or through PLL as System
+             clock source), the System clocks automatically switched to HSI and an interrupt
+             is generated if enabled. The interrupt is linked to the Cortex-M4 NMI
+             (Non-Maskable Interrupt) exception vector.
+
+         (#) MCO1 (microcontroller clock output), used to output HSI, LSE, HSE or PLL
+             clock (through a configurable prescaler) on PA8 pin.
+
+         (#) MCO2 (microcontroller clock output), used to output HSE, PLL, SYSCLK or PLLI2S
+             clock (through a configurable prescaler) on PC9 pin.
+
+    [..] System, AHB and APB busses clocks configuration
+         (#) Several clock sources can be used to drive the System clock (SYSCLK): HSI,
+             HSE and PLL.
+             The AHB clock (HCLK) is derived from System clock through configurable
+             prescaler and used to clock the CPU, memory and peripherals mapped
+             on AHB bus (DMA, GPIO...). APB1 (PCLK1) and APB2 (PCLK2) clocks are derived
+             from AHB clock through configurable prescalers and used to clock
+             the peripherals mapped on these busses. You can use
+             "HAL_RCC_GetSysClockFreq()" function to retrieve the frequencies of these clocks.
+
+         (#) For the STM32F405xx/07xx and STM32F415xx/17xx devices, the maximum
+             frequency of the SYSCLK and HCLK is 168 MHz, PCLK2 84 MHz and PCLK1 42 MHz.
+             Depending on the device voltage range, the maximum frequency should
+             be adapted accordingly (refer to the product datasheets for more details).
+
+         (#) For the STM32F42xxx, STM32F43xxx, STM32F446xx, STM32F469xx and STM32F479xx devices,
+             the maximum frequency of the SYSCLK and HCLK is 180 MHz, PCLK2 90 MHz and PCLK1 45 MHz.
+             Depending on the device voltage range, the maximum frequency should
+             be adapted accordingly (refer to the product datasheets for more details).
+
+         (#) For the STM32F401xx, the maximum frequency of the SYSCLK and HCLK is 84 MHz,
+             PCLK2 84 MHz and PCLK1 42 MHz.
+             Depending on the device voltage range, the maximum frequency should
+             be adapted accordingly (refer to the product datasheets for more details).
+
+         (#) For the STM32F41xxx, the maximum frequency of the SYSCLK and HCLK is 100 MHz,
+             PCLK2 100 MHz and PCLK1 50 MHz.
+             Depending on the device voltage range, the maximum frequency should
+             be adapted accordingly (refer to the product datasheets for more details).
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Resets the RCC clock configuration to the default reset state.
+  * @note   The default reset state of the clock configuration is given below:
+  *            - HSI ON and used as system clock source
+  *            - HSE and PLL OFF
+  *            - AHB, APB1 and APB2 prescaler set to 1.
+  *            - CSS, MCO1 and MCO2 OFF
+  *            - All interrupts disabled
+  * @note   This function doesn't modify the configuration of the
+  *            - Peripheral clocks
+  *            - LSI, LSE and RTC clocks
+  * @retval HAL status
+  */
+__weak HAL_StatusTypeDef HAL_RCC_DeInit(void)
+{
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the RCC Oscillators according to the specified parameters in the
+  *         RCC_OscInitTypeDef.
+  * @param  RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that
+  *         contains the configuration information for the RCC Oscillators.
+  * @note   The PLL is not disabled when used as system clock.
+  * @note   Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not
+  *         supported by this API. User should request a transition to LSE Off
+  *         first and then LSE On or LSE Bypass.
+  * @note   Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not
+  *         supported by this API. User should request a transition to HSE Off
+  *         first and then HSE On or HSE Bypass.
+  * @retval HAL status
+  */
+__weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct)
+{
+  uint32_t tickstart, pll_config;
+
+  /* Check Null pointer */
+  if(RCC_OscInitStruct == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
+  /*------------------------------- HSE Configuration ------------------------*/
+  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
+    /* When the HSE is used as system clock or clock source for PLL in these cases HSE will not disabled */
+    if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE) ||\
+      ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)))
+    {
+      if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
+      {
+        return HAL_ERROR;
+      }
+    }
+    else
+    {
+      /* Set the new HSE configuration ---------------------------------------*/
+      __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
+
+      /* Check the HSE State */
+      if((RCC_OscInitStruct->HSEState) != RCC_HSE_OFF)
+      {
+        /* Get Start Tick */
+        tickstart = HAL_GetTick();
+
+        /* Wait till HSE is ready */
+        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
+        {
+          if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
+          {
+            return HAL_TIMEOUT;
+          }
+        }
+      }
+      else
+      {
+        /* Get Start Tick */
+        tickstart = HAL_GetTick();
+
+        /* Wait till HSE is bypassed or disabled */
+        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
+        {
+          if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
+          {
+            return HAL_TIMEOUT;
+          }
+        }
+      }
+    }
+  }
+  /*----------------------------- HSI Configuration --------------------------*/
+  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
+    assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
+
+    /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
+    if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI) ||\
+      ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)))
+    {
+      /* When HSI is used as system clock it will not disabled */
+      if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
+      {
+        return HAL_ERROR;
+      }
+      /* Otherwise, just the calibration is allowed */
+      else
+      {
+        /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
+        __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
+      }
+    }
+    else
+    {
+      /* Check the HSI State */
+      if((RCC_OscInitStruct->HSIState)!= RCC_HSI_OFF)
+      {
+        /* Enable the Internal High Speed oscillator (HSI). */
+        __HAL_RCC_HSI_ENABLE();
+
+        /* Get Start Tick*/
+        tickstart = HAL_GetTick();
+
+        /* Wait till HSI is ready */
+        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
+        {
+          if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
+          {
+            return HAL_TIMEOUT;
+          }
+        }
+
+        /* Adjusts the Internal High Speed oscillator (HSI) calibration value. */
+        __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
+      }
+      else
+      {
+        /* Disable the Internal High Speed oscillator (HSI). */
+        __HAL_RCC_HSI_DISABLE();
+
+        /* Get Start Tick*/
+        tickstart = HAL_GetTick();
+
+        /* Wait till HSI is ready */
+        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
+        {
+          if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
+          {
+            return HAL_TIMEOUT;
+          }
+        }
+      }
+    }
+  }
+  /*------------------------------ LSI Configuration -------------------------*/
+  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
+
+    /* Check the LSI State */
+    if((RCC_OscInitStruct->LSIState)!= RCC_LSI_OFF)
+    {
+      /* Enable the Internal Low Speed oscillator (LSI). */
+      __HAL_RCC_LSI_ENABLE();
+
+      /* Get Start Tick*/
+      tickstart = HAL_GetTick();
+
+      /* Wait till LSI is ready */
+      while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
+      {
+        if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
+        {
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+    else
+    {
+      /* Disable the Internal Low Speed oscillator (LSI). */
+      __HAL_RCC_LSI_DISABLE();
+
+      /* Get Start Tick */
+      tickstart = HAL_GetTick();
+
+      /* Wait till LSI is ready */
+      while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
+      {
+        if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
+        {
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+  }
+  /*------------------------------ LSE Configuration -------------------------*/
+  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
+  {
+    FlagStatus       pwrclkchanged = RESET;
+
+    /* Check the parameters */
+    assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
+
+    /* Update LSE configuration in Backup Domain control register    */
+    /* Requires to enable write access to Backup Domain of necessary */
+    if(__HAL_RCC_PWR_IS_CLK_DISABLED())
+    {
+      __HAL_RCC_PWR_CLK_ENABLE();
+      pwrclkchanged = SET;
+    }
+
+    if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
+    {
+      /* Enable write access to Backup domain */
+      SET_BIT(PWR->CR, PWR_CR_DBP);
+
+      /* Wait for Backup domain Write protection disable */
+      tickstart = HAL_GetTick();
+
+      while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
+      {
+        if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
+        {
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+
+    /* Set the new LSE configuration -----------------------------------------*/
+    __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
+    /* Check the LSE State */
+    if((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF)
+    {
+      /* Get Start Tick*/
+      tickstart = HAL_GetTick();
+
+      /* Wait till LSE is ready */
+      while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
+      {
+        if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
+        {
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+    else
+    {
+      /* Get Start Tick */
+      tickstart = HAL_GetTick();
+
+      /* Wait till LSE is ready */
+      while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
+      {
+        if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
+        {
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+
+    /* Restore clock configuration if changed */
+    if(pwrclkchanged == SET)
+    {
+      __HAL_RCC_PWR_CLK_DISABLE();
+    }
+  }
+  /*-------------------------------- PLL Configuration -----------------------*/
+  /* Check the parameters */
+  assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
+  if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
+  {
+    /* Check if the PLL is used as system clock or not */
+    if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL)
+    {
+      if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
+      {
+        /* Check the parameters */
+        assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource));
+        assert_param(IS_RCC_PLLM_VALUE(RCC_OscInitStruct->PLL.PLLM));
+        assert_param(IS_RCC_PLLN_VALUE(RCC_OscInitStruct->PLL.PLLN));
+        assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP));
+        assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ));
+
+        /* Disable the main PLL. */
+        __HAL_RCC_PLL_DISABLE();
+
+        /* Get Start Tick */
+        tickstart = HAL_GetTick();
+
+        /* Wait till PLL is ready */
+        while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
+        {
+          if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
+          {
+            return HAL_TIMEOUT;
+          }
+        }
+
+        /* Configure the main PLL clock source, multiplication and division factors. */
+        WRITE_REG(RCC->PLLCFGR, (RCC_OscInitStruct->PLL.PLLSource                                            | \
+                                 RCC_OscInitStruct->PLL.PLLM                                                 | \
+                                 (RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PLLN_Pos)             | \
+                                 (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U) << RCC_PLLCFGR_PLLP_Pos) | \
+                                 (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos)));
+        /* Enable the main PLL. */
+        __HAL_RCC_PLL_ENABLE();
+
+        /* Get Start Tick */
+        tickstart = HAL_GetTick();
+
+        /* Wait till PLL is ready */
+        while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
+        {
+          if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
+          {
+            return HAL_TIMEOUT;
+          }
+        }
+      }
+      else
+      {
+        /* Disable the main PLL. */
+        __HAL_RCC_PLL_DISABLE();
+
+        /* Get Start Tick */
+        tickstart = HAL_GetTick();
+
+        /* Wait till PLL is ready */
+        while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
+        {
+          if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
+          {
+            return HAL_TIMEOUT;
+          }
+        }
+      }
+    }
+    else
+    {
+      /* Check if there is a request to disable the PLL used as System clock source */
+      if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF)
+      {
+        return HAL_ERROR;
+      }
+      else
+      {
+        /* Do not return HAL_ERROR if request repeats the current configuration */
+        pll_config = RCC->PLLCFGR;
+#if defined (RCC_PLLCFGR_PLLR)
+        if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) ||
+            (READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
+            (READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != (RCC_OscInitStruct->PLL.PLLM) << RCC_PLLCFGR_PLLM_Pos) ||
+            (READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN) << RCC_PLLCFGR_PLLN_Pos) ||
+            (READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U)) << RCC_PLLCFGR_PLLP_Pos) ||
+            (READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos)) ||
+            (READ_BIT(pll_config, RCC_PLLCFGR_PLLR) != (RCC_OscInitStruct->PLL.PLLR << RCC_PLLCFGR_PLLR_Pos)))
+#else
+        if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) ||
+            (READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
+            (READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != (RCC_OscInitStruct->PLL.PLLM) << RCC_PLLCFGR_PLLM_Pos) ||
+            (READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN) << RCC_PLLCFGR_PLLN_Pos) ||
+            (READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U)) << RCC_PLLCFGR_PLLP_Pos) ||
+            (READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos)))
+#endif
+        {
+          return HAL_ERROR;
+        }
+      }
+    }
+  }
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the CPU, AHB and APB busses clocks according to the specified
+  *         parameters in the RCC_ClkInitStruct.
+  * @param  RCC_ClkInitStruct pointer to an RCC_OscInitTypeDef structure that
+  *         contains the configuration information for the RCC peripheral.
+  * @param  FLatency FLASH Latency, this parameter depend on device selected
+  *
+  * @note   The SystemCoreClock CMSIS variable is used to store System Clock Frequency
+  *         and updated by HAL_RCC_GetHCLKFreq() function called within this function
+  *
+  * @note   The HSI is used (enabled by hardware) as system clock source after
+  *         startup from Reset, wake-up from STOP and STANDBY mode, or in case
+  *         of failure of the HSE used directly or indirectly as system clock
+  *         (if the Clock Security System CSS is enabled).
+  *
+  * @note   A switch from one clock source to another occurs only if the target
+  *         clock source is ready (clock stable after startup delay or PLL locked).
+  *         If a clock source which is not yet ready is selected, the switch will
+  *         occur when the clock source will be ready.
+  *
+  * @note   Depending on the device voltage range, the software has to set correctly
+  *         HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency
+  *         (for more details refer to section above "Initialization/de-initialization functions")
+  * @retval None
+  */
+HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef  *RCC_ClkInitStruct, uint32_t FLatency)
+{
+  uint32_t tickstart;
+
+  /* Check Null pointer */
+  if(RCC_ClkInitStruct == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_RCC_CLOCKTYPE(RCC_ClkInitStruct->ClockType));
+  assert_param(IS_FLASH_LATENCY(FLatency));
+
+  /* To correctly read data from FLASH memory, the number of wait states (LATENCY)
+    must be correctly programmed according to the frequency of the CPU clock
+    (HCLK) and the supply voltage of the device. */
+
+  /* Increasing the number of wait states because of higher CPU frequency */
+  if(FLatency > __HAL_FLASH_GET_LATENCY())
+  {
+    /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
+    __HAL_FLASH_SET_LATENCY(FLatency);
+
+    /* Check that the new number of wait states is taken into account to access the Flash
+    memory by reading the FLASH_ACR register */
+    if(__HAL_FLASH_GET_LATENCY() != FLatency)
+    {
+      return HAL_ERROR;
+    }
+  }
+
+  /*-------------------------- HCLK Configuration --------------------------*/
+  if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
+  {
+    /* Set the highest APBx dividers in order to ensure that we do not go through
+       a non-spec phase whatever we decrease or increase HCLK. */
+    if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
+    {
+      MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16);
+    }
+
+    if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
+    {
+      MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, (RCC_HCLK_DIV16 << 3));
+    }
+
+    assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
+    MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
+  }
+
+  /*------------------------- SYSCLK Configuration ---------------------------*/
+  if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
+  {
+    assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
+
+    /* HSE is selected as System Clock Source */
+    if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
+    {
+      /* Check the HSE ready flag */
+      if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
+      {
+        return HAL_ERROR;
+      }
+    }
+    /* PLL is selected as System Clock Source */
+    else if((RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)   ||
+            (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLRCLK))
+    {
+      /* Check the PLL ready flag */
+      if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
+      {
+        return HAL_ERROR;
+      }
+    }
+    /* HSI is selected as System Clock Source */
+    else
+    {
+      /* Check the HSI ready flag */
+      if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
+      {
+        return HAL_ERROR;
+      }
+    }
+
+    __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);
+
+    /* Get Start Tick */
+    tickstart = HAL_GetTick();
+
+    while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
+    {
+      if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
+      {
+        return HAL_TIMEOUT;
+      }
+    }
+  }
+
+  /* Decreasing the number of wait states because of lower CPU frequency */
+  if(FLatency < __HAL_FLASH_GET_LATENCY())
+  {
+     /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
+    __HAL_FLASH_SET_LATENCY(FLatency);
+
+    /* Check that the new number of wait states is taken into account to access the Flash
+    memory by reading the FLASH_ACR register */
+    if(__HAL_FLASH_GET_LATENCY() != FLatency)
+    {
+      return HAL_ERROR;
+    }
+  }
+
+  /*-------------------------- PCLK1 Configuration ---------------------------*/
+  if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
+  {
+    assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
+    MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
+  }
+
+  /*-------------------------- PCLK2 Configuration ---------------------------*/
+  if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
+  {
+    assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));
+    MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3U));
+  }
+
+  /* Update the SystemCoreClock global variable */
+  SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> RCC_CFGR_HPRE_Pos];
+
+  /* Configure the source of time base considering new system clocks settings */
+  HAL_InitTick (uwTickPrio);
+
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_Exported_Functions_Group2 Peripheral Control functions
+ *  @brief   RCC clocks control functions
+ *
+@verbatim
+ ===============================================================================
+                      ##### Peripheral Control functions #####
+ ===============================================================================
+    [..]
+    This subsection provides a set of functions allowing to control the RCC Clocks
+    frequencies.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Selects the clock source to output on MCO1 pin(PA8) or on MCO2 pin(PC9).
+  * @note   PA8/PC9 should be configured in alternate function mode.
+  * @param  RCC_MCOx specifies the output direction for the clock source.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_MCO1: Clock source to output on MCO1 pin(PA8).
+  *            @arg RCC_MCO2: Clock source to output on MCO2 pin(PC9).
+  * @param  RCC_MCOSource specifies the clock source to output.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_MCO1SOURCE_HSI: HSI clock selected as MCO1 source
+  *            @arg RCC_MCO1SOURCE_LSE: LSE clock selected as MCO1 source
+  *            @arg RCC_MCO1SOURCE_HSE: HSE clock selected as MCO1 source
+  *            @arg RCC_MCO1SOURCE_PLLCLK: main PLL clock selected as MCO1 source
+  *            @arg RCC_MCO2SOURCE_SYSCLK: System clock (SYSCLK) selected as MCO2 source
+  *            @arg RCC_MCO2SOURCE_PLLI2SCLK: PLLI2S clock selected as MCO2 source, available for all STM32F4 devices except STM32F410xx
+  *            @arg RCC_MCO2SOURCE_I2SCLK: I2SCLK clock selected as MCO2 source, available only for STM32F410Rx devices
+  *            @arg RCC_MCO2SOURCE_HSE: HSE clock selected as MCO2 source
+  *            @arg RCC_MCO2SOURCE_PLLCLK: main PLL clock selected as MCO2 source
+  * @param  RCC_MCODiv specifies the MCOx prescaler.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_MCODIV_1: no division applied to MCOx clock
+  *            @arg RCC_MCODIV_2: division by 2 applied to MCOx clock
+  *            @arg RCC_MCODIV_3: division by 3 applied to MCOx clock
+  *            @arg RCC_MCODIV_4: division by 4 applied to MCOx clock
+  *            @arg RCC_MCODIV_5: division by 5 applied to MCOx clock
+  * @note  For STM32F410Rx devices to output I2SCLK clock on MCO2 you should have
+  *        at last one of the SPI clocks enabled (SPI1, SPI2 or SPI5).
+  * @retval None
+  */
+void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv)
+{
+  GPIO_InitTypeDef GPIO_InitStruct;
+  /* Check the parameters */
+  assert_param(IS_RCC_MCO(RCC_MCOx));
+  assert_param(IS_RCC_MCODIV(RCC_MCODiv));
+  /* RCC_MCO1 */
+  if(RCC_MCOx == RCC_MCO1)
+  {
+    assert_param(IS_RCC_MCO1SOURCE(RCC_MCOSource));
+
+    /* MCO1 Clock Enable */
+    __MCO1_CLK_ENABLE();
+
+    /* Configure the MCO1 pin in alternate function mode */
+    GPIO_InitStruct.Pin = MCO1_PIN;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+    GPIO_InitStruct.Alternate = GPIO_AF0_MCO;
+    HAL_GPIO_Init(MCO1_GPIO_PORT, &GPIO_InitStruct);
+
+    /* Mask MCO1 and MCO1PRE[2:0] bits then Select MCO1 clock source and prescaler */
+    MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO1 | RCC_CFGR_MCO1PRE), (RCC_MCOSource | RCC_MCODiv));
+
+   /* This RCC MCO1 enable feature is available only on STM32F410xx devices */
+#if defined(RCC_CFGR_MCO1EN)
+    __HAL_RCC_MCO1_ENABLE();
+#endif /* RCC_CFGR_MCO1EN */
+  }
+#if defined(RCC_CFGR_MCO2)
+  else
+  {
+    assert_param(IS_RCC_MCO2SOURCE(RCC_MCOSource));
+
+    /* MCO2 Clock Enable */
+    __MCO2_CLK_ENABLE();
+
+    /* Configure the MCO2 pin in alternate function mode */
+    GPIO_InitStruct.Pin = MCO2_PIN;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+    GPIO_InitStruct.Alternate = GPIO_AF0_MCO;
+    HAL_GPIO_Init(MCO2_GPIO_PORT, &GPIO_InitStruct);
+
+    /* Mask MCO2 and MCO2PRE[2:0] bits then Select MCO2 clock source and prescaler */
+    MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO2 | RCC_CFGR_MCO2PRE), (RCC_MCOSource | (RCC_MCODiv << 3U)));
+
+   /* This RCC MCO2 enable feature is available only on STM32F410Rx devices */
+#if defined(RCC_CFGR_MCO2EN)
+    __HAL_RCC_MCO2_ENABLE();
+#endif /* RCC_CFGR_MCO2EN */
+  }
+#endif /* RCC_CFGR_MCO2 */
+}
+
+/**
+  * @brief  Enables the Clock Security System.
+  * @note   If a failure is detected on the HSE oscillator clock, this oscillator
+  *         is automatically disabled and an interrupt is generated to inform the
+  *         software about the failure (Clock Security System Interrupt, CSSI),
+  *         allowing the MCU to perform rescue operations. The CSSI is linked to
+  *         the Cortex-M4 NMI (Non-Maskable Interrupt) exception vector.
+  * @retval None
+  */
+void HAL_RCC_EnableCSS(void)
+{
+  *(__IO uint32_t *) RCC_CR_CSSON_BB = (uint32_t)ENABLE;
+}
+
+/**
+  * @brief  Disables the Clock Security System.
+  * @retval None
+  */
+void HAL_RCC_DisableCSS(void)
+{
+  *(__IO uint32_t *) RCC_CR_CSSON_BB = (uint32_t)DISABLE;
+}
+
+/**
+  * @brief  Returns the SYSCLK frequency
+  *
+  * @note   The system frequency computed by this function is not the real
+  *         frequency in the chip. It is calculated based on the predefined
+  *         constant and the selected clock source:
+  * @note     If SYSCLK source is HSI, function returns values based on HSI_VALUE(*)
+  * @note     If SYSCLK source is HSE, function returns values based on HSE_VALUE(**)
+  * @note     If SYSCLK source is PLL, function returns values based on HSE_VALUE(**)
+  *           or HSI_VALUE(*) multiplied/divided by the PLL factors.
+  * @note     (*) HSI_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value
+  *               16 MHz) but the real value may vary depending on the variations
+  *               in voltage and temperature.
+  * @note     (**) HSE_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value
+  *                25 MHz), user has to ensure that HSE_VALUE is same as the real
+  *                frequency of the crystal used. Otherwise, this function may
+  *                have wrong result.
+  *
+  * @note   The result of this function could be not correct when using fractional
+  *         value for HSE crystal.
+  *
+  * @note   This function can be used by the user application to compute the
+  *         baudrate for the communication peripherals or configure other parameters.
+  *
+  * @note   Each time SYSCLK changes, this function must be called to update the
+  *         right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.
+  *
+  *
+  * @retval SYSCLK frequency
+  */
+__weak uint32_t HAL_RCC_GetSysClockFreq(void)
+{
+  uint32_t pllm = 0U, pllvco = 0U, pllp = 0U;
+  uint32_t sysclockfreq = 0U;
+
+  /* Get SYSCLK source -------------------------------------------------------*/
+  switch (RCC->CFGR & RCC_CFGR_SWS)
+  {
+    case RCC_CFGR_SWS_HSI:  /* HSI used as system clock source */
+    {
+      sysclockfreq = HSI_VALUE;
+       break;
+    }
+    case RCC_CFGR_SWS_HSE:  /* HSE used as system clock  source */
+    {
+      sysclockfreq = HSE_VALUE;
+      break;
+    }
+    case RCC_CFGR_SWS_PLL:  /* PLL used as system clock  source */
+    {
+      /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
+      SYSCLK = PLL_VCO / PLLP */
+      pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
+      if(__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_HSI)
+      {
+        /* HSE used as PLL clock source */
+        pllvco = (uint32_t) ((((uint64_t) HSE_VALUE * ((uint64_t) ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm);
+      }
+      else
+      {
+        /* HSI used as PLL clock source */
+        pllvco = (uint32_t) ((((uint64_t) HSI_VALUE * ((uint64_t) ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm);
+      }
+      pllp = ((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >> RCC_PLLCFGR_PLLP_Pos) + 1U) *2U);
+
+      sysclockfreq = pllvco/pllp;
+      break;
+    }
+    default:
+    {
+      sysclockfreq = HSI_VALUE;
+      break;
+    }
+  }
+  return sysclockfreq;
+}
+
+/**
+  * @brief  Returns the HCLK frequency
+  * @note   Each time HCLK changes, this function must be called to update the
+  *         right HCLK value. Otherwise, any configuration based on this function will be incorrect.
+  *
+  * @note   The SystemCoreClock CMSIS variable is used to store System Clock Frequency
+  *         and updated within this function
+  * @retval HCLK frequency
+  */
+uint32_t HAL_RCC_GetHCLKFreq(void)
+{
+  return SystemCoreClock;
+}
+
+/**
+  * @brief  Returns the PCLK1 frequency
+  * @note   Each time PCLK1 changes, this function must be called to update the
+  *         right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
+  * @retval PCLK1 frequency
+  */
+uint32_t HAL_RCC_GetPCLK1Freq(void)
+{
+  /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
+  return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1)>> RCC_CFGR_PPRE1_Pos]);
+}
+
+/**
+  * @brief  Returns the PCLK2 frequency
+  * @note   Each time PCLK2 changes, this function must be called to update the
+  *         right PCLK2 value. Otherwise, any configuration based on this function will be incorrect.
+  * @retval PCLK2 frequency
+  */
+uint32_t HAL_RCC_GetPCLK2Freq(void)
+{
+  /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/
+  return (HAL_RCC_GetHCLKFreq()>> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2)>> RCC_CFGR_PPRE2_Pos]);
+}
+
+/**
+  * @brief  Configures the RCC_OscInitStruct according to the internal
+  * RCC configuration registers.
+  * @param  RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that
+  * will be configured.
+  * @retval None
+  */
+__weak void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct)
+{
+  /* Set all possible values for the Oscillator type parameter ---------------*/
+  RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI;
+
+  /* Get the HSE configuration -----------------------------------------------*/
+  if((RCC->CR &RCC_CR_HSEBYP) == RCC_CR_HSEBYP)
+  {
+    RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS;
+  }
+  else if((RCC->CR &RCC_CR_HSEON) == RCC_CR_HSEON)
+  {
+    RCC_OscInitStruct->HSEState = RCC_HSE_ON;
+  }
+  else
+  {
+    RCC_OscInitStruct->HSEState = RCC_HSE_OFF;
+  }
+
+  /* Get the HSI configuration -----------------------------------------------*/
+  if((RCC->CR &RCC_CR_HSION) == RCC_CR_HSION)
+  {
+    RCC_OscInitStruct->HSIState = RCC_HSI_ON;
+  }
+  else
+  {
+    RCC_OscInitStruct->HSIState = RCC_HSI_OFF;
+  }
+
+  RCC_OscInitStruct->HSICalibrationValue = (uint32_t)((RCC->CR &RCC_CR_HSITRIM) >> RCC_CR_HSITRIM_Pos);
+
+  /* Get the LSE configuration -----------------------------------------------*/
+  if((RCC->BDCR &RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP)
+  {
+    RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS;
+  }
+  else if((RCC->BDCR &RCC_BDCR_LSEON) == RCC_BDCR_LSEON)
+  {
+    RCC_OscInitStruct->LSEState = RCC_LSE_ON;
+  }
+  else
+  {
+    RCC_OscInitStruct->LSEState = RCC_LSE_OFF;
+  }
+
+  /* Get the LSI configuration -----------------------------------------------*/
+  if((RCC->CSR &RCC_CSR_LSION) == RCC_CSR_LSION)
+  {
+    RCC_OscInitStruct->LSIState = RCC_LSI_ON;
+  }
+  else
+  {
+    RCC_OscInitStruct->LSIState = RCC_LSI_OFF;
+  }
+
+  /* Get the PLL configuration -----------------------------------------------*/
+  if((RCC->CR &RCC_CR_PLLON) == RCC_CR_PLLON)
+  {
+    RCC_OscInitStruct->PLL.PLLState = RCC_PLL_ON;
+  }
+  else
+  {
+    RCC_OscInitStruct->PLL.PLLState = RCC_PLL_OFF;
+  }
+  RCC_OscInitStruct->PLL.PLLSource = (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
+  RCC_OscInitStruct->PLL.PLLM = (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM);
+  RCC_OscInitStruct->PLL.PLLN = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
+  RCC_OscInitStruct->PLL.PLLP = (uint32_t)((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) + RCC_PLLCFGR_PLLP_0) << 1U) >> RCC_PLLCFGR_PLLP_Pos);
+  RCC_OscInitStruct->PLL.PLLQ = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLQ) >> RCC_PLLCFGR_PLLQ_Pos);
+}
+
+/**
+  * @brief  Configures the RCC_ClkInitStruct according to the internal
+  * RCC configuration registers.
+  * @param  RCC_ClkInitStruct pointer to an RCC_ClkInitTypeDef structure that
+  * will be configured.
+  * @param  pFLatency Pointer on the Flash Latency.
+  * @retval None
+  */
+void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef  *RCC_ClkInitStruct, uint32_t *pFLatency)
+{
+  /* Set all possible values for the Clock type parameter --------------------*/
+  RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
+
+  /* Get the SYSCLK configuration --------------------------------------------*/
+  RCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR & RCC_CFGR_SW);
+
+  /* Get the HCLK configuration ----------------------------------------------*/
+  RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_HPRE);
+
+  /* Get the APB1 configuration ----------------------------------------------*/
+  RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_PPRE1);
+
+  /* Get the APB2 configuration ----------------------------------------------*/
+  RCC_ClkInitStruct->APB2CLKDivider = (uint32_t)((RCC->CFGR & RCC_CFGR_PPRE2) >> 3U);
+
+  /* Get the Flash Wait State (Latency) configuration ------------------------*/
+  *pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY);
+}
+
+/**
+  * @brief This function handles the RCC CSS interrupt request.
+  * @note This API should be called under the NMI_Handler().
+  * @retval None
+  */
+void HAL_RCC_NMI_IRQHandler(void)
+{
+  /* Check RCC CSSF flag  */
+  if(__HAL_RCC_GET_IT(RCC_IT_CSS))
+  {
+    /* RCC Clock Security System interrupt user callback */
+    HAL_RCC_CSSCallback();
+
+    /* Clear RCC CSS pending bit */
+    __HAL_RCC_CLEAR_IT(RCC_IT_CSS);
+  }
+}
+
+/**
+  * @brief  RCC Clock Security System interrupt callback
+  * @retval None
+  */
+__weak void HAL_RCC_CSSCallback(void)
+{
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_RCC_CSSCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* HAL_RCC_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
diff --git a/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c
new file mode 100644
index 0000000..dd89656
--- /dev/null
+++ b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c
@@ -0,0 +1,3784 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hal_rcc_ex.c
+  * @author  MCD Application Team
+  * @brief   Extension RCC HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities RCC extension peripheral:
+  *           + Extended Peripheral Control functions
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file in
+  * the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup RCCEx RCCEx
+  * @brief RCCEx HAL module driver
+  * @{
+  */
+
+#ifdef HAL_RCC_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @addtogroup RCCEx_Private_Constants
+  * @{
+  */
+/**
+  * @}
+  */
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup RCCEx_Exported_Functions RCCEx Exported Functions
+  *  @{
+  */
+
+/** @defgroup RCCEx_Exported_Functions_Group1 Extended Peripheral Control functions
+ *  @brief  Extended Peripheral Control functions
+ *
+@verbatim
+ ===============================================================================
+                ##### Extended Peripheral Control functions  #####
+ ===============================================================================
+    [..]
+    This subsection provides a set of functions allowing to control the RCC Clocks
+    frequencies.
+    [..]
+    (@) Important note: Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to
+        select the RTC clock source; in this case the Backup domain will be reset in
+        order to modify the RTC Clock source, as consequence RTC registers (including
+        the backup registers) and RCC_BDCR register are set to their reset values.
+
+@endverbatim
+  * @{
+  */
+
+#if defined(STM32F446xx)
+/**
+  * @brief  Initializes the RCC extended peripherals clocks according to the specified
+  *         parameters in the RCC_PeriphCLKInitTypeDef.
+  * @param  PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that
+  *         contains the configuration information for the Extended Peripherals
+  *         clocks(I2S, SAI, LTDC RTC and TIM).
+  *
+  * @note   Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select
+  *         the RTC clock source; in this case the Backup domain will be reset in
+  *         order to modify the RTC Clock source, as consequence RTC registers (including
+  *         the backup registers) and RCC_BDCR register are set to their reset values.
+  *
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit)
+{
+  uint32_t tickstart = 0U;
+  uint32_t tmpreg1 = 0U;
+  uint32_t plli2sp = 0U;
+  uint32_t plli2sq = 0U;
+  uint32_t plli2sr = 0U;
+  uint32_t pllsaip = 0U;
+  uint32_t pllsaiq = 0U;
+  uint32_t plli2sused = 0U;
+  uint32_t pllsaiused = 0U;
+
+  /* Check the peripheral clock selection parameters */
+  assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
+
+  /*------------------------ I2S APB1 configuration --------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB1) == (RCC_PERIPHCLK_I2S_APB1))
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_I2SAPB1CLKSOURCE(PeriphClkInit->I2sApb1ClockSelection));
+
+    /* Configure I2S Clock source */
+    __HAL_RCC_I2S_APB1_CONFIG(PeriphClkInit->I2sApb1ClockSelection);
+    /* Enable the PLLI2S when it's used as clock source for I2S */
+    if(PeriphClkInit->I2sApb1ClockSelection == RCC_I2SAPB1CLKSOURCE_PLLI2S)
+    {
+      plli2sused = 1U;
+    }
+  }
+  /*--------------------------------------------------------------------------*/
+
+  /*---------------------------- I2S APB2 configuration ----------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB2) == (RCC_PERIPHCLK_I2S_APB2))
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_I2SAPB2CLKSOURCE(PeriphClkInit->I2sApb2ClockSelection));
+
+    /* Configure I2S Clock source */
+    __HAL_RCC_I2S_APB2_CONFIG(PeriphClkInit->I2sApb2ClockSelection);
+    /* Enable the PLLI2S when it's used as clock source for I2S */
+    if(PeriphClkInit->I2sApb2ClockSelection == RCC_I2SAPB2CLKSOURCE_PLLI2S)
+    {
+      plli2sused = 1U;
+    }
+  }
+  /*--------------------------------------------------------------------------*/
+
+  /*--------------------------- SAI1 configuration ---------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == (RCC_PERIPHCLK_SAI1))
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_SAI1CLKSOURCE(PeriphClkInit->Sai1ClockSelection));
+
+    /* Configure SAI1 Clock source */
+    __HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection);
+    /* Enable the PLLI2S when it's used as clock source for SAI */
+    if(PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S)
+    {
+      plli2sused = 1U;
+    }
+    /* Enable the PLLSAI when it's used as clock source for SAI */
+    if(PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI)
+    {
+      pllsaiused = 1U;
+    }
+  }
+  /*--------------------------------------------------------------------------*/
+
+  /*-------------------------- SAI2 configuration ----------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == (RCC_PERIPHCLK_SAI2))
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_SAI2CLKSOURCE(PeriphClkInit->Sai2ClockSelection));
+
+    /* Configure SAI2 Clock source */
+    __HAL_RCC_SAI2_CONFIG(PeriphClkInit->Sai2ClockSelection);
+
+    /* Enable the PLLI2S when it's used as clock source for SAI */
+    if(PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S)
+    {
+      plli2sused = 1U;
+    }
+    /* Enable the PLLSAI when it's used as clock source for SAI */
+    if(PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI)
+    {
+      pllsaiused = 1U;
+    }
+  }
+  /*--------------------------------------------------------------------------*/
+
+  /*----------------------------- RTC configuration --------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC))
+  {
+    /* Check for RTC Parameters used to output RTCCLK */
+    assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
+
+    /* Enable Power Clock*/
+    __HAL_RCC_PWR_CLK_ENABLE();
+
+    /* Enable write access to Backup domain */
+    PWR->CR |= PWR_CR_DBP;
+
+    /* Get tick */
+    tickstart = HAL_GetTick();
+
+    while((PWR->CR & PWR_CR_DBP) == RESET)
+    {
+      if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE)
+      {
+        return HAL_TIMEOUT;
+      }
+    }
+    /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */
+    tmpreg1 = (RCC->BDCR & RCC_BDCR_RTCSEL);
+    if((tmpreg1 != 0x00000000U) && ((tmpreg1) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)))
+    {
+      /* Store the content of BDCR register before the reset of Backup Domain */
+      tmpreg1 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
+      /* RTC Clock selection can be changed only if the Backup Domain is reset */
+      __HAL_RCC_BACKUPRESET_FORCE();
+      __HAL_RCC_BACKUPRESET_RELEASE();
+      /* Restore the Content of BDCR register */
+      RCC->BDCR = tmpreg1;
+
+      /* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */
+      if(HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSEON))
+      {
+        /* Get tick */
+        tickstart = HAL_GetTick();
+
+        /* Wait till LSE is ready */
+        while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
+        {
+          if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
+          {
+            return HAL_TIMEOUT;
+          }
+        }
+      }
+    }
+    __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
+  }
+  /*--------------------------------------------------------------------------*/
+
+  /*---------------------------- TIM configuration ---------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM))
+  {
+    /* Configure Timer Prescaler */
+    __HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection);
+  }
+  /*--------------------------------------------------------------------------*/
+
+  /*---------------------------- FMPI2C1 Configuration -----------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FMPI2C1) == RCC_PERIPHCLK_FMPI2C1)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_FMPI2C1CLKSOURCE(PeriphClkInit->Fmpi2c1ClockSelection));
+
+    /* Configure the FMPI2C1 clock source */
+    __HAL_RCC_FMPI2C1_CONFIG(PeriphClkInit->Fmpi2c1ClockSelection);
+  }
+  /*--------------------------------------------------------------------------*/
+
+  /*------------------------------ CEC Configuration -------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_CECCLKSOURCE(PeriphClkInit->CecClockSelection));
+
+    /* Configure the CEC clock source */
+    __HAL_RCC_CEC_CONFIG(PeriphClkInit->CecClockSelection);
+  }
+  /*--------------------------------------------------------------------------*/
+
+  /*----------------------------- CLK48 Configuration ------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_CLK48CLKSOURCE(PeriphClkInit->Clk48ClockSelection));
+
+    /* Configure the CLK48 clock source */
+    __HAL_RCC_CLK48_CONFIG(PeriphClkInit->Clk48ClockSelection);
+
+    /* Enable the PLLSAI when it's used as clock source for CLK48 */
+    if(PeriphClkInit->Clk48ClockSelection == RCC_CLK48CLKSOURCE_PLLSAIP)
+    {
+      pllsaiused = 1U;
+    }
+  }
+  /*--------------------------------------------------------------------------*/
+
+  /*----------------------------- SDIO Configuration -------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDIO) == RCC_PERIPHCLK_SDIO)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_SDIOCLKSOURCE(PeriphClkInit->SdioClockSelection));
+
+    /* Configure the SDIO clock source */
+    __HAL_RCC_SDIO_CONFIG(PeriphClkInit->SdioClockSelection);
+  }
+  /*--------------------------------------------------------------------------*/
+
+  /*------------------------------ SPDIFRX Configuration ---------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_SPDIFRXCLKSOURCE(PeriphClkInit->SpdifClockSelection));
+
+    /* Configure the SPDIFRX clock source */
+    __HAL_RCC_SPDIFRX_CONFIG(PeriphClkInit->SpdifClockSelection);
+    /* Enable the PLLI2S when it's used as clock source for SPDIFRX */
+    if(PeriphClkInit->SpdifClockSelection == RCC_SPDIFRXCLKSOURCE_PLLI2SP)
+    {
+      plli2sused = 1U;
+    }
+  }
+  /*--------------------------------------------------------------------------*/
+
+  /*---------------------------- PLLI2S Configuration ------------------------*/
+  /* PLLI2S is configured when a peripheral will use it as source clock : SAI1, SAI2, I2S on APB1,
+     I2S on APB2 or SPDIFRX */
+  if((plli2sused == 1U) || (PeriphClkInit->PeriphClockSelection == RCC_PERIPHCLK_PLLI2S))
+  {
+    /* Disable the PLLI2S */
+    __HAL_RCC_PLLI2S_DISABLE();
+    /* Get tick */
+    tickstart = HAL_GetTick();
+    /* Wait till PLLI2S is disabled */
+    while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY)  != RESET)
+    {
+      if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
+      {
+        /* return in case of Timeout detected */
+        return HAL_TIMEOUT;
+      }
+    }
+
+    /* check for common PLLI2S Parameters */
+    assert_param(IS_RCC_PLLI2SM_VALUE(PeriphClkInit->PLLI2S.PLLI2SM));
+    assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN));
+
+    /*------ In Case of PLLI2S is selected as source clock for I2S -----------*/
+    if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB1) == RCC_PERIPHCLK_I2S_APB1) && (PeriphClkInit->I2sApb1ClockSelection == RCC_I2SAPB1CLKSOURCE_PLLI2S)) ||
+       ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB2) == RCC_PERIPHCLK_I2S_APB2) && (PeriphClkInit->I2sApb2ClockSelection == RCC_I2SAPB2CLKSOURCE_PLLI2S)))
+    {
+      /* check for Parameters */
+      assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));
+
+      /* Read PLLI2SP/PLLI2SQ value from PLLI2SCFGR register (this value is not needed for I2S configuration) */
+      plli2sp = ((((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> RCC_PLLI2SCFGR_PLLI2SP_Pos) + 1U) << 1U);
+      plli2sq = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos);
+      /* Configure the PLLI2S division factors */
+      /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLI2SM) */
+      /* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */
+      __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN , plli2sp, plli2sq, PeriphClkInit->PLLI2S.PLLI2SR);
+    }
+
+    /*------- In Case of PLLI2S is selected as source clock for SAI ----------*/
+    if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S)) ||
+       ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S)))
+    {
+      /* Check for PLLI2S Parameters */
+      assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ));
+      /* Check for PLLI2S/DIVQ parameters */
+      assert_param(IS_RCC_PLLI2S_DIVQ_VALUE(PeriphClkInit->PLLI2SDivQ));
+
+      /* Read PLLI2SP/PLLI2SR value from PLLI2SCFGR register (this value is not needed for SAI configuration) */
+      plli2sp = ((((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> RCC_PLLI2SCFGR_PLLI2SP_Pos) + 1U) << 1U);
+      plli2sr = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos);
+      /* Configure the PLLI2S division factors */
+      /* PLLI2S_VCO Input  = PLL_SOURCE/PLLI2SM */
+      /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
+      /* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */
+      __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN , plli2sp, PeriphClkInit->PLLI2S.PLLI2SQ, plli2sr);
+
+      /* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */
+      __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLI2SDivQ);
+    }
+
+    /*------ In Case of PLLI2S is selected as source clock for SPDIFRX -------*/
+    if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) && (PeriphClkInit->SpdifClockSelection == RCC_SPDIFRXCLKSOURCE_PLLI2SP))
+    {
+      /* check for Parameters */
+      assert_param(IS_RCC_PLLI2SP_VALUE(PeriphClkInit->PLLI2S.PLLI2SP));
+      /* Read PLLI2SR value from PLLI2SCFGR register (this value is not need for SAI configuration) */
+      plli2sq = ((((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> RCC_PLLI2SCFGR_PLLI2SP_Pos) + 1U) << 1U);
+      plli2sr = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos);
+      /* Configure the PLLI2S division factors */
+      /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLI2SM) */
+      /* SPDIFRXCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SP */
+      __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SP, plli2sq, plli2sr);
+    }
+
+     /*----------------- In Case of PLLI2S is just selected  -----------------*/
+    if((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S)
+    {
+      /* Check for Parameters */
+      assert_param(IS_RCC_PLLI2SP_VALUE(PeriphClkInit->PLLI2S.PLLI2SP));
+      assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));
+      assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ));
+
+      /* Configure the PLLI2S division factors */
+      /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLI2SM) */
+      __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SP, PeriphClkInit->PLLI2S.PLLI2SQ, PeriphClkInit->PLLI2S.PLLI2SR);
+    }
+
+    /* Enable the PLLI2S */
+    __HAL_RCC_PLLI2S_ENABLE();
+    /* Get tick */
+    tickstart = HAL_GetTick();
+    /* Wait till PLLI2S is ready */
+    while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY)  == RESET)
+    {
+      if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
+      {
+        /* return in case of Timeout detected */
+        return HAL_TIMEOUT;
+      }
+    }
+  }
+  /*--------------------------------------------------------------------------*/
+
+  /*----------------------------- PLLSAI Configuration -----------------------*/
+  /* PLLSAI is configured when a peripheral will use it as source clock : SAI1, SAI2, CLK48 or SDIO */
+  if(pllsaiused == 1U)
+  {
+    /* Disable PLLSAI Clock */
+    __HAL_RCC_PLLSAI_DISABLE();
+    /* Get tick */
+    tickstart = HAL_GetTick();
+    /* Wait till PLLSAI is disabled */
+    while(__HAL_RCC_PLLSAI_GET_FLAG() != RESET)
+    {
+      if((HAL_GetTick() - tickstart ) > PLLSAI_TIMEOUT_VALUE)
+      {
+        /* return in case of Timeout detected */
+        return HAL_TIMEOUT;
+      }
+    }
+
+    /* Check the PLLSAI division factors */
+    assert_param(IS_RCC_PLLSAIM_VALUE(PeriphClkInit->PLLSAI.PLLSAIM));
+    assert_param(IS_RCC_PLLSAIN_VALUE(PeriphClkInit->PLLSAI.PLLSAIN));
+
+    /*------ In Case of PLLSAI is selected as source clock for SAI -----------*/
+    if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI)) ||
+       ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI)))
+    {
+      /* check for PLLSAIQ Parameter */
+      assert_param(IS_RCC_PLLSAIQ_VALUE(PeriphClkInit->PLLSAI.PLLSAIQ));
+      /* check for PLLSAI/DIVQ Parameter */
+      assert_param(IS_RCC_PLLSAI_DIVQ_VALUE(PeriphClkInit->PLLSAIDivQ));
+
+      /* Read PLLSAIP value from PLLSAICFGR register (this value is not needed for SAI configuration) */
+      pllsaip = ((((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> RCC_PLLSAICFGR_PLLSAIP_Pos) + 1U) << 1U);
+      /* PLLSAI_VCO Input  = PLL_SOURCE/PLLM */
+      /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
+      /* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */
+      __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIM, PeriphClkInit->PLLSAI.PLLSAIN , pllsaip, PeriphClkInit->PLLSAI.PLLSAIQ, 0U);
+
+      /* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */
+      __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLSAIDivQ);
+    }
+
+    /*------ In Case of PLLSAI is selected as source clock for CLK48 ---------*/
+    /* In Case of PLLI2S is selected as source clock for CLK48 */
+    if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) && (PeriphClkInit->Clk48ClockSelection == RCC_CLK48CLKSOURCE_PLLSAIP))
+    {
+      /* check for Parameters */
+      assert_param(IS_RCC_PLLSAIP_VALUE(PeriphClkInit->PLLSAI.PLLSAIP));
+      /* Read PLLSAIQ value from PLLI2SCFGR register (this value is not need for SAI configuration) */
+      pllsaiq = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos);
+      /* Configure the PLLSAI division factors */
+      /* PLLSAI_VCO = f(VCO clock) = f(PLLSAI clock input) * (PLLI2SN/PLLSAIM) */
+      /* 48CLK = f(PLLSAI clock output) = f(VCO clock) / PLLSAIP */
+      __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIM, PeriphClkInit->PLLSAI.PLLSAIN , PeriphClkInit->PLLSAI.PLLSAIP, pllsaiq, 0U);
+    }
+
+    /* Enable PLLSAI Clock */
+    __HAL_RCC_PLLSAI_ENABLE();
+    /* Get tick */
+    tickstart = HAL_GetTick();
+    /* Wait till PLLSAI is ready */
+    while(__HAL_RCC_PLLSAI_GET_FLAG() == RESET)
+    {
+      if((HAL_GetTick() - tickstart ) > PLLSAI_TIMEOUT_VALUE)
+      {
+        /* return in case of Timeout detected */
+        return HAL_TIMEOUT;
+      }
+    }
+  }
+  return HAL_OK;
+}
+
+/**
+  * @brief  Get the RCC_PeriphCLKInitTypeDef according to the internal
+  *         RCC configuration registers.
+  * @param  PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that
+  *         will be configured.
+  * @retval None
+  */
+void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit)
+{
+  uint32_t tempreg;
+
+  /* Set all possible values for the extended clock type parameter------------*/
+  PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_I2S_APB1 | RCC_PERIPHCLK_I2S_APB2 |\
+                                        RCC_PERIPHCLK_SAI1     | RCC_PERIPHCLK_SAI2     |\
+                                        RCC_PERIPHCLK_TIM      | RCC_PERIPHCLK_RTC      |\
+                                        RCC_PERIPHCLK_CEC      | RCC_PERIPHCLK_FMPI2C1  |\
+                                        RCC_PERIPHCLK_CLK48     | RCC_PERIPHCLK_SDIO     |\
+                                        RCC_PERIPHCLK_SPDIFRX;
+
+  /* Get the PLLI2S Clock configuration --------------------------------------*/
+  PeriphClkInit->PLLI2S.PLLI2SM = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM) >> RCC_PLLI2SCFGR_PLLI2SM_Pos);
+  PeriphClkInit->PLLI2S.PLLI2SN = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> RCC_PLLI2SCFGR_PLLI2SN_Pos);
+  PeriphClkInit->PLLI2S.PLLI2SP = (uint32_t)((((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> RCC_PLLI2SCFGR_PLLI2SP_Pos) + 1U) << 1U);
+  PeriphClkInit->PLLI2S.PLLI2SQ = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos);
+  PeriphClkInit->PLLI2S.PLLI2SR = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos);
+  /* Get the PLLSAI Clock configuration --------------------------------------*/
+  PeriphClkInit->PLLSAI.PLLSAIM = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIM) >> RCC_PLLSAICFGR_PLLSAIM_Pos);
+  PeriphClkInit->PLLSAI.PLLSAIN = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> RCC_PLLSAICFGR_PLLSAIN_Pos);
+  PeriphClkInit->PLLSAI.PLLSAIP = (uint32_t)((((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> RCC_PLLSAICFGR_PLLSAIP_Pos) + 1U) << 1U);
+  PeriphClkInit->PLLSAI.PLLSAIQ = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos);
+  /* Get the PLLSAI/PLLI2S division factors ----------------------------------*/
+  PeriphClkInit->PLLI2SDivQ = (uint32_t)((RCC->DCKCFGR & RCC_DCKCFGR_PLLI2SDIVQ) >> RCC_DCKCFGR_PLLI2SDIVQ_Pos);
+  PeriphClkInit->PLLSAIDivQ = (uint32_t)((RCC->DCKCFGR & RCC_DCKCFGR_PLLSAIDIVQ) >> RCC_DCKCFGR_PLLSAIDIVQ_Pos);
+
+  /* Get the SAI1 clock configuration ----------------------------------------*/
+  PeriphClkInit->Sai1ClockSelection = __HAL_RCC_GET_SAI1_SOURCE();
+
+  /* Get the SAI2 clock configuration ----------------------------------------*/
+  PeriphClkInit->Sai2ClockSelection = __HAL_RCC_GET_SAI2_SOURCE();
+
+  /* Get the I2S APB1 clock configuration ------------------------------------*/
+  PeriphClkInit->I2sApb1ClockSelection = __HAL_RCC_GET_I2S_APB1_SOURCE();
+
+  /* Get the I2S APB2 clock configuration ------------------------------------*/
+  PeriphClkInit->I2sApb2ClockSelection = __HAL_RCC_GET_I2S_APB2_SOURCE();
+
+  /* Get the RTC Clock configuration -----------------------------------------*/
+  tempreg = (RCC->CFGR & RCC_CFGR_RTCPRE);
+  PeriphClkInit->RTCClockSelection = (uint32_t)((tempreg) | (RCC->BDCR & RCC_BDCR_RTCSEL));
+
+  /* Get the CEC clock configuration -----------------------------------------*/
+  PeriphClkInit->CecClockSelection = __HAL_RCC_GET_CEC_SOURCE();
+
+  /* Get the FMPI2C1 clock configuration -------------------------------------*/
+  PeriphClkInit->Fmpi2c1ClockSelection = __HAL_RCC_GET_FMPI2C1_SOURCE();
+
+  /* Get the CLK48 clock configuration ----------------------------------------*/
+  PeriphClkInit->Clk48ClockSelection = __HAL_RCC_GET_CLK48_SOURCE();
+
+  /* Get the SDIO clock configuration ----------------------------------------*/
+  PeriphClkInit->SdioClockSelection = __HAL_RCC_GET_SDIO_SOURCE();
+
+  /* Get the SPDIFRX clock configuration -------------------------------------*/
+  PeriphClkInit->SpdifClockSelection = __HAL_RCC_GET_SPDIFRX_SOURCE();
+
+  /* Get the TIM Prescaler configuration -------------------------------------*/
+  if ((RCC->DCKCFGR & RCC_DCKCFGR_TIMPRE) == RESET)
+  {
+    PeriphClkInit->TIMPresSelection = RCC_TIMPRES_DESACTIVATED;
+  }
+  else
+  {
+    PeriphClkInit->TIMPresSelection = RCC_TIMPRES_ACTIVATED;
+  }
+}
+
+/**
+  * @brief  Return the peripheral clock frequency for a given peripheral(SAI..)
+  * @note   Return 0 if peripheral clock identifier not managed by this API
+  * @param  PeriphClk Peripheral clock identifier
+  *         This parameter can be one of the following values:
+  *            @arg RCC_PERIPHCLK_SAI1: SAI1 peripheral clock
+  *            @arg RCC_PERIPHCLK_SAI2: SAI2 peripheral clock
+  *            @arg RCC_PERIPHCLK_I2S_APB1: I2S APB1 peripheral clock
+  *            @arg RCC_PERIPHCLK_I2S_APB2: I2S APB2 peripheral clock
+  * @retval Frequency in KHz
+  */
+uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
+{
+  uint32_t tmpreg1 = 0U;
+  /* This variable used to store the SAI clock frequency (value in Hz) */
+  uint32_t frequency = 0U;
+  /* This variable used to store the VCO Input (value in Hz) */
+  uint32_t vcoinput = 0U;
+  /* This variable used to store the SAI clock source */
+  uint32_t saiclocksource = 0U;
+  uint32_t srcclk = 0U;
+  /* This variable used to store the VCO Output (value in Hz) */
+  uint32_t vcooutput = 0U;
+  switch (PeriphClk)
+  {
+  case RCC_PERIPHCLK_SAI1:
+  case RCC_PERIPHCLK_SAI2:
+    {
+      saiclocksource = RCC->DCKCFGR;
+      saiclocksource &= (RCC_DCKCFGR_SAI1SRC | RCC_DCKCFGR_SAI2SRC);
+      switch (saiclocksource)
+      {
+      case 0U: /* PLLSAI is the clock source for SAI*/
+        {
+          /* Configure the PLLSAI division factor */
+          /* PLLSAI_VCO Input  = PLL_SOURCE/PLLSAIM */
+          if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI)
+          {
+            /* In Case the PLL Source is HSI (Internal Clock) */
+            vcoinput = (HSI_VALUE / (uint32_t)(RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIM));
+          }
+          else
+          {
+            /* In Case the PLL Source is HSE (External Clock) */
+            vcoinput = ((HSE_VALUE / (uint32_t)(RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIM)));
+          }
+          /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
+          /* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */
+          tmpreg1 = (RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> 24U;
+          frequency = (vcoinput * ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> 6U))/(tmpreg1);
+
+          /* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */
+          tmpreg1 = (((RCC->DCKCFGR & RCC_DCKCFGR_PLLSAIDIVQ) >> 8U) + 1U);
+          frequency = frequency/(tmpreg1);
+          break;
+        }
+      case RCC_DCKCFGR_SAI1SRC_0: /* PLLI2S is the clock source for SAI*/
+      case RCC_DCKCFGR_SAI2SRC_0: /* PLLI2S is the clock source for SAI*/
+        {
+          /* Configure the PLLI2S division factor */
+          /* PLLI2S_VCO Input  = PLL_SOURCE/PLLI2SM */
+          if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI)
+          {
+            /* In Case the PLL Source is HSI (Internal Clock) */
+            vcoinput = (HSI_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM));
+          }
+          else
+          {
+            /* In Case the PLL Source is HSE (External Clock) */
+            vcoinput = ((HSE_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM)));
+          }
+
+          /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
+          /* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */
+          tmpreg1 = (RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> 24U;
+          frequency = (vcoinput * ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6U))/(tmpreg1);
+
+          /* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */
+          tmpreg1 = ((RCC->DCKCFGR & RCC_DCKCFGR_PLLI2SDIVQ) + 1U);
+          frequency = frequency/(tmpreg1);
+          break;
+        }
+      case RCC_DCKCFGR_SAI1SRC_1: /* PLLR is the clock source for SAI*/
+      case RCC_DCKCFGR_SAI2SRC_1: /* PLLR is the clock source for SAI*/
+        {
+          /* Configure the PLLI2S division factor */
+          /* PLL_VCO Input  = PLL_SOURCE/PLLM */
+          if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI)
+          {
+            /* In Case the PLL Source is HSI (Internal Clock) */
+            vcoinput = (HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
+          }
+          else
+          {
+            /* In Case the PLL Source is HSE (External Clock) */
+            vcoinput = ((HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)));
+          }
+
+          /* PLL_VCO Output = PLL_VCO Input * PLLN */
+          /* SAI_CLK_x = PLL_VCO Output/PLLR */
+          tmpreg1 = (RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> 28U;
+          frequency = (vcoinput * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6U))/(tmpreg1);
+          break;
+        }
+      case RCC_DCKCFGR_SAI1SRC: /* External clock is the clock source for SAI*/
+        {
+          frequency = EXTERNAL_CLOCK_VALUE;
+          break;
+        }
+      case RCC_DCKCFGR_SAI2SRC: /* PLLSRC(HSE or HSI) is the clock source for SAI*/
+        {
+          if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI)
+          {
+            /* In Case the PLL Source is HSI (Internal Clock) */
+            frequency = (uint32_t)(HSI_VALUE);
+          }
+          else
+          {
+            /* In Case the PLL Source is HSE (External Clock) */
+            frequency = (uint32_t)(HSE_VALUE);
+          }
+          break;
+        }
+      default :
+        {
+          break;
+        }
+      }
+      break;
+    }
+  case RCC_PERIPHCLK_I2S_APB1:
+    {
+      /* Get the current I2S source */
+      srcclk = __HAL_RCC_GET_I2S_APB1_SOURCE();
+      switch (srcclk)
+      {
+      /* Check if I2S clock selection is External clock mapped on the I2S_CKIN pin used as I2S clock */
+      case RCC_I2SAPB1CLKSOURCE_EXT:
+        {
+          /* Set the I2S clock to the external clock  value */
+          frequency = EXTERNAL_CLOCK_VALUE;
+          break;
+        }
+      /* Check if I2S clock selection is PLLI2S VCO output clock divided by PLLI2SR used as I2S clock */
+      case RCC_I2SAPB1CLKSOURCE_PLLI2S:
+        {
+          /* Configure the PLLI2S division factor */
+          /* PLLI2S_VCO Input  = PLL_SOURCE/PLLI2SM */
+          if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE)
+          {
+            /* Get the I2S source clock value */
+            vcoinput = (uint32_t)(HSE_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM));
+          }
+          else
+          {
+            /* Get the I2S source clock value */
+            vcoinput = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM));
+          }
+
+          /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
+          vcooutput = (uint32_t)(vcoinput * (((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6U) & (RCC_PLLI2SCFGR_PLLI2SN >> 6U)));
+          /* I2S_CLK = PLLI2S_VCO Output/PLLI2SR */
+          frequency = (uint32_t)(vcooutput /(((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> 28U) & (RCC_PLLI2SCFGR_PLLI2SR >> 28U)));
+          break;
+        }
+      /* Check if I2S clock selection is PLL VCO Output divided by PLLR used as I2S clock */
+      case RCC_I2SAPB1CLKSOURCE_PLLR:
+        {
+          /* Configure the PLL division factor R */
+          /* PLL_VCO Input  = PLL_SOURCE/PLLM */
+          if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE)
+          {
+            /* Get the I2S source clock value */
+            vcoinput = (uint32_t)(HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
+          }
+          else
+          {
+            /* Get the I2S source clock value */
+            vcoinput = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
+          }
+
+          /* PLL_VCO Output = PLL_VCO Input * PLLN */
+          vcooutput = (uint32_t)(vcoinput * (((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6U) & (RCC_PLLCFGR_PLLN >> 6U)));
+          /* I2S_CLK = PLL_VCO Output/PLLR */
+          frequency = (uint32_t)(vcooutput /(((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> 28U) & (RCC_PLLCFGR_PLLR >> 28U)));
+          break;
+        }
+      /* Check if I2S clock selection is HSI or HSE depending from PLL source Clock */
+      case RCC_I2SAPB1CLKSOURCE_PLLSRC:
+        {
+          if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE)
+          {
+            frequency = HSE_VALUE;
+          }
+          else
+          {
+            frequency = HSI_VALUE;
+          }
+          break;
+        }
+        /* Clock not enabled for I2S*/
+      default:
+        {
+          frequency = 0U;
+          break;
+        }
+      }
+      break;
+    }
+  case RCC_PERIPHCLK_I2S_APB2:
+    {
+      /* Get the current I2S source */
+      srcclk = __HAL_RCC_GET_I2S_APB2_SOURCE();
+      switch (srcclk)
+      {
+        /* Check if I2S clock selection is External clock mapped on the I2S_CKIN pin used as I2S clock */
+      case RCC_I2SAPB2CLKSOURCE_EXT:
+        {
+          /* Set the I2S clock to the external clock  value */
+          frequency = EXTERNAL_CLOCK_VALUE;
+          break;
+        }
+        /* Check if I2S clock selection is PLLI2S VCO output clock divided by PLLI2SR used as I2S clock */
+      case RCC_I2SAPB2CLKSOURCE_PLLI2S:
+        {
+          /* Configure the PLLI2S division factor */
+          /* PLLI2S_VCO Input  = PLL_SOURCE/PLLI2SM */
+          if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE)
+          {
+            /* Get the I2S source clock value */
+            vcoinput = (uint32_t)(HSE_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM));
+          }
+          else
+          {
+            /* Get the I2S source clock value */
+            vcoinput = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM));
+          }
+
+          /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
+          vcooutput = (uint32_t)(vcoinput * (((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6U) & (RCC_PLLI2SCFGR_PLLI2SN >> 6U)));
+          /* I2S_CLK = PLLI2S_VCO Output/PLLI2SR */
+          frequency = (uint32_t)(vcooutput /(((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> 28U) & (RCC_PLLI2SCFGR_PLLI2SR >> 28U)));
+          break;
+        }
+        /* Check if I2S clock selection is PLL VCO Output divided by PLLR used as I2S clock */
+      case RCC_I2SAPB2CLKSOURCE_PLLR:
+        {
+          /* Configure the PLL division factor R */
+          /* PLL_VCO Input  = PLL_SOURCE/PLLM */
+          if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE)
+          {
+            /* Get the I2S source clock value */
+            vcoinput = (uint32_t)(HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
+          }
+          else
+          {
+            /* Get the I2S source clock value */
+            vcoinput = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
+          }
+
+          /* PLL_VCO Output = PLL_VCO Input * PLLN */
+          vcooutput = (uint32_t)(vcoinput * (((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6U) & (RCC_PLLCFGR_PLLN >> 6U)));
+          /* I2S_CLK = PLL_VCO Output/PLLR */
+          frequency = (uint32_t)(vcooutput /(((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> 28U) & (RCC_PLLCFGR_PLLR >> 28U)));
+          break;
+        }
+        /* Check if I2S clock selection is HSI or HSE depending from PLL source Clock */
+      case RCC_I2SAPB2CLKSOURCE_PLLSRC:
+        {
+          if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE)
+          {
+            frequency = HSE_VALUE;
+          }
+          else
+          {
+            frequency = HSI_VALUE;
+          }
+          break;
+        }
+        /* Clock not enabled for I2S*/
+      default:
+        {
+          frequency = 0U;
+          break;
+        }
+      }
+      break;
+    }
+  }
+  return frequency;
+}
+#endif /* STM32F446xx */
+
+#if defined(STM32F469xx) || defined(STM32F479xx)
+/**
+  * @brief  Initializes the RCC extended peripherals clocks according to the specified
+  *         parameters in the RCC_PeriphCLKInitTypeDef.
+  * @param  PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that
+  *         contains the configuration information for the Extended Peripherals
+  *         clocks(I2S, SAI, LTDC, RTC and TIM).
+  *
+  * @note   Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select
+  *         the RTC clock source; in this case the Backup domain will be reset in
+  *         order to modify the RTC Clock source, as consequence RTC registers (including
+  *         the backup registers) and RCC_BDCR register are set to their reset values.
+  *
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit)
+{
+  uint32_t tickstart = 0U;
+  uint32_t tmpreg1 = 0U;
+  uint32_t pllsaip = 0U;
+  uint32_t pllsaiq = 0U;
+  uint32_t pllsair = 0U;
+
+  /* Check the parameters */
+  assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
+
+  /*--------------------------- CLK48 Configuration --------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_CLK48CLKSOURCE(PeriphClkInit->Clk48ClockSelection));
+
+    /* Configure the CLK48 clock source */
+    __HAL_RCC_CLK48_CONFIG(PeriphClkInit->Clk48ClockSelection);
+  }
+  /*--------------------------------------------------------------------------*/
+
+  /*------------------------------ SDIO Configuration ------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDIO) == RCC_PERIPHCLK_SDIO)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_SDIOCLKSOURCE(PeriphClkInit->SdioClockSelection));
+
+    /* Configure the SDIO clock source */
+    __HAL_RCC_SDIO_CONFIG(PeriphClkInit->SdioClockSelection);
+  }
+  /*--------------------------------------------------------------------------*/
+
+  /*----------------------- SAI/I2S Configuration (PLLI2S) -------------------*/
+  /*------------------- Common configuration SAI/I2S -------------------------*/
+  /* In Case of SAI or I2S Clock Configuration through PLLI2S, PLLI2SN division
+     factor is common parameters for both peripherals */
+  if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) ||
+     (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLI2S) == RCC_PERIPHCLK_SAI_PLLI2S) ||
+     (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S))
+  {
+    /* check for Parameters */
+    assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN));
+
+    /* Disable the PLLI2S */
+    __HAL_RCC_PLLI2S_DISABLE();
+    /* Get tick */
+    tickstart = HAL_GetTick();
+    /* Wait till PLLI2S is disabled */
+    while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY)  != RESET)
+    {
+      if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
+      {
+        /* return in case of Timeout detected */
+        return HAL_TIMEOUT;
+      }
+    }
+
+    /*---------------------- I2S configuration -------------------------------*/
+    /* In Case of I2S Clock Configuration through PLLI2S, PLLI2SR must be added
+      only for I2S configuration */
+    if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == (RCC_PERIPHCLK_I2S))
+    {
+      /* check for Parameters */
+      assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));
+      /* Configure the PLLI2S division factors */
+      /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) x (PLLI2SN/PLLM) */
+      /* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */
+      __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SR);
+    }
+
+    /*---------------------------- SAI configuration -------------------------*/
+    /* In Case of SAI Clock Configuration through PLLI2S, PLLI2SQ and PLLI2S_DIVQ must
+       be added only for SAI configuration */
+    if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLI2S) == (RCC_PERIPHCLK_SAI_PLLI2S))
+    {
+      /* Check the PLLI2S division factors */
+      assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ));
+      assert_param(IS_RCC_PLLI2S_DIVQ_VALUE(PeriphClkInit->PLLI2SDivQ));
+
+      /* Read PLLI2SR value from PLLI2SCFGR register (this value is not need for SAI configuration) */
+      tmpreg1 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos);
+      /* Configure the PLLI2S division factors */
+      /* PLLI2S_VCO Input  = PLL_SOURCE/PLLM */
+      /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
+      /* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */
+      __HAL_RCC_PLLI2S_SAICLK_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SQ , tmpreg1);
+      /* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */
+      __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLI2SDivQ);
+    }
+
+    /*----------------- In Case of PLLI2S is just selected  -----------------*/
+    if((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S)
+    {
+      /* Check for Parameters */
+      assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ));
+      assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));
+
+      /* Configure the PLLI2S multiplication and division factors */
+      __HAL_RCC_PLLI2S_SAICLK_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN, PeriphClkInit->PLLI2S.PLLI2SQ, PeriphClkInit->PLLI2S.PLLI2SR);
+    }
+
+    /* Enable the PLLI2S */
+    __HAL_RCC_PLLI2S_ENABLE();
+    /* Get tick */
+    tickstart = HAL_GetTick();
+    /* Wait till PLLI2S is ready */
+    while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY)  == RESET)
+    {
+      if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
+      {
+        /* return in case of Timeout detected */
+        return HAL_TIMEOUT;
+      }
+    }
+  }
+  /*--------------------------------------------------------------------------*/
+
+  /*----------------------- SAI/LTDC Configuration (PLLSAI) ------------------*/
+  /*----------------------- Common configuration SAI/LTDC --------------------*/
+  /* In Case of SAI, LTDC or CLK48 Clock Configuration through PLLSAI, PLLSAIN division
+     factor is common parameters for these peripherals */
+  if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLSAI) == RCC_PERIPHCLK_SAI_PLLSAI) ||
+     (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC)             ||
+     ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48)          &&
+      (PeriphClkInit->Clk48ClockSelection == RCC_CLK48CLKSOURCE_PLLSAIP)))
+  {
+    /* Check the PLLSAI division factors */
+    assert_param(IS_RCC_PLLSAIN_VALUE(PeriphClkInit->PLLSAI.PLLSAIN));
+
+    /* Disable PLLSAI Clock */
+    __HAL_RCC_PLLSAI_DISABLE();
+    /* Get tick */
+    tickstart = HAL_GetTick();
+    /* Wait till PLLSAI is disabled */
+    while(__HAL_RCC_PLLSAI_GET_FLAG() != RESET)
+    {
+      if((HAL_GetTick() - tickstart ) > PLLSAI_TIMEOUT_VALUE)
+      {
+        /* return in case of Timeout detected */
+        return HAL_TIMEOUT;
+      }
+    }
+
+    /*---------------------------- SAI configuration -------------------------*/
+    /* In Case of SAI Clock Configuration through PLLSAI, PLLSAIQ and PLLSAI_DIVQ must
+       be added only for SAI configuration */
+    if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLSAI) == (RCC_PERIPHCLK_SAI_PLLSAI))
+    {
+      assert_param(IS_RCC_PLLSAIQ_VALUE(PeriphClkInit->PLLSAI.PLLSAIQ));
+      assert_param(IS_RCC_PLLSAI_DIVQ_VALUE(PeriphClkInit->PLLSAIDivQ));
+
+      /* Read PLLSAIP value from PLLSAICFGR register (this value is not needed for SAI configuration) */
+      pllsaip = ((((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> RCC_PLLSAICFGR_PLLSAIP_Pos) + 1U) << 1U);
+      /* Read PLLSAIR value from PLLSAICFGR register (this value is not need for SAI configuration) */
+      pllsair = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> RCC_PLLSAICFGR_PLLSAIR_Pos);
+      /* PLLSAI_VCO Input  = PLL_SOURCE/PLLM */
+      /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
+      /* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */
+      __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN, pllsaip, PeriphClkInit->PLLSAI.PLLSAIQ, pllsair);
+      /* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */
+      __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLSAIDivQ);
+    }
+
+    /*---------------------------- LTDC configuration ------------------------*/
+    if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == (RCC_PERIPHCLK_LTDC))
+    {
+      assert_param(IS_RCC_PLLSAIR_VALUE(PeriphClkInit->PLLSAI.PLLSAIR));
+      assert_param(IS_RCC_PLLSAI_DIVR_VALUE(PeriphClkInit->PLLSAIDivR));
+
+      /* Read PLLSAIP value from PLLSAICFGR register (this value is not needed for SAI configuration) */
+      pllsaip = ((((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> RCC_PLLSAICFGR_PLLSAIP_Pos) + 1U) << 1U);
+      /* Read PLLSAIQ value from PLLSAICFGR register (this value is not need for SAI configuration) */
+      pllsaiq = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos);
+      /* PLLSAI_VCO Input  = PLL_SOURCE/PLLM */
+      /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
+      /* LTDC_CLK(first level) = PLLSAI_VCO Output/PLLSAIR */
+      __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN, pllsaip, pllsaiq, PeriphClkInit->PLLSAI.PLLSAIR);
+      /* LTDC_CLK = LTDC_CLK(first level)/PLLSAIDIVR */
+      __HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG(PeriphClkInit->PLLSAIDivR);
+    }
+
+    /*---------------------------- CLK48 configuration ------------------------*/
+    /* Configure the PLLSAI when it is used as clock source for CLK48 */
+    if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == (RCC_PERIPHCLK_CLK48)) &&
+       (PeriphClkInit->Clk48ClockSelection == RCC_CLK48CLKSOURCE_PLLSAIP))
+    {
+      assert_param(IS_RCC_PLLSAIP_VALUE(PeriphClkInit->PLLSAI.PLLSAIP));
+
+      /* Read PLLSAIQ value from PLLSAICFGR register (this value is not need for SAI configuration) */
+      pllsaiq = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos);
+      /* Read PLLSAIR value from PLLSAICFGR register (this value is not need for SAI configuration) */
+      pllsair = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> RCC_PLLSAICFGR_PLLSAIR_Pos);
+      /* PLLSAI_VCO Input  = PLL_SOURCE/PLLM */
+      /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
+      /* CLK48_CLK(first level) = PLLSAI_VCO Output/PLLSAIP */
+      __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN, PeriphClkInit->PLLSAI.PLLSAIP, pllsaiq, pllsair);
+    }
+
+    /* Enable PLLSAI Clock */
+    __HAL_RCC_PLLSAI_ENABLE();
+    /* Get tick */
+    tickstart = HAL_GetTick();
+    /* Wait till PLLSAI is ready */
+    while(__HAL_RCC_PLLSAI_GET_FLAG() == RESET)
+    {
+      if((HAL_GetTick() - tickstart ) > PLLSAI_TIMEOUT_VALUE)
+      {
+        /* return in case of Timeout detected */
+        return HAL_TIMEOUT;
+      }
+    }
+  }
+
+  /*--------------------------------------------------------------------------*/
+
+  /*---------------------------- RTC configuration ---------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC))
+  {
+    /* Check for RTC Parameters used to output RTCCLK */
+    assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
+
+    /* Enable Power Clock*/
+    __HAL_RCC_PWR_CLK_ENABLE();
+
+    /* Enable write access to Backup domain */
+    PWR->CR |= PWR_CR_DBP;
+
+    /* Get tick */
+    tickstart = HAL_GetTick();
+
+    while((PWR->CR & PWR_CR_DBP) == RESET)
+    {
+      if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE)
+      {
+        return HAL_TIMEOUT;
+      }
+    }
+    /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */
+    tmpreg1 = (RCC->BDCR & RCC_BDCR_RTCSEL);
+    if((tmpreg1 != 0x00000000U) && ((tmpreg1) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)))
+    {
+      /* Store the content of BDCR register before the reset of Backup Domain */
+      tmpreg1 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
+      /* RTC Clock selection can be changed only if the Backup Domain is reset */
+      __HAL_RCC_BACKUPRESET_FORCE();
+      __HAL_RCC_BACKUPRESET_RELEASE();
+      /* Restore the Content of BDCR register */
+      RCC->BDCR = tmpreg1;
+
+      /* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */
+      if(HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSEON))
+      {
+        /* Get tick */
+        tickstart = HAL_GetTick();
+
+        /* Wait till LSE is ready */
+        while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
+        {
+          if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
+          {
+            return HAL_TIMEOUT;
+          }
+        }
+      }
+    }
+    __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
+  }
+  /*--------------------------------------------------------------------------*/
+
+  /*---------------------------- TIM configuration ---------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM))
+  {
+    __HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection);
+  }
+  return HAL_OK;
+}
+
+/**
+  * @brief  Configures the RCC_PeriphCLKInitTypeDef according to the internal
+  * RCC configuration registers.
+  * @param  PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that
+  *         will be configured.
+  * @retval None
+  */
+void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit)
+{
+  uint32_t tempreg;
+
+  /* Set all possible values for the extended clock type parameter------------*/
+  PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_I2S        | RCC_PERIPHCLK_SAI_PLLSAI |\
+                                        RCC_PERIPHCLK_SAI_PLLI2S | RCC_PERIPHCLK_LTDC       |\
+                                        RCC_PERIPHCLK_TIM        | RCC_PERIPHCLK_RTC        |\
+                                        RCC_PERIPHCLK_CLK48       | RCC_PERIPHCLK_SDIO;
+
+  /* Get the PLLI2S Clock configuration --------------------------------------*/
+  PeriphClkInit->PLLI2S.PLLI2SN = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> RCC_PLLI2SCFGR_PLLI2SN_Pos);
+  PeriphClkInit->PLLI2S.PLLI2SR = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos);
+  PeriphClkInit->PLLI2S.PLLI2SQ = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos);
+  /* Get the PLLSAI Clock configuration --------------------------------------*/
+  PeriphClkInit->PLLSAI.PLLSAIN = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> RCC_PLLSAICFGR_PLLSAIN_Pos);
+  PeriphClkInit->PLLSAI.PLLSAIR = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> RCC_PLLSAICFGR_PLLSAIR_Pos);
+  PeriphClkInit->PLLSAI.PLLSAIQ = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos);
+  /* Get the PLLSAI/PLLI2S division factors ----------------------------------*/
+  PeriphClkInit->PLLI2SDivQ = (uint32_t)((RCC->DCKCFGR & RCC_DCKCFGR_PLLI2SDIVQ) >> RCC_DCKCFGR_PLLI2SDIVQ_Pos);
+  PeriphClkInit->PLLSAIDivQ = (uint32_t)((RCC->DCKCFGR & RCC_DCKCFGR_PLLSAIDIVQ) >> RCC_DCKCFGR_PLLSAIDIVQ_Pos);
+  PeriphClkInit->PLLSAIDivR = (uint32_t)(RCC->DCKCFGR & RCC_DCKCFGR_PLLSAIDIVR);
+  /* Get the RTC Clock configuration -----------------------------------------*/
+  tempreg = (RCC->CFGR & RCC_CFGR_RTCPRE);
+  PeriphClkInit->RTCClockSelection = (uint32_t)((tempreg) | (RCC->BDCR & RCC_BDCR_RTCSEL));
+
+    /* Get the CLK48 clock configuration -------------------------------------*/
+  PeriphClkInit->Clk48ClockSelection = __HAL_RCC_GET_CLK48_SOURCE();
+
+  /* Get the SDIO clock configuration ----------------------------------------*/
+  PeriphClkInit->SdioClockSelection = __HAL_RCC_GET_SDIO_SOURCE();
+
+  if ((RCC->DCKCFGR & RCC_DCKCFGR_TIMPRE) == RESET)
+  {
+    PeriphClkInit->TIMPresSelection = RCC_TIMPRES_DESACTIVATED;
+  }
+  else
+  {
+    PeriphClkInit->TIMPresSelection = RCC_TIMPRES_ACTIVATED;
+  }
+}
+
+/**
+  * @brief  Return the peripheral clock frequency for a given peripheral(SAI..)
+  * @note   Return 0 if peripheral clock identifier not managed by this API
+  * @param  PeriphClk Peripheral clock identifier
+  *         This parameter can be one of the following values:
+  *            @arg RCC_PERIPHCLK_I2S: I2S peripheral clock
+  * @retval Frequency in KHz
+  */
+uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
+{
+  /* This variable used to store the I2S clock frequency (value in Hz) */
+  uint32_t frequency = 0U;
+  /* This variable used to store the VCO Input (value in Hz) */
+  uint32_t vcoinput = 0U;
+  uint32_t srcclk = 0U;
+  /* This variable used to store the VCO Output (value in Hz) */
+  uint32_t vcooutput = 0U;
+  switch (PeriphClk)
+  {
+  case RCC_PERIPHCLK_I2S:
+    {
+      /* Get the current I2S source */
+      srcclk = __HAL_RCC_GET_I2S_SOURCE();
+      switch (srcclk)
+      {
+      /* Check if I2S clock selection is External clock mapped on the I2S_CKIN pin used as I2S clock */
+      case RCC_I2SCLKSOURCE_EXT:
+        {
+          /* Set the I2S clock to the external clock  value */
+          frequency = EXTERNAL_CLOCK_VALUE;
+          break;
+        }
+      /* Check if I2S clock selection is PLLI2S VCO output clock divided by PLLI2SR used as I2S clock */
+      case RCC_I2SCLKSOURCE_PLLI2S:
+        {
+          /* Configure the PLLI2S division factor */
+          /* PLLI2S_VCO Input  = PLL_SOURCE/PLLI2SM */
+          if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE)
+          {
+            /* Get the I2S source clock value */
+            vcoinput = (uint32_t)(HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
+          }
+          else
+          {
+            /* Get the I2S source clock value */
+            vcoinput = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
+          }
+
+          /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
+          vcooutput = (uint32_t)(vcoinput * (((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6U) & (RCC_PLLI2SCFGR_PLLI2SN >> 6U)));
+          /* I2S_CLK = PLLI2S_VCO Output/PLLI2SR */
+          frequency = (uint32_t)(vcooutput /(((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> 28U) & (RCC_PLLI2SCFGR_PLLI2SR >> 28U)));
+          break;
+        }
+        /* Clock not enabled for I2S*/
+      default:
+        {
+          frequency = 0U;
+          break;
+        }
+      }
+      break;
+    }
+  }
+  return frequency;
+}
+#endif /* STM32F469xx || STM32F479xx */
+
+#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
+/**
+  * @brief  Initializes the RCC extended peripherals clocks according to the specified
+  *         parameters in the RCC_PeriphCLKInitTypeDef.
+  * @param  PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that
+  *         contains the configuration information for the Extended Peripherals
+  *         clocks(I2S, LTDC RTC and TIM).
+  *
+  * @note   Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select
+  *         the RTC clock source; in this case the Backup domain will be reset in
+  *         order to modify the RTC Clock source, as consequence RTC registers (including
+  *         the backup registers) and RCC_BDCR register are set to their reset values.
+  *
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit)
+{
+  uint32_t tickstart = 0U;
+  uint32_t tmpreg1 = 0U;
+#if defined(STM32F413xx) || defined(STM32F423xx)
+  uint32_t plli2sq = 0U;
+#endif /* STM32F413xx || STM32F423xx */
+  uint32_t plli2sused = 0U;
+
+  /* Check the peripheral clock selection parameters */
+  assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
+
+  /*----------------------------------- I2S APB1 configuration ---------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB1) == (RCC_PERIPHCLK_I2S_APB1))
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_I2SAPB1CLKSOURCE(PeriphClkInit->I2sApb1ClockSelection));
+
+    /* Configure I2S Clock source */
+    __HAL_RCC_I2S_APB1_CONFIG(PeriphClkInit->I2sApb1ClockSelection);
+    /* Enable the PLLI2S when it's used as clock source for I2S */
+    if(PeriphClkInit->I2sApb1ClockSelection == RCC_I2SAPB1CLKSOURCE_PLLI2S)
+    {
+      plli2sused = 1U;
+    }
+  }
+  /*--------------------------------------------------------------------------*/
+
+  /*----------------------------------- I2S APB2 configuration ---------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB2) == (RCC_PERIPHCLK_I2S_APB2))
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_I2SAPB2CLKSOURCE(PeriphClkInit->I2sApb2ClockSelection));
+
+    /* Configure I2S Clock source */
+    __HAL_RCC_I2S_APB2_CONFIG(PeriphClkInit->I2sApb2ClockSelection);
+    /* Enable the PLLI2S when it's used as clock source for I2S */
+    if(PeriphClkInit->I2sApb2ClockSelection == RCC_I2SAPB2CLKSOURCE_PLLI2S)
+    {
+      plli2sused = 1U;
+    }
+  }
+  /*--------------------------------------------------------------------------*/
+
+#if defined(STM32F413xx) || defined(STM32F423xx)
+  /*----------------------- SAI1 Block A configuration -----------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAIA) == (RCC_PERIPHCLK_SAIA))
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_SAIACLKSOURCE(PeriphClkInit->SaiAClockSelection));
+
+    /* Configure SAI1 Clock source */
+    __HAL_RCC_SAI_BLOCKACLKSOURCE_CONFIG(PeriphClkInit->SaiAClockSelection);
+    /* Enable the PLLI2S when it's used as clock source for SAI */
+    if(PeriphClkInit->SaiAClockSelection == RCC_SAIACLKSOURCE_PLLI2SR)
+    {
+      plli2sused = 1U;
+    }
+    /* Enable the PLLSAI when it's used as clock source for SAI */
+    if(PeriphClkInit->SaiAClockSelection == RCC_SAIACLKSOURCE_PLLR)
+    {
+      /* Check for PLL/DIVR parameters */
+      assert_param(IS_RCC_PLL_DIVR_VALUE(PeriphClkInit->PLLDivR));
+
+      /* SAI_CLK_x = SAI_CLK(first level)/PLLDIVR */
+      __HAL_RCC_PLL_PLLSAICLKDIVR_CONFIG(PeriphClkInit->PLLDivR);
+    }
+  }
+  /*--------------------------------------------------------------------------*/
+
+  /*---------------------- SAI1 Block B configuration ------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAIB) == (RCC_PERIPHCLK_SAIB))
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_SAIBCLKSOURCE(PeriphClkInit->SaiBClockSelection));
+
+    /* Configure SAI1 Clock source */
+    __HAL_RCC_SAI_BLOCKBCLKSOURCE_CONFIG(PeriphClkInit->SaiBClockSelection);
+    /* Enable the PLLI2S when it's used as clock source for SAI */
+    if(PeriphClkInit->SaiBClockSelection == RCC_SAIBCLKSOURCE_PLLI2SR)
+    {
+      plli2sused = 1U;
+    }
+    /* Enable the PLLSAI when it's used as clock source for SAI */
+    if(PeriphClkInit->SaiBClockSelection == RCC_SAIBCLKSOURCE_PLLR)
+    {
+      /* Check for PLL/DIVR parameters */
+      assert_param(IS_RCC_PLL_DIVR_VALUE(PeriphClkInit->PLLDivR));
+
+      /* SAI_CLK_x = SAI_CLK(first level)/PLLDIVR */
+      __HAL_RCC_PLL_PLLSAICLKDIVR_CONFIG(PeriphClkInit->PLLDivR);
+    }
+  }
+  /*--------------------------------------------------------------------------*/
+#endif /* STM32F413xx || STM32F423xx */
+
+  /*------------------------------------ RTC configuration -------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC))
+  {
+    /* Check for RTC Parameters used to output RTCCLK */
+    assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
+
+    /* Enable Power Clock*/
+    __HAL_RCC_PWR_CLK_ENABLE();
+
+    /* Enable write access to Backup domain */
+    PWR->CR |= PWR_CR_DBP;
+
+    /* Get tick */
+    tickstart = HAL_GetTick();
+
+    while((PWR->CR & PWR_CR_DBP) == RESET)
+    {
+      if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE)
+      {
+        return HAL_TIMEOUT;
+      }
+    }
+    /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */
+    tmpreg1 = (RCC->BDCR & RCC_BDCR_RTCSEL);
+    if((tmpreg1 != 0x00000000U) && ((tmpreg1) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)))
+    {
+      /* Store the content of BDCR register before the reset of Backup Domain */
+      tmpreg1 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
+      /* RTC Clock selection can be changed only if the Backup Domain is reset */
+      __HAL_RCC_BACKUPRESET_FORCE();
+      __HAL_RCC_BACKUPRESET_RELEASE();
+      /* Restore the Content of BDCR register */
+      RCC->BDCR = tmpreg1;
+
+      /* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */
+      if(HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSEON))
+      {
+        /* Get tick */
+        tickstart = HAL_GetTick();
+
+        /* Wait till LSE is ready */
+        while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
+        {
+          if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
+          {
+            return HAL_TIMEOUT;
+          }
+        }
+      }
+    }
+    __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
+  }
+  /*--------------------------------------------------------------------------*/
+
+  /*------------------------------------ TIM configuration -------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM))
+  {
+    /* Configure Timer Prescaler */
+    __HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection);
+  }
+  /*--------------------------------------------------------------------------*/
+
+  /*------------------------------------- FMPI2C1 Configuration --------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FMPI2C1) == RCC_PERIPHCLK_FMPI2C1)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_FMPI2C1CLKSOURCE(PeriphClkInit->Fmpi2c1ClockSelection));
+
+    /* Configure the FMPI2C1 clock source */
+    __HAL_RCC_FMPI2C1_CONFIG(PeriphClkInit->Fmpi2c1ClockSelection);
+  }
+  /*--------------------------------------------------------------------------*/
+
+  /*------------------------------------- CLK48 Configuration ----------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_CLK48CLKSOURCE(PeriphClkInit->Clk48ClockSelection));
+
+    /* Configure the SDIO clock source */
+    __HAL_RCC_CLK48_CONFIG(PeriphClkInit->Clk48ClockSelection);
+
+    /* Enable the PLLI2S when it's used as clock source for CLK48 */
+    if(PeriphClkInit->Clk48ClockSelection == RCC_CLK48CLKSOURCE_PLLI2SQ)
+    {
+      plli2sused = 1U;
+    }
+  }
+  /*--------------------------------------------------------------------------*/
+
+  /*------------------------------------- SDIO Configuration -----------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDIO) == RCC_PERIPHCLK_SDIO)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_SDIOCLKSOURCE(PeriphClkInit->SdioClockSelection));
+
+    /* Configure the SDIO clock source */
+    __HAL_RCC_SDIO_CONFIG(PeriphClkInit->SdioClockSelection);
+  }
+  /*--------------------------------------------------------------------------*/
+
+  /*-------------------------------------- PLLI2S Configuration --------------*/
+  /* PLLI2S is configured when a peripheral will use it as source clock : I2S on APB1 or
+     I2S on APB2*/
+  if((plli2sused == 1U) || (PeriphClkInit->PeriphClockSelection == RCC_PERIPHCLK_PLLI2S))
+  {
+    /* Disable the PLLI2S */
+    __HAL_RCC_PLLI2S_DISABLE();
+    /* Get tick */
+    tickstart = HAL_GetTick();
+    /* Wait till PLLI2S is disabled */
+    while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY)  != RESET)
+    {
+      if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
+      {
+        /* return in case of Timeout detected */
+        return HAL_TIMEOUT;
+      }
+    }
+
+    /* check for common PLLI2S Parameters */
+    assert_param(IS_RCC_PLLI2SCLKSOURCE(PeriphClkInit->PLLI2SSelection));
+    assert_param(IS_RCC_PLLI2SM_VALUE(PeriphClkInit->PLLI2S.PLLI2SM));
+    assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN));
+    /*-------------------- Set the PLL I2S clock -----------------------------*/
+    __HAL_RCC_PLL_I2S_CONFIG(PeriphClkInit->PLLI2SSelection);
+
+    /*------- In Case of PLLI2S is selected as source clock for I2S ----------*/
+    if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB1) == RCC_PERIPHCLK_I2S_APB1) && (PeriphClkInit->I2sApb1ClockSelection == RCC_I2SAPB1CLKSOURCE_PLLI2S)) ||
+       ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB2) == RCC_PERIPHCLK_I2S_APB2) && (PeriphClkInit->I2sApb2ClockSelection == RCC_I2SAPB2CLKSOURCE_PLLI2S)) ||
+       ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) && (PeriphClkInit->Clk48ClockSelection == RCC_CLK48CLKSOURCE_PLLI2SQ)) ||
+       ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDIO) == RCC_PERIPHCLK_SDIO) && (PeriphClkInit->SdioClockSelection == RCC_SDIOCLKSOURCE_CLK48) && (PeriphClkInit->Clk48ClockSelection == RCC_CLK48CLKSOURCE_PLLI2SQ)))
+    {
+      /* check for Parameters */
+      assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));
+      assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ));
+
+      /* Configure the PLLI2S division factors */
+      /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLI2SM)*/
+      /* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */
+      __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SQ, PeriphClkInit->PLLI2S.PLLI2SR);
+    }
+
+#if defined(STM32F413xx) || defined(STM32F423xx)
+    /*------- In Case of PLLI2S is selected as source clock for SAI ----------*/
+    if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAIA) == RCC_PERIPHCLK_SAIA) && (PeriphClkInit->SaiAClockSelection == RCC_SAIACLKSOURCE_PLLI2SR)) ||
+       ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAIB) == RCC_PERIPHCLK_SAIB) && (PeriphClkInit->SaiBClockSelection == RCC_SAIBCLKSOURCE_PLLI2SR)))
+    {
+      /* Check for PLLI2S Parameters */
+      assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));
+      /* Check for PLLI2S/DIVR parameters */
+      assert_param(IS_RCC_PLLI2S_DIVR_VALUE(PeriphClkInit->PLLI2SDivR));
+
+      /* Read PLLI2SQ value from PLLI2SCFGR register (this value is not needed for SAI configuration) */
+      plli2sq = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos);
+      /* Configure the PLLI2S division factors */
+      /* PLLI2S_VCO Input  = PLL_SOURCE/PLLI2SM */
+      /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
+      /* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */
+      __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN, plli2sq, PeriphClkInit->PLLI2S.PLLI2SR);
+
+      /* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVR */
+      __HAL_RCC_PLLI2S_PLLSAICLKDIVR_CONFIG(PeriphClkInit->PLLI2SDivR);
+    }
+#endif /* STM32F413xx || STM32F423xx */
+
+    /*----------------- In Case of PLLI2S is just selected  ------------------*/
+    if((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S)
+    {
+      /* Check for Parameters */
+      assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));
+      assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ));
+
+      /* Configure the PLLI2S division factors */
+      /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLI2SM)*/
+      /* SPDIFRXCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SP */
+      __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SQ, PeriphClkInit->PLLI2S.PLLI2SR);
+    }
+
+    /* Enable the PLLI2S */
+    __HAL_RCC_PLLI2S_ENABLE();
+    /* Get tick */
+    tickstart = HAL_GetTick();
+    /* Wait till PLLI2S is ready */
+    while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY)  == RESET)
+    {
+      if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
+      {
+        /* return in case of Timeout detected */
+        return HAL_TIMEOUT;
+      }
+    }
+  }
+  /*--------------------------------------------------------------------------*/
+
+  /*-------------------- DFSDM1 clock source configuration -------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_DFSDM1CLKSOURCE(PeriphClkInit->Dfsdm1ClockSelection));
+
+    /* Configure the DFSDM1 interface clock source */
+    __HAL_RCC_DFSDM1_CONFIG(PeriphClkInit->Dfsdm1ClockSelection);
+  }
+  /*--------------------------------------------------------------------------*/
+
+  /*-------------------- DFSDM1 Audio clock source configuration -------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM1_AUDIO) == RCC_PERIPHCLK_DFSDM1_AUDIO)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_DFSDM1AUDIOCLKSOURCE(PeriphClkInit->Dfsdm1AudioClockSelection));
+
+    /* Configure the DFSDM1 Audio interface clock source */
+    __HAL_RCC_DFSDM1AUDIO_CONFIG(PeriphClkInit->Dfsdm1AudioClockSelection);
+  }
+  /*--------------------------------------------------------------------------*/
+
+#if defined(STM32F413xx) || defined(STM32F423xx)
+  /*-------------------- DFSDM2 clock source configuration -------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM2) == RCC_PERIPHCLK_DFSDM2)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_DFSDM2CLKSOURCE(PeriphClkInit->Dfsdm2ClockSelection));
+
+    /* Configure the DFSDM1 interface clock source */
+    __HAL_RCC_DFSDM2_CONFIG(PeriphClkInit->Dfsdm2ClockSelection);
+  }
+  /*--------------------------------------------------------------------------*/
+
+  /*-------------------- DFSDM2 Audio clock source configuration -------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM2_AUDIO) == RCC_PERIPHCLK_DFSDM2_AUDIO)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_DFSDM2AUDIOCLKSOURCE(PeriphClkInit->Dfsdm2AudioClockSelection));
+
+    /* Configure the DFSDM1 Audio interface clock source */
+    __HAL_RCC_DFSDM2AUDIO_CONFIG(PeriphClkInit->Dfsdm2AudioClockSelection);
+  }
+  /*--------------------------------------------------------------------------*/
+
+  /*---------------------------- LPTIM1 Configuration ------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_LPTIM1CLKSOURCE(PeriphClkInit->Lptim1ClockSelection));
+
+    /* Configure the LPTIM1 clock source */
+    __HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection);
+  }
+  /*--------------------------------------------------------------------------*/
+#endif /* STM32F413xx || STM32F423xx */
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Get the RCC_PeriphCLKInitTypeDef according to the internal
+  *         RCC configuration registers.
+  * @param  PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that
+  *         will be configured.
+  * @retval None
+  */
+void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit)
+{
+  uint32_t tempreg;
+
+  /* Set all possible values for the extended clock type parameter------------*/
+#if defined(STM32F413xx) || defined(STM32F423xx)
+  PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_I2S_APB1     | RCC_PERIPHCLK_I2S_APB2 |\
+                                        RCC_PERIPHCLK_TIM          | RCC_PERIPHCLK_RTC      |\
+                                        RCC_PERIPHCLK_FMPI2C1      | RCC_PERIPHCLK_CLK48    |\
+                                        RCC_PERIPHCLK_SDIO         | RCC_PERIPHCLK_DFSDM1   |\
+                                        RCC_PERIPHCLK_DFSDM1_AUDIO | RCC_PERIPHCLK_DFSDM2   |\
+                                        RCC_PERIPHCLK_DFSDM2_AUDIO | RCC_PERIPHCLK_LPTIM1   |\
+                                        RCC_PERIPHCLK_SAIA         | RCC_PERIPHCLK_SAIB;
+#else /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */
+  PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_I2S_APB1 | RCC_PERIPHCLK_I2S_APB2 |\
+                                        RCC_PERIPHCLK_TIM      | RCC_PERIPHCLK_RTC      |\
+                                        RCC_PERIPHCLK_FMPI2C1  | RCC_PERIPHCLK_CLK48    |\
+                                        RCC_PERIPHCLK_SDIO     | RCC_PERIPHCLK_DFSDM1   |\
+                                        RCC_PERIPHCLK_DFSDM1_AUDIO;
+#endif /* STM32F413xx || STM32F423xx */
+
+
+
+  /* Get the PLLI2S Clock configuration --------------------------------------*/
+  PeriphClkInit->PLLI2S.PLLI2SM = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM) >> RCC_PLLI2SCFGR_PLLI2SM_Pos);
+  PeriphClkInit->PLLI2S.PLLI2SN = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> RCC_PLLI2SCFGR_PLLI2SN_Pos);
+  PeriphClkInit->PLLI2S.PLLI2SQ = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos);
+  PeriphClkInit->PLLI2S.PLLI2SR = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos);
+#if defined(STM32F413xx) || defined(STM32F423xx)
+  /* Get the PLL/PLLI2S division factors -------------------------------------*/
+  PeriphClkInit->PLLI2SDivR = (uint32_t)((RCC->DCKCFGR & RCC_DCKCFGR_PLLI2SDIVR) >> RCC_DCKCFGR_PLLI2SDIVR_Pos);
+  PeriphClkInit->PLLDivR = (uint32_t)((RCC->DCKCFGR & RCC_DCKCFGR_PLLDIVR) >> RCC_DCKCFGR_PLLDIVR_Pos);
+#endif /* STM32F413xx || STM32F423xx */
+
+  /* Get the I2S APB1 clock configuration ------------------------------------*/
+  PeriphClkInit->I2sApb1ClockSelection = __HAL_RCC_GET_I2S_APB1_SOURCE();
+
+  /* Get the I2S APB2 clock configuration ------------------------------------*/
+  PeriphClkInit->I2sApb2ClockSelection = __HAL_RCC_GET_I2S_APB2_SOURCE();
+
+  /* Get the RTC Clock configuration -----------------------------------------*/
+  tempreg = (RCC->CFGR & RCC_CFGR_RTCPRE);
+  PeriphClkInit->RTCClockSelection = (uint32_t)((tempreg) | (RCC->BDCR & RCC_BDCR_RTCSEL));
+
+  /* Get the FMPI2C1 clock configuration -------------------------------------*/
+  PeriphClkInit->Fmpi2c1ClockSelection = __HAL_RCC_GET_FMPI2C1_SOURCE();
+
+  /* Get the CLK48 clock configuration ---------------------------------------*/
+  PeriphClkInit->Clk48ClockSelection = __HAL_RCC_GET_CLK48_SOURCE();
+
+  /* Get the SDIO clock configuration ----------------------------------------*/
+  PeriphClkInit->SdioClockSelection = __HAL_RCC_GET_SDIO_SOURCE();
+
+  /* Get the DFSDM1 clock configuration --------------------------------------*/
+  PeriphClkInit->Dfsdm1ClockSelection = __HAL_RCC_GET_DFSDM1_SOURCE();
+
+  /* Get the DFSDM1 Audio clock configuration --------------------------------*/
+  PeriphClkInit->Dfsdm1AudioClockSelection = __HAL_RCC_GET_DFSDM1AUDIO_SOURCE();
+
+#if defined(STM32F413xx) || defined(STM32F423xx)
+  /* Get the DFSDM2 clock configuration --------------------------------------*/
+  PeriphClkInit->Dfsdm2ClockSelection = __HAL_RCC_GET_DFSDM2_SOURCE();
+
+  /* Get the DFSDM2 Audio clock configuration --------------------------------*/
+  PeriphClkInit->Dfsdm2AudioClockSelection = __HAL_RCC_GET_DFSDM2AUDIO_SOURCE();
+
+  /* Get the LPTIM1 clock configuration --------------------------------------*/
+  PeriphClkInit->Lptim1ClockSelection = __HAL_RCC_GET_LPTIM1_SOURCE();
+
+  /* Get the SAI1 Block Aclock configuration ---------------------------------*/
+  PeriphClkInit->SaiAClockSelection = __HAL_RCC_GET_SAI_BLOCKA_SOURCE();
+
+  /* Get the SAI1 Block B clock configuration --------------------------------*/
+  PeriphClkInit->SaiBClockSelection = __HAL_RCC_GET_SAI_BLOCKB_SOURCE();
+#endif /* STM32F413xx || STM32F423xx */
+
+  /* Get the TIM Prescaler configuration -------------------------------------*/
+  if ((RCC->DCKCFGR & RCC_DCKCFGR_TIMPRE) == RESET)
+  {
+    PeriphClkInit->TIMPresSelection = RCC_TIMPRES_DESACTIVATED;
+  }
+  else
+  {
+    PeriphClkInit->TIMPresSelection = RCC_TIMPRES_ACTIVATED;
+  }
+}
+
+/**
+  * @brief  Return the peripheral clock frequency for a given peripheral(I2S..)
+  * @note   Return 0 if peripheral clock identifier not managed by this API
+  * @param  PeriphClk Peripheral clock identifier
+  *         This parameter can be one of the following values:
+  *            @arg RCC_PERIPHCLK_I2S_APB1: I2S APB1 peripheral clock
+  *            @arg RCC_PERIPHCLK_I2S_APB2: I2S APB2 peripheral clock
+  * @retval Frequency in KHz
+  */
+uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
+{
+  /* This variable used to store the I2S clock frequency (value in Hz) */
+  uint32_t frequency = 0U;
+  /* This variable used to store the VCO Input (value in Hz) */
+  uint32_t vcoinput = 0U;
+  uint32_t srcclk = 0U;
+  /* This variable used to store the VCO Output (value in Hz) */
+  uint32_t vcooutput = 0U;
+  switch (PeriphClk)
+  {
+  case RCC_PERIPHCLK_I2S_APB1:
+    {
+      /* Get the current I2S source */
+      srcclk = __HAL_RCC_GET_I2S_APB1_SOURCE();
+      switch (srcclk)
+      {
+      /* Check if I2S clock selection is External clock mapped on the I2S_CKIN pin used as I2S clock */
+      case RCC_I2SAPB1CLKSOURCE_EXT:
+        {
+          /* Set the I2S clock to the external clock  value */
+          frequency = EXTERNAL_CLOCK_VALUE;
+          break;
+        }
+      /* Check if I2S clock selection is PLLI2S VCO output clock divided by PLLI2SR used as I2S clock */
+      case RCC_I2SAPB1CLKSOURCE_PLLI2S:
+        {
+          if((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SSRC) == RCC_PLLI2SCFGR_PLLI2SSRC)
+          {
+            /* Get the I2S source clock value */
+            vcoinput = (uint32_t)(EXTERNAL_CLOCK_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM));
+          }
+          else
+          {
+            /* Configure the PLLI2S division factor */
+            /* PLLI2S_VCO Input  = PLL_SOURCE/PLLI2SM */
+            if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE)
+            {
+              /* Get the I2S source clock value */
+              vcoinput = (uint32_t)(HSE_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM));
+            }
+            else
+            {
+              /* Get the I2S source clock value */
+              vcoinput = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM));
+            }
+          }
+          /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
+          vcooutput = (uint32_t)(vcoinput * (((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6U) & (RCC_PLLI2SCFGR_PLLI2SN >> 6U)));
+          /* I2S_CLK = PLLI2S_VCO Output/PLLI2SR */
+          frequency = (uint32_t)(vcooutput /(((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> 28U) & (RCC_PLLI2SCFGR_PLLI2SR >> 28U)));
+          break;
+        }
+      /* Check if I2S clock selection is PLL VCO Output divided by PLLR used as I2S clock */
+      case RCC_I2SAPB1CLKSOURCE_PLLR:
+        {
+          /* Configure the PLL division factor R */
+          /* PLL_VCO Input  = PLL_SOURCE/PLLM */
+          if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE)
+          {
+            /* Get the I2S source clock value */
+            vcoinput = (uint32_t)(HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
+          }
+          else
+          {
+            /* Get the I2S source clock value */
+            vcoinput = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
+          }
+
+          /* PLL_VCO Output = PLL_VCO Input * PLLN */
+          vcooutput = (uint32_t)(vcoinput * (((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6U) & (RCC_PLLCFGR_PLLN >> 6U)));
+          /* I2S_CLK = PLL_VCO Output/PLLR */
+          frequency = (uint32_t)(vcooutput /(((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> 28U) & (RCC_PLLCFGR_PLLR >> 28U)));
+          break;
+        }
+      /* Check if I2S clock selection is HSI or HSE depending from PLL source Clock */
+      case RCC_I2SAPB1CLKSOURCE_PLLSRC:
+        {
+          if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE)
+          {
+            frequency = HSE_VALUE;
+          }
+          else
+          {
+            frequency = HSI_VALUE;
+          }
+          break;
+        }
+        /* Clock not enabled for I2S*/
+      default:
+        {
+          frequency = 0U;
+          break;
+        }
+      }
+      break;
+    }
+  case RCC_PERIPHCLK_I2S_APB2:
+    {
+      /* Get the current I2S source */
+      srcclk = __HAL_RCC_GET_I2S_APB2_SOURCE();
+      switch (srcclk)
+      {
+        /* Check if I2S clock selection is External clock mapped on the I2S_CKIN pin used as I2S clock */
+      case RCC_I2SAPB2CLKSOURCE_EXT:
+        {
+          /* Set the I2S clock to the external clock  value */
+          frequency = EXTERNAL_CLOCK_VALUE;
+          break;
+        }
+        /* Check if I2S clock selection is PLLI2S VCO output clock divided by PLLI2SR used as I2S clock */
+      case RCC_I2SAPB2CLKSOURCE_PLLI2S:
+        {
+          if((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SSRC) == RCC_PLLI2SCFGR_PLLI2SSRC)
+          {
+            /* Get the I2S source clock value */
+            vcoinput = (uint32_t)(EXTERNAL_CLOCK_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM));
+          }
+          else
+          {
+            /* Configure the PLLI2S division factor */
+            /* PLLI2S_VCO Input  = PLL_SOURCE/PLLI2SM */
+            if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE)
+            {
+              /* Get the I2S source clock value */
+              vcoinput = (uint32_t)(HSE_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM));
+            }
+            else
+            {
+              /* Get the I2S source clock value */
+              vcoinput = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM));
+            }
+          }
+          /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
+          vcooutput = (uint32_t)(vcoinput * (((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6U) & (RCC_PLLI2SCFGR_PLLI2SN >> 6U)));
+          /* I2S_CLK = PLLI2S_VCO Output/PLLI2SR */
+          frequency = (uint32_t)(vcooutput /(((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> 28U) & (RCC_PLLI2SCFGR_PLLI2SR >> 28U)));
+          break;
+        }
+        /* Check if I2S clock selection is PLL VCO Output divided by PLLR used as I2S clock */
+      case RCC_I2SAPB2CLKSOURCE_PLLR:
+        {
+          /* Configure the PLL division factor R */
+          /* PLL_VCO Input  = PLL_SOURCE/PLLM */
+          if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE)
+          {
+            /* Get the I2S source clock value */
+            vcoinput = (uint32_t)(HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
+          }
+          else
+          {
+            /* Get the I2S source clock value */
+            vcoinput = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
+          }
+
+          /* PLL_VCO Output = PLL_VCO Input * PLLN */
+          vcooutput = (uint32_t)(vcoinput * (((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6U) & (RCC_PLLCFGR_PLLN >> 6U)));
+          /* I2S_CLK = PLL_VCO Output/PLLR */
+          frequency = (uint32_t)(vcooutput /(((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> 28U) & (RCC_PLLCFGR_PLLR >> 28U)));
+          break;
+        }
+        /* Check if I2S clock selection is HSI or HSE depending from PLL source Clock */
+      case RCC_I2SAPB2CLKSOURCE_PLLSRC:
+        {
+          if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE)
+          {
+            frequency = HSE_VALUE;
+          }
+          else
+          {
+            frequency = HSI_VALUE;
+          }
+          break;
+        }
+      /* Clock not enabled for I2S*/
+      default:
+        {
+          frequency = 0U;
+          break;
+        }
+      }
+      break;
+    }
+  }
+  return frequency;
+}
+#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */
+
+#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
+/**
+  * @brief  Initializes the RCC extended peripherals clocks according to the specified parameters in the
+  *         RCC_PeriphCLKInitTypeDef.
+  * @param  PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that
+  *         contains the configuration information for the Extended Peripherals clocks(I2S and RTC clocks).
+  *
+  * @note   A caution to be taken when HAL_RCCEx_PeriphCLKConfig() is used to select RTC clock selection, in this case
+  *         the Reset of Backup domain will be applied in order to modify the RTC Clock source as consequence all backup
+  *        domain (RTC and RCC_BDCR register expect BKPSRAM) will be reset
+  *
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit)
+{
+  uint32_t tickstart = 0U;
+  uint32_t tmpreg1 = 0U;
+
+  /* Check the parameters */
+  assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
+
+  /*---------------------------- RTC configuration ---------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC))
+  {
+    /* Check for RTC Parameters used to output RTCCLK */
+    assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
+
+    /* Enable Power Clock*/
+    __HAL_RCC_PWR_CLK_ENABLE();
+
+    /* Enable write access to Backup domain */
+    PWR->CR |= PWR_CR_DBP;
+
+    /* Get tick */
+    tickstart = HAL_GetTick();
+
+    while((PWR->CR & PWR_CR_DBP) == RESET)
+    {
+      if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE)
+      {
+        return HAL_TIMEOUT;
+      }
+    }
+    /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */
+    tmpreg1 = (RCC->BDCR & RCC_BDCR_RTCSEL);
+    if((tmpreg1 != 0x00000000U) && ((tmpreg1) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)))
+    {
+      /* Store the content of BDCR register before the reset of Backup Domain */
+      tmpreg1 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
+      /* RTC Clock selection can be changed only if the Backup Domain is reset */
+      __HAL_RCC_BACKUPRESET_FORCE();
+      __HAL_RCC_BACKUPRESET_RELEASE();
+      /* Restore the Content of BDCR register */
+      RCC->BDCR = tmpreg1;
+
+      /* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */
+      if(HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSEON))
+      {
+        /* Get tick */
+        tickstart = HAL_GetTick();
+
+        /* Wait till LSE is ready */
+        while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
+        {
+          if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
+          {
+            return HAL_TIMEOUT;
+          }
+        }
+      }
+    }
+    __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
+  }
+  /*--------------------------------------------------------------------------*/
+
+  /*---------------------------- TIM configuration ---------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM))
+  {
+    __HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection);
+  }
+  /*--------------------------------------------------------------------------*/
+
+  /*---------------------------- FMPI2C1 Configuration -----------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FMPI2C1) == RCC_PERIPHCLK_FMPI2C1)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_FMPI2C1CLKSOURCE(PeriphClkInit->Fmpi2c1ClockSelection));
+
+    /* Configure the FMPI2C1 clock source */
+    __HAL_RCC_FMPI2C1_CONFIG(PeriphClkInit->Fmpi2c1ClockSelection);
+  }
+  /*--------------------------------------------------------------------------*/
+
+  /*---------------------------- LPTIM1 Configuration ------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_LPTIM1CLKSOURCE(PeriphClkInit->Lptim1ClockSelection));
+
+    /* Configure the LPTIM1 clock source */
+    __HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection);
+  }
+
+  /*---------------------------- I2S Configuration ---------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_I2SAPBCLKSOURCE(PeriphClkInit->I2SClockSelection));
+
+    /* Configure the I2S clock source */
+    __HAL_RCC_I2S_CONFIG(PeriphClkInit->I2SClockSelection);
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Configures the RCC_OscInitStruct according to the internal
+  * RCC configuration registers.
+  * @param  PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that
+  * will be configured.
+  * @retval None
+  */
+void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit)
+{
+  uint32_t tempreg;
+
+  /* Set all possible values for the extended clock type parameter------------*/
+  PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_FMPI2C1 | RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_TIM | RCC_PERIPHCLK_RTC;
+
+  tempreg = (RCC->CFGR & RCC_CFGR_RTCPRE);
+  PeriphClkInit->RTCClockSelection = (uint32_t)((tempreg) | (RCC->BDCR & RCC_BDCR_RTCSEL));
+
+  if ((RCC->DCKCFGR & RCC_DCKCFGR_TIMPRE) == RESET)
+  {
+    PeriphClkInit->TIMPresSelection = RCC_TIMPRES_DESACTIVATED;
+  }
+  else
+  {
+    PeriphClkInit->TIMPresSelection = RCC_TIMPRES_ACTIVATED;
+  }
+  /* Get the FMPI2C1 clock configuration -------------------------------------*/
+  PeriphClkInit->Fmpi2c1ClockSelection = __HAL_RCC_GET_FMPI2C1_SOURCE();
+
+  /* Get the I2S clock configuration -----------------------------------------*/
+  PeriphClkInit->I2SClockSelection = __HAL_RCC_GET_I2S_SOURCE();
+
+
+}
+/**
+  * @brief  Return the peripheral clock frequency for a given peripheral(SAI..)
+  * @note   Return 0 if peripheral clock identifier not managed by this API
+  * @param  PeriphClk Peripheral clock identifier
+  *         This parameter can be one of the following values:
+  *            @arg RCC_PERIPHCLK_I2S: I2S peripheral clock
+  * @retval Frequency in KHz
+  */
+uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
+{
+  /* This variable used to store the I2S clock frequency (value in Hz) */
+  uint32_t frequency = 0U;
+  /* This variable used to store the VCO Input (value in Hz) */
+  uint32_t vcoinput = 0U;
+  uint32_t srcclk = 0U;
+  /* This variable used to store the VCO Output (value in Hz) */
+  uint32_t vcooutput = 0U;
+  switch (PeriphClk)
+  {
+  case RCC_PERIPHCLK_I2S:
+    {
+      /* Get the current I2S source */
+      srcclk = __HAL_RCC_GET_I2S_SOURCE();
+      switch (srcclk)
+      {
+      /* Check if I2S clock selection is External clock mapped on the I2S_CKIN pin used as I2S clock */
+      case RCC_I2SAPBCLKSOURCE_EXT:
+        {
+          /* Set the I2S clock to the external clock  value */
+          frequency = EXTERNAL_CLOCK_VALUE;
+          break;
+        }
+      /* Check if I2S clock selection is PLL VCO Output divided by PLLR used as I2S clock */
+      case RCC_I2SAPBCLKSOURCE_PLLR:
+        {
+          /* Configure the PLL division factor R */
+          /* PLL_VCO Input  = PLL_SOURCE/PLLM */
+          if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE)
+          {
+            /* Get the I2S source clock value */
+            vcoinput = (uint32_t)(HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
+          }
+          else
+          {
+            /* Get the I2S source clock value */
+            vcoinput = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
+          }
+
+          /* PLL_VCO Output = PLL_VCO Input * PLLN */
+          vcooutput = (uint32_t)(vcoinput * (((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6U) & (RCC_PLLCFGR_PLLN >> 6U)));
+          /* I2S_CLK = PLL_VCO Output/PLLR */
+          frequency = (uint32_t)(vcooutput /(((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> 28U) & (RCC_PLLCFGR_PLLR >> 28U)));
+          break;
+        }
+      /* Check if I2S clock selection is HSI or HSE depending from PLL source Clock */
+      case RCC_I2SAPBCLKSOURCE_PLLSRC:
+        {
+          if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE)
+          {
+            frequency = HSE_VALUE;
+          }
+          else
+          {
+            frequency = HSI_VALUE;
+          }
+          break;
+        }
+        /* Clock not enabled for I2S*/
+      default:
+        {
+          frequency = 0U;
+          break;
+        }
+      }
+      break;
+    }
+  }
+  return frequency;
+}
+#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
+/**
+  * @brief  Initializes the RCC extended peripherals clocks according to the specified
+  *         parameters in the RCC_PeriphCLKInitTypeDef.
+  * @param  PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that
+  *         contains the configuration information for the Extended Peripherals
+  *         clocks(I2S, SAI, LTDC RTC and TIM).
+  *
+  * @note   Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select
+  *         the RTC clock source; in this case the Backup domain will be reset in
+  *         order to modify the RTC Clock source, as consequence RTC registers (including
+  *         the backup registers) and RCC_BDCR register are set to their reset values.
+  *
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit)
+{
+  uint32_t tickstart = 0U;
+  uint32_t tmpreg1 = 0U;
+
+  /* Check the parameters */
+  assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
+
+  /*----------------------- SAI/I2S Configuration (PLLI2S) -------------------*/
+  /*----------------------- Common configuration SAI/I2S ---------------------*/
+  /* In Case of SAI or I2S Clock Configuration through PLLI2S, PLLI2SN division
+     factor is common parameters for both peripherals */
+  if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) ||
+     (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLI2S) == RCC_PERIPHCLK_SAI_PLLI2S) ||
+     (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S))
+  {
+    /* check for Parameters */
+    assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN));
+
+    /* Disable the PLLI2S */
+    __HAL_RCC_PLLI2S_DISABLE();
+    /* Get tick */
+    tickstart = HAL_GetTick();
+    /* Wait till PLLI2S is disabled */
+    while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY)  != RESET)
+    {
+      if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
+      {
+        /* return in case of Timeout detected */
+        return HAL_TIMEOUT;
+      }
+    }
+
+    /*---------------------------- I2S configuration -------------------------*/
+    /* In Case of I2S Clock Configuration through PLLI2S, PLLI2SR must be added
+      only for I2S configuration */
+    if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == (RCC_PERIPHCLK_I2S))
+    {
+      /* check for Parameters */
+      assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));
+      /* Configure the PLLI2S division factors */
+      /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLM) */
+      /* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */
+      __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SR);
+    }
+
+    /*---------------------------- SAI configuration -------------------------*/
+    /* In Case of SAI Clock Configuration through PLLI2S, PLLI2SQ and PLLI2S_DIVQ must
+       be added only for SAI configuration */
+    if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLI2S) == (RCC_PERIPHCLK_SAI_PLLI2S))
+    {
+      /* Check the PLLI2S division factors */
+      assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ));
+      assert_param(IS_RCC_PLLI2S_DIVQ_VALUE(PeriphClkInit->PLLI2SDivQ));
+
+      /* Read PLLI2SR value from PLLI2SCFGR register (this value is not need for SAI configuration) */
+      tmpreg1 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos);
+      /* Configure the PLLI2S division factors */
+      /* PLLI2S_VCO Input  = PLL_SOURCE/PLLM */
+      /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
+      /* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */
+      __HAL_RCC_PLLI2S_SAICLK_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SQ , tmpreg1);
+      /* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */
+      __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLI2SDivQ);
+    }
+
+    /*----------------- In Case of PLLI2S is just selected  -----------------*/
+    if((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S)
+    {
+      /* Check for Parameters */
+      assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ));
+      assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));
+
+      /* Configure the PLLI2S multiplication and division factors */
+      __HAL_RCC_PLLI2S_SAICLK_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN, PeriphClkInit->PLLI2S.PLLI2SQ, PeriphClkInit->PLLI2S.PLLI2SR);
+    }
+
+    /* Enable the PLLI2S */
+    __HAL_RCC_PLLI2S_ENABLE();
+    /* Get tick */
+    tickstart = HAL_GetTick();
+    /* Wait till PLLI2S is ready */
+    while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY)  == RESET)
+    {
+      if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
+      {
+        /* return in case of Timeout detected */
+        return HAL_TIMEOUT;
+      }
+    }
+  }
+  /*--------------------------------------------------------------------------*/
+
+  /*----------------------- SAI/LTDC Configuration (PLLSAI) ------------------*/
+  /*----------------------- Common configuration SAI/LTDC --------------------*/
+  /* In Case of SAI or LTDC Clock Configuration through PLLSAI, PLLSAIN division
+     factor is common parameters for both peripherals */
+  if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLSAI) == RCC_PERIPHCLK_SAI_PLLSAI) ||
+     (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC))
+  {
+    /* Check the PLLSAI division factors */
+    assert_param(IS_RCC_PLLSAIN_VALUE(PeriphClkInit->PLLSAI.PLLSAIN));
+
+    /* Disable PLLSAI Clock */
+    __HAL_RCC_PLLSAI_DISABLE();
+    /* Get tick */
+    tickstart = HAL_GetTick();
+    /* Wait till PLLSAI is disabled */
+    while(__HAL_RCC_PLLSAI_GET_FLAG() != RESET)
+    {
+      if((HAL_GetTick() - tickstart ) > PLLSAI_TIMEOUT_VALUE)
+      {
+        /* return in case of Timeout detected */
+        return HAL_TIMEOUT;
+      }
+    }
+
+    /*---------------------------- SAI configuration -------------------------*/
+    /* In Case of SAI Clock Configuration through PLLSAI, PLLSAIQ and PLLSAI_DIVQ must
+       be added only for SAI configuration */
+    if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLSAI) == (RCC_PERIPHCLK_SAI_PLLSAI))
+    {
+      assert_param(IS_RCC_PLLSAIQ_VALUE(PeriphClkInit->PLLSAI.PLLSAIQ));
+      assert_param(IS_RCC_PLLSAI_DIVQ_VALUE(PeriphClkInit->PLLSAIDivQ));
+
+      /* Read PLLSAIR value from PLLSAICFGR register (this value is not need for SAI configuration) */
+      tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> RCC_PLLSAICFGR_PLLSAIR_Pos);
+      /* PLLSAI_VCO Input  = PLL_SOURCE/PLLM */
+      /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
+      /* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */
+      __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , PeriphClkInit->PLLSAI.PLLSAIQ, tmpreg1);
+      /* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */
+      __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLSAIDivQ);
+    }
+
+    /*---------------------------- LTDC configuration ------------------------*/
+    if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == (RCC_PERIPHCLK_LTDC))
+    {
+      assert_param(IS_RCC_PLLSAIR_VALUE(PeriphClkInit->PLLSAI.PLLSAIR));
+      assert_param(IS_RCC_PLLSAI_DIVR_VALUE(PeriphClkInit->PLLSAIDivR));
+
+      /* Read PLLSAIR value from PLLSAICFGR register (this value is not need for SAI configuration) */
+      tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos);
+      /* PLLSAI_VCO Input  = PLL_SOURCE/PLLM */
+      /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
+      /* LTDC_CLK(first level) = PLLSAI_VCO Output/PLLSAIR */
+      __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , tmpreg1, PeriphClkInit->PLLSAI.PLLSAIR);
+      /* LTDC_CLK = LTDC_CLK(first level)/PLLSAIDIVR */
+      __HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG(PeriphClkInit->PLLSAIDivR);
+    }
+    /* Enable PLLSAI Clock */
+    __HAL_RCC_PLLSAI_ENABLE();
+    /* Get tick */
+    tickstart = HAL_GetTick();
+    /* Wait till PLLSAI is ready */
+    while(__HAL_RCC_PLLSAI_GET_FLAG() == RESET)
+    {
+      if((HAL_GetTick() - tickstart ) > PLLSAI_TIMEOUT_VALUE)
+      {
+        /* return in case of Timeout detected */
+        return HAL_TIMEOUT;
+      }
+    }
+  }
+  /*--------------------------------------------------------------------------*/
+
+  /*---------------------------- RTC configuration ---------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC))
+  {
+    /* Check for RTC Parameters used to output RTCCLK */
+    assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
+
+    /* Enable Power Clock*/
+    __HAL_RCC_PWR_CLK_ENABLE();
+
+    /* Enable write access to Backup domain */
+    PWR->CR |= PWR_CR_DBP;
+
+    /* Get tick */
+    tickstart = HAL_GetTick();
+
+    while((PWR->CR & PWR_CR_DBP) == RESET)
+    {
+      if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE)
+      {
+        return HAL_TIMEOUT;
+      }
+    }
+    /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */
+    tmpreg1 = (RCC->BDCR & RCC_BDCR_RTCSEL);
+    if((tmpreg1 != 0x00000000U) && ((tmpreg1) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)))
+    {
+      /* Store the content of BDCR register before the reset of Backup Domain */
+      tmpreg1 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
+      /* RTC Clock selection can be changed only if the Backup Domain is reset */
+      __HAL_RCC_BACKUPRESET_FORCE();
+      __HAL_RCC_BACKUPRESET_RELEASE();
+      /* Restore the Content of BDCR register */
+      RCC->BDCR = tmpreg1;
+
+      /* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */
+      if(HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSEON))
+      {
+        /* Get tick */
+        tickstart = HAL_GetTick();
+
+        /* Wait till LSE is ready */
+        while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
+        {
+          if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
+          {
+            return HAL_TIMEOUT;
+          }
+        }
+      }
+    }
+    __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
+  }
+  /*--------------------------------------------------------------------------*/
+
+  /*---------------------------- TIM configuration ---------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM))
+  {
+    __HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection);
+  }
+  return HAL_OK;
+}
+
+/**
+  * @brief  Configures the PeriphClkInit according to the internal
+  * RCC configuration registers.
+  * @param  PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that
+  *         will be configured.
+  * @retval None
+  */
+void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit)
+{
+  uint32_t tempreg;
+
+  /* Set all possible values for the extended clock type parameter------------*/
+  PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_I2S | RCC_PERIPHCLK_SAI_PLLSAI | RCC_PERIPHCLK_SAI_PLLI2S | RCC_PERIPHCLK_LTDC | RCC_PERIPHCLK_TIM | RCC_PERIPHCLK_RTC;
+
+  /* Get the PLLI2S Clock configuration -----------------------------------------------*/
+  PeriphClkInit->PLLI2S.PLLI2SN = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> RCC_PLLI2SCFGR_PLLI2SN_Pos);
+  PeriphClkInit->PLLI2S.PLLI2SR = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos);
+  PeriphClkInit->PLLI2S.PLLI2SQ = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos);
+  /* Get the PLLSAI Clock configuration -----------------------------------------------*/
+  PeriphClkInit->PLLSAI.PLLSAIN = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> RCC_PLLSAICFGR_PLLSAIN_Pos);
+  PeriphClkInit->PLLSAI.PLLSAIR = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> RCC_PLLSAICFGR_PLLSAIR_Pos);
+  PeriphClkInit->PLLSAI.PLLSAIQ = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos);
+  /* Get the PLLSAI/PLLI2S division factors -----------------------------------------------*/
+  PeriphClkInit->PLLI2SDivQ = (uint32_t)((RCC->DCKCFGR & RCC_DCKCFGR_PLLI2SDIVQ) >> RCC_DCKCFGR_PLLI2SDIVQ_Pos);
+  PeriphClkInit->PLLSAIDivQ = (uint32_t)((RCC->DCKCFGR & RCC_DCKCFGR_PLLSAIDIVQ) >> RCC_DCKCFGR_PLLSAIDIVQ_Pos);
+  PeriphClkInit->PLLSAIDivR = (uint32_t)(RCC->DCKCFGR & RCC_DCKCFGR_PLLSAIDIVR);
+  /* Get the RTC Clock configuration -----------------------------------------------*/
+  tempreg = (RCC->CFGR & RCC_CFGR_RTCPRE);
+  PeriphClkInit->RTCClockSelection = (uint32_t)((tempreg) | (RCC->BDCR & RCC_BDCR_RTCSEL));
+
+  if ((RCC->DCKCFGR & RCC_DCKCFGR_TIMPRE) == RESET)
+  {
+    PeriphClkInit->TIMPresSelection = RCC_TIMPRES_DESACTIVATED;
+  }
+  else
+  {
+    PeriphClkInit->TIMPresSelection = RCC_TIMPRES_ACTIVATED;
+  }
+}
+
+/**
+  * @brief  Return the peripheral clock frequency for a given peripheral(SAI..)
+  * @note   Return 0 if peripheral clock identifier not managed by this API
+  * @param  PeriphClk Peripheral clock identifier
+  *         This parameter can be one of the following values:
+  *            @arg RCC_PERIPHCLK_I2S: I2S peripheral clock
+  * @retval Frequency in KHz
+  */
+uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
+{
+  /* This variable used to store the I2S clock frequency (value in Hz) */
+  uint32_t frequency = 0U;
+  /* This variable used to store the VCO Input (value in Hz) */
+  uint32_t vcoinput = 0U;
+  uint32_t srcclk = 0U;
+  /* This variable used to store the VCO Output (value in Hz) */
+  uint32_t vcooutput = 0U;
+  switch (PeriphClk)
+  {
+  case RCC_PERIPHCLK_I2S:
+    {
+      /* Get the current I2S source */
+      srcclk = __HAL_RCC_GET_I2S_SOURCE();
+      switch (srcclk)
+      {
+      /* Check if I2S clock selection is External clock mapped on the I2S_CKIN pin used as I2S clock */
+      case RCC_I2SCLKSOURCE_EXT:
+        {
+          /* Set the I2S clock to the external clock  value */
+          frequency = EXTERNAL_CLOCK_VALUE;
+          break;
+        }
+      /* Check if I2S clock selection is PLLI2S VCO output clock divided by PLLI2SR used as I2S clock */
+      case RCC_I2SCLKSOURCE_PLLI2S:
+        {
+          /* Configure the PLLI2S division factor */
+          /* PLLI2S_VCO Input  = PLL_SOURCE/PLLM */
+          if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE)
+          {
+            /* Get the I2S source clock value */
+            vcoinput = (uint32_t)(HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
+          }
+          else
+          {
+            /* Get the I2S source clock value */
+            vcoinput = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
+          }
+
+          /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
+          vcooutput = (uint32_t)(vcoinput * (((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6U) & (RCC_PLLI2SCFGR_PLLI2SN >> 6U)));
+          /* I2S_CLK = PLLI2S_VCO Output/PLLI2SR */
+          frequency = (uint32_t)(vcooutput /(((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> 28U) & (RCC_PLLI2SCFGR_PLLI2SR >> 28U)));
+          break;
+        }
+        /* Clock not enabled for I2S*/
+      default:
+        {
+          frequency = 0U;
+          break;
+        }
+      }
+      break;
+    }
+  }
+  return frequency;
+}
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx) ||\
+    defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE)
+/**
+  * @brief  Initializes the RCC extended peripherals clocks according to the specified parameters in the
+  *         RCC_PeriphCLKInitTypeDef.
+  * @param  PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that
+  *         contains the configuration information for the Extended Peripherals clocks(I2S and RTC clocks).
+  *
+  * @note   A caution to be taken when HAL_RCCEx_PeriphCLKConfig() is used to select RTC clock selection, in this case
+  *         the Reset of Backup domain will be applied in order to modify the RTC Clock source as consequence all backup
+  *        domain (RTC and RCC_BDCR register expect BKPSRAM) will be reset
+  *
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit)
+{
+  uint32_t tickstart = 0U;
+  uint32_t tmpreg1 = 0U;
+
+  /* Check the parameters */
+  assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
+
+  /*---------------------------- I2S configuration ---------------------------*/
+  if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) ||
+     (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S))
+  {
+    /* check for Parameters */
+    assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));
+    assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN));
+#if defined(STM32F411xE)
+    assert_param(IS_RCC_PLLI2SM_VALUE(PeriphClkInit->PLLI2S.PLLI2SM));
+#endif /* STM32F411xE */
+    /* Disable the PLLI2S */
+    __HAL_RCC_PLLI2S_DISABLE();
+    /* Get tick */
+    tickstart = HAL_GetTick();
+    /* Wait till PLLI2S is disabled */
+    while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY)  != RESET)
+    {
+      if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
+      {
+        /* return in case of Timeout detected */
+        return HAL_TIMEOUT;
+      }
+    }
+
+#if defined(STM32F411xE)
+    /* Configure the PLLI2S division factors */
+    /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLI2SM) */
+    /* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */
+    __HAL_RCC_PLLI2S_I2SCLK_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN, PeriphClkInit->PLLI2S.PLLI2SR);
+#else
+    /* Configure the PLLI2S division factors */
+    /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLM) */
+    /* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */
+    __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SR);
+#endif /* STM32F411xE */
+
+    /* Enable the PLLI2S */
+    __HAL_RCC_PLLI2S_ENABLE();
+    /* Get tick */
+    tickstart = HAL_GetTick();
+    /* Wait till PLLI2S is ready */
+    while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY)  == RESET)
+    {
+      if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
+      {
+        /* return in case of Timeout detected */
+        return HAL_TIMEOUT;
+      }
+    }
+  }
+
+  /*---------------------------- RTC configuration ---------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC))
+  {
+    /* Check for RTC Parameters used to output RTCCLK */
+    assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
+
+    /* Enable Power Clock*/
+    __HAL_RCC_PWR_CLK_ENABLE();
+
+    /* Enable write access to Backup domain */
+    PWR->CR |= PWR_CR_DBP;
+
+    /* Get tick */
+    tickstart = HAL_GetTick();
+
+    while((PWR->CR & PWR_CR_DBP) == RESET)
+    {
+      if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE)
+      {
+        return HAL_TIMEOUT;
+      }
+    }
+    /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */
+    tmpreg1 = (RCC->BDCR & RCC_BDCR_RTCSEL);
+    if((tmpreg1 != 0x00000000U) && ((tmpreg1) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)))
+    {
+      /* Store the content of BDCR register before the reset of Backup Domain */
+      tmpreg1 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
+      /* RTC Clock selection can be changed only if the Backup Domain is reset */
+      __HAL_RCC_BACKUPRESET_FORCE();
+      __HAL_RCC_BACKUPRESET_RELEASE();
+      /* Restore the Content of BDCR register */
+      RCC->BDCR = tmpreg1;
+
+      /* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */
+      if(HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSEON))
+      {
+        /* Get tick */
+        tickstart = HAL_GetTick();
+
+        /* Wait till LSE is ready */
+        while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
+        {
+          if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
+          {
+            return HAL_TIMEOUT;
+          }
+        }
+      }
+    }
+    __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
+  }
+#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE)
+  /*---------------------------- TIM configuration ---------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM))
+  {
+    __HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection);
+  }
+#endif /* STM32F401xC || STM32F401xE || STM32F411xE */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Configures the RCC_OscInitStruct according to the internal
+  * RCC configuration registers.
+  * @param  PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that
+  * will be configured.
+  * @retval None
+  */
+void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit)
+{
+  uint32_t tempreg;
+
+  /* Set all possible values for the extended clock type parameter------------*/
+  PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_I2S | RCC_PERIPHCLK_RTC;
+
+  /* Get the PLLI2S Clock configuration --------------------------------------*/
+  PeriphClkInit->PLLI2S.PLLI2SN = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> RCC_PLLI2SCFGR_PLLI2SN_Pos);
+  PeriphClkInit->PLLI2S.PLLI2SR = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos);
+#if defined(STM32F411xE)
+  PeriphClkInit->PLLI2S.PLLI2SM = (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM);
+#endif /* STM32F411xE */
+  /* Get the RTC Clock configuration -----------------------------------------*/
+  tempreg = (RCC->CFGR & RCC_CFGR_RTCPRE);
+  PeriphClkInit->RTCClockSelection = (uint32_t)((tempreg) | (RCC->BDCR & RCC_BDCR_RTCSEL));
+
+#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE)
+  /* Get the TIM Prescaler configuration -------------------------------------*/
+  if ((RCC->DCKCFGR & RCC_DCKCFGR_TIMPRE) == RESET)
+  {
+    PeriphClkInit->TIMPresSelection = RCC_TIMPRES_DESACTIVATED;
+  }
+  else
+  {
+    PeriphClkInit->TIMPresSelection = RCC_TIMPRES_ACTIVATED;
+  }
+#endif /* STM32F401xC || STM32F401xE || STM32F411xE */
+}
+
+/**
+  * @brief  Return the peripheral clock frequency for a given peripheral(SAI..)
+  * @note   Return 0 if peripheral clock identifier not managed by this API
+  * @param  PeriphClk Peripheral clock identifier
+  *         This parameter can be one of the following values:
+  *            @arg RCC_PERIPHCLK_I2S: I2S peripheral clock
+  * @retval Frequency in KHz
+  */
+uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
+{
+  /* This variable used to store the I2S clock frequency (value in Hz) */
+  uint32_t frequency = 0U;
+  /* This variable used to store the VCO Input (value in Hz) */
+  uint32_t vcoinput = 0U;
+  uint32_t srcclk = 0U;
+  /* This variable used to store the VCO Output (value in Hz) */
+  uint32_t vcooutput = 0U;
+  switch (PeriphClk)
+  {
+  case RCC_PERIPHCLK_I2S:
+    {
+      /* Get the current I2S source */
+      srcclk = __HAL_RCC_GET_I2S_SOURCE();
+      switch (srcclk)
+      {
+      /* Check if I2S clock selection is External clock mapped on the I2S_CKIN pin used as I2S clock */
+      case RCC_I2SCLKSOURCE_EXT:
+        {
+          /* Set the I2S clock to the external clock  value */
+          frequency = EXTERNAL_CLOCK_VALUE;
+          break;
+        }
+      /* Check if I2S clock selection is PLLI2S VCO output clock divided by PLLI2SR used as I2S clock */
+      case RCC_I2SCLKSOURCE_PLLI2S:
+        {
+#if defined(STM32F411xE)
+          /* Configure the PLLI2S division factor */
+          /* PLLI2S_VCO Input  = PLL_SOURCE/PLLI2SM */
+          if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE)
+          {
+            /* Get the I2S source clock value */
+            vcoinput = (uint32_t)(HSE_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM));
+          }
+          else
+          {
+            /* Get the I2S source clock value */
+            vcoinput = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM));
+          }
+#else
+          /* Configure the PLLI2S division factor */
+          /* PLLI2S_VCO Input  = PLL_SOURCE/PLLM */
+          if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE)
+          {
+            /* Get the I2S source clock value */
+            vcoinput = (uint32_t)(HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
+          }
+          else
+          {
+            /* Get the I2S source clock value */
+            vcoinput = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
+          }
+#endif /* STM32F411xE */
+          /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
+          vcooutput = (uint32_t)(vcoinput * (((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6U) & (RCC_PLLI2SCFGR_PLLI2SN >> 6U)));
+          /* I2S_CLK = PLLI2S_VCO Output/PLLI2SR */
+          frequency = (uint32_t)(vcooutput /(((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> 28U) & (RCC_PLLI2SCFGR_PLLI2SR >> 28U)));
+          break;
+        }
+        /* Clock not enabled for I2S*/
+      default:
+        {
+          frequency = 0U;
+          break;
+        }
+      }
+      break;
+    }
+  }
+  return frequency;
+}
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE  || STM32F411xE */
+
+#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) ||\
+    defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
+/**
+  * @brief  Select LSE mode
+  *
+  * @note   This mode is only available for STM32F410xx/STM32F411xx/STM32F446xx/STM32F469xx/STM32F479xx/STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx  devices.
+  *
+  * @param  Mode specifies the LSE mode.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_LSE_LOWPOWER_MODE:  LSE oscillator in low power mode selection
+  *            @arg RCC_LSE_HIGHDRIVE_MODE: LSE oscillator in High Drive mode selection
+  * @retval None
+  */
+void HAL_RCCEx_SelectLSEMode(uint8_t Mode)
+{
+  /* Check the parameters */
+  assert_param(IS_RCC_LSE_MODE(Mode));
+  if(Mode == RCC_LSE_HIGHDRIVE_MODE)
+  {
+    SET_BIT(RCC->BDCR, RCC_BDCR_LSEMOD);
+  }
+  else
+  {
+    CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEMOD);
+  }
+}
+
+#endif /* STM32F410xx || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */
+
+/** @defgroup RCCEx_Exported_Functions_Group2 Extended Clock management functions
+ *  @brief  Extended Clock management functions
+ *
+@verbatim   
+ ===============================================================================
+                ##### Extended clock management functions  #####
+ ===============================================================================
+    [..]
+    This subsection provides a set of functions allowing to control the 
+    activation or deactivation of PLLI2S, PLLSAI.
+@endverbatim
+  * @{
+  */
+
+#if defined(RCC_PLLI2S_SUPPORT)
+/**
+  * @brief  Enable PLLI2S.
+  * @param  PLLI2SInit  pointer to an RCC_PLLI2SInitTypeDef structure that
+  *         contains the configuration information for the PLLI2S
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RCCEx_EnablePLLI2S(RCC_PLLI2SInitTypeDef  *PLLI2SInit)
+{
+  uint32_t tickstart;
+
+  /* Check for parameters */
+  assert_param(IS_RCC_PLLI2SN_VALUE(PLLI2SInit->PLLI2SN));
+  assert_param(IS_RCC_PLLI2SR_VALUE(PLLI2SInit->PLLI2SR));
+#if defined(RCC_PLLI2SCFGR_PLLI2SM)
+  assert_param(IS_RCC_PLLI2SM_VALUE(PLLI2SInit->PLLI2SM));
+#endif /* RCC_PLLI2SCFGR_PLLI2SM */
+#if defined(RCC_PLLI2SCFGR_PLLI2SP)
+  assert_param(IS_RCC_PLLI2SP_VALUE(PLLI2SInit->PLLI2SP));
+#endif /* RCC_PLLI2SCFGR_PLLI2SP */
+#if defined(RCC_PLLI2SCFGR_PLLI2SQ)
+  assert_param(IS_RCC_PLLI2SQ_VALUE(PLLI2SInit->PLLI2SQ));
+#endif /* RCC_PLLI2SCFGR_PLLI2SQ */
+
+  /* Disable the PLLI2S */
+  __HAL_RCC_PLLI2S_DISABLE();
+
+  /* Wait till PLLI2S is disabled */
+  tickstart = HAL_GetTick();
+  while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET)
+  {
+    if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
+    {
+      /* return in case of Timeout detected */
+      return HAL_TIMEOUT;
+    }
+  }
+
+  /* Configure the PLLI2S division factors */
+#if defined(STM32F446xx)
+  /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLI2SM) */
+  /* I2SPCLK = PLLI2S_VCO / PLLI2SP */
+  /* I2SQCLK = PLLI2S_VCO / PLLI2SQ */
+  /* I2SRCLK = PLLI2S_VCO / PLLI2SR */
+  __HAL_RCC_PLLI2S_CONFIG(PLLI2SInit->PLLI2SM, PLLI2SInit->PLLI2SN, \
+                          PLLI2SInit->PLLI2SP, PLLI2SInit->PLLI2SQ, PLLI2SInit->PLLI2SR);
+#elif defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) ||\
+      defined(STM32F413xx) || defined(STM32F423xx)
+  /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLI2SM)*/
+  /* I2SQCLK = PLLI2S_VCO / PLLI2SQ */
+  /* I2SRCLK = PLLI2S_VCO / PLLI2SR */
+  __HAL_RCC_PLLI2S_CONFIG(PLLI2SInit->PLLI2SM, PLLI2SInit->PLLI2SN, \
+                          PLLI2SInit->PLLI2SQ, PLLI2SInit->PLLI2SR);
+#elif defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
+      defined(STM32F469xx) || defined(STM32F479xx)
+  /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * PLLI2SN */
+  /* I2SQCLK = PLLI2S_VCO / PLLI2SQ */
+  /* I2SRCLK = PLLI2S_VCO / PLLI2SR */
+  __HAL_RCC_PLLI2S_SAICLK_CONFIG(PLLI2SInit->PLLI2SN, PLLI2SInit->PLLI2SQ, PLLI2SInit->PLLI2SR);
+#elif defined(STM32F411xE)
+  /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLI2SM) */
+  /* I2SRCLK = PLLI2S_VCO / PLLI2SR */
+  __HAL_RCC_PLLI2S_I2SCLK_CONFIG(PLLI2SInit->PLLI2SM, PLLI2SInit->PLLI2SN, PLLI2SInit->PLLI2SR);
+#else
+  /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) x PLLI2SN */
+  /* I2SRCLK = PLLI2S_VCO / PLLI2SR */
+  __HAL_RCC_PLLI2S_CONFIG(PLLI2SInit->PLLI2SN, PLLI2SInit->PLLI2SR);
+#endif /* STM32F446xx */
+
+  /* Enable the PLLI2S */
+  __HAL_RCC_PLLI2S_ENABLE();
+
+  /* Wait till PLLI2S is ready */
+  tickstart = HAL_GetTick();
+  while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET)
+  {
+    if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
+    {
+      /* return in case of Timeout detected */
+      return HAL_TIMEOUT;
+    }
+  }
+
+ return HAL_OK;
+}
+
+/**
+  * @brief  Disable PLLI2S.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RCCEx_DisablePLLI2S(void)
+{
+  uint32_t tickstart;
+
+  /* Disable the PLLI2S */
+  __HAL_RCC_PLLI2S_DISABLE();
+
+  /* Wait till PLLI2S is disabled */
+  tickstart = HAL_GetTick();
+  while(READ_BIT(RCC->CR, RCC_CR_PLLI2SRDY) != RESET)
+  {
+    if((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE)
+    {
+      /* return in case of Timeout detected */
+      return HAL_TIMEOUT;
+    }
+  }
+
+  return HAL_OK;
+}
+
+#endif /* RCC_PLLI2S_SUPPORT */
+
+#if defined(RCC_PLLSAI_SUPPORT)
+/**
+  * @brief  Enable PLLSAI.
+  * @param  PLLSAIInit  pointer to an RCC_PLLSAIInitTypeDef structure that
+  *         contains the configuration information for the PLLSAI
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RCCEx_EnablePLLSAI(RCC_PLLSAIInitTypeDef  *PLLSAIInit)
+{
+  uint32_t tickstart;
+
+  /* Check for parameters */
+  assert_param(IS_RCC_PLLSAIN_VALUE(PLLSAIInit->PLLSAIN));
+  assert_param(IS_RCC_PLLSAIQ_VALUE(PLLSAIInit->PLLSAIQ));
+#if defined(RCC_PLLSAICFGR_PLLSAIM)
+  assert_param(IS_RCC_PLLSAIM_VALUE(PLLSAIInit->PLLSAIM));
+#endif /* RCC_PLLSAICFGR_PLLSAIM */
+#if defined(RCC_PLLSAICFGR_PLLSAIP)
+  assert_param(IS_RCC_PLLSAIP_VALUE(PLLSAIInit->PLLSAIP));
+#endif /* RCC_PLLSAICFGR_PLLSAIP */
+#if defined(RCC_PLLSAICFGR_PLLSAIR)
+  assert_param(IS_RCC_PLLSAIR_VALUE(PLLSAIInit->PLLSAIR));
+#endif /* RCC_PLLSAICFGR_PLLSAIR */
+
+  /* Disable the PLLSAI */
+  __HAL_RCC_PLLSAI_DISABLE();
+
+  /* Wait till PLLSAI is disabled */
+  tickstart = HAL_GetTick();
+  while(__HAL_RCC_PLLSAI_GET_FLAG() != RESET)
+  {
+    if((HAL_GetTick() - tickstart ) > PLLSAI_TIMEOUT_VALUE)
+    {
+      /* return in case of Timeout detected */
+      return HAL_TIMEOUT;
+    }
+  }
+
+  /* Configure the PLLSAI division factors */
+#if defined(STM32F446xx)
+  /* PLLSAI_VCO = f(VCO clock) = f(PLLSAI clock input) * (PLLSAIN/PLLSAIM) */
+  /* SAIPCLK = PLLSAI_VCO / PLLSAIP */
+  /* SAIQCLK = PLLSAI_VCO / PLLSAIQ */
+  /* SAIRCLK = PLLSAI_VCO / PLLSAIR */
+  __HAL_RCC_PLLSAI_CONFIG(PLLSAIInit->PLLSAIM, PLLSAIInit->PLLSAIN, \
+                          PLLSAIInit->PLLSAIP, PLLSAIInit->PLLSAIQ, 0U);
+#elif defined(STM32F469xx) || defined(STM32F479xx)
+  /* PLLSAI_VCO = f(VCO clock) = f(PLLSAI clock input) * PLLSAIN */
+  /* SAIPCLK = PLLSAI_VCO / PLLSAIP */
+  /* SAIQCLK = PLLSAI_VCO / PLLSAIQ */
+  /* SAIRCLK = PLLSAI_VCO / PLLSAIR */
+  __HAL_RCC_PLLSAI_CONFIG(PLLSAIInit->PLLSAIN, PLLSAIInit->PLLSAIP, \
+                          PLLSAIInit->PLLSAIQ, PLLSAIInit->PLLSAIR);
+#else
+  /* PLLSAI_VCO = f(VCO clock) = f(PLLSAI clock input) x PLLSAIN */
+  /* SAIQCLK = PLLSAI_VCO / PLLSAIQ */
+  /* SAIRCLK = PLLSAI_VCO / PLLSAIR */
+  __HAL_RCC_PLLSAI_CONFIG(PLLSAIInit->PLLSAIN, PLLSAIInit->PLLSAIQ, PLLSAIInit->PLLSAIR);
+#endif /* STM32F446xx */
+
+  /* Enable the PLLSAI */
+  __HAL_RCC_PLLSAI_ENABLE();
+
+  /* Wait till PLLSAI is ready */
+  tickstart = HAL_GetTick();
+  while(__HAL_RCC_PLLSAI_GET_FLAG() == RESET)
+  {
+    if((HAL_GetTick() - tickstart ) > PLLSAI_TIMEOUT_VALUE)
+    {
+      /* return in case of Timeout detected */
+      return HAL_TIMEOUT;
+    }
+  }
+
+ return HAL_OK;
+}
+
+/**
+  * @brief  Disable PLLSAI.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI(void)
+{
+  uint32_t tickstart;
+
+  /* Disable the PLLSAI */
+  __HAL_RCC_PLLSAI_DISABLE();
+
+  /* Wait till PLLSAI is disabled */
+  tickstart = HAL_GetTick();
+  while(__HAL_RCC_PLLSAI_GET_FLAG() != RESET)
+  {
+    if((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE)
+    {
+      /* return in case of Timeout detected */
+      return HAL_TIMEOUT;
+    }
+  }
+
+  return HAL_OK;
+}
+
+#endif /* RCC_PLLSAI_SUPPORT */
+
+/**
+  * @}
+  */
+
+#if defined(STM32F446xx)
+/**
+  * @brief  Returns the SYSCLK frequency
+  *
+  * @note   This function implementation is valid only for STM32F446xx devices.
+  * @note   This function add the PLL/PLLR System clock source
+  *
+  * @note   The system frequency computed by this function is not the real
+  *         frequency in the chip. It is calculated based on the predefined
+  *         constant and the selected clock source:
+  * @note     If SYSCLK source is HSI, function returns values based on HSI_VALUE(*)
+  * @note     If SYSCLK source is HSE, function returns values based on HSE_VALUE(**)
+  * @note     If SYSCLK source is PLL or PLLR, function returns values based on HSE_VALUE(**)
+  *           or HSI_VALUE(*) multiplied/divided by the PLL factors.
+  * @note     (*) HSI_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value
+  *               16 MHz) but the real value may vary depending on the variations
+  *               in voltage and temperature.
+  * @note     (**) HSE_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value
+  *                25 MHz), user has to ensure that HSE_VALUE is same as the real
+  *                frequency of the crystal used. Otherwise, this function may
+  *                have wrong result.
+  *
+  * @note   The result of this function could be not correct when using fractional
+  *         value for HSE crystal.
+  *
+  * @note   This function can be used by the user application to compute the
+  *         baudrate for the communication peripherals or configure other parameters.
+  *
+  * @note   Each time SYSCLK changes, this function must be called to update the
+  *         right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.
+  *
+  *
+  * @retval SYSCLK frequency
+  */
+uint32_t HAL_RCC_GetSysClockFreq(void)
+{
+  uint32_t pllm = 0U;
+  uint32_t pllvco = 0U;
+  uint32_t pllp = 0U;
+  uint32_t pllr = 0U;
+  uint32_t sysclockfreq = 0U;
+
+  /* Get SYSCLK source -------------------------------------------------------*/
+  switch (RCC->CFGR & RCC_CFGR_SWS)
+  {
+    case RCC_CFGR_SWS_HSI:  /* HSI used as system clock source */
+    {
+      sysclockfreq = HSI_VALUE;
+       break;
+    }
+    case RCC_CFGR_SWS_HSE:  /* HSE used as system clock  source */
+    {
+      sysclockfreq = HSE_VALUE;
+      break;
+    }
+    case RCC_CFGR_SWS_PLL:  /* PLL/PLLP used as system clock  source */
+    {
+      /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
+      SYSCLK = PLL_VCO / PLLP */
+      pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
+      if(__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_HSI)
+      {
+        /* HSE used as PLL clock source */
+        pllvco = (uint32_t) ((((uint64_t) HSE_VALUE * ((uint64_t) ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm);
+      }
+      else
+      {
+        /* HSI used as PLL clock source */
+        pllvco = (uint32_t) ((((uint64_t) HSI_VALUE * ((uint64_t) ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm);
+      }
+      pllp = ((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >> RCC_PLLCFGR_PLLP_Pos) + 1U) *2U);
+
+      sysclockfreq = pllvco/pllp;
+      break;
+    }
+    case RCC_CFGR_SWS_PLLR:  /* PLL/PLLR used as system clock  source */
+    {
+      /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
+      SYSCLK = PLL_VCO / PLLR */
+      pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
+      if(__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_HSI)
+      {
+        /* HSE used as PLL clock source */
+        pllvco = (uint32_t) ((((uint64_t) HSE_VALUE * ((uint64_t) ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm);
+      }
+      else
+      {
+        /* HSI used as PLL clock source */
+        pllvco = (uint32_t) ((((uint64_t) HSI_VALUE * ((uint64_t) ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm);
+      }
+      pllr = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos);
+
+      sysclockfreq = pllvco/pllr;
+      break;
+    }
+    default:
+    {
+      sysclockfreq = HSI_VALUE;
+      break;
+    }
+  }
+  return sysclockfreq;
+}
+#endif /* STM32F446xx */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @brief  Resets the RCC clock configuration to the default reset state.
+  * @note   The default reset state of the clock configuration is given below:
+  *            - HSI ON and used as system clock source
+  *            - HSE, PLL, PLLI2S and PLLSAI OFF
+  *            - AHB, APB1 and APB2 prescaler set to 1.
+  *            - CSS, MCO1 and MCO2 OFF
+  *            - All interrupts disabled
+  * @note   This function doesn't modify the configuration of the
+  *            - Peripheral clocks
+  *            - LSI, LSE and RTC clocks
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RCC_DeInit(void)
+{
+  uint32_t tickstart;
+
+  /* Get Start Tick */
+  tickstart = HAL_GetTick();
+
+  /* Set HSION bit to the reset value */
+  SET_BIT(RCC->CR, RCC_CR_HSION);
+
+  /* Wait till HSI is ready */
+  while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == RESET)
+  {
+    if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
+    {
+      return HAL_TIMEOUT;
+    }
+  }
+
+  /* Set HSITRIM[4:0] bits to the reset value */
+  SET_BIT(RCC->CR, RCC_CR_HSITRIM_4);
+
+  /* Get Start Tick */
+  tickstart = HAL_GetTick();
+
+  /* Reset CFGR register */
+  CLEAR_REG(RCC->CFGR);
+
+  /* Wait till clock switch is ready */
+  while (READ_BIT(RCC->CFGR, RCC_CFGR_SWS) != RESET)
+  {
+    if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
+    {
+      return HAL_TIMEOUT;
+    }
+  }
+
+  /* Get Start Tick */
+  tickstart = HAL_GetTick();
+
+  /* Clear HSEON, HSEBYP and CSSON bits */
+  CLEAR_BIT(RCC->CR, RCC_CR_HSEON | RCC_CR_HSEBYP | RCC_CR_CSSON);
+
+  /* Wait till HSE is disabled */
+  while (READ_BIT(RCC->CR, RCC_CR_HSERDY) != RESET)
+  {
+    if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
+    {
+      return HAL_TIMEOUT;
+    }
+  }
+
+  /* Get Start Tick */
+  tickstart = HAL_GetTick();
+
+  /* Clear PLLON bit */
+  CLEAR_BIT(RCC->CR, RCC_CR_PLLON);
+
+  /* Wait till PLL is disabled */
+  while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != RESET)
+  {
+    if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
+    {
+      return HAL_TIMEOUT;
+    }
+  }
+
+#if defined(RCC_PLLI2S_SUPPORT)
+  /* Get Start Tick */
+  tickstart = HAL_GetTick();
+
+  /* Reset PLLI2SON bit */
+  CLEAR_BIT(RCC->CR, RCC_CR_PLLI2SON);
+
+  /* Wait till PLLI2S is disabled */
+  while (READ_BIT(RCC->CR, RCC_CR_PLLI2SRDY) != RESET)
+  {
+    if ((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE)
+    {
+      return HAL_TIMEOUT;
+    }
+  }
+#endif /* RCC_PLLI2S_SUPPORT */
+
+#if defined(RCC_PLLSAI_SUPPORT)
+  /* Get Start Tick */
+  tickstart = HAL_GetTick();
+
+  /* Reset PLLSAI bit */
+  CLEAR_BIT(RCC->CR, RCC_CR_PLLSAION);
+
+  /* Wait till PLLSAI is disabled */
+  while (READ_BIT(RCC->CR, RCC_CR_PLLSAIRDY) != RESET)
+  {
+    if ((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE)
+    {
+      return HAL_TIMEOUT;
+    }
+  }
+#endif /* RCC_PLLSAI_SUPPORT */
+
+  /* Once PLL, PLLI2S and PLLSAI are OFF, reset PLLCFGR register to default value */
+#if defined(STM32F412Cx) || defined(STM32F412Rx) || defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || \
+    defined(STM32F423xx) || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
+  RCC->PLLCFGR = RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLN_6 | RCC_PLLCFGR_PLLN_7 | RCC_PLLCFGR_PLLQ_2 | RCC_PLLCFGR_PLLR_1;
+#elif defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
+  RCC->PLLCFGR = RCC_PLLCFGR_PLLR_0 | RCC_PLLCFGR_PLLR_1 | RCC_PLLCFGR_PLLR_2 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLN_6 | RCC_PLLCFGR_PLLN_7 | RCC_PLLCFGR_PLLQ_0 | RCC_PLLCFGR_PLLQ_1 | RCC_PLLCFGR_PLLQ_2 | RCC_PLLCFGR_PLLQ_3;
+#else
+  RCC->PLLCFGR = RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLN_6 | RCC_PLLCFGR_PLLN_7 | RCC_PLLCFGR_PLLQ_2;
+#endif /* STM32F412Cx || STM32F412Rx || STM32F412Vx || STM32F412Zx || STM32F413xx || STM32F423xx || STM32F446xx || STM32F469xx || STM32F479xx */
+
+  /* Reset PLLI2SCFGR register to default value */
+#if defined(STM32F412Cx) || defined(STM32F412Rx) || defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || \
+    defined(STM32F423xx) || defined(STM32F446xx)
+  RCC->PLLI2SCFGR = RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SN_6 | RCC_PLLI2SCFGR_PLLI2SN_7 | RCC_PLLI2SCFGR_PLLI2SQ_2 | RCC_PLLI2SCFGR_PLLI2SR_1;
+#elif defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
+  RCC->PLLI2SCFGR = RCC_PLLI2SCFGR_PLLI2SN_6 | RCC_PLLI2SCFGR_PLLI2SN_7 | RCC_PLLI2SCFGR_PLLI2SR_1;
+#elif defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
+  RCC->PLLI2SCFGR = RCC_PLLI2SCFGR_PLLI2SN_6 | RCC_PLLI2SCFGR_PLLI2SN_7 | RCC_PLLI2SCFGR_PLLI2SQ_2 | RCC_PLLI2SCFGR_PLLI2SR_1;
+#elif defined(STM32F411xE)
+  RCC->PLLI2SCFGR = RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SN_6 | RCC_PLLI2SCFGR_PLLI2SN_7 | RCC_PLLI2SCFGR_PLLI2SR_1;
+#endif /* STM32F412Cx || STM32F412Rx || STM32F412Vx || STM32F412Zx || STM32F413xx || STM32F423xx || STM32F446xx */
+
+  /* Reset PLLSAICFGR register */
+#if defined(STM32F427xx) || defined(STM32F429xx) || defined(STM32F437xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
+  RCC->PLLSAICFGR = RCC_PLLSAICFGR_PLLSAIN_6 | RCC_PLLSAICFGR_PLLSAIN_7 | RCC_PLLSAICFGR_PLLSAIQ_2 | RCC_PLLSAICFGR_PLLSAIR_1;
+#elif defined(STM32F446xx)
+  RCC->PLLSAICFGR = RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIN_6 | RCC_PLLSAICFGR_PLLSAIN_7 | RCC_PLLSAICFGR_PLLSAIQ_2;
+#endif /* STM32F427xx || STM32F429xx || STM32F437xx || STM32F439xx || STM32F469xx || STM32F479xx */
+
+  /* Disable all interrupts */
+  CLEAR_BIT(RCC->CIR, RCC_CIR_LSIRDYIE | RCC_CIR_LSERDYIE | RCC_CIR_HSIRDYIE | RCC_CIR_HSERDYIE | RCC_CIR_PLLRDYIE);
+
+#if defined(RCC_CIR_PLLI2SRDYIE)
+  CLEAR_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYIE);
+#endif /* RCC_CIR_PLLI2SRDYIE */
+
+#if defined(RCC_CIR_PLLSAIRDYIE)
+  CLEAR_BIT(RCC->CIR, RCC_CIR_PLLSAIRDYIE);
+#endif /* RCC_CIR_PLLSAIRDYIE */
+
+  /* Clear all interrupt flags */
+  SET_BIT(RCC->CIR, RCC_CIR_LSIRDYC | RCC_CIR_LSERDYC | RCC_CIR_HSIRDYC | RCC_CIR_HSERDYC | RCC_CIR_PLLRDYC | RCC_CIR_CSSC);
+
+#if defined(RCC_CIR_PLLI2SRDYC)
+  SET_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYC);
+#endif /* RCC_CIR_PLLI2SRDYC */
+
+#if defined(RCC_CIR_PLLSAIRDYC)
+  SET_BIT(RCC->CIR, RCC_CIR_PLLSAIRDYC);
+#endif /* RCC_CIR_PLLSAIRDYC */
+
+  /* Clear LSION bit */
+  CLEAR_BIT(RCC->CSR, RCC_CSR_LSION);
+
+  /* Reset all CSR flags */
+  SET_BIT(RCC->CSR, RCC_CSR_RMVF);
+
+  /* Update the SystemCoreClock global variable */
+  SystemCoreClock = HSI_VALUE;
+
+  /* Adapt Systick interrupt period */
+  if(HAL_InitTick(uwTickPrio) != HAL_OK)
+  {
+    return HAL_ERROR;
+  }
+  else
+  {
+    return HAL_OK;
+  }
+}
+
+#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) ||\
+    defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
+/**
+  * @brief  Initializes the RCC Oscillators according to the specified parameters in the
+  *         RCC_OscInitTypeDef.
+  * @param  RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that
+  *         contains the configuration information for the RCC Oscillators.
+  * @note   The PLL is not disabled when used as system clock.
+  * @note   Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not
+  *         supported by this API. User should request a transition to LSE Off
+  *         first and then LSE On or LSE Bypass.
+  * @note   Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not
+  *         supported by this API. User should request a transition to HSE Off
+  *         first and then HSE On or HSE Bypass.
+  * @note   This function add the PLL/PLLR factor management during PLL configuration this feature
+  *         is only available in STM32F410xx/STM32F446xx/STM32F469xx/STM32F479xx/STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx devices
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct)
+{
+  uint32_t tickstart, pll_config;
+
+  /* Check Null pointer */
+  if(RCC_OscInitStruct == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
+  /*------------------------------- HSE Configuration ------------------------*/
+  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
+    /* When the HSE is used as system clock or clock source for PLL in these cases HSE will not disabled */
+#if defined(STM32F446xx)
+    if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE)                                                                     ||\
+      ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)) ||\
+      ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLLR) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)))
+#else
+    if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE)                                                                     ||\
+      ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)))
+#endif /* STM32F446xx */
+    {
+      if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
+      {
+        return HAL_ERROR;
+      }
+    }
+    else
+    {
+      /* Set the new HSE configuration ---------------------------------------*/
+      __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
+
+      /* Check the HSE State */
+      if((RCC_OscInitStruct->HSEState) != RCC_HSE_OFF)
+      {
+        /* Get Start Tick*/
+        tickstart = HAL_GetTick();
+
+        /* Wait till HSE is ready */
+        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
+        {
+          if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
+          {
+            return HAL_TIMEOUT;
+          }
+        }
+      }
+      else
+      {
+        /* Get Start Tick*/
+        tickstart = HAL_GetTick();
+
+        /* Wait till HSE is bypassed or disabled */
+        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
+        {
+          if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
+          {
+            return HAL_TIMEOUT;
+          }
+        }
+      }
+    }
+  }
+  /*----------------------------- HSI Configuration --------------------------*/
+  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
+    assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
+
+    /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
+#if defined(STM32F446xx)
+    if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI)                                                                     ||\
+      ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)) ||\
+      ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLLR) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)))
+#else
+    if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI)                                                                     ||\
+      ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)))
+#endif /* STM32F446xx */
+    {
+      /* When HSI is used as system clock it will not disabled */
+      if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
+      {
+        return HAL_ERROR;
+      }
+      /* Otherwise, just the calibration is allowed */
+      else
+      {
+        /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
+        __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
+      }
+    }
+    else
+    {
+      /* Check the HSI State */
+      if((RCC_OscInitStruct->HSIState)!= RCC_HSI_OFF)
+      {
+        /* Enable the Internal High Speed oscillator (HSI). */
+        __HAL_RCC_HSI_ENABLE();
+
+        /* Get Start Tick*/
+        tickstart = HAL_GetTick();
+
+        /* Wait till HSI is ready */
+        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
+        {
+          if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
+          {
+            return HAL_TIMEOUT;
+          }
+        }
+
+        /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
+        __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
+      }
+      else
+      {
+        /* Disable the Internal High Speed oscillator (HSI). */
+        __HAL_RCC_HSI_DISABLE();
+
+        /* Get Start Tick*/
+        tickstart = HAL_GetTick();
+
+        /* Wait till HSI is ready */
+        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
+        {
+          if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
+          {
+            return HAL_TIMEOUT;
+          }
+        }
+      }
+    }
+  }
+  /*------------------------------ LSI Configuration -------------------------*/
+  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
+
+    /* Check the LSI State */
+    if((RCC_OscInitStruct->LSIState)!= RCC_LSI_OFF)
+    {
+      /* Enable the Internal Low Speed oscillator (LSI). */
+      __HAL_RCC_LSI_ENABLE();
+
+      /* Get Start Tick*/
+      tickstart = HAL_GetTick();
+
+      /* Wait till LSI is ready */
+      while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
+      {
+        if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
+        {
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+    else
+    {
+      /* Disable the Internal Low Speed oscillator (LSI). */
+      __HAL_RCC_LSI_DISABLE();
+
+      /* Get Start Tick*/
+      tickstart = HAL_GetTick();
+
+      /* Wait till LSI is ready */
+      while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
+      {
+        if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
+        {
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+  }
+  /*------------------------------ LSE Configuration -------------------------*/
+  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
+  {
+    FlagStatus       pwrclkchanged = RESET;
+
+    /* Check the parameters */
+    assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
+
+    /* Update LSE configuration in Backup Domain control register    */
+    /* Requires to enable write access to Backup Domain of necessary */
+    if(__HAL_RCC_PWR_IS_CLK_DISABLED())
+    {
+      __HAL_RCC_PWR_CLK_ENABLE();
+      pwrclkchanged = SET;
+    }
+
+    if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
+    {
+      /* Enable write access to Backup domain */
+      SET_BIT(PWR->CR, PWR_CR_DBP);
+
+      /* Wait for Backup domain Write protection disable */
+      tickstart = HAL_GetTick();
+
+      while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
+      {
+        if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
+        {
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+
+    /* Set the new LSE configuration -----------------------------------------*/
+    __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
+    /* Check the LSE State */
+    if((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF)
+    {
+      /* Get Start Tick*/
+      tickstart = HAL_GetTick();
+
+      /* Wait till LSE is ready */
+      while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
+      {
+        if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
+        {
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+    else
+    {
+      /* Get Start Tick*/
+      tickstart = HAL_GetTick();
+
+      /* Wait till LSE is ready */
+      while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
+      {
+        if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
+        {
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+
+    /* Restore clock configuration if changed */
+    if(pwrclkchanged == SET)
+    {
+      __HAL_RCC_PWR_CLK_DISABLE();
+    }
+  }
+  /*-------------------------------- PLL Configuration -----------------------*/
+  /* Check the parameters */
+  assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
+  if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
+  {
+    /* Check if the PLL is used as system clock or not */
+    if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL)
+    {
+      if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
+      {
+        /* Check the parameters */
+        assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource));
+        assert_param(IS_RCC_PLLM_VALUE(RCC_OscInitStruct->PLL.PLLM));
+        assert_param(IS_RCC_PLLN_VALUE(RCC_OscInitStruct->PLL.PLLN));
+        assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP));
+        assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ));
+        assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR));
+
+        /* Disable the main PLL. */
+        __HAL_RCC_PLL_DISABLE();
+
+        /* Get Start Tick*/
+        tickstart = HAL_GetTick();
+
+        /* Wait till PLL is ready */
+        while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
+        {
+          if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
+          {
+            return HAL_TIMEOUT;
+          }
+        }
+
+        /* Configure the main PLL clock source, multiplication and division factors. */
+        WRITE_REG(RCC->PLLCFGR, (RCC_OscInitStruct->PLL.PLLSource                                            | \
+                                 RCC_OscInitStruct->PLL.PLLM                                                 | \
+                                 (RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PLLN_Pos)                       | \
+                                 (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U) << RCC_PLLCFGR_PLLP_Pos)        | \
+                                 (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos)                       | \
+                                 (RCC_OscInitStruct->PLL.PLLR << RCC_PLLCFGR_PLLR_Pos)));
+        /* Enable the main PLL. */
+        __HAL_RCC_PLL_ENABLE();
+
+        /* Get Start Tick*/
+        tickstart = HAL_GetTick();
+
+        /* Wait till PLL is ready */
+        while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
+        {
+          if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
+          {
+            return HAL_TIMEOUT;
+          }
+        }
+      }
+      else
+      {
+        /* Disable the main PLL. */
+        __HAL_RCC_PLL_DISABLE();
+
+        /* Get Start Tick*/
+        tickstart = HAL_GetTick();
+
+        /* Wait till PLL is ready */
+        while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
+        {
+          if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
+          {
+            return HAL_TIMEOUT;
+          }
+        }
+      }
+    }
+    else
+    {
+      /* Check if there is a request to disable the PLL used as System clock source */
+      if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF)
+      {
+        return HAL_ERROR;
+      }
+      else
+      {
+        /* Do not return HAL_ERROR if request repeats the current configuration */
+        pll_config = RCC->PLLCFGR;
+#if defined (RCC_PLLCFGR_PLLR)
+        if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) ||
+            (READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
+            (READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != (RCC_OscInitStruct->PLL.PLLM) << RCC_PLLCFGR_PLLM_Pos) ||
+            (READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN) << RCC_PLLCFGR_PLLN_Pos) ||
+            (READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U)) << RCC_PLLCFGR_PLLP_Pos) ||
+            (READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos)) ||
+            (READ_BIT(pll_config, RCC_PLLCFGR_PLLR) != (RCC_OscInitStruct->PLL.PLLR << RCC_PLLCFGR_PLLR_Pos)))
+#else
+        if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) ||
+            (READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
+            (READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != (RCC_OscInitStruct->PLL.PLLM) << RCC_PLLCFGR_PLLM_Pos) ||
+            (READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN) << RCC_PLLCFGR_PLLN_Pos) ||
+            (READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U)) << RCC_PLLCFGR_PLLP_Pos) ||
+            (READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos)))
+#endif
+        {
+          return HAL_ERROR;
+        }
+      }
+    }
+  }
+  return HAL_OK;
+}
+
+/**
+  * @brief  Configures the RCC_OscInitStruct according to the internal
+  * RCC configuration registers.
+  * @param  RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that will be configured.
+  *
+  * @note   This function is only available in case of STM32F410xx/STM32F446xx/STM32F469xx/STM32F479xx/STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx devices.
+  * @note   This function add the PLL/PLLR factor management
+  * @retval None
+  */
+void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct)
+{
+  /* Set all possible values for the Oscillator type parameter ---------------*/
+  RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI;
+
+  /* Get the HSE configuration -----------------------------------------------*/
+  if((RCC->CR &RCC_CR_HSEBYP) == RCC_CR_HSEBYP)
+  {
+    RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS;
+  }
+  else if((RCC->CR &RCC_CR_HSEON) == RCC_CR_HSEON)
+  {
+    RCC_OscInitStruct->HSEState = RCC_HSE_ON;
+  }
+  else
+  {
+    RCC_OscInitStruct->HSEState = RCC_HSE_OFF;
+  }
+
+  /* Get the HSI configuration -----------------------------------------------*/
+  if((RCC->CR &RCC_CR_HSION) == RCC_CR_HSION)
+  {
+    RCC_OscInitStruct->HSIState = RCC_HSI_ON;
+  }
+  else
+  {
+    RCC_OscInitStruct->HSIState = RCC_HSI_OFF;
+  }
+
+  RCC_OscInitStruct->HSICalibrationValue = (uint32_t)((RCC->CR &RCC_CR_HSITRIM) >> RCC_CR_HSITRIM_Pos);
+
+  /* Get the LSE configuration -----------------------------------------------*/
+  if((RCC->BDCR &RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP)
+  {
+    RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS;
+  }
+  else if((RCC->BDCR &RCC_BDCR_LSEON) == RCC_BDCR_LSEON)
+  {
+    RCC_OscInitStruct->LSEState = RCC_LSE_ON;
+  }
+  else
+  {
+    RCC_OscInitStruct->LSEState = RCC_LSE_OFF;
+  }
+
+  /* Get the LSI configuration -----------------------------------------------*/
+  if((RCC->CSR &RCC_CSR_LSION) == RCC_CSR_LSION)
+  {
+    RCC_OscInitStruct->LSIState = RCC_LSI_ON;
+  }
+  else
+  {
+    RCC_OscInitStruct->LSIState = RCC_LSI_OFF;
+  }
+
+  /* Get the PLL configuration -----------------------------------------------*/
+  if((RCC->CR &RCC_CR_PLLON) == RCC_CR_PLLON)
+  {
+    RCC_OscInitStruct->PLL.PLLState = RCC_PLL_ON;
+  }
+  else
+  {
+    RCC_OscInitStruct->PLL.PLLState = RCC_PLL_OFF;
+  }
+  RCC_OscInitStruct->PLL.PLLSource = (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
+  RCC_OscInitStruct->PLL.PLLM = (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM);
+  RCC_OscInitStruct->PLL.PLLN = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
+  RCC_OscInitStruct->PLL.PLLP = (uint32_t)((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) + RCC_PLLCFGR_PLLP_0) << 1U) >> RCC_PLLCFGR_PLLP_Pos);
+  RCC_OscInitStruct->PLL.PLLQ = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLQ) >> RCC_PLLCFGR_PLLQ_Pos);
+  RCC_OscInitStruct->PLL.PLLR = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos);
+}
+#endif /* STM32F410xx || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */
+
+#endif /* HAL_RCC_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
diff --git a/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sai.c b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sai.c
new file mode 100644
index 0000000..b131409
--- /dev/null
+++ b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sai.c
@@ -0,0 +1,2554 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hal_sai.c
+  * @author  MCD Application Team
+  * @brief   SAI HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the Serial Audio Interface (SAI) peripheral:
+  *           + Initialization/de-initialization functions
+  *           + I/O operation functions
+  *           + Peripheral Control functions
+  *           + Peripheral State functions
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  @verbatim
+  ==============================================================================
+                  ##### How to use this driver #####
+  ==============================================================================
+
+  [..]
+    The SAI HAL driver can be used as follows:
+
+    (#) Declare a SAI_HandleTypeDef handle structure (eg. SAI_HandleTypeDef hsai).
+    (#) Initialize the SAI low level resources by implementing the HAL_SAI_MspInit() API:
+        (##) Enable the SAI interface clock.
+        (##) SAI pins configuration:
+            (+++) Enable the clock for the SAI GPIOs.
+            (+++) Configure these SAI pins as alternate function pull-up.
+        (##) NVIC configuration if you need to use interrupt process (HAL_SAI_Transmit_IT()
+             and HAL_SAI_Receive_IT() APIs):
+            (+++) Configure the SAI interrupt priority.
+            (+++) Enable the NVIC SAI IRQ handle.
+
+        (##) DMA Configuration if you need to use DMA process (HAL_SAI_Transmit_DMA()
+             and HAL_SAI_Receive_DMA() APIs):
+            (+++) Declare a DMA handle structure for the Tx/Rx stream.
+            (+++) Enable the DMAx interface clock.
+            (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
+            (+++) Configure the DMA Tx/Rx Stream.
+            (+++) Associate the initialized DMA handle to the SAI DMA Tx/Rx handle.
+            (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the
+                DMA Tx/Rx Stream.
+
+    (#) The initialization can be done by two ways
+        (##) Expert mode : Initialize the structures Init, FrameInit and SlotInit and call HAL_SAI_Init().
+        (##) Simplified mode : Initialize the high part of Init Structure and call HAL_SAI_InitProtocol().
+
+  [..]
+    (@) The specific SAI interrupts (FIFO request and Overrun underrun interrupt)
+        will be managed using the macros __HAL_SAI_ENABLE_IT() and __HAL_SAI_DISABLE_IT()
+        inside the transmit and receive process.
+
+  [..]
+   (@) SAI Clock Source configuration is managed differently depending on the selected
+       STM32F4 devices :
+       (+@) For STM32F446xx devices, the configuration is managed through RCCEx_PeriphCLKConfig()
+            function in the HAL RCC drivers
+       (+@) For STM32F439xx/STM32F437xx/STM32F429xx/STM32F427xx devices, the configuration
+            is managed within HAL SAI drivers through HAL_SAI_Init() function using
+            ClockSource field of SAI_InitTypeDef structure.
+  [..]
+   (@) Make sure that either:
+       (+@) I2S PLL is configured or
+       (+@) SAI PLL is configured or
+       (+@) External clock source is configured after setting correctly
+            the define constant EXTERNAL_CLOCK_VALUE in the stm32f4xx_hal_conf.h file.
+  [..]
+    (@) In master Tx mode: enabling the audio block immediately generates the bit clock
+        for the external slaves even if there is no data in the FIFO, However FS signal
+        generation is conditioned by the presence of data in the FIFO.
+
+  [..]
+    (@) In master Rx mode: enabling the audio block immediately generates the bit clock
+        and FS signal for the external slaves.
+
+  [..]
+    (@) It is mandatory to respect the following conditions in order to avoid bad SAI behavior:
+        (+@) First bit Offset <= (SLOT size - Data size)
+        (+@) Data size <= SLOT size
+        (+@) Number of SLOT x SLOT size = Frame length
+        (+@) The number of slots should be even when SAI_FS_CHANNEL_IDENTIFICATION is selected.
+
+  [..]
+    Three operation modes are available within this driver :
+
+    *** Polling mode IO operation ***
+    =================================
+    [..]
+      (+) Send an amount of data in blocking mode using HAL_SAI_Transmit()
+      (+) Receive an amount of data in blocking mode using HAL_SAI_Receive()
+
+    *** Interrupt mode IO operation ***
+    ===================================
+    [..]
+      (+) Send an amount of data in non-blocking mode using HAL_SAI_Transmit_IT()
+      (+) At transmission end of transfer HAL_SAI_TxCpltCallback() is executed and user can
+          add his own code by customization of function pointer HAL_SAI_TxCpltCallback()
+      (+) Receive an amount of data in non-blocking mode using HAL_SAI_Receive_IT()
+      (+) At reception end of transfer HAL_SAI_RxCpltCallback() is executed and user can
+          add his own code by customization of function pointer HAL_SAI_RxCpltCallback()
+      (+) In case of flag error, HAL_SAI_ErrorCallback() function is executed and user can
+          add his own code by customization of function pointer HAL_SAI_ErrorCallback()
+
+    *** DMA mode IO operation ***
+    =============================
+    [..]
+      (+) Send an amount of data in non-blocking mode (DMA) using HAL_SAI_Transmit_DMA()
+      (+) At transmission end of transfer HAL_SAI_TxCpltCallback() is executed and user can
+          add his own code by customization of function pointer HAL_SAI_TxCpltCallback()
+      (+) Receive an amount of data in non-blocking mode (DMA) using HAL_SAI_Receive_DMA()
+      (+) At reception end of transfer HAL_SAI_RxCpltCallback() is executed and user can
+          add his own code by customization of function pointer HAL_SAI_RxCpltCallback()
+      (+) In case of flag error, HAL_SAI_ErrorCallback() function is executed and user can
+          add his own code by customization of function pointer HAL_SAI_ErrorCallback()
+      (+) Pause the DMA Transfer using HAL_SAI_DMAPause()
+      (+) Resume the DMA Transfer using HAL_SAI_DMAResume()
+      (+) Stop the DMA Transfer using HAL_SAI_DMAStop()
+
+    *** SAI HAL driver additional function list ***
+    ===============================================
+    [..]
+      Below the list the others API available SAI HAL driver :
+
+      (+) HAL_SAI_EnableTxMuteMode(): Enable the mute in tx mode
+      (+) HAL_SAI_DisableTxMuteMode(): Disable the mute in tx mode
+      (+) HAL_SAI_EnableRxMuteMode(): Enable the mute in Rx mode
+      (+) HAL_SAI_DisableRxMuteMode(): Disable the mute in Rx mode
+      (+) HAL_SAI_FlushRxFifo(): Flush the rx fifo.
+      (+) HAL_SAI_Abort(): Abort the current transfer
+
+    *** SAI HAL driver macros list ***
+    ==================================
+    [..]
+      Below the list of most used macros in SAI HAL driver :
+
+      (+) __HAL_SAI_ENABLE(): Enable the SAI peripheral
+      (+) __HAL_SAI_DISABLE(): Disable the SAI peripheral
+      (+) __HAL_SAI_ENABLE_IT(): Enable the specified SAI interrupts
+      (+) __HAL_SAI_DISABLE_IT(): Disable the specified SAI interrupts
+      (+) __HAL_SAI_GET_IT_SOURCE(): Check if the specified SAI interrupt source is
+          enabled or disabled
+      (+) __HAL_SAI_GET_FLAG(): Check whether the specified SAI flag is set or not
+
+    *** Callback registration ***
+    =============================
+    [..]
+    The compilation define USE_HAL_SAI_REGISTER_CALLBACKS when set to 1
+    allows the user to configure dynamically the driver callbacks.
+    Use functions HAL_SAI_RegisterCallback() to register a user callback.
+
+    [..]
+    Function HAL_SAI_RegisterCallback() allows to register following callbacks:
+      (+) RxCpltCallback     : SAI receive complete.
+      (+) RxHalfCpltCallback : SAI receive half complete.
+      (+) TxCpltCallback     : SAI transmit complete.
+      (+) TxHalfCpltCallback : SAI transmit half complete.
+      (+) ErrorCallback      : SAI error.
+      (+) MspInitCallback    : SAI MspInit.
+      (+) MspDeInitCallback  : SAI MspDeInit.
+    [..]
+    This function takes as parameters the HAL peripheral handle, the callback ID
+    and a pointer to the user callback function.
+
+    [..]
+    Use function HAL_SAI_UnRegisterCallback() to reset a callback to the default
+    weak (surcharged) function.
+    HAL_SAI_UnRegisterCallback() takes as parameters the HAL peripheral handle,
+    and the callback ID.
+    [..]
+    This function allows to reset following callbacks:
+      (+) RxCpltCallback     : SAI receive complete.
+      (+) RxHalfCpltCallback : SAI receive half complete.
+      (+) TxCpltCallback     : SAI transmit complete.
+      (+) TxHalfCpltCallback : SAI transmit half complete.
+      (+) ErrorCallback      : SAI error.
+      (+) MspInitCallback    : SAI MspInit.
+      (+) MspDeInitCallback  : SAI MspDeInit.
+
+    [..]
+    By default, after the HAL_SAI_Init and if the state is HAL_SAI_STATE_RESET
+    all callbacks are reset to the corresponding legacy weak (surcharged) functions:
+    examples HAL_SAI_RxCpltCallback(), HAL_SAI_ErrorCallback().
+    Exception done for MspInit and MspDeInit callbacks that are respectively
+    reset to the legacy weak (surcharged) functions in the HAL_SAI_Init
+    and HAL_SAI_DeInit only when these callbacks are null (not registered beforehand).
+    If not, MspInit or MspDeInit are not null, the HAL_SAI_Init and HAL_SAI_DeInit
+    keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
+
+    [..]
+    Callbacks can be registered/unregistered in READY state only.
+    Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
+    in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
+    during the Init/DeInit.
+    In that case first register the MspInit/MspDeInit user callbacks
+    using HAL_SAI_RegisterCallback before calling HAL_SAI_DeInit
+    or HAL_SAI_Init function.
+
+    [..]
+    When the compilation define USE_HAL_SAI_REGISTER_CALLBACKS is set to 0 or
+    not defined, the callback registering feature is not available
+    and weak (surcharged) callbacks are used.
+
+  @endverbatim
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup SAI SAI
+  * @brief SAI HAL module driver
+  * @{
+  */
+
+#ifdef HAL_SAI_MODULE_ENABLED
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
+    defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F413xx) ||\
+    defined(STM32F423xx)
+
+/** @defgroup SAI_Private_Typedefs  SAI Private Typedefs
+  * @{
+  */
+typedef enum
+{
+  SAI_MODE_DMA,
+  SAI_MODE_IT
+} SAI_ModeTypedef;
+/**
+  * @}
+  */
+
+/* Private define ------------------------------------------------------------*/
+
+/** @defgroup SAI_Private_Constants  SAI Private Constants
+  * @{
+  */
+#define SAI_DEFAULT_TIMEOUT   4U /* 4ms */
+#define SAI_LONG_TIMEOUT      1000U /* 1s */
+/**
+  * @}
+  */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @defgroup SAI_Private_Functions  SAI Private Functions
+  * @{
+  */
+static void SAI_FillFifo(SAI_HandleTypeDef *hsai);
+static uint32_t SAI_InterruptFlag(SAI_HandleTypeDef *hsai, uint32_t mode);
+static HAL_StatusTypeDef SAI_InitI2S(SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot);
+static HAL_StatusTypeDef SAI_InitPCM(SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot);
+
+static HAL_StatusTypeDef SAI_Disable(SAI_HandleTypeDef *hsai);
+static void SAI_Transmit_IT8Bit(SAI_HandleTypeDef *hsai);
+static void SAI_Transmit_IT16Bit(SAI_HandleTypeDef *hsai);
+static void SAI_Transmit_IT32Bit(SAI_HandleTypeDef *hsai);
+static void SAI_Receive_IT8Bit(SAI_HandleTypeDef *hsai);
+static void SAI_Receive_IT16Bit(SAI_HandleTypeDef *hsai);
+static void SAI_Receive_IT32Bit(SAI_HandleTypeDef *hsai);
+
+static void SAI_DMATxCplt(DMA_HandleTypeDef *hdma);
+static void SAI_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
+static void SAI_DMARxCplt(DMA_HandleTypeDef *hdma);
+static void SAI_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
+static void SAI_DMAError(DMA_HandleTypeDef *hdma);
+static void SAI_DMAAbort(DMA_HandleTypeDef *hdma);
+/**
+  * @}
+  */
+
+/* Exported functions ---------------------------------------------------------*/
+/** @defgroup SAI_Exported_Functions SAI Exported Functions
+  * @{
+  */
+
+/** @defgroup SAI_Exported_Functions_Group1 Initialization and de-initialization functions
+  * @brief    Initialization and Configuration functions
+  *
+@verbatim
+ ===============================================================================
+            ##### Initialization and de-initialization functions #####
+ ===============================================================================
+  [..]  This subsection provides a set of functions allowing to initialize and
+        de-initialize the SAIx peripheral:
+
+      (+) User must implement HAL_SAI_MspInit() function in which he configures
+          all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
+
+      (+) Call the function HAL_SAI_Init() to configure the selected device with
+          the selected configuration:
+        (++) Mode (Master/slave TX/RX)
+        (++) Protocol
+        (++) Data Size
+        (++) MCLK Output
+        (++) Audio frequency
+        (++) FIFO Threshold
+        (++) Frame Config
+        (++) Slot Config
+
+      (+) Call the function HAL_SAI_DeInit() to restore the default configuration
+          of the selected SAI peripheral.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initialize the structure FrameInit, SlotInit and the low part of
+  *         Init according to the specified parameters and call the function
+  *         HAL_SAI_Init to initialize the SAI block.
+  * @param  hsai pointer to a SAI_HandleTypeDef structure that contains
+  *               the configuration information for SAI module.
+  * @param  protocol one of the supported protocol @ref SAI_Protocol
+  * @param  datasize one of the supported datasize @ref SAI_Protocol_DataSize
+  *                   the configuration information for SAI module.
+  * @param  nbslot Number of slot.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SAI_InitProtocol(SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the parameters */
+  assert_param(IS_SAI_SUPPORTED_PROTOCOL(protocol));
+  assert_param(IS_SAI_PROTOCOL_DATASIZE(datasize));
+
+  switch (protocol)
+  {
+    case SAI_I2S_STANDARD :
+    case SAI_I2S_MSBJUSTIFIED :
+    case SAI_I2S_LSBJUSTIFIED :
+      status = SAI_InitI2S(hsai, protocol, datasize, nbslot);
+      break;
+    case SAI_PCM_LONG :
+    case SAI_PCM_SHORT :
+      status = SAI_InitPCM(hsai, protocol, datasize, nbslot);
+      break;
+    default :
+      status = HAL_ERROR;
+      break;
+  }
+
+  if (status == HAL_OK)
+  {
+    status = HAL_SAI_Init(hsai);
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Initialize the SAI according to the specified parameters.
+  *         in the SAI_InitTypeDef structure and initialize the associated handle.
+  * @param  hsai pointer to a SAI_HandleTypeDef structure that contains
+  *               the configuration information for SAI module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SAI_Init(SAI_HandleTypeDef *hsai)
+{
+  uint32_t tmpregisterGCR = 0U;
+
+  /* This variable used to store the SAI_CK_x (value in Hz) */
+  uint32_t freq = 0U;
+
+  /* This variable is used to compute CKSTR bits of SAI CR1 according to
+     ClockStrobing and AudioMode fields */
+  uint32_t ckstr_bits = 0U;
+  uint32_t syncen_bits = 0U;
+
+  /* Check the SAI handle allocation */
+  if (hsai == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* check the instance */
+  assert_param(IS_SAI_ALL_INSTANCE(hsai->Instance));
+
+  /* Check the SAI Block parameters */
+  assert_param(IS_SAI_AUDIO_FREQUENCY(hsai->Init.AudioFrequency));
+  assert_param(IS_SAI_BLOCK_PROTOCOL(hsai->Init.Protocol));
+  assert_param(IS_SAI_BLOCK_MODE(hsai->Init.AudioMode));
+  assert_param(IS_SAI_BLOCK_SYNCEXT(hsai->Init.SynchroExt));
+  assert_param(IS_SAI_BLOCK_DATASIZE(hsai->Init.DataSize));
+  assert_param(IS_SAI_BLOCK_FIRST_BIT(hsai->Init.FirstBit));
+  assert_param(IS_SAI_BLOCK_CLOCK_STROBING(hsai->Init.ClockStrobing));
+  assert_param(IS_SAI_BLOCK_SYNCHRO(hsai->Init.Synchro));
+  assert_param(IS_SAI_BLOCK_OUTPUT_DRIVE(hsai->Init.OutputDrive));
+  assert_param(IS_SAI_BLOCK_NODIVIDER(hsai->Init.NoDivider));
+  assert_param(IS_SAI_BLOCK_FIFO_THRESHOLD(hsai->Init.FIFOThreshold));
+  assert_param(IS_SAI_MONO_STEREO_MODE(hsai->Init.MonoStereoMode));
+  assert_param(IS_SAI_BLOCK_COMPANDING_MODE(hsai->Init.CompandingMode));
+  assert_param(IS_SAI_BLOCK_TRISTATE_MANAGEMENT(hsai->Init.TriState));
+
+  /* Check the SAI Block Frame parameters */
+  assert_param(IS_SAI_BLOCK_FRAME_LENGTH(hsai->FrameInit.FrameLength));
+  assert_param(IS_SAI_BLOCK_ACTIVE_FRAME(hsai->FrameInit.ActiveFrameLength));
+  assert_param(IS_SAI_BLOCK_FS_DEFINITION(hsai->FrameInit.FSDefinition));
+  assert_param(IS_SAI_BLOCK_FS_POLARITY(hsai->FrameInit.FSPolarity));
+  assert_param(IS_SAI_BLOCK_FS_OFFSET(hsai->FrameInit.FSOffset));
+
+  /* Check the SAI Block Slot parameters */
+  assert_param(IS_SAI_BLOCK_FIRSTBIT_OFFSET(hsai->SlotInit.FirstBitOffset));
+  assert_param(IS_SAI_BLOCK_SLOT_SIZE(hsai->SlotInit.SlotSize));
+  assert_param(IS_SAI_BLOCK_SLOT_NUMBER(hsai->SlotInit.SlotNumber));
+  assert_param(IS_SAI_SLOT_ACTIVE(hsai->SlotInit.SlotActive));
+
+  if (hsai->State == HAL_SAI_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    hsai->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
+    /* Reset callback pointers to the weak predefined callbacks */
+    hsai->RxCpltCallback     = HAL_SAI_RxCpltCallback;
+    hsai->RxHalfCpltCallback = HAL_SAI_RxHalfCpltCallback;
+    hsai->TxCpltCallback     = HAL_SAI_TxCpltCallback;
+    hsai->TxHalfCpltCallback = HAL_SAI_TxHalfCpltCallback;
+    hsai->ErrorCallback      = HAL_SAI_ErrorCallback;
+
+    /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
+    if (hsai->MspInitCallback == NULL)
+    {
+      hsai->MspInitCallback = HAL_SAI_MspInit;
+    }
+    hsai->MspInitCallback(hsai);
+#else
+    /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
+    HAL_SAI_MspInit(hsai);
+#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */
+  }
+
+  hsai->State = HAL_SAI_STATE_BUSY;
+
+  /* Disable the selected SAI peripheral */
+  SAI_Disable(hsai);
+
+  /* SAI Block Synchro Configuration -----------------------------------------*/
+  SAI_BlockSynchroConfig(hsai);
+
+  /* Configure Master Clock using the following formula :
+     MCLK_x = SAI_CK_x / (MCKDIV[3:0] * 2) with MCLK_x = 256 * FS
+     FS = SAI_CK_x / (MCKDIV[3:0] * 2) * 256
+     MCKDIV[3:0] = SAI_CK_x / FS * 512 */
+  if (hsai->Init.AudioFrequency != SAI_AUDIO_FREQUENCY_MCKDIV)
+  {
+    /* Get SAI clock source based on Source clock selection from RCC */
+    freq = SAI_GetInputClock(hsai);
+
+    /* (saiclocksource x 10) to keep Significant digits */
+    tmpregisterGCR = (((freq * 10U) / ((hsai->Init.AudioFrequency) * 512U)));
+
+    hsai->Init.Mckdiv = tmpregisterGCR / 10U;
+
+    /* Round result to the nearest integer */
+    if ((tmpregisterGCR % 10U) > 8U)
+    {
+      hsai->Init.Mckdiv += 1U;
+    }
+
+    /* For SPDIF protocol, SAI shall provide a bit clock twice faster the symbol-rate */
+    if (hsai->Init.Protocol == SAI_SPDIF_PROTOCOL)
+    {
+      hsai->Init.Mckdiv = hsai->Init.Mckdiv >> 1;
+    }
+  }
+
+  /* Check the SAI Block master clock divider parameter */
+  assert_param(IS_SAI_BLOCK_MASTER_DIVIDER(hsai->Init.Mckdiv));
+
+  /* Compute CKSTR bits of SAI CR1 according to ClockStrobing and AudioMode */
+  if ((hsai->Init.AudioMode == SAI_MODEMASTER_TX) || (hsai->Init.AudioMode == SAI_MODESLAVE_TX))
+  {
+    ckstr_bits = (hsai->Init.ClockStrobing == SAI_CLOCKSTROBING_RISINGEDGE) ? 0U : SAI_xCR1_CKSTR;
+  }
+  else
+  {
+    ckstr_bits = (hsai->Init.ClockStrobing == SAI_CLOCKSTROBING_RISINGEDGE) ? SAI_xCR1_CKSTR : 0U;
+  }
+
+  /* SAI Block Configuration -------------------------------------------------*/
+  switch (hsai->Init.Synchro)
+  {
+    case SAI_ASYNCHRONOUS :
+    {
+      syncen_bits = 0U;
+    }
+    break;
+    case SAI_SYNCHRONOUS :
+    {
+      syncen_bits = SAI_xCR1_SYNCEN_0;
+    }
+    break;
+    case SAI_SYNCHRONOUS_EXT_SAI1 :
+    case SAI_SYNCHRONOUS_EXT_SAI2 :
+    {
+      syncen_bits = SAI_xCR1_SYNCEN_1;
+    }
+    break;
+    default:
+      break;
+  }
+
+  /* SAI CR1 Configuration */
+  hsai->Instance->CR1 &= ~(SAI_xCR1_MODE | SAI_xCR1_PRTCFG |  SAI_xCR1_DS |      \
+                           SAI_xCR1_LSBFIRST | SAI_xCR1_CKSTR | SAI_xCR1_SYNCEN | \
+                           SAI_xCR1_MONO | SAI_xCR1_OUTDRIV  | SAI_xCR1_DMAEN |  \
+                           SAI_xCR1_NODIV | SAI_xCR1_MCKDIV);
+
+  hsai->Instance->CR1 |= (hsai->Init.AudioMode | hsai->Init.Protocol |           \
+                          hsai->Init.DataSize | hsai->Init.FirstBit  |           \
+                          ckstr_bits | syncen_bits |                             \
+                          hsai->Init.MonoStereoMode | hsai->Init.OutputDrive |   \
+                          hsai->Init.NoDivider | (hsai->Init.Mckdiv << 20U));
+
+  /* SAI CR2 Configuration */
+  hsai->Instance->CR2 &= ~(SAI_xCR2_FTH | SAI_xCR2_FFLUSH | SAI_xCR2_COMP | SAI_xCR2_CPL);
+  hsai->Instance->CR2 |= (hsai->Init.FIFOThreshold | hsai->Init.CompandingMode | hsai->Init.TriState);
+
+  /* SAI Frame Configuration -----------------------------------------*/
+  hsai->Instance->FRCR &= (~(SAI_xFRCR_FRL | SAI_xFRCR_FSALL | SAI_xFRCR_FSDEF | \
+                             SAI_xFRCR_FSPOL | SAI_xFRCR_FSOFF));
+  hsai->Instance->FRCR |= ((hsai->FrameInit.FrameLength - 1U) |
+                           hsai->FrameInit.FSOffset     |
+                           hsai->FrameInit.FSDefinition |
+                           hsai->FrameInit.FSPolarity   |
+                           ((hsai->FrameInit.ActiveFrameLength - 1U) << 8U));
+
+  /* SAI Block_x SLOT Configuration ------------------------------------------*/
+  /* This register has no meaning in AC 97 and SPDIF audio protocol */
+  hsai->Instance->SLOTR &= ~(SAI_xSLOTR_FBOFF | SAI_xSLOTR_SLOTSZ | \
+                             SAI_xSLOTR_NBSLOT | SAI_xSLOTR_SLOTEN);
+
+  hsai->Instance->SLOTR |=  hsai->SlotInit.FirstBitOffset |  hsai->SlotInit.SlotSize  | \
+                            (hsai->SlotInit.SlotActive << 16U) | ((hsai->SlotInit.SlotNumber - 1U) <<  8U);
+
+  /* Initialize the error code */
+  hsai->ErrorCode = HAL_SAI_ERROR_NONE;
+
+  /* Initialize the SAI state */
+  hsai->State = HAL_SAI_STATE_READY;
+
+  /* Release Lock */
+  __HAL_UNLOCK(hsai);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  DeInitialize the SAI peripheral.
+  * @param  hsai pointer to a SAI_HandleTypeDef structure that contains
+  *               the configuration information for SAI module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SAI_DeInit(SAI_HandleTypeDef *hsai)
+{
+  /* Check the SAI handle allocation */
+  if (hsai == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  hsai->State = HAL_SAI_STATE_BUSY;
+
+  /* Disabled All interrupt and clear all the flag */
+  hsai->Instance->IMR = 0U;
+  hsai->Instance->CLRFR = 0xFFFFFFFFU;
+
+  /* Disable the SAI */
+  SAI_Disable(hsai);
+
+  /* Flush the fifo */
+  SET_BIT(hsai->Instance->CR2, SAI_xCR2_FFLUSH);
+
+  /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
+#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
+  if (hsai->MspDeInitCallback == NULL)
+  {
+    hsai->MspDeInitCallback = HAL_SAI_MspDeInit;
+  }
+  hsai->MspDeInitCallback(hsai);
+#else
+  HAL_SAI_MspDeInit(hsai);
+#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */
+
+  /* Initialize the error code */
+  hsai->ErrorCode = HAL_SAI_ERROR_NONE;
+
+  /* Initialize the SAI state */
+  hsai->State = HAL_SAI_STATE_RESET;
+
+  /* Release Lock */
+  __HAL_UNLOCK(hsai);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief Initialize the SAI MSP.
+  * @param  hsai pointer to a SAI_HandleTypeDef structure that contains
+  *               the configuration information for SAI module.
+  * @retval None
+  */
+__weak void HAL_SAI_MspInit(SAI_HandleTypeDef *hsai)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hsai);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_SAI_MspInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief DeInitialize the SAI MSP.
+  * @param  hsai pointer to a SAI_HandleTypeDef structure that contains
+  *               the configuration information for SAI module.
+  * @retval None
+  */
+__weak void HAL_SAI_MspDeInit(SAI_HandleTypeDef *hsai)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hsai);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_SAI_MspDeInit could be implemented in the user file
+   */
+}
+
+#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
+/**
+  * @brief  Register a user SAI callback
+  *         to be used instead of the weak predefined callback.
+  * @param  hsai SAI handle.
+  * @param  CallbackID ID of the callback to be registered.
+  *         This parameter can be one of the following values:
+  *           @arg @ref HAL_SAI_RX_COMPLETE_CB_ID receive complete callback ID.
+  *           @arg @ref HAL_SAI_RX_HALFCOMPLETE_CB_ID receive half complete callback ID.
+  *           @arg @ref HAL_SAI_TX_COMPLETE_CB_ID transmit complete callback ID.
+  *           @arg @ref HAL_SAI_TX_HALFCOMPLETE_CB_ID transmit half complete callback ID.
+  *           @arg @ref HAL_SAI_ERROR_CB_ID error callback ID.
+  *           @arg @ref HAL_SAI_MSPINIT_CB_ID MSP init callback ID.
+  *           @arg @ref HAL_SAI_MSPDEINIT_CB_ID MSP de-init callback ID.
+  * @param  pCallback pointer to the callback function.
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_SAI_RegisterCallback(SAI_HandleTypeDef        *hsai,
+                                           HAL_SAI_CallbackIDTypeDef CallbackID,
+                                           pSAI_CallbackTypeDef      pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    /* update the error code */
+    hsai->ErrorCode |= HAL_SAI_ERROR_INVALID_CALLBACK;
+    /* update return status */
+    status = HAL_ERROR;
+  }
+  else
+  {
+    if (HAL_SAI_STATE_READY == hsai->State)
+    {
+      switch (CallbackID)
+      {
+        case HAL_SAI_RX_COMPLETE_CB_ID :
+          hsai->RxCpltCallback = pCallback;
+          break;
+        case HAL_SAI_RX_HALFCOMPLETE_CB_ID :
+          hsai->RxHalfCpltCallback = pCallback;
+          break;
+        case HAL_SAI_TX_COMPLETE_CB_ID :
+          hsai->TxCpltCallback = pCallback;
+          break;
+        case HAL_SAI_TX_HALFCOMPLETE_CB_ID :
+          hsai->TxHalfCpltCallback = pCallback;
+          break;
+        case HAL_SAI_ERROR_CB_ID :
+          hsai->ErrorCallback = pCallback;
+          break;
+        case HAL_SAI_MSPINIT_CB_ID :
+          hsai->MspInitCallback = pCallback;
+          break;
+        case HAL_SAI_MSPDEINIT_CB_ID :
+          hsai->MspDeInitCallback = pCallback;
+          break;
+        default :
+          /* update the error code */
+          hsai->ErrorCode |= HAL_SAI_ERROR_INVALID_CALLBACK;
+          /* update return status */
+          status = HAL_ERROR;
+          break;
+      }
+    }
+    else if (HAL_SAI_STATE_RESET == hsai->State)
+    {
+      switch (CallbackID)
+      {
+        case HAL_SAI_MSPINIT_CB_ID :
+          hsai->MspInitCallback = pCallback;
+          break;
+        case HAL_SAI_MSPDEINIT_CB_ID :
+          hsai->MspDeInitCallback = pCallback;
+          break;
+        default :
+          /* update the error code */
+          hsai->ErrorCode |= HAL_SAI_ERROR_INVALID_CALLBACK;
+          /* update return status */
+          status = HAL_ERROR;
+          break;
+      }
+    }
+    else
+    {
+      /* update the error code */
+      hsai->ErrorCode |= HAL_SAI_ERROR_INVALID_CALLBACK;
+      /* update return status */
+      status = HAL_ERROR;
+    }
+  }
+  return status;
+}
+
+/**
+  * @brief  Unregister a user SAI callback.
+  *         SAI callback is redirected to the weak predefined callback.
+  * @param  hsai SAI handle.
+  * @param  CallbackID ID of the callback to be unregistered.
+  *         This parameter can be one of the following values:
+  *           @arg @ref HAL_SAI_RX_COMPLETE_CB_ID receive complete callback ID.
+  *           @arg @ref HAL_SAI_RX_HALFCOMPLETE_CB_ID receive half complete callback ID.
+  *           @arg @ref HAL_SAI_TX_COMPLETE_CB_ID transmit complete callback ID.
+  *           @arg @ref HAL_SAI_TX_HALFCOMPLETE_CB_ID transmit half complete callback ID.
+  *           @arg @ref HAL_SAI_ERROR_CB_ID error callback ID.
+  *           @arg @ref HAL_SAI_MSPINIT_CB_ID MSP init callback ID.
+  *           @arg @ref HAL_SAI_MSPDEINIT_CB_ID MSP de-init callback ID.
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_SAI_UnRegisterCallback(SAI_HandleTypeDef        *hsai,
+                                             HAL_SAI_CallbackIDTypeDef CallbackID)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (HAL_SAI_STATE_READY == hsai->State)
+  {
+    switch (CallbackID)
+    {
+      case HAL_SAI_RX_COMPLETE_CB_ID :
+        hsai->RxCpltCallback = HAL_SAI_RxCpltCallback;
+        break;
+      case HAL_SAI_RX_HALFCOMPLETE_CB_ID :
+        hsai->RxHalfCpltCallback = HAL_SAI_RxHalfCpltCallback;
+        break;
+      case HAL_SAI_TX_COMPLETE_CB_ID :
+        hsai->TxCpltCallback = HAL_SAI_TxCpltCallback;
+        break;
+      case HAL_SAI_TX_HALFCOMPLETE_CB_ID :
+        hsai->TxHalfCpltCallback = HAL_SAI_TxHalfCpltCallback;
+        break;
+      case HAL_SAI_ERROR_CB_ID :
+        hsai->ErrorCallback = HAL_SAI_ErrorCallback;
+        break;
+      case HAL_SAI_MSPINIT_CB_ID :
+        hsai->MspInitCallback = HAL_SAI_MspInit;
+        break;
+      case HAL_SAI_MSPDEINIT_CB_ID :
+        hsai->MspDeInitCallback = HAL_SAI_MspDeInit;
+        break;
+      default :
+        /* update the error code */
+        hsai->ErrorCode |= HAL_SAI_ERROR_INVALID_CALLBACK;
+        /* update return status */
+        status = HAL_ERROR;
+        break;
+    }
+  }
+  else if (HAL_SAI_STATE_RESET == hsai->State)
+  {
+    switch (CallbackID)
+    {
+      case HAL_SAI_MSPINIT_CB_ID :
+        hsai->MspInitCallback = HAL_SAI_MspInit;
+        break;
+      case HAL_SAI_MSPDEINIT_CB_ID :
+        hsai->MspDeInitCallback = HAL_SAI_MspDeInit;
+        break;
+      default :
+        /* update the error code */
+        hsai->ErrorCode |= HAL_SAI_ERROR_INVALID_CALLBACK;
+        /* update return status */
+        status = HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    /* update the error code */
+    hsai->ErrorCode |= HAL_SAI_ERROR_INVALID_CALLBACK;
+    /* update return status */
+    status = HAL_ERROR;
+  }
+  return status;
+}
+#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+
+/** @defgroup SAI_Exported_Functions_Group2 IO operation functions
+  * @brief    Data transfers functions
+  *
+@verbatim
+  ==============================================================================
+                      ##### IO operation functions #####
+  ==============================================================================
+  [..]
+    This subsection provides a set of functions allowing to manage the SAI data
+    transfers.
+
+    (+) There are two modes of transfer:
+      (++) Blocking mode : The communication is performed in the polling mode.
+           The status of all data processing is returned by the same function
+           after finishing transfer.
+      (++) No-Blocking mode : The communication is performed using Interrupts
+           or DMA. These functions return the status of the transfer startup.
+           The end of the data processing will be indicated through the
+           dedicated SAI IRQ when using Interrupt mode or the DMA IRQ when
+           using DMA mode.
+
+    (+) Blocking mode functions are :
+      (++) HAL_SAI_Transmit()
+      (++) HAL_SAI_Receive()
+
+    (+) Non Blocking mode functions with Interrupt are :
+      (++) HAL_SAI_Transmit_IT()
+      (++) HAL_SAI_Receive_IT()
+
+    (+) Non Blocking mode functions with DMA are :
+      (++) HAL_SAI_Transmit_DMA()
+      (++) HAL_SAI_Receive_DMA()
+
+    (+) A set of Transfer Complete Callbacks are provided in non Blocking mode:
+      (++) HAL_SAI_TxCpltCallback()
+      (++) HAL_SAI_RxCpltCallback()
+      (++) HAL_SAI_ErrorCallback()
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Transmit an amount of data in blocking mode.
+  * @param  hsai pointer to a SAI_HandleTypeDef structure that contains
+  *               the configuration information for SAI module.
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @param  Timeout Timeout duration
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SAI_Transmit(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+  uint32_t tickstart = HAL_GetTick();
+
+  if ((pData == NULL) || (Size == 0))
+  {
+    return  HAL_ERROR;
+  }
+
+  if (hsai->State == HAL_SAI_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hsai);
+
+    hsai->XferSize = Size;
+    hsai->XferCount = Size;
+    hsai->pBuffPtr = pData;
+    hsai->State = HAL_SAI_STATE_BUSY_TX;
+    hsai->ErrorCode = HAL_SAI_ERROR_NONE;
+
+    /* Check if the SAI is already enabled */
+    if ((hsai->Instance->CR1 & SAI_xCR1_SAIEN) == RESET)
+    {
+      /* fill the fifo with data before to enabled the SAI */
+      SAI_FillFifo(hsai);
+      /* Enable SAI peripheral */
+      __HAL_SAI_ENABLE(hsai);
+    }
+
+    while (hsai->XferCount > 0U)
+    {
+      /* Write data if the FIFO is not full */
+      if ((hsai->Instance->SR & SAI_xSR_FLVL) != SAI_FIFOSTATUS_FULL)
+      {
+        if ((hsai->Init.DataSize == SAI_DATASIZE_8) && (hsai->Init.CompandingMode == SAI_NOCOMPANDING))
+        {
+          hsai->Instance->DR = (*hsai->pBuffPtr++);
+        }
+        else if (hsai->Init.DataSize <= SAI_DATASIZE_16)
+        {
+          hsai->Instance->DR = *((uint16_t *)hsai->pBuffPtr);
+          hsai->pBuffPtr += 2U;
+        }
+        else
+        {
+          hsai->Instance->DR = *((uint32_t *)hsai->pBuffPtr);
+          hsai->pBuffPtr += 4U;
+        }
+        hsai->XferCount--;
+      }
+      else
+      {
+        /* Check for the Timeout */
+        if ((Timeout != HAL_MAX_DELAY) && ((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout)))
+        {
+          /* Update error code */
+          hsai->ErrorCode |= HAL_SAI_ERROR_TIMEOUT;
+
+          /* Clear all the flags */
+          hsai->Instance->CLRFR = 0xFFFFFFFFU;
+
+          /* Disable SAI peripheral */
+          SAI_Disable(hsai);
+
+          /* Flush the fifo */
+          SET_BIT(hsai->Instance->CR2, SAI_xCR2_FFLUSH);
+
+          /* Change the SAI state */
+          hsai->State = HAL_SAI_STATE_READY;
+
+          /* Process Unlocked */
+          __HAL_UNLOCK(hsai);
+
+          return HAL_ERROR;
+        }
+      }
+    }
+
+    hsai->State = HAL_SAI_STATE_READY;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hsai);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Receive an amount of data in blocking mode.
+  * @param  hsai pointer to a SAI_HandleTypeDef structure that contains
+  *               the configuration information for SAI module.
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be received
+  * @param  Timeout Timeout duration
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SAI_Receive(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+  uint32_t tickstart = HAL_GetTick();
+
+  if ((pData == NULL) || (Size == 0))
+  {
+    return  HAL_ERROR;
+  }
+
+  if (hsai->State == HAL_SAI_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hsai);
+
+    hsai->pBuffPtr = pData;
+    hsai->XferSize = Size;
+    hsai->XferCount = Size;
+    hsai->State = HAL_SAI_STATE_BUSY_RX;
+    hsai->ErrorCode = HAL_SAI_ERROR_NONE;
+
+    /* Check if the SAI is already enabled */
+    if ((hsai->Instance->CR1 & SAI_xCR1_SAIEN) == RESET)
+    {
+      /* Enable SAI peripheral */
+      __HAL_SAI_ENABLE(hsai);
+    }
+
+    /* Receive data */
+    while (hsai->XferCount > 0U)
+    {
+      if ((hsai->Instance->SR & SAI_xSR_FLVL) != SAI_FIFOSTATUS_EMPTY)
+      {
+        if ((hsai->Init.DataSize == SAI_DATASIZE_8) && (hsai->Init.CompandingMode == SAI_NOCOMPANDING))
+        {
+          (*hsai->pBuffPtr++) = hsai->Instance->DR;
+        }
+        else if (hsai->Init.DataSize <= SAI_DATASIZE_16)
+        {
+          *((uint16_t *)hsai->pBuffPtr) = hsai->Instance->DR;
+          hsai->pBuffPtr += 2U;
+        }
+        else
+        {
+          *((uint32_t *)hsai->pBuffPtr) = hsai->Instance->DR;
+          hsai->pBuffPtr += 4U;
+        }
+        hsai->XferCount--;
+      }
+      else
+      {
+        /* Check for the Timeout */
+        if ((Timeout != HAL_MAX_DELAY) && ((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout)))
+        {
+          /* Update error code */
+          hsai->ErrorCode |= HAL_SAI_ERROR_TIMEOUT;
+
+          /* Clear all the flags */
+          hsai->Instance->CLRFR = 0xFFFFFFFFU;
+
+          /* Disable SAI peripheral */
+          SAI_Disable(hsai);
+
+          /* Flush the fifo */
+          SET_BIT(hsai->Instance->CR2, SAI_xCR2_FFLUSH);
+
+          /* Change the SAI state */
+          hsai->State = HAL_SAI_STATE_READY;
+
+          /* Process Unlocked */
+          __HAL_UNLOCK(hsai);
+
+          return HAL_ERROR;
+        }
+      }
+    }
+
+    hsai->State = HAL_SAI_STATE_READY;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hsai);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Transmit an amount of data in non-blocking mode with Interrupt.
+  * @param  hsai pointer to a SAI_HandleTypeDef structure that contains
+  *               the configuration information for SAI module.
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SAI_Transmit_IT(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size)
+{
+  if ((pData == NULL) || (Size == 0))
+  {
+    return  HAL_ERROR;
+  }
+
+  if (hsai->State == HAL_SAI_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hsai);
+
+    hsai->pBuffPtr = pData;
+    hsai->XferSize = Size;
+    hsai->XferCount = Size;
+    hsai->ErrorCode = HAL_SAI_ERROR_NONE;
+    hsai->State = HAL_SAI_STATE_BUSY_TX;
+
+    if ((hsai->Init.DataSize == SAI_DATASIZE_8) && (hsai->Init.CompandingMode == SAI_NOCOMPANDING))
+    {
+      hsai->InterruptServiceRoutine = SAI_Transmit_IT8Bit;
+    }
+    else if (hsai->Init.DataSize <= SAI_DATASIZE_16)
+    {
+      hsai->InterruptServiceRoutine = SAI_Transmit_IT16Bit;
+    }
+    else
+    {
+      hsai->InterruptServiceRoutine = SAI_Transmit_IT32Bit;
+    }
+
+    /* Fill the fifo before starting the communication */
+    SAI_FillFifo(hsai);
+
+    /* Enable FRQ and OVRUDR interrupts */
+    __HAL_SAI_ENABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT));
+
+    /* Check if the SAI is already enabled */
+    if ((hsai->Instance->CR1 & SAI_xCR1_SAIEN) == RESET)
+    {
+      /* Enable SAI peripheral */
+      __HAL_SAI_ENABLE(hsai);
+    }
+    /* Process Unlocked */
+    __HAL_UNLOCK(hsai);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Receive an amount of data in non-blocking mode with Interrupt.
+  * @param  hsai pointer to a SAI_HandleTypeDef structure that contains
+  *               the configuration information for SAI module.
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be received
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SAI_Receive_IT(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size)
+{
+  if ((pData == NULL) || (Size == 0))
+  {
+    return  HAL_ERROR;
+  }
+
+  if (hsai->State == HAL_SAI_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hsai);
+
+    hsai->pBuffPtr = pData;
+    hsai->XferSize = Size;
+    hsai->XferCount = Size;
+    hsai->ErrorCode = HAL_SAI_ERROR_NONE;
+    hsai->State = HAL_SAI_STATE_BUSY_RX;
+
+    if ((hsai->Init.DataSize == SAI_DATASIZE_8) && (hsai->Init.CompandingMode == SAI_NOCOMPANDING))
+    {
+      hsai->InterruptServiceRoutine = SAI_Receive_IT8Bit;
+    }
+    else if (hsai->Init.DataSize <= SAI_DATASIZE_16)
+    {
+      hsai->InterruptServiceRoutine = SAI_Receive_IT16Bit;
+    }
+    else
+    {
+      hsai->InterruptServiceRoutine = SAI_Receive_IT32Bit;
+    }
+
+    /* Enable TXE and OVRUDR interrupts */
+    __HAL_SAI_ENABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT));
+
+    /* Check if the SAI is already enabled */
+    if ((hsai->Instance->CR1 & SAI_xCR1_SAIEN) == RESET)
+    {
+      /* Enable SAI peripheral */
+      __HAL_SAI_ENABLE(hsai);
+    }
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hsai);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief Pause the audio stream playing from the Media.
+  * @param  hsai pointer to a SAI_HandleTypeDef structure that contains
+  *               the configuration information for SAI module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SAI_DMAPause(SAI_HandleTypeDef *hsai)
+{
+  /* Process Locked */
+  __HAL_LOCK(hsai);
+
+  /* Pause the audio file playing by disabling the SAI DMA requests */
+  hsai->Instance->CR1 &= ~SAI_xCR1_DMAEN;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hsai);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief Resume the audio stream playing from the Media.
+  * @param  hsai pointer to a SAI_HandleTypeDef structure that contains
+  *               the configuration information for SAI module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SAI_DMAResume(SAI_HandleTypeDef *hsai)
+{
+  /* Process Locked */
+  __HAL_LOCK(hsai);
+
+  /* Enable the SAI DMA requests */
+  hsai->Instance->CR1 |= SAI_xCR1_DMAEN;
+
+  /* If the SAI peripheral is still not enabled, enable it */
+  if ((hsai->Instance->CR1 & SAI_xCR1_SAIEN) == RESET)
+  {
+    /* Enable SAI peripheral */
+    __HAL_SAI_ENABLE(hsai);
+  }
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hsai);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief Stop the audio stream playing from the Media.
+  * @param  hsai pointer to a SAI_HandleTypeDef structure that contains
+  *               the configuration information for SAI module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SAI_DMAStop(SAI_HandleTypeDef *hsai)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Process Locked */
+  __HAL_LOCK(hsai);
+
+  /* Disable the SAI DMA request */
+  hsai->Instance->CR1 &= ~SAI_xCR1_DMAEN;
+
+  /* Abort the SAI Tx DMA Stream */
+  if ((hsai->hdmatx != NULL) && (hsai->State == HAL_SAI_STATE_BUSY_TX))
+  {
+    if (HAL_DMA_Abort(hsai->hdmatx) != HAL_OK)
+    {
+      /* If the DMA Tx errorCode is different from DMA No Transfer then return Error */
+      if (hsai->hdmatx->ErrorCode != HAL_DMA_ERROR_NO_XFER)
+      {
+        status = HAL_ERROR;
+        hsai->ErrorCode |= HAL_SAI_ERROR_DMA;
+      }
+    }
+  }
+
+  /* Abort the SAI Rx DMA Stream */
+  if ((hsai->hdmarx != NULL) && (hsai->State == HAL_SAI_STATE_BUSY_RX))
+  {
+    if (HAL_DMA_Abort(hsai->hdmarx) != HAL_OK)
+    {
+      /* If the DMA Rx errorCode is different from DMA No Transfer then return Error */
+      if (hsai->hdmarx->ErrorCode != HAL_DMA_ERROR_NO_XFER)
+      {
+        status = HAL_ERROR;
+        hsai->ErrorCode |= HAL_SAI_ERROR_DMA;
+      }
+    }
+  }
+
+  /* Disable SAI peripheral */
+  SAI_Disable(hsai);
+
+  /* Flush the fifo */
+  SET_BIT(hsai->Instance->CR2, SAI_xCR2_FFLUSH);
+
+  /* Set hsai state to ready */
+  hsai->State = HAL_SAI_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hsai);
+
+  return status;
+}
+
+/**
+  * @brief Abort the current transfer and disable the SAI.
+  * @param  hsai pointer to a SAI_HandleTypeDef structure that contains
+  *               the configuration information for SAI module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SAI_Abort(SAI_HandleTypeDef *hsai)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Process Locked */
+  __HAL_LOCK(hsai);
+
+  /* Check SAI DMA is enabled or not */
+  if ((hsai->Instance->CR1 & SAI_xCR1_DMAEN) == SAI_xCR1_DMAEN)
+  {
+    /* Disable the SAI DMA request */
+    hsai->Instance->CR1 &= ~SAI_xCR1_DMAEN;
+
+    /* Abort the SAI Tx DMA Stream */
+    if ((hsai->hdmatx != NULL) && (hsai->State == HAL_SAI_STATE_BUSY_TX))
+    {
+      if (HAL_DMA_Abort(hsai->hdmatx) != HAL_OK)
+      {
+        /* If the DMA Tx errorCode is different from DMA No Transfer then return Error */
+        if (hsai->hdmatx->ErrorCode != HAL_DMA_ERROR_NO_XFER)
+        {
+          status = HAL_ERROR;
+          hsai->ErrorCode |= HAL_SAI_ERROR_DMA;
+        }
+      }
+    }
+
+    /* Abort the SAI Rx DMA Stream */
+    if ((hsai->hdmarx != NULL) && (hsai->State == HAL_SAI_STATE_BUSY_RX))
+    {
+      if (HAL_DMA_Abort(hsai->hdmarx) != HAL_OK)
+      {
+        /* If the DMA Rx errorCode is different from DMA No Transfer then return Error */
+        if (hsai->hdmarx->ErrorCode != HAL_DMA_ERROR_NO_XFER)
+        {
+          status = HAL_ERROR;
+          hsai->ErrorCode |= HAL_SAI_ERROR_DMA;
+        }
+      }
+    }
+  }
+
+  /* Disabled All interrupt and clear all the flag */
+  hsai->Instance->IMR = 0U;
+  hsai->Instance->CLRFR = 0xFFFFFFFFU;
+
+  /* Disable SAI peripheral */
+  SAI_Disable(hsai);
+
+  /* Flush the fifo */
+  SET_BIT(hsai->Instance->CR2, SAI_xCR2_FFLUSH);
+
+  /* Set hsai state to ready */
+  hsai->State = HAL_SAI_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hsai);
+
+  return status;
+}
+
+/**
+  * @brief  Transmit an amount of data in non-blocking mode with DMA.
+  * @param  hsai pointer to a SAI_HandleTypeDef structure that contains
+  *               the configuration information for SAI module.
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SAI_Transmit_DMA(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size)
+{
+  uint32_t tickstart = HAL_GetTick();
+
+  if ((pData == NULL) || (Size == 0))
+  {
+    return  HAL_ERROR;
+  }
+
+  if (hsai->State == HAL_SAI_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hsai);
+
+    hsai->pBuffPtr = pData;
+    hsai->XferSize = Size;
+    hsai->XferCount = Size;
+    hsai->ErrorCode = HAL_SAI_ERROR_NONE;
+    hsai->State = HAL_SAI_STATE_BUSY_TX;
+
+    /* Set the SAI Tx DMA Half transfer complete callback */
+    hsai->hdmatx->XferHalfCpltCallback = SAI_DMATxHalfCplt;
+
+    /* Set the SAI TxDMA transfer complete callback */
+    hsai->hdmatx->XferCpltCallback = SAI_DMATxCplt;
+
+    /* Set the DMA error callback */
+    hsai->hdmatx->XferErrorCallback = SAI_DMAError;
+
+    /* Set the DMA Tx abort callback */
+    hsai->hdmatx->XferAbortCallback = NULL;
+
+    /* Enable the Tx DMA Stream */
+    if (HAL_DMA_Start_IT(hsai->hdmatx, (uint32_t)hsai->pBuffPtr, (uint32_t)&hsai->Instance->DR, hsai->XferSize) != HAL_OK)
+    {
+      __HAL_UNLOCK(hsai);
+      return  HAL_ERROR;
+    }
+
+    /* Enable the interrupts for error handling */
+    __HAL_SAI_ENABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_DMA));
+
+    /* Enable SAI Tx DMA Request */
+    hsai->Instance->CR1 |= SAI_xCR1_DMAEN;
+
+    /* Wait until FIFO is not empty */
+    while ((hsai->Instance->SR & SAI_xSR_FLVL) == SAI_FIFOSTATUS_EMPTY)
+    {
+      /* Check for the Timeout */
+      if ((HAL_GetTick() - tickstart) > SAI_LONG_TIMEOUT)
+      {
+        /* Update error code */
+        hsai->ErrorCode |= HAL_SAI_ERROR_TIMEOUT;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hsai);
+
+        return HAL_TIMEOUT;
+      }
+    }
+
+    /* Check if the SAI is already enabled */
+    if ((hsai->Instance->CR1 & SAI_xCR1_SAIEN) == 0U)
+    {
+      /* Enable SAI peripheral */
+      __HAL_SAI_ENABLE(hsai);
+    }
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hsai);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Receive an amount of data in non-blocking mode with DMA.
+  * @param  hsai pointer to a SAI_HandleTypeDef structure that contains
+  *               the configuration information for SAI module.
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be received
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SAI_Receive_DMA(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size)
+{
+  if ((pData == NULL) || (Size == 0))
+  {
+    return  HAL_ERROR;
+  }
+
+  if (hsai->State == HAL_SAI_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hsai);
+
+    hsai->pBuffPtr = pData;
+    hsai->XferSize = Size;
+    hsai->XferCount = Size;
+    hsai->ErrorCode = HAL_SAI_ERROR_NONE;
+    hsai->State = HAL_SAI_STATE_BUSY_RX;
+
+    /* Set the SAI Rx DMA Half transfer complete callback */
+    hsai->hdmarx->XferHalfCpltCallback = SAI_DMARxHalfCplt;
+
+    /* Set the SAI Rx DMA transfer complete callback */
+    hsai->hdmarx->XferCpltCallback = SAI_DMARxCplt;
+
+    /* Set the DMA error callback */
+    hsai->hdmarx->XferErrorCallback = SAI_DMAError;
+
+    /* Set the DMA Rx abort callback */
+    hsai->hdmarx->XferAbortCallback = NULL;
+
+    /* Enable the Rx DMA Stream */
+    if (HAL_DMA_Start_IT(hsai->hdmarx, (uint32_t)&hsai->Instance->DR, (uint32_t)hsai->pBuffPtr, hsai->XferSize) != HAL_OK)
+    {
+      __HAL_UNLOCK(hsai);
+      return  HAL_ERROR;
+    }
+
+    /* Enable the interrupts for error handling */
+    __HAL_SAI_ENABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_DMA));
+
+    /* Enable SAI Rx DMA Request */
+    hsai->Instance->CR1 |= SAI_xCR1_DMAEN;
+
+    /* Check if the SAI is already enabled */
+    if ((hsai->Instance->CR1 & SAI_xCR1_SAIEN) == RESET)
+    {
+      /* Enable SAI peripheral */
+      __HAL_SAI_ENABLE(hsai);
+    }
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hsai);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Enable the Tx mute mode.
+  * @param  hsai pointer to a SAI_HandleTypeDef structure that contains
+  *               the configuration information for SAI module.
+  * @param  val  value sent during the mute @ref SAI_Block_Mute_Value
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SAI_EnableTxMuteMode(SAI_HandleTypeDef *hsai, uint16_t val)
+{
+  assert_param(IS_SAI_BLOCK_MUTE_VALUE(val));
+
+  if (hsai->State != HAL_SAI_STATE_RESET)
+  {
+    CLEAR_BIT(hsai->Instance->CR2, SAI_xCR2_MUTEVAL | SAI_xCR2_MUTE);
+    SET_BIT(hsai->Instance->CR2, SAI_xCR2_MUTE | val);
+    return HAL_OK;
+  }
+  return HAL_ERROR;
+}
+
+/**
+  * @brief  Disable the Tx mute mode.
+  * @param  hsai pointer to a SAI_HandleTypeDef structure that contains
+  *               the configuration information for SAI module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SAI_DisableTxMuteMode(SAI_HandleTypeDef *hsai)
+{
+  if (hsai->State != HAL_SAI_STATE_RESET)
+  {
+    CLEAR_BIT(hsai->Instance->CR2, SAI_xCR2_MUTEVAL | SAI_xCR2_MUTE);
+    return HAL_OK;
+  }
+  return HAL_ERROR;
+}
+
+/**
+  * @brief  Enable the Rx mute detection.
+  * @param  hsai pointer to a SAI_HandleTypeDef structure that contains
+  *               the configuration information for SAI module.
+  * @param  callback function called when the mute is detected.
+  * @param  counter number a data before mute detection max 63.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SAI_EnableRxMuteMode(SAI_HandleTypeDef *hsai, SAIcallback callback, uint16_t counter)
+{
+  assert_param(IS_SAI_BLOCK_MUTE_COUNTER(counter));
+
+  if (hsai->State != HAL_SAI_STATE_RESET)
+  {
+    /* set the mute counter */
+    CLEAR_BIT(hsai->Instance->CR2, SAI_xCR2_MUTECNT);
+    SET_BIT(hsai->Instance->CR2, (uint32_t)((uint32_t)counter << SAI_xCR2_MUTECNT_Pos));
+    hsai->mutecallback = callback;
+    /* enable the IT interrupt */
+    __HAL_SAI_ENABLE_IT(hsai, SAI_IT_MUTEDET);
+    return HAL_OK;
+  }
+  return HAL_ERROR;
+}
+
+/**
+  * @brief  Disable the Rx mute detection.
+  * @param  hsai pointer to a SAI_HandleTypeDef structure that contains
+  *               the configuration information for SAI module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SAI_DisableRxMuteMode(SAI_HandleTypeDef *hsai)
+{
+  if (hsai->State != HAL_SAI_STATE_RESET)
+  {
+    /* set the mutecallback to NULL */
+    hsai->mutecallback = (SAIcallback)NULL;
+    /* enable the IT interrupt */
+    __HAL_SAI_DISABLE_IT(hsai, SAI_IT_MUTEDET);
+    return HAL_OK;
+  }
+  return HAL_ERROR;
+}
+
+/**
+  * @brief  Handle SAI interrupt request.
+  * @param  hsai pointer to a SAI_HandleTypeDef structure that contains
+  *               the configuration information for SAI module.
+  * @retval None
+  */
+void HAL_SAI_IRQHandler(SAI_HandleTypeDef *hsai)
+{
+  if (hsai->State != HAL_SAI_STATE_RESET)
+  {
+    uint32_t itflags = hsai->Instance->SR;
+    uint32_t itsources = hsai->Instance->IMR;
+    uint32_t cr1config = hsai->Instance->CR1;
+    uint32_t tmperror;
+
+    /* SAI Fifo request interrupt occurred ------------------------------------*/
+    if (((itflags & SAI_xSR_FREQ) == SAI_xSR_FREQ) && ((itsources & SAI_IT_FREQ) == SAI_IT_FREQ))
+    {
+      hsai->InterruptServiceRoutine(hsai);
+    }
+    /* SAI Overrun error interrupt occurred ----------------------------------*/
+    else if (((itflags & SAI_FLAG_OVRUDR) == SAI_FLAG_OVRUDR) && ((itsources & SAI_IT_OVRUDR) == SAI_IT_OVRUDR))
+    {
+      /* Clear the SAI Overrun flag */
+      __HAL_SAI_CLEAR_FLAG(hsai, SAI_FLAG_OVRUDR);
+
+      /* Get the SAI error code */
+      tmperror = ((hsai->State == HAL_SAI_STATE_BUSY_RX) ? HAL_SAI_ERROR_OVR : HAL_SAI_ERROR_UDR);
+
+      /* Change the SAI error code */
+      hsai->ErrorCode |= tmperror;
+
+      /* the transfer is not stopped, we will forward the information to the user and we let the user decide what needs to be done */
+#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
+      hsai->ErrorCallback(hsai);
+#else
+      HAL_SAI_ErrorCallback(hsai);
+#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */
+    }
+    /* SAI mutedet interrupt occurred ----------------------------------*/
+    else if (((itflags & SAI_FLAG_MUTEDET) == SAI_FLAG_MUTEDET) && ((itsources & SAI_IT_MUTEDET) == SAI_IT_MUTEDET))
+    {
+      /* Clear the SAI mutedet flag */
+      __HAL_SAI_CLEAR_FLAG(hsai, SAI_FLAG_MUTEDET);
+
+      /* call the call back function */
+      if (hsai->mutecallback != (SAIcallback)NULL)
+      {
+        /* inform the user that an RX mute event has been detected */
+        hsai->mutecallback();
+      }
+    }
+    /* SAI AFSDET interrupt occurred ----------------------------------*/
+    else if (((itflags & SAI_FLAG_AFSDET) == SAI_FLAG_AFSDET) && ((itsources & SAI_IT_AFSDET) == SAI_IT_AFSDET))
+    {
+      /* Clear the SAI AFSDET flag */
+      __HAL_SAI_CLEAR_FLAG(hsai, SAI_FLAG_AFSDET);
+
+      /* Change the SAI error code */
+      hsai->ErrorCode |= HAL_SAI_ERROR_AFSDET;
+
+      /* Check SAI DMA is enabled or not */
+      if ((cr1config & SAI_xCR1_DMAEN) == SAI_xCR1_DMAEN)
+      {
+        /* Abort the SAI DMA Streams */
+        if (hsai->hdmatx != NULL)
+        {
+          /* Set the DMA Tx abort callback */
+          hsai->hdmatx->XferAbortCallback = SAI_DMAAbort;
+
+          /* Abort DMA in IT mode */
+          HAL_DMA_Abort_IT(hsai->hdmatx);
+        }
+        else if (hsai->hdmarx != NULL)
+        {
+          /* Set the DMA Rx abort callback */
+          hsai->hdmarx->XferAbortCallback = SAI_DMAAbort;
+
+          /* Abort DMA in IT mode */
+          HAL_DMA_Abort_IT(hsai->hdmarx);
+        }
+      }
+      else
+      {
+        /* Abort SAI */
+        HAL_SAI_Abort(hsai);
+
+        /* Set error callback */
+#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
+        hsai->ErrorCallback(hsai);
+#else
+        HAL_SAI_ErrorCallback(hsai);
+#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */
+      }
+    }
+    /* SAI LFSDET interrupt occurred ----------------------------------*/
+    else if (((itflags & SAI_FLAG_LFSDET) == SAI_FLAG_LFSDET) && ((itsources & SAI_IT_LFSDET) == SAI_IT_LFSDET))
+    {
+      /* Clear the SAI LFSDET flag */
+      __HAL_SAI_CLEAR_FLAG(hsai, SAI_FLAG_LFSDET);
+
+      /* Change the SAI error code */
+      hsai->ErrorCode |= HAL_SAI_ERROR_LFSDET;
+
+      /* Check SAI DMA is enabled or not */
+      if ((cr1config & SAI_xCR1_DMAEN) == SAI_xCR1_DMAEN)
+      {
+        /* Abort the SAI DMA Streams */
+        if (hsai->hdmatx != NULL)
+        {
+          /* Set the DMA Tx abort callback */
+          hsai->hdmatx->XferAbortCallback = SAI_DMAAbort;
+
+          /* Abort DMA in IT mode */
+          HAL_DMA_Abort_IT(hsai->hdmatx);
+        }
+        else if (hsai->hdmarx != NULL)
+        {
+          /* Set the DMA Rx abort callback */
+          hsai->hdmarx->XferAbortCallback = SAI_DMAAbort;
+
+          /* Abort DMA in IT mode */
+          HAL_DMA_Abort_IT(hsai->hdmarx);
+        }
+      }
+      else
+      {
+        /* Abort SAI */
+        HAL_SAI_Abort(hsai);
+
+        /* Set error callback */
+#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
+        hsai->ErrorCallback(hsai);
+#else
+        HAL_SAI_ErrorCallback(hsai);
+#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */
+      }
+    }
+    /* SAI WCKCFG interrupt occurred ----------------------------------*/
+    else if (((itflags & SAI_FLAG_WCKCFG) == SAI_FLAG_WCKCFG) && ((itsources & SAI_IT_WCKCFG) == SAI_IT_WCKCFG))
+    {
+      /* Clear the SAI WCKCFG flag */
+      __HAL_SAI_CLEAR_FLAG(hsai, SAI_FLAG_WCKCFG);
+
+      /* Change the SAI error code */
+      hsai->ErrorCode |= HAL_SAI_ERROR_WCKCFG;
+
+      /* Check SAI DMA is enabled or not */
+      if ((cr1config & SAI_xCR1_DMAEN) == SAI_xCR1_DMAEN)
+      {
+        /* Abort the SAI DMA Streams */
+        if (hsai->hdmatx != NULL)
+        {
+          /* Set the DMA Tx abort callback */
+          hsai->hdmatx->XferAbortCallback = SAI_DMAAbort;
+
+          /* Abort DMA in IT mode */
+          HAL_DMA_Abort_IT(hsai->hdmatx);
+        }
+        else if (hsai->hdmarx != NULL)
+        {
+          /* Set the DMA Rx abort callback */
+          hsai->hdmarx->XferAbortCallback = SAI_DMAAbort;
+
+          /* Abort DMA in IT mode */
+          HAL_DMA_Abort_IT(hsai->hdmarx);
+        }
+      }
+      else
+      {
+        /* If WCKCFG occurs, SAI audio block is automatically disabled */
+        /* Disable all interrupts and clear all flags */
+        hsai->Instance->IMR = 0U;
+        hsai->Instance->CLRFR = 0xFFFFFFFFU;
+
+        /* Set the SAI state to ready to be able to start again the process */
+        hsai->State = HAL_SAI_STATE_READY;
+
+        /* Initialize XferCount */
+        hsai->XferCount = 0U;
+
+        /* SAI error Callback */
+#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
+        hsai->ErrorCallback(hsai);
+#else
+        HAL_SAI_ErrorCallback(hsai);
+#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */
+      }
+    }
+    /* SAI CNRDY interrupt occurred ----------------------------------*/
+    else if (((itflags & SAI_FLAG_CNRDY) == SAI_FLAG_CNRDY) && ((itsources & SAI_IT_CNRDY) == SAI_IT_CNRDY))
+    {
+      /* Clear the SAI CNRDY flag */
+      __HAL_SAI_CLEAR_FLAG(hsai, SAI_FLAG_CNRDY);
+
+      /* Change the SAI error code */
+      hsai->ErrorCode |= HAL_SAI_ERROR_CNREADY;
+
+      /* the transfer is not stopped, we will forward the information to the user and we let the user decide what needs to be done */
+#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
+      hsai->ErrorCallback(hsai);
+#else
+      HAL_SAI_ErrorCallback(hsai);
+#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */
+    }
+    else
+    {
+      /* Nothing to do */
+    }
+  }
+}
+
+/**
+  * @brief Tx Transfer completed callback.
+  * @param  hsai pointer to a SAI_HandleTypeDef structure that contains
+  *                the configuration information for SAI module.
+  * @retval None
+  */
+__weak void HAL_SAI_TxCpltCallback(SAI_HandleTypeDef *hsai)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hsai);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_SAI_TxCpltCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief Tx Transfer Half completed callback.
+  * @param  hsai pointer to a SAI_HandleTypeDef structure that contains
+  *               the configuration information for SAI module.
+  * @retval None
+  */
+__weak void HAL_SAI_TxHalfCpltCallback(SAI_HandleTypeDef *hsai)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hsai);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_SAI_TxHalfCpltCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief Rx Transfer completed callback.
+  * @param  hsai pointer to a SAI_HandleTypeDef structure that contains
+  *               the configuration information for SAI module.
+  * @retval None
+  */
+__weak void HAL_SAI_RxCpltCallback(SAI_HandleTypeDef *hsai)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hsai);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_SAI_RxCpltCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief Rx Transfer half completed callback.
+  * @param  hsai pointer to a SAI_HandleTypeDef structure that contains
+  *               the configuration information for SAI module.
+  * @retval None
+  */
+__weak void HAL_SAI_RxHalfCpltCallback(SAI_HandleTypeDef *hsai)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hsai);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_SAI_RxHalfCpltCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief SAI error callback.
+  * @param  hsai pointer to a SAI_HandleTypeDef structure that contains
+  *               the configuration information for SAI module.
+  * @retval None
+  */
+__weak void HAL_SAI_ErrorCallback(SAI_HandleTypeDef *hsai)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hsai);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_SAI_ErrorCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup SAI_Exported_Functions_Group3 Peripheral State functions
+  * @brief    Peripheral State functions
+  *
+@verbatim
+ ===============================================================================
+                ##### Peripheral State and Errors functions #####
+ ===============================================================================
+  [..]
+    This subsection permits to get in run-time the status of the peripheral
+    and the data flow.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Return the SAI handle state.
+  * @param  hsai pointer to a SAI_HandleTypeDef structure that contains
+  *               the configuration information for SAI module.
+  * @retval HAL state
+  */
+HAL_SAI_StateTypeDef HAL_SAI_GetState(SAI_HandleTypeDef *hsai)
+{
+  return hsai->State;
+}
+
+/**
+  * @brief  Return the SAI error code.
+  * @param  hsai pointer to a SAI_HandleTypeDef structure that contains
+  *              the configuration information for the specified SAI Block.
+  * @retval SAI Error Code
+  */
+uint32_t HAL_SAI_GetError(SAI_HandleTypeDef *hsai)
+{
+  return hsai->ErrorCode;
+}
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup SAI_Private_Functions
+  * @brief      Private functions
+  * @{
+  */
+
+/**
+  * @brief  Initialize the SAI I2S protocol according to the specified parameters
+  *         in the SAI_InitTypeDef and create the associated handle.
+  * @param  hsai pointer to a SAI_HandleTypeDef structure that contains
+  *               the configuration information for SAI module.
+  * @param  protocol one of the supported protocol.
+  * @param  datasize one of the supported datasize @ref SAI_Protocol_DataSize
+  *                the configuration information for SAI module.
+  * @param  nbslot number of slot minimum value is 2 and max is 16.
+  *                    the value must be a multiple of 2.
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef SAI_InitI2S(SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot)
+{
+  hsai->Init.Protocol            = SAI_FREE_PROTOCOL;
+  hsai->Init.FirstBit            = SAI_FIRSTBIT_MSB;
+  /* Compute ClockStrobing according AudioMode */
+  if ((hsai->Init.AudioMode == SAI_MODEMASTER_TX) || (hsai->Init.AudioMode == SAI_MODESLAVE_TX))
+  {
+    /* Transmit */
+    hsai->Init.ClockStrobing     = SAI_CLOCKSTROBING_FALLINGEDGE;
+  }
+  else
+  {
+    /* Receive */
+    hsai->Init.ClockStrobing     = SAI_CLOCKSTROBING_RISINGEDGE;
+  }
+  hsai->FrameInit.FSDefinition   = SAI_FS_CHANNEL_IDENTIFICATION;
+  hsai->SlotInit.SlotActive      = SAI_SLOTACTIVE_ALL;
+  hsai->SlotInit.FirstBitOffset  = 0U;
+  hsai->SlotInit.SlotNumber      = nbslot;
+
+  /* in IS2 the number of slot must be even */
+  if ((nbslot & 0x1U) != 0U)
+  {
+    return HAL_ERROR;
+  }
+
+  if (protocol == SAI_I2S_STANDARD)
+  {
+    hsai->FrameInit.FSPolarity = SAI_FS_ACTIVE_LOW;
+    hsai->FrameInit.FSOffset   = SAI_FS_BEFOREFIRSTBIT;
+  }
+  else
+  {
+    /* SAI_I2S_MSBJUSTIFIED or SAI_I2S_LSBJUSTIFIED */
+    hsai->FrameInit.FSPolarity = SAI_FS_ACTIVE_HIGH;
+    hsai->FrameInit.FSOffset   = SAI_FS_FIRSTBIT;
+  }
+
+  /* Frame definition */
+  switch (datasize)
+  {
+    case SAI_PROTOCOL_DATASIZE_16BIT:
+      hsai->Init.DataSize = SAI_DATASIZE_16;
+      hsai->FrameInit.FrameLength = 32U * (nbslot / 2U);
+      hsai->FrameInit.ActiveFrameLength = 16U * (nbslot / 2U);
+      hsai->SlotInit.SlotSize = SAI_SLOTSIZE_16B;
+      break;
+    case SAI_PROTOCOL_DATASIZE_16BITEXTENDED :
+      hsai->Init.DataSize = SAI_DATASIZE_16;
+      hsai->FrameInit.FrameLength = 64U * (nbslot / 2U);
+      hsai->FrameInit.ActiveFrameLength = 32U * (nbslot / 2U);
+      hsai->SlotInit.SlotSize = SAI_SLOTSIZE_32B;
+      break;
+    case SAI_PROTOCOL_DATASIZE_24BIT:
+      hsai->Init.DataSize = SAI_DATASIZE_24;
+      hsai->FrameInit.FrameLength = 64U * (nbslot / 2U);
+      hsai->FrameInit.ActiveFrameLength = 32U * (nbslot / 2U);
+      hsai->SlotInit.SlotSize = SAI_SLOTSIZE_32B;
+      break;
+    case SAI_PROTOCOL_DATASIZE_32BIT:
+      hsai->Init.DataSize = SAI_DATASIZE_32;
+      hsai->FrameInit.FrameLength = 64U * (nbslot / 2U);
+      hsai->FrameInit.ActiveFrameLength = 32U * (nbslot / 2U);
+      hsai->SlotInit.SlotSize = SAI_SLOTSIZE_32B;
+      break;
+    default :
+      return HAL_ERROR;
+  }
+  if (protocol == SAI_I2S_LSBJUSTIFIED)
+  {
+    if (datasize == SAI_PROTOCOL_DATASIZE_16BITEXTENDED)
+    {
+      hsai->SlotInit.FirstBitOffset = 16U;
+    }
+    if (datasize == SAI_PROTOCOL_DATASIZE_24BIT)
+    {
+      hsai->SlotInit.FirstBitOffset = 8U;
+    }
+  }
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initialize the SAI PCM protocol according to the specified parameters
+  *         in the SAI_InitTypeDef and create the associated handle.
+  * @param  hsai pointer to a SAI_HandleTypeDef structure that contains
+  *               the configuration information for SAI module.
+  * @param  protocol one of the supported protocol
+  * @param  datasize one of the supported datasize @ref SAI_Protocol_DataSize
+  * @param  nbslot number of slot minimum value is 1 and the max is 16.
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef SAI_InitPCM(SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot)
+{
+  hsai->Init.Protocol            = SAI_FREE_PROTOCOL;
+  hsai->Init.FirstBit            = SAI_FIRSTBIT_MSB;
+  /* Compute ClockStrobing according AudioMode */
+  if ((hsai->Init.AudioMode == SAI_MODEMASTER_TX) || (hsai->Init.AudioMode == SAI_MODESLAVE_TX))
+  {
+    /* Transmit */
+    hsai->Init.ClockStrobing     = SAI_CLOCKSTROBING_RISINGEDGE;
+  }
+  else
+  {
+    /* Receive */
+    hsai->Init.ClockStrobing     = SAI_CLOCKSTROBING_FALLINGEDGE;
+  }
+  hsai->FrameInit.FSDefinition   = SAI_FS_STARTFRAME;
+  hsai->FrameInit.FSPolarity     = SAI_FS_ACTIVE_HIGH;
+  hsai->FrameInit.FSOffset       = SAI_FS_BEFOREFIRSTBIT;
+  hsai->SlotInit.FirstBitOffset  = 0U;
+  hsai->SlotInit.SlotNumber      = nbslot;
+  hsai->SlotInit.SlotActive      = SAI_SLOTACTIVE_ALL;
+
+  if (protocol == SAI_PCM_SHORT)
+  {
+    hsai->FrameInit.ActiveFrameLength = 1;
+  }
+  else
+  {
+    /* SAI_PCM_LONG */
+    hsai->FrameInit.ActiveFrameLength = 13;
+  }
+
+  switch (datasize)
+  {
+    case SAI_PROTOCOL_DATASIZE_16BIT:
+      hsai->Init.DataSize = SAI_DATASIZE_16;
+      hsai->FrameInit.FrameLength = 16U * nbslot;
+      hsai->SlotInit.SlotSize = SAI_SLOTSIZE_16B;
+      break;
+    case SAI_PROTOCOL_DATASIZE_16BITEXTENDED :
+      hsai->Init.DataSize = SAI_DATASIZE_16;
+      hsai->FrameInit.FrameLength = 32U * nbslot;
+      hsai->SlotInit.SlotSize = SAI_SLOTSIZE_32B;
+      break;
+    case SAI_PROTOCOL_DATASIZE_24BIT :
+      hsai->Init.DataSize = SAI_DATASIZE_24;
+      hsai->FrameInit.FrameLength = 32U * nbslot;
+      hsai->SlotInit.SlotSize = SAI_SLOTSIZE_32B;
+      break;
+    case SAI_PROTOCOL_DATASIZE_32BIT:
+      hsai->Init.DataSize = SAI_DATASIZE_32;
+      hsai->FrameInit.FrameLength = 32U * nbslot;
+      hsai->SlotInit.SlotSize = SAI_SLOTSIZE_32B;
+      break;
+    default :
+      return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Fill the fifo.
+  * @param  hsai pointer to a SAI_HandleTypeDef structure that contains
+  *               the configuration information for SAI module.
+  * @retval None
+  */
+static void SAI_FillFifo(SAI_HandleTypeDef *hsai)
+{
+  /* fill the fifo with data before to enabled the SAI */
+  while (((hsai->Instance->SR & SAI_xSR_FLVL) != SAI_FIFOSTATUS_FULL) && (hsai->XferCount > 0U))
+  {
+    if ((hsai->Init.DataSize == SAI_DATASIZE_8) && (hsai->Init.CompandingMode == SAI_NOCOMPANDING))
+    {
+      hsai->Instance->DR = (*hsai->pBuffPtr++);
+    }
+    else if (hsai->Init.DataSize <= SAI_DATASIZE_16)
+    {
+      hsai->Instance->DR = *((uint32_t *)hsai->pBuffPtr);
+      hsai->pBuffPtr += 2U;
+    }
+    else
+    {
+      hsai->Instance->DR = *((uint32_t *)hsai->pBuffPtr);
+      hsai->pBuffPtr += 4U;
+    }
+    hsai->XferCount--;
+  }
+}
+
+/**
+  * @brief  Return the interrupt flag to set according the SAI setup.
+  * @param  hsai pointer to a SAI_HandleTypeDef structure that contains
+  *               the configuration information for SAI module.
+  * @param  mode SAI_MODE_DMA or SAI_MODE_IT
+  * @retval the list of the IT flag to enable
+ */
+static uint32_t SAI_InterruptFlag(SAI_HandleTypeDef *hsai, uint32_t mode)
+{
+  uint32_t tmpIT = SAI_IT_OVRUDR;
+
+  if (mode == SAI_MODE_IT)
+  {
+    tmpIT |= SAI_IT_FREQ;
+  }
+
+  if ((hsai->Init.Protocol == SAI_AC97_PROTOCOL) &&
+      ((hsai->Init.AudioMode == SAI_MODESLAVE_RX) || (hsai->Init.AudioMode == SAI_MODEMASTER_RX)))
+  {
+    tmpIT |= SAI_IT_CNRDY;
+  }
+
+  if ((hsai->Init.AudioMode == SAI_MODESLAVE_RX) || (hsai->Init.AudioMode == SAI_MODESLAVE_TX))
+  {
+    tmpIT |= SAI_IT_AFSDET | SAI_IT_LFSDET;
+  }
+  else
+  {
+    /* hsai has been configured in master mode */
+    tmpIT |= SAI_IT_WCKCFG;
+  }
+  return tmpIT;
+}
+
+/**
+  * @brief  Disable the SAI and wait for the disabling.
+  * @param  hsai  pointer to a SAI_HandleTypeDef structure that contains
+  *               the configuration information for SAI module.
+  * @retval None
+  */
+static HAL_StatusTypeDef SAI_Disable(SAI_HandleTypeDef *hsai)
+{
+  uint32_t count = SAI_DEFAULT_TIMEOUT * (SystemCoreClock / 7U / 1000U);
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Disable the SAI instance */
+  __HAL_SAI_DISABLE(hsai);
+
+  do
+  {
+    /* Check for the Timeout */
+    if (count-- == 0U)
+    {
+      /* Update error code */
+      hsai->ErrorCode |= HAL_SAI_ERROR_TIMEOUT;
+      status = HAL_TIMEOUT;
+      break;
+    }
+  }
+  while ((hsai->Instance->CR1 & SAI_xCR1_SAIEN) != RESET);
+
+  return status;
+}
+
+/**
+  * @brief  Tx Handler for Transmit in Interrupt mode 8-Bit transfer.
+  * @param  hsai pointer to a SAI_HandleTypeDef structure that contains
+  *               the configuration information for SAI module.
+  * @retval None
+  */
+static void SAI_Transmit_IT8Bit(SAI_HandleTypeDef *hsai)
+{
+  if (hsai->XferCount == 0U)
+  {
+    /* Handle the end of the transmission */
+    /* Disable FREQ and OVRUDR interrupts */
+    __HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT));
+    hsai->State = HAL_SAI_STATE_READY;
+#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
+    hsai->TxCpltCallback(hsai);
+#else
+    HAL_SAI_TxCpltCallback(hsai);
+#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */
+  }
+  else
+  {
+    /* Write data on DR register */
+    hsai->Instance->DR = (*hsai->pBuffPtr++);
+    hsai->XferCount--;
+  }
+}
+
+/**
+  * @brief  Tx Handler for Transmit in Interrupt mode for 16-Bit transfer.
+  * @param  hsai pointer to a SAI_HandleTypeDef structure that contains
+  *               the configuration information for SAI module.
+  * @retval None
+  */
+static void SAI_Transmit_IT16Bit(SAI_HandleTypeDef *hsai)
+{
+  if (hsai->XferCount == 0U)
+  {
+    /* Handle the end of the transmission */
+    /* Disable FREQ and OVRUDR interrupts */
+    __HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT));
+    hsai->State = HAL_SAI_STATE_READY;
+#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
+    hsai->TxCpltCallback(hsai);
+#else
+    HAL_SAI_TxCpltCallback(hsai);
+#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */
+  }
+  else
+  {
+    /* Write data on DR register */
+    hsai->Instance->DR = *(uint16_t *)hsai->pBuffPtr;
+    hsai->pBuffPtr += 2U;
+    hsai->XferCount--;
+  }
+}
+
+/**
+  * @brief  Tx Handler for Transmit in Interrupt mode for 32-Bit transfer.
+  * @param  hsai pointer to a SAI_HandleTypeDef structure that contains
+  *               the configuration information for SAI module.
+  * @retval None
+  */
+static void SAI_Transmit_IT32Bit(SAI_HandleTypeDef *hsai)
+{
+  if (hsai->XferCount == 0U)
+  {
+    /* Handle the end of the transmission */
+    /* Disable FREQ and OVRUDR interrupts */
+    __HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT));
+    hsai->State = HAL_SAI_STATE_READY;
+#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
+    hsai->TxCpltCallback(hsai);
+#else
+    HAL_SAI_TxCpltCallback(hsai);
+#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */
+  }
+  else
+  {
+    /* Write data on DR register */
+    hsai->Instance->DR = *(uint32_t *)hsai->pBuffPtr;
+    hsai->pBuffPtr += 4U;
+    hsai->XferCount--;
+  }
+}
+
+/**
+  * @brief  Rx Handler for Receive in Interrupt mode 8-Bit transfer.
+  * @param  hsai pointer to a SAI_HandleTypeDef structure that contains
+  *               the configuration information for SAI module.
+  * @retval None
+  */
+static void SAI_Receive_IT8Bit(SAI_HandleTypeDef *hsai)
+{
+  /* Receive data */
+  (*hsai->pBuffPtr++) = hsai->Instance->DR;
+  hsai->XferCount--;
+
+  /* Check end of the transfer */
+  if (hsai->XferCount == 0U)
+  {
+    /* Disable TXE and OVRUDR interrupts */
+    __HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT));
+
+    /* Clear the SAI Overrun flag */
+    __HAL_SAI_CLEAR_FLAG(hsai, SAI_FLAG_OVRUDR);
+
+    hsai->State = HAL_SAI_STATE_READY;
+#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
+    hsai->RxCpltCallback(hsai);
+#else
+    HAL_SAI_RxCpltCallback(hsai);
+#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */
+  }
+}
+
+/**
+  * @brief  Rx Handler for Receive in Interrupt mode for 16-Bit transfer.
+  * @param  hsai pointer to a SAI_HandleTypeDef structure that contains
+  *               the configuration information for SAI module.
+  * @retval None
+  */
+static void SAI_Receive_IT16Bit(SAI_HandleTypeDef *hsai)
+{
+  /* Receive data */
+  *(uint16_t *)hsai->pBuffPtr = hsai->Instance->DR;
+  hsai->pBuffPtr += 2U;
+  hsai->XferCount--;
+
+  /* Check end of the transfer */
+  if (hsai->XferCount == 0U)
+  {
+    /* Disable TXE and OVRUDR interrupts */
+    __HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT));
+
+    /* Clear the SAI Overrun flag */
+    __HAL_SAI_CLEAR_FLAG(hsai, SAI_FLAG_OVRUDR);
+
+    hsai->State = HAL_SAI_STATE_READY;
+#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
+    hsai->RxCpltCallback(hsai);
+#else
+    HAL_SAI_RxCpltCallback(hsai);
+#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */
+  }
+}
+
+/**
+  * @brief  Rx Handler for Receive in Interrupt mode for 32-Bit transfer.
+  * @param  hsai pointer to a SAI_HandleTypeDef structure that contains
+  *               the configuration information for SAI module.
+  * @retval None
+  */
+static void SAI_Receive_IT32Bit(SAI_HandleTypeDef *hsai)
+{
+  /* Receive data */
+  *(uint32_t *)hsai->pBuffPtr = hsai->Instance->DR;
+  hsai->pBuffPtr += 4U;
+  hsai->XferCount--;
+
+  /* Check end of the transfer */
+  if (hsai->XferCount == 0U)
+  {
+    /* Disable TXE and OVRUDR interrupts */
+    __HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT));
+
+    /* Clear the SAI Overrun flag */
+    __HAL_SAI_CLEAR_FLAG(hsai, SAI_FLAG_OVRUDR);
+
+    hsai->State = HAL_SAI_STATE_READY;
+#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
+    hsai->RxCpltCallback(hsai);
+#else
+    HAL_SAI_RxCpltCallback(hsai);
+#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */
+  }
+}
+
+/**
+  * @brief DMA SAI transmit process complete callback.
+  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
+  *               the configuration information for the specified DMA module.
+  * @retval None
+  */
+static void SAI_DMATxCplt(DMA_HandleTypeDef *hdma)
+{
+  SAI_HandleTypeDef *hsai = (SAI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+  if (hdma->Init.Mode != DMA_CIRCULAR)
+  {
+    hsai->XferCount = 0U;
+
+    /* Disable SAI Tx DMA Request */
+    hsai->Instance->CR1 &= (uint32_t)(~SAI_xCR1_DMAEN);
+
+    /* Stop the interrupts error handling */
+    __HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_DMA));
+
+    hsai->State = HAL_SAI_STATE_READY;
+  }
+#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
+  hsai->TxCpltCallback(hsai);
+#else
+  HAL_SAI_TxCpltCallback(hsai);
+#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */
+}
+
+/**
+  * @brief DMA SAI transmit process half complete callback.
+  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
+  *               the configuration information for the specified DMA module.
+  * @retval None
+  */
+static void SAI_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
+{
+  SAI_HandleTypeDef *hsai = (SAI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
+  hsai->TxHalfCpltCallback(hsai);
+#else
+  HAL_SAI_TxHalfCpltCallback(hsai);
+#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */
+}
+
+/**
+  * @brief DMA SAI receive process complete callback.
+  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
+  *               the configuration information for the specified DMA module.
+  * @retval None
+  */
+static void SAI_DMARxCplt(DMA_HandleTypeDef *hdma)
+{
+  SAI_HandleTypeDef *hsai = (SAI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+  if (hdma->Init.Mode != DMA_CIRCULAR)
+  {
+    /* Disable Rx DMA Request */
+    hsai->Instance->CR1 &= (uint32_t)(~SAI_xCR1_DMAEN);
+    hsai->XferCount = 0U;
+
+    /* Stop the interrupts error handling */
+    __HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_DMA));
+
+    hsai->State = HAL_SAI_STATE_READY;
+  }
+#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
+  hsai->RxCpltCallback(hsai);
+#else
+  HAL_SAI_RxCpltCallback(hsai);
+#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */
+}
+
+/**
+  * @brief DMA SAI receive process half complete callback
+  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
+  *               the configuration information for the specified DMA module.
+  * @retval None
+  */
+static void SAI_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
+{
+  SAI_HandleTypeDef *hsai = (SAI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
+  hsai->RxHalfCpltCallback(hsai);
+#else
+  HAL_SAI_RxHalfCpltCallback(hsai);
+#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */
+}
+
+/**
+  * @brief DMA SAI communication error callback.
+  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
+  *               the configuration information for the specified DMA module.
+  * @retval None
+  */
+static void SAI_DMAError(DMA_HandleTypeDef *hdma)
+{
+  SAI_HandleTypeDef *hsai = (SAI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+  /* Set SAI error code */
+  hsai->ErrorCode |= HAL_SAI_ERROR_DMA;
+
+  if ((hsai->hdmatx->ErrorCode == HAL_DMA_ERROR_TE) || (hsai->hdmarx->ErrorCode == HAL_DMA_ERROR_TE))
+  {
+    /* Disable the SAI DMA request */
+    hsai->Instance->CR1 &= ~SAI_xCR1_DMAEN;
+
+    /* Disable SAI peripheral */
+    SAI_Disable(hsai);
+
+    /* Set the SAI state ready to be able to start again the process */
+    hsai->State = HAL_SAI_STATE_READY;
+
+    /* Initialize XferCount */
+    hsai->XferCount = 0U;
+  }
+  /* SAI error Callback */
+#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
+  hsai->ErrorCallback(hsai);
+#else
+  HAL_SAI_ErrorCallback(hsai);
+#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */
+}
+
+/**
+  * @brief  DMA SAI Abort callback.
+  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
+  *               the configuration information for the specified DMA module.
+  * @retval None
+  */
+static void SAI_DMAAbort(DMA_HandleTypeDef *hdma)
+{
+  SAI_HandleTypeDef *hsai = (SAI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+  /* Disable DMA request */
+  hsai->Instance->CR1 &= ~SAI_xCR1_DMAEN;
+
+  /* Disable all interrupts and clear all flags */
+  hsai->Instance->IMR = 0U;
+  hsai->Instance->CLRFR = 0xFFFFFFFFU;
+
+  if (hsai->ErrorCode != HAL_SAI_ERROR_WCKCFG)
+  {
+    /* Disable SAI peripheral */
+    SAI_Disable(hsai);
+
+    /* Flush the fifo */
+    SET_BIT(hsai->Instance->CR2, SAI_xCR2_FFLUSH);
+  }
+  /* Set the SAI state to ready to be able to start again the process */
+  hsai->State = HAL_SAI_STATE_READY;
+
+  /* Initialize XferCount */
+  hsai->XferCount = 0U;
+
+  /* SAI error Callback */
+#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
+  hsai->ErrorCallback(hsai);
+#else
+  HAL_SAI_ErrorCallback(hsai);
+#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */
+}
+
+/**
+  * @}
+  */
+
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx || STM32F413xx || STM32F423xx */
+#endif /* HAL_SAI_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
diff --git a/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sai_ex.c b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sai_ex.c
new file mode 100644
index 0000000..4ae059b
--- /dev/null
+++ b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sai_ex.c
@@ -0,0 +1,310 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hal_sai_ex.c
+  * @author  MCD Application Team
+  * @brief   SAI Extension HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of SAI extension peripheral:
+  *           + Extension features functions
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  @verbatim
+  ==============================================================================
+               ##### SAI peripheral extension features  #####
+  ==============================================================================
+
+  [..] Comparing to other previous devices, the SAI interface for STM32F446xx
+       devices contains the following additional features :
+
+       (+) Possibility to be clocked from PLLR
+
+                     ##### How to use this driver #####
+  ==============================================================================
+  [..] This driver provides functions to manage several sources to clock SAI
+
+  @endverbatim
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup SAIEx SAIEx
+  * @brief SAI Extension HAL module driver
+  * @{
+  */
+
+#ifdef HAL_SAI_MODULE_ENABLED
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
+    defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F413xx) || \
+    defined(STM32F423xx)
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* SAI registers Masks */
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup SAI_Private_Functions  SAI Private Functions
+  * @{
+  */
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup SAIEx_Exported_Functions SAI Extended Exported Functions
+  * @{
+  */
+
+/** @defgroup SAIEx_Exported_Functions_Group1 Extension features functions
+  *  @brief   Extension features functions
+  *
+@verbatim
+ ===============================================================================
+                       ##### Extension features Functions #####
+ ===============================================================================
+    [..]
+    This subsection provides a set of functions allowing to manage the possible
+    SAI clock sources.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Configure SAI Block synchronization mode
+  * @param  hsai pointer to a SAI_HandleTypeDef structure that contains
+  *               the configuration information for SAI module.
+  * @retval SAI Clock Input
+  */
+void SAI_BlockSynchroConfig(SAI_HandleTypeDef *hsai)
+{
+  uint32_t tmpregisterGCR;
+
+#if defined(STM32F446xx)
+  /* This setting must be done with both audio block (A & B) disabled         */
+  switch (hsai->Init.SynchroExt)
+  {
+    case SAI_SYNCEXT_DISABLE :
+      tmpregisterGCR = 0U;
+      break;
+    case SAI_SYNCEXT_OUTBLOCKA_ENABLE :
+      tmpregisterGCR = SAI_GCR_SYNCOUT_0;
+      break;
+    case SAI_SYNCEXT_OUTBLOCKB_ENABLE :
+      tmpregisterGCR = SAI_GCR_SYNCOUT_1;
+      break;
+    default:
+      tmpregisterGCR = 0U;
+      break;
+  }
+
+  if ((hsai->Init.Synchro) == SAI_SYNCHRONOUS_EXT_SAI2)
+  {
+    tmpregisterGCR |= SAI_GCR_SYNCIN_0;
+  }
+
+  if ((hsai->Instance == SAI1_Block_A) || (hsai->Instance == SAI1_Block_B))
+  {
+    SAI1->GCR = tmpregisterGCR;
+  }
+  else
+  {
+    SAI2->GCR = tmpregisterGCR;
+  }
+#endif /* STM32F446xx */
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
+    defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F413xx) || defined(STM32F423xx)
+  /* This setting must be done with both audio block (A & B) disabled         */
+  switch (hsai->Init.SynchroExt)
+  {
+    case SAI_SYNCEXT_DISABLE :
+      tmpregisterGCR = 0U;
+      break;
+    case SAI_SYNCEXT_OUTBLOCKA_ENABLE :
+      tmpregisterGCR = SAI_GCR_SYNCOUT_0;
+      break;
+    case SAI_SYNCEXT_OUTBLOCKB_ENABLE :
+      tmpregisterGCR = SAI_GCR_SYNCOUT_1;
+      break;
+    default:
+      tmpregisterGCR = 0U;
+      break;
+  }
+  SAI1->GCR = tmpregisterGCR;
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx || STM32F413xx || STM32F423xx */
+}
+/**
+* @brief  Get SAI Input Clock based on SAI source clock selection
+* @param  hsai pointer to a SAI_HandleTypeDef structure that contains
+*               the configuration information for SAI module.
+* @retval SAI Clock Input
+*/
+uint32_t SAI_GetInputClock(SAI_HandleTypeDef *hsai)
+{
+  /* This variable used to store the SAI_CK_x (value in Hz) */
+  uint32_t saiclocksource = 0U;
+
+#if defined(STM32F446xx)
+  if ((hsai->Instance == SAI1_Block_A) || (hsai->Instance == SAI1_Block_B))
+  {
+    saiclocksource = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SAI1);
+  }
+  else /* SAI2_Block_A || SAI2_Block_B*/
+  {
+    saiclocksource = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SAI2);
+  }
+#endif /* STM32F446xx */
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
+  defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F413xx) || defined(STM32F423xx)
+  uint32_t vcoinput = 0U, tmpreg = 0U;
+
+  /* Check the SAI Block parameters */
+  assert_param(IS_SAI_CLK_SOURCE(hsai->Init.ClockSource));
+
+  /* SAI Block clock source selection */
+  if (hsai->Instance == SAI1_Block_A)
+  {
+    __HAL_RCC_SAI_BLOCKACLKSOURCE_CONFIG(hsai->Init.ClockSource);
+  }
+  else
+  {
+    __HAL_RCC_SAI_BLOCKBCLKSOURCE_CONFIG((uint32_t)(hsai->Init.ClockSource << 2U));
+  }
+
+  /* VCO Input Clock value calculation */
+  if ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI)
+  {
+    /* In Case the PLL Source is HSI (Internal Clock) */
+    vcoinput = (HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
+  }
+  else
+  {
+    /* In Case the PLL Source is HSE (External Clock) */
+    vcoinput = ((HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)));
+  }
+#if defined(STM32F413xx) || defined(STM32F423xx)
+  /* SAI_CLK_x : SAI Block Clock configuration for different clock sources selected */
+  if (hsai->Init.ClockSource == SAI_CLKSOURCE_PLLR)
+  {
+    /* Configure the PLLI2S division factor */
+    /* PLL_VCO Input  = PLL_SOURCE/PLLM */
+    /* PLL_VCO Output = PLL_VCO Input * PLLN */
+    /* SAI_CLK(first level) = PLL_VCO Output/PLLR */
+    tmpreg = (RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> 28U;
+    saiclocksource = (vcoinput * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6U)) / (tmpreg);
+
+    /* SAI_CLK_x = SAI_CLK(first level)/PLLDIVR */
+    tmpreg = (((RCC->DCKCFGR & RCC_DCKCFGR_PLLDIVR) >> 8U) + 1U);
+
+    saiclocksource = saiclocksource / (tmpreg);
+
+  }
+  else if (hsai->Init.ClockSource == SAI_CLKSOURCE_PLLI2S)
+  {
+    /* Configure the PLLI2S division factor */
+    /* PLLI2S_VCO Input  = PLL_SOURCE/PLLM */
+    /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
+    /* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SR */
+    tmpreg = (RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> 28U;
+    saiclocksource = (vcoinput * ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6U)) / (tmpreg);
+
+    /* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVR */
+    tmpreg = ((RCC->DCKCFGR & RCC_DCKCFGR_PLLI2SDIVR) + 1U);
+    saiclocksource = saiclocksource / (tmpreg);
+  }
+  else if (hsai->Init.ClockSource == SAI_CLKSOURCE_HS)
+  {
+    if ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE)
+    {
+      /* Get the I2S source clock value */
+      saiclocksource = (uint32_t)(HSE_VALUE);
+    }
+    else
+    {
+      /* Get the I2S source clock value */
+      saiclocksource = (uint32_t)(HSI_VALUE);
+    }
+  }
+  else /* sConfig->ClockSource == SAI_CLKSource_Ext */
+  {
+    saiclocksource = EXTERNAL_CLOCK_VALUE;
+  }
+#else
+  /* SAI_CLK_x : SAI Block Clock configuration for different clock sources selected */
+  if (hsai->Init.ClockSource == SAI_CLKSOURCE_PLLSAI)
+  {
+    /* Configure the PLLI2S division factor */
+    /* PLLSAI_VCO Input  = PLL_SOURCE/PLLM */
+    /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
+    /* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */
+    tmpreg = (RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> 24U;
+    saiclocksource = (vcoinput * ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> 6U)) / (tmpreg);
+
+    /* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */
+    tmpreg = (((RCC->DCKCFGR & RCC_DCKCFGR_PLLSAIDIVQ) >> 8U) + 1U);
+    saiclocksource = saiclocksource / (tmpreg);
+
+  }
+  else if (hsai->Init.ClockSource == SAI_CLKSOURCE_PLLI2S)
+  {
+    /* Configure the PLLI2S division factor */
+    /* PLLI2S_VCO Input  = PLL_SOURCE/PLLM */
+    /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
+    /* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */
+    tmpreg = (RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> 24U;
+    saiclocksource = (vcoinput * ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6U)) / (tmpreg);
+
+    /* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */
+    tmpreg = ((RCC->DCKCFGR & RCC_DCKCFGR_PLLI2SDIVQ) + 1U);
+    saiclocksource = saiclocksource / (tmpreg);
+  }
+  else /* sConfig->ClockSource == SAI_CLKSource_Ext */
+  {
+    /* Enable the External Clock selection */
+    __HAL_RCC_I2S_CONFIG(RCC_I2SCLKSOURCE_EXT);
+
+    saiclocksource = EXTERNAL_CLOCK_VALUE;
+  }
+#endif /* STM32F413xx || STM32F423xx */
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx || STM32F413xx || STM32F423xx */
+  /* the return result is the value of SAI clock */
+  return saiclocksource;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx  || STM32F446xx || STM32F469xx || STM32F479xx || STM32F413xx || STM32F423xx */
+#endif /* HAL_SAI_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
diff --git a/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.c b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.c
new file mode 100644
index 0000000..afd90c0
--- /dev/null
+++ b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.c
@@ -0,0 +1,3277 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hal_sd.c
+  * @author  MCD Application Team
+  * @brief   SD card HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the Secure Digital (SD) peripheral:
+  *           + Initialization and de-initialization functions
+  *           + IO operation functions
+  *           + Peripheral Control functions
+  *           + Peripheral State functions
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2016 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  @verbatim
+  ==============================================================================
+                        ##### How to use this driver #####
+  ==============================================================================
+  [..]
+    This driver implements a high level communication layer for read and write from/to
+    this memory. The needed STM32 hardware resources (SDIO and GPIO) are performed by
+    the user in HAL_SD_MspInit() function (MSP layer).
+    Basically, the MSP layer configuration should be the same as we provide in the
+    examples.
+    You can easily tailor this configuration according to hardware resources.
+
+  [..]
+    This driver is a generic layered driver for SDIO memories which uses the HAL
+    SDIO driver functions to interface with SD and uSD cards devices.
+    It is used as follows:
+
+    (#)Initialize the SDIO low level resources by implementing the HAL_SD_MspInit() API:
+        (##) Enable the SDIO interface clock using __HAL_RCC_SDIO_CLK_ENABLE();
+        (##) SDIO pins configuration for SD card
+            (+++) Enable the clock for the SDIO GPIOs using the functions __HAL_RCC_GPIOx_CLK_ENABLE();
+            (+++) Configure these SDIO pins as alternate function pull-up using HAL_GPIO_Init()
+                  and according to your pin assignment;
+        (##) DMA configuration if you need to use DMA process (HAL_SD_ReadBlocks_DMA()
+             and HAL_SD_WriteBlocks_DMA() APIs).
+            (+++) Enable the DMAx interface clock using __HAL_RCC_DMAx_CLK_ENABLE();
+            (+++) Configure the DMA using the function HAL_DMA_Init() with predeclared and filled.
+        (##) NVIC configuration if you need to use interrupt process when using DMA transfer.
+            (+++) Configure the SDIO and DMA interrupt priorities using functions
+                  HAL_NVIC_SetPriority(); DMA priority is superior to SDIO's priority
+            (+++) Enable the NVIC DMA and SDIO IRQs using function HAL_NVIC_EnableIRQ()
+            (+++) SDIO interrupts are managed using the macros __HAL_SD_ENABLE_IT()
+                  and __HAL_SD_DISABLE_IT() inside the communication process.
+            (+++) SDIO interrupts pending bits are managed using the macros __HAL_SD_GET_IT()
+                  and __HAL_SD_CLEAR_IT()
+        (##) NVIC configuration if you need to use interrupt process (HAL_SD_ReadBlocks_IT()
+             and HAL_SD_WriteBlocks_IT() APIs).
+            (+++) Configure the SDIO interrupt priorities using function HAL_NVIC_SetPriority();
+            (+++) Enable the NVIC SDIO IRQs using function HAL_NVIC_EnableIRQ()
+            (+++) SDIO interrupts are managed using the macros __HAL_SD_ENABLE_IT()
+                  and __HAL_SD_DISABLE_IT() inside the communication process.
+            (+++) SDIO interrupts pending bits are managed using the macros __HAL_SD_GET_IT()
+                  and __HAL_SD_CLEAR_IT()
+    (#) At this stage, you can perform SD read/write/erase operations after SD card initialization
+
+
+  *** SD Card Initialization and configuration ***
+  ================================================
+  [..]
+    To initialize the SD Card, use the HAL_SD_Init() function. It Initializes
+    SDIO Peripheral(STM32 side) and the SD Card, and put it into StandBy State (Ready for data transfer).
+    This function provide the following operations:
+
+    (#) Apply the SD Card initialization process at 400KHz and check the SD Card
+        type (Standard Capacity or High Capacity). You can change or adapt this
+        frequency by adjusting the "ClockDiv" field.
+        The SD Card frequency (SDIO_CK) is computed as follows:
+
+           SDIO_CK = SDIOCLK / (ClockDiv + 2)
+
+        In initialization mode and according to the SD Card standard,
+        make sure that the SDIO_CK frequency doesn't exceed 400KHz.
+
+        This phase of initialization is done through SDIO_Init() and
+        SDIO_PowerState_ON() SDIO low level APIs.
+
+    (#) Initialize the SD card. The API used is HAL_SD_InitCard().
+        This phase allows the card initialization and identification
+        and check the SD Card type (Standard Capacity or High Capacity)
+        The initialization flow is compatible with SD standard.
+
+        This API (HAL_SD_InitCard()) could be used also to reinitialize the card in case
+        of plug-off plug-in.
+
+    (#) Configure the SD Card Data transfer frequency. You can change or adapt this
+        frequency by adjusting the "ClockDiv" field.
+        In transfer mode and according to the SD Card standard, make sure that the
+        SDIO_CK frequency doesn't exceed 25MHz and 50MHz in High-speed mode switch.
+        To be able to use a frequency higher than 24MHz, you should use the SDIO
+        peripheral in bypass mode. Refer to the corresponding reference manual
+        for more details.
+
+    (#) Select the corresponding SD Card according to the address read with the step 2.
+
+    (#) Configure the SD Card in wide bus mode: 4-bits data.
+
+  *** SD Card Read operation ***
+  ==============================
+  [..]
+    (+) You can read from SD card in polling mode by using function HAL_SD_ReadBlocks().
+        This function support only 512-bytes block length (the block size should be
+        chosen as 512 bytes).
+        You can choose either one block read operation or multiple block read operation
+        by adjusting the "NumberOfBlocks" parameter.
+        After this, you have to ensure that the transfer is done correctly. The check is done
+        through HAL_SD_GetCardState() function for SD card state.
+
+    (+) You can read from SD card in DMA mode by using function HAL_SD_ReadBlocks_DMA().
+        This function support only 512-bytes block length (the block size should be
+        chosen as 512 bytes).
+        You can choose either one block read operation or multiple block read operation
+        by adjusting the "NumberOfBlocks" parameter.
+        After this, you have to ensure that the transfer is done correctly. The check is done
+        through HAL_SD_GetCardState() function for SD card state.
+        You could also check the DMA transfer process through the SD Rx interrupt event.
+
+    (+) You can read from SD card in Interrupt mode by using function HAL_SD_ReadBlocks_IT().
+        This function support only 512-bytes block length (the block size should be
+        chosen as 512 bytes).
+        You can choose either one block read operation or multiple block read operation
+        by adjusting the "NumberOfBlocks" parameter.
+        After this, you have to ensure that the transfer is done correctly. The check is done
+        through HAL_SD_GetCardState() function for SD card state.
+        You could also check the IT transfer process through the SD Rx interrupt event.
+
+  *** SD Card Write operation ***
+  ===============================
+  [..]
+    (+) You can write to SD card in polling mode by using function HAL_SD_WriteBlocks().
+        This function support only 512-bytes block length (the block size should be
+        chosen as 512 bytes).
+        You can choose either one block read operation or multiple block read operation
+        by adjusting the "NumberOfBlocks" parameter.
+        After this, you have to ensure that the transfer is done correctly. The check is done
+        through HAL_SD_GetCardState() function for SD card state.
+
+    (+) You can write to SD card in DMA mode by using function HAL_SD_WriteBlocks_DMA().
+        This function support only 512-bytes block length (the block size should be
+        chosen as 512 bytes).
+        You can choose either one block read operation or multiple block read operation
+        by adjusting the "NumberOfBlocks" parameter.
+        After this, you have to ensure that the transfer is done correctly. The check is done
+        through HAL_SD_GetCardState() function for SD card state.
+        You could also check the DMA transfer process through the SD Tx interrupt event.
+
+    (+) You can write to SD card in Interrupt mode by using function HAL_SD_WriteBlocks_IT().
+        This function support only 512-bytes block length (the block size should be
+        chosen as 512 bytes).
+        You can choose either one block read operation or multiple block read operation
+        by adjusting the "NumberOfBlocks" parameter.
+        After this, you have to ensure that the transfer is done correctly. The check is done
+        through HAL_SD_GetCardState() function for SD card state.
+        You could also check the IT transfer process through the SD Tx interrupt event.
+
+  *** SD card status ***
+  ======================
+  [..]
+    (+) The SD Status contains status bits that are related to the SD Memory
+        Card proprietary features. To get SD card status use the HAL_SD_GetCardStatus().
+
+  *** SD card information ***
+  ===========================
+  [..]
+    (+) To get SD card information, you can use the function HAL_SD_GetCardInfo().
+        It returns useful information about the SD card such as block size, card type,
+        block number ...
+
+  *** SD card CSD register ***
+  ============================
+    (+) The HAL_SD_GetCardCSD() API allows to get the parameters of the CSD register.
+        Some of the CSD parameters are useful for card initialization and identification.
+
+  *** SD card CID register ***
+  ============================
+    (+) The HAL_SD_GetCardCID() API allows to get the parameters of the CID register.
+        Some of the CSD parameters are useful for card initialization and identification.
+
+  *** SD HAL driver macros list ***
+  ==================================
+  [..]
+    Below the list of most used macros in SD HAL driver.
+
+    (+) __HAL_SD_ENABLE : Enable the SD device
+    (+) __HAL_SD_DISABLE : Disable the SD device
+    (+) __HAL_SD_DMA_ENABLE: Enable the SDIO DMA transfer
+    (+) __HAL_SD_DMA_DISABLE: Disable the SDIO DMA transfer
+    (+) __HAL_SD_ENABLE_IT: Enable the SD device interrupt
+    (+) __HAL_SD_DISABLE_IT: Disable the SD device interrupt
+    (+) __HAL_SD_GET_FLAG:Check whether the specified SD flag is set or not
+    (+) __HAL_SD_CLEAR_FLAG: Clear the SD's pending flags
+
+    (@) You can refer to the SD HAL driver header file for more useful macros
+
+  *** Callback registration ***
+  =============================================
+  [..]
+    The compilation define USE_HAL_SD_REGISTER_CALLBACKS when set to 1
+    allows the user to configure dynamically the driver callbacks.
+
+    Use Functions HAL_SD_RegisterCallback() to register a user callback,
+    it allows to register following callbacks:
+      (+) TxCpltCallback : callback when a transmission transfer is completed.
+      (+) RxCpltCallback : callback when a reception transfer is completed.
+      (+) ErrorCallback : callback when error occurs.
+      (+) AbortCpltCallback : callback when abort is completed.
+      (+) MspInitCallback    : SD MspInit.
+      (+) MspDeInitCallback  : SD MspDeInit.
+    This function takes as parameters the HAL peripheral handle, the Callback ID
+    and a pointer to the user callback function.
+
+    Use function HAL_SD_UnRegisterCallback() to reset a callback to the default
+    weak (surcharged) function. It allows to reset following callbacks:
+      (+) TxCpltCallback : callback when a transmission transfer is completed.
+      (+) RxCpltCallback : callback when a reception transfer is completed.
+      (+) ErrorCallback : callback when error occurs.
+      (+) AbortCpltCallback : callback when abort is completed.
+      (+) MspInitCallback    : SD MspInit.
+      (+) MspDeInitCallback  : SD MspDeInit.
+    This function) takes as parameters the HAL peripheral handle and the Callback ID.
+
+    By default, after the HAL_SD_Init and if the state is HAL_SD_STATE_RESET
+    all callbacks are reset to the corresponding legacy weak (surcharged) functions.
+    Exception done for MspInit and MspDeInit callbacks that are respectively
+    reset to the legacy weak (surcharged) functions in the HAL_SD_Init
+    and  HAL_SD_DeInit only when these callbacks are null (not registered beforehand).
+    If not, MspInit or MspDeInit are not null, the HAL_SD_Init and HAL_SD_DeInit
+    keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
+
+    Callbacks can be registered/unregistered in READY state only.
+    Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
+    in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
+    during the Init/DeInit.
+    In that case first register the MspInit/MspDeInit user callbacks
+    using HAL_SD_RegisterCallback before calling HAL_SD_DeInit
+    or HAL_SD_Init function.
+
+    When The compilation define USE_HAL_SD_REGISTER_CALLBACKS is set to 0 or
+    not defined, the callback registering feature is not available
+    and weak (surcharged) callbacks are used.
+
+  @endverbatim
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal.h"
+
+#if defined(SDIO)
+
+/** @addtogroup STM32F4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup SD
+  * @{
+  */
+
+#ifdef HAL_SD_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @addtogroup SD_Private_Defines
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup SD_Private_Functions SD Private Functions
+  * @{
+  */
+static uint32_t SD_InitCard(SD_HandleTypeDef *hsd);
+static uint32_t SD_PowerON(SD_HandleTypeDef *hsd);
+static uint32_t SD_SendSDStatus(SD_HandleTypeDef *hsd, uint32_t *pSDstatus);
+static uint32_t SD_SendStatus(SD_HandleTypeDef *hsd, uint32_t *pCardStatus);
+static uint32_t SD_WideBus_Enable(SD_HandleTypeDef *hsd);
+static uint32_t SD_WideBus_Disable(SD_HandleTypeDef *hsd);
+static uint32_t SD_FindSCR(SD_HandleTypeDef *hsd, uint32_t *pSCR);
+static void SD_PowerOFF(SD_HandleTypeDef *hsd);
+static void SD_Write_IT(SD_HandleTypeDef *hsd);
+static void SD_Read_IT(SD_HandleTypeDef *hsd);
+static void SD_DMATransmitCplt(DMA_HandleTypeDef *hdma);
+static void SD_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
+static void SD_DMAError(DMA_HandleTypeDef *hdma);
+static void SD_DMATxAbort(DMA_HandleTypeDef *hdma);
+static void SD_DMARxAbort(DMA_HandleTypeDef *hdma);
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup SD_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup SD_Exported_Functions_Group1
+ *  @brief   Initialization and de-initialization functions
+ *
+@verbatim
+  ==============================================================================
+          ##### Initialization and de-initialization functions #####
+  ==============================================================================
+  [..]
+    This section provides functions allowing to initialize/de-initialize the SD
+    card device to be ready for use.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initializes the SD according to the specified parameters in the
+            SD_HandleTypeDef and create the associated handle.
+  * @param  hsd: Pointer to the SD handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SD_Init(SD_HandleTypeDef *hsd)
+{
+  /* Check the SD handle allocation */
+  if(hsd == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_SDIO_ALL_INSTANCE(hsd->Instance));
+  assert_param(IS_SDIO_CLOCK_EDGE(hsd->Init.ClockEdge));
+  assert_param(IS_SDIO_CLOCK_BYPASS(hsd->Init.ClockBypass));
+  assert_param(IS_SDIO_CLOCK_POWER_SAVE(hsd->Init.ClockPowerSave));
+  assert_param(IS_SDIO_BUS_WIDE(hsd->Init.BusWide));
+  assert_param(IS_SDIO_HARDWARE_FLOW_CONTROL(hsd->Init.HardwareFlowControl));
+  assert_param(IS_SDIO_CLKDIV(hsd->Init.ClockDiv));
+
+  if(hsd->State == HAL_SD_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    hsd->Lock = HAL_UNLOCKED;
+#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
+    /* Reset Callback pointers in HAL_SD_STATE_RESET only */
+    hsd->TxCpltCallback    = HAL_SD_TxCpltCallback;
+    hsd->RxCpltCallback    = HAL_SD_RxCpltCallback;
+    hsd->ErrorCallback     = HAL_SD_ErrorCallback;
+    hsd->AbortCpltCallback = HAL_SD_AbortCallback;
+
+    if(hsd->MspInitCallback == NULL)
+    {
+      hsd->MspInitCallback = HAL_SD_MspInit;
+    }
+
+    /* Init the low level hardware */
+    hsd->MspInitCallback(hsd);
+#else
+    /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
+    HAL_SD_MspInit(hsd);
+#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
+  }
+
+  hsd->State = HAL_SD_STATE_BUSY;
+
+  /* Initialize the Card parameters */
+  if (HAL_SD_InitCard(hsd) != HAL_OK)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Initialize the error code */
+  hsd->ErrorCode = HAL_SD_ERROR_NONE;
+
+  /* Initialize the SD operation */
+  hsd->Context = SD_CONTEXT_NONE;
+
+  /* Initialize the SD state */
+  hsd->State = HAL_SD_STATE_READY;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the SD Card.
+  * @param  hsd: Pointer to SD handle
+  * @note   This function initializes the SD card. It could be used when a card
+            re-initialization is needed.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SD_InitCard(SD_HandleTypeDef *hsd)
+{
+  uint32_t errorstate;
+  HAL_StatusTypeDef status;
+  SD_InitTypeDef Init;
+  
+  /* Default SDIO peripheral configuration for SD card initialization */
+  Init.ClockEdge           = SDIO_CLOCK_EDGE_RISING;
+  Init.ClockBypass         = SDIO_CLOCK_BYPASS_DISABLE;
+  Init.ClockPowerSave      = SDIO_CLOCK_POWER_SAVE_DISABLE;
+  Init.BusWide             = SDIO_BUS_WIDE_1B;
+  Init.HardwareFlowControl = SDIO_HARDWARE_FLOW_CONTROL_DISABLE;
+  Init.ClockDiv            = SDIO_INIT_CLK_DIV;
+
+  /* Initialize SDIO peripheral interface with default configuration */
+  status = SDIO_Init(hsd->Instance, Init);
+  if(status != HAL_OK)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Disable SDIO Clock */
+  __HAL_SD_DISABLE(hsd);
+
+  /* Set Power State to ON */
+  (void)SDIO_PowerState_ON(hsd->Instance);
+
+  /* Enable SDIO Clock */
+  __HAL_SD_ENABLE(hsd);
+
+  /* Required power up waiting time before starting the SD initialization  sequence */
+  HAL_Delay(2);
+
+  /* Identify card operating voltage */
+  errorstate = SD_PowerON(hsd);
+  if(errorstate != HAL_SD_ERROR_NONE)
+  {
+    hsd->State = HAL_SD_STATE_READY;
+    hsd->ErrorCode |= errorstate;
+    return HAL_ERROR;
+  }
+
+  /* Card initialization */
+  errorstate = SD_InitCard(hsd);
+  if(errorstate != HAL_SD_ERROR_NONE)
+  {
+    hsd->State = HAL_SD_STATE_READY;
+    hsd->ErrorCode |= errorstate;
+    return HAL_ERROR;
+  }
+
+  /* Set Block Size for Card */
+  errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE);
+  if(errorstate != HAL_SD_ERROR_NONE)
+  {
+    /* Clear all the static flags */
+    __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
+    hsd->ErrorCode |= errorstate;
+    hsd->State = HAL_SD_STATE_READY;
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  De-Initializes the SD card.
+  * @param  hsd: Pointer to SD handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SD_DeInit(SD_HandleTypeDef *hsd)
+{
+  /* Check the SD handle allocation */
+  if(hsd == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_SDIO_ALL_INSTANCE(hsd->Instance));
+
+  hsd->State = HAL_SD_STATE_BUSY;
+
+  /* Set SD power state to off */
+  SD_PowerOFF(hsd);
+
+#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
+  if(hsd->MspDeInitCallback == NULL)
+  {
+    hsd->MspDeInitCallback = HAL_SD_MspDeInit;
+  }
+
+  /* DeInit the low level hardware */
+  hsd->MspDeInitCallback(hsd);
+#else
+  /* De-Initialize the MSP layer */
+  HAL_SD_MspDeInit(hsd);
+#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
+
+  hsd->ErrorCode = HAL_SD_ERROR_NONE;
+  hsd->State = HAL_SD_STATE_RESET;
+
+  return HAL_OK;
+}
+
+
+/**
+  * @brief  Initializes the SD MSP.
+  * @param  hsd: Pointer to SD handle
+  * @retval None
+  */
+__weak void HAL_SD_MspInit(SD_HandleTypeDef *hsd)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hsd);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_SD_MspInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  De-Initialize SD MSP.
+  * @param  hsd: Pointer to SD handle
+  * @retval None
+  */
+__weak void HAL_SD_MspDeInit(SD_HandleTypeDef *hsd)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hsd);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_SD_MspDeInit could be implemented in the user file
+   */
+}
+
+/**
+  * @}
+  */
+
+/** @addtogroup SD_Exported_Functions_Group2
+ *  @brief   Data transfer functions
+ *
+@verbatim
+  ==============================================================================
+                        ##### IO operation functions #####
+  ==============================================================================
+  [..]
+    This subsection provides a set of functions allowing to manage the data
+    transfer from/to SD card.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Reads block(s) from a specified address in a card. The Data transfer
+  *         is managed by polling mode.
+  * @note   This API should be followed by a check on the card state through
+  *         HAL_SD_GetCardState().
+  * @param  hsd: Pointer to SD handle
+  * @param  pData: pointer to the buffer that will contain the received data
+  * @param  BlockAdd: Block Address from where data is to be read
+  * @param  NumberOfBlocks: Number of SD blocks to read
+  * @param  Timeout: Specify timeout value
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout)
+{
+  SDIO_DataInitTypeDef config;
+  uint32_t errorstate;
+  uint32_t tickstart = HAL_GetTick();
+  uint32_t count, data, dataremaining;
+  uint32_t add = BlockAdd;
+  uint8_t *tempbuff = pData;
+
+  if(NULL == pData)
+  {
+    hsd->ErrorCode |= HAL_SD_ERROR_PARAM;
+    return HAL_ERROR;
+  }
+
+  if(hsd->State == HAL_SD_STATE_READY)
+  {
+    hsd->ErrorCode = HAL_SD_ERROR_NONE;
+
+    if((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr))
+    {
+      hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE;
+      return HAL_ERROR;
+    }
+
+    hsd->State = HAL_SD_STATE_BUSY;
+
+    /* Initialize data control register */
+    hsd->Instance->DCTRL = 0U;
+
+    if(hsd->SdCard.CardType != CARD_SDHC_SDXC)
+    {
+      add *= 512U;
+    }
+
+    /* Configure the SD DPSM (Data Path State Machine) */
+    config.DataTimeOut   = SDMMC_DATATIMEOUT;
+    config.DataLength    = NumberOfBlocks * BLOCKSIZE;
+    config.DataBlockSize = SDIO_DATABLOCK_SIZE_512B;
+    config.TransferDir   = SDIO_TRANSFER_DIR_TO_SDIO;
+    config.TransferMode  = SDIO_TRANSFER_MODE_BLOCK;
+    config.DPSM          = SDIO_DPSM_ENABLE;
+    (void)SDIO_ConfigData(hsd->Instance, &config);
+
+    /* Read block(s) in polling mode */
+    if(NumberOfBlocks > 1U)
+    {
+      hsd->Context = SD_CONTEXT_READ_MULTIPLE_BLOCK;
+
+      /* Read Multi Block command */
+      errorstate = SDMMC_CmdReadMultiBlock(hsd->Instance, add);
+    }
+    else
+    {
+      hsd->Context = SD_CONTEXT_READ_SINGLE_BLOCK;
+
+      /* Read Single Block command */
+      errorstate = SDMMC_CmdReadSingleBlock(hsd->Instance, add);
+    }
+    if(errorstate != HAL_SD_ERROR_NONE)
+    {
+      /* Clear all the static flags */
+      __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
+      hsd->ErrorCode |= errorstate;
+      hsd->State = HAL_SD_STATE_READY;
+      hsd->Context = SD_CONTEXT_NONE;
+      return HAL_ERROR;
+    }
+
+    /* Poll on SDIO flags */
+    dataremaining = config.DataLength;
+#if defined(SDIO_STA_STBITERR)
+    while(!__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_RXOVERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DATAEND | SDIO_FLAG_STBITERR))
+#else /* SDIO_STA_STBITERR not defined */
+    while(!__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_RXOVERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DATAEND))
+#endif /* SDIO_STA_STBITERR */
+    {
+      if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_RXFIFOHF) && (dataremaining > 0U))
+      {
+        /* Read data from SDIO Rx FIFO */
+        for(count = 0U; count < 8U; count++)
+        {
+          data = SDIO_ReadFIFO(hsd->Instance);
+          *tempbuff = (uint8_t)(data & 0xFFU);
+          tempbuff++;
+          dataremaining--;
+          *tempbuff = (uint8_t)((data >> 8U) & 0xFFU);
+          tempbuff++;
+          dataremaining--;
+          *tempbuff = (uint8_t)((data >> 16U) & 0xFFU);
+          tempbuff++;
+          dataremaining--;
+          *tempbuff = (uint8_t)((data >> 24U) & 0xFFU);
+          tempbuff++;
+          dataremaining--;
+        }
+      }
+
+      if(((HAL_GetTick()-tickstart) >=  Timeout) || (Timeout == 0U))
+      {
+        /* Clear all the static flags */
+        __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
+        hsd->ErrorCode |= HAL_SD_ERROR_TIMEOUT;
+        hsd->State= HAL_SD_STATE_READY;
+        hsd->Context = SD_CONTEXT_NONE;
+        return HAL_TIMEOUT;
+      }
+    }
+    
+    /* Send stop transmission command in case of multiblock read */
+    if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_DATAEND) && (NumberOfBlocks > 1U))
+    {
+      if(hsd->SdCard.CardType != CARD_SECURED)
+      {
+        /* Send stop transmission command */
+        errorstate = SDMMC_CmdStopTransfer(hsd->Instance);
+        if(errorstate != HAL_SD_ERROR_NONE)
+        {
+          /* Clear all the static flags */
+          __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
+          hsd->ErrorCode |= errorstate;
+          hsd->State = HAL_SD_STATE_READY;
+          hsd->Context = SD_CONTEXT_NONE;
+          return HAL_ERROR;
+        }
+      }
+    }
+
+    /* Get error state */
+    if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_DTIMEOUT))
+    {
+      /* Clear all the static flags */
+      __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
+      hsd->ErrorCode |= HAL_SD_ERROR_DATA_TIMEOUT;
+      hsd->State = HAL_SD_STATE_READY;
+      hsd->Context = SD_CONTEXT_NONE;
+      return HAL_ERROR;
+    }
+    else if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_DCRCFAIL))
+    {
+      /* Clear all the static flags */
+      __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
+      hsd->ErrorCode |= HAL_SD_ERROR_DATA_CRC_FAIL;
+      hsd->State = HAL_SD_STATE_READY;
+      hsd->Context = SD_CONTEXT_NONE;
+      return HAL_ERROR;
+    }
+    else if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_RXOVERR))
+    {
+      /* Clear all the static flags */
+      __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
+      hsd->ErrorCode |= HAL_SD_ERROR_RX_OVERRUN;
+      hsd->State = HAL_SD_STATE_READY;
+      hsd->Context = SD_CONTEXT_NONE;
+      return HAL_ERROR;
+    }
+    else
+    {
+      /* Nothing to do */
+    }
+
+    /* Empty FIFO if there is still any data */
+    while ((__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_RXDAVL)) && (dataremaining > 0U))
+    {
+      data = SDIO_ReadFIFO(hsd->Instance);
+      *tempbuff = (uint8_t)(data & 0xFFU);
+      tempbuff++;
+      dataremaining--;
+      *tempbuff = (uint8_t)((data >> 8U) & 0xFFU);
+      tempbuff++;
+      dataremaining--;
+      *tempbuff = (uint8_t)((data >> 16U) & 0xFFU);
+      tempbuff++;
+      dataremaining--;
+      *tempbuff = (uint8_t)((data >> 24U) & 0xFFU);
+      tempbuff++;
+      dataremaining--;
+
+      if(((HAL_GetTick()-tickstart) >=  Timeout) || (Timeout == 0U))
+      {
+        /* Clear all the static flags */
+        __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
+        hsd->ErrorCode |= HAL_SD_ERROR_TIMEOUT;
+        hsd->State= HAL_SD_STATE_READY;
+        hsd->Context = SD_CONTEXT_NONE;
+        return HAL_ERROR;
+      }
+    }
+
+    /* Clear all the static flags */
+    __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_DATA_FLAGS);
+
+    hsd->State = HAL_SD_STATE_READY;
+
+    return HAL_OK;
+  }
+  else
+  {
+    hsd->ErrorCode |= HAL_SD_ERROR_BUSY;
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Allows to write block(s) to a specified address in a card. The Data
+  *         transfer is managed by polling mode.
+  * @note   This API should be followed by a check on the card state through
+  *         HAL_SD_GetCardState().
+  * @param  hsd: Pointer to SD handle
+  * @param  pData: pointer to the buffer that will contain the data to transmit
+  * @param  BlockAdd: Block Address where data will be written
+  * @param  NumberOfBlocks: Number of SD blocks to write
+  * @param  Timeout: Specify timeout value
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout)
+{
+  SDIO_DataInitTypeDef config;
+  uint32_t errorstate;
+  uint32_t tickstart = HAL_GetTick();
+  uint32_t count, data, dataremaining;
+  uint32_t add = BlockAdd;
+  uint8_t *tempbuff = pData;
+
+  if(NULL == pData)
+  {
+    hsd->ErrorCode |= HAL_SD_ERROR_PARAM;
+    return HAL_ERROR;
+  }
+
+  if(hsd->State == HAL_SD_STATE_READY)
+  {
+    hsd->ErrorCode = HAL_SD_ERROR_NONE;
+
+    if((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr))
+    {
+      hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE;
+      return HAL_ERROR;
+    }
+
+    hsd->State = HAL_SD_STATE_BUSY;
+
+    /* Initialize data control register */
+    hsd->Instance->DCTRL = 0U;
+
+    if(hsd->SdCard.CardType != CARD_SDHC_SDXC)
+    {
+      add *= 512U;
+    }
+
+    /* Configure the SD DPSM (Data Path State Machine) */
+    config.DataTimeOut   = SDMMC_DATATIMEOUT;
+    config.DataLength    = NumberOfBlocks * BLOCKSIZE;
+    config.DataBlockSize = SDIO_DATABLOCK_SIZE_512B;
+    config.TransferDir   = SDIO_TRANSFER_DIR_TO_CARD;
+    config.TransferMode  = SDIO_TRANSFER_MODE_BLOCK;
+    config.DPSM          = SDIO_DPSM_ENABLE;
+    (void)SDIO_ConfigData(hsd->Instance, &config);
+
+    /* Write Blocks in Polling mode */
+    if(NumberOfBlocks > 1U)
+    {
+      hsd->Context = SD_CONTEXT_WRITE_MULTIPLE_BLOCK;
+
+      /* Write Multi Block command */
+      errorstate = SDMMC_CmdWriteMultiBlock(hsd->Instance, add);
+    }
+    else
+    {
+      hsd->Context = SD_CONTEXT_WRITE_SINGLE_BLOCK;
+
+      /* Write Single Block command */
+      errorstate = SDMMC_CmdWriteSingleBlock(hsd->Instance, add);
+    }
+    if(errorstate != HAL_SD_ERROR_NONE)
+    {
+      /* Clear all the static flags */
+      __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
+      hsd->ErrorCode |= errorstate;
+      hsd->State = HAL_SD_STATE_READY;
+      hsd->Context = SD_CONTEXT_NONE;
+      return HAL_ERROR;
+    }
+
+    /* Write block(s) in polling mode */
+    dataremaining = config.DataLength;
+#if defined(SDIO_STA_STBITERR)
+    while(!__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_TXUNDERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DATAEND | SDIO_FLAG_STBITERR))
+#else /* SDIO_STA_STBITERR not defined */
+    while(!__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_TXUNDERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DATAEND))
+#endif /* SDIO_STA_STBITERR */
+    {
+      if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_TXFIFOHE) && (dataremaining > 0U))
+      {
+        /* Write data to SDIO Tx FIFO */
+        for(count = 0U; count < 8U; count++)
+        {
+          data = (uint32_t)(*tempbuff);
+          tempbuff++;
+          dataremaining--;
+          data |= ((uint32_t)(*tempbuff) << 8U);
+          tempbuff++;
+          dataremaining--;
+          data |= ((uint32_t)(*tempbuff) << 16U);
+          tempbuff++;
+          dataremaining--;
+          data |= ((uint32_t)(*tempbuff) << 24U);
+          tempbuff++;
+          dataremaining--;
+          (void)SDIO_WriteFIFO(hsd->Instance, &data);
+        }
+      }
+
+      if(((HAL_GetTick()-tickstart) >=  Timeout) || (Timeout == 0U))
+      {
+        /* Clear all the static flags */
+        __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
+        hsd->ErrorCode |= errorstate;
+        hsd->State = HAL_SD_STATE_READY;
+        hsd->Context = SD_CONTEXT_NONE;
+        return HAL_TIMEOUT;
+      }
+    }
+
+    /* Send stop transmission command in case of multiblock write */
+    if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_DATAEND) && (NumberOfBlocks > 1U))
+    {
+      if(hsd->SdCard.CardType != CARD_SECURED)
+      {
+        /* Send stop transmission command */
+        errorstate = SDMMC_CmdStopTransfer(hsd->Instance);
+        if(errorstate != HAL_SD_ERROR_NONE)
+        {
+          /* Clear all the static flags */
+          __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
+          hsd->ErrorCode |= errorstate;
+          hsd->State = HAL_SD_STATE_READY;
+          hsd->Context = SD_CONTEXT_NONE;
+          return HAL_ERROR;
+        }
+      }
+    }
+
+    /* Get error state */
+    if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_DTIMEOUT))
+    {
+      /* Clear all the static flags */
+      __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
+      hsd->ErrorCode |= HAL_SD_ERROR_DATA_TIMEOUT;
+      hsd->State = HAL_SD_STATE_READY;
+      hsd->Context = SD_CONTEXT_NONE;
+      return HAL_ERROR;
+    }
+    else if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_DCRCFAIL))
+    {
+      /* Clear all the static flags */
+      __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
+      hsd->ErrorCode |= HAL_SD_ERROR_DATA_CRC_FAIL;
+      hsd->State = HAL_SD_STATE_READY;
+      hsd->Context = SD_CONTEXT_NONE;
+      return HAL_ERROR;
+    }
+    else if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_TXUNDERR))
+    {
+      /* Clear all the static flags */
+      __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
+      hsd->ErrorCode |= HAL_SD_ERROR_TX_UNDERRUN;
+      hsd->State = HAL_SD_STATE_READY;
+      hsd->Context = SD_CONTEXT_NONE;
+      return HAL_ERROR;
+    }
+    else
+    {
+      /* Nothing to do */
+    }
+
+    /* Clear all the static flags */
+    __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_DATA_FLAGS);
+
+    hsd->State = HAL_SD_STATE_READY;
+
+    return HAL_OK;
+  }
+  else
+  {
+    hsd->ErrorCode |= HAL_SD_ERROR_BUSY;
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Reads block(s) from a specified address in a card. The Data transfer
+  *         is managed in interrupt mode.
+  * @note   This API should be followed by a check on the card state through
+  *         HAL_SD_GetCardState().
+  * @note   You could also check the IT transfer process through the SD Rx
+  *         interrupt event.
+  * @param  hsd: Pointer to SD handle
+  * @param  pData: Pointer to the buffer that will contain the received data
+  * @param  BlockAdd: Block Address from where data is to be read
+  * @param  NumberOfBlocks: Number of blocks to read.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SD_ReadBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks)
+{
+  SDIO_DataInitTypeDef config;
+  uint32_t errorstate;
+  uint32_t add = BlockAdd;
+
+  if(NULL == pData)
+  {
+    hsd->ErrorCode |= HAL_SD_ERROR_PARAM;
+    return HAL_ERROR;
+  }
+
+  if(hsd->State == HAL_SD_STATE_READY)
+  {
+    hsd->ErrorCode = HAL_SD_ERROR_NONE;
+
+    if((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr))
+    {
+      hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE;
+      return HAL_ERROR;
+    }
+
+    hsd->State = HAL_SD_STATE_BUSY;
+
+    /* Initialize data control register */
+    hsd->Instance->DCTRL = 0U;
+
+    hsd->pRxBuffPtr = pData;
+    hsd->RxXferSize = BLOCKSIZE * NumberOfBlocks;
+
+#if defined(SDIO_STA_STBITERR)
+    __HAL_SD_ENABLE_IT(hsd, (SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_RXOVERR | SDIO_IT_DATAEND | SDIO_FLAG_RXFIFOHF | SDIO_IT_STBITERR));
+#else /* SDIO_STA_STBITERR not defined */
+    __HAL_SD_ENABLE_IT(hsd, (SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_RXOVERR | SDIO_IT_DATAEND | SDIO_FLAG_RXFIFOHF));
+#endif /* SDIO_STA_STBITERR */
+
+    if(hsd->SdCard.CardType != CARD_SDHC_SDXC)
+    {
+      add *= 512U;
+    }
+
+    /* Configure the SD DPSM (Data Path State Machine) */
+    config.DataTimeOut   = SDMMC_DATATIMEOUT;
+    config.DataLength    = BLOCKSIZE * NumberOfBlocks;
+    config.DataBlockSize = SDIO_DATABLOCK_SIZE_512B;
+    config.TransferDir   = SDIO_TRANSFER_DIR_TO_SDIO;
+    config.TransferMode  = SDIO_TRANSFER_MODE_BLOCK;
+    config.DPSM          = SDIO_DPSM_ENABLE;
+    (void)SDIO_ConfigData(hsd->Instance, &config);
+
+    /* Read Blocks in IT mode */
+    if(NumberOfBlocks > 1U)
+    {
+      hsd->Context = (SD_CONTEXT_READ_MULTIPLE_BLOCK | SD_CONTEXT_IT);
+
+      /* Read Multi Block command */
+      errorstate = SDMMC_CmdReadMultiBlock(hsd->Instance, add);
+    }
+    else
+    {
+      hsd->Context = (SD_CONTEXT_READ_SINGLE_BLOCK | SD_CONTEXT_IT);
+
+      /* Read Single Block command */
+      errorstate = SDMMC_CmdReadSingleBlock(hsd->Instance, add);
+    }
+    if(errorstate != HAL_SD_ERROR_NONE)
+    {
+      /* Clear all the static flags */
+      __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
+      hsd->ErrorCode |= errorstate;
+      hsd->State = HAL_SD_STATE_READY;
+      hsd->Context = SD_CONTEXT_NONE;
+      return HAL_ERROR;
+    }
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Writes block(s) to a specified address in a card. The Data transfer
+  *         is managed in interrupt mode.
+  * @note   This API should be followed by a check on the card state through
+  *         HAL_SD_GetCardState().
+  * @note   You could also check the IT transfer process through the SD Tx
+  *         interrupt event.
+  * @param  hsd: Pointer to SD handle
+  * @param  pData: Pointer to the buffer that will contain the data to transmit
+  * @param  BlockAdd: Block Address where data will be written
+  * @param  NumberOfBlocks: Number of blocks to write
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SD_WriteBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks)
+{
+  SDIO_DataInitTypeDef config;
+  uint32_t errorstate;
+  uint32_t add = BlockAdd;
+
+  if(NULL == pData)
+  {
+    hsd->ErrorCode |= HAL_SD_ERROR_PARAM;
+    return HAL_ERROR;
+  }
+
+  if(hsd->State == HAL_SD_STATE_READY)
+  {
+    hsd->ErrorCode = HAL_SD_ERROR_NONE;
+
+    if((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr))
+    {
+      hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE;
+      return HAL_ERROR;
+    }
+
+    hsd->State = HAL_SD_STATE_BUSY;
+
+    /* Initialize data control register */
+    hsd->Instance->DCTRL = 0U;
+
+    hsd->pTxBuffPtr = pData;
+    hsd->TxXferSize = BLOCKSIZE * NumberOfBlocks;
+
+    /* Enable transfer interrupts */
+#if defined(SDIO_STA_STBITERR)
+    __HAL_SD_ENABLE_IT(hsd, (SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_TXUNDERR | SDIO_IT_DATAEND | SDIO_FLAG_TXFIFOHE | SDIO_IT_STBITERR));
+#else /* SDIO_STA_STBITERR not defined */
+    __HAL_SD_ENABLE_IT(hsd, (SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_TXUNDERR | SDIO_IT_DATAEND | SDIO_FLAG_TXFIFOHE));
+#endif /* SDIO_STA_STBITERR */
+
+    if(hsd->SdCard.CardType != CARD_SDHC_SDXC)
+    {
+      add *= 512U;
+    }
+
+    /* Write Blocks in Polling mode */
+    if(NumberOfBlocks > 1U)
+    {
+      hsd->Context = (SD_CONTEXT_WRITE_MULTIPLE_BLOCK| SD_CONTEXT_IT);
+
+      /* Write Multi Block command */
+      errorstate = SDMMC_CmdWriteMultiBlock(hsd->Instance, add);
+    }
+    else
+    {
+      hsd->Context = (SD_CONTEXT_WRITE_SINGLE_BLOCK | SD_CONTEXT_IT);
+
+      /* Write Single Block command */
+      errorstate = SDMMC_CmdWriteSingleBlock(hsd->Instance, add);
+    }
+    if(errorstate != HAL_SD_ERROR_NONE)
+    {
+      /* Clear all the static flags */
+      __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
+      hsd->ErrorCode |= errorstate;
+      hsd->State = HAL_SD_STATE_READY;
+      hsd->Context = SD_CONTEXT_NONE;
+      return HAL_ERROR;
+    }
+
+    /* Configure the SD DPSM (Data Path State Machine) */
+    config.DataTimeOut   = SDMMC_DATATIMEOUT;
+    config.DataLength    = BLOCKSIZE * NumberOfBlocks;
+    config.DataBlockSize = SDIO_DATABLOCK_SIZE_512B;
+    config.TransferDir   = SDIO_TRANSFER_DIR_TO_CARD;
+    config.TransferMode  = SDIO_TRANSFER_MODE_BLOCK;
+    config.DPSM          = SDIO_DPSM_ENABLE;
+    (void)SDIO_ConfigData(hsd->Instance, &config);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Reads block(s) from a specified address in a card. The Data transfer
+  *         is managed by DMA mode.
+  * @note   This API should be followed by a check on the card state through
+  *         HAL_SD_GetCardState().
+  * @note   You could also check the DMA transfer process through the SD Rx
+  *         interrupt event.
+  * @param  hsd: Pointer SD handle
+  * @param  pData: Pointer to the buffer that will contain the received data
+  * @param  BlockAdd: Block Address from where data is to be read
+  * @param  NumberOfBlocks: Number of blocks to read.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SD_ReadBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks)
+{
+  SDIO_DataInitTypeDef config;
+  uint32_t errorstate;
+  uint32_t add = BlockAdd;
+
+  if(NULL == pData)
+  {
+    hsd->ErrorCode |= HAL_SD_ERROR_PARAM;
+    return HAL_ERROR;
+  }
+
+  if(hsd->State == HAL_SD_STATE_READY)
+  {
+    hsd->ErrorCode = HAL_SD_ERROR_NONE;
+
+    if((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr))
+    {
+      hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE;
+      return HAL_ERROR;
+    }
+
+    hsd->State = HAL_SD_STATE_BUSY;
+
+    /* Initialize data control register */
+    hsd->Instance->DCTRL = 0U;
+
+#if defined(SDIO_STA_STBITERR)
+    __HAL_SD_ENABLE_IT(hsd, (SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_RXOVERR | SDIO_IT_DATAEND | SDIO_IT_STBITERR));
+#else /* SDIO_STA_STBITERR not defined */
+    __HAL_SD_ENABLE_IT(hsd, (SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_RXOVERR | SDIO_IT_DATAEND));
+#endif /* SDIO_STA_STBITERR */
+
+    /* Set the DMA transfer complete callback */
+    hsd->hdmarx->XferCpltCallback = SD_DMAReceiveCplt;
+
+    /* Set the DMA error callback */
+    hsd->hdmarx->XferErrorCallback = SD_DMAError;
+
+    /* Set the DMA Abort callback */
+    hsd->hdmarx->XferAbortCallback = NULL;
+
+    /* Force DMA Direction */
+    hsd->hdmarx->Init.Direction = DMA_PERIPH_TO_MEMORY;
+    MODIFY_REG(hsd->hdmarx->Instance->CR, DMA_SxCR_DIR, hsd->hdmarx->Init.Direction);
+
+    /* Enable the DMA Channel */
+    if(HAL_DMA_Start_IT(hsd->hdmarx, (uint32_t)&hsd->Instance->FIFO, (uint32_t)pData, (uint32_t)(BLOCKSIZE * NumberOfBlocks)/4U) != HAL_OK)
+    {
+      __HAL_SD_DISABLE_IT(hsd, (SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_RXOVERR | SDIO_IT_DATAEND));
+      __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
+      hsd->ErrorCode |= HAL_SD_ERROR_DMA;
+      hsd->State = HAL_SD_STATE_READY;
+      return HAL_ERROR;
+    }
+    else
+    {
+      /* Enable SD DMA transfer */
+      __HAL_SD_DMA_ENABLE(hsd);
+
+      if(hsd->SdCard.CardType != CARD_SDHC_SDXC)
+      {
+        add *= 512U;
+      }
+
+      /* Configure the SD DPSM (Data Path State Machine) */
+      config.DataTimeOut   = SDMMC_DATATIMEOUT;
+      config.DataLength    = BLOCKSIZE * NumberOfBlocks;
+      config.DataBlockSize = SDIO_DATABLOCK_SIZE_512B;
+      config.TransferDir   = SDIO_TRANSFER_DIR_TO_SDIO;
+      config.TransferMode  = SDIO_TRANSFER_MODE_BLOCK;
+      config.DPSM          = SDIO_DPSM_ENABLE;
+      (void)SDIO_ConfigData(hsd->Instance, &config);
+
+      /* Read Blocks in DMA mode */
+      if(NumberOfBlocks > 1U)
+      {
+        hsd->Context = (SD_CONTEXT_READ_MULTIPLE_BLOCK | SD_CONTEXT_DMA);
+
+        /* Read Multi Block command */
+        errorstate = SDMMC_CmdReadMultiBlock(hsd->Instance, add);
+      }
+      else
+      {
+        hsd->Context = (SD_CONTEXT_READ_SINGLE_BLOCK | SD_CONTEXT_DMA);
+
+        /* Read Single Block command */
+        errorstate = SDMMC_CmdReadSingleBlock(hsd->Instance, add);
+      }
+      if(errorstate != HAL_SD_ERROR_NONE)
+      {
+        /* Clear all the static flags */
+        __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
+        hsd->ErrorCode |= errorstate;
+        hsd->State = HAL_SD_STATE_READY;
+        hsd->Context = SD_CONTEXT_NONE;
+        return HAL_ERROR;
+      }
+
+      return HAL_OK;
+    }
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Writes block(s) to a specified address in a card. The Data transfer
+  *         is managed by DMA mode.
+  * @note   This API should be followed by a check on the card state through
+  *         HAL_SD_GetCardState().
+  * @note   You could also check the DMA transfer process through the SD Tx
+  *         interrupt event.
+  * @param  hsd: Pointer to SD handle
+  * @param  pData: Pointer to the buffer that will contain the data to transmit
+  * @param  BlockAdd: Block Address where data will be written
+  * @param  NumberOfBlocks: Number of blocks to write
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks)
+{
+  SDIO_DataInitTypeDef config;
+  uint32_t errorstate;
+  uint32_t add = BlockAdd;
+
+  if(NULL == pData)
+  {
+    hsd->ErrorCode |= HAL_SD_ERROR_PARAM;
+    return HAL_ERROR;
+  }
+
+  if(hsd->State == HAL_SD_STATE_READY)
+  {
+    hsd->ErrorCode = HAL_SD_ERROR_NONE;
+
+    if((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr))
+    {
+      hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE;
+      return HAL_ERROR;
+    }
+
+    hsd->State = HAL_SD_STATE_BUSY;
+
+    /* Initialize data control register */
+    hsd->Instance->DCTRL = 0U;
+
+    /* Enable SD Error interrupts */
+#if defined(SDIO_STA_STBITERR)
+    __HAL_SD_ENABLE_IT(hsd, (SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_TXUNDERR | SDIO_IT_STBITERR));
+#else /* SDIO_STA_STBITERR not defined */
+    __HAL_SD_ENABLE_IT(hsd, (SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_TXUNDERR));   
+#endif /* SDIO_STA_STBITERR */
+
+    /* Set the DMA transfer complete callback */
+    hsd->hdmatx->XferCpltCallback = SD_DMATransmitCplt;
+
+    /* Set the DMA error callback */
+    hsd->hdmatx->XferErrorCallback = SD_DMAError;
+
+    /* Set the DMA Abort callback */
+    hsd->hdmatx->XferAbortCallback = NULL;
+
+    if(hsd->SdCard.CardType != CARD_SDHC_SDXC)
+    {
+      add *= 512U;
+    }
+
+    /* Write Blocks in Polling mode */
+    if(NumberOfBlocks > 1U)
+    {
+      hsd->Context = (SD_CONTEXT_WRITE_MULTIPLE_BLOCK | SD_CONTEXT_DMA);
+
+      /* Write Multi Block command */
+      errorstate = SDMMC_CmdWriteMultiBlock(hsd->Instance, add);
+    }
+    else
+    {
+      hsd->Context = (SD_CONTEXT_WRITE_SINGLE_BLOCK | SD_CONTEXT_DMA);
+
+      /* Write Single Block command */
+      errorstate = SDMMC_CmdWriteSingleBlock(hsd->Instance, add);
+    }
+    if(errorstate != HAL_SD_ERROR_NONE)
+    {
+      /* Clear all the static flags */
+      __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
+      hsd->ErrorCode |= errorstate;
+      hsd->State = HAL_SD_STATE_READY;
+      hsd->Context = SD_CONTEXT_NONE;
+      return HAL_ERROR;
+    }
+
+    /* Enable SDIO DMA transfer */
+    __HAL_SD_DMA_ENABLE(hsd);
+
+    /* Force DMA Direction */
+    hsd->hdmatx->Init.Direction = DMA_MEMORY_TO_PERIPH;
+    MODIFY_REG(hsd->hdmatx->Instance->CR, DMA_SxCR_DIR, hsd->hdmatx->Init.Direction);
+
+    /* Enable the DMA Channel */
+    if(HAL_DMA_Start_IT(hsd->hdmatx, (uint32_t)pData, (uint32_t)&hsd->Instance->FIFO, (uint32_t)(BLOCKSIZE * NumberOfBlocks)/4U) != HAL_OK)
+    {
+#if defined(SDIO_STA_STBITERR)
+      __HAL_SD_DISABLE_IT(hsd, (SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_TXUNDERR | SDIO_IT_STBITERR));
+#else /* SDIO_STA_STBITERR not defined */
+      __HAL_SD_DISABLE_IT(hsd, (SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_TXUNDERR));   
+#endif /* SDIO_STA_STBITERR */
+      __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
+      hsd->ErrorCode |= HAL_SD_ERROR_DMA;
+      hsd->State = HAL_SD_STATE_READY;
+      hsd->Context = SD_CONTEXT_NONE;
+      return HAL_ERROR;
+    }
+    else
+    {
+      /* Configure the SD DPSM (Data Path State Machine) */
+      config.DataTimeOut   = SDMMC_DATATIMEOUT;
+      config.DataLength    = BLOCKSIZE * NumberOfBlocks;
+      config.DataBlockSize = SDIO_DATABLOCK_SIZE_512B;
+      config.TransferDir   = SDIO_TRANSFER_DIR_TO_CARD;
+      config.TransferMode  = SDIO_TRANSFER_MODE_BLOCK;
+      config.DPSM          = SDIO_DPSM_ENABLE;
+      (void)SDIO_ConfigData(hsd->Instance, &config);
+
+      return HAL_OK;
+    }
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Erases the specified memory area of the given SD card.
+  * @note   This API should be followed by a check on the card state through
+  *         HAL_SD_GetCardState().
+  * @param  hsd: Pointer to SD handle
+  * @param  BlockStartAdd: Start Block address
+  * @param  BlockEndAdd: End Block address
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SD_Erase(SD_HandleTypeDef *hsd, uint32_t BlockStartAdd, uint32_t BlockEndAdd)
+{
+  uint32_t errorstate;
+  uint32_t start_add = BlockStartAdd;
+  uint32_t end_add = BlockEndAdd;
+
+  if(hsd->State == HAL_SD_STATE_READY)
+  {
+    hsd->ErrorCode = HAL_SD_ERROR_NONE;
+
+    if(end_add < start_add)
+    {
+      hsd->ErrorCode |= HAL_SD_ERROR_PARAM;
+      return HAL_ERROR;
+    }
+
+    if(end_add > (hsd->SdCard.LogBlockNbr))
+    {
+      hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE;
+      return HAL_ERROR;
+    }
+
+    hsd->State = HAL_SD_STATE_BUSY;
+
+    /* Check if the card command class supports erase command */
+    if(((hsd->SdCard.Class) & SDIO_CCCC_ERASE) == 0U)
+    {
+      /* Clear all the static flags */
+      __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
+      hsd->ErrorCode |= HAL_SD_ERROR_REQUEST_NOT_APPLICABLE;
+      hsd->State = HAL_SD_STATE_READY;
+      return HAL_ERROR;
+    }
+
+    if((SDIO_GetResponse(hsd->Instance, SDIO_RESP1) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED)
+    {
+      /* Clear all the static flags */
+      __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
+      hsd->ErrorCode |= HAL_SD_ERROR_LOCK_UNLOCK_FAILED;
+      hsd->State = HAL_SD_STATE_READY;
+      return HAL_ERROR;
+    }
+
+    /* Get start and end block for high capacity cards */
+    if(hsd->SdCard.CardType != CARD_SDHC_SDXC)
+    {
+      start_add *= 512U;
+      end_add   *= 512U;
+    }
+
+    /* According to sd-card spec 1.0 ERASE_GROUP_START (CMD32) and erase_group_end(CMD33) */
+    if(hsd->SdCard.CardType != CARD_SECURED)
+    {
+      /* Send CMD32 SD_ERASE_GRP_START with argument as addr  */
+      errorstate = SDMMC_CmdSDEraseStartAdd(hsd->Instance, start_add);
+      if(errorstate != HAL_SD_ERROR_NONE)
+      {
+        /* Clear all the static flags */
+        __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
+        hsd->ErrorCode |= errorstate;
+        hsd->State = HAL_SD_STATE_READY;
+        return HAL_ERROR;
+      }
+
+      /* Send CMD33 SD_ERASE_GRP_END with argument as addr  */
+      errorstate = SDMMC_CmdSDEraseEndAdd(hsd->Instance, end_add);
+      if(errorstate != HAL_SD_ERROR_NONE)
+      {
+        /* Clear all the static flags */
+        __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
+        hsd->ErrorCode |= errorstate;
+        hsd->State = HAL_SD_STATE_READY;
+        return HAL_ERROR;
+      }
+    }
+
+    /* Send CMD38 ERASE */
+    errorstate = SDMMC_CmdErase(hsd->Instance);
+    if(errorstate != HAL_SD_ERROR_NONE)
+    {
+      /* Clear all the static flags */
+      __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
+      hsd->ErrorCode |= errorstate;
+      hsd->State = HAL_SD_STATE_READY;
+      return HAL_ERROR;
+    }
+
+    hsd->State = HAL_SD_STATE_READY;
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  This function handles SD card interrupt request.
+  * @param  hsd: Pointer to SD handle
+  * @retval None
+  */
+void HAL_SD_IRQHandler(SD_HandleTypeDef *hsd)
+{
+  uint32_t errorstate;
+  uint32_t context = hsd->Context;
+
+  /* Check for SDIO interrupt flags */
+  if((__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_RXFIFOHF) != RESET) && ((context & SD_CONTEXT_IT) != 0U))
+  {
+    SD_Read_IT(hsd);
+  }
+
+  else if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_DATAEND) != RESET)
+  {
+    __HAL_SD_CLEAR_FLAG(hsd, SDIO_FLAG_DATAEND);
+
+#if defined(SDIO_STA_STBITERR)
+    __HAL_SD_DISABLE_IT(hsd, SDIO_IT_DATAEND  | SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT|\
+                             SDIO_IT_TXUNDERR | SDIO_IT_RXOVERR  | SDIO_IT_TXFIFOHE |\
+                             SDIO_IT_RXFIFOHF | SDIO_IT_STBITERR);
+#else /* SDIO_STA_STBITERR not defined */
+    __HAL_SD_DISABLE_IT(hsd, SDIO_IT_DATAEND  | SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT|\
+                             SDIO_IT_TXUNDERR | SDIO_IT_RXOVERR  | SDIO_IT_TXFIFOHE |\
+                             SDIO_IT_RXFIFOHF);
+#endif /* SDIO_STA_STBITERR */
+
+    hsd->Instance->DCTRL &= ~(SDIO_DCTRL_DTEN);
+    
+    if((context & SD_CONTEXT_IT) != 0U)
+    {
+      if(((context & SD_CONTEXT_READ_MULTIPLE_BLOCK) != 0U) || ((context & SD_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U))
+      {
+        errorstate = SDMMC_CmdStopTransfer(hsd->Instance);
+        if(errorstate != HAL_SD_ERROR_NONE)
+        {
+          hsd->ErrorCode |= errorstate;
+#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
+          hsd->ErrorCallback(hsd);
+#else
+          HAL_SD_ErrorCallback(hsd);
+#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
+        }
+      }
+
+      /* Clear all the static flags */
+      __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_DATA_FLAGS);
+
+      hsd->State = HAL_SD_STATE_READY;
+      hsd->Context = SD_CONTEXT_NONE;
+      if(((context & SD_CONTEXT_READ_SINGLE_BLOCK) != 0U) || ((context & SD_CONTEXT_READ_MULTIPLE_BLOCK) != 0U))
+      {
+#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
+        hsd->RxCpltCallback(hsd);
+#else
+        HAL_SD_RxCpltCallback(hsd);
+#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
+      }
+      else
+      {
+#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
+        hsd->TxCpltCallback(hsd);
+#else
+        HAL_SD_TxCpltCallback(hsd);
+#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
+      }
+    }
+    else if((context & SD_CONTEXT_DMA) != 0U)
+    {
+      if((context & SD_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U)
+      {
+        errorstate = SDMMC_CmdStopTransfer(hsd->Instance);
+        if(errorstate != HAL_SD_ERROR_NONE)
+        {
+          hsd->ErrorCode |= errorstate;
+#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
+          hsd->ErrorCallback(hsd);
+#else
+          HAL_SD_ErrorCallback(hsd);
+#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
+        }
+      }
+      if(((context & SD_CONTEXT_READ_SINGLE_BLOCK) == 0U) && ((context & SD_CONTEXT_READ_MULTIPLE_BLOCK) == 0U))
+      {
+        /* Disable the DMA transfer for transmit request by setting the DMAEN bit
+        in the SD DCTRL register */
+        hsd->Instance->DCTRL &= (uint32_t)~((uint32_t)SDIO_DCTRL_DMAEN);
+
+        hsd->State = HAL_SD_STATE_READY;
+
+#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
+        hsd->TxCpltCallback(hsd);
+#else
+        HAL_SD_TxCpltCallback(hsd);
+#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
+      }
+    }
+    else
+    {
+      /* Nothing to do */
+    }
+  }
+
+  else if((__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_TXFIFOHE) != RESET) && ((context & SD_CONTEXT_IT) != 0U))
+  {
+    SD_Write_IT(hsd);
+  }
+
+#if defined(SDIO_STA_STBITERR)
+  else if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_RXOVERR | SDIO_FLAG_TXUNDERR | SDIO_FLAG_STBITERR) != RESET)
+#else /* SDIO_STA_STBITERR not defined */
+  else if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_RXOVERR | SDIO_FLAG_TXUNDERR) != RESET)
+#endif /* SDIO_STA_STBITERR */
+  {
+    /* Set Error code */
+    if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_DCRCFAIL) != RESET)
+    {
+      hsd->ErrorCode |= HAL_SD_ERROR_DATA_CRC_FAIL;
+    }
+    if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_DTIMEOUT) != RESET)
+    {
+      hsd->ErrorCode |= HAL_SD_ERROR_DATA_TIMEOUT;
+    }
+    if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_RXOVERR) != RESET)
+    {
+      hsd->ErrorCode |= HAL_SD_ERROR_RX_OVERRUN;
+    }
+    if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_TXUNDERR) != RESET)
+    {
+      hsd->ErrorCode |= HAL_SD_ERROR_TX_UNDERRUN;
+    }
+#if defined(SDIO_STA_STBITERR)
+    if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_STBITERR) != RESET)
+    {
+      hsd->ErrorCode |= HAL_SD_ERROR_DATA_TIMEOUT;
+    }
+#endif /* SDIO_STA_STBITERR */
+
+#if defined(SDIO_STA_STBITERR)
+    /* Clear All flags */
+    __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_DATA_FLAGS | SDIO_FLAG_STBITERR);
+
+    /* Disable all interrupts */
+    __HAL_SD_DISABLE_IT(hsd, SDIO_IT_DATAEND | SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT|\
+                             SDIO_IT_TXUNDERR| SDIO_IT_RXOVERR | SDIO_IT_STBITERR);
+#else /* SDIO_STA_STBITERR not defined */
+    /* Clear All flags */
+    __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_DATA_FLAGS);
+
+    /* Disable all interrupts */
+    __HAL_SD_DISABLE_IT(hsd, SDIO_IT_DATAEND | SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT|\
+                             SDIO_IT_TXUNDERR| SDIO_IT_RXOVERR);
+#endif /* SDIO_STA_STBITERR */
+
+    hsd->ErrorCode |= SDMMC_CmdStopTransfer(hsd->Instance);
+
+    if((context & SD_CONTEXT_IT) != 0U)
+    {
+      /* Set the SD state to ready to be able to start again the process */
+      hsd->State = HAL_SD_STATE_READY;
+      hsd->Context = SD_CONTEXT_NONE;
+#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
+      hsd->ErrorCallback(hsd);
+#else
+      HAL_SD_ErrorCallback(hsd);
+#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
+    }
+    else if((context & SD_CONTEXT_DMA) != 0U)
+    {
+      /* Abort the SD DMA channel */
+      if(((context & SD_CONTEXT_WRITE_SINGLE_BLOCK) != 0U) || ((context & SD_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U))
+      {
+        /* Set the DMA Tx abort callback */
+        hsd->hdmatx->XferAbortCallback = SD_DMATxAbort;
+        /* Abort DMA in IT mode */
+        if(HAL_DMA_Abort_IT(hsd->hdmatx) != HAL_OK)
+        {
+          SD_DMATxAbort(hsd->hdmatx);
+        }
+      }
+      else if(((context & SD_CONTEXT_READ_SINGLE_BLOCK) != 0U) || ((context & SD_CONTEXT_READ_MULTIPLE_BLOCK) != 0U))
+      {
+        /* Set the DMA Rx abort callback */
+        hsd->hdmarx->XferAbortCallback = SD_DMARxAbort;
+        /* Abort DMA in IT mode */
+        if(HAL_DMA_Abort_IT(hsd->hdmarx) != HAL_OK)
+        {
+          SD_DMARxAbort(hsd->hdmarx);
+        }
+      }
+      else
+      {
+        hsd->ErrorCode = HAL_SD_ERROR_NONE;
+        hsd->State = HAL_SD_STATE_READY;
+        hsd->Context = SD_CONTEXT_NONE;
+#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
+        hsd->AbortCpltCallback(hsd);
+#else
+        HAL_SD_AbortCallback(hsd);
+#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
+      }
+    }
+    else
+    {
+      /* Nothing to do */
+    }
+  }
+  else
+  {
+    /* Nothing to do */
+  }
+}
+
+/**
+  * @brief return the SD state
+  * @param hsd: Pointer to sd handle
+  * @retval HAL state
+  */
+HAL_SD_StateTypeDef HAL_SD_GetState(SD_HandleTypeDef *hsd)
+{
+  return hsd->State;
+}
+
+/**
+* @brief  Return the SD error code
+* @param  hsd : Pointer to a SD_HandleTypeDef structure that contains
+  *              the configuration information.
+* @retval SD Error Code
+*/
+uint32_t HAL_SD_GetError(SD_HandleTypeDef *hsd)
+{
+  return hsd->ErrorCode;
+}
+
+/**
+  * @brief Tx Transfer completed callbacks
+  * @param hsd: Pointer to SD handle
+  * @retval None
+  */
+__weak void HAL_SD_TxCpltCallback(SD_HandleTypeDef *hsd)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hsd);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_SD_TxCpltCallback can be implemented in the user file
+   */
+}
+
+/**
+  * @brief Rx Transfer completed callbacks
+  * @param hsd: Pointer SD handle
+  * @retval None
+  */
+__weak void HAL_SD_RxCpltCallback(SD_HandleTypeDef *hsd)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hsd);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_SD_RxCpltCallback can be implemented in the user file
+   */
+}
+
+/**
+  * @brief SD error callbacks
+  * @param hsd: Pointer SD handle
+  * @retval None
+  */
+__weak void HAL_SD_ErrorCallback(SD_HandleTypeDef *hsd)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hsd);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_SD_ErrorCallback can be implemented in the user file
+   */
+}
+
+/**
+  * @brief SD Abort callbacks
+  * @param hsd: Pointer SD handle
+  * @retval None
+  */
+__weak void HAL_SD_AbortCallback(SD_HandleTypeDef *hsd)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hsd);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_SD_AbortCallback can be implemented in the user file
+   */
+}
+
+#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
+/**
+  * @brief  Register a User SD Callback
+  *         To be used instead of the weak (surcharged) predefined callback
+  * @param hsd : SD handle
+  * @param CallbackID : ID of the callback to be registered
+  *        This parameter can be one of the following values:
+  *          @arg @ref HAL_SD_TX_CPLT_CB_ID    SD Tx Complete Callback ID
+  *          @arg @ref HAL_SD_RX_CPLT_CB_ID    SD Rx Complete Callback ID
+  *          @arg @ref HAL_SD_ERROR_CB_ID      SD Error Callback ID
+  *          @arg @ref HAL_SD_ABORT_CB_ID      SD Abort Callback ID
+  *          @arg @ref HAL_SD_MSP_INIT_CB_ID   SD MspInit Callback ID
+  *          @arg @ref HAL_SD_MSP_DEINIT_CB_ID SD MspDeInit Callback ID
+  * @param pCallback : pointer to the Callback function
+  * @retval status
+  */
+HAL_StatusTypeDef HAL_SD_RegisterCallback(SD_HandleTypeDef *hsd, HAL_SD_CallbackIDTypeDef CallbackID, pSD_CallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if(pCallback == NULL)
+  {
+    /* Update the error code */
+    hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK;
+    return HAL_ERROR;
+  }
+
+  /* Process locked */
+  __HAL_LOCK(hsd);
+
+  if(hsd->State == HAL_SD_STATE_READY)
+  {
+    switch (CallbackID)
+    {
+    case HAL_SD_TX_CPLT_CB_ID :
+      hsd->TxCpltCallback = pCallback;
+      break;
+    case HAL_SD_RX_CPLT_CB_ID :
+      hsd->RxCpltCallback = pCallback;
+      break;
+    case HAL_SD_ERROR_CB_ID :
+      hsd->ErrorCallback = pCallback;
+      break;
+    case HAL_SD_ABORT_CB_ID :
+      hsd->AbortCpltCallback = pCallback;
+      break;
+    case HAL_SD_MSP_INIT_CB_ID :
+      hsd->MspInitCallback = pCallback;
+      break;
+    case HAL_SD_MSP_DEINIT_CB_ID :
+      hsd->MspDeInitCallback = pCallback;
+      break;
+    default :
+      /* Update the error code */
+      hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK;
+      /* update return status */
+      status =  HAL_ERROR;
+      break;
+    }
+  }
+  else if (hsd->State == HAL_SD_STATE_RESET)
+  {
+    switch (CallbackID)
+    {
+    case HAL_SD_MSP_INIT_CB_ID :
+      hsd->MspInitCallback = pCallback;
+      break;
+    case HAL_SD_MSP_DEINIT_CB_ID :
+      hsd->MspDeInitCallback = pCallback;
+      break;
+    default :
+      /* Update the error code */
+      hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK;
+      /* update return status */
+      status =  HAL_ERROR;
+      break;
+    }
+  }
+  else
+  {
+    /* Update the error code */
+    hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK;
+    /* update return status */
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(hsd);
+  return status;
+}
+
+/**
+  * @brief  Unregister a User SD Callback
+  *         SD Callback is redirected to the weak (surcharged) predefined callback
+  * @param hsd : SD handle
+  * @param CallbackID : ID of the callback to be unregistered
+  *        This parameter can be one of the following values:
+  *          @arg @ref HAL_SD_TX_CPLT_CB_ID    SD Tx Complete Callback ID
+  *          @arg @ref HAL_SD_RX_CPLT_CB_ID    SD Rx Complete Callback ID
+  *          @arg @ref HAL_SD_ERROR_CB_ID      SD Error Callback ID
+  *          @arg @ref HAL_SD_ABORT_CB_ID      SD Abort Callback ID
+  *          @arg @ref HAL_SD_MSP_INIT_CB_ID   SD MspInit Callback ID
+  *          @arg @ref HAL_SD_MSP_DEINIT_CB_ID SD MspDeInit Callback ID
+  * @retval status
+  */
+HAL_StatusTypeDef HAL_SD_UnRegisterCallback(SD_HandleTypeDef *hsd, HAL_SD_CallbackIDTypeDef CallbackID)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Process locked */
+  __HAL_LOCK(hsd);
+
+  if(hsd->State == HAL_SD_STATE_READY)
+  {
+    switch (CallbackID)
+    {
+    case HAL_SD_TX_CPLT_CB_ID :
+      hsd->TxCpltCallback = HAL_SD_TxCpltCallback;
+      break;
+    case HAL_SD_RX_CPLT_CB_ID :
+      hsd->RxCpltCallback = HAL_SD_RxCpltCallback;
+      break;
+    case HAL_SD_ERROR_CB_ID :
+      hsd->ErrorCallback = HAL_SD_ErrorCallback;
+      break;
+    case HAL_SD_ABORT_CB_ID :
+      hsd->AbortCpltCallback = HAL_SD_AbortCallback;
+      break;
+    case HAL_SD_MSP_INIT_CB_ID :
+      hsd->MspInitCallback = HAL_SD_MspInit;
+      break;
+    case HAL_SD_MSP_DEINIT_CB_ID :
+      hsd->MspDeInitCallback = HAL_SD_MspDeInit;
+      break;
+    default :
+      /* Update the error code */
+      hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK;
+      /* update return status */
+      status =  HAL_ERROR;
+      break;
+    }
+  }
+  else if (hsd->State == HAL_SD_STATE_RESET)
+  {
+    switch (CallbackID)
+    {
+    case HAL_SD_MSP_INIT_CB_ID :
+      hsd->MspInitCallback = HAL_SD_MspInit;
+      break;
+    case HAL_SD_MSP_DEINIT_CB_ID :
+      hsd->MspDeInitCallback = HAL_SD_MspDeInit;
+      break;
+    default :
+      /* Update the error code */
+      hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK;
+      /* update return status */
+      status =  HAL_ERROR;
+      break;
+    }
+  }
+  else
+  {
+    /* Update the error code */
+    hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK;
+    /* update return status */
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(hsd);
+  return status;
+}
+#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+
+/** @addtogroup SD_Exported_Functions_Group3
+ *  @brief   management functions
+ *
+@verbatim
+  ==============================================================================
+                      ##### Peripheral Control functions #####
+  ==============================================================================
+  [..]
+    This subsection provides a set of functions allowing to control the SD card
+    operations and get the related information
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Returns information the information of the card which are stored on
+  *         the CID register.
+  * @param  hsd: Pointer to SD handle
+  * @param  pCID: Pointer to a HAL_SD_CardCIDTypeDef structure that  
+  *         contains all CID register parameters
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SD_GetCardCID(SD_HandleTypeDef *hsd, HAL_SD_CardCIDTypeDef *pCID)
+{
+  pCID->ManufacturerID = (uint8_t)((hsd->CID[0] & 0xFF000000U) >> 24U);
+
+  pCID->OEM_AppliID = (uint16_t)((hsd->CID[0] & 0x00FFFF00U) >> 8U);
+
+  pCID->ProdName1 = (((hsd->CID[0] & 0x000000FFU) << 24U) | ((hsd->CID[1] & 0xFFFFFF00U) >> 8U));
+
+  pCID->ProdName2 = (uint8_t)(hsd->CID[1] & 0x000000FFU);
+
+  pCID->ProdRev = (uint8_t)((hsd->CID[2] & 0xFF000000U) >> 24U);
+
+  pCID->ProdSN = (((hsd->CID[2] & 0x00FFFFFFU) << 8U) | ((hsd->CID[3] & 0xFF000000U) >> 24U));
+
+  pCID->Reserved1 = (uint8_t)((hsd->CID[3] & 0x00F00000U) >> 20U);
+
+  pCID->ManufactDate = (uint16_t)((hsd->CID[3] & 0x000FFF00U) >> 8U);
+
+  pCID->CID_CRC = (uint8_t)((hsd->CID[3] & 0x000000FEU) >> 1U);
+
+  pCID->Reserved2 = 1U;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Returns information the information of the card which are stored on
+  *         the CSD register.
+  * @param  hsd: Pointer to SD handle
+  * @param  pCSD: Pointer to a HAL_SD_CardCSDTypeDef structure that  
+  *         contains all CSD register parameters
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SD_GetCardCSD(SD_HandleTypeDef *hsd, HAL_SD_CardCSDTypeDef *pCSD)
+{
+  pCSD->CSDStruct = (uint8_t)((hsd->CSD[0] & 0xC0000000U) >> 30U);
+
+  pCSD->SysSpecVersion = (uint8_t)((hsd->CSD[0] & 0x3C000000U) >> 26U);
+
+  pCSD->Reserved1 = (uint8_t)((hsd->CSD[0] & 0x03000000U) >> 24U);
+
+  pCSD->TAAC = (uint8_t)((hsd->CSD[0] & 0x00FF0000U) >> 16U);
+
+  pCSD->NSAC = (uint8_t)((hsd->CSD[0] & 0x0000FF00U) >> 8U);
+
+  pCSD->MaxBusClkFrec = (uint8_t)(hsd->CSD[0] & 0x000000FFU);
+
+  pCSD->CardComdClasses = (uint16_t)((hsd->CSD[1] & 0xFFF00000U) >> 20U);
+
+  pCSD->RdBlockLen = (uint8_t)((hsd->CSD[1] & 0x000F0000U) >> 16U);
+
+  pCSD->PartBlockRead   = (uint8_t)((hsd->CSD[1] & 0x00008000U) >> 15U);
+
+  pCSD->WrBlockMisalign = (uint8_t)((hsd->CSD[1] & 0x00004000U) >> 14U);
+
+  pCSD->RdBlockMisalign = (uint8_t)((hsd->CSD[1] & 0x00002000U) >> 13U);
+
+  pCSD->DSRImpl = (uint8_t)((hsd->CSD[1] & 0x00001000U) >> 12U);
+
+  pCSD->Reserved2 = 0U; /*!< Reserved */
+
+  if(hsd->SdCard.CardType == CARD_SDSC)
+  {
+    pCSD->DeviceSize = (((hsd->CSD[1] & 0x000003FFU) << 2U) | ((hsd->CSD[2] & 0xC0000000U) >> 30U));
+
+    pCSD->MaxRdCurrentVDDMin = (uint8_t)((hsd->CSD[2] & 0x38000000U) >> 27U);
+
+    pCSD->MaxRdCurrentVDDMax = (uint8_t)((hsd->CSD[2] & 0x07000000U) >> 24U);
+
+    pCSD->MaxWrCurrentVDDMin = (uint8_t)((hsd->CSD[2] & 0x00E00000U) >> 21U);
+
+    pCSD->MaxWrCurrentVDDMax = (uint8_t)((hsd->CSD[2] & 0x001C0000U) >> 18U);
+
+    pCSD->DeviceSizeMul = (uint8_t)((hsd->CSD[2] & 0x00038000U) >> 15U);
+
+    hsd->SdCard.BlockNbr  = (pCSD->DeviceSize + 1U) ;
+    hsd->SdCard.BlockNbr *= (1UL << ((pCSD->DeviceSizeMul & 0x07U) + 2U));
+    hsd->SdCard.BlockSize = (1UL << (pCSD->RdBlockLen & 0x0FU));
+
+    hsd->SdCard.LogBlockNbr =  (hsd->SdCard.BlockNbr) * ((hsd->SdCard.BlockSize) / 512U);
+    hsd->SdCard.LogBlockSize = 512U;
+  }
+  else if(hsd->SdCard.CardType == CARD_SDHC_SDXC)
+  {
+    /* Byte 7 */
+    pCSD->DeviceSize = (((hsd->CSD[1] & 0x0000003FU) << 16U) | ((hsd->CSD[2] & 0xFFFF0000U) >> 16U));
+
+    hsd->SdCard.BlockNbr = ((pCSD->DeviceSize + 1U) * 1024U);
+    hsd->SdCard.LogBlockNbr = hsd->SdCard.BlockNbr;
+    hsd->SdCard.BlockSize = 512U;
+    hsd->SdCard.LogBlockSize = hsd->SdCard.BlockSize;
+  }
+  else
+  {
+    /* Clear all the static flags */
+    __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
+    hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE;
+    hsd->State = HAL_SD_STATE_READY;
+    return HAL_ERROR;
+  }
+
+  pCSD->EraseGrSize = (uint8_t)((hsd->CSD[2] & 0x00004000U) >> 14U);
+
+  pCSD->EraseGrMul = (uint8_t)((hsd->CSD[2] & 0x00003F80U) >> 7U);
+
+  pCSD->WrProtectGrSize = (uint8_t)(hsd->CSD[2] & 0x0000007FU);
+
+  pCSD->WrProtectGrEnable = (uint8_t)((hsd->CSD[3] & 0x80000000U) >> 31U);
+
+  pCSD->ManDeflECC = (uint8_t)((hsd->CSD[3] & 0x60000000U) >> 29U);
+
+  pCSD->WrSpeedFact = (uint8_t)((hsd->CSD[3] & 0x1C000000U) >> 26U);
+
+  pCSD->MaxWrBlockLen= (uint8_t)((hsd->CSD[3] & 0x03C00000U) >> 22U);
+
+  pCSD->WriteBlockPaPartial = (uint8_t)((hsd->CSD[3] & 0x00200000U) >> 21U);
+
+  pCSD->Reserved3 = 0;
+
+  pCSD->ContentProtectAppli = (uint8_t)((hsd->CSD[3] & 0x00010000U) >> 16U);
+
+  pCSD->FileFormatGroup = (uint8_t)((hsd->CSD[3] & 0x00008000U) >> 15U);
+
+  pCSD->CopyFlag = (uint8_t)((hsd->CSD[3] & 0x00004000U) >> 14U);
+
+  pCSD->PermWrProtect = (uint8_t)((hsd->CSD[3] & 0x00002000U) >> 13U);
+
+  pCSD->TempWrProtect = (uint8_t)((hsd->CSD[3] & 0x00001000U) >> 12U);
+
+  pCSD->FileFormat = (uint8_t)((hsd->CSD[3] & 0x00000C00U) >> 10U);
+
+  pCSD->ECC= (uint8_t)((hsd->CSD[3] & 0x00000300U) >> 8U);
+
+  pCSD->CSD_CRC = (uint8_t)((hsd->CSD[3] & 0x000000FEU) >> 1U);
+
+  pCSD->Reserved4 = 1;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Gets the SD status info.
+  * @param  hsd: Pointer to SD handle
+  * @param  pStatus: Pointer to the HAL_SD_CardStatusTypeDef structure that 
+  *         will contain the SD card status information
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SD_GetCardStatus(SD_HandleTypeDef *hsd, HAL_SD_CardStatusTypeDef *pStatus)
+{
+  uint32_t sd_status[16];
+  uint32_t errorstate;
+  HAL_StatusTypeDef status = HAL_OK;
+
+  errorstate = SD_SendSDStatus(hsd, sd_status);
+  if(errorstate != HAL_SD_ERROR_NONE)
+  {
+    /* Clear all the static flags */
+    __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
+    hsd->ErrorCode |= errorstate;
+    hsd->State = HAL_SD_STATE_READY;
+    status = HAL_ERROR;
+  }
+  else
+  {
+    pStatus->DataBusWidth = (uint8_t)((sd_status[0] & 0xC0U) >> 6U);
+
+    pStatus->SecuredMode = (uint8_t)((sd_status[0] & 0x20U) >> 5U);
+
+    pStatus->CardType = (uint16_t)(((sd_status[0] & 0x00FF0000U) >> 8U) | ((sd_status[0] & 0xFF000000U) >> 24U));
+
+    pStatus->ProtectedAreaSize = (((sd_status[1] & 0xFFU) << 24U)    | ((sd_status[1] & 0xFF00U) << 8U) |
+                                  ((sd_status[1] & 0xFF0000U) >> 8U) | ((sd_status[1] & 0xFF000000U) >> 24U));
+
+    pStatus->SpeedClass = (uint8_t)(sd_status[2] & 0xFFU);
+
+    pStatus->PerformanceMove = (uint8_t)((sd_status[2] & 0xFF00U) >> 8U);
+
+    pStatus->AllocationUnitSize = (uint8_t)((sd_status[2] & 0xF00000U) >> 20U);
+
+    pStatus->EraseSize = (uint16_t)(((sd_status[2] & 0xFF000000U) >> 16U) | (sd_status[3] & 0xFFU));
+
+    pStatus->EraseTimeout = (uint8_t)((sd_status[3] & 0xFC00U) >> 10U);
+
+    pStatus->EraseOffset = (uint8_t)((sd_status[3] & 0x0300U) >> 8U);
+  }
+
+  /* Set Block Size for Card */
+  errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE);
+  if(errorstate != HAL_SD_ERROR_NONE)
+  {
+    /* Clear all the static flags */
+    __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
+    hsd->ErrorCode = errorstate;
+    hsd->State = HAL_SD_STATE_READY;
+    status = HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Gets the SD card info.
+  * @param  hsd: Pointer to SD handle
+  * @param  pCardInfo: Pointer to the HAL_SD_CardInfoTypeDef structure that
+  *         will contain the SD card status information
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SD_GetCardInfo(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypeDef *pCardInfo)
+{
+  pCardInfo->CardType     = (uint32_t)(hsd->SdCard.CardType);
+  pCardInfo->CardVersion  = (uint32_t)(hsd->SdCard.CardVersion);
+  pCardInfo->Class        = (uint32_t)(hsd->SdCard.Class);
+  pCardInfo->RelCardAdd   = (uint32_t)(hsd->SdCard.RelCardAdd);
+  pCardInfo->BlockNbr     = (uint32_t)(hsd->SdCard.BlockNbr);
+  pCardInfo->BlockSize    = (uint32_t)(hsd->SdCard.BlockSize);
+  pCardInfo->LogBlockNbr  = (uint32_t)(hsd->SdCard.LogBlockNbr);
+  pCardInfo->LogBlockSize = (uint32_t)(hsd->SdCard.LogBlockSize);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Enables wide bus operation for the requested card if supported by
+  *         card.
+  * @param  hsd: Pointer to SD handle
+  * @param  WideMode: Specifies the SD card wide bus mode
+  *          This parameter can be one of the following values:
+  *            @arg SDIO_BUS_WIDE_8B: 8-bit data transfer
+  *            @arg SDIO_BUS_WIDE_4B: 4-bit data transfer
+  *            @arg SDIO_BUS_WIDE_1B: 1-bit data transfer
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SD_ConfigWideBusOperation(SD_HandleTypeDef *hsd, uint32_t WideMode)
+{
+  SDIO_InitTypeDef Init;
+  uint32_t errorstate;
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the parameters */
+  assert_param(IS_SDIO_BUS_WIDE(WideMode));
+
+  /* Change State */
+  hsd->State = HAL_SD_STATE_BUSY;
+
+  if(hsd->SdCard.CardType != CARD_SECURED)
+  {
+    if(WideMode == SDIO_BUS_WIDE_8B)
+    {
+      hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE;
+    }
+    else if(WideMode == SDIO_BUS_WIDE_4B)
+    {
+      errorstate = SD_WideBus_Enable(hsd);
+
+      hsd->ErrorCode |= errorstate;
+    }
+    else if(WideMode == SDIO_BUS_WIDE_1B)
+    {
+      errorstate = SD_WideBus_Disable(hsd);
+
+      hsd->ErrorCode |= errorstate;
+    }
+    else
+    {
+      /* WideMode is not a valid argument*/
+      hsd->ErrorCode |= HAL_SD_ERROR_PARAM;
+    }
+  }
+  else
+  {
+    /* MMC Card does not support this feature */
+    hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE;
+  }
+
+  if(hsd->ErrorCode != HAL_SD_ERROR_NONE)
+  {
+    /* Clear all the static flags */
+    __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
+    hsd->State = HAL_SD_STATE_READY;
+    status = HAL_ERROR;
+  }
+  else
+  {
+    /* Configure the SDIO peripheral */
+    Init.ClockEdge           = hsd->Init.ClockEdge;
+    Init.ClockBypass         = hsd->Init.ClockBypass;
+    Init.ClockPowerSave      = hsd->Init.ClockPowerSave;
+    Init.BusWide             = WideMode;
+    Init.HardwareFlowControl = hsd->Init.HardwareFlowControl;
+    Init.ClockDiv            = hsd->Init.ClockDiv;
+    (void)SDIO_Init(hsd->Instance, Init);
+  }
+
+  /* Set Block Size for Card */
+  errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE);
+  if(errorstate != HAL_SD_ERROR_NONE)
+  {
+    /* Clear all the static flags */
+    __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
+    hsd->ErrorCode |= errorstate;
+    status = HAL_ERROR;
+  }
+
+  /* Change State */
+  hsd->State = HAL_SD_STATE_READY;
+
+  return status;
+}
+
+/**
+  * @brief  Gets the current sd card data state.
+  * @param  hsd: pointer to SD handle
+  * @retval Card state
+  */
+HAL_SD_CardStateTypeDef HAL_SD_GetCardState(SD_HandleTypeDef *hsd)
+{
+  uint32_t cardstate;
+  uint32_t errorstate;
+  uint32_t resp1 = 0;
+
+  errorstate = SD_SendStatus(hsd, &resp1);
+  if(errorstate != HAL_SD_ERROR_NONE)
+  {
+    hsd->ErrorCode |= errorstate;
+  }
+
+  cardstate = ((resp1 >> 9U) & 0x0FU);
+
+  return (HAL_SD_CardStateTypeDef)cardstate;
+}
+
+/**
+  * @brief  Abort the current transfer and disable the SD.
+  * @param  hsd: pointer to a SD_HandleTypeDef structure that contains
+  *                the configuration information for SD module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SD_Abort(SD_HandleTypeDef *hsd)
+{
+  HAL_SD_CardStateTypeDef CardState;
+  uint32_t context = hsd->Context;
+
+  /* DIsable All interrupts */
+  __HAL_SD_DISABLE_IT(hsd, SDIO_IT_DATAEND | SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT|\
+                           SDIO_IT_TXUNDERR| SDIO_IT_RXOVERR);
+
+  /* Clear All flags */
+  __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_DATA_FLAGS);
+
+  CLEAR_BIT(hsd->Instance->DCTRL, SDIO_DCTRL_DTEN);
+
+  if ((context & SD_CONTEXT_DMA) != 0U)
+  {
+    /* Disable the SD DMA request */
+    hsd->Instance->DCTRL &= (uint32_t)~((uint32_t)SDIO_DCTRL_DMAEN);
+
+    /* Abort the SD DMA Tx channel */
+    if (((context & SD_CONTEXT_WRITE_SINGLE_BLOCK) != 0U) || ((context & SD_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U))
+    {
+      if(HAL_DMA_Abort(hsd->hdmatx) != HAL_OK)
+      {
+        hsd->ErrorCode |= HAL_SD_ERROR_DMA;
+      }
+    }
+    /* Abort the SD DMA Rx channel */
+    else if (((context & SD_CONTEXT_READ_SINGLE_BLOCK) != 0U) || ((context & SD_CONTEXT_READ_MULTIPLE_BLOCK) != 0U))
+    {
+      if(HAL_DMA_Abort(hsd->hdmarx) != HAL_OK)
+      {
+        hsd->ErrorCode |= HAL_SD_ERROR_DMA;
+      }
+    }
+    else
+    {
+      /* Nothing to do */
+    }
+  }
+
+  hsd->State = HAL_SD_STATE_READY;
+
+  /* Initialize the SD operation */
+  hsd->Context = SD_CONTEXT_NONE;
+
+  CardState = HAL_SD_GetCardState(hsd);
+  if((CardState == HAL_SD_CARD_RECEIVING) || (CardState == HAL_SD_CARD_SENDING))
+  {
+    hsd->ErrorCode = SDMMC_CmdStopTransfer(hsd->Instance);
+  }
+  if(hsd->ErrorCode != HAL_SD_ERROR_NONE)
+  {
+    return HAL_ERROR;
+  }
+  return HAL_OK;
+}
+
+/**
+  * @brief  Abort the current transfer and disable the SD (IT mode).
+  * @param  hsd: pointer to a SD_HandleTypeDef structure that contains
+  *                the configuration information for SD module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SD_Abort_IT(SD_HandleTypeDef *hsd)
+{
+  HAL_SD_CardStateTypeDef CardState;
+  uint32_t context = hsd->Context;
+
+  /* Disable All interrupts */
+  __HAL_SD_DISABLE_IT(hsd, SDIO_IT_DATAEND | SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT|\
+                           SDIO_IT_TXUNDERR| SDIO_IT_RXOVERR);
+
+  CLEAR_BIT(hsd->Instance->DCTRL, SDIO_DCTRL_DTEN);
+
+  if ((context & SD_CONTEXT_DMA) != 0U)
+  {
+    /* Disable the SD DMA request */
+    hsd->Instance->DCTRL &= (uint32_t)~((uint32_t)SDIO_DCTRL_DMAEN);
+
+    /* Abort the SD DMA Tx channel */
+    if (((context & SD_CONTEXT_WRITE_SINGLE_BLOCK) != 0U) || ((context & SD_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U))
+    {
+      hsd->hdmatx->XferAbortCallback = SD_DMATxAbort;
+      if(HAL_DMA_Abort_IT(hsd->hdmatx) != HAL_OK)
+      {
+        hsd->hdmatx = NULL;
+      }
+    }
+    /* Abort the SD DMA Rx channel */
+    else if (((context & SD_CONTEXT_READ_SINGLE_BLOCK) != 0U) || ((context & SD_CONTEXT_READ_MULTIPLE_BLOCK) != 0U))
+    {
+      hsd->hdmarx->XferAbortCallback = SD_DMARxAbort;
+      if(HAL_DMA_Abort_IT(hsd->hdmarx) != HAL_OK)
+      {
+        hsd->hdmarx = NULL;
+      }
+    }
+    else
+    {
+      /* Nothing to do */
+    }
+  }
+  /* No transfer ongoing on both DMA channels*/
+  else
+  {
+    /* Clear All flags */
+    __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_DATA_FLAGS);
+
+    CardState = HAL_SD_GetCardState(hsd);
+    hsd->State = HAL_SD_STATE_READY;
+    hsd->Context = SD_CONTEXT_NONE;
+    if((CardState == HAL_SD_CARD_RECEIVING) || (CardState == HAL_SD_CARD_SENDING))
+    {
+      hsd->ErrorCode = SDMMC_CmdStopTransfer(hsd->Instance);
+    }
+    if(hsd->ErrorCode != HAL_SD_ERROR_NONE)
+    {
+      return HAL_ERROR;
+    }
+    else
+    {
+#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
+      hsd->AbortCpltCallback(hsd);
+#else
+      HAL_SD_AbortCallback(hsd);
+#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
+    }
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private function ----------------------------------------------------------*/
+/** @addtogroup SD_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  DMA SD transmit process complete callback
+  * @param  hdma: DMA handle
+  * @retval None
+  */
+static void SD_DMATransmitCplt(DMA_HandleTypeDef *hdma)
+{
+  SD_HandleTypeDef* hsd = (SD_HandleTypeDef* )(hdma->Parent);
+
+  /* Enable DATAEND Interrupt */
+  __HAL_SD_ENABLE_IT(hsd, (SDIO_IT_DATAEND));
+}
+
+/**
+  * @brief  DMA SD receive process complete callback
+  * @param  hdma: DMA handle
+  * @retval None
+  */
+static void SD_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
+{
+  SD_HandleTypeDef* hsd = (SD_HandleTypeDef* )(hdma->Parent);
+  uint32_t errorstate;
+
+  /* Send stop command in multiblock write */
+  if(hsd->Context == (SD_CONTEXT_READ_MULTIPLE_BLOCK | SD_CONTEXT_DMA))
+  {
+    errorstate = SDMMC_CmdStopTransfer(hsd->Instance);
+    if(errorstate != HAL_SD_ERROR_NONE)
+    {
+      hsd->ErrorCode |= errorstate;
+#if (USE_HAL_SD_REGISTER_CALLBACKS == 1)
+      hsd->ErrorCallback(hsd);
+#else
+      HAL_SD_ErrorCallback(hsd);
+#endif
+    }
+  }
+
+  /* Disable the DMA transfer for transmit request by setting the DMAEN bit
+  in the SD DCTRL register */
+  hsd->Instance->DCTRL &= (uint32_t)~((uint32_t)SDIO_DCTRL_DMAEN);
+
+  /* Clear all the static flags */
+  __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_DATA_FLAGS);
+
+  hsd->State = HAL_SD_STATE_READY;
+  hsd->Context = SD_CONTEXT_NONE;
+
+#if (USE_HAL_SD_REGISTER_CALLBACKS == 1)
+  hsd->RxCpltCallback(hsd);
+#else
+  HAL_SD_RxCpltCallback(hsd);
+#endif
+}
+
+/**
+  * @brief  DMA SD communication error callback
+  * @param  hdma: DMA handle
+  * @retval None
+  */
+static void SD_DMAError(DMA_HandleTypeDef *hdma)
+{
+  SD_HandleTypeDef* hsd = (SD_HandleTypeDef* )(hdma->Parent);
+  HAL_SD_CardStateTypeDef CardState;
+  uint32_t RxErrorCode, TxErrorCode;
+
+  /* if DMA error is FIFO error ignore it */
+  if(HAL_DMA_GetError(hdma) != HAL_DMA_ERROR_FE)
+  {
+    RxErrorCode = hsd->hdmarx->ErrorCode;
+    TxErrorCode = hsd->hdmatx->ErrorCode;  
+    if((RxErrorCode == HAL_DMA_ERROR_TE) || (TxErrorCode == HAL_DMA_ERROR_TE))
+    {
+      /* Clear All flags */
+      __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
+
+      /* Disable All interrupts */
+      __HAL_SD_DISABLE_IT(hsd, SDIO_IT_DATAEND | SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT|\
+        SDIO_IT_TXUNDERR| SDIO_IT_RXOVERR);
+
+      hsd->ErrorCode |= HAL_SD_ERROR_DMA;
+      CardState = HAL_SD_GetCardState(hsd);
+      if((CardState == HAL_SD_CARD_RECEIVING) || (CardState == HAL_SD_CARD_SENDING))
+      {
+        hsd->ErrorCode |= SDMMC_CmdStopTransfer(hsd->Instance);
+      }
+
+      hsd->State= HAL_SD_STATE_READY;
+      hsd->Context = SD_CONTEXT_NONE;
+    }
+
+#if (USE_HAL_SD_REGISTER_CALLBACKS == 1)
+    hsd->ErrorCallback(hsd);
+#else
+    HAL_SD_ErrorCallback(hsd);
+#endif
+  }
+}
+
+/**
+  * @brief  DMA SD Tx Abort callback
+  * @param  hdma: DMA handle
+  * @retval None
+  */
+static void SD_DMATxAbort(DMA_HandleTypeDef *hdma)
+{
+  SD_HandleTypeDef* hsd = (SD_HandleTypeDef* )(hdma->Parent);
+  HAL_SD_CardStateTypeDef CardState;
+
+  /* Clear All flags */
+  __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_DATA_FLAGS);
+
+  CardState = HAL_SD_GetCardState(hsd);
+  hsd->State = HAL_SD_STATE_READY;
+  hsd->Context = SD_CONTEXT_NONE;
+  if((CardState == HAL_SD_CARD_RECEIVING) || (CardState == HAL_SD_CARD_SENDING))
+  {
+    hsd->ErrorCode |= SDMMC_CmdStopTransfer(hsd->Instance);
+  }
+
+  if(hsd->ErrorCode == HAL_SD_ERROR_NONE)
+  {
+#if (USE_HAL_SD_REGISTER_CALLBACKS == 1)
+    hsd->AbortCpltCallback(hsd);
+#else
+    HAL_SD_AbortCallback(hsd);
+#endif
+  }
+  else
+  {
+#if (USE_HAL_SD_REGISTER_CALLBACKS == 1)
+    hsd->ErrorCallback(hsd);
+#else
+    HAL_SD_ErrorCallback(hsd);
+#endif
+  }
+}
+
+/**
+  * @brief  DMA SD Rx Abort callback
+  * @param  hdma: DMA handle
+  * @retval None
+  */
+static void SD_DMARxAbort(DMA_HandleTypeDef *hdma)
+{
+  SD_HandleTypeDef* hsd = (SD_HandleTypeDef* )(hdma->Parent);
+  HAL_SD_CardStateTypeDef CardState;
+
+  /* Clear All flags */
+  __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_DATA_FLAGS);
+
+  CardState = HAL_SD_GetCardState(hsd);
+  hsd->State = HAL_SD_STATE_READY;
+  hsd->Context = SD_CONTEXT_NONE;
+  if((CardState == HAL_SD_CARD_RECEIVING) || (CardState == HAL_SD_CARD_SENDING))
+  {
+    hsd->ErrorCode |= SDMMC_CmdStopTransfer(hsd->Instance);
+  }
+
+  if(hsd->ErrorCode == HAL_SD_ERROR_NONE)
+  {
+#if (USE_HAL_SD_REGISTER_CALLBACKS == 1)
+    hsd->AbortCpltCallback(hsd);
+#else
+    HAL_SD_AbortCallback(hsd);
+#endif
+  }
+  else
+  {
+#if (USE_HAL_SD_REGISTER_CALLBACKS == 1)
+    hsd->ErrorCallback(hsd);
+#else
+    HAL_SD_ErrorCallback(hsd);
+#endif
+  }
+}
+
+/**
+  * @brief  Initializes the sd card.
+  * @param  hsd: Pointer to SD handle
+  * @retval SD Card error state
+  */
+static uint32_t SD_InitCard(SD_HandleTypeDef *hsd)
+{
+  HAL_SD_CardCSDTypeDef CSD;
+  uint32_t errorstate;
+  uint16_t sd_rca = 1U;
+
+  /* Check the power State */
+  if(SDIO_GetPowerState(hsd->Instance) == 0U)
+  {
+    /* Power off */
+    return HAL_SD_ERROR_REQUEST_NOT_APPLICABLE;
+  }
+
+  if(hsd->SdCard.CardType != CARD_SECURED)
+  {
+    /* Send CMD2 ALL_SEND_CID */
+    errorstate = SDMMC_CmdSendCID(hsd->Instance);
+    if(errorstate != HAL_SD_ERROR_NONE)
+    {
+      return errorstate;
+    }
+    else
+    {
+      /* Get Card identification number data */
+      hsd->CID[0U] = SDIO_GetResponse(hsd->Instance, SDIO_RESP1);
+      hsd->CID[1U] = SDIO_GetResponse(hsd->Instance, SDIO_RESP2);
+      hsd->CID[2U] = SDIO_GetResponse(hsd->Instance, SDIO_RESP3);
+      hsd->CID[3U] = SDIO_GetResponse(hsd->Instance, SDIO_RESP4);
+    }
+  }
+
+  if(hsd->SdCard.CardType != CARD_SECURED)
+  {
+    /* Send CMD3 SET_REL_ADDR with argument 0 */
+    /* SD Card publishes its RCA. */
+    errorstate = SDMMC_CmdSetRelAdd(hsd->Instance, &sd_rca);
+    if(errorstate != HAL_SD_ERROR_NONE)
+    {
+      return errorstate;
+    }
+  }
+  if(hsd->SdCard.CardType != CARD_SECURED)
+  {
+    /* Get the SD card RCA */
+    hsd->SdCard.RelCardAdd = sd_rca;
+
+    /* Send CMD9 SEND_CSD with argument as card's RCA */
+    errorstate = SDMMC_CmdSendCSD(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16U));
+    if(errorstate != HAL_SD_ERROR_NONE)
+    {
+      return errorstate;
+    }
+    else
+    {
+      /* Get Card Specific Data */
+      hsd->CSD[0U] = SDIO_GetResponse(hsd->Instance, SDIO_RESP1);
+      hsd->CSD[1U] = SDIO_GetResponse(hsd->Instance, SDIO_RESP2);
+      hsd->CSD[2U] = SDIO_GetResponse(hsd->Instance, SDIO_RESP3);
+      hsd->CSD[3U] = SDIO_GetResponse(hsd->Instance, SDIO_RESP4);
+    }
+  }
+
+  /* Get the Card Class */
+  hsd->SdCard.Class = (SDIO_GetResponse(hsd->Instance, SDIO_RESP2) >> 20U);
+
+  /* Get CSD parameters */
+  if (HAL_SD_GetCardCSD(hsd, &CSD) != HAL_OK)
+  {
+    return HAL_SD_ERROR_UNSUPPORTED_FEATURE;
+  }
+
+  /* Select the Card */
+  errorstate = SDMMC_CmdSelDesel(hsd->Instance, (uint32_t)(((uint32_t)hsd->SdCard.RelCardAdd) << 16U));
+  if(errorstate != HAL_SD_ERROR_NONE)
+  {
+    return errorstate;
+  }
+
+  /* Configure SDIO peripheral interface */
+  (void)SDIO_Init(hsd->Instance, hsd->Init);
+
+  /* All cards are initialized */
+  return HAL_SD_ERROR_NONE;
+}
+
+/**
+  * @brief  Enquires cards about their operating voltage and configures clock
+  *         controls and stores SD information that will be needed in future
+  *         in the SD handle.
+  * @param  hsd: Pointer to SD handle
+  * @retval error state
+  */
+static uint32_t SD_PowerON(SD_HandleTypeDef *hsd)
+{
+  __IO uint32_t count = 0U;
+  uint32_t response = 0U, validvoltage = 0U;
+  uint32_t errorstate;
+
+  /* CMD0: GO_IDLE_STATE */
+  errorstate = SDMMC_CmdGoIdleState(hsd->Instance);
+  if(errorstate != HAL_SD_ERROR_NONE)
+  {
+    return errorstate;
+  }
+
+  /* CMD8: SEND_IF_COND: Command available only on V2.0 cards */
+  errorstate = SDMMC_CmdOperCond(hsd->Instance);
+  if(errorstate != HAL_SD_ERROR_NONE)
+  {
+    hsd->SdCard.CardVersion = CARD_V1_X;
+    /* CMD0: GO_IDLE_STATE */
+    errorstate = SDMMC_CmdGoIdleState(hsd->Instance);
+    if(errorstate != HAL_SD_ERROR_NONE)
+    {
+      return errorstate;
+    }
+
+  }
+  else
+  {
+    hsd->SdCard.CardVersion = CARD_V2_X;
+  }
+
+  if( hsd->SdCard.CardVersion == CARD_V2_X)
+  {
+    /* SEND CMD55 APP_CMD with RCA as 0 */
+    errorstate = SDMMC_CmdAppCommand(hsd->Instance, 0);
+    if(errorstate != HAL_SD_ERROR_NONE)
+    {
+      return HAL_SD_ERROR_UNSUPPORTED_FEATURE;
+    }
+  }
+  /* SD CARD */
+  /* Send ACMD41 SD_APP_OP_COND with Argument 0x80100000 */
+  while((count < SDMMC_MAX_VOLT_TRIAL) && (validvoltage == 0U))
+  {
+    /* SEND CMD55 APP_CMD with RCA as 0 */
+    errorstate = SDMMC_CmdAppCommand(hsd->Instance, 0);
+    if(errorstate != HAL_SD_ERROR_NONE)
+    {
+      return errorstate;
+    }
+
+    /* Send CMD41 */
+    errorstate = SDMMC_CmdAppOperCommand(hsd->Instance, SDMMC_VOLTAGE_WINDOW_SD | SDMMC_HIGH_CAPACITY | SD_SWITCH_1_8V_CAPACITY);
+    if(errorstate != HAL_SD_ERROR_NONE)
+    {
+      return HAL_SD_ERROR_UNSUPPORTED_FEATURE;
+    }
+
+    /* Get command response */
+    response = SDIO_GetResponse(hsd->Instance, SDIO_RESP1);
+
+    /* Get operating voltage*/
+    validvoltage = (((response >> 31U) == 1U) ? 1U : 0U);
+
+    count++;
+  }
+
+  if(count >= SDMMC_MAX_VOLT_TRIAL)
+  {
+    return HAL_SD_ERROR_INVALID_VOLTRANGE;
+  }
+
+  if((response & SDMMC_HIGH_CAPACITY) == SDMMC_HIGH_CAPACITY) /* (response &= SD_HIGH_CAPACITY) */
+  {
+    hsd->SdCard.CardType = CARD_SDHC_SDXC;
+  }
+  else
+  {
+    hsd->SdCard.CardType = CARD_SDSC;
+  }
+
+
+  return HAL_SD_ERROR_NONE;
+}
+
+/**
+  * @brief  Turns the SDIO output signals off.
+  * @param  hsd: Pointer to SD handle
+  * @retval None
+  */
+static void SD_PowerOFF(SD_HandleTypeDef *hsd)
+{
+  /* Set Power State to OFF */
+  (void)SDIO_PowerState_OFF(hsd->Instance);
+}
+
+/**
+  * @brief  Send Status info command.
+  * @param  hsd: pointer to SD handle
+  * @param  pSDstatus: Pointer to the buffer that will contain the SD card status
+  *         SD Status register)
+  * @retval error state
+  */
+static uint32_t SD_SendSDStatus(SD_HandleTypeDef *hsd, uint32_t *pSDstatus)
+{
+  SDIO_DataInitTypeDef config;
+  uint32_t errorstate;
+  uint32_t tickstart = HAL_GetTick();
+  uint32_t count;
+  uint32_t *pData = pSDstatus;
+
+  /* Check SD response */
+  if((SDIO_GetResponse(hsd->Instance, SDIO_RESP1) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED)
+  {
+    return HAL_SD_ERROR_LOCK_UNLOCK_FAILED;
+  }
+
+  /* Set block size for card if it is not equal to current block size for card */
+  errorstate = SDMMC_CmdBlockLength(hsd->Instance, 64U);
+  if(errorstate != HAL_SD_ERROR_NONE)
+  {
+    hsd->ErrorCode |= HAL_SD_ERROR_NONE;
+    return errorstate;
+  }
+
+  /* Send CMD55 */
+  errorstate = SDMMC_CmdAppCommand(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16U));
+  if(errorstate != HAL_SD_ERROR_NONE)
+  {
+    hsd->ErrorCode |= HAL_SD_ERROR_NONE;
+    return errorstate;
+  }
+
+  /* Configure the SD DPSM (Data Path State Machine) */
+  config.DataTimeOut   = SDMMC_DATATIMEOUT;
+  config.DataLength    = 64U;
+  config.DataBlockSize = SDIO_DATABLOCK_SIZE_64B;
+  config.TransferDir   = SDIO_TRANSFER_DIR_TO_SDIO;
+  config.TransferMode  = SDIO_TRANSFER_MODE_BLOCK;
+  config.DPSM          = SDIO_DPSM_ENABLE;
+  (void)SDIO_ConfigData(hsd->Instance, &config);
+
+  /* Send ACMD13 (SD_APP_STAUS)  with argument as card's RCA */
+  errorstate = SDMMC_CmdStatusRegister(hsd->Instance);
+  if(errorstate != HAL_SD_ERROR_NONE)
+  {
+    hsd->ErrorCode |= HAL_SD_ERROR_NONE;
+    return errorstate;
+  }
+
+  /* Get status data */
+  while(!__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_RXOVERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DBCKEND))
+  {
+    if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_RXFIFOHF))
+    {
+      for(count = 0U; count < 8U; count++)
+      {
+        *pData = SDIO_ReadFIFO(hsd->Instance);
+        pData++;
+      }
+    }
+
+    if((HAL_GetTick() - tickstart) >=  SDMMC_DATATIMEOUT)
+    {
+      return HAL_SD_ERROR_TIMEOUT;
+    }
+  }
+
+  if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_DTIMEOUT))
+  {
+    return HAL_SD_ERROR_DATA_TIMEOUT;
+  }
+  else if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_DCRCFAIL))
+  {
+    return HAL_SD_ERROR_DATA_CRC_FAIL;
+  }
+  else if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_RXOVERR))
+  {
+    return HAL_SD_ERROR_RX_OVERRUN;
+  }
+  else
+  {
+    /* Nothing to do */
+  }
+
+  while ((__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_RXDAVL)))
+  {
+    *pData = SDIO_ReadFIFO(hsd->Instance);
+    pData++;
+
+    if((HAL_GetTick() - tickstart) >=  SDMMC_DATATIMEOUT)
+    {
+      return HAL_SD_ERROR_TIMEOUT;
+    }
+  }
+
+  /* Clear all the static status flags*/
+  __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_DATA_FLAGS);
+
+  return HAL_SD_ERROR_NONE;
+}
+
+/**
+  * @brief  Returns the current card's status.
+  * @param  hsd: Pointer to SD handle
+  * @param  pCardStatus: pointer to the buffer that will contain the SD card
+  *         status (Card Status register)
+  * @retval error state
+  */
+static uint32_t SD_SendStatus(SD_HandleTypeDef *hsd, uint32_t *pCardStatus)
+{
+  uint32_t errorstate;
+
+  if(pCardStatus == NULL)
+  {
+    return HAL_SD_ERROR_PARAM;
+  }
+
+  /* Send Status command */
+  errorstate = SDMMC_CmdSendStatus(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16U));
+  if(errorstate != HAL_SD_ERROR_NONE)
+  {
+    return errorstate;
+  }
+
+  /* Get SD card status */
+  *pCardStatus = SDIO_GetResponse(hsd->Instance, SDIO_RESP1);
+
+  return HAL_SD_ERROR_NONE;
+}
+
+/**
+  * @brief  Enables the SDIO wide bus mode.
+  * @param  hsd: pointer to SD handle
+  * @retval error state
+  */
+static uint32_t SD_WideBus_Enable(SD_HandleTypeDef *hsd)
+{
+  uint32_t scr[2U] = {0U, 0U};
+  uint32_t errorstate;
+
+  if((SDIO_GetResponse(hsd->Instance, SDIO_RESP1) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED)
+  {
+    return HAL_SD_ERROR_LOCK_UNLOCK_FAILED;
+  }
+
+  /* Get SCR Register */
+  errorstate = SD_FindSCR(hsd, scr);
+  if(errorstate != HAL_SD_ERROR_NONE)
+  {
+    return errorstate;
+  }
+
+  /* If requested card supports wide bus operation */
+  if((scr[1U] & SDMMC_WIDE_BUS_SUPPORT) != SDMMC_ALLZERO)
+  {
+    /* Send CMD55 APP_CMD with argument as card's RCA.*/
+    errorstate = SDMMC_CmdAppCommand(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16U));
+    if(errorstate != HAL_SD_ERROR_NONE)
+    {
+      return errorstate;
+    }
+
+    /* Send ACMD6 APP_CMD with argument as 2 for wide bus mode */
+    errorstate = SDMMC_CmdBusWidth(hsd->Instance, 2U);
+    if(errorstate != HAL_SD_ERROR_NONE)
+    {
+      return errorstate;
+    }
+
+    return HAL_SD_ERROR_NONE;
+  }
+  else
+  {
+    return HAL_SD_ERROR_REQUEST_NOT_APPLICABLE;
+  }
+}
+
+/**
+  * @brief  Disables the SDIO wide bus mode.
+  * @param  hsd: Pointer to SD handle
+  * @retval error state
+  */
+static uint32_t SD_WideBus_Disable(SD_HandleTypeDef *hsd)
+{
+  uint32_t scr[2U] = {0U, 0U};
+  uint32_t errorstate;
+
+  if((SDIO_GetResponse(hsd->Instance, SDIO_RESP1) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED)
+  {
+    return HAL_SD_ERROR_LOCK_UNLOCK_FAILED;
+  }
+
+  /* Get SCR Register */
+  errorstate = SD_FindSCR(hsd, scr);
+  if(errorstate != HAL_SD_ERROR_NONE)
+  {
+    return errorstate;
+  }
+
+  /* If requested card supports 1 bit mode operation */
+  if((scr[1U] & SDMMC_SINGLE_BUS_SUPPORT) != SDMMC_ALLZERO)
+  {
+    /* Send CMD55 APP_CMD with argument as card's RCA */
+    errorstate = SDMMC_CmdAppCommand(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16U));
+    if(errorstate != HAL_SD_ERROR_NONE)
+    {
+      return errorstate;
+    }
+
+    /* Send ACMD6 APP_CMD with argument as 0 for single bus mode */
+    errorstate = SDMMC_CmdBusWidth(hsd->Instance, 0U);
+    if(errorstate != HAL_SD_ERROR_NONE)
+    {
+      return errorstate;
+    }
+
+    return HAL_SD_ERROR_NONE;
+  }
+  else
+  {
+    return HAL_SD_ERROR_REQUEST_NOT_APPLICABLE;
+  }
+}
+
+
+/**
+  * @brief  Finds the SD card SCR register value.
+  * @param  hsd: Pointer to SD handle
+  * @param  pSCR: pointer to the buffer that will contain the SCR value
+  * @retval error state
+  */
+static uint32_t SD_FindSCR(SD_HandleTypeDef *hsd, uint32_t *pSCR)
+{
+  SDIO_DataInitTypeDef config;
+  uint32_t errorstate;
+  uint32_t tickstart = HAL_GetTick();
+  uint32_t index = 0U;
+  uint32_t tempscr[2U] = {0U, 0U};
+  uint32_t *scr = pSCR;
+
+  /* Set Block Size To 8 Bytes */
+  errorstate = SDMMC_CmdBlockLength(hsd->Instance, 8U);
+  if(errorstate != HAL_SD_ERROR_NONE)
+  {
+    return errorstate;
+  }
+
+  /* Send CMD55 APP_CMD with argument as card's RCA */
+  errorstate = SDMMC_CmdAppCommand(hsd->Instance, (uint32_t)((hsd->SdCard.RelCardAdd) << 16U));
+  if(errorstate != HAL_SD_ERROR_NONE)
+  {
+    return errorstate;
+  }
+
+  config.DataTimeOut   = SDMMC_DATATIMEOUT;
+  config.DataLength    = 8U;
+  config.DataBlockSize = SDIO_DATABLOCK_SIZE_8B;
+  config.TransferDir   = SDIO_TRANSFER_DIR_TO_SDIO;
+  config.TransferMode  = SDIO_TRANSFER_MODE_BLOCK;
+  config.DPSM          = SDIO_DPSM_ENABLE;
+  (void)SDIO_ConfigData(hsd->Instance, &config);
+
+  /* Send ACMD51 SD_APP_SEND_SCR with argument as 0 */
+  errorstate = SDMMC_CmdSendSCR(hsd->Instance);
+  if(errorstate != HAL_SD_ERROR_NONE)
+  {
+    return errorstate;
+  }
+
+  while(!__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_RXOVERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT))
+  {
+    if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_RXDAVL))
+    {
+      *(tempscr + index) = SDIO_ReadFIFO(hsd->Instance);
+      index++;
+    }
+    else if(!__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_RXACT))
+    {
+      break;
+    }
+
+    if((HAL_GetTick() - tickstart) >=  SDMMC_DATATIMEOUT)
+    {
+      return HAL_SD_ERROR_TIMEOUT;
+    }
+  }
+
+  if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_DTIMEOUT))
+  {
+    __HAL_SD_CLEAR_FLAG(hsd, SDIO_FLAG_DTIMEOUT);
+
+    return HAL_SD_ERROR_DATA_TIMEOUT;
+  }
+  else if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_DCRCFAIL))
+  {
+    __HAL_SD_CLEAR_FLAG(hsd, SDIO_FLAG_DCRCFAIL);
+
+    return HAL_SD_ERROR_DATA_CRC_FAIL;
+  }
+  else if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_RXOVERR))
+  {
+    __HAL_SD_CLEAR_FLAG(hsd, SDIO_FLAG_RXOVERR);
+
+    return HAL_SD_ERROR_RX_OVERRUN;
+  }
+  else
+  {
+    /* No error flag set */
+    /* Clear all the static flags */
+    __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_DATA_FLAGS);
+
+    *scr = (((tempscr[1] & SDMMC_0TO7BITS) << 24)  | ((tempscr[1] & SDMMC_8TO15BITS) << 8) |\
+            ((tempscr[1] & SDMMC_16TO23BITS) >> 8) | ((tempscr[1] & SDMMC_24TO31BITS) >> 24));
+    scr++;
+    *scr = (((tempscr[0] & SDMMC_0TO7BITS) << 24)  | ((tempscr[0] & SDMMC_8TO15BITS) << 8) |\
+            ((tempscr[0] & SDMMC_16TO23BITS) >> 8) | ((tempscr[0] & SDMMC_24TO31BITS) >> 24));
+
+  }
+
+  return HAL_SD_ERROR_NONE;
+}
+
+/**
+  * @brief  Wrap up reading in non-blocking mode.
+  * @param  hsd: pointer to a SD_HandleTypeDef structure that contains
+  *              the configuration information.
+  * @retval None
+  */
+static void SD_Read_IT(SD_HandleTypeDef *hsd)
+{
+  uint32_t count, data, dataremaining;
+  uint8_t* tmp;
+
+  tmp = hsd->pRxBuffPtr;
+  dataremaining = hsd->RxXferSize;
+
+  if (dataremaining > 0U)
+  {
+    /* Read data from SDIO Rx FIFO */
+    for(count = 0U; count < 8U; count++)
+    {
+      data = SDIO_ReadFIFO(hsd->Instance);
+      *tmp = (uint8_t)(data & 0xFFU);
+      tmp++;
+      dataremaining--;
+      *tmp = (uint8_t)((data >> 8U) & 0xFFU);
+      tmp++;
+      dataremaining--;
+      *tmp = (uint8_t)((data >> 16U) & 0xFFU);
+      tmp++;
+      dataremaining--;
+      *tmp = (uint8_t)((data >> 24U) & 0xFFU);
+      tmp++;
+      dataremaining--;
+    }
+
+    hsd->pRxBuffPtr = tmp;
+    hsd->RxXferSize = dataremaining;
+  }
+}
+
+/**
+  * @brief  Wrap up writing in non-blocking mode.
+  * @param  hsd: pointer to a SD_HandleTypeDef structure that contains
+  *              the configuration information.
+  * @retval None
+  */
+static void SD_Write_IT(SD_HandleTypeDef *hsd)
+{
+  uint32_t count, data, dataremaining;
+  uint8_t* tmp;
+
+  tmp = hsd->pTxBuffPtr;
+  dataremaining = hsd->TxXferSize;
+
+  if (dataremaining > 0U)
+  {
+    /* Write data to SDIO Tx FIFO */
+    for(count = 0U; count < 8U; count++)
+    {
+      data = (uint32_t)(*tmp);
+      tmp++;
+      dataremaining--;
+      data |= ((uint32_t)(*tmp) << 8U);
+      tmp++;
+      dataremaining--;
+      data |= ((uint32_t)(*tmp) << 16U);
+      tmp++;
+      dataremaining--;
+      data |= ((uint32_t)(*tmp) << 24U);
+      tmp++;
+      dataremaining--;
+      (void)SDIO_WriteFIFO(hsd->Instance, &data);
+    }
+
+    hsd->pTxBuffPtr = tmp;
+    hsd->TxXferSize = dataremaining;
+  }
+}
+
+/**
+  * @}
+  */
+
+#endif /* HAL_SD_MODULE_ENABLED */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* SDIO */
diff --git a/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sdram.c b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sdram.c
new file mode 100644
index 0000000..91cc543
--- /dev/null
+++ b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sdram.c
@@ -0,0 +1,1308 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hal_sdram.c
+  * @author  MCD Application Team
+  * @brief   SDRAM HAL module driver.
+  *          This file provides a generic firmware to drive SDRAM memories mounted
+  *          as external device.
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2016 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  @verbatim
+  ==============================================================================
+                       ##### How to use this driver #####
+  ==============================================================================
+  [..]
+    This driver is a generic layered driver which contains a set of APIs used to
+    control SDRAM memories. It uses the FMC layer functions to interface
+    with SDRAM devices.
+    The following sequence should be followed to configure the FMC to interface
+    with SDRAM memories:
+
+   (#) Declare a SDRAM_HandleTypeDef handle structure, for example:
+          SDRAM_HandleTypeDef  hsdram
+
+       (++) Fill the SDRAM_HandleTypeDef handle "Init" field with the allowed
+            values of the structure member.
+
+       (++) Fill the SDRAM_HandleTypeDef handle "Instance" field with a predefined
+            base register instance for NOR or SDRAM device
+
+   (#) Declare a FMC_SDRAM_TimingTypeDef structure; for example:
+          FMC_SDRAM_TimingTypeDef  Timing;
+      and fill its fields with the allowed values of the structure member.
+
+   (#) Initialize the SDRAM Controller by calling the function HAL_SDRAM_Init(). This function
+       performs the following sequence:
+
+       (##) MSP hardware layer configuration using the function HAL_SDRAM_MspInit()
+       (##) Control register configuration using the FMC SDRAM interface function
+            FMC_SDRAM_Init()
+       (##) Timing register configuration using the FMC SDRAM interface function
+            FMC_SDRAM_Timing_Init()
+       (##) Program the SDRAM external device by applying its initialization sequence
+            according to the device plugged in your hardware. This step is mandatory
+            for accessing the SDRAM device.
+
+   (#) At this stage you can perform read/write accesses from/to the memory connected
+       to the SDRAM Bank. You can perform either polling or DMA transfer using the
+       following APIs:
+       (++) HAL_SDRAM_Read()/HAL_SDRAM_Write() for polling read/write access
+       (++) HAL_SDRAM_Read_DMA()/HAL_SDRAM_Write_DMA() for DMA read/write transfer
+
+   (#) You can also control the SDRAM device by calling the control APIs HAL_SDRAM_WriteOperation_Enable()/
+       HAL_SDRAM_WriteOperation_Disable() to respectively enable/disable the SDRAM write operation or
+       the function HAL_SDRAM_SendCommand() to send a specified command to the SDRAM
+       device. The command to be sent must be configured with the FMC_SDRAM_CommandTypeDef
+       structure.
+
+   (#) You can continuously monitor the SDRAM device HAL state by calling the function
+       HAL_SDRAM_GetState()
+
+   *** Callback registration ***
+    =============================================
+    [..]
+      The compilation define  USE_HAL_SDRAM_REGISTER_CALLBACKS when set to 1
+      allows the user to configure dynamically the driver callbacks.
+
+      Use Functions HAL_SDRAM_RegisterCallback() to register a user callback,
+      it allows to register following callbacks:
+        (+) MspInitCallback    : SDRAM MspInit.
+        (+) MspDeInitCallback  : SDRAM MspDeInit.
+      This function takes as parameters the HAL peripheral handle, the Callback ID
+      and a pointer to the user callback function.
+
+      Use function HAL_SDRAM_UnRegisterCallback() to reset a callback to the default
+      weak (surcharged) function. It allows to reset following callbacks:
+        (+) MspInitCallback    : SDRAM MspInit.
+        (+) MspDeInitCallback  : SDRAM MspDeInit.
+      This function) takes as parameters the HAL peripheral handle and the Callback ID.
+
+      By default, after the HAL_SDRAM_Init and if the state is HAL_SDRAM_STATE_RESET
+      all callbacks are reset to the corresponding legacy weak (surcharged) functions.
+      Exception done for MspInit and MspDeInit callbacks that are respectively
+      reset to the legacy weak (surcharged) functions in the HAL_SDRAM_Init
+      and  HAL_SDRAM_DeInit only when these callbacks are null (not registered beforehand).
+      If not, MspInit or MspDeInit are not null, the HAL_SDRAM_Init and HAL_SDRAM_DeInit
+      keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
+
+      Callbacks can be registered/unregistered in READY state only.
+      Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
+      in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
+      during the Init/DeInit.
+      In that case first register the MspInit/MspDeInit user callbacks
+      using HAL_SDRAM_RegisterCallback before calling HAL_SDRAM_DeInit
+      or HAL_SDRAM_Init function.
+
+      When The compilation define USE_HAL_SDRAM_REGISTER_CALLBACKS is set to 0 or
+      not defined, the callback registering feature is not available
+      and weak (surcharged) callbacks are used.
+
+  @endverbatim
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal.h"
+
+#if defined(FMC_Bank5_6)
+
+/** @addtogroup STM32F4xx_HAL_Driver
+  * @{
+  */
+
+#ifdef HAL_SDRAM_MODULE_ENABLED
+
+/** @defgroup SDRAM SDRAM
+  * @brief SDRAM driver modules
+  * @{
+  */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+static void SDRAM_DMACplt(DMA_HandleTypeDef *hdma);
+static void SDRAM_DMACpltProt(DMA_HandleTypeDef *hdma);
+static void SDRAM_DMAError(DMA_HandleTypeDef *hdma);
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup SDRAM_Exported_Functions SDRAM Exported Functions
+  * @{
+  */
+
+/** @defgroup SDRAM_Exported_Functions_Group1 Initialization and de-initialization functions
+  * @brief    Initialization and Configuration functions
+  *
+  @verbatim
+  ==============================================================================
+           ##### SDRAM Initialization and de_initialization functions #####
+  ==============================================================================
+  [..]
+    This section provides functions allowing to initialize/de-initialize
+    the SDRAM memory
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Performs the SDRAM device initialization sequence.
+  * @param  hsdram pointer to a SDRAM_HandleTypeDef structure that contains
+  *                the configuration information for SDRAM module.
+  * @param  Timing Pointer to SDRAM control timing structure
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SDRAM_Init(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_TimingTypeDef *Timing)
+{
+  /* Check the SDRAM handle parameter */
+  if (hsdram == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  if (hsdram->State == HAL_SDRAM_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    hsdram->Lock = HAL_UNLOCKED;
+#if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1)
+    if (hsdram->MspInitCallback == NULL)
+    {
+      hsdram->MspInitCallback = HAL_SDRAM_MspInit;
+    }
+    hsdram->RefreshErrorCallback = HAL_SDRAM_RefreshErrorCallback;
+    hsdram->DmaXferCpltCallback = HAL_SDRAM_DMA_XferCpltCallback;
+    hsdram->DmaXferErrorCallback = HAL_SDRAM_DMA_XferErrorCallback;
+
+    /* Init the low level hardware */
+    hsdram->MspInitCallback(hsdram);
+#else
+    /* Initialize the low level hardware (MSP) */
+    HAL_SDRAM_MspInit(hsdram);
+#endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */
+  }
+
+  /* Initialize the SDRAM controller state */
+  hsdram->State = HAL_SDRAM_STATE_BUSY;
+
+  /* Initialize SDRAM control Interface */
+  (void)FMC_SDRAM_Init(hsdram->Instance, &(hsdram->Init));
+
+  /* Initialize SDRAM timing Interface */
+  (void)FMC_SDRAM_Timing_Init(hsdram->Instance, Timing, hsdram->Init.SDBank);
+  /* Update the SDRAM controller state */
+  hsdram->State = HAL_SDRAM_STATE_READY;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Perform the SDRAM device initialization sequence.
+  * @param  hsdram pointer to a SDRAM_HandleTypeDef structure that contains
+  *                the configuration information for SDRAM module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SDRAM_DeInit(SDRAM_HandleTypeDef *hsdram)
+{
+#if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1)
+  if (hsdram->MspDeInitCallback == NULL)
+  {
+    hsdram->MspDeInitCallback = HAL_SDRAM_MspDeInit;
+  }
+
+  /* DeInit the low level hardware */
+  hsdram->MspDeInitCallback(hsdram);
+#else
+  /* Initialize the low level hardware (MSP) */
+  HAL_SDRAM_MspDeInit(hsdram);
+#endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */
+
+  /* Configure the SDRAM registers with their reset values */
+  (void)FMC_SDRAM_DeInit(hsdram->Instance, hsdram->Init.SDBank);
+
+  /* Reset the SDRAM controller state */
+  hsdram->State = HAL_SDRAM_STATE_RESET;
+
+  /* Release Lock */
+  __HAL_UNLOCK(hsdram);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  SDRAM MSP Init.
+  * @param  hsdram pointer to a SDRAM_HandleTypeDef structure that contains
+  *                the configuration information for SDRAM module.
+  * @retval None
+  */
+__weak void HAL_SDRAM_MspInit(SDRAM_HandleTypeDef *hsdram)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hsdram);
+
+  /* NOTE: This function Should not be modified, when the callback is needed,
+            the HAL_SDRAM_MspInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  SDRAM MSP DeInit.
+  * @param  hsdram pointer to a SDRAM_HandleTypeDef structure that contains
+  *                the configuration information for SDRAM module.
+  * @retval None
+  */
+__weak void HAL_SDRAM_MspDeInit(SDRAM_HandleTypeDef *hsdram)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hsdram);
+
+  /* NOTE: This function Should not be modified, when the callback is needed,
+            the HAL_SDRAM_MspDeInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  This function handles SDRAM refresh error interrupt request.
+  * @param  hsdram pointer to a SDRAM_HandleTypeDef structure that contains
+  *                the configuration information for SDRAM module.
+  * @retval HAL status
+  */
+void HAL_SDRAM_IRQHandler(SDRAM_HandleTypeDef *hsdram)
+{
+  /* Check SDRAM interrupt Rising edge flag */
+  if (__FMC_SDRAM_GET_FLAG(hsdram->Instance, FMC_SDRAM_FLAG_REFRESH_IT))
+  {
+    /* SDRAM refresh error interrupt callback */
+#if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1)
+    hsdram->RefreshErrorCallback(hsdram);
+#else
+    HAL_SDRAM_RefreshErrorCallback(hsdram);
+#endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */
+
+    /* Clear SDRAM refresh error interrupt pending bit */
+    __FMC_SDRAM_CLEAR_FLAG(hsdram->Instance, FMC_SDRAM_FLAG_REFRESH_ERROR);
+  }
+}
+
+/**
+  * @brief  SDRAM Refresh error callback.
+  * @param  hsdram pointer to a SDRAM_HandleTypeDef structure that contains
+  *                the configuration information for SDRAM module.
+  * @retval None
+  */
+__weak void HAL_SDRAM_RefreshErrorCallback(SDRAM_HandleTypeDef *hsdram)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hsdram);
+
+  /* NOTE: This function Should not be modified, when the callback is needed,
+            the HAL_SDRAM_RefreshErrorCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  DMA transfer complete callback.
+  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
+  *                the configuration information for the specified DMA module.
+  * @retval None
+  */
+__weak void HAL_SDRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hdma);
+
+  /* NOTE: This function Should not be modified, when the callback is needed,
+            the HAL_SDRAM_DMA_XferCpltCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  DMA transfer complete error callback.
+  * @param  hdma DMA handle
+  * @retval None
+  */
+__weak void HAL_SDRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hdma);
+
+  /* NOTE: This function Should not be modified, when the callback is needed,
+            the HAL_SDRAM_DMA_XferErrorCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup SDRAM_Exported_Functions_Group2 Input and Output functions
+  * @brief    Input Output and memory control functions
+  *
+  @verbatim
+  ==============================================================================
+                    ##### SDRAM Input and Output functions #####
+  ==============================================================================
+  [..]
+    This section provides functions allowing to use and control the SDRAM memory
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Reads 8-bit data buffer from the SDRAM memory.
+  * @param  hsdram pointer to a SDRAM_HandleTypeDef structure that contains
+  *                the configuration information for SDRAM module.
+  * @param  pAddress Pointer to read start address
+  * @param  pDstBuffer Pointer to destination buffer
+  * @param  BufferSize Size of the buffer to read from memory
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SDRAM_Read_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pDstBuffer,
+                                    uint32_t BufferSize)
+{
+  uint32_t size;
+  __IO uint8_t *pSdramAddress = (uint8_t *)pAddress;
+  uint8_t *pdestbuff = pDstBuffer;
+  HAL_SDRAM_StateTypeDef state = hsdram->State;
+
+  /* Check the SDRAM controller state */
+  if (state == HAL_SDRAM_STATE_BUSY)
+  {
+    return HAL_BUSY;
+  }
+  else if ((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_WRITE_PROTECTED))
+  {
+    /* Process Locked */
+    __HAL_LOCK(hsdram);
+
+    /* Update the SDRAM controller state */
+    hsdram->State = HAL_SDRAM_STATE_BUSY;
+
+    /* Read data from source */
+    for (size = BufferSize; size != 0U; size--)
+    {
+      *pdestbuff = *(__IO uint8_t *)pSdramAddress;
+      pdestbuff++;
+      pSdramAddress++;
+    }
+
+    /* Update the SDRAM controller state */
+    hsdram->State = state;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hsdram);
+  }
+  else
+  {
+    return  HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Writes 8-bit data buffer to SDRAM memory.
+  * @param  hsdram pointer to a SDRAM_HandleTypeDef structure that contains
+  *                the configuration information for SDRAM module.
+  * @param  pAddress Pointer to write start address
+  * @param  pSrcBuffer Pointer to source buffer to write
+  * @param  BufferSize Size of the buffer to write to memory
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SDRAM_Write_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pSrcBuffer,
+                                     uint32_t BufferSize)
+{
+  uint32_t size;
+  __IO uint8_t *pSdramAddress = (uint8_t *)pAddress;
+  uint8_t *psrcbuff = pSrcBuffer;
+
+  /* Check the SDRAM controller state */
+  if (hsdram->State == HAL_SDRAM_STATE_BUSY)
+  {
+    return HAL_BUSY;
+  }
+  else if (hsdram->State == HAL_SDRAM_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hsdram);
+
+    /* Update the SDRAM controller state */
+    hsdram->State = HAL_SDRAM_STATE_BUSY;
+
+    /* Write data to memory */
+    for (size = BufferSize; size != 0U; size--)
+    {
+      *(__IO uint8_t *)pSdramAddress = *psrcbuff;
+      psrcbuff++;
+      pSdramAddress++;
+    }
+
+    /* Update the SDRAM controller state */
+    hsdram->State = HAL_SDRAM_STATE_READY;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hsdram);
+  }
+  else
+  {
+    return  HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Reads 16-bit data buffer from the SDRAM memory.
+  * @param  hsdram pointer to a SDRAM_HandleTypeDef structure that contains
+  *                the configuration information for SDRAM module.
+  * @param  pAddress Pointer to read start address
+  * @param  pDstBuffer Pointer to destination buffer
+  * @param  BufferSize Size of the buffer to read from memory
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SDRAM_Read_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pDstBuffer,
+                                     uint32_t BufferSize)
+{
+  uint32_t size;
+  __IO uint32_t *pSdramAddress = pAddress;
+  uint16_t *pdestbuff = pDstBuffer;
+  HAL_SDRAM_StateTypeDef state = hsdram->State;
+
+  /* Check the SDRAM controller state */
+  if (state == HAL_SDRAM_STATE_BUSY)
+  {
+    return HAL_BUSY;
+  }
+  else if ((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_WRITE_PROTECTED))
+  {
+    /* Process Locked */
+    __HAL_LOCK(hsdram);
+
+    /* Update the SDRAM controller state */
+    hsdram->State = HAL_SDRAM_STATE_BUSY;
+
+    /* Read data from memory */
+    for (size = BufferSize; size >= 2U ; size -= 2U)
+    {
+      *pdestbuff = (uint16_t)((*pSdramAddress) & 0x0000FFFFU);
+      pdestbuff++;
+      *pdestbuff = (uint16_t)(((*pSdramAddress) & 0xFFFF0000U) >> 16U);
+      pdestbuff++;
+      pSdramAddress++;
+    }
+
+    /* Read last 16-bits if size is not 32-bits multiple */
+    if ((BufferSize % 2U) != 0U)
+    {
+      *pdestbuff = (uint16_t)((*pSdramAddress) & 0x0000FFFFU);
+    }
+
+    /* Update the SDRAM controller state */
+    hsdram->State = state;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hsdram);
+  }
+  else
+  {
+    return  HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Writes 16-bit data buffer to SDRAM memory.
+  * @param  hsdram pointer to a SDRAM_HandleTypeDef structure that contains
+  *                the configuration information for SDRAM module.
+  * @param  pAddress Pointer to write start address
+  * @param  pSrcBuffer Pointer to source buffer to write
+  * @param  BufferSize Size of the buffer to write to memory
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SDRAM_Write_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pSrcBuffer,
+                                      uint32_t BufferSize)
+{
+  uint32_t size;
+  __IO uint32_t *psdramaddress = pAddress;
+  uint16_t *psrcbuff = pSrcBuffer;
+
+  /* Check the SDRAM controller state */
+  if (hsdram->State == HAL_SDRAM_STATE_BUSY)
+  {
+    return HAL_BUSY;
+  }
+  else if (hsdram->State == HAL_SDRAM_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hsdram);
+
+    /* Update the SDRAM controller state */
+    hsdram->State = HAL_SDRAM_STATE_BUSY;
+
+    /* Write data to memory */
+    for (size = BufferSize; size >= 2U ; size -= 2U)
+    {
+      *psdramaddress = (uint32_t)(*psrcbuff);
+      psrcbuff++;
+      *psdramaddress |= ((uint32_t)(*psrcbuff) << 16U);
+      psrcbuff++;
+      psdramaddress++;
+    }
+
+    /* Write last 16-bits if size is not 32-bits multiple */
+    if ((BufferSize % 2U) != 0U)
+    {
+      *psdramaddress = ((uint32_t)(*psrcbuff) & 0x0000FFFFU) | ((*psdramaddress) & 0xFFFF0000U);
+    }
+
+    /* Update the SDRAM controller state */
+    hsdram->State = HAL_SDRAM_STATE_READY;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hsdram);
+  }
+  else
+  {
+    return  HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Reads 32-bit data buffer from the SDRAM memory.
+  * @param  hsdram pointer to a SDRAM_HandleTypeDef structure that contains
+  *                the configuration information for SDRAM module.
+  * @param  pAddress Pointer to read start address
+  * @param  pDstBuffer Pointer to destination buffer
+  * @param  BufferSize Size of the buffer to read from memory
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SDRAM_Read_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pDstBuffer,
+                                     uint32_t BufferSize)
+{
+  uint32_t size;
+  __IO uint32_t *pSdramAddress = (uint32_t *)pAddress;
+  uint32_t *pdestbuff = pDstBuffer;
+  HAL_SDRAM_StateTypeDef state = hsdram->State;
+
+  /* Check the SDRAM controller state */
+  if (state == HAL_SDRAM_STATE_BUSY)
+  {
+    return HAL_BUSY;
+  }
+  else if ((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_WRITE_PROTECTED))
+  {
+    /* Process Locked */
+    __HAL_LOCK(hsdram);
+
+    /* Update the SDRAM controller state */
+    hsdram->State = HAL_SDRAM_STATE_BUSY;
+
+    /* Read data from source */
+    for (size = BufferSize; size != 0U; size--)
+    {
+      *pdestbuff = *(__IO uint32_t *)pSdramAddress;
+      pdestbuff++;
+      pSdramAddress++;
+    }
+
+    /* Update the SDRAM controller state */
+    hsdram->State = state;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hsdram);
+  }
+  else
+  {
+    return  HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Writes 32-bit data buffer to SDRAM memory.
+  * @param  hsdram pointer to a SDRAM_HandleTypeDef structure that contains
+  *                the configuration information for SDRAM module.
+  * @param  pAddress Pointer to write start address
+  * @param  pSrcBuffer Pointer to source buffer to write
+  * @param  BufferSize Size of the buffer to write to memory
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SDRAM_Write_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer,
+                                      uint32_t BufferSize)
+{
+  uint32_t size;
+  __IO uint32_t *pSdramAddress = pAddress;
+  uint32_t *psrcbuff = pSrcBuffer;
+
+  /* Check the SDRAM controller state */
+  if (hsdram->State == HAL_SDRAM_STATE_BUSY)
+  {
+    return HAL_BUSY;
+  }
+  else if (hsdram->State == HAL_SDRAM_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hsdram);
+
+    /* Update the SDRAM controller state */
+    hsdram->State = HAL_SDRAM_STATE_BUSY;
+
+    /* Write data to memory */
+    for (size = BufferSize; size != 0U; size--)
+    {
+      *pSdramAddress = *psrcbuff;
+      psrcbuff++;
+      pSdramAddress++;
+    }
+
+    /* Update the SDRAM controller state */
+    hsdram->State = HAL_SDRAM_STATE_READY;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hsdram);
+  }
+  else
+  {
+    return  HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Reads a Words data from the SDRAM memory using DMA transfer.
+  * @param  hsdram pointer to a SDRAM_HandleTypeDef structure that contains
+  *                the configuration information for SDRAM module.
+  * @param  pAddress Pointer to read start address
+  * @param  pDstBuffer Pointer to destination buffer
+  * @param  BufferSize Size of the buffer to read from memory
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SDRAM_Read_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pDstBuffer,
+                                     uint32_t BufferSize)
+{
+  HAL_StatusTypeDef status;
+  HAL_SDRAM_StateTypeDef state = hsdram->State;
+
+  /* Check the SDRAM controller state */
+  if (state == HAL_SDRAM_STATE_BUSY)
+  {
+    status = HAL_BUSY;
+  }
+  else if ((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_WRITE_PROTECTED))
+  {
+    /* Process Locked */
+    __HAL_LOCK(hsdram);
+
+    /* Update the SDRAM controller state */
+    hsdram->State = HAL_SDRAM_STATE_BUSY;
+
+    /* Configure DMA user callbacks */
+    if (state == HAL_SDRAM_STATE_READY)
+    {
+      hsdram->hdma->XferCpltCallback = SDRAM_DMACplt;
+    }
+    else
+    {
+      hsdram->hdma->XferCpltCallback = SDRAM_DMACpltProt;
+    }
+    hsdram->hdma->XferErrorCallback = SDRAM_DMAError;
+
+    /* Enable the DMA Stream */
+    status = HAL_DMA_Start_IT(hsdram->hdma, (uint32_t)pAddress, (uint32_t)pDstBuffer, (uint32_t)BufferSize);
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hsdram);
+  }
+  else
+  {
+    status = HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Writes a Words data buffer to SDRAM memory using DMA transfer.
+  * @param  hsdram pointer to a SDRAM_HandleTypeDef structure that contains
+  *                the configuration information for SDRAM module.
+  * @param  pAddress Pointer to write start address
+  * @param  pSrcBuffer Pointer to source buffer to write
+  * @param  BufferSize Size of the buffer to write to memory
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SDRAM_Write_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer,
+                                      uint32_t BufferSize)
+{
+  HAL_StatusTypeDef status;
+
+  /* Check the SDRAM controller state */
+  if (hsdram->State == HAL_SDRAM_STATE_BUSY)
+  {
+    status = HAL_BUSY;
+  }
+  else if (hsdram->State == HAL_SDRAM_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hsdram);
+
+    /* Update the SDRAM controller state */
+    hsdram->State = HAL_SDRAM_STATE_BUSY;
+
+    /* Configure DMA user callbacks */
+    hsdram->hdma->XferCpltCallback = SDRAM_DMACplt;
+    hsdram->hdma->XferErrorCallback = SDRAM_DMAError;
+
+    /* Enable the DMA Stream */
+    status = HAL_DMA_Start_IT(hsdram->hdma, (uint32_t)pSrcBuffer, (uint32_t)pAddress, (uint32_t)BufferSize);
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hsdram);
+  }
+  else
+  {
+    status = HAL_ERROR;
+  }
+
+  return status;
+}
+
+#if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1)
+/**
+  * @brief  Register a User SDRAM Callback
+  *         To be used instead of the weak (surcharged) predefined callback
+  * @param hsdram : SDRAM handle
+  * @param CallbackId : ID of the callback to be registered
+  *        This parameter can be one of the following values:
+  *          @arg @ref HAL_SDRAM_MSP_INIT_CB_ID       SDRAM MspInit callback ID
+  *          @arg @ref HAL_SDRAM_MSP_DEINIT_CB_ID     SDRAM MspDeInit callback ID
+  *          @arg @ref HAL_SDRAM_REFRESH_ERR_CB_ID    SDRAM Refresh Error callback ID
+  * @param pCallback : pointer to the Callback function
+  * @retval status
+  */
+HAL_StatusTypeDef HAL_SDRAM_RegisterCallback(SDRAM_HandleTypeDef *hsdram, HAL_SDRAM_CallbackIDTypeDef CallbackId,
+                                             pSDRAM_CallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  HAL_SDRAM_StateTypeDef state;
+
+  if (pCallback == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Process locked */
+  __HAL_LOCK(hsdram);
+
+  state = hsdram->State;
+  if ((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_WRITE_PROTECTED))
+  {
+    switch (CallbackId)
+    {
+      case HAL_SDRAM_MSP_INIT_CB_ID :
+        hsdram->MspInitCallback = pCallback;
+        break;
+      case HAL_SDRAM_MSP_DEINIT_CB_ID :
+        hsdram->MspDeInitCallback = pCallback;
+        break;
+      case HAL_SDRAM_REFRESH_ERR_CB_ID :
+        hsdram->RefreshErrorCallback = pCallback;
+        break;
+      default :
+        /* update return status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else if (hsdram->State == HAL_SDRAM_STATE_RESET)
+  {
+    switch (CallbackId)
+    {
+      case HAL_SDRAM_MSP_INIT_CB_ID :
+        hsdram->MspInitCallback = pCallback;
+        break;
+      case HAL_SDRAM_MSP_DEINIT_CB_ID :
+        hsdram->MspDeInitCallback = pCallback;
+        break;
+      default :
+        /* update return status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    /* update return status */
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(hsdram);
+  return status;
+}
+
+/**
+  * @brief  Unregister a User SDRAM Callback
+  *         SDRAM Callback is redirected to the weak (surcharged) predefined callback
+  * @param hsdram : SDRAM handle
+  * @param CallbackId : ID of the callback to be unregistered
+  *        This parameter can be one of the following values:
+  *          @arg @ref HAL_SDRAM_MSP_INIT_CB_ID       SDRAM MspInit callback ID
+  *          @arg @ref HAL_SDRAM_MSP_DEINIT_CB_ID     SDRAM MspDeInit callback ID
+  *          @arg @ref HAL_SDRAM_REFRESH_ERR_CB_ID    SDRAM Refresh Error callback ID
+  *          @arg @ref HAL_SDRAM_DMA_XFER_CPLT_CB_ID  SDRAM DMA Xfer Complete callback ID
+  *          @arg @ref HAL_SDRAM_DMA_XFER_ERR_CB_ID   SDRAM DMA Xfer Error callback ID
+  * @retval status
+  */
+HAL_StatusTypeDef HAL_SDRAM_UnRegisterCallback(SDRAM_HandleTypeDef *hsdram, HAL_SDRAM_CallbackIDTypeDef CallbackId)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  HAL_SDRAM_StateTypeDef state;
+
+  /* Process locked */
+  __HAL_LOCK(hsdram);
+
+  state = hsdram->State;
+  if ((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_WRITE_PROTECTED))
+  {
+    switch (CallbackId)
+    {
+      case HAL_SDRAM_MSP_INIT_CB_ID :
+        hsdram->MspInitCallback = HAL_SDRAM_MspInit;
+        break;
+      case HAL_SDRAM_MSP_DEINIT_CB_ID :
+        hsdram->MspDeInitCallback = HAL_SDRAM_MspDeInit;
+        break;
+      case HAL_SDRAM_REFRESH_ERR_CB_ID :
+        hsdram->RefreshErrorCallback = HAL_SDRAM_RefreshErrorCallback;
+        break;
+      case HAL_SDRAM_DMA_XFER_CPLT_CB_ID :
+        hsdram->DmaXferCpltCallback = HAL_SDRAM_DMA_XferCpltCallback;
+        break;
+      case HAL_SDRAM_DMA_XFER_ERR_CB_ID :
+        hsdram->DmaXferErrorCallback = HAL_SDRAM_DMA_XferErrorCallback;
+        break;
+      default :
+        /* update return status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else if (hsdram->State == HAL_SDRAM_STATE_RESET)
+  {
+    switch (CallbackId)
+    {
+      case HAL_SDRAM_MSP_INIT_CB_ID :
+        hsdram->MspInitCallback = HAL_SDRAM_MspInit;
+        break;
+      case HAL_SDRAM_MSP_DEINIT_CB_ID :
+        hsdram->MspDeInitCallback = HAL_SDRAM_MspDeInit;
+        break;
+      default :
+        /* update return status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    /* update return status */
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(hsdram);
+  return status;
+}
+
+/**
+  * @brief  Register a User SDRAM Callback for DMA transfers
+  *         To be used instead of the weak (surcharged) predefined callback
+  * @param hsdram : SDRAM handle
+  * @param CallbackId : ID of the callback to be registered
+  *        This parameter can be one of the following values:
+  *          @arg @ref HAL_SDRAM_DMA_XFER_CPLT_CB_ID  SDRAM DMA Xfer Complete callback ID
+  *          @arg @ref HAL_SDRAM_DMA_XFER_ERR_CB_ID   SDRAM DMA Xfer Error callback ID
+  * @param pCallback : pointer to the Callback function
+  * @retval status
+  */
+HAL_StatusTypeDef HAL_SDRAM_RegisterDmaCallback(SDRAM_HandleTypeDef *hsdram, HAL_SDRAM_CallbackIDTypeDef CallbackId,
+                                                pSDRAM_DmaCallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  HAL_SDRAM_StateTypeDef state;
+
+  if (pCallback == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Process locked */
+  __HAL_LOCK(hsdram);
+
+  state = hsdram->State;
+  if ((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_WRITE_PROTECTED))
+  {
+    switch (CallbackId)
+    {
+      case HAL_SDRAM_DMA_XFER_CPLT_CB_ID :
+        hsdram->DmaXferCpltCallback = pCallback;
+        break;
+      case HAL_SDRAM_DMA_XFER_ERR_CB_ID :
+        hsdram->DmaXferErrorCallback = pCallback;
+        break;
+      default :
+        /* update return status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    /* update return status */
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(hsdram);
+  return status;
+}
+#endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+
+/** @defgroup SDRAM_Exported_Functions_Group3 Control functions
+  *  @brief   management functions
+  *
+@verbatim
+  ==============================================================================
+                         ##### SDRAM Control functions #####
+  ==============================================================================
+  [..]
+    This subsection provides a set of functions allowing to control dynamically
+    the SDRAM interface.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enables dynamically SDRAM write protection.
+  * @param  hsdram pointer to a SDRAM_HandleTypeDef structure that contains
+  *                the configuration information for SDRAM module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SDRAM_WriteProtection_Enable(SDRAM_HandleTypeDef *hsdram)
+{
+  /* Check the SDRAM controller state */
+  if (hsdram->State == HAL_SDRAM_STATE_BUSY)
+  {
+    return HAL_BUSY;
+  }
+  else if (hsdram->State == HAL_SDRAM_STATE_READY)
+  {
+    /* Update the SDRAM state */
+    hsdram->State = HAL_SDRAM_STATE_BUSY;
+
+    /* Enable write protection */
+    (void)FMC_SDRAM_WriteProtection_Enable(hsdram->Instance, hsdram->Init.SDBank);
+
+    /* Update the SDRAM state */
+    hsdram->State = HAL_SDRAM_STATE_WRITE_PROTECTED;
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Disables dynamically SDRAM write protection.
+  * @param  hsdram pointer to a SDRAM_HandleTypeDef structure that contains
+  *                the configuration information for SDRAM module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SDRAM_WriteProtection_Disable(SDRAM_HandleTypeDef *hsdram)
+{
+  HAL_SDRAM_StateTypeDef state = hsdram->State;
+
+  /* Check the SDRAM controller state */
+  if (state == HAL_SDRAM_STATE_BUSY)
+  {
+    return HAL_BUSY;
+  }
+  else if (state == HAL_SDRAM_STATE_WRITE_PROTECTED)
+  {
+    /* Update the SDRAM state */
+    hsdram->State = HAL_SDRAM_STATE_BUSY;
+
+    /* Disable write protection */
+    (void)FMC_SDRAM_WriteProtection_Disable(hsdram->Instance, hsdram->Init.SDBank);
+
+    /* Update the SDRAM state */
+    hsdram->State = HAL_SDRAM_STATE_READY;
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Sends Command to the SDRAM bank.
+  * @param  hsdram pointer to a SDRAM_HandleTypeDef structure that contains
+  *                the configuration information for SDRAM module.
+  * @param  Command SDRAM command structure
+  * @param  Timeout Timeout duration
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SDRAM_SendCommand(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_CommandTypeDef *Command,
+                                        uint32_t Timeout)
+{
+  HAL_SDRAM_StateTypeDef state = hsdram->State;
+
+  /* Check the SDRAM controller state */
+  if (state == HAL_SDRAM_STATE_BUSY)
+  {
+    return HAL_BUSY;
+  }
+  else if ((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_PRECHARGED))
+  {
+    /* Update the SDRAM state */
+    hsdram->State = HAL_SDRAM_STATE_BUSY;
+
+    /* Send SDRAM command */
+    (void)FMC_SDRAM_SendCommand(hsdram->Instance, Command, Timeout);
+
+    /* Update the SDRAM controller state state */
+    if (Command->CommandMode == FMC_SDRAM_CMD_PALL)
+    {
+      hsdram->State = HAL_SDRAM_STATE_PRECHARGED;
+    }
+    else
+    {
+      hsdram->State = HAL_SDRAM_STATE_READY;
+    }
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Programs the SDRAM Memory Refresh rate.
+  * @param  hsdram pointer to a SDRAM_HandleTypeDef structure that contains
+  *                the configuration information for SDRAM module.
+  * @param  RefreshRate The SDRAM refresh rate value
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SDRAM_ProgramRefreshRate(SDRAM_HandleTypeDef *hsdram, uint32_t RefreshRate)
+{
+  /* Check the SDRAM controller state */
+  if (hsdram->State == HAL_SDRAM_STATE_BUSY)
+  {
+    return HAL_BUSY;
+  }
+  else if (hsdram->State == HAL_SDRAM_STATE_READY)
+  {
+    /* Update the SDRAM state */
+    hsdram->State = HAL_SDRAM_STATE_BUSY;
+
+    /* Program the refresh rate */
+    (void)FMC_SDRAM_ProgramRefreshRate(hsdram->Instance, RefreshRate);
+
+    /* Update the SDRAM state */
+    hsdram->State = HAL_SDRAM_STATE_READY;
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Sets the Number of consecutive SDRAM Memory auto Refresh commands.
+  * @param  hsdram pointer to a SDRAM_HandleTypeDef structure that contains
+  *                the configuration information for SDRAM module.
+  * @param  AutoRefreshNumber The SDRAM auto Refresh number
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SDRAM_SetAutoRefreshNumber(SDRAM_HandleTypeDef *hsdram, uint32_t AutoRefreshNumber)
+{
+  /* Check the SDRAM controller state */
+  if (hsdram->State == HAL_SDRAM_STATE_BUSY)
+  {
+    return HAL_BUSY;
+  }
+  else if (hsdram->State == HAL_SDRAM_STATE_READY)
+  {
+    /* Update the SDRAM state */
+    hsdram->State = HAL_SDRAM_STATE_BUSY;
+
+    /* Set the Auto-Refresh number */
+    (void)FMC_SDRAM_SetAutoRefreshNumber(hsdram->Instance, AutoRefreshNumber);
+
+    /* Update the SDRAM state */
+    hsdram->State = HAL_SDRAM_STATE_READY;
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Returns the SDRAM memory current mode.
+  * @param  hsdram pointer to a SDRAM_HandleTypeDef structure that contains
+  *                the configuration information for SDRAM module.
+  * @retval The SDRAM memory mode.
+  */
+uint32_t HAL_SDRAM_GetModeStatus(SDRAM_HandleTypeDef *hsdram)
+{
+  /* Return the SDRAM memory current mode */
+  return (FMC_SDRAM_GetModeStatus(hsdram->Instance, hsdram->Init.SDBank));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup SDRAM_Exported_Functions_Group4 State functions
+  *  @brief   Peripheral State functions
+  *
+@verbatim
+  ==============================================================================
+                      ##### SDRAM State functions #####
+  ==============================================================================
+  [..]
+    This subsection permits to get in run-time the status of the SDRAM controller
+    and the data flow.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Returns the SDRAM state.
+  * @param  hsdram pointer to a SDRAM_HandleTypeDef structure that contains
+  *                the configuration information for SDRAM module.
+  * @retval HAL state
+  */
+HAL_SDRAM_StateTypeDef HAL_SDRAM_GetState(SDRAM_HandleTypeDef *hsdram)
+{
+  return hsdram->State;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @brief  DMA SDRAM process complete callback.
+  * @param  hdma : DMA handle
+  * @retval None
+  */
+static void SDRAM_DMACplt(DMA_HandleTypeDef *hdma)
+{
+  SDRAM_HandleTypeDef *hsdram = (SDRAM_HandleTypeDef *)(hdma->Parent);
+
+  /* Disable the DMA channel */
+  __HAL_DMA_DISABLE(hdma);
+
+  /* Update the SDRAM controller state */
+  hsdram->State = HAL_SDRAM_STATE_READY;
+
+#if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1)
+  hsdram->DmaXferCpltCallback(hdma);
+#else
+  HAL_SDRAM_DMA_XferCpltCallback(hdma);
+#endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */
+}
+
+/**
+  * @brief  DMA SRAM process complete callback.
+  * @param  hdma : DMA handle
+  * @retval None
+  */
+static void SDRAM_DMACpltProt(DMA_HandleTypeDef *hdma)
+{
+  SDRAM_HandleTypeDef *hsdram = (SDRAM_HandleTypeDef *)(hdma->Parent);
+
+  /* Disable the DMA channel */
+  __HAL_DMA_DISABLE(hdma);
+
+  /* Update the SDRAM controller state */
+  hsdram->State = HAL_SDRAM_STATE_WRITE_PROTECTED;
+
+#if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1)
+  hsdram->DmaXferCpltCallback(hdma);
+#else
+  HAL_SDRAM_DMA_XferCpltCallback(hdma);
+#endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */
+}
+
+/**
+  * @brief  DMA SDRAM error callback.
+  * @param  hdma : DMA handle
+  * @retval None
+  */
+static void SDRAM_DMAError(DMA_HandleTypeDef *hdma)
+{
+  SDRAM_HandleTypeDef *hsdram = (SDRAM_HandleTypeDef *)(hdma->Parent);
+
+  /* Disable the DMA channel */
+  __HAL_DMA_DISABLE(hdma);
+
+  /* Update the SDRAM controller state */
+  hsdram->State = HAL_SDRAM_STATE_ERROR;
+
+#if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1)
+  hsdram->DmaXferErrorCallback(hdma);
+#else
+  HAL_SDRAM_DMA_XferErrorCallback(hdma);
+#endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */
+}
+
+/**
+  * @}
+  */
+
+#endif /* HAL_SDRAM_MODULE_ENABLED */
+
+/**
+  * @}
+  */
+
+#endif /* FMC_Bank5_6 */
diff --git a/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c
new file mode 100644
index 0000000..eb3f5c3
--- /dev/null
+++ b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c
@@ -0,0 +1,7621 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hal_tim.c
+  * @author  MCD Application Team
+  * @brief   TIM HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the Timer (TIM) peripheral:
+  *           + TIM Time Base Initialization
+  *           + TIM Time Base Start
+  *           + TIM Time Base Start Interruption
+  *           + TIM Time Base Start DMA
+  *           + TIM Output Compare/PWM Initialization
+  *           + TIM Output Compare/PWM Channel Configuration
+  *           + TIM Output Compare/PWM  Start
+  *           + TIM Output Compare/PWM  Start Interruption
+  *           + TIM Output Compare/PWM Start DMA
+  *           + TIM Input Capture Initialization
+  *           + TIM Input Capture Channel Configuration
+  *           + TIM Input Capture Start
+  *           + TIM Input Capture Start Interruption
+  *           + TIM Input Capture Start DMA
+  *           + TIM One Pulse Initialization
+  *           + TIM One Pulse Channel Configuration
+  *           + TIM One Pulse Start
+  *           + TIM Encoder Interface Initialization
+  *           + TIM Encoder Interface Start
+  *           + TIM Encoder Interface Start Interruption
+  *           + TIM Encoder Interface Start DMA
+  *           + Commutation Event configuration with Interruption and DMA
+  *           + TIM OCRef clear configuration
+  *           + TIM External Clock configuration
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2016 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  @verbatim
+  ==============================================================================
+                      ##### TIMER Generic features #####
+  ==============================================================================
+  [..] The Timer features include:
+       (#) 16-bit up, down, up/down auto-reload counter.
+       (#) 16-bit programmable prescaler allowing dividing (also on the fly) the
+           counter clock frequency either by any factor between 1 and 65536.
+       (#) Up to 4 independent channels for:
+           (++) Input Capture
+           (++) Output Compare
+           (++) PWM generation (Edge and Center-aligned Mode)
+           (++) One-pulse mode output
+       (#) Synchronization circuit to control the timer with external signals and to interconnect
+            several timers together.
+       (#) Supports incremental encoder for positioning purposes
+
+            ##### How to use this driver #####
+  ==============================================================================
+    [..]
+     (#) Initialize the TIM low level resources by implementing the following functions
+         depending on the selected feature:
+           (++) Time Base : HAL_TIM_Base_MspInit()
+           (++) Input Capture : HAL_TIM_IC_MspInit()
+           (++) Output Compare : HAL_TIM_OC_MspInit()
+           (++) PWM generation : HAL_TIM_PWM_MspInit()
+           (++) One-pulse mode output : HAL_TIM_OnePulse_MspInit()
+           (++) Encoder mode output : HAL_TIM_Encoder_MspInit()
+
+     (#) Initialize the TIM low level resources :
+        (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE();
+        (##) TIM pins configuration
+            (+++) Enable the clock for the TIM GPIOs using the following function:
+             __HAL_RCC_GPIOx_CLK_ENABLE();
+            (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();
+
+     (#) The external Clock can be configured, if needed (the default clock is the
+         internal clock from the APBx), using the following function:
+         HAL_TIM_ConfigClockSource, the clock configuration should be done before
+         any start function.
+
+     (#) Configure the TIM in the desired functioning mode using one of the
+       Initialization function of this driver:
+       (++) HAL_TIM_Base_Init: to use the Timer to generate a simple time base
+       (++) HAL_TIM_OC_Init and HAL_TIM_OC_ConfigChannel: to use the Timer to generate an
+            Output Compare signal.
+       (++) HAL_TIM_PWM_Init and HAL_TIM_PWM_ConfigChannel: to use the Timer to generate a
+            PWM signal.
+       (++) HAL_TIM_IC_Init and HAL_TIM_IC_ConfigChannel: to use the Timer to measure an
+            external signal.
+       (++) HAL_TIM_OnePulse_Init and HAL_TIM_OnePulse_ConfigChannel: to use the Timer
+            in One Pulse Mode.
+       (++) HAL_TIM_Encoder_Init: to use the Timer Encoder Interface.
+
+     (#) Activate the TIM peripheral using one of the start functions depending from the feature used:
+           (++) Time Base : HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT()
+           (++) Input Capture :  HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT()
+           (++) Output Compare : HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT()
+           (++) PWM generation : HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT()
+           (++) One-pulse mode output : HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT()
+           (++) Encoder mode output : HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT().
+
+     (#) The DMA Burst is managed with the two following functions:
+         HAL_TIM_DMABurst_WriteStart()
+         HAL_TIM_DMABurst_ReadStart()
+
+    *** Callback registration ***
+  =============================================
+
+  [..]
+  The compilation define  USE_HAL_TIM_REGISTER_CALLBACKS when set to 1
+  allows the user to configure dynamically the driver callbacks.
+
+  [..]
+  Use Function HAL_TIM_RegisterCallback() to register a callback.
+  HAL_TIM_RegisterCallback() takes as parameters the HAL peripheral handle,
+  the Callback ID and a pointer to the user callback function.
+
+  [..]
+  Use function HAL_TIM_UnRegisterCallback() to reset a callback to the default
+  weak function.
+  HAL_TIM_UnRegisterCallback takes as parameters the HAL peripheral handle,
+  and the Callback ID.
+
+  [..]
+  These functions allow to register/unregister following callbacks:
+    (+) Base_MspInitCallback              : TIM Base Msp Init Callback.
+    (+) Base_MspDeInitCallback            : TIM Base Msp DeInit Callback.
+    (+) IC_MspInitCallback                : TIM IC Msp Init Callback.
+    (+) IC_MspDeInitCallback              : TIM IC Msp DeInit Callback.
+    (+) OC_MspInitCallback                : TIM OC Msp Init Callback.
+    (+) OC_MspDeInitCallback              : TIM OC Msp DeInit Callback.
+    (+) PWM_MspInitCallback               : TIM PWM Msp Init Callback.
+    (+) PWM_MspDeInitCallback             : TIM PWM Msp DeInit Callback.
+    (+) OnePulse_MspInitCallback          : TIM One Pulse Msp Init Callback.
+    (+) OnePulse_MspDeInitCallback        : TIM One Pulse Msp DeInit Callback.
+    (+) Encoder_MspInitCallback           : TIM Encoder Msp Init Callback.
+    (+) Encoder_MspDeInitCallback         : TIM Encoder Msp DeInit Callback.
+    (+) HallSensor_MspInitCallback        : TIM Hall Sensor Msp Init Callback.
+    (+) HallSensor_MspDeInitCallback      : TIM Hall Sensor Msp DeInit Callback.
+    (+) PeriodElapsedCallback             : TIM Period Elapsed Callback.
+    (+) PeriodElapsedHalfCpltCallback     : TIM Period Elapsed half complete Callback.
+    (+) TriggerCallback                   : TIM Trigger Callback.
+    (+) TriggerHalfCpltCallback           : TIM Trigger half complete Callback.
+    (+) IC_CaptureCallback                : TIM Input Capture Callback.
+    (+) IC_CaptureHalfCpltCallback        : TIM Input Capture half complete Callback.
+    (+) OC_DelayElapsedCallback           : TIM Output Compare Delay Elapsed Callback.
+    (+) PWM_PulseFinishedCallback         : TIM PWM Pulse Finished Callback.
+    (+) PWM_PulseFinishedHalfCpltCallback : TIM PWM Pulse Finished half complete Callback.
+    (+) ErrorCallback                     : TIM Error Callback.
+    (+) CommutationCallback               : TIM Commutation Callback.
+    (+) CommutationHalfCpltCallback       : TIM Commutation half complete Callback.
+    (+) BreakCallback                     : TIM Break Callback.
+
+  [..]
+By default, after the Init and when the state is HAL_TIM_STATE_RESET
+all interrupt callbacks are set to the corresponding weak functions:
+  examples HAL_TIM_TriggerCallback(), HAL_TIM_ErrorCallback().
+
+  [..]
+  Exception done for MspInit and MspDeInit functions that are reset to the legacy weak
+  functionalities in the Init / DeInit only when these callbacks are null
+  (not registered beforehand). If not, MspInit or MspDeInit are not null, the Init / DeInit
+    keep and use the user MspInit / MspDeInit callbacks(registered beforehand)
+
+  [..]
+    Callbacks can be registered / unregistered in HAL_TIM_STATE_READY state only.
+    Exception done MspInit / MspDeInit that can be registered / unregistered
+    in HAL_TIM_STATE_READY or HAL_TIM_STATE_RESET state,
+    thus registered(user) MspInit / DeInit callbacks can be used during the Init / DeInit.
+  In that case first register the MspInit/MspDeInit user callbacks
+      using HAL_TIM_RegisterCallback() before calling DeInit or Init function.
+
+  [..]
+      When The compilation define USE_HAL_TIM_REGISTER_CALLBACKS is set to 0 or
+      not defined, the callback registration feature is not available and all callbacks
+      are set to the corresponding weak functions.
+
+  @endverbatim
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup TIM TIM
+  * @brief TIM HAL module driver
+  * @{
+  */
+
+#ifdef HAL_TIM_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @addtogroup TIM_Private_Functions
+  * @{
+  */
+static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
+static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
+static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
+static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
+static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
+                              uint32_t TIM_ICFilter);
+static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
+static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
+                              uint32_t TIM_ICFilter);
+static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
+                              uint32_t TIM_ICFilter);
+static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource);
+static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma);
+static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma);
+static void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma);
+static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma);
+static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma);
+static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
+                                                  TIM_SlaveConfigTypeDef *sSlaveConfig);
+/**
+  * @}
+  */
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup TIM_Exported_Functions TIM Exported Functions
+  * @{
+  */
+
+/** @defgroup TIM_Exported_Functions_Group1 TIM Time Base functions
+  *  @brief    Time Base functions
+  *
+@verbatim
+  ==============================================================================
+              ##### Time Base functions #####
+  ==============================================================================
+  [..]
+    This section provides functions allowing to:
+    (+) Initialize and configure the TIM base.
+    (+) De-initialize the TIM base.
+    (+) Start the Time Base.
+    (+) Stop the Time Base.
+    (+) Start the Time Base and enable interrupt.
+    (+) Stop the Time Base and disable interrupt.
+    (+) Start the Time Base and enable DMA transfer.
+    (+) Stop the Time Base and disable DMA transfer.
+
+@endverbatim
+  * @{
+  */
+/**
+  * @brief  Initializes the TIM Time base Unit according to the specified
+  *         parameters in the TIM_HandleTypeDef and initialize the associated handle.
+  * @note   Switching from Center Aligned counter mode to Edge counter mode (or reverse)
+  *         requires a timer reset to avoid unexpected direction
+  *         due to DIR bit readonly in center aligned mode.
+  *         Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init()
+  * @param  htim TIM Base handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
+{
+  /* Check the TIM handle allocation */
+  if (htim == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_TIM_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
+  assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
+  assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
+
+  if (htim->State == HAL_TIM_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    htim->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+    /* Reset interrupt callbacks to legacy weak callbacks */
+    TIM_ResetCallback(htim);
+
+    if (htim->Base_MspInitCallback == NULL)
+    {
+      htim->Base_MspInitCallback = HAL_TIM_Base_MspInit;
+    }
+    /* Init the low level hardware : GPIO, CLOCK, NVIC */
+    htim->Base_MspInitCallback(htim);
+#else
+    /* Init the low level hardware : GPIO, CLOCK, NVIC */
+    HAL_TIM_Base_MspInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+  }
+
+  /* Set the TIM state */
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  /* Set the Time Base configuration */
+  TIM_Base_SetConfig(htim->Instance, &htim->Init);
+
+  /* Initialize the DMA burst operation state */
+  htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
+
+  /* Initialize the TIM channels state */
+  TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
+  TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
+
+  /* Initialize the TIM state*/
+  htim->State = HAL_TIM_STATE_READY;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  DeInitializes the TIM Base peripheral
+  * @param  htim TIM Base handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  /* Disable the TIM Peripheral Clock */
+  __HAL_TIM_DISABLE(htim);
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+  if (htim->Base_MspDeInitCallback == NULL)
+  {
+    htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit;
+  }
+  /* DeInit the low level hardware */
+  htim->Base_MspDeInitCallback(htim);
+#else
+  /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
+  HAL_TIM_Base_MspDeInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+  /* Change the DMA burst operation state */
+  htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
+
+  /* Change the TIM channels state */
+  TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
+  TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
+
+  /* Change TIM state */
+  htim->State = HAL_TIM_STATE_RESET;
+
+  /* Release Lock */
+  __HAL_UNLOCK(htim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the TIM Base MSP.
+  * @param  htim TIM Base handle
+  * @retval None
+  */
+__weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_Base_MspInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  DeInitializes TIM Base MSP.
+  * @param  htim TIM Base handle
+  * @retval None
+  */
+__weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_Base_MspDeInit could be implemented in the user file
+   */
+}
+
+
+/**
+  * @brief  Starts the TIM Base generation.
+  * @param  htim TIM Base handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim)
+{
+  uint32_t tmpsmcr;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+  /* Check the TIM state */
+  if (htim->State != HAL_TIM_STATE_READY)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Set the TIM state */
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+  if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+  {
+    tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+    if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+    {
+      __HAL_TIM_ENABLE(htim);
+    }
+  }
+  else
+  {
+    __HAL_TIM_ENABLE(htim);
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM Base generation.
+  * @param  htim TIM Base handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Set the TIM state */
+  htim->State = HAL_TIM_STATE_READY;
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Starts the TIM Base generation in interrupt mode.
+  * @param  htim TIM Base handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim)
+{
+  uint32_t tmpsmcr;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+  /* Check the TIM state */
+  if (htim->State != HAL_TIM_STATE_READY)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Set the TIM state */
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  /* Enable the TIM Update interrupt */
+  __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE);
+
+  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+  if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+  {
+    tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+    if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+    {
+      __HAL_TIM_ENABLE(htim);
+    }
+  }
+  else
+  {
+    __HAL_TIM_ENABLE(htim);
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM Base generation in interrupt mode.
+  * @param  htim TIM Base handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+  /* Disable the TIM Update interrupt */
+  __HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE);
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Set the TIM state */
+  htim->State = HAL_TIM_STATE_READY;
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Starts the TIM Base generation in DMA mode.
+  * @param  htim TIM Base handle
+  * @param  pData The source Buffer address.
+  * @param  Length The length of data to be transferred from memory to peripheral.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
+{
+  uint32_t tmpsmcr;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
+
+  /* Set the TIM state */
+  if (htim->State == HAL_TIM_STATE_BUSY)
+  {
+    return HAL_BUSY;
+  }
+  else if (htim->State == HAL_TIM_STATE_READY)
+  {
+    if ((pData == NULL) && (Length > 0U))
+    {
+      return HAL_ERROR;
+    }
+    else
+    {
+      htim->State = HAL_TIM_STATE_BUSY;
+    }
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  /* Set the DMA Period elapsed callbacks */
+  htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
+  htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt;
+
+  /* Set the DMA error callback */
+  htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
+
+  /* Enable the DMA stream */
+  if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR,
+                       Length) != HAL_OK)
+  {
+    /* Return error status */
+    return HAL_ERROR;
+  }
+
+  /* Enable the TIM Update DMA request */
+  __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_UPDATE);
+
+  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+  if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+  {
+    tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+    if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+    {
+      __HAL_TIM_ENABLE(htim);
+    }
+  }
+  else
+  {
+    __HAL_TIM_ENABLE(htim);
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM Base generation in DMA mode.
+  * @param  htim TIM Base handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
+
+  /* Disable the TIM Update DMA request */
+  __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_UPDATE);
+
+  (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Set the TIM state */
+  htim->State = HAL_TIM_STATE_READY;
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Exported_Functions_Group2 TIM Output Compare functions
+  *  @brief    TIM Output Compare functions
+  *
+@verbatim
+  ==============================================================================
+                  ##### TIM Output Compare functions #####
+  ==============================================================================
+  [..]
+    This section provides functions allowing to:
+    (+) Initialize and configure the TIM Output Compare.
+    (+) De-initialize the TIM Output Compare.
+    (+) Start the TIM Output Compare.
+    (+) Stop the TIM Output Compare.
+    (+) Start the TIM Output Compare and enable interrupt.
+    (+) Stop the TIM Output Compare and disable interrupt.
+    (+) Start the TIM Output Compare and enable DMA transfer.
+    (+) Stop the TIM Output Compare and disable DMA transfer.
+
+@endverbatim
+  * @{
+  */
+/**
+  * @brief  Initializes the TIM Output Compare according to the specified
+  *         parameters in the TIM_HandleTypeDef and initializes the associated handle.
+  * @note   Switching from Center Aligned counter mode to Edge counter mode (or reverse)
+  *         requires a timer reset to avoid unexpected direction
+  *         due to DIR bit readonly in center aligned mode.
+  *         Ex: call @ref HAL_TIM_OC_DeInit() before HAL_TIM_OC_Init()
+  * @param  htim TIM Output Compare handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim)
+{
+  /* Check the TIM handle allocation */
+  if (htim == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_TIM_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
+  assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
+  assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
+
+  if (htim->State == HAL_TIM_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    htim->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+    /* Reset interrupt callbacks to legacy weak callbacks */
+    TIM_ResetCallback(htim);
+
+    if (htim->OC_MspInitCallback == NULL)
+    {
+      htim->OC_MspInitCallback = HAL_TIM_OC_MspInit;
+    }
+    /* Init the low level hardware : GPIO, CLOCK, NVIC */
+    htim->OC_MspInitCallback(htim);
+#else
+    /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
+    HAL_TIM_OC_MspInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+  }
+
+  /* Set the TIM state */
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  /* Init the base time for the Output Compare */
+  TIM_Base_SetConfig(htim->Instance,  &htim->Init);
+
+  /* Initialize the DMA burst operation state */
+  htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
+
+  /* Initialize the TIM channels state */
+  TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
+  TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
+
+  /* Initialize the TIM state*/
+  htim->State = HAL_TIM_STATE_READY;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  DeInitializes the TIM peripheral
+  * @param  htim TIM Output Compare handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  /* Disable the TIM Peripheral Clock */
+  __HAL_TIM_DISABLE(htim);
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+  if (htim->OC_MspDeInitCallback == NULL)
+  {
+    htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit;
+  }
+  /* DeInit the low level hardware */
+  htim->OC_MspDeInitCallback(htim);
+#else
+  /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
+  HAL_TIM_OC_MspDeInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+  /* Change the DMA burst operation state */
+  htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
+
+  /* Change the TIM channels state */
+  TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
+  TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
+
+  /* Change TIM state */
+  htim->State = HAL_TIM_STATE_RESET;
+
+  /* Release Lock */
+  __HAL_UNLOCK(htim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the TIM Output Compare MSP.
+  * @param  htim TIM Output Compare handle
+  * @retval None
+  */
+__weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_OC_MspInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  DeInitializes TIM Output Compare MSP.
+  * @param  htim TIM Output Compare handle
+  * @retval None
+  */
+__weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_OC_MspDeInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Starts the TIM Output Compare signal generation.
+  * @param  htim TIM Output Compare handle
+  * @param  Channel TIM Channel to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  uint32_t tmpsmcr;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+  /* Check the TIM channel state */
+  if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Set the TIM channel state */
+  TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+
+  /* Enable the Output compare channel */
+  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+
+  if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+  {
+    /* Enable the main output */
+    __HAL_TIM_MOE_ENABLE(htim);
+  }
+
+  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+  if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+  {
+    tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+    if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+    {
+      __HAL_TIM_ENABLE(htim);
+    }
+  }
+  else
+  {
+    __HAL_TIM_ENABLE(htim);
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM Output Compare signal generation.
+  * @param  htim TIM Output Compare handle
+  * @param  Channel TIM Channel to be disabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+  /* Disable the Output compare channel */
+  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+
+  if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+  {
+    /* Disable the Main Output */
+    __HAL_TIM_MOE_DISABLE(htim);
+  }
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Set the TIM channel state */
+  TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Starts the TIM Output Compare signal generation in interrupt mode.
+  * @param  htim TIM Output Compare handle
+  * @param  Channel TIM Channel to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  uint32_t tmpsmcr;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+  /* Check the TIM channel state */
+  if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Set the TIM channel state */
+  TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Enable the TIM Capture/Compare 1 interrupt */
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      /* Enable the TIM Capture/Compare 2 interrupt */
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+      break;
+    }
+
+    case TIM_CHANNEL_3:
+    {
+      /* Enable the TIM Capture/Compare 3 interrupt */
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
+      break;
+    }
+
+    case TIM_CHANNEL_4:
+    {
+      /* Enable the TIM Capture/Compare 4 interrupt */
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
+      break;
+    }
+
+    default:
+      status = HAL_ERROR;
+      break;
+  }
+
+  if (status == HAL_OK)
+  {
+    /* Enable the Output compare channel */
+    TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+
+    if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+    {
+      /* Enable the main output */
+      __HAL_TIM_MOE_ENABLE(htim);
+    }
+
+    /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+    if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+    {
+      tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+      if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+      {
+        __HAL_TIM_ENABLE(htim);
+      }
+    }
+    else
+    {
+      __HAL_TIM_ENABLE(htim);
+    }
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  Stops the TIM Output Compare signal generation in interrupt mode.
+  * @param  htim TIM Output Compare handle
+  * @param  Channel TIM Channel to be disabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Disable the TIM Capture/Compare 1 interrupt */
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      /* Disable the TIM Capture/Compare 2 interrupt */
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+      break;
+    }
+
+    case TIM_CHANNEL_3:
+    {
+      /* Disable the TIM Capture/Compare 3 interrupt */
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
+      break;
+    }
+
+    case TIM_CHANNEL_4:
+    {
+      /* Disable the TIM Capture/Compare 4 interrupt */
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
+      break;
+    }
+
+    default:
+      status = HAL_ERROR;
+      break;
+  }
+
+  if (status == HAL_OK)
+  {
+    /* Disable the Output compare channel */
+    TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+
+    if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+    {
+      /* Disable the Main Output */
+      __HAL_TIM_MOE_DISABLE(htim);
+    }
+
+    /* Disable the Peripheral */
+    __HAL_TIM_DISABLE(htim);
+
+    /* Set the TIM channel state */
+    TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  Starts the TIM Output Compare signal generation in DMA mode.
+  * @param  htim TIM Output Compare handle
+  * @param  Channel TIM Channel to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @param  pData The source Buffer address.
+  * @param  Length The length of data to be transferred from memory to TIM peripheral
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  uint32_t tmpsmcr;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+  /* Set the TIM channel state */
+  if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY)
+  {
+    return HAL_BUSY;
+  }
+  else if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY)
+  {
+    if ((pData == NULL) && (Length > 0U))
+    {
+      return HAL_ERROR;
+    }
+    else
+    {
+      TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+    }
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Set the DMA compare callbacks */
+      htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
+      htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1,
+                           Length) != HAL_OK)
+      {
+        /* Return error status */
+        return HAL_ERROR;
+      }
+
+      /* Enable the TIM Capture/Compare 1 DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      /* Set the DMA compare callbacks */
+      htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
+      htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2,
+                           Length) != HAL_OK)
+      {
+        /* Return error status */
+        return HAL_ERROR;
+      }
+
+      /* Enable the TIM Capture/Compare 2 DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
+      break;
+    }
+
+    case TIM_CHANNEL_3:
+    {
+      /* Set the DMA compare callbacks */
+      htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
+      htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,
+                           Length) != HAL_OK)
+      {
+        /* Return error status */
+        return HAL_ERROR;
+      }
+      /* Enable the TIM Capture/Compare 3 DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
+      break;
+    }
+
+    case TIM_CHANNEL_4:
+    {
+      /* Set the DMA compare callbacks */
+      htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
+      htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4,
+                           Length) != HAL_OK)
+      {
+        /* Return error status */
+        return HAL_ERROR;
+      }
+      /* Enable the TIM Capture/Compare 4 DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
+      break;
+    }
+
+    default:
+      status = HAL_ERROR;
+      break;
+  }
+
+  if (status == HAL_OK)
+  {
+    /* Enable the Output compare channel */
+    TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+
+    if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+    {
+      /* Enable the main output */
+      __HAL_TIM_MOE_ENABLE(htim);
+    }
+
+    /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+    if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+    {
+      tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+      if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+      {
+        __HAL_TIM_ENABLE(htim);
+      }
+    }
+    else
+    {
+      __HAL_TIM_ENABLE(htim);
+    }
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  Stops the TIM Output Compare signal generation in DMA mode.
+  * @param  htim TIM Output Compare handle
+  * @param  Channel TIM Channel to be disabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Disable the TIM Capture/Compare 1 DMA request */
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      /* Disable the TIM Capture/Compare 2 DMA request */
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
+      break;
+    }
+
+    case TIM_CHANNEL_3:
+    {
+      /* Disable the TIM Capture/Compare 3 DMA request */
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
+      break;
+    }
+
+    case TIM_CHANNEL_4:
+    {
+      /* Disable the TIM Capture/Compare 4 interrupt */
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
+      break;
+    }
+
+    default:
+      status = HAL_ERROR;
+      break;
+  }
+
+  if (status == HAL_OK)
+  {
+    /* Disable the Output compare channel */
+    TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+
+    if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+    {
+      /* Disable the Main Output */
+      __HAL_TIM_MOE_DISABLE(htim);
+    }
+
+    /* Disable the Peripheral */
+    __HAL_TIM_DISABLE(htim);
+
+    /* Set the TIM channel state */
+    TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Exported_Functions_Group3 TIM PWM functions
+  *  @brief    TIM PWM functions
+  *
+@verbatim
+  ==============================================================================
+                          ##### TIM PWM functions #####
+  ==============================================================================
+  [..]
+    This section provides functions allowing to:
+    (+) Initialize and configure the TIM PWM.
+    (+) De-initialize the TIM PWM.
+    (+) Start the TIM PWM.
+    (+) Stop the TIM PWM.
+    (+) Start the TIM PWM and enable interrupt.
+    (+) Stop the TIM PWM and disable interrupt.
+    (+) Start the TIM PWM and enable DMA transfer.
+    (+) Stop the TIM PWM and disable DMA transfer.
+
+@endverbatim
+  * @{
+  */
+/**
+  * @brief  Initializes the TIM PWM Time Base according to the specified
+  *         parameters in the TIM_HandleTypeDef and initializes the associated handle.
+  * @note   Switching from Center Aligned counter mode to Edge counter mode (or reverse)
+  *         requires a timer reset to avoid unexpected direction
+  *         due to DIR bit readonly in center aligned mode.
+  *         Ex: call @ref HAL_TIM_PWM_DeInit() before HAL_TIM_PWM_Init()
+  * @param  htim TIM PWM handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim)
+{
+  /* Check the TIM handle allocation */
+  if (htim == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_TIM_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
+  assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
+  assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
+
+  if (htim->State == HAL_TIM_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    htim->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+    /* Reset interrupt callbacks to legacy weak callbacks */
+    TIM_ResetCallback(htim);
+
+    if (htim->PWM_MspInitCallback == NULL)
+    {
+      htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit;
+    }
+    /* Init the low level hardware : GPIO, CLOCK, NVIC */
+    htim->PWM_MspInitCallback(htim);
+#else
+    /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
+    HAL_TIM_PWM_MspInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+  }
+
+  /* Set the TIM state */
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  /* Init the base time for the PWM */
+  TIM_Base_SetConfig(htim->Instance, &htim->Init);
+
+  /* Initialize the DMA burst operation state */
+  htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
+
+  /* Initialize the TIM channels state */
+  TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
+  TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
+
+  /* Initialize the TIM state*/
+  htim->State = HAL_TIM_STATE_READY;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  DeInitializes the TIM peripheral
+  * @param  htim TIM PWM handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  /* Disable the TIM Peripheral Clock */
+  __HAL_TIM_DISABLE(htim);
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+  if (htim->PWM_MspDeInitCallback == NULL)
+  {
+    htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit;
+  }
+  /* DeInit the low level hardware */
+  htim->PWM_MspDeInitCallback(htim);
+#else
+  /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
+  HAL_TIM_PWM_MspDeInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+  /* Change the DMA burst operation state */
+  htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
+
+  /* Change the TIM channels state */
+  TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
+  TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
+
+  /* Change TIM state */
+  htim->State = HAL_TIM_STATE_RESET;
+
+  /* Release Lock */
+  __HAL_UNLOCK(htim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the TIM PWM MSP.
+  * @param  htim TIM PWM handle
+  * @retval None
+  */
+__weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_PWM_MspInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  DeInitializes TIM PWM MSP.
+  * @param  htim TIM PWM handle
+  * @retval None
+  */
+__weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_PWM_MspDeInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Starts the PWM signal generation.
+  * @param  htim TIM handle
+  * @param  Channel TIM Channels to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  uint32_t tmpsmcr;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+  /* Check the TIM channel state */
+  if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Set the TIM channel state */
+  TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+
+  /* Enable the Capture compare channel */
+  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+
+  if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+  {
+    /* Enable the main output */
+    __HAL_TIM_MOE_ENABLE(htim);
+  }
+
+  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+  if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+  {
+    tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+    if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+    {
+      __HAL_TIM_ENABLE(htim);
+    }
+  }
+  else
+  {
+    __HAL_TIM_ENABLE(htim);
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the PWM signal generation.
+  * @param  htim TIM PWM handle
+  * @param  Channel TIM Channels to be disabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+  /* Disable the Capture compare channel */
+  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+
+  if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+  {
+    /* Disable the Main Output */
+    __HAL_TIM_MOE_DISABLE(htim);
+  }
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Set the TIM channel state */
+  TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Starts the PWM signal generation in interrupt mode.
+  * @param  htim TIM PWM handle
+  * @param  Channel TIM Channel to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  uint32_t tmpsmcr;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+  /* Check the TIM channel state */
+  if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Set the TIM channel state */
+  TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Enable the TIM Capture/Compare 1 interrupt */
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      /* Enable the TIM Capture/Compare 2 interrupt */
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+      break;
+    }
+
+    case TIM_CHANNEL_3:
+    {
+      /* Enable the TIM Capture/Compare 3 interrupt */
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
+      break;
+    }
+
+    case TIM_CHANNEL_4:
+    {
+      /* Enable the TIM Capture/Compare 4 interrupt */
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
+      break;
+    }
+
+    default:
+      status = HAL_ERROR;
+      break;
+  }
+
+  if (status == HAL_OK)
+  {
+    /* Enable the Capture compare channel */
+    TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+
+    if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+    {
+      /* Enable the main output */
+      __HAL_TIM_MOE_ENABLE(htim);
+    }
+
+    /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+    if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+    {
+      tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+      if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+      {
+        __HAL_TIM_ENABLE(htim);
+      }
+    }
+    else
+    {
+      __HAL_TIM_ENABLE(htim);
+    }
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  Stops the PWM signal generation in interrupt mode.
+  * @param  htim TIM PWM handle
+  * @param  Channel TIM Channels to be disabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Disable the TIM Capture/Compare 1 interrupt */
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      /* Disable the TIM Capture/Compare 2 interrupt */
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+      break;
+    }
+
+    case TIM_CHANNEL_3:
+    {
+      /* Disable the TIM Capture/Compare 3 interrupt */
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
+      break;
+    }
+
+    case TIM_CHANNEL_4:
+    {
+      /* Disable the TIM Capture/Compare 4 interrupt */
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
+      break;
+    }
+
+    default:
+      status = HAL_ERROR;
+      break;
+  }
+
+  if (status == HAL_OK)
+  {
+    /* Disable the Capture compare channel */
+    TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+
+    if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+    {
+      /* Disable the Main Output */
+      __HAL_TIM_MOE_DISABLE(htim);
+    }
+
+    /* Disable the Peripheral */
+    __HAL_TIM_DISABLE(htim);
+
+    /* Set the TIM channel state */
+    TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  Starts the TIM PWM signal generation in DMA mode.
+  * @param  htim TIM PWM handle
+  * @param  Channel TIM Channels to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @param  pData The source Buffer address.
+  * @param  Length The length of data to be transferred from memory to TIM peripheral
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  uint32_t tmpsmcr;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+  /* Set the TIM channel state */
+  if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY)
+  {
+    return HAL_BUSY;
+  }
+  else if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY)
+  {
+    if ((pData == NULL) && (Length > 0U))
+    {
+      return HAL_ERROR;
+    }
+    else
+    {
+      TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+    }
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Set the DMA compare callbacks */
+      htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
+      htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1,
+                           Length) != HAL_OK)
+      {
+        /* Return error status */
+        return HAL_ERROR;
+      }
+
+      /* Enable the TIM Capture/Compare 1 DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      /* Set the DMA compare callbacks */
+      htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
+      htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2,
+                           Length) != HAL_OK)
+      {
+        /* Return error status */
+        return HAL_ERROR;
+      }
+      /* Enable the TIM Capture/Compare 2 DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
+      break;
+    }
+
+    case TIM_CHANNEL_3:
+    {
+      /* Set the DMA compare callbacks */
+      htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
+      htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,
+                           Length) != HAL_OK)
+      {
+        /* Return error status */
+        return HAL_ERROR;
+      }
+      /* Enable the TIM Output Capture/Compare 3 request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
+      break;
+    }
+
+    case TIM_CHANNEL_4:
+    {
+      /* Set the DMA compare callbacks */
+      htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
+      htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4,
+                           Length) != HAL_OK)
+      {
+        /* Return error status */
+        return HAL_ERROR;
+      }
+      /* Enable the TIM Capture/Compare 4 DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
+      break;
+    }
+
+    default:
+      status = HAL_ERROR;
+      break;
+  }
+
+  if (status == HAL_OK)
+  {
+    /* Enable the Capture compare channel */
+    TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+
+    if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+    {
+      /* Enable the main output */
+      __HAL_TIM_MOE_ENABLE(htim);
+    }
+
+    /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+    if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+    {
+      tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+      if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+      {
+        __HAL_TIM_ENABLE(htim);
+      }
+    }
+    else
+    {
+      __HAL_TIM_ENABLE(htim);
+    }
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  Stops the TIM PWM signal generation in DMA mode.
+  * @param  htim TIM PWM handle
+  * @param  Channel TIM Channels to be disabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Disable the TIM Capture/Compare 1 DMA request */
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      /* Disable the TIM Capture/Compare 2 DMA request */
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
+      break;
+    }
+
+    case TIM_CHANNEL_3:
+    {
+      /* Disable the TIM Capture/Compare 3 DMA request */
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
+      break;
+    }
+
+    case TIM_CHANNEL_4:
+    {
+      /* Disable the TIM Capture/Compare 4 interrupt */
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
+      break;
+    }
+
+    default:
+      status = HAL_ERROR;
+      break;
+  }
+
+  if (status == HAL_OK)
+  {
+    /* Disable the Capture compare channel */
+    TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+
+    if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+    {
+      /* Disable the Main Output */
+      __HAL_TIM_MOE_DISABLE(htim);
+    }
+
+    /* Disable the Peripheral */
+    __HAL_TIM_DISABLE(htim);
+
+    /* Set the TIM channel state */
+    TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Exported_Functions_Group4 TIM Input Capture functions
+  *  @brief    TIM Input Capture functions
+  *
+@verbatim
+  ==============================================================================
+              ##### TIM Input Capture functions #####
+  ==============================================================================
+ [..]
+   This section provides functions allowing to:
+   (+) Initialize and configure the TIM Input Capture.
+   (+) De-initialize the TIM Input Capture.
+   (+) Start the TIM Input Capture.
+   (+) Stop the TIM Input Capture.
+   (+) Start the TIM Input Capture and enable interrupt.
+   (+) Stop the TIM Input Capture and disable interrupt.
+   (+) Start the TIM Input Capture and enable DMA transfer.
+   (+) Stop the TIM Input Capture and disable DMA transfer.
+
+@endverbatim
+  * @{
+  */
+/**
+  * @brief  Initializes the TIM Input Capture Time base according to the specified
+  *         parameters in the TIM_HandleTypeDef and initializes the associated handle.
+  * @note   Switching from Center Aligned counter mode to Edge counter mode (or reverse)
+  *         requires a timer reset to avoid unexpected direction
+  *         due to DIR bit readonly in center aligned mode.
+  *         Ex: call @ref HAL_TIM_IC_DeInit() before HAL_TIM_IC_Init()
+  * @param  htim TIM Input Capture handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim)
+{
+  /* Check the TIM handle allocation */
+  if (htim == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_TIM_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
+  assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
+  assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
+
+  if (htim->State == HAL_TIM_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    htim->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+    /* Reset interrupt callbacks to legacy weak callbacks */
+    TIM_ResetCallback(htim);
+
+    if (htim->IC_MspInitCallback == NULL)
+    {
+      htim->IC_MspInitCallback = HAL_TIM_IC_MspInit;
+    }
+    /* Init the low level hardware : GPIO, CLOCK, NVIC */
+    htim->IC_MspInitCallback(htim);
+#else
+    /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
+    HAL_TIM_IC_MspInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+  }
+
+  /* Set the TIM state */
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  /* Init the base time for the input capture */
+  TIM_Base_SetConfig(htim->Instance, &htim->Init);
+
+  /* Initialize the DMA burst operation state */
+  htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
+
+  /* Initialize the TIM channels state */
+  TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
+  TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
+
+  /* Initialize the TIM state*/
+  htim->State = HAL_TIM_STATE_READY;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  DeInitializes the TIM peripheral
+  * @param  htim TIM Input Capture handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  /* Disable the TIM Peripheral Clock */
+  __HAL_TIM_DISABLE(htim);
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+  if (htim->IC_MspDeInitCallback == NULL)
+  {
+    htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit;
+  }
+  /* DeInit the low level hardware */
+  htim->IC_MspDeInitCallback(htim);
+#else
+  /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
+  HAL_TIM_IC_MspDeInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+  /* Change the DMA burst operation state */
+  htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
+
+  /* Change the TIM channels state */
+  TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
+  TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
+
+  /* Change TIM state */
+  htim->State = HAL_TIM_STATE_RESET;
+
+  /* Release Lock */
+  __HAL_UNLOCK(htim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the TIM Input Capture MSP.
+  * @param  htim TIM Input Capture handle
+  * @retval None
+  */
+__weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_IC_MspInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  DeInitializes TIM Input Capture MSP.
+  * @param  htim TIM handle
+  * @retval None
+  */
+__weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_IC_MspDeInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Starts the TIM Input Capture measurement.
+  * @param  htim TIM Input Capture handle
+  * @param  Channel TIM Channels to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  uint32_t tmpsmcr;
+  HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel);
+  HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+  /* Check the TIM channel state */
+  if ((channel_state != HAL_TIM_CHANNEL_STATE_READY)
+      || (complementary_channel_state != HAL_TIM_CHANNEL_STATE_READY))
+  {
+    return HAL_ERROR;
+  }
+
+  /* Set the TIM channel state */
+  TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+  TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+
+  /* Enable the Input Capture channel */
+  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+
+  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+  if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+  {
+    tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+    if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+    {
+      __HAL_TIM_ENABLE(htim);
+    }
+  }
+  else
+  {
+    __HAL_TIM_ENABLE(htim);
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM Input Capture measurement.
+  * @param  htim TIM Input Capture handle
+  * @param  Channel TIM Channels to be disabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+  /* Disable the Input Capture channel */
+  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Set the TIM channel state */
+  TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+  TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Starts the TIM Input Capture measurement in interrupt mode.
+  * @param  htim TIM Input Capture handle
+  * @param  Channel TIM Channels to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  uint32_t tmpsmcr;
+
+  HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel);
+  HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+  /* Check the TIM channel state */
+  if ((channel_state != HAL_TIM_CHANNEL_STATE_READY)
+      || (complementary_channel_state != HAL_TIM_CHANNEL_STATE_READY))
+  {
+    return HAL_ERROR;
+  }
+
+  /* Set the TIM channel state */
+  TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+  TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Enable the TIM Capture/Compare 1 interrupt */
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      /* Enable the TIM Capture/Compare 2 interrupt */
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+      break;
+    }
+
+    case TIM_CHANNEL_3:
+    {
+      /* Enable the TIM Capture/Compare 3 interrupt */
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
+      break;
+    }
+
+    case TIM_CHANNEL_4:
+    {
+      /* Enable the TIM Capture/Compare 4 interrupt */
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
+      break;
+    }
+
+    default:
+      status = HAL_ERROR;
+      break;
+  }
+
+  if (status == HAL_OK)
+  {
+    /* Enable the Input Capture channel */
+    TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+
+    /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+    if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+    {
+      tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+      if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+      {
+        __HAL_TIM_ENABLE(htim);
+      }
+    }
+    else
+    {
+      __HAL_TIM_ENABLE(htim);
+    }
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  Stops the TIM Input Capture measurement in interrupt mode.
+  * @param  htim TIM Input Capture handle
+  * @param  Channel TIM Channels to be disabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Disable the TIM Capture/Compare 1 interrupt */
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      /* Disable the TIM Capture/Compare 2 interrupt */
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+      break;
+    }
+
+    case TIM_CHANNEL_3:
+    {
+      /* Disable the TIM Capture/Compare 3 interrupt */
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
+      break;
+    }
+
+    case TIM_CHANNEL_4:
+    {
+      /* Disable the TIM Capture/Compare 4 interrupt */
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
+      break;
+    }
+
+    default:
+      status = HAL_ERROR;
+      break;
+  }
+
+  if (status == HAL_OK)
+  {
+    /* Disable the Input Capture channel */
+    TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+
+    /* Disable the Peripheral */
+    __HAL_TIM_DISABLE(htim);
+
+    /* Set the TIM channel state */
+    TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+    TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  Starts the TIM Input Capture measurement in DMA mode.
+  * @param  htim TIM Input Capture handle
+  * @param  Channel TIM Channels to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @param  pData The destination Buffer address.
+  * @param  Length The length of data to be transferred from TIM peripheral to memory.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  uint32_t tmpsmcr;
+
+  HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel);
+  HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+  assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
+
+  /* Set the TIM channel state */
+  if ((channel_state == HAL_TIM_CHANNEL_STATE_BUSY)
+      || (complementary_channel_state == HAL_TIM_CHANNEL_STATE_BUSY))
+  {
+    return HAL_BUSY;
+  }
+  else if ((channel_state == HAL_TIM_CHANNEL_STATE_READY)
+           && (complementary_channel_state == HAL_TIM_CHANNEL_STATE_READY))
+  {
+    if ((pData == NULL) && (Length > 0U))
+    {
+      return HAL_ERROR;
+    }
+    else
+    {
+      TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+      TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+    }
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  /* Enable the Input Capture channel */
+  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Set the DMA capture callbacks */
+      htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
+      htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData,
+                           Length) != HAL_OK)
+      {
+        /* Return error status */
+        return HAL_ERROR;
+      }
+      /* Enable the TIM Capture/Compare 1 DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      /* Set the DMA capture callbacks */
+      htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
+      htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData,
+                           Length) != HAL_OK)
+      {
+        /* Return error status */
+        return HAL_ERROR;
+      }
+      /* Enable the TIM Capture/Compare 2  DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
+      break;
+    }
+
+    case TIM_CHANNEL_3:
+    {
+      /* Set the DMA capture callbacks */
+      htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;
+      htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData,
+                           Length) != HAL_OK)
+      {
+        /* Return error status */
+        return HAL_ERROR;
+      }
+      /* Enable the TIM Capture/Compare 3  DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
+      break;
+    }
+
+    case TIM_CHANNEL_4:
+    {
+      /* Set the DMA capture callbacks */
+      htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;
+      htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData,
+                           Length) != HAL_OK)
+      {
+        /* Return error status */
+        return HAL_ERROR;
+      }
+      /* Enable the TIM Capture/Compare 4  DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
+      break;
+    }
+
+    default:
+      status = HAL_ERROR;
+      break;
+  }
+
+  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+  if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+  {
+    tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+    if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+    {
+      __HAL_TIM_ENABLE(htim);
+    }
+  }
+  else
+  {
+    __HAL_TIM_ENABLE(htim);
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  Stops the TIM Input Capture measurement in DMA mode.
+  * @param  htim TIM Input Capture handle
+  * @param  Channel TIM Channels to be disabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+  assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
+
+  /* Disable the Input Capture channel */
+  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Disable the TIM Capture/Compare 1 DMA request */
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      /* Disable the TIM Capture/Compare 2 DMA request */
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
+      break;
+    }
+
+    case TIM_CHANNEL_3:
+    {
+      /* Disable the TIM Capture/Compare 3  DMA request */
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
+      break;
+    }
+
+    case TIM_CHANNEL_4:
+    {
+      /* Disable the TIM Capture/Compare 4  DMA request */
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
+      break;
+    }
+
+    default:
+      status = HAL_ERROR;
+      break;
+  }
+
+  if (status == HAL_OK)
+  {
+    /* Disable the Peripheral */
+    __HAL_TIM_DISABLE(htim);
+
+    /* Set the TIM channel state */
+    TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+    TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+  }
+
+  /* Return function status */
+  return status;
+}
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Exported_Functions_Group5 TIM One Pulse functions
+  *  @brief    TIM One Pulse functions
+  *
+@verbatim
+  ==============================================================================
+                        ##### TIM One Pulse functions #####
+  ==============================================================================
+  [..]
+    This section provides functions allowing to:
+    (+) Initialize and configure the TIM One Pulse.
+    (+) De-initialize the TIM One Pulse.
+    (+) Start the TIM One Pulse.
+    (+) Stop the TIM One Pulse.
+    (+) Start the TIM One Pulse and enable interrupt.
+    (+) Stop the TIM One Pulse and disable interrupt.
+    (+) Start the TIM One Pulse and enable DMA transfer.
+    (+) Stop the TIM One Pulse and disable DMA transfer.
+
+@endverbatim
+  * @{
+  */
+/**
+  * @brief  Initializes the TIM One Pulse Time Base according to the specified
+  *         parameters in the TIM_HandleTypeDef and initializes the associated handle.
+  * @note   Switching from Center Aligned counter mode to Edge counter mode (or reverse)
+  *         requires a timer reset to avoid unexpected direction
+  *         due to DIR bit readonly in center aligned mode.
+  *         Ex: call @ref HAL_TIM_OnePulse_DeInit() before HAL_TIM_OnePulse_Init()
+  * @note   When the timer instance is initialized in One Pulse mode, timer
+  *         channels 1 and channel 2 are reserved and cannot be used for other
+  *         purpose.
+  * @param  htim TIM One Pulse handle
+  * @param  OnePulseMode Select the One pulse mode.
+  *         This parameter can be one of the following values:
+  *            @arg TIM_OPMODE_SINGLE: Only one pulse will be generated.
+  *            @arg TIM_OPMODE_REPETITIVE: Repetitive pulses will be generated.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode)
+{
+  /* Check the TIM handle allocation */
+  if (htim == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_TIM_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
+  assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
+  assert_param(IS_TIM_OPM_MODE(OnePulseMode));
+  assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
+
+  if (htim->State == HAL_TIM_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    htim->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+    /* Reset interrupt callbacks to legacy weak callbacks */
+    TIM_ResetCallback(htim);
+
+    if (htim->OnePulse_MspInitCallback == NULL)
+    {
+      htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit;
+    }
+    /* Init the low level hardware : GPIO, CLOCK, NVIC */
+    htim->OnePulse_MspInitCallback(htim);
+#else
+    /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
+    HAL_TIM_OnePulse_MspInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+  }
+
+  /* Set the TIM state */
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  /* Configure the Time base in the One Pulse Mode */
+  TIM_Base_SetConfig(htim->Instance, &htim->Init);
+
+  /* Reset the OPM Bit */
+  htim->Instance->CR1 &= ~TIM_CR1_OPM;
+
+  /* Configure the OPM Mode */
+  htim->Instance->CR1 |= OnePulseMode;
+
+  /* Initialize the DMA burst operation state */
+  htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
+
+  /* Initialize the TIM channels state */
+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+
+  /* Initialize the TIM state*/
+  htim->State = HAL_TIM_STATE_READY;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  DeInitializes the TIM One Pulse
+  * @param  htim TIM One Pulse handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  /* Disable the TIM Peripheral Clock */
+  __HAL_TIM_DISABLE(htim);
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+  if (htim->OnePulse_MspDeInitCallback == NULL)
+  {
+    htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit;
+  }
+  /* DeInit the low level hardware */
+  htim->OnePulse_MspDeInitCallback(htim);
+#else
+  /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
+  HAL_TIM_OnePulse_MspDeInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+  /* Change the DMA burst operation state */
+  htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
+
+  /* Set the TIM channel state */
+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
+  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
+  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
+
+  /* Change TIM state */
+  htim->State = HAL_TIM_STATE_RESET;
+
+  /* Release Lock */
+  __HAL_UNLOCK(htim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the TIM One Pulse MSP.
+  * @param  htim TIM One Pulse handle
+  * @retval None
+  */
+__weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_OnePulse_MspInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  DeInitializes TIM One Pulse MSP.
+  * @param  htim TIM One Pulse handle
+  * @retval None
+  */
+__weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_OnePulse_MspDeInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Starts the TIM One Pulse signal generation.
+  * @note Though OutputChannel parameter is deprecated and ignored by the function
+  *        it has been kept to avoid HAL_TIM API compatibility break.
+  * @note The pulse output channel is determined when calling
+  *       @ref HAL_TIM_OnePulse_ConfigChannel().
+  * @param  htim TIM One Pulse handle
+  * @param  OutputChannel See note above
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
+{
+  HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
+  HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
+  HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
+  HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
+
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(OutputChannel);
+
+  /* Check the TIM channels state */
+  if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+      || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
+      || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+      || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
+  {
+    return HAL_ERROR;
+  }
+
+  /* Set the TIM channels state */
+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+
+  /* Enable the Capture compare and the Input Capture channels
+    (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
+    if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
+    if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
+    whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
+
+    No need to enable the counter, it's enabled automatically by hardware
+    (the counter starts in response to a stimulus and generate a pulse */
+
+  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+
+  if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+  {
+    /* Enable the main output */
+    __HAL_TIM_MOE_ENABLE(htim);
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM One Pulse signal generation.
+  * @note Though OutputChannel parameter is deprecated and ignored by the function
+  *        it has been kept to avoid HAL_TIM API compatibility break.
+  * @note The pulse output channel is determined when calling
+  *       @ref HAL_TIM_OnePulse_ConfigChannel().
+  * @param  htim TIM One Pulse handle
+  * @param  OutputChannel See note above
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(OutputChannel);
+
+  /* Disable the Capture compare and the Input Capture channels
+  (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
+  if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
+  if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
+  whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
+
+  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+
+  if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+  {
+    /* Disable the Main Output */
+    __HAL_TIM_MOE_DISABLE(htim);
+  }
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Set the TIM channels state */
+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Starts the TIM One Pulse signal generation in interrupt mode.
+  * @note Though OutputChannel parameter is deprecated and ignored by the function
+  *        it has been kept to avoid HAL_TIM API compatibility break.
+  * @note The pulse output channel is determined when calling
+  *       @ref HAL_TIM_OnePulse_ConfigChannel().
+  * @param  htim TIM One Pulse handle
+  * @param  OutputChannel See note above
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
+{
+  HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
+  HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
+  HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
+  HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
+
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(OutputChannel);
+
+  /* Check the TIM channels state */
+  if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+      || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
+      || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+      || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
+  {
+    return HAL_ERROR;
+  }
+
+  /* Set the TIM channels state */
+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+
+  /* Enable the Capture compare and the Input Capture channels
+    (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
+    if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
+    if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
+    whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
+
+    No need to enable the counter, it's enabled automatically by hardware
+    (the counter starts in response to a stimulus and generate a pulse */
+
+  /* Enable the TIM Capture/Compare 1 interrupt */
+  __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+
+  /* Enable the TIM Capture/Compare 2 interrupt */
+  __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+
+  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+
+  if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+  {
+    /* Enable the main output */
+    __HAL_TIM_MOE_ENABLE(htim);
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM One Pulse signal generation in interrupt mode.
+  * @note Though OutputChannel parameter is deprecated and ignored by the function
+  *        it has been kept to avoid HAL_TIM API compatibility break.
+  * @note The pulse output channel is determined when calling
+  *       @ref HAL_TIM_OnePulse_ConfigChannel().
+  * @param  htim TIM One Pulse handle
+  * @param  OutputChannel See note above
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(OutputChannel);
+
+  /* Disable the TIM Capture/Compare 1 interrupt */
+  __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+
+  /* Disable the TIM Capture/Compare 2 interrupt */
+  __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+
+  /* Disable the Capture compare and the Input Capture channels
+  (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
+  if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
+  if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
+  whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
+  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+
+  if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+  {
+    /* Disable the Main Output */
+    __HAL_TIM_MOE_DISABLE(htim);
+  }
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Set the TIM channels state */
+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Exported_Functions_Group6 TIM Encoder functions
+  *  @brief    TIM Encoder functions
+  *
+@verbatim
+  ==============================================================================
+                          ##### TIM Encoder functions #####
+  ==============================================================================
+  [..]
+    This section provides functions allowing to:
+    (+) Initialize and configure the TIM Encoder.
+    (+) De-initialize the TIM Encoder.
+    (+) Start the TIM Encoder.
+    (+) Stop the TIM Encoder.
+    (+) Start the TIM Encoder and enable interrupt.
+    (+) Stop the TIM Encoder and disable interrupt.
+    (+) Start the TIM Encoder and enable DMA transfer.
+    (+) Stop the TIM Encoder and disable DMA transfer.
+
+@endverbatim
+  * @{
+  */
+/**
+  * @brief  Initializes the TIM Encoder Interface and initialize the associated handle.
+  * @note   Switching from Center Aligned counter mode to Edge counter mode (or reverse)
+  *         requires a timer reset to avoid unexpected direction
+  *         due to DIR bit readonly in center aligned mode.
+  *         Ex: call @ref HAL_TIM_Encoder_DeInit() before HAL_TIM_Encoder_Init()
+  * @note   Encoder mode and External clock mode 2 are not compatible and must not be selected together
+  *         Ex: A call for @ref HAL_TIM_Encoder_Init will erase the settings of @ref HAL_TIM_ConfigClockSource
+  *         using TIM_CLOCKSOURCE_ETRMODE2 and vice versa
+  * @note   When the timer instance is initialized in Encoder mode, timer
+  *         channels 1 and channel 2 are reserved and cannot be used for other
+  *         purpose.
+  * @param  htim TIM Encoder Interface handle
+  * @param  sConfig TIM Encoder Interface configuration structure
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim,  TIM_Encoder_InitTypeDef *sConfig)
+{
+  uint32_t tmpsmcr;
+  uint32_t tmpccmr1;
+  uint32_t tmpccer;
+
+  /* Check the TIM handle allocation */
+  if (htim == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
+  assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
+  assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
+  assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode));
+  assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection));
+  assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection));
+  assert_param(IS_TIM_ENCODERINPUT_POLARITY(sConfig->IC1Polarity));
+  assert_param(IS_TIM_ENCODERINPUT_POLARITY(sConfig->IC2Polarity));
+  assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
+  assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler));
+  assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
+  assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter));
+
+  if (htim->State == HAL_TIM_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    htim->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+    /* Reset interrupt callbacks to legacy weak callbacks */
+    TIM_ResetCallback(htim);
+
+    if (htim->Encoder_MspInitCallback == NULL)
+    {
+      htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit;
+    }
+    /* Init the low level hardware : GPIO, CLOCK, NVIC */
+    htim->Encoder_MspInitCallback(htim);
+#else
+    /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
+    HAL_TIM_Encoder_MspInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+  }
+
+  /* Set the TIM state */
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  /* Reset the SMS and ECE bits */
+  htim->Instance->SMCR &= ~(TIM_SMCR_SMS | TIM_SMCR_ECE);
+
+  /* Configure the Time base in the Encoder Mode */
+  TIM_Base_SetConfig(htim->Instance, &htim->Init);
+
+  /* Get the TIMx SMCR register value */
+  tmpsmcr = htim->Instance->SMCR;
+
+  /* Get the TIMx CCMR1 register value */
+  tmpccmr1 = htim->Instance->CCMR1;
+
+  /* Get the TIMx CCER register value */
+  tmpccer = htim->Instance->CCER;
+
+  /* Set the encoder Mode */
+  tmpsmcr |= sConfig->EncoderMode;
+
+  /* Select the Capture Compare 1 and the Capture Compare 2 as input */
+  tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S);
+  tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8U));
+
+  /* Set the Capture Compare 1 and the Capture Compare 2 prescalers and filters */
+  tmpccmr1 &= ~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC);
+  tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F);
+  tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8U);
+  tmpccmr1 |= (sConfig->IC1Filter << 4U) | (sConfig->IC2Filter << 12U);
+
+  /* Set the TI1 and the TI2 Polarities */
+  tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC2P);
+  tmpccer &= ~(TIM_CCER_CC1NP | TIM_CCER_CC2NP);
+  tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4U);
+
+  /* Write to TIMx SMCR */
+  htim->Instance->SMCR = tmpsmcr;
+
+  /* Write to TIMx CCMR1 */
+  htim->Instance->CCMR1 = tmpccmr1;
+
+  /* Write to TIMx CCER */
+  htim->Instance->CCER = tmpccer;
+
+  /* Initialize the DMA burst operation state */
+  htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
+
+  /* Set the TIM channels state */
+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+
+  /* Initialize the TIM state*/
+  htim->State = HAL_TIM_STATE_READY;
+
+  return HAL_OK;
+}
+
+
+/**
+  * @brief  DeInitializes the TIM Encoder interface
+  * @param  htim TIM Encoder Interface handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  /* Disable the TIM Peripheral Clock */
+  __HAL_TIM_DISABLE(htim);
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+  if (htim->Encoder_MspDeInitCallback == NULL)
+  {
+    htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit;
+  }
+  /* DeInit the low level hardware */
+  htim->Encoder_MspDeInitCallback(htim);
+#else
+  /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
+  HAL_TIM_Encoder_MspDeInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+  /* Change the DMA burst operation state */
+  htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
+
+  /* Set the TIM channels state */
+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
+  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
+  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
+
+  /* Change TIM state */
+  htim->State = HAL_TIM_STATE_RESET;
+
+  /* Release Lock */
+  __HAL_UNLOCK(htim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the TIM Encoder Interface MSP.
+  * @param  htim TIM Encoder Interface handle
+  * @retval None
+  */
+__weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_Encoder_MspInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  DeInitializes TIM Encoder Interface MSP.
+  * @param  htim TIM Encoder Interface handle
+  * @retval None
+  */
+__weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_Encoder_MspDeInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Starts the TIM Encoder Interface.
+  * @param  htim TIM Encoder Interface handle
+  * @param  Channel TIM Channels to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
+  HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
+  HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
+  HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
+
+  /* Check the parameters */
+  assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
+
+  /* Set the TIM channel(s) state */
+  if (Channel == TIM_CHANNEL_1)
+  {
+    if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+        || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY))
+    {
+      return HAL_ERROR;
+    }
+    else
+    {
+      TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+      TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+    }
+  }
+  else if (Channel == TIM_CHANNEL_2)
+  {
+    if ((channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
+        || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
+    {
+      return HAL_ERROR;
+    }
+    else
+    {
+      TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+      TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+    }
+  }
+  else
+  {
+    if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+        || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
+        || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+        || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
+    {
+      return HAL_ERROR;
+    }
+    else
+    {
+      TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+      TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+      TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+      TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+    }
+  }
+
+  /* Enable the encoder interface channels */
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+      break;
+    }
+
+    default :
+    {
+      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+      break;
+    }
+  }
+  /* Enable the Peripheral */
+  __HAL_TIM_ENABLE(htim);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM Encoder Interface.
+  * @param  htim TIM Encoder Interface handle
+  * @param  Channel TIM Channels to be disabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
+
+  /* Disable the Input Capture channels 1 and 2
+    (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+      break;
+    }
+
+    default :
+    {
+      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+      break;
+    }
+  }
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Set the TIM channel(s) state */
+  if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2))
+  {
+    TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+    TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+  }
+  else
+  {
+    TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+    TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+    TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+    TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Starts the TIM Encoder Interface in interrupt mode.
+  * @param  htim TIM Encoder Interface handle
+  * @param  Channel TIM Channels to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
+  HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
+  HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
+  HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
+
+  /* Check the parameters */
+  assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
+
+  /* Set the TIM channel(s) state */
+  if (Channel == TIM_CHANNEL_1)
+  {
+    if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+        || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY))
+    {
+      return HAL_ERROR;
+    }
+    else
+    {
+      TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+      TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+    }
+  }
+  else if (Channel == TIM_CHANNEL_2)
+  {
+    if ((channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
+        || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
+    {
+      return HAL_ERROR;
+    }
+    else
+    {
+      TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+      TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+    }
+  }
+  else
+  {
+    if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+        || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
+        || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+        || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
+    {
+      return HAL_ERROR;
+    }
+    else
+    {
+      TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+      TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+      TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+      TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+    }
+  }
+
+  /* Enable the encoder interface channels */
+  /* Enable the capture compare Interrupts 1 and/or 2 */
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+      break;
+    }
+
+    default :
+    {
+      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+      break;
+    }
+  }
+
+  /* Enable the Peripheral */
+  __HAL_TIM_ENABLE(htim);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM Encoder Interface in interrupt mode.
+  * @param  htim TIM Encoder Interface handle
+  * @param  Channel TIM Channels to be disabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
+
+  /* Disable the Input Capture channels 1 and 2
+    (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
+  if (Channel == TIM_CHANNEL_1)
+  {
+    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+
+    /* Disable the capture compare Interrupts 1 */
+    __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+  }
+  else if (Channel == TIM_CHANNEL_2)
+  {
+    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+
+    /* Disable the capture compare Interrupts 2 */
+    __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+  }
+  else
+  {
+    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+
+    /* Disable the capture compare Interrupts 1 and 2 */
+    __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+    __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+  }
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Set the TIM channel(s) state */
+  if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2))
+  {
+    TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+    TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+  }
+  else
+  {
+    TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+    TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+    TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+    TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Starts the TIM Encoder Interface in DMA mode.
+  * @param  htim TIM Encoder Interface handle
+  * @param  Channel TIM Channels to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
+  * @param  pData1 The destination Buffer address for IC1.
+  * @param  pData2 The destination Buffer address for IC2.
+  * @param  Length The length of data to be transferred from TIM peripheral to memory.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1,
+                                            uint32_t *pData2, uint16_t Length)
+{
+  HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
+  HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
+  HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
+  HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
+
+  /* Check the parameters */
+  assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
+
+  /* Set the TIM channel(s) state */
+  if (Channel == TIM_CHANNEL_1)
+  {
+    if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)
+        || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY))
+    {
+      return HAL_BUSY;
+    }
+    else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY)
+             && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY))
+    {
+      if ((pData1 == NULL) && (Length > 0U))
+      {
+        return HAL_ERROR;
+      }
+      else
+      {
+        TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+        TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+      }
+    }
+    else
+    {
+      return HAL_ERROR;
+    }
+  }
+  else if (Channel == TIM_CHANNEL_2)
+  {
+    if ((channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY)
+        || (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY))
+    {
+      return HAL_BUSY;
+    }
+    else if ((channel_2_state == HAL_TIM_CHANNEL_STATE_READY)
+             && (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_READY))
+    {
+      if ((pData2 == NULL) && (Length > 0U))
+      {
+        return HAL_ERROR;
+      }
+      else
+      {
+        TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+        TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+      }
+    }
+    else
+    {
+      return HAL_ERROR;
+    }
+  }
+  else
+  {
+    if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)
+        || (channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY)
+        || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)
+        || (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY))
+    {
+      return HAL_BUSY;
+    }
+    else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY)
+             && (channel_2_state == HAL_TIM_CHANNEL_STATE_READY)
+             && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY)
+             && (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_READY))
+    {
+      if ((((pData1 == NULL) || (pData2 == NULL))) && (Length > 0U))
+      {
+        return HAL_ERROR;
+      }
+      else
+      {
+        TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+        TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+        TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+        TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+      }
+    }
+    else
+    {
+      return HAL_ERROR;
+    }
+  }
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Set the DMA capture callbacks */
+      htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
+      htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1,
+                           Length) != HAL_OK)
+      {
+        /* Return error status */
+        return HAL_ERROR;
+      }
+      /* Enable the TIM Input Capture DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
+
+      /* Enable the Capture compare channel */
+      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+
+      /* Enable the Peripheral */
+      __HAL_TIM_ENABLE(htim);
+
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      /* Set the DMA capture callbacks */
+      htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
+      htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError;
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2,
+                           Length) != HAL_OK)
+      {
+        /* Return error status */
+        return HAL_ERROR;
+      }
+      /* Enable the TIM Input Capture  DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
+
+      /* Enable the Capture compare channel */
+      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+
+      /* Enable the Peripheral */
+      __HAL_TIM_ENABLE(htim);
+
+      break;
+    }
+
+    default:
+    {
+      /* Set the DMA capture callbacks */
+      htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
+      htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1,
+                           Length) != HAL_OK)
+      {
+        /* Return error status */
+        return HAL_ERROR;
+      }
+
+      /* Set the DMA capture callbacks */
+      htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
+      htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2,
+                           Length) != HAL_OK)
+      {
+        /* Return error status */
+        return HAL_ERROR;
+      }
+
+      /* Enable the TIM Input Capture  DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
+      /* Enable the TIM Input Capture  DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
+
+      /* Enable the Capture compare channel */
+      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+
+      /* Enable the Peripheral */
+      __HAL_TIM_ENABLE(htim);
+
+      break;
+    }
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM Encoder Interface in DMA mode.
+  * @param  htim TIM Encoder Interface handle
+  * @param  Channel TIM Channels to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
+
+  /* Disable the Input Capture channels 1 and 2
+    (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
+  if (Channel == TIM_CHANNEL_1)
+  {
+    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+
+    /* Disable the capture compare DMA Request 1 */
+    __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
+    (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
+  }
+  else if (Channel == TIM_CHANNEL_2)
+  {
+    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+
+    /* Disable the capture compare DMA Request 2 */
+    __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
+    (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
+  }
+  else
+  {
+    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+
+    /* Disable the capture compare DMA Request 1 and 2 */
+    __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
+    __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
+    (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
+    (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
+  }
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Set the TIM channel(s) state */
+  if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2))
+  {
+    TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+    TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+  }
+  else
+  {
+    TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+    TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+    TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+    TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+/** @defgroup TIM_Exported_Functions_Group7 TIM IRQ handler management
+  *  @brief    TIM IRQ handler management
+  *
+@verbatim
+  ==============================================================================
+                        ##### IRQ handler management #####
+  ==============================================================================
+  [..]
+    This section provides Timer IRQ handler function.
+
+@endverbatim
+  * @{
+  */
+/**
+  * @brief  This function handles TIM interrupts requests.
+  * @param  htim TIM  handle
+  * @retval None
+  */
+void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
+{
+  /* Capture compare 1 event */
+  if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET)
+  {
+    if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) != RESET)
+    {
+      {
+        __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1);
+        htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
+
+        /* Input capture event */
+        if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U)
+        {
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+          htim->IC_CaptureCallback(htim);
+#else
+          HAL_TIM_IC_CaptureCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+        }
+        /* Output compare event */
+        else
+        {
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+          htim->OC_DelayElapsedCallback(htim);
+          htim->PWM_PulseFinishedCallback(htim);
+#else
+          HAL_TIM_OC_DelayElapsedCallback(htim);
+          HAL_TIM_PWM_PulseFinishedCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+        }
+        htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+      }
+    }
+  }
+  /* Capture compare 2 event */
+  if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET)
+  {
+    if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) != RESET)
+    {
+      __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2);
+      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
+      /* Input capture event */
+      if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U)
+      {
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+        htim->IC_CaptureCallback(htim);
+#else
+        HAL_TIM_IC_CaptureCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+      }
+      /* Output compare event */
+      else
+      {
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+        htim->OC_DelayElapsedCallback(htim);
+        htim->PWM_PulseFinishedCallback(htim);
+#else
+        HAL_TIM_OC_DelayElapsedCallback(htim);
+        HAL_TIM_PWM_PulseFinishedCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+      }
+      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+    }
+  }
+  /* Capture compare 3 event */
+  if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET)
+  {
+    if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) != RESET)
+    {
+      __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3);
+      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
+      /* Input capture event */
+      if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U)
+      {
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+        htim->IC_CaptureCallback(htim);
+#else
+        HAL_TIM_IC_CaptureCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+      }
+      /* Output compare event */
+      else
+      {
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+        htim->OC_DelayElapsedCallback(htim);
+        htim->PWM_PulseFinishedCallback(htim);
+#else
+        HAL_TIM_OC_DelayElapsedCallback(htim);
+        HAL_TIM_PWM_PulseFinishedCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+      }
+      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+    }
+  }
+  /* Capture compare 4 event */
+  if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET)
+  {
+    if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) != RESET)
+    {
+      __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4);
+      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
+      /* Input capture event */
+      if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U)
+      {
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+        htim->IC_CaptureCallback(htim);
+#else
+        HAL_TIM_IC_CaptureCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+      }
+      /* Output compare event */
+      else
+      {
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+        htim->OC_DelayElapsedCallback(htim);
+        htim->PWM_PulseFinishedCallback(htim);
+#else
+        HAL_TIM_OC_DelayElapsedCallback(htim);
+        HAL_TIM_PWM_PulseFinishedCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+      }
+      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+    }
+  }
+  /* TIM Update event */
+  if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET)
+  {
+    if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) != RESET)
+    {
+      __HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE);
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+      htim->PeriodElapsedCallback(htim);
+#else
+      HAL_TIM_PeriodElapsedCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+    }
+  }
+  /* TIM Break input event */
+  if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET)
+  {
+    if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) != RESET)
+    {
+      __HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK);
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+      htim->BreakCallback(htim);
+#else
+      HAL_TIMEx_BreakCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+    }
+  }
+  /* TIM Trigger detection event */
+  if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET)
+  {
+    if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) != RESET)
+    {
+      __HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER);
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+      htim->TriggerCallback(htim);
+#else
+      HAL_TIM_TriggerCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+    }
+  }
+  /* TIM commutation event */
+  if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET)
+  {
+    if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_COM) != RESET)
+    {
+      __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM);
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+      htim->CommutationCallback(htim);
+#else
+      HAL_TIMEx_CommutCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+    }
+  }
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Exported_Functions_Group8 TIM Peripheral Control functions
+  *  @brief    TIM Peripheral Control functions
+  *
+@verbatim
+  ==============================================================================
+                   ##### Peripheral Control functions #####
+  ==============================================================================
+ [..]
+   This section provides functions allowing to:
+      (+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode.
+      (+) Configure External Clock source.
+      (+) Configure Complementary channels, break features and dead time.
+      (+) Configure Master and the Slave synchronization.
+      (+) Configure the DMA Burst Mode.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initializes the TIM Output Compare Channels according to the specified
+  *         parameters in the TIM_OC_InitTypeDef.
+  * @param  htim TIM Output Compare handle
+  * @param  sConfig TIM Output Compare configuration structure
+  * @param  Channel TIM Channels to configure
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim,
+                                           TIM_OC_InitTypeDef *sConfig,
+                                           uint32_t Channel)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CHANNELS(Channel));
+  assert_param(IS_TIM_OC_MODE(sConfig->OCMode));
+  assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
+
+  /* Process Locked */
+  __HAL_LOCK(htim);
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
+
+      /* Configure the TIM Channel 1 in Output Compare */
+      TIM_OC1_SetConfig(htim->Instance, sConfig);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+
+      /* Configure the TIM Channel 2 in Output Compare */
+      TIM_OC2_SetConfig(htim->Instance, sConfig);
+      break;
+    }
+
+    case TIM_CHANNEL_3:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
+
+      /* Configure the TIM Channel 3 in Output Compare */
+      TIM_OC3_SetConfig(htim->Instance, sConfig);
+      break;
+    }
+
+    case TIM_CHANNEL_4:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
+
+      /* Configure the TIM Channel 4 in Output Compare */
+      TIM_OC4_SetConfig(htim->Instance, sConfig);
+      break;
+    }
+
+    default:
+      status = HAL_ERROR;
+      break;
+  }
+
+  __HAL_UNLOCK(htim);
+
+  return status;
+}
+
+/**
+  * @brief  Initializes the TIM Input Capture Channels according to the specified
+  *         parameters in the TIM_IC_InitTypeDef.
+  * @param  htim TIM IC handle
+  * @param  sConfig TIM Input Capture configuration structure
+  * @param  Channel TIM Channel to configure
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef *sConfig, uint32_t Channel)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_IC_POLARITY(sConfig->ICPolarity));
+  assert_param(IS_TIM_IC_SELECTION(sConfig->ICSelection));
+  assert_param(IS_TIM_IC_PRESCALER(sConfig->ICPrescaler));
+  assert_param(IS_TIM_IC_FILTER(sConfig->ICFilter));
+
+  /* Process Locked */
+  __HAL_LOCK(htim);
+
+  if (Channel == TIM_CHANNEL_1)
+  {
+    /* TI1 Configuration */
+    TIM_TI1_SetConfig(htim->Instance,
+                      sConfig->ICPolarity,
+                      sConfig->ICSelection,
+                      sConfig->ICFilter);
+
+    /* Reset the IC1PSC Bits */
+    htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
+
+    /* Set the IC1PSC value */
+    htim->Instance->CCMR1 |= sConfig->ICPrescaler;
+  }
+  else if (Channel == TIM_CHANNEL_2)
+  {
+    /* TI2 Configuration */
+    assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+
+    TIM_TI2_SetConfig(htim->Instance,
+                      sConfig->ICPolarity,
+                      sConfig->ICSelection,
+                      sConfig->ICFilter);
+
+    /* Reset the IC2PSC Bits */
+    htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
+
+    /* Set the IC2PSC value */
+    htim->Instance->CCMR1 |= (sConfig->ICPrescaler << 8U);
+  }
+  else if (Channel == TIM_CHANNEL_3)
+  {
+    /* TI3 Configuration */
+    assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
+
+    TIM_TI3_SetConfig(htim->Instance,
+                      sConfig->ICPolarity,
+                      sConfig->ICSelection,
+                      sConfig->ICFilter);
+
+    /* Reset the IC3PSC Bits */
+    htim->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC;
+
+    /* Set the IC3PSC value */
+    htim->Instance->CCMR2 |= sConfig->ICPrescaler;
+  }
+  else if (Channel == TIM_CHANNEL_4)
+  {
+    /* TI4 Configuration */
+    assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
+
+    TIM_TI4_SetConfig(htim->Instance,
+                      sConfig->ICPolarity,
+                      sConfig->ICSelection,
+                      sConfig->ICFilter);
+
+    /* Reset the IC4PSC Bits */
+    htim->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC;
+
+    /* Set the IC4PSC value */
+    htim->Instance->CCMR2 |= (sConfig->ICPrescaler << 8U);
+  }
+  else
+  {
+    status = HAL_ERROR;
+  }
+
+  __HAL_UNLOCK(htim);
+
+  return status;
+}
+
+/**
+  * @brief  Initializes the TIM PWM  channels according to the specified
+  *         parameters in the TIM_OC_InitTypeDef.
+  * @param  htim TIM PWM handle
+  * @param  sConfig TIM PWM configuration structure
+  * @param  Channel TIM Channels to be configured
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim,
+                                            TIM_OC_InitTypeDef *sConfig,
+                                            uint32_t Channel)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CHANNELS(Channel));
+  assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));
+  assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
+  assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));
+
+  /* Process Locked */
+  __HAL_LOCK(htim);
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
+
+      /* Configure the Channel 1 in PWM mode */
+      TIM_OC1_SetConfig(htim->Instance, sConfig);
+
+      /* Set the Preload enable bit for channel1 */
+      htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE;
+
+      /* Configure the Output Fast mode */
+      htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;
+      htim->Instance->CCMR1 |= sConfig->OCFastMode;
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+
+      /* Configure the Channel 2 in PWM mode */
+      TIM_OC2_SetConfig(htim->Instance, sConfig);
+
+      /* Set the Preload enable bit for channel2 */
+      htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE;
+
+      /* Configure the Output Fast mode */
+      htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;
+      htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U;
+      break;
+    }
+
+    case TIM_CHANNEL_3:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
+
+      /* Configure the Channel 3 in PWM mode */
+      TIM_OC3_SetConfig(htim->Instance, sConfig);
+
+      /* Set the Preload enable bit for channel3 */
+      htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE;
+
+      /* Configure the Output Fast mode */
+      htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;
+      htim->Instance->CCMR2 |= sConfig->OCFastMode;
+      break;
+    }
+
+    case TIM_CHANNEL_4:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
+
+      /* Configure the Channel 4 in PWM mode */
+      TIM_OC4_SetConfig(htim->Instance, sConfig);
+
+      /* Set the Preload enable bit for channel4 */
+      htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE;
+
+      /* Configure the Output Fast mode */
+      htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;
+      htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U;
+      break;
+    }
+
+    default:
+      status = HAL_ERROR;
+      break;
+  }
+
+  __HAL_UNLOCK(htim);
+
+  return status;
+}
+
+/**
+  * @brief  Initializes the TIM One Pulse Channels according to the specified
+  *         parameters in the TIM_OnePulse_InitTypeDef.
+  * @param  htim TIM One Pulse handle
+  * @param  sConfig TIM One Pulse configuration structure
+  * @param  OutputChannel TIM output channel to configure
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  * @param  InputChannel TIM input Channel to configure
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  * @note  To output a waveform with a minimum delay user can enable the fast
+  *        mode by calling the @ref __HAL_TIM_ENABLE_OCxFAST macro. Then CCx
+  *        output is forced in response to the edge detection on TIx input,
+  *        without taking in account the comparison.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim,  TIM_OnePulse_InitTypeDef *sConfig,
+                                                 uint32_t OutputChannel,  uint32_t InputChannel)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  TIM_OC_InitTypeDef temp1;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_OPM_CHANNELS(OutputChannel));
+  assert_param(IS_TIM_OPM_CHANNELS(InputChannel));
+
+  if (OutputChannel != InputChannel)
+  {
+    /* Process Locked */
+    __HAL_LOCK(htim);
+
+    htim->State = HAL_TIM_STATE_BUSY;
+
+    /* Extract the Output compare configuration from sConfig structure */
+    temp1.OCMode = sConfig->OCMode;
+    temp1.Pulse = sConfig->Pulse;
+    temp1.OCPolarity = sConfig->OCPolarity;
+    temp1.OCNPolarity = sConfig->OCNPolarity;
+    temp1.OCIdleState = sConfig->OCIdleState;
+    temp1.OCNIdleState = sConfig->OCNIdleState;
+
+    switch (OutputChannel)
+    {
+      case TIM_CHANNEL_1:
+      {
+        assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
+
+        TIM_OC1_SetConfig(htim->Instance, &temp1);
+        break;
+      }
+
+      case TIM_CHANNEL_2:
+      {
+        assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+
+        TIM_OC2_SetConfig(htim->Instance, &temp1);
+        break;
+      }
+
+      default:
+        status = HAL_ERROR;
+        break;
+    }
+
+    if (status == HAL_OK)
+    {
+      switch (InputChannel)
+      {
+        case TIM_CHANNEL_1:
+        {
+          assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
+
+          TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity,
+                            sConfig->ICSelection, sConfig->ICFilter);
+
+          /* Reset the IC1PSC Bits */
+          htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
+
+          /* Select the Trigger source */
+          htim->Instance->SMCR &= ~TIM_SMCR_TS;
+          htim->Instance->SMCR |= TIM_TS_TI1FP1;
+
+          /* Select the Slave Mode */
+          htim->Instance->SMCR &= ~TIM_SMCR_SMS;
+          htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
+          break;
+        }
+
+        case TIM_CHANNEL_2:
+        {
+          assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+
+          TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity,
+                            sConfig->ICSelection, sConfig->ICFilter);
+
+          /* Reset the IC2PSC Bits */
+          htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
+
+          /* Select the Trigger source */
+          htim->Instance->SMCR &= ~TIM_SMCR_TS;
+          htim->Instance->SMCR |= TIM_TS_TI2FP2;
+
+          /* Select the Slave Mode */
+          htim->Instance->SMCR &= ~TIM_SMCR_SMS;
+          htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
+          break;
+        }
+
+        default:
+          status = HAL_ERROR;
+          break;
+      }
+    }
+
+    htim->State = HAL_TIM_STATE_READY;
+
+    __HAL_UNLOCK(htim);
+
+    return status;
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Configure the DMA Burst to transfer Data from the memory to the TIM peripheral
+  * @param  htim TIM handle
+  * @param  BurstBaseAddress TIM Base address from where the DMA  will start the Data write
+  *         This parameter can be one of the following values:
+  *            @arg TIM_DMABASE_CR1
+  *            @arg TIM_DMABASE_CR2
+  *            @arg TIM_DMABASE_SMCR
+  *            @arg TIM_DMABASE_DIER
+  *            @arg TIM_DMABASE_SR
+  *            @arg TIM_DMABASE_EGR
+  *            @arg TIM_DMABASE_CCMR1
+  *            @arg TIM_DMABASE_CCMR2
+  *            @arg TIM_DMABASE_CCER
+  *            @arg TIM_DMABASE_CNT
+  *            @arg TIM_DMABASE_PSC
+  *            @arg TIM_DMABASE_ARR
+  *            @arg TIM_DMABASE_RCR
+  *            @arg TIM_DMABASE_CCR1
+  *            @arg TIM_DMABASE_CCR2
+  *            @arg TIM_DMABASE_CCR3
+  *            @arg TIM_DMABASE_CCR4
+  *            @arg TIM_DMABASE_BDTR
+  * @param  BurstRequestSrc TIM DMA Request sources
+  *         This parameter can be one of the following values:
+  *            @arg TIM_DMA_UPDATE: TIM update Interrupt source
+  *            @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
+  *            @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
+  *            @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
+  *            @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
+  *            @arg TIM_DMA_COM: TIM Commutation DMA source
+  *            @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
+  * @param  BurstBuffer The Buffer address.
+  * @param  BurstLength DMA Burst length. This parameter can be one value
+  *         between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
+  * @note   This function should be used only when BurstLength is equal to DMA data transfer length.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
+                                              uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t  BurstLength)
+{
+  HAL_StatusTypeDef status;
+
+  status = HAL_TIM_DMABurst_MultiWriteStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength,
+                                            ((BurstLength) >> 8U) + 1U);
+
+
+
+  return status;
+}
+
+/**
+  * @brief  Configure the DMA Burst to transfer multiple Data from the memory to the TIM peripheral
+  * @param  htim TIM handle
+  * @param  BurstBaseAddress TIM Base address from where the DMA will start the Data write
+  *         This parameter can be one of the following values:
+  *            @arg TIM_DMABASE_CR1
+  *            @arg TIM_DMABASE_CR2
+  *            @arg TIM_DMABASE_SMCR
+  *            @arg TIM_DMABASE_DIER
+  *            @arg TIM_DMABASE_SR
+  *            @arg TIM_DMABASE_EGR
+  *            @arg TIM_DMABASE_CCMR1
+  *            @arg TIM_DMABASE_CCMR2
+  *            @arg TIM_DMABASE_CCER
+  *            @arg TIM_DMABASE_CNT
+  *            @arg TIM_DMABASE_PSC
+  *            @arg TIM_DMABASE_ARR
+  *            @arg TIM_DMABASE_RCR
+  *            @arg TIM_DMABASE_CCR1
+  *            @arg TIM_DMABASE_CCR2
+  *            @arg TIM_DMABASE_CCR3
+  *            @arg TIM_DMABASE_CCR4
+  *            @arg TIM_DMABASE_BDTR
+  * @param  BurstRequestSrc TIM DMA Request sources
+  *         This parameter can be one of the following values:
+  *            @arg TIM_DMA_UPDATE: TIM update Interrupt source
+  *            @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
+  *            @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
+  *            @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
+  *            @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
+  *            @arg TIM_DMA_COM: TIM Commutation DMA source
+  *            @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
+  * @param  BurstBuffer The Buffer address.
+  * @param  BurstLength DMA Burst length. This parameter can be one value
+  *         between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
+  * @param  DataLength Data length. This parameter can be one value
+  *         between 1 and 0xFFFF.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
+                                                   uint32_t BurstRequestSrc, uint32_t *BurstBuffer,
+                                                   uint32_t  BurstLength,  uint32_t  DataLength)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
+  assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
+  assert_param(IS_TIM_DMA_LENGTH(BurstLength));
+  assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength));
+
+  if (htim->DMABurstState == HAL_DMA_BURST_STATE_BUSY)
+  {
+    return HAL_BUSY;
+  }
+  else if (htim->DMABurstState == HAL_DMA_BURST_STATE_READY)
+  {
+    if ((BurstBuffer == NULL) && (BurstLength > 0U))
+    {
+      return HAL_ERROR;
+    }
+    else
+    {
+      htim->DMABurstState = HAL_DMA_BURST_STATE_BUSY;
+    }
+  }
+  else
+  {
+    /* nothing to do */
+  }
+
+  switch (BurstRequestSrc)
+  {
+    case TIM_DMA_UPDATE:
+    {
+      /* Set the DMA Period elapsed callbacks */
+      htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
+      htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer,
+                           (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
+      {
+        /* Return error status */
+        return HAL_ERROR;
+      }
+      break;
+    }
+    case TIM_DMA_CC1:
+    {
+      /* Set the DMA compare callbacks */
+      htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
+      htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer,
+                           (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
+      {
+        /* Return error status */
+        return HAL_ERROR;
+      }
+      break;
+    }
+    case TIM_DMA_CC2:
+    {
+      /* Set the DMA compare callbacks */
+      htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
+      htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer,
+                           (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
+      {
+        /* Return error status */
+        return HAL_ERROR;
+      }
+      break;
+    }
+    case TIM_DMA_CC3:
+    {
+      /* Set the DMA compare callbacks */
+      htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
+      htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer,
+                           (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
+      {
+        /* Return error status */
+        return HAL_ERROR;
+      }
+      break;
+    }
+    case TIM_DMA_CC4:
+    {
+      /* Set the DMA compare callbacks */
+      htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
+      htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer,
+                           (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
+      {
+        /* Return error status */
+        return HAL_ERROR;
+      }
+      break;
+    }
+    case TIM_DMA_COM:
+    {
+      /* Set the DMA commutation callbacks */
+      htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback =  TIMEx_DMACommutationCplt;
+      htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback =  TIMEx_DMACommutationHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer,
+                           (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
+      {
+        /* Return error status */
+        return HAL_ERROR;
+      }
+      break;
+    }
+    case TIM_DMA_TRIGGER:
+    {
+      /* Set the DMA trigger callbacks */
+      htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
+      htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback = TIM_DMATriggerHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer,
+                           (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
+      {
+        /* Return error status */
+        return HAL_ERROR;
+      }
+      break;
+    }
+    default:
+      status = HAL_ERROR;
+      break;
+  }
+
+  if (status == HAL_OK)
+  {
+    /* Configure the DMA Burst Mode */
+    htim->Instance->DCR = (BurstBaseAddress | BurstLength);
+    /* Enable the TIM DMA Request */
+    __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  Stops the TIM DMA Burst mode
+  * @param  htim TIM handle
+  * @param  BurstRequestSrc TIM DMA Request sources to disable
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
+
+  /* Abort the DMA transfer (at least disable the DMA stream) */
+  switch (BurstRequestSrc)
+  {
+    case TIM_DMA_UPDATE:
+    {
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);
+      break;
+    }
+    case TIM_DMA_CC1:
+    {
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
+      break;
+    }
+    case TIM_DMA_CC2:
+    {
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
+      break;
+    }
+    case TIM_DMA_CC3:
+    {
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
+      break;
+    }
+    case TIM_DMA_CC4:
+    {
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
+      break;
+    }
+    case TIM_DMA_COM:
+    {
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]);
+      break;
+    }
+    case TIM_DMA_TRIGGER:
+    {
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]);
+      break;
+    }
+    default:
+      status = HAL_ERROR;
+      break;
+  }
+
+  if (status == HAL_OK)
+  {
+    /* Disable the TIM Update DMA request */
+    __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
+
+    /* Change the DMA burst operation state */
+    htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  Configure the DMA Burst to transfer Data from the TIM peripheral to the memory
+  * @param  htim TIM handle
+  * @param  BurstBaseAddress TIM Base address from where the DMA  will start the Data read
+  *         This parameter can be one of the following values:
+  *            @arg TIM_DMABASE_CR1
+  *            @arg TIM_DMABASE_CR2
+  *            @arg TIM_DMABASE_SMCR
+  *            @arg TIM_DMABASE_DIER
+  *            @arg TIM_DMABASE_SR
+  *            @arg TIM_DMABASE_EGR
+  *            @arg TIM_DMABASE_CCMR1
+  *            @arg TIM_DMABASE_CCMR2
+  *            @arg TIM_DMABASE_CCER
+  *            @arg TIM_DMABASE_CNT
+  *            @arg TIM_DMABASE_PSC
+  *            @arg TIM_DMABASE_ARR
+  *            @arg TIM_DMABASE_RCR
+  *            @arg TIM_DMABASE_CCR1
+  *            @arg TIM_DMABASE_CCR2
+  *            @arg TIM_DMABASE_CCR3
+  *            @arg TIM_DMABASE_CCR4
+  *            @arg TIM_DMABASE_BDTR
+  * @param  BurstRequestSrc TIM DMA Request sources
+  *         This parameter can be one of the following values:
+  *            @arg TIM_DMA_UPDATE: TIM update Interrupt source
+  *            @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
+  *            @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
+  *            @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
+  *            @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
+  *            @arg TIM_DMA_COM: TIM Commutation DMA source
+  *            @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
+  * @param  BurstBuffer The Buffer address.
+  * @param  BurstLength DMA Burst length. This parameter can be one value
+  *         between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
+  * @note   This function should be used only when BurstLength is equal to DMA data transfer length.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
+                                             uint32_t BurstRequestSrc, uint32_t  *BurstBuffer, uint32_t  BurstLength)
+{
+  HAL_StatusTypeDef status;
+
+  status = HAL_TIM_DMABurst_MultiReadStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength,
+                                           ((BurstLength) >> 8U) + 1U);
+
+
+  return status;
+}
+
+/**
+  * @brief  Configure the DMA Burst to transfer Data from the TIM peripheral to the memory
+  * @param  htim TIM handle
+  * @param  BurstBaseAddress TIM Base address from where the DMA  will start the Data read
+  *         This parameter can be one of the following values:
+  *            @arg TIM_DMABASE_CR1
+  *            @arg TIM_DMABASE_CR2
+  *            @arg TIM_DMABASE_SMCR
+  *            @arg TIM_DMABASE_DIER
+  *            @arg TIM_DMABASE_SR
+  *            @arg TIM_DMABASE_EGR
+  *            @arg TIM_DMABASE_CCMR1
+  *            @arg TIM_DMABASE_CCMR2
+  *            @arg TIM_DMABASE_CCER
+  *            @arg TIM_DMABASE_CNT
+  *            @arg TIM_DMABASE_PSC
+  *            @arg TIM_DMABASE_ARR
+  *            @arg TIM_DMABASE_RCR
+  *            @arg TIM_DMABASE_CCR1
+  *            @arg TIM_DMABASE_CCR2
+  *            @arg TIM_DMABASE_CCR3
+  *            @arg TIM_DMABASE_CCR4
+  *            @arg TIM_DMABASE_BDTR
+  * @param  BurstRequestSrc TIM DMA Request sources
+  *         This parameter can be one of the following values:
+  *            @arg TIM_DMA_UPDATE: TIM update Interrupt source
+  *            @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
+  *            @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
+  *            @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
+  *            @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
+  *            @arg TIM_DMA_COM: TIM Commutation DMA source
+  *            @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
+  * @param  BurstBuffer The Buffer address.
+  * @param  BurstLength DMA Burst length. This parameter can be one value
+  *         between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
+  * @param  DataLength Data length. This parameter can be one value
+  *         between 1 and 0xFFFF.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
+                                                  uint32_t BurstRequestSrc, uint32_t  *BurstBuffer,
+                                                  uint32_t  BurstLength, uint32_t  DataLength)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
+  assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
+  assert_param(IS_TIM_DMA_LENGTH(BurstLength));
+  assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength));
+
+  if (htim->DMABurstState == HAL_DMA_BURST_STATE_BUSY)
+  {
+    return HAL_BUSY;
+  }
+  else if (htim->DMABurstState == HAL_DMA_BURST_STATE_READY)
+  {
+    if ((BurstBuffer == NULL) && (BurstLength > 0U))
+    {
+      return HAL_ERROR;
+    }
+    else
+    {
+      htim->DMABurstState = HAL_DMA_BURST_STATE_BUSY;
+    }
+  }
+  else
+  {
+    /* nothing to do */
+  }
+  switch (BurstRequestSrc)
+  {
+    case TIM_DMA_UPDATE:
+    {
+      /* Set the DMA Period elapsed callbacks */
+      htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
+      htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
+                           DataLength) != HAL_OK)
+      {
+        /* Return error status */
+        return HAL_ERROR;
+      }
+      break;
+    }
+    case TIM_DMA_CC1:
+    {
+      /* Set the DMA capture callbacks */
+      htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
+      htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
+                           DataLength) != HAL_OK)
+      {
+        /* Return error status */
+        return HAL_ERROR;
+      }
+      break;
+    }
+    case TIM_DMA_CC2:
+    {
+      /* Set the DMA capture callbacks */
+      htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
+      htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
+                           DataLength) != HAL_OK)
+      {
+        /* Return error status */
+        return HAL_ERROR;
+      }
+      break;
+    }
+    case TIM_DMA_CC3:
+    {
+      /* Set the DMA capture callbacks */
+      htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;
+      htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
+                           DataLength) != HAL_OK)
+      {
+        /* Return error status */
+        return HAL_ERROR;
+      }
+      break;
+    }
+    case TIM_DMA_CC4:
+    {
+      /* Set the DMA capture callbacks */
+      htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;
+      htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
+                           DataLength) != HAL_OK)
+      {
+        /* Return error status */
+        return HAL_ERROR;
+      }
+      break;
+    }
+    case TIM_DMA_COM:
+    {
+      /* Set the DMA commutation callbacks */
+      htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback =  TIMEx_DMACommutationCplt;
+      htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback =  TIMEx_DMACommutationHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
+                           DataLength) != HAL_OK)
+      {
+        /* Return error status */
+        return HAL_ERROR;
+      }
+      break;
+    }
+    case TIM_DMA_TRIGGER:
+    {
+      /* Set the DMA trigger callbacks */
+      htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
+      htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback = TIM_DMATriggerHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
+                           DataLength) != HAL_OK)
+      {
+        /* Return error status */
+        return HAL_ERROR;
+      }
+      break;
+    }
+    default:
+      status = HAL_ERROR;
+      break;
+  }
+
+  if (status == HAL_OK)
+  {
+    /* Configure the DMA Burst Mode */
+    htim->Instance->DCR = (BurstBaseAddress | BurstLength);
+
+    /* Enable the TIM DMA Request */
+    __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  Stop the DMA burst reading
+  * @param  htim TIM handle
+  * @param  BurstRequestSrc TIM DMA Request sources to disable.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
+
+  /* Abort the DMA transfer (at least disable the DMA stream) */
+  switch (BurstRequestSrc)
+  {
+    case TIM_DMA_UPDATE:
+    {
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);
+      break;
+    }
+    case TIM_DMA_CC1:
+    {
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
+      break;
+    }
+    case TIM_DMA_CC2:
+    {
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
+      break;
+    }
+    case TIM_DMA_CC3:
+    {
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
+      break;
+    }
+    case TIM_DMA_CC4:
+    {
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
+      break;
+    }
+    case TIM_DMA_COM:
+    {
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]);
+      break;
+    }
+    case TIM_DMA_TRIGGER:
+    {
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]);
+      break;
+    }
+    default:
+      status = HAL_ERROR;
+      break;
+  }
+
+  if (status == HAL_OK)
+  {
+    /* Disable the TIM Update DMA request */
+    __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
+
+    /* Change the DMA burst operation state */
+    htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  Generate a software event
+  * @param  htim TIM handle
+  * @param  EventSource specifies the event source.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_EVENTSOURCE_UPDATE: Timer update Event source
+  *            @arg TIM_EVENTSOURCE_CC1: Timer Capture Compare 1 Event source
+  *            @arg TIM_EVENTSOURCE_CC2: Timer Capture Compare 2 Event source
+  *            @arg TIM_EVENTSOURCE_CC3: Timer Capture Compare 3 Event source
+  *            @arg TIM_EVENTSOURCE_CC4: Timer Capture Compare 4 Event source
+  *            @arg TIM_EVENTSOURCE_COM: Timer COM event source
+  *            @arg TIM_EVENTSOURCE_TRIGGER: Timer Trigger Event source
+  *            @arg TIM_EVENTSOURCE_BREAK: Timer Break event source
+  * @note   Basic timers can only generate an update event.
+  * @note   TIM_EVENTSOURCE_COM is relevant only with advanced timer instances.
+  * @note   TIM_EVENTSOURCE_BREAK are relevant only for timer instances
+  *         supporting a break input.
+  * @retval HAL status
+  */
+
+HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_EVENT_SOURCE(EventSource));
+
+  /* Process Locked */
+  __HAL_LOCK(htim);
+
+  /* Change the TIM state */
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  /* Set the event sources */
+  htim->Instance->EGR = EventSource;
+
+  /* Change the TIM state */
+  htim->State = HAL_TIM_STATE_READY;
+
+  __HAL_UNLOCK(htim);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Configures the OCRef clear feature
+  * @param  htim TIM handle
+  * @param  sClearInputConfig pointer to a TIM_ClearInputConfigTypeDef structure that
+  *         contains the OCREF clear feature and parameters for the TIM peripheral.
+  * @param  Channel specifies the TIM Channel
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1
+  *            @arg TIM_CHANNEL_2: TIM Channel 2
+  *            @arg TIM_CHANNEL_3: TIM Channel 3
+  *            @arg TIM_CHANNEL_4: TIM Channel 4
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim,
+                                           TIM_ClearInputConfigTypeDef *sClearInputConfig,
+                                           uint32_t Channel)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_OCXREF_CLEAR_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource));
+
+  /* Process Locked */
+  __HAL_LOCK(htim);
+
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  switch (sClearInputConfig->ClearInputSource)
+  {
+    case TIM_CLEARINPUTSOURCE_NONE:
+    {
+      /* Clear the OCREF clear selection bit and the the ETR Bits */
+      CLEAR_BIT(htim->Instance->SMCR, (TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP));
+      break;
+    }
+
+    case TIM_CLEARINPUTSOURCE_ETR:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity));
+      assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler));
+      assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter));
+
+      /* When OCRef clear feature is used with ETR source, ETR prescaler must be off */
+      if (sClearInputConfig->ClearInputPrescaler != TIM_CLEARINPUTPRESCALER_DIV1)
+      {
+        htim->State = HAL_TIM_STATE_READY;
+        __HAL_UNLOCK(htim);
+        return HAL_ERROR;
+      }
+
+      TIM_ETR_SetConfig(htim->Instance,
+                        sClearInputConfig->ClearInputPrescaler,
+                        sClearInputConfig->ClearInputPolarity,
+                        sClearInputConfig->ClearInputFilter);
+      break;
+    }
+
+    default:
+      status = HAL_ERROR;
+      break;
+  }
+
+  if (status == HAL_OK)
+  {
+    switch (Channel)
+    {
+      case TIM_CHANNEL_1:
+      {
+        if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
+        {
+          /* Enable the OCREF clear feature for Channel 1 */
+          SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE);
+        }
+        else
+        {
+          /* Disable the OCREF clear feature for Channel 1 */
+          CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE);
+        }
+        break;
+      }
+      case TIM_CHANNEL_2:
+      {
+        if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
+        {
+          /* Enable the OCREF clear feature for Channel 2 */
+          SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE);
+        }
+        else
+        {
+          /* Disable the OCREF clear feature for Channel 2 */
+          CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE);
+        }
+        break;
+      }
+      case TIM_CHANNEL_3:
+      {
+        if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
+        {
+          /* Enable the OCREF clear feature for Channel 3 */
+          SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE);
+        }
+        else
+        {
+          /* Disable the OCREF clear feature for Channel 3 */
+          CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE);
+        }
+        break;
+      }
+      case TIM_CHANNEL_4:
+      {
+        if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
+        {
+          /* Enable the OCREF clear feature for Channel 4 */
+          SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE);
+        }
+        else
+        {
+          /* Disable the OCREF clear feature for Channel 4 */
+          CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE);
+        }
+        break;
+      }
+      default:
+        break;
+    }
+  }
+
+  htim->State = HAL_TIM_STATE_READY;
+
+  __HAL_UNLOCK(htim);
+
+  return status;
+}
+
+/**
+  * @brief   Configures the clock source to be used
+  * @param  htim TIM handle
+  * @param  sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that
+  *         contains the clock source information for the TIM peripheral.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  uint32_t tmpsmcr;
+
+  /* Process Locked */
+  __HAL_LOCK(htim);
+
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource));
+
+  /* Reset the SMS, TS, ECE, ETPS and ETRF bits */
+  tmpsmcr = htim->Instance->SMCR;
+  tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
+  tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
+  htim->Instance->SMCR = tmpsmcr;
+
+  switch (sClockSourceConfig->ClockSource)
+  {
+    case TIM_CLOCKSOURCE_INTERNAL:
+    {
+      assert_param(IS_TIM_INSTANCE(htim->Instance));
+      break;
+    }
+
+    case TIM_CLOCKSOURCE_ETRMODE1:
+    {
+      /* Check whether or not the timer instance supports external trigger input mode 1 (ETRF)*/
+      assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));
+
+      /* Check ETR input conditioning related parameters */
+      assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
+      assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
+      assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
+
+      /* Configure the ETR Clock source */
+      TIM_ETR_SetConfig(htim->Instance,
+                        sClockSourceConfig->ClockPrescaler,
+                        sClockSourceConfig->ClockPolarity,
+                        sClockSourceConfig->ClockFilter);
+
+      /* Select the External clock mode1 and the ETRF trigger */
+      tmpsmcr = htim->Instance->SMCR;
+      tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1);
+      /* Write to TIMx SMCR */
+      htim->Instance->SMCR = tmpsmcr;
+      break;
+    }
+
+    case TIM_CLOCKSOURCE_ETRMODE2:
+    {
+      /* Check whether or not the timer instance supports external trigger input mode 2 (ETRF)*/
+      assert_param(IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(htim->Instance));
+
+      /* Check ETR input conditioning related parameters */
+      assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
+      assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
+      assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
+
+      /* Configure the ETR Clock source */
+      TIM_ETR_SetConfig(htim->Instance,
+                        sClockSourceConfig->ClockPrescaler,
+                        sClockSourceConfig->ClockPolarity,
+                        sClockSourceConfig->ClockFilter);
+      /* Enable the External clock mode2 */
+      htim->Instance->SMCR |= TIM_SMCR_ECE;
+      break;
+    }
+
+    case TIM_CLOCKSOURCE_TI1:
+    {
+      /* Check whether or not the timer instance supports external clock mode 1 */
+      assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
+
+      /* Check TI1 input conditioning related parameters */
+      assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
+      assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
+
+      TIM_TI1_ConfigInputStage(htim->Instance,
+                               sClockSourceConfig->ClockPolarity,
+                               sClockSourceConfig->ClockFilter);
+      TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1);
+      break;
+    }
+
+    case TIM_CLOCKSOURCE_TI2:
+    {
+      /* Check whether or not the timer instance supports external clock mode 1 (ETRF)*/
+      assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
+
+      /* Check TI2 input conditioning related parameters */
+      assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
+      assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
+
+      TIM_TI2_ConfigInputStage(htim->Instance,
+                               sClockSourceConfig->ClockPolarity,
+                               sClockSourceConfig->ClockFilter);
+      TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2);
+      break;
+    }
+
+    case TIM_CLOCKSOURCE_TI1ED:
+    {
+      /* Check whether or not the timer instance supports external clock mode 1 */
+      assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
+
+      /* Check TI1 input conditioning related parameters */
+      assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
+      assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
+
+      TIM_TI1_ConfigInputStage(htim->Instance,
+                               sClockSourceConfig->ClockPolarity,
+                               sClockSourceConfig->ClockFilter);
+      TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED);
+      break;
+    }
+
+    case TIM_CLOCKSOURCE_ITR0:
+    case TIM_CLOCKSOURCE_ITR1:
+    case TIM_CLOCKSOURCE_ITR2:
+    case TIM_CLOCKSOURCE_ITR3:
+    {
+      /* Check whether or not the timer instance supports internal trigger input */
+      assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
+
+      TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource);
+      break;
+    }
+
+    default:
+      status = HAL_ERROR;
+      break;
+  }
+  htim->State = HAL_TIM_STATE_READY;
+
+  __HAL_UNLOCK(htim);
+
+  return status;
+}
+
+/**
+  * @brief  Selects the signal connected to the TI1 input: direct from CH1_input
+  *         or a XOR combination between CH1_input, CH2_input & CH3_input
+  * @param  htim TIM handle.
+  * @param  TI1_Selection Indicate whether or not channel 1 is connected to the
+  *         output of a XOR gate.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_TI1SELECTION_CH1: The TIMx_CH1 pin is connected to TI1 input
+  *            @arg TIM_TI1SELECTION_XORCOMBINATION: The TIMx_CH1, CH2 and CH3
+  *            pins are connected to the TI1 input (XOR combination)
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection)
+{
+  uint32_t tmpcr2;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_TI1SELECTION(TI1_Selection));
+
+  /* Get the TIMx CR2 register value */
+  tmpcr2 = htim->Instance->CR2;
+
+  /* Reset the TI1 selection */
+  tmpcr2 &= ~TIM_CR2_TI1S;
+
+  /* Set the TI1 selection */
+  tmpcr2 |= TI1_Selection;
+
+  /* Write to TIMxCR2 */
+  htim->Instance->CR2 = tmpcr2;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Configures the TIM in Slave mode
+  * @param  htim TIM handle.
+  * @param  sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that
+  *         contains the selected trigger (internal trigger input, filtered
+  *         timer input or external trigger input) and the Slave mode
+  *         (Disable, Reset, Gated, Trigger, External clock mode 1).
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
+  assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
+
+  __HAL_LOCK(htim);
+
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  if (TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK)
+  {
+    htim->State = HAL_TIM_STATE_READY;
+    __HAL_UNLOCK(htim);
+    return HAL_ERROR;
+  }
+
+  /* Disable Trigger Interrupt */
+  __HAL_TIM_DISABLE_IT(htim, TIM_IT_TRIGGER);
+
+  /* Disable Trigger DMA request */
+  __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
+
+  htim->State = HAL_TIM_STATE_READY;
+
+  __HAL_UNLOCK(htim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Configures the TIM in Slave mode in interrupt mode
+  * @param  htim TIM handle.
+  * @param  sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that
+  *         contains the selected trigger (internal trigger input, filtered
+  *         timer input or external trigger input) and the Slave mode
+  *         (Disable, Reset, Gated, Trigger, External clock mode 1).
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim,
+                                                TIM_SlaveConfigTypeDef *sSlaveConfig)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
+  assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
+
+  __HAL_LOCK(htim);
+
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  if (TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK)
+  {
+    htim->State = HAL_TIM_STATE_READY;
+    __HAL_UNLOCK(htim);
+    return HAL_ERROR;
+  }
+
+  /* Enable Trigger Interrupt */
+  __HAL_TIM_ENABLE_IT(htim, TIM_IT_TRIGGER);
+
+  /* Disable Trigger DMA request */
+  __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
+
+  htim->State = HAL_TIM_STATE_READY;
+
+  __HAL_UNLOCK(htim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Read the captured value from Capture Compare unit
+  * @param  htim TIM handle.
+  * @param  Channel TIM Channels to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @retval Captured value
+  */
+uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  uint32_t tmpreg = 0U;
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
+
+      /* Return the capture 1 value */
+      tmpreg =  htim->Instance->CCR1;
+
+      break;
+    }
+    case TIM_CHANNEL_2:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+
+      /* Return the capture 2 value */
+      tmpreg =   htim->Instance->CCR2;
+
+      break;
+    }
+
+    case TIM_CHANNEL_3:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
+
+      /* Return the capture 3 value */
+      tmpreg =   htim->Instance->CCR3;
+
+      break;
+    }
+
+    case TIM_CHANNEL_4:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
+
+      /* Return the capture 4 value */
+      tmpreg =   htim->Instance->CCR4;
+
+      break;
+    }
+
+    default:
+      break;
+  }
+
+  return tmpreg;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions
+  *  @brief    TIM Callbacks functions
+  *
+@verbatim
+  ==============================================================================
+                        ##### TIM Callbacks functions #####
+  ==============================================================================
+ [..]
+   This section provides TIM callback functions:
+   (+) TIM Period elapsed callback
+   (+) TIM Output Compare callback
+   (+) TIM Input capture callback
+   (+) TIM Trigger callback
+   (+) TIM Error callback
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Period elapsed callback in non-blocking mode
+  * @param  htim TIM handle
+  * @retval None
+  */
+__weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_PeriodElapsedCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Period elapsed half complete callback in non-blocking mode
+  * @param  htim TIM handle
+  * @retval None
+  */
+__weak void HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_PeriodElapsedHalfCpltCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Output Compare callback in non-blocking mode
+  * @param  htim TIM OC handle
+  * @retval None
+  */
+__weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Input Capture callback in non-blocking mode
+  * @param  htim TIM IC handle
+  * @retval None
+  */
+__weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_IC_CaptureCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Input Capture half complete callback in non-blocking mode
+  * @param  htim TIM IC handle
+  * @retval None
+  */
+__weak void HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_IC_CaptureHalfCpltCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  PWM Pulse finished callback in non-blocking mode
+  * @param  htim TIM handle
+  * @retval None
+  */
+__weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  PWM Pulse finished half complete callback in non-blocking mode
+  * @param  htim TIM handle
+  * @retval None
+  */
+__weak void HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_PWM_PulseFinishedHalfCpltCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Hall Trigger detection callback in non-blocking mode
+  * @param  htim TIM handle
+  * @retval None
+  */
+__weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_TriggerCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Hall Trigger detection half complete callback in non-blocking mode
+  * @param  htim TIM handle
+  * @retval None
+  */
+__weak void HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_TriggerHalfCpltCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Timer error callback in non-blocking mode
+  * @param  htim TIM handle
+  * @retval None
+  */
+__weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_ErrorCallback could be implemented in the user file
+   */
+}
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+/**
+  * @brief  Register a User TIM callback to be used instead of the weak predefined callback
+  * @param htim tim handle
+  * @param CallbackID ID of the callback to be registered
+  *        This parameter can be one of the following values:
+  *          @arg @ref HAL_TIM_BASE_MSPINIT_CB_ID Base MspInit Callback ID
+  *          @arg @ref HAL_TIM_BASE_MSPDEINIT_CB_ID Base MspDeInit Callback ID
+  *          @arg @ref HAL_TIM_IC_MSPINIT_CB_ID IC MspInit Callback ID
+  *          @arg @ref HAL_TIM_IC_MSPDEINIT_CB_ID IC MspDeInit Callback ID
+  *          @arg @ref HAL_TIM_OC_MSPINIT_CB_ID OC MspInit Callback ID
+  *          @arg @ref HAL_TIM_OC_MSPDEINIT_CB_ID OC MspDeInit Callback ID
+  *          @arg @ref HAL_TIM_PWM_MSPINIT_CB_ID PWM MspInit Callback ID
+  *          @arg @ref HAL_TIM_PWM_MSPDEINIT_CB_ID PWM MspDeInit Callback ID
+  *          @arg @ref HAL_TIM_ONE_PULSE_MSPINIT_CB_ID One Pulse MspInit Callback ID
+  *          @arg @ref HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID One Pulse MspDeInit Callback ID
+  *          @arg @ref HAL_TIM_ENCODER_MSPINIT_CB_ID Encoder MspInit Callback ID
+  *          @arg @ref HAL_TIM_ENCODER_MSPDEINIT_CB_ID Encoder MspDeInit Callback ID
+  *          @arg @ref HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID Hall Sensor MspInit Callback ID
+  *          @arg @ref HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID Hall Sensor MspDeInit Callback ID
+  *          @arg @ref HAL_TIM_PERIOD_ELAPSED_CB_ID Period Elapsed Callback ID
+  *          @arg @ref HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID Period Elapsed half complete Callback ID
+  *          @arg @ref HAL_TIM_TRIGGER_CB_ID Trigger Callback ID
+  *          @arg @ref HAL_TIM_TRIGGER_HALF_CB_ID Trigger half complete Callback ID
+  *          @arg @ref HAL_TIM_IC_CAPTURE_CB_ID Input Capture Callback ID
+  *          @arg @ref HAL_TIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete Callback ID
+  *          @arg @ref HAL_TIM_OC_DELAY_ELAPSED_CB_ID Output Compare Delay Elapsed Callback ID
+  *          @arg @ref HAL_TIM_PWM_PULSE_FINISHED_CB_ID PWM Pulse Finished Callback ID
+  *          @arg @ref HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID PWM Pulse Finished half complete Callback ID
+  *          @arg @ref HAL_TIM_ERROR_CB_ID Error Callback ID
+  *          @arg @ref HAL_TIM_COMMUTATION_CB_ID Commutation Callback ID
+  *          @arg @ref HAL_TIM_COMMUTATION_HALF_CB_ID Commutation half complete Callback ID
+  *          @arg @ref HAL_TIM_BREAK_CB_ID Break Callback ID
+  *          @param pCallback pointer to the callback function
+  *          @retval status
+  */
+HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID,
+                                           pTIM_CallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    return HAL_ERROR;
+  }
+  /* Process locked */
+  __HAL_LOCK(htim);
+
+  if (htim->State == HAL_TIM_STATE_READY)
+  {
+    switch (CallbackID)
+    {
+      case HAL_TIM_BASE_MSPINIT_CB_ID :
+        htim->Base_MspInitCallback                 = pCallback;
+        break;
+
+      case HAL_TIM_BASE_MSPDEINIT_CB_ID :
+        htim->Base_MspDeInitCallback               = pCallback;
+        break;
+
+      case HAL_TIM_IC_MSPINIT_CB_ID :
+        htim->IC_MspInitCallback                   = pCallback;
+        break;
+
+      case HAL_TIM_IC_MSPDEINIT_CB_ID :
+        htim->IC_MspDeInitCallback                 = pCallback;
+        break;
+
+      case HAL_TIM_OC_MSPINIT_CB_ID :
+        htim->OC_MspInitCallback                   = pCallback;
+        break;
+
+      case HAL_TIM_OC_MSPDEINIT_CB_ID :
+        htim->OC_MspDeInitCallback                 = pCallback;
+        break;
+
+      case HAL_TIM_PWM_MSPINIT_CB_ID :
+        htim->PWM_MspInitCallback                  = pCallback;
+        break;
+
+      case HAL_TIM_PWM_MSPDEINIT_CB_ID :
+        htim->PWM_MspDeInitCallback                = pCallback;
+        break;
+
+      case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
+        htim->OnePulse_MspInitCallback             = pCallback;
+        break;
+
+      case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
+        htim->OnePulse_MspDeInitCallback           = pCallback;
+        break;
+
+      case HAL_TIM_ENCODER_MSPINIT_CB_ID :
+        htim->Encoder_MspInitCallback              = pCallback;
+        break;
+
+      case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
+        htim->Encoder_MspDeInitCallback            = pCallback;
+        break;
+
+      case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :
+        htim->HallSensor_MspInitCallback           = pCallback;
+        break;
+
+      case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :
+        htim->HallSensor_MspDeInitCallback         = pCallback;
+        break;
+
+      case HAL_TIM_PERIOD_ELAPSED_CB_ID :
+        htim->PeriodElapsedCallback                = pCallback;
+        break;
+
+      case HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID :
+        htim->PeriodElapsedHalfCpltCallback        = pCallback;
+        break;
+
+      case HAL_TIM_TRIGGER_CB_ID :
+        htim->TriggerCallback                      = pCallback;
+        break;
+
+      case HAL_TIM_TRIGGER_HALF_CB_ID :
+        htim->TriggerHalfCpltCallback              = pCallback;
+        break;
+
+      case HAL_TIM_IC_CAPTURE_CB_ID :
+        htim->IC_CaptureCallback                   = pCallback;
+        break;
+
+      case HAL_TIM_IC_CAPTURE_HALF_CB_ID :
+        htim->IC_CaptureHalfCpltCallback           = pCallback;
+        break;
+
+      case HAL_TIM_OC_DELAY_ELAPSED_CB_ID :
+        htim->OC_DelayElapsedCallback              = pCallback;
+        break;
+
+      case HAL_TIM_PWM_PULSE_FINISHED_CB_ID :
+        htim->PWM_PulseFinishedCallback            = pCallback;
+        break;
+
+      case HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID :
+        htim->PWM_PulseFinishedHalfCpltCallback    = pCallback;
+        break;
+
+      case HAL_TIM_ERROR_CB_ID :
+        htim->ErrorCallback                        = pCallback;
+        break;
+
+      case HAL_TIM_COMMUTATION_CB_ID :
+        htim->CommutationCallback                  = pCallback;
+        break;
+
+      case HAL_TIM_COMMUTATION_HALF_CB_ID :
+        htim->CommutationHalfCpltCallback          = pCallback;
+        break;
+
+      case HAL_TIM_BREAK_CB_ID :
+        htim->BreakCallback                        = pCallback;
+        break;
+
+      default :
+        /* Return error status */
+        status = HAL_ERROR;
+        break;
+    }
+  }
+  else if (htim->State == HAL_TIM_STATE_RESET)
+  {
+    switch (CallbackID)
+    {
+      case HAL_TIM_BASE_MSPINIT_CB_ID :
+        htim->Base_MspInitCallback         = pCallback;
+        break;
+
+      case HAL_TIM_BASE_MSPDEINIT_CB_ID :
+        htim->Base_MspDeInitCallback       = pCallback;
+        break;
+
+      case HAL_TIM_IC_MSPINIT_CB_ID :
+        htim->IC_MspInitCallback           = pCallback;
+        break;
+
+      case HAL_TIM_IC_MSPDEINIT_CB_ID :
+        htim->IC_MspDeInitCallback         = pCallback;
+        break;
+
+      case HAL_TIM_OC_MSPINIT_CB_ID :
+        htim->OC_MspInitCallback           = pCallback;
+        break;
+
+      case HAL_TIM_OC_MSPDEINIT_CB_ID :
+        htim->OC_MspDeInitCallback         = pCallback;
+        break;
+
+      case HAL_TIM_PWM_MSPINIT_CB_ID :
+        htim->PWM_MspInitCallback          = pCallback;
+        break;
+
+      case HAL_TIM_PWM_MSPDEINIT_CB_ID :
+        htim->PWM_MspDeInitCallback        = pCallback;
+        break;
+
+      case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
+        htim->OnePulse_MspInitCallback     = pCallback;
+        break;
+
+      case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
+        htim->OnePulse_MspDeInitCallback   = pCallback;
+        break;
+
+      case HAL_TIM_ENCODER_MSPINIT_CB_ID :
+        htim->Encoder_MspInitCallback      = pCallback;
+        break;
+
+      case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
+        htim->Encoder_MspDeInitCallback    = pCallback;
+        break;
+
+      case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :
+        htim->HallSensor_MspInitCallback   = pCallback;
+        break;
+
+      case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :
+        htim->HallSensor_MspDeInitCallback = pCallback;
+        break;
+
+      default :
+        /* Return error status */
+        status = HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    /* Return error status */
+    status = HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(htim);
+
+  return status;
+}
+
+/**
+  * @brief  Unregister a TIM callback
+  *         TIM callback is redirected to the weak predefined callback
+  * @param htim tim handle
+  * @param CallbackID ID of the callback to be unregistered
+  *        This parameter can be one of the following values:
+  *          @arg @ref HAL_TIM_BASE_MSPINIT_CB_ID Base MspInit Callback ID
+  *          @arg @ref HAL_TIM_BASE_MSPDEINIT_CB_ID Base MspDeInit Callback ID
+  *          @arg @ref HAL_TIM_IC_MSPINIT_CB_ID IC MspInit Callback ID
+  *          @arg @ref HAL_TIM_IC_MSPDEINIT_CB_ID IC MspDeInit Callback ID
+  *          @arg @ref HAL_TIM_OC_MSPINIT_CB_ID OC MspInit Callback ID
+  *          @arg @ref HAL_TIM_OC_MSPDEINIT_CB_ID OC MspDeInit Callback ID
+  *          @arg @ref HAL_TIM_PWM_MSPINIT_CB_ID PWM MspInit Callback ID
+  *          @arg @ref HAL_TIM_PWM_MSPDEINIT_CB_ID PWM MspDeInit Callback ID
+  *          @arg @ref HAL_TIM_ONE_PULSE_MSPINIT_CB_ID One Pulse MspInit Callback ID
+  *          @arg @ref HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID One Pulse MspDeInit Callback ID
+  *          @arg @ref HAL_TIM_ENCODER_MSPINIT_CB_ID Encoder MspInit Callback ID
+  *          @arg @ref HAL_TIM_ENCODER_MSPDEINIT_CB_ID Encoder MspDeInit Callback ID
+  *          @arg @ref HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID Hall Sensor MspInit Callback ID
+  *          @arg @ref HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID Hall Sensor MspDeInit Callback ID
+  *          @arg @ref HAL_TIM_PERIOD_ELAPSED_CB_ID Period Elapsed Callback ID
+  *          @arg @ref HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID Period Elapsed half complete Callback ID
+  *          @arg @ref HAL_TIM_TRIGGER_CB_ID Trigger Callback ID
+  *          @arg @ref HAL_TIM_TRIGGER_HALF_CB_ID Trigger half complete Callback ID
+  *          @arg @ref HAL_TIM_IC_CAPTURE_CB_ID Input Capture Callback ID
+  *          @arg @ref HAL_TIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete Callback ID
+  *          @arg @ref HAL_TIM_OC_DELAY_ELAPSED_CB_ID Output Compare Delay Elapsed Callback ID
+  *          @arg @ref HAL_TIM_PWM_PULSE_FINISHED_CB_ID PWM Pulse Finished Callback ID
+  *          @arg @ref HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID PWM Pulse Finished half complete Callback ID
+  *          @arg @ref HAL_TIM_ERROR_CB_ID Error Callback ID
+  *          @arg @ref HAL_TIM_COMMUTATION_CB_ID Commutation Callback ID
+  *          @arg @ref HAL_TIM_COMMUTATION_HALF_CB_ID Commutation half complete Callback ID
+  *          @arg @ref HAL_TIM_BREAK_CB_ID Break Callback ID
+  *          @retval status
+  */
+HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Process locked */
+  __HAL_LOCK(htim);
+
+  if (htim->State == HAL_TIM_STATE_READY)
+  {
+    switch (CallbackID)
+    {
+      case HAL_TIM_BASE_MSPINIT_CB_ID :
+        /* Legacy weak Base MspInit Callback */
+        htim->Base_MspInitCallback              = HAL_TIM_Base_MspInit;
+        break;
+
+      case HAL_TIM_BASE_MSPDEINIT_CB_ID :
+        /* Legacy weak Base Msp DeInit Callback */
+        htim->Base_MspDeInitCallback            = HAL_TIM_Base_MspDeInit;
+        break;
+
+      case HAL_TIM_IC_MSPINIT_CB_ID :
+        /* Legacy weak IC Msp Init Callback */
+        htim->IC_MspInitCallback                = HAL_TIM_IC_MspInit;
+        break;
+
+      case HAL_TIM_IC_MSPDEINIT_CB_ID :
+        /* Legacy weak IC Msp DeInit Callback */
+        htim->IC_MspDeInitCallback              = HAL_TIM_IC_MspDeInit;
+        break;
+
+      case HAL_TIM_OC_MSPINIT_CB_ID :
+        /* Legacy weak OC Msp Init Callback */
+        htim->OC_MspInitCallback                = HAL_TIM_OC_MspInit;
+        break;
+
+      case HAL_TIM_OC_MSPDEINIT_CB_ID :
+        /* Legacy weak OC Msp DeInit Callback */
+        htim->OC_MspDeInitCallback              = HAL_TIM_OC_MspDeInit;
+        break;
+
+      case HAL_TIM_PWM_MSPINIT_CB_ID :
+        /* Legacy weak PWM Msp Init Callback */
+        htim->PWM_MspInitCallback               = HAL_TIM_PWM_MspInit;
+        break;
+
+      case HAL_TIM_PWM_MSPDEINIT_CB_ID :
+        /* Legacy weak PWM Msp DeInit Callback */
+        htim->PWM_MspDeInitCallback             = HAL_TIM_PWM_MspDeInit;
+        break;
+
+      case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
+        /* Legacy weak One Pulse Msp Init Callback */
+        htim->OnePulse_MspInitCallback          = HAL_TIM_OnePulse_MspInit;
+        break;
+
+      case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
+        /* Legacy weak One Pulse Msp DeInit Callback */
+        htim->OnePulse_MspDeInitCallback        = HAL_TIM_OnePulse_MspDeInit;
+        break;
+
+      case HAL_TIM_ENCODER_MSPINIT_CB_ID :
+        /* Legacy weak Encoder Msp Init Callback */
+        htim->Encoder_MspInitCallback           = HAL_TIM_Encoder_MspInit;
+        break;
+
+      case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
+        /* Legacy weak Encoder Msp DeInit Callback */
+        htim->Encoder_MspDeInitCallback         = HAL_TIM_Encoder_MspDeInit;
+        break;
+
+      case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :
+        /* Legacy weak Hall Sensor Msp Init Callback */
+        htim->HallSensor_MspInitCallback        = HAL_TIMEx_HallSensor_MspInit;
+        break;
+
+      case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :
+        /* Legacy weak Hall Sensor Msp DeInit Callback */
+        htim->HallSensor_MspDeInitCallback      = HAL_TIMEx_HallSensor_MspDeInit;
+        break;
+
+      case HAL_TIM_PERIOD_ELAPSED_CB_ID :
+        /* Legacy weak Period Elapsed Callback */
+        htim->PeriodElapsedCallback             = HAL_TIM_PeriodElapsedCallback;
+        break;
+
+      case HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID :
+        /* Legacy weak Period Elapsed half complete Callback */
+        htim->PeriodElapsedHalfCpltCallback     = HAL_TIM_PeriodElapsedHalfCpltCallback;
+        break;
+
+      case HAL_TIM_TRIGGER_CB_ID :
+        /* Legacy weak Trigger Callback */
+        htim->TriggerCallback                   = HAL_TIM_TriggerCallback;
+        break;
+
+      case HAL_TIM_TRIGGER_HALF_CB_ID :
+        /* Legacy weak Trigger half complete Callback */
+        htim->TriggerHalfCpltCallback           = HAL_TIM_TriggerHalfCpltCallback;
+        break;
+
+      case HAL_TIM_IC_CAPTURE_CB_ID :
+        /* Legacy weak IC Capture Callback */
+        htim->IC_CaptureCallback                = HAL_TIM_IC_CaptureCallback;
+        break;
+
+      case HAL_TIM_IC_CAPTURE_HALF_CB_ID :
+        /* Legacy weak IC Capture half complete Callback */
+        htim->IC_CaptureHalfCpltCallback        = HAL_TIM_IC_CaptureHalfCpltCallback;
+        break;
+
+      case HAL_TIM_OC_DELAY_ELAPSED_CB_ID :
+        /* Legacy weak OC Delay Elapsed Callback */
+        htim->OC_DelayElapsedCallback           = HAL_TIM_OC_DelayElapsedCallback;
+        break;
+
+      case HAL_TIM_PWM_PULSE_FINISHED_CB_ID :
+        /* Legacy weak PWM Pulse Finished Callback */
+        htim->PWM_PulseFinishedCallback         = HAL_TIM_PWM_PulseFinishedCallback;
+        break;
+
+      case HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID :
+        /* Legacy weak PWM Pulse Finished half complete Callback */
+        htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback;
+        break;
+
+      case HAL_TIM_ERROR_CB_ID :
+        /* Legacy weak Error Callback */
+        htim->ErrorCallback                     = HAL_TIM_ErrorCallback;
+        break;
+
+      case HAL_TIM_COMMUTATION_CB_ID :
+        /* Legacy weak Commutation Callback */
+        htim->CommutationCallback               = HAL_TIMEx_CommutCallback;
+        break;
+
+      case HAL_TIM_COMMUTATION_HALF_CB_ID :
+        /* Legacy weak Commutation half complete Callback */
+        htim->CommutationHalfCpltCallback       = HAL_TIMEx_CommutHalfCpltCallback;
+        break;
+
+      case HAL_TIM_BREAK_CB_ID :
+        /* Legacy weak Break Callback */
+        htim->BreakCallback                     = HAL_TIMEx_BreakCallback;
+        break;
+
+      default :
+        /* Return error status */
+        status = HAL_ERROR;
+        break;
+    }
+  }
+  else if (htim->State == HAL_TIM_STATE_RESET)
+  {
+    switch (CallbackID)
+    {
+      case HAL_TIM_BASE_MSPINIT_CB_ID :
+        /* Legacy weak Base MspInit Callback */
+        htim->Base_MspInitCallback         = HAL_TIM_Base_MspInit;
+        break;
+
+      case HAL_TIM_BASE_MSPDEINIT_CB_ID :
+        /* Legacy weak Base Msp DeInit Callback */
+        htim->Base_MspDeInitCallback       = HAL_TIM_Base_MspDeInit;
+        break;
+
+      case HAL_TIM_IC_MSPINIT_CB_ID :
+        /* Legacy weak IC Msp Init Callback */
+        htim->IC_MspInitCallback           = HAL_TIM_IC_MspInit;
+        break;
+
+      case HAL_TIM_IC_MSPDEINIT_CB_ID :
+        /* Legacy weak IC Msp DeInit Callback */
+        htim->IC_MspDeInitCallback         = HAL_TIM_IC_MspDeInit;
+        break;
+
+      case HAL_TIM_OC_MSPINIT_CB_ID :
+        /* Legacy weak OC Msp Init Callback */
+        htim->OC_MspInitCallback           = HAL_TIM_OC_MspInit;
+        break;
+
+      case HAL_TIM_OC_MSPDEINIT_CB_ID :
+        /* Legacy weak OC Msp DeInit Callback */
+        htim->OC_MspDeInitCallback         = HAL_TIM_OC_MspDeInit;
+        break;
+
+      case HAL_TIM_PWM_MSPINIT_CB_ID :
+        /* Legacy weak PWM Msp Init Callback */
+        htim->PWM_MspInitCallback          = HAL_TIM_PWM_MspInit;
+        break;
+
+      case HAL_TIM_PWM_MSPDEINIT_CB_ID :
+        /* Legacy weak PWM Msp DeInit Callback */
+        htim->PWM_MspDeInitCallback        = HAL_TIM_PWM_MspDeInit;
+        break;
+
+      case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
+        /* Legacy weak One Pulse Msp Init Callback */
+        htim->OnePulse_MspInitCallback     = HAL_TIM_OnePulse_MspInit;
+        break;
+
+      case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
+        /* Legacy weak One Pulse Msp DeInit Callback */
+        htim->OnePulse_MspDeInitCallback   = HAL_TIM_OnePulse_MspDeInit;
+        break;
+
+      case HAL_TIM_ENCODER_MSPINIT_CB_ID :
+        /* Legacy weak Encoder Msp Init Callback */
+        htim->Encoder_MspInitCallback      = HAL_TIM_Encoder_MspInit;
+        break;
+
+      case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
+        /* Legacy weak Encoder Msp DeInit Callback */
+        htim->Encoder_MspDeInitCallback    = HAL_TIM_Encoder_MspDeInit;
+        break;
+
+      case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :
+        /* Legacy weak Hall Sensor Msp Init Callback */
+        htim->HallSensor_MspInitCallback   = HAL_TIMEx_HallSensor_MspInit;
+        break;
+
+      case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :
+        /* Legacy weak Hall Sensor Msp DeInit Callback */
+        htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit;
+        break;
+
+      default :
+        /* Return error status */
+        status = HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    /* Return error status */
+    status = HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(htim);
+
+  return status;
+}
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Exported_Functions_Group10 TIM Peripheral State functions
+  *  @brief   TIM Peripheral State functions
+  *
+@verbatim
+  ==============================================================================
+                        ##### Peripheral State functions #####
+  ==============================================================================
+    [..]
+    This subsection permits to get in run-time the status of the peripheral
+    and the data flow.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Return the TIM Base handle state.
+  * @param  htim TIM Base handle
+  * @retval HAL state
+  */
+HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim)
+{
+  return htim->State;
+}
+
+/**
+  * @brief  Return the TIM OC handle state.
+  * @param  htim TIM Output Compare handle
+  * @retval HAL state
+  */
+HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim)
+{
+  return htim->State;
+}
+
+/**
+  * @brief  Return the TIM PWM handle state.
+  * @param  htim TIM handle
+  * @retval HAL state
+  */
+HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim)
+{
+  return htim->State;
+}
+
+/**
+  * @brief  Return the TIM Input Capture handle state.
+  * @param  htim TIM IC handle
+  * @retval HAL state
+  */
+HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim)
+{
+  return htim->State;
+}
+
+/**
+  * @brief  Return the TIM One Pulse Mode handle state.
+  * @param  htim TIM OPM handle
+  * @retval HAL state
+  */
+HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim)
+{
+  return htim->State;
+}
+
+/**
+  * @brief  Return the TIM Encoder Mode handle state.
+  * @param  htim TIM Encoder Interface handle
+  * @retval HAL state
+  */
+HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim)
+{
+  return htim->State;
+}
+
+/**
+  * @brief  Return the TIM Encoder Mode handle state.
+  * @param  htim TIM handle
+  * @retval Active channel
+  */
+HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(TIM_HandleTypeDef *htim)
+{
+  return htim->Channel;
+}
+
+/**
+  * @brief  Return actual state of the TIM channel.
+  * @param  htim TIM handle
+  * @param  Channel TIM Channel
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1
+  *            @arg TIM_CHANNEL_2: TIM Channel 2
+  *            @arg TIM_CHANNEL_3: TIM Channel 3
+  *            @arg TIM_CHANNEL_4: TIM Channel 4
+  *            @arg TIM_CHANNEL_5: TIM Channel 5
+  *            @arg TIM_CHANNEL_6: TIM Channel 6
+  * @retval TIM Channel state
+  */
+HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(TIM_HandleTypeDef *htim,  uint32_t Channel)
+{
+  HAL_TIM_ChannelStateTypeDef channel_state;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+  channel_state = TIM_CHANNEL_STATE_GET(htim, Channel);
+
+  return channel_state;
+}
+
+/**
+  * @brief  Return actual state of a DMA burst operation.
+  * @param  htim TIM handle
+  * @retval DMA burst state
+  */
+HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(TIM_HandleTypeDef *htim)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
+
+  return htim->DMABurstState;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Private_Functions TIM Private Functions
+  * @{
+  */
+
+/**
+  * @brief  TIM DMA error callback
+  * @param  hdma pointer to DMA handle.
+  * @retval None
+  */
+void TIM_DMAError(DMA_HandleTypeDef *hdma)
+{
+  TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+  if (hdma == htim->hdma[TIM_DMA_ID_CC1])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
+    TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+  }
+  else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
+    TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+  }
+  else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
+    TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
+  }
+  else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
+    TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
+  }
+  else
+  {
+    htim->State = HAL_TIM_STATE_READY;
+  }
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+  htim->ErrorCallback(htim);
+#else
+  HAL_TIM_ErrorCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+  htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+}
+
+/**
+  * @brief  TIM DMA Delay Pulse complete callback.
+  * @param  hdma pointer to DMA handle.
+  * @retval None
+  */
+static void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma)
+{
+  TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+  if (hdma == htim->hdma[TIM_DMA_ID_CC1])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
+
+    if (hdma->Init.Mode == DMA_NORMAL)
+    {
+      TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+    }
+  }
+  else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
+
+    if (hdma->Init.Mode == DMA_NORMAL)
+    {
+      TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+    }
+  }
+  else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
+
+    if (hdma->Init.Mode == DMA_NORMAL)
+    {
+      TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
+    }
+  }
+  else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
+
+    if (hdma->Init.Mode == DMA_NORMAL)
+    {
+      TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
+    }
+  }
+  else
+  {
+    /* nothing to do */
+  }
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+  htim->PWM_PulseFinishedCallback(htim);
+#else
+  HAL_TIM_PWM_PulseFinishedCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+  htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+}
+
+/**
+  * @brief  TIM DMA Delay Pulse half complete callback.
+  * @param  hdma pointer to DMA handle.
+  * @retval None
+  */
+void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma)
+{
+  TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+  if (hdma == htim->hdma[TIM_DMA_ID_CC1])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
+  }
+  else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
+  }
+  else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
+  }
+  else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
+  }
+  else
+  {
+    /* nothing to do */
+  }
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+  htim->PWM_PulseFinishedHalfCpltCallback(htim);
+#else
+  HAL_TIM_PWM_PulseFinishedHalfCpltCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+  htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+}
+
+/**
+  * @brief  TIM DMA Capture complete callback.
+  * @param  hdma pointer to DMA handle.
+  * @retval None
+  */
+void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma)
+{
+  TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+  if (hdma == htim->hdma[TIM_DMA_ID_CC1])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
+
+    if (hdma->Init.Mode == DMA_NORMAL)
+    {
+      TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+      TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+    }
+  }
+  else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
+
+    if (hdma->Init.Mode == DMA_NORMAL)
+    {
+      TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+      TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+    }
+  }
+  else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
+
+    if (hdma->Init.Mode == DMA_NORMAL)
+    {
+      TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
+      TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
+    }
+  }
+  else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
+
+    if (hdma->Init.Mode == DMA_NORMAL)
+    {
+      TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
+      TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
+    }
+  }
+  else
+  {
+    /* nothing to do */
+  }
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+  htim->IC_CaptureCallback(htim);
+#else
+  HAL_TIM_IC_CaptureCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+  htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+}
+
+/**
+  * @brief  TIM DMA Capture half complete callback.
+  * @param  hdma pointer to DMA handle.
+  * @retval None
+  */
+void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma)
+{
+  TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+  if (hdma == htim->hdma[TIM_DMA_ID_CC1])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
+  }
+  else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
+  }
+  else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
+  }
+  else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
+  }
+  else
+  {
+    /* nothing to do */
+  }
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+  htim->IC_CaptureHalfCpltCallback(htim);
+#else
+  HAL_TIM_IC_CaptureHalfCpltCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+  htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+}
+
+/**
+  * @brief  TIM DMA Period Elapse complete callback.
+  * @param  hdma pointer to DMA handle.
+  * @retval None
+  */
+static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma)
+{
+  TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+  if (htim->hdma[TIM_DMA_ID_UPDATE]->Init.Mode == DMA_NORMAL)
+  {
+    htim->State = HAL_TIM_STATE_READY;
+  }
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+  htim->PeriodElapsedCallback(htim);
+#else
+  HAL_TIM_PeriodElapsedCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+}
+
+/**
+  * @brief  TIM DMA Period Elapse half complete callback.
+  * @param  hdma pointer to DMA handle.
+  * @retval None
+  */
+static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma)
+{
+  TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+  htim->PeriodElapsedHalfCpltCallback(htim);
+#else
+  HAL_TIM_PeriodElapsedHalfCpltCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+}
+
+/**
+  * @brief  TIM DMA Trigger callback.
+  * @param  hdma pointer to DMA handle.
+  * @retval None
+  */
+static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma)
+{
+  TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+  if (htim->hdma[TIM_DMA_ID_TRIGGER]->Init.Mode == DMA_NORMAL)
+  {
+    htim->State = HAL_TIM_STATE_READY;
+  }
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+  htim->TriggerCallback(htim);
+#else
+  HAL_TIM_TriggerCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+}
+
+/**
+  * @brief  TIM DMA Trigger half complete callback.
+  * @param  hdma pointer to DMA handle.
+  * @retval None
+  */
+static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma)
+{
+  TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+  htim->TriggerHalfCpltCallback(htim);
+#else
+  HAL_TIM_TriggerHalfCpltCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+}
+
+/**
+  * @brief  Time Base configuration
+  * @param  TIMx TIM peripheral
+  * @param  Structure TIM Base configuration structure
+  * @retval None
+  */
+void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure)
+{
+  uint32_t tmpcr1;
+  tmpcr1 = TIMx->CR1;
+
+  /* Set TIM Time Base Unit parameters ---------------------------------------*/
+  if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
+  {
+    /* Select the Counter Mode */
+    tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
+    tmpcr1 |= Structure->CounterMode;
+  }
+
+  if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
+  {
+    /* Set the clock division */
+    tmpcr1 &= ~TIM_CR1_CKD;
+    tmpcr1 |= (uint32_t)Structure->ClockDivision;
+  }
+
+  /* Set the auto-reload preload */
+  MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload);
+
+  TIMx->CR1 = tmpcr1;
+
+  /* Set the Autoreload value */
+  TIMx->ARR = (uint32_t)Structure->Period ;
+
+  /* Set the Prescaler value */
+  TIMx->PSC = Structure->Prescaler;
+
+  if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
+  {
+    /* Set the Repetition Counter value */
+    TIMx->RCR = Structure->RepetitionCounter;
+  }
+
+  /* Generate an update event to reload the Prescaler
+     and the repetition counter (only for advanced timer) value immediately */
+  TIMx->EGR = TIM_EGR_UG;
+}
+
+/**
+  * @brief  Timer Output Compare 1 configuration
+  * @param  TIMx to select the TIM peripheral
+  * @param  OC_Config The output configuration structure
+  * @retval None
+  */
+static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
+{
+  uint32_t tmpccmrx;
+  uint32_t tmpccer;
+  uint32_t tmpcr2;
+
+  /* Disable the Channel 1: Reset the CC1E Bit */
+  TIMx->CCER &= ~TIM_CCER_CC1E;
+
+  /* Get the TIMx CCER register value */
+  tmpccer = TIMx->CCER;
+  /* Get the TIMx CR2 register value */
+  tmpcr2 =  TIMx->CR2;
+
+  /* Get the TIMx CCMR1 register value */
+  tmpccmrx = TIMx->CCMR1;
+
+  /* Reset the Output Compare Mode Bits */
+  tmpccmrx &= ~TIM_CCMR1_OC1M;
+  tmpccmrx &= ~TIM_CCMR1_CC1S;
+  /* Select the Output Compare Mode */
+  tmpccmrx |= OC_Config->OCMode;
+
+  /* Reset the Output Polarity level */
+  tmpccer &= ~TIM_CCER_CC1P;
+  /* Set the Output Compare Polarity */
+  tmpccer |= OC_Config->OCPolarity;
+
+  if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1))
+  {
+    /* Check parameters */
+    assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
+
+    /* Reset the Output N Polarity level */
+    tmpccer &= ~TIM_CCER_CC1NP;
+    /* Set the Output N Polarity */
+    tmpccer |= OC_Config->OCNPolarity;
+    /* Reset the Output N State */
+    tmpccer &= ~TIM_CCER_CC1NE;
+  }
+
+  if (IS_TIM_BREAK_INSTANCE(TIMx))
+  {
+    /* Check parameters */
+    assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
+    assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
+
+    /* Reset the Output Compare and Output Compare N IDLE State */
+    tmpcr2 &= ~TIM_CR2_OIS1;
+    tmpcr2 &= ~TIM_CR2_OIS1N;
+    /* Set the Output Idle state */
+    tmpcr2 |= OC_Config->OCIdleState;
+    /* Set the Output N Idle state */
+    tmpcr2 |= OC_Config->OCNIdleState;
+  }
+
+  /* Write to TIMx CR2 */
+  TIMx->CR2 = tmpcr2;
+
+  /* Write to TIMx CCMR1 */
+  TIMx->CCMR1 = tmpccmrx;
+
+  /* Set the Capture Compare Register value */
+  TIMx->CCR1 = OC_Config->Pulse;
+
+  /* Write to TIMx CCER */
+  TIMx->CCER = tmpccer;
+}
+
+/**
+  * @brief  Timer Output Compare 2 configuration
+  * @param  TIMx to select the TIM peripheral
+  * @param  OC_Config The output configuration structure
+  * @retval None
+  */
+void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
+{
+  uint32_t tmpccmrx;
+  uint32_t tmpccer;
+  uint32_t tmpcr2;
+
+  /* Disable the Channel 2: Reset the CC2E Bit */
+  TIMx->CCER &= ~TIM_CCER_CC2E;
+
+  /* Get the TIMx CCER register value */
+  tmpccer = TIMx->CCER;
+  /* Get the TIMx CR2 register value */
+  tmpcr2 =  TIMx->CR2;
+
+  /* Get the TIMx CCMR1 register value */
+  tmpccmrx = TIMx->CCMR1;
+
+  /* Reset the Output Compare mode and Capture/Compare selection Bits */
+  tmpccmrx &= ~TIM_CCMR1_OC2M;
+  tmpccmrx &= ~TIM_CCMR1_CC2S;
+
+  /* Select the Output Compare Mode */
+  tmpccmrx |= (OC_Config->OCMode << 8U);
+
+  /* Reset the Output Polarity level */
+  tmpccer &= ~TIM_CCER_CC2P;
+  /* Set the Output Compare Polarity */
+  tmpccer |= (OC_Config->OCPolarity << 4U);
+
+  if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2))
+  {
+    assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
+
+    /* Reset the Output N Polarity level */
+    tmpccer &= ~TIM_CCER_CC2NP;
+    /* Set the Output N Polarity */
+    tmpccer |= (OC_Config->OCNPolarity << 4U);
+    /* Reset the Output N State */
+    tmpccer &= ~TIM_CCER_CC2NE;
+
+  }
+
+  if (IS_TIM_BREAK_INSTANCE(TIMx))
+  {
+    /* Check parameters */
+    assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
+    assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
+
+    /* Reset the Output Compare and Output Compare N IDLE State */
+    tmpcr2 &= ~TIM_CR2_OIS2;
+    tmpcr2 &= ~TIM_CR2_OIS2N;
+    /* Set the Output Idle state */
+    tmpcr2 |= (OC_Config->OCIdleState << 2U);
+    /* Set the Output N Idle state */
+    tmpcr2 |= (OC_Config->OCNIdleState << 2U);
+  }
+
+  /* Write to TIMx CR2 */
+  TIMx->CR2 = tmpcr2;
+
+  /* Write to TIMx CCMR1 */
+  TIMx->CCMR1 = tmpccmrx;
+
+  /* Set the Capture Compare Register value */
+  TIMx->CCR2 = OC_Config->Pulse;
+
+  /* Write to TIMx CCER */
+  TIMx->CCER = tmpccer;
+}
+
+/**
+  * @brief  Timer Output Compare 3 configuration
+  * @param  TIMx to select the TIM peripheral
+  * @param  OC_Config The output configuration structure
+  * @retval None
+  */
+static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
+{
+  uint32_t tmpccmrx;
+  uint32_t tmpccer;
+  uint32_t tmpcr2;
+
+  /* Disable the Channel 3: Reset the CC2E Bit */
+  TIMx->CCER &= ~TIM_CCER_CC3E;
+
+  /* Get the TIMx CCER register value */
+  tmpccer = TIMx->CCER;
+  /* Get the TIMx CR2 register value */
+  tmpcr2 =  TIMx->CR2;
+
+  /* Get the TIMx CCMR2 register value */
+  tmpccmrx = TIMx->CCMR2;
+
+  /* Reset the Output Compare mode and Capture/Compare selection Bits */
+  tmpccmrx &= ~TIM_CCMR2_OC3M;
+  tmpccmrx &= ~TIM_CCMR2_CC3S;
+  /* Select the Output Compare Mode */
+  tmpccmrx |= OC_Config->OCMode;
+
+  /* Reset the Output Polarity level */
+  tmpccer &= ~TIM_CCER_CC3P;
+  /* Set the Output Compare Polarity */
+  tmpccer |= (OC_Config->OCPolarity << 8U);
+
+  if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3))
+  {
+    assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
+
+    /* Reset the Output N Polarity level */
+    tmpccer &= ~TIM_CCER_CC3NP;
+    /* Set the Output N Polarity */
+    tmpccer |= (OC_Config->OCNPolarity << 8U);
+    /* Reset the Output N State */
+    tmpccer &= ~TIM_CCER_CC3NE;
+  }
+
+  if (IS_TIM_BREAK_INSTANCE(TIMx))
+  {
+    /* Check parameters */
+    assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
+    assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
+
+    /* Reset the Output Compare and Output Compare N IDLE State */
+    tmpcr2 &= ~TIM_CR2_OIS3;
+    tmpcr2 &= ~TIM_CR2_OIS3N;
+    /* Set the Output Idle state */
+    tmpcr2 |= (OC_Config->OCIdleState << 4U);
+    /* Set the Output N Idle state */
+    tmpcr2 |= (OC_Config->OCNIdleState << 4U);
+  }
+
+  /* Write to TIMx CR2 */
+  TIMx->CR2 = tmpcr2;
+
+  /* Write to TIMx CCMR2 */
+  TIMx->CCMR2 = tmpccmrx;
+
+  /* Set the Capture Compare Register value */
+  TIMx->CCR3 = OC_Config->Pulse;
+
+  /* Write to TIMx CCER */
+  TIMx->CCER = tmpccer;
+}
+
+/**
+  * @brief  Timer Output Compare 4 configuration
+  * @param  TIMx to select the TIM peripheral
+  * @param  OC_Config The output configuration structure
+  * @retval None
+  */
+static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
+{
+  uint32_t tmpccmrx;
+  uint32_t tmpccer;
+  uint32_t tmpcr2;
+
+  /* Disable the Channel 4: Reset the CC4E Bit */
+  TIMx->CCER &= ~TIM_CCER_CC4E;
+
+  /* Get the TIMx CCER register value */
+  tmpccer = TIMx->CCER;
+  /* Get the TIMx CR2 register value */
+  tmpcr2 =  TIMx->CR2;
+
+  /* Get the TIMx CCMR2 register value */
+  tmpccmrx = TIMx->CCMR2;
+
+  /* Reset the Output Compare mode and Capture/Compare selection Bits */
+  tmpccmrx &= ~TIM_CCMR2_OC4M;
+  tmpccmrx &= ~TIM_CCMR2_CC4S;
+
+  /* Select the Output Compare Mode */
+  tmpccmrx |= (OC_Config->OCMode << 8U);
+
+  /* Reset the Output Polarity level */
+  tmpccer &= ~TIM_CCER_CC4P;
+  /* Set the Output Compare Polarity */
+  tmpccer |= (OC_Config->OCPolarity << 12U);
+
+  if (IS_TIM_BREAK_INSTANCE(TIMx))
+  {
+    /* Check parameters */
+    assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
+
+    /* Reset the Output Compare IDLE State */
+    tmpcr2 &= ~TIM_CR2_OIS4;
+
+    /* Set the Output Idle state */
+    tmpcr2 |= (OC_Config->OCIdleState << 6U);
+  }
+
+  /* Write to TIMx CR2 */
+  TIMx->CR2 = tmpcr2;
+
+  /* Write to TIMx CCMR2 */
+  TIMx->CCMR2 = tmpccmrx;
+
+  /* Set the Capture Compare Register value */
+  TIMx->CCR4 = OC_Config->Pulse;
+
+  /* Write to TIMx CCER */
+  TIMx->CCER = tmpccer;
+}
+
+/**
+  * @brief  Slave Timer configuration function
+  * @param  htim TIM handle
+  * @param  sSlaveConfig Slave timer configuration
+  * @retval None
+  */
+static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
+                                                  TIM_SlaveConfigTypeDef *sSlaveConfig)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  uint32_t tmpsmcr;
+  uint32_t tmpccmr1;
+  uint32_t tmpccer;
+
+  /* Get the TIMx SMCR register value */
+  tmpsmcr = htim->Instance->SMCR;
+
+  /* Reset the Trigger Selection Bits */
+  tmpsmcr &= ~TIM_SMCR_TS;
+  /* Set the Input Trigger source */
+  tmpsmcr |= sSlaveConfig->InputTrigger;
+
+  /* Reset the slave mode Bits */
+  tmpsmcr &= ~TIM_SMCR_SMS;
+  /* Set the slave mode */
+  tmpsmcr |= sSlaveConfig->SlaveMode;
+
+  /* Write to TIMx SMCR */
+  htim->Instance->SMCR = tmpsmcr;
+
+  /* Configure the trigger prescaler, filter, and polarity */
+  switch (sSlaveConfig->InputTrigger)
+  {
+    case TIM_TS_ETRF:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));
+      assert_param(IS_TIM_TRIGGERPRESCALER(sSlaveConfig->TriggerPrescaler));
+      assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
+      assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
+      /* Configure the ETR Trigger source */
+      TIM_ETR_SetConfig(htim->Instance,
+                        sSlaveConfig->TriggerPrescaler,
+                        sSlaveConfig->TriggerPolarity,
+                        sSlaveConfig->TriggerFilter);
+      break;
+    }
+
+    case TIM_TS_TI1F_ED:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
+      assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
+
+      if (sSlaveConfig->SlaveMode == TIM_SLAVEMODE_GATED)
+      {
+        return HAL_ERROR;
+      }
+
+      /* Disable the Channel 1: Reset the CC1E Bit */
+      tmpccer = htim->Instance->CCER;
+      htim->Instance->CCER &= ~TIM_CCER_CC1E;
+      tmpccmr1 = htim->Instance->CCMR1;
+
+      /* Set the filter */
+      tmpccmr1 &= ~TIM_CCMR1_IC1F;
+      tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4U);
+
+      /* Write to TIMx CCMR1 and CCER registers */
+      htim->Instance->CCMR1 = tmpccmr1;
+      htim->Instance->CCER = tmpccer;
+      break;
+    }
+
+    case TIM_TS_TI1FP1:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
+      assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
+      assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
+
+      /* Configure TI1 Filter and Polarity */
+      TIM_TI1_ConfigInputStage(htim->Instance,
+                               sSlaveConfig->TriggerPolarity,
+                               sSlaveConfig->TriggerFilter);
+      break;
+    }
+
+    case TIM_TS_TI2FP2:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+      assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
+      assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
+
+      /* Configure TI2 Filter and Polarity */
+      TIM_TI2_ConfigInputStage(htim->Instance,
+                               sSlaveConfig->TriggerPolarity,
+                               sSlaveConfig->TriggerFilter);
+      break;
+    }
+
+    case TIM_TS_ITR0:
+    case TIM_TS_ITR1:
+    case TIM_TS_ITR2:
+    case TIM_TS_ITR3:
+    {
+      /* Check the parameter */
+      assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+      break;
+    }
+
+    default:
+      status = HAL_ERROR;
+      break;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Configure the TI1 as Input.
+  * @param  TIMx to select the TIM peripheral.
+  * @param  TIM_ICPolarity The Input Polarity.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ICPOLARITY_RISING
+  *            @arg TIM_ICPOLARITY_FALLING
+  *            @arg TIM_ICPOLARITY_BOTHEDGE
+  * @param  TIM_ICSelection specifies the input to be used.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ICSELECTION_DIRECTTI: TIM Input 1 is selected to be connected to IC1.
+  *            @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 1 is selected to be connected to IC2.
+  *            @arg TIM_ICSELECTION_TRC: TIM Input 1 is selected to be connected to TRC.
+  * @param  TIM_ICFilter Specifies the Input Capture Filter.
+  *          This parameter must be a value between 0x00 and 0x0F.
+  * @retval None
+  * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI2FP1
+  *       (on channel2 path) is used as the input signal. Therefore CCMR1 must be
+  *        protected against un-initialized filter and polarity values.
+  */
+void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
+                       uint32_t TIM_ICFilter)
+{
+  uint32_t tmpccmr1;
+  uint32_t tmpccer;
+
+  /* Disable the Channel 1: Reset the CC1E Bit */
+  TIMx->CCER &= ~TIM_CCER_CC1E;
+  tmpccmr1 = TIMx->CCMR1;
+  tmpccer = TIMx->CCER;
+
+  /* Select the Input */
+  if (IS_TIM_CC2_INSTANCE(TIMx) != RESET)
+  {
+    tmpccmr1 &= ~TIM_CCMR1_CC1S;
+    tmpccmr1 |= TIM_ICSelection;
+  }
+  else
+  {
+    tmpccmr1 |= TIM_CCMR1_CC1S_0;
+  }
+
+  /* Set the filter */
+  tmpccmr1 &= ~TIM_CCMR1_IC1F;
+  tmpccmr1 |= ((TIM_ICFilter << 4U) & TIM_CCMR1_IC1F);
+
+  /* Select the Polarity and set the CC1E Bit */
+  tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
+  tmpccer |= (TIM_ICPolarity & (TIM_CCER_CC1P | TIM_CCER_CC1NP));
+
+  /* Write to TIMx CCMR1 and CCER registers */
+  TIMx->CCMR1 = tmpccmr1;
+  TIMx->CCER = tmpccer;
+}
+
+/**
+  * @brief  Configure the Polarity and Filter for TI1.
+  * @param  TIMx to select the TIM peripheral.
+  * @param  TIM_ICPolarity The Input Polarity.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ICPOLARITY_RISING
+  *            @arg TIM_ICPOLARITY_FALLING
+  *            @arg TIM_ICPOLARITY_BOTHEDGE
+  * @param  TIM_ICFilter Specifies the Input Capture Filter.
+  *          This parameter must be a value between 0x00 and 0x0F.
+  * @retval None
+  */
+static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
+{
+  uint32_t tmpccmr1;
+  uint32_t tmpccer;
+
+  /* Disable the Channel 1: Reset the CC1E Bit */
+  tmpccer = TIMx->CCER;
+  TIMx->CCER &= ~TIM_CCER_CC1E;
+  tmpccmr1 = TIMx->CCMR1;
+
+  /* Set the filter */
+  tmpccmr1 &= ~TIM_CCMR1_IC1F;
+  tmpccmr1 |= (TIM_ICFilter << 4U);
+
+  /* Select the Polarity and set the CC1E Bit */
+  tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
+  tmpccer |= TIM_ICPolarity;
+
+  /* Write to TIMx CCMR1 and CCER registers */
+  TIMx->CCMR1 = tmpccmr1;
+  TIMx->CCER = tmpccer;
+}
+
+/**
+  * @brief  Configure the TI2 as Input.
+  * @param  TIMx to select the TIM peripheral
+  * @param  TIM_ICPolarity The Input Polarity.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ICPOLARITY_RISING
+  *            @arg TIM_ICPOLARITY_FALLING
+  *            @arg TIM_ICPOLARITY_BOTHEDGE
+  * @param  TIM_ICSelection specifies the input to be used.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ICSELECTION_DIRECTTI: TIM Input 2 is selected to be connected to IC2.
+  *            @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 2 is selected to be connected to IC1.
+  *            @arg TIM_ICSELECTION_TRC: TIM Input 2 is selected to be connected to TRC.
+  * @param  TIM_ICFilter Specifies the Input Capture Filter.
+  *          This parameter must be a value between 0x00 and 0x0F.
+  * @retval None
+  * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI1FP2
+  *       (on channel1 path) is used as the input signal. Therefore CCMR1 must be
+  *        protected against un-initialized filter and polarity values.
+  */
+static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
+                              uint32_t TIM_ICFilter)
+{
+  uint32_t tmpccmr1;
+  uint32_t tmpccer;
+
+  /* Disable the Channel 2: Reset the CC2E Bit */
+  TIMx->CCER &= ~TIM_CCER_CC2E;
+  tmpccmr1 = TIMx->CCMR1;
+  tmpccer = TIMx->CCER;
+
+  /* Select the Input */
+  tmpccmr1 &= ~TIM_CCMR1_CC2S;
+  tmpccmr1 |= (TIM_ICSelection << 8U);
+
+  /* Set the filter */
+  tmpccmr1 &= ~TIM_CCMR1_IC2F;
+  tmpccmr1 |= ((TIM_ICFilter << 12U) & TIM_CCMR1_IC2F);
+
+  /* Select the Polarity and set the CC2E Bit */
+  tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
+  tmpccer |= ((TIM_ICPolarity << 4U) & (TIM_CCER_CC2P | TIM_CCER_CC2NP));
+
+  /* Write to TIMx CCMR1 and CCER registers */
+  TIMx->CCMR1 = tmpccmr1 ;
+  TIMx->CCER = tmpccer;
+}
+
+/**
+  * @brief  Configure the Polarity and Filter for TI2.
+  * @param  TIMx to select the TIM peripheral.
+  * @param  TIM_ICPolarity The Input Polarity.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ICPOLARITY_RISING
+  *            @arg TIM_ICPOLARITY_FALLING
+  *            @arg TIM_ICPOLARITY_BOTHEDGE
+  * @param  TIM_ICFilter Specifies the Input Capture Filter.
+  *          This parameter must be a value between 0x00 and 0x0F.
+  * @retval None
+  */
+static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
+{
+  uint32_t tmpccmr1;
+  uint32_t tmpccer;
+
+  /* Disable the Channel 2: Reset the CC2E Bit */
+  TIMx->CCER &= ~TIM_CCER_CC2E;
+  tmpccmr1 = TIMx->CCMR1;
+  tmpccer = TIMx->CCER;
+
+  /* Set the filter */
+  tmpccmr1 &= ~TIM_CCMR1_IC2F;
+  tmpccmr1 |= (TIM_ICFilter << 12U);
+
+  /* Select the Polarity and set the CC2E Bit */
+  tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
+  tmpccer |= (TIM_ICPolarity << 4U);
+
+  /* Write to TIMx CCMR1 and CCER registers */
+  TIMx->CCMR1 = tmpccmr1 ;
+  TIMx->CCER = tmpccer;
+}
+
+/**
+  * @brief  Configure the TI3 as Input.
+  * @param  TIMx to select the TIM peripheral
+  * @param  TIM_ICPolarity The Input Polarity.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ICPOLARITY_RISING
+  *            @arg TIM_ICPOLARITY_FALLING
+  *            @arg TIM_ICPOLARITY_BOTHEDGE
+  * @param  TIM_ICSelection specifies the input to be used.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ICSELECTION_DIRECTTI: TIM Input 3 is selected to be connected to IC3.
+  *            @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 3 is selected to be connected to IC4.
+  *            @arg TIM_ICSELECTION_TRC: TIM Input 3 is selected to be connected to TRC.
+  * @param  TIM_ICFilter Specifies the Input Capture Filter.
+  *          This parameter must be a value between 0x00 and 0x0F.
+  * @retval None
+  * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI3FP4
+  *       (on channel1 path) is used as the input signal. Therefore CCMR2 must be
+  *        protected against un-initialized filter and polarity values.
+  */
+static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
+                              uint32_t TIM_ICFilter)
+{
+  uint32_t tmpccmr2;
+  uint32_t tmpccer;
+
+  /* Disable the Channel 3: Reset the CC3E Bit */
+  TIMx->CCER &= ~TIM_CCER_CC3E;
+  tmpccmr2 = TIMx->CCMR2;
+  tmpccer = TIMx->CCER;
+
+  /* Select the Input */
+  tmpccmr2 &= ~TIM_CCMR2_CC3S;
+  tmpccmr2 |= TIM_ICSelection;
+
+  /* Set the filter */
+  tmpccmr2 &= ~TIM_CCMR2_IC3F;
+  tmpccmr2 |= ((TIM_ICFilter << 4U) & TIM_CCMR2_IC3F);
+
+  /* Select the Polarity and set the CC3E Bit */
+  tmpccer &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP);
+  tmpccer |= ((TIM_ICPolarity << 8U) & (TIM_CCER_CC3P | TIM_CCER_CC3NP));
+
+  /* Write to TIMx CCMR2 and CCER registers */
+  TIMx->CCMR2 = tmpccmr2;
+  TIMx->CCER = tmpccer;
+}
+
+/**
+  * @brief  Configure the TI4 as Input.
+  * @param  TIMx to select the TIM peripheral
+  * @param  TIM_ICPolarity The Input Polarity.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ICPOLARITY_RISING
+  *            @arg TIM_ICPOLARITY_FALLING
+  *            @arg TIM_ICPOLARITY_BOTHEDGE
+  * @param  TIM_ICSelection specifies the input to be used.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ICSELECTION_DIRECTTI: TIM Input 4 is selected to be connected to IC4.
+  *            @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 4 is selected to be connected to IC3.
+  *            @arg TIM_ICSELECTION_TRC: TIM Input 4 is selected to be connected to TRC.
+  * @param  TIM_ICFilter Specifies the Input Capture Filter.
+  *          This parameter must be a value between 0x00 and 0x0F.
+  * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI4FP3
+  *       (on channel1 path) is used as the input signal. Therefore CCMR2 must be
+  *        protected against un-initialized filter and polarity values.
+  * @retval None
+  */
+static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
+                              uint32_t TIM_ICFilter)
+{
+  uint32_t tmpccmr2;
+  uint32_t tmpccer;
+
+  /* Disable the Channel 4: Reset the CC4E Bit */
+  TIMx->CCER &= ~TIM_CCER_CC4E;
+  tmpccmr2 = TIMx->CCMR2;
+  tmpccer = TIMx->CCER;
+
+  /* Select the Input */
+  tmpccmr2 &= ~TIM_CCMR2_CC4S;
+  tmpccmr2 |= (TIM_ICSelection << 8U);
+
+  /* Set the filter */
+  tmpccmr2 &= ~TIM_CCMR2_IC4F;
+  tmpccmr2 |= ((TIM_ICFilter << 12U) & TIM_CCMR2_IC4F);
+
+  /* Select the Polarity and set the CC4E Bit */
+  tmpccer &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP);
+  tmpccer |= ((TIM_ICPolarity << 12U) & (TIM_CCER_CC4P | TIM_CCER_CC4NP));
+
+  /* Write to TIMx CCMR2 and CCER registers */
+  TIMx->CCMR2 = tmpccmr2;
+  TIMx->CCER = tmpccer ;
+}
+
+/**
+  * @brief  Selects the Input Trigger source
+  * @param  TIMx to select the TIM peripheral
+  * @param  InputTriggerSource The Input Trigger source.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_TS_ITR0: Internal Trigger 0
+  *            @arg TIM_TS_ITR1: Internal Trigger 1
+  *            @arg TIM_TS_ITR2: Internal Trigger 2
+  *            @arg TIM_TS_ITR3: Internal Trigger 3
+  *            @arg TIM_TS_TI1F_ED: TI1 Edge Detector
+  *            @arg TIM_TS_TI1FP1: Filtered Timer Input 1
+  *            @arg TIM_TS_TI2FP2: Filtered Timer Input 2
+  *            @arg TIM_TS_ETRF: External Trigger input
+  * @retval None
+  */
+static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource)
+{
+  uint32_t tmpsmcr;
+
+  /* Get the TIMx SMCR register value */
+  tmpsmcr = TIMx->SMCR;
+  /* Reset the TS Bits */
+  tmpsmcr &= ~TIM_SMCR_TS;
+  /* Set the Input Trigger source and the slave mode*/
+  tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1);
+  /* Write to TIMx SMCR */
+  TIMx->SMCR = tmpsmcr;
+}
+/**
+  * @brief  Configures the TIMx External Trigger (ETR).
+  * @param  TIMx to select the TIM peripheral
+  * @param  TIM_ExtTRGPrescaler The external Trigger Prescaler.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ETRPRESCALER_DIV1: ETRP Prescaler OFF.
+  *            @arg TIM_ETRPRESCALER_DIV2: ETRP frequency divided by 2.
+  *            @arg TIM_ETRPRESCALER_DIV4: ETRP frequency divided by 4.
+  *            @arg TIM_ETRPRESCALER_DIV8: ETRP frequency divided by 8.
+  * @param  TIM_ExtTRGPolarity The external Trigger Polarity.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ETRPOLARITY_INVERTED: active low or falling edge active.
+  *            @arg TIM_ETRPOLARITY_NONINVERTED: active high or rising edge active.
+  * @param  ExtTRGFilter External Trigger Filter.
+  *          This parameter must be a value between 0x00 and 0x0F
+  * @retval None
+  */
+void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler,
+                       uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
+{
+  uint32_t tmpsmcr;
+
+  tmpsmcr = TIMx->SMCR;
+
+  /* Reset the ETR Bits */
+  tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
+
+  /* Set the Prescaler, the Filter value and the Polarity */
+  tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U)));
+
+  /* Write to TIMx SMCR */
+  TIMx->SMCR = tmpsmcr;
+}
+
+/**
+  * @brief  Enables or disables the TIM Capture Compare Channel x.
+  * @param  TIMx to select the TIM peripheral
+  * @param  Channel specifies the TIM Channel
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1
+  *            @arg TIM_CHANNEL_2: TIM Channel 2
+  *            @arg TIM_CHANNEL_3: TIM Channel 3
+  *            @arg TIM_CHANNEL_4: TIM Channel 4
+  * @param  ChannelState specifies the TIM Channel CCxE bit new state.
+  *          This parameter can be: TIM_CCx_ENABLE or TIM_CCx_DISABLE.
+  * @retval None
+  */
+void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState)
+{
+  uint32_t tmp;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CC1_INSTANCE(TIMx));
+  assert_param(IS_TIM_CHANNELS(Channel));
+
+  tmp = TIM_CCER_CC1E << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */
+
+  /* Reset the CCxE Bit */
+  TIMx->CCER &= ~tmp;
+
+  /* Set or reset the CCxE Bit */
+  TIMx->CCER |= (uint32_t)(ChannelState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */
+}
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+/**
+  * @brief  Reset interrupt callbacks to the legacy weak callbacks.
+  * @param  htim pointer to a TIM_HandleTypeDef structure that contains
+  *                the configuration information for TIM module.
+  * @retval None
+  */
+void TIM_ResetCallback(TIM_HandleTypeDef *htim)
+{
+  /* Reset the TIM callback to the legacy weak callbacks */
+  htim->PeriodElapsedCallback             = HAL_TIM_PeriodElapsedCallback;
+  htim->PeriodElapsedHalfCpltCallback     = HAL_TIM_PeriodElapsedHalfCpltCallback;
+  htim->TriggerCallback                   = HAL_TIM_TriggerCallback;
+  htim->TriggerHalfCpltCallback           = HAL_TIM_TriggerHalfCpltCallback;
+  htim->IC_CaptureCallback                = HAL_TIM_IC_CaptureCallback;
+  htim->IC_CaptureHalfCpltCallback        = HAL_TIM_IC_CaptureHalfCpltCallback;
+  htim->OC_DelayElapsedCallback           = HAL_TIM_OC_DelayElapsedCallback;
+  htim->PWM_PulseFinishedCallback         = HAL_TIM_PWM_PulseFinishedCallback;
+  htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback;
+  htim->ErrorCallback                     = HAL_TIM_ErrorCallback;
+  htim->CommutationCallback               = HAL_TIMEx_CommutCallback;
+  htim->CommutationHalfCpltCallback       = HAL_TIMEx_CommutHalfCpltCallback;
+  htim->BreakCallback                     = HAL_TIMEx_BreakCallback;
+}
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+
+#endif /* HAL_TIM_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
diff --git a/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c
new file mode 100644
index 0000000..1b59f15
--- /dev/null
+++ b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c
@@ -0,0 +1,2428 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hal_tim_ex.c
+  * @author  MCD Application Team
+  * @brief   TIM HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the Timer Extended peripheral:
+  *           + Time Hall Sensor Interface Initialization
+  *           + Time Hall Sensor Interface Start
+  *           + Time Complementary signal break and dead time configuration
+  *           + Time Master and Slave synchronization configuration
+  *           + Timer remapping capabilities configuration
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2016 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  @verbatim
+  ==============================================================================
+                      ##### TIMER Extended features #####
+  ==============================================================================
+  [..]
+    The Timer Extended features include:
+    (#) Complementary outputs with programmable dead-time for :
+        (++) Output Compare
+        (++) PWM generation (Edge and Center-aligned Mode)
+        (++) One-pulse mode output
+    (#) Synchronization circuit to control the timer with external signals and to
+        interconnect several timers together.
+    (#) Break input to put the timer output signals in reset state or in a known state.
+    (#) Supports incremental (quadrature) encoder and hall-sensor circuitry for
+        positioning purposes
+
+            ##### How to use this driver #####
+  ==============================================================================
+    [..]
+     (#) Initialize the TIM low level resources by implementing the following functions
+         depending on the selected feature:
+           (++) Hall Sensor output : HAL_TIMEx_HallSensor_MspInit()
+
+     (#) Initialize the TIM low level resources :
+        (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE();
+        (##) TIM pins configuration
+            (+++) Enable the clock for the TIM GPIOs using the following function:
+              __HAL_RCC_GPIOx_CLK_ENABLE();
+            (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();
+
+     (#) The external Clock can be configured, if needed (the default clock is the
+         internal clock from the APBx), using the following function:
+         HAL_TIM_ConfigClockSource, the clock configuration should be done before
+         any start function.
+
+     (#) Configure the TIM in the desired functioning mode using one of the
+         initialization function of this driver:
+          (++) HAL_TIMEx_HallSensor_Init() and HAL_TIMEx_ConfigCommutEvent(): to use the
+               Timer Hall Sensor Interface and the commutation event with the corresponding
+               Interrupt and DMA request if needed (Note that One Timer is used to interface
+               with the Hall sensor Interface and another Timer should be used to use
+               the commutation event).
+
+     (#) Activate the TIM peripheral using one of the start functions:
+           (++) Complementary Output Compare : HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(),
+                HAL_TIMEx_OCN_Start_IT()
+           (++) Complementary PWM generation : HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(),
+                HAL_TIMEx_PWMN_Start_IT()
+           (++) Complementary One-pulse mode output : HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT()
+           (++) Hall Sensor output : HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(),
+                HAL_TIMEx_HallSensor_Start_IT().
+
+  @endverbatim
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup TIMEx TIMEx
+  * @brief TIM Extended HAL module driver
+  * @{
+  */
+
+#ifdef HAL_TIM_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+static void TIM_DMADelayPulseNCplt(DMA_HandleTypeDef *hdma);
+static void TIM_DMAErrorCCxN(DMA_HandleTypeDef *hdma);
+static void TIM_CCxNChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelNState);
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup TIMEx_Exported_Functions TIM Extended Exported Functions
+  * @{
+  */
+
+/** @defgroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions
+  * @brief    Timer Hall Sensor functions
+  *
+@verbatim
+  ==============================================================================
+                      ##### Timer Hall Sensor functions #####
+  ==============================================================================
+  [..]
+    This section provides functions allowing to:
+    (+) Initialize and configure TIM HAL Sensor.
+    (+) De-initialize TIM HAL Sensor.
+    (+) Start the Hall Sensor Interface.
+    (+) Stop the Hall Sensor Interface.
+    (+) Start the Hall Sensor Interface and enable interrupts.
+    (+) Stop the Hall Sensor Interface and disable interrupts.
+    (+) Start the Hall Sensor Interface and enable DMA transfers.
+    (+) Stop the Hall Sensor Interface and disable DMA transfers.
+
+@endverbatim
+  * @{
+  */
+/**
+  * @brief  Initializes the TIM Hall Sensor Interface and initialize the associated handle.
+  * @note   When the timer instance is initialized in Hall Sensor Interface mode,
+  *         timer channels 1 and channel 2 are reserved and cannot be used for
+  *         other purpose.
+  * @param  htim TIM Hall Sensor Interface handle
+  * @param  sConfig TIM Hall Sensor configuration structure
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef *sConfig)
+{
+  TIM_OC_InitTypeDef OC_Config;
+
+  /* Check the TIM handle allocation */
+  if (htim == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
+  assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
+  assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
+  assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity));
+  assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
+  assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
+
+  if (htim->State == HAL_TIM_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    htim->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+    /* Reset interrupt callbacks to legacy week callbacks */
+    TIM_ResetCallback(htim);
+
+    if (htim->HallSensor_MspInitCallback == NULL)
+    {
+      htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit;
+    }
+    /* Init the low level hardware : GPIO, CLOCK, NVIC */
+    htim->HallSensor_MspInitCallback(htim);
+#else
+    /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
+    HAL_TIMEx_HallSensor_MspInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+  }
+
+  /* Set the TIM state */
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  /* Configure the Time base in the Encoder Mode */
+  TIM_Base_SetConfig(htim->Instance, &htim->Init);
+
+  /* Configure the Channel 1 as Input Channel to interface with the three Outputs of the  Hall sensor */
+  TIM_TI1_SetConfig(htim->Instance, sConfig->IC1Polarity, TIM_ICSELECTION_TRC, sConfig->IC1Filter);
+
+  /* Reset the IC1PSC Bits */
+  htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
+  /* Set the IC1PSC value */
+  htim->Instance->CCMR1 |= sConfig->IC1Prescaler;
+
+  /* Enable the Hall sensor interface (XOR function of the three inputs) */
+  htim->Instance->CR2 |= TIM_CR2_TI1S;
+
+  /* Select the TIM_TS_TI1F_ED signal as Input trigger for the TIM */
+  htim->Instance->SMCR &= ~TIM_SMCR_TS;
+  htim->Instance->SMCR |= TIM_TS_TI1F_ED;
+
+  /* Use the TIM_TS_TI1F_ED signal to reset the TIM counter each edge detection */
+  htim->Instance->SMCR &= ~TIM_SMCR_SMS;
+  htim->Instance->SMCR |= TIM_SLAVEMODE_RESET;
+
+  /* Program channel 2 in PWM 2 mode with the desired Commutation_Delay*/
+  OC_Config.OCFastMode = TIM_OCFAST_DISABLE;
+  OC_Config.OCIdleState = TIM_OCIDLESTATE_RESET;
+  OC_Config.OCMode = TIM_OCMODE_PWM2;
+  OC_Config.OCNIdleState = TIM_OCNIDLESTATE_RESET;
+  OC_Config.OCNPolarity = TIM_OCNPOLARITY_HIGH;
+  OC_Config.OCPolarity = TIM_OCPOLARITY_HIGH;
+  OC_Config.Pulse = sConfig->Commutation_Delay;
+
+  TIM_OC2_SetConfig(htim->Instance, &OC_Config);
+
+  /* Select OC2REF as trigger output on TRGO: write the MMS bits in the TIMx_CR2
+    register to 101 */
+  htim->Instance->CR2 &= ~TIM_CR2_MMS;
+  htim->Instance->CR2 |= TIM_TRGO_OC2REF;
+
+  /* Initialize the DMA burst operation state */
+  htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
+
+  /* Initialize the TIM channels state */
+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+
+  /* Initialize the TIM state*/
+  htim->State = HAL_TIM_STATE_READY;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  DeInitializes the TIM Hall Sensor interface
+  * @param  htim TIM Hall Sensor Interface handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  /* Disable the TIM Peripheral Clock */
+  __HAL_TIM_DISABLE(htim);
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+  if (htim->HallSensor_MspDeInitCallback == NULL)
+  {
+    htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit;
+  }
+  /* DeInit the low level hardware */
+  htim->HallSensor_MspDeInitCallback(htim);
+#else
+  /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
+  HAL_TIMEx_HallSensor_MspDeInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+  /* Change the DMA burst operation state */
+  htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
+
+  /* Change the TIM channels state */
+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
+  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
+  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
+
+  /* Change TIM state */
+  htim->State = HAL_TIM_STATE_RESET;
+
+  /* Release Lock */
+  __HAL_UNLOCK(htim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the TIM Hall Sensor MSP.
+  * @param  htim TIM Hall Sensor Interface handle
+  * @retval None
+  */
+__weak void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIMEx_HallSensor_MspInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  DeInitializes TIM Hall Sensor MSP.
+  * @param  htim TIM Hall Sensor Interface handle
+  * @retval None
+  */
+__weak void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIMEx_HallSensor_MspDeInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Starts the TIM Hall Sensor Interface.
+  * @param  htim TIM Hall Sensor Interface handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim)
+{
+  uint32_t tmpsmcr;
+  HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
+  HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
+  HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
+  HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
+
+  /* Check the parameters */
+  assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
+
+  /* Check the TIM channels state */
+  if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+      || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
+      || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+      || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
+  {
+    return HAL_ERROR;
+  }
+
+  /* Set the TIM channels state */
+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+
+  /* Enable the Input Capture channel 1
+  (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1,
+  TIM_CHANNEL_2 and TIM_CHANNEL_3) */
+  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+
+  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+  if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+  {
+    tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+    if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+    {
+      __HAL_TIM_ENABLE(htim);
+    }
+  }
+  else
+  {
+    __HAL_TIM_ENABLE(htim);
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM Hall sensor Interface.
+  * @param  htim TIM Hall Sensor Interface handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
+
+  /* Disable the Input Capture channels 1, 2 and 3
+  (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1,
+  TIM_CHANNEL_2 and TIM_CHANNEL_3) */
+  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Set the TIM channels state */
+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Starts the TIM Hall Sensor Interface in interrupt mode.
+  * @param  htim TIM Hall Sensor Interface handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim)
+{
+  uint32_t tmpsmcr;
+  HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
+  HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
+  HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
+  HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
+
+  /* Check the parameters */
+  assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
+
+  /* Check the TIM channels state */
+  if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+      || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
+      || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+      || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
+  {
+    return HAL_ERROR;
+  }
+
+  /* Set the TIM channels state */
+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+
+  /* Enable the capture compare Interrupts 1 event */
+  __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+
+  /* Enable the Input Capture channel 1
+  (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1,
+  TIM_CHANNEL_2 and TIM_CHANNEL_3) */
+  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+
+  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+  if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+  {
+    tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+    if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+    {
+      __HAL_TIM_ENABLE(htim);
+    }
+  }
+  else
+  {
+    __HAL_TIM_ENABLE(htim);
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM Hall Sensor Interface in interrupt mode.
+  * @param  htim TIM Hall Sensor Interface handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
+
+  /* Disable the Input Capture channel 1
+  (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1,
+  TIM_CHANNEL_2 and TIM_CHANNEL_3) */
+  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+
+  /* Disable the capture compare Interrupts event */
+  __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Set the TIM channels state */
+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Starts the TIM Hall Sensor Interface in DMA mode.
+  * @param  htim TIM Hall Sensor Interface handle
+  * @param  pData The destination Buffer address.
+  * @param  Length The length of data to be transferred from TIM peripheral to memory.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
+{
+  uint32_t tmpsmcr;
+  HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
+  HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
+
+  /* Check the parameters */
+  assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
+
+  /* Set the TIM channel state */
+  if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)
+      || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY))
+  {
+    return HAL_BUSY;
+  }
+  else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY)
+           && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY))
+  {
+    if ((pData == NULL) && (Length > 0U))
+    {
+      return HAL_ERROR;
+    }
+    else
+    {
+      TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+      TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+    }
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  /* Enable the Input Capture channel 1
+  (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1,
+  TIM_CHANNEL_2 and TIM_CHANNEL_3) */
+  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+
+  /* Set the DMA Input Capture 1 Callbacks */
+  htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
+  htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+  /* Set the DMA error callback */
+  htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
+
+  /* Enable the DMA stream for Capture 1*/
+  if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length) != HAL_OK)
+  {
+    /* Return error status */
+    return HAL_ERROR;
+  }
+  /* Enable the capture compare 1 Interrupt */
+  __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
+
+  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+  if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+  {
+    tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+    if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+    {
+      __HAL_TIM_ENABLE(htim);
+    }
+  }
+  else
+  {
+    __HAL_TIM_ENABLE(htim);
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM Hall Sensor Interface in DMA mode.
+  * @param  htim TIM Hall Sensor Interface handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
+
+  /* Disable the Input Capture channel 1
+  (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1,
+  TIM_CHANNEL_2 and TIM_CHANNEL_3) */
+  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+
+
+  /* Disable the capture compare Interrupts 1 event */
+  __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
+
+  (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Set the TIM channel state */
+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIMEx_Exported_Functions_Group2 Extended Timer Complementary Output Compare functions
+  *  @brief   Timer Complementary Output Compare functions
+  *
+@verbatim
+  ==============================================================================
+              ##### Timer Complementary Output Compare functions #####
+  ==============================================================================
+  [..]
+    This section provides functions allowing to:
+    (+) Start the Complementary Output Compare/PWM.
+    (+) Stop the Complementary Output Compare/PWM.
+    (+) Start the Complementary Output Compare/PWM and enable interrupts.
+    (+) Stop the Complementary Output Compare/PWM and disable interrupts.
+    (+) Start the Complementary Output Compare/PWM and enable DMA transfers.
+    (+) Stop the Complementary Output Compare/PWM and disable DMA transfers.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Starts the TIM Output Compare signal generation on the complementary
+  *         output.
+  * @param  htim TIM Output Compare handle
+  * @param  Channel TIM Channel to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  uint32_t tmpsmcr;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+  /* Check the TIM complementary channel state */
+  if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Set the TIM complementary channel state */
+  TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+
+  /* Enable the Capture compare channel N */
+  TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
+
+  /* Enable the Main Output */
+  __HAL_TIM_MOE_ENABLE(htim);
+
+  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+  if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+  {
+    tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+    if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+    {
+      __HAL_TIM_ENABLE(htim);
+    }
+  }
+  else
+  {
+    __HAL_TIM_ENABLE(htim);
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM Output Compare signal generation on the complementary
+  *         output.
+  * @param  htim TIM handle
+  * @param  Channel TIM Channel to be disabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+  /* Disable the Capture compare channel N */
+  TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
+
+  /* Disable the Main Output */
+  __HAL_TIM_MOE_DISABLE(htim);
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Set the TIM complementary channel state */
+  TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Starts the TIM Output Compare signal generation in interrupt mode
+  *         on the complementary output.
+  * @param  htim TIM OC handle
+  * @param  Channel TIM Channel to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  uint32_t tmpsmcr;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+  /* Check the TIM complementary channel state */
+  if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Set the TIM complementary channel state */
+  TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Enable the TIM Output Compare interrupt */
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      /* Enable the TIM Output Compare interrupt */
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+      break;
+    }
+
+    case TIM_CHANNEL_3:
+    {
+      /* Enable the TIM Output Compare interrupt */
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
+      break;
+    }
+
+
+    default:
+      status = HAL_ERROR;
+      break;
+  }
+
+  if (status == HAL_OK)
+  {
+    /* Enable the TIM Break interrupt */
+    __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK);
+
+    /* Enable the Capture compare channel N */
+    TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
+
+    /* Enable the Main Output */
+    __HAL_TIM_MOE_ENABLE(htim);
+
+    /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+    if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+    {
+      tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+      if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+      {
+        __HAL_TIM_ENABLE(htim);
+      }
+    }
+    else
+    {
+      __HAL_TIM_ENABLE(htim);
+    }
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  Stops the TIM Output Compare signal generation in interrupt mode
+  *         on the complementary output.
+  * @param  htim TIM Output Compare handle
+  * @param  Channel TIM Channel to be disabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  uint32_t tmpccer;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Disable the TIM Output Compare interrupt */
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      /* Disable the TIM Output Compare interrupt */
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+      break;
+    }
+
+    case TIM_CHANNEL_3:
+    {
+      /* Disable the TIM Output Compare interrupt */
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
+      break;
+    }
+
+    default:
+      status = HAL_ERROR;
+      break;
+  }
+
+  if (status == HAL_OK)
+  {
+    /* Disable the Capture compare channel N */
+    TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
+
+    /* Disable the TIM Break interrupt (only if no more channel is active) */
+    tmpccer = htim->Instance->CCER;
+    if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == (uint32_t)RESET)
+    {
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);
+    }
+
+    /* Disable the Main Output */
+    __HAL_TIM_MOE_DISABLE(htim);
+
+    /* Disable the Peripheral */
+    __HAL_TIM_DISABLE(htim);
+
+    /* Set the TIM complementary channel state */
+    TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  Starts the TIM Output Compare signal generation in DMA mode
+  *         on the complementary output.
+  * @param  htim TIM Output Compare handle
+  * @param  Channel TIM Channel to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  * @param  pData The source Buffer address.
+  * @param  Length The length of data to be transferred from memory to TIM peripheral
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  uint32_t tmpsmcr;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+  /* Set the TIM complementary channel state */
+  if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY)
+  {
+    return HAL_BUSY;
+  }
+  else if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY)
+  {
+    if ((pData == NULL) && (Length > 0U))
+    {
+      return HAL_ERROR;
+    }
+    else
+    {
+      TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+    }
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Set the DMA compare callbacks */
+      htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseNCplt;
+      htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAErrorCCxN ;
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1,
+                           Length) != HAL_OK)
+      {
+        /* Return error status */
+        return HAL_ERROR;
+      }
+      /* Enable the TIM Output Compare DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      /* Set the DMA compare callbacks */
+      htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseNCplt;
+      htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAErrorCCxN ;
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2,
+                           Length) != HAL_OK)
+      {
+        /* Return error status */
+        return HAL_ERROR;
+      }
+      /* Enable the TIM Output Compare DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
+      break;
+    }
+
+    case TIM_CHANNEL_3:
+    {
+      /* Set the DMA compare callbacks */
+      htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseNCplt;
+      htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAErrorCCxN ;
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,
+                           Length) != HAL_OK)
+      {
+        /* Return error status */
+        return HAL_ERROR;
+      }
+      /* Enable the TIM Output Compare DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
+      break;
+    }
+
+    default:
+      status = HAL_ERROR;
+      break;
+  }
+
+  if (status == HAL_OK)
+  {
+    /* Enable the Capture compare channel N */
+    TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
+
+    /* Enable the Main Output */
+    __HAL_TIM_MOE_ENABLE(htim);
+
+    /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+    if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+    {
+      tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+      if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+      {
+        __HAL_TIM_ENABLE(htim);
+      }
+    }
+    else
+    {
+      __HAL_TIM_ENABLE(htim);
+    }
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  Stops the TIM Output Compare signal generation in DMA mode
+  *         on the complementary output.
+  * @param  htim TIM Output Compare handle
+  * @param  Channel TIM Channel to be disabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Disable the TIM Output Compare DMA request */
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      /* Disable the TIM Output Compare DMA request */
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
+      break;
+    }
+
+    case TIM_CHANNEL_3:
+    {
+      /* Disable the TIM Output Compare DMA request */
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
+      break;
+    }
+
+    default:
+      status = HAL_ERROR;
+      break;
+  }
+
+  if (status == HAL_OK)
+  {
+    /* Disable the Capture compare channel N */
+    TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
+
+    /* Disable the Main Output */
+    __HAL_TIM_MOE_DISABLE(htim);
+
+    /* Disable the Peripheral */
+    __HAL_TIM_DISABLE(htim);
+
+    /* Set the TIM complementary channel state */
+    TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIMEx_Exported_Functions_Group3 Extended Timer Complementary PWM functions
+  * @brief    Timer Complementary PWM functions
+  *
+@verbatim
+  ==============================================================================
+                 ##### Timer Complementary PWM functions #####
+  ==============================================================================
+  [..]
+    This section provides functions allowing to:
+    (+) Start the Complementary PWM.
+    (+) Stop the Complementary PWM.
+    (+) Start the Complementary PWM and enable interrupts.
+    (+) Stop the Complementary PWM and disable interrupts.
+    (+) Start the Complementary PWM and enable DMA transfers.
+    (+) Stop the Complementary PWM and disable DMA transfers.
+    (+) Start the Complementary Input Capture measurement.
+    (+) Stop the Complementary Input Capture.
+    (+) Start the Complementary Input Capture and enable interrupts.
+    (+) Stop the Complementary Input Capture and disable interrupts.
+    (+) Start the Complementary Input Capture and enable DMA transfers.
+    (+) Stop the Complementary Input Capture and disable DMA transfers.
+    (+) Start the Complementary One Pulse generation.
+    (+) Stop the Complementary One Pulse.
+    (+) Start the Complementary One Pulse and enable interrupts.
+    (+) Stop the Complementary One Pulse and disable interrupts.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Starts the PWM signal generation on the complementary output.
+  * @param  htim TIM handle
+  * @param  Channel TIM Channel to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  uint32_t tmpsmcr;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+  /* Check the TIM complementary channel state */
+  if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Set the TIM complementary channel state */
+  TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+
+  /* Enable the complementary PWM output  */
+  TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
+
+  /* Enable the Main Output */
+  __HAL_TIM_MOE_ENABLE(htim);
+
+  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+  if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+  {
+    tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+    if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+    {
+      __HAL_TIM_ENABLE(htim);
+    }
+  }
+  else
+  {
+    __HAL_TIM_ENABLE(htim);
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the PWM signal generation on the complementary output.
+  * @param  htim TIM handle
+  * @param  Channel TIM Channel to be disabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+  /* Disable the complementary PWM output  */
+  TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
+
+  /* Disable the Main Output */
+  __HAL_TIM_MOE_DISABLE(htim);
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Set the TIM complementary channel state */
+  TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Starts the PWM signal generation in interrupt mode on the
+  *         complementary output.
+  * @param  htim TIM handle
+  * @param  Channel TIM Channel to be disabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  uint32_t tmpsmcr;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+  /* Check the TIM complementary channel state */
+  if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Set the TIM complementary channel state */
+  TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Enable the TIM Capture/Compare 1 interrupt */
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      /* Enable the TIM Capture/Compare 2 interrupt */
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+      break;
+    }
+
+    case TIM_CHANNEL_3:
+    {
+      /* Enable the TIM Capture/Compare 3 interrupt */
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
+      break;
+    }
+
+    default:
+      status = HAL_ERROR;
+      break;
+  }
+
+  if (status == HAL_OK)
+  {
+    /* Enable the TIM Break interrupt */
+    __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK);
+
+    /* Enable the complementary PWM output  */
+    TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
+
+    /* Enable the Main Output */
+    __HAL_TIM_MOE_ENABLE(htim);
+
+    /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+    if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+    {
+      tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+      if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+      {
+        __HAL_TIM_ENABLE(htim);
+      }
+    }
+    else
+    {
+      __HAL_TIM_ENABLE(htim);
+    }
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  Stops the PWM signal generation in interrupt mode on the
+  *         complementary output.
+  * @param  htim TIM handle
+  * @param  Channel TIM Channel to be disabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  uint32_t tmpccer;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Disable the TIM Capture/Compare 1 interrupt */
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      /* Disable the TIM Capture/Compare 2 interrupt */
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+      break;
+    }
+
+    case TIM_CHANNEL_3:
+    {
+      /* Disable the TIM Capture/Compare 3 interrupt */
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
+      break;
+    }
+
+    default:
+      status = HAL_ERROR;
+      break;
+  }
+
+  if (status == HAL_OK)
+  {
+    /* Disable the complementary PWM output  */
+    TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
+
+    /* Disable the TIM Break interrupt (only if no more channel is active) */
+    tmpccer = htim->Instance->CCER;
+    if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == (uint32_t)RESET)
+    {
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);
+    }
+
+    /* Disable the Main Output */
+    __HAL_TIM_MOE_DISABLE(htim);
+
+    /* Disable the Peripheral */
+    __HAL_TIM_DISABLE(htim);
+
+    /* Set the TIM complementary channel state */
+    TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  Starts the TIM PWM signal generation in DMA mode on the
+  *         complementary output
+  * @param  htim TIM handle
+  * @param  Channel TIM Channel to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  * @param  pData The source Buffer address.
+  * @param  Length The length of data to be transferred from memory to TIM peripheral
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  uint32_t tmpsmcr;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+  /* Set the TIM complementary channel state */
+  if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY)
+  {
+    return HAL_BUSY;
+  }
+  else if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY)
+  {
+    if ((pData == NULL) && (Length > 0U))
+    {
+      return HAL_ERROR;
+    }
+    else
+    {
+      TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+    }
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Set the DMA compare callbacks */
+      htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseNCplt;
+      htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAErrorCCxN ;
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1,
+                           Length) != HAL_OK)
+      {
+        /* Return error status */
+        return HAL_ERROR;
+      }
+      /* Enable the TIM Capture/Compare 1 DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      /* Set the DMA compare callbacks */
+      htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseNCplt;
+      htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAErrorCCxN ;
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2,
+                           Length) != HAL_OK)
+      {
+        /* Return error status */
+        return HAL_ERROR;
+      }
+      /* Enable the TIM Capture/Compare 2 DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
+      break;
+    }
+
+    case TIM_CHANNEL_3:
+    {
+      /* Set the DMA compare callbacks */
+      htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseNCplt;
+      htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAErrorCCxN ;
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,
+                           Length) != HAL_OK)
+      {
+        /* Return error status */
+        return HAL_ERROR;
+      }
+      /* Enable the TIM Capture/Compare 3 DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
+      break;
+    }
+
+    default:
+      status = HAL_ERROR;
+      break;
+  }
+
+  if (status == HAL_OK)
+  {
+    /* Enable the complementary PWM output  */
+    TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
+
+    /* Enable the Main Output */
+    __HAL_TIM_MOE_ENABLE(htim);
+
+    /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+    if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+    {
+      tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+      if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+      {
+        __HAL_TIM_ENABLE(htim);
+      }
+    }
+    else
+    {
+      __HAL_TIM_ENABLE(htim);
+    }
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  Stops the TIM PWM signal generation in DMA mode on the complementary
+  *         output
+  * @param  htim TIM handle
+  * @param  Channel TIM Channel to be disabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Disable the TIM Capture/Compare 1 DMA request */
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      /* Disable the TIM Capture/Compare 2 DMA request */
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
+      break;
+    }
+
+    case TIM_CHANNEL_3:
+    {
+      /* Disable the TIM Capture/Compare 3 DMA request */
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
+      break;
+    }
+
+    default:
+      status = HAL_ERROR;
+      break;
+  }
+
+  if (status == HAL_OK)
+  {
+    /* Disable the complementary PWM output */
+    TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
+
+    /* Disable the Main Output */
+    __HAL_TIM_MOE_DISABLE(htim);
+
+    /* Disable the Peripheral */
+    __HAL_TIM_DISABLE(htim);
+
+    /* Set the TIM complementary channel state */
+    TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIMEx_Exported_Functions_Group4 Extended Timer Complementary One Pulse functions
+  * @brief    Timer Complementary One Pulse functions
+  *
+@verbatim
+  ==============================================================================
+                ##### Timer Complementary One Pulse functions #####
+  ==============================================================================
+  [..]
+    This section provides functions allowing to:
+    (+) Start the Complementary One Pulse generation.
+    (+) Stop the Complementary One Pulse.
+    (+) Start the Complementary One Pulse and enable interrupts.
+    (+) Stop the Complementary One Pulse and disable interrupts.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Starts the TIM One Pulse signal generation on the complementary
+  *         output.
+  * @note OutputChannel must match the pulse output channel chosen when calling
+  *       @ref HAL_TIM_OnePulse_ConfigChannel().
+  * @param  htim TIM One Pulse handle
+  * @param  OutputChannel pulse output channel to enable
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
+{
+  uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1;
+  HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
+  HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
+  HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
+  HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
+
+  /* Check the TIM channels state */
+  if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+      || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
+      || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+      || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
+  {
+    return HAL_ERROR;
+  }
+
+  /* Set the TIM channels state */
+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+
+  /* Enable the complementary One Pulse output channel and the Input Capture channel */
+  TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE);
+  TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_ENABLE);
+
+  /* Enable the Main Output */
+  __HAL_TIM_MOE_ENABLE(htim);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM One Pulse signal generation on the complementary
+  *         output.
+  * @note OutputChannel must match the pulse output channel chosen when calling
+  *       @ref HAL_TIM_OnePulse_ConfigChannel().
+  * @param  htim TIM One Pulse handle
+  * @param  OutputChannel pulse output channel to disable
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
+{
+  uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
+
+  /* Disable the complementary One Pulse output channel and the Input Capture channel */
+  TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE);
+  TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_DISABLE);
+
+  /* Disable the Main Output */
+  __HAL_TIM_MOE_DISABLE(htim);
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Set the TIM  channels state */
+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Starts the TIM One Pulse signal generation in interrupt mode on the
+  *         complementary channel.
+  * @note OutputChannel must match the pulse output channel chosen when calling
+  *       @ref HAL_TIM_OnePulse_ConfigChannel().
+  * @param  htim TIM One Pulse handle
+  * @param  OutputChannel pulse output channel to enable
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
+{
+  uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1;
+  HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
+  HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
+  HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
+  HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
+
+  /* Check the TIM channels state */
+  if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+      || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
+      || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+      || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
+  {
+    return HAL_ERROR;
+  }
+
+  /* Set the TIM channels state */
+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+
+  /* Enable the TIM Capture/Compare 1 interrupt */
+  __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+
+  /* Enable the TIM Capture/Compare 2 interrupt */
+  __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+
+  /* Enable the complementary One Pulse output channel and the Input Capture channel */
+  TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE);
+  TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_ENABLE);
+
+  /* Enable the Main Output */
+  __HAL_TIM_MOE_ENABLE(htim);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM One Pulse signal generation in interrupt mode on the
+  *         complementary channel.
+  * @note OutputChannel must match the pulse output channel chosen when calling
+  *       @ref HAL_TIM_OnePulse_ConfigChannel().
+  * @param  htim TIM One Pulse handle
+  * @param  OutputChannel pulse output channel to disable
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
+{
+  uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
+
+  /* Disable the TIM Capture/Compare 1 interrupt */
+  __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+
+  /* Disable the TIM Capture/Compare 2 interrupt */
+  __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+
+  /* Disable the complementary One Pulse output channel and the Input Capture channel */
+  TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE);
+  TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_DISABLE);
+
+  /* Disable the Main Output */
+  __HAL_TIM_MOE_DISABLE(htim);
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Set the TIM  channels state */
+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions
+  * @brief    Peripheral Control functions
+  *
+@verbatim
+  ==============================================================================
+                    ##### Peripheral Control functions #####
+  ==============================================================================
+  [..]
+    This section provides functions allowing to:
+      (+) Configure the commutation event in case of use of the Hall sensor interface.
+      (+) Configure Output channels for OC and PWM mode.
+
+      (+) Configure Complementary channels, break features and dead time.
+      (+) Configure Master synchronization.
+      (+) Configure timer remapping capabilities.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Configure the TIM commutation event sequence.
+  * @note  This function is mandatory to use the commutation event in order to
+  *        update the configuration at each commutation detection on the TRGI input of the Timer,
+  *        the typical use of this feature is with the use of another Timer(interface Timer)
+  *        configured in Hall sensor interface, this interface Timer will generate the
+  *        commutation at its TRGO output (connected to Timer used in this function) each time
+  *        the TI1 of the Interface Timer detect a commutation at its input TI1.
+  * @param  htim TIM handle
+  * @param  InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor
+  *          This parameter can be one of the following values:
+  *            @arg TIM_TS_ITR0: Internal trigger 0 selected
+  *            @arg TIM_TS_ITR1: Internal trigger 1 selected
+  *            @arg TIM_TS_ITR2: Internal trigger 2 selected
+  *            @arg TIM_TS_ITR3: Internal trigger 3 selected
+  *            @arg TIM_TS_NONE: No trigger is needed
+  * @param  CommutationSource the Commutation Event source
+  *          This parameter can be one of the following values:
+  *            @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
+  *            @arg TIM_COMMUTATION_SOFTWARE:  Commutation source is set by software using the COMG bit
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t  InputTrigger,
+                                              uint32_t  CommutationSource)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));
+
+  __HAL_LOCK(htim);
+
+  if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
+      (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3))
+  {
+    /* Select the Input trigger */
+    htim->Instance->SMCR &= ~TIM_SMCR_TS;
+    htim->Instance->SMCR |= InputTrigger;
+  }
+
+  /* Select the Capture Compare preload feature */
+  htim->Instance->CR2 |= TIM_CR2_CCPC;
+  /* Select the Commutation event source */
+  htim->Instance->CR2 &= ~TIM_CR2_CCUS;
+  htim->Instance->CR2 |= CommutationSource;
+
+  /* Disable Commutation Interrupt */
+  __HAL_TIM_DISABLE_IT(htim, TIM_IT_COM);
+
+  /* Disable Commutation DMA request */
+  __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_COM);
+
+  __HAL_UNLOCK(htim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Configure the TIM commutation event sequence with interrupt.
+  * @note  This function is mandatory to use the commutation event in order to
+  *        update the configuration at each commutation detection on the TRGI input of the Timer,
+  *        the typical use of this feature is with the use of another Timer(interface Timer)
+  *        configured in Hall sensor interface, this interface Timer will generate the
+  *        commutation at its TRGO output (connected to Timer used in this function) each time
+  *        the TI1 of the Interface Timer detect a commutation at its input TI1.
+  * @param  htim TIM handle
+  * @param  InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor
+  *          This parameter can be one of the following values:
+  *            @arg TIM_TS_ITR0: Internal trigger 0 selected
+  *            @arg TIM_TS_ITR1: Internal trigger 1 selected
+  *            @arg TIM_TS_ITR2: Internal trigger 2 selected
+  *            @arg TIM_TS_ITR3: Internal trigger 3 selected
+  *            @arg TIM_TS_NONE: No trigger is needed
+  * @param  CommutationSource the Commutation Event source
+  *          This parameter can be one of the following values:
+  *            @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
+  *            @arg TIM_COMMUTATION_SOFTWARE:  Commutation source is set by software using the COMG bit
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32_t  InputTrigger,
+                                                 uint32_t  CommutationSource)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));
+
+  __HAL_LOCK(htim);
+
+  if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
+      (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3))
+  {
+    /* Select the Input trigger */
+    htim->Instance->SMCR &= ~TIM_SMCR_TS;
+    htim->Instance->SMCR |= InputTrigger;
+  }
+
+  /* Select the Capture Compare preload feature */
+  htim->Instance->CR2 |= TIM_CR2_CCPC;
+  /* Select the Commutation event source */
+  htim->Instance->CR2 &= ~TIM_CR2_CCUS;
+  htim->Instance->CR2 |= CommutationSource;
+
+  /* Disable Commutation DMA request */
+  __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_COM);
+
+  /* Enable the Commutation Interrupt */
+  __HAL_TIM_ENABLE_IT(htim, TIM_IT_COM);
+
+  __HAL_UNLOCK(htim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Configure the TIM commutation event sequence with DMA.
+  * @note  This function is mandatory to use the commutation event in order to
+  *        update the configuration at each commutation detection on the TRGI input of the Timer,
+  *        the typical use of this feature is with the use of another Timer(interface Timer)
+  *        configured in Hall sensor interface, this interface Timer will generate the
+  *        commutation at its TRGO output (connected to Timer used in this function) each time
+  *        the TI1 of the Interface Timer detect a commutation at its input TI1.
+  * @note  The user should configure the DMA in his own software, in This function only the COMDE bit is set
+  * @param  htim TIM handle
+  * @param  InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor
+  *          This parameter can be one of the following values:
+  *            @arg TIM_TS_ITR0: Internal trigger 0 selected
+  *            @arg TIM_TS_ITR1: Internal trigger 1 selected
+  *            @arg TIM_TS_ITR2: Internal trigger 2 selected
+  *            @arg TIM_TS_ITR3: Internal trigger 3 selected
+  *            @arg TIM_TS_NONE: No trigger is needed
+  * @param  CommutationSource the Commutation Event source
+  *          This parameter can be one of the following values:
+  *            @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
+  *            @arg TIM_COMMUTATION_SOFTWARE:  Commutation source is set by software using the COMG bit
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint32_t  InputTrigger,
+                                                  uint32_t  CommutationSource)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));
+
+  __HAL_LOCK(htim);
+
+  if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
+      (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3))
+  {
+    /* Select the Input trigger */
+    htim->Instance->SMCR &= ~TIM_SMCR_TS;
+    htim->Instance->SMCR |= InputTrigger;
+  }
+
+  /* Select the Capture Compare preload feature */
+  htim->Instance->CR2 |= TIM_CR2_CCPC;
+  /* Select the Commutation event source */
+  htim->Instance->CR2 &= ~TIM_CR2_CCUS;
+  htim->Instance->CR2 |= CommutationSource;
+
+  /* Enable the Commutation DMA Request */
+  /* Set the DMA Commutation Callback */
+  htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt;
+  htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback = TIMEx_DMACommutationHalfCplt;
+  /* Set the DMA error callback */
+  htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError;
+
+  /* Disable Commutation Interrupt */
+  __HAL_TIM_DISABLE_IT(htim, TIM_IT_COM);
+
+  /* Enable the Commutation DMA Request */
+  __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_COM);
+
+  __HAL_UNLOCK(htim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Configures the TIM in master mode.
+  * @param  htim TIM handle.
+  * @param  sMasterConfig pointer to a TIM_MasterConfigTypeDef structure that
+  *         contains the selected trigger output (TRGO) and the Master/Slave
+  *         mode.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
+                                                        TIM_MasterConfigTypeDef *sMasterConfig)
+{
+  uint32_t tmpcr2;
+  uint32_t tmpsmcr;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger));
+  assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode));
+
+  /* Check input state */
+  __HAL_LOCK(htim);
+
+  /* Change the handler state */
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  /* Get the TIMx CR2 register value */
+  tmpcr2 = htim->Instance->CR2;
+
+  /* Get the TIMx SMCR register value */
+  tmpsmcr = htim->Instance->SMCR;
+
+  /* Reset the MMS Bits */
+  tmpcr2 &= ~TIM_CR2_MMS;
+  /* Select the TRGO source */
+  tmpcr2 |=  sMasterConfig->MasterOutputTrigger;
+
+  /* Update TIMx CR2 */
+  htim->Instance->CR2 = tmpcr2;
+
+  if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+  {
+    /* Reset the MSM Bit */
+    tmpsmcr &= ~TIM_SMCR_MSM;
+    /* Set master mode */
+    tmpsmcr |= sMasterConfig->MasterSlaveMode;
+
+    /* Update TIMx SMCR */
+    htim->Instance->SMCR = tmpsmcr;
+  }
+
+  /* Change the htim state */
+  htim->State = HAL_TIM_STATE_READY;
+
+  __HAL_UNLOCK(htim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Configures the Break feature, dead time, Lock level, OSSI/OSSR State
+  *         and the AOE(automatic output enable).
+  * @param  htim TIM handle
+  * @param  sBreakDeadTimeConfig pointer to a TIM_ConfigBreakDeadConfigTypeDef structure that
+  *         contains the BDTR Register configuration  information for the TIM peripheral.
+  * @note   Interrupts can be generated when an active level is detected on the
+  *         break input, the break 2 input or the system break input. Break
+  *         interrupt can be enabled by calling the @ref __HAL_TIM_ENABLE_IT macro.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,
+                                                TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig)
+{
+  /* Keep this variable initialized to 0 as it is used to configure BDTR register */
+  uint32_t tmpbdtr = 0U;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_OSSR_STATE(sBreakDeadTimeConfig->OffStateRunMode));
+  assert_param(IS_TIM_OSSI_STATE(sBreakDeadTimeConfig->OffStateIDLEMode));
+  assert_param(IS_TIM_LOCK_LEVEL(sBreakDeadTimeConfig->LockLevel));
+  assert_param(IS_TIM_DEADTIME(sBreakDeadTimeConfig->DeadTime));
+  assert_param(IS_TIM_BREAK_STATE(sBreakDeadTimeConfig->BreakState));
+  assert_param(IS_TIM_BREAK_POLARITY(sBreakDeadTimeConfig->BreakPolarity));
+  assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(sBreakDeadTimeConfig->AutomaticOutput));
+
+  /* Check input state */
+  __HAL_LOCK(htim);
+
+  /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
+     the OSSI State, the dead time value and the Automatic Output Enable Bit */
+
+  /* Set the BDTR bits */
+  MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, sBreakDeadTimeConfig->DeadTime);
+  MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, sBreakDeadTimeConfig->LockLevel);
+  MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, sBreakDeadTimeConfig->OffStateIDLEMode);
+  MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, sBreakDeadTimeConfig->OffStateRunMode);
+  MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, sBreakDeadTimeConfig->BreakState);
+  MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, sBreakDeadTimeConfig->BreakPolarity);
+  MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, sBreakDeadTimeConfig->AutomaticOutput);
+
+
+  /* Set TIMx_BDTR */
+  htim->Instance->BDTR = tmpbdtr;
+
+  __HAL_UNLOCK(htim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Configures the TIMx Remapping input capabilities.
+  * @param  htim TIM handle.
+  * @param  Remap specifies the TIM remapping source.
+  *         For TIM1, the parameter can have the following values:                   (**)
+  *           @arg TIM_TIM1_TIM3_TRGO:  TIM1 ITR2 is connected to TIM3 TRGO
+  *           @arg TIM_TIM1_LPTIM:      TIM1 ITR2 is connected to LPTIM1 output
+  *
+  *         For TIM2, the parameter can have the following values:                   (**)
+  *           @arg TIM_TIM2_TIM8_TRGO:  TIM2 ITR1 is connected to TIM8 TRGO          (*)
+  *           @arg TIM_TIM2_ETH_PTP:    TIM2 ITR1 is connected to PTP trigger output (*)
+  *           @arg TIM_TIM2_USBFS_SOF:  TIM2 ITR1 is connected to OTG FS SOF
+  *           @arg TIM_TIM2_USBHS_SOF:  TIM2 ITR1 is connected to OTG FS SOF
+  *
+  *         For TIM5, the parameter can have the following values:
+  *           @arg TIM_TIM5_GPIO:       TIM5 TI4 is connected to GPIO
+  *           @arg TIM_TIM5_LSI:        TIM5 TI4 is connected to LSI
+  *           @arg TIM_TIM5_LSE:        TIM5 TI4 is connected to LSE
+  *           @arg TIM_TIM5_RTC:        TIM5 TI4 is connected to the RTC wakeup interrupt
+  *           @arg TIM_TIM5_TIM3_TRGO:  TIM5 ITR1 is connected to TIM3 TRGO          (*)
+  *           @arg TIM_TIM5_LPTIM:      TIM5 ITR1 is connected to LPTIM1 output      (*)
+  *
+  *         For TIM9, the parameter can have the following values:                   (**)
+  *           @arg TIM_TIM9_TIM3_TRGO:  TIM9 ITR1 is connected to TIM3 TRGO
+  *           @arg TIM_TIM9_LPTIM:      TIM9 ITR1 is connected to LPTIM1 output
+  *
+  *         For TIM11, the parameter can have the following values:
+  *           @arg TIM_TIM11_GPIO:     TIM11 TI1 is connected to GPIO
+  *           @arg TIM_TIM11_HSE:      TIM11 TI1 is connected to HSE_RTC clock
+  *           @arg TIM_TIM11_SPDIFRX:  TIM11 TI1 is connected to SPDIFRX_FRAME_SYNC  (*)
+  *
+  *         (*)  Value not defined in all devices. \n
+  *         (**) Register not available in all devices.
+  *
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap)
+{
+
+  /* Check parameters */
+  assert_param(IS_TIM_REMAP(htim->Instance, Remap));
+
+  __HAL_LOCK(htim);
+
+#if defined(LPTIM_OR_TIM1_ITR2_RMP) && defined(LPTIM_OR_TIM5_ITR1_RMP) && defined(LPTIM_OR_TIM9_ITR1_RMP)
+  if ((Remap & LPTIM_REMAP_MASK) == LPTIM_REMAP_MASK)
+  {
+    /* Connect TIMx internal trigger to LPTIM1 output */
+    __HAL_RCC_LPTIM1_CLK_ENABLE();
+    MODIFY_REG(LPTIM1->OR,
+               (LPTIM_OR_TIM1_ITR2_RMP | LPTIM_OR_TIM5_ITR1_RMP | LPTIM_OR_TIM9_ITR1_RMP),
+               Remap & ~(LPTIM_REMAP_MASK));
+  }
+  else
+  {
+    /* Set the Timer remapping configuration */
+    WRITE_REG(htim->Instance->OR, Remap);
+  }
+#else
+  /* Set the Timer remapping configuration */
+  WRITE_REG(htim->Instance->OR, Remap);
+#endif /* LPTIM_OR_TIM1_ITR2_RMP &&  LPTIM_OR_TIM5_ITR1_RMP && LPTIM_OR_TIM9_ITR1_RMP */
+
+  __HAL_UNLOCK(htim);
+
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIMEx_Exported_Functions_Group6 Extended Callbacks functions
+  * @brief    Extended Callbacks functions
+  *
+@verbatim
+  ==============================================================================
+                    ##### Extended Callbacks functions #####
+  ==============================================================================
+  [..]
+    This section provides Extended TIM callback functions:
+    (+) Timer Commutation callback
+    (+) Timer Break callback
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Hall commutation changed callback in non-blocking mode
+  * @param  htim TIM handle
+  * @retval None
+  */
+__weak void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIMEx_CommutCallback could be implemented in the user file
+   */
+}
+/**
+  * @brief  Hall commutation changed half complete callback in non-blocking mode
+  * @param  htim TIM handle
+  * @retval None
+  */
+__weak void HAL_TIMEx_CommutHalfCpltCallback(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIMEx_CommutHalfCpltCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Hall Break detection callback in non-blocking mode
+  * @param  htim TIM handle
+  * @retval None
+  */
+__weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIMEx_BreakCallback could be implemented in the user file
+   */
+}
+/**
+  * @}
+  */
+
+/** @defgroup TIMEx_Exported_Functions_Group7 Extended Peripheral State functions
+  * @brief    Extended Peripheral State functions
+  *
+@verbatim
+  ==============================================================================
+                ##### Extended Peripheral State functions #####
+  ==============================================================================
+  [..]
+    This subsection permits to get in run-time the status of the peripheral
+    and the data flow.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Return the TIM Hall Sensor interface handle state.
+  * @param  htim TIM Hall Sensor handle
+  * @retval HAL state
+  */
+HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim)
+{
+  return htim->State;
+}
+
+/**
+  * @brief  Return actual state of the TIM complementary channel.
+  * @param  htim TIM handle
+  * @param  ChannelN TIM Complementary channel
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1
+  *            @arg TIM_CHANNEL_2: TIM Channel 2
+  *            @arg TIM_CHANNEL_3: TIM Channel 3
+  * @retval TIM Complementary channel state
+  */
+HAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState(TIM_HandleTypeDef *htim,  uint32_t ChannelN)
+{
+  HAL_TIM_ChannelStateTypeDef channel_state;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, ChannelN));
+
+  channel_state = TIM_CHANNEL_N_STATE_GET(htim, ChannelN);
+
+  return channel_state;
+}
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup TIMEx_Private_Functions TIM Extended Private Functions
+  * @{
+  */
+
+/**
+  * @brief  TIM DMA Commutation callback.
+  * @param  hdma pointer to DMA handle.
+  * @retval None
+  */
+void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma)
+{
+  TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+  /* Change the htim state */
+  htim->State = HAL_TIM_STATE_READY;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+  htim->CommutationCallback(htim);
+#else
+  HAL_TIMEx_CommutCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+}
+
+/**
+  * @brief  TIM DMA Commutation half complete callback.
+  * @param  hdma pointer to DMA handle.
+  * @retval None
+  */
+void TIMEx_DMACommutationHalfCplt(DMA_HandleTypeDef *hdma)
+{
+  TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+  /* Change the htim state */
+  htim->State = HAL_TIM_STATE_READY;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+  htim->CommutationHalfCpltCallback(htim);
+#else
+  HAL_TIMEx_CommutHalfCpltCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+}
+
+
+/**
+  * @brief  TIM DMA Delay Pulse complete callback (complementary channel).
+  * @param  hdma pointer to DMA handle.
+  * @retval None
+  */
+static void TIM_DMADelayPulseNCplt(DMA_HandleTypeDef *hdma)
+{
+  TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+  if (hdma == htim->hdma[TIM_DMA_ID_CC1])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
+
+    if (hdma->Init.Mode == DMA_NORMAL)
+    {
+      TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+    }
+  }
+  else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
+
+    if (hdma->Init.Mode == DMA_NORMAL)
+    {
+      TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+    }
+  }
+  else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
+
+    if (hdma->Init.Mode == DMA_NORMAL)
+    {
+      TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
+    }
+  }
+  else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
+
+    if (hdma->Init.Mode == DMA_NORMAL)
+    {
+      TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
+    }
+  }
+  else
+  {
+    /* nothing to do */
+  }
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+  htim->PWM_PulseFinishedCallback(htim);
+#else
+  HAL_TIM_PWM_PulseFinishedCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+  htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+}
+
+/**
+  * @brief  TIM DMA error callback (complementary channel)
+  * @param  hdma pointer to DMA handle.
+  * @retval None
+  */
+static void TIM_DMAErrorCCxN(DMA_HandleTypeDef *hdma)
+{
+  TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+  if (hdma == htim->hdma[TIM_DMA_ID_CC1])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
+    TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+  }
+  else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
+    TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+  }
+  else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
+    TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
+  }
+  else
+  {
+    /* nothing to do */
+  }
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+  htim->ErrorCallback(htim);
+#else
+  HAL_TIM_ErrorCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+  htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+}
+
+/**
+  * @brief  Enables or disables the TIM Capture Compare Channel xN.
+  * @param  TIMx to select the TIM peripheral
+  * @param  Channel specifies the TIM Channel
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1
+  *            @arg TIM_CHANNEL_2: TIM Channel 2
+  *            @arg TIM_CHANNEL_3: TIM Channel 3
+  * @param  ChannelNState specifies the TIM Channel CCxNE bit new state.
+  *          This parameter can be: TIM_CCxN_ENABLE or TIM_CCxN_Disable.
+  * @retval None
+  */
+static void TIM_CCxNChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelNState)
+{
+  uint32_t tmp;
+
+  tmp = TIM_CCER_CC1NE << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */
+
+  /* Reset the CCxNE Bit */
+  TIMx->CCER &=  ~tmp;
+
+  /* Set or reset the CCxNE Bit */
+  TIMx->CCER |= (uint32_t)(ChannelNState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */
+}
+/**
+  * @}
+  */
+
+#endif /* HAL_TIM_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
diff --git a/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c
new file mode 100644
index 0000000..d958ad6
--- /dev/null
+++ b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c
@@ -0,0 +1,3751 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hal_uart.c
+  * @author  MCD Application Team
+  * @brief   UART HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the Universal Asynchronous Receiver Transmitter Peripheral (UART).
+  *           + Initialization and de-initialization functions
+  *           + IO operation functions
+  *           + Peripheral Control functions
+  *           + Peripheral State and Errors functions
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2016 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  @verbatim
+  ==============================================================================
+                        ##### How to use this driver #####
+  ==============================================================================
+  [..]
+    The UART HAL driver can be used as follows:
+
+    (#) Declare a UART_HandleTypeDef handle structure (eg. UART_HandleTypeDef huart).
+    (#) Initialize the UART low level resources by implementing the HAL_UART_MspInit() API:
+        (##) Enable the USARTx interface clock.
+        (##) UART pins configuration:
+            (+++) Enable the clock for the UART GPIOs.
+            (+++) Configure the UART TX/RX pins as alternate function pull-up.
+        (##) NVIC configuration if you need to use interrupt process (HAL_UART_Transmit_IT()
+             and HAL_UART_Receive_IT() APIs):
+            (+++) Configure the USARTx interrupt priority.
+            (+++) Enable the NVIC USART IRQ handle.
+        (##) DMA Configuration if you need to use DMA process (HAL_UART_Transmit_DMA()
+             and HAL_UART_Receive_DMA() APIs):
+            (+++) Declare a DMA handle structure for the Tx/Rx stream.
+            (+++) Enable the DMAx interface clock.
+            (+++) Configure the declared DMA handle structure with the required
+                  Tx/Rx parameters.
+            (+++) Configure the DMA Tx/Rx stream.
+            (+++) Associate the initialized DMA handle to the UART DMA Tx/Rx handle.
+            (+++) Configure the priority and enable the NVIC for the transfer complete
+                  interrupt on the DMA Tx/Rx stream.
+            (+++) Configure the USARTx interrupt priority and enable the NVIC USART IRQ handle
+                  (used for last byte sending completion detection in DMA non circular mode)
+
+    (#) Program the Baud Rate, Word Length, Stop Bit, Parity, Hardware
+        flow control and Mode(Receiver/Transmitter) in the huart Init structure.
+
+    (#) For the UART asynchronous mode, initialize the UART registers by calling
+        the HAL_UART_Init() API.
+
+    (#) For the UART Half duplex mode, initialize the UART registers by calling
+        the HAL_HalfDuplex_Init() API.
+
+    (#) For the LIN mode, initialize the UART registers by calling the HAL_LIN_Init() API.
+
+    (#) For the Multi-Processor mode, initialize the UART registers by calling
+        the HAL_MultiProcessor_Init() API.
+
+     [..]
+       (@) The specific UART interrupts (Transmission complete interrupt,
+            RXNE interrupt and Error Interrupts) will be managed using the macros
+            __HAL_UART_ENABLE_IT() and __HAL_UART_DISABLE_IT() inside the transmit
+            and receive process.
+
+     [..]
+       (@) These APIs (HAL_UART_Init() and HAL_HalfDuplex_Init()) configure also the
+            low level Hardware GPIO, CLOCK, CORTEX...etc) by calling the customized
+            HAL_UART_MspInit() API.
+
+    ##### Callback registration #####
+    ==================================
+
+    [..]
+    The compilation define USE_HAL_UART_REGISTER_CALLBACKS when set to 1
+    allows the user to configure dynamically the driver callbacks.
+
+    [..]
+    Use Function HAL_UART_RegisterCallback() to register a user callback.
+    Function HAL_UART_RegisterCallback() allows to register following callbacks:
+    (+) TxHalfCpltCallback        : Tx Half Complete Callback.
+    (+) TxCpltCallback            : Tx Complete Callback.
+    (+) RxHalfCpltCallback        : Rx Half Complete Callback.
+    (+) RxCpltCallback            : Rx Complete Callback.
+    (+) ErrorCallback             : Error Callback.
+    (+) AbortCpltCallback         : Abort Complete Callback.
+    (+) AbortTransmitCpltCallback : Abort Transmit Complete Callback.
+    (+) AbortReceiveCpltCallback  : Abort Receive Complete Callback.
+    (+) MspInitCallback           : UART MspInit.
+    (+) MspDeInitCallback         : UART MspDeInit.
+    This function takes as parameters the HAL peripheral handle, the Callback ID
+    and a pointer to the user callback function.
+
+    [..]
+    Use function HAL_UART_UnRegisterCallback() to reset a callback to the default
+    weak (surcharged) function.
+    HAL_UART_UnRegisterCallback() takes as parameters the HAL peripheral handle,
+    and the Callback ID.
+    This function allows to reset following callbacks:
+    (+) TxHalfCpltCallback        : Tx Half Complete Callback.
+    (+) TxCpltCallback            : Tx Complete Callback.
+    (+) RxHalfCpltCallback        : Rx Half Complete Callback.
+    (+) RxCpltCallback            : Rx Complete Callback.
+    (+) ErrorCallback             : Error Callback.
+    (+) AbortCpltCallback         : Abort Complete Callback.
+    (+) AbortTransmitCpltCallback : Abort Transmit Complete Callback.
+    (+) AbortReceiveCpltCallback  : Abort Receive Complete Callback.
+    (+) MspInitCallback           : UART MspInit.
+    (+) MspDeInitCallback         : UART MspDeInit.
+
+    [..]
+    For specific callback RxEventCallback, use dedicated registration/reset functions:
+    respectively HAL_UART_RegisterRxEventCallback() , HAL_UART_UnRegisterRxEventCallback().
+
+    [..]
+    By default, after the HAL_UART_Init() and when the state is HAL_UART_STATE_RESET
+    all callbacks are set to the corresponding weak (surcharged) functions:
+    examples HAL_UART_TxCpltCallback(), HAL_UART_RxHalfCpltCallback().
+    Exception done for MspInit and MspDeInit functions that are respectively
+    reset to the legacy weak (surcharged) functions in the HAL_UART_Init()
+    and HAL_UART_DeInit() only when these callbacks are null (not registered beforehand).
+    If not, MspInit or MspDeInit are not null, the HAL_UART_Init() and HAL_UART_DeInit()
+    keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
+
+    [..]
+    Callbacks can be registered/unregistered in HAL_UART_STATE_READY state only.
+    Exception done MspInit/MspDeInit that can be registered/unregistered
+    in HAL_UART_STATE_READY or HAL_UART_STATE_RESET state, thus registered (user)
+    MspInit/DeInit callbacks can be used during the Init/DeInit.
+    In that case first register the MspInit/MspDeInit user callbacks
+    using HAL_UART_RegisterCallback() before calling HAL_UART_DeInit()
+    or HAL_UART_Init() function.
+
+    [..]
+    When The compilation define USE_HAL_UART_REGISTER_CALLBACKS is set to 0 or
+    not defined, the callback registration feature is not available
+    and weak (surcharged) callbacks are used.
+
+     [..]
+        Three operation modes are available within this driver :
+
+     *** Polling mode IO operation ***
+     =================================
+     [..]
+       (+) Send an amount of data in blocking mode using HAL_UART_Transmit()
+       (+) Receive an amount of data in blocking mode using HAL_UART_Receive()
+
+     *** Interrupt mode IO operation ***
+     ===================================
+     [..]
+       (+) Send an amount of data in non blocking mode using HAL_UART_Transmit_IT()
+       (+) At transmission end of transfer HAL_UART_TxCpltCallback is executed and user can
+            add his own code by customization of function pointer HAL_UART_TxCpltCallback
+       (+) Receive an amount of data in non blocking mode using HAL_UART_Receive_IT()
+       (+) At reception end of transfer HAL_UART_RxCpltCallback is executed and user can
+            add his own code by customization of function pointer HAL_UART_RxCpltCallback
+       (+) In case of transfer Error, HAL_UART_ErrorCallback() function is executed and user can
+            add his own code by customization of function pointer HAL_UART_ErrorCallback
+
+     *** DMA mode IO operation ***
+     ==============================
+     [..]
+       (+) Send an amount of data in non blocking mode (DMA) using HAL_UART_Transmit_DMA()
+       (+) At transmission end of half transfer HAL_UART_TxHalfCpltCallback is executed and user can
+            add his own code by customization of function pointer HAL_UART_TxHalfCpltCallback
+       (+) At transmission end of transfer HAL_UART_TxCpltCallback is executed and user can
+            add his own code by customization of function pointer HAL_UART_TxCpltCallback
+       (+) Receive an amount of data in non blocking mode (DMA) using HAL_UART_Receive_DMA()
+       (+) At reception end of half transfer HAL_UART_RxHalfCpltCallback is executed and user can
+            add his own code by customization of function pointer HAL_UART_RxHalfCpltCallback
+       (+) At reception end of transfer HAL_UART_RxCpltCallback is executed and user can
+            add his own code by customization of function pointer HAL_UART_RxCpltCallback
+       (+) In case of transfer Error, HAL_UART_ErrorCallback() function is executed and user can
+            add his own code by customization of function pointer HAL_UART_ErrorCallback
+       (+) Pause the DMA Transfer using HAL_UART_DMAPause()
+       (+) Resume the DMA Transfer using HAL_UART_DMAResume()
+       (+) Stop the DMA Transfer using HAL_UART_DMAStop()
+
+
+    [..] This subsection also provides a set of additional functions providing enhanced reception
+    services to user. (For example, these functions allow application to handle use cases
+    where number of data to be received is unknown).
+
+    (#) Compared to standard reception services which only consider number of received
+        data elements as reception completion criteria, these functions also consider additional events
+        as triggers for updating reception status to caller :
+       (+) Detection of inactivity period (RX line has not been active for a given period).
+          (++) RX inactivity detected by IDLE event, i.e. RX line has been in idle state (normally high state)
+               for 1 frame time, after last received byte.
+
+    (#) There are two mode of transfer:
+       (+) Blocking mode: The reception is performed in polling mode, until either expected number of data is received,
+           or till IDLE event occurs. Reception is handled only during function execution.
+           When function exits, no data reception could occur. HAL status and number of actually received data elements,
+           are returned by function after finishing transfer.
+       (+) Non-Blocking mode: The reception is performed using Interrupts or DMA.
+           These API's return the HAL status.
+           The end of the data processing will be indicated through the
+           dedicated UART IRQ when using Interrupt mode or the DMA IRQ when using DMA mode.
+           The HAL_UARTEx_RxEventCallback() user callback will be executed during Receive process
+           The HAL_UART_ErrorCallback()user callback will be executed when a reception error is detected.
+
+    (#) Blocking mode API:
+        (+) HAL_UARTEx_ReceiveToIdle()
+
+    (#) Non-Blocking mode API with Interrupt:
+        (+) HAL_UARTEx_ReceiveToIdle_IT()
+
+    (#) Non-Blocking mode API with DMA:
+        (+) HAL_UARTEx_ReceiveToIdle_DMA()
+
+
+     *** UART HAL driver macros list ***
+     =============================================
+     [..]
+       Below the list of most used macros in UART HAL driver.
+
+      (+) __HAL_UART_ENABLE: Enable the UART peripheral
+      (+) __HAL_UART_DISABLE: Disable the UART peripheral
+      (+) __HAL_UART_GET_FLAG : Check whether the specified UART flag is set or not
+      (+) __HAL_UART_CLEAR_FLAG : Clear the specified UART pending flag
+      (+) __HAL_UART_ENABLE_IT: Enable the specified UART interrupt
+      (+) __HAL_UART_DISABLE_IT: Disable the specified UART interrupt
+      (+) __HAL_UART_GET_IT_SOURCE: Check whether the specified UART interrupt has occurred or not
+
+     [..]
+       (@) You can refer to the UART HAL driver header file for more useful macros
+
+  @endverbatim
+     [..]
+       (@) Additional remark: If the parity is enabled, then the MSB bit of the data written
+           in the data register is transmitted but is changed by the parity bit.
+           Depending on the frame length defined by the M bit (8-bits or 9-bits),
+           the possible UART frame formats are as listed in the following table:
+    +-------------------------------------------------------------+
+    |   M bit |  PCE bit  |            UART frame                 |
+    |---------------------|---------------------------------------|
+    |    0    |    0      |    | SB | 8 bit data | STB |          |
+    |---------|-----------|---------------------------------------|
+    |    0    |    1      |    | SB | 7 bit data | PB | STB |     |
+    |---------|-----------|---------------------------------------|
+    |    1    |    0      |    | SB | 9 bit data | STB |          |
+    |---------|-----------|---------------------------------------|
+    |    1    |    1      |    | SB | 8 bit data | PB | STB |     |
+    +-------------------------------------------------------------+
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup UART UART
+  * @brief HAL UART module driver
+  * @{
+  */
+#ifdef HAL_UART_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @addtogroup UART_Private_Constants
+  * @{
+  */
+/**
+  * @}
+  */
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @addtogroup UART_Private_Functions  UART Private Functions
+  * @{
+  */
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+void UART_InitCallbacksToDefault(UART_HandleTypeDef *huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+static void UART_EndTxTransfer(UART_HandleTypeDef *huart);
+static void UART_EndRxTransfer(UART_HandleTypeDef *huart);
+static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma);
+static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
+static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
+static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
+static void UART_DMAError(DMA_HandleTypeDef *hdma);
+static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma);
+static void UART_DMATxAbortCallback(DMA_HandleTypeDef *hdma);
+static void UART_DMARxAbortCallback(DMA_HandleTypeDef *hdma);
+static void UART_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma);
+static void UART_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma);
+static HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart);
+static HAL_StatusTypeDef UART_EndTransmit_IT(UART_HandleTypeDef *huart);
+static HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart);
+static HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status,
+                                                     uint32_t Tickstart, uint32_t Timeout);
+static void UART_SetConfig(UART_HandleTypeDef *huart);
+
+/**
+  * @}
+  */
+
+/* Exported functions ---------------------------------------------------------*/
+/** @defgroup UART_Exported_Functions UART Exported Functions
+  * @{
+  */
+
+/** @defgroup UART_Exported_Functions_Group1 Initialization and de-initialization functions
+  *  @brief    Initialization and Configuration functions
+  *
+@verbatim
+ ===============================================================================
+            ##### Initialization and Configuration functions #####
+ ===============================================================================
+    [..]
+    This subsection provides a set of functions allowing to initialize the USARTx or the UARTy
+    in asynchronous mode.
+      (+) For the asynchronous mode only these parameters can be configured:
+        (++) Baud Rate
+        (++) Word Length
+        (++) Stop Bit
+        (++) Parity: If the parity is enabled, then the MSB bit of the data written
+             in the data register is transmitted but is changed by the parity bit.
+             Depending on the frame length defined by the M bit (8-bits or 9-bits),
+             please refer to Reference manual for possible UART frame formats.
+        (++) Hardware flow control
+        (++) Receiver/transmitter modes
+        (++) Over Sampling Method
+    [..]
+    The HAL_UART_Init(), HAL_HalfDuplex_Init(), HAL_LIN_Init() and HAL_MultiProcessor_Init() APIs
+    follow respectively the UART asynchronous, UART Half duplex, LIN and Multi-Processor configuration
+    procedures (details for the procedures are available in reference manual
+    (RM0430 for STM32F4X3xx MCUs and RM0402 for STM32F412xx MCUs
+     RM0383 for STM32F411xC/E MCUs and RM0401 for STM32F410xx MCUs
+     RM0090 for STM32F4X5xx/STM32F4X7xx/STM32F429xx/STM32F439xx MCUs
+     RM0390 for STM32F446xx MCUs and RM0386 for STM32F469xx/STM32F479xx MCUs)).
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initializes the UART mode according to the specified parameters in
+  *         the UART_InitTypeDef and create the associated handle.
+  * @param  huart  Pointer to a UART_HandleTypeDef structure that contains
+  *                the configuration information for the specified UART module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart)
+{
+  /* Check the UART handle allocation */
+  if (huart == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  if (huart->Init.HwFlowCtl != UART_HWCONTROL_NONE)
+  {
+    /* The hardware flow control is available only for USART1, USART2, USART3 and USART6.
+       Except for STM32F446xx devices, that is available for USART1, USART2, USART3, USART6, UART4 and UART5.
+    */
+    assert_param(IS_UART_HWFLOW_INSTANCE(huart->Instance));
+    assert_param(IS_UART_HARDWARE_FLOW_CONTROL(huart->Init.HwFlowCtl));
+  }
+  else
+  {
+    assert_param(IS_UART_INSTANCE(huart->Instance));
+  }
+  assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength));
+  assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling));
+
+  if (huart->gState == HAL_UART_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    huart->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+    UART_InitCallbacksToDefault(huart);
+
+    if (huart->MspInitCallback == NULL)
+    {
+      huart->MspInitCallback = HAL_UART_MspInit;
+    }
+
+    /* Init the low level hardware */
+    huart->MspInitCallback(huart);
+#else
+    /* Init the low level hardware : GPIO, CLOCK */
+    HAL_UART_MspInit(huart);
+#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
+  }
+
+  huart->gState = HAL_UART_STATE_BUSY;
+
+  /* Disable the peripheral */
+  __HAL_UART_DISABLE(huart);
+
+  /* Set the UART Communication parameters */
+  UART_SetConfig(huart);
+
+  /* In asynchronous mode, the following bits must be kept cleared:
+     - LINEN and CLKEN bits in the USART_CR2 register,
+     - SCEN, HDSEL and IREN  bits in the USART_CR3 register.*/
+  CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
+  CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
+
+  /* Enable the peripheral */
+  __HAL_UART_ENABLE(huart);
+
+  /* Initialize the UART state */
+  huart->ErrorCode = HAL_UART_ERROR_NONE;
+  huart->gState = HAL_UART_STATE_READY;
+  huart->RxState = HAL_UART_STATE_READY;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the half-duplex mode according to the specified
+  *         parameters in the UART_InitTypeDef and create the associated handle.
+  * @param  huart  Pointer to a UART_HandleTypeDef structure that contains
+  *                the configuration information for the specified UART module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart)
+{
+  /* Check the UART handle allocation */
+  if (huart == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_UART_HALFDUPLEX_INSTANCE(huart->Instance));
+  assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength));
+  assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling));
+
+  if (huart->gState == HAL_UART_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    huart->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+    UART_InitCallbacksToDefault(huart);
+
+    if (huart->MspInitCallback == NULL)
+    {
+      huart->MspInitCallback = HAL_UART_MspInit;
+    }
+
+    /* Init the low level hardware */
+    huart->MspInitCallback(huart);
+#else
+    /* Init the low level hardware : GPIO, CLOCK */
+    HAL_UART_MspInit(huart);
+#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
+  }
+
+  huart->gState = HAL_UART_STATE_BUSY;
+
+  /* Disable the peripheral */
+  __HAL_UART_DISABLE(huart);
+
+  /* Set the UART Communication parameters */
+  UART_SetConfig(huart);
+
+  /* In half-duplex mode, the following bits must be kept cleared:
+     - LINEN and CLKEN bits in the USART_CR2 register,
+     - SCEN and IREN bits in the USART_CR3 register.*/
+  CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
+  CLEAR_BIT(huart->Instance->CR3, (USART_CR3_IREN | USART_CR3_SCEN));
+
+  /* Enable the Half-Duplex mode by setting the HDSEL bit in the CR3 register */
+  SET_BIT(huart->Instance->CR3, USART_CR3_HDSEL);
+
+  /* Enable the peripheral */
+  __HAL_UART_ENABLE(huart);
+
+  /* Initialize the UART state*/
+  huart->ErrorCode = HAL_UART_ERROR_NONE;
+  huart->gState = HAL_UART_STATE_READY;
+  huart->RxState = HAL_UART_STATE_READY;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the LIN mode according to the specified
+  *         parameters in the UART_InitTypeDef and create the associated handle.
+  * @param  huart  Pointer to a UART_HandleTypeDef structure that contains
+  *                the configuration information for the specified UART module.
+  * @param  BreakDetectLength Specifies the LIN break detection length.
+  *         This parameter can be one of the following values:
+  *            @arg UART_LINBREAKDETECTLENGTH_10B: 10-bit break detection
+  *            @arg UART_LINBREAKDETECTLENGTH_11B: 11-bit break detection
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLength)
+{
+  /* Check the UART handle allocation */
+  if (huart == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the LIN UART instance */
+  assert_param(IS_UART_LIN_INSTANCE(huart->Instance));
+
+  /* Check the Break detection length parameter */
+  assert_param(IS_UART_LIN_BREAK_DETECT_LENGTH(BreakDetectLength));
+  assert_param(IS_UART_LIN_WORD_LENGTH(huart->Init.WordLength));
+  assert_param(IS_UART_LIN_OVERSAMPLING(huart->Init.OverSampling));
+
+  if (huart->gState == HAL_UART_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    huart->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+    UART_InitCallbacksToDefault(huart);
+
+    if (huart->MspInitCallback == NULL)
+    {
+      huart->MspInitCallback = HAL_UART_MspInit;
+    }
+
+    /* Init the low level hardware */
+    huart->MspInitCallback(huart);
+#else
+    /* Init the low level hardware : GPIO, CLOCK */
+    HAL_UART_MspInit(huart);
+#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
+  }
+
+  huart->gState = HAL_UART_STATE_BUSY;
+
+  /* Disable the peripheral */
+  __HAL_UART_DISABLE(huart);
+
+  /* Set the UART Communication parameters */
+  UART_SetConfig(huart);
+
+  /* In LIN mode, the following bits must be kept cleared:
+     - CLKEN bits in the USART_CR2 register,
+     - SCEN, HDSEL and IREN bits in the USART_CR3 register.*/
+  CLEAR_BIT(huart->Instance->CR2, (USART_CR2_CLKEN));
+  CLEAR_BIT(huart->Instance->CR3, (USART_CR3_HDSEL | USART_CR3_IREN | USART_CR3_SCEN));
+
+  /* Enable the LIN mode by setting the LINEN bit in the CR2 register */
+  SET_BIT(huart->Instance->CR2, USART_CR2_LINEN);
+
+  /* Set the USART LIN Break detection length. */
+  CLEAR_BIT(huart->Instance->CR2, USART_CR2_LBDL);
+  SET_BIT(huart->Instance->CR2, BreakDetectLength);
+
+  /* Enable the peripheral */
+  __HAL_UART_ENABLE(huart);
+
+  /* Initialize the UART state*/
+  huart->ErrorCode = HAL_UART_ERROR_NONE;
+  huart->gState = HAL_UART_STATE_READY;
+  huart->RxState = HAL_UART_STATE_READY;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the Multi-Processor mode according to the specified
+  *         parameters in the UART_InitTypeDef and create the associated handle.
+  * @param  huart  Pointer to a UART_HandleTypeDef structure that contains
+  *                the configuration information for the specified UART module.
+  * @param  Address USART address
+  * @param  WakeUpMethod specifies the USART wake-up method.
+  *         This parameter can be one of the following values:
+  *            @arg UART_WAKEUPMETHOD_IDLELINE: Wake-up by an idle line detection
+  *            @arg UART_WAKEUPMETHOD_ADDRESSMARK: Wake-up by an address mark
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod)
+{
+  /* Check the UART handle allocation */
+  if (huart == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_UART_INSTANCE(huart->Instance));
+
+  /* Check the Address & wake up method parameters */
+  assert_param(IS_UART_WAKEUPMETHOD(WakeUpMethod));
+  assert_param(IS_UART_ADDRESS(Address));
+  assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength));
+  assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling));
+
+  if (huart->gState == HAL_UART_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    huart->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+    UART_InitCallbacksToDefault(huart);
+
+    if (huart->MspInitCallback == NULL)
+    {
+      huart->MspInitCallback = HAL_UART_MspInit;
+    }
+
+    /* Init the low level hardware */
+    huart->MspInitCallback(huart);
+#else
+    /* Init the low level hardware : GPIO, CLOCK */
+    HAL_UART_MspInit(huart);
+#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
+  }
+
+  huart->gState = HAL_UART_STATE_BUSY;
+
+  /* Disable the peripheral */
+  __HAL_UART_DISABLE(huart);
+
+  /* Set the UART Communication parameters */
+  UART_SetConfig(huart);
+
+  /* In Multi-Processor mode, the following bits must be kept cleared:
+     - LINEN and CLKEN bits in the USART_CR2 register,
+     - SCEN, HDSEL and IREN  bits in the USART_CR3 register */
+  CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
+  CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
+
+  /* Set the USART address node */
+  CLEAR_BIT(huart->Instance->CR2, USART_CR2_ADD);
+  SET_BIT(huart->Instance->CR2, Address);
+
+  /* Set the wake up method by setting the WAKE bit in the CR1 register */
+  CLEAR_BIT(huart->Instance->CR1, USART_CR1_WAKE);
+  SET_BIT(huart->Instance->CR1, WakeUpMethod);
+
+  /* Enable the peripheral */
+  __HAL_UART_ENABLE(huart);
+
+  /* Initialize the UART state */
+  huart->ErrorCode = HAL_UART_ERROR_NONE;
+  huart->gState = HAL_UART_STATE_READY;
+  huart->RxState = HAL_UART_STATE_READY;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  DeInitializes the UART peripheral.
+  * @param  huart  Pointer to a UART_HandleTypeDef structure that contains
+  *                the configuration information for the specified UART module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart)
+{
+  /* Check the UART handle allocation */
+  if (huart == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_UART_INSTANCE(huart->Instance));
+
+  huart->gState = HAL_UART_STATE_BUSY;
+
+  /* Disable the Peripheral */
+  __HAL_UART_DISABLE(huart);
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+  if (huart->MspDeInitCallback == NULL)
+  {
+    huart->MspDeInitCallback = HAL_UART_MspDeInit;
+  }
+  /* DeInit the low level hardware */
+  huart->MspDeInitCallback(huart);
+#else
+  /* DeInit the low level hardware */
+  HAL_UART_MspDeInit(huart);
+#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
+
+  huart->ErrorCode = HAL_UART_ERROR_NONE;
+  huart->gState = HAL_UART_STATE_RESET;
+  huart->RxState = HAL_UART_STATE_RESET;
+  huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+
+  /* Process Unlock */
+  __HAL_UNLOCK(huart);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  UART MSP Init.
+  * @param  huart  Pointer to a UART_HandleTypeDef structure that contains
+  *                the configuration information for the specified UART module.
+  * @retval None
+  */
+__weak void HAL_UART_MspInit(UART_HandleTypeDef *huart)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(huart);
+  /* NOTE: This function should not be modified, when the callback is needed,
+           the HAL_UART_MspInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  UART MSP DeInit.
+  * @param  huart  Pointer to a UART_HandleTypeDef structure that contains
+  *                the configuration information for the specified UART module.
+  * @retval None
+  */
+__weak void HAL_UART_MspDeInit(UART_HandleTypeDef *huart)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(huart);
+  /* NOTE: This function should not be modified, when the callback is needed,
+           the HAL_UART_MspDeInit could be implemented in the user file
+   */
+}
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+/**
+  * @brief  Register a User UART Callback
+  *         To be used instead of the weak predefined callback
+  * @param  huart uart handle
+  * @param  CallbackID ID of the callback to be registered
+  *         This parameter can be one of the following values:
+  *           @arg @ref HAL_UART_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID
+  *           @arg @ref HAL_UART_TX_COMPLETE_CB_ID Tx Complete Callback ID
+  *           @arg @ref HAL_UART_RX_HALFCOMPLETE_CB_ID Rx Half Complete Callback ID
+  *           @arg @ref HAL_UART_RX_COMPLETE_CB_ID Rx Complete Callback ID
+  *           @arg @ref HAL_UART_ERROR_CB_ID Error Callback ID
+  *           @arg @ref HAL_UART_ABORT_COMPLETE_CB_ID Abort Complete Callback ID
+  *           @arg @ref HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID
+  *           @arg @ref HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID
+  *           @arg @ref HAL_UART_MSPINIT_CB_ID MspInit Callback ID
+  *           @arg @ref HAL_UART_MSPDEINIT_CB_ID MspDeInit Callback ID
+  * @param  pCallback pointer to the Callback function
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UART_RegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID,
+                                            pUART_CallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    /* Update the error code */
+    huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
+
+    return HAL_ERROR;
+  }
+  /* Process locked */
+  __HAL_LOCK(huart);
+
+  if (huart->gState == HAL_UART_STATE_READY)
+  {
+    switch (CallbackID)
+    {
+      case HAL_UART_TX_HALFCOMPLETE_CB_ID :
+        huart->TxHalfCpltCallback = pCallback;
+        break;
+
+      case HAL_UART_TX_COMPLETE_CB_ID :
+        huart->TxCpltCallback = pCallback;
+        break;
+
+      case HAL_UART_RX_HALFCOMPLETE_CB_ID :
+        huart->RxHalfCpltCallback = pCallback;
+        break;
+
+      case HAL_UART_RX_COMPLETE_CB_ID :
+        huart->RxCpltCallback = pCallback;
+        break;
+
+      case HAL_UART_ERROR_CB_ID :
+        huart->ErrorCallback = pCallback;
+        break;
+
+      case HAL_UART_ABORT_COMPLETE_CB_ID :
+        huart->AbortCpltCallback = pCallback;
+        break;
+
+      case HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID :
+        huart->AbortTransmitCpltCallback = pCallback;
+        break;
+
+      case HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID :
+        huart->AbortReceiveCpltCallback = pCallback;
+        break;
+
+      case HAL_UART_MSPINIT_CB_ID :
+        huart->MspInitCallback = pCallback;
+        break;
+
+      case HAL_UART_MSPDEINIT_CB_ID :
+        huart->MspDeInitCallback = pCallback;
+        break;
+
+      default :
+        /* Update the error code */
+        huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
+
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else if (huart->gState == HAL_UART_STATE_RESET)
+  {
+    switch (CallbackID)
+    {
+      case HAL_UART_MSPINIT_CB_ID :
+        huart->MspInitCallback = pCallback;
+        break;
+
+      case HAL_UART_MSPDEINIT_CB_ID :
+        huart->MspDeInitCallback = pCallback;
+        break;
+
+      default :
+        /* Update the error code */
+        huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
+
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    /* Update the error code */
+    huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(huart);
+
+  return status;
+}
+
+/**
+  * @brief  Unregister an UART Callback
+  *         UART callaback is redirected to the weak predefined callback
+  * @param  huart uart handle
+  * @param  CallbackID ID of the callback to be unregistered
+  *         This parameter can be one of the following values:
+  *           @arg @ref HAL_UART_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID
+  *           @arg @ref HAL_UART_TX_COMPLETE_CB_ID Tx Complete Callback ID
+  *           @arg @ref HAL_UART_RX_HALFCOMPLETE_CB_ID Rx Half Complete Callback ID
+  *           @arg @ref HAL_UART_RX_COMPLETE_CB_ID Rx Complete Callback ID
+  *           @arg @ref HAL_UART_ERROR_CB_ID Error Callback ID
+  *           @arg @ref HAL_UART_ABORT_COMPLETE_CB_ID Abort Complete Callback ID
+  *           @arg @ref HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID
+  *           @arg @ref HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID
+  *           @arg @ref HAL_UART_MSPINIT_CB_ID MspInit Callback ID
+  *           @arg @ref HAL_UART_MSPDEINIT_CB_ID MspDeInit Callback ID
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UART_UnRegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Process locked */
+  __HAL_LOCK(huart);
+
+  if (HAL_UART_STATE_READY == huart->gState)
+  {
+    switch (CallbackID)
+    {
+      case HAL_UART_TX_HALFCOMPLETE_CB_ID :
+        huart->TxHalfCpltCallback = HAL_UART_TxHalfCpltCallback;               /* Legacy weak  TxHalfCpltCallback       */
+        break;
+
+      case HAL_UART_TX_COMPLETE_CB_ID :
+        huart->TxCpltCallback = HAL_UART_TxCpltCallback;                       /* Legacy weak TxCpltCallback            */
+        break;
+
+      case HAL_UART_RX_HALFCOMPLETE_CB_ID :
+        huart->RxHalfCpltCallback = HAL_UART_RxHalfCpltCallback;               /* Legacy weak RxHalfCpltCallback        */
+        break;
+
+      case HAL_UART_RX_COMPLETE_CB_ID :
+        huart->RxCpltCallback = HAL_UART_RxCpltCallback;                       /* Legacy weak RxCpltCallback            */
+        break;
+
+      case HAL_UART_ERROR_CB_ID :
+        huart->ErrorCallback = HAL_UART_ErrorCallback;                         /* Legacy weak ErrorCallback             */
+        break;
+
+      case HAL_UART_ABORT_COMPLETE_CB_ID :
+        huart->AbortCpltCallback = HAL_UART_AbortCpltCallback;                 /* Legacy weak AbortCpltCallback         */
+        break;
+
+      case HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID :
+        huart->AbortTransmitCpltCallback = HAL_UART_AbortTransmitCpltCallback; /* Legacy weak AbortTransmitCpltCallback */
+        break;
+
+      case HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID :
+        huart->AbortReceiveCpltCallback = HAL_UART_AbortReceiveCpltCallback;   /* Legacy weak AbortReceiveCpltCallback  */
+        break;
+
+      case HAL_UART_MSPINIT_CB_ID :
+        huart->MspInitCallback = HAL_UART_MspInit;                             /* Legacy weak MspInitCallback           */
+        break;
+
+      case HAL_UART_MSPDEINIT_CB_ID :
+        huart->MspDeInitCallback = HAL_UART_MspDeInit;                         /* Legacy weak MspDeInitCallback         */
+        break;
+
+      default :
+        /* Update the error code */
+        huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
+
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else if (HAL_UART_STATE_RESET == huart->gState)
+  {
+    switch (CallbackID)
+    {
+      case HAL_UART_MSPINIT_CB_ID :
+        huart->MspInitCallback = HAL_UART_MspInit;
+        break;
+
+      case HAL_UART_MSPDEINIT_CB_ID :
+        huart->MspDeInitCallback = HAL_UART_MspDeInit;
+        break;
+
+      default :
+        /* Update the error code */
+        huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
+
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    /* Update the error code */
+    huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(huart);
+
+  return status;
+}
+
+/**
+  * @brief  Register a User UART Rx Event Callback
+  *         To be used instead of the weak predefined callback
+  * @param  huart     Uart handle
+  * @param  pCallback Pointer to the Rx Event Callback function
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UART_RegisterRxEventCallback(UART_HandleTypeDef *huart, pUART_RxEventCallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
+
+    return HAL_ERROR;
+  }
+
+  /* Process locked */
+  __HAL_LOCK(huart);
+
+  if (huart->gState == HAL_UART_STATE_READY)
+  {
+    huart->RxEventCallback = pCallback;
+  }
+  else
+  {
+    huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
+
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(huart);
+
+  return status;
+}
+
+/**
+  * @brief  UnRegister the UART Rx Event Callback
+  *         UART Rx Event Callback is redirected to the weak HAL_UARTEx_RxEventCallback() predefined callback
+  * @param  huart     Uart handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UART_UnRegisterRxEventCallback(UART_HandleTypeDef *huart)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Process locked */
+  __HAL_LOCK(huart);
+
+  if (huart->gState == HAL_UART_STATE_READY)
+  {
+    huart->RxEventCallback = HAL_UARTEx_RxEventCallback; /* Legacy weak UART Rx Event Callback  */
+  }
+  else
+  {
+    huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
+
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(huart);
+  return status;
+}
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+
+/** @defgroup UART_Exported_Functions_Group2 IO operation functions
+  *  @brief UART Transmit and Receive functions
+  *
+@verbatim
+ ===============================================================================
+                      ##### IO operation functions #####
+ ===============================================================================
+    This subsection provides a set of functions allowing to manage the UART asynchronous
+    and Half duplex data transfers.
+
+    (#) There are two modes of transfer:
+       (+) Blocking mode: The communication is performed in polling mode.
+           The HAL status of all data processing is returned by the same function
+           after finishing transfer.
+       (+) Non-Blocking mode: The communication is performed using Interrupts
+           or DMA, these API's return the HAL status.
+           The end of the data processing will be indicated through the
+           dedicated UART IRQ when using Interrupt mode or the DMA IRQ when
+           using DMA mode.
+           The HAL_UART_TxCpltCallback(), HAL_UART_RxCpltCallback() user callbacks
+           will be executed respectively at the end of the transmit or receive process
+           The HAL_UART_ErrorCallback()user callback will be executed when a communication error is detected.
+
+    (#) Blocking mode API's are :
+        (+) HAL_UART_Transmit()
+        (+) HAL_UART_Receive()
+
+    (#) Non-Blocking mode API's with Interrupt are :
+        (+) HAL_UART_Transmit_IT()
+        (+) HAL_UART_Receive_IT()
+        (+) HAL_UART_IRQHandler()
+
+    (#) Non-Blocking mode API's with DMA are :
+        (+) HAL_UART_Transmit_DMA()
+        (+) HAL_UART_Receive_DMA()
+        (+) HAL_UART_DMAPause()
+        (+) HAL_UART_DMAResume()
+        (+) HAL_UART_DMAStop()
+
+    (#) A set of Transfer Complete Callbacks are provided in Non_Blocking mode:
+        (+) HAL_UART_TxHalfCpltCallback()
+        (+) HAL_UART_TxCpltCallback()
+        (+) HAL_UART_RxHalfCpltCallback()
+        (+) HAL_UART_RxCpltCallback()
+        (+) HAL_UART_ErrorCallback()
+
+    (#) Non-Blocking mode transfers could be aborted using Abort API's :
+        (+) HAL_UART_Abort()
+        (+) HAL_UART_AbortTransmit()
+        (+) HAL_UART_AbortReceive()
+        (+) HAL_UART_Abort_IT()
+        (+) HAL_UART_AbortTransmit_IT()
+        (+) HAL_UART_AbortReceive_IT()
+
+    (#) For Abort services based on interrupts (HAL_UART_Abortxxx_IT), a set of Abort Complete Callbacks are provided:
+        (+) HAL_UART_AbortCpltCallback()
+        (+) HAL_UART_AbortTransmitCpltCallback()
+        (+) HAL_UART_AbortReceiveCpltCallback()
+
+    (#) A Rx Event Reception Callback (Rx event notification) is available for Non_Blocking modes of enhanced reception services:
+        (+) HAL_UARTEx_RxEventCallback()
+
+    (#) In Non-Blocking mode transfers, possible errors are split into 2 categories.
+        Errors are handled as follows :
+       (+) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is
+           to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error in Interrupt mode reception .
+           Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify error type,
+           and HAL_UART_ErrorCallback() user callback is executed. Transfer is kept ongoing on UART side.
+           If user wants to abort it, Abort services should be called by user.
+       (+) Error is considered as Blocking : Transfer could not be completed properly and is aborted.
+           This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode.
+           Error code is set to allow user to identify error type, and HAL_UART_ErrorCallback() user callback is executed.
+
+    -@- In the Half duplex communication, it is forbidden to run the transmit
+        and receive process in parallel, the UART state HAL_UART_STATE_BUSY_TX_RX can't be useful.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Sends an amount of data in blocking mode.
+  * @note   When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+  *         the sent data is handled as a set of u16. In this case, Size must indicate the number
+  *         of u16 provided through pData.
+  * @param  huart Pointer to a UART_HandleTypeDef structure that contains
+  *               the configuration information for the specified UART module.
+  * @param  pData Pointer to data buffer (u8 or u16 data elements).
+  * @param  Size  Amount of data elements (u8 or u16) to be sent
+  * @param  Timeout Timeout duration
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+  const uint8_t  *pdata8bits;
+  const uint16_t *pdata16bits;
+  uint32_t tickstart = 0U;
+
+  /* Check that a Tx process is not already ongoing */
+  if (huart->gState == HAL_UART_STATE_READY)
+  {
+    if ((pData == NULL) || (Size == 0U))
+    {
+      return  HAL_ERROR;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(huart);
+
+    huart->ErrorCode = HAL_UART_ERROR_NONE;
+    huart->gState = HAL_UART_STATE_BUSY_TX;
+
+    /* Init tickstart for timeout management */
+    tickstart = HAL_GetTick();
+
+    huart->TxXferSize = Size;
+    huart->TxXferCount = Size;
+
+    /* In case of 9bits/No Parity transfer, pData needs to be handled as a uint16_t pointer */
+    if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
+    {
+      pdata8bits  = NULL;
+      pdata16bits = (const uint16_t *) pData;
+    }
+    else
+    {
+      pdata8bits  = pData;
+      pdata16bits = NULL;
+    }
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(huart);
+
+    while (huart->TxXferCount > 0U)
+    {
+      if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
+      {
+        return HAL_TIMEOUT;
+      }
+      if (pdata8bits == NULL)
+      {
+        huart->Instance->DR = (uint16_t)(*pdata16bits & 0x01FFU);
+        pdata16bits++;
+      }
+      else
+      {
+        huart->Instance->DR = (uint8_t)(*pdata8bits & 0xFFU);
+        pdata8bits++;
+      }
+      huart->TxXferCount--;
+    }
+
+    if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
+    {
+      return HAL_TIMEOUT;
+    }
+
+    /* At end of Tx process, restore huart->gState to Ready */
+    huart->gState = HAL_UART_STATE_READY;
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Receives an amount of data in blocking mode.
+  * @note   When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+  *         the received data is handled as a set of u16. In this case, Size must indicate the number
+  *         of u16 available through pData.
+  * @param  huart Pointer to a UART_HandleTypeDef structure that contains
+  *               the configuration information for the specified UART module.
+  * @param  pData Pointer to data buffer (u8 or u16 data elements).
+  * @param  Size  Amount of data elements (u8 or u16) to be received.
+  * @param  Timeout Timeout duration
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+  uint8_t  *pdata8bits;
+  uint16_t *pdata16bits;
+  uint32_t tickstart = 0U;
+
+  /* Check that a Rx process is not already ongoing */
+  if (huart->RxState == HAL_UART_STATE_READY)
+  {
+    if ((pData == NULL) || (Size == 0U))
+    {
+      return  HAL_ERROR;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(huart);
+
+    huart->ErrorCode = HAL_UART_ERROR_NONE;
+    huart->RxState = HAL_UART_STATE_BUSY_RX;
+    huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+
+    /* Init tickstart for timeout management */
+    tickstart = HAL_GetTick();
+
+    huart->RxXferSize = Size;
+    huart->RxXferCount = Size;
+
+    /* In case of 9bits/No Parity transfer, pRxData needs to be handled as a uint16_t pointer */
+    if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
+    {
+      pdata8bits  = NULL;
+      pdata16bits = (uint16_t *) pData;
+    }
+    else
+    {
+      pdata8bits  = pData;
+      pdata16bits = NULL;
+    }
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(huart);
+
+    /* Check the remain data to be received */
+    while (huart->RxXferCount > 0U)
+    {
+      if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
+      {
+        return HAL_TIMEOUT;
+      }
+      if (pdata8bits == NULL)
+      {
+        *pdata16bits = (uint16_t)(huart->Instance->DR & 0x01FF);
+        pdata16bits++;
+      }
+      else
+      {
+        if ((huart->Init.WordLength == UART_WORDLENGTH_9B) || ((huart->Init.WordLength == UART_WORDLENGTH_8B) && (huart->Init.Parity == UART_PARITY_NONE)))
+        {
+          *pdata8bits = (uint8_t)(huart->Instance->DR & (uint8_t)0x00FF);
+        }
+        else
+        {
+          *pdata8bits = (uint8_t)(huart->Instance->DR & (uint8_t)0x007F);
+        }
+        pdata8bits++;
+      }
+      huart->RxXferCount--;
+    }
+
+    /* At end of Rx process, restore huart->RxState to Ready */
+    huart->RxState = HAL_UART_STATE_READY;
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Sends an amount of data in non blocking mode.
+  * @note   When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+  *         the sent data is handled as a set of u16. In this case, Size must indicate the number
+  *         of u16 provided through pData.
+  * @param  huart Pointer to a UART_HandleTypeDef structure that contains
+  *               the configuration information for the specified UART module.
+  * @param  pData Pointer to data buffer (u8 or u16 data elements).
+  * @param  Size  Amount of data elements (u8 or u16) to be sent
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size)
+{
+  /* Check that a Tx process is not already ongoing */
+  if (huart->gState == HAL_UART_STATE_READY)
+  {
+    if ((pData == NULL) || (Size == 0U))
+    {
+      return HAL_ERROR;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(huart);
+
+    huart->pTxBuffPtr = pData;
+    huart->TxXferSize = Size;
+    huart->TxXferCount = Size;
+
+    huart->ErrorCode = HAL_UART_ERROR_NONE;
+    huart->gState = HAL_UART_STATE_BUSY_TX;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(huart);
+
+    /* Enable the UART Transmit data register empty Interrupt */
+    __HAL_UART_ENABLE_IT(huart, UART_IT_TXE);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Receives an amount of data in non blocking mode.
+  * @note   When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+  *         the received data is handled as a set of u16. In this case, Size must indicate the number
+  *         of u16 available through pData.
+  * @param  huart Pointer to a UART_HandleTypeDef structure that contains
+  *               the configuration information for the specified UART module.
+  * @param  pData Pointer to data buffer (u8 or u16 data elements).
+  * @param  Size  Amount of data elements (u8 or u16) to be received.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
+{
+  /* Check that a Rx process is not already ongoing */
+  if (huart->RxState == HAL_UART_STATE_READY)
+  {
+    if ((pData == NULL) || (Size == 0U))
+    {
+      return HAL_ERROR;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(huart);
+
+    /* Set Reception type to Standard reception */
+    huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+
+    return (UART_Start_Receive_IT(huart, pData, Size));
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Sends an amount of data in DMA mode.
+  * @note   When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+  *         the sent data is handled as a set of u16. In this case, Size must indicate the number
+  *         of u16 provided through pData.
+  * @param  huart  Pointer to a UART_HandleTypeDef structure that contains
+  *                the configuration information for the specified UART module.
+  * @param  pData Pointer to data buffer (u8 or u16 data elements).
+  * @param  Size  Amount of data elements (u8 or u16) to be sent
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size)
+{
+  const uint32_t *tmp;
+
+  /* Check that a Tx process is not already ongoing */
+  if (huart->gState == HAL_UART_STATE_READY)
+  {
+    if ((pData == NULL) || (Size == 0U))
+    {
+      return HAL_ERROR;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(huart);
+
+    huart->pTxBuffPtr = pData;
+    huart->TxXferSize = Size;
+    huart->TxXferCount = Size;
+
+    huart->ErrorCode = HAL_UART_ERROR_NONE;
+    huart->gState = HAL_UART_STATE_BUSY_TX;
+
+    /* Set the UART DMA transfer complete callback */
+    huart->hdmatx->XferCpltCallback = UART_DMATransmitCplt;
+
+    /* Set the UART DMA Half transfer complete callback */
+    huart->hdmatx->XferHalfCpltCallback = UART_DMATxHalfCplt;
+
+    /* Set the DMA error callback */
+    huart->hdmatx->XferErrorCallback = UART_DMAError;
+
+    /* Set the DMA abort callback */
+    huart->hdmatx->XferAbortCallback = NULL;
+
+    /* Enable the UART transmit DMA stream */
+    tmp = (const uint32_t *)&pData;
+    HAL_DMA_Start_IT(huart->hdmatx, *(const uint32_t *)tmp, (uint32_t)&huart->Instance->DR, Size);
+
+    /* Clear the TC flag in the SR register by writing 0 to it */
+    __HAL_UART_CLEAR_FLAG(huart, UART_FLAG_TC);
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(huart);
+
+    /* Enable the DMA transfer for transmit request by setting the DMAT bit
+       in the UART CR3 register */
+    ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAT);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Receives an amount of data in DMA mode.
+  * @note   When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+  *         the received data is handled as a set of u16. In this case, Size must indicate the number
+  *         of u16 available through pData.
+  * @param  huart Pointer to a UART_HandleTypeDef structure that contains
+  *               the configuration information for the specified UART module.
+  * @param  pData Pointer to data buffer (u8 or u16 data elements).
+  * @param  Size  Amount of data elements (u8 or u16) to be received.
+  * @note   When the UART parity is enabled (PCE = 1) the received data contains the parity bit.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
+{
+  /* Check that a Rx process is not already ongoing */
+  if (huart->RxState == HAL_UART_STATE_READY)
+  {
+    if ((pData == NULL) || (Size == 0U))
+    {
+      return HAL_ERROR;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(huart);
+
+    /* Set Reception type to Standard reception */
+    huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+
+    return (UART_Start_Receive_DMA(huart, pData, Size));
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief Pauses the DMA Transfer.
+  * @param  huart  Pointer to a UART_HandleTypeDef structure that contains
+  *                the configuration information for the specified UART module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart)
+{
+  uint32_t dmarequest = 0x00U;
+
+  /* Process Locked */
+  __HAL_LOCK(huart);
+
+  dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT);
+  if ((huart->gState == HAL_UART_STATE_BUSY_TX) && dmarequest)
+  {
+    /* Disable the UART DMA Tx request */
+    ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
+  }
+
+  dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR);
+  if ((huart->RxState == HAL_UART_STATE_BUSY_RX) && dmarequest)
+  {
+    /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
+    ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
+    ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+
+    /* Disable the UART DMA Rx request */
+    ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+  }
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(huart);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief Resumes the DMA Transfer.
+  * @param  huart  Pointer to a UART_HandleTypeDef structure that contains
+  *                the configuration information for the specified UART module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart)
+{
+  /* Process Locked */
+  __HAL_LOCK(huart);
+
+  if (huart->gState == HAL_UART_STATE_BUSY_TX)
+  {
+    /* Enable the UART DMA Tx request */
+    ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAT);
+  }
+
+  if (huart->RxState == HAL_UART_STATE_BUSY_RX)
+  {
+    /* Clear the Overrun flag before resuming the Rx transfer*/
+    __HAL_UART_CLEAR_OREFLAG(huart);
+
+    /* Re-enable PE and ERR (Frame error, noise error, overrun error) interrupts */
+    if (huart->Init.Parity != UART_PARITY_NONE)
+    {
+      ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE);
+    }
+    ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_EIE);
+
+    /* Enable the UART DMA Rx request */
+    ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+  }
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(huart);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief Stops the DMA Transfer.
+  * @param  huart  Pointer to a UART_HandleTypeDef structure that contains
+  *                the configuration information for the specified UART module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart)
+{
+  uint32_t dmarequest = 0x00U;
+  /* The Lock is not implemented on this API to allow the user application
+     to call the HAL UART API under callbacks HAL_UART_TxCpltCallback() / HAL_UART_RxCpltCallback():
+     when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated
+     and the correspond call back is executed HAL_UART_TxCpltCallback() / HAL_UART_RxCpltCallback()
+     */
+
+  /* Stop UART DMA Tx request if ongoing */
+  dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT);
+  if ((huart->gState == HAL_UART_STATE_BUSY_TX) && dmarequest)
+  {
+    ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
+
+    /* Abort the UART DMA Tx stream */
+    if (huart->hdmatx != NULL)
+    {
+      HAL_DMA_Abort(huart->hdmatx);
+    }
+    UART_EndTxTransfer(huart);
+  }
+
+  /* Stop UART DMA Rx request if ongoing */
+  dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR);
+  if ((huart->RxState == HAL_UART_STATE_BUSY_RX) && dmarequest)
+  {
+    ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+
+    /* Abort the UART DMA Rx stream */
+    if (huart->hdmarx != NULL)
+    {
+      HAL_DMA_Abort(huart->hdmarx);
+    }
+    UART_EndRxTransfer(huart);
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief Receive an amount of data in blocking mode till either the expected number of data is received or an IDLE event occurs.
+  * @note   HAL_OK is returned if reception is completed (expected number of data has been received)
+  *         or if reception is stopped after IDLE event (less than the expected number of data has been received)
+  *         In this case, RxLen output parameter indicates number of data available in reception buffer.
+  * @note   When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M = 01),
+  *         the received data is handled as a set of uint16_t. In this case, Size must indicate the number
+  *         of uint16_t available through pData.
+  * @param huart   UART handle.
+  * @param pData   Pointer to data buffer (uint8_t or uint16_t data elements).
+  * @param Size    Amount of data elements (uint8_t or uint16_t) to be received.
+  * @param RxLen   Number of data elements finally received (could be lower than Size, in case reception ends on IDLE event)
+  * @param Timeout Timeout duration expressed in ms (covers the whole reception sequence).
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint16_t *RxLen,
+                                           uint32_t Timeout)
+{
+  uint8_t  *pdata8bits;
+  uint16_t *pdata16bits;
+  uint32_t tickstart;
+
+  /* Check that a Rx process is not already ongoing */
+  if (huart->RxState == HAL_UART_STATE_READY)
+  {
+    if ((pData == NULL) || (Size == 0U))
+    {
+      return  HAL_ERROR;
+    }
+
+    __HAL_LOCK(huart);
+
+    huart->ErrorCode = HAL_UART_ERROR_NONE;
+    huart->RxState = HAL_UART_STATE_BUSY_RX;
+    huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE;
+
+    /* Init tickstart for timeout management */
+    tickstart = HAL_GetTick();
+
+    huart->RxXferSize  = Size;
+    huart->RxXferCount = Size;
+
+    /* In case of 9bits/No Parity transfer, pRxData needs to be handled as a uint16_t pointer */
+    if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
+    {
+      pdata8bits  = NULL;
+      pdata16bits = (uint16_t *) pData;
+    }
+    else
+    {
+      pdata8bits  = pData;
+      pdata16bits = NULL;
+    }
+
+    __HAL_UNLOCK(huart);
+
+    /* Initialize output number of received elements */
+    *RxLen = 0U;
+
+    /* as long as data have to be received */
+    while (huart->RxXferCount > 0U)
+    {
+      /* Check if IDLE flag is set */
+      if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE))
+      {
+        /* Clear IDLE flag in ISR */
+        __HAL_UART_CLEAR_IDLEFLAG(huart);
+
+        /* If Set, but no data ever received, clear flag without exiting loop */
+        /* If Set, and data has already been received, this means Idle Event is valid : End reception */
+        if (*RxLen > 0U)
+        {
+          huart->RxState = HAL_UART_STATE_READY;
+
+          return HAL_OK;
+        }
+      }
+
+      /* Check if RXNE flag is set */
+      if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RXNE))
+      {
+        if (pdata8bits == NULL)
+        {
+          *pdata16bits = (uint16_t)(huart->Instance->DR & (uint16_t)0x01FF);
+          pdata16bits++;
+        }
+        else
+        {
+          if ((huart->Init.WordLength == UART_WORDLENGTH_9B) || ((huart->Init.WordLength == UART_WORDLENGTH_8B) && (huart->Init.Parity == UART_PARITY_NONE)))
+          {
+            *pdata8bits = (uint8_t)(huart->Instance->DR & (uint8_t)0x00FF);
+          }
+          else
+          {
+            *pdata8bits = (uint8_t)(huart->Instance->DR & (uint8_t)0x007F);
+          }
+
+          pdata8bits++;
+        }
+        /* Increment number of received elements */
+        *RxLen += 1U;
+        huart->RxXferCount--;
+      }
+
+      /* Check for the Timeout */
+      if (Timeout != HAL_MAX_DELAY)
+      {
+        if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
+        {
+          huart->RxState = HAL_UART_STATE_READY;
+
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+
+    /* Set number of received elements in output parameter : RxLen */
+    *RxLen = huart->RxXferSize - huart->RxXferCount;
+    /* At end of Rx process, restore huart->RxState to Ready */
+    huart->RxState = HAL_UART_STATE_READY;
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief Receive an amount of data in interrupt mode till either the expected number of data is received or an IDLE event occurs.
+  * @note   Reception is initiated by this function call. Further progress of reception is achieved thanks
+  *         to UART interrupts raised by RXNE and IDLE events. Callback is called at end of reception indicating
+  *         number of received data elements.
+  * @note   When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M = 01),
+  *         the received data is handled as a set of uint16_t. In this case, Size must indicate the number
+  *         of uint16_t available through pData.
+  * @param huart UART handle.
+  * @param pData Pointer to data buffer (uint8_t or uint16_t data elements).
+  * @param Size  Amount of data elements (uint8_t or uint16_t) to be received.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
+{
+  HAL_StatusTypeDef status;
+
+  /* Check that a Rx process is not already ongoing */
+  if (huart->RxState == HAL_UART_STATE_READY)
+  {
+    if ((pData == NULL) || (Size == 0U))
+    {
+      return HAL_ERROR;
+    }
+
+    __HAL_LOCK(huart);
+
+    /* Set Reception type to reception till IDLE Event*/
+    huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE;
+
+    status =  UART_Start_Receive_IT(huart, pData, Size);
+
+    /* Check Rx process has been successfully started */
+    if (status == HAL_OK)
+    {
+      if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
+      {
+        __HAL_UART_CLEAR_IDLEFLAG(huart);
+        ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
+      }
+      else
+      {
+        /* In case of errors already pending when reception is started,
+           Interrupts may have already been raised and lead to reception abortion.
+           (Overrun error for instance).
+           In such case Reception Type has been reset to HAL_UART_RECEPTION_STANDARD. */
+        status = HAL_ERROR;
+      }
+    }
+
+    return status;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief Receive an amount of data in DMA mode till either the expected number of data is received or an IDLE event occurs.
+  * @note   Reception is initiated by this function call. Further progress of reception is achieved thanks
+  *         to DMA services, transferring automatically received data elements in user reception buffer and
+  *         calling registered callbacks at half/end of reception. UART IDLE events are also used to consider
+  *         reception phase as ended. In all cases, callback execution will indicate number of received data elements.
+  * @note   When the UART parity is enabled (PCE = 1), the received data contain
+  *         the parity bit (MSB position).
+  * @note   When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M = 01),
+  *         the received data is handled as a set of uint16_t. In this case, Size must indicate the number
+  *         of uint16_t available through pData.
+  * @param huart UART handle.
+  * @param pData Pointer to data buffer (uint8_t or uint16_t data elements).
+  * @param Size  Amount of data elements (uint8_t or uint16_t) to be received.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
+{
+  HAL_StatusTypeDef status;
+
+  /* Check that a Rx process is not already ongoing */
+  if (huart->RxState == HAL_UART_STATE_READY)
+  {
+    if ((pData == NULL) || (Size == 0U))
+    {
+      return HAL_ERROR;
+    }
+
+    __HAL_LOCK(huart);
+
+    /* Set Reception type to reception till IDLE Event*/
+    huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE;
+
+    status =  UART_Start_Receive_DMA(huart, pData, Size);
+
+    /* Check Rx process has been successfully started */
+    if (status == HAL_OK)
+    {
+      if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
+      {
+        __HAL_UART_CLEAR_IDLEFLAG(huart);
+        ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
+      }
+      else
+      {
+        /* In case of errors already pending when reception is started,
+           Interrupts may have already been raised and lead to reception abortion.
+           (Overrun error for instance).
+           In such case Reception Type has been reset to HAL_UART_RECEPTION_STANDARD. */
+        status = HAL_ERROR;
+      }
+    }
+
+    return status;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Abort ongoing transfers (blocking mode).
+  * @param  huart UART handle.
+  * @note   This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
+  *         This procedure performs following operations :
+  *           - Disable UART Interrupts (Tx and Rx)
+  *           - Disable the DMA transfer in the peripheral register (if enabled)
+  *           - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
+  *           - Set handle State to READY
+  * @note   This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart)
+{
+  /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
+  ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE));
+  ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+
+  /* If Reception till IDLE event was ongoing, disable IDLEIE interrupt */
+  if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
+  {
+    ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE));
+  }
+
+  /* Disable the UART DMA Tx request if enabled */
+  if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
+  {
+    ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
+
+    /* Abort the UART DMA Tx stream: use blocking DMA Abort API (no callback) */
+    if (huart->hdmatx != NULL)
+    {
+      /* Set the UART DMA Abort callback to Null.
+         No call back execution at end of DMA abort procedure */
+      huart->hdmatx->XferAbortCallback = NULL;
+
+      if (HAL_DMA_Abort(huart->hdmatx) != HAL_OK)
+      {
+        if (HAL_DMA_GetError(huart->hdmatx) == HAL_DMA_ERROR_TIMEOUT)
+        {
+          /* Set error code to DMA */
+          huart->ErrorCode = HAL_UART_ERROR_DMA;
+
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+  }
+
+  /* Disable the UART DMA Rx request if enabled */
+  if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
+  {
+    ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+
+    /* Abort the UART DMA Rx stream: use blocking DMA Abort API (no callback) */
+    if (huart->hdmarx != NULL)
+    {
+      /* Set the UART DMA Abort callback to Null.
+         No call back execution at end of DMA abort procedure */
+      huart->hdmarx->XferAbortCallback = NULL;
+
+      if (HAL_DMA_Abort(huart->hdmarx) != HAL_OK)
+      {
+        if (HAL_DMA_GetError(huart->hdmarx) == HAL_DMA_ERROR_TIMEOUT)
+        {
+          /* Set error code to DMA */
+          huart->ErrorCode = HAL_UART_ERROR_DMA;
+
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+  }
+
+  /* Reset Tx and Rx transfer counters */
+  huart->TxXferCount = 0x00U;
+  huart->RxXferCount = 0x00U;
+
+  /* Reset ErrorCode */
+  huart->ErrorCode = HAL_UART_ERROR_NONE;
+
+  /* Restore huart->RxState and huart->gState to Ready */
+  huart->RxState = HAL_UART_STATE_READY;
+  huart->gState = HAL_UART_STATE_READY;
+  huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Abort ongoing Transmit transfer (blocking mode).
+  * @param  huart UART handle.
+  * @note   This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode.
+  *         This procedure performs following operations :
+  *           - Disable UART Interrupts (Tx)
+  *           - Disable the DMA transfer in the peripheral register (if enabled)
+  *           - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
+  *           - Set handle State to READY
+  * @note   This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart)
+{
+  /* Disable TXEIE and TCIE interrupts */
+  ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
+
+  /* Disable the UART DMA Tx request if enabled */
+  if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
+  {
+    ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
+
+    /* Abort the UART DMA Tx stream : use blocking DMA Abort API (no callback) */
+    if (huart->hdmatx != NULL)
+    {
+      /* Set the UART DMA Abort callback to Null.
+         No call back execution at end of DMA abort procedure */
+      huart->hdmatx->XferAbortCallback = NULL;
+
+      if (HAL_DMA_Abort(huart->hdmatx) != HAL_OK)
+      {
+        if (HAL_DMA_GetError(huart->hdmatx) == HAL_DMA_ERROR_TIMEOUT)
+        {
+          /* Set error code to DMA */
+          huart->ErrorCode = HAL_UART_ERROR_DMA;
+
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+  }
+
+  /* Reset Tx transfer counter */
+  huart->TxXferCount = 0x00U;
+
+  /* Restore huart->gState to Ready */
+  huart->gState = HAL_UART_STATE_READY;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Abort ongoing Receive transfer (blocking mode).
+  * @param  huart UART handle.
+  * @note   This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode.
+  *         This procedure performs following operations :
+  *           - Disable UART Interrupts (Rx)
+  *           - Disable the DMA transfer in the peripheral register (if enabled)
+  *           - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
+  *           - Set handle State to READY
+  * @note   This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UART_AbortReceive(UART_HandleTypeDef *huart)
+{
+  /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
+  ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
+  ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+
+  /* If Reception till IDLE event was ongoing, disable IDLEIE interrupt */
+  if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
+  {
+    ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE));
+  }
+
+  /* Disable the UART DMA Rx request if enabled */
+  if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
+  {
+    ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+
+    /* Abort the UART DMA Rx stream : use blocking DMA Abort API (no callback) */
+    if (huart->hdmarx != NULL)
+    {
+      /* Set the UART DMA Abort callback to Null.
+         No call back execution at end of DMA abort procedure */
+      huart->hdmarx->XferAbortCallback = NULL;
+
+      if (HAL_DMA_Abort(huart->hdmarx) != HAL_OK)
+      {
+        if (HAL_DMA_GetError(huart->hdmarx) == HAL_DMA_ERROR_TIMEOUT)
+        {
+          /* Set error code to DMA */
+          huart->ErrorCode = HAL_UART_ERROR_DMA;
+
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+  }
+
+  /* Reset Rx transfer counter */
+  huart->RxXferCount = 0x00U;
+
+  /* Restore huart->RxState to Ready */
+  huart->RxState = HAL_UART_STATE_READY;
+  huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Abort ongoing transfers (Interrupt mode).
+  * @param  huart UART handle.
+  * @note   This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
+  *         This procedure performs following operations :
+  *           - Disable UART Interrupts (Tx and Rx)
+  *           - Disable the DMA transfer in the peripheral register (if enabled)
+  *           - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
+  *           - Set handle State to READY
+  *           - At abort completion, call user abort complete callback
+  * @note   This procedure is executed in Interrupt mode, meaning that abort procedure could be
+  *         considered as completed only when user abort complete callback is executed (not when exiting function).
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart)
+{
+  uint32_t AbortCplt = 0x01U;
+
+  /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
+  ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE));
+  ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+
+  /* If Reception till IDLE event was ongoing, disable IDLEIE interrupt */
+  if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
+  {
+    ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE));
+  }
+
+  /* If DMA Tx and/or DMA Rx Handles are associated to UART Handle, DMA Abort complete callbacks should be initialised
+     before any call to DMA Abort functions */
+  /* DMA Tx Handle is valid */
+  if (huart->hdmatx != NULL)
+  {
+    /* Set DMA Abort Complete callback if UART DMA Tx request if enabled.
+       Otherwise, set it to NULL */
+    if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
+    {
+      huart->hdmatx->XferAbortCallback = UART_DMATxAbortCallback;
+    }
+    else
+    {
+      huart->hdmatx->XferAbortCallback = NULL;
+    }
+  }
+  /* DMA Rx Handle is valid */
+  if (huart->hdmarx != NULL)
+  {
+    /* Set DMA Abort Complete callback if UART DMA Rx request if enabled.
+       Otherwise, set it to NULL */
+    if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
+    {
+      huart->hdmarx->XferAbortCallback = UART_DMARxAbortCallback;
+    }
+    else
+    {
+      huart->hdmarx->XferAbortCallback = NULL;
+    }
+  }
+
+  /* Disable the UART DMA Tx request if enabled */
+  if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
+  {
+    /* Disable DMA Tx at UART level */
+    ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
+
+    /* Abort the UART DMA Tx stream : use non blocking DMA Abort API (callback) */
+    if (huart->hdmatx != NULL)
+    {
+      /* UART Tx DMA Abort callback has already been initialised :
+         will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */
+
+      /* Abort DMA TX */
+      if (HAL_DMA_Abort_IT(huart->hdmatx) != HAL_OK)
+      {
+        huart->hdmatx->XferAbortCallback = NULL;
+      }
+      else
+      {
+        AbortCplt = 0x00U;
+      }
+    }
+  }
+
+  /* Disable the UART DMA Rx request if enabled */
+  if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
+  {
+    ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+
+    /* Abort the UART DMA Rx stream : use non blocking DMA Abort API (callback) */
+    if (huart->hdmarx != NULL)
+    {
+      /* UART Rx DMA Abort callback has already been initialised :
+         will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */
+
+      /* Abort DMA RX */
+      if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK)
+      {
+        huart->hdmarx->XferAbortCallback = NULL;
+        AbortCplt = 0x01U;
+      }
+      else
+      {
+        AbortCplt = 0x00U;
+      }
+    }
+  }
+
+  /* if no DMA abort complete callback execution is required => call user Abort Complete callback */
+  if (AbortCplt == 0x01U)
+  {
+    /* Reset Tx and Rx transfer counters */
+    huart->TxXferCount = 0x00U;
+    huart->RxXferCount = 0x00U;
+
+    /* Reset ErrorCode */
+    huart->ErrorCode = HAL_UART_ERROR_NONE;
+
+    /* Restore huart->gState and huart->RxState to Ready */
+    huart->gState  = HAL_UART_STATE_READY;
+    huart->RxState = HAL_UART_STATE_READY;
+    huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+
+    /* As no DMA to be aborted, call directly user Abort complete callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+    /* Call registered Abort complete callback */
+    huart->AbortCpltCallback(huart);
+#else
+    /* Call legacy weak Abort complete callback */
+    HAL_UART_AbortCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Abort ongoing Transmit transfer (Interrupt mode).
+  * @param  huart UART handle.
+  * @note   This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode.
+  *         This procedure performs following operations :
+  *           - Disable UART Interrupts (Tx)
+  *           - Disable the DMA transfer in the peripheral register (if enabled)
+  *           - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
+  *           - Set handle State to READY
+  *           - At abort completion, call user abort complete callback
+  * @note   This procedure is executed in Interrupt mode, meaning that abort procedure could be
+  *         considered as completed only when user abort complete callback is executed (not when exiting function).
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart)
+{
+  /* Disable TXEIE and TCIE interrupts */
+  ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
+
+  /* Disable the UART DMA Tx request if enabled */
+  if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
+  {
+    ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
+
+    /* Abort the UART DMA Tx stream : use blocking DMA Abort API (no callback) */
+    if (huart->hdmatx != NULL)
+    {
+      /* Set the UART DMA Abort callback :
+         will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */
+      huart->hdmatx->XferAbortCallback = UART_DMATxOnlyAbortCallback;
+
+      /* Abort DMA TX */
+      if (HAL_DMA_Abort_IT(huart->hdmatx) != HAL_OK)
+      {
+        /* Call Directly huart->hdmatx->XferAbortCallback function in case of error */
+        huart->hdmatx->XferAbortCallback(huart->hdmatx);
+      }
+    }
+    else
+    {
+      /* Reset Tx transfer counter */
+      huart->TxXferCount = 0x00U;
+
+      /* Restore huart->gState to Ready */
+      huart->gState = HAL_UART_STATE_READY;
+
+      /* As no DMA to be aborted, call directly user Abort complete callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+      /* Call registered Abort Transmit Complete Callback */
+      huart->AbortTransmitCpltCallback(huart);
+#else
+      /* Call legacy weak Abort Transmit Complete Callback */
+      HAL_UART_AbortTransmitCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+    }
+  }
+  else
+  {
+    /* Reset Tx transfer counter */
+    huart->TxXferCount = 0x00U;
+
+    /* Restore huart->gState to Ready */
+    huart->gState = HAL_UART_STATE_READY;
+
+    /* As no DMA to be aborted, call directly user Abort complete callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+    /* Call registered Abort Transmit Complete Callback */
+    huart->AbortTransmitCpltCallback(huart);
+#else
+    /* Call legacy weak Abort Transmit Complete Callback */
+    HAL_UART_AbortTransmitCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Abort ongoing Receive transfer (Interrupt mode).
+  * @param  huart UART handle.
+  * @note   This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode.
+  *         This procedure performs following operations :
+  *           - Disable UART Interrupts (Rx)
+  *           - Disable the DMA transfer in the peripheral register (if enabled)
+  *           - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
+  *           - Set handle State to READY
+  *           - At abort completion, call user abort complete callback
+  * @note   This procedure is executed in Interrupt mode, meaning that abort procedure could be
+  *         considered as completed only when user abort complete callback is executed (not when exiting function).
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart)
+{
+  /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
+  ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
+  ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+
+  /* If Reception till IDLE event was ongoing, disable IDLEIE interrupt */
+  if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
+  {
+    ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE));
+  }
+
+  /* Disable the UART DMA Rx request if enabled */
+  if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
+  {
+    ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+
+    /* Abort the UART DMA Rx stream : use blocking DMA Abort API (no callback) */
+    if (huart->hdmarx != NULL)
+    {
+      /* Set the UART DMA Abort callback :
+         will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */
+      huart->hdmarx->XferAbortCallback = UART_DMARxOnlyAbortCallback;
+
+      /* Abort DMA RX */
+      if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK)
+      {
+        /* Call Directly huart->hdmarx->XferAbortCallback function in case of error */
+        huart->hdmarx->XferAbortCallback(huart->hdmarx);
+      }
+    }
+    else
+    {
+      /* Reset Rx transfer counter */
+      huart->RxXferCount = 0x00U;
+
+      /* Restore huart->RxState to Ready */
+      huart->RxState = HAL_UART_STATE_READY;
+      huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+
+      /* As no DMA to be aborted, call directly user Abort complete callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+      /* Call registered Abort Receive Complete Callback */
+      huart->AbortReceiveCpltCallback(huart);
+#else
+      /* Call legacy weak Abort Receive Complete Callback */
+      HAL_UART_AbortReceiveCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+    }
+  }
+  else
+  {
+    /* Reset Rx transfer counter */
+    huart->RxXferCount = 0x00U;
+
+    /* Restore huart->RxState to Ready */
+    huart->RxState = HAL_UART_STATE_READY;
+    huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+
+    /* As no DMA to be aborted, call directly user Abort complete callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+    /* Call registered Abort Receive Complete Callback */
+    huart->AbortReceiveCpltCallback(huart);
+#else
+    /* Call legacy weak Abort Receive Complete Callback */
+    HAL_UART_AbortReceiveCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  This function handles UART interrupt request.
+  * @param  huart  Pointer to a UART_HandleTypeDef structure that contains
+  *                the configuration information for the specified UART module.
+  * @retval None
+  */
+void HAL_UART_IRQHandler(UART_HandleTypeDef *huart)
+{
+  uint32_t isrflags   = READ_REG(huart->Instance->SR);
+  uint32_t cr1its     = READ_REG(huart->Instance->CR1);
+  uint32_t cr3its     = READ_REG(huart->Instance->CR3);
+  uint32_t errorflags = 0x00U;
+  uint32_t dmarequest = 0x00U;
+
+  /* If no error occurs */
+  errorflags = (isrflags & (uint32_t)(USART_SR_PE | USART_SR_FE | USART_SR_ORE | USART_SR_NE));
+  if (errorflags == RESET)
+  {
+    /* UART in mode Receiver -------------------------------------------------*/
+    if (((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
+    {
+      UART_Receive_IT(huart);
+      return;
+    }
+  }
+
+  /* If some errors occur */
+  if ((errorflags != RESET) && (((cr3its & USART_CR3_EIE) != RESET)
+                                || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != RESET)))
+  {
+    /* UART parity error interrupt occurred ----------------------------------*/
+    if (((isrflags & USART_SR_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET))
+    {
+      huart->ErrorCode |= HAL_UART_ERROR_PE;
+    }
+
+    /* UART noise error interrupt occurred -----------------------------------*/
+    if (((isrflags & USART_SR_NE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
+    {
+      huart->ErrorCode |= HAL_UART_ERROR_NE;
+    }
+
+    /* UART frame error interrupt occurred -----------------------------------*/
+    if (((isrflags & USART_SR_FE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
+    {
+      huart->ErrorCode |= HAL_UART_ERROR_FE;
+    }
+
+    /* UART Over-Run interrupt occurred --------------------------------------*/
+    if (((isrflags & USART_SR_ORE) != RESET) && (((cr1its & USART_CR1_RXNEIE) != RESET)
+                                                 || ((cr3its & USART_CR3_EIE) != RESET)))
+    {
+      huart->ErrorCode |= HAL_UART_ERROR_ORE;
+    }
+
+    /* Call UART Error Call back function if need be --------------------------*/
+    if (huart->ErrorCode != HAL_UART_ERROR_NONE)
+    {
+      /* UART in mode Receiver -----------------------------------------------*/
+      if (((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
+      {
+        UART_Receive_IT(huart);
+      }
+
+      /* If Overrun error occurs, or if any error occurs in DMA mode reception,
+         consider error as blocking */
+      dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR);
+      if (((huart->ErrorCode & HAL_UART_ERROR_ORE) != RESET) || dmarequest)
+      {
+        /* Blocking error : transfer is aborted
+           Set the UART state ready to be able to start again the process,
+           Disable Rx Interrupts, and disable Rx DMA request, if ongoing */
+        UART_EndRxTransfer(huart);
+
+        /* Disable the UART DMA Rx request if enabled */
+        if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
+        {
+          ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+
+          /* Abort the UART DMA Rx stream */
+          if (huart->hdmarx != NULL)
+          {
+            /* Set the UART DMA Abort callback :
+               will lead to call HAL_UART_ErrorCallback() at end of DMA abort procedure */
+            huart->hdmarx->XferAbortCallback = UART_DMAAbortOnError;
+            if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK)
+            {
+              /* Call Directly XferAbortCallback function in case of error */
+              huart->hdmarx->XferAbortCallback(huart->hdmarx);
+            }
+          }
+          else
+          {
+            /* Call user error callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+            /*Call registered error callback*/
+            huart->ErrorCallback(huart);
+#else
+            /*Call legacy weak error callback*/
+            HAL_UART_ErrorCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+          }
+        }
+        else
+        {
+          /* Call user error callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+          /*Call registered error callback*/
+          huart->ErrorCallback(huart);
+#else
+          /*Call legacy weak error callback*/
+          HAL_UART_ErrorCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+        }
+      }
+      else
+      {
+        /* Non Blocking error : transfer could go on.
+           Error is notified to user through user error callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+        /*Call registered error callback*/
+        huart->ErrorCallback(huart);
+#else
+        /*Call legacy weak error callback*/
+        HAL_UART_ErrorCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+
+        huart->ErrorCode = HAL_UART_ERROR_NONE;
+      }
+    }
+    return;
+  } /* End if some error occurs */
+
+  /* Check current reception Mode :
+     If Reception till IDLE event has been selected : */
+  if ((huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
+      && ((isrflags & USART_SR_IDLE) != 0U)
+      && ((cr1its & USART_SR_IDLE) != 0U))
+  {
+    __HAL_UART_CLEAR_IDLEFLAG(huart);
+
+    /* Check if DMA mode is enabled in UART */
+    if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
+    {
+      /* DMA mode enabled */
+      /* Check received length : If all expected data are received, do nothing,
+         (DMA cplt callback will be called).
+         Otherwise, if at least one data has already been received, IDLE event is to be notified to user */
+      uint16_t nb_remaining_rx_data = (uint16_t) __HAL_DMA_GET_COUNTER(huart->hdmarx);
+      if ((nb_remaining_rx_data > 0U)
+          && (nb_remaining_rx_data < huart->RxXferSize))
+      {
+        /* Reception is not complete */
+        huart->RxXferCount = nb_remaining_rx_data;
+
+        /* In Normal mode, end DMA xfer and HAL UART Rx process*/
+        if (huart->hdmarx->Init.Mode != DMA_CIRCULAR)
+        {
+          /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
+          ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
+          ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+
+          /* Disable the DMA transfer for the receiver request by resetting the DMAR bit
+             in the UART CR3 register */
+          ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+
+          /* At end of Rx process, restore huart->RxState to Ready */
+          huart->RxState = HAL_UART_STATE_READY;
+          huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+
+          ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
+
+          /* Last bytes received, so no need as the abort is immediate */
+          (void)HAL_DMA_Abort(huart->hdmarx);
+        }
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+        /*Call registered Rx Event callback*/
+        huart->RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount));
+#else
+        /*Call legacy weak Rx Event callback*/
+        HAL_UARTEx_RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount));
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+      }
+      return;
+    }
+    else
+    {
+      /* DMA mode not enabled */
+      /* Check received length : If all expected data are received, do nothing.
+         Otherwise, if at least one data has already been received, IDLE event is to be notified to user */
+      uint16_t nb_rx_data = huart->RxXferSize - huart->RxXferCount;
+      if ((huart->RxXferCount > 0U)
+          && (nb_rx_data > 0U))
+      {
+        /* Disable the UART Parity Error Interrupt and RXNE interrupts */
+        ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
+
+        /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */
+        ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+
+        /* Rx process is completed, restore huart->RxState to Ready */
+        huart->RxState = HAL_UART_STATE_READY;
+        huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+
+        ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+        /*Call registered Rx complete callback*/
+        huart->RxEventCallback(huart, nb_rx_data);
+#else
+        /*Call legacy weak Rx Event callback*/
+        HAL_UARTEx_RxEventCallback(huart, nb_rx_data);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+      }
+      return;
+    }
+  }
+
+  /* UART in mode Transmitter ------------------------------------------------*/
+  if (((isrflags & USART_SR_TXE) != RESET) && ((cr1its & USART_CR1_TXEIE) != RESET))
+  {
+    UART_Transmit_IT(huart);
+    return;
+  }
+
+  /* UART in mode Transmitter end --------------------------------------------*/
+  if (((isrflags & USART_SR_TC) != RESET) && ((cr1its & USART_CR1_TCIE) != RESET))
+  {
+    UART_EndTransmit_IT(huart);
+    return;
+  }
+}
+
+/**
+  * @brief  Tx Transfer completed callbacks.
+  * @param  huart  Pointer to a UART_HandleTypeDef structure that contains
+  *                the configuration information for the specified UART module.
+  * @retval None
+  */
+__weak void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(huart);
+  /* NOTE: This function should not be modified, when the callback is needed,
+           the HAL_UART_TxCpltCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Tx Half Transfer completed callbacks.
+  * @param  huart  Pointer to a UART_HandleTypeDef structure that contains
+  *                the configuration information for the specified UART module.
+  * @retval None
+  */
+__weak void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(huart);
+  /* NOTE: This function should not be modified, when the callback is needed,
+           the HAL_UART_TxHalfCpltCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Rx Transfer completed callbacks.
+  * @param  huart  Pointer to a UART_HandleTypeDef structure that contains
+  *                the configuration information for the specified UART module.
+  * @retval None
+  */
+__weak void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(huart);
+  /* NOTE: This function should not be modified, when the callback is needed,
+           the HAL_UART_RxCpltCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Rx Half Transfer completed callbacks.
+  * @param  huart  Pointer to a UART_HandleTypeDef structure that contains
+  *                the configuration information for the specified UART module.
+  * @retval None
+  */
+__weak void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(huart);
+  /* NOTE: This function should not be modified, when the callback is needed,
+           the HAL_UART_RxHalfCpltCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  UART error callbacks.
+  * @param  huart  Pointer to a UART_HandleTypeDef structure that contains
+  *                the configuration information for the specified UART module.
+  * @retval None
+  */
+__weak void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(huart);
+  /* NOTE: This function should not be modified, when the callback is needed,
+           the HAL_UART_ErrorCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  UART Abort Complete callback.
+  * @param  huart UART handle.
+  * @retval None
+  */
+__weak void HAL_UART_AbortCpltCallback(UART_HandleTypeDef *huart)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(huart);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_UART_AbortCpltCallback can be implemented in the user file.
+   */
+}
+
+/**
+  * @brief  UART Abort Complete callback.
+  * @param  huart UART handle.
+  * @retval None
+  */
+__weak void HAL_UART_AbortTransmitCpltCallback(UART_HandleTypeDef *huart)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(huart);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_UART_AbortTransmitCpltCallback can be implemented in the user file.
+   */
+}
+
+/**
+  * @brief  UART Abort Receive Complete callback.
+  * @param  huart UART handle.
+  * @retval None
+  */
+__weak void HAL_UART_AbortReceiveCpltCallback(UART_HandleTypeDef *huart)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(huart);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_UART_AbortReceiveCpltCallback can be implemented in the user file.
+   */
+}
+
+/**
+  * @brief  Reception Event Callback (Rx event notification called after use of advanced reception service).
+  * @param  huart UART handle
+  * @param  Size  Number of data available in application reception buffer (indicates a position in
+  *               reception buffer until which, data are available)
+  * @retval None
+  */
+__weak void HAL_UARTEx_RxEventCallback(UART_HandleTypeDef *huart, uint16_t Size)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(huart);
+  UNUSED(Size);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_UARTEx_RxEventCallback can be implemented in the user file.
+   */
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup UART_Exported_Functions_Group3 Peripheral Control functions
+  *  @brief   UART control functions
+  *
+@verbatim
+  ==============================================================================
+                      ##### Peripheral Control functions #####
+  ==============================================================================
+  [..]
+    This subsection provides a set of functions allowing to control the UART:
+    (+) HAL_LIN_SendBreak() API can be helpful to transmit the break character.
+    (+) HAL_MultiProcessor_EnterMuteMode() API can be helpful to enter the UART in mute mode.
+    (+) HAL_MultiProcessor_ExitMuteMode() API can be helpful to exit the UART mute mode by software.
+    (+) HAL_HalfDuplex_EnableTransmitter() API to enable the UART transmitter and disables the UART receiver in Half Duplex mode
+    (+) HAL_HalfDuplex_EnableReceiver() API to enable the UART receiver and disables the UART transmitter in Half Duplex mode
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Transmits break characters.
+  * @param  huart  Pointer to a UART_HandleTypeDef structure that contains
+  *                the configuration information for the specified UART module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart)
+{
+  /* Check the parameters */
+  assert_param(IS_UART_INSTANCE(huart->Instance));
+
+  /* Process Locked */
+  __HAL_LOCK(huart);
+
+  huart->gState = HAL_UART_STATE_BUSY;
+
+  /* Send break characters */
+  ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_SBK);
+
+  huart->gState = HAL_UART_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(huart);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Enters the UART in mute mode.
+  * @param  huart  Pointer to a UART_HandleTypeDef structure that contains
+  *                the configuration information for the specified UART module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart)
+{
+  /* Check the parameters */
+  assert_param(IS_UART_INSTANCE(huart->Instance));
+
+  /* Process Locked */
+  __HAL_LOCK(huart);
+
+  huart->gState = HAL_UART_STATE_BUSY;
+
+  /* Enable the USART mute mode  by setting the RWU bit in the CR1 register */
+  ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RWU);
+
+  huart->gState = HAL_UART_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(huart);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Exits the UART mute mode: wake up software.
+  * @param  huart  Pointer to a UART_HandleTypeDef structure that contains
+  *                the configuration information for the specified UART module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_MultiProcessor_ExitMuteMode(UART_HandleTypeDef *huart)
+{
+  /* Check the parameters */
+  assert_param(IS_UART_INSTANCE(huart->Instance));
+
+  /* Process Locked */
+  __HAL_LOCK(huart);
+
+  huart->gState = HAL_UART_STATE_BUSY;
+
+  /* Disable the USART mute mode by clearing the RWU bit in the CR1 register */
+  ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RWU);
+
+  huart->gState = HAL_UART_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(huart);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Enables the UART transmitter and disables the UART receiver.
+  * @param  huart  Pointer to a UART_HandleTypeDef structure that contains
+  *                the configuration information for the specified UART module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart)
+{
+  uint32_t tmpreg = 0x00U;
+
+  /* Process Locked */
+  __HAL_LOCK(huart);
+
+  huart->gState = HAL_UART_STATE_BUSY;
+
+  /*-------------------------- USART CR1 Configuration -----------------------*/
+  tmpreg = huart->Instance->CR1;
+
+  /* Clear TE and RE bits */
+  tmpreg &= (uint32_t)~((uint32_t)(USART_CR1_TE | USART_CR1_RE));
+
+  /* Enable the USART's transmit interface by setting the TE bit in the USART CR1 register */
+  tmpreg |= (uint32_t)USART_CR1_TE;
+
+  /* Write to USART CR1 */
+  WRITE_REG(huart->Instance->CR1, (uint32_t)tmpreg);
+
+  huart->gState = HAL_UART_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(huart);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Enables the UART receiver and disables the UART transmitter.
+  * @param  huart  Pointer to a UART_HandleTypeDef structure that contains
+  *                the configuration information for the specified UART module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart)
+{
+  uint32_t tmpreg = 0x00U;
+
+  /* Process Locked */
+  __HAL_LOCK(huart);
+
+  huart->gState = HAL_UART_STATE_BUSY;
+
+  /*-------------------------- USART CR1 Configuration -----------------------*/
+  tmpreg = huart->Instance->CR1;
+
+  /* Clear TE and RE bits */
+  tmpreg &= (uint32_t)~((uint32_t)(USART_CR1_TE | USART_CR1_RE));
+
+  /* Enable the USART's receive interface by setting the RE bit in the USART CR1 register */
+  tmpreg |= (uint32_t)USART_CR1_RE;
+
+  /* Write to USART CR1 */
+  WRITE_REG(huart->Instance->CR1, (uint32_t)tmpreg);
+
+  huart->gState = HAL_UART_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(huart);
+
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup UART_Exported_Functions_Group4 Peripheral State and Errors functions
+  *  @brief   UART State and Errors functions
+  *
+@verbatim
+  ==============================================================================
+                 ##### Peripheral State and Errors functions #####
+  ==============================================================================
+ [..]
+   This subsection provides a set of functions allowing to return the State of
+   UART communication process, return Peripheral Errors occurred during communication
+   process
+   (+) HAL_UART_GetState() API can be helpful to check in run-time the state of the UART peripheral.
+   (+) HAL_UART_GetError() check in run-time errors that could be occurred during communication.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Returns the UART state.
+  * @param  huart  Pointer to a UART_HandleTypeDef structure that contains
+  *                the configuration information for the specified UART module.
+  * @retval HAL state
+  */
+HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart)
+{
+  uint32_t temp1 = 0x00U, temp2 = 0x00U;
+  temp1 = huart->gState;
+  temp2 = huart->RxState;
+
+  return (HAL_UART_StateTypeDef)(temp1 | temp2);
+}
+
+/**
+  * @brief  Return the UART error code
+  * @param  huart Pointer to a UART_HandleTypeDef structure that contains
+  *               the configuration information for the specified UART.
+  * @retval UART Error Code
+  */
+uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart)
+{
+  return huart->ErrorCode;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup UART_Private_Functions UART Private Functions
+  * @{
+  */
+
+/**
+  * @brief  Initialize the callbacks to their default values.
+  * @param  huart UART handle.
+  * @retval none
+  */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+void UART_InitCallbacksToDefault(UART_HandleTypeDef *huart)
+{
+  /* Init the UART Callback settings */
+  huart->TxHalfCpltCallback        = HAL_UART_TxHalfCpltCallback;        /* Legacy weak TxHalfCpltCallback        */
+  huart->TxCpltCallback            = HAL_UART_TxCpltCallback;            /* Legacy weak TxCpltCallback            */
+  huart->RxHalfCpltCallback        = HAL_UART_RxHalfCpltCallback;        /* Legacy weak RxHalfCpltCallback        */
+  huart->RxCpltCallback            = HAL_UART_RxCpltCallback;            /* Legacy weak RxCpltCallback            */
+  huart->ErrorCallback             = HAL_UART_ErrorCallback;             /* Legacy weak ErrorCallback             */
+  huart->AbortCpltCallback         = HAL_UART_AbortCpltCallback;         /* Legacy weak AbortCpltCallback         */
+  huart->AbortTransmitCpltCallback = HAL_UART_AbortTransmitCpltCallback; /* Legacy weak AbortTransmitCpltCallback */
+  huart->AbortReceiveCpltCallback  = HAL_UART_AbortReceiveCpltCallback;  /* Legacy weak AbortReceiveCpltCallback  */
+  huart->RxEventCallback           = HAL_UARTEx_RxEventCallback;         /* Legacy weak RxEventCallback           */
+
+}
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+
+/**
+  * @brief  DMA UART transmit process complete callback.
+  * @param  hdma  Pointer to a DMA_HandleTypeDef structure that contains
+  *               the configuration information for the specified DMA module.
+  * @retval None
+  */
+static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma)
+{
+  UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+  /* DMA Normal mode*/
+  if ((hdma->Instance->CR & DMA_SxCR_CIRC) == 0U)
+  {
+    huart->TxXferCount = 0x00U;
+
+    /* Disable the DMA transfer for transmit request by setting the DMAT bit
+       in the UART CR3 register */
+    ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
+
+    /* Enable the UART Transmit Complete Interrupt */
+    ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);
+
+  }
+  /* DMA Circular mode */
+  else
+  {
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+    /*Call registered Tx complete callback*/
+    huart->TxCpltCallback(huart);
+#else
+    /*Call legacy weak Tx complete callback*/
+    HAL_UART_TxCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+  }
+}
+
+/**
+  * @brief DMA UART transmit process half complete callback
+  * @param  hdma  Pointer to a DMA_HandleTypeDef structure that contains
+  *               the configuration information for the specified DMA module.
+  * @retval None
+  */
+static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
+{
+  UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+  /*Call registered Tx complete callback*/
+  huart->TxHalfCpltCallback(huart);
+#else
+  /*Call legacy weak Tx complete callback*/
+  HAL_UART_TxHalfCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+}
+
+/**
+  * @brief  DMA UART receive process complete callback.
+  * @param  hdma  Pointer to a DMA_HandleTypeDef structure that contains
+  *               the configuration information for the specified DMA module.
+  * @retval None
+  */
+static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
+{
+  UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+  /* DMA Normal mode*/
+  if ((hdma->Instance->CR & DMA_SxCR_CIRC) == 0U)
+  {
+    huart->RxXferCount = 0U;
+
+    /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
+    ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
+    ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+
+    /* Disable the DMA transfer for the receiver request by setting the DMAR bit
+       in the UART CR3 register */
+    ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+
+    /* At end of Rx process, restore huart->RxState to Ready */
+    huart->RxState = HAL_UART_STATE_READY;
+
+    /* If Reception till IDLE event has been selected, Disable IDLE Interrupt */
+    if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
+    {
+      ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
+    }
+  }
+
+  /* Check current reception Mode :
+     If Reception till IDLE event has been selected : use Rx Event callback */
+  if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
+  {
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+    /*Call registered Rx Event callback*/
+    huart->RxEventCallback(huart, huart->RxXferSize);
+#else
+    /*Call legacy weak Rx Event callback*/
+    HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+  }
+  else
+  {
+    /* In other cases : use Rx Complete callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+    /*Call registered Rx complete callback*/
+    huart->RxCpltCallback(huart);
+#else
+    /*Call legacy weak Rx complete callback*/
+    HAL_UART_RxCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+  }
+}
+
+/**
+  * @brief DMA UART receive process half complete callback
+  * @param  hdma  Pointer to a DMA_HandleTypeDef structure that contains
+  *               the configuration information for the specified DMA module.
+  * @retval None
+  */
+static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
+{
+  UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+  /* Check current reception Mode :
+     If Reception till IDLE event has been selected : use Rx Event callback */
+  if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
+  {
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+    /*Call registered Rx Event callback*/
+    huart->RxEventCallback(huart, huart->RxXferSize / 2U);
+#else
+    /*Call legacy weak Rx Event callback*/
+    HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize / 2U);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+  }
+  else
+  {
+    /* In other cases : use Rx Half Complete callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+    /*Call registered Rx Half complete callback*/
+    huart->RxHalfCpltCallback(huart);
+#else
+    /*Call legacy weak Rx Half complete callback*/
+    HAL_UART_RxHalfCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+  }
+}
+
+/**
+  * @brief  DMA UART communication error callback.
+  * @param  hdma  Pointer to a DMA_HandleTypeDef structure that contains
+  *               the configuration information for the specified DMA module.
+  * @retval None
+  */
+static void UART_DMAError(DMA_HandleTypeDef *hdma)
+{
+  uint32_t dmarequest = 0x00U;
+  UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+  /* Stop UART DMA Tx request if ongoing */
+  dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT);
+  if ((huart->gState == HAL_UART_STATE_BUSY_TX) && dmarequest)
+  {
+    huart->TxXferCount = 0x00U;
+    UART_EndTxTransfer(huart);
+  }
+
+  /* Stop UART DMA Rx request if ongoing */
+  dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR);
+  if ((huart->RxState == HAL_UART_STATE_BUSY_RX) && dmarequest)
+  {
+    huart->RxXferCount = 0x00U;
+    UART_EndRxTransfer(huart);
+  }
+
+  huart->ErrorCode |= HAL_UART_ERROR_DMA;
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+  /*Call registered error callback*/
+  huart->ErrorCallback(huart);
+#else
+  /*Call legacy weak error callback*/
+  HAL_UART_ErrorCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+}
+
+/**
+  * @brief  This function handles UART Communication Timeout. It waits
+  *         until a flag is no longer in the specified status.
+  * @param  huart  Pointer to a UART_HandleTypeDef structure that contains
+  *                the configuration information for the specified UART module.
+  * @param  Flag specifies the UART flag to check.
+  * @param  Status The actual Flag status (SET or RESET).
+  * @param  Tickstart Tick start value
+  * @param  Timeout Timeout duration
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status,
+                                                     uint32_t Tickstart, uint32_t Timeout)
+{
+  /* Wait until flag is set */
+  while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
+  {
+    /* Check for the Timeout */
+    if (Timeout != HAL_MAX_DELAY)
+    {
+      if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) > Timeout))
+      {
+        /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
+        ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE));
+        ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+
+        huart->gState  = HAL_UART_STATE_READY;
+        huart->RxState = HAL_UART_STATE_READY;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(huart);
+
+        return HAL_TIMEOUT;
+      }
+    }
+  }
+  return HAL_OK;
+}
+
+/**
+  * @brief  Start Receive operation in interrupt mode.
+  * @note   This function could be called by all HAL UART API providing reception in Interrupt mode.
+  * @note   When calling this function, parameters validity is considered as already checked,
+  *         i.e. Rx State, buffer address, ...
+  *         UART Handle is assumed as Locked.
+  * @param  huart UART handle.
+  * @param  pData Pointer to data buffer (u8 or u16 data elements).
+  * @param  Size  Amount of data elements (u8 or u16) to be received.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef UART_Start_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
+{
+  huart->pRxBuffPtr = pData;
+  huart->RxXferSize = Size;
+  huart->RxXferCount = Size;
+
+  huart->ErrorCode = HAL_UART_ERROR_NONE;
+  huart->RxState = HAL_UART_STATE_BUSY_RX;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(huart);
+
+  if (huart->Init.Parity != UART_PARITY_NONE)
+  {
+    /* Enable the UART Parity Error Interrupt */
+    __HAL_UART_ENABLE_IT(huart, UART_IT_PE);
+  }
+
+  /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */
+  __HAL_UART_ENABLE_IT(huart, UART_IT_ERR);
+
+  /* Enable the UART Data Register not empty Interrupt */
+  __HAL_UART_ENABLE_IT(huart, UART_IT_RXNE);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Start Receive operation in DMA mode.
+  * @note   This function could be called by all HAL UART API providing reception in DMA mode.
+  * @note   When calling this function, parameters validity is considered as already checked,
+  *         i.e. Rx State, buffer address, ...
+  *         UART Handle is assumed as Locked.
+  * @param  huart UART handle.
+  * @param  pData Pointer to data buffer (u8 or u16 data elements).
+  * @param  Size  Amount of data elements (u8 or u16) to be received.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef UART_Start_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
+{
+  uint32_t *tmp;
+
+  huart->pRxBuffPtr = pData;
+  huart->RxXferSize = Size;
+
+  huart->ErrorCode = HAL_UART_ERROR_NONE;
+  huart->RxState = HAL_UART_STATE_BUSY_RX;
+
+  /* Set the UART DMA transfer complete callback */
+  huart->hdmarx->XferCpltCallback = UART_DMAReceiveCplt;
+
+  /* Set the UART DMA Half transfer complete callback */
+  huart->hdmarx->XferHalfCpltCallback = UART_DMARxHalfCplt;
+
+  /* Set the DMA error callback */
+  huart->hdmarx->XferErrorCallback = UART_DMAError;
+
+  /* Set the DMA abort callback */
+  huart->hdmarx->XferAbortCallback = NULL;
+
+  /* Enable the DMA stream */
+  tmp = (uint32_t *)&pData;
+  HAL_DMA_Start_IT(huart->hdmarx, (uint32_t)&huart->Instance->DR, *(uint32_t *)tmp, Size);
+
+  /* Clear the Overrun flag just before enabling the DMA Rx request: can be mandatory for the second transfer */
+  __HAL_UART_CLEAR_OREFLAG(huart);
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(huart);
+
+  if (huart->Init.Parity != UART_PARITY_NONE)
+  {
+    /* Enable the UART Parity Error Interrupt */
+    ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE);
+  }
+
+  /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */
+  ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_EIE);
+
+  /* Enable the DMA transfer for the receiver request by setting the DMAR bit
+  in the UART CR3 register */
+  ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  End ongoing Tx transfer on UART peripheral (following error detection or Transmit completion).
+  * @param  huart UART handle.
+  * @retval None
+  */
+static void UART_EndTxTransfer(UART_HandleTypeDef *huart)
+{
+  /* Disable TXEIE and TCIE interrupts */
+  ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
+
+  /* At end of Tx process, restore huart->gState to Ready */
+  huart->gState = HAL_UART_STATE_READY;
+}
+
+/**
+  * @brief  End ongoing Rx transfer on UART peripheral (following error detection or Reception completion).
+  * @param  huart UART handle.
+  * @retval None
+  */
+static void UART_EndRxTransfer(UART_HandleTypeDef *huart)
+{
+  /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
+  ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
+  ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+
+  /* In case of reception waiting for IDLE event, disable also the IDLE IE interrupt source */
+  if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
+  {
+    ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
+  }
+
+  /* At end of Rx process, restore huart->RxState to Ready */
+  huart->RxState = HAL_UART_STATE_READY;
+  huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+}
+
+/**
+  * @brief  DMA UART communication abort callback, when initiated by HAL services on Error
+  *         (To be called at end of DMA Abort procedure following error occurrence).
+  * @param  hdma  Pointer to a DMA_HandleTypeDef structure that contains
+  *               the configuration information for the specified DMA module.
+  * @retval None
+  */
+static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma)
+{
+  UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+  huart->RxXferCount = 0x00U;
+  huart->TxXferCount = 0x00U;
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+  /*Call registered error callback*/
+  huart->ErrorCallback(huart);
+#else
+  /*Call legacy weak error callback*/
+  HAL_UART_ErrorCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+}
+
+/**
+  * @brief  DMA UART Tx communication abort callback, when initiated by user
+  *         (To be called at end of DMA Tx Abort procedure following user abort request).
+  * @note   When this callback is executed, User Abort complete call back is called only if no
+  *         Abort still ongoing for Rx DMA Handle.
+  * @param  hdma  Pointer to a DMA_HandleTypeDef structure that contains
+  *               the configuration information for the specified DMA module.
+  * @retval None
+  */
+static void UART_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
+{
+  UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+  huart->hdmatx->XferAbortCallback = NULL;
+
+  /* Check if an Abort process is still ongoing */
+  if (huart->hdmarx != NULL)
+  {
+    if (huart->hdmarx->XferAbortCallback != NULL)
+    {
+      return;
+    }
+  }
+
+  /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
+  huart->TxXferCount = 0x00U;
+  huart->RxXferCount = 0x00U;
+
+  /* Reset ErrorCode */
+  huart->ErrorCode = HAL_UART_ERROR_NONE;
+
+  /* Restore huart->gState and huart->RxState to Ready */
+  huart->gState  = HAL_UART_STATE_READY;
+  huart->RxState = HAL_UART_STATE_READY;
+  huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+
+  /* Call user Abort complete callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+  /* Call registered Abort complete callback */
+  huart->AbortCpltCallback(huart);
+#else
+  /* Call legacy weak Abort complete callback */
+  HAL_UART_AbortCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+}
+
+/**
+  * @brief  DMA UART Rx communication abort callback, when initiated by user
+  *         (To be called at end of DMA Rx Abort procedure following user abort request).
+  * @note   When this callback is executed, User Abort complete call back is called only if no
+  *         Abort still ongoing for Tx DMA Handle.
+  * @param  hdma  Pointer to a DMA_HandleTypeDef structure that contains
+  *               the configuration information for the specified DMA module.
+  * @retval None
+  */
+static void UART_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
+{
+  UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+  huart->hdmarx->XferAbortCallback = NULL;
+
+  /* Check if an Abort process is still ongoing */
+  if (huart->hdmatx != NULL)
+  {
+    if (huart->hdmatx->XferAbortCallback != NULL)
+    {
+      return;
+    }
+  }
+
+  /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
+  huart->TxXferCount = 0x00U;
+  huart->RxXferCount = 0x00U;
+
+  /* Reset ErrorCode */
+  huart->ErrorCode = HAL_UART_ERROR_NONE;
+
+  /* Restore huart->gState and huart->RxState to Ready */
+  huart->gState  = HAL_UART_STATE_READY;
+  huart->RxState = HAL_UART_STATE_READY;
+  huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+
+  /* Call user Abort complete callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+  /* Call registered Abort complete callback */
+  huart->AbortCpltCallback(huart);
+#else
+  /* Call legacy weak Abort complete callback */
+  HAL_UART_AbortCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+}
+
+/**
+  * @brief  DMA UART Tx communication abort callback, when initiated by user by a call to
+  *         HAL_UART_AbortTransmit_IT API (Abort only Tx transfer)
+  *         (This callback is executed at end of DMA Tx Abort procedure following user abort request,
+  *         and leads to user Tx Abort Complete callback execution).
+  * @param  hdma  Pointer to a DMA_HandleTypeDef structure that contains
+  *               the configuration information for the specified DMA module.
+  * @retval None
+  */
+static void UART_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
+{
+  UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+  huart->TxXferCount = 0x00U;
+
+  /* Restore huart->gState to Ready */
+  huart->gState = HAL_UART_STATE_READY;
+
+  /* Call user Abort complete callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+  /* Call registered Abort Transmit Complete Callback */
+  huart->AbortTransmitCpltCallback(huart);
+#else
+  /* Call legacy weak Abort Transmit Complete Callback */
+  HAL_UART_AbortTransmitCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+}
+
+/**
+  * @brief  DMA UART Rx communication abort callback, when initiated by user by a call to
+  *         HAL_UART_AbortReceive_IT API (Abort only Rx transfer)
+  *         (This callback is executed at end of DMA Rx Abort procedure following user abort request,
+  *         and leads to user Rx Abort Complete callback execution).
+  * @param  hdma  Pointer to a DMA_HandleTypeDef structure that contains
+  *               the configuration information for the specified DMA module.
+  * @retval None
+  */
+static void UART_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
+{
+  UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+  huart->RxXferCount = 0x00U;
+
+  /* Restore huart->RxState to Ready */
+  huart->RxState = HAL_UART_STATE_READY;
+  huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+
+  /* Call user Abort complete callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+  /* Call registered Abort Receive Complete Callback */
+  huart->AbortReceiveCpltCallback(huart);
+#else
+  /* Call legacy weak Abort Receive Complete Callback */
+  HAL_UART_AbortReceiveCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+}
+
+/**
+  * @brief  Sends an amount of data in non blocking mode.
+  * @param  huart  Pointer to a UART_HandleTypeDef structure that contains
+  *                the configuration information for the specified UART module.
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart)
+{
+  const uint16_t *tmp;
+
+  /* Check that a Tx process is ongoing */
+  if (huart->gState == HAL_UART_STATE_BUSY_TX)
+  {
+    if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
+    {
+      tmp = (const uint16_t *) huart->pTxBuffPtr;
+      huart->Instance->DR = (uint16_t)(*tmp & (uint16_t)0x01FF);
+      huart->pTxBuffPtr += 2U;
+    }
+    else
+    {
+      huart->Instance->DR = (uint8_t)(*huart->pTxBuffPtr++ & (uint8_t)0x00FF);
+    }
+
+    if (--huart->TxXferCount == 0U)
+    {
+      /* Disable the UART Transmit Data Register Empty Interrupt */
+      __HAL_UART_DISABLE_IT(huart, UART_IT_TXE);
+
+      /* Enable the UART Transmit Complete Interrupt */
+      __HAL_UART_ENABLE_IT(huart, UART_IT_TC);
+    }
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Wraps up transmission in non blocking mode.
+  * @param  huart  Pointer to a UART_HandleTypeDef structure that contains
+  *                the configuration information for the specified UART module.
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef UART_EndTransmit_IT(UART_HandleTypeDef *huart)
+{
+  /* Disable the UART Transmit Complete Interrupt */
+  __HAL_UART_DISABLE_IT(huart, UART_IT_TC);
+
+  /* Tx process is ended, restore huart->gState to Ready */
+  huart->gState = HAL_UART_STATE_READY;
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+  /*Call registered Tx complete callback*/
+  huart->TxCpltCallback(huart);
+#else
+  /*Call legacy weak Tx complete callback*/
+  HAL_UART_TxCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Receives an amount of data in non blocking mode
+  * @param  huart  Pointer to a UART_HandleTypeDef structure that contains
+  *                the configuration information for the specified UART module.
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart)
+{
+  uint8_t  *pdata8bits;
+  uint16_t *pdata16bits;
+
+  /* Check that a Rx process is ongoing */
+  if (huart->RxState == HAL_UART_STATE_BUSY_RX)
+  {
+    if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
+    {
+      pdata8bits  = NULL;
+      pdata16bits = (uint16_t *) huart->pRxBuffPtr;
+      *pdata16bits = (uint16_t)(huart->Instance->DR & (uint16_t)0x01FF);
+      huart->pRxBuffPtr += 2U;
+    }
+    else
+    {
+      pdata8bits = (uint8_t *) huart->pRxBuffPtr;
+      pdata16bits  = NULL;
+
+      if ((huart->Init.WordLength == UART_WORDLENGTH_9B) || ((huart->Init.WordLength == UART_WORDLENGTH_8B) && (huart->Init.Parity == UART_PARITY_NONE)))
+      {
+        *pdata8bits = (uint8_t)(huart->Instance->DR & (uint8_t)0x00FF);
+      }
+      else
+      {
+        *pdata8bits = (uint8_t)(huart->Instance->DR & (uint8_t)0x007F);
+      }
+      huart->pRxBuffPtr += 1U;
+    }
+
+    if (--huart->RxXferCount == 0U)
+    {
+      /* Disable the UART Data Register not empty Interrupt */
+      __HAL_UART_DISABLE_IT(huart, UART_IT_RXNE);
+
+      /* Disable the UART Parity Error Interrupt */
+      __HAL_UART_DISABLE_IT(huart, UART_IT_PE);
+
+      /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */
+      __HAL_UART_DISABLE_IT(huart, UART_IT_ERR);
+
+      /* Rx process is completed, restore huart->RxState to Ready */
+      huart->RxState = HAL_UART_STATE_READY;
+
+      /* Check current reception Mode :
+         If Reception till IDLE event has been selected : */
+      if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
+      {
+        /* Set reception type to Standard */
+        huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+
+        /* Disable IDLE interrupt */
+        ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
+
+        /* Check if IDLE flag is set */
+        if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE))
+        {
+          /* Clear IDLE flag in ISR */
+          __HAL_UART_CLEAR_IDLEFLAG(huart);
+        }
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+        /*Call registered Rx Event callback*/
+        huart->RxEventCallback(huart, huart->RxXferSize);
+#else
+        /*Call legacy weak Rx Event callback*/
+        HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+      }
+      else
+      {
+        /* Standard reception API called */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+        /*Call registered Rx complete callback*/
+        huart->RxCpltCallback(huart);
+#else
+        /*Call legacy weak Rx complete callback*/
+        HAL_UART_RxCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+      }
+
+      return HAL_OK;
+    }
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Configures the UART peripheral.
+  * @param  huart  Pointer to a UART_HandleTypeDef structure that contains
+  *                the configuration information for the specified UART module.
+  * @retval None
+  */
+static void UART_SetConfig(UART_HandleTypeDef *huart)
+{
+  uint32_t tmpreg;
+  uint32_t pclk;
+
+  /* Check the parameters */
+  assert_param(IS_UART_BAUDRATE(huart->Init.BaudRate));
+  assert_param(IS_UART_STOPBITS(huart->Init.StopBits));
+  assert_param(IS_UART_PARITY(huart->Init.Parity));
+  assert_param(IS_UART_MODE(huart->Init.Mode));
+
+  /*-------------------------- USART CR2 Configuration -----------------------*/
+  /* Configure the UART Stop Bits: Set STOP[13:12] bits
+     according to huart->Init.StopBits value */
+  MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits);
+
+  /*-------------------------- USART CR1 Configuration -----------------------*/
+  /* Configure the UART Word Length, Parity and mode:
+     Set the M bits according to huart->Init.WordLength value
+     Set PCE and PS bits according to huart->Init.Parity value
+     Set TE and RE bits according to huart->Init.Mode value
+     Set OVER8 bit according to huart->Init.OverSampling value */
+
+  tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling;
+  MODIFY_REG(huart->Instance->CR1,
+             (uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8),
+             tmpreg);
+
+  /*-------------------------- USART CR3 Configuration -----------------------*/
+  /* Configure the UART HFC: Set CTSE and RTSE bits according to huart->Init.HwFlowCtl value */
+  MODIFY_REG(huart->Instance->CR3, (USART_CR3_RTSE | USART_CR3_CTSE), huart->Init.HwFlowCtl);
+
+
+#if defined(USART6) && defined(UART9) && defined(UART10)
+    if ((huart->Instance == USART1) || (huart->Instance == USART6) || (huart->Instance == UART9) || (huart->Instance == UART10))
+    {
+      pclk = HAL_RCC_GetPCLK2Freq();
+    }
+#elif defined(USART6)
+    if ((huart->Instance == USART1) || (huart->Instance == USART6))
+    {
+      pclk = HAL_RCC_GetPCLK2Freq();
+    }
+#else
+    if (huart->Instance == USART1)
+    {
+      pclk = HAL_RCC_GetPCLK2Freq();
+    }
+#endif /* USART6 */
+    else
+    {
+      pclk = HAL_RCC_GetPCLK1Freq();
+    }
+  /*-------------------------- USART BRR Configuration ---------------------*/
+  if (huart->Init.OverSampling == UART_OVERSAMPLING_8)
+  {
+    huart->Instance->BRR = UART_BRR_SAMPLING8(pclk, huart->Init.BaudRate);
+  }
+  else
+  {
+    huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate);
+  }
+}
+
+/**
+  * @}
+  */
+
+#endif /* HAL_UART_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
diff --git a/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_fmc.c b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_fmc.c
new file mode 100644
index 0000000..a53d419
--- /dev/null
+++ b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_fmc.c
@@ -0,0 +1,1498 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_ll_fmc.c
+  * @author  MCD Application Team
+  * @brief   FMC Low Layer HAL module driver.
+  *
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the Flexible Memory Controller (FMC) peripheral memories:
+  *           + Initialization/de-initialization functions
+  *           + Peripheral Control functions
+  *           + Peripheral State functions
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2016 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  @verbatim
+  ==============================================================================
+                        ##### FMC peripheral features #####
+  ==============================================================================
+  [..] The Flexible memory controller (FMC) includes following memory controllers:
+       (+) The NOR/PSRAM memory controller
+       (+) The NAND/PC Card memory controller
+       (+) The Synchronous DRAM (SDRAM) controller
+
+  [..] The FMC functional block makes the interface with synchronous and asynchronous static
+       memories, SDRAM memories, and 16-bit PC memory cards. Its main purposes are:
+       (+) to translate AHB transactions into the appropriate external device protocol
+       (+) to meet the access time requirements of the external memory devices
+
+  [..] All external memories share the addresses, data and control signals with the controller.
+       Each external device is accessed by means of a unique Chip Select. The FMC performs
+       only one access at a time to an external device.
+       The main features of the FMC controller are the following:
+        (+) Interface with static-memory mapped devices including:
+           (++) Static random access memory (SRAM)
+           (++) Read-only memory (ROM)
+           (++) NOR Flash memory/OneNAND Flash memory
+           (++) PSRAM (4 memory banks)
+           (++) 16-bit PC Card compatible devices
+           (++) Two banks of NAND Flash memory with ECC hardware to check up to 8 Kbytes of
+                data
+        (+) Interface with synchronous DRAM (SDRAM) memories
+        (+) Independent Chip Select control for each memory bank
+        (+) Independent configuration for each memory bank
+
+  @endverbatim
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+  * @{
+  */
+#if defined(HAL_NOR_MODULE_ENABLED) || defined(HAL_SRAM_MODULE_ENABLED) || (defined(HAL_NAND_MODULE_ENABLED)) || defined(HAL_PCCARD_MODULE_ENABLED) || defined(HAL_SDRAM_MODULE_ENABLED)
+
+/** @defgroup FMC_LL  FMC Low Layer
+  * @brief FMC driver modules
+  * @{
+  */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+
+/** @defgroup FMC_LL_Private_Constants FMC Low Layer Private Constants
+  * @{
+  */
+
+/* ----------------------- FMC registers bit mask --------------------------- */
+
+#if defined(FMC_Bank1)
+/* --- BCR Register ---*/
+/* BCR register clear mask */
+
+/* --- BTR Register ---*/
+/* BTR register clear mask */
+#define BTR_CLEAR_MASK    ((uint32_t)(FMC_BTR1_ADDSET | FMC_BTR1_ADDHLD  |\
+                                      FMC_BTR1_DATAST | FMC_BTR1_BUSTURN |\
+                                      FMC_BTR1_CLKDIV | FMC_BTR1_DATLAT  |\
+                                      FMC_BTR1_ACCMOD))
+
+/* --- BWTR Register ---*/
+/* BWTR register clear mask */
+#define BWTR_CLEAR_MASK   ((uint32_t)(FMC_BWTR1_ADDSET | FMC_BWTR1_ADDHLD  |\
+                                      FMC_BWTR1_DATAST | FMC_BWTR1_BUSTURN |\
+                                      FMC_BWTR1_ACCMOD))
+#endif /* FMC_Bank1 */
+#if defined(FMC_Bank3) || defined(FMC_Bank2_3)
+
+#if defined (FMC_PCR_PWAITEN)
+/* --- PCR Register ---*/
+/* PCR register clear mask */
+#define PCR_CLEAR_MASK    ((uint32_t)(FMC_PCR_PWAITEN | FMC_PCR_PBKEN  | \
+                                      FMC_PCR_PTYP    | FMC_PCR_PWID   | \
+                                      FMC_PCR_ECCEN   | FMC_PCR_TCLR   | \
+                                      FMC_PCR_TAR     | FMC_PCR_ECCPS))
+/* --- PMEM Register ---*/
+/* PMEM register clear mask */
+#define PMEM_CLEAR_MASK   ((uint32_t)(FMC_PMEM_MEMSET2  | FMC_PMEM_MEMWAIT2 |\
+                                      FMC_PMEM_MEMHOLD2 | FMC_PMEM_MEMHIZ2))
+
+/* --- PATT Register ---*/
+/* PATT register clear mask */
+#define PATT_CLEAR_MASK   ((uint32_t)(FMC_PATT_ATTSET2  | FMC_PATT_ATTWAIT2 |\
+                                      FMC_PATT_ATTHOLD2 | FMC_PATT_ATTHIZ2))
+#else
+/* --- PCR Register ---*/
+/* PCR register clear mask */
+#define PCR_CLEAR_MASK    ((uint32_t)(FMC_PCR2_PWAITEN | FMC_PCR2_PBKEN  | \
+                                      FMC_PCR2_PTYP    | FMC_PCR2_PWID   | \
+                                      FMC_PCR2_ECCEN   | FMC_PCR2_TCLR   | \
+                                      FMC_PCR2_TAR     | FMC_PCR2_ECCPS))
+/* --- PMEM Register ---*/
+/* PMEM register clear mask */
+#define PMEM_CLEAR_MASK   ((uint32_t)(FMC_PMEM2_MEMSET2  | FMC_PMEM2_MEMWAIT2 |\
+                                      FMC_PMEM2_MEMHOLD2 | FMC_PMEM2_MEMHIZ2))
+
+/* --- PATT Register ---*/
+/* PATT register clear mask */
+#define PATT_CLEAR_MASK   ((uint32_t)(FMC_PATT2_ATTSET2  | FMC_PATT2_ATTWAIT2 |\
+                                      FMC_PATT2_ATTHOLD2 | FMC_PATT2_ATTHIZ2))
+
+#endif /* FMC_PCR_PWAITEN */
+#endif /* FMC_Bank3) || defined(FMC_Bank2_3 */
+#if defined(FMC_Bank4)
+/* --- PCR Register ---*/
+/* PCR register clear mask */
+#define PCR4_CLEAR_MASK   ((uint32_t)(FMC_PCR4_PWAITEN | FMC_PCR4_PBKEN  | \
+                                      FMC_PCR4_PTYP    | FMC_PCR4_PWID   | \
+                                      FMC_PCR4_ECCEN   | FMC_PCR4_TCLR   | \
+                                      FMC_PCR4_TAR     | FMC_PCR4_ECCPS))
+/* --- PMEM Register ---*/
+/* PMEM register clear mask */
+#define PMEM4_CLEAR_MASK  ((uint32_t)(FMC_PMEM4_MEMSET4  | FMC_PMEM4_MEMWAIT4 |\
+                                      FMC_PMEM4_MEMHOLD4 | FMC_PMEM4_MEMHIZ4))
+
+/* --- PATT Register ---*/
+/* PATT register clear mask */
+#define PATT4_CLEAR_MASK  ((uint32_t)(FMC_PATT4_ATTSET4  | FMC_PATT4_ATTWAIT4 |\
+                                      FMC_PATT4_ATTHOLD4 | FMC_PATT4_ATTHIZ4))
+
+/* --- PIO4 Register ---*/
+/* PIO4 register clear mask */
+#define PIO4_CLEAR_MASK   ((uint32_t)(FMC_PIO4_IOSET4  | FMC_PIO4_IOWAIT4 | \
+                                      FMC_PIO4_IOHOLD4 | FMC_PIO4_IOHIZ4))
+
+#endif /* FMC_Bank4 */
+#if defined(FMC_Bank5_6)
+
+/* --- SDCR Register ---*/
+/* SDCR register clear mask */
+#define SDCR_CLEAR_MASK   ((uint32_t)(FMC_SDCR1_NC    | FMC_SDCR1_NR     | \
+                                      FMC_SDCR1_MWID  | FMC_SDCR1_NB     | \
+                                      FMC_SDCR1_CAS   | FMC_SDCR1_WP     | \
+                                      FMC_SDCR1_SDCLK | FMC_SDCR1_RBURST | \
+                                      FMC_SDCR1_RPIPE))
+
+/* --- SDTR Register ---*/
+/* SDTR register clear mask */
+#define SDTR_CLEAR_MASK   ((uint32_t)(FMC_SDTR1_TMRD  | FMC_SDTR1_TXSR   | \
+                                      FMC_SDTR1_TRAS  | FMC_SDTR1_TRC    | \
+                                      FMC_SDTR1_TWR   | FMC_SDTR1_TRP    | \
+                                      FMC_SDTR1_TRCD))
+#endif /* FMC_Bank5_6 */
+
+/**
+  * @}
+  */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup FMC_LL_Exported_Functions FMC Low Layer Exported Functions
+  * @{
+  */
+
+#if defined(FMC_Bank1)
+
+/** @defgroup FMC_LL_Exported_Functions_NORSRAM FMC Low Layer NOR SRAM Exported Functions
+  * @brief  NORSRAM Controller functions
+  *
+  @verbatim
+  ==============================================================================
+                   ##### How to use NORSRAM device driver #####
+  ==============================================================================
+
+  [..]
+    This driver contains a set of APIs to interface with the FMC NORSRAM banks in order
+    to run the NORSRAM external devices.
+
+    (+) FMC NORSRAM bank reset using the function FMC_NORSRAM_DeInit()
+    (+) FMC NORSRAM bank control configuration using the function FMC_NORSRAM_Init()
+    (+) FMC NORSRAM bank timing configuration using the function FMC_NORSRAM_Timing_Init()
+    (+) FMC NORSRAM bank extended timing configuration using the function
+        FMC_NORSRAM_Extended_Timing_Init()
+    (+) FMC NORSRAM bank enable/disable write operation using the functions
+        FMC_NORSRAM_WriteOperation_Enable()/FMC_NORSRAM_WriteOperation_Disable()
+
+@endverbatim
+  * @{
+  */
+
+/** @defgroup FMC_LL_NORSRAM_Exported_Functions_Group1 Initialization and de-initialization functions
+  * @brief    Initialization and Configuration functions
+  *
+  @verbatim
+  ==============================================================================
+              ##### Initialization and de_initialization functions #####
+  ==============================================================================
+  [..]
+    This section provides functions allowing to:
+    (+) Initialize and configure the FMC NORSRAM interface
+    (+) De-initialize the FMC NORSRAM interface
+    (+) Configure the FMC clock and associated GPIOs
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initialize the FMC_NORSRAM device according to the specified
+  *         control parameters in the FMC_NORSRAM_InitTypeDef
+  * @param  Device Pointer to NORSRAM device instance
+  * @param  Init Pointer to NORSRAM Initialization structure
+  * @retval HAL status
+  */
+HAL_StatusTypeDef  FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device,
+                                    FMC_NORSRAM_InitTypeDef *Init)
+{
+  uint32_t flashaccess;
+  uint32_t btcr_reg;
+  uint32_t mask;
+
+  /* Check the parameters */
+  assert_param(IS_FMC_NORSRAM_DEVICE(Device));
+  assert_param(IS_FMC_NORSRAM_BANK(Init->NSBank));
+  assert_param(IS_FMC_MUX(Init->DataAddressMux));
+  assert_param(IS_FMC_MEMORY(Init->MemoryType));
+  assert_param(IS_FMC_NORSRAM_MEMORY_WIDTH(Init->MemoryDataWidth));
+  assert_param(IS_FMC_BURSTMODE(Init->BurstAccessMode));
+  assert_param(IS_FMC_WAIT_POLARITY(Init->WaitSignalPolarity));
+#if defined(FMC_BCR1_WRAPMOD)
+  assert_param(IS_FMC_WRAP_MODE(Init->WrapMode));
+#endif /* FMC_BCR1_WRAPMOD */
+  assert_param(IS_FMC_WAIT_SIGNAL_ACTIVE(Init->WaitSignalActive));
+  assert_param(IS_FMC_WRITE_OPERATION(Init->WriteOperation));
+  assert_param(IS_FMC_WAITE_SIGNAL(Init->WaitSignal));
+  assert_param(IS_FMC_EXTENDED_MODE(Init->ExtendedMode));
+  assert_param(IS_FMC_ASYNWAIT(Init->AsynchronousWait));
+  assert_param(IS_FMC_WRITE_BURST(Init->WriteBurst));
+#if defined(FMC_BCR1_CCLKEN)
+  assert_param(IS_FMC_CONTINOUS_CLOCK(Init->ContinuousClock));
+#endif
+#if defined(FMC_BCR1_WFDIS)
+  assert_param(IS_FMC_WRITE_FIFO(Init->WriteFifo));
+#endif /* FMC_BCR1_WFDIS */
+  assert_param(IS_FMC_PAGESIZE(Init->PageSize));
+
+  /* Disable NORSRAM Device */
+  __FMC_NORSRAM_DISABLE(Device, Init->NSBank);
+
+  /* Set NORSRAM device control parameters */
+  if (Init->MemoryType == FMC_MEMORY_TYPE_NOR)
+  {
+    flashaccess = FMC_NORSRAM_FLASH_ACCESS_ENABLE;
+  }
+  else
+  {
+    flashaccess = FMC_NORSRAM_FLASH_ACCESS_DISABLE;
+  }
+
+  btcr_reg = (flashaccess                   | \
+              Init->DataAddressMux          | \
+              Init->MemoryType              | \
+              Init->MemoryDataWidth         | \
+              Init->BurstAccessMode         | \
+              Init->WaitSignalPolarity      | \
+              Init->WaitSignalActive        | \
+              Init->WriteOperation          | \
+              Init->WaitSignal              | \
+              Init->ExtendedMode            | \
+              Init->AsynchronousWait        | \
+              Init->WriteBurst);
+
+#if defined(FMC_BCR1_WRAPMOD)
+  btcr_reg |= Init->WrapMode;
+#endif /* FMC_BCR1_WRAPMOD */
+#if defined(FMC_BCR1_CCLKEN)
+  btcr_reg |= Init->ContinuousClock;
+#endif /* FMC_BCR1_CCLKEN */
+#if defined(FMC_BCR1_WFDIS)
+  btcr_reg |= Init->WriteFifo;
+#endif /* FMC_BCR1_WFDIS */
+  btcr_reg |= Init->PageSize;
+
+  mask = (FMC_BCR1_MBKEN                |
+          FMC_BCR1_MUXEN                |
+          FMC_BCR1_MTYP                 |
+          FMC_BCR1_MWID                 |
+          FMC_BCR1_FACCEN               |
+          FMC_BCR1_BURSTEN              |
+          FMC_BCR1_WAITPOL              |
+          FMC_BCR1_WAITCFG              |
+          FMC_BCR1_WREN                 |
+          FMC_BCR1_WAITEN               |
+          FMC_BCR1_EXTMOD               |
+          FMC_BCR1_ASYNCWAIT            |
+          FMC_BCR1_CBURSTRW);
+
+#if defined(FMC_BCR1_WRAPMOD)
+  mask |= FMC_BCR1_WRAPMOD;
+#endif /* FMC_BCR1_WRAPMOD */
+#if defined(FMC_BCR1_CCLKEN)
+  mask |= FMC_BCR1_CCLKEN;
+#endif
+#if defined(FMC_BCR1_WFDIS)
+  mask |= FMC_BCR1_WFDIS;
+#endif /* FMC_BCR1_WFDIS */
+  mask |= FMC_BCR1_CPSIZE;
+
+  MODIFY_REG(Device->BTCR[Init->NSBank], mask, btcr_reg);
+
+#if defined(FMC_BCR1_CCLKEN)
+  /* Configure synchronous mode when Continuous clock is enabled for bank2..4 */
+  if ((Init->ContinuousClock == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC) && (Init->NSBank != FMC_NORSRAM_BANK1))
+  {
+    MODIFY_REG(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN, Init->ContinuousClock);
+  }
+#endif
+#if defined(FMC_BCR1_WFDIS)
+
+  if (Init->NSBank != FMC_NORSRAM_BANK1)
+  {
+    /* Configure Write FIFO mode when Write Fifo is enabled for bank2..4 */
+    SET_BIT(Device->BTCR[FMC_NORSRAM_BANK1], (uint32_t)(Init->WriteFifo));
+  }
+#endif /* FMC_BCR1_WFDIS */
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  DeInitialize the FMC_NORSRAM peripheral
+  * @param  Device Pointer to NORSRAM device instance
+  * @param  ExDevice Pointer to NORSRAM extended mode device instance
+  * @param  Bank NORSRAM bank number
+  * @retval HAL status
+  */
+HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device,
+                                     FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank)
+{
+  /* Check the parameters */
+  assert_param(IS_FMC_NORSRAM_DEVICE(Device));
+  assert_param(IS_FMC_NORSRAM_EXTENDED_DEVICE(ExDevice));
+  assert_param(IS_FMC_NORSRAM_BANK(Bank));
+
+  /* Disable the FMC_NORSRAM device */
+  __FMC_NORSRAM_DISABLE(Device, Bank);
+
+  /* De-initialize the FMC_NORSRAM device */
+  /* FMC_NORSRAM_BANK1 */
+  if (Bank == FMC_NORSRAM_BANK1)
+  {
+    Device->BTCR[Bank] = 0x000030DBU;
+  }
+  /* FMC_NORSRAM_BANK2, FMC_NORSRAM_BANK3 or FMC_NORSRAM_BANK4 */
+  else
+  {
+    Device->BTCR[Bank] = 0x000030D2U;
+  }
+
+  Device->BTCR[Bank + 1U] = 0x0FFFFFFFU;
+  ExDevice->BWTR[Bank]   = 0x0FFFFFFFU;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initialize the FMC_NORSRAM Timing according to the specified
+  *         parameters in the FMC_NORSRAM_TimingTypeDef
+  * @param  Device Pointer to NORSRAM device instance
+  * @param  Timing Pointer to NORSRAM Timing structure
+  * @param  Bank NORSRAM bank number
+  * @retval HAL status
+  */
+HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device,
+                                          FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank)
+{
+#if defined(FMC_BCR1_CCLKEN)
+  uint32_t tmpr;
+#endif
+
+  /* Check the parameters */
+  assert_param(IS_FMC_NORSRAM_DEVICE(Device));
+  assert_param(IS_FMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime));
+  assert_param(IS_FMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime));
+  assert_param(IS_FMC_DATASETUP_TIME(Timing->DataSetupTime));
+  assert_param(IS_FMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration));
+  assert_param(IS_FMC_CLK_DIV(Timing->CLKDivision));
+  assert_param(IS_FMC_DATA_LATENCY(Timing->DataLatency));
+  assert_param(IS_FMC_ACCESS_MODE(Timing->AccessMode));
+  assert_param(IS_FMC_NORSRAM_BANK(Bank));
+
+  /* Set FMC_NORSRAM device timing parameters */
+  MODIFY_REG(Device->BTCR[Bank + 1U], BTR_CLEAR_MASK, (Timing->AddressSetupTime                                  |
+                                                       ((Timing->AddressHoldTime)        << FMC_BTR1_ADDHLD_Pos)  |
+                                                       ((Timing->DataSetupTime)          << FMC_BTR1_DATAST_Pos)  |
+                                                       ((Timing->BusTurnAroundDuration)  << FMC_BTR1_BUSTURN_Pos) |
+                                                       (((Timing->CLKDivision) - 1U)     << FMC_BTR1_CLKDIV_Pos)  |
+                                                       (((Timing->DataLatency) - 2U)     << FMC_BTR1_DATLAT_Pos)  |
+                                                       (Timing->AccessMode)));
+
+#if defined(FMC_BCR1_CCLKEN)
+  /* Configure Clock division value (in NORSRAM bank 1) when continuous clock is enabled */
+  if (HAL_IS_BIT_SET(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN))
+  {
+    tmpr = (uint32_t)(Device->BTCR[FMC_NORSRAM_BANK1 + 1U] & ~((0x0FU) << FMC_BTR1_CLKDIV_Pos));
+    tmpr |= (uint32_t)(((Timing->CLKDivision) - 1U) << FMC_BTR1_CLKDIV_Pos);
+    MODIFY_REG(Device->BTCR[FMC_NORSRAM_BANK1 + 1U], FMC_BTR1_CLKDIV, tmpr);
+  }
+
+#endif
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initialize the FMC_NORSRAM Extended mode Timing according to the specified
+  *         parameters in the FMC_NORSRAM_TimingTypeDef
+  * @param  Device Pointer to NORSRAM device instance
+  * @param  Timing Pointer to NORSRAM Timing structure
+  * @param  Bank NORSRAM bank number
+  * @param  ExtendedMode FMC Extended Mode
+  *          This parameter can be one of the following values:
+  *            @arg FMC_EXTENDED_MODE_DISABLE
+  *            @arg FMC_EXTENDED_MODE_ENABLE
+  * @retval HAL status
+  */
+HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device,
+                                                   FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank,
+                                                   uint32_t ExtendedMode)
+{
+  /* Check the parameters */
+  assert_param(IS_FMC_EXTENDED_MODE(ExtendedMode));
+
+  /* Set NORSRAM device timing register for write configuration, if extended mode is used */
+  if (ExtendedMode == FMC_EXTENDED_MODE_ENABLE)
+  {
+    /* Check the parameters */
+    assert_param(IS_FMC_NORSRAM_EXTENDED_DEVICE(Device));
+    assert_param(IS_FMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime));
+    assert_param(IS_FMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime));
+    assert_param(IS_FMC_DATASETUP_TIME(Timing->DataSetupTime));
+    assert_param(IS_FMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration));
+    assert_param(IS_FMC_ACCESS_MODE(Timing->AccessMode));
+    assert_param(IS_FMC_NORSRAM_BANK(Bank));
+
+    /* Set NORSRAM device timing register for write configuration, if extended mode is used */
+    MODIFY_REG(Device->BWTR[Bank], BWTR_CLEAR_MASK, (Timing->AddressSetupTime                                    |
+                                                     ((Timing->AddressHoldTime)        << FMC_BWTR1_ADDHLD_Pos)  |
+                                                     ((Timing->DataSetupTime)          << FMC_BWTR1_DATAST_Pos)  |
+                                                     Timing->AccessMode                                          |
+                                                     ((Timing->BusTurnAroundDuration)  << FMC_BWTR1_BUSTURN_Pos)));
+  }
+  else
+  {
+    Device->BWTR[Bank] = 0x0FFFFFFFU;
+  }
+
+  return HAL_OK;
+}
+/**
+  * @}
+  */
+
+/** @addtogroup FMC_LL_NORSRAM_Private_Functions_Group2
+  *  @brief   management functions
+  *
+@verbatim
+  ==============================================================================
+                      ##### FMC_NORSRAM Control functions #####
+  ==============================================================================
+  [..]
+    This subsection provides a set of functions allowing to control dynamically
+    the FMC NORSRAM interface.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enables dynamically FMC_NORSRAM write operation.
+  * @param  Device Pointer to NORSRAM device instance
+  * @param  Bank NORSRAM bank number
+  * @retval HAL status
+  */
+HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank)
+{
+  /* Check the parameters */
+  assert_param(IS_FMC_NORSRAM_DEVICE(Device));
+  assert_param(IS_FMC_NORSRAM_BANK(Bank));
+
+  /* Enable write operation */
+  SET_BIT(Device->BTCR[Bank], FMC_WRITE_OPERATION_ENABLE);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Disables dynamically FMC_NORSRAM write operation.
+  * @param  Device Pointer to NORSRAM device instance
+  * @param  Bank NORSRAM bank number
+  * @retval HAL status
+  */
+HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank)
+{
+  /* Check the parameters */
+  assert_param(IS_FMC_NORSRAM_DEVICE(Device));
+  assert_param(IS_FMC_NORSRAM_BANK(Bank));
+
+  /* Disable write operation */
+  CLEAR_BIT(Device->BTCR[Bank], FMC_WRITE_OPERATION_ENABLE);
+
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+#endif /* FMC_Bank1 */
+
+#if defined(FMC_Bank3) || defined(FMC_Bank2_3)
+
+/** @defgroup FMC_LL_Exported_Functions_NAND FMC Low Layer NAND Exported Functions
+  * @brief    NAND Controller functions
+  *
+  @verbatim
+  ==============================================================================
+                    ##### How to use NAND device driver #####
+  ==============================================================================
+  [..]
+    This driver contains a set of APIs to interface with the FMC NAND banks in order
+    to run the NAND external devices.
+
+    (+) FMC NAND bank reset using the function FMC_NAND_DeInit()
+    (+) FMC NAND bank control configuration using the function FMC_NAND_Init()
+    (+) FMC NAND bank common space timing configuration using the function
+        FMC_NAND_CommonSpace_Timing_Init()
+    (+) FMC NAND bank attribute space timing configuration using the function
+        FMC_NAND_AttributeSpace_Timing_Init()
+    (+) FMC NAND bank enable/disable ECC correction feature using the functions
+        FMC_NAND_ECC_Enable()/FMC_NAND_ECC_Disable()
+    (+) FMC NAND bank get ECC correction code using the function FMC_NAND_GetECC()
+
+@endverbatim
+  * @{
+  */
+
+/** @defgroup FMC_LL_NAND_Exported_Functions_Group1 Initialization and de-initialization functions
+  *  @brief    Initialization and Configuration functions
+  *
+@verbatim
+  ==============================================================================
+              ##### Initialization and de_initialization functions #####
+  ==============================================================================
+  [..]
+    This section provides functions allowing to:
+    (+) Initialize and configure the FMC NAND interface
+    (+) De-initialize the FMC NAND interface
+    (+) Configure the FMC clock and associated GPIOs
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initializes the FMC_NAND device according to the specified
+  *         control parameters in the FMC_NAND_HandleTypeDef
+  * @param  Device Pointer to NAND device instance
+  * @param  Init Pointer to NAND Initialization structure
+  * @retval HAL status
+  */
+HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef *Init)
+{
+  /* Check the parameters */
+  assert_param(IS_FMC_NAND_DEVICE(Device));
+  assert_param(IS_FMC_NAND_BANK(Init->NandBank));
+  assert_param(IS_FMC_WAIT_FEATURE(Init->Waitfeature));
+  assert_param(IS_FMC_NAND_MEMORY_WIDTH(Init->MemoryDataWidth));
+  assert_param(IS_FMC_ECC_STATE(Init->EccComputation));
+  assert_param(IS_FMC_ECCPAGE_SIZE(Init->ECCPageSize));
+  assert_param(IS_FMC_TCLR_TIME(Init->TCLRSetupTime));
+  assert_param(IS_FMC_TAR_TIME(Init->TARSetupTime));
+
+#if defined(FMC_Bank2_3)
+  /* Set NAND device control parameters */
+  if (Init->NandBank == FMC_NAND_BANK2)
+  {
+    /* NAND bank 2 registers configuration */
+    MODIFY_REG(Device->PCR2, PCR_CLEAR_MASK, (Init->Waitfeature                                      |
+                                              FMC_PCR_MEMORY_TYPE_NAND                               |
+                                              Init->MemoryDataWidth                                  |
+                                              Init->EccComputation                                   |
+                                              Init->ECCPageSize                                      |
+                                              ((Init->TCLRSetupTime) << FMC_PCR2_TCLR_Pos)  |
+                                              ((Init->TARSetupTime)  << FMC_PCR2_TAR_Pos)));
+  }
+  else
+  {
+    /* NAND bank 3 registers configuration */
+    MODIFY_REG(Device->PCR3, PCR_CLEAR_MASK, (Init->Waitfeature                                      |
+                                              FMC_PCR_MEMORY_TYPE_NAND                               |
+                                              Init->MemoryDataWidth                                  |
+                                              Init->EccComputation                                   |
+                                              Init->ECCPageSize                                      |
+                                              ((Init->TCLRSetupTime) << FMC_PCR2_TCLR_Pos)  |
+                                              ((Init->TARSetupTime)  << FMC_PCR2_TAR_Pos)));
+  }
+#else
+  /* NAND bank 3 registers configuration */
+  MODIFY_REG(Device->PCR, PCR_CLEAR_MASK, (Init->Waitfeature                            |
+                                           FMC_PCR_MEMORY_TYPE_NAND                     |
+                                           Init->MemoryDataWidth                        |
+                                           Init->EccComputation                         |
+                                           Init->ECCPageSize                            |
+                                           ((Init->TCLRSetupTime) << FMC_PCR_TCLR_Pos)  |
+                                           ((Init->TARSetupTime)  << FMC_PCR_TAR_Pos)));
+#endif
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the FMC_NAND Common space Timing according to the specified
+  *         parameters in the FMC_NAND_PCC_TimingTypeDef
+  * @param  Device Pointer to NAND device instance
+  * @param  Timing Pointer to NAND timing structure
+  * @param  Bank NAND bank number
+  * @retval HAL status
+  */
+HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device,
+                                                   FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
+{
+  /* Check the parameters */
+  assert_param(IS_FMC_NAND_DEVICE(Device));
+  assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));
+  assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));
+  assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));
+  assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
+  assert_param(IS_FMC_NAND_BANK(Bank));
+
+#if defined(FMC_Bank2_3)
+  /* Set FMC_NAND device timing parameters */
+  if (Bank == FMC_NAND_BANK2)
+  {
+    /* NAND bank 2 registers configuration */
+    MODIFY_REG(Device->PMEM2, PMEM_CLEAR_MASK, (Timing->SetupTime                                             |
+                                                ((Timing->WaitSetupTime) << FMC_PMEM2_MEMWAIT2_Pos) |
+                                                ((Timing->HoldSetupTime) << FMC_PMEM2_MEMHOLD2_Pos) |
+                                                ((Timing->HiZSetupTime)  << FMC_PMEM2_MEMHIZ2_Pos)));
+  }
+  else
+  {
+    /* NAND bank 3 registers configuration */
+    MODIFY_REG(Device->PMEM3, PMEM_CLEAR_MASK, (Timing->SetupTime                                             |
+                                                ((Timing->WaitSetupTime) << FMC_PMEM2_MEMWAIT2_Pos) |
+                                                ((Timing->HoldSetupTime) << FMC_PMEM2_MEMHOLD2_Pos) |
+                                                ((Timing->HiZSetupTime)  << FMC_PMEM2_MEMHIZ2_Pos)));
+  }
+#else
+  /* Prevent unused argument(s) compilation warning if no assert_param check */
+  UNUSED(Bank);
+
+  /* NAND bank 3 registers configuration */
+  MODIFY_REG(Device->PMEM, PMEM_CLEAR_MASK, (Timing->SetupTime                                 |
+                                             ((Timing->WaitSetupTime) << FMC_PMEM_MEMWAIT2_Pos) |
+                                             ((Timing->HoldSetupTime) << FMC_PMEM_MEMHOLD2_Pos) |
+                                             ((Timing->HiZSetupTime)  << FMC_PMEM_MEMHIZ2_Pos)));
+#endif
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the FMC_NAND Attribute space Timing according to the specified
+  *         parameters in the FMC_NAND_PCC_TimingTypeDef
+  * @param  Device Pointer to NAND device instance
+  * @param  Timing Pointer to NAND timing structure
+  * @param  Bank NAND bank number
+  * @retval HAL status
+  */
+HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device,
+                                                      FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
+{
+  /* Check the parameters */
+  assert_param(IS_FMC_NAND_DEVICE(Device));
+  assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));
+  assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));
+  assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));
+  assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
+  assert_param(IS_FMC_NAND_BANK(Bank));
+
+#if defined(FMC_Bank2_3)
+  /* Set FMC_NAND device timing parameters */
+  if (Bank == FMC_NAND_BANK2)
+  {
+    /* NAND bank 2 registers configuration */
+    MODIFY_REG(Device->PATT2, PATT_CLEAR_MASK, (Timing->SetupTime                                             |
+                                                ((Timing->WaitSetupTime) << FMC_PATT2_ATTWAIT2_Pos) |
+                                                ((Timing->HoldSetupTime) << FMC_PATT2_ATTHOLD2_Pos) |
+                                                ((Timing->HiZSetupTime)  << FMC_PATT2_ATTHIZ2_Pos)));
+  }
+  else
+  {
+    /* NAND bank 3 registers configuration */
+    MODIFY_REG(Device->PATT3, PATT_CLEAR_MASK, (Timing->SetupTime                                             |
+                                                ((Timing->WaitSetupTime) << FMC_PATT2_ATTWAIT2_Pos) |
+                                                ((Timing->HoldSetupTime) << FMC_PATT2_ATTHOLD2_Pos) |
+                                                ((Timing->HiZSetupTime)  << FMC_PATT2_ATTHIZ2_Pos)));
+  }
+#else
+  /* Prevent unused argument(s) compilation warning if no assert_param check */
+  UNUSED(Bank);
+
+  /* NAND bank 3 registers configuration */
+  MODIFY_REG(Device->PATT, PATT_CLEAR_MASK, (Timing->SetupTime                                 |
+                                             ((Timing->WaitSetupTime) << FMC_PATT_ATTWAIT2_Pos) |
+                                             ((Timing->HoldSetupTime) << FMC_PATT_ATTHOLD2_Pos) |
+                                             ((Timing->HiZSetupTime)  << FMC_PATT_ATTHIZ2_Pos)));
+#endif
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  DeInitializes the FMC_NAND device
+  * @param  Device Pointer to NAND device instance
+  * @param  Bank NAND bank number
+  * @retval HAL status
+  */
+HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank)
+{
+  /* Check the parameters */
+  assert_param(IS_FMC_NAND_DEVICE(Device));
+  assert_param(IS_FMC_NAND_BANK(Bank));
+
+  /* Disable the NAND Bank */
+  __FMC_NAND_DISABLE(Device, Bank);
+
+  /* De-initialize the NAND Bank */
+#if defined(FMC_Bank2_3)
+  if (Bank == FMC_NAND_BANK2)
+  {
+    /* Set the FMC_NAND_BANK2 registers to their reset values */
+    WRITE_REG(Device->PCR2,  0x00000018U);
+    WRITE_REG(Device->SR2,   0x00000040U);
+    WRITE_REG(Device->PMEM2, 0xFCFCFCFCU);
+    WRITE_REG(Device->PATT2, 0xFCFCFCFCU);
+  }
+  /* FMC_Bank3_NAND */
+  else
+  {
+    /* Set the FMC_NAND_BANK3 registers to their reset values */
+    WRITE_REG(Device->PCR3,  0x00000018U);
+    WRITE_REG(Device->SR3,   0x00000040U);
+    WRITE_REG(Device->PMEM3, 0xFCFCFCFCU);
+    WRITE_REG(Device->PATT3, 0xFCFCFCFCU);
+  }
+#else
+  /* Prevent unused argument(s) compilation warning if no assert_param check */
+  UNUSED(Bank);
+
+  /* Set the FMC_NAND_BANK3 registers to their reset values */
+  WRITE_REG(Device->PCR,  0x00000018U);
+  WRITE_REG(Device->SR,   0x00000040U);
+  WRITE_REG(Device->PMEM, 0xFCFCFCFCU);
+  WRITE_REG(Device->PATT, 0xFCFCFCFCU);
+#endif
+
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_FMC_NAND_Group2 Peripheral Control functions
+  *  @brief   management functions
+  *
+@verbatim
+  ==============================================================================
+                       ##### FMC_NAND Control functions #####
+  ==============================================================================
+  [..]
+    This subsection provides a set of functions allowing to control dynamically
+    the FMC NAND interface.
+
+@endverbatim
+  * @{
+  */
+
+
+/**
+  * @brief  Enables dynamically FMC_NAND ECC feature.
+  * @param  Device Pointer to NAND device instance
+  * @param  Bank NAND bank number
+  * @retval HAL status
+  */
+HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank)
+{
+  /* Check the parameters */
+  assert_param(IS_FMC_NAND_DEVICE(Device));
+  assert_param(IS_FMC_NAND_BANK(Bank));
+
+  /* Enable ECC feature */
+#if defined(FMC_Bank2_3)
+  if (Bank == FMC_NAND_BANK2)
+  {
+    SET_BIT(Device->PCR2, FMC_PCR2_ECCEN);
+  }
+  else
+  {
+    SET_BIT(Device->PCR3, FMC_PCR2_ECCEN);
+  }
+#else
+  /* Prevent unused argument(s) compilation warning if no assert_param check */
+  UNUSED(Bank);
+
+  SET_BIT(Device->PCR, FMC_PCR_ECCEN);
+#endif
+
+  return HAL_OK;
+}
+
+
+/**
+  * @brief  Disables dynamically FMC_NAND ECC feature.
+  * @param  Device Pointer to NAND device instance
+  * @param  Bank NAND bank number
+  * @retval HAL status
+  */
+HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank)
+{
+  /* Check the parameters */
+  assert_param(IS_FMC_NAND_DEVICE(Device));
+  assert_param(IS_FMC_NAND_BANK(Bank));
+
+  /* Disable ECC feature */
+#if defined(FMC_Bank2_3)
+  if (Bank == FMC_NAND_BANK2)
+  {
+    CLEAR_BIT(Device->PCR2, FMC_PCR2_ECCEN);
+  }
+  else
+  {
+    CLEAR_BIT(Device->PCR3, FMC_PCR2_ECCEN);
+  }
+#else
+  /* Prevent unused argument(s) compilation warning if no assert_param check */
+  UNUSED(Bank);
+
+  CLEAR_BIT(Device->PCR, FMC_PCR_ECCEN);
+#endif
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Disables dynamically FMC_NAND ECC feature.
+  * @param  Device Pointer to NAND device instance
+  * @param  ECCval Pointer to ECC value
+  * @param  Bank NAND bank number
+  * @param  Timeout Timeout wait value
+  * @retval HAL status
+  */
+HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank,
+                                  uint32_t Timeout)
+{
+  uint32_t tickstart;
+
+  /* Check the parameters */
+  assert_param(IS_FMC_NAND_DEVICE(Device));
+  assert_param(IS_FMC_NAND_BANK(Bank));
+
+  /* Get tick */
+  tickstart = HAL_GetTick();
+
+  /* Wait until FIFO is empty */
+  while (__FMC_NAND_GET_FLAG(Device, Bank, FMC_FLAG_FEMPT) == RESET)
+  {
+    /* Check for the Timeout */
+    if (Timeout != HAL_MAX_DELAY)
+    {
+      if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
+      {
+        return HAL_TIMEOUT;
+      }
+    }
+  }
+
+#if defined(FMC_Bank2_3)
+  if (Bank == FMC_NAND_BANK2)
+  {
+    /* Get the ECCR2 register value */
+    *ECCval = (uint32_t)Device->ECCR2;
+  }
+  else
+  {
+    /* Get the ECCR3 register value */
+    *ECCval = (uint32_t)Device->ECCR3;
+  }
+#else
+  /* Prevent unused argument(s) compilation warning if no assert_param check */
+  UNUSED(Bank);
+
+  /* Get the ECCR register value */
+  *ECCval = (uint32_t)Device->ECCR;
+#endif
+
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+#endif /* FMC_Bank3) || defined(FMC_Bank2_3 */
+
+#if defined(FMC_Bank4)
+
+/** @addtogroup FMC_LL_PCCARD
+  * @brief    PCCARD Controller functions
+  *
+  @verbatim
+  ==============================================================================
+                    ##### How to use PCCARD device driver #####
+  ==============================================================================
+  [..]
+    This driver contains a set of APIs to interface with the FMC PCCARD bank in order
+    to run the PCCARD/compact flash external devices.
+
+    (+) FMC PCCARD bank reset using the function FMC_PCCARD_DeInit()
+    (+) FMC PCCARD bank control configuration using the function FMC_PCCARD_Init()
+    (+) FMC PCCARD bank common space timing configuration using the function
+        FMC_PCCARD_CommonSpace_Timing_Init()
+    (+) FMC PCCARD bank attribute space timing configuration using the function
+        FMC_PCCARD_AttributeSpace_Timing_Init()
+    (+) FMC PCCARD bank IO space timing configuration using the function
+        FMC_PCCARD_IOSpace_Timing_Init()
+@endverbatim
+  * @{
+  */
+
+/** @addtogroup FMC_LL_PCCARD_Private_Functions_Group1
+  *  @brief    Initialization and Configuration functions
+  *
+@verbatim
+  ==============================================================================
+              ##### Initialization and de_initialization functions #####
+  ==============================================================================
+  [..]
+    This section provides functions allowing to:
+    (+) Initialize and configure the FMC PCCARD interface
+    (+) De-initialize the FMC PCCARD interface
+    (+) Configure the FMC clock and associated GPIOs
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initializes the FMC_PCCARD device according to the specified
+  *         control parameters in the FMC_PCCARD_HandleTypeDef
+  * @param  Device Pointer to PCCARD device instance
+  * @param  Init Pointer to PCCARD Initialization structure
+  * @retval HAL status
+  */
+HAL_StatusTypeDef FMC_PCCARD_Init(FMC_PCCARD_TypeDef *Device, FMC_PCCARD_InitTypeDef *Init)
+{
+  /* Check the parameters */
+  assert_param(IS_FMC_PCCARD_DEVICE(Device));
+#if defined(FMC_Bank3) || defined(FMC_Bank2_3)
+  assert_param(IS_FMC_WAIT_FEATURE(Init->Waitfeature));
+  assert_param(IS_FMC_TCLR_TIME(Init->TCLRSetupTime));
+  assert_param(IS_FMC_TAR_TIME(Init->TARSetupTime));
+#endif /* FMC_Bank3) || defined(FMC_Bank2_3 */
+
+  /* Set FMC_PCCARD device control parameters */
+  MODIFY_REG(Device->PCR4,
+             (FMC_PCR4_PTYP                                          |
+              FMC_PCR4_PWAITEN                                       |
+              FMC_PCR4_PWID                                          |
+              FMC_PCR4_TCLR                                          |
+              FMC_PCR4_TAR),
+             (FMC_PCR_MEMORY_TYPE_PCCARD                             |
+              Init->Waitfeature                                      |
+              FMC_NAND_PCC_MEM_BUS_WIDTH_16                          |
+              (Init->TCLRSetupTime << FMC_PCR4_TCLR_Pos)   |
+              (Init->TARSetupTime  << FMC_PCR4_TAR_Pos)));
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the FMC_PCCARD Common space Timing according to the specified
+  *         parameters in the FMC_NAND_PCC_TimingTypeDef
+  * @param  Device Pointer to PCCARD device instance
+  * @param  Timing Pointer to PCCARD timing structure
+  * @retval HAL status
+  */
+HAL_StatusTypeDef FMC_PCCARD_CommonSpace_Timing_Init(FMC_PCCARD_TypeDef *Device,
+                                                              FMC_NAND_PCC_TimingTypeDef *Timing)
+{
+  /* Check the parameters */
+  assert_param(IS_FMC_PCCARD_DEVICE(Device));
+#if defined(FMC_Bank3) || defined(FMC_Bank2_3)
+  assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));
+  assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));
+  assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));
+  assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
+#endif /* FMC_Bank3) || defined(FMC_Bank2_3 */
+
+  /* Set PCCARD timing parameters */
+  MODIFY_REG(Device->PMEM4, PMEM4_CLEAR_MASK,
+             (Timing->SetupTime                                              |
+              ((Timing->WaitSetupTime) << FMC_PMEM4_MEMWAIT4_Pos)  |
+              ((Timing->HoldSetupTime) << FMC_PMEM4_MEMHOLD4_Pos)  |
+              ((Timing->HiZSetupTime)  << FMC_PMEM4_MEMHIZ4_Pos)));
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the FMC_PCCARD Attribute space Timing according to the specified
+  *         parameters in the FMC_NAND_PCC_TimingTypeDef
+  * @param  Device Pointer to PCCARD device instance
+  * @param  Timing Pointer to PCCARD timing structure
+  * @retval HAL status
+  */
+HAL_StatusTypeDef FMC_PCCARD_AttributeSpace_Timing_Init(FMC_PCCARD_TypeDef *Device,
+                                                                 FMC_NAND_PCC_TimingTypeDef *Timing)
+{
+  /* Check the parameters */
+  assert_param(IS_FMC_PCCARD_DEVICE(Device));
+#if defined(FMC_Bank3) || defined(FMC_Bank2_3)
+  assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));
+  assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));
+  assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));
+  assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
+#endif /* FMC_Bank3) || defined(FMC_Bank2_3 */
+
+  /* Set PCCARD timing parameters */
+  MODIFY_REG(Device->PATT4, PATT4_CLEAR_MASK,
+             (Timing->SetupTime                                              |
+              ((Timing->WaitSetupTime) << FMC_PATT4_ATTWAIT4_Pos)  |
+              ((Timing->HoldSetupTime) << FMC_PATT4_ATTHOLD4_Pos)  |
+              ((Timing->HiZSetupTime)  << FMC_PATT4_ATTHIZ4_Pos)));
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the FMC_PCCARD IO space Timing according to the specified
+  *         parameters in the FMC_NAND_PCC_TimingTypeDef
+  * @param  Device Pointer to PCCARD device instance
+  * @param  Timing Pointer to PCCARD timing structure
+  * @retval HAL status
+  */
+HAL_StatusTypeDef FMC_PCCARD_IOSpace_Timing_Init(FMC_PCCARD_TypeDef *Device,
+                                                          FMC_NAND_PCC_TimingTypeDef *Timing)
+{
+  /* Check the parameters */
+  assert_param(IS_FMC_PCCARD_DEVICE(Device));
+#if defined(FMC_Bank3) || defined(FMC_Bank2_3)
+  assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));
+  assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));
+  assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));
+  assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
+#endif /* FMC_Bank3) || defined(FMC_Bank2_3 */
+
+  /* Set FMC_PCCARD device timing parameters */
+  MODIFY_REG(Device->PIO4, PIO4_CLEAR_MASK,
+             (Timing->SetupTime                                           |
+              (Timing->WaitSetupTime   << FMC_PIO4_IOWAIT4_Pos) |
+              (Timing->HoldSetupTime   << FMC_PIO4_IOHOLD4_Pos) |
+              (Timing->HiZSetupTime    << FMC_PIO4_IOHIZ4_Pos)));
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  DeInitializes the FMC_PCCARD device
+  * @param  Device Pointer to PCCARD device instance
+  * @retval HAL status
+  */
+HAL_StatusTypeDef FMC_PCCARD_DeInit(FMC_PCCARD_TypeDef *Device)
+{
+  /* Check the parameters */
+  assert_param(IS_FMC_PCCARD_DEVICE(Device));
+
+  /* Disable the FMC_PCCARD device */
+  __FMC_PCCARD_DISABLE(Device);
+
+  /* De-initialize the FMC_PCCARD device */
+  Device->PCR4    = 0x00000018U;
+  Device->SR4     = 0x00000040U;
+  Device->PMEM4   = 0xFCFCFCFCU;
+  Device->PATT4   = 0xFCFCFCFCU;
+  Device->PIO4    = 0xFCFCFCFCU;
+
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+#endif /* FMC_Bank4 */
+
+#if defined(FMC_Bank5_6)
+
+/** @defgroup FMC_LL_SDRAM
+  * @brief    SDRAM Controller functions
+  *
+  @verbatim
+  ==============================================================================
+                     ##### How to use SDRAM device driver #####
+  ==============================================================================
+  [..]
+    This driver contains a set of APIs to interface with the FMC SDRAM banks in order
+    to run the SDRAM external devices.
+
+    (+) FMC SDRAM bank reset using the function FMC_SDRAM_DeInit()
+    (+) FMC SDRAM bank control configuration using the function FMC_SDRAM_Init()
+    (+) FMC SDRAM bank timing configuration using the function FMC_SDRAM_Timing_Init()
+    (+) FMC SDRAM bank enable/disable write operation using the functions
+        FMC_SDRAM_WriteOperation_Enable()/FMC_SDRAM_WriteOperation_Disable()
+    (+) FMC SDRAM bank send command using the function FMC_SDRAM_SendCommand()
+
+@endverbatim
+  * @{
+  */
+
+/** @addtogroup FMC_LL_SDRAM_Private_Functions_Group1
+  *  @brief    Initialization and Configuration functions
+  *
+@verbatim
+  ==============================================================================
+              ##### Initialization and de_initialization functions #####
+  ==============================================================================
+  [..]
+    This section provides functions allowing to:
+    (+) Initialize and configure the FMC SDRAM interface
+    (+) De-initialize the FMC SDRAM interface
+    (+) Configure the FMC clock and associated GPIOs
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initializes the FMC_SDRAM device according to the specified
+  *         control parameters in the FMC_SDRAM_InitTypeDef
+  * @param  Device Pointer to SDRAM device instance
+  * @param  Init Pointer to SDRAM Initialization structure
+  * @retval HAL status
+  */
+HAL_StatusTypeDef FMC_SDRAM_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_InitTypeDef *Init)
+{
+  /* Check the parameters */
+  assert_param(IS_FMC_SDRAM_DEVICE(Device));
+  assert_param(IS_FMC_SDRAM_BANK(Init->SDBank));
+  assert_param(IS_FMC_COLUMNBITS_NUMBER(Init->ColumnBitsNumber));
+  assert_param(IS_FMC_ROWBITS_NUMBER(Init->RowBitsNumber));
+  assert_param(IS_FMC_SDMEMORY_WIDTH(Init->MemoryDataWidth));
+  assert_param(IS_FMC_INTERNALBANK_NUMBER(Init->InternalBankNumber));
+  assert_param(IS_FMC_CAS_LATENCY(Init->CASLatency));
+  assert_param(IS_FMC_WRITE_PROTECTION(Init->WriteProtection));
+  assert_param(IS_FMC_SDCLOCK_PERIOD(Init->SDClockPeriod));
+  assert_param(IS_FMC_READ_BURST(Init->ReadBurst));
+  assert_param(IS_FMC_READPIPE_DELAY(Init->ReadPipeDelay));
+
+  /* Set SDRAM bank configuration parameters */
+  if (Init->SDBank == FMC_SDRAM_BANK1)
+  {
+    MODIFY_REG(Device->SDCR[FMC_SDRAM_BANK1],
+               SDCR_CLEAR_MASK,
+               (Init->ColumnBitsNumber   |
+                Init->RowBitsNumber      |
+                Init->MemoryDataWidth    |
+                Init->InternalBankNumber |
+                Init->CASLatency         |
+                Init->WriteProtection    |
+                Init->SDClockPeriod      |
+                Init->ReadBurst          |
+                Init->ReadPipeDelay));
+  }
+  else /* FMC_Bank2_SDRAM */
+  {
+    MODIFY_REG(Device->SDCR[FMC_SDRAM_BANK1],
+               FMC_SDCR1_SDCLK           |
+               FMC_SDCR1_RBURST          |
+               FMC_SDCR1_RPIPE,
+               (Init->SDClockPeriod      |
+                Init->ReadBurst          |
+                Init->ReadPipeDelay));
+
+    MODIFY_REG(Device->SDCR[FMC_SDRAM_BANK2],
+               SDCR_CLEAR_MASK,
+               (Init->ColumnBitsNumber   |
+                Init->RowBitsNumber      |
+                Init->MemoryDataWidth    |
+                Init->InternalBankNumber |
+                Init->CASLatency         |
+                Init->WriteProtection));
+  }
+
+  return HAL_OK;
+}
+
+
+/**
+  * @brief  Initializes the FMC_SDRAM device timing according to the specified
+  *         parameters in the FMC_SDRAM_TimingTypeDef
+  * @param  Device Pointer to SDRAM device instance
+  * @param  Timing Pointer to SDRAM Timing structure
+  * @param  Bank SDRAM bank number
+  * @retval HAL status
+  */
+HAL_StatusTypeDef FMC_SDRAM_Timing_Init(FMC_SDRAM_TypeDef *Device,
+                                        FMC_SDRAM_TimingTypeDef *Timing, uint32_t Bank)
+{
+  /* Check the parameters */
+  assert_param(IS_FMC_SDRAM_DEVICE(Device));
+  assert_param(IS_FMC_LOADTOACTIVE_DELAY(Timing->LoadToActiveDelay));
+  assert_param(IS_FMC_EXITSELFREFRESH_DELAY(Timing->ExitSelfRefreshDelay));
+  assert_param(IS_FMC_SELFREFRESH_TIME(Timing->SelfRefreshTime));
+  assert_param(IS_FMC_ROWCYCLE_DELAY(Timing->RowCycleDelay));
+  assert_param(IS_FMC_WRITE_RECOVERY_TIME(Timing->WriteRecoveryTime));
+  assert_param(IS_FMC_RP_DELAY(Timing->RPDelay));
+  assert_param(IS_FMC_RCD_DELAY(Timing->RCDDelay));
+  assert_param(IS_FMC_SDRAM_BANK(Bank));
+
+  /* Set SDRAM device timing parameters */
+  if (Bank == FMC_SDRAM_BANK1)
+  {
+    MODIFY_REG(Device->SDTR[FMC_SDRAM_BANK1],
+               SDTR_CLEAR_MASK,
+               (((Timing->LoadToActiveDelay) - 1U)                                      |
+                (((Timing->ExitSelfRefreshDelay) - 1U) << FMC_SDTR1_TXSR_Pos) |
+                (((Timing->SelfRefreshTime) - 1U)      << FMC_SDTR1_TRAS_Pos) |
+                (((Timing->RowCycleDelay) - 1U)        << FMC_SDTR1_TRC_Pos)  |
+                (((Timing->WriteRecoveryTime) - 1U)    << FMC_SDTR1_TWR_Pos)  |
+                (((Timing->RPDelay) - 1U)              << FMC_SDTR1_TRP_Pos)  |
+                (((Timing->RCDDelay) - 1U)             << FMC_SDTR1_TRCD_Pos)));
+  }
+  else /* FMC_Bank2_SDRAM */
+  {
+    MODIFY_REG(Device->SDTR[FMC_SDRAM_BANK1],
+               FMC_SDTR1_TRC |
+               FMC_SDTR1_TRP,
+               (((Timing->RowCycleDelay) - 1U)         << FMC_SDTR1_TRC_Pos)  |
+               (((Timing->RPDelay) - 1U)               << FMC_SDTR1_TRP_Pos));
+
+    MODIFY_REG(Device->SDTR[FMC_SDRAM_BANK2],
+               SDTR_CLEAR_MASK,
+               (((Timing->LoadToActiveDelay) - 1U)                                      |
+                (((Timing->ExitSelfRefreshDelay) - 1U) << FMC_SDTR1_TXSR_Pos) |
+                (((Timing->SelfRefreshTime) - 1U)      << FMC_SDTR1_TRAS_Pos) |
+                (((Timing->WriteRecoveryTime) - 1U)    << FMC_SDTR1_TWR_Pos)  |
+                (((Timing->RCDDelay) - 1U)             << FMC_SDTR1_TRCD_Pos)));
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  DeInitializes the FMC_SDRAM peripheral
+  * @param  Device Pointer to SDRAM device instance
+  * @retval HAL status
+  */
+HAL_StatusTypeDef FMC_SDRAM_DeInit(FMC_SDRAM_TypeDef *Device, uint32_t Bank)
+{
+  /* Check the parameters */
+  assert_param(IS_FMC_SDRAM_DEVICE(Device));
+  assert_param(IS_FMC_SDRAM_BANK(Bank));
+
+  /* De-initialize the SDRAM device */
+  Device->SDCR[Bank] = 0x000002D0U;
+  Device->SDTR[Bank] = 0x0FFFFFFFU;
+  Device->SDCMR      = 0x00000000U;
+  Device->SDRTR      = 0x00000000U;
+  Device->SDSR       = 0x00000000U;
+
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/** @addtogroup FMC_LL_SDRAMPrivate_Functions_Group2
+  *  @brief   management functions
+  *
+@verbatim
+  ==============================================================================
+                      ##### FMC_SDRAM Control functions #####
+  ==============================================================================
+  [..]
+    This subsection provides a set of functions allowing to control dynamically
+    the FMC SDRAM interface.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enables dynamically FMC_SDRAM write protection.
+  * @param  Device Pointer to SDRAM device instance
+  * @param  Bank SDRAM bank number
+  * @retval HAL status
+  */
+HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Enable(FMC_SDRAM_TypeDef *Device, uint32_t Bank)
+{
+  /* Check the parameters */
+  assert_param(IS_FMC_SDRAM_DEVICE(Device));
+  assert_param(IS_FMC_SDRAM_BANK(Bank));
+
+  /* Enable write protection */
+  SET_BIT(Device->SDCR[Bank], FMC_SDRAM_WRITE_PROTECTION_ENABLE);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Disables dynamically FMC_SDRAM write protection.
+  * @param  hsdram FMC_SDRAM handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Disable(FMC_SDRAM_TypeDef *Device, uint32_t Bank)
+{
+  /* Check the parameters */
+  assert_param(IS_FMC_SDRAM_DEVICE(Device));
+  assert_param(IS_FMC_SDRAM_BANK(Bank));
+
+  /* Disable write protection */
+  CLEAR_BIT(Device->SDCR[Bank], FMC_SDRAM_WRITE_PROTECTION_ENABLE);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Send Command to the FMC SDRAM bank
+  * @param  Device Pointer to SDRAM device instance
+  * @param  Command Pointer to SDRAM command structure
+  * @param  Timing Pointer to SDRAM Timing structure
+  * @param  Timeout Timeout wait value
+  * @retval HAL state
+  */
+HAL_StatusTypeDef FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef *Device,
+                                        FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout)
+{
+  uint32_t tickstart = 0U;
+  /* Check the parameters */
+  assert_param(IS_FMC_SDRAM_DEVICE(Device));
+  assert_param(IS_FMC_COMMAND_MODE(Command->CommandMode));
+  assert_param(IS_FMC_COMMAND_TARGET(Command->CommandTarget));
+  assert_param(IS_FMC_AUTOREFRESH_NUMBER(Command->AutoRefreshNumber));
+  assert_param(IS_FMC_MODE_REGISTER(Command->ModeRegisterDefinition));
+
+  /* Set command register */
+  MODIFY_REG(Device->SDCMR, (FMC_SDCMR_MODE | FMC_SDCMR_CTB2 | FMC_SDCMR_CTB1 | FMC_SDCMR_NRFS | FMC_SDCMR_MRD),
+             ((Command->CommandMode) | (Command->CommandTarget) |
+              (((Command->AutoRefreshNumber) - 1U) << FMC_SDCMR_NRFS_Pos) |
+              ((Command->ModeRegisterDefinition) << FMC_SDCMR_MRD_Pos)));
+  /* Get tick */
+  tickstart = HAL_GetTick();
+
+  /* wait until command is send */
+  while (HAL_IS_BIT_SET(Device->SDSR, FMC_SDSR_BUSY))
+  {
+    /* Check for the Timeout */
+    if (Timeout != HAL_MAX_DELAY)
+    {
+      if ((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout))
+      {
+        return HAL_TIMEOUT;
+      }
+    }
+  }
+  return HAL_OK;
+}
+
+/**
+  * @brief  Program the SDRAM Memory Refresh rate.
+  * @param  Device Pointer to SDRAM device instance
+  * @param  RefreshRate The SDRAM refresh rate value.
+  * @retval HAL state
+  */
+HAL_StatusTypeDef FMC_SDRAM_ProgramRefreshRate(FMC_SDRAM_TypeDef *Device, uint32_t RefreshRate)
+{
+  /* Check the parameters */
+  assert_param(IS_FMC_SDRAM_DEVICE(Device));
+  assert_param(IS_FMC_REFRESH_RATE(RefreshRate));
+
+  /* Set the refresh rate in command register */
+  MODIFY_REG(Device->SDRTR, FMC_SDRTR_COUNT, (RefreshRate << FMC_SDRTR_COUNT_Pos));
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Set the Number of consecutive SDRAM Memory auto Refresh commands.
+  * @param  Device Pointer to SDRAM device instance
+  * @param  AutoRefreshNumber Specifies the auto Refresh number.
+  * @retval None
+  */
+HAL_StatusTypeDef FMC_SDRAM_SetAutoRefreshNumber(FMC_SDRAM_TypeDef *Device,
+                                                 uint32_t AutoRefreshNumber)
+{
+  /* Check the parameters */
+  assert_param(IS_FMC_SDRAM_DEVICE(Device));
+  assert_param(IS_FMC_AUTOREFRESH_NUMBER(AutoRefreshNumber));
+
+  /* Set the Auto-refresh number in command register */
+  MODIFY_REG(Device->SDCMR, FMC_SDCMR_NRFS, ((AutoRefreshNumber - 1U) << FMC_SDCMR_NRFS_Pos));
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Returns the indicated FMC SDRAM bank mode status.
+  * @param  Device Pointer to SDRAM device instance
+  * @param  Bank Defines the FMC SDRAM bank. This parameter can be
+  *                     FMC_Bank1_SDRAM or FMC_Bank2_SDRAM.
+  * @retval The FMC SDRAM bank mode status, could be on of the following values:
+  *         FMC_SDRAM_NORMAL_MODE, FMC_SDRAM_SELF_REFRESH_MODE or
+  *         FMC_SDRAM_POWER_DOWN_MODE.
+  */
+uint32_t FMC_SDRAM_GetModeStatus(FMC_SDRAM_TypeDef *Device, uint32_t Bank)
+{
+  uint32_t tmpreg;
+
+  /* Check the parameters */
+  assert_param(IS_FMC_SDRAM_DEVICE(Device));
+  assert_param(IS_FMC_SDRAM_BANK(Bank));
+
+  /* Get the corresponding bank mode */
+  if (Bank == FMC_SDRAM_BANK1)
+  {
+    tmpreg = (uint32_t)(Device->SDSR & FMC_SDSR_MODES1);
+  }
+  else
+  {
+    tmpreg = ((uint32_t)(Device->SDSR & FMC_SDSR_MODES2) >> 2U);
+  }
+
+  /* Return the mode status */
+  return tmpreg;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* FMC_Bank5_6 */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* HAL_NOR_MODULE_ENABLED */
+/**
+  * @}
+  */
+/**
+  * @}
+  */
diff --git a/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_sdmmc.c b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_sdmmc.c
new file mode 100644
index 0000000..872aa04
--- /dev/null
+++ b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_sdmmc.c
@@ -0,0 +1,1578 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_ll_sdmmc.c
+  * @author  MCD Application Team
+  * @brief   SDMMC Low Layer HAL module driver.
+  *    
+  *          This file provides firmware functions to manage the following 
+  *          functionalities of the SDMMC peripheral:
+  *           + Initialization/de-initialization functions
+  *           + I/O operation functions
+  *           + Peripheral Control functions 
+  *           + Peripheral State functions
+  *         
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2016 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  @verbatim
+  ==============================================================================
+                       ##### SDMMC peripheral features #####
+  ==============================================================================        
+    [..] The SD/SDMMC MMC card host interface (SDMMC) provides an interface between the AHB
+         peripheral bus and MultiMedia cards (MMCs), SD memory cards, SDMMC cards and CE-ATA
+         devices.
+    
+    [..] The SDMMC features include the following:
+         (+) Full compliance with MultiMedia Card System Specification Version 4.2. Card support
+             for three different databus modes: 1-bit (default), 4-bit and 8-bit
+         (+) Full compatibility with previous versions of MultiMedia Cards (forward compatibility)
+         (+) Full compliance with SD Memory Card Specifications Version 2.0
+         (+) Full compliance with SD I/O Card Specification Version 2.0: card support for two
+             different data bus modes: 1-bit (default) and 4-bit
+         (+) Full support of the CE-ATA features (full compliance with CE-ATA digital protocol
+             Rev1.1)
+         (+) Data transfer up to 48 MHz for the 8 bit mode
+         (+) Data and command output enable signals to control external bidirectional drivers
+   
+                           ##### How to use this driver #####
+  ==============================================================================
+    [..]
+      This driver is a considered as a driver of service for external devices drivers 
+      that interfaces with the SDMMC peripheral.
+      According to the device used (SD card/ MMC card / SDMMC card ...), a set of APIs 
+      is used in the device's driver to perform SDMMC operations and functionalities.
+   
+      This driver is almost transparent for the final user, it is only used to implement other
+      functionalities of the external device.
+   
+    [..]
+      (+) The SDMMC clock (SDMMCCLK = 48 MHz) is coming from a specific output (MSI, PLLUSB1CLK,
+          PLLUSB2CLK). Before start working with SDMMC peripheral make sure that the
+          PLL is well configured.
+          The SDMMC peripheral uses two clock signals:
+          (++) SDMMC adapter clock (SDMMCCLK = 48 MHz)
+          (++) APB2 bus clock (PCLK2)
+       
+          -@@- PCLK2 and SDMMC_CK clock frequencies must respect the following condition:
+               Frequency(PCLK2) >= (3 / 8 x Frequency(SDMMC_CK))
+  
+      (+) Enable/Disable peripheral clock using RCC peripheral macros related to SDMMC
+          peripheral.
+
+      (+) Enable the Power ON State using the SDIO_PowerState_ON() 
+          function and disable it using the function SDIO_PowerState_OFF().
+                
+      (+) Enable/Disable the clock using the __SDIO_ENABLE()/__SDIO_DISABLE() macros.
+  
+      (+) Enable/Disable the peripheral interrupts using the macros __SDIO_ENABLE_IT() 
+          and __SDIO_DISABLE_IT() if you need to use interrupt mode. 
+  
+      (+) When using the DMA mode 
+          (++) Configure the DMA in the MSP layer of the external device
+          (++) Active the needed channel Request 
+          (++) Enable the DMA using __SDIO_DMA_ENABLE() macro or Disable it using the macro
+               __SDIO_DMA_DISABLE().
+  
+      (+) To control the CPSM (Command Path State Machine) and send 
+          commands to the card use the SDIO_SendCommand(), 
+          SDIO_GetCommandResponse() and SDIO_GetResponse() functions. First, user has
+          to fill the command structure (pointer to SDIO_CmdInitTypeDef) according 
+          to the selected command to be sent.
+          The parameters that should be filled are:
+           (++) Command Argument
+           (++) Command Index
+           (++) Command Response type
+           (++) Command Wait
+           (++) CPSM Status (Enable or Disable).
+  
+          -@@- To check if the command is well received, read the SDIO_CMDRESP
+              register using the SDIO_GetCommandResponse().
+              The SDMMC responses registers (SDIO_RESP1 to SDIO_RESP2), use the
+              SDIO_GetResponse() function.
+  
+      (+) To control the DPSM (Data Path State Machine) and send/receive 
+           data to/from the card use the SDIO_DataConfig(), SDIO_GetDataCounter(), 
+          SDIO_ReadFIFO(), SDIO_WriteFIFO() and SDIO_GetFIFOCount() functions.
+  
+    *** Read Operations ***
+    =======================
+    [..]
+      (#) First, user has to fill the data structure (pointer to
+          SDIO_DataInitTypeDef) according to the selected data type to be received.
+          The parameters that should be filled are:
+           (++) Data TimeOut
+           (++) Data Length
+           (++) Data Block size
+           (++) Data Transfer direction: should be from card (To SDMMC)
+           (++) Data Transfer mode
+           (++) DPSM Status (Enable or Disable)
+                                     
+      (#) Configure the SDMMC resources to receive the data from the card
+          according to selected transfer mode (Refer to Step 8, 9 and 10).
+  
+      (#) Send the selected Read command (refer to step 11).
+                    
+      (#) Use the SDIO flags/interrupts to check the transfer status.
+  
+    *** Write Operations ***
+    ========================
+    [..]
+     (#) First, user has to fill the data structure (pointer to
+         SDIO_DataInitTypeDef) according to the selected data type to be received.
+         The parameters that should be filled are:
+          (++) Data TimeOut
+          (++) Data Length
+          (++) Data Block size
+          (++) Data Transfer direction:  should be to card (To CARD)
+          (++) Data Transfer mode
+          (++) DPSM Status (Enable or Disable)
+  
+     (#) Configure the SDMMC resources to send the data to the card according to 
+         selected transfer mode.
+                     
+     (#) Send the selected Write command.
+                    
+     (#) Use the SDIO flags/interrupts to check the transfer status.
+       
+    *** Command management operations ***
+    =====================================
+    [..]
+     (#) The commands used for Read/Write/Erase operations are managed in 
+         separate functions. 
+         Each function allows to send the needed command with the related argument,
+         then check the response.
+         By the same approach, you could implement a command and check the response.
+  
+  @endverbatim
+  ******************************************************************************
+  */ 
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal.h"
+
+#if defined(SDIO)
+
+/** @addtogroup STM32F4xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup SDMMC_LL SDMMC Low Layer
+  * @brief Low layer module for SD
+  * @{
+  */
+
+#if defined(HAL_SD_MODULE_ENABLED) || defined(HAL_MMC_MODULE_ENABLED)
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+static uint32_t SDMMC_GetCmdError(SDIO_TypeDef *SDIOx);
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup SDMMC_LL_Exported_Functions SDMMC Low Layer Exported Functions
+  * @{
+  */
+
+/** @defgroup HAL_SDMMC_LL_Group1 Initialization de-initialization functions 
+ *  @brief    Initialization and Configuration functions 
+ *
+@verbatim    
+ ===============================================================================
+              ##### Initialization/de-initialization functions #####
+ ===============================================================================
+    [..]  This section provides functions allowing to:
+ 
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initializes the SDMMC according to the specified
+  *         parameters in the SDMMC_InitTypeDef and create the associated handle.
+  * @param  SDIOx: Pointer to SDMMC register base
+  * @param  Init: SDMMC initialization structure   
+  * @retval HAL status
+  */
+HAL_StatusTypeDef SDIO_Init(SDIO_TypeDef *SDIOx, SDIO_InitTypeDef Init)
+{
+  uint32_t tmpreg = 0;
+
+  /* Check the parameters */
+  assert_param(IS_SDIO_ALL_INSTANCE(SDIOx));
+  assert_param(IS_SDIO_CLOCK_EDGE(Init.ClockEdge)); 
+  assert_param(IS_SDIO_CLOCK_BYPASS(Init.ClockBypass));
+  assert_param(IS_SDIO_CLOCK_POWER_SAVE(Init.ClockPowerSave));
+  assert_param(IS_SDIO_BUS_WIDE(Init.BusWide));
+  assert_param(IS_SDIO_HARDWARE_FLOW_CONTROL(Init.HardwareFlowControl));
+  assert_param(IS_SDIO_CLKDIV(Init.ClockDiv));
+  
+  /* Set SDMMC configuration parameters */
+  tmpreg |= (Init.ClockEdge           |\
+             Init.ClockBypass         |\
+             Init.ClockPowerSave      |\
+             Init.BusWide             |\
+             Init.HardwareFlowControl |\
+             Init.ClockDiv
+             ); 
+  
+  /* Write to SDMMC CLKCR */
+  MODIFY_REG(SDIOx->CLKCR, CLKCR_CLEAR_MASK, tmpreg);  
+
+  return HAL_OK;
+}
+
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_SDMMC_LL_Group2 IO operation functions 
+ *  @brief   Data transfers functions 
+ *
+@verbatim   
+ ===============================================================================
+                      ##### I/O operation functions #####
+ ===============================================================================  
+    [..]
+    This subsection provides a set of functions allowing to manage the SDMMC data 
+    transfers.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Read data (word) from Rx FIFO in blocking mode (polling) 
+  * @param  SDIOx: Pointer to SDMMC register base
+  * @retval HAL status
+  */
+uint32_t SDIO_ReadFIFO(SDIO_TypeDef *SDIOx)
+{
+  /* Read data from Rx FIFO */ 
+  return (SDIOx->FIFO);
+}
+
+/**
+  * @brief  Write data (word) to Tx FIFO in blocking mode (polling) 
+  * @param  SDIOx: Pointer to SDMMC register base
+  * @param  pWriteData: pointer to data to write
+  * @retval HAL status
+  */
+HAL_StatusTypeDef SDIO_WriteFIFO(SDIO_TypeDef *SDIOx, uint32_t *pWriteData)
+{ 
+  /* Write data to FIFO */ 
+  SDIOx->FIFO = *pWriteData;
+
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_SDMMC_LL_Group3 Peripheral Control functions 
+ *  @brief   management functions 
+ *
+@verbatim   
+ ===============================================================================
+                      ##### Peripheral Control functions #####
+ ===============================================================================  
+    [..]
+    This subsection provides a set of functions allowing to control the SDMMC data 
+    transfers.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Set SDMMC Power state to ON. 
+  * @param  SDIOx: Pointer to SDMMC register base
+  * @retval HAL status
+  */
+HAL_StatusTypeDef SDIO_PowerState_ON(SDIO_TypeDef *SDIOx)
+{  
+  /* Set power state to ON */ 
+  SDIOx->POWER = SDIO_POWER_PWRCTRL;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Set SDMMC Power state to OFF. 
+  * @param  SDIOx: Pointer to SDMMC register base
+  * @retval HAL status
+  */
+HAL_StatusTypeDef SDIO_PowerState_OFF(SDIO_TypeDef *SDIOx)
+{
+  /* Set power state to OFF */
+  SDIOx->POWER = (uint32_t)0x00000000;
+  
+  return HAL_OK;
+}
+
+/**
+  * @brief  Get SDMMC Power state. 
+  * @param  SDIOx: Pointer to SDMMC register base
+  * @retval Power status of the controller. The returned value can be one of the 
+  *         following values:
+  *            - 0x00: Power OFF
+  *            - 0x02: Power UP
+  *            - 0x03: Power ON 
+  */
+uint32_t SDIO_GetPowerState(SDIO_TypeDef *SDIOx)  
+{
+  return (SDIOx->POWER & SDIO_POWER_PWRCTRL);
+}
+
+/**
+  * @brief  Configure the SDMMC command path according to the specified parameters in
+  *         SDIO_CmdInitTypeDef structure and send the command 
+  * @param  SDIOx: Pointer to SDMMC register base
+  * @param  Command: pointer to a SDIO_CmdInitTypeDef structure that contains 
+  *         the configuration information for the SDMMC command
+  * @retval HAL status
+  */
+HAL_StatusTypeDef SDIO_SendCommand(SDIO_TypeDef *SDIOx, SDIO_CmdInitTypeDef *Command)
+{
+  uint32_t tmpreg = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_SDIO_CMD_INDEX(Command->CmdIndex));
+  assert_param(IS_SDIO_RESPONSE(Command->Response));
+  assert_param(IS_SDIO_WAIT(Command->WaitForInterrupt));
+  assert_param(IS_SDIO_CPSM(Command->CPSM));
+
+  /* Set the SDMMC Argument value */
+  SDIOx->ARG = Command->Argument;
+
+  /* Set SDMMC command parameters */
+  tmpreg |= (uint32_t)(Command->CmdIndex         |\
+                       Command->Response         |\
+                       Command->WaitForInterrupt |\
+                       Command->CPSM);
+  
+  /* Write to SDMMC CMD register */
+  MODIFY_REG(SDIOx->CMD, CMD_CLEAR_MASK, tmpreg); 
+  
+  return HAL_OK;  
+}
+
+/**
+  * @brief  Return the command index of last command for which response received
+  * @param  SDIOx: Pointer to SDMMC register base
+  * @retval Command index of the last command response received
+  */
+uint8_t SDIO_GetCommandResponse(SDIO_TypeDef *SDIOx)
+{
+  return (uint8_t)(SDIOx->RESPCMD);
+}
+
+
+/**
+  * @brief  Return the response received from the card for the last command
+  * @param  SDIOx: Pointer to SDMMC register base    
+  * @param  Response: Specifies the SDMMC response register. 
+  *          This parameter can be one of the following values:
+  *            @arg SDIO_RESP1: Response Register 1
+  *            @arg SDIO_RESP2: Response Register 2
+  *            @arg SDIO_RESP3: Response Register 3
+  *            @arg SDIO_RESP4: Response Register 4  
+  * @retval The Corresponding response register value
+  */
+uint32_t SDIO_GetResponse(SDIO_TypeDef *SDIOx, uint32_t Response)
+{
+  uint32_t tmp;
+
+  /* Check the parameters */
+  assert_param(IS_SDIO_RESP(Response));
+  
+  /* Get the response */
+  tmp = (uint32_t)(&(SDIOx->RESP1)) + Response;
+  
+  return (*(__IO uint32_t *) tmp);
+}  
+
+/**
+  * @brief  Configure the SDMMC data path according to the specified 
+  *         parameters in the SDIO_DataInitTypeDef.
+  * @param  SDIOx: Pointer to SDIO register base  
+  * @param  Data : pointer to a SDIO_DataInitTypeDef structure 
+  *         that contains the configuration information for the SDMMC data.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef SDIO_ConfigData(SDIO_TypeDef *SDIOx, SDIO_DataInitTypeDef* Data)
+{
+  uint32_t tmpreg = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_SDIO_DATA_LENGTH(Data->DataLength));
+  assert_param(IS_SDIO_BLOCK_SIZE(Data->DataBlockSize));
+  assert_param(IS_SDIO_TRANSFER_DIR(Data->TransferDir));
+  assert_param(IS_SDIO_TRANSFER_MODE(Data->TransferMode));
+  assert_param(IS_SDIO_DPSM(Data->DPSM));
+
+  /* Set the SDMMC Data TimeOut value */
+  SDIOx->DTIMER = Data->DataTimeOut;
+
+  /* Set the SDMMC DataLength value */
+  SDIOx->DLEN = Data->DataLength;
+
+  /* Set the SDMMC data configuration parameters */
+  tmpreg |= (uint32_t)(Data->DataBlockSize |\
+                       Data->TransferDir   |\
+                       Data->TransferMode  |\
+                       Data->DPSM);
+  
+  /* Write to SDMMC DCTRL */
+  MODIFY_REG(SDIOx->DCTRL, DCTRL_CLEAR_MASK, tmpreg);
+
+  return HAL_OK;
+
+}
+
+/**
+  * @brief  Returns number of remaining data bytes to be transferred.
+  * @param  SDIOx: Pointer to SDIO register base
+  * @retval Number of remaining data bytes to be transferred
+  */
+uint32_t SDIO_GetDataCounter(SDIO_TypeDef *SDIOx)
+{
+  return (SDIOx->DCOUNT);
+}
+
+/**
+  * @brief  Get the FIFO data
+  * @param  SDIOx: Pointer to SDIO register base 
+  * @retval Data received
+  */
+uint32_t SDIO_GetFIFOCount(SDIO_TypeDef *SDIOx)
+{
+  return (SDIOx->FIFO);
+}
+
+/**
+  * @brief  Sets one of the two options of inserting read wait interval.
+  * @param  SDIOx: Pointer to SDIO register base   
+  * @param  SDIO_ReadWaitMode: SDMMC Read Wait operation mode.
+  *          This parameter can be:
+  *            @arg SDIO_READ_WAIT_MODE_CLK: Read Wait control by stopping SDMMCCLK
+  *            @arg SDIO_READ_WAIT_MODE_DATA2: Read Wait control using SDMMC_DATA2
+  * @retval None
+  */
+HAL_StatusTypeDef SDIO_SetSDMMCReadWaitMode(SDIO_TypeDef *SDIOx, uint32_t SDIO_ReadWaitMode)
+{
+  /* Check the parameters */
+  assert_param(IS_SDIO_READWAIT_MODE(SDIO_ReadWaitMode));
+
+  /* Set SDMMC read wait mode */
+  MODIFY_REG(SDIOx->DCTRL, SDIO_DCTRL_RWMOD, SDIO_ReadWaitMode);
+  
+  return HAL_OK;  
+}
+
+/**
+  * @}
+  */
+
+
+/** @defgroup HAL_SDMMC_LL_Group4 Command management functions 
+ *  @brief   Data transfers functions 
+ *
+@verbatim   
+ ===============================================================================
+                   ##### Commands management functions #####
+ ===============================================================================  
+    [..]
+    This subsection provides a set of functions allowing to manage the needed commands.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Send the Data Block Length command and check the response
+  * @param  SDIOx: Pointer to SDIO register base 
+  * @retval HAL status
+  */
+uint32_t SDMMC_CmdBlockLength(SDIO_TypeDef *SDIOx, uint32_t BlockSize)
+{
+  SDIO_CmdInitTypeDef  sdmmc_cmdinit;
+  uint32_t errorstate;
+  
+  /* Set Block Size for Card */ 
+  sdmmc_cmdinit.Argument         = (uint32_t)BlockSize;
+  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_SET_BLOCKLEN;
+  sdmmc_cmdinit.Response         = SDIO_RESPONSE_SHORT;
+  sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
+  sdmmc_cmdinit.CPSM             = SDIO_CPSM_ENABLE;
+  (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
+  
+  /* Check for error conditions */
+  errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_SET_BLOCKLEN, SDIO_CMDTIMEOUT);
+
+  return errorstate;
+}
+
+/**
+  * @brief  Send the Read Single Block command and check the response
+  * @param  SDIOx: Pointer to SDIO register base 
+  * @retval HAL status
+  */
+uint32_t SDMMC_CmdReadSingleBlock(SDIO_TypeDef *SDIOx, uint32_t ReadAdd)
+{
+  SDIO_CmdInitTypeDef  sdmmc_cmdinit;
+  uint32_t errorstate;
+  
+  /* Set Block Size for Card */ 
+  sdmmc_cmdinit.Argument         = (uint32_t)ReadAdd;
+  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_READ_SINGLE_BLOCK;
+  sdmmc_cmdinit.Response         = SDIO_RESPONSE_SHORT;
+  sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
+  sdmmc_cmdinit.CPSM             = SDIO_CPSM_ENABLE;
+  (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
+  
+  /* Check for error conditions */
+  errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_READ_SINGLE_BLOCK, SDIO_CMDTIMEOUT);
+
+  return errorstate;
+}
+
+/**
+  * @brief  Send the Read Multi Block command and check the response
+  * @param  SDIOx: Pointer to SDIO register base 
+  * @retval HAL status
+  */
+uint32_t SDMMC_CmdReadMultiBlock(SDIO_TypeDef *SDIOx, uint32_t ReadAdd)
+{
+  SDIO_CmdInitTypeDef  sdmmc_cmdinit;
+  uint32_t errorstate;
+  
+  /* Set Block Size for Card */ 
+  sdmmc_cmdinit.Argument         = (uint32_t)ReadAdd;
+  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_READ_MULT_BLOCK;
+  sdmmc_cmdinit.Response         = SDIO_RESPONSE_SHORT;
+  sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
+  sdmmc_cmdinit.CPSM             = SDIO_CPSM_ENABLE;
+  (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
+  
+  /* Check for error conditions */
+  errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_READ_MULT_BLOCK, SDIO_CMDTIMEOUT);
+
+  return errorstate;
+}
+
+/**
+  * @brief  Send the Write Single Block command and check the response
+  * @param  SDIOx: Pointer to SDIO register base 
+  * @retval HAL status
+  */
+uint32_t SDMMC_CmdWriteSingleBlock(SDIO_TypeDef *SDIOx, uint32_t WriteAdd)
+{
+  SDIO_CmdInitTypeDef  sdmmc_cmdinit;
+  uint32_t errorstate;
+  
+  /* Set Block Size for Card */ 
+  sdmmc_cmdinit.Argument         = (uint32_t)WriteAdd;
+  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_WRITE_SINGLE_BLOCK;
+  sdmmc_cmdinit.Response         = SDIO_RESPONSE_SHORT;
+  sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
+  sdmmc_cmdinit.CPSM             = SDIO_CPSM_ENABLE;
+  (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
+  
+  /* Check for error conditions */
+  errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_WRITE_SINGLE_BLOCK, SDIO_CMDTIMEOUT);
+
+  return errorstate;
+}
+
+/**
+  * @brief  Send the Write Multi Block command and check the response
+  * @param  SDIOx: Pointer to SDIO register base 
+  * @retval HAL status
+  */
+uint32_t SDMMC_CmdWriteMultiBlock(SDIO_TypeDef *SDIOx, uint32_t WriteAdd)
+{
+  SDIO_CmdInitTypeDef  sdmmc_cmdinit;
+  uint32_t errorstate;
+  
+  /* Set Block Size for Card */ 
+  sdmmc_cmdinit.Argument         = (uint32_t)WriteAdd;
+  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_WRITE_MULT_BLOCK;
+  sdmmc_cmdinit.Response         = SDIO_RESPONSE_SHORT;
+  sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
+  sdmmc_cmdinit.CPSM             = SDIO_CPSM_ENABLE;
+  (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
+  
+  /* Check for error conditions */
+  errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_WRITE_MULT_BLOCK, SDIO_CMDTIMEOUT);
+
+  return errorstate;
+}
+
+/**
+  * @brief  Send the Start Address Erase command for SD and check the response
+  * @param  SDIOx: Pointer to SDIO register base 
+  * @retval HAL status
+  */
+uint32_t SDMMC_CmdSDEraseStartAdd(SDIO_TypeDef *SDIOx, uint32_t StartAdd)
+{
+  SDIO_CmdInitTypeDef  sdmmc_cmdinit;
+  uint32_t errorstate;
+  
+  /* Set Block Size for Card */ 
+  sdmmc_cmdinit.Argument         = (uint32_t)StartAdd;
+  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_SD_ERASE_GRP_START;
+  sdmmc_cmdinit.Response         = SDIO_RESPONSE_SHORT;
+  sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
+  sdmmc_cmdinit.CPSM             = SDIO_CPSM_ENABLE;
+  (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
+  
+  /* Check for error conditions */
+  errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_SD_ERASE_GRP_START, SDIO_CMDTIMEOUT);
+
+  return errorstate;
+}
+
+/**
+  * @brief  Send the End Address Erase command for SD and check the response
+  * @param  SDIOx: Pointer to SDIO register base 
+  * @retval HAL status
+  */
+uint32_t SDMMC_CmdSDEraseEndAdd(SDIO_TypeDef *SDIOx, uint32_t EndAdd)
+{
+  SDIO_CmdInitTypeDef  sdmmc_cmdinit;
+  uint32_t errorstate;
+  
+  /* Set Block Size for Card */ 
+  sdmmc_cmdinit.Argument         = (uint32_t)EndAdd;
+  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_SD_ERASE_GRP_END;
+  sdmmc_cmdinit.Response         = SDIO_RESPONSE_SHORT;
+  sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
+  sdmmc_cmdinit.CPSM             = SDIO_CPSM_ENABLE;
+  (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
+  
+  /* Check for error conditions */
+  errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_SD_ERASE_GRP_END, SDIO_CMDTIMEOUT);
+
+  return errorstate;
+}
+
+/**
+  * @brief  Send the Start Address Erase command and check the response
+  * @param  SDIOx: Pointer to SDIO register base 
+  * @retval HAL status
+  */
+uint32_t SDMMC_CmdEraseStartAdd(SDIO_TypeDef *SDIOx, uint32_t StartAdd)
+{
+  SDIO_CmdInitTypeDef  sdmmc_cmdinit;
+  uint32_t errorstate;
+  
+  /* Set Block Size for Card */ 
+  sdmmc_cmdinit.Argument         = (uint32_t)StartAdd;
+  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_ERASE_GRP_START;
+  sdmmc_cmdinit.Response         = SDIO_RESPONSE_SHORT;
+  sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
+  sdmmc_cmdinit.CPSM             = SDIO_CPSM_ENABLE;
+  (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
+  
+  /* Check for error conditions */
+  errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_ERASE_GRP_START, SDIO_CMDTIMEOUT);
+
+  return errorstate;
+}
+
+/**
+  * @brief  Send the End Address Erase command and check the response
+  * @param  SDIOx: Pointer to SDIO register base 
+  * @retval HAL status
+  */
+uint32_t SDMMC_CmdEraseEndAdd(SDIO_TypeDef *SDIOx, uint32_t EndAdd)
+{
+  SDIO_CmdInitTypeDef  sdmmc_cmdinit;
+  uint32_t errorstate;
+  
+  /* Set Block Size for Card */ 
+  sdmmc_cmdinit.Argument         = (uint32_t)EndAdd;
+  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_ERASE_GRP_END;
+  sdmmc_cmdinit.Response         = SDIO_RESPONSE_SHORT;
+  sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
+  sdmmc_cmdinit.CPSM             = SDIO_CPSM_ENABLE;
+  (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
+  
+  /* Check for error conditions */
+  errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_ERASE_GRP_END, SDIO_CMDTIMEOUT);
+
+  return errorstate;
+}
+
+/**
+  * @brief  Send the Erase command and check the response
+  * @param  SDIOx: Pointer to SDIO register base 
+  * @retval HAL status
+  */
+uint32_t SDMMC_CmdErase(SDIO_TypeDef *SDIOx)
+{
+  SDIO_CmdInitTypeDef  sdmmc_cmdinit;
+  uint32_t errorstate;
+  
+  /* Set Block Size for Card */ 
+  sdmmc_cmdinit.Argument         = 0U;
+  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_ERASE;
+  sdmmc_cmdinit.Response         = SDIO_RESPONSE_SHORT;
+  sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
+  sdmmc_cmdinit.CPSM             = SDIO_CPSM_ENABLE;
+  (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
+  
+  /* Check for error conditions */
+  errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_ERASE, SDIO_MAXERASETIMEOUT);
+
+  return errorstate;
+}
+
+/**
+  * @brief  Send the Stop Transfer command and check the response.
+  * @param  SDIOx: Pointer to SDIO register base 
+  * @retval HAL status
+  */
+uint32_t SDMMC_CmdStopTransfer(SDIO_TypeDef *SDIOx)
+{
+  SDIO_CmdInitTypeDef  sdmmc_cmdinit;
+  uint32_t errorstate;
+  
+  /* Send CMD12 STOP_TRANSMISSION  */
+  sdmmc_cmdinit.Argument         = 0U;
+  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_STOP_TRANSMISSION;
+  sdmmc_cmdinit.Response         = SDIO_RESPONSE_SHORT;
+  sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
+  sdmmc_cmdinit.CPSM             = SDIO_CPSM_ENABLE;
+  (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
+  
+  /* Check for error conditions */
+  errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_STOP_TRANSMISSION, SDIO_STOPTRANSFERTIMEOUT);
+
+  return errorstate;
+}
+
+/**
+  * @brief  Send the Select Deselect command and check the response.
+  * @param  SDIOx: Pointer to SDIO register base 
+  * @param  addr: Address of the card to be selected  
+  * @retval HAL status
+  */
+uint32_t SDMMC_CmdSelDesel(SDIO_TypeDef *SDIOx, uint64_t Addr)
+{
+  SDIO_CmdInitTypeDef  sdmmc_cmdinit;
+  uint32_t errorstate;
+  
+  /* Send CMD7 SDMMC_SEL_DESEL_CARD */
+  sdmmc_cmdinit.Argument         = (uint32_t)Addr;
+  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_SEL_DESEL_CARD;
+  sdmmc_cmdinit.Response         = SDIO_RESPONSE_SHORT;
+  sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
+  sdmmc_cmdinit.CPSM             = SDIO_CPSM_ENABLE;
+  (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
+  
+  /* Check for error conditions */
+  errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_SEL_DESEL_CARD, SDIO_CMDTIMEOUT);
+
+  return errorstate;
+}
+
+/**
+  * @brief  Send the Go Idle State command and check the response.
+  * @param  SDIOx: Pointer to SDIO register base 
+  * @retval HAL status
+  */
+uint32_t SDMMC_CmdGoIdleState(SDIO_TypeDef *SDIOx)
+{
+  SDIO_CmdInitTypeDef  sdmmc_cmdinit;
+  uint32_t errorstate;
+  
+  sdmmc_cmdinit.Argument         = 0U;
+  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_GO_IDLE_STATE;
+  sdmmc_cmdinit.Response         = SDIO_RESPONSE_NO;
+  sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
+  sdmmc_cmdinit.CPSM             = SDIO_CPSM_ENABLE;
+  (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
+  
+  /* Check for error conditions */
+  errorstate = SDMMC_GetCmdError(SDIOx);
+
+  return errorstate;
+}
+
+/**
+  * @brief  Send the Operating Condition command and check the response.
+  * @param  SDIOx: Pointer to SDIO register base 
+  * @retval HAL status
+  */
+uint32_t SDMMC_CmdOperCond(SDIO_TypeDef *SDIOx)
+{
+  SDIO_CmdInitTypeDef  sdmmc_cmdinit;
+  uint32_t errorstate;
+  
+  /* Send CMD8 to verify SD card interface operating condition */
+  /* Argument: - [31:12]: Reserved (shall be set to '0')
+  - [11:8]: Supply Voltage (VHS) 0x1 (Range: 2.7-3.6 V)
+  - [7:0]: Check Pattern (recommended 0xAA) */
+  /* CMD Response: R7 */
+  sdmmc_cmdinit.Argument         = SDMMC_CHECK_PATTERN;
+  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_HS_SEND_EXT_CSD;
+  sdmmc_cmdinit.Response         = SDIO_RESPONSE_SHORT;
+  sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
+  sdmmc_cmdinit.CPSM             = SDIO_CPSM_ENABLE;
+  (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
+  
+  /* Check for error conditions */
+  errorstate = SDMMC_GetCmdResp7(SDIOx);
+
+  return errorstate;
+}
+
+/**
+  * @brief  Send the Application command to verify that that the next command 
+  *         is an application specific com-mand rather than a standard command
+  *         and check the response.
+  * @param  SDIOx: Pointer to SDIO register base 
+  * @param  Argument: Command Argument 
+  * @retval HAL status
+  */
+uint32_t SDMMC_CmdAppCommand(SDIO_TypeDef *SDIOx, uint32_t Argument)
+{
+  SDIO_CmdInitTypeDef  sdmmc_cmdinit;
+  uint32_t errorstate;
+  
+  sdmmc_cmdinit.Argument         = (uint32_t)Argument;
+  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_APP_CMD;
+  sdmmc_cmdinit.Response         = SDIO_RESPONSE_SHORT;
+  sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
+  sdmmc_cmdinit.CPSM             = SDIO_CPSM_ENABLE;
+  (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
+  
+  /* Check for error conditions */
+  /* If there is a HAL_ERROR, it is a MMC card, else
+  it is a SD card: SD card 2.0 (voltage range mismatch)
+     or SD card 1.x */
+  errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_APP_CMD, SDIO_CMDTIMEOUT);
+
+  return errorstate;
+}
+
+/**
+  * @brief  Send the command asking the accessed card to send its operating 
+  *         condition register (OCR)
+  * @param  SDIOx: Pointer to SDIO register base 
+  * @param  Argument: Command Argument
+  * @retval HAL status
+  */
+uint32_t SDMMC_CmdAppOperCommand(SDIO_TypeDef *SDIOx, uint32_t Argument)
+{
+  SDIO_CmdInitTypeDef  sdmmc_cmdinit;
+  uint32_t errorstate;
+  
+  sdmmc_cmdinit.Argument         = SDMMC_VOLTAGE_WINDOW_SD | Argument;
+  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_SD_APP_OP_COND;
+  sdmmc_cmdinit.Response         = SDIO_RESPONSE_SHORT;
+  sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
+  sdmmc_cmdinit.CPSM             = SDIO_CPSM_ENABLE;
+  (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
+  
+  /* Check for error conditions */
+  errorstate = SDMMC_GetCmdResp3(SDIOx);
+
+  return errorstate;
+}
+
+/**
+  * @brief  Send the Bus Width command and check the response.
+  * @param  SDIOx: Pointer to SDIO register base 
+  * @param  BusWidth: BusWidth
+  * @retval HAL status
+  */
+uint32_t SDMMC_CmdBusWidth(SDIO_TypeDef *SDIOx, uint32_t BusWidth)
+{
+  SDIO_CmdInitTypeDef  sdmmc_cmdinit;
+  uint32_t errorstate;
+  
+  sdmmc_cmdinit.Argument         = (uint32_t)BusWidth;
+  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_APP_SD_SET_BUSWIDTH;
+  sdmmc_cmdinit.Response         = SDIO_RESPONSE_SHORT;
+  sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
+  sdmmc_cmdinit.CPSM             = SDIO_CPSM_ENABLE;
+  (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
+  
+  /* Check for error conditions */
+  errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_APP_SD_SET_BUSWIDTH, SDIO_CMDTIMEOUT);
+
+  return errorstate;
+}
+
+/**
+  * @brief  Send the Send SCR command and check the response.
+  * @param  SDIOx: Pointer to SDIO register base 
+  * @retval HAL status
+  */
+uint32_t SDMMC_CmdSendSCR(SDIO_TypeDef *SDIOx)
+{
+  SDIO_CmdInitTypeDef  sdmmc_cmdinit;
+  uint32_t errorstate;
+  
+  /* Send CMD51 SD_APP_SEND_SCR */
+  sdmmc_cmdinit.Argument         = 0U;
+  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_SD_APP_SEND_SCR;
+  sdmmc_cmdinit.Response         = SDIO_RESPONSE_SHORT;
+  sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
+  sdmmc_cmdinit.CPSM             = SDIO_CPSM_ENABLE;
+  (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
+  
+  /* Check for error conditions */
+  errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_SD_APP_SEND_SCR, SDIO_CMDTIMEOUT);
+
+  return errorstate;
+}
+
+/**
+  * @brief  Send the Send CID command and check the response.
+  * @param  SDIOx: Pointer to SDIO register base 
+  * @retval HAL status
+  */
+uint32_t SDMMC_CmdSendCID(SDIO_TypeDef *SDIOx)
+{
+  SDIO_CmdInitTypeDef  sdmmc_cmdinit;
+  uint32_t errorstate;
+  
+  /* Send CMD2 ALL_SEND_CID */
+  sdmmc_cmdinit.Argument         = 0U;
+  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_ALL_SEND_CID;
+  sdmmc_cmdinit.Response         = SDIO_RESPONSE_LONG;
+  sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
+  sdmmc_cmdinit.CPSM             = SDIO_CPSM_ENABLE;
+  (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
+  
+  /* Check for error conditions */
+  errorstate = SDMMC_GetCmdResp2(SDIOx);
+
+  return errorstate;
+}
+
+/**
+  * @brief  Send the Send CSD command and check the response.
+  * @param  SDIOx: Pointer to SDIO register base 
+  * @param  Argument: Command Argument
+  * @retval HAL status
+  */
+uint32_t SDMMC_CmdSendCSD(SDIO_TypeDef *SDIOx, uint32_t Argument)
+{
+  SDIO_CmdInitTypeDef  sdmmc_cmdinit;
+  uint32_t errorstate;
+  
+  /* Send CMD9 SEND_CSD */
+  sdmmc_cmdinit.Argument         = Argument;
+  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_SEND_CSD;
+  sdmmc_cmdinit.Response         = SDIO_RESPONSE_LONG;
+  sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
+  sdmmc_cmdinit.CPSM             = SDIO_CPSM_ENABLE;
+  (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
+  
+  /* Check for error conditions */
+  errorstate = SDMMC_GetCmdResp2(SDIOx);
+
+  return errorstate;
+}
+
+/**
+  * @brief  Send the Send CSD command and check the response.
+  * @param  SDIOx: Pointer to SDIO register base 
+  * @param  pRCA: Card RCA  
+  * @retval HAL status
+  */
+uint32_t SDMMC_CmdSetRelAdd(SDIO_TypeDef *SDIOx, uint16_t *pRCA)
+{
+  SDIO_CmdInitTypeDef  sdmmc_cmdinit;
+  uint32_t errorstate;
+  
+  /* Send CMD3 SD_CMD_SET_REL_ADDR */
+  sdmmc_cmdinit.Argument         = 0U;
+  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_SET_REL_ADDR;
+  sdmmc_cmdinit.Response         = SDIO_RESPONSE_SHORT;
+  sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
+  sdmmc_cmdinit.CPSM             = SDIO_CPSM_ENABLE;
+  (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
+  
+  /* Check for error conditions */
+  errorstate = SDMMC_GetCmdResp6(SDIOx, SDMMC_CMD_SET_REL_ADDR, pRCA);
+
+  return errorstate;
+}
+
+/**
+  * @brief  Send the Set Relative Address command to MMC card (not SD card).
+  * @param  SDIOx Pointer to SDIO register base
+  * @param  RCA Card RCA
+  * @retval HAL status
+  */
+uint32_t SDMMC_CmdSetRelAddMmc(SDIO_TypeDef *SDIOx, uint16_t RCA)
+{
+  SDIO_CmdInitTypeDef  sdmmc_cmdinit;
+  uint32_t errorstate;
+
+  /* Send CMD3 SD_CMD_SET_REL_ADDR */
+  sdmmc_cmdinit.Argument         = ((uint32_t)RCA << 16U);
+  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_SET_REL_ADDR;
+  sdmmc_cmdinit.Response         = SDIO_RESPONSE_SHORT;
+  sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
+  sdmmc_cmdinit.CPSM             = SDIO_CPSM_ENABLE;
+  (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
+
+  /* Check for error conditions */
+  errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_SET_REL_ADDR, SDIO_CMDTIMEOUT);
+
+  return errorstate;
+}
+
+/**
+  * @brief  Send the Status command and check the response.
+  * @param  SDIOx: Pointer to SDIO register base 
+  * @param  Argument: Command Argument
+  * @retval HAL status
+  */
+uint32_t SDMMC_CmdSendStatus(SDIO_TypeDef *SDIOx, uint32_t Argument)
+{
+  SDIO_CmdInitTypeDef  sdmmc_cmdinit;
+  uint32_t errorstate;
+  
+  sdmmc_cmdinit.Argument         = Argument;
+  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_SEND_STATUS;
+  sdmmc_cmdinit.Response         = SDIO_RESPONSE_SHORT;
+  sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
+  sdmmc_cmdinit.CPSM             = SDIO_CPSM_ENABLE;
+  (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
+  
+  /* Check for error conditions */
+  errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_SEND_STATUS, SDIO_CMDTIMEOUT);
+
+  return errorstate;
+}
+
+/**
+  * @brief  Send the Status register command and check the response.
+  * @param  SDIOx: Pointer to SDIO register base 
+  * @retval HAL status
+  */
+uint32_t SDMMC_CmdStatusRegister(SDIO_TypeDef *SDIOx)
+{
+  SDIO_CmdInitTypeDef  sdmmc_cmdinit;
+  uint32_t errorstate;
+  
+  sdmmc_cmdinit.Argument         = 0U;
+  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_SD_APP_STATUS;
+  sdmmc_cmdinit.Response         = SDIO_RESPONSE_SHORT;
+  sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
+  sdmmc_cmdinit.CPSM             = SDIO_CPSM_ENABLE;
+  (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
+  
+  /* Check for error conditions */
+  errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_SD_APP_STATUS, SDIO_CMDTIMEOUT);
+
+  return errorstate;
+}
+
+/**
+  * @brief  Sends host capacity support information and activates the card's 
+  *         initialization process. Send SDMMC_CMD_SEND_OP_COND command
+  * @param  SDIOx: Pointer to SDIO register base 
+  * @parame Argument: Argument used for the command
+  * @retval HAL status
+  */
+uint32_t SDMMC_CmdOpCondition(SDIO_TypeDef *SDIOx, uint32_t Argument)
+{
+  SDIO_CmdInitTypeDef  sdmmc_cmdinit;
+  uint32_t errorstate;
+  
+  sdmmc_cmdinit.Argument         = Argument;
+  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_SEND_OP_COND;
+  sdmmc_cmdinit.Response         = SDIO_RESPONSE_SHORT;
+  sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
+  sdmmc_cmdinit.CPSM             = SDIO_CPSM_ENABLE;
+  (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
+  
+  /* Check for error conditions */
+  errorstate = SDMMC_GetCmdResp3(SDIOx);
+
+  return errorstate;
+}
+
+/**
+  * @brief  Checks switchable function and switch card function. SDMMC_CMD_HS_SWITCH command
+  * @param  SDIOx: Pointer to SDIO register base 
+  * @parame Argument: Argument used for the command
+  * @retval HAL status
+  */
+uint32_t SDMMC_CmdSwitch(SDIO_TypeDef *SDIOx, uint32_t Argument)
+{
+  SDIO_CmdInitTypeDef  sdmmc_cmdinit;
+  uint32_t errorstate;
+  
+  /* Send CMD6 to activate SDR50 Mode and Power Limit 1.44W */
+  /* CMD Response: R1 */
+  sdmmc_cmdinit.Argument         = Argument; /* SDMMC_SDR25_SWITCH_PATTERN */
+  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_HS_SWITCH;
+  sdmmc_cmdinit.Response         = SDIO_RESPONSE_SHORT;
+  sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
+  sdmmc_cmdinit.CPSM             = SDIO_CPSM_ENABLE;
+  (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
+  
+  /* Check for error conditions */
+  errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_HS_SWITCH, SDIO_CMDTIMEOUT);
+
+  return errorstate;
+}
+
+/**
+  * @brief  Send the Send EXT_CSD command and check the response.
+  * @param  SDIOx Pointer to SDMMC register base
+  * @param  Argument Command Argument
+  * @retval HAL status
+  */
+uint32_t SDMMC_CmdSendEXTCSD(SDIO_TypeDef *SDIOx, uint32_t Argument)
+{
+  SDIO_CmdInitTypeDef  sdmmc_cmdinit;
+  uint32_t errorstate;
+
+  /* Send CMD9 SEND_CSD */
+  sdmmc_cmdinit.Argument         = Argument;
+  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_HS_SEND_EXT_CSD;
+  sdmmc_cmdinit.Response         = SDIO_RESPONSE_SHORT;
+  sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
+  sdmmc_cmdinit.CPSM             = SDIO_CPSM_ENABLE;
+  (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
+
+  /* Check for error conditions */
+  errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_HS_SEND_EXT_CSD,SDIO_CMDTIMEOUT);
+
+  return errorstate;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_SDMMC_LL_Group5 Responses management functions
+ *  @brief   Responses functions
+ *
+@verbatim
+ ===============================================================================
+                   ##### Responses management functions #####
+ ===============================================================================
+    [..]
+    This subsection provides a set of functions allowing to manage the needed responses.
+
+@endverbatim
+  * @{
+  */
+/**
+  * @brief  Checks for error conditions for R1 response.
+  * @param  SDIOx Pointer to SDMMC register base
+  * @param  SD_CMD: The sent command index  
+  * @retval SD Card error state
+  */
+uint32_t SDMMC_GetCmdResp1(SDIO_TypeDef *SDIOx, uint8_t SD_CMD, uint32_t Timeout)
+{
+  uint32_t response_r1;
+  uint32_t sta_reg;
+  
+  /* 8 is the number of required instructions cycles for the below loop statement.
+  The Timeout is expressed in ms */
+  uint32_t count = Timeout * (SystemCoreClock / 8U /1000U);
+  
+  do
+  {
+    if (count-- == 0U)
+    {
+      return SDMMC_ERROR_TIMEOUT;
+    }
+    sta_reg = SDIOx->STA;
+  }while(((sta_reg & (SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT)) == 0U) ||
+         ((sta_reg & SDIO_FLAG_CMDACT) != 0U ));
+    
+  if(__SDIO_GET_FLAG(SDIOx, SDIO_FLAG_CTIMEOUT))
+  {
+    __SDIO_CLEAR_FLAG(SDIOx, SDIO_FLAG_CTIMEOUT);
+    
+    return SDMMC_ERROR_CMD_RSP_TIMEOUT;
+  }
+  else if(__SDIO_GET_FLAG(SDIOx, SDIO_FLAG_CCRCFAIL))
+  {
+    __SDIO_CLEAR_FLAG(SDIOx, SDIO_FLAG_CCRCFAIL);
+    
+    return SDMMC_ERROR_CMD_CRC_FAIL;
+  }
+  else
+  {
+    /* Nothing to do */
+  }
+  
+  /* Clear all the static flags */
+  __SDIO_CLEAR_FLAG(SDIOx, SDIO_STATIC_CMD_FLAGS);
+  
+  /* Check response received is of desired command */
+  if(SDIO_GetCommandResponse(SDIOx) != SD_CMD)
+  {
+    return SDMMC_ERROR_CMD_CRC_FAIL;
+  }
+  
+  /* We have received response, retrieve it for analysis  */
+  response_r1 = SDIO_GetResponse(SDIOx, SDIO_RESP1);
+  
+  if((response_r1 & SDMMC_OCR_ERRORBITS) == SDMMC_ALLZERO)
+  {
+    return SDMMC_ERROR_NONE;
+  }
+  else if((response_r1 & SDMMC_OCR_ADDR_OUT_OF_RANGE) == SDMMC_OCR_ADDR_OUT_OF_RANGE)
+  {
+    return SDMMC_ERROR_ADDR_OUT_OF_RANGE;
+  }
+  else if((response_r1 & SDMMC_OCR_ADDR_MISALIGNED) == SDMMC_OCR_ADDR_MISALIGNED)
+  {
+    return SDMMC_ERROR_ADDR_MISALIGNED;
+  }
+  else if((response_r1 & SDMMC_OCR_BLOCK_LEN_ERR) == SDMMC_OCR_BLOCK_LEN_ERR)
+  {
+    return SDMMC_ERROR_BLOCK_LEN_ERR;
+  }
+  else if((response_r1 & SDMMC_OCR_ERASE_SEQ_ERR) == SDMMC_OCR_ERASE_SEQ_ERR)
+  {
+    return SDMMC_ERROR_ERASE_SEQ_ERR;
+  }
+  else if((response_r1 & SDMMC_OCR_BAD_ERASE_PARAM) == SDMMC_OCR_BAD_ERASE_PARAM)
+  {
+    return SDMMC_ERROR_BAD_ERASE_PARAM;
+  }
+  else if((response_r1 & SDMMC_OCR_WRITE_PROT_VIOLATION) == SDMMC_OCR_WRITE_PROT_VIOLATION)
+  {
+    return SDMMC_ERROR_WRITE_PROT_VIOLATION;
+  }
+  else if((response_r1 & SDMMC_OCR_LOCK_UNLOCK_FAILED) == SDMMC_OCR_LOCK_UNLOCK_FAILED)
+  {
+    return SDMMC_ERROR_LOCK_UNLOCK_FAILED;
+  }
+  else if((response_r1 & SDMMC_OCR_COM_CRC_FAILED) == SDMMC_OCR_COM_CRC_FAILED)
+  {
+    return SDMMC_ERROR_COM_CRC_FAILED;
+  }
+  else if((response_r1 & SDMMC_OCR_ILLEGAL_CMD) == SDMMC_OCR_ILLEGAL_CMD)
+  {
+    return SDMMC_ERROR_ILLEGAL_CMD;
+  }
+  else if((response_r1 & SDMMC_OCR_CARD_ECC_FAILED) == SDMMC_OCR_CARD_ECC_FAILED)
+  {
+    return SDMMC_ERROR_CARD_ECC_FAILED;
+  }
+  else if((response_r1 & SDMMC_OCR_CC_ERROR) == SDMMC_OCR_CC_ERROR)
+  {
+    return SDMMC_ERROR_CC_ERR;
+  }
+  else if((response_r1 & SDMMC_OCR_STREAM_READ_UNDERRUN) == SDMMC_OCR_STREAM_READ_UNDERRUN)
+  {
+    return SDMMC_ERROR_STREAM_READ_UNDERRUN;
+  }
+  else if((response_r1 & SDMMC_OCR_STREAM_WRITE_OVERRUN) == SDMMC_OCR_STREAM_WRITE_OVERRUN)
+  {
+    return SDMMC_ERROR_STREAM_WRITE_OVERRUN;
+  }
+  else if((response_r1 & SDMMC_OCR_CID_CSD_OVERWRITE) == SDMMC_OCR_CID_CSD_OVERWRITE)
+  {
+    return SDMMC_ERROR_CID_CSD_OVERWRITE;
+  }
+  else if((response_r1 & SDMMC_OCR_WP_ERASE_SKIP) == SDMMC_OCR_WP_ERASE_SKIP)
+  {
+    return SDMMC_ERROR_WP_ERASE_SKIP;
+  }
+  else if((response_r1 & SDMMC_OCR_CARD_ECC_DISABLED) == SDMMC_OCR_CARD_ECC_DISABLED)
+  {
+    return SDMMC_ERROR_CARD_ECC_DISABLED;
+  }
+  else if((response_r1 & SDMMC_OCR_ERASE_RESET) == SDMMC_OCR_ERASE_RESET)
+  {
+    return SDMMC_ERROR_ERASE_RESET;
+  }
+  else if((response_r1 & SDMMC_OCR_AKE_SEQ_ERROR) == SDMMC_OCR_AKE_SEQ_ERROR)
+  {
+    return SDMMC_ERROR_AKE_SEQ_ERR;
+  }
+  else
+  {
+    return SDMMC_ERROR_GENERAL_UNKNOWN_ERR;
+  }
+}
+
+/**
+  * @brief  Checks for error conditions for R2 (CID or CSD) response.
+  * @param  SDIOx Pointer to SDMMC register base
+  * @retval SD Card error state
+  */
+uint32_t SDMMC_GetCmdResp2(SDIO_TypeDef *SDIOx)
+{
+  uint32_t sta_reg;
+  /* 8 is the number of required instructions cycles for the below loop statement.
+  The SDIO_CMDTIMEOUT is expressed in ms */
+  uint32_t count = SDIO_CMDTIMEOUT * (SystemCoreClock / 8U /1000U);
+  
+  do
+  {
+    if (count-- == 0U)
+    {
+      return SDMMC_ERROR_TIMEOUT;
+    }
+    sta_reg = SDIOx->STA;
+  }while(((sta_reg & (SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT)) == 0U) ||
+         ((sta_reg & SDIO_FLAG_CMDACT) != 0U ));
+    
+  if (__SDIO_GET_FLAG(SDIOx, SDIO_FLAG_CTIMEOUT))
+  {
+    __SDIO_CLEAR_FLAG(SDIOx, SDIO_FLAG_CTIMEOUT);
+    
+    return SDMMC_ERROR_CMD_RSP_TIMEOUT;
+  }
+  else if (__SDIO_GET_FLAG(SDIOx, SDIO_FLAG_CCRCFAIL))
+  {
+    __SDIO_CLEAR_FLAG(SDIOx, SDIO_FLAG_CCRCFAIL);
+    
+    return SDMMC_ERROR_CMD_CRC_FAIL;
+  }
+  else
+  {
+    /* No error flag set */
+    /* Clear all the static flags */
+    __SDIO_CLEAR_FLAG(SDIOx, SDIO_STATIC_CMD_FLAGS);
+  }
+
+  return SDMMC_ERROR_NONE;
+}
+
+/**
+  * @brief  Checks for error conditions for R3 (OCR) response.
+  * @param  SDIOx Pointer to SDMMC register base
+  * @retval SD Card error state
+  */
+uint32_t SDMMC_GetCmdResp3(SDIO_TypeDef *SDIOx)
+{
+  uint32_t sta_reg;
+  /* 8 is the number of required instructions cycles for the below loop statement.
+  The SDIO_CMDTIMEOUT is expressed in ms */
+  uint32_t count = SDIO_CMDTIMEOUT * (SystemCoreClock / 8U /1000U);
+  
+  do
+  {
+    if (count-- == 0U)
+    {
+      return SDMMC_ERROR_TIMEOUT;
+    }
+    sta_reg = SDIOx->STA;
+  }while(((sta_reg & (SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT)) == 0U) ||
+         ((sta_reg & SDIO_FLAG_CMDACT) != 0U ));
+    
+  if(__SDIO_GET_FLAG(SDIOx, SDIO_FLAG_CTIMEOUT))
+  {
+    __SDIO_CLEAR_FLAG(SDIOx, SDIO_FLAG_CTIMEOUT);
+    
+    return SDMMC_ERROR_CMD_RSP_TIMEOUT;
+  }
+  else
+  {  
+    /* Clear all the static flags */
+    __SDIO_CLEAR_FLAG(SDIOx, SDIO_STATIC_CMD_FLAGS);
+  }
+  
+  return SDMMC_ERROR_NONE;
+}
+
+/**
+  * @brief  Checks for error conditions for R6 (RCA) response.
+  * @param  SDIOx Pointer to SDMMC register base
+  * @param  SD_CMD: The sent command index
+  * @param  pRCA: Pointer to the variable that will contain the SD card relative 
+  *         address RCA   
+  * @retval SD Card error state
+  */
+uint32_t SDMMC_GetCmdResp6(SDIO_TypeDef *SDIOx, uint8_t SD_CMD, uint16_t *pRCA)
+{
+  uint32_t response_r1;
+  uint32_t sta_reg;
+
+  /* 8 is the number of required instructions cycles for the below loop statement.
+  The SDIO_CMDTIMEOUT is expressed in ms */
+  uint32_t count = SDIO_CMDTIMEOUT * (SystemCoreClock / 8U /1000U);
+  
+  do
+  {
+    if (count-- == 0U)
+    {
+      return SDMMC_ERROR_TIMEOUT;
+    }
+    sta_reg = SDIOx->STA;
+  }while(((sta_reg & (SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT)) == 0U) ||
+         ((sta_reg & SDIO_FLAG_CMDACT) != 0U ));
+    
+  if(__SDIO_GET_FLAG(SDIOx, SDIO_FLAG_CTIMEOUT))
+  {
+    __SDIO_CLEAR_FLAG(SDIOx, SDIO_FLAG_CTIMEOUT);
+    
+    return SDMMC_ERROR_CMD_RSP_TIMEOUT;
+  }
+  else if(__SDIO_GET_FLAG(SDIOx, SDIO_FLAG_CCRCFAIL))
+  {
+    __SDIO_CLEAR_FLAG(SDIOx, SDIO_FLAG_CCRCFAIL);
+    
+    return SDMMC_ERROR_CMD_CRC_FAIL;
+  }
+  else
+  {
+    /* Nothing to do */
+  }
+  
+  /* Check response received is of desired command */
+  if(SDIO_GetCommandResponse(SDIOx) != SD_CMD)
+  {
+    return SDMMC_ERROR_CMD_CRC_FAIL;
+  }
+  
+  /* Clear all the static flags */
+  __SDIO_CLEAR_FLAG(SDIOx, SDIO_STATIC_CMD_FLAGS);
+  
+  /* We have received response, retrieve it.  */
+  response_r1 = SDIO_GetResponse(SDIOx, SDIO_RESP1);
+  
+  if((response_r1 & (SDMMC_R6_GENERAL_UNKNOWN_ERROR | SDMMC_R6_ILLEGAL_CMD | SDMMC_R6_COM_CRC_FAILED)) == SDMMC_ALLZERO)
+  {
+    *pRCA = (uint16_t) (response_r1 >> 16);
+    
+    return SDMMC_ERROR_NONE;
+  }
+  else if((response_r1 & SDMMC_R6_ILLEGAL_CMD) == SDMMC_R6_ILLEGAL_CMD)
+  {
+    return SDMMC_ERROR_ILLEGAL_CMD;
+  }
+  else if((response_r1 & SDMMC_R6_COM_CRC_FAILED) == SDMMC_R6_COM_CRC_FAILED)
+  {
+    return SDMMC_ERROR_COM_CRC_FAILED;
+  }
+  else
+  {
+    return SDMMC_ERROR_GENERAL_UNKNOWN_ERR;
+  }
+}
+
+/**
+  * @brief  Checks for error conditions for R7 response.
+  * @param  SDIOx Pointer to SDMMC register base
+  * @retval SD Card error state
+  */
+uint32_t SDMMC_GetCmdResp7(SDIO_TypeDef *SDIOx)
+{
+  uint32_t sta_reg;
+  /* 8 is the number of required instructions cycles for the below loop statement.
+  The SDIO_CMDTIMEOUT is expressed in ms */
+  uint32_t count = SDIO_CMDTIMEOUT * (SystemCoreClock / 8U /1000U);
+  
+  do
+  {
+    if (count-- == 0U)
+    {
+      return SDMMC_ERROR_TIMEOUT;
+    }
+    sta_reg = SDIOx->STA;
+  }while(((sta_reg & (SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT)) == 0U) ||
+         ((sta_reg & SDIO_FLAG_CMDACT) != 0U ));
+    
+  if(__SDIO_GET_FLAG(SDIOx, SDIO_FLAG_CTIMEOUT))
+  {
+    /* Card is SD V2.0 compliant */
+    __SDIO_CLEAR_FLAG(SDIOx, SDIO_FLAG_CTIMEOUT);
+    
+    return SDMMC_ERROR_CMD_RSP_TIMEOUT;
+  }
+  else if(__SDIO_GET_FLAG(SDIOx, SDIO_FLAG_CCRCFAIL))
+  {
+    /* Card is SD V2.0 compliant */
+    __SDIO_CLEAR_FLAG(SDIOx, SDIO_FLAG_CCRCFAIL);
+    
+    return SDMMC_ERROR_CMD_CRC_FAIL;
+  }
+  else
+  {
+    /* Nothing to do */
+  }
+  
+  if(__SDIO_GET_FLAG(SDIOx, SDIO_FLAG_CMDREND))
+  {
+    /* Card is SD V2.0 compliant */
+    __SDIO_CLEAR_FLAG(SDIOx, SDIO_FLAG_CMDREND);
+  }
+  
+  return SDMMC_ERROR_NONE;
+  
+}
+
+/**
+  * @}
+  */
+
+/* Private function ----------------------------------------------------------*/  
+/** @addtogroup SD_Private_Functions
+  * @{
+  */
+    
+/**
+  * @brief  Checks for error conditions for CMD0.
+  * @param  SDIOx Pointer to SDMMC register base
+  * @retval SD Card error state
+  */
+static uint32_t SDMMC_GetCmdError(SDIO_TypeDef *SDIOx)
+{
+  /* 8 is the number of required instructions cycles for the below loop statement.
+  The SDIO_CMDTIMEOUT is expressed in ms */
+  uint32_t count = SDIO_CMDTIMEOUT * (SystemCoreClock / 8U /1000U);
+  
+  do
+  {
+    if (count-- == 0U)
+    {
+      return SDMMC_ERROR_TIMEOUT;
+    }
+    
+  }while(!__SDIO_GET_FLAG(SDIOx, SDIO_FLAG_CMDSENT));
+  
+  /* Clear all the static flags */
+  __SDIO_CLEAR_FLAG(SDIOx, SDIO_STATIC_CMD_FLAGS);
+  
+  return SDMMC_ERROR_NONE;
+}
+
+
+/**
+  * @}
+  */
+
+#endif /* HAL_SD_MODULE_ENABLED || HAL_MMC_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* SDIO */
diff --git a/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c
new file mode 100644
index 0000000..fbd4bc0
--- /dev/null
+++ b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c
@@ -0,0 +1,2224 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_ll_usb.c
+  * @author  MCD Application Team
+  * @brief   USB Low Layer HAL module driver.
+  *
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the USB Peripheral Controller:
+  *           + Initialization/de-initialization functions
+  *           + I/O operation functions
+  *           + Peripheral Control functions
+  *           + Peripheral State functions
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2016 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  @verbatim
+  ==============================================================================
+                    ##### How to use this driver #####
+  ==============================================================================
+    [..]
+      (#) Fill parameters of Init structure in USB_OTG_CfgTypeDef structure.
+
+      (#) Call USB_CoreInit() API to initialize the USB Core peripheral.
+
+      (#) The upper HAL HCD/PCD driver will call the right routines for its internal processes.
+
+  @endverbatim
+
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal.h"
+
+/** @addtogroup STM32F4xx_LL_USB_DRIVER
+  * @{
+  */
+
+#if defined (HAL_PCD_MODULE_ENABLED) || defined (HAL_HCD_MODULE_ENABLED)
+#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
+static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx);
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup USB_LL_Exported_Functions USB Low Layer Exported Functions
+  * @{
+  */
+
+/** @defgroup USB_LL_Exported_Functions_Group1 Initialization/de-initialization functions
+  *  @brief    Initialization and Configuration functions
+  *
+@verbatim
+ ===============================================================================
+                      ##### Initialization/de-initialization functions #####
+ ===============================================================================
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initializes the USB Core
+  * @param  USBx USB Instance
+  * @param  cfg pointer to a USB_OTG_CfgTypeDef structure that contains
+  *         the configuration information for the specified USBx peripheral.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef USB_CoreInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg)
+{
+  HAL_StatusTypeDef ret;
+  if (cfg.phy_itface == USB_OTG_ULPI_PHY)
+  {
+    USBx->GCCFG &= ~(USB_OTG_GCCFG_PWRDWN);
+
+    /* Init The ULPI Interface */
+    USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_TSDPS | USB_OTG_GUSBCFG_ULPIFSLS | USB_OTG_GUSBCFG_PHYSEL);
+
+    /* Select vbus source */
+    USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_ULPIEVBUSD | USB_OTG_GUSBCFG_ULPIEVBUSI);
+    if (cfg.use_external_vbus == 1U)
+    {
+      USBx->GUSBCFG |= USB_OTG_GUSBCFG_ULPIEVBUSD;
+    }
+
+    /* Reset after a PHY select */
+    ret = USB_CoreReset(USBx);
+  }
+  else /* FS interface (embedded Phy) */
+  {
+    /* Select FS Embedded PHY */
+    USBx->GUSBCFG |= USB_OTG_GUSBCFG_PHYSEL;
+
+    /* Reset after a PHY select */
+    ret = USB_CoreReset(USBx);
+
+    if (cfg.battery_charging_enable == 0U)
+    {
+      /* Activate the USB Transceiver */
+      USBx->GCCFG |= USB_OTG_GCCFG_PWRDWN;
+    }
+    else
+    {
+      /* Deactivate the USB Transceiver */
+      USBx->GCCFG &= ~(USB_OTG_GCCFG_PWRDWN);
+    }
+  }
+
+  if (cfg.dma_enable == 1U)
+  {
+    USBx->GAHBCFG |= USB_OTG_GAHBCFG_HBSTLEN_2;
+    USBx->GAHBCFG |= USB_OTG_GAHBCFG_DMAEN;
+  }
+
+  return ret;
+}
+
+
+/**
+  * @brief  Set the USB turnaround time
+  * @param  USBx USB Instance
+  * @param  hclk: AHB clock frequency
+  * @retval USB turnaround time In PHY Clocks number
+  */
+HAL_StatusTypeDef USB_SetTurnaroundTime(USB_OTG_GlobalTypeDef *USBx,
+                                        uint32_t hclk, uint8_t speed)
+{
+  uint32_t UsbTrd;
+
+  /* The USBTRD is configured according to the tables below, depending on AHB frequency
+  used by application. In the low AHB frequency range it is used to stretch enough the USB response
+  time to IN tokens, the USB turnaround time, so to compensate for the longer AHB read access
+  latency to the Data FIFO */
+  if (speed == USBD_FS_SPEED)
+  {
+    if ((hclk >= 14200000U) && (hclk < 15000000U))
+    {
+      /* hclk Clock Range between 14.2-15 MHz */
+      UsbTrd = 0xFU;
+    }
+    else if ((hclk >= 15000000U) && (hclk < 16000000U))
+    {
+      /* hclk Clock Range between 15-16 MHz */
+      UsbTrd = 0xEU;
+    }
+    else if ((hclk >= 16000000U) && (hclk < 17200000U))
+    {
+      /* hclk Clock Range between 16-17.2 MHz */
+      UsbTrd = 0xDU;
+    }
+    else if ((hclk >= 17200000U) && (hclk < 18500000U))
+    {
+      /* hclk Clock Range between 17.2-18.5 MHz */
+      UsbTrd = 0xCU;
+    }
+    else if ((hclk >= 18500000U) && (hclk < 20000000U))
+    {
+      /* hclk Clock Range between 18.5-20 MHz */
+      UsbTrd = 0xBU;
+    }
+    else if ((hclk >= 20000000U) && (hclk < 21800000U))
+    {
+      /* hclk Clock Range between 20-21.8 MHz */
+      UsbTrd = 0xAU;
+    }
+    else if ((hclk >= 21800000U) && (hclk < 24000000U))
+    {
+      /* hclk Clock Range between 21.8-24 MHz */
+      UsbTrd = 0x9U;
+    }
+    else if ((hclk >= 24000000U) && (hclk < 27700000U))
+    {
+      /* hclk Clock Range between 24-27.7 MHz */
+      UsbTrd = 0x8U;
+    }
+    else if ((hclk >= 27700000U) && (hclk < 32000000U))
+    {
+      /* hclk Clock Range between 27.7-32 MHz */
+      UsbTrd = 0x7U;
+    }
+    else /* if(hclk >= 32000000) */
+    {
+      /* hclk Clock Range between 32-200 MHz */
+      UsbTrd = 0x6U;
+    }
+  }
+  else if (speed == USBD_HS_SPEED)
+  {
+    UsbTrd = USBD_HS_TRDT_VALUE;
+  }
+  else
+  {
+    UsbTrd = USBD_DEFAULT_TRDT_VALUE;
+  }
+
+  USBx->GUSBCFG &= ~USB_OTG_GUSBCFG_TRDT;
+  USBx->GUSBCFG |= (uint32_t)((UsbTrd << 10) & USB_OTG_GUSBCFG_TRDT);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  USB_EnableGlobalInt
+  *         Enables the controller's Global Int in the AHB Config reg
+  * @param  USBx  Selected device
+  * @retval HAL status
+  */
+HAL_StatusTypeDef USB_EnableGlobalInt(USB_OTG_GlobalTypeDef *USBx)
+{
+  USBx->GAHBCFG |= USB_OTG_GAHBCFG_GINT;
+  return HAL_OK;
+}
+
+/**
+  * @brief  USB_DisableGlobalInt
+  *         Disable the controller's Global Int in the AHB Config reg
+  * @param  USBx  Selected device
+  * @retval HAL status
+  */
+HAL_StatusTypeDef USB_DisableGlobalInt(USB_OTG_GlobalTypeDef *USBx)
+{
+  USBx->GAHBCFG &= ~USB_OTG_GAHBCFG_GINT;
+  return HAL_OK;
+}
+
+/**
+  * @brief  USB_SetCurrentMode Set functional mode
+  * @param  USBx  Selected device
+  * @param  mode  current core mode
+  *          This parameter can be one of these values:
+  *            @arg USB_DEVICE_MODE Peripheral mode
+  *            @arg USB_HOST_MODE Host mode
+  * @retval HAL status
+  */
+HAL_StatusTypeDef USB_SetCurrentMode(USB_OTG_GlobalTypeDef *USBx, USB_OTG_ModeTypeDef mode)
+{
+  uint32_t ms = 0U;
+
+  USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_FHMOD | USB_OTG_GUSBCFG_FDMOD);
+
+  if (mode == USB_HOST_MODE)
+  {
+    USBx->GUSBCFG |= USB_OTG_GUSBCFG_FHMOD;
+
+    do
+    {
+      HAL_Delay(1U);
+      ms++;
+    } while ((USB_GetMode(USBx) != (uint32_t)USB_HOST_MODE) && (ms < 50U));
+  }
+  else if (mode == USB_DEVICE_MODE)
+  {
+    USBx->GUSBCFG |= USB_OTG_GUSBCFG_FDMOD;
+
+    do
+    {
+      HAL_Delay(1U);
+      ms++;
+    } while ((USB_GetMode(USBx) != (uint32_t)USB_DEVICE_MODE) && (ms < 50U));
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  if (ms == 50U)
+  {
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  USB_DevInit Initializes the USB_OTG controller registers
+  *         for device mode
+  * @param  USBx  Selected device
+  * @param  cfg   pointer to a USB_OTG_CfgTypeDef structure that contains
+  *         the configuration information for the specified USBx peripheral.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef USB_DevInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg)
+{
+  HAL_StatusTypeDef ret = HAL_OK;
+  uint32_t USBx_BASE = (uint32_t)USBx;
+  uint32_t i;
+
+  for (i = 0U; i < 15U; i++)
+  {
+    USBx->DIEPTXF[i] = 0U;
+  }
+
+#if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
+  /* VBUS Sensing setup */
+  if (cfg.vbus_sensing_enable == 0U)
+  {
+    USBx_DEVICE->DCTL |= USB_OTG_DCTL_SDIS;
+
+    /* Deactivate VBUS Sensing B */
+    USBx->GCCFG &= ~USB_OTG_GCCFG_VBDEN;
+
+    /* B-peripheral session valid override enable */
+    USBx->GOTGCTL |= USB_OTG_GOTGCTL_BVALOEN;
+    USBx->GOTGCTL |= USB_OTG_GOTGCTL_BVALOVAL;
+  }
+  else
+  {
+    /* Enable HW VBUS sensing */
+    USBx->GCCFG |= USB_OTG_GCCFG_VBDEN;
+  }
+#else
+  /* VBUS Sensing setup */
+  if (cfg.vbus_sensing_enable == 0U)
+  {
+    /*
+     * Disable HW VBUS sensing. VBUS is internally considered to be always
+     * at VBUS-Valid level (5V).
+     */
+    USBx_DEVICE->DCTL |= USB_OTG_DCTL_SDIS;
+    USBx->GCCFG |= USB_OTG_GCCFG_NOVBUSSENS;
+    USBx->GCCFG &= ~USB_OTG_GCCFG_VBUSBSEN;
+    USBx->GCCFG &= ~USB_OTG_GCCFG_VBUSASEN;
+  }
+  else
+  {
+    /* Enable HW VBUS sensing */
+    USBx->GCCFG &= ~USB_OTG_GCCFG_NOVBUSSENS;
+    USBx->GCCFG |= USB_OTG_GCCFG_VBUSBSEN;
+  }
+#endif /* defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) */
+
+  /* Restart the Phy Clock */
+  USBx_PCGCCTL = 0U;
+
+  /* Device mode configuration */
+  USBx_DEVICE->DCFG |= DCFG_FRAME_INTERVAL_80;
+
+  if (cfg.phy_itface == USB_OTG_ULPI_PHY)
+  {
+    if (cfg.speed == USBD_HS_SPEED)
+    {
+      /* Set Core speed to High speed mode */
+      (void)USB_SetDevSpeed(USBx, USB_OTG_SPEED_HIGH);
+    }
+    else
+    {
+      /* Set Core speed to Full speed mode */
+      (void)USB_SetDevSpeed(USBx, USB_OTG_SPEED_HIGH_IN_FULL);
+    }
+  }
+  else
+  {
+    /* Set Core speed to Full speed mode */
+    (void)USB_SetDevSpeed(USBx, USB_OTG_SPEED_FULL);
+  }
+
+  /* Flush the FIFOs */
+  if (USB_FlushTxFifo(USBx, 0x10U) != HAL_OK) /* all Tx FIFOs */
+  {
+    ret = HAL_ERROR;
+  }
+
+  if (USB_FlushRxFifo(USBx) != HAL_OK)
+  {
+    ret = HAL_ERROR;
+  }
+
+  /* Clear all pending Device Interrupts */
+  USBx_DEVICE->DIEPMSK = 0U;
+  USBx_DEVICE->DOEPMSK = 0U;
+  USBx_DEVICE->DAINTMSK = 0U;
+
+  for (i = 0U; i < cfg.dev_endpoints; i++)
+  {
+    if ((USBx_INEP(i)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA)
+    {
+      if (i == 0U)
+      {
+        USBx_INEP(i)->DIEPCTL = USB_OTG_DIEPCTL_SNAK;
+      }
+      else
+      {
+        USBx_INEP(i)->DIEPCTL = USB_OTG_DIEPCTL_EPDIS | USB_OTG_DIEPCTL_SNAK;
+      }
+    }
+    else
+    {
+      USBx_INEP(i)->DIEPCTL = 0U;
+    }
+
+    USBx_INEP(i)->DIEPTSIZ = 0U;
+    USBx_INEP(i)->DIEPINT  = 0xFB7FU;
+  }
+
+  for (i = 0U; i < cfg.dev_endpoints; i++)
+  {
+    if ((USBx_OUTEP(i)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA)
+    {
+      if (i == 0U)
+      {
+        USBx_OUTEP(i)->DOEPCTL = USB_OTG_DOEPCTL_SNAK;
+      }
+      else
+      {
+        USBx_OUTEP(i)->DOEPCTL = USB_OTG_DOEPCTL_EPDIS | USB_OTG_DOEPCTL_SNAK;
+      }
+    }
+    else
+    {
+      USBx_OUTEP(i)->DOEPCTL = 0U;
+    }
+
+    USBx_OUTEP(i)->DOEPTSIZ = 0U;
+    USBx_OUTEP(i)->DOEPINT  = 0xFB7FU;
+  }
+
+  USBx_DEVICE->DIEPMSK &= ~(USB_OTG_DIEPMSK_TXFURM);
+
+  /* Disable all interrupts. */
+  USBx->GINTMSK = 0U;
+
+  /* Clear any pending interrupts */
+  USBx->GINTSTS = 0xBFFFFFFFU;
+
+  /* Enable the common interrupts */
+  if (cfg.dma_enable == 0U)
+  {
+    USBx->GINTMSK |= USB_OTG_GINTMSK_RXFLVLM;
+  }
+
+  /* Enable interrupts matching to the Device mode ONLY */
+  USBx->GINTMSK |= USB_OTG_GINTMSK_USBSUSPM | USB_OTG_GINTMSK_USBRST |
+                   USB_OTG_GINTMSK_ENUMDNEM | USB_OTG_GINTMSK_IEPINT |
+                   USB_OTG_GINTMSK_OEPINT   | USB_OTG_GINTMSK_IISOIXFRM |
+                   USB_OTG_GINTMSK_PXFRM_IISOOXFRM | USB_OTG_GINTMSK_WUIM;
+
+  if (cfg.Sof_enable != 0U)
+  {
+    USBx->GINTMSK |= USB_OTG_GINTMSK_SOFM;
+  }
+
+  if (cfg.vbus_sensing_enable == 1U)
+  {
+    USBx->GINTMSK |= (USB_OTG_GINTMSK_SRQIM | USB_OTG_GINTMSK_OTGINT);
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  USB_FlushTxFifo Flush a Tx FIFO
+  * @param  USBx  Selected device
+  * @param  num  FIFO number
+  *         This parameter can be a value from 1 to 15
+            15 means Flush all Tx FIFOs
+  * @retval HAL status
+  */
+HAL_StatusTypeDef USB_FlushTxFifo(USB_OTG_GlobalTypeDef *USBx, uint32_t num)
+{
+  __IO uint32_t count = 0U;
+
+  /* Wait for AHB master IDLE state. */
+  do
+  {
+    count++;
+
+    if (count > 200000U)
+    {
+      return HAL_TIMEOUT;
+    }
+  } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U);
+
+  /* Flush TX Fifo */
+  count = 0U;
+  USBx->GRSTCTL = (USB_OTG_GRSTCTL_TXFFLSH | (num << 6));
+
+  do
+  {
+    count++;
+
+    if (count > 200000U)
+    {
+      return HAL_TIMEOUT;
+    }
+  } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_TXFFLSH) == USB_OTG_GRSTCTL_TXFFLSH);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  USB_FlushRxFifo  Flush Rx FIFO
+  * @param  USBx  Selected device
+  * @retval HAL status
+  */
+HAL_StatusTypeDef USB_FlushRxFifo(USB_OTG_GlobalTypeDef *USBx)
+{
+  __IO uint32_t count = 0U;
+
+  /* Wait for AHB master IDLE state. */
+  do
+  {
+    count++;
+
+    if (count > 200000U)
+    {
+      return HAL_TIMEOUT;
+    }
+  } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U);
+
+  /* Flush RX Fifo */
+  count = 0U;
+  USBx->GRSTCTL = USB_OTG_GRSTCTL_RXFFLSH;
+
+  do
+  {
+    count++;
+
+    if (count > 200000U)
+    {
+      return HAL_TIMEOUT;
+    }
+  } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_RXFFLSH) == USB_OTG_GRSTCTL_RXFFLSH);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  USB_SetDevSpeed  Initializes the DevSpd field of DCFG register
+  *         depending the PHY type and the enumeration speed of the device.
+  * @param  USBx  Selected device
+  * @param  speed  device speed
+  *          This parameter can be one of these values:
+  *            @arg USB_OTG_SPEED_HIGH: High speed mode
+  *            @arg USB_OTG_SPEED_HIGH_IN_FULL: High speed core in Full Speed mode
+  *            @arg USB_OTG_SPEED_FULL: Full speed mode
+  * @retval  Hal status
+  */
+HAL_StatusTypeDef USB_SetDevSpeed(USB_OTG_GlobalTypeDef *USBx, uint8_t speed)
+{
+  uint32_t USBx_BASE = (uint32_t)USBx;
+
+  USBx_DEVICE->DCFG |= speed;
+  return HAL_OK;
+}
+
+/**
+  * @brief  USB_GetDevSpeed  Return the Dev Speed
+  * @param  USBx  Selected device
+  * @retval speed  device speed
+  *          This parameter can be one of these values:
+  *            @arg USBD_HS_SPEED: High speed mode
+  *            @arg USBD_FS_SPEED: Full speed mode
+  */
+uint8_t USB_GetDevSpeed(USB_OTG_GlobalTypeDef *USBx)
+{
+  uint32_t USBx_BASE = (uint32_t)USBx;
+  uint8_t speed;
+  uint32_t DevEnumSpeed = USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD;
+
+  if (DevEnumSpeed == DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ)
+  {
+    speed = USBD_HS_SPEED;
+  }
+  else if ((DevEnumSpeed == DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ) ||
+           (DevEnumSpeed == DSTS_ENUMSPD_FS_PHY_48MHZ))
+  {
+    speed = USBD_FS_SPEED;
+  }
+  else
+  {
+    speed = 0xFU;
+  }
+
+  return speed;
+}
+
+/**
+  * @brief  Activate and configure an endpoint
+  * @param  USBx  Selected device
+  * @param  ep pointer to endpoint structure
+  * @retval HAL status
+  */
+HAL_StatusTypeDef USB_ActivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)
+{
+  uint32_t USBx_BASE = (uint32_t)USBx;
+  uint32_t epnum = (uint32_t)ep->num;
+
+  if (ep->is_in == 1U)
+  {
+    USBx_DEVICE->DAINTMSK |= USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK));
+
+    if ((USBx_INEP(epnum)->DIEPCTL & USB_OTG_DIEPCTL_USBAEP) == 0U)
+    {
+      USBx_INEP(epnum)->DIEPCTL |= (ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ) |
+                                   ((uint32_t)ep->type << 18) | (epnum << 22) |
+                                   USB_OTG_DIEPCTL_SD0PID_SEVNFRM |
+                                   USB_OTG_DIEPCTL_USBAEP;
+    }
+  }
+  else
+  {
+    USBx_DEVICE->DAINTMSK |= USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16);
+
+    if (((USBx_OUTEP(epnum)->DOEPCTL) & USB_OTG_DOEPCTL_USBAEP) == 0U)
+    {
+      USBx_OUTEP(epnum)->DOEPCTL |= (ep->maxpacket & USB_OTG_DOEPCTL_MPSIZ) |
+                                    ((uint32_t)ep->type << 18) |
+                                    USB_OTG_DIEPCTL_SD0PID_SEVNFRM |
+                                    USB_OTG_DOEPCTL_USBAEP;
+    }
+  }
+  return HAL_OK;
+}
+
+/**
+  * @brief  Activate and configure a dedicated endpoint
+  * @param  USBx  Selected device
+  * @param  ep pointer to endpoint structure
+  * @retval HAL status
+  */
+HAL_StatusTypeDef USB_ActivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)
+{
+  uint32_t USBx_BASE = (uint32_t)USBx;
+  uint32_t epnum = (uint32_t)ep->num;
+
+  /* Read DEPCTLn register */
+  if (ep->is_in == 1U)
+  {
+    if (((USBx_INEP(epnum)->DIEPCTL) & USB_OTG_DIEPCTL_USBAEP) == 0U)
+    {
+      USBx_INEP(epnum)->DIEPCTL |= (ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ) |
+                                   ((uint32_t)ep->type << 18) | (epnum << 22) |
+                                   USB_OTG_DIEPCTL_SD0PID_SEVNFRM |
+                                   USB_OTG_DIEPCTL_USBAEP;
+    }
+
+    USBx_DEVICE->DEACHMSK |= USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK));
+  }
+  else
+  {
+    if (((USBx_OUTEP(epnum)->DOEPCTL) & USB_OTG_DOEPCTL_USBAEP) == 0U)
+    {
+      USBx_OUTEP(epnum)->DOEPCTL |= (ep->maxpacket & USB_OTG_DOEPCTL_MPSIZ) |
+                                    ((uint32_t)ep->type << 18) | (epnum << 22) |
+                                    USB_OTG_DOEPCTL_USBAEP;
+    }
+
+    USBx_DEVICE->DEACHMSK |= USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16);
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  De-activate and de-initialize an endpoint
+  * @param  USBx  Selected device
+  * @param  ep pointer to endpoint structure
+  * @retval HAL status
+  */
+HAL_StatusTypeDef USB_DeactivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)
+{
+  uint32_t USBx_BASE = (uint32_t)USBx;
+  uint32_t epnum = (uint32_t)ep->num;
+
+  /* Read DEPCTLn register */
+  if (ep->is_in == 1U)
+  {
+    if ((USBx_INEP(epnum)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA)
+    {
+      USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SNAK;
+      USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_EPDIS;
+    }
+
+    USBx_DEVICE->DEACHMSK &= ~(USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK)));
+    USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK)));
+    USBx_INEP(epnum)->DIEPCTL &= ~(USB_OTG_DIEPCTL_USBAEP |
+                                   USB_OTG_DIEPCTL_MPSIZ |
+                                   USB_OTG_DIEPCTL_TXFNUM |
+                                   USB_OTG_DIEPCTL_SD0PID_SEVNFRM |
+                                   USB_OTG_DIEPCTL_EPTYP);
+  }
+  else
+  {
+    if ((USBx_OUTEP(epnum)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA)
+    {
+      USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SNAK;
+      USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_EPDIS;
+    }
+
+    USBx_DEVICE->DEACHMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16));
+    USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16));
+    USBx_OUTEP(epnum)->DOEPCTL &= ~(USB_OTG_DOEPCTL_USBAEP |
+                                    USB_OTG_DOEPCTL_MPSIZ |
+                                    USB_OTG_DOEPCTL_SD0PID_SEVNFRM |
+                                    USB_OTG_DOEPCTL_EPTYP);
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  De-activate and de-initialize a dedicated endpoint
+  * @param  USBx  Selected device
+  * @param  ep pointer to endpoint structure
+  * @retval HAL status
+  */
+HAL_StatusTypeDef USB_DeactivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)
+{
+  uint32_t USBx_BASE = (uint32_t)USBx;
+  uint32_t epnum = (uint32_t)ep->num;
+
+  /* Read DEPCTLn register */
+  if (ep->is_in == 1U)
+  {
+    if ((USBx_INEP(epnum)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA)
+    {
+      USBx_INEP(epnum)->DIEPCTL  |= USB_OTG_DIEPCTL_SNAK;
+      USBx_INEP(epnum)->DIEPCTL  |= USB_OTG_DIEPCTL_EPDIS;
+    }
+
+    USBx_INEP(epnum)->DIEPCTL &= ~ USB_OTG_DIEPCTL_USBAEP;
+    USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK)));
+  }
+  else
+  {
+    if ((USBx_OUTEP(epnum)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA)
+    {
+      USBx_OUTEP(epnum)->DOEPCTL  |= USB_OTG_DOEPCTL_SNAK;
+      USBx_OUTEP(epnum)->DOEPCTL  |= USB_OTG_DOEPCTL_EPDIS;
+    }
+
+    USBx_OUTEP(epnum)->DOEPCTL &= ~USB_OTG_DOEPCTL_USBAEP;
+    USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16));
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  USB_EPStartXfer : setup and starts a transfer over an EP
+  * @param  USBx  Selected device
+  * @param  ep pointer to endpoint structure
+  * @param  dma USB dma enabled or disabled
+  *          This parameter can be one of these values:
+  *           0 : DMA feature not used
+  *           1 : DMA feature used
+  * @retval HAL status
+  */
+HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep, uint8_t dma)
+{
+  uint32_t USBx_BASE = (uint32_t)USBx;
+  uint32_t epnum = (uint32_t)ep->num;
+  uint16_t pktcnt;
+
+  /* IN endpoint */
+  if (ep->is_in == 1U)
+  {
+    /* Zero Length Packet? */
+    if (ep->xfer_len == 0U)
+    {
+      USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT);
+      USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1U << 19));
+      USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ);
+    }
+    else
+    {
+      /* Program the transfer size and packet count
+      * as follows: xfersize = N * maxpacket +
+      * short_packet pktcnt = N + (short_packet
+      * exist ? 1 : 0)
+      */
+      USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ);
+      USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT);
+      USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT &
+                                     (((ep->xfer_len + ep->maxpacket - 1U) / ep->maxpacket) << 19));
+
+      USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_XFRSIZ & ep->xfer_len);
+
+      if (ep->type == EP_TYPE_ISOC)
+      {
+        USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_MULCNT);
+        USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_MULCNT & (1U << 29));
+      }
+    }
+
+    if (dma == 1U)
+    {
+      if ((uint32_t)ep->dma_addr != 0U)
+      {
+        USBx_INEP(epnum)->DIEPDMA = (uint32_t)(ep->dma_addr);
+      }
+
+      if (ep->type == EP_TYPE_ISOC)
+      {
+        if ((USBx_DEVICE->DSTS & (1U << 8)) == 0U)
+        {
+          USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SODDFRM;
+        }
+        else
+        {
+          USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM;
+        }
+      }
+
+      /* EP enable, IN data in FIFO */
+      USBx_INEP(epnum)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA);
+    }
+    else
+    {
+      /* EP enable, IN data in FIFO */
+      USBx_INEP(epnum)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA);
+
+      if (ep->type != EP_TYPE_ISOC)
+      {
+        /* Enable the Tx FIFO Empty Interrupt for this EP */
+        if (ep->xfer_len > 0U)
+        {
+          USBx_DEVICE->DIEPEMPMSK |= 1UL << (ep->num & EP_ADDR_MSK);
+        }
+      }
+      else
+      {
+        if ((USBx_DEVICE->DSTS & (1U << 8)) == 0U)
+        {
+          USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SODDFRM;
+        }
+        else
+        {
+          USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM;
+        }
+
+        (void)USB_WritePacket(USBx, ep->xfer_buff, ep->num, (uint16_t)ep->xfer_len, dma);
+      }
+    }
+  }
+  else /* OUT endpoint */
+  {
+    /* Program the transfer size and packet count as follows:
+    * pktcnt = N
+    * xfersize = N * maxpacket
+    */
+    USBx_OUTEP(epnum)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_XFRSIZ);
+    USBx_OUTEP(epnum)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_PKTCNT);
+
+    if (ep->xfer_len == 0U)
+    {
+      USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & ep->maxpacket);
+      USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19));
+    }
+    else
+    {
+      pktcnt = (uint16_t)((ep->xfer_len + ep->maxpacket - 1U) / ep->maxpacket);
+      ep->xfer_size = ep->maxpacket * pktcnt;
+
+      USBx_OUTEP(epnum)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_PKTCNT & ((uint32_t)pktcnt << 19);
+      USBx_OUTEP(epnum)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_XFRSIZ & ep->xfer_size;
+    }
+
+    if (dma == 1U)
+    {
+      if ((uint32_t)ep->xfer_buff != 0U)
+      {
+        USBx_OUTEP(epnum)->DOEPDMA = (uint32_t)(ep->xfer_buff);
+      }
+    }
+
+    if (ep->type == EP_TYPE_ISOC)
+    {
+      if ((USBx_DEVICE->DSTS & (1U << 8)) == 0U)
+      {
+        USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SODDFRM;
+      }
+      else
+      {
+        USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SD0PID_SEVNFRM;
+      }
+    }
+    /* EP enable */
+    USBx_OUTEP(epnum)->DOEPCTL |= (USB_OTG_DOEPCTL_CNAK | USB_OTG_DOEPCTL_EPENA);
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  USB_EP0StartXfer : setup and starts a transfer over the EP  0
+  * @param  USBx  Selected device
+  * @param  ep pointer to endpoint structure
+  * @param  dma USB dma enabled or disabled
+  *          This parameter can be one of these values:
+  *           0 : DMA feature not used
+  *           1 : DMA feature used
+  * @retval HAL status
+  */
+HAL_StatusTypeDef USB_EP0StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep, uint8_t dma)
+{
+  uint32_t USBx_BASE = (uint32_t)USBx;
+  uint32_t epnum = (uint32_t)ep->num;
+
+  /* IN endpoint */
+  if (ep->is_in == 1U)
+  {
+    /* Zero Length Packet? */
+    if (ep->xfer_len == 0U)
+    {
+      USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT);
+      USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1U << 19));
+      USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ);
+    }
+    else
+    {
+      /* Program the transfer size and packet count
+      * as follows: xfersize = N * maxpacket +
+      * short_packet pktcnt = N + (short_packet
+      * exist ? 1 : 0)
+      */
+      USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ);
+      USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT);
+
+      if (ep->xfer_len > ep->maxpacket)
+      {
+        ep->xfer_len = ep->maxpacket;
+      }
+      USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1U << 19));
+      USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_XFRSIZ & ep->xfer_len);
+    }
+
+    if (dma == 1U)
+    {
+      if ((uint32_t)ep->dma_addr != 0U)
+      {
+        USBx_INEP(epnum)->DIEPDMA = (uint32_t)(ep->dma_addr);
+      }
+
+      /* EP enable, IN data in FIFO */
+      USBx_INEP(epnum)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA);
+    }
+    else
+    {
+      /* EP enable, IN data in FIFO */
+      USBx_INEP(epnum)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA);
+
+      /* Enable the Tx FIFO Empty Interrupt for this EP */
+      if (ep->xfer_len > 0U)
+      {
+        USBx_DEVICE->DIEPEMPMSK |= 1UL << (ep->num & EP_ADDR_MSK);
+      }
+    }
+  }
+  else /* OUT endpoint */
+  {
+    /* Program the transfer size and packet count as follows:
+    * pktcnt = N
+    * xfersize = N * maxpacket
+    */
+    USBx_OUTEP(epnum)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_XFRSIZ);
+    USBx_OUTEP(epnum)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_PKTCNT);
+
+    if (ep->xfer_len > 0U)
+    {
+      ep->xfer_len = ep->maxpacket;
+    }
+
+    /* Store transfer size, for EP0 this is equal to endpoint max packet size */
+    ep->xfer_size = ep->maxpacket;
+
+    USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19));
+    USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & ep->xfer_size);
+
+    if (dma == 1U)
+    {
+      if ((uint32_t)ep->xfer_buff != 0U)
+      {
+        USBx_OUTEP(epnum)->DOEPDMA = (uint32_t)(ep->xfer_buff);
+      }
+    }
+
+    /* EP enable */
+    USBx_OUTEP(epnum)->DOEPCTL |= (USB_OTG_DOEPCTL_CNAK | USB_OTG_DOEPCTL_EPENA);
+  }
+
+  return HAL_OK;
+}
+
+
+/**
+   * @brief  USB_EPStoptXfer  Stop transfer on an EP
+   * @param  USBx  usb device instance
+   * @param  ep pointer to endpoint structure
+   * @retval HAL status
+   */
+HAL_StatusTypeDef USB_EPStopXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)
+{
+  __IO uint32_t count = 0U;
+  HAL_StatusTypeDef ret = HAL_OK;
+  uint32_t USBx_BASE = (uint32_t)USBx;
+
+  /* IN endpoint */
+  if (ep->is_in == 1U)
+  {
+    /* EP enable, IN data in FIFO */
+    if (((USBx_INEP(ep->num)->DIEPCTL) & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA)
+    {
+      USBx_INEP(ep->num)->DIEPCTL |= (USB_OTG_DIEPCTL_SNAK);
+      USBx_INEP(ep->num)->DIEPCTL |= (USB_OTG_DIEPCTL_EPDIS);
+
+      do
+      {
+        count++;
+
+        if (count > 10000U)
+        {
+          ret = HAL_ERROR;
+          break;
+        }
+      } while (((USBx_INEP(ep->num)->DIEPCTL) & USB_OTG_DIEPCTL_EPENA) ==  USB_OTG_DIEPCTL_EPENA);
+    }
+  }
+  else /* OUT endpoint */
+  {
+    if (((USBx_OUTEP(ep->num)->DOEPCTL) & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA)
+    {
+      USBx_OUTEP(ep->num)->DOEPCTL |= (USB_OTG_DOEPCTL_SNAK);
+      USBx_OUTEP(ep->num)->DOEPCTL |= (USB_OTG_DOEPCTL_EPDIS);
+
+      do
+      {
+        count++;
+
+        if (count > 10000U)
+        {
+          ret = HAL_ERROR;
+          break;
+        }
+      } while (((USBx_OUTEP(ep->num)->DOEPCTL) & USB_OTG_DOEPCTL_EPENA) ==  USB_OTG_DOEPCTL_EPENA);
+    }
+  }
+
+  return ret;
+}
+
+
+/**
+  * @brief  USB_WritePacket : Writes a packet into the Tx FIFO associated
+  *         with the EP/channel
+  * @param  USBx  Selected device
+  * @param  src   pointer to source buffer
+  * @param  ch_ep_num  endpoint or host channel number
+  * @param  len  Number of bytes to write
+  * @param  dma USB dma enabled or disabled
+  *          This parameter can be one of these values:
+  *           0 : DMA feature not used
+  *           1 : DMA feature used
+  * @retval HAL status
+  */
+HAL_StatusTypeDef USB_WritePacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *src,
+                                  uint8_t ch_ep_num, uint16_t len, uint8_t dma)
+{
+  uint32_t USBx_BASE = (uint32_t)USBx;
+  uint8_t *pSrc = src;
+  uint32_t count32b;
+  uint32_t i;
+
+  if (dma == 0U)
+  {
+    count32b = ((uint32_t)len + 3U) / 4U;
+    for (i = 0U; i < count32b; i++)
+    {
+      USBx_DFIFO((uint32_t)ch_ep_num) = __UNALIGNED_UINT32_READ(pSrc);
+      pSrc++;
+      pSrc++;
+      pSrc++;
+      pSrc++;
+    }
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  USB_ReadPacket : read a packet from the RX FIFO
+  * @param  USBx  Selected device
+  * @param  dest  source pointer
+  * @param  len  Number of bytes to read
+  * @retval pointer to destination buffer
+  */
+void *USB_ReadPacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len)
+{
+  uint32_t USBx_BASE = (uint32_t)USBx;
+  uint8_t *pDest = dest;
+  uint32_t pData;
+  uint32_t i;
+  uint32_t count32b = (uint32_t)len >> 2U;
+  uint16_t remaining_bytes = len % 4U;
+
+  for (i = 0U; i < count32b; i++)
+  {
+    __UNALIGNED_UINT32_WRITE(pDest, USBx_DFIFO(0U));
+    pDest++;
+    pDest++;
+    pDest++;
+    pDest++;
+  }
+
+  /* When Number of data is not word aligned, read the remaining byte */
+  if (remaining_bytes != 0U)
+  {
+    i = 0U;
+    __UNALIGNED_UINT32_WRITE(&pData, USBx_DFIFO(0U));
+
+    do
+    {
+      *(uint8_t *)pDest = (uint8_t)(pData >> (8U * (uint8_t)(i)));
+      i++;
+      pDest++;
+      remaining_bytes--;
+    } while (remaining_bytes != 0U);
+  }
+
+  return ((void *)pDest);
+}
+
+/**
+  * @brief  USB_EPSetStall : set a stall condition over an EP
+  * @param  USBx  Selected device
+  * @param  ep pointer to endpoint structure
+  * @retval HAL status
+  */
+HAL_StatusTypeDef USB_EPSetStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)
+{
+  uint32_t USBx_BASE = (uint32_t)USBx;
+  uint32_t epnum = (uint32_t)ep->num;
+
+  if (ep->is_in == 1U)
+  {
+    if (((USBx_INEP(epnum)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == 0U) && (epnum != 0U))
+    {
+      USBx_INEP(epnum)->DIEPCTL &= ~(USB_OTG_DIEPCTL_EPDIS);
+    }
+    USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_STALL;
+  }
+  else
+  {
+    if (((USBx_OUTEP(epnum)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == 0U) && (epnum != 0U))
+    {
+      USBx_OUTEP(epnum)->DOEPCTL &= ~(USB_OTG_DOEPCTL_EPDIS);
+    }
+    USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_STALL;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  USB_EPClearStall : Clear a stall condition over an EP
+  * @param  USBx  Selected device
+  * @param  ep pointer to endpoint structure
+  * @retval HAL status
+  */
+HAL_StatusTypeDef USB_EPClearStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)
+{
+  uint32_t USBx_BASE = (uint32_t)USBx;
+  uint32_t epnum = (uint32_t)ep->num;
+
+  if (ep->is_in == 1U)
+  {
+    USBx_INEP(epnum)->DIEPCTL &= ~USB_OTG_DIEPCTL_STALL;
+    if ((ep->type == EP_TYPE_INTR) || (ep->type == EP_TYPE_BULK))
+    {
+      USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM; /* DATA0 */
+    }
+  }
+  else
+  {
+    USBx_OUTEP(epnum)->DOEPCTL &= ~USB_OTG_DOEPCTL_STALL;
+    if ((ep->type == EP_TYPE_INTR) || (ep->type == EP_TYPE_BULK))
+    {
+      USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SD0PID_SEVNFRM; /* DATA0 */
+    }
+  }
+  return HAL_OK;
+}
+
+/**
+  * @brief  USB_StopDevice : Stop the usb device mode
+  * @param  USBx  Selected device
+  * @retval HAL status
+  */
+HAL_StatusTypeDef USB_StopDevice(USB_OTG_GlobalTypeDef *USBx)
+{
+  HAL_StatusTypeDef ret;
+  uint32_t USBx_BASE = (uint32_t)USBx;
+  uint32_t i;
+
+  /* Clear Pending interrupt */
+  for (i = 0U; i < 15U; i++)
+  {
+    USBx_INEP(i)->DIEPINT = 0xFB7FU;
+    USBx_OUTEP(i)->DOEPINT = 0xFB7FU;
+  }
+
+  /* Clear interrupt masks */
+  USBx_DEVICE->DIEPMSK  = 0U;
+  USBx_DEVICE->DOEPMSK  = 0U;
+  USBx_DEVICE->DAINTMSK = 0U;
+
+  /* Flush the FIFO */
+  ret = USB_FlushRxFifo(USBx);
+  if (ret != HAL_OK)
+  {
+    return ret;
+  }
+
+  ret = USB_FlushTxFifo(USBx,  0x10U);
+  if (ret != HAL_OK)
+  {
+    return ret;
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  USB_SetDevAddress : Stop the usb device mode
+  * @param  USBx  Selected device
+  * @param  address  new device address to be assigned
+  *          This parameter can be a value from 0 to 255
+  * @retval HAL status
+  */
+HAL_StatusTypeDef  USB_SetDevAddress(USB_OTG_GlobalTypeDef *USBx, uint8_t address)
+{
+  uint32_t USBx_BASE = (uint32_t)USBx;
+
+  USBx_DEVICE->DCFG &= ~(USB_OTG_DCFG_DAD);
+  USBx_DEVICE->DCFG |= ((uint32_t)address << 4) & USB_OTG_DCFG_DAD;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  USB_DevConnect : Connect the USB device by enabling Rpu
+  * @param  USBx  Selected device
+  * @retval HAL status
+  */
+HAL_StatusTypeDef  USB_DevConnect(USB_OTG_GlobalTypeDef *USBx)
+{
+  uint32_t USBx_BASE = (uint32_t)USBx;
+
+  /* In case phy is stopped, ensure to ungate and restore the phy CLK */
+  USBx_PCGCCTL &= ~(USB_OTG_PCGCCTL_STOPCLK | USB_OTG_PCGCCTL_GATECLK);
+
+  USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_SDIS;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  USB_DevDisconnect : Disconnect the USB device by disabling Rpu
+  * @param  USBx  Selected device
+  * @retval HAL status
+  */
+HAL_StatusTypeDef  USB_DevDisconnect(USB_OTG_GlobalTypeDef *USBx)
+{
+  uint32_t USBx_BASE = (uint32_t)USBx;
+
+  /* In case phy is stopped, ensure to ungate and restore the phy CLK */
+  USBx_PCGCCTL &= ~(USB_OTG_PCGCCTL_STOPCLK | USB_OTG_PCGCCTL_GATECLK);
+
+  USBx_DEVICE->DCTL |= USB_OTG_DCTL_SDIS;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  USB_ReadInterrupts: return the global USB interrupt status
+  * @param  USBx  Selected device
+  * @retval HAL status
+  */
+uint32_t  USB_ReadInterrupts(USB_OTG_GlobalTypeDef *USBx)
+{
+  uint32_t tmpreg;
+
+  tmpreg = USBx->GINTSTS;
+  tmpreg &= USBx->GINTMSK;
+
+  return tmpreg;
+}
+
+/**
+  * @brief  USB_ReadDevAllOutEpInterrupt: return the USB device OUT endpoints interrupt status
+  * @param  USBx  Selected device
+  * @retval HAL status
+  */
+uint32_t USB_ReadDevAllOutEpInterrupt(USB_OTG_GlobalTypeDef *USBx)
+{
+  uint32_t USBx_BASE = (uint32_t)USBx;
+  uint32_t tmpreg;
+
+  tmpreg  = USBx_DEVICE->DAINT;
+  tmpreg &= USBx_DEVICE->DAINTMSK;
+
+  return ((tmpreg & 0xffff0000U) >> 16);
+}
+
+/**
+  * @brief  USB_ReadDevAllInEpInterrupt: return the USB device IN endpoints interrupt status
+  * @param  USBx  Selected device
+  * @retval HAL status
+  */
+uint32_t USB_ReadDevAllInEpInterrupt(USB_OTG_GlobalTypeDef *USBx)
+{
+  uint32_t USBx_BASE = (uint32_t)USBx;
+  uint32_t tmpreg;
+
+  tmpreg  = USBx_DEVICE->DAINT;
+  tmpreg &= USBx_DEVICE->DAINTMSK;
+
+  return ((tmpreg & 0xFFFFU));
+}
+
+/**
+  * @brief  Returns Device OUT EP Interrupt register
+  * @param  USBx  Selected device
+  * @param  epnum  endpoint number
+  *          This parameter can be a value from 0 to 15
+  * @retval Device OUT EP Interrupt register
+  */
+uint32_t USB_ReadDevOutEPInterrupt(USB_OTG_GlobalTypeDef *USBx, uint8_t epnum)
+{
+  uint32_t USBx_BASE = (uint32_t)USBx;
+  uint32_t tmpreg;
+
+  tmpreg  = USBx_OUTEP((uint32_t)epnum)->DOEPINT;
+  tmpreg &= USBx_DEVICE->DOEPMSK;
+
+  return tmpreg;
+}
+
+/**
+  * @brief  Returns Device IN EP Interrupt register
+  * @param  USBx  Selected device
+  * @param  epnum  endpoint number
+  *          This parameter can be a value from 0 to 15
+  * @retval Device IN EP Interrupt register
+  */
+uint32_t USB_ReadDevInEPInterrupt(USB_OTG_GlobalTypeDef *USBx, uint8_t epnum)
+{
+  uint32_t USBx_BASE = (uint32_t)USBx;
+  uint32_t tmpreg;
+  uint32_t msk;
+  uint32_t emp;
+
+  msk = USBx_DEVICE->DIEPMSK;
+  emp = USBx_DEVICE->DIEPEMPMSK;
+  msk |= ((emp >> (epnum & EP_ADDR_MSK)) & 0x1U) << 7;
+  tmpreg = USBx_INEP((uint32_t)epnum)->DIEPINT & msk;
+
+  return tmpreg;
+}
+
+/**
+  * @brief  USB_ClearInterrupts: clear a USB interrupt
+  * @param  USBx  Selected device
+  * @param  interrupt  flag
+  * @retval None
+  */
+void  USB_ClearInterrupts(USB_OTG_GlobalTypeDef *USBx, uint32_t interrupt)
+{
+  USBx->GINTSTS |= interrupt;
+}
+
+/**
+  * @brief  Returns USB core mode
+  * @param  USBx  Selected device
+  * @retval return core mode : Host or Device
+  *          This parameter can be one of these values:
+  *           0 : Host
+  *           1 : Device
+  */
+uint32_t USB_GetMode(USB_OTG_GlobalTypeDef *USBx)
+{
+  return ((USBx->GINTSTS) & 0x1U);
+}
+
+/**
+  * @brief  Activate EP0 for Setup transactions
+  * @param  USBx  Selected device
+  * @retval HAL status
+  */
+HAL_StatusTypeDef  USB_ActivateSetup(USB_OTG_GlobalTypeDef *USBx)
+{
+  uint32_t USBx_BASE = (uint32_t)USBx;
+
+  /* Set the MPS of the IN EP0 to 64 bytes */
+  USBx_INEP(0U)->DIEPCTL &= ~USB_OTG_DIEPCTL_MPSIZ;
+
+  USBx_DEVICE->DCTL |= USB_OTG_DCTL_CGINAK;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Prepare the EP0 to start the first control setup
+  * @param  USBx  Selected device
+  * @param  dma USB dma enabled or disabled
+  *          This parameter can be one of these values:
+  *           0 : DMA feature not used
+  *           1 : DMA feature used
+  * @param  psetup  pointer to setup packet
+  * @retval HAL status
+  */
+HAL_StatusTypeDef USB_EP0_OutStart(USB_OTG_GlobalTypeDef *USBx, uint8_t dma, uint8_t *psetup)
+{
+  uint32_t USBx_BASE = (uint32_t)USBx;
+  uint32_t gSNPSiD = *(__IO uint32_t *)(&USBx->CID + 0x1U);
+
+  if (gSNPSiD > USB_OTG_CORE_ID_300A)
+  {
+    if ((USBx_OUTEP(0U)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA)
+    {
+      return HAL_OK;
+    }
+  }
+
+  USBx_OUTEP(0U)->DOEPTSIZ = 0U;
+  USBx_OUTEP(0U)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19));
+  USBx_OUTEP(0U)->DOEPTSIZ |= (3U * 8U);
+  USBx_OUTEP(0U)->DOEPTSIZ |=  USB_OTG_DOEPTSIZ_STUPCNT;
+
+  if (dma == 1U)
+  {
+    USBx_OUTEP(0U)->DOEPDMA = (uint32_t)psetup;
+    /* EP enable */
+    USBx_OUTEP(0U)->DOEPCTL |= USB_OTG_DOEPCTL_EPENA | USB_OTG_DOEPCTL_USBAEP;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Reset the USB Core (needed after USB clock settings change)
+  * @param  USBx  Selected device
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx)
+{
+  __IO uint32_t count = 0U;
+
+  /* Wait for AHB master IDLE state. */
+  do
+  {
+    count++;
+
+    if (count > 200000U)
+    {
+      return HAL_TIMEOUT;
+    }
+  } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U);
+
+  /* Core Soft Reset */
+  count = 0U;
+  USBx->GRSTCTL |= USB_OTG_GRSTCTL_CSRST;
+
+  do
+  {
+    count++;
+
+    if (count > 200000U)
+    {
+      return HAL_TIMEOUT;
+    }
+  } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_CSRST) == USB_OTG_GRSTCTL_CSRST);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  USB_HostInit : Initializes the USB OTG controller registers
+  *         for Host mode
+  * @param  USBx  Selected device
+  * @param  cfg   pointer to a USB_OTG_CfgTypeDef structure that contains
+  *         the configuration information for the specified USBx peripheral.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef USB_HostInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg)
+{
+  HAL_StatusTypeDef ret = HAL_OK;
+  uint32_t USBx_BASE = (uint32_t)USBx;
+  uint32_t i;
+
+  /* Restart the Phy Clock */
+  USBx_PCGCCTL = 0U;
+
+#if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
+  /* Disable HW VBUS sensing */
+  USBx->GCCFG &= ~(USB_OTG_GCCFG_VBDEN);
+#else
+  /*
+  * Disable HW VBUS sensing. VBUS is internally considered to be always
+  * at VBUS-Valid level (5V).
+  */
+  USBx->GCCFG |= USB_OTG_GCCFG_NOVBUSSENS;
+  USBx->GCCFG &= ~USB_OTG_GCCFG_VBUSBSEN;
+  USBx->GCCFG &= ~USB_OTG_GCCFG_VBUSASEN;
+#endif /* defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) */
+#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
+  /* Disable Battery chargin detector */
+  USBx->GCCFG &= ~(USB_OTG_GCCFG_BCDEN);
+#endif /* defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) */
+
+  if ((USBx->CID & (0x1U << 8)) != 0U)
+  {
+    if (cfg.speed == USBH_FSLS_SPEED)
+    {
+      /* Force Device Enumeration to FS/LS mode only */
+      USBx_HOST->HCFG |= USB_OTG_HCFG_FSLSS;
+    }
+    else
+    {
+      /* Set default Max speed support */
+      USBx_HOST->HCFG &= ~(USB_OTG_HCFG_FSLSS);
+    }
+  }
+  else
+  {
+    /* Set default Max speed support */
+    USBx_HOST->HCFG &= ~(USB_OTG_HCFG_FSLSS);
+  }
+
+  /* Make sure the FIFOs are flushed. */
+  if (USB_FlushTxFifo(USBx, 0x10U) != HAL_OK) /* all Tx FIFOs */
+  {
+    ret = HAL_ERROR;
+  }
+
+  if (USB_FlushRxFifo(USBx) != HAL_OK)
+  {
+    ret = HAL_ERROR;
+  }
+
+  /* Clear all pending HC Interrupts */
+  for (i = 0U; i < cfg.Host_channels; i++)
+  {
+    USBx_HC(i)->HCINT = 0xFFFFFFFFU;
+    USBx_HC(i)->HCINTMSK = 0U;
+  }
+
+  /* Disable all interrupts. */
+  USBx->GINTMSK = 0U;
+
+  /* Clear any pending interrupts */
+  USBx->GINTSTS = 0xFFFFFFFFU;
+
+  if ((USBx->CID & (0x1U << 8)) != 0U)
+  {
+    /* set Rx FIFO size */
+    USBx->GRXFSIZ  = 0x200U;
+    USBx->DIEPTXF0_HNPTXFSIZ = (uint32_t)(((0x100U << 16) & USB_OTG_NPTXFD) | 0x200U);
+    USBx->HPTXFSIZ = (uint32_t)(((0xE0U << 16) & USB_OTG_HPTXFSIZ_PTXFD) | 0x300U);
+  }
+  else
+  {
+    /* set Rx FIFO size */
+    USBx->GRXFSIZ  = 0x80U;
+    USBx->DIEPTXF0_HNPTXFSIZ = (uint32_t)(((0x60U << 16) & USB_OTG_NPTXFD) | 0x80U);
+    USBx->HPTXFSIZ = (uint32_t)(((0x40U << 16)& USB_OTG_HPTXFSIZ_PTXFD) | 0xE0U);
+  }
+
+  /* Enable the common interrupts */
+  if (cfg.dma_enable == 0U)
+  {
+    USBx->GINTMSK |= USB_OTG_GINTMSK_RXFLVLM;
+  }
+
+  /* Enable interrupts matching to the Host mode ONLY */
+  USBx->GINTMSK |= (USB_OTG_GINTMSK_PRTIM            | USB_OTG_GINTMSK_HCIM | \
+                    USB_OTG_GINTMSK_SOFM             | USB_OTG_GINTSTS_DISCINT | \
+                    USB_OTG_GINTMSK_PXFRM_IISOOXFRM  | USB_OTG_GINTMSK_WUIM);
+
+  return ret;
+}
+
+/**
+  * @brief  USB_InitFSLSPClkSel : Initializes the FSLSPClkSel field of the
+  *         HCFG register on the PHY type and set the right frame interval
+  * @param  USBx  Selected device
+  * @param  freq  clock frequency
+  *          This parameter can be one of these values:
+  *           HCFG_48_MHZ : Full Speed 48 MHz Clock
+  *           HCFG_6_MHZ : Low Speed 6 MHz Clock
+  * @retval HAL status
+  */
+HAL_StatusTypeDef USB_InitFSLSPClkSel(USB_OTG_GlobalTypeDef *USBx, uint8_t freq)
+{
+  uint32_t USBx_BASE = (uint32_t)USBx;
+
+  USBx_HOST->HCFG &= ~(USB_OTG_HCFG_FSLSPCS);
+  USBx_HOST->HCFG |= (uint32_t)freq & USB_OTG_HCFG_FSLSPCS;
+
+  if (freq == HCFG_48_MHZ)
+  {
+    USBx_HOST->HFIR = 48000U;
+  }
+  else if (freq == HCFG_6_MHZ)
+  {
+    USBx_HOST->HFIR = 6000U;
+  }
+  else
+  {
+    /* ... */
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  USB_OTG_ResetPort : Reset Host Port
+  * @param  USBx  Selected device
+  * @retval HAL status
+  * @note (1)The application must wait at least 10 ms
+  *   before clearing the reset bit.
+  */
+HAL_StatusTypeDef USB_ResetPort(USB_OTG_GlobalTypeDef *USBx)
+{
+  uint32_t USBx_BASE = (uint32_t)USBx;
+
+  __IO uint32_t hprt0 = 0U;
+
+  hprt0 = USBx_HPRT0;
+
+  hprt0 &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET |
+             USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG);
+
+  USBx_HPRT0 = (USB_OTG_HPRT_PRST | hprt0);
+  HAL_Delay(100U);                                 /* See Note #1 */
+  USBx_HPRT0 = ((~USB_OTG_HPRT_PRST) & hprt0);
+  HAL_Delay(10U);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  USB_DriveVbus : activate or de-activate vbus
+  * @param  state  VBUS state
+  *          This parameter can be one of these values:
+  *           0 : Deactivate VBUS
+  *           1 : Activate VBUS
+  * @retval HAL status
+  */
+HAL_StatusTypeDef USB_DriveVbus(USB_OTG_GlobalTypeDef *USBx, uint8_t state)
+{
+  uint32_t USBx_BASE = (uint32_t)USBx;
+  __IO uint32_t hprt0 = 0U;
+
+  hprt0 = USBx_HPRT0;
+
+  hprt0 &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET |
+             USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG);
+
+  if (((hprt0 & USB_OTG_HPRT_PPWR) == 0U) && (state == 1U))
+  {
+    USBx_HPRT0 = (USB_OTG_HPRT_PPWR | hprt0);
+  }
+  if (((hprt0 & USB_OTG_HPRT_PPWR) == USB_OTG_HPRT_PPWR) && (state == 0U))
+  {
+    USBx_HPRT0 = ((~USB_OTG_HPRT_PPWR) & hprt0);
+  }
+  return HAL_OK;
+}
+
+/**
+  * @brief  Return Host Core speed
+  * @param  USBx  Selected device
+  * @retval speed : Host speed
+  *          This parameter can be one of these values:
+  *            @arg HCD_SPEED_HIGH: High speed mode
+  *            @arg HCD_SPEED_FULL: Full speed mode
+  *            @arg HCD_SPEED_LOW: Low speed mode
+  */
+uint32_t USB_GetHostSpeed(USB_OTG_GlobalTypeDef *USBx)
+{
+  uint32_t USBx_BASE = (uint32_t)USBx;
+  __IO uint32_t hprt0 = 0U;
+
+  hprt0 = USBx_HPRT0;
+  return ((hprt0 & USB_OTG_HPRT_PSPD) >> 17);
+}
+
+/**
+  * @brief  Return Host Current Frame number
+  * @param  USBx  Selected device
+  * @retval current frame number
+  */
+uint32_t USB_GetCurrentFrame(USB_OTG_GlobalTypeDef *USBx)
+{
+  uint32_t USBx_BASE = (uint32_t)USBx;
+
+  return (USBx_HOST->HFNUM & USB_OTG_HFNUM_FRNUM);
+}
+
+/**
+  * @brief  Initialize a host channel
+  * @param  USBx  Selected device
+  * @param  ch_num  Channel number
+  *         This parameter can be a value from 1 to 15
+  * @param  epnum  Endpoint number
+  *          This parameter can be a value from 1 to 15
+  * @param  dev_address  Current device address
+  *          This parameter can be a value from 0 to 255
+  * @param  speed  Current device speed
+  *          This parameter can be one of these values:
+  *            @arg USB_OTG_SPEED_HIGH: High speed mode
+  *            @arg USB_OTG_SPEED_FULL: Full speed mode
+  *            @arg USB_OTG_SPEED_LOW: Low speed mode
+  * @param  ep_type  Endpoint Type
+  *          This parameter can be one of these values:
+  *            @arg EP_TYPE_CTRL: Control type
+  *            @arg EP_TYPE_ISOC: Isochronous type
+  *            @arg EP_TYPE_BULK: Bulk type
+  *            @arg EP_TYPE_INTR: Interrupt type
+  * @param  mps  Max Packet Size
+  *          This parameter can be a value from 0 to 32K
+  * @retval HAL state
+  */
+HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num,
+                              uint8_t epnum, uint8_t dev_address, uint8_t speed,
+                              uint8_t ep_type, uint16_t mps)
+{
+  HAL_StatusTypeDef ret = HAL_OK;
+  uint32_t USBx_BASE = (uint32_t)USBx;
+  uint32_t HCcharEpDir;
+  uint32_t HCcharLowSpeed;
+  uint32_t HostCoreSpeed;
+
+  /* Clear old interrupt conditions for this host channel. */
+  USBx_HC((uint32_t)ch_num)->HCINT = 0xFFFFFFFFU;
+
+  /* Enable channel interrupts required for this transfer. */
+  switch (ep_type)
+  {
+    case EP_TYPE_CTRL:
+    case EP_TYPE_BULK:
+      USBx_HC((uint32_t)ch_num)->HCINTMSK = USB_OTG_HCINTMSK_XFRCM  |
+                                            USB_OTG_HCINTMSK_STALLM |
+                                            USB_OTG_HCINTMSK_TXERRM |
+                                            USB_OTG_HCINTMSK_DTERRM |
+                                            USB_OTG_HCINTMSK_AHBERR |
+                                            USB_OTG_HCINTMSK_NAKM;
+
+      if ((epnum & 0x80U) == 0x80U)
+      {
+        USBx_HC((uint32_t)ch_num)->HCINTMSK |= USB_OTG_HCINTMSK_BBERRM;
+      }
+      else
+      {
+        if ((USBx->CID & (0x1U << 8)) != 0U)
+        {
+          USBx_HC((uint32_t)ch_num)->HCINTMSK |= USB_OTG_HCINTMSK_NYET |
+                                                 USB_OTG_HCINTMSK_ACKM;
+        }
+      }
+      break;
+
+    case EP_TYPE_INTR:
+      USBx_HC((uint32_t)ch_num)->HCINTMSK = USB_OTG_HCINTMSK_XFRCM  |
+                                            USB_OTG_HCINTMSK_STALLM |
+                                            USB_OTG_HCINTMSK_TXERRM |
+                                            USB_OTG_HCINTMSK_DTERRM |
+                                            USB_OTG_HCINTMSK_NAKM   |
+                                            USB_OTG_HCINTMSK_AHBERR |
+                                            USB_OTG_HCINTMSK_FRMORM;
+
+      if ((epnum & 0x80U) == 0x80U)
+      {
+        USBx_HC((uint32_t)ch_num)->HCINTMSK |= USB_OTG_HCINTMSK_BBERRM;
+      }
+
+      break;
+
+    case EP_TYPE_ISOC:
+      USBx_HC((uint32_t)ch_num)->HCINTMSK = USB_OTG_HCINTMSK_XFRCM  |
+                                            USB_OTG_HCINTMSK_ACKM   |
+                                            USB_OTG_HCINTMSK_AHBERR |
+                                            USB_OTG_HCINTMSK_FRMORM;
+
+      if ((epnum & 0x80U) == 0x80U)
+      {
+        USBx_HC((uint32_t)ch_num)->HCINTMSK |= (USB_OTG_HCINTMSK_TXERRM | USB_OTG_HCINTMSK_BBERRM);
+      }
+      break;
+
+    default:
+      ret = HAL_ERROR;
+      break;
+  }
+
+  /* Enable host channel Halt interrupt */
+  USBx_HC((uint32_t)ch_num)->HCINTMSK |= USB_OTG_HCINTMSK_CHHM;
+
+  /* Enable the top level host channel interrupt. */
+  USBx_HOST->HAINTMSK |= 1UL << (ch_num & 0xFU);
+
+  /* Make sure host channel interrupts are enabled. */
+  USBx->GINTMSK |= USB_OTG_GINTMSK_HCIM;
+
+  /* Program the HCCHAR register */
+  if ((epnum & 0x80U) == 0x80U)
+  {
+    HCcharEpDir = (0x1U << 15) & USB_OTG_HCCHAR_EPDIR;
+  }
+  else
+  {
+    HCcharEpDir = 0U;
+  }
+
+  HostCoreSpeed = USB_GetHostSpeed(USBx);
+
+  /* LS device plugged to HUB */
+  if ((speed == HPRT0_PRTSPD_LOW_SPEED) && (HostCoreSpeed != HPRT0_PRTSPD_LOW_SPEED))
+  {
+    HCcharLowSpeed = (0x1U << 17) & USB_OTG_HCCHAR_LSDEV;
+  }
+  else
+  {
+    HCcharLowSpeed = 0U;
+  }
+
+  USBx_HC((uint32_t)ch_num)->HCCHAR = (((uint32_t)dev_address << 22) & USB_OTG_HCCHAR_DAD) |
+                                      ((((uint32_t)epnum & 0x7FU) << 11) & USB_OTG_HCCHAR_EPNUM) |
+                                      (((uint32_t)ep_type << 18) & USB_OTG_HCCHAR_EPTYP) |
+                                      ((uint32_t)mps & USB_OTG_HCCHAR_MPSIZ) | HCcharEpDir | HCcharLowSpeed;
+
+  if ((ep_type == EP_TYPE_INTR) || (ep_type == EP_TYPE_ISOC))
+  {
+    USBx_HC((uint32_t)ch_num)->HCCHAR |= USB_OTG_HCCHAR_ODDFRM;
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  Start a transfer over a host channel
+  * @param  USBx  Selected device
+  * @param  hc  pointer to host channel structure
+  * @param  dma USB dma enabled or disabled
+  *          This parameter can be one of these values:
+  *           0 : DMA feature not used
+  *           1 : DMA feature used
+  * @retval HAL state
+  */
+HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCTypeDef *hc, uint8_t dma)
+{
+  uint32_t USBx_BASE = (uint32_t)USBx;
+  uint32_t ch_num = (uint32_t)hc->ch_num;
+  __IO uint32_t tmpreg;
+  uint8_t  is_oddframe;
+  uint16_t len_words;
+  uint16_t num_packets;
+  uint16_t max_hc_pkt_count = 256U;
+
+  if (((USBx->CID & (0x1U << 8)) != 0U) && (hc->speed == USBH_HS_SPEED))
+  {
+    /* in DMA mode host Core automatically issues ping  in case of NYET/NAK */
+    if ((dma == 1U) && ((hc->ep_type == EP_TYPE_CTRL) || (hc->ep_type == EP_TYPE_BULK)))
+    {
+      USBx_HC((uint32_t)ch_num)->HCINTMSK &= ~(USB_OTG_HCINTMSK_NYET |
+                                               USB_OTG_HCINTMSK_ACKM |
+                                               USB_OTG_HCINTMSK_NAKM);
+    }
+
+    if ((dma == 0U) && (hc->do_ping == 1U))
+    {
+      (void)USB_DoPing(USBx, hc->ch_num);
+      return HAL_OK;
+    }
+
+  }
+
+  /* Compute the expected number of packets associated to the transfer */
+  if (hc->xfer_len > 0U)
+  {
+    num_packets = (uint16_t)((hc->xfer_len + hc->max_packet - 1U) / hc->max_packet);
+
+    if (num_packets > max_hc_pkt_count)
+    {
+      num_packets = max_hc_pkt_count;
+      hc->XferSize = (uint32_t)num_packets * hc->max_packet;
+    }
+  }
+  else
+  {
+    num_packets = 1U;
+  }
+
+  /*
+   * For IN channel HCTSIZ.XferSize is expected to be an integer multiple of
+   * max_packet size.
+   */
+  if (hc->ep_is_in != 0U)
+  {
+    hc->XferSize = (uint32_t)num_packets * hc->max_packet;
+  }
+  else
+  {
+    hc->XferSize = hc->xfer_len;
+  }
+
+  /* Initialize the HCTSIZn register */
+  USBx_HC(ch_num)->HCTSIZ = (hc->XferSize & USB_OTG_HCTSIZ_XFRSIZ) |
+                            (((uint32_t)num_packets << 19) & USB_OTG_HCTSIZ_PKTCNT) |
+                            (((uint32_t)hc->data_pid << 29) & USB_OTG_HCTSIZ_DPID);
+
+  if (dma != 0U)
+  {
+    /* xfer_buff MUST be 32-bits aligned */
+    USBx_HC(ch_num)->HCDMA = (uint32_t)hc->xfer_buff;
+  }
+
+  is_oddframe = (((uint32_t)USBx_HOST->HFNUM & 0x01U) != 0U) ? 0U : 1U;
+  USBx_HC(ch_num)->HCCHAR &= ~USB_OTG_HCCHAR_ODDFRM;
+  USBx_HC(ch_num)->HCCHAR |= (uint32_t)is_oddframe << 29;
+
+  /* Set host channel enable */
+  tmpreg = USBx_HC(ch_num)->HCCHAR;
+  tmpreg &= ~USB_OTG_HCCHAR_CHDIS;
+
+  /* make sure to set the correct ep direction */
+  if (hc->ep_is_in != 0U)
+  {
+    tmpreg |= USB_OTG_HCCHAR_EPDIR;
+  }
+  else
+  {
+    tmpreg &= ~USB_OTG_HCCHAR_EPDIR;
+  }
+  tmpreg |= USB_OTG_HCCHAR_CHENA;
+  USBx_HC(ch_num)->HCCHAR = tmpreg;
+
+  if (dma != 0U) /* dma mode */
+  {
+    return HAL_OK;
+  }
+
+  if ((hc->ep_is_in == 0U) && (hc->xfer_len > 0U))
+  {
+    switch (hc->ep_type)
+    {
+      /* Non periodic transfer */
+      case EP_TYPE_CTRL:
+      case EP_TYPE_BULK:
+
+        len_words = (uint16_t)((hc->xfer_len + 3U) / 4U);
+
+        /* check if there is enough space in FIFO space */
+        if (len_words > (USBx->HNPTXSTS & 0xFFFFU))
+        {
+          /* need to process data in nptxfempty interrupt */
+          USBx->GINTMSK |= USB_OTG_GINTMSK_NPTXFEM;
+        }
+        break;
+
+      /* Periodic transfer */
+      case EP_TYPE_INTR:
+      case EP_TYPE_ISOC:
+        len_words = (uint16_t)((hc->xfer_len + 3U) / 4U);
+        /* check if there is enough space in FIFO space */
+        if (len_words > (USBx_HOST->HPTXSTS & 0xFFFFU)) /* split the transfer */
+        {
+          /* need to process data in ptxfempty interrupt */
+          USBx->GINTMSK |= USB_OTG_GINTMSK_PTXFEM;
+        }
+        break;
+
+      default:
+        break;
+    }
+
+    /* Write packet into the Tx FIFO. */
+    (void)USB_WritePacket(USBx, hc->xfer_buff, hc->ch_num, (uint16_t)hc->xfer_len, 0);
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief Read all host channel interrupts status
+  * @param  USBx  Selected device
+  * @retval HAL state
+  */
+uint32_t USB_HC_ReadInterrupt(USB_OTG_GlobalTypeDef *USBx)
+{
+  uint32_t USBx_BASE = (uint32_t)USBx;
+
+  return ((USBx_HOST->HAINT) & 0xFFFFU);
+}
+
+/**
+  * @brief  Halt a host channel
+  * @param  USBx  Selected device
+  * @param  hc_num  Host Channel number
+  *         This parameter can be a value from 1 to 15
+  * @retval HAL state
+  */
+HAL_StatusTypeDef USB_HC_Halt(USB_OTG_GlobalTypeDef *USBx, uint8_t hc_num)
+{
+  uint32_t USBx_BASE = (uint32_t)USBx;
+  uint32_t hcnum = (uint32_t)hc_num;
+  __IO uint32_t count = 0U;
+  uint32_t HcEpType = (USBx_HC(hcnum)->HCCHAR & USB_OTG_HCCHAR_EPTYP) >> 18;
+  uint32_t ChannelEna = (USBx_HC(hcnum)->HCCHAR & USB_OTG_HCCHAR_CHENA) >> 31;
+
+  if (((USBx->GAHBCFG & USB_OTG_GAHBCFG_DMAEN) == USB_OTG_GAHBCFG_DMAEN) &&
+      (ChannelEna == 0U))
+  {
+    return HAL_OK;
+  }
+
+  /* Check for space in the request queue to issue the halt. */
+  if ((HcEpType == HCCHAR_CTRL) || (HcEpType == HCCHAR_BULK))
+  {
+    USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHDIS;
+
+    if ((USBx->GAHBCFG & USB_OTG_GAHBCFG_DMAEN) == 0U)
+    {
+      if ((USBx->HNPTXSTS & (0xFFU << 16)) == 0U)
+      {
+        USBx_HC(hcnum)->HCCHAR &= ~USB_OTG_HCCHAR_CHENA;
+        USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA;
+        do
+        {
+          count++;
+
+          if (count > 1000U)
+          {
+            break;
+          }
+        } while ((USBx_HC(hcnum)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA);
+      }
+      else
+      {
+        USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA;
+      }
+    }
+  }
+  else
+  {
+    USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHDIS;
+
+    if ((USBx_HOST->HPTXSTS & (0xFFU << 16)) == 0U)
+    {
+      USBx_HC(hcnum)->HCCHAR &= ~USB_OTG_HCCHAR_CHENA;
+      USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA;
+      do
+      {
+        count++;
+
+        if (count > 1000U)
+        {
+          break;
+        }
+      } while ((USBx_HC(hcnum)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA);
+    }
+    else
+    {
+      USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA;
+    }
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initiate Do Ping protocol
+  * @param  USBx  Selected device
+  * @param  hc_num  Host Channel number
+  *         This parameter can be a value from 1 to 15
+  * @retval HAL state
+  */
+HAL_StatusTypeDef USB_DoPing(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num)
+{
+  uint32_t USBx_BASE = (uint32_t)USBx;
+  uint32_t chnum = (uint32_t)ch_num;
+  uint32_t num_packets = 1U;
+  uint32_t tmpreg;
+
+  USBx_HC(chnum)->HCTSIZ = ((num_packets << 19) & USB_OTG_HCTSIZ_PKTCNT) |
+                           USB_OTG_HCTSIZ_DOPING;
+
+  /* Set host channel enable */
+  tmpreg = USBx_HC(chnum)->HCCHAR;
+  tmpreg &= ~USB_OTG_HCCHAR_CHDIS;
+  tmpreg |= USB_OTG_HCCHAR_CHENA;
+  USBx_HC(chnum)->HCCHAR = tmpreg;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stop Host Core
+  * @param  USBx  Selected device
+  * @retval HAL state
+  */
+HAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx)
+{
+  HAL_StatusTypeDef ret = HAL_OK;
+  uint32_t USBx_BASE = (uint32_t)USBx;
+  __IO uint32_t count = 0U;
+  uint32_t value;
+  uint32_t i;
+
+  (void)USB_DisableGlobalInt(USBx);
+
+  /* Flush USB FIFO */
+  if (USB_FlushTxFifo(USBx, 0x10U) != HAL_OK) /* all Tx FIFOs */
+  {
+    ret = HAL_ERROR;
+  }
+
+  if (USB_FlushRxFifo(USBx) != HAL_OK)
+  {
+    ret = HAL_ERROR;
+  }
+
+  /* Flush out any leftover queued requests. */
+  for (i = 0U; i <= 15U; i++)
+  {
+    value = USBx_HC(i)->HCCHAR;
+    value |=  USB_OTG_HCCHAR_CHDIS;
+    value &= ~USB_OTG_HCCHAR_CHENA;
+    value &= ~USB_OTG_HCCHAR_EPDIR;
+    USBx_HC(i)->HCCHAR = value;
+  }
+
+  /* Halt all channels to put them into a known state. */
+  for (i = 0U; i <= 15U; i++)
+  {
+    value = USBx_HC(i)->HCCHAR;
+    value |= USB_OTG_HCCHAR_CHDIS;
+    value |= USB_OTG_HCCHAR_CHENA;
+    value &= ~USB_OTG_HCCHAR_EPDIR;
+    USBx_HC(i)->HCCHAR = value;
+
+    do
+    {
+      count++;
+
+      if (count > 1000U)
+      {
+        break;
+      }
+    } while ((USBx_HC(i)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA);
+  }
+
+  /* Clear any pending Host interrupts */
+  USBx_HOST->HAINT = 0xFFFFFFFFU;
+  USBx->GINTSTS = 0xFFFFFFFFU;
+
+  (void)USB_EnableGlobalInt(USBx);
+
+  return ret;
+}
+
+/**
+  * @brief  USB_ActivateRemoteWakeup active remote wakeup signalling
+  * @param  USBx Selected device
+  * @retval HAL status
+  */
+HAL_StatusTypeDef USB_ActivateRemoteWakeup(USB_OTG_GlobalTypeDef *USBx)
+{
+  uint32_t USBx_BASE = (uint32_t)USBx;
+
+  if ((USBx_DEVICE->DSTS & USB_OTG_DSTS_SUSPSTS) == USB_OTG_DSTS_SUSPSTS)
+  {
+    /* active Remote wakeup signalling */
+    USBx_DEVICE->DCTL |= USB_OTG_DCTL_RWUSIG;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  USB_DeActivateRemoteWakeup de-active remote wakeup signalling
+  * @param  USBx Selected device
+  * @retval HAL status
+  */
+HAL_StatusTypeDef USB_DeActivateRemoteWakeup(USB_OTG_GlobalTypeDef *USBx)
+{
+  uint32_t USBx_BASE = (uint32_t)USBx;
+
+  /* active Remote wakeup signalling */
+  USBx_DEVICE->DCTL &= ~(USB_OTG_DCTL_RWUSIG);
+
+  return HAL_OK;
+}
+#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
+#endif /* defined (HAL_PCD_MODULE_ENABLED) || defined (HAL_HCD_MODULE_ENABLED) */
+
+/**
+  * @}
+  */
diff --git a/FATFS/App/fatfs.c b/FATFS/App/fatfs.c
new file mode 100644
index 0000000..4ea8493
--- /dev/null
+++ b/FATFS/App/fatfs.c
@@ -0,0 +1,54 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file   fatfs.c
+  * @brief  Code for fatfs applications
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2022 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+#include "fatfs.h"
+
+uint8_t retSD;    /* Return value for SD */
+char SDPath[4];   /* SD logical drive path */
+FATFS SDFatFS;    /* File system object for SD logical drive */
+FIL SDFile;       /* File object for SD */
+
+/* USER CODE BEGIN Variables */
+
+/* USER CODE END Variables */
+
+void MX_FATFS_Init(void)
+{
+  /*## FatFS: Link the SD driver ###########################*/
+  retSD = FATFS_LinkDriver(&SD_Driver, SDPath);
+
+  /* USER CODE BEGIN Init */
+  /* additional user code for init */
+  /* USER CODE END Init */
+}
+
+/**
+  * @brief  Gets Time from RTC
+  * @param  None
+  * @retval Time in DWORD
+  */
+DWORD get_fattime(void)
+{
+  /* USER CODE BEGIN get_fattime */
+  return 0;
+  /* USER CODE END get_fattime */
+}
+
+/* USER CODE BEGIN Application */
+
+/* USER CODE END Application */
diff --git a/FATFS/App/fatfs.h b/FATFS/App/fatfs.h
new file mode 100644
index 0000000..d9b069d
--- /dev/null
+++ b/FATFS/App/fatfs.h
@@ -0,0 +1,47 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file   fatfs.h
+  * @brief  Header for fatfs applications
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2022 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __fatfs_H
+#define __fatfs_H
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "ff.h"
+#include "ff_gen_drv.h"
+#include "sd_diskio.h" /* defines SD_Driver as external */
+
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+extern uint8_t retSD; /* Return value for SD */
+extern char SDPath[4]; /* SD logical drive path */
+extern FATFS SDFatFS; /* File system object for SD logical drive */
+extern FIL SDFile; /* File object for SD */
+
+void MX_FATFS_Init(void);
+
+/* USER CODE BEGIN Prototypes */
+
+/* USER CODE END Prototypes */
+#ifdef __cplusplus
+}
+#endif
+#endif /*__fatfs_H */
diff --git a/FATFS/Target/bsp_driver_sd.c b/FATFS/Target/bsp_driver_sd.c
new file mode 100644
index 0000000..871b620
--- /dev/null
+++ b/FATFS/Target/bsp_driver_sd.c
@@ -0,0 +1,316 @@
+/* USER CODE BEGIN Header */
+/**
+ ******************************************************************************
+  * @file    bsp_driver_sd.c for F4 (based on stm324x9i_eval_sd.c)
+ * @brief   This file includes a generic uSD card driver.
+ *          To be completed by the user according to the board used for the project.
+ * @note    Some functions generated as weak: they can be overridden by
+ *          - code in user files
+ *          - or BSP code from the FW pack files
+ *          if such files are added to the generated project (by the user).
+ ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2022 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+ ******************************************************************************
+ */
+/* USER CODE END Header */
+
+#ifdef OLD_API
+/* kept to avoid issue when migrating old projects. */
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+#else
+/* USER CODE BEGIN FirstSection */
+/* can be used to modify / undefine following code or add new definitions */
+/* USER CODE END FirstSection */
+/* Includes ------------------------------------------------------------------*/
+#include "bsp_driver_sd.h"
+
+/* Extern variables ---------------------------------------------------------*/
+
+extern SD_HandleTypeDef hsd;
+
+/* USER CODE BEGIN BeforeInitSection */
+/* can be used to modify / undefine following code or add code */
+/* USER CODE END BeforeInitSection */
+/**
+  * @brief  Initializes the SD card device.
+  * @retval SD status
+  */
+__weak uint8_t BSP_SD_Init(void)
+{
+  uint8_t sd_state = MSD_OK;
+  /* Check if the SD card is plugged in the slot */
+  if (BSP_SD_IsDetected() != SD_PRESENT)
+  {
+    return MSD_ERROR;
+  }
+  /* HAL SD initialization */
+  sd_state = HAL_SD_Init(&hsd);
+  /* Configure SD Bus width (4 bits mode selected) */
+  if (sd_state == MSD_OK)
+  {
+    /* Enable wide operation */
+    if (HAL_SD_ConfigWideBusOperation(&hsd, SDIO_BUS_WIDE_4B) != HAL_OK)
+    {
+      sd_state = MSD_ERROR;
+    }
+  }
+
+  return sd_state;
+}
+/* USER CODE BEGIN AfterInitSection */
+/* can be used to modify previous code / undefine following code / add code */
+/* USER CODE END AfterInitSection */
+
+/* USER CODE BEGIN InterruptMode */
+/**
+  * @brief  Configures Interrupt mode for SD detection pin.
+  * @retval Returns 0
+  */
+__weak uint8_t BSP_SD_ITConfig(void)
+{
+  /* Code to be updated by the user or replaced by one from the FW pack (in a stmxxxx_sd.c file) */
+
+  return (uint8_t)0;
+}
+
+/** @brief  SD detect IT treatment
+  */
+__weak void BSP_SD_DetectIT(void)
+{
+  /* Code to be updated by the user or replaced by one from the FW pack (in a stmxxxx_sd.c file) */
+}
+/* USER CODE END InterruptMode */
+
+/* USER CODE BEGIN BeforeReadBlocksSection */
+/* can be used to modify previous code / undefine following code / add code */
+/* USER CODE END BeforeReadBlocksSection */
+/**
+  * @brief  Reads block(s) from a specified address in an SD card, in polling mode.
+  * @param  pData: Pointer to the buffer that will contain the data to transmit
+  * @param  ReadAddr: Address from where data is to be read
+  * @param  NumOfBlocks: Number of SD blocks to read
+  * @param  Timeout: Timeout for read operation
+  * @retval SD status
+  */
+__weak uint8_t BSP_SD_ReadBlocks(uint32_t *pData, uint32_t ReadAddr, uint32_t NumOfBlocks, uint32_t Timeout)
+{
+  uint8_t sd_state = MSD_OK;
+
+  if (HAL_SD_ReadBlocks(&hsd, (uint8_t *)pData, ReadAddr, NumOfBlocks, Timeout) != HAL_OK)
+  {
+    sd_state = MSD_ERROR;
+  }
+
+  return sd_state;
+}
+
+/* USER CODE BEGIN BeforeWriteBlocksSection */
+/* can be used to modify previous code / undefine following code / add code */
+/* USER CODE END BeforeWriteBlocksSection */
+/**
+  * @brief  Writes block(s) to a specified address in an SD card, in polling mode.
+  * @param  pData: Pointer to the buffer that will contain the data to transmit
+  * @param  WriteAddr: Address from where data is to be written
+  * @param  NumOfBlocks: Number of SD blocks to write
+  * @param  Timeout: Timeout for write operation
+  * @retval SD status
+  */
+__weak uint8_t BSP_SD_WriteBlocks(uint32_t *pData, uint32_t WriteAddr, uint32_t NumOfBlocks, uint32_t Timeout)
+{
+  uint8_t sd_state = MSD_OK;
+
+  if (HAL_SD_WriteBlocks(&hsd, (uint8_t *)pData, WriteAddr, NumOfBlocks, Timeout) != HAL_OK)
+  {
+    sd_state = MSD_ERROR;
+  }
+
+  return sd_state;
+}
+
+/* USER CODE BEGIN BeforeReadDMABlocksSection */
+/* can be used to modify previous code / undefine following code / add code */
+/* USER CODE END BeforeReadDMABlocksSection */
+/**
+  * @brief  Reads block(s) from a specified address in an SD card, in DMA mode.
+  * @param  pData: Pointer to the buffer that will contain the data to transmit
+  * @param  ReadAddr: Address from where data is to be read
+  * @param  NumOfBlocks: Number of SD blocks to read
+  * @retval SD status
+  */
+__weak uint8_t BSP_SD_ReadBlocks_DMA(uint32_t *pData, uint32_t ReadAddr, uint32_t NumOfBlocks)
+{
+  uint8_t sd_state = MSD_OK;
+
+  /* Read block(s) in DMA transfer mode */
+  if (HAL_SD_ReadBlocks_DMA(&hsd, (uint8_t *)pData, ReadAddr, NumOfBlocks) != HAL_OK)
+  {
+    sd_state = MSD_ERROR;
+  }
+
+  return sd_state;
+}
+
+/* USER CODE BEGIN BeforeWriteDMABlocksSection */
+/* can be used to modify previous code / undefine following code / add code */
+/* USER CODE END BeforeWriteDMABlocksSection */
+/**
+  * @brief  Writes block(s) to a specified address in an SD card, in DMA mode.
+  * @param  pData: Pointer to the buffer that will contain the data to transmit
+  * @param  WriteAddr: Address from where data is to be written
+  * @param  NumOfBlocks: Number of SD blocks to write
+  * @retval SD status
+  */
+__weak uint8_t BSP_SD_WriteBlocks_DMA(uint32_t *pData, uint32_t WriteAddr, uint32_t NumOfBlocks)
+{
+  uint8_t sd_state = MSD_OK;
+
+  /* Write block(s) in DMA transfer mode */
+  if (HAL_SD_WriteBlocks_DMA(&hsd, (uint8_t *)pData, WriteAddr, NumOfBlocks) != HAL_OK)
+  {
+    sd_state = MSD_ERROR;
+  }
+
+  return sd_state;
+}
+
+/* USER CODE BEGIN BeforeEraseSection */
+/* can be used to modify previous code / undefine following code / add code */
+/* USER CODE END BeforeEraseSection */
+/**
+  * @brief  Erases the specified memory area of the given SD card.
+  * @param  StartAddr: Start byte address
+  * @param  EndAddr: End byte address
+  * @retval SD status
+  */
+__weak uint8_t BSP_SD_Erase(uint32_t StartAddr, uint32_t EndAddr)
+{
+  uint8_t sd_state = MSD_OK;
+
+  if (HAL_SD_Erase(&hsd, StartAddr, EndAddr) != HAL_OK)
+  {
+    sd_state = MSD_ERROR;
+  }
+
+  return sd_state;
+}
+
+/**
+  * @brief  Gets the current SD card data status.
+  * @param  None
+  * @retval Data transfer state.
+  *          This value can be one of the following values:
+  *            @arg  SD_TRANSFER_OK: No data transfer is acting
+  *            @arg  SD_TRANSFER_BUSY: Data transfer is acting
+  */
+__weak uint8_t BSP_SD_GetCardState(void)
+{
+  return ((HAL_SD_GetCardState(&hsd) == HAL_SD_CARD_TRANSFER ) ? SD_TRANSFER_OK : SD_TRANSFER_BUSY);
+}
+
+/**
+  * @brief  Get SD information about specific SD card.
+  * @param  CardInfo: Pointer to HAL_SD_CardInfoTypedef structure
+  * @retval None
+  */
+__weak void BSP_SD_GetCardInfo(HAL_SD_CardInfoTypeDef *CardInfo)
+{
+  /* Get SD card Information */
+  HAL_SD_GetCardInfo(&hsd, CardInfo);
+}
+
+/* USER CODE BEGIN BeforeCallBacksSection */
+/* can be used to modify previous code / undefine following code / add code */
+/* USER CODE END BeforeCallBacksSection */
+/**
+  * @brief SD Abort callbacks
+  * @param hsd: SD handle
+  * @retval None
+  */
+void HAL_SD_AbortCallback(SD_HandleTypeDef *hsd)
+{
+  BSP_SD_AbortCallback();
+}
+
+/**
+  * @brief Tx Transfer completed callback
+  * @param hsd: SD handle
+  * @retval None
+  */
+void HAL_SD_TxCpltCallback(SD_HandleTypeDef *hsd)
+{
+  BSP_SD_WriteCpltCallback();
+}
+
+/**
+  * @brief Rx Transfer completed callback
+  * @param hsd: SD handle
+  * @retval None
+  */
+void HAL_SD_RxCpltCallback(SD_HandleTypeDef *hsd)
+{
+  BSP_SD_ReadCpltCallback();
+}
+
+/* USER CODE BEGIN CallBacksSection_C */
+/**
+  * @brief BSP SD Abort callback
+  * @retval None
+  * @note empty (up to the user to fill it in or to remove it if useless)
+  */
+__weak void BSP_SD_AbortCallback(void)
+{
+
+}
+
+/**
+  * @brief BSP Tx Transfer completed callback
+  * @retval None
+  * @note empty (up to the user to fill it in or to remove it if useless)
+  */
+__weak void BSP_SD_WriteCpltCallback(void)
+{
+
+}
+
+/**
+  * @brief BSP Rx Transfer completed callback
+  * @retval None
+  * @note empty (up to the user to fill it in or to remove it if useless)
+  */
+__weak void BSP_SD_ReadCpltCallback(void)
+{
+
+}
+/* USER CODE END CallBacksSection_C */
+#endif
+
+/**
+ * @brief  Detects if SD card is correctly plugged in the memory slot or not.
+ * @param  None
+ * @retval Returns if SD is detected or not
+ */
+__weak uint8_t BSP_SD_IsDetected(void)
+{
+  __IO uint8_t status = SD_PRESENT;
+
+  if (BSP_PlatformIsDetected() == 0x0)
+  {
+    status = SD_NOT_PRESENT;
+  }
+
+  return status;
+}
+
+/* USER CODE BEGIN AdditionalCode */
+/* user code can be inserted here */
+/* USER CODE END AdditionalCode */
diff --git a/FATFS/Target/bsp_driver_sd.h b/FATFS/Target/bsp_driver_sd.h
new file mode 100644
index 0000000..9ce3165
--- /dev/null
+++ b/FATFS/Target/bsp_driver_sd.h
@@ -0,0 +1,91 @@
+/* USER CODE BEGIN Header */
+/**
+ ******************************************************************************
+  * @file    bsp_driver_sd.h for F4 (based on stm324x9i_eval_sd.h)
+  * @brief   This file contains the common defines and functions prototypes for
+  *          the bsp_driver_sd.c driver.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2022 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4_SD_H
+#define __STM32F4_SD_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal.h"
+#include "fatfs_platform.h"
+
+/* Exported types --------------------------------------------------------*/
+/**
+  * @brief SD Card information structure
+  */
+#define BSP_SD_CardInfo HAL_SD_CardInfoTypeDef
+
+/* Exported constants --------------------------------------------------------*/
+/**
+  * @brief  SD status structure definition
+  */
+#define   MSD_OK                        ((uint8_t)0x00)
+#define   MSD_ERROR                     ((uint8_t)0x01)
+
+/**
+  * @brief  SD transfer state definition
+  */
+#define   SD_TRANSFER_OK                ((uint8_t)0x00)
+#define   SD_TRANSFER_BUSY              ((uint8_t)0x01)
+
+#define SD_PRESENT               ((uint8_t)0x01)
+#define SD_NOT_PRESENT           ((uint8_t)0x00)
+#define SD_DATATIMEOUT           ((uint32_t)100000000)
+
+#ifdef OLD_API
+/* kept to avoid issue when migrating old projects. */
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+#else
+/* USER CODE BEGIN BSP_H_CODE */
+/* Exported functions --------------------------------------------------------*/
+uint8_t BSP_SD_Init(void);
+uint8_t BSP_SD_ITConfig(void);
+void    BSP_SD_DetectIT(void);
+void    BSP_SD_DetectCallback(void);
+uint8_t BSP_SD_ReadBlocks(uint32_t *pData, uint32_t ReadAddr, uint32_t NumOfBlocks, uint32_t Timeout);
+uint8_t BSP_SD_WriteBlocks(uint32_t *pData, uint32_t WriteAddr, uint32_t NumOfBlocks, uint32_t Timeout);
+uint8_t BSP_SD_ReadBlocks_DMA(uint32_t *pData, uint32_t ReadAddr, uint32_t NumOfBlocks);
+uint8_t BSP_SD_WriteBlocks_DMA(uint32_t *pData, uint32_t WriteAddr, uint32_t NumOfBlocks);
+uint8_t BSP_SD_Erase(uint32_t StartAddr, uint32_t EndAddr);
+void BSP_SD_IRQHandler(void);
+void BSP_SD_DMA_Tx_IRQHandler(void);
+void BSP_SD_DMA_Rx_IRQHandler(void);
+uint8_t BSP_SD_GetCardState(void);
+void    BSP_SD_GetCardInfo(HAL_SD_CardInfoTypeDef *CardInfo);
+uint8_t BSP_SD_IsDetected(void);
+
+/* These functions can be modified in case the current settings (e.g. DMA stream)
+   need to be changed for specific application needs */
+void    BSP_SD_AbortCallback(void);
+void    BSP_SD_WriteCpltCallback(void);
+void    BSP_SD_ReadCpltCallback(void);
+/* USER CODE END BSP_H_CODE */
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4_SD_H */
diff --git a/FATFS/Target/fatfs_platform.c b/FATFS/Target/fatfs_platform.c
new file mode 100644
index 0000000..26e4df7
--- /dev/null
+++ b/FATFS/Target/fatfs_platform.c
@@ -0,0 +1,32 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file           : fatfs_platform.c
+  * @brief          : fatfs_platform source file
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2022 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+*/
+/* USER CODE END Header */
+#include "fatfs_platform.h"
+
+uint8_t	BSP_PlatformIsDetected(void) {
+    uint8_t status = SD_PRESENT;
+    /* Check SD card detect pin */
+    if(HAL_GPIO_ReadPin(SD_DETECT_GPIO_PORT, SD_DETECT_PIN) != GPIO_PIN_RESET)
+    {
+        status = SD_NOT_PRESENT;
+    }
+    /* USER CODE BEGIN 1 */
+    /* user code can be inserted here */
+    /* USER CODE END 1 */
+    return status;
+}
diff --git a/FATFS/Target/fatfs_platform.h b/FATFS/Target/fatfs_platform.h
new file mode 100644
index 0000000..ff428b7
--- /dev/null
+++ b/FATFS/Target/fatfs_platform.h
@@ -0,0 +1,27 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file           : fatfs_platform.h
+  * @brief          : fatfs_platform header file
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2022 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+*/
+/* USER CODE END Header */
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal.h"
+/* Defines ------------------------------------------------------------------*/
+#define SD_PRESENT               ((uint8_t)0x01)  /* also in bsp_driver_sd.h */
+#define SD_NOT_PRESENT           ((uint8_t)0x00)  /* also in bsp_driver_sd.h */
+#define SD_DETECT_PIN         GPIO_PIN_2
+#define SD_DETECT_GPIO_PORT   GPIOG
+/* Prototypes ---------------------------------------------------------------*/
+uint8_t	BSP_PlatformIsDetected(void);
diff --git a/FATFS/Target/ffconf.h b/FATFS/Target/ffconf.h
new file mode 100644
index 0000000..0339a65
--- /dev/null
+++ b/FATFS/Target/ffconf.h
@@ -0,0 +1,270 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  *  FatFs - Generic FAT file system module  R0.12c (C)ChaN, 2017
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2022 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+#ifndef _FFCONF
+#define _FFCONF 68300	/* Revision ID */
+
+/*-----------------------------------------------------------------------------/
+/ Additional user header to be used
+/-----------------------------------------------------------------------------*/
+#include "main.h"
+#include "stm32f4xx_hal.h"
+#include "bsp_driver_sd.h"
+#include "cmsis_os.h" /* _FS_REENTRANT set to 1 and CMSIS API chosen */
+
+/*-----------------------------------------------------------------------------/
+/ Function Configurations
+/-----------------------------------------------------------------------------*/
+
+#define _FS_READONLY         0      /* 0:Read/Write or 1:Read only */
+/* This option switches read-only configuration. (0:Read/Write or 1:Read-only)
+/  Read-only configuration removes writing API functions, f_write(), f_sync(),
+/  f_unlink(), f_mkdir(), f_chmod(), f_rename(), f_truncate(), f_getfree()
+/  and optional writing functions as well. */
+
+#define _FS_MINIMIZE         0      /* 0 to 3 */
+/* This option defines minimization level to remove some basic API functions.
+/
+/   0: All basic functions are enabled.
+/   1: f_stat(), f_getfree(), f_unlink(), f_mkdir(), f_truncate() and f_rename()
+/      are removed.
+/   2: f_opendir(), f_readdir() and f_closedir() are removed in addition to 1.
+/   3: f_lseek() function is removed in addition to 2. */
+
+#define _USE_STRFUNC         2      /* 0:Disable or 1-2:Enable */
+/* This option switches string functions, f_gets(), f_putc(), f_puts() and
+/  f_printf().
+/
+/  0: Disable string functions.
+/  1: Enable without LF-CRLF conversion.
+/  2: Enable with LF-CRLF conversion. */
+
+#define _USE_FIND            0
+/* This option switches filtered directory read functions, f_findfirst() and
+/  f_findnext(). (0:Disable, 1:Enable 2:Enable with matching altname[] too) */
+
+#define _USE_MKFS            1
+/* This option switches f_mkfs() function. (0:Disable or 1:Enable) */
+
+#define _USE_FASTSEEK        1
+/* This option switches fast seek feature. (0:Disable or 1:Enable) */
+
+#define	_USE_EXPAND		0
+/* This option switches f_expand function. (0:Disable or 1:Enable) */
+
+#define _USE_CHMOD		0
+/* This option switches attribute manipulation functions, f_chmod() and f_utime().
+/  (0:Disable or 1:Enable) Also _FS_READONLY needs to be 0 to enable this option. */
+
+#define _USE_LABEL           0
+/* This option switches volume label functions, f_getlabel() and f_setlabel().
+/  (0:Disable or 1:Enable) */
+
+#define _USE_FORWARD         0
+/* This option switches f_forward() function. (0:Disable or 1:Enable) */
+
+/*-----------------------------------------------------------------------------/
+/ Locale and Namespace Configurations
+/-----------------------------------------------------------------------------*/
+
+#define _CODE_PAGE         850
+/* This option specifies the OEM code page to be used on the target system.
+/  Incorrect setting of the code page can cause a file open failure.
+/
+/   1   - ASCII (No extended character. Non-LFN cfg. only)
+/   437 - U.S.
+/   720 - Arabic
+/   737 - Greek
+/   771 - KBL
+/   775 - Baltic
+/   850 - Latin 1
+/   852 - Latin 2
+/   855 - Cyrillic
+/   857 - Turkish
+/   860 - Portuguese
+/   861 - Icelandic
+/   862 - Hebrew
+/   863 - Canadian French
+/   864 - Arabic
+/   865 - Nordic
+/   866 - Russian
+/   869 - Greek 2
+/   932 - Japanese (DBCS)
+/   936 - Simplified Chinese (DBCS)
+/   949 - Korean (DBCS)
+/   950 - Traditional Chinese (DBCS)
+*/
+
+#define _USE_LFN     0    /* 0 to 3 */
+#define _MAX_LFN     255  /* Maximum LFN length to handle (12 to 255) */
+/* The _USE_LFN switches the support of long file name (LFN).
+/
+/   0: Disable support of LFN. _MAX_LFN has no effect.
+/   1: Enable LFN with static working buffer on the BSS. Always NOT thread-safe.
+/   2: Enable LFN with dynamic working buffer on the STACK.
+/   3: Enable LFN with dynamic working buffer on the HEAP.
+/
+/  To enable the LFN, Unicode handling functions (option/unicode.c) must be added
+/  to the project. The working buffer occupies (_MAX_LFN + 1) * 2 bytes and
+/  additional 608 bytes at exFAT enabled. _MAX_LFN can be in range from 12 to 255.
+/  It should be set 255 to support full featured LFN operations.
+/  When use stack for the working buffer, take care on stack overflow. When use heap
+/  memory for the working buffer, memory management functions, ff_memalloc() and
+/  ff_memfree(), must be added to the project. */
+
+#define _LFN_UNICODE    0 /* 0:ANSI/OEM or 1:Unicode */
+/* This option switches character encoding on the API. (0:ANSI/OEM or 1:UTF-16)
+/  To use Unicode string for the path name, enable LFN and set _LFN_UNICODE = 1.
+/  This option also affects behavior of string I/O functions. */
+
+#define _STRF_ENCODE    3
+/* When _LFN_UNICODE == 1, this option selects the character encoding ON THE FILE to
+/  be read/written via string I/O functions, f_gets(), f_putc(), f_puts and f_printf().
+/
+/  0: ANSI/OEM
+/  1: UTF-16LE
+/  2: UTF-16BE
+/  3: UTF-8
+/
+/  This option has no effect when _LFN_UNICODE == 0. */
+
+#define _FS_RPATH       0 /* 0 to 2 */
+/* This option configures support of relative path.
+/
+/   0: Disable relative path and remove related functions.
+/   1: Enable relative path. f_chdir() and f_chdrive() are available.
+/   2: f_getcwd() function is available in addition to 1.
+*/
+
+/*---------------------------------------------------------------------------/
+/ Drive/Volume Configurations
+/----------------------------------------------------------------------------*/
+
+#define _VOLUMES    1
+/* Number of volumes (logical drives) to be used. */
+
+/* USER CODE BEGIN Volumes */
+#define _STR_VOLUME_ID          0	/* 0:Use only 0-9 for drive ID, 1:Use strings for drive ID */
+#define _VOLUME_STRS            "RAM","NAND","CF","SD1","SD2","USB1","USB2","USB3"
+/* _STR_VOLUME_ID switches string support of volume ID.
+/  When _STR_VOLUME_ID is set to 1, also pre-defined strings can be used as drive
+/  number in the path name. _VOLUME_STRS defines the drive ID strings for each
+/  logical drives. Number of items must be equal to _VOLUMES. Valid characters for
+/  the drive ID strings are: A-Z and 0-9. */
+/* USER CODE END Volumes */
+
+#define _MULTI_PARTITION     0 /* 0:Single partition, 1:Multiple partition */
+/* This option switches support of multi-partition on a physical drive.
+/  By default (0), each logical drive number is bound to the same physical drive
+/  number and only an FAT volume found on the physical drive will be mounted.
+/  When multi-partition is enabled (1), each logical drive number can be bound to
+/  arbitrary physical drive and partition listed in the VolToPart[]. Also f_fdisk()
+/  function will be available. */
+#define _MIN_SS    512  /* 512, 1024, 2048 or 4096 */
+#define _MAX_SS    512  /* 512, 1024, 2048 or 4096 */
+/* These options configure the range of sector size to be supported. (512, 1024,
+/  2048 or 4096) Always set both 512 for most systems, all type of memory cards and
+/  harddisk. But a larger value may be required for on-board flash memory and some
+/  type of optical media. When _MAX_SS is larger than _MIN_SS, FatFs is configured
+/  to variable sector size and GET_SECTOR_SIZE command must be implemented to the
+/  disk_ioctl() function. */
+
+#define	_USE_TRIM      0
+/* This option switches support of ATA-TRIM. (0:Disable or 1:Enable)
+/  To enable Trim function, also CTRL_TRIM command should be implemented to the
+/  disk_ioctl() function. */
+
+#define _FS_NOFSINFO    0 /* 0,1,2 or 3 */
+/* If you need to know correct free space on the FAT32 volume, set bit 0 of this
+/  option, and f_getfree() function at first time after volume mount will force
+/  a full FAT scan. Bit 1 controls the use of last allocated cluster number.
+/
+/  bit0=0: Use free cluster count in the FSINFO if available.
+/  bit0=1: Do not trust free cluster count in the FSINFO.
+/  bit1=0: Use last allocated cluster number in the FSINFO if available.
+/  bit1=1: Do not trust last allocated cluster number in the FSINFO.
+*/
+
+/*---------------------------------------------------------------------------/
+/ System Configurations
+/----------------------------------------------------------------------------*/
+
+#define _FS_TINY    0      /* 0:Normal or 1:Tiny */
+/* This option switches tiny buffer configuration. (0:Normal or 1:Tiny)
+/  At the tiny configuration, size of file object (FIL) is reduced _MAX_SS bytes.
+/  Instead of private sector buffer eliminated from the file object, common sector
+/  buffer in the file system object (FATFS) is used for the file data transfer. */
+
+#define _FS_EXFAT	0
+/* This option switches support of exFAT file system. (0:Disable or 1:Enable)
+/  When enable exFAT, also LFN needs to be enabled. (_USE_LFN >= 1)
+/  Note that enabling exFAT discards C89 compatibility. */
+
+#define _FS_NORTC	0
+#define _NORTC_MON	6
+#define _NORTC_MDAY	4
+#define _NORTC_YEAR	2015
+/* The option _FS_NORTC switches timestamp functiton. If the system does not have
+/  any RTC function or valid timestamp is not needed, set _FS_NORTC = 1 to disable
+/  the timestamp function. All objects modified by FatFs will have a fixed timestamp
+/  defined by _NORTC_MON, _NORTC_MDAY and _NORTC_YEAR in local time.
+/  To enable timestamp function (_FS_NORTC = 0), get_fattime() function need to be
+/  added to the project to get current time form real-time clock. _NORTC_MON,
+/  _NORTC_MDAY and _NORTC_YEAR have no effect.
+/  These options have no effect at read-only configuration (_FS_READONLY = 1). */
+
+#define _FS_LOCK    2     /* 0:Disable or >=1:Enable */
+/* The option _FS_LOCK switches file lock function to control duplicated file open
+/  and illegal operation to open objects. This option must be 0 when _FS_READONLY
+/  is 1.
+/
+/  0:  Disable file lock function. To avoid volume corruption, application program
+/      should avoid illegal open, remove and rename to the open objects.
+/  >0: Enable file lock function. The value defines how many files/sub-directories
+/      can be opened simultaneously under file lock control. Note that the file
+/      lock control is independent of re-entrancy. */
+
+#define _FS_REENTRANT    1  /* 0:Disable or 1:Enable */
+
+#define _USE_MUTEX       0 /* 0:Disable or 1:Enable */
+#define _FS_TIMEOUT      1000 /* Timeout period in unit of time ticks */
+#define _SYNC_t          osSemaphoreId_t
+/* The option _FS_REENTRANT switches the re-entrancy (thread safe) of the FatFs
+/  module itself. Note that regardless of this option, file access to different
+/  volume is always re-entrant and volume control functions, f_mount(), f_mkfs()
+/  and f_fdisk() function, are always not re-entrant. Only file/directory access
+/  to the same volume is under control of this function.
+/
+/   0: Disable re-entrancy. _FS_TIMEOUT and _SYNC_t have no effect.
+/   1: Enable re-entrancy. Also user provided synchronization handlers,
+/      ff_req_grant(), ff_rel_grant(), ff_del_syncobj() and ff_cre_syncobj()
+/      function, must be added to the project. Samples are available in
+/      option/syscall.c.
+/
+/  The _FS_TIMEOUT defines timeout period in unit of time tick.
+/  The _SYNC_t defines O/S dependent sync object type. e.g. HANDLE, ID, OS_EVENT*,
+/  SemaphoreHandle_t and etc.. A header file for O/S definitions needs to be
+/  included somewhere in the scope of ff.h. */
+
+/* define the ff_malloc ff_free macros as FreeRTOS pvPortMalloc and vPortFree macros */
+#if !defined(ff_malloc) && !defined(ff_free)
+#define ff_malloc  pvPortMalloc
+#define ff_free  vPortFree
+#endif
+
+#endif /* _FFCONF */
diff --git a/FATFS/Target/sd_diskio.c b/FATFS/Target/sd_diskio.c
new file mode 100644
index 0000000..70f6945
--- /dev/null
+++ b/FATFS/Target/sd_diskio.c
@@ -0,0 +1,683 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    sd_diskio.c
+  * @brief   SD Disk I/O driver
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2022 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Note: code generation based on sd_diskio_dma_rtos_template_bspv1.c v2.1.4
+   as FreeRTOS is enabled. */
+
+/* USER CODE BEGIN firstSection */
+/* can be used to modify / undefine following code or add new definitions */
+/* USER CODE END firstSection*/
+
+/* Includes ------------------------------------------------------------------*/
+#include "ff_gen_drv.h"
+#include "sd_diskio.h"
+
+#include <string.h>
+#include <stdio.h>
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+
+#define QUEUE_SIZE         (uint32_t) 10
+#define READ_CPLT_MSG      (uint32_t) 1
+#define WRITE_CPLT_MSG     (uint32_t) 2
+/*
+==================================================================
+enable the defines below to send custom rtos messages
+when an error or an abort occurs.
+Notice: depending on the HAL/SD driver the HAL_SD_ErrorCallback()
+may not be available.
+See BSP_SD_ErrorCallback() and BSP_SD_AbortCallback() below
+==================================================================
+
+#define RW_ERROR_MSG       (uint32_t) 3
+#define RW_ABORT_MSG       (uint32_t) 4
+*/
+/*
+ * the following Timeout is useful to give the control back to the applications
+ * in case of errors in either BSP_SD_ReadCpltCallback() or BSP_SD_WriteCpltCallback()
+ * the value by default is as defined in the BSP platform driver otherwise 30 secs
+ */
+#define SD_TIMEOUT 30 * 1000
+
+#define SD_DEFAULT_BLOCK_SIZE 512
+
+/*
+ * Depending on the use case, the SD card initialization could be done at the
+ * application level: if it is the case define the flag below to disable
+ * the BSP_SD_Init() call in the SD_Initialize() and add a call to
+ * BSP_SD_Init() elsewhere in the application.
+ */
+/* USER CODE BEGIN disableSDInit */
+/* #define DISABLE_SD_INIT */
+/* USER CODE END disableSDInit */
+
+/*
+ * when using cacheable memory region, it may be needed to maintain the cache
+ * validity. Enable the define below to activate a cache maintenance at each
+ * read and write operation.
+ * Notice: This is applicable only for cortex M7 based platform.
+ */
+/* USER CODE BEGIN enableSDDmaCacheMaintenance */
+/* #define ENABLE_SD_DMA_CACHE_MAINTENANCE  1 */
+/* USER CODE END enableSDDmaCacheMaintenance */
+
+/*
+* Some DMA requires 4-Byte aligned address buffer to correctly read/write data,
+* in FatFs some accesses aren't thus we need a 4-byte aligned scratch buffer to correctly
+* transfer data
+*/
+/* USER CODE BEGIN enableScratchBuffer */
+/* #define ENABLE_SCRATCH_BUFFER */
+/* USER CODE END enableScratchBuffer */
+
+/* Private variables ---------------------------------------------------------*/
+#if defined(ENABLE_SCRATCH_BUFFER)
+#if defined (ENABLE_SD_DMA_CACHE_MAINTENANCE)
+ALIGN_32BYTES(static uint8_t scratch[BLOCKSIZE]); // 32-Byte aligned for cache maintenance
+#else
+__ALIGN_BEGIN static uint8_t scratch[BLOCKSIZE] __ALIGN_END;
+#endif
+#endif
+/* Disk status */
+static volatile DSTATUS Stat = STA_NOINIT;
+
+#if (osCMSIS <= 0x20000U)
+static osMessageQId SDQueueID = NULL;
+#else
+static osMessageQueueId_t SDQueueID = NULL;
+#endif
+/* Private function prototypes -----------------------------------------------*/
+static DSTATUS SD_CheckStatus(BYTE lun);
+DSTATUS SD_initialize (BYTE);
+DSTATUS SD_status (BYTE);
+DRESULT SD_read (BYTE, BYTE*, DWORD, UINT);
+#if _USE_WRITE == 1
+DRESULT SD_write (BYTE, const BYTE*, DWORD, UINT);
+#endif /* _USE_WRITE == 1 */
+#if _USE_IOCTL == 1
+DRESULT SD_ioctl (BYTE, BYTE, void*);
+#endif  /* _USE_IOCTL == 1 */
+
+const Diskio_drvTypeDef  SD_Driver =
+{
+  SD_initialize,
+  SD_status,
+  SD_read,
+#if  _USE_WRITE == 1
+  SD_write,
+#endif /* _USE_WRITE == 1 */
+
+#if  _USE_IOCTL == 1
+  SD_ioctl,
+#endif /* _USE_IOCTL == 1 */
+};
+
+/* USER CODE BEGIN beforeFunctionSection */
+/* can be used to modify / undefine following code or add new code */
+/* USER CODE END beforeFunctionSection */
+
+/* Private functions ---------------------------------------------------------*/
+
+static int SD_CheckStatusWithTimeout(uint32_t timeout)
+{
+  uint32_t timer;
+  /* block until SDIO peripheral is ready again or a timeout occur */
+#if (osCMSIS <= 0x20000U)
+  timer = osKernelSysTick();
+  while( osKernelSysTick() - timer < timeout)
+#else
+  timer = osKernelGetTickCount();
+  while( osKernelGetTickCount() - timer < timeout)
+#endif
+  {
+    if (BSP_SD_GetCardState() == SD_TRANSFER_OK)
+    {
+      return 0;
+    }
+  }
+
+  return -1;
+}
+
+static DSTATUS SD_CheckStatus(BYTE lun)
+{
+  Stat = STA_NOINIT;
+
+  if(BSP_SD_GetCardState() == SD_TRANSFER_OK)
+  {
+    Stat &= ~STA_NOINIT;
+  }
+
+  return Stat;
+}
+
+/**
+  * @brief  Initializes a Drive
+  * @param  lun : not used
+  * @retval DSTATUS: Operation status
+  */
+DSTATUS SD_initialize(BYTE lun)
+{
+Stat = STA_NOINIT;
+
+  /*
+   * check that the kernel has been started before continuing
+   * as the osMessage API will fail otherwise
+   */
+#if (osCMSIS <= 0x20000U)
+  if(osKernelRunning())
+#else
+  if(osKernelGetState() == osKernelRunning)
+#endif
+  {
+#if !defined(DISABLE_SD_INIT)
+
+    if(BSP_SD_Init() == MSD_OK)
+    {
+      Stat = SD_CheckStatus(lun);
+    }
+
+#else
+    Stat = SD_CheckStatus(lun);
+#endif
+
+    /*
+    * if the SD is correctly initialized, create the operation queue
+    * if not already created
+    */
+
+    if (Stat != STA_NOINIT)
+    {
+      if (SDQueueID == NULL)
+      {
+ #if (osCMSIS <= 0x20000U)
+      osMessageQDef(SD_Queue, QUEUE_SIZE, uint16_t);
+      SDQueueID = osMessageCreate (osMessageQ(SD_Queue), NULL);
+#else
+      SDQueueID = osMessageQueueNew(QUEUE_SIZE, 2, NULL);
+#endif
+      }
+
+      if (SDQueueID == NULL)
+      {
+        Stat |= STA_NOINIT;
+      }
+    }
+  }
+
+  return Stat;
+}
+
+/**
+  * @brief  Gets Disk Status
+  * @param  lun : not used
+  * @retval DSTATUS: Operation status
+  */
+DSTATUS SD_status(BYTE lun)
+{
+  return SD_CheckStatus(lun);
+}
+
+/* USER CODE BEGIN beforeReadSection */
+/* can be used to modify previous code / undefine following code / add new code */
+/* USER CODE END beforeReadSection */
+/**
+  * @brief  Reads Sector(s)
+  * @param  lun : not used
+  * @param  *buff: Data buffer to store read data
+  * @param  sector: Sector address (LBA)
+  * @param  count: Number of sectors to read (1..128)
+  * @retval DRESULT: Operation result
+  */
+
+DRESULT SD_read(BYTE lun, BYTE *buff, DWORD sector, UINT count)
+{
+  uint8_t ret;
+  DRESULT res = RES_ERROR;
+  uint32_t timer;
+#if (osCMSIS < 0x20000U)
+  osEvent event;
+#else
+  uint16_t event;
+  osStatus_t status;
+#endif
+#if (ENABLE_SD_DMA_CACHE_MAINTENANCE == 1)
+  uint32_t alignedAddr;
+#endif
+  /*
+  * ensure the SDCard is ready for a new operation
+  */
+
+  if (SD_CheckStatusWithTimeout(SD_TIMEOUT) < 0)
+  {
+    return res;
+  }
+
+#if defined(ENABLE_SCRATCH_BUFFER)
+  if (!((uint32_t)buff & 0x3))
+  {
+#endif
+    /* Fast path cause destination buffer is correctly aligned */
+    ret = BSP_SD_ReadBlocks_DMA((uint32_t*)buff, (uint32_t)(sector), count);
+
+    if (ret == MSD_OK) {
+#if (osCMSIS < 0x20000U)
+    /* wait for a message from the queue or a timeout */
+    event = osMessageGet(SDQueueID, SD_TIMEOUT);
+
+    if (event.status == osEventMessage)
+    {
+      if (event.value.v == READ_CPLT_MSG)
+      {
+        timer = osKernelSysTick();
+        /* block until SDIO IP is ready or a timeout occur */
+        while(osKernelSysTick() - timer <SD_TIMEOUT)
+#else
+          status = osMessageQueueGet(SDQueueID, (void *)&event, NULL, SD_TIMEOUT);
+          if ((status == osOK) && (event == READ_CPLT_MSG))
+          {
+            timer = osKernelGetTickCount();
+            /* block until SDIO IP is ready or a timeout occur */
+            while(osKernelGetTickCount() - timer <SD_TIMEOUT)
+#endif
+            {
+              if (BSP_SD_GetCardState() == SD_TRANSFER_OK)
+              {
+                res = RES_OK;
+#if (ENABLE_SD_DMA_CACHE_MAINTENANCE == 1)
+                /*
+                the SCB_InvalidateDCache_by_Addr() requires a 32-Byte aligned address,
+                adjust the address and the D-Cache size to invalidate accordingly.
+                */
+                alignedAddr = (uint32_t)buff & ~0x1F;
+                SCB_InvalidateDCache_by_Addr((uint32_t*)alignedAddr, count*BLOCKSIZE + ((uint32_t)buff - alignedAddr));
+#endif
+                break;
+              }
+            }
+#if (osCMSIS < 0x20000U)
+          }
+        }
+#else
+      }
+#endif
+    }
+
+#if defined(ENABLE_SCRATCH_BUFFER)
+    }
+    else
+    {
+      /* Slow path, fetch each sector a part and memcpy to destination buffer */
+      int i;
+
+      for (i = 0; i < count; i++)
+      {
+        ret = BSP_SD_ReadBlocks_DMA((uint32_t*)scratch, (uint32_t)sector++, 1);
+        if (ret == MSD_OK )
+        {
+          /* wait until the read is successful or a timeout occurs */
+#if (osCMSIS < 0x20000U)
+          /* wait for a message from the queue or a timeout */
+          event = osMessageGet(SDQueueID, SD_TIMEOUT);
+
+          if (event.status == osEventMessage)
+          {
+            if (event.value.v == READ_CPLT_MSG)
+            {
+              timer = osKernelSysTick();
+              /* block until SDIO IP is ready or a timeout occur */
+              while(osKernelSysTick() - timer <SD_TIMEOUT)
+#else
+                status = osMessageQueueGet(SDQueueID, (void *)&event, NULL, SD_TIMEOUT);
+              if ((status == osOK) && (event == READ_CPLT_MSG))
+              {
+                timer = osKernelGetTickCount();
+                /* block until SDIO IP is ready or a timeout occur */
+                ret = MSD_ERROR;
+                while(osKernelGetTickCount() - timer < SD_TIMEOUT)
+#endif
+                {
+                  ret = BSP_SD_GetCardState();
+
+                  if (ret == MSD_OK)
+                  {
+                    break;
+                  }
+                }
+
+                if (ret != MSD_OK)
+                {
+                  break;
+                }
+#if (osCMSIS < 0x20000U)
+              }
+            }
+#else
+          }
+#endif
+#if (ENABLE_SD_DMA_CACHE_MAINTENANCE == 1)
+          /*
+          *
+          * invalidate the scratch buffer before the next read to get the actual data instead of the cached one
+          */
+          SCB_InvalidateDCache_by_Addr((uint32_t*)scratch, BLOCKSIZE);
+#endif
+          memcpy(buff, scratch, BLOCKSIZE);
+          buff += BLOCKSIZE;
+        }
+        else
+        {
+          break;
+        }
+      }
+
+      if ((i == count) && (ret == MSD_OK ))
+        res = RES_OK;
+    }
+#endif
+  return res;
+}
+
+/* USER CODE BEGIN beforeWriteSection */
+/* can be used to modify previous code / undefine following code / add new code */
+/* USER CODE END beforeWriteSection */
+/**
+  * @brief  Writes Sector(s)
+  * @param  lun : not used
+  * @param  *buff: Data to be written
+  * @param  sector: Sector address (LBA)
+  * @param  count: Number of sectors to write (1..128)
+  * @retval DRESULT: Operation result
+  */
+#if _USE_WRITE == 1
+
+DRESULT SD_write(BYTE lun, const BYTE *buff, DWORD sector, UINT count)
+{
+  DRESULT res = RES_ERROR;
+  uint32_t timer;
+
+#if (osCMSIS < 0x20000U)
+  osEvent event;
+#else
+  uint16_t event;
+  osStatus_t status;
+#endif
+
+#if defined(ENABLE_SCRATCH_BUFFER)
+  int32_t ret;
+#endif
+
+  /*
+  * ensure the SDCard is ready for a new operation
+  */
+
+  if (SD_CheckStatusWithTimeout(SD_TIMEOUT) < 0)
+  {
+    return res;
+  }
+
+#if defined(ENABLE_SCRATCH_BUFFER)
+  if (!((uint32_t)buff & 0x3))
+  {
+#endif
+#if (ENABLE_SD_DMA_CACHE_MAINTENANCE == 1)
+  uint32_t alignedAddr;
+  /*
+    the SCB_CleanDCache_by_Addr() requires a 32-Byte aligned address
+    adjust the address and the D-Cache size to clean accordingly.
+  */
+  alignedAddr = (uint32_t)buff & ~0x1F;
+  SCB_CleanDCache_by_Addr((uint32_t*)alignedAddr, count*BLOCKSIZE + ((uint32_t)buff - alignedAddr));
+#endif
+
+  if(BSP_SD_WriteBlocks_DMA((uint32_t*)buff,
+                           (uint32_t) (sector),
+                           count) == MSD_OK)
+  {
+#if (osCMSIS < 0x20000U)
+    /* Get the message from the queue */
+    event = osMessageGet(SDQueueID, SD_TIMEOUT);
+
+    if (event.status == osEventMessage)
+    {
+      if (event.value.v == WRITE_CPLT_MSG)
+      {
+#else
+    status = osMessageQueueGet(SDQueueID, (void *)&event, NULL, SD_TIMEOUT);
+    if ((status == osOK) && (event == WRITE_CPLT_MSG))
+    {
+#endif
+ #if (osCMSIS < 0x20000U)
+        timer = osKernelSysTick();
+        /* block until SDIO IP is ready or a timeout occur */
+        while(osKernelSysTick() - timer  < SD_TIMEOUT)
+#else
+        timer = osKernelGetTickCount();
+        /* block until SDIO IP is ready or a timeout occur */
+        while(osKernelGetTickCount() - timer  < SD_TIMEOUT)
+#endif
+        {
+          if (BSP_SD_GetCardState() == SD_TRANSFER_OK)
+          {
+            res = RES_OK;
+            break;
+          }
+        }
+#if (osCMSIS < 0x20000U)
+      }
+    }
+#else
+    }
+#endif
+  }
+#if defined(ENABLE_SCRATCH_BUFFER)
+  else {
+    /* Slow path, fetch each sector a part and memcpy to destination buffer */
+    int i;
+
+#if (ENABLE_SD_DMA_CACHE_MAINTENANCE == 1)
+    /*
+     * invalidate the scratch buffer before the next write to get the actual data instead of the cached one
+     */
+     SCB_InvalidateDCache_by_Addr((uint32_t*)scratch, BLOCKSIZE);
+#endif
+      for (i = 0; i < count; i++)
+      {
+        memcpy((void *)scratch, buff, BLOCKSIZE);
+        buff += BLOCKSIZE;
+
+        ret = BSP_SD_WriteBlocks_DMA((uint32_t*)scratch, (uint32_t)sector++, 1);
+        if (ret == MSD_OK )
+        {
+          /* wait until the read is successful or a timeout occurs */
+#if (osCMSIS < 0x20000U)
+          /* wait for a message from the queue or a timeout */
+          event = osMessageGet(SDQueueID, SD_TIMEOUT);
+
+          if (event.status == osEventMessage)
+          {
+            if (event.value.v == READ_CPLT_MSG)
+            {
+              timer = osKernelSysTick();
+              /* block until SDIO IP is ready or a timeout occur */
+              while(osKernelSysTick() - timer <SD_TIMEOUT)
+#else
+                status = osMessageQueueGet(SDQueueID, (void *)&event, NULL, SD_TIMEOUT);
+              if ((status == osOK) && (event == READ_CPLT_MSG))
+              {
+                timer = osKernelGetTickCount();
+                /* block until SDIO IP is ready or a timeout occur */
+                ret = MSD_ERROR;
+                while(osKernelGetTickCount() - timer < SD_TIMEOUT)
+#endif
+                {
+                  ret = BSP_SD_GetCardState();
+
+                  if (ret == MSD_OK)
+                  {
+                    break;
+                  }
+                }
+
+                if (ret != MSD_OK)
+                {
+                  break;
+                }
+#if (osCMSIS < 0x20000U)
+              }
+            }
+#else
+          }
+#endif
+        }
+        else
+        {
+          break;
+        }
+      }
+
+      if ((i == count) && (ret == MSD_OK ))
+        res = RES_OK;
+    }
+
+  }
+#endif
+
+  return res;
+}
+ #endif /* _USE_WRITE == 1 */
+
+/* USER CODE BEGIN beforeIoctlSection */
+/* can be used to modify previous code / undefine following code / add new code */
+/* USER CODE END beforeIoctlSection */
+/**
+  * @brief  I/O control operation
+  * @param  lun : not used
+  * @param  cmd: Control code
+  * @param  *buff: Buffer to send/receive control data
+  * @retval DRESULT: Operation result
+  */
+#if _USE_IOCTL == 1
+DRESULT SD_ioctl(BYTE lun, BYTE cmd, void *buff)
+{
+  DRESULT res = RES_ERROR;
+  BSP_SD_CardInfo CardInfo;
+
+  if (Stat & STA_NOINIT) return RES_NOTRDY;
+
+  switch (cmd)
+  {
+  /* Make sure that no pending write process */
+  case CTRL_SYNC :
+    res = RES_OK;
+    break;
+
+  /* Get number of sectors on the disk (DWORD) */
+  case GET_SECTOR_COUNT :
+    BSP_SD_GetCardInfo(&CardInfo);
+    *(DWORD*)buff = CardInfo.LogBlockNbr;
+    res = RES_OK;
+    break;
+
+  /* Get R/W sector size (WORD) */
+  case GET_SECTOR_SIZE :
+    BSP_SD_GetCardInfo(&CardInfo);
+    *(WORD*)buff = CardInfo.LogBlockSize;
+    res = RES_OK;
+    break;
+
+  /* Get erase block size in unit of sector (DWORD) */
+  case GET_BLOCK_SIZE :
+    BSP_SD_GetCardInfo(&CardInfo);
+    *(DWORD*)buff = CardInfo.LogBlockSize / SD_DEFAULT_BLOCK_SIZE;
+    res = RES_OK;
+    break;
+
+  default:
+    res = RES_PARERR;
+  }
+
+  return res;
+}
+#endif /* _USE_IOCTL == 1 */
+
+/* USER CODE BEGIN afterIoctlSection */
+/* can be used to modify previous code / undefine following code / add new code */
+/* USER CODE END afterIoctlSection */
+
+/* USER CODE BEGIN callbackSection */
+/* can be used to modify / following code or add new code */
+/* USER CODE END callbackSection */
+/**
+  * @brief Tx Transfer completed callbacks
+  * @param hsd: SD handle
+  * @retval None
+  */
+void BSP_SD_WriteCpltCallback(void)
+{
+
+  /*
+   * No need to add an "osKernelRunning()" check here, as the SD_initialize()
+   * is always called before any SD_Read()/SD_Write() call
+   */
+#if (osCMSIS < 0x20000U)
+   osMessagePut(SDQueueID, WRITE_CPLT_MSG, 0);
+#else
+   const uint16_t msg = WRITE_CPLT_MSG;
+   osMessageQueuePut(SDQueueID, (const void *)&msg, NULL, 0);
+#endif
+}
+
+/**
+  * @brief Rx Transfer completed callbacks
+  * @param hsd: SD handle
+  * @retval None
+  */
+void BSP_SD_ReadCpltCallback(void)
+{
+  /*
+   * No need to add an "osKernelRunning()" check here, as the SD_initialize()
+   * is always called before any SD_Read()/SD_Write() call
+   */
+#if (osCMSIS < 0x20000U)
+   osMessagePut(SDQueueID, READ_CPLT_MSG, 0);
+#else
+   const uint16_t msg = READ_CPLT_MSG;
+   osMessageQueuePut(SDQueueID, (const void *)&msg, NULL, 0);
+#endif
+}
+
+/* USER CODE BEGIN ErrorAbortCallbacks */
+/*
+void BSP_SD_AbortCallback(void)
+{
+#if (osCMSIS < 0x20000U)
+   osMessagePut(SDQueueID, RW_ABORT_MSG, 0);
+#else
+   const uint16_t msg = RW_ABORT_MSG;
+   osMessageQueuePut(SDQueueID, (const void *)&msg, NULL, 0);
+#endif
+}
+*/
+/* USER CODE END ErrorAbortCallbacks */
+
+/* USER CODE BEGIN lastSection */
+/* can be used to modify / undefine previous code or add new code */
+/* USER CODE END lastSection */
diff --git a/FATFS/Target/sd_diskio.h b/FATFS/Target/sd_diskio.h
new file mode 100644
index 0000000..71d46f1
--- /dev/null
+++ b/FATFS/Target/sd_diskio.h
@@ -0,0 +1,41 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    sd_diskio.h
+  * @brief   Header for sd_diskio.c module
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2022 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Note: code generation based on sd_diskio_dma_rtos_template.h */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __SD_DISKIO_H
+#define __SD_DISKIO_H
+
+/* USER CODE BEGIN firstSection */
+/* can be used to modify / undefine following code or add new definitions */
+/* USER CODE END firstSection */
+
+/* Includes ------------------------------------------------------------------*/
+#include "bsp_driver_sd.h"
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+extern const Diskio_drvTypeDef  SD_Driver;
+
+/* USER CODE BEGIN lastSection */
+/* can be used to modify / undefine previous code or add new definitions */
+/* USER CODE END lastSection */
+
+#endif /* __SD_DISKIO_H */
diff --git a/Middlewares/ST/STM32_Audio/Addons/PDM/Inc/pdm2pcm_glo.h b/Middlewares/ST/STM32_Audio/Addons/PDM/Inc/pdm2pcm_glo.h
new file mode 100644
index 0000000..4494066
--- /dev/null
+++ b/Middlewares/ST/STM32_Audio/Addons/PDM/Inc/pdm2pcm_glo.h
@@ -0,0 +1,95 @@
+/**
+  ******************************************************************************
+  * @file    pdm2pcm_glo.h
+  * @author  MCD Application Team
+  * @brief   Global header for PDM2PCM conversion code
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Image SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_image_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __PDM2PCM_FILTER_H
+#define __PDM2PCM_FILTER_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include <stdint.h>
+
+/* Exported constants --------------------------------------------------------*/
+#define PDM_FILTER_ENDIANNESS_LE     ((uint16_t)0x0000)
+#define PDM_FILTER_ENDIANNESS_BE     ((uint16_t)0x0001)
+
+#define PDM_FILTER_BIT_ORDER_LSB     ((uint16_t)0x0000)
+#define PDM_FILTER_BIT_ORDER_MSB     ((uint16_t)0x0001)
+
+#define PDM_FILTER_DEC_FACTOR_48     ((uint16_t)0x0001)
+#define PDM_FILTER_DEC_FACTOR_64     ((uint16_t)0x0002)
+#define PDM_FILTER_DEC_FACTOR_80     ((uint16_t)0x0003)
+#define PDM_FILTER_DEC_FACTOR_128    ((uint16_t)0x0004)
+#define PDM_FILTER_DEC_FACTOR_16     ((uint16_t)0x0005)
+#define PDM_FILTER_DEC_FACTOR_24     ((uint16_t)0x0006)
+#define PDM_FILTER_DEC_FACTOR_32     ((uint16_t)0x0007)
+
+#define PDM_FILTER_INIT_ERROR           ((uint16_t)0x0010)
+#define PDM_FILTER_CONFIG_ERROR         ((uint16_t)0x0020)
+#define PDM_FILTER_ENDIANNESS_ERROR     ((uint16_t)0x0001)
+#define PDM_FILTER_BIT_ORDER_ERROR      ((uint16_t)0x0002)
+#define PDM_FILTER_CRC_LOCK_ERROR       ((uint16_t)0x0004)
+#define PDM_FILTER_DECIMATION_ERROR     ((uint16_t)0x0008)
+#define PDM_FILTER_GAIN_ERROR           ((uint16_t)0x0040)
+#define PDM_FILTER_SAMPLES_NUMBER_ERROR ((uint16_t)0x0080)
+#define PDM2PCM_INTERNAL_MEMORY_SIZE 16
+
+/* Exported types ------------------------------------------------------------*/
+typedef struct{
+  uint16_t bit_order;
+  uint16_t endianness;
+  uint32_t high_pass_tap;
+  uint16_t in_ptr_channels;
+  uint16_t out_ptr_channels;
+  uint32_t pInternalMemory[PDM2PCM_INTERNAL_MEMORY_SIZE];
+}PDM_Filter_Handler_t;
+
+typedef struct{
+  uint16_t decimation_factor;
+  uint16_t output_samples_number;
+  int16_t  mic_gain;
+}PDM_Filter_Config_t;
+
+/* Exported macros -----------------------------------------------------------*/
+
+/* Exported functions ------------------------------------------------------- */
+uint32_t PDM_Filter_Init(PDM_Filter_Handler_t *pHandler);
+uint32_t PDM_Filter_setConfig(PDM_Filter_Handler_t *pHandler, PDM_Filter_Config_t *pConfig); 
+uint32_t PDM_Filter_getConfig(PDM_Filter_Handler_t *pHandler, PDM_Filter_Config_t *pConfig);
+uint32_t PDM_Filter_deInterleave(void *pDataIn, void *pDataOut, PDM_Filter_Handler_t * pHandler);
+uint32_t PDM_Filter(void *pDataIn, void *pDataOut, PDM_Filter_Handler_t *pHandler);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __PDM2PCM_FILTER_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/Middlewares/ST/STM32_USB_Host_Library/Class/CDC/Inc/usbh_cdc.h b/Middlewares/ST/STM32_USB_Host_Library/Class/CDC/Inc/usbh_cdc.h
new file mode 100644
index 0000000..3afc137
--- /dev/null
+++ b/Middlewares/ST/STM32_USB_Host_Library/Class/CDC/Inc/usbh_cdc.h
@@ -0,0 +1,448 @@
+/**
+  ******************************************************************************
+  * @file    usbh_cdc.h
+  * @author  MCD Application Team
+  * @brief   This file contains all the prototypes for the usbh_cdc.c
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2015 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                      www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive  ----------------------------------------------*/
+#ifndef __USBH_CDC_H
+#define __USBH_CDC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "usbh_core.h"
+
+
+/** @addtogroup USBH_LIB
+  * @{
+  */
+
+/** @addtogroup USBH_CLASS
+  * @{
+  */
+
+/** @addtogroup USBH_CDC_CLASS
+  * @{
+  */
+
+/** @defgroup USBH_CDC_CORE
+  * @brief This file is the Header file for usbh_core.c
+  * @{
+  */
+
+
+
+
+/*Communication Class codes*/
+#define USB_CDC_CLASS                                           0x02U
+#define COMMUNICATION_INTERFACE_CLASS_CODE                      0x02U
+
+/*Data Interface Class Codes*/
+#define DATA_INTERFACE_CLASS_CODE                               0x0AU
+
+/*Communication sub class codes*/
+#define RESERVED                                                0x00U
+#define DIRECT_LINE_CONTROL_MODEL                               0x01U
+#define ABSTRACT_CONTROL_MODEL                                  0x02U
+#define TELEPHONE_CONTROL_MODEL                                 0x03U
+#define MULTICHANNEL_CONTROL_MODEL                              0x04U
+#define CAPI_CONTROL_MODEL                                      0x05U
+#define ETHERNET_NETWORKING_CONTROL_MODEL                       0x06U
+#define ATM_NETWORKING_CONTROL_MODEL                            0x07U
+
+
+/*Communication Interface Class Control Protocol Codes*/
+#define NO_CLASS_SPECIFIC_PROTOCOL_CODE                         0x00U
+#define COMMON_AT_COMMAND                                       0x01U
+#define VENDOR_SPECIFIC                                         0xFFU
+
+
+#define CS_INTERFACE                                            0x24U
+#define CDC_PAGE_SIZE_64                                        0x40U
+
+/*Class-Specific Request Codes*/
+#define CDC_SEND_ENCAPSULATED_COMMAND                           0x00U
+#define CDC_GET_ENCAPSULATED_RESPONSE                           0x01U
+#define CDC_SET_COMM_FEATURE                                    0x02U
+#define CDC_GET_COMM_FEATURE                                    0x03U
+#define CDC_CLEAR_COMM_FEATURE                                  0x04U
+
+#define CDC_SET_AUX_LINE_STATE                                  0x10U
+#define CDC_SET_HOOK_STATE                                      0x11U
+#define CDC_PULSE_SETUP                                         0x12U
+#define CDC_SEND_PULSE                                          0x13U
+#define CDC_SET_PULSE_TIME                                      0x14U
+#define CDC_RING_AUX_JACK                                       0x15U
+
+#define CDC_SET_LINE_CODING                                     0x20U
+#define CDC_GET_LINE_CODING                                     0x21U
+#define CDC_SET_CONTROL_LINE_STATE                              0x22U
+#define CDC_SEND_BREAK                                          0x23U
+
+#define CDC_SET_RINGER_PARMS                                    0x30U
+#define CDC_GET_RINGER_PARMS                                    0x31U
+#define CDC_SET_OPERATION_PARMS                                 0x32U
+#define CDC_GET_OPERATION_PARMS                                 0x33U
+#define CDC_SET_LINE_PARMS                                      0x34U
+#define CDC_GET_LINE_PARMS                                      0x35U
+#define CDC_DIAL_DIGITS                                         0x36U
+#define CDC_SET_UNIT_PARAMETER                                  0x37U
+#define CDC_GET_UNIT_PARAMETER                                  0x38U
+#define CDC_CLEAR_UNIT_PARAMETER                                0x39U
+#define CDC_GET_PROFILE                                         0x3AU
+
+#define CDC_SET_ETHERNET_MULTICAST_FILTERS                      0x40U
+#define CDC_SET_ETHERNET_POWER_MANAGEMENT_PATTERN FILTER        0x41U
+#define CDC_GET_ETHERNET_POWER_MANAGEMENT_PATTERN FILTER        0x42U
+#define CDC_SET_ETHERNET_PACKET_FILTER                          0x43U
+#define CDC_GET_ETHERNET_STATISTIC                              0x44U
+
+#define CDC_SET_ATM_DATA_FORMAT                                 0x50U
+#define CDC_GET_ATM_DEVICE_STATISTICS                           0x51U
+#define CDC_SET_ATM_DEFAULT_VC                                  0x52U
+#define CDC_GET_ATM_VC_STATISTICS                               0x53U
+
+
+/* wValue for SetControlLineState*/
+#define CDC_ACTIVATE_CARRIER_SIGNAL_RTS                         0x0002U
+#define CDC_DEACTIVATE_CARRIER_SIGNAL_RTS                       0x0000U
+#define CDC_ACTIVATE_SIGNAL_DTR                                 0x0001U
+#define CDC_DEACTIVATE_SIGNAL_DTR                               0x0000U
+
+#define LINE_CODING_STRUCTURE_SIZE                              0x07U
+/**
+  * @}
+  */
+
+/** @defgroup USBH_CDC_CORE_Exported_Types
+  * @{
+  */
+
+/* States for CDC State Machine */
+typedef enum
+{
+  CDC_IDLE = 0U,
+  CDC_SEND_DATA,
+  CDC_SEND_DATA_WAIT,
+  CDC_RECEIVE_DATA,
+  CDC_RECEIVE_DATA_WAIT,
+}
+CDC_DataStateTypeDef;
+
+typedef enum
+{
+  CDC_IDLE_STATE = 0U,
+  CDC_SET_LINE_CODING_STATE,
+  CDC_GET_LAST_LINE_CODING_STATE,
+  CDC_TRANSFER_DATA,
+  CDC_ERROR_STATE,
+}
+CDC_StateTypeDef;
+
+
+/*Line coding structure*/
+typedef union _CDC_LineCodingStructure
+{
+  uint8_t Array[LINE_CODING_STRUCTURE_SIZE];
+
+  struct
+  {
+
+    uint32_t             dwDTERate;     /*Data terminal rate, in bits per second*/
+    uint8_t              bCharFormat;   /*Stop bits
+    0 - 1 Stop bit
+    1 - 1.5 Stop bits
+    2 - 2 Stop bits*/
+    uint8_t              bParityType;   /* Parity
+    0 - None
+    1 - Odd
+    2 - Even
+    3 - Mark
+    4 - Space*/
+    uint8_t                bDataBits;     /* Data bits (5, 6, 7, 8 or 16). */
+  } b;
+}
+CDC_LineCodingTypeDef;
+
+
+
+/* Header Functional Descriptor
+--------------------------------------------------------------------------------
+Offset|  field              | Size  |    Value   |   Description
+------|---------------------|-------|------------|------------------------------
+0     |  bFunctionLength    | 1     |   number   |  Size of this descriptor.
+1     |  bDescriptorType    | 1     |   Constant |  CS_INTERFACE (0x24)
+2     |  bDescriptorSubtype | 1     |   Constant |  Identifier (ID) of functional
+      |                     |       |            | descriptor.
+3     |  bcdCDC             | 2     |            |
+      |                     |       |   Number   | USB Class Definitions for
+      |                     |       |            | Communication Devices Specification
+      |                     |       |            | release number in binary-coded
+      |                     |       |            | decimal
+------|---------------------|-------|------------|------------------------------
+  */
+typedef struct _FunctionalDescriptorHeader
+{
+  uint8_t     bLength;            /*Size of this descriptor.*/
+  uint8_t     bDescriptorType;    /*CS_INTERFACE (0x24)*/
+  uint8_t     bDescriptorSubType; /* Header functional descriptor subtype as*/
+  uint16_t    bcdCDC;             /* USB Class Definitions for Communication
+                                    Devices Specification release number in
+                                  binary-coded decimal. */
+}
+CDC_HeaderFuncDesc_TypeDef;
+/* Call Management Functional Descriptor
+--------------------------------------------------------------------------------
+Offset|  field              | Size  |    Value   |   Description
+------|---------------------|-------|------------|------------------------------
+0     |  bFunctionLength    | 1     |   number   |  Size of this descriptor.
+1     |  bDescriptorType    | 1     |   Constant |  CS_INTERFACE (0x24)
+2     |  bDescriptorSubtype | 1     |   Constant |  Call Management functional
+      |                     |       |            |  descriptor subtype.
+3     |  bmCapabilities     | 1     |   Bitmap   | The capabilities that this configuration
+      |                     |       |            | supports:
+      |                     |       |            | D7..D2: RESERVED (Reset to zero)
+      |                     |       |            | D1: 0 - Device sends/receives call
+      |                     |       |            | management information only over
+      |                     |       |            | the Communication Class
+      |                     |       |            | interface.
+      |                     |       |            | 1 - Device can send/receive call
+      |                     \       |            | management information over a
+      |                     |       |            | Data Class interface.
+      |                     |       |            | D0: 0 - Device does not handle call
+      |                     |       |            | management itself.
+      |                     |       |            | 1 - Device handles call
+      |                     |       |            | management itself.
+      |                     |       |            | The previous bits, in combination, identify
+      |                     |       |            | which call management scenario is used. If bit
+      |                     |       |            | D0 is reset to 0, then the value of bit D1 is
+      |                     |       |            | ignored. In this case, bit D1 is reset to zero for
+      |                     |       |            | future compatibility.
+4     | bDataInterface      | 1     | Number     | Interface number of Data Class interface
+      |                     |       |            | optionally used for call management.
+------|---------------------|-------|------------|------------------------------
+  */
+typedef struct _CallMgmtFunctionalDescriptor
+{
+  uint8_t    bLength;            /*Size of this functional descriptor, in bytes.*/
+  uint8_t    bDescriptorType;    /*CS_INTERFACE (0x24)*/
+  uint8_t    bDescriptorSubType; /* Call Management functional descriptor subtype*/
+  uint8_t    bmCapabilities;      /* bmCapabilities: D0+D1 */
+  uint8_t    bDataInterface;      /*bDataInterface: 1*/
+}
+CDC_CallMgmtFuncDesc_TypeDef;
+/* Abstract Control Management Functional Descriptor
+--------------------------------------------------------------------------------
+Offset|  field              | Size  |    Value   |   Description
+------|---------------------|-------|------------|------------------------------
+0     |  bFunctionLength    | 1     |   number   |  Size of functional descriptor, in bytes.
+1     |  bDescriptorType    | 1     |   Constant |  CS_INTERFACE (0x24)
+2     |  bDescriptorSubtype | 1     |   Constant |  Abstract Control Management
+      |                     |       |            |  functional  descriptor subtype.
+3     |  bmCapabilities     | 1     |   Bitmap   | The capabilities that this configuration
+      |                     |       |            | supports ((A bit value of zero means that the
+      |                     |       |            | request is not supported.) )
+                                                   D7..D4: RESERVED (Reset to zero)
+      |                     |       |            | D3: 1 - Device supports the notification
+      |                     |       |            | Network_Connection.
+      |                     |       |            | D2: 1 - Device supports the request
+      |                     |       |            | Send_Break
+      |                     |       |            | D1: 1 - Device supports the request
+      |                     \       |            | combination of Set_Line_Coding,
+      |                     |       |            | Set_Control_Line_State, Get_Line_Coding, and the
+                                                   notification Serial_State.
+      |                     |       |            | D0: 1 - Device supports the request
+      |                     |       |            | combination of Set_Comm_Feature,
+      |                     |       |            | Clear_Comm_Feature, and Get_Comm_Feature.
+      |                     |       |            | The previous bits, in combination, identify
+      |                     |       |            | which requests/notifications are supported by
+      |                     |       |            | a Communication Class interface with the
+      |                     |       |            |   SubClass code of Abstract Control Model.
+------|---------------------|-------|------------|------------------------------
+  */
+typedef struct _AbstractCntrlMgmtFunctionalDescriptor
+{
+  uint8_t    bLength;            /*Size of this functional descriptor, in bytes.*/
+  uint8_t    bDescriptorType;    /*CS_INTERFACE (0x24)*/
+  uint8_t    bDescriptorSubType; /* Abstract Control Management functional
+                                  descriptor subtype*/
+  uint8_t    bmCapabilities;      /* The capabilities that this configuration supports */
+}
+CDC_AbstCntrlMgmtFuncDesc_TypeDef;
+/* Union Functional Descriptor
+--------------------------------------------------------------------------------
+Offset|  field              | Size  |    Value   |   Description
+------|---------------------|-------|------------|------------------------------
+0     |  bFunctionLength    | 1     |   number   |  Size of this descriptor.
+1     |  bDescriptorType    | 1     |   Constant |  CS_INTERFACE (0x24)
+2     |  bDescriptorSubtype | 1     |   Constant |  Union functional
+      |                     |       |            |  descriptor subtype.
+3     |  bMasterInterface   | 1     |   Constant | The interface number of the
+      |                     |       |            | Communication or Data Class interface
+4     | bSlaveInterface0    | 1     | Number     | nterface number of first slave or associated
+      |                     |       |            | interface in the union.
+------|---------------------|-------|------------|------------------------------
+  */
+typedef struct _UnionFunctionalDescriptor
+{
+  uint8_t    bLength;            /*Size of this functional descriptor, in bytes*/
+  uint8_t    bDescriptorType;    /*CS_INTERFACE (0x24)*/
+  uint8_t    bDescriptorSubType; /* Union functional descriptor SubType*/
+  uint8_t    bMasterInterface;   /* The interface number of the Communication or
+                                 Data Class interface,*/
+  uint8_t    bSlaveInterface0;   /*Interface number of first slave*/
+}
+CDC_UnionFuncDesc_TypeDef;
+
+typedef struct _USBH_CDCInterfaceDesc
+{
+  CDC_HeaderFuncDesc_TypeDef           CDC_HeaderFuncDesc;
+  CDC_CallMgmtFuncDesc_TypeDef         CDC_CallMgmtFuncDesc;
+  CDC_AbstCntrlMgmtFuncDesc_TypeDef    CDC_AbstCntrlMgmtFuncDesc;
+  CDC_UnionFuncDesc_TypeDef            CDC_UnionFuncDesc;
+}
+CDC_InterfaceDesc_Typedef;
+
+
+/* Structure for CDC process */
+typedef struct
+{
+  uint8_t              NotifPipe;
+  uint8_t              NotifEp;
+  uint8_t              buff[8];
+  uint16_t             NotifEpSize;
+}
+CDC_CommItfTypedef ;
+
+typedef struct
+{
+  uint8_t              InPipe;
+  uint8_t              OutPipe;
+  uint8_t              OutEp;
+  uint8_t              InEp;
+  uint8_t              buff[8];
+  uint16_t             OutEpSize;
+  uint16_t             InEpSize;
+}
+CDC_DataItfTypedef ;
+
+/* Structure for CDC process */
+typedef struct _CDC_Process
+{
+  CDC_CommItfTypedef                CommItf;
+  CDC_DataItfTypedef                DataItf;
+  uint8_t                           *pTxData;
+  uint8_t                           *pRxData;
+  uint32_t                           TxDataLength;
+  uint32_t                           RxDataLength;
+  CDC_InterfaceDesc_Typedef         CDC_Desc;
+  CDC_LineCodingTypeDef             LineCoding;
+  CDC_LineCodingTypeDef             *pUserLineCoding;
+  CDC_StateTypeDef                  state;
+  CDC_DataStateTypeDef              data_tx_state;
+  CDC_DataStateTypeDef              data_rx_state;
+  uint8_t                           Rx_Poll;
+}
+CDC_HandleTypeDef;
+
+/**
+  * @}
+  */
+
+/** @defgroup USBH_CDC_CORE_Exported_Defines
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup USBH_CDC_CORE_Exported_Macros
+  * @{
+  */
+/**
+  * @}
+  */
+
+/** @defgroup USBH_CDC_CORE_Exported_Variables
+  * @{
+  */
+extern USBH_ClassTypeDef  CDC_Class;
+#define USBH_CDC_CLASS    &CDC_Class
+
+/**
+  * @}
+  */
+
+/** @defgroup USBH_CDC_CORE_Exported_FunctionsPrototype
+  * @{
+  */
+
+USBH_StatusTypeDef  USBH_CDC_SetLineCoding(USBH_HandleTypeDef *phost,
+                                           CDC_LineCodingTypeDef *linecoding);
+
+USBH_StatusTypeDef  USBH_CDC_GetLineCoding(USBH_HandleTypeDef *phost,
+                                           CDC_LineCodingTypeDef *linecoding);
+
+USBH_StatusTypeDef  USBH_CDC_Transmit(USBH_HandleTypeDef *phost,
+                                      uint8_t *pbuff,
+                                      uint32_t length);
+
+USBH_StatusTypeDef  USBH_CDC_Receive(USBH_HandleTypeDef *phost,
+                                     uint8_t *pbuff,
+                                     uint32_t length);
+
+
+uint16_t            USBH_CDC_GetLastReceivedDataSize(USBH_HandleTypeDef *phost);
+
+USBH_StatusTypeDef  USBH_CDC_Stop(USBH_HandleTypeDef *phost);
+
+void USBH_CDC_LineCodingChanged(USBH_HandleTypeDef *phost);
+
+void USBH_CDC_TransmitCallback(USBH_HandleTypeDef *phost);
+
+void USBH_CDC_ReceiveCallback(USBH_HandleTypeDef *phost);
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __USBH_CDC_H */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/Middlewares/ST/STM32_USB_Host_Library/Class/CDC/Src/usbh_cdc.c b/Middlewares/ST/STM32_USB_Host_Library/Class/CDC/Src/usbh_cdc.c
new file mode 100644
index 0000000..3ad2b2e
--- /dev/null
+++ b/Middlewares/ST/STM32_USB_Host_Library/Class/CDC/Src/usbh_cdc.c
@@ -0,0 +1,837 @@
+/**
+  ******************************************************************************
+  * @file    usbh_cdc.c
+  * @author  MCD Application Team
+  * @brief   This file is the CDC Layer Handlers for USB Host CDC class.
+  *
+  *  @verbatim
+  *
+  *          ===================================================================
+  *                                CDC Class Driver Description
+  *          ===================================================================
+  *           This driver manages the "Universal Serial Bus Class Definitions for Communications Devices
+  *           Revision 1.2 November 16, 2007" and the sub-protocol specification of "Universal Serial Bus
+  *           Communications Class Subclass Specification for PSTN Devices Revision 1.2 February 9, 2007"
+  *           This driver implements the following aspects of the specification:
+  *             - Device descriptor management
+  *             - Configuration descriptor management
+  *             - Enumeration as CDC device with 2 data endpoints (IN and OUT) and 1 command endpoint (IN)
+  *             - Requests management (as described in section 6.2 in specification)
+  *             - Abstract Control Model compliant
+  *             - Union Functional collection (using 1 IN endpoint for control)
+  *             - Data interface class
+  *
+  *  @endverbatim
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2015 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                      www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+
+/* BSPDependencies
+- "stm32xxxxx_{eval}{discovery}{nucleo_144}.c"
+- "stm32xxxxx_{eval}{discovery}_io.c"
+- "stm32xxxxx_{eval}{discovery}{adafruit}_sd.c"
+- "stm32xxxxx_{eval}{discovery}{adafruit}_lcd.c"
+- "stm32xxxxx_{eval}{discovery}_sdram.c"
+EndBSPDependencies */
+
+/* Includes ------------------------------------------------------------------*/
+#include "usbh_cdc.h"
+
+/** @addtogroup USBH_LIB
+  * @{
+  */
+
+/** @addtogroup USBH_CLASS
+  * @{
+  */
+
+/** @addtogroup USBH_CDC_CLASS
+  * @{
+  */
+
+/** @defgroup USBH_CDC_CORE
+  * @brief    This file includes CDC Layer Handlers for USB Host CDC class.
+  * @{
+  */
+
+/** @defgroup USBH_CDC_CORE_Private_TypesDefinitions
+  * @{
+  */
+/**
+  * @}
+  */
+
+
+/** @defgroup USBH_CDC_CORE_Private_Defines
+  * @{
+  */
+#define USBH_CDC_BUFFER_SIZE                 1024
+/**
+  * @}
+  */
+
+
+/** @defgroup USBH_CDC_CORE_Private_Macros
+  * @{
+  */
+/**
+  * @}
+  */
+
+
+/** @defgroup USBH_CDC_CORE_Private_Variables
+  * @{
+  */
+/**
+  * @}
+  */
+
+
+/** @defgroup USBH_CDC_CORE_Private_FunctionPrototypes
+  * @{
+  */
+
+static USBH_StatusTypeDef USBH_CDC_InterfaceInit(USBH_HandleTypeDef *phost);
+
+static USBH_StatusTypeDef USBH_CDC_InterfaceDeInit(USBH_HandleTypeDef *phost);
+
+static USBH_StatusTypeDef USBH_CDC_Process(USBH_HandleTypeDef *phost);
+
+static USBH_StatusTypeDef USBH_CDC_SOFProcess(USBH_HandleTypeDef *phost);
+
+static USBH_StatusTypeDef USBH_CDC_ClassRequest(USBH_HandleTypeDef *phost);
+
+static USBH_StatusTypeDef GetLineCoding(USBH_HandleTypeDef *phost,
+                                        CDC_LineCodingTypeDef *linecoding);
+
+static USBH_StatusTypeDef SetLineCoding(USBH_HandleTypeDef *phost,
+                                        CDC_LineCodingTypeDef *linecoding);
+
+static void CDC_ProcessTransmission(USBH_HandleTypeDef *phost);
+
+static void CDC_ProcessReception(USBH_HandleTypeDef *phost);
+
+USBH_ClassTypeDef  CDC_Class =
+{
+  "CDC",
+  USB_CDC_CLASS,
+  USBH_CDC_InterfaceInit,
+  USBH_CDC_InterfaceDeInit,
+  USBH_CDC_ClassRequest,
+  USBH_CDC_Process,
+  USBH_CDC_SOFProcess,
+  NULL,
+};
+/**
+  * @}
+  */
+
+
+/** @defgroup USBH_CDC_CORE_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  USBH_CDC_InterfaceInit
+  *         The function init the CDC class.
+  * @param  phost: Host handle
+  * @retval USBH Status
+  */
+static USBH_StatusTypeDef USBH_CDC_InterfaceInit(USBH_HandleTypeDef *phost)
+{
+
+  USBH_StatusTypeDef status;
+  uint8_t interface;
+  CDC_HandleTypeDef *CDC_Handle;
+
+  interface = USBH_FindInterface(phost, COMMUNICATION_INTERFACE_CLASS_CODE,
+                                   ABSTRACT_CONTROL_MODEL, COMMON_AT_COMMAND);
+
+  if ((interface == 0xFFU) || (interface >= USBH_MAX_NUM_INTERFACES)) /* No Valid Interface */
+  {
+    USBH_DbgLog("Cannot Find the interface for Communication Interface Class.", phost->pActiveClass->Name);
+    return USBH_FAIL;
+  }
+
+  status = USBH_SelectInterface(phost, interface);
+
+  if (status != USBH_OK)
+  {
+    return USBH_FAIL;
+  }
+
+  phost->pActiveClass->pData = (CDC_HandleTypeDef *)USBH_malloc(sizeof(CDC_HandleTypeDef));
+  CDC_Handle = (CDC_HandleTypeDef *) phost->pActiveClass->pData;
+
+  if (CDC_Handle == NULL)
+  {
+    USBH_DbgLog("Cannot allocate memory for CDC Handle");
+    return USBH_FAIL;
+  }
+
+  /* Initialize cdc handler */
+  (void)USBH_memset(CDC_Handle, 0, sizeof(CDC_HandleTypeDef));
+
+  /*Collect the notification endpoint address and length*/
+  if ((phost->device.CfgDesc.Itf_Desc[interface].Ep_Desc[0].bEndpointAddress & 0x80U) != 0U)
+  {
+    CDC_Handle->CommItf.NotifEp = phost->device.CfgDesc.Itf_Desc[interface].Ep_Desc[0].bEndpointAddress;
+    CDC_Handle->CommItf.NotifEpSize  = phost->device.CfgDesc.Itf_Desc[interface].Ep_Desc[0].wMaxPacketSize;
+  }
+
+  /*Allocate the length for host channel number in*/
+  CDC_Handle->CommItf.NotifPipe = USBH_AllocPipe(phost, CDC_Handle->CommItf.NotifEp);
+
+  /* Open pipe for Notification endpoint */
+  (void)USBH_OpenPipe(phost, CDC_Handle->CommItf.NotifPipe, CDC_Handle->CommItf.NotifEp,
+                      phost->device.address, phost->device.speed, USB_EP_TYPE_INTR,
+                      CDC_Handle->CommItf.NotifEpSize);
+
+  (void)USBH_LL_SetToggle(phost, CDC_Handle->CommItf.NotifPipe, 0U);
+
+  interface = USBH_FindInterface(phost, DATA_INTERFACE_CLASS_CODE,
+                                   RESERVED, NO_CLASS_SPECIFIC_PROTOCOL_CODE);
+
+  if ((interface == 0xFFU) || (interface >= USBH_MAX_NUM_INTERFACES)) /* No Valid Interface */
+  {
+    USBH_DbgLog("Cannot Find the interface for Data Interface Class.", phost->pActiveClass->Name);
+    return USBH_FAIL;
+  }
+
+  /*Collect the class specific endpoint address and length*/
+  if ((phost->device.CfgDesc.Itf_Desc[interface].Ep_Desc[0].bEndpointAddress & 0x80U) != 0U)
+  {
+    CDC_Handle->DataItf.InEp = phost->device.CfgDesc.Itf_Desc[interface].Ep_Desc[0].bEndpointAddress;
+    CDC_Handle->DataItf.InEpSize  = phost->device.CfgDesc.Itf_Desc[interface].Ep_Desc[0].wMaxPacketSize;
+  }
+  else
+  {
+    CDC_Handle->DataItf.OutEp = phost->device.CfgDesc.Itf_Desc[interface].Ep_Desc[0].bEndpointAddress;
+    CDC_Handle->DataItf.OutEpSize  = phost->device.CfgDesc.Itf_Desc[interface].Ep_Desc[0].wMaxPacketSize;
+  }
+
+  if ((phost->device.CfgDesc.Itf_Desc[interface].Ep_Desc[1].bEndpointAddress & 0x80U) != 0U)
+  {
+    CDC_Handle->DataItf.InEp = phost->device.CfgDesc.Itf_Desc[interface].Ep_Desc[1].bEndpointAddress;
+    CDC_Handle->DataItf.InEpSize  = phost->device.CfgDesc.Itf_Desc[interface].Ep_Desc[1].wMaxPacketSize;
+  }
+  else
+  {
+    CDC_Handle->DataItf.OutEp = phost->device.CfgDesc.Itf_Desc[interface].Ep_Desc[1].bEndpointAddress;
+    CDC_Handle->DataItf.OutEpSize = phost->device.CfgDesc.Itf_Desc[interface].Ep_Desc[1].wMaxPacketSize;
+  }
+
+  /*Allocate the length for host channel number out*/
+  CDC_Handle->DataItf.OutPipe = USBH_AllocPipe(phost, CDC_Handle->DataItf.OutEp);
+
+  /*Allocate the length for host channel number in*/
+  CDC_Handle->DataItf.InPipe = USBH_AllocPipe(phost, CDC_Handle->DataItf.InEp);
+
+  /* Open channel for OUT endpoint */
+  (void)USBH_OpenPipe(phost, CDC_Handle->DataItf.OutPipe, CDC_Handle->DataItf.OutEp,
+                      phost->device.address, phost->device.speed, USB_EP_TYPE_BULK,
+                      CDC_Handle->DataItf.OutEpSize);
+
+  /* Open channel for IN endpoint */
+  (void)USBH_OpenPipe(phost, CDC_Handle->DataItf.InPipe, CDC_Handle->DataItf.InEp,
+                      phost->device.address, phost->device.speed, USB_EP_TYPE_BULK,
+                      CDC_Handle->DataItf.InEpSize);
+
+  CDC_Handle->state = CDC_IDLE_STATE;
+
+  (void)USBH_LL_SetToggle(phost, CDC_Handle->DataItf.OutPipe, 0U);
+  (void)USBH_LL_SetToggle(phost, CDC_Handle->DataItf.InPipe, 0U);
+
+  return USBH_OK;
+}
+
+
+
+/**
+  * @brief  USBH_CDC_InterfaceDeInit
+  *         The function DeInit the Pipes used for the CDC class.
+  * @param  phost: Host handle
+  * @retval USBH Status
+  */
+static USBH_StatusTypeDef USBH_CDC_InterfaceDeInit(USBH_HandleTypeDef *phost)
+{
+  CDC_HandleTypeDef *CDC_Handle = (CDC_HandleTypeDef *) phost->pActiveClass->pData;
+
+  if ((CDC_Handle->CommItf.NotifPipe) != 0U)
+  {
+    (void)USBH_ClosePipe(phost, CDC_Handle->CommItf.NotifPipe);
+    (void)USBH_FreePipe(phost, CDC_Handle->CommItf.NotifPipe);
+    CDC_Handle->CommItf.NotifPipe = 0U;     /* Reset the Channel as Free */
+  }
+
+  if ((CDC_Handle->DataItf.InPipe) != 0U)
+  {
+    (void)USBH_ClosePipe(phost, CDC_Handle->DataItf.InPipe);
+    (void)USBH_FreePipe(phost, CDC_Handle->DataItf.InPipe);
+    CDC_Handle->DataItf.InPipe = 0U;     /* Reset the Channel as Free */
+  }
+
+  if ((CDC_Handle->DataItf.OutPipe) != 0U)
+  {
+    (void)USBH_ClosePipe(phost, CDC_Handle->DataItf.OutPipe);
+    (void)USBH_FreePipe(phost, CDC_Handle->DataItf.OutPipe);
+    CDC_Handle->DataItf.OutPipe = 0U;    /* Reset the Channel as Free */
+  }
+
+  if ((phost->pActiveClass->pData) != NULL)
+  {
+    USBH_free(phost->pActiveClass->pData);
+    phost->pActiveClass->pData = 0U;
+  }
+
+  return USBH_OK;
+}
+
+/**
+  * @brief  USBH_CDC_ClassRequest
+  *         The function is responsible for handling Standard requests
+  *         for CDC class.
+  * @param  phost: Host handle
+  * @retval USBH Status
+  */
+static USBH_StatusTypeDef USBH_CDC_ClassRequest(USBH_HandleTypeDef *phost)
+{
+  USBH_StatusTypeDef status;
+  CDC_HandleTypeDef *CDC_Handle = (CDC_HandleTypeDef *) phost->pActiveClass->pData;
+
+  /* Issue the get line coding request */
+  status = GetLineCoding(phost, &CDC_Handle->LineCoding);
+  if (status == USBH_OK)
+  {
+    phost->pUser(phost, HOST_USER_CLASS_ACTIVE);
+  }
+  else if (status == USBH_NOT_SUPPORTED)
+  {
+    USBH_ErrLog("Control error: CDC: Device Get Line Coding configuration failed");
+  }
+  else
+  {
+    /* .. */
+  }
+
+  return status;
+}
+
+
+/**
+  * @brief  USBH_CDC_Process
+  *         The function is for managing state machine for CDC data transfers
+  * @param  phost: Host handle
+  * @retval USBH Status
+  */
+static USBH_StatusTypeDef USBH_CDC_Process(USBH_HandleTypeDef *phost)
+{
+  USBH_StatusTypeDef status = USBH_BUSY;
+  USBH_StatusTypeDef req_status = USBH_OK;
+  CDC_HandleTypeDef *CDC_Handle = (CDC_HandleTypeDef *) phost->pActiveClass->pData;
+
+  switch (CDC_Handle->state)
+  {
+
+    case CDC_IDLE_STATE:
+      status = USBH_OK;
+      break;
+
+    case CDC_SET_LINE_CODING_STATE:
+      req_status = SetLineCoding(phost, CDC_Handle->pUserLineCoding);
+
+      if (req_status == USBH_OK)
+      {
+        CDC_Handle->state = CDC_GET_LAST_LINE_CODING_STATE;
+      }
+
+      else
+      {
+        if (req_status != USBH_BUSY)
+        {
+          CDC_Handle->state = CDC_ERROR_STATE;
+        }
+      }
+      break;
+
+
+    case CDC_GET_LAST_LINE_CODING_STATE:
+      req_status = GetLineCoding(phost, &(CDC_Handle->LineCoding));
+
+      if (req_status == USBH_OK)
+      {
+        CDC_Handle->state = CDC_IDLE_STATE;
+
+        if ((CDC_Handle->LineCoding.b.bCharFormat == CDC_Handle->pUserLineCoding->b.bCharFormat) &&
+            (CDC_Handle->LineCoding.b.bDataBits == CDC_Handle->pUserLineCoding->b.bDataBits) &&
+            (CDC_Handle->LineCoding.b.bParityType == CDC_Handle->pUserLineCoding->b.bParityType) &&
+            (CDC_Handle->LineCoding.b.dwDTERate == CDC_Handle->pUserLineCoding->b.dwDTERate))
+        {
+          USBH_CDC_LineCodingChanged(phost);
+        }
+      }
+      else
+      {
+        if (req_status != USBH_BUSY)
+        {
+          CDC_Handle->state = CDC_ERROR_STATE;
+        }
+      }
+      break;
+
+    case CDC_TRANSFER_DATA:
+      CDC_ProcessTransmission(phost);
+      CDC_ProcessReception(phost);
+      break;
+
+    case CDC_ERROR_STATE:
+      req_status = USBH_ClrFeature(phost, 0x00U);
+
+      if (req_status == USBH_OK)
+      {
+        /*Change the state to waiting*/
+        CDC_Handle->state = CDC_IDLE_STATE;
+      }
+      break;
+
+    default:
+      break;
+
+  }
+
+  return status;
+}
+
+/**
+  * @brief  USBH_CDC_SOFProcess
+  *         The function is for managing SOF callback
+  * @param  phost: Host handle
+  * @retval USBH Status
+  */
+static USBH_StatusTypeDef USBH_CDC_SOFProcess(USBH_HandleTypeDef *phost)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(phost);
+
+  return USBH_OK;
+}
+
+
+/**
+  * @brief  USBH_CDC_Stop
+  *         Stop current CDC Transmission
+  * @param  phost: Host handle
+  * @retval USBH Status
+  */
+USBH_StatusTypeDef  USBH_CDC_Stop(USBH_HandleTypeDef *phost)
+{
+  CDC_HandleTypeDef *CDC_Handle = (CDC_HandleTypeDef *) phost->pActiveClass->pData;
+
+  if (phost->gState == HOST_CLASS)
+  {
+    CDC_Handle->state = CDC_IDLE_STATE;
+
+    (void)USBH_ClosePipe(phost, CDC_Handle->CommItf.NotifPipe);
+    (void)USBH_ClosePipe(phost, CDC_Handle->DataItf.InPipe);
+    (void)USBH_ClosePipe(phost, CDC_Handle->DataItf.OutPipe);
+  }
+  return USBH_OK;
+}
+/**
+  * @brief  This request allows the host to find out the currently
+  *         configured line coding.
+  * @param  pdev: Selected device
+  * @retval USBH_StatusTypeDef : USB ctl xfer status
+  */
+static USBH_StatusTypeDef GetLineCoding(USBH_HandleTypeDef *phost, CDC_LineCodingTypeDef *linecoding)
+{
+
+  phost->Control.setup.b.bmRequestType = USB_D2H | USB_REQ_TYPE_CLASS | \
+                                         USB_REQ_RECIPIENT_INTERFACE;
+
+  phost->Control.setup.b.bRequest = CDC_GET_LINE_CODING;
+  phost->Control.setup.b.wValue.w = 0U;
+  phost->Control.setup.b.wIndex.w = 0U;
+  phost->Control.setup.b.wLength.w = LINE_CODING_STRUCTURE_SIZE;
+
+  return USBH_CtlReq(phost, linecoding->Array, LINE_CODING_STRUCTURE_SIZE);
+}
+
+
+/**
+  * @brief  This request allows the host to specify typical asynchronous
+  * line-character formatting properties
+  * This request applies to asynchronous byte stream data class interfaces
+  * and endpoints
+  * @param  pdev: Selected device
+  * @retval USBH_StatusTypeDef : USB ctl xfer status
+  */
+static USBH_StatusTypeDef SetLineCoding(USBH_HandleTypeDef *phost,
+                                        CDC_LineCodingTypeDef *linecoding)
+{
+  phost->Control.setup.b.bmRequestType = USB_H2D | USB_REQ_TYPE_CLASS |
+                                         USB_REQ_RECIPIENT_INTERFACE;
+
+  phost->Control.setup.b.bRequest = CDC_SET_LINE_CODING;
+  phost->Control.setup.b.wValue.w = 0U;
+
+  phost->Control.setup.b.wIndex.w = 0U;
+
+  phost->Control.setup.b.wLength.w = LINE_CODING_STRUCTURE_SIZE;
+
+  return USBH_CtlReq(phost, linecoding->Array, LINE_CODING_STRUCTURE_SIZE);
+}
+
+/**
+  * @brief  This function prepares the state before issuing the class specific commands
+  * @param  None
+  * @retval None
+  */
+USBH_StatusTypeDef USBH_CDC_SetLineCoding(USBH_HandleTypeDef *phost,
+                                          CDC_LineCodingTypeDef *linecoding)
+{
+  CDC_HandleTypeDef *CDC_Handle = (CDC_HandleTypeDef *) phost->pActiveClass->pData;
+
+  if (phost->gState == HOST_CLASS)
+  {
+    CDC_Handle->state = CDC_SET_LINE_CODING_STATE;
+    CDC_Handle->pUserLineCoding = linecoding;
+
+#if (USBH_USE_OS == 1U)
+    phost->os_msg = (uint32_t)USBH_CLASS_EVENT;
+#if (osCMSIS < 0x20000U)
+    (void)osMessagePut(phost->os_event, phost->os_msg, 0U);
+#else
+    (void)osMessageQueuePut(phost->os_event, &phost->os_msg, 0U, 0U);
+#endif
+#endif
+  }
+
+  return USBH_OK;
+}
+
+/**
+  * @brief  This function prepares the state before issuing the class specific commands
+  * @param  None
+  * @retval None
+  */
+USBH_StatusTypeDef  USBH_CDC_GetLineCoding(USBH_HandleTypeDef *phost,
+                                           CDC_LineCodingTypeDef *linecoding)
+{
+  CDC_HandleTypeDef *CDC_Handle = (CDC_HandleTypeDef *) phost->pActiveClass->pData;
+
+  if ((phost->gState == HOST_CLASS) || (phost->gState == HOST_CLASS_REQUEST))
+  {
+    *linecoding = CDC_Handle->LineCoding;
+    return USBH_OK;
+  }
+  else
+  {
+    return USBH_FAIL;
+  }
+}
+
+/**
+  * @brief  This function return last received data size
+  * @param  None
+  * @retval None
+  */
+uint16_t USBH_CDC_GetLastReceivedDataSize(USBH_HandleTypeDef *phost)
+{
+  uint32_t dataSize;
+  CDC_HandleTypeDef *CDC_Handle = (CDC_HandleTypeDef *) phost->pActiveClass->pData;
+
+  if (phost->gState == HOST_CLASS)
+  {
+    dataSize = USBH_LL_GetLastXferSize(phost, CDC_Handle->DataItf.InPipe);
+  }
+  else
+  {
+    dataSize =  0U;
+  }
+
+  return (uint16_t)dataSize;
+}
+
+/**
+  * @brief  This function prepares the state before issuing the class specific commands
+  * @param  None
+  * @retval None
+  */
+USBH_StatusTypeDef  USBH_CDC_Transmit(USBH_HandleTypeDef *phost, uint8_t *pbuff, uint32_t length)
+{
+  USBH_StatusTypeDef Status = USBH_BUSY;
+  CDC_HandleTypeDef *CDC_Handle = (CDC_HandleTypeDef *) phost->pActiveClass->pData;
+
+  if ((CDC_Handle->state == CDC_IDLE_STATE) || (CDC_Handle->state == CDC_TRANSFER_DATA))
+  {
+    CDC_Handle->pTxData = pbuff;
+    CDC_Handle->TxDataLength = length;
+    CDC_Handle->state = CDC_TRANSFER_DATA;
+    CDC_Handle->data_tx_state = CDC_SEND_DATA;
+    Status = USBH_OK;
+
+#if (USBH_USE_OS == 1U)
+    phost->os_msg = (uint32_t)USBH_CLASS_EVENT;
+#if (osCMSIS < 0x20000U)
+    (void)osMessagePut(phost->os_event, phost->os_msg, 0U);
+#else
+    (void)osMessageQueuePut(phost->os_event, &phost->os_msg, 0U, 0U);
+#endif
+#endif
+  }
+  return Status;
+}
+
+
+/**
+  * @brief  This function prepares the state before issuing the class specific commands
+  * @param  None
+  * @retval None
+  */
+USBH_StatusTypeDef  USBH_CDC_Receive(USBH_HandleTypeDef *phost, uint8_t *pbuff, uint32_t length)
+{
+  USBH_StatusTypeDef Status = USBH_BUSY;
+  CDC_HandleTypeDef *CDC_Handle = (CDC_HandleTypeDef *) phost->pActiveClass->pData;
+
+  if ((CDC_Handle->state == CDC_IDLE_STATE) || (CDC_Handle->state == CDC_TRANSFER_DATA))
+  {
+    CDC_Handle->pRxData = pbuff;
+    CDC_Handle->RxDataLength = length;
+    CDC_Handle->state = CDC_TRANSFER_DATA;
+    CDC_Handle->data_rx_state = CDC_RECEIVE_DATA;
+    Status = USBH_OK;
+
+#if (USBH_USE_OS == 1U)
+    phost->os_msg = (uint32_t)USBH_CLASS_EVENT;
+#if (osCMSIS < 0x20000U)
+    (void)osMessagePut(phost->os_event, phost->os_msg, 0U);
+#else
+    (void)osMessageQueuePut(phost->os_event, &phost->os_msg, 0U, 0U);
+#endif
+#endif
+  }
+  return Status;
+}
+
+/**
+  * @brief  The function is responsible for sending data to the device
+  *  @param  pdev: Selected device
+  * @retval None
+  */
+static void CDC_ProcessTransmission(USBH_HandleTypeDef *phost)
+{
+  CDC_HandleTypeDef *CDC_Handle = (CDC_HandleTypeDef *) phost->pActiveClass->pData;
+  USBH_URBStateTypeDef URB_Status = USBH_URB_IDLE;
+
+  switch (CDC_Handle->data_tx_state)
+  {
+    case CDC_SEND_DATA:
+      if (CDC_Handle->TxDataLength > CDC_Handle->DataItf.OutEpSize)
+      {
+        (void)USBH_BulkSendData(phost,
+                                CDC_Handle->pTxData,
+                                CDC_Handle->DataItf.OutEpSize,
+                                CDC_Handle->DataItf.OutPipe,
+                                1U);
+      }
+      else
+      {
+        (void)USBH_BulkSendData(phost,
+                                CDC_Handle->pTxData,
+                                (uint16_t)CDC_Handle->TxDataLength,
+                                CDC_Handle->DataItf.OutPipe,
+                                1U);
+      }
+
+      CDC_Handle->data_tx_state = CDC_SEND_DATA_WAIT;
+      break;
+
+    case CDC_SEND_DATA_WAIT:
+
+      URB_Status = USBH_LL_GetURBState(phost, CDC_Handle->DataItf.OutPipe);
+
+      /* Check the status done for transmission */
+      if (URB_Status == USBH_URB_DONE)
+      {
+        if (CDC_Handle->TxDataLength > CDC_Handle->DataItf.OutEpSize)
+        {
+          CDC_Handle->TxDataLength -= CDC_Handle->DataItf.OutEpSize;
+          CDC_Handle->pTxData += CDC_Handle->DataItf.OutEpSize;
+        }
+        else
+        {
+          CDC_Handle->TxDataLength = 0U;
+        }
+
+        if (CDC_Handle->TxDataLength > 0U)
+        {
+          CDC_Handle->data_tx_state = CDC_SEND_DATA;
+        }
+        else
+        {
+          CDC_Handle->data_tx_state = CDC_IDLE;
+          USBH_CDC_TransmitCallback(phost);
+        }
+
+#if (USBH_USE_OS == 1U)
+        phost->os_msg = (uint32_t)USBH_CLASS_EVENT;
+#if (osCMSIS < 0x20000U)
+        (void)osMessagePut(phost->os_event, phost->os_msg, 0U);
+#else
+        (void)osMessageQueuePut(phost->os_event, &phost->os_msg, 0U, 0U);
+#endif
+#endif
+      }
+      else
+      {
+        if (URB_Status == USBH_URB_NOTREADY)
+        {
+          CDC_Handle->data_tx_state = CDC_SEND_DATA;
+
+#if (USBH_USE_OS == 1U)
+          phost->os_msg = (uint32_t)USBH_CLASS_EVENT;
+#if (osCMSIS < 0x20000U)
+          (void)osMessagePut(phost->os_event, phost->os_msg, 0U);
+#else
+          (void)osMessageQueuePut(phost->os_event, &phost->os_msg, 0U, 0U);
+#endif
+#endif
+        }
+      }
+      break;
+
+    default:
+      break;
+  }
+}
+/**
+  * @brief  This function responsible for reception of data from the device
+  *  @param  pdev: Selected device
+  * @retval None
+  */
+
+static void CDC_ProcessReception(USBH_HandleTypeDef *phost)
+{
+  CDC_HandleTypeDef *CDC_Handle = (CDC_HandleTypeDef *) phost->pActiveClass->pData;
+  USBH_URBStateTypeDef URB_Status = USBH_URB_IDLE;
+  uint32_t length;
+
+  switch (CDC_Handle->data_rx_state)
+  {
+
+    case CDC_RECEIVE_DATA:
+
+      (void)USBH_BulkReceiveData(phost,
+                                 CDC_Handle->pRxData,
+                                 CDC_Handle->DataItf.InEpSize,
+                                 CDC_Handle->DataItf.InPipe);
+
+      CDC_Handle->data_rx_state = CDC_RECEIVE_DATA_WAIT;
+
+      break;
+
+    case CDC_RECEIVE_DATA_WAIT:
+
+      URB_Status = USBH_LL_GetURBState(phost, CDC_Handle->DataItf.InPipe);
+
+      /*Check the status done for reception*/
+      if (URB_Status == USBH_URB_DONE)
+      {
+        length = USBH_LL_GetLastXferSize(phost, CDC_Handle->DataItf.InPipe);
+
+        if (((CDC_Handle->RxDataLength - length) > 0U) && (length > CDC_Handle->DataItf.InEpSize))
+        {
+          CDC_Handle->RxDataLength -= length ;
+          CDC_Handle->pRxData += length;
+          CDC_Handle->data_rx_state = CDC_RECEIVE_DATA;
+        }
+        else
+        {
+          CDC_Handle->data_rx_state = CDC_IDLE;
+          USBH_CDC_ReceiveCallback(phost);
+        }
+
+#if (USBH_USE_OS == 1U)
+        phost->os_msg = (uint32_t)USBH_CLASS_EVENT;
+#if (osCMSIS < 0x20000U)
+        (void)osMessagePut(phost->os_event, phost->os_msg, 0U);
+#else
+        (void)osMessageQueuePut(phost->os_event, &phost->os_msg, 0U, 0U);
+#endif
+#endif
+      }
+      break;
+
+    default:
+      break;
+  }
+}
+
+/**
+  * @brief  The function informs user that data have been received
+  *  @param  pdev: Selected device
+  * @retval None
+  */
+__weak void USBH_CDC_TransmitCallback(USBH_HandleTypeDef *phost)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(phost);
+}
+
+/**
+  * @brief  The function informs user that data have been sent
+  *  @param  pdev: Selected device
+  * @retval None
+  */
+__weak void USBH_CDC_ReceiveCallback(USBH_HandleTypeDef *phost)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(phost);
+}
+
+/**
+  * @brief  The function informs user that Settings have been changed
+  *  @param  pdev: Selected device
+  * @retval None
+  */
+__weak void USBH_CDC_LineCodingChanged(USBH_HandleTypeDef *phost)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(phost);
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+
+/**
+  * @}
+  */
+
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Middlewares/ST/STM32_USB_Host_Library/Core/Inc/usbh_core.h b/Middlewares/ST/STM32_USB_Host_Library/Core/Inc/usbh_core.h
new file mode 100644
index 0000000..b7497d8
--- /dev/null
+++ b/Middlewares/ST/STM32_USB_Host_Library/Core/Inc/usbh_core.h
@@ -0,0 +1,192 @@
+/**
+  ******************************************************************************
+  * @file    usbh_core.h
+  * @author  MCD Application Team
+  * @brief   Header file for usbh_core.c
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2015 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                      www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+/* Define to prevent recursive  ----------------------------------------------*/
+#ifndef __USBH_CORE_H
+#define __USBH_CORE_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "usbh_conf.h"
+#include "usbh_def.h"
+#include "usbh_ioreq.h"
+#include "usbh_pipes.h"
+#include "usbh_ctlreq.h"
+
+/** @addtogroup USBH_LIB
+  * @{
+  */
+
+/** @addtogroup USBH_LIB_CORE
+  * @{
+  */
+
+/** @defgroup USBH_CORE
+  * @brief This file is the Header file for usbh_core.c
+  * @{
+  */
+
+
+/** @defgroup USBH_CORE_Exported_Defines
+  * @{
+  */
+
+/**
+  * @}
+  */
+#define HOST_USER_SELECT_CONFIGURATION          0x01U
+#define HOST_USER_CLASS_ACTIVE                  0x02U
+#define HOST_USER_CLASS_SELECTED                0x03U
+#define HOST_USER_CONNECTION                    0x04U
+#define HOST_USER_DISCONNECTION                 0x05U
+#define HOST_USER_UNRECOVERED_ERROR             0x06U
+
+
+/**
+  * @}
+  */
+
+
+
+/** @defgroup USBH_CORE_Exported_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup USBH_CORE_Exported_Variables
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup USBH_CORE_Exported_FunctionsPrototype
+  * @{
+  */
+
+
+USBH_StatusTypeDef  USBH_Init(USBH_HandleTypeDef *phost, void (*pUsrFunc)(USBH_HandleTypeDef *phost, uint8_t id), uint8_t id);
+USBH_StatusTypeDef  USBH_DeInit(USBH_HandleTypeDef *phost);
+USBH_StatusTypeDef  USBH_RegisterClass(USBH_HandleTypeDef *phost, USBH_ClassTypeDef *pclass);
+USBH_StatusTypeDef  USBH_SelectInterface(USBH_HandleTypeDef *phost, uint8_t interface);
+uint8_t             USBH_FindInterface(USBH_HandleTypeDef *phost,
+                                       uint8_t Class,
+                                       uint8_t SubClass,
+                                       uint8_t Protocol);
+uint8_t             USBH_GetActiveClass(USBH_HandleTypeDef *phost);
+
+uint8_t             USBH_FindInterfaceIndex(USBH_HandleTypeDef *phost,
+                                            uint8_t interface_number,
+                                            uint8_t alt_settings);
+
+uint8_t              USBH_IsPortEnabled(USBH_HandleTypeDef *phost);
+
+USBH_StatusTypeDef  USBH_Start(USBH_HandleTypeDef *phost);
+USBH_StatusTypeDef  USBH_Stop(USBH_HandleTypeDef *phost);
+USBH_StatusTypeDef  USBH_Process(USBH_HandleTypeDef *phost);
+USBH_StatusTypeDef  USBH_ReEnumerate(USBH_HandleTypeDef *phost);
+
+/* USBH Low Level Driver */
+USBH_StatusTypeDef   USBH_LL_Init(USBH_HandleTypeDef *phost);
+USBH_StatusTypeDef   USBH_LL_DeInit(USBH_HandleTypeDef *phost);
+USBH_StatusTypeDef   USBH_LL_Start(USBH_HandleTypeDef *phost);
+USBH_StatusTypeDef   USBH_LL_Stop(USBH_HandleTypeDef *phost);
+
+USBH_StatusTypeDef   USBH_LL_Connect(USBH_HandleTypeDef *phost);
+USBH_StatusTypeDef   USBH_LL_Disconnect(USBH_HandleTypeDef *phost);
+USBH_SpeedTypeDef    USBH_LL_GetSpeed(USBH_HandleTypeDef *phost);
+USBH_StatusTypeDef   USBH_LL_ResetPort(USBH_HandleTypeDef *phost);
+uint32_t             USBH_LL_GetLastXferSize(USBH_HandleTypeDef *phost,
+                                             uint8_t pipe);
+
+USBH_StatusTypeDef   USBH_LL_DriverVBUS(USBH_HandleTypeDef *phost,
+                                        uint8_t state);
+
+USBH_StatusTypeDef   USBH_LL_OpenPipe(USBH_HandleTypeDef *phost,
+                                      uint8_t pipe,
+                                      uint8_t epnum,
+                                      uint8_t dev_address,
+                                      uint8_t speed,
+                                      uint8_t ep_type,
+                                      uint16_t mps);
+
+USBH_StatusTypeDef   USBH_LL_ClosePipe(USBH_HandleTypeDef *phost,
+                                       uint8_t pipe);
+
+USBH_StatusTypeDef   USBH_LL_SubmitURB(USBH_HandleTypeDef *phost,
+                                       uint8_t pipe,
+                                       uint8_t direction,
+                                       uint8_t ep_type,
+                                       uint8_t token,
+                                       uint8_t *pbuff,
+                                       uint16_t length,
+                                       uint8_t do_ping);
+
+USBH_URBStateTypeDef USBH_LL_GetURBState(USBH_HandleTypeDef *phost,
+                                         uint8_t pipe);
+
+#if (USBH_USE_OS == 1U)
+USBH_StatusTypeDef  USBH_LL_NotifyURBChange(USBH_HandleTypeDef *phost);
+#endif
+
+USBH_StatusTypeDef USBH_LL_SetToggle(USBH_HandleTypeDef *phost,
+                                     uint8_t pipe, uint8_t toggle);
+
+uint8_t USBH_LL_GetToggle(USBH_HandleTypeDef *phost, uint8_t pipe);
+
+void                 USBH_LL_PortDisabled(USBH_HandleTypeDef *phost);
+void                 USBH_LL_PortEnabled(USBH_HandleTypeDef *phost);
+
+/* USBH Time base */
+void USBH_LL_SetTimer(USBH_HandleTypeDef *phost, uint32_t time);
+void USBH_LL_IncTimer(USBH_HandleTypeDef *phost);
+
+void USBH_Delay(uint32_t Delay);
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __USBH_CORE_H */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
+
+
diff --git a/Middlewares/ST/STM32_USB_Host_Library/Core/Inc/usbh_ctlreq.h b/Middlewares/ST/STM32_USB_Host_Library/Core/Inc/usbh_ctlreq.h
new file mode 100644
index 0000000..2b4a96a
--- /dev/null
+++ b/Middlewares/ST/STM32_USB_Host_Library/Core/Inc/usbh_ctlreq.h
@@ -0,0 +1,141 @@
+/**
+  ******************************************************************************
+  * @file    usbh_ctlreq.h
+  * @author  MCD Application Team
+  * @brief   Header file for usbh_ctlreq.c
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2015 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                      www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive  ----------------------------------------------*/
+#ifndef __USBH_CTLREQ_H
+#define __USBH_CTLREQ_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "usbh_core.h"
+
+/** @addtogroup USBH_LIB
+  * @{
+  */
+
+/** @addtogroup USBH_LIB_CORE
+  * @{
+  */
+
+/** @defgroup USBH_CTLREQ
+  * @brief This file is the
+  * @{
+  */
+
+
+/** @defgroup USBH_CTLREQ_Exported_Defines
+  * @{
+  */
+/*Standard Feature Selector for clear feature command*/
+#define FEATURE_SELECTOR_ENDPOINT         0x00U
+#define FEATURE_SELECTOR_DEVICE           0x01U
+#define FEATURE_SELECTOR_REMOTEWAKEUP     0X01U
+
+
+#define INTERFACE_DESC_TYPE               0x04U
+#define ENDPOINT_DESC_TYPE                0x05U
+#define INTERFACE_DESC_SIZE               0x09U
+
+/**
+  * @}
+  */
+
+
+/** @defgroup USBH_CTLREQ_Exported_Types
+  * @{
+  */
+/**
+  * @}
+  */
+
+
+/** @defgroup USBH_CTLREQ_Exported_Macros
+  * @{
+  */
+/**
+  * @}
+  */
+
+/** @defgroup USBH_CTLREQ_Exported_Variables
+  * @{
+  */
+extern uint8_t USBH_CfgDesc[512];
+/**
+  * @}
+  */
+
+/** @defgroup USBH_CTLREQ_Exported_FunctionsPrototype
+  * @{
+  */
+USBH_StatusTypeDef USBH_CtlReq(USBH_HandleTypeDef *phost, uint8_t *buff,
+                               uint16_t length);
+
+USBH_StatusTypeDef USBH_GetDescriptor(USBH_HandleTypeDef *phost,
+                                      uint8_t  req_type, uint16_t value_idx,
+                                      uint8_t *buff, uint16_t length);
+
+USBH_StatusTypeDef USBH_Get_DevDesc(USBH_HandleTypeDef *phost, uint8_t length);
+
+USBH_StatusTypeDef USBH_Get_StringDesc(USBH_HandleTypeDef *phost,
+                                       uint8_t string_index, uint8_t *buff,
+                                       uint16_t length);
+
+USBH_StatusTypeDef USBH_SetCfg(USBH_HandleTypeDef *phost, uint16_t cfg_idx);
+
+USBH_StatusTypeDef USBH_Get_CfgDesc(USBH_HandleTypeDef *phost, uint16_t length);
+
+USBH_StatusTypeDef USBH_SetAddress(USBH_HandleTypeDef *phost,
+                                   uint8_t DeviceAddress);
+
+USBH_StatusTypeDef USBH_SetInterface(USBH_HandleTypeDef *phost, uint8_t ep_num,
+                                     uint8_t altSetting);
+
+USBH_StatusTypeDef USBH_SetFeature(USBH_HandleTypeDef *phost, uint8_t wValue);
+
+USBH_StatusTypeDef USBH_ClrFeature(USBH_HandleTypeDef *phost, uint8_t ep_num);
+
+USBH_DescHeader_t *USBH_GetNextDesc(uint8_t *pbuf, uint16_t *ptr);
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __USBH_CTLREQ_H */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
+
diff --git a/Middlewares/ST/STM32_USB_Host_Library/Core/Inc/usbh_def.h b/Middlewares/ST/STM32_USB_Host_Library/Core/Inc/usbh_def.h
new file mode 100644
index 0000000..e2686a9
--- /dev/null
+++ b/Middlewares/ST/STM32_USB_Host_Library/Core/Inc/usbh_def.h
@@ -0,0 +1,512 @@
+/**
+  ******************************************************************************
+  * @file    usbh_def.h
+  * @author  MCD Application Team
+  * @brief   Definitions used in the USB host library
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2015 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                      www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive  ----------------------------------------------*/
+#ifndef  USBH_DEF_H
+#define  USBH_DEF_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "usbh_conf.h"
+
+/** @addtogroup USBH_LIB
+  * @{
+  */
+
+/** @addtogroup USBH_LIB_CORE
+  * @{
+  */
+
+/** @defgroup USBH_DEF
+  * @brief This file is includes USB descriptors
+  * @{
+  */
+
+#ifndef NULL
+#define NULL  0U
+#endif
+
+#ifndef FALSE
+#define FALSE 0U
+#endif
+
+#ifndef TRUE
+#define TRUE  1U
+#endif
+
+#ifndef USBH_DEV_RESET_TIMEOUT
+#define USBH_DEV_RESET_TIMEOUT                        1000U
+#endif
+
+#define ValBit(VAR,POS)                               (VAR & (1 << POS))
+#define SetBit(VAR,POS)                               (VAR |= (1 << POS))
+#define ClrBit(VAR,POS)                               (VAR &= ((1 << POS)^255))
+
+#ifndef MIN
+#define MIN(a, b)  (((a) < (b)) ? (a) : (b))
+#endif
+
+#ifndef MAX
+#define MAX(a, b)  (((a) > (b)) ? (a) : (b))
+#endif
+
+#define LE16(addr)        (((uint16_t)(addr)[0]) | \
+                           ((uint16_t)(((uint32_t)(addr)[1]) << 8)))
+
+#define LE24(addr)        (((uint32_t)(addr)[0]) | \
+                           (((uint32_t)(addr)[1]) << 8) | \
+                           (((uint32_t)(addr)[2]) << 16))
+
+#define LE32(addr)        (((uint32_t)(addr)[0]) | \
+                           (((uint32_t)(addr)[1]) << 8) | \
+                           (((uint32_t)(addr)[2]) << 16) | \
+                           (((uint32_t)(addr)[3]) << 24))
+
+#define LE64(addr)        (((uint64_t)(addr)[0]) | \
+                           (((uint64_t)(addr)[1]) << 8) | \
+                           (((uint64_t)(addr)[2]) << 16) | \
+                           (((uint64_t)(addr)[3]) << 24) | \
+                           (((uint64_t)(addr)[4]) << 32) | \
+                           (((uint64_t)(addr)[5]) << 40) | \
+                           (((uint64_t)(addr)[6]) << 48) | \
+                           (((uint64_t)(addr)[7]) << 56))
+
+#define LE16S(addr)       ((int16_t)(LE16((addr))))
+#define LE24S(addr)       ((int32_t)(LE24((addr))))
+#define LE32S(addr)       ((int32_t)(LE32((addr))))
+#define LE64S(addr)       ((int64_t)(LE64((addr))))
+
+#ifndef USBH_MAX_DATA_BUFFER
+#define USBH_MAX_DATA_BUFFER                               0x400U
+#endif
+
+#define USBH_MAX_EP_PACKET_SIZE                            0x400U
+
+#define  USB_LEN_DESC_HDR                                  0x02U
+#define  USB_LEN_DEV_DESC                                  0x12U
+#define  USB_LEN_CFG_DESC                                  0x09U
+#define  USB_LEN_IF_DESC                                   0x09U
+#define  USB_LEN_EP_DESC                                   0x07U
+#define  USB_LEN_OTG_DESC                                  0x03U
+#define  USB_LEN_SETUP_PKT                                 0x08U
+
+/* bmRequestType :D7 Data Phase Transfer Direction  */
+#define  USB_REQ_DIR_MASK                                  0x80U
+#define  USB_H2D                                           0x00U
+#define  USB_D2H                                           0x80U
+
+/* bmRequestType D6..5 Type */
+#define  USB_REQ_TYPE_STANDARD                             0x00U
+#define  USB_REQ_TYPE_CLASS                                0x20U
+#define  USB_REQ_TYPE_VENDOR                               0x40U
+#define  USB_REQ_TYPE_RESERVED                             0x60U
+
+/* bmRequestType D4..0 Recipient */
+#define  USB_REQ_RECIPIENT_DEVICE                          0x00U
+#define  USB_REQ_RECIPIENT_INTERFACE                       0x01U
+#define  USB_REQ_RECIPIENT_ENDPOINT                        0x02U
+#define  USB_REQ_RECIPIENT_OTHER                           0x03U
+
+/* Table 9-4. Standard Request Codes  */
+/* bRequest , Value */
+#define  USB_REQ_GET_STATUS                                0x00U
+#define  USB_REQ_CLEAR_FEATURE                             0x01U
+#define  USB_REQ_SET_FEATURE                               0x03U
+#define  USB_REQ_SET_ADDRESS                               0x05U
+#define  USB_REQ_GET_DESCRIPTOR                            0x06U
+#define  USB_REQ_SET_DESCRIPTOR                            0x07U
+#define  USB_REQ_GET_CONFIGURATION                         0x08U
+#define  USB_REQ_SET_CONFIGURATION                         0x09U
+#define  USB_REQ_GET_INTERFACE                             0x0AU
+#define  USB_REQ_SET_INTERFACE                             0x0BU
+#define  USB_REQ_SYNCH_FRAME                               0x0CU
+
+/* Table 9-5. Descriptor Types of USB Specifications */
+#define  USB_DESC_TYPE_DEVICE                              0x01U
+#define  USB_DESC_TYPE_CONFIGURATION                       0x02U
+#define  USB_DESC_TYPE_STRING                              0x03U
+#define  USB_DESC_TYPE_INTERFACE                           0x04U
+#define  USB_DESC_TYPE_ENDPOINT                            0x05U
+#define  USB_DESC_TYPE_DEVICE_QUALIFIER                    0x06U
+#define  USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION           0x07U
+#define  USB_DESC_TYPE_INTERFACE_POWER                     0x08U
+#define  USB_DESC_TYPE_HID                                 0x21U
+#define  USB_DESC_TYPE_HID_REPORT                          0x22U
+
+
+#define USB_DEVICE_DESC_SIZE                               0x12U
+#define USB_CONFIGURATION_DESC_SIZE                        0x09U
+#define USB_HID_DESC_SIZE                                  0x09U
+#define USB_INTERFACE_DESC_SIZE                            0x09U
+#define USB_ENDPOINT_DESC_SIZE                             0x07U
+
+/* Descriptor Type and Descriptor Index  */
+/* Use the following values when calling the function USBH_GetDescriptor  */
+#define  USB_DESC_DEVICE                    ((USB_DESC_TYPE_DEVICE << 8) & 0xFF00U)
+#define  USB_DESC_CONFIGURATION             ((USB_DESC_TYPE_CONFIGURATION << 8) & 0xFF00U)
+#define  USB_DESC_STRING                    ((USB_DESC_TYPE_STRING << 8) & 0xFF00U)
+#define  USB_DESC_INTERFACE                 ((USB_DESC_TYPE_INTERFACE << 8) & 0xFF00U)
+#define  USB_DESC_ENDPOINT                  ((USB_DESC_TYPE_INTERFACE << 8) & 0xFF00U)
+#define  USB_DESC_DEVICE_QUALIFIER          ((USB_DESC_TYPE_DEVICE_QUALIFIER << 8) & 0xFF00U)
+#define  USB_DESC_OTHER_SPEED_CONFIGURATION ((USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION << 8) & 0xFF00U)
+#define  USB_DESC_INTERFACE_POWER           ((USB_DESC_TYPE_INTERFACE_POWER << 8) & 0xFF00U)
+#define  USB_DESC_HID_REPORT                ((USB_DESC_TYPE_HID_REPORT << 8) & 0xFF00U)
+#define  USB_DESC_HID                       ((USB_DESC_TYPE_HID << 8) & 0xFF00U)
+
+
+#define  USB_EP_TYPE_CTRL                                  0x00U
+#define  USB_EP_TYPE_ISOC                                  0x01U
+#define  USB_EP_TYPE_BULK                                  0x02U
+#define  USB_EP_TYPE_INTR                                  0x03U
+
+#define  USB_EP_DIR_OUT                                    0x00U
+#define  USB_EP_DIR_IN                                     0x80U
+#define  USB_EP_DIR_MSK                                    0x80U
+
+#ifndef USBH_MAX_PIPES_NBR
+#define USBH_MAX_PIPES_NBR                                 16U
+#endif /* USBH_MAX_PIPES_NBR */
+
+#define USBH_DEVICE_ADDRESS_DEFAULT                        0x00U
+#define USBH_DEVICE_ADDRESS                                0x01U
+
+#define USBH_MAX_ERROR_COUNT                               0x02U
+
+#if (USBH_USE_OS == 1U)
+#define MSGQUEUE_OBJECTS                                   0x10U
+#endif
+
+
+/**
+  * @}
+  */
+
+
+#define USBH_CONFIGURATION_DESCRIPTOR_SIZE (USB_CONFIGURATION_DESC_SIZE \
+                                            + USB_INTERFACE_DESC_SIZE\
+                                            + (USBH_MAX_NUM_ENDPOINTS * USB_ENDPOINT_DESC_SIZE))
+
+
+#define CONFIG_DESC_wTOTAL_LENGTH (ConfigurationDescriptorData.ConfigDescfield.\
+                                   ConfigurationDescriptor.wTotalLength)
+
+
+typedef union
+{
+  uint16_t w;
+  struct BW
+  {
+    uint8_t msb;
+    uint8_t lsb;
+  }
+  bw;
+}
+uint16_t_uint8_t;
+
+
+typedef union _USB_Setup
+{
+  uint32_t d8[2];
+
+  struct _SetupPkt_Struc
+  {
+    uint8_t           bmRequestType;
+    uint8_t           bRequest;
+    uint16_t_uint8_t  wValue;
+    uint16_t_uint8_t  wIndex;
+    uint16_t_uint8_t  wLength;
+  } b;
+}
+USB_Setup_TypeDef;
+
+typedef  struct  _DescHeader
+{
+  uint8_t  bLength;
+  uint8_t  bDescriptorType;
+}
+USBH_DescHeader_t;
+
+typedef struct _DeviceDescriptor
+{
+  uint8_t   bLength;
+  uint8_t   bDescriptorType;
+  uint16_t  bcdUSB;        /* USB Specification Number which device complies too */
+  uint8_t   bDeviceClass;
+  uint8_t   bDeviceSubClass;
+  uint8_t   bDeviceProtocol;
+  /* If equal to Zero, each interface specifies its own class
+  code if equal to 0xFF, the class code is vendor specified.
+  Otherwise field is valid Class Code.*/
+  uint8_t   bMaxPacketSize;
+  uint16_t  idVendor;      /* Vendor ID (Assigned by USB Org) */
+  uint16_t  idProduct;     /* Product ID (Assigned by Manufacturer) */
+  uint16_t  bcdDevice;     /* Device Release Number */
+  uint8_t   iManufacturer;  /* Index of Manufacturer String Descriptor */
+  uint8_t   iProduct;       /* Index of Product String Descriptor */
+  uint8_t   iSerialNumber;  /* Index of Serial Number String Descriptor */
+  uint8_t   bNumConfigurations; /* Number of Possible Configurations */
+}
+USBH_DevDescTypeDef;
+
+typedef struct _EndpointDescriptor
+{
+  uint8_t   bLength;
+  uint8_t   bDescriptorType;
+  uint8_t   bEndpointAddress;   /* indicates what endpoint this descriptor is describing */
+  uint8_t   bmAttributes;       /* specifies the transfer type. */
+  uint16_t  wMaxPacketSize;    /* Maximum Packet Size this endpoint is capable of sending or receiving */
+  uint8_t   bInterval;          /* is used to specify the polling interval of certain transfers. */
+}
+USBH_EpDescTypeDef;
+
+typedef struct _InterfaceDescriptor
+{
+  uint8_t bLength;
+  uint8_t bDescriptorType;
+  uint8_t bInterfaceNumber;
+  uint8_t bAlternateSetting;    /* Value used to select alternative setting */
+  uint8_t bNumEndpoints;        /* Number of Endpoints used for this interface */
+  uint8_t bInterfaceClass;      /* Class Code (Assigned by USB Org) */
+  uint8_t bInterfaceSubClass;   /* Subclass Code (Assigned by USB Org) */
+  uint8_t bInterfaceProtocol;   /* Protocol Code */
+  uint8_t iInterface;           /* Index of String Descriptor Describing this interface */
+  USBH_EpDescTypeDef               Ep_Desc[USBH_MAX_NUM_ENDPOINTS];
+}
+USBH_InterfaceDescTypeDef;
+
+
+typedef struct _ConfigurationDescriptor
+{
+  uint8_t   bLength;
+  uint8_t   bDescriptorType;
+  uint16_t  wTotalLength;        /* Total Length of Data Returned */
+  uint8_t   bNumInterfaces;       /* Number of Interfaces */
+  uint8_t   bConfigurationValue;  /* Value to use as an argument to select this configuration*/
+  uint8_t   iConfiguration;       /*Index of String Descriptor Describing this configuration */
+  uint8_t   bmAttributes;         /* D7 Bus Powered , D6 Self Powered, D5 Remote Wakeup , D4..0 Reserved (0)*/
+  uint8_t   bMaxPower;            /*Maximum Power Consumption */
+  USBH_InterfaceDescTypeDef        Itf_Desc[USBH_MAX_NUM_INTERFACES];
+}
+USBH_CfgDescTypeDef;
+
+
+/* Following USB Host status */
+typedef enum
+{
+  USBH_OK = 0,
+  USBH_BUSY,
+  USBH_FAIL,
+  USBH_NOT_SUPPORTED,
+  USBH_UNRECOVERED_ERROR,
+  USBH_ERROR_SPEED_UNKNOWN,
+} USBH_StatusTypeDef;
+
+
+/** @defgroup USBH_CORE_Exported_Types
+  * @{
+  */
+
+typedef enum
+{
+  USBH_SPEED_HIGH  = 0U,
+  USBH_SPEED_FULL  = 1U,
+  USBH_SPEED_LOW   = 2U,
+
+} USBH_SpeedTypeDef;
+
+/* Following states are used for gState */
+typedef enum
+{
+  HOST_IDLE = 0U,
+  HOST_DEV_WAIT_FOR_ATTACHMENT,
+  HOST_DEV_ATTACHED,
+  HOST_DEV_DISCONNECTED,
+  HOST_DETECT_DEVICE_SPEED,
+  HOST_ENUMERATION,
+  HOST_CLASS_REQUEST,
+  HOST_INPUT,
+  HOST_SET_CONFIGURATION,
+  HOST_SET_WAKEUP_FEATURE,
+  HOST_CHECK_CLASS,
+  HOST_CLASS,
+  HOST_SUSPENDED,
+  HOST_ABORT_STATE,
+} HOST_StateTypeDef;
+
+/* Following states are used for EnumerationState */
+typedef enum
+{
+  ENUM_IDLE = 0U,
+  ENUM_GET_FULL_DEV_DESC,
+  ENUM_SET_ADDR,
+  ENUM_GET_CFG_DESC,
+  ENUM_GET_FULL_CFG_DESC,
+  ENUM_GET_MFC_STRING_DESC,
+  ENUM_GET_PRODUCT_STRING_DESC,
+  ENUM_GET_SERIALNUM_STRING_DESC,
+} ENUM_StateTypeDef;
+
+/* Following states are used for CtrlXferStateMachine */
+typedef enum
+{
+  CTRL_IDLE = 0U,
+  CTRL_SETUP,
+  CTRL_SETUP_WAIT,
+  CTRL_DATA_IN,
+  CTRL_DATA_IN_WAIT,
+  CTRL_DATA_OUT,
+  CTRL_DATA_OUT_WAIT,
+  CTRL_STATUS_IN,
+  CTRL_STATUS_IN_WAIT,
+  CTRL_STATUS_OUT,
+  CTRL_STATUS_OUT_WAIT,
+  CTRL_ERROR,
+  CTRL_STALLED,
+  CTRL_COMPLETE
+} CTRL_StateTypeDef;
+
+
+/* Following states are used for RequestState */
+typedef enum
+{
+  CMD_IDLE = 0U,
+  CMD_SEND,
+  CMD_WAIT
+} CMD_StateTypeDef;
+
+typedef enum
+{
+  USBH_URB_IDLE = 0U,
+  USBH_URB_DONE,
+  USBH_URB_NOTREADY,
+  USBH_URB_NYET,
+  USBH_URB_ERROR,
+  USBH_URB_STALL
+} USBH_URBStateTypeDef;
+
+typedef enum
+{
+  USBH_PORT_EVENT = 1U,
+  USBH_URB_EVENT,
+  USBH_CONTROL_EVENT,
+  USBH_CLASS_EVENT,
+  USBH_STATE_CHANGED_EVENT,
+}
+USBH_OSEventTypeDef;
+
+/* Control request structure */
+typedef struct
+{
+  uint8_t               pipe_in;
+  uint8_t               pipe_out;
+  uint8_t               pipe_size;
+  uint8_t               *buff;
+  uint16_t              length;
+  uint16_t              timer;
+  USB_Setup_TypeDef     setup;
+  CTRL_StateTypeDef     state;
+  uint8_t               errorcount;
+
+} USBH_CtrlTypeDef;
+
+/* Attached device structure */
+typedef struct
+{
+  uint8_t                           CfgDesc_Raw[USBH_MAX_SIZE_CONFIGURATION];
+  uint8_t                           Data[USBH_MAX_DATA_BUFFER];
+  uint8_t                           address;
+  uint8_t                           speed;
+  uint8_t                           EnumCnt;
+  uint8_t                           RstCnt;
+  __IO uint8_t                      is_connected;
+  __IO uint8_t                      is_disconnected;
+  __IO uint8_t                      is_ReEnumerated;
+  uint8_t                           PortEnabled;
+  uint8_t                           current_interface;
+  USBH_DevDescTypeDef               DevDesc;
+  USBH_CfgDescTypeDef               CfgDesc;
+} USBH_DeviceTypeDef;
+
+struct _USBH_HandleTypeDef;
+
+/* USB Host Class structure */
+typedef struct
+{
+  const char          *Name;
+  uint8_t              ClassCode;
+  USBH_StatusTypeDef(*Init)(struct _USBH_HandleTypeDef *phost);
+  USBH_StatusTypeDef(*DeInit)(struct _USBH_HandleTypeDef *phost);
+  USBH_StatusTypeDef(*Requests)(struct _USBH_HandleTypeDef *phost);
+  USBH_StatusTypeDef(*BgndProcess)(struct _USBH_HandleTypeDef *phost);
+  USBH_StatusTypeDef(*SOFProcess)(struct _USBH_HandleTypeDef *phost);
+  void                *pData;
+} USBH_ClassTypeDef;
+
+/* USB Host handle structure */
+typedef struct _USBH_HandleTypeDef
+{
+  __IO HOST_StateTypeDef     gState;       /*  Host State Machine Value */
+  ENUM_StateTypeDef     EnumState;    /* Enumeration state Machine */
+  CMD_StateTypeDef      RequestState;
+  USBH_CtrlTypeDef      Control;
+  USBH_DeviceTypeDef    device;
+  USBH_ClassTypeDef    *pClass[USBH_MAX_NUM_SUPPORTED_CLASS];
+  USBH_ClassTypeDef    *pActiveClass;
+  uint32_t              ClassNumber;
+  uint32_t              Pipes[16];
+  __IO uint32_t         Timer;
+  uint32_t              Timeout;
+  uint8_t               id;
+  void                 *pData;
+  void (* pUser)(struct _USBH_HandleTypeDef *pHandle, uint8_t id);
+
+#if (USBH_USE_OS == 1U)
+#if osCMSIS < 0x20000
+  osMessageQId          os_event;
+  osThreadId            thread;
+#else
+  osMessageQueueId_t    os_event;
+  osThreadId_t          thread;
+#endif
+  uint32_t              os_msg;
+#endif
+
+} USBH_HandleTypeDef;
+
+
+#if  defined ( __GNUC__ )
+#ifndef __weak
+#define __weak   __attribute__((weak))
+#endif /* __weak */
+#ifndef __packed
+#define __packed __attribute__((__packed__))
+#endif /* __packed */
+#endif /* __GNUC__ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* USBH_DEF_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/Middlewares/ST/STM32_USB_Host_Library/Core/Inc/usbh_ioreq.h b/Middlewares/ST/STM32_USB_Host_Library/Core/Inc/usbh_ioreq.h
new file mode 100644
index 0000000..7592e55
--- /dev/null
+++ b/Middlewares/ST/STM32_USB_Host_Library/Core/Inc/usbh_ioreq.h
@@ -0,0 +1,160 @@
+/**
+  ******************************************************************************
+  * @file    usbh_ioreq.h
+  * @author  MCD Application Team
+  * @brief   Header file for usbh_ioreq.c
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2015 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                      www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive  ----------------------------------------------*/
+#ifndef __USBH_IOREQ_H
+#define __USBH_IOREQ_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "usbh_conf.h"
+#include "usbh_core.h"
+
+/** @addtogroup USBH_LIB
+  * @{
+  */
+
+/** @addtogroup USBH_LIB_CORE
+  * @{
+  */
+
+/** @defgroup USBH_IOREQ
+  * @brief This file is the header file for usbh_ioreq.c
+  * @{
+  */
+
+
+/** @defgroup USBH_IOREQ_Exported_Defines
+  * @{
+  */
+
+#define USBH_PID_SETUP                            0U
+#define USBH_PID_DATA                             1U
+
+#define USBH_EP_CONTROL                           0U
+#define USBH_EP_ISO                               1U
+#define USBH_EP_BULK                              2U
+#define USBH_EP_INTERRUPT                         3U
+
+#define USBH_SETUP_PKT_SIZE                       8U
+/**
+  * @}
+  */
+
+
+/** @defgroup USBH_IOREQ_Exported_Types
+  * @{
+  */
+/**
+  * @}
+  */
+
+
+/** @defgroup USBH_IOREQ_Exported_Macros
+  * @{
+  */
+/**
+  * @}
+  */
+
+/** @defgroup USBH_IOREQ_Exported_Variables
+  * @{
+  */
+/**
+  * @}
+  */
+
+/** @defgroup USBH_IOREQ_Exported_FunctionsPrototype
+  * @{
+  */
+USBH_StatusTypeDef USBH_CtlSendSetup(USBH_HandleTypeDef *phost,
+                                     uint8_t *buff,
+                                     uint8_t pipe_num);
+
+USBH_StatusTypeDef USBH_CtlSendData(USBH_HandleTypeDef *phost,
+                                    uint8_t *buff,
+                                    uint16_t length,
+                                    uint8_t pipe_num,
+                                    uint8_t do_ping);
+
+USBH_StatusTypeDef USBH_CtlReceiveData(USBH_HandleTypeDef *phost,
+                                       uint8_t *buff,
+                                       uint16_t length,
+                                       uint8_t pipe_num);
+
+USBH_StatusTypeDef USBH_BulkReceiveData(USBH_HandleTypeDef *phost,
+                                        uint8_t *buff,
+                                        uint16_t length,
+                                        uint8_t pipe_num);
+
+USBH_StatusTypeDef USBH_BulkSendData(USBH_HandleTypeDef *phost,
+                                     uint8_t *buff,
+                                     uint16_t length,
+                                     uint8_t pipe_num,
+                                     uint8_t do_ping);
+
+USBH_StatusTypeDef USBH_InterruptReceiveData(USBH_HandleTypeDef *phost,
+                                             uint8_t             *buff,
+                                             uint8_t             length,
+                                             uint8_t             pipe_num);
+
+USBH_StatusTypeDef USBH_InterruptSendData(USBH_HandleTypeDef *phost,
+                                          uint8_t *buff,
+                                          uint8_t length,
+                                          uint8_t pipe_num);
+
+
+USBH_StatusTypeDef USBH_IsocReceiveData(USBH_HandleTypeDef *phost,
+                                        uint8_t *buff,
+                                        uint32_t length,
+                                        uint8_t pipe_num);
+
+
+USBH_StatusTypeDef USBH_IsocSendData(USBH_HandleTypeDef *phost,
+                                     uint8_t *buff,
+                                     uint32_t length,
+                                     uint8_t pipe_num);
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __USBH_IOREQ_H */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
+
diff --git a/Middlewares/ST/STM32_USB_Host_Library/Core/Inc/usbh_pipes.h b/Middlewares/ST/STM32_USB_Host_Library/Core/Inc/usbh_pipes.h
new file mode 100644
index 0000000..98d4f0a
--- /dev/null
+++ b/Middlewares/ST/STM32_USB_Host_Library/Core/Inc/usbh_pipes.h
@@ -0,0 +1,123 @@
+/**
+  ******************************************************************************
+  * @file    usbh_pipes.h
+  * @author  MCD Application Team
+  * @brief   Header file for usbh_pipes.c
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2015 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                      www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive  ----------------------------------------------*/
+#ifndef __USBH_PIPES_H
+#define __USBH_PIPES_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "usbh_core.h"
+
+/** @addtogroup USBH_LIB
+  * @{
+  */
+
+/** @addtogroup USBH_LIB_CORE
+  * @{
+  */
+
+/** @defgroup USBH_PIPES
+  * @brief This file is the header file for usbh_pipes.c
+  * @{
+  */
+
+/** @defgroup USBH_PIPES_Exported_Defines
+  * @{
+  */
+/**
+  * @}
+  */
+
+/** @defgroup USBH_PIPES_Exported_Types
+  * @{
+  */
+/**
+  * @}
+  */
+
+
+/** @defgroup USBH_PIPES_Exported_Macros
+  * @{
+  */
+/**
+  * @}
+  */
+
+/** @defgroup USBH_PIPES_Exported_Variables
+  * @{
+  */
+/**
+  * @}
+  */
+
+/** @defgroup USBH_PIPES_Exported_FunctionsPrototype
+  * @{
+  */
+
+USBH_StatusTypeDef USBH_OpenPipe(USBH_HandleTypeDef *phost,
+                                 uint8_t pipe_num,
+                                 uint8_t epnum,
+                                 uint8_t dev_address,
+                                 uint8_t speed,
+                                 uint8_t ep_type,
+                                 uint16_t mps);
+
+USBH_StatusTypeDef USBH_ClosePipe(USBH_HandleTypeDef *phost,
+                                  uint8_t pipe_num);
+
+uint8_t USBH_AllocPipe(USBH_HandleTypeDef *phost,
+                       uint8_t ep_addr);
+
+USBH_StatusTypeDef USBH_FreePipe(USBH_HandleTypeDef *phost,
+                                 uint8_t idx);
+
+
+
+
+/**
+  * @}
+  */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __USBH_PIPES_H */
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
+
diff --git a/Middlewares/ST/STM32_USB_Host_Library/Core/Src/usbh_core.c b/Middlewares/ST/STM32_USB_Host_Library/Core/Src/usbh_core.c
new file mode 100644
index 0000000..832559a
--- /dev/null
+++ b/Middlewares/ST/STM32_USB_Host_Library/Core/Src/usbh_core.c
@@ -0,0 +1,1397 @@
+/**
+  ******************************************************************************
+  * @file    usbh_core.c
+  * @author  MCD Application Team
+  * @brief   This file implements the functions for the core state machine process
+  *          the enumeration and the control transfer process
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2015 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                      www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "usbh_core.h"
+
+
+/** @addtogroup USBH_LIB
+  * @{
+  */
+
+/** @addtogroup USBH_LIB_CORE
+  * @{
+  */
+
+/** @defgroup USBH_CORE
+  * @brief This file handles the basic enumeration when a device is connected
+  *          to the host.
+  * @{
+  */
+
+
+/** @defgroup USBH_CORE_Private_Defines
+  * @{
+  */
+#define USBH_ADDRESS_DEFAULT                     0x00U
+#define USBH_ADDRESS_ASSIGNED                    0x01U
+#define USBH_MPS_DEFAULT                         0x40U
+/**
+  * @}
+  */
+
+/** @defgroup USBH_CORE_Private_Macros
+  * @{
+  */
+/**
+  * @}
+  */
+
+
+/** @defgroup USBH_CORE_Private_Variables
+  * @{
+  */
+#if (USBH_USE_OS == 1U)
+#if (osCMSIS >= 0x20000U)
+osThreadAttr_t USBH_Thread_Atrr;
+#endif
+#endif
+
+
+/**
+  * @}
+  */
+
+
+/** @defgroup USBH_CORE_Private_Functions
+  * @{
+  */
+static USBH_StatusTypeDef USBH_HandleEnum(USBH_HandleTypeDef *phost);
+static void USBH_HandleSof(USBH_HandleTypeDef *phost);
+static USBH_StatusTypeDef DeInitStateMachine(USBH_HandleTypeDef *phost);
+
+#if (USBH_USE_OS == 1U)
+#if (osCMSIS < 0x20000U)
+static void USBH_Process_OS(void const *argument);
+#else
+static void USBH_Process_OS(void *argument);
+#endif
+#endif
+
+
+/**
+  * @brief  HCD_Init
+  *         Initialize the HOST Core.
+  * @param  phost: Host Handle
+  * @param  pUsrFunc: User Callback
+  * @retval USBH Status
+  */
+USBH_StatusTypeDef  USBH_Init(USBH_HandleTypeDef *phost,
+                              void (*pUsrFunc)(USBH_HandleTypeDef *phost,
+                                               uint8_t id), uint8_t id)
+{
+  /* Check whether the USB Host handle is valid */
+  if (phost == NULL)
+  {
+    USBH_ErrLog("Invalid Host handle");
+    return USBH_FAIL;
+  }
+
+  /* Set DRiver ID */
+  phost->id = id;
+
+  /* Unlink class*/
+  phost->pActiveClass = NULL;
+  phost->ClassNumber = 0U;
+
+  /* Restore default states and prepare EP0 */
+  (void)DeInitStateMachine(phost);
+
+  /* Restore default Device connection states */
+  phost->device.PortEnabled = 0U;
+  phost->device.is_connected = 0U;
+  phost->device.is_disconnected = 0U;
+  phost->device.is_ReEnumerated = 0U;
+
+  /* Assign User process */
+  if (pUsrFunc != NULL)
+  {
+    phost->pUser = pUsrFunc;
+  }
+
+#if (USBH_USE_OS == 1U)
+#if (osCMSIS < 0x20000U)
+
+  /* Create USB Host Queue */
+  osMessageQDef(USBH_Queue, MSGQUEUE_OBJECTS, uint16_t);
+  phost->os_event = osMessageCreate(osMessageQ(USBH_Queue), NULL);
+
+  /* Create USB Host Task */
+#if defined (USBH_PROCESS_STACK_SIZE)
+  osThreadDef(USBH_Thread, USBH_Process_OS, USBH_PROCESS_PRIO, 0U, USBH_PROCESS_STACK_SIZE);
+#else
+  osThreadDef(USBH_Thread, USBH_Process_OS, USBH_PROCESS_PRIO, 0U, 8U * configMINIMAL_STACK_SIZE);
+#endif /* defined (USBH_PROCESS_STACK_SIZE) */
+
+  phost->thread = osThreadCreate(osThread(USBH_Thread), phost);
+
+#else
+
+  /* Create USB Host Queue */
+  phost->os_event = osMessageQueueNew(MSGQUEUE_OBJECTS, sizeof(uint32_t), NULL);
+
+  /* Create USB Host Task */
+  USBH_Thread_Atrr.name = "USBH_Queue";
+
+#if defined (USBH_PROCESS_STACK_SIZE)
+  USBH_Thread_Atrr.stack_size = USBH_PROCESS_STACK_SIZE;
+#else
+  USBH_Thread_Atrr.stack_size = (8U * configMINIMAL_STACK_SIZE);
+#endif /* defined (USBH_PROCESS_STACK_SIZE) */
+
+  USBH_Thread_Atrr.priority = USBH_PROCESS_PRIO;
+  phost->thread = osThreadNew(USBH_Process_OS, phost, &USBH_Thread_Atrr);
+
+#endif /* (osCMSIS < 0x20000U) */
+#endif /* (USBH_USE_OS == 1U) */
+
+  /* Initialize low level driver */
+  (void)USBH_LL_Init(phost);
+
+  return USBH_OK;
+}
+
+
+/**
+  * @brief  HCD_Init
+  *         De-Initialize the Host portion of the driver.
+  * @param  phost: Host Handle
+  * @retval USBH Status
+  */
+USBH_StatusTypeDef USBH_DeInit(USBH_HandleTypeDef *phost)
+{
+  (void)DeInitStateMachine(phost);
+
+  /* Restore default Device connection states */
+  phost->device.PortEnabled = 0U;
+  phost->device.is_connected = 0U;
+  phost->device.is_disconnected = 0U;
+  phost->device.is_ReEnumerated = 0U;
+  phost->device.RstCnt = 0U;
+  phost->device.EnumCnt = 0U;
+
+  if (phost->pData != NULL)
+  {
+    (void)USBH_LL_Stop(phost);
+  }
+
+#if (USBH_USE_OS == 1U)
+#if (osCMSIS < 0x20000U)
+
+  /* Free allocated resource for USBH process */
+  (void)osThreadTerminate(phost->thread);
+  (void)osMessageDelete(phost->os_event);
+
+#else
+
+  /* Free allocated resource for USBH process */
+  (void)osThreadTerminate(phost->thread);
+  (void)osMessageQueueDelete(phost->os_event);
+
+#endif /* (osCMSIS < 0x20000U) */
+#endif /* (USBH_USE_OS == 1U) */
+
+  return USBH_OK;
+}
+
+
+/**
+  * @brief  DeInitStateMachine
+  *         De-Initialize the Host state machine.
+  * @param  phost: Host Handle
+  * @retval USBH Status
+  */
+static USBH_StatusTypeDef DeInitStateMachine(USBH_HandleTypeDef *phost)
+{
+  uint32_t i = 0U;
+
+  /* Clear Pipes flags*/
+  for (i = 0U; i < USBH_MAX_PIPES_NBR; i++)
+  {
+    phost->Pipes[i] = 0U;
+  }
+
+  for (i = 0U; i < USBH_MAX_DATA_BUFFER; i++)
+  {
+    phost->device.Data[i] = 0U;
+  }
+
+  phost->gState = HOST_IDLE;
+  phost->EnumState = ENUM_IDLE;
+  phost->RequestState = CMD_SEND;
+  phost->Timer = 0U;
+
+  phost->Control.state = CTRL_SETUP;
+  phost->Control.pipe_size = USBH_MPS_DEFAULT;
+  phost->Control.errorcount = 0U;
+
+  phost->device.address = USBH_ADDRESS_DEFAULT;
+  phost->device.speed = (uint8_t)USBH_SPEED_FULL;
+  phost->device.RstCnt = 0U;
+  phost->device.EnumCnt = 0U;
+
+  return USBH_OK;
+}
+
+
+/**
+  * @brief  USBH_RegisterClass
+  *         Link class driver to Host Core.
+  * @param  phost : Host Handle
+  * @param  pclass: Class handle
+  * @retval USBH Status
+  */
+USBH_StatusTypeDef USBH_RegisterClass(USBH_HandleTypeDef *phost, USBH_ClassTypeDef *pclass)
+{
+  USBH_StatusTypeDef status = USBH_OK;
+
+  if (pclass != NULL)
+  {
+    if (phost->ClassNumber < USBH_MAX_NUM_SUPPORTED_CLASS)
+    {
+      /* link the class to the USB Host handle */
+      phost->pClass[phost->ClassNumber++] = pclass;
+      status = USBH_OK;
+    }
+    else
+    {
+      USBH_ErrLog("Max Class Number reached");
+      status = USBH_FAIL;
+    }
+  }
+  else
+  {
+    USBH_ErrLog("Invalid Class handle");
+    status = USBH_FAIL;
+  }
+
+  return status;
+}
+
+
+/**
+  * @brief  USBH_SelectInterface
+  *         Select current interface.
+  * @param  phost: Host Handle
+  * @param  interface: Interface number
+  * @retval USBH Status
+  */
+USBH_StatusTypeDef USBH_SelectInterface(USBH_HandleTypeDef *phost, uint8_t interface)
+{
+  USBH_StatusTypeDef status = USBH_OK;
+
+  if (interface < phost->device.CfgDesc.bNumInterfaces)
+  {
+    phost->device.current_interface = interface;
+    USBH_UsrLog("Switching to Interface (#%d)", interface);
+    USBH_UsrLog("Class    : %xh", phost->device.CfgDesc.Itf_Desc[interface].bInterfaceClass);
+    USBH_UsrLog("SubClass : %xh", phost->device.CfgDesc.Itf_Desc[interface].bInterfaceSubClass);
+    USBH_UsrLog("Protocol : %xh", phost->device.CfgDesc.Itf_Desc[interface].bInterfaceProtocol);
+  }
+  else
+  {
+    USBH_ErrLog("Cannot Select This Interface.");
+    status = USBH_FAIL;
+  }
+
+  return status;
+}
+
+
+/**
+  * @brief  USBH_GetActiveClass
+  *         Return Device Class.
+  * @param  phost: Host Handle
+  * @param  interface: Interface index
+  * @retval Class Code
+  */
+uint8_t USBH_GetActiveClass(USBH_HandleTypeDef *phost)
+{
+  return (phost->device.CfgDesc.Itf_Desc[0].bInterfaceClass);
+}
+
+
+/**
+  * @brief  USBH_FindInterface
+  *         Find the interface index for a specific class.
+  * @param  phost: Host Handle
+  * @param  Class: Class code
+  * @param  SubClass: SubClass code
+  * @param  Protocol: Protocol code
+  * @retval interface index in the configuration structure
+  * @note : (1)interface index 0xFF means interface index not found
+  */
+uint8_t  USBH_FindInterface(USBH_HandleTypeDef *phost, uint8_t Class, uint8_t SubClass, uint8_t Protocol)
+{
+  USBH_InterfaceDescTypeDef *pif;
+  USBH_CfgDescTypeDef *pcfg;
+  uint8_t if_ix = 0U;
+
+  pif = (USBH_InterfaceDescTypeDef *)NULL;
+  pcfg = &phost->device.CfgDesc;
+
+  while (if_ix < USBH_MAX_NUM_INTERFACES)
+  {
+    pif = &pcfg->Itf_Desc[if_ix];
+    if (((pif->bInterfaceClass == Class) || (Class == 0xFFU)) &&
+        ((pif->bInterfaceSubClass == SubClass) || (SubClass == 0xFFU)) &&
+        ((pif->bInterfaceProtocol == Protocol) || (Protocol == 0xFFU)))
+    {
+      return  if_ix;
+    }
+    if_ix++;
+  }
+  return 0xFFU;
+}
+
+
+/**
+  * @brief  USBH_FindInterfaceIndex
+  *         Find the interface index for a specific class interface and alternate setting number.
+  * @param  phost: Host Handle
+  * @param  interface_number: interface number
+  * @param  alt_settings    : alternate setting number
+  * @retval interface index in the configuration structure
+  * @note : (1)interface index 0xFF means interface index not found
+  */
+uint8_t  USBH_FindInterfaceIndex(USBH_HandleTypeDef *phost, uint8_t interface_number, uint8_t alt_settings)
+{
+  USBH_InterfaceDescTypeDef *pif;
+  USBH_CfgDescTypeDef *pcfg;
+  uint8_t if_ix = 0U;
+
+  pif = (USBH_InterfaceDescTypeDef *)NULL;
+  pcfg = &phost->device.CfgDesc;
+
+  while (if_ix < USBH_MAX_NUM_INTERFACES)
+  {
+    pif = &pcfg->Itf_Desc[if_ix];
+    if ((pif->bInterfaceNumber == interface_number) && (pif->bAlternateSetting == alt_settings))
+    {
+      return  if_ix;
+    }
+    if_ix++;
+  }
+  return 0xFFU;
+}
+
+
+/**
+  * @brief  USBH_Start
+  *         Start the USB Host Core.
+  * @param  phost: Host Handle
+  * @retval USBH Status
+  */
+USBH_StatusTypeDef  USBH_Start(USBH_HandleTypeDef *phost)
+{
+  /* Start the low level driver  */
+  (void)USBH_LL_Start(phost);
+
+  /* Activate VBUS on the port */
+  (void)USBH_LL_DriverVBUS(phost, TRUE);
+
+  return USBH_OK;
+}
+
+
+/**
+  * @brief  USBH_Stop
+  *         Stop the USB Host Core.
+  * @param  phost: Host Handle
+  * @retval USBH Status
+  */
+USBH_StatusTypeDef  USBH_Stop(USBH_HandleTypeDef *phost)
+{
+  /* DeActivate VBUS on the port */
+  (void)USBH_LL_DriverVBUS(phost, FALSE);
+
+  /* Stop and cleanup the low level driver  */
+  (void)USBH_LL_Stop(phost);
+
+  /* Free Control Pipes */
+  (void)USBH_FreePipe(phost, phost->Control.pipe_in);
+  (void)USBH_FreePipe(phost, phost->Control.pipe_out);
+
+  return USBH_OK;
+}
+
+
+/**
+  * @brief  HCD_ReEnumerate
+  *         Perform a new Enumeration phase.
+  * @param  phost: Host Handle
+  * @retval USBH Status
+  */
+USBH_StatusTypeDef USBH_ReEnumerate(USBH_HandleTypeDef *phost)
+{
+  if (USBH_IsPortEnabled(phost) != 0U)
+  {
+    phost->device.is_ReEnumerated = 1U;
+
+    /* Stop Host */
+    (void)USBH_Stop(phost);
+
+    phost->device.is_disconnected = 1U;
+  }
+
+#if (USBH_USE_OS == 1U)
+  phost->os_msg = (uint32_t)USBH_PORT_EVENT;
+#if (osCMSIS < 0x20000U)
+  (void)osMessagePut(phost->os_event, phost->os_msg, 0U);
+#else
+  (void)osMessageQueuePut(phost->os_event, &phost->os_msg, 0U, 0U);
+#endif
+#endif
+
+  return USBH_OK;
+}
+
+
+/**
+  * @brief  USBH_Process
+  *         Background process of the USB Core.
+  * @param  phost: Host Handle
+  * @retval USBH Status
+  */
+USBH_StatusTypeDef  USBH_Process(USBH_HandleTypeDef *phost)
+{
+  __IO USBH_StatusTypeDef status = USBH_FAIL;
+  uint8_t idx = 0U;
+
+  /* check for Host pending port disconnect event */
+  if (phost->device.is_disconnected == 1U)
+  {
+    phost->gState = HOST_DEV_DISCONNECTED;
+  }
+
+  switch (phost->gState)
+  {
+    case HOST_IDLE :
+
+      if ((phost->device.is_connected) != 0U)
+      {
+        USBH_UsrLog("USB Device Connected");
+
+        /* Wait for 200 ms after connection */
+        phost->gState = HOST_DEV_WAIT_FOR_ATTACHMENT;
+        USBH_Delay(200U);
+        (void)USBH_LL_ResetPort(phost);
+
+        /* Make sure to start with Default address */
+        phost->device.address = USBH_ADDRESS_DEFAULT;
+        phost->Timeout = 0U;
+
+#if (USBH_USE_OS == 1U)
+        phost->os_msg = (uint32_t)USBH_PORT_EVENT;
+#if (osCMSIS < 0x20000U)
+        (void)osMessagePut(phost->os_event, phost->os_msg, 0U);
+#else
+        (void)osMessageQueuePut(phost->os_event, &phost->os_msg, 0U, 0U);
+#endif
+#endif
+      }
+      break;
+
+    case HOST_DEV_WAIT_FOR_ATTACHMENT: /* Wait for Port Enabled */
+
+      if (phost->device.PortEnabled == 1U)
+      {
+        USBH_UsrLog("USB Device Reset Completed");
+        phost->device.RstCnt = 0U;
+        phost->gState = HOST_DEV_ATTACHED;
+      }
+      else
+      {
+        if (phost->Timeout > USBH_DEV_RESET_TIMEOUT)
+        {
+          phost->device.RstCnt++;
+          if (phost->device.RstCnt > 3U)
+          {
+            /* Buggy Device can't complete reset */
+            USBH_UsrLog("USB Reset Failed, Please unplug the Device.");
+            phost->gState = HOST_ABORT_STATE;
+          }
+          else
+          {
+            phost->gState = HOST_IDLE;
+          }
+        }
+        else
+        {
+          phost->Timeout += 10U;
+          USBH_Delay(10U);
+        }
+      }
+#if (USBH_USE_OS == 1U)
+      phost->os_msg = (uint32_t)USBH_PORT_EVENT;
+#if (osCMSIS < 0x20000U)
+      (void)osMessagePut(phost->os_event, phost->os_msg, 0U);
+#else
+      (void)osMessageQueuePut(phost->os_event, &phost->os_msg, 0U, 0U);
+#endif
+#endif
+      break;
+
+    case HOST_DEV_ATTACHED :
+
+      if (phost->pUser != NULL)
+      {
+        phost->pUser(phost, HOST_USER_CONNECTION);
+      }
+
+      /* Wait for 100 ms after Reset */
+      USBH_Delay(100U);
+
+      phost->device.speed = (uint8_t)USBH_LL_GetSpeed(phost);
+
+      phost->gState = HOST_ENUMERATION;
+
+      phost->Control.pipe_out = USBH_AllocPipe(phost, 0x00U);
+      phost->Control.pipe_in  = USBH_AllocPipe(phost, 0x80U);
+
+      /* Open Control pipes */
+      (void)USBH_OpenPipe(phost, phost->Control.pipe_in, 0x80U,
+                          phost->device.address, phost->device.speed,
+                          USBH_EP_CONTROL, (uint16_t)phost->Control.pipe_size);
+
+      /* Open Control pipes */
+      (void)USBH_OpenPipe(phost, phost->Control.pipe_out, 0x00U,
+                          phost->device.address, phost->device.speed,
+                          USBH_EP_CONTROL, (uint16_t)phost->Control.pipe_size);
+
+#if (USBH_USE_OS == 1U)
+      phost->os_msg = (uint32_t)USBH_PORT_EVENT;
+#if (osCMSIS < 0x20000U)
+      (void)osMessagePut(phost->os_event, phost->os_msg, 0U);
+#else
+      (void)osMessageQueuePut(phost->os_event, &phost->os_msg, 0U, 0U);
+#endif
+#endif
+      break;
+
+    case HOST_ENUMERATION:
+      /* Check for enumeration status */
+      status = USBH_HandleEnum(phost);
+      if (status == USBH_OK)
+      {
+        /* The function shall return USBH_OK when full enumeration is complete */
+        USBH_UsrLog("Enumeration done.");
+
+        phost->device.current_interface = 0U;
+
+        if (phost->device.DevDesc.bNumConfigurations == 1U)
+        {
+          USBH_UsrLog("This device has only 1 configuration.");
+          phost->gState = HOST_SET_CONFIGURATION;
+        }
+        else
+        {
+          phost->gState = HOST_INPUT;
+        }
+#if (USBH_USE_OS == 1U)
+        phost->os_msg = (uint32_t)USBH_STATE_CHANGED_EVENT;
+#if (osCMSIS < 0x20000U)
+        (void)osMessagePut(phost->os_event, phost->os_msg, 0U);
+#else
+        (void)osMessageQueuePut(phost->os_event, &phost->os_msg, 0U, 0U);
+#endif
+#endif
+      }
+      break;
+
+    case HOST_INPUT:
+    {
+      /* user callback for end of device basic enumeration */
+      if (phost->pUser != NULL)
+      {
+        phost->pUser(phost, HOST_USER_SELECT_CONFIGURATION);
+        phost->gState = HOST_SET_CONFIGURATION;
+
+#if (USBH_USE_OS == 1U)
+        phost->os_msg = (uint32_t)USBH_STATE_CHANGED_EVENT;
+#if (osCMSIS < 0x20000U)
+        (void)osMessagePut(phost->os_event, phost->os_msg, 0U);
+#else
+        (void)osMessageQueuePut(phost->os_event, &phost->os_msg, 0U, 0U);
+#endif
+#endif
+      }
+    }
+    break;
+
+    case HOST_SET_CONFIGURATION:
+      /* set configuration */
+      if (USBH_SetCfg(phost, (uint16_t)phost->device.CfgDesc.bConfigurationValue) == USBH_OK)
+      {
+        phost->gState = HOST_SET_WAKEUP_FEATURE;
+        USBH_UsrLog("Default configuration set.");
+      }
+
+#if (USBH_USE_OS == 1U)
+      phost->os_msg = (uint32_t)USBH_PORT_EVENT;
+#if (osCMSIS < 0x20000U)
+      (void)osMessagePut(phost->os_event, phost->os_msg, 0U);
+#else
+      (void)osMessageQueuePut(phost->os_event, &phost->os_msg, 0U, 0U);
+#endif
+#endif
+      break;
+
+    case  HOST_SET_WAKEUP_FEATURE:
+
+      if (((phost->device.CfgDesc.bmAttributes) & (1U << 5)) != 0U)
+      {
+        status = USBH_SetFeature(phost, FEATURE_SELECTOR_REMOTEWAKEUP);
+
+        if (status == USBH_OK)
+        {
+          USBH_UsrLog("Device remote wakeup enabled");
+          phost->gState = HOST_CHECK_CLASS;
+        }
+        else if (status == USBH_NOT_SUPPORTED)
+        {
+          USBH_UsrLog("Remote wakeup not supported by the device");
+          phost->gState = HOST_CHECK_CLASS;
+        }
+        else
+        {
+          /* .. */
+        }
+      }
+      else
+      {
+        phost->gState = HOST_CHECK_CLASS;
+      }
+
+#if (USBH_USE_OS == 1U)
+      phost->os_msg = (uint32_t)USBH_PORT_EVENT;
+#if (osCMSIS < 0x20000U)
+      (void)osMessagePut(phost->os_event, phost->os_msg, 0U);
+#else
+      (void)osMessageQueuePut(phost->os_event, &phost->os_msg, 0U, 0U);
+#endif
+#endif
+      break;
+
+    case HOST_CHECK_CLASS:
+
+      if (phost->ClassNumber == 0U)
+      {
+        USBH_UsrLog("No Class has been registered.");
+      }
+      else
+      {
+        phost->pActiveClass = NULL;
+
+        for (idx = 0U; idx < USBH_MAX_NUM_SUPPORTED_CLASS; idx++)
+        {
+          if (phost->pClass[idx]->ClassCode == phost->device.CfgDesc.Itf_Desc[0].bInterfaceClass)
+          {
+            phost->pActiveClass = phost->pClass[idx];
+            break;
+          }
+        }
+
+        if (phost->pActiveClass != NULL)
+        {
+          if (phost->pActiveClass->Init(phost) == USBH_OK)
+          {
+            phost->gState = HOST_CLASS_REQUEST;
+            USBH_UsrLog("%s class started.", phost->pActiveClass->Name);
+
+            /* Inform user that a class has been activated */
+            phost->pUser(phost, HOST_USER_CLASS_SELECTED);
+          }
+          else
+          {
+            phost->gState = HOST_ABORT_STATE;
+            USBH_UsrLog("Device not supporting %s class.", phost->pActiveClass->Name);
+          }
+        }
+        else
+        {
+          phost->gState = HOST_ABORT_STATE;
+          USBH_UsrLog("No registered class for this device.");
+        }
+      }
+
+#if (USBH_USE_OS == 1U)
+      phost->os_msg = (uint32_t)USBH_STATE_CHANGED_EVENT;
+#if (osCMSIS < 0x20000U)
+      (void)osMessagePut(phost->os_event, phost->os_msg, 0U);
+#else
+      (void)osMessageQueuePut(phost->os_event, &phost->os_msg, 0U, 0U);
+#endif
+#endif
+      break;
+
+    case HOST_CLASS_REQUEST:
+      /* process class standard control requests state machine */
+      if (phost->pActiveClass != NULL)
+      {
+        status = phost->pActiveClass->Requests(phost);
+
+        if (status == USBH_OK)
+        {
+          phost->gState = HOST_CLASS;
+        }
+        else if (status == USBH_FAIL)
+        {
+          phost->gState = HOST_ABORT_STATE;
+          USBH_ErrLog("Device not responding Please Unplug.");
+        }
+        else
+        {
+          /* .. */
+        }
+      }
+      else
+      {
+        phost->gState = HOST_ABORT_STATE;
+        USBH_ErrLog("Invalid Class Driver.");
+      }
+#if (USBH_USE_OS == 1U)
+      phost->os_msg = (uint32_t)USBH_STATE_CHANGED_EVENT;
+#if (osCMSIS < 0x20000U)
+      (void)osMessagePut(phost->os_event, phost->os_msg, 0U);
+#else
+      (void)osMessageQueuePut(phost->os_event, &phost->os_msg, 0U, 0U);
+#endif
+#endif
+      break;
+
+    case HOST_CLASS:
+      /* process class state machine */
+      if (phost->pActiveClass != NULL)
+      {
+        phost->pActiveClass->BgndProcess(phost);
+      }
+      break;
+
+    case HOST_DEV_DISCONNECTED :
+      phost->device.is_disconnected = 0U;
+
+      (void)DeInitStateMachine(phost);
+
+      /* Re-Initilaize Host for new Enumeration */
+      if (phost->pActiveClass != NULL)
+      {
+        phost->pActiveClass->DeInit(phost);
+        phost->pActiveClass = NULL;
+      }
+
+      if (phost->pUser != NULL)
+      {
+        phost->pUser(phost, HOST_USER_DISCONNECTION);
+      }
+      USBH_UsrLog("USB Device disconnected");
+
+      if (phost->device.is_ReEnumerated == 1U)
+      {
+        phost->device.is_ReEnumerated = 0U;
+
+        /* Start the host and re-enable Vbus */
+        (void)USBH_Start(phost);
+      }
+      else
+      {
+        /* Device Disconnection Completed, start USB Driver */
+        (void)USBH_LL_Start(phost);
+      }
+
+#if (USBH_USE_OS == 1U)
+      phost->os_msg = (uint32_t)USBH_PORT_EVENT;
+#if (osCMSIS < 0x20000U)
+      (void)osMessagePut(phost->os_event, phost->os_msg, 0U);
+#else
+      (void)osMessageQueuePut(phost->os_event, &phost->os_msg, 0U, 0U);
+#endif
+#endif
+      break;
+
+    case HOST_ABORT_STATE:
+    default :
+      break;
+  }
+  return USBH_OK;
+}
+
+
+/**
+  * @brief  USBH_HandleEnum
+  *         This function includes the complete enumeration process
+  * @param  phost: Host Handle
+  * @retval USBH_Status
+  */
+static USBH_StatusTypeDef USBH_HandleEnum(USBH_HandleTypeDef *phost)
+{
+  USBH_StatusTypeDef Status = USBH_BUSY;
+  USBH_StatusTypeDef ReqStatus = USBH_BUSY;
+
+  switch (phost->EnumState)
+  {
+    case ENUM_IDLE:
+      /* Get Device Desc for only 1st 8 bytes : To get EP0 MaxPacketSize */
+      ReqStatus = USBH_Get_DevDesc(phost, 8U);
+      if (ReqStatus == USBH_OK)
+      {
+        phost->Control.pipe_size = phost->device.DevDesc.bMaxPacketSize;
+
+        phost->EnumState = ENUM_GET_FULL_DEV_DESC;
+
+        /* modify control channels configuration for MaxPacket size */
+        (void)USBH_OpenPipe(phost, phost->Control.pipe_in, 0x80U, phost->device.address,
+                            phost->device.speed, USBH_EP_CONTROL,
+                            (uint16_t)phost->Control.pipe_size);
+
+        /* Open Control pipes */
+        (void)USBH_OpenPipe(phost, phost->Control.pipe_out, 0x00U, phost->device.address,
+                            phost->device.speed, USBH_EP_CONTROL,
+                            (uint16_t)phost->Control.pipe_size);
+      }
+      else if (ReqStatus == USBH_NOT_SUPPORTED)
+      {
+        USBH_ErrLog("Control error: Get Device Descriptor request failed");
+        phost->device.EnumCnt++;
+        if (phost->device.EnumCnt > 3U)
+        {
+          /* Buggy Device can't complete get device desc request */
+          USBH_UsrLog("Control error, Device not Responding Please unplug the Device.");
+          phost->gState = HOST_ABORT_STATE;
+        }
+        else
+        {
+          /* free control pipes */
+          (void)USBH_FreePipe(phost, phost->Control.pipe_out);
+          (void)USBH_FreePipe(phost, phost->Control.pipe_in);
+
+          /* Reset the USB Device */
+          phost->gState = HOST_IDLE;
+        }
+      }
+      else
+      {
+        /* .. */
+      }
+      break;
+
+    case ENUM_GET_FULL_DEV_DESC:
+      /* Get FULL Device Desc  */
+      ReqStatus = USBH_Get_DevDesc(phost, USB_DEVICE_DESC_SIZE);
+      if (ReqStatus == USBH_OK)
+      {
+        USBH_UsrLog("PID: %xh", phost->device.DevDesc.idProduct);
+        USBH_UsrLog("VID: %xh", phost->device.DevDesc.idVendor);
+
+        phost->EnumState = ENUM_SET_ADDR;
+      }
+      else if (ReqStatus == USBH_NOT_SUPPORTED)
+      {
+        USBH_ErrLog("Control error: Get Full Device Descriptor request failed");
+        phost->device.EnumCnt++;
+        if (phost->device.EnumCnt > 3U)
+        {
+          /* Buggy Device can't complete get device desc request */
+          USBH_UsrLog("Control error, Device not Responding Please unplug the Device.");
+          phost->gState = HOST_ABORT_STATE;
+        }
+        else
+        {
+          /* Free control pipes */
+          (void)USBH_FreePipe(phost, phost->Control.pipe_out);
+          (void)USBH_FreePipe(phost, phost->Control.pipe_in);
+
+          /* Reset the USB Device */
+          phost->EnumState = ENUM_IDLE;
+          phost->gState = HOST_IDLE;
+        }
+      }
+      else
+      {
+        /* .. */
+      }
+      break;
+
+    case ENUM_SET_ADDR:
+      /* set address */
+      ReqStatus = USBH_SetAddress(phost, USBH_DEVICE_ADDRESS);
+      if (ReqStatus == USBH_OK)
+      {
+        USBH_Delay(2U);
+        phost->device.address = USBH_DEVICE_ADDRESS;
+
+        /* user callback for device address assigned */
+        USBH_UsrLog("Address (#%d) assigned.", phost->device.address);
+        phost->EnumState = ENUM_GET_CFG_DESC;
+
+        /* modify control channels to update device address */
+        (void)USBH_OpenPipe(phost, phost->Control.pipe_in, 0x80U,  phost->device.address,
+                            phost->device.speed, USBH_EP_CONTROL,
+                            (uint16_t)phost->Control.pipe_size);
+
+        /* Open Control pipes */
+        (void)USBH_OpenPipe(phost, phost->Control.pipe_out, 0x00U, phost->device.address,
+                            phost->device.speed, USBH_EP_CONTROL,
+                            (uint16_t)phost->Control.pipe_size);
+      }
+      else if (ReqStatus == USBH_NOT_SUPPORTED)
+      {
+        USBH_ErrLog("Control error: Device Set Address request failed");
+
+        /* Buggy Device can't complete get device desc request */
+        USBH_UsrLog("Control error, Device not Responding Please unplug the Device.");
+        phost->gState = HOST_ABORT_STATE;
+        phost->EnumState = ENUM_IDLE;
+      }
+      else
+      {
+        /* .. */
+      }
+      break;
+
+    case ENUM_GET_CFG_DESC:
+      /* get standard configuration descriptor */
+      ReqStatus = USBH_Get_CfgDesc(phost, USB_CONFIGURATION_DESC_SIZE);
+      if (ReqStatus == USBH_OK)
+      {
+        phost->EnumState = ENUM_GET_FULL_CFG_DESC;
+      }
+      else if (ReqStatus == USBH_NOT_SUPPORTED)
+      {
+        USBH_ErrLog("Control error: Get Device configuration descriptor request failed");
+        phost->device.EnumCnt++;
+        if (phost->device.EnumCnt > 3U)
+        {
+          /* Buggy Device can't complete get device desc request */
+          USBH_UsrLog("Control error, Device not Responding Please unplug the Device.");
+          phost->gState = HOST_ABORT_STATE;
+        }
+        else
+        {
+          /* Free control pipes */
+          (void)USBH_FreePipe(phost, phost->Control.pipe_out);
+          (void)USBH_FreePipe(phost, phost->Control.pipe_in);
+
+          /* Reset the USB Device */
+          phost->EnumState = ENUM_IDLE;
+          phost->gState = HOST_IDLE;
+        }
+      }
+      else
+      {
+        /* .. */
+      }
+      break;
+
+    case ENUM_GET_FULL_CFG_DESC:
+      /* get FULL config descriptor (config, interface, endpoints) */
+      ReqStatus = USBH_Get_CfgDesc(phost, phost->device.CfgDesc.wTotalLength);
+      if (ReqStatus == USBH_OK)
+      {
+        phost->EnumState = ENUM_GET_MFC_STRING_DESC;
+      }
+      else if (ReqStatus == USBH_NOT_SUPPORTED)
+      {
+        USBH_ErrLog("Control error: Get Device configuration descriptor request failed");
+        phost->device.EnumCnt++;
+        if (phost->device.EnumCnt > 3U)
+        {
+          /* Buggy Device can't complete get device desc request */
+          USBH_UsrLog("Control error, Device not Responding Please unplug the Device.");
+          phost->gState = HOST_ABORT_STATE;
+        }
+        else
+        {
+          /* Free control pipes */
+          (void)USBH_FreePipe(phost, phost->Control.pipe_out);
+          (void)USBH_FreePipe(phost, phost->Control.pipe_in);
+
+          /* Reset the USB Device */
+          phost->EnumState = ENUM_IDLE;
+          phost->gState = HOST_IDLE;
+        }
+      }
+      else
+      {
+        /* .. */
+      }
+      break;
+
+    case ENUM_GET_MFC_STRING_DESC:
+      if (phost->device.DevDesc.iManufacturer != 0U)
+      {
+        /* Check that Manufacturer String is available */
+        ReqStatus = USBH_Get_StringDesc(phost, phost->device.DevDesc.iManufacturer,
+                                        phost->device.Data, 0xFFU);
+        if (ReqStatus == USBH_OK)
+        {
+          /* User callback for Manufacturing string */
+          USBH_UsrLog("Manufacturer : %s", (char *)(void *)phost->device.Data);
+          phost->EnumState = ENUM_GET_PRODUCT_STRING_DESC;
+
+#if (USBH_USE_OS == 1U)
+          phost->os_msg = (uint32_t)USBH_STATE_CHANGED_EVENT;
+#if (osCMSIS < 0x20000U)
+          (void)osMessagePut(phost->os_event, phost->os_msg, 0U);
+#else
+          (void)osMessageQueuePut(phost->os_event, &phost->os_msg, 0U, 0U);
+#endif
+#endif
+        }
+        else if (ReqStatus == USBH_NOT_SUPPORTED)
+        {
+          USBH_UsrLog("Manufacturer : N/A");
+          phost->EnumState = ENUM_GET_PRODUCT_STRING_DESC;
+
+#if (USBH_USE_OS == 1U)
+          phost->os_msg = (uint32_t)USBH_STATE_CHANGED_EVENT;
+#if (osCMSIS < 0x20000U)
+          (void)osMessagePut(phost->os_event, phost->os_msg, 0U);
+#else
+          (void)osMessageQueuePut(phost->os_event, &phost->os_msg, 0U, 0U);
+#endif
+#endif
+        }
+        else
+        {
+          /* .. */
+        }
+      }
+      else
+      {
+        USBH_UsrLog("Manufacturer : N/A");
+        phost->EnumState = ENUM_GET_PRODUCT_STRING_DESC;
+
+#if (USBH_USE_OS == 1U)
+        phost->os_msg = (uint32_t)USBH_STATE_CHANGED_EVENT;
+#if (osCMSIS < 0x20000U)
+        (void)osMessagePut(phost->os_event, phost->os_msg, 0U);
+#else
+        (void)osMessageQueuePut(phost->os_event, &phost->os_msg, 0U, 0U);
+#endif
+#endif
+      }
+      break;
+
+    case ENUM_GET_PRODUCT_STRING_DESC:
+      if (phost->device.DevDesc.iProduct != 0U)
+      {
+        /* Check that Product string is available */
+        ReqStatus = USBH_Get_StringDesc(phost, phost->device.DevDesc.iProduct,
+                                        phost->device.Data, 0xFFU);
+        if (ReqStatus == USBH_OK)
+        {
+          /* User callback for Product string */
+          USBH_UsrLog("Product : %s", (char *)(void *)phost->device.Data);
+          phost->EnumState = ENUM_GET_SERIALNUM_STRING_DESC;
+        }
+        else if (ReqStatus == USBH_NOT_SUPPORTED)
+        {
+          USBH_UsrLog("Product : N/A");
+          phost->EnumState = ENUM_GET_SERIALNUM_STRING_DESC;
+
+#if (USBH_USE_OS == 1U)
+          phost->os_msg = (uint32_t)USBH_STATE_CHANGED_EVENT;
+#if (osCMSIS < 0x20000U)
+          (void)osMessagePut(phost->os_event, phost->os_msg, 0U);
+#else
+          (void)osMessageQueuePut(phost->os_event, &phost->os_msg, 0U, 0U);
+#endif
+#endif
+        }
+        else
+        {
+          /* .. */
+        }
+      }
+      else
+      {
+        USBH_UsrLog("Product : N/A");
+        phost->EnumState = ENUM_GET_SERIALNUM_STRING_DESC;
+
+#if (USBH_USE_OS == 1U)
+        phost->os_msg = (uint32_t)USBH_STATE_CHANGED_EVENT;
+#if (osCMSIS < 0x20000U)
+        (void)osMessagePut(phost->os_event, phost->os_msg, 0U);
+#else
+        (void)osMessageQueuePut(phost->os_event, &phost->os_msg, 0U, 0U);
+#endif
+#endif
+      }
+      break;
+
+    case ENUM_GET_SERIALNUM_STRING_DESC:
+      if (phost->device.DevDesc.iSerialNumber != 0U)
+      {
+        /* Check that Serial number string is available */
+        ReqStatus = USBH_Get_StringDesc(phost, phost->device.DevDesc.iSerialNumber,
+                                        phost->device.Data, 0xFFU);
+        if (ReqStatus == USBH_OK)
+        {
+          /* User callback for Serial number string */
+          USBH_UsrLog("Serial Number : %s", (char *)(void *)phost->device.Data);
+          Status = USBH_OK;
+        }
+        else if (ReqStatus == USBH_NOT_SUPPORTED)
+        {
+          USBH_UsrLog("Serial Number : N/A");
+          Status = USBH_OK;
+        }
+        else
+        {
+          /* .. */
+        }
+      }
+      else
+      {
+        USBH_UsrLog("Serial Number : N/A");
+        Status = USBH_OK;
+      }
+      break;
+
+    default:
+      break;
+  }
+  return Status;
+}
+
+
+/**
+  * @brief  USBH_LL_SetTimer
+  *         Set the initial Host Timer tick
+  * @param  phost: Host Handle
+  * @retval None
+  */
+void  USBH_LL_SetTimer(USBH_HandleTypeDef *phost, uint32_t time)
+{
+  phost->Timer = time;
+}
+
+
+/**
+  * @brief  USBH_LL_IncTimer
+  *         Increment Host Timer tick
+  * @param  phost: Host Handle
+  * @retval None
+  */
+void  USBH_LL_IncTimer(USBH_HandleTypeDef *phost)
+{
+  phost->Timer++;
+  USBH_HandleSof(phost);
+}
+
+
+/**
+  * @brief  USBH_HandleSof
+  *         Call SOF process
+  * @param  phost: Host Handle
+  * @retval None
+  */
+static void  USBH_HandleSof(USBH_HandleTypeDef *phost)
+{
+  if ((phost->gState == HOST_CLASS) && (phost->pActiveClass != NULL))
+  {
+    phost->pActiveClass->SOFProcess(phost);
+  }
+}
+
+
+/**
+  * @brief  USBH_PortEnabled
+  *         Port Enabled
+  * @param  phost: Host Handle
+  * @retval None
+  */
+void USBH_LL_PortEnabled(USBH_HandleTypeDef *phost)
+{
+  phost->device.PortEnabled = 1U;
+
+#if (USBH_USE_OS == 1U)
+  phost->os_msg = (uint32_t)USBH_PORT_EVENT;
+#if (osCMSIS < 0x20000U)
+  (void)osMessagePut(phost->os_event, phost->os_msg, 0U);
+#else
+  (void)osMessageQueuePut(phost->os_event, &phost->os_msg, 0U, 0U);
+#endif
+#endif
+
+  return;
+}
+
+
+/**
+  * @brief  USBH_LL_PortDisabled
+  *         Port Disabled
+  * @param  phost: Host Handle
+  * @retval None
+  */
+void USBH_LL_PortDisabled(USBH_HandleTypeDef *phost)
+{
+  phost->device.PortEnabled = 0U;
+
+  return;
+}
+
+
+/**
+  * @brief  HCD_IsPortEnabled
+  *         Is Port Enabled
+  * @param  phost: Host Handle
+  * @retval None
+  */
+uint8_t USBH_IsPortEnabled(USBH_HandleTypeDef *phost)
+{
+  return (phost->device.PortEnabled);
+}
+
+
+/**
+  * @brief  USBH_LL_Connect
+  *         Handle USB Host connexion event
+  * @param  phost: Host Handle
+  * @retval USBH_Status
+  */
+USBH_StatusTypeDef  USBH_LL_Connect(USBH_HandleTypeDef *phost)
+{
+  phost->device.is_connected = 1U;
+  phost->device.is_disconnected = 0U;
+  phost->device.is_ReEnumerated = 0U;
+
+
+#if (USBH_USE_OS == 1U)
+  phost->os_msg = (uint32_t)USBH_PORT_EVENT;
+#if (osCMSIS < 0x20000U)
+  (void)osMessagePut(phost->os_event, phost->os_msg, 0U);
+#else
+  (void)osMessageQueuePut(phost->os_event, &phost->os_msg, 0U, 0U);
+#endif
+#endif
+
+  return USBH_OK;
+}
+
+
+/**
+  * @brief  USBH_LL_Disconnect
+  *         Handle USB Host disconnection event
+  * @param  phost: Host Handle
+  * @retval USBH_Status
+  */
+USBH_StatusTypeDef  USBH_LL_Disconnect(USBH_HandleTypeDef *phost)
+{
+  /* update device connection states */
+  phost->device.is_disconnected = 1U;
+  phost->device.is_connected = 0U;
+  phost->device.PortEnabled = 0U;
+
+  /* Stop Host */
+  (void)USBH_LL_Stop(phost);
+
+  /* FRee Control Pipes */
+  (void)USBH_FreePipe(phost, phost->Control.pipe_in);
+  (void)USBH_FreePipe(phost, phost->Control.pipe_out);
+#if (USBH_USE_OS == 1U)
+  phost->os_msg = (uint32_t)USBH_PORT_EVENT;
+#if (osCMSIS < 0x20000U)
+  (void)osMessagePut(phost->os_event, phost->os_msg, 0U);
+#else
+  (void)osMessageQueuePut(phost->os_event, &phost->os_msg, 0U, 0U);
+#endif
+#endif
+
+  return USBH_OK;
+}
+
+
+#if (USBH_USE_OS == 1U)
+/**
+  * @brief  USB Host Thread task
+  * @param  pvParameters not used
+  * @retval None
+  */
+
+#if (osCMSIS < 0x20000U)
+static void USBH_Process_OS(void const *argument)
+{
+  osEvent event;
+
+  for (;;)
+  {
+    event = osMessageGet(((USBH_HandleTypeDef *)argument)->os_event, osWaitForever);
+    if (event.status == osEventMessage)
+    {
+      USBH_Process((USBH_HandleTypeDef *)argument);
+    }
+  }
+}
+#else
+static void USBH_Process_OS(void *argument)
+{
+  osStatus_t status;
+
+  for (;;)
+  {
+    status = osMessageQueueGet(((USBH_HandleTypeDef *)argument)->os_event,
+                               &((USBH_HandleTypeDef *)argument)->os_msg, NULL, osWaitForever);
+    if (status == osOK)
+    {
+      USBH_Process((USBH_HandleTypeDef *)argument);
+    }
+  }
+}
+#endif /* (osCMSIS < 0x20000U) */
+
+
+/**
+  * @brief  USBH_LL_NotifyURBChange
+  *         Notify URB state Change
+  * @param  phost: Host handle
+  * @retval USBH Status
+  */
+USBH_StatusTypeDef  USBH_LL_NotifyURBChange(USBH_HandleTypeDef *phost)
+{
+  phost->os_msg = (uint32_t)USBH_PORT_EVENT;
+
+#if (osCMSIS < 0x20000U)
+  (void)osMessagePut(phost->os_event, phost->os_msg, 0U);
+#else
+  (void)osMessageQueuePut(phost->os_event, &phost->os_msg, 0U, 0U);
+#endif
+
+  return USBH_OK;
+}
+#endif
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Middlewares/ST/STM32_USB_Host_Library/Core/Src/usbh_ctlreq.c b/Middlewares/ST/STM32_USB_Host_Library/Core/Src/usbh_ctlreq.c
new file mode 100644
index 0000000..3b75767
--- /dev/null
+++ b/Middlewares/ST/STM32_USB_Host_Library/Core/Src/usbh_ctlreq.c
@@ -0,0 +1,1140 @@
+/**
+  ******************************************************************************
+  * @file    usbh_ctlreq.c
+  * @author  MCD Application Team
+  * @brief   This file implements the control requests for device enumeration
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2015 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                      www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "usbh_ctlreq.h"
+
+/** @addtogroup USBH_LIB
+  * @{
+  */
+
+/** @addtogroup USBH_LIB_CORE
+  * @{
+  */
+
+/** @defgroup USBH_CTLREQ
+  * @brief This file implements the standard requests for device enumeration
+  * @{
+  */
+
+
+/** @defgroup USBH_CTLREQ_Private_Defines
+  * @{
+  */
+/**
+  * @}
+  */
+
+
+/** @defgroup USBH_CTLREQ_Private_TypesDefinitions
+  * @{
+  */
+/**
+  * @}
+  */
+
+
+
+/** @defgroup USBH_CTLREQ_Private_Macros
+  * @{
+  */
+/**
+  * @}
+  */
+
+
+/** @defgroup USBH_CTLREQ_Private_Variables
+  * @{
+  */
+/**
+  * @}
+  */
+
+/** @defgroup USBH_CTLREQ_Private_FunctionPrototypes
+  * @{
+  */
+static USBH_StatusTypeDef USBH_HandleControl(USBH_HandleTypeDef *phost);
+
+static void USBH_ParseDevDesc(USBH_DevDescTypeDef *dev_desc,
+                              uint8_t *buf, uint16_t length);
+
+static USBH_StatusTypeDef USBH_ParseCfgDesc(USBH_HandleTypeDef *phost,
+                                            uint8_t *buf, uint16_t length);
+
+static USBH_StatusTypeDef USBH_ParseEPDesc(USBH_HandleTypeDef *phost, USBH_EpDescTypeDef  *ep_descriptor, uint8_t *buf);
+static void USBH_ParseStringDesc(uint8_t *psrc, uint8_t *pdest, uint16_t length);
+static void USBH_ParseInterfaceDesc(USBH_InterfaceDescTypeDef  *if_descriptor, uint8_t *buf);
+
+
+/**
+  * @}
+  */
+
+
+/** @defgroup USBH_CTLREQ_Private_Functions
+  * @{
+  */
+
+
+/**
+  * @brief  USBH_Get_DevDesc
+  *         Issue Get Device Descriptor command to the device. Once the response
+  *         received, it parses the device descriptor and updates the status.
+  * @param  phost: Host Handle
+  * @param  length: Length of the descriptor
+  * @retval USBH Status
+  */
+USBH_StatusTypeDef USBH_Get_DevDesc(USBH_HandleTypeDef *phost, uint8_t length)
+{
+  USBH_StatusTypeDef status;
+
+  status = USBH_GetDescriptor(phost,
+                              USB_REQ_RECIPIENT_DEVICE | USB_REQ_TYPE_STANDARD,
+                              USB_DESC_DEVICE, phost->device.Data,
+                              (uint16_t)length);
+
+  if (status == USBH_OK)
+  {
+    /* Commands successfully sent and Response Received */
+    USBH_ParseDevDesc(&phost->device.DevDesc, phost->device.Data,
+                      (uint16_t)length);
+  }
+
+  return status;
+}
+
+
+/**
+  * @brief  USBH_Get_CfgDesc
+  *         Issues Configuration Descriptor to the device. Once the response
+  *         received, it parses the configuration descriptor and updates the
+  *         status.
+  * @param  phost: Host Handle
+  * @param  length: Length of the descriptor
+  * @retval USBH Status
+  */
+USBH_StatusTypeDef USBH_Get_CfgDesc(USBH_HandleTypeDef *phost,
+                                    uint16_t length)
+
+{
+  USBH_StatusTypeDef status;
+  uint8_t *pData = phost->device.CfgDesc_Raw;
+
+  status = USBH_GetDescriptor(phost, (USB_REQ_RECIPIENT_DEVICE | USB_REQ_TYPE_STANDARD),
+                              USB_DESC_CONFIGURATION, pData, length);
+
+  if (status == USBH_OK)
+  {
+    /* Commands successfully sent and Response Received  */
+    status = USBH_ParseCfgDesc(phost, pData, length);
+  }
+
+  return status;
+}
+
+
+/**
+  * @brief  USBH_Get_StringDesc
+  *         Issues string Descriptor command to the device. Once the response
+  *         received, it parses the string descriptor and updates the status.
+  * @param  phost: Host Handle
+  * @param  string_index: String index for the descriptor
+  * @param  buff: Buffer address for the descriptor
+  * @param  length: Length of the descriptor
+  * @retval USBH Status
+  */
+USBH_StatusTypeDef USBH_Get_StringDesc(USBH_HandleTypeDef *phost,
+                                       uint8_t string_index, uint8_t *buff,
+                                       uint16_t length)
+{
+  USBH_StatusTypeDef status;
+
+  status = USBH_GetDescriptor(phost,
+                              USB_REQ_RECIPIENT_DEVICE | USB_REQ_TYPE_STANDARD,
+                              USB_DESC_STRING | string_index,
+                              phost->device.Data, length);
+
+  if (status == USBH_OK)
+  {
+    /* Commands successfully sent and Response Received  */
+    USBH_ParseStringDesc(phost->device.Data, buff, length);
+  }
+
+  return status;
+}
+
+
+/**
+  * @brief  USBH_GetDescriptor
+  *         Issues Descriptor command to the device. Once the response received,
+  *         it parses the descriptor and updates the status.
+  * @param  phost: Host Handle
+  * @param  req_type: Descriptor type
+  * @param  value_idx: Value for the GetDescriptr request
+  * @param  buff: Buffer to store the descriptor
+  * @param  length: Length of the descriptor
+  * @retval USBH Status
+  */
+USBH_StatusTypeDef USBH_GetDescriptor(USBH_HandleTypeDef *phost,
+                                      uint8_t  req_type,
+                                      uint16_t value_idx,
+                                      uint8_t *buff,
+                                      uint16_t length)
+{
+  if (phost->RequestState == CMD_SEND)
+  {
+    phost->Control.setup.b.bmRequestType = USB_D2H | req_type;
+    phost->Control.setup.b.bRequest = USB_REQ_GET_DESCRIPTOR;
+    phost->Control.setup.b.wValue.w = value_idx;
+
+    if ((value_idx & 0xff00U) == USB_DESC_STRING)
+    {
+      phost->Control.setup.b.wIndex.w = 0x0409U;
+    }
+    else
+    {
+      phost->Control.setup.b.wIndex.w = 0U;
+    }
+    phost->Control.setup.b.wLength.w = length;
+  }
+
+  return USBH_CtlReq(phost, buff, length);
+}
+
+
+/**
+  * @brief  USBH_SetAddress
+  *         This command sets the address to the connected device
+  * @param  phost: Host Handle
+  * @param  DeviceAddress: Device address to assign
+  * @retval USBH Status
+  */
+USBH_StatusTypeDef USBH_SetAddress(USBH_HandleTypeDef *phost,
+                                   uint8_t DeviceAddress)
+{
+  if (phost->RequestState == CMD_SEND)
+  {
+    phost->Control.setup.b.bmRequestType = USB_H2D | USB_REQ_RECIPIENT_DEVICE | \
+                                           USB_REQ_TYPE_STANDARD;
+
+    phost->Control.setup.b.bRequest = USB_REQ_SET_ADDRESS;
+
+    phost->Control.setup.b.wValue.w = (uint16_t)DeviceAddress;
+    phost->Control.setup.b.wIndex.w = 0U;
+    phost->Control.setup.b.wLength.w = 0U;
+  }
+
+  return USBH_CtlReq(phost, NULL, 0U);
+}
+
+
+/**
+  * @brief  USBH_SetCfg
+  *         The command sets the configuration value to the connected device
+  * @param  phost: Host Handle
+  * @param  cfg_idx: Configuration value
+  * @retval USBH Status
+  */
+USBH_StatusTypeDef USBH_SetCfg(USBH_HandleTypeDef *phost, uint16_t cfg_idx)
+{
+  if (phost->RequestState == CMD_SEND)
+  {
+    phost->Control.setup.b.bmRequestType = USB_H2D | USB_REQ_RECIPIENT_DEVICE
+                                           | USB_REQ_TYPE_STANDARD;
+
+    phost->Control.setup.b.bRequest = USB_REQ_SET_CONFIGURATION;
+    phost->Control.setup.b.wValue.w = cfg_idx;
+    phost->Control.setup.b.wIndex.w = 0U;
+    phost->Control.setup.b.wLength.w = 0U;
+  }
+
+  return USBH_CtlReq(phost, NULL, 0U);
+}
+
+
+/**
+  * @brief  USBH_SetInterface
+  *         The command sets the Interface value to the connected device
+  * @param  phost: Host Handle
+  * @param  altSetting: Interface value
+  * @retval USBH Status
+  */
+USBH_StatusTypeDef USBH_SetInterface(USBH_HandleTypeDef *phost, uint8_t ep_num,
+                                     uint8_t altSetting)
+{
+  if (phost->RequestState == CMD_SEND)
+  {
+    phost->Control.setup.b.bmRequestType = USB_H2D | USB_REQ_RECIPIENT_INTERFACE
+                                           | USB_REQ_TYPE_STANDARD;
+
+    phost->Control.setup.b.bRequest = USB_REQ_SET_INTERFACE;
+    phost->Control.setup.b.wValue.w = altSetting;
+    phost->Control.setup.b.wIndex.w = ep_num;
+    phost->Control.setup.b.wLength.w = 0U;
+  }
+
+  return USBH_CtlReq(phost, NULL, 0U);
+}
+
+
+/**
+  * @brief  USBH_SetFeature
+  *         The command sets the device features (remote wakeup feature,..)
+  * @param  pdev: Selected device
+  * @param  itf_idx
+  * @retval Status
+  */
+USBH_StatusTypeDef USBH_SetFeature(USBH_HandleTypeDef *phost, uint8_t wValue)
+{
+  if (phost->RequestState == CMD_SEND)
+  {
+    phost->Control.setup.b.bmRequestType = USB_H2D | USB_REQ_RECIPIENT_DEVICE
+                                           | USB_REQ_TYPE_STANDARD;
+
+    phost->Control.setup.b.bRequest = USB_REQ_SET_FEATURE;
+    phost->Control.setup.b.wValue.w = wValue;
+    phost->Control.setup.b.wIndex.w = 0U;
+    phost->Control.setup.b.wLength.w = 0U;
+  }
+
+  return USBH_CtlReq(phost, NULL, 0U);
+}
+
+
+/**
+  * @brief  USBH_ClrFeature
+  *         This request is used to clear or disable a specific feature.
+  * @param  phost: Host Handle
+  * @param  ep_num: endpoint number
+  * @param  hc_num: Host channel number
+  * @retval USBH Status
+  */
+USBH_StatusTypeDef USBH_ClrFeature(USBH_HandleTypeDef *phost, uint8_t ep_num)
+{
+  if (phost->RequestState == CMD_SEND)
+  {
+    phost->Control.setup.b.bmRequestType = USB_H2D | USB_REQ_RECIPIENT_ENDPOINT
+                                           | USB_REQ_TYPE_STANDARD;
+
+    phost->Control.setup.b.bRequest = USB_REQ_CLEAR_FEATURE;
+    phost->Control.setup.b.wValue.w = FEATURE_SELECTOR_ENDPOINT;
+    phost->Control.setup.b.wIndex.w = ep_num;
+    phost->Control.setup.b.wLength.w = 0U;
+  }
+  return USBH_CtlReq(phost, NULL, 0U);
+}
+
+
+/**
+  * @brief  USBH_ParseDevDesc
+  *         This function Parses the device descriptor
+  * @param  dev_desc: device_descriptor destination address
+  * @param  buf: Buffer where the source descriptor is available
+  * @param  length: Length of the descriptor
+  * @retval None
+  */
+static void  USBH_ParseDevDesc(USBH_DevDescTypeDef *dev_desc, uint8_t *buf,
+                               uint16_t length)
+{
+  dev_desc->bLength            = *(uint8_t *)(buf +  0);
+  dev_desc->bDescriptorType    = *(uint8_t *)(buf +  1);
+  dev_desc->bcdUSB             = LE16(buf +  2);
+  dev_desc->bDeviceClass       = *(uint8_t *)(buf +  4);
+  dev_desc->bDeviceSubClass    = *(uint8_t *)(buf +  5);
+  dev_desc->bDeviceProtocol    = *(uint8_t *)(buf +  6);
+  dev_desc->bMaxPacketSize     = *(uint8_t *)(buf +  7);
+
+  /* Make sure that the max packet size is either 8, 16, 32, 64 or force it to 64 */
+  switch (dev_desc->bMaxPacketSize)
+  {
+    case 8:
+    case 16:
+    case 32:
+    case 64:
+      dev_desc->bMaxPacketSize = dev_desc->bMaxPacketSize;
+      break;
+
+    default:
+      /*set the size to 64 in case the device has answered with incorrect size */
+      dev_desc->bMaxPacketSize = 64U;
+      break;
+  }
+
+  if (length > 8U)
+  {
+    /* For 1st time after device connection, Host may issue only 8 bytes for
+    Device Descriptor Length  */
+    dev_desc->idVendor           = LE16(buf +  8);
+    dev_desc->idProduct          = LE16(buf + 10);
+    dev_desc->bcdDevice          = LE16(buf + 12);
+    dev_desc->iManufacturer      = *(uint8_t *)(buf + 14);
+    dev_desc->iProduct           = *(uint8_t *)(buf + 15);
+    dev_desc->iSerialNumber      = *(uint8_t *)(buf + 16);
+    dev_desc->bNumConfigurations = *(uint8_t *)(buf + 17);
+  }
+}
+
+
+/**
+  * @brief  USBH_ParseCfgDesc
+  *         This function Parses the configuration descriptor
+  * @param  phost: USB Host handler
+  * @param  buf: Buffer where the source descriptor is available
+  * @param  length: Length of the descriptor
+  * @retval USBH statuse
+  */
+static USBH_StatusTypeDef USBH_ParseCfgDesc(USBH_HandleTypeDef *phost, uint8_t *buf, uint16_t length)
+{
+  USBH_CfgDescTypeDef *cfg_desc = &phost->device.CfgDesc;
+  USBH_StatusTypeDef           status = USBH_OK;
+  USBH_InterfaceDescTypeDef    *pif ;
+  USBH_EpDescTypeDef           *pep;
+  USBH_DescHeader_t            *pdesc = (USBH_DescHeader_t *)(void *)buf;
+  uint16_t                     ptr;
+  uint8_t                      if_ix = 0U;
+  uint8_t                      ep_ix = 0U;
+
+  pdesc   = (USBH_DescHeader_t *)(void *)buf;
+
+  /* Parse configuration descriptor */
+  cfg_desc->bLength             = *(uint8_t *)(buf + 0);
+  cfg_desc->bDescriptorType     = *(uint8_t *)(buf + 1);
+  cfg_desc->wTotalLength        = MIN(((uint16_t) LE16(buf + 2)), ((uint16_t)USBH_MAX_SIZE_CONFIGURATION));
+  cfg_desc->bNumInterfaces      = *(uint8_t *)(buf + 4);
+  cfg_desc->bConfigurationValue = *(uint8_t *)(buf + 5);
+  cfg_desc->iConfiguration      = *(uint8_t *)(buf + 6);
+  cfg_desc->bmAttributes        = *(uint8_t *)(buf + 7);
+  cfg_desc->bMaxPower           = *(uint8_t *)(buf + 8);
+
+  /* Make sure that the Confguration descriptor's bLength is equal to USB_CONFIGURATION_DESC_SIZE */
+  if (cfg_desc->bLength  != USB_CONFIGURATION_DESC_SIZE)
+  {
+    cfg_desc->bLength = USB_CONFIGURATION_DESC_SIZE;
+  }
+
+  if (length > USB_CONFIGURATION_DESC_SIZE)
+  {
+    ptr = USB_LEN_CFG_DESC;
+    pif = (USBH_InterfaceDescTypeDef *)NULL;
+
+    while ((if_ix < USBH_MAX_NUM_INTERFACES) && (ptr < cfg_desc->wTotalLength))
+    {
+      pdesc = USBH_GetNextDesc((uint8_t *)(void *)pdesc, &ptr);
+      if (pdesc->bDescriptorType == USB_DESC_TYPE_INTERFACE)
+      {
+        /* Make sure that the interface descriptor's bLength is equal to USB_INTERFACE_DESC_SIZE */
+        if (pdesc->bLength != USB_INTERFACE_DESC_SIZE)
+        {
+          pdesc->bLength = USB_INTERFACE_DESC_SIZE;
+        }
+
+        pif = &cfg_desc->Itf_Desc[if_ix];
+        USBH_ParseInterfaceDesc(pif, (uint8_t *)(void *)pdesc);
+
+        ep_ix = 0U;
+        pep = (USBH_EpDescTypeDef *)NULL;
+
+        while ((ep_ix < pif->bNumEndpoints) && (ptr < cfg_desc->wTotalLength))
+        {
+          pdesc = USBH_GetNextDesc((uint8_t *)(void *)pdesc, &ptr);
+
+          if (pdesc->bDescriptorType == USB_DESC_TYPE_ENDPOINT)
+          {
+            /* Check if the endpoint is appartening to an audio streaming interface */
+            if ((pif->bInterfaceClass == 0x01U) && (pif->bInterfaceSubClass == 0x02U))
+            {
+              /* Check if it is supporting the USB AUDIO 01 class specification */
+              if ((pif->bInterfaceProtocol == 0x00U) && (pdesc->bLength != 0x09U))
+              {
+                pdesc->bLength = 0x09U;
+              }
+            }
+            /* Make sure that the endpoint descriptor's bLength is equal to
+               USB_ENDPOINT_DESC_SIZE for all other endpoints types */
+            else if (pdesc->bLength != USB_ENDPOINT_DESC_SIZE)
+            {
+              pdesc->bLength = USB_ENDPOINT_DESC_SIZE;
+            }
+            else
+            {
+              /* ... */
+            }
+
+            pep = &cfg_desc->Itf_Desc[if_ix].Ep_Desc[ep_ix];
+
+            status = USBH_ParseEPDesc(phost, pep, (uint8_t *)(void *)pdesc);
+
+            ep_ix++;
+          }
+        }
+
+        /* Check if the required endpoint(s) data are parsed */
+        if (ep_ix < pif->bNumEndpoints)
+        {
+          return USBH_NOT_SUPPORTED;
+        }
+
+        if_ix++;
+      }
+    }
+
+    /* Check if the required interface(s) data are parsed */
+    if (if_ix < MIN(cfg_desc->bNumInterfaces, (uint8_t)USBH_MAX_NUM_INTERFACES))
+    {
+      return USBH_NOT_SUPPORTED;
+    }
+  }
+
+  return status;
+}
+
+
+/**
+  * @brief  USBH_ParseInterfaceDesc
+  *         This function Parses the interface descriptor
+  * @param  if_descriptor : Interface descriptor destination
+  * @param  buf: Buffer where the descriptor data is available
+  * @retval None
+  */
+static void  USBH_ParseInterfaceDesc(USBH_InterfaceDescTypeDef *if_descriptor,
+                                     uint8_t *buf)
+{
+  if_descriptor->bLength            = *(uint8_t *)(buf + 0);
+  if_descriptor->bDescriptorType    = *(uint8_t *)(buf + 1);
+  if_descriptor->bInterfaceNumber   = *(uint8_t *)(buf + 2);
+  if_descriptor->bAlternateSetting  = *(uint8_t *)(buf + 3);
+  if_descriptor->bNumEndpoints      = *(uint8_t *)(buf + 4);
+  if_descriptor->bInterfaceClass    = *(uint8_t *)(buf + 5);
+  if_descriptor->bInterfaceSubClass = *(uint8_t *)(buf + 6);
+  if_descriptor->bInterfaceProtocol = *(uint8_t *)(buf + 7);
+  if_descriptor->iInterface         = *(uint8_t *)(buf + 8);
+}
+
+
+/**
+  * @brief  USBH_ParseEPDesc
+  *         This function Parses the endpoint descriptor
+  * @param  phost: USB Host handler
+  * @param  ep_descriptor: Endpoint descriptor destination address
+  * @param  buf: Buffer where the parsed descriptor stored
+  * @retval USBH Status
+  */
+static USBH_StatusTypeDef  USBH_ParseEPDesc(USBH_HandleTypeDef *phost, USBH_EpDescTypeDef  *ep_descriptor,
+                                            uint8_t *buf)
+{
+  USBH_StatusTypeDef status = USBH_OK;
+  ep_descriptor->bLength          = *(uint8_t *)(buf + 0);
+  ep_descriptor->bDescriptorType  = *(uint8_t *)(buf + 1);
+  ep_descriptor->bEndpointAddress = *(uint8_t *)(buf + 2);
+  ep_descriptor->bmAttributes     = *(uint8_t *)(buf + 3);
+  ep_descriptor->wMaxPacketSize   = LE16(buf + 4);
+  ep_descriptor->bInterval        = *(uint8_t *)(buf + 6);
+
+  /* Make sure that wMaxPacketSize is different from 0 */
+  if (ep_descriptor->wMaxPacketSize == 0x00U)
+  {
+    status = USBH_NOT_SUPPORTED;
+  }
+  else if (USBH_MAX_EP_PACKET_SIZE < (uint16_t)USBH_MAX_DATA_BUFFER)
+  {
+    /* Make sure that maximum packet size (bits 0..10) does not exceed the max endpoint packet size */
+    ep_descriptor->wMaxPacketSize &= ~0x7FFU;
+    ep_descriptor->wMaxPacketSize |=  MIN((uint16_t)(LE16(buf + 4) & 0x7FFU), (uint16_t)USBH_MAX_EP_PACKET_SIZE);
+
+  }
+  else if ((uint16_t)USBH_MAX_DATA_BUFFER < USBH_MAX_EP_PACKET_SIZE)
+  {
+    /* Make sure that maximum packet size (bits 0..10) does not exceed the total buffer length */
+    ep_descriptor->wMaxPacketSize &= ~0x7FFU;
+    ep_descriptor->wMaxPacketSize |= MIN((uint16_t)(LE16(buf + 4) & 0x7FFU), (uint16_t)USBH_MAX_DATA_BUFFER);
+  }
+  else
+  {
+    /* ... */
+  }
+
+  /* For high-speed interrupt/isochronous endpoints, bInterval can vary from 1 to 16 */
+  if (phost->device.speed == (uint8_t)USBH_SPEED_HIGH)
+  {
+    if (((ep_descriptor->bmAttributes & EP_TYPE_MSK) == EP_TYPE_ISOC) ||
+        ((ep_descriptor->bmAttributes & EP_TYPE_MSK) == EP_TYPE_INTR))
+    {
+      if ((ep_descriptor->bInterval == 0U) || (ep_descriptor->bInterval > 0x10U))
+      {
+        status = USBH_NOT_SUPPORTED;
+      }
+    }
+  }
+  else
+  {
+    /* For full-speed isochronous endpoints, the value of bInterval must be in the range from 1 to 16.*/
+    if ((ep_descriptor->bmAttributes & EP_TYPE_MSK) == EP_TYPE_ISOC)
+    {
+      if ((ep_descriptor->bInterval == 0U) || (ep_descriptor->bInterval > 0x10U))
+      {
+        status = USBH_NOT_SUPPORTED;
+      }
+    }
+    /* For full-/low-speed interrupt endpoints, the value of bInterval may be from 1 to 255.*/
+    else if ((ep_descriptor->bmAttributes & EP_TYPE_MSK) == EP_TYPE_INTR)
+    {
+      if (ep_descriptor->bInterval == 0U)
+      {
+        status = USBH_NOT_SUPPORTED;
+      }
+    }
+    else
+    {
+      /* ... */
+    }
+  }
+
+  return status;
+}
+
+
+/**
+  * @brief  USBH_ParseStringDesc
+  *         This function Parses the string descriptor
+  * @param  psrc: Source pointer containing the descriptor data
+  * @param  pdest: Destination address pointer
+  * @param  length: Length of the descriptor
+  * @retval None
+  */
+static void USBH_ParseStringDesc(uint8_t *psrc, uint8_t *pdest, uint16_t length)
+{
+  uint16_t strlength;
+  uint16_t idx;
+
+  /* The UNICODE string descriptor is not NULL-terminated. The string length is
+  computed by subtracting two from the value of the first byte of the descriptor.
+  */
+
+  /* Check which is lower size, the Size of string or the length of bytes read
+  from the device */
+
+  if (psrc[1] == USB_DESC_TYPE_STRING)
+  {
+    /* Make sure the Descriptor is String Type */
+
+    /* psrc[0] contains Size of Descriptor, subtract 2 to get the length of string */
+    strlength = ((((uint16_t)psrc[0] - 2U) <= length) ? ((uint16_t)psrc[0] - 2U) : length);
+
+    /* Adjust the offset ignoring the String Len and Descriptor type */
+    psrc += 2U;
+
+    for (idx = 0U; idx < strlength; idx += 2U)
+    {
+      /* Copy Only the string and ignore the UNICODE ID, hence add the src */
+      *pdest =  psrc[idx];
+      pdest++;
+    }
+    *pdest = 0U; /* mark end of string */
+  }
+}
+
+
+/**
+  * @brief  USBH_GetNextDesc
+  *         This function return the next descriptor header
+  * @param  buf: Buffer where the cfg descriptor is available
+  * @param  ptr: data pointer inside the cfg descriptor
+  * @retval next header
+  */
+USBH_DescHeader_t  *USBH_GetNextDesc(uint8_t   *pbuf, uint16_t  *ptr)
+{
+  USBH_DescHeader_t  *pnext;
+
+  *ptr += ((USBH_DescHeader_t *)(void *)pbuf)->bLength;
+  pnext = (USBH_DescHeader_t *)(void *)((uint8_t *)(void *)pbuf + \
+                                        ((USBH_DescHeader_t *)(void *)pbuf)->bLength);
+
+  return (pnext);
+}
+
+
+/**
+  * @brief  USBH_CtlReq
+  *         USBH_CtlReq sends a control request and provide the status after
+  *            completion of the request
+  * @param  phost: Host Handle
+  * @param  req: Setup Request Structure
+  * @param  buff: data buffer address to store the response
+  * @param  length: length of the response
+  * @retval USBH Status
+  */
+USBH_StatusTypeDef USBH_CtlReq(USBH_HandleTypeDef *phost, uint8_t *buff,
+                               uint16_t length)
+{
+  USBH_StatusTypeDef status;
+  status = USBH_BUSY;
+
+  switch (phost->RequestState)
+  {
+    case CMD_SEND:
+      /* Start a SETUP transfer */
+      phost->Control.buff = buff;
+      phost->Control.length = length;
+      phost->Control.state = CTRL_SETUP;
+      phost->RequestState = CMD_WAIT;
+      status = USBH_BUSY;
+
+#if (USBH_USE_OS == 1U)
+      phost->os_msg = (uint32_t)USBH_CONTROL_EVENT;
+#if (osCMSIS < 0x20000U)
+      (void)osMessagePut(phost->os_event, phost->os_msg, 0U);
+#else
+      (void)osMessageQueuePut(phost->os_event, &phost->os_msg, 0U, 0U);
+#endif
+#endif
+      break;
+
+    case CMD_WAIT:
+      status = USBH_HandleControl(phost);
+      if ((status == USBH_OK) || (status == USBH_NOT_SUPPORTED))
+      {
+        /* Transaction completed, move control state to idle */
+        phost->RequestState = CMD_SEND;
+        phost->Control.state = CTRL_IDLE;
+      }
+      else if (status == USBH_FAIL)
+      {
+        /* Failure Mode */
+        phost->RequestState = CMD_SEND;
+      }
+      else
+      {
+        /* .. */
+      }
+#if (USBH_USE_OS == 1U)
+      phost->os_msg = (uint32_t)USBH_CONTROL_EVENT;
+#if (osCMSIS < 0x20000U)
+      (void)osMessagePut(phost->os_event, phost->os_msg, 0U);
+#else
+      (void)osMessageQueuePut(phost->os_event, &phost->os_msg, 0U, 0U);
+#endif
+#endif
+      break;
+
+    default:
+      break;
+  }
+  return status;
+}
+
+
+/**
+  * @brief  USBH_HandleControl
+  *         Handles the USB control transfer state machine
+  * @param  phost: Host Handle
+  * @retval USBH Status
+  */
+static USBH_StatusTypeDef USBH_HandleControl(USBH_HandleTypeDef *phost)
+{
+  uint8_t direction;
+  USBH_StatusTypeDef status = USBH_BUSY;
+  USBH_URBStateTypeDef URB_Status = USBH_URB_IDLE;
+
+  switch (phost->Control.state)
+  {
+    case CTRL_SETUP:
+      /* send a SETUP packet */
+      (void)USBH_CtlSendSetup(phost, (uint8_t *)(void *)phost->Control.setup.d8,
+                              phost->Control.pipe_out);
+
+      phost->Control.state = CTRL_SETUP_WAIT;
+      break;
+
+    case CTRL_SETUP_WAIT:
+
+      URB_Status = USBH_LL_GetURBState(phost, phost->Control.pipe_out);
+      /* case SETUP packet sent successfully */
+      if (URB_Status == USBH_URB_DONE)
+      {
+        direction = (phost->Control.setup.b.bmRequestType & USB_REQ_DIR_MASK);
+
+        /* check if there is a data stage */
+        if (phost->Control.setup.b.wLength.w != 0U)
+        {
+          if (direction == USB_D2H)
+          {
+            /* Data Direction is IN */
+            phost->Control.state = CTRL_DATA_IN;
+          }
+          else
+          {
+            /* Data Direction is OUT */
+            phost->Control.state = CTRL_DATA_OUT;
+          }
+        }
+        /* No DATA stage */
+        else
+        {
+          /* If there is No Data Transfer Stage */
+          if (direction == USB_D2H)
+          {
+            /* Data Direction is IN */
+            phost->Control.state = CTRL_STATUS_OUT;
+          }
+          else
+          {
+            /* Data Direction is OUT */
+            phost->Control.state = CTRL_STATUS_IN;
+          }
+        }
+
+#if (USBH_USE_OS == 1U)
+        phost->os_msg = (uint32_t)USBH_CONTROL_EVENT;
+#if (osCMSIS < 0x20000U)
+        (void)osMessagePut(phost->os_event, phost->os_msg, 0U);
+#else
+        (void)osMessageQueuePut(phost->os_event, &phost->os_msg, 0U, 0U);
+#endif
+#endif
+      }
+      else
+      {
+        if ((URB_Status == USBH_URB_ERROR) || (URB_Status == USBH_URB_NOTREADY))
+        {
+          phost->Control.state = CTRL_ERROR;
+
+#if (USBH_USE_OS == 1U)
+          phost->os_msg = (uint32_t)USBH_CONTROL_EVENT;
+#if (osCMSIS < 0x20000U)
+          (void)osMessagePut(phost->os_event, phost->os_msg, 0U);
+#else
+          (void)osMessageQueuePut(phost->os_event, &phost->os_msg, 0U, 0U);
+#endif
+#endif
+        }
+      }
+      break;
+
+    case CTRL_DATA_IN:
+      /* Issue an IN token */
+      phost->Control.timer = (uint16_t)phost->Timer;
+      (void)USBH_CtlReceiveData(phost, phost->Control.buff,
+                                phost->Control.length, phost->Control.pipe_in);
+
+      phost->Control.state = CTRL_DATA_IN_WAIT;
+      break;
+
+    case CTRL_DATA_IN_WAIT:
+
+      URB_Status = USBH_LL_GetURBState(phost, phost->Control.pipe_in);
+
+      /* check is DATA packet transferred successfully */
+      if (URB_Status == USBH_URB_DONE)
+      {
+        phost->Control.state = CTRL_STATUS_OUT;
+
+#if (USBH_USE_OS == 1U)
+        phost->os_msg = (uint32_t)USBH_CONTROL_EVENT;
+#if (osCMSIS < 0x20000U)
+        (void)osMessagePut(phost->os_event, phost->os_msg, 0U);
+#else
+        (void)osMessageQueuePut(phost->os_event, &phost->os_msg, 0U, 0U);
+#endif
+#endif
+      }
+
+      /* manage error cases*/
+      if (URB_Status == USBH_URB_STALL)
+      {
+        /* In stall case, return to previous machine state*/
+        status = USBH_NOT_SUPPORTED;
+
+#if (USBH_USE_OS == 1U)
+        phost->os_msg = (uint32_t)USBH_CONTROL_EVENT;
+#if (osCMSIS < 0x20000U)
+        (void)osMessagePut(phost->os_event, phost->os_msg, 0U);
+#else
+        (void)osMessageQueuePut(phost->os_event, &phost->os_msg, 0U, 0U);
+#endif
+#endif
+      }
+      else
+      {
+        if (URB_Status == USBH_URB_ERROR)
+        {
+          /* Device error */
+          phost->Control.state = CTRL_ERROR;
+
+#if (USBH_USE_OS == 1U)
+          phost->os_msg = (uint32_t)USBH_CONTROL_EVENT;
+#if (osCMSIS < 0x20000U)
+          (void)osMessagePut(phost->os_event, phost->os_msg, 0U);
+#else
+          (void)osMessageQueuePut(phost->os_event, &phost->os_msg, 0U, 0U);
+#endif
+#endif
+        }
+      }
+      break;
+
+    case CTRL_DATA_OUT:
+
+      (void)USBH_CtlSendData(phost, phost->Control.buff, phost->Control.length,
+                             phost->Control.pipe_out, 1U);
+
+      phost->Control.timer = (uint16_t)phost->Timer;
+      phost->Control.state = CTRL_DATA_OUT_WAIT;
+      break;
+
+    case CTRL_DATA_OUT_WAIT:
+
+      URB_Status = USBH_LL_GetURBState(phost, phost->Control.pipe_out);
+
+      if (URB_Status == USBH_URB_DONE)
+      {
+        /* If the Setup Pkt is sent successful, then change the state */
+        phost->Control.state = CTRL_STATUS_IN;
+
+#if (USBH_USE_OS == 1U)
+        phost->os_msg = (uint32_t)USBH_CONTROL_EVENT;
+#if (osCMSIS < 0x20000U)
+        (void)osMessagePut(phost->os_event, phost->os_msg, 0U);
+#else
+        (void)osMessageQueuePut(phost->os_event, &phost->os_msg, 0U, 0U);
+#endif
+#endif
+      }
+
+      /* handle error cases */
+      else if (URB_Status == USBH_URB_STALL)
+      {
+        /* In stall case, return to previous machine state*/
+        phost->Control.state = CTRL_STALLED;
+        status = USBH_NOT_SUPPORTED;
+
+#if (USBH_USE_OS == 1U)
+        phost->os_msg = (uint32_t)USBH_CONTROL_EVENT;
+#if (osCMSIS < 0x20000U)
+        (void)osMessagePut(phost->os_event, phost->os_msg, 0U);
+#else
+        (void)osMessageQueuePut(phost->os_event, &phost->os_msg, 0U, 0U);
+#endif
+#endif
+      }
+      else if (URB_Status == USBH_URB_NOTREADY)
+      {
+        /* Nack received from device */
+        phost->Control.state = CTRL_DATA_OUT;
+
+#if (USBH_USE_OS == 1U)
+        phost->os_msg = (uint32_t)USBH_CONTROL_EVENT;
+#if (osCMSIS < 0x20000U)
+        (void)osMessagePut(phost->os_event, phost->os_msg, 0U);
+#else
+        (void)osMessageQueuePut(phost->os_event, &phost->os_msg, 0U, 0U);
+#endif
+#endif
+      }
+      else
+      {
+        if (URB_Status == USBH_URB_ERROR)
+        {
+          /* device error */
+          phost->Control.state = CTRL_ERROR;
+          status = USBH_FAIL;
+
+#if (USBH_USE_OS == 1U)
+          phost->os_msg = (uint32_t)USBH_CONTROL_EVENT;
+#if (osCMSIS < 0x20000U)
+          (void)osMessagePut(phost->os_event, phost->os_msg, 0U);
+#else
+          (void)osMessageQueuePut(phost->os_event, &phost->os_msg, 0U, 0U);
+#endif
+#endif
+        }
+      }
+      break;
+
+    case CTRL_STATUS_IN:
+      /* Send 0 bytes out packet */
+      (void)USBH_CtlReceiveData(phost, NULL, 0U, phost->Control.pipe_in);
+
+      phost->Control.timer = (uint16_t)phost->Timer;
+      phost->Control.state = CTRL_STATUS_IN_WAIT;
+
+      break;
+
+    case CTRL_STATUS_IN_WAIT:
+
+      URB_Status = USBH_LL_GetURBState(phost, phost->Control.pipe_in);
+
+      if (URB_Status == USBH_URB_DONE)
+      {
+        /* Control transfers completed, Exit the State Machine */
+        phost->Control.state = CTRL_COMPLETE;
+        status = USBH_OK;
+
+#if (USBH_USE_OS == 1U)
+        phost->os_msg = (uint32_t)USBH_CONTROL_EVENT;
+#if (osCMSIS < 0x20000U)
+        (void)osMessagePut(phost->os_event, phost->os_msg, 0U);
+#else
+        (void)osMessageQueuePut(phost->os_event, &phost->os_msg, 0U, 0U);
+#endif
+#endif
+      }
+      else if (URB_Status == USBH_URB_ERROR)
+      {
+        phost->Control.state = CTRL_ERROR;
+
+#if (USBH_USE_OS == 1U)
+        phost->os_msg = (uint32_t)USBH_CONTROL_EVENT;
+#if (osCMSIS < 0x20000U)
+        (void)osMessagePut(phost->os_event, phost->os_msg, 0U);
+#else
+        (void)osMessageQueuePut(phost->os_event, &phost->os_msg, 0U, 0U);
+#endif
+#endif
+      }
+      else
+      {
+        if (URB_Status == USBH_URB_STALL)
+        {
+          /* Control transfers completed, Exit the State Machine */
+          status = USBH_NOT_SUPPORTED;
+
+#if (USBH_USE_OS == 1U)
+          phost->os_msg = (uint32_t)USBH_CONTROL_EVENT;
+#if (osCMSIS < 0x20000U)
+          (void)osMessagePut(phost->os_event, phost->os_msg, 0U);
+#else
+          (void)osMessageQueuePut(phost->os_event, &phost->os_msg, 0U, 0U);
+#endif
+#endif
+        }
+      }
+      break;
+
+    case CTRL_STATUS_OUT:
+      (void)USBH_CtlSendData(phost, NULL, 0U, phost->Control.pipe_out, 1U);
+
+      phost->Control.timer = (uint16_t)phost->Timer;
+      phost->Control.state = CTRL_STATUS_OUT_WAIT;
+      break;
+
+    case CTRL_STATUS_OUT_WAIT:
+      URB_Status = USBH_LL_GetURBState(phost, phost->Control.pipe_out);
+      if (URB_Status == USBH_URB_DONE)
+      {
+        status = USBH_OK;
+        phost->Control.state = CTRL_COMPLETE;
+
+#if (USBH_USE_OS == 1U)
+        phost->os_msg = (uint32_t)USBH_CONTROL_EVENT;
+#if (osCMSIS < 0x20000U)
+        (void)osMessagePut(phost->os_event, phost->os_msg, 0U);
+#else
+        (void)osMessageQueuePut(phost->os_event, &phost->os_msg, 0U, 0U);
+#endif
+#endif
+      }
+      else if (URB_Status == USBH_URB_NOTREADY)
+      {
+        phost->Control.state = CTRL_STATUS_OUT;
+
+#if (USBH_USE_OS == 1U)
+        phost->os_msg = (uint32_t)USBH_CONTROL_EVENT;
+#if (osCMSIS < 0x20000U)
+        (void)osMessagePut(phost->os_event, phost->os_msg, 0U);
+#else
+        (void)osMessageQueuePut(phost->os_event, &phost->os_msg, 0U, 0U);
+#endif
+#endif
+      }
+      else
+      {
+        if (URB_Status == USBH_URB_ERROR)
+        {
+          phost->Control.state = CTRL_ERROR;
+
+#if (USBH_USE_OS == 1U)
+          phost->os_msg = (uint32_t)USBH_CONTROL_EVENT;
+#if (osCMSIS < 0x20000U)
+          (void)osMessagePut(phost->os_event, phost->os_msg, 0U);
+#else
+          (void)osMessageQueuePut(phost->os_event, &phost->os_msg, 0U, 0U);
+#endif
+#endif
+        }
+      }
+      break;
+
+    case CTRL_ERROR:
+      /*
+      After a halt condition is encountered or an error is detected by the
+      host, a control endpoint is allowed to recover by accepting the next Setup
+      PID; i.e., recovery actions via some other pipe are not required for control
+      endpoints. For the Default Control Pipe, a device reset will ultimately be
+      required to clear the halt or error condition if the next Setup PID is not
+      accepted.
+      */
+      if (++phost->Control.errorcount <= USBH_MAX_ERROR_COUNT)
+      {
+        /* Do the transmission again, starting from SETUP Packet */
+        phost->Control.state = CTRL_SETUP;
+        phost->RequestState = CMD_SEND;
+      }
+      else
+      {
+        phost->pUser(phost, HOST_USER_UNRECOVERED_ERROR);
+        phost->Control.errorcount = 0U;
+        USBH_ErrLog("Control error: Device not responding");
+
+        /* Free control pipes */
+        (void)USBH_FreePipe(phost, phost->Control.pipe_out);
+        (void)USBH_FreePipe(phost, phost->Control.pipe_in);
+
+        phost->gState = HOST_IDLE;
+        status = USBH_FAIL;
+      }
+      break;
+
+    default:
+      break;
+  }
+
+  return status;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
+
+
+
diff --git a/Middlewares/ST/STM32_USB_Host_Library/Core/Src/usbh_ioreq.c b/Middlewares/ST/STM32_USB_Host_Library/Core/Src/usbh_ioreq.c
new file mode 100644
index 0000000..00131f3
--- /dev/null
+++ b/Middlewares/ST/STM32_USB_Host_Library/Core/Src/usbh_ioreq.c
@@ -0,0 +1,350 @@
+/**
+  ******************************************************************************
+  * @file    usbh_ioreq.c
+  * @author  MCD Application Team
+  * @brief   This file handles the issuing of the USB transactions
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2015 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                      www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "usbh_ioreq.h"
+
+/** @addtogroup USBH_LIB
+  * @{
+  */
+
+/** @addtogroup USBH_LIB_CORE
+  * @{
+  */
+
+/** @defgroup USBH_IOREQ
+  * @brief This file handles the standard protocol processing (USB v2.0)
+  * @{
+  */
+
+
+/** @defgroup USBH_IOREQ_Private_Defines
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+
+/** @defgroup USBH_IOREQ_Private_TypesDefinitions
+  * @{
+  */
+/**
+  * @}
+  */
+
+
+
+/** @defgroup USBH_IOREQ_Private_Macros
+  * @{
+  */
+/**
+  * @}
+  */
+
+
+/** @defgroup USBH_IOREQ_Private_Variables
+  * @{
+  */
+/**
+  * @}
+  */
+/** @defgroup USBH_IOREQ_Private_FunctionPrototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+
+/** @defgroup USBH_IOREQ_Private_Functions
+  * @{
+  */
+
+
+
+/**
+  * @brief  USBH_CtlSendSetup
+  *         Sends the Setup Packet to the Device
+  * @param  phost: Host Handle
+  * @param  buff: Buffer pointer from which the Data will be send to Device
+  * @param  pipe_num: Pipe Number
+  * @retval USBH Status
+  */
+USBH_StatusTypeDef USBH_CtlSendSetup(USBH_HandleTypeDef *phost,
+                                     uint8_t *buff,
+                                     uint8_t pipe_num)
+{
+
+  (void)USBH_LL_SubmitURB(phost,                /* Driver handle    */
+                          pipe_num,             /* Pipe index       */
+                          0U,                   /* Direction : OUT  */
+                          USBH_EP_CONTROL,      /* EP type          */
+                          USBH_PID_SETUP,       /* Type setup       */
+                          buff,                 /* data buffer      */
+                          USBH_SETUP_PKT_SIZE,  /* data length      */
+                          0U);
+  return USBH_OK;
+}
+
+
+/**
+  * @brief  USBH_CtlSendData
+  *         Sends a data Packet to the Device
+  * @param  phost: Host Handle
+  * @param  buff: Buffer pointer from which the Data will be sent to Device
+  * @param  length: Length of the data to be sent
+  * @param  pipe_num: Pipe Number
+  * @retval USBH Status
+  */
+USBH_StatusTypeDef USBH_CtlSendData(USBH_HandleTypeDef *phost,
+                                    uint8_t *buff,
+                                    uint16_t length,
+                                    uint8_t pipe_num,
+                                    uint8_t do_ping)
+{
+  if (phost->device.speed != USBH_SPEED_HIGH)
+  {
+    do_ping = 0U;
+  }
+
+  (void)USBH_LL_SubmitURB(phost,                /* Driver handle    */
+                          pipe_num,             /* Pipe index       */
+                          0U,                   /* Direction : OUT  */
+                          USBH_EP_CONTROL,      /* EP type          */
+                          USBH_PID_DATA,        /* Type Data        */
+                          buff,                 /* data buffer      */
+                          length,               /* data length      */
+                          do_ping);             /* do ping (HS Only)*/
+
+  return USBH_OK;
+}
+
+
+/**
+  * @brief  USBH_CtlReceiveData
+  *         Receives the Device Response to the Setup Packet
+  * @param  phost: Host Handle
+  * @param  buff: Buffer pointer in which the response needs to be copied
+  * @param  length: Length of the data to be received
+  * @param  pipe_num: Pipe Number
+  * @retval USBH Status.
+  */
+USBH_StatusTypeDef USBH_CtlReceiveData(USBH_HandleTypeDef *phost,
+                                       uint8_t *buff,
+                                       uint16_t length,
+                                       uint8_t pipe_num)
+{
+  (void)USBH_LL_SubmitURB(phost,                /* Driver handle    */
+                          pipe_num,             /* Pipe index       */
+                          1U,                   /* Direction : IN   */
+                          USBH_EP_CONTROL,      /* EP type          */
+                          USBH_PID_DATA,        /* Type Data        */
+                          buff,                 /* data buffer      */
+                          length,               /* data length      */
+                          0U);
+  return USBH_OK;
+
+}
+
+
+/**
+  * @brief  USBH_BulkSendData
+  *         Sends the Bulk Packet to the device
+  * @param  phost: Host Handle
+  * @param  buff: Buffer pointer from which the Data will be sent to Device
+  * @param  length: Length of the data to be sent
+  * @param  pipe_num: Pipe Number
+  * @retval USBH Status
+  */
+USBH_StatusTypeDef USBH_BulkSendData(USBH_HandleTypeDef *phost,
+                                     uint8_t *buff,
+                                     uint16_t length,
+                                     uint8_t pipe_num,
+                                     uint8_t do_ping)
+{
+  if (phost->device.speed != USBH_SPEED_HIGH)
+  {
+    do_ping = 0U;
+  }
+
+  (void)USBH_LL_SubmitURB(phost,                /* Driver handle    */
+                          pipe_num,             /* Pipe index       */
+                          0U,                   /* Direction : IN   */
+                          USBH_EP_BULK,         /* EP type          */
+                          USBH_PID_DATA,        /* Type Data        */
+                          buff,                 /* data buffer      */
+                          length,               /* data length      */
+                          do_ping);             /* do ping (HS Only)*/
+  return USBH_OK;
+}
+
+
+/**
+  * @brief  USBH_BulkReceiveData
+  *         Receives IN bulk packet from device
+  * @param  phost: Host Handle
+  * @param  buff: Buffer pointer in which the received data packet to be copied
+  * @param  length: Length of the data to be received
+  * @param  pipe_num: Pipe Number
+  * @retval USBH Status.
+  */
+USBH_StatusTypeDef USBH_BulkReceiveData(USBH_HandleTypeDef *phost,
+                                        uint8_t *buff,
+                                        uint16_t length,
+                                        uint8_t pipe_num)
+{
+  (void)USBH_LL_SubmitURB(phost,                /* Driver handle    */
+                          pipe_num,             /* Pipe index       */
+                          1U,                   /* Direction : IN   */
+                          USBH_EP_BULK,         /* EP type          */
+                          USBH_PID_DATA,        /* Type Data        */
+                          buff,                 /* data buffer      */
+                          length,               /* data length      */
+                          0U);
+  return USBH_OK;
+}
+
+
+/**
+  * @brief  USBH_InterruptReceiveData
+  *         Receives the Device Response to the Interrupt IN token
+  * @param  phost: Host Handle
+  * @param  buff: Buffer pointer in which the response needs to be copied
+  * @param  length: Length of the data to be received
+  * @param  pipe_num: Pipe Number
+  * @retval USBH Status.
+  */
+USBH_StatusTypeDef USBH_InterruptReceiveData(USBH_HandleTypeDef *phost,
+                                             uint8_t *buff,
+                                             uint8_t length,
+                                             uint8_t pipe_num)
+{
+  (void)USBH_LL_SubmitURB(phost,                /* Driver handle    */
+                          pipe_num,             /* Pipe index       */
+                          1U,                   /* Direction : IN   */
+                          USBH_EP_INTERRUPT,    /* EP type          */
+                          USBH_PID_DATA,        /* Type Data        */
+                          buff,                 /* data buffer      */
+                          (uint16_t)length,     /* data length      */
+                          0U);
+
+  return USBH_OK;
+}
+
+/**
+  * @brief  USBH_InterruptSendData
+  *         Sends the data on Interrupt OUT Endpoint
+  * @param  phost: Host Handle
+  * @param  buff: Buffer pointer from where the data needs to be copied
+  * @param  length: Length of the data to be sent
+  * @param  pipe_num: Pipe Number
+  * @retval USBH Status.
+  */
+USBH_StatusTypeDef USBH_InterruptSendData(USBH_HandleTypeDef *phost,
+                                          uint8_t *buff,
+                                          uint8_t length,
+                                          uint8_t pipe_num)
+{
+  (void)USBH_LL_SubmitURB(phost,                /* Driver handle    */
+                          pipe_num,             /* Pipe index       */
+                          0U,                   /* Direction : OUT  */
+                          USBH_EP_INTERRUPT,    /* EP type          */
+                          USBH_PID_DATA,        /* Type Data        */
+                          buff,                 /* data buffer      */
+                          (uint16_t)length,     /* data length      */
+                          0U);
+
+  return USBH_OK;
+}
+
+/**
+  * @brief  USBH_IsocReceiveData
+  *         Receives the Device Response to the Isochronous IN token
+  * @param  phost: Host Handle
+  * @param  buff: Buffer pointer in which the response needs to be copied
+  * @param  length: Length of the data to be received
+  * @param  pipe_num: Pipe Number
+  * @retval USBH Status.
+  */
+USBH_StatusTypeDef USBH_IsocReceiveData(USBH_HandleTypeDef *phost,
+                                        uint8_t *buff,
+                                        uint32_t length,
+                                        uint8_t pipe_num)
+{
+  (void)USBH_LL_SubmitURB(phost,                /* Driver handle    */
+                          pipe_num,             /* Pipe index       */
+                          1U,                   /* Direction : IN   */
+                          USBH_EP_ISO,          /* EP type          */
+                          USBH_PID_DATA,        /* Type Data        */
+                          buff,                 /* data buffer      */
+                          (uint16_t)length,     /* data length      */
+                          0U);
+
+
+  return USBH_OK;
+}
+
+/**
+  * @brief  USBH_IsocSendData
+  *         Sends the data on Isochronous OUT Endpoint
+  * @param  phost: Host Handle
+  * @param  buff: Buffer pointer from where the data needs to be copied
+  * @param  length: Length of the data to be sent
+  * @param  pipe_num: Pipe Number
+  * @retval USBH Status.
+  */
+USBH_StatusTypeDef USBH_IsocSendData(USBH_HandleTypeDef *phost,
+                                     uint8_t *buff,
+                                     uint32_t length,
+                                     uint8_t pipe_num)
+{
+  (void)USBH_LL_SubmitURB(phost,                /* Driver handle    */
+                          pipe_num,             /* Pipe index       */
+                          0U,                   /* Direction : OUT  */
+                          USBH_EP_ISO,          /* EP type          */
+                          USBH_PID_DATA,        /* Type Data        */
+                          buff,                 /* data buffer      */
+                          (uint16_t)length,     /* data length      */
+                          0U);
+
+  return USBH_OK;
+}
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
+
+
diff --git a/Middlewares/ST/STM32_USB_Host_Library/Core/Src/usbh_pipes.c b/Middlewares/ST/STM32_USB_Host_Library/Core/Src/usbh_pipes.c
new file mode 100644
index 0000000..091473f
--- /dev/null
+++ b/Middlewares/ST/STM32_USB_Host_Library/Core/Src/usbh_pipes.c
@@ -0,0 +1,188 @@
+/**
+  ******************************************************************************
+  * @file    usbh_pipes.c
+  * @author  MCD Application Team
+  * @brief   This file implements functions for opening and closing Pipes
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2015 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                      www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "usbh_pipes.h"
+
+/** @addtogroup USBH_LIB
+  * @{
+  */
+
+/** @addtogroup USBH_LIB_CORE
+  * @{
+  */
+
+/** @defgroup USBH_PIPES
+  * @brief This file includes opening and closing Pipes
+  * @{
+  */
+
+/** @defgroup USBH_PIPES_Private_Defines
+  * @{
+  */
+/**
+  * @}
+  */
+
+/** @defgroup USBH_PIPES_Private_TypesDefinitions
+  * @{
+  */
+/**
+  * @}
+  */
+
+
+/** @defgroup USBH_PIPES_Private_Macros
+  * @{
+  */
+/**
+  * @}
+  */
+
+
+/** @defgroup USBH_PIPES_Private_Variables
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+
+/** @defgroup USBH_PIPES_Private_Functions
+  * @{
+  */
+static uint16_t USBH_GetFreePipe(USBH_HandleTypeDef *phost);
+
+
+/**
+  * @brief  USBH_Open_Pipe
+  *         Open a  pipe
+  * @param  phost: Host Handle
+  * @param  pipe_num: Pipe Number
+  * @param  dev_address: USB Device address allocated to attached device
+  * @param  speed : USB device speed (Full/Low)
+  * @param  ep_type: end point type (Bulk/int/ctl)
+  * @param  mps: max pkt size
+  * @retval USBH Status
+  */
+USBH_StatusTypeDef USBH_OpenPipe(USBH_HandleTypeDef *phost, uint8_t pipe_num,
+                                 uint8_t epnum, uint8_t dev_address,
+                                 uint8_t speed, uint8_t ep_type, uint16_t mps)
+{
+  (void)USBH_LL_OpenPipe(phost, pipe_num, epnum, dev_address, speed, ep_type, mps);
+
+  return USBH_OK;
+}
+
+
+/**
+  * @brief  USBH_ClosePipe
+  *         Close a  pipe
+  * @param  phost: Host Handle
+  * @param  pipe_num: Pipe Number
+  * @retval USBH Status
+  */
+USBH_StatusTypeDef USBH_ClosePipe(USBH_HandleTypeDef *phost, uint8_t pipe_num)
+{
+  (void)USBH_LL_ClosePipe(phost, pipe_num);
+
+  return USBH_OK;
+}
+
+
+/**
+  * @brief  USBH_Alloc_Pipe
+  *         Allocate a new Pipe
+  * @param  phost: Host Handle
+  * @param  ep_addr: End point for which the Pipe to be allocated
+  * @retval Pipe number
+  */
+uint8_t USBH_AllocPipe(USBH_HandleTypeDef *phost, uint8_t ep_addr)
+{
+  uint16_t pipe;
+
+  pipe =  USBH_GetFreePipe(phost);
+
+  if (pipe != 0xFFFFU)
+  {
+    phost->Pipes[pipe & 0xFU] = (uint32_t)(0x8000U | ep_addr);
+  }
+
+  return (uint8_t)pipe;
+}
+
+
+/**
+  * @brief  USBH_Free_Pipe
+  *         Free the USB Pipe
+  * @param  phost: Host Handle
+  * @param  idx: Pipe number to be freed
+  * @retval USBH Status
+  */
+USBH_StatusTypeDef USBH_FreePipe(USBH_HandleTypeDef *phost, uint8_t idx)
+{
+  if (idx < USBH_MAX_PIPES_NBR)
+  {
+    phost->Pipes[idx] &= 0x7FFFU;
+  }
+
+  return USBH_OK;
+}
+
+
+/**
+  * @brief  USBH_GetFreePipe
+  * @param  phost: Host Handle
+  *         Get a free Pipe number for allocation to a device endpoint
+  * @retval idx: Free Pipe number
+  */
+static uint16_t USBH_GetFreePipe(USBH_HandleTypeDef *phost)
+{
+  uint8_t idx = 0U;
+
+  for (idx = 0U ; idx < USBH_MAX_PIPES_NBR ; idx++)
+  {
+    if ((phost->Pipes[idx] & 0x8000U) == 0U)
+    {
+      return (uint16_t)idx;
+    }
+  }
+
+  return 0xFFFFU;
+}
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
+
diff --git a/Middlewares/Third_Party/FatFs/src/diskio.c b/Middlewares/Third_Party/FatFs/src/diskio.c
new file mode 100644
index 0000000..6c0881f
--- /dev/null
+++ b/Middlewares/Third_Party/FatFs/src/diskio.c
@@ -0,0 +1,141 @@
+/*-----------------------------------------------------------------------*/
+/* Low level disk I/O module skeleton for FatFs     (C)ChaN, 2017        */
+/*                                                                       */
+/*   Portions COPYRIGHT 2017 STMicroelectronics                          */
+/*   Portions Copyright (C) 2017, ChaN, all right reserved               */
+/*-----------------------------------------------------------------------*/
+/* If a working storage control module is available, it should be        */
+/* attached to the FatFs via a glue function rather than modifying it.   */
+/* This is an example of glue functions to attach various existing      */
+/* storage control modules to the FatFs module with a defined API.       */
+/*-----------------------------------------------------------------------*/
+
+/* Includes ------------------------------------------------------------------*/
+#include "diskio.h"
+#include "ff_gen_drv.h"
+
+#if defined ( __GNUC__ )
+#ifndef __weak
+#define __weak __attribute__((weak))
+#endif
+#endif
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+extern Disk_drvTypeDef  disk;
+
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/**
+  * @brief  Gets Disk Status
+  * @param  pdrv: Physical drive number (0..)
+  * @retval DSTATUS: Operation status
+  */
+DSTATUS disk_status (
+	BYTE pdrv		/* Physical drive number to identify the drive */
+)
+{
+  DSTATUS stat;
+
+  stat = disk.drv[pdrv]->disk_status(disk.lun[pdrv]);
+  return stat;
+}
+
+/**
+  * @brief  Initializes a Drive
+  * @param  pdrv: Physical drive number (0..)
+  * @retval DSTATUS: Operation status
+  */
+DSTATUS disk_initialize (
+	BYTE pdrv				/* Physical drive nmuber to identify the drive */
+)
+{
+  DSTATUS stat = RES_OK;
+
+  if(disk.is_initialized[pdrv] == 0)
+  {
+    disk.is_initialized[pdrv] = 1;
+    stat = disk.drv[pdrv]->disk_initialize(disk.lun[pdrv]);
+  }
+  return stat;
+}
+
+/**
+  * @brief  Reads Sector(s)
+  * @param  pdrv: Physical drive number (0..)
+  * @param  *buff: Data buffer to store read data
+  * @param  sector: Sector address (LBA)
+  * @param  count: Number of sectors to read (1..128)
+  * @retval DRESULT: Operation result
+  */
+DRESULT disk_read (
+	BYTE pdrv,		/* Physical drive nmuber to identify the drive */
+	BYTE *buff,		/* Data buffer to store read data */
+	DWORD sector,	        /* Sector address in LBA */
+	UINT count		/* Number of sectors to read */
+)
+{
+  DRESULT res;
+
+  res = disk.drv[pdrv]->disk_read(disk.lun[pdrv], buff, sector, count);
+  return res;
+}
+
+/**
+  * @brief  Writes Sector(s)
+  * @param  pdrv: Physical drive number (0..)
+  * @param  *buff: Data to be written
+  * @param  sector: Sector address (LBA)
+  * @param  count: Number of sectors to write (1..128)
+  * @retval DRESULT: Operation result
+  */
+#if _USE_WRITE == 1
+DRESULT disk_write (
+	BYTE pdrv,		/* Physical drive nmuber to identify the drive */
+	const BYTE *buff,	/* Data to be written */
+	DWORD sector,		/* Sector address in LBA */
+	UINT count        	/* Number of sectors to write */
+)
+{
+  DRESULT res;
+
+  res = disk.drv[pdrv]->disk_write(disk.lun[pdrv], buff, sector, count);
+  return res;
+}
+#endif /* _USE_WRITE == 1 */
+
+/**
+  * @brief  I/O control operation
+  * @param  pdrv: Physical drive number (0..)
+  * @param  cmd: Control code
+  * @param  *buff: Buffer to send/receive control data
+  * @retval DRESULT: Operation result
+  */
+#if _USE_IOCTL == 1
+DRESULT disk_ioctl (
+	BYTE pdrv,		/* Physical drive nmuber (0..) */
+	BYTE cmd,		/* Control code */
+	void *buff		/* Buffer to send/receive control data */
+)
+{
+  DRESULT res;
+
+  res = disk.drv[pdrv]->disk_ioctl(disk.lun[pdrv], cmd, buff);
+  return res;
+}
+#endif /* _USE_IOCTL == 1 */
+
+/**
+  * @brief  Gets Time from RTC
+  * @param  None
+  * @retval Time in DWORD
+  */
+__weak DWORD get_fattime (void)
+{
+  return 0;
+}
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/Middlewares/Third_Party/FatFs/src/diskio.h b/Middlewares/Third_Party/FatFs/src/diskio.h
new file mode 100644
index 0000000..7a417d9
--- /dev/null
+++ b/Middlewares/Third_Party/FatFs/src/diskio.h
@@ -0,0 +1,80 @@
+/*-----------------------------------------------------------------------/
+/  Low level disk interface modlue include file   (C)ChaN, 2014          /
+/-----------------------------------------------------------------------*/
+
+#ifndef _DISKIO_DEFINED
+#define _DISKIO_DEFINED
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define _USE_WRITE	1	/* 1: Enable disk_write function */
+#define _USE_IOCTL	1	/* 1: Enable disk_ioctl function */
+
+#include "integer.h"
+
+
+/* Status of Disk Functions */
+typedef BYTE	DSTATUS;
+
+/* Results of Disk Functions */
+typedef enum {
+	RES_OK = 0,		/* 0: Successful */
+	RES_ERROR,		/* 1: R/W Error */
+	RES_WRPRT,		/* 2: Write Protected */
+	RES_NOTRDY,		/* 3: Not Ready */
+	RES_PARERR		/* 4: Invalid Parameter */
+} DRESULT;
+
+
+/*---------------------------------------*/
+/* Prototypes for disk control functions */
+
+
+DSTATUS disk_initialize (BYTE pdrv);
+DSTATUS disk_status (BYTE pdrv);
+DRESULT disk_read (BYTE pdrv, BYTE* buff, DWORD sector, UINT count);
+DRESULT disk_write (BYTE pdrv, const BYTE* buff, DWORD sector, UINT count);
+DRESULT disk_ioctl (BYTE pdrv, BYTE cmd, void* buff);
+DWORD get_fattime (void);
+
+/* Disk Status Bits (DSTATUS) */
+
+#define STA_NOINIT		0x01	/* Drive not initialized */
+#define STA_NODISK		0x02	/* No medium in the drive */
+#define STA_PROTECT		0x04	/* Write protected */
+
+
+/* Command code for disk_ioctrl fucntion */
+
+/* Generic command (Used by FatFs) */
+#define CTRL_SYNC		0	/* Complete pending write process (needed at _FS_READONLY == 0) */
+#define GET_SECTOR_COUNT	1	/* Get media size (needed at _USE_MKFS == 1) */
+#define GET_SECTOR_SIZE		2	/* Get sector size (needed at _MAX_SS != _MIN_SS) */
+#define GET_BLOCK_SIZE		3	/* Get erase block size (needed at _USE_MKFS == 1) */
+#define CTRL_TRIM		4	/* Inform device that the data on the block of sectors is no longer used (needed at _USE_TRIM == 1) */
+
+/* Generic command (Not used by FatFs) */
+#define CTRL_POWER			5	/* Get/Set power status */
+#define CTRL_LOCK			6	/* Lock/Unlock media removal */
+#define CTRL_EJECT			7	/* Eject media */
+#define CTRL_FORMAT			8	/* Create physical format on the media */
+
+/* MMC/SDC specific ioctl command */
+#define MMC_GET_TYPE		10	/* Get card type */
+#define MMC_GET_CSD			11	/* Get CSD */
+#define MMC_GET_CID			12	/* Get CID */
+#define MMC_GET_OCR			13	/* Get OCR */
+#define MMC_GET_SDSTAT		14	/* Get SD status */
+
+/* ATA/CF specific ioctl command */
+#define ATA_GET_REV			20	/* Get F/W revision */
+#define ATA_GET_MODEL		21	/* Get model name */
+#define ATA_GET_SN			22	/* Get serial number */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/Middlewares/Third_Party/FatFs/src/ff.c b/Middlewares/Third_Party/FatFs/src/ff.c
new file mode 100644
index 0000000..253de3c
--- /dev/null
+++ b/Middlewares/Third_Party/FatFs/src/ff.c
@@ -0,0 +1,6140 @@
+/*----------------------------------------------------------------------------/
+/  FatFs - Generic FAT file system module  R0.12c                             /
+/-----------------------------------------------------------------------------/
+/
+/ Copyright (C) 2017, ChaN, all right reserved.
+/
+/ FatFs module is an open source software. Redistribution and use of FatFs in
+/ source and binary forms, with or without modification, are permitted provided
+/ that the following condition is met:
+/
+/ 1. Redistributions of source code must retain the above copyright notice,
+/    this condition and the following disclaimer.
+/
+/ This software is provided by the copyright holder and contributors "AS IS"
+/ and any warranties related to this software are DISCLAIMED.
+/ The copyright owner or contributors be NOT LIABLE for any damages caused
+/ by use of this software.
+/----------------------------------------------------------------------------*/
+
+
+#include "ff.h"			/* Declarations of FatFs API */
+#include "diskio.h"		/* Declarations of device I/O functions */
+
+
+/*--------------------------------------------------------------------------
+
+   Module Private Definitions
+
+---------------------------------------------------------------------------*/
+
+#if _FATFS != 68300	/* Revision ID */
+#error Wrong include file (ff.h).
+#endif
+
+
+/* DBCS code ranges and SBCS upper conversion tables */
+
+#if _CODE_PAGE == 932	/* Japanese Shift-JIS */
+#define _DF1S	0x81	/* DBC 1st byte range 1 start */
+#define _DF1E	0x9F	/* DBC 1st byte range 1 end */
+#define _DF2S	0xE0	/* DBC 1st byte range 2 start */
+#define _DF2E	0xFC	/* DBC 1st byte range 2 end */
+#define _DS1S	0x40	/* DBC 2nd byte range 1 start */
+#define _DS1E	0x7E	/* DBC 2nd byte range 1 end */
+#define _DS2S	0x80	/* DBC 2nd byte range 2 start */
+#define _DS2E	0xFC	/* DBC 2nd byte range 2 end */
+
+#elif _CODE_PAGE == 936	/* Simplified Chinese GBK */
+#define _DF1S	0x81
+#define _DF1E	0xFE
+#define _DS1S	0x40
+#define _DS1E	0x7E
+#define _DS2S	0x80
+#define _DS2E	0xFE
+
+#elif _CODE_PAGE == 949	/* Korean */
+#define _DF1S	0x81
+#define _DF1E	0xFE
+#define _DS1S	0x41
+#define _DS1E	0x5A
+#define _DS2S	0x61
+#define _DS2E	0x7A
+#define _DS3S	0x81
+#define _DS3E	0xFE
+
+#elif _CODE_PAGE == 950	/* Traditional Chinese Big5 */
+#define _DF1S	0x81
+#define _DF1E	0xFE
+#define _DS1S	0x40
+#define _DS1E	0x7E
+#define _DS2S	0xA1
+#define _DS2E	0xFE
+
+#elif _CODE_PAGE == 437	/* U.S. */
+#define _DF1S	0
+#define _EXCVT {0x80,0x9A,0x45,0x41,0x8E,0x41,0x8F,0x80,0x45,0x45,0x45,0x49,0x49,0x49,0x8E,0x8F, \
+				0x90,0x92,0x92,0x4F,0x99,0x4F,0x55,0x55,0x59,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
+				0x41,0x49,0x4F,0x55,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF, \
+				0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \
+				0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF, \
+				0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 720	/* Arabic */
+#define _DF1S	0
+#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F, \
+				0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
+				0xA0,0xA1,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF, \
+				0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \
+				0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF, \
+				0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 737	/* Greek */
+#define _DF1S	0
+#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F, \
+				0x90,0x92,0x92,0x93,0x94,0x95,0x96,0x97,0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87, \
+				0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0xAA,0x92,0x93,0x94,0x95,0x96, \
+				0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \
+				0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0x97,0xEA,0xEB,0xEC,0xE4,0xED,0xEE,0xEF,0xF5,0xF0,0xEA,0xEB,0xEC,0xED,0xEE,0xEF, \
+				0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 771	/* KBL */
+#define _DF1S	0
+#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F, \
+				0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
+				0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F, \
+				0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \
+				0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDC,0xDE,0xDE, \
+				0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
+				0xF0,0xF0,0xF2,0xF2,0xF4,0xF4,0xF6,0xF6,0xF8,0xF8,0xFA,0xFA,0xFC,0xFC,0xFE,0xFF}
+
+#elif _CODE_PAGE == 775	/* Baltic */
+#define _DF1S	0
+#define _EXCVT {0x80,0x9A,0x91,0xA0,0x8E,0x95,0x8F,0x80,0xAD,0xED,0x8A,0x8A,0xA1,0x8D,0x8E,0x8F, \
+				0x90,0x92,0x92,0xE2,0x99,0x95,0x96,0x97,0x97,0x99,0x9A,0x9D,0x9C,0x9D,0x9E,0x9F, \
+				0xA0,0xA1,0xE0,0xA3,0xA3,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF, \
+				0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \
+				0xB5,0xB6,0xB7,0xB8,0xBD,0xBE,0xC6,0xC7,0xA5,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0xE0,0xE1,0xE2,0xE3,0xE5,0xE5,0xE6,0xE3,0xE8,0xE8,0xEA,0xEA,0xEE,0xED,0xEE,0xEF, \
+				0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 850	/* Latin 1 */
+#define _DF1S	0
+#define _EXCVT {0x43,0x55,0x45,0x41,0x41,0x41,0x41,0x43,0x45,0x45,0x45,0x49,0x49,0x49,0x41,0x41, \
+				0x45,0x92,0x92,0x4F,0x4F,0x4F,0x55,0x55,0x59,0x4F,0x55,0x4F,0x9C,0x4F,0x9E,0x9F, \
+				0x41,0x49,0x4F,0x55,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF, \
+				0xB0,0xB1,0xB2,0xB3,0xB4,0x41,0x41,0x41,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0x41,0x41,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \
+				0xD1,0xD1,0x45,0x45,0x45,0x49,0x49,0x49,0x49,0xD9,0xDA,0xDB,0xDC,0xDD,0x49,0xDF, \
+				0x4F,0xE1,0x4F,0x4F,0x4F,0x4F,0xE6,0xE8,0xE8,0x55,0x55,0x55,0x59,0x59,0xEE,0xEF, \
+				0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 852	/* Latin 2 */
+#define _DF1S	0
+#define _EXCVT {0x80,0x9A,0x90,0xB6,0x8E,0xDE,0x8F,0x80,0x9D,0xD3,0x8A,0x8A,0xD7,0x8D,0x8E,0x8F, \
+				0x90,0x91,0x91,0xE2,0x99,0x95,0x95,0x97,0x97,0x99,0x9A,0x9B,0x9B,0x9D,0x9E,0xAC, \
+				0xB5,0xD6,0xE0,0xE9,0xA4,0xA4,0xA6,0xA6,0xA8,0xA8,0xAA,0x8D,0xAC,0xB8,0xAE,0xAF, \
+				0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBD,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC6,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \
+				0xD1,0xD1,0xD2,0xD3,0xD2,0xD5,0xD6,0xD7,0xB7,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0xE0,0xE1,0xE2,0xE3,0xE3,0xD5,0xE6,0xE6,0xE8,0xE9,0xE8,0xEB,0xED,0xED,0xDD,0xEF, \
+				0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xEB,0xFC,0xFC,0xFE,0xFF}
+
+#elif _CODE_PAGE == 855	/* Cyrillic */
+#define _DF1S	0
+#define _EXCVT {0x81,0x81,0x83,0x83,0x85,0x85,0x87,0x87,0x89,0x89,0x8B,0x8B,0x8D,0x8D,0x8F,0x8F, \
+				0x91,0x91,0x93,0x93,0x95,0x95,0x97,0x97,0x99,0x99,0x9B,0x9B,0x9D,0x9D,0x9F,0x9F, \
+				0xA1,0xA1,0xA3,0xA3,0xA5,0xA5,0xA7,0xA7,0xA9,0xA9,0xAB,0xAB,0xAD,0xAD,0xAE,0xAF, \
+				0xB0,0xB1,0xB2,0xB3,0xB4,0xB6,0xB6,0xB8,0xB8,0xB9,0xBA,0xBB,0xBC,0xBE,0xBE,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC7,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \
+				0xD1,0xD1,0xD3,0xD3,0xD5,0xD5,0xD7,0xD7,0xDD,0xD9,0xDA,0xDB,0xDC,0xDD,0xE0,0xDF, \
+				0xE0,0xE2,0xE2,0xE4,0xE4,0xE6,0xE6,0xE8,0xE8,0xEA,0xEA,0xEC,0xEC,0xEE,0xEE,0xEF, \
+				0xF0,0xF2,0xF2,0xF4,0xF4,0xF6,0xF6,0xF8,0xF8,0xFA,0xFA,0xFC,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 857	/* Turkish */
+#define _DF1S	0
+#define _EXCVT {0x80,0x9A,0x90,0xB6,0x8E,0xB7,0x8F,0x80,0xD2,0xD3,0xD4,0xD8,0xD7,0x49,0x8E,0x8F, \
+				0x90,0x92,0x92,0xE2,0x99,0xE3,0xEA,0xEB,0x98,0x99,0x9A,0x9D,0x9C,0x9D,0x9E,0x9E, \
+				0xB5,0xD6,0xE0,0xE9,0xA5,0xA5,0xA6,0xA6,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF, \
+				0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC7,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \
+				0xD0,0xD1,0xD2,0xD3,0xD4,0x49,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0xE0,0xE1,0xE2,0xE3,0xE5,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xDE,0xED,0xEE,0xEF, \
+				0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 860	/* Portuguese */
+#define _DF1S	0
+#define _EXCVT {0x80,0x9A,0x90,0x8F,0x8E,0x91,0x86,0x80,0x89,0x89,0x92,0x8B,0x8C,0x98,0x8E,0x8F, \
+				0x90,0x91,0x92,0x8C,0x99,0xA9,0x96,0x9D,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
+				0x86,0x8B,0x9F,0x96,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF, \
+				0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \
+				0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF, \
+				0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 861	/* Icelandic */
+#define _DF1S	0
+#define _EXCVT {0x80,0x9A,0x90,0x41,0x8E,0x41,0x8F,0x80,0x45,0x45,0x45,0x8B,0x8B,0x8D,0x8E,0x8F, \
+				0x90,0x92,0x92,0x4F,0x99,0x8D,0x55,0x97,0x97,0x99,0x9A,0x9D,0x9C,0x9D,0x9E,0x9F, \
+				0xA4,0xA5,0xA6,0xA7,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF, \
+				0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \
+				0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF, \
+				0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 862	/* Hebrew */
+#define _DF1S	0
+#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F, \
+				0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
+				0x41,0x49,0x4F,0x55,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF, \
+				0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \
+				0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF, \
+				0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 863	/* Canadian-French */
+#define _DF1S	0
+#define _EXCVT {0x43,0x55,0x45,0x41,0x41,0x41,0x86,0x43,0x45,0x45,0x45,0x49,0x49,0x8D,0x41,0x8F, \
+				0x45,0x45,0x45,0x4F,0x45,0x49,0x55,0x55,0x98,0x4F,0x55,0x9B,0x9C,0x55,0x55,0x9F, \
+				0xA0,0xA1,0x4F,0x55,0xA4,0xA5,0xA6,0xA7,0x49,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF, \
+				0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \
+				0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF, \
+				0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 864	/* Arabic */
+#define _DF1S	0
+#define _EXCVT {0x80,0x9A,0x45,0x41,0x8E,0x41,0x8F,0x80,0x45,0x45,0x45,0x49,0x49,0x49,0x8E,0x8F, \
+				0x90,0x92,0x92,0x4F,0x99,0x4F,0x55,0x55,0x59,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
+				0x41,0x49,0x4F,0x55,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF, \
+				0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \
+				0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF, \
+				0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 865	/* Nordic */
+#define _DF1S	0
+#define _EXCVT {0x80,0x9A,0x90,0x41,0x8E,0x41,0x8F,0x80,0x45,0x45,0x45,0x49,0x49,0x49,0x8E,0x8F, \
+				0x90,0x92,0x92,0x4F,0x99,0x4F,0x55,0x55,0x59,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
+				0x41,0x49,0x4F,0x55,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF, \
+				0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \
+				0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF, \
+				0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 866	/* Russian */
+#define _DF1S	0
+#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F, \
+				0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
+				0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F, \
+				0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \
+				0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
+				0xF0,0xF0,0xF2,0xF2,0xF4,0xF4,0xF6,0xF6,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 869	/* Greek 2 */
+#define _DF1S	0
+#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F, \
+				0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x86,0x9C,0x8D,0x8F,0x90, \
+				0x91,0x90,0x92,0x95,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF, \
+				0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \
+				0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xA4,0xA5,0xA6,0xD9,0xDA,0xDB,0xDC,0xA7,0xA8,0xDF, \
+				0xA9,0xAA,0xAC,0xAD,0xB5,0xB6,0xB7,0xB8,0xBD,0xBE,0xC6,0xC7,0xCF,0xCF,0xD0,0xEF, \
+				0xF0,0xF1,0xD1,0xD2,0xD3,0xF5,0xD4,0xF7,0xF8,0xF9,0xD5,0x96,0x95,0x98,0xFE,0xFF}
+
+#elif _CODE_PAGE == 1	/* ASCII (for only non-LFN cfg) */
+#if _USE_LFN != 0
+#error Cannot enable LFN without valid code page.
+#endif
+#define _DF1S	0
+
+#else
+#error Unknown code page
+
+#endif
+
+
+/* Character code support macros */
+#define IsUpper(c)	(((c)>='A')&&((c)<='Z'))
+#define IsLower(c)	(((c)>='a')&&((c)<='z'))
+#define IsDigit(c)	(((c)>='0')&&((c)<='9'))
+
+#if _DF1S != 0	/* Code page is DBCS */
+
+#ifdef _DF2S	/* Two 1st byte areas */
+#define IsDBCS1(c)	(((BYTE)(c) >= _DF1S && (BYTE)(c) <= _DF1E) || ((BYTE)(c) >= _DF2S && (BYTE)(c) <= _DF2E))
+#else			/* One 1st byte area */
+#define IsDBCS1(c)	((BYTE)(c) >= _DF1S && (BYTE)(c) <= _DF1E)
+#endif
+
+#ifdef _DS3S	/* Three 2nd byte areas */
+#define IsDBCS2(c)	(((BYTE)(c) >= _DS1S && (BYTE)(c) <= _DS1E) || ((BYTE)(c) >= _DS2S && (BYTE)(c) <= _DS2E) || ((BYTE)(c) >= _DS3S && (BYTE)(c) <= _DS3E))
+#else			/* Two 2nd byte areas */
+#define IsDBCS2(c)	(((BYTE)(c) >= _DS1S && (BYTE)(c) <= _DS1E) || ((BYTE)(c) >= _DS2S && (BYTE)(c) <= _DS2E))
+#endif
+
+#else			/* Code page is SBCS */
+
+#define IsDBCS1(c)	0
+#define IsDBCS2(c)	0
+
+#endif /* _DF1S */
+
+
+/* Additional file attribute bits for internal use */
+#define	AM_VOL		0x08	/* Volume label */
+#define AM_LFN		0x0F	/* LFN entry */
+#define AM_MASK		0x3F	/* Mask of defined bits */
+
+
+/* Additional file access control and file status flags for internal use */
+#define FA_SEEKEND	0x20	/* Seek to end of the file on file open */
+#define FA_MODIFIED	0x40	/* File has been modified */
+#define FA_DIRTY	0x80	/* FIL.buf[] needs to be written-back */
+
+
+/* Name status flags in fn[] */
+#define NSFLAG		11		/* Index of the name status byte */
+#define NS_LOSS		0x01	/* Out of 8.3 format */
+#define NS_LFN		0x02	/* Force to create LFN entry */
+#define NS_LAST		0x04	/* Last segment */
+#define NS_BODY		0x08	/* Lower case flag (body) */
+#define NS_EXT		0x10	/* Lower case flag (ext) */
+#define NS_DOT		0x20	/* Dot entry */
+#define NS_NOLFN	0x40	/* Do not find LFN */
+#define NS_NONAME	0x80	/* Not followed */
+
+
+/* Limits and boundaries */
+#define MAX_DIR		0x200000		/* Max size of FAT directory */
+#define MAX_DIR_EX	0x10000000		/* Max size of exFAT directory */
+#define MAX_FAT12	0xFF5			/* Max FAT12 clusters (differs from specs, but correct for real DOS/Windows behavior) */
+#define	MAX_FAT16	0xFFF5			/* Max FAT16 clusters (differs from specs, but correct for real DOS/Windows behavior) */
+#define	MAX_FAT32	0x0FFFFFF5		/* Max FAT32 clusters (not specified, practical limit) */
+#define	MAX_EXFAT	0x7FFFFFFD		/* Max exFAT clusters (differs from specs, implementation limit) */
+
+
+/* FatFs refers the FAT structure as simple byte array instead of structure member
+/ because the C structure is not binary compatible between different platforms */
+
+#define BS_JmpBoot			0		/* x86 jump instruction (3-byte) */
+#define BS_OEMName			3		/* OEM name (8-byte) */
+#define BPB_BytsPerSec		11		/* Sector size [byte] (WORD) */
+#define BPB_SecPerClus		13		/* Cluster size [sector] (BYTE) */
+#define BPB_RsvdSecCnt		14		/* Size of reserved area [sector] (WORD) */
+#define BPB_NumFATs			16		/* Number of FATs (BYTE) */
+#define BPB_RootEntCnt		17		/* Size of root directory area for FAT12/16 [entry] (WORD) */
+#define BPB_TotSec16		19		/* Volume size (16-bit) [sector] (WORD) */
+#define BPB_Media			21		/* Media descriptor byte (BYTE) */
+#define BPB_FATSz16			22		/* FAT size (16-bit) [sector] (WORD) */
+#define BPB_SecPerTrk		24		/* Track size for int13h [sector] (WORD) */
+#define BPB_NumHeads		26		/* Number of heads for int13h (WORD) */
+#define BPB_HiddSec			28		/* Volume offset from top of the drive (DWORD) */
+#define BPB_TotSec32		32		/* Volume size (32-bit) [sector] (DWORD) */
+#define BS_DrvNum			36		/* Physical drive number for int13h (BYTE) */
+#define BS_NTres			37		/* Error flag (BYTE) */
+#define BS_BootSig			38		/* Extended boot signature (BYTE) */
+#define BS_VolID			39		/* Volume serial number (DWORD) */
+#define BS_VolLab			43		/* Volume label string (8-byte) */
+#define BS_FilSysType		54		/* File system type string (8-byte) */
+#define BS_BootCode			62		/* Boot code (448-byte) */
+#define BS_55AA				510		/* Signature word (WORD) */
+
+#define BPB_FATSz32			36		/* FAT32: FAT size [sector] (DWORD) */
+#define BPB_ExtFlags32		40		/* FAT32: Extended flags (WORD) */
+#define BPB_FSVer32			42		/* FAT32: File system version (WORD) */
+#define BPB_RootClus32		44		/* FAT32: Root directory cluster (DWORD) */
+#define BPB_FSInfo32		48		/* FAT32: Offset of FSINFO sector (WORD) */
+#define BPB_BkBootSec32		50		/* FAT32: Offset of backup boot sector (WORD) */
+#define BS_DrvNum32			64		/* FAT32: Physical drive number for int13h (BYTE) */
+#define BS_NTres32			65		/* FAT32: Error flag (BYTE) */
+#define BS_BootSig32		66		/* FAT32: Extended boot signature (BYTE) */
+#define BS_VolID32			67		/* FAT32: Volume serial number (DWORD) */
+#define BS_VolLab32			71		/* FAT32: Volume label string (8-byte) */
+#define BS_FilSysType32		82		/* FAT32: File system type string (8-byte) */
+#define BS_BootCode32		90		/* FAT32: Boot code (420-byte) */
+
+#define BPB_ZeroedEx		11		/* exFAT: MBZ field (53-byte) */
+#define BPB_VolOfsEx		64		/* exFAT: Volume offset from top of the drive [sector] (QWORD) */
+#define BPB_TotSecEx		72		/* exFAT: Volume size [sector] (QWORD) */
+#define BPB_FatOfsEx		80		/* exFAT: FAT offset from top of the volume [sector] (DWORD) */
+#define BPB_FatSzEx			84		/* exFAT: FAT size [sector] (DWORD) */
+#define BPB_DataOfsEx		88		/* exFAT: Data offset from top of the volume [sector] (DWORD) */
+#define BPB_NumClusEx		92		/* exFAT: Number of clusters (DWORD) */
+#define BPB_RootClusEx		96		/* exFAT: Root directory start cluster (DWORD) */
+#define BPB_VolIDEx			100		/* exFAT: Volume serial number (DWORD) */
+#define BPB_FSVerEx			104		/* exFAT: File system version (WORD) */
+#define BPB_VolFlagEx		106		/* exFAT: Volume flags (BYTE) */
+#define BPB_ActFatEx		107		/* exFAT: Active FAT flags (BYTE) */
+#define BPB_BytsPerSecEx	108		/* exFAT: Log2 of sector size in unit of byte (BYTE) */
+#define BPB_SecPerClusEx	109		/* exFAT: Log2 of cluster size in unit of sector (BYTE) */
+#define BPB_NumFATsEx		110		/* exFAT: Number of FATs (BYTE) */
+#define BPB_DrvNumEx		111		/* exFAT: Physical drive number for int13h (BYTE) */
+#define BPB_PercInUseEx		112		/* exFAT: Percent in use (BYTE) */
+#define	BPB_RsvdEx			113		/* exFAT: Reserved (7-byte) */
+#define BS_BootCodeEx		120		/* exFAT: Boot code (390-byte) */
+
+#define	DIR_Name			0		/* Short file name (11-byte) */
+#define	DIR_Attr			11		/* Attribute (BYTE) */
+#define	DIR_NTres			12		/* Lower case flag (BYTE) */
+#define DIR_CrtTime10		13		/* Created time sub-second (BYTE) */
+#define	DIR_CrtTime			14		/* Created time (DWORD) */
+#define DIR_LstAccDate		18		/* Last accessed date (WORD) */
+#define	DIR_FstClusHI		20		/* Higher 16-bit of first cluster (WORD) */
+#define	DIR_ModTime			22		/* Modified time (DWORD) */
+#define	DIR_FstClusLO		26		/* Lower 16-bit of first cluster (WORD) */
+#define	DIR_FileSize		28		/* File size (DWORD) */
+#define	LDIR_Ord			0		/* LFN: LFN order and LLE flag (BYTE) */
+#define	LDIR_Attr			11		/* LFN: LFN attribute (BYTE) */
+#define	LDIR_Type			12		/* LFN: Entry type (BYTE) */
+#define	LDIR_Chksum			13		/* LFN: Checksum of the SFN (BYTE) */
+#define	LDIR_FstClusLO		26		/* LFN: MBZ field (WORD) */
+#define	XDIR_Type			0		/* exFAT: Type of exFAT directory entry (BYTE) */
+#define	XDIR_NumLabel		1		/* exFAT: Number of volume label characters (BYTE) */
+#define	XDIR_Label			2		/* exFAT: Volume label (11-WORD) */
+#define	XDIR_CaseSum		4		/* exFAT: Sum of case conversion table (DWORD) */
+#define	XDIR_NumSec			1		/* exFAT: Number of secondary entries (BYTE) */
+#define	XDIR_SetSum			2		/* exFAT: Sum of the set of directory entries (WORD) */
+#define	XDIR_Attr			4		/* exFAT: File attribute (WORD) */
+#define	XDIR_CrtTime		8		/* exFAT: Created time (DWORD) */
+#define	XDIR_ModTime		12		/* exFAT: Modified time (DWORD) */
+#define	XDIR_AccTime		16		/* exFAT: Last accessed time (DWORD) */
+#define	XDIR_CrtTime10		20		/* exFAT: Created time subsecond (BYTE) */
+#define	XDIR_ModTime10		21		/* exFAT: Modified time subsecond (BYTE) */
+#define	XDIR_CrtTZ			22		/* exFAT: Created timezone (BYTE) */
+#define	XDIR_ModTZ			23		/* exFAT: Modified timezone (BYTE) */
+#define	XDIR_AccTZ			24		/* exFAT: Last accessed timezone (BYTE) */
+#define	XDIR_GenFlags		33		/* exFAT: General secondary flags (WORD) */
+#define	XDIR_NumName		35		/* exFAT: Number of file name characters (BYTE) */
+#define	XDIR_NameHash		36		/* exFAT: Hash of file name (WORD) */
+#define XDIR_ValidFileSize	40		/* exFAT: Valid file size (QWORD) */
+#define	XDIR_FstClus		52		/* exFAT: First cluster of the file data (DWORD) */
+#define	XDIR_FileSize		56		/* exFAT: File/Directory size (QWORD) */
+
+#define	SZDIRE				32		/* Size of a directory entry */
+#define	DDEM				0xE5	/* Deleted directory entry mark set to DIR_Name[0] */
+#define	RDDEM				0x05	/* Replacement of the character collides with DDEM */
+#define	LLEF				0x40	/* Last long entry flag in LDIR_Ord */
+
+#define	FSI_LeadSig			0		/* FAT32 FSI: Leading signature (DWORD) */
+#define	FSI_StrucSig		484		/* FAT32 FSI: Structure signature (DWORD) */
+#define	FSI_Free_Count		488		/* FAT32 FSI: Number of free clusters (DWORD) */
+#define	FSI_Nxt_Free		492		/* FAT32 FSI: Last allocated cluster (DWORD) */
+
+#define MBR_Table			446		/* MBR: Offset of partition table in the MBR */
+#define	SZ_PTE				16		/* MBR: Size of a partition table entry */
+#define PTE_Boot			0		/* MBR PTE: Boot indicator */
+#define PTE_StHead			1		/* MBR PTE: Start head */
+#define PTE_StSec			2		/* MBR PTE: Start sector */
+#define PTE_StCyl			3		/* MBR PTE: Start cylinder */
+#define PTE_System			4		/* MBR PTE: System ID */
+#define PTE_EdHead			5		/* MBR PTE: End head */
+#define PTE_EdSec			6		/* MBR PTE: End sector */
+#define PTE_EdCyl			7		/* MBR PTE: End cylinder */
+#define PTE_StLba			8		/* MBR PTE: Start in LBA */
+#define PTE_SizLba			12		/* MBR PTE: Size in LBA */
+
+
+/* Post process after fatal error on file operation */
+#define	ABORT(fs, res)		{ fp->err = (BYTE)(res); LEAVE_FF(fs, res); }
+
+
+/* Reentrancy related */
+#if _FS_REENTRANT
+#if _USE_LFN == 1
+#error Static LFN work area cannot be used at thread-safe configuration
+#endif
+#define	ENTER_FF(fs)		{ if (!lock_fs(fs)) return FR_TIMEOUT; }
+#define	LEAVE_FF(fs, res)	{ unlock_fs(fs, res); return res; }
+#else
+#define	ENTER_FF(fs)
+#define LEAVE_FF(fs, res)	return res
+#endif
+
+
+/* Definitions of volume - partition conversion */
+#if _MULTI_PARTITION
+#define LD2PD(vol) VolToPart[vol].pd	/* Get physical drive number */
+#define LD2PT(vol) VolToPart[vol].pt	/* Get partition index */
+#else
+#define LD2PD(vol) (BYTE)(vol)	/* Each logical drive is bound to the same physical drive number */
+#define LD2PT(vol) 0			/* Find first valid partition or in SFD */
+#endif
+
+
+/* Definitions of sector size */
+#if (_MAX_SS < _MIN_SS) || (_MAX_SS != 512 && _MAX_SS != 1024 && _MAX_SS != 2048 && _MAX_SS != 4096) || (_MIN_SS != 512 && _MIN_SS != 1024 && _MIN_SS != 2048 && _MIN_SS != 4096)
+#error Wrong sector size configuration
+#endif
+#if _MAX_SS == _MIN_SS
+#define	SS(fs)	((UINT)_MAX_SS)	/* Fixed sector size */
+#else
+#define	SS(fs)	((fs)->ssize)	/* Variable sector size */
+#endif
+
+
+/* Timestamp */
+#if _FS_NORTC == 1
+#if _NORTC_YEAR < 1980 || _NORTC_YEAR > 2107 || _NORTC_MON < 1 || _NORTC_MON > 12 || _NORTC_MDAY < 1 || _NORTC_MDAY > 31
+#error Invalid _FS_NORTC settings
+#endif
+#define GET_FATTIME()	((DWORD)(_NORTC_YEAR - 1980) << 25 | (DWORD)_NORTC_MON << 21 | (DWORD)_NORTC_MDAY << 16)
+#else
+#define GET_FATTIME()	get_fattime()
+#endif
+
+
+/* File lock controls */
+#if _FS_LOCK != 0
+#if _FS_READONLY
+#error _FS_LOCK must be 0 at read-only configuration
+#endif
+typedef struct {
+	FATFS *fs;		/* Object ID 1, volume (NULL:blank entry) */
+	DWORD clu;		/* Object ID 2, containing directory (0:root) */
+	DWORD ofs;		/* Object ID 3, offset in the directory */
+	WORD ctr;		/* Object open counter, 0:none, 0x01..0xFF:read mode open count, 0x100:write mode */
+} FILESEM;
+#endif
+
+
+
+
+
+/*--------------------------------------------------------------------------
+
+   Module Private Work Area
+
+---------------------------------------------------------------------------*/
+
+/* Remark: Variables defined here without initial value shall be guaranteed
+/  zero/null at start-up. If not, the linker option or start-up routine is
+/  not compliance with C standard. */
+
+#if _VOLUMES < 1 || _VOLUMES > 10
+#error Wrong _VOLUMES setting
+#endif
+static FATFS *FatFs[_VOLUMES];	/* Pointer to the file system objects (logical drives) */
+static WORD Fsid;				/* File system mount ID */
+
+#if _FS_RPATH != 0 && _VOLUMES >= 2
+static BYTE CurrVol;			/* Current drive */
+#endif
+
+#if _FS_LOCK != 0
+static FILESEM Files[_FS_LOCK];	/* Open object lock semaphores */
+#endif
+
+#if _USE_LFN == 0		/* Non-LFN configuration */
+#define	DEF_NAMBUF
+#define INIT_NAMBUF(fs)
+#define	FREE_NAMBUF()
+
+#else					/* LFN configuration */
+#if _MAX_LFN < 12 || _MAX_LFN > 255
+#error Wrong _MAX_LFN value
+#endif
+#define MAXDIRB(nc)	((nc + 44U) / 15 * SZDIRE)
+
+#if _USE_LFN == 1		/* LFN enabled with static working buffer */
+#if _FS_EXFAT
+static BYTE	DirBuf[MAXDIRB(_MAX_LFN)];	/* Directory entry block scratchpad buffer */
+#endif
+static WCHAR LfnBuf[_MAX_LFN + 1];	/* LFN enabled with static working buffer */
+#define	DEF_NAMBUF
+#define INIT_NAMBUF(fs)
+#define	FREE_NAMBUF()
+
+#elif _USE_LFN == 2 	/* LFN enabled with dynamic working buffer on the stack */
+#if _FS_EXFAT
+#define	DEF_NAMBUF		WCHAR lbuf[_MAX_LFN+1]; BYTE dbuf[MAXDIRB(_MAX_LFN)];
+#define INIT_NAMBUF(fs)	{ (fs)->lfnbuf = lbuf; (fs)->dirbuf = dbuf; }
+#define	FREE_NAMBUF()
+#else
+#define	DEF_NAMBUF		WCHAR lbuf[_MAX_LFN+1];
+#define INIT_NAMBUF(fs)	{ (fs)->lfnbuf = lbuf; }
+#define	FREE_NAMBUF()
+#endif
+
+#elif _USE_LFN == 3 	/* LFN enabled with dynamic working buffer on the heap */
+#if _FS_EXFAT
+#define	DEF_NAMBUF		WCHAR *lfn;
+#define INIT_NAMBUF(fs)	{ lfn = ff_memalloc((_MAX_LFN+1)*2 + MAXDIRB(_MAX_LFN)); if (!lfn) LEAVE_FF(fs, FR_NOT_ENOUGH_CORE); (fs)->lfnbuf = lfn; (fs)->dirbuf = (BYTE*)(lfn+_MAX_LFN+1); }
+#define	FREE_NAMBUF()	ff_memfree(lfn)
+#else
+#define	DEF_NAMBUF		WCHAR *lfn;
+#define INIT_NAMBUF(fs)	{ lfn = ff_memalloc((_MAX_LFN+1)*2); if (!lfn) LEAVE_FF(fs, FR_NOT_ENOUGH_CORE); (fs)->lfnbuf = lfn; }
+#define	FREE_NAMBUF()	ff_memfree(lfn)
+#endif
+
+#else
+#error Wrong _USE_LFN setting
+
+#endif
+#endif	/* else _USE_LFN == 0 */
+
+#ifdef _EXCVT
+static const BYTE ExCvt[] = _EXCVT;	/* Upper conversion table for SBCS extended characters */
+#endif
+
+
+
+
+
+
+/*--------------------------------------------------------------------------
+
+   Module Private Functions
+
+---------------------------------------------------------------------------*/
+
+
+/*-----------------------------------------------------------------------*/
+/* Load/Store multi-byte word in the FAT structure                       */
+/*-----------------------------------------------------------------------*/
+
+static
+WORD ld_word (const BYTE* ptr)	/*	 Load a 2-byte little-endian word */
+{
+	WORD rv;
+
+	rv = ptr[1];
+	rv = rv << 8 | ptr[0];
+	return rv;
+}
+
+static
+DWORD ld_dword (const BYTE* ptr)	/* Load a 4-byte little-endian word */
+{
+	DWORD rv;
+
+	rv = ptr[3];
+	rv = rv << 8 | ptr[2];
+	rv = rv << 8 | ptr[1];
+	rv = rv << 8 | ptr[0];
+	return rv;
+}
+
+#if _FS_EXFAT
+static
+QWORD ld_qword (const BYTE* ptr)	/* Load an 8-byte little-endian word */
+{
+	QWORD rv;
+
+	rv = ptr[7];
+	rv = rv << 8 | ptr[6];
+	rv = rv << 8 | ptr[5];
+	rv = rv << 8 | ptr[4];
+	rv = rv << 8 | ptr[3];
+	rv = rv << 8 | ptr[2];
+	rv = rv << 8 | ptr[1];
+	rv = rv << 8 | ptr[0];
+	return rv;
+}
+#endif
+
+#if !_FS_READONLY
+static
+void st_word (BYTE* ptr, WORD val)	/* Store a 2-byte word in little-endian */
+{
+	*ptr++ = (BYTE)val; val >>= 8;
+	*ptr++ = (BYTE)val;
+}
+
+static
+void st_dword (BYTE* ptr, DWORD val)	/* Store a 4-byte word in little-endian */
+{
+	*ptr++ = (BYTE)val; val >>= 8;
+	*ptr++ = (BYTE)val; val >>= 8;
+	*ptr++ = (BYTE)val; val >>= 8;
+	*ptr++ = (BYTE)val;
+}
+
+#if _FS_EXFAT
+static
+void st_qword (BYTE* ptr, QWORD val)	/* Store an 8-byte word in little-endian */
+{
+	*ptr++ = (BYTE)val; val >>= 8;
+	*ptr++ = (BYTE)val; val >>= 8;
+	*ptr++ = (BYTE)val; val >>= 8;
+	*ptr++ = (BYTE)val; val >>= 8;
+	*ptr++ = (BYTE)val; val >>= 8;
+	*ptr++ = (BYTE)val; val >>= 8;
+	*ptr++ = (BYTE)val; val >>= 8;
+	*ptr++ = (BYTE)val;
+}
+#endif
+#endif	/* !_FS_READONLY */
+
+
+
+/*-----------------------------------------------------------------------*/
+/* String functions                                                      */
+/*-----------------------------------------------------------------------*/
+
+/* Copy memory to memory */
+static
+void mem_cpy (void* dst, const void* src, UINT cnt) {
+	BYTE *d = (BYTE*)dst;
+	const BYTE *s = (const BYTE*)src;
+
+	if (cnt) {
+		do {
+			*d++ = *s++;
+		} while (--cnt);
+	}
+}
+
+/* Fill memory block */
+static
+void mem_set (void* dst, int val, UINT cnt) {
+	BYTE *d = (BYTE*)dst;
+
+	do {
+		*d++ = (BYTE)val;
+	} while (--cnt);
+}
+
+/* Compare memory block */
+static
+int mem_cmp (const void* dst, const void* src, UINT cnt) {	/* ZR:same, NZ:different */
+	const BYTE *d = (const BYTE *)dst, *s = (const BYTE *)src;
+	int r = 0;
+
+	do {
+		r = *d++ - *s++;
+	} while (--cnt && r == 0);
+
+	return r;
+}
+
+/* Check if chr is contained in the string */
+static
+int chk_chr (const char* str, int chr) {	/* NZ:contained, ZR:not contained */
+	while (*str && *str != chr) str++;
+	return *str;
+}
+
+
+
+
+#if _FS_REENTRANT
+/*-----------------------------------------------------------------------*/
+/* Request/Release grant to access the volume                            */
+/*-----------------------------------------------------------------------*/
+static
+int lock_fs (
+	FATFS* fs		/* File system object */
+)
+{
+	return (fs && ff_req_grant(fs->sobj)) ? 1 : 0;
+}
+
+
+static
+void unlock_fs (
+	FATFS* fs,		/* File system object */
+	FRESULT res		/* Result code to be returned */
+)
+{
+	if (fs && res != FR_NOT_ENABLED && res != FR_INVALID_DRIVE && res != FR_TIMEOUT) {
+		ff_rel_grant(fs->sobj);
+	}
+}
+
+#endif
+
+
+
+#if _FS_LOCK != 0
+/*-----------------------------------------------------------------------*/
+/* File lock control functions                                           */
+/*-----------------------------------------------------------------------*/
+
+static
+FRESULT chk_lock (	/* Check if the file can be accessed */
+	DIR* dp,		/* Directory object pointing the file to be checked */
+	int acc			/* Desired access type (0:Read, 1:Write, 2:Delete/Rename) */
+)
+{
+	UINT i, be;
+
+	/* Search file semaphore table */
+	for (i = be = 0; i < _FS_LOCK; i++) {
+		if (Files[i].fs) {	/* Existing entry */
+			if (Files[i].fs == dp->obj.fs &&	 	/* Check if the object matched with an open object */
+				Files[i].clu == dp->obj.sclust &&
+				Files[i].ofs == dp->dptr) break;
+		} else {			/* Blank entry */
+			be = 1;
+		}
+	}
+	if (i == _FS_LOCK) {	/* The object is not opened */
+		return (be || acc == 2) ? FR_OK : FR_TOO_MANY_OPEN_FILES;	/* Is there a blank entry for new object? */
+	}
+
+	/* The object has been opened. Reject any open against writing file and all write mode open */
+	return (acc || Files[i].ctr == 0x100) ? FR_LOCKED : FR_OK;
+}
+
+
+static
+int enq_lock (void)	/* Check if an entry is available for a new object */
+{
+	UINT i;
+
+	for (i = 0; i < _FS_LOCK && Files[i].fs; i++) ;
+	return (i == _FS_LOCK) ? 0 : 1;
+}
+
+
+static
+UINT inc_lock (	/* Increment object open counter and returns its index (0:Internal error) */
+	DIR* dp,	/* Directory object pointing the file to register or increment */
+	int acc		/* Desired access (0:Read, 1:Write, 2:Delete/Rename) */
+)
+{
+	UINT i;
+
+
+	for (i = 0; i < _FS_LOCK; i++) {	/* Find the object */
+		if (Files[i].fs == dp->obj.fs &&
+			Files[i].clu == dp->obj.sclust &&
+			Files[i].ofs == dp->dptr) break;
+	}
+
+	if (i == _FS_LOCK) {				/* Not opened. Register it as new. */
+		for (i = 0; i < _FS_LOCK && Files[i].fs; i++) ;
+		if (i == _FS_LOCK) return 0;	/* No free entry to register (int err) */
+		Files[i].fs = dp->obj.fs;
+		Files[i].clu = dp->obj.sclust;
+		Files[i].ofs = dp->dptr;
+		Files[i].ctr = 0;
+	}
+
+	if (acc && Files[i].ctr) return 0;	/* Access violation (int err) */
+
+	Files[i].ctr = acc ? 0x100 : Files[i].ctr + 1;	/* Set semaphore value */
+
+	return i + 1;
+}
+
+
+static
+FRESULT dec_lock (	/* Decrement object open counter */
+	UINT i			/* Semaphore index (1..) */
+)
+{
+	WORD n;
+	FRESULT res;
+
+
+	if (--i < _FS_LOCK) {	/* Shift index number origin from 0 */
+		n = Files[i].ctr;
+		if (n == 0x100) n = 0;		/* If write mode open, delete the entry */
+		if (n > 0) n--;				/* Decrement read mode open count */
+		Files[i].ctr = n;
+		if (n == 0) Files[i].fs = 0;	/* Delete the entry if open count gets zero */
+		res = FR_OK;
+	} else {
+		res = FR_INT_ERR;			/* Invalid index nunber */
+	}
+	return res;
+}
+
+
+static
+void clear_lock (	/* Clear lock entries of the volume */
+	FATFS *fs
+)
+{
+	UINT i;
+
+	for (i = 0; i < _FS_LOCK; i++) {
+		if (Files[i].fs == fs) Files[i].fs = 0;
+	}
+}
+
+#endif	/* _FS_LOCK != 0 */
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Move/Flush disk access window in the file system object               */
+/*-----------------------------------------------------------------------*/
+#if !_FS_READONLY
+static
+FRESULT sync_window (	/* Returns FR_OK or FR_DISK_ERROR */
+	FATFS* fs			/* File system object */
+)
+{
+	DWORD wsect;
+	UINT nf;
+	FRESULT res = FR_OK;
+
+
+	if (fs->wflag) {	/* Write back the sector if it is dirty */
+		wsect = fs->winsect;	/* Current sector number */
+		if (disk_write(fs->drv, fs->win, wsect, 1) != RES_OK) {
+			res = FR_DISK_ERR;
+		} else {
+			fs->wflag = 0;
+			if (wsect - fs->fatbase < fs->fsize) {		/* Is it in the FAT area? */
+				for (nf = fs->n_fats; nf >= 2; nf--) {	/* Reflect the change to all FAT copies */
+					wsect += fs->fsize;
+					disk_write(fs->drv, fs->win, wsect, 1);
+				}
+			}
+		}
+	}
+	return res;
+}
+#endif
+
+
+static
+FRESULT move_window (	/* Returns FR_OK or FR_DISK_ERROR */
+	FATFS* fs,			/* File system object */
+	DWORD sector		/* Sector number to make appearance in the fs->win[] */
+)
+{
+	FRESULT res = FR_OK;
+
+
+	if (sector != fs->winsect) {	/* Window offset changed? */
+#if !_FS_READONLY
+		res = sync_window(fs);		/* Write-back changes */
+#endif
+		if (res == FR_OK) {			/* Fill sector window with new data */
+			if (disk_read(fs->drv, fs->win, sector, 1) != RES_OK) {
+				sector = 0xFFFFFFFF;	/* Invalidate window if data is not reliable */
+				res = FR_DISK_ERR;
+			}
+			fs->winsect = sector;
+		}
+	}
+	return res;
+}
+
+
+
+
+#if !_FS_READONLY
+/*-----------------------------------------------------------------------*/
+/* Synchronize file system and strage device                             */
+/*-----------------------------------------------------------------------*/
+
+static
+FRESULT sync_fs (	/* FR_OK:succeeded, !=0:error */
+	FATFS* fs		/* File system object */
+)
+{
+	FRESULT res;
+
+
+	res = sync_window(fs);
+	if (res == FR_OK) {
+		/* Update FSInfo sector if needed */
+		if (fs->fs_type == FS_FAT32 && fs->fsi_flag == 1) {
+			/* Create FSInfo structure */
+			mem_set(fs->win, 0, SS(fs));
+			st_word(fs->win + BS_55AA, 0xAA55);
+			st_dword(fs->win + FSI_LeadSig, 0x41615252);
+			st_dword(fs->win + FSI_StrucSig, 0x61417272);
+			st_dword(fs->win + FSI_Free_Count, fs->free_clst);
+			st_dword(fs->win + FSI_Nxt_Free, fs->last_clst);
+			/* Write it into the FSInfo sector */
+			fs->winsect = fs->volbase + 1;
+			disk_write(fs->drv, fs->win, fs->winsect, 1);
+			fs->fsi_flag = 0;
+		}
+		/* Make sure that no pending write process in the physical drive */
+		if (disk_ioctl(fs->drv, CTRL_SYNC, 0) != RES_OK) res = FR_DISK_ERR;
+	}
+
+	return res;
+}
+
+#endif
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Get sector# from cluster#                                             */
+/*-----------------------------------------------------------------------*/
+
+static
+DWORD clust2sect (	/* !=0:Sector number, 0:Failed (invalid cluster#) */
+	FATFS* fs,		/* File system object */
+	DWORD clst		/* Cluster# to be converted */
+)
+{
+	clst -= 2;
+	if (clst >= fs->n_fatent - 2) return 0;		/* Invalid cluster# */
+	return clst * fs->csize + fs->database;
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* FAT access - Read value of a FAT entry                                */
+/*-----------------------------------------------------------------------*/
+
+static
+DWORD get_fat (	/* 0xFFFFFFFF:Disk error, 1:Internal error, 2..0x7FFFFFFF:Cluster status */
+	_FDID* obj,	/* Corresponding object */
+	DWORD clst	/* Cluster number to get the value */
+)
+{
+	UINT wc, bc;
+	DWORD val;
+	FATFS *fs = obj->fs;
+
+
+	if (clst < 2 || clst >= fs->n_fatent) {	/* Check if in valid range */
+		val = 1;	/* Internal error */
+
+	} else {
+		val = 0xFFFFFFFF;	/* Default value falls on disk error */
+
+		switch (fs->fs_type) {
+		case FS_FAT12 :
+			bc = (UINT)clst; bc += bc / 2;
+			if (move_window(fs, fs->fatbase + (bc / SS(fs))) != FR_OK) break;
+			wc = fs->win[bc++ % SS(fs)];
+			if (move_window(fs, fs->fatbase + (bc / SS(fs))) != FR_OK) break;
+			wc |= fs->win[bc % SS(fs)] << 8;
+			val = (clst & 1) ? (wc >> 4) : (wc & 0xFFF);
+			break;
+
+		case FS_FAT16 :
+			if (move_window(fs, fs->fatbase + (clst / (SS(fs) / 2))) != FR_OK) break;
+			val = ld_word(fs->win + clst * 2 % SS(fs));
+			break;
+
+		case FS_FAT32 :
+			if (move_window(fs, fs->fatbase + (clst / (SS(fs) / 4))) != FR_OK) break;
+			val = ld_dword(fs->win + clst * 4 % SS(fs)) & 0x0FFFFFFF;
+			break;
+#if _FS_EXFAT
+		case FS_EXFAT :
+			if (obj->objsize) {
+				DWORD cofs = clst - obj->sclust;	/* Offset from start cluster */
+				DWORD clen = (DWORD)((obj->objsize - 1) / SS(fs)) / fs->csize;	/* Number of clusters - 1 */
+
+				if (obj->stat == 2) {	/* Is there no valid chain on the FAT? */
+					if (cofs <= clen) {
+						val = (cofs == clen) ? 0x7FFFFFFF : clst + 1;	/* Generate the value */
+						break;
+					}
+				}
+				if (obj->stat == 3 && cofs < obj->n_cont) {	/* Is it in the 1st fragment? */
+					val = clst + 1; 	/* Generate the value */
+					break;
+				}
+				if (obj->stat != 2) {	/* Get value from FAT if FAT chain is valid */
+					if (obj->n_frag != 0) {	/* Is it on the growing edge? */
+						val = 0x7FFFFFFF;	/* Generate EOC */
+					} else {
+						if (move_window(fs, fs->fatbase + (clst / (SS(fs) / 4))) != FR_OK) break;
+						val = ld_dword(fs->win + clst * 4 % SS(fs)) & 0x7FFFFFFF;
+					}
+					break;
+				}
+			}
+			/* go to default */
+#endif
+		default:
+			val = 1;	/* Internal error */
+		}
+	}
+
+	return val;
+}
+
+
+
+
+#if !_FS_READONLY
+/*-----------------------------------------------------------------------*/
+/* FAT access - Change value of a FAT entry                              */
+/*-----------------------------------------------------------------------*/
+
+static
+FRESULT put_fat (	/* FR_OK(0):succeeded, !=0:error */
+	FATFS* fs,		/* Corresponding file system object */
+	DWORD clst,		/* FAT index number (cluster number) to be changed */
+	DWORD val		/* New value to be set to the entry */
+)
+{
+	UINT bc;
+	BYTE *p;
+	FRESULT res = FR_INT_ERR;
+
+	if (clst >= 2 && clst < fs->n_fatent) {	/* Check if in valid range */
+		switch (fs->fs_type) {
+		case FS_FAT12 :	/* Bitfield items */
+			bc = (UINT)clst; bc += bc / 2;
+			res = move_window(fs, fs->fatbase + (bc / SS(fs)));
+			if (res != FR_OK) break;
+			p = fs->win + bc++ % SS(fs);
+			*p = (clst & 1) ? ((*p & 0x0F) | ((BYTE)val << 4)) : (BYTE)val;
+			fs->wflag = 1;
+			res = move_window(fs, fs->fatbase + (bc / SS(fs)));
+			if (res != FR_OK) break;
+			p = fs->win + bc % SS(fs);
+			*p = (clst & 1) ? (BYTE)(val >> 4) : ((*p & 0xF0) | ((BYTE)(val >> 8) & 0x0F));
+			fs->wflag = 1;
+			break;
+
+		case FS_FAT16 :	/* WORD aligned items */
+			res = move_window(fs, fs->fatbase + (clst / (SS(fs) / 2)));
+			if (res != FR_OK) break;
+			st_word(fs->win + clst * 2 % SS(fs), (WORD)val);
+			fs->wflag = 1;
+			break;
+
+		case FS_FAT32 :	/* DWORD aligned items */
+#if _FS_EXFAT
+		case FS_EXFAT :
+#endif
+			res = move_window(fs, fs->fatbase + (clst / (SS(fs) / 4)));
+			if (res != FR_OK) break;
+			if (!_FS_EXFAT || fs->fs_type != FS_EXFAT) {
+				val = (val & 0x0FFFFFFF) | (ld_dword(fs->win + clst * 4 % SS(fs)) & 0xF0000000);
+			}
+			st_dword(fs->win + clst * 4 % SS(fs), val);
+			fs->wflag = 1;
+			break;
+		}
+	}
+	return res;
+}
+
+#endif /* !_FS_READONLY */
+
+
+
+
+#if _FS_EXFAT && !_FS_READONLY
+/*-----------------------------------------------------------------------*/
+/* exFAT: Accessing FAT and Allocation Bitmap                            */
+/*-----------------------------------------------------------------------*/
+
+/*--------------------------------------*/
+/* Find a contiguous free cluster block */
+/*--------------------------------------*/
+
+static
+DWORD find_bitmap (	/* 0:Not found, 2..:Cluster block found, 0xFFFFFFFF:Disk error */
+	FATFS* fs,	/* File system object */
+	DWORD clst,	/* Cluster number to scan from */
+	DWORD ncl	/* Number of contiguous clusters to find (1..) */
+)
+{
+	BYTE bm, bv;
+	UINT i;
+	DWORD val, scl, ctr;
+
+
+	clst -= 2;	/* The first bit in the bitmap corresponds to cluster #2 */
+	if (clst >= fs->n_fatent - 2) clst = 0;
+	scl = val = clst; ctr = 0;
+	for (;;) {
+		if (move_window(fs, fs->database + val / 8 / SS(fs)) != FR_OK) return 0xFFFFFFFF;	/* (assuming bitmap is located top of the cluster heap) */
+		i = val / 8 % SS(fs); bm = 1 << (val % 8);
+		do {
+			do {
+				bv = fs->win[i] & bm; bm <<= 1;		/* Get bit value */
+				if (++val >= fs->n_fatent - 2) {	/* Next cluster (with wrap-around) */
+					val = 0; bm = 0; i = SS(fs);
+				}
+				if (!bv) {	/* Is it a free cluster? */
+					if (++ctr == ncl) return scl + 2;	/* Check if run length is sufficient for required */
+				} else {
+					scl = val; ctr = 0;		/* Encountered a cluster in-use, restart to scan */
+				}
+				if (val == clst) return 0;	/* All cluster scanned? */
+			} while (bm);
+			bm = 1;
+		} while (++i < SS(fs));
+	}
+}
+
+
+/*----------------------------------------*/
+/* Set/Clear a block of allocation bitmap */
+/*----------------------------------------*/
+
+static
+FRESULT change_bitmap (
+	FATFS* fs,	/* File system object */
+	DWORD clst,	/* Cluster number to change from */
+	DWORD ncl,	/* Number of clusters to be changed */
+	int bv		/* bit value to be set (0 or 1) */
+)
+{
+	BYTE bm;
+	UINT i;
+	DWORD sect;
+
+	clst -= 2;	/* The first bit corresponds to cluster #2 */
+	sect = fs->database + clst / 8 / SS(fs);	/* Sector address (assuming bitmap is located top of the cluster heap) */
+	i = clst / 8 % SS(fs);						/* Byte offset in the sector */
+	bm = 1 << (clst % 8);						/* Bit mask in the byte */
+	for (;;) {
+		if (move_window(fs, sect++) != FR_OK) return FR_DISK_ERR;
+		do {
+			do {
+				if (bv == (int)((fs->win[i] & bm) != 0)) return FR_INT_ERR;	/* Is the bit expected value? */
+				fs->win[i] ^= bm;	/* Flip the bit */
+				fs->wflag = 1;
+				if (--ncl == 0) return FR_OK;	/* All bits processed? */
+			} while (bm <<= 1);		/* Next bit */
+			bm = 1;
+		} while (++i < SS(fs));		/* Next byte */
+		i = 0;
+	}
+}
+
+
+/*---------------------------------------------*/
+/* Fill the first fragment of the FAT chain    */
+/*---------------------------------------------*/
+
+static
+FRESULT fill_first_frag (
+	_FDID* obj	/* Pointer to the corresponding object */
+)
+{
+	FRESULT res;
+	DWORD cl, n;
+
+	if (obj->stat == 3) {	/* Has the object been changed 'fragmented'? */
+		for (cl = obj->sclust, n = obj->n_cont; n; cl++, n--) {	/* Create cluster chain on the FAT */
+			res = put_fat(obj->fs, cl, cl + 1);
+			if (res != FR_OK) return res;
+		}
+		obj->stat = 0;	/* Change status 'FAT chain is valid' */
+	}
+	return FR_OK;
+}
+
+
+/*---------------------------------------------*/
+/* Fill the last fragment of the FAT chain     */
+/*---------------------------------------------*/
+
+static
+FRESULT fill_last_frag (
+	_FDID* obj,	/* Pointer to the corresponding object */
+	DWORD lcl,	/* Last cluster of the fragment */
+	DWORD term	/* Value to set the last FAT entry */
+)
+{
+	FRESULT res;
+
+	while (obj->n_frag > 0) {	/* Create the last chain on the FAT */
+		res = put_fat(obj->fs, lcl - obj->n_frag + 1, (obj->n_frag > 1) ? lcl - obj->n_frag + 2 : term);
+		if (res != FR_OK) return res;
+		obj->n_frag--;
+	}
+	return FR_OK;
+}
+
+#endif	/* _FS_EXFAT && !_FS_READONLY */
+
+
+
+#if !_FS_READONLY
+/*-----------------------------------------------------------------------*/
+/* FAT handling - Remove a cluster chain                                 */
+/*-----------------------------------------------------------------------*/
+static
+FRESULT remove_chain (	/* FR_OK(0):succeeded, !=0:error */
+	_FDID* obj,			/* Corresponding object */
+	DWORD clst,			/* Cluster to remove a chain from */
+	DWORD pclst			/* Previous cluster of clst (0:an entire chain) */
+)
+{
+	FRESULT res = FR_OK;
+	DWORD nxt;
+	FATFS *fs = obj->fs;
+#if _FS_EXFAT || _USE_TRIM
+	DWORD scl = clst, ecl = clst;
+#endif
+#if _USE_TRIM
+	DWORD rt[2];
+#endif
+
+	if (clst < 2 || clst >= fs->n_fatent) return FR_INT_ERR;	/* Check if in valid range */
+
+	/* Mark the previous cluster 'EOC' on the FAT if it exists */
+	if (pclst && (!_FS_EXFAT || fs->fs_type != FS_EXFAT || obj->stat != 2)) {
+		res = put_fat(fs, pclst, 0xFFFFFFFF);
+		if (res != FR_OK) return res;
+	}
+
+	/* Remove the chain */
+	do {
+		nxt = get_fat(obj, clst);			/* Get cluster status */
+		if (nxt == 0) break;				/* Empty cluster? */
+		if (nxt == 1) return FR_INT_ERR;	/* Internal error? */
+		if (nxt == 0xFFFFFFFF) return FR_DISK_ERR;	/* Disk error? */
+		if (!_FS_EXFAT || fs->fs_type != FS_EXFAT) {
+			res = put_fat(fs, clst, 0);		/* Mark the cluster 'free' on the FAT */
+			if (res != FR_OK) return res;
+		}
+		if (fs->free_clst < fs->n_fatent - 2) {	/* Update FSINFO */
+			fs->free_clst++;
+			fs->fsi_flag |= 1;
+		}
+#if _FS_EXFAT || _USE_TRIM
+		if (ecl + 1 == nxt) {	/* Is next cluster contiguous? */
+			ecl = nxt;
+		} else {				/* End of contiguous cluster block */
+#if _FS_EXFAT
+			if (fs->fs_type == FS_EXFAT) {
+				res = change_bitmap(fs, scl, ecl - scl + 1, 0);	/* Mark the cluster block 'free' on the bitmap */
+				if (res != FR_OK) return res;
+			}
+#endif
+#if _USE_TRIM
+			rt[0] = clust2sect(fs, scl);					/* Start sector */
+			rt[1] = clust2sect(fs, ecl) + fs->csize - 1;	/* End sector */
+			disk_ioctl(fs->drv, CTRL_TRIM, rt);				/* Inform device the block can be erased */
+#endif
+			scl = ecl = nxt;
+		}
+#endif
+		clst = nxt;					/* Next cluster */
+	} while (clst < fs->n_fatent);	/* Repeat while not the last link */
+
+#if _FS_EXFAT
+	if (fs->fs_type == FS_EXFAT) {
+		if (pclst == 0) {	/* Does the object have no chain? */
+			obj->stat = 0;		/* Change the object status 'initial' */
+		} else {
+			if (obj->stat == 3 && pclst >= obj->sclust && pclst <= obj->sclust + obj->n_cont) {	/* Did the chain get contiguous? */
+				obj->stat = 2;	/* Change the object status 'contiguous' */
+			}
+		}
+	}
+#endif
+	return FR_OK;
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* FAT handling - Stretch a chain or Create a new chain                  */
+/*-----------------------------------------------------------------------*/
+static
+DWORD create_chain (	/* 0:No free cluster, 1:Internal error, 0xFFFFFFFF:Disk error, >=2:New cluster# */
+	_FDID* obj,			/* Corresponding object */
+	DWORD clst			/* Cluster# to stretch, 0:Create a new chain */
+)
+{
+	DWORD cs, ncl, scl;
+	FRESULT res;
+	FATFS *fs = obj->fs;
+
+
+	if (clst == 0) {	/* Create a new chain */
+		scl = fs->last_clst;				/* Get suggested cluster to start from */
+		if (scl == 0 || scl >= fs->n_fatent) scl = 1;
+	}
+	else {				/* Stretch current chain */
+		cs = get_fat(obj, clst);			/* Check the cluster status */
+		if (cs < 2) return 1;				/* Invalid FAT value */
+		if (cs == 0xFFFFFFFF) return cs;	/* A disk error occurred */
+		if (cs < fs->n_fatent) return cs;	/* It is already followed by next cluster */
+		scl = clst;
+	}
+
+#if _FS_EXFAT
+	if (fs->fs_type == FS_EXFAT) {	/* On the exFAT volume */
+		ncl = find_bitmap(fs, scl, 1);				/* Find a free cluster */
+		if (ncl == 0 || ncl == 0xFFFFFFFF) return ncl;	/* No free cluster or hard error? */
+		res = change_bitmap(fs, ncl, 1, 1);			/* Mark the cluster 'in use' */
+		if (res == FR_INT_ERR) return 1;
+		if (res == FR_DISK_ERR) return 0xFFFFFFFF;
+		if (clst == 0) {							/* Is it a new chain? */
+			obj->stat = 2;							/* Set status 'contiguous' */
+		} else {									/* It is a stretched chain */
+			if (obj->stat == 2 && ncl != scl + 1) {	/* Is the chain got fragmented? */
+				obj->n_cont = scl - obj->sclust;	/* Set size of the contiguous part */
+				obj->stat = 3;						/* Change status 'just fragmented' */
+			}
+		}
+		if (obj->stat != 2) {	/* Is the file non-contiguous? */
+			if (ncl == clst + 1) {	/* Is the cluster next to previous one? */
+				obj->n_frag = obj->n_frag ? obj->n_frag + 1 : 2;	/* Increment size of last framgent */
+			} else {				/* New fragment */
+				if (obj->n_frag == 0) obj->n_frag = 1;
+				res = fill_last_frag(obj, clst, ncl);	/* Fill last fragment on the FAT and link it to new one */
+				if (res == FR_OK) obj->n_frag = 1;
+			}
+		}
+	} else
+#endif
+	{	/* On the FAT12/16/32 volume */
+		ncl = scl;	/* Start cluster */
+		for (;;) {
+			ncl++;							/* Next cluster */
+			if (ncl >= fs->n_fatent) {		/* Check wrap-around */
+				ncl = 2;
+				if (ncl > scl) return 0;	/* No free cluster */
+			}
+			cs = get_fat(obj, ncl);			/* Get the cluster status */
+			if (cs == 0) break;				/* Found a free cluster */
+			if (cs == 1 || cs == 0xFFFFFFFF) return cs;	/* An error occurred */
+			if (ncl == scl) return 0;		/* No free cluster */
+		}
+		res = put_fat(fs, ncl, 0xFFFFFFFF);	/* Mark the new cluster 'EOC' */
+		if (res == FR_OK && clst != 0) {
+			res = put_fat(fs, clst, ncl);	/* Link it from the previous one if needed */
+		}
+	}
+
+	if (res == FR_OK) {			/* Update FSINFO if function succeeded. */
+		fs->last_clst = ncl;
+		if (fs->free_clst <= fs->n_fatent - 2) fs->free_clst--;
+		fs->fsi_flag |= 1;
+	} else {
+		ncl = (res == FR_DISK_ERR) ? 0xFFFFFFFF : 1;	/* Failed. Generate error status */
+	}
+
+	return ncl;		/* Return new cluster number or error status */
+}
+
+#endif /* !_FS_READONLY */
+
+
+
+
+#if _USE_FASTSEEK
+/*-----------------------------------------------------------------------*/
+/* FAT handling - Convert offset into cluster with link map table        */
+/*-----------------------------------------------------------------------*/
+
+static
+DWORD clmt_clust (	/* <2:Error, >=2:Cluster number */
+	FIL* fp,		/* Pointer to the file object */
+	FSIZE_t ofs		/* File offset to be converted to cluster# */
+)
+{
+	DWORD cl, ncl, *tbl;
+	FATFS *fs = fp->obj.fs;
+
+
+	tbl = fp->cltbl + 1;	/* Top of CLMT */
+	cl = (DWORD)(ofs / SS(fs) / fs->csize);	/* Cluster order from top of the file */
+	for (;;) {
+		ncl = *tbl++;			/* Number of cluters in the fragment */
+		if (ncl == 0) return 0;	/* End of table? (error) */
+		if (cl < ncl) break;	/* In this fragment? */
+		cl -= ncl; tbl++;		/* Next fragment */
+	}
+	return cl + *tbl;	/* Return the cluster number */
+}
+
+#endif	/* _USE_FASTSEEK */
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Directory handling - Set directory index                              */
+/*-----------------------------------------------------------------------*/
+
+static
+FRESULT dir_sdi (	/* FR_OK(0):succeeded, !=0:error */
+	DIR* dp,		/* Pointer to directory object */
+	DWORD ofs		/* Offset of directory table */
+)
+{
+	DWORD csz, clst;
+	FATFS *fs = dp->obj.fs;
+
+
+	if (ofs >= (DWORD)((_FS_EXFAT && fs->fs_type == FS_EXFAT) ? MAX_DIR_EX : MAX_DIR) || ofs % SZDIRE) {	/* Check range of offset and alignment */
+		return FR_INT_ERR;
+	}
+	dp->dptr = ofs;				/* Set current offset */
+	clst = dp->obj.sclust;		/* Table start cluster (0:root) */
+	if (clst == 0 && fs->fs_type >= FS_FAT32) {	/* Replace cluster# 0 with root cluster# */
+		clst = fs->dirbase;
+		if (_FS_EXFAT) dp->obj.stat = 0;	/* exFAT: Root dir has an FAT chain */
+	}
+
+	if (clst == 0) {	/* Static table (root-directory in FAT12/16) */
+		if (ofs / SZDIRE >= fs->n_rootdir)	return FR_INT_ERR;	/* Is index out of range? */
+		dp->sect = fs->dirbase;
+
+	} else {			/* Dynamic table (sub-directory or root-directory in FAT32+) */
+		csz = (DWORD)fs->csize * SS(fs);	/* Bytes per cluster */
+		while (ofs >= csz) {				/* Follow cluster chain */
+			clst = get_fat(&dp->obj, clst);				/* Get next cluster */
+			if (clst == 0xFFFFFFFF) return FR_DISK_ERR;	/* Disk error */
+			if (clst < 2 || clst >= fs->n_fatent) return FR_INT_ERR;	/* Reached to end of table or internal error */
+			ofs -= csz;
+		}
+		dp->sect = clust2sect(fs, clst);
+	}
+	dp->clust = clst;					/* Current cluster# */
+	if (!dp->sect) return FR_INT_ERR;
+	dp->sect += ofs / SS(fs);			/* Sector# of the directory entry */
+	dp->dir = fs->win + (ofs % SS(fs));	/* Pointer to the entry in the win[] */
+
+	return FR_OK;
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Directory handling - Move directory table index next                  */
+/*-----------------------------------------------------------------------*/
+
+static
+FRESULT dir_next (	/* FR_OK(0):succeeded, FR_NO_FILE:End of table, FR_DENIED:Could not stretch */
+	DIR* dp,		/* Pointer to the directory object */
+	int stretch		/* 0: Do not stretch table, 1: Stretch table if needed */
+)
+{
+	DWORD ofs, clst;
+	FATFS *fs = dp->obj.fs;
+#if !_FS_READONLY
+	UINT n;
+#endif
+
+	ofs = dp->dptr + SZDIRE;	/* Next entry */
+	if (!dp->sect || ofs >= (DWORD)((_FS_EXFAT && fs->fs_type == FS_EXFAT) ? MAX_DIR_EX : MAX_DIR)) return FR_NO_FILE;	/* Report EOT when offset has reached max value */
+
+	if (ofs % SS(fs) == 0) {	/* Sector changed? */
+		dp->sect++;				/* Next sector */
+
+		if (!dp->clust) {		/* Static table */
+			if (ofs / SZDIRE >= fs->n_rootdir) {	/* Report EOT if it reached end of static table */
+				dp->sect = 0; return FR_NO_FILE;
+			}
+		}
+		else {					/* Dynamic table */
+			if ((ofs / SS(fs) & (fs->csize - 1)) == 0) {		/* Cluster changed? */
+				clst = get_fat(&dp->obj, dp->clust);			/* Get next cluster */
+				if (clst <= 1) return FR_INT_ERR;				/* Internal error */
+				if (clst == 0xFFFFFFFF) return FR_DISK_ERR;		/* Disk error */
+				if (clst >= fs->n_fatent) {						/* Reached end of dynamic table */
+#if !_FS_READONLY
+					if (!stretch) {								/* If no stretch, report EOT */
+						dp->sect = 0; return FR_NO_FILE;
+					}
+					clst = create_chain(&dp->obj, dp->clust);	/* Allocate a cluster */
+					if (clst == 0) return FR_DENIED;			/* No free cluster */
+					if (clst == 1) return FR_INT_ERR;			/* Internal error */
+					if (clst == 0xFFFFFFFF) return FR_DISK_ERR;	/* Disk error */
+					/* Clean-up the stretched table */
+					if (_FS_EXFAT) dp->obj.stat |= 4;			/* The directory needs to be updated */
+					if (sync_window(fs) != FR_OK) return FR_DISK_ERR;	/* Flush disk access window */
+					mem_set(fs->win, 0, SS(fs));				/* Clear window buffer */
+					for (n = 0, fs->winsect = clust2sect(fs, clst); n < fs->csize; n++, fs->winsect++) {	/* Fill the new cluster with 0 */
+						fs->wflag = 1;
+						if (sync_window(fs) != FR_OK) return FR_DISK_ERR;
+					}
+					fs->winsect -= n;							/* Restore window offset */
+#else
+					if (!stretch) dp->sect = 0;					/* (this line is to suppress compiler warning) */
+					dp->sect = 0; return FR_NO_FILE;			/* Report EOT */
+#endif
+				}
+				dp->clust = clst;		/* Initialize data for new cluster */
+				dp->sect = clust2sect(fs, clst);
+			}
+		}
+	}
+	dp->dptr = ofs;						/* Current entry */
+	dp->dir = fs->win + ofs % SS(fs);	/* Pointer to the entry in the win[] */
+
+	return FR_OK;
+}
+
+
+
+
+#if !_FS_READONLY
+/*-----------------------------------------------------------------------*/
+/* Directory handling - Reserve a block of directory entries             */
+/*-----------------------------------------------------------------------*/
+
+static
+FRESULT dir_alloc (	/* FR_OK(0):succeeded, !=0:error */
+	DIR* dp,		/* Pointer to the directory object */
+	UINT nent		/* Number of contiguous entries to allocate */
+)
+{
+	FRESULT res;
+	UINT n;
+	FATFS *fs = dp->obj.fs;
+
+
+	res = dir_sdi(dp, 0);
+	if (res == FR_OK) {
+		n = 0;
+		do {
+			res = move_window(fs, dp->sect);
+			if (res != FR_OK) break;
+#if _FS_EXFAT
+			if ((fs->fs_type == FS_EXFAT) ? (int)((dp->dir[XDIR_Type] & 0x80) == 0) : (int)(dp->dir[DIR_Name] == DDEM || dp->dir[DIR_Name] == 0)) {
+#else
+			if (dp->dir[DIR_Name] == DDEM || dp->dir[DIR_Name] == 0) {
+#endif
+				if (++n == nent) break;	/* A block of contiguous free entries is found */
+			} else {
+				n = 0;					/* Not a blank entry. Restart to search */
+			}
+			res = dir_next(dp, 1);
+		} while (res == FR_OK);	/* Next entry with table stretch enabled */
+	}
+
+	if (res == FR_NO_FILE) res = FR_DENIED;	/* No directory entry to allocate */
+	return res;
+}
+
+#endif	/* !_FS_READONLY */
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* FAT: Directory handling - Load/Store start cluster number             */
+/*-----------------------------------------------------------------------*/
+
+static
+DWORD ld_clust (	/* Returns the top cluster value of the SFN entry */
+	FATFS* fs,		/* Pointer to the fs object */
+	const BYTE* dir	/* Pointer to the key entry */
+)
+{
+	DWORD cl;
+
+	cl = ld_word(dir + DIR_FstClusLO);
+	if (fs->fs_type == FS_FAT32) {
+		cl |= (DWORD)ld_word(dir + DIR_FstClusHI) << 16;
+	}
+
+	return cl;
+}
+
+
+#if !_FS_READONLY
+static
+void st_clust (
+	FATFS* fs,	/* Pointer to the fs object */
+	BYTE* dir,	/* Pointer to the key entry */
+	DWORD cl	/* Value to be set */
+)
+{
+	st_word(dir + DIR_FstClusLO, (WORD)cl);
+	if (fs->fs_type == FS_FAT32) {
+		st_word(dir + DIR_FstClusHI, (WORD)(cl >> 16));
+	}
+}
+#endif
+
+
+
+#if _USE_LFN != 0
+/*------------------------------------------------------------------------*/
+/* FAT-LFN: LFN handling                                                  */
+/*------------------------------------------------------------------------*/
+static
+const BYTE LfnOfs[] = {1,3,5,7,9,14,16,18,20,22,24,28,30};	/* Offset of LFN characters in the directory entry */
+
+
+/*--------------------------------------------------------*/
+/* FAT-LFN: Compare a part of file name with an LFN entry */
+/*--------------------------------------------------------*/
+static
+int cmp_lfn (				/* 1:matched, 0:not matched */
+	const WCHAR* lfnbuf,	/* Pointer to the LFN working buffer to be compared */
+	BYTE* dir				/* Pointer to the directory entry containing the part of LFN */
+)
+{
+	UINT i, s;
+	WCHAR wc, uc;
+
+
+	if (ld_word(dir + LDIR_FstClusLO) != 0) return 0;	/* Check LDIR_FstClusLO */
+
+	i = ((dir[LDIR_Ord] & 0x3F) - 1) * 13;	/* Offset in the LFN buffer */
+
+	for (wc = 1, s = 0; s < 13; s++) {		/* Process all characters in the entry */
+		uc = ld_word(dir + LfnOfs[s]);		/* Pick an LFN character */
+		if (wc) {
+			if (i >= _MAX_LFN || ff_wtoupper(uc) != ff_wtoupper(lfnbuf[i++])) {	/* Compare it */
+				return 0;					/* Not matched */
+			}
+			wc = uc;
+		} else {
+			if (uc != 0xFFFF) return 0;		/* Check filler */
+		}
+	}
+
+	if ((dir[LDIR_Ord] & LLEF) && wc && lfnbuf[i]) return 0;	/* Last segment matched but different length */
+
+	return 1;		/* The part of LFN matched */
+}
+
+
+#if _FS_MINIMIZE <= 1 || _FS_RPATH >= 2 || _USE_LABEL || _FS_EXFAT
+/*-----------------------------------------------------*/
+/* FAT-LFN: Pick a part of file name from an LFN entry */
+/*-----------------------------------------------------*/
+static
+int pick_lfn (			/* 1:succeeded, 0:buffer overflow or invalid LFN entry */
+	WCHAR* lfnbuf,		/* Pointer to the LFN working buffer */
+	BYTE* dir			/* Pointer to the LFN entry */
+)
+{
+	UINT i, s;
+	WCHAR wc, uc;
+
+
+	if (ld_word(dir + LDIR_FstClusLO) != 0) return 0;	/* Check LDIR_FstClusLO is 0 */
+
+	i = ((dir[LDIR_Ord] & ~LLEF) - 1) * 13;	/* Offset in the LFN buffer */
+
+	for (wc = 1, s = 0; s < 13; s++) {		/* Process all characters in the entry */
+		uc = ld_word(dir + LfnOfs[s]);		/* Pick an LFN character */
+		if (wc) {
+			if (i >= _MAX_LFN) return 0;	/* Buffer overflow? */
+			lfnbuf[i++] = wc = uc;			/* Store it */
+		} else {
+			if (uc != 0xFFFF) return 0;		/* Check filler */
+		}
+	}
+
+	if (dir[LDIR_Ord] & LLEF) {				/* Put terminator if it is the last LFN part */
+		if (i >= _MAX_LFN) return 0;		/* Buffer overflow? */
+		lfnbuf[i] = 0;
+	}
+
+	return 1;		/* The part of LFN is valid */
+}
+#endif
+
+
+#if !_FS_READONLY
+/*-----------------------------------------*/
+/* FAT-LFN: Create an entry of LFN entries */
+/*-----------------------------------------*/
+static
+void put_lfn (
+	const WCHAR* lfn,	/* Pointer to the LFN */
+	BYTE* dir,			/* Pointer to the LFN entry to be created */
+	BYTE ord,			/* LFN order (1-20) */
+	BYTE sum			/* Checksum of the corresponding SFN */
+)
+{
+	UINT i, s;
+	WCHAR wc;
+
+
+	dir[LDIR_Chksum] = sum;			/* Set checksum */
+	dir[LDIR_Attr] = AM_LFN;		/* Set attribute. LFN entry */
+	dir[LDIR_Type] = 0;
+	st_word(dir + LDIR_FstClusLO, 0);
+
+	i = (ord - 1) * 13;				/* Get offset in the LFN working buffer */
+	s = wc = 0;
+	do {
+		if (wc != 0xFFFF) wc = lfn[i++];	/* Get an effective character */
+		st_word(dir + LfnOfs[s], wc);		/* Put it */
+		if (wc == 0) wc = 0xFFFF;		/* Padding characters for left locations */
+	} while (++s < 13);
+	if (wc == 0xFFFF || !lfn[i]) ord |= LLEF;	/* Last LFN part is the start of LFN sequence */
+	dir[LDIR_Ord] = ord;			/* Set the LFN order */
+}
+
+#endif	/* !_FS_READONLY */
+#endif	/* _USE_LFN != 0 */
+
+
+
+#if _USE_LFN != 0 && !_FS_READONLY
+/*-----------------------------------------------------------------------*/
+/* FAT-LFN: Create a Numbered SFN                                        */
+/*-----------------------------------------------------------------------*/
+
+static
+void gen_numname (
+	BYTE* dst,			/* Pointer to the buffer to store numbered SFN */
+	const BYTE* src,	/* Pointer to SFN */
+	const WCHAR* lfn,	/* Pointer to LFN */
+	UINT seq			/* Sequence number */
+)
+{
+	BYTE ns[8], c;
+	UINT i, j;
+	WCHAR wc;
+	DWORD sr;
+
+
+	mem_cpy(dst, src, 11);
+
+	if (seq > 5) {	/* In case of many collisions, generate a hash number instead of sequential number */
+		sr = seq;
+		while (*lfn) {	/* Create a CRC */
+			wc = *lfn++;
+			for (i = 0; i < 16; i++) {
+				sr = (sr << 1) + (wc & 1);
+				wc >>= 1;
+				if (sr & 0x10000) sr ^= 0x11021;
+			}
+		}
+		seq = (UINT)sr;
+	}
+
+	/* itoa (hexdecimal) */
+	i = 7;
+	do {
+		c = (BYTE)((seq % 16) + '0');
+		if (c > '9') c += 7;
+		ns[i--] = c;
+		seq /= 16;
+	} while (seq);
+	ns[i] = '~';
+
+	/* Append the number */
+	for (j = 0; j < i && dst[j] != ' '; j++) {
+		if (IsDBCS1(dst[j])) {
+			if (j == i - 1) break;
+			j++;
+		}
+	}
+	do {
+		dst[j++] = (i < 8) ? ns[i++] : ' ';
+	} while (j < 8);
+}
+#endif	/* _USE_LFN != 0 && !_FS_READONLY */
+
+
+
+#if _USE_LFN != 0
+/*-----------------------------------------------------------------------*/
+/* FAT-LFN: Calculate checksum of an SFN entry                           */
+/*-----------------------------------------------------------------------*/
+
+static
+BYTE sum_sfn (
+	const BYTE* dir		/* Pointer to the SFN entry */
+)
+{
+	BYTE sum = 0;
+	UINT n = 11;
+
+	do {
+		sum = (sum >> 1) + (sum << 7) + *dir++;
+	} while (--n);
+	return sum;
+}
+
+#endif	/* _USE_LFN != 0 */
+
+
+
+#if _FS_EXFAT
+/*-----------------------------------------------------------------------*/
+/* exFAT: Checksum                                                       */
+/*-----------------------------------------------------------------------*/
+
+static
+WORD xdir_sum (			/* Get checksum of the directoly block */
+	const BYTE* dir		/* Directory entry block to be calculated */
+)
+{
+	UINT i, szblk;
+	WORD sum;
+
+
+	szblk = (dir[XDIR_NumSec] + 1) * SZDIRE;
+	for (i = sum = 0; i < szblk; i++) {
+		if (i == XDIR_SetSum) {	/* Skip sum field */
+			i++;
+		} else {
+			sum = ((sum & 1) ? 0x8000 : 0) + (sum >> 1) + dir[i];
+		}
+	}
+	return sum;
+}
+
+
+
+static
+WORD xname_sum (		/* Get check sum (to be used as hash) of the name */
+	const WCHAR* name	/* File name to be calculated */
+)
+{
+	WCHAR chr;
+	WORD sum = 0;
+
+
+	while ((chr = *name++) != 0) {
+		chr = ff_wtoupper(chr);		/* File name needs to be ignored case */
+		sum = ((sum & 1) ? 0x8000 : 0) + (sum >> 1) + (chr & 0xFF);
+		sum = ((sum & 1) ? 0x8000 : 0) + (sum >> 1) + (chr >> 8);
+	}
+	return sum;
+}
+
+
+#if !_FS_READONLY && _USE_MKFS
+static
+DWORD xsum32 (
+	BYTE  dat,	/* Data to be sumed */
+	DWORD sum	/* Previous value */
+)
+{
+	sum = ((sum & 1) ? 0x80000000 : 0) + (sum >> 1) + dat;
+	return sum;
+}
+#endif
+
+
+#if _FS_MINIMIZE <= 1 || _FS_RPATH >= 2
+/*------------------------------------------------------*/
+/* exFAT: Get object information from a directory block */
+/*------------------------------------------------------*/
+
+static
+void get_xdir_info (
+	BYTE* dirb,			/* Pointer to the direcotry entry block 85+C0+C1s */
+	FILINFO* fno		/* Buffer to store the extracted file information */
+)
+{
+	UINT di, si;
+	WCHAR w;
+#if !_LFN_UNICODE
+	UINT nc;
+#endif
+
+	/* Get file name */
+	di = 0;
+#if _LFN_UNICODE
+	for (si = SZDIRE * 2; di < dirb[XDIR_NumName]; si += 2, di++) {
+		if ((si % SZDIRE) == 0) si += 2;		/* Skip entry type field */
+		w = ld_word(dirb + si);					/* Get a character */
+		if (di >= _MAX_LFN) { di = 0; break; }	/* Buffer overflow --> inaccessible object name */
+		fno->fname[di] = w;						/* Store it */
+	}
+#else
+	for (si = SZDIRE * 2, nc = 0; nc < dirb[XDIR_NumName]; si += 2, nc++) {
+		if ((si % SZDIRE) == 0) si += 2;		/* Skip entry type field */
+		w = ff_convert(ld_word(dirb + si), 0);	/* Get a character and Unicode -> OEM */
+		if (_DF1S && w >= 0x100) {				/* Is it a double byte char? (always false at SBCS cfg) */
+			fno->fname[di++] = (char)(w >> 8);	/* Put 1st byte of the DBC */
+		}
+		if (w == 0 || di >= _MAX_LFN) { di = 0; break; }	/* Invalid char or buffer overflow --> inaccessible object name */
+		fno->fname[di++] = (char)w;
+	}
+#endif
+	if (di == 0) fno->fname[di++] = '?';	/* Inaccessible object name? */
+	fno->fname[di] = 0;						/* Terminate file name */
+
+	fno->altname[0] = 0;							/* No SFN */
+	fno->fattrib = dirb[XDIR_Attr];					/* Attribute */
+	fno->fsize = (fno->fattrib & AM_DIR) ? 0 : ld_qword(dirb + XDIR_FileSize);	/* Size */
+	fno->ftime = ld_word(dirb + XDIR_ModTime + 0);	/* Time */
+	fno->fdate = ld_word(dirb + XDIR_ModTime + 2);	/* Date */
+}
+
+#endif	/* _FS_MINIMIZE <= 1 || _FS_RPATH >= 2 */
+
+
+/*-----------------------------------*/
+/* exFAT: Get a directry entry block */
+/*-----------------------------------*/
+
+static
+FRESULT load_xdir (	/* FR_INT_ERR: invalid entry block */
+	DIR* dp			/* Pointer to the reading direcotry object pointing the 85 entry */
+)
+{
+	FRESULT res;
+	UINT i, sz_ent;
+	BYTE* dirb = dp->obj.fs->dirbuf;	/* Pointer to the on-memory direcotry entry block 85+C0+C1s */
+
+
+	/* Load 85 entry */
+	res = move_window(dp->obj.fs, dp->sect);
+	if (res != FR_OK) return res;
+	if (dp->dir[XDIR_Type] != 0x85) return FR_INT_ERR;
+	mem_cpy(dirb + 0, dp->dir, SZDIRE);
+	sz_ent = (dirb[XDIR_NumSec] + 1) * SZDIRE;
+	if (sz_ent < 3 * SZDIRE || sz_ent > 19 * SZDIRE) return FR_INT_ERR;
+
+	/* Load C0 entry */
+	res = dir_next(dp, 0);
+	if (res != FR_OK) return res;
+	res = move_window(dp->obj.fs, dp->sect);
+	if (res != FR_OK) return res;
+	if (dp->dir[XDIR_Type] != 0xC0) return FR_INT_ERR;
+	mem_cpy(dirb + SZDIRE, dp->dir, SZDIRE);
+	if (MAXDIRB(dirb[XDIR_NumName]) > sz_ent) return FR_INT_ERR;
+
+	/* Load C1 entries */
+	i = SZDIRE * 2;	/* C1 offset */
+	do {
+		res = dir_next(dp, 0);
+		if (res != FR_OK) return res;
+		res = move_window(dp->obj.fs, dp->sect);
+		if (res != FR_OK) return res;
+		if (dp->dir[XDIR_Type] != 0xC1) return FR_INT_ERR;
+		if (i < MAXDIRB(_MAX_LFN)) mem_cpy(dirb + i, dp->dir, SZDIRE);
+	} while ((i += SZDIRE) < sz_ent);
+
+	/* Sanity check (do it when accessible object name) */
+	if (i <= MAXDIRB(_MAX_LFN)) {
+		if (xdir_sum(dirb) != ld_word(dirb + XDIR_SetSum)) return FR_INT_ERR;
+	}
+	return FR_OK;
+}
+
+
+#if !_FS_READONLY || _FS_RPATH != 0
+/*------------------------------------------------*/
+/* exFAT: Load the object's directory entry block */
+/*------------------------------------------------*/
+static
+FRESULT load_obj_dir (
+	DIR* dp,			/* Blank directory object to be used to access containing direcotry */
+	const _FDID* obj	/* Object with its containing directory information */
+)
+{
+	FRESULT res;
+
+	/* Open object containing directory */
+	dp->obj.fs = obj->fs;
+	dp->obj.sclust = obj->c_scl;
+	dp->obj.stat = (BYTE)obj->c_size;
+	dp->obj.objsize = obj->c_size & 0xFFFFFF00;
+	dp->blk_ofs = obj->c_ofs;
+
+	res = dir_sdi(dp, dp->blk_ofs);	/* Goto object's entry block */
+	if (res == FR_OK) {
+		res = load_xdir(dp);		/* Load the object's entry block */
+	}
+	return res;
+}
+#endif
+
+
+#if !_FS_READONLY
+/*-----------------------------------------------*/
+/* exFAT: Store the directory block to the media */
+/*-----------------------------------------------*/
+static
+FRESULT store_xdir (
+	DIR* dp				/* Pointer to the direcotry object */
+)
+{
+	FRESULT res;
+	UINT nent;
+	BYTE* dirb = dp->obj.fs->dirbuf;	/* Pointer to the direcotry entry block 85+C0+C1s */
+
+	/* Create set sum */
+	st_word(dirb + XDIR_SetSum, xdir_sum(dirb));
+	nent = dirb[XDIR_NumSec] + 1;
+
+	/* Store the set of directory to the volume */
+	res = dir_sdi(dp, dp->blk_ofs);
+	while (res == FR_OK) {
+		res = move_window(dp->obj.fs, dp->sect);
+		if (res != FR_OK) break;
+		mem_cpy(dp->dir, dirb, SZDIRE);
+		dp->obj.fs->wflag = 1;
+		if (--nent == 0) break;
+		dirb += SZDIRE;
+		res = dir_next(dp, 0);
+	}
+	return (res == FR_OK || res == FR_DISK_ERR) ? res : FR_INT_ERR;
+}
+
+
+
+/*-------------------------------------------*/
+/* exFAT: Create a new directory enrty block */
+/*-------------------------------------------*/
+
+static
+void create_xdir (
+	BYTE* dirb,			/* Pointer to the direcotry entry block buffer */
+	const WCHAR* lfn	/* Pointer to the nul terminated file name */
+)
+{
+	UINT i;
+	BYTE nb, nc;
+	WCHAR chr;
+
+
+	/* Create 85+C0 entry */
+	mem_set(dirb, 0, 2 * SZDIRE);
+	dirb[XDIR_Type] = 0x85;
+	dirb[XDIR_Type + SZDIRE] = 0xC0;
+
+	/* Create C1 entries */
+	nc = 0; nb = 1; chr = 1; i = SZDIRE * 2;
+	do {
+		dirb[i++] = 0xC1; dirb[i++] = 0;	/* Entry type C1 */
+		do {	/* Fill name field */
+			if (chr && (chr = lfn[nc]) != 0) nc++;	/* Get a character if exist */
+			st_word(dirb + i, chr); 		/* Store it */
+		} while ((i += 2) % SZDIRE != 0);
+		nb++;
+	} while (lfn[nc]);	/* Fill next entry if any char follows */
+
+	dirb[XDIR_NumName] = nc;	/* Set name length */
+	dirb[XDIR_NumSec] = nb;		/* Set block length */
+	st_word(dirb + XDIR_NameHash, xname_sum(lfn));	/* Set name hash */
+}
+
+#endif	/* !_FS_READONLY */
+#endif	/* _FS_EXFAT */
+
+
+
+#if _FS_MINIMIZE <= 1 || _FS_RPATH >= 2 || _USE_LABEL || _FS_EXFAT
+/*-----------------------------------------------------------------------*/
+/* Read an object from the directory                                     */
+/*-----------------------------------------------------------------------*/
+
+static
+FRESULT dir_read (
+	DIR* dp,		/* Pointer to the directory object */
+	int vol			/* Filtered by 0:file/directory or 1:volume label */
+)
+{
+	FRESULT res = FR_NO_FILE;
+	FATFS *fs = dp->obj.fs;
+	BYTE a, c;
+#if _USE_LFN != 0
+	BYTE ord = 0xFF, sum = 0xFF;
+#endif
+
+	while (dp->sect) {
+		res = move_window(fs, dp->sect);
+		if (res != FR_OK) break;
+		c = dp->dir[DIR_Name];	/* Test for the entry type */
+		if (c == 0) {
+			res = FR_NO_FILE; break; /* Reached to end of the directory */
+		}
+#if _FS_EXFAT
+		if (fs->fs_type == FS_EXFAT) {	/* On the exFAT volume */
+			if (_USE_LABEL && vol) {
+				if (c == 0x83) break;	/* Volume label entry? */
+			} else {
+				if (c == 0x85) {		/* Start of the file entry block? */
+					dp->blk_ofs = dp->dptr;	/* Get location of the block */
+					res = load_xdir(dp);	/* Load the entry block */
+					if (res == FR_OK) {
+						dp->obj.attr = fs->dirbuf[XDIR_Attr] & AM_MASK;	/* Get attribute */
+					}
+					break;
+				}
+			}
+		} else
+#endif
+		{	/* On the FAT12/16/32 volume */
+			dp->obj.attr = a = dp->dir[DIR_Attr] & AM_MASK;	/* Get attribute */
+#if _USE_LFN != 0	/* LFN configuration */
+			if (c == DDEM || c == '.' || (int)((a & ~AM_ARC) == AM_VOL) != vol) {	/* An entry without valid data */
+				ord = 0xFF;
+			} else {
+				if (a == AM_LFN) {			/* An LFN entry is found */
+					if (c & LLEF) {			/* Is it start of an LFN sequence? */
+						sum = dp->dir[LDIR_Chksum];
+						c &= (BYTE)~LLEF; ord = c;
+						dp->blk_ofs = dp->dptr;
+					}
+					/* Check LFN validity and capture it */
+					ord = (c == ord && sum == dp->dir[LDIR_Chksum] && pick_lfn(fs->lfnbuf, dp->dir)) ? ord - 1 : 0xFF;
+				} else {					/* An SFN entry is found */
+					if (ord || sum != sum_sfn(dp->dir)) {	/* Is there a valid LFN? */
+						dp->blk_ofs = 0xFFFFFFFF;			/* It has no LFN. */
+					}
+					break;
+				}
+			}
+#else		/* Non LFN configuration */
+			if (c != DDEM && c != '.' && a != AM_LFN && (int)((a & ~AM_ARC) == AM_VOL) == vol) {	/* Is it a valid entry? */
+				break;
+			}
+#endif
+		}
+		res = dir_next(dp, 0);		/* Next entry */
+		if (res != FR_OK) break;
+	}
+
+	if (res != FR_OK) dp->sect = 0;		/* Terminate the read operation on error or EOT */
+	return res;
+}
+
+#endif	/* _FS_MINIMIZE <= 1 || _USE_LABEL || _FS_RPATH >= 2 */
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Directory handling - Find an object in the directory                  */
+/*-----------------------------------------------------------------------*/
+
+static
+FRESULT dir_find (	/* FR_OK(0):succeeded, !=0:error */
+	DIR* dp			/* Pointer to the directory object with the file name */
+)
+{
+	FRESULT res;
+	FATFS *fs = dp->obj.fs;
+	BYTE c;
+#if _USE_LFN != 0
+	BYTE a, ord, sum;
+#endif
+
+	res = dir_sdi(dp, 0);			/* Rewind directory object */
+	if (res != FR_OK) return res;
+#if _FS_EXFAT
+	if (fs->fs_type == FS_EXFAT) {	/* On the exFAT volume */
+		BYTE nc;
+		UINT di, ni;
+		WORD hash = xname_sum(fs->lfnbuf);		/* Hash value of the name to find */
+
+		while ((res = dir_read(dp, 0)) == FR_OK) {	/* Read an item */
+#if _MAX_LFN < 255
+			if (fs->dirbuf[XDIR_NumName] > _MAX_LFN) continue;			/* Skip comparison if inaccessible object name */
+#endif
+			if (ld_word(fs->dirbuf + XDIR_NameHash) != hash) continue;	/* Skip comparison if hash mismatched */
+			for (nc = fs->dirbuf[XDIR_NumName], di = SZDIRE * 2, ni = 0; nc; nc--, di += 2, ni++) {	/* Compare the name */
+				if ((di % SZDIRE) == 0) di += 2;
+				if (ff_wtoupper(ld_word(fs->dirbuf + di)) != ff_wtoupper(fs->lfnbuf[ni])) break;
+			}
+			if (nc == 0 && !fs->lfnbuf[ni]) break;	/* Name matched? */
+		}
+		return res;
+	}
+#endif
+	/* On the FAT12/16/32 volume */
+#if _USE_LFN != 0
+	ord = sum = 0xFF; dp->blk_ofs = 0xFFFFFFFF;	/* Reset LFN sequence */
+#endif
+	do {
+		res = move_window(fs, dp->sect);
+		if (res != FR_OK) break;
+		c = dp->dir[DIR_Name];
+		if (c == 0) { res = FR_NO_FILE; break; }	/* Reached to end of table */
+#if _USE_LFN != 0	/* LFN configuration */
+		dp->obj.attr = a = dp->dir[DIR_Attr] & AM_MASK;
+		if (c == DDEM || ((a & AM_VOL) && a != AM_LFN)) {	/* An entry without valid data */
+			ord = 0xFF; dp->blk_ofs = 0xFFFFFFFF;	/* Reset LFN sequence */
+		} else {
+			if (a == AM_LFN) {			/* An LFN entry is found */
+				if (!(dp->fn[NSFLAG] & NS_NOLFN)) {
+					if (c & LLEF) {		/* Is it start of LFN sequence? */
+						sum = dp->dir[LDIR_Chksum];
+						c &= (BYTE)~LLEF; ord = c;	/* LFN start order */
+						dp->blk_ofs = dp->dptr;	/* Start offset of LFN */
+					}
+					/* Check validity of the LFN entry and compare it with given name */
+					ord = (c == ord && sum == dp->dir[LDIR_Chksum] && cmp_lfn(fs->lfnbuf, dp->dir)) ? ord - 1 : 0xFF;
+				}
+			} else {					/* An SFN entry is found */
+				if (!ord && sum == sum_sfn(dp->dir)) break;	/* LFN matched? */
+				if (!(dp->fn[NSFLAG] & NS_LOSS) && !mem_cmp(dp->dir, dp->fn, 11)) break;	/* SFN matched? */
+				ord = 0xFF; dp->blk_ofs = 0xFFFFFFFF;	/* Reset LFN sequence */
+			}
+		}
+#else		/* Non LFN configuration */
+		dp->obj.attr = dp->dir[DIR_Attr] & AM_MASK;
+		if (!(dp->dir[DIR_Attr] & AM_VOL) && !mem_cmp(dp->dir, dp->fn, 11)) break;	/* Is it a valid entry? */
+#endif
+		res = dir_next(dp, 0);	/* Next entry */
+	} while (res == FR_OK);
+
+	return res;
+}
+
+
+
+
+#if !_FS_READONLY
+/*-----------------------------------------------------------------------*/
+/* Register an object to the directory                                   */
+/*-----------------------------------------------------------------------*/
+
+static
+FRESULT dir_register (	/* FR_OK:succeeded, FR_DENIED:no free entry or too many SFN collision, FR_DISK_ERR:disk error */
+	DIR* dp				/* Target directory with object name to be created */
+)
+{
+	FRESULT res;
+	FATFS *fs = dp->obj.fs;
+#if _USE_LFN != 0	/* LFN configuration */
+	UINT n, nlen, nent;
+	BYTE sn[12], sum;
+
+
+	if (dp->fn[NSFLAG] & (NS_DOT | NS_NONAME)) return FR_INVALID_NAME;	/* Check name validity */
+	for (nlen = 0; fs->lfnbuf[nlen]; nlen++) ;	/* Get lfn length */
+
+#if _FS_EXFAT
+	if (fs->fs_type == FS_EXFAT) {	/* On the exFAT volume */
+		DIR dj;
+
+		nent = (nlen + 14) / 15 + 2;	/* Number of entries to allocate (85+C0+C1s) */
+		res = dir_alloc(dp, nent);		/* Allocate entries */
+		if (res != FR_OK) return res;
+		dp->blk_ofs = dp->dptr - SZDIRE * (nent - 1);	/* Set the allocated entry block offset */
+
+		if (dp->obj.sclust != 0 && (dp->obj.stat & 4)) {	/* Has the sub-directory been stretched? */
+			dp->obj.objsize += (DWORD)fs->csize * SS(fs);	/* Increase the directory size by cluster size */
+			res = fill_first_frag(&dp->obj);				/* Fill first fragment on the FAT if needed */
+			if (res != FR_OK) return res;
+			res = fill_last_frag(&dp->obj, dp->clust, 0xFFFFFFFF);	/* Fill last fragment on the FAT if needed */
+			if (res != FR_OK) return res;
+			res = load_obj_dir(&dj, &dp->obj);				/* Load the object status */
+			if (res != FR_OK) return res;
+			st_qword(fs->dirbuf + XDIR_FileSize, dp->obj.objsize);		/* Update the allocation status */
+			st_qword(fs->dirbuf + XDIR_ValidFileSize, dp->obj.objsize);
+			fs->dirbuf[XDIR_GenFlags] = dp->obj.stat | 1;
+			res = store_xdir(&dj);							/* Store the object status */
+			if (res != FR_OK) return res;
+		}
+
+		create_xdir(fs->dirbuf, fs->lfnbuf);	/* Create on-memory directory block to be written later */
+		return FR_OK;
+	}
+#endif
+	/* On the FAT12/16/32 volume */
+	mem_cpy(sn, dp->fn, 12);
+	if (sn[NSFLAG] & NS_LOSS) {			/* When LFN is out of 8.3 format, generate a numbered name */
+		dp->fn[NSFLAG] = NS_NOLFN;		/* Find only SFN */
+		for (n = 1; n < 100; n++) {
+			gen_numname(dp->fn, sn, fs->lfnbuf, n);	/* Generate a numbered name */
+			res = dir_find(dp);				/* Check if the name collides with existing SFN */
+			if (res != FR_OK) break;
+		}
+		if (n == 100) return FR_DENIED;		/* Abort if too many collisions */
+		if (res != FR_NO_FILE) return res;	/* Abort if the result is other than 'not collided' */
+		dp->fn[NSFLAG] = sn[NSFLAG];
+	}
+
+	/* Create an SFN with/without LFNs. */
+	nent = (sn[NSFLAG] & NS_LFN) ? (nlen + 12) / 13 + 1 : 1;	/* Number of entries to allocate */
+	res = dir_alloc(dp, nent);		/* Allocate entries */
+	if (res == FR_OK && --nent) {	/* Set LFN entry if needed */
+		res = dir_sdi(dp, dp->dptr - nent * SZDIRE);
+		if (res == FR_OK) {
+			sum = sum_sfn(dp->fn);	/* Checksum value of the SFN tied to the LFN */
+			do {					/* Store LFN entries in bottom first */
+				res = move_window(fs, dp->sect);
+				if (res != FR_OK) break;
+				put_lfn(fs->lfnbuf, dp->dir, (BYTE)nent, sum);
+				fs->wflag = 1;
+				res = dir_next(dp, 0);	/* Next entry */
+			} while (res == FR_OK && --nent);
+		}
+	}
+
+#else	/* Non LFN configuration */
+	res = dir_alloc(dp, 1);		/* Allocate an entry for SFN */
+
+#endif
+
+	/* Set SFN entry */
+	if (res == FR_OK) {
+		res = move_window(fs, dp->sect);
+		if (res == FR_OK) {
+			mem_set(dp->dir, 0, SZDIRE);	/* Clean the entry */
+			mem_cpy(dp->dir + DIR_Name, dp->fn, 11);	/* Put SFN */
+#if _USE_LFN != 0
+			dp->dir[DIR_NTres] = dp->fn[NSFLAG] & (NS_BODY | NS_EXT);	/* Put NT flag */
+#endif
+			fs->wflag = 1;
+		}
+	}
+
+	return res;
+}
+
+#endif /* !_FS_READONLY */
+
+
+
+#if !_FS_READONLY && _FS_MINIMIZE == 0
+/*-----------------------------------------------------------------------*/
+/* Remove an object from the directory                                   */
+/*-----------------------------------------------------------------------*/
+
+static
+FRESULT dir_remove (	/* FR_OK:Succeeded, FR_DISK_ERR:A disk error */
+	DIR* dp				/* Directory object pointing the entry to be removed */
+)
+{
+	FRESULT res;
+	FATFS *fs = dp->obj.fs;
+#if _USE_LFN != 0	/* LFN configuration */
+	DWORD last = dp->dptr;
+
+	res = (dp->blk_ofs == 0xFFFFFFFF) ? FR_OK : dir_sdi(dp, dp->blk_ofs);	/* Goto top of the entry block if LFN is exist */
+	if (res == FR_OK) {
+		do {
+			res = move_window(fs, dp->sect);
+			if (res != FR_OK) break;
+			/* Mark an entry 'deleted' */
+			if (_FS_EXFAT && fs->fs_type == FS_EXFAT) {	/* On the exFAT volume */
+				dp->dir[XDIR_Type] &= 0x7F;
+			} else {									/* On the FAT12/16/32 volume */
+				dp->dir[DIR_Name] = DDEM;
+			}
+			fs->wflag = 1;
+			if (dp->dptr >= last) break;	/* If reached last entry then all entries of the object has been deleted. */
+			res = dir_next(dp, 0);	/* Next entry */
+		} while (res == FR_OK);
+		if (res == FR_NO_FILE) res = FR_INT_ERR;
+	}
+#else			/* Non LFN configuration */
+
+	res = move_window(fs, dp->sect);
+	if (res == FR_OK) {
+		dp->dir[DIR_Name] = DDEM;
+		fs->wflag = 1;
+	}
+#endif
+
+	return res;
+}
+
+#endif /* !_FS_READONLY && _FS_MINIMIZE == 0 */
+
+
+
+#if _FS_MINIMIZE <= 1 || _FS_RPATH >= 2
+/*-----------------------------------------------------------------------*/
+/* Get file information from directory entry                             */
+/*-----------------------------------------------------------------------*/
+
+static
+void get_fileinfo (		/* No return code */
+	DIR* dp,			/* Pointer to the directory object */
+	FILINFO* fno	 	/* Pointer to the file information to be filled */
+)
+{
+	UINT i, j;
+	TCHAR c;
+	DWORD tm;
+#if _USE_LFN != 0
+	WCHAR w, lfv;
+	FATFS *fs = dp->obj.fs;
+#endif
+
+
+	fno->fname[0] = 0;		/* Invaidate file info */
+	if (!dp->sect) return;	/* Exit if read pointer has reached end of directory */
+
+#if _USE_LFN != 0	/* LFN configuration */
+#if _FS_EXFAT
+	if (fs->fs_type == FS_EXFAT) {	/* On the exFAT volume */
+		get_xdir_info(fs->dirbuf, fno);
+		return;
+	} else
+#endif
+	{	/* On the FAT12/16/32 volume */
+		if (dp->blk_ofs != 0xFFFFFFFF) {	/* Get LFN if available */
+			i = j = 0;
+			while ((w = fs->lfnbuf[j++]) != 0) {	/* Get an LFN character */
+#if !_LFN_UNICODE
+				w = ff_convert(w, 0);		/* Unicode -> OEM */
+				if (w == 0) { i = 0; break; }	/* No LFN if it could not be converted */
+				if (_DF1S && w >= 0x100) {	/* Put 1st byte if it is a DBC (always false at SBCS cfg) */
+					fno->fname[i++] = (char)(w >> 8);
+				}
+#endif
+				if (i >= _MAX_LFN) { i = 0; break; }	/* No LFN if buffer overflow */
+				fno->fname[i++] = (TCHAR)w;
+			}
+			fno->fname[i] = 0;	/* Terminate the LFN */
+		}
+	}
+
+	i = j = 0;
+	lfv = fno->fname[i];	/* LFN is exist if non-zero */
+	while (i < 11) {		/* Copy name body and extension */
+		c = (TCHAR)dp->dir[i++];
+		if (c == ' ') continue;				/* Skip padding spaces */
+		if (c == RDDEM) c = (TCHAR)DDEM;	/* Restore replaced DDEM character */
+		if (i == 9) {						/* Insert a . if extension is exist */
+			if (!lfv) fno->fname[j] = '.';
+			fno->altname[j++] = '.';
+		}
+#if _LFN_UNICODE
+		if (IsDBCS1(c) && i != 8 && i != 11 && IsDBCS2(dp->dir[i])) {
+			c = c << 8 | dp->dir[i++];
+		}
+		c = ff_convert(c, 1);	/* OEM -> Unicode */
+		if (!c) c = '?';
+#endif
+		fno->altname[j] = c;
+		if (!lfv) {
+			if (IsUpper(c) && (dp->dir[DIR_NTres] & ((i >= 9) ? NS_EXT : NS_BODY))) {
+				c += 0x20;			/* To lower */
+			}
+			fno->fname[j] = c;
+		}
+		j++;
+	}
+	if (!lfv) {
+		fno->fname[j] = 0;
+		if (!dp->dir[DIR_NTres]) j = 0;	/* Altname is no longer needed if neither LFN nor case info is exist. */
+	}
+	fno->altname[j] = 0;	/* Terminate the SFN */
+
+#else	/* Non-LFN configuration */
+	i = j = 0;
+	while (i < 11) {		/* Copy name body and extension */
+		c = (TCHAR)dp->dir[i++];
+		if (c == ' ') continue;				/* Skip padding spaces */
+		if (c == RDDEM) c = (TCHAR)DDEM;	/* Restore replaced DDEM character */
+		if (i == 9) fno->fname[j++] = '.';	/* Insert a . if extension is exist */
+		fno->fname[j++] = c;
+	}
+	fno->fname[j] = 0;
+#endif
+
+	fno->fattrib = dp->dir[DIR_Attr];				/* Attribute */
+	fno->fsize = ld_dword(dp->dir + DIR_FileSize);	/* Size */
+	tm = ld_dword(dp->dir + DIR_ModTime);			/* Timestamp */
+	fno->ftime = (WORD)tm; fno->fdate = (WORD)(tm >> 16);
+}
+
+#endif /* _FS_MINIMIZE <= 1 || _FS_RPATH >= 2 */
+
+
+
+#if _USE_FIND && _FS_MINIMIZE <= 1
+/*-----------------------------------------------------------------------*/
+/* Pattern matching                                                      */
+/*-----------------------------------------------------------------------*/
+
+static
+WCHAR get_achar (		/* Get a character and advances ptr 1 or 2 */
+	const TCHAR** ptr	/* Pointer to pointer to the SBCS/DBCS/Unicode string */
+)
+{
+#if !_LFN_UNICODE
+	WCHAR chr;
+
+	chr = (BYTE)*(*ptr)++;					/* Get a byte */
+	if (IsLower(chr)) chr -= 0x20;			/* To upper ASCII char */
+#ifdef _EXCVT
+	if (chr >= 0x80) chr = ExCvt[chr - 0x80];	/* To upper SBCS extended char */
+#else
+	if (IsDBCS1(chr) && IsDBCS2(**ptr)) {		/* Get DBC 2nd byte if needed */
+		chr = chr << 8 | (BYTE)*(*ptr)++;
+	}
+#endif
+	return chr;
+#else
+	return ff_wtoupper(*(*ptr)++);			/* Get a word and to upper */
+#endif
+}
+
+
+static
+int pattern_matching (	/* 0:not matched, 1:matched */
+	const TCHAR* pat,	/* Matching pattern */
+	const TCHAR* nam,	/* String to be tested */
+	int skip,			/* Number of pre-skip chars (number of ?s) */
+	int inf				/* Infinite search (* specified) */
+)
+{
+	const TCHAR *pp, *np;
+	WCHAR pc, nc;
+	int nm, nx;
+
+
+	while (skip--) {				/* Pre-skip name chars */
+		if (!get_achar(&nam)) return 0;	/* Branch mismatched if less name chars */
+	}
+	if (!*pat && inf) return 1;		/* (short circuit) */
+
+	do {
+		pp = pat; np = nam;			/* Top of pattern and name to match */
+		for (;;) {
+			if (*pp == '?' || *pp == '*') {	/* Wildcard? */
+				nm = nx = 0;
+				do {				/* Analyze the wildcard chars */
+					if (*pp++ == '?') nm++; else nx = 1;
+				} while (*pp == '?' || *pp == '*');
+				if (pattern_matching(pp, np, nm, nx)) return 1;	/* Test new branch (recurs upto number of wildcard blocks in the pattern) */
+				nc = *np; break;	/* Branch mismatched */
+			}
+			pc = get_achar(&pp);	/* Get a pattern char */
+			nc = get_achar(&np);	/* Get a name char */
+			if (pc != nc) break;	/* Branch mismatched? */
+			if (pc == 0) return 1;	/* Branch matched? (matched at end of both strings) */
+		}
+		get_achar(&nam);			/* nam++ */
+	} while (inf && nc);			/* Retry until end of name if infinite search is specified */
+
+	return 0;
+}
+
+#endif /* _USE_FIND && _FS_MINIMIZE <= 1 */
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Pick a top segment and create the object name in directory form       */
+/*-----------------------------------------------------------------------*/
+
+static
+FRESULT create_name (	/* FR_OK: successful, FR_INVALID_NAME: could not create */
+	DIR* dp,			/* Pointer to the directory object */
+	const TCHAR** path	/* Pointer to pointer to the segment in the path string */
+)
+{
+#if _USE_LFN != 0	/* LFN configuration */
+	BYTE b, cf;
+	WCHAR w, *lfn;
+	UINT i, ni, si, di;
+	const TCHAR *p;
+
+	/* Create LFN in Unicode */
+	p = *path; lfn = dp->obj.fs->lfnbuf; si = di = 0;
+	for (;;) {
+		w = p[si++];					/* Get a character */
+		if (w < ' ') break;				/* Break if end of the path name */
+		if (w == '/' || w == '\\') {	/* Break if a separator is found */
+			while (p[si] == '/' || p[si] == '\\') si++;	/* Skip duplicated separator if exist */
+			break;
+		}
+		if (di >= _MAX_LFN) return FR_INVALID_NAME;	/* Reject too long name */
+#if !_LFN_UNICODE
+		w &= 0xFF;
+		if (IsDBCS1(w)) {				/* Check if it is a DBC 1st byte (always false on SBCS cfg) */
+			b = (BYTE)p[si++];			/* Get 2nd byte */
+			w = (w << 8) + b;			/* Create a DBC */
+			if (!IsDBCS2(b)) return FR_INVALID_NAME;	/* Reject invalid sequence */
+		}
+		w = ff_convert(w, 1);			/* Convert ANSI/OEM to Unicode */
+		if (!w) return FR_INVALID_NAME;	/* Reject invalid code */
+#endif
+		if (w < 0x80 && chk_chr("\"*:<>\?|\x7F", w)) return FR_INVALID_NAME;	/* Reject illegal characters for LFN */
+		lfn[di++] = w;					/* Store the Unicode character */
+	}
+	*path = &p[si];						/* Return pointer to the next segment */
+	cf = (w < ' ') ? NS_LAST : 0;		/* Set last segment flag if end of the path */
+#if _FS_RPATH != 0
+	if ((di == 1 && lfn[di - 1] == '.') ||
+		(di == 2 && lfn[di - 1] == '.' && lfn[di - 2] == '.')) {	/* Is this segment a dot name? */
+		lfn[di] = 0;
+		for (i = 0; i < 11; i++)		/* Create dot name for SFN entry */
+			dp->fn[i] = (i < di) ? '.' : ' ';
+		dp->fn[i] = cf | NS_DOT;		/* This is a dot entry */
+		return FR_OK;
+	}
+#endif
+	while (di) {						/* Snip off trailing spaces and dots if exist */
+		w = lfn[di - 1];
+		if (w != ' ' && w != '.') break;
+		di--;
+	}
+	lfn[di] = 0;						/* LFN is created */
+	if (di == 0) return FR_INVALID_NAME;	/* Reject nul name */
+
+	/* Create SFN in directory form */
+	mem_set(dp->fn, ' ', 11);
+	for (si = 0; lfn[si] == ' ' || lfn[si] == '.'; si++) ;	/* Strip leading spaces and dots */
+	if (si) cf |= NS_LOSS | NS_LFN;
+	while (di && lfn[di - 1] != '.') di--;	/* Find extension (di<=si: no extension) */
+
+	i = b = 0; ni = 8;
+	for (;;) {
+		w = lfn[si++];					/* Get an LFN character */
+		if (!w) break;					/* Break on end of the LFN */
+		if (w == ' ' || (w == '.' && si != di)) {	/* Remove spaces and dots */
+			cf |= NS_LOSS | NS_LFN; continue;
+		}
+
+		if (i >= ni || si == di) {		/* Extension or end of SFN */
+			if (ni == 11) {				/* Long extension */
+				cf |= NS_LOSS | NS_LFN; break;
+			}
+			if (si != di) cf |= NS_LOSS | NS_LFN;	/* Out of 8.3 format */
+			if (si > di) break;			/* No extension */
+			si = di; i = 8; ni = 11;	/* Enter extension section */
+			b <<= 2; continue;
+		}
+
+		if (w >= 0x80) {				/* Non ASCII character */
+#ifdef _EXCVT
+			w = ff_convert(w, 0);		/* Unicode -> OEM code */
+			if (w) w = ExCvt[w - 0x80];	/* Convert extended character to upper (SBCS) */
+#else
+			w = ff_convert(ff_wtoupper(w), 0);	/* Upper converted Unicode -> OEM code */
+#endif
+			cf |= NS_LFN;				/* Force create LFN entry */
+		}
+
+		if (_DF1S && w >= 0x100) {		/* Is this DBC? (always false at SBCS cfg) */
+			if (i >= ni - 1) {
+				cf |= NS_LOSS | NS_LFN; i = ni; continue;
+			}
+			dp->fn[i++] = (BYTE)(w >> 8);
+		} else {						/* SBC */
+			if (!w || chk_chr("+,;=[]", w)) {	/* Replace illegal characters for SFN */
+				w = '_'; cf |= NS_LOSS | NS_LFN;/* Lossy conversion */
+			} else {
+				if (IsUpper(w)) {		/* ASCII large capital */
+					b |= 2;
+				} else {
+					if (IsLower(w)) {	/* ASCII small capital */
+						b |= 1; w -= 0x20;
+					}
+				}
+			}
+		}
+		dp->fn[i++] = (BYTE)w;
+	}
+
+	if (dp->fn[0] == DDEM) dp->fn[0] = RDDEM;	/* If the first character collides with DDEM, replace it with RDDEM */
+
+	if (ni == 8) b <<= 2;
+	if ((b & 0x0C) == 0x0C || (b & 0x03) == 0x03) cf |= NS_LFN;	/* Create LFN entry when there are composite capitals */
+	if (!(cf & NS_LFN)) {						/* When LFN is in 8.3 format without extended character, NT flags are created */
+		if ((b & 0x03) == 0x01) cf |= NS_EXT;	/* NT flag (Extension has only small capital) */
+		if ((b & 0x0C) == 0x04) cf |= NS_BODY;	/* NT flag (Filename has only small capital) */
+	}
+
+	dp->fn[NSFLAG] = cf;	/* SFN is created */
+
+	return FR_OK;
+
+
+#else	/* _USE_LFN != 0 : Non-LFN configuration */
+	BYTE c, d, *sfn;
+	UINT ni, si, i;
+	const char *p;
+
+	/* Create file name in directory form */
+	p = *path; sfn = dp->fn;
+	mem_set(sfn, ' ', 11);
+	si = i = 0; ni = 8;
+#if _FS_RPATH != 0
+	if (p[si] == '.') { /* Is this a dot entry? */
+		for (;;) {
+			c = (BYTE)p[si++];
+			if (c != '.' || si >= 3) break;
+			sfn[i++] = c;
+		}
+		if (c != '/' && c != '\\' && c > ' ') return FR_INVALID_NAME;
+		*path = p + si;								/* Return pointer to the next segment */
+		sfn[NSFLAG] = (c <= ' ') ? NS_LAST | NS_DOT : NS_DOT;	/* Set last segment flag if end of the path */
+		return FR_OK;
+	}
+#endif
+	for (;;) {
+		c = (BYTE)p[si++];
+		if (c <= ' ') break; 			/* Break if end of the path name */
+		if (c == '/' || c == '\\') {	/* Break if a separator is found */
+			while (p[si] == '/' || p[si] == '\\') si++;	/* Skip duplicated separator if exist */
+			break;
+		}
+		if (c == '.' || i >= ni) {		/* End of body or over size? */
+			if (ni == 11 || c != '.') return FR_INVALID_NAME;	/* Over size or invalid dot */
+			i = 8; ni = 11;				/* Goto extension */
+			continue;
+		}
+		if (c >= 0x80) {				/* Extended character? */
+#ifdef _EXCVT
+			c = ExCvt[c - 0x80];		/* To upper extended characters (SBCS cfg) */
+#else
+#if !_DF1S
+			return FR_INVALID_NAME;		/* Reject extended characters (ASCII only cfg) */
+#endif
+#endif
+		}
+		if (IsDBCS1(c)) {				/* Check if it is a DBC 1st byte (always false at SBCS cfg.) */
+			d = (BYTE)p[si++];			/* Get 2nd byte */
+			if (!IsDBCS2(d) || i >= ni - 1) return FR_INVALID_NAME;	/* Reject invalid DBC */
+			sfn[i++] = c;
+			sfn[i++] = d;
+		} else {						/* SBC */
+			if (chk_chr("\"*+,:;<=>\?[]|\x7F", c)) return FR_INVALID_NAME;	/* Reject illegal chrs for SFN */
+			if (IsLower(c)) c -= 0x20;	/* To upper */
+			sfn[i++] = c;
+		}
+	}
+	*path = p + si;						/* Return pointer to the next segment */
+	if (i == 0) return FR_INVALID_NAME;	/* Reject nul string */
+
+	if (sfn[0] == DDEM) sfn[0] = RDDEM;	/* If the first character collides with DDEM, replace it with RDDEM */
+	sfn[NSFLAG] = (c <= ' ') ? NS_LAST : 0;		/* Set last segment flag if end of the path */
+
+	return FR_OK;
+#endif /* _USE_LFN != 0 */
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Follow a file path                                                    */
+/*-----------------------------------------------------------------------*/
+
+static
+FRESULT follow_path (	/* FR_OK(0): successful, !=0: error code */
+	DIR* dp,			/* Directory object to return last directory and found object */
+	const TCHAR* path	/* Full-path string to find a file or directory */
+)
+{
+	FRESULT res;
+	BYTE ns;
+	_FDID *obj = &dp->obj;
+	FATFS *fs = obj->fs;
+
+
+#if _FS_RPATH != 0
+	if (*path != '/' && *path != '\\') {	/* Without heading separator */
+		obj->sclust = fs->cdir;				/* Start from current directory */
+	} else
+#endif
+	{										/* With heading separator */
+		while (*path == '/' || *path == '\\') path++;	/* Strip heading separator */
+		obj->sclust = 0;					/* Start from root directory */
+	}
+#if _FS_EXFAT
+	obj->n_frag = 0;	/* Invalidate last fragment counter of the object */
+#if _FS_RPATH != 0
+	if (fs->fs_type == FS_EXFAT && obj->sclust) {	/* Retrieve the sub-directory status if needed */
+		DIR dj;
+
+		obj->c_scl = fs->cdc_scl;
+		obj->c_size = fs->cdc_size;
+		obj->c_ofs = fs->cdc_ofs;
+		res = load_obj_dir(&dj, obj);
+		if (res != FR_OK) return res;
+		obj->objsize = ld_dword(fs->dirbuf + XDIR_FileSize);
+		obj->stat = fs->dirbuf[XDIR_GenFlags] & 2;
+	}
+#endif
+#endif
+
+	if ((UINT)*path < ' ') {				/* Null path name is the origin directory itself */
+		dp->fn[NSFLAG] = NS_NONAME;
+		res = dir_sdi(dp, 0);
+
+	} else {								/* Follow path */
+		for (;;) {
+			res = create_name(dp, &path);	/* Get a segment name of the path */
+			if (res != FR_OK) break;
+			res = dir_find(dp);				/* Find an object with the segment name */
+			ns = dp->fn[NSFLAG];
+			if (res != FR_OK) {				/* Failed to find the object */
+				if (res == FR_NO_FILE) {	/* Object is not found */
+					if (_FS_RPATH && (ns & NS_DOT)) {	/* If dot entry is not exist, stay there */
+						if (!(ns & NS_LAST)) continue;	/* Continue to follow if not last segment */
+						dp->fn[NSFLAG] = NS_NONAME;
+						res = FR_OK;
+					} else {							/* Could not find the object */
+						if (!(ns & NS_LAST)) res = FR_NO_PATH;	/* Adjust error code if not last segment */
+					}
+				}
+				break;
+			}
+			if (ns & NS_LAST) break;			/* Last segment matched. Function completed. */
+			/* Get into the sub-directory */
+			if (!(obj->attr & AM_DIR)) {		/* It is not a sub-directory and cannot follow */
+				res = FR_NO_PATH; break;
+			}
+#if _FS_EXFAT
+			if (fs->fs_type == FS_EXFAT) {		/* Save containing directory information for next dir */
+				obj->c_scl = obj->sclust;
+				obj->c_size = ((DWORD)obj->objsize & 0xFFFFFF00) | obj->stat;
+				obj->c_ofs = dp->blk_ofs;
+				obj->sclust = ld_dword(fs->dirbuf + XDIR_FstClus);	/* Open next directory */
+				obj->stat = fs->dirbuf[XDIR_GenFlags] & 2;
+				obj->objsize = ld_qword(fs->dirbuf + XDIR_FileSize);
+			} else
+#endif
+			{
+				obj->sclust = ld_clust(fs, fs->win + dp->dptr % SS(fs));	/* Open next directory */
+			}
+		}
+	}
+
+	return res;
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Get logical drive number from path name                               */
+/*-----------------------------------------------------------------------*/
+
+static
+int get_ldnumber (		/* Returns logical drive number (-1:invalid drive) */
+	const TCHAR** path	/* Pointer to pointer to the path name */
+)
+{
+	const TCHAR *tp, *tt;
+	UINT i;
+	int vol = -1;
+#if _STR_VOLUME_ID		/* Find string drive id */
+	static const char* const volid[] = {_VOLUME_STRS};
+	const char *sp;
+	char c;
+	TCHAR tc;
+#endif
+
+
+	if (*path) {	/* If the pointer is not a null */
+		for (tt = *path; (UINT)*tt >= (_USE_LFN ? ' ' : '!') && *tt != ':'; tt++) ;	/* Find ':' in the path */
+		if (*tt == ':') {	/* If a ':' is exist in the path name */
+			tp = *path;
+			i = *tp++ - '0';
+			if (i < 10 && tp == tt) {	/* Is there a numeric drive id? */
+				if (i < _VOLUMES) {	/* If a drive id is found, get the value and strip it */
+					vol = (int)i;
+					*path = ++tt;
+				}
+			}
+#if _STR_VOLUME_ID
+			 else {	/* No numeric drive number, find string drive id */
+				i = 0; tt++;
+				do {
+					sp = volid[i]; tp = *path;
+					do {	/* Compare a string drive id with path name */
+						c = *sp++; tc = *tp++;
+						if (IsLower(tc)) tc -= 0x20;
+					} while (c && (TCHAR)c == tc);
+				} while ((c || tp != tt) && ++i < _VOLUMES);	/* Repeat for each id until pattern match */
+				if (i < _VOLUMES) {	/* If a drive id is found, get the value and strip it */
+					vol = (int)i;
+					*path = tt;
+				}
+			}
+#endif
+			return vol;
+		}
+#if _FS_RPATH != 0 && _VOLUMES >= 2
+		vol = CurrVol;	/* Current drive */
+#else
+		vol = 0;		/* Drive 0 */
+#endif
+	}
+	return vol;
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Load a sector and check if it is an FAT boot sector                   */
+/*-----------------------------------------------------------------------*/
+
+static
+BYTE check_fs (	/* 0:FAT, 1:exFAT, 2:Valid BS but not FAT, 3:Not a BS, 4:Disk error */
+	FATFS* fs,	/* File system object */
+	DWORD sect	/* Sector# (lba) to load and check if it is an FAT-VBR or not */
+)
+{
+	fs->wflag = 0; fs->winsect = 0xFFFFFFFF;		/* Invaidate window */
+	if (move_window(fs, sect) != FR_OK) return 4;	/* Load boot record */
+
+	if (ld_word(fs->win + BS_55AA) != 0xAA55) return 3;	/* Check boot record signature (always placed here even if the sector size is >512) */
+
+	if (fs->win[BS_JmpBoot] == 0xE9 || (fs->win[BS_JmpBoot] == 0xEB && fs->win[BS_JmpBoot + 2] == 0x90)) {
+		if ((ld_dword(fs->win + BS_FilSysType) & 0xFFFFFF) == 0x544146) return 0;	/* Check "FAT" string */
+		if (ld_dword(fs->win + BS_FilSysType32) == 0x33544146) return 0;			/* Check "FAT3" string */
+	}
+#if _FS_EXFAT
+	if (!mem_cmp(fs->win + BS_JmpBoot, "\xEB\x76\x90" "EXFAT   ", 11)) return 1;
+#endif
+	return 2;
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Find logical drive and check if the volume is mounted                 */
+/*-----------------------------------------------------------------------*/
+
+static
+FRESULT find_volume (	/* FR_OK(0): successful, !=0: any error occurred */
+	const TCHAR** path,	/* Pointer to pointer to the path name (drive number) */
+	FATFS** rfs,		/* Pointer to pointer to the found file system object */
+	BYTE mode			/* !=0: Check write protection for write access */
+)
+{
+	BYTE fmt, *pt;
+	int vol;
+	DSTATUS stat;
+	DWORD bsect, fasize, tsect, sysect, nclst, szbfat, br[4];
+	WORD nrsv;
+	FATFS *fs;
+	UINT i;
+
+
+	/* Get logical drive number */
+	*rfs = 0;
+	vol = get_ldnumber(path);
+	if (vol < 0) return FR_INVALID_DRIVE;
+
+	/* Check if the file system object is valid or not */
+	fs = FatFs[vol];					/* Get pointer to the file system object */
+	if (!fs) return FR_NOT_ENABLED;		/* Is the file system object available? */
+
+	ENTER_FF(fs);						/* Lock the volume */
+	*rfs = fs;							/* Return pointer to the file system object */
+
+	mode &= (BYTE)~FA_READ;				/* Desired access mode, write access or not */
+	if (fs->fs_type) {					/* If the volume has been mounted */
+		stat = disk_status(fs->drv);
+		if (!(stat & STA_NOINIT)) {		/* and the physical drive is kept initialized */
+			if (!_FS_READONLY && mode && (stat & STA_PROTECT)) {	/* Check write protection if needed */
+				return FR_WRITE_PROTECTED;
+			}
+			return FR_OK;				/* The file system object is valid */
+		}
+	}
+
+	/* The file system object is not valid. */
+	/* Following code attempts to mount the volume. (analyze BPB and initialize the fs object) */
+
+	fs->fs_type = 0;					/* Clear the file system object */
+	fs->drv = LD2PD(vol);				/* Bind the logical drive and a physical drive */
+	stat = disk_initialize(fs->drv);	/* Initialize the physical drive */
+	if (stat & STA_NOINIT) { 			/* Check if the initialization succeeded */
+		return FR_NOT_READY;			/* Failed to initialize due to no medium or hard error */
+	}
+	if (!_FS_READONLY && mode && (stat & STA_PROTECT)) { /* Check disk write protection if needed */
+		return FR_WRITE_PROTECTED;
+	}
+#if _MAX_SS != _MIN_SS					/* Get sector size (multiple sector size cfg only) */
+	if (disk_ioctl(fs->drv, GET_SECTOR_SIZE, &SS(fs)) != RES_OK) return FR_DISK_ERR;
+	if (SS(fs) > _MAX_SS || SS(fs) < _MIN_SS || (SS(fs) & (SS(fs) - 1))) return FR_DISK_ERR;
+#endif
+
+	/* Find an FAT partition on the drive. Supports only generic partitioning rules, FDISK and SFD. */
+	bsect = 0;
+	fmt = check_fs(fs, bsect);			/* Load sector 0 and check if it is an FAT-VBR as SFD */
+	if (fmt == 2 || (fmt < 2 && LD2PT(vol) != 0)) {	/* Not an FAT-VBR or forced partition number */
+		for (i = 0; i < 4; i++) {		/* Get partition offset */
+			pt = fs->win + (MBR_Table + i * SZ_PTE);
+			br[i] = pt[PTE_System] ? ld_dword(pt + PTE_StLba) : 0;
+		}
+		i = LD2PT(vol);					/* Partition number: 0:auto, 1-4:forced */
+		if (i) i--;
+		do {							/* Find an FAT volume */
+			bsect = br[i];
+			fmt = bsect ? check_fs(fs, bsect) : 3;	/* Check the partition */
+		} while (LD2PT(vol) == 0 && fmt >= 2 && ++i < 4);
+	}
+	if (fmt == 4) return FR_DISK_ERR;		/* An error occured in the disk I/O layer */
+	if (fmt >= 2) return FR_NO_FILESYSTEM;	/* No FAT volume is found */
+
+	/* An FAT volume is found (bsect). Following code initializes the file system object */
+
+#if _FS_EXFAT
+	if (fmt == 1) {
+		QWORD maxlba;
+
+		for (i = BPB_ZeroedEx; i < BPB_ZeroedEx + 53 && fs->win[i] == 0; i++) ;	/* Check zero filler */
+		if (i < BPB_ZeroedEx + 53) return FR_NO_FILESYSTEM;
+
+		if (ld_word(fs->win + BPB_FSVerEx) != 0x100) return FR_NO_FILESYSTEM;	/* Check exFAT revision (Must be 1.0) */
+
+		if (1 << fs->win[BPB_BytsPerSecEx] != SS(fs)) {	/* (BPB_BytsPerSecEx must be equal to the physical sector size) */
+			return FR_NO_FILESYSTEM;
+		}
+
+		maxlba = ld_qword(fs->win + BPB_TotSecEx) + bsect;	/* Last LBA + 1 of the volume */
+		if (maxlba >= 0x100000000) return FR_NO_FILESYSTEM;	/* (It cannot be handled in 32-bit LBA) */
+
+		fs->fsize = ld_dword(fs->win + BPB_FatSzEx);	/* Number of sectors per FAT */
+
+		fs->n_fats = fs->win[BPB_NumFATsEx];			/* Number of FATs */
+		if (fs->n_fats != 1) return FR_NO_FILESYSTEM;	/* (Supports only 1 FAT) */
+
+		fs->csize = 1 << fs->win[BPB_SecPerClusEx];		/* Cluster size */
+		if (fs->csize == 0)	return FR_NO_FILESYSTEM;	/* (Must be 1..32768) */
+
+		nclst = ld_dword(fs->win + BPB_NumClusEx);		/* Number of clusters */
+		if (nclst > MAX_EXFAT) return FR_NO_FILESYSTEM;	/* (Too many clusters) */
+		fs->n_fatent = nclst + 2;
+
+		/* Boundaries and Limits */
+		fs->volbase = bsect;
+		fs->database = bsect + ld_dword(fs->win + BPB_DataOfsEx);
+		fs->fatbase = bsect + ld_dword(fs->win + BPB_FatOfsEx);
+		if (maxlba < (QWORD)fs->database + nclst * fs->csize) return FR_NO_FILESYSTEM;	/* (Volume size must not be smaller than the size requiered) */
+		fs->dirbase = ld_dword(fs->win + BPB_RootClusEx);
+
+		/* Check if bitmap location is in assumption (at the first cluster) */
+		if (move_window(fs, clust2sect(fs, fs->dirbase)) != FR_OK) return FR_DISK_ERR;
+		for (i = 0; i < SS(fs); i += SZDIRE) {
+			if (fs->win[i] == 0x81 && ld_dword(fs->win + i + 20) == 2) break;	/* 81 entry with cluster #2? */
+		}
+		if (i == SS(fs)) return FR_NO_FILESYSTEM;
+#if !_FS_READONLY
+		fs->last_clst = fs->free_clst = 0xFFFFFFFF;		/* Initialize cluster allocation information */
+#endif
+		fmt = FS_EXFAT;			/* FAT sub-type */
+	} else
+#endif	/* _FS_EXFAT */
+	{
+		if (ld_word(fs->win + BPB_BytsPerSec) != SS(fs)) return FR_NO_FILESYSTEM;	/* (BPB_BytsPerSec must be equal to the physical sector size) */
+
+		fasize = ld_word(fs->win + BPB_FATSz16);		/* Number of sectors per FAT */
+		if (fasize == 0) fasize = ld_dword(fs->win + BPB_FATSz32);
+		fs->fsize = fasize;
+
+		fs->n_fats = fs->win[BPB_NumFATs];				/* Number of FATs */
+		if (fs->n_fats != 1 && fs->n_fats != 2) return FR_NO_FILESYSTEM;	/* (Must be 1 or 2) */
+		fasize *= fs->n_fats;							/* Number of sectors for FAT area */
+
+		fs->csize = fs->win[BPB_SecPerClus];			/* Cluster size */
+		if (fs->csize == 0 || (fs->csize & (fs->csize - 1))) return FR_NO_FILESYSTEM;	/* (Must be power of 2) */
+
+		fs->n_rootdir = ld_word(fs->win + BPB_RootEntCnt);	/* Number of root directory entries */
+		if (fs->n_rootdir % (SS(fs) / SZDIRE)) return FR_NO_FILESYSTEM;	/* (Must be sector aligned) */
+
+		tsect = ld_word(fs->win + BPB_TotSec16);		/* Number of sectors on the volume */
+		if (tsect == 0) tsect = ld_dword(fs->win + BPB_TotSec32);
+
+		nrsv = ld_word(fs->win + BPB_RsvdSecCnt);		/* Number of reserved sectors */
+		if (nrsv == 0) return FR_NO_FILESYSTEM;			/* (Must not be 0) */
+
+		/* Determine the FAT sub type */
+		sysect = nrsv + fasize + fs->n_rootdir / (SS(fs) / SZDIRE);	/* RSV + FAT + DIR */
+		if (tsect < sysect) return FR_NO_FILESYSTEM;	/* (Invalid volume size) */
+		nclst = (tsect - sysect) / fs->csize;			/* Number of clusters */
+		if (nclst == 0) return FR_NO_FILESYSTEM;		/* (Invalid volume size) */
+		fmt = FS_FAT32;
+		if (nclst <= MAX_FAT16) fmt = FS_FAT16;
+		if (nclst <= MAX_FAT12) fmt = FS_FAT12;
+
+		/* Boundaries and Limits */
+		fs->n_fatent = nclst + 2;						/* Number of FAT entries */
+		fs->volbase = bsect;							/* Volume start sector */
+		fs->fatbase = bsect + nrsv; 					/* FAT start sector */
+		fs->database = bsect + sysect;					/* Data start sector */
+		if (fmt == FS_FAT32) {
+			if (ld_word(fs->win + BPB_FSVer32) != 0) return FR_NO_FILESYSTEM;	/* (Must be FAT32 revision 0.0) */
+			if (fs->n_rootdir) return FR_NO_FILESYSTEM;	/* (BPB_RootEntCnt must be 0) */
+			fs->dirbase = ld_dword(fs->win + BPB_RootClus32);	/* Root directory start cluster */
+			szbfat = fs->n_fatent * 4;					/* (Needed FAT size) */
+		} else {
+			if (fs->n_rootdir == 0)	return FR_NO_FILESYSTEM;/* (BPB_RootEntCnt must not be 0) */
+			fs->dirbase = fs->fatbase + fasize;			/* Root directory start sector */
+			szbfat = (fmt == FS_FAT16) ?				/* (Needed FAT size) */
+				fs->n_fatent * 2 : fs->n_fatent * 3 / 2 + (fs->n_fatent & 1);
+		}
+		if (fs->fsize < (szbfat + (SS(fs) - 1)) / SS(fs)) return FR_NO_FILESYSTEM;	/* (BPB_FATSz must not be less than the size needed) */
+
+#if !_FS_READONLY
+		/* Get FSINFO if available */
+		fs->last_clst = fs->free_clst = 0xFFFFFFFF;		/* Initialize cluster allocation information */
+		fs->fsi_flag = 0x80;
+#if (_FS_NOFSINFO & 3) != 3
+		if (fmt == FS_FAT32				/* Enable FSINFO only if FAT32 and BPB_FSInfo32 == 1 */
+			&& ld_word(fs->win + BPB_FSInfo32) == 1
+			&& move_window(fs, bsect + 1) == FR_OK)
+		{
+			fs->fsi_flag = 0;
+			if (ld_word(fs->win + BS_55AA) == 0xAA55	/* Load FSINFO data if available */
+				&& ld_dword(fs->win + FSI_LeadSig) == 0x41615252
+				&& ld_dword(fs->win + FSI_StrucSig) == 0x61417272)
+			{
+#if (_FS_NOFSINFO & 1) == 0
+				fs->free_clst = ld_dword(fs->win + FSI_Free_Count);
+#endif
+#if (_FS_NOFSINFO & 2) == 0
+				fs->last_clst = ld_dword(fs->win + FSI_Nxt_Free);
+#endif
+			}
+		}
+#endif	/* (_FS_NOFSINFO & 3) != 3 */
+#endif	/* !_FS_READONLY */
+	}
+
+	fs->fs_type = fmt;		/* FAT sub-type */
+	fs->id = ++Fsid;		/* File system mount ID */
+#if _USE_LFN == 1
+	fs->lfnbuf = LfnBuf;	/* Static LFN working buffer */
+#if _FS_EXFAT
+	fs->dirbuf = DirBuf;	/* Static directory block scratchpad buuffer */
+#endif
+#endif
+#if _FS_RPATH != 0
+	fs->cdir = 0;			/* Initialize current directory */
+#endif
+#if _FS_LOCK != 0			/* Clear file lock semaphores */
+	clear_lock(fs);
+#endif
+	return FR_OK;
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Check if the file/directory object is valid or not                    */
+/*-----------------------------------------------------------------------*/
+
+static
+FRESULT validate (	/* Returns FR_OK or FR_INVALID_OBJECT */
+	_FDID* obj,		/* Pointer to the _OBJ, the 1st member in the FIL/DIR object, to check validity */
+	FATFS** fs		/* Pointer to pointer to the owner file system object to return */
+)
+{
+	FRESULT res = FR_INVALID_OBJECT;
+
+
+	if (obj && obj->fs && obj->fs->fs_type && obj->id == obj->fs->id) {	/* Test if the object is valid */
+#if _FS_REENTRANT
+		if (lock_fs(obj->fs)) {	/* Obtain the filesystem object */
+			if (!(disk_status(obj->fs->drv) & STA_NOINIT)) { /* Test if the phsical drive is kept initialized */
+				res = FR_OK;
+			} else {
+				unlock_fs(obj->fs, FR_OK);
+			}
+		} else {
+			res = FR_TIMEOUT;
+		}
+#else
+		if (!(disk_status(obj->fs->drv) & STA_NOINIT)) { /* Test if the phsical drive is kept initialized */
+			res = FR_OK;
+		}
+#endif
+	}
+	*fs = (res == FR_OK) ? obj->fs : 0;	/* Corresponding filesystem object */
+	return res;
+}
+
+
+
+
+/*---------------------------------------------------------------------------
+
+   Public Functions (FatFs API)
+
+----------------------------------------------------------------------------*/
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Mount/Unmount a Logical Drive                                         */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_mount (
+	FATFS* fs,			/* Pointer to the file system object (NULL:unmount)*/
+	const TCHAR* path,	/* Logical drive number to be mounted/unmounted */
+	BYTE opt			/* Mode option 0:Do not mount (delayed mount), 1:Mount immediately */
+)
+{
+	FATFS *cfs;
+	int vol;
+	FRESULT res;
+	const TCHAR *rp = path;
+
+
+	/* Get logical drive number */
+	vol = get_ldnumber(&rp);
+	if (vol < 0) return FR_INVALID_DRIVE;
+	cfs = FatFs[vol];					/* Pointer to fs object */
+
+	if (cfs) {
+#if _FS_LOCK != 0
+		clear_lock(cfs);
+#endif
+#if _FS_REENTRANT						/* Discard sync object of the current volume */
+		if (!ff_del_syncobj(cfs->sobj)) return FR_INT_ERR;
+#endif
+		cfs->fs_type = 0;				/* Clear old fs object */
+	}
+
+	if (fs) {
+		fs->fs_type = 0;				/* Clear new fs object */
+#if _FS_REENTRANT						/* Create sync object for the new volume */
+		if (!ff_cre_syncobj((BYTE)vol, &fs->sobj)) return FR_INT_ERR;
+#endif
+	}
+	FatFs[vol] = fs;					/* Register new fs object */
+
+	if (!fs || opt != 1) return FR_OK;	/* Do not mount now, it will be mounted later */
+
+	res = find_volume(&path, &fs, 0);	/* Force mounted the volume */
+	LEAVE_FF(fs, res);
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Open or Create a File                                                 */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_open (
+	FIL* fp,			/* Pointer to the blank file object */
+	const TCHAR* path,	/* Pointer to the file name */
+	BYTE mode			/* Access mode and file open mode flags */
+)
+{
+	FRESULT res;
+	DIR dj;
+	FATFS *fs;
+#if !_FS_READONLY
+	DWORD dw, cl, bcs, clst, sc;
+	FSIZE_t ofs;
+#endif
+	DEF_NAMBUF
+
+
+	if (!fp) return FR_INVALID_OBJECT;
+
+	/* Get logical drive */
+	mode &= _FS_READONLY ? FA_READ : FA_READ | FA_WRITE | FA_CREATE_ALWAYS | FA_CREATE_NEW | FA_OPEN_ALWAYS | FA_OPEN_APPEND | FA_SEEKEND;
+	res = find_volume(&path, &fs, mode);
+	if (res == FR_OK) {
+		dj.obj.fs = fs;
+		INIT_NAMBUF(fs);
+		res = follow_path(&dj, path);	/* Follow the file path */
+#if !_FS_READONLY	/* R/W configuration */
+		if (res == FR_OK) {
+			if (dj.fn[NSFLAG] & NS_NONAME) {	/* Origin directory itself? */
+				res = FR_INVALID_NAME;
+			}
+#if _FS_LOCK != 0
+			else {
+				res = chk_lock(&dj, (mode & ~FA_READ) ? 1 : 0);
+			}
+#endif
+		}
+		/* Create or Open a file */
+		if (mode & (FA_CREATE_ALWAYS | FA_OPEN_ALWAYS | FA_CREATE_NEW)) {
+			if (res != FR_OK) {					/* No file, create new */
+				if (res == FR_NO_FILE) {		/* There is no file to open, create a new entry */
+#if _FS_LOCK != 0
+					res = enq_lock() ? dir_register(&dj) : FR_TOO_MANY_OPEN_FILES;
+#else
+					res = dir_register(&dj);
+#endif
+				}
+				mode |= FA_CREATE_ALWAYS;		/* File is created */
+			}
+			else {								/* Any object is already existing */
+				if (dj.obj.attr & (AM_RDO | AM_DIR)) {	/* Cannot overwrite it (R/O or DIR) */
+					res = FR_DENIED;
+				} else {
+					if (mode & FA_CREATE_NEW) res = FR_EXIST;	/* Cannot create as new file */
+				}
+			}
+			if (res == FR_OK && (mode & FA_CREATE_ALWAYS)) {	/* Truncate it if overwrite mode */
+				dw = GET_FATTIME();
+#if _FS_EXFAT
+				if (fs->fs_type == FS_EXFAT) {
+					/* Get current allocation info */
+					fp->obj.fs = fs;
+					fp->obj.sclust = ld_dword(fs->dirbuf + XDIR_FstClus);
+					fp->obj.objsize = ld_qword(fs->dirbuf + XDIR_FileSize);
+					fp->obj.stat = fs->dirbuf[XDIR_GenFlags] & 2;
+					fp->obj.n_frag = 0;
+					/* Initialize directory entry block */
+					st_dword(fs->dirbuf + XDIR_CrtTime, dw);	/* Set created time */
+					fs->dirbuf[XDIR_CrtTime10] = 0;
+					st_dword(fs->dirbuf + XDIR_ModTime, dw);	/* Set modified time */
+					fs->dirbuf[XDIR_ModTime10] = 0;
+					fs->dirbuf[XDIR_Attr] = AM_ARC;				/* Reset attribute */
+					st_dword(fs->dirbuf + XDIR_FstClus, 0);		/* Reset file allocation info */
+					st_qword(fs->dirbuf + XDIR_FileSize, 0);
+					st_qword(fs->dirbuf + XDIR_ValidFileSize, 0);
+					fs->dirbuf[XDIR_GenFlags] = 1;
+					res = store_xdir(&dj);
+					if (res == FR_OK && fp->obj.sclust) {		/* Remove the cluster chain if exist */
+						res = remove_chain(&fp->obj, fp->obj.sclust, 0);
+						fs->last_clst = fp->obj.sclust - 1;		/* Reuse the cluster hole */
+					}
+				} else
+#endif
+				{
+					/* Clean directory info */
+					st_dword(dj.dir + DIR_CrtTime, dw);	/* Set created time */
+					st_dword(dj.dir + DIR_ModTime, dw);	/* Set modified time */
+					dj.dir[DIR_Attr] = AM_ARC;			/* Reset attribute */
+					cl = ld_clust(fs, dj.dir);			/* Get cluster chain */
+					st_clust(fs, dj.dir, 0);			/* Reset file allocation info */
+					st_dword(dj.dir + DIR_FileSize, 0);
+					fs->wflag = 1;
+
+					if (cl) {							/* Remove the cluster chain if exist */
+						dw = fs->winsect;
+						res = remove_chain(&dj.obj, cl, 0);
+						if (res == FR_OK) {
+							res = move_window(fs, dw);
+							fs->last_clst = cl - 1;		/* Reuse the cluster hole */
+						}
+					}
+				}
+			}
+		}
+		else {	/* Open an existing file */
+			if (res == FR_OK) {					/* Following succeeded */
+				if (dj.obj.attr & AM_DIR) {		/* It is a directory */
+					res = FR_NO_FILE;
+				} else {
+					if ((mode & FA_WRITE) && (dj.obj.attr & AM_RDO)) { /* R/O violation */
+						res = FR_DENIED;
+					}
+				}
+			}
+		}
+		if (res == FR_OK) {
+			if (mode & FA_CREATE_ALWAYS)		/* Set file change flag if created or overwritten */
+				mode |= FA_MODIFIED;
+			fp->dir_sect = fs->winsect;			/* Pointer to the directory entry */
+			fp->dir_ptr = dj.dir;
+#if _FS_LOCK != 0
+			fp->obj.lockid = inc_lock(&dj, (mode & ~FA_READ) ? 1 : 0);
+			if (!fp->obj.lockid) res = FR_INT_ERR;
+#endif
+		}
+#else		/* R/O configuration */
+		if (res == FR_OK) {
+			if (dj.fn[NSFLAG] & NS_NONAME) {	/* Origin directory itself? */
+				res = FR_INVALID_NAME;
+			} else {
+				if (dj.obj.attr & AM_DIR) {		/* It is a directory */
+					res = FR_NO_FILE;
+				}
+			}
+		}
+#endif
+
+		if (res == FR_OK) {
+#if _FS_EXFAT
+			if (fs->fs_type == FS_EXFAT) {
+				fp->obj.c_scl = dj.obj.sclust;							/* Get containing directory info */
+				fp->obj.c_size = ((DWORD)dj.obj.objsize & 0xFFFFFF00) | dj.obj.stat;
+				fp->obj.c_ofs = dj.blk_ofs;
+				fp->obj.sclust = ld_dword(fs->dirbuf + XDIR_FstClus);	/* Get object allocation info */
+				fp->obj.objsize = ld_qword(fs->dirbuf + XDIR_FileSize);
+				fp->obj.stat = fs->dirbuf[XDIR_GenFlags] & 2;
+			} else
+#endif
+			{
+				fp->obj.sclust = ld_clust(fs, dj.dir);					/* Get object allocation info */
+				fp->obj.objsize = ld_dword(dj.dir + DIR_FileSize);
+			}
+#if _USE_FASTSEEK
+			fp->cltbl = 0;			/* Disable fast seek mode */
+#endif
+			fp->obj.fs = fs;	 	/* Validate the file object */
+			fp->obj.id = fs->id;
+			fp->flag = mode;		/* Set file access mode */
+			fp->err = 0;			/* Clear error flag */
+			fp->sect = 0;			/* Invalidate current data sector */
+			fp->fptr = 0;			/* Set file pointer top of the file */
+#if !_FS_READONLY
+#if !_FS_TINY
+			mem_set(fp->buf, 0, _MAX_SS);	/* Clear sector buffer */
+#endif
+			if ((mode & FA_SEEKEND) && fp->obj.objsize > 0) {	/* Seek to end of file if FA_OPEN_APPEND is specified */
+				fp->fptr = fp->obj.objsize;			/* Offset to seek */
+				bcs = (DWORD)fs->csize * SS(fs);	/* Cluster size in byte */
+				clst = fp->obj.sclust;				/* Follow the cluster chain */
+				for (ofs = fp->obj.objsize; res == FR_OK && ofs > bcs; ofs -= bcs) {
+					clst = get_fat(&fp->obj, clst);
+					if (clst <= 1) res = FR_INT_ERR;
+					if (clst == 0xFFFFFFFF) res = FR_DISK_ERR;
+				}
+				fp->clust = clst;
+				if (res == FR_OK && ofs % SS(fs)) {	/* Fill sector buffer if not on the sector boundary */
+					if ((sc = clust2sect(fs, clst)) == 0) {
+						res = FR_INT_ERR;
+					} else {
+						fp->sect = sc + (DWORD)(ofs / SS(fs));
+#if !_FS_TINY
+						if (disk_read(fs->drv, fp->buf, fp->sect, 1) != RES_OK) res = FR_DISK_ERR;
+#endif
+					}
+				}
+			}
+#endif
+		}
+
+		FREE_NAMBUF();
+	}
+
+	if (res != FR_OK) fp->obj.fs = 0;	/* Invalidate file object on error */
+
+	LEAVE_FF(fs, res);
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Read File                                                             */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_read (
+	FIL* fp, 	/* Pointer to the file object */
+	void* buff,	/* Pointer to data buffer */
+	UINT btr,	/* Number of bytes to read */
+	UINT* br	/* Pointer to number of bytes read */
+)
+{
+	FRESULT res;
+	FATFS *fs;
+	DWORD clst, sect;
+	FSIZE_t remain;
+	UINT rcnt, cc, csect;
+	BYTE *rbuff = (BYTE*)buff;
+
+
+	*br = 0;	/* Clear read byte counter */
+	res = validate(&fp->obj, &fs);				/* Check validity of the file object */
+	if (res != FR_OK || (res = (FRESULT)fp->err) != FR_OK) LEAVE_FF(fs, res);	/* Check validity */
+	if (!(fp->flag & FA_READ)) LEAVE_FF(fs, FR_DENIED); /* Check access mode */
+	remain = fp->obj.objsize - fp->fptr;
+	if (btr > remain) btr = (UINT)remain;		/* Truncate btr by remaining bytes */
+
+	for ( ;  btr;								/* Repeat until all data read */
+		rbuff += rcnt, fp->fptr += rcnt, *br += rcnt, btr -= rcnt) {
+		if (fp->fptr % SS(fs) == 0) {			/* On the sector boundary? */
+			csect = (UINT)(fp->fptr / SS(fs) & (fs->csize - 1));	/* Sector offset in the cluster */
+			if (csect == 0) {					/* On the cluster boundary? */
+				if (fp->fptr == 0) {			/* On the top of the file? */
+					clst = fp->obj.sclust;		/* Follow cluster chain from the origin */
+				} else {						/* Middle or end of the file */
+#if _USE_FASTSEEK
+					if (fp->cltbl) {
+						clst = clmt_clust(fp, fp->fptr);	/* Get cluster# from the CLMT */
+					} else
+#endif
+					{
+						clst = get_fat(&fp->obj, fp->clust);	/* Follow cluster chain on the FAT */
+					}
+				}
+				if (clst < 2) ABORT(fs, FR_INT_ERR);
+				if (clst == 0xFFFFFFFF) ABORT(fs, FR_DISK_ERR);
+				fp->clust = clst;				/* Update current cluster */
+			}
+			sect = clust2sect(fs, fp->clust);	/* Get current sector */
+			if (!sect) ABORT(fs, FR_INT_ERR);
+			sect += csect;
+			cc = btr / SS(fs);					/* When remaining bytes >= sector size, */
+			if (cc) {							/* Read maximum contiguous sectors directly */
+				if (csect + cc > fs->csize) {	/* Clip at cluster boundary */
+					cc = fs->csize - csect;
+				}
+				if (disk_read(fs->drv, rbuff, sect, cc) != RES_OK) ABORT(fs, FR_DISK_ERR);
+#if !_FS_READONLY && _FS_MINIMIZE <= 2			/* Replace one of the read sectors with cached data if it contains a dirty sector */
+#if _FS_TINY
+				if (fs->wflag && fs->winsect - sect < cc) {
+					mem_cpy(rbuff + ((fs->winsect - sect) * SS(fs)), fs->win, SS(fs));
+				}
+#else
+				if ((fp->flag & FA_DIRTY) && fp->sect - sect < cc) {
+					mem_cpy(rbuff + ((fp->sect - sect) * SS(fs)), fp->buf, SS(fs));
+				}
+#endif
+#endif
+				rcnt = SS(fs) * cc;				/* Number of bytes transferred */
+				continue;
+			}
+#if !_FS_TINY
+			if (fp->sect != sect) {			/* Load data sector if not in cache */
+#if !_FS_READONLY
+				if (fp->flag & FA_DIRTY) {		/* Write-back dirty sector cache */
+					if (disk_write(fs->drv, fp->buf, fp->sect, 1) != RES_OK) ABORT(fs, FR_DISK_ERR);
+					fp->flag &= (BYTE)~FA_DIRTY;
+				}
+#endif
+				if (disk_read(fs->drv, fp->buf, sect, 1) != RES_OK)	ABORT(fs, FR_DISK_ERR);	/* Fill sector cache */
+			}
+#endif
+			fp->sect = sect;
+		}
+		rcnt = SS(fs) - (UINT)fp->fptr % SS(fs);	/* Number of bytes left in the sector */
+		if (rcnt > btr) rcnt = btr;					/* Clip it by btr if needed */
+#if _FS_TINY
+		if (move_window(fs, fp->sect) != FR_OK) ABORT(fs, FR_DISK_ERR);	/* Move sector window */
+		mem_cpy(rbuff, fs->win + fp->fptr % SS(fs), rcnt);	/* Extract partial sector */
+#else
+		mem_cpy(rbuff, fp->buf + fp->fptr % SS(fs), rcnt);	/* Extract partial sector */
+#endif
+	}
+
+	LEAVE_FF(fs, FR_OK);
+}
+
+
+
+
+#if !_FS_READONLY
+/*-----------------------------------------------------------------------*/
+/* Write File                                                            */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_write (
+	FIL* fp,			/* Pointer to the file object */
+	const void* buff,	/* Pointer to the data to be written */
+	UINT btw,			/* Number of bytes to write */
+	UINT* bw			/* Pointer to number of bytes written */
+)
+{
+	FRESULT res;
+	FATFS *fs;
+	DWORD clst, sect;
+	UINT wcnt, cc, csect;
+	const BYTE *wbuff = (const BYTE*)buff;
+
+
+	*bw = 0;	/* Clear write byte counter */
+	res = validate(&fp->obj, &fs);			/* Check validity of the file object */
+	if (res != FR_OK || (res = (FRESULT)fp->err) != FR_OK) LEAVE_FF(fs, res);	/* Check validity */
+	if (!(fp->flag & FA_WRITE)) LEAVE_FF(fs, FR_DENIED);	/* Check access mode */
+
+	/* Check fptr wrap-around (file size cannot reach 4GiB on FATxx) */
+	if ((!_FS_EXFAT || fs->fs_type != FS_EXFAT) && (DWORD)(fp->fptr + btw) < (DWORD)fp->fptr) {
+		btw = (UINT)(0xFFFFFFFF - (DWORD)fp->fptr);
+	}
+
+	for ( ;  btw;							/* Repeat until all data written */
+		wbuff += wcnt, fp->fptr += wcnt, fp->obj.objsize = (fp->fptr > fp->obj.objsize) ? fp->fptr : fp->obj.objsize, *bw += wcnt, btw -= wcnt) {
+		if (fp->fptr % SS(fs) == 0) {		/* On the sector boundary? */
+			csect = (UINT)(fp->fptr / SS(fs)) & (fs->csize - 1);	/* Sector offset in the cluster */
+			if (csect == 0) {				/* On the cluster boundary? */
+				if (fp->fptr == 0) {		/* On the top of the file? */
+					clst = fp->obj.sclust;	/* Follow from the origin */
+					if (clst == 0) {		/* If no cluster is allocated, */
+						clst = create_chain(&fp->obj, 0);	/* create a new cluster chain */
+					}
+				} else {					/* On the middle or end of the file */
+#if _USE_FASTSEEK
+					if (fp->cltbl) {
+						clst = clmt_clust(fp, fp->fptr);	/* Get cluster# from the CLMT */
+					} else
+#endif
+					{
+						clst = create_chain(&fp->obj, fp->clust);	/* Follow or stretch cluster chain on the FAT */
+					}
+				}
+				if (clst == 0) break;		/* Could not allocate a new cluster (disk full) */
+				if (clst == 1) ABORT(fs, FR_INT_ERR);
+				if (clst == 0xFFFFFFFF) ABORT(fs, FR_DISK_ERR);
+				fp->clust = clst;			/* Update current cluster */
+				if (fp->obj.sclust == 0) fp->obj.sclust = clst;	/* Set start cluster if the first write */
+			}
+#if _FS_TINY
+			if (fs->winsect == fp->sect && sync_window(fs) != FR_OK) ABORT(fs, FR_DISK_ERR);	/* Write-back sector cache */
+#else
+			if (fp->flag & FA_DIRTY) {		/* Write-back sector cache */
+				if (disk_write(fs->drv, fp->buf, fp->sect, 1) != RES_OK) ABORT(fs, FR_DISK_ERR);
+				fp->flag &= (BYTE)~FA_DIRTY;
+			}
+#endif
+			sect = clust2sect(fs, fp->clust);	/* Get current sector */
+			if (!sect) ABORT(fs, FR_INT_ERR);
+			sect += csect;
+			cc = btw / SS(fs);				/* When remaining bytes >= sector size, */
+			if (cc) {						/* Write maximum contiguous sectors directly */
+				if (csect + cc > fs->csize) {	/* Clip at cluster boundary */
+					cc = fs->csize - csect;
+				}
+				if (disk_write(fs->drv, wbuff, sect, cc) != RES_OK) ABORT(fs, FR_DISK_ERR);
+#if _FS_MINIMIZE <= 2
+#if _FS_TINY
+				if (fs->winsect - sect < cc) {	/* Refill sector cache if it gets invalidated by the direct write */
+					mem_cpy(fs->win, wbuff + ((fs->winsect - sect) * SS(fs)), SS(fs));
+					fs->wflag = 0;
+				}
+#else
+				if (fp->sect - sect < cc) { /* Refill sector cache if it gets invalidated by the direct write */
+					mem_cpy(fp->buf, wbuff + ((fp->sect - sect) * SS(fs)), SS(fs));
+					fp->flag &= (BYTE)~FA_DIRTY;
+				}
+#endif
+#endif
+				wcnt = SS(fs) * cc;		/* Number of bytes transferred */
+				continue;
+			}
+#if _FS_TINY
+			if (fp->fptr >= fp->obj.objsize) {	/* Avoid silly cache filling on the growing edge */
+				if (sync_window(fs) != FR_OK) ABORT(fs, FR_DISK_ERR);
+				fs->winsect = sect;
+			}
+#else
+			if (fp->sect != sect && 		/* Fill sector cache with file data */
+				fp->fptr < fp->obj.objsize &&
+				disk_read(fs->drv, fp->buf, sect, 1) != RES_OK) {
+					ABORT(fs, FR_DISK_ERR);
+			}
+#endif
+			fp->sect = sect;
+		}
+		wcnt = SS(fs) - (UINT)fp->fptr % SS(fs);	/* Number of bytes left in the sector */
+		if (wcnt > btw) wcnt = btw;					/* Clip it by btw if needed */
+#if _FS_TINY
+		if (move_window(fs, fp->sect) != FR_OK) ABORT(fs, FR_DISK_ERR);	/* Move sector window */
+		mem_cpy(fs->win + fp->fptr % SS(fs), wbuff, wcnt);	/* Fit data to the sector */
+		fs->wflag = 1;
+#else
+		mem_cpy(fp->buf + fp->fptr % SS(fs), wbuff, wcnt);	/* Fit data to the sector */
+		fp->flag |= FA_DIRTY;
+#endif
+	}
+
+	fp->flag |= FA_MODIFIED;				/* Set file change flag */
+
+	LEAVE_FF(fs, FR_OK);
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Synchronize the File                                                  */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_sync (
+	FIL* fp		/* Pointer to the file object */
+)
+{
+	FRESULT res;
+	FATFS *fs;
+	DWORD tm;
+	BYTE *dir;
+#if _FS_EXFAT
+	DIR dj;
+	DEF_NAMBUF
+#endif
+
+	res = validate(&fp->obj, &fs);	/* Check validity of the file object */
+	if (res == FR_OK) {
+		if (fp->flag & FA_MODIFIED) {	/* Is there any change to the file? */
+#if !_FS_TINY
+			if (fp->flag & FA_DIRTY) {	/* Write-back cached data if needed */
+				if (disk_write(fs->drv, fp->buf, fp->sect, 1) != RES_OK) LEAVE_FF(fs, FR_DISK_ERR);
+				fp->flag &= (BYTE)~FA_DIRTY;
+			}
+#endif
+			/* Update the directory entry */
+			tm = GET_FATTIME();				/* Modified time */
+#if _FS_EXFAT
+			if (fs->fs_type == FS_EXFAT) {
+				res = fill_first_frag(&fp->obj);	/* Fill first fragment on the FAT if needed */
+				if (res == FR_OK) {
+					res = fill_last_frag(&fp->obj, fp->clust, 0xFFFFFFFF);	/* Fill last fragment on the FAT if needed */
+				}
+				if (res == FR_OK) {
+					INIT_NAMBUF(fs);
+					res = load_obj_dir(&dj, &fp->obj);	/* Load directory entry block */
+					if (res == FR_OK) {
+						fs->dirbuf[XDIR_Attr] |= AM_ARC;				/* Set archive bit */
+						fs->dirbuf[XDIR_GenFlags] = fp->obj.stat | 1;	/* Update file allocation info */
+						st_dword(fs->dirbuf + XDIR_FstClus, fp->obj.sclust);
+						st_qword(fs->dirbuf + XDIR_FileSize, fp->obj.objsize);
+						st_qword(fs->dirbuf + XDIR_ValidFileSize, fp->obj.objsize);
+						st_dword(fs->dirbuf + XDIR_ModTime, tm);		/* Update modified time */
+						fs->dirbuf[XDIR_ModTime10] = 0;
+						st_dword(fs->dirbuf + XDIR_AccTime, 0);
+						res = store_xdir(&dj);	/* Restore it to the directory */
+						if (res == FR_OK) {
+							res = sync_fs(fs);
+							fp->flag &= (BYTE)~FA_MODIFIED;
+						}
+					}
+					FREE_NAMBUF();
+				}
+			} else
+#endif
+			{
+				res = move_window(fs, fp->dir_sect);
+				if (res == FR_OK) {
+					dir = fp->dir_ptr;
+					dir[DIR_Attr] |= AM_ARC;						/* Set archive bit */
+					st_clust(fp->obj.fs, dir, fp->obj.sclust);		/* Update file allocation info  */
+					st_dword(dir + DIR_FileSize, (DWORD)fp->obj.objsize);	/* Update file size */
+					st_dword(dir + DIR_ModTime, tm);				/* Update modified time */
+					st_word(dir + DIR_LstAccDate, 0);
+					fs->wflag = 1;
+					res = sync_fs(fs);					/* Restore it to the directory */
+					fp->flag &= (BYTE)~FA_MODIFIED;
+				}
+			}
+		}
+	}
+
+	LEAVE_FF(fs, res);
+}
+
+#endif /* !_FS_READONLY */
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Close File                                                            */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_close (
+	FIL* fp		/* Pointer to the file object to be closed */
+)
+{
+	FRESULT res;
+	FATFS *fs;
+
+#if !_FS_READONLY
+	res = f_sync(fp);					/* Flush cached data */
+	if (res == FR_OK)
+#endif
+	{
+		res = validate(&fp->obj, &fs);	/* Lock volume */
+		if (res == FR_OK) {
+#if _FS_LOCK != 0
+			res = dec_lock(fp->obj.lockid);	/* Decrement file open counter */
+			if (res == FR_OK)
+#endif
+			{
+				fp->obj.fs = 0;			/* Invalidate file object */
+			}
+#if _FS_REENTRANT
+			unlock_fs(fs, FR_OK);		/* Unlock volume */
+#endif
+		}
+	}
+	return res;
+}
+
+
+
+
+#if _FS_RPATH >= 1
+/*-----------------------------------------------------------------------*/
+/* Change Current Directory or Current Drive, Get Current Directory      */
+/*-----------------------------------------------------------------------*/
+
+#if _VOLUMES >= 2
+FRESULT f_chdrive (
+	const TCHAR* path		/* Drive number */
+)
+{
+	int vol;
+
+
+	/* Get logical drive number */
+	vol = get_ldnumber(&path);
+	if (vol < 0) return FR_INVALID_DRIVE;
+
+	CurrVol = (BYTE)vol;	/* Set it as current volume */
+
+	return FR_OK;
+}
+#endif
+
+
+FRESULT f_chdir (
+	const TCHAR* path	/* Pointer to the directory path */
+)
+{
+	FRESULT res;
+	DIR dj;
+	FATFS *fs;
+	DEF_NAMBUF
+
+	/* Get logical drive */
+	res = find_volume(&path, &fs, 0);
+	if (res == FR_OK) {
+		dj.obj.fs = fs;
+		INIT_NAMBUF(fs);
+		res = follow_path(&dj, path);		/* Follow the path */
+		if (res == FR_OK) {					/* Follow completed */
+			if (dj.fn[NSFLAG] & NS_NONAME) {
+				fs->cdir = dj.obj.sclust;	/* It is the start directory itself */
+#if _FS_EXFAT
+				if (fs->fs_type == FS_EXFAT) {
+					fs->cdc_scl = dj.obj.c_scl;
+					fs->cdc_size = dj.obj.c_size;
+					fs->cdc_ofs = dj.obj.c_ofs;
+				}
+#endif
+			} else {
+				if (dj.obj.attr & AM_DIR) {	/* It is a sub-directory */
+#if _FS_EXFAT
+					if (fs->fs_type == FS_EXFAT) {
+						fs->cdir = ld_dword(fs->dirbuf + XDIR_FstClus);		/* Sub-directory cluster */
+						fs->cdc_scl = dj.obj.sclust;						/* Save containing directory information */
+						fs->cdc_size = ((DWORD)dj.obj.objsize & 0xFFFFFF00) | dj.obj.stat;
+						fs->cdc_ofs = dj.blk_ofs;
+					} else
+#endif
+					{
+						fs->cdir = ld_clust(fs, dj.dir);					/* Sub-directory cluster */
+					}
+				} else {
+					res = FR_NO_PATH;		/* Reached but a file */
+				}
+			}
+		}
+		FREE_NAMBUF();
+		if (res == FR_NO_FILE) res = FR_NO_PATH;
+	}
+
+	LEAVE_FF(fs, res);
+}
+
+
+#if _FS_RPATH >= 2
+FRESULT f_getcwd (
+	TCHAR* buff,	/* Pointer to the directory path */
+	UINT len		/* Size of path */
+)
+{
+	FRESULT res;
+	DIR dj;
+	FATFS *fs;
+	UINT i, n;
+	DWORD ccl;
+	TCHAR *tp;
+	FILINFO fno;
+	DEF_NAMBUF
+
+
+	*buff = 0;
+	/* Get logical drive */
+	res = find_volume((const TCHAR**)&buff, &fs, 0);	/* Get current volume */
+	if (res == FR_OK) {
+		dj.obj.fs = fs;
+		INIT_NAMBUF(fs);
+		i = len;			/* Bottom of buffer (directory stack base) */
+		if (!_FS_EXFAT || fs->fs_type != FS_EXFAT) {	/* (Cannot do getcwd on exFAT and returns root path) */
+			dj.obj.sclust = fs->cdir;				/* Start to follow upper directory from current directory */
+			while ((ccl = dj.obj.sclust) != 0) {	/* Repeat while current directory is a sub-directory */
+				res = dir_sdi(&dj, 1 * SZDIRE);	/* Get parent directory */
+				if (res != FR_OK) break;
+				res = move_window(fs, dj.sect);
+				if (res != FR_OK) break;
+				dj.obj.sclust = ld_clust(fs, dj.dir);	/* Goto parent directory */
+				res = dir_sdi(&dj, 0);
+				if (res != FR_OK) break;
+				do {							/* Find the entry links to the child directory */
+					res = dir_read(&dj, 0);
+					if (res != FR_OK) break;
+					if (ccl == ld_clust(fs, dj.dir)) break;	/* Found the entry */
+					res = dir_next(&dj, 0);
+				} while (res == FR_OK);
+				if (res == FR_NO_FILE) res = FR_INT_ERR;/* It cannot be 'not found'. */
+				if (res != FR_OK) break;
+				get_fileinfo(&dj, &fno);		/* Get the directory name and push it to the buffer */
+				for (n = 0; fno.fname[n]; n++) ;
+				if (i < n + 3) {
+					res = FR_NOT_ENOUGH_CORE; break;
+				}
+				while (n) buff[--i] = fno.fname[--n];
+				buff[--i] = '/';
+			}
+		}
+		tp = buff;
+		if (res == FR_OK) {
+#if _VOLUMES >= 2
+			*tp++ = '0' + CurrVol;			/* Put drive number */
+			*tp++ = ':';
+#endif
+			if (i == len) {					/* Root-directory */
+				*tp++ = '/';
+			} else {						/* Sub-directroy */
+				do		/* Add stacked path str */
+					*tp++ = buff[i++];
+				while (i < len);
+			}
+		}
+		*tp = 0;
+		FREE_NAMBUF();
+	}
+
+	LEAVE_FF(fs, res);
+}
+
+#endif /* _FS_RPATH >= 2 */
+#endif /* _FS_RPATH >= 1 */
+
+
+
+#if _FS_MINIMIZE <= 2
+/*-----------------------------------------------------------------------*/
+/* Seek File R/W Pointer                                                 */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_lseek (
+	FIL* fp,		/* Pointer to the file object */
+	FSIZE_t ofs		/* File pointer from top of file */
+)
+{
+	FRESULT res;
+	FATFS *fs;
+	DWORD clst, bcs, nsect;
+	FSIZE_t ifptr;
+#if _USE_FASTSEEK
+	DWORD cl, pcl, ncl, tcl, dsc, tlen, ulen, *tbl;
+#endif
+
+	res = validate(&fp->obj, &fs);		/* Check validity of the file object */
+	if (res == FR_OK) res = (FRESULT)fp->err;
+#if _FS_EXFAT && !_FS_READONLY
+	if (res == FR_OK && fs->fs_type == FS_EXFAT) {
+		res = fill_last_frag(&fp->obj, fp->clust, 0xFFFFFFFF);	/* Fill last fragment on the FAT if needed */
+	}
+#endif
+	if (res != FR_OK) LEAVE_FF(fs, res);
+
+#if _USE_FASTSEEK
+	if (fp->cltbl) {	/* Fast seek */
+		if (ofs == CREATE_LINKMAP) {	/* Create CLMT */
+			tbl = fp->cltbl;
+			tlen = *tbl++; ulen = 2;	/* Given table size and required table size */
+			cl = fp->obj.sclust;		/* Origin of the chain */
+			if (cl) {
+				do {
+					/* Get a fragment */
+					tcl = cl; ncl = 0; ulen += 2;	/* Top, length and used items */
+					do {
+						pcl = cl; ncl++;
+						cl = get_fat(&fp->obj, cl);
+						if (cl <= 1) ABORT(fs, FR_INT_ERR);
+						if (cl == 0xFFFFFFFF) ABORT(fs, FR_DISK_ERR);
+					} while (cl == pcl + 1);
+					if (ulen <= tlen) {		/* Store the length and top of the fragment */
+						*tbl++ = ncl; *tbl++ = tcl;
+					}
+				} while (cl < fs->n_fatent);	/* Repeat until end of chain */
+			}
+			*fp->cltbl = ulen;	/* Number of items used */
+			if (ulen <= tlen) {
+				*tbl = 0;		/* Terminate table */
+			} else {
+				res = FR_NOT_ENOUGH_CORE;	/* Given table size is smaller than required */
+			}
+		} else {						/* Fast seek */
+			if (ofs > fp->obj.objsize) ofs = fp->obj.objsize;	/* Clip offset at the file size */
+			fp->fptr = ofs;				/* Set file pointer */
+			if (ofs) {
+				fp->clust = clmt_clust(fp, ofs - 1);
+				dsc = clust2sect(fs, fp->clust);
+				if (!dsc) ABORT(fs, FR_INT_ERR);
+				dsc += (DWORD)((ofs - 1) / SS(fs)) & (fs->csize - 1);
+				if (fp->fptr % SS(fs) && dsc != fp->sect) {	/* Refill sector cache if needed */
+#if !_FS_TINY
+#if !_FS_READONLY
+					if (fp->flag & FA_DIRTY) {		/* Write-back dirty sector cache */
+						if (disk_write(fs->drv, fp->buf, fp->sect, 1) != RES_OK) ABORT(fs, FR_DISK_ERR);
+						fp->flag &= (BYTE)~FA_DIRTY;
+					}
+#endif
+					if (disk_read(fs->drv, fp->buf, dsc, 1) != RES_OK) ABORT(fs, FR_DISK_ERR);	/* Load current sector */
+#endif
+					fp->sect = dsc;
+				}
+			}
+		}
+	} else
+#endif
+
+	/* Normal Seek */
+	{
+#if _FS_EXFAT
+		if (fs->fs_type != FS_EXFAT && ofs >= 0x100000000) ofs = 0xFFFFFFFF;	/* Clip at 4GiB-1 if at FATxx */
+#endif
+		if (ofs > fp->obj.objsize && (_FS_READONLY || !(fp->flag & FA_WRITE))) {	/* In read-only mode, clip offset with the file size */
+			ofs = fp->obj.objsize;
+		}
+		ifptr = fp->fptr;
+		fp->fptr = nsect = 0;
+		if (ofs) {
+			bcs = (DWORD)fs->csize * SS(fs);	/* Cluster size (byte) */
+			if (ifptr > 0 &&
+				(ofs - 1) / bcs >= (ifptr - 1) / bcs) {	/* When seek to same or following cluster, */
+				fp->fptr = (ifptr - 1) & ~(FSIZE_t)(bcs - 1);	/* start from the current cluster */
+				ofs -= fp->fptr;
+				clst = fp->clust;
+			} else {									/* When seek to back cluster, */
+				clst = fp->obj.sclust;					/* start from the first cluster */
+#if !_FS_READONLY
+				if (clst == 0) {						/* If no cluster chain, create a new chain */
+					clst = create_chain(&fp->obj, 0);
+					if (clst == 1) ABORT(fs, FR_INT_ERR);
+					if (clst == 0xFFFFFFFF) ABORT(fs, FR_DISK_ERR);
+					fp->obj.sclust = clst;
+				}
+#endif
+				fp->clust = clst;
+			}
+			if (clst != 0) {
+				while (ofs > bcs) {						/* Cluster following loop */
+					ofs -= bcs; fp->fptr += bcs;
+#if !_FS_READONLY
+					if (fp->flag & FA_WRITE) {			/* Check if in write mode or not */
+						if (_FS_EXFAT && fp->fptr > fp->obj.objsize) {	/* No FAT chain object needs correct objsize to generate FAT value */
+							fp->obj.objsize = fp->fptr;
+							fp->flag |= FA_MODIFIED;
+						}
+						clst = create_chain(&fp->obj, clst);	/* Follow chain with forceed stretch */
+						if (clst == 0) {				/* Clip file size in case of disk full */
+							ofs = 0; break;
+						}
+					} else
+#endif
+					{
+						clst = get_fat(&fp->obj, clst);	/* Follow cluster chain if not in write mode */
+					}
+					if (clst == 0xFFFFFFFF) ABORT(fs, FR_DISK_ERR);
+					if (clst <= 1 || clst >= fs->n_fatent) ABORT(fs, FR_INT_ERR);
+					fp->clust = clst;
+				}
+				fp->fptr += ofs;
+				if (ofs % SS(fs)) {
+					nsect = clust2sect(fs, clst);	/* Current sector */
+					if (!nsect) ABORT(fs, FR_INT_ERR);
+					nsect += (DWORD)(ofs / SS(fs));
+				}
+			}
+		}
+		if (!_FS_READONLY && fp->fptr > fp->obj.objsize) {		/* Set file change flag if the file size is extended */
+			fp->obj.objsize = fp->fptr;
+			fp->flag |= FA_MODIFIED;
+		}
+		if (fp->fptr % SS(fs) && nsect != fp->sect) {	/* Fill sector cache if needed */
+#if !_FS_TINY
+#if !_FS_READONLY
+			if (fp->flag & FA_DIRTY) {			/* Write-back dirty sector cache */
+				if (disk_write(fs->drv, fp->buf, fp->sect, 1) != RES_OK) ABORT(fs, FR_DISK_ERR);
+				fp->flag &= (BYTE)~FA_DIRTY;
+			}
+#endif
+			if (disk_read(fs->drv, fp->buf, nsect, 1) != RES_OK) ABORT(fs, FR_DISK_ERR);	/* Fill sector cache */
+#endif
+			fp->sect = nsect;
+		}
+	}
+
+	LEAVE_FF(fs, res);
+}
+
+
+
+#if _FS_MINIMIZE <= 1
+/*-----------------------------------------------------------------------*/
+/* Create a Directory Object                                             */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_opendir (
+	DIR* dp,			/* Pointer to directory object to create */
+	const TCHAR* path	/* Pointer to the directory path */
+)
+{
+	FRESULT res;
+	FATFS *fs;
+	_FDID *obj;
+	DEF_NAMBUF
+
+
+	if (!dp) return FR_INVALID_OBJECT;
+
+	/* Get logical drive */
+	obj = &dp->obj;
+	res = find_volume(&path, &fs, 0);
+	if (res == FR_OK) {
+		obj->fs = fs;
+		INIT_NAMBUF(fs);
+		res = follow_path(dp, path);			/* Follow the path to the directory */
+		if (res == FR_OK) {						/* Follow completed */
+			if (!(dp->fn[NSFLAG] & NS_NONAME)) {	/* It is not the origin directory itself */
+				if (obj->attr & AM_DIR) {		/* This object is a sub-directory */
+#if _FS_EXFAT
+					if (fs->fs_type == FS_EXFAT) {
+						obj->c_scl = obj->sclust;							/* Get containing directory inforamation */
+						obj->c_size = ((DWORD)obj->objsize & 0xFFFFFF00) | obj->stat;
+						obj->c_ofs = dp->blk_ofs;
+						obj->sclust = ld_dword(fs->dirbuf + XDIR_FstClus);	/* Get object allocation info */
+						obj->objsize = ld_qword(fs->dirbuf + XDIR_FileSize);
+						obj->stat = fs->dirbuf[XDIR_GenFlags] & 2;
+					} else
+#endif
+					{
+						obj->sclust = ld_clust(fs, dp->dir);	/* Get object allocation info */
+					}
+				} else {						/* This object is a file */
+					res = FR_NO_PATH;
+				}
+			}
+			if (res == FR_OK) {
+				obj->id = fs->id;
+				res = dir_sdi(dp, 0);			/* Rewind directory */
+#if _FS_LOCK != 0
+				if (res == FR_OK) {
+					if (obj->sclust) {
+						obj->lockid = inc_lock(dp, 0);	/* Lock the sub directory */
+						if (!obj->lockid) res = FR_TOO_MANY_OPEN_FILES;
+					} else {
+						obj->lockid = 0;	/* Root directory need not to be locked */
+					}
+				}
+#endif
+			}
+		}
+		FREE_NAMBUF();
+		if (res == FR_NO_FILE) res = FR_NO_PATH;
+	}
+	if (res != FR_OK) obj->fs = 0;		/* Invalidate the directory object if function faild */
+
+	LEAVE_FF(fs, res);
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Close Directory                                                       */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_closedir (
+	DIR *dp		/* Pointer to the directory object to be closed */
+)
+{
+	FRESULT res;
+	FATFS *fs;
+
+
+	res = validate(&dp->obj, &fs);			/* Check validity of the file object */
+	if (res == FR_OK) {
+#if _FS_LOCK != 0
+		if (dp->obj.lockid) {				/* Decrement sub-directory open counter */
+			res = dec_lock(dp->obj.lockid);
+		}
+		if (res == FR_OK)
+#endif
+		{
+			dp->obj.fs = 0;			/* Invalidate directory object */
+		}
+#if _FS_REENTRANT
+		unlock_fs(fs, FR_OK);		/* Unlock volume */
+#endif
+	}
+	return res;
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Read Directory Entries in Sequence                                    */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_readdir (
+	DIR* dp,			/* Pointer to the open directory object */
+	FILINFO* fno		/* Pointer to file information to return */
+)
+{
+	FRESULT res;
+	FATFS *fs;
+	DEF_NAMBUF
+
+
+	res = validate(&dp->obj, &fs);	/* Check validity of the directory object */
+	if (res == FR_OK) {
+		if (!fno) {
+			res = dir_sdi(dp, 0);			/* Rewind the directory object */
+		} else {
+			INIT_NAMBUF(fs);
+			res = dir_read(dp, 0);			/* Read an item */
+			if (res == FR_NO_FILE) res = FR_OK;	/* Ignore end of directory */
+			if (res == FR_OK) {				/* A valid entry is found */
+				get_fileinfo(dp, fno);		/* Get the object information */
+				res = dir_next(dp, 0);		/* Increment index for next */
+				if (res == FR_NO_FILE) res = FR_OK;	/* Ignore end of directory now */
+			}
+			FREE_NAMBUF();
+		}
+	}
+	LEAVE_FF(fs, res);
+}
+
+
+
+#if _USE_FIND
+/*-----------------------------------------------------------------------*/
+/* Find Next File                                                        */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_findnext (
+	DIR* dp,		/* Pointer to the open directory object */
+	FILINFO* fno	/* Pointer to the file information structure */
+)
+{
+	FRESULT res;
+
+
+	for (;;) {
+		res = f_readdir(dp, fno);		/* Get a directory item */
+		if (res != FR_OK || !fno || !fno->fname[0]) break;	/* Terminate if any error or end of directory */
+		if (pattern_matching(dp->pat, fno->fname, 0, 0)) break;		/* Test for the file name */
+#if _USE_LFN != 0 && _USE_FIND == 2
+		if (pattern_matching(dp->pat, fno->altname, 0, 0)) break;	/* Test for alternative name if exist */
+#endif
+	}
+	return res;
+}
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Find First File                                                       */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_findfirst (
+	DIR* dp,				/* Pointer to the blank directory object */
+	FILINFO* fno,			/* Pointer to the file information structure */
+	const TCHAR* path,		/* Pointer to the directory to open */
+	const TCHAR* pattern	/* Pointer to the matching pattern */
+)
+{
+	FRESULT res;
+
+
+	dp->pat = pattern;		/* Save pointer to pattern string */
+	res = f_opendir(dp, path);		/* Open the target directory */
+	if (res == FR_OK) {
+		res = f_findnext(dp, fno);	/* Find the first item */
+	}
+	return res;
+}
+
+#endif	/* _USE_FIND */
+
+
+
+#if _FS_MINIMIZE == 0
+/*-----------------------------------------------------------------------*/
+/* Get File Status                                                       */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_stat (
+	const TCHAR* path,	/* Pointer to the file path */
+	FILINFO* fno		/* Pointer to file information to return */
+)
+{
+	FRESULT res;
+	DIR dj;
+	DEF_NAMBUF
+
+
+	/* Get logical drive */
+	res = find_volume(&path, &dj.obj.fs, 0);
+	if (res == FR_OK) {
+		INIT_NAMBUF(dj.obj.fs);
+		res = follow_path(&dj, path);	/* Follow the file path */
+		if (res == FR_OK) {				/* Follow completed */
+			if (dj.fn[NSFLAG] & NS_NONAME) {	/* It is origin directory */
+				res = FR_INVALID_NAME;
+			} else {							/* Found an object */
+				if (fno) get_fileinfo(&dj, fno);
+			}
+		}
+		FREE_NAMBUF();
+	}
+
+	LEAVE_FF(dj.obj.fs, res);
+}
+
+
+
+#if !_FS_READONLY
+/*-----------------------------------------------------------------------*/
+/* Get Number of Free Clusters                                           */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_getfree (
+	const TCHAR* path,	/* Path name of the logical drive number */
+	DWORD* nclst,		/* Pointer to a variable to return number of free clusters */
+	FATFS** fatfs		/* Pointer to return pointer to corresponding file system object */
+)
+{
+	FRESULT res;
+	FATFS *fs;
+	DWORD nfree, clst, sect, stat;
+	UINT i;
+	BYTE *p;
+	_FDID obj;
+
+
+	/* Get logical drive */
+	res = find_volume(&path, &fs, 0);
+	if (res == FR_OK) {
+		*fatfs = fs;				/* Return ptr to the fs object */
+		/* If free_clst is valid, return it without full cluster scan */
+		if (fs->free_clst <= fs->n_fatent - 2) {
+			*nclst = fs->free_clst;
+		} else {
+			/* Get number of free clusters */
+			nfree = 0;
+			if (fs->fs_type == FS_FAT12) {	/* FAT12: Sector unalighed FAT entries */
+				clst = 2; obj.fs = fs;
+				do {
+					stat = get_fat(&obj, clst);
+					if (stat == 0xFFFFFFFF) { res = FR_DISK_ERR; break; }
+					if (stat == 1) { res = FR_INT_ERR; break; }
+					if (stat == 0) nfree++;
+				} while (++clst < fs->n_fatent);
+			} else {
+#if _FS_EXFAT
+				if (fs->fs_type == FS_EXFAT) {	/* exFAT: Scan bitmap table */
+					BYTE bm;
+					UINT b;
+
+					clst = fs->n_fatent - 2;
+					sect = fs->database;
+					i = 0;
+					do {
+						if (i == 0 && (res = move_window(fs, sect++)) != FR_OK) break;
+						for (b = 8, bm = fs->win[i]; b && clst; b--, clst--) {
+							if (!(bm & 1)) nfree++;
+							bm >>= 1;
+						}
+						i = (i + 1) % SS(fs);
+					} while (clst);
+				} else
+#endif
+				{	/* FAT16/32: Sector alighed FAT entries */
+					clst = fs->n_fatent; sect = fs->fatbase;
+					i = 0; p = 0;
+					do {
+						if (i == 0) {
+							res = move_window(fs, sect++);
+							if (res != FR_OK) break;
+							p = fs->win;
+							i = SS(fs);
+						}
+						if (fs->fs_type == FS_FAT16) {
+							if (ld_word(p) == 0) nfree++;
+							p += 2; i -= 2;
+						} else {
+							if ((ld_dword(p) & 0x0FFFFFFF) == 0) nfree++;
+							p += 4; i -= 4;
+						}
+					} while (--clst);
+				}
+			}
+			*nclst = nfree;			/* Return the free clusters */
+			fs->free_clst = nfree;	/* Now free_clst is valid */
+			fs->fsi_flag |= 1;		/* FSInfo is to be updated */
+		}
+	}
+
+	LEAVE_FF(fs, res);
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Truncate File                                                         */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_truncate (
+	FIL* fp		/* Pointer to the file object */
+)
+{
+	FRESULT res;
+	FATFS *fs;
+	DWORD ncl;
+
+
+	res = validate(&fp->obj, &fs);	/* Check validity of the file object */
+	if (res != FR_OK || (res = (FRESULT)fp->err) != FR_OK) LEAVE_FF(fs, res);
+	if (!(fp->flag & FA_WRITE)) LEAVE_FF(fs, FR_DENIED);	/* Check access mode */
+
+	if (fp->fptr < fp->obj.objsize) {	/* Process when fptr is not on the eof */
+		if (fp->fptr == 0) {	/* When set file size to zero, remove entire cluster chain */
+			res = remove_chain(&fp->obj, fp->obj.sclust, 0);
+			fp->obj.sclust = 0;
+		} else {				/* When truncate a part of the file, remove remaining clusters */
+			ncl = get_fat(&fp->obj, fp->clust);
+			res = FR_OK;
+			if (ncl == 0xFFFFFFFF) res = FR_DISK_ERR;
+			if (ncl == 1) res = FR_INT_ERR;
+			if (res == FR_OK && ncl < fs->n_fatent) {
+				res = remove_chain(&fp->obj, ncl, fp->clust);
+			}
+		}
+		fp->obj.objsize = fp->fptr;	/* Set file size to current R/W point */
+		fp->flag |= FA_MODIFIED;
+#if !_FS_TINY
+		if (res == FR_OK && (fp->flag & FA_DIRTY)) {
+			if (disk_write(fs->drv, fp->buf, fp->sect, 1) != RES_OK) {
+				res = FR_DISK_ERR;
+			} else {
+				fp->flag &= (BYTE)~FA_DIRTY;
+			}
+		}
+#endif
+		if (res != FR_OK) ABORT(fs, res);
+	}
+
+	LEAVE_FF(fs, res);
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Delete a File/Directory                                               */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_unlink (
+	const TCHAR* path		/* Pointer to the file or directory path */
+)
+{
+	FRESULT res;
+	DIR dj, sdj;
+	DWORD dclst = 0;
+	FATFS *fs;
+#if _FS_EXFAT
+	_FDID obj;
+#endif
+	DEF_NAMBUF
+
+
+	/* Get logical drive */
+	res = find_volume(&path, &fs, FA_WRITE);
+	dj.obj.fs = fs;
+	if (res == FR_OK) {
+		INIT_NAMBUF(fs);
+		res = follow_path(&dj, path);		/* Follow the file path */
+		if (_FS_RPATH && res == FR_OK && (dj.fn[NSFLAG] & NS_DOT)) {
+			res = FR_INVALID_NAME;			/* Cannot remove dot entry */
+		}
+#if _FS_LOCK != 0
+		if (res == FR_OK) res = chk_lock(&dj, 2);	/* Check if it is an open object */
+#endif
+		if (res == FR_OK) {					/* The object is accessible */
+			if (dj.fn[NSFLAG] & NS_NONAME) {
+				res = FR_INVALID_NAME;		/* Cannot remove the origin directory */
+			} else {
+				if (dj.obj.attr & AM_RDO) {
+					res = FR_DENIED;		/* Cannot remove R/O object */
+				}
+			}
+			if (res == FR_OK) {
+#if _FS_EXFAT
+				obj.fs = fs;
+				if (fs->fs_type == FS_EXFAT) {
+					obj.sclust = dclst = ld_dword(fs->dirbuf + XDIR_FstClus);
+					obj.objsize = ld_qword(fs->dirbuf + XDIR_FileSize);
+					obj.stat = fs->dirbuf[XDIR_GenFlags] & 2;
+				} else
+#endif
+				{
+					dclst = ld_clust(fs, dj.dir);
+				}
+				if (dj.obj.attr & AM_DIR) {			/* Is it a sub-directory? */
+#if _FS_RPATH != 0
+					if (dclst == fs->cdir) {		 		/* Is it the current directory? */
+						res = FR_DENIED;
+					} else
+#endif
+					{
+						sdj.obj.fs = fs;						/* Open the sub-directory */
+						sdj.obj.sclust = dclst;
+#if _FS_EXFAT
+						if (fs->fs_type == FS_EXFAT) {
+							sdj.obj.objsize = obj.objsize;
+							sdj.obj.stat = obj.stat;
+						}
+#endif
+						res = dir_sdi(&sdj, 0);
+						if (res == FR_OK) {
+							res = dir_read(&sdj, 0);			/* Read an item */
+							if (res == FR_OK) res = FR_DENIED;	/* Not empty? */
+							if (res == FR_NO_FILE) res = FR_OK;	/* Empty? */
+						}
+					}
+				}
+			}
+			if (res == FR_OK) {
+				res = dir_remove(&dj);			/* Remove the directory entry */
+				if (res == FR_OK && dclst) {	/* Remove the cluster chain if exist */
+#if _FS_EXFAT
+					res = remove_chain(&obj, dclst, 0);
+#else
+					res = remove_chain(&dj.obj, dclst, 0);
+#endif
+				}
+				if (res == FR_OK) res = sync_fs(fs);
+			}
+		}
+		FREE_NAMBUF();
+	}
+
+	LEAVE_FF(fs, res);
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Create a Directory                                                    */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_mkdir (
+	const TCHAR* path		/* Pointer to the directory path */
+)
+{
+	FRESULT res;
+	DIR dj;
+	FATFS *fs;
+	BYTE *dir;
+	UINT n;
+	DWORD dsc, dcl, pcl, tm;
+	DEF_NAMBUF
+
+
+	/* Get logical drive */
+	res = find_volume(&path, &fs, FA_WRITE);
+	dj.obj.fs = fs;
+	if (res == FR_OK) {
+		INIT_NAMBUF(fs);
+		res = follow_path(&dj, path);			/* Follow the file path */
+		if (res == FR_OK) res = FR_EXIST;		/* Any object with same name is already existing */
+		if (_FS_RPATH && res == FR_NO_FILE && (dj.fn[NSFLAG] & NS_DOT)) {
+			res = FR_INVALID_NAME;
+		}
+		if (res == FR_NO_FILE) {				/* Can create a new directory */
+			dcl = create_chain(&dj.obj, 0);		/* Allocate a cluster for the new directory table */
+			dj.obj.objsize = (DWORD)fs->csize * SS(fs);
+			res = FR_OK;
+			if (dcl == 0) res = FR_DENIED;		/* No space to allocate a new cluster */
+			if (dcl == 1) res = FR_INT_ERR;
+			if (dcl == 0xFFFFFFFF) res = FR_DISK_ERR;
+			if (res == FR_OK) res = sync_window(fs);	/* Flush FAT */
+			tm = GET_FATTIME();
+			if (res == FR_OK) {					/* Initialize the new directory table */
+				dsc = clust2sect(fs, dcl);
+				dir = fs->win;
+				mem_set(dir, 0, SS(fs));
+				if (!_FS_EXFAT || fs->fs_type != FS_EXFAT) {
+					mem_set(dir + DIR_Name, ' ', 11);	/* Create "." entry */
+					dir[DIR_Name] = '.';
+					dir[DIR_Attr] = AM_DIR;
+					st_dword(dir + DIR_ModTime, tm);
+					st_clust(fs, dir, dcl);
+					mem_cpy(dir + SZDIRE, dir, SZDIRE); 	/* Create ".." entry */
+					dir[SZDIRE + 1] = '.'; pcl = dj.obj.sclust;
+					if (fs->fs_type == FS_FAT32 && pcl == fs->dirbase) pcl = 0;
+					st_clust(fs, dir + SZDIRE, pcl);
+				}
+				for (n = fs->csize; n; n--) {	/* Write dot entries and clear following sectors */
+					fs->winsect = dsc++;
+					fs->wflag = 1;
+					res = sync_window(fs);
+					if (res != FR_OK) break;
+					mem_set(dir, 0, SS(fs));
+				}
+			}
+			if (res == FR_OK) {
+				res = dir_register(&dj);	/* Register the object to the directoy */
+			}
+			if (res == FR_OK) {
+#if _FS_EXFAT
+				if (fs->fs_type == FS_EXFAT) {	/* Initialize directory entry block */
+					st_dword(fs->dirbuf + XDIR_ModTime, tm);	/* Created time */
+					st_dword(fs->dirbuf + XDIR_FstClus, dcl);	/* Table start cluster */
+					st_dword(fs->dirbuf + XDIR_FileSize, (DWORD)dj.obj.objsize);	/* File size needs to be valid */
+					st_dword(fs->dirbuf + XDIR_ValidFileSize, (DWORD)dj.obj.objsize);
+					fs->dirbuf[XDIR_GenFlags] = 3;				/* Initialize the object flag (contiguous) */
+					fs->dirbuf[XDIR_Attr] = AM_DIR;				/* Attribute */
+					res = store_xdir(&dj);
+				} else
+#endif
+				{
+					dir = dj.dir;
+					st_dword(dir + DIR_ModTime, tm);	/* Created time */
+					st_clust(fs, dir, dcl);				/* Table start cluster */
+					dir[DIR_Attr] = AM_DIR;				/* Attribute */
+					fs->wflag = 1;
+				}
+				if (res == FR_OK) {
+					res = sync_fs(fs);
+				}
+			} else {
+				remove_chain(&dj.obj, dcl, 0);		/* Could not register, remove cluster chain */
+			}
+		}
+		FREE_NAMBUF();
+	}
+
+	LEAVE_FF(fs, res);
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Rename a File/Directory                                               */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_rename (
+	const TCHAR* path_old,	/* Pointer to the object name to be renamed */
+	const TCHAR* path_new	/* Pointer to the new name */
+)
+{
+	FRESULT res;
+	DIR djo, djn;
+	FATFS *fs;
+	BYTE buf[_FS_EXFAT ? SZDIRE * 2 : 24], *dir;
+	DWORD dw;
+	DEF_NAMBUF
+
+
+	get_ldnumber(&path_new);						/* Snip drive number of new name off */
+	res = find_volume(&path_old, &fs, FA_WRITE);	/* Get logical drive of the old object */
+	if (res == FR_OK) {
+		djo.obj.fs = fs;
+		INIT_NAMBUF(fs);
+		res = follow_path(&djo, path_old);		/* Check old object */
+		if (res == FR_OK && (djo.fn[NSFLAG] & (NS_DOT | NS_NONAME))) res = FR_INVALID_NAME;	/* Check validity of name */
+#if _FS_LOCK != 0
+		if (res == FR_OK) {
+			res = chk_lock(&djo, 2);
+		}
+#endif
+		if (res == FR_OK) {						/* Object to be renamed is found */
+#if _FS_EXFAT
+			if (fs->fs_type == FS_EXFAT) {	/* At exFAT */
+				BYTE nf, nn;
+				WORD nh;
+
+				mem_cpy(buf, fs->dirbuf, SZDIRE * 2);	/* Save 85+C0 entry of old object */
+				mem_cpy(&djn, &djo, sizeof djo);
+				res = follow_path(&djn, path_new);		/* Make sure if new object name is not in use */
+				if (res == FR_OK) {						/* Is new name already in use by any other object? */
+					res = (djn.obj.sclust == djo.obj.sclust && djn.dptr == djo.dptr) ? FR_NO_FILE : FR_EXIST;
+				}
+				if (res == FR_NO_FILE) { 				/* It is a valid path and no name collision */
+					res = dir_register(&djn);			/* Register the new entry */
+					if (res == FR_OK) {
+						nf = fs->dirbuf[XDIR_NumSec]; nn = fs->dirbuf[XDIR_NumName];
+						nh = ld_word(fs->dirbuf + XDIR_NameHash);
+						mem_cpy(fs->dirbuf, buf, SZDIRE * 2);
+						fs->dirbuf[XDIR_NumSec] = nf; fs->dirbuf[XDIR_NumName] = nn;
+						st_word(fs->dirbuf + XDIR_NameHash, nh);
+/* Start of critical section where an interruption can cause a cross-link */
+						res = store_xdir(&djn);
+					}
+				}
+			} else
+#endif
+			{	/* At FAT12/FAT16/FAT32 */
+				mem_cpy(buf, djo.dir + DIR_Attr, 21);	/* Save information about the object except name */
+				mem_cpy(&djn, &djo, sizeof (DIR));		/* Duplicate the directory object */
+				res = follow_path(&djn, path_new);		/* Make sure if new object name is not in use */
+				if (res == FR_OK) {						/* Is new name already in use by any other object? */
+					res = (djn.obj.sclust == djo.obj.sclust && djn.dptr == djo.dptr) ? FR_NO_FILE : FR_EXIST;
+				}
+				if (res == FR_NO_FILE) { 				/* It is a valid path and no name collision */
+					res = dir_register(&djn);			/* Register the new entry */
+					if (res == FR_OK) {
+						dir = djn.dir;					/* Copy information about object except name */
+						mem_cpy(dir + 13, buf + 2, 19);
+						dir[DIR_Attr] = buf[0] | AM_ARC;
+						fs->wflag = 1;
+						if ((dir[DIR_Attr] & AM_DIR) && djo.obj.sclust != djn.obj.sclust) {	/* Update .. entry in the sub-directory if needed */
+							dw = clust2sect(fs, ld_clust(fs, dir));
+							if (!dw) {
+								res = FR_INT_ERR;
+							} else {
+/* Start of critical section where an interruption can cause a cross-link */
+								res = move_window(fs, dw);
+								dir = fs->win + SZDIRE * 1;	/* Ptr to .. entry */
+								if (res == FR_OK && dir[1] == '.') {
+									st_clust(fs, dir, djn.obj.sclust);
+									fs->wflag = 1;
+								}
+							}
+						}
+					}
+				}
+			}
+			if (res == FR_OK) {
+				res = dir_remove(&djo);		/* Remove old entry */
+				if (res == FR_OK) {
+					res = sync_fs(fs);
+				}
+			}
+/* End of the critical section */
+		}
+		FREE_NAMBUF();
+	}
+
+	LEAVE_FF(fs, res);
+}
+
+#endif /* !_FS_READONLY */
+#endif /* _FS_MINIMIZE == 0 */
+#endif /* _FS_MINIMIZE <= 1 */
+#endif /* _FS_MINIMIZE <= 2 */
+
+
+
+#if _USE_CHMOD && !_FS_READONLY
+/*-----------------------------------------------------------------------*/
+/* Change Attribute                                                      */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_chmod (
+	const TCHAR* path,	/* Pointer to the file path */
+	BYTE attr,			/* Attribute bits */
+	BYTE mask			/* Attribute mask to change */
+)
+{
+	FRESULT res;
+	DIR dj;
+	FATFS *fs;
+	DEF_NAMBUF
+
+
+	res = find_volume(&path, &fs, FA_WRITE);	/* Get logical drive */
+	dj.obj.fs = fs;
+	if (res == FR_OK) {
+		INIT_NAMBUF(fs);
+		res = follow_path(&dj, path);	/* Follow the file path */
+		if (res == FR_OK && (dj.fn[NSFLAG] & (NS_DOT | NS_NONAME))) res = FR_INVALID_NAME;	/* Check object validity */
+		if (res == FR_OK) {
+			mask &= AM_RDO|AM_HID|AM_SYS|AM_ARC;	/* Valid attribute mask */
+#if _FS_EXFAT
+			if (fs->fs_type == FS_EXFAT) {
+				fs->dirbuf[XDIR_Attr] = (attr & mask) | (fs->dirbuf[XDIR_Attr] & (BYTE)~mask);	/* Apply attribute change */
+				res = store_xdir(&dj);
+			} else
+#endif
+			{
+				dj.dir[DIR_Attr] = (attr & mask) | (dj.dir[DIR_Attr] & (BYTE)~mask);	/* Apply attribute change */
+				fs->wflag = 1;
+			}
+			if (res == FR_OK) {
+				res = sync_fs(fs);
+			}
+		}
+		FREE_NAMBUF();
+	}
+
+	LEAVE_FF(fs, res);
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Change Timestamp                                                      */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_utime (
+	const TCHAR* path,	/* Pointer to the file/directory name */
+	const FILINFO* fno	/* Pointer to the time stamp to be set */
+)
+{
+	FRESULT res;
+	DIR dj;
+	FATFS *fs;
+	DEF_NAMBUF
+
+
+	res = find_volume(&path, &fs, FA_WRITE);	/* Get logical drive */
+	dj.obj.fs = fs;
+	if (res == FR_OK) {
+		INIT_NAMBUF(fs);
+		res = follow_path(&dj, path);	/* Follow the file path */
+		if (res == FR_OK && (dj.fn[NSFLAG] & (NS_DOT | NS_NONAME))) res = FR_INVALID_NAME;	/* Check object validity */
+		if (res == FR_OK) {
+#if _FS_EXFAT
+			if (fs->fs_type == FS_EXFAT) {
+				st_dword(fs->dirbuf + XDIR_ModTime, (DWORD)fno->fdate << 16 | fno->ftime);
+				res = store_xdir(&dj);
+			} else
+#endif
+			{
+				st_dword(dj.dir + DIR_ModTime, (DWORD)fno->fdate << 16 | fno->ftime);
+				fs->wflag = 1;
+			}
+			if (res == FR_OK) {
+				res = sync_fs(fs);
+			}
+		}
+		FREE_NAMBUF();
+	}
+
+	LEAVE_FF(fs, res);
+}
+
+#endif	/* _USE_CHMOD && !_FS_READONLY */
+
+
+
+#if _USE_LABEL
+/*-----------------------------------------------------------------------*/
+/* Get Volume Label                                                      */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_getlabel (
+	const TCHAR* path,	/* Path name of the logical drive number */
+	TCHAR* label,		/* Pointer to a buffer to return the volume label */
+	DWORD* vsn			/* Pointer to a variable to return the volume serial number */
+)
+{
+	FRESULT res;
+	DIR dj;
+	FATFS *fs;
+	UINT si, di;
+#if _LFN_UNICODE || _FS_EXFAT
+	WCHAR w;
+#endif
+
+	/* Get logical drive */
+	res = find_volume(&path, &fs, 0);
+
+	/* Get volume label */
+	if (res == FR_OK && label) {
+		dj.obj.fs = fs; dj.obj.sclust = 0;	/* Open root directory */
+		res = dir_sdi(&dj, 0);
+		if (res == FR_OK) {
+		 	res = dir_read(&dj, 1);			/* Find a volume label entry */
+		 	if (res == FR_OK) {
+#if _FS_EXFAT
+				if (fs->fs_type == FS_EXFAT) {
+					for (si = di = 0; si < dj.dir[XDIR_NumLabel]; si++) {	/* Extract volume label from 83 entry */
+						w = ld_word(dj.dir + XDIR_Label + si * 2);
+#if _LFN_UNICODE
+						label[di++] = w;
+#else
+						w = ff_convert(w, 0);	/* Unicode -> OEM */
+						if (w == 0) w = '?';	/* Replace wrong character */
+						if (_DF1S && w >= 0x100) label[di++] = (char)(w >> 8);
+						label[di++] = (char)w;
+#endif
+					}
+					label[di] = 0;
+				} else
+#endif
+				{
+					si = di = 0;		/* Extract volume label from AM_VOL entry with code comversion */
+					do {
+#if _LFN_UNICODE
+						w = (si < 11) ? dj.dir[si++] : ' ';
+						if (IsDBCS1(w) && si < 11 && IsDBCS2(dj.dir[si])) {
+							w = w << 8 | dj.dir[si++];
+						}
+						label[di++] = ff_convert(w, 1);	/* OEM -> Unicode */
+#else
+						label[di++] = dj.dir[si++];
+#endif
+					} while (di < 11);
+					do {				/* Truncate trailing spaces */
+						label[di] = 0;
+						if (di == 0) break;
+					} while (label[--di] == ' ');
+				}
+			}
+		}
+		if (res == FR_NO_FILE) {	/* No label entry and return nul string */
+			label[0] = 0;
+			res = FR_OK;
+		}
+	}
+
+	/* Get volume serial number */
+	if (res == FR_OK && vsn) {
+		res = move_window(fs, fs->volbase);
+		if (res == FR_OK) {
+			switch (fs->fs_type) {
+			case FS_EXFAT:
+				di = BPB_VolIDEx; break;
+
+			case FS_FAT32:
+				di = BS_VolID32; break;
+
+			default:
+				di = BS_VolID;
+			}
+			*vsn = ld_dword(fs->win + di);
+		}
+	}
+
+	LEAVE_FF(fs, res);
+}
+
+
+
+#if !_FS_READONLY
+/*-----------------------------------------------------------------------*/
+/* Set Volume Label                                                      */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_setlabel (
+	const TCHAR* label	/* Pointer to the volume label to set */
+)
+{
+	FRESULT res;
+	DIR dj;
+	FATFS *fs;
+	BYTE dirvn[22];
+	UINT i, j, slen;
+	WCHAR w;
+	static const char badchr[] = "\"*+,.:;<=>\?[]|\x7F";
+
+
+	/* Get logical drive */
+	res = find_volume(&label, &fs, FA_WRITE);
+	if (res != FR_OK) LEAVE_FF(fs, res);
+	dj.obj.fs = fs;
+
+	/* Get length of given volume label */
+	for (slen = 0; (UINT)label[slen] >= ' '; slen++) ;	/* Get name length */
+
+#if _FS_EXFAT
+	if (fs->fs_type == FS_EXFAT) {	/* On the exFAT volume */
+		for (i = j = 0; i < slen; ) {	/* Create volume label in directory form */
+			w = label[i++];
+#if !_LFN_UNICODE
+			if (IsDBCS1(w)) {
+				w = (i < slen && IsDBCS2(label[i])) ? w << 8 | (BYTE)label[i++] : 0;
+			}
+			w = ff_convert(w, 1);
+#endif
+			if (w == 0 || chk_chr(badchr, w) || j == 22) {	/* Check validity check validity of the volume label */
+				LEAVE_FF(fs, FR_INVALID_NAME);
+			}
+			st_word(dirvn + j, w); j += 2;
+		}
+		slen = j;
+	} else
+#endif
+	{	/* On the FAT12/16/32 volume */
+		for ( ; slen && label[slen - 1] == ' '; slen--) ;	/* Remove trailing spaces */
+		if (slen) {		/* Is there a volume label to be set? */
+			dirvn[0] = 0; i = j = 0;	/* Create volume label in directory form */
+			do {
+#if _LFN_UNICODE
+				w = ff_convert(ff_wtoupper(label[i++]), 0);
+#else
+				w = (BYTE)label[i++];
+				if (IsDBCS1(w)) {
+					w = (j < 10 && i < slen && IsDBCS2(label[i])) ? w << 8 | (BYTE)label[i++] : 0;
+				}
+#if _USE_LFN != 0
+				w = ff_convert(ff_wtoupper(ff_convert(w, 1)), 0);
+#else
+				if (IsLower(w)) w -= 0x20;			/* To upper ASCII characters */
+#ifdef _EXCVT
+				if (w >= 0x80) w = ExCvt[w - 0x80];	/* To upper extended characters (SBCS cfg) */
+#else
+				if (!_DF1S && w >= 0x80) w = 0;		/* Reject extended characters (ASCII cfg) */
+#endif
+#endif
+#endif
+				if (w == 0 || chk_chr(badchr, w) || j >= (UINT)((w >= 0x100) ? 10 : 11)) {	/* Reject invalid characters for volume label */
+					LEAVE_FF(fs, FR_INVALID_NAME);
+				}
+				if (w >= 0x100) dirvn[j++] = (BYTE)(w >> 8);
+				dirvn[j++] = (BYTE)w;
+			} while (i < slen);
+			while (j < 11) dirvn[j++] = ' ';	/* Fill remaining name field */
+			if (dirvn[0] == DDEM) LEAVE_FF(fs, FR_INVALID_NAME);	/* Reject illegal name (heading DDEM) */
+		}
+	}
+
+	/* Set volume label */
+	dj.obj.sclust = 0;		/* Open root directory */
+	res = dir_sdi(&dj, 0);
+	if (res == FR_OK) {
+		res = dir_read(&dj, 1);	/* Get volume label entry */
+		if (res == FR_OK) {
+			if (_FS_EXFAT && fs->fs_type == FS_EXFAT) {
+				dj.dir[XDIR_NumLabel] = (BYTE)(slen / 2);	/* Change the volume label */
+				mem_cpy(dj.dir + XDIR_Label, dirvn, slen);
+			} else {
+				if (slen) {
+					mem_cpy(dj.dir, dirvn, 11);	/* Change the volume label */
+				} else {
+					dj.dir[DIR_Name] = DDEM;	/* Remove the volume label */
+				}
+			}
+			fs->wflag = 1;
+			res = sync_fs(fs);
+		} else {			/* No volume label entry is found or error */
+			if (res == FR_NO_FILE) {
+				res = FR_OK;
+				if (slen) {	/* Create a volume label entry */
+					res = dir_alloc(&dj, 1);	/* Allocate an entry */
+					if (res == FR_OK) {
+						mem_set(dj.dir, 0, SZDIRE);	/* Clear the entry */
+						if (_FS_EXFAT && fs->fs_type == FS_EXFAT) {
+							dj.dir[XDIR_Type] = 0x83;		/* Create 83 entry */
+							dj.dir[XDIR_NumLabel] = (BYTE)(slen / 2);
+							mem_cpy(dj.dir + XDIR_Label, dirvn, slen);
+						} else {
+							dj.dir[DIR_Attr] = AM_VOL;		/* Create volume label entry */
+							mem_cpy(dj.dir, dirvn, 11);
+						}
+						fs->wflag = 1;
+						res = sync_fs(fs);
+					}
+				}
+			}
+		}
+	}
+
+	LEAVE_FF(fs, res);
+}
+
+#endif /* !_FS_READONLY */
+#endif /* _USE_LABEL */
+
+
+
+#if _USE_EXPAND && !_FS_READONLY
+/*-----------------------------------------------------------------------*/
+/* Allocate a Contiguous Blocks to the File                              */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_expand (
+	FIL* fp,		/* Pointer to the file object */
+	FSIZE_t fsz,	/* File size to be expanded to */
+	BYTE opt		/* Operation mode 0:Find and prepare or 1:Find and allocate */
+)
+{
+	FRESULT res;
+	FATFS *fs;
+	DWORD n, clst, stcl, scl, ncl, tcl, lclst;
+
+
+	res = validate(&fp->obj, &fs);		/* Check validity of the file object */
+	if (res != FR_OK || (res = (FRESULT)fp->err) != FR_OK) LEAVE_FF(fs, res);
+	if (fsz == 0 || fp->obj.objsize != 0 || !(fp->flag & FA_WRITE)) LEAVE_FF(fs, FR_DENIED);
+#if _FS_EXFAT
+	if (fs->fs_type != FS_EXFAT && fsz >= 0x100000000) LEAVE_FF(fs, FR_DENIED);	/* Check if in size limit */
+#endif
+	n = (DWORD)fs->csize * SS(fs);	/* Cluster size */
+	tcl = (DWORD)(fsz / n) + ((fsz & (n - 1)) ? 1 : 0);	/* Number of clusters required */
+	stcl = fs->last_clst; lclst = 0;
+	if (stcl < 2 || stcl >= fs->n_fatent) stcl = 2;
+
+#if _FS_EXFAT
+	if (fs->fs_type == FS_EXFAT) {
+		scl = find_bitmap(fs, stcl, tcl);			/* Find a contiguous cluster block */
+		if (scl == 0) res = FR_DENIED;				/* No contiguous cluster block was found */
+		if (scl == 0xFFFFFFFF) res = FR_DISK_ERR;
+		if (res == FR_OK) {	/* A contiguous free area is found */
+			if (opt) {		/* Allocate it now */
+				res = change_bitmap(fs, scl, tcl, 1);	/* Mark the cluster block 'in use' */
+				lclst = scl + tcl - 1;
+			} else {		/* Set it as suggested point for next allocation */
+				lclst = scl - 1;
+			}
+		}
+	} else
+#endif
+	{
+		scl = clst = stcl; ncl = 0;
+		for (;;) {	/* Find a contiguous cluster block */
+			n = get_fat(&fp->obj, clst);
+			if (++clst >= fs->n_fatent) clst = 2;
+			if (n == 1) { res = FR_INT_ERR; break; }
+			if (n == 0xFFFFFFFF) { res = FR_DISK_ERR; break; }
+			if (n == 0) {	/* Is it a free cluster? */
+				if (++ncl == tcl) break;	/* Break if a contiguous cluster block is found */
+			} else {
+				scl = clst; ncl = 0;		/* Not a free cluster */
+			}
+			if (clst == stcl) { res = FR_DENIED; break; }	/* No contiguous cluster? */
+		}
+		if (res == FR_OK) {	/* A contiguous free area is found */
+			if (opt) {		/* Allocate it now */
+				for (clst = scl, n = tcl; n; clst++, n--) {	/* Create a cluster chain on the FAT */
+					res = put_fat(fs, clst, (n == 1) ? 0xFFFFFFFF : clst + 1);
+					if (res != FR_OK) break;
+					lclst = clst;
+				}
+			} else {		/* Set it as suggested point for next allocation */
+				lclst = scl - 1;
+			}
+		}
+	}
+
+	if (res == FR_OK) {
+		fs->last_clst = lclst;		/* Set suggested start cluster to start next */
+		if (opt) {	/* Is it allocated now? */
+			fp->obj.sclust = scl;		/* Update object allocation information */
+			fp->obj.objsize = fsz;
+			if (_FS_EXFAT) fp->obj.stat = 2;	/* Set status 'contiguous chain' */
+			fp->flag |= FA_MODIFIED;
+			if (fs->free_clst <= fs->n_fatent - 2) {	/* Update FSINFO */
+				fs->free_clst -= tcl;
+				fs->fsi_flag |= 1;
+			}
+		}
+	}
+
+	LEAVE_FF(fs, res);
+}
+
+#endif /* _USE_EXPAND && !_FS_READONLY */
+
+
+
+#if _USE_FORWARD
+/*-----------------------------------------------------------------------*/
+/* Forward data to the stream directly                                   */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_forward (
+	FIL* fp, 						/* Pointer to the file object */
+	UINT (*func)(const BYTE*,UINT),	/* Pointer to the streaming function */
+	UINT btf,						/* Number of bytes to forward */
+	UINT* bf						/* Pointer to number of bytes forwarded */
+)
+{
+	FRESULT res;
+	FATFS *fs;
+	DWORD clst, sect;
+	FSIZE_t remain;
+	UINT rcnt, csect;
+	BYTE *dbuf;
+
+
+	*bf = 0;	/* Clear transfer byte counter */
+	res = validate(&fp->obj, &fs);		/* Check validity of the file object */
+	if (res != FR_OK || (res = (FRESULT)fp->err) != FR_OK) LEAVE_FF(fs, res);
+	if (!(fp->flag & FA_READ)) LEAVE_FF(fs, FR_DENIED);	/* Check access mode */
+
+	remain = fp->obj.objsize - fp->fptr;
+	if (btf > remain) btf = (UINT)remain;			/* Truncate btf by remaining bytes */
+
+	for ( ;  btf && (*func)(0, 0);					/* Repeat until all data transferred or stream goes busy */
+		fp->fptr += rcnt, *bf += rcnt, btf -= rcnt) {
+		csect = (UINT)(fp->fptr / SS(fs) & (fs->csize - 1));	/* Sector offset in the cluster */
+		if (fp->fptr % SS(fs) == 0) {				/* On the sector boundary? */
+			if (csect == 0) {						/* On the cluster boundary? */
+				clst = (fp->fptr == 0) ?			/* On the top of the file? */
+					fp->obj.sclust : get_fat(&fp->obj, fp->clust);
+				if (clst <= 1) ABORT(fs, FR_INT_ERR);
+				if (clst == 0xFFFFFFFF) ABORT(fs, FR_DISK_ERR);
+				fp->clust = clst;					/* Update current cluster */
+			}
+		}
+		sect = clust2sect(fs, fp->clust);			/* Get current data sector */
+		if (!sect) ABORT(fs, FR_INT_ERR);
+		sect += csect;
+#if _FS_TINY
+		if (move_window(fs, sect) != FR_OK) ABORT(fs, FR_DISK_ERR);	/* Move sector window to the file data */
+		dbuf = fs->win;
+#else
+		if (fp->sect != sect) {		/* Fill sector cache with file data */
+#if !_FS_READONLY
+			if (fp->flag & FA_DIRTY) {		/* Write-back dirty sector cache */
+				if (disk_write(fs->drv, fp->buf, fp->sect, 1) != RES_OK) ABORT(fs, FR_DISK_ERR);
+				fp->flag &= (BYTE)~FA_DIRTY;
+			}
+#endif
+			if (disk_read(fs->drv, fp->buf, sect, 1) != RES_OK) ABORT(fs, FR_DISK_ERR);
+		}
+		dbuf = fp->buf;
+#endif
+		fp->sect = sect;
+		rcnt = SS(fs) - (UINT)fp->fptr % SS(fs);	/* Number of bytes left in the sector */
+		if (rcnt > btf) rcnt = btf;					/* Clip it by btr if needed */
+		rcnt = (*func)(dbuf + ((UINT)fp->fptr % SS(fs)), rcnt);	/* Forward the file data */
+		if (!rcnt) ABORT(fs, FR_INT_ERR);
+	}
+
+	LEAVE_FF(fs, FR_OK);
+}
+#endif /* _USE_FORWARD */
+
+
+
+#if _USE_MKFS && !_FS_READONLY
+/*-----------------------------------------------------------------------*/
+/* Create an FAT/exFAT volume                                            */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_mkfs (
+	const TCHAR* path,	/* Logical drive number */
+	BYTE opt,			/* Format option */
+	DWORD au,			/* Size of allocation unit (cluster) [byte] */
+	void* work,			/* Pointer to working buffer */
+	UINT len			/* Size of working buffer */
+)
+{
+	const UINT n_fats = 1;		/* Number of FATs for FAT12/16/32 volume (1 or 2) */
+	const UINT n_rootdir = 512;	/* Number of root directory entries for FAT12/16 volume */
+	static const WORD cst[] = {1, 4, 16, 64, 256, 512, 0};	/* Cluster size boundary for FAT12/16 volume (4Ks unit) */
+	static const WORD cst32[] = {1, 2, 4, 8, 16, 32, 0};	/* Cluster size boundary for FAT32 volume (128Ks unit) */
+	BYTE fmt, sys, *buf, *pte, pdrv, part;
+	WORD ss;
+	DWORD szb_buf, sz_buf, sz_blk, n_clst, pau, sect, nsect, n;
+	DWORD b_vol, b_fat, b_data;				/* Base LBA for volume, fat, data */
+	DWORD sz_vol, sz_rsv, sz_fat, sz_dir;	/* Size for volume, fat, dir, data */
+	UINT i;
+	int vol;
+	DSTATUS stat;
+#if _USE_TRIM || _FS_EXFAT
+	DWORD tbl[3];
+#endif
+
+
+	/* Check mounted drive and clear work area */
+	vol = get_ldnumber(&path);					/* Get target logical drive */
+	if (vol < 0) return FR_INVALID_DRIVE;
+	if (FatFs[vol]) FatFs[vol]->fs_type = 0;	/* Clear the volume */
+	pdrv = LD2PD(vol);	/* Physical drive */
+	part = LD2PT(vol);	/* Partition (0:create as new, 1-4:get from partition table) */
+
+	/* Check physical drive status */
+	stat = disk_initialize(pdrv);
+	if (stat & STA_NOINIT) return FR_NOT_READY;
+	if (stat & STA_PROTECT) return FR_WRITE_PROTECTED;
+	if (disk_ioctl(pdrv, GET_BLOCK_SIZE, &sz_blk) != RES_OK || !sz_blk || sz_blk > 32768 || (sz_blk & (sz_blk - 1))) sz_blk = 1;	/* Erase block to align data area */
+#if _MAX_SS != _MIN_SS		/* Get sector size of the medium if variable sector size cfg. */
+	if (disk_ioctl(pdrv, GET_SECTOR_SIZE, &ss) != RES_OK) return FR_DISK_ERR;
+	if (ss > _MAX_SS || ss < _MIN_SS || (ss & (ss - 1))) return FR_DISK_ERR;
+#else
+	ss = _MAX_SS;
+#endif
+	if ((au != 0 && au < ss) || au > 0x1000000 || (au & (au - 1))) return FR_INVALID_PARAMETER;	/* Check if au is valid */
+	au /= ss;	/* Cluster size in unit of sector */
+
+	/* Get working buffer */
+	buf = (BYTE*)work;		/* Working buffer */
+	sz_buf = len / ss;		/* Size of working buffer (sector) */
+	szb_buf = sz_buf * ss;	/* Size of working buffer (byte) */
+	if (!szb_buf) return FR_MKFS_ABORTED;
+
+	/* Determine where the volume to be located (b_vol, sz_vol) */
+	if (_MULTI_PARTITION && part != 0) {
+		/* Get partition information from partition table in the MBR */
+		if (disk_read(pdrv, buf, 0, 1) != RES_OK) return FR_DISK_ERR;	/* Load MBR */
+		if (ld_word(buf + BS_55AA) != 0xAA55) return FR_MKFS_ABORTED;	/* Check if MBR is valid */
+		pte = buf + (MBR_Table + (part - 1) * SZ_PTE);
+		if (!pte[PTE_System]) return FR_MKFS_ABORTED;	/* No partition? */
+		b_vol = ld_dword(pte + PTE_StLba);		/* Get volume start sector */
+		sz_vol = ld_dword(pte + PTE_SizLba);	/* Get volume size */
+	} else {
+		/* Create a single-partition in this function */
+		if (disk_ioctl(pdrv, GET_SECTOR_COUNT, &sz_vol) != RES_OK) return FR_DISK_ERR;
+		b_vol = (opt & FM_SFD) ? 0 : 63;		/* Volume start sector */
+		if (sz_vol < b_vol) return FR_MKFS_ABORTED;
+		sz_vol -= b_vol;						/* Volume size */
+	}
+	if (sz_vol < 128) return FR_MKFS_ABORTED;	/* Check if volume size is >=128s */
+
+	/* Pre-determine the FAT type */
+	do {
+		if (_FS_EXFAT && (opt & FM_EXFAT)) {	/* exFAT possible? */
+			if ((opt & FM_ANY) == FM_EXFAT || sz_vol >= 0x4000000 || au > 128) {	/* exFAT only, vol >= 64Ms or au > 128s ? */
+				fmt = FS_EXFAT; break;
+			}
+		}
+		if (au > 128) return FR_INVALID_PARAMETER;	/* Too large au for FAT/FAT32 */
+		if (opt & FM_FAT32) {	/* FAT32 possible? */
+			if ((opt & FM_ANY) == FM_FAT32 || !(opt & FM_FAT)) {	/* FAT32 only or no-FAT? */
+				fmt = FS_FAT32; break;
+			}
+		}
+		if (!(opt & FM_FAT)) return FR_INVALID_PARAMETER;	/* no-FAT? */
+		fmt = FS_FAT16;
+	} while (0);
+
+#if _FS_EXFAT
+	if (fmt == FS_EXFAT) {	/* Create an exFAT volume */
+		DWORD szb_bit, szb_case, sum, nb, cl;
+		WCHAR ch, si;
+		UINT j, st;
+		BYTE b;
+
+		if (sz_vol < 0x1000) return FR_MKFS_ABORTED;	/* Too small volume? */
+#if _USE_TRIM
+		tbl[0] = b_vol; tbl[1] = b_vol + sz_vol - 1;	/* Inform the device the volume area may be erased */
+		disk_ioctl(pdrv, CTRL_TRIM, tbl);
+#endif
+		/* Determine FAT location, data location and number of clusters */
+		if (!au) {	/* au auto-selection */
+			au = 8;
+			if (sz_vol >= 0x80000) au = 64;		/* >= 512Ks */
+			if (sz_vol >= 0x4000000) au = 256;	/* >= 64Ms */
+		}
+		b_fat = b_vol + 32;										/* FAT start at offset 32 */
+		sz_fat = ((sz_vol / au + 2) * 4 + ss - 1) / ss;			/* Number of FAT sectors */
+		b_data = (b_fat + sz_fat + sz_blk - 1) & ~(sz_blk - 1);	/* Align data area to the erase block boundary */
+		if (b_data >= sz_vol / 2) return FR_MKFS_ABORTED;		/* Too small volume? */
+		n_clst = (sz_vol - (b_data - b_vol)) / au;				/* Number of clusters */
+		if (n_clst <16) return FR_MKFS_ABORTED;					/* Too few clusters? */
+		if (n_clst > MAX_EXFAT) return FR_MKFS_ABORTED;			/* Too many clusters? */
+
+		szb_bit = (n_clst + 7) / 8;						/* Size of allocation bitmap */
+		tbl[0] = (szb_bit + au * ss - 1) / (au * ss);	/* Number of allocation bitmap clusters */
+
+		/* Create a compressed up-case table */
+		sect = b_data + au * tbl[0];	/* Table start sector */
+		sum = 0;						/* Table checksum to be stored in the 82 entry */
+		st = si = i = j = szb_case = 0;
+		do {
+			switch (st) {
+			case 0:
+				ch = ff_wtoupper(si);	/* Get an up-case char */
+				if (ch != si) {
+					si++; break;		/* Store the up-case char if exist */
+				}
+				for (j = 1; (WCHAR)(si + j) && (WCHAR)(si + j) == ff_wtoupper((WCHAR)(si + j)); j++) ;	/* Get run length of no-case block */
+				if (j >= 128) {
+					ch = 0xFFFF; st = 2; break;	/* Compress the no-case block if run is >= 128 */
+				}
+				st = 1;			/* Do not compress short run */
+				/* go to next case */
+			case 1:
+				ch = si++;		/* Fill the short run */
+				if (--j == 0) st = 0;
+				break;
+
+			default:
+				ch = (WCHAR)j; si += j;	/* Number of chars to skip */
+				st = 0;
+			}
+			sum = xsum32(buf[i + 0] = (BYTE)ch, sum);		/* Put it into the write buffer */
+			sum = xsum32(buf[i + 1] = (BYTE)(ch >> 8), sum);
+			i += 2; szb_case += 2;
+			if (!si || i == szb_buf) {		/* Write buffered data when buffer full or end of process */
+				n = (i + ss - 1) / ss;
+				if (disk_write(pdrv, buf, sect, n) != RES_OK) return FR_DISK_ERR;
+				sect += n; i = 0;
+			}
+		} while (si);
+		tbl[1] = (szb_case + au * ss - 1) / (au * ss);	/* Number of up-case table clusters */
+		tbl[2] = 1;										/* Number of root dir clusters */
+
+		/* Initialize the allocation bitmap */
+		sect = b_data; nsect = (szb_bit + ss - 1) / ss;	/* Start of bitmap and number of sectors */
+		nb = tbl[0] + tbl[1] + tbl[2];					/* Number of clusters in-use by system */
+		do {
+			mem_set(buf, 0, szb_buf);
+			for (i = 0; nb >= 8 && i < szb_buf; buf[i++] = 0xFF, nb -= 8) ;
+			for (b = 1; nb && i < szb_buf; buf[i] |= b, b <<= 1, nb--) ;
+			n = (nsect > sz_buf) ? sz_buf : nsect;		/* Write the buffered data */
+			if (disk_write(pdrv, buf, sect, n) != RES_OK) return FR_DISK_ERR;
+			sect += n; nsect -= n;
+		} while (nsect);
+
+		/* Initialize the FAT */
+		sect = b_fat; nsect = sz_fat;	/* Start of FAT and number of FAT sectors */
+		j = nb = cl = 0;
+		do {
+			mem_set(buf, 0, szb_buf); i = 0;	/* Clear work area and reset write index */
+			if (cl == 0) {	/* Set entry 0 and 1 */
+				st_dword(buf + i, 0xFFFFFFF8); i += 4; cl++;
+				st_dword(buf + i, 0xFFFFFFFF); i += 4; cl++;
+			}
+			do {			/* Create chains of bitmap, up-case and root dir */
+				while (nb && i < szb_buf) {			/* Create a chain */
+					st_dword(buf + i, (nb > 1) ? cl + 1 : 0xFFFFFFFF);
+					i += 4; cl++; nb--;
+				}
+				if (!nb && j < 3) nb = tbl[j++];	/* Next chain */
+			} while (nb && i < szb_buf);
+			n = (nsect > sz_buf) ? sz_buf : nsect;	/* Write the buffered data */
+			if (disk_write(pdrv, buf, sect, n) != RES_OK) return FR_DISK_ERR;
+			sect += n; nsect -= n;
+		} while (nsect);
+
+		/* Initialize the root directory */
+		mem_set(buf, 0, szb_buf);
+		buf[SZDIRE * 0 + 0] = 0x83;		/* 83 entry (volume label) */
+		buf[SZDIRE * 1 + 0] = 0x81;		/* 81 entry (allocation bitmap) */
+		st_dword(buf + SZDIRE * 1 + 20, 2);
+		st_dword(buf + SZDIRE * 1 + 24, szb_bit);
+		buf[SZDIRE * 2 + 0] = 0x82;		/* 82 entry (up-case table) */
+		st_dword(buf + SZDIRE * 2 + 4, sum);
+		st_dword(buf + SZDIRE * 2 + 20, 2 + tbl[0]);
+		st_dword(buf + SZDIRE * 2 + 24, szb_case);
+		sect = b_data + au * (tbl[0] + tbl[1]);	nsect = au;	/* Start of the root directory and number of sectors */
+		do {	/* Fill root directory sectors */
+			n = (nsect > sz_buf) ? sz_buf : nsect;
+			if (disk_write(pdrv, buf, sect, n) != RES_OK) return FR_DISK_ERR;
+			mem_set(buf, 0, ss);
+			sect += n; nsect -= n;
+		} while (nsect);
+
+		/* Create two set of the exFAT VBR blocks */
+		sect = b_vol;
+		for (n = 0; n < 2; n++) {
+			/* Main record (+0) */
+			mem_set(buf, 0, ss);
+			mem_cpy(buf + BS_JmpBoot, "\xEB\x76\x90" "EXFAT   ", 11);	/* Boot jump code (x86), OEM name */
+			st_dword(buf + BPB_VolOfsEx, b_vol);					/* Volume offset in the physical drive [sector] */
+			st_dword(buf + BPB_TotSecEx, sz_vol);					/* Volume size [sector] */
+			st_dword(buf + BPB_FatOfsEx, b_fat - b_vol);			/* FAT offset [sector] */
+			st_dword(buf + BPB_FatSzEx, sz_fat);					/* FAT size [sector] */
+			st_dword(buf + BPB_DataOfsEx, b_data - b_vol);			/* Data offset [sector] */
+			st_dword(buf + BPB_NumClusEx, n_clst);					/* Number of clusters */
+			st_dword(buf + BPB_RootClusEx, 2 + tbl[0] + tbl[1]);	/* Root dir cluster # */
+			st_dword(buf + BPB_VolIDEx, GET_FATTIME());				/* VSN */
+			st_word(buf + BPB_FSVerEx, 0x100);						/* File system version (1.00) */
+			for (buf[BPB_BytsPerSecEx] = 0, i = ss; i >>= 1; buf[BPB_BytsPerSecEx]++) ;	/* Log2 of sector size [byte] */
+			for (buf[BPB_SecPerClusEx] = 0, i = au; i >>= 1; buf[BPB_SecPerClusEx]++) ;	/* Log2 of cluster size [sector] */
+			buf[BPB_NumFATsEx] = 1;					/* Number of FATs */
+			buf[BPB_DrvNumEx] = 0x80;				/* Drive number (for int13) */
+			st_word(buf + BS_BootCodeEx, 0xFEEB);	/* Boot code (x86) */
+			st_word(buf + BS_55AA, 0xAA55);			/* Signature (placed here regardless of sector size) */
+			for (i = sum = 0; i < ss; i++) {		/* VBR checksum */
+				if (i != BPB_VolFlagEx && i != BPB_VolFlagEx + 1 && i != BPB_PercInUseEx) sum = xsum32(buf[i], sum);
+			}
+			if (disk_write(pdrv, buf, sect++, 1) != RES_OK) return FR_DISK_ERR;
+			/* Extended bootstrap record (+1..+8) */
+			mem_set(buf, 0, ss);
+			st_word(buf + ss - 2, 0xAA55);	/* Signature (placed at end of sector) */
+			for (j = 1; j < 9; j++) {
+				for (i = 0; i < ss; sum = xsum32(buf[i++], sum)) ;	/* VBR checksum */
+				if (disk_write(pdrv, buf, sect++, 1) != RES_OK) return FR_DISK_ERR;
+			}
+			/* OEM/Reserved record (+9..+10) */
+			mem_set(buf, 0, ss);
+			for ( ; j < 11; j++) {
+				for (i = 0; i < ss; sum = xsum32(buf[i++], sum)) ;	/* VBR checksum */
+				if (disk_write(pdrv, buf, sect++, 1) != RES_OK) return FR_DISK_ERR;
+			}
+			/* Sum record (+11) */
+			for (i = 0; i < ss; i += 4) st_dword(buf + i, sum);		/* Fill with checksum value */
+			if (disk_write(pdrv, buf, sect++, 1) != RES_OK) return FR_DISK_ERR;
+		}
+
+	} else
+#endif	/* _FS_EXFAT */
+	{	/* Create an FAT12/16/32 volume */
+		do {
+			pau = au;
+			/* Pre-determine number of clusters and FAT sub-type */
+			if (fmt == FS_FAT32) {	/* FAT32 volume */
+				if (!pau) {	/* au auto-selection */
+					n = sz_vol / 0x20000;	/* Volume size in unit of 128KS */
+					for (i = 0, pau = 1; cst32[i] && cst32[i] <= n; i++, pau <<= 1) ;	/* Get from table */
+				}
+				n_clst = sz_vol / pau;	/* Number of clusters */
+				sz_fat = (n_clst * 4 + 8 + ss - 1) / ss;	/* FAT size [sector] */
+				sz_rsv = 32;	/* Number of reserved sectors */
+				sz_dir = 0;		/* No static directory */
+				if (n_clst <= MAX_FAT16 || n_clst > MAX_FAT32) return FR_MKFS_ABORTED;
+			} else {				/* FAT12/16 volume */
+				if (!pau) {	/* au auto-selection */
+					n = sz_vol / 0x1000;	/* Volume size in unit of 4KS */
+					for (i = 0, pau = 1; cst[i] && cst[i] <= n; i++, pau <<= 1) ;	/* Get from table */
+				}
+				n_clst = sz_vol / pau;
+				if (n_clst > MAX_FAT12) {
+					n = n_clst * 2 + 4;		/* FAT size [byte] */
+				} else {
+					fmt = FS_FAT12;
+					n = (n_clst * 3 + 1) / 2 + 3;	/* FAT size [byte] */
+				}
+				sz_fat = (n + ss - 1) / ss;		/* FAT size [sector] */
+				sz_rsv = 1;						/* Number of reserved sectors */
+				sz_dir = (DWORD)n_rootdir * SZDIRE / ss;	/* Rootdir size [sector] */
+			}
+			b_fat = b_vol + sz_rsv;						/* FAT base */
+			b_data = b_fat + sz_fat * n_fats + sz_dir;	/* Data base */
+
+			/* Align data base to erase block boundary (for flash memory media) */
+			n = ((b_data + sz_blk - 1) & ~(sz_blk - 1)) - b_data;	/* Next nearest erase block from current data base */
+			if (fmt == FS_FAT32) {		/* FAT32: Move FAT base */
+				sz_rsv += n; b_fat += n;
+			} else {					/* FAT12/16: Expand FAT size */
+				sz_fat += n / n_fats;
+			}
+
+			/* Determine number of clusters and final check of validity of the FAT sub-type */
+			if (sz_vol < b_data + pau * 16 - b_vol) return FR_MKFS_ABORTED;	/* Too small volume */
+			n_clst = (sz_vol - sz_rsv - sz_fat * n_fats - sz_dir) / pau;
+			if (fmt == FS_FAT32) {
+				if (n_clst <= MAX_FAT16) {	/* Too few clusters for FAT32 */
+					if (!au && (au = pau / 2) != 0) continue;	/* Adjust cluster size and retry */
+					return FR_MKFS_ABORTED;
+				}
+			}
+			if (fmt == FS_FAT16) {
+				if (n_clst > MAX_FAT16) {	/* Too many clusters for FAT16 */
+					if (!au && (pau * 2) <= 64) {
+						au = pau * 2; continue;		/* Adjust cluster size and retry */
+					}
+					if ((opt & FM_FAT32)) {
+						fmt = FS_FAT32; continue;	/* Switch type to FAT32 and retry */
+					}
+					if (!au && (au = pau * 2) <= 128) continue;	/* Adjust cluster size and retry */
+					return FR_MKFS_ABORTED;
+				}
+				if  (n_clst <= MAX_FAT12) {	/* Too few clusters for FAT16 */
+					if (!au && (au = pau * 2) <= 128) continue;	/* Adjust cluster size and retry */
+					return FR_MKFS_ABORTED;
+				}
+			}
+			if (fmt == FS_FAT12 && n_clst > MAX_FAT12) return FR_MKFS_ABORTED;	/* Too many clusters for FAT12 */
+
+			/* Ok, it is the valid cluster configuration */
+			break;
+		} while (1);
+
+#if _USE_TRIM
+		tbl[0] = b_vol; tbl[1] = b_vol + sz_vol - 1;	/* Inform the device the volume area can be erased */
+		disk_ioctl(pdrv, CTRL_TRIM, tbl);
+#endif
+		/* Create FAT VBR */
+		mem_set(buf, 0, ss);
+		mem_cpy(buf + BS_JmpBoot, "\xEB\xFE\x90" "MSDOS5.0", 11);/* Boot jump code (x86), OEM name */
+		st_word(buf + BPB_BytsPerSec, ss);				/* Sector size [byte] */
+		buf[BPB_SecPerClus] = (BYTE)pau;				/* Cluster size [sector] */
+		st_word(buf + BPB_RsvdSecCnt, (WORD)sz_rsv);	/* Size of reserved area */
+		buf[BPB_NumFATs] = (BYTE)n_fats;				/* Number of FATs */
+		st_word(buf + BPB_RootEntCnt, (WORD)((fmt == FS_FAT32) ? 0 : n_rootdir));	/* Number of root directory entries */
+		if (sz_vol < 0x10000) {
+			st_word(buf + BPB_TotSec16, (WORD)sz_vol);	/* Volume size in 16-bit LBA */
+		} else {
+			st_dword(buf + BPB_TotSec32, sz_vol);		/* Volume size in 32-bit LBA */
+		}
+		buf[BPB_Media] = 0xF8;							/* Media descriptor byte */
+		st_word(buf + BPB_SecPerTrk, 63);				/* Number of sectors per track (for int13) */
+		st_word(buf + BPB_NumHeads, 255);				/* Number of heads (for int13) */
+		st_dword(buf + BPB_HiddSec, b_vol);				/* Volume offset in the physical drive [sector] */
+		if (fmt == FS_FAT32) {
+			st_dword(buf + BS_VolID32, GET_FATTIME());	/* VSN */
+			st_dword(buf + BPB_FATSz32, sz_fat);		/* FAT size [sector] */
+			st_dword(buf + BPB_RootClus32, 2);			/* Root directory cluster # (2) */
+			st_word(buf + BPB_FSInfo32, 1);				/* Offset of FSINFO sector (VBR + 1) */
+			st_word(buf + BPB_BkBootSec32, 6);			/* Offset of backup VBR (VBR + 6) */
+			buf[BS_DrvNum32] = 0x80;					/* Drive number (for int13) */
+			buf[BS_BootSig32] = 0x29;					/* Extended boot signature */
+			mem_cpy(buf + BS_VolLab32, "NO NAME    " "FAT32   ", 19);	/* Volume label, FAT signature */
+		} else {
+			st_dword(buf + BS_VolID, GET_FATTIME());	/* VSN */
+			st_word(buf + BPB_FATSz16, (WORD)sz_fat);	/* FAT size [sector] */
+			buf[BS_DrvNum] = 0x80;						/* Drive number (for int13) */
+			buf[BS_BootSig] = 0x29;						/* Extended boot signature */
+			mem_cpy(buf + BS_VolLab, "NO NAME    " "FAT     ", 19);	/* Volume label, FAT signature */
+		}
+		st_word(buf + BS_55AA, 0xAA55);					/* Signature (offset is fixed here regardless of sector size) */
+		if (disk_write(pdrv, buf, b_vol, 1) != RES_OK) return FR_DISK_ERR;	/* Write it to the VBR sector */
+
+		/* Create FSINFO record if needed */
+		if (fmt == FS_FAT32) {
+			disk_write(pdrv, buf, b_vol + 6, 1);		/* Write backup VBR (VBR + 6) */
+			mem_set(buf, 0, ss);
+			st_dword(buf + FSI_LeadSig, 0x41615252);
+			st_dword(buf + FSI_StrucSig, 0x61417272);
+			st_dword(buf + FSI_Free_Count, n_clst - 1);	/* Number of free clusters */
+			st_dword(buf + FSI_Nxt_Free, 2);			/* Last allocated cluster# */
+			st_word(buf + BS_55AA, 0xAA55);
+			disk_write(pdrv, buf, b_vol + 7, 1);		/* Write backup FSINFO (VBR + 7) */
+			disk_write(pdrv, buf, b_vol + 1, 1);		/* Write original FSINFO (VBR + 1) */
+		}
+
+		/* Initialize FAT area */
+		mem_set(buf, 0, (UINT)szb_buf);
+		sect = b_fat;		/* FAT start sector */
+		for (i = 0; i < n_fats; i++) {			/* Initialize FATs each */
+			if (fmt == FS_FAT32) {
+				st_dword(buf + 0, 0xFFFFFFF8);	/* Entry 0 */
+				st_dword(buf + 4, 0xFFFFFFFF);	/* Entry 1 */
+				st_dword(buf + 8, 0x0FFFFFFF);	/* Entry 2 (root directory) */
+			} else {
+				st_dword(buf + 0, (fmt == FS_FAT12) ? 0xFFFFF8 : 0xFFFFFFF8);	/* Entry 0 and 1 */
+			}
+			nsect = sz_fat;		/* Number of FAT sectors */
+			do {	/* Fill FAT sectors */
+				n = (nsect > sz_buf) ? sz_buf : nsect;
+				if (disk_write(pdrv, buf, sect, (UINT)n) != RES_OK) return FR_DISK_ERR;
+				mem_set(buf, 0, ss);
+				sect += n; nsect -= n;
+			} while (nsect);
+		}
+
+		/* Initialize root directory (fill with zero) */
+		nsect = (fmt == FS_FAT32) ? pau : sz_dir;	/* Number of root directory sectors */
+		do {
+			n = (nsect > sz_buf) ? sz_buf : nsect;
+			if (disk_write(pdrv, buf, sect, (UINT)n) != RES_OK) return FR_DISK_ERR;
+			sect += n; nsect -= n;
+		} while (nsect);
+	}
+
+	/* Determine system ID in the partition table */
+	if (_FS_EXFAT && fmt == FS_EXFAT) {
+		sys = 0x07;			/* HPFS/NTFS/exFAT */
+	} else {
+		if (fmt == FS_FAT32) {
+			sys = 0x0C;		/* FAT32X */
+		} else {
+			if (sz_vol >= 0x10000) {
+				sys = 0x06;	/* FAT12/16 (>=64KS) */
+			} else {
+				sys = (fmt == FS_FAT16) ? 0x04 : 0x01;	/* FAT16 (<64KS) : FAT12 (<64KS) */
+			}
+		}
+	}
+
+	/* Update partition information */
+	if (_MULTI_PARTITION && part != 0) {	/* Created in the existing partition */
+		/* Update system ID in the partition table */
+		if (disk_read(pdrv, buf, 0, 1) != RES_OK) return FR_DISK_ERR;	/* Read the MBR */
+		buf[MBR_Table + (part - 1) * SZ_PTE + PTE_System] = sys;		/* Set system ID */
+		if (disk_write(pdrv, buf, 0, 1) != RES_OK) return FR_DISK_ERR;	/* Write it back to the MBR */
+	} else {								/* Created as a new single partition */
+		if (!(opt & FM_SFD)) {	/* Create partition table if in FDISK format */
+			mem_set(buf, 0, ss);
+			st_word(buf + BS_55AA, 0xAA55);		/* MBR signature */
+			pte = buf + MBR_Table;				/* Create partition table for single partition in the drive */
+			pte[PTE_Boot] = 0;					/* Boot indicator */
+			pte[PTE_StHead] = 1;				/* Start head */
+			pte[PTE_StSec] = 1;					/* Start sector */
+			pte[PTE_StCyl] = 0;					/* Start cylinder */
+			pte[PTE_System] = sys;				/* System type */
+			n = (b_vol + sz_vol) / (63 * 255);	/* (End CHS may be invalid) */
+			pte[PTE_EdHead] = 254;				/* End head */
+			pte[PTE_EdSec] = (BYTE)(n >> 2 | 63);	/* End sector */
+			pte[PTE_EdCyl] = (BYTE)n;			/* End cylinder */
+			st_dword(pte + PTE_StLba, b_vol);	/* Start offset in LBA */
+			st_dword(pte + PTE_SizLba, sz_vol);	/* Size in sectors */
+			if (disk_write(pdrv, buf, 0, 1) != RES_OK) return FR_DISK_ERR;	/* Write it to the MBR */
+		}
+	}
+
+	if (disk_ioctl(pdrv, CTRL_SYNC, 0) != RES_OK) return FR_DISK_ERR;
+
+	return FR_OK;
+}
+
+
+
+#if _MULTI_PARTITION
+/*-----------------------------------------------------------------------*/
+/* Create partition table on the physical drive                          */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_fdisk (
+	BYTE pdrv,			/* Physical drive number */
+	const DWORD* szt,	/* Pointer to the size table for each partitions */
+	void* work			/* Pointer to the working buffer */
+)
+{
+	UINT i, n, sz_cyl, tot_cyl, b_cyl, e_cyl, p_cyl;
+	BYTE s_hd, e_hd, *p, *buf = (BYTE*)work;
+	DSTATUS stat;
+	DWORD sz_disk, sz_part, s_part;
+
+
+	stat = disk_initialize(pdrv);
+	if (stat & STA_NOINIT) return FR_NOT_READY;
+	if (stat & STA_PROTECT) return FR_WRITE_PROTECTED;
+	if (disk_ioctl(pdrv, GET_SECTOR_COUNT, &sz_disk)) return FR_DISK_ERR;
+
+	/* Determine the CHS without any consideration of the drive geometry */
+	for (n = 16; n < 256 && sz_disk / n / 63 > 1024; n *= 2) ;
+	if (n == 256) n--;
+	e_hd = n - 1;
+	sz_cyl = 63 * n;
+	tot_cyl = sz_disk / sz_cyl;
+
+	/* Create partition table */
+	mem_set(buf, 0, _MAX_SS);
+	p = buf + MBR_Table; b_cyl = 0;
+	for (i = 0; i < 4; i++, p += SZ_PTE) {
+		p_cyl = (szt[i] <= 100U) ? (DWORD)tot_cyl * szt[i] / 100 : szt[i] / sz_cyl;	/* Number of cylinders */
+		if (!p_cyl) continue;
+		s_part = (DWORD)sz_cyl * b_cyl;
+		sz_part = (DWORD)sz_cyl * p_cyl;
+		if (i == 0) {	/* Exclude first track of cylinder 0 */
+			s_hd = 1;
+			s_part += 63; sz_part -= 63;
+		} else {
+			s_hd = 0;
+		}
+		e_cyl = b_cyl + p_cyl - 1;	/* End cylinder */
+		if (e_cyl >= tot_cyl) return FR_INVALID_PARAMETER;
+
+		/* Set partition table */
+		p[1] = s_hd;						/* Start head */
+		p[2] = (BYTE)((b_cyl >> 2) + 1);	/* Start sector */
+		p[3] = (BYTE)b_cyl;					/* Start cylinder */
+		p[4] = 0x07;						/* System type (temporary setting) */
+		p[5] = e_hd;						/* End head */
+		p[6] = (BYTE)((e_cyl >> 2) + 63);	/* End sector */
+		p[7] = (BYTE)e_cyl;					/* End cylinder */
+		st_dword(p + 8, s_part);			/* Start sector in LBA */
+		st_dword(p + 12, sz_part);			/* Number of sectors */
+
+		/* Next partition */
+		b_cyl += p_cyl;
+	}
+	st_word(p, 0xAA55);
+
+	/* Write it to the MBR */
+	return (disk_write(pdrv, buf, 0, 1) != RES_OK || disk_ioctl(pdrv, CTRL_SYNC, 0) != RES_OK) ? FR_DISK_ERR : FR_OK;
+}
+
+#endif /* _MULTI_PARTITION */
+#endif /* _USE_MKFS && !_FS_READONLY */
+
+
+
+
+#if _USE_STRFUNC
+/*-----------------------------------------------------------------------*/
+/* Get a string from the file                                            */
+/*-----------------------------------------------------------------------*/
+
+TCHAR* f_gets (
+	TCHAR* buff,	/* Pointer to the string buffer to read */
+	int len,		/* Size of string buffer (characters) */
+	FIL* fp			/* Pointer to the file object */
+)
+{
+	int n = 0;
+	TCHAR c, *p = buff;
+	BYTE s[2];
+	UINT rc;
+
+
+	while (n < len - 1) {	/* Read characters until buffer gets filled */
+#if _LFN_UNICODE
+#if _STRF_ENCODE == 3		/* Read a character in UTF-8 */
+		f_read(fp, s, 1, &rc);
+		if (rc != 1) break;
+		c = s[0];
+		if (c >= 0x80) {
+			if (c < 0xC0) continue;	/* Skip stray trailer */
+			if (c < 0xE0) {			/* Two-byte sequence (0x80-0x7FF) */
+				f_read(fp, s, 1, &rc);
+				if (rc != 1) break;
+				c = (c & 0x1F) << 6 | (s[0] & 0x3F);
+				if (c < 0x80) c = '?';	/* Reject invalid code range */
+			} else {
+				if (c < 0xF0) {		/* Three-byte sequence (0x800-0xFFFF) */
+					f_read(fp, s, 2, &rc);
+					if (rc != 2) break;
+					c = c << 12 | (s[0] & 0x3F) << 6 | (s[1] & 0x3F);
+					if (c < 0x800) c = '?';	/* Reject invalid code range */
+				} else {			/* Reject four-byte sequence */
+					c = '?';
+				}
+			}
+		}
+#elif _STRF_ENCODE == 2		/* Read a character in UTF-16BE */
+		f_read(fp, s, 2, &rc);
+		if (rc != 2) break;
+		c = s[1] + (s[0] << 8);
+#elif _STRF_ENCODE == 1		/* Read a character in UTF-16LE */
+		f_read(fp, s, 2, &rc);
+		if (rc != 2) break;
+		c = s[0] + (s[1] << 8);
+#else						/* Read a character in ANSI/OEM */
+		f_read(fp, s, 1, &rc);
+		if (rc != 1) break;
+		c = s[0];
+		if (IsDBCS1(c)) {
+			f_read(fp, s, 1, &rc);
+			if (rc != 1) break;
+			c = (c << 8) + s[0];
+		}
+		c = ff_convert(c, 1);	/* OEM -> Unicode */
+		if (!c) c = '?';
+#endif
+#else						/* Read a character without conversion */
+		f_read(fp, s, 1, &rc);
+		if (rc != 1) break;
+		c = s[0];
+#endif
+		if (_USE_STRFUNC == 2 && c == '\r') continue;	/* Strip '\r' */
+		*p++ = c;
+		n++;
+		if (c == '\n') break;		/* Break on EOL */
+	}
+	*p = 0;
+	return n ? buff : 0;			/* When no data read (eof or error), return with error. */
+}
+
+
+
+
+#if !_FS_READONLY
+#include <stdarg.h>
+/*-----------------------------------------------------------------------*/
+/* Put a character to the file                                           */
+/*-----------------------------------------------------------------------*/
+
+typedef struct {
+	FIL *fp;		/* Ptr to the writing file */
+	int idx, nchr;	/* Write index of buf[] (-1:error), number of chars written */
+	BYTE buf[64];	/* Write buffer */
+} putbuff;
+
+
+static
+void putc_bfd (		/* Buffered write with code conversion */
+	putbuff* pb,
+	TCHAR c
+)
+{
+	UINT bw;
+	int i;
+
+
+	if (_USE_STRFUNC == 2 && c == '\n') {	 /* LF -> CRLF conversion */
+		putc_bfd(pb, '\r');
+	}
+
+	i = pb->idx;		/* Write index of pb->buf[] */
+	if (i < 0) return;
+
+#if _LFN_UNICODE
+#if _STRF_ENCODE == 3			/* Write a character in UTF-8 */
+	if (c < 0x80) {				/* 7-bit */
+		pb->buf[i++] = (BYTE)c;
+	} else {
+		if (c < 0x800) {		/* 11-bit */
+			pb->buf[i++] = (BYTE)(0xC0 | c >> 6);
+		} else {				/* 16-bit */
+			pb->buf[i++] = (BYTE)(0xE0 | c >> 12);
+			pb->buf[i++] = (BYTE)(0x80 | (c >> 6 & 0x3F));
+		}
+		pb->buf[i++] = (BYTE)(0x80 | (c & 0x3F));
+	}
+#elif _STRF_ENCODE == 2			/* Write a character in UTF-16BE */
+	pb->buf[i++] = (BYTE)(c >> 8);
+	pb->buf[i++] = (BYTE)c;
+#elif _STRF_ENCODE == 1			/* Write a character in UTF-16LE */
+	pb->buf[i++] = (BYTE)c;
+	pb->buf[i++] = (BYTE)(c >> 8);
+#else							/* Write a character in ANSI/OEM */
+	c = ff_convert(c, 0);	/* Unicode -> OEM */
+	if (!c) c = '?';
+	if (c >= 0x100)
+		pb->buf[i++] = (BYTE)(c >> 8);
+	pb->buf[i++] = (BYTE)c;
+#endif
+#else							/* Write a character without conversion */
+	pb->buf[i++] = (BYTE)c;
+#endif
+
+	if (i >= (int)(sizeof pb->buf) - 3) {	/* Write buffered characters to the file */
+		f_write(pb->fp, pb->buf, (UINT)i, &bw);
+		i = (bw == (UINT)i) ? 0 : -1;
+	}
+	pb->idx = i;
+	pb->nchr++;
+}
+
+
+static
+int putc_flush (		/* Flush left characters in the buffer */
+	putbuff* pb
+)
+{
+	UINT nw;
+
+	if (   pb->idx >= 0	/* Flush buffered characters to the file */
+		&& f_write(pb->fp, pb->buf, (UINT)pb->idx, &nw) == FR_OK
+		&& (UINT)pb->idx == nw) return pb->nchr;
+	return EOF;
+}
+
+
+static
+void putc_init (		/* Initialize write buffer */
+	putbuff* pb,
+	FIL* fp
+)
+{
+	pb->fp = fp;
+	pb->nchr = pb->idx = 0;
+}
+
+
+
+int f_putc (
+	TCHAR c,	/* A character to be output */
+	FIL* fp		/* Pointer to the file object */
+)
+{
+	putbuff pb;
+
+
+	putc_init(&pb, fp);
+	putc_bfd(&pb, c);	/* Put the character */
+	return putc_flush(&pb);
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Put a string to the file                                              */
+/*-----------------------------------------------------------------------*/
+
+int f_puts (
+	const TCHAR* str,	/* Pointer to the string to be output */
+	FIL* fp				/* Pointer to the file object */
+)
+{
+	putbuff pb;
+
+
+	putc_init(&pb, fp);
+	while (*str) putc_bfd(&pb, *str++);		/* Put the string */
+	return putc_flush(&pb);
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Put a formatted string to the file                                    */
+/*-----------------------------------------------------------------------*/
+
+int f_printf (
+	FIL* fp,			/* Pointer to the file object */
+	const TCHAR* fmt,	/* Pointer to the format string */
+	...					/* Optional arguments... */
+)
+{
+	va_list arp;
+	putbuff pb;
+	BYTE f, r;
+	UINT i, j, w;
+	DWORD v;
+	TCHAR c, d, str[32], *p;
+
+
+	putc_init(&pb, fp);
+
+	va_start(arp, fmt);
+
+	for (;;) {
+		c = *fmt++;
+		if (c == 0) break;			/* End of string */
+		if (c != '%') {				/* Non escape character */
+			putc_bfd(&pb, c);
+			continue;
+		}
+		w = f = 0;
+		c = *fmt++;
+		if (c == '0') {				/* Flag: '0' padding */
+			f = 1; c = *fmt++;
+		} else {
+			if (c == '-') {			/* Flag: left justified */
+				f = 2; c = *fmt++;
+			}
+		}
+		while (IsDigit(c)) {		/* Precision */
+			w = w * 10 + c - '0';
+			c = *fmt++;
+		}
+		if (c == 'l' || c == 'L') {	/* Prefix: Size is long int */
+			f |= 4; c = *fmt++;
+		}
+		if (!c) break;
+		d = c;
+		if (IsLower(d)) d -= 0x20;
+		switch (d) {				/* Type is... */
+		case 'S' :					/* String */
+			p = va_arg(arp, TCHAR*);
+			for (j = 0; p[j]; j++) ;
+			if (!(f & 2)) {
+				while (j++ < w) putc_bfd(&pb, ' ');
+			}
+			while (*p) putc_bfd(&pb, *p++);
+			while (j++ < w) putc_bfd(&pb, ' ');
+			continue;
+
+		case 'C' :					/* Character */
+			putc_bfd(&pb, (TCHAR)va_arg(arp, int)); continue;
+
+		case 'B' :					/* Binary */
+			r = 2; break;
+
+		case 'O' :					/* Octal */
+			r = 8; break;
+
+		case 'D' :					/* Signed decimal */
+		case 'U' :					/* Unsigned decimal */
+			r = 10; break;
+
+		case 'X' :					/* Hexdecimal */
+			r = 16; break;
+
+		default:					/* Unknown type (pass-through) */
+			putc_bfd(&pb, c); continue;
+		}
+
+		/* Get an argument and put it in numeral */
+		v = (f & 4) ? (DWORD)va_arg(arp, long) : ((d == 'D') ? (DWORD)(long)va_arg(arp, int) : (DWORD)va_arg(arp, unsigned int));
+		if (d == 'D' && (v & 0x80000000)) {
+			v = 0 - v;
+			f |= 8;
+		}
+		i = 0;
+		do {
+			d = (TCHAR)(v % r); v /= r;
+			if (d > 9) d += (c == 'x') ? 0x27 : 0x07;
+			str[i++] = d + '0';
+		} while (v && i < sizeof str / sizeof str[0]);
+		if (f & 8) str[i++] = '-';
+		j = i; d = (f & 1) ? '0' : ' ';
+		while (!(f & 2) && j++ < w) putc_bfd(&pb, d);
+		do {
+			putc_bfd(&pb, str[--i]);
+		} while (i);
+		while (j++ < w) putc_bfd(&pb, d);
+	}
+
+	va_end(arp);
+
+	return putc_flush(&pb);
+}
+
+#endif /* !_FS_READONLY */
+#endif /* _USE_STRFUNC */
diff --git a/Middlewares/Third_Party/FatFs/src/ff.h b/Middlewares/Third_Party/FatFs/src/ff.h
new file mode 100644
index 0000000..a233e16
--- /dev/null
+++ b/Middlewares/Third_Party/FatFs/src/ff.h
@@ -0,0 +1,361 @@
+/*----------------------------------------------------------------------------/
+/  FatFs - Generic FAT file system module  R0.12c                             /
+/-----------------------------------------------------------------------------/
+/
+/ Copyright (C) 2017, ChaN, all right reserved.
+/
+/ FatFs module is an open source software. Redistribution and use of FatFs in
+/ source and binary forms, with or without modification, are permitted provided
+/ that the following condition is met:
+
+/ 1. Redistributions of source code must retain the above copyright notice,
+/    this condition and the following disclaimer.
+/
+/ This software is provided by the copyright holder and contributors "AS IS"
+/ and any warranties related to this software are DISCLAIMED.
+/ The copyright owner or contributors be NOT LIABLE for any damages caused
+/ by use of this software.
+/----------------------------------------------------------------------------*/
+
+
+#ifndef _FATFS
+#define _FATFS	68300	/* Revision ID */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "integer.h"	/* Basic integer types */
+#include "ffconf.h"		/* FatFs configuration options */
+
+#if _FATFS != _FFCONF
+#error Wrong configuration file (ffconf.h).
+#endif
+
+
+
+/* Definitions of volume management */
+
+#if _MULTI_PARTITION		/* Multiple partition configuration */
+typedef struct {
+	BYTE pd;	/* Physical drive number */
+	BYTE pt;	/* Partition: 0:Auto detect, 1-4:Forced partition) */
+} PARTITION;
+extern PARTITION VolToPart[];	/* Volume - Partition resolution table */
+#endif
+
+
+
+/* Type of path name strings on FatFs API */
+
+#if _LFN_UNICODE			/* Unicode (UTF-16) string */
+#if _USE_LFN == 0
+#error _LFN_UNICODE must be 0 at non-LFN cfg.
+#endif
+#ifndef _INC_TCHAR
+typedef WCHAR TCHAR;
+#define _T(x) L ## x
+#define _TEXT(x) L ## x
+#endif
+#else						/* ANSI/OEM string */
+#ifndef _INC_TCHAR
+typedef char TCHAR;
+#define _T(x) x
+#define _TEXT(x) x
+#endif
+#endif
+
+
+
+/* Type of file size variables */
+
+#if _FS_EXFAT
+#if _USE_LFN == 0
+#error LFN must be enabled when enable exFAT
+#endif
+typedef QWORD FSIZE_t;
+#else
+typedef DWORD FSIZE_t;
+#endif
+
+
+
+/* File system object structure (FATFS) */
+
+typedef struct {
+	BYTE	fs_type;		/* File system type (0:N/A) */
+	BYTE	drv;			/* Physical drive number */
+	BYTE	n_fats;			/* Number of FATs (1 or 2) */
+	BYTE	wflag;			/* win[] flag (b0:dirty) */
+	BYTE	fsi_flag;		/* FSINFO flags (b7:disabled, b0:dirty) */
+	WORD	id;				/* File system mount ID */
+	WORD	n_rootdir;		/* Number of root directory entries (FAT12/16) */
+	WORD	csize;			/* Cluster size [sectors] */
+#if _MAX_SS != _MIN_SS
+	WORD	ssize;			/* Sector size (512, 1024, 2048 or 4096) */
+#endif
+#if _USE_LFN != 0
+	WCHAR*	lfnbuf;			/* LFN working buffer */
+#endif
+#if _FS_EXFAT
+	BYTE*	dirbuf;			/* Directory entry block scratchpad buffer */
+#endif
+#if _FS_REENTRANT
+	_SYNC_t	sobj;			/* Identifier of sync object */
+#endif
+#if !_FS_READONLY
+	DWORD	last_clst;		/* Last allocated cluster */
+	DWORD	free_clst;		/* Number of free clusters */
+#endif
+#if _FS_RPATH != 0
+	DWORD	cdir;			/* Current directory start cluster (0:root) */
+#if _FS_EXFAT
+	DWORD	cdc_scl;		/* Containing directory start cluster (invalid when cdir is 0) */
+	DWORD	cdc_size;		/* b31-b8:Size of containing directory, b7-b0: Chain status */
+	DWORD	cdc_ofs;		/* Offset in the containing directory (invalid when cdir is 0) */
+#endif
+#endif
+	DWORD	n_fatent;		/* Number of FAT entries (number of clusters + 2) */
+	DWORD	fsize;			/* Size of an FAT [sectors] */
+	DWORD	volbase;		/* Volume base sector */
+	DWORD	fatbase;		/* FAT base sector */
+	DWORD	dirbase;		/* Root directory base sector/cluster */
+	DWORD	database;		/* Data base sector */
+	DWORD	winsect;		/* Current sector appearing in the win[] */
+	BYTE	win[_MAX_SS];	/* Disk access window for Directory, FAT (and file data at tiny cfg) */
+} FATFS;
+
+
+
+/* Object ID and allocation information (_FDID) */
+
+typedef struct {
+	FATFS*	fs;			/* Pointer to the owner file system object */
+	WORD	id;			/* Owner file system mount ID */
+	BYTE	attr;		/* Object attribute */
+	BYTE	stat;		/* Object chain status (b1-0: =0:not contiguous, =2:contiguous (no data on FAT), =3:flagmented in this session, b2:sub-directory stretched) */
+	DWORD	sclust;		/* Object start cluster (0:no cluster or root directory) */
+	FSIZE_t	objsize;	/* Object size (valid when sclust != 0) */
+#if _FS_EXFAT
+	DWORD	n_cont;		/* Size of first fragment, clusters - 1 (valid when stat == 3) */
+	DWORD	n_frag;		/* Size of last fragment needs to be written (valid when not zero) */
+	DWORD	c_scl;		/* Containing directory start cluster (valid when sclust != 0) */
+	DWORD	c_size;		/* b31-b8:Size of containing directory, b7-b0: Chain status (valid when c_scl != 0) */
+	DWORD	c_ofs;		/* Offset in the containing directory (valid when sclust != 0 and non-directory object) */
+#endif
+#if _FS_LOCK != 0
+	UINT	lockid;		/* File lock ID origin from 1 (index of file semaphore table Files[]) */
+#endif
+} _FDID;
+
+
+
+/* File object structure (FIL) */
+
+typedef struct {
+	_FDID	obj;			/* Object identifier (must be the 1st member to detect invalid object pointer) */
+	BYTE	flag;			/* File status flags */
+	BYTE	err;			/* Abort flag (error code) */
+	FSIZE_t	fptr;			/* File read/write pointer (Zeroed on file open) */
+	DWORD	clust;			/* Current cluster of fpter (invalid when fptr is 0) */
+	DWORD	sect;			/* Sector number appearing in buf[] (0:invalid) */
+#if !_FS_READONLY
+	DWORD	dir_sect;		/* Sector number containing the directory entry */
+	BYTE*	dir_ptr;		/* Pointer to the directory entry in the win[] */
+#endif
+#if _USE_FASTSEEK
+	DWORD*	cltbl;			/* Pointer to the cluster link map table (nulled on open, set by application) */
+#endif
+#if !_FS_TINY
+	BYTE	buf[_MAX_SS];	/* File private data read/write window */
+#endif
+} FIL;
+
+
+
+/* Directory object structure (DIR) */
+
+typedef struct {
+	_FDID	obj;			/* Object identifier */
+	DWORD	dptr;			/* Current read/write offset */
+	DWORD	clust;			/* Current cluster */
+	DWORD	sect;			/* Current sector (0:Read operation has terminated) */
+	BYTE*	dir;			/* Pointer to the directory item in the win[] */
+	BYTE	fn[12];			/* SFN (in/out) {body[8],ext[3],status[1]} */
+#if _USE_LFN != 0
+	DWORD	blk_ofs;		/* Offset of current entry block being processed (0xFFFFFFFF:Invalid) */
+#endif
+#if _USE_FIND
+	const TCHAR* pat;		/* Pointer to the name matching pattern */
+#endif
+} DIR;
+
+
+
+/* File information structure (FILINFO) */
+
+typedef struct {
+	FSIZE_t	fsize;			/* File size */
+	WORD	fdate;			/* Modified date */
+	WORD	ftime;			/* Modified time */
+	BYTE	fattrib;		/* File attribute */
+#if _USE_LFN != 0
+	TCHAR	altname[13];			/* Alternative file name */
+	TCHAR	fname[_MAX_LFN + 1];	/* Primary file name */
+#else
+	TCHAR	fname[13];		/* File name */
+#endif
+} FILINFO;
+
+
+
+/* File function return code (FRESULT) */
+
+typedef enum {
+	FR_OK = 0,				/* (0) Succeeded */
+	FR_DISK_ERR,			/* (1) A hard error occurred in the low level disk I/O layer */
+	FR_INT_ERR,				/* (2) Assertion failed */
+	FR_NOT_READY,			/* (3) The physical drive cannot work */
+	FR_NO_FILE,				/* (4) Could not find the file */
+	FR_NO_PATH,				/* (5) Could not find the path */
+	FR_INVALID_NAME,		/* (6) The path name format is invalid */
+	FR_DENIED,				/* (7) Access denied due to prohibited access or directory full */
+	FR_EXIST,				/* (8) Access denied due to prohibited access */
+	FR_INVALID_OBJECT,		/* (9) The file/directory object is invalid */
+	FR_WRITE_PROTECTED,		/* (10) The physical drive is write protected */
+	FR_INVALID_DRIVE,		/* (11) The logical drive number is invalid */
+	FR_NOT_ENABLED,			/* (12) The volume has no work area */
+	FR_NO_FILESYSTEM,		/* (13) There is no valid FAT volume */
+	FR_MKFS_ABORTED,		/* (14) The f_mkfs() aborted due to any problem */
+	FR_TIMEOUT,				/* (15) Could not get a grant to access the volume within defined period */
+	FR_LOCKED,				/* (16) The operation is rejected according to the file sharing policy */
+	FR_NOT_ENOUGH_CORE,		/* (17) LFN working buffer could not be allocated */
+	FR_TOO_MANY_OPEN_FILES,	/* (18) Number of open files > _FS_LOCK */
+	FR_INVALID_PARAMETER	/* (19) Given parameter is invalid */
+} FRESULT;
+
+
+
+/*--------------------------------------------------------------*/
+/* FatFs module application interface                           */
+
+FRESULT f_open (FIL* fp, const TCHAR* path, BYTE mode);				/* Open or create a file */
+FRESULT f_close (FIL* fp);											/* Close an open file object */
+FRESULT f_read (FIL* fp, void* buff, UINT btr, UINT* br);			/* Read data from the file */
+FRESULT f_write (FIL* fp, const void* buff, UINT btw, UINT* bw);	/* Write data to the file */
+FRESULT f_lseek (FIL* fp, FSIZE_t ofs);								/* Move file pointer of the file object */
+FRESULT f_truncate (FIL* fp);										/* Truncate the file */
+FRESULT f_sync (FIL* fp);											/* Flush cached data of the writing file */
+FRESULT f_opendir (DIR* dp, const TCHAR* path);						/* Open a directory */
+FRESULT f_closedir (DIR* dp);										/* Close an open directory */
+FRESULT f_readdir (DIR* dp, FILINFO* fno);							/* Read a directory item */
+FRESULT f_findfirst (DIR* dp, FILINFO* fno, const TCHAR* path, const TCHAR* pattern);	/* Find first file */
+FRESULT f_findnext (DIR* dp, FILINFO* fno);							/* Find next file */
+FRESULT f_mkdir (const TCHAR* path);								/* Create a sub directory */
+FRESULT f_unlink (const TCHAR* path);								/* Delete an existing file or directory */
+FRESULT f_rename (const TCHAR* path_old, const TCHAR* path_new);	/* Rename/Move a file or directory */
+FRESULT f_stat (const TCHAR* path, FILINFO* fno);					/* Get file status */
+FRESULT f_chmod (const TCHAR* path, BYTE attr, BYTE mask);			/* Change attribute of a file/dir */
+FRESULT f_utime (const TCHAR* path, const FILINFO* fno);			/* Change timestamp of a file/dir */
+FRESULT f_chdir (const TCHAR* path);								/* Change current directory */
+FRESULT f_chdrive (const TCHAR* path);								/* Change current drive */
+FRESULT f_getcwd (TCHAR* buff, UINT len);							/* Get current directory */
+FRESULT f_getfree (const TCHAR* path, DWORD* nclst, FATFS** fatfs);	/* Get number of free clusters on the drive */
+FRESULT f_getlabel (const TCHAR* path, TCHAR* label, DWORD* vsn);	/* Get volume label */
+FRESULT f_setlabel (const TCHAR* label);							/* Set volume label */
+FRESULT f_forward (FIL* fp, UINT(*func)(const BYTE*,UINT), UINT btf, UINT* bf);	/* Forward data to the stream */
+FRESULT f_expand (FIL* fp, FSIZE_t szf, BYTE opt);					/* Allocate a contiguous block to the file */
+FRESULT f_mount (FATFS* fs, const TCHAR* path, BYTE opt);			/* Mount/Unmount a logical drive */
+FRESULT f_mkfs (const TCHAR* path, BYTE opt, DWORD au, void* work, UINT len);	/* Create a FAT volume */
+FRESULT f_fdisk (BYTE pdrv, const DWORD* szt, void* work);			/* Divide a physical drive into some partitions */
+int f_putc (TCHAR c, FIL* fp);										/* Put a character to the file */
+int f_puts (const TCHAR* str, FIL* cp);								/* Put a string to the file */
+int f_printf (FIL* fp, const TCHAR* str, ...);						/* Put a formatted string to the file */
+TCHAR* f_gets (TCHAR* buff, int len, FIL* fp);						/* Get a string from the file */
+
+#define f_eof(fp) ((int)((fp)->fptr == (fp)->obj.objsize))
+#define f_error(fp) ((fp)->err)
+#define f_tell(fp) ((fp)->fptr)
+#define f_size(fp) ((fp)->obj.objsize)
+#define f_rewind(fp) f_lseek((fp), 0)
+#define f_rewinddir(dp) f_readdir((dp), 0)
+#define f_rmdir(path) f_unlink(path)
+
+#ifndef EOF
+#define EOF (-1)
+#endif
+
+
+
+
+/*--------------------------------------------------------------*/
+/* Additional user defined functions                            */
+
+/* RTC function */
+#if !_FS_READONLY && !_FS_NORTC
+DWORD get_fattime (void);
+#endif
+
+/* Unicode support functions */
+#if _USE_LFN != 0						/* Unicode - OEM code conversion */
+WCHAR ff_convert (WCHAR chr, UINT dir);	/* OEM-Unicode bidirectional conversion */
+WCHAR ff_wtoupper (WCHAR chr);			/* Unicode upper-case conversion */
+#if _USE_LFN == 3						/* Memory functions */
+void* ff_memalloc (UINT msize);			/* Allocate memory block */
+void ff_memfree (void* mblock);			/* Free memory block */
+#endif
+#endif
+
+/* Sync functions */
+#if _FS_REENTRANT
+int ff_cre_syncobj (BYTE vol, _SYNC_t* sobj);	/* Create a sync object */
+int ff_req_grant (_SYNC_t sobj);				/* Lock sync object */
+void ff_rel_grant (_SYNC_t sobj);				/* Unlock sync object */
+int ff_del_syncobj (_SYNC_t sobj);				/* Delete a sync object */
+#endif
+
+
+
+
+/*--------------------------------------------------------------*/
+/* Flags and offset address                                     */
+
+
+/* File access mode and open method flags (3rd argument of f_open) */
+#define	FA_READ				0x01
+#define	FA_WRITE			0x02
+#define	FA_OPEN_EXISTING	0x00
+#define	FA_CREATE_NEW		0x04
+#define	FA_CREATE_ALWAYS	0x08
+#define	FA_OPEN_ALWAYS		0x10
+#define	FA_OPEN_APPEND		0x30
+
+/* Fast seek controls (2nd argument of f_lseek) */
+#define CREATE_LINKMAP	((FSIZE_t)0 - 1)
+
+/* Format options (2nd argument of f_mkfs) */
+#define FM_FAT		0x01
+#define FM_FAT32	0x02
+#define FM_EXFAT	0x04
+#define FM_ANY		0x07
+#define FM_SFD		0x08
+
+/* Filesystem type (FATFS.fs_type) */
+#define FS_FAT12	1
+#define FS_FAT16	2
+#define FS_FAT32	3
+#define FS_EXFAT	4
+
+/* File attribute bits for directory entry (FILINFO.fattrib) */
+#define	AM_RDO	0x01	/* Read only */
+#define	AM_HID	0x02	/* Hidden */
+#define	AM_SYS	0x04	/* System */
+#define AM_DIR	0x10	/* Directory */
+#define AM_ARC	0x20	/* Archive */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _FATFS */
diff --git a/Middlewares/Third_Party/FatFs/src/ff_gen_drv.c b/Middlewares/Third_Party/FatFs/src/ff_gen_drv.c
new file mode 100644
index 0000000..1036ef4
--- /dev/null
+++ b/Middlewares/Third_Party/FatFs/src/ff_gen_drv.c
@@ -0,0 +1,122 @@
+/**
+  ******************************************************************************
+  * @file    ff_gen_drv.c
+  * @author  MCD Application Team
+  * @brief   FatFs generic low level driver.
+  *****************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics. All rights reserved.
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                       opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+**/
+/* Includes ------------------------------------------------------------------*/
+#include "ff_gen_drv.h"
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+Disk_drvTypeDef disk = {{0},{0},{0},0};
+
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/**
+  * @brief  Links a compatible diskio driver/lun id and increments the number of active
+  *         linked drivers.
+  * @note   The number of linked drivers (volumes) is up to 10 due to FatFs limits.
+  * @param  drv: pointer to the disk IO Driver structure
+  * @param  path: pointer to the logical drive path
+  * @param  lun : only used for USB Key Disk to add multi-lun management
+            else the parameter must be equal to 0
+  * @retval Returns 0 in case of success, otherwise 1.
+  */
+uint8_t FATFS_LinkDriverEx(const Diskio_drvTypeDef *drv, char *path, uint8_t lun)
+{
+  uint8_t ret = 1;
+  uint8_t DiskNum = 0;
+
+  if(disk.nbr < _VOLUMES)
+  {
+    disk.is_initialized[disk.nbr] = 0;
+    disk.drv[disk.nbr] = drv;
+    disk.lun[disk.nbr] = lun;
+    DiskNum = disk.nbr++;
+    path[0] = DiskNum + '0';
+    path[1] = ':';
+    path[2] = '/';
+    path[3] = 0;
+    ret = 0;
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  Links a compatible diskio driver and increments the number of active
+  *         linked drivers.
+  * @note   The number of linked drivers (volumes) is up to 10 due to FatFs limits
+  * @param  drv: pointer to the disk IO Driver structure
+  * @param  path: pointer to the logical drive path
+  * @retval Returns 0 in case of success, otherwise 1.
+  */
+uint8_t FATFS_LinkDriver(const Diskio_drvTypeDef *drv, char *path)
+{
+  return FATFS_LinkDriverEx(drv, path, 0);
+}
+
+/**
+  * @brief  Unlinks a diskio driver and decrements the number of active linked
+  *         drivers.
+  * @param  path: pointer to the logical drive path
+  * @param  lun : not used
+  * @retval Returns 0 in case of success, otherwise 1.
+  */
+uint8_t FATFS_UnLinkDriverEx(char *path, uint8_t lun)
+{
+  uint8_t DiskNum = 0;
+  uint8_t ret = 1;
+
+  if(disk.nbr >= 1)
+  {
+    DiskNum = path[0] - '0';
+    if(disk.drv[DiskNum] != 0)
+    {
+      disk.drv[DiskNum] = 0;
+      disk.lun[DiskNum] = 0;
+      disk.nbr--;
+      ret = 0;
+    }
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  Unlinks a diskio driver and decrements the number of active linked
+  *         drivers.
+  * @param  path: pointer to the logical drive path
+  * @retval Returns 0 in case of success, otherwise 1.
+  */
+uint8_t FATFS_UnLinkDriver(char *path)
+{
+  return FATFS_UnLinkDriverEx(path, 0);
+}
+
+/**
+  * @brief  Gets number of linked drivers to the FatFs module.
+  * @param  None
+  * @retval Number of attached drivers.
+  */
+uint8_t FATFS_GetAttachedDriversNbr(void)
+{
+  return disk.nbr;
+}
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/Middlewares/Third_Party/FatFs/src/ff_gen_drv.h b/Middlewares/Third_Party/FatFs/src/ff_gen_drv.h
new file mode 100644
index 0000000..65d879c
--- /dev/null
+++ b/Middlewares/Third_Party/FatFs/src/ff_gen_drv.h
@@ -0,0 +1,80 @@
+/**
+  ******************************************************************************
+  * @file    ff_gen_drv.h
+  * @author  MCD Application Team
+  * @brief   Header for ff_gen_drv.c module.
+  *****************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics. All rights reserved.
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                       opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+**/
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __FF_GEN_DRV_H
+#define __FF_GEN_DRV_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "diskio.h"
+#include "ff.h"
+#include "stdint.h"
+
+
+/* Exported types ------------------------------------------------------------*/
+
+/**
+  * @brief  Disk IO Driver structure definition
+  */
+typedef struct
+{
+  DSTATUS (*disk_initialize) (BYTE);                     /*!< Initialize Disk Drive                     */
+  DSTATUS (*disk_status)     (BYTE);                     /*!< Get Disk Status                           */
+  DRESULT (*disk_read)       (BYTE, BYTE*, DWORD, UINT);       /*!< Read Sector(s)                            */
+#if _USE_WRITE == 1
+  DRESULT (*disk_write)      (BYTE, const BYTE*, DWORD, UINT); /*!< Write Sector(s) when _USE_WRITE = 0       */
+#endif /* _USE_WRITE == 1 */
+#if _USE_IOCTL == 1
+  DRESULT (*disk_ioctl)      (BYTE, BYTE, void*);              /*!< I/O control operation when _USE_IOCTL = 1 */
+#endif /* _USE_IOCTL == 1 */
+
+}Diskio_drvTypeDef;
+
+/**
+  * @brief  Global Disk IO Drivers structure definition
+  */
+typedef struct
+{
+  uint8_t                 is_initialized[_VOLUMES];
+  const Diskio_drvTypeDef *drv[_VOLUMES];
+  uint8_t                 lun[_VOLUMES];
+  volatile uint8_t        nbr;
+
+}Disk_drvTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+uint8_t FATFS_LinkDriver(const Diskio_drvTypeDef *drv, char *path);
+uint8_t FATFS_UnLinkDriver(char *path);
+uint8_t FATFS_LinkDriverEx(const Diskio_drvTypeDef *drv, char *path, BYTE lun);
+uint8_t FATFS_UnLinkDriverEx(char *path, BYTE lun);
+uint8_t FATFS_GetAttachedDriversNbr(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __FF_GEN_DRV_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/Middlewares/Third_Party/FatFs/src/integer.h b/Middlewares/Third_Party/FatFs/src/integer.h
new file mode 100644
index 0000000..d8e911c
--- /dev/null
+++ b/Middlewares/Third_Party/FatFs/src/integer.h
@@ -0,0 +1,38 @@
+/*-------------------------------------------*/
+/* Integer type definitions for FatFs module */
+/*-------------------------------------------*/
+
+#ifndef _FF_INTEGER
+#define _FF_INTEGER
+
+#ifdef _WIN32	/* FatFs development platform */
+
+#include <windows.h>
+#include <tchar.h>
+typedef unsigned __int64 QWORD;
+
+
+#else			/* Embedded platform */
+
+/* These types MUST be 16-bit or 32-bit */
+typedef int				INT;
+typedef unsigned int	UINT;
+
+/* This type MUST be 8-bit */
+typedef unsigned char	BYTE;
+
+/* These types MUST be 16-bit */
+typedef short			SHORT;
+typedef unsigned short	WORD;
+typedef unsigned short	WCHAR;
+
+/* These types MUST be 32-bit */
+typedef long			LONG;
+typedef unsigned long	DWORD;
+
+/* This type MUST be 64-bit (Remove this for ANSI C (C89) compatibility) */
+typedef unsigned long long QWORD;
+
+#endif
+
+#endif
diff --git a/Middlewares/Third_Party/FatFs/src/option/syscall.c b/Middlewares/Third_Party/FatFs/src/option/syscall.c
new file mode 100644
index 0000000..327d941
--- /dev/null
+++ b/Middlewares/Third_Party/FatFs/src/option/syscall.c
@@ -0,0 +1,177 @@
+/*------------------------------------------------------------------------*/
+/* Sample code of OS dependent controls for FatFs                         */
+/* (C)ChaN, 2014                                                          */
+/*   Portions COPYRIGHT 2017 STMicroelectronics                           */
+/*   Portions Copyright (C) 2014, ChaN, all right reserved                */
+/*------------------------------------------------------------------------*/
+
+/**
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics. All rights reserved.
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                       opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+**/
+
+
+
+#include "../ff.h"
+
+
+#if _FS_REENTRANT
+/*------------------------------------------------------------------------*/
+/* Create a Synchronization Object                                        */
+/*------------------------------------------------------------------------*/
+/* This function is called in f_mount() function to create a new
+/  synchronization object, such as semaphore and mutex. When a 0 is returned,
+/  the f_mount() function fails with FR_INT_ERR.
+*/
+
+int ff_cre_syncobj (	/* 1:Function succeeded, 0:Could not create the sync object */
+	BYTE vol,			/* Corresponding volume (logical drive number) */
+	_SYNC_t *sobj		/* Pointer to return the created sync object */
+)
+{
+
+    int ret;
+#if _USE_MUTEX
+
+#if (osCMSIS < 0x20000U)
+    osMutexDef(MTX);
+    *sobj = osMutexCreate(osMutex(MTX));
+#else
+    *sobj = osMutexNew(NULL);
+#endif
+
+#else
+
+#if (osCMSIS < 0x20000U)
+    osSemaphoreDef(SEM);
+    *sobj = osSemaphoreCreate(osSemaphore(SEM), 1);
+#else
+    *sobj = osSemaphoreNew(1, 1, NULL);
+#endif
+
+#endif
+    ret = (*sobj != NULL);
+
+    return ret;
+}
+
+
+
+/*------------------------------------------------------------------------*/
+/* Delete a Synchronization Object                                        */
+/*------------------------------------------------------------------------*/
+/* This function is called in f_mount() function to delete a synchronization
+/  object that created with ff_cre_syncobj() function. When a 0 is returned,
+/  the f_mount() function fails with FR_INT_ERR.
+*/
+
+int ff_del_syncobj (	/* 1:Function succeeded, 0:Could not delete due to any error */
+	_SYNC_t sobj		/* Sync object tied to the logical drive to be deleted */
+)
+{
+#if _USE_MUTEX
+    osMutexDelete (sobj);
+#else
+    osSemaphoreDelete (sobj);
+#endif
+    return 1;
+}
+
+
+
+/*------------------------------------------------------------------------*/
+/* Request Grant to Access the Volume                                     */
+/*------------------------------------------------------------------------*/
+/* This function is called on entering file functions to lock the volume.
+/  When a 0 is returned, the file function fails with FR_TIMEOUT.
+*/
+
+int ff_req_grant (	/* 1:Got a grant to access the volume, 0:Could not get a grant */
+	_SYNC_t sobj	/* Sync object to wait */
+)
+{
+  int ret = 0;
+#if (osCMSIS < 0x20000U)
+
+#if _USE_MUTEX
+  if(osMutexWait(sobj, _FS_TIMEOUT) == osOK)
+#else
+  if(osSemaphoreWait(sobj, _FS_TIMEOUT) == osOK)
+#endif
+
+#else
+
+#if _USE_MUTEX
+   if(osMutexAcquire(sobj, _FS_TIMEOUT) == osOK)
+#else
+   if(osSemaphoreAcquire(sobj, _FS_TIMEOUT) == osOK)
+#endif
+
+#endif
+  {
+    ret = 1;
+  }
+
+  return ret;
+}
+
+
+
+/*------------------------------------------------------------------------*/
+/* Release Grant to Access the Volume                                     */
+/*------------------------------------------------------------------------*/
+/* This function is called on leaving file functions to unlock the volume.
+*/
+
+void ff_rel_grant (
+	_SYNC_t sobj	/* Sync object to be signaled */
+)
+{
+#if _USE_MUTEX
+  osMutexRelease(sobj);
+#else
+  osSemaphoreRelease(sobj);
+#endif
+}
+
+#endif
+
+
+
+
+#if _USE_LFN == 3	/* LFN with a working buffer on the heap */
+/*------------------------------------------------------------------------*/
+/* Allocate a memory block                                                */
+/*------------------------------------------------------------------------*/
+/* If a NULL is returned, the file function fails with FR_NOT_ENOUGH_CORE.
+*/
+
+void* ff_memalloc (	/* Returns pointer to the allocated memory block */
+	UINT msize		/* Number of bytes to allocate */
+)
+{
+	return ff_malloc(msize);	/* Allocate a new memory block with POSIX API */
+}
+
+
+/*------------------------------------------------------------------------*/
+/* Free a memory block                                                    */
+/*------------------------------------------------------------------------*/
+
+void ff_memfree (
+	void* mblock	/* Pointer to the memory block to free */
+)
+{
+	ff_free(mblock);	/* Discard the memory block with POSIX API */
+}
+
+#endif
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os.h b/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os.h
new file mode 100644
index 0000000..6375df1
--- /dev/null
+++ b/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os.h
@@ -0,0 +1,846 @@
+/*
+ * Copyright (c) 2013-2019 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * ----------------------------------------------------------------------
+ *
+ * $Date:        10. January 2017
+ * $Revision:    V2.1.0
+ *
+ * Project:      CMSIS-RTOS API
+ * Title:        cmsis_os.h FreeRTOS header file
+ *
+ * Version 0.02
+ *    Initial Proposal Phase
+ * Version 0.03
+ *    osKernelStart added, optional feature: main started as thread
+ *    osSemaphores have standard behavior
+ *    osTimerCreate does not start the timer, added osTimerStart
+ *    osThreadPass is renamed to osThreadYield
+ * Version 1.01
+ *    Support for C++ interface
+ *     - const attribute removed from the osXxxxDef_t typedefs
+ *     - const attribute added to the osXxxxDef macros
+ *    Added: osTimerDelete, osMutexDelete, osSemaphoreDelete
+ *    Added: osKernelInitialize
+ * Version 1.02
+ *    Control functions for short timeouts in microsecond resolution:
+ *    Added: osKernelSysTick, osKernelSysTickFrequency, osKernelSysTickMicroSec
+ *    Removed: osSignalGet 
+ * Version 2.0.0
+ *    OS objects creation without macros (dynamic creation and resource allocation):
+ *     - added: osXxxxNew functions which replace osXxxxCreate
+ *     - added: osXxxxAttr_t structures
+ *     - deprecated: osXxxxCreate functions, osXxxxDef_t structures
+ *     - deprecated: osXxxxDef and osXxxx macros
+ *    osStatus codes simplified and renamed to osStatus_t
+ *    osEvent return structure deprecated
+ *    Kernel:
+ *     - added: osKernelInfo_t and osKernelGetInfo
+ *     - added: osKernelState_t and osKernelGetState (replaces osKernelRunning)
+ *     - added: osKernelLock, osKernelUnlock
+ *     - added: osKernelSuspend, osKernelResume
+ *     - added: osKernelGetTickCount, osKernelGetTickFreq
+ *     - renamed osKernelSysTick to osKernelGetSysTimerCount
+ *     - replaced osKernelSysTickFrequency with osKernelGetSysTimerFreq
+ *     - deprecated osKernelSysTickMicroSec
+ *    Thread:
+ *     - extended number of thread priorities
+ *     - renamed osPrioriry to osPrioriry_t
+ *     - replaced osThreadCreate with osThreadNew
+ *     - added: osThreadGetName
+ *     - added: osThreadState_t and osThreadGetState
+ *     - added: osThreadGetStackSize, osThreadGetStackSpace
+ *     - added: osThreadSuspend, osThreadResume
+ *     - added: osThreadJoin, osThreadDetach, osThreadExit
+ *     - added: osThreadGetCount, osThreadEnumerate
+ *     - added: Thread Flags (moved from Signals) 
+ *    Signals:
+ *     - renamed osSignals to osThreadFlags (moved to Thread Flags)
+ *     - changed return value of Set/Clear/Wait functions
+ *     - Clear function limited to current running thread
+ *     - extended Wait function (options)
+ *     - added: osThreadFlagsGet
+ *    Event Flags:
+ *     - added new independent object for handling Event Flags
+ *    Delay and Wait functions:
+ *     - added: osDelayUntil
+ *     - deprecated: osWait
+ *    Timer:
+ *     - replaced osTimerCreate with osTimerNew
+ *     - added: osTimerGetName, osTimerIsRunning
+ *    Mutex:
+ *     - extended: attributes (Recursive, Priority Inherit, Robust)
+ *     - replaced osMutexCreate with osMutexNew
+ *     - renamed osMutexWait to osMutexAcquire
+ *     - added: osMutexGetName, osMutexGetOwner
+ *    Semaphore:
+ *     - extended: maximum and initial token count
+ *     - replaced osSemaphoreCreate with osSemaphoreNew
+ *     - renamed osSemaphoreWait to osSemaphoreAcquire (changed return value)
+ *     - added: osSemaphoreGetName, osSemaphoreGetCount
+ *    Memory Pool:
+ *     - using osMemoryPool prefix instead of osPool
+ *     - replaced osPoolCreate with osMemoryPoolNew
+ *     - extended osMemoryPoolAlloc (timeout)
+ *     - added: osMemoryPoolGetName
+ *     - added: osMemoryPoolGetCapacity, osMemoryPoolGetBlockSize
+ *     - added: osMemoryPoolGetCount, osMemoryPoolGetSpace
+ *     - added: osMemoryPoolDelete
+ *     - deprecated: osPoolCAlloc
+ *    Message Queue:
+ *     - extended: fixed size message instead of a single 32-bit value
+ *     - using osMessageQueue prefix instead of osMessage
+ *     - replaced osMessageCreate with osMessageQueueNew
+ *     - updated: osMessageQueuePut, osMessageQueueGet
+ *     - added: osMessageQueueGetName
+ *     - added: osMessageQueueGetCapacity, osMessageQueueGetMsgSize
+ *     - added: osMessageQueueGetCount, osMessageQueueGetSpace
+ *     - added: osMessageQueueReset, osMessageQueueDelete
+ *    Mail Queue: 
+ *     - deprecated (superseded by extended Message Queue functionality)
+ * Version 2.1.0
+ *    Support for critical and uncritical sections (nesting safe):
+ *    - updated: osKernelLock, osKernelUnlock
+ *    - added: osKernelRestoreLock
+ *    Updated Thread and Event Flags:
+ *    - changed flags parameter and return type from int32_t to uint32_t
+ *---------------------------------------------------------------------------*/
+ 
+#ifndef CMSIS_OS_H_
+#define CMSIS_OS_H_
+
+#include "FreeRTOS.h"
+#include "task.h"
+
+#define RTOS_ID_n             ((tskKERNEL_VERSION_MAJOR << 16) | (tskKERNEL_VERSION_MINOR))
+#define RTOS_ID_s             ("FreeRTOS " tskKERNEL_VERSION_NUMBER)
+
+#define osCMSIS               0x20001U  ///< API version (main[31:16].sub[15:0])
+
+#define osCMSIS_FreeRTOS      RTOS_ID_n ///< RTOS identification and version (main[31:16].sub[15:0])
+ 
+#define osKernelSystemId      RTOS_ID_s ///< RTOS identification string
+ 
+#define osFeature_MainThread  0         ///< main thread      1=main can be thread, 0=not available
+#define osFeature_Signals     24U       ///< maximum number of Signal Flags available per thread
+#define osFeature_Semaphore   65535U    ///< maximum count for \ref osSemaphoreCreate function
+#define osFeature_Wait        0         ///< osWait function: 1=available, 0=not available
+#define osFeature_SysTick     1         ///< osKernelSysTick functions: 1=available, 0=not available
+#define osFeature_Pool        0         ///< Memory Pools:    1=available, 0=not available
+#define osFeature_MessageQ    1         ///< Message Queues:  1=available, 0=not available
+#define osFeature_MailQ       0         ///< Mail Queues:     1=available, 0=not available
+ 
+#if   defined(__CC_ARM)
+#define os_InRegs __value_in_regs
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#define os_InRegs __attribute__((value_in_regs))
+#else
+#define os_InRegs
+#endif
+ 
+#include "cmsis_os2.h"
+ 
+#ifdef  __cplusplus
+extern "C"
+{
+#endif
+ 
+ 
+// ==== Enumerations, structures, defines ====
+ 
+/// Priority values.
+#if (osCMSIS < 0x20000U)
+typedef enum {
+  osPriorityIdle          = -3,         ///< Priority: idle (lowest)
+  osPriorityLow           = -2,         ///< Priority: low
+  osPriorityBelowNormal   = -1,         ///< Priority: below normal
+  osPriorityNormal        =  0,         ///< Priority: normal (default)
+  osPriorityAboveNormal   = +1,         ///< Priority: above normal
+  osPriorityHigh          = +2,         ///< Priority: high
+  osPriorityRealtime      = +3,         ///< Priority: realtime (highest)
+  osPriorityError         = 0x84,       ///< System cannot determine priority or illegal priority.
+  osPriorityReserved      = 0x7FFFFFFF  ///< Prevents enum down-size compiler optimization.
+} osPriority;
+#else
+#define osPriority osPriority_t
+#endif
+
+/// Entry point of a thread.
+typedef void (*os_pthread) (void const *argument);
+ 
+/// Entry point of a timer call back function.
+typedef void (*os_ptimer) (void const *argument);
+ 
+/// Timer type.
+#if (osCMSIS < 0x20000U)
+typedef enum {
+  osTimerOnce             = 0,          ///< One-shot timer.
+  osTimerPeriodic         = 1           ///< Repeating timer.
+} os_timer_type;
+#else
+#define os_timer_type osTimerType_t
+#endif
+ 
+/// Timeout value.
+#define osWaitForever       0xFFFFFFFFU ///< Wait forever timeout value.
+ 
+/// Status code values returned by CMSIS-RTOS functions.
+#if (osCMSIS < 0x20000U)
+typedef enum {
+  osOK                    =    0,       ///< Function completed; no error or event occurred.
+  osEventSignal           = 0x08,       ///< Function completed; signal event occurred.
+  osEventMessage          = 0x10,       ///< Function completed; message event occurred.
+  osEventMail             = 0x20,       ///< Function completed; mail event occurred.
+  osEventTimeout          = 0x40,       ///< Function completed; timeout occurred.
+  osErrorParameter        = 0x80,       ///< Parameter error: a mandatory parameter was missing or specified an incorrect object.
+  osErrorResource         = 0x81,       ///< Resource not available: a specified resource was not available.
+  osErrorTimeoutResource  = 0xC1,       ///< Resource not available within given time: a specified resource was not available within the timeout period.
+  osErrorISR              = 0x82,       ///< Not allowed in ISR context: the function cannot be called from interrupt service routines.
+  osErrorISRRecursive     = 0x83,       ///< Function called multiple times from ISR with same object.
+  osErrorPriority         = 0x84,       ///< System cannot determine priority or thread has illegal priority.
+  osErrorNoMemory         = 0x85,       ///< System is out of memory: it was impossible to allocate or reserve memory for the operation.
+  osErrorValue            = 0x86,       ///< Value of a parameter is out of range.
+  osErrorOS               = 0xFF,       ///< Unspecified RTOS error: run-time error but no other error message fits.
+  osStatusReserved        = 0x7FFFFFFF  ///< Prevents enum down-size compiler optimization.
+} osStatus;
+#else
+typedef int32_t                  osStatus;
+#define osEventSignal           (0x08)
+#define osEventMessage          (0x10)
+#define osEventMail             (0x20)
+#define osEventTimeout          (0x40)
+#define osErrorOS               osError
+#define osErrorTimeoutResource  osErrorTimeout
+#define osErrorISRRecursive     (-126)
+#define osErrorValue            (-127)
+#define osErrorPriority         (-128)
+#endif
+ 
+ 
+// >>> the following data type definitions may be adapted towards a specific RTOS
+ 
+/// Thread ID identifies the thread.
+#if (osCMSIS < 0x20000U)
+typedef void *osThreadId;
+#else
+#define osThreadId osThreadId_t
+#endif
+ 
+/// Timer ID identifies the timer.
+#if (osCMSIS < 0x20000U)
+typedef void *osTimerId;
+#else
+#define osTimerId osTimerId_t
+#endif
+ 
+/// Mutex ID identifies the mutex.
+#if (osCMSIS < 0x20000U)
+typedef void *osMutexId;
+#else
+#define osMutexId osMutexId_t
+#endif
+ 
+/// Semaphore ID identifies the semaphore.
+#if (osCMSIS < 0x20000U)
+typedef void *osSemaphoreId;
+#else
+#define osSemaphoreId osSemaphoreId_t
+#endif
+ 
+/// Pool ID identifies the memory pool.
+typedef void *osPoolId;
+ 
+/// Message ID identifies the message queue.
+typedef void *osMessageQId;
+ 
+/// Mail ID identifies the mail queue.
+typedef void *osMailQId;
+ 
+ 
+/// Thread Definition structure contains startup information of a thread.
+#if (osCMSIS < 0x20000U)
+typedef struct os_thread_def {
+  os_pthread                 pthread;   ///< start address of thread function
+  osPriority               tpriority;   ///< initial thread priority
+  uint32_t                 instances;   ///< maximum number of instances of that thread function
+  uint32_t                 stacksize;   ///< stack size requirements in bytes; 0 is default stack size
+} osThreadDef_t;
+#else
+typedef struct os_thread_def {
+  os_pthread                 pthread;   ///< start address of thread function
+  osThreadAttr_t                attr;   ///< thread attributes
+} osThreadDef_t;
+#endif
+ 
+/// Timer Definition structure contains timer parameters.
+#if (osCMSIS < 0x20000U)
+typedef struct os_timer_def {
+  os_ptimer                   ptimer;   ///< start address of a timer function
+} osTimerDef_t;
+#else
+typedef struct os_timer_def {
+  os_ptimer                   ptimer;   ///< start address of a timer function
+  osTimerAttr_t                 attr;   ///< timer attributes
+} osTimerDef_t;
+#endif
+ 
+/// Mutex Definition structure contains setup information for a mutex.
+#if (osCMSIS < 0x20000U)
+typedef struct os_mutex_def {
+  uint32_t                     dummy;   ///< dummy value
+} osMutexDef_t;
+#else
+#define osMutexDef_t osMutexAttr_t
+#endif
+ 
+/// Semaphore Definition structure contains setup information for a semaphore.
+#if (osCMSIS < 0x20000U)
+typedef struct os_semaphore_def {
+  uint32_t                     dummy;   ///< dummy value
+} osSemaphoreDef_t;
+#else
+#define osSemaphoreDef_t osSemaphoreAttr_t
+#endif
+ 
+/// Definition structure for memory block allocation.
+#if (osCMSIS < 0x20000U)
+typedef struct os_pool_def {
+  uint32_t                   pool_sz;   ///< number of items (elements) in the pool
+  uint32_t                   item_sz;   ///< size of an item
+  void                         *pool;   ///< pointer to memory for pool
+} osPoolDef_t;
+#else
+typedef struct os_pool_def {
+  uint32_t                   pool_sz;   ///< number of items (elements) in the pool
+  uint32_t                   item_sz;   ///< size of an item
+  osMemoryPoolAttr_t            attr;   ///< memory pool attributes
+} osPoolDef_t;
+#endif
+ 
+/// Definition structure for message queue.
+#if (osCMSIS < 0x20000U)
+typedef struct os_messageQ_def {
+  uint32_t                  queue_sz;   ///< number of elements in the queue
+  void                         *pool;   ///< memory array for messages
+} osMessageQDef_t;
+#else
+typedef struct os_messageQ_def {
+  uint32_t                  queue_sz;   ///< number of elements in the queue
+  osMessageQueueAttr_t          attr;   ///< message queue attributes
+} osMessageQDef_t;
+#endif
+ 
+/// Definition structure for mail queue.
+#if (osCMSIS < 0x20000U)
+typedef struct os_mailQ_def {
+  uint32_t                  queue_sz;   ///< number of elements in the queue
+  uint32_t                   item_sz;   ///< size of an item
+  void                         *pool;   ///< memory array for mail
+} osMailQDef_t;
+#else
+typedef struct os_mailQ_def {
+  uint32_t                  queue_sz;   ///< number of elements in the queue
+  uint32_t                   item_sz;   ///< size of an item
+  void                         *mail;   ///< pointer to mail
+  osMemoryPoolAttr_t         mp_attr;   ///< memory pool attributes
+  osMessageQueueAttr_t       mq_attr;   ///< message queue attributes
+} osMailQDef_t;
+#endif
+ 
+ 
+/// Event structure contains detailed information about an event.
+typedef struct {
+  osStatus                    status;   ///< status code: event or error information
+  union {
+    uint32_t                       v;   ///< message as 32-bit value
+    void                          *p;   ///< message or mail as void pointer
+    int32_t                  signals;   ///< signal flags
+  } value;                              ///< event value
+  union {
+    osMailQId                mail_id;   ///< mail id obtained by \ref osMailCreate
+    osMessageQId          message_id;   ///< message id obtained by \ref osMessageCreate
+  } def;                                ///< event definition
+} osEvent;
+ 
+ 
+//  ==== Kernel Management Functions ====
+ 
+/// Initialize the RTOS Kernel for creating objects.
+/// \return status code that indicates the execution status of the function.
+#if (osCMSIS < 0x20000U)
+osStatus osKernelInitialize (void);
+#endif
+ 
+/// Start the RTOS Kernel scheduler.
+/// \return status code that indicates the execution status of the function.
+#if (osCMSIS < 0x20000U)
+osStatus osKernelStart (void);
+#endif
+ 
+/// Check if the RTOS kernel is already started.
+/// \return 0 RTOS is not started, 1 RTOS is started.
+#if (osCMSIS < 0x20000U)
+int32_t osKernelRunning(void);
+#endif
+ 
+#if (defined(osFeature_SysTick) && (osFeature_SysTick != 0))  // System Timer available
+ 
+/// Get the RTOS kernel system timer counter.
+/// \return RTOS kernel system timer as 32-bit value 
+#if (osCMSIS < 0x20000U)
+uint32_t osKernelSysTick (void);
+#else
+#define  osKernelSysTick osKernelGetSysTimerCount
+#endif
+ 
+/// The RTOS kernel system timer frequency in Hz.
+/// \note Reflects the system timer setting and is typically defined in a configuration file.
+#if (osCMSIS < 0x20000U)
+#define osKernelSysTickFrequency 100000000
+#endif
+ 
+/// Convert a microseconds value to a RTOS kernel system timer value.
+/// \param         microsec     time value in microseconds.
+/// \return time value normalized to the \ref osKernelSysTickFrequency
+#if (osCMSIS < 0x20000U)
+#define osKernelSysTickMicroSec(microsec) (((uint64_t)microsec * (osKernelSysTickFrequency)) / 1000000)
+#else
+#define osKernelSysTickMicroSec(microsec) (((uint64_t)microsec *  osKernelGetSysTimerFreq()) / 1000000)
+#endif
+ 
+#endif  // System Timer available
+ 
+ 
+//  ==== Thread Management Functions ====
+ 
+/// Create a Thread Definition with function, priority, and stack requirements.
+/// \param         name          name of the thread function.
+/// \param         priority      initial priority of the thread function.
+/// \param         instances     number of possible thread instances.
+/// \param         stacksz       stack size (in bytes) requirements for the thread function.
+#if defined (osObjectsExternal)  // object is external
+#define osThreadDef(name, priority, instances, stacksz) \
+extern const osThreadDef_t os_thread_def_##name
+#else                            // define the object
+#define osThreadDef(name, priority, instances, stacksz) \
+static uint64_t os_thread_stack##name[(stacksz)?(((stacksz+7)/8)):1]; \
+static StaticTask_t os_thread_cb_##name; \
+const osThreadDef_t os_thread_def_##name = \
+{ (name), \
+  { NULL, osThreadDetached, \
+    (instances == 1) ? (&os_thread_cb_##name) : NULL,\
+    (instances == 1) ? sizeof(StaticTask_t) : 0U, \
+    ((stacksz) && (instances == 1)) ? (&os_thread_stack##name) : NULL, \
+    8*((stacksz+7)/8), \
+    (priority), 0U, 0U } }
+#endif
+ 
+/// Access a Thread definition.
+/// \param         name          name of the thread definition object.
+#define osThread(name) \
+&os_thread_def_##name
+ 
+/// Create a thread and add it to Active Threads and set it to state READY.
+/// \param[in]     thread_def    thread definition referenced with \ref osThread.
+/// \param[in]     argument      pointer that is passed to the thread function as start argument.
+/// \return thread ID for reference by other functions or NULL in case of error.
+osThreadId osThreadCreate (const osThreadDef_t *thread_def, void *argument);
+ 
+/// Return the thread ID of the current running thread.
+/// \return thread ID for reference by other functions or NULL in case of error.
+#if (osCMSIS < 0x20000U)
+osThreadId osThreadGetId (void);
+#endif
+ 
+/// Change priority of a thread.
+/// \param[in]     thread_id     thread ID obtained by \ref osThreadCreate or \ref osThreadGetId.
+/// \param[in]     priority      new priority value for the thread function.
+/// \return status code that indicates the execution status of the function.
+#if (osCMSIS < 0x20000U)
+osStatus osThreadSetPriority (osThreadId thread_id, osPriority priority);
+#endif
+ 
+/// Get current priority of a thread.
+/// \param[in]     thread_id     thread ID obtained by \ref osThreadCreate or \ref osThreadGetId.
+/// \return current priority value of the specified thread.
+#if (osCMSIS < 0x20000U)
+osPriority osThreadGetPriority (osThreadId thread_id);
+#endif
+ 
+/// Pass control to next thread that is in state \b READY.
+/// \return status code that indicates the execution status of the function.
+#if (osCMSIS < 0x20000U)
+osStatus osThreadYield (void);
+#endif
+ 
+/// Terminate execution of a thread.
+/// \param[in]     thread_id     thread ID obtained by \ref osThreadCreate or \ref osThreadGetId.
+/// \return status code that indicates the execution status of the function.
+#if (osCMSIS < 0x20000U)
+osStatus osThreadTerminate (osThreadId thread_id);
+#endif
+ 
+ 
+//  ==== Signal Management ====
+ 
+/// Set the specified Signal Flags of an active thread.
+/// \param[in]     thread_id     thread ID obtained by \ref osThreadCreate or \ref osThreadGetId.
+/// \param[in]     signals       specifies the signal flags of the thread that should be set.
+/// \return previous signal flags of the specified thread or 0x80000000 in case of incorrect parameters.
+int32_t osSignalSet (osThreadId thread_id, int32_t signals);
+ 
+/// Clear the specified Signal Flags of an active thread.
+/// \param[in]     thread_id     thread ID obtained by \ref osThreadCreate or \ref osThreadGetId.
+/// \param[in]     signals       specifies the signal flags of the thread that shall be cleared.
+/// \return previous signal flags of the specified thread or 0x80000000 in case of incorrect parameters or call from ISR.
+int32_t osSignalClear (osThreadId thread_id, int32_t signals);
+ 
+/// Wait for one or more Signal Flags to become signaled for the current \b RUNNING thread.
+/// \param[in]     signals       wait until all specified signal flags set or 0 for any single signal flag.
+/// \param[in]     millisec      \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.
+/// \return event flag information or error code.
+os_InRegs osEvent osSignalWait (int32_t signals, uint32_t millisec);
+ 
+ 
+//  ==== Generic Wait Functions ====
+ 
+/// Wait for Timeout (Time Delay).
+/// \param[in]     millisec      \ref CMSIS_RTOS_TimeOutValue "time delay" value
+/// \return status code that indicates the execution status of the function.
+#if (osCMSIS < 0x20000U)
+osStatus osDelay (uint32_t millisec);
+#endif
+ 
+#if (defined (osFeature_Wait) && (osFeature_Wait != 0))  // Generic Wait available
+ 
+/// Wait for Signal, Message, Mail, or Timeout.
+/// \param[in] millisec          \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out
+/// \return event that contains signal, message, or mail information or error code.
+os_InRegs osEvent osWait (uint32_t millisec);
+ 
+#endif  // Generic Wait available
+ 
+ 
+//  ==== Timer Management Functions ====
+ 
+/// Define a Timer object.
+/// \param         name          name of the timer object.
+/// \param         function      name of the timer call back function.
+#if defined (osObjectsExternal)  // object is external
+#define osTimerDef(name, function) \
+extern const osTimerDef_t os_timer_def_##name
+#else                            // define the object
+#define osTimerDef(name, function) \
+static StaticTimer_t os_timer_cb_##name; \
+const osTimerDef_t os_timer_def_##name = \
+{ (function), { NULL, 0U, (&os_timer_cb_##name), sizeof(StaticTimer_t) } }
+#endif
+ 
+/// Access a Timer definition.
+/// \param         name          name of the timer object.
+#define osTimer(name) \
+&os_timer_def_##name
+ 
+/// Create and Initialize a timer.
+/// \param[in]     timer_def     timer object referenced with \ref osTimer.
+/// \param[in]     type          osTimerOnce for one-shot or osTimerPeriodic for periodic behavior.
+/// \param[in]     argument      argument to the timer call back function.
+/// \return timer ID for reference by other functions or NULL in case of error.
+osTimerId osTimerCreate (const osTimerDef_t *timer_def, os_timer_type type, void *argument);
+ 
+/// Start or restart a timer.
+/// \param[in]     timer_id      timer ID obtained by \ref osTimerCreate.
+/// \param[in]     millisec      \ref CMSIS_RTOS_TimeOutValue "time delay" value of the timer.
+/// \return status code that indicates the execution status of the function.
+#if (osCMSIS < 0x20000U)
+osStatus osTimerStart (osTimerId timer_id, uint32_t millisec);
+#endif
+ 
+/// Stop a timer.
+/// \param[in]     timer_id      timer ID obtained by \ref osTimerCreate.
+/// \return status code that indicates the execution status of the function.
+#if (osCMSIS < 0x20000U)
+osStatus osTimerStop (osTimerId timer_id);
+#endif
+ 
+/// Delete a timer.
+/// \param[in]     timer_id      timer ID obtained by \ref osTimerCreate.
+/// \return status code that indicates the execution status of the function.
+#if (osCMSIS < 0x20000U)
+osStatus osTimerDelete (osTimerId timer_id);
+#endif
+ 
+ 
+//  ==== Mutex Management Functions ====
+ 
+/// Define a Mutex.
+/// \param         name          name of the mutex object.
+#if defined (osObjectsExternal)  // object is external
+#define osMutexDef(name) \
+extern const osMutexDef_t os_mutex_def_##name
+#else                            // define the object
+#define osMutexDef(name) \
+static StaticSemaphore_t os_mutex_cb_##name; \
+const osMutexDef_t os_mutex_def_##name = \
+{ NULL, osMutexRecursive | osMutexPrioInherit, (&os_mutex_cb_##name), sizeof(StaticSemaphore_t) }
+#endif
+ 
+/// Access a Mutex definition.
+/// \param         name          name of the mutex object.
+#define osMutex(name) \
+&os_mutex_def_##name
+ 
+/// Create and Initialize a Mutex object.
+/// \param[in]     mutex_def     mutex definition referenced with \ref osMutex.
+/// \return mutex ID for reference by other functions or NULL in case of error.
+osMutexId osMutexCreate (const osMutexDef_t *mutex_def);
+ 
+/// Wait until a Mutex becomes available.
+/// \param[in]     mutex_id      mutex ID obtained by \ref osMutexCreate.
+/// \param[in]     millisec      \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.
+/// \return status code that indicates the execution status of the function.
+#if (osCMSIS < 0x20000U)
+osStatus osMutexWait (osMutexId mutex_id, uint32_t millisec);
+#else
+#define  osMutexWait osMutexAcquire
+#endif
+ 
+/// Release a Mutex that was obtained by \ref osMutexWait.
+/// \param[in]     mutex_id      mutex ID obtained by \ref osMutexCreate.
+/// \return status code that indicates the execution status of the function.
+#if (osCMSIS < 0x20000U)
+osStatus osMutexRelease (osMutexId mutex_id);
+#endif
+ 
+/// Delete a Mutex object.
+/// \param[in]     mutex_id      mutex ID obtained by \ref osMutexCreate.
+/// \return status code that indicates the execution status of the function.
+#if (osCMSIS < 0x20000U)
+osStatus osMutexDelete (osMutexId mutex_id);
+#endif
+ 
+ 
+//  ==== Semaphore Management Functions ====
+ 
+#if (defined (osFeature_Semaphore) && (osFeature_Semaphore != 0U))  // Semaphore available
+ 
+/// Define a Semaphore object.
+/// \param         name          name of the semaphore object.
+#if defined (osObjectsExternal)  // object is external
+#define osSemaphoreDef(name) \
+extern const osSemaphoreDef_t os_semaphore_def_##name
+#else                            // define the object
+#define osSemaphoreDef(name) \
+static StaticSemaphore_t os_semaphore_cb_##name; \
+const osSemaphoreDef_t os_semaphore_def_##name = \
+{ NULL, 0U, (&os_semaphore_cb_##name), sizeof(StaticSemaphore_t) }
+#endif
+ 
+/// Access a Semaphore definition.
+/// \param         name          name of the semaphore object.
+#define osSemaphore(name) \
+&os_semaphore_def_##name
+ 
+/// Create and Initialize a Semaphore object.
+/// \param[in]     semaphore_def semaphore definition referenced with \ref osSemaphore.
+/// \param[in]     count         maximum and initial number of available tokens.
+/// \return semaphore ID for reference by other functions or NULL in case of error.
+osSemaphoreId osSemaphoreCreate (const osSemaphoreDef_t *semaphore_def, int32_t count);
+ 
+/// Wait until a Semaphore token becomes available.
+/// \param[in]     semaphore_id  semaphore object referenced with \ref osSemaphoreCreate.
+/// \param[in]     millisec      \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.
+/// \return number of available tokens, or -1 in case of incorrect parameters.
+int32_t osSemaphoreWait (osSemaphoreId semaphore_id, uint32_t millisec);
+ 
+/// Release a Semaphore token.
+/// \param[in]     semaphore_id  semaphore object referenced with \ref osSemaphoreCreate.
+/// \return status code that indicates the execution status of the function.
+#if (osCMSIS < 0x20000U)
+osStatus osSemaphoreRelease (osSemaphoreId semaphore_id);
+#endif
+ 
+/// Delete a Semaphore object.
+/// \param[in]     semaphore_id  semaphore object referenced with \ref osSemaphoreCreate.
+/// \return status code that indicates the execution status of the function.
+#if (osCMSIS < 0x20000U)
+osStatus osSemaphoreDelete (osSemaphoreId semaphore_id);
+#endif
+ 
+#endif  // Semaphore available
+ 
+ 
+//  ==== Memory Pool Management Functions ====
+
+#if (defined(osFeature_Pool) && (osFeature_Pool != 0))  // Memory Pool available
+ 
+/// \brief Define a Memory Pool.
+/// \param         name          name of the memory pool.
+/// \param         no            maximum number of blocks (objects) in the memory pool.
+/// \param         type          data type of a single block (object).
+#if defined (osObjectsExternal)  // object is external
+#define osPoolDef(name, no, type) \
+extern const osPoolDef_t os_pool_def_##name
+#else                            // define the object
+#define osPoolDef(name, no, type) \
+const osPoolDef_t os_pool_def_##name = \
+{ (no), sizeof(type), {NULL} }
+#endif
+ 
+/// \brief Access a Memory Pool definition.
+/// \param         name          name of the memory pool
+#define osPool(name) \
+&os_pool_def_##name
+ 
+/// Create and Initialize a Memory Pool object.
+/// \param[in]     pool_def      memory pool definition referenced with \ref osPool.
+/// \return memory pool ID for reference by other functions or NULL in case of error.
+osPoolId osPoolCreate (const osPoolDef_t *pool_def);
+ 
+/// Allocate a memory block from a Memory Pool.
+/// \param[in]     pool_id       memory pool ID obtain referenced with \ref osPoolCreate.
+/// \return address of the allocated memory block or NULL in case of no memory available.
+void *osPoolAlloc (osPoolId pool_id);
+ 
+/// Allocate a memory block from a Memory Pool and set memory block to zero.
+/// \param[in]     pool_id       memory pool ID obtain referenced with \ref osPoolCreate.
+/// \return address of the allocated memory block or NULL in case of no memory available.
+void *osPoolCAlloc (osPoolId pool_id);
+ 
+/// Return an allocated memory block back to a Memory Pool.
+/// \param[in]     pool_id       memory pool ID obtain referenced with \ref osPoolCreate.
+/// \param[in]     block         address of the allocated memory block to be returned to the memory pool.
+/// \return status code that indicates the execution status of the function.
+osStatus osPoolFree (osPoolId pool_id, void *block);
+ 
+#endif  // Memory Pool available
+ 
+ 
+//  ==== Message Queue Management Functions ====
+ 
+#if (defined(osFeature_MessageQ) && (osFeature_MessageQ != 0))  // Message Queue available
+  
+/// \brief Create a Message Queue Definition.
+/// \param         name          name of the queue.
+/// \param         queue_sz      maximum number of messages in the queue.
+/// \param         type          data type of a single message element (for debugger).
+#if defined (osObjectsExternal)  // object is external
+#define osMessageQDef(name, queue_sz, type) \
+extern const osMessageQDef_t os_messageQ_def_##name
+#else                            // define the object
+#define osMessageQDef(name, queue_sz, type) \
+static StaticQueue_t os_mq_cb_##name; \
+static uint32_t os_mq_data_##name[(queue_sz) * sizeof(type)]; \
+const osMessageQDef_t os_messageQ_def_##name = \
+{ (queue_sz), \
+  { NULL, 0U, (&os_mq_cb_##name), sizeof(StaticQueue_t), \
+              (&os_mq_data_##name), sizeof(os_mq_data_##name) } }
+#endif
+ 
+/// \brief Access a Message Queue Definition.
+/// \param         name          name of the queue
+#define osMessageQ(name) \
+&os_messageQ_def_##name
+ 
+/// Create and Initialize a Message Queue object.
+/// \param[in]     queue_def     message queue definition referenced with \ref osMessageQ.
+/// \param[in]     thread_id     thread ID (obtained by \ref osThreadCreate or \ref osThreadGetId) or NULL.
+/// \return message queue ID for reference by other functions or NULL in case of error.
+osMessageQId osMessageCreate (const osMessageQDef_t *queue_def, osThreadId thread_id);
+ 
+/// Put a Message to a Queue.
+/// \param[in]     queue_id      message queue ID obtained with \ref osMessageCreate.
+/// \param[in]     info          message information.
+/// \param[in]     millisec      \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.
+/// \return status code that indicates the execution status of the function.
+osStatus osMessagePut (osMessageQId queue_id, uint32_t info, uint32_t millisec);
+ 
+/// Get a Message from a Queue or timeout if Queue is empty.
+/// \param[in]     queue_id      message queue ID obtained with \ref osMessageCreate.
+/// \param[in]     millisec      \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.
+/// \return event information that includes status code.
+os_InRegs osEvent osMessageGet (osMessageQId queue_id, uint32_t millisec);
+ 
+#endif  // Message Queue available
+ 
+ 
+//  ==== Mail Queue Management Functions ====
+ 
+#if (defined(osFeature_MailQ) && (osFeature_MailQ != 0))  // Mail Queue available
+ 
+/// \brief Create a Mail Queue Definition.
+/// \param         name          name of the queue.
+/// \param         queue_sz      maximum number of mails in the queue.
+/// \param         type          data type of a single mail element.
+#if defined (osObjectsExternal)  // object is external
+#define osMailQDef(name, queue_sz, type) \
+extern const osMailQDef_t os_mailQ_def_##name
+#else                            // define the object
+#define osMailQDef(name, queue_sz, type) \
+const osMailQDef_t os_mailQ_def_##name = \
+{ (queue_sz), sizeof(type), NULL }
+#endif
+ 
+/// \brief Access a Mail Queue Definition.
+/// \param         name          name of the queue
+#define osMailQ(name) \
+&os_mailQ_def_##name
+ 
+/// Create and Initialize a Mail Queue object.
+/// \param[in]     queue_def     mail queue definition referenced with \ref osMailQ.
+/// \param[in]     thread_id     thread ID (obtained by \ref osThreadCreate or \ref osThreadGetId) or NULL.
+/// \return mail queue ID for reference by other functions or NULL in case of error.
+osMailQId osMailCreate (const osMailQDef_t *queue_def, osThreadId thread_id);
+ 
+/// Allocate a memory block for mail from a mail memory pool.
+/// \param[in]     queue_id      mail queue ID obtained with \ref osMailCreate.
+/// \param[in]     millisec      \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out
+/// \return pointer to memory block that can be filled with mail or NULL in case of error.
+void *osMailAlloc (osMailQId queue_id, uint32_t millisec);
+ 
+/// Allocate a memory block for mail from a mail memory pool and set memory block to zero.
+/// \param[in]     queue_id      mail queue ID obtained with \ref osMailCreate.
+/// \param[in]     millisec      \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out
+/// \return pointer to memory block that can be filled with mail or NULL in case of error.
+void *osMailCAlloc (osMailQId queue_id, uint32_t millisec);
+ 
+/// Put a Mail into a Queue.
+/// \param[in]     queue_id      mail queue ID obtained with \ref osMailCreate.
+/// \param[in]     mail          pointer to memory with mail to put into a queue.
+/// \return status code that indicates the execution status of the function.
+osStatus osMailPut (osMailQId queue_id, const void *mail);
+ 
+/// Get a Mail from a Queue or timeout if Queue is empty.
+/// \param[in]     queue_id      mail queue ID obtained with \ref osMailCreate.
+/// \param[in]     millisec      \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.
+/// \return event information that includes status code.
+os_InRegs osEvent osMailGet (osMailQId queue_id, uint32_t millisec);
+ 
+/// Free a memory block by returning it to a mail memory pool.
+/// \param[in]     queue_id      mail queue ID obtained with \ref osMailCreate.
+/// \param[in]     mail          pointer to memory block that was obtained with \ref osMailGet.
+/// \return status code that indicates the execution status of the function.
+osStatus osMailFree (osMailQId queue_id, void *mail);
+ 
+#endif  // Mail Queue available
+ 
+ 
+#ifdef  __cplusplus
+}
+#endif
+ 
+#endif  // CMSIS_OS_H_
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.c b/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.c
new file mode 100644
index 0000000..60e5b08
--- /dev/null
+++ b/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.c
@@ -0,0 +1,2482 @@
+/* --------------------------------------------------------------------------
+ * Copyright (c) 2013-2020 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ *      Name:    cmsis_os2.c
+ *      Purpose: CMSIS RTOS2 wrapper for FreeRTOS
+ *
+ *---------------------------------------------------------------------------*/
+
+#include <string.h>
+
+#include "cmsis_os2.h"                  // ::CMSIS:RTOS2
+#include "cmsis_compiler.h"             // Compiler agnostic definitions
+
+#include "FreeRTOS.h"                   // ARM.FreeRTOS::RTOS:Core
+#include "task.h"                       // ARM.FreeRTOS::RTOS:Core
+#include "event_groups.h"               // ARM.FreeRTOS::RTOS:Event Groups
+#include "semphr.h"                     // ARM.FreeRTOS::RTOS:Core
+
+#include "freertos_mpool.h"             // osMemoryPool definitions
+#include "freertos_os2.h"               // Configuration check and setup
+
+/*---------------------------------------------------------------------------*/
+#ifndef __ARM_ARCH_6M__
+  #define __ARM_ARCH_6M__         0
+#endif
+#ifndef __ARM_ARCH_7M__
+  #define __ARM_ARCH_7M__         0
+#endif
+#ifndef __ARM_ARCH_7EM__
+  #define __ARM_ARCH_7EM__        0
+#endif
+#ifndef __ARM_ARCH_8M_MAIN__
+  #define __ARM_ARCH_8M_MAIN__    0
+#endif
+#ifndef __ARM_ARCH_7A__
+  #define __ARM_ARCH_7A__         0
+#endif
+
+#if   ((__ARM_ARCH_7M__      == 1U) || \
+       (__ARM_ARCH_7EM__     == 1U) || \
+       (__ARM_ARCH_8M_MAIN__ == 1U))
+#define IS_IRQ_MASKED()           ((__get_PRIMASK() != 0U) || (__get_BASEPRI() != 0U))
+#elif  (__ARM_ARCH_6M__      == 1U)
+#define IS_IRQ_MASKED()           (__get_PRIMASK() != 0U)
+#elif (__ARM_ARCH_7A__       == 1U)
+/* CPSR mask bits */
+#define CPSR_MASKBIT_I            0x80U
+
+#define IS_IRQ_MASKED()           ((__get_CPSR() & CPSR_MASKBIT_I) != 0U)
+#else
+#define IS_IRQ_MASKED()           (__get_PRIMASK() != 0U)
+#endif
+
+#if    (__ARM_ARCH_7A__      == 1U)
+/* CPSR mode bitmasks */
+#define CPSR_MODE_USER            0x10U
+#define CPSR_MODE_SYSTEM          0x1FU
+
+#define IS_IRQ_MODE()             ((__get_mode() != CPSR_MODE_USER) && (__get_mode() != CPSR_MODE_SYSTEM))
+#else
+#define IS_IRQ_MODE()             (__get_IPSR() != 0U)
+#endif
+
+#define IS_IRQ()                  IS_IRQ_MODE()
+
+#define SVCall_IRQ_NBR            (IRQn_Type) -5	/* SVCall_IRQ_NBR added as SV_Call handler name is not the same for CM0 and for all other CMx */
+
+/* Limits */
+#define MAX_BITS_TASK_NOTIFY      31U
+#define MAX_BITS_EVENT_GROUPS     24U
+
+#define THREAD_FLAGS_INVALID_BITS (~((1UL << MAX_BITS_TASK_NOTIFY)  - 1U))
+#define EVENT_FLAGS_INVALID_BITS  (~((1UL << MAX_BITS_EVENT_GROUPS) - 1U))
+
+/* Kernel version and identification string definition (major.minor.rev: mmnnnrrrr dec) */
+#define KERNEL_VERSION            (((uint32_t)tskKERNEL_VERSION_MAJOR * 10000000UL) | \
+                                   ((uint32_t)tskKERNEL_VERSION_MINOR *    10000UL) | \
+                                   ((uint32_t)tskKERNEL_VERSION_BUILD *        1UL))
+
+#define KERNEL_ID                 ("FreeRTOS " tskKERNEL_VERSION_NUMBER)
+
+/* Timer callback information structure definition */
+typedef struct {
+  osTimerFunc_t func;
+  void         *arg;
+} TimerCallback_t;
+
+/* Kernel initialization state */
+static osKernelState_t KernelState = osKernelInactive;
+
+/*
+  Heap region definition used by heap_5 variant
+
+  Define configAPPLICATION_ALLOCATED_HEAP as nonzero value in FreeRTOSConfig.h if
+  heap regions are already defined and vPortDefineHeapRegions is called in application.
+
+  Otherwise vPortDefineHeapRegions will be called by osKernelInitialize using
+  definition configHEAP_5_REGIONS as parameter. Overriding configHEAP_5_REGIONS
+  is possible by defining it globally or in FreeRTOSConfig.h.
+*/
+#if defined(USE_FreeRTOS_HEAP_5)
+#if (configAPPLICATION_ALLOCATED_HEAP == 0)
+  /*
+    FreeRTOS heap is not defined by the application.
+    Single region of size configTOTAL_HEAP_SIZE (defined in FreeRTOSConfig.h)
+    is provided by default. Define configHEAP_5_REGIONS to provide custom
+    HeapRegion_t array.
+  */
+  #define HEAP_5_REGION_SETUP   1
+  
+  #ifndef configHEAP_5_REGIONS
+    #define configHEAP_5_REGIONS xHeapRegions
+
+    static uint8_t ucHeap[configTOTAL_HEAP_SIZE];
+
+    static HeapRegion_t xHeapRegions[] = {
+      { ucHeap, configTOTAL_HEAP_SIZE },
+      { NULL,   0                     }
+    };
+  #else
+    /* Global definition is provided to override default heap array */
+    extern HeapRegion_t configHEAP_5_REGIONS[];
+  #endif
+#else
+  /*
+    The application already defined the array used for the FreeRTOS heap and
+    called vPortDefineHeapRegions to initialize heap.
+  */
+  #define HEAP_5_REGION_SETUP   0
+#endif /* configAPPLICATION_ALLOCATED_HEAP */
+#endif /* USE_FreeRTOS_HEAP_5 */
+
+#if defined(SysTick)
+#undef SysTick_Handler
+
+/* CMSIS SysTick interrupt handler prototype */
+extern void SysTick_Handler     (void);
+/* FreeRTOS tick timer interrupt handler prototype */
+extern void xPortSysTickHandler (void);
+
+/*
+  SysTick handler implementation that also clears overflow flag.
+*/
+#if (USE_CUSTOM_SYSTICK_HANDLER_IMPLEMENTATION == 0)
+void SysTick_Handler (void) {
+  /* Clear overflow flag */
+  SysTick->CTRL;
+
+  if (xTaskGetSchedulerState() != taskSCHEDULER_NOT_STARTED) {
+    /* Call tick handler */
+    xPortSysTickHandler();
+  }
+}
+#endif
+#endif /* SysTick */
+
+/*
+  Setup SVC to reset value.
+*/
+__STATIC_INLINE void SVC_Setup (void) {
+#if (__ARM_ARCH_7A__ == 0U)
+  /* Service Call interrupt might be configured before kernel start     */
+  /* and when its priority is lower or equal to BASEPRI, svc intruction */
+  /* causes a Hard Fault.                                               */
+  NVIC_SetPriority (SVCall_IRQ_NBR, 0U);
+#endif
+}
+
+/*
+  Function macro used to retrieve semaphore count from ISR
+*/
+#ifndef uxSemaphoreGetCountFromISR
+#define uxSemaphoreGetCountFromISR( xSemaphore ) uxQueueMessagesWaitingFromISR( ( QueueHandle_t ) ( xSemaphore ) )
+#endif
+
+/* Get OS Tick count value */
+static uint32_t OS_Tick_GetCount (void);
+/* Get OS Tick overflow status */
+static uint32_t OS_Tick_GetOverflow (void);
+/* Get OS Tick interval */
+static uint32_t OS_Tick_GetInterval (void);
+/*---------------------------------------------------------------------------*/
+
+osStatus_t osKernelInitialize (void) {
+  osStatus_t stat;
+
+  if (IS_IRQ()) {
+    stat = osErrorISR;
+  }
+  else {
+    if (KernelState == osKernelInactive) {
+      #if defined(USE_TRACE_EVENT_RECORDER)
+        EvrFreeRTOSSetup(0U);
+      #endif
+      #if defined(USE_FreeRTOS_HEAP_5) && (HEAP_5_REGION_SETUP == 1)
+        vPortDefineHeapRegions (configHEAP_5_REGIONS);
+      #endif
+      KernelState = osKernelReady;
+      stat = osOK;
+    } else {
+      stat = osError;
+    }
+  }
+
+  return (stat);
+}
+
+osStatus_t osKernelGetInfo (osVersion_t *version, char *id_buf, uint32_t id_size) {
+
+  if (version != NULL) {
+    /* Version encoding is major.minor.rev: mmnnnrrrr dec */
+    version->api    = KERNEL_VERSION;
+    version->kernel = KERNEL_VERSION;
+  }
+
+  if ((id_buf != NULL) && (id_size != 0U)) {
+    if (id_size > sizeof(KERNEL_ID)) {
+      id_size = sizeof(KERNEL_ID);
+    }
+    memcpy(id_buf, KERNEL_ID, id_size);
+  }
+
+  return (osOK);
+}
+
+osKernelState_t osKernelGetState (void) {
+  osKernelState_t state;
+
+  switch (xTaskGetSchedulerState()) {
+    case taskSCHEDULER_RUNNING:
+      state = osKernelRunning;
+      break;
+
+    case taskSCHEDULER_SUSPENDED:
+      state = osKernelLocked;
+      break;
+
+    case taskSCHEDULER_NOT_STARTED:
+    default:
+      if (KernelState == osKernelReady) {
+        state = osKernelReady;
+      } else {
+        state = osKernelInactive;
+      }
+      break;
+  }
+
+  return (state);
+}
+
+osStatus_t osKernelStart (void) {
+  osStatus_t stat;
+
+  if (IS_IRQ()) {
+    stat = osErrorISR;
+  }
+  else {
+    if (KernelState == osKernelReady) {
+      /* Ensure SVC priority is at the reset value */
+      SVC_Setup();
+      /* Change state to enable IRQ masking check */
+      KernelState = osKernelRunning;
+      /* Start the kernel scheduler */
+      vTaskStartScheduler();
+      stat = osOK;
+    } else {
+      stat = osError;
+    }
+  }
+
+  return (stat);
+}
+
+int32_t osKernelLock (void) {
+  int32_t lock;
+
+  if (IS_IRQ()) {
+    lock = (int32_t)osErrorISR;
+  }
+  else {
+    switch (xTaskGetSchedulerState()) {
+      case taskSCHEDULER_SUSPENDED:
+        lock = 1;
+        break;
+
+      case taskSCHEDULER_RUNNING:
+        vTaskSuspendAll();
+        lock = 0;
+        break;
+
+      case taskSCHEDULER_NOT_STARTED:
+      default:
+        lock = (int32_t)osError;
+        break;
+    }
+  }
+
+  return (lock);
+}
+
+int32_t osKernelUnlock (void) {
+  int32_t lock;
+
+  if (IS_IRQ()) {
+    lock = (int32_t)osErrorISR;
+  }
+  else {
+    switch (xTaskGetSchedulerState()) {
+      case taskSCHEDULER_SUSPENDED:
+        lock = 1;
+
+        if (xTaskResumeAll() != pdTRUE) {
+          if (xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED) {
+            lock = (int32_t)osError;
+          }
+        }
+        break;
+
+      case taskSCHEDULER_RUNNING:
+        lock = 0;
+        break;
+
+      case taskSCHEDULER_NOT_STARTED:
+      default:
+        lock = (int32_t)osError;
+        break;
+    }
+  }
+
+  return (lock);
+}
+
+int32_t osKernelRestoreLock (int32_t lock) {
+
+  if (IS_IRQ()) {
+    lock = (int32_t)osErrorISR;
+  }
+  else {
+    switch (xTaskGetSchedulerState()) {
+      case taskSCHEDULER_SUSPENDED:
+      case taskSCHEDULER_RUNNING:
+        if (lock == 1) {
+          vTaskSuspendAll();
+        }
+        else {
+          if (lock != 0) {
+            lock = (int32_t)osError;
+          }
+          else {
+            if (xTaskResumeAll() != pdTRUE) {
+              if (xTaskGetSchedulerState() != taskSCHEDULER_RUNNING) {
+                lock = (int32_t)osError;
+              }
+            }
+          }
+        }
+        break;
+
+      case taskSCHEDULER_NOT_STARTED:
+      default:
+        lock = (int32_t)osError;
+        break;
+    }
+  }
+
+  return (lock);
+}
+
+uint32_t osKernelGetTickCount (void) {
+  TickType_t ticks;
+
+  if (IS_IRQ()) {
+    ticks = xTaskGetTickCountFromISR();
+  } else {
+    ticks = xTaskGetTickCount();
+  }
+
+  return (ticks);
+}
+
+uint32_t osKernelGetTickFreq (void) {
+  return (configTICK_RATE_HZ);
+}
+
+/* Get OS Tick count value */
+static uint32_t OS_Tick_GetCount (void) {
+  uint32_t load = SysTick->LOAD;
+  return  (load - SysTick->VAL);
+}
+
+/* Get OS Tick overflow status */
+static uint32_t OS_Tick_GetOverflow (void) {
+  return ((SysTick->CTRL >> 16) & 1U);
+}
+
+/* Get OS Tick interval */
+static uint32_t OS_Tick_GetInterval (void) {
+  return (SysTick->LOAD + 1U);
+}
+
+uint32_t osKernelGetSysTimerCount (void) {
+  uint32_t irqmask = IS_IRQ_MASKED();
+  TickType_t ticks;
+  uint32_t val;
+
+  __disable_irq();
+
+  ticks = xTaskGetTickCount();
+  val   = OS_Tick_GetCount();
+
+  if (OS_Tick_GetOverflow() != 0U) {
+    val = OS_Tick_GetCount();
+    ticks++;
+  }
+  val += ticks * OS_Tick_GetInterval();
+
+  if (irqmask == 0U) {
+    __enable_irq();
+  }
+
+  return (val);
+}
+
+uint32_t osKernelGetSysTimerFreq (void) {
+  return (configCPU_CLOCK_HZ);
+}
+
+/*---------------------------------------------------------------------------*/
+
+osThreadId_t osThreadNew (osThreadFunc_t func, void *argument, const osThreadAttr_t *attr) {
+  const char *name;
+  uint32_t stack;
+  TaskHandle_t hTask;
+  UBaseType_t prio;
+  int32_t mem;
+
+  hTask = NULL;
+
+  if (!IS_IRQ() && (func != NULL)) {
+    stack = configMINIMAL_STACK_SIZE;
+    prio  = (UBaseType_t)osPriorityNormal;
+
+    name = NULL;
+    mem  = -1;
+
+    if (attr != NULL) {
+      if (attr->name != NULL) {
+        name = attr->name;
+      }
+      if (attr->priority != osPriorityNone) {
+        prio = (UBaseType_t)attr->priority;
+      }
+
+      if ((prio < osPriorityIdle) || (prio > osPriorityISR) || ((attr->attr_bits & osThreadJoinable) == osThreadJoinable)) {
+        return (NULL);
+      }
+
+      if (attr->stack_size > 0U) {
+        /* In FreeRTOS stack is not in bytes, but in sizeof(StackType_t) which is 4 on ARM ports.       */
+        /* Stack size should be therefore 4 byte aligned in order to avoid division caused side effects */
+        stack = attr->stack_size / sizeof(StackType_t);
+      }
+
+      if ((attr->cb_mem    != NULL) && (attr->cb_size    >= sizeof(StaticTask_t)) &&
+          (attr->stack_mem != NULL) && (attr->stack_size >  0U)) {
+        mem = 1;
+      }
+      else {
+        if ((attr->cb_mem == NULL) && (attr->cb_size == 0U) && (attr->stack_mem == NULL)) {
+          mem = 0;
+        }
+      }
+    }
+    else {
+      mem = 0;
+    }
+
+    if (mem == 1) {
+      #if (configSUPPORT_STATIC_ALLOCATION == 1)
+        hTask = xTaskCreateStatic ((TaskFunction_t)func, name, stack, argument, prio, (StackType_t  *)attr->stack_mem,
+                                                                                      (StaticTask_t *)attr->cb_mem);
+      #endif
+    }
+    else {
+      if (mem == 0) {
+        #if (configSUPPORT_DYNAMIC_ALLOCATION == 1)
+          if (xTaskCreate ((TaskFunction_t)func, name, (uint16_t)stack, argument, prio, &hTask) != pdPASS) {
+            hTask = NULL;
+          }
+        #endif
+      }
+    }
+  }
+
+  return ((osThreadId_t)hTask);
+}
+
+const char *osThreadGetName (osThreadId_t thread_id) {
+  TaskHandle_t hTask = (TaskHandle_t)thread_id;
+  const char *name;
+
+  if (IS_IRQ() || (hTask == NULL)) {
+    name = NULL;
+  } else {
+    name = pcTaskGetName (hTask);
+  }
+
+  return (name);
+}
+
+osThreadId_t osThreadGetId (void) {
+  osThreadId_t id;
+
+  id = (osThreadId_t)xTaskGetCurrentTaskHandle();
+
+  return (id);
+}
+
+osThreadState_t osThreadGetState (osThreadId_t thread_id) {
+  TaskHandle_t hTask = (TaskHandle_t)thread_id;
+  osThreadState_t state;
+
+  if (IS_IRQ() || (hTask == NULL)) {
+    state = osThreadError;
+  }
+  else {
+    switch (eTaskGetState (hTask)) {
+      case eRunning:   state = osThreadRunning;    break;
+      case eReady:     state = osThreadReady;      break;
+      case eBlocked:
+      case eSuspended: state = osThreadBlocked;    break;
+      case eDeleted:   state = osThreadTerminated; break;
+      case eInvalid:
+      default:         state = osThreadError;      break;
+    }
+  }
+
+  return (state);
+}
+
+uint32_t osThreadGetStackSpace (osThreadId_t thread_id) {
+  TaskHandle_t hTask = (TaskHandle_t)thread_id;
+  uint32_t sz;
+
+  if (IS_IRQ() || (hTask == NULL)) {
+    sz = 0U;
+  } else {
+    sz = (uint32_t)(uxTaskGetStackHighWaterMark(hTask) * sizeof(StackType_t));
+  }
+
+  return (sz);
+}
+
+osStatus_t osThreadSetPriority (osThreadId_t thread_id, osPriority_t priority) {
+  TaskHandle_t hTask = (TaskHandle_t)thread_id;
+  osStatus_t stat;
+
+  if (IS_IRQ()) {
+    stat = osErrorISR;
+  }
+  else if ((hTask == NULL) || (priority < osPriorityIdle) || (priority > osPriorityISR)) {
+    stat = osErrorParameter;
+  }
+  else {
+    stat = osOK;
+    vTaskPrioritySet (hTask, (UBaseType_t)priority);
+  }
+
+  return (stat);
+}
+
+osPriority_t osThreadGetPriority (osThreadId_t thread_id) {
+  TaskHandle_t hTask = (TaskHandle_t)thread_id;
+  osPriority_t prio;
+
+  if (IS_IRQ() || (hTask == NULL)) {
+    prio = osPriorityError;
+  } else {
+    prio = (osPriority_t)((int32_t)uxTaskPriorityGet (hTask));
+  }
+
+  return (prio);
+}
+
+osStatus_t osThreadYield (void) {
+  osStatus_t stat;
+
+  if (IS_IRQ()) {
+    stat = osErrorISR;
+  } else {
+    stat = osOK;
+    taskYIELD();
+  }
+
+  return (stat);
+}
+
+#if (configUSE_OS2_THREAD_SUSPEND_RESUME == 1)
+osStatus_t osThreadSuspend (osThreadId_t thread_id) {
+  TaskHandle_t hTask = (TaskHandle_t)thread_id;
+  osStatus_t stat;
+
+  if (IS_IRQ()) {
+    stat = osErrorISR;
+  }
+  else if (hTask == NULL) {
+    stat = osErrorParameter;
+  }
+  else {
+    stat = osOK;
+    vTaskSuspend (hTask);
+  }
+
+  return (stat);
+}
+
+osStatus_t osThreadResume (osThreadId_t thread_id) {
+  TaskHandle_t hTask = (TaskHandle_t)thread_id;
+  osStatus_t stat;
+
+  if (IS_IRQ()) {
+    stat = osErrorISR;
+  }
+  else if (hTask == NULL) {
+    stat = osErrorParameter;
+  }
+  else {
+    stat = osOK;
+    vTaskResume (hTask);
+  }
+
+  return (stat);
+}
+#endif /* (configUSE_OS2_THREAD_SUSPEND_RESUME == 1) */
+
+__NO_RETURN void osThreadExit (void) {
+#ifndef USE_FreeRTOS_HEAP_1
+  vTaskDelete (NULL);
+#endif
+  for (;;);
+}
+
+osStatus_t osThreadTerminate (osThreadId_t thread_id) {
+  TaskHandle_t hTask = (TaskHandle_t)thread_id;
+  osStatus_t stat;
+#ifndef USE_FreeRTOS_HEAP_1
+  eTaskState tstate;
+
+  if (IS_IRQ()) {
+    stat = osErrorISR;
+  }
+  else if (hTask == NULL) {
+    stat = osErrorParameter;
+  }
+  else {
+    tstate = eTaskGetState (hTask);
+
+    if (tstate != eDeleted) {
+      stat = osOK;
+      vTaskDelete (hTask);
+    } else {
+      stat = osErrorResource;
+    }
+  }
+#else
+  stat = osError;
+#endif
+
+  return (stat);
+}
+
+uint32_t osThreadGetCount (void) {
+  uint32_t count;
+
+  if (IS_IRQ()) {
+    count = 0U;
+  } else {
+    count = uxTaskGetNumberOfTasks();
+  }
+
+  return (count);
+}
+
+#if (configUSE_OS2_THREAD_ENUMERATE == 1)
+uint32_t osThreadEnumerate (osThreadId_t *thread_array, uint32_t array_items) {
+  uint32_t i, count;
+  TaskStatus_t *task;
+
+  if (IS_IRQ() || (thread_array == NULL) || (array_items == 0U)) {
+    count = 0U;
+  } else {
+    vTaskSuspendAll();
+
+    count = uxTaskGetNumberOfTasks();
+    task  = pvPortMalloc (count * sizeof(TaskStatus_t));
+
+    if (task != NULL) {
+      count = uxTaskGetSystemState (task, count, NULL);
+
+      for (i = 0U; (i < count) && (i < array_items); i++) {
+        thread_array[i] = (osThreadId_t)task[i].xHandle;
+      }
+      count = i;
+    }
+    (void)xTaskResumeAll();
+
+    vPortFree (task);
+  }
+
+  return (count);
+}
+#endif /* (configUSE_OS2_THREAD_ENUMERATE == 1) */
+
+#if (configUSE_OS2_THREAD_FLAGS == 1)
+uint32_t osThreadFlagsSet (osThreadId_t thread_id, uint32_t flags) {
+  TaskHandle_t hTask = (TaskHandle_t)thread_id;
+  uint32_t rflags;
+  BaseType_t yield;
+
+  if ((hTask == NULL) || ((flags & THREAD_FLAGS_INVALID_BITS) != 0U)) {
+    rflags = (uint32_t)osErrorParameter;
+  }
+  else {
+    rflags = (uint32_t)osError;
+
+    if (IS_IRQ()) {
+      yield = pdFALSE;
+
+      (void)xTaskNotifyFromISR (hTask, flags, eSetBits, &yield);
+      (void)xTaskNotifyAndQueryFromISR (hTask, 0, eNoAction, &rflags, NULL);
+
+      portYIELD_FROM_ISR (yield);
+    }
+    else {
+      (void)xTaskNotify (hTask, flags, eSetBits);
+      (void)xTaskNotifyAndQuery (hTask, 0, eNoAction, &rflags);
+    }
+  }
+  /* Return flags after setting */
+  return (rflags);
+}
+
+uint32_t osThreadFlagsClear (uint32_t flags) {
+  TaskHandle_t hTask;
+  uint32_t rflags, cflags;
+
+  if (IS_IRQ()) {
+    rflags = (uint32_t)osErrorISR;
+  }
+  else if ((flags & THREAD_FLAGS_INVALID_BITS) != 0U) {
+    rflags = (uint32_t)osErrorParameter;
+  }
+  else {
+    hTask = xTaskGetCurrentTaskHandle();
+
+    if (xTaskNotifyAndQuery (hTask, 0, eNoAction, &cflags) == pdPASS) {
+      rflags = cflags;
+      cflags &= ~flags;
+
+      if (xTaskNotify (hTask, cflags, eSetValueWithOverwrite) != pdPASS) {
+        rflags = (uint32_t)osError;
+      }
+    }
+    else {
+      rflags = (uint32_t)osError;
+    }
+  }
+
+  /* Return flags before clearing */
+  return (rflags);
+}
+
+uint32_t osThreadFlagsGet (void) {
+  TaskHandle_t hTask;
+  uint32_t rflags;
+
+  if (IS_IRQ()) {
+    rflags = (uint32_t)osErrorISR;
+  }
+  else {
+    hTask = xTaskGetCurrentTaskHandle();
+
+    if (xTaskNotifyAndQuery (hTask, 0, eNoAction, &rflags) != pdPASS) {
+      rflags = (uint32_t)osError;
+    }
+  }
+
+  return (rflags);
+}
+
+uint32_t osThreadFlagsWait (uint32_t flags, uint32_t options, uint32_t timeout) {
+  uint32_t rflags, nval;
+  uint32_t clear;
+  TickType_t t0, td, tout;
+  BaseType_t rval;
+
+  if (IS_IRQ()) {
+    rflags = (uint32_t)osErrorISR;
+  }
+  else if ((flags & THREAD_FLAGS_INVALID_BITS) != 0U) {
+    rflags = (uint32_t)osErrorParameter;
+  }
+  else {
+    if ((options & osFlagsNoClear) == osFlagsNoClear) {
+      clear = 0U;
+    } else {
+      clear = flags;
+    }
+
+    rflags = 0U;
+    tout   = timeout;
+
+    t0 = xTaskGetTickCount();
+    do {
+      rval = xTaskNotifyWait (0, clear, &nval, tout);
+
+      if (rval == pdPASS) {
+        rflags &= flags;
+        rflags |= nval;
+
+        if ((options & osFlagsWaitAll) == osFlagsWaitAll) {
+          if ((flags & rflags) == flags) {
+            break;
+          } else {
+            if (timeout == 0U) {
+              rflags = (uint32_t)osErrorResource;
+              break;
+            }
+          }
+        }
+        else {
+          if ((flags & rflags) != 0) {
+            break;
+          } else {
+            if (timeout == 0U) {
+              rflags = (uint32_t)osErrorResource;
+              break;
+            }
+          }
+        }
+
+        /* Update timeout */
+        td = xTaskGetTickCount() - t0;
+
+        if (td > tout) {
+          tout  = 0;
+        } else {
+          tout -= td;
+        }
+      }
+      else {
+        if (timeout == 0) {
+          rflags = (uint32_t)osErrorResource;
+        } else {
+          rflags = (uint32_t)osErrorTimeout;
+        }
+      }
+    }
+    while (rval != pdFAIL);
+  }
+
+  /* Return flags before clearing */
+  return (rflags);
+}
+#endif /* (configUSE_OS2_THREAD_FLAGS == 1) */
+
+osStatus_t osDelay (uint32_t ticks) {
+  osStatus_t stat;
+
+  if (IS_IRQ()) {
+    stat = osErrorISR;
+  }
+  else {
+    stat = osOK;
+
+    if (ticks != 0U) {
+      vTaskDelay(ticks);
+    }
+  }
+
+  return (stat);
+}
+
+osStatus_t osDelayUntil (uint32_t ticks) {
+  TickType_t tcnt, delay;
+  osStatus_t stat;
+
+  if (IS_IRQ()) {
+    stat = osErrorISR;
+  }
+  else {
+    stat = osOK;
+    tcnt = xTaskGetTickCount();
+
+    /* Determine remaining number of ticks to delay */
+    delay = (TickType_t)ticks - tcnt;
+
+    /* Check if target tick has not expired */
+    if((delay != 0U) && (0 == (delay >> (8 * sizeof(TickType_t) - 1)))) {
+      vTaskDelayUntil (&tcnt, delay);
+    }
+    else
+    {
+      /* No delay or already expired */
+      stat = osErrorParameter;
+    }
+  }
+
+  return (stat);
+}
+
+/*---------------------------------------------------------------------------*/
+#if (configUSE_OS2_TIMER == 1)
+
+static void TimerCallback (TimerHandle_t hTimer) {
+  TimerCallback_t *callb;
+
+  callb = (TimerCallback_t *)pvTimerGetTimerID (hTimer);
+
+  if (callb != NULL) {
+    callb->func (callb->arg);
+  }
+}
+
+osTimerId_t osTimerNew (osTimerFunc_t func, osTimerType_t type, void *argument, const osTimerAttr_t *attr) {
+  const char *name;
+  TimerHandle_t hTimer;
+  TimerCallback_t *callb;
+  UBaseType_t reload;
+  int32_t mem;
+
+  hTimer = NULL;
+
+  if (!IS_IRQ() && (func != NULL)) {
+    /* Allocate memory to store callback function and argument */
+    callb = pvPortMalloc (sizeof(TimerCallback_t));
+
+    if (callb != NULL) {
+      callb->func = func;
+      callb->arg  = argument;
+
+      if (type == osTimerOnce) {
+        reload = pdFALSE;
+      } else {
+        reload = pdTRUE;
+      }
+
+      mem  = -1;
+      name = NULL;
+
+      if (attr != NULL) {
+        if (attr->name != NULL) {
+          name = attr->name;
+        }
+
+        if ((attr->cb_mem != NULL) && (attr->cb_size >= sizeof(StaticTimer_t))) {
+          mem = 1;
+        }
+        else {
+          if ((attr->cb_mem == NULL) && (attr->cb_size == 0U)) {
+            mem = 0;
+          }
+        }
+      }
+      else {
+        mem = 0;
+      }
+
+      if (mem == 1) {
+        #if (configSUPPORT_STATIC_ALLOCATION == 1)
+          hTimer = xTimerCreateStatic (name, 1, reload, callb, TimerCallback, (StaticTimer_t *)attr->cb_mem);
+        #endif
+      }
+      else {
+        if (mem == 0) {
+          #if (configSUPPORT_DYNAMIC_ALLOCATION == 1)
+            hTimer = xTimerCreate (name, 1, reload, callb, TimerCallback);
+          #endif
+        }
+      }
+
+      if ((hTimer == NULL) && (callb != NULL)) {
+        vPortFree (callb);
+      }
+    }
+  }
+
+  return ((osTimerId_t)hTimer);
+}
+
+const char *osTimerGetName (osTimerId_t timer_id) {
+  TimerHandle_t hTimer = (TimerHandle_t)timer_id;
+  const char *p;
+
+  if (IS_IRQ() || (hTimer == NULL)) {
+    p = NULL;
+  } else {
+    p = pcTimerGetName (hTimer);
+  }
+
+  return (p);
+}
+
+osStatus_t osTimerStart (osTimerId_t timer_id, uint32_t ticks) {
+  TimerHandle_t hTimer = (TimerHandle_t)timer_id;
+  osStatus_t stat;
+
+  if (IS_IRQ()) {
+    stat = osErrorISR;
+  }
+  else if (hTimer == NULL) {
+    stat = osErrorParameter;
+  }
+  else {
+    if (xTimerChangePeriod (hTimer, ticks, 0) == pdPASS) {
+      stat = osOK;
+    } else {
+      stat = osErrorResource;
+    }
+  }
+
+  return (stat);
+}
+
+osStatus_t osTimerStop (osTimerId_t timer_id) {
+  TimerHandle_t hTimer = (TimerHandle_t)timer_id;
+  osStatus_t stat;
+
+  if (IS_IRQ()) {
+    stat = osErrorISR;
+  }
+  else if (hTimer == NULL) {
+    stat = osErrorParameter;
+  }
+  else {
+    if (xTimerIsTimerActive (hTimer) == pdFALSE) {
+      stat = osErrorResource;
+    }
+    else {
+      if (xTimerStop (hTimer, 0) == pdPASS) {
+        stat = osOK;
+      } else {
+        stat = osError;
+      }
+    }
+  }
+
+  return (stat);
+}
+
+uint32_t osTimerIsRunning (osTimerId_t timer_id) {
+  TimerHandle_t hTimer = (TimerHandle_t)timer_id;
+  uint32_t running;
+
+  if (IS_IRQ() || (hTimer == NULL)) {
+    running = 0U;
+  } else {
+    running = (uint32_t)xTimerIsTimerActive (hTimer);
+  }
+
+  return (running);
+}
+
+osStatus_t osTimerDelete (osTimerId_t timer_id) {
+  TimerHandle_t hTimer = (TimerHandle_t)timer_id;
+  osStatus_t stat;
+#ifndef USE_FreeRTOS_HEAP_1
+  TimerCallback_t *callb;
+
+  if (IS_IRQ()) {
+    stat = osErrorISR;
+  }
+  else if (hTimer == NULL) {
+    stat = osErrorParameter;
+  }
+  else {
+    callb = (TimerCallback_t *)pvTimerGetTimerID (hTimer);
+
+    if (xTimerDelete (hTimer, 0) == pdPASS) {
+      vPortFree (callb);
+      stat = osOK;
+    } else {
+      stat = osErrorResource;
+    }
+  }
+#else
+  stat = osError;
+#endif
+
+  return (stat);
+}
+#endif /* (configUSE_OS2_TIMER == 1) */
+
+/*---------------------------------------------------------------------------*/
+
+osEventFlagsId_t osEventFlagsNew (const osEventFlagsAttr_t *attr) {
+  EventGroupHandle_t hEventGroup;
+  int32_t mem;
+
+  hEventGroup = NULL;
+
+  if (!IS_IRQ()) {
+    mem = -1;
+
+    if (attr != NULL) {
+      if ((attr->cb_mem != NULL) && (attr->cb_size >= sizeof(StaticEventGroup_t))) {
+        mem = 1;
+      }
+      else {
+        if ((attr->cb_mem == NULL) && (attr->cb_size == 0U)) {
+          mem = 0;
+        }
+      }
+    }
+    else {
+      mem = 0;
+    }
+
+    if (mem == 1) {
+      #if (configSUPPORT_STATIC_ALLOCATION == 1)
+      hEventGroup = xEventGroupCreateStatic (attr->cb_mem);
+      #endif
+    }
+    else {
+      if (mem == 0) {
+        #if (configSUPPORT_DYNAMIC_ALLOCATION == 1)
+          hEventGroup = xEventGroupCreate();
+        #endif
+      }
+    }
+  }
+
+  return ((osEventFlagsId_t)hEventGroup);
+}
+
+uint32_t osEventFlagsSet (osEventFlagsId_t ef_id, uint32_t flags) {
+  EventGroupHandle_t hEventGroup = (EventGroupHandle_t)ef_id;
+  uint32_t rflags;
+  BaseType_t yield;
+
+  if ((hEventGroup == NULL) || ((flags & EVENT_FLAGS_INVALID_BITS) != 0U)) {
+    rflags = (uint32_t)osErrorParameter;
+  }
+  else if (IS_IRQ()) {
+  #if (configUSE_OS2_EVENTFLAGS_FROM_ISR == 0)
+    (void)yield;
+    /* Enable timers and xTimerPendFunctionCall function to support osEventFlagsSet from ISR */
+    rflags = (uint32_t)osErrorResource;
+  #else
+    yield = pdFALSE;
+
+    if (xEventGroupSetBitsFromISR (hEventGroup, (EventBits_t)flags, &yield) == pdFAIL) {
+      rflags = (uint32_t)osErrorResource;
+    } else {
+      rflags = flags;
+      portYIELD_FROM_ISR (yield);
+    }
+  #endif
+  }
+  else {
+    rflags = xEventGroupSetBits (hEventGroup, (EventBits_t)flags);
+  }
+
+  return (rflags);
+}
+
+uint32_t osEventFlagsClear (osEventFlagsId_t ef_id, uint32_t flags) {
+  EventGroupHandle_t hEventGroup = (EventGroupHandle_t)ef_id;
+  uint32_t rflags;
+
+  if ((hEventGroup == NULL) || ((flags & EVENT_FLAGS_INVALID_BITS) != 0U)) {
+    rflags = (uint32_t)osErrorParameter;
+  }
+  else if (IS_IRQ()) {
+  #if (configUSE_OS2_EVENTFLAGS_FROM_ISR == 0)
+    /* Enable timers and xTimerPendFunctionCall function to support osEventFlagsSet from ISR */
+    rflags = (uint32_t)osErrorResource;
+  #else
+    rflags = xEventGroupGetBitsFromISR (hEventGroup);
+
+    if (xEventGroupClearBitsFromISR (hEventGroup, (EventBits_t)flags) == pdFAIL) {
+      rflags = (uint32_t)osErrorResource;
+    }
+  #endif
+  }
+  else {
+    rflags = xEventGroupClearBits (hEventGroup, (EventBits_t)flags);
+  }
+
+  return (rflags);
+}
+
+uint32_t osEventFlagsGet (osEventFlagsId_t ef_id) {
+  EventGroupHandle_t hEventGroup = (EventGroupHandle_t)ef_id;
+  uint32_t rflags;
+
+  if (ef_id == NULL) {
+    rflags = 0U;
+  }
+  else if (IS_IRQ()) {
+    rflags = xEventGroupGetBitsFromISR (hEventGroup);
+  }
+  else {
+    rflags = xEventGroupGetBits (hEventGroup);
+  }
+
+  return (rflags);
+}
+
+uint32_t osEventFlagsWait (osEventFlagsId_t ef_id, uint32_t flags, uint32_t options, uint32_t timeout) {
+  EventGroupHandle_t hEventGroup = (EventGroupHandle_t)ef_id;
+  BaseType_t wait_all;
+  BaseType_t exit_clr;
+  uint32_t rflags;
+
+  if ((hEventGroup == NULL) || ((flags & EVENT_FLAGS_INVALID_BITS) != 0U)) {
+    rflags = (uint32_t)osErrorParameter;
+  }
+  else if (IS_IRQ()) {
+    rflags = (uint32_t)osErrorISR;
+  }
+  else {
+    if (options & osFlagsWaitAll) {
+      wait_all = pdTRUE;
+    } else {
+      wait_all = pdFAIL;
+    }
+
+    if (options & osFlagsNoClear) {
+      exit_clr = pdFAIL;
+    } else {
+      exit_clr = pdTRUE;
+    }
+
+    rflags = xEventGroupWaitBits (hEventGroup, (EventBits_t)flags, exit_clr, wait_all, (TickType_t)timeout);
+
+    if (options & osFlagsWaitAll) {
+      if ((flags & rflags) != flags) {
+        if (timeout > 0U) {
+          rflags = (uint32_t)osErrorTimeout;
+        } else {
+          rflags = (uint32_t)osErrorResource;
+        }
+      }
+    }
+    else {
+      if ((flags & rflags) == 0U) {
+        if (timeout > 0U) {
+          rflags = (uint32_t)osErrorTimeout;
+        } else {
+          rflags = (uint32_t)osErrorResource;
+        }
+      }
+    }
+  }
+
+  return (rflags);
+}
+
+osStatus_t osEventFlagsDelete (osEventFlagsId_t ef_id) {
+  EventGroupHandle_t hEventGroup = (EventGroupHandle_t)ef_id;
+  osStatus_t stat;
+
+#ifndef USE_FreeRTOS_HEAP_1
+  if (IS_IRQ()) {
+    stat = osErrorISR;
+  }
+  else if (hEventGroup == NULL) {
+    stat = osErrorParameter;
+  }
+  else {
+    stat = osOK;
+    vEventGroupDelete (hEventGroup);
+  }
+#else
+  stat = osError;
+#endif
+
+  return (stat);
+}
+
+/*---------------------------------------------------------------------------*/
+#if (configUSE_OS2_MUTEX == 1)
+
+osMutexId_t osMutexNew (const osMutexAttr_t *attr) {
+  SemaphoreHandle_t hMutex;
+  uint32_t type;
+  uint32_t rmtx;
+  int32_t  mem;
+  #if (configQUEUE_REGISTRY_SIZE > 0)
+  const char *name;
+  #endif
+
+  hMutex = NULL;
+
+  if (!IS_IRQ()) {
+    if (attr != NULL) {
+      type = attr->attr_bits;
+    } else {
+      type = 0U;
+    }
+
+    if ((type & osMutexRecursive) == osMutexRecursive) {
+      rmtx = 1U;
+    } else {
+      rmtx = 0U;
+    }
+
+    if ((type & osMutexRobust) != osMutexRobust) {
+      mem = -1;
+
+      if (attr != NULL) {
+        if ((attr->cb_mem != NULL) && (attr->cb_size >= sizeof(StaticSemaphore_t))) {
+          mem = 1;
+        }
+        else {
+          if ((attr->cb_mem == NULL) && (attr->cb_size == 0U)) {
+            mem = 0;
+          }
+        }
+      }
+      else {
+        mem = 0;
+      }
+
+      if (mem == 1) {
+        #if (configSUPPORT_STATIC_ALLOCATION == 1)
+          if (rmtx != 0U) {
+            #if (configUSE_RECURSIVE_MUTEXES == 1)
+            hMutex = xSemaphoreCreateRecursiveMutexStatic (attr->cb_mem);
+            #endif
+          }
+          else {
+            hMutex = xSemaphoreCreateMutexStatic (attr->cb_mem);
+          }
+        #endif
+      }
+      else {
+        if (mem == 0) {
+          #if (configSUPPORT_DYNAMIC_ALLOCATION == 1)
+            if (rmtx != 0U) {
+              #if (configUSE_RECURSIVE_MUTEXES == 1)
+              hMutex = xSemaphoreCreateRecursiveMutex ();
+              #endif
+            } else {
+              hMutex = xSemaphoreCreateMutex ();
+            }
+          #endif
+        }
+      }
+
+      #if (configQUEUE_REGISTRY_SIZE > 0)
+      if (hMutex != NULL) {
+        if (attr != NULL) {
+          name = attr->name;
+        } else {
+          name = NULL;
+        }
+        vQueueAddToRegistry (hMutex, name);
+      }
+      #endif
+
+      if ((hMutex != NULL) && (rmtx != 0U)) {
+        hMutex = (SemaphoreHandle_t)((uint32_t)hMutex | 1U);
+      }
+    }
+  }
+
+  return ((osMutexId_t)hMutex);
+}
+
+osStatus_t osMutexAcquire (osMutexId_t mutex_id, uint32_t timeout) {
+  SemaphoreHandle_t hMutex;
+  osStatus_t stat;
+  uint32_t rmtx;
+
+  hMutex = (SemaphoreHandle_t)((uint32_t)mutex_id & ~1U);
+
+  rmtx = (uint32_t)mutex_id & 1U;
+
+  stat = osOK;
+
+  if (IS_IRQ()) {
+    stat = osErrorISR;
+  }
+  else if (hMutex == NULL) {
+    stat = osErrorParameter;
+  }
+  else {
+    if (rmtx != 0U) {
+      #if (configUSE_RECURSIVE_MUTEXES == 1)
+      if (xSemaphoreTakeRecursive (hMutex, timeout) != pdPASS) {
+        if (timeout != 0U) {
+          stat = osErrorTimeout;
+        } else {
+          stat = osErrorResource;
+        }
+      }
+      #endif
+    }
+    else {
+      if (xSemaphoreTake (hMutex, timeout) != pdPASS) {
+        if (timeout != 0U) {
+          stat = osErrorTimeout;
+        } else {
+          stat = osErrorResource;
+        }
+      }
+    }
+  }
+
+  return (stat);
+}
+
+osStatus_t osMutexRelease (osMutexId_t mutex_id) {
+  SemaphoreHandle_t hMutex;
+  osStatus_t stat;
+  uint32_t rmtx;
+
+  hMutex = (SemaphoreHandle_t)((uint32_t)mutex_id & ~1U);
+
+  rmtx = (uint32_t)mutex_id & 1U;
+
+  stat = osOK;
+
+  if (IS_IRQ()) {
+    stat = osErrorISR;
+  }
+  else if (hMutex == NULL) {
+    stat = osErrorParameter;
+  }
+  else {
+    if (rmtx != 0U) {
+      #if (configUSE_RECURSIVE_MUTEXES == 1)
+      if (xSemaphoreGiveRecursive (hMutex) != pdPASS) {
+        stat = osErrorResource;
+      }
+      #endif
+    }
+    else {
+      if (xSemaphoreGive (hMutex) != pdPASS) {
+        stat = osErrorResource;
+      }
+    }
+  }
+
+  return (stat);
+}
+
+osThreadId_t osMutexGetOwner (osMutexId_t mutex_id) {
+  SemaphoreHandle_t hMutex;
+  osThreadId_t owner;
+
+  hMutex = (SemaphoreHandle_t)((uint32_t)mutex_id & ~1U);
+
+  if (IS_IRQ() || (hMutex == NULL)) {
+    owner = NULL;
+  } else {
+    owner = (osThreadId_t)xSemaphoreGetMutexHolder (hMutex);
+  }
+
+  return (owner);
+}
+
+osStatus_t osMutexDelete (osMutexId_t mutex_id) {
+  osStatus_t stat;
+#ifndef USE_FreeRTOS_HEAP_1
+  SemaphoreHandle_t hMutex;
+
+  hMutex = (SemaphoreHandle_t)((uint32_t)mutex_id & ~1U);
+
+  if (IS_IRQ()) {
+    stat = osErrorISR;
+  }
+  else if (hMutex == NULL) {
+    stat = osErrorParameter;
+  }
+  else {
+    #if (configQUEUE_REGISTRY_SIZE > 0)
+    vQueueUnregisterQueue (hMutex);
+    #endif
+    stat = osOK;
+    vSemaphoreDelete (hMutex);
+  }
+#else
+  stat = osError;
+#endif
+
+  return (stat);
+}
+#endif /* (configUSE_OS2_MUTEX == 1) */
+
+/*---------------------------------------------------------------------------*/
+
+osSemaphoreId_t osSemaphoreNew (uint32_t max_count, uint32_t initial_count, const osSemaphoreAttr_t *attr) {
+  SemaphoreHandle_t hSemaphore;
+  int32_t mem;
+  #if (configQUEUE_REGISTRY_SIZE > 0)
+  const char *name;
+  #endif
+
+  hSemaphore = NULL;
+
+  if (!IS_IRQ() && (max_count > 0U) && (initial_count <= max_count)) {
+    mem = -1;
+
+    if (attr != NULL) {
+      if ((attr->cb_mem != NULL) && (attr->cb_size >= sizeof(StaticSemaphore_t))) {
+        mem = 1;
+      }
+      else {
+        if ((attr->cb_mem == NULL) && (attr->cb_size == 0U)) {
+          mem = 0;
+        }
+      }
+    }
+    else {
+      mem = 0;
+    }
+
+    if (mem != -1) {
+      if (max_count == 1U) {
+        if (mem == 1) {
+          #if (configSUPPORT_STATIC_ALLOCATION == 1)
+            hSemaphore = xSemaphoreCreateBinaryStatic ((StaticSemaphore_t *)attr->cb_mem);
+          #endif
+        }
+        else {
+          #if (configSUPPORT_DYNAMIC_ALLOCATION == 1)
+            hSemaphore = xSemaphoreCreateBinary();
+          #endif
+        }
+
+        if ((hSemaphore != NULL) && (initial_count != 0U)) {
+          if (xSemaphoreGive (hSemaphore) != pdPASS) {
+            vSemaphoreDelete (hSemaphore);
+            hSemaphore = NULL;
+          }
+        }
+      }
+      else {
+        if (mem == 1) {
+          #if (configSUPPORT_STATIC_ALLOCATION == 1)
+            hSemaphore = xSemaphoreCreateCountingStatic (max_count, initial_count, (StaticSemaphore_t *)attr->cb_mem);
+          #endif
+        }
+        else {
+          #if (configSUPPORT_DYNAMIC_ALLOCATION == 1)
+            hSemaphore = xSemaphoreCreateCounting (max_count, initial_count);
+          #endif
+        }
+      }
+      
+      #if (configQUEUE_REGISTRY_SIZE > 0)
+      if (hSemaphore != NULL) {
+        if (attr != NULL) {
+          name = attr->name;
+        } else {
+          name = NULL;
+        }
+        vQueueAddToRegistry (hSemaphore, name);
+      }
+      #endif
+    }
+  }
+
+  return ((osSemaphoreId_t)hSemaphore);
+}
+
+osStatus_t osSemaphoreAcquire (osSemaphoreId_t semaphore_id, uint32_t timeout) {
+  SemaphoreHandle_t hSemaphore = (SemaphoreHandle_t)semaphore_id;
+  osStatus_t stat;
+  BaseType_t yield;
+
+  stat = osOK;
+
+  if (hSemaphore == NULL) {
+    stat = osErrorParameter;
+  }
+  else if (IS_IRQ()) {
+    if (timeout != 0U) {
+      stat = osErrorParameter;
+    }
+    else {
+      yield = pdFALSE;
+
+      if (xSemaphoreTakeFromISR (hSemaphore, &yield) != pdPASS) {
+        stat = osErrorResource;
+      } else {
+        portYIELD_FROM_ISR (yield);
+      }
+    }
+  }
+  else {
+    if (xSemaphoreTake (hSemaphore, (TickType_t)timeout) != pdPASS) {
+      if (timeout != 0U) {
+        stat = osErrorTimeout;
+      } else {
+        stat = osErrorResource;
+      }
+    }
+  }
+
+  return (stat);
+}
+
+osStatus_t osSemaphoreRelease (osSemaphoreId_t semaphore_id) {
+  SemaphoreHandle_t hSemaphore = (SemaphoreHandle_t)semaphore_id;
+  osStatus_t stat;
+  BaseType_t yield;
+
+  stat = osOK;
+
+  if (hSemaphore == NULL) {
+    stat = osErrorParameter;
+  }
+  else if (IS_IRQ()) {
+    yield = pdFALSE;
+
+    if (xSemaphoreGiveFromISR (hSemaphore, &yield) != pdTRUE) {
+      stat = osErrorResource;
+    } else {
+      portYIELD_FROM_ISR (yield);
+    }
+  }
+  else {
+    if (xSemaphoreGive (hSemaphore) != pdPASS) {
+      stat = osErrorResource;
+    }
+  }
+
+  return (stat);
+}
+
+uint32_t osSemaphoreGetCount (osSemaphoreId_t semaphore_id) {
+  SemaphoreHandle_t hSemaphore = (SemaphoreHandle_t)semaphore_id;
+  uint32_t count;
+
+  if (hSemaphore == NULL) {
+    count = 0U;
+  }
+  else if (IS_IRQ()) {
+    count = uxQueueMessagesWaitingFromISR (hSemaphore);
+  } else {
+    count = (uint32_t)uxSemaphoreGetCount (hSemaphore);
+  }
+
+  return (count);
+}
+
+osStatus_t osSemaphoreDelete (osSemaphoreId_t semaphore_id) {
+  SemaphoreHandle_t hSemaphore = (SemaphoreHandle_t)semaphore_id;
+  osStatus_t stat;
+
+#ifndef USE_FreeRTOS_HEAP_1
+  if (IS_IRQ()) {
+    stat = osErrorISR;
+  }
+  else if (hSemaphore == NULL) {
+    stat = osErrorParameter;
+  }
+  else {
+    #if (configQUEUE_REGISTRY_SIZE > 0)
+    vQueueUnregisterQueue (hSemaphore);
+    #endif
+
+    stat = osOK;
+    vSemaphoreDelete (hSemaphore);
+  }
+#else
+  stat = osError;
+#endif
+
+  return (stat);
+}
+
+/*---------------------------------------------------------------------------*/
+
+osMessageQueueId_t osMessageQueueNew (uint32_t msg_count, uint32_t msg_size, const osMessageQueueAttr_t *attr) {
+  QueueHandle_t hQueue;
+  int32_t mem;
+  #if (configQUEUE_REGISTRY_SIZE > 0)
+  const char *name;
+  #endif
+
+  hQueue = NULL;
+
+  if (!IS_IRQ() && (msg_count > 0U) && (msg_size > 0U)) {
+    mem = -1;
+
+    if (attr != NULL) {
+      if ((attr->cb_mem != NULL) && (attr->cb_size >= sizeof(StaticQueue_t)) &&
+          (attr->mq_mem != NULL) && (attr->mq_size >= (msg_count * msg_size))) {
+        mem = 1;
+      }
+      else {
+        if ((attr->cb_mem == NULL) && (attr->cb_size == 0U) &&
+            (attr->mq_mem == NULL) && (attr->mq_size == 0U)) {
+          mem = 0;
+        }
+      }
+    }
+    else {
+      mem = 0;
+    }
+
+    if (mem == 1) {
+      #if (configSUPPORT_STATIC_ALLOCATION == 1)
+        hQueue = xQueueCreateStatic (msg_count, msg_size, attr->mq_mem, attr->cb_mem);
+      #endif
+    }
+    else {
+      if (mem == 0) {
+        #if (configSUPPORT_DYNAMIC_ALLOCATION == 1)
+          hQueue = xQueueCreate (msg_count, msg_size);
+        #endif
+      }
+    }
+
+    #if (configQUEUE_REGISTRY_SIZE > 0)
+    if (hQueue != NULL) {
+      if (attr != NULL) {
+        name = attr->name;
+      } else {
+        name = NULL;
+      }
+      vQueueAddToRegistry (hQueue, name);
+    }
+    #endif
+
+  }
+
+  return ((osMessageQueueId_t)hQueue);
+}
+
+osStatus_t osMessageQueuePut (osMessageQueueId_t mq_id, const void *msg_ptr, uint8_t msg_prio, uint32_t timeout) {
+  QueueHandle_t hQueue = (QueueHandle_t)mq_id;
+  osStatus_t stat;
+  BaseType_t yield;
+
+  (void)msg_prio; /* Message priority is ignored */
+
+  stat = osOK;
+
+  if (IS_IRQ()) {
+    if ((hQueue == NULL) || (msg_ptr == NULL) || (timeout != 0U)) {
+      stat = osErrorParameter;
+    }
+    else {
+      yield = pdFALSE;
+
+      if (xQueueSendToBackFromISR (hQueue, msg_ptr, &yield) != pdTRUE) {
+        stat = osErrorResource;
+      } else {
+        portYIELD_FROM_ISR (yield);
+      }
+    }
+  }
+  else {
+    if ((hQueue == NULL) || (msg_ptr == NULL)) {
+      stat = osErrorParameter;
+    }
+    else {
+      if (xQueueSendToBack (hQueue, msg_ptr, (TickType_t)timeout) != pdPASS) {
+        if (timeout != 0U) {
+          stat = osErrorTimeout;
+        } else {
+          stat = osErrorResource;
+        }
+      }
+    }
+  }
+
+  return (stat);
+}
+
+osStatus_t osMessageQueueGet (osMessageQueueId_t mq_id, void *msg_ptr, uint8_t *msg_prio, uint32_t timeout) {
+  QueueHandle_t hQueue = (QueueHandle_t)mq_id;
+  osStatus_t stat;
+  BaseType_t yield;
+
+  (void)msg_prio; /* Message priority is ignored */
+
+  stat = osOK;
+
+  if (IS_IRQ()) {
+    if ((hQueue == NULL) || (msg_ptr == NULL) || (timeout != 0U)) {
+      stat = osErrorParameter;
+    }
+    else {
+      yield = pdFALSE;
+
+      if (xQueueReceiveFromISR (hQueue, msg_ptr, &yield) != pdPASS) {
+        stat = osErrorResource;
+      } else {
+        portYIELD_FROM_ISR (yield);
+      }
+    }
+  }
+  else {
+    if ((hQueue == NULL) || (msg_ptr == NULL)) {
+      stat = osErrorParameter;
+    }
+    else {
+      if (xQueueReceive (hQueue, msg_ptr, (TickType_t)timeout) != pdPASS) {
+        if (timeout != 0U) {
+          stat = osErrorTimeout;
+        } else {
+          stat = osErrorResource;
+        }
+      }
+    }
+  }
+
+  return (stat);
+}
+
+uint32_t osMessageQueueGetCapacity (osMessageQueueId_t mq_id) {
+  StaticQueue_t *mq = (StaticQueue_t *)mq_id;
+  uint32_t capacity;
+
+  if (mq == NULL) {
+    capacity = 0U;
+  } else {
+    /* capacity = pxQueue->uxLength */
+    capacity = mq->uxDummy4[1];
+  }
+
+  return (capacity);
+}
+
+uint32_t osMessageQueueGetMsgSize (osMessageQueueId_t mq_id) {
+  StaticQueue_t *mq = (StaticQueue_t *)mq_id;
+  uint32_t size;
+
+  if (mq == NULL) {
+    size = 0U;
+  } else {
+    /* size = pxQueue->uxItemSize */
+    size = mq->uxDummy4[2];
+  }
+
+  return (size);
+}
+
+uint32_t osMessageQueueGetCount (osMessageQueueId_t mq_id) {
+  QueueHandle_t hQueue = (QueueHandle_t)mq_id;
+  UBaseType_t count;
+
+  if (hQueue == NULL) {
+    count = 0U;
+  }
+  else if (IS_IRQ()) {
+    count = uxQueueMessagesWaitingFromISR (hQueue);
+  }
+  else {
+    count = uxQueueMessagesWaiting (hQueue);
+  }
+
+  return ((uint32_t)count);
+}
+
+uint32_t osMessageQueueGetSpace (osMessageQueueId_t mq_id) {
+  StaticQueue_t *mq = (StaticQueue_t *)mq_id;
+  uint32_t space;
+  uint32_t isrm;
+
+  if (mq == NULL) {
+    space = 0U;
+  }
+  else if (IS_IRQ()) {
+    isrm = taskENTER_CRITICAL_FROM_ISR();
+
+    /* space = pxQueue->uxLength - pxQueue->uxMessagesWaiting; */
+    space = mq->uxDummy4[1] - mq->uxDummy4[0];
+
+    taskEXIT_CRITICAL_FROM_ISR(isrm);
+  }
+  else {
+    space = (uint32_t)uxQueueSpacesAvailable ((QueueHandle_t)mq);
+  }
+
+  return (space);
+}
+
+osStatus_t osMessageQueueReset (osMessageQueueId_t mq_id) {
+  QueueHandle_t hQueue = (QueueHandle_t)mq_id;
+  osStatus_t stat;
+
+  if (IS_IRQ()) {
+    stat = osErrorISR;
+  }
+  else if (hQueue == NULL) {
+    stat = osErrorParameter;
+  }
+  else {
+    stat = osOK;
+    (void)xQueueReset (hQueue);
+  }
+
+  return (stat);
+}
+
+osStatus_t osMessageQueueDelete (osMessageQueueId_t mq_id) {
+  QueueHandle_t hQueue = (QueueHandle_t)mq_id;
+  osStatus_t stat;
+
+#ifndef USE_FreeRTOS_HEAP_1
+  if (IS_IRQ()) {
+    stat = osErrorISR;
+  }
+  else if (hQueue == NULL) {
+    stat = osErrorParameter;
+  }
+  else {
+    #if (configQUEUE_REGISTRY_SIZE > 0)
+    vQueueUnregisterQueue (hQueue);
+    #endif
+
+    stat = osOK;
+    vQueueDelete (hQueue);
+  }
+#else
+  stat = osError;
+#endif
+
+  return (stat);
+}
+
+/*---------------------------------------------------------------------------*/
+#ifdef FREERTOS_MPOOL_H_
+
+/* Static memory pool functions */
+static void  FreeBlock   (MemPool_t *mp, void *block);
+static void *AllocBlock  (MemPool_t *mp);
+static void *CreateBlock (MemPool_t *mp);
+
+osMemoryPoolId_t osMemoryPoolNew (uint32_t block_count, uint32_t block_size, const osMemoryPoolAttr_t *attr) {
+  MemPool_t *mp;
+  const char *name;
+  int32_t mem_cb, mem_mp;
+  uint32_t sz;
+
+  if (IS_IRQ()) {
+    mp = NULL;
+  }
+  else if ((block_count == 0U) || (block_size == 0U)) {
+    mp = NULL;
+  }
+  else {
+    mp = NULL;
+    sz = MEMPOOL_ARR_SIZE (block_count, block_size);
+
+    name = NULL;
+    mem_cb = -1;
+    mem_mp = -1;
+
+    if (attr != NULL) {
+      if (attr->name != NULL) {
+        name = attr->name;
+      }
+
+      if ((attr->cb_mem != NULL) && (attr->cb_size >= sizeof(MemPool_t))) {
+        /* Static control block is provided */
+        mem_cb = 1;
+      }
+      else if ((attr->cb_mem == NULL) && (attr->cb_size == 0U)) {
+        /* Allocate control block memory on heap */
+        mem_cb = 0;
+      }
+
+      if ((attr->mp_mem == NULL) && (attr->mp_size == 0U)) {
+        /* Allocate memory array on heap */
+          mem_mp = 0;
+      }
+      else {
+        if (attr->mp_mem != NULL) {
+          /* Check if array is 4-byte aligned */
+          if (((uint32_t)attr->mp_mem & 3U) == 0U) {
+            /* Check if array big enough */
+            if (attr->mp_size >= sz) {
+              /* Static memory pool array is provided */
+              mem_mp = 1;
+            }
+          }
+        }
+      }
+    }
+    else {
+      /* Attributes not provided, allocate memory on heap */
+      mem_cb = 0;
+      mem_mp = 0;
+    }
+
+    if (mem_cb == 0) {
+      mp = pvPortMalloc (sizeof(MemPool_t));
+    } else {
+      mp = attr->cb_mem;
+    }
+
+    if (mp != NULL) {
+      /* Create a semaphore (max count == initial count == block_count) */
+      #if (configSUPPORT_STATIC_ALLOCATION == 1)
+        mp->sem = xSemaphoreCreateCountingStatic (block_count, block_count, &mp->mem_sem);
+      #elif (configSUPPORT_DYNAMIC_ALLOCATION == 1)
+        mp->sem = xSemaphoreCreateCounting (block_count, block_count);
+      #else
+        mp->sem == NULL;
+      #endif
+
+      if (mp->sem != NULL) {
+        /* Setup memory array */
+        if (mem_mp == 0) {
+          mp->mem_arr = pvPortMalloc (sz);
+        } else {
+          mp->mem_arr = attr->mp_mem;
+        }
+      }
+    }
+
+    if ((mp != NULL) && (mp->mem_arr != NULL)) {
+      /* Memory pool can be created */
+      mp->head    = NULL;
+      mp->mem_sz  = sz;
+      mp->name    = name;
+      mp->bl_sz   = block_size;
+      mp->bl_cnt  = block_count;
+      mp->n       = 0U;
+
+      /* Set heap allocated memory flags */
+      mp->status = MPOOL_STATUS;
+
+      if (mem_cb == 0) {
+        /* Control block on heap */
+        mp->status |= 1U;
+      }
+      if (mem_mp == 0) {
+        /* Memory array on heap */
+        mp->status |= 2U;
+      }
+    }
+    else {
+      /* Memory pool cannot be created, release allocated resources */
+      if ((mem_cb == 0) && (mp != NULL)) {
+        /* Free control block memory */
+        vPortFree (mp);
+      }
+      mp = NULL;
+    }
+  }
+
+  return (mp);
+}
+
+const char *osMemoryPoolGetName (osMemoryPoolId_t mp_id) {
+  MemPool_t *mp = (osMemoryPoolId_t)mp_id;
+  const char *p;
+
+  if (IS_IRQ()) {
+    p = NULL;
+  }
+  else if (mp_id == NULL) {
+    p = NULL;
+  }
+  else {
+    p = mp->name;
+  }
+
+  return (p);
+}
+
+void *osMemoryPoolAlloc (osMemoryPoolId_t mp_id, uint32_t timeout) {
+  MemPool_t *mp;
+  void *block;
+  uint32_t isrm;
+
+  if (mp_id == NULL) {
+    /* Invalid input parameters */
+    block = NULL;
+  }
+  else {
+    block = NULL;
+
+    mp = (MemPool_t *)mp_id;
+
+    if ((mp->status & MPOOL_STATUS) == MPOOL_STATUS) {
+      if (IS_IRQ()) {
+        if (timeout == 0U) {
+          if (xSemaphoreTakeFromISR (mp->sem, NULL) == pdTRUE) {
+            if ((mp->status & MPOOL_STATUS) == MPOOL_STATUS) {
+              isrm  = taskENTER_CRITICAL_FROM_ISR();
+
+              /* Get a block from the free-list */
+              block = AllocBlock(mp);
+
+              if (block == NULL) {
+                /* List of free blocks is empty, 'create' new block */
+                block = CreateBlock(mp);
+              }
+
+              taskEXIT_CRITICAL_FROM_ISR(isrm);
+            }
+          }
+        }
+      }
+      else {
+        if (xSemaphoreTake (mp->sem, (TickType_t)timeout) == pdTRUE) {
+          if ((mp->status & MPOOL_STATUS) == MPOOL_STATUS) {
+            taskENTER_CRITICAL();
+
+            /* Get a block from the free-list */
+            block = AllocBlock(mp);
+
+            if (block == NULL) {
+              /* List of free blocks is empty, 'create' new block */
+              block = CreateBlock(mp);
+            }
+
+            taskEXIT_CRITICAL();
+          }
+        }
+      }
+    }
+  }
+
+  return (block);
+}
+
+osStatus_t osMemoryPoolFree (osMemoryPoolId_t mp_id, void *block) {
+  MemPool_t *mp;
+  osStatus_t stat;
+  uint32_t isrm;
+  BaseType_t yield;
+
+  if ((mp_id == NULL) || (block == NULL)) {
+    /* Invalid input parameters */
+    stat = osErrorParameter;
+  }
+  else {
+    mp = (MemPool_t *)mp_id;
+
+    if ((mp->status & MPOOL_STATUS) != MPOOL_STATUS) {
+      /* Invalid object status */
+      stat = osErrorResource;
+    }
+    else if ((block < (void *)&mp->mem_arr[0]) || (block > (void*)&mp->mem_arr[mp->mem_sz-1])) {
+      /* Block pointer outside of memory array area */
+      stat = osErrorParameter;
+    }
+    else {
+      stat = osOK;
+
+      if (IS_IRQ()) {
+        if (uxSemaphoreGetCountFromISR (mp->sem) == mp->bl_cnt) {
+          stat = osErrorResource;
+        }
+        else {
+          isrm = taskENTER_CRITICAL_FROM_ISR();
+
+          /* Add block to the list of free blocks */
+          FreeBlock(mp, block);
+
+          taskEXIT_CRITICAL_FROM_ISR(isrm);
+
+          yield = pdFALSE;
+          xSemaphoreGiveFromISR (mp->sem, &yield);
+          portYIELD_FROM_ISR (yield);
+        }
+      }
+      else {
+        if (uxSemaphoreGetCount (mp->sem) == mp->bl_cnt) {
+          stat = osErrorResource;
+        }
+        else {
+          taskENTER_CRITICAL();
+
+          /* Add block to the list of free blocks */
+          FreeBlock(mp, block);
+
+          taskEXIT_CRITICAL();
+
+          xSemaphoreGive (mp->sem);
+        }
+      }
+    }
+  }
+
+  return (stat);
+}
+
+uint32_t osMemoryPoolGetCapacity (osMemoryPoolId_t mp_id) {
+  MemPool_t *mp;
+  uint32_t  n;
+
+  if (mp_id == NULL) {
+    /* Invalid input parameters */
+    n = 0U;
+  }
+  else {
+    mp = (MemPool_t *)mp_id;
+
+    if ((mp->status & MPOOL_STATUS) != MPOOL_STATUS) {
+      /* Invalid object status */
+      n = 0U;
+    }
+    else {
+      n = mp->bl_cnt;
+    }
+  }
+
+  /* Return maximum number of memory blocks */
+  return (n);
+}
+
+uint32_t osMemoryPoolGetBlockSize (osMemoryPoolId_t mp_id) {
+  MemPool_t *mp;
+  uint32_t  sz;
+
+  if (mp_id == NULL) {
+    /* Invalid input parameters */
+    sz = 0U;
+  }
+  else {
+    mp = (MemPool_t *)mp_id;
+
+    if ((mp->status & MPOOL_STATUS) != MPOOL_STATUS) {
+      /* Invalid object status */
+      sz = 0U;
+    }
+    else {
+      sz = mp->bl_sz;
+    }
+  }
+
+  /* Return memory block size in bytes */
+  return (sz);
+}
+
+uint32_t osMemoryPoolGetCount (osMemoryPoolId_t mp_id) {
+  MemPool_t *mp;
+  uint32_t  n;
+
+  if (mp_id == NULL) {
+    /* Invalid input parameters */
+    n = 0U;
+  }
+  else {
+    mp = (MemPool_t *)mp_id;
+
+    if ((mp->status & MPOOL_STATUS) != MPOOL_STATUS) {
+      /* Invalid object status */
+      n = 0U;
+    }
+    else {
+      if (IS_IRQ()) {
+        n = uxSemaphoreGetCountFromISR (mp->sem);
+      } else {
+        n = uxSemaphoreGetCount        (mp->sem);
+      }
+
+      n = mp->bl_cnt - n;
+    }
+  }
+
+  /* Return number of memory blocks used */
+  return (n);
+}
+
+uint32_t osMemoryPoolGetSpace (osMemoryPoolId_t mp_id) {
+  MemPool_t *mp;
+  uint32_t  n;
+
+  if (mp_id == NULL) {
+    /* Invalid input parameters */
+    n = 0U;
+  }
+  else {
+    mp = (MemPool_t *)mp_id;
+
+    if ((mp->status & MPOOL_STATUS) != MPOOL_STATUS) {
+      /* Invalid object status */
+      n = 0U;
+    }
+    else {
+      if (IS_IRQ()) {
+        n = uxSemaphoreGetCountFromISR (mp->sem);
+      } else {
+        n = uxSemaphoreGetCount        (mp->sem);
+      }
+    }
+  }
+
+  /* Return number of memory blocks available */
+  return (n);
+}
+
+osStatus_t osMemoryPoolDelete (osMemoryPoolId_t mp_id) {
+  MemPool_t *mp;
+  osStatus_t stat;
+
+  if (mp_id == NULL) {
+    /* Invalid input parameters */
+    stat = osErrorParameter;
+  }
+  else if (IS_IRQ()) {
+    stat = osErrorISR;
+  }
+  else {
+    mp = (MemPool_t *)mp_id;
+
+    taskENTER_CRITICAL();
+
+    /* Invalidate control block status */
+    mp->status  = mp->status & 3U;
+
+    /* Wake-up tasks waiting for pool semaphore */
+    while (xSemaphoreGive (mp->sem) == pdTRUE);
+
+    mp->head    = NULL;
+    mp->bl_sz   = 0U;
+    mp->bl_cnt  = 0U;
+
+    if ((mp->status & 2U) != 0U) {
+      /* Memory pool array allocated on heap */
+      vPortFree (mp->mem_arr);
+    }
+    if ((mp->status & 1U) != 0U) {
+      /* Memory pool control block allocated on heap */
+      vPortFree (mp);
+    }
+
+    taskEXIT_CRITICAL();
+
+    stat = osOK;
+  }
+
+  return (stat);
+}
+
+/*
+  Create new block given according to the current block index.
+*/
+static void *CreateBlock (MemPool_t *mp) {
+  MemPoolBlock_t *p = NULL;
+
+  if (mp->n < mp->bl_cnt) {
+    /* Unallocated blocks exist, set pointer to new block */
+    p = (void *)(mp->mem_arr + (mp->bl_sz * mp->n));
+
+    /* Increment block index */
+    mp->n += 1U;
+  }
+
+  return (p);
+}
+
+/*
+  Allocate a block by reading the list of free blocks.
+*/
+static void *AllocBlock (MemPool_t *mp) {
+  MemPoolBlock_t *p = NULL;
+
+  if (mp->head != NULL) {
+    /* List of free block exists, get head block */
+    p = mp->head;
+
+    /* Head block is now next on the list */
+    mp->head = p->next;
+  }
+
+  return (p);
+}
+
+/*
+  Free block by putting it to the list of free blocks.
+*/
+static void FreeBlock (MemPool_t *mp, void *block) {
+  MemPoolBlock_t *p = block;
+
+  /* Store current head into block memory space */
+  p->next = mp->head;
+
+  /* Store current block as new head */
+  mp->head = p;
+}
+#endif /* FREERTOS_MPOOL_H_ */
+/*---------------------------------------------------------------------------*/
+
+/* Callback function prototypes */
+extern void vApplicationIdleHook (void);
+extern void vApplicationTickHook (void);
+extern void vApplicationMallocFailedHook (void);
+extern void vApplicationDaemonTaskStartupHook (void);
+extern void vApplicationStackOverflowHook (TaskHandle_t xTask, signed char *pcTaskName);
+
+/**
+  Dummy implementation of the callback function vApplicationIdleHook().
+*/
+#if (configUSE_IDLE_HOOK == 1)
+__WEAK void vApplicationIdleHook (void){}
+#endif
+
+/**
+  Dummy implementation of the callback function vApplicationTickHook().
+*/
+#if (configUSE_TICK_HOOK == 1)
+ __WEAK void vApplicationTickHook (void){}
+#endif
+
+/**
+  Dummy implementation of the callback function vApplicationMallocFailedHook().
+*/
+#if (configUSE_MALLOC_FAILED_HOOK == 1)
+__WEAK void vApplicationMallocFailedHook (void){}
+#endif
+
+/**
+  Dummy implementation of the callback function vApplicationDaemonTaskStartupHook().
+*/
+#if (configUSE_DAEMON_TASK_STARTUP_HOOK == 1)
+__WEAK void vApplicationDaemonTaskStartupHook (void){}
+#endif
+
+/**
+  Dummy implementation of the callback function vApplicationStackOverflowHook().
+*/
+#if (configCHECK_FOR_STACK_OVERFLOW > 0)
+__WEAK void vApplicationStackOverflowHook (TaskHandle_t xTask, signed char *pcTaskName) {
+  (void)xTask;
+  (void)pcTaskName;
+  configASSERT(0);
+}
+#endif
+
+/*---------------------------------------------------------------------------*/
+#if (configSUPPORT_STATIC_ALLOCATION == 1)
+/* External Idle and Timer task static memory allocation functions */
+extern void vApplicationGetIdleTaskMemory  (StaticTask_t **ppxIdleTaskTCBBuffer,  StackType_t **ppxIdleTaskStackBuffer,  uint32_t *pulIdleTaskStackSize);
+extern void vApplicationGetTimerTaskMemory (StaticTask_t **ppxTimerTaskTCBBuffer, StackType_t **ppxTimerTaskStackBuffer, uint32_t *pulTimerTaskStackSize);
+
+/*
+  vApplicationGetIdleTaskMemory gets called when configSUPPORT_STATIC_ALLOCATION
+  equals to 1 and is required for static memory allocation support.
+*/
+__WEAK void vApplicationGetIdleTaskMemory (StaticTask_t **ppxIdleTaskTCBBuffer, StackType_t **ppxIdleTaskStackBuffer, uint32_t *pulIdleTaskStackSize) {
+  /* Idle task control block and stack */
+  static StaticTask_t Idle_TCB;
+  static StackType_t  Idle_Stack[configMINIMAL_STACK_SIZE];
+
+  *ppxIdleTaskTCBBuffer   = &Idle_TCB;
+  *ppxIdleTaskStackBuffer = &Idle_Stack[0];
+  *pulIdleTaskStackSize   = (uint32_t)configMINIMAL_STACK_SIZE;
+}
+
+/*
+  vApplicationGetTimerTaskMemory gets called when configSUPPORT_STATIC_ALLOCATION
+  equals to 1 and is required for static memory allocation support.
+*/
+__WEAK void vApplicationGetTimerTaskMemory (StaticTask_t **ppxTimerTaskTCBBuffer, StackType_t **ppxTimerTaskStackBuffer, uint32_t *pulTimerTaskStackSize) {
+  /* Timer task control block and stack */
+  static StaticTask_t Timer_TCB;
+  static StackType_t  Timer_Stack[configTIMER_TASK_STACK_DEPTH];
+
+  *ppxTimerTaskTCBBuffer   = &Timer_TCB;
+  *ppxTimerTaskStackBuffer = &Timer_Stack[0];
+  *pulTimerTaskStackSize   = (uint32_t)configTIMER_TASK_STACK_DEPTH;
+}
+#endif
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.h b/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.h
new file mode 100644
index 0000000..0d3634d
--- /dev/null
+++ b/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.h
@@ -0,0 +1,734 @@
+/* --------------------------------------------------------------------------
+ * Portions Copyright © 2017 STMicroelectronics International N.V. All rights reserved.
+ * Portions Copyright (c) 2013-2017 ARM Limited. All rights reserved.
+ * --------------------------------------------------------------------------
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ *      Name:    cmsis_os2.h
+ *      Purpose: CMSIS RTOS2 wrapper for FreeRTOS
+ *
+ *---------------------------------------------------------------------------*/
+
+#ifndef CMSIS_OS2_H_
+#define CMSIS_OS2_H_
+
+#ifndef __NO_RETURN
+#if   defined(__CC_ARM)
+#define __NO_RETURN __declspec(noreturn)
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#define __NO_RETURN __attribute__((__noreturn__))
+#elif defined(__GNUC__)
+#define __NO_RETURN __attribute__((__noreturn__))
+#elif defined(__ICCARM__)
+#define __NO_RETURN __noreturn
+#else
+#define __NO_RETURN
+#endif
+#endif
+
+#include <stdint.h>
+#include <stddef.h>
+
+#ifdef  __cplusplus
+extern "C"
+{
+#endif
+
+
+//  ==== Enumerations, structures, defines ====
+
+/// Version information.
+typedef struct {
+  uint32_t                       api;   ///< API version (major.minor.rev: mmnnnrrrr dec).
+  uint32_t                    kernel;   ///< Kernel version (major.minor.rev: mmnnnrrrr dec).
+} osVersion_t;
+
+/// Kernel state.
+typedef enum {
+  osKernelInactive        =  0,         ///< Inactive.
+  osKernelReady           =  1,         ///< Ready.
+  osKernelRunning         =  2,         ///< Running.
+  osKernelLocked          =  3,         ///< Locked.
+  osKernelSuspended       =  4,         ///< Suspended.
+  osKernelError           = -1,         ///< Error.
+  osKernelReserved        = 0x7FFFFFFFU ///< Prevents enum down-size compiler optimization.
+} osKernelState_t;
+
+/// Thread state.
+typedef enum {
+  osThreadInactive        =  0,         ///< Inactive.
+  osThreadReady           =  1,         ///< Ready.
+  osThreadRunning         =  2,         ///< Running.
+  osThreadBlocked         =  3,         ///< Blocked.
+  osThreadTerminated      =  4,         ///< Terminated.
+  osThreadError           = -1,         ///< Error.
+  osThreadReserved        = 0x7FFFFFFF  ///< Prevents enum down-size compiler optimization.
+} osThreadState_t;
+
+/// Priority values.
+typedef enum {
+  osPriorityNone          =  0,         ///< No priority (not initialized).
+  osPriorityIdle          =  1,         ///< Reserved for Idle thread.
+  osPriorityLow           =  8,         ///< Priority: low
+  osPriorityLow1          =  8+1,       ///< Priority: low + 1
+  osPriorityLow2          =  8+2,       ///< Priority: low + 2
+  osPriorityLow3          =  8+3,       ///< Priority: low + 3
+  osPriorityLow4          =  8+4,       ///< Priority: low + 4
+  osPriorityLow5          =  8+5,       ///< Priority: low + 5
+  osPriorityLow6          =  8+6,       ///< Priority: low + 6
+  osPriorityLow7          =  8+7,       ///< Priority: low + 7
+  osPriorityBelowNormal   = 16,         ///< Priority: below normal
+  osPriorityBelowNormal1  = 16+1,       ///< Priority: below normal + 1
+  osPriorityBelowNormal2  = 16+2,       ///< Priority: below normal + 2
+  osPriorityBelowNormal3  = 16+3,       ///< Priority: below normal + 3
+  osPriorityBelowNormal4  = 16+4,       ///< Priority: below normal + 4
+  osPriorityBelowNormal5  = 16+5,       ///< Priority: below normal + 5
+  osPriorityBelowNormal6  = 16+6,       ///< Priority: below normal + 6
+  osPriorityBelowNormal7  = 16+7,       ///< Priority: below normal + 7
+  osPriorityNormal        = 24,         ///< Priority: normal
+  osPriorityNormal1       = 24+1,       ///< Priority: normal + 1
+  osPriorityNormal2       = 24+2,       ///< Priority: normal + 2
+  osPriorityNormal3       = 24+3,       ///< Priority: normal + 3
+  osPriorityNormal4       = 24+4,       ///< Priority: normal + 4
+  osPriorityNormal5       = 24+5,       ///< Priority: normal + 5
+  osPriorityNormal6       = 24+6,       ///< Priority: normal + 6
+  osPriorityNormal7       = 24+7,       ///< Priority: normal + 7
+  osPriorityAboveNormal   = 32,         ///< Priority: above normal
+  osPriorityAboveNormal1  = 32+1,       ///< Priority: above normal + 1
+  osPriorityAboveNormal2  = 32+2,       ///< Priority: above normal + 2
+  osPriorityAboveNormal3  = 32+3,       ///< Priority: above normal + 3
+  osPriorityAboveNormal4  = 32+4,       ///< Priority: above normal + 4
+  osPriorityAboveNormal5  = 32+5,       ///< Priority: above normal + 5
+  osPriorityAboveNormal6  = 32+6,       ///< Priority: above normal + 6
+  osPriorityAboveNormal7  = 32+7,       ///< Priority: above normal + 7
+  osPriorityHigh          = 40,         ///< Priority: high
+  osPriorityHigh1         = 40+1,       ///< Priority: high + 1
+  osPriorityHigh2         = 40+2,       ///< Priority: high + 2
+  osPriorityHigh3         = 40+3,       ///< Priority: high + 3
+  osPriorityHigh4         = 40+4,       ///< Priority: high + 4
+  osPriorityHigh5         = 40+5,       ///< Priority: high + 5
+  osPriorityHigh6         = 40+6,       ///< Priority: high + 6
+  osPriorityHigh7         = 40+7,       ///< Priority: high + 7
+  osPriorityRealtime      = 48,         ///< Priority: realtime
+  osPriorityRealtime1     = 48+1,       ///< Priority: realtime + 1
+  osPriorityRealtime2     = 48+2,       ///< Priority: realtime + 2
+  osPriorityRealtime3     = 48+3,       ///< Priority: realtime + 3
+  osPriorityRealtime4     = 48+4,       ///< Priority: realtime + 4
+  osPriorityRealtime5     = 48+5,       ///< Priority: realtime + 5
+  osPriorityRealtime6     = 48+6,       ///< Priority: realtime + 6
+  osPriorityRealtime7     = 48+7,       ///< Priority: realtime + 7
+  osPriorityISR           = 56,         ///< Reserved for ISR deferred thread.
+  osPriorityError         = -1,         ///< System cannot determine priority or illegal priority.
+  osPriorityReserved      = 0x7FFFFFFF  ///< Prevents enum down-size compiler optimization.
+} osPriority_t;
+
+/// Entry point of a thread.
+typedef void (*osThreadFunc_t) (void *argument);
+
+/// Timer callback function.
+typedef void (*osTimerFunc_t) (void *argument);
+
+/// Timer type.
+typedef enum {
+  osTimerOnce               = 0,          ///< One-shot timer.
+  osTimerPeriodic           = 1           ///< Repeating timer.
+} osTimerType_t;
+
+// Timeout value.
+#define osWaitForever         0xFFFFFFFFU ///< Wait forever timeout value.
+
+// Flags options (\ref osThreadFlagsWait and \ref osEventFlagsWait).
+#define osFlagsWaitAny        0x00000000U ///< Wait for any flag (default).
+#define osFlagsWaitAll        0x00000001U ///< Wait for all flags.
+#define osFlagsNoClear        0x00000002U ///< Do not clear flags which have been specified to wait for.
+
+// Flags errors (returned by osThreadFlagsXxxx and osEventFlagsXxxx).
+#define osFlagsError          0x80000000U ///< Error indicator.
+#define osFlagsErrorUnknown   0xFFFFFFFFU ///< osError (-1).
+#define osFlagsErrorTimeout   0xFFFFFFFEU ///< osErrorTimeout (-2).
+#define osFlagsErrorResource  0xFFFFFFFDU ///< osErrorResource (-3).
+#define osFlagsErrorParameter 0xFFFFFFFCU ///< osErrorParameter (-4).
+#define osFlagsErrorISR       0xFFFFFFFAU ///< osErrorISR (-6).
+
+// Thread attributes (attr_bits in \ref osThreadAttr_t).
+#define osThreadDetached      0x00000000U ///< Thread created in detached mode (default)
+#define osThreadJoinable      0x00000001U ///< Thread created in joinable mode
+
+// Mutex attributes (attr_bits in \ref osMutexAttr_t).
+#define osMutexRecursive      0x00000001U ///< Recursive mutex.
+#define osMutexPrioInherit    0x00000002U ///< Priority inherit protocol.
+#define osMutexRobust         0x00000008U ///< Robust mutex.
+
+/// Status code values returned by CMSIS-RTOS functions.
+typedef enum {
+  osOK                      =  0,         ///< Operation completed successfully.
+  osError                   = -1,         ///< Unspecified RTOS error: run-time error but no other error message fits.
+  osErrorTimeout            = -2,         ///< Operation not completed within the timeout period.
+  osErrorResource           = -3,         ///< Resource not available.
+  osErrorParameter          = -4,         ///< Parameter error.
+  osErrorNoMemory           = -5,         ///< System is out of memory: it was impossible to allocate or reserve memory for the operation.
+  osErrorISR                = -6,         ///< Not allowed in ISR context: the function cannot be called from interrupt service routines.
+  osStatusReserved          = 0x7FFFFFFF  ///< Prevents enum down-size compiler optimization.
+} osStatus_t;
+
+
+/// \details Thread ID identifies the thread.
+typedef void *osThreadId_t;
+
+/// \details Timer ID identifies the timer.
+typedef void *osTimerId_t;
+
+/// \details Event Flags ID identifies the event flags.
+typedef void *osEventFlagsId_t;
+
+/// \details Mutex ID identifies the mutex.
+typedef void *osMutexId_t;
+
+/// \details Semaphore ID identifies the semaphore.
+typedef void *osSemaphoreId_t;
+
+/// \details Memory Pool ID identifies the memory pool.
+typedef void *osMemoryPoolId_t;
+
+/// \details Message Queue ID identifies the message queue.
+typedef void *osMessageQueueId_t;
+
+
+#ifndef TZ_MODULEID_T
+#define TZ_MODULEID_T
+/// \details Data type that identifies secure software modules called by a process.
+typedef uint32_t TZ_ModuleId_t;
+#endif
+
+
+/// Attributes structure for thread.
+typedef struct {
+  const char                   *name;   ///< name of the thread
+  uint32_t                 attr_bits;   ///< attribute bits
+  void                      *cb_mem;    ///< memory for control block
+  uint32_t                   cb_size;   ///< size of provided memory for control block
+  void                   *stack_mem;    ///< memory for stack
+  uint32_t                stack_size;   ///< size of stack
+  osPriority_t              priority;   ///< initial thread priority (default: osPriorityNormal)
+  TZ_ModuleId_t            tz_module;   ///< TrustZone module identifier
+  uint32_t                  reserved;   ///< reserved (must be 0)
+} osThreadAttr_t;
+
+/// Attributes structure for timer.
+typedef struct {
+  const char                   *name;   ///< name of the timer
+  uint32_t                 attr_bits;   ///< attribute bits
+  void                      *cb_mem;    ///< memory for control block
+  uint32_t                   cb_size;   ///< size of provided memory for control block
+} osTimerAttr_t;
+
+/// Attributes structure for event flags.
+typedef struct {
+  const char                   *name;   ///< name of the event flags
+  uint32_t                 attr_bits;   ///< attribute bits
+  void                      *cb_mem;    ///< memory for control block
+  uint32_t                   cb_size;   ///< size of provided memory for control block
+} osEventFlagsAttr_t;
+
+/// Attributes structure for mutex.
+typedef struct {
+  const char                   *name;   ///< name of the mutex
+  uint32_t                 attr_bits;   ///< attribute bits
+  void                      *cb_mem;    ///< memory for control block
+  uint32_t                   cb_size;   ///< size of provided memory for control block
+} osMutexAttr_t;
+
+/// Attributes structure for semaphore.
+typedef struct {
+  const char                   *name;   ///< name of the semaphore
+  uint32_t                 attr_bits;   ///< attribute bits
+  void                      *cb_mem;    ///< memory for control block
+  uint32_t                   cb_size;   ///< size of provided memory for control block
+} osSemaphoreAttr_t;
+
+/// Attributes structure for memory pool.
+typedef struct {
+  const char                   *name;   ///< name of the memory pool
+  uint32_t                 attr_bits;   ///< attribute bits
+  void                      *cb_mem;    ///< memory for control block
+  uint32_t                   cb_size;   ///< size of provided memory for control block
+  void                      *mp_mem;    ///< memory for data storage
+  uint32_t                   mp_size;   ///< size of provided memory for data storage
+} osMemoryPoolAttr_t;
+
+/// Attributes structure for message queue.
+typedef struct {
+  const char                   *name;   ///< name of the message queue
+  uint32_t                 attr_bits;   ///< attribute bits
+  void                      *cb_mem;    ///< memory for control block
+  uint32_t                   cb_size;   ///< size of provided memory for control block
+  void                      *mq_mem;    ///< memory for data storage
+  uint32_t                   mq_size;   ///< size of provided memory for data storage
+} osMessageQueueAttr_t;
+
+
+//  ==== Kernel Management Functions ====
+
+/// Initialize the RTOS Kernel.
+/// \return status code that indicates the execution status of the function.
+osStatus_t osKernelInitialize (void);
+
+///  Get RTOS Kernel Information.
+/// \param[out]    version       pointer to buffer for retrieving version information.
+/// \param[out]    id_buf        pointer to buffer for retrieving kernel identification string.
+/// \param[in]     id_size       size of buffer for kernel identification string.
+/// \return status code that indicates the execution status of the function.
+osStatus_t osKernelGetInfo (osVersion_t *version, char *id_buf, uint32_t id_size);
+
+/// Get the current RTOS Kernel state.
+/// \return current RTOS Kernel state.
+osKernelState_t osKernelGetState (void);
+
+/// Start the RTOS Kernel scheduler.
+/// \return status code that indicates the execution status of the function.
+osStatus_t osKernelStart (void);
+
+/// Lock the RTOS Kernel scheduler.
+/// \return previous lock state (1 - locked, 0 - not locked, error code if negative).
+int32_t osKernelLock (void);
+
+/// Unlock the RTOS Kernel scheduler.
+/// \return previous lock state (1 - locked, 0 - not locked, error code if negative).
+int32_t osKernelUnlock (void);
+
+/// Restore the RTOS Kernel scheduler lock state.
+/// \param[in]     lock          lock state obtained by \ref osKernelLock or \ref osKernelUnlock.
+/// \return new lock state (1 - locked, 0 - not locked, error code if negative).
+int32_t osKernelRestoreLock (int32_t lock);
+
+/// Suspend the RTOS Kernel scheduler.
+/// \return time in ticks, for how long the system can sleep or power-down.
+uint32_t osKernelSuspend (void);
+
+/// Resume the RTOS Kernel scheduler.
+/// \param[in]     sleep_ticks   time in ticks for how long the system was in sleep or power-down mode.
+void osKernelResume (uint32_t sleep_ticks);
+
+/// Get the RTOS kernel tick count.
+/// \return RTOS kernel current tick count.
+uint32_t osKernelGetTickCount (void);
+
+/// Get the RTOS kernel tick frequency.
+/// \return frequency of the kernel tick in hertz, i.e. kernel ticks per second.
+uint32_t osKernelGetTickFreq (void);
+
+/// Get the RTOS kernel system timer count.
+/// \return RTOS kernel current system timer count as 32-bit value.
+uint32_t osKernelGetSysTimerCount (void);
+
+/// Get the RTOS kernel system timer frequency.
+/// \return frequency of the system timer in hertz, i.e. timer ticks per second.
+uint32_t osKernelGetSysTimerFreq (void);
+
+
+//  ==== Thread Management Functions ====
+
+/// Create a thread and add it to Active Threads.
+/// \param[in]     func          thread function.
+/// \param[in]     argument      pointer that is passed to the thread function as start argument.
+/// \param[in]     attr          thread attributes; NULL: default values.
+/// \return thread ID for reference by other functions or NULL in case of error.
+osThreadId_t osThreadNew (osThreadFunc_t func, void *argument, const osThreadAttr_t *attr);
+
+/// Get name of a thread.
+/// \param[in]     thread_id     thread ID obtained by \ref osThreadNew or \ref osThreadGetId.
+/// \return name as NULL terminated string.
+const char *osThreadGetName (osThreadId_t thread_id);
+
+/// Return the thread ID of the current running thread.
+/// \return thread ID for reference by other functions or NULL in case of error.
+osThreadId_t osThreadGetId (void);
+
+/// Get current thread state of a thread.
+/// \param[in]     thread_id     thread ID obtained by \ref osThreadNew or \ref osThreadGetId.
+/// \return current thread state of the specified thread.
+osThreadState_t osThreadGetState (osThreadId_t thread_id);
+
+/// Get stack size of a thread.
+/// \param[in]     thread_id     thread ID obtained by \ref osThreadNew or \ref osThreadGetId.
+/// \return stack size in bytes.
+uint32_t osThreadGetStackSize (osThreadId_t thread_id);
+
+/// Get available stack space of a thread based on stack watermark recording during execution.
+/// \param[in]     thread_id     thread ID obtained by \ref osThreadNew or \ref osThreadGetId.
+/// \return remaining stack space in bytes.
+uint32_t osThreadGetStackSpace (osThreadId_t thread_id);
+
+/// Change priority of a thread.
+/// \param[in]     thread_id     thread ID obtained by \ref osThreadNew or \ref osThreadGetId.
+/// \param[in]     priority      new priority value for the thread function.
+/// \return status code that indicates the execution status of the function.
+osStatus_t osThreadSetPriority (osThreadId_t thread_id, osPriority_t priority);
+
+/// Get current priority of a thread.
+/// \param[in]     thread_id     thread ID obtained by \ref osThreadNew or \ref osThreadGetId.
+/// \return current priority value of the specified thread.
+osPriority_t osThreadGetPriority (osThreadId_t thread_id);
+
+/// Pass control to next thread that is in state \b READY.
+/// \return status code that indicates the execution status of the function.
+osStatus_t osThreadYield (void);
+
+/// Suspend execution of a thread.
+/// \param[in]     thread_id     thread ID obtained by \ref osThreadNew or \ref osThreadGetId.
+/// \return status code that indicates the execution status of the function.
+osStatus_t osThreadSuspend (osThreadId_t thread_id);
+
+/// Resume execution of a thread.
+/// \param[in]     thread_id     thread ID obtained by \ref osThreadNew or \ref osThreadGetId.
+/// \return status code that indicates the execution status of the function.
+osStatus_t osThreadResume (osThreadId_t thread_id);
+
+/// Detach a thread (thread storage can be reclaimed when thread terminates).
+/// \param[in]     thread_id     thread ID obtained by \ref osThreadNew or \ref osThreadGetId.
+/// \return status code that indicates the execution status of the function.
+osStatus_t osThreadDetach (osThreadId_t thread_id);
+
+/// Wait for specified thread to terminate.
+/// \param[in]     thread_id     thread ID obtained by \ref osThreadNew or \ref osThreadGetId.
+/// \return status code that indicates the execution status of the function.
+osStatus_t osThreadJoin (osThreadId_t thread_id);
+
+/// Terminate execution of current running thread.
+__NO_RETURN void osThreadExit (void);
+
+/// Terminate execution of a thread.
+/// \param[in]     thread_id     thread ID obtained by \ref osThreadNew or \ref osThreadGetId.
+/// \return status code that indicates the execution status of the function.
+osStatus_t osThreadTerminate (osThreadId_t thread_id);
+
+/// Get number of active threads.
+/// \return number of active threads.
+uint32_t osThreadGetCount (void);
+
+/// Enumerate active threads.
+/// \param[out]    thread_array  pointer to array for retrieving thread IDs.
+/// \param[in]     array_items   maximum number of items in array for retrieving thread IDs.
+/// \return number of enumerated threads.
+uint32_t osThreadEnumerate (osThreadId_t *thread_array, uint32_t array_items);
+
+
+//  ==== Thread Flags Functions ====
+
+/// Set the specified Thread Flags of a thread.
+/// \param[in]     thread_id     thread ID obtained by \ref osThreadNew or \ref osThreadGetId.
+/// \param[in]     flags         specifies the flags of the thread that shall be set.
+/// \return thread flags after setting or error code if highest bit set.
+uint32_t osThreadFlagsSet (osThreadId_t thread_id, uint32_t flags);
+
+/// Clear the specified Thread Flags of current running thread.
+/// \param[in]     flags         specifies the flags of the thread that shall be cleared.
+/// \return thread flags before clearing or error code if highest bit set.
+uint32_t osThreadFlagsClear (uint32_t flags);
+
+/// Get the current Thread Flags of current running thread.
+/// \return current thread flags.
+uint32_t osThreadFlagsGet (void);
+
+/// Wait for one or more Thread Flags of the current running thread to become signaled.
+/// \param[in]     flags         specifies the flags to wait for.
+/// \param[in]     options       specifies flags options (osFlagsXxxx).
+/// \param[in]     timeout       \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.
+/// \return thread flags before clearing or error code if highest bit set.
+uint32_t osThreadFlagsWait (uint32_t flags, uint32_t options, uint32_t timeout);
+
+
+//  ==== Generic Wait Functions ====
+
+/// Wait for Timeout (Time Delay).
+/// \param[in]     ticks         \ref CMSIS_RTOS_TimeOutValue "time ticks" value
+/// \return status code that indicates the execution status of the function.
+osStatus_t osDelay (uint32_t ticks);
+
+/// Wait until specified time.
+/// \param[in]     ticks         absolute time in ticks
+/// \return status code that indicates the execution status of the function.
+osStatus_t osDelayUntil (uint32_t ticks);
+
+
+//  ==== Timer Management Functions ====
+
+/// Create and Initialize a timer.
+/// \param[in]     func          function pointer to callback function.
+/// \param[in]     type          \ref osTimerOnce for one-shot or \ref osTimerPeriodic for periodic behavior.
+/// \param[in]     argument      argument to the timer callback function.
+/// \param[in]     attr          timer attributes; NULL: default values.
+/// \return timer ID for reference by other functions or NULL in case of error.
+osTimerId_t osTimerNew (osTimerFunc_t func, osTimerType_t type, void *argument, const osTimerAttr_t *attr);
+
+/// Get name of a timer.
+/// \param[in]     timer_id      timer ID obtained by \ref osTimerNew.
+/// \return name as NULL terminated string.
+const char *osTimerGetName (osTimerId_t timer_id);
+
+/// Start or restart a timer.
+/// \param[in]     timer_id      timer ID obtained by \ref osTimerNew.
+/// \param[in]     ticks         \ref CMSIS_RTOS_TimeOutValue "time ticks" value of the timer.
+/// \return status code that indicates the execution status of the function.
+osStatus_t osTimerStart (osTimerId_t timer_id, uint32_t ticks);
+
+/// Stop a timer.
+/// \param[in]     timer_id      timer ID obtained by \ref osTimerNew.
+/// \return status code that indicates the execution status of the function.
+osStatus_t osTimerStop (osTimerId_t timer_id);
+
+/// Check if a timer is running.
+/// \param[in]     timer_id      timer ID obtained by \ref osTimerNew.
+/// \return 0 not running, 1 running.
+uint32_t osTimerIsRunning (osTimerId_t timer_id);
+
+/// Delete a timer.
+/// \param[in]     timer_id      timer ID obtained by \ref osTimerNew.
+/// \return status code that indicates the execution status of the function.
+osStatus_t osTimerDelete (osTimerId_t timer_id);
+
+
+//  ==== Event Flags Management Functions ====
+
+/// Create and Initialize an Event Flags object.
+/// \param[in]     attr          event flags attributes; NULL: default values.
+/// \return event flags ID for reference by other functions or NULL in case of error.
+osEventFlagsId_t osEventFlagsNew (const osEventFlagsAttr_t *attr);
+
+/// Get name of an Event Flags object.
+/// \param[in]     ef_id         event flags ID obtained by \ref osEventFlagsNew.
+/// \return name as NULL terminated string.
+const char *osEventFlagsGetName (osEventFlagsId_t ef_id);
+
+/// Set the specified Event Flags.
+/// \param[in]     ef_id         event flags ID obtained by \ref osEventFlagsNew.
+/// \param[in]     flags         specifies the flags that shall be set.
+/// \return event flags after setting or error code if highest bit set.
+uint32_t osEventFlagsSet (osEventFlagsId_t ef_id, uint32_t flags);
+
+/// Clear the specified Event Flags.
+/// \param[in]     ef_id         event flags ID obtained by \ref osEventFlagsNew.
+/// \param[in]     flags         specifies the flags that shall be cleared.
+/// \return event flags before clearing or error code if highest bit set.
+uint32_t osEventFlagsClear (osEventFlagsId_t ef_id, uint32_t flags);
+
+/// Get the current Event Flags.
+/// \param[in]     ef_id         event flags ID obtained by \ref osEventFlagsNew.
+/// \return current event flags.
+uint32_t osEventFlagsGet (osEventFlagsId_t ef_id);
+
+/// Wait for one or more Event Flags to become signaled.
+/// \param[in]     ef_id         event flags ID obtained by \ref osEventFlagsNew.
+/// \param[in]     flags         specifies the flags to wait for.
+/// \param[in]     options       specifies flags options (osFlagsXxxx).
+/// \param[in]     timeout       \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.
+/// \return event flags before clearing or error code if highest bit set.
+uint32_t osEventFlagsWait (osEventFlagsId_t ef_id, uint32_t flags, uint32_t options, uint32_t timeout);
+
+/// Delete an Event Flags object.
+/// \param[in]     ef_id         event flags ID obtained by \ref osEventFlagsNew.
+/// \return status code that indicates the execution status of the function.
+osStatus_t osEventFlagsDelete (osEventFlagsId_t ef_id);
+
+
+//  ==== Mutex Management Functions ====
+
+/// Create and Initialize a Mutex object.
+/// \param[in]     attr          mutex attributes; NULL: default values.
+/// \return mutex ID for reference by other functions or NULL in case of error.
+osMutexId_t osMutexNew (const osMutexAttr_t *attr);
+
+/// Get name of a Mutex object.
+/// \param[in]     mutex_id      mutex ID obtained by \ref osMutexNew.
+/// \return name as NULL terminated string.
+const char *osMutexGetName (osMutexId_t mutex_id);
+
+/// Acquire a Mutex or timeout if it is locked.
+/// \param[in]     mutex_id      mutex ID obtained by \ref osMutexNew.
+/// \param[in]     timeout       \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.
+/// \return status code that indicates the execution status of the function.
+osStatus_t osMutexAcquire (osMutexId_t mutex_id, uint32_t timeout);
+
+/// Release a Mutex that was acquired by \ref osMutexAcquire.
+/// \param[in]     mutex_id      mutex ID obtained by \ref osMutexNew.
+/// \return status code that indicates the execution status of the function.
+osStatus_t osMutexRelease (osMutexId_t mutex_id);
+
+/// Get Thread which owns a Mutex object.
+/// \param[in]     mutex_id      mutex ID obtained by \ref osMutexNew.
+/// \return thread ID of owner thread or NULL when mutex was not acquired.
+osThreadId_t osMutexGetOwner (osMutexId_t mutex_id);
+
+/// Delete a Mutex object.
+/// \param[in]     mutex_id      mutex ID obtained by \ref osMutexNew.
+/// \return status code that indicates the execution status of the function.
+osStatus_t osMutexDelete (osMutexId_t mutex_id);
+
+
+//  ==== Semaphore Management Functions ====
+
+/// Create and Initialize a Semaphore object.
+/// \param[in]     max_count     maximum number of available tokens.
+/// \param[in]     initial_count initial number of available tokens.
+/// \param[in]     attr          semaphore attributes; NULL: default values.
+/// \return semaphore ID for reference by other functions or NULL in case of error.
+osSemaphoreId_t osSemaphoreNew (uint32_t max_count, uint32_t initial_count, const osSemaphoreAttr_t *attr);
+
+/// Get name of a Semaphore object.
+/// \param[in]     semaphore_id  semaphore ID obtained by \ref osSemaphoreNew.
+/// \return name as NULL terminated string.
+const char *osSemaphoreGetName (osSemaphoreId_t semaphore_id);
+
+/// Acquire a Semaphore token or timeout if no tokens are available.
+/// \param[in]     semaphore_id  semaphore ID obtained by \ref osSemaphoreNew.
+/// \param[in]     timeout       \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.
+/// \return status code that indicates the execution status of the function.
+osStatus_t osSemaphoreAcquire (osSemaphoreId_t semaphore_id, uint32_t timeout);
+
+/// Release a Semaphore token up to the initial maximum count.
+/// \param[in]     semaphore_id  semaphore ID obtained by \ref osSemaphoreNew.
+/// \return status code that indicates the execution status of the function.
+osStatus_t osSemaphoreRelease (osSemaphoreId_t semaphore_id);
+
+/// Get current Semaphore token count.
+/// \param[in]     semaphore_id  semaphore ID obtained by \ref osSemaphoreNew.
+/// \return number of tokens available.
+uint32_t osSemaphoreGetCount (osSemaphoreId_t semaphore_id);
+
+/// Delete a Semaphore object.
+/// \param[in]     semaphore_id  semaphore ID obtained by \ref osSemaphoreNew.
+/// \return status code that indicates the execution status of the function.
+osStatus_t osSemaphoreDelete (osSemaphoreId_t semaphore_id);
+
+
+//  ==== Memory Pool Management Functions ====
+
+/// Create and Initialize a Memory Pool object.
+/// \param[in]     block_count   maximum number of memory blocks in memory pool.
+/// \param[in]     block_size    memory block size in bytes.
+/// \param[in]     attr          memory pool attributes; NULL: default values.
+/// \return memory pool ID for reference by other functions or NULL in case of error.
+osMemoryPoolId_t osMemoryPoolNew (uint32_t block_count, uint32_t block_size, const osMemoryPoolAttr_t *attr);
+
+/// Get name of a Memory Pool object.
+/// \param[in]     mp_id         memory pool ID obtained by \ref osMemoryPoolNew.
+/// \return name as NULL terminated string.
+const char *osMemoryPoolGetName (osMemoryPoolId_t mp_id);
+
+/// Allocate a memory block from a Memory Pool.
+/// \param[in]     mp_id         memory pool ID obtained by \ref osMemoryPoolNew.
+/// \param[in]     timeout       \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.
+/// \return address of the allocated memory block or NULL in case of no memory is available.
+void *osMemoryPoolAlloc (osMemoryPoolId_t mp_id, uint32_t timeout);
+
+/// Return an allocated memory block back to a Memory Pool.
+/// \param[in]     mp_id         memory pool ID obtained by \ref osMemoryPoolNew.
+/// \param[in]     block         address of the allocated memory block to be returned to the memory pool.
+/// \return status code that indicates the execution status of the function.
+osStatus_t osMemoryPoolFree (osMemoryPoolId_t mp_id, void *block);
+
+/// Get maximum number of memory blocks in a Memory Pool.
+/// \param[in]     mp_id         memory pool ID obtained by \ref osMemoryPoolNew.
+/// \return maximum number of memory blocks.
+uint32_t osMemoryPoolGetCapacity (osMemoryPoolId_t mp_id);
+
+/// Get memory block size in a Memory Pool.
+/// \param[in]     mp_id         memory pool ID obtained by \ref osMemoryPoolNew.
+/// \return memory block size in bytes.
+uint32_t osMemoryPoolGetBlockSize (osMemoryPoolId_t mp_id);
+
+/// Get number of memory blocks used in a Memory Pool.
+/// \param[in]     mp_id         memory pool ID obtained by \ref osMemoryPoolNew.
+/// \return number of memory blocks used.
+uint32_t osMemoryPoolGetCount (osMemoryPoolId_t mp_id);
+
+/// Get number of memory blocks available in a Memory Pool.
+/// \param[in]     mp_id         memory pool ID obtained by \ref osMemoryPoolNew.
+/// \return number of memory blocks available.
+uint32_t osMemoryPoolGetSpace (osMemoryPoolId_t mp_id);
+
+/// Delete a Memory Pool object.
+/// \param[in]     mp_id         memory pool ID obtained by \ref osMemoryPoolNew.
+/// \return status code that indicates the execution status of the function.
+osStatus_t osMemoryPoolDelete (osMemoryPoolId_t mp_id);
+
+
+//  ==== Message Queue Management Functions ====
+
+/// Create and Initialize a Message Queue object.
+/// \param[in]     msg_count     maximum number of messages in queue.
+/// \param[in]     msg_size      maximum message size in bytes.
+/// \param[in]     attr          message queue attributes; NULL: default values.
+/// \return message queue ID for reference by other functions or NULL in case of error.
+osMessageQueueId_t osMessageQueueNew (uint32_t msg_count, uint32_t msg_size, const osMessageQueueAttr_t *attr);
+
+/// Get name of a Message Queue object.
+/// \param[in]     mq_id         message queue ID obtained by \ref osMessageQueueNew.
+/// \return name as NULL terminated string.
+const char *osMessageQueueGetName (osMessageQueueId_t mq_id);
+
+/// Put a Message into a Queue or timeout if Queue is full.
+/// \param[in]     mq_id         message queue ID obtained by \ref osMessageQueueNew.
+/// \param[in]     msg_ptr       pointer to buffer with message to put into a queue.
+/// \param[in]     msg_prio      message priority.
+/// \param[in]     timeout       \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.
+/// \return status code that indicates the execution status of the function.
+osStatus_t osMessageQueuePut (osMessageQueueId_t mq_id, const void *msg_ptr, uint8_t msg_prio, uint32_t timeout);
+
+/// Get a Message from a Queue or timeout if Queue is empty.
+/// \param[in]     mq_id         message queue ID obtained by \ref osMessageQueueNew.
+/// \param[out]    msg_ptr       pointer to buffer for message to get from a queue.
+/// \param[out]    msg_prio      pointer to buffer for message priority or NULL.
+/// \param[in]     timeout       \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.
+/// \return status code that indicates the execution status of the function.
+osStatus_t osMessageQueueGet (osMessageQueueId_t mq_id, void *msg_ptr, uint8_t *msg_prio, uint32_t timeout);
+
+/// Get maximum number of messages in a Message Queue.
+/// \param[in]     mq_id         message queue ID obtained by \ref osMessageQueueNew.
+/// \return maximum number of messages.
+uint32_t osMessageQueueGetCapacity (osMessageQueueId_t mq_id);
+
+/// Get maximum message size in a Memory Pool.
+/// \param[in]     mq_id         message queue ID obtained by \ref osMessageQueueNew.
+/// \return maximum message size in bytes.
+uint32_t osMessageQueueGetMsgSize (osMessageQueueId_t mq_id);
+
+/// Get number of queued messages in a Message Queue.
+/// \param[in]     mq_id         message queue ID obtained by \ref osMessageQueueNew.
+/// \return number of queued messages.
+uint32_t osMessageQueueGetCount (osMessageQueueId_t mq_id);
+
+/// Get number of available slots for messages in a Message Queue.
+/// \param[in]     mq_id         message queue ID obtained by \ref osMessageQueueNew.
+/// \return number of available slots for messages.
+uint32_t osMessageQueueGetSpace (osMessageQueueId_t mq_id);
+
+/// Reset a Message Queue to initial empty state.
+/// \param[in]     mq_id         message queue ID obtained by \ref osMessageQueueNew.
+/// \return status code that indicates the execution status of the function.
+osStatus_t osMessageQueueReset (osMessageQueueId_t mq_id);
+
+/// Delete a Message Queue object.
+/// \param[in]     mq_id         message queue ID obtained by \ref osMessageQueueNew.
+/// \return status code that indicates the execution status of the function.
+osStatus_t osMessageQueueDelete (osMessageQueueId_t mq_id);
+
+
+#ifdef  __cplusplus
+}
+#endif
+
+#endif  // CMSIS_OS2_H_
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/freertos_mpool.h b/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/freertos_mpool.h
new file mode 100644
index 0000000..ffb4088
--- /dev/null
+++ b/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/freertos_mpool.h
@@ -0,0 +1,63 @@
+/* --------------------------------------------------------------------------
+ * Copyright (c) 2013-2020 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ *      Name:    freertos_mpool.h
+ *      Purpose: CMSIS RTOS2 wrapper for FreeRTOS
+ *
+ *---------------------------------------------------------------------------*/
+
+#ifndef FREERTOS_MPOOL_H_
+#define FREERTOS_MPOOL_H_
+
+#include <stdint.h>
+#include "FreeRTOS.h"
+#include "semphr.h"
+
+/* Memory Pool implementation definitions */
+#define MPOOL_STATUS              0x5EED0000U
+
+/* Memory Block header */
+typedef struct {
+  void *next;                   /* Pointer to next block  */
+} MemPoolBlock_t;
+
+/* Memory Pool control block */
+typedef struct MemPoolDef_t {
+  MemPoolBlock_t    *head;      /* Pointer to head block   */
+  SemaphoreHandle_t  sem;       /* Pool semaphore handle   */
+  uint8_t           *mem_arr;   /* Pool memory array       */
+  uint32_t           mem_sz;    /* Pool memory array size  */
+  const char        *name;      /* Pointer to name string  */
+  uint32_t           bl_sz;     /* Size of a single block  */
+  uint32_t           bl_cnt;    /* Number of blocks        */
+  uint32_t           n;         /* Block allocation index  */
+  volatile uint32_t  status;    /* Object status flags     */
+#if (configSUPPORT_STATIC_ALLOCATION == 1)
+  StaticSemaphore_t  mem_sem;   /* Semaphore object memory */
+#endif
+} MemPool_t;
+
+/* No need to hide static object type, just align to coding style */
+#define StaticMemPool_t         MemPool_t
+
+/* Define memory pool control block size */
+#define MEMPOOL_CB_SIZE         (sizeof(StaticMemPool_t))
+
+/* Define size of the byte array required to create count of blocks of given size */
+#define MEMPOOL_ARR_SIZE(bl_count, bl_size) (((((bl_size) + (4 - 1)) / 4) * 4)*(bl_count))
+
+#endif /* FREERTOS_MPOOL_H_ */
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/freertos_os2.h b/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/freertos_os2.h
new file mode 100644
index 0000000..83e050e
--- /dev/null
+++ b/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/freertos_os2.h
@@ -0,0 +1,310 @@
+/* --------------------------------------------------------------------------
+ * Copyright (c) 2013-2020 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ *      Name:    freertos_os2.h
+ *      Purpose: CMSIS RTOS2 wrapper for FreeRTOS
+ *
+ *---------------------------------------------------------------------------*/
+
+#ifndef FREERTOS_OS2_H_
+#define FREERTOS_OS2_H_
+
+#include <string.h>
+#include <stdint.h>
+
+#include "FreeRTOS.h"                   // ARM.FreeRTOS::RTOS:Core
+
+#include CMSIS_device_header
+
+/*
+  CMSIS-RTOS2 FreeRTOS image size optimization definitions.
+
+  Note: Definitions configUSE_OS2 can be used to optimize FreeRTOS image size when
+        certain functionality is not required when using CMSIS-RTOS2 API.
+        In general optimization decisions are left to the tool chain but in cases
+        when coding style prevents it to optimize the code following optional
+        definitions can be used.
+*/
+
+/*
+  Option to exclude CMSIS-RTOS2 functions osThreadSuspend and osThreadResume from
+  the application image.
+*/
+#ifndef configUSE_OS2_THREAD_SUSPEND_RESUME
+#define configUSE_OS2_THREAD_SUSPEND_RESUME   1
+#endif
+
+/*
+  Option to exclude CMSIS-RTOS2 function osThreadEnumerate from the application image.
+*/
+#ifndef configUSE_OS2_THREAD_ENUMERATE
+#define configUSE_OS2_THREAD_ENUMERATE        1
+#endif
+
+/*
+  Option to disable CMSIS-RTOS2 function osEventFlagsSet and osEventFlagsClear
+  operation from ISR.
+*/
+#ifndef configUSE_OS2_EVENTFLAGS_FROM_ISR
+#define configUSE_OS2_EVENTFLAGS_FROM_ISR     1
+#endif
+
+/*
+  Option to exclude CMSIS-RTOS2 Thread Flags API functions from the application image.
+*/
+#ifndef configUSE_OS2_THREAD_FLAGS
+#define configUSE_OS2_THREAD_FLAGS            configUSE_TASK_NOTIFICATIONS
+#endif
+
+/*
+  Option to exclude CMSIS-RTOS2 Timer API functions from the application image.
+*/
+#ifndef configUSE_OS2_TIMER
+#define configUSE_OS2_TIMER                   configUSE_TIMERS
+#endif
+
+/*
+  Option to exclude CMSIS-RTOS2 Mutex API functions from the application image.
+*/
+#ifndef configUSE_OS2_MUTEX
+#define configUSE_OS2_MUTEX                   configUSE_MUTEXES
+#endif
+
+
+/*
+  CMSIS-RTOS2 FreeRTOS configuration check (FreeRTOSConfig.h).
+
+  Note: CMSIS-RTOS API requires functions included by using following definitions.
+        In case if certain API function is not used compiler will optimize it away.
+*/
+#if (INCLUDE_xSemaphoreGetMutexHolder == 0)
+  /*
+    CMSIS-RTOS2 function osMutexGetOwner uses FreeRTOS function xSemaphoreGetMutexHolder. In case if
+    osMutexGetOwner is not used in the application image, compiler will optimize it away.
+    Set #define INCLUDE_xSemaphoreGetMutexHolder 1 to fix this error.
+  */
+  #error "Definition INCLUDE_xSemaphoreGetMutexHolder must equal 1 to implement Mutex Management API."
+#endif
+#if (INCLUDE_vTaskDelay == 0)
+  /*
+    CMSIS-RTOS2 function osDelay uses FreeRTOS function vTaskDelay. In case if
+    osDelay is not used in the application image, compiler will optimize it away.
+    Set #define INCLUDE_vTaskDelay 1 to fix this error.
+  */
+  #error "Definition INCLUDE_vTaskDelay must equal 1 to implement Generic Wait Functions API."
+#endif
+#if (INCLUDE_vTaskDelayUntil == 0)
+  /*
+    CMSIS-RTOS2 function osDelayUntil uses FreeRTOS function vTaskDelayUntil. In case if
+    osDelayUntil is not used in the application image, compiler will optimize it away.
+    Set #define INCLUDE_vTaskDelayUntil 1 to fix this error.
+  */
+  #error "Definition INCLUDE_vTaskDelayUntil must equal 1 to implement Generic Wait Functions API."
+#endif
+#if (INCLUDE_vTaskDelete == 0)
+  /*
+    CMSIS-RTOS2 function osThreadTerminate and osThreadExit uses FreeRTOS function
+    vTaskDelete. In case if they are not used in the application image, compiler
+    will optimize them away.
+    Set #define INCLUDE_vTaskDelete 1 to fix this error.
+  */
+  #error "Definition INCLUDE_vTaskDelete must equal 1 to implement Thread Management API."
+#endif
+#if (INCLUDE_xTaskGetCurrentTaskHandle == 0)
+  /*
+    CMSIS-RTOS2 API uses FreeRTOS function xTaskGetCurrentTaskHandle to implement
+    functions osThreadGetId, osThreadFlagsClear and osThreadFlagsGet. In case if these
+    functions are not used in the application image, compiler will optimize them away.
+    Set #define INCLUDE_xTaskGetCurrentTaskHandle 1 to fix this error.
+  */
+  #error "Definition INCLUDE_xTaskGetCurrentTaskHandle must equal 1 to implement Thread Management API."
+#endif
+#if (INCLUDE_xTaskGetSchedulerState == 0)
+  /*
+    CMSIS-RTOS2 API uses FreeRTOS function xTaskGetSchedulerState to implement Kernel
+    tick handling and therefore it is vital that xTaskGetSchedulerState is included into
+    the application image.
+    Set #define INCLUDE_xTaskGetSchedulerState 1 to fix this error.
+  */
+  #error "Definition INCLUDE_xTaskGetSchedulerState must equal 1 to implement Kernel Information and Control API."
+#endif
+#if (INCLUDE_uxTaskGetStackHighWaterMark == 0)
+  /*
+    CMSIS-RTOS2 function osThreadGetStackSpace uses FreeRTOS function uxTaskGetStackHighWaterMark.
+    In case if osThreadGetStackSpace is not used in the application image, compiler will
+    optimize it away.
+    Set #define INCLUDE_uxTaskGetStackHighWaterMark 1 to fix this error.
+  */
+  #error "Definition INCLUDE_uxTaskGetStackHighWaterMark must equal 1 to implement Thread Management API."
+#endif
+#if (INCLUDE_uxTaskPriorityGet == 0)
+  /*
+    CMSIS-RTOS2 function osThreadGetPriority uses FreeRTOS function uxTaskPriorityGet. In case if
+    osThreadGetPriority is not used in the application image, compiler will optimize it away.
+    Set #define INCLUDE_uxTaskPriorityGet 1 to fix this error.
+  */
+  #error "Definition INCLUDE_uxTaskPriorityGet must equal 1 to implement Thread Management API."
+#endif
+#if (INCLUDE_vTaskPrioritySet == 0)
+  /*
+    CMSIS-RTOS2 function osThreadSetPriority uses FreeRTOS function vTaskPrioritySet. In case if
+    osThreadSetPriority is not used in the application image, compiler will optimize it away.
+    Set #define INCLUDE_vTaskPrioritySet 1 to fix this error.
+  */
+  #error "Definition INCLUDE_vTaskPrioritySet must equal 1 to implement Thread Management API."
+#endif
+#if (INCLUDE_eTaskGetState == 0)
+  /*
+    CMSIS-RTOS2 API uses FreeRTOS function vTaskDelayUntil to implement functions osThreadGetState
+    and osThreadTerminate. In case if these functions are not used in the application image,
+    compiler will optimize them away.
+    Set #define INCLUDE_eTaskGetState 1 to fix this error.
+  */
+  #error "Definition INCLUDE_eTaskGetState must equal 1 to implement Thread Management API."
+#endif
+#if (INCLUDE_vTaskSuspend == 0)
+  /*
+    CMSIS-RTOS2 API uses FreeRTOS functions vTaskSuspend and vTaskResume to implement
+    functions osThreadSuspend and osThreadResume. In case if these functions are not
+    used in the application image, compiler will optimize them away.
+    Set #define INCLUDE_vTaskSuspend 1 to fix this error.
+
+    Alternatively, if the application does not use osThreadSuspend and
+    osThreadResume they can be excluded from the image code by setting:
+    #define configUSE_OS2_THREAD_SUSPEND_RESUME 0 (in FreeRTOSConfig.h)
+  */
+  #if (configUSE_OS2_THREAD_SUSPEND_RESUME == 1)
+    #error "Definition INCLUDE_vTaskSuspend must equal 1 to implement Kernel Information and Control API."
+  #endif
+#endif
+#if (INCLUDE_xTimerPendFunctionCall == 0)
+  /*
+    CMSIS-RTOS2 function osEventFlagsSet and osEventFlagsClear, when called from
+    the ISR, call FreeRTOS functions xEventGroupSetBitsFromISR and
+    xEventGroupClearBitsFromISR which are only enabled if timers are operational and
+    xTimerPendFunctionCall in enabled.
+    Set #define INCLUDE_xTimerPendFunctionCall 1 and #define configUSE_TIMERS 1
+    to fix this error.
+
+    Alternatively, if the application does not use osEventFlagsSet and osEventFlagsClear
+    from the ISR their operation from ISR can be restricted by setting:
+    #define configUSE_OS2_EVENTFLAGS_FROM_ISR 0 (in FreeRTOSConfig.h)
+  */
+  #if (configUSE_OS2_EVENTFLAGS_FROM_ISR == 1)
+    #error "Definition INCLUDE_xTimerPendFunctionCall must equal 1 to implement Event Flags API."
+  #endif
+#endif
+
+#if (configUSE_TIMERS == 0)
+  /*
+    CMSIS-RTOS2 Timer Management API functions use FreeRTOS timer functions to implement
+    timer management. In case if these functions are not used in the application image,
+    compiler will optimize them away.
+    Set #define configUSE_TIMERS 1 to fix this error.
+
+    Alternatively, if the application does not use timer functions they can be
+    excluded from the image code by setting:
+    #define configUSE_OS2_TIMER 0 (in FreeRTOSConfig.h)
+  */
+  #if (configUSE_OS2_TIMER == 1)
+    #error "Definition configUSE_TIMERS must equal 1 to implement Timer Management API."
+  #endif
+#endif
+
+#if (configUSE_MUTEXES == 0)
+  /*
+    CMSIS-RTOS2 Mutex Management API functions use FreeRTOS mutex functions to implement
+    mutex management. In case if these functions are not used in the application image,
+    compiler will optimize them away.
+    Set #define configUSE_MUTEXES 1 to fix this error.
+
+    Alternatively, if the application does not use mutex functions they can be
+    excluded from the image code by setting:
+    #define configUSE_OS2_MUTEX 0 (in FreeRTOSConfig.h)
+  */
+  #if (configUSE_OS2_MUTEX == 1)
+    #error "Definition configUSE_MUTEXES must equal 1 to implement Mutex Management API."
+  #endif
+#endif
+
+#if (configUSE_COUNTING_SEMAPHORES == 0)
+  /*
+    CMSIS-RTOS2 Memory Pool functions use FreeRTOS function xSemaphoreCreateCounting
+    to implement memory pools. In case if these functions are not used in the application image,
+    compiler will optimize them away.
+    Set #define configUSE_COUNTING_SEMAPHORES 1 to fix this error.
+  */
+  #error "Definition configUSE_COUNTING_SEMAPHORES must equal 1 to implement Memory Pool API."
+#endif
+#if (configUSE_TASK_NOTIFICATIONS == 0)
+  /*
+    CMSIS-RTOS2 Thread Flags API functions use FreeRTOS Task Notification functions to implement
+    thread flag management. In case if these functions are not used in the application image,
+    compiler will optimize them away.
+    Set #define configUSE_TASK_NOTIFICATIONS 1 to fix this error.
+
+    Alternatively, if the application does not use thread flags functions they can be
+    excluded from the image code by setting:
+    #define configUSE_OS2_THREAD_FLAGS 0 (in FreeRTOSConfig.h)
+  */
+  #if (configUSE_OS2_THREAD_FLAGS == 1)
+    #error "Definition configUSE_TASK_NOTIFICATIONS must equal 1 to implement Thread Flags API."
+  #endif
+#endif
+
+#if (configUSE_TRACE_FACILITY == 0)
+  /*
+    CMSIS-RTOS2 function osThreadEnumerate requires FreeRTOS function uxTaskGetSystemState
+    which is only enabled if configUSE_TRACE_FACILITY == 1.
+    Set #define configUSE_TRACE_FACILITY 1 to fix this error.
+
+    Alternatively, if the application does not use osThreadEnumerate it can be
+    excluded from the image code by setting:
+    #define configUSE_OS2_THREAD_ENUMERATE 0 (in FreeRTOSConfig.h)
+  */
+  #if (configUSE_OS2_THREAD_ENUMERATE == 1)
+    #error "Definition configUSE_TRACE_FACILITY must equal 1 to implement osThreadEnumerate."
+  #endif
+#endif
+
+#if (configUSE_16_BIT_TICKS == 1)
+  /*
+    CMSIS-RTOS2 wrapper for FreeRTOS relies on 32-bit tick timer which is also optimal on
+    a 32-bit CPU architectures.
+    Set #define configUSE_16_BIT_TICKS 0 to fix this error.
+  */
+  #error "Definition configUSE_16_BIT_TICKS must be zero to implement CMSIS-RTOS2 API."
+#endif
+
+#if (configMAX_PRIORITIES != 56)
+  /*
+    CMSIS-RTOS2 defines 56 different priorities (see osPriority_t) and portable CMSIS-RTOS2
+    implementation should implement the same number of priorities.
+    Set #define configMAX_PRIORITIES 56 to fix this error.
+  */
+  #error "Definition configMAX_PRIORITIES must equal 56 to implement Thread Management API."
+#endif
+#if (configUSE_PORT_OPTIMISED_TASK_SELECTION != 0)
+  /*
+    CMSIS-RTOS2 requires handling of 56 different priorities (see osPriority_t) while FreeRTOS port
+    optimised selection for Cortex core only handles 32 different priorities.
+    Set #define configUSE_PORT_OPTIMISED_TASK_SELECTION 0 to fix this error.
+  */
+  #error "Definition configUSE_PORT_OPTIMISED_TASK_SELECTION must be zero to implement Thread Management API."
+#endif
+
+#endif /* FREERTOS_OS2_H_ */
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/LICENSE b/Middlewares/Third_Party/FreeRTOS/Source/LICENSE
new file mode 100644
index 0000000..d479d8b
--- /dev/null
+++ b/Middlewares/Third_Party/FreeRTOS/Source/LICENSE
@@ -0,0 +1,18 @@
+Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+Permission is hereby granted, free of charge, to any person obtaining a copy of
+this software and associated documentation files (the "Software"), to deal in
+the Software without restriction, including without limitation the rights to
+use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+the Software, and to permit persons to whom the Software is furnished to do so,
+subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/croutine.c b/Middlewares/Third_Party/FreeRTOS/Source/croutine.c
new file mode 100644
index 0000000..507e217
--- /dev/null
+++ b/Middlewares/Third_Party/FreeRTOS/Source/croutine.c
@@ -0,0 +1,353 @@
+/*
+ * FreeRTOS Kernel V10.3.1
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#include "FreeRTOS.h"
+#include "task.h"
+#include "croutine.h"
+
+/* Remove the whole file is co-routines are not being used. */
+#if( configUSE_CO_ROUTINES != 0 )
+
+/*
+ * Some kernel aware debuggers require data to be viewed to be global, rather
+ * than file scope.
+ */
+#ifdef portREMOVE_STATIC_QUALIFIER
+	#define static
+#endif
+
+
+/* Lists for ready and blocked co-routines. --------------------*/
+static List_t pxReadyCoRoutineLists[ configMAX_CO_ROUTINE_PRIORITIES ];	/*< Prioritised ready co-routines. */
+static List_t xDelayedCoRoutineList1;									/*< Delayed co-routines. */
+static List_t xDelayedCoRoutineList2;									/*< Delayed co-routines (two lists are used - one for delays that have overflowed the current tick count. */
+static List_t * pxDelayedCoRoutineList;									/*< Points to the delayed co-routine list currently being used. */
+static List_t * pxOverflowDelayedCoRoutineList;							/*< Points to the delayed co-routine list currently being used to hold co-routines that have overflowed the current tick count. */
+static List_t xPendingReadyCoRoutineList;								/*< Holds co-routines that have been readied by an external event.  They cannot be added directly to the ready lists as the ready lists cannot be accessed by interrupts. */
+
+/* Other file private variables. --------------------------------*/
+CRCB_t * pxCurrentCoRoutine = NULL;
+static UBaseType_t uxTopCoRoutineReadyPriority = 0;
+static TickType_t xCoRoutineTickCount = 0, xLastTickCount = 0, xPassedTicks = 0;
+
+/* The initial state of the co-routine when it is created. */
+#define corINITIAL_STATE	( 0 )
+
+/*
+ * Place the co-routine represented by pxCRCB into the appropriate ready queue
+ * for the priority.  It is inserted at the end of the list.
+ *
+ * This macro accesses the co-routine ready lists and therefore must not be
+ * used from within an ISR.
+ */
+#define prvAddCoRoutineToReadyQueue( pxCRCB )																		\
+{																													\
+	if( pxCRCB->uxPriority > uxTopCoRoutineReadyPriority )															\
+	{																												\
+		uxTopCoRoutineReadyPriority = pxCRCB->uxPriority;															\
+	}																												\
+	vListInsertEnd( ( List_t * ) &( pxReadyCoRoutineLists[ pxCRCB->uxPriority ] ), &( pxCRCB->xGenericListItem ) );	\
+}
+
+/*
+ * Utility to ready all the lists used by the scheduler.  This is called
+ * automatically upon the creation of the first co-routine.
+ */
+static void prvInitialiseCoRoutineLists( void );
+
+/*
+ * Co-routines that are readied by an interrupt cannot be placed directly into
+ * the ready lists (there is no mutual exclusion).  Instead they are placed in
+ * in the pending ready list in order that they can later be moved to the ready
+ * list by the co-routine scheduler.
+ */
+static void prvCheckPendingReadyList( void );
+
+/*
+ * Macro that looks at the list of co-routines that are currently delayed to
+ * see if any require waking.
+ *
+ * Co-routines are stored in the queue in the order of their wake time -
+ * meaning once one co-routine has been found whose timer has not expired
+ * we need not look any further down the list.
+ */
+static void prvCheckDelayedList( void );
+
+/*-----------------------------------------------------------*/
+
+BaseType_t xCoRoutineCreate( crCOROUTINE_CODE pxCoRoutineCode, UBaseType_t uxPriority, UBaseType_t uxIndex )
+{
+BaseType_t xReturn;
+CRCB_t *pxCoRoutine;
+
+	/* Allocate the memory that will store the co-routine control block. */
+	pxCoRoutine = ( CRCB_t * ) pvPortMalloc( sizeof( CRCB_t ) );
+	if( pxCoRoutine )
+	{
+		/* If pxCurrentCoRoutine is NULL then this is the first co-routine to
+		be created and the co-routine data structures need initialising. */
+		if( pxCurrentCoRoutine == NULL )
+		{
+			pxCurrentCoRoutine = pxCoRoutine;
+			prvInitialiseCoRoutineLists();
+		}
+
+		/* Check the priority is within limits. */
+		if( uxPriority >= configMAX_CO_ROUTINE_PRIORITIES )
+		{
+			uxPriority = configMAX_CO_ROUTINE_PRIORITIES - 1;
+		}
+
+		/* Fill out the co-routine control block from the function parameters. */
+		pxCoRoutine->uxState = corINITIAL_STATE;
+		pxCoRoutine->uxPriority = uxPriority;
+		pxCoRoutine->uxIndex = uxIndex;
+		pxCoRoutine->pxCoRoutineFunction = pxCoRoutineCode;
+
+		/* Initialise all the other co-routine control block parameters. */
+		vListInitialiseItem( &( pxCoRoutine->xGenericListItem ) );
+		vListInitialiseItem( &( pxCoRoutine->xEventListItem ) );
+
+		/* Set the co-routine control block as a link back from the ListItem_t.
+		This is so we can get back to the containing CRCB from a generic item
+		in a list. */
+		listSET_LIST_ITEM_OWNER( &( pxCoRoutine->xGenericListItem ), pxCoRoutine );
+		listSET_LIST_ITEM_OWNER( &( pxCoRoutine->xEventListItem ), pxCoRoutine );
+
+		/* Event lists are always in priority order. */
+		listSET_LIST_ITEM_VALUE( &( pxCoRoutine->xEventListItem ), ( ( TickType_t ) configMAX_CO_ROUTINE_PRIORITIES - ( TickType_t ) uxPriority ) );
+
+		/* Now the co-routine has been initialised it can be added to the ready
+		list at the correct priority. */
+		prvAddCoRoutineToReadyQueue( pxCoRoutine );
+
+		xReturn = pdPASS;
+	}
+	else
+	{
+		xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY;
+	}
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+void vCoRoutineAddToDelayedList( TickType_t xTicksToDelay, List_t *pxEventList )
+{
+TickType_t xTimeToWake;
+
+	/* Calculate the time to wake - this may overflow but this is
+	not a problem. */
+	xTimeToWake = xCoRoutineTickCount + xTicksToDelay;
+
+	/* We must remove ourselves from the ready list before adding
+	ourselves to the blocked list as the same list item is used for
+	both lists. */
+	( void ) uxListRemove( ( ListItem_t * ) &( pxCurrentCoRoutine->xGenericListItem ) );
+
+	/* The list item will be inserted in wake time order. */
+	listSET_LIST_ITEM_VALUE( &( pxCurrentCoRoutine->xGenericListItem ), xTimeToWake );
+
+	if( xTimeToWake < xCoRoutineTickCount )
+	{
+		/* Wake time has overflowed.  Place this item in the
+		overflow list. */
+		vListInsert( ( List_t * ) pxOverflowDelayedCoRoutineList, ( ListItem_t * ) &( pxCurrentCoRoutine->xGenericListItem ) );
+	}
+	else
+	{
+		/* The wake time has not overflowed, so we can use the
+		current block list. */
+		vListInsert( ( List_t * ) pxDelayedCoRoutineList, ( ListItem_t * ) &( pxCurrentCoRoutine->xGenericListItem ) );
+	}
+
+	if( pxEventList )
+	{
+		/* Also add the co-routine to an event list.  If this is done then the
+		function must be called with interrupts disabled. */
+		vListInsert( pxEventList, &( pxCurrentCoRoutine->xEventListItem ) );
+	}
+}
+/*-----------------------------------------------------------*/
+
+static void prvCheckPendingReadyList( void )
+{
+	/* Are there any co-routines waiting to get moved to the ready list?  These
+	are co-routines that have been readied by an ISR.  The ISR cannot access
+	the	ready lists itself. */
+	while( listLIST_IS_EMPTY( &xPendingReadyCoRoutineList ) == pdFALSE )
+	{
+		CRCB_t *pxUnblockedCRCB;
+
+		/* The pending ready list can be accessed by an ISR. */
+		portDISABLE_INTERRUPTS();
+		{
+			pxUnblockedCRCB = ( CRCB_t * ) listGET_OWNER_OF_HEAD_ENTRY( (&xPendingReadyCoRoutineList) );
+			( void ) uxListRemove( &( pxUnblockedCRCB->xEventListItem ) );
+		}
+		portENABLE_INTERRUPTS();
+
+		( void ) uxListRemove( &( pxUnblockedCRCB->xGenericListItem ) );
+		prvAddCoRoutineToReadyQueue( pxUnblockedCRCB );
+	}
+}
+/*-----------------------------------------------------------*/
+
+static void prvCheckDelayedList( void )
+{
+CRCB_t *pxCRCB;
+
+	xPassedTicks = xTaskGetTickCount() - xLastTickCount;
+	while( xPassedTicks )
+	{
+		xCoRoutineTickCount++;
+		xPassedTicks--;
+
+		/* If the tick count has overflowed we need to swap the ready lists. */
+		if( xCoRoutineTickCount == 0 )
+		{
+			List_t * pxTemp;
+
+			/* Tick count has overflowed so we need to swap the delay lists.  If there are
+			any items in pxDelayedCoRoutineList here then there is an error! */
+			pxTemp = pxDelayedCoRoutineList;
+			pxDelayedCoRoutineList = pxOverflowDelayedCoRoutineList;
+			pxOverflowDelayedCoRoutineList = pxTemp;
+		}
+
+		/* See if this tick has made a timeout expire. */
+		while( listLIST_IS_EMPTY( pxDelayedCoRoutineList ) == pdFALSE )
+		{
+			pxCRCB = ( CRCB_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxDelayedCoRoutineList );
+
+			if( xCoRoutineTickCount < listGET_LIST_ITEM_VALUE( &( pxCRCB->xGenericListItem ) ) )
+			{
+				/* Timeout not yet expired. */
+				break;
+			}
+
+			portDISABLE_INTERRUPTS();
+			{
+				/* The event could have occurred just before this critical
+				section.  If this is the case then the generic list item will
+				have been moved to the pending ready list and the following
+				line is still valid.  Also the pvContainer parameter will have
+				been set to NULL so the following lines are also valid. */
+				( void ) uxListRemove( &( pxCRCB->xGenericListItem ) );
+
+				/* Is the co-routine waiting on an event also? */
+				if( pxCRCB->xEventListItem.pxContainer )
+				{
+					( void ) uxListRemove( &( pxCRCB->xEventListItem ) );
+				}
+			}
+			portENABLE_INTERRUPTS();
+
+			prvAddCoRoutineToReadyQueue( pxCRCB );
+		}
+	}
+
+	xLastTickCount = xCoRoutineTickCount;
+}
+/*-----------------------------------------------------------*/
+
+void vCoRoutineSchedule( void )
+{
+	/* See if any co-routines readied by events need moving to the ready lists. */
+	prvCheckPendingReadyList();
+
+	/* See if any delayed co-routines have timed out. */
+	prvCheckDelayedList();
+
+	/* Find the highest priority queue that contains ready co-routines. */
+	while( listLIST_IS_EMPTY( &( pxReadyCoRoutineLists[ uxTopCoRoutineReadyPriority ] ) ) )
+	{
+		if( uxTopCoRoutineReadyPriority == 0 )
+		{
+			/* No more co-routines to check. */
+			return;
+		}
+		--uxTopCoRoutineReadyPriority;
+	}
+
+	/* listGET_OWNER_OF_NEXT_ENTRY walks through the list, so the co-routines
+	 of the	same priority get an equal share of the processor time. */
+	listGET_OWNER_OF_NEXT_ENTRY( pxCurrentCoRoutine, &( pxReadyCoRoutineLists[ uxTopCoRoutineReadyPriority ] ) );
+
+	/* Call the co-routine. */
+	( pxCurrentCoRoutine->pxCoRoutineFunction )( pxCurrentCoRoutine, pxCurrentCoRoutine->uxIndex );
+
+	return;
+}
+/*-----------------------------------------------------------*/
+
+static void prvInitialiseCoRoutineLists( void )
+{
+UBaseType_t uxPriority;
+
+	for( uxPriority = 0; uxPriority < configMAX_CO_ROUTINE_PRIORITIES; uxPriority++ )
+	{
+		vListInitialise( ( List_t * ) &( pxReadyCoRoutineLists[ uxPriority ] ) );
+	}
+
+	vListInitialise( ( List_t * ) &xDelayedCoRoutineList1 );
+	vListInitialise( ( List_t * ) &xDelayedCoRoutineList2 );
+	vListInitialise( ( List_t * ) &xPendingReadyCoRoutineList );
+
+	/* Start with pxDelayedCoRoutineList using list1 and the
+	pxOverflowDelayedCoRoutineList using list2. */
+	pxDelayedCoRoutineList = &xDelayedCoRoutineList1;
+	pxOverflowDelayedCoRoutineList = &xDelayedCoRoutineList2;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xCoRoutineRemoveFromEventList( const List_t *pxEventList )
+{
+CRCB_t *pxUnblockedCRCB;
+BaseType_t xReturn;
+
+	/* This function is called from within an interrupt.  It can only access
+	event lists and the pending ready list.  This function assumes that a
+	check has already been made to ensure pxEventList is not empty. */
+	pxUnblockedCRCB = ( CRCB_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxEventList );
+	( void ) uxListRemove( &( pxUnblockedCRCB->xEventListItem ) );
+	vListInsertEnd( ( List_t * ) &( xPendingReadyCoRoutineList ), &( pxUnblockedCRCB->xEventListItem ) );
+
+	if( pxUnblockedCRCB->uxPriority >= pxCurrentCoRoutine->uxPriority )
+	{
+		xReturn = pdTRUE;
+	}
+	else
+	{
+		xReturn = pdFALSE;
+	}
+
+	return xReturn;
+}
+
+#endif /* configUSE_CO_ROUTINES == 0 */
+
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/event_groups.c b/Middlewares/Third_Party/FreeRTOS/Source/event_groups.c
new file mode 100644
index 0000000..0bf3b96
--- /dev/null
+++ b/Middlewares/Third_Party/FreeRTOS/Source/event_groups.c
@@ -0,0 +1,753 @@
+/*
+ * FreeRTOS Kernel V10.3.1
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Standard includes. */
+#include <stdlib.h>
+
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
+all the API functions to use the MPU wrappers.  That should only be done when
+task.h is included from an application file. */
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+/* FreeRTOS includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+#include "timers.h"
+#include "event_groups.h"
+
+/* Lint e961, e750 and e9021 are suppressed as a MISRA exception justified
+because the MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined
+for the header files above, but not in this file, in order to generate the
+correct privileged Vs unprivileged linkage and placement. */
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE /*lint !e961 !e750 !e9021 See comment above. */
+
+/* The following bit fields convey control information in a task's event list
+item value.  It is important they don't clash with the
+taskEVENT_LIST_ITEM_VALUE_IN_USE definition. */
+#if configUSE_16_BIT_TICKS == 1
+	#define eventCLEAR_EVENTS_ON_EXIT_BIT	0x0100U
+	#define eventUNBLOCKED_DUE_TO_BIT_SET	0x0200U
+	#define eventWAIT_FOR_ALL_BITS			0x0400U
+	#define eventEVENT_BITS_CONTROL_BYTES	0xff00U
+#else
+	#define eventCLEAR_EVENTS_ON_EXIT_BIT	0x01000000UL
+	#define eventUNBLOCKED_DUE_TO_BIT_SET	0x02000000UL
+	#define eventWAIT_FOR_ALL_BITS			0x04000000UL
+	#define eventEVENT_BITS_CONTROL_BYTES	0xff000000UL
+#endif
+
+typedef struct EventGroupDef_t
+{
+	EventBits_t uxEventBits;
+	List_t xTasksWaitingForBits;		/*< List of tasks waiting for a bit to be set. */
+
+	#if( configUSE_TRACE_FACILITY == 1 )
+		UBaseType_t uxEventGroupNumber;
+	#endif
+
+	#if( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
+		uint8_t ucStaticallyAllocated; /*< Set to pdTRUE if the event group is statically allocated to ensure no attempt is made to free the memory. */
+	#endif
+} EventGroup_t;
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Test the bits set in uxCurrentEventBits to see if the wait condition is met.
+ * The wait condition is defined by xWaitForAllBits.  If xWaitForAllBits is
+ * pdTRUE then the wait condition is met if all the bits set in uxBitsToWaitFor
+ * are also set in uxCurrentEventBits.  If xWaitForAllBits is pdFALSE then the
+ * wait condition is met if any of the bits set in uxBitsToWait for are also set
+ * in uxCurrentEventBits.
+ */
+static BaseType_t prvTestWaitCondition( const EventBits_t uxCurrentEventBits, const EventBits_t uxBitsToWaitFor, const BaseType_t xWaitForAllBits ) PRIVILEGED_FUNCTION;
+
+/*-----------------------------------------------------------*/
+
+#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+
+	EventGroupHandle_t xEventGroupCreateStatic( StaticEventGroup_t *pxEventGroupBuffer )
+	{
+	EventGroup_t *pxEventBits;
+
+		/* A StaticEventGroup_t object must be provided. */
+		configASSERT( pxEventGroupBuffer );
+
+		#if( configASSERT_DEFINED == 1 )
+		{
+			/* Sanity check that the size of the structure used to declare a
+			variable of type StaticEventGroup_t equals the size of the real
+			event group structure. */
+			volatile size_t xSize = sizeof( StaticEventGroup_t );
+			configASSERT( xSize == sizeof( EventGroup_t ) );
+		} /*lint !e529 xSize is referenced if configASSERT() is defined. */
+		#endif /* configASSERT_DEFINED */
+
+		/* The user has provided a statically allocated event group - use it. */
+		pxEventBits = ( EventGroup_t * ) pxEventGroupBuffer; /*lint !e740 !e9087 EventGroup_t and StaticEventGroup_t are deliberately aliased for data hiding purposes and guaranteed to have the same size and alignment requirement - checked by configASSERT(). */
+
+		if( pxEventBits != NULL )
+		{
+			pxEventBits->uxEventBits = 0;
+			vListInitialise( &( pxEventBits->xTasksWaitingForBits ) );
+
+			#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+			{
+				/* Both static and dynamic allocation can be used, so note that
+				this event group was created statically in case the event group
+				is later deleted. */
+				pxEventBits->ucStaticallyAllocated = pdTRUE;
+			}
+			#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
+
+			traceEVENT_GROUP_CREATE( pxEventBits );
+		}
+		else
+		{
+			/* xEventGroupCreateStatic should only ever be called with
+			pxEventGroupBuffer pointing to a pre-allocated (compile time
+			allocated) StaticEventGroup_t variable. */
+			traceEVENT_GROUP_CREATE_FAILED();
+		}
+
+		return pxEventBits;
+	}
+
+#endif /* configSUPPORT_STATIC_ALLOCATION */
+/*-----------------------------------------------------------*/
+
+#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+
+	EventGroupHandle_t xEventGroupCreate( void )
+	{
+	EventGroup_t *pxEventBits;
+
+		/* Allocate the event group.  Justification for MISRA deviation as
+		follows:  pvPortMalloc() always ensures returned memory blocks are
+		aligned per the requirements of the MCU stack.  In this case
+		pvPortMalloc() must return a pointer that is guaranteed to meet the
+		alignment requirements of the EventGroup_t structure - which (if you
+		follow it through) is the alignment requirements of the TickType_t type
+		(EventBits_t being of TickType_t itself).  Therefore, whenever the
+		stack alignment requirements are greater than or equal to the
+		TickType_t alignment requirements the cast is safe.  In other cases,
+		where the natural word size of the architecture is less than
+		sizeof( TickType_t ), the TickType_t variables will be accessed in two
+		or more reads operations, and the alignment requirements is only that
+		of each individual read. */
+		pxEventBits = ( EventGroup_t * ) pvPortMalloc( sizeof( EventGroup_t ) ); /*lint !e9087 !e9079 see comment above. */
+
+		if( pxEventBits != NULL )
+		{
+			pxEventBits->uxEventBits = 0;
+			vListInitialise( &( pxEventBits->xTasksWaitingForBits ) );
+
+			#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+			{
+				/* Both static and dynamic allocation can be used, so note this
+				event group was allocated statically in case the event group is
+				later deleted. */
+				pxEventBits->ucStaticallyAllocated = pdFALSE;
+			}
+			#endif /* configSUPPORT_STATIC_ALLOCATION */
+
+			traceEVENT_GROUP_CREATE( pxEventBits );
+		}
+		else
+		{
+			traceEVENT_GROUP_CREATE_FAILED(); /*lint !e9063 Else branch only exists to allow tracing and does not generate code if trace macros are not defined. */
+		}
+
+		return pxEventBits;
+	}
+
+#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
+/*-----------------------------------------------------------*/
+
+EventBits_t xEventGroupSync( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet, const EventBits_t uxBitsToWaitFor, TickType_t xTicksToWait )
+{
+EventBits_t uxOriginalBitValue, uxReturn;
+EventGroup_t *pxEventBits = xEventGroup;
+BaseType_t xAlreadyYielded;
+BaseType_t xTimeoutOccurred = pdFALSE;
+
+	configASSERT( ( uxBitsToWaitFor & eventEVENT_BITS_CONTROL_BYTES ) == 0 );
+	configASSERT( uxBitsToWaitFor != 0 );
+	#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
+	{
+		configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) );
+	}
+	#endif
+
+	vTaskSuspendAll();
+	{
+		uxOriginalBitValue = pxEventBits->uxEventBits;
+
+		( void ) xEventGroupSetBits( xEventGroup, uxBitsToSet );
+
+		if( ( ( uxOriginalBitValue | uxBitsToSet ) & uxBitsToWaitFor ) == uxBitsToWaitFor )
+		{
+			/* All the rendezvous bits are now set - no need to block. */
+			uxReturn = ( uxOriginalBitValue | uxBitsToSet );
+
+			/* Rendezvous always clear the bits.  They will have been cleared
+			already unless this is the only task in the rendezvous. */
+			pxEventBits->uxEventBits &= ~uxBitsToWaitFor;
+
+			xTicksToWait = 0;
+		}
+		else
+		{
+			if( xTicksToWait != ( TickType_t ) 0 )
+			{
+				traceEVENT_GROUP_SYNC_BLOCK( xEventGroup, uxBitsToSet, uxBitsToWaitFor );
+
+				/* Store the bits that the calling task is waiting for in the
+				task's event list item so the kernel knows when a match is
+				found.  Then enter the blocked state. */
+				vTaskPlaceOnUnorderedEventList( &( pxEventBits->xTasksWaitingForBits ), ( uxBitsToWaitFor | eventCLEAR_EVENTS_ON_EXIT_BIT | eventWAIT_FOR_ALL_BITS ), xTicksToWait );
+
+				/* This assignment is obsolete as uxReturn will get set after
+				the task unblocks, but some compilers mistakenly generate a
+				warning about uxReturn being returned without being set if the
+				assignment is omitted. */
+				uxReturn = 0;
+			}
+			else
+			{
+				/* The rendezvous bits were not set, but no block time was
+				specified - just return the current event bit value. */
+				uxReturn = pxEventBits->uxEventBits;
+				xTimeoutOccurred = pdTRUE;
+			}
+		}
+	}
+	xAlreadyYielded = xTaskResumeAll();
+
+	if( xTicksToWait != ( TickType_t ) 0 )
+	{
+		if( xAlreadyYielded == pdFALSE )
+		{
+			portYIELD_WITHIN_API();
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+
+		/* The task blocked to wait for its required bits to be set - at this
+		point either the required bits were set or the block time expired.  If
+		the required bits were set they will have been stored in the task's
+		event list item, and they should now be retrieved then cleared. */
+		uxReturn = uxTaskResetEventItemValue();
+
+		if( ( uxReturn & eventUNBLOCKED_DUE_TO_BIT_SET ) == ( EventBits_t ) 0 )
+		{
+			/* The task timed out, just return the current event bit value. */
+			taskENTER_CRITICAL();
+			{
+				uxReturn = pxEventBits->uxEventBits;
+
+				/* Although the task got here because it timed out before the
+				bits it was waiting for were set, it is possible that since it
+				unblocked another task has set the bits.  If this is the case
+				then it needs to clear the bits before exiting. */
+				if( ( uxReturn & uxBitsToWaitFor ) == uxBitsToWaitFor )
+				{
+					pxEventBits->uxEventBits &= ~uxBitsToWaitFor;
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			taskEXIT_CRITICAL();
+
+			xTimeoutOccurred = pdTRUE;
+		}
+		else
+		{
+			/* The task unblocked because the bits were set. */
+		}
+
+		/* Control bits might be set as the task had blocked should not be
+		returned. */
+		uxReturn &= ~eventEVENT_BITS_CONTROL_BYTES;
+	}
+
+	traceEVENT_GROUP_SYNC_END( xEventGroup, uxBitsToSet, uxBitsToWaitFor, xTimeoutOccurred );
+
+	/* Prevent compiler warnings when trace macros are not used. */
+	( void ) xTimeoutOccurred;
+
+	return uxReturn;
+}
+/*-----------------------------------------------------------*/
+
+EventBits_t xEventGroupWaitBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToWaitFor, const BaseType_t xClearOnExit, const BaseType_t xWaitForAllBits, TickType_t xTicksToWait )
+{
+EventGroup_t *pxEventBits = xEventGroup;
+EventBits_t uxReturn, uxControlBits = 0;
+BaseType_t xWaitConditionMet, xAlreadyYielded;
+BaseType_t xTimeoutOccurred = pdFALSE;
+
+	/* Check the user is not attempting to wait on the bits used by the kernel
+	itself, and that at least one bit is being requested. */
+	configASSERT( xEventGroup );
+	configASSERT( ( uxBitsToWaitFor & eventEVENT_BITS_CONTROL_BYTES ) == 0 );
+	configASSERT( uxBitsToWaitFor != 0 );
+	#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
+	{
+		configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) );
+	}
+	#endif
+
+	vTaskSuspendAll();
+	{
+		const EventBits_t uxCurrentEventBits = pxEventBits->uxEventBits;
+
+		/* Check to see if the wait condition is already met or not. */
+		xWaitConditionMet = prvTestWaitCondition( uxCurrentEventBits, uxBitsToWaitFor, xWaitForAllBits );
+
+		if( xWaitConditionMet != pdFALSE )
+		{
+			/* The wait condition has already been met so there is no need to
+			block. */
+			uxReturn = uxCurrentEventBits;
+			xTicksToWait = ( TickType_t ) 0;
+
+			/* Clear the wait bits if requested to do so. */
+			if( xClearOnExit != pdFALSE )
+			{
+				pxEventBits->uxEventBits &= ~uxBitsToWaitFor;
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		else if( xTicksToWait == ( TickType_t ) 0 )
+		{
+			/* The wait condition has not been met, but no block time was
+			specified, so just return the current value. */
+			uxReturn = uxCurrentEventBits;
+			xTimeoutOccurred = pdTRUE;
+		}
+		else
+		{
+			/* The task is going to block to wait for its required bits to be
+			set.  uxControlBits are used to remember the specified behaviour of
+			this call to xEventGroupWaitBits() - for use when the event bits
+			unblock the task. */
+			if( xClearOnExit != pdFALSE )
+			{
+				uxControlBits |= eventCLEAR_EVENTS_ON_EXIT_BIT;
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+
+			if( xWaitForAllBits != pdFALSE )
+			{
+				uxControlBits |= eventWAIT_FOR_ALL_BITS;
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+
+			/* Store the bits that the calling task is waiting for in the
+			task's event list item so the kernel knows when a match is
+			found.  Then enter the blocked state. */
+			vTaskPlaceOnUnorderedEventList( &( pxEventBits->xTasksWaitingForBits ), ( uxBitsToWaitFor | uxControlBits ), xTicksToWait );
+
+			/* This is obsolete as it will get set after the task unblocks, but
+			some compilers mistakenly generate a warning about the variable
+			being returned without being set if it is not done. */
+			uxReturn = 0;
+
+			traceEVENT_GROUP_WAIT_BITS_BLOCK( xEventGroup, uxBitsToWaitFor );
+		}
+	}
+	xAlreadyYielded = xTaskResumeAll();
+
+	if( xTicksToWait != ( TickType_t ) 0 )
+	{
+		if( xAlreadyYielded == pdFALSE )
+		{
+			portYIELD_WITHIN_API();
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+
+		/* The task blocked to wait for its required bits to be set - at this
+		point either the required bits were set or the block time expired.  If
+		the required bits were set they will have been stored in the task's
+		event list item, and they should now be retrieved then cleared. */
+		uxReturn = uxTaskResetEventItemValue();
+
+		if( ( uxReturn & eventUNBLOCKED_DUE_TO_BIT_SET ) == ( EventBits_t ) 0 )
+		{
+			taskENTER_CRITICAL();
+			{
+				/* The task timed out, just return the current event bit value. */
+				uxReturn = pxEventBits->uxEventBits;
+
+				/* It is possible that the event bits were updated between this
+				task leaving the Blocked state and running again. */
+				if( prvTestWaitCondition( uxReturn, uxBitsToWaitFor, xWaitForAllBits ) != pdFALSE )
+				{
+					if( xClearOnExit != pdFALSE )
+					{
+						pxEventBits->uxEventBits &= ~uxBitsToWaitFor;
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+				xTimeoutOccurred = pdTRUE;
+			}
+			taskEXIT_CRITICAL();
+		}
+		else
+		{
+			/* The task unblocked because the bits were set. */
+		}
+
+		/* The task blocked so control bits may have been set. */
+		uxReturn &= ~eventEVENT_BITS_CONTROL_BYTES;
+	}
+	traceEVENT_GROUP_WAIT_BITS_END( xEventGroup, uxBitsToWaitFor, xTimeoutOccurred );
+
+	/* Prevent compiler warnings when trace macros are not used. */
+	( void ) xTimeoutOccurred;
+
+	return uxReturn;
+}
+/*-----------------------------------------------------------*/
+
+EventBits_t xEventGroupClearBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToClear )
+{
+EventGroup_t *pxEventBits = xEventGroup;
+EventBits_t uxReturn;
+
+	/* Check the user is not attempting to clear the bits used by the kernel
+	itself. */
+	configASSERT( xEventGroup );
+	configASSERT( ( uxBitsToClear & eventEVENT_BITS_CONTROL_BYTES ) == 0 );
+
+	taskENTER_CRITICAL();
+	{
+		traceEVENT_GROUP_CLEAR_BITS( xEventGroup, uxBitsToClear );
+
+		/* The value returned is the event group value prior to the bits being
+		cleared. */
+		uxReturn = pxEventBits->uxEventBits;
+
+		/* Clear the bits. */
+		pxEventBits->uxEventBits &= ~uxBitsToClear;
+	}
+	taskEXIT_CRITICAL();
+
+	return uxReturn;
+}
+/*-----------------------------------------------------------*/
+
+#if ( ( configUSE_TRACE_FACILITY == 1 ) && ( INCLUDE_xTimerPendFunctionCall == 1 ) && ( configUSE_TIMERS == 1 ) )
+
+	BaseType_t xEventGroupClearBitsFromISR( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToClear )
+	{
+		BaseType_t xReturn;
+
+		traceEVENT_GROUP_CLEAR_BITS_FROM_ISR( xEventGroup, uxBitsToClear );
+		xReturn = xTimerPendFunctionCallFromISR( vEventGroupClearBitsCallback, ( void * ) xEventGroup, ( uint32_t ) uxBitsToClear, NULL ); /*lint !e9087 Can't avoid cast to void* as a generic callback function not specific to this use case. Callback casts back to original type so safe. */
+
+		return xReturn;
+	}
+
+#endif
+/*-----------------------------------------------------------*/
+
+EventBits_t xEventGroupGetBitsFromISR( EventGroupHandle_t xEventGroup )
+{
+UBaseType_t uxSavedInterruptStatus;
+EventGroup_t const * const pxEventBits = xEventGroup;
+EventBits_t uxReturn;
+
+	uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
+	{
+		uxReturn = pxEventBits->uxEventBits;
+	}
+	portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
+
+	return uxReturn;
+} /*lint !e818 EventGroupHandle_t is a typedef used in other functions to so can't be pointer to const. */
+/*-----------------------------------------------------------*/
+
+EventBits_t xEventGroupSetBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet )
+{
+ListItem_t *pxListItem, *pxNext;
+ListItem_t const *pxListEnd;
+List_t const * pxList;
+EventBits_t uxBitsToClear = 0, uxBitsWaitedFor, uxControlBits;
+EventGroup_t *pxEventBits = xEventGroup;
+BaseType_t xMatchFound = pdFALSE;
+
+	/* Check the user is not attempting to set the bits used by the kernel
+	itself. */
+	configASSERT( xEventGroup );
+	configASSERT( ( uxBitsToSet & eventEVENT_BITS_CONTROL_BYTES ) == 0 );
+
+	pxList = &( pxEventBits->xTasksWaitingForBits );
+	pxListEnd = listGET_END_MARKER( pxList ); /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM.  This is checked and valid. */
+	vTaskSuspendAll();
+	{
+		traceEVENT_GROUP_SET_BITS( xEventGroup, uxBitsToSet );
+
+		pxListItem = listGET_HEAD_ENTRY( pxList );
+
+		/* Set the bits. */
+		pxEventBits->uxEventBits |= uxBitsToSet;
+
+		/* See if the new bit value should unblock any tasks. */
+		while( pxListItem != pxListEnd )
+		{
+			pxNext = listGET_NEXT( pxListItem );
+			uxBitsWaitedFor = listGET_LIST_ITEM_VALUE( pxListItem );
+			xMatchFound = pdFALSE;
+
+			/* Split the bits waited for from the control bits. */
+			uxControlBits = uxBitsWaitedFor & eventEVENT_BITS_CONTROL_BYTES;
+			uxBitsWaitedFor &= ~eventEVENT_BITS_CONTROL_BYTES;
+
+			if( ( uxControlBits & eventWAIT_FOR_ALL_BITS ) == ( EventBits_t ) 0 )
+			{
+				/* Just looking for single bit being set. */
+				if( ( uxBitsWaitedFor & pxEventBits->uxEventBits ) != ( EventBits_t ) 0 )
+				{
+					xMatchFound = pdTRUE;
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else if( ( uxBitsWaitedFor & pxEventBits->uxEventBits ) == uxBitsWaitedFor )
+			{
+				/* All bits are set. */
+				xMatchFound = pdTRUE;
+			}
+			else
+			{
+				/* Need all bits to be set, but not all the bits were set. */
+			}
+
+			if( xMatchFound != pdFALSE )
+			{
+				/* The bits match.  Should the bits be cleared on exit? */
+				if( ( uxControlBits & eventCLEAR_EVENTS_ON_EXIT_BIT ) != ( EventBits_t ) 0 )
+				{
+					uxBitsToClear |= uxBitsWaitedFor;
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+
+				/* Store the actual event flag value in the task's event list
+				item before removing the task from the event list.  The
+				eventUNBLOCKED_DUE_TO_BIT_SET bit is set so the task knows
+				that is was unblocked due to its required bits matching, rather
+				than because it timed out. */
+				vTaskRemoveFromUnorderedEventList( pxListItem, pxEventBits->uxEventBits | eventUNBLOCKED_DUE_TO_BIT_SET );
+			}
+
+			/* Move onto the next list item.  Note pxListItem->pxNext is not
+			used here as the list item may have been removed from the event list
+			and inserted into the ready/pending reading list. */
+			pxListItem = pxNext;
+		}
+
+		/* Clear any bits that matched when the eventCLEAR_EVENTS_ON_EXIT_BIT
+		bit was set in the control word. */
+		pxEventBits->uxEventBits &= ~uxBitsToClear;
+	}
+	( void ) xTaskResumeAll();
+
+	return pxEventBits->uxEventBits;
+}
+/*-----------------------------------------------------------*/
+
+void vEventGroupDelete( EventGroupHandle_t xEventGroup )
+{
+EventGroup_t *pxEventBits = xEventGroup;
+const List_t *pxTasksWaitingForBits = &( pxEventBits->xTasksWaitingForBits );
+
+	vTaskSuspendAll();
+	{
+		traceEVENT_GROUP_DELETE( xEventGroup );
+
+		while( listCURRENT_LIST_LENGTH( pxTasksWaitingForBits ) > ( UBaseType_t ) 0 )
+		{
+			/* Unblock the task, returning 0 as the event list is being deleted
+			and cannot therefore have any bits set. */
+			configASSERT( pxTasksWaitingForBits->xListEnd.pxNext != ( const ListItem_t * ) &( pxTasksWaitingForBits->xListEnd ) );
+			vTaskRemoveFromUnorderedEventList( pxTasksWaitingForBits->xListEnd.pxNext, eventUNBLOCKED_DUE_TO_BIT_SET );
+		}
+
+		#if( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 0 ) )
+		{
+			/* The event group can only have been allocated dynamically - free
+			it again. */
+			vPortFree( pxEventBits );
+		}
+		#elif( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) )
+		{
+			/* The event group could have been allocated statically or
+			dynamically, so check before attempting to free the memory. */
+			if( pxEventBits->ucStaticallyAllocated == ( uint8_t ) pdFALSE )
+			{
+				vPortFree( pxEventBits );
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
+	}
+	( void ) xTaskResumeAll();
+}
+/*-----------------------------------------------------------*/
+
+/* For internal use only - execute a 'set bits' command that was pended from
+an interrupt. */
+void vEventGroupSetBitsCallback( void *pvEventGroup, const uint32_t ulBitsToSet )
+{
+	( void ) xEventGroupSetBits( pvEventGroup, ( EventBits_t ) ulBitsToSet ); /*lint !e9079 Can't avoid cast to void* as a generic timer callback prototype. Callback casts back to original type so safe. */
+}
+/*-----------------------------------------------------------*/
+
+/* For internal use only - execute a 'clear bits' command that was pended from
+an interrupt. */
+void vEventGroupClearBitsCallback( void *pvEventGroup, const uint32_t ulBitsToClear )
+{
+	( void ) xEventGroupClearBits( pvEventGroup, ( EventBits_t ) ulBitsToClear ); /*lint !e9079 Can't avoid cast to void* as a generic timer callback prototype. Callback casts back to original type so safe. */
+}
+/*-----------------------------------------------------------*/
+
+static BaseType_t prvTestWaitCondition( const EventBits_t uxCurrentEventBits, const EventBits_t uxBitsToWaitFor, const BaseType_t xWaitForAllBits )
+{
+BaseType_t xWaitConditionMet = pdFALSE;
+
+	if( xWaitForAllBits == pdFALSE )
+	{
+		/* Task only has to wait for one bit within uxBitsToWaitFor to be
+		set.  Is one already set? */
+		if( ( uxCurrentEventBits & uxBitsToWaitFor ) != ( EventBits_t ) 0 )
+		{
+			xWaitConditionMet = pdTRUE;
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+	else
+	{
+		/* Task has to wait for all the bits in uxBitsToWaitFor to be set.
+		Are they set already? */
+		if( ( uxCurrentEventBits & uxBitsToWaitFor ) == uxBitsToWaitFor )
+		{
+			xWaitConditionMet = pdTRUE;
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+
+	return xWaitConditionMet;
+}
+/*-----------------------------------------------------------*/
+
+#if ( ( configUSE_TRACE_FACILITY == 1 ) && ( INCLUDE_xTimerPendFunctionCall == 1 ) && ( configUSE_TIMERS == 1 ) )
+
+	BaseType_t xEventGroupSetBitsFromISR( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet, BaseType_t *pxHigherPriorityTaskWoken )
+	{
+	BaseType_t xReturn;
+
+		traceEVENT_GROUP_SET_BITS_FROM_ISR( xEventGroup, uxBitsToSet );
+		xReturn = xTimerPendFunctionCallFromISR( vEventGroupSetBitsCallback, ( void * ) xEventGroup, ( uint32_t ) uxBitsToSet, pxHigherPriorityTaskWoken ); /*lint !e9087 Can't avoid cast to void* as a generic callback function not specific to this use case. Callback casts back to original type so safe. */
+
+		return xReturn;
+	}
+
+#endif
+/*-----------------------------------------------------------*/
+
+#if (configUSE_TRACE_FACILITY == 1)
+
+	UBaseType_t uxEventGroupGetNumber( void* xEventGroup )
+	{
+	UBaseType_t xReturn;
+	EventGroup_t const *pxEventBits = ( EventGroup_t * ) xEventGroup; /*lint !e9087 !e9079 EventGroupHandle_t is a pointer to an EventGroup_t, but EventGroupHandle_t is kept opaque outside of this file for data hiding purposes. */
+
+		if( xEventGroup == NULL )
+		{
+			xReturn = 0;
+		}
+		else
+		{
+			xReturn = pxEventBits->uxEventGroupNumber;
+		}
+
+		return xReturn;
+	}
+
+#endif /* configUSE_TRACE_FACILITY */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TRACE_FACILITY == 1 )
+
+	void vEventGroupSetNumber( void * xEventGroup, UBaseType_t uxEventGroupNumber )
+	{
+		( ( EventGroup_t * ) xEventGroup )->uxEventGroupNumber = uxEventGroupNumber; /*lint !e9087 !e9079 EventGroupHandle_t is a pointer to an EventGroup_t, but EventGroupHandle_t is kept opaque outside of this file for data hiding purposes. */
+	}
+
+#endif /* configUSE_TRACE_FACILITY */
+/*-----------------------------------------------------------*/
+
+
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h b/Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h
new file mode 100644
index 0000000..5a1a497
--- /dev/null
+++ b/Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h
@@ -0,0 +1,1295 @@
+/*
+ * FreeRTOS Kernel V10.3.1
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef INC_FREERTOS_H
+#define INC_FREERTOS_H
+
+/*
+ * Include the generic headers required for the FreeRTOS port being used.
+ */
+#include <stddef.h>
+
+/*
+ * If stdint.h cannot be located then:
+ *   + If using GCC ensure the -nostdint options is *not* being used.
+ *   + Ensure the project's include path includes the directory in which your
+ *     compiler stores stdint.h.
+ *   + Set any compiler options necessary for it to support C99, as technically
+ *     stdint.h is only mandatory with C99 (FreeRTOS does not require C99 in any
+ *     other way).
+ *   + The FreeRTOS download includes a simple stdint.h definition that can be
+ *     used in cases where none is provided by the compiler.  The files only
+ *     contains the typedefs required to build FreeRTOS.  Read the instructions
+ *     in FreeRTOS/source/stdint.readme for more information.
+ */
+#include <stdint.h> /* READ COMMENT ABOVE. */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Application specific configuration options. */
+#include "FreeRTOSConfig.h"
+
+/* Basic FreeRTOS definitions. */
+#include "projdefs.h"
+
+/* Definitions specific to the port being used. */
+#include "portable.h"
+
+/* Must be defaulted before configUSE_NEWLIB_REENTRANT is used below. */
+#ifndef configUSE_NEWLIB_REENTRANT
+	#define configUSE_NEWLIB_REENTRANT 0
+#endif
+
+/* Required if struct _reent is used. */
+#if ( configUSE_NEWLIB_REENTRANT == 1 )
+	#include <reent.h>
+#endif
+/*
+ * Check all the required application specific macros have been defined.
+ * These macros are application specific and (as downloaded) are defined
+ * within FreeRTOSConfig.h.
+ */
+
+#ifndef configMINIMAL_STACK_SIZE
+	#error Missing definition:  configMINIMAL_STACK_SIZE must be defined in FreeRTOSConfig.h.  configMINIMAL_STACK_SIZE defines the size (in words) of the stack allocated to the idle task.  Refer to the demo project provided for your port for a suitable value.
+#endif
+
+#ifndef configMAX_PRIORITIES
+	#error Missing definition:  configMAX_PRIORITIES must be defined in FreeRTOSConfig.h.  See the Configuration section of the FreeRTOS API documentation for details.
+#endif
+
+#if configMAX_PRIORITIES < 1
+	#error configMAX_PRIORITIES must be defined to be greater than or equal to 1.
+#endif
+
+#ifndef configUSE_PREEMPTION
+	#error Missing definition:  configUSE_PREEMPTION must be defined in FreeRTOSConfig.h as either 1 or 0.  See the Configuration section of the FreeRTOS API documentation for details.
+#endif
+
+#ifndef configUSE_IDLE_HOOK
+	#error Missing definition:  configUSE_IDLE_HOOK must be defined in FreeRTOSConfig.h as either 1 or 0.  See the Configuration section of the FreeRTOS API documentation for details.
+#endif
+
+#ifndef configUSE_TICK_HOOK
+	#error Missing definition:  configUSE_TICK_HOOK must be defined in FreeRTOSConfig.h as either 1 or 0.  See the Configuration section of the FreeRTOS API documentation for details.
+#endif
+
+#ifndef configUSE_16_BIT_TICKS
+	#error Missing definition:  configUSE_16_BIT_TICKS must be defined in FreeRTOSConfig.h as either 1 or 0.  See the Configuration section of the FreeRTOS API documentation for details.
+#endif
+
+#ifndef configUSE_CO_ROUTINES
+	#define configUSE_CO_ROUTINES 0
+#endif
+
+#ifndef INCLUDE_vTaskPrioritySet
+	#define INCLUDE_vTaskPrioritySet 0
+#endif
+
+#ifndef INCLUDE_uxTaskPriorityGet
+	#define INCLUDE_uxTaskPriorityGet 0
+#endif
+
+#ifndef INCLUDE_vTaskDelete
+	#define INCLUDE_vTaskDelete 0
+#endif
+
+#ifndef INCLUDE_vTaskSuspend
+	#define INCLUDE_vTaskSuspend 0
+#endif
+
+#ifndef INCLUDE_vTaskDelayUntil
+	#define INCLUDE_vTaskDelayUntil 0
+#endif
+
+#ifndef INCLUDE_vTaskDelay
+	#define INCLUDE_vTaskDelay 0
+#endif
+
+#ifndef INCLUDE_xTaskGetIdleTaskHandle
+	#define INCLUDE_xTaskGetIdleTaskHandle 0
+#endif
+
+#ifndef INCLUDE_xTaskAbortDelay
+	#define INCLUDE_xTaskAbortDelay 0
+#endif
+
+#ifndef INCLUDE_xQueueGetMutexHolder
+	#define INCLUDE_xQueueGetMutexHolder 0
+#endif
+
+#ifndef INCLUDE_xSemaphoreGetMutexHolder
+	#define INCLUDE_xSemaphoreGetMutexHolder INCLUDE_xQueueGetMutexHolder
+#endif
+
+#ifndef INCLUDE_xTaskGetHandle
+	#define INCLUDE_xTaskGetHandle 0
+#endif
+
+#ifndef INCLUDE_uxTaskGetStackHighWaterMark
+	#define INCLUDE_uxTaskGetStackHighWaterMark 0
+#endif
+
+#ifndef INCLUDE_uxTaskGetStackHighWaterMark2
+	#define INCLUDE_uxTaskGetStackHighWaterMark2 0
+#endif
+
+#ifndef INCLUDE_eTaskGetState
+	#define INCLUDE_eTaskGetState 0
+#endif
+
+#ifndef INCLUDE_xTaskResumeFromISR
+	#define INCLUDE_xTaskResumeFromISR 1
+#endif
+
+#ifndef INCLUDE_xTimerPendFunctionCall
+	#define INCLUDE_xTimerPendFunctionCall 0
+#endif
+
+#ifndef INCLUDE_xTaskGetSchedulerState
+	#define INCLUDE_xTaskGetSchedulerState 0
+#endif
+
+#ifndef INCLUDE_xTaskGetCurrentTaskHandle
+	#define INCLUDE_xTaskGetCurrentTaskHandle 0
+#endif
+
+#if configUSE_CO_ROUTINES != 0
+	#ifndef configMAX_CO_ROUTINE_PRIORITIES
+		#error configMAX_CO_ROUTINE_PRIORITIES must be greater than or equal to 1.
+	#endif
+#endif
+
+#ifndef configUSE_DAEMON_TASK_STARTUP_HOOK
+	#define configUSE_DAEMON_TASK_STARTUP_HOOK 0
+#endif
+
+#ifndef configUSE_APPLICATION_TASK_TAG
+	#define configUSE_APPLICATION_TASK_TAG 0
+#endif
+
+#ifndef configNUM_THREAD_LOCAL_STORAGE_POINTERS
+	#define configNUM_THREAD_LOCAL_STORAGE_POINTERS 0
+#endif
+
+#ifndef configUSE_RECURSIVE_MUTEXES
+	#define configUSE_RECURSIVE_MUTEXES 0
+#endif
+
+#ifndef configUSE_MUTEXES
+	#define configUSE_MUTEXES 0
+#endif
+
+#ifndef configUSE_TIMERS
+	#define configUSE_TIMERS 0
+#endif
+
+#ifndef configUSE_COUNTING_SEMAPHORES
+	#define configUSE_COUNTING_SEMAPHORES 0
+#endif
+
+#ifndef configUSE_ALTERNATIVE_API
+	#define configUSE_ALTERNATIVE_API 0
+#endif
+
+#ifndef portCRITICAL_NESTING_IN_TCB
+	#define portCRITICAL_NESTING_IN_TCB 0
+#endif
+
+#ifndef configMAX_TASK_NAME_LEN
+	#define configMAX_TASK_NAME_LEN 16
+#endif
+
+#ifndef configIDLE_SHOULD_YIELD
+	#define configIDLE_SHOULD_YIELD		1
+#endif
+
+#if configMAX_TASK_NAME_LEN < 1
+	#error configMAX_TASK_NAME_LEN must be set to a minimum of 1 in FreeRTOSConfig.h
+#endif
+
+#ifndef configASSERT
+	#define configASSERT( x )
+	#define configASSERT_DEFINED 0
+#else
+	#define configASSERT_DEFINED 1
+#endif
+
+/* configPRECONDITION should be defined as configASSERT.
+The CBMC proofs need a way to track assumptions and assertions.
+A configPRECONDITION statement should express an implicit invariant or
+assumption made.  A configASSERT statement should express an invariant that must
+hold explicit before calling the code. */
+#ifndef configPRECONDITION
+	#define configPRECONDITION( X ) configASSERT(X)
+	#define configPRECONDITION_DEFINED 0
+#else
+	#define configPRECONDITION_DEFINED 1
+#endif
+
+#ifndef portMEMORY_BARRIER
+	#define portMEMORY_BARRIER()
+#endif
+
+#ifndef portSOFTWARE_BARRIER
+	#define portSOFTWARE_BARRIER()
+#endif
+
+/* The timers module relies on xTaskGetSchedulerState(). */
+#if configUSE_TIMERS == 1
+
+	#ifndef configTIMER_TASK_PRIORITY
+		#error If configUSE_TIMERS is set to 1 then configTIMER_TASK_PRIORITY must also be defined.
+	#endif /* configTIMER_TASK_PRIORITY */
+
+	#ifndef configTIMER_QUEUE_LENGTH
+		#error If configUSE_TIMERS is set to 1 then configTIMER_QUEUE_LENGTH must also be defined.
+	#endif /* configTIMER_QUEUE_LENGTH */
+
+	#ifndef configTIMER_TASK_STACK_DEPTH
+		#error If configUSE_TIMERS is set to 1 then configTIMER_TASK_STACK_DEPTH must also be defined.
+	#endif /* configTIMER_TASK_STACK_DEPTH */
+
+#endif /* configUSE_TIMERS */
+
+#ifndef portSET_INTERRUPT_MASK_FROM_ISR
+	#define portSET_INTERRUPT_MASK_FROM_ISR() 0
+#endif
+
+#ifndef portCLEAR_INTERRUPT_MASK_FROM_ISR
+	#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedStatusValue ) ( void ) uxSavedStatusValue
+#endif
+
+#ifndef portCLEAN_UP_TCB
+	#define portCLEAN_UP_TCB( pxTCB ) ( void ) pxTCB
+#endif
+
+#ifndef portPRE_TASK_DELETE_HOOK
+	#define portPRE_TASK_DELETE_HOOK( pvTaskToDelete, pxYieldPending )
+#endif
+
+#ifndef portSETUP_TCB
+	#define portSETUP_TCB( pxTCB ) ( void ) pxTCB
+#endif
+
+#ifndef configQUEUE_REGISTRY_SIZE
+	#define configQUEUE_REGISTRY_SIZE 0U
+#endif
+
+#if ( configQUEUE_REGISTRY_SIZE < 1 )
+	#define vQueueAddToRegistry( xQueue, pcName )
+	#define vQueueUnregisterQueue( xQueue )
+	#define pcQueueGetName( xQueue )
+#endif
+
+#ifndef portPOINTER_SIZE_TYPE
+	#define portPOINTER_SIZE_TYPE uint32_t
+#endif
+
+/* Remove any unused trace macros. */
+#ifndef traceSTART
+	/* Used to perform any necessary initialisation - for example, open a file
+	into which trace is to be written. */
+	#define traceSTART()
+#endif
+
+#ifndef traceEND
+	/* Use to close a trace, for example close a file into which trace has been
+	written. */
+	#define traceEND()
+#endif
+
+#ifndef traceTASK_SWITCHED_IN
+	/* Called after a task has been selected to run.  pxCurrentTCB holds a pointer
+	to the task control block of the selected task. */
+	#define traceTASK_SWITCHED_IN()
+#endif
+
+#ifndef traceINCREASE_TICK_COUNT
+	/* Called before stepping the tick count after waking from tickless idle
+	sleep. */
+	#define traceINCREASE_TICK_COUNT( x )
+#endif
+
+#ifndef traceLOW_POWER_IDLE_BEGIN
+	/* Called immediately before entering tickless idle. */
+	#define traceLOW_POWER_IDLE_BEGIN()
+#endif
+
+#ifndef	traceLOW_POWER_IDLE_END
+	/* Called when returning to the Idle task after a tickless idle. */
+	#define traceLOW_POWER_IDLE_END()
+#endif
+
+#ifndef traceTASK_SWITCHED_OUT
+	/* Called before a task has been selected to run.  pxCurrentTCB holds a pointer
+	to the task control block of the task being switched out. */
+	#define traceTASK_SWITCHED_OUT()
+#endif
+
+#ifndef traceTASK_PRIORITY_INHERIT
+	/* Called when a task attempts to take a mutex that is already held by a
+	lower priority task.  pxTCBOfMutexHolder is a pointer to the TCB of the task
+	that holds the mutex.  uxInheritedPriority is the priority the mutex holder
+	will inherit (the priority of the task that is attempting to obtain the
+	muted. */
+	#define traceTASK_PRIORITY_INHERIT( pxTCBOfMutexHolder, uxInheritedPriority )
+#endif
+
+#ifndef traceTASK_PRIORITY_DISINHERIT
+	/* Called when a task releases a mutex, the holding of which had resulted in
+	the task inheriting the priority of a higher priority task.
+	pxTCBOfMutexHolder is a pointer to the TCB of the task that is releasing the
+	mutex.  uxOriginalPriority is the task's configured (base) priority. */
+	#define traceTASK_PRIORITY_DISINHERIT( pxTCBOfMutexHolder, uxOriginalPriority )
+#endif
+
+#ifndef traceBLOCKING_ON_QUEUE_RECEIVE
+	/* Task is about to block because it cannot read from a
+	queue/mutex/semaphore.  pxQueue is a pointer to the queue/mutex/semaphore
+	upon which the read was attempted.  pxCurrentTCB points to the TCB of the
+	task that attempted the read. */
+	#define traceBLOCKING_ON_QUEUE_RECEIVE( pxQueue )
+#endif
+
+#ifndef traceBLOCKING_ON_QUEUE_PEEK
+	/* Task is about to block because it cannot read from a
+	queue/mutex/semaphore.  pxQueue is a pointer to the queue/mutex/semaphore
+	upon which the read was attempted.  pxCurrentTCB points to the TCB of the
+	task that attempted the read. */
+	#define traceBLOCKING_ON_QUEUE_PEEK( pxQueue )
+#endif
+
+#ifndef traceBLOCKING_ON_QUEUE_SEND
+	/* Task is about to block because it cannot write to a
+	queue/mutex/semaphore.  pxQueue is a pointer to the queue/mutex/semaphore
+	upon which the write was attempted.  pxCurrentTCB points to the TCB of the
+	task that attempted the write. */
+	#define traceBLOCKING_ON_QUEUE_SEND( pxQueue )
+#endif
+
+#ifndef configCHECK_FOR_STACK_OVERFLOW
+	#define configCHECK_FOR_STACK_OVERFLOW 0
+#endif
+
+#ifndef configRECORD_STACK_HIGH_ADDRESS
+	#define configRECORD_STACK_HIGH_ADDRESS 0
+#endif
+
+#ifndef configINCLUDE_FREERTOS_TASK_C_ADDITIONS_H
+	#define configINCLUDE_FREERTOS_TASK_C_ADDITIONS_H 0
+#endif
+
+/* The following event macros are embedded in the kernel API calls. */
+
+#ifndef traceMOVED_TASK_TO_READY_STATE
+	#define traceMOVED_TASK_TO_READY_STATE( pxTCB )
+#endif
+
+#ifndef tracePOST_MOVED_TASK_TO_READY_STATE
+	#define tracePOST_MOVED_TASK_TO_READY_STATE( pxTCB )
+#endif
+
+#ifndef traceQUEUE_CREATE
+	#define traceQUEUE_CREATE( pxNewQueue )
+#endif
+
+#ifndef traceQUEUE_CREATE_FAILED
+	#define traceQUEUE_CREATE_FAILED( ucQueueType )
+#endif
+
+#ifndef traceCREATE_MUTEX
+	#define traceCREATE_MUTEX( pxNewQueue )
+#endif
+
+#ifndef traceCREATE_MUTEX_FAILED
+	#define traceCREATE_MUTEX_FAILED()
+#endif
+
+#ifndef traceGIVE_MUTEX_RECURSIVE
+	#define traceGIVE_MUTEX_RECURSIVE( pxMutex )
+#endif
+
+#ifndef traceGIVE_MUTEX_RECURSIVE_FAILED
+	#define traceGIVE_MUTEX_RECURSIVE_FAILED( pxMutex )
+#endif
+
+#ifndef traceTAKE_MUTEX_RECURSIVE
+	#define traceTAKE_MUTEX_RECURSIVE( pxMutex )
+#endif
+
+#ifndef traceTAKE_MUTEX_RECURSIVE_FAILED
+	#define traceTAKE_MUTEX_RECURSIVE_FAILED( pxMutex )
+#endif
+
+#ifndef traceCREATE_COUNTING_SEMAPHORE
+	#define traceCREATE_COUNTING_SEMAPHORE()
+#endif
+
+#ifndef traceCREATE_COUNTING_SEMAPHORE_FAILED
+	#define traceCREATE_COUNTING_SEMAPHORE_FAILED()
+#endif
+
+#ifndef traceQUEUE_SEND
+	#define traceQUEUE_SEND( pxQueue )
+#endif
+
+#ifndef traceQUEUE_SEND_FAILED
+	#define traceQUEUE_SEND_FAILED( pxQueue )
+#endif
+
+#ifndef traceQUEUE_RECEIVE
+	#define traceQUEUE_RECEIVE( pxQueue )
+#endif
+
+#ifndef traceQUEUE_PEEK
+	#define traceQUEUE_PEEK( pxQueue )
+#endif
+
+#ifndef traceQUEUE_PEEK_FAILED
+	#define traceQUEUE_PEEK_FAILED( pxQueue )
+#endif
+
+#ifndef traceQUEUE_PEEK_FROM_ISR
+	#define traceQUEUE_PEEK_FROM_ISR( pxQueue )
+#endif
+
+#ifndef traceQUEUE_RECEIVE_FAILED
+	#define traceQUEUE_RECEIVE_FAILED( pxQueue )
+#endif
+
+#ifndef traceQUEUE_SEND_FROM_ISR
+	#define traceQUEUE_SEND_FROM_ISR( pxQueue )
+#endif
+
+#ifndef traceQUEUE_SEND_FROM_ISR_FAILED
+	#define traceQUEUE_SEND_FROM_ISR_FAILED( pxQueue )
+#endif
+
+#ifndef traceQUEUE_RECEIVE_FROM_ISR
+	#define traceQUEUE_RECEIVE_FROM_ISR( pxQueue )
+#endif
+
+#ifndef traceQUEUE_RECEIVE_FROM_ISR_FAILED
+	#define traceQUEUE_RECEIVE_FROM_ISR_FAILED( pxQueue )
+#endif
+
+#ifndef traceQUEUE_PEEK_FROM_ISR_FAILED
+	#define traceQUEUE_PEEK_FROM_ISR_FAILED( pxQueue )
+#endif
+
+#ifndef traceQUEUE_DELETE
+	#define traceQUEUE_DELETE( pxQueue )
+#endif
+
+#ifndef traceTASK_CREATE
+	#define traceTASK_CREATE( pxNewTCB )
+#endif
+
+#ifndef traceTASK_CREATE_FAILED
+	#define traceTASK_CREATE_FAILED()
+#endif
+
+#ifndef traceTASK_DELETE
+	#define traceTASK_DELETE( pxTaskToDelete )
+#endif
+
+#ifndef traceTASK_DELAY_UNTIL
+	#define traceTASK_DELAY_UNTIL( x )
+#endif
+
+#ifndef traceTASK_DELAY
+	#define traceTASK_DELAY()
+#endif
+
+#ifndef traceTASK_PRIORITY_SET
+	#define traceTASK_PRIORITY_SET( pxTask, uxNewPriority )
+#endif
+
+#ifndef traceTASK_SUSPEND
+	#define traceTASK_SUSPEND( pxTaskToSuspend )
+#endif
+
+#ifndef traceTASK_RESUME
+	#define traceTASK_RESUME( pxTaskToResume )
+#endif
+
+#ifndef traceTASK_RESUME_FROM_ISR
+	#define traceTASK_RESUME_FROM_ISR( pxTaskToResume )
+#endif
+
+#ifndef traceTASK_INCREMENT_TICK
+	#define traceTASK_INCREMENT_TICK( xTickCount )
+#endif
+
+#ifndef traceTIMER_CREATE
+	#define traceTIMER_CREATE( pxNewTimer )
+#endif
+
+#ifndef traceTIMER_CREATE_FAILED
+	#define traceTIMER_CREATE_FAILED()
+#endif
+
+#ifndef traceTIMER_COMMAND_SEND
+	#define traceTIMER_COMMAND_SEND( xTimer, xMessageID, xMessageValueValue, xReturn )
+#endif
+
+#ifndef traceTIMER_EXPIRED
+	#define traceTIMER_EXPIRED( pxTimer )
+#endif
+
+#ifndef traceTIMER_COMMAND_RECEIVED
+	#define traceTIMER_COMMAND_RECEIVED( pxTimer, xMessageID, xMessageValue )
+#endif
+
+#ifndef traceMALLOC
+    #define traceMALLOC( pvAddress, uiSize )
+#endif
+
+#ifndef traceFREE
+    #define traceFREE( pvAddress, uiSize )
+#endif
+
+#ifndef traceEVENT_GROUP_CREATE
+	#define traceEVENT_GROUP_CREATE( xEventGroup )
+#endif
+
+#ifndef traceEVENT_GROUP_CREATE_FAILED
+	#define traceEVENT_GROUP_CREATE_FAILED()
+#endif
+
+#ifndef traceEVENT_GROUP_SYNC_BLOCK
+	#define traceEVENT_GROUP_SYNC_BLOCK( xEventGroup, uxBitsToSet, uxBitsToWaitFor )
+#endif
+
+#ifndef traceEVENT_GROUP_SYNC_END
+	#define traceEVENT_GROUP_SYNC_END( xEventGroup, uxBitsToSet, uxBitsToWaitFor, xTimeoutOccurred ) ( void ) xTimeoutOccurred
+#endif
+
+#ifndef traceEVENT_GROUP_WAIT_BITS_BLOCK
+	#define traceEVENT_GROUP_WAIT_BITS_BLOCK( xEventGroup, uxBitsToWaitFor )
+#endif
+
+#ifndef traceEVENT_GROUP_WAIT_BITS_END
+	#define traceEVENT_GROUP_WAIT_BITS_END( xEventGroup, uxBitsToWaitFor, xTimeoutOccurred ) ( void ) xTimeoutOccurred
+#endif
+
+#ifndef traceEVENT_GROUP_CLEAR_BITS
+	#define traceEVENT_GROUP_CLEAR_BITS( xEventGroup, uxBitsToClear )
+#endif
+
+#ifndef traceEVENT_GROUP_CLEAR_BITS_FROM_ISR
+	#define traceEVENT_GROUP_CLEAR_BITS_FROM_ISR( xEventGroup, uxBitsToClear )
+#endif
+
+#ifndef traceEVENT_GROUP_SET_BITS
+	#define traceEVENT_GROUP_SET_BITS( xEventGroup, uxBitsToSet )
+#endif
+
+#ifndef traceEVENT_GROUP_SET_BITS_FROM_ISR
+	#define traceEVENT_GROUP_SET_BITS_FROM_ISR( xEventGroup, uxBitsToSet )
+#endif
+
+#ifndef traceEVENT_GROUP_DELETE
+	#define traceEVENT_GROUP_DELETE( xEventGroup )
+#endif
+
+#ifndef tracePEND_FUNC_CALL
+	#define tracePEND_FUNC_CALL(xFunctionToPend, pvParameter1, ulParameter2, ret)
+#endif
+
+#ifndef tracePEND_FUNC_CALL_FROM_ISR
+	#define tracePEND_FUNC_CALL_FROM_ISR(xFunctionToPend, pvParameter1, ulParameter2, ret)
+#endif
+
+#ifndef traceQUEUE_REGISTRY_ADD
+	#define traceQUEUE_REGISTRY_ADD(xQueue, pcQueueName)
+#endif
+
+#ifndef traceTASK_NOTIFY_TAKE_BLOCK
+	#define traceTASK_NOTIFY_TAKE_BLOCK()
+#endif
+
+#ifndef traceTASK_NOTIFY_TAKE
+	#define traceTASK_NOTIFY_TAKE()
+#endif
+
+#ifndef traceTASK_NOTIFY_WAIT_BLOCK
+	#define traceTASK_NOTIFY_WAIT_BLOCK()
+#endif
+
+#ifndef traceTASK_NOTIFY_WAIT
+	#define traceTASK_NOTIFY_WAIT()
+#endif
+
+#ifndef traceTASK_NOTIFY
+	#define traceTASK_NOTIFY()
+#endif
+
+#ifndef traceTASK_NOTIFY_FROM_ISR
+	#define traceTASK_NOTIFY_FROM_ISR()
+#endif
+
+#ifndef traceTASK_NOTIFY_GIVE_FROM_ISR
+	#define traceTASK_NOTIFY_GIVE_FROM_ISR()
+#endif
+
+#ifndef traceSTREAM_BUFFER_CREATE_FAILED
+	#define traceSTREAM_BUFFER_CREATE_FAILED( xIsMessageBuffer )
+#endif
+
+#ifndef traceSTREAM_BUFFER_CREATE_STATIC_FAILED
+	#define traceSTREAM_BUFFER_CREATE_STATIC_FAILED( xReturn, xIsMessageBuffer )
+#endif
+
+#ifndef traceSTREAM_BUFFER_CREATE
+	#define traceSTREAM_BUFFER_CREATE( pxStreamBuffer, xIsMessageBuffer )
+#endif
+
+#ifndef traceSTREAM_BUFFER_DELETE
+	#define traceSTREAM_BUFFER_DELETE( xStreamBuffer )
+#endif
+
+#ifndef traceSTREAM_BUFFER_RESET
+	#define traceSTREAM_BUFFER_RESET( xStreamBuffer )
+#endif
+
+#ifndef traceBLOCKING_ON_STREAM_BUFFER_SEND
+	#define traceBLOCKING_ON_STREAM_BUFFER_SEND( xStreamBuffer )
+#endif
+
+#ifndef traceSTREAM_BUFFER_SEND
+	#define traceSTREAM_BUFFER_SEND( xStreamBuffer, xBytesSent )
+#endif
+
+#ifndef traceSTREAM_BUFFER_SEND_FAILED
+	#define traceSTREAM_BUFFER_SEND_FAILED( xStreamBuffer )
+#endif
+
+#ifndef traceSTREAM_BUFFER_SEND_FROM_ISR
+	#define traceSTREAM_BUFFER_SEND_FROM_ISR( xStreamBuffer, xBytesSent )
+#endif
+
+#ifndef traceBLOCKING_ON_STREAM_BUFFER_RECEIVE
+	#define traceBLOCKING_ON_STREAM_BUFFER_RECEIVE( xStreamBuffer )
+#endif
+
+#ifndef traceSTREAM_BUFFER_RECEIVE
+	#define traceSTREAM_BUFFER_RECEIVE( xStreamBuffer, xReceivedLength )
+#endif
+
+#ifndef traceSTREAM_BUFFER_RECEIVE_FAILED
+	#define traceSTREAM_BUFFER_RECEIVE_FAILED( xStreamBuffer )
+#endif
+
+#ifndef traceSTREAM_BUFFER_RECEIVE_FROM_ISR
+	#define traceSTREAM_BUFFER_RECEIVE_FROM_ISR( xStreamBuffer, xReceivedLength )
+#endif
+
+#ifndef configGENERATE_RUN_TIME_STATS
+	#define configGENERATE_RUN_TIME_STATS 0
+#endif
+
+#if ( configGENERATE_RUN_TIME_STATS == 1 )
+
+	#ifndef portCONFIGURE_TIMER_FOR_RUN_TIME_STATS
+		#error If configGENERATE_RUN_TIME_STATS is defined then portCONFIGURE_TIMER_FOR_RUN_TIME_STATS must also be defined.  portCONFIGURE_TIMER_FOR_RUN_TIME_STATS should call a port layer function to setup a peripheral timer/counter that can then be used as the run time counter time base.
+	#endif /* portCONFIGURE_TIMER_FOR_RUN_TIME_STATS */
+
+	#ifndef portGET_RUN_TIME_COUNTER_VALUE
+		#ifndef portALT_GET_RUN_TIME_COUNTER_VALUE
+			#error If configGENERATE_RUN_TIME_STATS is defined then either portGET_RUN_TIME_COUNTER_VALUE or portALT_GET_RUN_TIME_COUNTER_VALUE must also be defined.  See the examples provided and the FreeRTOS web site for more information.
+		#endif /* portALT_GET_RUN_TIME_COUNTER_VALUE */
+	#endif /* portGET_RUN_TIME_COUNTER_VALUE */
+
+#endif /* configGENERATE_RUN_TIME_STATS */
+
+#ifndef portCONFIGURE_TIMER_FOR_RUN_TIME_STATS
+	#define portCONFIGURE_TIMER_FOR_RUN_TIME_STATS()
+#endif
+
+#ifndef configUSE_MALLOC_FAILED_HOOK
+	#define configUSE_MALLOC_FAILED_HOOK 0
+#endif
+
+#ifndef portPRIVILEGE_BIT
+	#define portPRIVILEGE_BIT ( ( UBaseType_t ) 0x00 )
+#endif
+
+#ifndef portYIELD_WITHIN_API
+	#define portYIELD_WITHIN_API portYIELD
+#endif
+
+#ifndef portSUPPRESS_TICKS_AND_SLEEP
+	#define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime )
+#endif
+
+#ifndef configEXPECTED_IDLE_TIME_BEFORE_SLEEP
+	#define configEXPECTED_IDLE_TIME_BEFORE_SLEEP 2
+#endif
+
+#if configEXPECTED_IDLE_TIME_BEFORE_SLEEP < 2
+	#error configEXPECTED_IDLE_TIME_BEFORE_SLEEP must not be less than 2
+#endif
+
+#ifndef configUSE_TICKLESS_IDLE
+	#define configUSE_TICKLESS_IDLE 0
+#endif
+
+#ifndef configPRE_SUPPRESS_TICKS_AND_SLEEP_PROCESSING
+	#define configPRE_SUPPRESS_TICKS_AND_SLEEP_PROCESSING( x )
+#endif
+
+#ifndef configPRE_SLEEP_PROCESSING
+	#define configPRE_SLEEP_PROCESSING( x )
+#endif
+
+#ifndef configPOST_SLEEP_PROCESSING
+	#define configPOST_SLEEP_PROCESSING( x )
+#endif
+
+#ifndef configUSE_QUEUE_SETS
+	#define configUSE_QUEUE_SETS 0
+#endif
+
+#ifndef portTASK_USES_FLOATING_POINT
+	#define portTASK_USES_FLOATING_POINT()
+#endif
+
+#ifndef portALLOCATE_SECURE_CONTEXT
+	#define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )
+#endif
+
+#ifndef portDONT_DISCARD
+	#define portDONT_DISCARD
+#endif
+
+#ifndef configUSE_TIME_SLICING
+	#define configUSE_TIME_SLICING 1
+#endif
+
+#ifndef configINCLUDE_APPLICATION_DEFINED_PRIVILEGED_FUNCTIONS
+	#define configINCLUDE_APPLICATION_DEFINED_PRIVILEGED_FUNCTIONS 0
+#endif
+
+#ifndef configUSE_STATS_FORMATTING_FUNCTIONS
+	#define configUSE_STATS_FORMATTING_FUNCTIONS 0
+#endif
+
+#ifndef portASSERT_IF_INTERRUPT_PRIORITY_INVALID
+	#define portASSERT_IF_INTERRUPT_PRIORITY_INVALID()
+#endif
+
+#ifndef configUSE_TRACE_FACILITY
+	#define configUSE_TRACE_FACILITY 0
+#endif
+
+#ifndef mtCOVERAGE_TEST_MARKER
+	#define mtCOVERAGE_TEST_MARKER()
+#endif
+
+#ifndef mtCOVERAGE_TEST_DELAY
+	#define mtCOVERAGE_TEST_DELAY()
+#endif
+
+#ifndef portASSERT_IF_IN_ISR
+	#define portASSERT_IF_IN_ISR()
+#endif
+
+#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
+	#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
+#endif
+
+#ifndef configAPPLICATION_ALLOCATED_HEAP
+	#define configAPPLICATION_ALLOCATED_HEAP 0
+#endif
+
+#ifndef configUSE_TASK_NOTIFICATIONS
+	#define configUSE_TASK_NOTIFICATIONS 1
+#endif
+
+#ifndef configUSE_POSIX_ERRNO
+	#define configUSE_POSIX_ERRNO 0
+#endif
+
+#ifndef portTICK_TYPE_IS_ATOMIC
+	#define portTICK_TYPE_IS_ATOMIC 0
+#endif
+
+#ifndef configSUPPORT_STATIC_ALLOCATION
+	/* Defaults to 0 for backward compatibility. */
+	#define configSUPPORT_STATIC_ALLOCATION 0
+#endif
+
+#ifndef configSUPPORT_DYNAMIC_ALLOCATION
+	/* Defaults to 1 for backward compatibility. */
+	#define configSUPPORT_DYNAMIC_ALLOCATION 1
+#endif
+
+#ifndef configSTACK_DEPTH_TYPE
+	/* Defaults to uint16_t for backward compatibility, but can be overridden
+	in FreeRTOSConfig.h if uint16_t is too restrictive. */
+	#define configSTACK_DEPTH_TYPE uint16_t
+#endif
+
+#ifndef configMESSAGE_BUFFER_LENGTH_TYPE
+	/* Defaults to size_t for backward compatibility, but can be overridden
+	in FreeRTOSConfig.h if lengths will always be less than the number of bytes
+	in a size_t. */
+	#define configMESSAGE_BUFFER_LENGTH_TYPE size_t
+#endif
+
+/* Sanity check the configuration. */
+#if( configUSE_TICKLESS_IDLE != 0 )
+	#if( INCLUDE_vTaskSuspend != 1 )
+		#error INCLUDE_vTaskSuspend must be set to 1 if configUSE_TICKLESS_IDLE is not set to 0
+	#endif /* INCLUDE_vTaskSuspend */
+#endif /* configUSE_TICKLESS_IDLE */
+
+#if( ( configSUPPORT_STATIC_ALLOCATION == 0 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 0 ) )
+	#error configSUPPORT_STATIC_ALLOCATION and configSUPPORT_DYNAMIC_ALLOCATION cannot both be 0, but can both be 1.
+#endif
+
+#if( ( configUSE_RECURSIVE_MUTEXES == 1 ) && ( configUSE_MUTEXES != 1 ) )
+	#error configUSE_MUTEXES must be set to 1 to use recursive mutexes
+#endif
+
+#ifndef configINITIAL_TICK_COUNT
+	#define configINITIAL_TICK_COUNT 0
+#endif
+
+#if( portTICK_TYPE_IS_ATOMIC == 0 )
+	/* Either variables of tick type cannot be read atomically, or
+	portTICK_TYPE_IS_ATOMIC was not set - map the critical sections used when
+	the tick count is returned to the standard critical section macros. */
+	#define portTICK_TYPE_ENTER_CRITICAL() portENTER_CRITICAL()
+	#define portTICK_TYPE_EXIT_CRITICAL() portEXIT_CRITICAL()
+	#define portTICK_TYPE_SET_INTERRUPT_MASK_FROM_ISR() portSET_INTERRUPT_MASK_FROM_ISR()
+	#define portTICK_TYPE_CLEAR_INTERRUPT_MASK_FROM_ISR( x ) portCLEAR_INTERRUPT_MASK_FROM_ISR( ( x ) )
+#else
+	/* The tick type can be read atomically, so critical sections used when the
+	tick count is returned can be defined away. */
+	#define portTICK_TYPE_ENTER_CRITICAL()
+	#define portTICK_TYPE_EXIT_CRITICAL()
+	#define portTICK_TYPE_SET_INTERRUPT_MASK_FROM_ISR() 0
+	#define portTICK_TYPE_CLEAR_INTERRUPT_MASK_FROM_ISR( x ) ( void ) x
+#endif
+
+/* Definitions to allow backward compatibility with FreeRTOS versions prior to
+V8 if desired. */
+#ifndef configENABLE_BACKWARD_COMPATIBILITY
+	#define configENABLE_BACKWARD_COMPATIBILITY 1
+#endif
+
+#ifndef configPRINTF
+	/* configPRINTF() was not defined, so define it away to nothing.  To use
+	configPRINTF() then define it as follows (where MyPrintFunction() is
+	provided by the application writer):
+
+	void MyPrintFunction(const char *pcFormat, ... );
+	#define configPRINTF( X )   MyPrintFunction X
+
+	Then call like a standard printf() function, but placing brackets around
+	all parameters so they are passed as a single parameter.  For example:
+	configPRINTF( ("Value = %d", MyVariable) ); */
+	#define configPRINTF( X )
+#endif
+
+#ifndef configMAX
+	/* The application writer has not provided their own MAX macro, so define
+	the following generic implementation. */
+	#define configMAX( a, b ) ( ( ( a ) > ( b ) ) ? ( a ) : ( b ) )
+#endif
+
+#ifndef configMIN
+	/* The application writer has not provided their own MAX macro, so define
+	the following generic implementation. */
+	#define configMIN( a, b ) ( ( ( a ) < ( b ) ) ? ( a ) : ( b ) )
+#endif
+
+#if configENABLE_BACKWARD_COMPATIBILITY == 1
+	#define eTaskStateGet eTaskGetState
+	#define portTickType TickType_t
+	#define xTaskHandle TaskHandle_t
+	#define xQueueHandle QueueHandle_t
+	#define xSemaphoreHandle SemaphoreHandle_t
+	#define xQueueSetHandle QueueSetHandle_t
+	#define xQueueSetMemberHandle QueueSetMemberHandle_t
+	#define xTimeOutType TimeOut_t
+	#define xMemoryRegion MemoryRegion_t
+	#define xTaskParameters TaskParameters_t
+	#define xTaskStatusType	TaskStatus_t
+	#define xTimerHandle TimerHandle_t
+	#define xCoRoutineHandle CoRoutineHandle_t
+	#define pdTASK_HOOK_CODE TaskHookFunction_t
+	#define portTICK_RATE_MS portTICK_PERIOD_MS
+	#define pcTaskGetTaskName pcTaskGetName
+	#define pcTimerGetTimerName pcTimerGetName
+	#define pcQueueGetQueueName pcQueueGetName
+	#define vTaskGetTaskInfo vTaskGetInfo
+	#define xTaskGetIdleRunTimeCounter ulTaskGetIdleRunTimeCounter
+
+	/* Backward compatibility within the scheduler code only - these definitions
+	are not really required but are included for completeness. */
+	#define tmrTIMER_CALLBACK TimerCallbackFunction_t
+	#define pdTASK_CODE TaskFunction_t
+	#define xListItem ListItem_t
+	#define xList List_t
+
+	/* For libraries that break the list data hiding, and access list structure
+	members directly (which is not supposed to be done). */
+	#define pxContainer pvContainer
+#endif /* configENABLE_BACKWARD_COMPATIBILITY */
+
+#if( configUSE_ALTERNATIVE_API != 0 )
+	#error The alternative API was deprecated some time ago, and was removed in FreeRTOS V9.0 0
+#endif
+
+/* Set configUSE_TASK_FPU_SUPPORT to 0 to omit floating point support even
+if floating point hardware is otherwise supported by the FreeRTOS port in use.
+This constant is not supported by all FreeRTOS ports that include floating
+point support. */
+#ifndef configUSE_TASK_FPU_SUPPORT
+	#define configUSE_TASK_FPU_SUPPORT 1
+#endif
+
+/* Set configENABLE_MPU to 1 to enable MPU support and 0 to disable it. This is
+currently used in ARMv8M ports. */
+#ifndef configENABLE_MPU
+	#define configENABLE_MPU 0
+#endif
+
+/* Set configENABLE_FPU to 1 to enable FPU support and 0 to disable it. This is
+currently used in ARMv8M ports. */
+#ifndef configENABLE_FPU
+	#define configENABLE_FPU 1
+#endif
+
+/* Set configENABLE_TRUSTZONE to 1 enable TrustZone support and 0 to disable it.
+This is currently used in ARMv8M ports. */
+#ifndef configENABLE_TRUSTZONE
+	#define configENABLE_TRUSTZONE 1
+#endif
+
+/* Set configRUN_FREERTOS_SECURE_ONLY to 1 to run the FreeRTOS ARMv8M port on
+the Secure Side only. */
+#ifndef configRUN_FREERTOS_SECURE_ONLY
+	#define configRUN_FREERTOS_SECURE_ONLY 0
+#endif
+
+/* Sometimes the FreeRTOSConfig.h settings only allow a task to be created using
+ * dynamically allocated RAM, in which case when any task is deleted it is known
+ * that both the task's stack and TCB need to be freed.  Sometimes the
+ * FreeRTOSConfig.h settings only allow a task to be created using statically
+ * allocated RAM, in which case when any task is deleted it is known that neither
+ * the task's stack or TCB should be freed.  Sometimes the FreeRTOSConfig.h
+ * settings allow a task to be created using either statically or dynamically
+ * allocated RAM, in which case a member of the TCB is used to record whether the
+ * stack and/or TCB were allocated statically or dynamically, so when a task is
+ * deleted the RAM that was allocated dynamically is freed again and no attempt is
+ * made to free the RAM that was allocated statically.
+ * tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE is only true if it is possible for a
+ * task to be created using either statically or dynamically allocated RAM.  Note
+ * that if portUSING_MPU_WRAPPERS is 1 then a protected task can be created with
+ * a statically allocated stack and a dynamically allocated TCB.
+ *
+ * The following table lists various combinations of portUSING_MPU_WRAPPERS,
+ * configSUPPORT_DYNAMIC_ALLOCATION and configSUPPORT_STATIC_ALLOCATION and
+ * when it is possible to have both static and dynamic allocation:
+ *  +-----+---------+--------+-----------------------------+-----------------------------------+------------------+-----------+
+ * | MPU | Dynamic | Static |     Available Functions     |       Possible Allocations        | Both Dynamic and | Need Free |
+ * |     |         |        |                             |                                   | Static Possible  |           |
+ * +-----+---------+--------+-----------------------------+-----------------------------------+------------------+-----------+
+ * | 0   | 0       | 1      | xTaskCreateStatic           | TCB - Static, Stack - Static      | No               | No        |
+ * +-----|---------|--------|-----------------------------|-----------------------------------|------------------|-----------|
+ * | 0   | 1       | 0      | xTaskCreate                 | TCB - Dynamic, Stack - Dynamic    | No               | Yes       |
+ * +-----|---------|--------|-----------------------------|-----------------------------------|------------------|-----------|
+ * | 0   | 1       | 1      | xTaskCreate,                | 1. TCB - Dynamic, Stack - Dynamic | Yes              | Yes       |
+ * |     |         |        | xTaskCreateStatic           | 2. TCB - Static, Stack - Static   |                  |           |
+ * +-----|---------|--------|-----------------------------|-----------------------------------|------------------|-----------|
+ * | 1   | 0       | 1      | xTaskCreateStatic,          | TCB - Static, Stack - Static      | No               | No        |
+ * |     |         |        | xTaskCreateRestrictedStatic |                                   |                  |           |
+ * +-----|---------|--------|-----------------------------|-----------------------------------|------------------|-----------|
+ * | 1   | 1       | 0      | xTaskCreate,                | 1. TCB - Dynamic, Stack - Dynamic | Yes              | Yes       |
+ * |     |         |        | xTaskCreateRestricted       | 2. TCB - Dynamic, Stack - Static  |                  |           |
+ * +-----|---------|--------|-----------------------------|-----------------------------------|------------------|-----------|
+ * | 1   | 1       | 1      | xTaskCreate,                | 1. TCB - Dynamic, Stack - Dynamic | Yes              | Yes       |
+ * |     |         |        | xTaskCreateStatic,          | 2. TCB - Dynamic, Stack - Static  |                  |           |
+ * |     |         |        | xTaskCreateRestricted,      | 3. TCB - Static, Stack - Static   |                  |           |
+ * |     |         |        | xTaskCreateRestrictedStatic |                                   |                  |           |
+ * +-----+---------+--------+-----------------------------+-----------------------------------+------------------+-----------+
+ */
+#define tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE	( ( ( portUSING_MPU_WRAPPERS == 0 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) ) || \
+													  ( ( portUSING_MPU_WRAPPERS == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) )
+
+/*
+ * In line with software engineering best practice, FreeRTOS implements a strict
+ * data hiding policy, so the real structures used by FreeRTOS to maintain the
+ * state of tasks, queues, semaphores, etc. are not accessible to the application
+ * code.  However, if the application writer wants to statically allocate such
+ * an object then the size of the object needs to be know.  Dummy structures
+ * that are guaranteed to have the same size and alignment requirements of the
+ * real objects are used for this purpose.  The dummy list and list item
+ * structures below are used for inclusion in such a dummy structure.
+ */
+struct xSTATIC_LIST_ITEM
+{
+	#if( configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES == 1 )
+		TickType_t xDummy1;
+	#endif
+	TickType_t xDummy2;
+	void *pvDummy3[ 4 ];
+	#if( configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES == 1 )
+		TickType_t xDummy4;
+	#endif
+};
+typedef struct xSTATIC_LIST_ITEM StaticListItem_t;
+
+/* See the comments above the struct xSTATIC_LIST_ITEM definition. */
+struct xSTATIC_MINI_LIST_ITEM
+{
+	#if( configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES == 1 )
+		TickType_t xDummy1;
+	#endif
+	TickType_t xDummy2;
+	void *pvDummy3[ 2 ];
+};
+typedef struct xSTATIC_MINI_LIST_ITEM StaticMiniListItem_t;
+
+/* See the comments above the struct xSTATIC_LIST_ITEM definition. */
+typedef struct xSTATIC_LIST
+{
+	#if( configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES == 1 )
+		TickType_t xDummy1;
+	#endif
+	UBaseType_t uxDummy2;
+	void *pvDummy3;
+	StaticMiniListItem_t xDummy4;
+	#if( configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES == 1 )
+		TickType_t xDummy5;
+	#endif
+} StaticList_t;
+
+/*
+ * In line with software engineering best practice, especially when supplying a
+ * library that is likely to change in future versions, FreeRTOS implements a
+ * strict data hiding policy.  This means the Task structure used internally by
+ * FreeRTOS is not accessible to application code.  However, if the application
+ * writer wants to statically allocate the memory required to create a task then
+ * the size of the task object needs to be know.  The StaticTask_t structure
+ * below is provided for this purpose.  Its sizes and alignment requirements are
+ * guaranteed to match those of the genuine structure, no matter which
+ * architecture is being used, and no matter how the values in FreeRTOSConfig.h
+ * are set.  Its contents are somewhat obfuscated in the hope users will
+ * recognise that it would be unwise to make direct use of the structure members.
+ */
+typedef struct xSTATIC_TCB
+{
+	void				*pxDummy1;
+	#if ( portUSING_MPU_WRAPPERS == 1 )
+		xMPU_SETTINGS	xDummy2;
+	#endif
+	StaticListItem_t	xDummy3[ 2 ];
+	UBaseType_t			uxDummy5;
+	void				*pxDummy6;
+	uint8_t				ucDummy7[ configMAX_TASK_NAME_LEN ];
+	#if ( ( portSTACK_GROWTH > 0 ) || ( configRECORD_STACK_HIGH_ADDRESS == 1 ) )
+		void			*pxDummy8;
+	#endif
+	#if ( portCRITICAL_NESTING_IN_TCB == 1 )
+		UBaseType_t		uxDummy9;
+	#endif
+	#if ( configUSE_TRACE_FACILITY == 1 )
+		UBaseType_t		uxDummy10[ 2 ];
+	#endif
+	#if ( configUSE_MUTEXES == 1 )
+		UBaseType_t		uxDummy12[ 2 ];
+	#endif
+	#if ( configUSE_APPLICATION_TASK_TAG == 1 )
+		void			*pxDummy14;
+	#endif
+	#if( configNUM_THREAD_LOCAL_STORAGE_POINTERS > 0 )
+		void			*pvDummy15[ configNUM_THREAD_LOCAL_STORAGE_POINTERS ];
+	#endif
+	#if ( configGENERATE_RUN_TIME_STATS == 1 )
+		uint32_t		ulDummy16;
+	#endif
+	#if ( configUSE_NEWLIB_REENTRANT == 1 )
+		struct	_reent	xDummy17;
+	#endif
+	#if ( configUSE_TASK_NOTIFICATIONS == 1 )
+		uint32_t 		ulDummy18;
+		uint8_t 		ucDummy19;
+	#endif
+	#if ( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 )
+		uint8_t			uxDummy20;
+	#endif
+
+	#if( INCLUDE_xTaskAbortDelay == 1 )
+		uint8_t ucDummy21;
+	#endif
+	#if ( configUSE_POSIX_ERRNO == 1 )
+		int				iDummy22;
+	#endif
+} StaticTask_t;
+
+/*
+ * In line with software engineering best practice, especially when supplying a
+ * library that is likely to change in future versions, FreeRTOS implements a
+ * strict data hiding policy.  This means the Queue structure used internally by
+ * FreeRTOS is not accessible to application code.  However, if the application
+ * writer wants to statically allocate the memory required to create a queue
+ * then the size of the queue object needs to be know.  The StaticQueue_t
+ * structure below is provided for this purpose.  Its sizes and alignment
+ * requirements are guaranteed to match those of the genuine structure, no
+ * matter which architecture is being used, and no matter how the values in
+ * FreeRTOSConfig.h are set.  Its contents are somewhat obfuscated in the hope
+ * users will recognise that it would be unwise to make direct use of the
+ * structure members.
+ */
+typedef struct xSTATIC_QUEUE
+{
+	void *pvDummy1[ 3 ];
+
+	union
+	{
+		void *pvDummy2;
+		UBaseType_t uxDummy2;
+	} u;
+
+	StaticList_t xDummy3[ 2 ];
+	UBaseType_t uxDummy4[ 3 ];
+	uint8_t ucDummy5[ 2 ];
+
+	#if( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
+		uint8_t ucDummy6;
+	#endif
+
+	#if ( configUSE_QUEUE_SETS == 1 )
+		void *pvDummy7;
+	#endif
+
+	#if ( configUSE_TRACE_FACILITY == 1 )
+		UBaseType_t uxDummy8;
+		uint8_t ucDummy9;
+	#endif
+
+} StaticQueue_t;
+typedef StaticQueue_t StaticSemaphore_t;
+
+/*
+ * In line with software engineering best practice, especially when supplying a
+ * library that is likely to change in future versions, FreeRTOS implements a
+ * strict data hiding policy.  This means the event group structure used
+ * internally by FreeRTOS is not accessible to application code.  However, if
+ * the application writer wants to statically allocate the memory required to
+ * create an event group then the size of the event group object needs to be
+ * know.  The StaticEventGroup_t structure below is provided for this purpose.
+ * Its sizes and alignment requirements are guaranteed to match those of the
+ * genuine structure, no matter which architecture is being used, and no matter
+ * how the values in FreeRTOSConfig.h are set.  Its contents are somewhat
+ * obfuscated in the hope users will recognise that it would be unwise to make
+ * direct use of the structure members.
+ */
+typedef struct xSTATIC_EVENT_GROUP
+{
+	TickType_t xDummy1;
+	StaticList_t xDummy2;
+
+	#if( configUSE_TRACE_FACILITY == 1 )
+		UBaseType_t uxDummy3;
+	#endif
+
+	#if( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
+			uint8_t ucDummy4;
+	#endif
+
+} StaticEventGroup_t;
+
+/*
+ * In line with software engineering best practice, especially when supplying a
+ * library that is likely to change in future versions, FreeRTOS implements a
+ * strict data hiding policy.  This means the software timer structure used
+ * internally by FreeRTOS is not accessible to application code.  However, if
+ * the application writer wants to statically allocate the memory required to
+ * create a software timer then the size of the queue object needs to be know.
+ * The StaticTimer_t structure below is provided for this purpose.  Its sizes
+ * and alignment requirements are guaranteed to match those of the genuine
+ * structure, no matter which architecture is being used, and no matter how the
+ * values in FreeRTOSConfig.h are set.  Its contents are somewhat obfuscated in
+ * the hope users will recognise that it would be unwise to make direct use of
+ * the structure members.
+ */
+typedef struct xSTATIC_TIMER
+{
+	void				*pvDummy1;
+	StaticListItem_t	xDummy2;
+	TickType_t			xDummy3;
+	void 				*pvDummy5;
+	TaskFunction_t		pvDummy6;
+	#if( configUSE_TRACE_FACILITY == 1 )
+		UBaseType_t		uxDummy7;
+	#endif
+	uint8_t 			ucDummy8;
+
+} StaticTimer_t;
+
+/*
+* In line with software engineering best practice, especially when supplying a
+* library that is likely to change in future versions, FreeRTOS implements a
+* strict data hiding policy.  This means the stream buffer structure used
+* internally by FreeRTOS is not accessible to application code.  However, if
+* the application writer wants to statically allocate the memory required to
+* create a stream buffer then the size of the stream buffer object needs to be
+* know.  The StaticStreamBuffer_t structure below is provided for this purpose.
+* Its size and alignment requirements are guaranteed to match those of the
+* genuine structure, no matter which architecture is being used, and no matter
+* how the values in FreeRTOSConfig.h are set.  Its contents are somewhat
+* obfuscated in the hope users will recognise that it would be unwise to make
+* direct use of the structure members.
+*/
+typedef struct xSTATIC_STREAM_BUFFER
+{
+	size_t uxDummy1[ 4 ];
+	void * pvDummy2[ 3 ];
+	uint8_t ucDummy3;
+	#if ( configUSE_TRACE_FACILITY == 1 )
+		UBaseType_t uxDummy4;
+	#endif
+} StaticStreamBuffer_t;
+
+/* Message buffers are built on stream buffers. */
+typedef StaticStreamBuffer_t StaticMessageBuffer_t;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* INC_FREERTOS_H */
+
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/include/StackMacros.h b/Middlewares/Third_Party/FreeRTOS/Source/include/StackMacros.h
new file mode 100644
index 0000000..ac94611
--- /dev/null
+++ b/Middlewares/Third_Party/FreeRTOS/Source/include/StackMacros.h
@@ -0,0 +1,133 @@
+/*
+ * FreeRTOS Kernel V10.3.1
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef STACK_MACROS_H
+#define STACK_MACROS_H
+
+#ifndef _MSC_VER /* Visual Studio doesn't support #warning. */
+	#warning The name of this file has changed to stack_macros.h.  Please update your code accordingly.  This source file (which has the original name) will be removed in future released.
+#endif
+
+/*
+ * Call the stack overflow hook function if the stack of the task being swapped
+ * out is currently overflowed, or looks like it might have overflowed in the
+ * past.
+ *
+ * Setting configCHECK_FOR_STACK_OVERFLOW to 1 will cause the macro to check
+ * the current stack state only - comparing the current top of stack value to
+ * the stack limit.  Setting configCHECK_FOR_STACK_OVERFLOW to greater than 1
+ * will also cause the last few stack bytes to be checked to ensure the value
+ * to which the bytes were set when the task was created have not been
+ * overwritten.  Note this second test does not guarantee that an overflowed
+ * stack will always be recognised.
+ */
+
+/*-----------------------------------------------------------*/
+
+#if( ( configCHECK_FOR_STACK_OVERFLOW == 1 ) && ( portSTACK_GROWTH < 0 ) )
+
+	/* Only the current stack state is to be checked. */
+	#define taskCHECK_FOR_STACK_OVERFLOW()																\
+	{																									\
+		/* Is the currently saved stack pointer within the stack limit? */								\
+		if( pxCurrentTCB->pxTopOfStack <= pxCurrentTCB->pxStack )										\
+		{																								\
+			vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pxCurrentTCB->pcTaskName );	\
+		}																								\
+	}
+
+#endif /* configCHECK_FOR_STACK_OVERFLOW == 1 */
+/*-----------------------------------------------------------*/
+
+#if( ( configCHECK_FOR_STACK_OVERFLOW == 1 ) && ( portSTACK_GROWTH > 0 ) )
+
+	/* Only the current stack state is to be checked. */
+	#define taskCHECK_FOR_STACK_OVERFLOW()																\
+	{																									\
+																										\
+		/* Is the currently saved stack pointer within the stack limit? */								\
+		if( pxCurrentTCB->pxTopOfStack >= pxCurrentTCB->pxEndOfStack )									\
+		{																								\
+			vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pxCurrentTCB->pcTaskName );	\
+		}																								\
+	}
+
+#endif /* configCHECK_FOR_STACK_OVERFLOW == 1 */
+/*-----------------------------------------------------------*/
+
+#if( ( configCHECK_FOR_STACK_OVERFLOW > 1 ) && ( portSTACK_GROWTH < 0 ) )
+
+	#define taskCHECK_FOR_STACK_OVERFLOW()																\
+	{																									\
+		const uint32_t * const pulStack = ( uint32_t * ) pxCurrentTCB->pxStack;							\
+		const uint32_t ulCheckValue = ( uint32_t ) 0xa5a5a5a5;											\
+																										\
+		if( ( pulStack[ 0 ] != ulCheckValue ) ||												\
+			( pulStack[ 1 ] != ulCheckValue ) ||												\
+			( pulStack[ 2 ] != ulCheckValue ) ||												\
+			( pulStack[ 3 ] != ulCheckValue ) )												\
+		{																								\
+			vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pxCurrentTCB->pcTaskName );	\
+		}																								\
+	}
+
+#endif /* #if( configCHECK_FOR_STACK_OVERFLOW > 1 ) */
+/*-----------------------------------------------------------*/
+
+#if( ( configCHECK_FOR_STACK_OVERFLOW > 1 ) && ( portSTACK_GROWTH > 0 ) )
+
+	#define taskCHECK_FOR_STACK_OVERFLOW()																								\
+	{																																	\
+	int8_t *pcEndOfStack = ( int8_t * ) pxCurrentTCB->pxEndOfStack;																		\
+	static const uint8_t ucExpectedStackBytes[] = {	tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE,		\
+													tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE,		\
+													tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE,		\
+													tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE,		\
+													tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE };	\
+																																		\
+																																		\
+		pcEndOfStack -= sizeof( ucExpectedStackBytes );																					\
+																																		\
+		/* Has the extremity of the task stack ever been written over? */																\
+		if( memcmp( ( void * ) pcEndOfStack, ( void * ) ucExpectedStackBytes, sizeof( ucExpectedStackBytes ) ) != 0 )					\
+		{																																\
+			vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pxCurrentTCB->pcTaskName );									\
+		}																																\
+	}
+
+#endif /* #if( configCHECK_FOR_STACK_OVERFLOW > 1 ) */
+/*-----------------------------------------------------------*/
+
+/* Remove stack overflow macro if not being used. */
+#ifndef taskCHECK_FOR_STACK_OVERFLOW
+	#define taskCHECK_FOR_STACK_OVERFLOW()
+#endif
+
+
+
+#endif /* STACK_MACROS_H */
+
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/include/atomic.h b/Middlewares/Third_Party/FreeRTOS/Source/include/atomic.h
new file mode 100644
index 0000000..795d801
--- /dev/null
+++ b/Middlewares/Third_Party/FreeRTOS/Source/include/atomic.h
@@ -0,0 +1,414 @@
+/*
+ * FreeRTOS Kernel V10.3.1
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/**
+ * @file atomic.h
+ * @brief FreeRTOS atomic operation support.
+ *
+ * This file implements atomic functions by disabling interrupts globally.
+ * Implementations with architecture specific atomic instructions can be
+ * provided under each compiler directory.
+ */
+
+#ifndef ATOMIC_H
+#define ATOMIC_H
+
+#ifndef INC_FREERTOS_H
+	#error "include FreeRTOS.h must appear in source files before include atomic.h"
+#endif
+
+/* Standard includes. */
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+ * Port specific definitions -- entering/exiting critical section.
+ * Refer template -- ./lib/FreeRTOS/portable/Compiler/Arch/portmacro.h
+ *
+ * Every call to ATOMIC_EXIT_CRITICAL() must be closely paired with
+ * ATOMIC_ENTER_CRITICAL().
+ *
+ */
+#if defined( portSET_INTERRUPT_MASK_FROM_ISR )
+
+	/* Nested interrupt scheme is supported in this port. */
+	#define ATOMIC_ENTER_CRITICAL()	 \
+		UBaseType_t uxCriticalSectionType = portSET_INTERRUPT_MASK_FROM_ISR()
+
+	#define ATOMIC_EXIT_CRITICAL()	  \
+		portCLEAR_INTERRUPT_MASK_FROM_ISR( uxCriticalSectionType )
+
+#else
+
+	/* Nested interrupt scheme is NOT supported in this port. */
+	#define ATOMIC_ENTER_CRITICAL()	 portENTER_CRITICAL()
+	#define ATOMIC_EXIT_CRITICAL()	  portEXIT_CRITICAL()
+
+#endif /* portSET_INTERRUPT_MASK_FROM_ISR() */
+
+/*
+ * Port specific definition -- "always inline".
+ * Inline is compiler specific, and may not always get inlined depending on your
+ * optimization level.  Also, inline is considered as performance optimization
+ * for atomic.  Thus, if portFORCE_INLINE is not provided by portmacro.h,
+ * instead of resulting error, simply define it away.
+ */
+#ifndef portFORCE_INLINE
+	#define portFORCE_INLINE
+#endif
+
+#define ATOMIC_COMPARE_AND_SWAP_SUCCESS	 0x1U		/**< Compare and swap succeeded, swapped. */
+#define ATOMIC_COMPARE_AND_SWAP_FAILURE	 0x0U		/**< Compare and swap failed, did not swap. */
+
+/*----------------------------- Swap && CAS ------------------------------*/
+
+/**
+ * Atomic compare-and-swap
+ *
+ * @brief Performs an atomic compare-and-swap operation on the specified values.
+ *
+ * @param[in, out] pulDestination  Pointer to memory location from where value is
+ *                               to be loaded and checked.
+ * @param[in] ulExchange         If condition meets, write this value to memory.
+ * @param[in] ulComparand        Swap condition.
+ *
+ * @return Unsigned integer of value 1 or 0. 1 for swapped, 0 for not swapped.
+ *
+ * @note This function only swaps *pulDestination with ulExchange, if previous
+ *       *pulDestination value equals ulComparand.
+ */
+static portFORCE_INLINE uint32_t Atomic_CompareAndSwap_u32( uint32_t volatile * pulDestination,
+															uint32_t ulExchange,
+															uint32_t ulComparand )
+{
+uint32_t ulReturnValue;
+
+	ATOMIC_ENTER_CRITICAL();
+	{
+		if( *pulDestination == ulComparand )
+		{
+			*pulDestination = ulExchange;
+			ulReturnValue = ATOMIC_COMPARE_AND_SWAP_SUCCESS;
+		}
+		else
+		{
+			ulReturnValue = ATOMIC_COMPARE_AND_SWAP_FAILURE;
+		}
+	}
+	ATOMIC_EXIT_CRITICAL();
+
+	return ulReturnValue;
+}
+/*-----------------------------------------------------------*/
+
+/**
+ * Atomic swap (pointers)
+ *
+ * @brief Atomically sets the address pointed to by *ppvDestination to the value
+ *        of *pvExchange.
+ *
+ * @param[in, out] ppvDestination  Pointer to memory location from where a pointer
+ *                                 value is to be loaded and written back to.
+ * @param[in] pvExchange           Pointer value to be written to *ppvDestination.
+ *
+ * @return The initial value of *ppvDestination.
+ */
+static portFORCE_INLINE void * Atomic_SwapPointers_p32( void * volatile * ppvDestination,
+														void * pvExchange )
+{
+void * pReturnValue;
+
+	ATOMIC_ENTER_CRITICAL();
+	{
+		pReturnValue = *ppvDestination;
+		*ppvDestination = pvExchange;
+	}
+	ATOMIC_EXIT_CRITICAL();
+
+	return pReturnValue;
+}
+/*-----------------------------------------------------------*/
+
+/**
+ * Atomic compare-and-swap (pointers)
+ *
+ * @brief Performs an atomic compare-and-swap operation on the specified pointer
+ *        values.
+ *
+ * @param[in, out] ppvDestination  Pointer to memory location from where a pointer
+ *                                 value is to be loaded and checked.
+ * @param[in] pvExchange           If condition meets, write this value to memory.
+ * @param[in] pvComparand          Swap condition.
+ *
+ * @return Unsigned integer of value 1 or 0. 1 for swapped, 0 for not swapped.
+ *
+ * @note This function only swaps *ppvDestination with pvExchange, if previous
+ *       *ppvDestination value equals pvComparand.
+ */
+static portFORCE_INLINE uint32_t Atomic_CompareAndSwapPointers_p32( void * volatile * ppvDestination,
+																	void * pvExchange,
+																	void * pvComparand )
+{
+uint32_t ulReturnValue = ATOMIC_COMPARE_AND_SWAP_FAILURE;
+
+	ATOMIC_ENTER_CRITICAL();
+	{
+		if( *ppvDestination == pvComparand )
+		{
+			*ppvDestination = pvExchange;
+			ulReturnValue = ATOMIC_COMPARE_AND_SWAP_SUCCESS;
+		}
+	}
+	ATOMIC_EXIT_CRITICAL();
+
+	return ulReturnValue;
+}
+
+
+/*----------------------------- Arithmetic ------------------------------*/
+
+/**
+ * Atomic add
+ *
+ * @brief Atomically adds count to the value of the specified pointer points to.
+ *
+ * @param[in,out] pulAddend  Pointer to memory location from where value is to be
+ *                         loaded and written back to.
+ * @param[in] ulCount      Value to be added to *pulAddend.
+ *
+ * @return previous *pulAddend value.
+ */
+static portFORCE_INLINE uint32_t Atomic_Add_u32( uint32_t volatile * pulAddend,
+												 uint32_t ulCount )
+{
+	uint32_t ulCurrent;
+
+	ATOMIC_ENTER_CRITICAL();
+	{
+		ulCurrent = *pulAddend;
+		*pulAddend += ulCount;
+	}
+	ATOMIC_EXIT_CRITICAL();
+
+	return ulCurrent;
+}
+/*-----------------------------------------------------------*/
+
+/**
+ * Atomic subtract
+ *
+ * @brief Atomically subtracts count from the value of the specified pointer
+ *        pointers to.
+ *
+ * @param[in,out] pulAddend  Pointer to memory location from where value is to be
+ *                         loaded and written back to.
+ * @param[in] ulCount      Value to be subtract from *pulAddend.
+ *
+ * @return previous *pulAddend value.
+ */
+static portFORCE_INLINE uint32_t Atomic_Subtract_u32( uint32_t volatile * pulAddend,
+													  uint32_t ulCount )
+{
+	uint32_t ulCurrent;
+
+	ATOMIC_ENTER_CRITICAL();
+	{
+		ulCurrent = *pulAddend;
+		*pulAddend -= ulCount;
+	}
+	ATOMIC_EXIT_CRITICAL();
+
+	return ulCurrent;
+}
+/*-----------------------------------------------------------*/
+
+/**
+ * Atomic increment
+ *
+ * @brief Atomically increments the value of the specified pointer points to.
+ *
+ * @param[in,out] pulAddend  Pointer to memory location from where value is to be
+ *                         loaded and written back to.
+ *
+ * @return *pulAddend value before increment.
+ */
+static portFORCE_INLINE uint32_t Atomic_Increment_u32( uint32_t volatile * pulAddend )
+{
+uint32_t ulCurrent;
+
+	ATOMIC_ENTER_CRITICAL();
+	{
+		ulCurrent = *pulAddend;
+		*pulAddend += 1;
+	}
+	ATOMIC_EXIT_CRITICAL();
+
+	return ulCurrent;
+}
+/*-----------------------------------------------------------*/
+
+/**
+ * Atomic decrement
+ *
+ * @brief Atomically decrements the value of the specified pointer points to
+ *
+ * @param[in,out] pulAddend  Pointer to memory location from where value is to be
+ *                         loaded and written back to.
+ *
+ * @return *pulAddend value before decrement.
+ */
+static portFORCE_INLINE uint32_t Atomic_Decrement_u32( uint32_t volatile * pulAddend )
+{
+uint32_t ulCurrent;
+
+	ATOMIC_ENTER_CRITICAL();
+	{
+		ulCurrent = *pulAddend;
+		*pulAddend -= 1;
+	}
+	ATOMIC_EXIT_CRITICAL();
+
+	return ulCurrent;
+}
+
+/*----------------------------- Bitwise Logical ------------------------------*/
+
+/**
+ * Atomic OR
+ *
+ * @brief Performs an atomic OR operation on the specified values.
+ *
+ * @param [in, out] pulDestination  Pointer to memory location from where value is
+ *                                to be loaded and written back to.
+ * @param [in] ulValue            Value to be ORed with *pulDestination.
+ *
+ * @return The original value of *pulDestination.
+ */
+static portFORCE_INLINE uint32_t Atomic_OR_u32( uint32_t volatile * pulDestination,
+												uint32_t ulValue )
+{
+uint32_t ulCurrent;
+
+	ATOMIC_ENTER_CRITICAL();
+	{
+		ulCurrent = *pulDestination;
+		*pulDestination |= ulValue;
+	}
+	ATOMIC_EXIT_CRITICAL();
+
+	return ulCurrent;
+}
+/*-----------------------------------------------------------*/
+
+/**
+ * Atomic AND
+ *
+ * @brief Performs an atomic AND operation on the specified values.
+ *
+ * @param [in, out] pulDestination  Pointer to memory location from where value is
+ *                                to be loaded and written back to.
+ * @param [in] ulValue            Value to be ANDed with *pulDestination.
+ *
+ * @return The original value of *pulDestination.
+ */
+static portFORCE_INLINE uint32_t Atomic_AND_u32( uint32_t volatile * pulDestination,
+												 uint32_t ulValue )
+{
+uint32_t ulCurrent;
+
+	ATOMIC_ENTER_CRITICAL();
+	{
+		ulCurrent = *pulDestination;
+		*pulDestination &= ulValue;
+	}
+	ATOMIC_EXIT_CRITICAL();
+
+	return ulCurrent;
+}
+/*-----------------------------------------------------------*/
+
+/**
+ * Atomic NAND
+ *
+ * @brief Performs an atomic NAND operation on the specified values.
+ *
+ * @param [in, out] pulDestination  Pointer to memory location from where value is
+ *                                to be loaded and written back to.
+ * @param [in] ulValue            Value to be NANDed with *pulDestination.
+ *
+ * @return The original value of *pulDestination.
+ */
+static portFORCE_INLINE uint32_t Atomic_NAND_u32( uint32_t volatile * pulDestination,
+												  uint32_t ulValue )
+{
+uint32_t ulCurrent;
+
+	ATOMIC_ENTER_CRITICAL();
+	{
+		ulCurrent = *pulDestination;
+		*pulDestination = ~( ulCurrent & ulValue );
+	}
+	ATOMIC_EXIT_CRITICAL();
+
+	return ulCurrent;
+}
+/*-----------------------------------------------------------*/
+
+/**
+ * Atomic XOR
+ *
+ * @brief Performs an atomic XOR operation on the specified values.
+ *
+ * @param [in, out] pulDestination  Pointer to memory location from where value is
+ *                                to be loaded and written back to.
+ * @param [in] ulValue            Value to be XORed with *pulDestination.
+ *
+ * @return The original value of *pulDestination.
+ */
+static portFORCE_INLINE uint32_t Atomic_XOR_u32( uint32_t volatile * pulDestination,
+												 uint32_t ulValue )
+{
+uint32_t ulCurrent;
+
+	ATOMIC_ENTER_CRITICAL();
+	{
+		ulCurrent = *pulDestination;
+		*pulDestination ^= ulValue;
+	}
+	ATOMIC_EXIT_CRITICAL();
+
+	return ulCurrent;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* ATOMIC_H */
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/include/croutine.h b/Middlewares/Third_Party/FreeRTOS/Source/include/croutine.h
new file mode 100644
index 0000000..ed2c161
--- /dev/null
+++ b/Middlewares/Third_Party/FreeRTOS/Source/include/croutine.h
@@ -0,0 +1,720 @@
+/*
+ * FreeRTOS Kernel V10.3.1
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef CO_ROUTINE_H
+#define CO_ROUTINE_H
+
+#ifndef INC_FREERTOS_H
+	#error "include FreeRTOS.h must appear in source files before include croutine.h"
+#endif
+
+#include "list.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Used to hide the implementation of the co-routine control block.  The
+control block structure however has to be included in the header due to
+the macro implementation of the co-routine functionality. */
+typedef void * CoRoutineHandle_t;
+
+/* Defines the prototype to which co-routine functions must conform. */
+typedef void (*crCOROUTINE_CODE)( CoRoutineHandle_t, UBaseType_t );
+
+typedef struct corCoRoutineControlBlock
+{
+	crCOROUTINE_CODE 	pxCoRoutineFunction;
+	ListItem_t			xGenericListItem;	/*< List item used to place the CRCB in ready and blocked queues. */
+	ListItem_t			xEventListItem;		/*< List item used to place the CRCB in event lists. */
+	UBaseType_t 		uxPriority;			/*< The priority of the co-routine in relation to other co-routines. */
+	UBaseType_t 		uxIndex;			/*< Used to distinguish between co-routines when multiple co-routines use the same co-routine function. */
+	uint16_t 			uxState;			/*< Used internally by the co-routine implementation. */
+} CRCB_t; /* Co-routine control block.  Note must be identical in size down to uxPriority with TCB_t. */
+
+/**
+ * croutine. h
+ *<pre>
+ BaseType_t xCoRoutineCreate(
+                                 crCOROUTINE_CODE pxCoRoutineCode,
+                                 UBaseType_t uxPriority,
+                                 UBaseType_t uxIndex
+                               );</pre>
+ *
+ * Create a new co-routine and add it to the list of co-routines that are
+ * ready to run.
+ *
+ * @param pxCoRoutineCode Pointer to the co-routine function.  Co-routine
+ * functions require special syntax - see the co-routine section of the WEB
+ * documentation for more information.
+ *
+ * @param uxPriority The priority with respect to other co-routines at which
+ *  the co-routine will run.
+ *
+ * @param uxIndex Used to distinguish between different co-routines that
+ * execute the same function.  See the example below and the co-routine section
+ * of the WEB documentation for further information.
+ *
+ * @return pdPASS if the co-routine was successfully created and added to a ready
+ * list, otherwise an error code defined with ProjDefs.h.
+ *
+ * Example usage:
+   <pre>
+ // Co-routine to be created.
+ void vFlashCoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )
+ {
+ // Variables in co-routines must be declared static if they must maintain value across a blocking call.
+ // This may not be necessary for const variables.
+ static const char cLedToFlash[ 2 ] = { 5, 6 };
+ static const TickType_t uxFlashRates[ 2 ] = { 200, 400 };
+
+     // Must start every co-routine with a call to crSTART();
+     crSTART( xHandle );
+
+     for( ;; )
+     {
+         // This co-routine just delays for a fixed period, then toggles
+         // an LED.  Two co-routines are created using this function, so
+         // the uxIndex parameter is used to tell the co-routine which
+         // LED to flash and how int32_t to delay.  This assumes xQueue has
+         // already been created.
+         vParTestToggleLED( cLedToFlash[ uxIndex ] );
+         crDELAY( xHandle, uxFlashRates[ uxIndex ] );
+     }
+
+     // Must end every co-routine with a call to crEND();
+     crEND();
+ }
+
+ // Function that creates two co-routines.
+ void vOtherFunction( void )
+ {
+ uint8_t ucParameterToPass;
+ TaskHandle_t xHandle;
+
+     // Create two co-routines at priority 0.  The first is given index 0
+     // so (from the code above) toggles LED 5 every 200 ticks.  The second
+     // is given index 1 so toggles LED 6 every 400 ticks.
+     for( uxIndex = 0; uxIndex < 2; uxIndex++ )
+     {
+         xCoRoutineCreate( vFlashCoRoutine, 0, uxIndex );
+     }
+ }
+   </pre>
+ * \defgroup xCoRoutineCreate xCoRoutineCreate
+ * \ingroup Tasks
+ */
+BaseType_t xCoRoutineCreate( crCOROUTINE_CODE pxCoRoutineCode, UBaseType_t uxPriority, UBaseType_t uxIndex );
+
+
+/**
+ * croutine. h
+ *<pre>
+ void vCoRoutineSchedule( void );</pre>
+ *
+ * Run a co-routine.
+ *
+ * vCoRoutineSchedule() executes the highest priority co-routine that is able
+ * to run.  The co-routine will execute until it either blocks, yields or is
+ * preempted by a task.  Co-routines execute cooperatively so one
+ * co-routine cannot be preempted by another, but can be preempted by a task.
+ *
+ * If an application comprises of both tasks and co-routines then
+ * vCoRoutineSchedule should be called from the idle task (in an idle task
+ * hook).
+ *
+ * Example usage:
+   <pre>
+ // This idle task hook will schedule a co-routine each time it is called.
+ // The rest of the idle task will execute between co-routine calls.
+ void vApplicationIdleHook( void )
+ {
+	vCoRoutineSchedule();
+ }
+
+ // Alternatively, if you do not require any other part of the idle task to
+ // execute, the idle task hook can call vCoRoutineSchedule() within an
+ // infinite loop.
+ void vApplicationIdleHook( void )
+ {
+    for( ;; )
+    {
+        vCoRoutineSchedule();
+    }
+ }
+ </pre>
+ * \defgroup vCoRoutineSchedule vCoRoutineSchedule
+ * \ingroup Tasks
+ */
+void vCoRoutineSchedule( void );
+
+/**
+ * croutine. h
+ * <pre>
+ crSTART( CoRoutineHandle_t xHandle );</pre>
+ *
+ * This macro MUST always be called at the start of a co-routine function.
+ *
+ * Example usage:
+   <pre>
+ // Co-routine to be created.
+ void vACoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )
+ {
+ // Variables in co-routines must be declared static if they must maintain value across a blocking call.
+ static int32_t ulAVariable;
+
+     // Must start every co-routine with a call to crSTART();
+     crSTART( xHandle );
+
+     for( ;; )
+     {
+          // Co-routine functionality goes here.
+     }
+
+     // Must end every co-routine with a call to crEND();
+     crEND();
+ }</pre>
+ * \defgroup crSTART crSTART
+ * \ingroup Tasks
+ */
+#define crSTART( pxCRCB ) switch( ( ( CRCB_t * )( pxCRCB ) )->uxState ) { case 0:
+
+/**
+ * croutine. h
+ * <pre>
+ crEND();</pre>
+ *
+ * This macro MUST always be called at the end of a co-routine function.
+ *
+ * Example usage:
+   <pre>
+ // Co-routine to be created.
+ void vACoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )
+ {
+ // Variables in co-routines must be declared static if they must maintain value across a blocking call.
+ static int32_t ulAVariable;
+
+     // Must start every co-routine with a call to crSTART();
+     crSTART( xHandle );
+
+     for( ;; )
+     {
+          // Co-routine functionality goes here.
+     }
+
+     // Must end every co-routine with a call to crEND();
+     crEND();
+ }</pre>
+ * \defgroup crSTART crSTART
+ * \ingroup Tasks
+ */
+#define crEND() }
+
+/*
+ * These macros are intended for internal use by the co-routine implementation
+ * only.  The macros should not be used directly by application writers.
+ */
+#define crSET_STATE0( xHandle ) ( ( CRCB_t * )( xHandle ) )->uxState = (__LINE__ * 2); return; case (__LINE__ * 2):
+#define crSET_STATE1( xHandle ) ( ( CRCB_t * )( xHandle ) )->uxState = ((__LINE__ * 2)+1); return; case ((__LINE__ * 2)+1):
+
+/**
+ * croutine. h
+ *<pre>
+ crDELAY( CoRoutineHandle_t xHandle, TickType_t xTicksToDelay );</pre>
+ *
+ * Delay a co-routine for a fixed period of time.
+ *
+ * crDELAY can only be called from the co-routine function itself - not
+ * from within a function called by the co-routine function.  This is because
+ * co-routines do not maintain their own stack.
+ *
+ * @param xHandle The handle of the co-routine to delay.  This is the xHandle
+ * parameter of the co-routine function.
+ *
+ * @param xTickToDelay The number of ticks that the co-routine should delay
+ * for.  The actual amount of time this equates to is defined by
+ * configTICK_RATE_HZ (set in FreeRTOSConfig.h).  The constant portTICK_PERIOD_MS
+ * can be used to convert ticks to milliseconds.
+ *
+ * Example usage:
+   <pre>
+ // Co-routine to be created.
+ void vACoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )
+ {
+ // Variables in co-routines must be declared static if they must maintain value across a blocking call.
+ // This may not be necessary for const variables.
+ // We are to delay for 200ms.
+ static const xTickType xDelayTime = 200 / portTICK_PERIOD_MS;
+
+     // Must start every co-routine with a call to crSTART();
+     crSTART( xHandle );
+
+     for( ;; )
+     {
+        // Delay for 200ms.
+        crDELAY( xHandle, xDelayTime );
+
+        // Do something here.
+     }
+
+     // Must end every co-routine with a call to crEND();
+     crEND();
+ }</pre>
+ * \defgroup crDELAY crDELAY
+ * \ingroup Tasks
+ */
+#define crDELAY( xHandle, xTicksToDelay )												\
+	if( ( xTicksToDelay ) > 0 )															\
+	{																					\
+		vCoRoutineAddToDelayedList( ( xTicksToDelay ), NULL );							\
+	}																					\
+	crSET_STATE0( ( xHandle ) );
+
+/**
+ * <pre>
+ crQUEUE_SEND(
+                  CoRoutineHandle_t xHandle,
+                  QueueHandle_t pxQueue,
+                  void *pvItemToQueue,
+                  TickType_t xTicksToWait,
+                  BaseType_t *pxResult
+             )</pre>
+ *
+ * The macro's crQUEUE_SEND() and crQUEUE_RECEIVE() are the co-routine
+ * equivalent to the xQueueSend() and xQueueReceive() functions used by tasks.
+ *
+ * crQUEUE_SEND and crQUEUE_RECEIVE can only be used from a co-routine whereas
+ * xQueueSend() and xQueueReceive() can only be used from tasks.
+ *
+ * crQUEUE_SEND can only be called from the co-routine function itself - not
+ * from within a function called by the co-routine function.  This is because
+ * co-routines do not maintain their own stack.
+ *
+ * See the co-routine section of the WEB documentation for information on
+ * passing data between tasks and co-routines and between ISR's and
+ * co-routines.
+ *
+ * @param xHandle The handle of the calling co-routine.  This is the xHandle
+ * parameter of the co-routine function.
+ *
+ * @param pxQueue The handle of the queue on which the data will be posted.
+ * The handle is obtained as the return value when the queue is created using
+ * the xQueueCreate() API function.
+ *
+ * @param pvItemToQueue A pointer to the data being posted onto the queue.
+ * The number of bytes of each queued item is specified when the queue is
+ * created.  This number of bytes is copied from pvItemToQueue into the queue
+ * itself.
+ *
+ * @param xTickToDelay The number of ticks that the co-routine should block
+ * to wait for space to become available on the queue, should space not be
+ * available immediately. The actual amount of time this equates to is defined
+ * by configTICK_RATE_HZ (set in FreeRTOSConfig.h).  The constant
+ * portTICK_PERIOD_MS can be used to convert ticks to milliseconds (see example
+ * below).
+ *
+ * @param pxResult The variable pointed to by pxResult will be set to pdPASS if
+ * data was successfully posted onto the queue, otherwise it will be set to an
+ * error defined within ProjDefs.h.
+ *
+ * Example usage:
+   <pre>
+ // Co-routine function that blocks for a fixed period then posts a number onto
+ // a queue.
+ static void prvCoRoutineFlashTask( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )
+ {
+ // Variables in co-routines must be declared static if they must maintain value across a blocking call.
+ static BaseType_t xNumberToPost = 0;
+ static BaseType_t xResult;
+
+    // Co-routines must begin with a call to crSTART().
+    crSTART( xHandle );
+
+    for( ;; )
+    {
+        // This assumes the queue has already been created.
+        crQUEUE_SEND( xHandle, xCoRoutineQueue, &xNumberToPost, NO_DELAY, &xResult );
+
+        if( xResult != pdPASS )
+        {
+            // The message was not posted!
+        }
+
+        // Increment the number to be posted onto the queue.
+        xNumberToPost++;
+
+        // Delay for 100 ticks.
+        crDELAY( xHandle, 100 );
+    }
+
+    // Co-routines must end with a call to crEND().
+    crEND();
+ }</pre>
+ * \defgroup crQUEUE_SEND crQUEUE_SEND
+ * \ingroup Tasks
+ */
+#define crQUEUE_SEND( xHandle, pxQueue, pvItemToQueue, xTicksToWait, pxResult )			\
+{																						\
+	*( pxResult ) = xQueueCRSend( ( pxQueue) , ( pvItemToQueue) , ( xTicksToWait ) );	\
+	if( *( pxResult ) == errQUEUE_BLOCKED )												\
+	{																					\
+		crSET_STATE0( ( xHandle ) );													\
+		*pxResult = xQueueCRSend( ( pxQueue ), ( pvItemToQueue ), 0 );					\
+	}																					\
+	if( *pxResult == errQUEUE_YIELD )													\
+	{																					\
+		crSET_STATE1( ( xHandle ) );													\
+		*pxResult = pdPASS;																\
+	}																					\
+}
+
+/**
+ * croutine. h
+ * <pre>
+  crQUEUE_RECEIVE(
+                     CoRoutineHandle_t xHandle,
+                     QueueHandle_t pxQueue,
+                     void *pvBuffer,
+                     TickType_t xTicksToWait,
+                     BaseType_t *pxResult
+                 )</pre>
+ *
+ * The macro's crQUEUE_SEND() and crQUEUE_RECEIVE() are the co-routine
+ * equivalent to the xQueueSend() and xQueueReceive() functions used by tasks.
+ *
+ * crQUEUE_SEND and crQUEUE_RECEIVE can only be used from a co-routine whereas
+ * xQueueSend() and xQueueReceive() can only be used from tasks.
+ *
+ * crQUEUE_RECEIVE can only be called from the co-routine function itself - not
+ * from within a function called by the co-routine function.  This is because
+ * co-routines do not maintain their own stack.
+ *
+ * See the co-routine section of the WEB documentation for information on
+ * passing data between tasks and co-routines and between ISR's and
+ * co-routines.
+ *
+ * @param xHandle The handle of the calling co-routine.  This is the xHandle
+ * parameter of the co-routine function.
+ *
+ * @param pxQueue The handle of the queue from which the data will be received.
+ * The handle is obtained as the return value when the queue is created using
+ * the xQueueCreate() API function.
+ *
+ * @param pvBuffer The buffer into which the received item is to be copied.
+ * The number of bytes of each queued item is specified when the queue is
+ * created.  This number of bytes is copied into pvBuffer.
+ *
+ * @param xTickToDelay The number of ticks that the co-routine should block
+ * to wait for data to become available from the queue, should data not be
+ * available immediately. The actual amount of time this equates to is defined
+ * by configTICK_RATE_HZ (set in FreeRTOSConfig.h).  The constant
+ * portTICK_PERIOD_MS can be used to convert ticks to milliseconds (see the
+ * crQUEUE_SEND example).
+ *
+ * @param pxResult The variable pointed to by pxResult will be set to pdPASS if
+ * data was successfully retrieved from the queue, otherwise it will be set to
+ * an error code as defined within ProjDefs.h.
+ *
+ * Example usage:
+ <pre>
+ // A co-routine receives the number of an LED to flash from a queue.  It
+ // blocks on the queue until the number is received.
+ static void prvCoRoutineFlashWorkTask( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )
+ {
+ // Variables in co-routines must be declared static if they must maintain value across a blocking call.
+ static BaseType_t xResult;
+ static UBaseType_t uxLEDToFlash;
+
+    // All co-routines must start with a call to crSTART().
+    crSTART( xHandle );
+
+    for( ;; )
+    {
+        // Wait for data to become available on the queue.
+        crQUEUE_RECEIVE( xHandle, xCoRoutineQueue, &uxLEDToFlash, portMAX_DELAY, &xResult );
+
+        if( xResult == pdPASS )
+        {
+            // We received the LED to flash - flash it!
+            vParTestToggleLED( uxLEDToFlash );
+        }
+    }
+
+    crEND();
+ }</pre>
+ * \defgroup crQUEUE_RECEIVE crQUEUE_RECEIVE
+ * \ingroup Tasks
+ */
+#define crQUEUE_RECEIVE( xHandle, pxQueue, pvBuffer, xTicksToWait, pxResult )			\
+{																						\
+	*( pxResult ) = xQueueCRReceive( ( pxQueue) , ( pvBuffer ), ( xTicksToWait ) );		\
+	if( *( pxResult ) == errQUEUE_BLOCKED ) 											\
+	{																					\
+		crSET_STATE0( ( xHandle ) );													\
+		*( pxResult ) = xQueueCRReceive( ( pxQueue) , ( pvBuffer ), 0 );				\
+	}																					\
+	if( *( pxResult ) == errQUEUE_YIELD )												\
+	{																					\
+		crSET_STATE1( ( xHandle ) );													\
+		*( pxResult ) = pdPASS;															\
+	}																					\
+}
+
+/**
+ * croutine. h
+ * <pre>
+  crQUEUE_SEND_FROM_ISR(
+                            QueueHandle_t pxQueue,
+                            void *pvItemToQueue,
+                            BaseType_t xCoRoutinePreviouslyWoken
+                       )</pre>
+ *
+ * The macro's crQUEUE_SEND_FROM_ISR() and crQUEUE_RECEIVE_FROM_ISR() are the
+ * co-routine equivalent to the xQueueSendFromISR() and xQueueReceiveFromISR()
+ * functions used by tasks.
+ *
+ * crQUEUE_SEND_FROM_ISR() and crQUEUE_RECEIVE_FROM_ISR() can only be used to
+ * pass data between a co-routine and and ISR, whereas xQueueSendFromISR() and
+ * xQueueReceiveFromISR() can only be used to pass data between a task and and
+ * ISR.
+ *
+ * crQUEUE_SEND_FROM_ISR can only be called from an ISR to send data to a queue
+ * that is being used from within a co-routine.
+ *
+ * See the co-routine section of the WEB documentation for information on
+ * passing data between tasks and co-routines and between ISR's and
+ * co-routines.
+ *
+ * @param xQueue The handle to the queue on which the item is to be posted.
+ *
+ * @param pvItemToQueue A pointer to the item that is to be placed on the
+ * queue.  The size of the items the queue will hold was defined when the
+ * queue was created, so this many bytes will be copied from pvItemToQueue
+ * into the queue storage area.
+ *
+ * @param xCoRoutinePreviouslyWoken This is included so an ISR can post onto
+ * the same queue multiple times from a single interrupt.  The first call
+ * should always pass in pdFALSE.  Subsequent calls should pass in
+ * the value returned from the previous call.
+ *
+ * @return pdTRUE if a co-routine was woken by posting onto the queue.  This is
+ * used by the ISR to determine if a context switch may be required following
+ * the ISR.
+ *
+ * Example usage:
+ <pre>
+ // A co-routine that blocks on a queue waiting for characters to be received.
+ static void vReceivingCoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )
+ {
+ char cRxedChar;
+ BaseType_t xResult;
+
+     // All co-routines must start with a call to crSTART().
+     crSTART( xHandle );
+
+     for( ;; )
+     {
+         // Wait for data to become available on the queue.  This assumes the
+         // queue xCommsRxQueue has already been created!
+         crQUEUE_RECEIVE( xHandle, xCommsRxQueue, &uxLEDToFlash, portMAX_DELAY, &xResult );
+
+         // Was a character received?
+         if( xResult == pdPASS )
+         {
+             // Process the character here.
+         }
+     }
+
+     // All co-routines must end with a call to crEND().
+     crEND();
+ }
+
+ // An ISR that uses a queue to send characters received on a serial port to
+ // a co-routine.
+ void vUART_ISR( void )
+ {
+ char cRxedChar;
+ BaseType_t xCRWokenByPost = pdFALSE;
+
+     // We loop around reading characters until there are none left in the UART.
+     while( UART_RX_REG_NOT_EMPTY() )
+     {
+         // Obtain the character from the UART.
+         cRxedChar = UART_RX_REG;
+
+         // Post the character onto a queue.  xCRWokenByPost will be pdFALSE
+         // the first time around the loop.  If the post causes a co-routine
+         // to be woken (unblocked) then xCRWokenByPost will be set to pdTRUE.
+         // In this manner we can ensure that if more than one co-routine is
+         // blocked on the queue only one is woken by this ISR no matter how
+         // many characters are posted to the queue.
+         xCRWokenByPost = crQUEUE_SEND_FROM_ISR( xCommsRxQueue, &cRxedChar, xCRWokenByPost );
+     }
+ }</pre>
+ * \defgroup crQUEUE_SEND_FROM_ISR crQUEUE_SEND_FROM_ISR
+ * \ingroup Tasks
+ */
+#define crQUEUE_SEND_FROM_ISR( pxQueue, pvItemToQueue, xCoRoutinePreviouslyWoken ) xQueueCRSendFromISR( ( pxQueue ), ( pvItemToQueue ), ( xCoRoutinePreviouslyWoken ) )
+
+
+/**
+ * croutine. h
+ * <pre>
+  crQUEUE_SEND_FROM_ISR(
+                            QueueHandle_t pxQueue,
+                            void *pvBuffer,
+                            BaseType_t * pxCoRoutineWoken
+                       )</pre>
+ *
+ * The macro's crQUEUE_SEND_FROM_ISR() and crQUEUE_RECEIVE_FROM_ISR() are the
+ * co-routine equivalent to the xQueueSendFromISR() and xQueueReceiveFromISR()
+ * functions used by tasks.
+ *
+ * crQUEUE_SEND_FROM_ISR() and crQUEUE_RECEIVE_FROM_ISR() can only be used to
+ * pass data between a co-routine and and ISR, whereas xQueueSendFromISR() and
+ * xQueueReceiveFromISR() can only be used to pass data between a task and and
+ * ISR.
+ *
+ * crQUEUE_RECEIVE_FROM_ISR can only be called from an ISR to receive data
+ * from a queue that is being used from within a co-routine (a co-routine
+ * posted to the queue).
+ *
+ * See the co-routine section of the WEB documentation for information on
+ * passing data between tasks and co-routines and between ISR's and
+ * co-routines.
+ *
+ * @param xQueue The handle to the queue on which the item is to be posted.
+ *
+ * @param pvBuffer A pointer to a buffer into which the received item will be
+ * placed.  The size of the items the queue will hold was defined when the
+ * queue was created, so this many bytes will be copied from the queue into
+ * pvBuffer.
+ *
+ * @param pxCoRoutineWoken A co-routine may be blocked waiting for space to become
+ * available on the queue.  If crQUEUE_RECEIVE_FROM_ISR causes such a
+ * co-routine to unblock *pxCoRoutineWoken will get set to pdTRUE, otherwise
+ * *pxCoRoutineWoken will remain unchanged.
+ *
+ * @return pdTRUE an item was successfully received from the queue, otherwise
+ * pdFALSE.
+ *
+ * Example usage:
+ <pre>
+ // A co-routine that posts a character to a queue then blocks for a fixed
+ // period.  The character is incremented each time.
+ static void vSendingCoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )
+ {
+ // cChar holds its value while this co-routine is blocked and must therefore
+ // be declared static.
+ static char cCharToTx = 'a';
+ BaseType_t xResult;
+
+     // All co-routines must start with a call to crSTART().
+     crSTART( xHandle );
+
+     for( ;; )
+     {
+         // Send the next character to the queue.
+         crQUEUE_SEND( xHandle, xCoRoutineQueue, &cCharToTx, NO_DELAY, &xResult );
+
+         if( xResult == pdPASS )
+         {
+             // The character was successfully posted to the queue.
+         }
+		 else
+		 {
+			// Could not post the character to the queue.
+		 }
+
+         // Enable the UART Tx interrupt to cause an interrupt in this
+		 // hypothetical UART.  The interrupt will obtain the character
+		 // from the queue and send it.
+		 ENABLE_RX_INTERRUPT();
+
+		 // Increment to the next character then block for a fixed period.
+		 // cCharToTx will maintain its value across the delay as it is
+		 // declared static.
+		 cCharToTx++;
+		 if( cCharToTx > 'x' )
+		 {
+			cCharToTx = 'a';
+		 }
+		 crDELAY( 100 );
+     }
+
+     // All co-routines must end with a call to crEND().
+     crEND();
+ }
+
+ // An ISR that uses a queue to receive characters to send on a UART.
+ void vUART_ISR( void )
+ {
+ char cCharToTx;
+ BaseType_t xCRWokenByPost = pdFALSE;
+
+     while( UART_TX_REG_EMPTY() )
+     {
+         // Are there any characters in the queue waiting to be sent?
+		 // xCRWokenByPost will automatically be set to pdTRUE if a co-routine
+		 // is woken by the post - ensuring that only a single co-routine is
+		 // woken no matter how many times we go around this loop.
+         if( crQUEUE_RECEIVE_FROM_ISR( pxQueue, &cCharToTx, &xCRWokenByPost ) )
+		 {
+			 SEND_CHARACTER( cCharToTx );
+		 }
+     }
+ }</pre>
+ * \defgroup crQUEUE_RECEIVE_FROM_ISR crQUEUE_RECEIVE_FROM_ISR
+ * \ingroup Tasks
+ */
+#define crQUEUE_RECEIVE_FROM_ISR( pxQueue, pvBuffer, pxCoRoutineWoken ) xQueueCRReceiveFromISR( ( pxQueue ), ( pvBuffer ), ( pxCoRoutineWoken ) )
+
+/*
+ * This function is intended for internal use by the co-routine macros only.
+ * The macro nature of the co-routine implementation requires that the
+ * prototype appears here.  The function should not be used by application
+ * writers.
+ *
+ * Removes the current co-routine from its ready list and places it in the
+ * appropriate delayed list.
+ */
+void vCoRoutineAddToDelayedList( TickType_t xTicksToDelay, List_t *pxEventList );
+
+/*
+ * This function is intended for internal use by the queue implementation only.
+ * The function should not be used by application writers.
+ *
+ * Removes the highest priority co-routine from the event list and places it in
+ * the pending ready list.
+ */
+BaseType_t xCoRoutineRemoveFromEventList( const List_t *pxEventList );
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* CO_ROUTINE_H */
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h b/Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h
new file mode 100644
index 0000000..e048e6c
--- /dev/null
+++ b/Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h
@@ -0,0 +1,279 @@
+/*
+ * FreeRTOS Kernel V10.3.1
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef DEPRECATED_DEFINITIONS_H
+#define DEPRECATED_DEFINITIONS_H
+
+
+/* Each FreeRTOS port has a unique portmacro.h header file.  Originally a
+pre-processor definition was used to ensure the pre-processor found the correct
+portmacro.h file for the port being used.  That scheme was deprecated in favour
+of setting the compiler's include path such that it found the correct
+portmacro.h file - removing the need for the constant and allowing the
+portmacro.h file to be located anywhere in relation to the port being used.  The
+definitions below remain in the code for backward compatibility only.  New
+projects should not use them. */
+
+#ifdef OPEN_WATCOM_INDUSTRIAL_PC_PORT
+	#include "..\..\Source\portable\owatcom\16bitdos\pc\portmacro.h"
+	typedef void ( __interrupt __far *pxISR )();
+#endif
+
+#ifdef OPEN_WATCOM_FLASH_LITE_186_PORT
+	#include "..\..\Source\portable\owatcom\16bitdos\flsh186\portmacro.h"
+	typedef void ( __interrupt __far *pxISR )();
+#endif
+
+#ifdef GCC_MEGA_AVR
+	#include "../portable/GCC/ATMega323/portmacro.h"
+#endif
+
+#ifdef IAR_MEGA_AVR
+	#include "../portable/IAR/ATMega323/portmacro.h"
+#endif
+
+#ifdef MPLAB_PIC24_PORT
+	#include "../../Source/portable/MPLAB/PIC24_dsPIC/portmacro.h"
+#endif
+
+#ifdef MPLAB_DSPIC_PORT
+	#include "../../Source/portable/MPLAB/PIC24_dsPIC/portmacro.h"
+#endif
+
+#ifdef MPLAB_PIC18F_PORT
+	#include "../../Source/portable/MPLAB/PIC18F/portmacro.h"
+#endif
+
+#ifdef MPLAB_PIC32MX_PORT
+	#include "../../Source/portable/MPLAB/PIC32MX/portmacro.h"
+#endif
+
+#ifdef _FEDPICC
+	#include "libFreeRTOS/Include/portmacro.h"
+#endif
+
+#ifdef SDCC_CYGNAL
+	#include "../../Source/portable/SDCC/Cygnal/portmacro.h"
+#endif
+
+#ifdef GCC_ARM7
+	#include "../../Source/portable/GCC/ARM7_LPC2000/portmacro.h"
+#endif
+
+#ifdef GCC_ARM7_ECLIPSE
+	#include "portmacro.h"
+#endif
+
+#ifdef ROWLEY_LPC23xx
+	#include "../../Source/portable/GCC/ARM7_LPC23xx/portmacro.h"
+#endif
+
+#ifdef IAR_MSP430
+	#include "..\..\Source\portable\IAR\MSP430\portmacro.h"
+#endif
+
+#ifdef GCC_MSP430
+	#include "../../Source/portable/GCC/MSP430F449/portmacro.h"
+#endif
+
+#ifdef ROWLEY_MSP430
+	#include "../../Source/portable/Rowley/MSP430F449/portmacro.h"
+#endif
+
+#ifdef ARM7_LPC21xx_KEIL_RVDS
+	#include "..\..\Source\portable\RVDS\ARM7_LPC21xx\portmacro.h"
+#endif
+
+#ifdef SAM7_GCC
+	#include "../../Source/portable/GCC/ARM7_AT91SAM7S/portmacro.h"
+#endif
+
+#ifdef SAM7_IAR
+	#include "..\..\Source\portable\IAR\AtmelSAM7S64\portmacro.h"
+#endif
+
+#ifdef SAM9XE_IAR
+	#include "..\..\Source\portable\IAR\AtmelSAM9XE\portmacro.h"
+#endif
+
+#ifdef LPC2000_IAR
+	#include "..\..\Source\portable\IAR\LPC2000\portmacro.h"
+#endif
+
+#ifdef STR71X_IAR
+	#include "..\..\Source\portable\IAR\STR71x\portmacro.h"
+#endif
+
+#ifdef STR75X_IAR
+	#include "..\..\Source\portable\IAR\STR75x\portmacro.h"
+#endif
+
+#ifdef STR75X_GCC
+	#include "..\..\Source\portable\GCC\STR75x\portmacro.h"
+#endif
+
+#ifdef STR91X_IAR
+	#include "..\..\Source\portable\IAR\STR91x\portmacro.h"
+#endif
+
+#ifdef GCC_H8S
+	#include "../../Source/portable/GCC/H8S2329/portmacro.h"
+#endif
+
+#ifdef GCC_AT91FR40008
+	#include "../../Source/portable/GCC/ARM7_AT91FR40008/portmacro.h"
+#endif
+
+#ifdef RVDS_ARMCM3_LM3S102
+	#include "../../Source/portable/RVDS/ARM_CM3/portmacro.h"
+#endif
+
+#ifdef GCC_ARMCM3_LM3S102
+	#include "../../Source/portable/GCC/ARM_CM3/portmacro.h"
+#endif
+
+#ifdef GCC_ARMCM3
+	#include "../../Source/portable/GCC/ARM_CM3/portmacro.h"
+#endif
+
+#ifdef IAR_ARM_CM3
+	#include "../../Source/portable/IAR/ARM_CM3/portmacro.h"
+#endif
+
+#ifdef IAR_ARMCM3_LM
+	#include "../../Source/portable/IAR/ARM_CM3/portmacro.h"
+#endif
+
+#ifdef HCS12_CODE_WARRIOR
+	#include "../../Source/portable/CodeWarrior/HCS12/portmacro.h"
+#endif
+
+#ifdef MICROBLAZE_GCC
+	#include "../../Source/portable/GCC/MicroBlaze/portmacro.h"
+#endif
+
+#ifdef TERN_EE
+	#include "..\..\Source\portable\Paradigm\Tern_EE\small\portmacro.h"
+#endif
+
+#ifdef GCC_HCS12
+	#include "../../Source/portable/GCC/HCS12/portmacro.h"
+#endif
+
+#ifdef GCC_MCF5235
+    #include "../../Source/portable/GCC/MCF5235/portmacro.h"
+#endif
+
+#ifdef COLDFIRE_V2_GCC
+	#include "../../../Source/portable/GCC/ColdFire_V2/portmacro.h"
+#endif
+
+#ifdef COLDFIRE_V2_CODEWARRIOR
+	#include "../../Source/portable/CodeWarrior/ColdFire_V2/portmacro.h"
+#endif
+
+#ifdef GCC_PPC405
+	#include "../../Source/portable/GCC/PPC405_Xilinx/portmacro.h"
+#endif
+
+#ifdef GCC_PPC440
+	#include "../../Source/portable/GCC/PPC440_Xilinx/portmacro.h"
+#endif
+
+#ifdef _16FX_SOFTUNE
+	#include "..\..\Source\portable\Softune\MB96340\portmacro.h"
+#endif
+
+#ifdef BCC_INDUSTRIAL_PC_PORT
+	/* A short file name has to be used in place of the normal
+	FreeRTOSConfig.h when using the Borland compiler. */
+	#include "frconfig.h"
+	#include "..\portable\BCC\16BitDOS\PC\prtmacro.h"
+    typedef void ( __interrupt __far *pxISR )();
+#endif
+
+#ifdef BCC_FLASH_LITE_186_PORT
+	/* A short file name has to be used in place of the normal
+	FreeRTOSConfig.h when using the Borland compiler. */
+	#include "frconfig.h"
+	#include "..\portable\BCC\16BitDOS\flsh186\prtmacro.h"
+    typedef void ( __interrupt __far *pxISR )();
+#endif
+
+#ifdef __GNUC__
+   #ifdef __AVR32_AVR32A__
+	   #include "portmacro.h"
+   #endif
+#endif
+
+#ifdef __ICCAVR32__
+   #ifdef __CORE__
+      #if __CORE__ == __AVR32A__
+	      #include "portmacro.h"
+      #endif
+   #endif
+#endif
+
+#ifdef __91467D
+	#include "portmacro.h"
+#endif
+
+#ifdef __96340
+	#include "portmacro.h"
+#endif
+
+
+#ifdef __IAR_V850ES_Fx3__
+	#include "../../Source/portable/IAR/V850ES/portmacro.h"
+#endif
+
+#ifdef __IAR_V850ES_Jx3__
+	#include "../../Source/portable/IAR/V850ES/portmacro.h"
+#endif
+
+#ifdef __IAR_V850ES_Jx3_L__
+	#include "../../Source/portable/IAR/V850ES/portmacro.h"
+#endif
+
+#ifdef __IAR_V850ES_Jx2__
+	#include "../../Source/portable/IAR/V850ES/portmacro.h"
+#endif
+
+#ifdef __IAR_V850ES_Hx2__
+	#include "../../Source/portable/IAR/V850ES/portmacro.h"
+#endif
+
+#ifdef __IAR_78K0R_Kx3__
+	#include "../../Source/portable/IAR/78K0R/portmacro.h"
+#endif
+
+#ifdef __IAR_78K0R_Kx3L__
+	#include "../../Source/portable/IAR/78K0R/portmacro.h"
+#endif
+
+#endif /* DEPRECATED_DEFINITIONS_H */
+
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/include/event_groups.h b/Middlewares/Third_Party/FreeRTOS/Source/include/event_groups.h
new file mode 100644
index 0000000..bf8a985
--- /dev/null
+++ b/Middlewares/Third_Party/FreeRTOS/Source/include/event_groups.h
@@ -0,0 +1,757 @@
+/*
+ * FreeRTOS Kernel V10.3.1
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef EVENT_GROUPS_H
+#define EVENT_GROUPS_H
+
+#ifndef INC_FREERTOS_H
+	#error "include FreeRTOS.h" must appear in source files before "include event_groups.h"
+#endif
+
+/* FreeRTOS includes. */
+#include "timers.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * An event group is a collection of bits to which an application can assign a
+ * meaning.  For example, an application may create an event group to convey
+ * the status of various CAN bus related events in which bit 0 might mean "A CAN
+ * message has been received and is ready for processing", bit 1 might mean "The
+ * application has queued a message that is ready for sending onto the CAN
+ * network", and bit 2 might mean "It is time to send a SYNC message onto the
+ * CAN network" etc.  A task can then test the bit values to see which events
+ * are active, and optionally enter the Blocked state to wait for a specified
+ * bit or a group of specified bits to be active.  To continue the CAN bus
+ * example, a CAN controlling task can enter the Blocked state (and therefore
+ * not consume any processing time) until either bit 0, bit 1 or bit 2 are
+ * active, at which time the bit that was actually active would inform the task
+ * which action it had to take (process a received message, send a message, or
+ * send a SYNC).
+ *
+ * The event groups implementation contains intelligence to avoid race
+ * conditions that would otherwise occur were an application to use a simple
+ * variable for the same purpose.  This is particularly important with respect
+ * to when a bit within an event group is to be cleared, and when bits have to
+ * be set and then tested atomically - as is the case where event groups are
+ * used to create a synchronisation point between multiple tasks (a
+ * 'rendezvous').
+ *
+ * \defgroup EventGroup
+ */
+
+
+
+/**
+ * event_groups.h
+ *
+ * Type by which event groups are referenced.  For example, a call to
+ * xEventGroupCreate() returns an EventGroupHandle_t variable that can then
+ * be used as a parameter to other event group functions.
+ *
+ * \defgroup EventGroupHandle_t EventGroupHandle_t
+ * \ingroup EventGroup
+ */
+struct EventGroupDef_t;
+typedef struct EventGroupDef_t * EventGroupHandle_t;
+
+/*
+ * The type that holds event bits always matches TickType_t - therefore the
+ * number of bits it holds is set by configUSE_16_BIT_TICKS (16 bits if set to 1,
+ * 32 bits if set to 0.
+ *
+ * \defgroup EventBits_t EventBits_t
+ * \ingroup EventGroup
+ */
+typedef TickType_t EventBits_t;
+
+/**
+ * event_groups.h
+ *<pre>
+ EventGroupHandle_t xEventGroupCreate( void );
+ </pre>
+ *
+ * Create a new event group.
+ *
+ * Internally, within the FreeRTOS implementation, event groups use a [small]
+ * block of memory, in which the event group's structure is stored.  If an event
+ * groups is created using xEventGropuCreate() then the required memory is
+ * automatically dynamically allocated inside the xEventGroupCreate() function.
+ * (see http://www.freertos.org/a00111.html).  If an event group is created
+ * using xEventGropuCreateStatic() then the application writer must instead
+ * provide the memory that will get used by the event group.
+ * xEventGroupCreateStatic() therefore allows an event group to be created
+ * without using any dynamic memory allocation.
+ *
+ * Although event groups are not related to ticks, for internal implementation
+ * reasons the number of bits available for use in an event group is dependent
+ * on the configUSE_16_BIT_TICKS setting in FreeRTOSConfig.h.  If
+ * configUSE_16_BIT_TICKS is 1 then each event group contains 8 usable bits (bit
+ * 0 to bit 7).  If configUSE_16_BIT_TICKS is set to 0 then each event group has
+ * 24 usable bits (bit 0 to bit 23).  The EventBits_t type is used to store
+ * event bits within an event group.
+ *
+ * @return If the event group was created then a handle to the event group is
+ * returned.  If there was insufficient FreeRTOS heap available to create the
+ * event group then NULL is returned.  See http://www.freertos.org/a00111.html
+ *
+ * Example usage:
+   <pre>
+	// Declare a variable to hold the created event group.
+	EventGroupHandle_t xCreatedEventGroup;
+
+	// Attempt to create the event group.
+	xCreatedEventGroup = xEventGroupCreate();
+
+	// Was the event group created successfully?
+	if( xCreatedEventGroup == NULL )
+	{
+		// The event group was not created because there was insufficient
+		// FreeRTOS heap available.
+	}
+	else
+	{
+		// The event group was created.
+	}
+   </pre>
+ * \defgroup xEventGroupCreate xEventGroupCreate
+ * \ingroup EventGroup
+ */
+#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+	EventGroupHandle_t xEventGroupCreate( void ) PRIVILEGED_FUNCTION;
+#endif
+
+/**
+ * event_groups.h
+ *<pre>
+ EventGroupHandle_t xEventGroupCreateStatic( EventGroupHandle_t * pxEventGroupBuffer );
+ </pre>
+ *
+ * Create a new event group.
+ *
+ * Internally, within the FreeRTOS implementation, event groups use a [small]
+ * block of memory, in which the event group's structure is stored.  If an event
+ * groups is created using xEventGropuCreate() then the required memory is
+ * automatically dynamically allocated inside the xEventGroupCreate() function.
+ * (see http://www.freertos.org/a00111.html).  If an event group is created
+ * using xEventGropuCreateStatic() then the application writer must instead
+ * provide the memory that will get used by the event group.
+ * xEventGroupCreateStatic() therefore allows an event group to be created
+ * without using any dynamic memory allocation.
+ *
+ * Although event groups are not related to ticks, for internal implementation
+ * reasons the number of bits available for use in an event group is dependent
+ * on the configUSE_16_BIT_TICKS setting in FreeRTOSConfig.h.  If
+ * configUSE_16_BIT_TICKS is 1 then each event group contains 8 usable bits (bit
+ * 0 to bit 7).  If configUSE_16_BIT_TICKS is set to 0 then each event group has
+ * 24 usable bits (bit 0 to bit 23).  The EventBits_t type is used to store
+ * event bits within an event group.
+ *
+ * @param pxEventGroupBuffer pxEventGroupBuffer must point to a variable of type
+ * StaticEventGroup_t, which will be then be used to hold the event group's data
+ * structures, removing the need for the memory to be allocated dynamically.
+ *
+ * @return If the event group was created then a handle to the event group is
+ * returned.  If pxEventGroupBuffer was NULL then NULL is returned.
+ *
+ * Example usage:
+   <pre>
+	// StaticEventGroup_t is a publicly accessible structure that has the same
+	// size and alignment requirements as the real event group structure.  It is
+	// provided as a mechanism for applications to know the size of the event
+	// group (which is dependent on the architecture and configuration file
+	// settings) without breaking the strict data hiding policy by exposing the
+	// real event group internals.  This StaticEventGroup_t variable is passed
+	// into the xSemaphoreCreateEventGroupStatic() function and is used to store
+	// the event group's data structures
+	StaticEventGroup_t xEventGroupBuffer;
+
+	// Create the event group without dynamically allocating any memory.
+	xEventGroup = xEventGroupCreateStatic( &xEventGroupBuffer );
+   </pre>
+ */
+#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+	EventGroupHandle_t xEventGroupCreateStatic( StaticEventGroup_t *pxEventGroupBuffer ) PRIVILEGED_FUNCTION;
+#endif
+
+/**
+ * event_groups.h
+ *<pre>
+	EventBits_t xEventGroupWaitBits( 	EventGroupHandle_t xEventGroup,
+										const EventBits_t uxBitsToWaitFor,
+										const BaseType_t xClearOnExit,
+										const BaseType_t xWaitForAllBits,
+										const TickType_t xTicksToWait );
+ </pre>
+ *
+ * [Potentially] block to wait for one or more bits to be set within a
+ * previously created event group.
+ *
+ * This function cannot be called from an interrupt.
+ *
+ * @param xEventGroup The event group in which the bits are being tested.  The
+ * event group must have previously been created using a call to
+ * xEventGroupCreate().
+ *
+ * @param uxBitsToWaitFor A bitwise value that indicates the bit or bits to test
+ * inside the event group.  For example, to wait for bit 0 and/or bit 2 set
+ * uxBitsToWaitFor to 0x05.  To wait for bits 0 and/or bit 1 and/or bit 2 set
+ * uxBitsToWaitFor to 0x07.  Etc.
+ *
+ * @param xClearOnExit If xClearOnExit is set to pdTRUE then any bits within
+ * uxBitsToWaitFor that are set within the event group will be cleared before
+ * xEventGroupWaitBits() returns if the wait condition was met (if the function
+ * returns for a reason other than a timeout).  If xClearOnExit is set to
+ * pdFALSE then the bits set in the event group are not altered when the call to
+ * xEventGroupWaitBits() returns.
+ *
+ * @param xWaitForAllBits If xWaitForAllBits is set to pdTRUE then
+ * xEventGroupWaitBits() will return when either all the bits in uxBitsToWaitFor
+ * are set or the specified block time expires.  If xWaitForAllBits is set to
+ * pdFALSE then xEventGroupWaitBits() will return when any one of the bits set
+ * in uxBitsToWaitFor is set or the specified block time expires.  The block
+ * time is specified by the xTicksToWait parameter.
+ *
+ * @param xTicksToWait The maximum amount of time (specified in 'ticks') to wait
+ * for one/all (depending on the xWaitForAllBits value) of the bits specified by
+ * uxBitsToWaitFor to become set.
+ *
+ * @return The value of the event group at the time either the bits being waited
+ * for became set, or the block time expired.  Test the return value to know
+ * which bits were set.  If xEventGroupWaitBits() returned because its timeout
+ * expired then not all the bits being waited for will be set.  If
+ * xEventGroupWaitBits() returned because the bits it was waiting for were set
+ * then the returned value is the event group value before any bits were
+ * automatically cleared in the case that xClearOnExit parameter was set to
+ * pdTRUE.
+ *
+ * Example usage:
+   <pre>
+   #define BIT_0	( 1 << 0 )
+   #define BIT_4	( 1 << 4 )
+
+   void aFunction( EventGroupHandle_t xEventGroup )
+   {
+   EventBits_t uxBits;
+   const TickType_t xTicksToWait = 100 / portTICK_PERIOD_MS;
+
+		// Wait a maximum of 100ms for either bit 0 or bit 4 to be set within
+		// the event group.  Clear the bits before exiting.
+		uxBits = xEventGroupWaitBits(
+					xEventGroup,	// The event group being tested.
+					BIT_0 | BIT_4,	// The bits within the event group to wait for.
+					pdTRUE,			// BIT_0 and BIT_4 should be cleared before returning.
+					pdFALSE,		// Don't wait for both bits, either bit will do.
+					xTicksToWait );	// Wait a maximum of 100ms for either bit to be set.
+
+		if( ( uxBits & ( BIT_0 | BIT_4 ) ) == ( BIT_0 | BIT_4 ) )
+		{
+			// xEventGroupWaitBits() returned because both bits were set.
+		}
+		else if( ( uxBits & BIT_0 ) != 0 )
+		{
+			// xEventGroupWaitBits() returned because just BIT_0 was set.
+		}
+		else if( ( uxBits & BIT_4 ) != 0 )
+		{
+			// xEventGroupWaitBits() returned because just BIT_4 was set.
+		}
+		else
+		{
+			// xEventGroupWaitBits() returned because xTicksToWait ticks passed
+			// without either BIT_0 or BIT_4 becoming set.
+		}
+   }
+   </pre>
+ * \defgroup xEventGroupWaitBits xEventGroupWaitBits
+ * \ingroup EventGroup
+ */
+EventBits_t xEventGroupWaitBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToWaitFor, const BaseType_t xClearOnExit, const BaseType_t xWaitForAllBits, TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+
+/**
+ * event_groups.h
+ *<pre>
+	EventBits_t xEventGroupClearBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToClear );
+ </pre>
+ *
+ * Clear bits within an event group.  This function cannot be called from an
+ * interrupt.
+ *
+ * @param xEventGroup The event group in which the bits are to be cleared.
+ *
+ * @param uxBitsToClear A bitwise value that indicates the bit or bits to clear
+ * in the event group.  For example, to clear bit 3 only, set uxBitsToClear to
+ * 0x08.  To clear bit 3 and bit 0 set uxBitsToClear to 0x09.
+ *
+ * @return The value of the event group before the specified bits were cleared.
+ *
+ * Example usage:
+   <pre>
+   #define BIT_0	( 1 << 0 )
+   #define BIT_4	( 1 << 4 )
+
+   void aFunction( EventGroupHandle_t xEventGroup )
+   {
+   EventBits_t uxBits;
+
+		// Clear bit 0 and bit 4 in xEventGroup.
+		uxBits = xEventGroupClearBits(
+								xEventGroup,	// The event group being updated.
+								BIT_0 | BIT_4 );// The bits being cleared.
+
+		if( ( uxBits & ( BIT_0 | BIT_4 ) ) == ( BIT_0 | BIT_4 ) )
+		{
+			// Both bit 0 and bit 4 were set before xEventGroupClearBits() was
+			// called.  Both will now be clear (not set).
+		}
+		else if( ( uxBits & BIT_0 ) != 0 )
+		{
+			// Bit 0 was set before xEventGroupClearBits() was called.  It will
+			// now be clear.
+		}
+		else if( ( uxBits & BIT_4 ) != 0 )
+		{
+			// Bit 4 was set before xEventGroupClearBits() was called.  It will
+			// now be clear.
+		}
+		else
+		{
+			// Neither bit 0 nor bit 4 were set in the first place.
+		}
+   }
+   </pre>
+ * \defgroup xEventGroupClearBits xEventGroupClearBits
+ * \ingroup EventGroup
+ */
+EventBits_t xEventGroupClearBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToClear ) PRIVILEGED_FUNCTION;
+
+/**
+ * event_groups.h
+ *<pre>
+	BaseType_t xEventGroupClearBitsFromISR( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet );
+ </pre>
+ *
+ * A version of xEventGroupClearBits() that can be called from an interrupt.
+ *
+ * Setting bits in an event group is not a deterministic operation because there
+ * are an unknown number of tasks that may be waiting for the bit or bits being
+ * set.  FreeRTOS does not allow nondeterministic operations to be performed
+ * while interrupts are disabled, so protects event groups that are accessed
+ * from tasks by suspending the scheduler rather than disabling interrupts.  As
+ * a result event groups cannot be accessed directly from an interrupt service
+ * routine.  Therefore xEventGroupClearBitsFromISR() sends a message to the
+ * timer task to have the clear operation performed in the context of the timer
+ * task.
+ *
+ * @param xEventGroup The event group in which the bits are to be cleared.
+ *
+ * @param uxBitsToClear A bitwise value that indicates the bit or bits to clear.
+ * For example, to clear bit 3 only, set uxBitsToClear to 0x08.  To clear bit 3
+ * and bit 0 set uxBitsToClear to 0x09.
+ *
+ * @return If the request to execute the function was posted successfully then
+ * pdPASS is returned, otherwise pdFALSE is returned.  pdFALSE will be returned
+ * if the timer service queue was full.
+ *
+ * Example usage:
+   <pre>
+   #define BIT_0	( 1 << 0 )
+   #define BIT_4	( 1 << 4 )
+
+   // An event group which it is assumed has already been created by a call to
+   // xEventGroupCreate().
+   EventGroupHandle_t xEventGroup;
+
+   void anInterruptHandler( void )
+   {
+		// Clear bit 0 and bit 4 in xEventGroup.
+		xResult = xEventGroupClearBitsFromISR(
+							xEventGroup,	 // The event group being updated.
+							BIT_0 | BIT_4 ); // The bits being set.
+
+		if( xResult == pdPASS )
+		{
+			// The message was posted successfully.
+		}
+  }
+   </pre>
+ * \defgroup xEventGroupClearBitsFromISR xEventGroupClearBitsFromISR
+ * \ingroup EventGroup
+ */
+#if( configUSE_TRACE_FACILITY == 1 )
+	BaseType_t xEventGroupClearBitsFromISR( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToClear ) PRIVILEGED_FUNCTION;
+#else
+	#define xEventGroupClearBitsFromISR( xEventGroup, uxBitsToClear ) xTimerPendFunctionCallFromISR( vEventGroupClearBitsCallback, ( void * ) xEventGroup, ( uint32_t ) uxBitsToClear, NULL )
+#endif
+
+/**
+ * event_groups.h
+ *<pre>
+	EventBits_t xEventGroupSetBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet );
+ </pre>
+ *
+ * Set bits within an event group.
+ * This function cannot be called from an interrupt.  xEventGroupSetBitsFromISR()
+ * is a version that can be called from an interrupt.
+ *
+ * Setting bits in an event group will automatically unblock tasks that are
+ * blocked waiting for the bits.
+ *
+ * @param xEventGroup The event group in which the bits are to be set.
+ *
+ * @param uxBitsToSet A bitwise value that indicates the bit or bits to set.
+ * For example, to set bit 3 only, set uxBitsToSet to 0x08.  To set bit 3
+ * and bit 0 set uxBitsToSet to 0x09.
+ *
+ * @return The value of the event group at the time the call to
+ * xEventGroupSetBits() returns.  There are two reasons why the returned value
+ * might have the bits specified by the uxBitsToSet parameter cleared.  First,
+ * if setting a bit results in a task that was waiting for the bit leaving the
+ * blocked state then it is possible the bit will be cleared automatically
+ * (see the xClearBitOnExit parameter of xEventGroupWaitBits()).  Second, any
+ * unblocked (or otherwise Ready state) task that has a priority above that of
+ * the task that called xEventGroupSetBits() will execute and may change the
+ * event group value before the call to xEventGroupSetBits() returns.
+ *
+ * Example usage:
+   <pre>
+   #define BIT_0	( 1 << 0 )
+   #define BIT_4	( 1 << 4 )
+
+   void aFunction( EventGroupHandle_t xEventGroup )
+   {
+   EventBits_t uxBits;
+
+		// Set bit 0 and bit 4 in xEventGroup.
+		uxBits = xEventGroupSetBits(
+							xEventGroup,	// The event group being updated.
+							BIT_0 | BIT_4 );// The bits being set.
+
+		if( ( uxBits & ( BIT_0 | BIT_4 ) ) == ( BIT_0 | BIT_4 ) )
+		{
+			// Both bit 0 and bit 4 remained set when the function returned.
+		}
+		else if( ( uxBits & BIT_0 ) != 0 )
+		{
+			// Bit 0 remained set when the function returned, but bit 4 was
+			// cleared.  It might be that bit 4 was cleared automatically as a
+			// task that was waiting for bit 4 was removed from the Blocked
+			// state.
+		}
+		else if( ( uxBits & BIT_4 ) != 0 )
+		{
+			// Bit 4 remained set when the function returned, but bit 0 was
+			// cleared.  It might be that bit 0 was cleared automatically as a
+			// task that was waiting for bit 0 was removed from the Blocked
+			// state.
+		}
+		else
+		{
+			// Neither bit 0 nor bit 4 remained set.  It might be that a task
+			// was waiting for both of the bits to be set, and the bits were
+			// cleared as the task left the Blocked state.
+		}
+   }
+   </pre>
+ * \defgroup xEventGroupSetBits xEventGroupSetBits
+ * \ingroup EventGroup
+ */
+EventBits_t xEventGroupSetBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet ) PRIVILEGED_FUNCTION;
+
+/**
+ * event_groups.h
+ *<pre>
+	BaseType_t xEventGroupSetBitsFromISR( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet, BaseType_t *pxHigherPriorityTaskWoken );
+ </pre>
+ *
+ * A version of xEventGroupSetBits() that can be called from an interrupt.
+ *
+ * Setting bits in an event group is not a deterministic operation because there
+ * are an unknown number of tasks that may be waiting for the bit or bits being
+ * set.  FreeRTOS does not allow nondeterministic operations to be performed in
+ * interrupts or from critical sections.  Therefore xEventGroupSetBitsFromISR()
+ * sends a message to the timer task to have the set operation performed in the
+ * context of the timer task - where a scheduler lock is used in place of a
+ * critical section.
+ *
+ * @param xEventGroup The event group in which the bits are to be set.
+ *
+ * @param uxBitsToSet A bitwise value that indicates the bit or bits to set.
+ * For example, to set bit 3 only, set uxBitsToSet to 0x08.  To set bit 3
+ * and bit 0 set uxBitsToSet to 0x09.
+ *
+ * @param pxHigherPriorityTaskWoken As mentioned above, calling this function
+ * will result in a message being sent to the timer daemon task.  If the
+ * priority of the timer daemon task is higher than the priority of the
+ * currently running task (the task the interrupt interrupted) then
+ * *pxHigherPriorityTaskWoken will be set to pdTRUE by
+ * xEventGroupSetBitsFromISR(), indicating that a context switch should be
+ * requested before the interrupt exits.  For that reason
+ * *pxHigherPriorityTaskWoken must be initialised to pdFALSE.  See the
+ * example code below.
+ *
+ * @return If the request to execute the function was posted successfully then
+ * pdPASS is returned, otherwise pdFALSE is returned.  pdFALSE will be returned
+ * if the timer service queue was full.
+ *
+ * Example usage:
+   <pre>
+   #define BIT_0	( 1 << 0 )
+   #define BIT_4	( 1 << 4 )
+
+   // An event group which it is assumed has already been created by a call to
+   // xEventGroupCreate().
+   EventGroupHandle_t xEventGroup;
+
+   void anInterruptHandler( void )
+   {
+   BaseType_t xHigherPriorityTaskWoken, xResult;
+
+		// xHigherPriorityTaskWoken must be initialised to pdFALSE.
+		xHigherPriorityTaskWoken = pdFALSE;
+
+		// Set bit 0 and bit 4 in xEventGroup.
+		xResult = xEventGroupSetBitsFromISR(
+							xEventGroup,	// The event group being updated.
+							BIT_0 | BIT_4   // The bits being set.
+							&xHigherPriorityTaskWoken );
+
+		// Was the message posted successfully?
+		if( xResult == pdPASS )
+		{
+			// If xHigherPriorityTaskWoken is now set to pdTRUE then a context
+			// switch should be requested.  The macro used is port specific and
+			// will be either portYIELD_FROM_ISR() or portEND_SWITCHING_ISR() -
+			// refer to the documentation page for the port being used.
+			portYIELD_FROM_ISR( xHigherPriorityTaskWoken );
+		}
+  }
+   </pre>
+ * \defgroup xEventGroupSetBitsFromISR xEventGroupSetBitsFromISR
+ * \ingroup EventGroup
+ */
+#if( configUSE_TRACE_FACILITY == 1 )
+	BaseType_t xEventGroupSetBitsFromISR( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet, BaseType_t *pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;
+#else
+	#define xEventGroupSetBitsFromISR( xEventGroup, uxBitsToSet, pxHigherPriorityTaskWoken ) xTimerPendFunctionCallFromISR( vEventGroupSetBitsCallback, ( void * ) xEventGroup, ( uint32_t ) uxBitsToSet, pxHigherPriorityTaskWoken )
+#endif
+
+/**
+ * event_groups.h
+ *<pre>
+	EventBits_t xEventGroupSync(	EventGroupHandle_t xEventGroup,
+									const EventBits_t uxBitsToSet,
+									const EventBits_t uxBitsToWaitFor,
+									TickType_t xTicksToWait );
+ </pre>
+ *
+ * Atomically set bits within an event group, then wait for a combination of
+ * bits to be set within the same event group.  This functionality is typically
+ * used to synchronise multiple tasks, where each task has to wait for the other
+ * tasks to reach a synchronisation point before proceeding.
+ *
+ * This function cannot be used from an interrupt.
+ *
+ * The function will return before its block time expires if the bits specified
+ * by the uxBitsToWait parameter are set, or become set within that time.  In
+ * this case all the bits specified by uxBitsToWait will be automatically
+ * cleared before the function returns.
+ *
+ * @param xEventGroup The event group in which the bits are being tested.  The
+ * event group must have previously been created using a call to
+ * xEventGroupCreate().
+ *
+ * @param uxBitsToSet The bits to set in the event group before determining
+ * if, and possibly waiting for, all the bits specified by the uxBitsToWait
+ * parameter are set.
+ *
+ * @param uxBitsToWaitFor A bitwise value that indicates the bit or bits to test
+ * inside the event group.  For example, to wait for bit 0 and bit 2 set
+ * uxBitsToWaitFor to 0x05.  To wait for bits 0 and bit 1 and bit 2 set
+ * uxBitsToWaitFor to 0x07.  Etc.
+ *
+ * @param xTicksToWait The maximum amount of time (specified in 'ticks') to wait
+ * for all of the bits specified by uxBitsToWaitFor to become set.
+ *
+ * @return The value of the event group at the time either the bits being waited
+ * for became set, or the block time expired.  Test the return value to know
+ * which bits were set.  If xEventGroupSync() returned because its timeout
+ * expired then not all the bits being waited for will be set.  If
+ * xEventGroupSync() returned because all the bits it was waiting for were
+ * set then the returned value is the event group value before any bits were
+ * automatically cleared.
+ *
+ * Example usage:
+ <pre>
+ // Bits used by the three tasks.
+ #define TASK_0_BIT		( 1 << 0 )
+ #define TASK_1_BIT		( 1 << 1 )
+ #define TASK_2_BIT		( 1 << 2 )
+
+ #define ALL_SYNC_BITS ( TASK_0_BIT | TASK_1_BIT | TASK_2_BIT )
+
+ // Use an event group to synchronise three tasks.  It is assumed this event
+ // group has already been created elsewhere.
+ EventGroupHandle_t xEventBits;
+
+ void vTask0( void *pvParameters )
+ {
+ EventBits_t uxReturn;
+ TickType_t xTicksToWait = 100 / portTICK_PERIOD_MS;
+
+	 for( ;; )
+	 {
+		// Perform task functionality here.
+
+		// Set bit 0 in the event flag to note this task has reached the
+		// sync point.  The other two tasks will set the other two bits defined
+		// by ALL_SYNC_BITS.  All three tasks have reached the synchronisation
+		// point when all the ALL_SYNC_BITS are set.  Wait a maximum of 100ms
+		// for this to happen.
+		uxReturn = xEventGroupSync( xEventBits, TASK_0_BIT, ALL_SYNC_BITS, xTicksToWait );
+
+		if( ( uxReturn & ALL_SYNC_BITS ) == ALL_SYNC_BITS )
+		{
+			// All three tasks reached the synchronisation point before the call
+			// to xEventGroupSync() timed out.
+		}
+	}
+ }
+
+ void vTask1( void *pvParameters )
+ {
+	 for( ;; )
+	 {
+		// Perform task functionality here.
+
+		// Set bit 1 in the event flag to note this task has reached the
+		// synchronisation point.  The other two tasks will set the other two
+		// bits defined by ALL_SYNC_BITS.  All three tasks have reached the
+		// synchronisation point when all the ALL_SYNC_BITS are set.  Wait
+		// indefinitely for this to happen.
+		xEventGroupSync( xEventBits, TASK_1_BIT, ALL_SYNC_BITS, portMAX_DELAY );
+
+		// xEventGroupSync() was called with an indefinite block time, so
+		// this task will only reach here if the syncrhonisation was made by all
+		// three tasks, so there is no need to test the return value.
+	 }
+ }
+
+ void vTask2( void *pvParameters )
+ {
+	 for( ;; )
+	 {
+		// Perform task functionality here.
+
+		// Set bit 2 in the event flag to note this task has reached the
+		// synchronisation point.  The other two tasks will set the other two
+		// bits defined by ALL_SYNC_BITS.  All three tasks have reached the
+		// synchronisation point when all the ALL_SYNC_BITS are set.  Wait
+		// indefinitely for this to happen.
+		xEventGroupSync( xEventBits, TASK_2_BIT, ALL_SYNC_BITS, portMAX_DELAY );
+
+		// xEventGroupSync() was called with an indefinite block time, so
+		// this task will only reach here if the syncrhonisation was made by all
+		// three tasks, so there is no need to test the return value.
+	}
+ }
+
+ </pre>
+ * \defgroup xEventGroupSync xEventGroupSync
+ * \ingroup EventGroup
+ */
+EventBits_t xEventGroupSync( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet, const EventBits_t uxBitsToWaitFor, TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+
+
+/**
+ * event_groups.h
+ *<pre>
+	EventBits_t xEventGroupGetBits( EventGroupHandle_t xEventGroup );
+ </pre>
+ *
+ * Returns the current value of the bits in an event group.  This function
+ * cannot be used from an interrupt.
+ *
+ * @param xEventGroup The event group being queried.
+ *
+ * @return The event group bits at the time xEventGroupGetBits() was called.
+ *
+ * \defgroup xEventGroupGetBits xEventGroupGetBits
+ * \ingroup EventGroup
+ */
+#define xEventGroupGetBits( xEventGroup ) xEventGroupClearBits( xEventGroup, 0 )
+
+/**
+ * event_groups.h
+ *<pre>
+	EventBits_t xEventGroupGetBitsFromISR( EventGroupHandle_t xEventGroup );
+ </pre>
+ *
+ * A version of xEventGroupGetBits() that can be called from an ISR.
+ *
+ * @param xEventGroup The event group being queried.
+ *
+ * @return The event group bits at the time xEventGroupGetBitsFromISR() was called.
+ *
+ * \defgroup xEventGroupGetBitsFromISR xEventGroupGetBitsFromISR
+ * \ingroup EventGroup
+ */
+EventBits_t xEventGroupGetBitsFromISR( EventGroupHandle_t xEventGroup ) PRIVILEGED_FUNCTION;
+
+/**
+ * event_groups.h
+ *<pre>
+	void xEventGroupDelete( EventGroupHandle_t xEventGroup );
+ </pre>
+ *
+ * Delete an event group that was previously created by a call to
+ * xEventGroupCreate().  Tasks that are blocked on the event group will be
+ * unblocked and obtain 0 as the event group's value.
+ *
+ * @param xEventGroup The event group being deleted.
+ */
+void vEventGroupDelete( EventGroupHandle_t xEventGroup ) PRIVILEGED_FUNCTION;
+
+/* For internal use only. */
+void vEventGroupSetBitsCallback( void *pvEventGroup, const uint32_t ulBitsToSet ) PRIVILEGED_FUNCTION;
+void vEventGroupClearBitsCallback( void *pvEventGroup, const uint32_t ulBitsToClear ) PRIVILEGED_FUNCTION;
+
+
+#if (configUSE_TRACE_FACILITY == 1)
+	UBaseType_t uxEventGroupGetNumber( void* xEventGroup ) PRIVILEGED_FUNCTION;
+	void vEventGroupSetNumber( void* xEventGroup, UBaseType_t uxEventGroupNumber ) PRIVILEGED_FUNCTION;
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* EVENT_GROUPS_H */
+
+
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/include/list.h b/Middlewares/Third_Party/FreeRTOS/Source/include/list.h
new file mode 100644
index 0000000..0598a93
--- /dev/null
+++ b/Middlewares/Third_Party/FreeRTOS/Source/include/list.h
@@ -0,0 +1,412 @@
+/*
+ * FreeRTOS Kernel V10.3.1
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*
+ * This is the list implementation used by the scheduler.  While it is tailored
+ * heavily for the schedulers needs, it is also available for use by
+ * application code.
+ *
+ * list_ts can only store pointers to list_item_ts.  Each ListItem_t contains a
+ * numeric value (xItemValue).  Most of the time the lists are sorted in
+ * descending item value order.
+ *
+ * Lists are created already containing one list item.  The value of this
+ * item is the maximum possible that can be stored, it is therefore always at
+ * the end of the list and acts as a marker.  The list member pxHead always
+ * points to this marker - even though it is at the tail of the list.  This
+ * is because the tail contains a wrap back pointer to the true head of
+ * the list.
+ *
+ * In addition to it's value, each list item contains a pointer to the next
+ * item in the list (pxNext), a pointer to the list it is in (pxContainer)
+ * and a pointer to back to the object that contains it.  These later two
+ * pointers are included for efficiency of list manipulation.  There is
+ * effectively a two way link between the object containing the list item and
+ * the list item itself.
+ *
+ *
+ * \page ListIntroduction List Implementation
+ * \ingroup FreeRTOSIntro
+ */
+
+#ifndef INC_FREERTOS_H
+	#error FreeRTOS.h must be included before list.h
+#endif
+
+#ifndef LIST_H
+#define LIST_H
+
+/*
+ * The list structure members are modified from within interrupts, and therefore
+ * by rights should be declared volatile.  However, they are only modified in a
+ * functionally atomic way (within critical sections of with the scheduler
+ * suspended) and are either passed by reference into a function or indexed via
+ * a volatile variable.  Therefore, in all use cases tested so far, the volatile
+ * qualifier can be omitted in order to provide a moderate performance
+ * improvement without adversely affecting functional behaviour.  The assembly
+ * instructions generated by the IAR, ARM and GCC compilers when the respective
+ * compiler's options were set for maximum optimisation has been inspected and
+ * deemed to be as intended.  That said, as compiler technology advances, and
+ * especially if aggressive cross module optimisation is used (a use case that
+ * has not been exercised to any great extend) then it is feasible that the
+ * volatile qualifier will be needed for correct optimisation.  It is expected
+ * that a compiler removing essential code because, without the volatile
+ * qualifier on the list structure members and with aggressive cross module
+ * optimisation, the compiler deemed the code unnecessary will result in
+ * complete and obvious failure of the scheduler.  If this is ever experienced
+ * then the volatile qualifier can be inserted in the relevant places within the
+ * list structures by simply defining configLIST_VOLATILE to volatile in
+ * FreeRTOSConfig.h (as per the example at the bottom of this comment block).
+ * If configLIST_VOLATILE is not defined then the preprocessor directives below
+ * will simply #define configLIST_VOLATILE away completely.
+ *
+ * To use volatile list structure members then add the following line to
+ * FreeRTOSConfig.h (without the quotes):
+ * "#define configLIST_VOLATILE volatile"
+ */
+#ifndef configLIST_VOLATILE
+	#define configLIST_VOLATILE
+#endif /* configSUPPORT_CROSS_MODULE_OPTIMISATION */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Macros that can be used to place known values within the list structures,
+then check that the known values do not get corrupted during the execution of
+the application.   These may catch the list data structures being overwritten in
+memory.  They will not catch data errors caused by incorrect configuration or
+use of FreeRTOS.*/
+#if( configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES == 0 )
+	/* Define the macros to do nothing. */
+	#define listFIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE
+	#define listSECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE
+	#define listFIRST_LIST_INTEGRITY_CHECK_VALUE
+	#define listSECOND_LIST_INTEGRITY_CHECK_VALUE
+	#define listSET_FIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem )
+	#define listSET_SECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem )
+	#define listSET_LIST_INTEGRITY_CHECK_1_VALUE( pxList )
+	#define listSET_LIST_INTEGRITY_CHECK_2_VALUE( pxList )
+	#define listTEST_LIST_ITEM_INTEGRITY( pxItem )
+	#define listTEST_LIST_INTEGRITY( pxList )
+#else
+	/* Define macros that add new members into the list structures. */
+	#define listFIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE				TickType_t xListItemIntegrityValue1;
+	#define listSECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE				TickType_t xListItemIntegrityValue2;
+	#define listFIRST_LIST_INTEGRITY_CHECK_VALUE					TickType_t xListIntegrityValue1;
+	#define listSECOND_LIST_INTEGRITY_CHECK_VALUE					TickType_t xListIntegrityValue2;
+
+	/* Define macros that set the new structure members to known values. */
+	#define listSET_FIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem )		( pxItem )->xListItemIntegrityValue1 = pdINTEGRITY_CHECK_VALUE
+	#define listSET_SECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem )	( pxItem )->xListItemIntegrityValue2 = pdINTEGRITY_CHECK_VALUE
+	#define listSET_LIST_INTEGRITY_CHECK_1_VALUE( pxList )		( pxList )->xListIntegrityValue1 = pdINTEGRITY_CHECK_VALUE
+	#define listSET_LIST_INTEGRITY_CHECK_2_VALUE( pxList )		( pxList )->xListIntegrityValue2 = pdINTEGRITY_CHECK_VALUE
+
+	/* Define macros that will assert if one of the structure members does not
+	contain its expected value. */
+	#define listTEST_LIST_ITEM_INTEGRITY( pxItem )		configASSERT( ( ( pxItem )->xListItemIntegrityValue1 == pdINTEGRITY_CHECK_VALUE ) && ( ( pxItem )->xListItemIntegrityValue2 == pdINTEGRITY_CHECK_VALUE ) )
+	#define listTEST_LIST_INTEGRITY( pxList )			configASSERT( ( ( pxList )->xListIntegrityValue1 == pdINTEGRITY_CHECK_VALUE ) && ( ( pxList )->xListIntegrityValue2 == pdINTEGRITY_CHECK_VALUE ) )
+#endif /* configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES */
+
+
+/*
+ * Definition of the only type of object that a list can contain.
+ */
+struct xLIST;
+struct xLIST_ITEM
+{
+	listFIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE			/*< Set to a known value if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */
+	configLIST_VOLATILE TickType_t xItemValue;			/*< The value being listed.  In most cases this is used to sort the list in descending order. */
+	struct xLIST_ITEM * configLIST_VOLATILE pxNext;		/*< Pointer to the next ListItem_t in the list. */
+	struct xLIST_ITEM * configLIST_VOLATILE pxPrevious;	/*< Pointer to the previous ListItem_t in the list. */
+	void * pvOwner;										/*< Pointer to the object (normally a TCB) that contains the list item.  There is therefore a two way link between the object containing the list item and the list item itself. */
+	struct xLIST * configLIST_VOLATILE pxContainer;		/*< Pointer to the list in which this list item is placed (if any). */
+	listSECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE			/*< Set to a known value if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */
+};
+typedef struct xLIST_ITEM ListItem_t;					/* For some reason lint wants this as two separate definitions. */
+
+struct xMINI_LIST_ITEM
+{
+	listFIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE			/*< Set to a known value if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */
+	configLIST_VOLATILE TickType_t xItemValue;
+	struct xLIST_ITEM * configLIST_VOLATILE pxNext;
+	struct xLIST_ITEM * configLIST_VOLATILE pxPrevious;
+};
+typedef struct xMINI_LIST_ITEM MiniListItem_t;
+
+/*
+ * Definition of the type of queue used by the scheduler.
+ */
+typedef struct xLIST
+{
+	listFIRST_LIST_INTEGRITY_CHECK_VALUE				/*< Set to a known value if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */
+	volatile UBaseType_t uxNumberOfItems;
+	ListItem_t * configLIST_VOLATILE pxIndex;			/*< Used to walk through the list.  Points to the last item returned by a call to listGET_OWNER_OF_NEXT_ENTRY (). */
+	MiniListItem_t xListEnd;							/*< List item that contains the maximum possible item value meaning it is always at the end of the list and is therefore used as a marker. */
+	listSECOND_LIST_INTEGRITY_CHECK_VALUE				/*< Set to a known value if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */
+} List_t;
+
+/*
+ * Access macro to set the owner of a list item.  The owner of a list item
+ * is the object (usually a TCB) that contains the list item.
+ *
+ * \page listSET_LIST_ITEM_OWNER listSET_LIST_ITEM_OWNER
+ * \ingroup LinkedList
+ */
+#define listSET_LIST_ITEM_OWNER( pxListItem, pxOwner )		( ( pxListItem )->pvOwner = ( void * ) ( pxOwner ) )
+
+/*
+ * Access macro to get the owner of a list item.  The owner of a list item
+ * is the object (usually a TCB) that contains the list item.
+ *
+ * \page listGET_LIST_ITEM_OWNER listSET_LIST_ITEM_OWNER
+ * \ingroup LinkedList
+ */
+#define listGET_LIST_ITEM_OWNER( pxListItem )	( ( pxListItem )->pvOwner )
+
+/*
+ * Access macro to set the value of the list item.  In most cases the value is
+ * used to sort the list in descending order.
+ *
+ * \page listSET_LIST_ITEM_VALUE listSET_LIST_ITEM_VALUE
+ * \ingroup LinkedList
+ */
+#define listSET_LIST_ITEM_VALUE( pxListItem, xValue )	( ( pxListItem )->xItemValue = ( xValue ) )
+
+/*
+ * Access macro to retrieve the value of the list item.  The value can
+ * represent anything - for example the priority of a task, or the time at
+ * which a task should be unblocked.
+ *
+ * \page listGET_LIST_ITEM_VALUE listGET_LIST_ITEM_VALUE
+ * \ingroup LinkedList
+ */
+#define listGET_LIST_ITEM_VALUE( pxListItem )	( ( pxListItem )->xItemValue )
+
+/*
+ * Access macro to retrieve the value of the list item at the head of a given
+ * list.
+ *
+ * \page listGET_LIST_ITEM_VALUE listGET_LIST_ITEM_VALUE
+ * \ingroup LinkedList
+ */
+#define listGET_ITEM_VALUE_OF_HEAD_ENTRY( pxList )	( ( ( pxList )->xListEnd ).pxNext->xItemValue )
+
+/*
+ * Return the list item at the head of the list.
+ *
+ * \page listGET_HEAD_ENTRY listGET_HEAD_ENTRY
+ * \ingroup LinkedList
+ */
+#define listGET_HEAD_ENTRY( pxList )	( ( ( pxList )->xListEnd ).pxNext )
+
+/*
+ * Return the next list item.
+ *
+ * \page listGET_NEXT listGET_NEXT
+ * \ingroup LinkedList
+ */
+#define listGET_NEXT( pxListItem )	( ( pxListItem )->pxNext )
+
+/*
+ * Return the list item that marks the end of the list
+ *
+ * \page listGET_END_MARKER listGET_END_MARKER
+ * \ingroup LinkedList
+ */
+#define listGET_END_MARKER( pxList )	( ( ListItem_t const * ) ( &( ( pxList )->xListEnd ) ) )
+
+/*
+ * Access macro to determine if a list contains any items.  The macro will
+ * only have the value true if the list is empty.
+ *
+ * \page listLIST_IS_EMPTY listLIST_IS_EMPTY
+ * \ingroup LinkedList
+ */
+#define listLIST_IS_EMPTY( pxList )	( ( ( pxList )->uxNumberOfItems == ( UBaseType_t ) 0 ) ? pdTRUE : pdFALSE )
+
+/*
+ * Access macro to return the number of items in the list.
+ */
+#define listCURRENT_LIST_LENGTH( pxList )	( ( pxList )->uxNumberOfItems )
+
+/*
+ * Access function to obtain the owner of the next entry in a list.
+ *
+ * The list member pxIndex is used to walk through a list.  Calling
+ * listGET_OWNER_OF_NEXT_ENTRY increments pxIndex to the next item in the list
+ * and returns that entry's pxOwner parameter.  Using multiple calls to this
+ * function it is therefore possible to move through every item contained in
+ * a list.
+ *
+ * The pxOwner parameter of a list item is a pointer to the object that owns
+ * the list item.  In the scheduler this is normally a task control block.
+ * The pxOwner parameter effectively creates a two way link between the list
+ * item and its owner.
+ *
+ * @param pxTCB pxTCB is set to the address of the owner of the next list item.
+ * @param pxList The list from which the next item owner is to be returned.
+ *
+ * \page listGET_OWNER_OF_NEXT_ENTRY listGET_OWNER_OF_NEXT_ENTRY
+ * \ingroup LinkedList
+ */
+#define listGET_OWNER_OF_NEXT_ENTRY( pxTCB, pxList )										\
+{																							\
+List_t * const pxConstList = ( pxList );													\
+	/* Increment the index to the next item and return the item, ensuring */				\
+	/* we don't return the marker used at the end of the list.  */							\
+	( pxConstList )->pxIndex = ( pxConstList )->pxIndex->pxNext;							\
+	if( ( void * ) ( pxConstList )->pxIndex == ( void * ) &( ( pxConstList )->xListEnd ) )	\
+	{																						\
+		( pxConstList )->pxIndex = ( pxConstList )->pxIndex->pxNext;						\
+	}																						\
+	( pxTCB ) = ( pxConstList )->pxIndex->pvOwner;											\
+}
+
+
+/*
+ * Access function to obtain the owner of the first entry in a list.  Lists
+ * are normally sorted in ascending item value order.
+ *
+ * This function returns the pxOwner member of the first item in the list.
+ * The pxOwner parameter of a list item is a pointer to the object that owns
+ * the list item.  In the scheduler this is normally a task control block.
+ * The pxOwner parameter effectively creates a two way link between the list
+ * item and its owner.
+ *
+ * @param pxList The list from which the owner of the head item is to be
+ * returned.
+ *
+ * \page listGET_OWNER_OF_HEAD_ENTRY listGET_OWNER_OF_HEAD_ENTRY
+ * \ingroup LinkedList
+ */
+#define listGET_OWNER_OF_HEAD_ENTRY( pxList )  ( (&( ( pxList )->xListEnd ))->pxNext->pvOwner )
+
+/*
+ * Check to see if a list item is within a list.  The list item maintains a
+ * "container" pointer that points to the list it is in.  All this macro does
+ * is check to see if the container and the list match.
+ *
+ * @param pxList The list we want to know if the list item is within.
+ * @param pxListItem The list item we want to know if is in the list.
+ * @return pdTRUE if the list item is in the list, otherwise pdFALSE.
+ */
+#define listIS_CONTAINED_WITHIN( pxList, pxListItem ) ( ( ( pxListItem )->pxContainer == ( pxList ) ) ? ( pdTRUE ) : ( pdFALSE ) )
+
+/*
+ * Return the list a list item is contained within (referenced from).
+ *
+ * @param pxListItem The list item being queried.
+ * @return A pointer to the List_t object that references the pxListItem
+ */
+#define listLIST_ITEM_CONTAINER( pxListItem ) ( ( pxListItem )->pxContainer )
+
+/*
+ * This provides a crude means of knowing if a list has been initialised, as
+ * pxList->xListEnd.xItemValue is set to portMAX_DELAY by the vListInitialise()
+ * function.
+ */
+#define listLIST_IS_INITIALISED( pxList ) ( ( pxList )->xListEnd.xItemValue == portMAX_DELAY )
+
+/*
+ * Must be called before a list is used!  This initialises all the members
+ * of the list structure and inserts the xListEnd item into the list as a
+ * marker to the back of the list.
+ *
+ * @param pxList Pointer to the list being initialised.
+ *
+ * \page vListInitialise vListInitialise
+ * \ingroup LinkedList
+ */
+void vListInitialise( List_t * const pxList ) PRIVILEGED_FUNCTION;
+
+/*
+ * Must be called before a list item is used.  This sets the list container to
+ * null so the item does not think that it is already contained in a list.
+ *
+ * @param pxItem Pointer to the list item being initialised.
+ *
+ * \page vListInitialiseItem vListInitialiseItem
+ * \ingroup LinkedList
+ */
+void vListInitialiseItem( ListItem_t * const pxItem ) PRIVILEGED_FUNCTION;
+
+/*
+ * Insert a list item into a list.  The item will be inserted into the list in
+ * a position determined by its item value (descending item value order).
+ *
+ * @param pxList The list into which the item is to be inserted.
+ *
+ * @param pxNewListItem The item that is to be placed in the list.
+ *
+ * \page vListInsert vListInsert
+ * \ingroup LinkedList
+ */
+void vListInsert( List_t * const pxList, ListItem_t * const pxNewListItem ) PRIVILEGED_FUNCTION;
+
+/*
+ * Insert a list item into a list.  The item will be inserted in a position
+ * such that it will be the last item within the list returned by multiple
+ * calls to listGET_OWNER_OF_NEXT_ENTRY.
+ *
+ * The list member pxIndex is used to walk through a list.  Calling
+ * listGET_OWNER_OF_NEXT_ENTRY increments pxIndex to the next item in the list.
+ * Placing an item in a list using vListInsertEnd effectively places the item
+ * in the list position pointed to by pxIndex.  This means that every other
+ * item within the list will be returned by listGET_OWNER_OF_NEXT_ENTRY before
+ * the pxIndex parameter again points to the item being inserted.
+ *
+ * @param pxList The list into which the item is to be inserted.
+ *
+ * @param pxNewListItem The list item to be inserted into the list.
+ *
+ * \page vListInsertEnd vListInsertEnd
+ * \ingroup LinkedList
+ */
+void vListInsertEnd( List_t * const pxList, ListItem_t * const pxNewListItem ) PRIVILEGED_FUNCTION;
+
+/*
+ * Remove an item from a list.  The list item has a pointer to the list that
+ * it is in, so only the list item need be passed into the function.
+ *
+ * @param uxListRemove The item to be removed.  The item will remove itself from
+ * the list pointed to by it's pxContainer parameter.
+ *
+ * @return The number of items that remain in the list after the list item has
+ * been removed.
+ *
+ * \page uxListRemove uxListRemove
+ * \ingroup LinkedList
+ */
+UBaseType_t uxListRemove( ListItem_t * const pxItemToRemove ) PRIVILEGED_FUNCTION;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/include/message_buffer.h b/Middlewares/Third_Party/FreeRTOS/Source/include/message_buffer.h
new file mode 100644
index 0000000..b20c09e
--- /dev/null
+++ b/Middlewares/Third_Party/FreeRTOS/Source/include/message_buffer.h
@@ -0,0 +1,803 @@
+/*
+ * FreeRTOS Kernel V10.3.1
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+/*
+ * Message buffers build functionality on top of FreeRTOS stream buffers.
+ * Whereas stream buffers are used to send a continuous stream of data from one
+ * task or interrupt to another, message buffers are used to send variable
+ * length discrete messages from one task or interrupt to another.  Their
+ * implementation is light weight, making them particularly suited for interrupt
+ * to task and core to core communication scenarios.
+ *
+ * ***NOTE***:  Uniquely among FreeRTOS objects, the stream buffer
+ * implementation (so also the message buffer implementation, as message buffers
+ * are built on top of stream buffers) assumes there is only one task or
+ * interrupt that will write to the buffer (the writer), and only one task or
+ * interrupt that will read from the buffer (the reader).  It is safe for the
+ * writer and reader to be different tasks or interrupts, but, unlike other
+ * FreeRTOS objects, it is not safe to have multiple different writers or
+ * multiple different readers.  If there are to be multiple different writers
+ * then the application writer must place each call to a writing API function
+ * (such as xMessageBufferSend()) inside a critical section and set the send
+ * block time to 0.  Likewise, if there are to be multiple different readers
+ * then the application writer must place each call to a reading API function
+ * (such as xMessageBufferRead()) inside a critical section and set the receive
+ * timeout to 0.
+ *
+ * Message buffers hold variable length messages.  To enable that, when a
+ * message is written to the message buffer an additional sizeof( size_t ) bytes
+ * are also written to store the message's length (that happens internally, with
+ * the API function).  sizeof( size_t ) is typically 4 bytes on a 32-bit
+ * architecture, so writing a 10 byte message to a message buffer on a 32-bit
+ * architecture will actually reduce the available space in the message buffer
+ * by 14 bytes (10 byte are used by the message, and 4 bytes to hold the length
+ * of the message).
+ */
+
+#ifndef FREERTOS_MESSAGE_BUFFER_H
+#define FREERTOS_MESSAGE_BUFFER_H
+
+#ifndef INC_FREERTOS_H
+	#error "include FreeRTOS.h must appear in source files before include message_buffer.h"
+#endif
+
+/* Message buffers are built onto of stream buffers. */
+#include "stream_buffer.h"
+
+#if defined( __cplusplus )
+extern "C" {
+#endif
+
+/**
+ * Type by which message buffers are referenced.  For example, a call to
+ * xMessageBufferCreate() returns an MessageBufferHandle_t variable that can
+ * then be used as a parameter to xMessageBufferSend(), xMessageBufferReceive(),
+ * etc.
+ */
+typedef void * MessageBufferHandle_t;
+
+/*-----------------------------------------------------------*/
+
+/**
+ * message_buffer.h
+ *
+<pre>
+MessageBufferHandle_t xMessageBufferCreate( size_t xBufferSizeBytes );
+</pre>
+ *
+ * Creates a new message buffer using dynamically allocated memory.  See
+ * xMessageBufferCreateStatic() for a version that uses statically allocated
+ * memory (memory that is allocated at compile time).
+ *
+ * configSUPPORT_DYNAMIC_ALLOCATION must be set to 1 or left undefined in
+ * FreeRTOSConfig.h for xMessageBufferCreate() to be available.
+ *
+ * @param xBufferSizeBytes The total number of bytes (not messages) the message
+ * buffer will be able to hold at any one time.  When a message is written to
+ * the message buffer an additional sizeof( size_t ) bytes are also written to
+ * store the message's length.  sizeof( size_t ) is typically 4 bytes on a
+ * 32-bit architecture, so on most 32-bit architectures a 10 byte message will
+ * take up 14 bytes of message buffer space.
+ *
+ * @return If NULL is returned, then the message buffer cannot be created
+ * because there is insufficient heap memory available for FreeRTOS to allocate
+ * the message buffer data structures and storage area.  A non-NULL value being
+ * returned indicates that the message buffer has been created successfully -
+ * the returned value should be stored as the handle to the created message
+ * buffer.
+ *
+ * Example use:
+<pre>
+
+void vAFunction( void )
+{
+MessageBufferHandle_t xMessageBuffer;
+const size_t xMessageBufferSizeBytes = 100;
+
+    // Create a message buffer that can hold 100 bytes.  The memory used to hold
+    // both the message buffer structure and the messages themselves is allocated
+    // dynamically.  Each message added to the buffer consumes an additional 4
+    // bytes which are used to hold the lengh of the message.
+    xMessageBuffer = xMessageBufferCreate( xMessageBufferSizeBytes );
+
+    if( xMessageBuffer == NULL )
+    {
+        // There was not enough heap memory space available to create the
+        // message buffer.
+    }
+    else
+    {
+        // The message buffer was created successfully and can now be used.
+    }
+
+</pre>
+ * \defgroup xMessageBufferCreate xMessageBufferCreate
+ * \ingroup MessageBufferManagement
+ */
+#define xMessageBufferCreate( xBufferSizeBytes ) ( MessageBufferHandle_t ) xStreamBufferGenericCreate( xBufferSizeBytes, ( size_t ) 0, pdTRUE )
+
+/**
+ * message_buffer.h
+ *
+<pre>
+MessageBufferHandle_t xMessageBufferCreateStatic( size_t xBufferSizeBytes,
+                                                  uint8_t *pucMessageBufferStorageArea,
+                                                  StaticMessageBuffer_t *pxStaticMessageBuffer );
+</pre>
+ * Creates a new message buffer using statically allocated memory.  See
+ * xMessageBufferCreate() for a version that uses dynamically allocated memory.
+ *
+ * @param xBufferSizeBytes The size, in bytes, of the buffer pointed to by the
+ * pucMessageBufferStorageArea parameter.  When a message is written to the
+ * message buffer an additional sizeof( size_t ) bytes are also written to store
+ * the message's length.  sizeof( size_t ) is typically 4 bytes on a 32-bit
+ * architecture, so on most 32-bit architecture a 10 byte message will take up
+ * 14 bytes of message buffer space.  The maximum number of bytes that can be
+ * stored in the message buffer is actually (xBufferSizeBytes - 1).
+ *
+ * @param pucMessageBufferStorageArea Must point to a uint8_t array that is at
+ * least xBufferSizeBytes + 1 big.  This is the array to which messages are
+ * copied when they are written to the message buffer.
+ *
+ * @param pxStaticMessageBuffer Must point to a variable of type
+ * StaticMessageBuffer_t, which will be used to hold the message buffer's data
+ * structure.
+ *
+ * @return If the message buffer is created successfully then a handle to the
+ * created message buffer is returned. If either pucMessageBufferStorageArea or
+ * pxStaticmessageBuffer are NULL then NULL is returned.
+ *
+ * Example use:
+<pre>
+
+// Used to dimension the array used to hold the messages.  The available space
+// will actually be one less than this, so 999.
+#define STORAGE_SIZE_BYTES 1000
+
+// Defines the memory that will actually hold the messages within the message
+// buffer.
+static uint8_t ucStorageBuffer[ STORAGE_SIZE_BYTES ];
+
+// The variable used to hold the message buffer structure.
+StaticMessageBuffer_t xMessageBufferStruct;
+
+void MyFunction( void )
+{
+MessageBufferHandle_t xMessageBuffer;
+
+    xMessageBuffer = xMessageBufferCreateStatic( sizeof( ucBufferStorage ),
+                                                 ucBufferStorage,
+                                                 &xMessageBufferStruct );
+
+    // As neither the pucMessageBufferStorageArea or pxStaticMessageBuffer
+    // parameters were NULL, xMessageBuffer will not be NULL, and can be used to
+    // reference the created message buffer in other message buffer API calls.
+
+    // Other code that uses the message buffer can go here.
+}
+
+</pre>
+ * \defgroup xMessageBufferCreateStatic xMessageBufferCreateStatic
+ * \ingroup MessageBufferManagement
+ */
+#define xMessageBufferCreateStatic( xBufferSizeBytes, pucMessageBufferStorageArea, pxStaticMessageBuffer ) ( MessageBufferHandle_t ) xStreamBufferGenericCreateStatic( xBufferSizeBytes, 0, pdTRUE, pucMessageBufferStorageArea, pxStaticMessageBuffer )
+
+/**
+ * message_buffer.h
+ *
+<pre>
+size_t xMessageBufferSend( MessageBufferHandle_t xMessageBuffer,
+                           const void *pvTxData,
+                           size_t xDataLengthBytes,
+                           TickType_t xTicksToWait );
+<pre>
+ *
+ * Sends a discrete message to the message buffer.  The message can be any
+ * length that fits within the buffer's free space, and is copied into the
+ * buffer.
+ *
+ * ***NOTE***:  Uniquely among FreeRTOS objects, the stream buffer
+ * implementation (so also the message buffer implementation, as message buffers
+ * are built on top of stream buffers) assumes there is only one task or
+ * interrupt that will write to the buffer (the writer), and only one task or
+ * interrupt that will read from the buffer (the reader).  It is safe for the
+ * writer and reader to be different tasks or interrupts, but, unlike other
+ * FreeRTOS objects, it is not safe to have multiple different writers or
+ * multiple different readers.  If there are to be multiple different writers
+ * then the application writer must place each call to a writing API function
+ * (such as xMessageBufferSend()) inside a critical section and set the send
+ * block time to 0.  Likewise, if there are to be multiple different readers
+ * then the application writer must place each call to a reading API function
+ * (such as xMessageBufferRead()) inside a critical section and set the receive
+ * block time to 0.
+ *
+ * Use xMessageBufferSend() to write to a message buffer from a task.  Use
+ * xMessageBufferSendFromISR() to write to a message buffer from an interrupt
+ * service routine (ISR).
+ *
+ * @param xMessageBuffer The handle of the message buffer to which a message is
+ * being sent.
+ *
+ * @param pvTxData A pointer to the message that is to be copied into the
+ * message buffer.
+ *
+ * @param xDataLengthBytes The length of the message.  That is, the number of
+ * bytes to copy from pvTxData into the message buffer.  When a message is
+ * written to the message buffer an additional sizeof( size_t ) bytes are also
+ * written to store the message's length.  sizeof( size_t ) is typically 4 bytes
+ * on a 32-bit architecture, so on most 32-bit architecture setting
+ * xDataLengthBytes to 20 will reduce the free space in the message buffer by 24
+ * bytes (20 bytes of message data and 4 bytes to hold the message length).
+ *
+ * @param xTicksToWait The maximum amount of time the calling task should remain
+ * in the Blocked state to wait for enough space to become available in the
+ * message buffer, should the message buffer have insufficient space when
+ * xMessageBufferSend() is called.  The calling task will never block if
+ * xTicksToWait is zero.  The block time is specified in tick periods, so the
+ * absolute time it represents is dependent on the tick frequency.  The macro
+ * pdMS_TO_TICKS() can be used to convert a time specified in milliseconds into
+ * a time specified in ticks.  Setting xTicksToWait to portMAX_DELAY will cause
+ * the task to wait indefinitely (without timing out), provided
+ * INCLUDE_vTaskSuspend is set to 1 in FreeRTOSConfig.h.  Tasks do not use any
+ * CPU time when they are in the Blocked state.
+ *
+ * @return The number of bytes written to the message buffer.  If the call to
+ * xMessageBufferSend() times out before there was enough space to write the
+ * message into the message buffer then zero is returned.  If the call did not
+ * time out then xDataLengthBytes is returned.
+ *
+ * Example use:
+<pre>
+void vAFunction( MessageBufferHandle_t xMessageBuffer )
+{
+size_t xBytesSent;
+uint8_t ucArrayToSend[] = { 0, 1, 2, 3 };
+char *pcStringToSend = "String to send";
+const TickType_t x100ms = pdMS_TO_TICKS( 100 );
+
+    // Send an array to the message buffer, blocking for a maximum of 100ms to
+    // wait for enough space to be available in the message buffer.
+    xBytesSent = xMessageBufferSend( xMessageBuffer, ( void * ) ucArrayToSend, sizeof( ucArrayToSend ), x100ms );
+
+    if( xBytesSent != sizeof( ucArrayToSend ) )
+    {
+        // The call to xMessageBufferSend() times out before there was enough
+        // space in the buffer for the data to be written.
+    }
+
+    // Send the string to the message buffer.  Return immediately if there is
+    // not enough space in the buffer.
+    xBytesSent = xMessageBufferSend( xMessageBuffer, ( void * ) pcStringToSend, strlen( pcStringToSend ), 0 );
+
+    if( xBytesSent != strlen( pcStringToSend ) )
+    {
+        // The string could not be added to the message buffer because there was
+        // not enough free space in the buffer.
+    }
+}
+</pre>
+ * \defgroup xMessageBufferSend xMessageBufferSend
+ * \ingroup MessageBufferManagement
+ */
+#define xMessageBufferSend( xMessageBuffer, pvTxData, xDataLengthBytes, xTicksToWait ) xStreamBufferSend( ( StreamBufferHandle_t ) xMessageBuffer, pvTxData, xDataLengthBytes, xTicksToWait )
+
+/**
+ * message_buffer.h
+ *
+<pre>
+size_t xMessageBufferSendFromISR( MessageBufferHandle_t xMessageBuffer,
+                                  const void *pvTxData,
+                                  size_t xDataLengthBytes,
+                                  BaseType_t *pxHigherPriorityTaskWoken );
+<pre>
+ *
+ * Interrupt safe version of the API function that sends a discrete message to
+ * the message buffer.  The message can be any length that fits within the
+ * buffer's free space, and is copied into the buffer.
+ *
+ * ***NOTE***:  Uniquely among FreeRTOS objects, the stream buffer
+ * implementation (so also the message buffer implementation, as message buffers
+ * are built on top of stream buffers) assumes there is only one task or
+ * interrupt that will write to the buffer (the writer), and only one task or
+ * interrupt that will read from the buffer (the reader).  It is safe for the
+ * writer and reader to be different tasks or interrupts, but, unlike other
+ * FreeRTOS objects, it is not safe to have multiple different writers or
+ * multiple different readers.  If there are to be multiple different writers
+ * then the application writer must place each call to a writing API function
+ * (such as xMessageBufferSend()) inside a critical section and set the send
+ * block time to 0.  Likewise, if there are to be multiple different readers
+ * then the application writer must place each call to a reading API function
+ * (such as xMessageBufferRead()) inside a critical section and set the receive
+ * block time to 0.
+ *
+ * Use xMessageBufferSend() to write to a message buffer from a task.  Use
+ * xMessageBufferSendFromISR() to write to a message buffer from an interrupt
+ * service routine (ISR).
+ *
+ * @param xMessageBuffer The handle of the message buffer to which a message is
+ * being sent.
+ *
+ * @param pvTxData A pointer to the message that is to be copied into the
+ * message buffer.
+ *
+ * @param xDataLengthBytes The length of the message.  That is, the number of
+ * bytes to copy from pvTxData into the message buffer.  When a message is
+ * written to the message buffer an additional sizeof( size_t ) bytes are also
+ * written to store the message's length.  sizeof( size_t ) is typically 4 bytes
+ * on a 32-bit architecture, so on most 32-bit architecture setting
+ * xDataLengthBytes to 20 will reduce the free space in the message buffer by 24
+ * bytes (20 bytes of message data and 4 bytes to hold the message length).
+ *
+ * @param pxHigherPriorityTaskWoken  It is possible that a message buffer will
+ * have a task blocked on it waiting for data.  Calling
+ * xMessageBufferSendFromISR() can make data available, and so cause a task that
+ * was waiting for data to leave the Blocked state.  If calling
+ * xMessageBufferSendFromISR() causes a task to leave the Blocked state, and the
+ * unblocked task has a priority higher than the currently executing task (the
+ * task that was interrupted), then, internally, xMessageBufferSendFromISR()
+ * will set *pxHigherPriorityTaskWoken to pdTRUE.  If
+ * xMessageBufferSendFromISR() sets this value to pdTRUE, then normally a
+ * context switch should be performed before the interrupt is exited.  This will
+ * ensure that the interrupt returns directly to the highest priority Ready
+ * state task.  *pxHigherPriorityTaskWoken should be set to pdFALSE before it
+ * is passed into the function.  See the code example below for an example.
+ *
+ * @return The number of bytes actually written to the message buffer.  If the
+ * message buffer didn't have enough free space for the message to be stored
+ * then 0 is returned, otherwise xDataLengthBytes is returned.
+ *
+ * Example use:
+<pre>
+// A message buffer that has already been created.
+MessageBufferHandle_t xMessageBuffer;
+
+void vAnInterruptServiceRoutine( void )
+{
+size_t xBytesSent;
+char *pcStringToSend = "String to send";
+BaseType_t xHigherPriorityTaskWoken = pdFALSE; // Initialised to pdFALSE.
+
+    // Attempt to send the string to the message buffer.
+    xBytesSent = xMessageBufferSendFromISR( xMessageBuffer,
+                                            ( void * ) pcStringToSend,
+                                            strlen( pcStringToSend ),
+                                            &xHigherPriorityTaskWoken );
+
+    if( xBytesSent != strlen( pcStringToSend ) )
+    {
+        // The string could not be added to the message buffer because there was
+        // not enough free space in the buffer.
+    }
+
+    // If xHigherPriorityTaskWoken was set to pdTRUE inside
+    // xMessageBufferSendFromISR() then a task that has a priority above the
+    // priority of the currently executing task was unblocked and a context
+    // switch should be performed to ensure the ISR returns to the unblocked
+    // task.  In most FreeRTOS ports this is done by simply passing
+    // xHigherPriorityTaskWoken into portYIELD_FROM_ISR(), which will test the
+    // variables value, and perform the context switch if necessary.  Check the
+    // documentation for the port in use for port specific instructions.
+    portYIELD_FROM_ISR( xHigherPriorityTaskWoken );
+}
+</pre>
+ * \defgroup xMessageBufferSendFromISR xMessageBufferSendFromISR
+ * \ingroup MessageBufferManagement
+ */
+#define xMessageBufferSendFromISR( xMessageBuffer, pvTxData, xDataLengthBytes, pxHigherPriorityTaskWoken ) xStreamBufferSendFromISR( ( StreamBufferHandle_t ) xMessageBuffer, pvTxData, xDataLengthBytes, pxHigherPriorityTaskWoken )
+
+/**
+ * message_buffer.h
+ *
+<pre>
+size_t xMessageBufferReceive( MessageBufferHandle_t xMessageBuffer,
+                              void *pvRxData,
+                              size_t xBufferLengthBytes,
+                              TickType_t xTicksToWait );
+</pre>
+ *
+ * Receives a discrete message from a message buffer.  Messages can be of
+ * variable length and are copied out of the buffer.
+ *
+ * ***NOTE***:  Uniquely among FreeRTOS objects, the stream buffer
+ * implementation (so also the message buffer implementation, as message buffers
+ * are built on top of stream buffers) assumes there is only one task or
+ * interrupt that will write to the buffer (the writer), and only one task or
+ * interrupt that will read from the buffer (the reader).  It is safe for the
+ * writer and reader to be different tasks or interrupts, but, unlike other
+ * FreeRTOS objects, it is not safe to have multiple different writers or
+ * multiple different readers.  If there are to be multiple different writers
+ * then the application writer must place each call to a writing API function
+ * (such as xMessageBufferSend()) inside a critical section and set the send
+ * block time to 0.  Likewise, if there are to be multiple different readers
+ * then the application writer must place each call to a reading API function
+ * (such as xMessageBufferRead()) inside a critical section and set the receive
+ * block time to 0.
+ *
+ * Use xMessageBufferReceive() to read from a message buffer from a task.  Use
+ * xMessageBufferReceiveFromISR() to read from a message buffer from an
+ * interrupt service routine (ISR).
+ *
+ * @param xMessageBuffer The handle of the message buffer from which a message
+ * is being received.
+ *
+ * @param pvRxData A pointer to the buffer into which the received message is
+ * to be copied.
+ *
+ * @param xBufferLengthBytes The length of the buffer pointed to by the pvRxData
+ * parameter.  This sets the maximum length of the message that can be received.
+ * If xBufferLengthBytes is too small to hold the next message then the message
+ * will be left in the message buffer and 0 will be returned.
+ *
+ * @param xTicksToWait The maximum amount of time the task should remain in the
+ * Blocked state to wait for a message, should the message buffer be empty.
+ * xMessageBufferReceive() will return immediately if xTicksToWait is zero and
+ * the message buffer is empty.  The block time is specified in tick periods, so
+ * the absolute time it represents is dependent on the tick frequency.  The
+ * macro pdMS_TO_TICKS() can be used to convert a time specified in milliseconds
+ * into a time specified in ticks.  Setting xTicksToWait to portMAX_DELAY will
+ * cause the task to wait indefinitely (without timing out), provided
+ * INCLUDE_vTaskSuspend is set to 1 in FreeRTOSConfig.h.  Tasks do not use any
+ * CPU time when they are in the Blocked state.
+ *
+ * @return The length, in bytes, of the message read from the message buffer, if
+ * any.  If xMessageBufferReceive() times out before a message became available
+ * then zero is returned.  If the length of the message is greater than
+ * xBufferLengthBytes then the message will be left in the message buffer and
+ * zero is returned.
+ *
+ * Example use:
+<pre>
+void vAFunction( MessageBuffer_t xMessageBuffer )
+{
+uint8_t ucRxData[ 20 ];
+size_t xReceivedBytes;
+const TickType_t xBlockTime = pdMS_TO_TICKS( 20 );
+
+    // Receive the next message from the message buffer.  Wait in the Blocked
+    // state (so not using any CPU processing time) for a maximum of 100ms for
+    // a message to become available.
+    xReceivedBytes = xMessageBufferReceive( xMessageBuffer,
+                                            ( void * ) ucRxData,
+                                            sizeof( ucRxData ),
+                                            xBlockTime );
+
+    if( xReceivedBytes > 0 )
+    {
+        // A ucRxData contains a message that is xReceivedBytes long.  Process
+        // the message here....
+    }
+}
+</pre>
+ * \defgroup xMessageBufferReceive xMessageBufferReceive
+ * \ingroup MessageBufferManagement
+ */
+#define xMessageBufferReceive( xMessageBuffer, pvRxData, xBufferLengthBytes, xTicksToWait ) xStreamBufferReceive( ( StreamBufferHandle_t ) xMessageBuffer, pvRxData, xBufferLengthBytes, xTicksToWait )
+
+
+/**
+ * message_buffer.h
+ *
+<pre>
+size_t xMessageBufferReceiveFromISR( MessageBufferHandle_t xMessageBuffer,
+                                     void *pvRxData,
+                                     size_t xBufferLengthBytes,
+                                     BaseType_t *pxHigherPriorityTaskWoken );
+</pre>
+ *
+ * An interrupt safe version of the API function that receives a discrete
+ * message from a message buffer.  Messages can be of variable length and are
+ * copied out of the buffer.
+ *
+ * ***NOTE***:  Uniquely among FreeRTOS objects, the stream buffer
+ * implementation (so also the message buffer implementation, as message buffers
+ * are built on top of stream buffers) assumes there is only one task or
+ * interrupt that will write to the buffer (the writer), and only one task or
+ * interrupt that will read from the buffer (the reader).  It is safe for the
+ * writer and reader to be different tasks or interrupts, but, unlike other
+ * FreeRTOS objects, it is not safe to have multiple different writers or
+ * multiple different readers.  If there are to be multiple different writers
+ * then the application writer must place each call to a writing API function
+ * (such as xMessageBufferSend()) inside a critical section and set the send
+ * block time to 0.  Likewise, if there are to be multiple different readers
+ * then the application writer must place each call to a reading API function
+ * (such as xMessageBufferRead()) inside a critical section and set the receive
+ * block time to 0.
+ *
+ * Use xMessageBufferReceive() to read from a message buffer from a task.  Use
+ * xMessageBufferReceiveFromISR() to read from a message buffer from an
+ * interrupt service routine (ISR).
+ *
+ * @param xMessageBuffer The handle of the message buffer from which a message
+ * is being received.
+ *
+ * @param pvRxData A pointer to the buffer into which the received message is
+ * to be copied.
+ *
+ * @param xBufferLengthBytes The length of the buffer pointed to by the pvRxData
+ * parameter.  This sets the maximum length of the message that can be received.
+ * If xBufferLengthBytes is too small to hold the next message then the message
+ * will be left in the message buffer and 0 will be returned.
+ *
+ * @param pxHigherPriorityTaskWoken  It is possible that a message buffer will
+ * have a task blocked on it waiting for space to become available.  Calling
+ * xMessageBufferReceiveFromISR() can make space available, and so cause a task
+ * that is waiting for space to leave the Blocked state.  If calling
+ * xMessageBufferReceiveFromISR() causes a task to leave the Blocked state, and
+ * the unblocked task has a priority higher than the currently executing task
+ * (the task that was interrupted), then, internally,
+ * xMessageBufferReceiveFromISR() will set *pxHigherPriorityTaskWoken to pdTRUE.
+ * If xMessageBufferReceiveFromISR() sets this value to pdTRUE, then normally a
+ * context switch should be performed before the interrupt is exited.  That will
+ * ensure the interrupt returns directly to the highest priority Ready state
+ * task.  *pxHigherPriorityTaskWoken should be set to pdFALSE before it is
+ * passed into the function.  See the code example below for an example.
+ *
+ * @return The length, in bytes, of the message read from the message buffer, if
+ * any.
+ *
+ * Example use:
+<pre>
+// A message buffer that has already been created.
+MessageBuffer_t xMessageBuffer;
+
+void vAnInterruptServiceRoutine( void )
+{
+uint8_t ucRxData[ 20 ];
+size_t xReceivedBytes;
+BaseType_t xHigherPriorityTaskWoken = pdFALSE;  // Initialised to pdFALSE.
+
+    // Receive the next message from the message buffer.
+    xReceivedBytes = xMessageBufferReceiveFromISR( xMessageBuffer,
+                                                  ( void * ) ucRxData,
+                                                  sizeof( ucRxData ),
+                                                  &xHigherPriorityTaskWoken );
+
+    if( xReceivedBytes > 0 )
+    {
+        // A ucRxData contains a message that is xReceivedBytes long.  Process
+        // the message here....
+    }
+
+    // If xHigherPriorityTaskWoken was set to pdTRUE inside
+    // xMessageBufferReceiveFromISR() then a task that has a priority above the
+    // priority of the currently executing task was unblocked and a context
+    // switch should be performed to ensure the ISR returns to the unblocked
+    // task.  In most FreeRTOS ports this is done by simply passing
+    // xHigherPriorityTaskWoken into portYIELD_FROM_ISR(), which will test the
+    // variables value, and perform the context switch if necessary.  Check the
+    // documentation for the port in use for port specific instructions.
+    portYIELD_FROM_ISR( xHigherPriorityTaskWoken );
+}
+</pre>
+ * \defgroup xMessageBufferReceiveFromISR xMessageBufferReceiveFromISR
+ * \ingroup MessageBufferManagement
+ */
+#define xMessageBufferReceiveFromISR( xMessageBuffer, pvRxData, xBufferLengthBytes, pxHigherPriorityTaskWoken ) xStreamBufferReceiveFromISR( ( StreamBufferHandle_t ) xMessageBuffer, pvRxData, xBufferLengthBytes, pxHigherPriorityTaskWoken )
+
+/**
+ * message_buffer.h
+ *
+<pre>
+void vMessageBufferDelete( MessageBufferHandle_t xMessageBuffer );
+</pre>
+ *
+ * Deletes a message buffer that was previously created using a call to
+ * xMessageBufferCreate() or xMessageBufferCreateStatic().  If the message
+ * buffer was created using dynamic memory (that is, by xMessageBufferCreate()),
+ * then the allocated memory is freed.
+ *
+ * A message buffer handle must not be used after the message buffer has been
+ * deleted.
+ *
+ * @param xMessageBuffer The handle of the message buffer to be deleted.
+ *
+ */
+#define vMessageBufferDelete( xMessageBuffer ) vStreamBufferDelete( ( StreamBufferHandle_t ) xMessageBuffer )
+
+/**
+ * message_buffer.h
+<pre>
+BaseType_t xMessageBufferIsFull( MessageBufferHandle_t xMessageBuffer ) );
+</pre>
+ *
+ * Tests to see if a message buffer is full.  A message buffer is full if it
+ * cannot accept any more messages, of any size, until space is made available
+ * by a message being removed from the message buffer.
+ *
+ * @param xMessageBuffer The handle of the message buffer being queried.
+ *
+ * @return If the message buffer referenced by xMessageBuffer is full then
+ * pdTRUE is returned.  Otherwise pdFALSE is returned.
+ */
+#define xMessageBufferIsFull( xMessageBuffer ) xStreamBufferIsFull( ( StreamBufferHandle_t ) xMessageBuffer )
+
+/**
+ * message_buffer.h
+<pre>
+BaseType_t xMessageBufferIsEmpty( MessageBufferHandle_t xMessageBuffer ) );
+</pre>
+ *
+ * Tests to see if a message buffer is empty (does not contain any messages).
+ *
+ * @param xMessageBuffer The handle of the message buffer being queried.
+ *
+ * @return If the message buffer referenced by xMessageBuffer is empty then
+ * pdTRUE is returned.  Otherwise pdFALSE is returned.
+ *
+ */
+#define xMessageBufferIsEmpty( xMessageBuffer ) xStreamBufferIsEmpty( ( StreamBufferHandle_t ) xMessageBuffer )
+
+/**
+ * message_buffer.h
+<pre>
+BaseType_t xMessageBufferReset( MessageBufferHandle_t xMessageBuffer );
+</pre>
+ *
+ * Resets a message buffer to its initial empty state, discarding any message it
+ * contained.
+ *
+ * A message buffer can only be reset if there are no tasks blocked on it.
+ *
+ * @param xMessageBuffer The handle of the message buffer being reset.
+ *
+ * @return If the message buffer was reset then pdPASS is returned.  If the
+ * message buffer could not be reset because either there was a task blocked on
+ * the message queue to wait for space to become available, or to wait for a
+ * a message to be available, then pdFAIL is returned.
+ *
+ * \defgroup xMessageBufferReset xMessageBufferReset
+ * \ingroup MessageBufferManagement
+ */
+#define xMessageBufferReset( xMessageBuffer ) xStreamBufferReset( ( StreamBufferHandle_t ) xMessageBuffer )
+
+
+/**
+ * message_buffer.h
+<pre>
+size_t xMessageBufferSpaceAvailable( MessageBufferHandle_t xMessageBuffer ) );
+</pre>
+ * Returns the number of bytes of free space in the message buffer.
+ *
+ * @param xMessageBuffer The handle of the message buffer being queried.
+ *
+ * @return The number of bytes that can be written to the message buffer before
+ * the message buffer would be full.  When a message is written to the message
+ * buffer an additional sizeof( size_t ) bytes are also written to store the
+ * message's length.  sizeof( size_t ) is typically 4 bytes on a 32-bit
+ * architecture, so if xMessageBufferSpacesAvailable() returns 10, then the size
+ * of the largest message that can be written to the message buffer is 6 bytes.
+ *
+ * \defgroup xMessageBufferSpaceAvailable xMessageBufferSpaceAvailable
+ * \ingroup MessageBufferManagement
+ */
+#define xMessageBufferSpaceAvailable( xMessageBuffer ) xStreamBufferSpacesAvailable( ( StreamBufferHandle_t ) xMessageBuffer )
+#define xMessageBufferSpacesAvailable( xMessageBuffer ) xStreamBufferSpacesAvailable( ( StreamBufferHandle_t ) xMessageBuffer ) /* Corrects typo in original macro name. */
+
+/**
+ * message_buffer.h
+ <pre>
+ size_t xMessageBufferNextLengthBytes( MessageBufferHandle_t xMessageBuffer ) );
+ </pre>
+ * Returns the length (in bytes) of the next message in a message buffer.
+ * Useful if xMessageBufferReceive() returned 0 because the size of the buffer
+ * passed into xMessageBufferReceive() was too small to hold the next message.
+ *
+ * @param xMessageBuffer The handle of the message buffer being queried.
+ *
+ * @return The length (in bytes) of the next message in the message buffer, or 0
+ * if the message buffer is empty.
+ *
+ * \defgroup xMessageBufferNextLengthBytes xMessageBufferNextLengthBytes
+ * \ingroup MessageBufferManagement
+ */
+#define xMessageBufferNextLengthBytes( xMessageBuffer ) xStreamBufferNextMessageLengthBytes( ( StreamBufferHandle_t ) xMessageBuffer ) PRIVILEGED_FUNCTION;
+
+/**
+ * message_buffer.h
+ *
+<pre>
+BaseType_t xMessageBufferSendCompletedFromISR( MessageBufferHandle_t xStreamBuffer, BaseType_t *pxHigherPriorityTaskWoken );
+</pre>
+ *
+ * For advanced users only.
+ *
+ * The sbSEND_COMPLETED() macro is called from within the FreeRTOS APIs when
+ * data is sent to a message buffer or stream buffer.  If there was a task that
+ * was blocked on the message or stream buffer waiting for data to arrive then
+ * the sbSEND_COMPLETED() macro sends a notification to the task to remove it
+ * from the Blocked state.  xMessageBufferSendCompletedFromISR() does the same
+ * thing.  It is provided to enable application writers to implement their own
+ * version of sbSEND_COMPLETED(), and MUST NOT BE USED AT ANY OTHER TIME.
+ *
+ * See the example implemented in FreeRTOS/Demo/Minimal/MessageBufferAMP.c for
+ * additional information.
+ *
+ * @param xStreamBuffer The handle of the stream buffer to which data was
+ * written.
+ *
+ * @param pxHigherPriorityTaskWoken *pxHigherPriorityTaskWoken should be
+ * initialised to pdFALSE before it is passed into
+ * xMessageBufferSendCompletedFromISR().  If calling
+ * xMessageBufferSendCompletedFromISR() removes a task from the Blocked state,
+ * and the task has a priority above the priority of the currently running task,
+ * then *pxHigherPriorityTaskWoken will get set to pdTRUE indicating that a
+ * context switch should be performed before exiting the ISR.
+ *
+ * @return If a task was removed from the Blocked state then pdTRUE is returned.
+ * Otherwise pdFALSE is returned.
+ *
+ * \defgroup xMessageBufferSendCompletedFromISR xMessageBufferSendCompletedFromISR
+ * \ingroup StreamBufferManagement
+ */
+#define xMessageBufferSendCompletedFromISR( xMessageBuffer, pxHigherPriorityTaskWoken ) xStreamBufferSendCompletedFromISR( ( StreamBufferHandle_t ) xMessageBuffer, pxHigherPriorityTaskWoken )
+
+/**
+ * message_buffer.h
+ *
+<pre>
+BaseType_t xMessageBufferReceiveCompletedFromISR( MessageBufferHandle_t xStreamBuffer, BaseType_t *pxHigherPriorityTaskWoken );
+</pre>
+ *
+ * For advanced users only.
+ *
+ * The sbRECEIVE_COMPLETED() macro is called from within the FreeRTOS APIs when
+ * data is read out of a message buffer or stream buffer.  If there was a task
+ * that was blocked on the message or stream buffer waiting for data to arrive
+ * then the sbRECEIVE_COMPLETED() macro sends a notification to the task to
+ * remove it from the Blocked state.  xMessageBufferReceiveCompletedFromISR()
+ * does the same thing.  It is provided to enable application writers to
+ * implement their own version of sbRECEIVE_COMPLETED(), and MUST NOT BE USED AT
+ * ANY OTHER TIME.
+ *
+ * See the example implemented in FreeRTOS/Demo/Minimal/MessageBufferAMP.c for
+ * additional information.
+ *
+ * @param xStreamBuffer The handle of the stream buffer from which data was
+ * read.
+ *
+ * @param pxHigherPriorityTaskWoken *pxHigherPriorityTaskWoken should be
+ * initialised to pdFALSE before it is passed into
+ * xMessageBufferReceiveCompletedFromISR().  If calling
+ * xMessageBufferReceiveCompletedFromISR() removes a task from the Blocked state,
+ * and the task has a priority above the priority of the currently running task,
+ * then *pxHigherPriorityTaskWoken will get set to pdTRUE indicating that a
+ * context switch should be performed before exiting the ISR.
+ *
+ * @return If a task was removed from the Blocked state then pdTRUE is returned.
+ * Otherwise pdFALSE is returned.
+ *
+ * \defgroup xMessageBufferReceiveCompletedFromISR xMessageBufferReceiveCompletedFromISR
+ * \ingroup StreamBufferManagement
+ */
+#define xMessageBufferReceiveCompletedFromISR( xMessageBuffer, pxHigherPriorityTaskWoken ) xStreamBufferReceiveCompletedFromISR( ( StreamBufferHandle_t ) xMessageBuffer, pxHigherPriorityTaskWoken )
+
+#if defined( __cplusplus )
+} /* extern "C" */
+#endif
+
+#endif	/* !defined( FREERTOS_MESSAGE_BUFFER_H ) */
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/include/mpu_prototypes.h b/Middlewares/Third_Party/FreeRTOS/Source/include/mpu_prototypes.h
new file mode 100644
index 0000000..79a185b
--- /dev/null
+++ b/Middlewares/Third_Party/FreeRTOS/Source/include/mpu_prototypes.h
@@ -0,0 +1,160 @@
+/*
+ * FreeRTOS Kernel V10.3.1
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*
+ * When the MPU is used the standard (non MPU) API functions are mapped to
+ * equivalents that start "MPU_", the prototypes for which are defined in this
+ * header files.  This will cause the application code to call the MPU_ version
+ * which wraps the non-MPU version with privilege promoting then demoting code,
+ * so the kernel code always runs will full privileges.
+ */
+
+
+#ifndef MPU_PROTOTYPES_H
+#define MPU_PROTOTYPES_H
+
+/* MPU versions of tasks.h API functions. */
+BaseType_t MPU_xTaskCreate( TaskFunction_t pxTaskCode, const char * const pcName, const uint16_t usStackDepth, void * const pvParameters, UBaseType_t uxPriority, TaskHandle_t * const pxCreatedTask ) FREERTOS_SYSTEM_CALL;
+TaskHandle_t MPU_xTaskCreateStatic( TaskFunction_t pxTaskCode, const char * const pcName, const uint32_t ulStackDepth, void * const pvParameters, UBaseType_t uxPriority, StackType_t * const puxStackBuffer, StaticTask_t * const pxTaskBuffer ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTaskCreateRestricted( const TaskParameters_t * const pxTaskDefinition, TaskHandle_t *pxCreatedTask ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTaskCreateRestrictedStatic( const TaskParameters_t * const pxTaskDefinition, TaskHandle_t *pxCreatedTask ) FREERTOS_SYSTEM_CALL;
+void MPU_vTaskAllocateMPURegions( TaskHandle_t xTask, const MemoryRegion_t * const pxRegions ) FREERTOS_SYSTEM_CALL;
+void MPU_vTaskDelete( TaskHandle_t xTaskToDelete ) FREERTOS_SYSTEM_CALL;
+void MPU_vTaskDelay( const TickType_t xTicksToDelay ) FREERTOS_SYSTEM_CALL;
+void MPU_vTaskDelayUntil( TickType_t * const pxPreviousWakeTime, const TickType_t xTimeIncrement ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTaskAbortDelay( TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL;
+UBaseType_t MPU_uxTaskPriorityGet( const TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL;
+eTaskState MPU_eTaskGetState( TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL;
+void MPU_vTaskGetInfo( TaskHandle_t xTask, TaskStatus_t *pxTaskStatus, BaseType_t xGetFreeStackSpace, eTaskState eState ) FREERTOS_SYSTEM_CALL;
+void MPU_vTaskPrioritySet( TaskHandle_t xTask, UBaseType_t uxNewPriority ) FREERTOS_SYSTEM_CALL;
+void MPU_vTaskSuspend( TaskHandle_t xTaskToSuspend ) FREERTOS_SYSTEM_CALL;
+void MPU_vTaskResume( TaskHandle_t xTaskToResume ) FREERTOS_SYSTEM_CALL;
+void MPU_vTaskStartScheduler( void ) FREERTOS_SYSTEM_CALL;
+void MPU_vTaskSuspendAll( void ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTaskResumeAll( void ) FREERTOS_SYSTEM_CALL;
+TickType_t MPU_xTaskGetTickCount( void ) FREERTOS_SYSTEM_CALL;
+UBaseType_t MPU_uxTaskGetNumberOfTasks( void ) FREERTOS_SYSTEM_CALL;
+char * MPU_pcTaskGetName( TaskHandle_t xTaskToQuery ) FREERTOS_SYSTEM_CALL;
+TaskHandle_t MPU_xTaskGetHandle( const char *pcNameToQuery ) FREERTOS_SYSTEM_CALL;
+UBaseType_t MPU_uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL;
+configSTACK_DEPTH_TYPE MPU_uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL;
+void MPU_vTaskSetApplicationTaskTag( TaskHandle_t xTask, TaskHookFunction_t pxHookFunction ) FREERTOS_SYSTEM_CALL;
+TaskHookFunction_t MPU_xTaskGetApplicationTaskTag( TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL;
+void MPU_vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet, BaseType_t xIndex, void *pvValue ) FREERTOS_SYSTEM_CALL;
+void * MPU_pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery, BaseType_t xIndex ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTaskCallApplicationTaskHook( TaskHandle_t xTask, void *pvParameter ) FREERTOS_SYSTEM_CALL;
+TaskHandle_t MPU_xTaskGetIdleTaskHandle( void ) FREERTOS_SYSTEM_CALL;
+UBaseType_t MPU_uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray, const UBaseType_t uxArraySize, uint32_t * const pulTotalRunTime ) FREERTOS_SYSTEM_CALL;
+uint32_t MPU_ulTaskGetIdleRunTimeCounter( void ) FREERTOS_SYSTEM_CALL;
+void MPU_vTaskList( char * pcWriteBuffer ) FREERTOS_SYSTEM_CALL;
+void MPU_vTaskGetRunTimeStats( char *pcWriteBuffer ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTaskGenericNotify( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction, uint32_t *pulPreviousNotificationValue ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTaskNotifyWait( uint32_t ulBitsToClearOnEntry, uint32_t ulBitsToClearOnExit, uint32_t *pulNotificationValue, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
+uint32_t MPU_ulTaskNotifyTake( BaseType_t xClearCountOnExit, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTaskNotifyStateClear( TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL;
+uint32_t MPU_ulTaskNotifyValueClear( TaskHandle_t xTask, uint32_t ulBitsToClear ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTaskIncrementTick( void ) FREERTOS_SYSTEM_CALL;
+TaskHandle_t MPU_xTaskGetCurrentTaskHandle( void ) FREERTOS_SYSTEM_CALL;
+void MPU_vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, TickType_t * const pxTicksToWait ) FREERTOS_SYSTEM_CALL;
+void MPU_vTaskMissedYield( void ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTaskGetSchedulerState( void ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTaskCatchUpTicks( TickType_t xTicksToCatchUp ) FREERTOS_SYSTEM_CALL;
+
+/* MPU versions of queue.h API functions. */
+BaseType_t MPU_xQueueGenericSend( QueueHandle_t xQueue, const void * const pvItemToQueue, TickType_t xTicksToWait, const BaseType_t xCopyPosition ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xQueueReceive( QueueHandle_t xQueue, void * const pvBuffer, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xQueuePeek( QueueHandle_t xQueue, void * const pvBuffer, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xQueueSemaphoreTake( QueueHandle_t xQueue, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
+UBaseType_t MPU_uxQueueMessagesWaiting( const QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL;
+UBaseType_t MPU_uxQueueSpacesAvailable( const QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL;
+void MPU_vQueueDelete( QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL;
+QueueHandle_t MPU_xQueueCreateMutex( const uint8_t ucQueueType ) FREERTOS_SYSTEM_CALL;
+QueueHandle_t MPU_xQueueCreateMutexStatic( const uint8_t ucQueueType, StaticQueue_t *pxStaticQueue ) FREERTOS_SYSTEM_CALL;
+QueueHandle_t MPU_xQueueCreateCountingSemaphore( const UBaseType_t uxMaxCount, const UBaseType_t uxInitialCount ) FREERTOS_SYSTEM_CALL;
+QueueHandle_t MPU_xQueueCreateCountingSemaphoreStatic( const UBaseType_t uxMaxCount, const UBaseType_t uxInitialCount, StaticQueue_t *pxStaticQueue ) FREERTOS_SYSTEM_CALL;
+TaskHandle_t MPU_xQueueGetMutexHolder( QueueHandle_t xSemaphore ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xQueueTakeMutexRecursive( QueueHandle_t xMutex, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xQueueGiveMutexRecursive( QueueHandle_t pxMutex ) FREERTOS_SYSTEM_CALL;
+void MPU_vQueueAddToRegistry( QueueHandle_t xQueue, const char *pcName ) FREERTOS_SYSTEM_CALL;
+void MPU_vQueueUnregisterQueue( QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL;
+const char * MPU_pcQueueGetName( QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL;
+QueueHandle_t MPU_xQueueGenericCreate( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, const uint8_t ucQueueType ) FREERTOS_SYSTEM_CALL;
+QueueHandle_t MPU_xQueueGenericCreateStatic( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, uint8_t *pucQueueStorage, StaticQueue_t *pxStaticQueue, const uint8_t ucQueueType ) FREERTOS_SYSTEM_CALL;
+QueueSetHandle_t MPU_xQueueCreateSet( const UBaseType_t uxEventQueueLength ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore, QueueSetHandle_t xQueueSet ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xQueueRemoveFromSet( QueueSetMemberHandle_t xQueueOrSemaphore, QueueSetHandle_t xQueueSet ) FREERTOS_SYSTEM_CALL;
+QueueSetMemberHandle_t MPU_xQueueSelectFromSet( QueueSetHandle_t xQueueSet, const TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xQueueGenericReset( QueueHandle_t xQueue, BaseType_t xNewQueue ) FREERTOS_SYSTEM_CALL;
+void MPU_vQueueSetQueueNumber( QueueHandle_t xQueue, UBaseType_t uxQueueNumber ) FREERTOS_SYSTEM_CALL;
+UBaseType_t MPU_uxQueueGetQueueNumber( QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL;
+uint8_t MPU_ucQueueGetQueueType( QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL;
+
+/* MPU versions of timers.h API functions. */
+TimerHandle_t MPU_xTimerCreate( const char * const pcTimerName, const TickType_t xTimerPeriodInTicks, const UBaseType_t uxAutoReload, void * const pvTimerID, TimerCallbackFunction_t pxCallbackFunction ) FREERTOS_SYSTEM_CALL;
+TimerHandle_t MPU_xTimerCreateStatic( const char * const pcTimerName, const TickType_t xTimerPeriodInTicks, const UBaseType_t uxAutoReload, void * const pvTimerID, TimerCallbackFunction_t pxCallbackFunction, StaticTimer_t *pxTimerBuffer ) FREERTOS_SYSTEM_CALL;
+void * MPU_pvTimerGetTimerID( const TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL;
+void MPU_vTimerSetTimerID( TimerHandle_t xTimer, void *pvNewID ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTimerIsTimerActive( TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL;
+TaskHandle_t MPU_xTimerGetTimerDaemonTaskHandle( void ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTimerPendFunctionCall( PendedFunction_t xFunctionToPend, void *pvParameter1, uint32_t ulParameter2, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
+const char * MPU_pcTimerGetName( TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL;
+void MPU_vTimerSetReloadMode( TimerHandle_t xTimer, const UBaseType_t uxAutoReload ) FREERTOS_SYSTEM_CALL;
+UBaseType_t MPU_uxTimerGetReloadMode( TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL;
+TickType_t MPU_xTimerGetPeriod( TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL;
+TickType_t MPU_xTimerGetExpiryTime( TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTimerCreateTimerTask( void ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTimerGenericCommand( TimerHandle_t xTimer, const BaseType_t xCommandID, const TickType_t xOptionalValue, BaseType_t * const pxHigherPriorityTaskWoken, const TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
+
+/* MPU versions of event_group.h API functions. */
+EventGroupHandle_t MPU_xEventGroupCreate( void ) FREERTOS_SYSTEM_CALL;
+EventGroupHandle_t MPU_xEventGroupCreateStatic( StaticEventGroup_t *pxEventGroupBuffer ) FREERTOS_SYSTEM_CALL;
+EventBits_t MPU_xEventGroupWaitBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToWaitFor, const BaseType_t xClearOnExit, const BaseType_t xWaitForAllBits, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
+EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToClear ) FREERTOS_SYSTEM_CALL;
+EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet ) FREERTOS_SYSTEM_CALL;
+EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet, const EventBits_t uxBitsToWaitFor, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
+void MPU_vEventGroupDelete( EventGroupHandle_t xEventGroup ) FREERTOS_SYSTEM_CALL;
+UBaseType_t MPU_uxEventGroupGetNumber( void* xEventGroup ) FREERTOS_SYSTEM_CALL;
+
+/* MPU versions of message/stream_buffer.h API functions. */
+size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer, const void *pvTxData, size_t xDataLengthBytes, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
+size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer, void *pvRxData, size_t xBufferLengthBytes, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
+size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL;
+void MPU_vStreamBufferDelete( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xStreamBufferReset( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL;
+size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL;
+size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer, size_t xTriggerLevel ) FREERTOS_SYSTEM_CALL;
+StreamBufferHandle_t MPU_xStreamBufferGenericCreate( size_t xBufferSizeBytes, size_t xTriggerLevelBytes, BaseType_t xIsMessageBuffer ) FREERTOS_SYSTEM_CALL;
+StreamBufferHandle_t MPU_xStreamBufferGenericCreateStatic( size_t xBufferSizeBytes, size_t xTriggerLevelBytes, BaseType_t xIsMessageBuffer, uint8_t * const pucStreamBufferStorageArea, StaticStreamBuffer_t * const pxStaticStreamBuffer ) FREERTOS_SYSTEM_CALL;
+
+
+
+#endif /* MPU_PROTOTYPES_H */
+
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h b/Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h
new file mode 100644
index 0000000..87a2f2c
--- /dev/null
+++ b/Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h
@@ -0,0 +1,189 @@
+/*
+ * FreeRTOS Kernel V10.3.1
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef MPU_WRAPPERS_H
+#define MPU_WRAPPERS_H
+
+/* This file redefines API functions to be called through a wrapper macro, but
+only for ports that are using the MPU. */
+#ifdef portUSING_MPU_WRAPPERS
+
+	/* MPU_WRAPPERS_INCLUDED_FROM_API_FILE will be defined when this file is
+	included from queue.c or task.c to prevent it from having an effect within
+	those files. */
+	#ifndef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+		/*
+		 * Map standard (non MPU) API functions to equivalents that start
+		 * "MPU_".  This will cause the application code to call the MPU_
+		 * version, which wraps the non-MPU version with privilege promoting
+		 * then demoting code, so the kernel code always runs will full
+		 * privileges.
+		 */
+
+		/* Map standard tasks.h API functions to the MPU equivalents. */
+		#define xTaskCreate								MPU_xTaskCreate
+		#define xTaskCreateStatic						MPU_xTaskCreateStatic
+		#define xTaskCreateRestricted					MPU_xTaskCreateRestricted
+		#define vTaskAllocateMPURegions					MPU_vTaskAllocateMPURegions
+		#define vTaskDelete								MPU_vTaskDelete
+		#define vTaskDelay								MPU_vTaskDelay
+		#define vTaskDelayUntil							MPU_vTaskDelayUntil
+		#define xTaskAbortDelay							MPU_xTaskAbortDelay
+		#define uxTaskPriorityGet						MPU_uxTaskPriorityGet
+		#define eTaskGetState							MPU_eTaskGetState
+		#define vTaskGetInfo							MPU_vTaskGetInfo
+		#define vTaskPrioritySet						MPU_vTaskPrioritySet
+		#define vTaskSuspend							MPU_vTaskSuspend
+		#define vTaskResume								MPU_vTaskResume
+		#define vTaskSuspendAll							MPU_vTaskSuspendAll
+		#define xTaskResumeAll							MPU_xTaskResumeAll
+		#define xTaskGetTickCount						MPU_xTaskGetTickCount
+		#define uxTaskGetNumberOfTasks					MPU_uxTaskGetNumberOfTasks
+		#define pcTaskGetName							MPU_pcTaskGetName
+		#define xTaskGetHandle							MPU_xTaskGetHandle
+		#define uxTaskGetStackHighWaterMark				MPU_uxTaskGetStackHighWaterMark
+		#define uxTaskGetStackHighWaterMark2			MPU_uxTaskGetStackHighWaterMark2
+		#define vTaskSetApplicationTaskTag				MPU_vTaskSetApplicationTaskTag
+		#define xTaskGetApplicationTaskTag				MPU_xTaskGetApplicationTaskTag
+		#define vTaskSetThreadLocalStoragePointer		MPU_vTaskSetThreadLocalStoragePointer
+		#define pvTaskGetThreadLocalStoragePointer		MPU_pvTaskGetThreadLocalStoragePointer
+		#define xTaskCallApplicationTaskHook			MPU_xTaskCallApplicationTaskHook
+		#define xTaskGetIdleTaskHandle					MPU_xTaskGetIdleTaskHandle
+		#define uxTaskGetSystemState					MPU_uxTaskGetSystemState
+		#define vTaskList								MPU_vTaskList
+		#define vTaskGetRunTimeStats					MPU_vTaskGetRunTimeStats
+		#define ulTaskGetIdleRunTimeCounter				MPU_ulTaskGetIdleRunTimeCounter
+		#define xTaskGenericNotify						MPU_xTaskGenericNotify
+		#define xTaskNotifyWait							MPU_xTaskNotifyWait
+		#define ulTaskNotifyTake						MPU_ulTaskNotifyTake
+		#define xTaskNotifyStateClear					MPU_xTaskNotifyStateClear
+		#define ulTaskNotifyValueClear					MPU_ulTaskNotifyValueClear
+		#define xTaskCatchUpTicks						MPU_xTaskCatchUpTicks
+
+		#define xTaskGetCurrentTaskHandle				MPU_xTaskGetCurrentTaskHandle
+		#define vTaskSetTimeOutState					MPU_vTaskSetTimeOutState
+		#define xTaskCheckForTimeOut					MPU_xTaskCheckForTimeOut
+		#define xTaskGetSchedulerState					MPU_xTaskGetSchedulerState
+
+		/* Map standard queue.h API functions to the MPU equivalents. */
+		#define xQueueGenericSend						MPU_xQueueGenericSend
+		#define xQueueReceive							MPU_xQueueReceive
+		#define xQueuePeek								MPU_xQueuePeek
+		#define xQueueSemaphoreTake						MPU_xQueueSemaphoreTake
+		#define uxQueueMessagesWaiting					MPU_uxQueueMessagesWaiting
+		#define uxQueueSpacesAvailable					MPU_uxQueueSpacesAvailable
+		#define vQueueDelete							MPU_vQueueDelete
+		#define xQueueCreateMutex						MPU_xQueueCreateMutex
+		#define xQueueCreateMutexStatic					MPU_xQueueCreateMutexStatic
+		#define xQueueCreateCountingSemaphore			MPU_xQueueCreateCountingSemaphore
+		#define xQueueCreateCountingSemaphoreStatic		MPU_xQueueCreateCountingSemaphoreStatic
+		#define xQueueGetMutexHolder					MPU_xQueueGetMutexHolder
+		#define xQueueTakeMutexRecursive				MPU_xQueueTakeMutexRecursive
+		#define xQueueGiveMutexRecursive				MPU_xQueueGiveMutexRecursive
+		#define xQueueGenericCreate						MPU_xQueueGenericCreate
+		#define xQueueGenericCreateStatic				MPU_xQueueGenericCreateStatic
+		#define xQueueCreateSet							MPU_xQueueCreateSet
+		#define xQueueAddToSet							MPU_xQueueAddToSet
+		#define xQueueRemoveFromSet						MPU_xQueueRemoveFromSet
+		#define xQueueSelectFromSet						MPU_xQueueSelectFromSet
+		#define xQueueGenericReset						MPU_xQueueGenericReset
+
+		#if( configQUEUE_REGISTRY_SIZE > 0 )
+			#define vQueueAddToRegistry						MPU_vQueueAddToRegistry
+			#define vQueueUnregisterQueue					MPU_vQueueUnregisterQueue
+			#define pcQueueGetName							MPU_pcQueueGetName
+		#endif
+
+		/* Map standard timer.h API functions to the MPU equivalents. */
+		#define xTimerCreate							MPU_xTimerCreate
+		#define xTimerCreateStatic						MPU_xTimerCreateStatic
+		#define pvTimerGetTimerID						MPU_pvTimerGetTimerID
+		#define vTimerSetTimerID						MPU_vTimerSetTimerID
+		#define xTimerIsTimerActive						MPU_xTimerIsTimerActive
+		#define xTimerGetTimerDaemonTaskHandle			MPU_xTimerGetTimerDaemonTaskHandle
+		#define xTimerPendFunctionCall					MPU_xTimerPendFunctionCall
+		#define pcTimerGetName							MPU_pcTimerGetName
+		#define vTimerSetReloadMode						MPU_vTimerSetReloadMode
+		#define uxTimerGetReloadMode					MPU_uxTimerGetReloadMode
+		#define xTimerGetPeriod							MPU_xTimerGetPeriod
+		#define xTimerGetExpiryTime						MPU_xTimerGetExpiryTime
+		#define xTimerGenericCommand					MPU_xTimerGenericCommand
+
+		/* Map standard event_group.h API functions to the MPU equivalents. */
+		#define xEventGroupCreate						MPU_xEventGroupCreate
+		#define xEventGroupCreateStatic					MPU_xEventGroupCreateStatic
+		#define xEventGroupWaitBits						MPU_xEventGroupWaitBits
+		#define xEventGroupClearBits					MPU_xEventGroupClearBits
+		#define xEventGroupSetBits						MPU_xEventGroupSetBits
+		#define xEventGroupSync							MPU_xEventGroupSync
+		#define vEventGroupDelete						MPU_vEventGroupDelete
+
+		/* Map standard message/stream_buffer.h API functions to the MPU
+		equivalents. */
+		#define xStreamBufferSend						MPU_xStreamBufferSend
+		#define xStreamBufferReceive					MPU_xStreamBufferReceive
+		#define xStreamBufferNextMessageLengthBytes		MPU_xStreamBufferNextMessageLengthBytes
+		#define vStreamBufferDelete						MPU_vStreamBufferDelete
+		#define xStreamBufferIsFull						MPU_xStreamBufferIsFull
+		#define xStreamBufferIsEmpty					MPU_xStreamBufferIsEmpty
+		#define xStreamBufferReset						MPU_xStreamBufferReset
+		#define xStreamBufferSpacesAvailable			MPU_xStreamBufferSpacesAvailable
+		#define xStreamBufferBytesAvailable				MPU_xStreamBufferBytesAvailable
+		#define xStreamBufferSetTriggerLevel			MPU_xStreamBufferSetTriggerLevel
+		#define xStreamBufferGenericCreate				MPU_xStreamBufferGenericCreate
+		#define xStreamBufferGenericCreateStatic		MPU_xStreamBufferGenericCreateStatic
+
+
+		/* Remove the privileged function macro, but keep the PRIVILEGED_DATA
+		macro so applications can place data in privileged access sections
+		(useful when using statically allocated objects). */
+		#define PRIVILEGED_FUNCTION
+		#define PRIVILEGED_DATA __attribute__((section("privileged_data")))
+		#define FREERTOS_SYSTEM_CALL
+
+	#else /* MPU_WRAPPERS_INCLUDED_FROM_API_FILE */
+
+		/* Ensure API functions go in the privileged execution section. */
+		#define PRIVILEGED_FUNCTION __attribute__((section("privileged_functions")))
+		#define PRIVILEGED_DATA __attribute__((section("privileged_data")))
+		#define FREERTOS_SYSTEM_CALL __attribute__((section( "freertos_system_calls")))
+
+	#endif /* MPU_WRAPPERS_INCLUDED_FROM_API_FILE */
+
+#else /* portUSING_MPU_WRAPPERS */
+
+	#define PRIVILEGED_FUNCTION
+	#define PRIVILEGED_DATA
+	#define FREERTOS_SYSTEM_CALL
+	#define portUSING_MPU_WRAPPERS 0
+
+#endif /* portUSING_MPU_WRAPPERS */
+
+
+#endif /* MPU_WRAPPERS_H */
+
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/include/portable.h b/Middlewares/Third_Party/FreeRTOS/Source/include/portable.h
new file mode 100644
index 0000000..47ceab9
--- /dev/null
+++ b/Middlewares/Third_Party/FreeRTOS/Source/include/portable.h
@@ -0,0 +1,199 @@
+/*
+ * FreeRTOS Kernel V10.3.1
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*-----------------------------------------------------------
+ * Portable layer API.  Each function must be defined for each port.
+ *----------------------------------------------------------*/
+
+#ifndef PORTABLE_H
+#define PORTABLE_H
+
+/* Each FreeRTOS port has a unique portmacro.h header file.  Originally a
+pre-processor definition was used to ensure the pre-processor found the correct
+portmacro.h file for the port being used.  That scheme was deprecated in favour
+of setting the compiler's include path such that it found the correct
+portmacro.h file - removing the need for the constant and allowing the
+portmacro.h file to be located anywhere in relation to the port being used.
+Purely for reasons of backward compatibility the old method is still valid, but
+to make it clear that new projects should not use it, support for the port
+specific constants has been moved into the deprecated_definitions.h header
+file. */
+#include "deprecated_definitions.h"
+
+/* If portENTER_CRITICAL is not defined then including deprecated_definitions.h
+did not result in a portmacro.h header file being included - and it should be
+included here.  In this case the path to the correct portmacro.h header file
+must be set in the compiler's include path. */
+#ifndef portENTER_CRITICAL
+	#include "portmacro.h"
+#endif
+
+#if portBYTE_ALIGNMENT == 32
+	#define portBYTE_ALIGNMENT_MASK ( 0x001f )
+#endif
+
+#if portBYTE_ALIGNMENT == 16
+	#define portBYTE_ALIGNMENT_MASK ( 0x000f )
+#endif
+
+#if portBYTE_ALIGNMENT == 8
+	#define portBYTE_ALIGNMENT_MASK ( 0x0007 )
+#endif
+
+#if portBYTE_ALIGNMENT == 4
+	#define portBYTE_ALIGNMENT_MASK	( 0x0003 )
+#endif
+
+#if portBYTE_ALIGNMENT == 2
+	#define portBYTE_ALIGNMENT_MASK	( 0x0001 )
+#endif
+
+#if portBYTE_ALIGNMENT == 1
+	#define portBYTE_ALIGNMENT_MASK	( 0x0000 )
+#endif
+
+#ifndef portBYTE_ALIGNMENT_MASK
+	#error "Invalid portBYTE_ALIGNMENT definition"
+#endif
+
+#ifndef portNUM_CONFIGURABLE_REGIONS
+	#define portNUM_CONFIGURABLE_REGIONS 1
+#endif
+
+#ifndef portHAS_STACK_OVERFLOW_CHECKING
+	#define portHAS_STACK_OVERFLOW_CHECKING 0
+#endif
+
+#ifndef portARCH_NAME
+	#define portARCH_NAME NULL
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "mpu_wrappers.h"
+
+/*
+ * Setup the stack of a new task so it is ready to be placed under the
+ * scheduler control.  The registers have to be placed on the stack in
+ * the order that the port expects to find them.
+ *
+ */
+#if( portUSING_MPU_WRAPPERS == 1 )
+	#if( portHAS_STACK_OVERFLOW_CHECKING == 1 )
+		StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, StackType_t *pxEndOfStack, TaskFunction_t pxCode, void *pvParameters, BaseType_t xRunPrivileged ) PRIVILEGED_FUNCTION;
+	#else
+		StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters, BaseType_t xRunPrivileged ) PRIVILEGED_FUNCTION;
+	#endif
+#else
+	#if( portHAS_STACK_OVERFLOW_CHECKING == 1 )
+		StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, StackType_t *pxEndOfStack, TaskFunction_t pxCode, void *pvParameters ) PRIVILEGED_FUNCTION;
+	#else
+		StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) PRIVILEGED_FUNCTION;
+	#endif
+#endif
+
+/* Used by heap_5.c to define the start address and size of each memory region
+that together comprise the total FreeRTOS heap space. */
+typedef struct HeapRegion
+{
+	uint8_t *pucStartAddress;
+	size_t xSizeInBytes;
+} HeapRegion_t;
+
+/* Used to pass information about the heap out of vPortGetHeapStats(). */
+typedef struct xHeapStats
+{
+	size_t xAvailableHeapSpaceInBytes;		/* The total heap size currently available - this is the sum of all the free blocks, not the largest block that can be allocated. */
+	size_t xSizeOfLargestFreeBlockInBytes; 	/* The maximum size, in bytes, of all the free blocks within the heap at the time vPortGetHeapStats() is called. */
+	size_t xSizeOfSmallestFreeBlockInBytes; /* The minimum size, in bytes, of all the free blocks within the heap at the time vPortGetHeapStats() is called. */
+	size_t xNumberOfFreeBlocks;				/* The number of free memory blocks within the heap at the time vPortGetHeapStats() is called. */
+	size_t xMinimumEverFreeBytesRemaining;	/* The minimum amount of total free memory (sum of all free blocks) there has been in the heap since the system booted. */
+	size_t xNumberOfSuccessfulAllocations;	/* The number of calls to pvPortMalloc() that have returned a valid memory block. */
+	size_t xNumberOfSuccessfulFrees;		/* The number of calls to vPortFree() that has successfully freed a block of memory. */
+} HeapStats_t;
+
+/*
+ * Used to define multiple heap regions for use by heap_5.c.  This function
+ * must be called before any calls to pvPortMalloc() - not creating a task,
+ * queue, semaphore, mutex, software timer, event group, etc. will result in
+ * pvPortMalloc being called.
+ *
+ * pxHeapRegions passes in an array of HeapRegion_t structures - each of which
+ * defines a region of memory that can be used as the heap.  The array is
+ * terminated by a HeapRegions_t structure that has a size of 0.  The region
+ * with the lowest start address must appear first in the array.
+ */
+void vPortDefineHeapRegions( const HeapRegion_t * const pxHeapRegions ) PRIVILEGED_FUNCTION;
+
+/*
+ * Returns a HeapStats_t structure filled with information about the current
+ * heap state.
+ */
+void vPortGetHeapStats( HeapStats_t *pxHeapStats );
+
+/*
+ * Map to the memory management routines required for the port.
+ */
+void *pvPortMalloc( size_t xSize ) PRIVILEGED_FUNCTION;
+void vPortFree( void *pv ) PRIVILEGED_FUNCTION;
+void vPortInitialiseBlocks( void ) PRIVILEGED_FUNCTION;
+size_t xPortGetFreeHeapSize( void ) PRIVILEGED_FUNCTION;
+size_t xPortGetMinimumEverFreeHeapSize( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * Setup the hardware ready for the scheduler to take control.  This generally
+ * sets up a tick interrupt and sets timers for the correct tick frequency.
+ */
+BaseType_t xPortStartScheduler( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * Undo any hardware/ISR setup that was performed by xPortStartScheduler() so
+ * the hardware is left in its original condition after the scheduler stops
+ * executing.
+ */
+void vPortEndScheduler( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * The structures and methods of manipulating the MPU are contained within the
+ * port layer.
+ *
+ * Fills the xMPUSettings structure with the memory region information
+ * contained in xRegions.
+ */
+#if( portUSING_MPU_WRAPPERS == 1 )
+	struct xMEMORY_REGION;
+	void vPortStoreTaskMPUSettings( xMPU_SETTINGS *xMPUSettings, const struct xMEMORY_REGION * const xRegions, StackType_t *pxBottomOfStack, uint32_t ulStackDepth ) PRIVILEGED_FUNCTION;
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTABLE_H */
+
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h b/Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h
new file mode 100644
index 0000000..75d4155
--- /dev/null
+++ b/Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h
@@ -0,0 +1,124 @@
+/*
+ * FreeRTOS Kernel V10.3.1
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef PROJDEFS_H
+#define PROJDEFS_H
+
+/*
+ * Defines the prototype to which task functions must conform.  Defined in this
+ * file to ensure the type is known before portable.h is included.
+ */
+typedef void (*TaskFunction_t)( void * );
+
+/* Converts a time in milliseconds to a time in ticks.  This macro can be
+overridden by a macro of the same name defined in FreeRTOSConfig.h in case the
+definition here is not suitable for your application. */
+#ifndef pdMS_TO_TICKS
+	#define pdMS_TO_TICKS( xTimeInMs ) ( ( TickType_t ) ( ( ( TickType_t ) ( xTimeInMs ) * ( TickType_t ) configTICK_RATE_HZ ) / ( TickType_t ) 1000 ) )
+#endif
+
+#define pdFALSE			( ( BaseType_t ) 0 )
+#define pdTRUE			( ( BaseType_t ) 1 )
+
+#define pdPASS			( pdTRUE )
+#define pdFAIL			( pdFALSE )
+#define errQUEUE_EMPTY	( ( BaseType_t ) 0 )
+#define errQUEUE_FULL	( ( BaseType_t ) 0 )
+
+/* FreeRTOS error definitions. */
+#define errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY	( -1 )
+#define errQUEUE_BLOCKED						( -4 )
+#define errQUEUE_YIELD							( -5 )
+
+/* Macros used for basic data corruption checks. */
+#ifndef configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES
+	#define configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES 0
+#endif
+
+#if( configUSE_16_BIT_TICKS == 1 )
+	#define pdINTEGRITY_CHECK_VALUE 0x5a5a
+#else
+	#define pdINTEGRITY_CHECK_VALUE 0x5a5a5a5aUL
+#endif
+
+/* The following errno values are used by FreeRTOS+ components, not FreeRTOS
+itself. */
+#define pdFREERTOS_ERRNO_NONE			0	/* No errors */
+#define	pdFREERTOS_ERRNO_ENOENT			2	/* No such file or directory */
+#define	pdFREERTOS_ERRNO_EINTR			4	/* Interrupted system call */
+#define	pdFREERTOS_ERRNO_EIO			5	/* I/O error */
+#define	pdFREERTOS_ERRNO_ENXIO			6	/* No such device or address */
+#define	pdFREERTOS_ERRNO_EBADF			9	/* Bad file number */
+#define	pdFREERTOS_ERRNO_EAGAIN			11	/* No more processes */
+#define	pdFREERTOS_ERRNO_EWOULDBLOCK	11	/* Operation would block */
+#define	pdFREERTOS_ERRNO_ENOMEM			12	/* Not enough memory */
+#define	pdFREERTOS_ERRNO_EACCES			13	/* Permission denied */
+#define	pdFREERTOS_ERRNO_EFAULT			14	/* Bad address */
+#define	pdFREERTOS_ERRNO_EBUSY			16	/* Mount device busy */
+#define	pdFREERTOS_ERRNO_EEXIST			17	/* File exists */
+#define	pdFREERTOS_ERRNO_EXDEV			18	/* Cross-device link */
+#define	pdFREERTOS_ERRNO_ENODEV			19	/* No such device */
+#define	pdFREERTOS_ERRNO_ENOTDIR		20	/* Not a directory */
+#define	pdFREERTOS_ERRNO_EISDIR			21	/* Is a directory */
+#define	pdFREERTOS_ERRNO_EINVAL			22	/* Invalid argument */
+#define	pdFREERTOS_ERRNO_ENOSPC			28	/* No space left on device */
+#define	pdFREERTOS_ERRNO_ESPIPE			29	/* Illegal seek */
+#define	pdFREERTOS_ERRNO_EROFS			30	/* Read only file system */
+#define	pdFREERTOS_ERRNO_EUNATCH		42	/* Protocol driver not attached */
+#define	pdFREERTOS_ERRNO_EBADE			50	/* Invalid exchange */
+#define	pdFREERTOS_ERRNO_EFTYPE			79	/* Inappropriate file type or format */
+#define	pdFREERTOS_ERRNO_ENMFILE		89	/* No more files */
+#define	pdFREERTOS_ERRNO_ENOTEMPTY		90	/* Directory not empty */
+#define	pdFREERTOS_ERRNO_ENAMETOOLONG 	91	/* File or path name too long */
+#define	pdFREERTOS_ERRNO_EOPNOTSUPP		95	/* Operation not supported on transport endpoint */
+#define	pdFREERTOS_ERRNO_ENOBUFS		105	/* No buffer space available */
+#define	pdFREERTOS_ERRNO_ENOPROTOOPT	109	/* Protocol not available */
+#define	pdFREERTOS_ERRNO_EADDRINUSE		112	/* Address already in use */
+#define	pdFREERTOS_ERRNO_ETIMEDOUT		116	/* Connection timed out */
+#define	pdFREERTOS_ERRNO_EINPROGRESS	119	/* Connection already in progress */
+#define	pdFREERTOS_ERRNO_EALREADY		120	/* Socket already connected */
+#define	pdFREERTOS_ERRNO_EADDRNOTAVAIL 	125	/* Address not available */
+#define	pdFREERTOS_ERRNO_EISCONN		127	/* Socket is already connected */
+#define	pdFREERTOS_ERRNO_ENOTCONN		128	/* Socket is not connected */
+#define	pdFREERTOS_ERRNO_ENOMEDIUM		135	/* No medium inserted */
+#define	pdFREERTOS_ERRNO_EILSEQ			138	/* An invalid UTF-16 sequence was encountered. */
+#define	pdFREERTOS_ERRNO_ECANCELED		140	/* Operation canceled. */
+
+/* The following endian values are used by FreeRTOS+ components, not FreeRTOS
+itself. */
+#define pdFREERTOS_LITTLE_ENDIAN		0
+#define pdFREERTOS_BIG_ENDIAN			1
+
+/* Re-defining endian values for generic naming. */
+#define pdLITTLE_ENDIAN					pdFREERTOS_LITTLE_ENDIAN
+#define pdBIG_ENDIAN					pdFREERTOS_BIG_ENDIAN
+
+
+#endif /* PROJDEFS_H */
+
+
+
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/include/queue.h b/Middlewares/Third_Party/FreeRTOS/Source/include/queue.h
new file mode 100644
index 0000000..fb82315
--- /dev/null
+++ b/Middlewares/Third_Party/FreeRTOS/Source/include/queue.h
@@ -0,0 +1,1655 @@
+/*
+ * FreeRTOS Kernel V10.3.1
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef QUEUE_H
+#define QUEUE_H
+
+#ifndef INC_FREERTOS_H
+	#error "include FreeRTOS.h" must appear in source files before "include queue.h"
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "task.h"
+
+/**
+ * Type by which queues are referenced.  For example, a call to xQueueCreate()
+ * returns an QueueHandle_t variable that can then be used as a parameter to
+ * xQueueSend(), xQueueReceive(), etc.
+ */
+struct QueueDefinition; /* Using old naming convention so as not to break kernel aware debuggers. */
+typedef struct QueueDefinition * QueueHandle_t;
+
+/**
+ * Type by which queue sets are referenced.  For example, a call to
+ * xQueueCreateSet() returns an xQueueSet variable that can then be used as a
+ * parameter to xQueueSelectFromSet(), xQueueAddToSet(), etc.
+ */
+typedef struct QueueDefinition * QueueSetHandle_t;
+
+/**
+ * Queue sets can contain both queues and semaphores, so the
+ * QueueSetMemberHandle_t is defined as a type to be used where a parameter or
+ * return value can be either an QueueHandle_t or an SemaphoreHandle_t.
+ */
+typedef struct QueueDefinition * QueueSetMemberHandle_t;
+
+/* For internal use only. */
+#define	queueSEND_TO_BACK		( ( BaseType_t ) 0 )
+#define	queueSEND_TO_FRONT		( ( BaseType_t ) 1 )
+#define queueOVERWRITE			( ( BaseType_t ) 2 )
+
+/* For internal use only.  These definitions *must* match those in queue.c. */
+#define queueQUEUE_TYPE_BASE				( ( uint8_t ) 0U )
+#define queueQUEUE_TYPE_SET					( ( uint8_t ) 0U )
+#define queueQUEUE_TYPE_MUTEX 				( ( uint8_t ) 1U )
+#define queueQUEUE_TYPE_COUNTING_SEMAPHORE	( ( uint8_t ) 2U )
+#define queueQUEUE_TYPE_BINARY_SEMAPHORE	( ( uint8_t ) 3U )
+#define queueQUEUE_TYPE_RECURSIVE_MUTEX		( ( uint8_t ) 4U )
+
+/**
+ * queue. h
+ * <pre>
+ QueueHandle_t xQueueCreate(
+							  UBaseType_t uxQueueLength,
+							  UBaseType_t uxItemSize
+						  );
+ * </pre>
+ *
+ * Creates a new queue instance, and returns a handle by which the new queue
+ * can be referenced.
+ *
+ * Internally, within the FreeRTOS implementation, queues use two blocks of
+ * memory.  The first block is used to hold the queue's data structures.  The
+ * second block is used to hold items placed into the queue.  If a queue is
+ * created using xQueueCreate() then both blocks of memory are automatically
+ * dynamically allocated inside the xQueueCreate() function.  (see
+ * http://www.freertos.org/a00111.html).  If a queue is created using
+ * xQueueCreateStatic() then the application writer must provide the memory that
+ * will get used by the queue.  xQueueCreateStatic() therefore allows a queue to
+ * be created without using any dynamic memory allocation.
+ *
+ * http://www.FreeRTOS.org/Embedded-RTOS-Queues.html
+ *
+ * @param uxQueueLength The maximum number of items that the queue can contain.
+ *
+ * @param uxItemSize The number of bytes each item in the queue will require.
+ * Items are queued by copy, not by reference, so this is the number of bytes
+ * that will be copied for each posted item.  Each item on the queue must be
+ * the same size.
+ *
+ * @return If the queue is successfully create then a handle to the newly
+ * created queue is returned.  If the queue cannot be created then 0 is
+ * returned.
+ *
+ * Example usage:
+   <pre>
+ struct AMessage
+ {
+	char ucMessageID;
+	char ucData[ 20 ];
+ };
+
+ void vATask( void *pvParameters )
+ {
+ QueueHandle_t xQueue1, xQueue2;
+
+	// Create a queue capable of containing 10 uint32_t values.
+	xQueue1 = xQueueCreate( 10, sizeof( uint32_t ) );
+	if( xQueue1 == 0 )
+	{
+		// Queue was not created and must not be used.
+	}
+
+	// Create a queue capable of containing 10 pointers to AMessage structures.
+	// These should be passed by pointer as they contain a lot of data.
+	xQueue2 = xQueueCreate( 10, sizeof( struct AMessage * ) );
+	if( xQueue2 == 0 )
+	{
+		// Queue was not created and must not be used.
+	}
+
+	// ... Rest of task code.
+ }
+ </pre>
+ * \defgroup xQueueCreate xQueueCreate
+ * \ingroup QueueManagement
+ */
+#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+	#define xQueueCreate( uxQueueLength, uxItemSize ) xQueueGenericCreate( ( uxQueueLength ), ( uxItemSize ), ( queueQUEUE_TYPE_BASE ) )
+#endif
+
+/**
+ * queue. h
+ * <pre>
+ QueueHandle_t xQueueCreateStatic(
+							  UBaseType_t uxQueueLength,
+							  UBaseType_t uxItemSize,
+							  uint8_t *pucQueueStorageBuffer,
+							  StaticQueue_t *pxQueueBuffer
+						  );
+ * </pre>
+ *
+ * Creates a new queue instance, and returns a handle by which the new queue
+ * can be referenced.
+ *
+ * Internally, within the FreeRTOS implementation, queues use two blocks of
+ * memory.  The first block is used to hold the queue's data structures.  The
+ * second block is used to hold items placed into the queue.  If a queue is
+ * created using xQueueCreate() then both blocks of memory are automatically
+ * dynamically allocated inside the xQueueCreate() function.  (see
+ * http://www.freertos.org/a00111.html).  If a queue is created using
+ * xQueueCreateStatic() then the application writer must provide the memory that
+ * will get used by the queue.  xQueueCreateStatic() therefore allows a queue to
+ * be created without using any dynamic memory allocation.
+ *
+ * http://www.FreeRTOS.org/Embedded-RTOS-Queues.html
+ *
+ * @param uxQueueLength The maximum number of items that the queue can contain.
+ *
+ * @param uxItemSize The number of bytes each item in the queue will require.
+ * Items are queued by copy, not by reference, so this is the number of bytes
+ * that will be copied for each posted item.  Each item on the queue must be
+ * the same size.
+ *
+ * @param pucQueueStorageBuffer If uxItemSize is not zero then
+ * pucQueueStorageBuffer must point to a uint8_t array that is at least large
+ * enough to hold the maximum number of items that can be in the queue at any
+ * one time - which is ( uxQueueLength * uxItemsSize ) bytes.  If uxItemSize is
+ * zero then pucQueueStorageBuffer can be NULL.
+ *
+ * @param pxQueueBuffer Must point to a variable of type StaticQueue_t, which
+ * will be used to hold the queue's data structure.
+ *
+ * @return If the queue is created then a handle to the created queue is
+ * returned.  If pxQueueBuffer is NULL then NULL is returned.
+ *
+ * Example usage:
+   <pre>
+ struct AMessage
+ {
+	char ucMessageID;
+	char ucData[ 20 ];
+ };
+
+ #define QUEUE_LENGTH 10
+ #define ITEM_SIZE sizeof( uint32_t )
+
+ // xQueueBuffer will hold the queue structure.
+ StaticQueue_t xQueueBuffer;
+
+ // ucQueueStorage will hold the items posted to the queue.  Must be at least
+ // [(queue length) * ( queue item size)] bytes long.
+ uint8_t ucQueueStorage[ QUEUE_LENGTH * ITEM_SIZE ];
+
+ void vATask( void *pvParameters )
+ {
+ QueueHandle_t xQueue1;
+
+	// Create a queue capable of containing 10 uint32_t values.
+	xQueue1 = xQueueCreate( QUEUE_LENGTH, // The number of items the queue can hold.
+							ITEM_SIZE	  // The size of each item in the queue
+							&( ucQueueStorage[ 0 ] ), // The buffer that will hold the items in the queue.
+							&xQueueBuffer ); // The buffer that will hold the queue structure.
+
+	// The queue is guaranteed to be created successfully as no dynamic memory
+	// allocation is used.  Therefore xQueue1 is now a handle to a valid queue.
+
+	// ... Rest of task code.
+ }
+ </pre>
+ * \defgroup xQueueCreateStatic xQueueCreateStatic
+ * \ingroup QueueManagement
+ */
+#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+	#define xQueueCreateStatic( uxQueueLength, uxItemSize, pucQueueStorage, pxQueueBuffer ) xQueueGenericCreateStatic( ( uxQueueLength ), ( uxItemSize ), ( pucQueueStorage ), ( pxQueueBuffer ), ( queueQUEUE_TYPE_BASE ) )
+#endif /* configSUPPORT_STATIC_ALLOCATION */
+
+/**
+ * queue. h
+ * <pre>
+ BaseType_t xQueueSendToToFront(
+								   QueueHandle_t	xQueue,
+								   const void		*pvItemToQueue,
+								   TickType_t		xTicksToWait
+							   );
+ * </pre>
+ *
+ * Post an item to the front of a queue.  The item is queued by copy, not by
+ * reference.  This function must not be called from an interrupt service
+ * routine.  See xQueueSendFromISR () for an alternative which may be used
+ * in an ISR.
+ *
+ * @param xQueue The handle to the queue on which the item is to be posted.
+ *
+ * @param pvItemToQueue A pointer to the item that is to be placed on the
+ * queue.  The size of the items the queue will hold was defined when the
+ * queue was created, so this many bytes will be copied from pvItemToQueue
+ * into the queue storage area.
+ *
+ * @param xTicksToWait The maximum amount of time the task should block
+ * waiting for space to become available on the queue, should it already
+ * be full.  The call will return immediately if this is set to 0 and the
+ * queue is full.  The time is defined in tick periods so the constant
+ * portTICK_PERIOD_MS should be used to convert to real time if this is required.
+ *
+ * @return pdTRUE if the item was successfully posted, otherwise errQUEUE_FULL.
+ *
+ * Example usage:
+   <pre>
+ struct AMessage
+ {
+	char ucMessageID;
+	char ucData[ 20 ];
+ } xMessage;
+
+ uint32_t ulVar = 10UL;
+
+ void vATask( void *pvParameters )
+ {
+ QueueHandle_t xQueue1, xQueue2;
+ struct AMessage *pxMessage;
+
+	// Create a queue capable of containing 10 uint32_t values.
+	xQueue1 = xQueueCreate( 10, sizeof( uint32_t ) );
+
+	// Create a queue capable of containing 10 pointers to AMessage structures.
+	// These should be passed by pointer as they contain a lot of data.
+	xQueue2 = xQueueCreate( 10, sizeof( struct AMessage * ) );
+
+	// ...
+
+	if( xQueue1 != 0 )
+	{
+		// Send an uint32_t.  Wait for 10 ticks for space to become
+		// available if necessary.
+		if( xQueueSendToFront( xQueue1, ( void * ) &ulVar, ( TickType_t ) 10 ) != pdPASS )
+		{
+			// Failed to post the message, even after 10 ticks.
+		}
+	}
+
+	if( xQueue2 != 0 )
+	{
+		// Send a pointer to a struct AMessage object.  Don't block if the
+		// queue is already full.
+		pxMessage = & xMessage;
+		xQueueSendToFront( xQueue2, ( void * ) &pxMessage, ( TickType_t ) 0 );
+	}
+
+	// ... Rest of task code.
+ }
+ </pre>
+ * \defgroup xQueueSend xQueueSend
+ * \ingroup QueueManagement
+ */
+#define xQueueSendToFront( xQueue, pvItemToQueue, xTicksToWait ) xQueueGenericSend( ( xQueue ), ( pvItemToQueue ), ( xTicksToWait ), queueSEND_TO_FRONT )
+
+/**
+ * queue. h
+ * <pre>
+ BaseType_t xQueueSendToBack(
+								   QueueHandle_t	xQueue,
+								   const void		*pvItemToQueue,
+								   TickType_t		xTicksToWait
+							   );
+ * </pre>
+ *
+ * This is a macro that calls xQueueGenericSend().
+ *
+ * Post an item to the back of a queue.  The item is queued by copy, not by
+ * reference.  This function must not be called from an interrupt service
+ * routine.  See xQueueSendFromISR () for an alternative which may be used
+ * in an ISR.
+ *
+ * @param xQueue The handle to the queue on which the item is to be posted.
+ *
+ * @param pvItemToQueue A pointer to the item that is to be placed on the
+ * queue.  The size of the items the queue will hold was defined when the
+ * queue was created, so this many bytes will be copied from pvItemToQueue
+ * into the queue storage area.
+ *
+ * @param xTicksToWait The maximum amount of time the task should block
+ * waiting for space to become available on the queue, should it already
+ * be full.  The call will return immediately if this is set to 0 and the queue
+ * is full.  The  time is defined in tick periods so the constant
+ * portTICK_PERIOD_MS should be used to convert to real time if this is required.
+ *
+ * @return pdTRUE if the item was successfully posted, otherwise errQUEUE_FULL.
+ *
+ * Example usage:
+   <pre>
+ struct AMessage
+ {
+	char ucMessageID;
+	char ucData[ 20 ];
+ } xMessage;
+
+ uint32_t ulVar = 10UL;
+
+ void vATask( void *pvParameters )
+ {
+ QueueHandle_t xQueue1, xQueue2;
+ struct AMessage *pxMessage;
+
+	// Create a queue capable of containing 10 uint32_t values.
+	xQueue1 = xQueueCreate( 10, sizeof( uint32_t ) );
+
+	// Create a queue capable of containing 10 pointers to AMessage structures.
+	// These should be passed by pointer as they contain a lot of data.
+	xQueue2 = xQueueCreate( 10, sizeof( struct AMessage * ) );
+
+	// ...
+
+	if( xQueue1 != 0 )
+	{
+		// Send an uint32_t.  Wait for 10 ticks for space to become
+		// available if necessary.
+		if( xQueueSendToBack( xQueue1, ( void * ) &ulVar, ( TickType_t ) 10 ) != pdPASS )
+		{
+			// Failed to post the message, even after 10 ticks.
+		}
+	}
+
+	if( xQueue2 != 0 )
+	{
+		// Send a pointer to a struct AMessage object.  Don't block if the
+		// queue is already full.
+		pxMessage = & xMessage;
+		xQueueSendToBack( xQueue2, ( void * ) &pxMessage, ( TickType_t ) 0 );
+	}
+
+	// ... Rest of task code.
+ }
+ </pre>
+ * \defgroup xQueueSend xQueueSend
+ * \ingroup QueueManagement
+ */
+#define xQueueSendToBack( xQueue, pvItemToQueue, xTicksToWait ) xQueueGenericSend( ( xQueue ), ( pvItemToQueue ), ( xTicksToWait ), queueSEND_TO_BACK )
+
+/**
+ * queue. h
+ * <pre>
+ BaseType_t xQueueSend(
+							  QueueHandle_t xQueue,
+							  const void * pvItemToQueue,
+							  TickType_t xTicksToWait
+						 );
+ * </pre>
+ *
+ * This is a macro that calls xQueueGenericSend().  It is included for
+ * backward compatibility with versions of FreeRTOS.org that did not
+ * include the xQueueSendToFront() and xQueueSendToBack() macros.  It is
+ * equivalent to xQueueSendToBack().
+ *
+ * Post an item on a queue.  The item is queued by copy, not by reference.
+ * This function must not be called from an interrupt service routine.
+ * See xQueueSendFromISR () for an alternative which may be used in an ISR.
+ *
+ * @param xQueue The handle to the queue on which the item is to be posted.
+ *
+ * @param pvItemToQueue A pointer to the item that is to be placed on the
+ * queue.  The size of the items the queue will hold was defined when the
+ * queue was created, so this many bytes will be copied from pvItemToQueue
+ * into the queue storage area.
+ *
+ * @param xTicksToWait The maximum amount of time the task should block
+ * waiting for space to become available on the queue, should it already
+ * be full.  The call will return immediately if this is set to 0 and the
+ * queue is full.  The time is defined in tick periods so the constant
+ * portTICK_PERIOD_MS should be used to convert to real time if this is required.
+ *
+ * @return pdTRUE if the item was successfully posted, otherwise errQUEUE_FULL.
+ *
+ * Example usage:
+   <pre>
+ struct AMessage
+ {
+	char ucMessageID;
+	char ucData[ 20 ];
+ } xMessage;
+
+ uint32_t ulVar = 10UL;
+
+ void vATask( void *pvParameters )
+ {
+ QueueHandle_t xQueue1, xQueue2;
+ struct AMessage *pxMessage;
+
+	// Create a queue capable of containing 10 uint32_t values.
+	xQueue1 = xQueueCreate( 10, sizeof( uint32_t ) );
+
+	// Create a queue capable of containing 10 pointers to AMessage structures.
+	// These should be passed by pointer as they contain a lot of data.
+	xQueue2 = xQueueCreate( 10, sizeof( struct AMessage * ) );
+
+	// ...
+
+	if( xQueue1 != 0 )
+	{
+		// Send an uint32_t.  Wait for 10 ticks for space to become
+		// available if necessary.
+		if( xQueueSend( xQueue1, ( void * ) &ulVar, ( TickType_t ) 10 ) != pdPASS )
+		{
+			// Failed to post the message, even after 10 ticks.
+		}
+	}
+
+	if( xQueue2 != 0 )
+	{
+		// Send a pointer to a struct AMessage object.  Don't block if the
+		// queue is already full.
+		pxMessage = & xMessage;
+		xQueueSend( xQueue2, ( void * ) &pxMessage, ( TickType_t ) 0 );
+	}
+
+	// ... Rest of task code.
+ }
+ </pre>
+ * \defgroup xQueueSend xQueueSend
+ * \ingroup QueueManagement
+ */
+#define xQueueSend( xQueue, pvItemToQueue, xTicksToWait ) xQueueGenericSend( ( xQueue ), ( pvItemToQueue ), ( xTicksToWait ), queueSEND_TO_BACK )
+
+/**
+ * queue. h
+ * <pre>
+ BaseType_t xQueueOverwrite(
+							  QueueHandle_t xQueue,
+							  const void * pvItemToQueue
+						 );
+ * </pre>
+ *
+ * Only for use with queues that have a length of one - so the queue is either
+ * empty or full.
+ *
+ * Post an item on a queue.  If the queue is already full then overwrite the
+ * value held in the queue.  The item is queued by copy, not by reference.
+ *
+ * This function must not be called from an interrupt service routine.
+ * See xQueueOverwriteFromISR () for an alternative which may be used in an ISR.
+ *
+ * @param xQueue The handle of the queue to which the data is being sent.
+ *
+ * @param pvItemToQueue A pointer to the item that is to be placed on the
+ * queue.  The size of the items the queue will hold was defined when the
+ * queue was created, so this many bytes will be copied from pvItemToQueue
+ * into the queue storage area.
+ *
+ * @return xQueueOverwrite() is a macro that calls xQueueGenericSend(), and
+ * therefore has the same return values as xQueueSendToFront().  However, pdPASS
+ * is the only value that can be returned because xQueueOverwrite() will write
+ * to the queue even when the queue is already full.
+ *
+ * Example usage:
+   <pre>
+
+ void vFunction( void *pvParameters )
+ {
+ QueueHandle_t xQueue;
+ uint32_t ulVarToSend, ulValReceived;
+
+	// Create a queue to hold one uint32_t value.  It is strongly
+	// recommended *not* to use xQueueOverwrite() on queues that can
+	// contain more than one value, and doing so will trigger an assertion
+	// if configASSERT() is defined.
+	xQueue = xQueueCreate( 1, sizeof( uint32_t ) );
+
+	// Write the value 10 to the queue using xQueueOverwrite().
+	ulVarToSend = 10;
+	xQueueOverwrite( xQueue, &ulVarToSend );
+
+	// Peeking the queue should now return 10, but leave the value 10 in
+	// the queue.  A block time of zero is used as it is known that the
+	// queue holds a value.
+	ulValReceived = 0;
+	xQueuePeek( xQueue, &ulValReceived, 0 );
+
+	if( ulValReceived != 10 )
+	{
+		// Error unless the item was removed by a different task.
+	}
+
+	// The queue is still full.  Use xQueueOverwrite() to overwrite the
+	// value held in the queue with 100.
+	ulVarToSend = 100;
+	xQueueOverwrite( xQueue, &ulVarToSend );
+
+	// This time read from the queue, leaving the queue empty once more.
+	// A block time of 0 is used again.
+	xQueueReceive( xQueue, &ulValReceived, 0 );
+
+	// The value read should be the last value written, even though the
+	// queue was already full when the value was written.
+	if( ulValReceived != 100 )
+	{
+		// Error!
+	}
+
+	// ...
+}
+ </pre>
+ * \defgroup xQueueOverwrite xQueueOverwrite
+ * \ingroup QueueManagement
+ */
+#define xQueueOverwrite( xQueue, pvItemToQueue ) xQueueGenericSend( ( xQueue ), ( pvItemToQueue ), 0, queueOVERWRITE )
+
+
+/**
+ * queue. h
+ * <pre>
+ BaseType_t xQueueGenericSend(
+									QueueHandle_t xQueue,
+									const void * pvItemToQueue,
+									TickType_t xTicksToWait
+									BaseType_t xCopyPosition
+								);
+ * </pre>
+ *
+ * It is preferred that the macros xQueueSend(), xQueueSendToFront() and
+ * xQueueSendToBack() are used in place of calling this function directly.
+ *
+ * Post an item on a queue.  The item is queued by copy, not by reference.
+ * This function must not be called from an interrupt service routine.
+ * See xQueueSendFromISR () for an alternative which may be used in an ISR.
+ *
+ * @param xQueue The handle to the queue on which the item is to be posted.
+ *
+ * @param pvItemToQueue A pointer to the item that is to be placed on the
+ * queue.  The size of the items the queue will hold was defined when the
+ * queue was created, so this many bytes will be copied from pvItemToQueue
+ * into the queue storage area.
+ *
+ * @param xTicksToWait The maximum amount of time the task should block
+ * waiting for space to become available on the queue, should it already
+ * be full.  The call will return immediately if this is set to 0 and the
+ * queue is full.  The time is defined in tick periods so the constant
+ * portTICK_PERIOD_MS should be used to convert to real time if this is required.
+ *
+ * @param xCopyPosition Can take the value queueSEND_TO_BACK to place the
+ * item at the back of the queue, or queueSEND_TO_FRONT to place the item
+ * at the front of the queue (for high priority messages).
+ *
+ * @return pdTRUE if the item was successfully posted, otherwise errQUEUE_FULL.
+ *
+ * Example usage:
+   <pre>
+ struct AMessage
+ {
+	char ucMessageID;
+	char ucData[ 20 ];
+ } xMessage;
+
+ uint32_t ulVar = 10UL;
+
+ void vATask( void *pvParameters )
+ {
+ QueueHandle_t xQueue1, xQueue2;
+ struct AMessage *pxMessage;
+
+	// Create a queue capable of containing 10 uint32_t values.
+	xQueue1 = xQueueCreate( 10, sizeof( uint32_t ) );
+
+	// Create a queue capable of containing 10 pointers to AMessage structures.
+	// These should be passed by pointer as they contain a lot of data.
+	xQueue2 = xQueueCreate( 10, sizeof( struct AMessage * ) );
+
+	// ...
+
+	if( xQueue1 != 0 )
+	{
+		// Send an uint32_t.  Wait for 10 ticks for space to become
+		// available if necessary.
+		if( xQueueGenericSend( xQueue1, ( void * ) &ulVar, ( TickType_t ) 10, queueSEND_TO_BACK ) != pdPASS )
+		{
+			// Failed to post the message, even after 10 ticks.
+		}
+	}
+
+	if( xQueue2 != 0 )
+	{
+		// Send a pointer to a struct AMessage object.  Don't block if the
+		// queue is already full.
+		pxMessage = & xMessage;
+		xQueueGenericSend( xQueue2, ( void * ) &pxMessage, ( TickType_t ) 0, queueSEND_TO_BACK );
+	}
+
+	// ... Rest of task code.
+ }
+ </pre>
+ * \defgroup xQueueSend xQueueSend
+ * \ingroup QueueManagement
+ */
+BaseType_t xQueueGenericSend( QueueHandle_t xQueue, const void * const pvItemToQueue, TickType_t xTicksToWait, const BaseType_t xCopyPosition ) PRIVILEGED_FUNCTION;
+
+/**
+ * queue. h
+ * <pre>
+ BaseType_t xQueuePeek(
+							 QueueHandle_t xQueue,
+							 void * const pvBuffer,
+							 TickType_t xTicksToWait
+						 );</pre>
+ *
+ * Receive an item from a queue without removing the item from the queue.
+ * The item is received by copy so a buffer of adequate size must be
+ * provided.  The number of bytes copied into the buffer was defined when
+ * the queue was created.
+ *
+ * Successfully received items remain on the queue so will be returned again
+ * by the next call, or a call to xQueueReceive().
+ *
+ * This macro must not be used in an interrupt service routine.  See
+ * xQueuePeekFromISR() for an alternative that can be called from an interrupt
+ * service routine.
+ *
+ * @param xQueue The handle to the queue from which the item is to be
+ * received.
+ *
+ * @param pvBuffer Pointer to the buffer into which the received item will
+ * be copied.
+ *
+ * @param xTicksToWait The maximum amount of time the task should block
+ * waiting for an item to receive should the queue be empty at the time
+ * of the call.	 The time is defined in tick periods so the constant
+ * portTICK_PERIOD_MS should be used to convert to real time if this is required.
+ * xQueuePeek() will return immediately if xTicksToWait is 0 and the queue
+ * is empty.
+ *
+ * @return pdTRUE if an item was successfully received from the queue,
+ * otherwise pdFALSE.
+ *
+ * Example usage:
+   <pre>
+ struct AMessage
+ {
+	char ucMessageID;
+	char ucData[ 20 ];
+ } xMessage;
+
+ QueueHandle_t xQueue;
+
+ // Task to create a queue and post a value.
+ void vATask( void *pvParameters )
+ {
+ struct AMessage *pxMessage;
+
+	// Create a queue capable of containing 10 pointers to AMessage structures.
+	// These should be passed by pointer as they contain a lot of data.
+	xQueue = xQueueCreate( 10, sizeof( struct AMessage * ) );
+	if( xQueue == 0 )
+	{
+		// Failed to create the queue.
+	}
+
+	// ...
+
+	// Send a pointer to a struct AMessage object.  Don't block if the
+	// queue is already full.
+	pxMessage = & xMessage;
+	xQueueSend( xQueue, ( void * ) &pxMessage, ( TickType_t ) 0 );
+
+	// ... Rest of task code.
+ }
+
+ // Task to peek the data from the queue.
+ void vADifferentTask( void *pvParameters )
+ {
+ struct AMessage *pxRxedMessage;
+
+	if( xQueue != 0 )
+	{
+		// Peek a message on the created queue.  Block for 10 ticks if a
+		// message is not immediately available.
+		if( xQueuePeek( xQueue, &( pxRxedMessage ), ( TickType_t ) 10 ) )
+		{
+			// pcRxedMessage now points to the struct AMessage variable posted
+			// by vATask, but the item still remains on the queue.
+		}
+	}
+
+	// ... Rest of task code.
+ }
+ </pre>
+ * \defgroup xQueuePeek xQueuePeek
+ * \ingroup QueueManagement
+ */
+BaseType_t xQueuePeek( QueueHandle_t xQueue, void * const pvBuffer, TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+
+/**
+ * queue. h
+ * <pre>
+ BaseType_t xQueuePeekFromISR(
+									QueueHandle_t xQueue,
+									void *pvBuffer,
+								);</pre>
+ *
+ * A version of xQueuePeek() that can be called from an interrupt service
+ * routine (ISR).
+ *
+ * Receive an item from a queue without removing the item from the queue.
+ * The item is received by copy so a buffer of adequate size must be
+ * provided.  The number of bytes copied into the buffer was defined when
+ * the queue was created.
+ *
+ * Successfully received items remain on the queue so will be returned again
+ * by the next call, or a call to xQueueReceive().
+ *
+ * @param xQueue The handle to the queue from which the item is to be
+ * received.
+ *
+ * @param pvBuffer Pointer to the buffer into which the received item will
+ * be copied.
+ *
+ * @return pdTRUE if an item was successfully received from the queue,
+ * otherwise pdFALSE.
+ *
+ * \defgroup xQueuePeekFromISR xQueuePeekFromISR
+ * \ingroup QueueManagement
+ */
+BaseType_t xQueuePeekFromISR( QueueHandle_t xQueue, void * const pvBuffer ) PRIVILEGED_FUNCTION;
+
+/**
+ * queue. h
+ * <pre>
+ BaseType_t xQueueReceive(
+								 QueueHandle_t xQueue,
+								 void *pvBuffer,
+								 TickType_t xTicksToWait
+							);</pre>
+ *
+ * Receive an item from a queue.  The item is received by copy so a buffer of
+ * adequate size must be provided.  The number of bytes copied into the buffer
+ * was defined when the queue was created.
+ *
+ * Successfully received items are removed from the queue.
+ *
+ * This function must not be used in an interrupt service routine.  See
+ * xQueueReceiveFromISR for an alternative that can.
+ *
+ * @param xQueue The handle to the queue from which the item is to be
+ * received.
+ *
+ * @param pvBuffer Pointer to the buffer into which the received item will
+ * be copied.
+ *
+ * @param xTicksToWait The maximum amount of time the task should block
+ * waiting for an item to receive should the queue be empty at the time
+ * of the call.	 xQueueReceive() will return immediately if xTicksToWait
+ * is zero and the queue is empty.  The time is defined in tick periods so the
+ * constant portTICK_PERIOD_MS should be used to convert to real time if this is
+ * required.
+ *
+ * @return pdTRUE if an item was successfully received from the queue,
+ * otherwise pdFALSE.
+ *
+ * Example usage:
+   <pre>
+ struct AMessage
+ {
+	char ucMessageID;
+	char ucData[ 20 ];
+ } xMessage;
+
+ QueueHandle_t xQueue;
+
+ // Task to create a queue and post a value.
+ void vATask( void *pvParameters )
+ {
+ struct AMessage *pxMessage;
+
+	// Create a queue capable of containing 10 pointers to AMessage structures.
+	// These should be passed by pointer as they contain a lot of data.
+	xQueue = xQueueCreate( 10, sizeof( struct AMessage * ) );
+	if( xQueue == 0 )
+	{
+		// Failed to create the queue.
+	}
+
+	// ...
+
+	// Send a pointer to a struct AMessage object.  Don't block if the
+	// queue is already full.
+	pxMessage = & xMessage;
+	xQueueSend( xQueue, ( void * ) &pxMessage, ( TickType_t ) 0 );
+
+	// ... Rest of task code.
+ }
+
+ // Task to receive from the queue.
+ void vADifferentTask( void *pvParameters )
+ {
+ struct AMessage *pxRxedMessage;
+
+	if( xQueue != 0 )
+	{
+		// Receive a message on the created queue.  Block for 10 ticks if a
+		// message is not immediately available.
+		if( xQueueReceive( xQueue, &( pxRxedMessage ), ( TickType_t ) 10 ) )
+		{
+			// pcRxedMessage now points to the struct AMessage variable posted
+			// by vATask.
+		}
+	}
+
+	// ... Rest of task code.
+ }
+ </pre>
+ * \defgroup xQueueReceive xQueueReceive
+ * \ingroup QueueManagement
+ */
+BaseType_t xQueueReceive( QueueHandle_t xQueue, void * const pvBuffer, TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+
+/**
+ * queue. h
+ * <pre>UBaseType_t uxQueueMessagesWaiting( const QueueHandle_t xQueue );</pre>
+ *
+ * Return the number of messages stored in a queue.
+ *
+ * @param xQueue A handle to the queue being queried.
+ *
+ * @return The number of messages available in the queue.
+ *
+ * \defgroup uxQueueMessagesWaiting uxQueueMessagesWaiting
+ * \ingroup QueueManagement
+ */
+UBaseType_t uxQueueMessagesWaiting( const QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
+
+/**
+ * queue. h
+ * <pre>UBaseType_t uxQueueSpacesAvailable( const QueueHandle_t xQueue );</pre>
+ *
+ * Return the number of free spaces available in a queue.  This is equal to the
+ * number of items that can be sent to the queue before the queue becomes full
+ * if no items are removed.
+ *
+ * @param xQueue A handle to the queue being queried.
+ *
+ * @return The number of spaces available in the queue.
+ *
+ * \defgroup uxQueueMessagesWaiting uxQueueMessagesWaiting
+ * \ingroup QueueManagement
+ */
+UBaseType_t uxQueueSpacesAvailable( const QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
+
+/**
+ * queue. h
+ * <pre>void vQueueDelete( QueueHandle_t xQueue );</pre>
+ *
+ * Delete a queue - freeing all the memory allocated for storing of items
+ * placed on the queue.
+ *
+ * @param xQueue A handle to the queue to be deleted.
+ *
+ * \defgroup vQueueDelete vQueueDelete
+ * \ingroup QueueManagement
+ */
+void vQueueDelete( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
+
+/**
+ * queue. h
+ * <pre>
+ BaseType_t xQueueSendToFrontFromISR(
+										 QueueHandle_t xQueue,
+										 const void *pvItemToQueue,
+										 BaseType_t *pxHigherPriorityTaskWoken
+									  );
+ </pre>
+ *
+ * This is a macro that calls xQueueGenericSendFromISR().
+ *
+ * Post an item to the front of a queue.  It is safe to use this macro from
+ * within an interrupt service routine.
+ *
+ * Items are queued by copy not reference so it is preferable to only
+ * queue small items, especially when called from an ISR.  In most cases
+ * it would be preferable to store a pointer to the item being queued.
+ *
+ * @param xQueue The handle to the queue on which the item is to be posted.
+ *
+ * @param pvItemToQueue A pointer to the item that is to be placed on the
+ * queue.  The size of the items the queue will hold was defined when the
+ * queue was created, so this many bytes will be copied from pvItemToQueue
+ * into the queue storage area.
+ *
+ * @param pxHigherPriorityTaskWoken xQueueSendToFrontFromISR() will set
+ * *pxHigherPriorityTaskWoken to pdTRUE if sending to the queue caused a task
+ * to unblock, and the unblocked task has a priority higher than the currently
+ * running task.  If xQueueSendToFromFromISR() sets this value to pdTRUE then
+ * a context switch should be requested before the interrupt is exited.
+ *
+ * @return pdTRUE if the data was successfully sent to the queue, otherwise
+ * errQUEUE_FULL.
+ *
+ * Example usage for buffered IO (where the ISR can obtain more than one value
+ * per call):
+   <pre>
+ void vBufferISR( void )
+ {
+ char cIn;
+ BaseType_t xHigherPrioritTaskWoken;
+
+	// We have not woken a task at the start of the ISR.
+	xHigherPriorityTaskWoken = pdFALSE;
+
+	// Loop until the buffer is empty.
+	do
+	{
+		// Obtain a byte from the buffer.
+		cIn = portINPUT_BYTE( RX_REGISTER_ADDRESS );
+
+		// Post the byte.
+		xQueueSendToFrontFromISR( xRxQueue, &cIn, &xHigherPriorityTaskWoken );
+
+	} while( portINPUT_BYTE( BUFFER_COUNT ) );
+
+	// Now the buffer is empty we can switch context if necessary.
+	if( xHigherPriorityTaskWoken )
+	{
+		taskYIELD ();
+	}
+ }
+ </pre>
+ *
+ * \defgroup xQueueSendFromISR xQueueSendFromISR
+ * \ingroup QueueManagement
+ */
+#define xQueueSendToFrontFromISR( xQueue, pvItemToQueue, pxHigherPriorityTaskWoken ) xQueueGenericSendFromISR( ( xQueue ), ( pvItemToQueue ), ( pxHigherPriorityTaskWoken ), queueSEND_TO_FRONT )
+
+
+/**
+ * queue. h
+ * <pre>
+ BaseType_t xQueueSendToBackFromISR(
+										 QueueHandle_t xQueue,
+										 const void *pvItemToQueue,
+										 BaseType_t *pxHigherPriorityTaskWoken
+									  );
+ </pre>
+ *
+ * This is a macro that calls xQueueGenericSendFromISR().
+ *
+ * Post an item to the back of a queue.  It is safe to use this macro from
+ * within an interrupt service routine.
+ *
+ * Items are queued by copy not reference so it is preferable to only
+ * queue small items, especially when called from an ISR.  In most cases
+ * it would be preferable to store a pointer to the item being queued.
+ *
+ * @param xQueue The handle to the queue on which the item is to be posted.
+ *
+ * @param pvItemToQueue A pointer to the item that is to be placed on the
+ * queue.  The size of the items the queue will hold was defined when the
+ * queue was created, so this many bytes will be copied from pvItemToQueue
+ * into the queue storage area.
+ *
+ * @param pxHigherPriorityTaskWoken xQueueSendToBackFromISR() will set
+ * *pxHigherPriorityTaskWoken to pdTRUE if sending to the queue caused a task
+ * to unblock, and the unblocked task has a priority higher than the currently
+ * running task.  If xQueueSendToBackFromISR() sets this value to pdTRUE then
+ * a context switch should be requested before the interrupt is exited.
+ *
+ * @return pdTRUE if the data was successfully sent to the queue, otherwise
+ * errQUEUE_FULL.
+ *
+ * Example usage for buffered IO (where the ISR can obtain more than one value
+ * per call):
+   <pre>
+ void vBufferISR( void )
+ {
+ char cIn;
+ BaseType_t xHigherPriorityTaskWoken;
+
+	// We have not woken a task at the start of the ISR.
+	xHigherPriorityTaskWoken = pdFALSE;
+
+	// Loop until the buffer is empty.
+	do
+	{
+		// Obtain a byte from the buffer.
+		cIn = portINPUT_BYTE( RX_REGISTER_ADDRESS );
+
+		// Post the byte.
+		xQueueSendToBackFromISR( xRxQueue, &cIn, &xHigherPriorityTaskWoken );
+
+	} while( portINPUT_BYTE( BUFFER_COUNT ) );
+
+	// Now the buffer is empty we can switch context if necessary.
+	if( xHigherPriorityTaskWoken )
+	{
+		taskYIELD ();
+	}
+ }
+ </pre>
+ *
+ * \defgroup xQueueSendFromISR xQueueSendFromISR
+ * \ingroup QueueManagement
+ */
+#define xQueueSendToBackFromISR( xQueue, pvItemToQueue, pxHigherPriorityTaskWoken ) xQueueGenericSendFromISR( ( xQueue ), ( pvItemToQueue ), ( pxHigherPriorityTaskWoken ), queueSEND_TO_BACK )
+
+/**
+ * queue. h
+ * <pre>
+ BaseType_t xQueueOverwriteFromISR(
+							  QueueHandle_t xQueue,
+							  const void * pvItemToQueue,
+							  BaseType_t *pxHigherPriorityTaskWoken
+						 );
+ * </pre>
+ *
+ * A version of xQueueOverwrite() that can be used in an interrupt service
+ * routine (ISR).
+ *
+ * Only for use with queues that can hold a single item - so the queue is either
+ * empty or full.
+ *
+ * Post an item on a queue.  If the queue is already full then overwrite the
+ * value held in the queue.  The item is queued by copy, not by reference.
+ *
+ * @param xQueue The handle to the queue on which the item is to be posted.
+ *
+ * @param pvItemToQueue A pointer to the item that is to be placed on the
+ * queue.  The size of the items the queue will hold was defined when the
+ * queue was created, so this many bytes will be copied from pvItemToQueue
+ * into the queue storage area.
+ *
+ * @param pxHigherPriorityTaskWoken xQueueOverwriteFromISR() will set
+ * *pxHigherPriorityTaskWoken to pdTRUE if sending to the queue caused a task
+ * to unblock, and the unblocked task has a priority higher than the currently
+ * running task.  If xQueueOverwriteFromISR() sets this value to pdTRUE then
+ * a context switch should be requested before the interrupt is exited.
+ *
+ * @return xQueueOverwriteFromISR() is a macro that calls
+ * xQueueGenericSendFromISR(), and therefore has the same return values as
+ * xQueueSendToFrontFromISR().  However, pdPASS is the only value that can be
+ * returned because xQueueOverwriteFromISR() will write to the queue even when
+ * the queue is already full.
+ *
+ * Example usage:
+   <pre>
+
+ QueueHandle_t xQueue;
+
+ void vFunction( void *pvParameters )
+ {
+ 	// Create a queue to hold one uint32_t value.  It is strongly
+	// recommended *not* to use xQueueOverwriteFromISR() on queues that can
+	// contain more than one value, and doing so will trigger an assertion
+	// if configASSERT() is defined.
+	xQueue = xQueueCreate( 1, sizeof( uint32_t ) );
+}
+
+void vAnInterruptHandler( void )
+{
+// xHigherPriorityTaskWoken must be set to pdFALSE before it is used.
+BaseType_t xHigherPriorityTaskWoken = pdFALSE;
+uint32_t ulVarToSend, ulValReceived;
+
+	// Write the value 10 to the queue using xQueueOverwriteFromISR().
+	ulVarToSend = 10;
+	xQueueOverwriteFromISR( xQueue, &ulVarToSend, &xHigherPriorityTaskWoken );
+
+	// The queue is full, but calling xQueueOverwriteFromISR() again will still
+	// pass because the value held in the queue will be overwritten with the
+	// new value.
+	ulVarToSend = 100;
+	xQueueOverwriteFromISR( xQueue, &ulVarToSend, &xHigherPriorityTaskWoken );
+
+	// Reading from the queue will now return 100.
+
+	// ...
+
+	if( xHigherPrioritytaskWoken == pdTRUE )
+	{
+		// Writing to the queue caused a task to unblock and the unblocked task
+		// has a priority higher than or equal to the priority of the currently
+		// executing task (the task this interrupt interrupted).  Perform a context
+		// switch so this interrupt returns directly to the unblocked task.
+		portYIELD_FROM_ISR(); // or portEND_SWITCHING_ISR() depending on the port.
+	}
+}
+ </pre>
+ * \defgroup xQueueOverwriteFromISR xQueueOverwriteFromISR
+ * \ingroup QueueManagement
+ */
+#define xQueueOverwriteFromISR( xQueue, pvItemToQueue, pxHigherPriorityTaskWoken ) xQueueGenericSendFromISR( ( xQueue ), ( pvItemToQueue ), ( pxHigherPriorityTaskWoken ), queueOVERWRITE )
+
+/**
+ * queue. h
+ * <pre>
+ BaseType_t xQueueSendFromISR(
+									 QueueHandle_t xQueue,
+									 const void *pvItemToQueue,
+									 BaseType_t *pxHigherPriorityTaskWoken
+								);
+ </pre>
+ *
+ * This is a macro that calls xQueueGenericSendFromISR().  It is included
+ * for backward compatibility with versions of FreeRTOS.org that did not
+ * include the xQueueSendToBackFromISR() and xQueueSendToFrontFromISR()
+ * macros.
+ *
+ * Post an item to the back of a queue.  It is safe to use this function from
+ * within an interrupt service routine.
+ *
+ * Items are queued by copy not reference so it is preferable to only
+ * queue small items, especially when called from an ISR.  In most cases
+ * it would be preferable to store a pointer to the item being queued.
+ *
+ * @param xQueue The handle to the queue on which the item is to be posted.
+ *
+ * @param pvItemToQueue A pointer to the item that is to be placed on the
+ * queue.  The size of the items the queue will hold was defined when the
+ * queue was created, so this many bytes will be copied from pvItemToQueue
+ * into the queue storage area.
+ *
+ * @param pxHigherPriorityTaskWoken xQueueSendFromISR() will set
+ * *pxHigherPriorityTaskWoken to pdTRUE if sending to the queue caused a task
+ * to unblock, and the unblocked task has a priority higher than the currently
+ * running task.  If xQueueSendFromISR() sets this value to pdTRUE then
+ * a context switch should be requested before the interrupt is exited.
+ *
+ * @return pdTRUE if the data was successfully sent to the queue, otherwise
+ * errQUEUE_FULL.
+ *
+ * Example usage for buffered IO (where the ISR can obtain more than one value
+ * per call):
+   <pre>
+ void vBufferISR( void )
+ {
+ char cIn;
+ BaseType_t xHigherPriorityTaskWoken;
+
+	// We have not woken a task at the start of the ISR.
+	xHigherPriorityTaskWoken = pdFALSE;
+
+	// Loop until the buffer is empty.
+	do
+	{
+		// Obtain a byte from the buffer.
+		cIn = portINPUT_BYTE( RX_REGISTER_ADDRESS );
+
+		// Post the byte.
+		xQueueSendFromISR( xRxQueue, &cIn, &xHigherPriorityTaskWoken );
+
+	} while( portINPUT_BYTE( BUFFER_COUNT ) );
+
+	// Now the buffer is empty we can switch context if necessary.
+	if( xHigherPriorityTaskWoken )
+	{
+		// Actual macro used here is port specific.
+		portYIELD_FROM_ISR ();
+	}
+ }
+ </pre>
+ *
+ * \defgroup xQueueSendFromISR xQueueSendFromISR
+ * \ingroup QueueManagement
+ */
+#define xQueueSendFromISR( xQueue, pvItemToQueue, pxHigherPriorityTaskWoken ) xQueueGenericSendFromISR( ( xQueue ), ( pvItemToQueue ), ( pxHigherPriorityTaskWoken ), queueSEND_TO_BACK )
+
+/**
+ * queue. h
+ * <pre>
+ BaseType_t xQueueGenericSendFromISR(
+										   QueueHandle_t		xQueue,
+										   const	void	*pvItemToQueue,
+										   BaseType_t	*pxHigherPriorityTaskWoken,
+										   BaseType_t	xCopyPosition
+									   );
+ </pre>
+ *
+ * It is preferred that the macros xQueueSendFromISR(),
+ * xQueueSendToFrontFromISR() and xQueueSendToBackFromISR() be used in place
+ * of calling this function directly.  xQueueGiveFromISR() is an
+ * equivalent for use by semaphores that don't actually copy any data.
+ *
+ * Post an item on a queue.  It is safe to use this function from within an
+ * interrupt service routine.
+ *
+ * Items are queued by copy not reference so it is preferable to only
+ * queue small items, especially when called from an ISR.  In most cases
+ * it would be preferable to store a pointer to the item being queued.
+ *
+ * @param xQueue The handle to the queue on which the item is to be posted.
+ *
+ * @param pvItemToQueue A pointer to the item that is to be placed on the
+ * queue.  The size of the items the queue will hold was defined when the
+ * queue was created, so this many bytes will be copied from pvItemToQueue
+ * into the queue storage area.
+ *
+ * @param pxHigherPriorityTaskWoken xQueueGenericSendFromISR() will set
+ * *pxHigherPriorityTaskWoken to pdTRUE if sending to the queue caused a task
+ * to unblock, and the unblocked task has a priority higher than the currently
+ * running task.  If xQueueGenericSendFromISR() sets this value to pdTRUE then
+ * a context switch should be requested before the interrupt is exited.
+ *
+ * @param xCopyPosition Can take the value queueSEND_TO_BACK to place the
+ * item at the back of the queue, or queueSEND_TO_FRONT to place the item
+ * at the front of the queue (for high priority messages).
+ *
+ * @return pdTRUE if the data was successfully sent to the queue, otherwise
+ * errQUEUE_FULL.
+ *
+ * Example usage for buffered IO (where the ISR can obtain more than one value
+ * per call):
+   <pre>
+ void vBufferISR( void )
+ {
+ char cIn;
+ BaseType_t xHigherPriorityTaskWokenByPost;
+
+	// We have not woken a task at the start of the ISR.
+	xHigherPriorityTaskWokenByPost = pdFALSE;
+
+	// Loop until the buffer is empty.
+	do
+	{
+		// Obtain a byte from the buffer.
+		cIn = portINPUT_BYTE( RX_REGISTER_ADDRESS );
+
+		// Post each byte.
+		xQueueGenericSendFromISR( xRxQueue, &cIn, &xHigherPriorityTaskWokenByPost, queueSEND_TO_BACK );
+
+	} while( portINPUT_BYTE( BUFFER_COUNT ) );
+
+	// Now the buffer is empty we can switch context if necessary.  Note that the
+	// name of the yield function required is port specific.
+	if( xHigherPriorityTaskWokenByPost )
+	{
+		portYIELD_FROM_ISR();
+	}
+ }
+ </pre>
+ *
+ * \defgroup xQueueSendFromISR xQueueSendFromISR
+ * \ingroup QueueManagement
+ */
+BaseType_t xQueueGenericSendFromISR( QueueHandle_t xQueue, const void * const pvItemToQueue, BaseType_t * const pxHigherPriorityTaskWoken, const BaseType_t xCopyPosition ) PRIVILEGED_FUNCTION;
+BaseType_t xQueueGiveFromISR( QueueHandle_t xQueue, BaseType_t * const pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;
+
+/**
+ * queue. h
+ * <pre>
+ BaseType_t xQueueReceiveFromISR(
+									   QueueHandle_t	xQueue,
+									   void	*pvBuffer,
+									   BaseType_t *pxTaskWoken
+								   );
+ * </pre>
+ *
+ * Receive an item from a queue.  It is safe to use this function from within an
+ * interrupt service routine.
+ *
+ * @param xQueue The handle to the queue from which the item is to be
+ * received.
+ *
+ * @param pvBuffer Pointer to the buffer into which the received item will
+ * be copied.
+ *
+ * @param pxTaskWoken A task may be blocked waiting for space to become
+ * available on the queue.  If xQueueReceiveFromISR causes such a task to
+ * unblock *pxTaskWoken will get set to pdTRUE, otherwise *pxTaskWoken will
+ * remain unchanged.
+ *
+ * @return pdTRUE if an item was successfully received from the queue,
+ * otherwise pdFALSE.
+ *
+ * Example usage:
+   <pre>
+
+ QueueHandle_t xQueue;
+
+ // Function to create a queue and post some values.
+ void vAFunction( void *pvParameters )
+ {
+ char cValueToPost;
+ const TickType_t xTicksToWait = ( TickType_t )0xff;
+
+	// Create a queue capable of containing 10 characters.
+	xQueue = xQueueCreate( 10, sizeof( char ) );
+	if( xQueue == 0 )
+	{
+		// Failed to create the queue.
+	}
+
+	// ...
+
+	// Post some characters that will be used within an ISR.  If the queue
+	// is full then this task will block for xTicksToWait ticks.
+	cValueToPost = 'a';
+	xQueueSend( xQueue, ( void * ) &cValueToPost, xTicksToWait );
+	cValueToPost = 'b';
+	xQueueSend( xQueue, ( void * ) &cValueToPost, xTicksToWait );
+
+	// ... keep posting characters ... this task may block when the queue
+	// becomes full.
+
+	cValueToPost = 'c';
+	xQueueSend( xQueue, ( void * ) &cValueToPost, xTicksToWait );
+ }
+
+ // ISR that outputs all the characters received on the queue.
+ void vISR_Routine( void )
+ {
+ BaseType_t xTaskWokenByReceive = pdFALSE;
+ char cRxedChar;
+
+	while( xQueueReceiveFromISR( xQueue, ( void * ) &cRxedChar, &xTaskWokenByReceive) )
+	{
+		// A character was received.  Output the character now.
+		vOutputCharacter( cRxedChar );
+
+		// If removing the character from the queue woke the task that was
+		// posting onto the queue cTaskWokenByReceive will have been set to
+		// pdTRUE.  No matter how many times this loop iterates only one
+		// task will be woken.
+	}
+
+	if( cTaskWokenByPost != ( char ) pdFALSE;
+	{
+		taskYIELD ();
+	}
+ }
+ </pre>
+ * \defgroup xQueueReceiveFromISR xQueueReceiveFromISR
+ * \ingroup QueueManagement
+ */
+BaseType_t xQueueReceiveFromISR( QueueHandle_t xQueue, void * const pvBuffer, BaseType_t * const pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;
+
+/*
+ * Utilities to query queues that are safe to use from an ISR.  These utilities
+ * should be used only from witin an ISR, or within a critical section.
+ */
+BaseType_t xQueueIsQueueEmptyFromISR( const QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
+BaseType_t xQueueIsQueueFullFromISR( const QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
+UBaseType_t uxQueueMessagesWaitingFromISR( const QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
+
+/*
+ * The functions defined above are for passing data to and from tasks.  The
+ * functions below are the equivalents for passing data to and from
+ * co-routines.
+ *
+ * These functions are called from the co-routine macro implementation and
+ * should not be called directly from application code.  Instead use the macro
+ * wrappers defined within croutine.h.
+ */
+BaseType_t xQueueCRSendFromISR( QueueHandle_t xQueue, const void *pvItemToQueue, BaseType_t xCoRoutinePreviouslyWoken );
+BaseType_t xQueueCRReceiveFromISR( QueueHandle_t xQueue, void *pvBuffer, BaseType_t *pxTaskWoken );
+BaseType_t xQueueCRSend( QueueHandle_t xQueue, const void *pvItemToQueue, TickType_t xTicksToWait );
+BaseType_t xQueueCRReceive( QueueHandle_t xQueue, void *pvBuffer, TickType_t xTicksToWait );
+
+/*
+ * For internal use only.  Use xSemaphoreCreateMutex(),
+ * xSemaphoreCreateCounting() or xSemaphoreGetMutexHolder() instead of calling
+ * these functions directly.
+ */
+QueueHandle_t xQueueCreateMutex( const uint8_t ucQueueType ) PRIVILEGED_FUNCTION;
+QueueHandle_t xQueueCreateMutexStatic( const uint8_t ucQueueType, StaticQueue_t *pxStaticQueue ) PRIVILEGED_FUNCTION;
+QueueHandle_t xQueueCreateCountingSemaphore( const UBaseType_t uxMaxCount, const UBaseType_t uxInitialCount ) PRIVILEGED_FUNCTION;
+QueueHandle_t xQueueCreateCountingSemaphoreStatic( const UBaseType_t uxMaxCount, const UBaseType_t uxInitialCount, StaticQueue_t *pxStaticQueue ) PRIVILEGED_FUNCTION;
+BaseType_t xQueueSemaphoreTake( QueueHandle_t xQueue, TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+TaskHandle_t xQueueGetMutexHolder( QueueHandle_t xSemaphore ) PRIVILEGED_FUNCTION;
+TaskHandle_t xQueueGetMutexHolderFromISR( QueueHandle_t xSemaphore ) PRIVILEGED_FUNCTION;
+
+/*
+ * For internal use only.  Use xSemaphoreTakeMutexRecursive() or
+ * xSemaphoreGiveMutexRecursive() instead of calling these functions directly.
+ */
+BaseType_t xQueueTakeMutexRecursive( QueueHandle_t xMutex, TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+BaseType_t xQueueGiveMutexRecursive( QueueHandle_t xMutex ) PRIVILEGED_FUNCTION;
+
+/*
+ * Reset a queue back to its original empty state.  The return value is now
+ * obsolete and is always set to pdPASS.
+ */
+#define xQueueReset( xQueue ) xQueueGenericReset( xQueue, pdFALSE )
+
+/*
+ * The registry is provided as a means for kernel aware debuggers to
+ * locate queues, semaphores and mutexes.  Call vQueueAddToRegistry() add
+ * a queue, semaphore or mutex handle to the registry if you want the handle
+ * to be available to a kernel aware debugger.  If you are not using a kernel
+ * aware debugger then this function can be ignored.
+ *
+ * configQUEUE_REGISTRY_SIZE defines the maximum number of handles the
+ * registry can hold.  configQUEUE_REGISTRY_SIZE must be greater than 0
+ * within FreeRTOSConfig.h for the registry to be available.  Its value
+ * does not effect the number of queues, semaphores and mutexes that can be
+ * created - just the number that the registry can hold.
+ *
+ * @param xQueue The handle of the queue being added to the registry.  This
+ * is the handle returned by a call to xQueueCreate().  Semaphore and mutex
+ * handles can also be passed in here.
+ *
+ * @param pcName The name to be associated with the handle.  This is the
+ * name that the kernel aware debugger will display.  The queue registry only
+ * stores a pointer to the string - so the string must be persistent (global or
+ * preferably in ROM/Flash), not on the stack.
+ */
+#if( configQUEUE_REGISTRY_SIZE > 0 )
+	void vQueueAddToRegistry( QueueHandle_t xQueue, const char *pcQueueName ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+#endif
+
+/*
+ * The registry is provided as a means for kernel aware debuggers to
+ * locate queues, semaphores and mutexes.  Call vQueueAddToRegistry() add
+ * a queue, semaphore or mutex handle to the registry if you want the handle
+ * to be available to a kernel aware debugger, and vQueueUnregisterQueue() to
+ * remove the queue, semaphore or mutex from the register.  If you are not using
+ * a kernel aware debugger then this function can be ignored.
+ *
+ * @param xQueue The handle of the queue being removed from the registry.
+ */
+#if( configQUEUE_REGISTRY_SIZE > 0 )
+	void vQueueUnregisterQueue( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
+#endif
+
+/*
+ * The queue registry is provided as a means for kernel aware debuggers to
+ * locate queues, semaphores and mutexes.  Call pcQueueGetName() to look
+ * up and return the name of a queue in the queue registry from the queue's
+ * handle.
+ *
+ * @param xQueue The handle of the queue the name of which will be returned.
+ * @return If the queue is in the registry then a pointer to the name of the
+ * queue is returned.  If the queue is not in the registry then NULL is
+ * returned.
+ */
+#if( configQUEUE_REGISTRY_SIZE > 0 )
+	const char *pcQueueGetName( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+#endif
+
+/*
+ * Generic version of the function used to creaet a queue using dynamic memory
+ * allocation.  This is called by other functions and macros that create other
+ * RTOS objects that use the queue structure as their base.
+ */
+#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+	QueueHandle_t xQueueGenericCreate( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, const uint8_t ucQueueType ) PRIVILEGED_FUNCTION;
+#endif
+
+/*
+ * Generic version of the function used to creaet a queue using dynamic memory
+ * allocation.  This is called by other functions and macros that create other
+ * RTOS objects that use the queue structure as their base.
+ */
+#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+	QueueHandle_t xQueueGenericCreateStatic( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, uint8_t *pucQueueStorage, StaticQueue_t *pxStaticQueue, const uint8_t ucQueueType ) PRIVILEGED_FUNCTION;
+#endif
+
+/*
+ * Queue sets provide a mechanism to allow a task to block (pend) on a read
+ * operation from multiple queues or semaphores simultaneously.
+ *
+ * See FreeRTOS/Source/Demo/Common/Minimal/QueueSet.c for an example using this
+ * function.
+ *
+ * A queue set must be explicitly created using a call to xQueueCreateSet()
+ * before it can be used.  Once created, standard FreeRTOS queues and semaphores
+ * can be added to the set using calls to xQueueAddToSet().
+ * xQueueSelectFromSet() is then used to determine which, if any, of the queues
+ * or semaphores contained in the set is in a state where a queue read or
+ * semaphore take operation would be successful.
+ *
+ * Note 1:  See the documentation on http://wwwFreeRTOS.org/RTOS-queue-sets.html
+ * for reasons why queue sets are very rarely needed in practice as there are
+ * simpler methods of blocking on multiple objects.
+ *
+ * Note 2:  Blocking on a queue set that contains a mutex will not cause the
+ * mutex holder to inherit the priority of the blocked task.
+ *
+ * Note 3:  An additional 4 bytes of RAM is required for each space in a every
+ * queue added to a queue set.  Therefore counting semaphores that have a high
+ * maximum count value should not be added to a queue set.
+ *
+ * Note 4:  A receive (in the case of a queue) or take (in the case of a
+ * semaphore) operation must not be performed on a member of a queue set unless
+ * a call to xQueueSelectFromSet() has first returned a handle to that set member.
+ *
+ * @param uxEventQueueLength Queue sets store events that occur on
+ * the queues and semaphores contained in the set.  uxEventQueueLength specifies
+ * the maximum number of events that can be queued at once.  To be absolutely
+ * certain that events are not lost uxEventQueueLength should be set to the
+ * total sum of the length of the queues added to the set, where binary
+ * semaphores and mutexes have a length of 1, and counting semaphores have a
+ * length set by their maximum count value.  Examples:
+ *  + If a queue set is to hold a queue of length 5, another queue of length 12,
+ *    and a binary semaphore, then uxEventQueueLength should be set to
+ *    (5 + 12 + 1), or 18.
+ *  + If a queue set is to hold three binary semaphores then uxEventQueueLength
+ *    should be set to (1 + 1 + 1 ), or 3.
+ *  + If a queue set is to hold a counting semaphore that has a maximum count of
+ *    5, and a counting semaphore that has a maximum count of 3, then
+ *    uxEventQueueLength should be set to (5 + 3), or 8.
+ *
+ * @return If the queue set is created successfully then a handle to the created
+ * queue set is returned.  Otherwise NULL is returned.
+ */
+QueueSetHandle_t xQueueCreateSet( const UBaseType_t uxEventQueueLength ) PRIVILEGED_FUNCTION;
+
+/*
+ * Adds a queue or semaphore to a queue set that was previously created by a
+ * call to xQueueCreateSet().
+ *
+ * See FreeRTOS/Source/Demo/Common/Minimal/QueueSet.c for an example using this
+ * function.
+ *
+ * Note 1:  A receive (in the case of a queue) or take (in the case of a
+ * semaphore) operation must not be performed on a member of a queue set unless
+ * a call to xQueueSelectFromSet() has first returned a handle to that set member.
+ *
+ * @param xQueueOrSemaphore The handle of the queue or semaphore being added to
+ * the queue set (cast to an QueueSetMemberHandle_t type).
+ *
+ * @param xQueueSet The handle of the queue set to which the queue or semaphore
+ * is being added.
+ *
+ * @return If the queue or semaphore was successfully added to the queue set
+ * then pdPASS is returned.  If the queue could not be successfully added to the
+ * queue set because it is already a member of a different queue set then pdFAIL
+ * is returned.
+ */
+BaseType_t xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore, QueueSetHandle_t xQueueSet ) PRIVILEGED_FUNCTION;
+
+/*
+ * Removes a queue or semaphore from a queue set.  A queue or semaphore can only
+ * be removed from a set if the queue or semaphore is empty.
+ *
+ * See FreeRTOS/Source/Demo/Common/Minimal/QueueSet.c for an example using this
+ * function.
+ *
+ * @param xQueueOrSemaphore The handle of the queue or semaphore being removed
+ * from the queue set (cast to an QueueSetMemberHandle_t type).
+ *
+ * @param xQueueSet The handle of the queue set in which the queue or semaphore
+ * is included.
+ *
+ * @return If the queue or semaphore was successfully removed from the queue set
+ * then pdPASS is returned.  If the queue was not in the queue set, or the
+ * queue (or semaphore) was not empty, then pdFAIL is returned.
+ */
+BaseType_t xQueueRemoveFromSet( QueueSetMemberHandle_t xQueueOrSemaphore, QueueSetHandle_t xQueueSet ) PRIVILEGED_FUNCTION;
+
+/*
+ * xQueueSelectFromSet() selects from the members of a queue set a queue or
+ * semaphore that either contains data (in the case of a queue) or is available
+ * to take (in the case of a semaphore).  xQueueSelectFromSet() effectively
+ * allows a task to block (pend) on a read operation on all the queues and
+ * semaphores in a queue set simultaneously.
+ *
+ * See FreeRTOS/Source/Demo/Common/Minimal/QueueSet.c for an example using this
+ * function.
+ *
+ * Note 1:  See the documentation on http://wwwFreeRTOS.org/RTOS-queue-sets.html
+ * for reasons why queue sets are very rarely needed in practice as there are
+ * simpler methods of blocking on multiple objects.
+ *
+ * Note 2:  Blocking on a queue set that contains a mutex will not cause the
+ * mutex holder to inherit the priority of the blocked task.
+ *
+ * Note 3:  A receive (in the case of a queue) or take (in the case of a
+ * semaphore) operation must not be performed on a member of a queue set unless
+ * a call to xQueueSelectFromSet() has first returned a handle to that set member.
+ *
+ * @param xQueueSet The queue set on which the task will (potentially) block.
+ *
+ * @param xTicksToWait The maximum time, in ticks, that the calling task will
+ * remain in the Blocked state (with other tasks executing) to wait for a member
+ * of the queue set to be ready for a successful queue read or semaphore take
+ * operation.
+ *
+ * @return xQueueSelectFromSet() will return the handle of a queue (cast to
+ * a QueueSetMemberHandle_t type) contained in the queue set that contains data,
+ * or the handle of a semaphore (cast to a QueueSetMemberHandle_t type) contained
+ * in the queue set that is available, or NULL if no such queue or semaphore
+ * exists before before the specified block time expires.
+ */
+QueueSetMemberHandle_t xQueueSelectFromSet( QueueSetHandle_t xQueueSet, const TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+
+/*
+ * A version of xQueueSelectFromSet() that can be used from an ISR.
+ */
+QueueSetMemberHandle_t xQueueSelectFromSetFromISR( QueueSetHandle_t xQueueSet ) PRIVILEGED_FUNCTION;
+
+/* Not public API functions. */
+void vQueueWaitForMessageRestricted( QueueHandle_t xQueue, TickType_t xTicksToWait, const BaseType_t xWaitIndefinitely ) PRIVILEGED_FUNCTION;
+BaseType_t xQueueGenericReset( QueueHandle_t xQueue, BaseType_t xNewQueue ) PRIVILEGED_FUNCTION;
+void vQueueSetQueueNumber( QueueHandle_t xQueue, UBaseType_t uxQueueNumber ) PRIVILEGED_FUNCTION;
+UBaseType_t uxQueueGetQueueNumber( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
+uint8_t ucQueueGetQueueType( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* QUEUE_H */
+
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/include/semphr.h b/Middlewares/Third_Party/FreeRTOS/Source/include/semphr.h
new file mode 100644
index 0000000..ff21a39
--- /dev/null
+++ b/Middlewares/Third_Party/FreeRTOS/Source/include/semphr.h
@@ -0,0 +1,1140 @@
+/*
+ * FreeRTOS Kernel V10.3.1
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef SEMAPHORE_H
+#define SEMAPHORE_H
+
+#ifndef INC_FREERTOS_H
+	#error "include FreeRTOS.h" must appear in source files before "include semphr.h"
+#endif
+
+#include "queue.h"
+
+typedef QueueHandle_t SemaphoreHandle_t;
+
+#define semBINARY_SEMAPHORE_QUEUE_LENGTH	( ( uint8_t ) 1U )
+#define semSEMAPHORE_QUEUE_ITEM_LENGTH		( ( uint8_t ) 0U )
+#define semGIVE_BLOCK_TIME					( ( TickType_t ) 0U )
+
+
+/**
+ * semphr. h
+ * <pre>vSemaphoreCreateBinary( SemaphoreHandle_t xSemaphore )</pre>
+ *
+ * In many usage scenarios it is faster and more memory efficient to use a
+ * direct to task notification in place of a binary semaphore!
+ * http://www.freertos.org/RTOS-task-notifications.html
+ *
+ * This old vSemaphoreCreateBinary() macro is now deprecated in favour of the
+ * xSemaphoreCreateBinary() function.  Note that binary semaphores created using
+ * the vSemaphoreCreateBinary() macro are created in a state such that the
+ * first call to 'take' the semaphore would pass, whereas binary semaphores
+ * created using xSemaphoreCreateBinary() are created in a state such that the
+ * the semaphore must first be 'given' before it can be 'taken'.
+ *
+ * <i>Macro</i> that implements a semaphore by using the existing queue mechanism.
+ * The queue length is 1 as this is a binary semaphore.  The data size is 0
+ * as we don't want to actually store any data - we just want to know if the
+ * queue is empty or full.
+ *
+ * This type of semaphore can be used for pure synchronisation between tasks or
+ * between an interrupt and a task.  The semaphore need not be given back once
+ * obtained, so one task/interrupt can continuously 'give' the semaphore while
+ * another continuously 'takes' the semaphore.  For this reason this type of
+ * semaphore does not use a priority inheritance mechanism.  For an alternative
+ * that does use priority inheritance see xSemaphoreCreateMutex().
+ *
+ * @param xSemaphore Handle to the created semaphore.  Should be of type SemaphoreHandle_t.
+ *
+ * Example usage:
+ <pre>
+ SemaphoreHandle_t xSemaphore = NULL;
+
+ void vATask( void * pvParameters )
+ {
+    // Semaphore cannot be used before a call to vSemaphoreCreateBinary ().
+    // This is a macro so pass the variable in directly.
+    vSemaphoreCreateBinary( xSemaphore );
+
+    if( xSemaphore != NULL )
+    {
+        // The semaphore was created successfully.
+        // The semaphore can now be used.
+    }
+ }
+ </pre>
+ * \defgroup vSemaphoreCreateBinary vSemaphoreCreateBinary
+ * \ingroup Semaphores
+ */
+#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+	#define vSemaphoreCreateBinary( xSemaphore )																							\
+		{																																	\
+			( xSemaphore ) = xQueueGenericCreate( ( UBaseType_t ) 1, semSEMAPHORE_QUEUE_ITEM_LENGTH, queueQUEUE_TYPE_BINARY_SEMAPHORE );	\
+			if( ( xSemaphore ) != NULL )																									\
+			{																																\
+				( void ) xSemaphoreGive( ( xSemaphore ) );																					\
+			}																																\
+		}
+#endif
+
+/**
+ * semphr. h
+ * <pre>SemaphoreHandle_t xSemaphoreCreateBinary( void )</pre>
+ *
+ * Creates a new binary semaphore instance, and returns a handle by which the
+ * new semaphore can be referenced.
+ *
+ * In many usage scenarios it is faster and more memory efficient to use a
+ * direct to task notification in place of a binary semaphore!
+ * http://www.freertos.org/RTOS-task-notifications.html
+ *
+ * Internally, within the FreeRTOS implementation, binary semaphores use a block
+ * of memory, in which the semaphore structure is stored.  If a binary semaphore
+ * is created using xSemaphoreCreateBinary() then the required memory is
+ * automatically dynamically allocated inside the xSemaphoreCreateBinary()
+ * function.  (see http://www.freertos.org/a00111.html).  If a binary semaphore
+ * is created using xSemaphoreCreateBinaryStatic() then the application writer
+ * must provide the memory.  xSemaphoreCreateBinaryStatic() therefore allows a
+ * binary semaphore to be created without using any dynamic memory allocation.
+ *
+ * The old vSemaphoreCreateBinary() macro is now deprecated in favour of this
+ * xSemaphoreCreateBinary() function.  Note that binary semaphores created using
+ * the vSemaphoreCreateBinary() macro are created in a state such that the
+ * first call to 'take' the semaphore would pass, whereas binary semaphores
+ * created using xSemaphoreCreateBinary() are created in a state such that the
+ * the semaphore must first be 'given' before it can be 'taken'.
+ *
+ * This type of semaphore can be used for pure synchronisation between tasks or
+ * between an interrupt and a task.  The semaphore need not be given back once
+ * obtained, so one task/interrupt can continuously 'give' the semaphore while
+ * another continuously 'takes' the semaphore.  For this reason this type of
+ * semaphore does not use a priority inheritance mechanism.  For an alternative
+ * that does use priority inheritance see xSemaphoreCreateMutex().
+ *
+ * @return Handle to the created semaphore, or NULL if the memory required to
+ * hold the semaphore's data structures could not be allocated.
+ *
+ * Example usage:
+ <pre>
+ SemaphoreHandle_t xSemaphore = NULL;
+
+ void vATask( void * pvParameters )
+ {
+    // Semaphore cannot be used before a call to xSemaphoreCreateBinary().
+    // This is a macro so pass the variable in directly.
+    xSemaphore = xSemaphoreCreateBinary();
+
+    if( xSemaphore != NULL )
+    {
+        // The semaphore was created successfully.
+        // The semaphore can now be used.
+    }
+ }
+ </pre>
+ * \defgroup xSemaphoreCreateBinary xSemaphoreCreateBinary
+ * \ingroup Semaphores
+ */
+#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+	#define xSemaphoreCreateBinary() xQueueGenericCreate( ( UBaseType_t ) 1, semSEMAPHORE_QUEUE_ITEM_LENGTH, queueQUEUE_TYPE_BINARY_SEMAPHORE )
+#endif
+
+/**
+ * semphr. h
+ * <pre>SemaphoreHandle_t xSemaphoreCreateBinaryStatic( StaticSemaphore_t *pxSemaphoreBuffer )</pre>
+ *
+ * Creates a new binary semaphore instance, and returns a handle by which the
+ * new semaphore can be referenced.
+ *
+ * NOTE: In many usage scenarios it is faster and more memory efficient to use a
+ * direct to task notification in place of a binary semaphore!
+ * http://www.freertos.org/RTOS-task-notifications.html
+ *
+ * Internally, within the FreeRTOS implementation, binary semaphores use a block
+ * of memory, in which the semaphore structure is stored.  If a binary semaphore
+ * is created using xSemaphoreCreateBinary() then the required memory is
+ * automatically dynamically allocated inside the xSemaphoreCreateBinary()
+ * function.  (see http://www.freertos.org/a00111.html).  If a binary semaphore
+ * is created using xSemaphoreCreateBinaryStatic() then the application writer
+ * must provide the memory.  xSemaphoreCreateBinaryStatic() therefore allows a
+ * binary semaphore to be created without using any dynamic memory allocation.
+ *
+ * This type of semaphore can be used for pure synchronisation between tasks or
+ * between an interrupt and a task.  The semaphore need not be given back once
+ * obtained, so one task/interrupt can continuously 'give' the semaphore while
+ * another continuously 'takes' the semaphore.  For this reason this type of
+ * semaphore does not use a priority inheritance mechanism.  For an alternative
+ * that does use priority inheritance see xSemaphoreCreateMutex().
+ *
+ * @param pxSemaphoreBuffer Must point to a variable of type StaticSemaphore_t,
+ * which will then be used to hold the semaphore's data structure, removing the
+ * need for the memory to be allocated dynamically.
+ *
+ * @return If the semaphore is created then a handle to the created semaphore is
+ * returned.  If pxSemaphoreBuffer is NULL then NULL is returned.
+ *
+ * Example usage:
+ <pre>
+ SemaphoreHandle_t xSemaphore = NULL;
+ StaticSemaphore_t xSemaphoreBuffer;
+
+ void vATask( void * pvParameters )
+ {
+    // Semaphore cannot be used before a call to xSemaphoreCreateBinary().
+    // The semaphore's data structures will be placed in the xSemaphoreBuffer
+    // variable, the address of which is passed into the function.  The
+    // function's parameter is not NULL, so the function will not attempt any
+    // dynamic memory allocation, and therefore the function will not return
+    // return NULL.
+    xSemaphore = xSemaphoreCreateBinary( &xSemaphoreBuffer );
+
+    // Rest of task code goes here.
+ }
+ </pre>
+ * \defgroup xSemaphoreCreateBinaryStatic xSemaphoreCreateBinaryStatic
+ * \ingroup Semaphores
+ */
+#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+	#define xSemaphoreCreateBinaryStatic( pxStaticSemaphore ) xQueueGenericCreateStatic( ( UBaseType_t ) 1, semSEMAPHORE_QUEUE_ITEM_LENGTH, NULL, pxStaticSemaphore, queueQUEUE_TYPE_BINARY_SEMAPHORE )
+#endif /* configSUPPORT_STATIC_ALLOCATION */
+
+/**
+ * semphr. h
+ * <pre>xSemaphoreTake(
+ *                   SemaphoreHandle_t xSemaphore,
+ *                   TickType_t xBlockTime
+ *               )</pre>
+ *
+ * <i>Macro</i> to obtain a semaphore.  The semaphore must have previously been
+ * created with a call to xSemaphoreCreateBinary(), xSemaphoreCreateMutex() or
+ * xSemaphoreCreateCounting().
+ *
+ * @param xSemaphore A handle to the semaphore being taken - obtained when
+ * the semaphore was created.
+ *
+ * @param xBlockTime The time in ticks to wait for the semaphore to become
+ * available.  The macro portTICK_PERIOD_MS can be used to convert this to a
+ * real time.  A block time of zero can be used to poll the semaphore.  A block
+ * time of portMAX_DELAY can be used to block indefinitely (provided
+ * INCLUDE_vTaskSuspend is set to 1 in FreeRTOSConfig.h).
+ *
+ * @return pdTRUE if the semaphore was obtained.  pdFALSE
+ * if xBlockTime expired without the semaphore becoming available.
+ *
+ * Example usage:
+ <pre>
+ SemaphoreHandle_t xSemaphore = NULL;
+
+ // A task that creates a semaphore.
+ void vATask( void * pvParameters )
+ {
+    // Create the semaphore to guard a shared resource.
+    xSemaphore = xSemaphoreCreateBinary();
+ }
+
+ // A task that uses the semaphore.
+ void vAnotherTask( void * pvParameters )
+ {
+    // ... Do other things.
+
+    if( xSemaphore != NULL )
+    {
+        // See if we can obtain the semaphore.  If the semaphore is not available
+        // wait 10 ticks to see if it becomes free.
+        if( xSemaphoreTake( xSemaphore, ( TickType_t ) 10 ) == pdTRUE )
+        {
+            // We were able to obtain the semaphore and can now access the
+            // shared resource.
+
+            // ...
+
+            // We have finished accessing the shared resource.  Release the
+            // semaphore.
+            xSemaphoreGive( xSemaphore );
+        }
+        else
+        {
+            // We could not obtain the semaphore and can therefore not access
+            // the shared resource safely.
+        }
+    }
+ }
+ </pre>
+ * \defgroup xSemaphoreTake xSemaphoreTake
+ * \ingroup Semaphores
+ */
+#define xSemaphoreTake( xSemaphore, xBlockTime )		xQueueSemaphoreTake( ( xSemaphore ), ( xBlockTime ) )
+
+/**
+ * semphr. h
+ * xSemaphoreTakeRecursive(
+ *                          SemaphoreHandle_t xMutex,
+ *                          TickType_t xBlockTime
+ *                        )
+ *
+ * <i>Macro</i> to recursively obtain, or 'take', a mutex type semaphore.
+ * The mutex must have previously been created using a call to
+ * xSemaphoreCreateRecursiveMutex();
+ *
+ * configUSE_RECURSIVE_MUTEXES must be set to 1 in FreeRTOSConfig.h for this
+ * macro to be available.
+ *
+ * This macro must not be used on mutexes created using xSemaphoreCreateMutex().
+ *
+ * A mutex used recursively can be 'taken' repeatedly by the owner. The mutex
+ * doesn't become available again until the owner has called
+ * xSemaphoreGiveRecursive() for each successful 'take' request.  For example,
+ * if a task successfully 'takes' the same mutex 5 times then the mutex will
+ * not be available to any other task until it has also  'given' the mutex back
+ * exactly five times.
+ *
+ * @param xMutex A handle to the mutex being obtained.  This is the
+ * handle returned by xSemaphoreCreateRecursiveMutex();
+ *
+ * @param xBlockTime The time in ticks to wait for the semaphore to become
+ * available.  The macro portTICK_PERIOD_MS can be used to convert this to a
+ * real time.  A block time of zero can be used to poll the semaphore.  If
+ * the task already owns the semaphore then xSemaphoreTakeRecursive() will
+ * return immediately no matter what the value of xBlockTime.
+ *
+ * @return pdTRUE if the semaphore was obtained.  pdFALSE if xBlockTime
+ * expired without the semaphore becoming available.
+ *
+ * Example usage:
+ <pre>
+ SemaphoreHandle_t xMutex = NULL;
+
+ // A task that creates a mutex.
+ void vATask( void * pvParameters )
+ {
+    // Create the mutex to guard a shared resource.
+    xMutex = xSemaphoreCreateRecursiveMutex();
+ }
+
+ // A task that uses the mutex.
+ void vAnotherTask( void * pvParameters )
+ {
+    // ... Do other things.
+
+    if( xMutex != NULL )
+    {
+        // See if we can obtain the mutex.  If the mutex is not available
+        // wait 10 ticks to see if it becomes free.
+        if( xSemaphoreTakeRecursive( xSemaphore, ( TickType_t ) 10 ) == pdTRUE )
+        {
+            // We were able to obtain the mutex and can now access the
+            // shared resource.
+
+            // ...
+            // For some reason due to the nature of the code further calls to
+            // xSemaphoreTakeRecursive() are made on the same mutex.  In real
+            // code these would not be just sequential calls as this would make
+            // no sense.  Instead the calls are likely to be buried inside
+            // a more complex call structure.
+            xSemaphoreTakeRecursive( xMutex, ( TickType_t ) 10 );
+            xSemaphoreTakeRecursive( xMutex, ( TickType_t ) 10 );
+
+            // The mutex has now been 'taken' three times, so will not be
+            // available to another task until it has also been given back
+            // three times.  Again it is unlikely that real code would have
+            // these calls sequentially, but instead buried in a more complex
+            // call structure.  This is just for illustrative purposes.
+            xSemaphoreGiveRecursive( xMutex );
+            xSemaphoreGiveRecursive( xMutex );
+            xSemaphoreGiveRecursive( xMutex );
+
+            // Now the mutex can be taken by other tasks.
+        }
+        else
+        {
+            // We could not obtain the mutex and can therefore not access
+            // the shared resource safely.
+        }
+    }
+ }
+ </pre>
+ * \defgroup xSemaphoreTakeRecursive xSemaphoreTakeRecursive
+ * \ingroup Semaphores
+ */
+#if( configUSE_RECURSIVE_MUTEXES == 1 )
+	#define xSemaphoreTakeRecursive( xMutex, xBlockTime )	xQueueTakeMutexRecursive( ( xMutex ), ( xBlockTime ) )
+#endif
+
+/**
+ * semphr. h
+ * <pre>xSemaphoreGive( SemaphoreHandle_t xSemaphore )</pre>
+ *
+ * <i>Macro</i> to release a semaphore.  The semaphore must have previously been
+ * created with a call to xSemaphoreCreateBinary(), xSemaphoreCreateMutex() or
+ * xSemaphoreCreateCounting(). and obtained using sSemaphoreTake().
+ *
+ * This macro must not be used from an ISR.  See xSemaphoreGiveFromISR () for
+ * an alternative which can be used from an ISR.
+ *
+ * This macro must also not be used on semaphores created using
+ * xSemaphoreCreateRecursiveMutex().
+ *
+ * @param xSemaphore A handle to the semaphore being released.  This is the
+ * handle returned when the semaphore was created.
+ *
+ * @return pdTRUE if the semaphore was released.  pdFALSE if an error occurred.
+ * Semaphores are implemented using queues.  An error can occur if there is
+ * no space on the queue to post a message - indicating that the
+ * semaphore was not first obtained correctly.
+ *
+ * Example usage:
+ <pre>
+ SemaphoreHandle_t xSemaphore = NULL;
+
+ void vATask( void * pvParameters )
+ {
+    // Create the semaphore to guard a shared resource.
+    xSemaphore = vSemaphoreCreateBinary();
+
+    if( xSemaphore != NULL )
+    {
+        if( xSemaphoreGive( xSemaphore ) != pdTRUE )
+        {
+            // We would expect this call to fail because we cannot give
+            // a semaphore without first "taking" it!
+        }
+
+        // Obtain the semaphore - don't block if the semaphore is not
+        // immediately available.
+        if( xSemaphoreTake( xSemaphore, ( TickType_t ) 0 ) )
+        {
+            // We now have the semaphore and can access the shared resource.
+
+            // ...
+
+            // We have finished accessing the shared resource so can free the
+            // semaphore.
+            if( xSemaphoreGive( xSemaphore ) != pdTRUE )
+            {
+                // We would not expect this call to fail because we must have
+                // obtained the semaphore to get here.
+            }
+        }
+    }
+ }
+ </pre>
+ * \defgroup xSemaphoreGive xSemaphoreGive
+ * \ingroup Semaphores
+ */
+#define xSemaphoreGive( xSemaphore )		xQueueGenericSend( ( QueueHandle_t ) ( xSemaphore ), NULL, semGIVE_BLOCK_TIME, queueSEND_TO_BACK )
+
+/**
+ * semphr. h
+ * <pre>xSemaphoreGiveRecursive( SemaphoreHandle_t xMutex )</pre>
+ *
+ * <i>Macro</i> to recursively release, or 'give', a mutex type semaphore.
+ * The mutex must have previously been created using a call to
+ * xSemaphoreCreateRecursiveMutex();
+ *
+ * configUSE_RECURSIVE_MUTEXES must be set to 1 in FreeRTOSConfig.h for this
+ * macro to be available.
+ *
+ * This macro must not be used on mutexes created using xSemaphoreCreateMutex().
+ *
+ * A mutex used recursively can be 'taken' repeatedly by the owner. The mutex
+ * doesn't become available again until the owner has called
+ * xSemaphoreGiveRecursive() for each successful 'take' request.  For example,
+ * if a task successfully 'takes' the same mutex 5 times then the mutex will
+ * not be available to any other task until it has also  'given' the mutex back
+ * exactly five times.
+ *
+ * @param xMutex A handle to the mutex being released, or 'given'.  This is the
+ * handle returned by xSemaphoreCreateMutex();
+ *
+ * @return pdTRUE if the semaphore was given.
+ *
+ * Example usage:
+ <pre>
+ SemaphoreHandle_t xMutex = NULL;
+
+ // A task that creates a mutex.
+ void vATask( void * pvParameters )
+ {
+    // Create the mutex to guard a shared resource.
+    xMutex = xSemaphoreCreateRecursiveMutex();
+ }
+
+ // A task that uses the mutex.
+ void vAnotherTask( void * pvParameters )
+ {
+    // ... Do other things.
+
+    if( xMutex != NULL )
+    {
+        // See if we can obtain the mutex.  If the mutex is not available
+        // wait 10 ticks to see if it becomes free.
+        if( xSemaphoreTakeRecursive( xMutex, ( TickType_t ) 10 ) == pdTRUE )
+        {
+            // We were able to obtain the mutex and can now access the
+            // shared resource.
+
+            // ...
+            // For some reason due to the nature of the code further calls to
+			// xSemaphoreTakeRecursive() are made on the same mutex.  In real
+			// code these would not be just sequential calls as this would make
+			// no sense.  Instead the calls are likely to be buried inside
+			// a more complex call structure.
+            xSemaphoreTakeRecursive( xMutex, ( TickType_t ) 10 );
+            xSemaphoreTakeRecursive( xMutex, ( TickType_t ) 10 );
+
+            // The mutex has now been 'taken' three times, so will not be
+			// available to another task until it has also been given back
+			// three times.  Again it is unlikely that real code would have
+			// these calls sequentially, it would be more likely that the calls
+			// to xSemaphoreGiveRecursive() would be called as a call stack
+			// unwound.  This is just for demonstrative purposes.
+            xSemaphoreGiveRecursive( xMutex );
+			xSemaphoreGiveRecursive( xMutex );
+			xSemaphoreGiveRecursive( xMutex );
+
+			// Now the mutex can be taken by other tasks.
+        }
+        else
+        {
+            // We could not obtain the mutex and can therefore not access
+            // the shared resource safely.
+        }
+    }
+ }
+ </pre>
+ * \defgroup xSemaphoreGiveRecursive xSemaphoreGiveRecursive
+ * \ingroup Semaphores
+ */
+#if( configUSE_RECURSIVE_MUTEXES == 1 )
+	#define xSemaphoreGiveRecursive( xMutex )	xQueueGiveMutexRecursive( ( xMutex ) )
+#endif
+
+/**
+ * semphr. h
+ * <pre>
+ xSemaphoreGiveFromISR(
+                          SemaphoreHandle_t xSemaphore,
+                          BaseType_t *pxHigherPriorityTaskWoken
+                      )</pre>
+ *
+ * <i>Macro</i> to  release a semaphore.  The semaphore must have previously been
+ * created with a call to xSemaphoreCreateBinary() or xSemaphoreCreateCounting().
+ *
+ * Mutex type semaphores (those created using a call to xSemaphoreCreateMutex())
+ * must not be used with this macro.
+ *
+ * This macro can be used from an ISR.
+ *
+ * @param xSemaphore A handle to the semaphore being released.  This is the
+ * handle returned when the semaphore was created.
+ *
+ * @param pxHigherPriorityTaskWoken xSemaphoreGiveFromISR() will set
+ * *pxHigherPriorityTaskWoken to pdTRUE if giving the semaphore caused a task
+ * to unblock, and the unblocked task has a priority higher than the currently
+ * running task.  If xSemaphoreGiveFromISR() sets this value to pdTRUE then
+ * a context switch should be requested before the interrupt is exited.
+ *
+ * @return pdTRUE if the semaphore was successfully given, otherwise errQUEUE_FULL.
+ *
+ * Example usage:
+ <pre>
+ \#define LONG_TIME 0xffff
+ \#define TICKS_TO_WAIT	10
+ SemaphoreHandle_t xSemaphore = NULL;
+
+ // Repetitive task.
+ void vATask( void * pvParameters )
+ {
+    for( ;; )
+    {
+        // We want this task to run every 10 ticks of a timer.  The semaphore
+        // was created before this task was started.
+
+        // Block waiting for the semaphore to become available.
+        if( xSemaphoreTake( xSemaphore, LONG_TIME ) == pdTRUE )
+        {
+            // It is time to execute.
+
+            // ...
+
+            // We have finished our task.  Return to the top of the loop where
+            // we will block on the semaphore until it is time to execute
+            // again.  Note when using the semaphore for synchronisation with an
+			// ISR in this manner there is no need to 'give' the semaphore back.
+        }
+    }
+ }
+
+ // Timer ISR
+ void vTimerISR( void * pvParameters )
+ {
+ static uint8_t ucLocalTickCount = 0;
+ static BaseType_t xHigherPriorityTaskWoken;
+
+    // A timer tick has occurred.
+
+    // ... Do other time functions.
+
+    // Is it time for vATask () to run?
+	xHigherPriorityTaskWoken = pdFALSE;
+    ucLocalTickCount++;
+    if( ucLocalTickCount >= TICKS_TO_WAIT )
+    {
+        // Unblock the task by releasing the semaphore.
+        xSemaphoreGiveFromISR( xSemaphore, &xHigherPriorityTaskWoken );
+
+        // Reset the count so we release the semaphore again in 10 ticks time.
+        ucLocalTickCount = 0;
+    }
+
+    if( xHigherPriorityTaskWoken != pdFALSE )
+    {
+        // We can force a context switch here.  Context switching from an
+        // ISR uses port specific syntax.  Check the demo task for your port
+        // to find the syntax required.
+    }
+ }
+ </pre>
+ * \defgroup xSemaphoreGiveFromISR xSemaphoreGiveFromISR
+ * \ingroup Semaphores
+ */
+#define xSemaphoreGiveFromISR( xSemaphore, pxHigherPriorityTaskWoken )	xQueueGiveFromISR( ( QueueHandle_t ) ( xSemaphore ), ( pxHigherPriorityTaskWoken ) )
+
+/**
+ * semphr. h
+ * <pre>
+ xSemaphoreTakeFromISR(
+                          SemaphoreHandle_t xSemaphore,
+                          BaseType_t *pxHigherPriorityTaskWoken
+                      )</pre>
+ *
+ * <i>Macro</i> to  take a semaphore from an ISR.  The semaphore must have
+ * previously been created with a call to xSemaphoreCreateBinary() or
+ * xSemaphoreCreateCounting().
+ *
+ * Mutex type semaphores (those created using a call to xSemaphoreCreateMutex())
+ * must not be used with this macro.
+ *
+ * This macro can be used from an ISR, however taking a semaphore from an ISR
+ * is not a common operation.  It is likely to only be useful when taking a
+ * counting semaphore when an interrupt is obtaining an object from a resource
+ * pool (when the semaphore count indicates the number of resources available).
+ *
+ * @param xSemaphore A handle to the semaphore being taken.  This is the
+ * handle returned when the semaphore was created.
+ *
+ * @param pxHigherPriorityTaskWoken xSemaphoreTakeFromISR() will set
+ * *pxHigherPriorityTaskWoken to pdTRUE if taking the semaphore caused a task
+ * to unblock, and the unblocked task has a priority higher than the currently
+ * running task.  If xSemaphoreTakeFromISR() sets this value to pdTRUE then
+ * a context switch should be requested before the interrupt is exited.
+ *
+ * @return pdTRUE if the semaphore was successfully taken, otherwise
+ * pdFALSE
+ */
+#define xSemaphoreTakeFromISR( xSemaphore, pxHigherPriorityTaskWoken )	xQueueReceiveFromISR( ( QueueHandle_t ) ( xSemaphore ), NULL, ( pxHigherPriorityTaskWoken ) )
+
+/**
+ * semphr. h
+ * <pre>SemaphoreHandle_t xSemaphoreCreateMutex( void )</pre>
+ *
+ * Creates a new mutex type semaphore instance, and returns a handle by which
+ * the new mutex can be referenced.
+ *
+ * Internally, within the FreeRTOS implementation, mutex semaphores use a block
+ * of memory, in which the mutex structure is stored.  If a mutex is created
+ * using xSemaphoreCreateMutex() then the required memory is automatically
+ * dynamically allocated inside the xSemaphoreCreateMutex() function.  (see
+ * http://www.freertos.org/a00111.html).  If a mutex is created using
+ * xSemaphoreCreateMutexStatic() then the application writer must provided the
+ * memory.  xSemaphoreCreateMutexStatic() therefore allows a mutex to be created
+ * without using any dynamic memory allocation.
+ *
+ * Mutexes created using this function can be accessed using the xSemaphoreTake()
+ * and xSemaphoreGive() macros.  The xSemaphoreTakeRecursive() and
+ * xSemaphoreGiveRecursive() macros must not be used.
+ *
+ * This type of semaphore uses a priority inheritance mechanism so a task
+ * 'taking' a semaphore MUST ALWAYS 'give' the semaphore back once the
+ * semaphore it is no longer required.
+ *
+ * Mutex type semaphores cannot be used from within interrupt service routines.
+ *
+ * See xSemaphoreCreateBinary() for an alternative implementation that can be
+ * used for pure synchronisation (where one task or interrupt always 'gives' the
+ * semaphore and another always 'takes' the semaphore) and from within interrupt
+ * service routines.
+ *
+ * @return If the mutex was successfully created then a handle to the created
+ * semaphore is returned.  If there was not enough heap to allocate the mutex
+ * data structures then NULL is returned.
+ *
+ * Example usage:
+ <pre>
+ SemaphoreHandle_t xSemaphore;
+
+ void vATask( void * pvParameters )
+ {
+    // Semaphore cannot be used before a call to xSemaphoreCreateMutex().
+    // This is a macro so pass the variable in directly.
+    xSemaphore = xSemaphoreCreateMutex();
+
+    if( xSemaphore != NULL )
+    {
+        // The semaphore was created successfully.
+        // The semaphore can now be used.
+    }
+ }
+ </pre>
+ * \defgroup xSemaphoreCreateMutex xSemaphoreCreateMutex
+ * \ingroup Semaphores
+ */
+#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+	#define xSemaphoreCreateMutex() xQueueCreateMutex( queueQUEUE_TYPE_MUTEX )
+#endif
+
+/**
+ * semphr. h
+ * <pre>SemaphoreHandle_t xSemaphoreCreateMutexStatic( StaticSemaphore_t *pxMutexBuffer )</pre>
+ *
+ * Creates a new mutex type semaphore instance, and returns a handle by which
+ * the new mutex can be referenced.
+ *
+ * Internally, within the FreeRTOS implementation, mutex semaphores use a block
+ * of memory, in which the mutex structure is stored.  If a mutex is created
+ * using xSemaphoreCreateMutex() then the required memory is automatically
+ * dynamically allocated inside the xSemaphoreCreateMutex() function.  (see
+ * http://www.freertos.org/a00111.html).  If a mutex is created using
+ * xSemaphoreCreateMutexStatic() then the application writer must provided the
+ * memory.  xSemaphoreCreateMutexStatic() therefore allows a mutex to be created
+ * without using any dynamic memory allocation.
+ *
+ * Mutexes created using this function can be accessed using the xSemaphoreTake()
+ * and xSemaphoreGive() macros.  The xSemaphoreTakeRecursive() and
+ * xSemaphoreGiveRecursive() macros must not be used.
+ *
+ * This type of semaphore uses a priority inheritance mechanism so a task
+ * 'taking' a semaphore MUST ALWAYS 'give' the semaphore back once the
+ * semaphore it is no longer required.
+ *
+ * Mutex type semaphores cannot be used from within interrupt service routines.
+ *
+ * See xSemaphoreCreateBinary() for an alternative implementation that can be
+ * used for pure synchronisation (where one task or interrupt always 'gives' the
+ * semaphore and another always 'takes' the semaphore) and from within interrupt
+ * service routines.
+ *
+ * @param pxMutexBuffer Must point to a variable of type StaticSemaphore_t,
+ * which will be used to hold the mutex's data structure, removing the need for
+ * the memory to be allocated dynamically.
+ *
+ * @return If the mutex was successfully created then a handle to the created
+ * mutex is returned.  If pxMutexBuffer was NULL then NULL is returned.
+ *
+ * Example usage:
+ <pre>
+ SemaphoreHandle_t xSemaphore;
+ StaticSemaphore_t xMutexBuffer;
+
+ void vATask( void * pvParameters )
+ {
+    // A mutex cannot be used before it has been created.  xMutexBuffer is
+    // into xSemaphoreCreateMutexStatic() so no dynamic memory allocation is
+    // attempted.
+    xSemaphore = xSemaphoreCreateMutexStatic( &xMutexBuffer );
+
+    // As no dynamic memory allocation was performed, xSemaphore cannot be NULL,
+    // so there is no need to check it.
+ }
+ </pre>
+ * \defgroup xSemaphoreCreateMutexStatic xSemaphoreCreateMutexStatic
+ * \ingroup Semaphores
+ */
+ #if( configSUPPORT_STATIC_ALLOCATION == 1 )
+	#define xSemaphoreCreateMutexStatic( pxMutexBuffer ) xQueueCreateMutexStatic( queueQUEUE_TYPE_MUTEX, ( pxMutexBuffer ) )
+#endif /* configSUPPORT_STATIC_ALLOCATION */
+
+
+/**
+ * semphr. h
+ * <pre>SemaphoreHandle_t xSemaphoreCreateRecursiveMutex( void )</pre>
+ *
+ * Creates a new recursive mutex type semaphore instance, and returns a handle
+ * by which the new recursive mutex can be referenced.
+ *
+ * Internally, within the FreeRTOS implementation, recursive mutexs use a block
+ * of memory, in which the mutex structure is stored.  If a recursive mutex is
+ * created using xSemaphoreCreateRecursiveMutex() then the required memory is
+ * automatically dynamically allocated inside the
+ * xSemaphoreCreateRecursiveMutex() function.  (see
+ * http://www.freertos.org/a00111.html).  If a recursive mutex is created using
+ * xSemaphoreCreateRecursiveMutexStatic() then the application writer must
+ * provide the memory that will get used by the mutex.
+ * xSemaphoreCreateRecursiveMutexStatic() therefore allows a recursive mutex to
+ * be created without using any dynamic memory allocation.
+ *
+ * Mutexes created using this macro can be accessed using the
+ * xSemaphoreTakeRecursive() and xSemaphoreGiveRecursive() macros.  The
+ * xSemaphoreTake() and xSemaphoreGive() macros must not be used.
+ *
+ * A mutex used recursively can be 'taken' repeatedly by the owner. The mutex
+ * doesn't become available again until the owner has called
+ * xSemaphoreGiveRecursive() for each successful 'take' request.  For example,
+ * if a task successfully 'takes' the same mutex 5 times then the mutex will
+ * not be available to any other task until it has also  'given' the mutex back
+ * exactly five times.
+ *
+ * This type of semaphore uses a priority inheritance mechanism so a task
+ * 'taking' a semaphore MUST ALWAYS 'give' the semaphore back once the
+ * semaphore it is no longer required.
+ *
+ * Mutex type semaphores cannot be used from within interrupt service routines.
+ *
+ * See xSemaphoreCreateBinary() for an alternative implementation that can be
+ * used for pure synchronisation (where one task or interrupt always 'gives' the
+ * semaphore and another always 'takes' the semaphore) and from within interrupt
+ * service routines.
+ *
+ * @return xSemaphore Handle to the created mutex semaphore.  Should be of type
+ * SemaphoreHandle_t.
+ *
+ * Example usage:
+ <pre>
+ SemaphoreHandle_t xSemaphore;
+
+ void vATask( void * pvParameters )
+ {
+    // Semaphore cannot be used before a call to xSemaphoreCreateMutex().
+    // This is a macro so pass the variable in directly.
+    xSemaphore = xSemaphoreCreateRecursiveMutex();
+
+    if( xSemaphore != NULL )
+    {
+        // The semaphore was created successfully.
+        // The semaphore can now be used.
+    }
+ }
+ </pre>
+ * \defgroup xSemaphoreCreateRecursiveMutex xSemaphoreCreateRecursiveMutex
+ * \ingroup Semaphores
+ */
+#if( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configUSE_RECURSIVE_MUTEXES == 1 ) )
+	#define xSemaphoreCreateRecursiveMutex() xQueueCreateMutex( queueQUEUE_TYPE_RECURSIVE_MUTEX )
+#endif
+
+/**
+ * semphr. h
+ * <pre>SemaphoreHandle_t xSemaphoreCreateRecursiveMutexStatic( StaticSemaphore_t *pxMutexBuffer )</pre>
+ *
+ * Creates a new recursive mutex type semaphore instance, and returns a handle
+ * by which the new recursive mutex can be referenced.
+ *
+ * Internally, within the FreeRTOS implementation, recursive mutexs use a block
+ * of memory, in which the mutex structure is stored.  If a recursive mutex is
+ * created using xSemaphoreCreateRecursiveMutex() then the required memory is
+ * automatically dynamically allocated inside the
+ * xSemaphoreCreateRecursiveMutex() function.  (see
+ * http://www.freertos.org/a00111.html).  If a recursive mutex is created using
+ * xSemaphoreCreateRecursiveMutexStatic() then the application writer must
+ * provide the memory that will get used by the mutex.
+ * xSemaphoreCreateRecursiveMutexStatic() therefore allows a recursive mutex to
+ * be created without using any dynamic memory allocation.
+ *
+ * Mutexes created using this macro can be accessed using the
+ * xSemaphoreTakeRecursive() and xSemaphoreGiveRecursive() macros.  The
+ * xSemaphoreTake() and xSemaphoreGive() macros must not be used.
+ *
+ * A mutex used recursively can be 'taken' repeatedly by the owner. The mutex
+ * doesn't become available again until the owner has called
+ * xSemaphoreGiveRecursive() for each successful 'take' request.  For example,
+ * if a task successfully 'takes' the same mutex 5 times then the mutex will
+ * not be available to any other task until it has also  'given' the mutex back
+ * exactly five times.
+ *
+ * This type of semaphore uses a priority inheritance mechanism so a task
+ * 'taking' a semaphore MUST ALWAYS 'give' the semaphore back once the
+ * semaphore it is no longer required.
+ *
+ * Mutex type semaphores cannot be used from within interrupt service routines.
+ *
+ * See xSemaphoreCreateBinary() for an alternative implementation that can be
+ * used for pure synchronisation (where one task or interrupt always 'gives' the
+ * semaphore and another always 'takes' the semaphore) and from within interrupt
+ * service routines.
+ *
+ * @param pxMutexBuffer Must point to a variable of type StaticSemaphore_t,
+ * which will then be used to hold the recursive mutex's data structure,
+ * removing the need for the memory to be allocated dynamically.
+ *
+ * @return If the recursive mutex was successfully created then a handle to the
+ * created recursive mutex is returned.  If pxMutexBuffer was NULL then NULL is
+ * returned.
+ *
+ * Example usage:
+ <pre>
+ SemaphoreHandle_t xSemaphore;
+ StaticSemaphore_t xMutexBuffer;
+
+ void vATask( void * pvParameters )
+ {
+    // A recursive semaphore cannot be used before it is created.  Here a
+    // recursive mutex is created using xSemaphoreCreateRecursiveMutexStatic().
+    // The address of xMutexBuffer is passed into the function, and will hold
+    // the mutexes data structures - so no dynamic memory allocation will be
+    // attempted.
+    xSemaphore = xSemaphoreCreateRecursiveMutexStatic( &xMutexBuffer );
+
+    // As no dynamic memory allocation was performed, xSemaphore cannot be NULL,
+    // so there is no need to check it.
+ }
+ </pre>
+ * \defgroup xSemaphoreCreateRecursiveMutexStatic xSemaphoreCreateRecursiveMutexStatic
+ * \ingroup Semaphores
+ */
+#if( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configUSE_RECURSIVE_MUTEXES == 1 ) )
+	#define xSemaphoreCreateRecursiveMutexStatic( pxStaticSemaphore ) xQueueCreateMutexStatic( queueQUEUE_TYPE_RECURSIVE_MUTEX, pxStaticSemaphore )
+#endif /* configSUPPORT_STATIC_ALLOCATION */
+
+/**
+ * semphr. h
+ * <pre>SemaphoreHandle_t xSemaphoreCreateCounting( UBaseType_t uxMaxCount, UBaseType_t uxInitialCount )</pre>
+ *
+ * Creates a new counting semaphore instance, and returns a handle by which the
+ * new counting semaphore can be referenced.
+ *
+ * In many usage scenarios it is faster and more memory efficient to use a
+ * direct to task notification in place of a counting semaphore!
+ * http://www.freertos.org/RTOS-task-notifications.html
+ *
+ * Internally, within the FreeRTOS implementation, counting semaphores use a
+ * block of memory, in which the counting semaphore structure is stored.  If a
+ * counting semaphore is created using xSemaphoreCreateCounting() then the
+ * required memory is automatically dynamically allocated inside the
+ * xSemaphoreCreateCounting() function.  (see
+ * http://www.freertos.org/a00111.html).  If a counting semaphore is created
+ * using xSemaphoreCreateCountingStatic() then the application writer can
+ * instead optionally provide the memory that will get used by the counting
+ * semaphore.  xSemaphoreCreateCountingStatic() therefore allows a counting
+ * semaphore to be created without using any dynamic memory allocation.
+ *
+ * Counting semaphores are typically used for two things:
+ *
+ * 1) Counting events.
+ *
+ *    In this usage scenario an event handler will 'give' a semaphore each time
+ *    an event occurs (incrementing the semaphore count value), and a handler
+ *    task will 'take' a semaphore each time it processes an event
+ *    (decrementing the semaphore count value).  The count value is therefore
+ *    the difference between the number of events that have occurred and the
+ *    number that have been processed.  In this case it is desirable for the
+ *    initial count value to be zero.
+ *
+ * 2) Resource management.
+ *
+ *    In this usage scenario the count value indicates the number of resources
+ *    available.  To obtain control of a resource a task must first obtain a
+ *    semaphore - decrementing the semaphore count value.  When the count value
+ *    reaches zero there are no free resources.  When a task finishes with the
+ *    resource it 'gives' the semaphore back - incrementing the semaphore count
+ *    value.  In this case it is desirable for the initial count value to be
+ *    equal to the maximum count value, indicating that all resources are free.
+ *
+ * @param uxMaxCount The maximum count value that can be reached.  When the
+ *        semaphore reaches this value it can no longer be 'given'.
+ *
+ * @param uxInitialCount The count value assigned to the semaphore when it is
+ *        created.
+ *
+ * @return Handle to the created semaphore.  Null if the semaphore could not be
+ *         created.
+ *
+ * Example usage:
+ <pre>
+ SemaphoreHandle_t xSemaphore;
+
+ void vATask( void * pvParameters )
+ {
+ SemaphoreHandle_t xSemaphore = NULL;
+
+    // Semaphore cannot be used before a call to xSemaphoreCreateCounting().
+    // The max value to which the semaphore can count should be 10, and the
+    // initial value assigned to the count should be 0.
+    xSemaphore = xSemaphoreCreateCounting( 10, 0 );
+
+    if( xSemaphore != NULL )
+    {
+        // The semaphore was created successfully.
+        // The semaphore can now be used.
+    }
+ }
+ </pre>
+ * \defgroup xSemaphoreCreateCounting xSemaphoreCreateCounting
+ * \ingroup Semaphores
+ */
+#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+	#define xSemaphoreCreateCounting( uxMaxCount, uxInitialCount ) xQueueCreateCountingSemaphore( ( uxMaxCount ), ( uxInitialCount ) )
+#endif
+
+/**
+ * semphr. h
+ * <pre>SemaphoreHandle_t xSemaphoreCreateCountingStatic( UBaseType_t uxMaxCount, UBaseType_t uxInitialCount, StaticSemaphore_t *pxSemaphoreBuffer )</pre>
+ *
+ * Creates a new counting semaphore instance, and returns a handle by which the
+ * new counting semaphore can be referenced.
+ *
+ * In many usage scenarios it is faster and more memory efficient to use a
+ * direct to task notification in place of a counting semaphore!
+ * http://www.freertos.org/RTOS-task-notifications.html
+ *
+ * Internally, within the FreeRTOS implementation, counting semaphores use a
+ * block of memory, in which the counting semaphore structure is stored.  If a
+ * counting semaphore is created using xSemaphoreCreateCounting() then the
+ * required memory is automatically dynamically allocated inside the
+ * xSemaphoreCreateCounting() function.  (see
+ * http://www.freertos.org/a00111.html).  If a counting semaphore is created
+ * using xSemaphoreCreateCountingStatic() then the application writer must
+ * provide the memory.  xSemaphoreCreateCountingStatic() therefore allows a
+ * counting semaphore to be created without using any dynamic memory allocation.
+ *
+ * Counting semaphores are typically used for two things:
+ *
+ * 1) Counting events.
+ *
+ *    In this usage scenario an event handler will 'give' a semaphore each time
+ *    an event occurs (incrementing the semaphore count value), and a handler
+ *    task will 'take' a semaphore each time it processes an event
+ *    (decrementing the semaphore count value).  The count value is therefore
+ *    the difference between the number of events that have occurred and the
+ *    number that have been processed.  In this case it is desirable for the
+ *    initial count value to be zero.
+ *
+ * 2) Resource management.
+ *
+ *    In this usage scenario the count value indicates the number of resources
+ *    available.  To obtain control of a resource a task must first obtain a
+ *    semaphore - decrementing the semaphore count value.  When the count value
+ *    reaches zero there are no free resources.  When a task finishes with the
+ *    resource it 'gives' the semaphore back - incrementing the semaphore count
+ *    value.  In this case it is desirable for the initial count value to be
+ *    equal to the maximum count value, indicating that all resources are free.
+ *
+ * @param uxMaxCount The maximum count value that can be reached.  When the
+ *        semaphore reaches this value it can no longer be 'given'.
+ *
+ * @param uxInitialCount The count value assigned to the semaphore when it is
+ *        created.
+ *
+ * @param pxSemaphoreBuffer Must point to a variable of type StaticSemaphore_t,
+ * which will then be used to hold the semaphore's data structure, removing the
+ * need for the memory to be allocated dynamically.
+ *
+ * @return If the counting semaphore was successfully created then a handle to
+ * the created counting semaphore is returned.  If pxSemaphoreBuffer was NULL
+ * then NULL is returned.
+ *
+ * Example usage:
+ <pre>
+ SemaphoreHandle_t xSemaphore;
+ StaticSemaphore_t xSemaphoreBuffer;
+
+ void vATask( void * pvParameters )
+ {
+ SemaphoreHandle_t xSemaphore = NULL;
+
+    // Counting semaphore cannot be used before they have been created.  Create
+    // a counting semaphore using xSemaphoreCreateCountingStatic().  The max
+    // value to which the semaphore can count is 10, and the initial value
+    // assigned to the count will be 0.  The address of xSemaphoreBuffer is
+    // passed in and will be used to hold the semaphore structure, so no dynamic
+    // memory allocation will be used.
+    xSemaphore = xSemaphoreCreateCounting( 10, 0, &xSemaphoreBuffer );
+
+    // No memory allocation was attempted so xSemaphore cannot be NULL, so there
+    // is no need to check its value.
+ }
+ </pre>
+ * \defgroup xSemaphoreCreateCountingStatic xSemaphoreCreateCountingStatic
+ * \ingroup Semaphores
+ */
+#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+	#define xSemaphoreCreateCountingStatic( uxMaxCount, uxInitialCount, pxSemaphoreBuffer ) xQueueCreateCountingSemaphoreStatic( ( uxMaxCount ), ( uxInitialCount ), ( pxSemaphoreBuffer ) )
+#endif /* configSUPPORT_STATIC_ALLOCATION */
+
+/**
+ * semphr. h
+ * <pre>void vSemaphoreDelete( SemaphoreHandle_t xSemaphore );</pre>
+ *
+ * Delete a semaphore.  This function must be used with care.  For example,
+ * do not delete a mutex type semaphore if the mutex is held by a task.
+ *
+ * @param xSemaphore A handle to the semaphore to be deleted.
+ *
+ * \defgroup vSemaphoreDelete vSemaphoreDelete
+ * \ingroup Semaphores
+ */
+#define vSemaphoreDelete( xSemaphore ) vQueueDelete( ( QueueHandle_t ) ( xSemaphore ) )
+
+/**
+ * semphr.h
+ * <pre>TaskHandle_t xSemaphoreGetMutexHolder( SemaphoreHandle_t xMutex );</pre>
+ *
+ * If xMutex is indeed a mutex type semaphore, return the current mutex holder.
+ * If xMutex is not a mutex type semaphore, or the mutex is available (not held
+ * by a task), return NULL.
+ *
+ * Note: This is a good way of determining if the calling task is the mutex
+ * holder, but not a good way of determining the identity of the mutex holder as
+ * the holder may change between the function exiting and the returned value
+ * being tested.
+ */
+#define xSemaphoreGetMutexHolder( xSemaphore ) xQueueGetMutexHolder( ( xSemaphore ) )
+
+/**
+ * semphr.h
+ * <pre>TaskHandle_t xSemaphoreGetMutexHolderFromISR( SemaphoreHandle_t xMutex );</pre>
+ *
+ * If xMutex is indeed a mutex type semaphore, return the current mutex holder.
+ * If xMutex is not a mutex type semaphore, or the mutex is available (not held
+ * by a task), return NULL.
+ *
+ */
+#define xSemaphoreGetMutexHolderFromISR( xSemaphore ) xQueueGetMutexHolderFromISR( ( xSemaphore ) )
+
+/**
+ * semphr.h
+ * <pre>UBaseType_t uxSemaphoreGetCount( SemaphoreHandle_t xSemaphore );</pre>
+ *
+ * If the semaphore is a counting semaphore then uxSemaphoreGetCount() returns
+ * its current count value.  If the semaphore is a binary semaphore then
+ * uxSemaphoreGetCount() returns 1 if the semaphore is available, and 0 if the
+ * semaphore is not available.
+ *
+ */
+#define uxSemaphoreGetCount( xSemaphore ) uxQueueMessagesWaiting( ( QueueHandle_t ) ( xSemaphore ) )
+
+#endif /* SEMAPHORE_H */
+
+
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/include/stack_macros.h b/Middlewares/Third_Party/FreeRTOS/Source/include/stack_macros.h
new file mode 100644
index 0000000..c505574
--- /dev/null
+++ b/Middlewares/Third_Party/FreeRTOS/Source/include/stack_macros.h
@@ -0,0 +1,129 @@
+/*
+ * FreeRTOS Kernel V10.3.1
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef STACK_MACROS_H
+#define STACK_MACROS_H
+
+/*
+ * Call the stack overflow hook function if the stack of the task being swapped
+ * out is currently overflowed, or looks like it might have overflowed in the
+ * past.
+ *
+ * Setting configCHECK_FOR_STACK_OVERFLOW to 1 will cause the macro to check
+ * the current stack state only - comparing the current top of stack value to
+ * the stack limit.  Setting configCHECK_FOR_STACK_OVERFLOW to greater than 1
+ * will also cause the last few stack bytes to be checked to ensure the value
+ * to which the bytes were set when the task was created have not been
+ * overwritten.  Note this second test does not guarantee that an overflowed
+ * stack will always be recognised.
+ */
+
+/*-----------------------------------------------------------*/
+
+#if( ( configCHECK_FOR_STACK_OVERFLOW == 1 ) && ( portSTACK_GROWTH < 0 ) )
+
+	/* Only the current stack state is to be checked. */
+	#define taskCHECK_FOR_STACK_OVERFLOW()																\
+	{																									\
+		/* Is the currently saved stack pointer within the stack limit? */								\
+		if( pxCurrentTCB->pxTopOfStack <= pxCurrentTCB->pxStack )										\
+		{																								\
+			vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pxCurrentTCB->pcTaskName );	\
+		}																								\
+	}
+
+#endif /* configCHECK_FOR_STACK_OVERFLOW == 1 */
+/*-----------------------------------------------------------*/
+
+#if( ( configCHECK_FOR_STACK_OVERFLOW == 1 ) && ( portSTACK_GROWTH > 0 ) )
+
+	/* Only the current stack state is to be checked. */
+	#define taskCHECK_FOR_STACK_OVERFLOW()																\
+	{																									\
+																										\
+		/* Is the currently saved stack pointer within the stack limit? */								\
+		if( pxCurrentTCB->pxTopOfStack >= pxCurrentTCB->pxEndOfStack )									\
+		{																								\
+			vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pxCurrentTCB->pcTaskName );	\
+		}																								\
+	}
+
+#endif /* configCHECK_FOR_STACK_OVERFLOW == 1 */
+/*-----------------------------------------------------------*/
+
+#if( ( configCHECK_FOR_STACK_OVERFLOW > 1 ) && ( portSTACK_GROWTH < 0 ) )
+
+	#define taskCHECK_FOR_STACK_OVERFLOW()																\
+	{																									\
+		const uint32_t * const pulStack = ( uint32_t * ) pxCurrentTCB->pxStack;							\
+		const uint32_t ulCheckValue = ( uint32_t ) 0xa5a5a5a5;											\
+																										\
+		if( ( pulStack[ 0 ] != ulCheckValue ) ||														\
+			( pulStack[ 1 ] != ulCheckValue ) ||														\
+			( pulStack[ 2 ] != ulCheckValue ) ||														\
+			( pulStack[ 3 ] != ulCheckValue ) )															\
+		{																								\
+			vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pxCurrentTCB->pcTaskName );	\
+		}																								\
+	}
+
+#endif /* #if( configCHECK_FOR_STACK_OVERFLOW > 1 ) */
+/*-----------------------------------------------------------*/
+
+#if( ( configCHECK_FOR_STACK_OVERFLOW > 1 ) && ( portSTACK_GROWTH > 0 ) )
+
+	#define taskCHECK_FOR_STACK_OVERFLOW()																								\
+	{																																	\
+	int8_t *pcEndOfStack = ( int8_t * ) pxCurrentTCB->pxEndOfStack;																		\
+	static const uint8_t ucExpectedStackBytes[] = {	tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE,		\
+													tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE,		\
+													tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE,		\
+													tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE,		\
+													tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE };	\
+																																		\
+																																		\
+		pcEndOfStack -= sizeof( ucExpectedStackBytes );																					\
+																																		\
+		/* Has the extremity of the task stack ever been written over? */																\
+		if( memcmp( ( void * ) pcEndOfStack, ( void * ) ucExpectedStackBytes, sizeof( ucExpectedStackBytes ) ) != 0 )					\
+		{																																\
+			vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pxCurrentTCB->pcTaskName );									\
+		}																																\
+	}
+
+#endif /* #if( configCHECK_FOR_STACK_OVERFLOW > 1 ) */
+/*-----------------------------------------------------------*/
+
+/* Remove stack overflow macro if not being used. */
+#ifndef taskCHECK_FOR_STACK_OVERFLOW
+	#define taskCHECK_FOR_STACK_OVERFLOW()
+#endif
+
+
+
+#endif /* STACK_MACROS_H */
+
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/include/stream_buffer.h b/Middlewares/Third_Party/FreeRTOS/Source/include/stream_buffer.h
new file mode 100644
index 0000000..3605703
--- /dev/null
+++ b/Middlewares/Third_Party/FreeRTOS/Source/include/stream_buffer.h
@@ -0,0 +1,859 @@
+/*
+ * FreeRTOS Kernel V10.3.1
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*
+ * Stream buffers are used to send a continuous stream of data from one task or
+ * interrupt to another.  Their implementation is light weight, making them
+ * particularly suited for interrupt to task and core to core communication
+ * scenarios.
+ *
+ * ***NOTE***:  Uniquely among FreeRTOS objects, the stream buffer
+ * implementation (so also the message buffer implementation, as message buffers
+ * are built on top of stream buffers) assumes there is only one task or
+ * interrupt that will write to the buffer (the writer), and only one task or
+ * interrupt that will read from the buffer (the reader).  It is safe for the
+ * writer and reader to be different tasks or interrupts, but, unlike other
+ * FreeRTOS objects, it is not safe to have multiple different writers or
+ * multiple different readers.  If there are to be multiple different writers
+ * then the application writer must place each call to a writing API function
+ * (such as xStreamBufferSend()) inside a critical section and set the send
+ * block time to 0.  Likewise, if there are to be multiple different readers
+ * then the application writer must place each call to a reading API function
+ * (such as xStreamBufferReceive()) inside a critical section section and set the
+ * receive block time to 0.
+ *
+ */
+
+#ifndef STREAM_BUFFER_H
+#define STREAM_BUFFER_H
+
+#ifndef INC_FREERTOS_H
+	#error "include FreeRTOS.h must appear in source files before include stream_buffer.h"
+#endif
+
+#if defined( __cplusplus )
+extern "C" {
+#endif
+
+/**
+ * Type by which stream buffers are referenced.  For example, a call to
+ * xStreamBufferCreate() returns an StreamBufferHandle_t variable that can
+ * then be used as a parameter to xStreamBufferSend(), xStreamBufferReceive(),
+ * etc.
+ */
+struct StreamBufferDef_t;
+typedef struct StreamBufferDef_t * StreamBufferHandle_t;
+
+
+/**
+ * message_buffer.h
+ *
+<pre>
+StreamBufferHandle_t xStreamBufferCreate( size_t xBufferSizeBytes, size_t xTriggerLevelBytes );
+</pre>
+ *
+ * Creates a new stream buffer using dynamically allocated memory.  See
+ * xStreamBufferCreateStatic() for a version that uses statically allocated
+ * memory (memory that is allocated at compile time).
+ *
+ * configSUPPORT_DYNAMIC_ALLOCATION must be set to 1 or left undefined in
+ * FreeRTOSConfig.h for xStreamBufferCreate() to be available.
+ *
+ * @param xBufferSizeBytes The total number of bytes the stream buffer will be
+ * able to hold at any one time.
+ *
+ * @param xTriggerLevelBytes The number of bytes that must be in the stream
+ * buffer before a task that is blocked on the stream buffer to wait for data is
+ * moved out of the blocked state.  For example, if a task is blocked on a read
+ * of an empty stream buffer that has a trigger level of 1 then the task will be
+ * unblocked when a single byte is written to the buffer or the task's block
+ * time expires.  As another example, if a task is blocked on a read of an empty
+ * stream buffer that has a trigger level of 10 then the task will not be
+ * unblocked until the stream buffer contains at least 10 bytes or the task's
+ * block time expires.  If a reading task's block time expires before the
+ * trigger level is reached then the task will still receive however many bytes
+ * are actually available.  Setting a trigger level of 0 will result in a
+ * trigger level of 1 being used.  It is not valid to specify a trigger level
+ * that is greater than the buffer size.
+ *
+ * @return If NULL is returned, then the stream buffer cannot be created
+ * because there is insufficient heap memory available for FreeRTOS to allocate
+ * the stream buffer data structures and storage area.  A non-NULL value being
+ * returned indicates that the stream buffer has been created successfully -
+ * the returned value should be stored as the handle to the created stream
+ * buffer.
+ *
+ * Example use:
+<pre>
+
+void vAFunction( void )
+{
+StreamBufferHandle_t xStreamBuffer;
+const size_t xStreamBufferSizeBytes = 100, xTriggerLevel = 10;
+
+    // Create a stream buffer that can hold 100 bytes.  The memory used to hold
+    // both the stream buffer structure and the data in the stream buffer is
+    // allocated dynamically.
+    xStreamBuffer = xStreamBufferCreate( xStreamBufferSizeBytes, xTriggerLevel );
+
+    if( xStreamBuffer == NULL )
+    {
+        // There was not enough heap memory space available to create the
+        // stream buffer.
+    }
+    else
+    {
+        // The stream buffer was created successfully and can now be used.
+    }
+}
+</pre>
+ * \defgroup xStreamBufferCreate xStreamBufferCreate
+ * \ingroup StreamBufferManagement
+ */
+#define xStreamBufferCreate( xBufferSizeBytes, xTriggerLevelBytes ) xStreamBufferGenericCreate( xBufferSizeBytes, xTriggerLevelBytes, pdFALSE )
+
+/**
+ * stream_buffer.h
+ *
+<pre>
+StreamBufferHandle_t xStreamBufferCreateStatic( size_t xBufferSizeBytes,
+                                                size_t xTriggerLevelBytes,
+                                                uint8_t *pucStreamBufferStorageArea,
+                                                StaticStreamBuffer_t *pxStaticStreamBuffer );
+</pre>
+ * Creates a new stream buffer using statically allocated memory.  See
+ * xStreamBufferCreate() for a version that uses dynamically allocated memory.
+ *
+ * configSUPPORT_STATIC_ALLOCATION must be set to 1 in FreeRTOSConfig.h for
+ * xStreamBufferCreateStatic() to be available.
+ *
+ * @param xBufferSizeBytes The size, in bytes, of the buffer pointed to by the
+ * pucStreamBufferStorageArea parameter.
+ *
+ * @param xTriggerLevelBytes The number of bytes that must be in the stream
+ * buffer before a task that is blocked on the stream buffer to wait for data is
+ * moved out of the blocked state.  For example, if a task is blocked on a read
+ * of an empty stream buffer that has a trigger level of 1 then the task will be
+ * unblocked when a single byte is written to the buffer or the task's block
+ * time expires.  As another example, if a task is blocked on a read of an empty
+ * stream buffer that has a trigger level of 10 then the task will not be
+ * unblocked until the stream buffer contains at least 10 bytes or the task's
+ * block time expires.  If a reading task's block time expires before the
+ * trigger level is reached then the task will still receive however many bytes
+ * are actually available.  Setting a trigger level of 0 will result in a
+ * trigger level of 1 being used.  It is not valid to specify a trigger level
+ * that is greater than the buffer size.
+ *
+ * @param pucStreamBufferStorageArea Must point to a uint8_t array that is at
+ * least xBufferSizeBytes + 1 big.  This is the array to which streams are
+ * copied when they are written to the stream buffer.
+ *
+ * @param pxStaticStreamBuffer Must point to a variable of type
+ * StaticStreamBuffer_t, which will be used to hold the stream buffer's data
+ * structure.
+ *
+ * @return If the stream buffer is created successfully then a handle to the
+ * created stream buffer is returned. If either pucStreamBufferStorageArea or
+ * pxStaticstreamBuffer are NULL then NULL is returned.
+ *
+ * Example use:
+<pre>
+
+// Used to dimension the array used to hold the streams.  The available space
+// will actually be one less than this, so 999.
+#define STORAGE_SIZE_BYTES 1000
+
+// Defines the memory that will actually hold the streams within the stream
+// buffer.
+static uint8_t ucStorageBuffer[ STORAGE_SIZE_BYTES ];
+
+// The variable used to hold the stream buffer structure.
+StaticStreamBuffer_t xStreamBufferStruct;
+
+void MyFunction( void )
+{
+StreamBufferHandle_t xStreamBuffer;
+const size_t xTriggerLevel = 1;
+
+    xStreamBuffer = xStreamBufferCreateStatic( sizeof( ucBufferStorage ),
+                                               xTriggerLevel,
+                                               ucBufferStorage,
+                                               &xStreamBufferStruct );
+
+    // As neither the pucStreamBufferStorageArea or pxStaticStreamBuffer
+    // parameters were NULL, xStreamBuffer will not be NULL, and can be used to
+    // reference the created stream buffer in other stream buffer API calls.
+
+    // Other code that uses the stream buffer can go here.
+}
+
+</pre>
+ * \defgroup xStreamBufferCreateStatic xStreamBufferCreateStatic
+ * \ingroup StreamBufferManagement
+ */
+#define xStreamBufferCreateStatic( xBufferSizeBytes, xTriggerLevelBytes, pucStreamBufferStorageArea, pxStaticStreamBuffer ) xStreamBufferGenericCreateStatic( xBufferSizeBytes, xTriggerLevelBytes, pdFALSE, pucStreamBufferStorageArea, pxStaticStreamBuffer )
+
+/**
+ * stream_buffer.h
+ *
+<pre>
+size_t xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
+                          const void *pvTxData,
+                          size_t xDataLengthBytes,
+                          TickType_t xTicksToWait );
+</pre>
+ *
+ * Sends bytes to a stream buffer.  The bytes are copied into the stream buffer.
+ *
+ * ***NOTE***:  Uniquely among FreeRTOS objects, the stream buffer
+ * implementation (so also the message buffer implementation, as message buffers
+ * are built on top of stream buffers) assumes there is only one task or
+ * interrupt that will write to the buffer (the writer), and only one task or
+ * interrupt that will read from the buffer (the reader).  It is safe for the
+ * writer and reader to be different tasks or interrupts, but, unlike other
+ * FreeRTOS objects, it is not safe to have multiple different writers or
+ * multiple different readers.  If there are to be multiple different writers
+ * then the application writer must place each call to a writing API function
+ * (such as xStreamBufferSend()) inside a critical section and set the send
+ * block time to 0.  Likewise, if there are to be multiple different readers
+ * then the application writer must place each call to a reading API function
+ * (such as xStreamBufferReceive()) inside a critical section and set the receive
+ * block time to 0.
+ *
+ * Use xStreamBufferSend() to write to a stream buffer from a task.  Use
+ * xStreamBufferSendFromISR() to write to a stream buffer from an interrupt
+ * service routine (ISR).
+ *
+ * @param xStreamBuffer The handle of the stream buffer to which a stream is
+ * being sent.
+ *
+ * @param pvTxData A pointer to the buffer that holds the bytes to be copied
+ * into the stream buffer.
+ *
+ * @param xDataLengthBytes   The maximum number of bytes to copy from pvTxData
+ * into the stream buffer.
+ *
+ * @param xTicksToWait The maximum amount of time the task should remain in the
+ * Blocked state to wait for enough space to become available in the stream
+ * buffer, should the stream buffer contain too little space to hold the
+ * another xDataLengthBytes bytes.  The block time is specified in tick periods,
+ * so the absolute time it represents is dependent on the tick frequency.  The
+ * macro pdMS_TO_TICKS() can be used to convert a time specified in milliseconds
+ * into a time specified in ticks.  Setting xTicksToWait to portMAX_DELAY will
+ * cause the task to wait indefinitely (without timing out), provided
+ * INCLUDE_vTaskSuspend is set to 1 in FreeRTOSConfig.h.  If a task times out
+ * before it can write all xDataLengthBytes into the buffer it will still write
+ * as many bytes as possible.  A task does not use any CPU time when it is in
+ * the blocked state.
+ *
+ * @return The number of bytes written to the stream buffer.  If a task times
+ * out before it can write all xDataLengthBytes into the buffer it will still
+ * write as many bytes as possible.
+ *
+ * Example use:
+<pre>
+void vAFunction( StreamBufferHandle_t xStreamBuffer )
+{
+size_t xBytesSent;
+uint8_t ucArrayToSend[] = { 0, 1, 2, 3 };
+char *pcStringToSend = "String to send";
+const TickType_t x100ms = pdMS_TO_TICKS( 100 );
+
+    // Send an array to the stream buffer, blocking for a maximum of 100ms to
+    // wait for enough space to be available in the stream buffer.
+    xBytesSent = xStreamBufferSend( xStreamBuffer, ( void * ) ucArrayToSend, sizeof( ucArrayToSend ), x100ms );
+
+    if( xBytesSent != sizeof( ucArrayToSend ) )
+    {
+        // The call to xStreamBufferSend() times out before there was enough
+        // space in the buffer for the data to be written, but it did
+        // successfully write xBytesSent bytes.
+    }
+
+    // Send the string to the stream buffer.  Return immediately if there is not
+    // enough space in the buffer.
+    xBytesSent = xStreamBufferSend( xStreamBuffer, ( void * ) pcStringToSend, strlen( pcStringToSend ), 0 );
+
+    if( xBytesSent != strlen( pcStringToSend ) )
+    {
+        // The entire string could not be added to the stream buffer because
+        // there was not enough free space in the buffer, but xBytesSent bytes
+        // were sent.  Could try again to send the remaining bytes.
+    }
+}
+</pre>
+ * \defgroup xStreamBufferSend xStreamBufferSend
+ * \ingroup StreamBufferManagement
+ */
+size_t xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
+						  const void *pvTxData,
+						  size_t xDataLengthBytes,
+						  TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+
+/**
+ * stream_buffer.h
+ *
+<pre>
+size_t xStreamBufferSendFromISR( StreamBufferHandle_t xStreamBuffer,
+                                 const void *pvTxData,
+                                 size_t xDataLengthBytes,
+                                 BaseType_t *pxHigherPriorityTaskWoken );
+</pre>
+ *
+ * Interrupt safe version of the API function that sends a stream of bytes to
+ * the stream buffer.
+ *
+ * ***NOTE***:  Uniquely among FreeRTOS objects, the stream buffer
+ * implementation (so also the message buffer implementation, as message buffers
+ * are built on top of stream buffers) assumes there is only one task or
+ * interrupt that will write to the buffer (the writer), and only one task or
+ * interrupt that will read from the buffer (the reader).  It is safe for the
+ * writer and reader to be different tasks or interrupts, but, unlike other
+ * FreeRTOS objects, it is not safe to have multiple different writers or
+ * multiple different readers.  If there are to be multiple different writers
+ * then the application writer must place each call to a writing API function
+ * (such as xStreamBufferSend()) inside a critical section and set the send
+ * block time to 0.  Likewise, if there are to be multiple different readers
+ * then the application writer must place each call to a reading API function
+ * (such as xStreamBufferReceive()) inside a critical section and set the receive
+ * block time to 0.
+ *
+ * Use xStreamBufferSend() to write to a stream buffer from a task.  Use
+ * xStreamBufferSendFromISR() to write to a stream buffer from an interrupt
+ * service routine (ISR).
+ *
+ * @param xStreamBuffer The handle of the stream buffer to which a stream is
+ * being sent.
+ *
+ * @param pvTxData A pointer to the data that is to be copied into the stream
+ * buffer.
+ *
+ * @param xDataLengthBytes The maximum number of bytes to copy from pvTxData
+ * into the stream buffer.
+ *
+ * @param pxHigherPriorityTaskWoken  It is possible that a stream buffer will
+ * have a task blocked on it waiting for data.  Calling
+ * xStreamBufferSendFromISR() can make data available, and so cause a task that
+ * was waiting for data to leave the Blocked state.  If calling
+ * xStreamBufferSendFromISR() causes a task to leave the Blocked state, and the
+ * unblocked task has a priority higher than the currently executing task (the
+ * task that was interrupted), then, internally, xStreamBufferSendFromISR()
+ * will set *pxHigherPriorityTaskWoken to pdTRUE.  If
+ * xStreamBufferSendFromISR() sets this value to pdTRUE, then normally a
+ * context switch should be performed before the interrupt is exited.  This will
+ * ensure that the interrupt returns directly to the highest priority Ready
+ * state task.  *pxHigherPriorityTaskWoken should be set to pdFALSE before it
+ * is passed into the function.  See the example code below for an example.
+ *
+ * @return The number of bytes actually written to the stream buffer, which will
+ * be less than xDataLengthBytes if the stream buffer didn't have enough free
+ * space for all the bytes to be written.
+ *
+ * Example use:
+<pre>
+// A stream buffer that has already been created.
+StreamBufferHandle_t xStreamBuffer;
+
+void vAnInterruptServiceRoutine( void )
+{
+size_t xBytesSent;
+char *pcStringToSend = "String to send";
+BaseType_t xHigherPriorityTaskWoken = pdFALSE; // Initialised to pdFALSE.
+
+    // Attempt to send the string to the stream buffer.
+    xBytesSent = xStreamBufferSendFromISR( xStreamBuffer,
+                                           ( void * ) pcStringToSend,
+                                           strlen( pcStringToSend ),
+                                           &xHigherPriorityTaskWoken );
+
+    if( xBytesSent != strlen( pcStringToSend ) )
+    {
+        // There was not enough free space in the stream buffer for the entire
+        // string to be written, ut xBytesSent bytes were written.
+    }
+
+    // If xHigherPriorityTaskWoken was set to pdTRUE inside
+    // xStreamBufferSendFromISR() then a task that has a priority above the
+    // priority of the currently executing task was unblocked and a context
+    // switch should be performed to ensure the ISR returns to the unblocked
+    // task.  In most FreeRTOS ports this is done by simply passing
+    // xHigherPriorityTaskWoken into taskYIELD_FROM_ISR(), which will test the
+    // variables value, and perform the context switch if necessary.  Check the
+    // documentation for the port in use for port specific instructions.
+    taskYIELD_FROM_ISR( xHigherPriorityTaskWoken );
+}
+</pre>
+ * \defgroup xStreamBufferSendFromISR xStreamBufferSendFromISR
+ * \ingroup StreamBufferManagement
+ */
+size_t xStreamBufferSendFromISR( StreamBufferHandle_t xStreamBuffer,
+								 const void *pvTxData,
+								 size_t xDataLengthBytes,
+								 BaseType_t * const pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;
+
+/**
+ * stream_buffer.h
+ *
+<pre>
+size_t xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
+                             void *pvRxData,
+                             size_t xBufferLengthBytes,
+                             TickType_t xTicksToWait );
+</pre>
+ *
+ * Receives bytes from a stream buffer.
+ *
+ * ***NOTE***:  Uniquely among FreeRTOS objects, the stream buffer
+ * implementation (so also the message buffer implementation, as message buffers
+ * are built on top of stream buffers) assumes there is only one task or
+ * interrupt that will write to the buffer (the writer), and only one task or
+ * interrupt that will read from the buffer (the reader).  It is safe for the
+ * writer and reader to be different tasks or interrupts, but, unlike other
+ * FreeRTOS objects, it is not safe to have multiple different writers or
+ * multiple different readers.  If there are to be multiple different writers
+ * then the application writer must place each call to a writing API function
+ * (such as xStreamBufferSend()) inside a critical section and set the send
+ * block time to 0.  Likewise, if there are to be multiple different readers
+ * then the application writer must place each call to a reading API function
+ * (such as xStreamBufferReceive()) inside a critical section and set the receive
+ * block time to 0.
+ *
+ * Use xStreamBufferReceive() to read from a stream buffer from a task.  Use
+ * xStreamBufferReceiveFromISR() to read from a stream buffer from an
+ * interrupt service routine (ISR).
+ *
+ * @param xStreamBuffer The handle of the stream buffer from which bytes are to
+ * be received.
+ *
+ * @param pvRxData A pointer to the buffer into which the received bytes will be
+ * copied.
+ *
+ * @param xBufferLengthBytes The length of the buffer pointed to by the
+ * pvRxData parameter.  This sets the maximum number of bytes to receive in one
+ * call.  xStreamBufferReceive will return as many bytes as possible up to a
+ * maximum set by xBufferLengthBytes.
+ *
+ * @param xTicksToWait The maximum amount of time the task should remain in the
+ * Blocked state to wait for data to become available if the stream buffer is
+ * empty.  xStreamBufferReceive() will return immediately if xTicksToWait is
+ * zero.  The block time is specified in tick periods, so the absolute time it
+ * represents is dependent on the tick frequency.  The macro pdMS_TO_TICKS() can
+ * be used to convert a time specified in milliseconds into a time specified in
+ * ticks.  Setting xTicksToWait to portMAX_DELAY will cause the task to wait
+ * indefinitely (without timing out), provided INCLUDE_vTaskSuspend is set to 1
+ * in FreeRTOSConfig.h.  A task does not use any CPU time when it is in the
+ * Blocked state.
+ *
+ * @return The number of bytes actually read from the stream buffer, which will
+ * be less than xBufferLengthBytes if the call to xStreamBufferReceive() timed
+ * out before xBufferLengthBytes were available.
+ *
+ * Example use:
+<pre>
+void vAFunction( StreamBuffer_t xStreamBuffer )
+{
+uint8_t ucRxData[ 20 ];
+size_t xReceivedBytes;
+const TickType_t xBlockTime = pdMS_TO_TICKS( 20 );
+
+    // Receive up to another sizeof( ucRxData ) bytes from the stream buffer.
+    // Wait in the Blocked state (so not using any CPU processing time) for a
+    // maximum of 100ms for the full sizeof( ucRxData ) number of bytes to be
+    // available.
+    xReceivedBytes = xStreamBufferReceive( xStreamBuffer,
+                                           ( void * ) ucRxData,
+                                           sizeof( ucRxData ),
+                                           xBlockTime );
+
+    if( xReceivedBytes > 0 )
+    {
+        // A ucRxData contains another xRecievedBytes bytes of data, which can
+        // be processed here....
+    }
+}
+</pre>
+ * \defgroup xStreamBufferReceive xStreamBufferReceive
+ * \ingroup StreamBufferManagement
+ */
+size_t xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
+							 void *pvRxData,
+							 size_t xBufferLengthBytes,
+							 TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+
+/**
+ * stream_buffer.h
+ *
+<pre>
+size_t xStreamBufferReceiveFromISR( StreamBufferHandle_t xStreamBuffer,
+                                    void *pvRxData,
+                                    size_t xBufferLengthBytes,
+                                    BaseType_t *pxHigherPriorityTaskWoken );
+</pre>
+ *
+ * An interrupt safe version of the API function that receives bytes from a
+ * stream buffer.
+ *
+ * Use xStreamBufferReceive() to read bytes from a stream buffer from a task.
+ * Use xStreamBufferReceiveFromISR() to read bytes from a stream buffer from an
+ * interrupt service routine (ISR).
+ *
+ * @param xStreamBuffer The handle of the stream buffer from which a stream
+ * is being received.
+ *
+ * @param pvRxData A pointer to the buffer into which the received bytes are
+ * copied.
+ *
+ * @param xBufferLengthBytes The length of the buffer pointed to by the
+ * pvRxData parameter.  This sets the maximum number of bytes to receive in one
+ * call.  xStreamBufferReceive will return as many bytes as possible up to a
+ * maximum set by xBufferLengthBytes.
+ *
+ * @param pxHigherPriorityTaskWoken  It is possible that a stream buffer will
+ * have a task blocked on it waiting for space to become available.  Calling
+ * xStreamBufferReceiveFromISR() can make space available, and so cause a task
+ * that is waiting for space to leave the Blocked state.  If calling
+ * xStreamBufferReceiveFromISR() causes a task to leave the Blocked state, and
+ * the unblocked task has a priority higher than the currently executing task
+ * (the task that was interrupted), then, internally,
+ * xStreamBufferReceiveFromISR() will set *pxHigherPriorityTaskWoken to pdTRUE.
+ * If xStreamBufferReceiveFromISR() sets this value to pdTRUE, then normally a
+ * context switch should be performed before the interrupt is exited.  That will
+ * ensure the interrupt returns directly to the highest priority Ready state
+ * task.  *pxHigherPriorityTaskWoken should be set to pdFALSE before it is
+ * passed into the function.  See the code example below for an example.
+ *
+ * @return The number of bytes read from the stream buffer, if any.
+ *
+ * Example use:
+<pre>
+// A stream buffer that has already been created.
+StreamBuffer_t xStreamBuffer;
+
+void vAnInterruptServiceRoutine( void )
+{
+uint8_t ucRxData[ 20 ];
+size_t xReceivedBytes;
+BaseType_t xHigherPriorityTaskWoken = pdFALSE;  // Initialised to pdFALSE.
+
+    // Receive the next stream from the stream buffer.
+    xReceivedBytes = xStreamBufferReceiveFromISR( xStreamBuffer,
+                                                  ( void * ) ucRxData,
+                                                  sizeof( ucRxData ),
+                                                  &xHigherPriorityTaskWoken );
+
+    if( xReceivedBytes > 0 )
+    {
+        // ucRxData contains xReceivedBytes read from the stream buffer.
+        // Process the stream here....
+    }
+
+    // If xHigherPriorityTaskWoken was set to pdTRUE inside
+    // xStreamBufferReceiveFromISR() then a task that has a priority above the
+    // priority of the currently executing task was unblocked and a context
+    // switch should be performed to ensure the ISR returns to the unblocked
+    // task.  In most FreeRTOS ports this is done by simply passing
+    // xHigherPriorityTaskWoken into taskYIELD_FROM_ISR(), which will test the
+    // variables value, and perform the context switch if necessary.  Check the
+    // documentation for the port in use for port specific instructions.
+    taskYIELD_FROM_ISR( xHigherPriorityTaskWoken );
+}
+</pre>
+ * \defgroup xStreamBufferReceiveFromISR xStreamBufferReceiveFromISR
+ * \ingroup StreamBufferManagement
+ */
+size_t xStreamBufferReceiveFromISR( StreamBufferHandle_t xStreamBuffer,
+									void *pvRxData,
+									size_t xBufferLengthBytes,
+									BaseType_t * const pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;
+
+/**
+ * stream_buffer.h
+ *
+<pre>
+void vStreamBufferDelete( StreamBufferHandle_t xStreamBuffer );
+</pre>
+ *
+ * Deletes a stream buffer that was previously created using a call to
+ * xStreamBufferCreate() or xStreamBufferCreateStatic().  If the stream
+ * buffer was created using dynamic memory (that is, by xStreamBufferCreate()),
+ * then the allocated memory is freed.
+ *
+ * A stream buffer handle must not be used after the stream buffer has been
+ * deleted.
+ *
+ * @param xStreamBuffer The handle of the stream buffer to be deleted.
+ *
+ * \defgroup vStreamBufferDelete vStreamBufferDelete
+ * \ingroup StreamBufferManagement
+ */
+void vStreamBufferDelete( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;
+
+/**
+ * stream_buffer.h
+ *
+<pre>
+BaseType_t xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer );
+</pre>
+ *
+ * Queries a stream buffer to see if it is full.  A stream buffer is full if it
+ * does not have any free space, and therefore cannot accept any more data.
+ *
+ * @param xStreamBuffer The handle of the stream buffer being queried.
+ *
+ * @return If the stream buffer is full then pdTRUE is returned.  Otherwise
+ * pdFALSE is returned.
+ *
+ * \defgroup xStreamBufferIsFull xStreamBufferIsFull
+ * \ingroup StreamBufferManagement
+ */
+BaseType_t xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;
+
+/**
+ * stream_buffer.h
+ *
+<pre>
+BaseType_t xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer );
+</pre>
+ *
+ * Queries a stream buffer to see if it is empty.  A stream buffer is empty if
+ * it does not contain any data.
+ *
+ * @param xStreamBuffer The handle of the stream buffer being queried.
+ *
+ * @return If the stream buffer is empty then pdTRUE is returned.  Otherwise
+ * pdFALSE is returned.
+ *
+ * \defgroup xStreamBufferIsEmpty xStreamBufferIsEmpty
+ * \ingroup StreamBufferManagement
+ */
+BaseType_t xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;
+
+/**
+ * stream_buffer.h
+ *
+<pre>
+BaseType_t xStreamBufferReset( StreamBufferHandle_t xStreamBuffer );
+</pre>
+ *
+ * Resets a stream buffer to its initial, empty, state.  Any data that was in
+ * the stream buffer is discarded.  A stream buffer can only be reset if there
+ * are no tasks blocked waiting to either send to or receive from the stream
+ * buffer.
+ *
+ * @param xStreamBuffer The handle of the stream buffer being reset.
+ *
+ * @return If the stream buffer is reset then pdPASS is returned.  If there was
+ * a task blocked waiting to send to or read from the stream buffer then the
+ * stream buffer is not reset and pdFAIL is returned.
+ *
+ * \defgroup xStreamBufferReset xStreamBufferReset
+ * \ingroup StreamBufferManagement
+ */
+BaseType_t xStreamBufferReset( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;
+
+/**
+ * stream_buffer.h
+ *
+<pre>
+size_t xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer );
+</pre>
+ *
+ * Queries a stream buffer to see how much free space it contains, which is
+ * equal to the amount of data that can be sent to the stream buffer before it
+ * is full.
+ *
+ * @param xStreamBuffer The handle of the stream buffer being queried.
+ *
+ * @return The number of bytes that can be written to the stream buffer before
+ * the stream buffer would be full.
+ *
+ * \defgroup xStreamBufferSpacesAvailable xStreamBufferSpacesAvailable
+ * \ingroup StreamBufferManagement
+ */
+size_t xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;
+
+/**
+ * stream_buffer.h
+ *
+<pre>
+size_t xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer );
+</pre>
+ *
+ * Queries a stream buffer to see how much data it contains, which is equal to
+ * the number of bytes that can be read from the stream buffer before the stream
+ * buffer would be empty.
+ *
+ * @param xStreamBuffer The handle of the stream buffer being queried.
+ *
+ * @return The number of bytes that can be read from the stream buffer before
+ * the stream buffer would be empty.
+ *
+ * \defgroup xStreamBufferBytesAvailable xStreamBufferBytesAvailable
+ * \ingroup StreamBufferManagement
+ */
+size_t xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;
+
+/**
+ * stream_buffer.h
+ *
+<pre>
+BaseType_t xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer, size_t xTriggerLevel );
+</pre>
+ *
+ * A stream buffer's trigger level is the number of bytes that must be in the
+ * stream buffer before a task that is blocked on the stream buffer to
+ * wait for data is moved out of the blocked state.  For example, if a task is
+ * blocked on a read of an empty stream buffer that has a trigger level of 1
+ * then the task will be unblocked when a single byte is written to the buffer
+ * or the task's block time expires.  As another example, if a task is blocked
+ * on a read of an empty stream buffer that has a trigger level of 10 then the
+ * task will not be unblocked until the stream buffer contains at least 10 bytes
+ * or the task's block time expires.  If a reading task's block time expires
+ * before the trigger level is reached then the task will still receive however
+ * many bytes are actually available.  Setting a trigger level of 0 will result
+ * in a trigger level of 1 being used.  It is not valid to specify a trigger
+ * level that is greater than the buffer size.
+ *
+ * A trigger level is set when the stream buffer is created, and can be modified
+ * using xStreamBufferSetTriggerLevel().
+ *
+ * @param xStreamBuffer The handle of the stream buffer being updated.
+ *
+ * @param xTriggerLevel The new trigger level for the stream buffer.
+ *
+ * @return If xTriggerLevel was less than or equal to the stream buffer's length
+ * then the trigger level will be updated and pdTRUE is returned.  Otherwise
+ * pdFALSE is returned.
+ *
+ * \defgroup xStreamBufferSetTriggerLevel xStreamBufferSetTriggerLevel
+ * \ingroup StreamBufferManagement
+ */
+BaseType_t xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer, size_t xTriggerLevel ) PRIVILEGED_FUNCTION;
+
+/**
+ * stream_buffer.h
+ *
+<pre>
+BaseType_t xStreamBufferSendCompletedFromISR( StreamBufferHandle_t xStreamBuffer, BaseType_t *pxHigherPriorityTaskWoken );
+</pre>
+ *
+ * For advanced users only.
+ *
+ * The sbSEND_COMPLETED() macro is called from within the FreeRTOS APIs when
+ * data is sent to a message buffer or stream buffer.  If there was a task that
+ * was blocked on the message or stream buffer waiting for data to arrive then
+ * the sbSEND_COMPLETED() macro sends a notification to the task to remove it
+ * from the Blocked state.  xStreamBufferSendCompletedFromISR() does the same
+ * thing.  It is provided to enable application writers to implement their own
+ * version of sbSEND_COMPLETED(), and MUST NOT BE USED AT ANY OTHER TIME.
+ *
+ * See the example implemented in FreeRTOS/Demo/Minimal/MessageBufferAMP.c for
+ * additional information.
+ *
+ * @param xStreamBuffer The handle of the stream buffer to which data was
+ * written.
+ *
+ * @param pxHigherPriorityTaskWoken *pxHigherPriorityTaskWoken should be
+ * initialised to pdFALSE before it is passed into
+ * xStreamBufferSendCompletedFromISR().  If calling
+ * xStreamBufferSendCompletedFromISR() removes a task from the Blocked state,
+ * and the task has a priority above the priority of the currently running task,
+ * then *pxHigherPriorityTaskWoken will get set to pdTRUE indicating that a
+ * context switch should be performed before exiting the ISR.
+ *
+ * @return If a task was removed from the Blocked state then pdTRUE is returned.
+ * Otherwise pdFALSE is returned.
+ *
+ * \defgroup xStreamBufferSendCompletedFromISR xStreamBufferSendCompletedFromISR
+ * \ingroup StreamBufferManagement
+ */
+BaseType_t xStreamBufferSendCompletedFromISR( StreamBufferHandle_t xStreamBuffer, BaseType_t *pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;
+
+/**
+ * stream_buffer.h
+ *
+<pre>
+BaseType_t xStreamBufferReceiveCompletedFromISR( StreamBufferHandle_t xStreamBuffer, BaseType_t *pxHigherPriorityTaskWoken );
+</pre>
+ *
+ * For advanced users only.
+ *
+ * The sbRECEIVE_COMPLETED() macro is called from within the FreeRTOS APIs when
+ * data is read out of a message buffer or stream buffer.  If there was a task
+ * that was blocked on the message or stream buffer waiting for data to arrive
+ * then the sbRECEIVE_COMPLETED() macro sends a notification to the task to
+ * remove it from the Blocked state.  xStreamBufferReceiveCompletedFromISR()
+ * does the same thing.  It is provided to enable application writers to
+ * implement their own version of sbRECEIVE_COMPLETED(), and MUST NOT BE USED AT
+ * ANY OTHER TIME.
+ *
+ * See the example implemented in FreeRTOS/Demo/Minimal/MessageBufferAMP.c for
+ * additional information.
+ *
+ * @param xStreamBuffer The handle of the stream buffer from which data was
+ * read.
+ *
+ * @param pxHigherPriorityTaskWoken *pxHigherPriorityTaskWoken should be
+ * initialised to pdFALSE before it is passed into
+ * xStreamBufferReceiveCompletedFromISR().  If calling
+ * xStreamBufferReceiveCompletedFromISR() removes a task from the Blocked state,
+ * and the task has a priority above the priority of the currently running task,
+ * then *pxHigherPriorityTaskWoken will get set to pdTRUE indicating that a
+ * context switch should be performed before exiting the ISR.
+ *
+ * @return If a task was removed from the Blocked state then pdTRUE is returned.
+ * Otherwise pdFALSE is returned.
+ *
+ * \defgroup xStreamBufferReceiveCompletedFromISR xStreamBufferReceiveCompletedFromISR
+ * \ingroup StreamBufferManagement
+ */
+BaseType_t xStreamBufferReceiveCompletedFromISR( StreamBufferHandle_t xStreamBuffer, BaseType_t *pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;
+
+/* Functions below here are not part of the public API. */
+StreamBufferHandle_t xStreamBufferGenericCreate( size_t xBufferSizeBytes,
+												 size_t xTriggerLevelBytes,
+												 BaseType_t xIsMessageBuffer ) PRIVILEGED_FUNCTION;
+
+StreamBufferHandle_t xStreamBufferGenericCreateStatic( size_t xBufferSizeBytes,
+													   size_t xTriggerLevelBytes,
+													   BaseType_t xIsMessageBuffer,
+													   uint8_t * const pucStreamBufferStorageArea,
+													   StaticStreamBuffer_t * const pxStaticStreamBuffer ) PRIVILEGED_FUNCTION;
+
+size_t xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;
+
+#if( configUSE_TRACE_FACILITY == 1 )
+	void vStreamBufferSetStreamBufferNumber( StreamBufferHandle_t xStreamBuffer, UBaseType_t uxStreamBufferNumber ) PRIVILEGED_FUNCTION;
+	UBaseType_t uxStreamBufferGetStreamBufferNumber( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;
+	uint8_t ucStreamBufferGetStreamBufferType( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;
+#endif
+
+#if defined( __cplusplus )
+}
+#endif
+
+#endif	/* !defined( STREAM_BUFFER_H ) */
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/include/task.h b/Middlewares/Third_Party/FreeRTOS/Source/include/task.h
new file mode 100644
index 0000000..4b8639c
--- /dev/null
+++ b/Middlewares/Third_Party/FreeRTOS/Source/include/task.h
@@ -0,0 +1,2543 @@
+/*
+ * FreeRTOS Kernel V10.3.1
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef INC_TASK_H
+#define INC_TASK_H
+
+#ifndef INC_FREERTOS_H
+	#error "include FreeRTOS.h must appear in source files before include task.h"
+#endif
+
+#include "list.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*-----------------------------------------------------------
+ * MACROS AND DEFINITIONS
+ *----------------------------------------------------------*/
+
+#define tskKERNEL_VERSION_NUMBER "V10.3.1"
+#define tskKERNEL_VERSION_MAJOR 10
+#define tskKERNEL_VERSION_MINOR 3
+#define tskKERNEL_VERSION_BUILD 1
+
+/* MPU region parameters passed in ulParameters
+ * of MemoryRegion_t struct. */
+#define tskMPU_REGION_READ_ONLY			( 1UL << 0UL )
+#define tskMPU_REGION_READ_WRITE		( 1UL << 1UL )
+#define tskMPU_REGION_EXECUTE_NEVER		( 1UL << 2UL )
+#define tskMPU_REGION_NORMAL_MEMORY		( 1UL << 3UL )
+#define tskMPU_REGION_DEVICE_MEMORY		( 1UL << 4UL )
+
+/**
+ * task. h
+ *
+ * Type by which tasks are referenced.  For example, a call to xTaskCreate
+ * returns (via a pointer parameter) an TaskHandle_t variable that can then
+ * be used as a parameter to vTaskDelete to delete the task.
+ *
+ * \defgroup TaskHandle_t TaskHandle_t
+ * \ingroup Tasks
+ */
+struct tskTaskControlBlock; /* The old naming convention is used to prevent breaking kernel aware debuggers. */
+typedef struct tskTaskControlBlock* TaskHandle_t;
+
+/*
+ * Defines the prototype to which the application task hook function must
+ * conform.
+ */
+typedef BaseType_t (*TaskHookFunction_t)( void * );
+
+/* Task states returned by eTaskGetState. */
+typedef enum
+{
+	eRunning = 0,	/* A task is querying the state of itself, so must be running. */
+	eReady,			/* The task being queried is in a read or pending ready list. */
+	eBlocked,		/* The task being queried is in the Blocked state. */
+	eSuspended,		/* The task being queried is in the Suspended state, or is in the Blocked state with an infinite time out. */
+	eDeleted,		/* The task being queried has been deleted, but its TCB has not yet been freed. */
+	eInvalid		/* Used as an 'invalid state' value. */
+} eTaskState;
+
+/* Actions that can be performed when vTaskNotify() is called. */
+typedef enum
+{
+	eNoAction = 0,				/* Notify the task without updating its notify value. */
+	eSetBits,					/* Set bits in the task's notification value. */
+	eIncrement,					/* Increment the task's notification value. */
+	eSetValueWithOverwrite,		/* Set the task's notification value to a specific value even if the previous value has not yet been read by the task. */
+	eSetValueWithoutOverwrite	/* Set the task's notification value if the previous value has been read by the task. */
+} eNotifyAction;
+
+/*
+ * Used internally only.
+ */
+typedef struct xTIME_OUT
+{
+	BaseType_t xOverflowCount;
+	TickType_t xTimeOnEntering;
+} TimeOut_t;
+
+/*
+ * Defines the memory ranges allocated to the task when an MPU is used.
+ */
+typedef struct xMEMORY_REGION
+{
+	void *pvBaseAddress;
+	uint32_t ulLengthInBytes;
+	uint32_t ulParameters;
+} MemoryRegion_t;
+
+/*
+ * Parameters required to create an MPU protected task.
+ */
+typedef struct xTASK_PARAMETERS
+{
+	TaskFunction_t pvTaskCode;
+	const char * const pcName;	/*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+	configSTACK_DEPTH_TYPE usStackDepth;
+	void *pvParameters;
+	UBaseType_t uxPriority;
+	StackType_t *puxStackBuffer;
+	MemoryRegion_t xRegions[ portNUM_CONFIGURABLE_REGIONS ];
+	#if ( ( portUSING_MPU_WRAPPERS == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) )
+		StaticTask_t * const pxTaskBuffer;
+	#endif
+} TaskParameters_t;
+
+/* Used with the uxTaskGetSystemState() function to return the state of each task
+in the system. */
+typedef struct xTASK_STATUS
+{
+	TaskHandle_t xHandle;			/* The handle of the task to which the rest of the information in the structure relates. */
+	const char *pcTaskName;			/* A pointer to the task's name.  This value will be invalid if the task was deleted since the structure was populated! */ /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+	UBaseType_t xTaskNumber;		/* A number unique to the task. */
+	eTaskState eCurrentState;		/* The state in which the task existed when the structure was populated. */
+	UBaseType_t uxCurrentPriority;	/* The priority at which the task was running (may be inherited) when the structure was populated. */
+	UBaseType_t uxBasePriority;		/* The priority to which the task will return if the task's current priority has been inherited to avoid unbounded priority inversion when obtaining a mutex.  Only valid if configUSE_MUTEXES is defined as 1 in FreeRTOSConfig.h. */
+	uint32_t ulRunTimeCounter;		/* The total run time allocated to the task so far, as defined by the run time stats clock.  See http://www.freertos.org/rtos-run-time-stats.html.  Only valid when configGENERATE_RUN_TIME_STATS is defined as 1 in FreeRTOSConfig.h. */
+	StackType_t *pxStackBase;		/* Points to the lowest address of the task's stack area. */
+	configSTACK_DEPTH_TYPE usStackHighWaterMark;	/* The minimum amount of stack space that has remained for the task since the task was created.  The closer this value is to zero the closer the task has come to overflowing its stack. */
+} TaskStatus_t;
+
+/* Possible return values for eTaskConfirmSleepModeStatus(). */
+typedef enum
+{
+	eAbortSleep = 0,		/* A task has been made ready or a context switch pended since portSUPPORESS_TICKS_AND_SLEEP() was called - abort entering a sleep mode. */
+	eStandardSleep,			/* Enter a sleep mode that will not last any longer than the expected idle time. */
+	eNoTasksWaitingTimeout	/* No tasks are waiting for a timeout so it is safe to enter a sleep mode that can only be exited by an external interrupt. */
+} eSleepModeStatus;
+
+/**
+ * Defines the priority used by the idle task.  This must not be modified.
+ *
+ * \ingroup TaskUtils
+ */
+#define tskIDLE_PRIORITY			( ( UBaseType_t ) 0U )
+
+/**
+ * task. h
+ *
+ * Macro for forcing a context switch.
+ *
+ * \defgroup taskYIELD taskYIELD
+ * \ingroup SchedulerControl
+ */
+#define taskYIELD()					portYIELD()
+
+/**
+ * task. h
+ *
+ * Macro to mark the start of a critical code region.  Preemptive context
+ * switches cannot occur when in a critical region.
+ *
+ * NOTE: This may alter the stack (depending on the portable implementation)
+ * so must be used with care!
+ *
+ * \defgroup taskENTER_CRITICAL taskENTER_CRITICAL
+ * \ingroup SchedulerControl
+ */
+#define taskENTER_CRITICAL()		portENTER_CRITICAL()
+#define taskENTER_CRITICAL_FROM_ISR() portSET_INTERRUPT_MASK_FROM_ISR()
+
+/**
+ * task. h
+ *
+ * Macro to mark the end of a critical code region.  Preemptive context
+ * switches cannot occur when in a critical region.
+ *
+ * NOTE: This may alter the stack (depending on the portable implementation)
+ * so must be used with care!
+ *
+ * \defgroup taskEXIT_CRITICAL taskEXIT_CRITICAL
+ * \ingroup SchedulerControl
+ */
+#define taskEXIT_CRITICAL()			portEXIT_CRITICAL()
+#define taskEXIT_CRITICAL_FROM_ISR( x ) portCLEAR_INTERRUPT_MASK_FROM_ISR( x )
+/**
+ * task. h
+ *
+ * Macro to disable all maskable interrupts.
+ *
+ * \defgroup taskDISABLE_INTERRUPTS taskDISABLE_INTERRUPTS
+ * \ingroup SchedulerControl
+ */
+#define taskDISABLE_INTERRUPTS()	portDISABLE_INTERRUPTS()
+
+/**
+ * task. h
+ *
+ * Macro to enable microcontroller interrupts.
+ *
+ * \defgroup taskENABLE_INTERRUPTS taskENABLE_INTERRUPTS
+ * \ingroup SchedulerControl
+ */
+#define taskENABLE_INTERRUPTS()		portENABLE_INTERRUPTS()
+
+/* Definitions returned by xTaskGetSchedulerState().  taskSCHEDULER_SUSPENDED is
+0 to generate more optimal code when configASSERT() is defined as the constant
+is used in assert() statements. */
+#define taskSCHEDULER_SUSPENDED		( ( BaseType_t ) 0 )
+#define taskSCHEDULER_NOT_STARTED	( ( BaseType_t ) 1 )
+#define taskSCHEDULER_RUNNING		( ( BaseType_t ) 2 )
+
+
+/*-----------------------------------------------------------
+ * TASK CREATION API
+ *----------------------------------------------------------*/
+
+/**
+ * task. h
+ *<pre>
+ BaseType_t xTaskCreate(
+							  TaskFunction_t pvTaskCode,
+							  const char * const pcName,
+							  configSTACK_DEPTH_TYPE usStackDepth,
+							  void *pvParameters,
+							  UBaseType_t uxPriority,
+							  TaskHandle_t *pvCreatedTask
+						  );</pre>
+ *
+ * Create a new task and add it to the list of tasks that are ready to run.
+ *
+ * Internally, within the FreeRTOS implementation, tasks use two blocks of
+ * memory.  The first block is used to hold the task's data structures.  The
+ * second block is used by the task as its stack.  If a task is created using
+ * xTaskCreate() then both blocks of memory are automatically dynamically
+ * allocated inside the xTaskCreate() function.  (see
+ * http://www.freertos.org/a00111.html).  If a task is created using
+ * xTaskCreateStatic() then the application writer must provide the required
+ * memory.  xTaskCreateStatic() therefore allows a task to be created without
+ * using any dynamic memory allocation.
+ *
+ * See xTaskCreateStatic() for a version that does not use any dynamic memory
+ * allocation.
+ *
+ * xTaskCreate() can only be used to create a task that has unrestricted
+ * access to the entire microcontroller memory map.  Systems that include MPU
+ * support can alternatively create an MPU constrained task using
+ * xTaskCreateRestricted().
+ *
+ * @param pvTaskCode Pointer to the task entry function.  Tasks
+ * must be implemented to never return (i.e. continuous loop).
+ *
+ * @param pcName A descriptive name for the task.  This is mainly used to
+ * facilitate debugging.  Max length defined by configMAX_TASK_NAME_LEN - default
+ * is 16.
+ *
+ * @param usStackDepth The size of the task stack specified as the number of
+ * variables the stack can hold - not the number of bytes.  For example, if
+ * the stack is 16 bits wide and usStackDepth is defined as 100, 200 bytes
+ * will be allocated for stack storage.
+ *
+ * @param pvParameters Pointer that will be used as the parameter for the task
+ * being created.
+ *
+ * @param uxPriority The priority at which the task should run.  Systems that
+ * include MPU support can optionally create tasks in a privileged (system)
+ * mode by setting bit portPRIVILEGE_BIT of the priority parameter.  For
+ * example, to create a privileged task at priority 2 the uxPriority parameter
+ * should be set to ( 2 | portPRIVILEGE_BIT ).
+ *
+ * @param pvCreatedTask Used to pass back a handle by which the created task
+ * can be referenced.
+ *
+ * @return pdPASS if the task was successfully created and added to a ready
+ * list, otherwise an error code defined in the file projdefs.h
+ *
+ * Example usage:
+   <pre>
+ // Task to be created.
+ void vTaskCode( void * pvParameters )
+ {
+	 for( ;; )
+	 {
+		 // Task code goes here.
+	 }
+ }
+
+ // Function that creates a task.
+ void vOtherFunction( void )
+ {
+ static uint8_t ucParameterToPass;
+ TaskHandle_t xHandle = NULL;
+
+	 // Create the task, storing the handle.  Note that the passed parameter ucParameterToPass
+	 // must exist for the lifetime of the task, so in this case is declared static.  If it was just an
+	 // an automatic stack variable it might no longer exist, or at least have been corrupted, by the time
+	 // the new task attempts to access it.
+	 xTaskCreate( vTaskCode, "NAME", STACK_SIZE, &ucParameterToPass, tskIDLE_PRIORITY, &xHandle );
+	 configASSERT( xHandle );
+
+	 // Use the handle to delete the task.
+	 if( xHandle != NULL )
+	 {
+	 	vTaskDelete( xHandle );
+	 }
+ }
+   </pre>
+ * \defgroup xTaskCreate xTaskCreate
+ * \ingroup Tasks
+ */
+#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+	BaseType_t xTaskCreate(	TaskFunction_t pxTaskCode,
+							const char * const pcName,	/*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+							const configSTACK_DEPTH_TYPE usStackDepth,
+							void * const pvParameters,
+							UBaseType_t uxPriority,
+							TaskHandle_t * const pxCreatedTask ) PRIVILEGED_FUNCTION;
+#endif
+
+/**
+ * task. h
+ *<pre>
+ TaskHandle_t xTaskCreateStatic( TaskFunction_t pvTaskCode,
+								 const char * const pcName,
+								 uint32_t ulStackDepth,
+								 void *pvParameters,
+								 UBaseType_t uxPriority,
+								 StackType_t *pxStackBuffer,
+								 StaticTask_t *pxTaskBuffer );</pre>
+ *
+ * Create a new task and add it to the list of tasks that are ready to run.
+ *
+ * Internally, within the FreeRTOS implementation, tasks use two blocks of
+ * memory.  The first block is used to hold the task's data structures.  The
+ * second block is used by the task as its stack.  If a task is created using
+ * xTaskCreate() then both blocks of memory are automatically dynamically
+ * allocated inside the xTaskCreate() function.  (see
+ * http://www.freertos.org/a00111.html).  If a task is created using
+ * xTaskCreateStatic() then the application writer must provide the required
+ * memory.  xTaskCreateStatic() therefore allows a task to be created without
+ * using any dynamic memory allocation.
+ *
+ * @param pvTaskCode Pointer to the task entry function.  Tasks
+ * must be implemented to never return (i.e. continuous loop).
+ *
+ * @param pcName A descriptive name for the task.  This is mainly used to
+ * facilitate debugging.  The maximum length of the string is defined by
+ * configMAX_TASK_NAME_LEN in FreeRTOSConfig.h.
+ *
+ * @param ulStackDepth The size of the task stack specified as the number of
+ * variables the stack can hold - not the number of bytes.  For example, if
+ * the stack is 32-bits wide and ulStackDepth is defined as 100 then 400 bytes
+ * will be allocated for stack storage.
+ *
+ * @param pvParameters Pointer that will be used as the parameter for the task
+ * being created.
+ *
+ * @param uxPriority The priority at which the task will run.
+ *
+ * @param pxStackBuffer Must point to a StackType_t array that has at least
+ * ulStackDepth indexes - the array will then be used as the task's stack,
+ * removing the need for the stack to be allocated dynamically.
+ *
+ * @param pxTaskBuffer Must point to a variable of type StaticTask_t, which will
+ * then be used to hold the task's data structures, removing the need for the
+ * memory to be allocated dynamically.
+ *
+ * @return If neither pxStackBuffer or pxTaskBuffer are NULL, then the task will
+ * be created and a handle to the created task is returned.  If either
+ * pxStackBuffer or pxTaskBuffer are NULL then the task will not be created and
+ * NULL is returned.
+ *
+ * Example usage:
+   <pre>
+
+    // Dimensions the buffer that the task being created will use as its stack.
+    // NOTE:  This is the number of words the stack will hold, not the number of
+    // bytes.  For example, if each stack item is 32-bits, and this is set to 100,
+    // then 400 bytes (100 * 32-bits) will be allocated.
+    #define STACK_SIZE 200
+
+    // Structure that will hold the TCB of the task being created.
+    StaticTask_t xTaskBuffer;
+
+    // Buffer that the task being created will use as its stack.  Note this is
+    // an array of StackType_t variables.  The size of StackType_t is dependent on
+    // the RTOS port.
+    StackType_t xStack[ STACK_SIZE ];
+
+    // Function that implements the task being created.
+    void vTaskCode( void * pvParameters )
+    {
+        // The parameter value is expected to be 1 as 1 is passed in the
+        // pvParameters value in the call to xTaskCreateStatic().
+        configASSERT( ( uint32_t ) pvParameters == 1UL );
+
+        for( ;; )
+        {
+            // Task code goes here.
+        }
+    }
+
+    // Function that creates a task.
+    void vOtherFunction( void )
+    {
+        TaskHandle_t xHandle = NULL;
+
+        // Create the task without using any dynamic memory allocation.
+        xHandle = xTaskCreateStatic(
+                      vTaskCode,       // Function that implements the task.
+                      "NAME",          // Text name for the task.
+                      STACK_SIZE,      // Stack size in words, not bytes.
+                      ( void * ) 1,    // Parameter passed into the task.
+                      tskIDLE_PRIORITY,// Priority at which the task is created.
+                      xStack,          // Array to use as the task's stack.
+                      &xTaskBuffer );  // Variable to hold the task's data structure.
+
+        // puxStackBuffer and pxTaskBuffer were not NULL, so the task will have
+        // been created, and xHandle will be the task's handle.  Use the handle
+        // to suspend the task.
+        vTaskSuspend( xHandle );
+    }
+   </pre>
+ * \defgroup xTaskCreateStatic xTaskCreateStatic
+ * \ingroup Tasks
+ */
+#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+	TaskHandle_t xTaskCreateStatic(	TaskFunction_t pxTaskCode,
+									const char * const pcName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+									const uint32_t ulStackDepth,
+									void * const pvParameters,
+									UBaseType_t uxPriority,
+									StackType_t * const puxStackBuffer,
+									StaticTask_t * const pxTaskBuffer ) PRIVILEGED_FUNCTION;
+#endif /* configSUPPORT_STATIC_ALLOCATION */
+
+/**
+ * task. h
+ *<pre>
+ BaseType_t xTaskCreateRestricted( TaskParameters_t *pxTaskDefinition, TaskHandle_t *pxCreatedTask );</pre>
+ *
+ * Only available when configSUPPORT_DYNAMIC_ALLOCATION is set to 1.
+ *
+ * xTaskCreateRestricted() should only be used in systems that include an MPU
+ * implementation.
+ *
+ * Create a new task and add it to the list of tasks that are ready to run.
+ * The function parameters define the memory regions and associated access
+ * permissions allocated to the task.
+ *
+ * See xTaskCreateRestrictedStatic() for a version that does not use any
+ * dynamic memory allocation.
+ *
+ * @param pxTaskDefinition Pointer to a structure that contains a member
+ * for each of the normal xTaskCreate() parameters (see the xTaskCreate() API
+ * documentation) plus an optional stack buffer and the memory region
+ * definitions.
+ *
+ * @param pxCreatedTask Used to pass back a handle by which the created task
+ * can be referenced.
+ *
+ * @return pdPASS if the task was successfully created and added to a ready
+ * list, otherwise an error code defined in the file projdefs.h
+ *
+ * Example usage:
+   <pre>
+// Create an TaskParameters_t structure that defines the task to be created.
+static const TaskParameters_t xCheckTaskParameters =
+{
+	vATask,		// pvTaskCode - the function that implements the task.
+	"ATask",	// pcName - just a text name for the task to assist debugging.
+	100,		// usStackDepth	- the stack size DEFINED IN WORDS.
+	NULL,		// pvParameters - passed into the task function as the function parameters.
+	( 1UL | portPRIVILEGE_BIT ),// uxPriority - task priority, set the portPRIVILEGE_BIT if the task should run in a privileged state.
+	cStackBuffer,// puxStackBuffer - the buffer to be used as the task stack.
+
+	// xRegions - Allocate up to three separate memory regions for access by
+	// the task, with appropriate access permissions.  Different processors have
+	// different memory alignment requirements - refer to the FreeRTOS documentation
+	// for full information.
+	{
+		// Base address					Length	Parameters
+		{ cReadWriteArray,				32,		portMPU_REGION_READ_WRITE },
+		{ cReadOnlyArray,				32,		portMPU_REGION_READ_ONLY },
+		{ cPrivilegedOnlyAccessArray,	128,	portMPU_REGION_PRIVILEGED_READ_WRITE }
+	}
+};
+
+int main( void )
+{
+TaskHandle_t xHandle;
+
+	// Create a task from the const structure defined above.  The task handle
+	// is requested (the second parameter is not NULL) but in this case just for
+	// demonstration purposes as its not actually used.
+	xTaskCreateRestricted( &xRegTest1Parameters, &xHandle );
+
+	// Start the scheduler.
+	vTaskStartScheduler();
+
+	// Will only get here if there was insufficient memory to create the idle
+	// and/or timer task.
+	for( ;; );
+}
+   </pre>
+ * \defgroup xTaskCreateRestricted xTaskCreateRestricted
+ * \ingroup Tasks
+ */
+#if( portUSING_MPU_WRAPPERS == 1 )
+	BaseType_t xTaskCreateRestricted( const TaskParameters_t * const pxTaskDefinition, TaskHandle_t *pxCreatedTask ) PRIVILEGED_FUNCTION;
+#endif
+
+/**
+ * task. h
+ *<pre>
+ BaseType_t xTaskCreateRestrictedStatic( TaskParameters_t *pxTaskDefinition, TaskHandle_t *pxCreatedTask );</pre>
+ *
+ * Only available when configSUPPORT_STATIC_ALLOCATION is set to 1.
+ *
+ * xTaskCreateRestrictedStatic() should only be used in systems that include an
+ * MPU implementation.
+ *
+ * Internally, within the FreeRTOS implementation, tasks use two blocks of
+ * memory.  The first block is used to hold the task's data structures.  The
+ * second block is used by the task as its stack.  If a task is created using
+ * xTaskCreateRestricted() then the stack is provided by the application writer,
+ * and the memory used to hold the task's data structure is automatically
+ * dynamically allocated inside the xTaskCreateRestricted() function.  If a task
+ * is created using xTaskCreateRestrictedStatic() then the application writer
+ * must provide the memory used to hold the task's data structures too.
+ * xTaskCreateRestrictedStatic() therefore allows a memory protected task to be
+ * created without using any dynamic memory allocation.
+ *
+ * @param pxTaskDefinition Pointer to a structure that contains a member
+ * for each of the normal xTaskCreate() parameters (see the xTaskCreate() API
+ * documentation) plus an optional stack buffer and the memory region
+ * definitions.  If configSUPPORT_STATIC_ALLOCATION is set to 1 the structure
+ * contains an additional member, which is used to point to a variable of type
+ * StaticTask_t - which is then used to hold the task's data structure.
+ *
+ * @param pxCreatedTask Used to pass back a handle by which the created task
+ * can be referenced.
+ *
+ * @return pdPASS if the task was successfully created and added to a ready
+ * list, otherwise an error code defined in the file projdefs.h
+ *
+ * Example usage:
+   <pre>
+// Create an TaskParameters_t structure that defines the task to be created.
+// The StaticTask_t variable is only included in the structure when
+// configSUPPORT_STATIC_ALLOCATION is set to 1.  The PRIVILEGED_DATA macro can
+// be used to force the variable into the RTOS kernel's privileged data area.
+static PRIVILEGED_DATA StaticTask_t xTaskBuffer;
+static const TaskParameters_t xCheckTaskParameters =
+{
+	vATask,		// pvTaskCode - the function that implements the task.
+	"ATask",	// pcName - just a text name for the task to assist debugging.
+	100,		// usStackDepth	- the stack size DEFINED IN WORDS.
+	NULL,		// pvParameters - passed into the task function as the function parameters.
+	( 1UL | portPRIVILEGE_BIT ),// uxPriority - task priority, set the portPRIVILEGE_BIT if the task should run in a privileged state.
+	cStackBuffer,// puxStackBuffer - the buffer to be used as the task stack.
+
+	// xRegions - Allocate up to three separate memory regions for access by
+	// the task, with appropriate access permissions.  Different processors have
+	// different memory alignment requirements - refer to the FreeRTOS documentation
+	// for full information.
+	{
+		// Base address					Length	Parameters
+		{ cReadWriteArray,				32,		portMPU_REGION_READ_WRITE },
+		{ cReadOnlyArray,				32,		portMPU_REGION_READ_ONLY },
+		{ cPrivilegedOnlyAccessArray,	128,	portMPU_REGION_PRIVILEGED_READ_WRITE }
+	}
+
+	&xTaskBuffer; // Holds the task's data structure.
+};
+
+int main( void )
+{
+TaskHandle_t xHandle;
+
+	// Create a task from the const structure defined above.  The task handle
+	// is requested (the second parameter is not NULL) but in this case just for
+	// demonstration purposes as its not actually used.
+	xTaskCreateRestricted( &xRegTest1Parameters, &xHandle );
+
+	// Start the scheduler.
+	vTaskStartScheduler();
+
+	// Will only get here if there was insufficient memory to create the idle
+	// and/or timer task.
+	for( ;; );
+}
+   </pre>
+ * \defgroup xTaskCreateRestrictedStatic xTaskCreateRestrictedStatic
+ * \ingroup Tasks
+ */
+#if( ( portUSING_MPU_WRAPPERS == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) )
+	BaseType_t xTaskCreateRestrictedStatic( const TaskParameters_t * const pxTaskDefinition, TaskHandle_t *pxCreatedTask ) PRIVILEGED_FUNCTION;
+#endif
+
+/**
+ * task. h
+ *<pre>
+ void vTaskAllocateMPURegions( TaskHandle_t xTask, const MemoryRegion_t * const pxRegions );</pre>
+ *
+ * Memory regions are assigned to a restricted task when the task is created by
+ * a call to xTaskCreateRestricted().  These regions can be redefined using
+ * vTaskAllocateMPURegions().
+ *
+ * @param xTask The handle of the task being updated.
+ *
+ * @param xRegions A pointer to an MemoryRegion_t structure that contains the
+ * new memory region definitions.
+ *
+ * Example usage:
+   <pre>
+// Define an array of MemoryRegion_t structures that configures an MPU region
+// allowing read/write access for 1024 bytes starting at the beginning of the
+// ucOneKByte array.  The other two of the maximum 3 definable regions are
+// unused so set to zero.
+static const MemoryRegion_t xAltRegions[ portNUM_CONFIGURABLE_REGIONS ] =
+{
+	// Base address		Length		Parameters
+	{ ucOneKByte,		1024,		portMPU_REGION_READ_WRITE },
+	{ 0,				0,			0 },
+	{ 0,				0,			0 }
+};
+
+void vATask( void *pvParameters )
+{
+	// This task was created such that it has access to certain regions of
+	// memory as defined by the MPU configuration.  At some point it is
+	// desired that these MPU regions are replaced with that defined in the
+	// xAltRegions const struct above.  Use a call to vTaskAllocateMPURegions()
+	// for this purpose.  NULL is used as the task handle to indicate that this
+	// function should modify the MPU regions of the calling task.
+	vTaskAllocateMPURegions( NULL, xAltRegions );
+
+	// Now the task can continue its function, but from this point on can only
+	// access its stack and the ucOneKByte array (unless any other statically
+	// defined or shared regions have been declared elsewhere).
+}
+   </pre>
+ * \defgroup xTaskCreateRestricted xTaskCreateRestricted
+ * \ingroup Tasks
+ */
+void vTaskAllocateMPURegions( TaskHandle_t xTask, const MemoryRegion_t * const pxRegions ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * <pre>void vTaskDelete( TaskHandle_t xTask );</pre>
+ *
+ * INCLUDE_vTaskDelete must be defined as 1 for this function to be available.
+ * See the configuration section for more information.
+ *
+ * Remove a task from the RTOS real time kernel's management.  The task being
+ * deleted will be removed from all ready, blocked, suspended and event lists.
+ *
+ * NOTE:  The idle task is responsible for freeing the kernel allocated
+ * memory from tasks that have been deleted.  It is therefore important that
+ * the idle task is not starved of microcontroller processing time if your
+ * application makes any calls to vTaskDelete ().  Memory allocated by the
+ * task code is not automatically freed, and should be freed before the task
+ * is deleted.
+ *
+ * See the demo application file death.c for sample code that utilises
+ * vTaskDelete ().
+ *
+ * @param xTask The handle of the task to be deleted.  Passing NULL will
+ * cause the calling task to be deleted.
+ *
+ * Example usage:
+   <pre>
+ void vOtherFunction( void )
+ {
+ TaskHandle_t xHandle;
+
+	 // Create the task, storing the handle.
+	 xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle );
+
+	 // Use the handle to delete the task.
+	 vTaskDelete( xHandle );
+ }
+   </pre>
+ * \defgroup vTaskDelete vTaskDelete
+ * \ingroup Tasks
+ */
+void vTaskDelete( TaskHandle_t xTaskToDelete ) PRIVILEGED_FUNCTION;
+
+/*-----------------------------------------------------------
+ * TASK CONTROL API
+ *----------------------------------------------------------*/
+
+/**
+ * task. h
+ * <pre>void vTaskDelay( const TickType_t xTicksToDelay );</pre>
+ *
+ * Delay a task for a given number of ticks.  The actual time that the
+ * task remains blocked depends on the tick rate.  The constant
+ * portTICK_PERIOD_MS can be used to calculate real time from the tick
+ * rate - with the resolution of one tick period.
+ *
+ * INCLUDE_vTaskDelay must be defined as 1 for this function to be available.
+ * See the configuration section for more information.
+ *
+ *
+ * vTaskDelay() specifies a time at which the task wishes to unblock relative to
+ * the time at which vTaskDelay() is called.  For example, specifying a block
+ * period of 100 ticks will cause the task to unblock 100 ticks after
+ * vTaskDelay() is called.  vTaskDelay() does not therefore provide a good method
+ * of controlling the frequency of a periodic task as the path taken through the
+ * code, as well as other task and interrupt activity, will effect the frequency
+ * at which vTaskDelay() gets called and therefore the time at which the task
+ * next executes.  See vTaskDelayUntil() for an alternative API function designed
+ * to facilitate fixed frequency execution.  It does this by specifying an
+ * absolute time (rather than a relative time) at which the calling task should
+ * unblock.
+ *
+ * @param xTicksToDelay The amount of time, in tick periods, that
+ * the calling task should block.
+ *
+ * Example usage:
+
+ void vTaskFunction( void * pvParameters )
+ {
+ // Block for 500ms.
+ const TickType_t xDelay = 500 / portTICK_PERIOD_MS;
+
+	 for( ;; )
+	 {
+		 // Simply toggle the LED every 500ms, blocking between each toggle.
+		 vToggleLED();
+		 vTaskDelay( xDelay );
+	 }
+ }
+
+ * \defgroup vTaskDelay vTaskDelay
+ * \ingroup TaskCtrl
+ */
+void vTaskDelay( const TickType_t xTicksToDelay ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * <pre>void vTaskDelayUntil( TickType_t *pxPreviousWakeTime, const TickType_t xTimeIncrement );</pre>
+ *
+ * INCLUDE_vTaskDelayUntil must be defined as 1 for this function to be available.
+ * See the configuration section for more information.
+ *
+ * Delay a task until a specified time.  This function can be used by periodic
+ * tasks to ensure a constant execution frequency.
+ *
+ * This function differs from vTaskDelay () in one important aspect:  vTaskDelay () will
+ * cause a task to block for the specified number of ticks from the time vTaskDelay () is
+ * called.  It is therefore difficult to use vTaskDelay () by itself to generate a fixed
+ * execution frequency as the time between a task starting to execute and that task
+ * calling vTaskDelay () may not be fixed [the task may take a different path though the
+ * code between calls, or may get interrupted or preempted a different number of times
+ * each time it executes].
+ *
+ * Whereas vTaskDelay () specifies a wake time relative to the time at which the function
+ * is called, vTaskDelayUntil () specifies the absolute (exact) time at which it wishes to
+ * unblock.
+ *
+ * The constant portTICK_PERIOD_MS can be used to calculate real time from the tick
+ * rate - with the resolution of one tick period.
+ *
+ * @param pxPreviousWakeTime Pointer to a variable that holds the time at which the
+ * task was last unblocked.  The variable must be initialised with the current time
+ * prior to its first use (see the example below).  Following this the variable is
+ * automatically updated within vTaskDelayUntil ().
+ *
+ * @param xTimeIncrement The cycle time period.  The task will be unblocked at
+ * time *pxPreviousWakeTime + xTimeIncrement.  Calling vTaskDelayUntil with the
+ * same xTimeIncrement parameter value will cause the task to execute with
+ * a fixed interface period.
+ *
+ * Example usage:
+   <pre>
+ // Perform an action every 10 ticks.
+ void vTaskFunction( void * pvParameters )
+ {
+ TickType_t xLastWakeTime;
+ const TickType_t xFrequency = 10;
+
+	 // Initialise the xLastWakeTime variable with the current time.
+	 xLastWakeTime = xTaskGetTickCount ();
+	 for( ;; )
+	 {
+		 // Wait for the next cycle.
+		 vTaskDelayUntil( &xLastWakeTime, xFrequency );
+
+		 // Perform action here.
+	 }
+ }
+   </pre>
+ * \defgroup vTaskDelayUntil vTaskDelayUntil
+ * \ingroup TaskCtrl
+ */
+void vTaskDelayUntil( TickType_t * const pxPreviousWakeTime, const TickType_t xTimeIncrement ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * <pre>BaseType_t xTaskAbortDelay( TaskHandle_t xTask );</pre>
+ *
+ * INCLUDE_xTaskAbortDelay must be defined as 1 in FreeRTOSConfig.h for this
+ * function to be available.
+ *
+ * A task will enter the Blocked state when it is waiting for an event.  The
+ * event it is waiting for can be a temporal event (waiting for a time), such
+ * as when vTaskDelay() is called, or an event on an object, such as when
+ * xQueueReceive() or ulTaskNotifyTake() is called.  If the handle of a task
+ * that is in the Blocked state is used in a call to xTaskAbortDelay() then the
+ * task will leave the Blocked state, and return from whichever function call
+ * placed the task into the Blocked state.
+ *
+ * There is no 'FromISR' version of this function as an interrupt would need to
+ * know which object a task was blocked on in order to know which actions to
+ * take.  For example, if the task was blocked on a queue the interrupt handler
+ * would then need to know if the queue was locked.
+ *
+ * @param xTask The handle of the task to remove from the Blocked state.
+ *
+ * @return If the task referenced by xTask was not in the Blocked state then
+ * pdFAIL is returned.  Otherwise pdPASS is returned.
+ *
+ * \defgroup xTaskAbortDelay xTaskAbortDelay
+ * \ingroup TaskCtrl
+ */
+BaseType_t xTaskAbortDelay( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * <pre>UBaseType_t uxTaskPriorityGet( const TaskHandle_t xTask );</pre>
+ *
+ * INCLUDE_uxTaskPriorityGet must be defined as 1 for this function to be available.
+ * See the configuration section for more information.
+ *
+ * Obtain the priority of any task.
+ *
+ * @param xTask Handle of the task to be queried.  Passing a NULL
+ * handle results in the priority of the calling task being returned.
+ *
+ * @return The priority of xTask.
+ *
+ * Example usage:
+   <pre>
+ void vAFunction( void )
+ {
+ TaskHandle_t xHandle;
+
+	 // Create a task, storing the handle.
+	 xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle );
+
+	 // ...
+
+	 // Use the handle to obtain the priority of the created task.
+	 // It was created with tskIDLE_PRIORITY, but may have changed
+	 // it itself.
+	 if( uxTaskPriorityGet( xHandle ) != tskIDLE_PRIORITY )
+	 {
+		 // The task has changed it's priority.
+	 }
+
+	 // ...
+
+	 // Is our priority higher than the created task?
+	 if( uxTaskPriorityGet( xHandle ) < uxTaskPriorityGet( NULL ) )
+	 {
+		 // Our priority (obtained using NULL handle) is higher.
+	 }
+ }
+   </pre>
+ * \defgroup uxTaskPriorityGet uxTaskPriorityGet
+ * \ingroup TaskCtrl
+ */
+UBaseType_t uxTaskPriorityGet( const TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * <pre>UBaseType_t uxTaskPriorityGetFromISR( const TaskHandle_t xTask );</pre>
+ *
+ * A version of uxTaskPriorityGet() that can be used from an ISR.
+ */
+UBaseType_t uxTaskPriorityGetFromISR( const TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * <pre>eTaskState eTaskGetState( TaskHandle_t xTask );</pre>
+ *
+ * INCLUDE_eTaskGetState must be defined as 1 for this function to be available.
+ * See the configuration section for more information.
+ *
+ * Obtain the state of any task.  States are encoded by the eTaskState
+ * enumerated type.
+ *
+ * @param xTask Handle of the task to be queried.
+ *
+ * @return The state of xTask at the time the function was called.  Note the
+ * state of the task might change between the function being called, and the
+ * functions return value being tested by the calling task.
+ */
+eTaskState eTaskGetState( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * <pre>void vTaskGetInfo( TaskHandle_t xTask, TaskStatus_t *pxTaskStatus, BaseType_t xGetFreeStackSpace, eTaskState eState );</pre>
+ *
+ * configUSE_TRACE_FACILITY must be defined as 1 for this function to be
+ * available.  See the configuration section for more information.
+ *
+ * Populates a TaskStatus_t structure with information about a task.
+ *
+ * @param xTask Handle of the task being queried.  If xTask is NULL then
+ * information will be returned about the calling task.
+ *
+ * @param pxTaskStatus A pointer to the TaskStatus_t structure that will be
+ * filled with information about the task referenced by the handle passed using
+ * the xTask parameter.
+ *
+ * @xGetFreeStackSpace The TaskStatus_t structure contains a member to report
+ * the stack high water mark of the task being queried.  Calculating the stack
+ * high water mark takes a relatively long time, and can make the system
+ * temporarily unresponsive - so the xGetFreeStackSpace parameter is provided to
+ * allow the high water mark checking to be skipped.  The high watermark value
+ * will only be written to the TaskStatus_t structure if xGetFreeStackSpace is
+ * not set to pdFALSE;
+ *
+ * @param eState The TaskStatus_t structure contains a member to report the
+ * state of the task being queried.  Obtaining the task state is not as fast as
+ * a simple assignment - so the eState parameter is provided to allow the state
+ * information to be omitted from the TaskStatus_t structure.  To obtain state
+ * information then set eState to eInvalid - otherwise the value passed in
+ * eState will be reported as the task state in the TaskStatus_t structure.
+ *
+ * Example usage:
+   <pre>
+ void vAFunction( void )
+ {
+ TaskHandle_t xHandle;
+ TaskStatus_t xTaskDetails;
+
+    // Obtain the handle of a task from its name.
+    xHandle = xTaskGetHandle( "Task_Name" );
+
+    // Check the handle is not NULL.
+    configASSERT( xHandle );
+
+    // Use the handle to obtain further information about the task.
+    vTaskGetInfo( xHandle,
+                  &xTaskDetails,
+                  pdTRUE, // Include the high water mark in xTaskDetails.
+                  eInvalid ); // Include the task state in xTaskDetails.
+ }
+   </pre>
+ * \defgroup vTaskGetInfo vTaskGetInfo
+ * \ingroup TaskCtrl
+ */
+void vTaskGetInfo( TaskHandle_t xTask, TaskStatus_t *pxTaskStatus, BaseType_t xGetFreeStackSpace, eTaskState eState ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * <pre>void vTaskPrioritySet( TaskHandle_t xTask, UBaseType_t uxNewPriority );</pre>
+ *
+ * INCLUDE_vTaskPrioritySet must be defined as 1 for this function to be available.
+ * See the configuration section for more information.
+ *
+ * Set the priority of any task.
+ *
+ * A context switch will occur before the function returns if the priority
+ * being set is higher than the currently executing task.
+ *
+ * @param xTask Handle to the task for which the priority is being set.
+ * Passing a NULL handle results in the priority of the calling task being set.
+ *
+ * @param uxNewPriority The priority to which the task will be set.
+ *
+ * Example usage:
+   <pre>
+ void vAFunction( void )
+ {
+ TaskHandle_t xHandle;
+
+	 // Create a task, storing the handle.
+	 xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle );
+
+	 // ...
+
+	 // Use the handle to raise the priority of the created task.
+	 vTaskPrioritySet( xHandle, tskIDLE_PRIORITY + 1 );
+
+	 // ...
+
+	 // Use a NULL handle to raise our priority to the same value.
+	 vTaskPrioritySet( NULL, tskIDLE_PRIORITY + 1 );
+ }
+   </pre>
+ * \defgroup vTaskPrioritySet vTaskPrioritySet
+ * \ingroup TaskCtrl
+ */
+void vTaskPrioritySet( TaskHandle_t xTask, UBaseType_t uxNewPriority ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * <pre>void vTaskSuspend( TaskHandle_t xTaskToSuspend );</pre>
+ *
+ * INCLUDE_vTaskSuspend must be defined as 1 for this function to be available.
+ * See the configuration section for more information.
+ *
+ * Suspend any task.  When suspended a task will never get any microcontroller
+ * processing time, no matter what its priority.
+ *
+ * Calls to vTaskSuspend are not accumulative -
+ * i.e. calling vTaskSuspend () twice on the same task still only requires one
+ * call to vTaskResume () to ready the suspended task.
+ *
+ * @param xTaskToSuspend Handle to the task being suspended.  Passing a NULL
+ * handle will cause the calling task to be suspended.
+ *
+ * Example usage:
+   <pre>
+ void vAFunction( void )
+ {
+ TaskHandle_t xHandle;
+
+	 // Create a task, storing the handle.
+	 xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle );
+
+	 // ...
+
+	 // Use the handle to suspend the created task.
+	 vTaskSuspend( xHandle );
+
+	 // ...
+
+	 // The created task will not run during this period, unless
+	 // another task calls vTaskResume( xHandle ).
+
+	 //...
+
+
+	 // Suspend ourselves.
+	 vTaskSuspend( NULL );
+
+	 // We cannot get here unless another task calls vTaskResume
+	 // with our handle as the parameter.
+ }
+   </pre>
+ * \defgroup vTaskSuspend vTaskSuspend
+ * \ingroup TaskCtrl
+ */
+void vTaskSuspend( TaskHandle_t xTaskToSuspend ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * <pre>void vTaskResume( TaskHandle_t xTaskToResume );</pre>
+ *
+ * INCLUDE_vTaskSuspend must be defined as 1 for this function to be available.
+ * See the configuration section for more information.
+ *
+ * Resumes a suspended task.
+ *
+ * A task that has been suspended by one or more calls to vTaskSuspend ()
+ * will be made available for running again by a single call to
+ * vTaskResume ().
+ *
+ * @param xTaskToResume Handle to the task being readied.
+ *
+ * Example usage:
+   <pre>
+ void vAFunction( void )
+ {
+ TaskHandle_t xHandle;
+
+	 // Create a task, storing the handle.
+	 xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle );
+
+	 // ...
+
+	 // Use the handle to suspend the created task.
+	 vTaskSuspend( xHandle );
+
+	 // ...
+
+	 // The created task will not run during this period, unless
+	 // another task calls vTaskResume( xHandle ).
+
+	 //...
+
+
+	 // Resume the suspended task ourselves.
+	 vTaskResume( xHandle );
+
+	 // The created task will once again get microcontroller processing
+	 // time in accordance with its priority within the system.
+ }
+   </pre>
+ * \defgroup vTaskResume vTaskResume
+ * \ingroup TaskCtrl
+ */
+void vTaskResume( TaskHandle_t xTaskToResume ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * <pre>void xTaskResumeFromISR( TaskHandle_t xTaskToResume );</pre>
+ *
+ * INCLUDE_xTaskResumeFromISR must be defined as 1 for this function to be
+ * available.  See the configuration section for more information.
+ *
+ * An implementation of vTaskResume() that can be called from within an ISR.
+ *
+ * A task that has been suspended by one or more calls to vTaskSuspend ()
+ * will be made available for running again by a single call to
+ * xTaskResumeFromISR ().
+ *
+ * xTaskResumeFromISR() should not be used to synchronise a task with an
+ * interrupt if there is a chance that the interrupt could arrive prior to the
+ * task being suspended - as this can lead to interrupts being missed. Use of a
+ * semaphore as a synchronisation mechanism would avoid this eventuality.
+ *
+ * @param xTaskToResume Handle to the task being readied.
+ *
+ * @return pdTRUE if resuming the task should result in a context switch,
+ * otherwise pdFALSE. This is used by the ISR to determine if a context switch
+ * may be required following the ISR.
+ *
+ * \defgroup vTaskResumeFromISR vTaskResumeFromISR
+ * \ingroup TaskCtrl
+ */
+BaseType_t xTaskResumeFromISR( TaskHandle_t xTaskToResume ) PRIVILEGED_FUNCTION;
+
+/*-----------------------------------------------------------
+ * SCHEDULER CONTROL
+ *----------------------------------------------------------*/
+
+/**
+ * task. h
+ * <pre>void vTaskStartScheduler( void );</pre>
+ *
+ * Starts the real time kernel tick processing.  After calling the kernel
+ * has control over which tasks are executed and when.
+ *
+ * See the demo application file main.c for an example of creating
+ * tasks and starting the kernel.
+ *
+ * Example usage:
+   <pre>
+ void vAFunction( void )
+ {
+	 // Create at least one task before starting the kernel.
+	 xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, NULL );
+
+	 // Start the real time kernel with preemption.
+	 vTaskStartScheduler ();
+
+	 // Will not get here unless a task calls vTaskEndScheduler ()
+ }
+   </pre>
+ *
+ * \defgroup vTaskStartScheduler vTaskStartScheduler
+ * \ingroup SchedulerControl
+ */
+void vTaskStartScheduler( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * <pre>void vTaskEndScheduler( void );</pre>
+ *
+ * NOTE:  At the time of writing only the x86 real mode port, which runs on a PC
+ * in place of DOS, implements this function.
+ *
+ * Stops the real time kernel tick.  All created tasks will be automatically
+ * deleted and multitasking (either preemptive or cooperative) will
+ * stop.  Execution then resumes from the point where vTaskStartScheduler ()
+ * was called, as if vTaskStartScheduler () had just returned.
+ *
+ * See the demo application file main. c in the demo/PC directory for an
+ * example that uses vTaskEndScheduler ().
+ *
+ * vTaskEndScheduler () requires an exit function to be defined within the
+ * portable layer (see vPortEndScheduler () in port. c for the PC port).  This
+ * performs hardware specific operations such as stopping the kernel tick.
+ *
+ * vTaskEndScheduler () will cause all of the resources allocated by the
+ * kernel to be freed - but will not free resources allocated by application
+ * tasks.
+ *
+ * Example usage:
+   <pre>
+ void vTaskCode( void * pvParameters )
+ {
+	 for( ;; )
+	 {
+		 // Task code goes here.
+
+		 // At some point we want to end the real time kernel processing
+		 // so call ...
+		 vTaskEndScheduler ();
+	 }
+ }
+
+ void vAFunction( void )
+ {
+	 // Create at least one task before starting the kernel.
+	 xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, NULL );
+
+	 // Start the real time kernel with preemption.
+	 vTaskStartScheduler ();
+
+	 // Will only get here when the vTaskCode () task has called
+	 // vTaskEndScheduler ().  When we get here we are back to single task
+	 // execution.
+ }
+   </pre>
+ *
+ * \defgroup vTaskEndScheduler vTaskEndScheduler
+ * \ingroup SchedulerControl
+ */
+void vTaskEndScheduler( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * <pre>void vTaskSuspendAll( void );</pre>
+ *
+ * Suspends the scheduler without disabling interrupts.  Context switches will
+ * not occur while the scheduler is suspended.
+ *
+ * After calling vTaskSuspendAll () the calling task will continue to execute
+ * without risk of being swapped out until a call to xTaskResumeAll () has been
+ * made.
+ *
+ * API functions that have the potential to cause a context switch (for example,
+ * vTaskDelayUntil(), xQueueSend(), etc.) must not be called while the scheduler
+ * is suspended.
+ *
+ * Example usage:
+   <pre>
+ void vTask1( void * pvParameters )
+ {
+	 for( ;; )
+	 {
+		 // Task code goes here.
+
+		 // ...
+
+		 // At some point the task wants to perform a long operation during
+		 // which it does not want to get swapped out.  It cannot use
+		 // taskENTER_CRITICAL ()/taskEXIT_CRITICAL () as the length of the
+		 // operation may cause interrupts to be missed - including the
+		 // ticks.
+
+		 // Prevent the real time kernel swapping out the task.
+		 vTaskSuspendAll ();
+
+		 // Perform the operation here.  There is no need to use critical
+		 // sections as we have all the microcontroller processing time.
+		 // During this time interrupts will still operate and the kernel
+		 // tick count will be maintained.
+
+		 // ...
+
+		 // The operation is complete.  Restart the kernel.
+		 xTaskResumeAll ();
+	 }
+ }
+   </pre>
+ * \defgroup vTaskSuspendAll vTaskSuspendAll
+ * \ingroup SchedulerControl
+ */
+void vTaskSuspendAll( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * <pre>BaseType_t xTaskResumeAll( void );</pre>
+ *
+ * Resumes scheduler activity after it was suspended by a call to
+ * vTaskSuspendAll().
+ *
+ * xTaskResumeAll() only resumes the scheduler.  It does not unsuspend tasks
+ * that were previously suspended by a call to vTaskSuspend().
+ *
+ * @return If resuming the scheduler caused a context switch then pdTRUE is
+ *		  returned, otherwise pdFALSE is returned.
+ *
+ * Example usage:
+   <pre>
+ void vTask1( void * pvParameters )
+ {
+	 for( ;; )
+	 {
+		 // Task code goes here.
+
+		 // ...
+
+		 // At some point the task wants to perform a long operation during
+		 // which it does not want to get swapped out.  It cannot use
+		 // taskENTER_CRITICAL ()/taskEXIT_CRITICAL () as the length of the
+		 // operation may cause interrupts to be missed - including the
+		 // ticks.
+
+		 // Prevent the real time kernel swapping out the task.
+		 vTaskSuspendAll ();
+
+		 // Perform the operation here.  There is no need to use critical
+		 // sections as we have all the microcontroller processing time.
+		 // During this time interrupts will still operate and the real
+		 // time kernel tick count will be maintained.
+
+		 // ...
+
+		 // The operation is complete.  Restart the kernel.  We want to force
+		 // a context switch - but there is no point if resuming the scheduler
+		 // caused a context switch already.
+		 if( !xTaskResumeAll () )
+		 {
+			  taskYIELD ();
+		 }
+	 }
+ }
+   </pre>
+ * \defgroup xTaskResumeAll xTaskResumeAll
+ * \ingroup SchedulerControl
+ */
+BaseType_t xTaskResumeAll( void ) PRIVILEGED_FUNCTION;
+
+/*-----------------------------------------------------------
+ * TASK UTILITIES
+ *----------------------------------------------------------*/
+
+/**
+ * task. h
+ * <PRE>TickType_t xTaskGetTickCount( void );</PRE>
+ *
+ * @return The count of ticks since vTaskStartScheduler was called.
+ *
+ * \defgroup xTaskGetTickCount xTaskGetTickCount
+ * \ingroup TaskUtils
+ */
+TickType_t xTaskGetTickCount( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * <PRE>TickType_t xTaskGetTickCountFromISR( void );</PRE>
+ *
+ * @return The count of ticks since vTaskStartScheduler was called.
+ *
+ * This is a version of xTaskGetTickCount() that is safe to be called from an
+ * ISR - provided that TickType_t is the natural word size of the
+ * microcontroller being used or interrupt nesting is either not supported or
+ * not being used.
+ *
+ * \defgroup xTaskGetTickCountFromISR xTaskGetTickCountFromISR
+ * \ingroup TaskUtils
+ */
+TickType_t xTaskGetTickCountFromISR( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * <PRE>uint16_t uxTaskGetNumberOfTasks( void );</PRE>
+ *
+ * @return The number of tasks that the real time kernel is currently managing.
+ * This includes all ready, blocked and suspended tasks.  A task that
+ * has been deleted but not yet freed by the idle task will also be
+ * included in the count.
+ *
+ * \defgroup uxTaskGetNumberOfTasks uxTaskGetNumberOfTasks
+ * \ingroup TaskUtils
+ */
+UBaseType_t uxTaskGetNumberOfTasks( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * <PRE>char *pcTaskGetName( TaskHandle_t xTaskToQuery );</PRE>
+ *
+ * @return The text (human readable) name of the task referenced by the handle
+ * xTaskToQuery.  A task can query its own name by either passing in its own
+ * handle, or by setting xTaskToQuery to NULL.
+ *
+ * \defgroup pcTaskGetName pcTaskGetName
+ * \ingroup TaskUtils
+ */
+char *pcTaskGetName( TaskHandle_t xTaskToQuery ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+
+/**
+ * task. h
+ * <PRE>TaskHandle_t xTaskGetHandle( const char *pcNameToQuery );</PRE>
+ *
+ * NOTE:  This function takes a relatively long time to complete and should be
+ * used sparingly.
+ *
+ * @return The handle of the task that has the human readable name pcNameToQuery.
+ * NULL is returned if no matching name is found.  INCLUDE_xTaskGetHandle
+ * must be set to 1 in FreeRTOSConfig.h for pcTaskGetHandle() to be available.
+ *
+ * \defgroup pcTaskGetHandle pcTaskGetHandle
+ * \ingroup TaskUtils
+ */
+TaskHandle_t xTaskGetHandle( const char *pcNameToQuery ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+
+/**
+ * task.h
+ * <PRE>UBaseType_t uxTaskGetStackHighWaterMark( TaskHandle_t xTask );</PRE>
+ *
+ * INCLUDE_uxTaskGetStackHighWaterMark must be set to 1 in FreeRTOSConfig.h for
+ * this function to be available.
+ *
+ * Returns the high water mark of the stack associated with xTask.  That is,
+ * the minimum free stack space there has been (in words, so on a 32 bit machine
+ * a value of 1 means 4 bytes) since the task started.  The smaller the returned
+ * number the closer the task has come to overflowing its stack.
+ *
+ * uxTaskGetStackHighWaterMark() and uxTaskGetStackHighWaterMark2() are the
+ * same except for their return type.  Using configSTACK_DEPTH_TYPE allows the
+ * user to determine the return type.  It gets around the problem of the value
+ * overflowing on 8-bit types without breaking backward compatibility for
+ * applications that expect an 8-bit return type.
+ *
+ * @param xTask Handle of the task associated with the stack to be checked.
+ * Set xTask to NULL to check the stack of the calling task.
+ *
+ * @return The smallest amount of free stack space there has been (in words, so
+ * actual spaces on the stack rather than bytes) since the task referenced by
+ * xTask was created.
+ */
+UBaseType_t uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
+
+/**
+ * task.h
+ * <PRE>configSTACK_DEPTH_TYPE uxTaskGetStackHighWaterMark2( TaskHandle_t xTask );</PRE>
+ *
+ * INCLUDE_uxTaskGetStackHighWaterMark2 must be set to 1 in FreeRTOSConfig.h for
+ * this function to be available.
+ *
+ * Returns the high water mark of the stack associated with xTask.  That is,
+ * the minimum free stack space there has been (in words, so on a 32 bit machine
+ * a value of 1 means 4 bytes) since the task started.  The smaller the returned
+ * number the closer the task has come to overflowing its stack.
+ *
+ * uxTaskGetStackHighWaterMark() and uxTaskGetStackHighWaterMark2() are the
+ * same except for their return type.  Using configSTACK_DEPTH_TYPE allows the
+ * user to determine the return type.  It gets around the problem of the value
+ * overflowing on 8-bit types without breaking backward compatibility for
+ * applications that expect an 8-bit return type.
+ *
+ * @param xTask Handle of the task associated with the stack to be checked.
+ * Set xTask to NULL to check the stack of the calling task.
+ *
+ * @return The smallest amount of free stack space there has been (in words, so
+ * actual spaces on the stack rather than bytes) since the task referenced by
+ * xTask was created.
+ */
+configSTACK_DEPTH_TYPE uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
+
+/* When using trace macros it is sometimes necessary to include task.h before
+FreeRTOS.h.  When this is done TaskHookFunction_t will not yet have been defined,
+so the following two prototypes will cause a compilation error.  This can be
+fixed by simply guarding against the inclusion of these two prototypes unless
+they are explicitly required by the configUSE_APPLICATION_TASK_TAG configuration
+constant. */
+#ifdef configUSE_APPLICATION_TASK_TAG
+	#if configUSE_APPLICATION_TASK_TAG == 1
+		/**
+		 * task.h
+		 * <pre>void vTaskSetApplicationTaskTag( TaskHandle_t xTask, TaskHookFunction_t pxHookFunction );</pre>
+		 *
+		 * Sets pxHookFunction to be the task hook function used by the task xTask.
+		 * Passing xTask as NULL has the effect of setting the calling tasks hook
+		 * function.
+		 */
+		void vTaskSetApplicationTaskTag( TaskHandle_t xTask, TaskHookFunction_t pxHookFunction ) PRIVILEGED_FUNCTION;
+
+		/**
+		 * task.h
+		 * <pre>void xTaskGetApplicationTaskTag( TaskHandle_t xTask );</pre>
+		 *
+		 * Returns the pxHookFunction value assigned to the task xTask.  Do not
+		 * call from an interrupt service routine - call
+		 * xTaskGetApplicationTaskTagFromISR() instead.
+		 */
+		TaskHookFunction_t xTaskGetApplicationTaskTag( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
+
+		/**
+		 * task.h
+		 * <pre>void xTaskGetApplicationTaskTagFromISR( TaskHandle_t xTask );</pre>
+		 *
+		 * Returns the pxHookFunction value assigned to the task xTask.  Can
+		 * be called from an interrupt service routine.
+		 */
+		TaskHookFunction_t xTaskGetApplicationTaskTagFromISR( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
+	#endif /* configUSE_APPLICATION_TASK_TAG ==1 */
+#endif /* ifdef configUSE_APPLICATION_TASK_TAG */
+
+#if( configNUM_THREAD_LOCAL_STORAGE_POINTERS > 0 )
+
+	/* Each task contains an array of pointers that is dimensioned by the
+	configNUM_THREAD_LOCAL_STORAGE_POINTERS setting in FreeRTOSConfig.h.  The
+	kernel does not use the pointers itself, so the application writer can use
+	the pointers for any purpose they wish.  The following two functions are
+	used to set and query a pointer respectively. */
+	void vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet, BaseType_t xIndex, void *pvValue ) PRIVILEGED_FUNCTION;
+	void *pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery, BaseType_t xIndex ) PRIVILEGED_FUNCTION;
+
+#endif
+
+/**
+ * task.h
+ * <pre>BaseType_t xTaskCallApplicationTaskHook( TaskHandle_t xTask, void *pvParameter );</pre>
+ *
+ * Calls the hook function associated with xTask.  Passing xTask as NULL has
+ * the effect of calling the Running tasks (the calling task) hook function.
+ *
+ * pvParameter is passed to the hook function for the task to interpret as it
+ * wants.  The return value is the value returned by the task hook function
+ * registered by the user.
+ */
+BaseType_t xTaskCallApplicationTaskHook( TaskHandle_t xTask, void *pvParameter ) PRIVILEGED_FUNCTION;
+
+/**
+ * xTaskGetIdleTaskHandle() is only available if
+ * INCLUDE_xTaskGetIdleTaskHandle is set to 1 in FreeRTOSConfig.h.
+ *
+ * Simply returns the handle of the idle task.  It is not valid to call
+ * xTaskGetIdleTaskHandle() before the scheduler has been started.
+ */
+TaskHandle_t xTaskGetIdleTaskHandle( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * configUSE_TRACE_FACILITY must be defined as 1 in FreeRTOSConfig.h for
+ * uxTaskGetSystemState() to be available.
+ *
+ * uxTaskGetSystemState() populates an TaskStatus_t structure for each task in
+ * the system.  TaskStatus_t structures contain, among other things, members
+ * for the task handle, task name, task priority, task state, and total amount
+ * of run time consumed by the task.  See the TaskStatus_t structure
+ * definition in this file for the full member list.
+ *
+ * NOTE:  This function is intended for debugging use only as its use results in
+ * the scheduler remaining suspended for an extended period.
+ *
+ * @param pxTaskStatusArray A pointer to an array of TaskStatus_t structures.
+ * The array must contain at least one TaskStatus_t structure for each task
+ * that is under the control of the RTOS.  The number of tasks under the control
+ * of the RTOS can be determined using the uxTaskGetNumberOfTasks() API function.
+ *
+ * @param uxArraySize The size of the array pointed to by the pxTaskStatusArray
+ * parameter.  The size is specified as the number of indexes in the array, or
+ * the number of TaskStatus_t structures contained in the array, not by the
+ * number of bytes in the array.
+ *
+ * @param pulTotalRunTime If configGENERATE_RUN_TIME_STATS is set to 1 in
+ * FreeRTOSConfig.h then *pulTotalRunTime is set by uxTaskGetSystemState() to the
+ * total run time (as defined by the run time stats clock, see
+ * http://www.freertos.org/rtos-run-time-stats.html) since the target booted.
+ * pulTotalRunTime can be set to NULL to omit the total run time information.
+ *
+ * @return The number of TaskStatus_t structures that were populated by
+ * uxTaskGetSystemState().  This should equal the number returned by the
+ * uxTaskGetNumberOfTasks() API function, but will be zero if the value passed
+ * in the uxArraySize parameter was too small.
+ *
+ * Example usage:
+   <pre>
+    // This example demonstrates how a human readable table of run time stats
+	// information is generated from raw data provided by uxTaskGetSystemState().
+	// The human readable table is written to pcWriteBuffer
+	void vTaskGetRunTimeStats( char *pcWriteBuffer )
+	{
+	TaskStatus_t *pxTaskStatusArray;
+	volatile UBaseType_t uxArraySize, x;
+	uint32_t ulTotalRunTime, ulStatsAsPercentage;
+
+		// Make sure the write buffer does not contain a string.
+		*pcWriteBuffer = 0x00;
+
+		// Take a snapshot of the number of tasks in case it changes while this
+		// function is executing.
+		uxArraySize = uxTaskGetNumberOfTasks();
+
+		// Allocate a TaskStatus_t structure for each task.  An array could be
+		// allocated statically at compile time.
+		pxTaskStatusArray = pvPortMalloc( uxArraySize * sizeof( TaskStatus_t ) );
+
+		if( pxTaskStatusArray != NULL )
+		{
+			// Generate raw status information about each task.
+			uxArraySize = uxTaskGetSystemState( pxTaskStatusArray, uxArraySize, &ulTotalRunTime );
+
+			// For percentage calculations.
+			ulTotalRunTime /= 100UL;
+
+			// Avoid divide by zero errors.
+			if( ulTotalRunTime > 0 )
+			{
+				// For each populated position in the pxTaskStatusArray array,
+				// format the raw data as human readable ASCII data
+				for( x = 0; x < uxArraySize; x++ )
+				{
+					// What percentage of the total run time has the task used?
+					// This will always be rounded down to the nearest integer.
+					// ulTotalRunTimeDiv100 has already been divided by 100.
+					ulStatsAsPercentage = pxTaskStatusArray[ x ].ulRunTimeCounter / ulTotalRunTime;
+
+					if( ulStatsAsPercentage > 0UL )
+					{
+						sprintf( pcWriteBuffer, "%s\t\t%lu\t\t%lu%%\r\n", pxTaskStatusArray[ x ].pcTaskName, pxTaskStatusArray[ x ].ulRunTimeCounter, ulStatsAsPercentage );
+					}
+					else
+					{
+						// If the percentage is zero here then the task has
+						// consumed less than 1% of the total run time.
+						sprintf( pcWriteBuffer, "%s\t\t%lu\t\t<1%%\r\n", pxTaskStatusArray[ x ].pcTaskName, pxTaskStatusArray[ x ].ulRunTimeCounter );
+					}
+
+					pcWriteBuffer += strlen( ( char * ) pcWriteBuffer );
+				}
+			}
+
+			// The array is no longer needed, free the memory it consumes.
+			vPortFree( pxTaskStatusArray );
+		}
+	}
+	</pre>
+ */
+UBaseType_t uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray, const UBaseType_t uxArraySize, uint32_t * const pulTotalRunTime ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * <PRE>void vTaskList( char *pcWriteBuffer );</PRE>
+ *
+ * configUSE_TRACE_FACILITY and configUSE_STATS_FORMATTING_FUNCTIONS must
+ * both be defined as 1 for this function to be available.  See the
+ * configuration section of the FreeRTOS.org website for more information.
+ *
+ * NOTE 1: This function will disable interrupts for its duration.  It is
+ * not intended for normal application runtime use but as a debug aid.
+ *
+ * Lists all the current tasks, along with their current state and stack
+ * usage high water mark.
+ *
+ * Tasks are reported as blocked ('B'), ready ('R'), deleted ('D') or
+ * suspended ('S').
+ *
+ * PLEASE NOTE:
+ *
+ * This function is provided for convenience only, and is used by many of the
+ * demo applications.  Do not consider it to be part of the scheduler.
+ *
+ * vTaskList() calls uxTaskGetSystemState(), then formats part of the
+ * uxTaskGetSystemState() output into a human readable table that displays task
+ * names, states and stack usage.
+ *
+ * vTaskList() has a dependency on the sprintf() C library function that might
+ * bloat the code size, use a lot of stack, and provide different results on
+ * different platforms.  An alternative, tiny, third party, and limited
+ * functionality implementation of sprintf() is provided in many of the
+ * FreeRTOS/Demo sub-directories in a file called printf-stdarg.c (note
+ * printf-stdarg.c does not provide a full snprintf() implementation!).
+ *
+ * It is recommended that production systems call uxTaskGetSystemState()
+ * directly to get access to raw stats data, rather than indirectly through a
+ * call to vTaskList().
+ *
+ * @param pcWriteBuffer A buffer into which the above mentioned details
+ * will be written, in ASCII form.  This buffer is assumed to be large
+ * enough to contain the generated report.  Approximately 40 bytes per
+ * task should be sufficient.
+ *
+ * \defgroup vTaskList vTaskList
+ * \ingroup TaskUtils
+ */
+void vTaskList( char * pcWriteBuffer ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+
+/**
+ * task. h
+ * <PRE>void vTaskGetRunTimeStats( char *pcWriteBuffer );</PRE>
+ *
+ * configGENERATE_RUN_TIME_STATS and configUSE_STATS_FORMATTING_FUNCTIONS
+ * must both be defined as 1 for this function to be available.  The application
+ * must also then provide definitions for
+ * portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() and portGET_RUN_TIME_COUNTER_VALUE()
+ * to configure a peripheral timer/counter and return the timers current count
+ * value respectively.  The counter should be at least 10 times the frequency of
+ * the tick count.
+ *
+ * NOTE 1: This function will disable interrupts for its duration.  It is
+ * not intended for normal application runtime use but as a debug aid.
+ *
+ * Setting configGENERATE_RUN_TIME_STATS to 1 will result in a total
+ * accumulated execution time being stored for each task.  The resolution
+ * of the accumulated time value depends on the frequency of the timer
+ * configured by the portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() macro.
+ * Calling vTaskGetRunTimeStats() writes the total execution time of each
+ * task into a buffer, both as an absolute count value and as a percentage
+ * of the total system execution time.
+ *
+ * NOTE 2:
+ *
+ * This function is provided for convenience only, and is used by many of the
+ * demo applications.  Do not consider it to be part of the scheduler.
+ *
+ * vTaskGetRunTimeStats() calls uxTaskGetSystemState(), then formats part of the
+ * uxTaskGetSystemState() output into a human readable table that displays the
+ * amount of time each task has spent in the Running state in both absolute and
+ * percentage terms.
+ *
+ * vTaskGetRunTimeStats() has a dependency on the sprintf() C library function
+ * that might bloat the code size, use a lot of stack, and provide different
+ * results on different platforms.  An alternative, tiny, third party, and
+ * limited functionality implementation of sprintf() is provided in many of the
+ * FreeRTOS/Demo sub-directories in a file called printf-stdarg.c (note
+ * printf-stdarg.c does not provide a full snprintf() implementation!).
+ *
+ * It is recommended that production systems call uxTaskGetSystemState() directly
+ * to get access to raw stats data, rather than indirectly through a call to
+ * vTaskGetRunTimeStats().
+ *
+ * @param pcWriteBuffer A buffer into which the execution times will be
+ * written, in ASCII form.  This buffer is assumed to be large enough to
+ * contain the generated report.  Approximately 40 bytes per task should
+ * be sufficient.
+ *
+ * \defgroup vTaskGetRunTimeStats vTaskGetRunTimeStats
+ * \ingroup TaskUtils
+ */
+void vTaskGetRunTimeStats( char *pcWriteBuffer ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+
+/**
+* task. h
+* <PRE>uint32_t ulTaskGetIdleRunTimeCounter( void );</PRE>
+*
+* configGENERATE_RUN_TIME_STATS and configUSE_STATS_FORMATTING_FUNCTIONS
+* must both be defined as 1 for this function to be available.  The application
+* must also then provide definitions for
+* portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() and portGET_RUN_TIME_COUNTER_VALUE()
+* to configure a peripheral timer/counter and return the timers current count
+* value respectively.  The counter should be at least 10 times the frequency of
+* the tick count.
+*
+* Setting configGENERATE_RUN_TIME_STATS to 1 will result in a total
+* accumulated execution time being stored for each task.  The resolution
+* of the accumulated time value depends on the frequency of the timer
+* configured by the portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() macro.
+* While uxTaskGetSystemState() and vTaskGetRunTimeStats() writes the total
+* execution time of each task into a buffer, ulTaskGetIdleRunTimeCounter()
+* returns the total execution time of just the idle task.
+*
+* @return The total run time of the idle task.  This is the amount of time the
+* idle task has actually been executing.  The unit of time is dependent on the
+* frequency configured using the portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() and
+* portGET_RUN_TIME_COUNTER_VALUE() macros.
+*
+* \defgroup ulTaskGetIdleRunTimeCounter ulTaskGetIdleRunTimeCounter
+* \ingroup TaskUtils
+*/
+uint32_t ulTaskGetIdleRunTimeCounter( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * <PRE>BaseType_t xTaskNotify( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction );</PRE>
+ *
+ * configUSE_TASK_NOTIFICATIONS must be undefined or defined as 1 for this
+ * function to be available.
+ *
+ * When configUSE_TASK_NOTIFICATIONS is set to one each task has its own private
+ * "notification value", which is a 32-bit unsigned integer (uint32_t).
+ *
+ * Events can be sent to a task using an intermediary object.  Examples of such
+ * objects are queues, semaphores, mutexes and event groups.  Task notifications
+ * are a method of sending an event directly to a task without the need for such
+ * an intermediary object.
+ *
+ * A notification sent to a task can optionally perform an action, such as
+ * update, overwrite or increment the task's notification value.  In that way
+ * task notifications can be used to send data to a task, or be used as light
+ * weight and fast binary or counting semaphores.
+ *
+ * A notification sent to a task will remain pending until it is cleared by the
+ * task calling xTaskNotifyWait() or ulTaskNotifyTake().  If the task was
+ * already in the Blocked state to wait for a notification when the notification
+ * arrives then the task will automatically be removed from the Blocked state
+ * (unblocked) and the notification cleared.
+ *
+ * A task can use xTaskNotifyWait() to [optionally] block to wait for a
+ * notification to be pending, or ulTaskNotifyTake() to [optionally] block
+ * to wait for its notification value to have a non-zero value.  The task does
+ * not consume any CPU time while it is in the Blocked state.
+ *
+ * See http://www.FreeRTOS.org/RTOS-task-notifications.html for details.
+ *
+ * @param xTaskToNotify The handle of the task being notified.  The handle to a
+ * task can be returned from the xTaskCreate() API function used to create the
+ * task, and the handle of the currently running task can be obtained by calling
+ * xTaskGetCurrentTaskHandle().
+ *
+ * @param ulValue Data that can be sent with the notification.  How the data is
+ * used depends on the value of the eAction parameter.
+ *
+ * @param eAction Specifies how the notification updates the task's notification
+ * value, if at all.  Valid values for eAction are as follows:
+ *
+ * eSetBits -
+ * The task's notification value is bitwise ORed with ulValue.  xTaskNofify()
+ * always returns pdPASS in this case.
+ *
+ * eIncrement -
+ * The task's notification value is incremented.  ulValue is not used and
+ * xTaskNotify() always returns pdPASS in this case.
+ *
+ * eSetValueWithOverwrite -
+ * The task's notification value is set to the value of ulValue, even if the
+ * task being notified had not yet processed the previous notification (the
+ * task already had a notification pending).  xTaskNotify() always returns
+ * pdPASS in this case.
+ *
+ * eSetValueWithoutOverwrite -
+ * If the task being notified did not already have a notification pending then
+ * the task's notification value is set to ulValue and xTaskNotify() will
+ * return pdPASS.  If the task being notified already had a notification
+ * pending then no action is performed and pdFAIL is returned.
+ *
+ * eNoAction -
+ * The task receives a notification without its notification value being
+ * updated.  ulValue is not used and xTaskNotify() always returns pdPASS in
+ * this case.
+ *
+ *  pulPreviousNotificationValue -
+ *  Can be used to pass out the subject task's notification value before any
+ *  bits are modified by the notify function.
+ *
+ * @return Dependent on the value of eAction.  See the description of the
+ * eAction parameter.
+ *
+ * \defgroup xTaskNotify xTaskNotify
+ * \ingroup TaskNotifications
+ */
+BaseType_t xTaskGenericNotify( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction, uint32_t *pulPreviousNotificationValue ) PRIVILEGED_FUNCTION;
+#define xTaskNotify( xTaskToNotify, ulValue, eAction ) xTaskGenericNotify( ( xTaskToNotify ), ( ulValue ), ( eAction ), NULL )
+#define xTaskNotifyAndQuery( xTaskToNotify, ulValue, eAction, pulPreviousNotifyValue ) xTaskGenericNotify( ( xTaskToNotify ), ( ulValue ), ( eAction ), ( pulPreviousNotifyValue ) )
+
+/**
+ * task. h
+ * <PRE>BaseType_t xTaskNotifyFromISR( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction, BaseType_t *pxHigherPriorityTaskWoken );</PRE>
+ *
+ * configUSE_TASK_NOTIFICATIONS must be undefined or defined as 1 for this
+ * function to be available.
+ *
+ * When configUSE_TASK_NOTIFICATIONS is set to one each task has its own private
+ * "notification value", which is a 32-bit unsigned integer (uint32_t).
+ *
+ * A version of xTaskNotify() that can be used from an interrupt service routine
+ * (ISR).
+ *
+ * Events can be sent to a task using an intermediary object.  Examples of such
+ * objects are queues, semaphores, mutexes and event groups.  Task notifications
+ * are a method of sending an event directly to a task without the need for such
+ * an intermediary object.
+ *
+ * A notification sent to a task can optionally perform an action, such as
+ * update, overwrite or increment the task's notification value.  In that way
+ * task notifications can be used to send data to a task, or be used as light
+ * weight and fast binary or counting semaphores.
+ *
+ * A notification sent to a task will remain pending until it is cleared by the
+ * task calling xTaskNotifyWait() or ulTaskNotifyTake().  If the task was
+ * already in the Blocked state to wait for a notification when the notification
+ * arrives then the task will automatically be removed from the Blocked state
+ * (unblocked) and the notification cleared.
+ *
+ * A task can use xTaskNotifyWait() to [optionally] block to wait for a
+ * notification to be pending, or ulTaskNotifyTake() to [optionally] block
+ * to wait for its notification value to have a non-zero value.  The task does
+ * not consume any CPU time while it is in the Blocked state.
+ *
+ * See http://www.FreeRTOS.org/RTOS-task-notifications.html for details.
+ *
+ * @param xTaskToNotify The handle of the task being notified.  The handle to a
+ * task can be returned from the xTaskCreate() API function used to create the
+ * task, and the handle of the currently running task can be obtained by calling
+ * xTaskGetCurrentTaskHandle().
+ *
+ * @param ulValue Data that can be sent with the notification.  How the data is
+ * used depends on the value of the eAction parameter.
+ *
+ * @param eAction Specifies how the notification updates the task's notification
+ * value, if at all.  Valid values for eAction are as follows:
+ *
+ * eSetBits -
+ * The task's notification value is bitwise ORed with ulValue.  xTaskNofify()
+ * always returns pdPASS in this case.
+ *
+ * eIncrement -
+ * The task's notification value is incremented.  ulValue is not used and
+ * xTaskNotify() always returns pdPASS in this case.
+ *
+ * eSetValueWithOverwrite -
+ * The task's notification value is set to the value of ulValue, even if the
+ * task being notified had not yet processed the previous notification (the
+ * task already had a notification pending).  xTaskNotify() always returns
+ * pdPASS in this case.
+ *
+ * eSetValueWithoutOverwrite -
+ * If the task being notified did not already have a notification pending then
+ * the task's notification value is set to ulValue and xTaskNotify() will
+ * return pdPASS.  If the task being notified already had a notification
+ * pending then no action is performed and pdFAIL is returned.
+ *
+ * eNoAction -
+ * The task receives a notification without its notification value being
+ * updated.  ulValue is not used and xTaskNotify() always returns pdPASS in
+ * this case.
+ *
+ * @param pxHigherPriorityTaskWoken  xTaskNotifyFromISR() will set
+ * *pxHigherPriorityTaskWoken to pdTRUE if sending the notification caused the
+ * task to which the notification was sent to leave the Blocked state, and the
+ * unblocked task has a priority higher than the currently running task.  If
+ * xTaskNotifyFromISR() sets this value to pdTRUE then a context switch should
+ * be requested before the interrupt is exited.  How a context switch is
+ * requested from an ISR is dependent on the port - see the documentation page
+ * for the port in use.
+ *
+ * @return Dependent on the value of eAction.  See the description of the
+ * eAction parameter.
+ *
+ * \defgroup xTaskNotify xTaskNotify
+ * \ingroup TaskNotifications
+ */
+BaseType_t xTaskGenericNotifyFromISR( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction, uint32_t *pulPreviousNotificationValue, BaseType_t *pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;
+#define xTaskNotifyFromISR( xTaskToNotify, ulValue, eAction, pxHigherPriorityTaskWoken ) xTaskGenericNotifyFromISR( ( xTaskToNotify ), ( ulValue ), ( eAction ), NULL, ( pxHigherPriorityTaskWoken ) )
+#define xTaskNotifyAndQueryFromISR( xTaskToNotify, ulValue, eAction, pulPreviousNotificationValue, pxHigherPriorityTaskWoken ) xTaskGenericNotifyFromISR( ( xTaskToNotify ), ( ulValue ), ( eAction ), ( pulPreviousNotificationValue ), ( pxHigherPriorityTaskWoken ) )
+
+/**
+ * task. h
+ * <PRE>BaseType_t xTaskNotifyWait( uint32_t ulBitsToClearOnEntry, uint32_t ulBitsToClearOnExit, uint32_t *pulNotificationValue, TickType_t xTicksToWait );</pre>
+ *
+ * configUSE_TASK_NOTIFICATIONS must be undefined or defined as 1 for this
+ * function to be available.
+ *
+ * When configUSE_TASK_NOTIFICATIONS is set to one each task has its own private
+ * "notification value", which is a 32-bit unsigned integer (uint32_t).
+ *
+ * Events can be sent to a task using an intermediary object.  Examples of such
+ * objects are queues, semaphores, mutexes and event groups.  Task notifications
+ * are a method of sending an event directly to a task without the need for such
+ * an intermediary object.
+ *
+ * A notification sent to a task can optionally perform an action, such as
+ * update, overwrite or increment the task's notification value.  In that way
+ * task notifications can be used to send data to a task, or be used as light
+ * weight and fast binary or counting semaphores.
+ *
+ * A notification sent to a task will remain pending until it is cleared by the
+ * task calling xTaskNotifyWait() or ulTaskNotifyTake().  If the task was
+ * already in the Blocked state to wait for a notification when the notification
+ * arrives then the task will automatically be removed from the Blocked state
+ * (unblocked) and the notification cleared.
+ *
+ * A task can use xTaskNotifyWait() to [optionally] block to wait for a
+ * notification to be pending, or ulTaskNotifyTake() to [optionally] block
+ * to wait for its notification value to have a non-zero value.  The task does
+ * not consume any CPU time while it is in the Blocked state.
+ *
+ * See http://www.FreeRTOS.org/RTOS-task-notifications.html for details.
+ *
+ * @param ulBitsToClearOnEntry Bits that are set in ulBitsToClearOnEntry value
+ * will be cleared in the calling task's notification value before the task
+ * checks to see if any notifications are pending, and optionally blocks if no
+ * notifications are pending.  Setting ulBitsToClearOnEntry to ULONG_MAX (if
+ * limits.h is included) or 0xffffffffUL (if limits.h is not included) will have
+ * the effect of resetting the task's notification value to 0.  Setting
+ * ulBitsToClearOnEntry to 0 will leave the task's notification value unchanged.
+ *
+ * @param ulBitsToClearOnExit If a notification is pending or received before
+ * the calling task exits the xTaskNotifyWait() function then the task's
+ * notification value (see the xTaskNotify() API function) is passed out using
+ * the pulNotificationValue parameter.  Then any bits that are set in
+ * ulBitsToClearOnExit will be cleared in the task's notification value (note
+ * *pulNotificationValue is set before any bits are cleared).  Setting
+ * ulBitsToClearOnExit to ULONG_MAX (if limits.h is included) or 0xffffffffUL
+ * (if limits.h is not included) will have the effect of resetting the task's
+ * notification value to 0 before the function exits.  Setting
+ * ulBitsToClearOnExit to 0 will leave the task's notification value unchanged
+ * when the function exits (in which case the value passed out in
+ * pulNotificationValue will match the task's notification value).
+ *
+ * @param pulNotificationValue Used to pass the task's notification value out
+ * of the function.  Note the value passed out will not be effected by the
+ * clearing of any bits caused by ulBitsToClearOnExit being non-zero.
+ *
+ * @param xTicksToWait The maximum amount of time that the task should wait in
+ * the Blocked state for a notification to be received, should a notification
+ * not already be pending when xTaskNotifyWait() was called.  The task
+ * will not consume any processing time while it is in the Blocked state.  This
+ * is specified in kernel ticks, the macro pdMS_TO_TICSK( value_in_ms ) can be
+ * used to convert a time specified in milliseconds to a time specified in
+ * ticks.
+ *
+ * @return If a notification was received (including notifications that were
+ * already pending when xTaskNotifyWait was called) then pdPASS is
+ * returned.  Otherwise pdFAIL is returned.
+ *
+ * \defgroup xTaskNotifyWait xTaskNotifyWait
+ * \ingroup TaskNotifications
+ */
+BaseType_t xTaskNotifyWait( uint32_t ulBitsToClearOnEntry, uint32_t ulBitsToClearOnExit, uint32_t *pulNotificationValue, TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * <PRE>BaseType_t xTaskNotifyGive( TaskHandle_t xTaskToNotify );</PRE>
+ *
+ * configUSE_TASK_NOTIFICATIONS must be undefined or defined as 1 for this macro
+ * to be available.
+ *
+ * When configUSE_TASK_NOTIFICATIONS is set to one each task has its own private
+ * "notification value", which is a 32-bit unsigned integer (uint32_t).
+ *
+ * Events can be sent to a task using an intermediary object.  Examples of such
+ * objects are queues, semaphores, mutexes and event groups.  Task notifications
+ * are a method of sending an event directly to a task without the need for such
+ * an intermediary object.
+ *
+ * A notification sent to a task can optionally perform an action, such as
+ * update, overwrite or increment the task's notification value.  In that way
+ * task notifications can be used to send data to a task, or be used as light
+ * weight and fast binary or counting semaphores.
+ *
+ * xTaskNotifyGive() is a helper macro intended for use when task notifications
+ * are used as light weight and faster binary or counting semaphore equivalents.
+ * Actual FreeRTOS semaphores are given using the xSemaphoreGive() API function,
+ * the equivalent action that instead uses a task notification is
+ * xTaskNotifyGive().
+ *
+ * When task notifications are being used as a binary or counting semaphore
+ * equivalent then the task being notified should wait for the notification
+ * using the ulTaskNotificationTake() API function rather than the
+ * xTaskNotifyWait() API function.
+ *
+ * See http://www.FreeRTOS.org/RTOS-task-notifications.html for more details.
+ *
+ * @param xTaskToNotify The handle of the task being notified.  The handle to a
+ * task can be returned from the xTaskCreate() API function used to create the
+ * task, and the handle of the currently running task can be obtained by calling
+ * xTaskGetCurrentTaskHandle().
+ *
+ * @return xTaskNotifyGive() is a macro that calls xTaskNotify() with the
+ * eAction parameter set to eIncrement - so pdPASS is always returned.
+ *
+ * \defgroup xTaskNotifyGive xTaskNotifyGive
+ * \ingroup TaskNotifications
+ */
+#define xTaskNotifyGive( xTaskToNotify ) xTaskGenericNotify( ( xTaskToNotify ), ( 0 ), eIncrement, NULL )
+
+/**
+ * task. h
+ * <PRE>void vTaskNotifyGiveFromISR( TaskHandle_t xTaskHandle, BaseType_t *pxHigherPriorityTaskWoken );
+ *
+ * configUSE_TASK_NOTIFICATIONS must be undefined or defined as 1 for this macro
+ * to be available.
+ *
+ * When configUSE_TASK_NOTIFICATIONS is set to one each task has its own private
+ * "notification value", which is a 32-bit unsigned integer (uint32_t).
+ *
+ * A version of xTaskNotifyGive() that can be called from an interrupt service
+ * routine (ISR).
+ *
+ * Events can be sent to a task using an intermediary object.  Examples of such
+ * objects are queues, semaphores, mutexes and event groups.  Task notifications
+ * are a method of sending an event directly to a task without the need for such
+ * an intermediary object.
+ *
+ * A notification sent to a task can optionally perform an action, such as
+ * update, overwrite or increment the task's notification value.  In that way
+ * task notifications can be used to send data to a task, or be used as light
+ * weight and fast binary or counting semaphores.
+ *
+ * vTaskNotifyGiveFromISR() is intended for use when task notifications are
+ * used as light weight and faster binary or counting semaphore equivalents.
+ * Actual FreeRTOS semaphores are given from an ISR using the
+ * xSemaphoreGiveFromISR() API function, the equivalent action that instead uses
+ * a task notification is vTaskNotifyGiveFromISR().
+ *
+ * When task notifications are being used as a binary or counting semaphore
+ * equivalent then the task being notified should wait for the notification
+ * using the ulTaskNotificationTake() API function rather than the
+ * xTaskNotifyWait() API function.
+ *
+ * See http://www.FreeRTOS.org/RTOS-task-notifications.html for more details.
+ *
+ * @param xTaskToNotify The handle of the task being notified.  The handle to a
+ * task can be returned from the xTaskCreate() API function used to create the
+ * task, and the handle of the currently running task can be obtained by calling
+ * xTaskGetCurrentTaskHandle().
+ *
+ * @param pxHigherPriorityTaskWoken  vTaskNotifyGiveFromISR() will set
+ * *pxHigherPriorityTaskWoken to pdTRUE if sending the notification caused the
+ * task to which the notification was sent to leave the Blocked state, and the
+ * unblocked task has a priority higher than the currently running task.  If
+ * vTaskNotifyGiveFromISR() sets this value to pdTRUE then a context switch
+ * should be requested before the interrupt is exited.  How a context switch is
+ * requested from an ISR is dependent on the port - see the documentation page
+ * for the port in use.
+ *
+ * \defgroup xTaskNotifyWait xTaskNotifyWait
+ * \ingroup TaskNotifications
+ */
+void vTaskNotifyGiveFromISR( TaskHandle_t xTaskToNotify, BaseType_t *pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * <PRE>uint32_t ulTaskNotifyTake( BaseType_t xClearCountOnExit, TickType_t xTicksToWait );</pre>
+ *
+ * configUSE_TASK_NOTIFICATIONS must be undefined or defined as 1 for this
+ * function to be available.
+ *
+ * When configUSE_TASK_NOTIFICATIONS is set to one each task has its own private
+ * "notification value", which is a 32-bit unsigned integer (uint32_t).
+ *
+ * Events can be sent to a task using an intermediary object.  Examples of such
+ * objects are queues, semaphores, mutexes and event groups.  Task notifications
+ * are a method of sending an event directly to a task without the need for such
+ * an intermediary object.
+ *
+ * A notification sent to a task can optionally perform an action, such as
+ * update, overwrite or increment the task's notification value.  In that way
+ * task notifications can be used to send data to a task, or be used as light
+ * weight and fast binary or counting semaphores.
+ *
+ * ulTaskNotifyTake() is intended for use when a task notification is used as a
+ * faster and lighter weight binary or counting semaphore alternative.  Actual
+ * FreeRTOS semaphores are taken using the xSemaphoreTake() API function, the
+ * equivalent action that instead uses a task notification is
+ * ulTaskNotifyTake().
+ *
+ * When a task is using its notification value as a binary or counting semaphore
+ * other tasks should send notifications to it using the xTaskNotifyGive()
+ * macro, or xTaskNotify() function with the eAction parameter set to
+ * eIncrement.
+ *
+ * ulTaskNotifyTake() can either clear the task's notification value to
+ * zero on exit, in which case the notification value acts like a binary
+ * semaphore, or decrement the task's notification value on exit, in which case
+ * the notification value acts like a counting semaphore.
+ *
+ * A task can use ulTaskNotifyTake() to [optionally] block to wait for a
+ * the task's notification value to be non-zero.  The task does not consume any
+ * CPU time while it is in the Blocked state.
+ *
+ * Where as xTaskNotifyWait() will return when a notification is pending,
+ * ulTaskNotifyTake() will return when the task's notification value is
+ * not zero.
+ *
+ * See http://www.FreeRTOS.org/RTOS-task-notifications.html for details.
+ *
+ * @param xClearCountOnExit if xClearCountOnExit is pdFALSE then the task's
+ * notification value is decremented when the function exits.  In this way the
+ * notification value acts like a counting semaphore.  If xClearCountOnExit is
+ * not pdFALSE then the task's notification value is cleared to zero when the
+ * function exits.  In this way the notification value acts like a binary
+ * semaphore.
+ *
+ * @param xTicksToWait The maximum amount of time that the task should wait in
+ * the Blocked state for the task's notification value to be greater than zero,
+ * should the count not already be greater than zero when
+ * ulTaskNotifyTake() was called.  The task will not consume any processing
+ * time while it is in the Blocked state.  This is specified in kernel ticks,
+ * the macro pdMS_TO_TICSK( value_in_ms ) can be used to convert a time
+ * specified in milliseconds to a time specified in ticks.
+ *
+ * @return The task's notification count before it is either cleared to zero or
+ * decremented (see the xClearCountOnExit parameter).
+ *
+ * \defgroup ulTaskNotifyTake ulTaskNotifyTake
+ * \ingroup TaskNotifications
+ */
+uint32_t ulTaskNotifyTake( BaseType_t xClearCountOnExit, TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * <PRE>BaseType_t xTaskNotifyStateClear( TaskHandle_t xTask );</pre>
+ *
+ * If the notification state of the task referenced by the handle xTask is
+ * eNotified, then set the task's notification state to eNotWaitingNotification.
+ * The task's notification value is not altered.  Set xTask to NULL to clear the
+ * notification state of the calling task.
+ *
+ * @return pdTRUE if the task's notification state was set to
+ * eNotWaitingNotification, otherwise pdFALSE.
+ * \defgroup xTaskNotifyStateClear xTaskNotifyStateClear
+ * \ingroup TaskNotifications
+ */
+BaseType_t xTaskNotifyStateClear( TaskHandle_t xTask );
+
+/**
+* task. h
+* <PRE>uint32_t ulTaskNotifyValueClear( TaskHandle_t xTask, uint32_t ulBitsToClear );</pre>
+*
+* Clears the bits specified by the ulBitsToClear bit mask in the notification
+* value of the task referenced by xTask.
+*
+* Set ulBitsToClear to 0xffffffff (UINT_MAX on 32-bit architectures) to clear
+* the notification value to 0.  Set ulBitsToClear to 0 to query the task's
+* notification value without clearing any bits.
+*
+* @return The value of the target task's notification value before the bits
+* specified by ulBitsToClear were cleared.
+* \defgroup ulTaskNotifyValueClear ulTaskNotifyValueClear
+* \ingroup TaskNotifications
+*/
+uint32_t ulTaskNotifyValueClear( TaskHandle_t xTask, uint32_t ulBitsToClear ) PRIVILEGED_FUNCTION;
+
+/**
+ * task.h
+ * <pre>void vTaskSetTimeOutState( TimeOut_t * const pxTimeOut )</pre>
+ *
+ * Capture the current time for future use with xTaskCheckForTimeOut().
+ *
+ * @param pxTimeOut Pointer to a timeout object into which the current time
+ * is to be captured.  The captured time includes the tick count and the number
+ * of times the tick count has overflowed since the system first booted.
+ * \defgroup vTaskSetTimeOutState vTaskSetTimeOutState
+ * \ingroup TaskCtrl
+ */
+void vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) PRIVILEGED_FUNCTION;
+
+/**
+ * task.h
+ * <pre>BaseType_t xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, TickType_t * const pxTicksToWait );</pre>
+ *
+ * Determines if pxTicksToWait ticks has passed since a time was captured
+ * using a call to vTaskSetTimeOutState().  The captured time includes the tick
+ * count and the number of times the tick count has overflowed.
+ *
+ * @param pxTimeOut The time status as captured previously using
+ * vTaskSetTimeOutState. If the timeout has not yet occurred, it is updated
+ * to reflect the current time status.
+ * @param pxTicksToWait The number of ticks to check for timeout i.e. if
+ * pxTicksToWait ticks have passed since pxTimeOut was last updated (either by
+ * vTaskSetTimeOutState() or xTaskCheckForTimeOut()), the timeout has occurred.
+ * If the timeout has not occurred, pxTIcksToWait is updated to reflect the
+ * number of remaining ticks.
+ *
+ * @return If timeout has occurred, pdTRUE is returned. Otherwise pdFALSE is
+ * returned and pxTicksToWait is updated to reflect the number of remaining
+ * ticks.
+ *
+ * @see https://www.freertos.org/xTaskCheckForTimeOut.html
+ *
+ * Example Usage:
+ * <pre>
+	// Driver library function used to receive uxWantedBytes from an Rx buffer
+	// that is filled by a UART interrupt. If there are not enough bytes in the
+	// Rx buffer then the task enters the Blocked state until it is notified that
+	// more data has been placed into the buffer. If there is still not enough
+	// data then the task re-enters the Blocked state, and xTaskCheckForTimeOut()
+	// is used to re-calculate the Block time to ensure the total amount of time
+	// spent in the Blocked state does not exceed MAX_TIME_TO_WAIT. This
+	// continues until either the buffer contains at least uxWantedBytes bytes,
+	// or the total amount of time spent in the Blocked state reaches
+	// MAX_TIME_TO_WAIT – at which point the task reads however many bytes are
+	// available up to a maximum of uxWantedBytes.
+
+	size_t xUART_Receive( uint8_t *pucBuffer, size_t uxWantedBytes )
+	{
+	size_t uxReceived = 0;
+	TickType_t xTicksToWait = MAX_TIME_TO_WAIT;
+	TimeOut_t xTimeOut;
+
+		// Initialize xTimeOut.  This records the time at which this function
+		// was entered.
+		vTaskSetTimeOutState( &xTimeOut );
+
+		// Loop until the buffer contains the wanted number of bytes, or a
+		// timeout occurs.
+		while( UART_bytes_in_rx_buffer( pxUARTInstance ) < uxWantedBytes )
+		{
+			// The buffer didn't contain enough data so this task is going to
+			// enter the Blocked state. Adjusting xTicksToWait to account for
+			// any time that has been spent in the Blocked state within this
+			// function so far to ensure the total amount of time spent in the
+			// Blocked state does not exceed MAX_TIME_TO_WAIT.
+			if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) != pdFALSE )
+			{
+				//Timed out before the wanted number of bytes were available,
+				// exit the loop.
+				break;
+			}
+
+			// Wait for a maximum of xTicksToWait ticks to be notified that the
+			// receive interrupt has placed more data into the buffer.
+			ulTaskNotifyTake( pdTRUE, xTicksToWait );
+		}
+
+		// Attempt to read uxWantedBytes from the receive buffer into pucBuffer.
+		// The actual number of bytes read (which might be less than
+		// uxWantedBytes) is returned.
+		uxReceived = UART_read_from_receive_buffer( pxUARTInstance,
+													pucBuffer,
+													uxWantedBytes );
+
+		return uxReceived;
+	}
+ </pre>
+ * \defgroup xTaskCheckForTimeOut xTaskCheckForTimeOut
+ * \ingroup TaskCtrl
+ */
+BaseType_t xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, TickType_t * const pxTicksToWait ) PRIVILEGED_FUNCTION;
+
+/*-----------------------------------------------------------
+ * SCHEDULER INTERNALS AVAILABLE FOR PORTING PURPOSES
+ *----------------------------------------------------------*/
+
+/*
+ * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE.  IT IS ONLY
+ * INTENDED FOR USE WHEN IMPLEMENTING A PORT OF THE SCHEDULER AND IS
+ * AN INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER.
+ *
+ * Called from the real time kernel tick (either preemptive or cooperative),
+ * this increments the tick count and checks if any tasks that are blocked
+ * for a finite period required removing from a blocked list and placing on
+ * a ready list.  If a non-zero value is returned then a context switch is
+ * required because either:
+ *   + A task was removed from a blocked list because its timeout had expired,
+ *     or
+ *   + Time slicing is in use and there is a task of equal priority to the
+ *     currently running task.
+ */
+BaseType_t xTaskIncrementTick( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE.  IT IS AN
+ * INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER.
+ *
+ * THIS FUNCTION MUST BE CALLED WITH INTERRUPTS DISABLED.
+ *
+ * Removes the calling task from the ready list and places it both
+ * on the list of tasks waiting for a particular event, and the
+ * list of delayed tasks.  The task will be removed from both lists
+ * and replaced on the ready list should either the event occur (and
+ * there be no higher priority tasks waiting on the same event) or
+ * the delay period expires.
+ *
+ * The 'unordered' version replaces the event list item value with the
+ * xItemValue value, and inserts the list item at the end of the list.
+ *
+ * The 'ordered' version uses the existing event list item value (which is the
+ * owning tasks priority) to insert the list item into the event list is task
+ * priority order.
+ *
+ * @param pxEventList The list containing tasks that are blocked waiting
+ * for the event to occur.
+ *
+ * @param xItemValue The item value to use for the event list item when the
+ * event list is not ordered by task priority.
+ *
+ * @param xTicksToWait The maximum amount of time that the task should wait
+ * for the event to occur.  This is specified in kernel ticks,the constant
+ * portTICK_PERIOD_MS can be used to convert kernel ticks into a real time
+ * period.
+ */
+void vTaskPlaceOnEventList( List_t * const pxEventList, const TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+void vTaskPlaceOnUnorderedEventList( List_t * pxEventList, const TickType_t xItemValue, const TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+
+/*
+ * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE.  IT IS AN
+ * INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER.
+ *
+ * THIS FUNCTION MUST BE CALLED WITH INTERRUPTS DISABLED.
+ *
+ * This function performs nearly the same function as vTaskPlaceOnEventList().
+ * The difference being that this function does not permit tasks to block
+ * indefinitely, whereas vTaskPlaceOnEventList() does.
+ *
+ */
+void vTaskPlaceOnEventListRestricted( List_t * const pxEventList, TickType_t xTicksToWait, const BaseType_t xWaitIndefinitely ) PRIVILEGED_FUNCTION;
+
+/*
+ * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE.  IT IS AN
+ * INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER.
+ *
+ * THIS FUNCTION MUST BE CALLED WITH INTERRUPTS DISABLED.
+ *
+ * Removes a task from both the specified event list and the list of blocked
+ * tasks, and places it on a ready queue.
+ *
+ * xTaskRemoveFromEventList()/vTaskRemoveFromUnorderedEventList() will be called
+ * if either an event occurs to unblock a task, or the block timeout period
+ * expires.
+ *
+ * xTaskRemoveFromEventList() is used when the event list is in task priority
+ * order.  It removes the list item from the head of the event list as that will
+ * have the highest priority owning task of all the tasks on the event list.
+ * vTaskRemoveFromUnorderedEventList() is used when the event list is not
+ * ordered and the event list items hold something other than the owning tasks
+ * priority.  In this case the event list item value is updated to the value
+ * passed in the xItemValue parameter.
+ *
+ * @return pdTRUE if the task being removed has a higher priority than the task
+ * making the call, otherwise pdFALSE.
+ */
+BaseType_t xTaskRemoveFromEventList( const List_t * const pxEventList ) PRIVILEGED_FUNCTION;
+void vTaskRemoveFromUnorderedEventList( ListItem_t * pxEventListItem, const TickType_t xItemValue ) PRIVILEGED_FUNCTION;
+
+/*
+ * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE.  IT IS ONLY
+ * INTENDED FOR USE WHEN IMPLEMENTING A PORT OF THE SCHEDULER AND IS
+ * AN INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER.
+ *
+ * Sets the pointer to the current TCB to the TCB of the highest priority task
+ * that is ready to run.
+ */
+portDONT_DISCARD void vTaskSwitchContext( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * THESE FUNCTIONS MUST NOT BE USED FROM APPLICATION CODE.  THEY ARE USED BY
+ * THE EVENT BITS MODULE.
+ */
+TickType_t uxTaskResetEventItemValue( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * Return the handle of the calling task.
+ */
+TaskHandle_t xTaskGetCurrentTaskHandle( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * Shortcut used by the queue implementation to prevent unnecessary call to
+ * taskYIELD();
+ */
+void vTaskMissedYield( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * Returns the scheduler state as taskSCHEDULER_RUNNING,
+ * taskSCHEDULER_NOT_STARTED or taskSCHEDULER_SUSPENDED.
+ */
+BaseType_t xTaskGetSchedulerState( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * Raises the priority of the mutex holder to that of the calling task should
+ * the mutex holder have a priority less than the calling task.
+ */
+BaseType_t xTaskPriorityInherit( TaskHandle_t const pxMutexHolder ) PRIVILEGED_FUNCTION;
+
+/*
+ * Set the priority of a task back to its proper priority in the case that it
+ * inherited a higher priority while it was holding a semaphore.
+ */
+BaseType_t xTaskPriorityDisinherit( TaskHandle_t const pxMutexHolder ) PRIVILEGED_FUNCTION;
+
+/*
+ * If a higher priority task attempting to obtain a mutex caused a lower
+ * priority task to inherit the higher priority task's priority - but the higher
+ * priority task then timed out without obtaining the mutex, then the lower
+ * priority task will disinherit the priority again - but only down as far as
+ * the highest priority task that is still waiting for the mutex (if there were
+ * more than one task waiting for the mutex).
+ */
+void vTaskPriorityDisinheritAfterTimeout( TaskHandle_t const pxMutexHolder, UBaseType_t uxHighestPriorityWaitingTask ) PRIVILEGED_FUNCTION;
+
+/*
+ * Get the uxTCBNumber assigned to the task referenced by the xTask parameter.
+ */
+UBaseType_t uxTaskGetTaskNumber( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
+
+/*
+ * Set the uxTaskNumber of the task referenced by the xTask parameter to
+ * uxHandle.
+ */
+void vTaskSetTaskNumber( TaskHandle_t xTask, const UBaseType_t uxHandle ) PRIVILEGED_FUNCTION;
+
+/*
+ * Only available when configUSE_TICKLESS_IDLE is set to 1.
+ * If tickless mode is being used, or a low power mode is implemented, then
+ * the tick interrupt will not execute during idle periods.  When this is the
+ * case, the tick count value maintained by the scheduler needs to be kept up
+ * to date with the actual execution time by being skipped forward by a time
+ * equal to the idle period.
+ */
+void vTaskStepTick( const TickType_t xTicksToJump ) PRIVILEGED_FUNCTION;
+
+/* Correct the tick count value after the application code has held
+interrupts disabled for an extended period.  xTicksToCatchUp is the number
+of tick interrupts that have been missed due to interrupts being disabled.
+Its value is not computed automatically, so must be computed by the
+application writer.
+
+This function is similar to vTaskStepTick(), however, unlike
+vTaskStepTick(), xTaskCatchUpTicks() may move the tick count forward past a
+time at which a task should be removed from the blocked state.  That means
+tasks may have to be removed from the blocked state as the tick count is
+moved. */
+BaseType_t xTaskCatchUpTicks( TickType_t xTicksToCatchUp ) PRIVILEGED_FUNCTION;
+
+/*
+ * Only available when configUSE_TICKLESS_IDLE is set to 1.
+ * Provided for use within portSUPPRESS_TICKS_AND_SLEEP() to allow the port
+ * specific sleep function to determine if it is ok to proceed with the sleep,
+ * and if it is ok to proceed, if it is ok to sleep indefinitely.
+ *
+ * This function is necessary because portSUPPRESS_TICKS_AND_SLEEP() is only
+ * called with the scheduler suspended, not from within a critical section.  It
+ * is therefore possible for an interrupt to request a context switch between
+ * portSUPPRESS_TICKS_AND_SLEEP() and the low power mode actually being
+ * entered.  eTaskConfirmSleepModeStatus() should be called from a short
+ * critical section between the timer being stopped and the sleep mode being
+ * entered to ensure it is ok to proceed into the sleep mode.
+ */
+eSleepModeStatus eTaskConfirmSleepModeStatus( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * For internal use only.  Increment the mutex held count when a mutex is
+ * taken and return the handle of the task that has taken the mutex.
+ */
+TaskHandle_t pvTaskIncrementMutexHeldCount( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * For internal use only.  Same as vTaskSetTimeOutState(), but without a critial
+ * section.
+ */
+void vTaskInternalSetTimeOutState( TimeOut_t * const pxTimeOut ) PRIVILEGED_FUNCTION;
+
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* INC_TASK_H */
+
+
+
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/include/timers.h b/Middlewares/Third_Party/FreeRTOS/Source/include/timers.h
new file mode 100644
index 0000000..9ee2a0c
--- /dev/null
+++ b/Middlewares/Third_Party/FreeRTOS/Source/include/timers.h
@@ -0,0 +1,1309 @@
+/*
+ * FreeRTOS Kernel V10.3.1
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef TIMERS_H
+#define TIMERS_H
+
+#ifndef INC_FREERTOS_H
+	#error "include FreeRTOS.h must appear in source files before include timers.h"
+#endif
+
+/*lint -save -e537 This headers are only multiply included if the application code
+happens to also be including task.h. */
+#include "task.h"
+/*lint -restore */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*-----------------------------------------------------------
+ * MACROS AND DEFINITIONS
+ *----------------------------------------------------------*/
+
+/* IDs for commands that can be sent/received on the timer queue.  These are to
+be used solely through the macros that make up the public software timer API,
+as defined below.  The commands that are sent from interrupts must use the
+highest numbers as tmrFIRST_FROM_ISR_COMMAND is used to determine if the task
+or interrupt version of the queue send function should be used. */
+#define tmrCOMMAND_EXECUTE_CALLBACK_FROM_ISR 	( ( BaseType_t ) -2 )
+#define tmrCOMMAND_EXECUTE_CALLBACK				( ( BaseType_t ) -1 )
+#define tmrCOMMAND_START_DONT_TRACE				( ( BaseType_t ) 0 )
+#define tmrCOMMAND_START					    ( ( BaseType_t ) 1 )
+#define tmrCOMMAND_RESET						( ( BaseType_t ) 2 )
+#define tmrCOMMAND_STOP							( ( BaseType_t ) 3 )
+#define tmrCOMMAND_CHANGE_PERIOD				( ( BaseType_t ) 4 )
+#define tmrCOMMAND_DELETE						( ( BaseType_t ) 5 )
+
+#define tmrFIRST_FROM_ISR_COMMAND				( ( BaseType_t ) 6 )
+#define tmrCOMMAND_START_FROM_ISR				( ( BaseType_t ) 6 )
+#define tmrCOMMAND_RESET_FROM_ISR				( ( BaseType_t ) 7 )
+#define tmrCOMMAND_STOP_FROM_ISR				( ( BaseType_t ) 8 )
+#define tmrCOMMAND_CHANGE_PERIOD_FROM_ISR		( ( BaseType_t ) 9 )
+
+
+/**
+ * Type by which software timers are referenced.  For example, a call to
+ * xTimerCreate() returns an TimerHandle_t variable that can then be used to
+ * reference the subject timer in calls to other software timer API functions
+ * (for example, xTimerStart(), xTimerReset(), etc.).
+ */
+struct tmrTimerControl; /* The old naming convention is used to prevent breaking kernel aware debuggers. */
+typedef struct tmrTimerControl * TimerHandle_t;
+
+/*
+ * Defines the prototype to which timer callback functions must conform.
+ */
+typedef void (*TimerCallbackFunction_t)( TimerHandle_t xTimer );
+
+/*
+ * Defines the prototype to which functions used with the
+ * xTimerPendFunctionCallFromISR() function must conform.
+ */
+typedef void (*PendedFunction_t)( void *, uint32_t );
+
+/**
+ * TimerHandle_t xTimerCreate( 	const char * const pcTimerName,
+ * 								TickType_t xTimerPeriodInTicks,
+ * 								UBaseType_t uxAutoReload,
+ * 								void * pvTimerID,
+ * 								TimerCallbackFunction_t pxCallbackFunction );
+ *
+ * Creates a new software timer instance, and returns a handle by which the
+ * created software timer can be referenced.
+ *
+ * Internally, within the FreeRTOS implementation, software timers use a block
+ * of memory, in which the timer data structure is stored.  If a software timer
+ * is created using xTimerCreate() then the required memory is automatically
+ * dynamically allocated inside the xTimerCreate() function.  (see
+ * http://www.freertos.org/a00111.html).  If a software timer is created using
+ * xTimerCreateStatic() then the application writer must provide the memory that
+ * will get used by the software timer.  xTimerCreateStatic() therefore allows a
+ * software timer to be created without using any dynamic memory allocation.
+ *
+ * Timers are created in the dormant state.  The xTimerStart(), xTimerReset(),
+ * xTimerStartFromISR(), xTimerResetFromISR(), xTimerChangePeriod() and
+ * xTimerChangePeriodFromISR() API functions can all be used to transition a
+ * timer into the active state.
+ *
+ * @param pcTimerName A text name that is assigned to the timer.  This is done
+ * purely to assist debugging.  The kernel itself only ever references a timer
+ * by its handle, and never by its name.
+ *
+ * @param xTimerPeriodInTicks The timer period.  The time is defined in tick
+ * periods so the constant portTICK_PERIOD_MS can be used to convert a time that
+ * has been specified in milliseconds.  For example, if the timer must expire
+ * after 100 ticks, then xTimerPeriodInTicks should be set to 100.
+ * Alternatively, if the timer must expire after 500ms, then xPeriod can be set
+ * to ( 500 / portTICK_PERIOD_MS ) provided configTICK_RATE_HZ is less than or
+ * equal to 1000.  Time timer period must be greater than 0.
+ *
+ * @param uxAutoReload If uxAutoReload is set to pdTRUE then the timer will
+ * expire repeatedly with a frequency set by the xTimerPeriodInTicks parameter.
+ * If uxAutoReload is set to pdFALSE then the timer will be a one-shot timer and
+ * enter the dormant state after it expires.
+ *
+ * @param pvTimerID An identifier that is assigned to the timer being created.
+ * Typically this would be used in the timer callback function to identify which
+ * timer expired when the same callback function is assigned to more than one
+ * timer.
+ *
+ * @param pxCallbackFunction The function to call when the timer expires.
+ * Callback functions must have the prototype defined by TimerCallbackFunction_t,
+ * which is	"void vCallbackFunction( TimerHandle_t xTimer );".
+ *
+ * @return If the timer is successfully created then a handle to the newly
+ * created timer is returned.  If the timer cannot be created because there is
+ * insufficient FreeRTOS heap remaining to allocate the timer
+ * structures then NULL is returned.
+ *
+ * Example usage:
+ * @verbatim
+ * #define NUM_TIMERS 5
+ *
+ * // An array to hold handles to the created timers.
+ * TimerHandle_t xTimers[ NUM_TIMERS ];
+ *
+ * // An array to hold a count of the number of times each timer expires.
+ * int32_t lExpireCounters[ NUM_TIMERS ] = { 0 };
+ *
+ * // Define a callback function that will be used by multiple timer instances.
+ * // The callback function does nothing but count the number of times the
+ * // associated timer expires, and stop the timer once the timer has expired
+ * // 10 times.
+ * void vTimerCallback( TimerHandle_t pxTimer )
+ * {
+ * int32_t lArrayIndex;
+ * const int32_t xMaxExpiryCountBeforeStopping = 10;
+ *
+ * 	   // Optionally do something if the pxTimer parameter is NULL.
+ * 	   configASSERT( pxTimer );
+ *
+ *     // Which timer expired?
+ *     lArrayIndex = ( int32_t ) pvTimerGetTimerID( pxTimer );
+ *
+ *     // Increment the number of times that pxTimer has expired.
+ *     lExpireCounters[ lArrayIndex ] += 1;
+ *
+ *     // If the timer has expired 10 times then stop it from running.
+ *     if( lExpireCounters[ lArrayIndex ] == xMaxExpiryCountBeforeStopping )
+ *     {
+ *         // Do not use a block time if calling a timer API function from a
+ *         // timer callback function, as doing so could cause a deadlock!
+ *         xTimerStop( pxTimer, 0 );
+ *     }
+ * }
+ *
+ * void main( void )
+ * {
+ * int32_t x;
+ *
+ *     // Create then start some timers.  Starting the timers before the scheduler
+ *     // has been started means the timers will start running immediately that
+ *     // the scheduler starts.
+ *     for( x = 0; x < NUM_TIMERS; x++ )
+ *     {
+ *         xTimers[ x ] = xTimerCreate(    "Timer",       // Just a text name, not used by the kernel.
+ *                                         ( 100 * x ),   // The timer period in ticks.
+ *                                         pdTRUE,        // The timers will auto-reload themselves when they expire.
+ *                                         ( void * ) x,  // Assign each timer a unique id equal to its array index.
+ *                                         vTimerCallback // Each timer calls the same callback when it expires.
+ *                                     );
+ *
+ *         if( xTimers[ x ] == NULL )
+ *         {
+ *             // The timer was not created.
+ *         }
+ *         else
+ *         {
+ *             // Start the timer.  No block time is specified, and even if one was
+ *             // it would be ignored because the scheduler has not yet been
+ *             // started.
+ *             if( xTimerStart( xTimers[ x ], 0 ) != pdPASS )
+ *             {
+ *                 // The timer could not be set into the Active state.
+ *             }
+ *         }
+ *     }
+ *
+ *     // ...
+ *     // Create tasks here.
+ *     // ...
+ *
+ *     // Starting the scheduler will start the timers running as they have already
+ *     // been set into the active state.
+ *     vTaskStartScheduler();
+ *
+ *     // Should not reach here.
+ *     for( ;; );
+ * }
+ * @endverbatim
+ */
+#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+	TimerHandle_t xTimerCreate(	const char * const pcTimerName,			/*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+								const TickType_t xTimerPeriodInTicks,
+								const UBaseType_t uxAutoReload,
+								void * const pvTimerID,
+								TimerCallbackFunction_t pxCallbackFunction ) PRIVILEGED_FUNCTION;
+#endif
+
+/**
+ * TimerHandle_t xTimerCreateStatic(const char * const pcTimerName,
+ * 									TickType_t xTimerPeriodInTicks,
+ * 									UBaseType_t uxAutoReload,
+ * 									void * pvTimerID,
+ * 									TimerCallbackFunction_t pxCallbackFunction,
+ *									StaticTimer_t *pxTimerBuffer );
+ *
+ * Creates a new software timer instance, and returns a handle by which the
+ * created software timer can be referenced.
+ *
+ * Internally, within the FreeRTOS implementation, software timers use a block
+ * of memory, in which the timer data structure is stored.  If a software timer
+ * is created using xTimerCreate() then the required memory is automatically
+ * dynamically allocated inside the xTimerCreate() function.  (see
+ * http://www.freertos.org/a00111.html).  If a software timer is created using
+ * xTimerCreateStatic() then the application writer must provide the memory that
+ * will get used by the software timer.  xTimerCreateStatic() therefore allows a
+ * software timer to be created without using any dynamic memory allocation.
+ *
+ * Timers are created in the dormant state.  The xTimerStart(), xTimerReset(),
+ * xTimerStartFromISR(), xTimerResetFromISR(), xTimerChangePeriod() and
+ * xTimerChangePeriodFromISR() API functions can all be used to transition a
+ * timer into the active state.
+ *
+ * @param pcTimerName A text name that is assigned to the timer.  This is done
+ * purely to assist debugging.  The kernel itself only ever references a timer
+ * by its handle, and never by its name.
+ *
+ * @param xTimerPeriodInTicks The timer period.  The time is defined in tick
+ * periods so the constant portTICK_PERIOD_MS can be used to convert a time that
+ * has been specified in milliseconds.  For example, if the timer must expire
+ * after 100 ticks, then xTimerPeriodInTicks should be set to 100.
+ * Alternatively, if the timer must expire after 500ms, then xPeriod can be set
+ * to ( 500 / portTICK_PERIOD_MS ) provided configTICK_RATE_HZ is less than or
+ * equal to 1000.  The timer period must be greater than 0.
+ *
+ * @param uxAutoReload If uxAutoReload is set to pdTRUE then the timer will
+ * expire repeatedly with a frequency set by the xTimerPeriodInTicks parameter.
+ * If uxAutoReload is set to pdFALSE then the timer will be a one-shot timer and
+ * enter the dormant state after it expires.
+ *
+ * @param pvTimerID An identifier that is assigned to the timer being created.
+ * Typically this would be used in the timer callback function to identify which
+ * timer expired when the same callback function is assigned to more than one
+ * timer.
+ *
+ * @param pxCallbackFunction The function to call when the timer expires.
+ * Callback functions must have the prototype defined by TimerCallbackFunction_t,
+ * which is "void vCallbackFunction( TimerHandle_t xTimer );".
+ *
+ * @param pxTimerBuffer Must point to a variable of type StaticTimer_t, which
+ * will be then be used to hold the software timer's data structures, removing
+ * the need for the memory to be allocated dynamically.
+ *
+ * @return If the timer is created then a handle to the created timer is
+ * returned.  If pxTimerBuffer was NULL then NULL is returned.
+ *
+ * Example usage:
+ * @verbatim
+ *
+ * // The buffer used to hold the software timer's data structure.
+ * static StaticTimer_t xTimerBuffer;
+ *
+ * // A variable that will be incremented by the software timer's callback
+ * // function.
+ * UBaseType_t uxVariableToIncrement = 0;
+ *
+ * // A software timer callback function that increments a variable passed to
+ * // it when the software timer was created.  After the 5th increment the
+ * // callback function stops the software timer.
+ * static void prvTimerCallback( TimerHandle_t xExpiredTimer )
+ * {
+ * UBaseType_t *puxVariableToIncrement;
+ * BaseType_t xReturned;
+ *
+ *     // Obtain the address of the variable to increment from the timer ID.
+ *     puxVariableToIncrement = ( UBaseType_t * ) pvTimerGetTimerID( xExpiredTimer );
+ *
+ *     // Increment the variable to show the timer callback has executed.
+ *     ( *puxVariableToIncrement )++;
+ *
+ *     // If this callback has executed the required number of times, stop the
+ *     // timer.
+ *     if( *puxVariableToIncrement == 5 )
+ *     {
+ *         // This is called from a timer callback so must not block.
+ *         xTimerStop( xExpiredTimer, staticDONT_BLOCK );
+ *     }
+ * }
+ *
+ *
+ * void main( void )
+ * {
+ *     // Create the software time.  xTimerCreateStatic() has an extra parameter
+ *     // than the normal xTimerCreate() API function.  The parameter is a pointer
+ *     // to the StaticTimer_t structure that will hold the software timer
+ *     // structure.  If the parameter is passed as NULL then the structure will be
+ *     // allocated dynamically, just as if xTimerCreate() had been called.
+ *     xTimer = xTimerCreateStatic( "T1",             // Text name for the task.  Helps debugging only.  Not used by FreeRTOS.
+ *                                  xTimerPeriod,     // The period of the timer in ticks.
+ *                                  pdTRUE,           // This is an auto-reload timer.
+ *                                  ( void * ) &uxVariableToIncrement,    // A variable incremented by the software timer's callback function
+ *                                  prvTimerCallback, // The function to execute when the timer expires.
+ *                                  &xTimerBuffer );  // The buffer that will hold the software timer structure.
+ *
+ *     // The scheduler has not started yet so a block time is not used.
+ *     xReturned = xTimerStart( xTimer, 0 );
+ *
+ *     // ...
+ *     // Create tasks here.
+ *     // ...
+ *
+ *     // Starting the scheduler will start the timers running as they have already
+ *     // been set into the active state.
+ *     vTaskStartScheduler();
+ *
+ *     // Should not reach here.
+ *     for( ;; );
+ * }
+ * @endverbatim
+ */
+#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+	TimerHandle_t xTimerCreateStatic(	const char * const pcTimerName,			/*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+										const TickType_t xTimerPeriodInTicks,
+										const UBaseType_t uxAutoReload,
+										void * const pvTimerID,
+										TimerCallbackFunction_t pxCallbackFunction,
+										StaticTimer_t *pxTimerBuffer ) PRIVILEGED_FUNCTION;
+#endif /* configSUPPORT_STATIC_ALLOCATION */
+
+/**
+ * void *pvTimerGetTimerID( TimerHandle_t xTimer );
+ *
+ * Returns the ID assigned to the timer.
+ *
+ * IDs are assigned to timers using the pvTimerID parameter of the call to
+ * xTimerCreated() that was used to create the timer, and by calling the
+ * vTimerSetTimerID() API function.
+ *
+ * If the same callback function is assigned to multiple timers then the timer
+ * ID can be used as time specific (timer local) storage.
+ *
+ * @param xTimer The timer being queried.
+ *
+ * @return The ID assigned to the timer being queried.
+ *
+ * Example usage:
+ *
+ * See the xTimerCreate() API function example usage scenario.
+ */
+void *pvTimerGetTimerID( const TimerHandle_t xTimer ) PRIVILEGED_FUNCTION;
+
+/**
+ * void vTimerSetTimerID( TimerHandle_t xTimer, void *pvNewID );
+ *
+ * Sets the ID assigned to the timer.
+ *
+ * IDs are assigned to timers using the pvTimerID parameter of the call to
+ * xTimerCreated() that was used to create the timer.
+ *
+ * If the same callback function is assigned to multiple timers then the timer
+ * ID can be used as time specific (timer local) storage.
+ *
+ * @param xTimer The timer being updated.
+ *
+ * @param pvNewID The ID to assign to the timer.
+ *
+ * Example usage:
+ *
+ * See the xTimerCreate() API function example usage scenario.
+ */
+void vTimerSetTimerID( TimerHandle_t xTimer, void *pvNewID ) PRIVILEGED_FUNCTION;
+
+/**
+ * BaseType_t xTimerIsTimerActive( TimerHandle_t xTimer );
+ *
+ * Queries a timer to see if it is active or dormant.
+ *
+ * A timer will be dormant if:
+ *     1) It has been created but not started, or
+ *     2) It is an expired one-shot timer that has not been restarted.
+ *
+ * Timers are created in the dormant state.  The xTimerStart(), xTimerReset(),
+ * xTimerStartFromISR(), xTimerResetFromISR(), xTimerChangePeriod() and
+ * xTimerChangePeriodFromISR() API functions can all be used to transition a timer into the
+ * active state.
+ *
+ * @param xTimer The timer being queried.
+ *
+ * @return pdFALSE will be returned if the timer is dormant.  A value other than
+ * pdFALSE will be returned if the timer is active.
+ *
+ * Example usage:
+ * @verbatim
+ * // This function assumes xTimer has already been created.
+ * void vAFunction( TimerHandle_t xTimer )
+ * {
+ *     if( xTimerIsTimerActive( xTimer ) != pdFALSE ) // or more simply and equivalently "if( xTimerIsTimerActive( xTimer ) )"
+ *     {
+ *         // xTimer is active, do something.
+ *     }
+ *     else
+ *     {
+ *         // xTimer is not active, do something else.
+ *     }
+ * }
+ * @endverbatim
+ */
+BaseType_t xTimerIsTimerActive( TimerHandle_t xTimer ) PRIVILEGED_FUNCTION;
+
+/**
+ * TaskHandle_t xTimerGetTimerDaemonTaskHandle( void );
+ *
+ * Simply returns the handle of the timer service/daemon task.  It it not valid
+ * to call xTimerGetTimerDaemonTaskHandle() before the scheduler has been started.
+ */
+TaskHandle_t xTimerGetTimerDaemonTaskHandle( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * BaseType_t xTimerStart( TimerHandle_t xTimer, TickType_t xTicksToWait );
+ *
+ * Timer functionality is provided by a timer service/daemon task.  Many of the
+ * public FreeRTOS timer API functions send commands to the timer service task
+ * through a queue called the timer command queue.  The timer command queue is
+ * private to the kernel itself and is not directly accessible to application
+ * code.  The length of the timer command queue is set by the
+ * configTIMER_QUEUE_LENGTH configuration constant.
+ *
+ * xTimerStart() starts a timer that was previously created using the
+ * xTimerCreate() API function.  If the timer had already been started and was
+ * already in the active state, then xTimerStart() has equivalent functionality
+ * to the xTimerReset() API function.
+ *
+ * Starting a timer ensures the timer is in the active state.  If the timer
+ * is not stopped, deleted, or reset in the mean time, the callback function
+ * associated with the timer will get called 'n' ticks after xTimerStart() was
+ * called, where 'n' is the timers defined period.
+ *
+ * It is valid to call xTimerStart() before the scheduler has been started, but
+ * when this is done the timer will not actually start until the scheduler is
+ * started, and the timers expiry time will be relative to when the scheduler is
+ * started, not relative to when xTimerStart() was called.
+ *
+ * The configUSE_TIMERS configuration constant must be set to 1 for xTimerStart()
+ * to be available.
+ *
+ * @param xTimer The handle of the timer being started/restarted.
+ *
+ * @param xTicksToWait Specifies the time, in ticks, that the calling task should
+ * be held in the Blocked state to wait for the start command to be successfully
+ * sent to the timer command queue, should the queue already be full when
+ * xTimerStart() was called.  xTicksToWait is ignored if xTimerStart() is called
+ * before the scheduler is started.
+ *
+ * @return pdFAIL will be returned if the start command could not be sent to
+ * the timer command queue even after xTicksToWait ticks had passed.  pdPASS will
+ * be returned if the command was successfully sent to the timer command queue.
+ * When the command is actually processed will depend on the priority of the
+ * timer service/daemon task relative to other tasks in the system, although the
+ * timers expiry time is relative to when xTimerStart() is actually called.  The
+ * timer service/daemon task priority is set by the configTIMER_TASK_PRIORITY
+ * configuration constant.
+ *
+ * Example usage:
+ *
+ * See the xTimerCreate() API function example usage scenario.
+ *
+ */
+#define xTimerStart( xTimer, xTicksToWait ) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_START, ( xTaskGetTickCount() ), NULL, ( xTicksToWait ) )
+
+/**
+ * BaseType_t xTimerStop( TimerHandle_t xTimer, TickType_t xTicksToWait );
+ *
+ * Timer functionality is provided by a timer service/daemon task.  Many of the
+ * public FreeRTOS timer API functions send commands to the timer service task
+ * through a queue called the timer command queue.  The timer command queue is
+ * private to the kernel itself and is not directly accessible to application
+ * code.  The length of the timer command queue is set by the
+ * configTIMER_QUEUE_LENGTH configuration constant.
+ *
+ * xTimerStop() stops a timer that was previously started using either of the
+ * The xTimerStart(), xTimerReset(), xTimerStartFromISR(), xTimerResetFromISR(),
+ * xTimerChangePeriod() or xTimerChangePeriodFromISR() API functions.
+ *
+ * Stopping a timer ensures the timer is not in the active state.
+ *
+ * The configUSE_TIMERS configuration constant must be set to 1 for xTimerStop()
+ * to be available.
+ *
+ * @param xTimer The handle of the timer being stopped.
+ *
+ * @param xTicksToWait Specifies the time, in ticks, that the calling task should
+ * be held in the Blocked state to wait for the stop command to be successfully
+ * sent to the timer command queue, should the queue already be full when
+ * xTimerStop() was called.  xTicksToWait is ignored if xTimerStop() is called
+ * before the scheduler is started.
+ *
+ * @return pdFAIL will be returned if the stop command could not be sent to
+ * the timer command queue even after xTicksToWait ticks had passed.  pdPASS will
+ * be returned if the command was successfully sent to the timer command queue.
+ * When the command is actually processed will depend on the priority of the
+ * timer service/daemon task relative to other tasks in the system.  The timer
+ * service/daemon task priority is set by the configTIMER_TASK_PRIORITY
+ * configuration constant.
+ *
+ * Example usage:
+ *
+ * See the xTimerCreate() API function example usage scenario.
+ *
+ */
+#define xTimerStop( xTimer, xTicksToWait ) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_STOP, 0U, NULL, ( xTicksToWait ) )
+
+/**
+ * BaseType_t xTimerChangePeriod( 	TimerHandle_t xTimer,
+ *										TickType_t xNewPeriod,
+ *										TickType_t xTicksToWait );
+ *
+ * Timer functionality is provided by a timer service/daemon task.  Many of the
+ * public FreeRTOS timer API functions send commands to the timer service task
+ * through a queue called the timer command queue.  The timer command queue is
+ * private to the kernel itself and is not directly accessible to application
+ * code.  The length of the timer command queue is set by the
+ * configTIMER_QUEUE_LENGTH configuration constant.
+ *
+ * xTimerChangePeriod() changes the period of a timer that was previously
+ * created using the xTimerCreate() API function.
+ *
+ * xTimerChangePeriod() can be called to change the period of an active or
+ * dormant state timer.
+ *
+ * The configUSE_TIMERS configuration constant must be set to 1 for
+ * xTimerChangePeriod() to be available.
+ *
+ * @param xTimer The handle of the timer that is having its period changed.
+ *
+ * @param xNewPeriod The new period for xTimer. Timer periods are specified in
+ * tick periods, so the constant portTICK_PERIOD_MS can be used to convert a time
+ * that has been specified in milliseconds.  For example, if the timer must
+ * expire after 100 ticks, then xNewPeriod should be set to 100.  Alternatively,
+ * if the timer must expire after 500ms, then xNewPeriod can be set to
+ * ( 500 / portTICK_PERIOD_MS ) provided configTICK_RATE_HZ is less than
+ * or equal to 1000.
+ *
+ * @param xTicksToWait Specifies the time, in ticks, that the calling task should
+ * be held in the Blocked state to wait for the change period command to be
+ * successfully sent to the timer command queue, should the queue already be
+ * full when xTimerChangePeriod() was called.  xTicksToWait is ignored if
+ * xTimerChangePeriod() is called before the scheduler is started.
+ *
+ * @return pdFAIL will be returned if the change period command could not be
+ * sent to the timer command queue even after xTicksToWait ticks had passed.
+ * pdPASS will be returned if the command was successfully sent to the timer
+ * command queue.  When the command is actually processed will depend on the
+ * priority of the timer service/daemon task relative to other tasks in the
+ * system.  The timer service/daemon task priority is set by the
+ * configTIMER_TASK_PRIORITY configuration constant.
+ *
+ * Example usage:
+ * @verbatim
+ * // This function assumes xTimer has already been created.  If the timer
+ * // referenced by xTimer is already active when it is called, then the timer
+ * // is deleted.  If the timer referenced by xTimer is not active when it is
+ * // called, then the period of the timer is set to 500ms and the timer is
+ * // started.
+ * void vAFunction( TimerHandle_t xTimer )
+ * {
+ *     if( xTimerIsTimerActive( xTimer ) != pdFALSE ) // or more simply and equivalently "if( xTimerIsTimerActive( xTimer ) )"
+ *     {
+ *         // xTimer is already active - delete it.
+ *         xTimerDelete( xTimer );
+ *     }
+ *     else
+ *     {
+ *         // xTimer is not active, change its period to 500ms.  This will also
+ *         // cause the timer to start.  Block for a maximum of 100 ticks if the
+ *         // change period command cannot immediately be sent to the timer
+ *         // command queue.
+ *         if( xTimerChangePeriod( xTimer, 500 / portTICK_PERIOD_MS, 100 ) == pdPASS )
+ *         {
+ *             // The command was successfully sent.
+ *         }
+ *         else
+ *         {
+ *             // The command could not be sent, even after waiting for 100 ticks
+ *             // to pass.  Take appropriate action here.
+ *         }
+ *     }
+ * }
+ * @endverbatim
+ */
+ #define xTimerChangePeriod( xTimer, xNewPeriod, xTicksToWait ) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_CHANGE_PERIOD, ( xNewPeriod ), NULL, ( xTicksToWait ) )
+
+/**
+ * BaseType_t xTimerDelete( TimerHandle_t xTimer, TickType_t xTicksToWait );
+ *
+ * Timer functionality is provided by a timer service/daemon task.  Many of the
+ * public FreeRTOS timer API functions send commands to the timer service task
+ * through a queue called the timer command queue.  The timer command queue is
+ * private to the kernel itself and is not directly accessible to application
+ * code.  The length of the timer command queue is set by the
+ * configTIMER_QUEUE_LENGTH configuration constant.
+ *
+ * xTimerDelete() deletes a timer that was previously created using the
+ * xTimerCreate() API function.
+ *
+ * The configUSE_TIMERS configuration constant must be set to 1 for
+ * xTimerDelete() to be available.
+ *
+ * @param xTimer The handle of the timer being deleted.
+ *
+ * @param xTicksToWait Specifies the time, in ticks, that the calling task should
+ * be held in the Blocked state to wait for the delete command to be
+ * successfully sent to the timer command queue, should the queue already be
+ * full when xTimerDelete() was called.  xTicksToWait is ignored if xTimerDelete()
+ * is called before the scheduler is started.
+ *
+ * @return pdFAIL will be returned if the delete command could not be sent to
+ * the timer command queue even after xTicksToWait ticks had passed.  pdPASS will
+ * be returned if the command was successfully sent to the timer command queue.
+ * When the command is actually processed will depend on the priority of the
+ * timer service/daemon task relative to other tasks in the system.  The timer
+ * service/daemon task priority is set by the configTIMER_TASK_PRIORITY
+ * configuration constant.
+ *
+ * Example usage:
+ *
+ * See the xTimerChangePeriod() API function example usage scenario.
+ */
+#define xTimerDelete( xTimer, xTicksToWait ) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_DELETE, 0U, NULL, ( xTicksToWait ) )
+
+/**
+ * BaseType_t xTimerReset( TimerHandle_t xTimer, TickType_t xTicksToWait );
+ *
+ * Timer functionality is provided by a timer service/daemon task.  Many of the
+ * public FreeRTOS timer API functions send commands to the timer service task
+ * through a queue called the timer command queue.  The timer command queue is
+ * private to the kernel itself and is not directly accessible to application
+ * code.  The length of the timer command queue is set by the
+ * configTIMER_QUEUE_LENGTH configuration constant.
+ *
+ * xTimerReset() re-starts a timer that was previously created using the
+ * xTimerCreate() API function.  If the timer had already been started and was
+ * already in the active state, then xTimerReset() will cause the timer to
+ * re-evaluate its expiry time so that it is relative to when xTimerReset() was
+ * called.  If the timer was in the dormant state then xTimerReset() has
+ * equivalent functionality to the xTimerStart() API function.
+ *
+ * Resetting a timer ensures the timer is in the active state.  If the timer
+ * is not stopped, deleted, or reset in the mean time, the callback function
+ * associated with the timer will get called 'n' ticks after xTimerReset() was
+ * called, where 'n' is the timers defined period.
+ *
+ * It is valid to call xTimerReset() before the scheduler has been started, but
+ * when this is done the timer will not actually start until the scheduler is
+ * started, and the timers expiry time will be relative to when the scheduler is
+ * started, not relative to when xTimerReset() was called.
+ *
+ * The configUSE_TIMERS configuration constant must be set to 1 for xTimerReset()
+ * to be available.
+ *
+ * @param xTimer The handle of the timer being reset/started/restarted.
+ *
+ * @param xTicksToWait Specifies the time, in ticks, that the calling task should
+ * be held in the Blocked state to wait for the reset command to be successfully
+ * sent to the timer command queue, should the queue already be full when
+ * xTimerReset() was called.  xTicksToWait is ignored if xTimerReset() is called
+ * before the scheduler is started.
+ *
+ * @return pdFAIL will be returned if the reset command could not be sent to
+ * the timer command queue even after xTicksToWait ticks had passed.  pdPASS will
+ * be returned if the command was successfully sent to the timer command queue.
+ * When the command is actually processed will depend on the priority of the
+ * timer service/daemon task relative to other tasks in the system, although the
+ * timers expiry time is relative to when xTimerStart() is actually called.  The
+ * timer service/daemon task priority is set by the configTIMER_TASK_PRIORITY
+ * configuration constant.
+ *
+ * Example usage:
+ * @verbatim
+ * // When a key is pressed, an LCD back-light is switched on.  If 5 seconds pass
+ * // without a key being pressed, then the LCD back-light is switched off.  In
+ * // this case, the timer is a one-shot timer.
+ *
+ * TimerHandle_t xBacklightTimer = NULL;
+ *
+ * // The callback function assigned to the one-shot timer.  In this case the
+ * // parameter is not used.
+ * void vBacklightTimerCallback( TimerHandle_t pxTimer )
+ * {
+ *     // The timer expired, therefore 5 seconds must have passed since a key
+ *     // was pressed.  Switch off the LCD back-light.
+ *     vSetBacklightState( BACKLIGHT_OFF );
+ * }
+ *
+ * // The key press event handler.
+ * void vKeyPressEventHandler( char cKey )
+ * {
+ *     // Ensure the LCD back-light is on, then reset the timer that is
+ *     // responsible for turning the back-light off after 5 seconds of
+ *     // key inactivity.  Wait 10 ticks for the command to be successfully sent
+ *     // if it cannot be sent immediately.
+ *     vSetBacklightState( BACKLIGHT_ON );
+ *     if( xTimerReset( xBacklightTimer, 100 ) != pdPASS )
+ *     {
+ *         // The reset command was not executed successfully.  Take appropriate
+ *         // action here.
+ *     }
+ *
+ *     // Perform the rest of the key processing here.
+ * }
+ *
+ * void main( void )
+ * {
+ * int32_t x;
+ *
+ *     // Create then start the one-shot timer that is responsible for turning
+ *     // the back-light off if no keys are pressed within a 5 second period.
+ *     xBacklightTimer = xTimerCreate( "BacklightTimer",           // Just a text name, not used by the kernel.
+ *                                     ( 5000 / portTICK_PERIOD_MS), // The timer period in ticks.
+ *                                     pdFALSE,                    // The timer is a one-shot timer.
+ *                                     0,                          // The id is not used by the callback so can take any value.
+ *                                     vBacklightTimerCallback     // The callback function that switches the LCD back-light off.
+ *                                   );
+ *
+ *     if( xBacklightTimer == NULL )
+ *     {
+ *         // The timer was not created.
+ *     }
+ *     else
+ *     {
+ *         // Start the timer.  No block time is specified, and even if one was
+ *         // it would be ignored because the scheduler has not yet been
+ *         // started.
+ *         if( xTimerStart( xBacklightTimer, 0 ) != pdPASS )
+ *         {
+ *             // The timer could not be set into the Active state.
+ *         }
+ *     }
+ *
+ *     // ...
+ *     // Create tasks here.
+ *     // ...
+ *
+ *     // Starting the scheduler will start the timer running as it has already
+ *     // been set into the active state.
+ *     vTaskStartScheduler();
+ *
+ *     // Should not reach here.
+ *     for( ;; );
+ * }
+ * @endverbatim
+ */
+#define xTimerReset( xTimer, xTicksToWait ) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_RESET, ( xTaskGetTickCount() ), NULL, ( xTicksToWait ) )
+
+/**
+ * BaseType_t xTimerStartFromISR( 	TimerHandle_t xTimer,
+ *									BaseType_t *pxHigherPriorityTaskWoken );
+ *
+ * A version of xTimerStart() that can be called from an interrupt service
+ * routine.
+ *
+ * @param xTimer The handle of the timer being started/restarted.
+ *
+ * @param pxHigherPriorityTaskWoken The timer service/daemon task spends most
+ * of its time in the Blocked state, waiting for messages to arrive on the timer
+ * command queue.  Calling xTimerStartFromISR() writes a message to the timer
+ * command queue, so has the potential to transition the timer service/daemon
+ * task out of the Blocked state.  If calling xTimerStartFromISR() causes the
+ * timer service/daemon task to leave the Blocked state, and the timer service/
+ * daemon task has a priority equal to or greater than the currently executing
+ * task (the task that was interrupted), then *pxHigherPriorityTaskWoken will
+ * get set to pdTRUE internally within the xTimerStartFromISR() function.  If
+ * xTimerStartFromISR() sets this value to pdTRUE then a context switch should
+ * be performed before the interrupt exits.
+ *
+ * @return pdFAIL will be returned if the start command could not be sent to
+ * the timer command queue.  pdPASS will be returned if the command was
+ * successfully sent to the timer command queue.  When the command is actually
+ * processed will depend on the priority of the timer service/daemon task
+ * relative to other tasks in the system, although the timers expiry time is
+ * relative to when xTimerStartFromISR() is actually called.  The timer
+ * service/daemon task priority is set by the configTIMER_TASK_PRIORITY
+ * configuration constant.
+ *
+ * Example usage:
+ * @verbatim
+ * // This scenario assumes xBacklightTimer has already been created.  When a
+ * // key is pressed, an LCD back-light is switched on.  If 5 seconds pass
+ * // without a key being pressed, then the LCD back-light is switched off.  In
+ * // this case, the timer is a one-shot timer, and unlike the example given for
+ * // the xTimerReset() function, the key press event handler is an interrupt
+ * // service routine.
+ *
+ * // The callback function assigned to the one-shot timer.  In this case the
+ * // parameter is not used.
+ * void vBacklightTimerCallback( TimerHandle_t pxTimer )
+ * {
+ *     // The timer expired, therefore 5 seconds must have passed since a key
+ *     // was pressed.  Switch off the LCD back-light.
+ *     vSetBacklightState( BACKLIGHT_OFF );
+ * }
+ *
+ * // The key press interrupt service routine.
+ * void vKeyPressEventInterruptHandler( void )
+ * {
+ * BaseType_t xHigherPriorityTaskWoken = pdFALSE;
+ *
+ *     // Ensure the LCD back-light is on, then restart the timer that is
+ *     // responsible for turning the back-light off after 5 seconds of
+ *     // key inactivity.  This is an interrupt service routine so can only
+ *     // call FreeRTOS API functions that end in "FromISR".
+ *     vSetBacklightState( BACKLIGHT_ON );
+ *
+ *     // xTimerStartFromISR() or xTimerResetFromISR() could be called here
+ *     // as both cause the timer to re-calculate its expiry time.
+ *     // xHigherPriorityTaskWoken was initialised to pdFALSE when it was
+ *     // declared (in this function).
+ *     if( xTimerStartFromISR( xBacklightTimer, &xHigherPriorityTaskWoken ) != pdPASS )
+ *     {
+ *         // The start command was not executed successfully.  Take appropriate
+ *         // action here.
+ *     }
+ *
+ *     // Perform the rest of the key processing here.
+ *
+ *     // If xHigherPriorityTaskWoken equals pdTRUE, then a context switch
+ *     // should be performed.  The syntax required to perform a context switch
+ *     // from inside an ISR varies from port to port, and from compiler to
+ *     // compiler.  Inspect the demos for the port you are using to find the
+ *     // actual syntax required.
+ *     if( xHigherPriorityTaskWoken != pdFALSE )
+ *     {
+ *         // Call the interrupt safe yield function here (actual function
+ *         // depends on the FreeRTOS port being used).
+ *     }
+ * }
+ * @endverbatim
+ */
+#define xTimerStartFromISR( xTimer, pxHigherPriorityTaskWoken ) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_START_FROM_ISR, ( xTaskGetTickCountFromISR() ), ( pxHigherPriorityTaskWoken ), 0U )
+
+/**
+ * BaseType_t xTimerStopFromISR( 	TimerHandle_t xTimer,
+ *									BaseType_t *pxHigherPriorityTaskWoken );
+ *
+ * A version of xTimerStop() that can be called from an interrupt service
+ * routine.
+ *
+ * @param xTimer The handle of the timer being stopped.
+ *
+ * @param pxHigherPriorityTaskWoken The timer service/daemon task spends most
+ * of its time in the Blocked state, waiting for messages to arrive on the timer
+ * command queue.  Calling xTimerStopFromISR() writes a message to the timer
+ * command queue, so has the potential to transition the timer service/daemon
+ * task out of the Blocked state.  If calling xTimerStopFromISR() causes the
+ * timer service/daemon task to leave the Blocked state, and the timer service/
+ * daemon task has a priority equal to or greater than the currently executing
+ * task (the task that was interrupted), then *pxHigherPriorityTaskWoken will
+ * get set to pdTRUE internally within the xTimerStopFromISR() function.  If
+ * xTimerStopFromISR() sets this value to pdTRUE then a context switch should
+ * be performed before the interrupt exits.
+ *
+ * @return pdFAIL will be returned if the stop command could not be sent to
+ * the timer command queue.  pdPASS will be returned if the command was
+ * successfully sent to the timer command queue.  When the command is actually
+ * processed will depend on the priority of the timer service/daemon task
+ * relative to other tasks in the system.  The timer service/daemon task
+ * priority is set by the configTIMER_TASK_PRIORITY configuration constant.
+ *
+ * Example usage:
+ * @verbatim
+ * // This scenario assumes xTimer has already been created and started.  When
+ * // an interrupt occurs, the timer should be simply stopped.
+ *
+ * // The interrupt service routine that stops the timer.
+ * void vAnExampleInterruptServiceRoutine( void )
+ * {
+ * BaseType_t xHigherPriorityTaskWoken = pdFALSE;
+ *
+ *     // The interrupt has occurred - simply stop the timer.
+ *     // xHigherPriorityTaskWoken was set to pdFALSE where it was defined
+ *     // (within this function).  As this is an interrupt service routine, only
+ *     // FreeRTOS API functions that end in "FromISR" can be used.
+ *     if( xTimerStopFromISR( xTimer, &xHigherPriorityTaskWoken ) != pdPASS )
+ *     {
+ *         // The stop command was not executed successfully.  Take appropriate
+ *         // action here.
+ *     }
+ *
+ *     // If xHigherPriorityTaskWoken equals pdTRUE, then a context switch
+ *     // should be performed.  The syntax required to perform a context switch
+ *     // from inside an ISR varies from port to port, and from compiler to
+ *     // compiler.  Inspect the demos for the port you are using to find the
+ *     // actual syntax required.
+ *     if( xHigherPriorityTaskWoken != pdFALSE )
+ *     {
+ *         // Call the interrupt safe yield function here (actual function
+ *         // depends on the FreeRTOS port being used).
+ *     }
+ * }
+ * @endverbatim
+ */
+#define xTimerStopFromISR( xTimer, pxHigherPriorityTaskWoken ) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_STOP_FROM_ISR, 0, ( pxHigherPriorityTaskWoken ), 0U )
+
+/**
+ * BaseType_t xTimerChangePeriodFromISR( TimerHandle_t xTimer,
+ *										 TickType_t xNewPeriod,
+ *										 BaseType_t *pxHigherPriorityTaskWoken );
+ *
+ * A version of xTimerChangePeriod() that can be called from an interrupt
+ * service routine.
+ *
+ * @param xTimer The handle of the timer that is having its period changed.
+ *
+ * @param xNewPeriod The new period for xTimer. Timer periods are specified in
+ * tick periods, so the constant portTICK_PERIOD_MS can be used to convert a time
+ * that has been specified in milliseconds.  For example, if the timer must
+ * expire after 100 ticks, then xNewPeriod should be set to 100.  Alternatively,
+ * if the timer must expire after 500ms, then xNewPeriod can be set to
+ * ( 500 / portTICK_PERIOD_MS ) provided configTICK_RATE_HZ is less than
+ * or equal to 1000.
+ *
+ * @param pxHigherPriorityTaskWoken The timer service/daemon task spends most
+ * of its time in the Blocked state, waiting for messages to arrive on the timer
+ * command queue.  Calling xTimerChangePeriodFromISR() writes a message to the
+ * timer command queue, so has the potential to transition the timer service/
+ * daemon task out of the Blocked state.  If calling xTimerChangePeriodFromISR()
+ * causes the timer service/daemon task to leave the Blocked state, and the
+ * timer service/daemon task has a priority equal to or greater than the
+ * currently executing task (the task that was interrupted), then
+ * *pxHigherPriorityTaskWoken will get set to pdTRUE internally within the
+ * xTimerChangePeriodFromISR() function.  If xTimerChangePeriodFromISR() sets
+ * this value to pdTRUE then a context switch should be performed before the
+ * interrupt exits.
+ *
+ * @return pdFAIL will be returned if the command to change the timers period
+ * could not be sent to the timer command queue.  pdPASS will be returned if the
+ * command was successfully sent to the timer command queue.  When the command
+ * is actually processed will depend on the priority of the timer service/daemon
+ * task relative to other tasks in the system.  The timer service/daemon task
+ * priority is set by the configTIMER_TASK_PRIORITY configuration constant.
+ *
+ * Example usage:
+ * @verbatim
+ * // This scenario assumes xTimer has already been created and started.  When
+ * // an interrupt occurs, the period of xTimer should be changed to 500ms.
+ *
+ * // The interrupt service routine that changes the period of xTimer.
+ * void vAnExampleInterruptServiceRoutine( void )
+ * {
+ * BaseType_t xHigherPriorityTaskWoken = pdFALSE;
+ *
+ *     // The interrupt has occurred - change the period of xTimer to 500ms.
+ *     // xHigherPriorityTaskWoken was set to pdFALSE where it was defined
+ *     // (within this function).  As this is an interrupt service routine, only
+ *     // FreeRTOS API functions that end in "FromISR" can be used.
+ *     if( xTimerChangePeriodFromISR( xTimer, &xHigherPriorityTaskWoken ) != pdPASS )
+ *     {
+ *         // The command to change the timers period was not executed
+ *         // successfully.  Take appropriate action here.
+ *     }
+ *
+ *     // If xHigherPriorityTaskWoken equals pdTRUE, then a context switch
+ *     // should be performed.  The syntax required to perform a context switch
+ *     // from inside an ISR varies from port to port, and from compiler to
+ *     // compiler.  Inspect the demos for the port you are using to find the
+ *     // actual syntax required.
+ *     if( xHigherPriorityTaskWoken != pdFALSE )
+ *     {
+ *         // Call the interrupt safe yield function here (actual function
+ *         // depends on the FreeRTOS port being used).
+ *     }
+ * }
+ * @endverbatim
+ */
+#define xTimerChangePeriodFromISR( xTimer, xNewPeriod, pxHigherPriorityTaskWoken ) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_CHANGE_PERIOD_FROM_ISR, ( xNewPeriod ), ( pxHigherPriorityTaskWoken ), 0U )
+
+/**
+ * BaseType_t xTimerResetFromISR( 	TimerHandle_t xTimer,
+ *									BaseType_t *pxHigherPriorityTaskWoken );
+ *
+ * A version of xTimerReset() that can be called from an interrupt service
+ * routine.
+ *
+ * @param xTimer The handle of the timer that is to be started, reset, or
+ * restarted.
+ *
+ * @param pxHigherPriorityTaskWoken The timer service/daemon task spends most
+ * of its time in the Blocked state, waiting for messages to arrive on the timer
+ * command queue.  Calling xTimerResetFromISR() writes a message to the timer
+ * command queue, so has the potential to transition the timer service/daemon
+ * task out of the Blocked state.  If calling xTimerResetFromISR() causes the
+ * timer service/daemon task to leave the Blocked state, and the timer service/
+ * daemon task has a priority equal to or greater than the currently executing
+ * task (the task that was interrupted), then *pxHigherPriorityTaskWoken will
+ * get set to pdTRUE internally within the xTimerResetFromISR() function.  If
+ * xTimerResetFromISR() sets this value to pdTRUE then a context switch should
+ * be performed before the interrupt exits.
+ *
+ * @return pdFAIL will be returned if the reset command could not be sent to
+ * the timer command queue.  pdPASS will be returned if the command was
+ * successfully sent to the timer command queue.  When the command is actually
+ * processed will depend on the priority of the timer service/daemon task
+ * relative to other tasks in the system, although the timers expiry time is
+ * relative to when xTimerResetFromISR() is actually called.  The timer service/daemon
+ * task priority is set by the configTIMER_TASK_PRIORITY configuration constant.
+ *
+ * Example usage:
+ * @verbatim
+ * // This scenario assumes xBacklightTimer has already been created.  When a
+ * // key is pressed, an LCD back-light is switched on.  If 5 seconds pass
+ * // without a key being pressed, then the LCD back-light is switched off.  In
+ * // this case, the timer is a one-shot timer, and unlike the example given for
+ * // the xTimerReset() function, the key press event handler is an interrupt
+ * // service routine.
+ *
+ * // The callback function assigned to the one-shot timer.  In this case the
+ * // parameter is not used.
+ * void vBacklightTimerCallback( TimerHandle_t pxTimer )
+ * {
+ *     // The timer expired, therefore 5 seconds must have passed since a key
+ *     // was pressed.  Switch off the LCD back-light.
+ *     vSetBacklightState( BACKLIGHT_OFF );
+ * }
+ *
+ * // The key press interrupt service routine.
+ * void vKeyPressEventInterruptHandler( void )
+ * {
+ * BaseType_t xHigherPriorityTaskWoken = pdFALSE;
+ *
+ *     // Ensure the LCD back-light is on, then reset the timer that is
+ *     // responsible for turning the back-light off after 5 seconds of
+ *     // key inactivity.  This is an interrupt service routine so can only
+ *     // call FreeRTOS API functions that end in "FromISR".
+ *     vSetBacklightState( BACKLIGHT_ON );
+ *
+ *     // xTimerStartFromISR() or xTimerResetFromISR() could be called here
+ *     // as both cause the timer to re-calculate its expiry time.
+ *     // xHigherPriorityTaskWoken was initialised to pdFALSE when it was
+ *     // declared (in this function).
+ *     if( xTimerResetFromISR( xBacklightTimer, &xHigherPriorityTaskWoken ) != pdPASS )
+ *     {
+ *         // The reset command was not executed successfully.  Take appropriate
+ *         // action here.
+ *     }
+ *
+ *     // Perform the rest of the key processing here.
+ *
+ *     // If xHigherPriorityTaskWoken equals pdTRUE, then a context switch
+ *     // should be performed.  The syntax required to perform a context switch
+ *     // from inside an ISR varies from port to port, and from compiler to
+ *     // compiler.  Inspect the demos for the port you are using to find the
+ *     // actual syntax required.
+ *     if( xHigherPriorityTaskWoken != pdFALSE )
+ *     {
+ *         // Call the interrupt safe yield function here (actual function
+ *         // depends on the FreeRTOS port being used).
+ *     }
+ * }
+ * @endverbatim
+ */
+#define xTimerResetFromISR( xTimer, pxHigherPriorityTaskWoken ) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_RESET_FROM_ISR, ( xTaskGetTickCountFromISR() ), ( pxHigherPriorityTaskWoken ), 0U )
+
+
+/**
+ * BaseType_t xTimerPendFunctionCallFromISR( PendedFunction_t xFunctionToPend,
+ *                                          void *pvParameter1,
+ *                                          uint32_t ulParameter2,
+ *                                          BaseType_t *pxHigherPriorityTaskWoken );
+ *
+ *
+ * Used from application interrupt service routines to defer the execution of a
+ * function to the RTOS daemon task (the timer service task, hence this function
+ * is implemented in timers.c and is prefixed with 'Timer').
+ *
+ * Ideally an interrupt service routine (ISR) is kept as short as possible, but
+ * sometimes an ISR either has a lot of processing to do, or needs to perform
+ * processing that is not deterministic.  In these cases
+ * xTimerPendFunctionCallFromISR() can be used to defer processing of a function
+ * to the RTOS daemon task.
+ *
+ * A mechanism is provided that allows the interrupt to return directly to the
+ * task that will subsequently execute the pended callback function.  This
+ * allows the callback function to execute contiguously in time with the
+ * interrupt - just as if the callback had executed in the interrupt itself.
+ *
+ * @param xFunctionToPend The function to execute from the timer service/
+ * daemon task.  The function must conform to the PendedFunction_t
+ * prototype.
+ *
+ * @param pvParameter1 The value of the callback function's first parameter.
+ * The parameter has a void * type to allow it to be used to pass any type.
+ * For example, unsigned longs can be cast to a void *, or the void * can be
+ * used to point to a structure.
+ *
+ * @param ulParameter2 The value of the callback function's second parameter.
+ *
+ * @param pxHigherPriorityTaskWoken As mentioned above, calling this function
+ * will result in a message being sent to the timer daemon task.  If the
+ * priority of the timer daemon task (which is set using
+ * configTIMER_TASK_PRIORITY in FreeRTOSConfig.h) is higher than the priority of
+ * the currently running task (the task the interrupt interrupted) then
+ * *pxHigherPriorityTaskWoken will be set to pdTRUE within
+ * xTimerPendFunctionCallFromISR(), indicating that a context switch should be
+ * requested before the interrupt exits.  For that reason
+ * *pxHigherPriorityTaskWoken must be initialised to pdFALSE.  See the
+ * example code below.
+ *
+ * @return pdPASS is returned if the message was successfully sent to the
+ * timer daemon task, otherwise pdFALSE is returned.
+ *
+ * Example usage:
+ * @verbatim
+ *
+ *	// The callback function that will execute in the context of the daemon task.
+ *  // Note callback functions must all use this same prototype.
+ *  void vProcessInterface( void *pvParameter1, uint32_t ulParameter2 )
+ *	{
+ *		BaseType_t xInterfaceToService;
+ *
+ *		// The interface that requires servicing is passed in the second
+ *      // parameter.  The first parameter is not used in this case.
+ *		xInterfaceToService = ( BaseType_t ) ulParameter2;
+ *
+ *		// ...Perform the processing here...
+ *	}
+ *
+ *	// An ISR that receives data packets from multiple interfaces
+ *  void vAnISR( void )
+ *	{
+ *		BaseType_t xInterfaceToService, xHigherPriorityTaskWoken;
+ *
+ *		// Query the hardware to determine which interface needs processing.
+ *		xInterfaceToService = prvCheckInterfaces();
+ *
+ *      // The actual processing is to be deferred to a task.  Request the
+ *      // vProcessInterface() callback function is executed, passing in the
+ *		// number of the interface that needs processing.  The interface to
+ *		// service is passed in the second parameter.  The first parameter is
+ *		// not used in this case.
+ *		xHigherPriorityTaskWoken = pdFALSE;
+ *		xTimerPendFunctionCallFromISR( vProcessInterface, NULL, ( uint32_t ) xInterfaceToService, &xHigherPriorityTaskWoken );
+ *
+ *		// If xHigherPriorityTaskWoken is now set to pdTRUE then a context
+ *		// switch should be requested.  The macro used is port specific and will
+ *		// be either portYIELD_FROM_ISR() or portEND_SWITCHING_ISR() - refer to
+ *		// the documentation page for the port being used.
+ *		portYIELD_FROM_ISR( xHigherPriorityTaskWoken );
+ *
+ *	}
+ * @endverbatim
+ */
+BaseType_t xTimerPendFunctionCallFromISR( PendedFunction_t xFunctionToPend, void *pvParameter1, uint32_t ulParameter2, BaseType_t *pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;
+
+ /**
+  * BaseType_t xTimerPendFunctionCall( PendedFunction_t xFunctionToPend,
+  *                                    void *pvParameter1,
+  *                                    uint32_t ulParameter2,
+  *                                    TickType_t xTicksToWait );
+  *
+  *
+  * Used to defer the execution of a function to the RTOS daemon task (the timer
+  * service task, hence this function is implemented in timers.c and is prefixed
+  * with 'Timer').
+  *
+  * @param xFunctionToPend The function to execute from the timer service/
+  * daemon task.  The function must conform to the PendedFunction_t
+  * prototype.
+  *
+  * @param pvParameter1 The value of the callback function's first parameter.
+  * The parameter has a void * type to allow it to be used to pass any type.
+  * For example, unsigned longs can be cast to a void *, or the void * can be
+  * used to point to a structure.
+  *
+  * @param ulParameter2 The value of the callback function's second parameter.
+  *
+  * @param xTicksToWait Calling this function will result in a message being
+  * sent to the timer daemon task on a queue.  xTicksToWait is the amount of
+  * time the calling task should remain in the Blocked state (so not using any
+  * processing time) for space to become available on the timer queue if the
+  * queue is found to be full.
+  *
+  * @return pdPASS is returned if the message was successfully sent to the
+  * timer daemon task, otherwise pdFALSE is returned.
+  *
+  */
+BaseType_t xTimerPendFunctionCall( PendedFunction_t xFunctionToPend, void *pvParameter1, uint32_t ulParameter2, TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+
+/**
+ * const char * const pcTimerGetName( TimerHandle_t xTimer );
+ *
+ * Returns the name that was assigned to a timer when the timer was created.
+ *
+ * @param xTimer The handle of the timer being queried.
+ *
+ * @return The name assigned to the timer specified by the xTimer parameter.
+ */
+const char * pcTimerGetName( TimerHandle_t xTimer ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+
+/**
+ * void vTimerSetReloadMode( TimerHandle_t xTimer, const UBaseType_t uxAutoReload );
+ *
+ * Updates a timer to be either an auto-reload timer, in which case the timer
+ * automatically resets itself each time it expires, or a one-shot timer, in
+ * which case the timer will only expire once unless it is manually restarted.
+ *
+ * @param xTimer The handle of the timer being updated.
+ *
+ * @param uxAutoReload If uxAutoReload is set to pdTRUE then the timer will
+ * expire repeatedly with a frequency set by the timer's period (see the
+ * xTimerPeriodInTicks parameter of the xTimerCreate() API function).  If
+ * uxAutoReload is set to pdFALSE then the timer will be a one-shot timer and
+ * enter the dormant state after it expires.
+ */
+void vTimerSetReloadMode( TimerHandle_t xTimer, const UBaseType_t uxAutoReload ) PRIVILEGED_FUNCTION;
+
+/**
+* UBaseType_t uxTimerGetReloadMode( TimerHandle_t xTimer );
+*
+* Queries a timer to determine if it is an auto-reload timer, in which case the timer
+* automatically resets itself each time it expires, or a one-shot timer, in
+* which case the timer will only expire once unless it is manually restarted.
+*
+* @param xTimer The handle of the timer being queried.
+*
+* @return If the timer is an auto-reload timer then pdTRUE is returned, otherwise
+* pdFALSE is returned.
+*/
+UBaseType_t uxTimerGetReloadMode( TimerHandle_t xTimer ) PRIVILEGED_FUNCTION;
+
+/**
+ * TickType_t xTimerGetPeriod( TimerHandle_t xTimer );
+ *
+ * Returns the period of a timer.
+ *
+ * @param xTimer The handle of the timer being queried.
+ *
+ * @return The period of the timer in ticks.
+ */
+TickType_t xTimerGetPeriod( TimerHandle_t xTimer ) PRIVILEGED_FUNCTION;
+
+/**
+* TickType_t xTimerGetExpiryTime( TimerHandle_t xTimer );
+*
+* Returns the time in ticks at which the timer will expire.  If this is less
+* than the current tick count then the expiry time has overflowed from the
+* current time.
+*
+* @param xTimer The handle of the timer being queried.
+*
+* @return If the timer is running then the time in ticks at which the timer
+* will next expire is returned.  If the timer is not running then the return
+* value is undefined.
+*/
+TickType_t xTimerGetExpiryTime( TimerHandle_t xTimer ) PRIVILEGED_FUNCTION;
+
+/*
+ * Functions beyond this part are not part of the public API and are intended
+ * for use by the kernel only.
+ */
+BaseType_t xTimerCreateTimerTask( void ) PRIVILEGED_FUNCTION;
+BaseType_t xTimerGenericCommand( TimerHandle_t xTimer, const BaseType_t xCommandID, const TickType_t xOptionalValue, BaseType_t * const pxHigherPriorityTaskWoken, const TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+
+#if( configUSE_TRACE_FACILITY == 1 )
+	void vTimerSetTimerNumber( TimerHandle_t xTimer, UBaseType_t uxTimerNumber ) PRIVILEGED_FUNCTION;
+	UBaseType_t uxTimerGetTimerNumber( TimerHandle_t xTimer ) PRIVILEGED_FUNCTION;
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* TIMERS_H */
+
+
+
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/list.c b/Middlewares/Third_Party/FreeRTOS/Source/list.c
new file mode 100644
index 0000000..0e0e72d
--- /dev/null
+++ b/Middlewares/Third_Party/FreeRTOS/Source/list.c
@@ -0,0 +1,198 @@
+/*
+ * FreeRTOS Kernel V10.3.1
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#include <stdlib.h>
+#include "FreeRTOS.h"
+#include "list.h"
+
+/*-----------------------------------------------------------
+ * PUBLIC LIST API documented in list.h
+ *----------------------------------------------------------*/
+
+void vListInitialise( List_t * const pxList )
+{
+	/* The list structure contains a list item which is used to mark the
+	end of the list.  To initialise the list the list end is inserted
+	as the only list entry. */
+	pxList->pxIndex = ( ListItem_t * ) &( pxList->xListEnd );			/*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM.  This is checked and valid. */
+
+	/* The list end value is the highest possible value in the list to
+	ensure it remains at the end of the list. */
+	pxList->xListEnd.xItemValue = portMAX_DELAY;
+
+	/* The list end next and previous pointers point to itself so we know
+	when the list is empty. */
+	pxList->xListEnd.pxNext = ( ListItem_t * ) &( pxList->xListEnd );	/*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM.  This is checked and valid. */
+	pxList->xListEnd.pxPrevious = ( ListItem_t * ) &( pxList->xListEnd );/*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM.  This is checked and valid. */
+
+	pxList->uxNumberOfItems = ( UBaseType_t ) 0U;
+
+	/* Write known values into the list if
+	configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */
+	listSET_LIST_INTEGRITY_CHECK_1_VALUE( pxList );
+	listSET_LIST_INTEGRITY_CHECK_2_VALUE( pxList );
+}
+/*-----------------------------------------------------------*/
+
+void vListInitialiseItem( ListItem_t * const pxItem )
+{
+	/* Make sure the list item is not recorded as being on a list. */
+	pxItem->pxContainer = NULL;
+
+	/* Write known values into the list item if
+	configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */
+	listSET_FIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem );
+	listSET_SECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem );
+}
+/*-----------------------------------------------------------*/
+
+void vListInsertEnd( List_t * const pxList, ListItem_t * const pxNewListItem )
+{
+ListItem_t * const pxIndex = pxList->pxIndex;
+
+	/* Only effective when configASSERT() is also defined, these tests may catch
+	the list data structures being overwritten in memory.  They will not catch
+	data errors caused by incorrect configuration or use of FreeRTOS. */
+	listTEST_LIST_INTEGRITY( pxList );
+	listTEST_LIST_ITEM_INTEGRITY( pxNewListItem );
+
+	/* Insert a new list item into pxList, but rather than sort the list,
+	makes the new list item the last item to be removed by a call to
+	listGET_OWNER_OF_NEXT_ENTRY(). */
+	pxNewListItem->pxNext = pxIndex;
+	pxNewListItem->pxPrevious = pxIndex->pxPrevious;
+
+	/* Only used during decision coverage testing. */
+	mtCOVERAGE_TEST_DELAY();
+
+	pxIndex->pxPrevious->pxNext = pxNewListItem;
+	pxIndex->pxPrevious = pxNewListItem;
+
+	/* Remember which list the item is in. */
+	pxNewListItem->pxContainer = pxList;
+
+	( pxList->uxNumberOfItems )++;
+}
+/*-----------------------------------------------------------*/
+
+void vListInsert( List_t * const pxList, ListItem_t * const pxNewListItem )
+{
+ListItem_t *pxIterator;
+const TickType_t xValueOfInsertion = pxNewListItem->xItemValue;
+
+	/* Only effective when configASSERT() is also defined, these tests may catch
+	the list data structures being overwritten in memory.  They will not catch
+	data errors caused by incorrect configuration or use of FreeRTOS. */
+	listTEST_LIST_INTEGRITY( pxList );
+	listTEST_LIST_ITEM_INTEGRITY( pxNewListItem );
+
+	/* Insert the new list item into the list, sorted in xItemValue order.
+
+	If the list already contains a list item with the same item value then the
+	new list item should be placed after it.  This ensures that TCBs which are
+	stored in ready lists (all of which have the same xItemValue value) get a
+	share of the CPU.  However, if the xItemValue is the same as the back marker
+	the iteration loop below will not end.  Therefore the value is checked
+	first, and the algorithm slightly modified if necessary. */
+	if( xValueOfInsertion == portMAX_DELAY )
+	{
+		pxIterator = pxList->xListEnd.pxPrevious;
+	}
+	else
+	{
+		/* *** NOTE ***********************************************************
+		If you find your application is crashing here then likely causes are
+		listed below.  In addition see https://www.freertos.org/FAQHelp.html for
+		more tips, and ensure configASSERT() is defined!
+		https://www.freertos.org/a00110.html#configASSERT
+
+			1) Stack overflow -
+			   see https://www.freertos.org/Stacks-and-stack-overflow-checking.html
+			2) Incorrect interrupt priority assignment, especially on Cortex-M
+			   parts where numerically high priority values denote low actual
+			   interrupt priorities, which can seem counter intuitive.  See
+			   https://www.freertos.org/RTOS-Cortex-M3-M4.html and the definition
+			   of configMAX_SYSCALL_INTERRUPT_PRIORITY on
+			   https://www.freertos.org/a00110.html
+			3) Calling an API function from within a critical section or when
+			   the scheduler is suspended, or calling an API function that does
+			   not end in "FromISR" from an interrupt.
+			4) Using a queue or semaphore before it has been initialised or
+			   before the scheduler has been started (are interrupts firing
+			   before vTaskStartScheduler() has been called?).
+		**********************************************************************/
+
+		for( pxIterator = ( ListItem_t * ) &( pxList->xListEnd ); pxIterator->pxNext->xItemValue <= xValueOfInsertion; pxIterator = pxIterator->pxNext ) /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM.  This is checked and valid. *//*lint !e440 The iterator moves to a different value, not xValueOfInsertion. */
+		{
+			/* There is nothing to do here, just iterating to the wanted
+			insertion position. */
+		}
+	}
+
+	pxNewListItem->pxNext = pxIterator->pxNext;
+	pxNewListItem->pxNext->pxPrevious = pxNewListItem;
+	pxNewListItem->pxPrevious = pxIterator;
+	pxIterator->pxNext = pxNewListItem;
+
+	/* Remember which list the item is in.  This allows fast removal of the
+	item later. */
+	pxNewListItem->pxContainer = pxList;
+
+	( pxList->uxNumberOfItems )++;
+}
+/*-----------------------------------------------------------*/
+
+UBaseType_t uxListRemove( ListItem_t * const pxItemToRemove )
+{
+/* The list item knows which list it is in.  Obtain the list from the list
+item. */
+List_t * const pxList = pxItemToRemove->pxContainer;
+
+	pxItemToRemove->pxNext->pxPrevious = pxItemToRemove->pxPrevious;
+	pxItemToRemove->pxPrevious->pxNext = pxItemToRemove->pxNext;
+
+	/* Only used during decision coverage testing. */
+	mtCOVERAGE_TEST_DELAY();
+
+	/* Make sure the index is left pointing to a valid item. */
+	if( pxList->pxIndex == pxItemToRemove )
+	{
+		pxList->pxIndex = pxItemToRemove->pxPrevious;
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	pxItemToRemove->pxContainer = NULL;
+	( pxList->uxNumberOfItems )--;
+
+	return pxList->uxNumberOfItems;
+}
+/*-----------------------------------------------------------*/
+
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/port.c b/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/port.c
new file mode 100644
index 0000000..9e1d1a8
--- /dev/null
+++ b/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/port.c
@@ -0,0 +1,775 @@
+/*
+ * FreeRTOS Kernel V10.3.1
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*-----------------------------------------------------------
+ * Implementation of functions defined in portable.h for the ARM CM4F port.
+ *----------------------------------------------------------*/
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+#ifndef __VFP_FP__
+	#error This port can only be used when the project options are configured to enable hardware floating point support.
+#endif
+
+#ifndef configSYSTICK_CLOCK_HZ
+	#define configSYSTICK_CLOCK_HZ configCPU_CLOCK_HZ
+	/* Ensure the SysTick is clocked at the same frequency as the core. */
+	#define portNVIC_SYSTICK_CLK_BIT	( 1UL << 2UL )
+#else
+	/* The way the SysTick is clocked is not modified in case it is not the same
+	as the core. */
+	#define portNVIC_SYSTICK_CLK_BIT	( 0 )
+#endif
+
+/* Constants required to manipulate the core.  Registers first... */
+#define portNVIC_SYSTICK_CTRL_REG			( * ( ( volatile uint32_t * ) 0xe000e010 ) )
+#define portNVIC_SYSTICK_LOAD_REG			( * ( ( volatile uint32_t * ) 0xe000e014 ) )
+#define portNVIC_SYSTICK_CURRENT_VALUE_REG	( * ( ( volatile uint32_t * ) 0xe000e018 ) )
+#define portNVIC_SYSPRI2_REG				( * ( ( volatile uint32_t * ) 0xe000ed20 ) )
+/* ...then bits in the registers. */
+#define portNVIC_SYSTICK_INT_BIT			( 1UL << 1UL )
+#define portNVIC_SYSTICK_ENABLE_BIT			( 1UL << 0UL )
+#define portNVIC_SYSTICK_COUNT_FLAG_BIT		( 1UL << 16UL )
+#define portNVIC_PENDSVCLEAR_BIT 			( 1UL << 27UL )
+#define portNVIC_PEND_SYSTICK_CLEAR_BIT		( 1UL << 25UL )
+
+/* Constants used to detect a Cortex-M7 r0p1 core, which should use the ARM_CM7
+r0p1 port. */
+#define portCPUID							( * ( ( volatile uint32_t * ) 0xE000ed00 ) )
+#define portCORTEX_M7_r0p1_ID				( 0x410FC271UL )
+#define portCORTEX_M7_r0p0_ID				( 0x410FC270UL )
+
+#define portNVIC_PENDSV_PRI					( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )
+#define portNVIC_SYSTICK_PRI				( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )
+
+/* Constants required to check the validity of an interrupt priority. */
+#define portFIRST_USER_INTERRUPT_NUMBER		( 16 )
+#define portNVIC_IP_REGISTERS_OFFSET_16 	( 0xE000E3F0 )
+#define portAIRCR_REG						( * ( ( volatile uint32_t * ) 0xE000ED0C ) )
+#define portMAX_8_BIT_VALUE					( ( uint8_t ) 0xff )
+#define portTOP_BIT_OF_BYTE					( ( uint8_t ) 0x80 )
+#define portMAX_PRIGROUP_BITS				( ( uint8_t ) 7 )
+#define portPRIORITY_GROUP_MASK				( 0x07UL << 8UL )
+#define portPRIGROUP_SHIFT					( 8UL )
+
+/* Masks off all bits but the VECTACTIVE bits in the ICSR register. */
+#define portVECTACTIVE_MASK					( 0xFFUL )
+
+/* Constants required to manipulate the VFP. */
+#define portFPCCR							( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating point context control register. */
+#define portASPEN_AND_LSPEN_BITS			( 0x3UL << 30UL )
+
+/* Constants required to set up the initial stack. */
+#define portINITIAL_XPSR					( 0x01000000 )
+#define portINITIAL_EXC_RETURN				( 0xfffffffd )
+
+/* The systick is a 24-bit counter. */
+#define portMAX_24_BIT_NUMBER				( 0xffffffUL )
+
+/* For strict compliance with the Cortex-M spec the task start address should
+have bit-0 clear, as it is loaded into the PC on exit from an ISR. */
+#define portSTART_ADDRESS_MASK		( ( StackType_t ) 0xfffffffeUL )
+
+/* A fiddle factor to estimate the number of SysTick counts that would have
+occurred while the SysTick counter is stopped during tickless idle
+calculations. */
+#define portMISSED_COUNTS_FACTOR			( 45UL )
+
+/* Let the user override the pre-loading of the initial LR with the address of
+prvTaskExitError() in case it messes up unwinding of the stack in the
+debugger. */
+#ifdef configTASK_RETURN_ADDRESS
+	#define portTASK_RETURN_ADDRESS	configTASK_RETURN_ADDRESS
+#else
+	#define portTASK_RETURN_ADDRESS	prvTaskExitError
+#endif
+
+/*
+ * Setup the timer to generate the tick interrupts.  The implementation in this
+ * file is weak to allow application writers to change the timer used to
+ * generate the tick interrupt.
+ */
+void vPortSetupTimerInterrupt( void );
+
+/*
+ * Exception handlers.
+ */
+void xPortPendSVHandler( void ) __attribute__ (( naked ));
+void xPortSysTickHandler( void );
+void vPortSVCHandler( void ) __attribute__ (( naked ));
+
+/*
+ * Start first task is a separate function so it can be tested in isolation.
+ */
+static void prvPortStartFirstTask( void ) __attribute__ (( naked ));
+
+/*
+ * Function to enable the VFP.
+ */
+static void vPortEnableVFP( void ) __attribute__ (( naked ));
+
+/*
+ * Used to catch tasks that attempt to return from their implementing function.
+ */
+static void prvTaskExitError( void );
+
+/*-----------------------------------------------------------*/
+
+/* Each task maintains its own interrupt status in the critical nesting
+variable. */
+static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;
+
+/*
+ * The number of SysTick increments that make up one tick period.
+ */
+#if( configUSE_TICKLESS_IDLE == 1 )
+	static uint32_t ulTimerCountsForOneTick = 0;
+#endif /* configUSE_TICKLESS_IDLE */
+
+/*
+ * The maximum number of tick periods that can be suppressed is limited by the
+ * 24 bit resolution of the SysTick timer.
+ */
+#if( configUSE_TICKLESS_IDLE == 1 )
+	static uint32_t xMaximumPossibleSuppressedTicks = 0;
+#endif /* configUSE_TICKLESS_IDLE */
+
+/*
+ * Compensate for the CPU cycles that pass while the SysTick is stopped (low
+ * power functionality only.
+ */
+#if( configUSE_TICKLESS_IDLE == 1 )
+	static uint32_t ulStoppedTimerCompensation = 0;
+#endif /* configUSE_TICKLESS_IDLE */
+
+/*
+ * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure
+ * FreeRTOS API functions are not called from interrupts that have been assigned
+ * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.
+ */
+#if( configASSERT_DEFINED == 1 )
+	 static uint8_t ucMaxSysCallPriority = 0;
+	 static uint32_t ulMaxPRIGROUPValue = 0;
+	 static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * const ) portNVIC_IP_REGISTERS_OFFSET_16;
+#endif /* configASSERT_DEFINED */
+
+/*-----------------------------------------------------------*/
+
+/*
+ * See header file for description.
+ */
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+{
+	/* Simulate the stack frame as it would be created by a context switch
+	interrupt. */
+
+	/* Offset added to account for the way the MCU uses the stack on entry/exit
+	of interrupts, and to ensure alignment. */
+	pxTopOfStack--;
+
+	*pxTopOfStack = portINITIAL_XPSR;	/* xPSR */
+	pxTopOfStack--;
+	*pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK;	/* PC */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS;	/* LR */
+
+	/* Save code space by skipping register initialisation. */
+	pxTopOfStack -= 5;	/* R12, R3, R2 and R1. */
+	*pxTopOfStack = ( StackType_t ) pvParameters;	/* R0 */
+
+	/* A save method is being used that requires each task to maintain its
+	own exec return value. */
+	pxTopOfStack--;
+	*pxTopOfStack = portINITIAL_EXC_RETURN;
+
+	pxTopOfStack -= 8;	/* R11, R10, R9, R8, R7, R6, R5 and R4. */
+
+	return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+static void prvTaskExitError( void )
+{
+volatile uint32_t ulDummy = 0;
+
+	/* A function that implements a task must not exit or attempt to return to
+	its caller as there is nothing to return to.  If a task wants to exit it
+	should instead call vTaskDelete( NULL ).
+
+	Artificially force an assert() to be triggered if configASSERT() is
+	defined, then stop here so application writers can catch the error. */
+	configASSERT( uxCriticalNesting == ~0UL );
+	portDISABLE_INTERRUPTS();
+	while( ulDummy == 0 )
+	{
+		/* This file calls prvTaskExitError() after the scheduler has been
+		started to remove a compiler warning about the function being defined
+		but never called.  ulDummy is used purely to quieten other warnings
+		about code appearing after this function is called - making ulDummy
+		volatile makes the compiler think the function could return and
+		therefore not output an 'unreachable code' warning for code that appears
+		after it. */
+	}
+}
+/*-----------------------------------------------------------*/
+
+void vPortSVCHandler( void )
+{
+	__asm volatile (
+					"	ldr	r3, pxCurrentTCBConst2		\n" /* Restore the context. */
+					"	ldr r1, [r3]					\n" /* Use pxCurrentTCBConst to get the pxCurrentTCB address. */
+					"	ldr r0, [r1]					\n" /* The first item in pxCurrentTCB is the task top of stack. */
+					"	ldmia r0!, {r4-r11, r14}		\n" /* Pop the registers that are not automatically saved on exception entry and the critical nesting count. */
+					"	msr psp, r0						\n" /* Restore the task stack pointer. */
+					"	isb								\n"
+					"	mov r0, #0 						\n"
+					"	msr	basepri, r0					\n"
+					"	bx r14							\n"
+					"									\n"
+					"	.align 4						\n"
+					"pxCurrentTCBConst2: .word pxCurrentTCB				\n"
+				);
+}
+/*-----------------------------------------------------------*/
+
+static void prvPortStartFirstTask( void )
+{
+	/* Start the first task.  This also clears the bit that indicates the FPU is
+	in use in case the FPU was used before the scheduler was started - which
+	would otherwise result in the unnecessary leaving of space in the SVC stack
+	for lazy saving of FPU registers. */
+	__asm volatile(
+					" ldr r0, =0xE000ED08 	\n" /* Use the NVIC offset register to locate the stack. */
+					" ldr r0, [r0] 			\n"
+					" ldr r0, [r0] 			\n"
+					" msr msp, r0			\n" /* Set the msp back to the start of the stack. */
+					" mov r0, #0			\n" /* Clear the bit that indicates the FPU is in use, see comment above. */
+					" msr control, r0		\n"
+					" cpsie i				\n" /* Globally enable interrupts. */
+					" cpsie f				\n"
+					" dsb					\n"
+					" isb					\n"
+					" svc 0					\n" /* System call to start first task. */
+					" nop					\n"
+				);
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * See header file for description.
+ */
+BaseType_t xPortStartScheduler( void )
+{
+	/* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.
+	See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
+	configASSERT( configMAX_SYSCALL_INTERRUPT_PRIORITY );
+
+	/* This port can be used on all revisions of the Cortex-M7 core other than
+	the r0p1 parts.  r0p1 parts should use the port from the
+	/source/portable/GCC/ARM_CM7/r0p1 directory. */
+	configASSERT( portCPUID != portCORTEX_M7_r0p1_ID );
+	configASSERT( portCPUID != portCORTEX_M7_r0p0_ID );
+
+	#if( configASSERT_DEFINED == 1 )
+	{
+		volatile uint32_t ulOriginalPriority;
+		volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );
+		volatile uint8_t ucMaxPriorityValue;
+
+		/* Determine the maximum priority from which ISR safe FreeRTOS API
+		functions can be called.  ISR safe functions are those that end in
+		"FromISR".  FreeRTOS maintains separate thread and ISR API functions to
+		ensure interrupt entry is as fast and simple as possible.
+
+		Save the interrupt priority value that is about to be clobbered. */
+		ulOriginalPriority = *pucFirstUserPriorityRegister;
+
+		/* Determine the number of priority bits available.  First write to all
+		possible bits. */
+		*pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
+
+		/* Read the value back to see how many bits stuck. */
+		ucMaxPriorityValue = *pucFirstUserPriorityRegister;
+
+		/* Use the same mask on the maximum system call priority. */
+		ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
+
+		/* Calculate the maximum acceptable priority group value for the number
+		of bits read back. */
+		ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
+		while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
+		{
+			ulMaxPRIGROUPValue--;
+			ucMaxPriorityValue <<= ( uint8_t ) 0x01;
+		}
+
+		#ifdef __NVIC_PRIO_BITS
+		{
+			/* Check the CMSIS configuration that defines the number of
+			priority bits matches the number of priority bits actually queried
+			from the hardware. */
+			configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == __NVIC_PRIO_BITS );
+		}
+		#endif
+
+		#ifdef configPRIO_BITS
+		{
+			/* Check the FreeRTOS configuration that defines the number of
+			priority bits matches the number of priority bits actually queried
+			from the hardware. */
+			configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS );
+		}
+		#endif
+
+		/* Shift the priority group value back to its position within the AIRCR
+		register. */
+		ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
+		ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
+
+		/* Restore the clobbered interrupt priority register to its original
+		value. */
+		*pucFirstUserPriorityRegister = ulOriginalPriority;
+	}
+	#endif /* conifgASSERT_DEFINED */
+
+	/* Make PendSV and SysTick the lowest priority interrupts. */
+	portNVIC_SYSPRI2_REG |= portNVIC_PENDSV_PRI;
+	portNVIC_SYSPRI2_REG |= portNVIC_SYSTICK_PRI;
+
+	/* Start the timer that generates the tick ISR.  Interrupts are disabled
+	here already. */
+	vPortSetupTimerInterrupt();
+
+	/* Initialise the critical nesting count ready for the first task. */
+	uxCriticalNesting = 0;
+
+	/* Ensure the VFP is enabled - it should be anyway. */
+	vPortEnableVFP();
+
+	/* Lazy save always. */
+	*( portFPCCR ) |= portASPEN_AND_LSPEN_BITS;
+
+	/* Start the first task. */
+	prvPortStartFirstTask();
+
+	/* Should never get here as the tasks will now be executing!  Call the task
+	exit error function to prevent compiler warnings about a static function
+	not being called in the case that the application writer overrides this
+	functionality by defining configTASK_RETURN_ADDRESS.  Call
+	vTaskSwitchContext() so link time optimisation does not remove the
+	symbol. */
+	vTaskSwitchContext();
+	prvTaskExitError();
+
+	/* Should not get here! */
+	return 0;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+	/* Not implemented in ports where there is nothing to return to.
+	Artificially force an assert. */
+	configASSERT( uxCriticalNesting == 1000UL );
+}
+/*-----------------------------------------------------------*/
+
+void vPortEnterCritical( void )
+{
+	portDISABLE_INTERRUPTS();
+	uxCriticalNesting++;
+
+	/* This is not the interrupt safe version of the enter critical function so
+	assert() if it is being called from an interrupt context.  Only API
+	functions that end in "FromISR" can be used in an interrupt.  Only assert if
+	the critical nesting count is 1 to protect against recursive calls if the
+	assert function also uses a critical section. */
+	if( uxCriticalNesting == 1 )
+	{
+		configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 );
+	}
+}
+/*-----------------------------------------------------------*/
+
+void vPortExitCritical( void )
+{
+	configASSERT( uxCriticalNesting );
+	uxCriticalNesting--;
+	if( uxCriticalNesting == 0 )
+	{
+		portENABLE_INTERRUPTS();
+	}
+}
+/*-----------------------------------------------------------*/
+
+void xPortPendSVHandler( void )
+{
+	/* This is a naked function. */
+
+	__asm volatile
+	(
+	"	mrs r0, psp							\n"
+	"	isb									\n"
+	"										\n"
+	"	ldr	r3, pxCurrentTCBConst			\n" /* Get the location of the current TCB. */
+	"	ldr	r2, [r3]						\n"
+	"										\n"
+	"	tst r14, #0x10						\n" /* Is the task using the FPU context?  If so, push high vfp registers. */
+	"	it eq								\n"
+	"	vstmdbeq r0!, {s16-s31}				\n"
+	"										\n"
+	"	stmdb r0!, {r4-r11, r14}			\n" /* Save the core registers. */
+	"	str r0, [r2]						\n" /* Save the new top of stack into the first member of the TCB. */
+	"										\n"
+	"	stmdb sp!, {r0, r3}					\n"
+	"	mov r0, %0 							\n"
+	"	msr basepri, r0						\n"
+	"	dsb									\n"
+	"	isb									\n"
+	"	bl vTaskSwitchContext				\n"
+	"	mov r0, #0							\n"
+	"	msr basepri, r0						\n"
+	"	ldmia sp!, {r0, r3}					\n"
+	"										\n"
+	"	ldr r1, [r3]						\n" /* The first item in pxCurrentTCB is the task top of stack. */
+	"	ldr r0, [r1]						\n"
+	"										\n"
+	"	ldmia r0!, {r4-r11, r14}			\n" /* Pop the core registers. */
+	"										\n"
+	"	tst r14, #0x10						\n" /* Is the task using the FPU context?  If so, pop the high vfp registers too. */
+	"	it eq								\n"
+	"	vldmiaeq r0!, {s16-s31}				\n"
+	"										\n"
+	"	msr psp, r0							\n"
+	"	isb									\n"
+	"										\n"
+	#ifdef WORKAROUND_PMU_CM001 /* XMC4000 specific errata workaround. */
+		#if WORKAROUND_PMU_CM001 == 1
+	"			push { r14 }				\n"
+	"			pop { pc }					\n"
+		#endif
+	#endif
+	"										\n"
+	"	bx r14								\n"
+	"										\n"
+	"	.align 4							\n"
+	"pxCurrentTCBConst: .word pxCurrentTCB	\n"
+	::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY)
+	);
+}
+/*-----------------------------------------------------------*/
+
+void xPortSysTickHandler( void )
+{
+	/* The SysTick runs at the lowest interrupt priority, so when this interrupt
+	executes all interrupts must be unmasked.  There is therefore no need to
+	save and then restore the interrupt mask value as its value is already
+	known. */
+	portDISABLE_INTERRUPTS();
+	{
+		/* Increment the RTOS tick. */
+		if( xTaskIncrementTick() != pdFALSE )
+		{
+			/* A context switch is required.  Context switching is performed in
+			the PendSV interrupt.  Pend the PendSV interrupt. */
+			portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
+		}
+	}
+	portENABLE_INTERRUPTS();
+}
+/*-----------------------------------------------------------*/
+
+#if( configUSE_TICKLESS_IDLE == 1 )
+
+	__attribute__((weak)) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
+	{
+	uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements;
+	TickType_t xModifiableIdleTime;
+
+		/* Make sure the SysTick reload value does not overflow the counter. */
+		if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )
+		{
+			xExpectedIdleTime = xMaximumPossibleSuppressedTicks;
+		}
+
+		/* Stop the SysTick momentarily.  The time the SysTick is stopped for
+		is accounted for as best it can be, but using the tickless mode will
+		inevitably result in some tiny drift of the time maintained by the
+		kernel with respect to calendar time. */
+		portNVIC_SYSTICK_CTRL_REG &= ~portNVIC_SYSTICK_ENABLE_BIT;
+
+		/* Calculate the reload value required to wait xExpectedIdleTime
+		tick periods.  -1 is used because this code will execute part way
+		through one of the tick periods. */
+		ulReloadValue = portNVIC_SYSTICK_CURRENT_VALUE_REG + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );
+		if( ulReloadValue > ulStoppedTimerCompensation )
+		{
+			ulReloadValue -= ulStoppedTimerCompensation;
+		}
+
+		/* Enter a critical section but don't use the taskENTER_CRITICAL()
+		method as that will mask interrupts that should exit sleep mode. */
+		__asm volatile( "cpsid i" ::: "memory" );
+		__asm volatile( "dsb" );
+		__asm volatile( "isb" );
+
+		/* If a context switch is pending or a task is waiting for the scheduler
+		to be unsuspended then abandon the low power entry. */
+		if( eTaskConfirmSleepModeStatus() == eAbortSleep )
+		{
+			/* Restart from whatever is left in the count register to complete
+			this tick period. */
+			portNVIC_SYSTICK_LOAD_REG = portNVIC_SYSTICK_CURRENT_VALUE_REG;
+
+			/* Restart SysTick. */
+			portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
+
+			/* Reset the reload register to the value required for normal tick
+			periods. */
+			portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
+
+			/* Re-enable interrupts - see comments above the cpsid instruction()
+			above. */
+			__asm volatile( "cpsie i" ::: "memory" );
+		}
+		else
+		{
+			/* Set the new reload value. */
+			portNVIC_SYSTICK_LOAD_REG = ulReloadValue;
+
+			/* Clear the SysTick count flag and set the count value back to
+			zero. */
+			portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
+
+			/* Restart SysTick. */
+			portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
+
+			/* Sleep until something happens.  configPRE_SLEEP_PROCESSING() can
+			set its parameter to 0 to indicate that its implementation contains
+			its own wait for interrupt or wait for event instruction, and so wfi
+			should not be executed again.  However, the original expected idle
+			time variable must remain unmodified, so a copy is taken. */
+			xModifiableIdleTime = xExpectedIdleTime;
+			configPRE_SLEEP_PROCESSING( xModifiableIdleTime );
+			if( xModifiableIdleTime > 0 )
+			{
+				__asm volatile( "dsb" ::: "memory" );
+				__asm volatile( "wfi" );
+				__asm volatile( "isb" );
+			}
+			configPOST_SLEEP_PROCESSING( xExpectedIdleTime );
+
+			/* Re-enable interrupts to allow the interrupt that brought the MCU
+			out of sleep mode to execute immediately.  see comments above
+			__disable_interrupt() call above. */
+			__asm volatile( "cpsie i" ::: "memory" );
+			__asm volatile( "dsb" );
+			__asm volatile( "isb" );
+
+			/* Disable interrupts again because the clock is about to be stopped
+			and interrupts that execute while the clock is stopped will increase
+			any slippage between the time maintained by the RTOS and calendar
+			time. */
+			__asm volatile( "cpsid i" ::: "memory" );
+			__asm volatile( "dsb" );
+			__asm volatile( "isb" );
+
+			/* Disable the SysTick clock without reading the
+			portNVIC_SYSTICK_CTRL_REG register to ensure the
+			portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set.  Again,
+			the time the SysTick is stopped for is accounted for as best it can
+			be, but using the tickless mode will inevitably result in some tiny
+			drift of the time maintained by the kernel with respect to calendar
+			time*/
+			portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT );
+
+			/* Determine if the SysTick clock has already counted to zero and
+			been set back to the current reload value (the reload back being
+			correct for the entire expected idle time) or if the SysTick is yet
+			to count to zero (in which case an interrupt other than the SysTick
+			must have brought the system out of sleep mode). */
+			if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )
+			{
+				uint32_t ulCalculatedLoadValue;
+
+				/* The tick interrupt is already pending, and the SysTick count
+				reloaded with ulReloadValue.  Reset the
+				portNVIC_SYSTICK_LOAD_REG with whatever remains of this tick
+				period. */
+				ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );
+
+				/* Don't allow a tiny value, or values that have somehow
+				underflowed because the post sleep hook did something
+				that took too long. */
+				if( ( ulCalculatedLoadValue < ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) )
+				{
+					ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL );
+				}
+
+				portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue;
+
+				/* As the pending tick will be processed as soon as this
+				function exits, the tick value maintained by the tick is stepped
+				forward by one less than the time spent waiting. */
+				ulCompleteTickPeriods = xExpectedIdleTime - 1UL;
+			}
+			else
+			{
+				/* Something other than the tick interrupt ended the sleep.
+				Work out how long the sleep lasted rounded to complete tick
+				periods (not the ulReload value which accounted for part
+				ticks). */
+				ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - portNVIC_SYSTICK_CURRENT_VALUE_REG;
+
+				/* How many complete tick periods passed while the processor
+				was waiting? */
+				ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick;
+
+				/* The reload value is set to whatever fraction of a single tick
+				period remains. */
+				portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;
+			}
+
+			/* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG
+			again, then set portNVIC_SYSTICK_LOAD_REG back to its standard
+			value. */
+			portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
+			portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
+			vTaskStepTick( ulCompleteTickPeriods );
+			portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
+
+			/* Exit with interrupts enabled. */
+			__asm volatile( "cpsie i" ::: "memory" );
+		}
+	}
+
+#endif /* #if configUSE_TICKLESS_IDLE */
+/*-----------------------------------------------------------*/
+
+/*
+ * Setup the systick timer to generate the tick interrupts at the required
+ * frequency.
+ */
+__attribute__(( weak )) void vPortSetupTimerInterrupt( void )
+{
+	/* Calculate the constants required to configure the tick interrupt. */
+	#if( configUSE_TICKLESS_IDLE == 1 )
+	{
+		ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );
+		xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;
+		ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );
+	}
+	#endif /* configUSE_TICKLESS_IDLE */
+
+	/* Stop and clear the SysTick. */
+	portNVIC_SYSTICK_CTRL_REG = 0UL;
+	portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
+
+	/* Configure SysTick to interrupt at the requested rate. */
+	portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
+	portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT );
+}
+/*-----------------------------------------------------------*/
+
+/* This is a naked function. */
+static void vPortEnableVFP( void )
+{
+	__asm volatile
+	(
+		"	ldr.w r0, =0xE000ED88		\n" /* The FPU enable bits are in the CPACR. */
+		"	ldr r1, [r0]				\n"
+		"								\n"
+		"	orr r1, r1, #( 0xf << 20 )	\n" /* Enable CP10 and CP11 coprocessors, then save back. */
+		"	str r1, [r0]				\n"
+		"	bx r14						"
+	);
+}
+/*-----------------------------------------------------------*/
+
+#if( configASSERT_DEFINED == 1 )
+
+	void vPortValidateInterruptPriority( void )
+	{
+	uint32_t ulCurrentInterrupt;
+	uint8_t ucCurrentPriority;
+
+		/* Obtain the number of the currently executing interrupt. */
+		__asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) :: "memory" );
+
+		/* Is the interrupt number a user defined interrupt? */
+		if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )
+		{
+			/* Look up the interrupt's priority. */
+			ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];
+
+			/* The following assertion will fail if a service routine (ISR) for
+			an interrupt that has been assigned a priority above
+			configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
+			function.  ISR safe FreeRTOS API functions must *only* be called
+			from interrupts that have been assigned a priority at or below
+			configMAX_SYSCALL_INTERRUPT_PRIORITY.
+
+			Numerically low interrupt priority numbers represent logically high
+			interrupt priorities, therefore the priority of the interrupt must
+			be set to a value equal to or numerically *higher* than
+			configMAX_SYSCALL_INTERRUPT_PRIORITY.
+
+			Interrupts that	use the FreeRTOS API must not be left at their
+			default priority of	zero as that is the highest possible priority,
+			which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY,
+			and	therefore also guaranteed to be invalid.
+
+			FreeRTOS maintains separate thread and ISR API functions to ensure
+			interrupt entry is as fast and simple as possible.
+
+			The following links provide detailed information:
+			http://www.freertos.org/RTOS-Cortex-M3-M4.html
+			http://www.freertos.org/FAQHelp.html */
+			configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
+		}
+
+		/* Priority grouping:  The interrupt controller (NVIC) allows the bits
+		that define each interrupt's priority to be split between bits that
+		define the interrupt's pre-emption priority bits and bits that define
+		the interrupt's sub-priority.  For simplicity all bits must be defined
+		to be pre-emption priority bits.  The following assertion will fail if
+		this is not the case (if some bits represent a sub-priority).
+
+		If the application only uses CMSIS libraries for interrupt
+		configuration then the correct setting can be achieved on all Cortex-M
+		devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the
+		scheduler.  Note however that some vendor specific peripheral libraries
+		assume a non-zero priority group setting, in which cases using a value
+		of zero will result in unpredictable behaviour. */
+		configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
+	}
+
+#endif /* configASSERT_DEFINED */
+
+
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/portmacro.h b/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/portmacro.h
new file mode 100644
index 0000000..e1e7fad
--- /dev/null
+++ b/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/portmacro.h
@@ -0,0 +1,243 @@
+/*
+ * FreeRTOS Kernel V10.3.1
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+#define portCHAR		char
+#define portFLOAT		float
+#define portDOUBLE		double
+#define portLONG		long
+#define portSHORT		short
+#define portSTACK_TYPE	uint32_t
+#define portBASE_TYPE	long
+
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
+
+#if( configUSE_16_BIT_TICKS == 1 )
+	typedef uint16_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+	typedef uint32_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+
+	/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+	not need to be guarded with a critical section. */
+	#define portTICK_TYPE_IS_ATOMIC 1
+#endif
+/*-----------------------------------------------------------*/
+
+/* Architecture specifics. */
+#define portSTACK_GROWTH			( -1 )
+#define portTICK_PERIOD_MS			( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT			8
+/*-----------------------------------------------------------*/
+
+/* Scheduler utilities. */
+#define portYIELD() 															\
+{																				\
+	/* Set a PendSV to request a context switch. */								\
+	portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;								\
+																				\
+	/* Barriers are normally not required but do ensure the code is completely	\
+	within the specified behaviour for the architecture. */						\
+	__asm volatile( "dsb" ::: "memory" );										\
+	__asm volatile( "isb" );													\
+}
+
+#define portNVIC_INT_CTRL_REG		( * ( ( volatile uint32_t * ) 0xe000ed04 ) )
+#define portNVIC_PENDSVSET_BIT		( 1UL << 28UL )
+#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired != pdFALSE ) portYIELD()
+#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
+/*-----------------------------------------------------------*/
+
+/* Critical section management. */
+extern void vPortEnterCritical( void );
+extern void vPortExitCritical( void );
+#define portSET_INTERRUPT_MASK_FROM_ISR()		ulPortRaiseBASEPRI()
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x)	vPortSetBASEPRI(x)
+#define portDISABLE_INTERRUPTS()				vPortRaiseBASEPRI()
+#define portENABLE_INTERRUPTS()					vPortSetBASEPRI(0)
+#define portENTER_CRITICAL()					vPortEnterCritical()
+#define portEXIT_CRITICAL()						vPortExitCritical()
+
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site.  These are
+not necessary for to use this port.  They are defined so the common demo files
+(which build with all the ports) will build. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+/*-----------------------------------------------------------*/
+
+/* Tickless idle/low power functionality. */
+#ifndef portSUPPRESS_TICKS_AND_SLEEP
+	extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
+	#define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime )
+#endif
+/*-----------------------------------------------------------*/
+
+/* Architecture specific optimisations. */
+#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
+	#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
+#endif
+
+#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
+
+	/* Generic helper function. */
+	__attribute__( ( always_inline ) ) static inline uint8_t ucPortCountLeadingZeros( uint32_t ulBitmap )
+	{
+	uint8_t ucReturn;
+
+		__asm volatile ( "clz %0, %1" : "=r" ( ucReturn ) : "r" ( ulBitmap ) : "memory" );
+		return ucReturn;
+	}
+
+	/* Check the configuration. */
+	#if( configMAX_PRIORITIES > 32 )
+		#error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
+	#endif
+
+	/* Store/clear the ready priorities in a bit map. */
+	#define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+	#define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+
+	/*-----------------------------------------------------------*/
+
+	#define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( uint32_t ) ucPortCountLeadingZeros( ( uxReadyPriorities ) ) )
+
+#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+
+/*-----------------------------------------------------------*/
+
+#ifdef configASSERT
+	void vPortValidateInterruptPriority( void );
+	#define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() 	vPortValidateInterruptPriority()
+#endif
+
+/* portNOP() is not required by this port. */
+#define portNOP()
+
+#define portINLINE	__inline
+
+#ifndef portFORCE_INLINE
+	#define portFORCE_INLINE inline __attribute__(( always_inline))
+#endif
+
+portFORCE_INLINE static BaseType_t xPortIsInsideInterrupt( void )
+{
+uint32_t ulCurrentInterrupt;
+BaseType_t xReturn;
+
+	/* Obtain the number of the currently executing interrupt. */
+	__asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) :: "memory" );
+
+	if( ulCurrentInterrupt == 0 )
+	{
+		xReturn = pdFALSE;
+	}
+	else
+	{
+		xReturn = pdTRUE;
+	}
+
+	return xReturn;
+}
+
+/*-----------------------------------------------------------*/
+
+portFORCE_INLINE static void vPortRaiseBASEPRI( void )
+{
+uint32_t ulNewBASEPRI;
+
+	__asm volatile
+	(
+		"	mov %0, %1												\n"	\
+		"	msr basepri, %0											\n" \
+		"	isb														\n" \
+		"	dsb														\n" \
+		:"=r" (ulNewBASEPRI) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
+	);
+}
+
+/*-----------------------------------------------------------*/
+
+portFORCE_INLINE static uint32_t ulPortRaiseBASEPRI( void )
+{
+uint32_t ulOriginalBASEPRI, ulNewBASEPRI;
+
+	__asm volatile
+	(
+		"	mrs %0, basepri											\n" \
+		"	mov %1, %2												\n"	\
+		"	msr basepri, %1											\n" \
+		"	isb														\n" \
+		"	dsb														\n" \
+		:"=r" (ulOriginalBASEPRI), "=r" (ulNewBASEPRI) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
+	);
+
+	/* This return will not be reached but is necessary to prevent compiler
+	warnings. */
+	return ulOriginalBASEPRI;
+}
+/*-----------------------------------------------------------*/
+
+portFORCE_INLINE static void vPortSetBASEPRI( uint32_t ulNewMaskValue )
+{
+	__asm volatile
+	(
+		"	msr basepri, %0	" :: "r" ( ulNewMaskValue ) : "memory"
+	);
+}
+/*-----------------------------------------------------------*/
+
+#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" )
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */
+
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.c b/Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.c
new file mode 100644
index 0000000..a266144
--- /dev/null
+++ b/Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.c
@@ -0,0 +1,492 @@
+/*
+ * FreeRTOS Kernel V10.3.1
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*
+ * A sample implementation of pvPortMalloc() and vPortFree() that combines
+ * (coalescences) adjacent memory blocks as they are freed, and in so doing
+ * limits memory fragmentation.
+ *
+ * See heap_1.c, heap_2.c and heap_3.c for alternative implementations, and the
+ * memory management pages of http://www.FreeRTOS.org for more information.
+ */
+#include <stdlib.h>
+
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
+all the API functions to use the MPU wrappers.  That should only be done when
+task.h is included from an application file. */
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+#include "FreeRTOS.h"
+#include "task.h"
+
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+#if( configSUPPORT_DYNAMIC_ALLOCATION == 0 )
+	#error This file must not be used if configSUPPORT_DYNAMIC_ALLOCATION is 0
+#endif
+
+/* Block sizes must not get too small. */
+#define heapMINIMUM_BLOCK_SIZE	( ( size_t ) ( xHeapStructSize << 1 ) )
+
+/* Assumes 8bit bytes! */
+#define heapBITS_PER_BYTE		( ( size_t ) 8 )
+
+/* Allocate the memory for the heap. */
+#if( configAPPLICATION_ALLOCATED_HEAP == 1 )
+	/* The application writer has already defined the array used for the RTOS
+	heap - probably so it can be placed in a special segment or address. */
+	extern uint8_t ucHeap[ configTOTAL_HEAP_SIZE ];
+#else
+	static uint8_t ucHeap[ configTOTAL_HEAP_SIZE ];
+#endif /* configAPPLICATION_ALLOCATED_HEAP */
+
+/* Define the linked list structure.  This is used to link free blocks in order
+of their memory address. */
+typedef struct A_BLOCK_LINK
+{
+	struct A_BLOCK_LINK *pxNextFreeBlock;	/*<< The next free block in the list. */
+	size_t xBlockSize;						/*<< The size of the free block. */
+} BlockLink_t;
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Inserts a block of memory that is being freed into the correct position in
+ * the list of free memory blocks.  The block being freed will be merged with
+ * the block in front it and/or the block behind it if the memory blocks are
+ * adjacent to each other.
+ */
+static void prvInsertBlockIntoFreeList( BlockLink_t *pxBlockToInsert );
+
+/*
+ * Called automatically to setup the required heap structures the first time
+ * pvPortMalloc() is called.
+ */
+static void prvHeapInit( void );
+
+/*-----------------------------------------------------------*/
+
+/* The size of the structure placed at the beginning of each allocated memory
+block must by correctly byte aligned. */
+static const size_t xHeapStructSize	= ( sizeof( BlockLink_t ) + ( ( size_t ) ( portBYTE_ALIGNMENT - 1 ) ) ) & ~( ( size_t ) portBYTE_ALIGNMENT_MASK );
+
+/* Create a couple of list links to mark the start and end of the list. */
+static BlockLink_t xStart, *pxEnd = NULL;
+
+/* Keeps track of the number of calls to allocate and free memory as well as the
+number of free bytes remaining, but says nothing about fragmentation. */
+static size_t xFreeBytesRemaining = 0U;
+static size_t xMinimumEverFreeBytesRemaining = 0U;
+static size_t xNumberOfSuccessfulAllocations = 0;
+static size_t xNumberOfSuccessfulFrees = 0;
+
+/* Gets set to the top bit of an size_t type.  When this bit in the xBlockSize
+member of an BlockLink_t structure is set then the block belongs to the
+application.  When the bit is free the block is still part of the free heap
+space. */
+static size_t xBlockAllocatedBit = 0;
+
+/*-----------------------------------------------------------*/
+
+void *pvPortMalloc( size_t xWantedSize )
+{
+BlockLink_t *pxBlock, *pxPreviousBlock, *pxNewBlockLink;
+void *pvReturn = NULL;
+
+	vTaskSuspendAll();
+	{
+		/* If this is the first call to malloc then the heap will require
+		initialisation to setup the list of free blocks. */
+		if( pxEnd == NULL )
+		{
+			prvHeapInit();
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+
+		/* Check the requested block size is not so large that the top bit is
+		set.  The top bit of the block size member of the BlockLink_t structure
+		is used to determine who owns the block - the application or the
+		kernel, so it must be free. */
+		if( ( xWantedSize & xBlockAllocatedBit ) == 0 )
+		{
+			/* The wanted size is increased so it can contain a BlockLink_t
+			structure in addition to the requested amount of bytes. */
+			if( xWantedSize > 0 )
+			{
+				xWantedSize += xHeapStructSize;
+
+				/* Ensure that blocks are always aligned to the required number
+				of bytes. */
+				if( ( xWantedSize & portBYTE_ALIGNMENT_MASK ) != 0x00 )
+				{
+					/* Byte alignment required. */
+					xWantedSize += ( portBYTE_ALIGNMENT - ( xWantedSize & portBYTE_ALIGNMENT_MASK ) );
+					configASSERT( ( xWantedSize & portBYTE_ALIGNMENT_MASK ) == 0 );
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+
+			if( ( xWantedSize > 0 ) && ( xWantedSize <= xFreeBytesRemaining ) )
+			{
+				/* Traverse the list from the start	(lowest address) block until
+				one	of adequate size is found. */
+				pxPreviousBlock = &xStart;
+				pxBlock = xStart.pxNextFreeBlock;
+				while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) )
+				{
+					pxPreviousBlock = pxBlock;
+					pxBlock = pxBlock->pxNextFreeBlock;
+				}
+
+				/* If the end marker was reached then a block of adequate size
+				was	not found. */
+				if( pxBlock != pxEnd )
+				{
+					/* Return the memory space pointed to - jumping over the
+					BlockLink_t structure at its start. */
+					pvReturn = ( void * ) ( ( ( uint8_t * ) pxPreviousBlock->pxNextFreeBlock ) + xHeapStructSize );
+
+					/* This block is being returned for use so must be taken out
+					of the list of free blocks. */
+					pxPreviousBlock->pxNextFreeBlock = pxBlock->pxNextFreeBlock;
+
+					/* If the block is larger than required it can be split into
+					two. */
+					if( ( pxBlock->xBlockSize - xWantedSize ) > heapMINIMUM_BLOCK_SIZE )
+					{
+						/* This block is to be split into two.  Create a new
+						block following the number of bytes requested. The void
+						cast is used to prevent byte alignment warnings from the
+						compiler. */
+						pxNewBlockLink = ( void * ) ( ( ( uint8_t * ) pxBlock ) + xWantedSize );
+						configASSERT( ( ( ( size_t ) pxNewBlockLink ) & portBYTE_ALIGNMENT_MASK ) == 0 );
+
+						/* Calculate the sizes of two blocks split from the
+						single block. */
+						pxNewBlockLink->xBlockSize = pxBlock->xBlockSize - xWantedSize;
+						pxBlock->xBlockSize = xWantedSize;
+
+						/* Insert the new block into the list of free blocks. */
+						prvInsertBlockIntoFreeList( pxNewBlockLink );
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+
+					xFreeBytesRemaining -= pxBlock->xBlockSize;
+
+					if( xFreeBytesRemaining < xMinimumEverFreeBytesRemaining )
+					{
+						xMinimumEverFreeBytesRemaining = xFreeBytesRemaining;
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+
+					/* The block is being returned - it is allocated and owned
+					by the application and has no "next" block. */
+					pxBlock->xBlockSize |= xBlockAllocatedBit;
+					pxBlock->pxNextFreeBlock = NULL;
+					xNumberOfSuccessfulAllocations++;
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+
+		traceMALLOC( pvReturn, xWantedSize );
+	}
+	( void ) xTaskResumeAll();
+
+	#if( configUSE_MALLOC_FAILED_HOOK == 1 )
+	{
+		if( pvReturn == NULL )
+		{
+			extern void vApplicationMallocFailedHook( void );
+			vApplicationMallocFailedHook();
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+	#endif
+
+	configASSERT( ( ( ( size_t ) pvReturn ) & ( size_t ) portBYTE_ALIGNMENT_MASK ) == 0 );
+	return pvReturn;
+}
+/*-----------------------------------------------------------*/
+
+void vPortFree( void *pv )
+{
+uint8_t *puc = ( uint8_t * ) pv;
+BlockLink_t *pxLink;
+
+	if( pv != NULL )
+	{
+		/* The memory being freed will have an BlockLink_t structure immediately
+		before it. */
+		puc -= xHeapStructSize;
+
+		/* This casting is to keep the compiler from issuing warnings. */
+		pxLink = ( void * ) puc;
+
+		/* Check the block is actually allocated. */
+		configASSERT( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 );
+		configASSERT( pxLink->pxNextFreeBlock == NULL );
+
+		if( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 )
+		{
+			if( pxLink->pxNextFreeBlock == NULL )
+			{
+				/* The block is being returned to the heap - it is no longer
+				allocated. */
+				pxLink->xBlockSize &= ~xBlockAllocatedBit;
+
+				vTaskSuspendAll();
+				{
+					/* Add this block to the list of free blocks. */
+					xFreeBytesRemaining += pxLink->xBlockSize;
+					traceFREE( pv, pxLink->xBlockSize );
+					prvInsertBlockIntoFreeList( ( ( BlockLink_t * ) pxLink ) );
+					xNumberOfSuccessfulFrees++;
+				}
+				( void ) xTaskResumeAll();
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+}
+/*-----------------------------------------------------------*/
+
+size_t xPortGetFreeHeapSize( void )
+{
+	return xFreeBytesRemaining;
+}
+/*-----------------------------------------------------------*/
+
+size_t xPortGetMinimumEverFreeHeapSize( void )
+{
+	return xMinimumEverFreeBytesRemaining;
+}
+/*-----------------------------------------------------------*/
+
+void vPortInitialiseBlocks( void )
+{
+	/* This just exists to keep the linker quiet. */
+}
+/*-----------------------------------------------------------*/
+
+static void prvHeapInit( void )
+{
+BlockLink_t *pxFirstFreeBlock;
+uint8_t *pucAlignedHeap;
+size_t uxAddress;
+size_t xTotalHeapSize = configTOTAL_HEAP_SIZE;
+
+	/* Ensure the heap starts on a correctly aligned boundary. */
+	uxAddress = ( size_t ) ucHeap;
+
+	if( ( uxAddress & portBYTE_ALIGNMENT_MASK ) != 0 )
+	{
+		uxAddress += ( portBYTE_ALIGNMENT - 1 );
+		uxAddress &= ~( ( size_t ) portBYTE_ALIGNMENT_MASK );
+		xTotalHeapSize -= uxAddress - ( size_t ) ucHeap;
+	}
+
+	pucAlignedHeap = ( uint8_t * ) uxAddress;
+
+	/* xStart is used to hold a pointer to the first item in the list of free
+	blocks.  The void cast is used to prevent compiler warnings. */
+	xStart.pxNextFreeBlock = ( void * ) pucAlignedHeap;
+	xStart.xBlockSize = ( size_t ) 0;
+
+	/* pxEnd is used to mark the end of the list of free blocks and is inserted
+	at the end of the heap space. */
+	uxAddress = ( ( size_t ) pucAlignedHeap ) + xTotalHeapSize;
+	uxAddress -= xHeapStructSize;
+	uxAddress &= ~( ( size_t ) portBYTE_ALIGNMENT_MASK );
+	pxEnd = ( void * ) uxAddress;
+	pxEnd->xBlockSize = 0;
+	pxEnd->pxNextFreeBlock = NULL;
+
+	/* To start with there is a single free block that is sized to take up the
+	entire heap space, minus the space taken by pxEnd. */
+	pxFirstFreeBlock = ( void * ) pucAlignedHeap;
+	pxFirstFreeBlock->xBlockSize = uxAddress - ( size_t ) pxFirstFreeBlock;
+	pxFirstFreeBlock->pxNextFreeBlock = pxEnd;
+
+	/* Only one block exists - and it covers the entire usable heap space. */
+	xMinimumEverFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;
+	xFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;
+
+	/* Work out the position of the top bit in a size_t variable. */
+	xBlockAllocatedBit = ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * heapBITS_PER_BYTE ) - 1 );
+}
+/*-----------------------------------------------------------*/
+
+static void prvInsertBlockIntoFreeList( BlockLink_t *pxBlockToInsert )
+{
+BlockLink_t *pxIterator;
+uint8_t *puc;
+
+	/* Iterate through the list until a block is found that has a higher address
+	than the block being inserted. */
+	for( pxIterator = &xStart; pxIterator->pxNextFreeBlock < pxBlockToInsert; pxIterator = pxIterator->pxNextFreeBlock )
+	{
+		/* Nothing to do here, just iterate to the right position. */
+	}
+
+	/* Do the block being inserted, and the block it is being inserted after
+	make a contiguous block of memory? */
+	puc = ( uint8_t * ) pxIterator;
+	if( ( puc + pxIterator->xBlockSize ) == ( uint8_t * ) pxBlockToInsert )
+	{
+		pxIterator->xBlockSize += pxBlockToInsert->xBlockSize;
+		pxBlockToInsert = pxIterator;
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	/* Do the block being inserted, and the block it is being inserted before
+	make a contiguous block of memory? */
+	puc = ( uint8_t * ) pxBlockToInsert;
+	if( ( puc + pxBlockToInsert->xBlockSize ) == ( uint8_t * ) pxIterator->pxNextFreeBlock )
+	{
+		if( pxIterator->pxNextFreeBlock != pxEnd )
+		{
+			/* Form one big block from the two blocks. */
+			pxBlockToInsert->xBlockSize += pxIterator->pxNextFreeBlock->xBlockSize;
+			pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock->pxNextFreeBlock;
+		}
+		else
+		{
+			pxBlockToInsert->pxNextFreeBlock = pxEnd;
+		}
+	}
+	else
+	{
+		pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock;
+	}
+
+	/* If the block being inserted plugged a gab, so was merged with the block
+	before and the block after, then it's pxNextFreeBlock pointer will have
+	already been set, and should not be set here as that would make it point
+	to itself. */
+	if( pxIterator != pxBlockToInsert )
+	{
+		pxIterator->pxNextFreeBlock = pxBlockToInsert;
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+}
+/*-----------------------------------------------------------*/
+
+void vPortGetHeapStats( HeapStats_t *pxHeapStats )
+{
+BlockLink_t *pxBlock;
+size_t xBlocks = 0, xMaxSize = 0, xMinSize = portMAX_DELAY; /* portMAX_DELAY used as a portable way of getting the maximum value. */
+
+	vTaskSuspendAll();
+	{
+		pxBlock = xStart.pxNextFreeBlock;
+
+		/* pxBlock will be NULL if the heap has not been initialised.  The heap
+		is initialised automatically when the first allocation is made. */
+		if( pxBlock != NULL )
+		{
+			do
+			{
+				/* Increment the number of blocks and record the largest block seen
+				so far. */
+				xBlocks++;
+
+				if( pxBlock->xBlockSize > xMaxSize )
+				{
+					xMaxSize = pxBlock->xBlockSize;
+				}
+
+				if( pxBlock->xBlockSize < xMinSize )
+				{
+					xMinSize = pxBlock->xBlockSize;
+				}
+
+				/* Move to the next block in the chain until the last block is
+				reached. */
+				pxBlock = pxBlock->pxNextFreeBlock;
+			} while( pxBlock != pxEnd );
+		}
+	}
+	xTaskResumeAll();
+
+	pxHeapStats->xSizeOfLargestFreeBlockInBytes = xMaxSize;
+	pxHeapStats->xSizeOfSmallestFreeBlockInBytes = xMinSize;
+	pxHeapStats->xNumberOfFreeBlocks = xBlocks;
+
+	taskENTER_CRITICAL();
+	{
+		pxHeapStats->xAvailableHeapSpaceInBytes = xFreeBytesRemaining;
+		pxHeapStats->xNumberOfSuccessfulAllocations = xNumberOfSuccessfulAllocations;
+		pxHeapStats->xNumberOfSuccessfulFrees = xNumberOfSuccessfulFrees;
+		pxHeapStats->xMinimumEverFreeBytesRemaining = xMinimumEverFreeBytesRemaining;
+	}
+	taskEXIT_CRITICAL();
+}
+
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/queue.c b/Middlewares/Third_Party/FreeRTOS/Source/queue.c
new file mode 100644
index 0000000..e35055f
--- /dev/null
+++ b/Middlewares/Third_Party/FreeRTOS/Source/queue.c
@@ -0,0 +1,2945 @@
+/*
+ * FreeRTOS Kernel V10.3.1
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#include <stdlib.h>
+#include <string.h>
+
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
+all the API functions to use the MPU wrappers.  That should only be done when
+task.h is included from an application file. */
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+#include "FreeRTOS.h"
+#include "task.h"
+#include "queue.h"
+
+#if ( configUSE_CO_ROUTINES == 1 )
+	#include "croutine.h"
+#endif
+
+/* Lint e9021, e961 and e750 are suppressed as a MISRA exception justified
+because the MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined
+for the header files above, but not in this file, in order to generate the
+correct privileged Vs unprivileged linkage and placement. */
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE /*lint !e961 !e750 !e9021. */
+
+
+/* Constants used with the cRxLock and cTxLock structure members. */
+#define queueUNLOCKED					( ( int8_t ) -1 )
+#define queueLOCKED_UNMODIFIED			( ( int8_t ) 0 )
+
+/* When the Queue_t structure is used to represent a base queue its pcHead and
+pcTail members are used as pointers into the queue storage area.  When the
+Queue_t structure is used to represent a mutex pcHead and pcTail pointers are
+not necessary, and the pcHead pointer is set to NULL to indicate that the
+structure instead holds a pointer to the mutex holder (if any).  Map alternative
+names to the pcHead and structure member to ensure the readability of the code
+is maintained.  The QueuePointers_t and SemaphoreData_t types are used to form
+a union as their usage is mutually exclusive dependent on what the queue is
+being used for. */
+#define uxQueueType						pcHead
+#define queueQUEUE_IS_MUTEX				NULL
+
+typedef struct QueuePointers
+{
+	int8_t *pcTail;					/*< Points to the byte at the end of the queue storage area.  Once more byte is allocated than necessary to store the queue items, this is used as a marker. */
+	int8_t *pcReadFrom;				/*< Points to the last place that a queued item was read from when the structure is used as a queue. */
+} QueuePointers_t;
+
+typedef struct SemaphoreData
+{
+	TaskHandle_t xMutexHolder;		 /*< The handle of the task that holds the mutex. */
+	UBaseType_t uxRecursiveCallCount;/*< Maintains a count of the number of times a recursive mutex has been recursively 'taken' when the structure is used as a mutex. */
+} SemaphoreData_t;
+
+/* Semaphores do not actually store or copy data, so have an item size of
+zero. */
+#define queueSEMAPHORE_QUEUE_ITEM_LENGTH ( ( UBaseType_t ) 0 )
+#define queueMUTEX_GIVE_BLOCK_TIME		 ( ( TickType_t ) 0U )
+
+#if( configUSE_PREEMPTION == 0 )
+	/* If the cooperative scheduler is being used then a yield should not be
+	performed just because a higher priority task has been woken. */
+	#define queueYIELD_IF_USING_PREEMPTION()
+#else
+	#define queueYIELD_IF_USING_PREEMPTION() portYIELD_WITHIN_API()
+#endif
+
+/*
+ * Definition of the queue used by the scheduler.
+ * Items are queued by copy, not reference.  See the following link for the
+ * rationale: https://www.freertos.org/Embedded-RTOS-Queues.html
+ */
+typedef struct QueueDefinition 		/* The old naming convention is used to prevent breaking kernel aware debuggers. */
+{
+	int8_t *pcHead;					/*< Points to the beginning of the queue storage area. */
+	int8_t *pcWriteTo;				/*< Points to the free next place in the storage area. */
+
+	union
+	{
+		QueuePointers_t xQueue;		/*< Data required exclusively when this structure is used as a queue. */
+		SemaphoreData_t xSemaphore; /*< Data required exclusively when this structure is used as a semaphore. */
+	} u;
+
+	List_t xTasksWaitingToSend;		/*< List of tasks that are blocked waiting to post onto this queue.  Stored in priority order. */
+	List_t xTasksWaitingToReceive;	/*< List of tasks that are blocked waiting to read from this queue.  Stored in priority order. */
+
+	volatile UBaseType_t uxMessagesWaiting;/*< The number of items currently in the queue. */
+	UBaseType_t uxLength;			/*< The length of the queue defined as the number of items it will hold, not the number of bytes. */
+	UBaseType_t uxItemSize;			/*< The size of each items that the queue will hold. */
+
+	volatile int8_t cRxLock;		/*< Stores the number of items received from the queue (removed from the queue) while the queue was locked.  Set to queueUNLOCKED when the queue is not locked. */
+	volatile int8_t cTxLock;		/*< Stores the number of items transmitted to the queue (added to the queue) while the queue was locked.  Set to queueUNLOCKED when the queue is not locked. */
+
+	#if( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
+		uint8_t ucStaticallyAllocated;	/*< Set to pdTRUE if the memory used by the queue was statically allocated to ensure no attempt is made to free the memory. */
+	#endif
+
+	#if ( configUSE_QUEUE_SETS == 1 )
+		struct QueueDefinition *pxQueueSetContainer;
+	#endif
+
+	#if ( configUSE_TRACE_FACILITY == 1 )
+		UBaseType_t uxQueueNumber;
+		uint8_t ucQueueType;
+	#endif
+
+} xQUEUE;
+
+/* The old xQUEUE name is maintained above then typedefed to the new Queue_t
+name below to enable the use of older kernel aware debuggers. */
+typedef xQUEUE Queue_t;
+
+/*-----------------------------------------------------------*/
+
+/*
+ * The queue registry is just a means for kernel aware debuggers to locate
+ * queue structures.  It has no other purpose so is an optional component.
+ */
+#if ( configQUEUE_REGISTRY_SIZE > 0 )
+
+	/* The type stored within the queue registry array.  This allows a name
+	to be assigned to each queue making kernel aware debugging a little
+	more user friendly. */
+	typedef struct QUEUE_REGISTRY_ITEM
+	{
+		const char *pcQueueName; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+		QueueHandle_t xHandle;
+	} xQueueRegistryItem;
+
+	/* The old xQueueRegistryItem name is maintained above then typedefed to the
+	new xQueueRegistryItem name below to enable the use of older kernel aware
+	debuggers. */
+	typedef xQueueRegistryItem QueueRegistryItem_t;
+
+	/* The queue registry is simply an array of QueueRegistryItem_t structures.
+	The pcQueueName member of a structure being NULL is indicative of the
+	array position being vacant. */
+	PRIVILEGED_DATA QueueRegistryItem_t xQueueRegistry[ configQUEUE_REGISTRY_SIZE ];
+
+#endif /* configQUEUE_REGISTRY_SIZE */
+
+/*
+ * Unlocks a queue locked by a call to prvLockQueue.  Locking a queue does not
+ * prevent an ISR from adding or removing items to the queue, but does prevent
+ * an ISR from removing tasks from the queue event lists.  If an ISR finds a
+ * queue is locked it will instead increment the appropriate queue lock count
+ * to indicate that a task may require unblocking.  When the queue in unlocked
+ * these lock counts are inspected, and the appropriate action taken.
+ */
+static void prvUnlockQueue( Queue_t * const pxQueue ) PRIVILEGED_FUNCTION;
+
+/*
+ * Uses a critical section to determine if there is any data in a queue.
+ *
+ * @return pdTRUE if the queue contains no items, otherwise pdFALSE.
+ */
+static BaseType_t prvIsQueueEmpty( const Queue_t *pxQueue ) PRIVILEGED_FUNCTION;
+
+/*
+ * Uses a critical section to determine if there is any space in a queue.
+ *
+ * @return pdTRUE if there is no space, otherwise pdFALSE;
+ */
+static BaseType_t prvIsQueueFull( const Queue_t *pxQueue ) PRIVILEGED_FUNCTION;
+
+/*
+ * Copies an item into the queue, either at the front of the queue or the
+ * back of the queue.
+ */
+static BaseType_t prvCopyDataToQueue( Queue_t * const pxQueue, const void *pvItemToQueue, const BaseType_t xPosition ) PRIVILEGED_FUNCTION;
+
+/*
+ * Copies an item out of a queue.
+ */
+static void prvCopyDataFromQueue( Queue_t * const pxQueue, void * const pvBuffer ) PRIVILEGED_FUNCTION;
+
+#if ( configUSE_QUEUE_SETS == 1 )
+	/*
+	 * Checks to see if a queue is a member of a queue set, and if so, notifies
+	 * the queue set that the queue contains data.
+	 */
+	static BaseType_t prvNotifyQueueSetContainer( const Queue_t * const pxQueue ) PRIVILEGED_FUNCTION;
+#endif
+
+/*
+ * Called after a Queue_t structure has been allocated either statically or
+ * dynamically to fill in the structure's members.
+ */
+static void prvInitialiseNewQueue( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, uint8_t *pucQueueStorage, const uint8_t ucQueueType, Queue_t *pxNewQueue ) PRIVILEGED_FUNCTION;
+
+/*
+ * Mutexes are a special type of queue.  When a mutex is created, first the
+ * queue is created, then prvInitialiseMutex() is called to configure the queue
+ * as a mutex.
+ */
+#if( configUSE_MUTEXES == 1 )
+	static void prvInitialiseMutex( Queue_t *pxNewQueue ) PRIVILEGED_FUNCTION;
+#endif
+
+#if( configUSE_MUTEXES == 1 )
+	/*
+	 * If a task waiting for a mutex causes the mutex holder to inherit a
+	 * priority, but the waiting task times out, then the holder should
+	 * disinherit the priority - but only down to the highest priority of any
+	 * other tasks that are waiting for the same mutex.  This function returns
+	 * that priority.
+	 */
+	static UBaseType_t prvGetDisinheritPriorityAfterTimeout( const Queue_t * const pxQueue ) PRIVILEGED_FUNCTION;
+#endif
+/*-----------------------------------------------------------*/
+
+/*
+ * Macro to mark a queue as locked.  Locking a queue prevents an ISR from
+ * accessing the queue event lists.
+ */
+#define prvLockQueue( pxQueue )								\
+	taskENTER_CRITICAL();									\
+	{														\
+		if( ( pxQueue )->cRxLock == queueUNLOCKED )			\
+		{													\
+			( pxQueue )->cRxLock = queueLOCKED_UNMODIFIED;	\
+		}													\
+		if( ( pxQueue )->cTxLock == queueUNLOCKED )			\
+		{													\
+			( pxQueue )->cTxLock = queueLOCKED_UNMODIFIED;	\
+		}													\
+	}														\
+	taskEXIT_CRITICAL()
+/*-----------------------------------------------------------*/
+
+BaseType_t xQueueGenericReset( QueueHandle_t xQueue, BaseType_t xNewQueue )
+{
+Queue_t * const pxQueue = xQueue;
+
+	configASSERT( pxQueue );
+
+	taskENTER_CRITICAL();
+	{
+		pxQueue->u.xQueue.pcTail = pxQueue->pcHead + ( pxQueue->uxLength * pxQueue->uxItemSize ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */
+		pxQueue->uxMessagesWaiting = ( UBaseType_t ) 0U;
+		pxQueue->pcWriteTo = pxQueue->pcHead;
+		pxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead + ( ( pxQueue->uxLength - 1U ) * pxQueue->uxItemSize ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */
+		pxQueue->cRxLock = queueUNLOCKED;
+		pxQueue->cTxLock = queueUNLOCKED;
+
+		if( xNewQueue == pdFALSE )
+		{
+			/* If there are tasks blocked waiting to read from the queue, then
+			the tasks will remain blocked as after this function exits the queue
+			will still be empty.  If there are tasks blocked waiting to write to
+			the queue, then one should be unblocked as after this function exits
+			it will be possible to write to it. */
+			if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
+			{
+				if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
+				{
+					queueYIELD_IF_USING_PREEMPTION();
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		else
+		{
+			/* Ensure the event queues start in the correct state. */
+			vListInitialise( &( pxQueue->xTasksWaitingToSend ) );
+			vListInitialise( &( pxQueue->xTasksWaitingToReceive ) );
+		}
+	}
+	taskEXIT_CRITICAL();
+
+	/* A value is returned for calling semantic consistency with previous
+	versions. */
+	return pdPASS;
+}
+/*-----------------------------------------------------------*/
+
+#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+
+	QueueHandle_t xQueueGenericCreateStatic( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, uint8_t *pucQueueStorage, StaticQueue_t *pxStaticQueue, const uint8_t ucQueueType )
+	{
+	Queue_t *pxNewQueue;
+
+		configASSERT( uxQueueLength > ( UBaseType_t ) 0 );
+
+		/* The StaticQueue_t structure and the queue storage area must be
+		supplied. */
+		configASSERT( pxStaticQueue != NULL );
+
+		/* A queue storage area should be provided if the item size is not 0, and
+		should not be provided if the item size is 0. */
+		configASSERT( !( ( pucQueueStorage != NULL ) && ( uxItemSize == 0 ) ) );
+		configASSERT( !( ( pucQueueStorage == NULL ) && ( uxItemSize != 0 ) ) );
+
+		#if( configASSERT_DEFINED == 1 )
+		{
+			/* Sanity check that the size of the structure used to declare a
+			variable of type StaticQueue_t or StaticSemaphore_t equals the size of
+			the real queue and semaphore structures. */
+			volatile size_t xSize = sizeof( StaticQueue_t );
+			configASSERT( xSize == sizeof( Queue_t ) );
+			( void ) xSize; /* Keeps lint quiet when configASSERT() is not defined. */
+		}
+		#endif /* configASSERT_DEFINED */
+
+		/* The address of a statically allocated queue was passed in, use it.
+		The address of a statically allocated storage area was also passed in
+		but is already set. */
+		pxNewQueue = ( Queue_t * ) pxStaticQueue; /*lint !e740 !e9087 Unusual cast is ok as the structures are designed to have the same alignment, and the size is checked by an assert. */
+
+		if( pxNewQueue != NULL )
+		{
+			#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+			{
+				/* Queues can be allocated wither statically or dynamically, so
+				note this queue was allocated statically in case the queue is
+				later deleted. */
+				pxNewQueue->ucStaticallyAllocated = pdTRUE;
+			}
+			#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
+
+			prvInitialiseNewQueue( uxQueueLength, uxItemSize, pucQueueStorage, ucQueueType, pxNewQueue );
+		}
+		else
+		{
+			traceQUEUE_CREATE_FAILED( ucQueueType );
+			mtCOVERAGE_TEST_MARKER();
+		}
+
+		return pxNewQueue;
+	}
+
+#endif /* configSUPPORT_STATIC_ALLOCATION */
+/*-----------------------------------------------------------*/
+
+#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+
+	QueueHandle_t xQueueGenericCreate( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, const uint8_t ucQueueType )
+	{
+	Queue_t *pxNewQueue;
+	size_t xQueueSizeInBytes;
+	uint8_t *pucQueueStorage;
+
+		configASSERT( uxQueueLength > ( UBaseType_t ) 0 );
+
+		/* Allocate enough space to hold the maximum number of items that
+		can be in the queue at any time.  It is valid for uxItemSize to be
+		zero in the case the queue is used as a semaphore. */
+		xQueueSizeInBytes = ( size_t ) ( uxQueueLength * uxItemSize ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
+
+		/* Allocate the queue and storage area.  Justification for MISRA
+		deviation as follows:  pvPortMalloc() always ensures returned memory
+		blocks are aligned per the requirements of the MCU stack.  In this case
+		pvPortMalloc() must return a pointer that is guaranteed to meet the
+		alignment requirements of the Queue_t structure - which in this case
+		is an int8_t *.  Therefore, whenever the stack alignment requirements
+		are greater than or equal to the pointer to char requirements the cast
+		is safe.  In other cases alignment requirements are not strict (one or
+		two bytes). */
+		pxNewQueue = ( Queue_t * ) pvPortMalloc( sizeof( Queue_t ) + xQueueSizeInBytes ); /*lint !e9087 !e9079 see comment above. */
+
+		if( pxNewQueue != NULL )
+		{
+			/* Jump past the queue structure to find the location of the queue
+			storage area. */
+			pucQueueStorage = ( uint8_t * ) pxNewQueue;
+			pucQueueStorage += sizeof( Queue_t ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */
+
+			#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+			{
+				/* Queues can be created either statically or dynamically, so
+				note this task was created dynamically in case it is later
+				deleted. */
+				pxNewQueue->ucStaticallyAllocated = pdFALSE;
+			}
+			#endif /* configSUPPORT_STATIC_ALLOCATION */
+
+			prvInitialiseNewQueue( uxQueueLength, uxItemSize, pucQueueStorage, ucQueueType, pxNewQueue );
+		}
+		else
+		{
+			traceQUEUE_CREATE_FAILED( ucQueueType );
+			mtCOVERAGE_TEST_MARKER();
+		}
+
+		return pxNewQueue;
+	}
+
+#endif /* configSUPPORT_STATIC_ALLOCATION */
+/*-----------------------------------------------------------*/
+
+static void prvInitialiseNewQueue( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, uint8_t *pucQueueStorage, const uint8_t ucQueueType, Queue_t *pxNewQueue )
+{
+	/* Remove compiler warnings about unused parameters should
+	configUSE_TRACE_FACILITY not be set to 1. */
+	( void ) ucQueueType;
+
+	if( uxItemSize == ( UBaseType_t ) 0 )
+	{
+		/* No RAM was allocated for the queue storage area, but PC head cannot
+		be set to NULL because NULL is used as a key to say the queue is used as
+		a mutex.  Therefore just set pcHead to point to the queue as a benign
+		value that is known to be within the memory map. */
+		pxNewQueue->pcHead = ( int8_t * ) pxNewQueue;
+	}
+	else
+	{
+		/* Set the head to the start of the queue storage area. */
+		pxNewQueue->pcHead = ( int8_t * ) pucQueueStorage;
+	}
+
+	/* Initialise the queue members as described where the queue type is
+	defined. */
+	pxNewQueue->uxLength = uxQueueLength;
+	pxNewQueue->uxItemSize = uxItemSize;
+	( void ) xQueueGenericReset( pxNewQueue, pdTRUE );
+
+	#if ( configUSE_TRACE_FACILITY == 1 )
+	{
+		pxNewQueue->ucQueueType = ucQueueType;
+	}
+	#endif /* configUSE_TRACE_FACILITY */
+
+	#if( configUSE_QUEUE_SETS == 1 )
+	{
+		pxNewQueue->pxQueueSetContainer = NULL;
+	}
+	#endif /* configUSE_QUEUE_SETS */
+
+	traceQUEUE_CREATE( pxNewQueue );
+}
+/*-----------------------------------------------------------*/
+
+#if( configUSE_MUTEXES == 1 )
+
+	static void prvInitialiseMutex( Queue_t *pxNewQueue )
+	{
+		if( pxNewQueue != NULL )
+		{
+			/* The queue create function will set all the queue structure members
+			correctly for a generic queue, but this function is creating a
+			mutex.  Overwrite those members that need to be set differently -
+			in particular the information required for priority inheritance. */
+			pxNewQueue->u.xSemaphore.xMutexHolder = NULL;
+			pxNewQueue->uxQueueType = queueQUEUE_IS_MUTEX;
+
+			/* In case this is a recursive mutex. */
+			pxNewQueue->u.xSemaphore.uxRecursiveCallCount = 0;
+
+			traceCREATE_MUTEX( pxNewQueue );
+
+			/* Start with the semaphore in the expected state. */
+			( void ) xQueueGenericSend( pxNewQueue, NULL, ( TickType_t ) 0U, queueSEND_TO_BACK );
+		}
+		else
+		{
+			traceCREATE_MUTEX_FAILED();
+		}
+	}
+
+#endif /* configUSE_MUTEXES */
+/*-----------------------------------------------------------*/
+
+#if( ( configUSE_MUTEXES == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
+
+	QueueHandle_t xQueueCreateMutex( const uint8_t ucQueueType )
+	{
+	QueueHandle_t xNewQueue;
+	const UBaseType_t uxMutexLength = ( UBaseType_t ) 1, uxMutexSize = ( UBaseType_t ) 0;
+
+		xNewQueue = xQueueGenericCreate( uxMutexLength, uxMutexSize, ucQueueType );
+		prvInitialiseMutex( ( Queue_t * ) xNewQueue );
+
+		return xNewQueue;
+	}
+
+#endif /* configUSE_MUTEXES */
+/*-----------------------------------------------------------*/
+
+#if( ( configUSE_MUTEXES == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) )
+
+	QueueHandle_t xQueueCreateMutexStatic( const uint8_t ucQueueType, StaticQueue_t *pxStaticQueue )
+	{
+	QueueHandle_t xNewQueue;
+	const UBaseType_t uxMutexLength = ( UBaseType_t ) 1, uxMutexSize = ( UBaseType_t ) 0;
+
+		/* Prevent compiler warnings about unused parameters if
+		configUSE_TRACE_FACILITY does not equal 1. */
+		( void ) ucQueueType;
+
+		xNewQueue = xQueueGenericCreateStatic( uxMutexLength, uxMutexSize, NULL, pxStaticQueue, ucQueueType );
+		prvInitialiseMutex( ( Queue_t * ) xNewQueue );
+
+		return xNewQueue;
+	}
+
+#endif /* configUSE_MUTEXES */
+/*-----------------------------------------------------------*/
+
+#if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) )
+
+	TaskHandle_t xQueueGetMutexHolder( QueueHandle_t xSemaphore )
+	{
+	TaskHandle_t pxReturn;
+	Queue_t * const pxSemaphore = ( Queue_t * ) xSemaphore;
+
+		/* This function is called by xSemaphoreGetMutexHolder(), and should not
+		be called directly.  Note:  This is a good way of determining if the
+		calling task is the mutex holder, but not a good way of determining the
+		identity of the mutex holder, as the holder may change between the
+		following critical section exiting and the function returning. */
+		taskENTER_CRITICAL();
+		{
+			if( pxSemaphore->uxQueueType == queueQUEUE_IS_MUTEX )
+			{
+				pxReturn = pxSemaphore->u.xSemaphore.xMutexHolder;
+			}
+			else
+			{
+				pxReturn = NULL;
+			}
+		}
+		taskEXIT_CRITICAL();
+
+		return pxReturn;
+	} /*lint !e818 xSemaphore cannot be a pointer to const because it is a typedef. */
+
+#endif
+/*-----------------------------------------------------------*/
+
+#if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) )
+
+	TaskHandle_t xQueueGetMutexHolderFromISR( QueueHandle_t xSemaphore )
+	{
+	TaskHandle_t pxReturn;
+
+		configASSERT( xSemaphore );
+
+		/* Mutexes cannot be used in interrupt service routines, so the mutex
+		holder should not change in an ISR, and therefore a critical section is
+		not required here. */
+		if( ( ( Queue_t * ) xSemaphore )->uxQueueType == queueQUEUE_IS_MUTEX )
+		{
+			pxReturn = ( ( Queue_t * ) xSemaphore )->u.xSemaphore.xMutexHolder;
+		}
+		else
+		{
+			pxReturn = NULL;
+		}
+
+		return pxReturn;
+	} /*lint !e818 xSemaphore cannot be a pointer to const because it is a typedef. */
+
+#endif
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_RECURSIVE_MUTEXES == 1 )
+
+	BaseType_t xQueueGiveMutexRecursive( QueueHandle_t xMutex )
+	{
+	BaseType_t xReturn;
+	Queue_t * const pxMutex = ( Queue_t * ) xMutex;
+
+		configASSERT( pxMutex );
+
+		/* If this is the task that holds the mutex then xMutexHolder will not
+		change outside of this task.  If this task does not hold the mutex then
+		pxMutexHolder can never coincidentally equal the tasks handle, and as
+		this is the only condition we are interested in it does not matter if
+		pxMutexHolder is accessed simultaneously by another task.  Therefore no
+		mutual exclusion is required to test the pxMutexHolder variable. */
+		if( pxMutex->u.xSemaphore.xMutexHolder == xTaskGetCurrentTaskHandle() )
+		{
+			traceGIVE_MUTEX_RECURSIVE( pxMutex );
+
+			/* uxRecursiveCallCount cannot be zero if xMutexHolder is equal to
+			the task handle, therefore no underflow check is required.  Also,
+			uxRecursiveCallCount is only modified by the mutex holder, and as
+			there can only be one, no mutual exclusion is required to modify the
+			uxRecursiveCallCount member. */
+			( pxMutex->u.xSemaphore.uxRecursiveCallCount )--;
+
+			/* Has the recursive call count unwound to 0? */
+			if( pxMutex->u.xSemaphore.uxRecursiveCallCount == ( UBaseType_t ) 0 )
+			{
+				/* Return the mutex.  This will automatically unblock any other
+				task that might be waiting to access the mutex. */
+				( void ) xQueueGenericSend( pxMutex, NULL, queueMUTEX_GIVE_BLOCK_TIME, queueSEND_TO_BACK );
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+
+			xReturn = pdPASS;
+		}
+		else
+		{
+			/* The mutex cannot be given because the calling task is not the
+			holder. */
+			xReturn = pdFAIL;
+
+			traceGIVE_MUTEX_RECURSIVE_FAILED( pxMutex );
+		}
+
+		return xReturn;
+	}
+
+#endif /* configUSE_RECURSIVE_MUTEXES */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_RECURSIVE_MUTEXES == 1 )
+
+	BaseType_t xQueueTakeMutexRecursive( QueueHandle_t xMutex, TickType_t xTicksToWait )
+	{
+	BaseType_t xReturn;
+	Queue_t * const pxMutex = ( Queue_t * ) xMutex;
+
+		configASSERT( pxMutex );
+
+		/* Comments regarding mutual exclusion as per those within
+		xQueueGiveMutexRecursive(). */
+
+		traceTAKE_MUTEX_RECURSIVE( pxMutex );
+
+		if( pxMutex->u.xSemaphore.xMutexHolder == xTaskGetCurrentTaskHandle() )
+		{
+			( pxMutex->u.xSemaphore.uxRecursiveCallCount )++;
+			xReturn = pdPASS;
+		}
+		else
+		{
+			xReturn = xQueueSemaphoreTake( pxMutex, xTicksToWait );
+
+			/* pdPASS will only be returned if the mutex was successfully
+			obtained.  The calling task may have entered the Blocked state
+			before reaching here. */
+			if( xReturn != pdFAIL )
+			{
+				( pxMutex->u.xSemaphore.uxRecursiveCallCount )++;
+			}
+			else
+			{
+				traceTAKE_MUTEX_RECURSIVE_FAILED( pxMutex );
+			}
+		}
+
+		return xReturn;
+	}
+
+#endif /* configUSE_RECURSIVE_MUTEXES */
+/*-----------------------------------------------------------*/
+
+#if( ( configUSE_COUNTING_SEMAPHORES == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) )
+
+	QueueHandle_t xQueueCreateCountingSemaphoreStatic( const UBaseType_t uxMaxCount, const UBaseType_t uxInitialCount, StaticQueue_t *pxStaticQueue )
+	{
+	QueueHandle_t xHandle;
+
+		configASSERT( uxMaxCount != 0 );
+		configASSERT( uxInitialCount <= uxMaxCount );
+
+		xHandle = xQueueGenericCreateStatic( uxMaxCount, queueSEMAPHORE_QUEUE_ITEM_LENGTH, NULL, pxStaticQueue, queueQUEUE_TYPE_COUNTING_SEMAPHORE );
+
+		if( xHandle != NULL )
+		{
+			( ( Queue_t * ) xHandle )->uxMessagesWaiting = uxInitialCount;
+
+			traceCREATE_COUNTING_SEMAPHORE();
+		}
+		else
+		{
+			traceCREATE_COUNTING_SEMAPHORE_FAILED();
+		}
+
+		return xHandle;
+	}
+
+#endif /* ( ( configUSE_COUNTING_SEMAPHORES == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+#if( ( configUSE_COUNTING_SEMAPHORES == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
+
+	QueueHandle_t xQueueCreateCountingSemaphore( const UBaseType_t uxMaxCount, const UBaseType_t uxInitialCount )
+	{
+	QueueHandle_t xHandle;
+
+		configASSERT( uxMaxCount != 0 );
+		configASSERT( uxInitialCount <= uxMaxCount );
+
+		xHandle = xQueueGenericCreate( uxMaxCount, queueSEMAPHORE_QUEUE_ITEM_LENGTH, queueQUEUE_TYPE_COUNTING_SEMAPHORE );
+
+		if( xHandle != NULL )
+		{
+			( ( Queue_t * ) xHandle )->uxMessagesWaiting = uxInitialCount;
+
+			traceCREATE_COUNTING_SEMAPHORE();
+		}
+		else
+		{
+			traceCREATE_COUNTING_SEMAPHORE_FAILED();
+		}
+
+		return xHandle;
+	}
+
+#endif /* ( ( configUSE_COUNTING_SEMAPHORES == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+BaseType_t xQueueGenericSend( QueueHandle_t xQueue, const void * const pvItemToQueue, TickType_t xTicksToWait, const BaseType_t xCopyPosition )
+{
+BaseType_t xEntryTimeSet = pdFALSE, xYieldRequired;
+TimeOut_t xTimeOut;
+Queue_t * const pxQueue = xQueue;
+
+	configASSERT( pxQueue );
+	configASSERT( !( ( pvItemToQueue == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) );
+	configASSERT( !( ( xCopyPosition == queueOVERWRITE ) && ( pxQueue->uxLength != 1 ) ) );
+	#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
+	{
+		configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) );
+	}
+	#endif
+
+
+	/*lint -save -e904 This function relaxes the coding standard somewhat to
+	allow return statements within the function itself.  This is done in the
+	interest of execution time efficiency. */
+	for( ;; )
+	{
+		taskENTER_CRITICAL();
+		{
+			/* Is there room on the queue now?  The running task must be the
+			highest priority task wanting to access the queue.  If the head item
+			in the queue is to be overwritten then it does not matter if the
+			queue is full. */
+			if( ( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) || ( xCopyPosition == queueOVERWRITE ) )
+			{
+				traceQUEUE_SEND( pxQueue );
+
+				#if ( configUSE_QUEUE_SETS == 1 )
+				{
+				const UBaseType_t uxPreviousMessagesWaiting = pxQueue->uxMessagesWaiting;
+
+					xYieldRequired = prvCopyDataToQueue( pxQueue, pvItemToQueue, xCopyPosition );
+
+					if( pxQueue->pxQueueSetContainer != NULL )
+					{
+						if( ( xCopyPosition == queueOVERWRITE ) && ( uxPreviousMessagesWaiting != ( UBaseType_t ) 0 ) )
+						{
+							/* Do not notify the queue set as an existing item
+							was overwritten in the queue so the number of items
+							in the queue has not changed. */
+							mtCOVERAGE_TEST_MARKER();
+						}
+						else if( prvNotifyQueueSetContainer( pxQueue ) != pdFALSE )
+						{
+							/* The queue is a member of a queue set, and posting
+							to the queue set caused a higher priority task to
+							unblock. A context switch is required. */
+							queueYIELD_IF_USING_PREEMPTION();
+						}
+						else
+						{
+							mtCOVERAGE_TEST_MARKER();
+						}
+					}
+					else
+					{
+						/* If there was a task waiting for data to arrive on the
+						queue then unblock it now. */
+						if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
+						{
+							if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
+							{
+								/* The unblocked task has a priority higher than
+								our own so yield immediately.  Yes it is ok to
+								do this from within the critical section - the
+								kernel takes care of that. */
+								queueYIELD_IF_USING_PREEMPTION();
+							}
+							else
+							{
+								mtCOVERAGE_TEST_MARKER();
+							}
+						}
+						else if( xYieldRequired != pdFALSE )
+						{
+							/* This path is a special case that will only get
+							executed if the task was holding multiple mutexes
+							and the mutexes were given back in an order that is
+							different to that in which they were taken. */
+							queueYIELD_IF_USING_PREEMPTION();
+						}
+						else
+						{
+							mtCOVERAGE_TEST_MARKER();
+						}
+					}
+				}
+				#else /* configUSE_QUEUE_SETS */
+				{
+					xYieldRequired = prvCopyDataToQueue( pxQueue, pvItemToQueue, xCopyPosition );
+
+					/* If there was a task waiting for data to arrive on the
+					queue then unblock it now. */
+					if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
+					{
+						if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
+						{
+							/* The unblocked task has a priority higher than
+							our own so yield immediately.  Yes it is ok to do
+							this from within the critical section - the kernel
+							takes care of that. */
+							queueYIELD_IF_USING_PREEMPTION();
+						}
+						else
+						{
+							mtCOVERAGE_TEST_MARKER();
+						}
+					}
+					else if( xYieldRequired != pdFALSE )
+					{
+						/* This path is a special case that will only get
+						executed if the task was holding multiple mutexes and
+						the mutexes were given back in an order that is
+						different to that in which they were taken. */
+						queueYIELD_IF_USING_PREEMPTION();
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				#endif /* configUSE_QUEUE_SETS */
+
+				taskEXIT_CRITICAL();
+				return pdPASS;
+			}
+			else
+			{
+				if( xTicksToWait == ( TickType_t ) 0 )
+				{
+					/* The queue was full and no block time is specified (or
+					the block time has expired) so leave now. */
+					taskEXIT_CRITICAL();
+
+					/* Return to the original privilege level before exiting
+					the function. */
+					traceQUEUE_SEND_FAILED( pxQueue );
+					return errQUEUE_FULL;
+				}
+				else if( xEntryTimeSet == pdFALSE )
+				{
+					/* The queue was full and a block time was specified so
+					configure the timeout structure. */
+					vTaskInternalSetTimeOutState( &xTimeOut );
+					xEntryTimeSet = pdTRUE;
+				}
+				else
+				{
+					/* Entry time was already set. */
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+		}
+		taskEXIT_CRITICAL();
+
+		/* Interrupts and other tasks can send to and receive from the queue
+		now the critical section has been exited. */
+
+		vTaskSuspendAll();
+		prvLockQueue( pxQueue );
+
+		/* Update the timeout state to see if it has expired yet. */
+		if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE )
+		{
+			if( prvIsQueueFull( pxQueue ) != pdFALSE )
+			{
+				traceBLOCKING_ON_QUEUE_SEND( pxQueue );
+				vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToSend ), xTicksToWait );
+
+				/* Unlocking the queue means queue events can effect the
+				event list.  It is possible that interrupts occurring now
+				remove this task from the event list again - but as the
+				scheduler is suspended the task will go onto the pending
+				ready last instead of the actual ready list. */
+				prvUnlockQueue( pxQueue );
+
+				/* Resuming the scheduler will move tasks from the pending
+				ready list into the ready list - so it is feasible that this
+				task is already in a ready list before it yields - in which
+				case the yield will not cause a context switch unless there
+				is also a higher priority task in the pending ready list. */
+				if( xTaskResumeAll() == pdFALSE )
+				{
+					portYIELD_WITHIN_API();
+				}
+			}
+			else
+			{
+				/* Try again. */
+				prvUnlockQueue( pxQueue );
+				( void ) xTaskResumeAll();
+			}
+		}
+		else
+		{
+			/* The timeout has expired. */
+			prvUnlockQueue( pxQueue );
+			( void ) xTaskResumeAll();
+
+			traceQUEUE_SEND_FAILED( pxQueue );
+			return errQUEUE_FULL;
+		}
+	} /*lint -restore */
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xQueueGenericSendFromISR( QueueHandle_t xQueue, const void * const pvItemToQueue, BaseType_t * const pxHigherPriorityTaskWoken, const BaseType_t xCopyPosition )
+{
+BaseType_t xReturn;
+UBaseType_t uxSavedInterruptStatus;
+Queue_t * const pxQueue = xQueue;
+
+	configASSERT( pxQueue );
+	configASSERT( !( ( pvItemToQueue == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) );
+	configASSERT( !( ( xCopyPosition == queueOVERWRITE ) && ( pxQueue->uxLength != 1 ) ) );
+
+	/* RTOS ports that support interrupt nesting have the concept of a maximum
+	system call (or maximum API call) interrupt priority.  Interrupts that are
+	above the maximum system call priority are kept permanently enabled, even
+	when the RTOS kernel is in a critical section, but cannot make any calls to
+	FreeRTOS API functions.  If configASSERT() is defined in FreeRTOSConfig.h
+	then portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion
+	failure if a FreeRTOS API function is called from an interrupt that has been
+	assigned a priority above the configured maximum system call priority.
+	Only FreeRTOS functions that end in FromISR can be called from interrupts
+	that have been assigned a priority at or (logically) below the maximum
+	system call	interrupt priority.  FreeRTOS maintains a separate interrupt
+	safe API to ensure interrupt entry is as fast and as simple as possible.
+	More information (albeit Cortex-M specific) is provided on the following
+	link: http://www.freertos.org/RTOS-Cortex-M3-M4.html */
+	portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
+
+	/* Similar to xQueueGenericSend, except without blocking if there is no room
+	in the queue.  Also don't directly wake a task that was blocked on a queue
+	read, instead return a flag to say whether a context switch is required or
+	not (i.e. has a task with a higher priority than us been woken by this
+	post). */
+	uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
+	{
+		if( ( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) || ( xCopyPosition == queueOVERWRITE ) )
+		{
+			const int8_t cTxLock = pxQueue->cTxLock;
+			const UBaseType_t uxPreviousMessagesWaiting = pxQueue->uxMessagesWaiting;
+
+			traceQUEUE_SEND_FROM_ISR( pxQueue );
+
+			/* Semaphores use xQueueGiveFromISR(), so pxQueue will not be a
+			semaphore or mutex.  That means prvCopyDataToQueue() cannot result
+			in a task disinheriting a priority and prvCopyDataToQueue() can be
+			called here even though the disinherit function does not check if
+			the scheduler is suspended before accessing the ready lists. */
+			( void ) prvCopyDataToQueue( pxQueue, pvItemToQueue, xCopyPosition );
+
+			/* The event list is not altered if the queue is locked.  This will
+			be done when the queue is unlocked later. */
+			if( cTxLock == queueUNLOCKED )
+			{
+				#if ( configUSE_QUEUE_SETS == 1 )
+				{
+					if( pxQueue->pxQueueSetContainer != NULL )
+					{
+						if( ( xCopyPosition == queueOVERWRITE ) && ( uxPreviousMessagesWaiting != ( UBaseType_t ) 0 ) )
+						{
+							/* Do not notify the queue set as an existing item
+							was overwritten in the queue so the number of items
+							in the queue has not changed. */
+							mtCOVERAGE_TEST_MARKER();
+						}
+						else if( prvNotifyQueueSetContainer( pxQueue ) != pdFALSE )
+						{
+							/* The queue is a member of a queue set, and posting
+							to the queue set caused a higher priority task to
+							unblock.  A context switch is required. */
+							if( pxHigherPriorityTaskWoken != NULL )
+							{
+								*pxHigherPriorityTaskWoken = pdTRUE;
+							}
+							else
+							{
+								mtCOVERAGE_TEST_MARKER();
+							}
+						}
+						else
+						{
+							mtCOVERAGE_TEST_MARKER();
+						}
+					}
+					else
+					{
+						if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
+						{
+							if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
+							{
+								/* The task waiting has a higher priority so
+								record that a context switch is required. */
+								if( pxHigherPriorityTaskWoken != NULL )
+								{
+									*pxHigherPriorityTaskWoken = pdTRUE;
+								}
+								else
+								{
+									mtCOVERAGE_TEST_MARKER();
+								}
+							}
+							else
+							{
+								mtCOVERAGE_TEST_MARKER();
+							}
+						}
+						else
+						{
+							mtCOVERAGE_TEST_MARKER();
+						}
+					}
+				}
+				#else /* configUSE_QUEUE_SETS */
+				{
+					if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
+					{
+						if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
+						{
+							/* The task waiting has a higher priority so record that a
+							context	switch is required. */
+							if( pxHigherPriorityTaskWoken != NULL )
+							{
+								*pxHigherPriorityTaskWoken = pdTRUE;
+							}
+							else
+							{
+								mtCOVERAGE_TEST_MARKER();
+							}
+						}
+						else
+						{
+							mtCOVERAGE_TEST_MARKER();
+						}
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+					
+					/* Not used in this path. */
+					( void ) uxPreviousMessagesWaiting;
+				}
+				#endif /* configUSE_QUEUE_SETS */
+			}
+			else
+			{
+				/* Increment the lock count so the task that unlocks the queue
+				knows that data was posted while it was locked. */
+				pxQueue->cTxLock = ( int8_t ) ( cTxLock + 1 );
+			}
+
+			xReturn = pdPASS;
+		}
+		else
+		{
+			traceQUEUE_SEND_FROM_ISR_FAILED( pxQueue );
+			xReturn = errQUEUE_FULL;
+		}
+	}
+	portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xQueueGiveFromISR( QueueHandle_t xQueue, BaseType_t * const pxHigherPriorityTaskWoken )
+{
+BaseType_t xReturn;
+UBaseType_t uxSavedInterruptStatus;
+Queue_t * const pxQueue = xQueue;
+
+	/* Similar to xQueueGenericSendFromISR() but used with semaphores where the
+	item size is 0.  Don't directly wake a task that was blocked on a queue
+	read, instead return a flag to say whether a context switch is required or
+	not (i.e. has a task with a higher priority than us been woken by this
+	post). */
+
+	configASSERT( pxQueue );
+
+	/* xQueueGenericSendFromISR() should be used instead of xQueueGiveFromISR()
+	if the item size is not 0. */
+	configASSERT( pxQueue->uxItemSize == 0 );
+
+	/* Normally a mutex would not be given from an interrupt, especially if
+	there is a mutex holder, as priority inheritance makes no sense for an
+	interrupts, only tasks. */
+	configASSERT( !( ( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX ) && ( pxQueue->u.xSemaphore.xMutexHolder != NULL ) ) );
+
+	/* RTOS ports that support interrupt nesting have the concept of a maximum
+	system call (or maximum API call) interrupt priority.  Interrupts that are
+	above the maximum system call priority are kept permanently enabled, even
+	when the RTOS kernel is in a critical section, but cannot make any calls to
+	FreeRTOS API functions.  If configASSERT() is defined in FreeRTOSConfig.h
+	then portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion
+	failure if a FreeRTOS API function is called from an interrupt that has been
+	assigned a priority above the configured maximum system call priority.
+	Only FreeRTOS functions that end in FromISR can be called from interrupts
+	that have been assigned a priority at or (logically) below the maximum
+	system call	interrupt priority.  FreeRTOS maintains a separate interrupt
+	safe API to ensure interrupt entry is as fast and as simple as possible.
+	More information (albeit Cortex-M specific) is provided on the following
+	link: http://www.freertos.org/RTOS-Cortex-M3-M4.html */
+	portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
+
+	uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
+	{
+		const UBaseType_t uxMessagesWaiting = pxQueue->uxMessagesWaiting;
+
+		/* When the queue is used to implement a semaphore no data is ever
+		moved through the queue but it is still valid to see if the queue 'has
+		space'. */
+		if( uxMessagesWaiting < pxQueue->uxLength )
+		{
+			const int8_t cTxLock = pxQueue->cTxLock;
+
+			traceQUEUE_SEND_FROM_ISR( pxQueue );
+
+			/* A task can only have an inherited priority if it is a mutex
+			holder - and if there is a mutex holder then the mutex cannot be
+			given from an ISR.  As this is the ISR version of the function it
+			can be assumed there is no mutex holder and no need to determine if
+			priority disinheritance is needed.  Simply increase the count of
+			messages (semaphores) available. */
+			pxQueue->uxMessagesWaiting = uxMessagesWaiting + ( UBaseType_t ) 1;
+
+			/* The event list is not altered if the queue is locked.  This will
+			be done when the queue is unlocked later. */
+			if( cTxLock == queueUNLOCKED )
+			{
+				#if ( configUSE_QUEUE_SETS == 1 )
+				{
+					if( pxQueue->pxQueueSetContainer != NULL )
+					{
+						if( prvNotifyQueueSetContainer( pxQueue ) != pdFALSE )
+						{
+							/* The semaphore is a member of a queue set, and
+							posting	to the queue set caused a higher priority
+							task to	unblock.  A context switch is required. */
+							if( pxHigherPriorityTaskWoken != NULL )
+							{
+								*pxHigherPriorityTaskWoken = pdTRUE;
+							}
+							else
+							{
+								mtCOVERAGE_TEST_MARKER();
+							}
+						}
+						else
+						{
+							mtCOVERAGE_TEST_MARKER();
+						}
+					}
+					else
+					{
+						if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
+						{
+							if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
+							{
+								/* The task waiting has a higher priority so
+								record that a context switch is required. */
+								if( pxHigherPriorityTaskWoken != NULL )
+								{
+									*pxHigherPriorityTaskWoken = pdTRUE;
+								}
+								else
+								{
+									mtCOVERAGE_TEST_MARKER();
+								}
+							}
+							else
+							{
+								mtCOVERAGE_TEST_MARKER();
+							}
+						}
+						else
+						{
+							mtCOVERAGE_TEST_MARKER();
+						}
+					}
+				}
+				#else /* configUSE_QUEUE_SETS */
+				{
+					if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
+					{
+						if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
+						{
+							/* The task waiting has a higher priority so record that a
+							context	switch is required. */
+							if( pxHigherPriorityTaskWoken != NULL )
+							{
+								*pxHigherPriorityTaskWoken = pdTRUE;
+							}
+							else
+							{
+								mtCOVERAGE_TEST_MARKER();
+							}
+						}
+						else
+						{
+							mtCOVERAGE_TEST_MARKER();
+						}
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				#endif /* configUSE_QUEUE_SETS */
+			}
+			else
+			{
+				/* Increment the lock count so the task that unlocks the queue
+				knows that data was posted while it was locked. */
+				pxQueue->cTxLock = ( int8_t ) ( cTxLock + 1 );
+			}
+
+			xReturn = pdPASS;
+		}
+		else
+		{
+			traceQUEUE_SEND_FROM_ISR_FAILED( pxQueue );
+			xReturn = errQUEUE_FULL;
+		}
+	}
+	portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xQueueReceive( QueueHandle_t xQueue, void * const pvBuffer, TickType_t xTicksToWait )
+{
+BaseType_t xEntryTimeSet = pdFALSE;
+TimeOut_t xTimeOut;
+Queue_t * const pxQueue = xQueue;
+
+	/* Check the pointer is not NULL. */
+	configASSERT( ( pxQueue ) );
+
+	/* The buffer into which data is received can only be NULL if the data size
+	is zero (so no data is copied into the buffer. */
+	configASSERT( !( ( ( pvBuffer ) == NULL ) && ( ( pxQueue )->uxItemSize != ( UBaseType_t ) 0U ) ) );
+
+	/* Cannot block if the scheduler is suspended. */
+	#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
+	{
+		configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) );
+	}
+	#endif
+
+
+	/*lint -save -e904  This function relaxes the coding standard somewhat to
+	allow return statements within the function itself.  This is done in the
+	interest of execution time efficiency. */
+	for( ;; )
+	{
+		taskENTER_CRITICAL();
+		{
+			const UBaseType_t uxMessagesWaiting = pxQueue->uxMessagesWaiting;
+
+			/* Is there data in the queue now?  To be running the calling task
+			must be the highest priority task wanting to access the queue. */
+			if( uxMessagesWaiting > ( UBaseType_t ) 0 )
+			{
+				/* Data available, remove one item. */
+				prvCopyDataFromQueue( pxQueue, pvBuffer );
+				traceQUEUE_RECEIVE( pxQueue );
+				pxQueue->uxMessagesWaiting = uxMessagesWaiting - ( UBaseType_t ) 1;
+
+				/* There is now space in the queue, were any tasks waiting to
+				post to the queue?  If so, unblock the highest priority waiting
+				task. */
+				if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
+				{
+					if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
+					{
+						queueYIELD_IF_USING_PREEMPTION();
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+
+				taskEXIT_CRITICAL();
+				return pdPASS;
+			}
+			else
+			{
+				if( xTicksToWait == ( TickType_t ) 0 )
+				{
+					/* The queue was empty and no block time is specified (or
+					the block time has expired) so leave now. */
+					taskEXIT_CRITICAL();
+					traceQUEUE_RECEIVE_FAILED( pxQueue );
+					return errQUEUE_EMPTY;
+				}
+				else if( xEntryTimeSet == pdFALSE )
+				{
+					/* The queue was empty and a block time was specified so
+					configure the timeout structure. */
+					vTaskInternalSetTimeOutState( &xTimeOut );
+					xEntryTimeSet = pdTRUE;
+				}
+				else
+				{
+					/* Entry time was already set. */
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+		}
+		taskEXIT_CRITICAL();
+
+		/* Interrupts and other tasks can send to and receive from the queue
+		now the critical section has been exited. */
+
+		vTaskSuspendAll();
+		prvLockQueue( pxQueue );
+
+		/* Update the timeout state to see if it has expired yet. */
+		if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE )
+		{
+			/* The timeout has not expired.  If the queue is still empty place
+			the task on the list of tasks waiting to receive from the queue. */
+			if( prvIsQueueEmpty( pxQueue ) != pdFALSE )
+			{
+				traceBLOCKING_ON_QUEUE_RECEIVE( pxQueue );
+				vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait );
+				prvUnlockQueue( pxQueue );
+				if( xTaskResumeAll() == pdFALSE )
+				{
+					portYIELD_WITHIN_API();
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				/* The queue contains data again.  Loop back to try and read the
+				data. */
+				prvUnlockQueue( pxQueue );
+				( void ) xTaskResumeAll();
+			}
+		}
+		else
+		{
+			/* Timed out.  If there is no data in the queue exit, otherwise loop
+			back and attempt to read the data. */
+			prvUnlockQueue( pxQueue );
+			( void ) xTaskResumeAll();
+
+			if( prvIsQueueEmpty( pxQueue ) != pdFALSE )
+			{
+				traceQUEUE_RECEIVE_FAILED( pxQueue );
+				return errQUEUE_EMPTY;
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+	} /*lint -restore */
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xQueueSemaphoreTake( QueueHandle_t xQueue, TickType_t xTicksToWait )
+{
+BaseType_t xEntryTimeSet = pdFALSE;
+TimeOut_t xTimeOut;
+Queue_t * const pxQueue = xQueue;
+
+#if( configUSE_MUTEXES == 1 )
+	BaseType_t xInheritanceOccurred = pdFALSE;
+#endif
+
+	/* Check the queue pointer is not NULL. */
+	configASSERT( ( pxQueue ) );
+
+	/* Check this really is a semaphore, in which case the item size will be
+	0. */
+	configASSERT( pxQueue->uxItemSize == 0 );
+
+	/* Cannot block if the scheduler is suspended. */
+	#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
+	{
+		configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) );
+	}
+	#endif
+
+
+	/*lint -save -e904 This function relaxes the coding standard somewhat to allow return
+	statements within the function itself.  This is done in the interest
+	of execution time efficiency. */
+	for( ;; )
+	{
+		taskENTER_CRITICAL();
+		{
+			/* Semaphores are queues with an item size of 0, and where the
+			number of messages in the queue is the semaphore's count value. */
+			const UBaseType_t uxSemaphoreCount = pxQueue->uxMessagesWaiting;
+
+			/* Is there data in the queue now?  To be running the calling task
+			must be the highest priority task wanting to access the queue. */
+			if( uxSemaphoreCount > ( UBaseType_t ) 0 )
+			{
+				traceQUEUE_RECEIVE( pxQueue );
+
+				/* Semaphores are queues with a data size of zero and where the
+				messages waiting is the semaphore's count.  Reduce the count. */
+				pxQueue->uxMessagesWaiting = uxSemaphoreCount - ( UBaseType_t ) 1;
+
+				#if ( configUSE_MUTEXES == 1 )
+				{
+					if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX )
+					{
+						/* Record the information required to implement
+						priority inheritance should it become necessary. */
+						pxQueue->u.xSemaphore.xMutexHolder = pvTaskIncrementMutexHeldCount();
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				#endif /* configUSE_MUTEXES */
+
+				/* Check to see if other tasks are blocked waiting to give the
+				semaphore, and if so, unblock the highest priority such task. */
+				if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
+				{
+					if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
+					{
+						queueYIELD_IF_USING_PREEMPTION();
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+
+				taskEXIT_CRITICAL();
+				return pdPASS;
+			}
+			else
+			{
+				if( xTicksToWait == ( TickType_t ) 0 )
+				{
+					/* For inheritance to have occurred there must have been an
+					initial timeout, and an adjusted timeout cannot become 0, as
+					if it were 0 the function would have exited. */
+					#if( configUSE_MUTEXES == 1 )
+					{
+						configASSERT( xInheritanceOccurred == pdFALSE );
+					}
+					#endif /* configUSE_MUTEXES */
+
+					/* The semaphore count was 0 and no block time is specified
+					(or the block time has expired) so exit now. */
+					taskEXIT_CRITICAL();
+					traceQUEUE_RECEIVE_FAILED( pxQueue );
+					return errQUEUE_EMPTY;
+				}
+				else if( xEntryTimeSet == pdFALSE )
+				{
+					/* The semaphore count was 0 and a block time was specified
+					so configure the timeout structure ready to block. */
+					vTaskInternalSetTimeOutState( &xTimeOut );
+					xEntryTimeSet = pdTRUE;
+				}
+				else
+				{
+					/* Entry time was already set. */
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+		}
+		taskEXIT_CRITICAL();
+
+		/* Interrupts and other tasks can give to and take from the semaphore
+		now the critical section has been exited. */
+
+		vTaskSuspendAll();
+		prvLockQueue( pxQueue );
+
+		/* Update the timeout state to see if it has expired yet. */
+		if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE )
+		{
+			/* A block time is specified and not expired.  If the semaphore
+			count is 0 then enter the Blocked state to wait for a semaphore to
+			become available.  As semaphores are implemented with queues the
+			queue being empty is equivalent to the semaphore count being 0. */
+			if( prvIsQueueEmpty( pxQueue ) != pdFALSE )
+			{
+				traceBLOCKING_ON_QUEUE_RECEIVE( pxQueue );
+
+				#if ( configUSE_MUTEXES == 1 )
+				{
+					if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX )
+					{
+						taskENTER_CRITICAL();
+						{
+							xInheritanceOccurred = xTaskPriorityInherit( pxQueue->u.xSemaphore.xMutexHolder );
+						}
+						taskEXIT_CRITICAL();
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				#endif
+
+				vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait );
+				prvUnlockQueue( pxQueue );
+				if( xTaskResumeAll() == pdFALSE )
+				{
+					portYIELD_WITHIN_API();
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				/* There was no timeout and the semaphore count was not 0, so
+				attempt to take the semaphore again. */
+				prvUnlockQueue( pxQueue );
+				( void ) xTaskResumeAll();
+			}
+		}
+		else
+		{
+			/* Timed out. */
+			prvUnlockQueue( pxQueue );
+			( void ) xTaskResumeAll();
+
+			/* If the semaphore count is 0 exit now as the timeout has
+			expired.  Otherwise return to attempt to take the semaphore that is
+			known to be available.  As semaphores are implemented by queues the
+			queue being empty is equivalent to the semaphore count being 0. */
+			if( prvIsQueueEmpty( pxQueue ) != pdFALSE )
+			{
+				#if ( configUSE_MUTEXES == 1 )
+				{
+					/* xInheritanceOccurred could only have be set if
+					pxQueue->uxQueueType == queueQUEUE_IS_MUTEX so no need to
+					test the mutex type again to check it is actually a mutex. */
+					if( xInheritanceOccurred != pdFALSE )
+					{
+						taskENTER_CRITICAL();
+						{
+							UBaseType_t uxHighestWaitingPriority;
+
+							/* This task blocking on the mutex caused another
+							task to inherit this task's priority.  Now this task
+							has timed out the priority should be disinherited
+							again, but only as low as the next highest priority
+							task that is waiting for the same mutex. */
+							uxHighestWaitingPriority = prvGetDisinheritPriorityAfterTimeout( pxQueue );
+							vTaskPriorityDisinheritAfterTimeout( pxQueue->u.xSemaphore.xMutexHolder, uxHighestWaitingPriority );
+						}
+						taskEXIT_CRITICAL();
+					}
+				}
+				#endif /* configUSE_MUTEXES */
+
+				traceQUEUE_RECEIVE_FAILED( pxQueue );
+				return errQUEUE_EMPTY;
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+	} /*lint -restore */
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xQueuePeek( QueueHandle_t xQueue, void * const pvBuffer, TickType_t xTicksToWait )
+{
+BaseType_t xEntryTimeSet = pdFALSE;
+TimeOut_t xTimeOut;
+int8_t *pcOriginalReadPosition;
+Queue_t * const pxQueue = xQueue;
+
+	/* Check the pointer is not NULL. */
+	configASSERT( ( pxQueue ) );
+
+	/* The buffer into which data is received can only be NULL if the data size
+	is zero (so no data is copied into the buffer. */
+	configASSERT( !( ( ( pvBuffer ) == NULL ) && ( ( pxQueue )->uxItemSize != ( UBaseType_t ) 0U ) ) );
+
+	/* Cannot block if the scheduler is suspended. */
+	#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
+	{
+		configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) );
+	}
+	#endif
+
+
+	/*lint -save -e904  This function relaxes the coding standard somewhat to
+	allow return statements within the function itself.  This is done in the
+	interest of execution time efficiency. */
+	for( ;; )
+	{
+		taskENTER_CRITICAL();
+		{
+			const UBaseType_t uxMessagesWaiting = pxQueue->uxMessagesWaiting;
+
+			/* Is there data in the queue now?  To be running the calling task
+			must be the highest priority task wanting to access the queue. */
+			if( uxMessagesWaiting > ( UBaseType_t ) 0 )
+			{
+				/* Remember the read position so it can be reset after the data
+				is read from the queue as this function is only peeking the
+				data, not removing it. */
+				pcOriginalReadPosition = pxQueue->u.xQueue.pcReadFrom;
+
+				prvCopyDataFromQueue( pxQueue, pvBuffer );
+				traceQUEUE_PEEK( pxQueue );
+
+				/* The data is not being removed, so reset the read pointer. */
+				pxQueue->u.xQueue.pcReadFrom = pcOriginalReadPosition;
+
+				/* The data is being left in the queue, so see if there are
+				any other tasks waiting for the data. */
+				if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
+				{
+					if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
+					{
+						/* The task waiting has a higher priority than this task. */
+						queueYIELD_IF_USING_PREEMPTION();
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+
+				taskEXIT_CRITICAL();
+				return pdPASS;
+			}
+			else
+			{
+				if( xTicksToWait == ( TickType_t ) 0 )
+				{
+					/* The queue was empty and no block time is specified (or
+					the block time has expired) so leave now. */
+					taskEXIT_CRITICAL();
+					traceQUEUE_PEEK_FAILED( pxQueue );
+					return errQUEUE_EMPTY;
+				}
+				else if( xEntryTimeSet == pdFALSE )
+				{
+					/* The queue was empty and a block time was specified so
+					configure the timeout structure ready to enter the blocked
+					state. */
+					vTaskInternalSetTimeOutState( &xTimeOut );
+					xEntryTimeSet = pdTRUE;
+				}
+				else
+				{
+					/* Entry time was already set. */
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+		}
+		taskEXIT_CRITICAL();
+
+		/* Interrupts and other tasks can send to and receive from the queue
+		now the critical section has been exited. */
+
+		vTaskSuspendAll();
+		prvLockQueue( pxQueue );
+
+		/* Update the timeout state to see if it has expired yet. */
+		if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE )
+		{
+			/* Timeout has not expired yet, check to see if there is data in the
+			queue now, and if not enter the Blocked state to wait for data. */
+			if( prvIsQueueEmpty( pxQueue ) != pdFALSE )
+			{
+				traceBLOCKING_ON_QUEUE_PEEK( pxQueue );
+				vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait );
+				prvUnlockQueue( pxQueue );
+				if( xTaskResumeAll() == pdFALSE )
+				{
+					portYIELD_WITHIN_API();
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				/* There is data in the queue now, so don't enter the blocked
+				state, instead return to try and obtain the data. */
+				prvUnlockQueue( pxQueue );
+				( void ) xTaskResumeAll();
+			}
+		}
+		else
+		{
+			/* The timeout has expired.  If there is still no data in the queue
+			exit, otherwise go back and try to read the data again. */
+			prvUnlockQueue( pxQueue );
+			( void ) xTaskResumeAll();
+
+			if( prvIsQueueEmpty( pxQueue ) != pdFALSE )
+			{
+				traceQUEUE_PEEK_FAILED( pxQueue );
+				return errQUEUE_EMPTY;
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+	} /*lint -restore */
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xQueueReceiveFromISR( QueueHandle_t xQueue, void * const pvBuffer, BaseType_t * const pxHigherPriorityTaskWoken )
+{
+BaseType_t xReturn;
+UBaseType_t uxSavedInterruptStatus;
+Queue_t * const pxQueue = xQueue;
+
+	configASSERT( pxQueue );
+	configASSERT( !( ( pvBuffer == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) );
+
+	/* RTOS ports that support interrupt nesting have the concept of a maximum
+	system call (or maximum API call) interrupt priority.  Interrupts that are
+	above the maximum system call priority are kept permanently enabled, even
+	when the RTOS kernel is in a critical section, but cannot make any calls to
+	FreeRTOS API functions.  If configASSERT() is defined in FreeRTOSConfig.h
+	then portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion
+	failure if a FreeRTOS API function is called from an interrupt that has been
+	assigned a priority above the configured maximum system call priority.
+	Only FreeRTOS functions that end in FromISR can be called from interrupts
+	that have been assigned a priority at or (logically) below the maximum
+	system call	interrupt priority.  FreeRTOS maintains a separate interrupt
+	safe API to ensure interrupt entry is as fast and as simple as possible.
+	More information (albeit Cortex-M specific) is provided on the following
+	link: http://www.freertos.org/RTOS-Cortex-M3-M4.html */
+	portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
+
+	uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
+	{
+		const UBaseType_t uxMessagesWaiting = pxQueue->uxMessagesWaiting;
+
+		/* Cannot block in an ISR, so check there is data available. */
+		if( uxMessagesWaiting > ( UBaseType_t ) 0 )
+		{
+			const int8_t cRxLock = pxQueue->cRxLock;
+
+			traceQUEUE_RECEIVE_FROM_ISR( pxQueue );
+
+			prvCopyDataFromQueue( pxQueue, pvBuffer );
+			pxQueue->uxMessagesWaiting = uxMessagesWaiting - ( UBaseType_t ) 1;
+
+			/* If the queue is locked the event list will not be modified.
+			Instead update the lock count so the task that unlocks the queue
+			will know that an ISR has removed data while the queue was
+			locked. */
+			if( cRxLock == queueUNLOCKED )
+			{
+				if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
+				{
+					if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
+					{
+						/* The task waiting has a higher priority than us so
+						force a context switch. */
+						if( pxHigherPriorityTaskWoken != NULL )
+						{
+							*pxHigherPriorityTaskWoken = pdTRUE;
+						}
+						else
+						{
+							mtCOVERAGE_TEST_MARKER();
+						}
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				/* Increment the lock count so the task that unlocks the queue
+				knows that data was removed while it was locked. */
+				pxQueue->cRxLock = ( int8_t ) ( cRxLock + 1 );
+			}
+
+			xReturn = pdPASS;
+		}
+		else
+		{
+			xReturn = pdFAIL;
+			traceQUEUE_RECEIVE_FROM_ISR_FAILED( pxQueue );
+		}
+	}
+	portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xQueuePeekFromISR( QueueHandle_t xQueue,  void * const pvBuffer )
+{
+BaseType_t xReturn;
+UBaseType_t uxSavedInterruptStatus;
+int8_t *pcOriginalReadPosition;
+Queue_t * const pxQueue = xQueue;
+
+	configASSERT( pxQueue );
+	configASSERT( !( ( pvBuffer == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) );
+	configASSERT( pxQueue->uxItemSize != 0 ); /* Can't peek a semaphore. */
+
+	/* RTOS ports that support interrupt nesting have the concept of a maximum
+	system call (or maximum API call) interrupt priority.  Interrupts that are
+	above the maximum system call priority are kept permanently enabled, even
+	when the RTOS kernel is in a critical section, but cannot make any calls to
+	FreeRTOS API functions.  If configASSERT() is defined in FreeRTOSConfig.h
+	then portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion
+	failure if a FreeRTOS API function is called from an interrupt that has been
+	assigned a priority above the configured maximum system call priority.
+	Only FreeRTOS functions that end in FromISR can be called from interrupts
+	that have been assigned a priority at or (logically) below the maximum
+	system call	interrupt priority.  FreeRTOS maintains a separate interrupt
+	safe API to ensure interrupt entry is as fast and as simple as possible.
+	More information (albeit Cortex-M specific) is provided on the following
+	link: http://www.freertos.org/RTOS-Cortex-M3-M4.html */
+	portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
+
+	uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
+	{
+		/* Cannot block in an ISR, so check there is data available. */
+		if( pxQueue->uxMessagesWaiting > ( UBaseType_t ) 0 )
+		{
+			traceQUEUE_PEEK_FROM_ISR( pxQueue );
+
+			/* Remember the read position so it can be reset as nothing is
+			actually being removed from the queue. */
+			pcOriginalReadPosition = pxQueue->u.xQueue.pcReadFrom;
+			prvCopyDataFromQueue( pxQueue, pvBuffer );
+			pxQueue->u.xQueue.pcReadFrom = pcOriginalReadPosition;
+
+			xReturn = pdPASS;
+		}
+		else
+		{
+			xReturn = pdFAIL;
+			traceQUEUE_PEEK_FROM_ISR_FAILED( pxQueue );
+		}
+	}
+	portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+UBaseType_t uxQueueMessagesWaiting( const QueueHandle_t xQueue )
+{
+UBaseType_t uxReturn;
+
+	configASSERT( xQueue );
+
+	taskENTER_CRITICAL();
+	{
+		uxReturn = ( ( Queue_t * ) xQueue )->uxMessagesWaiting;
+	}
+	taskEXIT_CRITICAL();
+
+	return uxReturn;
+} /*lint !e818 Pointer cannot be declared const as xQueue is a typedef not pointer. */
+/*-----------------------------------------------------------*/
+
+UBaseType_t uxQueueSpacesAvailable( const QueueHandle_t xQueue )
+{
+UBaseType_t uxReturn;
+Queue_t * const pxQueue = xQueue;
+
+	configASSERT( pxQueue );
+
+	taskENTER_CRITICAL();
+	{
+		uxReturn = pxQueue->uxLength - pxQueue->uxMessagesWaiting;
+	}
+	taskEXIT_CRITICAL();
+
+	return uxReturn;
+} /*lint !e818 Pointer cannot be declared const as xQueue is a typedef not pointer. */
+/*-----------------------------------------------------------*/
+
+UBaseType_t uxQueueMessagesWaitingFromISR( const QueueHandle_t xQueue )
+{
+UBaseType_t uxReturn;
+Queue_t * const pxQueue = xQueue;
+
+	configASSERT( pxQueue );
+	uxReturn = pxQueue->uxMessagesWaiting;
+
+	return uxReturn;
+} /*lint !e818 Pointer cannot be declared const as xQueue is a typedef not pointer. */
+/*-----------------------------------------------------------*/
+
+void vQueueDelete( QueueHandle_t xQueue )
+{
+Queue_t * const pxQueue = xQueue;
+
+	configASSERT( pxQueue );
+	traceQUEUE_DELETE( pxQueue );
+
+	#if ( configQUEUE_REGISTRY_SIZE > 0 )
+	{
+		vQueueUnregisterQueue( pxQueue );
+	}
+	#endif
+
+	#if( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 0 ) )
+	{
+		/* The queue can only have been allocated dynamically - free it
+		again. */
+		vPortFree( pxQueue );
+	}
+	#elif( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) )
+	{
+		/* The queue could have been allocated statically or dynamically, so
+		check before attempting to free the memory. */
+		if( pxQueue->ucStaticallyAllocated == ( uint8_t ) pdFALSE )
+		{
+			vPortFree( pxQueue );
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+	#else
+	{
+		/* The queue must have been statically allocated, so is not going to be
+		deleted.  Avoid compiler warnings about the unused parameter. */
+		( void ) pxQueue;
+	}
+	#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
+}
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TRACE_FACILITY == 1 )
+
+	UBaseType_t uxQueueGetQueueNumber( QueueHandle_t xQueue )
+	{
+		return ( ( Queue_t * ) xQueue )->uxQueueNumber;
+	}
+
+#endif /* configUSE_TRACE_FACILITY */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TRACE_FACILITY == 1 )
+
+	void vQueueSetQueueNumber( QueueHandle_t xQueue, UBaseType_t uxQueueNumber )
+	{
+		( ( Queue_t * ) xQueue )->uxQueueNumber = uxQueueNumber;
+	}
+
+#endif /* configUSE_TRACE_FACILITY */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TRACE_FACILITY == 1 )
+
+	uint8_t ucQueueGetQueueType( QueueHandle_t xQueue )
+	{
+		return ( ( Queue_t * ) xQueue )->ucQueueType;
+	}
+
+#endif /* configUSE_TRACE_FACILITY */
+/*-----------------------------------------------------------*/
+
+#if( configUSE_MUTEXES == 1 )
+
+	static UBaseType_t prvGetDisinheritPriorityAfterTimeout( const Queue_t * const pxQueue )
+	{
+	UBaseType_t uxHighestPriorityOfWaitingTasks;
+
+		/* If a task waiting for a mutex causes the mutex holder to inherit a
+		priority, but the waiting task times out, then the holder should
+		disinherit the priority - but only down to the highest priority of any
+		other tasks that are waiting for the same mutex.  For this purpose,
+		return the priority of the highest priority task that is waiting for the
+		mutex. */
+		if( listCURRENT_LIST_LENGTH( &( pxQueue->xTasksWaitingToReceive ) ) > 0U )
+		{
+			uxHighestPriorityOfWaitingTasks = ( UBaseType_t ) configMAX_PRIORITIES - ( UBaseType_t ) listGET_ITEM_VALUE_OF_HEAD_ENTRY( &( pxQueue->xTasksWaitingToReceive ) );
+		}
+		else
+		{
+			uxHighestPriorityOfWaitingTasks = tskIDLE_PRIORITY;
+		}
+
+		return uxHighestPriorityOfWaitingTasks;
+	}
+
+#endif /* configUSE_MUTEXES */
+/*-----------------------------------------------------------*/
+
+static BaseType_t prvCopyDataToQueue( Queue_t * const pxQueue, const void *pvItemToQueue, const BaseType_t xPosition )
+{
+BaseType_t xReturn = pdFALSE;
+UBaseType_t uxMessagesWaiting;
+
+	/* This function is called from a critical section. */
+
+	uxMessagesWaiting = pxQueue->uxMessagesWaiting;
+
+	if( pxQueue->uxItemSize == ( UBaseType_t ) 0 )
+	{
+		#if ( configUSE_MUTEXES == 1 )
+		{
+			if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX )
+			{
+				/* The mutex is no longer being held. */
+				xReturn = xTaskPriorityDisinherit( pxQueue->u.xSemaphore.xMutexHolder );
+				pxQueue->u.xSemaphore.xMutexHolder = NULL;
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		#endif /* configUSE_MUTEXES */
+	}
+	else if( xPosition == queueSEND_TO_BACK )
+	{
+		( void ) memcpy( ( void * ) pxQueue->pcWriteTo, pvItemToQueue, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e418 !e9087 MISRA exception as the casts are only redundant for some ports, plus previous logic ensures a null pointer can only be passed to memcpy() if the copy size is 0.  Cast to void required by function signature and safe as no alignment requirement and copy length specified in bytes. */
+		pxQueue->pcWriteTo += pxQueue->uxItemSize; /*lint !e9016 Pointer arithmetic on char types ok, especially in this use case where it is the clearest way of conveying intent. */
+		if( pxQueue->pcWriteTo >= pxQueue->u.xQueue.pcTail ) /*lint !e946 MISRA exception justified as comparison of pointers is the cleanest solution. */
+		{
+			pxQueue->pcWriteTo = pxQueue->pcHead;
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+	else
+	{
+		( void ) memcpy( ( void * ) pxQueue->u.xQueue.pcReadFrom, pvItemToQueue, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e9087 !e418 MISRA exception as the casts are only redundant for some ports.  Cast to void required by function signature and safe as no alignment requirement and copy length specified in bytes.  Assert checks null pointer only used when length is 0. */
+		pxQueue->u.xQueue.pcReadFrom -= pxQueue->uxItemSize;
+		if( pxQueue->u.xQueue.pcReadFrom < pxQueue->pcHead ) /*lint !e946 MISRA exception justified as comparison of pointers is the cleanest solution. */
+		{
+			pxQueue->u.xQueue.pcReadFrom = ( pxQueue->u.xQueue.pcTail - pxQueue->uxItemSize );
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+
+		if( xPosition == queueOVERWRITE )
+		{
+			if( uxMessagesWaiting > ( UBaseType_t ) 0 )
+			{
+				/* An item is not being added but overwritten, so subtract
+				one from the recorded number of items in the queue so when
+				one is added again below the number of recorded items remains
+				correct. */
+				--uxMessagesWaiting;
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+
+	pxQueue->uxMessagesWaiting = uxMessagesWaiting + ( UBaseType_t ) 1;
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+static void prvCopyDataFromQueue( Queue_t * const pxQueue, void * const pvBuffer )
+{
+	if( pxQueue->uxItemSize != ( UBaseType_t ) 0 )
+	{
+		pxQueue->u.xQueue.pcReadFrom += pxQueue->uxItemSize; /*lint !e9016 Pointer arithmetic on char types ok, especially in this use case where it is the clearest way of conveying intent. */
+		if( pxQueue->u.xQueue.pcReadFrom >= pxQueue->u.xQueue.pcTail ) /*lint !e946 MISRA exception justified as use of the relational operator is the cleanest solutions. */
+		{
+			pxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead;
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+		( void ) memcpy( ( void * ) pvBuffer, ( void * ) pxQueue->u.xQueue.pcReadFrom, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e418 !e9087 MISRA exception as the casts are only redundant for some ports.  Also previous logic ensures a null pointer can only be passed to memcpy() when the count is 0.  Cast to void required by function signature and safe as no alignment requirement and copy length specified in bytes. */
+	}
+}
+/*-----------------------------------------------------------*/
+
+static void prvUnlockQueue( Queue_t * const pxQueue )
+{
+	/* THIS FUNCTION MUST BE CALLED WITH THE SCHEDULER SUSPENDED. */
+
+	/* The lock counts contains the number of extra data items placed or
+	removed from the queue while the queue was locked.  When a queue is
+	locked items can be added or removed, but the event lists cannot be
+	updated. */
+	taskENTER_CRITICAL();
+	{
+		int8_t cTxLock = pxQueue->cTxLock;
+
+		/* See if data was added to the queue while it was locked. */
+		while( cTxLock > queueLOCKED_UNMODIFIED )
+		{
+			/* Data was posted while the queue was locked.  Are any tasks
+			blocked waiting for data to become available? */
+			#if ( configUSE_QUEUE_SETS == 1 )
+			{
+				if( pxQueue->pxQueueSetContainer != NULL )
+				{
+					if( prvNotifyQueueSetContainer( pxQueue ) != pdFALSE )
+					{
+						/* The queue is a member of a queue set, and posting to
+						the queue set caused a higher priority task to unblock.
+						A context switch is required. */
+						vTaskMissedYield();
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				else
+				{
+					/* Tasks that are removed from the event list will get
+					added to the pending ready list as the scheduler is still
+					suspended. */
+					if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
+					{
+						if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
+						{
+							/* The task waiting has a higher priority so record that a
+							context	switch is required. */
+							vTaskMissedYield();
+						}
+						else
+						{
+							mtCOVERAGE_TEST_MARKER();
+						}
+					}
+					else
+					{
+						break;
+					}
+				}
+			}
+			#else /* configUSE_QUEUE_SETS */
+			{
+				/* Tasks that are removed from the event list will get added to
+				the pending ready list as the scheduler is still suspended. */
+				if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
+				{
+					if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
+					{
+						/* The task waiting has a higher priority so record that
+						a context switch is required. */
+						vTaskMissedYield();
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				else
+				{
+					break;
+				}
+			}
+			#endif /* configUSE_QUEUE_SETS */
+
+			--cTxLock;
+		}
+
+		pxQueue->cTxLock = queueUNLOCKED;
+	}
+	taskEXIT_CRITICAL();
+
+	/* Do the same for the Rx lock. */
+	taskENTER_CRITICAL();
+	{
+		int8_t cRxLock = pxQueue->cRxLock;
+
+		while( cRxLock > queueLOCKED_UNMODIFIED )
+		{
+			if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
+			{
+				if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
+				{
+					vTaskMissedYield();
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+
+				--cRxLock;
+			}
+			else
+			{
+				break;
+			}
+		}
+
+		pxQueue->cRxLock = queueUNLOCKED;
+	}
+	taskEXIT_CRITICAL();
+}
+/*-----------------------------------------------------------*/
+
+static BaseType_t prvIsQueueEmpty( const Queue_t *pxQueue )
+{
+BaseType_t xReturn;
+
+	taskENTER_CRITICAL();
+	{
+		if( pxQueue->uxMessagesWaiting == ( UBaseType_t )  0 )
+		{
+			xReturn = pdTRUE;
+		}
+		else
+		{
+			xReturn = pdFALSE;
+		}
+	}
+	taskEXIT_CRITICAL();
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xQueueIsQueueEmptyFromISR( const QueueHandle_t xQueue )
+{
+BaseType_t xReturn;
+Queue_t * const pxQueue = xQueue;
+
+	configASSERT( pxQueue );
+	if( pxQueue->uxMessagesWaiting == ( UBaseType_t ) 0 )
+	{
+		xReturn = pdTRUE;
+	}
+	else
+	{
+		xReturn = pdFALSE;
+	}
+
+	return xReturn;
+} /*lint !e818 xQueue could not be pointer to const because it is a typedef. */
+/*-----------------------------------------------------------*/
+
+static BaseType_t prvIsQueueFull( const Queue_t *pxQueue )
+{
+BaseType_t xReturn;
+
+	taskENTER_CRITICAL();
+	{
+		if( pxQueue->uxMessagesWaiting == pxQueue->uxLength )
+		{
+			xReturn = pdTRUE;
+		}
+		else
+		{
+			xReturn = pdFALSE;
+		}
+	}
+	taskEXIT_CRITICAL();
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xQueueIsQueueFullFromISR( const QueueHandle_t xQueue )
+{
+BaseType_t xReturn;
+Queue_t * const pxQueue = xQueue;
+
+	configASSERT( pxQueue );
+	if( pxQueue->uxMessagesWaiting == pxQueue->uxLength )
+	{
+		xReturn = pdTRUE;
+	}
+	else
+	{
+		xReturn = pdFALSE;
+	}
+
+	return xReturn;
+} /*lint !e818 xQueue could not be pointer to const because it is a typedef. */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_CO_ROUTINES == 1 )
+
+	BaseType_t xQueueCRSend( QueueHandle_t xQueue, const void *pvItemToQueue, TickType_t xTicksToWait )
+	{
+	BaseType_t xReturn;
+	Queue_t * const pxQueue = xQueue;
+
+		/* If the queue is already full we may have to block.  A critical section
+		is required to prevent an interrupt removing something from the queue
+		between the check to see if the queue is full and blocking on the queue. */
+		portDISABLE_INTERRUPTS();
+		{
+			if( prvIsQueueFull( pxQueue ) != pdFALSE )
+			{
+				/* The queue is full - do we want to block or just leave without
+				posting? */
+				if( xTicksToWait > ( TickType_t ) 0 )
+				{
+					/* As this is called from a coroutine we cannot block directly, but
+					return indicating that we need to block. */
+					vCoRoutineAddToDelayedList( xTicksToWait, &( pxQueue->xTasksWaitingToSend ) );
+					portENABLE_INTERRUPTS();
+					return errQUEUE_BLOCKED;
+				}
+				else
+				{
+					portENABLE_INTERRUPTS();
+					return errQUEUE_FULL;
+				}
+			}
+		}
+		portENABLE_INTERRUPTS();
+
+		portDISABLE_INTERRUPTS();
+		{
+			if( pxQueue->uxMessagesWaiting < pxQueue->uxLength )
+			{
+				/* There is room in the queue, copy the data into the queue. */
+				prvCopyDataToQueue( pxQueue, pvItemToQueue, queueSEND_TO_BACK );
+				xReturn = pdPASS;
+
+				/* Were any co-routines waiting for data to become available? */
+				if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
+				{
+					/* In this instance the co-routine could be placed directly
+					into the ready list as we are within a critical section.
+					Instead the same pending ready list mechanism is used as if
+					the event were caused from within an interrupt. */
+					if( xCoRoutineRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
+					{
+						/* The co-routine waiting has a higher priority so record
+						that a yield might be appropriate. */
+						xReturn = errQUEUE_YIELD;
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				xReturn = errQUEUE_FULL;
+			}
+		}
+		portENABLE_INTERRUPTS();
+
+		return xReturn;
+	}
+
+#endif /* configUSE_CO_ROUTINES */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_CO_ROUTINES == 1 )
+
+	BaseType_t xQueueCRReceive( QueueHandle_t xQueue, void *pvBuffer, TickType_t xTicksToWait )
+	{
+	BaseType_t xReturn;
+	Queue_t * const pxQueue = xQueue;
+
+		/* If the queue is already empty we may have to block.  A critical section
+		is required to prevent an interrupt adding something to the queue
+		between the check to see if the queue is empty and blocking on the queue. */
+		portDISABLE_INTERRUPTS();
+		{
+			if( pxQueue->uxMessagesWaiting == ( UBaseType_t ) 0 )
+			{
+				/* There are no messages in the queue, do we want to block or just
+				leave with nothing? */
+				if( xTicksToWait > ( TickType_t ) 0 )
+				{
+					/* As this is a co-routine we cannot block directly, but return
+					indicating that we need to block. */
+					vCoRoutineAddToDelayedList( xTicksToWait, &( pxQueue->xTasksWaitingToReceive ) );
+					portENABLE_INTERRUPTS();
+					return errQUEUE_BLOCKED;
+				}
+				else
+				{
+					portENABLE_INTERRUPTS();
+					return errQUEUE_FULL;
+				}
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		portENABLE_INTERRUPTS();
+
+		portDISABLE_INTERRUPTS();
+		{
+			if( pxQueue->uxMessagesWaiting > ( UBaseType_t ) 0 )
+			{
+				/* Data is available from the queue. */
+				pxQueue->u.xQueue.pcReadFrom += pxQueue->uxItemSize;
+				if( pxQueue->u.xQueue.pcReadFrom >= pxQueue->u.xQueue.pcTail )
+				{
+					pxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead;
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+				--( pxQueue->uxMessagesWaiting );
+				( void ) memcpy( ( void * ) pvBuffer, ( void * ) pxQueue->u.xQueue.pcReadFrom, ( unsigned ) pxQueue->uxItemSize );
+
+				xReturn = pdPASS;
+
+				/* Were any co-routines waiting for space to become available? */
+				if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
+				{
+					/* In this instance the co-routine could be placed directly
+					into the ready list as we are within a critical section.
+					Instead the same pending ready list mechanism is used as if
+					the event were caused from within an interrupt. */
+					if( xCoRoutineRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
+					{
+						xReturn = errQUEUE_YIELD;
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				xReturn = pdFAIL;
+			}
+		}
+		portENABLE_INTERRUPTS();
+
+		return xReturn;
+	}
+
+#endif /* configUSE_CO_ROUTINES */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_CO_ROUTINES == 1 )
+
+	BaseType_t xQueueCRSendFromISR( QueueHandle_t xQueue, const void *pvItemToQueue, BaseType_t xCoRoutinePreviouslyWoken )
+	{
+	Queue_t * const pxQueue = xQueue;
+
+		/* Cannot block within an ISR so if there is no space on the queue then
+		exit without doing anything. */
+		if( pxQueue->uxMessagesWaiting < pxQueue->uxLength )
+		{
+			prvCopyDataToQueue( pxQueue, pvItemToQueue, queueSEND_TO_BACK );
+
+			/* We only want to wake one co-routine per ISR, so check that a
+			co-routine has not already been woken. */
+			if( xCoRoutinePreviouslyWoken == pdFALSE )
+			{
+				if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
+				{
+					if( xCoRoutineRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
+					{
+						return pdTRUE;
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+
+		return xCoRoutinePreviouslyWoken;
+	}
+
+#endif /* configUSE_CO_ROUTINES */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_CO_ROUTINES == 1 )
+
+	BaseType_t xQueueCRReceiveFromISR( QueueHandle_t xQueue, void *pvBuffer, BaseType_t *pxCoRoutineWoken )
+	{
+	BaseType_t xReturn;
+	Queue_t * const pxQueue = xQueue;
+
+		/* We cannot block from an ISR, so check there is data available. If
+		not then just leave without doing anything. */
+		if( pxQueue->uxMessagesWaiting > ( UBaseType_t ) 0 )
+		{
+			/* Copy the data from the queue. */
+			pxQueue->u.xQueue.pcReadFrom += pxQueue->uxItemSize;
+			if( pxQueue->u.xQueue.pcReadFrom >= pxQueue->u.xQueue.pcTail )
+			{
+				pxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead;
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+			--( pxQueue->uxMessagesWaiting );
+			( void ) memcpy( ( void * ) pvBuffer, ( void * ) pxQueue->u.xQueue.pcReadFrom, ( unsigned ) pxQueue->uxItemSize );
+
+			if( ( *pxCoRoutineWoken ) == pdFALSE )
+			{
+				if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
+				{
+					if( xCoRoutineRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
+					{
+						*pxCoRoutineWoken = pdTRUE;
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+
+			xReturn = pdPASS;
+		}
+		else
+		{
+			xReturn = pdFAIL;
+		}
+
+		return xReturn;
+	}
+
+#endif /* configUSE_CO_ROUTINES */
+/*-----------------------------------------------------------*/
+
+#if ( configQUEUE_REGISTRY_SIZE > 0 )
+
+	void vQueueAddToRegistry( QueueHandle_t xQueue, const char *pcQueueName ) /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+	{
+	UBaseType_t ux;
+
+		/* See if there is an empty space in the registry.  A NULL name denotes
+		a free slot. */
+		for( ux = ( UBaseType_t ) 0U; ux < ( UBaseType_t ) configQUEUE_REGISTRY_SIZE; ux++ )
+		{
+			if( xQueueRegistry[ ux ].pcQueueName == NULL )
+			{
+				/* Store the information on this queue. */
+				xQueueRegistry[ ux ].pcQueueName = pcQueueName;
+				xQueueRegistry[ ux ].xHandle = xQueue;
+
+				traceQUEUE_REGISTRY_ADD( xQueue, pcQueueName );
+				break;
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+	}
+
+#endif /* configQUEUE_REGISTRY_SIZE */
+/*-----------------------------------------------------------*/
+
+#if ( configQUEUE_REGISTRY_SIZE > 0 )
+
+	const char *pcQueueGetName( QueueHandle_t xQueue ) /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+	{
+	UBaseType_t ux;
+	const char *pcReturn = NULL; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+
+		/* Note there is nothing here to protect against another task adding or
+		removing entries from the registry while it is being searched. */
+		for( ux = ( UBaseType_t ) 0U; ux < ( UBaseType_t ) configQUEUE_REGISTRY_SIZE; ux++ )
+		{
+			if( xQueueRegistry[ ux ].xHandle == xQueue )
+			{
+				pcReturn = xQueueRegistry[ ux ].pcQueueName;
+				break;
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+
+		return pcReturn;
+	} /*lint !e818 xQueue cannot be a pointer to const because it is a typedef. */
+
+#endif /* configQUEUE_REGISTRY_SIZE */
+/*-----------------------------------------------------------*/
+
+#if ( configQUEUE_REGISTRY_SIZE > 0 )
+
+	void vQueueUnregisterQueue( QueueHandle_t xQueue )
+	{
+	UBaseType_t ux;
+
+		/* See if the handle of the queue being unregistered in actually in the
+		registry. */
+		for( ux = ( UBaseType_t ) 0U; ux < ( UBaseType_t ) configQUEUE_REGISTRY_SIZE; ux++ )
+		{
+			if( xQueueRegistry[ ux ].xHandle == xQueue )
+			{
+				/* Set the name to NULL to show that this slot if free again. */
+				xQueueRegistry[ ux ].pcQueueName = NULL;
+
+				/* Set the handle to NULL to ensure the same queue handle cannot
+				appear in the registry twice if it is added, removed, then
+				added again. */
+				xQueueRegistry[ ux ].xHandle = ( QueueHandle_t ) 0;
+				break;
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+
+	} /*lint !e818 xQueue could not be pointer to const because it is a typedef. */
+
+#endif /* configQUEUE_REGISTRY_SIZE */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TIMERS == 1 )
+
+	void vQueueWaitForMessageRestricted( QueueHandle_t xQueue, TickType_t xTicksToWait, const BaseType_t xWaitIndefinitely )
+	{
+	Queue_t * const pxQueue = xQueue;
+
+		/* This function should not be called by application code hence the
+		'Restricted' in its name.  It is not part of the public API.  It is
+		designed for use by kernel code, and has special calling requirements.
+		It can result in vListInsert() being called on a list that can only
+		possibly ever have one item in it, so the list will be fast, but even
+		so it should be called with the scheduler locked and not from a critical
+		section. */
+
+		/* Only do anything if there are no messages in the queue.  This function
+		will not actually cause the task to block, just place it on a blocked
+		list.  It will not block until the scheduler is unlocked - at which
+		time a yield will be performed.  If an item is added to the queue while
+		the queue is locked, and the calling task blocks on the queue, then the
+		calling task will be immediately unblocked when the queue is unlocked. */
+		prvLockQueue( pxQueue );
+		if( pxQueue->uxMessagesWaiting == ( UBaseType_t ) 0U )
+		{
+			/* There is nothing in the queue, block for the specified period. */
+			vTaskPlaceOnEventListRestricted( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait, xWaitIndefinitely );
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+		prvUnlockQueue( pxQueue );
+	}
+
+#endif /* configUSE_TIMERS */
+/*-----------------------------------------------------------*/
+
+#if( ( configUSE_QUEUE_SETS == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
+
+	QueueSetHandle_t xQueueCreateSet( const UBaseType_t uxEventQueueLength )
+	{
+	QueueSetHandle_t pxQueue;
+
+		pxQueue = xQueueGenericCreate( uxEventQueueLength, ( UBaseType_t ) sizeof( Queue_t * ), queueQUEUE_TYPE_SET );
+
+		return pxQueue;
+	}
+
+#endif /* configUSE_QUEUE_SETS */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_QUEUE_SETS == 1 )
+
+	BaseType_t xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore, QueueSetHandle_t xQueueSet )
+	{
+	BaseType_t xReturn;
+
+		taskENTER_CRITICAL();
+		{
+			if( ( ( Queue_t * ) xQueueOrSemaphore )->pxQueueSetContainer != NULL )
+			{
+				/* Cannot add a queue/semaphore to more than one queue set. */
+				xReturn = pdFAIL;
+			}
+			else if( ( ( Queue_t * ) xQueueOrSemaphore )->uxMessagesWaiting != ( UBaseType_t ) 0 )
+			{
+				/* Cannot add a queue/semaphore to a queue set if there are already
+				items in the queue/semaphore. */
+				xReturn = pdFAIL;
+			}
+			else
+			{
+				( ( Queue_t * ) xQueueOrSemaphore )->pxQueueSetContainer = xQueueSet;
+				xReturn = pdPASS;
+			}
+		}
+		taskEXIT_CRITICAL();
+
+		return xReturn;
+	}
+
+#endif /* configUSE_QUEUE_SETS */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_QUEUE_SETS == 1 )
+
+	BaseType_t xQueueRemoveFromSet( QueueSetMemberHandle_t xQueueOrSemaphore, QueueSetHandle_t xQueueSet )
+	{
+	BaseType_t xReturn;
+	Queue_t * const pxQueueOrSemaphore = ( Queue_t * ) xQueueOrSemaphore;
+
+		if( pxQueueOrSemaphore->pxQueueSetContainer != xQueueSet )
+		{
+			/* The queue was not a member of the set. */
+			xReturn = pdFAIL;
+		}
+		else if( pxQueueOrSemaphore->uxMessagesWaiting != ( UBaseType_t ) 0 )
+		{
+			/* It is dangerous to remove a queue from a set when the queue is
+			not empty because the queue set will still hold pending events for
+			the queue. */
+			xReturn = pdFAIL;
+		}
+		else
+		{
+			taskENTER_CRITICAL();
+			{
+				/* The queue is no longer contained in the set. */
+				pxQueueOrSemaphore->pxQueueSetContainer = NULL;
+			}
+			taskEXIT_CRITICAL();
+			xReturn = pdPASS;
+		}
+
+		return xReturn;
+	} /*lint !e818 xQueueSet could not be declared as pointing to const as it is a typedef. */
+
+#endif /* configUSE_QUEUE_SETS */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_QUEUE_SETS == 1 )
+
+	QueueSetMemberHandle_t xQueueSelectFromSet( QueueSetHandle_t xQueueSet, TickType_t const xTicksToWait )
+	{
+	QueueSetMemberHandle_t xReturn = NULL;
+
+		( void ) xQueueReceive( ( QueueHandle_t ) xQueueSet, &xReturn, xTicksToWait ); /*lint !e961 Casting from one typedef to another is not redundant. */
+		return xReturn;
+	}
+
+#endif /* configUSE_QUEUE_SETS */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_QUEUE_SETS == 1 )
+
+	QueueSetMemberHandle_t xQueueSelectFromSetFromISR( QueueSetHandle_t xQueueSet )
+	{
+	QueueSetMemberHandle_t xReturn = NULL;
+
+		( void ) xQueueReceiveFromISR( ( QueueHandle_t ) xQueueSet, &xReturn, NULL ); /*lint !e961 Casting from one typedef to another is not redundant. */
+		return xReturn;
+	}
+
+#endif /* configUSE_QUEUE_SETS */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_QUEUE_SETS == 1 )
+
+	static BaseType_t prvNotifyQueueSetContainer( const Queue_t * const pxQueue )
+	{
+	Queue_t *pxQueueSetContainer = pxQueue->pxQueueSetContainer;
+	BaseType_t xReturn = pdFALSE;
+
+		/* This function must be called form a critical section. */
+
+		configASSERT( pxQueueSetContainer );
+		configASSERT( pxQueueSetContainer->uxMessagesWaiting < pxQueueSetContainer->uxLength );
+
+		if( pxQueueSetContainer->uxMessagesWaiting < pxQueueSetContainer->uxLength )
+		{
+			const int8_t cTxLock = pxQueueSetContainer->cTxLock;
+
+			traceQUEUE_SEND( pxQueueSetContainer );
+
+			/* The data copied is the handle of the queue that contains data. */
+			xReturn = prvCopyDataToQueue( pxQueueSetContainer, &pxQueue, queueSEND_TO_BACK );
+
+			if( cTxLock == queueUNLOCKED )
+			{
+				if( listLIST_IS_EMPTY( &( pxQueueSetContainer->xTasksWaitingToReceive ) ) == pdFALSE )
+				{
+					if( xTaskRemoveFromEventList( &( pxQueueSetContainer->xTasksWaitingToReceive ) ) != pdFALSE )
+					{
+						/* The task waiting has a higher priority. */
+						xReturn = pdTRUE;
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				pxQueueSetContainer->cTxLock = ( int8_t ) ( cTxLock + 1 );
+			}
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+
+		return xReturn;
+	}
+
+#endif /* configUSE_QUEUE_SETS */
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.c b/Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.c
new file mode 100644
index 0000000..c88e4ea
--- /dev/null
+++ b/Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.c
@@ -0,0 +1,1263 @@
+/*
+ * FreeRTOS Kernel V10.3.1
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Standard includes. */
+#include <stdint.h>
+#include <string.h>
+
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
+all the API functions to use the MPU wrappers.  That should only be done when
+task.h is included from an application file. */
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+/* FreeRTOS includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+#include "stream_buffer.h"
+
+#if( configUSE_TASK_NOTIFICATIONS != 1 )
+	#error configUSE_TASK_NOTIFICATIONS must be set to 1 to build stream_buffer.c
+#endif
+
+/* Lint e961, e9021 and e750 are suppressed as a MISRA exception justified
+because the MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined
+for the header files above, but not in this file, in order to generate the
+correct privileged Vs unprivileged linkage and placement. */
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE /*lint !e961 !e750 !e9021. */
+
+/* If the user has not provided application specific Rx notification macros,
+or #defined the notification macros away, them provide default implementations
+that uses task notifications. */
+/*lint -save -e9026 Function like macros allowed and needed here so they can be overidden. */
+#ifndef sbRECEIVE_COMPLETED
+	#define sbRECEIVE_COMPLETED( pxStreamBuffer )										\
+		vTaskSuspendAll();																\
+		{																				\
+			if( ( pxStreamBuffer )->xTaskWaitingToSend != NULL )						\
+			{																			\
+				( void ) xTaskNotify( ( pxStreamBuffer )->xTaskWaitingToSend,			\
+									  ( uint32_t ) 0,									\
+									  eNoAction );										\
+				( pxStreamBuffer )->xTaskWaitingToSend = NULL;							\
+			}																			\
+		}																				\
+		( void ) xTaskResumeAll();
+#endif /* sbRECEIVE_COMPLETED */
+
+#ifndef sbRECEIVE_COMPLETED_FROM_ISR
+	#define sbRECEIVE_COMPLETED_FROM_ISR( pxStreamBuffer,								\
+										  pxHigherPriorityTaskWoken )					\
+	{																					\
+	UBaseType_t uxSavedInterruptStatus;													\
+																						\
+		uxSavedInterruptStatus = ( UBaseType_t ) portSET_INTERRUPT_MASK_FROM_ISR();		\
+		{																				\
+			if( ( pxStreamBuffer )->xTaskWaitingToSend != NULL )						\
+			{																			\
+				( void ) xTaskNotifyFromISR( ( pxStreamBuffer )->xTaskWaitingToSend,	\
+											 ( uint32_t ) 0,							\
+											 eNoAction,									\
+											 pxHigherPriorityTaskWoken );				\
+				( pxStreamBuffer )->xTaskWaitingToSend = NULL;							\
+			}																			\
+		}																				\
+		portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );					\
+	}
+#endif /* sbRECEIVE_COMPLETED_FROM_ISR */
+
+/* If the user has not provided an application specific Tx notification macro,
+or #defined the notification macro away, them provide a default implementation
+that uses task notifications. */
+#ifndef sbSEND_COMPLETED
+	#define sbSEND_COMPLETED( pxStreamBuffer )											\
+		vTaskSuspendAll();																\
+		{																				\
+			if( ( pxStreamBuffer )->xTaskWaitingToReceive != NULL )						\
+			{																			\
+				( void ) xTaskNotify( ( pxStreamBuffer )->xTaskWaitingToReceive,		\
+									  ( uint32_t ) 0,									\
+									  eNoAction );										\
+				( pxStreamBuffer )->xTaskWaitingToReceive = NULL;						\
+			}																			\
+		}																				\
+		( void ) xTaskResumeAll();
+#endif /* sbSEND_COMPLETED */
+
+#ifndef sbSEND_COMPLETE_FROM_ISR
+	#define sbSEND_COMPLETE_FROM_ISR( pxStreamBuffer, pxHigherPriorityTaskWoken )		\
+	{																					\
+	UBaseType_t uxSavedInterruptStatus;													\
+																						\
+		uxSavedInterruptStatus = ( UBaseType_t ) portSET_INTERRUPT_MASK_FROM_ISR();		\
+		{																				\
+			if( ( pxStreamBuffer )->xTaskWaitingToReceive != NULL )						\
+			{																			\
+				( void ) xTaskNotifyFromISR( ( pxStreamBuffer )->xTaskWaitingToReceive,	\
+											 ( uint32_t ) 0,							\
+											 eNoAction,									\
+											 pxHigherPriorityTaskWoken );				\
+				( pxStreamBuffer )->xTaskWaitingToReceive = NULL;						\
+			}																			\
+		}																				\
+		portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );					\
+	}
+#endif /* sbSEND_COMPLETE_FROM_ISR */
+/*lint -restore (9026) */
+
+/* The number of bytes used to hold the length of a message in the buffer. */
+#define sbBYTES_TO_STORE_MESSAGE_LENGTH ( sizeof( configMESSAGE_BUFFER_LENGTH_TYPE ) )
+
+/* Bits stored in the ucFlags field of the stream buffer. */
+#define sbFLAGS_IS_MESSAGE_BUFFER		( ( uint8_t ) 1 ) /* Set if the stream buffer was created as a message buffer, in which case it holds discrete messages rather than a stream. */
+#define sbFLAGS_IS_STATICALLY_ALLOCATED ( ( uint8_t ) 2 ) /* Set if the stream buffer was created using statically allocated memory. */
+
+/*-----------------------------------------------------------*/
+
+/* Structure that hold state information on the buffer. */
+typedef struct StreamBufferDef_t /*lint !e9058 Style convention uses tag. */
+{
+	volatile size_t xTail;				/* Index to the next item to read within the buffer. */
+	volatile size_t xHead;				/* Index to the next item to write within the buffer. */
+	size_t xLength;						/* The length of the buffer pointed to by pucBuffer. */
+	size_t xTriggerLevelBytes;			/* The number of bytes that must be in the stream buffer before a task that is waiting for data is unblocked. */
+	volatile TaskHandle_t xTaskWaitingToReceive; /* Holds the handle of a task waiting for data, or NULL if no tasks are waiting. */
+	volatile TaskHandle_t xTaskWaitingToSend;	/* Holds the handle of a task waiting to send data to a message buffer that is full. */
+	uint8_t *pucBuffer;					/* Points to the buffer itself - that is - the RAM that stores the data passed through the buffer. */
+	uint8_t ucFlags;
+
+	#if ( configUSE_TRACE_FACILITY == 1 )
+		UBaseType_t uxStreamBufferNumber;		/* Used for tracing purposes. */
+	#endif
+} StreamBuffer_t;
+
+/*
+ * The number of bytes available to be read from the buffer.
+ */
+static size_t prvBytesInBuffer( const StreamBuffer_t * const pxStreamBuffer ) PRIVILEGED_FUNCTION;
+
+/*
+ * Add xCount bytes from pucData into the pxStreamBuffer message buffer.
+ * Returns the number of bytes written, which will either equal xCount in the
+ * success case, or 0 if there was not enough space in the buffer (in which case
+ * no data is written into the buffer).
+ */
+static size_t prvWriteBytesToBuffer( StreamBuffer_t * const pxStreamBuffer, const uint8_t *pucData, size_t xCount ) PRIVILEGED_FUNCTION;
+
+/*
+ * If the stream buffer is being used as a message buffer, then reads an entire
+ * message out of the buffer.  If the stream buffer is being used as a stream
+ * buffer then read as many bytes as possible from the buffer.
+ * prvReadBytesFromBuffer() is called to actually extract the bytes from the
+ * buffer's data storage area.
+ */
+static size_t prvReadMessageFromBuffer( StreamBuffer_t *pxStreamBuffer,
+										void *pvRxData,
+										size_t xBufferLengthBytes,
+										size_t xBytesAvailable,
+										size_t xBytesToStoreMessageLength ) PRIVILEGED_FUNCTION;
+
+/*
+ * If the stream buffer is being used as a message buffer, then writes an entire
+ * message to the buffer.  If the stream buffer is being used as a stream
+ * buffer then write as many bytes as possible to the buffer.
+ * prvWriteBytestoBuffer() is called to actually send the bytes to the buffer's
+ * data storage area.
+ */
+static size_t prvWriteMessageToBuffer(  StreamBuffer_t * const pxStreamBuffer,
+										const void * pvTxData,
+										size_t xDataLengthBytes,
+										size_t xSpace,
+										size_t xRequiredSpace ) PRIVILEGED_FUNCTION;
+
+/*
+ * Read xMaxCount bytes from the pxStreamBuffer message buffer and write them
+ * to pucData.
+ */
+static size_t prvReadBytesFromBuffer( StreamBuffer_t *pxStreamBuffer,
+									  uint8_t *pucData,
+									  size_t xMaxCount,
+									  size_t xBytesAvailable ) PRIVILEGED_FUNCTION;
+
+/*
+ * Called by both pxStreamBufferCreate() and pxStreamBufferCreateStatic() to
+ * initialise the members of the newly created stream buffer structure.
+ */
+static void prvInitialiseNewStreamBuffer( StreamBuffer_t * const pxStreamBuffer,
+										  uint8_t * const pucBuffer,
+										  size_t xBufferSizeBytes,
+										  size_t xTriggerLevelBytes,
+										  uint8_t ucFlags ) PRIVILEGED_FUNCTION;
+
+/*-----------------------------------------------------------*/
+
+#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+
+	StreamBufferHandle_t xStreamBufferGenericCreate( size_t xBufferSizeBytes, size_t xTriggerLevelBytes, BaseType_t xIsMessageBuffer )
+	{
+	uint8_t *pucAllocatedMemory;
+	uint8_t ucFlags;
+
+		/* In case the stream buffer is going to be used as a message buffer
+		(that is, it will hold discrete messages with a little meta data that
+		says how big the next message is) check the buffer will be large enough
+		to hold at least one message. */
+		if( xIsMessageBuffer == pdTRUE )
+		{
+			/* Is a message buffer but not statically allocated. */
+			ucFlags = sbFLAGS_IS_MESSAGE_BUFFER;
+			configASSERT( xBufferSizeBytes > sbBYTES_TO_STORE_MESSAGE_LENGTH );
+		}
+		else
+		{
+			/* Not a message buffer and not statically allocated. */
+			ucFlags = 0;
+			configASSERT( xBufferSizeBytes > 0 );
+		}
+		configASSERT( xTriggerLevelBytes <= xBufferSizeBytes );
+
+		/* A trigger level of 0 would cause a waiting task to unblock even when
+		the buffer was empty. */
+		if( xTriggerLevelBytes == ( size_t ) 0 )
+		{
+			xTriggerLevelBytes = ( size_t ) 1;
+		}
+
+		/* A stream buffer requires a StreamBuffer_t structure and a buffer.
+		Both are allocated in a single call to pvPortMalloc().  The
+		StreamBuffer_t structure is placed at the start of the allocated memory
+		and the buffer follows immediately after.  The requested size is
+		incremented so the free space is returned as the user would expect -
+		this is a quirk of the implementation that means otherwise the free
+		space would be reported as one byte smaller than would be logically
+		expected. */
+		xBufferSizeBytes++;
+		pucAllocatedMemory = ( uint8_t * ) pvPortMalloc( xBufferSizeBytes + sizeof( StreamBuffer_t ) ); /*lint !e9079 malloc() only returns void*. */
+
+		if( pucAllocatedMemory != NULL )
+		{
+			prvInitialiseNewStreamBuffer( ( StreamBuffer_t * ) pucAllocatedMemory, /* Structure at the start of the allocated memory. */ /*lint !e9087 Safe cast as allocated memory is aligned. */ /*lint !e826 Area is not too small and alignment is guaranteed provided malloc() behaves as expected and returns aligned buffer. */
+										   pucAllocatedMemory + sizeof( StreamBuffer_t ),  /* Storage area follows. */ /*lint !e9016 Indexing past structure valid for uint8_t pointer, also storage area has no alignment requirement. */
+										   xBufferSizeBytes,
+										   xTriggerLevelBytes,
+										   ucFlags );
+
+			traceSTREAM_BUFFER_CREATE( ( ( StreamBuffer_t * ) pucAllocatedMemory ), xIsMessageBuffer );
+		}
+		else
+		{
+			traceSTREAM_BUFFER_CREATE_FAILED( xIsMessageBuffer );
+		}
+
+		return ( StreamBufferHandle_t ) pucAllocatedMemory; /*lint !e9087 !e826 Safe cast as allocated memory is aligned. */
+	}
+
+#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
+/*-----------------------------------------------------------*/
+
+#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+
+	StreamBufferHandle_t xStreamBufferGenericCreateStatic( size_t xBufferSizeBytes,
+														   size_t xTriggerLevelBytes,
+														   BaseType_t xIsMessageBuffer,
+														   uint8_t * const pucStreamBufferStorageArea,
+														   StaticStreamBuffer_t * const pxStaticStreamBuffer )
+	{
+	StreamBuffer_t * const pxStreamBuffer = ( StreamBuffer_t * ) pxStaticStreamBuffer; /*lint !e740 !e9087 Safe cast as StaticStreamBuffer_t is opaque Streambuffer_t. */
+	StreamBufferHandle_t xReturn;
+	uint8_t ucFlags;
+
+		configASSERT( pucStreamBufferStorageArea );
+		configASSERT( pxStaticStreamBuffer );
+		configASSERT( xTriggerLevelBytes <= xBufferSizeBytes );
+
+		/* A trigger level of 0 would cause a waiting task to unblock even when
+		the buffer was empty. */
+		if( xTriggerLevelBytes == ( size_t ) 0 )
+		{
+			xTriggerLevelBytes = ( size_t ) 1;
+		}
+
+		if( xIsMessageBuffer != pdFALSE )
+		{
+			/* Statically allocated message buffer. */
+			ucFlags = sbFLAGS_IS_MESSAGE_BUFFER | sbFLAGS_IS_STATICALLY_ALLOCATED;
+		}
+		else
+		{
+			/* Statically allocated stream buffer. */
+			ucFlags = sbFLAGS_IS_STATICALLY_ALLOCATED;
+		}
+
+		/* In case the stream buffer is going to be used as a message buffer
+		(that is, it will hold discrete messages with a little meta data that
+		says how big the next message is) check the buffer will be large enough
+		to hold at least one message. */
+		configASSERT( xBufferSizeBytes > sbBYTES_TO_STORE_MESSAGE_LENGTH );
+
+		#if( configASSERT_DEFINED == 1 )
+		{
+			/* Sanity check that the size of the structure used to declare a
+			variable of type StaticStreamBuffer_t equals the size of the real
+			message buffer structure. */
+			volatile size_t xSize = sizeof( StaticStreamBuffer_t );
+			configASSERT( xSize == sizeof( StreamBuffer_t ) );
+		} /*lint !e529 xSize is referenced is configASSERT() is defined. */
+		#endif /* configASSERT_DEFINED */
+
+		if( ( pucStreamBufferStorageArea != NULL ) && ( pxStaticStreamBuffer != NULL ) )
+		{
+			prvInitialiseNewStreamBuffer( pxStreamBuffer,
+										  pucStreamBufferStorageArea,
+										  xBufferSizeBytes,
+										  xTriggerLevelBytes,
+										  ucFlags );
+
+			/* Remember this was statically allocated in case it is ever deleted
+			again. */
+			pxStreamBuffer->ucFlags |= sbFLAGS_IS_STATICALLY_ALLOCATED;
+
+			traceSTREAM_BUFFER_CREATE( pxStreamBuffer, xIsMessageBuffer );
+
+			xReturn = ( StreamBufferHandle_t ) pxStaticStreamBuffer; /*lint !e9087 Data hiding requires cast to opaque type. */
+		}
+		else
+		{
+			xReturn = NULL;
+			traceSTREAM_BUFFER_CREATE_STATIC_FAILED( xReturn, xIsMessageBuffer );
+		}
+
+		return xReturn;
+	}
+
+#endif /* ( configSUPPORT_STATIC_ALLOCATION == 1 ) */
+/*-----------------------------------------------------------*/
+
+void vStreamBufferDelete( StreamBufferHandle_t xStreamBuffer )
+{
+StreamBuffer_t * pxStreamBuffer = xStreamBuffer;
+
+	configASSERT( pxStreamBuffer );
+
+	traceSTREAM_BUFFER_DELETE( xStreamBuffer );
+
+	if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_STATICALLY_ALLOCATED ) == ( uint8_t ) pdFALSE )
+	{
+		#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+		{
+			/* Both the structure and the buffer were allocated using a single call
+			to pvPortMalloc(), hence only one call to vPortFree() is required. */
+			vPortFree( ( void * ) pxStreamBuffer ); /*lint !e9087 Standard free() semantics require void *, plus pxStreamBuffer was allocated by pvPortMalloc(). */
+		}
+		#else
+		{
+			/* Should not be possible to get here, ucFlags must be corrupt.
+			Force an assert. */
+			configASSERT( xStreamBuffer == ( StreamBufferHandle_t ) ~0 );
+		}
+		#endif
+	}
+	else
+	{
+		/* The structure and buffer were not allocated dynamically and cannot be
+		freed - just scrub the structure so future use will assert. */
+		( void ) memset( pxStreamBuffer, 0x00, sizeof( StreamBuffer_t ) );
+	}
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xStreamBufferReset( StreamBufferHandle_t xStreamBuffer )
+{
+StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
+BaseType_t xReturn = pdFAIL;
+
+#if( configUSE_TRACE_FACILITY == 1 )
+	UBaseType_t uxStreamBufferNumber;
+#endif
+
+	configASSERT( pxStreamBuffer );
+
+	#if( configUSE_TRACE_FACILITY == 1 )
+	{
+		/* Store the stream buffer number so it can be restored after the
+		reset. */
+		uxStreamBufferNumber = pxStreamBuffer->uxStreamBufferNumber;
+	}
+	#endif
+
+	/* Can only reset a message buffer if there are no tasks blocked on it. */
+	taskENTER_CRITICAL();
+	{
+		if( pxStreamBuffer->xTaskWaitingToReceive == NULL )
+		{
+			if( pxStreamBuffer->xTaskWaitingToSend == NULL )
+			{
+				prvInitialiseNewStreamBuffer( pxStreamBuffer,
+											  pxStreamBuffer->pucBuffer,
+											  pxStreamBuffer->xLength,
+											  pxStreamBuffer->xTriggerLevelBytes,
+											  pxStreamBuffer->ucFlags );
+				xReturn = pdPASS;
+
+				#if( configUSE_TRACE_FACILITY == 1 )
+				{
+					pxStreamBuffer->uxStreamBufferNumber = uxStreamBufferNumber;
+				}
+				#endif
+
+				traceSTREAM_BUFFER_RESET( xStreamBuffer );
+			}
+		}
+	}
+	taskEXIT_CRITICAL();
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer, size_t xTriggerLevel )
+{
+StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
+BaseType_t xReturn;
+
+	configASSERT( pxStreamBuffer );
+
+	/* It is not valid for the trigger level to be 0. */
+	if( xTriggerLevel == ( size_t ) 0 )
+	{
+		xTriggerLevel = ( size_t ) 1;
+	}
+
+	/* The trigger level is the number of bytes that must be in the stream
+	buffer before a task that is waiting for data is unblocked. */
+	if( xTriggerLevel <= pxStreamBuffer->xLength )
+	{
+		pxStreamBuffer->xTriggerLevelBytes = xTriggerLevel;
+		xReturn = pdPASS;
+	}
+	else
+	{
+		xReturn = pdFALSE;
+	}
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+size_t xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer )
+{
+const StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
+size_t xSpace;
+
+	configASSERT( pxStreamBuffer );
+
+	xSpace = pxStreamBuffer->xLength + pxStreamBuffer->xTail;
+	xSpace -= pxStreamBuffer->xHead;
+	xSpace -= ( size_t ) 1;
+
+	if( xSpace >= pxStreamBuffer->xLength )
+	{
+		xSpace -= pxStreamBuffer->xLength;
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	return xSpace;
+}
+/*-----------------------------------------------------------*/
+
+size_t xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer )
+{
+const StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
+size_t xReturn;
+
+	configASSERT( pxStreamBuffer );
+
+	xReturn = prvBytesInBuffer( pxStreamBuffer );
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+size_t xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
+						  const void *pvTxData,
+						  size_t xDataLengthBytes,
+						  TickType_t xTicksToWait )
+{
+StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
+size_t xReturn, xSpace = 0;
+size_t xRequiredSpace = xDataLengthBytes;
+TimeOut_t xTimeOut;
+
+	configASSERT( pvTxData );
+	configASSERT( pxStreamBuffer );
+
+	/* This send function is used to write to both message buffers and stream
+	buffers.  If this is a message buffer then the space needed must be
+	increased by the amount of bytes needed to store the length of the
+	message. */
+	if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) != ( uint8_t ) 0 )
+	{
+		xRequiredSpace += sbBYTES_TO_STORE_MESSAGE_LENGTH;
+
+		/* Overflow? */
+		configASSERT( xRequiredSpace > xDataLengthBytes );
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	if( xTicksToWait != ( TickType_t ) 0 )
+	{
+		vTaskSetTimeOutState( &xTimeOut );
+
+		do
+		{
+			/* Wait until the required number of bytes are free in the message
+			buffer. */
+			taskENTER_CRITICAL();
+			{
+				xSpace = xStreamBufferSpacesAvailable( pxStreamBuffer );
+
+				if( xSpace < xRequiredSpace )
+				{
+					/* Clear notification state as going to wait for space. */
+					( void ) xTaskNotifyStateClear( NULL );
+
+					/* Should only be one writer. */
+					configASSERT( pxStreamBuffer->xTaskWaitingToSend == NULL );
+					pxStreamBuffer->xTaskWaitingToSend = xTaskGetCurrentTaskHandle();
+				}
+				else
+				{
+					taskEXIT_CRITICAL();
+					break;
+				}
+			}
+			taskEXIT_CRITICAL();
+
+			traceBLOCKING_ON_STREAM_BUFFER_SEND( xStreamBuffer );
+			( void ) xTaskNotifyWait( ( uint32_t ) 0, ( uint32_t ) 0, NULL, xTicksToWait );
+			pxStreamBuffer->xTaskWaitingToSend = NULL;
+
+		} while( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE );
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	if( xSpace == ( size_t ) 0 )
+	{
+		xSpace = xStreamBufferSpacesAvailable( pxStreamBuffer );
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	xReturn = prvWriteMessageToBuffer( pxStreamBuffer, pvTxData, xDataLengthBytes, xSpace, xRequiredSpace );
+
+	if( xReturn > ( size_t ) 0 )
+	{
+		traceSTREAM_BUFFER_SEND( xStreamBuffer, xReturn );
+
+		/* Was a task waiting for the data? */
+		if( prvBytesInBuffer( pxStreamBuffer ) >= pxStreamBuffer->xTriggerLevelBytes )
+		{
+			sbSEND_COMPLETED( pxStreamBuffer );
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+		traceSTREAM_BUFFER_SEND_FAILED( xStreamBuffer );
+	}
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+size_t xStreamBufferSendFromISR( StreamBufferHandle_t xStreamBuffer,
+								 const void *pvTxData,
+								 size_t xDataLengthBytes,
+								 BaseType_t * const pxHigherPriorityTaskWoken )
+{
+StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
+size_t xReturn, xSpace;
+size_t xRequiredSpace = xDataLengthBytes;
+
+	configASSERT( pvTxData );
+	configASSERT( pxStreamBuffer );
+
+	/* This send function is used to write to both message buffers and stream
+	buffers.  If this is a message buffer then the space needed must be
+	increased by the amount of bytes needed to store the length of the
+	message. */
+	if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) != ( uint8_t ) 0 )
+	{
+		xRequiredSpace += sbBYTES_TO_STORE_MESSAGE_LENGTH;
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	xSpace = xStreamBufferSpacesAvailable( pxStreamBuffer );
+	xReturn = prvWriteMessageToBuffer( pxStreamBuffer, pvTxData, xDataLengthBytes, xSpace, xRequiredSpace );
+
+	if( xReturn > ( size_t ) 0 )
+	{
+		/* Was a task waiting for the data? */
+		if( prvBytesInBuffer( pxStreamBuffer ) >= pxStreamBuffer->xTriggerLevelBytes )
+		{
+			sbSEND_COMPLETE_FROM_ISR( pxStreamBuffer, pxHigherPriorityTaskWoken );
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	traceSTREAM_BUFFER_SEND_FROM_ISR( xStreamBuffer, xReturn );
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+static size_t prvWriteMessageToBuffer( StreamBuffer_t * const pxStreamBuffer,
+									   const void * pvTxData,
+									   size_t xDataLengthBytes,
+									   size_t xSpace,
+									   size_t xRequiredSpace )
+{
+	BaseType_t xShouldWrite;
+	size_t xReturn;
+
+	if( xSpace == ( size_t ) 0 )
+	{
+		/* Doesn't matter if this is a stream buffer or a message buffer, there
+		is no space to write. */
+		xShouldWrite = pdFALSE;
+	}
+	else if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) == ( uint8_t ) 0 )
+	{
+		/* This is a stream buffer, as opposed to a message buffer, so writing a
+		stream of bytes rather than discrete messages.  Write as many bytes as
+		possible. */
+		xShouldWrite = pdTRUE;
+		xDataLengthBytes = configMIN( xDataLengthBytes, xSpace );
+	}
+	else if( xSpace >= xRequiredSpace )
+	{
+		/* This is a message buffer, as opposed to a stream buffer, and there
+		is enough space to write both the message length and the message itself
+		into the buffer.  Start by writing the length of the data, the data
+		itself will be written later in this function. */
+		xShouldWrite = pdTRUE;
+		( void ) prvWriteBytesToBuffer( pxStreamBuffer, ( const uint8_t * ) &( xDataLengthBytes ), sbBYTES_TO_STORE_MESSAGE_LENGTH );
+	}
+	else
+	{
+		/* There is space available, but not enough space. */
+		xShouldWrite = pdFALSE;
+	}
+
+	if( xShouldWrite != pdFALSE )
+	{
+		/* Writes the data itself. */
+		xReturn = prvWriteBytesToBuffer( pxStreamBuffer, ( const uint8_t * ) pvTxData, xDataLengthBytes ); /*lint !e9079 Storage buffer is implemented as uint8_t for ease of sizing, alighment and access. */
+	}
+	else
+	{
+		xReturn = 0;
+	}
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+size_t xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
+							 void *pvRxData,
+							 size_t xBufferLengthBytes,
+							 TickType_t xTicksToWait )
+{
+StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
+size_t xReceivedLength = 0, xBytesAvailable, xBytesToStoreMessageLength;
+
+	configASSERT( pvRxData );
+	configASSERT( pxStreamBuffer );
+
+	/* This receive function is used by both message buffers, which store
+	discrete messages, and stream buffers, which store a continuous stream of
+	bytes.  Discrete messages include an additional
+	sbBYTES_TO_STORE_MESSAGE_LENGTH bytes that hold the length of the
+	message. */
+	if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) != ( uint8_t ) 0 )
+	{
+		xBytesToStoreMessageLength = sbBYTES_TO_STORE_MESSAGE_LENGTH;
+	}
+	else
+	{
+		xBytesToStoreMessageLength = 0;
+	}
+
+	if( xTicksToWait != ( TickType_t ) 0 )
+	{
+		/* Checking if there is data and clearing the notification state must be
+		performed atomically. */
+		taskENTER_CRITICAL();
+		{
+			xBytesAvailable = prvBytesInBuffer( pxStreamBuffer );
+
+			/* If this function was invoked by a message buffer read then
+			xBytesToStoreMessageLength holds the number of bytes used to hold
+			the length of the next discrete message.  If this function was
+			invoked by a stream buffer read then xBytesToStoreMessageLength will
+			be 0. */
+			if( xBytesAvailable <= xBytesToStoreMessageLength )
+			{
+				/* Clear notification state as going to wait for data. */
+				( void ) xTaskNotifyStateClear( NULL );
+
+				/* Should only be one reader. */
+				configASSERT( pxStreamBuffer->xTaskWaitingToReceive == NULL );
+				pxStreamBuffer->xTaskWaitingToReceive = xTaskGetCurrentTaskHandle();
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		taskEXIT_CRITICAL();
+
+		if( xBytesAvailable <= xBytesToStoreMessageLength )
+		{
+			/* Wait for data to be available. */
+			traceBLOCKING_ON_STREAM_BUFFER_RECEIVE( xStreamBuffer );
+			( void ) xTaskNotifyWait( ( uint32_t ) 0, ( uint32_t ) 0, NULL, xTicksToWait );
+			pxStreamBuffer->xTaskWaitingToReceive = NULL;
+
+			/* Recheck the data available after blocking. */
+			xBytesAvailable = prvBytesInBuffer( pxStreamBuffer );
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+	else
+	{
+		xBytesAvailable = prvBytesInBuffer( pxStreamBuffer );
+	}
+
+	/* Whether receiving a discrete message (where xBytesToStoreMessageLength
+	holds the number of bytes used to store the message length) or a stream of
+	bytes (where xBytesToStoreMessageLength is zero), the number of bytes
+	available must be greater than xBytesToStoreMessageLength to be able to
+	read bytes from the buffer. */
+	if( xBytesAvailable > xBytesToStoreMessageLength )
+	{
+		xReceivedLength = prvReadMessageFromBuffer( pxStreamBuffer, pvRxData, xBufferLengthBytes, xBytesAvailable, xBytesToStoreMessageLength );
+
+		/* Was a task waiting for space in the buffer? */
+		if( xReceivedLength != ( size_t ) 0 )
+		{
+			traceSTREAM_BUFFER_RECEIVE( xStreamBuffer, xReceivedLength );
+			sbRECEIVE_COMPLETED( pxStreamBuffer );
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+	else
+	{
+		traceSTREAM_BUFFER_RECEIVE_FAILED( xStreamBuffer );
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	return xReceivedLength;
+}
+/*-----------------------------------------------------------*/
+
+size_t xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer )
+{
+StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
+size_t xReturn, xBytesAvailable, xOriginalTail;
+configMESSAGE_BUFFER_LENGTH_TYPE xTempReturn;
+
+	configASSERT( pxStreamBuffer );
+
+	/* Ensure the stream buffer is being used as a message buffer. */
+	if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) != ( uint8_t ) 0 )
+	{
+		xBytesAvailable = prvBytesInBuffer( pxStreamBuffer );
+		if( xBytesAvailable > sbBYTES_TO_STORE_MESSAGE_LENGTH )
+		{
+			/* The number of bytes available is greater than the number of bytes
+			required to hold the length of the next message, so another message
+			is available.  Return its length without removing the length bytes
+			from the buffer.  A copy of the tail is stored so the buffer can be
+			returned to its prior state as the message is not actually being
+			removed from the buffer. */
+			xOriginalTail = pxStreamBuffer->xTail;
+			( void ) prvReadBytesFromBuffer( pxStreamBuffer, ( uint8_t * ) &xTempReturn, sbBYTES_TO_STORE_MESSAGE_LENGTH, xBytesAvailable );
+			xReturn = ( size_t ) xTempReturn;
+			pxStreamBuffer->xTail = xOriginalTail;
+		}
+		else
+		{
+			/* The minimum amount of bytes in a message buffer is
+			( sbBYTES_TO_STORE_MESSAGE_LENGTH + 1 ), so if xBytesAvailable is
+			less than sbBYTES_TO_STORE_MESSAGE_LENGTH the only other valid
+			value is 0. */
+			configASSERT( xBytesAvailable == 0 );
+			xReturn = 0;
+		}
+	}
+	else
+	{
+		xReturn = 0;
+	}
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+size_t xStreamBufferReceiveFromISR( StreamBufferHandle_t xStreamBuffer,
+									void *pvRxData,
+									size_t xBufferLengthBytes,
+									BaseType_t * const pxHigherPriorityTaskWoken )
+{
+StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
+size_t xReceivedLength = 0, xBytesAvailable, xBytesToStoreMessageLength;
+
+	configASSERT( pvRxData );
+	configASSERT( pxStreamBuffer );
+
+	/* This receive function is used by both message buffers, which store
+	discrete messages, and stream buffers, which store a continuous stream of
+	bytes.  Discrete messages include an additional
+	sbBYTES_TO_STORE_MESSAGE_LENGTH bytes that hold the length of the
+	message. */
+	if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) != ( uint8_t ) 0 )
+	{
+		xBytesToStoreMessageLength = sbBYTES_TO_STORE_MESSAGE_LENGTH;
+	}
+	else
+	{
+		xBytesToStoreMessageLength = 0;
+	}
+
+	xBytesAvailable = prvBytesInBuffer( pxStreamBuffer );
+
+	/* Whether receiving a discrete message (where xBytesToStoreMessageLength
+	holds the number of bytes used to store the message length) or a stream of
+	bytes (where xBytesToStoreMessageLength is zero), the number of bytes
+	available must be greater than xBytesToStoreMessageLength to be able to
+	read bytes from the buffer. */
+	if( xBytesAvailable > xBytesToStoreMessageLength )
+	{
+		xReceivedLength = prvReadMessageFromBuffer( pxStreamBuffer, pvRxData, xBufferLengthBytes, xBytesAvailable, xBytesToStoreMessageLength );
+
+		/* Was a task waiting for space in the buffer? */
+		if( xReceivedLength != ( size_t ) 0 )
+		{
+			sbRECEIVE_COMPLETED_FROM_ISR( pxStreamBuffer, pxHigherPriorityTaskWoken );
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	traceSTREAM_BUFFER_RECEIVE_FROM_ISR( xStreamBuffer, xReceivedLength );
+
+	return xReceivedLength;
+}
+/*-----------------------------------------------------------*/
+
+static size_t prvReadMessageFromBuffer( StreamBuffer_t *pxStreamBuffer,
+										void *pvRxData,
+										size_t xBufferLengthBytes,
+										size_t xBytesAvailable,
+										size_t xBytesToStoreMessageLength )
+{
+size_t xOriginalTail, xReceivedLength, xNextMessageLength;
+configMESSAGE_BUFFER_LENGTH_TYPE xTempNextMessageLength;
+
+	if( xBytesToStoreMessageLength != ( size_t ) 0 )
+	{
+		/* A discrete message is being received.  First receive the length
+		of the message.  A copy of the tail is stored so the buffer can be
+		returned to its prior state if the length of the message is too
+		large for the provided buffer. */
+		xOriginalTail = pxStreamBuffer->xTail;
+		( void ) prvReadBytesFromBuffer( pxStreamBuffer, ( uint8_t * ) &xTempNextMessageLength, xBytesToStoreMessageLength, xBytesAvailable );
+		xNextMessageLength = ( size_t ) xTempNextMessageLength;
+
+		/* Reduce the number of bytes available by the number of bytes just
+		read out. */
+		xBytesAvailable -= xBytesToStoreMessageLength;
+
+		/* Check there is enough space in the buffer provided by the
+		user. */
+		if( xNextMessageLength > xBufferLengthBytes )
+		{
+			/* The user has provided insufficient space to read the message
+			so return the buffer to its previous state (so the length of
+			the message is in the buffer again). */
+			pxStreamBuffer->xTail = xOriginalTail;
+			xNextMessageLength = 0;
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+	else
+	{
+		/* A stream of bytes is being received (as opposed to a discrete
+		message), so read as many bytes as possible. */
+		xNextMessageLength = xBufferLengthBytes;
+	}
+
+	/* Read the actual data. */
+	xReceivedLength = prvReadBytesFromBuffer( pxStreamBuffer, ( uint8_t * ) pvRxData, xNextMessageLength, xBytesAvailable ); /*lint !e9079 Data storage area is implemented as uint8_t array for ease of sizing, indexing and alignment. */
+
+	return xReceivedLength;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer )
+{
+const StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
+BaseType_t xReturn;
+size_t xTail;
+
+	configASSERT( pxStreamBuffer );
+
+	/* True if no bytes are available. */
+	xTail = pxStreamBuffer->xTail;
+	if( pxStreamBuffer->xHead == xTail )
+	{
+		xReturn = pdTRUE;
+	}
+	else
+	{
+		xReturn = pdFALSE;
+	}
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer )
+{
+BaseType_t xReturn;
+size_t xBytesToStoreMessageLength;
+const StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
+
+	configASSERT( pxStreamBuffer );
+
+	/* This generic version of the receive function is used by both message
+	buffers, which store discrete messages, and stream buffers, which store a
+	continuous stream of bytes.  Discrete messages include an additional
+	sbBYTES_TO_STORE_MESSAGE_LENGTH bytes that hold the length of the message. */
+	if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) != ( uint8_t ) 0 )
+	{
+		xBytesToStoreMessageLength = sbBYTES_TO_STORE_MESSAGE_LENGTH;
+	}
+	else
+	{
+		xBytesToStoreMessageLength = 0;
+	}
+
+	/* True if the available space equals zero. */
+	if( xStreamBufferSpacesAvailable( xStreamBuffer ) <= xBytesToStoreMessageLength )
+	{
+		xReturn = pdTRUE;
+	}
+	else
+	{
+		xReturn = pdFALSE;
+	}
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xStreamBufferSendCompletedFromISR( StreamBufferHandle_t xStreamBuffer, BaseType_t *pxHigherPriorityTaskWoken )
+{
+StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
+BaseType_t xReturn;
+UBaseType_t uxSavedInterruptStatus;
+
+	configASSERT( pxStreamBuffer );
+
+	uxSavedInterruptStatus = ( UBaseType_t ) portSET_INTERRUPT_MASK_FROM_ISR();
+	{
+		if( ( pxStreamBuffer )->xTaskWaitingToReceive != NULL )
+		{
+			( void ) xTaskNotifyFromISR( ( pxStreamBuffer )->xTaskWaitingToReceive,
+										 ( uint32_t ) 0,
+										 eNoAction,
+										 pxHigherPriorityTaskWoken );
+			( pxStreamBuffer )->xTaskWaitingToReceive = NULL;
+			xReturn = pdTRUE;
+		}
+		else
+		{
+			xReturn = pdFALSE;
+		}
+	}
+	portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xStreamBufferReceiveCompletedFromISR( StreamBufferHandle_t xStreamBuffer, BaseType_t *pxHigherPriorityTaskWoken )
+{
+StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
+BaseType_t xReturn;
+UBaseType_t uxSavedInterruptStatus;
+
+	configASSERT( pxStreamBuffer );
+
+	uxSavedInterruptStatus = ( UBaseType_t ) portSET_INTERRUPT_MASK_FROM_ISR();
+	{
+		if( ( pxStreamBuffer )->xTaskWaitingToSend != NULL )
+		{
+			( void ) xTaskNotifyFromISR( ( pxStreamBuffer )->xTaskWaitingToSend,
+										 ( uint32_t ) 0,
+										 eNoAction,
+										 pxHigherPriorityTaskWoken );
+			( pxStreamBuffer )->xTaskWaitingToSend = NULL;
+			xReturn = pdTRUE;
+		}
+		else
+		{
+			xReturn = pdFALSE;
+		}
+	}
+	portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+static size_t prvWriteBytesToBuffer( StreamBuffer_t * const pxStreamBuffer, const uint8_t *pucData, size_t xCount )
+{
+size_t xNextHead, xFirstLength;
+
+	configASSERT( xCount > ( size_t ) 0 );
+
+	xNextHead = pxStreamBuffer->xHead;
+
+	/* Calculate the number of bytes that can be added in the first write -
+	which may be less than the total number of bytes that need to be added if
+	the buffer will wrap back to the beginning. */
+	xFirstLength = configMIN( pxStreamBuffer->xLength - xNextHead, xCount );
+
+	/* Write as many bytes as can be written in the first write. */
+	configASSERT( ( xNextHead + xFirstLength ) <= pxStreamBuffer->xLength );
+	( void ) memcpy( ( void* ) ( &( pxStreamBuffer->pucBuffer[ xNextHead ] ) ), ( const void * ) pucData, xFirstLength ); /*lint !e9087 memcpy() requires void *. */
+
+	/* If the number of bytes written was less than the number that could be
+	written in the first write... */
+	if( xCount > xFirstLength )
+	{
+		/* ...then write the remaining bytes to the start of the buffer. */
+		configASSERT( ( xCount - xFirstLength ) <= pxStreamBuffer->xLength );
+		( void ) memcpy( ( void * ) pxStreamBuffer->pucBuffer, ( const void * ) &( pucData[ xFirstLength ] ), xCount - xFirstLength ); /*lint !e9087 memcpy() requires void *. */
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	xNextHead += xCount;
+	if( xNextHead >= pxStreamBuffer->xLength )
+	{
+		xNextHead -= pxStreamBuffer->xLength;
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	pxStreamBuffer->xHead = xNextHead;
+
+	return xCount;
+}
+/*-----------------------------------------------------------*/
+
+static size_t prvReadBytesFromBuffer( StreamBuffer_t *pxStreamBuffer, uint8_t *pucData, size_t xMaxCount, size_t xBytesAvailable )
+{
+size_t xCount, xFirstLength, xNextTail;
+
+	/* Use the minimum of the wanted bytes and the available bytes. */
+	xCount = configMIN( xBytesAvailable, xMaxCount );
+
+	if( xCount > ( size_t ) 0 )
+	{
+		xNextTail = pxStreamBuffer->xTail;
+
+		/* Calculate the number of bytes that can be read - which may be
+		less than the number wanted if the data wraps around to the start of
+		the buffer. */
+		xFirstLength = configMIN( pxStreamBuffer->xLength - xNextTail, xCount );
+
+		/* Obtain the number of bytes it is possible to obtain in the first
+		read.  Asserts check bounds of read and write. */
+		configASSERT( xFirstLength <= xMaxCount );
+		configASSERT( ( xNextTail + xFirstLength ) <= pxStreamBuffer->xLength );
+		( void ) memcpy( ( void * ) pucData, ( const void * ) &( pxStreamBuffer->pucBuffer[ xNextTail ] ), xFirstLength ); /*lint !e9087 memcpy() requires void *. */
+
+		/* If the total number of wanted bytes is greater than the number
+		that could be read in the first read... */
+		if( xCount > xFirstLength )
+		{
+			/*...then read the remaining bytes from the start of the buffer. */
+			configASSERT( xCount <= xMaxCount );
+			( void ) memcpy( ( void * ) &( pucData[ xFirstLength ] ), ( void * ) ( pxStreamBuffer->pucBuffer ), xCount - xFirstLength ); /*lint !e9087 memcpy() requires void *. */
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+
+		/* Move the tail pointer to effectively remove the data read from
+		the buffer. */
+		xNextTail += xCount;
+
+		if( xNextTail >= pxStreamBuffer->xLength )
+		{
+			xNextTail -= pxStreamBuffer->xLength;
+		}
+
+		pxStreamBuffer->xTail = xNextTail;
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	return xCount;
+}
+/*-----------------------------------------------------------*/
+
+static size_t prvBytesInBuffer( const StreamBuffer_t * const pxStreamBuffer )
+{
+/* Returns the distance between xTail and xHead. */
+size_t xCount;
+
+	xCount = pxStreamBuffer->xLength + pxStreamBuffer->xHead;
+	xCount -= pxStreamBuffer->xTail;
+	if ( xCount >= pxStreamBuffer->xLength )
+	{
+		xCount -= pxStreamBuffer->xLength;
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	return xCount;
+}
+/*-----------------------------------------------------------*/
+
+static void prvInitialiseNewStreamBuffer( StreamBuffer_t * const pxStreamBuffer,
+										  uint8_t * const pucBuffer,
+										  size_t xBufferSizeBytes,
+										  size_t xTriggerLevelBytes,
+										  uint8_t ucFlags )
+{
+	/* Assert here is deliberately writing to the entire buffer to ensure it can
+	be written to without generating exceptions, and is setting the buffer to a
+	known value to assist in development/debugging. */
+	#if( configASSERT_DEFINED == 1 )
+	{
+		/* The value written just has to be identifiable when looking at the
+		memory.  Don't use 0xA5 as that is the stack fill value and could
+		result in confusion as to what is actually being observed. */
+		const BaseType_t xWriteValue = 0x55;
+		configASSERT( memset( pucBuffer, ( int ) xWriteValue, xBufferSizeBytes ) == pucBuffer );
+	} /*lint !e529 !e438 xWriteValue is only used if configASSERT() is defined. */
+	#endif
+
+	( void ) memset( ( void * ) pxStreamBuffer, 0x00, sizeof( StreamBuffer_t ) ); /*lint !e9087 memset() requires void *. */
+	pxStreamBuffer->pucBuffer = pucBuffer;
+	pxStreamBuffer->xLength = xBufferSizeBytes;
+	pxStreamBuffer->xTriggerLevelBytes = xTriggerLevelBytes;
+	pxStreamBuffer->ucFlags = ucFlags;
+}
+
+#if ( configUSE_TRACE_FACILITY == 1 )
+
+	UBaseType_t uxStreamBufferGetStreamBufferNumber( StreamBufferHandle_t xStreamBuffer )
+	{
+		return xStreamBuffer->uxStreamBufferNumber;
+	}
+
+#endif /* configUSE_TRACE_FACILITY */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TRACE_FACILITY == 1 )
+
+	void vStreamBufferSetStreamBufferNumber( StreamBufferHandle_t xStreamBuffer, UBaseType_t uxStreamBufferNumber )
+	{
+		xStreamBuffer->uxStreamBufferNumber = uxStreamBufferNumber;
+	}
+
+#endif /* configUSE_TRACE_FACILITY */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TRACE_FACILITY == 1 )
+
+	uint8_t ucStreamBufferGetStreamBufferType( StreamBufferHandle_t xStreamBuffer )
+	{
+		return ( xStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER );
+	}
+
+#endif /* configUSE_TRACE_FACILITY */
+/*-----------------------------------------------------------*/
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/tasks.c b/Middlewares/Third_Party/FreeRTOS/Source/tasks.c
new file mode 100644
index 0000000..f93fca0
--- /dev/null
+++ b/Middlewares/Third_Party/FreeRTOS/Source/tasks.c
@@ -0,0 +1,5310 @@
+/*
+ * FreeRTOS Kernel V10.3.1
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Standard includes. */
+#include <stdlib.h>
+#include <string.h>
+
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
+all the API functions to use the MPU wrappers.  That should only be done when
+task.h is included from an application file. */
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+/* FreeRTOS includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+#include "timers.h"
+#include "stack_macros.h"
+
+/* Lint e9021, e961 and e750 are suppressed as a MISRA exception justified
+because the MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined
+for the header files above, but not in this file, in order to generate the
+correct privileged Vs unprivileged linkage and placement. */
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE /*lint !e961 !e750 !e9021. */
+
+/* Set configUSE_STATS_FORMATTING_FUNCTIONS to 2 to include the stats formatting
+functions but without including stdio.h here. */
+#if ( configUSE_STATS_FORMATTING_FUNCTIONS == 1 )
+	/* At the bottom of this file are two optional functions that can be used
+	to generate human readable text from the raw data generated by the
+	uxTaskGetSystemState() function.  Note the formatting functions are provided
+	for convenience only, and are NOT considered part of the kernel. */
+	#include <stdio.h>
+#endif /* configUSE_STATS_FORMATTING_FUNCTIONS == 1 ) */
+
+#if( configUSE_PREEMPTION == 0 )
+	/* If the cooperative scheduler is being used then a yield should not be
+	performed just because a higher priority task has been woken. */
+	#define taskYIELD_IF_USING_PREEMPTION()
+#else
+	#define taskYIELD_IF_USING_PREEMPTION() portYIELD_WITHIN_API()
+#endif
+
+/* Values that can be assigned to the ucNotifyState member of the TCB. */
+#define taskNOT_WAITING_NOTIFICATION	( ( uint8_t ) 0 )
+#define taskWAITING_NOTIFICATION		( ( uint8_t ) 1 )
+#define taskNOTIFICATION_RECEIVED		( ( uint8_t ) 2 )
+
+/*
+ * The value used to fill the stack of a task when the task is created.  This
+ * is used purely for checking the high water mark for tasks.
+ */
+#define tskSTACK_FILL_BYTE	( 0xa5U )
+
+/* Bits used to recored how a task's stack and TCB were allocated. */
+#define tskDYNAMICALLY_ALLOCATED_STACK_AND_TCB 		( ( uint8_t ) 0 )
+#define tskSTATICALLY_ALLOCATED_STACK_ONLY 			( ( uint8_t ) 1 )
+#define tskSTATICALLY_ALLOCATED_STACK_AND_TCB		( ( uint8_t ) 2 )
+
+/* If any of the following are set then task stacks are filled with a known
+value so the high water mark can be determined.  If none of the following are
+set then don't fill the stack so there is no unnecessary dependency on memset. */
+#if( ( configCHECK_FOR_STACK_OVERFLOW > 1 ) || ( configUSE_TRACE_FACILITY == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 ) )
+	#define tskSET_NEW_STACKS_TO_KNOWN_VALUE	1
+#else
+	#define tskSET_NEW_STACKS_TO_KNOWN_VALUE	0
+#endif
+
+/*
+ * Macros used by vListTask to indicate which state a task is in.
+ */
+#define tskRUNNING_CHAR		( 'X' )
+#define tskBLOCKED_CHAR		( 'B' )
+#define tskREADY_CHAR		( 'R' )
+#define tskDELETED_CHAR		( 'D' )
+#define tskSUSPENDED_CHAR	( 'S' )
+
+/*
+ * Some kernel aware debuggers require the data the debugger needs access to be
+ * global, rather than file scope.
+ */
+#ifdef portREMOVE_STATIC_QUALIFIER
+	#define static
+#endif
+
+/* The name allocated to the Idle task.  This can be overridden by defining
+configIDLE_TASK_NAME in FreeRTOSConfig.h. */
+#ifndef configIDLE_TASK_NAME
+	#define configIDLE_TASK_NAME "IDLE"
+#endif
+
+#if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 0 )
+
+	/* If configUSE_PORT_OPTIMISED_TASK_SELECTION is 0 then task selection is
+	performed in a generic way that is not optimised to any particular
+	microcontroller architecture. */
+
+	/* uxTopReadyPriority holds the priority of the highest priority ready
+	state task. */
+	#define taskRECORD_READY_PRIORITY( uxPriority )														\
+	{																									\
+		if( ( uxPriority ) > uxTopReadyPriority )														\
+		{																								\
+			uxTopReadyPriority = ( uxPriority );														\
+		}																								\
+	} /* taskRECORD_READY_PRIORITY */
+
+	/*-----------------------------------------------------------*/
+
+	#define taskSELECT_HIGHEST_PRIORITY_TASK()															\
+	{																									\
+	UBaseType_t uxTopPriority = uxTopReadyPriority;														\
+																										\
+		/* Find the highest priority queue that contains ready tasks. */								\
+		while( listLIST_IS_EMPTY( &( pxReadyTasksLists[ uxTopPriority ] ) ) )							\
+		{																								\
+			configASSERT( uxTopPriority );																\
+			--uxTopPriority;																			\
+		}																								\
+																										\
+		/* listGET_OWNER_OF_NEXT_ENTRY indexes through the list, so the tasks of						\
+		the	same priority get an equal share of the processor time. */									\
+		listGET_OWNER_OF_NEXT_ENTRY( pxCurrentTCB, &( pxReadyTasksLists[ uxTopPriority ] ) );			\
+		uxTopReadyPriority = uxTopPriority;																\
+	} /* taskSELECT_HIGHEST_PRIORITY_TASK */
+
+	/*-----------------------------------------------------------*/
+
+	/* Define away taskRESET_READY_PRIORITY() and portRESET_READY_PRIORITY() as
+	they are only required when a port optimised method of task selection is
+	being used. */
+	#define taskRESET_READY_PRIORITY( uxPriority )
+	#define portRESET_READY_PRIORITY( uxPriority, uxTopReadyPriority )
+
+#else /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+
+	/* If configUSE_PORT_OPTIMISED_TASK_SELECTION is 1 then task selection is
+	performed in a way that is tailored to the particular microcontroller
+	architecture being used. */
+
+	/* A port optimised version is provided.  Call the port defined macros. */
+	#define taskRECORD_READY_PRIORITY( uxPriority )	portRECORD_READY_PRIORITY( uxPriority, uxTopReadyPriority )
+
+	/*-----------------------------------------------------------*/
+
+	#define taskSELECT_HIGHEST_PRIORITY_TASK()														\
+	{																								\
+	UBaseType_t uxTopPriority;																		\
+																									\
+		/* Find the highest priority list that contains ready tasks. */								\
+		portGET_HIGHEST_PRIORITY( uxTopPriority, uxTopReadyPriority );								\
+		configASSERT( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ uxTopPriority ] ) ) > 0 );		\
+		listGET_OWNER_OF_NEXT_ENTRY( pxCurrentTCB, &( pxReadyTasksLists[ uxTopPriority ] ) );		\
+	} /* taskSELECT_HIGHEST_PRIORITY_TASK() */
+
+	/*-----------------------------------------------------------*/
+
+	/* A port optimised version is provided, call it only if the TCB being reset
+	is being referenced from a ready list.  If it is referenced from a delayed
+	or suspended list then it won't be in a ready list. */
+	#define taskRESET_READY_PRIORITY( uxPriority )														\
+	{																									\
+		if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ ( uxPriority ) ] ) ) == ( UBaseType_t ) 0 )	\
+		{																								\
+			portRESET_READY_PRIORITY( ( uxPriority ), ( uxTopReadyPriority ) );							\
+		}																								\
+	}
+
+#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+
+/*-----------------------------------------------------------*/
+
+/* pxDelayedTaskList and pxOverflowDelayedTaskList are switched when the tick
+count overflows. */
+#define taskSWITCH_DELAYED_LISTS()																	\
+{																									\
+	List_t *pxTemp;																					\
+																									\
+	/* The delayed tasks list should be empty when the lists are switched. */						\
+	configASSERT( ( listLIST_IS_EMPTY( pxDelayedTaskList ) ) );										\
+																									\
+	pxTemp = pxDelayedTaskList;																		\
+	pxDelayedTaskList = pxOverflowDelayedTaskList;													\
+	pxOverflowDelayedTaskList = pxTemp;																\
+	xNumOfOverflows++;																				\
+	prvResetNextTaskUnblockTime();																	\
+}
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Place the task represented by pxTCB into the appropriate ready list for
+ * the task.  It is inserted at the end of the list.
+ */
+#define prvAddTaskToReadyList( pxTCB )																\
+	traceMOVED_TASK_TO_READY_STATE( pxTCB );														\
+	taskRECORD_READY_PRIORITY( ( pxTCB )->uxPriority );												\
+	vListInsertEnd( &( pxReadyTasksLists[ ( pxTCB )->uxPriority ] ), &( ( pxTCB )->xStateListItem ) ); \
+	tracePOST_MOVED_TASK_TO_READY_STATE( pxTCB )
+/*-----------------------------------------------------------*/
+
+/*
+ * Several functions take an TaskHandle_t parameter that can optionally be NULL,
+ * where NULL is used to indicate that the handle of the currently executing
+ * task should be used in place of the parameter.  This macro simply checks to
+ * see if the parameter is NULL and returns a pointer to the appropriate TCB.
+ */
+#define prvGetTCBFromHandle( pxHandle ) ( ( ( pxHandle ) == NULL ) ? pxCurrentTCB : ( pxHandle ) )
+
+/* The item value of the event list item is normally used to hold the priority
+of the task to which it belongs (coded to allow it to be held in reverse
+priority order).  However, it is occasionally borrowed for other purposes.  It
+is important its value is not updated due to a task priority change while it is
+being used for another purpose.  The following bit definition is used to inform
+the scheduler that the value should not be changed - in which case it is the
+responsibility of whichever module is using the value to ensure it gets set back
+to its original value when it is released. */
+#if( configUSE_16_BIT_TICKS == 1 )
+	#define taskEVENT_LIST_ITEM_VALUE_IN_USE	0x8000U
+#else
+	#define taskEVENT_LIST_ITEM_VALUE_IN_USE	0x80000000UL
+#endif
+
+/*
+ * Task control block.  A task control block (TCB) is allocated for each task,
+ * and stores task state information, including a pointer to the task's context
+ * (the task's run time environment, including register values)
+ */
+typedef struct tskTaskControlBlock 			/* The old naming convention is used to prevent breaking kernel aware debuggers. */
+{
+	volatile StackType_t	*pxTopOfStack;	/*< Points to the location of the last item placed on the tasks stack.  THIS MUST BE THE FIRST MEMBER OF THE TCB STRUCT. */
+
+	#if ( portUSING_MPU_WRAPPERS == 1 )
+		xMPU_SETTINGS	xMPUSettings;		/*< The MPU settings are defined as part of the port layer.  THIS MUST BE THE SECOND MEMBER OF THE TCB STRUCT. */
+	#endif
+
+	ListItem_t			xStateListItem;	/*< The list that the state list item of a task is reference from denotes the state of that task (Ready, Blocked, Suspended ). */
+	ListItem_t			xEventListItem;		/*< Used to reference a task from an event list. */
+	UBaseType_t			uxPriority;			/*< The priority of the task.  0 is the lowest priority. */
+	StackType_t			*pxStack;			/*< Points to the start of the stack. */
+	char				pcTaskName[ configMAX_TASK_NAME_LEN ];/*< Descriptive name given to the task when created.  Facilitates debugging only. */ /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+
+	#if ( ( portSTACK_GROWTH > 0 ) || ( configRECORD_STACK_HIGH_ADDRESS == 1 ) )
+		StackType_t		*pxEndOfStack;		/*< Points to the highest valid address for the stack. */
+	#endif
+
+	#if ( portCRITICAL_NESTING_IN_TCB == 1 )
+		UBaseType_t		uxCriticalNesting;	/*< Holds the critical section nesting depth for ports that do not maintain their own count in the port layer. */
+	#endif
+
+	#if ( configUSE_TRACE_FACILITY == 1 )
+		UBaseType_t		uxTCBNumber;		/*< Stores a number that increments each time a TCB is created.  It allows debuggers to determine when a task has been deleted and then recreated. */
+		UBaseType_t		uxTaskNumber;		/*< Stores a number specifically for use by third party trace code. */
+	#endif
+
+	#if ( configUSE_MUTEXES == 1 )
+		UBaseType_t		uxBasePriority;		/*< The priority last assigned to the task - used by the priority inheritance mechanism. */
+		UBaseType_t		uxMutexesHeld;
+	#endif
+
+	#if ( configUSE_APPLICATION_TASK_TAG == 1 )
+		TaskHookFunction_t pxTaskTag;
+	#endif
+
+	#if( configNUM_THREAD_LOCAL_STORAGE_POINTERS > 0 )
+		void			*pvThreadLocalStoragePointers[ configNUM_THREAD_LOCAL_STORAGE_POINTERS ];
+	#endif
+
+	#if( configGENERATE_RUN_TIME_STATS == 1 )
+		uint32_t		ulRunTimeCounter;	/*< Stores the amount of time the task has spent in the Running state. */
+	#endif
+
+	#if ( configUSE_NEWLIB_REENTRANT == 1 )
+		/* Allocate a Newlib reent structure that is specific to this task.
+		Note Newlib support has been included by popular demand, but is not
+		used by the FreeRTOS maintainers themselves.  FreeRTOS is not
+		responsible for resulting newlib operation.  User must be familiar with
+		newlib and must provide system-wide implementations of the necessary
+		stubs. Be warned that (at the time of writing) the current newlib design
+		implements a system-wide malloc() that must be provided with locks.
+
+		See the third party link http://www.nadler.com/embedded/newlibAndFreeRTOS.html
+		for additional information. */
+		struct	_reent xNewLib_reent;
+	#endif
+
+	#if( configUSE_TASK_NOTIFICATIONS == 1 )
+		volatile uint32_t ulNotifiedValue;
+		volatile uint8_t ucNotifyState;
+	#endif
+
+	/* See the comments in FreeRTOS.h with the definition of
+	tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE. */
+	#if( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e731 !e9029 Macro has been consolidated for readability reasons. */
+		uint8_t	ucStaticallyAllocated; 		/*< Set to pdTRUE if the task is a statically allocated to ensure no attempt is made to free the memory. */
+	#endif
+
+	#if( INCLUDE_xTaskAbortDelay == 1 )
+		uint8_t ucDelayAborted;
+	#endif
+
+	#if( configUSE_POSIX_ERRNO == 1 )
+		int iTaskErrno;
+	#endif
+
+} tskTCB;
+
+/* The old tskTCB name is maintained above then typedefed to the new TCB_t name
+below to enable the use of older kernel aware debuggers. */
+typedef tskTCB TCB_t;
+
+/*lint -save -e956 A manual analysis and inspection has been used to determine
+which static variables must be declared volatile. */
+PRIVILEGED_DATA TCB_t * volatile pxCurrentTCB = NULL;
+
+/* Lists for ready and blocked tasks. --------------------
+xDelayedTaskList1 and xDelayedTaskList2 could be move to function scople but
+doing so breaks some kernel aware debuggers and debuggers that rely on removing
+the static qualifier. */
+PRIVILEGED_DATA static List_t pxReadyTasksLists[ configMAX_PRIORITIES ];/*< Prioritised ready tasks. */
+PRIVILEGED_DATA static List_t xDelayedTaskList1;						/*< Delayed tasks. */
+PRIVILEGED_DATA static List_t xDelayedTaskList2;						/*< Delayed tasks (two lists are used - one for delays that have overflowed the current tick count. */
+PRIVILEGED_DATA static List_t * volatile pxDelayedTaskList;				/*< Points to the delayed task list currently being used. */
+PRIVILEGED_DATA static List_t * volatile pxOverflowDelayedTaskList;		/*< Points to the delayed task list currently being used to hold tasks that have overflowed the current tick count. */
+PRIVILEGED_DATA static List_t xPendingReadyList;						/*< Tasks that have been readied while the scheduler was suspended.  They will be moved to the ready list when the scheduler is resumed. */
+
+#if( INCLUDE_vTaskDelete == 1 )
+
+	PRIVILEGED_DATA static List_t xTasksWaitingTermination;				/*< Tasks that have been deleted - but their memory not yet freed. */
+	PRIVILEGED_DATA static volatile UBaseType_t uxDeletedTasksWaitingCleanUp = ( UBaseType_t ) 0U;
+
+#endif
+
+#if ( INCLUDE_vTaskSuspend == 1 )
+
+	PRIVILEGED_DATA static List_t xSuspendedTaskList;					/*< Tasks that are currently suspended. */
+
+#endif
+
+/* Global POSIX errno. Its value is changed upon context switching to match
+the errno of the currently running task. */
+#if ( configUSE_POSIX_ERRNO == 1 )
+	int FreeRTOS_errno = 0;
+#endif
+
+/* Other file private variables. --------------------------------*/
+PRIVILEGED_DATA static volatile UBaseType_t uxCurrentNumberOfTasks 	= ( UBaseType_t ) 0U;
+PRIVILEGED_DATA static volatile TickType_t xTickCount 				= ( TickType_t ) configINITIAL_TICK_COUNT;
+PRIVILEGED_DATA static volatile UBaseType_t uxTopReadyPriority 		= tskIDLE_PRIORITY;
+PRIVILEGED_DATA static volatile BaseType_t xSchedulerRunning 		= pdFALSE;
+PRIVILEGED_DATA static volatile TickType_t xPendedTicks 			= ( TickType_t ) 0U;
+PRIVILEGED_DATA static volatile BaseType_t xYieldPending 			= pdFALSE;
+PRIVILEGED_DATA static volatile BaseType_t xNumOfOverflows 			= ( BaseType_t ) 0;
+PRIVILEGED_DATA static UBaseType_t uxTaskNumber 					= ( UBaseType_t ) 0U;
+PRIVILEGED_DATA static volatile TickType_t xNextTaskUnblockTime		= ( TickType_t ) 0U; /* Initialised to portMAX_DELAY before the scheduler starts. */
+PRIVILEGED_DATA static TaskHandle_t xIdleTaskHandle					= NULL;			/*< Holds the handle of the idle task.  The idle task is created automatically when the scheduler is started. */
+
+/* Context switches are held pending while the scheduler is suspended.  Also,
+interrupts must not manipulate the xStateListItem of a TCB, or any of the
+lists the xStateListItem can be referenced from, if the scheduler is suspended.
+If an interrupt needs to unblock a task while the scheduler is suspended then it
+moves the task's event list item into the xPendingReadyList, ready for the
+kernel to move the task from the pending ready list into the real ready list
+when the scheduler is unsuspended.  The pending ready list itself can only be
+accessed from a critical section. */
+PRIVILEGED_DATA static volatile UBaseType_t uxSchedulerSuspended	= ( UBaseType_t ) pdFALSE;
+
+#if ( configGENERATE_RUN_TIME_STATS == 1 )
+
+	/* Do not move these variables to function scope as doing so prevents the
+	code working with debuggers that need to remove the static qualifier. */
+	PRIVILEGED_DATA static uint32_t ulTaskSwitchedInTime = 0UL;	/*< Holds the value of a timer/counter the last time a task was switched in. */
+	PRIVILEGED_DATA static uint32_t ulTotalRunTime = 0UL;		/*< Holds the total amount of execution time as defined by the run time counter clock. */
+
+#endif
+
+/*lint -restore */
+
+/*-----------------------------------------------------------*/
+
+/* Callback function prototypes. --------------------------*/
+#if(  configCHECK_FOR_STACK_OVERFLOW > 0 )
+
+	extern void vApplicationStackOverflowHook( TaskHandle_t xTask, char *pcTaskName );
+
+#endif
+
+#if( configUSE_TICK_HOOK > 0 )
+
+	extern void vApplicationTickHook( void ); /*lint !e526 Symbol not defined as it is an application callback. */
+
+#endif
+
+#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+
+	extern void vApplicationGetIdleTaskMemory( StaticTask_t **ppxIdleTaskTCBBuffer, StackType_t **ppxIdleTaskStackBuffer, uint32_t *pulIdleTaskStackSize ); /*lint !e526 Symbol not defined as it is an application callback. */
+
+#endif
+
+/* File private functions. --------------------------------*/
+
+/**
+ * Utility task that simply returns pdTRUE if the task referenced by xTask is
+ * currently in the Suspended state, or pdFALSE if the task referenced by xTask
+ * is in any other state.
+ */
+#if ( INCLUDE_vTaskSuspend == 1 )
+
+	static BaseType_t prvTaskIsTaskSuspended( const TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
+
+#endif /* INCLUDE_vTaskSuspend */
+
+/*
+ * Utility to ready all the lists used by the scheduler.  This is called
+ * automatically upon the creation of the first task.
+ */
+static void prvInitialiseTaskLists( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * The idle task, which as all tasks is implemented as a never ending loop.
+ * The idle task is automatically created and added to the ready lists upon
+ * creation of the first user task.
+ *
+ * The portTASK_FUNCTION_PROTO() macro is used to allow port/compiler specific
+ * language extensions.  The equivalent prototype for this function is:
+ *
+ * void prvIdleTask( void *pvParameters );
+ *
+ */
+static portTASK_FUNCTION_PROTO( prvIdleTask, pvParameters );
+
+/*
+ * Utility to free all memory allocated by the scheduler to hold a TCB,
+ * including the stack pointed to by the TCB.
+ *
+ * This does not free memory allocated by the task itself (i.e. memory
+ * allocated by calls to pvPortMalloc from within the tasks application code).
+ */
+#if ( INCLUDE_vTaskDelete == 1 )
+
+	static void prvDeleteTCB( TCB_t *pxTCB ) PRIVILEGED_FUNCTION;
+
+#endif
+
+/*
+ * Used only by the idle task.  This checks to see if anything has been placed
+ * in the list of tasks waiting to be deleted.  If so the task is cleaned up
+ * and its TCB deleted.
+ */
+static void prvCheckTasksWaitingTermination( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * The currently executing task is entering the Blocked state.  Add the task to
+ * either the current or the overflow delayed task list.
+ */
+static void prvAddCurrentTaskToDelayedList( TickType_t xTicksToWait, const BaseType_t xCanBlockIndefinitely ) PRIVILEGED_FUNCTION;
+
+/*
+ * Fills an TaskStatus_t structure with information on each task that is
+ * referenced from the pxList list (which may be a ready list, a delayed list,
+ * a suspended list, etc.).
+ *
+ * THIS FUNCTION IS INTENDED FOR DEBUGGING ONLY, AND SHOULD NOT BE CALLED FROM
+ * NORMAL APPLICATION CODE.
+ */
+#if ( configUSE_TRACE_FACILITY == 1 )
+
+	static UBaseType_t prvListTasksWithinSingleList( TaskStatus_t *pxTaskStatusArray, List_t *pxList, eTaskState eState ) PRIVILEGED_FUNCTION;
+
+#endif
+
+/*
+ * Searches pxList for a task with name pcNameToQuery - returning a handle to
+ * the task if it is found, or NULL if the task is not found.
+ */
+#if ( INCLUDE_xTaskGetHandle == 1 )
+
+	static TCB_t *prvSearchForNameWithinSingleList( List_t *pxList, const char pcNameToQuery[] ) PRIVILEGED_FUNCTION;
+
+#endif
+
+/*
+ * When a task is created, the stack of the task is filled with a known value.
+ * This function determines the 'high water mark' of the task stack by
+ * determining how much of the stack remains at the original preset value.
+ */
+#if ( ( configUSE_TRACE_FACILITY == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 ) )
+
+	static configSTACK_DEPTH_TYPE prvTaskCheckFreeStackSpace( const uint8_t * pucStackByte ) PRIVILEGED_FUNCTION;
+
+#endif
+
+/*
+ * Return the amount of time, in ticks, that will pass before the kernel will
+ * next move a task from the Blocked state to the Running state.
+ *
+ * This conditional compilation should use inequality to 0, not equality to 1.
+ * This is to ensure portSUPPRESS_TICKS_AND_SLEEP() can be called when user
+ * defined low power mode implementations require configUSE_TICKLESS_IDLE to be
+ * set to a value other than 1.
+ */
+#if ( configUSE_TICKLESS_IDLE != 0 )
+
+	static TickType_t prvGetExpectedIdleTime( void ) PRIVILEGED_FUNCTION;
+
+#endif
+
+/*
+ * Set xNextTaskUnblockTime to the time at which the next Blocked state task
+ * will exit the Blocked state.
+ */
+static void prvResetNextTaskUnblockTime( void );
+
+#if ( ( configUSE_TRACE_FACILITY == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) )
+
+	/*
+	 * Helper function used to pad task names with spaces when printing out
+	 * human readable tables of task information.
+	 */
+	static char *prvWriteNameToBuffer( char *pcBuffer, const char *pcTaskName ) PRIVILEGED_FUNCTION;
+
+#endif
+
+/*
+ * Called after a Task_t structure has been allocated either statically or
+ * dynamically to fill in the structure's members.
+ */
+static void prvInitialiseNewTask( 	TaskFunction_t pxTaskCode,
+									const char * const pcName, 		/*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+									const uint32_t ulStackDepth,
+									void * const pvParameters,
+									UBaseType_t uxPriority,
+									TaskHandle_t * const pxCreatedTask,
+									TCB_t *pxNewTCB,
+									const MemoryRegion_t * const xRegions ) PRIVILEGED_FUNCTION;
+
+/*
+ * Called after a new task has been created and initialised to place the task
+ * under the control of the scheduler.
+ */
+static void prvAddNewTaskToReadyList( TCB_t *pxNewTCB ) PRIVILEGED_FUNCTION;
+
+/*
+ * freertos_tasks_c_additions_init() should only be called if the user definable
+ * macro FREERTOS_TASKS_C_ADDITIONS_INIT() is defined, as that is the only macro
+ * called by the function.
+ */
+#ifdef FREERTOS_TASKS_C_ADDITIONS_INIT
+
+	static void freertos_tasks_c_additions_init( void ) PRIVILEGED_FUNCTION;
+
+#endif
+
+/*-----------------------------------------------------------*/
+
+#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+
+	TaskHandle_t xTaskCreateStatic(	TaskFunction_t pxTaskCode,
+									const char * const pcName,		/*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+									const uint32_t ulStackDepth,
+									void * const pvParameters,
+									UBaseType_t uxPriority,
+									StackType_t * const puxStackBuffer,
+									StaticTask_t * const pxTaskBuffer )
+	{
+	TCB_t *pxNewTCB;
+	TaskHandle_t xReturn;
+
+		configASSERT( puxStackBuffer != NULL );
+		configASSERT( pxTaskBuffer != NULL );
+
+		#if( configASSERT_DEFINED == 1 )
+		{
+			/* Sanity check that the size of the structure used to declare a
+			variable of type StaticTask_t equals the size of the real task
+			structure. */
+			volatile size_t xSize = sizeof( StaticTask_t );
+			configASSERT( xSize == sizeof( TCB_t ) );
+			( void ) xSize; /* Prevent lint warning when configASSERT() is not used. */
+		}
+		#endif /* configASSERT_DEFINED */
+
+
+		if( ( pxTaskBuffer != NULL ) && ( puxStackBuffer != NULL ) )
+		{
+			/* The memory used for the task's TCB and stack are passed into this
+			function - use them. */
+			pxNewTCB = ( TCB_t * ) pxTaskBuffer; /*lint !e740 !e9087 Unusual cast is ok as the structures are designed to have the same alignment, and the size is checked by an assert. */
+			pxNewTCB->pxStack = ( StackType_t * ) puxStackBuffer;
+
+			#if( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e731 !e9029 Macro has been consolidated for readability reasons. */
+			{
+				/* Tasks can be created statically or dynamically, so note this
+				task was created statically in case the task is later deleted. */
+				pxNewTCB->ucStaticallyAllocated = tskSTATICALLY_ALLOCATED_STACK_AND_TCB;
+			}
+			#endif /* tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE */
+
+			prvInitialiseNewTask( pxTaskCode, pcName, ulStackDepth, pvParameters, uxPriority, &xReturn, pxNewTCB, NULL );
+			prvAddNewTaskToReadyList( pxNewTCB );
+		}
+		else
+		{
+			xReturn = NULL;
+		}
+
+		return xReturn;
+	}
+
+#endif /* SUPPORT_STATIC_ALLOCATION */
+/*-----------------------------------------------------------*/
+
+#if( ( portUSING_MPU_WRAPPERS == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) )
+
+	BaseType_t xTaskCreateRestrictedStatic( const TaskParameters_t * const pxTaskDefinition, TaskHandle_t *pxCreatedTask )
+	{
+	TCB_t *pxNewTCB;
+	BaseType_t xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY;
+
+		configASSERT( pxTaskDefinition->puxStackBuffer != NULL );
+		configASSERT( pxTaskDefinition->pxTaskBuffer != NULL );
+
+		if( ( pxTaskDefinition->puxStackBuffer != NULL ) && ( pxTaskDefinition->pxTaskBuffer != NULL ) )
+		{
+			/* Allocate space for the TCB.  Where the memory comes from depends
+			on the implementation of the port malloc function and whether or
+			not static allocation is being used. */
+			pxNewTCB = ( TCB_t * ) pxTaskDefinition->pxTaskBuffer;
+
+			/* Store the stack location in the TCB. */
+			pxNewTCB->pxStack = pxTaskDefinition->puxStackBuffer;
+
+			#if( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 )
+			{
+				/* Tasks can be created statically or dynamically, so note this
+				task was created statically in case the task is later deleted. */
+				pxNewTCB->ucStaticallyAllocated = tskSTATICALLY_ALLOCATED_STACK_AND_TCB;
+			}
+			#endif /* tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE */
+
+			prvInitialiseNewTask(	pxTaskDefinition->pvTaskCode,
+									pxTaskDefinition->pcName,
+									( uint32_t ) pxTaskDefinition->usStackDepth,
+									pxTaskDefinition->pvParameters,
+									pxTaskDefinition->uxPriority,
+									pxCreatedTask, pxNewTCB,
+									pxTaskDefinition->xRegions );
+
+			prvAddNewTaskToReadyList( pxNewTCB );
+			xReturn = pdPASS;
+		}
+
+		return xReturn;
+	}
+
+#endif /* ( portUSING_MPU_WRAPPERS == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) */
+/*-----------------------------------------------------------*/
+
+#if( ( portUSING_MPU_WRAPPERS == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
+
+	BaseType_t xTaskCreateRestricted( const TaskParameters_t * const pxTaskDefinition, TaskHandle_t *pxCreatedTask )
+	{
+	TCB_t *pxNewTCB;
+	BaseType_t xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY;
+
+		configASSERT( pxTaskDefinition->puxStackBuffer );
+
+		if( pxTaskDefinition->puxStackBuffer != NULL )
+		{
+			/* Allocate space for the TCB.  Where the memory comes from depends
+			on the implementation of the port malloc function and whether or
+			not static allocation is being used. */
+			pxNewTCB = ( TCB_t * ) pvPortMalloc( sizeof( TCB_t ) );
+
+			if( pxNewTCB != NULL )
+			{
+				/* Store the stack location in the TCB. */
+				pxNewTCB->pxStack = pxTaskDefinition->puxStackBuffer;
+
+				#if( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 )
+				{
+					/* Tasks can be created statically or dynamically, so note
+					this task had a statically allocated stack in case it is
+					later deleted.  The TCB was allocated dynamically. */
+					pxNewTCB->ucStaticallyAllocated = tskSTATICALLY_ALLOCATED_STACK_ONLY;
+				}
+				#endif /* tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE */
+
+				prvInitialiseNewTask(	pxTaskDefinition->pvTaskCode,
+										pxTaskDefinition->pcName,
+										( uint32_t ) pxTaskDefinition->usStackDepth,
+										pxTaskDefinition->pvParameters,
+										pxTaskDefinition->uxPriority,
+										pxCreatedTask, pxNewTCB,
+										pxTaskDefinition->xRegions );
+
+				prvAddNewTaskToReadyList( pxNewTCB );
+				xReturn = pdPASS;
+			}
+		}
+
+		return xReturn;
+	}
+
+#endif /* portUSING_MPU_WRAPPERS */
+/*-----------------------------------------------------------*/
+
+#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+
+	BaseType_t xTaskCreate(	TaskFunction_t pxTaskCode,
+							const char * const pcName,		/*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+							const configSTACK_DEPTH_TYPE usStackDepth,
+							void * const pvParameters,
+							UBaseType_t uxPriority,
+							TaskHandle_t * const pxCreatedTask )
+	{
+	TCB_t *pxNewTCB;
+	BaseType_t xReturn;
+
+		/* If the stack grows down then allocate the stack then the TCB so the stack
+		does not grow into the TCB.  Likewise if the stack grows up then allocate
+		the TCB then the stack. */
+		#if( portSTACK_GROWTH > 0 )
+		{
+			/* Allocate space for the TCB.  Where the memory comes from depends on
+			the implementation of the port malloc function and whether or not static
+			allocation is being used. */
+			pxNewTCB = ( TCB_t * ) pvPortMalloc( sizeof( TCB_t ) );
+
+			if( pxNewTCB != NULL )
+			{
+				/* Allocate space for the stack used by the task being created.
+				The base of the stack memory stored in the TCB so the task can
+				be deleted later if required. */
+				pxNewTCB->pxStack = ( StackType_t * ) pvPortMalloc( ( ( ( size_t ) usStackDepth ) * sizeof( StackType_t ) ) ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
+
+				if( pxNewTCB->pxStack == NULL )
+				{
+					/* Could not allocate the stack.  Delete the allocated TCB. */
+					vPortFree( pxNewTCB );
+					pxNewTCB = NULL;
+				}
+			}
+		}
+		#else /* portSTACK_GROWTH */
+		{
+		StackType_t *pxStack;
+
+			/* Allocate space for the stack used by the task being created. */
+			pxStack = pvPortMalloc( ( ( ( size_t ) usStackDepth ) * sizeof( StackType_t ) ) ); /*lint !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack and this allocation is the stack. */
+
+			if( pxStack != NULL )
+			{
+				/* Allocate space for the TCB. */
+				pxNewTCB = ( TCB_t * ) pvPortMalloc( sizeof( TCB_t ) ); /*lint !e9087 !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack, and the first member of TCB_t is always a pointer to the task's stack. */
+
+				if( pxNewTCB != NULL )
+				{
+					/* Store the stack location in the TCB. */
+					pxNewTCB->pxStack = pxStack;
+				}
+				else
+				{
+					/* The stack cannot be used as the TCB was not created.  Free
+					it again. */
+					vPortFree( pxStack );
+				}
+			}
+			else
+			{
+				pxNewTCB = NULL;
+			}
+		}
+		#endif /* portSTACK_GROWTH */
+
+		if( pxNewTCB != NULL )
+		{
+			#if( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e9029 !e731 Macro has been consolidated for readability reasons. */
+			{
+				/* Tasks can be created statically or dynamically, so note this
+				task was created dynamically in case it is later deleted. */
+				pxNewTCB->ucStaticallyAllocated = tskDYNAMICALLY_ALLOCATED_STACK_AND_TCB;
+			}
+			#endif /* tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE */
+
+			prvInitialiseNewTask( pxTaskCode, pcName, ( uint32_t ) usStackDepth, pvParameters, uxPriority, pxCreatedTask, pxNewTCB, NULL );
+			prvAddNewTaskToReadyList( pxNewTCB );
+			xReturn = pdPASS;
+		}
+		else
+		{
+			xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY;
+		}
+
+		return xReturn;
+	}
+
+#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
+/*-----------------------------------------------------------*/
+
+static void prvInitialiseNewTask( 	TaskFunction_t pxTaskCode,
+									const char * const pcName,		/*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+									const uint32_t ulStackDepth,
+									void * const pvParameters,
+									UBaseType_t uxPriority,
+									TaskHandle_t * const pxCreatedTask,
+									TCB_t *pxNewTCB,
+									const MemoryRegion_t * const xRegions )
+{
+StackType_t *pxTopOfStack;
+UBaseType_t x;
+
+	#if( portUSING_MPU_WRAPPERS == 1 )
+		/* Should the task be created in privileged mode? */
+		BaseType_t xRunPrivileged;
+		if( ( uxPriority & portPRIVILEGE_BIT ) != 0U )
+		{
+			xRunPrivileged = pdTRUE;
+		}
+		else
+		{
+			xRunPrivileged = pdFALSE;
+		}
+		uxPriority &= ~portPRIVILEGE_BIT;
+	#endif /* portUSING_MPU_WRAPPERS == 1 */
+
+	/* Avoid dependency on memset() if it is not required. */
+	#if( tskSET_NEW_STACKS_TO_KNOWN_VALUE == 1 )
+	{
+		/* Fill the stack with a known value to assist debugging. */
+		( void ) memset( pxNewTCB->pxStack, ( int ) tskSTACK_FILL_BYTE, ( size_t ) ulStackDepth * sizeof( StackType_t ) );
+	}
+	#endif /* tskSET_NEW_STACKS_TO_KNOWN_VALUE */
+
+	/* Calculate the top of stack address.  This depends on whether the stack
+	grows from high memory to low (as per the 80x86) or vice versa.
+	portSTACK_GROWTH is used to make the result positive or negative as required
+	by the port. */
+	#if( portSTACK_GROWTH < 0 )
+	{
+		pxTopOfStack = &( pxNewTCB->pxStack[ ulStackDepth - ( uint32_t ) 1 ] );
+		pxTopOfStack = ( StackType_t * ) ( ( ( portPOINTER_SIZE_TYPE ) pxTopOfStack ) & ( ~( ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) ) ); /*lint !e923 !e9033 !e9078 MISRA exception.  Avoiding casts between pointers and integers is not practical.  Size differences accounted for using portPOINTER_SIZE_TYPE type.  Checked by assert(). */
+
+		/* Check the alignment of the calculated top of stack is correct. */
+		configASSERT( ( ( ( portPOINTER_SIZE_TYPE ) pxTopOfStack & ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) == 0UL ) );
+
+		#if( configRECORD_STACK_HIGH_ADDRESS == 1 )
+		{
+			/* Also record the stack's high address, which may assist
+			debugging. */
+			pxNewTCB->pxEndOfStack = pxTopOfStack;
+		}
+		#endif /* configRECORD_STACK_HIGH_ADDRESS */
+	}
+	#else /* portSTACK_GROWTH */
+	{
+		pxTopOfStack = pxNewTCB->pxStack;
+
+		/* Check the alignment of the stack buffer is correct. */
+		configASSERT( ( ( ( portPOINTER_SIZE_TYPE ) pxNewTCB->pxStack & ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) == 0UL ) );
+
+		/* The other extreme of the stack space is required if stack checking is
+		performed. */
+		pxNewTCB->pxEndOfStack = pxNewTCB->pxStack + ( ulStackDepth - ( uint32_t ) 1 );
+	}
+	#endif /* portSTACK_GROWTH */
+
+	/* Store the task name in the TCB. */
+	if( pcName != NULL )
+	{
+		for( x = ( UBaseType_t ) 0; x < ( UBaseType_t ) configMAX_TASK_NAME_LEN; x++ )
+		{
+			pxNewTCB->pcTaskName[ x ] = pcName[ x ];
+
+			/* Don't copy all configMAX_TASK_NAME_LEN if the string is shorter than
+			configMAX_TASK_NAME_LEN characters just in case the memory after the
+			string is not accessible (extremely unlikely). */
+			if( pcName[ x ] == ( char ) 0x00 )
+			{
+				break;
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+
+		/* Ensure the name string is terminated in the case that the string length
+		was greater or equal to configMAX_TASK_NAME_LEN. */
+		pxNewTCB->pcTaskName[ configMAX_TASK_NAME_LEN - 1 ] = '\0';
+	}
+	else
+	{
+		/* The task has not been given a name, so just ensure there is a NULL
+		terminator when it is read out. */
+		pxNewTCB->pcTaskName[ 0 ] = 0x00;
+	}
+
+	/* This is used as an array index so must ensure it's not too large.  First
+	remove the privilege bit if one is present. */
+	if( uxPriority >= ( UBaseType_t ) configMAX_PRIORITIES )
+	{
+		uxPriority = ( UBaseType_t ) configMAX_PRIORITIES - ( UBaseType_t ) 1U;
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	pxNewTCB->uxPriority = uxPriority;
+	#if ( configUSE_MUTEXES == 1 )
+	{
+		pxNewTCB->uxBasePriority = uxPriority;
+		pxNewTCB->uxMutexesHeld = 0;
+	}
+	#endif /* configUSE_MUTEXES */
+
+	vListInitialiseItem( &( pxNewTCB->xStateListItem ) );
+	vListInitialiseItem( &( pxNewTCB->xEventListItem ) );
+
+	/* Set the pxNewTCB as a link back from the ListItem_t.  This is so we can get
+	back to	the containing TCB from a generic item in a list. */
+	listSET_LIST_ITEM_OWNER( &( pxNewTCB->xStateListItem ), pxNewTCB );
+
+	/* Event lists are always in priority order. */
+	listSET_LIST_ITEM_VALUE( &( pxNewTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
+	listSET_LIST_ITEM_OWNER( &( pxNewTCB->xEventListItem ), pxNewTCB );
+
+	#if ( portCRITICAL_NESTING_IN_TCB == 1 )
+	{
+		pxNewTCB->uxCriticalNesting = ( UBaseType_t ) 0U;
+	}
+	#endif /* portCRITICAL_NESTING_IN_TCB */
+
+	#if ( configUSE_APPLICATION_TASK_TAG == 1 )
+	{
+		pxNewTCB->pxTaskTag = NULL;
+	}
+	#endif /* configUSE_APPLICATION_TASK_TAG */
+
+	#if ( configGENERATE_RUN_TIME_STATS == 1 )
+	{
+		pxNewTCB->ulRunTimeCounter = 0UL;
+	}
+	#endif /* configGENERATE_RUN_TIME_STATS */
+
+	#if ( portUSING_MPU_WRAPPERS == 1 )
+	{
+		vPortStoreTaskMPUSettings( &( pxNewTCB->xMPUSettings ), xRegions, pxNewTCB->pxStack, ulStackDepth );
+	}
+	#else
+	{
+		/* Avoid compiler warning about unreferenced parameter. */
+		( void ) xRegions;
+	}
+	#endif
+
+	#if( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 )
+	{
+		for( x = 0; x < ( UBaseType_t ) configNUM_THREAD_LOCAL_STORAGE_POINTERS; x++ )
+		{
+			pxNewTCB->pvThreadLocalStoragePointers[ x ] = NULL;
+		}
+	}
+	#endif
+
+	#if ( configUSE_TASK_NOTIFICATIONS == 1 )
+	{
+		pxNewTCB->ulNotifiedValue = 0;
+		pxNewTCB->ucNotifyState = taskNOT_WAITING_NOTIFICATION;
+	}
+	#endif
+
+	#if ( configUSE_NEWLIB_REENTRANT == 1 )
+	{
+		/* Initialise this task's Newlib reent structure.
+		See the third party link http://www.nadler.com/embedded/newlibAndFreeRTOS.html
+		for additional information. */
+		_REENT_INIT_PTR( ( &( pxNewTCB->xNewLib_reent ) ) );
+	}
+	#endif
+
+	#if( INCLUDE_xTaskAbortDelay == 1 )
+	{
+		pxNewTCB->ucDelayAborted = pdFALSE;
+	}
+	#endif
+
+	/* Initialize the TCB stack to look as if the task was already running,
+	but had been interrupted by the scheduler.  The return address is set
+	to the start of the task function. Once the stack has been initialised
+	the top of stack variable is updated. */
+	#if( portUSING_MPU_WRAPPERS == 1 )
+	{
+		/* If the port has capability to detect stack overflow,
+		pass the stack end address to the stack initialization
+		function as well. */
+		#if( portHAS_STACK_OVERFLOW_CHECKING == 1 )
+		{
+			#if( portSTACK_GROWTH < 0 )
+			{
+				pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxNewTCB->pxStack, pxTaskCode, pvParameters, xRunPrivileged );
+			}
+			#else /* portSTACK_GROWTH */
+			{
+				pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxNewTCB->pxEndOfStack, pxTaskCode, pvParameters, xRunPrivileged );
+			}
+			#endif /* portSTACK_GROWTH */
+		}
+		#else /* portHAS_STACK_OVERFLOW_CHECKING */
+		{
+			pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxTaskCode, pvParameters, xRunPrivileged );
+		}
+		#endif /* portHAS_STACK_OVERFLOW_CHECKING */
+	}
+	#else /* portUSING_MPU_WRAPPERS */
+	{
+		/* If the port has capability to detect stack overflow,
+		pass the stack end address to the stack initialization
+		function as well. */
+		#if( portHAS_STACK_OVERFLOW_CHECKING == 1 )
+		{
+			#if( portSTACK_GROWTH < 0 )
+			{
+				pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxNewTCB->pxStack, pxTaskCode, pvParameters );
+			}
+			#else /* portSTACK_GROWTH */
+			{
+				pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxNewTCB->pxEndOfStack, pxTaskCode, pvParameters );
+			}
+			#endif /* portSTACK_GROWTH */
+		}
+		#else /* portHAS_STACK_OVERFLOW_CHECKING */
+		{
+			pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxTaskCode, pvParameters );
+		}
+		#endif /* portHAS_STACK_OVERFLOW_CHECKING */
+	}
+	#endif /* portUSING_MPU_WRAPPERS */
+
+	if( pxCreatedTask != NULL )
+	{
+		/* Pass the handle out in an anonymous way.  The handle can be used to
+		change the created task's priority, delete the created task, etc.*/
+		*pxCreatedTask = ( TaskHandle_t ) pxNewTCB;
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+}
+/*-----------------------------------------------------------*/
+
+static void prvAddNewTaskToReadyList( TCB_t *pxNewTCB )
+{
+	/* Ensure interrupts don't access the task lists while the lists are being
+	updated. */
+	taskENTER_CRITICAL();
+	{
+		uxCurrentNumberOfTasks++;
+		if( pxCurrentTCB == NULL )
+		{
+			/* There are no other tasks, or all the other tasks are in
+			the suspended state - make this the current task. */
+			pxCurrentTCB = pxNewTCB;
+
+			if( uxCurrentNumberOfTasks == ( UBaseType_t ) 1 )
+			{
+				/* This is the first task to be created so do the preliminary
+				initialisation required.  We will not recover if this call
+				fails, but we will report the failure. */
+				prvInitialiseTaskLists();
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		else
+		{
+			/* If the scheduler is not already running, make this task the
+			current task if it is the highest priority task to be created
+			so far. */
+			if( xSchedulerRunning == pdFALSE )
+			{
+				if( pxCurrentTCB->uxPriority <= pxNewTCB->uxPriority )
+				{
+					pxCurrentTCB = pxNewTCB;
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+
+		uxTaskNumber++;
+
+		#if ( configUSE_TRACE_FACILITY == 1 )
+		{
+			/* Add a counter into the TCB for tracing only. */
+			pxNewTCB->uxTCBNumber = uxTaskNumber;
+		}
+		#endif /* configUSE_TRACE_FACILITY */
+		traceTASK_CREATE( pxNewTCB );
+
+		prvAddTaskToReadyList( pxNewTCB );
+
+		portSETUP_TCB( pxNewTCB );
+	}
+	taskEXIT_CRITICAL();
+
+	if( xSchedulerRunning != pdFALSE )
+	{
+		/* If the created task is of a higher priority than the current task
+		then it should run now. */
+		if( pxCurrentTCB->uxPriority < pxNewTCB->uxPriority )
+		{
+			taskYIELD_IF_USING_PREEMPTION();
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+}
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_vTaskDelete == 1 )
+
+	void vTaskDelete( TaskHandle_t xTaskToDelete )
+	{
+	TCB_t *pxTCB;
+
+		taskENTER_CRITICAL();
+		{
+			/* If null is passed in here then it is the calling task that is
+			being deleted. */
+			pxTCB = prvGetTCBFromHandle( xTaskToDelete );
+
+			/* Remove task from the ready/delayed list. */
+			if( uxListRemove( &( pxTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )
+			{
+				taskRESET_READY_PRIORITY( pxTCB->uxPriority );
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+
+			/* Is the task waiting on an event also? */
+			if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) != NULL )
+			{
+				( void ) uxListRemove( &( pxTCB->xEventListItem ) );
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+
+			/* Increment the uxTaskNumber also so kernel aware debuggers can
+			detect that the task lists need re-generating.  This is done before
+			portPRE_TASK_DELETE_HOOK() as in the Windows port that macro will
+			not return. */
+			uxTaskNumber++;
+
+			if( pxTCB == pxCurrentTCB )
+			{
+				/* A task is deleting itself.  This cannot complete within the
+				task itself, as a context switch to another task is required.
+				Place the task in the termination list.  The idle task will
+				check the termination list and free up any memory allocated by
+				the scheduler for the TCB and stack of the deleted task. */
+				vListInsertEnd( &xTasksWaitingTermination, &( pxTCB->xStateListItem ) );
+
+				/* Increment the ucTasksDeleted variable so the idle task knows
+				there is a task that has been deleted and that it should therefore
+				check the xTasksWaitingTermination list. */
+				++uxDeletedTasksWaitingCleanUp;
+
+				/* Call the delete hook before portPRE_TASK_DELETE_HOOK() as
+				portPRE_TASK_DELETE_HOOK() does not return in the Win32 port. */
+				traceTASK_DELETE( pxTCB );
+
+				/* The pre-delete hook is primarily for the Windows simulator,
+				in which Windows specific clean up operations are performed,
+				after which it is not possible to yield away from this task -
+				hence xYieldPending is used to latch that a context switch is
+				required. */
+				portPRE_TASK_DELETE_HOOK( pxTCB, &xYieldPending );
+			}
+			else
+			{
+				--uxCurrentNumberOfTasks;
+				traceTASK_DELETE( pxTCB );
+				prvDeleteTCB( pxTCB );
+
+				/* Reset the next expected unblock time in case it referred to
+				the task that has just been deleted. */
+				prvResetNextTaskUnblockTime();
+			}
+		}
+		taskEXIT_CRITICAL();
+
+		/* Force a reschedule if it is the currently running task that has just
+		been deleted. */
+		if( xSchedulerRunning != pdFALSE )
+		{
+			if( pxTCB == pxCurrentTCB )
+			{
+				configASSERT( uxSchedulerSuspended == 0 );
+				portYIELD_WITHIN_API();
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+	}
+
+#endif /* INCLUDE_vTaskDelete */
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_vTaskDelayUntil == 1 )
+
+	void vTaskDelayUntil( TickType_t * const pxPreviousWakeTime, const TickType_t xTimeIncrement )
+	{
+	TickType_t xTimeToWake;
+	BaseType_t xAlreadyYielded, xShouldDelay = pdFALSE;
+
+		configASSERT( pxPreviousWakeTime );
+		configASSERT( ( xTimeIncrement > 0U ) );
+		configASSERT( uxSchedulerSuspended == 0 );
+
+		vTaskSuspendAll();
+		{
+			/* Minor optimisation.  The tick count cannot change in this
+			block. */
+			const TickType_t xConstTickCount = xTickCount;
+
+			/* Generate the tick time at which the task wants to wake. */
+			xTimeToWake = *pxPreviousWakeTime + xTimeIncrement;
+
+			if( xConstTickCount < *pxPreviousWakeTime )
+			{
+				/* The tick count has overflowed since this function was
+				lasted called.  In this case the only time we should ever
+				actually delay is if the wake time has also	overflowed,
+				and the wake time is greater than the tick time.  When this
+				is the case it is as if neither time had overflowed. */
+				if( ( xTimeToWake < *pxPreviousWakeTime ) && ( xTimeToWake > xConstTickCount ) )
+				{
+					xShouldDelay = pdTRUE;
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				/* The tick time has not overflowed.  In this case we will
+				delay if either the wake time has overflowed, and/or the
+				tick time is less than the wake time. */
+				if( ( xTimeToWake < *pxPreviousWakeTime ) || ( xTimeToWake > xConstTickCount ) )
+				{
+					xShouldDelay = pdTRUE;
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+
+			/* Update the wake time ready for the next call. */
+			*pxPreviousWakeTime = xTimeToWake;
+
+			if( xShouldDelay != pdFALSE )
+			{
+				traceTASK_DELAY_UNTIL( xTimeToWake );
+
+				/* prvAddCurrentTaskToDelayedList() needs the block time, not
+				the time to wake, so subtract the current tick count. */
+				prvAddCurrentTaskToDelayedList( xTimeToWake - xConstTickCount, pdFALSE );
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		xAlreadyYielded = xTaskResumeAll();
+
+		/* Force a reschedule if xTaskResumeAll has not already done so, we may
+		have put ourselves to sleep. */
+		if( xAlreadyYielded == pdFALSE )
+		{
+			portYIELD_WITHIN_API();
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+
+#endif /* INCLUDE_vTaskDelayUntil */
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_vTaskDelay == 1 )
+
+	void vTaskDelay( const TickType_t xTicksToDelay )
+	{
+	BaseType_t xAlreadyYielded = pdFALSE;
+
+		/* A delay time of zero just forces a reschedule. */
+		if( xTicksToDelay > ( TickType_t ) 0U )
+		{
+			configASSERT( uxSchedulerSuspended == 0 );
+			vTaskSuspendAll();
+			{
+				traceTASK_DELAY();
+
+				/* A task that is removed from the event list while the
+				scheduler is suspended will not get placed in the ready
+				list or removed from the blocked list until the scheduler
+				is resumed.
+
+				This task cannot be in an event list as it is the currently
+				executing task. */
+				prvAddCurrentTaskToDelayedList( xTicksToDelay, pdFALSE );
+			}
+			xAlreadyYielded = xTaskResumeAll();
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+
+		/* Force a reschedule if xTaskResumeAll has not already done so, we may
+		have put ourselves to sleep. */
+		if( xAlreadyYielded == pdFALSE )
+		{
+			portYIELD_WITHIN_API();
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+
+#endif /* INCLUDE_vTaskDelay */
+/*-----------------------------------------------------------*/
+
+#if( ( INCLUDE_eTaskGetState == 1 ) || ( configUSE_TRACE_FACILITY == 1 ) || ( INCLUDE_xTaskAbortDelay == 1 ) )
+
+	eTaskState eTaskGetState( TaskHandle_t xTask )
+	{
+	eTaskState eReturn;
+	List_t const * pxStateList, *pxDelayedList, *pxOverflowedDelayedList;
+	const TCB_t * const pxTCB = xTask;
+
+		configASSERT( pxTCB );
+
+		if( pxTCB == pxCurrentTCB )
+		{
+			/* The task calling this function is querying its own state. */
+			eReturn = eRunning;
+		}
+		else
+		{
+			taskENTER_CRITICAL();
+			{
+				pxStateList = listLIST_ITEM_CONTAINER( &( pxTCB->xStateListItem ) );
+				pxDelayedList = pxDelayedTaskList;
+				pxOverflowedDelayedList = pxOverflowDelayedTaskList;
+			}
+			taskEXIT_CRITICAL();
+
+			if( ( pxStateList == pxDelayedList ) || ( pxStateList == pxOverflowedDelayedList ) )
+			{
+				/* The task being queried is referenced from one of the Blocked
+				lists. */
+				eReturn = eBlocked;
+			}
+
+			#if ( INCLUDE_vTaskSuspend == 1 )
+				else if( pxStateList == &xSuspendedTaskList )
+				{
+					/* The task being queried is referenced from the suspended
+					list.  Is it genuinely suspended or is it blocked
+					indefinitely? */
+					if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) == NULL )
+					{
+						#if( configUSE_TASK_NOTIFICATIONS == 1 )
+						{
+							/* The task does not appear on the event list item of
+							and of the RTOS objects, but could still be in the
+							blocked state if it is waiting on its notification
+							rather than waiting on an object. */
+							if( pxTCB->ucNotifyState == taskWAITING_NOTIFICATION )
+							{
+								eReturn = eBlocked;
+							}
+							else
+							{
+								eReturn = eSuspended;
+							}
+						}
+						#else
+						{
+							eReturn = eSuspended;
+						}
+						#endif
+					}
+					else
+					{
+						eReturn = eBlocked;
+					}
+				}
+			#endif
+
+			#if ( INCLUDE_vTaskDelete == 1 )
+				else if( ( pxStateList == &xTasksWaitingTermination ) || ( pxStateList == NULL ) )
+				{
+					/* The task being queried is referenced from the deleted
+					tasks list, or it is not referenced from any lists at
+					all. */
+					eReturn = eDeleted;
+				}
+			#endif
+
+			else /*lint !e525 Negative indentation is intended to make use of pre-processor clearer. */
+			{
+				/* If the task is not in any other state, it must be in the
+				Ready (including pending ready) state. */
+				eReturn = eReady;
+			}
+		}
+
+		return eReturn;
+	} /*lint !e818 xTask cannot be a pointer to const because it is a typedef. */
+
+#endif /* INCLUDE_eTaskGetState */
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_uxTaskPriorityGet == 1 )
+
+	UBaseType_t uxTaskPriorityGet( const TaskHandle_t xTask )
+	{
+	TCB_t const *pxTCB;
+	UBaseType_t uxReturn;
+
+		taskENTER_CRITICAL();
+		{
+			/* If null is passed in here then it is the priority of the task
+			that called uxTaskPriorityGet() that is being queried. */
+			pxTCB = prvGetTCBFromHandle( xTask );
+			uxReturn = pxTCB->uxPriority;
+		}
+		taskEXIT_CRITICAL();
+
+		return uxReturn;
+	}
+
+#endif /* INCLUDE_uxTaskPriorityGet */
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_uxTaskPriorityGet == 1 )
+
+	UBaseType_t uxTaskPriorityGetFromISR( const TaskHandle_t xTask )
+	{
+	TCB_t const *pxTCB;
+	UBaseType_t uxReturn, uxSavedInterruptState;
+
+		/* RTOS ports that support interrupt nesting have the concept of a
+		maximum	system call (or maximum API call) interrupt priority.
+		Interrupts that are	above the maximum system call priority are keep
+		permanently enabled, even when the RTOS kernel is in a critical section,
+		but cannot make any calls to FreeRTOS API functions.  If configASSERT()
+		is defined in FreeRTOSConfig.h then
+		portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion
+		failure if a FreeRTOS API function is called from an interrupt that has
+		been assigned a priority above the configured maximum system call
+		priority.  Only FreeRTOS functions that end in FromISR can be called
+		from interrupts	that have been assigned a priority at or (logically)
+		below the maximum system call interrupt priority.  FreeRTOS maintains a
+		separate interrupt safe API to ensure interrupt entry is as fast and as
+		simple as possible.  More information (albeit Cortex-M specific) is
+		provided on the following link:
+		https://www.freertos.org/RTOS-Cortex-M3-M4.html */
+		portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
+
+		uxSavedInterruptState = portSET_INTERRUPT_MASK_FROM_ISR();
+		{
+			/* If null is passed in here then it is the priority of the calling
+			task that is being queried. */
+			pxTCB = prvGetTCBFromHandle( xTask );
+			uxReturn = pxTCB->uxPriority;
+		}
+		portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptState );
+
+		return uxReturn;
+	}
+
+#endif /* INCLUDE_uxTaskPriorityGet */
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_vTaskPrioritySet == 1 )
+
+	void vTaskPrioritySet( TaskHandle_t xTask, UBaseType_t uxNewPriority )
+	{
+	TCB_t *pxTCB;
+	UBaseType_t uxCurrentBasePriority, uxPriorityUsedOnEntry;
+	BaseType_t xYieldRequired = pdFALSE;
+
+		configASSERT( ( uxNewPriority < configMAX_PRIORITIES ) );
+
+		/* Ensure the new priority is valid. */
+		if( uxNewPriority >= ( UBaseType_t ) configMAX_PRIORITIES )
+		{
+			uxNewPriority = ( UBaseType_t ) configMAX_PRIORITIES - ( UBaseType_t ) 1U;
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+
+		taskENTER_CRITICAL();
+		{
+			/* If null is passed in here then it is the priority of the calling
+			task that is being changed. */
+			pxTCB = prvGetTCBFromHandle( xTask );
+
+			traceTASK_PRIORITY_SET( pxTCB, uxNewPriority );
+
+			#if ( configUSE_MUTEXES == 1 )
+			{
+				uxCurrentBasePriority = pxTCB->uxBasePriority;
+			}
+			#else
+			{
+				uxCurrentBasePriority = pxTCB->uxPriority;
+			}
+			#endif
+
+			if( uxCurrentBasePriority != uxNewPriority )
+			{
+				/* The priority change may have readied a task of higher
+				priority than the calling task. */
+				if( uxNewPriority > uxCurrentBasePriority )
+				{
+					if( pxTCB != pxCurrentTCB )
+					{
+						/* The priority of a task other than the currently
+						running task is being raised.  Is the priority being
+						raised above that of the running task? */
+						if( uxNewPriority >= pxCurrentTCB->uxPriority )
+						{
+							xYieldRequired = pdTRUE;
+						}
+						else
+						{
+							mtCOVERAGE_TEST_MARKER();
+						}
+					}
+					else
+					{
+						/* The priority of the running task is being raised,
+						but the running task must already be the highest
+						priority task able to run so no yield is required. */
+					}
+				}
+				else if( pxTCB == pxCurrentTCB )
+				{
+					/* Setting the priority of the running task down means
+					there may now be another task of higher priority that
+					is ready to execute. */
+					xYieldRequired = pdTRUE;
+				}
+				else
+				{
+					/* Setting the priority of any other task down does not
+					require a yield as the running task must be above the
+					new priority of the task being modified. */
+				}
+
+				/* Remember the ready list the task might be referenced from
+				before its uxPriority member is changed so the
+				taskRESET_READY_PRIORITY() macro can function correctly. */
+				uxPriorityUsedOnEntry = pxTCB->uxPriority;
+
+				#if ( configUSE_MUTEXES == 1 )
+				{
+					/* Only change the priority being used if the task is not
+					currently using an inherited priority. */
+					if( pxTCB->uxBasePriority == pxTCB->uxPriority )
+					{
+						pxTCB->uxPriority = uxNewPriority;
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+
+					/* The base priority gets set whatever. */
+					pxTCB->uxBasePriority = uxNewPriority;
+				}
+				#else
+				{
+					pxTCB->uxPriority = uxNewPriority;
+				}
+				#endif
+
+				/* Only reset the event list item value if the value is not
+				being used for anything else. */
+				if( ( listGET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ) ) & taskEVENT_LIST_ITEM_VALUE_IN_USE ) == 0UL )
+				{
+					listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), ( ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) uxNewPriority ) ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+
+				/* If the task is in the blocked or suspended list we need do
+				nothing more than change its priority variable. However, if
+				the task is in a ready list it needs to be removed and placed
+				in the list appropriate to its new priority. */
+				if( listIS_CONTAINED_WITHIN( &( pxReadyTasksLists[ uxPriorityUsedOnEntry ] ), &( pxTCB->xStateListItem ) ) != pdFALSE )
+				{
+					/* The task is currently in its ready list - remove before
+					adding it to it's new ready list.  As we are in a critical
+					section we can do this even if the scheduler is suspended. */
+					if( uxListRemove( &( pxTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )
+					{
+						/* It is known that the task is in its ready list so
+						there is no need to check again and the port level
+						reset macro can be called directly. */
+						portRESET_READY_PRIORITY( uxPriorityUsedOnEntry, uxTopReadyPriority );
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+					prvAddTaskToReadyList( pxTCB );
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+
+				if( xYieldRequired != pdFALSE )
+				{
+					taskYIELD_IF_USING_PREEMPTION();
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+
+				/* Remove compiler warning about unused variables when the port
+				optimised task selection is not being used. */
+				( void ) uxPriorityUsedOnEntry;
+			}
+		}
+		taskEXIT_CRITICAL();
+	}
+
+#endif /* INCLUDE_vTaskPrioritySet */
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_vTaskSuspend == 1 )
+
+	void vTaskSuspend( TaskHandle_t xTaskToSuspend )
+	{
+	TCB_t *pxTCB;
+
+		taskENTER_CRITICAL();
+		{
+			/* If null is passed in here then it is the running task that is
+			being suspended. */
+			pxTCB = prvGetTCBFromHandle( xTaskToSuspend );
+
+			traceTASK_SUSPEND( pxTCB );
+
+			/* Remove task from the ready/delayed list and place in the
+			suspended list. */
+			if( uxListRemove( &( pxTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )
+			{
+				taskRESET_READY_PRIORITY( pxTCB->uxPriority );
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+
+			/* Is the task waiting on an event also? */
+			if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) != NULL )
+			{
+				( void ) uxListRemove( &( pxTCB->xEventListItem ) );
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+
+			vListInsertEnd( &xSuspendedTaskList, &( pxTCB->xStateListItem ) );
+
+			#if( configUSE_TASK_NOTIFICATIONS == 1 )
+			{
+				if( pxTCB->ucNotifyState == taskWAITING_NOTIFICATION )
+				{
+					/* The task was blocked to wait for a notification, but is
+					now suspended, so no notification was received. */
+					pxTCB->ucNotifyState = taskNOT_WAITING_NOTIFICATION;
+				}
+			}
+			#endif
+		}
+		taskEXIT_CRITICAL();
+
+		if( xSchedulerRunning != pdFALSE )
+		{
+			/* Reset the next expected unblock time in case it referred to the
+			task that is now in the Suspended state. */
+			taskENTER_CRITICAL();
+			{
+				prvResetNextTaskUnblockTime();
+			}
+			taskEXIT_CRITICAL();
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+
+		if( pxTCB == pxCurrentTCB )
+		{
+			if( xSchedulerRunning != pdFALSE )
+			{
+				/* The current task has just been suspended. */
+				configASSERT( uxSchedulerSuspended == 0 );
+				portYIELD_WITHIN_API();
+			}
+			else
+			{
+				/* The scheduler is not running, but the task that was pointed
+				to by pxCurrentTCB has just been suspended and pxCurrentTCB
+				must be adjusted to point to a different task. */
+				if( listCURRENT_LIST_LENGTH( &xSuspendedTaskList ) == uxCurrentNumberOfTasks ) /*lint !e931 Right has no side effect, just volatile. */
+				{
+					/* No other tasks are ready, so set pxCurrentTCB back to
+					NULL so when the next task is created pxCurrentTCB will
+					be set to point to it no matter what its relative priority
+					is. */
+					pxCurrentTCB = NULL;
+				}
+				else
+				{
+					vTaskSwitchContext();
+				}
+			}
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+
+#endif /* INCLUDE_vTaskSuspend */
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_vTaskSuspend == 1 )
+
+	static BaseType_t prvTaskIsTaskSuspended( const TaskHandle_t xTask )
+	{
+	BaseType_t xReturn = pdFALSE;
+	const TCB_t * const pxTCB = xTask;
+
+		/* Accesses xPendingReadyList so must be called from a critical
+		section. */
+
+		/* It does not make sense to check if the calling task is suspended. */
+		configASSERT( xTask );
+
+		/* Is the task being resumed actually in the suspended list? */
+		if( listIS_CONTAINED_WITHIN( &xSuspendedTaskList, &( pxTCB->xStateListItem ) ) != pdFALSE )
+		{
+			/* Has the task already been resumed from within an ISR? */
+			if( listIS_CONTAINED_WITHIN( &xPendingReadyList, &( pxTCB->xEventListItem ) ) == pdFALSE )
+			{
+				/* Is it in the suspended list because it is in the	Suspended
+				state, or because is is blocked with no timeout? */
+				if( listIS_CONTAINED_WITHIN( NULL, &( pxTCB->xEventListItem ) ) != pdFALSE ) /*lint !e961.  The cast is only redundant when NULL is used. */
+				{
+					xReturn = pdTRUE;
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+
+		return xReturn;
+	} /*lint !e818 xTask cannot be a pointer to const because it is a typedef. */
+
+#endif /* INCLUDE_vTaskSuspend */
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_vTaskSuspend == 1 )
+
+	void vTaskResume( TaskHandle_t xTaskToResume )
+	{
+	TCB_t * const pxTCB = xTaskToResume;
+
+		/* It does not make sense to resume the calling task. */
+		configASSERT( xTaskToResume );
+
+		/* The parameter cannot be NULL as it is impossible to resume the
+		currently executing task. */
+		if( ( pxTCB != pxCurrentTCB ) && ( pxTCB != NULL ) )
+		{
+			taskENTER_CRITICAL();
+			{
+				if( prvTaskIsTaskSuspended( pxTCB ) != pdFALSE )
+				{
+					traceTASK_RESUME( pxTCB );
+
+					/* The ready list can be accessed even if the scheduler is
+					suspended because this is inside a critical section. */
+					( void ) uxListRemove(  &( pxTCB->xStateListItem ) );
+					prvAddTaskToReadyList( pxTCB );
+
+					/* A higher priority task may have just been resumed. */
+					if( pxTCB->uxPriority >= pxCurrentTCB->uxPriority )
+					{
+						/* This yield may not cause the task just resumed to run,
+						but will leave the lists in the correct state for the
+						next yield. */
+						taskYIELD_IF_USING_PREEMPTION();
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			taskEXIT_CRITICAL();
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+
+#endif /* INCLUDE_vTaskSuspend */
+
+/*-----------------------------------------------------------*/
+
+#if ( ( INCLUDE_xTaskResumeFromISR == 1 ) && ( INCLUDE_vTaskSuspend == 1 ) )
+
+	BaseType_t xTaskResumeFromISR( TaskHandle_t xTaskToResume )
+	{
+	BaseType_t xYieldRequired = pdFALSE;
+	TCB_t * const pxTCB = xTaskToResume;
+	UBaseType_t uxSavedInterruptStatus;
+
+		configASSERT( xTaskToResume );
+
+		/* RTOS ports that support interrupt nesting have the concept of a
+		maximum	system call (or maximum API call) interrupt priority.
+		Interrupts that are	above the maximum system call priority are keep
+		permanently enabled, even when the RTOS kernel is in a critical section,
+		but cannot make any calls to FreeRTOS API functions.  If configASSERT()
+		is defined in FreeRTOSConfig.h then
+		portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion
+		failure if a FreeRTOS API function is called from an interrupt that has
+		been assigned a priority above the configured maximum system call
+		priority.  Only FreeRTOS functions that end in FromISR can be called
+		from interrupts	that have been assigned a priority at or (logically)
+		below the maximum system call interrupt priority.  FreeRTOS maintains a
+		separate interrupt safe API to ensure interrupt entry is as fast and as
+		simple as possible.  More information (albeit Cortex-M specific) is
+		provided on the following link:
+		https://www.freertos.org/RTOS-Cortex-M3-M4.html */
+		portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
+
+		uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
+		{
+			if( prvTaskIsTaskSuspended( pxTCB ) != pdFALSE )
+			{
+				traceTASK_RESUME_FROM_ISR( pxTCB );
+
+				/* Check the ready lists can be accessed. */
+				if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )
+				{
+					/* Ready lists can be accessed so move the task from the
+					suspended list to the ready list directly. */
+					if( pxTCB->uxPriority >= pxCurrentTCB->uxPriority )
+					{
+						xYieldRequired = pdTRUE;
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+
+					( void ) uxListRemove( &( pxTCB->xStateListItem ) );
+					prvAddTaskToReadyList( pxTCB );
+				}
+				else
+				{
+					/* The delayed or ready lists cannot be accessed so the task
+					is held in the pending ready list until the scheduler is
+					unsuspended. */
+					vListInsertEnd( &( xPendingReadyList ), &( pxTCB->xEventListItem ) );
+				}
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
+
+		return xYieldRequired;
+	}
+
+#endif /* ( ( INCLUDE_xTaskResumeFromISR == 1 ) && ( INCLUDE_vTaskSuspend == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+void vTaskStartScheduler( void )
+{
+BaseType_t xReturn;
+
+	/* Add the idle task at the lowest priority. */
+	#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+	{
+		StaticTask_t *pxIdleTaskTCBBuffer = NULL;
+		StackType_t *pxIdleTaskStackBuffer = NULL;
+		uint32_t ulIdleTaskStackSize;
+
+		/* The Idle task is created using user provided RAM - obtain the
+		address of the RAM then create the idle task. */
+		vApplicationGetIdleTaskMemory( &pxIdleTaskTCBBuffer, &pxIdleTaskStackBuffer, &ulIdleTaskStackSize );
+		xIdleTaskHandle = xTaskCreateStatic(	prvIdleTask,
+												configIDLE_TASK_NAME,
+												ulIdleTaskStackSize,
+												( void * ) NULL, /*lint !e961.  The cast is not redundant for all compilers. */
+												portPRIVILEGE_BIT, /* In effect ( tskIDLE_PRIORITY | portPRIVILEGE_BIT ), but tskIDLE_PRIORITY is zero. */
+												pxIdleTaskStackBuffer,
+												pxIdleTaskTCBBuffer ); /*lint !e961 MISRA exception, justified as it is not a redundant explicit cast to all supported compilers. */
+
+		if( xIdleTaskHandle != NULL )
+		{
+			xReturn = pdPASS;
+		}
+		else
+		{
+			xReturn = pdFAIL;
+		}
+	}
+	#else
+	{
+		/* The Idle task is being created using dynamically allocated RAM. */
+		xReturn = xTaskCreate(	prvIdleTask,
+								configIDLE_TASK_NAME,
+								configMINIMAL_STACK_SIZE,
+								( void * ) NULL,
+								portPRIVILEGE_BIT, /* In effect ( tskIDLE_PRIORITY | portPRIVILEGE_BIT ), but tskIDLE_PRIORITY is zero. */
+								&xIdleTaskHandle ); /*lint !e961 MISRA exception, justified as it is not a redundant explicit cast to all supported compilers. */
+	}
+	#endif /* configSUPPORT_STATIC_ALLOCATION */
+
+	#if ( configUSE_TIMERS == 1 )
+	{
+		if( xReturn == pdPASS )
+		{
+			xReturn = xTimerCreateTimerTask();
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+	#endif /* configUSE_TIMERS */
+
+	if( xReturn == pdPASS )
+	{
+		/* freertos_tasks_c_additions_init() should only be called if the user
+		definable macro FREERTOS_TASKS_C_ADDITIONS_INIT() is defined, as that is
+		the only macro called by the function. */
+		#ifdef FREERTOS_TASKS_C_ADDITIONS_INIT
+		{
+			freertos_tasks_c_additions_init();
+		}
+		#endif
+
+		/* Interrupts are turned off here, to ensure a tick does not occur
+		before or during the call to xPortStartScheduler().  The stacks of
+		the created tasks contain a status word with interrupts switched on
+		so interrupts will automatically get re-enabled when the first task
+		starts to run. */
+		portDISABLE_INTERRUPTS();
+
+		#if ( configUSE_NEWLIB_REENTRANT == 1 )
+		{
+			/* Switch Newlib's _impure_ptr variable to point to the _reent
+			structure specific to the task that will run first.
+			See the third party link http://www.nadler.com/embedded/newlibAndFreeRTOS.html
+			for additional information. */
+			_impure_ptr = &( pxCurrentTCB->xNewLib_reent );
+		}
+		#endif /* configUSE_NEWLIB_REENTRANT */
+
+		xNextTaskUnblockTime = portMAX_DELAY;
+		xSchedulerRunning = pdTRUE;
+		xTickCount = ( TickType_t ) configINITIAL_TICK_COUNT;
+
+		/* If configGENERATE_RUN_TIME_STATS is defined then the following
+		macro must be defined to configure the timer/counter used to generate
+		the run time counter time base.   NOTE:  If configGENERATE_RUN_TIME_STATS
+		is set to 0 and the following line fails to build then ensure you do not
+		have portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() defined in your
+		FreeRTOSConfig.h file. */
+		portCONFIGURE_TIMER_FOR_RUN_TIME_STATS();
+
+		traceTASK_SWITCHED_IN();
+
+		/* Setting up the timer tick is hardware specific and thus in the
+		portable interface. */
+		if( xPortStartScheduler() != pdFALSE )
+		{
+			/* Should not reach here as if the scheduler is running the
+			function will not return. */
+		}
+		else
+		{
+			/* Should only reach here if a task calls xTaskEndScheduler(). */
+		}
+	}
+	else
+	{
+		/* This line will only be reached if the kernel could not be started,
+		because there was not enough FreeRTOS heap to create the idle task
+		or the timer task. */
+		configASSERT( xReturn != errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY );
+	}
+
+	/* Prevent compiler warnings if INCLUDE_xTaskGetIdleTaskHandle is set to 0,
+	meaning xIdleTaskHandle is not used anywhere else. */
+	( void ) xIdleTaskHandle;
+}
+/*-----------------------------------------------------------*/
+
+void vTaskEndScheduler( void )
+{
+	/* Stop the scheduler interrupts and call the portable scheduler end
+	routine so the original ISRs can be restored if necessary.  The port
+	layer must ensure interrupts enable	bit is left in the correct state. */
+	portDISABLE_INTERRUPTS();
+	xSchedulerRunning = pdFALSE;
+	vPortEndScheduler();
+}
+/*----------------------------------------------------------*/
+
+void vTaskSuspendAll( void )
+{
+	/* A critical section is not required as the variable is of type
+	BaseType_t.  Please read Richard Barry's reply in the following link to a
+	post in the FreeRTOS support forum before reporting this as a bug! -
+	http://goo.gl/wu4acr */
+
+	/* portSOFRWARE_BARRIER() is only implemented for emulated/simulated ports that
+	do not otherwise exhibit real time behaviour. */
+	portSOFTWARE_BARRIER();
+
+	/* The scheduler is suspended if uxSchedulerSuspended is non-zero.  An increment
+	is used to allow calls to vTaskSuspendAll() to nest. */
+	++uxSchedulerSuspended;
+
+	/* Enforces ordering for ports and optimised compilers that may otherwise place
+	the above increment elsewhere. */
+	portMEMORY_BARRIER();
+}
+/*----------------------------------------------------------*/
+
+#if ( configUSE_TICKLESS_IDLE != 0 )
+
+	static TickType_t prvGetExpectedIdleTime( void )
+	{
+	TickType_t xReturn;
+	UBaseType_t uxHigherPriorityReadyTasks = pdFALSE;
+
+		/* uxHigherPriorityReadyTasks takes care of the case where
+		configUSE_PREEMPTION is 0, so there may be tasks above the idle priority
+		task that are in the Ready state, even though the idle task is
+		running. */
+		#if( configUSE_PORT_OPTIMISED_TASK_SELECTION == 0 )
+		{
+			if( uxTopReadyPriority > tskIDLE_PRIORITY )
+			{
+				uxHigherPriorityReadyTasks = pdTRUE;
+			}
+		}
+		#else
+		{
+			const UBaseType_t uxLeastSignificantBit = ( UBaseType_t ) 0x01;
+
+			/* When port optimised task selection is used the uxTopReadyPriority
+			variable is used as a bit map.  If bits other than the least
+			significant bit are set then there are tasks that have a priority
+			above the idle priority that are in the Ready state.  This takes
+			care of the case where the co-operative scheduler is in use. */
+			if( uxTopReadyPriority > uxLeastSignificantBit )
+			{
+				uxHigherPriorityReadyTasks = pdTRUE;
+			}
+		}
+		#endif
+
+		if( pxCurrentTCB->uxPriority > tskIDLE_PRIORITY )
+		{
+			xReturn = 0;
+		}
+		else if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ tskIDLE_PRIORITY ] ) ) > 1 )
+		{
+			/* There are other idle priority tasks in the ready state.  If
+			time slicing is used then the very next tick interrupt must be
+			processed. */
+			xReturn = 0;
+		}
+		else if( uxHigherPriorityReadyTasks != pdFALSE )
+		{
+			/* There are tasks in the Ready state that have a priority above the
+			idle priority.  This path can only be reached if
+			configUSE_PREEMPTION is 0. */
+			xReturn = 0;
+		}
+		else
+		{
+			xReturn = xNextTaskUnblockTime - xTickCount;
+		}
+
+		return xReturn;
+	}
+
+#endif /* configUSE_TICKLESS_IDLE */
+/*----------------------------------------------------------*/
+
+BaseType_t xTaskResumeAll( void )
+{
+TCB_t *pxTCB = NULL;
+BaseType_t xAlreadyYielded = pdFALSE;
+
+	/* If uxSchedulerSuspended is zero then this function does not match a
+	previous call to vTaskSuspendAll(). */
+	configASSERT( uxSchedulerSuspended );
+
+	/* It is possible that an ISR caused a task to be removed from an event
+	list while the scheduler was suspended.  If this was the case then the
+	removed task will have been added to the xPendingReadyList.  Once the
+	scheduler has been resumed it is safe to move all the pending ready
+	tasks from this list into their appropriate ready list. */
+	taskENTER_CRITICAL();
+	{
+		--uxSchedulerSuspended;
+
+		if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )
+		{
+			if( uxCurrentNumberOfTasks > ( UBaseType_t ) 0U )
+			{
+				/* Move any readied tasks from the pending list into the
+				appropriate ready list. */
+				while( listLIST_IS_EMPTY( &xPendingReadyList ) == pdFALSE )
+				{
+					pxTCB = listGET_OWNER_OF_HEAD_ENTRY( ( &xPendingReadyList ) ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
+					( void ) uxListRemove( &( pxTCB->xEventListItem ) );
+					( void ) uxListRemove( &( pxTCB->xStateListItem ) );
+					prvAddTaskToReadyList( pxTCB );
+
+					/* If the moved task has a priority higher than the current
+					task then a yield must be performed. */
+					if( pxTCB->uxPriority >= pxCurrentTCB->uxPriority )
+					{
+						xYieldPending = pdTRUE;
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+
+				if( pxTCB != NULL )
+				{
+					/* A task was unblocked while the scheduler was suspended,
+					which may have prevented the next unblock time from being
+					re-calculated, in which case re-calculate it now.  Mainly
+					important for low power tickless implementations, where
+					this can prevent an unnecessary exit from low power
+					state. */
+					prvResetNextTaskUnblockTime();
+				}
+
+				/* If any ticks occurred while the scheduler was suspended then
+				they should be processed now.  This ensures the tick count does
+				not	slip, and that any delayed tasks are resumed at the correct
+				time. */
+				{
+					TickType_t xPendedCounts = xPendedTicks; /* Non-volatile copy. */
+
+					if( xPendedCounts > ( TickType_t ) 0U )
+					{
+						do
+						{
+							if( xTaskIncrementTick() != pdFALSE )
+							{
+								xYieldPending = pdTRUE;
+							}
+							else
+							{
+								mtCOVERAGE_TEST_MARKER();
+							}
+							--xPendedCounts;
+						} while( xPendedCounts > ( TickType_t ) 0U );
+
+						xPendedTicks = 0;
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+
+				if( xYieldPending != pdFALSE )
+				{
+					#if( configUSE_PREEMPTION != 0 )
+					{
+						xAlreadyYielded = pdTRUE;
+					}
+					#endif
+					taskYIELD_IF_USING_PREEMPTION();
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+	taskEXIT_CRITICAL();
+
+	return xAlreadyYielded;
+}
+/*-----------------------------------------------------------*/
+
+TickType_t xTaskGetTickCount( void )
+{
+TickType_t xTicks;
+
+	/* Critical section required if running on a 16 bit processor. */
+	portTICK_TYPE_ENTER_CRITICAL();
+	{
+		xTicks = xTickCount;
+	}
+	portTICK_TYPE_EXIT_CRITICAL();
+
+	return xTicks;
+}
+/*-----------------------------------------------------------*/
+
+TickType_t xTaskGetTickCountFromISR( void )
+{
+TickType_t xReturn;
+UBaseType_t uxSavedInterruptStatus;
+
+	/* RTOS ports that support interrupt nesting have the concept of a maximum
+	system call (or maximum API call) interrupt priority.  Interrupts that are
+	above the maximum system call priority are kept permanently enabled, even
+	when the RTOS kernel is in a critical section, but cannot make any calls to
+	FreeRTOS API functions.  If configASSERT() is defined in FreeRTOSConfig.h
+	then portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion
+	failure if a FreeRTOS API function is called from an interrupt that has been
+	assigned a priority above the configured maximum system call priority.
+	Only FreeRTOS functions that end in FromISR can be called from interrupts
+	that have been assigned a priority at or (logically) below the maximum
+	system call	interrupt priority.  FreeRTOS maintains a separate interrupt
+	safe API to ensure interrupt entry is as fast and as simple as possible.
+	More information (albeit Cortex-M specific) is provided on the following
+	link: https://www.freertos.org/RTOS-Cortex-M3-M4.html */
+	portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
+
+	uxSavedInterruptStatus = portTICK_TYPE_SET_INTERRUPT_MASK_FROM_ISR();
+	{
+		xReturn = xTickCount;
+	}
+	portTICK_TYPE_CLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+UBaseType_t uxTaskGetNumberOfTasks( void )
+{
+	/* A critical section is not required because the variables are of type
+	BaseType_t. */
+	return uxCurrentNumberOfTasks;
+}
+/*-----------------------------------------------------------*/
+
+char *pcTaskGetName( TaskHandle_t xTaskToQuery ) /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+{
+TCB_t *pxTCB;
+
+	/* If null is passed in here then the name of the calling task is being
+	queried. */
+	pxTCB = prvGetTCBFromHandle( xTaskToQuery );
+	configASSERT( pxTCB );
+	return &( pxTCB->pcTaskName[ 0 ] );
+}
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_xTaskGetHandle == 1 )
+
+	static TCB_t *prvSearchForNameWithinSingleList( List_t *pxList, const char pcNameToQuery[] )
+	{
+	TCB_t *pxNextTCB, *pxFirstTCB, *pxReturn = NULL;
+	UBaseType_t x;
+	char cNextChar;
+	BaseType_t xBreakLoop;
+
+		/* This function is called with the scheduler suspended. */
+
+		if( listCURRENT_LIST_LENGTH( pxList ) > ( UBaseType_t ) 0 )
+		{
+			listGET_OWNER_OF_NEXT_ENTRY( pxFirstTCB, pxList );  /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
+
+			do
+			{
+				listGET_OWNER_OF_NEXT_ENTRY( pxNextTCB, pxList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
+
+				/* Check each character in the name looking for a match or
+				mismatch. */
+				xBreakLoop = pdFALSE;
+				for( x = ( UBaseType_t ) 0; x < ( UBaseType_t ) configMAX_TASK_NAME_LEN; x++ )
+				{
+					cNextChar = pxNextTCB->pcTaskName[ x ];
+
+					if( cNextChar != pcNameToQuery[ x ] )
+					{
+						/* Characters didn't match. */
+						xBreakLoop = pdTRUE;
+					}
+					else if( cNextChar == ( char ) 0x00 )
+					{
+						/* Both strings terminated, a match must have been
+						found. */
+						pxReturn = pxNextTCB;
+						xBreakLoop = pdTRUE;
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+
+					if( xBreakLoop != pdFALSE )
+					{
+						break;
+					}
+				}
+
+				if( pxReturn != NULL )
+				{
+					/* The handle has been found. */
+					break;
+				}
+
+			} while( pxNextTCB != pxFirstTCB );
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+
+		return pxReturn;
+	}
+
+#endif /* INCLUDE_xTaskGetHandle */
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_xTaskGetHandle == 1 )
+
+	TaskHandle_t xTaskGetHandle( const char *pcNameToQuery ) /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+	{
+	UBaseType_t uxQueue = configMAX_PRIORITIES;
+	TCB_t* pxTCB;
+
+		/* Task names will be truncated to configMAX_TASK_NAME_LEN - 1 bytes. */
+		configASSERT( strlen( pcNameToQuery ) < configMAX_TASK_NAME_LEN );
+
+		vTaskSuspendAll();
+		{
+			/* Search the ready lists. */
+			do
+			{
+				uxQueue--;
+				pxTCB = prvSearchForNameWithinSingleList( ( List_t * ) &( pxReadyTasksLists[ uxQueue ] ), pcNameToQuery );
+
+				if( pxTCB != NULL )
+				{
+					/* Found the handle. */
+					break;
+				}
+
+			} while( uxQueue > ( UBaseType_t ) tskIDLE_PRIORITY ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
+
+			/* Search the delayed lists. */
+			if( pxTCB == NULL )
+			{
+				pxTCB = prvSearchForNameWithinSingleList( ( List_t * ) pxDelayedTaskList, pcNameToQuery );
+			}
+
+			if( pxTCB == NULL )
+			{
+				pxTCB = prvSearchForNameWithinSingleList( ( List_t * ) pxOverflowDelayedTaskList, pcNameToQuery );
+			}
+
+			#if ( INCLUDE_vTaskSuspend == 1 )
+			{
+				if( pxTCB == NULL )
+				{
+					/* Search the suspended list. */
+					pxTCB = prvSearchForNameWithinSingleList( &xSuspendedTaskList, pcNameToQuery );
+				}
+			}
+			#endif
+
+			#if( INCLUDE_vTaskDelete == 1 )
+			{
+				if( pxTCB == NULL )
+				{
+					/* Search the deleted list. */
+					pxTCB = prvSearchForNameWithinSingleList( &xTasksWaitingTermination, pcNameToQuery );
+				}
+			}
+			#endif
+		}
+		( void ) xTaskResumeAll();
+
+		return pxTCB;
+	}
+
+#endif /* INCLUDE_xTaskGetHandle */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TRACE_FACILITY == 1 )
+
+	UBaseType_t uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray, const UBaseType_t uxArraySize, uint32_t * const pulTotalRunTime )
+	{
+	UBaseType_t uxTask = 0, uxQueue = configMAX_PRIORITIES;
+
+		vTaskSuspendAll();
+		{
+			/* Is there a space in the array for each task in the system? */
+			if( uxArraySize >= uxCurrentNumberOfTasks )
+			{
+				/* Fill in an TaskStatus_t structure with information on each
+				task in the Ready state. */
+				do
+				{
+					uxQueue--;
+					uxTask += prvListTasksWithinSingleList( &( pxTaskStatusArray[ uxTask ] ), &( pxReadyTasksLists[ uxQueue ] ), eReady );
+
+				} while( uxQueue > ( UBaseType_t ) tskIDLE_PRIORITY ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
+
+				/* Fill in an TaskStatus_t structure with information on each
+				task in the Blocked state. */
+				uxTask += prvListTasksWithinSingleList( &( pxTaskStatusArray[ uxTask ] ), ( List_t * ) pxDelayedTaskList, eBlocked );
+				uxTask += prvListTasksWithinSingleList( &( pxTaskStatusArray[ uxTask ] ), ( List_t * ) pxOverflowDelayedTaskList, eBlocked );
+
+				#if( INCLUDE_vTaskDelete == 1 )
+				{
+					/* Fill in an TaskStatus_t structure with information on
+					each task that has been deleted but not yet cleaned up. */
+					uxTask += prvListTasksWithinSingleList( &( pxTaskStatusArray[ uxTask ] ), &xTasksWaitingTermination, eDeleted );
+				}
+				#endif
+
+				#if ( INCLUDE_vTaskSuspend == 1 )
+				{
+					/* Fill in an TaskStatus_t structure with information on
+					each task in the Suspended state. */
+					uxTask += prvListTasksWithinSingleList( &( pxTaskStatusArray[ uxTask ] ), &xSuspendedTaskList, eSuspended );
+				}
+				#endif
+
+				#if ( configGENERATE_RUN_TIME_STATS == 1)
+				{
+					if( pulTotalRunTime != NULL )
+					{
+						#ifdef portALT_GET_RUN_TIME_COUNTER_VALUE
+							portALT_GET_RUN_TIME_COUNTER_VALUE( ( *pulTotalRunTime ) );
+						#else
+							*pulTotalRunTime = portGET_RUN_TIME_COUNTER_VALUE();
+						#endif
+					}
+				}
+				#else
+				{
+					if( pulTotalRunTime != NULL )
+					{
+						*pulTotalRunTime = 0;
+					}
+				}
+				#endif
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		( void ) xTaskResumeAll();
+
+		return uxTask;
+	}
+
+#endif /* configUSE_TRACE_FACILITY */
+/*----------------------------------------------------------*/
+
+#if ( INCLUDE_xTaskGetIdleTaskHandle == 1 )
+
+	TaskHandle_t xTaskGetIdleTaskHandle( void )
+	{
+		/* If xTaskGetIdleTaskHandle() is called before the scheduler has been
+		started, then xIdleTaskHandle will be NULL. */
+		configASSERT( ( xIdleTaskHandle != NULL ) );
+		return xIdleTaskHandle;
+	}
+
+#endif /* INCLUDE_xTaskGetIdleTaskHandle */
+/*----------------------------------------------------------*/
+
+/* This conditional compilation should use inequality to 0, not equality to 1.
+This is to ensure vTaskStepTick() is available when user defined low power mode
+implementations require configUSE_TICKLESS_IDLE to be set to a value other than
+1. */
+#if ( configUSE_TICKLESS_IDLE != 0 )
+
+	void vTaskStepTick( const TickType_t xTicksToJump )
+	{
+		/* Correct the tick count value after a period during which the tick
+		was suppressed.  Note this does *not* call the tick hook function for
+		each stepped tick. */
+		configASSERT( ( xTickCount + xTicksToJump ) <= xNextTaskUnblockTime );
+		xTickCount += xTicksToJump;
+		traceINCREASE_TICK_COUNT( xTicksToJump );
+	}
+
+#endif /* configUSE_TICKLESS_IDLE */
+/*----------------------------------------------------------*/
+
+BaseType_t xTaskCatchUpTicks( TickType_t xTicksToCatchUp )
+{
+BaseType_t xYieldRequired = pdFALSE;
+
+	/* Must not be called with the scheduler suspended as the implementation
+	relies on xPendedTicks being wound down to 0 in xTaskResumeAll(). */
+	configASSERT( uxSchedulerSuspended == 0 );
+
+	/* Use xPendedTicks to mimic xTicksToCatchUp number of ticks occurring when
+	the scheduler is suspended so the ticks are executed in xTaskResumeAll(). */
+	vTaskSuspendAll();
+	xPendedTicks += xTicksToCatchUp;
+	xYieldRequired = xTaskResumeAll();
+
+	return xYieldRequired;
+}
+/*----------------------------------------------------------*/
+
+#if ( INCLUDE_xTaskAbortDelay == 1 )
+
+	BaseType_t xTaskAbortDelay( TaskHandle_t xTask )
+	{
+	TCB_t *pxTCB = xTask;
+	BaseType_t xReturn;
+
+		configASSERT( pxTCB );
+
+		vTaskSuspendAll();
+		{
+			/* A task can only be prematurely removed from the Blocked state if
+			it is actually in the Blocked state. */
+			if( eTaskGetState( xTask ) == eBlocked )
+			{
+				xReturn = pdPASS;
+
+				/* Remove the reference to the task from the blocked list.  An
+				interrupt won't touch the xStateListItem because the
+				scheduler is suspended. */
+				( void ) uxListRemove( &( pxTCB->xStateListItem ) );
+
+				/* Is the task waiting on an event also?  If so remove it from
+				the event list too.  Interrupts can touch the event list item,
+				even though the scheduler is suspended, so a critical section
+				is used. */
+				taskENTER_CRITICAL();
+				{
+					if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) != NULL )
+					{
+						( void ) uxListRemove( &( pxTCB->xEventListItem ) );
+
+						/* This lets the task know it was forcibly removed from the
+						blocked state so it should not re-evaluate its block time and
+						then block again. */
+						pxTCB->ucDelayAborted = pdTRUE;
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				taskEXIT_CRITICAL();
+
+				/* Place the unblocked task into the appropriate ready list. */
+				prvAddTaskToReadyList( pxTCB );
+
+				/* A task being unblocked cannot cause an immediate context
+				switch if preemption is turned off. */
+				#if (  configUSE_PREEMPTION == 1 )
+				{
+					/* Preemption is on, but a context switch should only be
+					performed if the unblocked task has a priority that is
+					equal to or higher than the currently executing task. */
+					if( pxTCB->uxPriority > pxCurrentTCB->uxPriority )
+					{
+						/* Pend the yield to be performed when the scheduler
+						is unsuspended. */
+						xYieldPending = pdTRUE;
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				#endif /* configUSE_PREEMPTION */
+			}
+			else
+			{
+				xReturn = pdFAIL;
+			}
+		}
+		( void ) xTaskResumeAll();
+
+		return xReturn;
+	}
+
+#endif /* INCLUDE_xTaskAbortDelay */
+/*----------------------------------------------------------*/
+
+BaseType_t xTaskIncrementTick( void )
+{
+TCB_t * pxTCB;
+TickType_t xItemValue;
+BaseType_t xSwitchRequired = pdFALSE;
+
+	/* Called by the portable layer each time a tick interrupt occurs.
+	Increments the tick then checks to see if the new tick value will cause any
+	tasks to be unblocked. */
+	traceTASK_INCREMENT_TICK( xTickCount );
+	if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )
+	{
+		/* Minor optimisation.  The tick count cannot change in this
+		block. */
+		const TickType_t xConstTickCount = xTickCount + ( TickType_t ) 1;
+
+		/* Increment the RTOS tick, switching the delayed and overflowed
+		delayed lists if it wraps to 0. */
+		xTickCount = xConstTickCount;
+
+		if( xConstTickCount == ( TickType_t ) 0U ) /*lint !e774 'if' does not always evaluate to false as it is looking for an overflow. */
+		{
+			taskSWITCH_DELAYED_LISTS();
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+
+		/* See if this tick has made a timeout expire.  Tasks are stored in
+		the	queue in the order of their wake time - meaning once one task
+		has been found whose block time has not expired there is no need to
+		look any further down the list. */
+		if( xConstTickCount >= xNextTaskUnblockTime )
+		{
+			for( ;; )
+			{
+				if( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE )
+				{
+					/* The delayed list is empty.  Set xNextTaskUnblockTime
+					to the maximum possible value so it is extremely
+					unlikely that the
+					if( xTickCount >= xNextTaskUnblockTime ) test will pass
+					next time through. */
+					xNextTaskUnblockTime = portMAX_DELAY; /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
+					break;
+				}
+				else
+				{
+					/* The delayed list is not empty, get the value of the
+					item at the head of the delayed list.  This is the time
+					at which the task at the head of the delayed list must
+					be removed from the Blocked state. */
+					pxTCB = listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
+					xItemValue = listGET_LIST_ITEM_VALUE( &( pxTCB->xStateListItem ) );
+
+					if( xConstTickCount < xItemValue )
+					{
+						/* It is not time to unblock this item yet, but the
+						item value is the time at which the task at the head
+						of the blocked list must be removed from the Blocked
+						state -	so record the item value in
+						xNextTaskUnblockTime. */
+						xNextTaskUnblockTime = xItemValue;
+						break; /*lint !e9011 Code structure here is deedmed easier to understand with multiple breaks. */
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+
+					/* It is time to remove the item from the Blocked state. */
+					( void ) uxListRemove( &( pxTCB->xStateListItem ) );
+
+					/* Is the task waiting on an event also?  If so remove
+					it from the event list. */
+					if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) != NULL )
+					{
+						( void ) uxListRemove( &( pxTCB->xEventListItem ) );
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+
+					/* Place the unblocked task into the appropriate ready
+					list. */
+					prvAddTaskToReadyList( pxTCB );
+
+					/* A task being unblocked cannot cause an immediate
+					context switch if preemption is turned off. */
+					#if (  configUSE_PREEMPTION == 1 )
+					{
+						/* Preemption is on, but a context switch should
+						only be performed if the unblocked task has a
+						priority that is equal to or higher than the
+						currently executing task. */
+						if( pxTCB->uxPriority >= pxCurrentTCB->uxPriority )
+						{
+							xSwitchRequired = pdTRUE;
+						}
+						else
+						{
+							mtCOVERAGE_TEST_MARKER();
+						}
+					}
+					#endif /* configUSE_PREEMPTION */
+				}
+			}
+		}
+
+		/* Tasks of equal priority to the currently running task will share
+		processing time (time slice) if preemption is on, and the application
+		writer has not explicitly turned time slicing off. */
+		#if ( ( configUSE_PREEMPTION == 1 ) && ( configUSE_TIME_SLICING == 1 ) )
+		{
+			if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ pxCurrentTCB->uxPriority ] ) ) > ( UBaseType_t ) 1 )
+			{
+				xSwitchRequired = pdTRUE;
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		#endif /* ( ( configUSE_PREEMPTION == 1 ) && ( configUSE_TIME_SLICING == 1 ) ) */
+
+		#if ( configUSE_TICK_HOOK == 1 )
+		{
+			/* Guard against the tick hook being called when the pended tick
+			count is being unwound (when the scheduler is being unlocked). */
+			if( xPendedTicks == ( TickType_t ) 0 )
+			{
+				vApplicationTickHook();
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		#endif /* configUSE_TICK_HOOK */
+
+		#if ( configUSE_PREEMPTION == 1 )
+		{
+			if( xYieldPending != pdFALSE )
+			{
+				xSwitchRequired = pdTRUE;
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		#endif /* configUSE_PREEMPTION */
+	}
+	else
+	{
+		++xPendedTicks;
+
+		/* The tick hook gets called at regular intervals, even if the
+		scheduler is locked. */
+		#if ( configUSE_TICK_HOOK == 1 )
+		{
+			vApplicationTickHook();
+		}
+		#endif
+	}
+
+	return xSwitchRequired;
+}
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_APPLICATION_TASK_TAG == 1 )
+
+	void vTaskSetApplicationTaskTag( TaskHandle_t xTask, TaskHookFunction_t pxHookFunction )
+	{
+	TCB_t *xTCB;
+
+		/* If xTask is NULL then it is the task hook of the calling task that is
+		getting set. */
+		if( xTask == NULL )
+		{
+			xTCB = ( TCB_t * ) pxCurrentTCB;
+		}
+		else
+		{
+			xTCB = xTask;
+		}
+
+		/* Save the hook function in the TCB.  A critical section is required as
+		the value can be accessed from an interrupt. */
+		taskENTER_CRITICAL();
+		{
+			xTCB->pxTaskTag = pxHookFunction;
+		}
+		taskEXIT_CRITICAL();
+	}
+
+#endif /* configUSE_APPLICATION_TASK_TAG */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_APPLICATION_TASK_TAG == 1 )
+
+	TaskHookFunction_t xTaskGetApplicationTaskTag( TaskHandle_t xTask )
+	{
+	TCB_t *pxTCB;
+	TaskHookFunction_t xReturn;
+
+		/* If xTask is NULL then set the calling task's hook. */
+		pxTCB = prvGetTCBFromHandle( xTask );
+
+		/* Save the hook function in the TCB.  A critical section is required as
+		the value can be accessed from an interrupt. */
+		taskENTER_CRITICAL();
+		{
+			xReturn = pxTCB->pxTaskTag;
+		}
+		taskEXIT_CRITICAL();
+
+		return xReturn;
+	}
+
+#endif /* configUSE_APPLICATION_TASK_TAG */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_APPLICATION_TASK_TAG == 1 )
+
+	TaskHookFunction_t xTaskGetApplicationTaskTagFromISR( TaskHandle_t xTask )
+	{
+	TCB_t *pxTCB;
+	TaskHookFunction_t xReturn;
+	UBaseType_t uxSavedInterruptStatus;
+
+		/* If xTask is NULL then set the calling task's hook. */
+		pxTCB = prvGetTCBFromHandle( xTask );
+
+		/* Save the hook function in the TCB.  A critical section is required as
+		the value can be accessed from an interrupt. */
+		uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
+		{
+			xReturn = pxTCB->pxTaskTag;
+		}
+		portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
+
+		return xReturn;
+	}
+
+#endif /* configUSE_APPLICATION_TASK_TAG */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_APPLICATION_TASK_TAG == 1 )
+
+	BaseType_t xTaskCallApplicationTaskHook( TaskHandle_t xTask, void *pvParameter )
+	{
+	TCB_t *xTCB;
+	BaseType_t xReturn;
+
+		/* If xTask is NULL then we are calling our own task hook. */
+		if( xTask == NULL )
+		{
+			xTCB = pxCurrentTCB;
+		}
+		else
+		{
+			xTCB = xTask;
+		}
+
+		if( xTCB->pxTaskTag != NULL )
+		{
+			xReturn = xTCB->pxTaskTag( pvParameter );
+		}
+		else
+		{
+			xReturn = pdFAIL;
+		}
+
+		return xReturn;
+	}
+
+#endif /* configUSE_APPLICATION_TASK_TAG */
+/*-----------------------------------------------------------*/
+
+void vTaskSwitchContext( void )
+{
+	if( uxSchedulerSuspended != ( UBaseType_t ) pdFALSE )
+	{
+		/* The scheduler is currently suspended - do not allow a context
+		switch. */
+		xYieldPending = pdTRUE;
+	}
+	else
+	{
+		xYieldPending = pdFALSE;
+		traceTASK_SWITCHED_OUT();
+
+		#if ( configGENERATE_RUN_TIME_STATS == 1 )
+		{
+			#ifdef portALT_GET_RUN_TIME_COUNTER_VALUE
+				portALT_GET_RUN_TIME_COUNTER_VALUE( ulTotalRunTime );
+			#else
+				ulTotalRunTime = portGET_RUN_TIME_COUNTER_VALUE();
+			#endif
+
+			/* Add the amount of time the task has been running to the
+			accumulated time so far.  The time the task started running was
+			stored in ulTaskSwitchedInTime.  Note that there is no overflow
+			protection here so count values are only valid until the timer
+			overflows.  The guard against negative values is to protect
+			against suspect run time stat counter implementations - which
+			are provided by the application, not the kernel. */
+			if( ulTotalRunTime > ulTaskSwitchedInTime )
+			{
+				pxCurrentTCB->ulRunTimeCounter += ( ulTotalRunTime - ulTaskSwitchedInTime );
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+			ulTaskSwitchedInTime = ulTotalRunTime;
+		}
+		#endif /* configGENERATE_RUN_TIME_STATS */
+
+		/* Check for stack overflow, if configured. */
+		taskCHECK_FOR_STACK_OVERFLOW();
+
+		/* Before the currently running task is switched out, save its errno. */
+		#if( configUSE_POSIX_ERRNO == 1 )
+		{
+			pxCurrentTCB->iTaskErrno = FreeRTOS_errno;
+		}
+		#endif
+
+		/* Select a new task to run using either the generic C or port
+		optimised asm code. */
+		taskSELECT_HIGHEST_PRIORITY_TASK(); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
+		traceTASK_SWITCHED_IN();
+
+		/* After the new task is switched in, update the global errno. */
+		#if( configUSE_POSIX_ERRNO == 1 )
+		{
+			FreeRTOS_errno = pxCurrentTCB->iTaskErrno;
+		}
+		#endif
+
+		#if ( configUSE_NEWLIB_REENTRANT == 1 )
+		{
+			/* Switch Newlib's _impure_ptr variable to point to the _reent
+			structure specific to this task.
+			See the third party link http://www.nadler.com/embedded/newlibAndFreeRTOS.html
+			for additional information. */
+			_impure_ptr = &( pxCurrentTCB->xNewLib_reent );
+		}
+		#endif /* configUSE_NEWLIB_REENTRANT */
+	}
+}
+/*-----------------------------------------------------------*/
+
+void vTaskPlaceOnEventList( List_t * const pxEventList, const TickType_t xTicksToWait )
+{
+	configASSERT( pxEventList );
+
+	/* THIS FUNCTION MUST BE CALLED WITH EITHER INTERRUPTS DISABLED OR THE
+	SCHEDULER SUSPENDED AND THE QUEUE BEING ACCESSED LOCKED. */
+
+	/* Place the event list item of the TCB in the appropriate event list.
+	This is placed in the list in priority order so the highest priority task
+	is the first to be woken by the event.  The queue that contains the event
+	list is locked, preventing simultaneous access from interrupts. */
+	vListInsert( pxEventList, &( pxCurrentTCB->xEventListItem ) );
+
+	prvAddCurrentTaskToDelayedList( xTicksToWait, pdTRUE );
+}
+/*-----------------------------------------------------------*/
+
+void vTaskPlaceOnUnorderedEventList( List_t * pxEventList, const TickType_t xItemValue, const TickType_t xTicksToWait )
+{
+	configASSERT( pxEventList );
+
+	/* THIS FUNCTION MUST BE CALLED WITH THE SCHEDULER SUSPENDED.  It is used by
+	the event groups implementation. */
+	configASSERT( uxSchedulerSuspended != 0 );
+
+	/* Store the item value in the event list item.  It is safe to access the
+	event list item here as interrupts won't access the event list item of a
+	task that is not in the Blocked state. */
+	listSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xEventListItem ), xItemValue | taskEVENT_LIST_ITEM_VALUE_IN_USE );
+
+	/* Place the event list item of the TCB at the end of the appropriate event
+	list.  It is safe to access the event list here because it is part of an
+	event group implementation - and interrupts don't access event groups
+	directly (instead they access them indirectly by pending function calls to
+	the task level). */
+	vListInsertEnd( pxEventList, &( pxCurrentTCB->xEventListItem ) );
+
+	prvAddCurrentTaskToDelayedList( xTicksToWait, pdTRUE );
+}
+/*-----------------------------------------------------------*/
+
+#if( configUSE_TIMERS == 1 )
+
+	void vTaskPlaceOnEventListRestricted( List_t * const pxEventList, TickType_t xTicksToWait, const BaseType_t xWaitIndefinitely )
+	{
+		configASSERT( pxEventList );
+
+		/* This function should not be called by application code hence the
+		'Restricted' in its name.  It is not part of the public API.  It is
+		designed for use by kernel code, and has special calling requirements -
+		it should be called with the scheduler suspended. */
+
+
+		/* Place the event list item of the TCB in the appropriate event list.
+		In this case it is assume that this is the only task that is going to
+		be waiting on this event list, so the faster vListInsertEnd() function
+		can be used in place of vListInsert. */
+		vListInsertEnd( pxEventList, &( pxCurrentTCB->xEventListItem ) );
+
+		/* If the task should block indefinitely then set the block time to a
+		value that will be recognised as an indefinite delay inside the
+		prvAddCurrentTaskToDelayedList() function. */
+		if( xWaitIndefinitely != pdFALSE )
+		{
+			xTicksToWait = portMAX_DELAY;
+		}
+
+		traceTASK_DELAY_UNTIL( ( xTickCount + xTicksToWait ) );
+		prvAddCurrentTaskToDelayedList( xTicksToWait, xWaitIndefinitely );
+	}
+
+#endif /* configUSE_TIMERS */
+/*-----------------------------------------------------------*/
+
+BaseType_t xTaskRemoveFromEventList( const List_t * const pxEventList )
+{
+TCB_t *pxUnblockedTCB;
+BaseType_t xReturn;
+
+	/* THIS FUNCTION MUST BE CALLED FROM A CRITICAL SECTION.  It can also be
+	called from a critical section within an ISR. */
+
+	/* The event list is sorted in priority order, so the first in the list can
+	be removed as it is known to be the highest priority.  Remove the TCB from
+	the delayed list, and add it to the ready list.
+
+	If an event is for a queue that is locked then this function will never
+	get called - the lock count on the queue will get modified instead.  This
+	means exclusive access to the event list is guaranteed here.
+
+	This function assumes that a check has already been made to ensure that
+	pxEventList is not empty. */
+	pxUnblockedTCB = listGET_OWNER_OF_HEAD_ENTRY( pxEventList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
+	configASSERT( pxUnblockedTCB );
+	( void ) uxListRemove( &( pxUnblockedTCB->xEventListItem ) );
+
+	if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )
+	{
+		( void ) uxListRemove( &( pxUnblockedTCB->xStateListItem ) );
+		prvAddTaskToReadyList( pxUnblockedTCB );
+
+		#if( configUSE_TICKLESS_IDLE != 0 )
+		{
+			/* If a task is blocked on a kernel object then xNextTaskUnblockTime
+			might be set to the blocked task's time out time.  If the task is
+			unblocked for a reason other than a timeout xNextTaskUnblockTime is
+			normally left unchanged, because it is automatically reset to a new
+			value when the tick count equals xNextTaskUnblockTime.  However if
+			tickless idling is used it might be more important to enter sleep mode
+			at the earliest possible time - so reset xNextTaskUnblockTime here to
+			ensure it is updated at the earliest possible time. */
+			prvResetNextTaskUnblockTime();
+		}
+		#endif
+	}
+	else
+	{
+		/* The delayed and ready lists cannot be accessed, so hold this task
+		pending until the scheduler is resumed. */
+		vListInsertEnd( &( xPendingReadyList ), &( pxUnblockedTCB->xEventListItem ) );
+	}
+
+	if( pxUnblockedTCB->uxPriority > pxCurrentTCB->uxPriority )
+	{
+		/* Return true if the task removed from the event list has a higher
+		priority than the calling task.  This allows the calling task to know if
+		it should force a context switch now. */
+		xReturn = pdTRUE;
+
+		/* Mark that a yield is pending in case the user is not using the
+		"xHigherPriorityTaskWoken" parameter to an ISR safe FreeRTOS function. */
+		xYieldPending = pdTRUE;
+	}
+	else
+	{
+		xReturn = pdFALSE;
+	}
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+void vTaskRemoveFromUnorderedEventList( ListItem_t * pxEventListItem, const TickType_t xItemValue )
+{
+TCB_t *pxUnblockedTCB;
+
+	/* THIS FUNCTION MUST BE CALLED WITH THE SCHEDULER SUSPENDED.  It is used by
+	the event flags implementation. */
+	configASSERT( uxSchedulerSuspended != pdFALSE );
+
+	/* Store the new item value in the event list. */
+	listSET_LIST_ITEM_VALUE( pxEventListItem, xItemValue | taskEVENT_LIST_ITEM_VALUE_IN_USE );
+
+	/* Remove the event list form the event flag.  Interrupts do not access
+	event flags. */
+	pxUnblockedTCB = listGET_LIST_ITEM_OWNER( pxEventListItem ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
+	configASSERT( pxUnblockedTCB );
+	( void ) uxListRemove( pxEventListItem );
+
+	#if( configUSE_TICKLESS_IDLE != 0 )
+	{
+		/* If a task is blocked on a kernel object then xNextTaskUnblockTime
+		might be set to the blocked task's time out time.  If the task is
+		unblocked for a reason other than a timeout xNextTaskUnblockTime is
+		normally left unchanged, because it is automatically reset to a new
+		value when the tick count equals xNextTaskUnblockTime.  However if
+		tickless idling is used it might be more important to enter sleep mode
+		at the earliest possible time - so reset xNextTaskUnblockTime here to
+		ensure it is updated at the earliest possible time. */
+		prvResetNextTaskUnblockTime();
+	}
+	#endif
+
+	/* Remove the task from the delayed list and add it to the ready list.  The
+	scheduler is suspended so interrupts will not be accessing the ready
+	lists. */
+	( void ) uxListRemove( &( pxUnblockedTCB->xStateListItem ) );
+	prvAddTaskToReadyList( pxUnblockedTCB );
+
+	if( pxUnblockedTCB->uxPriority > pxCurrentTCB->uxPriority )
+	{
+		/* The unblocked task has a priority above that of the calling task, so
+		a context switch is required.  This function is called with the
+		scheduler suspended so xYieldPending is set so the context switch
+		occurs immediately that the scheduler is resumed (unsuspended). */
+		xYieldPending = pdTRUE;
+	}
+}
+/*-----------------------------------------------------------*/
+
+void vTaskSetTimeOutState( TimeOut_t * const pxTimeOut )
+{
+	configASSERT( pxTimeOut );
+	taskENTER_CRITICAL();
+	{
+		pxTimeOut->xOverflowCount = xNumOfOverflows;
+		pxTimeOut->xTimeOnEntering = xTickCount;
+	}
+	taskEXIT_CRITICAL();
+}
+/*-----------------------------------------------------------*/
+
+void vTaskInternalSetTimeOutState( TimeOut_t * const pxTimeOut )
+{
+	/* For internal use only as it does not use a critical section. */
+	pxTimeOut->xOverflowCount = xNumOfOverflows;
+	pxTimeOut->xTimeOnEntering = xTickCount;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, TickType_t * const pxTicksToWait )
+{
+BaseType_t xReturn;
+
+	configASSERT( pxTimeOut );
+	configASSERT( pxTicksToWait );
+
+	taskENTER_CRITICAL();
+	{
+		/* Minor optimisation.  The tick count cannot change in this block. */
+		const TickType_t xConstTickCount = xTickCount;
+		const TickType_t xElapsedTime = xConstTickCount - pxTimeOut->xTimeOnEntering;
+
+		#if( INCLUDE_xTaskAbortDelay == 1 )
+			if( pxCurrentTCB->ucDelayAborted != ( uint8_t ) pdFALSE )
+			{
+				/* The delay was aborted, which is not the same as a time out,
+				but has the same result. */
+				pxCurrentTCB->ucDelayAborted = pdFALSE;
+				xReturn = pdTRUE;
+			}
+			else
+		#endif
+
+		#if ( INCLUDE_vTaskSuspend == 1 )
+			if( *pxTicksToWait == portMAX_DELAY )
+			{
+				/* If INCLUDE_vTaskSuspend is set to 1 and the block time
+				specified is the maximum block time then the task should block
+				indefinitely, and therefore never time out. */
+				xReturn = pdFALSE;
+			}
+			else
+		#endif
+
+		if( ( xNumOfOverflows != pxTimeOut->xOverflowCount ) && ( xConstTickCount >= pxTimeOut->xTimeOnEntering ) ) /*lint !e525 Indentation preferred as is to make code within pre-processor directives clearer. */
+		{
+			/* The tick count is greater than the time at which
+			vTaskSetTimeout() was called, but has also overflowed since
+			vTaskSetTimeOut() was called.  It must have wrapped all the way
+			around and gone past again. This passed since vTaskSetTimeout()
+			was called. */
+			xReturn = pdTRUE;
+		}
+		else if( xElapsedTime < *pxTicksToWait ) /*lint !e961 Explicit casting is only redundant with some compilers, whereas others require it to prevent integer conversion errors. */
+		{
+			/* Not a genuine timeout. Adjust parameters for time remaining. */
+			*pxTicksToWait -= xElapsedTime;
+			vTaskInternalSetTimeOutState( pxTimeOut );
+			xReturn = pdFALSE;
+		}
+		else
+		{
+			*pxTicksToWait = 0;
+			xReturn = pdTRUE;
+		}
+	}
+	taskEXIT_CRITICAL();
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+void vTaskMissedYield( void )
+{
+	xYieldPending = pdTRUE;
+}
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TRACE_FACILITY == 1 )
+
+	UBaseType_t uxTaskGetTaskNumber( TaskHandle_t xTask )
+	{
+	UBaseType_t uxReturn;
+	TCB_t const *pxTCB;
+
+		if( xTask != NULL )
+		{
+			pxTCB = xTask;
+			uxReturn = pxTCB->uxTaskNumber;
+		}
+		else
+		{
+			uxReturn = 0U;
+		}
+
+		return uxReturn;
+	}
+
+#endif /* configUSE_TRACE_FACILITY */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TRACE_FACILITY == 1 )
+
+	void vTaskSetTaskNumber( TaskHandle_t xTask, const UBaseType_t uxHandle )
+	{
+	TCB_t * pxTCB;
+
+		if( xTask != NULL )
+		{
+			pxTCB = xTask;
+			pxTCB->uxTaskNumber = uxHandle;
+		}
+	}
+
+#endif /* configUSE_TRACE_FACILITY */
+
+/*
+ * -----------------------------------------------------------
+ * The Idle task.
+ * ----------------------------------------------------------
+ *
+ * The portTASK_FUNCTION() macro is used to allow port/compiler specific
+ * language extensions.  The equivalent prototype for this function is:
+ *
+ * void prvIdleTask( void *pvParameters );
+ *
+ */
+static portTASK_FUNCTION( prvIdleTask, pvParameters )
+{
+	/* Stop warnings. */
+	( void ) pvParameters;
+
+	/** THIS IS THE RTOS IDLE TASK - WHICH IS CREATED AUTOMATICALLY WHEN THE
+	SCHEDULER IS STARTED. **/
+
+	/* In case a task that has a secure context deletes itself, in which case
+	the idle task is responsible for deleting the task's secure context, if
+	any. */
+	portALLOCATE_SECURE_CONTEXT( configMINIMAL_SECURE_STACK_SIZE );
+
+	for( ;; )
+	{
+		/* See if any tasks have deleted themselves - if so then the idle task
+		is responsible for freeing the deleted task's TCB and stack. */
+		prvCheckTasksWaitingTermination();
+
+		#if ( configUSE_PREEMPTION == 0 )
+		{
+			/* If we are not using preemption we keep forcing a task switch to
+			see if any other task has become available.  If we are using
+			preemption we don't need to do this as any task becoming available
+			will automatically get the processor anyway. */
+			taskYIELD();
+		}
+		#endif /* configUSE_PREEMPTION */
+
+		#if ( ( configUSE_PREEMPTION == 1 ) && ( configIDLE_SHOULD_YIELD == 1 ) )
+		{
+			/* When using preemption tasks of equal priority will be
+			timesliced.  If a task that is sharing the idle priority is ready
+			to run then the idle task should yield before the end of the
+			timeslice.
+
+			A critical region is not required here as we are just reading from
+			the list, and an occasional incorrect value will not matter.  If
+			the ready list at the idle priority contains more than one task
+			then a task other than the idle task is ready to execute. */
+			if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ tskIDLE_PRIORITY ] ) ) > ( UBaseType_t ) 1 )
+			{
+				taskYIELD();
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		#endif /* ( ( configUSE_PREEMPTION == 1 ) && ( configIDLE_SHOULD_YIELD == 1 ) ) */
+
+		#if ( configUSE_IDLE_HOOK == 1 )
+		{
+			extern void vApplicationIdleHook( void );
+
+			/* Call the user defined function from within the idle task.  This
+			allows the application designer to add background functionality
+			without the overhead of a separate task.
+			NOTE: vApplicationIdleHook() MUST NOT, UNDER ANY CIRCUMSTANCES,
+			CALL A FUNCTION THAT MIGHT BLOCK. */
+			vApplicationIdleHook();
+		}
+		#endif /* configUSE_IDLE_HOOK */
+
+		/* This conditional compilation should use inequality to 0, not equality
+		to 1.  This is to ensure portSUPPRESS_TICKS_AND_SLEEP() is called when
+		user defined low power mode	implementations require
+		configUSE_TICKLESS_IDLE to be set to a value other than 1. */
+		#if ( configUSE_TICKLESS_IDLE != 0 )
+		{
+		TickType_t xExpectedIdleTime;
+
+			/* It is not desirable to suspend then resume the scheduler on
+			each iteration of the idle task.  Therefore, a preliminary
+			test of the expected idle time is performed without the
+			scheduler suspended.  The result here is not necessarily
+			valid. */
+			xExpectedIdleTime = prvGetExpectedIdleTime();
+
+			if( xExpectedIdleTime >= configEXPECTED_IDLE_TIME_BEFORE_SLEEP )
+			{
+				vTaskSuspendAll();
+				{
+					/* Now the scheduler is suspended, the expected idle
+					time can be sampled again, and this time its value can
+					be used. */
+					configASSERT( xNextTaskUnblockTime >= xTickCount );
+					xExpectedIdleTime = prvGetExpectedIdleTime();
+
+					/* Define the following macro to set xExpectedIdleTime to 0
+					if the application does not want
+					portSUPPRESS_TICKS_AND_SLEEP() to be called. */
+					configPRE_SUPPRESS_TICKS_AND_SLEEP_PROCESSING( xExpectedIdleTime );
+
+					if( xExpectedIdleTime >= configEXPECTED_IDLE_TIME_BEFORE_SLEEP )
+					{
+						traceLOW_POWER_IDLE_BEGIN();
+						portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime );
+						traceLOW_POWER_IDLE_END();
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				( void ) xTaskResumeAll();
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		#endif /* configUSE_TICKLESS_IDLE */
+	}
+}
+/*-----------------------------------------------------------*/
+
+#if( configUSE_TICKLESS_IDLE != 0 )
+
+	eSleepModeStatus eTaskConfirmSleepModeStatus( void )
+	{
+	/* The idle task exists in addition to the application tasks. */
+	const UBaseType_t uxNonApplicationTasks = 1;
+	eSleepModeStatus eReturn = eStandardSleep;
+
+		/* This function must be called from a critical section. */
+
+		if( listCURRENT_LIST_LENGTH( &xPendingReadyList ) != 0 )
+		{
+			/* A task was made ready while the scheduler was suspended. */
+			eReturn = eAbortSleep;
+		}
+		else if( xYieldPending != pdFALSE )
+		{
+			/* A yield was pended while the scheduler was suspended. */
+			eReturn = eAbortSleep;
+		}
+		else
+		{
+			/* If all the tasks are in the suspended list (which might mean they
+			have an infinite block time rather than actually being suspended)
+			then it is safe to turn all clocks off and just wait for external
+			interrupts. */
+			if( listCURRENT_LIST_LENGTH( &xSuspendedTaskList ) == ( uxCurrentNumberOfTasks - uxNonApplicationTasks ) )
+			{
+				eReturn = eNoTasksWaitingTimeout;
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+
+		return eReturn;
+	}
+
+#endif /* configUSE_TICKLESS_IDLE */
+/*-----------------------------------------------------------*/
+
+#if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 )
+
+	void vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet, BaseType_t xIndex, void *pvValue )
+	{
+	TCB_t *pxTCB;
+
+		if( xIndex < configNUM_THREAD_LOCAL_STORAGE_POINTERS )
+		{
+			pxTCB = prvGetTCBFromHandle( xTaskToSet );
+			configASSERT( pxTCB != NULL );
+			pxTCB->pvThreadLocalStoragePointers[ xIndex ] = pvValue;
+		}
+	}
+
+#endif /* configNUM_THREAD_LOCAL_STORAGE_POINTERS */
+/*-----------------------------------------------------------*/
+
+#if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 )
+
+	void *pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery, BaseType_t xIndex )
+	{
+	void *pvReturn = NULL;
+	TCB_t *pxTCB;
+
+		if( xIndex < configNUM_THREAD_LOCAL_STORAGE_POINTERS )
+		{
+			pxTCB = prvGetTCBFromHandle( xTaskToQuery );
+			pvReturn = pxTCB->pvThreadLocalStoragePointers[ xIndex ];
+		}
+		else
+		{
+			pvReturn = NULL;
+		}
+
+		return pvReturn;
+	}
+
+#endif /* configNUM_THREAD_LOCAL_STORAGE_POINTERS */
+/*-----------------------------------------------------------*/
+
+#if ( portUSING_MPU_WRAPPERS == 1 )
+
+	void vTaskAllocateMPURegions( TaskHandle_t xTaskToModify, const MemoryRegion_t * const xRegions )
+	{
+	TCB_t *pxTCB;
+
+		/* If null is passed in here then we are modifying the MPU settings of
+		the calling task. */
+		pxTCB = prvGetTCBFromHandle( xTaskToModify );
+
+		vPortStoreTaskMPUSettings( &( pxTCB->xMPUSettings ), xRegions, NULL, 0 );
+	}
+
+#endif /* portUSING_MPU_WRAPPERS */
+/*-----------------------------------------------------------*/
+
+static void prvInitialiseTaskLists( void )
+{
+UBaseType_t uxPriority;
+
+	for( uxPriority = ( UBaseType_t ) 0U; uxPriority < ( UBaseType_t ) configMAX_PRIORITIES; uxPriority++ )
+	{
+		vListInitialise( &( pxReadyTasksLists[ uxPriority ] ) );
+	}
+
+	vListInitialise( &xDelayedTaskList1 );
+	vListInitialise( &xDelayedTaskList2 );
+	vListInitialise( &xPendingReadyList );
+
+	#if ( INCLUDE_vTaskDelete == 1 )
+	{
+		vListInitialise( &xTasksWaitingTermination );
+	}
+	#endif /* INCLUDE_vTaskDelete */
+
+	#if ( INCLUDE_vTaskSuspend == 1 )
+	{
+		vListInitialise( &xSuspendedTaskList );
+	}
+	#endif /* INCLUDE_vTaskSuspend */
+
+	/* Start with pxDelayedTaskList using list1 and the pxOverflowDelayedTaskList
+	using list2. */
+	pxDelayedTaskList = &xDelayedTaskList1;
+	pxOverflowDelayedTaskList = &xDelayedTaskList2;
+}
+/*-----------------------------------------------------------*/
+
+static void prvCheckTasksWaitingTermination( void )
+{
+
+	/** THIS FUNCTION IS CALLED FROM THE RTOS IDLE TASK **/
+
+	#if ( INCLUDE_vTaskDelete == 1 )
+	{
+		TCB_t *pxTCB;
+
+		/* uxDeletedTasksWaitingCleanUp is used to prevent taskENTER_CRITICAL()
+		being called too often in the idle task. */
+		while( uxDeletedTasksWaitingCleanUp > ( UBaseType_t ) 0U )
+		{
+			taskENTER_CRITICAL();
+			{
+				pxTCB = listGET_OWNER_OF_HEAD_ENTRY( ( &xTasksWaitingTermination ) ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
+				( void ) uxListRemove( &( pxTCB->xStateListItem ) );
+				--uxCurrentNumberOfTasks;
+				--uxDeletedTasksWaitingCleanUp;
+			}
+			taskEXIT_CRITICAL();
+
+			prvDeleteTCB( pxTCB );
+		}
+	}
+	#endif /* INCLUDE_vTaskDelete */
+}
+/*-----------------------------------------------------------*/
+
+#if( configUSE_TRACE_FACILITY == 1 )
+
+	void vTaskGetInfo( TaskHandle_t xTask, TaskStatus_t *pxTaskStatus, BaseType_t xGetFreeStackSpace, eTaskState eState )
+	{
+	TCB_t *pxTCB;
+
+		/* xTask is NULL then get the state of the calling task. */
+		pxTCB = prvGetTCBFromHandle( xTask );
+
+		pxTaskStatus->xHandle = ( TaskHandle_t ) pxTCB;
+		pxTaskStatus->pcTaskName = ( const char * ) &( pxTCB->pcTaskName [ 0 ] );
+		pxTaskStatus->uxCurrentPriority = pxTCB->uxPriority;
+		pxTaskStatus->pxStackBase = pxTCB->pxStack;
+		pxTaskStatus->xTaskNumber = pxTCB->uxTCBNumber;
+
+		#if ( configUSE_MUTEXES == 1 )
+		{
+			pxTaskStatus->uxBasePriority = pxTCB->uxBasePriority;
+		}
+		#else
+		{
+			pxTaskStatus->uxBasePriority = 0;
+		}
+		#endif
+
+		#if ( configGENERATE_RUN_TIME_STATS == 1 )
+		{
+			pxTaskStatus->ulRunTimeCounter = pxTCB->ulRunTimeCounter;
+		}
+		#else
+		{
+			pxTaskStatus->ulRunTimeCounter = 0;
+		}
+		#endif
+
+		/* Obtaining the task state is a little fiddly, so is only done if the
+		value of eState passed into this function is eInvalid - otherwise the
+		state is just set to whatever is passed in. */
+		if( eState != eInvalid )
+		{
+			if( pxTCB == pxCurrentTCB )
+			{
+				pxTaskStatus->eCurrentState = eRunning;
+			}
+			else
+			{
+				pxTaskStatus->eCurrentState = eState;
+
+				#if ( INCLUDE_vTaskSuspend == 1 )
+				{
+					/* If the task is in the suspended list then there is a
+					chance it is actually just blocked indefinitely - so really
+					it should be reported as being in the Blocked state. */
+					if( eState == eSuspended )
+					{
+						vTaskSuspendAll();
+						{
+							if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) != NULL )
+							{
+								pxTaskStatus->eCurrentState = eBlocked;
+							}
+						}
+						( void ) xTaskResumeAll();
+					}
+				}
+				#endif /* INCLUDE_vTaskSuspend */
+			}
+		}
+		else
+		{
+			pxTaskStatus->eCurrentState = eTaskGetState( pxTCB );
+		}
+
+		/* Obtaining the stack space takes some time, so the xGetFreeStackSpace
+		parameter is provided to allow it to be skipped. */
+		if( xGetFreeStackSpace != pdFALSE )
+		{
+			#if ( portSTACK_GROWTH > 0 )
+			{
+				pxTaskStatus->usStackHighWaterMark = prvTaskCheckFreeStackSpace( ( uint8_t * ) pxTCB->pxEndOfStack );
+			}
+			#else
+			{
+				pxTaskStatus->usStackHighWaterMark = prvTaskCheckFreeStackSpace( ( uint8_t * ) pxTCB->pxStack );
+			}
+			#endif
+		}
+		else
+		{
+			pxTaskStatus->usStackHighWaterMark = 0;
+		}
+	}
+
+#endif /* configUSE_TRACE_FACILITY */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TRACE_FACILITY == 1 )
+
+	static UBaseType_t prvListTasksWithinSingleList( TaskStatus_t *pxTaskStatusArray, List_t *pxList, eTaskState eState )
+	{
+	configLIST_VOLATILE TCB_t *pxNextTCB, *pxFirstTCB;
+	UBaseType_t uxTask = 0;
+
+		if( listCURRENT_LIST_LENGTH( pxList ) > ( UBaseType_t ) 0 )
+		{
+			listGET_OWNER_OF_NEXT_ENTRY( pxFirstTCB, pxList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
+
+			/* Populate an TaskStatus_t structure within the
+			pxTaskStatusArray array for each task that is referenced from
+			pxList.  See the definition of TaskStatus_t in task.h for the
+			meaning of each TaskStatus_t structure member. */
+			do
+			{
+				listGET_OWNER_OF_NEXT_ENTRY( pxNextTCB, pxList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
+				vTaskGetInfo( ( TaskHandle_t ) pxNextTCB, &( pxTaskStatusArray[ uxTask ] ), pdTRUE, eState );
+				uxTask++;
+			} while( pxNextTCB != pxFirstTCB );
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+
+		return uxTask;
+	}
+
+#endif /* configUSE_TRACE_FACILITY */
+/*-----------------------------------------------------------*/
+
+#if ( ( configUSE_TRACE_FACILITY == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 ) )
+
+	static configSTACK_DEPTH_TYPE prvTaskCheckFreeStackSpace( const uint8_t * pucStackByte )
+	{
+	uint32_t ulCount = 0U;
+
+		while( *pucStackByte == ( uint8_t ) tskSTACK_FILL_BYTE )
+		{
+			pucStackByte -= portSTACK_GROWTH;
+			ulCount++;
+		}
+
+		ulCount /= ( uint32_t ) sizeof( StackType_t ); /*lint !e961 Casting is not redundant on smaller architectures. */
+
+		return ( configSTACK_DEPTH_TYPE ) ulCount;
+	}
+
+#endif /* ( ( configUSE_TRACE_FACILITY == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 )
+
+	/* uxTaskGetStackHighWaterMark() and uxTaskGetStackHighWaterMark2() are the
+	same except for their return type.  Using configSTACK_DEPTH_TYPE allows the
+	user to determine the return type.  It gets around the problem of the value
+	overflowing on 8-bit types without breaking backward compatibility for
+	applications that expect an 8-bit return type. */
+	configSTACK_DEPTH_TYPE uxTaskGetStackHighWaterMark2( TaskHandle_t xTask )
+	{
+	TCB_t *pxTCB;
+	uint8_t *pucEndOfStack;
+	configSTACK_DEPTH_TYPE uxReturn;
+
+		/* uxTaskGetStackHighWaterMark() and uxTaskGetStackHighWaterMark2() are
+		the same except for their return type.  Using configSTACK_DEPTH_TYPE
+		allows the user to determine the return type.  It gets around the
+		problem of the value overflowing on 8-bit types without breaking
+		backward compatibility for applications that expect an 8-bit return
+		type. */
+
+		pxTCB = prvGetTCBFromHandle( xTask );
+
+		#if portSTACK_GROWTH < 0
+		{
+			pucEndOfStack = ( uint8_t * ) pxTCB->pxStack;
+		}
+		#else
+		{
+			pucEndOfStack = ( uint8_t * ) pxTCB->pxEndOfStack;
+		}
+		#endif
+
+		uxReturn = prvTaskCheckFreeStackSpace( pucEndOfStack );
+
+		return uxReturn;
+	}
+
+#endif /* INCLUDE_uxTaskGetStackHighWaterMark2 */
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_uxTaskGetStackHighWaterMark == 1 )
+
+	UBaseType_t uxTaskGetStackHighWaterMark( TaskHandle_t xTask )
+	{
+	TCB_t *pxTCB;
+	uint8_t *pucEndOfStack;
+	UBaseType_t uxReturn;
+
+		pxTCB = prvGetTCBFromHandle( xTask );
+
+		#if portSTACK_GROWTH < 0
+		{
+			pucEndOfStack = ( uint8_t * ) pxTCB->pxStack;
+		}
+		#else
+		{
+			pucEndOfStack = ( uint8_t * ) pxTCB->pxEndOfStack;
+		}
+		#endif
+
+		uxReturn = ( UBaseType_t ) prvTaskCheckFreeStackSpace( pucEndOfStack );
+
+		return uxReturn;
+	}
+
+#endif /* INCLUDE_uxTaskGetStackHighWaterMark */
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_vTaskDelete == 1 )
+
+	static void prvDeleteTCB( TCB_t *pxTCB )
+	{
+		/* This call is required specifically for the TriCore port.  It must be
+		above the vPortFree() calls.  The call is also used by ports/demos that
+		want to allocate and clean RAM statically. */
+		portCLEAN_UP_TCB( pxTCB );
+
+		/* Free up the memory allocated by the scheduler for the task.  It is up
+		to the task to free any memory allocated at the application level.
+		See the third party link http://www.nadler.com/embedded/newlibAndFreeRTOS.html
+		for additional information. */
+		#if ( configUSE_NEWLIB_REENTRANT == 1 )
+		{
+			_reclaim_reent( &( pxTCB->xNewLib_reent ) );
+		}
+		#endif /* configUSE_NEWLIB_REENTRANT */
+
+		#if( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 0 ) && ( portUSING_MPU_WRAPPERS == 0 ) )
+		{
+			/* The task can only have been allocated dynamically - free both
+			the stack and TCB. */
+			vPortFree( pxTCB->pxStack );
+			vPortFree( pxTCB );
+		}
+		#elif( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e731 !e9029 Macro has been consolidated for readability reasons. */
+		{
+			/* The task could have been allocated statically or dynamically, so
+			check what was statically allocated before trying to free the
+			memory. */
+			if( pxTCB->ucStaticallyAllocated == tskDYNAMICALLY_ALLOCATED_STACK_AND_TCB )
+			{
+				/* Both the stack and TCB were allocated dynamically, so both
+				must be freed. */
+				vPortFree( pxTCB->pxStack );
+				vPortFree( pxTCB );
+			}
+			else if( pxTCB->ucStaticallyAllocated == tskSTATICALLY_ALLOCATED_STACK_ONLY )
+			{
+				/* Only the stack was statically allocated, so the TCB is the
+				only memory that must be freed. */
+				vPortFree( pxTCB );
+			}
+			else
+			{
+				/* Neither the stack nor the TCB were allocated dynamically, so
+				nothing needs to be freed. */
+				configASSERT( pxTCB->ucStaticallyAllocated == tskSTATICALLY_ALLOCATED_STACK_AND_TCB	);
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
+	}
+
+#endif /* INCLUDE_vTaskDelete */
+/*-----------------------------------------------------------*/
+
+static void prvResetNextTaskUnblockTime( void )
+{
+TCB_t *pxTCB;
+
+	if( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE )
+	{
+		/* The new current delayed list is empty.  Set xNextTaskUnblockTime to
+		the maximum possible value so it is	extremely unlikely that the
+		if( xTickCount >= xNextTaskUnblockTime ) test will pass until
+		there is an item in the delayed list. */
+		xNextTaskUnblockTime = portMAX_DELAY;
+	}
+	else
+	{
+		/* The new current delayed list is not empty, get the value of
+		the item at the head of the delayed list.  This is the time at
+		which the task at the head of the delayed list should be removed
+		from the Blocked state. */
+		( pxTCB ) = listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
+		xNextTaskUnblockTime = listGET_LIST_ITEM_VALUE( &( ( pxTCB )->xStateListItem ) );
+	}
+}
+/*-----------------------------------------------------------*/
+
+#if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) )
+
+	TaskHandle_t xTaskGetCurrentTaskHandle( void )
+	{
+	TaskHandle_t xReturn;
+
+		/* A critical section is not required as this is not called from
+		an interrupt and the current TCB will always be the same for any
+		individual execution thread. */
+		xReturn = pxCurrentTCB;
+
+		return xReturn;
+	}
+
+#endif /* ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
+
+	BaseType_t xTaskGetSchedulerState( void )
+	{
+	BaseType_t xReturn;
+
+		if( xSchedulerRunning == pdFALSE )
+		{
+			xReturn = taskSCHEDULER_NOT_STARTED;
+		}
+		else
+		{
+			if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )
+			{
+				xReturn = taskSCHEDULER_RUNNING;
+			}
+			else
+			{
+				xReturn = taskSCHEDULER_SUSPENDED;
+			}
+		}
+
+		return xReturn;
+	}
+
+#endif /* ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_MUTEXES == 1 )
+
+	BaseType_t xTaskPriorityInherit( TaskHandle_t const pxMutexHolder )
+	{
+	TCB_t * const pxMutexHolderTCB = pxMutexHolder;
+	BaseType_t xReturn = pdFALSE;
+
+		/* If the mutex was given back by an interrupt while the queue was
+		locked then the mutex holder might now be NULL.  _RB_ Is this still
+		needed as interrupts can no longer use mutexes? */
+		if( pxMutexHolder != NULL )
+		{
+			/* If the holder of the mutex has a priority below the priority of
+			the task attempting to obtain the mutex then it will temporarily
+			inherit the priority of the task attempting to obtain the mutex. */
+			if( pxMutexHolderTCB->uxPriority < pxCurrentTCB->uxPriority )
+			{
+				/* Adjust the mutex holder state to account for its new
+				priority.  Only reset the event list item value if the value is
+				not being used for anything else. */
+				if( ( listGET_LIST_ITEM_VALUE( &( pxMutexHolderTCB->xEventListItem ) ) & taskEVENT_LIST_ITEM_VALUE_IN_USE ) == 0UL )
+				{
+					listSET_LIST_ITEM_VALUE( &( pxMutexHolderTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) pxCurrentTCB->uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+
+				/* If the task being modified is in the ready state it will need
+				to be moved into a new list. */
+				if( listIS_CONTAINED_WITHIN( &( pxReadyTasksLists[ pxMutexHolderTCB->uxPriority ] ), &( pxMutexHolderTCB->xStateListItem ) ) != pdFALSE )
+				{
+					if( uxListRemove( &( pxMutexHolderTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )
+					{
+						/* It is known that the task is in its ready list so
+						there is no need to check again and the port level
+						reset macro can be called directly. */
+						portRESET_READY_PRIORITY( pxMutexHolderTCB->uxPriority, uxTopReadyPriority );
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+
+					/* Inherit the priority before being moved into the new list. */
+					pxMutexHolderTCB->uxPriority = pxCurrentTCB->uxPriority;
+					prvAddTaskToReadyList( pxMutexHolderTCB );
+				}
+				else
+				{
+					/* Just inherit the priority. */
+					pxMutexHolderTCB->uxPriority = pxCurrentTCB->uxPriority;
+				}
+
+				traceTASK_PRIORITY_INHERIT( pxMutexHolderTCB, pxCurrentTCB->uxPriority );
+
+				/* Inheritance occurred. */
+				xReturn = pdTRUE;
+			}
+			else
+			{
+				if( pxMutexHolderTCB->uxBasePriority < pxCurrentTCB->uxPriority )
+				{
+					/* The base priority of the mutex holder is lower than the
+					priority of the task attempting to take the mutex, but the
+					current priority of the mutex holder is not lower than the
+					priority of the task attempting to take the mutex.
+					Therefore the mutex holder must have already inherited a
+					priority, but inheritance would have occurred if that had
+					not been the case. */
+					xReturn = pdTRUE;
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+
+		return xReturn;
+	}
+
+#endif /* configUSE_MUTEXES */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_MUTEXES == 1 )
+
+	BaseType_t xTaskPriorityDisinherit( TaskHandle_t const pxMutexHolder )
+	{
+	TCB_t * const pxTCB = pxMutexHolder;
+	BaseType_t xReturn = pdFALSE;
+
+		if( pxMutexHolder != NULL )
+		{
+			/* A task can only have an inherited priority if it holds the mutex.
+			If the mutex is held by a task then it cannot be given from an
+			interrupt, and if a mutex is given by the holding task then it must
+			be the running state task. */
+			configASSERT( pxTCB == pxCurrentTCB );
+			configASSERT( pxTCB->uxMutexesHeld );
+			( pxTCB->uxMutexesHeld )--;
+
+			/* Has the holder of the mutex inherited the priority of another
+			task? */
+			if( pxTCB->uxPriority != pxTCB->uxBasePriority )
+			{
+				/* Only disinherit if no other mutexes are held. */
+				if( pxTCB->uxMutexesHeld == ( UBaseType_t ) 0 )
+				{
+					/* A task can only have an inherited priority if it holds
+					the mutex.  If the mutex is held by a task then it cannot be
+					given from an interrupt, and if a mutex is given by the
+					holding task then it must be the running state task.  Remove
+					the holding task from the ready/delayed list. */
+					if( uxListRemove( &( pxTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )
+					{
+						taskRESET_READY_PRIORITY( pxTCB->uxPriority );
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+
+					/* Disinherit the priority before adding the task into the
+					new	ready list. */
+					traceTASK_PRIORITY_DISINHERIT( pxTCB, pxTCB->uxBasePriority );
+					pxTCB->uxPriority = pxTCB->uxBasePriority;
+
+					/* Reset the event list item value.  It cannot be in use for
+					any other purpose if this task is running, and it must be
+					running to give back the mutex. */
+					listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) pxTCB->uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
+					prvAddTaskToReadyList( pxTCB );
+
+					/* Return true to indicate that a context switch is required.
+					This is only actually required in the corner case whereby
+					multiple mutexes were held and the mutexes were given back
+					in an order different to that in which they were taken.
+					If a context switch did not occur when the first mutex was
+					returned, even if a task was waiting on it, then a context
+					switch should occur when the last mutex is returned whether
+					a task is waiting on it or not. */
+					xReturn = pdTRUE;
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+
+		return xReturn;
+	}
+
+#endif /* configUSE_MUTEXES */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_MUTEXES == 1 )
+
+	void vTaskPriorityDisinheritAfterTimeout( TaskHandle_t const pxMutexHolder, UBaseType_t uxHighestPriorityWaitingTask )
+	{
+	TCB_t * const pxTCB = pxMutexHolder;
+	UBaseType_t uxPriorityUsedOnEntry, uxPriorityToUse;
+	const UBaseType_t uxOnlyOneMutexHeld = ( UBaseType_t ) 1;
+
+		if( pxMutexHolder != NULL )
+		{
+			/* If pxMutexHolder is not NULL then the holder must hold at least
+			one mutex. */
+			configASSERT( pxTCB->uxMutexesHeld );
+
+			/* Determine the priority to which the priority of the task that
+			holds the mutex should be set.  This will be the greater of the
+			holding task's base priority and the priority of the highest
+			priority task that is waiting to obtain the mutex. */
+			if( pxTCB->uxBasePriority < uxHighestPriorityWaitingTask )
+			{
+				uxPriorityToUse = uxHighestPriorityWaitingTask;
+			}
+			else
+			{
+				uxPriorityToUse = pxTCB->uxBasePriority;
+			}
+
+			/* Does the priority need to change? */
+			if( pxTCB->uxPriority != uxPriorityToUse )
+			{
+				/* Only disinherit if no other mutexes are held.  This is a
+				simplification in the priority inheritance implementation.  If
+				the task that holds the mutex is also holding other mutexes then
+				the other mutexes may have caused the priority inheritance. */
+				if( pxTCB->uxMutexesHeld == uxOnlyOneMutexHeld )
+				{
+					/* If a task has timed out because it already holds the
+					mutex it was trying to obtain then it cannot of inherited
+					its own priority. */
+					configASSERT( pxTCB != pxCurrentTCB );
+
+					/* Disinherit the priority, remembering the previous
+					priority to facilitate determining the subject task's
+					state. */
+					traceTASK_PRIORITY_DISINHERIT( pxTCB, pxTCB->uxBasePriority );
+					uxPriorityUsedOnEntry = pxTCB->uxPriority;
+					pxTCB->uxPriority = uxPriorityToUse;
+
+					/* Only reset the event list item value if the value is not
+					being used for anything else. */
+					if( ( listGET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ) ) & taskEVENT_LIST_ITEM_VALUE_IN_USE ) == 0UL )
+					{
+						listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) uxPriorityToUse ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+
+					/* If the running task is not the task that holds the mutex
+					then the task that holds the mutex could be in either the
+					Ready, Blocked or Suspended states.  Only remove the task
+					from its current state list if it is in the Ready state as
+					the task's priority is going to change and there is one
+					Ready list per priority. */
+					if( listIS_CONTAINED_WITHIN( &( pxReadyTasksLists[ uxPriorityUsedOnEntry ] ), &( pxTCB->xStateListItem ) ) != pdFALSE )
+					{
+						if( uxListRemove( &( pxTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )
+						{
+							/* It is known that the task is in its ready list so
+							there is no need to check again and the port level
+							reset macro can be called directly. */
+							portRESET_READY_PRIORITY( pxTCB->uxPriority, uxTopReadyPriority );
+						}
+						else
+						{
+							mtCOVERAGE_TEST_MARKER();
+						}
+
+						prvAddTaskToReadyList( pxTCB );
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+
+#endif /* configUSE_MUTEXES */
+/*-----------------------------------------------------------*/
+
+#if ( portCRITICAL_NESTING_IN_TCB == 1 )
+
+	void vTaskEnterCritical( void )
+	{
+		portDISABLE_INTERRUPTS();
+
+		if( xSchedulerRunning != pdFALSE )
+		{
+			( pxCurrentTCB->uxCriticalNesting )++;
+
+			/* This is not the interrupt safe version of the enter critical
+			function so	assert() if it is being called from an interrupt
+			context.  Only API functions that end in "FromISR" can be used in an
+			interrupt.  Only assert if the critical nesting count is 1 to
+			protect against recursive calls if the assert function also uses a
+			critical section. */
+			if( pxCurrentTCB->uxCriticalNesting == 1 )
+			{
+				portASSERT_IF_IN_ISR();
+			}
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+
+#endif /* portCRITICAL_NESTING_IN_TCB */
+/*-----------------------------------------------------------*/
+
+#if ( portCRITICAL_NESTING_IN_TCB == 1 )
+
+	void vTaskExitCritical( void )
+	{
+		if( xSchedulerRunning != pdFALSE )
+		{
+			if( pxCurrentTCB->uxCriticalNesting > 0U )
+			{
+				( pxCurrentTCB->uxCriticalNesting )--;
+
+				if( pxCurrentTCB->uxCriticalNesting == 0U )
+				{
+					portENABLE_INTERRUPTS();
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+
+#endif /* portCRITICAL_NESTING_IN_TCB */
+/*-----------------------------------------------------------*/
+
+#if ( ( configUSE_TRACE_FACILITY == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) )
+
+	static char *prvWriteNameToBuffer( char *pcBuffer, const char *pcTaskName )
+	{
+	size_t x;
+
+		/* Start by copying the entire string. */
+		strcpy( pcBuffer, pcTaskName );
+
+		/* Pad the end of the string with spaces to ensure columns line up when
+		printed out. */
+		for( x = strlen( pcBuffer ); x < ( size_t ) ( configMAX_TASK_NAME_LEN - 1 ); x++ )
+		{
+			pcBuffer[ x ] = ' ';
+		}
+
+		/* Terminate. */
+		pcBuffer[ x ] = ( char ) 0x00;
+
+		/* Return the new end of string. */
+		return &( pcBuffer[ x ] );
+	}
+
+#endif /* ( configUSE_TRACE_FACILITY == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) */
+/*-----------------------------------------------------------*/
+
+#if ( ( configUSE_TRACE_FACILITY == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
+
+	void vTaskList( char * pcWriteBuffer )
+	{
+	TaskStatus_t *pxTaskStatusArray;
+	UBaseType_t uxArraySize, x;
+	char cStatus;
+
+		/*
+		 * PLEASE NOTE:
+		 *
+		 * This function is provided for convenience only, and is used by many
+		 * of the demo applications.  Do not consider it to be part of the
+		 * scheduler.
+		 *
+		 * vTaskList() calls uxTaskGetSystemState(), then formats part of the
+		 * uxTaskGetSystemState() output into a human readable table that
+		 * displays task names, states and stack usage.
+		 *
+		 * vTaskList() has a dependency on the sprintf() C library function that
+		 * might bloat the code size, use a lot of stack, and provide different
+		 * results on different platforms.  An alternative, tiny, third party,
+		 * and limited functionality implementation of sprintf() is provided in
+		 * many of the FreeRTOS/Demo sub-directories in a file called
+		 * printf-stdarg.c (note printf-stdarg.c does not provide a full
+		 * snprintf() implementation!).
+		 *
+		 * It is recommended that production systems call uxTaskGetSystemState()
+		 * directly to get access to raw stats data, rather than indirectly
+		 * through a call to vTaskList().
+		 */
+
+
+		/* Make sure the write buffer does not contain a string. */
+		*pcWriteBuffer = ( char ) 0x00;
+
+		/* Take a snapshot of the number of tasks in case it changes while this
+		function is executing. */
+		uxArraySize = uxCurrentNumberOfTasks;
+
+		/* Allocate an array index for each task.  NOTE!  if
+		configSUPPORT_DYNAMIC_ALLOCATION is set to 0 then pvPortMalloc() will
+		equate to NULL. */
+		pxTaskStatusArray = pvPortMalloc( uxCurrentNumberOfTasks * sizeof( TaskStatus_t ) ); /*lint !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack and this allocation allocates a struct that has the alignment requirements of a pointer. */
+
+		if( pxTaskStatusArray != NULL )
+		{
+			/* Generate the (binary) data. */
+			uxArraySize = uxTaskGetSystemState( pxTaskStatusArray, uxArraySize, NULL );
+
+			/* Create a human readable table from the binary data. */
+			for( x = 0; x < uxArraySize; x++ )
+			{
+				switch( pxTaskStatusArray[ x ].eCurrentState )
+				{
+					case eRunning:		cStatus = tskRUNNING_CHAR;
+										break;
+
+					case eReady:		cStatus = tskREADY_CHAR;
+										break;
+
+					case eBlocked:		cStatus = tskBLOCKED_CHAR;
+										break;
+
+					case eSuspended:	cStatus = tskSUSPENDED_CHAR;
+										break;
+
+					case eDeleted:		cStatus = tskDELETED_CHAR;
+										break;
+
+					case eInvalid:		/* Fall through. */
+					default:			/* Should not get here, but it is included
+										to prevent static checking errors. */
+										cStatus = ( char ) 0x00;
+										break;
+				}
+
+				/* Write the task name to the string, padding with spaces so it
+				can be printed in tabular form more easily. */
+				pcWriteBuffer = prvWriteNameToBuffer( pcWriteBuffer, pxTaskStatusArray[ x ].pcTaskName );
+
+				/* Write the rest of the string. */
+				sprintf( pcWriteBuffer, "\t%c\t%u\t%u\t%u\r\n", cStatus, ( unsigned int ) pxTaskStatusArray[ x ].uxCurrentPriority, ( unsigned int ) pxTaskStatusArray[ x ].usStackHighWaterMark, ( unsigned int ) pxTaskStatusArray[ x ].xTaskNumber ); /*lint !e586 sprintf() allowed as this is compiled with many compilers and this is a utility function only - not part of the core kernel implementation. */
+				pcWriteBuffer += strlen( pcWriteBuffer ); /*lint !e9016 Pointer arithmetic ok on char pointers especially as in this case where it best denotes the intent of the code. */
+			}
+
+			/* Free the array again.  NOTE!  If configSUPPORT_DYNAMIC_ALLOCATION
+			is 0 then vPortFree() will be #defined to nothing. */
+			vPortFree( pxTaskStatusArray );
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+
+#endif /* ( ( configUSE_TRACE_FACILITY == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) */
+/*----------------------------------------------------------*/
+
+#if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
+
+	void vTaskGetRunTimeStats( char *pcWriteBuffer )
+	{
+	TaskStatus_t *pxTaskStatusArray;
+	UBaseType_t uxArraySize, x;
+	uint32_t ulTotalTime, ulStatsAsPercentage;
+
+		#if( configUSE_TRACE_FACILITY != 1 )
+		{
+			#error configUSE_TRACE_FACILITY must also be set to 1 in FreeRTOSConfig.h to use vTaskGetRunTimeStats().
+		}
+		#endif
+
+		/*
+		 * PLEASE NOTE:
+		 *
+		 * This function is provided for convenience only, and is used by many
+		 * of the demo applications.  Do not consider it to be part of the
+		 * scheduler.
+		 *
+		 * vTaskGetRunTimeStats() calls uxTaskGetSystemState(), then formats part
+		 * of the uxTaskGetSystemState() output into a human readable table that
+		 * displays the amount of time each task has spent in the Running state
+		 * in both absolute and percentage terms.
+		 *
+		 * vTaskGetRunTimeStats() has a dependency on the sprintf() C library
+		 * function that might bloat the code size, use a lot of stack, and
+		 * provide different results on different platforms.  An alternative,
+		 * tiny, third party, and limited functionality implementation of
+		 * sprintf() is provided in many of the FreeRTOS/Demo sub-directories in
+		 * a file called printf-stdarg.c (note printf-stdarg.c does not provide
+		 * a full snprintf() implementation!).
+		 *
+		 * It is recommended that production systems call uxTaskGetSystemState()
+		 * directly to get access to raw stats data, rather than indirectly
+		 * through a call to vTaskGetRunTimeStats().
+		 */
+
+		/* Make sure the write buffer does not contain a string. */
+		*pcWriteBuffer = ( char ) 0x00;
+
+		/* Take a snapshot of the number of tasks in case it changes while this
+		function is executing. */
+		uxArraySize = uxCurrentNumberOfTasks;
+
+		/* Allocate an array index for each task.  NOTE!  If
+		configSUPPORT_DYNAMIC_ALLOCATION is set to 0 then pvPortMalloc() will
+		equate to NULL. */
+		pxTaskStatusArray = pvPortMalloc( uxCurrentNumberOfTasks * sizeof( TaskStatus_t ) ); /*lint !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack and this allocation allocates a struct that has the alignment requirements of a pointer. */
+
+		if( pxTaskStatusArray != NULL )
+		{
+			/* Generate the (binary) data. */
+			uxArraySize = uxTaskGetSystemState( pxTaskStatusArray, uxArraySize, &ulTotalTime );
+
+			/* For percentage calculations. */
+			ulTotalTime /= 100UL;
+
+			/* Avoid divide by zero errors. */
+			if( ulTotalTime > 0UL )
+			{
+				/* Create a human readable table from the binary data. */
+				for( x = 0; x < uxArraySize; x++ )
+				{
+					/* What percentage of the total run time has the task used?
+					This will always be rounded down to the nearest integer.
+					ulTotalRunTimeDiv100 has already been divided by 100. */
+					ulStatsAsPercentage = pxTaskStatusArray[ x ].ulRunTimeCounter / ulTotalTime;
+
+					/* Write the task name to the string, padding with
+					spaces so it can be printed in tabular form more
+					easily. */
+					pcWriteBuffer = prvWriteNameToBuffer( pcWriteBuffer, pxTaskStatusArray[ x ].pcTaskName );
+
+					if( ulStatsAsPercentage > 0UL )
+					{
+						#ifdef portLU_PRINTF_SPECIFIER_REQUIRED
+						{
+							sprintf( pcWriteBuffer, "\t%lu\t\t%lu%%\r\n", pxTaskStatusArray[ x ].ulRunTimeCounter, ulStatsAsPercentage );
+						}
+						#else
+						{
+							/* sizeof( int ) == sizeof( long ) so a smaller
+							printf() library can be used. */
+							sprintf( pcWriteBuffer, "\t%u\t\t%u%%\r\n", ( unsigned int ) pxTaskStatusArray[ x ].ulRunTimeCounter, ( unsigned int ) ulStatsAsPercentage ); /*lint !e586 sprintf() allowed as this is compiled with many compilers and this is a utility function only - not part of the core kernel implementation. */
+						}
+						#endif
+					}
+					else
+					{
+						/* If the percentage is zero here then the task has
+						consumed less than 1% of the total run time. */
+						#ifdef portLU_PRINTF_SPECIFIER_REQUIRED
+						{
+							sprintf( pcWriteBuffer, "\t%lu\t\t<1%%\r\n", pxTaskStatusArray[ x ].ulRunTimeCounter );
+						}
+						#else
+						{
+							/* sizeof( int ) == sizeof( long ) so a smaller
+							printf() library can be used. */
+							sprintf( pcWriteBuffer, "\t%u\t\t<1%%\r\n", ( unsigned int ) pxTaskStatusArray[ x ].ulRunTimeCounter ); /*lint !e586 sprintf() allowed as this is compiled with many compilers and this is a utility function only - not part of the core kernel implementation. */
+						}
+						#endif
+					}
+
+					pcWriteBuffer += strlen( pcWriteBuffer ); /*lint !e9016 Pointer arithmetic ok on char pointers especially as in this case where it best denotes the intent of the code. */
+				}
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+
+			/* Free the array again.  NOTE!  If configSUPPORT_DYNAMIC_ALLOCATION
+			is 0 then vPortFree() will be #defined to nothing. */
+			vPortFree( pxTaskStatusArray );
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+
+#endif /* ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+TickType_t uxTaskResetEventItemValue( void )
+{
+TickType_t uxReturn;
+
+	uxReturn = listGET_LIST_ITEM_VALUE( &( pxCurrentTCB->xEventListItem ) );
+
+	/* Reset the event list item to its normal value - so it can be used with
+	queues and semaphores. */
+	listSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xEventListItem ), ( ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) pxCurrentTCB->uxPriority ) ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
+
+	return uxReturn;
+}
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_MUTEXES == 1 )
+
+	TaskHandle_t pvTaskIncrementMutexHeldCount( void )
+	{
+		/* If xSemaphoreCreateMutex() is called before any tasks have been created
+		then pxCurrentTCB will be NULL. */
+		if( pxCurrentTCB != NULL )
+		{
+			( pxCurrentTCB->uxMutexesHeld )++;
+		}
+
+		return pxCurrentTCB;
+	}
+
+#endif /* configUSE_MUTEXES */
+/*-----------------------------------------------------------*/
+
+#if( configUSE_TASK_NOTIFICATIONS == 1 )
+
+	uint32_t ulTaskNotifyTake( BaseType_t xClearCountOnExit, TickType_t xTicksToWait )
+	{
+	uint32_t ulReturn;
+
+		taskENTER_CRITICAL();
+		{
+			/* Only block if the notification count is not already non-zero. */
+			if( pxCurrentTCB->ulNotifiedValue == 0UL )
+			{
+				/* Mark this task as waiting for a notification. */
+				pxCurrentTCB->ucNotifyState = taskWAITING_NOTIFICATION;
+
+				if( xTicksToWait > ( TickType_t ) 0 )
+				{
+					prvAddCurrentTaskToDelayedList( xTicksToWait, pdTRUE );
+					traceTASK_NOTIFY_TAKE_BLOCK();
+
+					/* All ports are written to allow a yield in a critical
+					section (some will yield immediately, others wait until the
+					critical section exits) - but it is not something that
+					application code should ever do. */
+					portYIELD_WITHIN_API();
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		taskEXIT_CRITICAL();
+
+		taskENTER_CRITICAL();
+		{
+			traceTASK_NOTIFY_TAKE();
+			ulReturn = pxCurrentTCB->ulNotifiedValue;
+
+			if( ulReturn != 0UL )
+			{
+				if( xClearCountOnExit != pdFALSE )
+				{
+					pxCurrentTCB->ulNotifiedValue = 0UL;
+				}
+				else
+				{
+					pxCurrentTCB->ulNotifiedValue = ulReturn - ( uint32_t ) 1;
+				}
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+
+			pxCurrentTCB->ucNotifyState = taskNOT_WAITING_NOTIFICATION;
+		}
+		taskEXIT_CRITICAL();
+
+		return ulReturn;
+	}
+
+#endif /* configUSE_TASK_NOTIFICATIONS */
+/*-----------------------------------------------------------*/
+
+#if( configUSE_TASK_NOTIFICATIONS == 1 )
+
+	BaseType_t xTaskNotifyWait( uint32_t ulBitsToClearOnEntry, uint32_t ulBitsToClearOnExit, uint32_t *pulNotificationValue, TickType_t xTicksToWait )
+	{
+	BaseType_t xReturn;
+
+		taskENTER_CRITICAL();
+		{
+			/* Only block if a notification is not already pending. */
+			if( pxCurrentTCB->ucNotifyState != taskNOTIFICATION_RECEIVED )
+			{
+				/* Clear bits in the task's notification value as bits may get
+				set	by the notifying task or interrupt.  This can be used to
+				clear the value to zero. */
+				pxCurrentTCB->ulNotifiedValue &= ~ulBitsToClearOnEntry;
+
+				/* Mark this task as waiting for a notification. */
+				pxCurrentTCB->ucNotifyState = taskWAITING_NOTIFICATION;
+
+				if( xTicksToWait > ( TickType_t ) 0 )
+				{
+					prvAddCurrentTaskToDelayedList( xTicksToWait, pdTRUE );
+					traceTASK_NOTIFY_WAIT_BLOCK();
+
+					/* All ports are written to allow a yield in a critical
+					section (some will yield immediately, others wait until the
+					critical section exits) - but it is not something that
+					application code should ever do. */
+					portYIELD_WITHIN_API();
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		taskEXIT_CRITICAL();
+
+		taskENTER_CRITICAL();
+		{
+			traceTASK_NOTIFY_WAIT();
+
+			if( pulNotificationValue != NULL )
+			{
+				/* Output the current notification value, which may or may not
+				have changed. */
+				*pulNotificationValue = pxCurrentTCB->ulNotifiedValue;
+			}
+
+			/* If ucNotifyValue is set then either the task never entered the
+			blocked state (because a notification was already pending) or the
+			task unblocked because of a notification.  Otherwise the task
+			unblocked because of a timeout. */
+			if( pxCurrentTCB->ucNotifyState != taskNOTIFICATION_RECEIVED )
+			{
+				/* A notification was not received. */
+				xReturn = pdFALSE;
+			}
+			else
+			{
+				/* A notification was already pending or a notification was
+				received while the task was waiting. */
+				pxCurrentTCB->ulNotifiedValue &= ~ulBitsToClearOnExit;
+				xReturn = pdTRUE;
+			}
+
+			pxCurrentTCB->ucNotifyState = taskNOT_WAITING_NOTIFICATION;
+		}
+		taskEXIT_CRITICAL();
+
+		return xReturn;
+	}
+
+#endif /* configUSE_TASK_NOTIFICATIONS */
+/*-----------------------------------------------------------*/
+
+#if( configUSE_TASK_NOTIFICATIONS == 1 )
+
+	BaseType_t xTaskGenericNotify( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction, uint32_t *pulPreviousNotificationValue )
+	{
+	TCB_t * pxTCB;
+	BaseType_t xReturn = pdPASS;
+	uint8_t ucOriginalNotifyState;
+
+		configASSERT( xTaskToNotify );
+		pxTCB = xTaskToNotify;
+
+		taskENTER_CRITICAL();
+		{
+			if( pulPreviousNotificationValue != NULL )
+			{
+				*pulPreviousNotificationValue = pxTCB->ulNotifiedValue;
+			}
+
+			ucOriginalNotifyState = pxTCB->ucNotifyState;
+
+			pxTCB->ucNotifyState = taskNOTIFICATION_RECEIVED;
+
+			switch( eAction )
+			{
+				case eSetBits	:
+					pxTCB->ulNotifiedValue |= ulValue;
+					break;
+
+				case eIncrement	:
+					( pxTCB->ulNotifiedValue )++;
+					break;
+
+				case eSetValueWithOverwrite	:
+					pxTCB->ulNotifiedValue = ulValue;
+					break;
+
+				case eSetValueWithoutOverwrite :
+					if( ucOriginalNotifyState != taskNOTIFICATION_RECEIVED )
+					{
+						pxTCB->ulNotifiedValue = ulValue;
+					}
+					else
+					{
+						/* The value could not be written to the task. */
+						xReturn = pdFAIL;
+					}
+					break;
+
+				case eNoAction:
+					/* The task is being notified without its notify value being
+					updated. */
+					break;
+
+				default:
+					/* Should not get here if all enums are handled.
+					Artificially force an assert by testing a value the
+					compiler can't assume is const. */
+					configASSERT( pxTCB->ulNotifiedValue == ~0UL );
+
+					break;
+			}
+
+			traceTASK_NOTIFY();
+
+			/* If the task is in the blocked state specifically to wait for a
+			notification then unblock it now. */
+			if( ucOriginalNotifyState == taskWAITING_NOTIFICATION )
+			{
+				( void ) uxListRemove( &( pxTCB->xStateListItem ) );
+				prvAddTaskToReadyList( pxTCB );
+
+				/* The task should not have been on an event list. */
+				configASSERT( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) == NULL );
+
+				#if( configUSE_TICKLESS_IDLE != 0 )
+				{
+					/* If a task is blocked waiting for a notification then
+					xNextTaskUnblockTime might be set to the blocked task's time
+					out time.  If the task is unblocked for a reason other than
+					a timeout xNextTaskUnblockTime is normally left unchanged,
+					because it will automatically get reset to a new value when
+					the tick count equals xNextTaskUnblockTime.  However if
+					tickless idling is used it might be more important to enter
+					sleep mode at the earliest possible time - so reset
+					xNextTaskUnblockTime here to ensure it is updated at the
+					earliest possible time. */
+					prvResetNextTaskUnblockTime();
+				}
+				#endif
+
+				if( pxTCB->uxPriority > pxCurrentTCB->uxPriority )
+				{
+					/* The notified task has a priority above the currently
+					executing task so a yield is required. */
+					taskYIELD_IF_USING_PREEMPTION();
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		taskEXIT_CRITICAL();
+
+		return xReturn;
+	}
+
+#endif /* configUSE_TASK_NOTIFICATIONS */
+/*-----------------------------------------------------------*/
+
+#if( configUSE_TASK_NOTIFICATIONS == 1 )
+
+	BaseType_t xTaskGenericNotifyFromISR( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction, uint32_t *pulPreviousNotificationValue, BaseType_t *pxHigherPriorityTaskWoken )
+	{
+	TCB_t * pxTCB;
+	uint8_t ucOriginalNotifyState;
+	BaseType_t xReturn = pdPASS;
+	UBaseType_t uxSavedInterruptStatus;
+
+		configASSERT( xTaskToNotify );
+
+		/* RTOS ports that support interrupt nesting have the concept of a
+		maximum	system call (or maximum API call) interrupt priority.
+		Interrupts that are	above the maximum system call priority are keep
+		permanently enabled, even when the RTOS kernel is in a critical section,
+		but cannot make any calls to FreeRTOS API functions.  If configASSERT()
+		is defined in FreeRTOSConfig.h then
+		portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion
+		failure if a FreeRTOS API function is called from an interrupt that has
+		been assigned a priority above the configured maximum system call
+		priority.  Only FreeRTOS functions that end in FromISR can be called
+		from interrupts	that have been assigned a priority at or (logically)
+		below the maximum system call interrupt priority.  FreeRTOS maintains a
+		separate interrupt safe API to ensure interrupt entry is as fast and as
+		simple as possible.  More information (albeit Cortex-M specific) is
+		provided on the following link:
+		http://www.freertos.org/RTOS-Cortex-M3-M4.html */
+		portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
+
+		pxTCB = xTaskToNotify;
+
+		uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
+		{
+			if( pulPreviousNotificationValue != NULL )
+			{
+				*pulPreviousNotificationValue = pxTCB->ulNotifiedValue;
+			}
+
+			ucOriginalNotifyState = pxTCB->ucNotifyState;
+			pxTCB->ucNotifyState = taskNOTIFICATION_RECEIVED;
+
+			switch( eAction )
+			{
+				case eSetBits	:
+					pxTCB->ulNotifiedValue |= ulValue;
+					break;
+
+				case eIncrement	:
+					( pxTCB->ulNotifiedValue )++;
+					break;
+
+				case eSetValueWithOverwrite	:
+					pxTCB->ulNotifiedValue = ulValue;
+					break;
+
+				case eSetValueWithoutOverwrite :
+					if( ucOriginalNotifyState != taskNOTIFICATION_RECEIVED )
+					{
+						pxTCB->ulNotifiedValue = ulValue;
+					}
+					else
+					{
+						/* The value could not be written to the task. */
+						xReturn = pdFAIL;
+					}
+					break;
+
+				case eNoAction :
+					/* The task is being notified without its notify value being
+					updated. */
+					break;
+
+				default:
+					/* Should not get here if all enums are handled.
+					Artificially force an assert by testing a value the
+					compiler can't assume is const. */
+					configASSERT( pxTCB->ulNotifiedValue == ~0UL );
+					break;
+			}
+
+			traceTASK_NOTIFY_FROM_ISR();
+
+			/* If the task is in the blocked state specifically to wait for a
+			notification then unblock it now. */
+			if( ucOriginalNotifyState == taskWAITING_NOTIFICATION )
+			{
+				/* The task should not have been on an event list. */
+				configASSERT( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) == NULL );
+
+				if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )
+				{
+					( void ) uxListRemove( &( pxTCB->xStateListItem ) );
+					prvAddTaskToReadyList( pxTCB );
+				}
+				else
+				{
+					/* The delayed and ready lists cannot be accessed, so hold
+					this task pending until the scheduler is resumed. */
+					vListInsertEnd( &( xPendingReadyList ), &( pxTCB->xEventListItem ) );
+				}
+
+				if( pxTCB->uxPriority > pxCurrentTCB->uxPriority )
+				{
+					/* The notified task has a priority above the currently
+					executing task so a yield is required. */
+					if( pxHigherPriorityTaskWoken != NULL )
+					{
+						*pxHigherPriorityTaskWoken = pdTRUE;
+					}
+
+					/* Mark that a yield is pending in case the user is not
+					using the "xHigherPriorityTaskWoken" parameter to an ISR
+					safe FreeRTOS function. */
+					xYieldPending = pdTRUE;
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+		}
+		portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
+
+		return xReturn;
+	}
+
+#endif /* configUSE_TASK_NOTIFICATIONS */
+/*-----------------------------------------------------------*/
+
+#if( configUSE_TASK_NOTIFICATIONS == 1 )
+
+	void vTaskNotifyGiveFromISR( TaskHandle_t xTaskToNotify, BaseType_t *pxHigherPriorityTaskWoken )
+	{
+	TCB_t * pxTCB;
+	uint8_t ucOriginalNotifyState;
+	UBaseType_t uxSavedInterruptStatus;
+
+		configASSERT( xTaskToNotify );
+
+		/* RTOS ports that support interrupt nesting have the concept of a
+		maximum	system call (or maximum API call) interrupt priority.
+		Interrupts that are	above the maximum system call priority are keep
+		permanently enabled, even when the RTOS kernel is in a critical section,
+		but cannot make any calls to FreeRTOS API functions.  If configASSERT()
+		is defined in FreeRTOSConfig.h then
+		portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion
+		failure if a FreeRTOS API function is called from an interrupt that has
+		been assigned a priority above the configured maximum system call
+		priority.  Only FreeRTOS functions that end in FromISR can be called
+		from interrupts	that have been assigned a priority at or (logically)
+		below the maximum system call interrupt priority.  FreeRTOS maintains a
+		separate interrupt safe API to ensure interrupt entry is as fast and as
+		simple as possible.  More information (albeit Cortex-M specific) is
+		provided on the following link:
+		http://www.freertos.org/RTOS-Cortex-M3-M4.html */
+		portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
+
+		pxTCB = xTaskToNotify;
+
+		uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
+		{
+			ucOriginalNotifyState = pxTCB->ucNotifyState;
+			pxTCB->ucNotifyState = taskNOTIFICATION_RECEIVED;
+
+			/* 'Giving' is equivalent to incrementing a count in a counting
+			semaphore. */
+			( pxTCB->ulNotifiedValue )++;
+
+			traceTASK_NOTIFY_GIVE_FROM_ISR();
+
+			/* If the task is in the blocked state specifically to wait for a
+			notification then unblock it now. */
+			if( ucOriginalNotifyState == taskWAITING_NOTIFICATION )
+			{
+				/* The task should not have been on an event list. */
+				configASSERT( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) == NULL );
+
+				if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )
+				{
+					( void ) uxListRemove( &( pxTCB->xStateListItem ) );
+					prvAddTaskToReadyList( pxTCB );
+				}
+				else
+				{
+					/* The delayed and ready lists cannot be accessed, so hold
+					this task pending until the scheduler is resumed. */
+					vListInsertEnd( &( xPendingReadyList ), &( pxTCB->xEventListItem ) );
+				}
+
+				if( pxTCB->uxPriority > pxCurrentTCB->uxPriority )
+				{
+					/* The notified task has a priority above the currently
+					executing task so a yield is required. */
+					if( pxHigherPriorityTaskWoken != NULL )
+					{
+						*pxHigherPriorityTaskWoken = pdTRUE;
+					}
+
+					/* Mark that a yield is pending in case the user is not
+					using the "xHigherPriorityTaskWoken" parameter in an ISR
+					safe FreeRTOS function. */
+					xYieldPending = pdTRUE;
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+		}
+		portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
+	}
+
+#endif /* configUSE_TASK_NOTIFICATIONS */
+/*-----------------------------------------------------------*/
+
+#if( configUSE_TASK_NOTIFICATIONS == 1 )
+
+	BaseType_t xTaskNotifyStateClear( TaskHandle_t xTask )
+	{
+	TCB_t *pxTCB;
+	BaseType_t xReturn;
+
+		/* If null is passed in here then it is the calling task that is having
+		its notification state cleared. */
+		pxTCB = prvGetTCBFromHandle( xTask );
+
+		taskENTER_CRITICAL();
+		{
+			if( pxTCB->ucNotifyState == taskNOTIFICATION_RECEIVED )
+			{
+				pxTCB->ucNotifyState = taskNOT_WAITING_NOTIFICATION;
+				xReturn = pdPASS;
+			}
+			else
+			{
+				xReturn = pdFAIL;
+			}
+		}
+		taskEXIT_CRITICAL();
+
+		return xReturn;
+	}
+
+#endif /* configUSE_TASK_NOTIFICATIONS */
+/*-----------------------------------------------------------*/
+
+#if( configUSE_TASK_NOTIFICATIONS == 1 )
+
+	uint32_t ulTaskNotifyValueClear( TaskHandle_t xTask, uint32_t ulBitsToClear )
+	{
+	TCB_t *pxTCB;
+	uint32_t ulReturn;
+
+		/* If null is passed in here then it is the calling task that is having
+		its notification state cleared. */
+		pxTCB = prvGetTCBFromHandle( xTask );
+
+		taskENTER_CRITICAL();
+		{
+			/* Return the notification as it was before the bits were cleared,
+			then clear the bit mask. */
+			ulReturn = pxCurrentTCB->ulNotifiedValue;
+			pxTCB->ulNotifiedValue &= ~ulBitsToClear;
+		}
+		taskEXIT_CRITICAL();
+
+		return ulReturn;
+	}
+
+#endif /* configUSE_TASK_NOTIFICATIONS */
+/*-----------------------------------------------------------*/
+
+#if( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) )
+
+	uint32_t ulTaskGetIdleRunTimeCounter( void )
+	{
+		return xIdleTaskHandle->ulRunTimeCounter;
+	}
+
+#endif
+/*-----------------------------------------------------------*/
+
+static void prvAddCurrentTaskToDelayedList( TickType_t xTicksToWait, const BaseType_t xCanBlockIndefinitely )
+{
+TickType_t xTimeToWake;
+const TickType_t xConstTickCount = xTickCount;
+
+	#if( INCLUDE_xTaskAbortDelay == 1 )
+	{
+		/* About to enter a delayed list, so ensure the ucDelayAborted flag is
+		reset to pdFALSE so it can be detected as having been set to pdTRUE
+		when the task leaves the Blocked state. */
+		pxCurrentTCB->ucDelayAborted = pdFALSE;
+	}
+	#endif
+
+	/* Remove the task from the ready list before adding it to the blocked list
+	as the same list item is used for both lists. */
+	if( uxListRemove( &( pxCurrentTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )
+	{
+		/* The current task must be in a ready list, so there is no need to
+		check, and the port reset macro can be called directly. */
+		portRESET_READY_PRIORITY( pxCurrentTCB->uxPriority, uxTopReadyPriority ); /*lint !e931 pxCurrentTCB cannot change as it is the calling task.  pxCurrentTCB->uxPriority and uxTopReadyPriority cannot change as called with scheduler suspended or in a critical section. */
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	#if ( INCLUDE_vTaskSuspend == 1 )
+	{
+		if( ( xTicksToWait == portMAX_DELAY ) && ( xCanBlockIndefinitely != pdFALSE ) )
+		{
+			/* Add the task to the suspended task list instead of a delayed task
+			list to ensure it is not woken by a timing event.  It will block
+			indefinitely. */
+			vListInsertEnd( &xSuspendedTaskList, &( pxCurrentTCB->xStateListItem ) );
+		}
+		else
+		{
+			/* Calculate the time at which the task should be woken if the event
+			does not occur.  This may overflow but this doesn't matter, the
+			kernel will manage it correctly. */
+			xTimeToWake = xConstTickCount + xTicksToWait;
+
+			/* The list item will be inserted in wake time order. */
+			listSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xStateListItem ), xTimeToWake );
+
+			if( xTimeToWake < xConstTickCount )
+			{
+				/* Wake time has overflowed.  Place this item in the overflow
+				list. */
+				vListInsert( pxOverflowDelayedTaskList, &( pxCurrentTCB->xStateListItem ) );
+			}
+			else
+			{
+				/* The wake time has not overflowed, so the current block list
+				is used. */
+				vListInsert( pxDelayedTaskList, &( pxCurrentTCB->xStateListItem ) );
+
+				/* If the task entering the blocked state was placed at the
+				head of the list of blocked tasks then xNextTaskUnblockTime
+				needs to be updated too. */
+				if( xTimeToWake < xNextTaskUnblockTime )
+				{
+					xNextTaskUnblockTime = xTimeToWake;
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+		}
+	}
+	#else /* INCLUDE_vTaskSuspend */
+	{
+		/* Calculate the time at which the task should be woken if the event
+		does not occur.  This may overflow but this doesn't matter, the kernel
+		will manage it correctly. */
+		xTimeToWake = xConstTickCount + xTicksToWait;
+
+		/* The list item will be inserted in wake time order. */
+		listSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xStateListItem ), xTimeToWake );
+
+		if( xTimeToWake < xConstTickCount )
+		{
+			/* Wake time has overflowed.  Place this item in the overflow list. */
+			vListInsert( pxOverflowDelayedTaskList, &( pxCurrentTCB->xStateListItem ) );
+		}
+		else
+		{
+			/* The wake time has not overflowed, so the current block list is used. */
+			vListInsert( pxDelayedTaskList, &( pxCurrentTCB->xStateListItem ) );
+
+			/* If the task entering the blocked state was placed at the head of the
+			list of blocked tasks then xNextTaskUnblockTime needs to be updated
+			too. */
+			if( xTimeToWake < xNextTaskUnblockTime )
+			{
+				xNextTaskUnblockTime = xTimeToWake;
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+
+		/* Avoid compiler warning when INCLUDE_vTaskSuspend is not 1. */
+		( void ) xCanBlockIndefinitely;
+	}
+	#endif /* INCLUDE_vTaskSuspend */
+}
+
+/* Code below here allows additional code to be inserted into this source file,
+especially where access to file scope functions and data is needed (for example
+when performing module tests). */
+
+#ifdef FREERTOS_MODULE_TEST
+	#include "tasks_test_access_functions.h"
+#endif
+
+
+#if( configINCLUDE_FREERTOS_TASK_C_ADDITIONS_H == 1 )
+
+	#include "freertos_tasks_c_additions.h"
+
+	#ifdef FREERTOS_TASKS_C_ADDITIONS_INIT
+		static void freertos_tasks_c_additions_init( void )
+		{
+			FREERTOS_TASKS_C_ADDITIONS_INIT();
+		}
+	#endif
+
+#endif
+
+
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/timers.c b/Middlewares/Third_Party/FreeRTOS/Source/timers.c
new file mode 100644
index 0000000..d10c832
--- /dev/null
+++ b/Middlewares/Third_Party/FreeRTOS/Source/timers.c
@@ -0,0 +1,1127 @@
+/*
+ * FreeRTOS Kernel V10.3.1
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Standard includes. */
+#include <stdlib.h>
+
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
+all the API functions to use the MPU wrappers.  That should only be done when
+task.h is included from an application file. */
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+#include "FreeRTOS.h"
+#include "task.h"
+#include "queue.h"
+#include "timers.h"
+
+#if ( INCLUDE_xTimerPendFunctionCall == 1 ) && ( configUSE_TIMERS == 0 )
+	#error configUSE_TIMERS must be set to 1 to make the xTimerPendFunctionCall() function available.
+#endif
+
+/* Lint e9021, e961 and e750 are suppressed as a MISRA exception justified
+because the MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined
+for the header files above, but not in this file, in order to generate the
+correct privileged Vs unprivileged linkage and placement. */
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE /*lint !e9021 !e961 !e750. */
+
+
+/* This entire source file will be skipped if the application is not configured
+to include software timer functionality.  This #if is closed at the very bottom
+of this file.  If you want to include software timer functionality then ensure
+configUSE_TIMERS is set to 1 in FreeRTOSConfig.h. */
+#if ( configUSE_TIMERS == 1 )
+
+/* Misc definitions. */
+#define tmrNO_DELAY		( TickType_t ) 0U
+
+/* The name assigned to the timer service task.  This can be overridden by
+defining trmTIMER_SERVICE_TASK_NAME in FreeRTOSConfig.h. */
+#ifndef configTIMER_SERVICE_TASK_NAME
+	#define configTIMER_SERVICE_TASK_NAME "Tmr Svc"
+#endif
+
+/* Bit definitions used in the ucStatus member of a timer structure. */
+#define tmrSTATUS_IS_ACTIVE					( ( uint8_t ) 0x01 )
+#define tmrSTATUS_IS_STATICALLY_ALLOCATED	( ( uint8_t ) 0x02 )
+#define tmrSTATUS_IS_AUTORELOAD				( ( uint8_t ) 0x04 )
+
+/* The definition of the timers themselves. */
+typedef struct tmrTimerControl /* The old naming convention is used to prevent breaking kernel aware debuggers. */
+{
+	const char				*pcTimerName;		/*<< Text name.  This is not used by the kernel, it is included simply to make debugging easier. */ /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+	ListItem_t				xTimerListItem;		/*<< Standard linked list item as used by all kernel features for event management. */
+	TickType_t				xTimerPeriodInTicks;/*<< How quickly and often the timer expires. */
+	void 					*pvTimerID;			/*<< An ID to identify the timer.  This allows the timer to be identified when the same callback is used for multiple timers. */
+	TimerCallbackFunction_t	pxCallbackFunction;	/*<< The function that will be called when the timer expires. */
+	#if( configUSE_TRACE_FACILITY == 1 )
+		UBaseType_t			uxTimerNumber;		/*<< An ID assigned by trace tools such as FreeRTOS+Trace */
+	#endif
+	uint8_t 				ucStatus;			/*<< Holds bits to say if the timer was statically allocated or not, and if it is active or not. */
+} xTIMER;
+
+/* The old xTIMER name is maintained above then typedefed to the new Timer_t
+name below to enable the use of older kernel aware debuggers. */
+typedef xTIMER Timer_t;
+
+/* The definition of messages that can be sent and received on the timer queue.
+Two types of message can be queued - messages that manipulate a software timer,
+and messages that request the execution of a non-timer related callback.  The
+two message types are defined in two separate structures, xTimerParametersType
+and xCallbackParametersType respectively. */
+typedef struct tmrTimerParameters
+{
+	TickType_t			xMessageValue;		/*<< An optional value used by a subset of commands, for example, when changing the period of a timer. */
+	Timer_t *			pxTimer;			/*<< The timer to which the command will be applied. */
+} TimerParameter_t;
+
+
+typedef struct tmrCallbackParameters
+{
+	PendedFunction_t	pxCallbackFunction;	/* << The callback function to execute. */
+	void *pvParameter1;						/* << The value that will be used as the callback functions first parameter. */
+	uint32_t ulParameter2;					/* << The value that will be used as the callback functions second parameter. */
+} CallbackParameters_t;
+
+/* The structure that contains the two message types, along with an identifier
+that is used to determine which message type is valid. */
+typedef struct tmrTimerQueueMessage
+{
+	BaseType_t			xMessageID;			/*<< The command being sent to the timer service task. */
+	union
+	{
+		TimerParameter_t xTimerParameters;
+
+		/* Don't include xCallbackParameters if it is not going to be used as
+		it makes the structure (and therefore the timer queue) larger. */
+		#if ( INCLUDE_xTimerPendFunctionCall == 1 )
+			CallbackParameters_t xCallbackParameters;
+		#endif /* INCLUDE_xTimerPendFunctionCall */
+	} u;
+} DaemonTaskMessage_t;
+
+/*lint -save -e956 A manual analysis and inspection has been used to determine
+which static variables must be declared volatile. */
+
+/* The list in which active timers are stored.  Timers are referenced in expire
+time order, with the nearest expiry time at the front of the list.  Only the
+timer service task is allowed to access these lists.
+xActiveTimerList1 and xActiveTimerList2 could be at function scope but that
+breaks some kernel aware debuggers, and debuggers that reply on removing the
+static qualifier. */
+PRIVILEGED_DATA static List_t xActiveTimerList1;
+PRIVILEGED_DATA static List_t xActiveTimerList2;
+PRIVILEGED_DATA static List_t *pxCurrentTimerList;
+PRIVILEGED_DATA static List_t *pxOverflowTimerList;
+
+/* A queue that is used to send commands to the timer service task. */
+PRIVILEGED_DATA static QueueHandle_t xTimerQueue = NULL;
+PRIVILEGED_DATA static TaskHandle_t xTimerTaskHandle = NULL;
+
+/*lint -restore */
+
+/*-----------------------------------------------------------*/
+
+#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+
+	/* If static allocation is supported then the application must provide the
+	following callback function - which enables the application to optionally
+	provide the memory that will be used by the timer task as the task's stack
+	and TCB. */
+	extern void vApplicationGetTimerTaskMemory( StaticTask_t **ppxTimerTaskTCBBuffer, StackType_t **ppxTimerTaskStackBuffer, uint32_t *pulTimerTaskStackSize );
+
+#endif
+
+/*
+ * Initialise the infrastructure used by the timer service task if it has not
+ * been initialised already.
+ */
+static void prvCheckForValidListAndQueue( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * The timer service task (daemon).  Timer functionality is controlled by this
+ * task.  Other tasks communicate with the timer service task using the
+ * xTimerQueue queue.
+ */
+static portTASK_FUNCTION_PROTO( prvTimerTask, pvParameters ) PRIVILEGED_FUNCTION;
+
+/*
+ * Called by the timer service task to interpret and process a command it
+ * received on the timer queue.
+ */
+static void prvProcessReceivedCommands( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * Insert the timer into either xActiveTimerList1, or xActiveTimerList2,
+ * depending on if the expire time causes a timer counter overflow.
+ */
+static BaseType_t prvInsertTimerInActiveList( Timer_t * const pxTimer, const TickType_t xNextExpiryTime, const TickType_t xTimeNow, const TickType_t xCommandTime ) PRIVILEGED_FUNCTION;
+
+/*
+ * An active timer has reached its expire time.  Reload the timer if it is an
+ * auto-reload timer, then call its callback.
+ */
+static void prvProcessExpiredTimer( const TickType_t xNextExpireTime, const TickType_t xTimeNow ) PRIVILEGED_FUNCTION;
+
+/*
+ * The tick count has overflowed.  Switch the timer lists after ensuring the
+ * current timer list does not still reference some timers.
+ */
+static void prvSwitchTimerLists( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * Obtain the current tick count, setting *pxTimerListsWereSwitched to pdTRUE
+ * if a tick count overflow occurred since prvSampleTimeNow() was last called.
+ */
+static TickType_t prvSampleTimeNow( BaseType_t * const pxTimerListsWereSwitched ) PRIVILEGED_FUNCTION;
+
+/*
+ * If the timer list contains any active timers then return the expire time of
+ * the timer that will expire first and set *pxListWasEmpty to false.  If the
+ * timer list does not contain any timers then return 0 and set *pxListWasEmpty
+ * to pdTRUE.
+ */
+static TickType_t prvGetNextExpireTime( BaseType_t * const pxListWasEmpty ) PRIVILEGED_FUNCTION;
+
+/*
+ * If a timer has expired, process it.  Otherwise, block the timer service task
+ * until either a timer does expire or a command is received.
+ */
+static void prvProcessTimerOrBlockTask( const TickType_t xNextExpireTime, BaseType_t xListWasEmpty ) PRIVILEGED_FUNCTION;
+
+/*
+ * Called after a Timer_t structure has been allocated either statically or
+ * dynamically to fill in the structure's members.
+ */
+static void prvInitialiseNewTimer(	const char * const pcTimerName,			/*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+									const TickType_t xTimerPeriodInTicks,
+									const UBaseType_t uxAutoReload,
+									void * const pvTimerID,
+									TimerCallbackFunction_t pxCallbackFunction,
+									Timer_t *pxNewTimer ) PRIVILEGED_FUNCTION;
+/*-----------------------------------------------------------*/
+
+BaseType_t xTimerCreateTimerTask( void )
+{
+BaseType_t xReturn = pdFAIL;
+
+	/* This function is called when the scheduler is started if
+	configUSE_TIMERS is set to 1.  Check that the infrastructure used by the
+	timer service task has been created/initialised.  If timers have already
+	been created then the initialisation will already have been performed. */
+	prvCheckForValidListAndQueue();
+
+	if( xTimerQueue != NULL )
+	{
+		#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+		{
+			StaticTask_t *pxTimerTaskTCBBuffer = NULL;
+			StackType_t *pxTimerTaskStackBuffer = NULL;
+			uint32_t ulTimerTaskStackSize;
+
+			vApplicationGetTimerTaskMemory( &pxTimerTaskTCBBuffer, &pxTimerTaskStackBuffer, &ulTimerTaskStackSize );
+			xTimerTaskHandle = xTaskCreateStatic(	prvTimerTask,
+													configTIMER_SERVICE_TASK_NAME,
+													ulTimerTaskStackSize,
+													NULL,
+													( ( UBaseType_t ) configTIMER_TASK_PRIORITY ) | portPRIVILEGE_BIT,
+													pxTimerTaskStackBuffer,
+													pxTimerTaskTCBBuffer );
+
+			if( xTimerTaskHandle != NULL )
+			{
+				xReturn = pdPASS;
+			}
+		}
+		#else
+		{
+			xReturn = xTaskCreate(	prvTimerTask,
+									configTIMER_SERVICE_TASK_NAME,
+									configTIMER_TASK_STACK_DEPTH,
+									NULL,
+									( ( UBaseType_t ) configTIMER_TASK_PRIORITY ) | portPRIVILEGE_BIT,
+									&xTimerTaskHandle );
+		}
+		#endif /* configSUPPORT_STATIC_ALLOCATION */
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	configASSERT( xReturn );
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+
+	TimerHandle_t xTimerCreate(	const char * const pcTimerName,			/*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+								const TickType_t xTimerPeriodInTicks,
+								const UBaseType_t uxAutoReload,
+								void * const pvTimerID,
+								TimerCallbackFunction_t pxCallbackFunction )
+	{
+	Timer_t *pxNewTimer;
+
+		pxNewTimer = ( Timer_t * ) pvPortMalloc( sizeof( Timer_t ) ); /*lint !e9087 !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack, and the first member of Timer_t is always a pointer to the timer's mame. */
+
+		if( pxNewTimer != NULL )
+		{
+			/* Status is thus far zero as the timer is not created statically
+			and has not been started.  The auto-reload bit may get set in
+			prvInitialiseNewTimer. */
+			pxNewTimer->ucStatus = 0x00;
+			prvInitialiseNewTimer( pcTimerName, xTimerPeriodInTicks, uxAutoReload, pvTimerID, pxCallbackFunction, pxNewTimer );
+		}
+
+		return pxNewTimer;
+	}
+
+#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
+/*-----------------------------------------------------------*/
+
+#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+
+	TimerHandle_t xTimerCreateStatic(	const char * const pcTimerName,		/*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+										const TickType_t xTimerPeriodInTicks,
+										const UBaseType_t uxAutoReload,
+										void * const pvTimerID,
+										TimerCallbackFunction_t pxCallbackFunction,
+										StaticTimer_t *pxTimerBuffer )
+	{
+	Timer_t *pxNewTimer;
+
+		#if( configASSERT_DEFINED == 1 )
+		{
+			/* Sanity check that the size of the structure used to declare a
+			variable of type StaticTimer_t equals the size of the real timer
+			structure. */
+			volatile size_t xSize = sizeof( StaticTimer_t );
+			configASSERT( xSize == sizeof( Timer_t ) );
+			( void ) xSize; /* Keeps lint quiet when configASSERT() is not defined. */
+		}
+		#endif /* configASSERT_DEFINED */
+
+		/* A pointer to a StaticTimer_t structure MUST be provided, use it. */
+		configASSERT( pxTimerBuffer );
+		pxNewTimer = ( Timer_t * ) pxTimerBuffer; /*lint !e740 !e9087 StaticTimer_t is a pointer to a Timer_t, so guaranteed to be aligned and sized correctly (checked by an assert()), so this is safe. */
+
+		if( pxNewTimer != NULL )
+		{
+			/* Timers can be created statically or dynamically so note this
+			timer was created statically in case it is later deleted.  The
+			auto-reload bit may get set in prvInitialiseNewTimer(). */
+			pxNewTimer->ucStatus = tmrSTATUS_IS_STATICALLY_ALLOCATED;
+
+			prvInitialiseNewTimer( pcTimerName, xTimerPeriodInTicks, uxAutoReload, pvTimerID, pxCallbackFunction, pxNewTimer );
+		}
+
+		return pxNewTimer;
+	}
+
+#endif /* configSUPPORT_STATIC_ALLOCATION */
+/*-----------------------------------------------------------*/
+
+static void prvInitialiseNewTimer(	const char * const pcTimerName,			/*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+									const TickType_t xTimerPeriodInTicks,
+									const UBaseType_t uxAutoReload,
+									void * const pvTimerID,
+									TimerCallbackFunction_t pxCallbackFunction,
+									Timer_t *pxNewTimer )
+{
+	/* 0 is not a valid value for xTimerPeriodInTicks. */
+	configASSERT( ( xTimerPeriodInTicks > 0 ) );
+
+	if( pxNewTimer != NULL )
+	{
+		/* Ensure the infrastructure used by the timer service task has been
+		created/initialised. */
+		prvCheckForValidListAndQueue();
+
+		/* Initialise the timer structure members using the function
+		parameters. */
+		pxNewTimer->pcTimerName = pcTimerName;
+		pxNewTimer->xTimerPeriodInTicks = xTimerPeriodInTicks;
+		pxNewTimer->pvTimerID = pvTimerID;
+		pxNewTimer->pxCallbackFunction = pxCallbackFunction;
+		vListInitialiseItem( &( pxNewTimer->xTimerListItem ) );
+		if( uxAutoReload != pdFALSE )
+		{
+			pxNewTimer->ucStatus |= tmrSTATUS_IS_AUTORELOAD;
+		}
+		traceTIMER_CREATE( pxNewTimer );
+	}
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xTimerGenericCommand( TimerHandle_t xTimer, const BaseType_t xCommandID, const TickType_t xOptionalValue, BaseType_t * const pxHigherPriorityTaskWoken, const TickType_t xTicksToWait )
+{
+BaseType_t xReturn = pdFAIL;
+DaemonTaskMessage_t xMessage;
+
+	configASSERT( xTimer );
+
+	/* Send a message to the timer service task to perform a particular action
+	on a particular timer definition. */
+	if( xTimerQueue != NULL )
+	{
+		/* Send a command to the timer service task to start the xTimer timer. */
+		xMessage.xMessageID = xCommandID;
+		xMessage.u.xTimerParameters.xMessageValue = xOptionalValue;
+		xMessage.u.xTimerParameters.pxTimer = xTimer;
+
+		if( xCommandID < tmrFIRST_FROM_ISR_COMMAND )
+		{
+			if( xTaskGetSchedulerState() == taskSCHEDULER_RUNNING )
+			{
+				xReturn = xQueueSendToBack( xTimerQueue, &xMessage, xTicksToWait );
+			}
+			else
+			{
+				xReturn = xQueueSendToBack( xTimerQueue, &xMessage, tmrNO_DELAY );
+			}
+		}
+		else
+		{
+			xReturn = xQueueSendToBackFromISR( xTimerQueue, &xMessage, pxHigherPriorityTaskWoken );
+		}
+
+		traceTIMER_COMMAND_SEND( xTimer, xCommandID, xOptionalValue, xReturn );
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+TaskHandle_t xTimerGetTimerDaemonTaskHandle( void )
+{
+	/* If xTimerGetTimerDaemonTaskHandle() is called before the scheduler has been
+	started, then xTimerTaskHandle will be NULL. */
+	configASSERT( ( xTimerTaskHandle != NULL ) );
+	return xTimerTaskHandle;
+}
+/*-----------------------------------------------------------*/
+
+TickType_t xTimerGetPeriod( TimerHandle_t xTimer )
+{
+Timer_t *pxTimer = xTimer;
+
+	configASSERT( xTimer );
+	return pxTimer->xTimerPeriodInTicks;
+}
+/*-----------------------------------------------------------*/
+
+void vTimerSetReloadMode( TimerHandle_t xTimer, const UBaseType_t uxAutoReload )
+{
+Timer_t * pxTimer =  xTimer;
+
+	configASSERT( xTimer );
+	taskENTER_CRITICAL();
+	{
+		if( uxAutoReload != pdFALSE )
+		{
+			pxTimer->ucStatus |= tmrSTATUS_IS_AUTORELOAD;
+		}
+		else
+		{
+			pxTimer->ucStatus &= ~tmrSTATUS_IS_AUTORELOAD;
+		}
+	}
+	taskEXIT_CRITICAL();
+}
+/*-----------------------------------------------------------*/
+
+UBaseType_t uxTimerGetReloadMode( TimerHandle_t xTimer )
+{
+Timer_t * pxTimer =  xTimer;
+UBaseType_t uxReturn;
+
+	configASSERT( xTimer );
+	taskENTER_CRITICAL();
+	{
+		if( ( pxTimer->ucStatus & tmrSTATUS_IS_AUTORELOAD ) == 0 )
+		{
+			/* Not an auto-reload timer. */
+			uxReturn = ( UBaseType_t ) pdFALSE;
+		}
+		else
+		{
+			/* Is an auto-reload timer. */
+			uxReturn = ( UBaseType_t ) pdTRUE;
+		}
+	}
+	taskEXIT_CRITICAL();
+
+	return uxReturn;
+}
+/*-----------------------------------------------------------*/
+
+TickType_t xTimerGetExpiryTime( TimerHandle_t xTimer )
+{
+Timer_t * pxTimer =  xTimer;
+TickType_t xReturn;
+
+	configASSERT( xTimer );
+	xReturn = listGET_LIST_ITEM_VALUE( &( pxTimer->xTimerListItem ) );
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+const char * pcTimerGetName( TimerHandle_t xTimer ) /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+{
+Timer_t *pxTimer = xTimer;
+
+	configASSERT( xTimer );
+	return pxTimer->pcTimerName;
+}
+/*-----------------------------------------------------------*/
+
+static void prvProcessExpiredTimer( const TickType_t xNextExpireTime, const TickType_t xTimeNow )
+{
+BaseType_t xResult;
+Timer_t * const pxTimer = ( Timer_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxCurrentTimerList ); /*lint !e9087 !e9079 void * is used as this macro is used with tasks and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
+
+	/* Remove the timer from the list of active timers.  A check has already
+	been performed to ensure the list is not empty. */
+	( void ) uxListRemove( &( pxTimer->xTimerListItem ) );
+	traceTIMER_EXPIRED( pxTimer );
+
+	/* If the timer is an auto-reload timer then calculate the next
+	expiry time and re-insert the timer in the list of active timers. */
+	if( ( pxTimer->ucStatus & tmrSTATUS_IS_AUTORELOAD ) != 0 )
+	{
+		/* The timer is inserted into a list using a time relative to anything
+		other than the current time.  It will therefore be inserted into the
+		correct list relative to the time this task thinks it is now. */
+		if( prvInsertTimerInActiveList( pxTimer, ( xNextExpireTime + pxTimer->xTimerPeriodInTicks ), xTimeNow, xNextExpireTime ) != pdFALSE )
+		{
+			/* The timer expired before it was added to the active timer
+			list.  Reload it now.  */
+			xResult = xTimerGenericCommand( pxTimer, tmrCOMMAND_START_DONT_TRACE, xNextExpireTime, NULL, tmrNO_DELAY );
+			configASSERT( xResult );
+			( void ) xResult;
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+	else
+	{
+		pxTimer->ucStatus &= ~tmrSTATUS_IS_ACTIVE;
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	/* Call the timer callback. */
+	pxTimer->pxCallbackFunction( ( TimerHandle_t ) pxTimer );
+}
+/*-----------------------------------------------------------*/
+
+static portTASK_FUNCTION( prvTimerTask, pvParameters )
+{
+TickType_t xNextExpireTime;
+BaseType_t xListWasEmpty;
+
+	/* Just to avoid compiler warnings. */
+	( void ) pvParameters;
+
+	#if( configUSE_DAEMON_TASK_STARTUP_HOOK == 1 )
+	{
+		extern void vApplicationDaemonTaskStartupHook( void );
+
+		/* Allow the application writer to execute some code in the context of
+		this task at the point the task starts executing.  This is useful if the
+		application includes initialisation code that would benefit from
+		executing after the scheduler has been started. */
+		vApplicationDaemonTaskStartupHook();
+	}
+	#endif /* configUSE_DAEMON_TASK_STARTUP_HOOK */
+
+	for( ;; )
+	{
+		/* Query the timers list to see if it contains any timers, and if so,
+		obtain the time at which the next timer will expire. */
+		xNextExpireTime = prvGetNextExpireTime( &xListWasEmpty );
+
+		/* If a timer has expired, process it.  Otherwise, block this task
+		until either a timer does expire, or a command is received. */
+		prvProcessTimerOrBlockTask( xNextExpireTime, xListWasEmpty );
+
+		/* Empty the command queue. */
+		prvProcessReceivedCommands();
+	}
+}
+/*-----------------------------------------------------------*/
+
+static void prvProcessTimerOrBlockTask( const TickType_t xNextExpireTime, BaseType_t xListWasEmpty )
+{
+TickType_t xTimeNow;
+BaseType_t xTimerListsWereSwitched;
+
+	vTaskSuspendAll();
+	{
+		/* Obtain the time now to make an assessment as to whether the timer
+		has expired or not.  If obtaining the time causes the lists to switch
+		then don't process this timer as any timers that remained in the list
+		when the lists were switched will have been processed within the
+		prvSampleTimeNow() function. */
+		xTimeNow = prvSampleTimeNow( &xTimerListsWereSwitched );
+		if( xTimerListsWereSwitched == pdFALSE )
+		{
+			/* The tick count has not overflowed, has the timer expired? */
+			if( ( xListWasEmpty == pdFALSE ) && ( xNextExpireTime <= xTimeNow ) )
+			{
+				( void ) xTaskResumeAll();
+				prvProcessExpiredTimer( xNextExpireTime, xTimeNow );
+			}
+			else
+			{
+				/* The tick count has not overflowed, and the next expire
+				time has not been reached yet.  This task should therefore
+				block to wait for the next expire time or a command to be
+				received - whichever comes first.  The following line cannot
+				be reached unless xNextExpireTime > xTimeNow, except in the
+				case when the current timer list is empty. */
+				if( xListWasEmpty != pdFALSE )
+				{
+					/* The current timer list is empty - is the overflow list
+					also empty? */
+					xListWasEmpty = listLIST_IS_EMPTY( pxOverflowTimerList );
+				}
+
+				vQueueWaitForMessageRestricted( xTimerQueue, ( xNextExpireTime - xTimeNow ), xListWasEmpty );
+
+				if( xTaskResumeAll() == pdFALSE )
+				{
+					/* Yield to wait for either a command to arrive, or the
+					block time to expire.  If a command arrived between the
+					critical section being exited and this yield then the yield
+					will not cause the task to block. */
+					portYIELD_WITHIN_API();
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+		}
+		else
+		{
+			( void ) xTaskResumeAll();
+		}
+	}
+}
+/*-----------------------------------------------------------*/
+
+static TickType_t prvGetNextExpireTime( BaseType_t * const pxListWasEmpty )
+{
+TickType_t xNextExpireTime;
+
+	/* Timers are listed in expiry time order, with the head of the list
+	referencing the task that will expire first.  Obtain the time at which
+	the timer with the nearest expiry time will expire.  If there are no
+	active timers then just set the next expire time to 0.  That will cause
+	this task to unblock when the tick count overflows, at which point the
+	timer lists will be switched and the next expiry time can be
+	re-assessed.  */
+	*pxListWasEmpty = listLIST_IS_EMPTY( pxCurrentTimerList );
+	if( *pxListWasEmpty == pdFALSE )
+	{
+		xNextExpireTime = listGET_ITEM_VALUE_OF_HEAD_ENTRY( pxCurrentTimerList );
+	}
+	else
+	{
+		/* Ensure the task unblocks when the tick count rolls over. */
+		xNextExpireTime = ( TickType_t ) 0U;
+	}
+
+	return xNextExpireTime;
+}
+/*-----------------------------------------------------------*/
+
+static TickType_t prvSampleTimeNow( BaseType_t * const pxTimerListsWereSwitched )
+{
+TickType_t xTimeNow;
+PRIVILEGED_DATA static TickType_t xLastTime = ( TickType_t ) 0U; /*lint !e956 Variable is only accessible to one task. */
+
+	xTimeNow = xTaskGetTickCount();
+
+	if( xTimeNow < xLastTime )
+	{
+		prvSwitchTimerLists();
+		*pxTimerListsWereSwitched = pdTRUE;
+	}
+	else
+	{
+		*pxTimerListsWereSwitched = pdFALSE;
+	}
+
+	xLastTime = xTimeNow;
+
+	return xTimeNow;
+}
+/*-----------------------------------------------------------*/
+
+static BaseType_t prvInsertTimerInActiveList( Timer_t * const pxTimer, const TickType_t xNextExpiryTime, const TickType_t xTimeNow, const TickType_t xCommandTime )
+{
+BaseType_t xProcessTimerNow = pdFALSE;
+
+	listSET_LIST_ITEM_VALUE( &( pxTimer->xTimerListItem ), xNextExpiryTime );
+	listSET_LIST_ITEM_OWNER( &( pxTimer->xTimerListItem ), pxTimer );
+
+	if( xNextExpiryTime <= xTimeNow )
+	{
+		/* Has the expiry time elapsed between the command to start/reset a
+		timer was issued, and the time the command was processed? */
+		if( ( ( TickType_t ) ( xTimeNow - xCommandTime ) ) >= pxTimer->xTimerPeriodInTicks ) /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
+		{
+			/* The time between a command being issued and the command being
+			processed actually exceeds the timers period.  */
+			xProcessTimerNow = pdTRUE;
+		}
+		else
+		{
+			vListInsert( pxOverflowTimerList, &( pxTimer->xTimerListItem ) );
+		}
+	}
+	else
+	{
+		if( ( xTimeNow < xCommandTime ) && ( xNextExpiryTime >= xCommandTime ) )
+		{
+			/* If, since the command was issued, the tick count has overflowed
+			but the expiry time has not, then the timer must have already passed
+			its expiry time and should be processed immediately. */
+			xProcessTimerNow = pdTRUE;
+		}
+		else
+		{
+			vListInsert( pxCurrentTimerList, &( pxTimer->xTimerListItem ) );
+		}
+	}
+
+	return xProcessTimerNow;
+}
+/*-----------------------------------------------------------*/
+
+static void	prvProcessReceivedCommands( void )
+{
+DaemonTaskMessage_t xMessage;
+Timer_t *pxTimer;
+BaseType_t xTimerListsWereSwitched, xResult;
+TickType_t xTimeNow;
+
+	while( xQueueReceive( xTimerQueue, &xMessage, tmrNO_DELAY ) != pdFAIL ) /*lint !e603 xMessage does not have to be initialised as it is passed out, not in, and it is not used unless xQueueReceive() returns pdTRUE. */
+	{
+		#if ( INCLUDE_xTimerPendFunctionCall == 1 )
+		{
+			/* Negative commands are pended function calls rather than timer
+			commands. */
+			if( xMessage.xMessageID < ( BaseType_t ) 0 )
+			{
+				const CallbackParameters_t * const pxCallback = &( xMessage.u.xCallbackParameters );
+
+				/* The timer uses the xCallbackParameters member to request a
+				callback be executed.  Check the callback is not NULL. */
+				configASSERT( pxCallback );
+
+				/* Call the function. */
+				pxCallback->pxCallbackFunction( pxCallback->pvParameter1, pxCallback->ulParameter2 );
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		#endif /* INCLUDE_xTimerPendFunctionCall */
+
+		/* Commands that are positive are timer commands rather than pended
+		function calls. */
+		if( xMessage.xMessageID >= ( BaseType_t ) 0 )
+		{
+			/* The messages uses the xTimerParameters member to work on a
+			software timer. */
+			pxTimer = xMessage.u.xTimerParameters.pxTimer;
+
+			if( listIS_CONTAINED_WITHIN( NULL, &( pxTimer->xTimerListItem ) ) == pdFALSE ) /*lint !e961. The cast is only redundant when NULL is passed into the macro. */
+			{
+				/* The timer is in a list, remove it. */
+				( void ) uxListRemove( &( pxTimer->xTimerListItem ) );
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+
+			traceTIMER_COMMAND_RECEIVED( pxTimer, xMessage.xMessageID, xMessage.u.xTimerParameters.xMessageValue );
+
+			/* In this case the xTimerListsWereSwitched parameter is not used, but
+			it must be present in the function call.  prvSampleTimeNow() must be
+			called after the message is received from xTimerQueue so there is no
+			possibility of a higher priority task adding a message to the message
+			queue with a time that is ahead of the timer daemon task (because it
+			pre-empted the timer daemon task after the xTimeNow value was set). */
+			xTimeNow = prvSampleTimeNow( &xTimerListsWereSwitched );
+
+			switch( xMessage.xMessageID )
+			{
+				case tmrCOMMAND_START :
+				case tmrCOMMAND_START_FROM_ISR :
+				case tmrCOMMAND_RESET :
+				case tmrCOMMAND_RESET_FROM_ISR :
+				case tmrCOMMAND_START_DONT_TRACE :
+					/* Start or restart a timer. */
+					pxTimer->ucStatus |= tmrSTATUS_IS_ACTIVE;
+					if( prvInsertTimerInActiveList( pxTimer,  xMessage.u.xTimerParameters.xMessageValue + pxTimer->xTimerPeriodInTicks, xTimeNow, xMessage.u.xTimerParameters.xMessageValue ) != pdFALSE )
+					{
+						/* The timer expired before it was added to the active
+						timer list.  Process it now. */
+						pxTimer->pxCallbackFunction( ( TimerHandle_t ) pxTimer );
+						traceTIMER_EXPIRED( pxTimer );
+
+						if( ( pxTimer->ucStatus & tmrSTATUS_IS_AUTORELOAD ) != 0 )
+						{
+							xResult = xTimerGenericCommand( pxTimer, tmrCOMMAND_START_DONT_TRACE, xMessage.u.xTimerParameters.xMessageValue + pxTimer->xTimerPeriodInTicks, NULL, tmrNO_DELAY );
+							configASSERT( xResult );
+							( void ) xResult;
+						}
+						else
+						{
+							mtCOVERAGE_TEST_MARKER();
+						}
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+					break;
+
+				case tmrCOMMAND_STOP :
+				case tmrCOMMAND_STOP_FROM_ISR :
+					/* The timer has already been removed from the active list. */
+					pxTimer->ucStatus &= ~tmrSTATUS_IS_ACTIVE;
+					break;
+
+				case tmrCOMMAND_CHANGE_PERIOD :
+				case tmrCOMMAND_CHANGE_PERIOD_FROM_ISR :
+					pxTimer->ucStatus |= tmrSTATUS_IS_ACTIVE;
+					pxTimer->xTimerPeriodInTicks = xMessage.u.xTimerParameters.xMessageValue;
+					configASSERT( ( pxTimer->xTimerPeriodInTicks > 0 ) );
+
+					/* The new period does not really have a reference, and can
+					be longer or shorter than the old one.  The command time is
+					therefore set to the current time, and as the period cannot
+					be zero the next expiry time can only be in the future,
+					meaning (unlike for the xTimerStart() case above) there is
+					no fail case that needs to be handled here. */
+					( void ) prvInsertTimerInActiveList( pxTimer, ( xTimeNow + pxTimer->xTimerPeriodInTicks ), xTimeNow, xTimeNow );
+					break;
+
+				case tmrCOMMAND_DELETE :
+					#if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+					{
+						/* The timer has already been removed from the active list,
+						just free up the memory if the memory was dynamically
+						allocated. */
+						if( ( pxTimer->ucStatus & tmrSTATUS_IS_STATICALLY_ALLOCATED ) == ( uint8_t ) 0 )
+						{
+							vPortFree( pxTimer );
+						}
+						else
+						{
+							pxTimer->ucStatus &= ~tmrSTATUS_IS_ACTIVE;
+						}
+					}
+					#else
+					{
+						/* If dynamic allocation is not enabled, the memory
+						could not have been dynamically allocated. So there is
+						no need to free the memory - just mark the timer as
+						"not active". */
+						pxTimer->ucStatus &= ~tmrSTATUS_IS_ACTIVE;
+					}
+					#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
+					break;
+
+				default	:
+					/* Don't expect to get here. */
+					break;
+			}
+		}
+	}
+}
+/*-----------------------------------------------------------*/
+
+static void prvSwitchTimerLists( void )
+{
+TickType_t xNextExpireTime, xReloadTime;
+List_t *pxTemp;
+Timer_t *pxTimer;
+BaseType_t xResult;
+
+	/* The tick count has overflowed.  The timer lists must be switched.
+	If there are any timers still referenced from the current timer list
+	then they must have expired and should be processed before the lists
+	are switched. */
+	while( listLIST_IS_EMPTY( pxCurrentTimerList ) == pdFALSE )
+	{
+		xNextExpireTime = listGET_ITEM_VALUE_OF_HEAD_ENTRY( pxCurrentTimerList );
+
+		/* Remove the timer from the list. */
+		pxTimer = ( Timer_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxCurrentTimerList ); /*lint !e9087 !e9079 void * is used as this macro is used with tasks and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
+		( void ) uxListRemove( &( pxTimer->xTimerListItem ) );
+		traceTIMER_EXPIRED( pxTimer );
+
+		/* Execute its callback, then send a command to restart the timer if
+		it is an auto-reload timer.  It cannot be restarted here as the lists
+		have not yet been switched. */
+		pxTimer->pxCallbackFunction( ( TimerHandle_t ) pxTimer );
+
+		if( ( pxTimer->ucStatus & tmrSTATUS_IS_AUTORELOAD ) != 0 )
+		{
+			/* Calculate the reload value, and if the reload value results in
+			the timer going into the same timer list then it has already expired
+			and the timer should be re-inserted into the current list so it is
+			processed again within this loop.  Otherwise a command should be sent
+			to restart the timer to ensure it is only inserted into a list after
+			the lists have been swapped. */
+			xReloadTime = ( xNextExpireTime + pxTimer->xTimerPeriodInTicks );
+			if( xReloadTime > xNextExpireTime )
+			{
+				listSET_LIST_ITEM_VALUE( &( pxTimer->xTimerListItem ), xReloadTime );
+				listSET_LIST_ITEM_OWNER( &( pxTimer->xTimerListItem ), pxTimer );
+				vListInsert( pxCurrentTimerList, &( pxTimer->xTimerListItem ) );
+			}
+			else
+			{
+				xResult = xTimerGenericCommand( pxTimer, tmrCOMMAND_START_DONT_TRACE, xNextExpireTime, NULL, tmrNO_DELAY );
+				configASSERT( xResult );
+				( void ) xResult;
+			}
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+
+	pxTemp = pxCurrentTimerList;
+	pxCurrentTimerList = pxOverflowTimerList;
+	pxOverflowTimerList = pxTemp;
+}
+/*-----------------------------------------------------------*/
+
+static void prvCheckForValidListAndQueue( void )
+{
+	/* Check that the list from which active timers are referenced, and the
+	queue used to communicate with the timer service, have been
+	initialised. */
+	taskENTER_CRITICAL();
+	{
+		if( xTimerQueue == NULL )
+		{
+			vListInitialise( &xActiveTimerList1 );
+			vListInitialise( &xActiveTimerList2 );
+			pxCurrentTimerList = &xActiveTimerList1;
+			pxOverflowTimerList = &xActiveTimerList2;
+
+			#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+			{
+				/* The timer queue is allocated statically in case
+				configSUPPORT_DYNAMIC_ALLOCATION is 0. */
+				static StaticQueue_t xStaticTimerQueue; /*lint !e956 Ok to declare in this manner to prevent additional conditional compilation guards in other locations. */
+				static uint8_t ucStaticTimerQueueStorage[ ( size_t ) configTIMER_QUEUE_LENGTH * sizeof( DaemonTaskMessage_t ) ]; /*lint !e956 Ok to declare in this manner to prevent additional conditional compilation guards in other locations. */
+
+				xTimerQueue = xQueueCreateStatic( ( UBaseType_t ) configTIMER_QUEUE_LENGTH, ( UBaseType_t ) sizeof( DaemonTaskMessage_t ), &( ucStaticTimerQueueStorage[ 0 ] ), &xStaticTimerQueue );
+			}
+			#else
+			{
+				xTimerQueue = xQueueCreate( ( UBaseType_t ) configTIMER_QUEUE_LENGTH, sizeof( DaemonTaskMessage_t ) );
+			}
+			#endif
+
+			#if ( configQUEUE_REGISTRY_SIZE > 0 )
+			{
+				if( xTimerQueue != NULL )
+				{
+					vQueueAddToRegistry( xTimerQueue, "TmrQ" );
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			#endif /* configQUEUE_REGISTRY_SIZE */
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+	taskEXIT_CRITICAL();
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xTimerIsTimerActive( TimerHandle_t xTimer )
+{
+BaseType_t xReturn;
+Timer_t *pxTimer = xTimer;
+
+	configASSERT( xTimer );
+
+	/* Is the timer in the list of active timers? */
+	taskENTER_CRITICAL();
+	{
+		if( ( pxTimer->ucStatus & tmrSTATUS_IS_ACTIVE ) == 0 )
+		{
+			xReturn = pdFALSE;
+		}
+		else
+		{
+			xReturn = pdTRUE;
+		}
+	}
+	taskEXIT_CRITICAL();
+
+	return xReturn;
+} /*lint !e818 Can't be pointer to const due to the typedef. */
+/*-----------------------------------------------------------*/
+
+void *pvTimerGetTimerID( const TimerHandle_t xTimer )
+{
+Timer_t * const pxTimer = xTimer;
+void *pvReturn;
+
+	configASSERT( xTimer );
+
+	taskENTER_CRITICAL();
+	{
+		pvReturn = pxTimer->pvTimerID;
+	}
+	taskEXIT_CRITICAL();
+
+	return pvReturn;
+}
+/*-----------------------------------------------------------*/
+
+void vTimerSetTimerID( TimerHandle_t xTimer, void *pvNewID )
+{
+Timer_t * const pxTimer = xTimer;
+
+	configASSERT( xTimer );
+
+	taskENTER_CRITICAL();
+	{
+		pxTimer->pvTimerID = pvNewID;
+	}
+	taskEXIT_CRITICAL();
+}
+/*-----------------------------------------------------------*/
+
+#if( INCLUDE_xTimerPendFunctionCall == 1 )
+
+	BaseType_t xTimerPendFunctionCallFromISR( PendedFunction_t xFunctionToPend, void *pvParameter1, uint32_t ulParameter2, BaseType_t *pxHigherPriorityTaskWoken )
+	{
+	DaemonTaskMessage_t xMessage;
+	BaseType_t xReturn;
+
+		/* Complete the message with the function parameters and post it to the
+		daemon task. */
+		xMessage.xMessageID = tmrCOMMAND_EXECUTE_CALLBACK_FROM_ISR;
+		xMessage.u.xCallbackParameters.pxCallbackFunction = xFunctionToPend;
+		xMessage.u.xCallbackParameters.pvParameter1 = pvParameter1;
+		xMessage.u.xCallbackParameters.ulParameter2 = ulParameter2;
+
+		xReturn = xQueueSendFromISR( xTimerQueue, &xMessage, pxHigherPriorityTaskWoken );
+
+		tracePEND_FUNC_CALL_FROM_ISR( xFunctionToPend, pvParameter1, ulParameter2, xReturn );
+
+		return xReturn;
+	}
+
+#endif /* INCLUDE_xTimerPendFunctionCall */
+/*-----------------------------------------------------------*/
+
+#if( INCLUDE_xTimerPendFunctionCall == 1 )
+
+	BaseType_t xTimerPendFunctionCall( PendedFunction_t xFunctionToPend, void *pvParameter1, uint32_t ulParameter2, TickType_t xTicksToWait )
+	{
+	DaemonTaskMessage_t xMessage;
+	BaseType_t xReturn;
+
+		/* This function can only be called after a timer has been created or
+		after the scheduler has been started because, until then, the timer
+		queue does not exist. */
+		configASSERT( xTimerQueue );
+
+		/* Complete the message with the function parameters and post it to the
+		daemon task. */
+		xMessage.xMessageID = tmrCOMMAND_EXECUTE_CALLBACK;
+		xMessage.u.xCallbackParameters.pxCallbackFunction = xFunctionToPend;
+		xMessage.u.xCallbackParameters.pvParameter1 = pvParameter1;
+		xMessage.u.xCallbackParameters.ulParameter2 = ulParameter2;
+
+		xReturn = xQueueSendToBack( xTimerQueue, &xMessage, xTicksToWait );
+
+		tracePEND_FUNC_CALL( xFunctionToPend, pvParameter1, ulParameter2, xReturn );
+
+		return xReturn;
+	}
+
+#endif /* INCLUDE_xTimerPendFunctionCall */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TRACE_FACILITY == 1 )
+
+	UBaseType_t uxTimerGetTimerNumber( TimerHandle_t xTimer )
+	{
+		return ( ( Timer_t * ) xTimer )->uxTimerNumber;
+	}
+
+#endif /* configUSE_TRACE_FACILITY */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TRACE_FACILITY == 1 )
+
+	void vTimerSetTimerNumber( TimerHandle_t xTimer, UBaseType_t uxTimerNumber )
+	{
+		( ( Timer_t * ) xTimer )->uxTimerNumber = uxTimerNumber;
+	}
+
+#endif /* configUSE_TRACE_FACILITY */
+/*-----------------------------------------------------------*/
+
+/* This entire source file will be skipped if the application is not configured
+to include software timer functionality.  If you want to include software timer
+functionality then ensure configUSE_TIMERS is set to 1 in FreeRTOSConfig.h. */
+#endif /* configUSE_TIMERS == 1 */
+
+
+
diff --git a/STM32F469NIHX_FLASH.ld b/STM32F469NIHX_FLASH.ld
new file mode 100644
index 0000000..47d3735
--- /dev/null
+++ b/STM32F469NIHX_FLASH.ld
@@ -0,0 +1,206 @@
+/*
+******************************************************************************
+**
+** @file        : LinkerScript.ld
+**
+** @author      : Auto-generated by STM32CubeIDE
+**
+**  Abstract    : Linker script for STM32F469I-DISCO Board embedding STM32F469NIHx Device from stm32f4 series
+**                      2048Kbytes FLASH
+**                      64Kbytes CCMRAM
+**                      320Kbytes RAM
+**
+**                Set heap size, stack size and stack location according
+**                to application requirements.
+**
+**                Set memory bank area and size if external memory is used
+**
+**  Target      : STMicroelectronics STM32
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+******************************************************************************
+** @attention
+**
+** Copyright (c) 2022 STMicroelectronics.
+** All rights reserved.
+**
+** This software is licensed under terms that can be found in the LICENSE file
+** in the root directory of this software component.
+** If no LICENSE file comes with this software, it is provided AS-IS.
+**
+******************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */
+
+_Min_Heap_Size = 0x200 ; /* required amount of heap */
+_Min_Stack_Size = 0x400 ; /* required amount of stack */
+
+/* Memories definition */
+MEMORY
+{
+  CCMRAM    (xrw)    : ORIGIN = 0x10000000,   LENGTH = 64K
+  RAM    (xrw)    : ORIGIN = 0x20000000,   LENGTH = 320K
+  FLASH    (rx)    : ORIGIN = 0x8000000,   LENGTH = 2048K
+}
+
+/* Sections */
+SECTIONS
+{
+  /* The startup code into "FLASH" Rom type memory */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data into "FLASH" Rom type memory */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data into "FLASH" Rom type memory */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab   : {
+    . = ALIGN(4);
+    *(.ARM.extab* .gnu.linkonce.armextab.*)
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM : {
+    . = ALIGN(4);
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+    . = ALIGN(4);
+  } >FLASH
+
+  .preinit_array     :
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  .init_array :
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  .fini_array :
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  /* Used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections into "RAM" Ram type memory */
+  .data :
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+    *(.RamFunc)        /* .RamFunc sections */
+    *(.RamFunc*)       /* .RamFunc* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+
+  } >RAM AT> FLASH
+
+  _siccmram = LOADADDR(.ccmram);
+
+  /* CCM-RAM section
+  *
+  * IMPORTANT NOTE!
+  * If initialized variables will be placed in this section,
+  * the startup code needs to be modified to copy the init-values.
+  */
+  .ccmram :
+  {
+    . = ALIGN(4);
+    _sccmram = .;       /* create a global symbol at ccmram start */
+    *(.ccmram)
+    *(.ccmram*)
+
+    . = ALIGN(4);
+    _eccmram = .;       /* create a global symbol at ccmram end */
+  } >CCMRAM AT> FLASH
+
+  /* Uninitialized data section into "RAM" Ram type memory */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss section */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM
+
+  /* User_heap_stack section, used to check that there is enough "RAM" Ram  type memory left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM
+
+  /* Remove information from the compiler libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+}
diff --git a/STM32F469NIHX_RAM.ld b/STM32F469NIHX_RAM.ld
new file mode 100644
index 0000000..5048a24
--- /dev/null
+++ b/STM32F469NIHX_RAM.ld
@@ -0,0 +1,206 @@
+/*
+******************************************************************************
+**
+** @file        : LinkerScript.ld (debug in RAM dedicated)
+**
+** @author      : Auto-generated by STM32CubeIDE
+**
+**  Abstract    : Linker script for STM32F469I-DISCO Board embedding STM32F469NIHx Device from stm32f4 series
+**                      2048Kbytes FLASH
+**                      64Kbytes CCMRAM
+**                      320Kbytes RAM
+**
+**                Set heap size, stack size and stack location according
+**                to application requirements.
+**
+**                Set memory bank area and size if external memory is used
+**
+**  Target      : STMicroelectronics STM32
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+******************************************************************************
+** @attention
+**
+** Copyright (c) 2022 STMicroelectronics.
+** All rights reserved.
+**
+** This software is licensed under terms that can be found in the LICENSE file
+** in the root directory of this software component.
+** If no LICENSE file comes with this software, it is provided AS-IS.
+**
+******************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */
+
+_Min_Heap_Size = 0x200; /* required amount of heap */
+_Min_Stack_Size = 0x400; /* required amount of stack */
+
+/* Memories definition */
+MEMORY
+{
+  CCMRAM    (xrw)    : ORIGIN = 0x10000000,   LENGTH = 64K
+  RAM    (xrw)    : ORIGIN = 0x20000000,   LENGTH = 320K
+  FLASH    (rx)    : ORIGIN = 0x8000000,   LENGTH = 2048K
+}
+
+/* Sections */
+SECTIONS
+{
+  /* The startup code into "RAM" Ram type memory */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >RAM
+
+  /* The program code and other data into "RAM" Ram type memory */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+    *(.RamFunc)        /* .RamFunc sections */
+    *(.RamFunc*)       /* .RamFunc* sections */
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >RAM
+
+  /* Constant data into "RAM" Ram type memory */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >RAM
+
+  .ARM.extab   : {
+    . = ALIGN(4);
+    *(.ARM.extab* .gnu.linkonce.armextab.*)
+    . = ALIGN(4);
+  } >RAM
+
+  .ARM : {
+    . = ALIGN(4);
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+    . = ALIGN(4);
+  } >RAM
+
+  .preinit_array     :
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+    . = ALIGN(4);
+  } >RAM
+
+  .init_array :
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+    . = ALIGN(4);
+  } >RAM
+
+  .fini_array :
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+    . = ALIGN(4);
+  } >RAM
+
+  /* Used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections into "RAM" Ram type memory */
+  .data :
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+
+  } >RAM
+
+  _siccmram = LOADADDR(.ccmram);
+
+  /* CCM-RAM section
+  *
+  * IMPORTANT NOTE!
+  * If initialized variables will be placed in this section,
+  * the startup code needs to be modified to copy the init-values.
+  */
+  .ccmram :
+  {
+    . = ALIGN(4);
+    _sccmram = .;       /* create a global symbol at ccmram start */
+    *(.ccmram)
+    *(.ccmram*)
+
+    . = ALIGN(4);
+    _eccmram = .;       /* create a global symbol at ccmram end */
+  } >CCMRAM AT> RAM
+
+  /* Uninitialized data section into "RAM" Ram type memory */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss section */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM
+
+  /* User_heap_stack section, used to check that there is enough "RAM" Ram  type memory left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM
+
+  /* Remove information from the compiler libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+}
diff --git a/Src/conf/eez/conf.h b/Src/conf/eez/conf.h
new file mode 100644
index 0000000..9f15eae
--- /dev/null
+++ b/Src/conf/eez/conf.h
@@ -0,0 +1,45 @@
+#pragma once
+
+#include <stdint.h>
+
+#if defined(EEZ_PLATFORM_STM32)
+#if CONF_OPTION_FPGA
+static const uint32_t DISPLAY_WIDTH = 800;
+static const uint32_t DISPLAY_HEIGHT = 480;
+#else
+static const uint32_t DISPLAY_WIDTH = 480;
+static const uint32_t DISPLAY_HEIGHT = 272;
+#endif
+static const uint32_t DISPLAY_BPP = 16; // RGB565
+#endif
+
+#if defined(EEZ_PLATFORM_SIMULATOR)
+static const uint32_t DISPLAY_WIDTH = 680;
+static const uint32_t DISPLAY_HEIGHT = 472;
+static const uint32_t DISPLAY_BPP = 32;  // RGBA8888
+
+static const char *TITLE = "Uvitron Integrated Rayven";
+static const char *ICON = "uvitron.png";
+#endif
+
+
+#define MAX_NUM_OF_Y_AXES 18
+#define MAX_NUM_OF_Y_VALUES MAX_NUM_OF_Y_AXES
+
+#define OPTION_KEYBOARD 0
+#define OPTION_MOUSE 0
+
+#define CUSTOM_VALUE_TYPES
+
+#define DISPLAY_BACKGROUND_LUMINOSITY_STEP_MIN 0
+#define DISPLAY_BACKGROUND_LUMINOSITY_STEP_MAX 20
+#define DISPLAY_BACKGROUND_LUMINOSITY_STEP_DEFAULT 10
+
+#define UTF8_SUPPORT 0
+
+#if defined(EEZ_PLATFORM_STM32)
+static const uint32_t GUI_STATE_BUFFER_SIZE = 64 * 1024;
+#endif
+#if defined(EEZ_PLATFORM_SIMULATOR)
+static const uint32_t GUI_STATE_BUFFER_SIZE = 128 * 1024;
+#endif
diff --git a/Src/conf/eez/gui_conf.h b/Src/conf/eez/gui_conf.h
new file mode 100644
index 0000000..043e5cf
--- /dev/null
+++ b/Src/conf/eez/gui_conf.h
@@ -0,0 +1,10 @@
+#pragma once
+
+#include "../../gui/document.h"
+
+#define PAGE_ID_ASYNC_OPERATION_IN_PROGRESS 0
+#define COLOR_ID_BOOKMARK 0
+
+/// Maximum allowed length (including label) of the keypad text.
+#define MAX_KEYPAD_TEXT_LENGTH 128
+#define MAX_KEYPAD_LABEL_LENGTH 64
diff --git a/Src/eez-flow-template-stm32f469i-disco-gui.eez-project b/Src/eez-flow-template-stm32f469i-disco-gui.eez-project
new file mode 100644
index 0000000..0b0a2f7
--- /dev/null
+++ b/Src/eez-flow-template-stm32f469i-disco-gui.eez-project
@@ -0,0 +1,2589 @@
+{
+  "settings": {
+    "general": {
+      "projectVersion": "v3",
+      "projectType": "firmware-module",
+      "imports": [
+        {
+          "projectFilePath": "eez-flow-template-stm32f469i-disco.eez-project"
+        }
+      ],
+      "flowSupport": true,
+      "displayWidth": 480,
+      "displayHeight": 272
+    },
+    "build": {
+      "configurations": [
+        {
+          "name": "stm32"
+        },
+        {
+          "name": "simulator"
+        }
+      ],
+      "files": []
+    }
+  },
+  "variables": {
+    "globalVariables": [
+      {
+        "id": 1,
+        "name": "alert_message",
+        "description": "Message in alert dialog",
+        "type": "string",
+        "defaultValue": "\"Are you sure?\"",
+        "native": true
+      },
+      {
+        "id": 2,
+        "name": "touch_calibration_point",
+        "type": "enum:Touch_calibration_point",
+        "defaultValue": "0",
+        "native": true
+      },
+      {
+        "id": 3,
+        "name": "keypad_text",
+        "type": "string",
+        "defaultValue": "\"\"",
+        "persistent": false,
+        "native": true
+      },
+      {
+        "id": 4,
+        "name": "keypad_edit_unit",
+        "type": "string",
+        "defaultValue": "\"\"",
+        "persistent": false,
+        "native": true
+      },
+      {
+        "id": 5,
+        "name": "keypad_sign_enabled",
+        "type": "boolean",
+        "defaultValue": "false",
+        "persistent": false,
+        "native": true
+      },
+      {
+        "id": 6,
+        "name": "keypad_unit_enabled",
+        "type": "boolean",
+        "defaultValue": "false",
+        "persistent": false,
+        "native": true
+      },
+      {
+        "id": 7,
+        "name": "keypad_dot_enabled",
+        "type": "boolean",
+        "defaultValue": "false",
+        "persistent": false,
+        "native": true
+      },
+      {
+        "id": 8,
+        "name": "keypad_option1_enabled",
+        "type": "boolean",
+        "defaultValue": "false",
+        "persistent": false,
+        "native": true
+      },
+      {
+        "id": 9,
+        "name": "keypad_option1_text",
+        "type": "string",
+        "defaultValue": "\"\"",
+        "persistent": false,
+        "native": true
+      },
+      {
+        "id": 10,
+        "name": "keypad_option2_enabled",
+        "type": "boolean",
+        "defaultValue": "false",
+        "persistent": false,
+        "native": true
+      },
+      {
+        "id": 11,
+        "name": "keypad_option2_text",
+        "type": "string",
+        "defaultValue": "\"\"",
+        "persistent": false,
+        "native": true
+      },
+      {
+        "id": 12,
+        "name": "keypad_option3_enabled",
+        "type": "boolean",
+        "defaultValue": "false",
+        "persistent": false,
+        "native": true
+      },
+      {
+        "id": 13,
+        "name": "keypad_option3_text",
+        "type": "string",
+        "defaultValue": "\"\"",
+        "persistent": false,
+        "native": true
+      },
+      {
+        "id": 14,
+        "name": "keypad_mode",
+        "type": "integer",
+        "defaultValue": "0",
+        "persistent": false,
+        "native": true
+      },
+      {
+        "id": 15,
+        "name": "keypad_ok_enabled",
+        "type": "boolean",
+        "defaultValue": "false",
+        "persistent": false,
+        "native": true
+      }
+    ],
+    "structures": [],
+    "enums": [
+      {
+        "name": "Touch_calibration_point",
+        "members": [
+          {
+            "name": "Top left",
+            "value": 0
+          },
+          {
+            "name": "Bottom right",
+            "value": 1
+          },
+          {
+            "name": "Top right",
+            "value": 2
+          }
+        ]
+      }
+    ]
+  },
+  "actions": [
+    {
+      "components": [],
+      "connectionLines": [],
+      "localVariables": [],
+      "id": 1,
+      "name": "yes",
+      "implementationType": "native"
+    },
+    {
+      "components": [],
+      "connectionLines": [],
+      "localVariables": [],
+      "id": 2,
+      "name": "no",
+      "implementationType": "native"
+    },
+    {
+      "components": [],
+      "connectionLines": [],
+      "localVariables": [],
+      "id": 3,
+      "name": "cancel",
+      "implementationType": "native"
+    },
+    {
+      "components": [],
+      "connectionLines": [],
+      "localVariables": [],
+      "id": 4,
+      "name": "edit",
+      "implementationType": "native"
+    },
+    {
+      "components": [],
+      "connectionLines": [],
+      "localVariables": [],
+      "id": 5,
+      "name": "drag_overlay",
+      "implementationType": "native"
+    },
+    {
+      "components": [],
+      "connectionLines": [],
+      "localVariables": [],
+      "id": 6,
+      "name": "scroll",
+      "implementationType": "native"
+    },
+    {
+      "components": [],
+      "connectionLines": [],
+      "localVariables": [],
+      "id": 7,
+      "name": "keypad_key",
+      "implementationType": "native"
+    },
+    {
+      "components": [],
+      "connectionLines": [],
+      "localVariables": [],
+      "id": 8,
+      "name": "keypad_back",
+      "implementationType": "native"
+    },
+    {
+      "components": [],
+      "connectionLines": [],
+      "localVariables": [],
+      "id": 9,
+      "name": "keypad_unit",
+      "implementationType": "native"
+    },
+    {
+      "components": [],
+      "connectionLines": [],
+      "localVariables": [],
+      "id": 10,
+      "name": "keypad_option1",
+      "implementationType": "native"
+    },
+    {
+      "components": [],
+      "connectionLines": [],
+      "localVariables": [],
+      "id": 11,
+      "name": "keypad_option2",
+      "implementationType": "native"
+    },
+    {
+      "components": [],
+      "connectionLines": [],
+      "localVariables": [],
+      "id": 12,
+      "name": "keypad_option3",
+      "implementationType": "native"
+    },
+    {
+      "components": [],
+      "connectionLines": [],
+      "localVariables": [],
+      "id": 13,
+      "name": "keypad_sign",
+      "implementationType": "native"
+    },
+    {
+      "components": [],
+      "connectionLines": [],
+      "localVariables": [],
+      "id": 14,
+      "name": "keypad_ok",
+      "implementationType": "native"
+    },
+    {
+      "components": [],
+      "connectionLines": [],
+      "localVariables": [],
+      "id": 15,
+      "name": "keypad_cancel",
+      "implementationType": "native"
+    },
+    {
+      "components": [],
+      "connectionLines": [],
+      "localVariables": [],
+      "id": 16,
+      "name": "toggle_keypad_mode",
+      "implementationType": "native"
+    },
+    {
+      "components": [],
+      "connectionLines": [],
+      "localVariables": [],
+      "id": 17,
+      "name": "keypad_space",
+      "implementationType": "native"
+    }
+  ],
+  "pages": [
+    {
+      "components": [
+        {
+          "type": "Select",
+          "left": 0,
+          "top": 0,
+          "width": 480,
+          "height": 272,
+          "wireID": "29b822b5-0191-44ac-ccfc-b5d473083547",
+          "customInputs": [],
+          "customOutputs": [],
+          "data": "touch_calibration_point",
+          "style": {
+            "inheritFrom": "touch_calibration"
+          },
+          "widgets": [
+            {
+              "type": "Container",
+              "left": 0,
+              "top": 0,
+              "width": 480,
+              "height": 272,
+              "wireID": "7311d830-c36c-464b-ee3a-7d04e357b513",
+              "customInputs": [],
+              "customOutputs": [],
+              "style": {
+                "inheritFrom": "touch_calibration"
+              },
+              "widgets": [
+                {
+                  "type": "MultilineText",
+                  "left": 95,
+                  "top": 98,
+                  "width": 290,
+                  "height": 76,
+                  "wireID": "b835daad-dba0-4ddc-bf30-e59136add4ee",
+                  "customInputs": [],
+                  "customOutputs": [],
+                  "data": "\"Touch top-left cross in the center until change color\"",
+                  "style": {
+                    "inheritFrom": "note_M"
+                  }
+                },
+                {
+                  "type": "Text",
+                  "left": 0,
+                  "top": 0,
+                  "width": 35,
+                  "height": 35,
+                  "wireID": "6279d14d-f079-4b71-b03f-a45ef374be16",
+                  "customInputs": [],
+                  "customOutputs": [],
+                  "data": "\"+\"",
+                  "action": "",
+                  "style": {
+                    "inheritFrom": "touch_calibration_point",
+                    "activeBackgroundColor": "#000000"
+                  }
+                }
+              ]
+            },
+            {
+              "type": "Container",
+              "left": 0,
+              "top": 0,
+              "width": 480,
+              "height": 272,
+              "wireID": "6e7b9361-0965-4ca2-9116-613a7b8d9735",
+              "customInputs": [],
+              "customOutputs": [],
+              "style": {
+                "inheritFrom": "touch_calibration"
+              },
+              "widgets": [
+                {
+                  "type": "MultilineText",
+                  "left": 95,
+                  "top": 98,
+                  "width": 290,
+                  "height": 76,
+                  "wireID": "729f4182-e9be-49d4-c1c1-2bf4767ac4fd",
+                  "customInputs": [],
+                  "customOutputs": [],
+                  "data": "\"Touch bottom-right cross in the center until change color\"",
+                  "style": {
+                    "inheritFrom": "note_M"
+                  }
+                },
+                {
+                  "type": "Text",
+                  "left": 445,
+                  "top": 237,
+                  "width": 35,
+                  "height": 35,
+                  "wireID": "4a88c334-572d-4f06-a440-9c667eef30e2",
+                  "customInputs": [],
+                  "customOutputs": [],
+                  "data": "\"+\"",
+                  "action": "",
+                  "style": {
+                    "inheritFrom": "touch_calibration_point"
+                  }
+                }
+              ]
+            },
+            {
+              "type": "Container",
+              "left": 0,
+              "top": 0,
+              "width": 480,
+              "height": 272,
+              "wireID": "9ce862b9-9ec4-4173-f463-59bcb854e96d",
+              "customInputs": [],
+              "customOutputs": [],
+              "style": {
+                "inheritFrom": "touch_calibration"
+              },
+              "widgets": [
+                {
+                  "type": "MultilineText",
+                  "left": 95,
+                  "top": 98,
+                  "width": 290,
+                  "height": 76,
+                  "wireID": "1513bc9a-aca5-4cb0-efca-c777e048c478",
+                  "customInputs": [],
+                  "customOutputs": [],
+                  "data": "\"Touch top-right cross in the center until change color\"",
+                  "style": {
+                    "inheritFrom": "note_M"
+                  }
+                },
+                {
+                  "type": "Text",
+                  "left": 445,
+                  "top": 0,
+                  "width": 35,
+                  "height": 35,
+                  "wireID": "3fa9d7e7-d7b3-4d2e-dc14-2b76e0cdd8df",
+                  "customInputs": [],
+                  "customOutputs": [],
+                  "data": "\"+\"",
+                  "action": "",
+                  "style": {
+                    "inheritFrom": "touch_calibration_point"
+                  }
+                }
+              ]
+            }
+          ]
+        }
+      ],
+      "connectionLines": [],
+      "localVariables": [],
+      "id": 2,
+      "name": "touch_calibration",
+      "style": "background",
+      "left": 0,
+      "top": 0,
+      "width": 480,
+      "height": 272
+    },
+    {
+      "components": [
+        {
+          "type": "DisplayData",
+          "left": 0,
+          "top": 82,
+          "width": 480,
+          "height": 40,
+          "wireID": "5ffa4219-e9d1-4160-a8f6-f8bf4cbfadc4",
+          "customInputs": [],
+          "customOutputs": [],
+          "data": "alert_message",
+          "style": {
+            "inheritFrom": "default"
+          },
+          "displayOption": 0
+        },
+        {
+          "type": "Text",
+          "left": 90,
+          "top": 176,
+          "width": 140,
+          "height": 40,
+          "wireID": "15ec65f7-bed9-4a08-b4b5-b91d2e5bd549",
+          "customInputs": [],
+          "customOutputs": [],
+          "data": "\"Yes\"",
+          "action": "yes",
+          "style": {
+            "inheritFrom": "button"
+          }
+        },
+        {
+          "type": "Text",
+          "left": 250,
+          "top": 176,
+          "width": 140,
+          "height": 40,
+          "wireID": "0c230611-18aa-4d6f-d95c-2cffe0881728",
+          "customInputs": [],
+          "customOutputs": [],
+          "data": "\"Start again\"",
+          "action": "no",
+          "style": {
+            "inheritFrom": "button"
+          }
+        }
+      ],
+      "connectionLines": [],
+      "localVariables": [],
+      "id": 3,
+      "name": "touch_calibration_yes_no",
+      "description": "Touchscreen calibration confirmation",
+      "style": "background",
+      "left": 0,
+      "top": 0,
+      "width": 480,
+      "height": 272
+    }
+  ],
+  "styles": [
+    {
+      "id": 1,
+      "name": "default",
+      "description": "",
+      "inheritFrom": "",
+      "font": "medium",
+      "alignHorizontal": "center",
+      "alignVertical": "center",
+      "color": "text",
+      "backgroundColor": "background",
+      "activeColor": "background",
+      "activeBackgroundColor": "text",
+      "borderColor": "border",
+      "padding": "0"
+    },
+    {
+      "id": 2,
+      "name": "info_alert",
+      "inheritFrom": "default",
+      "alwaysBuild": true,
+      "padding": "20",
+      "margin": "20"
+    },
+    {
+      "id": 3,
+      "name": "error_alert",
+      "inheritFrom": "default",
+      "alwaysBuild": true,
+      "color": "dark_text",
+      "backgroundColor": "error",
+      "activeColor": "error",
+      "activeBackgroundColor": "dark_text",
+      "padding": "20",
+      "margin": "20"
+    },
+    {
+      "id": 4,
+      "name": "error_alert_button",
+      "inheritFrom": "button",
+      "alwaysBuild": true,
+      "padding": "8 16 8 16"
+    },
+    {
+      "id": 5,
+      "name": "select_enum_item_popup_container",
+      "inheritFrom": "default",
+      "alwaysBuild": true,
+      "color": "drop_down_list_color",
+      "backgroundColor": "drop_down_list_background",
+      "activeColor": "drop_down_list_background",
+      "activeBackgroundColor": "drop_down_list_color",
+      "padding": "12"
+    },
+    {
+      "id": 6,
+      "name": "select_enum_item_popup_container_S",
+      "inheritFrom": "select_enum_item_popup_container",
+      "alwaysBuild": true
+    },
+    {
+      "id": 7,
+      "name": "select_enum_item_popup_item",
+      "inheritFrom": "select_enum_item_popup_container",
+      "alwaysBuild": true,
+      "padding": "6"
+    },
+    {
+      "id": 8,
+      "name": "select_enum_item_popup_item_S",
+      "inheritFrom": "select_enum_item_popup_container_S",
+      "alwaysBuild": true,
+      "alignHorizontal": "left",
+      "padding": "6"
+    },
+    {
+      "id": 9,
+      "name": "select_enum_item_popup_disabled_item",
+      "inheritFrom": "select_enum_item_popup_item",
+      "alwaysBuild": true,
+      "color": "drop_down_list_color_disabled"
+    },
+    {
+      "id": 10,
+      "name": "select_enum_item_popup_disabled_item_S",
+      "inheritFrom": "select_enum_item_popup_item_S",
+      "alwaysBuild": true,
+      "color": "drop_down_list_color_disabled"
+    },
+    {
+      "id": 11,
+      "name": "menu_with_buttons_message",
+      "inheritFrom": "default",
+      "alwaysBuild": true,
+      "alignVertical": "top",
+      "color": "text",
+      "backgroundColor": "background",
+      "activeColor": "background",
+      "activeBackgroundColor": "text",
+      "padding": "0 0 10 0",
+      "margin": "0"
+    },
+    {
+      "id": 12,
+      "name": "menu_with_buttons_container",
+      "inheritFrom": "default",
+      "alwaysBuild": true,
+      "padding": "20",
+      "margin": "20"
+    },
+    {
+      "id": 13,
+      "name": "menu_with_buttons_button",
+      "inheritFrom": "button",
+      "alwaysBuild": true,
+      "padding": "0 4",
+      "margin": "0"
+    },
+    {
+      "id": 14,
+      "name": "fps_graph",
+      "inheritFrom": "default",
+      "alwaysBuild": true,
+      "color": "#00ff1e",
+      "backgroundColor": "#000000",
+      "borderSize": "1",
+      "borderColor": "backdrop"
+    },
+    {
+      "name": "slider_widget",
+      "inheritFrom": "default",
+      "color": "slider_widget_color",
+      "backgroundColor": "slider_widget_background"
+    },
+    {
+      "name": "background",
+      "inheritFrom": "default",
+      "backgroundColor": "background",
+      "backgroundImage": ""
+    },
+    {
+      "name": "button",
+      "inheritFrom": "default",
+      "color": "button_text",
+      "backgroundColor": "button_background",
+      "activeColor": "button_text",
+      "activeBackgroundColor": "button_active_background",
+      "borderSize": "2",
+      "borderRadius": "8",
+      "borderColor": "button_border"
+    },
+    {
+      "name": "button_disabled",
+      "inheritFrom": "button",
+      "color": "button_disabled_text",
+      "backgroundColor": "button_disabled_background",
+      "activeColor": "button_disabled_text",
+      "activeBackgroundColor": "button_disabled_background",
+      "borderColor": "button_disabled_border"
+    },
+    {
+      "name": "touch_calibration",
+      "inheritFrom": "default",
+      "font": "gui_icons",
+      "color": "#ffffff",
+      "backgroundColor": "#000000",
+      "activeColor": "#000000",
+      "activeBackgroundColor": "#ffffff"
+    },
+    {
+      "name": "touch_calibration_point",
+      "inheritFrom": "touch_calibration",
+      "activeColor": "#00ff00",
+      "activeBackgroundColor": "#000000"
+    },
+    {
+      "name": "note_M",
+      "inheritFrom": "default",
+      "color": "dark_text",
+      "backgroundColor": "note"
+    },
+    {
+      "name": "drop_down_list",
+      "inheritFrom": "default",
+      "color": "drop_down_list_color",
+      "backgroundColor": "drop_down_list_background",
+      "activeColor": "drop_down_list_color",
+      "activeBackgroundColor": "drop_down_list_active_background",
+      "borderSize": "2",
+      "borderRadius": "8",
+      "borderColor": "drop_down_list_border"
+    }
+  ],
+  "fonts": [
+    {
+      "id": 1,
+      "name": "shadow",
+      "source": {
+        "filePath": "Oswald-Medium.ttf",
+        "size": 14
+      },
+      "bpp": 8,
+      "height": 20,
+      "ascent": 20,
+      "descent": 0,
+      "glyphs": [
+        {
+          "encoding": 32,
+          "x": 0,
+          "y": 0,
+          "width": 20,
+          "height": 20,
+          "dx": 20,
+          "glyphBitmap": {
+            "width": 20,
+            "height": 20,
+            "pixelArray": "0000000000000000000303030303060606060606000000000000030606060a0a0a0a0a0a0a0a0a0a000000000306060a10101010171717171717171700000003060a10171b1e21212828282828282828000003060a101b000000000000000000000000000000060a101b280000000000000000000000000000030a101b28390000000000000000000000000000060a1721364e000000000000000000000000000006101b2c445f000000000000000000000000000306101e324e7000000000000000000000000000030a102139587a00000000000000000000000000060a10213d5f8400000000000000000000000000060a1728405f8b00000000000000000000000000060a172844668b00000000000000000000000000060a172844668b00000000000000000000000000060a172844668e00000000000000000000000000060a172844668e00000000000000000000000000060a172844668e00000000000000000000000000060a172844668e00000000000000000000000000060a172844668e00000000000000000000000000"
+          }
+        },
+        {
+          "encoding": 33,
+          "x": 0,
+          "y": 0,
+          "width": 20,
+          "height": 20,
+          "dx": 20,
+          "glyphBitmap": {
+            "width": 20,
+            "height": 20,
+            "pixelArray": "06060606060606060606060606060606060606060a0a0a0a0a0a0a0a0a0a0a0a0a0a0a0a0a0a0a0a171717171717171717171717171717171717171728282828282828282828282828282828282828280000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"
+          }
+        },
+        {
+          "encoding": 34,
+          "x": 0,
+          "y": 0,
+          "width": 20,
+          "height": 20,
+          "dx": 20,
+          "glyphBitmap": {
+            "width": 20,
+            "height": 20,
+            "pixelArray": "06060606060603030303030000000000000000000a0a0a0a0a0a0a0a0a0a060606030000000000001717171717171717101010100a06060300000000282828282828282821211e1b17100a0603000000000000000000000000000000001b100a0603000000000000000000000000000000281b100a0600000000000000000000000000000039281b100a0300000000000000000000000000004e3621170a0600000000000000000000000000005f442c1b10060000000000000000000000000000704e321e100603000000000000000000000000007a583921100a0300000000000000000000000000845f3d21100a06000000000000000000000000008b5f4028170a06000000000000000000000000008b664428170a06000000000000000000000000008b664428170a06000000000000000000000000008e664428170a06000000000000000000000000008e664428170a06000000000000000000000000008e664428170a06000000000000000000000000008e664428170a06000000000000000000000000008e664428170a06"
+          }
+        },
+        {
+          "encoding": 35,
+          "x": 0,
+          "y": 0,
+          "width": 20,
+          "height": 20,
+          "dx": 20,
+          "glyphBitmap": {
+            "width": 20,
+            "height": 20,
+            "pixelArray": "060a172844668e00000000000000000000000000060a172844668e00000000000000000000000000060a172844668e00000000000000000000000000060a172844668e00000000000000000000000000060a172844668e00000000000000000000000000060a172844668e00000000000000000000000000060a172844668e00000000000000000000000000060a172844668e00000000000000000000000000060a172844668e00000000000000000000000000060a172844668e00000000000000000000000000060a172844668e00000000000000000000000000060a172844668e00000000000000000000000000060a172844668e00000000000000000000000000060a172844668e00000000000000000000000000060a172844668e00000000000000000000000000060a172844668e00000000000000000000000000060a172844668e00000000000000000000000000060a172844668e00000000000000000000000000060a172844668e00000000000000000000000000060a172844668e00000000000000000000000000"
+          }
+        },
+        {
+          "encoding": 36,
+          "x": 0,
+          "y": 0,
+          "width": 20,
+          "height": 20,
+          "dx": 20,
+          "glyphBitmap": {
+            "width": 20,
+            "height": 20,
+            "pixelArray": "000000000000000000000000008e664428170a06000000000000000000000000008e664428170a06000000000000000000000000008e664428170a06000000000000000000000000008e664428170a06000000000000000000000000008e664428170a06000000000000000000000000008e664428170a06000000000000000000000000008e664428170a06000000000000000000000000008e664428170a06000000000000000000000000008e664428170a06000000000000000000000000008e664428170a06000000000000000000000000008e664428170a06000000000000000000000000008e664428170a06000000000000000000000000008e664428170a06000000000000000000000000008e664428170a06000000000000000000000000008e664428170a06000000000000000000000000008e664428170a06000000000000000000000000008e664428170a06000000000000000000000000008e664428170a06000000000000000000000000008e664428170a06000000000000000000000000008e664428170a06"
+          }
+        },
+        {
+          "encoding": 37,
+          "x": 0,
+          "y": 0,
+          "width": 20,
+          "height": 20,
+          "dx": 20,
+          "glyphBitmap": {
+            "width": 20,
+            "height": 20,
+            "pixelArray": "060a172844668e00000000000000000000000000060a172844668e00000000000000000000000000060a172844668e00000000000000000000000000060a172844668e00000000000000000000000000060a172844668e00000000000000000000000000060a172844668b00000000000000000000000000060a172844668b00000000000000000000000000060a1728405f8b00000000000000000000000000060a10213d5f84f8000000000000000000000000030a102139587ac5fb00000000000000000000000306101e324e708eb0c8ddeaf4f4fbfbfbfbfbfb0006101b2c445f7a99adbeccd2d6dddddddddddd00060a1721364e667a8e9faab0b4b4b4b4b4b4b400030a101b28394e5f707a84888b8b8b8e8e8e8e0000060a101b2836444e585f5f66666666666666000003060a101b212c32393d404444444444444400000003060a10171b1e21212828282828282828000000000306060a101010101717171717171b1b000000000000030606060a0a0a0a0a0a0a0d0d0d000000000000000000030303030306060a0a0a0a"
+          }
+        },
+        {
+          "encoding": 38,
+          "x": 0,
+          "y": 0,
+          "width": 20,
+          "height": 20,
+          "dx": 20,
+          "glyphBitmap": {
+            "width": 20,
+            "height": 20,
+            "pixelArray": "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000fbfbfbfbfbfbfbfbfbfbfbfbfbfbfbfbfbfbfbfbddddddddddddddddddddddddddddddddddddddddb4b4b4b4b4b4b4b4b4b4b4b4b4b4b4b4b4b4b4b48e8e8e8e8e8e8e8e8e8e8e8e8e8e8e8e8e8e8e8e6666666666666666666666666666666666666666444444444444444444444444444444444444444428282828282828282828282828282828282828281b1b1b1b1b1b1b1b1b1b1b1b1b1b1b1b1b1b1b1b0d0d0d0d0d0d0d0d0d0d0d0d0d0d0d0d0d0d0d0d0a0a0a0a0a0a0a0a0a0a0a0a0a0a0a0a0a0a0a0a"
+          }
+        },
+        {
+          "encoding": 39,
+          "x": 0,
+          "y": 0,
+          "width": 20,
+          "height": 20,
+          "dx": 20,
+          "glyphBitmap": {
+            "width": 20,
+            "height": 20,
+            "pixelArray": "000000000000000000000000008e664428170a06000000000000000000000000008e664428170a06000000000000000000000000008e664428170a06000000000000000000000000008e664428170a06000000000000000000000000008e664428170a06000000000000000000000000008b664428170a06000000000000000000000000008b664428170a06000000000000000000000000008b5f4028170a06000000000000000000000000f8845f3d21100a060000000000000000000000fbc57a583921100a03fbfbfbfbfbfbf4f4eaddc8b08e704e321e100603ddddddddddddd6d2ccbead997a5f442c1b100600b4b4b4b4b4b4b4b0aa9f8e7a664e3621170a06008e8e8e8e8b8b8b88847a705f4e39281b100a0300666666666666665f5f584e4436281b100a06000044444444444444403d39322c211b100a06030000282828282828282821211e1b17100a06030000001b17171717171717101010100a060603000000000d0d0a0a0a0a0a0a0a0a060606030000000000000a0a0a0606060303030303000000000000000000"
+          }
+        }
+      ],
+      "alwaysBuild": true
+    },
+    {
+      "name": "gui_icons",
+      "source": {
+        "filePath": "Oswald-Medium.ttf",
+        "size": 14
+      },
+      "bpp": 8,
+      "height": 35,
+      "ascent": 35,
+      "descent": 0,
+      "glyphs": [
+        {
+          "encoding": 32,
+          "x": 0,
+          "y": 0,
+          "width": 0,
+          "height": 0,
+          "dx": 0,
+          "glyphBitmap": {
+            "width": 0,
+            "height": 0,
+            "pixelArray": ""
+          },
+          "source": {
+            "filePath": "Oswald-Medium.ttf",
+            "size": 14,
+            "encoding": 32
+          }
+        },
+        {
+          "encoding": 33,
+          "x": 0,
+          "y": 0,
+          "width": 0,
+          "height": 0,
+          "dx": 0,
+          "glyphBitmap": {
+            "width": 0,
+            "height": 0,
+            "pixelArray": ""
+          },
+          "source": {
+            "filePath": "Oswald-Medium.ttf",
+            "size": 14,
+            "encoding": 33
+          }
+        },
+        {
+          "encoding": 34,
+          "x": 0,
+          "y": 0,
+          "width": 0,
+          "height": 0,
+          "dx": 0,
+          "glyphBitmap": {
+            "width": 0,
+            "height": 0,
+            "pixelArray": ""
+          },
+          "source": {
+            "filePath": "Oswald-Medium.ttf",
+            "size": 14,
+            "encoding": 34
+          }
+        },
+        {
+          "encoding": 35,
+          "x": 0,
+          "y": 0,
+          "width": 0,
+          "height": 0,
+          "dx": 0,
+          "glyphBitmap": {
+            "width": 0,
+            "height": 0,
+            "pixelArray": ""
+          },
+          "source": {
+            "filePath": "Oswald-Medium.ttf",
+            "size": 14,
+            "encoding": 35
+          }
+        },
+        {
+          "encoding": 36,
+          "x": 0,
+          "y": 0,
+          "width": 0,
+          "height": 0,
+          "dx": 0,
+          "glyphBitmap": {
+            "width": 0,
+            "height": 0,
+            "pixelArray": ""
+          },
+          "source": {
+            "filePath": "Oswald-Medium.ttf",
+            "size": 14,
+            "encoding": 36
+          }
+        },
+        {
+          "encoding": 37,
+          "x": 0,
+          "y": 0,
+          "width": 0,
+          "height": 0,
+          "dx": 0,
+          "glyphBitmap": {
+            "width": 0,
+            "height": 0,
+            "pixelArray": ""
+          },
+          "source": {
+            "filePath": "Oswald-Medium.ttf",
+            "size": 14,
+            "encoding": 37
+          }
+        },
+        {
+          "encoding": 38,
+          "x": 0,
+          "y": 0,
+          "width": 0,
+          "height": 0,
+          "dx": 0,
+          "glyphBitmap": {
+            "width": 0,
+            "height": 0,
+            "pixelArray": ""
+          },
+          "source": {
+            "filePath": "Oswald-Medium.ttf",
+            "size": 14,
+            "encoding": 38
+          }
+        },
+        {
+          "encoding": 39,
+          "x": 0,
+          "y": 0,
+          "width": 0,
+          "height": 0,
+          "dx": 0,
+          "glyphBitmap": {
+            "width": 0,
+            "height": 0,
+            "pixelArray": ""
+          },
+          "source": {
+            "filePath": "Oswald-Medium.ttf",
+            "size": 14,
+            "encoding": 39
+          }
+        },
+        {
+          "encoding": 40,
+          "x": 0,
+          "y": 0,
+          "width": 0,
+          "height": 0,
+          "dx": 0,
+          "glyphBitmap": {
+            "width": 0,
+            "height": 0,
+            "pixelArray": ""
+          },
+          "source": {
+            "filePath": "Oswald-Medium.ttf",
+            "size": 14,
+            "encoding": 40
+          }
+        },
+        {
+          "encoding": 41,
+          "x": 0,
+          "y": 0,
+          "width": 0,
+          "height": 0,
+          "dx": 0,
+          "glyphBitmap": {
+            "width": 0,
+            "height": 0,
+            "pixelArray": ""
+          },
+          "source": {
+            "filePath": "Oswald-Medium.ttf",
+            "size": 14,
+            "encoding": 41
+          }
+        },
+        {
+          "encoding": 42,
+          "x": 0,
+          "y": 0,
+          "width": 0,
+          "height": 0,
+          "dx": 0,
+          "glyphBitmap": {
+            "width": 0,
+            "height": 0,
+            "pixelArray": ""
+          },
+          "source": {
+            "filePath": "Oswald-Medium.ttf",
+            "size": 14,
+            "encoding": 42
+          }
+        },
+        {
+          "encoding": 43,
+          "x": 0,
+          "y": 0,
+          "width": 35,
+          "height": 35,
+          "dx": 35,
+          "glyphBitmap": {
+            "width": 35,
+            "height": 35,
+            "pixelArray": "00000000000000000000000000000000ffffff0000000000000000000000000000000000000000000000000000000000000000ffffff0000000000000000000000000000000000000000000000000000000000000000ffffff0000000000000000000000000000000000000000000000000000000000000000ffffff0000000000000000000000000000000000000000000000000000000000000000ffffff0000000000000000000000000000000000000000000000000000000000000000ffffff0000000000000000000000000000000000000000000000000000000000000000ffffff0000000000000000000000000000000000000000000000000000000000000000ffffff0000000000000000000000000000000000000000000000000000000000000000ffffff0000000000000000000000000000000000000000000000000000000000000000ffffff0000000000000000000000000000000000000000000000000000000000000000ffffff0000000000000000000000000000000000000000000000000000000000000000ffffff0000000000000000000000000000000000000000000000000000000000000000ffffff0000000000000000000000000000000000000000000000000000000000000000ffffff0000000000000000000000000000000000000000000000000000000000000000ffffff000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ffffffffffffffffffffffffffffff0000000000ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff0000000000ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff0000000000ffffffffffffffffffffffffffffff000000000000000000000000000000000000000000000000000000000000000000000000000404040404040404040404000000ffffff0000040404040404040404040100000000000000000000000000000000000000ffffff0000000000000000000000000000000000000000000000000000000000000000ffffff0000000000000000000000000000000000000000000000000000000000000000ffffff0000000000000000000000000000000000000000000000000000000000000000ffffff0000000000000000000000000000000000000000000000000000000000000000ffffff0000000000000000000000000000000000000000000000000000000000000000ffffff0000000000000000000000000000000000000000000000000000000000000000ffffff0000000000000000000000000000000000000000000000000000000000000000ffffff0000000000000000000000000000000000000000000000000000000000000000ffffff0000000000000000000000000000000000000000000000000000000000000000ffffff0000000000000000000000000000000000000000000000000000000000000000ffffff0000000000000000000000000000000000000000000000000000000000000000ffffff0000000000000000000000000000000000000000000000000000000000000000ffffff0000000000000000000000000000000000000000000000000000000000000000ffffff00000000000000000000000000000000"
+          },
+          "source": {
+            "filePath": "Oswald-Medium.ttf",
+            "size": 14,
+            "encoding": 43
+          }
+        },
+        {
+          "encoding": 44,
+          "x": 0,
+          "y": 0,
+          "width": 0,
+          "height": 0,
+          "dx": 0,
+          "glyphBitmap": {
+            "width": 0,
+            "height": 0,
+            "pixelArray": ""
+          },
+          "source": {
+            "filePath": "Oswald-Medium.ttf",
+            "size": 14,
+            "encoding": 44
+          }
+        },
+        {
+          "encoding": 45,
+          "x": 0,
+          "y": 0,
+          "width": 0,
+          "height": 0,
+          "dx": 0,
+          "glyphBitmap": {
+            "width": 0,
+            "height": 0,
+            "pixelArray": ""
+          },
+          "source": {
+            "filePath": "Oswald-Medium.ttf",
+            "size": 14,
+            "encoding": 45
+          }
+        },
+        {
+          "encoding": 46,
+          "x": 0,
+          "y": 0,
+          "width": 0,
+          "height": 0,
+          "dx": 0,
+          "glyphBitmap": {
+            "width": 0,
+            "height": 0,
+            "pixelArray": ""
+          },
+          "source": {
+            "filePath": "Oswald-Medium.ttf",
+            "size": 14,
+            "encoding": 46
+          }
+        },
+        {
+          "encoding": 47,
+          "x": 0,
+          "y": 0,
+          "width": 0,
+          "height": 0,
+          "dx": 0,
+          "glyphBitmap": {
+            "width": 0,
+            "height": 0,
+            "pixelArray": ""
+          },
+          "source": {
+            "filePath": "Oswald-Medium.ttf",
+            "size": 14,
+            "encoding": 47
+          }
+        },
+        {
+          "encoding": 48,
+          "x": 0,
+          "y": 0,
+          "width": 0,
+          "height": 0,
+          "dx": 0,
+          "glyphBitmap": {
+            "width": 0,
+            "height": 0,
+            "pixelArray": ""
+          },
+          "source": {
+            "filePath": "Oswald-Medium.ttf",
+            "size": 14,
+            "encoding": 48
+          }
+        },
+        {
+          "encoding": 49,
+          "x": 0,
+          "y": 0,
+          "width": 0,
+          "height": 0,
+          "dx": 0,
+          "glyphBitmap": {
+            "width": 0,
+            "height": 0,
+            "pixelArray": ""
+          },
+          "source": {
+            "filePath": "Oswald-Medium.ttf",
+            "size": 14,
+            "encoding": 49
+          }
+        },
+        {
+          "encoding": 50,
+          "x": 0,
+          "y": 0,
+          "width": 0,
+          "height": 0,
+          "dx": 0,
+          "glyphBitmap": {
+            "width": 0,
+            "height": 0,
+            "pixelArray": ""
+          },
+          "source": {
+            "filePath": "Oswald-Medium.ttf",
+            "size": 14,
+            "encoding": 50
+          }
+        },
+        {
+          "encoding": 51,
+          "x": 0,
+          "y": 0,
+          "width": 0,
+          "height": 0,
+          "dx": 0,
+          "glyphBitmap": {
+            "width": 0,
+            "height": 0,
+            "pixelArray": ""
+          },
+          "source": {
+            "filePath": "Oswald-Medium.ttf",
+            "size": 14,
+            "encoding": 51
+          }
+        },
+        {
+          "encoding": 52,
+          "x": 0,
+          "y": 0,
+          "width": 0,
+          "height": 0,
+          "dx": 0,
+          "glyphBitmap": {
+            "width": 0,
+            "height": 0,
+            "pixelArray": ""
+          },
+          "source": {
+            "filePath": "Oswald-Medium.ttf",
+            "size": 14,
+            "encoding": 52
+          }
+        },
+        {
+          "encoding": 53,
+          "x": 0,
+          "y": 0,
+          "width": 0,
+          "height": 0,
+          "dx": 0,
+          "glyphBitmap": {
+            "width": 0,
+            "height": 0,
+            "pixelArray": ""
+          },
+          "source": {
+            "filePath": "Oswald-Medium.ttf",
+            "size": 14,
+            "encoding": 53
+          }
+        },
+        {
+          "encoding": 54,
+          "x": 0,
+          "y": 0,
+          "width": 0,
+          "height": 0,
+          "dx": 0,
+          "glyphBitmap": {
+            "width": 0,
+            "height": 0,
+            "pixelArray": ""
+          },
+          "source": {
+            "filePath": "Oswald-Medium.ttf",
+            "size": 14,
+            "encoding": 54
+          }
+        },
+        {
+          "encoding": 55,
+          "x": 0,
+          "y": 0,
+          "width": 0,
+          "height": 0,
+          "dx": 0,
+          "glyphBitmap": {
+            "width": 0,
+            "height": 0,
+            "pixelArray": ""
+          },
+          "source": {
+            "filePath": "Oswald-Medium.ttf",
+            "size": 14,
+            "encoding": 55
+          }
+        },
+        {
+          "encoding": 56,
+          "x": 0,
+          "y": 0,
+          "width": 0,
+          "height": 0,
+          "dx": 0,
+          "glyphBitmap": {
+            "width": 0,
+            "height": 0,
+            "pixelArray": ""
+          },
+          "source": {
+            "filePath": "Oswald-Medium.ttf",
+            "size": 14,
+            "encoding": 56
+          }
+        },
+        {
+          "encoding": 57,
+          "x": 0,
+          "y": 0,
+          "width": 0,
+          "height": 0,
+          "dx": 0,
+          "glyphBitmap": {
+            "width": 0,
+            "height": 0,
+            "pixelArray": ""
+          },
+          "source": {
+            "filePath": "Oswald-Medium.ttf",
+            "size": 14,
+            "encoding": 57
+          }
+        },
+        {
+          "encoding": 58,
+          "x": 0,
+          "y": 0,
+          "width": 0,
+          "height": 0,
+          "dx": 0,
+          "glyphBitmap": {
+            "width": 0,
+            "height": 0,
+            "pixelArray": ""
+          },
+          "source": {
+            "filePath": "Oswald-Medium.ttf",
+            "size": 14,
+            "encoding": 58
+          }
+        },
+        {
+          "encoding": 59,
+          "x": 0,
+          "y": 0,
+          "width": 0,
+          "height": 0,
+          "dx": 0,
+          "glyphBitmap": {
+            "width": 0,
+            "height": 0,
+            "pixelArray": ""
+          },
+          "source": {
+            "filePath": "Oswald-Medium.ttf",
+            "size": 14,
+            "encoding": 59
+          }
+        },
+        {
+          "encoding": 60,
+          "x": 0,
+          "y": 0,
+          "width": 0,
+          "height": 0,
+          "dx": 0,
+          "glyphBitmap": {
+            "width": 0,
+            "height": 0,
+            "pixelArray": ""
+          },
+          "source": {
+            "filePath": "Oswald-Medium.ttf",
+            "size": 14,
+            "encoding": 60
+          }
+        },
+        {
+          "encoding": 61,
+          "x": 0,
+          "y": 0,
+          "width": 0,
+          "height": 0,
+          "dx": 0,
+          "glyphBitmap": {
+            "width": 0,
+            "height": 0,
+            "pixelArray": ""
+          },
+          "source": {
+            "filePath": "Oswald-Medium.ttf",
+            "size": 14,
+            "encoding": 61
+          }
+        },
+        {
+          "encoding": 62,
+          "x": 0,
+          "y": 0,
+          "width": 0,
+          "height": 0,
+          "dx": 0,
+          "glyphBitmap": {
+            "width": 0,
+            "height": 0,
+            "pixelArray": ""
+          },
+          "source": {
+            "filePath": "Oswald-Medium.ttf",
+            "size": 14,
+            "encoding": 62
+          }
+        },
+        {
+          "encoding": 63,
+          "x": 0,
+          "y": 0,
+          "width": 0,
+          "height": 0,
+          "dx": 0,
+          "glyphBitmap": {
+            "width": 0,
+            "height": 0,
+            "pixelArray": ""
+          },
+          "source": {
+            "filePath": "Oswald-Medium.ttf",
+            "size": 14,
+            "encoding": 63
+          }
+        },
+        {
+          "encoding": 64,
+          "x": 0,
+          "y": 0,
+          "width": 0,
+          "height": 0,
+          "dx": 0,
+          "glyphBitmap": {
+            "width": 0,
+            "height": 0,
+            "pixelArray": ""
+          },
+          "source": {
+            "filePath": "Oswald-Medium.ttf",
+            "size": 14,
+            "encoding": 64
+          }
+        },
+        {
+          "encoding": 65,
+          "x": 0,
+          "y": 0,
+          "width": 0,
+          "height": 0,
+          "dx": 0,
+          "glyphBitmap": {
+            "width": 0,
+            "height": 0,
+            "pixelArray": ""
+          },
+          "source": {
+            "filePath": "Oswald-Medium.ttf",
+            "size": 14,
+            "encoding": 65
+          }
+        },
+        {
+          "encoding": 66,
+          "x": 0,
+          "y": 0,
+          "width": 0,
+          "height": 0,
+          "dx": 0,
+          "glyphBitmap": {
+            "width": 0,
+            "height": 0,
+            "pixelArray": ""
+          },
+          "source": {
+            "filePath": "Oswald-Medium.ttf",
+            "size": 14,
+            "encoding": 66
+          }
+        },
+        {
+          "encoding": 67,
+          "x": 0,
+          "y": 0,
+          "width": 0,
+          "height": 0,
+          "dx": 0,
+          "glyphBitmap": {
+            "width": 0,
+            "height": 0,
+            "pixelArray": ""
+          },
+          "source": {
+            "filePath": "Oswald-Medium.ttf",
+            "size": 14,
+            "encoding": 67
+          }
+        },
+        {
+          "encoding": 68,
+          "x": 0,
+          "y": 0,
+          "width": 0,
+          "height": 0,
+          "dx": 0,
+          "glyphBitmap": {
+            "width": 0,
+            "height": 0,
+            "pixelArray": ""
+          },
+          "source": {
+            "filePath": "Oswald-Medium.ttf",
+            "size": 14,
+            "encoding": 68
+          }
+        },
+        {
+          "encoding": 69,
+          "x": 0,
+          "y": 0,
+          "width": 0,
+          "height": 0,
+          "dx": 0,
+          "glyphBitmap": {
+            "width": 0,
+            "height": 0,
+            "pixelArray": ""
+          },
+          "source": {
+            "filePath": "Oswald-Medium.ttf",
+            "size": 14,
+            "encoding": 69
+          }
+        },
+        {
+          "encoding": 70,
+          "x": 0,
+          "y": 0,
+          "width": 0,
+          "height": 0,
+          "dx": 0,
+          "glyphBitmap": {
+            "width": 0,
+            "height": 0,
+            "pixelArray": ""
+          },
+          "source": {
+            "filePath": "Oswald-Medium.ttf",
+            "size": 14,
+            "encoding": 70
+          }
+        },
+        {
+          "encoding": 71,
+          "x": 0,
+          "y": 0,
+          "width": 0,
+          "height": 0,
+          "dx": 0,
+          "glyphBitmap": {
+            "width": 0,
+            "height": 0,
+            "pixelArray": ""
+          },
+          "source": {
+            "filePath": "Oswald-Medium.ttf",
+            "size": 14,
+            "encoding": 71
+          }
+        },
+        {
+          "encoding": 72,
+          "x": 0,
+          "y": 0,
+          "width": 0,
+          "height": 0,
+          "dx": 0,
+          "glyphBitmap": {
+            "width": 0,
+            "height": 0,
+            "pixelArray": ""
+          },
+          "source": {
+            "filePath": "Oswald-Medium.ttf",
+            "size": 14,
+            "encoding": 72
+          }
+        },
+        {
+          "encoding": 73,
+          "x": 0,
+          "y": 0,
+          "width": 0,
+          "height": 0,
+          "dx": 0,
+          "glyphBitmap": {
+            "width": 0,
+            "height": 0,
+            "pixelArray": ""
+          },
+          "source": {
+            "filePath": "Oswald-Medium.ttf",
+            "size": 14,
+            "encoding": 73
+          }
+        },
+        {
+          "encoding": 74,
+          "x": 0,
+          "y": 0,
+          "width": 0,
+          "height": 0,
+          "dx": 0,
+          "glyphBitmap": {
+            "width": 0,
+            "height": 0,
+            "pixelArray": ""
+          },
+          "source": {
+            "filePath": "Oswald-Medium.ttf",
+            "size": 14,
+            "encoding": 74
+          }
+        },
+        {
+          "encoding": 75,
+          "x": 0,
+          "y": 0,
+          "width": 0,
+          "height": 0,
+          "dx": 0,
+          "glyphBitmap": {
+            "width": 0,
+            "height": 0,
+            "pixelArray": ""
+          },
+          "source": {
+            "filePath": "Oswald-Medium.ttf",
+            "size": 14,
+            "encoding": 75
+          }
+        },
+        {
+          "encoding": 76,
+          "x": 0,
+          "y": 0,
+          "width": 0,
+          "height": 0,
+          "dx": 0,
+          "glyphBitmap": {
+            "width": 0,
+            "height": 0,
+            "pixelArray": ""
+          },
+          "source": {
+            "filePath": "Oswald-Medium.ttf",
+            "size": 14,
+            "encoding": 76
+          }
+        },
+        {
+          "encoding": 77,
+          "x": 0,
+          "y": 0,
+          "width": 0,
+          "height": 0,
+          "dx": 0,
+          "glyphBitmap": {
+            "width": 0,
+            "height": 0,
+            "pixelArray": ""
+          },
+          "source": {
+            "filePath": "Oswald-Medium.ttf",
+            "size": 14,
+            "encoding": 77
+          }
+        },
+        {
+          "encoding": 78,
+          "x": 0,
+          "y": 0,
+          "width": 0,
+          "height": 0,
+          "dx": 0,
+          "glyphBitmap": {
+            "width": 0,
+            "height": 0,
+            "pixelArray": ""
+          },
+          "source": {
+            "filePath": "Oswald-Medium.ttf",
+            "size": 14,
+            "encoding": 78
+          }
+        },
+        {
+          "encoding": 79,
+          "x": 0,
+          "y": 0,
+          "width": 0,
+          "height": 0,
+          "dx": 0,
+          "glyphBitmap": {
+            "width": 0,
+            "height": 0,
+            "pixelArray": ""
+          },
+          "source": {
+            "filePath": "Oswald-Medium.ttf",
+            "size": 14,
+            "encoding": 79
+          }
+        },
+        {
+          "encoding": 80,
+          "x": 0,
+          "y": 0,
+          "width": 0,
+          "height": 0,
+          "dx": 0,
+          "glyphBitmap": {
+            "width": 0,
+            "height": 0,
+            "pixelArray": ""
+          },
+          "source": {
+            "filePath": "Oswald-Medium.ttf",
+            "size": 14,
+            "encoding": 80
+          }
+        },
+        {
+          "encoding": 81,
+          "x": 0,
+          "y": 0,
+          "width": 0,
+          "height": 0,
+          "dx": 0,
+          "glyphBitmap": {
+            "width": 0,
+            "height": 0,
+            "pixelArray": ""
+          },
+          "source": {
+            "filePath": "Oswald-Medium.ttf",
+            "size": 14,
+            "encoding": 81
+          }
+        },
+        {
+          "encoding": 82,
+          "x": 0,
+          "y": 0,
+          "width": 0,
+          "height": 0,
+          "dx": 0,
+          "glyphBitmap": {
+            "width": 0,
+            "height": 0,
+            "pixelArray": ""
+          },
+          "source": {
+            "filePath": "Oswald-Medium.ttf",
+            "size": 14,
+            "encoding": 82
+          }
+        },
+        {
+          "encoding": 83,
+          "x": 0,
+          "y": 0,
+          "width": 0,
+          "height": 0,
+          "dx": 0,
+          "glyphBitmap": {
+            "width": 0,
+            "height": 0,
+            "pixelArray": ""
+          },
+          "source": {
+            "filePath": "Oswald-Medium.ttf",
+            "size": 14,
+            "encoding": 83
+          }
+        },
+        {
+          "encoding": 84,
+          "x": 0,
+          "y": 0,
+          "width": 0,
+          "height": 0,
+          "dx": 0,
+          "glyphBitmap": {
+            "width": 0,
+            "height": 0,
+            "pixelArray": ""
+          },
+          "source": {
+            "filePath": "Oswald-Medium.ttf",
+            "size": 14,
+            "encoding": 84
+          }
+        },
+        {
+          "encoding": 85,
+          "x": 0,
+          "y": 0,
+          "width": 0,
+          "height": 0,
+          "dx": 0,
+          "glyphBitmap": {
+            "width": 0,
+            "height": 0,
+            "pixelArray": ""
+          },
+          "source": {
+            "filePath": "Oswald-Medium.ttf",
+            "size": 14,
+            "encoding": 85
+          }
+        },
+        {
+          "encoding": 86,
+          "x": 0,
+          "y": 0,
+          "width": 0,
+          "height": 0,
+          "dx": 0,
+          "glyphBitmap": {
+            "width": 0,
+            "height": 0,
+            "pixelArray": ""
+          },
+          "source": {
+            "filePath": "Oswald-Medium.ttf",
+            "size": 14,
+            "encoding": 86
+          }
+        },
+        {
+          "encoding": 87,
+          "x": 0,
+          "y": 0,
+          "width": 0,
+          "height": 0,
+          "dx": 0,
+          "glyphBitmap": {
+            "width": 0,
+            "height": 0,
+            "pixelArray": ""
+          },
+          "source": {
+            "filePath": "Oswald-Medium.ttf",
+            "size": 14,
+            "encoding": 87
+          }
+        },
+        {
+          "encoding": 88,
+          "x": 0,
+          "y": 0,
+          "width": 0,
+          "height": 0,
+          "dx": 0,
+          "glyphBitmap": {
+            "width": 0,
+            "height": 0,
+            "pixelArray": ""
+          },
+          "source": {
+            "filePath": "Oswald-Medium.ttf",
+            "size": 14,
+            "encoding": 88
+          }
+        },
+        {
+          "encoding": 89,
+          "x": 0,
+          "y": 0,
+          "width": 0,
+          "height": 0,
+          "dx": 0,
+          "glyphBitmap": {
+            "width": 0,
+            "height": 0,
+            "pixelArray": ""
+          },
+          "source": {
+            "filePath": "Oswald-Medium.ttf",
+            "size": 14,
+            "encoding": 89
+          }
+        },
+        {
+          "encoding": 90,
+          "x": 0,
+          "y": 0,
+          "width": 0,
+          "height": 0,
+          "dx": 0,
+          "glyphBitmap": {
+            "width": 0,
+            "height": 0,
+            "pixelArray": ""
+          },
+          "source": {
+            "filePath": "Oswald-Medium.ttf",
+            "size": 14,
+            "encoding": 90
+          }
+        },
+        {
+          "encoding": 91,
+          "x": 0,
+          "y": 0,
+          "width": 0,
+          "height": 0,
+          "dx": 0,
+          "glyphBitmap": {
+            "width": 0,
+            "height": 0,
+            "pixelArray": ""
+          },
+          "source": {
+            "filePath": "Oswald-Medium.ttf",
+            "size": 14,
+            "encoding": 91
+          }
+        },
+        {
+          "encoding": 92,
+          "x": 0,
+          "y": 0,
+          "width": 0,
+          "height": 0,
+          "dx": 0,
+          "glyphBitmap": {
+            "width": 0,
+            "height": 0,
+            "pixelArray": ""
+          },
+          "source": {
+            "filePath": "Oswald-Medium.ttf",
+            "size": 14,
+            "encoding": 92
+          }
+        },
+        {
+          "encoding": 93,
+          "x": 0,
+          "y": 0,
+          "width": 0,
+          "height": 0,
+          "dx": 0,
+          "glyphBitmap": {
+            "width": 0,
+            "height": 0,
+            "pixelArray": ""
+          },
+          "source": {
+            "filePath": "Oswald-Medium.ttf",
+            "size": 14,
+            "encoding": 93
+          }
+        },
+        {
+          "encoding": 94,
+          "x": 0,
+          "y": 0,
+          "width": 0,
+          "height": 0,
+          "dx": 0,
+          "glyphBitmap": {
+            "width": 0,
+            "height": 0,
+            "pixelArray": ""
+          },
+          "source": {
+            "filePath": "Oswald-Medium.ttf",
+            "size": 14,
+            "encoding": 94
+          }
+        },
+        {
+          "encoding": 95,
+          "x": 0,
+          "y": 0,
+          "width": 0,
+          "height": 0,
+          "dx": 0,
+          "glyphBitmap": {
+            "width": 0,
+            "height": 0,
+            "pixelArray": ""
+          },
+          "source": {
+            "filePath": "Oswald-Medium.ttf",
+            "size": 14,
+            "encoding": 95
+          }
+        },
+        {
+          "encoding": 96,
+          "x": 0,
+          "y": 0,
+          "width": 0,
+          "height": 0,
+          "dx": 0,
+          "glyphBitmap": {
+            "width": 0,
+            "height": 0,
+            "pixelArray": ""
+          },
+          "source": {
+            "filePath": "Oswald-Medium.ttf",
+            "size": 14,
+            "encoding": 96
+          }
+        },
+        {
+          "encoding": 97,
+          "x": 0,
+          "y": 0,
+          "width": 0,
+          "height": 0,
+          "dx": 0,
+          "glyphBitmap": {
+            "width": 0,
+            "height": 0,
+            "pixelArray": ""
+          },
+          "source": {
+            "filePath": "Oswald-Medium.ttf",
+            "size": 14,
+            "encoding": 97
+          }
+        },
+        {
+          "encoding": 98,
+          "x": 0,
+          "y": 0,
+          "width": 0,
+          "height": 0,
+          "dx": 0,
+          "glyphBitmap": {
+            "width": 0,
+            "height": 0,
+            "pixelArray": ""
+          },
+          "source": {
+            "filePath": "Oswald-Medium.ttf",
+            "size": 14,
+            "encoding": 98
+          }
+        },
+        {
+          "encoding": 99,
+          "x": 0,
+          "y": 0,
+          "width": 0,
+          "height": 0,
+          "dx": 0,
+          "glyphBitmap": {
+            "width": 0,
+            "height": 0,
+            "pixelArray": ""
+          },
+          "source": {
+            "filePath": "Oswald-Medium.ttf",
+            "size": 14,
+            "encoding": 99
+          }
+        },
+        {
+          "encoding": 100,
+          "x": 0,
+          "y": 0,
+          "width": 0,
+          "height": 0,
+          "dx": 0,
+          "glyphBitmap": {
+            "width": 0,
+            "height": 0,
+            "pixelArray": ""
+          },
+          "source": {
+            "filePath": "Oswald-Medium.ttf",
+            "size": 14,
+            "encoding": 100
+          }
+        },
+        {
+          "encoding": 101,
+          "x": 0,
+          "y": 0,
+          "width": 0,
+          "height": 0,
+          "dx": 0,
+          "glyphBitmap": {
+            "width": 0,
+            "height": 0,
+            "pixelArray": ""
+          },
+          "source": {
+            "filePath": "Oswald-Medium.ttf",
+            "size": 14,
+            "encoding": 101
+          }
+        },
+        {
+          "encoding": 102,
+          "x": 0,
+          "y": 0,
+          "width": 0,
+          "height": 0,
+          "dx": 0,
+          "glyphBitmap": {
+            "width": 0,
+            "height": 0,
+            "pixelArray": ""
+          },
+          "source": {
+            "filePath": "Oswald-Medium.ttf",
+            "size": 14,
+            "encoding": 102
+          }
+        },
+        {
+          "encoding": 103,
+          "x": 0,
+          "y": 0,
+          "width": 0,
+          "height": 0,
+          "dx": 0,
+          "glyphBitmap": {
+            "width": 0,
+            "height": 0,
+            "pixelArray": ""
+          },
+          "source": {
+            "filePath": "Oswald-Medium.ttf",
+            "size": 14,
+            "encoding": 103
+          }
+        },
+        {
+          "encoding": 104,
+          "x": 0,
+          "y": 0,
+          "width": 0,
+          "height": 0,
+          "dx": 0,
+          "glyphBitmap": {
+            "width": 0,
+            "height": 0,
+            "pixelArray": ""
+          },
+          "source": {
+            "filePath": "Oswald-Medium.ttf",
+            "size": 14,
+            "encoding": 104
+          }
+        },
+        {
+          "encoding": 105,
+          "x": 0,
+          "y": 0,
+          "width": 0,
+          "height": 0,
+          "dx": 0,
+          "glyphBitmap": {
+            "width": 0,
+            "height": 0,
+            "pixelArray": ""
+          },
+          "source": {
+            "filePath": "Oswald-Medium.ttf",
+            "size": 14,
+            "encoding": 105
+          }
+        },
+        {
+          "encoding": 106,
+          "x": 0,
+          "y": 0,
+          "width": 0,
+          "height": 0,
+          "dx": 0,
+          "glyphBitmap": {
+            "width": 0,
+            "height": 0,
+            "pixelArray": ""
+          },
+          "source": {
+            "filePath": "Oswald-Medium.ttf",
+            "size": 14,
+            "encoding": 106
+          }
+        },
+        {
+          "encoding": 107,
+          "x": 0,
+          "y": 0,
+          "width": 0,
+          "height": 0,
+          "dx": 0,
+          "glyphBitmap": {
+            "width": 0,
+            "height": 0,
+            "pixelArray": ""
+          },
+          "source": {
+            "filePath": "Oswald-Medium.ttf",
+            "size": 14,
+            "encoding": 107
+          }
+        },
+        {
+          "encoding": 108,
+          "x": 0,
+          "y": 0,
+          "width": 0,
+          "height": 0,
+          "dx": 0,
+          "glyphBitmap": {
+            "width": 0,
+            "height": 0,
+            "pixelArray": ""
+          },
+          "source": {
+            "filePath": "Oswald-Medium.ttf",
+            "size": 14,
+            "encoding": 108
+          }
+        },
+        {
+          "encoding": 109,
+          "x": 0,
+          "y": 0,
+          "width": 0,
+          "height": 0,
+          "dx": 0,
+          "glyphBitmap": {
+            "width": 0,
+            "height": 0,
+            "pixelArray": ""
+          },
+          "source": {
+            "filePath": "Oswald-Medium.ttf",
+            "size": 14,
+            "encoding": 109
+          }
+        },
+        {
+          "encoding": 110,
+          "x": 0,
+          "y": 0,
+          "width": 0,
+          "height": 0,
+          "dx": 0,
+          "glyphBitmap": {
+            "width": 0,
+            "height": 0,
+            "pixelArray": ""
+          },
+          "source": {
+            "filePath": "Oswald-Medium.ttf",
+            "size": 14,
+            "encoding": 110
+          }
+        },
+        {
+          "encoding": 111,
+          "x": 0,
+          "y": 0,
+          "width": 0,
+          "height": 0,
+          "dx": 0,
+          "glyphBitmap": {
+            "width": 0,
+            "height": 0,
+            "pixelArray": ""
+          },
+          "source": {
+            "filePath": "Oswald-Medium.ttf",
+            "size": 14,
+            "encoding": 111
+          }
+        },
+        {
+          "encoding": 112,
+          "x": 0,
+          "y": 0,
+          "width": 0,
+          "height": 0,
+          "dx": 0,
+          "glyphBitmap": {
+            "width": 0,
+            "height": 0,
+            "pixelArray": ""
+          },
+          "source": {
+            "filePath": "Oswald-Medium.ttf",
+            "size": 14,
+            "encoding": 112
+          }
+        },
+        {
+          "encoding": 113,
+          "x": 0,
+          "y": 0,
+          "width": 0,
+          "height": 0,
+          "dx": 0,
+          "glyphBitmap": {
+            "width": 0,
+            "height": 0,
+            "pixelArray": ""
+          },
+          "source": {
+            "filePath": "Oswald-Medium.ttf",
+            "size": 14,
+            "encoding": 113
+          }
+        },
+        {
+          "encoding": 114,
+          "x": 0,
+          "y": 0,
+          "width": 0,
+          "height": 0,
+          "dx": 0,
+          "glyphBitmap": {
+            "width": 0,
+            "height": 0,
+            "pixelArray": ""
+          },
+          "source": {
+            "filePath": "Oswald-Medium.ttf",
+            "size": 14,
+            "encoding": 114
+          }
+        },
+        {
+          "encoding": 115,
+          "x": 0,
+          "y": 0,
+          "width": 0,
+          "height": 0,
+          "dx": 0,
+          "glyphBitmap": {
+            "width": 0,
+            "height": 0,
+            "pixelArray": ""
+          },
+          "source": {
+            "filePath": "Oswald-Medium.ttf",
+            "size": 14,
+            "encoding": 115
+          }
+        },
+        {
+          "encoding": 116,
+          "x": 0,
+          "y": 0,
+          "width": 0,
+          "height": 0,
+          "dx": 0,
+          "glyphBitmap": {
+            "width": 0,
+            "height": 0,
+            "pixelArray": ""
+          },
+          "source": {
+            "filePath": "Oswald-Medium.ttf",
+            "size": 14,
+            "encoding": 116
+          }
+        },
+        {
+          "encoding": 117,
+          "x": 0,
+          "y": 0,
+          "width": 0,
+          "height": 0,
+          "dx": 0,
+          "glyphBitmap": {
+            "width": 0,
+            "height": 0,
+            "pixelArray": ""
+          },
+          "source": {
+            "filePath": "Oswald-Medium.ttf",
+            "size": 14,
+            "encoding": 117
+          }
+        },
+        {
+          "encoding": 118,
+          "x": 0,
+          "y": 0,
+          "width": 0,
+          "height": 0,
+          "dx": 0,
+          "glyphBitmap": {
+            "width": 0,
+            "height": 0,
+            "pixelArray": ""
+          },
+          "source": {
+            "filePath": "Oswald-Medium.ttf",
+            "size": 14,
+            "encoding": 118
+          }
+        },
+        {
+          "encoding": 119,
+          "x": 0,
+          "y": 0,
+          "width": 0,
+          "height": 0,
+          "dx": 0,
+          "glyphBitmap": {
+            "width": 0,
+            "height": 0,
+            "pixelArray": ""
+          },
+          "source": {
+            "filePath": "Oswald-Medium.ttf",
+            "size": 14,
+            "encoding": 119
+          }
+        },
+        {
+          "encoding": 120,
+          "x": 0,
+          "y": 0,
+          "width": 0,
+          "height": 0,
+          "dx": 0,
+          "glyphBitmap": {
+            "width": 0,
+            "height": 0,
+            "pixelArray": ""
+          },
+          "source": {
+            "filePath": "Oswald-Medium.ttf",
+            "size": 14,
+            "encoding": 120
+          }
+        },
+        {
+          "encoding": 121,
+          "x": 0,
+          "y": 0,
+          "width": 0,
+          "height": 0,
+          "dx": 0,
+          "glyphBitmap": {
+            "width": 0,
+            "height": 0,
+            "pixelArray": ""
+          },
+          "source": {
+            "filePath": "Oswald-Medium.ttf",
+            "size": 14,
+            "encoding": 121
+          }
+        },
+        {
+          "encoding": 122,
+          "x": 0,
+          "y": 0,
+          "width": 0,
+          "height": 0,
+          "dx": 0,
+          "glyphBitmap": {
+            "width": 0,
+            "height": 0,
+            "pixelArray": ""
+          },
+          "source": {
+            "filePath": "Oswald-Medium.ttf",
+            "size": 14,
+            "encoding": 122
+          }
+        },
+        {
+          "encoding": 123,
+          "x": 0,
+          "y": 0,
+          "width": 0,
+          "height": 0,
+          "dx": 0,
+          "glyphBitmap": {
+            "width": 0,
+            "height": 0,
+            "pixelArray": ""
+          },
+          "source": {
+            "filePath": "Oswald-Medium.ttf",
+            "size": 14,
+            "encoding": 123
+          }
+        },
+        {
+          "encoding": 124,
+          "x": 0,
+          "y": 0,
+          "width": 0,
+          "height": 0,
+          "dx": 0,
+          "glyphBitmap": {
+            "width": 0,
+            "height": 0,
+            "pixelArray": ""
+          },
+          "source": {
+            "filePath": "Oswald-Medium.ttf",
+            "size": 14,
+            "encoding": 124
+          }
+        },
+        {
+          "encoding": 125,
+          "x": 0,
+          "y": 0,
+          "width": 0,
+          "height": 0,
+          "dx": 0,
+          "glyphBitmap": {
+            "width": 0,
+            "height": 0,
+            "pixelArray": ""
+          },
+          "source": {
+            "filePath": "Oswald-Medium.ttf",
+            "size": 14,
+            "encoding": 125
+          }
+        },
+        {
+          "encoding": 126,
+          "x": 0,
+          "y": 0,
+          "width": 0,
+          "height": 0,
+          "dx": 0,
+          "glyphBitmap": {
+            "width": 0,
+            "height": 0,
+            "pixelArray": ""
+          },
+          "source": {
+            "filePath": "Oswald-Medium.ttf",
+            "size": 14,
+            "encoding": 126
+          }
+        },
+        {
+          "encoding": 127,
+          "x": 0,
+          "y": 0,
+          "width": 0,
+          "height": 0,
+          "dx": 0,
+          "glyphBitmap": {
+            "width": 0,
+            "height": 0,
+            "pixelArray": ""
+          },
+          "source": {
+            "filePath": "Oswald-Medium.ttf",
+            "size": 14,
+            "encoding": 127
+          }
+        }
+      ]
+    }
+  ],
+  "bitmaps": [],
+  "colors": [],
+  "themes": []
+}
\ No newline at end of file
diff --git a/Src/eez-flow-template-stm32f469i-disco.eez-project b/Src/eez-flow-template-stm32f469i-disco.eez-project
new file mode 100644
index 0000000..6896c0f
--- /dev/null
+++ b/Src/eez-flow-template-stm32f469i-disco.eez-project
@@ -0,0 +1,1965 @@
+{
+  "settings": {
+    "general": {
+      "projectVersion": "v3",
+      "projectType": "firmware",
+      "imports": [
+        {
+          "projectFilePath": "eez-flow-template-stm32f469i-disco-gui.eez-project"
+        }
+      ],
+      "flowSupport": true,
+      "displayWidth": 800,
+      "displayHeight": 480
+    },
+    "build": {
+      "configurations": [
+        {
+          "name": "default"
+        }
+      ],
+      "files": [
+        {
+          "fileName": "gui/document.h",
+          "template": "#pragma once\n\n#include <eez/gui/data.h>\n#include <eez/gui/widget.h>\n\nnamespace eez {\nnamespace gui {\n\n//${eez-studio DATA_ENUM}\n\n//${eez-studio DATA_FUNCS_DECL}\n\n//${eez-studio DATA_ARRAY_DECL}\n\n//${eez-studio ACTIONS_ENUM}\n\n//${eez-studio ACTIONS_FUNCS_DECL}\n\n//${eez-studio ACTIONS_ARRAY_DECL}\n\n//${eez-studio GUI_FONTS_ENUM}\n\n//${eez-studio GUI_BITMAPS_ENUM}\n\n//${eez-studio GUI_STYLES_ENUM}\n\n//${eez-studio GUI_THEMES_ENUM}\n\n//${eez-studio GUI_COLORS_ENUM}\n\n//${eez-studio GUI_PAGES_ENUM}\n\n//${eez-studio GUI_ASSETS_DECL_COMPRESSED}\n\n} // namespace gui\n} // namespace eez\n"
+        },
+        {
+          "fileName": "gui/document.cpp",
+          "template": "#include \"document.h\"\n\nnamespace eez {\nnamespace gui {\n\n//${eez-studio DATA_ARRAY_DEF}\n\n//${eez-studio ACTIONS_ARRAY_DEF}\n\n//${eez-studio GUI_ASSETS_DEF_COMPRESSED}\n\n} // namespace gui\n} // namespace eez\n"
+        }
+      ],
+      "destinationFolder": "."
+    }
+  },
+  "variables": {
+    "globalVariables": [],
+    "structures": [],
+    "enums": []
+  },
+  "actions": [],
+  "pages": [
+    {
+      "components": [
+        {
+          "type": "TextWidget",
+          "left": 0,
+          "top": 218,
+          "width": 800,
+          "height": 44,
+          "wireID": "eab24b5b-fd70-4464-d05a-d3bf0df7eac9",
+          "customInputs": [],
+          "customOutputs": [],
+          "data": "\"Hello, world!\"",
+          "style": {
+            "inheritFrom": "default"
+          },
+          "timeline": []
+        }
+      ],
+      "connectionLines": [],
+      "localVariables": [],
+      "id": 1,
+      "name": "main",
+      "style": "background",
+      "left": 0,
+      "top": 0,
+      "width": 800,
+      "height": 480
+    },
+    {
+      "components": [],
+      "connectionLines": [],
+      "localVariables": [],
+      "name": "numeric_keypad",
+      "left": 0,
+      "top": 0,
+      "width": 800,
+      "height": 480
+    }
+  ],
+  "styles": [],
+  "fonts": [
+    {
+      "name": "medium",
+      "renderingEngine": "freetype",
+      "source": {
+        "filePath": "Oswald-Medium.ttf",
+        "size": 12
+      },
+      "bpp": 8,
+      "height": 22,
+      "ascent": 18,
+      "descent": 4,
+      "glyphs": [
+        {
+          "encoding": 32,
+          "x": 0,
+          "y": 0,
+          "width": 0,
+          "height": 0,
+          "dx": 4,
+          "glyphBitmap": {
+            "width": 0,
+            "height": 0,
+            "pixelArray": ""
+          },
+          "source": {
+            "filePath": "Oswald-Medium.ttf",
+            "size": 12,
+            "encoding": 32
+          }
+        },
+        {
+          "encoding": 33,
+          "x": 0,
+          "y": 0,
+          "width": 4,
+          "height": 14,
+          "dx": 4,
+          "glyphBitmap": {
+            "width": 4,
+            "height": 14,
+            "pixelArray": "28fcfc1718ffff0508fff20000f8df0000e7cd0000d7ba0000c7a80000b6950000a682000095700000855d0000020200239c9c0538ffff08"
+          },
+          "source": {
+            "filePath": "Oswald-Medium.ttf",
+            "size": 12,
+            "encoding": 33
+          }
+        },
+        {
+          "encoding": 34,
+          "x": 1,
+          "y": 8,
+          "width": 5,
+          "height": 6,
+          "dx": 6,
+          "glyphBitmap": {
+            "width": 5,
+            "height": 6,
+            "pixelArray": "f5f122fccbf8ca20ffa1f89e20ff75f87220ff48f84620ff1b0401010401"
+          },
+          "source": {
+            "filePath": "Oswald-Medium.ttf",
+            "size": 12,
+            "encoding": 34
+          }
+        },
+        {
+          "encoding": 35,
+          "x": 0,
+          "y": 0,
+          "width": 9,
+          "height": 14,
+          "dx": 9,
+          "glyphBitmap": {
+            "width": 9,
+            "height": 14,
+            "pixelArray": "00006cfc7d1efcc80000008fff5c41ffa8000000b1ff3964ff85000000d3ff1687ff620056fcfffffdfffffe0b3ab5ffe7a4f4ffa8060042ffa401f3f4010039beffd49ffff39c055fffffffffffffff0502a9ff435bff8f040100c7ff2078ff6d000000e7fc0498ff4e000008ffe000b8ff2f000025ffc000d8ff100000"
+          },
+          "source": {
+            "filePath": "Oswald-Medium.ttf",
+            "size": 12,
+            "encoding": 35
+          }
+        },
+        {
+          "encoding": 36,
+          "x": 0,
+          "y": -2,
+          "width": 8,
+          "height": 18,
+          "dx": 8,
+          "glyphBitmap": {
+            "width": 8,
+            "height": 18,
+            "pixelArray": "0000001844000000000000308e0000000030bcf7ffd443000febffcdc1fff21358fff40701d5ff6271fff505009acb5652ffff87000000000ce6ffff8c0200000039f4ffffa70500000034e9ffff9f0000000023ddffff490532470023f6ffa86fffd30000adffc83cfffd2100b0ffac03d1ffe2adfeff4c001cadf2ffe4630000000000b7010000000000005a000000"
+          },
+          "source": {
+            "filePath": "Oswald-Medium.ttf",
+            "size": 12,
+            "encoding": 36
+          }
+        },
+        {
+          "encoding": 37,
+          "x": 0,
+          "y": 0,
+          "width": 16,
+          "height": 14,
+          "dx": 16,
+          "glyphBitmap": {
+            "width": 16,
+            "height": 14,
+            "pixelArray": "0043d0f9e381020000c8d6000000000009eeffb3ebff540014fe9200000000003bffc4006cff990059ff4b000000000052ffb10056ffaf00a0f90b000000000052ffb10056ffae01e6bd00000000000039ffc90072ff962eff7500000000000007eaffaeecff4e75ff2e0a6897893700003fd3ffec8201bce601b5fffffffe410000000200000bf9a016ffeb197cffa00000000000004aff5838ffc60043ffc100000000000091fe133bffc50041ffc3000000000000d8ca0026ffdb0155ffaf00000000001fff830002e0ffb2e1ff69000000000065ff3c000036c7faeb9205"
+          },
+          "source": {
+            "filePath": "Oswald-Medium.ttf",
+            "size": 12,
+            "encoding": 37
+          }
+        },
+        {
+          "encoding": 38,
+          "x": 0,
+          "y": 0,
+          "width": 10,
+          "height": 14,
+          "dx": 10,
+          "glyphBitmap": {
+            "width": 10,
+            "height": 14,
+            "pixelArray": "000063dcf7bf380000000039fff6b5ffef0c0000008fff8c00caff4800000094ff8701e3ff3600000054ffbe36ffd90200000005dcfcc2fd40000000000064ffff6400000000000ad2fffe31009ab817008affcaffc604f4fe0902eeff28b7ff8bffca0021fff40129fcffff670016fffb0c02c3ffff480300bcffc8cbfff1ffff30001baff7f0a8177ef630"
+          },
+          "source": {
+            "filePath": "Oswald-Medium.ttf",
+            "size": 12,
+            "encoding": 38
+          }
+        },
+        {
+          "encoding": 39,
+          "x": 1,
+          "y": 8,
+          "width": 3,
+          "height": 6,
+          "dx": 5,
+          "glyphBitmap": {
+            "width": 3,
+            "height": 6,
+            "pixelArray": "d9fc0ddce300dcbb00dc9200dc6900040200"
+          },
+          "source": {
+            "filePath": "Oswald-Medium.ttf",
+            "size": 12,
+            "encoding": 39
+          }
+        },
+        {
+          "encoding": 40,
+          "x": 1,
+          "y": -3,
+          "width": 4,
+          "height": 17,
+          "dx": 5,
+          "glyphBitmap": {
+            "width": 4,
+            "height": 17,
+            "pixelArray": "001badd402cdffb342ffe00588ff9700afff7700c6ff6300d6ff5900dbff5500dcff5400dcff5400d6ff5800c7ff6100b0ff75008aff980042ffdf0502cfffb0001db1d7"
+          },
+          "source": {
+            "filePath": "Oswald-Medium.ttf",
+            "size": 12,
+            "encoding": 40
+          }
+        },
+        {
+          "encoding": 41,
+          "x": 0,
+          "y": -3,
+          "width": 5,
+          "height": 17,
+          "dx": 5,
+          "glyphBitmap": {
+            "width": 5,
+            "height": 17,
+            "pixelArray": "71d552000050f8fe3900007affa7000030ffed01000dffff170001fbff2d0000f0ff3a0000edff410000ecff440000edff420000f0ff3a0001faff2e000cffff170032ffee01007cffa7004ff8fe390073d9540000"
+          },
+          "source": {
+            "filePath": "Oswald-Medium.ttf",
+            "size": 12,
+            "encoding": 41
+          }
+        },
+        {
+          "encoding": 42,
+          "x": 0,
+          "y": 8,
+          "width": 7,
+          "height": 6,
+          "dx": 7,
+          "glyphBitmap": {
+            "width": 7,
+            "height": 6,
+            "pixelArray": "000018fc890000018e2bfc78723d19e6fdfefafe780004a1fff62600002cf88ff698000036c40f878402"
+          },
+          "source": {
+            "filePath": "Oswald-Medium.ttf",
+            "size": 12,
+            "encoding": 42
+          }
+        },
+        {
+          "encoding": 43,
+          "x": 0,
+          "y": 3,
+          "width": 7,
+          "height": 8,
+          "dx": 7,
+          "glyphBitmap": {
+            "width": 7,
+            "height": 8,
+            "pixelArray": "000028fc7b0000000028ff7c0000589cacffcd9c9590fffffffffff403042cff7f0404000028ff7c0000000028ff7c000000000104020000"
+          },
+          "source": {
+            "filePath": "Oswald-Medium.ttf",
+            "size": 12,
+            "encoding": 43
+          }
+        },
+        {
+          "encoding": 44,
+          "x": 0,
+          "y": -3,
+          "width": 3,
+          "height": 6,
+          "dx": 4,
+          "glyphBitmap": {
+            "width": 3,
+            "height": 6,
+            "pixelArray": "0c242354fff454fff4003ae016e16e022c00"
+          },
+          "source": {
+            "filePath": "Oswald-Medium.ttf",
+            "size": 12,
+            "encoding": 44
+          }
+        },
+        {
+          "encoding": 45,
+          "x": 0,
+          "y": 4,
+          "width": 6,
+          "height": 3,
+          "dx": 6,
+          "glyphBitmap": {
+            "width": 6,
+            "height": 3,
+            "pixelArray": "089c9c9c9c0a0cffffffff10010404040401"
+          },
+          "source": {
+            "filePath": "Oswald-Medium.ttf",
+            "size": 12,
+            "encoding": 45
+          }
+        },
+        {
+          "encoding": 46,
+          "x": 0,
+          "y": 0,
+          "width": 4,
+          "height": 3,
+          "dx": 4,
+          "glyphBitmap": {
+            "width": 4,
+            "height": 3,
+            "pixelArray": "0824240238ffff0838ffff08"
+          },
+          "source": {
+            "filePath": "Oswald-Medium.ttf",
+            "size": 12,
+            "encoding": 46
+          }
+        },
+        {
+          "encoding": 47,
+          "x": 0,
+          "y": 0,
+          "width": 7,
+          "height": 14,
+          "dx": 7,
+          "glyphBitmap": {
+            "width": 7,
+            "height": 14,
+            "pixelArray": "00000000a1f20800000002eab60000000032ff6e0000000079ff2700000000c0df010000000dfb98000000004fff500000000096fb0e00000000ddc10000000024ff7a000000006cff3200000000b3ea0200000006f4a30000000041ff5c00000000"
+          },
+          "source": {
+            "filePath": "Oswald-Medium.ttf",
+            "size": 12,
+            "encoding": 47
+          }
+        },
+        {
+          "encoding": 48,
+          "x": 0,
+          "y": 0,
+          "width": 8,
+          "height": 14,
+          "dx": 9,
+          "glyphBitmap": {
+            "width": 8,
+            "height": 14,
+            "pixelArray": "00098de6f9d25900009bffebb2feff480bfaff5200a6ffb734ffff27007cffe33cffff240078ffec3cffff240078ffec3cffff240078ffec3cffff240078ffec3cffff240078ffec3cffff240078ffec35ffff29007dffe40efbff5700abffb80099ffebaffeff4a00098ee9fdd55c00"
+          },
+          "source": {
+            "filePath": "Oswald-Medium.ttf",
+            "size": 12,
+            "encoding": 48
+          }
+        },
+        {
+          "encoding": 49,
+          "x": 1,
+          "y": 0,
+          "width": 6,
+          "height": 14,
+          "dx": 9,
+          "glyphBitmap": {
+            "width": 6,
+            "height": 14,
+            "pixelArray": "00056bf6fc0c4cdcffffff0c88fde1ffff0c210f50ffff0c000050ffff0c000050ffff0c000050ffff0c000050ffff0c000050ffff0c000050ffff0c000050ffff0c000050ffff0c000050ffff0c000050ffff0c"
+          },
+          "source": {
+            "filePath": "Oswald-Medium.ttf",
+            "size": 12,
+            "encoding": 49
+          }
+        },
+        {
+          "encoding": 50,
+          "x": 0,
+          "y": 0,
+          "width": 8,
+          "height": 14,
+          "dx": 9,
+          "glyphBitmap": {
+            "width": 8,
+            "height": 14,
+            "pixelArray": "000685e1fadb74020089fff6b1f9ff6d02f0ff700087ffce1cffff390064fff317a0a01e008bffe9000000000ceaffaa000000008cffff380000002bfbff9d00000001c0ffe7100000005affff540000000fe7ffb0010000008ffff21b00000023fcffd99c9c9c603cffffffffffff9c"
+          },
+          "source": {
+            "filePath": "Oswald-Medium.ttf",
+            "size": 12,
+            "encoding": 50
+          }
+        },
+        {
+          "encoding": 51,
+          "x": 0,
+          "y": 0,
+          "width": 8,
+          "height": 14,
+          "dx": 9,
+          "glyphBitmap": {
+            "width": 8,
+            "height": 14,
+            "pixelArray": "001098e9f8d15b0000b8ffe4b5feff4f25ffff3a00a7ffb84cffff11007dffdc25747406008affc8000000001cd8ff750000006bffff940300000046c6ffea2a0000000001baffa41d5c5c050080ffd84affff170080ffd821ffff6106c0ffaa00c2fffffbffff4b0017a4eefdd76300"
+          },
+          "source": {
+            "filePath": "Oswald-Medium.ttf",
+            "size": 12,
+            "encoding": 51
+          }
+        },
+        {
+          "encoding": 52,
+          "x": 0,
+          "y": 0,
+          "width": 9,
+          "height": 14,
+          "dx": 9,
+          "glyphBitmap": {
+            "width": 9,
+            "height": 14,
+            "pixelArray": "0000001dfafcdd00000000007fffffe00000000003e3ffffe0000000004bffc7ffe000000000b0ff75ffe00000001afcc858ffe00000007bff7558ffe0000002e0ff2258ffe0000045ffcf0058ffe0000064fffffcfefffffc4b63fcfcfcfefffffc4b0000000058ffe000000000000058ffe000000000000058ffe00000"
+          },
+          "source": {
+            "filePath": "Oswald-Medium.ttf",
+            "size": 12,
+            "encoding": 52
+          }
+        },
+        {
+          "encoding": 53,
+          "x": 0,
+          "y": 0,
+          "width": 8,
+          "height": 14,
+          "dx": 9,
+          "glyphBitmap": {
+            "width": 8,
+            "height": 14,
+            "pixelArray": "00dbfcfcfcfcfc6300e2ffb2a4a4a44100e6ff200000000000e9ff170000000000edff0e0000000000f0ffabf3ea890300f4ffebb0fbff6900d0d836008fffc2000000000064ffe400000000005effe926fcfc270064ffd80dfeff4f008affa800b5ffe7a8f8ff440018aef0fdd96100"
+          },
+          "source": {
+            "filePath": "Oswald-Medium.ttf",
+            "size": 12,
+            "encoding": 53
+          }
+        },
+        {
+          "encoding": 54,
+          "x": 0,
+          "y": 0,
+          "width": 9,
+          "height": 14,
+          "dx": 9,
+          "glyphBitmap": {
+            "width": 9,
+            "height": 14,
+            "pixelArray": "000276dff9dd820400006afff9aff4ff7c0000d8ff7b007affd5000fffff4c0031887f0022ffff3d000000000024ffff5f899244000024fffffcffffff5a0024ffff9310afffcd0024ffff3c005dfffc0323ffff3c0052ffff0913ffff420057fff60100dbff740086ffc1000068fff5a9f7ff5400000173e1fddd690000"
+          },
+          "source": {
+            "filePath": "Oswald-Medium.ttf",
+            "size": 12,
+            "encoding": 54
+          }
+        },
+        {
+          "encoding": 55,
+          "x": 0,
+          "y": 0,
+          "width": 7,
+          "height": 14,
+          "dx": 9,
+          "glyphBitmap": {
+            "width": 7,
+            "height": 14,
+            "pixelArray": "53fcfcfcfcfc9e36a4a4a4e8ff9100000000e1ff5c00000019ffff2600000050ffee0100000088ffb800000000bfff8200000004f4ff4b0000002fffff1500000066ffde000000009effa700000000d6ff7000000010ffff3a00000045fffb090000"
+          },
+          "source": {
+            "filePath": "Oswald-Medium.ttf",
+            "size": 12,
+            "encoding": 55
+          }
+        },
+        {
+          "encoding": 56,
+          "x": 0,
+          "y": 0,
+          "width": 8,
+          "height": 14,
+          "dx": 9,
+          "glyphBitmap": {
+            "width": 8,
+            "height": 14,
+            "pixelArray": "000c95e9f8cb4400009effe9befff92206f6ff4b01d1ff771cffff2300a7ff980cfeff3300b6ff8600b9ff8b1af1ff390020f1ffffff92000088ffe7b9ffe81f1afdff3600b5ff974cfffb03007dffcf4dfff801007affd128ffff2600a8ffab01c2ffdcaeffff480016a4effcd45d00"
+          },
+          "source": {
+            "filePath": "Oswald-Medium.ttf",
+            "size": 12,
+            "encoding": 56
+          }
+        },
+        {
+          "encoding": 57,
+          "x": 0,
+          "y": 0,
+          "width": 8,
+          "height": 14,
+          "dx": 9,
+          "glyphBitmap": {
+            "width": 8,
+            "height": 14,
+            "pixelArray": "00058ae5f8ca4400008fffeab9fffb2e0af6ff5200b8ff9d34ffff200084ffd246ffff19007cffe33effff24007cffe413fdff720fbdffe4009cfffffffeffe40005699f818effe400000000007effe11aa0a014008fffcd10feff4c04caff9900b6fffbe8fffc310014a1ecfcd45000"
+          },
+          "source": {
+            "filePath": "Oswald-Medium.ttf",
+            "size": 12,
+            "encoding": 57
+          }
+        },
+        {
+          "encoding": 58,
+          "x": 1,
+          "y": 0,
+          "width": 3,
+          "height": 9,
+          "dx": 4,
+          "glyphBitmap": {
+            "width": 3,
+            "height": 9,
+            "pixelArray": "959c2cf4ff48040402000000000000000000959c2cf4ff48040402"
+          },
+          "source": {
+            "filePath": "Oswald-Medium.ttf",
+            "size": 12,
+            "encoding": 58
+          }
+        },
+        {
+          "encoding": 59,
+          "x": 1,
+          "y": -2,
+          "width": 3,
+          "height": 12,
+          "dx": 4,
+          "glyphBitmap": {
+            "width": 3,
+            "height": 12,
+            "pixelArray": "f5fc47f8ff482b2c0d00000000000000000023240cf8ff54f8ff5407db42a9cc08150200"
+          },
+          "source": {
+            "filePath": "Oswald-Medium.ttf",
+            "size": 12,
+            "encoding": 59
+          }
+        },
+        {
+          "encoding": 60,
+          "x": 0,
+          "y": 0,
+          "width": 6,
+          "height": 11,
+          "dx": 7,
+          "glyphBitmap": {
+            "width": 6,
+            "height": 11,
+            "pixelArray": "000000000005000000016689000016b2ff94004be9ffc8235ffffd8205007cff940100004ffaffa810000030d4ffe03700000990ff94000000004579000000000001"
+          },
+          "source": {
+            "filePath": "Oswald-Medium.ttf",
+            "size": 12,
+            "encoding": 60
+          }
+        },
+        {
+          "encoding": 61,
+          "x": 0,
+          "y": 4,
+          "width": 7,
+          "height": 6,
+          "dx": 7,
+          "glyphBitmap": {
+            "width": 7,
+            "height": 6,
+            "pixelArray": "039c9c9c9c9c3104ffffffffff5001040404040402039c9c9c9c9c3104ffffffffff5001040404040402"
+          },
+          "source": {
+            "filePath": "Oswald-Medium.ttf",
+            "size": 12,
+            "encoding": 61
+          }
+        },
+        {
+          "encoding": 62,
+          "x": 0,
+          "y": 0,
+          "width": 7,
+          "height": 11,
+          "dx": 7,
+          "glyphBitmap": {
+            "width": 7,
+            "height": 11,
+            "pixelArray": "020300000000000cc421000000000cfff25f010000016bf7ffab130000002ad0ffe6050000001cedff08000047e8ffd104038dfffe8907000cffe13f0000000ca20f0000000001000000000000"
+          },
+          "source": {
+            "filePath": "Oswald-Medium.ttf",
+            "size": 12,
+            "encoding": 62
+          }
+        },
+        {
+          "encoding": 63,
+          "x": 0,
+          "y": 0,
+          "width": 8,
+          "height": 14,
+          "dx": 8,
+          "glyphBitmap": {
+            "width": 8,
+            "height": 14,
+            "pixelArray": "002db9f2f4c23f0009e7ffd3c5fff92836fffe0e01c9ff872afff70700a7ffa60533060001d6ff8b000000003fffff3b0000000dd8ffad00000006b6ffd51000000079ffd8190000000084ff94000000000047884f0000000000162419000000000098ffb0000000000098ffb0000000"
+          },
+          "source": {
+            "filePath": "Oswald-Medium.ttf",
+            "size": 12,
+            "encoding": 63
+          }
+        },
+        {
+          "encoding": 64,
+          "x": 0,
+          "y": -3,
+          "width": 16,
+          "height": 17,
+          "dx": 16,
+          "glyphBitmap": {
+            "width": 16,
+            "height": 17,
+            "pixelArray": "00000000003c9dd4f6f6d289150000000000000da0ffffd5abb1e6ffed3b0000000008c4ffc429000000036dfceb180000007fffb70600000000000076ff92000015f6f6180024b7f4a0fcaf05e3ec02006dff920015e6ffcfd5ff8b0096ff2300adff3f0093ffa90292ff650070ff3700daff0d07f2ff1e00b6ff3f006cff3401faea0035ffdd0000daff19008dff1a06ffdf004bffcd0005faf30102d6de0101faeb0038fff7337cffd9006cff790000deff1406e2fffff5f6fac3ffd50a00009dff640030bfd7576cf2f4a6160000003affe111000000000001010000000000009fffd43700000000010c000000000000069bffffdaaea4bce89a00000000000000003ba0d8fafce0ba6800000000"
+          },
+          "source": {
+            "filePath": "Oswald-Medium.ttf",
+            "size": 12,
+            "encoding": 64
+          }
+        },
+        {
+          "encoding": 65,
+          "x": 0,
+          "y": 0,
+          "width": 9,
+          "height": 14,
+          "dx": 9,
+          "glyphBitmap": {
+            "width": 9,
+            "height": 14,
+            "pixelArray": "000006f5fcd2000000000031fffffd0b0000000064ffffff3a0000000097ffeeff6d00000000caffa0ffa000000006f9ff4dffd300000031ffec0efffd0a000064ffc300e4ff39000097ff9900baff6c0000cafffffcffff9f0006f9ffb9a4c4ffd20031ffff1b003cfffc0964fff0010011ffff3897ffc5000000e6ff6b"
+          },
+          "source": {
+            "filePath": "Oswald-Medium.ttf",
+            "size": 12,
+            "encoding": 65
+          }
+        },
+        {
+          "encoding": 66,
+          "x": 1,
+          "y": 0,
+          "width": 8,
+          "height": 14,
+          "dx": 9,
+          "glyphBitmap": {
+            "width": 8,
+            "height": 14,
+            "pixelArray": "f5fcfcfae5a42100f8ffd5abe4ffe00af8ff88000dedff4df8ff880000c5ff6df8ff880000d8ff5bf8ff880352fff318f8ffffffffe93c00f8ffd5a9e5ffcf17f8ff88000ae2ff8ef8ff8800009fffcbf8ff88000099ffd2f8ff880003d5ffa9f8ffd29fd6fffe3ef8fffffff7c84b00"
+          },
+          "source": {
+            "filePath": "Oswald-Medium.ttf",
+            "size": 12,
+            "encoding": 66
+          }
+        },
+        {
+          "encoding": 67,
+          "x": 0,
+          "y": 0,
+          "width": 9,
+          "height": 14,
+          "dx": 9,
+          "glyphBitmap": {
+            "width": 9,
+            "height": 14,
+            "pixelArray": "00047ad8f8edb225000084fffaaedaffe00703eeff860016ffff4820ffff5d0000fbff6b2fffff580000f8ff7030ffff58000010100730ffff58000000000030ffff58000000000030ffff5800003334172fffff580000f8ff7021ffff5e0001fcff6903efff89001bffff430083fffaabd5ffdb0400037bdffcf2b52500"
+          },
+          "source": {
+            "filePath": "Oswald-Medium.ttf",
+            "size": 12,
+            "encoding": 67
+          }
+        },
+        {
+          "encoding": 68,
+          "x": 1,
+          "y": 0,
+          "width": 8,
+          "height": 14,
+          "dx": 9,
+          "glyphBitmap": {
+            "width": 8,
+            "height": 14,
+            "pixelArray": "f5fcfcfae4a72300f8ffd5a9e8ffe60df8ff880025ffff63f8ff880001f8ff8cf8ff880000f5ff98f8ff880000f4ff98f8ff880000f4ff98f8ff880000f4ff98f8ff880000f4ff98f8ff880000f5ff98f8ff880001fcff88f8ff88002cffff5bf8ffd2a2e6ffe009f8ffffffe9ac2100"
+          },
+          "source": {
+            "filePath": "Oswald-Medium.ttf",
+            "size": 12,
+            "encoding": 68
+          }
+        },
+        {
+          "encoding": 69,
+          "x": 1,
+          "y": 0,
+          "width": 6,
+          "height": 14,
+          "dx": 7,
+          "glyphBitmap": {
+            "width": 6,
+            "height": 14,
+            "pixelArray": "f5fcfcfcfcc9f8ffd5a4a483f8ff88000000f8ff88000000f8ff88000000f8ff88000000f8fffffcfc1cf8ffd5a4a412f8ff88000000f8ff88000000f8ff88000000f8ff88000000f8ffd29c9c82f8ffffffffd4"
+          },
+          "source": {
+            "filePath": "Oswald-Medium.ttf",
+            "size": 12,
+            "encoding": 69
+          }
+        },
+        {
+          "encoding": 70,
+          "x": 1,
+          "y": 0,
+          "width": 6,
+          "height": 14,
+          "dx": 7,
+          "glyphBitmap": {
+            "width": 6,
+            "height": 14,
+            "pixelArray": "f5fcfcfcfcaef8ffd5a4a471f8ff88000000f8ff88000000f8ff88000000f8ff88000000f8fffffcfc0cf8ffd5a4a408f8ff88000000f8ff88000000f8ff88000000f8ff88000000f8ff88000000f8ff88000000"
+          },
+          "source": {
+            "filePath": "Oswald-Medium.ttf",
+            "size": 12,
+            "encoding": 70
+          }
+        },
+        {
+          "encoding": 71,
+          "x": 0,
+          "y": 0,
+          "width": 9,
+          "height": 14,
+          "dx": 9,
+          "glyphBitmap": {
+            "width": 9,
+            "height": 14,
+            "pixelArray": "000377d8f9eeb32c00007ffffab1d6ffeb0f02ecff87000cf9ff5e1dffff5c0000e0ff852dffff58000094ac5f30ffff58000000000030ffff58000000000030ffff5820fcfcfc9a30ffff5815a4dfff9c2dffff580000a5ff9c19ffff610000afff9c01e6ff900005e2ff9c0080fffcafcbf6ff9c000582e4fdd049ff9c"
+          },
+          "source": {
+            "filePath": "Oswald-Medium.ttf",
+            "size": 12,
+            "encoding": 71
+          }
+        },
+        {
+          "encoding": 72,
+          "x": 1,
+          "y": 0,
+          "width": 8,
+          "height": 14,
+          "dx": 10,
+          "glyphBitmap": {
+            "width": 8,
+            "height": 14,
+            "pixelArray": "f1fc8e0000a2fcd9f4ff900000a4ffdcf4ff900000a4ffdcf4ff900000a4ffdcf4ff900000a4ffdcf4ff900000a4ffdcf4fffffcfcffffdcf4ffd8a4a4dfffdcf4ff900000a4ffdcf4ff900000a4ffdcf4ff900000a4ffdcf4ff900000a4ffdcf4ff900000a4ffdcf4ff900000a4ffdc"
+          },
+          "source": {
+            "filePath": "Oswald-Medium.ttf",
+            "size": 12,
+            "encoding": 72
+          }
+        },
+        {
+          "encoding": 73,
+          "x": 1,
+          "y": 0,
+          "width": 3,
+          "height": 14,
+          "dx": 5,
+          "glyphBitmap": {
+            "width": 3,
+            "height": 14,
+            "pixelArray": "e1fc92e4ff94e4ff94e4ff94e4ff94e4ff94e4ff94e4ff94e4ff94e4ff94e4ff94e4ff94e4ff94e4ff94"
+          },
+          "source": {
+            "filePath": "Oswald-Medium.ttf",
+            "size": 12,
+            "encoding": 73
+          }
+        },
+        {
+          "encoding": 74,
+          "x": 0,
+          "y": 0,
+          "width": 5,
+          "height": 14,
+          "dx": 6,
+          "glyphBitmap": {
+            "width": 5,
+            "height": 14,
+            "pixelArray": "0000fcfc7e0000ffff7f0000ffff7f0000ffff7e0000ffff7e0000ffff7e0000ffff7d0000ffff7d0000ffff7c0000ffff7c0002ffff7b002fffff6ca9f4ffff30d8fde37000"
+          },
+          "source": {
+            "filePath": "Oswald-Medium.ttf",
+            "size": 12,
+            "encoding": 74
+          }
+        },
+        {
+          "encoding": 75,
+          "x": 1,
+          "y": 0,
+          "width": 8,
+          "height": 14,
+          "dx": 9,
+          "glyphBitmap": {
+            "width": 8,
+            "height": 14,
+            "pixelArray": "f5fc86000bebfc6df8ff88006afff410f8ff8802dbff9800f8ff884fffff2d00f8ff88c1ffc00000f8ffbcffff540000f8ffffffff1e0000f8ffefefff750000f8ff9198ffd60100f8ff883bffff3600f8ff8801ddff9600f8ff880081ffef08f8ff880025ffff57f8ff880000c7ffb8"
+          },
+          "source": {
+            "filePath": "Oswald-Medium.ttf",
+            "size": 12,
+            "encoding": 75
+          }
+        },
+        {
+          "encoding": 76,
+          "x": 1,
+          "y": 0,
+          "width": 6,
+          "height": 14,
+          "dx": 7,
+          "glyphBitmap": {
+            "width": 6,
+            "height": 14,
+            "pixelArray": "f5fc86000000f8ff88000000f8ff88000000f8ff88000000f8ff88000000f8ff88000000f8ff88000000f8ff88000000f8ff88000000f8ff88000000f8ff88000000f8ff88000000f8ffdfb8b899f8ffffffffd4"
+          },
+          "source": {
+            "filePath": "Oswald-Medium.ttf",
+            "size": 12,
+            "encoding": 76
+          }
+        },
+        {
+          "encoding": 77,
+          "x": 1,
+          "y": 0,
+          "width": 10,
+          "height": 14,
+          "dx": 12,
+          "glyphBitmap": {
+            "width": 10,
+            "height": 14,
+            "pixelArray": "c4fce200000042fcfc5dcbffff1a000078ffff62cfffff4d0000adffff66d4ffff810000e2ffff6bd8fff4b50018fff6ff6fdcffbfe9014dffc0ff73e0ff85ff1d82ff88ff77e5ff4cff51b7e46bff7ce9ff14ff86edaf66ff80edfe00dcdaff7a61ff84f2fa00a7ffff455dff89f6f60072ffff1158ff8dfaf2003dffdb0054ff91feee000bfda6004fff96"
+          },
+          "source": {
+            "filePath": "Oswald-Medium.ttf",
+            "size": 12,
+            "encoding": 77
+          }
+        },
+        {
+          "encoding": 78,
+          "x": 1,
+          "y": 0,
+          "width": 8,
+          "height": 14,
+          "dx": 9,
+          "glyphBitmap": {
+            "width": 8,
+            "height": 14,
+            "pixelArray": "f5ea090000ddfc34f8ff620000e0ff34f8ffcf0100e0ff34f8ffff3b00e0ff34f8ffffa800e0ff34f8fffcfb1ae0ff34f8ffadff82e0ff34f8ff47fee9e7ff34f8ff28b3ffffff34f8ff284affffff34f8ff2803dfffff34f8ff280078ffff34f8ff280016faff34f8ff280000a5ff34"
+          },
+          "source": {
+            "filePath": "Oswald-Medium.ttf",
+            "size": 12,
+            "encoding": 78
+          }
+        },
+        {
+          "encoding": 79,
+          "x": 0,
+          "y": 0,
+          "width": 9,
+          "height": 14,
+          "dx": 10,
+          "glyphBitmap": {
+            "width": 9,
+            "height": 14,
+            "pixelArray": "000479d7f9eeb52e000084fffbb1d5fff01803f0ff87000bf2ff7921ffff5f0000d3ffab2fffff5c0000d0ffbc30ffff5c0000d0ffbc30ffff5c0000d0ffbc30ffff5c0000d0ffbc30ffff5c0000d0ffbc30ffff5c0000d0ffbb1fffff5e0000d3ffaa02ecff850009f2ff790082fff9a9cefff01800047adafcf2be3100"
+          },
+          "source": {
+            "filePath": "Oswald-Medium.ttf",
+            "size": 12,
+            "encoding": 79
+          }
+        },
+        {
+          "encoding": 80,
+          "x": 1,
+          "y": 0,
+          "width": 8,
+          "height": 14,
+          "dx": 9,
+          "glyphBitmap": {
+            "width": 8,
+            "height": 14,
+            "pixelArray": "f5fcfcfcf3ba2c00f8ffd5a8ddffe80ef8ff880010f8ff59f8ff880000dcff7ef8ff880000e5ff7af8ff88024cffff48f8ffffffffffba02f8ffd5a496570400f8ff880000000000f8ff880000000000f8ff880000000000f8ff880000000000f8ff880000000000f8ff880000000000"
+          },
+          "source": {
+            "filePath": "Oswald-Medium.ttf",
+            "size": 12,
+            "encoding": 80
+          }
+        },
+        {
+          "encoding": 81,
+          "x": 0,
+          "y": -3,
+          "width": 9,
+          "height": 17,
+          "dx": 10,
+          "glyphBitmap": {
+            "width": 9,
+            "height": 17,
+            "pixelArray": "000479d7f9eeb52e000084fffbb1d5fff01703f0ff87000bf2ff7821ffff5f0000d3ffab2fffff5c0000d0ffbc30ffff5c0000d0ffbc30ffff5c0000d0ffbc30ffff5c0000d0ffbc30ffff5c0000d0ffbc30ffff5c0000d0ffbb1fffff5e0000d3ffaa02ecff850009f2ff780082fff9a9cefff11800047adafdfffa3a00000000000090ffaa08000000000004acf709000000000000034d00"
+          },
+          "source": {
+            "filePath": "Oswald-Medium.ttf",
+            "size": 12,
+            "encoding": 81
+          }
+        },
+        {
+          "encoding": 82,
+          "x": 1,
+          "y": 0,
+          "width": 8,
+          "height": 14,
+          "dx": 9,
+          "glyphBitmap": {
+            "width": 8,
+            "height": 14,
+            "pixelArray": "f5fcfcf9e3a62700f8ffd5aae8ffeb15f8ff880016fbff69f8ff880000d6ff8cf8ff880001e5ff82f8ff880764ffff50f8ffffffffffb604f8ffd5c0fffa0a00f8ff8820ffff4500f8ff8800deff8d00f8ff88009cffd500f8ff88005affff1df8ff880019ffff64f8ff880000d6ffac"
+          },
+          "source": {
+            "filePath": "Oswald-Medium.ttf",
+            "size": 12,
+            "encoding": 82
+          }
+        },
+        {
+          "encoding": 83,
+          "x": 0,
+          "y": 0,
+          "width": 8,
+          "height": 14,
+          "dx": 8,
+          "glyphBitmap": {
+            "width": 8,
+            "height": 14,
+            "pixelArray": "0016a1ebf7cc490001c8ffdab4fffa272fffff1e00aeff874affff200076d2722dffffb10500000002d0ffffb60c00000026e8ffffca1400000023dbffffc90600000016ccffff74022a520011e5ffd044fff5030089ffed15fdff430088ffd100a1ffefa8f5ff6700098be4fedc6d01"
+          },
+          "source": {
+            "filePath": "Oswald-Medium.ttf",
+            "size": 12,
+            "encoding": 83
+          }
+        },
+        {
+          "encoding": 84,
+          "x": 0,
+          "y": 0,
+          "width": 8,
+          "height": 14,
+          "dx": 7,
+          "glyphBitmap": {
+            "width": 8,
+            "height": 14,
+            "pixelArray": "edfcfcfcfcfcfc1c9aa4defff5a4a4120000a0ffe00000000000a0ffe00000000000a0ffe00000000000a0ffe00000000000a0ffe00000000000a0ffe00000000000a0ffe00000000000a0ffe00000000000a0ffe00000000000a0ffe00000000000a0ffe00000000000a0ffe0000000"
+          },
+          "source": {
+            "filePath": "Oswald-Medium.ttf",
+            "size": 12,
+            "encoding": 84
+          }
+        },
+        {
+          "encoding": 85,
+          "x": 0,
+          "y": 0,
+          "width": 9,
+          "height": 14,
+          "dx": 10,
+          "glyphBitmap": {
+            "width": 9,
+            "height": 14,
+            "pixelArray": "14fcfc5b0000c5fca614ffff5c0000c8ffa814ffff5c0000c8ffa814ffff5c0000c8ffa814ffff5c0000c8ffa814ffff5c0000c8ffa814ffff5c0000c8ffa814ffff5c0000c8ffa814ffff5c0000c8ffa813ffff5c0000c9ffa606ffff630000cfff9600d6ff95000df5ff68006dfffeaed3ffed14000274dbfbf3bc3200"
+          },
+          "source": {
+            "filePath": "Oswald-Medium.ttf",
+            "size": 12,
+            "encoding": 85
+          }
+        },
+        {
+          "encoding": 86,
+          "x": 0,
+          "y": 0,
+          "width": 9,
+          "height": 14,
+          "dx": 9,
+          "glyphBitmap": {
+            "width": 9,
+            "height": 14,
+            "pixelArray": "81fcb1000001eefc4e51ffe2000020ffff1c1effff13004dffe90101ecff42007affb60000b9ff7100a7ff82000086ffa100d4ff4f000053ffd007fcff1c000020fffa35ffe901000001edff8bffb600000000baffe5ff820000000087ffffff4f0000000054ffffff1c0000000021ffffe9010000000001eeffb6000000"
+          },
+          "source": {
+            "filePath": "Oswald-Medium.ttf",
+            "size": 12,
+            "encoding": 86
+          }
+        },
+        {
+          "encoding": 87,
+          "x": 0,
+          "y": 0,
+          "width": 12,
+          "height": 14,
+          "dx": 12,
+          "glyphBitmap": {
+            "width": 12,
+            "height": 14,
+            "pixelArray": "5efcb90000cefb0b007bfc903bffdb0003f8ff33009cff6e17fffa0224ffff5d00bcff4a01f3ff1b4effff8800dcff2600cfff3b77fffcb202fafd0600abff5aa1fac2dd1bffde000087ff7acbd394fe45ffba000063ff9bf4a869ff8cff9600003fffd8ff7e3fffd7ff7200001bffffff5314ffffff4e000002f6ffff2900eaffff2a000000d3fffa0500bffffe08000000afffd4000095ffe2000000008bffa900006affbe0000"
+          },
+          "source": {
+            "filePath": "Oswald-Medium.ttf",
+            "size": 12,
+            "encoding": 87
+          }
+        },
+        {
+          "encoding": 88,
+          "x": 0,
+          "y": 0,
+          "width": 9,
+          "height": 14,
+          "dx": 8,
+          "glyphBitmap": {
+            "width": 9,
+            "height": 14,
+            "pixelArray": "8bfcc9000040fce70627ffff35009bff900000bdff9f07efff30000054fff761ffcf00000005e7fff4ff6e0000000083fffffa14000000002bffffad000000000067ffffa80000000000c7fffffa1700000027fff3e1ff7900000086ff9f78ffdf030003e4ff4316f9ff4a0045ffe40300a4ffb300a5ff8a00003afffe1f"
+          },
+          "source": {
+            "filePath": "Oswald-Medium.ttf",
+            "size": 12,
+            "encoding": 88
+          }
+        },
+        {
+          "encoding": 89,
+          "x": 0,
+          "y": 0,
+          "width": 9,
+          "height": 14,
+          "dx": 8,
+          "glyphBitmap": {
+            "width": 9,
+            "height": 14,
+            "pixelArray": "adfca4000050fcf0085effef05009bffaa0011fbff4101e5ff580000b8ff8f30fff90e000065ffde7bffb400000016fdffe4ff6200000000c0fffffd14000000006dffffbe00000000001dffff71000000000008ffff5c000000000008ffff5c000000000008ffff5c000000000008ffff5c000000000008ffff5c000000"
+          },
+          "source": {
+            "filePath": "Oswald-Medium.ttf",
+            "size": 12,
+            "encoding": 89
+          }
+        },
+        {
+          "encoding": 90,
+          "x": 0,
+          "y": 0,
+          "width": 7,
+          "height": 14,
+          "dx": 7,
+          "glyphBitmap": {
+            "width": 7,
+            "height": 14,
+            "pixelArray": "38fcfcfcfcfccd24a4a4a4efffb200000011faff5c00000061fff70e000000b7ffad00000013fbff5600000063fff40b000000baffa700000015fcff5000000066fff108000000bcffa100000016fdff4a0000005effffa29c9c8268ffffffffffd4"
+          },
+          "source": {
+            "filePath": "Oswald-Medium.ttf",
+            "size": 12,
+            "encoding": 90
+          }
+        },
+        {
+          "encoding": 91,
+          "x": 0,
+          "y": -3,
+          "width": 6,
+          "height": 17,
+          "dx": 6,
+          "glyphBitmap": {
+            "width": 6,
+            "height": 17,
+            "pixelArray": "05fcfcfcfc1405ffffa7a40d05ffff08000005ffff08000006ffff08000006ffff08000006ffff08000006ffff08000007ffff08000007ffff08000007ffff08000007ffff08000008ffff08000008ffff08000008ffff08000008ffffa3a00a08ffffffff10"
+          },
+          "source": {
+            "filePath": "Oswald-Medium.ttf",
+            "size": 12,
+            "encoding": 91
+          }
+        },
+        {
+          "encoding": 92,
+          "x": 0,
+          "y": 0,
+          "width": 7,
+          "height": 14,
+          "dx": 7,
+          "glyphBitmap": {
+            "width": 7,
+            "height": 14,
+            "pixelArray": "40fc5a0000000007f5a20000000000b4e802000000006dff310000000026ff780000000001dec0000000000097fb0d0000000050ff4f000000000efb960000000000c1de01000000007aff250000000033ff6d0000000002eab40000000000a4f508"
+          },
+          "source": {
+            "filePath": "Oswald-Medium.ttf",
+            "size": 12,
+            "encoding": 92
+          }
+        },
+        {
+          "encoding": 93,
+          "x": 0,
+          "y": -3,
+          "width": 5,
+          "height": 17,
+          "dx": 5,
+          "glyphBitmap": {
+            "width": 5,
+            "height": 17,
+            "pixelArray": "9efcfcfc7767a4dbff78000098ff78000098ff78000098ff78000098ff78000098ff78000098ff78000098ff78000098ff78000098ff78000098ff78000098ff78000098ff78000098ff7864a0d9ff78a0ffffff78"
+          },
+          "source": {
+            "filePath": "Oswald-Medium.ttf",
+            "size": 12,
+            "encoding": 93
+          }
+        },
+        {
+          "encoding": 94,
+          "x": 0,
+          "y": 8,
+          "width": 8,
+          "height": 6,
+          "dx": 8,
+          "glyphBitmap": {
+            "width": 8,
+            "height": 6,
+            "pixelArray": "00004dfcfc3200000000bbffffa000000029ffb9d2f916000095ff5d76ff7d000ff4f50c1dfee7062c846100006e8421"
+          },
+          "source": {
+            "filePath": "Oswald-Medium.ttf",
+            "size": 12,
+            "encoding": 94
+          }
+        },
+        {
+          "encoding": 95,
+          "x": 0,
+          "y": -3,
+          "width": 7,
+          "height": 2,
+          "dx": 6,
+          "glyphBitmap": {
+            "width": 7,
+            "height": 2,
+            "pixelArray": "a0a0a0a0a0a00affffffffffff10"
+          },
+          "source": {
+            "filePath": "Oswald-Medium.ttf",
+            "size": 12,
+            "encoding": 95
+          }
+        },
+        {
+          "encoding": 96,
+          "x": 0,
+          "y": 10,
+          "width": 5,
+          "height": 4,
+          "dx": 5,
+          "glyphBitmap": {
+            "width": 5,
+            "height": 4,
+            "pixelArray": "04c8fc6100002af8b700000073fb120000010401"
+          },
+          "source": {
+            "filePath": "Oswald-Medium.ttf",
+            "size": 12,
+            "encoding": 96
+          }
+        },
+        {
+          "encoding": 97,
+          "x": 0,
+          "y": 0,
+          "width": 8,
+          "height": 10,
+          "dx": 8,
+          "glyphBitmap": {
+            "width": 8,
+            "height": 10,
+            "pixelArray": "0024aff1f1a7100001cfffc9e5ff8d0021ffff1770ffd300145c5c0370ffe000000040bfffffe000007cffd287ffe00022fffd1e64ffe0004fffef026bffe1002affffb7e4ffeb00007df3db51fffe05"
+          },
+          "source": {
+            "filePath": "Oswald-Medium.ttf",
+            "size": 12,
+            "encoding": 97
+          }
+        },
+        {
+          "encoding": 98,
+          "x": 0,
+          "y": 0,
+          "width": 8,
+          "height": 14,
+          "dx": 8,
+          "glyphBitmap": {
+            "width": 8,
+            "height": 14,
+            "pixelArray": "18fcfc3c0000000018ffff3c0000000018ffff3c0000000018ffff3c0000000018ffff88d4f0700018ffffdbc4fffd1a18ffff3d09fbff5618ffff3c00edff6418ffff3c00ecff6418ffff3c00ecff6418ffff3c00edff6318ffff3c07fbff5018ffffcfbbfffa1518ffff95e0f16800"
+          },
+          "source": {
+            "filePath": "Oswald-Medium.ttf",
+            "size": 12,
+            "encoding": 98
+          }
+        },
+        {
+          "encoding": 99,
+          "x": 0,
+          "y": 0,
+          "width": 7,
+          "height": 10,
+          "dx": 7,
+          "glyphBitmap": {
+            "width": 7,
+            "height": 10,
+            "pixelArray": "0030c3f6eda41003e0ffc8e3ff8c2fffff1964ffcb4affff0944c4a34cffff080000004cffff080000004affff0954f4cb30ffff1865ffc904e2ffc8e2ff890034c8faf0a30e"
+          },
+          "source": {
+            "filePath": "Oswald-Medium.ttf",
+            "size": 12,
+            "encoding": 99
+          }
+        },
+        {
+          "encoding": 100,
+          "x": 0,
+          "y": 0,
+          "width": 8,
+          "height": 14,
+          "dx": 8,
+          "glyphBitmap": {
+            "width": 8,
+            "height": 14,
+            "pixelArray": "000000002cfcfc28000000002cffff28000000002cffff28000000002cffff28004ce3e99affff2804e9ffd2ceffff282fffff272cffff2846ffff112cffff2848ffff102cffff2848ffff102cffff2847ffff112cffff2834ffff222cffff2806f4ffccc5ffff28005be6ed9cffff28"
+          },
+          "source": {
+            "filePath": "Oswald-Medium.ttf",
+            "size": 12,
+            "encoding": 100
+          }
+        },
+        {
+          "encoding": 101,
+          "x": 0,
+          "y": 0,
+          "width": 7,
+          "height": 10,
+          "dx": 8,
+          "glyphBitmap": {
+            "width": 7,
+            "height": 10,
+            "pixelArray": "002dc1f6ee9f0b03ddffc3deff832effff0f58ffcb4affff9ebcffe14cffffffffffe44cffff080404044affff042b887930ffff1460ffd504e3ffcde6ff8d0035c7f9efa00d"
+          },
+          "source": {
+            "filePath": "Oswald-Medium.ttf",
+            "size": 12,
+            "encoding": 101
+          }
+        },
+        {
+          "encoding": 102,
+          "x": 0,
+          "y": 0,
+          "width": 6,
+          "height": 14,
+          "dx": 5,
+          "glyphBitmap": {
+            "width": 6,
+            "height": 14,
+            "pixelArray": "000caef5f00f006dfffcb30d0098ffbe000000a0ffb00000aefffffffc1071deffe4a40b00a0ffb0000000a0ffb0000000a0ffb0000000a0ffb0000000a0ffb0000000a0ffb0000000a0ffb0000000a0ffb00000"
+          },
+          "source": {
+            "filePath": "Oswald-Medium.ttf",
+            "size": 12,
+            "encoding": 102
+          }
+        },
+        {
+          "encoding": 103,
+          "x": 0,
+          "y": -3,
+          "width": 9,
+          "height": 14,
+          "dx": 8,
+          "glyphBitmap": {
+            "width": 9,
+            "height": 14,
+            "pixelArray": "000000000000000f00002abbf6e56486d40101d9ffc2e1ffdb680428fff70457ffa7000042ffe60044ffcf00002ffff40454ffc2000003d3ffbaddff7d0000007df2f8f39d0800002cfe9b1b03000000002cfafffffdda73010002a8e99eb9f2ff430066ff84000068ff6f0096ffeeada6e7ff440020b0ecfffdda7c0100"
+          },
+          "source": {
+            "filePath": "Oswald-Medium.ttf",
+            "size": 12,
+            "encoding": 103
+          }
+        },
+        {
+          "encoding": 104,
+          "x": 0,
+          "y": 0,
+          "width": 8,
+          "height": 14,
+          "dx": 8,
+          "glyphBitmap": {
+            "width": 8,
+            "height": 14,
+            "pixelArray": "10fcfc3f0000000010ffff400000000010ffff400000000010ffff400000000010ffff6fb8f6b30310ffffe9beffff3b10ffff4309ffff4c10ffff4004ffff4c10ffff4004ffff4c10ffff4004ffff4c10ffff4004ffff4c10ffff4004ffff4c10ffff4004ffff4c10ffff4004ffff4c"
+          },
+          "source": {
+            "filePath": "Oswald-Medium.ttf",
+            "size": 12,
+            "encoding": 104
+          }
+        },
+        {
+          "encoding": 105,
+          "x": 0,
+          "y": 0,
+          "width": 4,
+          "height": 14,
+          "dx": 4,
+          "glyphBitmap": {
+            "width": 4,
+            "height": 14,
+            "pixelArray": "08fcfc4b06a4a431000000000000000008fcfc4708ffff4808ffff4808ffff4808ffff4808ffff4808ffff4808ffff4808ffff4808ffff48"
+          },
+          "source": {
+            "filePath": "Oswald-Medium.ttf",
+            "size": 12,
+            "encoding": 105
+          }
+        },
+        {
+          "encoding": 106,
+          "x": -1,
+          "y": -3,
+          "width": 5,
+          "height": 17,
+          "dx": 4,
+          "glyphBitmap": {
+            "width": 5,
+            "height": 17,
+            "pixelArray": "0000e1fc73000093a44b000000000000000000000000ddfc6f0000e0ff700000e0ff700000e0ff700000e0ff700000e0ff700000e0ff700000e0ff700000e0ff700000e0ff700004eeff6d31d9ffff3734f7ec7d01"
+          },
+          "source": {
+            "filePath": "Oswald-Medium.ttf",
+            "size": 12,
+            "encoding": 106
+          }
+        },
+        {
+          "encoding": 107,
+          "x": 0,
+          "y": 0,
+          "width": 9,
+          "height": 14,
+          "dx": 8,
+          "glyphBitmap": {
+            "width": 9,
+            "height": 14,
+            "pixelArray": "18fcfc38000000000018ffff38000000000018ffff38000000000018ffff38000000000018ffff38009ffcd90818ffff383fffff4c0018ffff3ed6ffb3000018ffffb0fff822000018ffffffffef09000018ffffb3e3ff5d000018ffff3c89ffc3000018ffff382effff2a0018ffff3800d2ff8f0018ffff380076ffee08"
+          },
+          "source": {
+            "filePath": "Oswald-Medium.ttf",
+            "size": 12,
+            "encoding": 107
+          }
+        },
+        {
+          "encoding": 108,
+          "x": 1,
+          "y": 0,
+          "width": 3,
+          "height": 14,
+          "dx": 4,
+          "glyphBitmap": {
+            "width": 3,
+            "height": 14,
+            "pixelArray": "f5fc5bf8ff5cf8ff5cf8ff5cf8ff5cf8ff5cf8ff5cf8ff5cf8ff5cf8ff5cf8ff5cf8ff5cf8ff5cf8ff5c"
+          },
+          "source": {
+            "filePath": "Oswald-Medium.ttf",
+            "size": 12,
+            "encoding": 108
+          }
+        },
+        {
+          "encoding": 109,
+          "x": 0,
+          "y": 0,
+          "width": 12,
+          "height": 10,
+          "dx": 12,
+          "glyphBitmap": {
+            "width": 12,
+            "height": 10,
+            "pixelArray": "1cfcfc67d3f69039c7f7a6031cffffe9bbffffe9b4ffff3c1cffff2303fcff4600deff5b1cffff1800f8ff3c00d8ff5c1cffff1800f8ff3c00d8ff5c1cffff1800f8ff3c00d8ff5c1cffff1800f8ff3c00d8ff5c1cffff1800f8ff3c00d8ff5c1cffff1800f8ff3c00d8ff5c1cffff1800f8ff3c00d8ff5c"
+          },
+          "source": {
+            "filePath": "Oswald-Medium.ttf",
+            "size": 12,
+            "encoding": 109
+          }
+        },
+        {
+          "encoding": 110,
+          "x": 0,
+          "y": 0,
+          "width": 8,
+          "height": 10,
+          "dx": 8,
+          "glyphBitmap": {
+            "width": 8,
+            "height": 10,
+            "pixelArray": "1cfcfc6fb7f6a1011cffffe3c4ffff221cffff3a21ffff381cffff381cffff381cffff381cffff381cffff381cffff381cffff381cffff381cffff381cffff381cffff381cffff381cffff381cffff38"
+          },
+          "source": {
+            "filePath": "Oswald-Medium.ttf",
+            "size": 12,
+            "encoding": 110
+          }
+        },
+        {
+          "encoding": 111,
+          "x": 0,
+          "y": 0,
+          "width": 7,
+          "height": 10,
+          "dx": 8,
+          "glyphBitmap": {
+            "width": 7,
+            "height": 10,
+            "pixelArray": "002cbff6ed9d0d04dfffc8e3ff9633ffff135dffe74bffff014dffff4cffff004cffff4cffff004cffff4bffff004dffff34ffff0f5dffe804e3ffc1deff9b0032c1f9efa110"
+          },
+          "source": {
+            "filePath": "Oswald-Medium.ttf",
+            "size": 12,
+            "encoding": 111
+          }
+        },
+        {
+          "encoding": 112,
+          "x": 0,
+          "y": -3,
+          "width": 8,
+          "height": 13,
+          "dx": 8,
+          "glyphBitmap": {
+            "width": 8,
+            "height": 13,
+            "pixelArray": "1cfcfc8dd8ef6d001cffffdac7fffc171cffff390bfdff4f1cffff3800f1ff601cffff3800f0ff601cffff3800f0ff601cffff3800f1ff5f1cffff3808fdff4c1cffffcdbefff9121cffff91e0ef65001cffff38000000001cffff38000000001cffff3800000000"
+          },
+          "source": {
+            "filePath": "Oswald-Medium.ttf",
+            "size": 12,
+            "encoding": 112
+          }
+        },
+        {
+          "encoding": 113,
+          "x": 0,
+          "y": -3,
+          "width": 8,
+          "height": 13,
+          "dx": 8,
+          "glyphBitmap": {
+            "width": 8,
+            "height": 13,
+            "pixelArray": "0048e1e995fcfc3004e8ffd3cdffff3030ffff2724ffff3043ffff1124ffff3044ffff1024ffff3044ffff1024ffff3043ffff1124ffff3030ffff2224ffff3005f1ffccc4ffff300059e6ed97ffff300000000024ffff300000000024ffff300000000024ffff30"
+          },
+          "source": {
+            "filePath": "Oswald-Medium.ttf",
+            "size": 12,
+            "encoding": 113
+          }
+        },
+        {
+          "encoding": 114,
+          "x": 0,
+          "y": 0,
+          "width": 6,
+          "height": 11,
+          "dx": 6,
+          "glyphBitmap": {
+            "width": 6,
+            "height": 11,
+            "pixelArray": "00000000000214fcfc6bcea614fffffbb87914ffff77000014ffff40000014ffff40000014ffff40000014ffff40000014ffff40000014ffff40000014ffff400000"
+          },
+          "source": {
+            "filePath": "Oswald-Medium.ttf",
+            "size": 12,
+            "encoding": 114
+          }
+        },
+        {
+          "encoding": 115,
+          "x": 0,
+          "y": 0,
+          "width": 7,
+          "height": 10,
+          "dx": 7,
+          "glyphBitmap": {
+            "width": 7,
+            "height": 10,
+            "pixelArray": "0054d4f7bb240021fdfbb4fccd015fffc6008ed71531ffff730a01000093ffff8b0200000283ffff9200000c0863ffff3167f56300c7ff5b31fef4abfcfd20005bd7fbd15700"
+          },
+          "source": {
+            "filePath": "Oswald-Medium.ttf",
+            "size": 12,
+            "encoding": 115
+          }
+        },
+        {
+          "encoding": 116,
+          "x": 0,
+          "y": 0,
+          "width": 6,
+          "height": 13,
+          "dx": 6,
+          "glyphBitmap": {
+            "width": 6,
+            "height": 13,
+            "pixelArray": "00b6fc9e000000b8ffa0000000b8ffa00000aefffffffc1c71e7ffdea41200b8ffa0000000b8ffa0000000b8ffa0000000b8ffa0000000b8ffa0000000b4ffad00000088ffffdb320017c6fcf533"
+          },
+          "source": {
+            "filePath": "Oswald-Medium.ttf",
+            "size": 12,
+            "encoding": 116
+          }
+        },
+        {
+          "encoding": 117,
+          "x": 0,
+          "y": 0,
+          "width": 8,
+          "height": 10,
+          "dx": 8,
+          "glyphBitmap": {
+            "width": 8,
+            "height": 10,
+            "pixelArray": "2cfcfc2434fcfc1c2cffff2434ffff1c2cffff2434ffff1c2cffff2434ffff1c2cffff2434ffff1c2cffff2434ffff1c2cffff2434ffff1c2cffff2a37ffff1c19ffffd0e7ffff1c009ffac067ffff1c"
+          },
+          "source": {
+            "filePath": "Oswald-Medium.ttf",
+            "size": 12,
+            "encoding": 117
+          }
+        },
+        {
+          "encoding": 118,
+          "x": 0,
+          "y": 0,
+          "width": 7,
+          "height": 10,
+          "dx": 7,
+          "glyphBitmap": {
+            "width": 7,
+            "height": 10,
+            "pixelArray": "aefc8b00a3fc9280ffaf00c7ff634effd200e8ff331dfff40cfffb0701ecff43ffd10000bbff88ffa0000089ffccff6f000058fffeff3e000027ffffff0e000002f3ffdc0000"
+          },
+          "source": {
+            "filePath": "Oswald-Medium.ttf",
+            "size": 12,
+            "encoding": 118
+          }
+        },
+        {
+          "encoding": 119,
+          "x": 0,
+          "y": 0,
+          "width": 10,
+          "height": 10,
+          "dx": 10,
+          "glyphBitmap": {
+            "width": 10,
+            "height": 10,
+            "pixelArray": "7ffc6700d6f9063afc965bff8907fcff295eff7134ffab2cffff5082ff490effcc55fffe76a6ff2100e7ed7ef1cd9dcbf80300c0ffb7c3a0c4f0d2000099fff79474f5ffaa000072ffff6547ffff8300004bffff361bffff5b000024fffe0a01efff3400"
+          },
+          "source": {
+            "filePath": "Oswald-Medium.ttf",
+            "size": 12,
+            "encoding": 119
+          }
+        },
+        {
+          "encoding": 120,
+          "x": 0,
+          "y": 0,
+          "width": 7,
+          "height": 10,
+          "dx": 7,
+          "glyphBitmap": {
+            "width": 7,
+            "height": 10,
+            "pixelArray": "92fcb10064fc9926feff26c8ff2f00b1ffbdffc200003fffffff55000001d8ffe405000015f9ffe808000073ffffff620001d9ff98ffd4013fffc210f3ff48a5ff63008effbb"
+          },
+          "source": {
+            "filePath": "Oswald-Medium.ttf",
+            "size": 12,
+            "encoding": 120
+          }
+        },
+        {
+          "encoding": 121,
+          "x": 0,
+          "y": -3,
+          "width": 7,
+          "height": 13,
+          "dx": 7,
+          "glyphBitmap": {
+            "width": 7,
+            "height": 13,
+            "pixelArray": "c3fc750067fcd289ffa50090ff9e4bffd300b8ff6610fefb07e0ff2f00ceff3afff504008fff8fffc0000051ffe4ff89000014ffffff51000000d5ffff1a00000098ffe30000000075ffab00000bb6f0ff52000010fdd574010000"
+          },
+          "source": {
+            "filePath": "Oswald-Medium.ttf",
+            "size": 12,
+            "encoding": 121
+          }
+        },
+        {
+          "encoding": 122,
+          "x": 0,
+          "y": 0,
+          "width": 6,
+          "height": 10,
+          "dx": 6,
+          "glyphBitmap": {
+            "width": 6,
+            "height": 10,
+            "pixelArray": "2cfcfcfcfcd51da4a4e3ffbe000009eeff5b00005effee080000c6ff9000002effff2b000095ffc400000cf2ff5e00005dffffa69c7f70ffffffffd0"
+          },
+          "source": {
+            "filePath": "Oswald-Medium.ttf",
+            "size": 12,
+            "encoding": 122
+          }
+        },
+        {
+          "encoding": 123,
+          "x": 0,
+          "y": -3,
+          "width": 6,
+          "height": 17,
+          "dx": 6,
+          "glyphBitmap": {
+            "width": 6,
+            "height": 17,
+            "pixelArray": "00007de8fc4b0017ffffcc310035ffff1f000038ffff14000038ffff1400003affff1400004afffa05002ad4ffa8000044fffc5200000270ffe10000003effff0b000039ffff14000038ffff14000038ffff14000032ffff21000013feffca30000076ebff4c"
+          },
+          "source": {
+            "filePath": "Oswald-Medium.ttf",
+            "size": 12,
+            "encoding": 123
+          }
+        },
+        {
+          "encoding": 124,
+          "x": 1,
+          "y": -3,
+          "width": 3,
+          "height": 17,
+          "dx": 4,
+          "glyphBitmap": {
+            "width": 3,
+            "height": 17,
+            "pixelArray": "dafc28ddff28ddff28ddff28deff28deff28deff28deff28dfff28dfff28dfff28dfff28e0ff28e0ff28e0ff28e0ff28e0ff28"
+          },
+          "source": {
+            "filePath": "Oswald-Medium.ttf",
+            "size": 12,
+            "encoding": 124
+          }
+        },
+        {
+          "encoding": 125,
+          "x": 0,
+          "y": -3,
+          "width": 6,
+          "height": 17,
+          "dx": 6,
+          "glyphBitmap": {
+            "width": 6,
+            "height": 17,
+            "pixelArray": "43fce98400002cc9ffff1e000018ffff3e00000dffff4400000cffff4400000cffff44000002f6ff50000000a3ffd72f00004dfaff4c0000dcff76020006ffff4600000cffff4400000cffff4400000dffff4400001affff3b002bc7ffff1a0044ffed7d0000"
+          },
+          "source": {
+            "filePath": "Oswald-Medium.ttf",
+            "size": 12,
+            "encoding": 125
+          }
+        },
+        {
+          "encoding": 126,
+          "x": 0,
+          "y": 5,
+          "width": 8,
+          "height": 4,
+          "dx": 8,
+          "glyphBitmap": {
+            "width": 8,
+            "height": 4,
+            "pixelArray": "00218c630700220026efffffe4b4fd2e067a1753cbf57a010000000000010000"
+          },
+          "source": {
+            "filePath": "Oswald-Medium.ttf",
+            "size": 12,
+            "encoding": 126
+          }
+        },
+        {
+          "encoding": 127,
+          "x": 0,
+          "y": 0,
+          "width": 6,
+          "height": 12,
+          "dx": 6,
+          "glyphBitmap": {
+            "width": 6,
+            "height": 12,
+            "pixelArray": "25545454540770553c3c9b14702000007c14702000007c14702000007c14702000007c14702000007c14702000007c14702000007c14702000007c14702000007c14709b8c8cc514"
+          },
+          "source": {
+            "filePath": "Oswald-Medium.ttf",
+            "size": 12,
+            "encoding": 127
+          }
+        }
+      ],
+      "alwaysBuild": false
+    }
+  ],
+  "bitmaps": [],
+  "colors": [
+    {
+      "name": "background"
+    },
+    {
+      "name": "text"
+    },
+    {
+      "name": "text_inactive"
+    },
+    {
+      "name": "dark_text"
+    },
+    {
+      "name": "border"
+    },
+    {
+      "id": 1,
+      "name": "backdrop"
+    },
+    {
+      "name": "active_background"
+    },
+    {
+      "name": "button_text"
+    },
+    {
+      "name": "button_background"
+    },
+    {
+      "name": "button_active_background"
+    },
+    {
+      "name": "button_border"
+    },
+    {
+      "name": "button_disabled_text"
+    },
+    {
+      "name": "button_disabled_background"
+    },
+    {
+      "name": "button_disabled_border"
+    },
+    {
+      "name": "error"
+    },
+    {
+      "name": "note"
+    },
+    {
+      "name": "switch_widget_color"
+    },
+    {
+      "name": "switch_widget_background_on"
+    },
+    {
+      "name": "switch_widget_background_off"
+    },
+    {
+      "name": "switch_widget_border"
+    },
+    {
+      "name": "slider_widget_color"
+    },
+    {
+      "name": "slider_widget_background"
+    },
+    {
+      "name": "drop_down_list_color"
+    },
+    {
+      "name": "drop_down_list_color_disabled"
+    },
+    {
+      "name": "drop_down_list_background"
+    },
+    {
+      "name": "drop_down_list_border"
+    },
+    {
+      "name": "drop_down_list_active_background"
+    },
+    {
+      "name": "text_input_color"
+    },
+    {
+      "name": "text_input_color_disabled"
+    },
+    {
+      "name": "text_input_background"
+    },
+    {
+      "name": "text_input_active_background"
+    },
+    {
+      "name": "text_input_border"
+    }
+  ],
+  "themes": [
+    {
+      "name": "default",
+      "colors": [
+        "#474747",
+        "#ffffff",
+        "#c0c0c0",
+        "#202020",
+        "#3b3b3b",
+        "#808080",
+        "#c490ee",
+        "#ffffff",
+        "#202020",
+        "#5c5c5c",
+        "#808080",
+        "#404040",
+        "#202020",
+        "#808080",
+        "#ffa3a3",
+        "#fce440",
+        "#ffffff",
+        "#0080ff",
+        "#808080",
+        "#c0c0c0",
+        "#0080ff",
+        "#ffffff",
+        "#404040",
+        "#808080",
+        "#ffffff",
+        "#404040",
+        "#c0c0c0",
+        "#404040",
+        "#808080",
+        "#ffffff",
+        "#c0c0c0",
+        "#404040"
+      ]
+    }
+  ]
+}
\ No newline at end of file
diff --git a/Src/gui/document.cpp b/Src/gui/document.cpp
new file mode 100644
index 0000000..4d7d273
--- /dev/null
+++ b/Src/gui/document.cpp
@@ -0,0 +1,664 @@
+#include "document.h"
+
+namespace eez {
+namespace gui {
+
+DataOperationsFunction g_dataOperationsFunctions[] = {
+    data_none,
+    data_alert_message,
+    data_touch_calibration_point,
+    data_keypad_text,
+    data_keypad_edit_unit,
+    data_keypad_sign_enabled,
+    data_keypad_unit_enabled,
+    data_keypad_dot_enabled,
+    data_keypad_option1_enabled,
+    data_keypad_option1_text,
+    data_keypad_option2_enabled,
+    data_keypad_option2_text,
+    data_keypad_option3_enabled,
+    data_keypad_option3_text,
+    data_keypad_mode,
+    data_keypad_ok_enabled
+};
+
+ActionExecFunc g_actionExecFunctions[] = {
+    0,
+    action_yes,
+    action_no,
+    action_cancel,
+    action_edit,
+    action_drag_overlay,
+    action_scroll,
+    action_keypad_key,
+    action_keypad_back,
+    action_keypad_unit,
+    action_keypad_option1,
+    action_keypad_option2,
+    action_keypad_option3,
+    action_keypad_sign,
+    action_keypad_ok,
+    action_keypad_cancel,
+    action_toggle_keypad_mode,
+    action_keypad_space
+};
+
+// ASSETS DEFINITION
+const uint8_t assets[9804] = {
+    0x7E, 0x65, 0x65, 0x7A, 0x03, 0x00, 0x01, 0x00, 0x10, 0x4B, 0x00, 0x00, 0xF6, 0x0B, 0x44, 0x00,
+    0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x48, 0x00, 0x00, 0x00, 0x13, 0x00, 0x00, 0x00, 0x58, 0x00,
+    0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0xA4, 0x00, 0x01, 0x00, 0x2E, 0xB0, 0x00, 0x01, 0x00, 0x17,
+    0xC0, 0x0C, 0x00, 0x50, 0x20, 0x03, 0xE0, 0x01, 0xD8, 0x48, 0x00, 0xF2, 0x62, 0x01, 0x00, 0x00,
+    0x30, 0x01, 0x00, 0x00, 0x5C, 0x01, 0x00, 0x00, 0x88, 0x01, 0x00, 0x00, 0xAC, 0x01, 0x00, 0x00,
+    0xD0, 0x01, 0x00, 0x00, 0xF4, 0x01, 0x00, 0x00, 0x18, 0x02, 0x00, 0x00, 0x3C, 0x02, 0x00, 0x00,
+    0x60, 0x02, 0x00, 0x00, 0x84, 0x02, 0x00, 0x00, 0xA8, 0x02, 0x00, 0x00, 0xCC, 0x02, 0x00, 0x00,
+    0xF0, 0x02, 0x00, 0x00, 0x14, 0x03, 0x00, 0x00, 0x38, 0x03, 0x00, 0x00, 0x5C, 0x03, 0x00, 0x00,
+    0x80, 0x03, 0x00, 0x00, 0xA4, 0x03, 0x00, 0x00, 0xC8, 0x03, 0x00, 0x00, 0xEC, 0x03, 0x00, 0x00,
+    0x10, 0x04, 0x00, 0x00, 0x34, 0x04, 0x00, 0x00, 0x50, 0x04, 0x00, 0x00, 0x6C, 0x04, 0x00, 0x00,
+    0x01, 0x00, 0x00, 0x00, 0x88, 0x04, 0x00, 0x00, 0x05, 0x00, 0x00, 0x00, 0x8C, 0x04, 0xBC, 0x00,
+    0x50, 0x98, 0x04, 0x00, 0x00, 0x09, 0x10, 0x00, 0x16, 0x49, 0x94, 0x00, 0x1B, 0x01, 0xA0, 0x00,
+    0x2A, 0x0F, 0x00, 0x1C, 0x00, 0x5F, 0xA8, 0x04, 0x00, 0x00, 0x08, 0x2C, 0x00, 0x00, 0x3D, 0xE0,
+    0x01, 0x10, 0x2C, 0x00, 0x1F, 0xAC, 0x2C, 0x00, 0x14, 0x00, 0x38, 0x01, 0x1F, 0xB0, 0x2C, 0x00,
+    0x04, 0x00, 0x84, 0x00, 0x1F, 0x01, 0x48, 0x01, 0x00, 0x04, 0x2C, 0x00, 0x70, 0x12, 0x00, 0x00,
+    0x00, 0x02, 0x00, 0x02, 0x2A, 0x00, 0x21, 0x00, 0x20, 0x12, 0x00, 0x15, 0x05, 0x24, 0x00, 0x2F,
+    0x02, 0xFF, 0x24, 0x00, 0x11, 0x40, 0x14, 0x14, 0x14, 0x14, 0x24, 0x00, 0x7F, 0x0E, 0x00, 0x04,
+    0x00, 0x04, 0x00, 0x0E, 0x24, 0x00, 0x0A, 0x71, 0x08, 0x00, 0x07, 0x00, 0x09, 0x00, 0x07, 0x24,
+    0x00, 0x73, 0x02, 0x02, 0x02, 0x02, 0x0A, 0x00, 0x08, 0x01, 0x00, 0x60, 0x02, 0xFF, 0x08, 0x10,
+    0x08, 0x10, 0x24, 0x00, 0x7F, 0x18, 0x00, 0x16, 0x00, 0x16, 0x00, 0x18, 0x48, 0x00, 0x02, 0x4F,
+    0x0C, 0x0C, 0x0C, 0x0C, 0x24, 0x00, 0x31, 0x7F, 0x06, 0x06, 0x06, 0x06, 0x00, 0x00, 0x10, 0x24,
+    0x00, 0x10, 0x00, 0x48, 0x00, 0x1F, 0x17, 0x48, 0x00, 0x10, 0x0F, 0x24, 0x00, 0x0D, 0x1F, 0x02,
+    0x68, 0x01, 0x0C, 0x1E, 0x0A, 0x68, 0x01, 0x0F, 0x44, 0x01, 0x20, 0x01, 0x83, 0x01, 0x65, 0x00,
+    0x12, 0x00, 0x21, 0x00, 0x22, 0x48, 0x00, 0x10, 0x01, 0x01, 0x00, 0x0F, 0xD4, 0x01, 0x1C, 0x04,
+    0x24, 0x00, 0x7F, 0x21, 0x00, 0x23, 0x00, 0x23, 0x00, 0x21, 0x24, 0x00, 0x00, 0x15, 0x03, 0x24,
+    0x00, 0x3F, 0x0F, 0x00, 0x04, 0x48, 0x00, 0x12, 0x3F, 0x21, 0x00, 0x24, 0x48, 0x00, 0x06, 0x0F,
+    0xD8, 0x00, 0x0E, 0x01, 0x01, 0x00, 0x11, 0x14, 0x66, 0x00, 0x33, 0x00, 0x00, 0x27, 0xE4, 0x02,
+    0x13, 0xBC, 0xF4, 0x02, 0x10, 0xC0, 0xF4, 0x00, 0x12, 0x04, 0x1C, 0x00, 0x13, 0x7F, 0x1C, 0x00,
+    0xEA, 0xE0, 0x04, 0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0xE4, 0x04, 0x00, 0x00, 0x23, 0x00, 0x1C,
+    0x00, 0x22, 0x64, 0x06, 0x1C, 0x00, 0x62, 0x68, 0x06, 0x00, 0x00, 0xE8, 0x07, 0x5C, 0x00, 0xF2,
+    0xFF, 0xFF, 0xFF, 0x4E, 0xE3, 0x07, 0xFF, 0xFF, 0xE0, 0x07, 0x00, 0x00, 0xF4, 0x07, 0x00, 0x00,
+    0x1C, 0x08, 0x00, 0x00, 0x44, 0x08, 0x00, 0x00, 0x6C, 0x08, 0x00, 0x00, 0x94, 0x08, 0x00, 0x00,
+    0xB8, 0x08, 0x00, 0x00, 0xDC, 0x08, 0x00, 0x00, 0xFC, 0x08, 0x00, 0x00, 0x20, 0x09, 0x00, 0x00,
+    0x44, 0x09, 0x00, 0x00, 0x50, 0x09, 0x00, 0x00, 0xE8, 0x0A, 0x00, 0x00, 0x80, 0x0C, 0x00, 0x00,
+    0x18, 0x0E, 0x00, 0x00, 0xB0, 0x0F, 0x00, 0x00, 0x48, 0x11, 0x00, 0x00, 0xE0, 0x12, 0x00, 0x00,
+    0x78, 0x14, 0x00, 0x00, 0x10, 0x16, 0x00, 0x00, 0x1C, 0x16, 0x00, 0x00, 0x24, 0x16, 0x00, 0x00,
+    0x64, 0x16, 0x00, 0x00, 0x8C, 0x16, 0x00, 0x00, 0x14, 0x17, 0x00, 0x00, 0xAC, 0x17, 0x00, 0x00,
+    0x94, 0x18, 0x00, 0x00, 0x28, 0x19, 0x00, 0x00, 0x44, 0x19, 0x00, 0x00, 0x90, 0x19, 0x00, 0x00,
+    0xF0, 0x19, 0x00, 0x00, 0x24, 0x1A, 0x00, 0x00, 0x64, 0x1A, 0x00, 0x00, 0x80, 0x1A, 0x00, 0x00,
+    0x9C, 0x1A, 0x00, 0x00, 0xB0, 0x1A, 0x00, 0x00, 0x1C, 0x1B, 0x00, 0x00, 0x94, 0x1B, 0x00, 0x00,
+    0xF0, 0x1B, 0x00, 0x00, 0x68, 0x1C, 0x00, 0x00, 0xE0, 0x1C, 0x00, 0x00, 0x68, 0x1D, 0x00, 0x00,
+    0xE0, 0x1D, 0x00, 0x00, 0x68, 0x1E, 0x00, 0x00, 0xD4, 0x1E, 0x00, 0x00, 0x4C, 0x1F, 0x00, 0x00,
+    0xC4, 0x1F, 0x00, 0x00, 0xE8, 0x1F, 0x00, 0x00, 0x14, 0x20, 0x00, 0x00, 0x60, 0x20, 0x00, 0x00,
+    0x94, 0x20, 0x00, 0x00, 0xEC, 0x20, 0x00, 0x00, 0x64, 0x21, 0x00, 0x00, 0x7C, 0x22, 0x00, 0x00,
+    0x04, 0x23, 0x00, 0x00, 0x7C, 0x23, 0x00, 0x00, 0x04, 0x24, 0x00, 0x00, 0x7C, 0x24, 0x00, 0x00,
+    0xD8, 0x24, 0x00, 0x00, 0x34, 0x25, 0x00, 0x00, 0xBC, 0x25, 0x00, 0x00, 0x34, 0x26, 0x00, 0x00,
+    0x68, 0x26, 0x00, 0x00, 0xB8, 0x26, 0x00, 0x00, 0x30, 0x27, 0x00, 0x00, 0x8C, 0x27, 0x00, 0x00,
+    0x20, 0x28, 0x00, 0x00, 0x98, 0x28, 0x00, 0x00, 0x20, 0x29, 0x00, 0x00, 0x98, 0x29, 0x00, 0x00,
+    0x3C, 0x2A, 0x00, 0x00, 0xB4, 0x2A, 0x00, 0x00, 0x2C, 0x2B, 0x00, 0x00, 0xA4, 0x2B, 0x00, 0x00,
+    0x2C, 0x2C, 0x00, 0x00, 0xB4, 0x2C, 0x00, 0x00, 0x64, 0x2D, 0x00, 0x00, 0xEC, 0x2D, 0x00, 0x00,
+    0x74, 0x2E, 0x00, 0x00, 0xE0, 0x2E, 0x00, 0x00, 0x50, 0x2F, 0x00, 0x00, 0xBC, 0x2F, 0x00, 0x00,
+    0x1C, 0x30, 0x00, 0x00, 0x54, 0x30, 0x00, 0x00, 0x6C, 0x30, 0x00, 0x00, 0x88, 0x30, 0x00, 0x00,
+    0xE0, 0x30, 0x00, 0x00, 0x58, 0x31, 0x00, 0x00, 0xA8, 0x31, 0x00, 0x00, 0x20, 0x32, 0x00, 0x00,
+    0x70, 0x32, 0x00, 0x00, 0xCC, 0x32, 0x00, 0x00, 0x54, 0x33, 0x00, 0x00, 0xCC, 0x33, 0x00, 0x00,
+    0x0C, 0x34, 0x00, 0x00, 0x6C, 0x34, 0x00, 0x00, 0xF4, 0x34, 0x00, 0x00, 0x28, 0x35, 0x00, 0x00,
+    0xA8, 0x35, 0x00, 0x00, 0x00, 0x36, 0x00, 0x00, 0x50, 0x36, 0x00, 0x00, 0xC0, 0x36, 0x00, 0x00,
+    0x30, 0x37, 0x00, 0x00, 0x7C, 0x37, 0x00, 0x00, 0xCC, 0x37, 0x00, 0x00, 0x24, 0x38, 0x00, 0x00,
+    0x7C, 0x38, 0x00, 0x00, 0xCC, 0x38, 0x00, 0x00, 0x38, 0x39, 0x00, 0x00, 0x88, 0x39, 0x00, 0x00,
+    0xEC, 0x39, 0x00, 0x00, 0x30, 0x3A, 0x00, 0x00, 0xA0, 0x3A, 0x00, 0x00, 0xDC, 0x3A, 0x00, 0x00,
+    0x4C, 0x3B, 0x00, 0x00, 0x74, 0x3B, 0x00, 0x00, 0xC4, 0x3B, 0x00, 0x00, 0xD0, 0x3B, 0x00, 0x00,
+    0xD8, 0x3B, 0x00, 0x00, 0xE0, 0x3B, 0x00, 0x00, 0xE8, 0x3B, 0x00, 0x00, 0xF0, 0x3B, 0x00, 0x00,
+    0xF8, 0x3B, 0x00, 0x00, 0x00, 0x3C, 0x00, 0x00, 0x08, 0x3C, 0x00, 0x00, 0x10, 0x3C, 0x00, 0x00,
+    0x18, 0x3C, 0x00, 0x00, 0x20, 0x3C, 0x00, 0x00, 0x28, 0x3C, 0x00, 0x00, 0xFC, 0x40, 0x00, 0x00,
+    0x04, 0x41, 0x00, 0x00, 0x0C, 0x41, 0x00, 0x00, 0x14, 0x41, 0x00, 0x00, 0x1C, 0x41, 0x00, 0x00,
+    0x24, 0x41, 0x00, 0x00, 0x2C, 0x41, 0x00, 0x00, 0x34, 0x41, 0x00, 0x00, 0x3C, 0x41, 0x00, 0x00,
+    0x44, 0x41, 0x00, 0x00, 0x4C, 0x41, 0x00, 0x00, 0x54, 0x41, 0x00, 0x00, 0x5C, 0x41, 0x00, 0x00,
+    0x64, 0x41, 0x00, 0x00, 0x6C, 0x41, 0x00, 0x00, 0x74, 0x41, 0x00, 0x00, 0x7C, 0x41, 0x00, 0x00,
+    0x84, 0x41, 0x00, 0x00, 0x8C, 0x41, 0x00, 0x00, 0x94, 0x41, 0x00, 0x00, 0x9C, 0x41, 0x00, 0x00,
+    0xA4, 0x41, 0x00, 0x00, 0xAC, 0x41, 0x00, 0x00, 0xB4, 0x41, 0x00, 0x00, 0xBC, 0x41, 0x00, 0x00,
+    0xC4, 0x41, 0x00, 0x00, 0xCC, 0x41, 0x00, 0x00, 0xD4, 0x41, 0x00, 0x00, 0xDC, 0x41, 0x00, 0x00,
+    0xE4, 0x41, 0x00, 0x00, 0xEC, 0x41, 0x00, 0x00, 0xF4, 0x41, 0x00, 0x00, 0xFC, 0x41, 0x00, 0x00,
+    0x04, 0x42, 0x00, 0x00, 0x0C, 0x42, 0x00, 0x00, 0x14, 0x42, 0x00, 0x00, 0x1C, 0x42, 0x00, 0x00,
+    0x24, 0x42, 0x00, 0x00, 0x2C, 0x42, 0x00, 0x00, 0x34, 0x42, 0x00, 0x00, 0x3C, 0x42, 0x00, 0x00,
+    0x44, 0x42, 0x00, 0x00, 0x4C, 0x42, 0x00, 0x00, 0x54, 0x42, 0x00, 0x00, 0x5C, 0x42, 0x00, 0x00,
+    0x64, 0x42, 0x00, 0x00, 0x6C, 0x42, 0x00, 0x00, 0x74, 0x42, 0x00, 0x00, 0x7C, 0x42, 0x00, 0x00,
+    0x84, 0x42, 0x00, 0x00, 0x8C, 0x42, 0x00, 0x00, 0x94, 0x42, 0x00, 0x00, 0x9C, 0x42, 0x00, 0x00,
+    0xA4, 0x42, 0x00, 0x00, 0xAC, 0x42, 0x00, 0x00, 0xB4, 0x42, 0x00, 0x00, 0xBC, 0x42, 0x00, 0x00,
+    0xC4, 0x42, 0x00, 0x00, 0xCC, 0x42, 0x00, 0x00, 0xD4, 0x42, 0x00, 0x00, 0xDC, 0x42, 0x00, 0x00,
+    0xE4, 0x42, 0x00, 0x00, 0xEC, 0x42, 0x00, 0x00, 0xF4, 0x42, 0x00, 0x00, 0xFC, 0x42, 0x00, 0x00,
+    0x04, 0x43, 0x00, 0x00, 0x0C, 0x43, 0x00, 0x00, 0x14, 0x43, 0x00, 0x00, 0x1C, 0x43, 0x00, 0x00,
+    0x24, 0x43, 0x00, 0x00, 0x2C, 0x43, 0x00, 0x00, 0x34, 0x43, 0x00, 0x00, 0x3C, 0x43, 0x00, 0x00,
+    0x44, 0x43, 0x00, 0x00, 0x4C, 0x43, 0x00, 0x00, 0x54, 0x43, 0x00, 0x00, 0x5C, 0x43, 0x00, 0x00,
+    0x64, 0x43, 0x00, 0x00, 0x6C, 0x43, 0x00, 0x00, 0x74, 0x43, 0x00, 0x00, 0x7C, 0x43, 0x00, 0x00,
+    0x84, 0x43, 0x00, 0x00, 0x8C, 0x43, 0x00, 0x00, 0x94, 0x43, 0x00, 0x00, 0x9C, 0x43, 0x7C, 0x03,
+    0x22, 0xA4, 0x43, 0x7C, 0x03, 0x2E, 0xE4, 0x43, 0x8C, 0x06, 0x00, 0x18, 0x00, 0x17, 0xE8, 0x18,
+    0x00, 0x00, 0x0C, 0x05, 0x1F, 0xEC, 0x28, 0x00, 0x00, 0x00, 0xAB, 0x03, 0x2A, 0x14, 0x44, 0xF8,
+    0x06, 0x2E, 0x30, 0x44, 0x28, 0x00, 0x00, 0x18, 0x00, 0x3F, 0x3C, 0x44, 0x00, 0x01, 0x00, 0x1E,
+    0x33, 0x06, 0x00, 0xFF, 0x6A, 0x04, 0x6F, 0xDA, 0x00, 0x20, 0x03, 0x2C, 0x00, 0x38, 0x07, 0x01,
+    0x15, 0x04, 0x24, 0x00, 0x02, 0x88, 0x07, 0x1B, 0x10, 0x78, 0x00, 0x20, 0x48, 0x44, 0xDE, 0x04,
+    0x04, 0x24, 0x00, 0x5D, 0x52, 0x00, 0xE0, 0x01, 0x28, 0x48, 0x00, 0x40, 0x06, 0x00, 0xFE, 0xFF,
+    0xF6, 0x00, 0x9F, 0x5A, 0x00, 0xB0, 0x00, 0x8C, 0x00, 0x28, 0x00, 0x13, 0x8C, 0x00, 0x02, 0x20,
+    0xFD, 0xFF, 0xA2, 0x05, 0x1F, 0xFA, 0x24, 0x00, 0x08, 0x17, 0x20, 0xCC, 0x07, 0x01, 0x1D, 0x06,
+    0x09, 0x05, 0x01, 0x00, 0x01, 0x00, 0x22, 0x06, 0x06, 0x7E, 0x06, 0x01, 0x11, 0x00, 0x45, 0x06,
+    0x06, 0x06, 0x0A, 0x01, 0x00, 0x03, 0x12, 0x00, 0x63, 0x0A, 0x10, 0x10, 0x10, 0x10, 0x17, 0x01,
+    0x00, 0x01, 0x13, 0x00, 0x83, 0x0A, 0x10, 0x17, 0x1B, 0x1E, 0x21, 0x21, 0x28, 0x01, 0x00, 0x02,
+    0x13, 0x00, 0x1C, 0x1B, 0x9E, 0x00, 0x4B, 0x0A, 0x10, 0x1B, 0x28, 0x70, 0x00, 0x00, 0x13, 0x00,
+    0x1C, 0x39, 0x27, 0x00, 0x4B, 0x17, 0x21, 0x36, 0x4E, 0x14, 0x00, 0x5A, 0x10, 0x1B, 0x2C, 0x44,
+    0x5F, 0x3B, 0x00, 0x6C, 0x06, 0x10, 0x1E, 0x32, 0x4E, 0x70, 0x4F, 0x00, 0x4C, 0x21, 0x39, 0x58,
+    0x7A, 0x76, 0x00, 0x4C, 0x21, 0x3D, 0x5F, 0x84, 0x63, 0x00, 0x4D, 0x28, 0x40, 0x5F, 0x8B, 0x14,
+    0x00, 0x2F, 0x44, 0x66, 0x14, 0x00, 0x15, 0x1F, 0x8E, 0x14, 0x00, 0x4A, 0x04, 0x98, 0x01, 0x1F,
+    0x06, 0x01, 0x00, 0x00, 0x1F, 0x0A, 0x01, 0x00, 0x00, 0x1F, 0x17, 0x01, 0x00, 0x00, 0x1F, 0x28,
+    0x01, 0x00, 0x00, 0x1F, 0x00, 0x01, 0x00, 0xFF, 0x2D, 0x0A, 0x98, 0x01, 0x01, 0x2D, 0x03, 0x06,
+    0x80, 0x04, 0x05, 0x01, 0x00, 0x00, 0x1B, 0x00, 0x02, 0x14, 0x00, 0x04, 0x8C, 0x01, 0x00, 0x30,
+    0x03, 0x13, 0x0A, 0x16, 0x00, 0x04, 0x8C, 0x01, 0x9C, 0x21, 0x21, 0x1E, 0x1B, 0x17, 0x10, 0x0A,
+    0x06, 0x03, 0x65, 0x00, 0x1F, 0x1B, 0x15, 0x00, 0x00, 0x10, 0x28, 0x15, 0x00, 0x0B, 0x14, 0x00,
+    0x10, 0x39, 0x15, 0x00, 0x0B, 0x29, 0x00, 0x4C, 0x4E, 0x36, 0x21, 0x17, 0x29, 0x00, 0x5B, 0x5F,
+    0x44, 0x2C, 0x1B, 0x10, 0x14, 0x00, 0x5B, 0x70, 0x4E, 0x32, 0x1E, 0x10, 0x66, 0x00, 0x4C, 0x7A,
+    0x58, 0x39, 0x21, 0x51, 0x00, 0x4C, 0x84, 0x5F, 0x3D, 0x21, 0x7A, 0x00, 0x4C, 0x8B, 0x5F, 0x40,
+    0x28, 0x65, 0x00, 0x3F, 0x8B, 0x66, 0x44, 0x14, 0x00, 0x12, 0x1F, 0x8E, 0x14, 0x00, 0x43, 0x05,
+    0x98, 0x01, 0x0E, 0x9C, 0x03, 0x0F, 0x14, 0x00, 0xFF, 0x6B, 0x0D, 0x60, 0x06, 0x0E, 0x04, 0x02,
+    0x0F, 0x14, 0x00, 0xFF, 0x63, 0x0F, 0x30, 0x03, 0x5F, 0x0F, 0x58, 0x07, 0x13, 0x0E, 0x94, 0x07,
+    0x01, 0xBC, 0x07, 0x1F, 0xF8, 0xE4, 0x07, 0x00, 0x2E, 0xC5, 0xFB, 0x0C, 0x08, 0x81, 0x8E, 0xB0,
+    0xC8, 0xDD, 0xEA, 0xF4, 0xF4, 0xFB, 0x01, 0x00, 0x03, 0x34, 0x08, 0x81, 0x7A, 0x99, 0xAD, 0xBE,
+    0xCC, 0xD2, 0xD6, 0xDD, 0x01, 0x00, 0x03, 0x5C, 0x08, 0x72, 0x66, 0x7A, 0x8E, 0x9F, 0xAA, 0xB0,
+    0xB4, 0x01, 0x00, 0x03, 0x84, 0x08, 0xD3, 0x4E, 0x5F, 0x70, 0x7A, 0x84, 0x88, 0x8B, 0x8B, 0x8B,
+    0x8E, 0x8E, 0x8E, 0x8E, 0xAC, 0x08, 0x72, 0x36, 0x44, 0x4E, 0x58, 0x5F, 0x5F, 0x66, 0x01, 0x00,
+    0x03, 0xD4, 0x08, 0x72, 0x21, 0x2C, 0x32, 0x39, 0x3D, 0x40, 0x44, 0x01, 0x00, 0x0F, 0xFC, 0x08,
+    0x03, 0x0C, 0x24, 0x09, 0x2D, 0x1B, 0x1B, 0x4C, 0x09, 0x3C, 0x0D, 0x0D, 0x0D, 0x74, 0x09, 0x00,
+    0x17, 0x00, 0x0E, 0x30, 0x03, 0x0F, 0x30, 0x07, 0xAB, 0x1F, 0xFB, 0x01, 0x00, 0x00, 0x1F, 0xDD,
+    0x01, 0x00, 0x00, 0x1F, 0xB4, 0x01, 0x00, 0x00, 0x1F, 0x8E, 0x01, 0x00, 0x00, 0x1F, 0x66, 0x01,
+    0x00, 0x00, 0x1F, 0x44, 0x01, 0x00, 0x00, 0x0F, 0xFC, 0x08, 0x01, 0x1F, 0x1B, 0x01, 0x00, 0x00,
+    0x1F, 0x0D, 0x01, 0x00, 0x00, 0x0F, 0x60, 0x09, 0x01, 0x0F, 0xC8, 0x04, 0x66, 0x0F, 0x58, 0x07,
+    0x15, 0x0F, 0x94, 0x07, 0x00, 0x1E, 0xF8, 0xBC, 0x07, 0x23, 0xFB, 0xC5, 0xE4, 0x07, 0x02, 0x8A,
+    0x01, 0x73, 0xF4, 0xF4, 0xEA, 0xDD, 0xC8, 0xB0, 0x8E, 0x0C, 0x08, 0x02, 0x8A, 0x01, 0x73, 0xD6,
+    0xD2, 0xCC, 0xBE, 0xAD, 0x99, 0x7A, 0x34, 0x08, 0x03, 0x8B, 0x01, 0x63, 0xB0, 0xAA, 0x9F, 0x8E,
+    0x7A, 0x66, 0x5C, 0x08, 0x00, 0x88, 0x01, 0x93, 0x8B, 0x8B, 0x8B, 0x88, 0x84, 0x7A, 0x70, 0x5F,
+    0x4E, 0x84, 0x08, 0x03, 0x8B, 0x01, 0x63, 0x5F, 0x5F, 0x58, 0x4E, 0x44, 0x36, 0xAC, 0x08, 0x03,
+    0x8B, 0x01, 0x63, 0x40, 0x3D, 0x39, 0x32, 0x2C, 0x21, 0xD4, 0x08, 0x0F, 0xFC, 0x08, 0x01, 0x1F,
+    0x1B, 0x24, 0x09, 0x00, 0x2E, 0x0D, 0x0D, 0x4C, 0x09, 0x03, 0x0D, 0x00, 0x09, 0x74, 0x09, 0x04,
+    0xCC, 0x0C, 0x13, 0x60, 0x18, 0x16, 0x01, 0x6C, 0x0D, 0x22, 0x04, 0x0E, 0x33, 0x09, 0xF0, 0x2C,
+    0xFC, 0xFC, 0x17, 0x18, 0xFF, 0xFF, 0x05, 0x08, 0xFF, 0xF2, 0x00, 0x00, 0xF8, 0xDF, 0x00, 0x00,
+    0xE7, 0xCD, 0x00, 0x00, 0xD7, 0xBA, 0x00, 0x00, 0xC7, 0xA8, 0x00, 0x00, 0xB6, 0x95, 0x00, 0x00,
+    0xA6, 0x82, 0x00, 0x00, 0x95, 0x70, 0x00, 0x00, 0x85, 0x5D, 0x00, 0x00, 0x02, 0x02, 0x00, 0x23,
+    0x9C, 0x9C, 0x05, 0x38, 0xFF, 0xFF, 0x08, 0x06, 0x05, 0x06, 0x01, 0x1C, 0x0D, 0xF0, 0x0D, 0xF5,
+    0xF1, 0x22, 0xFC, 0xCB, 0xF8, 0xCA, 0x20, 0xFF, 0xA1, 0xF8, 0x9E, 0x20, 0xFF, 0x75, 0xF8, 0x72,
+    0x20, 0xFF, 0x48, 0xF8, 0x46, 0x20, 0xFF, 0x1B, 0x04, 0x01, 0x01, 0x3C, 0x16, 0x33, 0x09, 0x09,
+    0x0E, 0x72, 0x00, 0xF2, 0x39, 0x6C, 0xFC, 0x7D, 0x1E, 0xFC, 0xC8, 0x00, 0x00, 0x00, 0x8F, 0xFF,
+    0x5C, 0x41, 0xFF, 0xA8, 0x00, 0x00, 0x00, 0xB1, 0xFF, 0x39, 0x64, 0xFF, 0x85, 0x00, 0x00, 0x00,
+    0xD3, 0xFF, 0x16, 0x87, 0xFF, 0x62, 0x00, 0x56, 0xFC, 0xFF, 0xFF, 0xFD, 0xFF, 0xFF, 0xFE, 0x0B,
+    0x3A, 0xB5, 0xFF, 0xE7, 0xA4, 0xF4, 0xFF, 0xA8, 0x06, 0x00, 0x42, 0xFF, 0xA4, 0x01, 0xF3, 0xF4,
+    0x01, 0x00, 0x39, 0xBE, 0xFF, 0xD4, 0x9F, 0xFF, 0xF3, 0x9C, 0x05, 0x5F, 0xFF, 0x01, 0x00, 0xF1,
+    0x1C, 0x05, 0x02, 0xA9, 0xFF, 0x43, 0x5B, 0xFF, 0x8F, 0x04, 0x01, 0x00, 0xC7, 0xFF, 0x20, 0x78,
+    0xFF, 0x6D, 0x00, 0x00, 0x00, 0xE7, 0xFC, 0x04, 0x98, 0xFF, 0x4E, 0x00, 0x00, 0x08, 0xFF, 0xE0,
+    0x00, 0xB8, 0xFF, 0x2F, 0x00, 0x00, 0x25, 0xFF, 0xC0, 0x00, 0xD8, 0xFF, 0x47, 0x0E, 0x52, 0x08,
+    0x08, 0x12, 0x00, 0xFE, 0x89, 0x00, 0x13, 0x18, 0xBF, 0x0E, 0x11, 0x30, 0x82, 0x05, 0xF0, 0x14,
+    0x30, 0xBC, 0xF7, 0xFF, 0xD4, 0x43, 0x00, 0x0F, 0xEB, 0xFF, 0xCD, 0xC1, 0xFF, 0xF2, 0x13, 0x58,
+    0xFF, 0xF4, 0x07, 0x01, 0xD5, 0xFF, 0x62, 0x71, 0xFF, 0xF5, 0x05, 0x00, 0x9A, 0xCB, 0x56, 0x52,
+    0xFF, 0xFF, 0x87, 0x27, 0x00, 0x50, 0x0C, 0xE6, 0xFF, 0xFF, 0x8C, 0x8B, 0x13, 0x50, 0x39, 0xF4,
+    0xFF, 0xFF, 0xA7, 0x64, 0x13, 0x50, 0x34, 0xE9, 0xFF, 0xFF, 0x9F, 0x1B, 0x00, 0xF1, 0x1D, 0x23,
+    0xDD, 0xFF, 0xFF, 0x49, 0x05, 0x32, 0x47, 0x00, 0x23, 0xF6, 0xFF, 0xA8, 0x6F, 0xFF, 0xD3, 0x00,
+    0x00, 0xAD, 0xFF, 0xC8, 0x3C, 0xFF, 0xFD, 0x21, 0x00, 0xB0, 0xFF, 0xAC, 0x03, 0xD1, 0xFF, 0xE2,
+    0xAD, 0xFE, 0xFF, 0x4C, 0x00, 0x1C, 0xAD, 0xF2, 0xFF, 0xE4, 0x63, 0x79, 0x00, 0x13, 0xB7, 0xB5,
+    0x0E, 0x63, 0x5A, 0x00, 0x00, 0x00, 0x10, 0x10, 0x20, 0x01, 0xA1, 0x43, 0xD0, 0xF9, 0xE3, 0x81,
+    0x02, 0x00, 0x00, 0xC8, 0xD6, 0x0F, 0x00, 0xB1, 0x09, 0xEE, 0xFF, 0xB3, 0xEB, 0xFF, 0x54, 0x00,
+    0x14, 0xFE, 0x92, 0x10, 0x00, 0xB2, 0x3B, 0xFF, 0xC4, 0x00, 0x6C, 0xFF, 0x99, 0x00, 0x59, 0xFF,
+    0x4B, 0xFE, 0x0E, 0xA7, 0xFF, 0xB1, 0x00, 0x56, 0xFF, 0xAF, 0x00, 0xA0, 0xF9, 0x0B, 0x10, 0x00,
+    0x43, 0xAE, 0x01, 0xE6, 0xBD, 0xF7, 0x0A, 0x92, 0xFF, 0xC9, 0x00, 0x72, 0xFF, 0x96, 0x2E, 0xFF,
+    0x75, 0x10, 0x00, 0xF1, 0x11, 0x07, 0xEA, 0xFF, 0xAE, 0xEC, 0xFF, 0x4E, 0x75, 0xFF, 0x2E, 0x0A,
+    0x68, 0x97, 0x89, 0x37, 0x00, 0x00, 0x3F, 0xD3, 0xFF, 0xEC, 0x82, 0x01, 0xBC, 0xE6, 0x01, 0xB5,
+    0xFF, 0xFF, 0xFF, 0xFE, 0x41, 0xB3, 0x14, 0xB2, 0x00, 0x0B, 0xF9, 0xA0, 0x16, 0xFF, 0xEB, 0x19,
+    0x7C, 0xFF, 0xA0, 0x36, 0x00, 0xA2, 0x4A, 0xFF, 0x58, 0x38, 0xFF, 0xC6, 0x00, 0x43, 0xFF, 0xC1,
+    0x10, 0x00, 0xA2, 0x91, 0xFE, 0x13, 0x3B, 0xFF, 0xC5, 0x00, 0x41, 0xFF, 0xC3, 0x10, 0x00, 0xA1,
+    0xD8, 0xCA, 0x00, 0x26, 0xFF, 0xDB, 0x01, 0x55, 0xFF, 0xAF, 0x0F, 0x00, 0xB1, 0x1F, 0xFF, 0x83,
+    0x00, 0x02, 0xE0, 0xFF, 0xB2, 0xE1, 0xFF, 0x69, 0x10, 0x00, 0xD4, 0x65, 0xFF, 0x3C, 0x00, 0x00,
+    0x36, 0xC7, 0xFA, 0xEB, 0x92, 0x05, 0x0A, 0x0A, 0x08, 0x02, 0x52, 0x63, 0xDC, 0xF7, 0xBF, 0x38,
+    0xA3, 0x00, 0x51, 0xF6, 0xB5, 0xFF, 0xEF, 0x0C, 0x12, 0x02, 0x40, 0x8C, 0x00, 0xCA, 0xFF, 0xAF,
+    0x18, 0xF0, 0x01, 0x94, 0xFF, 0x87, 0x01, 0xE3, 0xFF, 0x36, 0x00, 0x00, 0x00, 0x54, 0xFF, 0xBE,
+    0x36, 0xFF, 0xD9, 0x72, 0x01, 0x61, 0x05, 0xDC, 0xFC, 0xC2, 0xFD, 0x40, 0x3C, 0x00, 0x42, 0x64,
+    0xFF, 0xFF, 0x64, 0xE7, 0x02, 0xF2, 0x37, 0xD2, 0xFF, 0xFE, 0x31, 0x00, 0x9A, 0xB8, 0x17, 0x00,
+    0x8A, 0xFF, 0xCA, 0xFF, 0xC6, 0x04, 0xF4, 0xFE, 0x09, 0x02, 0xEE, 0xFF, 0x28, 0xB7, 0xFF, 0x8B,
+    0xFF, 0xCA, 0x00, 0x21, 0xFF, 0xF4, 0x01, 0x29, 0xFC, 0xFF, 0xFF, 0x67, 0x00, 0x16, 0xFF, 0xFB,
+    0x0C, 0x02, 0xC3, 0xFF, 0xFF, 0x48, 0x03, 0x00, 0xBC, 0xFF, 0xC8, 0xCB, 0xFF, 0xF1, 0xFF, 0xFF,
+    0x30, 0x00, 0x1B, 0xAF, 0xF7, 0xF0, 0xA8, 0x17, 0x7E, 0xF6, 0x30, 0x05, 0x03, 0xC4, 0x02, 0xF1,
+    0x01, 0xD9, 0xFC, 0x0D, 0xDC, 0xE3, 0x00, 0xDC, 0xBB, 0x00, 0xDC, 0x92, 0x00, 0xDC, 0x69, 0x00,
+    0x04, 0x75, 0x00, 0x41, 0x04, 0x11, 0x01, 0xFD, 0x68, 0x0C, 0xF1, 0x12, 0xAD, 0xD4, 0x02, 0xCD,
+    0xFF, 0xB3, 0x42, 0xFF, 0xE0, 0x05, 0x88, 0xFF, 0x97, 0x00, 0xAF, 0xFF, 0x77, 0x00, 0xC6, 0xFF,
+    0x63, 0x00, 0xD6, 0xFF, 0x59, 0x00, 0xDB, 0xFF, 0x55, 0x00, 0xDC, 0xFF, 0x54, 0x04, 0x00, 0xF0,
+    0x11, 0xD6, 0xFF, 0x58, 0x00, 0xC7, 0xFF, 0x61, 0x00, 0xB0, 0xFF, 0x75, 0x00, 0x8A, 0xFF, 0x98,
+    0x00, 0x42, 0xFF, 0xDF, 0x05, 0x02, 0xCF, 0xFF, 0xB0, 0x00, 0x1D, 0xB1, 0xD7, 0x05, 0x05, 0x11,
+    0x00, 0x4C, 0x00, 0xF0, 0x18, 0x71, 0xD5, 0x52, 0x00, 0x00, 0x50, 0xF8, 0xFE, 0x39, 0x00, 0x00,
+    0x7A, 0xFF, 0xA7, 0x00, 0x00, 0x30, 0xFF, 0xED, 0x01, 0x00, 0x0D, 0xFF, 0xFF, 0x17, 0x00, 0x01,
+    0xFB, 0xFF, 0x2D, 0x00, 0x00, 0xF0, 0xFF, 0x3A, 0x00, 0x00, 0xED, 0xFF, 0xB2, 0x12, 0x20, 0xFF,
+    0x44, 0x0A, 0x00, 0x12, 0x42, 0x14, 0x00, 0x60, 0x01, 0xFA, 0xFF, 0x2E, 0x00, 0x0C, 0x28, 0x00,
+    0xA0, 0x32, 0xFF, 0xEE, 0x01, 0x00, 0x7C, 0xFF, 0xA7, 0x00, 0x4F, 0x46, 0x00, 0x32, 0x73, 0xD9,
+    0x54, 0xDC, 0x01, 0x23, 0x07, 0x06, 0x74, 0x18, 0xF0, 0x17, 0x18, 0xFC, 0x89, 0x00, 0x00, 0x01,
+    0x8E, 0x2B, 0xFC, 0x78, 0x72, 0x3D, 0x19, 0xE6, 0xFD, 0xFE, 0xFA, 0xFE, 0x78, 0x00, 0x04, 0xA1,
+    0xFF, 0xF6, 0x26, 0x00, 0x00, 0x2C, 0xF8, 0x8F, 0xF6, 0x98, 0x00, 0x00, 0x36, 0xC4, 0x0F, 0x87,
+    0xAC, 0x19, 0x53, 0x07, 0x07, 0x08, 0x00, 0x03, 0x02, 0x04, 0x11, 0x7B, 0x07, 0x00, 0xC1, 0xFF,
+    0x7C, 0x00, 0x00, 0x58, 0x9C, 0xAC, 0xFF, 0xCD, 0x9C, 0x95, 0x90, 0x63, 0x03, 0x83, 0xF4, 0x03,
+    0x04, 0x2C, 0xFF, 0x7F, 0x04, 0x04, 0x1C, 0x00, 0x05, 0x07, 0x00, 0x10, 0x01, 0x21, 0x01, 0x31,
+    0x04, 0x03, 0x06, 0xD4, 0x00, 0xF1, 0x02, 0x0C, 0x24, 0x23, 0x54, 0xFF, 0xF4, 0x54, 0xFF, 0xF4,
+    0x00, 0x3A, 0xE0, 0x16, 0xE1, 0x6E, 0x02, 0x2C, 0xF8, 0x0D, 0x11, 0x03, 0x68, 0x04, 0x70, 0x08,
+    0x9C, 0x9C, 0x9C, 0x9C, 0x0A, 0x0C, 0x4C, 0x00, 0x50, 0x10, 0x01, 0x04, 0x04, 0x04, 0x10, 0x04,
+    0x22, 0x04, 0x04, 0x76, 0x00, 0x40, 0x08, 0x24, 0x24, 0x02, 0x48, 0x04, 0x00, 0x04, 0x00, 0x35,
+    0x07, 0x07, 0x0E, 0xAC, 0x04, 0x20, 0xA1, 0xF2, 0xCA, 0x00, 0x30, 0x02, 0xEA, 0xB6, 0x0D, 0x00,
+    0x30, 0x32, 0xFF, 0x6E, 0x07, 0x00, 0x31, 0x79, 0xFF, 0x27, 0x9F, 0x1A, 0x10, 0xDF, 0x38, 0x03,
+    0x30, 0x0D, 0xFB, 0x98, 0x0D, 0x00, 0x30, 0x4F, 0xFF, 0x50, 0x07, 0x00, 0x21, 0x96, 0xFB, 0x3B,
+    0x00, 0x11, 0xDD, 0xA0, 0x02, 0x21, 0x24, 0xFF, 0xD4, 0x10, 0x30, 0x6C, 0xFF, 0x32, 0x07, 0x00,
+    0x20, 0xB3, 0xEA, 0xC8, 0x01, 0x30, 0x06, 0xF4, 0xA3, 0x0D, 0x00, 0x32, 0x41, 0xFF, 0x5C, 0x60,
+    0x00, 0x23, 0x09, 0x08, 0x6C, 0x00, 0xFF, 0x18, 0x09, 0x8D, 0xE6, 0xF9, 0xD2, 0x59, 0x00, 0x00,
+    0x9B, 0xFF, 0xEB, 0xB2, 0xFE, 0xFF, 0x48, 0x0B, 0xFA, 0xFF, 0x52, 0x00, 0xA6, 0xFF, 0xB7, 0x34,
+    0xFF, 0xFF, 0x27, 0x00, 0x7C, 0xFF, 0xE3, 0x3C, 0xFF, 0xFF, 0x24, 0x00, 0x78, 0xFF, 0xEC, 0x08,
+    0x00, 0x15, 0xF2, 0x14, 0x35, 0xFF, 0xFF, 0x29, 0x00, 0x7D, 0xFF, 0xE4, 0x0E, 0xFB, 0xFF, 0x57,
+    0x00, 0xAB, 0xFF, 0xB8, 0x00, 0x99, 0xFF, 0xEB, 0xAF, 0xFE, 0xFF, 0x4A, 0x00, 0x09, 0x8E, 0xE9,
+    0xFD, 0xD5, 0x5C, 0x00, 0x09, 0x06, 0x0E, 0xF6, 0x03, 0xFF, 0x0A, 0x05, 0x6B, 0xF6, 0xFC, 0x0C,
+    0x4C, 0xDC, 0xFF, 0xFF, 0xFF, 0x0C, 0x88, 0xFD, 0xE1, 0xFF, 0xFF, 0x0C, 0x21, 0x0F, 0x50, 0xFF,
+    0xFF, 0x0C, 0x00, 0x00, 0x06, 0x00, 0x27, 0x05, 0xD4, 0x00, 0xF1, 0x18, 0x06, 0x85, 0xE1, 0xFA,
+    0xDB, 0x74, 0x02, 0x00, 0x89, 0xFF, 0xF6, 0xB1, 0xF9, 0xFF, 0x6D, 0x02, 0xF0, 0xFF, 0x70, 0x00,
+    0x87, 0xFF, 0xCE, 0x1C, 0xFF, 0xFF, 0x39, 0x00, 0x64, 0xFF, 0xF3, 0x17, 0xA0, 0xA0, 0x1E, 0x00,
+    0x8B, 0xFF, 0xE9, 0xD0, 0x04, 0x30, 0xEA, 0xFF, 0xAA, 0x08, 0x00, 0x30, 0x8C, 0xFF, 0xFF, 0x8D,
+    0x03, 0x40, 0x2B, 0xFB, 0xFF, 0x9D, 0xDB, 0x01, 0x30, 0xC0, 0xFF, 0xE7, 0x2F, 0x05, 0x30, 0x5A,
+    0xFF, 0xFF, 0x5B, 0x02, 0x51, 0x0F, 0xE7, 0xFF, 0xB0, 0x01, 0xA0, 0x03, 0x10, 0xF2, 0x9D, 0x09,
+    0x92, 0x23, 0xFC, 0xFF, 0xD9, 0x9C, 0x9C, 0x9C, 0x60, 0x3C, 0x83, 0x05, 0x15, 0x9C, 0x78, 0x00,
+    0xF0, 0x17, 0x10, 0x98, 0xE9, 0xF8, 0xD1, 0x5B, 0x00, 0x00, 0xB8, 0xFF, 0xE4, 0xB5, 0xFE, 0xFF,
+    0x4F, 0x25, 0xFF, 0xFF, 0x3A, 0x00, 0xA7, 0xFF, 0xB8, 0x4C, 0xFF, 0xFF, 0x11, 0x00, 0x7D, 0xFF,
+    0xDC, 0x25, 0x74, 0x74, 0x06, 0x00, 0x8A, 0xFF, 0xFC, 0x05, 0x31, 0x00, 0x1C, 0xD8, 0x92, 0x04,
+    0x40, 0x6B, 0xFF, 0xFF, 0x94, 0x09, 0x02, 0x51, 0x46, 0xC6, 0xFF, 0xEA, 0x2A, 0x55, 0x02, 0xC0,
+    0xBA, 0xFF, 0xA4, 0x1D, 0x5C, 0x5C, 0x05, 0x00, 0x80, 0xFF, 0xD8, 0x4A, 0xEB, 0x02, 0xF7, 0x0B,
+    0x80, 0xFF, 0xD8, 0x21, 0xFF, 0xFF, 0x61, 0x06, 0xC0, 0xFF, 0xAA, 0x00, 0xC2, 0xFF, 0xFF, 0xFB,
+    0xFF, 0xFF, 0x4B, 0x00, 0x17, 0xA4, 0xEE, 0xFD, 0xD7, 0x63, 0x54, 0x06, 0x51, 0x00, 0x1D, 0xFA,
+    0xFC, 0xDD, 0x09, 0x00, 0x41, 0x7F, 0xFF, 0xFF, 0xE0, 0x27, 0x0A, 0x13, 0xE3, 0x09, 0x00, 0x32,
+    0x4B, 0xFF, 0xC7, 0x09, 0x00, 0x31, 0xB0, 0xFF, 0x75, 0x09, 0x00, 0x41, 0x1A, 0xFC, 0xC8, 0x58,
+    0x09, 0x00, 0x31, 0x7B, 0xFF, 0x75, 0x09, 0x00, 0x41, 0x02, 0xE0, 0xFF, 0x22, 0x09, 0x00, 0x41,
+    0x45, 0xFF, 0xCF, 0x00, 0x09, 0x00, 0xC2, 0x64, 0xFF, 0xFF, 0xFC, 0xFE, 0xFF, 0xFF, 0xFC, 0x4B,
+    0x63, 0xFC, 0xFC, 0x09, 0x00, 0x00, 0x41, 0x00, 0x02, 0x36, 0x00, 0x0F, 0x09, 0x00, 0x00, 0x05,
+    0x00, 0x01, 0x20, 0xDB, 0xFC, 0x01, 0x00, 0xC2, 0x63, 0x00, 0xE2, 0xFF, 0xB2, 0xA4, 0xA4, 0xA4,
+    0x41, 0x00, 0xE6, 0xFF, 0x73, 0x07, 0x31, 0xE9, 0xFF, 0x17, 0x08, 0x00, 0x22, 0xED, 0xFF, 0x29,
+    0x00, 0xF3, 0x08, 0xF0, 0xFF, 0xAB, 0xF3, 0xEA, 0x89, 0x03, 0x00, 0xF4, 0xFF, 0xEB, 0xB0, 0xFB,
+    0xFF, 0x69, 0x00, 0xD0, 0xD8, 0x36, 0x00, 0x8F, 0xFF, 0xC2, 0xDB, 0x04, 0x11, 0xE4, 0x08, 0x00,
+    0xF6, 0x13, 0x5E, 0xFF, 0xE9, 0x26, 0xFC, 0xFC, 0x27, 0x00, 0x64, 0xFF, 0xD8, 0x0D, 0xFE, 0xFF,
+    0x4F, 0x00, 0x8A, 0xFF, 0xA8, 0x00, 0xB5, 0xFF, 0xE7, 0xA8, 0xF8, 0xFF, 0x44, 0x00, 0x18, 0xAE,
+    0xF0, 0xFD, 0xD9, 0x61, 0x00, 0x01, 0xE0, 0x02, 0x76, 0xDF, 0xF9, 0xDD, 0x82, 0x04, 0x00, 0x00,
+    0x6A, 0xFF, 0xF9, 0xAF, 0xF4, 0x9E, 0x03, 0xF2, 0x07, 0xD8, 0xFF, 0x7B, 0x00, 0x7A, 0xFF, 0xD5,
+    0x00, 0x0F, 0xFF, 0xFF, 0x4C, 0x00, 0x31, 0x88, 0x7F, 0x00, 0x22, 0xFF, 0xFF, 0x3D, 0x00, 0x1D,
+    0x03, 0x51, 0xFF, 0x5F, 0x89, 0x92, 0x44, 0x09, 0x00, 0x50, 0xFC, 0xFF, 0xFF, 0xFF, 0x5A, 0x09,
+    0x00, 0x50, 0x93, 0x10, 0xAF, 0xFF, 0xCD, 0x09, 0x00, 0x70, 0x3C, 0x00, 0x5D, 0xFF, 0xFC, 0x03,
+    0x23, 0x09, 0x00, 0xF0, 0x04, 0x52, 0xFF, 0xFF, 0x09, 0x13, 0xFF, 0xFF, 0x42, 0x00, 0x57, 0xFF,
+    0xF6, 0x01, 0x00, 0xDB, 0xFF, 0x74, 0x00, 0x86, 0xFF, 0x05, 0x50, 0x68, 0xFF, 0xF5, 0xA9, 0xF7,
+    0x16, 0x02, 0x51, 0x01, 0x73, 0xE1, 0xFD, 0xDD, 0xE0, 0x05, 0x13, 0x09, 0xB8, 0x03, 0x11, 0x53,
+    0xFF, 0x00, 0x80, 0x9E, 0x36, 0xA4, 0xA4, 0xA4, 0xE8, 0xFF, 0x91, 0x12, 0x00, 0x11, 0xE1, 0x6F,
+    0x03, 0x50, 0x19, 0xFF, 0xFF, 0x26, 0x00, 0xA3, 0x02, 0x11, 0xEE, 0xE2, 0x1D, 0x20, 0xFF, 0xB8,
+    0x1B, 0x00, 0x30, 0xBF, 0xFF, 0x82, 0x7F, 0x08, 0x11, 0xF4, 0xC8, 0x06, 0xA0, 0x2F, 0xFF, 0xFF,
+    0x15, 0x00, 0x00, 0x00, 0x66, 0xFF, 0xDE, 0x1B, 0x00, 0x10, 0x9E, 0x15, 0x05, 0x40, 0x00, 0x00,
+    0xD6, 0xFF, 0xAF, 0x14, 0x10, 0x10, 0x45, 0x02, 0x00, 0x9C, 0x01, 0x29, 0xFB, 0x09, 0x6C, 0x01,
+    0x60, 0x0C, 0x95, 0xE9, 0xF8, 0xCB, 0x44, 0x2D, 0x00, 0xF0, 0x1D, 0xE9, 0xBE, 0xFF, 0xF9, 0x22,
+    0x06, 0xF6, 0xFF, 0x4B, 0x01, 0xD1, 0xFF, 0x77, 0x1C, 0xFF, 0xFF, 0x23, 0x00, 0xA7, 0xFF, 0x98,
+    0x0C, 0xFE, 0xFF, 0x33, 0x00, 0xB6, 0xFF, 0x86, 0x00, 0xB9, 0xFF, 0x8B, 0x1A, 0xF1, 0xFF, 0x39,
+    0x00, 0x20, 0xF1, 0xFF, 0xFF, 0xFF, 0x92, 0x7F, 0x00, 0xF0, 0x0F, 0xE7, 0xB9, 0xFF, 0xE8, 0x1F,
+    0x1A, 0xFD, 0xFF, 0x36, 0x00, 0xB5, 0xFF, 0x97, 0x4C, 0xFF, 0xFB, 0x03, 0x00, 0x7D, 0xFF, 0xCF,
+    0x4D, 0xFF, 0xF8, 0x01, 0x00, 0x7A, 0xFF, 0xD1, 0x28, 0xAC, 0x00, 0xF6, 0x03, 0xA8, 0xFF, 0xAB,
+    0x01, 0xC2, 0xFF, 0xDC, 0xAE, 0xFF, 0xFF, 0x48, 0x00, 0x16, 0xA4, 0xEF, 0xFC, 0xD4, 0x5D, 0x78,
+    0x00, 0x60, 0x05, 0x8A, 0xE5, 0xF8, 0xCA, 0x44, 0x0C, 0x03, 0xF0, 0x0A, 0xEA, 0xB9, 0xFF, 0xFB,
+    0x2E, 0x0A, 0xF6, 0xFF, 0x52, 0x00, 0xB8, 0xFF, 0x9D, 0x34, 0xFF, 0xFF, 0x20, 0x00, 0x84, 0xFF,
+    0xD2, 0x46, 0xFF, 0xFF, 0x19, 0x38, 0x04, 0x10, 0x3E, 0x10, 0x04, 0xD0, 0x7C, 0xFF, 0xE4, 0x13,
+    0xFD, 0xFF, 0x72, 0x0F, 0xBD, 0xFF, 0xE4, 0x00, 0x9C, 0x5F, 0x07, 0x83, 0xFF, 0xE4, 0x00, 0x05,
+    0x69, 0x9F, 0x81, 0x8E, 0xE4, 0x01, 0xF1, 0x17, 0x7E, 0xFF, 0xE1, 0x1A, 0xA0, 0xA0, 0x14, 0x00,
+    0x8F, 0xFF, 0xCD, 0x10, 0xFE, 0xFF, 0x4C, 0x04, 0xCA, 0xFF, 0x99, 0x00, 0xB6, 0xFF, 0xFB, 0xE8,
+    0xFF, 0xFC, 0x31, 0x00, 0x14, 0xA1, 0xEC, 0xFC, 0xD4, 0x50, 0x00, 0x04, 0x03, 0x09, 0x30, 0x04,
+    0x95, 0x95, 0x9C, 0x2C, 0xF4, 0xFF, 0x48, 0x04, 0x04, 0x02, 0x22, 0x05, 0x06, 0x12, 0x00, 0x40,
+    0x04, 0x03, 0x0C, 0x01, 0xD4, 0x08, 0x86, 0xF5, 0xFC, 0x47, 0xF8, 0xFF, 0x48, 0x2B, 0x2C, 0x2D,
+    0x0D, 0xF6, 0x06, 0x23, 0x24, 0x0C, 0xF8, 0xFF, 0x54, 0xF8, 0xFF, 0x54, 0x07, 0xDB, 0x42, 0xA9,
+    0xCC, 0x08, 0x15, 0x02, 0x00, 0x07, 0x06, 0x0B, 0xE2, 0x0A, 0x00, 0xBF, 0x08, 0xF0, 0x1E, 0x01,
+    0x66, 0x89, 0x00, 0x00, 0x16, 0xB2, 0xFF, 0x94, 0x00, 0x4B, 0xE9, 0xFF, 0xC8, 0x23, 0x5F, 0xFF,
+    0xFD, 0x82, 0x05, 0x00, 0x7C, 0xFF, 0x94, 0x01, 0x00, 0x00, 0x4F, 0xFA, 0xFF, 0xA8, 0x10, 0x00,
+    0x00, 0x30, 0xD4, 0xFF, 0xE0, 0x37, 0x00, 0x00, 0x09, 0x90, 0xFF, 0x94, 0x35, 0x00, 0x24, 0x45,
+    0x79, 0x51, 0x18, 0x00, 0x70, 0x06, 0x00, 0xE0, 0x05, 0x10, 0x03, 0xE0, 0x05, 0x31, 0x9C, 0x31,
+    0x04, 0x0E, 0x04, 0x11, 0x50, 0xE2, 0x05, 0x2F, 0x04, 0x02, 0x15, 0x00, 0x02, 0x00, 0x34, 0x00,
+    0x02, 0x80, 0x00, 0x12, 0x02, 0xFF, 0x05, 0x31, 0x0C, 0xC4, 0x21, 0x07, 0x00, 0xB0, 0xFF, 0xF2,
+    0x5F, 0x01, 0x00, 0x00, 0x01, 0x6B, 0xF7, 0xFF, 0xAB, 0x86, 0x17, 0x40, 0x2A, 0xD0, 0xFF, 0xE6,
+    0x9D, 0x00, 0xF0, 0x07, 0x1C, 0xED, 0xFF, 0x08, 0x00, 0x00, 0x47, 0xE8, 0xFF, 0xD1, 0x04, 0x03,
+    0x8D, 0xFF, 0xFE, 0x89, 0x07, 0x00, 0x0C, 0xFF, 0xE1, 0x3F, 0x31, 0x00, 0x2A, 0xA2, 0x0F, 0x86,
+    0x1F, 0x14, 0x08, 0xA0, 0x01, 0xF1, 0x17, 0x2D, 0xB9, 0xF2, 0xF4, 0xC2, 0x3F, 0x00, 0x09, 0xE7,
+    0xFF, 0xD3, 0xC5, 0xFF, 0xF9, 0x28, 0x36, 0xFF, 0xFE, 0x0E, 0x01, 0xC9, 0xFF, 0x87, 0x2A, 0xFF,
+    0xF7, 0x07, 0x00, 0xA7, 0xFF, 0xA6, 0x05, 0x33, 0x06, 0x00, 0x01, 0xD6, 0xFF, 0x39, 0x0F, 0x30,
+    0x3F, 0xFF, 0xFF, 0xA6, 0x1A, 0x40, 0x0D, 0xD8, 0xFF, 0xAD, 0x35, 0x05, 0x41, 0xB6, 0xFF, 0xD5,
+    0x10, 0x66, 0x06, 0x21, 0xD8, 0x19, 0xCD, 0x13, 0x02, 0xEF, 0x00, 0x41, 0x00, 0x47, 0x88, 0x4F,
+    0x08, 0x00, 0x21, 0x16, 0x24, 0x17, 0x00, 0x47, 0x00, 0x98, 0xFF, 0xB0, 0x08, 0x00, 0x22, 0x10,
+    0x10, 0xD4, 0x07, 0x01, 0x85, 0x00, 0x82, 0x3C, 0x9D, 0xD4, 0xF6, 0xF6, 0xD2, 0x89, 0x15, 0x0E,
+    0x00, 0xB1, 0x0D, 0xA0, 0xFF, 0xFF, 0xD5, 0xAB, 0xB1, 0xE6, 0xFF, 0xED, 0x3B, 0xA2, 0x00, 0x40,
+    0xC4, 0xFF, 0xC4, 0x29, 0x2E, 0x01, 0x41, 0x6D, 0xFC, 0xEB, 0x18, 0xAA, 0x04, 0x13, 0xB7, 0x6E,
+    0x0C, 0x10, 0x76, 0x98, 0x02, 0xF2, 0x85, 0x15, 0xF6, 0xF6, 0x18, 0x00, 0x24, 0xB7, 0xF4, 0xA0,
+    0xFC, 0xAF, 0x05, 0xE3, 0xEC, 0x02, 0x00, 0x6D, 0xFF, 0x92, 0x00, 0x15, 0xE6, 0xFF, 0xCF, 0xD5,
+    0xFF, 0x8B, 0x00, 0x96, 0xFF, 0x23, 0x00, 0xAD, 0xFF, 0x3F, 0x00, 0x93, 0xFF, 0xA9, 0x02, 0x92,
+    0xFF, 0x65, 0x00, 0x70, 0xFF, 0x37, 0x00, 0xDA, 0xFF, 0x0D, 0x07, 0xF2, 0xFF, 0x1E, 0x00, 0xB6,
+    0xFF, 0x3F, 0x00, 0x6C, 0xFF, 0x34, 0x01, 0xFA, 0xEA, 0x00, 0x35, 0xFF, 0xDD, 0x00, 0x00, 0xDA,
+    0xFF, 0x19, 0x00, 0x8D, 0xFF, 0x1A, 0x06, 0xFF, 0xDF, 0x00, 0x4B, 0xFF, 0xCD, 0x00, 0x05, 0xFA,
+    0xF3, 0x01, 0x02, 0xD6, 0xDE, 0x01, 0x01, 0xFA, 0xEB, 0x00, 0x38, 0xFF, 0xF7, 0x33, 0x7C, 0xFF,
+    0xD9, 0x00, 0x6C, 0xFF, 0x79, 0x00, 0x00, 0xDE, 0xFF, 0x14, 0x06, 0xE2, 0xFF, 0xFF, 0xF5, 0xF6,
+    0xFA, 0xC3, 0xFF, 0xD5, 0x0A, 0x00, 0x00, 0x9D, 0xFF, 0x64, 0x00, 0x30, 0xBF, 0xD7, 0x57, 0x6C,
+    0xF2, 0xF4, 0xA6, 0x16, 0x00, 0x00, 0x00, 0x3A, 0xFF, 0xE1, 0x11, 0xE9, 0x01, 0x03, 0x65, 0x01,
+    0x41, 0x9F, 0xFF, 0xD4, 0x37, 0x10, 0x00, 0x13, 0x0C, 0x65, 0x06, 0x94, 0x9B, 0xFF, 0xFF, 0xDA,
+    0xAE, 0xA4, 0xBC, 0xE8, 0x9A, 0xFF, 0x00, 0xA8, 0x3B, 0xA0, 0xD8, 0xFA, 0xFC, 0xE0, 0xBA, 0x68,
+    0x00, 0x00, 0xF0, 0x0B, 0x41, 0x06, 0xF5, 0xFC, 0xD2, 0x09, 0x00, 0x53, 0x31, 0xFF, 0xFF, 0xFD,
+    0x0B, 0xBE, 0x09, 0x01, 0xD4, 0x03, 0x41, 0x00, 0x97, 0xFF, 0xEE, 0xB1, 0x0B, 0x41, 0x00, 0xCA,
+    0xFF, 0xA0, 0x6B, 0x0A, 0x61, 0x06, 0xF9, 0xFF, 0x4D, 0xFF, 0xD3, 0x2C, 0x00, 0x50, 0xEC, 0x0E,
+    0xFF, 0xFD, 0x0A, 0x2C, 0x00, 0x50, 0xC3, 0x00, 0xE4, 0xFF, 0x39, 0x2C, 0x00, 0x50, 0x99, 0x00,
+    0xBA, 0xFF, 0x6C, 0x2C, 0x00, 0x00, 0xB8, 0x04, 0x10, 0x9F, 0x2C, 0x00, 0x50, 0xB9, 0xA4, 0xC4,
+    0xFF, 0xD2, 0x58, 0x00, 0xF1, 0x09, 0x1B, 0x00, 0x3C, 0xFF, 0xFC, 0x09, 0x64, 0xFF, 0xF0, 0x01,
+    0x00, 0x11, 0xFF, 0xFF, 0x38, 0x97, 0xFF, 0xC5, 0x00, 0x00, 0x00, 0xE6, 0xFF, 0x6B, 0x30, 0x04,
+    0x01, 0xC0, 0x00, 0xF0, 0x09, 0xF5, 0xFC, 0xFC, 0xFA, 0xE5, 0xA4, 0x21, 0x00, 0xF8, 0xFF, 0xD5,
+    0xAB, 0xE4, 0xFF, 0xE0, 0x0A, 0xF8, 0xFF, 0x88, 0x00, 0x0D, 0xED, 0xFF, 0x4D, 0x08, 0x00, 0x41,
+    0x00, 0xC5, 0xFF, 0x6D, 0x08, 0x00, 0xC0, 0xD8, 0xFF, 0x5B, 0xF8, 0xFF, 0x88, 0x03, 0x52, 0xFF,
+    0xF3, 0x18, 0xF8, 0xB7, 0x02, 0x20, 0xE9, 0x3C, 0x30, 0x00, 0x50, 0xA9, 0xE5, 0xFF, 0xCF, 0x17,
+    0x20, 0x00, 0x41, 0x0A, 0xE2, 0xFF, 0x8E, 0x28, 0x00, 0x31, 0x9F, 0xFF, 0xCB, 0x08, 0x00, 0x30,
+    0x99, 0xFF, 0xD2, 0x08, 0x00, 0xC0, 0x03, 0xD5, 0xFF, 0xA9, 0xF8, 0xFF, 0xD2, 0x9F, 0xD6, 0xFF,
+    0xFE, 0x3E, 0x38, 0x00, 0x36, 0xF7, 0xC8, 0x4B, 0x00, 0x01, 0x70, 0x04, 0x7A, 0xD8, 0xF8, 0xED,
+    0xB2, 0x25, 0x50, 0x02, 0xF1, 0x13, 0xFA, 0xAE, 0xDA, 0xFF, 0xE0, 0x07, 0x03, 0xEE, 0xFF, 0x86,
+    0x00, 0x16, 0xFF, 0xFF, 0x48, 0x20, 0xFF, 0xFF, 0x5D, 0x00, 0x00, 0xFB, 0xFF, 0x6B, 0x2F, 0xFF,
+    0xFF, 0x58, 0x00, 0x00, 0xF8, 0xFF, 0x70, 0x30, 0x09, 0x00, 0x32, 0x10, 0x10, 0x07, 0x09, 0x00,
+    0x00, 0x96, 0x0C, 0x0A, 0x09, 0x00, 0x35, 0x33, 0x34, 0x17, 0x2D, 0x00, 0xFA, 0x15, 0x21, 0xFF,
+    0xFF, 0x5E, 0x00, 0x01, 0xFC, 0xFF, 0x69, 0x03, 0xEF, 0xFF, 0x89, 0x00, 0x1B, 0xFF, 0xFF, 0x43,
+    0x00, 0x83, 0xFF, 0xFA, 0xAB, 0xD5, 0xFF, 0xDB, 0x04, 0x00, 0x03, 0x7B, 0xDF, 0xFC, 0xF2, 0xB5,
+    0x25, 0x00, 0x00, 0x01, 0x31, 0xE4, 0xA7, 0x23, 0xD0, 0x00, 0x40, 0xE8, 0xFF, 0xE6, 0x0D, 0xB8,
+    0x00, 0x40, 0x25, 0xFF, 0xFF, 0x63, 0x08, 0x00, 0x41, 0x01, 0xF8, 0xFF, 0x8C, 0xD0, 0x00, 0x31,
+    0xF5, 0xFF, 0x98, 0x08, 0x00, 0x1F, 0xF4, 0x08, 0x00, 0x0C, 0x03, 0x28, 0x00, 0x40, 0x01, 0xFC,
+    0xFF, 0x88, 0x08, 0x00, 0x20, 0x2C, 0xFF, 0x38, 0x01, 0x60, 0xD2, 0xA2, 0xE6, 0xFF, 0xE0, 0x09,
+    0x00, 0x01, 0x65, 0xE9, 0xAC, 0x21, 0x00, 0x07, 0x06, 0x78, 0x00, 0x91, 0xFC, 0xFC, 0xC9, 0xF8,
+    0xFF, 0xD5, 0xA4, 0xA4, 0x83, 0x3C, 0x00, 0x1F, 0x00, 0x06, 0x00, 0x01, 0x41, 0xFF, 0xFC, 0xFC,
+    0x1C, 0x24, 0x00, 0x1F, 0x12, 0x24, 0x00, 0x07, 0x41, 0xD2, 0x9C, 0x9C, 0x82, 0x96, 0x01, 0x19,
+    0xD4, 0x5C, 0x00, 0x11, 0xAE, 0x38, 0x00, 0x1F, 0x71, 0x5C, 0x00, 0x0A, 0x11, 0x0C, 0x24, 0x00,
+    0x1E, 0x08, 0x24, 0x00, 0x0E, 0x06, 0x00, 0x05, 0xB8, 0x01, 0x70, 0x03, 0x77, 0xD8, 0xF9, 0xEE,
+    0xB3, 0x2C, 0xA8, 0x03, 0xF0, 0x02, 0xFA, 0xB1, 0xD6, 0xFF, 0xEB, 0x0F, 0x02, 0xEC, 0xFF, 0x87,
+    0x00, 0x0C, 0xF9, 0xFF, 0x5E, 0x1D, 0xFF, 0xD6, 0x06, 0x41, 0xE0, 0xFF, 0x85, 0x2D, 0x8B, 0x01,
+    0x3F, 0x94, 0xAC, 0x5F, 0xAF, 0x01, 0x03, 0x50, 0x20, 0xFC, 0xFC, 0xFC, 0x9A, 0x09, 0x00, 0x52,
+    0x15, 0xA4, 0xDF, 0xFF, 0x9C, 0x2D, 0x00, 0xF3, 0x1B, 0xA5, 0xFF, 0x9C, 0x19, 0xFF, 0xFF, 0x61,
+    0x00, 0x00, 0xAF, 0xFF, 0x9C, 0x01, 0xE6, 0xFF, 0x90, 0x00, 0x05, 0xE2, 0xFF, 0x9C, 0x00, 0x80,
+    0xFF, 0xFC, 0xAF, 0xCB, 0xF6, 0xFF, 0x9C, 0x00, 0x05, 0x82, 0xE4, 0xFD, 0xD0, 0x49, 0xFF, 0x9C,
+    0x00, 0x00, 0x0A, 0xB8, 0x01, 0xFF, 0x01, 0xF1, 0xFC, 0x8E, 0x00, 0x00, 0xA2, 0xFC, 0xD9, 0xF4,
+    0xFF, 0x90, 0x00, 0x00, 0xA4, 0xFF, 0xDC, 0x08, 0x00, 0x0F, 0x40, 0xFF, 0xFC, 0xFC, 0xFF, 0x08,
+    0x00, 0x4E, 0xD8, 0xA4, 0xA4, 0xDF, 0x30, 0x00, 0x0F, 0x08, 0x00, 0x0D, 0x22, 0x05, 0x03, 0x78,
+    0x00, 0x6F, 0xE1, 0xFC, 0x92, 0xE4, 0xFF, 0x94, 0x03, 0x00, 0x11, 0x44, 0x00, 0x00, 0x06, 0x05,
+    0xEC, 0x03, 0x85, 0xFC, 0xFC, 0x7E, 0x00, 0x00, 0xFF, 0xFF, 0x7F, 0x05, 0x00, 0x1A, 0x7E, 0x05,
+    0x00, 0x15, 0x7D, 0x05, 0x00, 0x12, 0x7C, 0x05, 0x00, 0x40, 0x02, 0xFF, 0xFF, 0x7B, 0xFE, 0x07,
+    0xA9, 0x6C, 0xA9, 0xF4, 0xFF, 0xFF, 0x30, 0xD8, 0xFD, 0xE3, 0x70, 0xB4, 0x02, 0x51, 0x86, 0x00,
+    0x0B, 0xEB, 0xFC, 0x9C, 0x03, 0xB0, 0x6A, 0xFF, 0xF4, 0x10, 0xF8, 0xFF, 0x88, 0x02, 0xDB, 0xFF,
+    0x98, 0xAA, 0x01, 0x40, 0x4F, 0xFF, 0xFF, 0x2D, 0x08, 0x00, 0x30, 0xC1, 0xFF, 0xC0, 0xBA, 0x01,
+    0x11, 0xBC, 0xA8, 0x0A, 0x01, 0x1E, 0x02, 0x10, 0x1E, 0x08, 0x00, 0x20, 0xEF, 0xEF, 0x5E, 0x0A,
+    0x70, 0xF8, 0xFF, 0x91, 0x98, 0xFF, 0xD6, 0x01, 0x28, 0x00, 0x40, 0x3B, 0xFF, 0xFF, 0x36, 0x08,
+    0x00, 0x41, 0x01, 0xDD, 0xFF, 0x96, 0xEA, 0x01, 0x43, 0x81, 0xFF, 0xEF, 0x08, 0x04, 0x03, 0x11,
+    0x57, 0xFA, 0x01, 0x36, 0xC7, 0xFF, 0xB8, 0x58, 0x02, 0x1E, 0x86, 0x28, 0x02, 0x0F, 0x06, 0x00,
+    0x22, 0x42, 0xDF, 0xB8, 0xB8, 0x99, 0xB4, 0x02, 0x22, 0x0C, 0x0A, 0x5C, 0x00, 0xF0, 0x09, 0xC4,
+    0xFC, 0xE2, 0x00, 0x00, 0x00, 0x42, 0xFC, 0xFC, 0x5D, 0xCB, 0xFF, 0xFF, 0x1A, 0x00, 0x00, 0x78,
+    0xFF, 0xFF, 0x62, 0xCF, 0xFF, 0xFF, 0x4D, 0x2D, 0x10, 0xF5, 0x61, 0xFF, 0x66, 0xD4, 0xFF, 0xFF,
+    0x81, 0x00, 0x00, 0xE2, 0xFF, 0xFF, 0x6B, 0xD8, 0xFF, 0xF4, 0xB5, 0x00, 0x18, 0xFF, 0xF6, 0xFF,
+    0x6F, 0xDC, 0xFF, 0xBF, 0xE9, 0x01, 0x4D, 0xFF, 0xC0, 0xFF, 0x73, 0xE0, 0xFF, 0x85, 0xFF, 0x1D,
+    0x82, 0xFF, 0x88, 0xFF, 0x77, 0xE5, 0xFF, 0x4C, 0xFF, 0x51, 0xB7, 0xE4, 0x6B, 0xFF, 0x7C, 0xE9,
+    0xFF, 0x14, 0xFF, 0x86, 0xED, 0xAF, 0x66, 0xFF, 0x80, 0xED, 0xFE, 0x00, 0xDC, 0xDA, 0xFF, 0x7A,
+    0x61, 0xFF, 0x84, 0xF2, 0xFA, 0x00, 0xA7, 0xFF, 0xFF, 0x45, 0x5D, 0xFF, 0x89, 0xF6, 0xF6, 0x00,
+    0x72, 0xFF, 0xFF, 0x11, 0x58, 0xFF, 0x8D, 0xFA, 0xF2, 0x00, 0x3D, 0xFF, 0xDB, 0x00, 0x54, 0xFF,
+    0x91, 0xFE, 0xEE, 0x00, 0x0B, 0xFD, 0xA6, 0x00, 0x4F, 0xFF, 0x96, 0x68, 0x01, 0xA0, 0xEA, 0x09,
+    0x00, 0x00, 0xDD, 0xFC, 0x34, 0xF8, 0xFF, 0x62, 0xD8, 0x02, 0x52, 0x34, 0xF8, 0xFF, 0xCF, 0x01,
+    0x08, 0x00, 0x23, 0xFF, 0x3B, 0x08, 0x00, 0x12, 0xA8, 0x08, 0x00, 0x31, 0xFC, 0xFB, 0x1A, 0x08,
+    0x00, 0x31, 0xAD, 0xFF, 0x82, 0x08, 0x00, 0x40, 0x47, 0xFE, 0xE9, 0xE7, 0x08, 0x00, 0x41, 0x28,
+    0xB3, 0xFF, 0xFF, 0x08, 0x00, 0x13, 0x4A, 0x08, 0x00, 0x22, 0x03, 0xDF, 0x08, 0x00, 0x23, 0x00,
+    0x78, 0x08, 0x00, 0x22, 0x16, 0xFA, 0x08, 0x00, 0x55, 0x00, 0xA5, 0xFF, 0x34, 0x0A, 0x1C, 0x05,
+    0x60, 0x79, 0xD7, 0xF9, 0xEE, 0xB5, 0x2E, 0x1C, 0x05, 0xF0, 0x04, 0xFB, 0xB1, 0xD5, 0xFF, 0xF0,
+    0x18, 0x03, 0xF0, 0xFF, 0x87, 0x00, 0x0B, 0xF2, 0xFF, 0x79, 0x21, 0xFF, 0xFF, 0x5F, 0x10, 0x12,
+    0x21, 0xAB, 0x2F, 0x6D, 0x03, 0x4F, 0xD0, 0xFF, 0xBC, 0x30, 0x09, 0x00, 0x18, 0x20, 0xBB, 0x1F,
+    0x1C, 0x05, 0xFA, 0x0F, 0x00, 0xD3, 0xFF, 0xAA, 0x02, 0xEC, 0xFF, 0x85, 0x00, 0x09, 0xF2, 0xFF,
+    0x79, 0x00, 0x82, 0xFF, 0xF9, 0xA9, 0xCE, 0xFF, 0xF0, 0x18, 0x00, 0x04, 0x7A, 0xDA, 0xFC, 0xF2,
+    0xBE, 0x31, 0x1C, 0x05, 0x40, 0xFC, 0xF3, 0xBA, 0x2C, 0x1C, 0x05, 0x50, 0xA8, 0xDD, 0xFF, 0xE8,
+    0x0E, 0xBE, 0x01, 0x41, 0x10, 0xF8, 0xFF, 0x59, 0xC6, 0x01, 0x31, 0xDC, 0xFF, 0x7E, 0x08, 0x00,
+    0x30, 0xE5, 0xFF, 0x7A, 0x80, 0x02, 0x41, 0x4C, 0xFF, 0xFF, 0x48, 0xD2, 0x01, 0x30, 0xFF, 0xBA,
+    0x02, 0x56, 0x04, 0x33, 0x96, 0x57, 0x04, 0xEE, 0x01, 0x1F, 0x00, 0x08, 0x00, 0x16, 0x23, 0x0A,
+    0x09, 0x34, 0x08, 0x0C, 0x00, 0x01, 0x14, 0x17, 0x00, 0x01, 0x1F, 0x78, 0x00, 0x01, 0x3D, 0x13,
+    0x78, 0x00, 0x01, 0x11, 0xF1, 0x00, 0x01, 0x42, 0xFD, 0xFF, 0xFA, 0x3A, 0x82, 0x01, 0x32, 0x90,
+    0xFF, 0xAA, 0x32, 0x10, 0x43, 0x04, 0xAC, 0xF7, 0x09, 0xF9, 0x04, 0x2A, 0x4D, 0x00, 0x1C, 0x01,
+    0x40, 0xF9, 0xE3, 0xA6, 0x27, 0x1C, 0x01, 0x50, 0xAA, 0xE8, 0xFF, 0xEB, 0x15, 0xC4, 0x00, 0x41,
+    0x16, 0xFB, 0xFF, 0x69, 0xCC, 0x00, 0x12, 0xD6, 0x38, 0x06, 0xC2, 0x01, 0xE5, 0xFF, 0x82, 0xF8,
+    0xFF, 0x88, 0x07, 0x64, 0xFF, 0xFF, 0x50, 0x1C, 0x01, 0x90, 0xB6, 0x04, 0xF8, 0xFF, 0xD5, 0xC0,
+    0xFF, 0xFA, 0x0A, 0xF4, 0x00, 0x41, 0x20, 0xFF, 0xFF, 0x45, 0xFC, 0x00, 0x31, 0xDE, 0xFF, 0x8D,
+    0x08, 0x00, 0x31, 0x9C, 0xFF, 0xD5, 0x08, 0x00, 0x40, 0x5A, 0xFF, 0xFF, 0x1D, 0x08, 0x00, 0x43,
+    0x19, 0xFF, 0xFF, 0x64, 0x50, 0x00, 0x15, 0xAC, 0xC8, 0x09, 0xF0, 0x01, 0x16, 0xA1, 0xEB, 0xF7,
+    0xCC, 0x49, 0x00, 0x01, 0xC8, 0xFF, 0xDA, 0xB4, 0xFF, 0xFA, 0x27, 0x2F, 0xDA, 0x03, 0x40, 0xAE,
+    0xFF, 0x87, 0x4A, 0x68, 0x0B, 0x70, 0x76, 0xD2, 0x72, 0x2D, 0xFF, 0xFF, 0xB1, 0x22, 0x0A, 0x50,
+    0x02, 0xD0, 0xFF, 0xFF, 0xB6, 0x92, 0x08, 0x50, 0x26, 0xE8, 0xFF, 0xFF, 0xCA, 0x78, 0x16, 0x50,
+    0x23, 0xDB, 0xFF, 0xFF, 0xC9, 0x5A, 0x09, 0xF3, 0x1F, 0x16, 0xCC, 0xFF, 0xFF, 0x74, 0x02, 0x2A,
+    0x52, 0x00, 0x11, 0xE5, 0xFF, 0xD0, 0x44, 0xFF, 0xF5, 0x03, 0x00, 0x89, 0xFF, 0xED, 0x15, 0xFD,
+    0xFF, 0x43, 0x00, 0x88, 0xFF, 0xD1, 0x00, 0xA1, 0xFF, 0xEF, 0xA8, 0xF5, 0xFF, 0x67, 0x00, 0x09,
+    0x8B, 0xE4, 0xFE, 0xDC, 0x6D, 0x01, 0x07, 0x78, 0x00, 0x11, 0xED, 0xC4, 0x0C, 0xD3, 0xFC, 0x1C,
+    0x9A, 0xA4, 0xDE, 0xFF, 0xF5, 0xA4, 0xA4, 0x12, 0x00, 0x00, 0xA0, 0xEE, 0x0D, 0x0F, 0x08, 0x00,
+    0x43, 0x04, 0x0C, 0x03, 0xA1, 0x14, 0xFC, 0xFC, 0x5B, 0x00, 0x00, 0xC5, 0xFC, 0xA6, 0x14, 0xC4,
+    0x01, 0x3F, 0xC8, 0xFF, 0xA8, 0x09, 0x00, 0x2C, 0x11, 0x13, 0x09, 0x00, 0xF7, 0x17, 0xC9, 0xFF,
+    0xA6, 0x06, 0xFF, 0xFF, 0x63, 0x00, 0x00, 0xCF, 0xFF, 0x96, 0x00, 0xD6, 0xFF, 0x95, 0x00, 0x0D,
+    0xF5, 0xFF, 0x68, 0x00, 0x6D, 0xFF, 0xFE, 0xAE, 0xD3, 0xFF, 0xED, 0x14, 0x00, 0x02, 0x74, 0xDB,
+    0xFB, 0xF3, 0xBC, 0x32, 0xF8, 0x06, 0xF0, 0x1B, 0x81, 0xFC, 0xB1, 0x00, 0x00, 0x01, 0xEE, 0xFC,
+    0x4E, 0x51, 0xFF, 0xE2, 0x00, 0x00, 0x20, 0xFF, 0xFF, 0x1C, 0x1E, 0xFF, 0xFF, 0x13, 0x00, 0x4D,
+    0xFF, 0xE9, 0x01, 0x01, 0xEC, 0xFF, 0x42, 0x00, 0x7A, 0xFF, 0xB6, 0x00, 0x00, 0xB9, 0xFF, 0x71,
+    0x00, 0xA7, 0xC0, 0x0D, 0xF0, 0x01, 0x86, 0xFF, 0xA1, 0x00, 0xD4, 0xFF, 0x4F, 0x00, 0x00, 0x53,
+    0xFF, 0xD0, 0x07, 0xFC, 0xFF, 0x1C, 0x32, 0x00, 0x40, 0xFA, 0x35, 0xFF, 0xE9, 0xCC, 0x0B, 0x41,
+    0xED, 0xFF, 0x8B, 0xFF, 0xBE, 0x11, 0x31, 0xBA, 0xFF, 0xE5, 0xEC, 0x0D, 0x51, 0x00, 0x87, 0xFF,
+    0xFF, 0xFF, 0x4C, 0x0B, 0x30, 0x54, 0xFF, 0xFF, 0x2C, 0x00, 0x41, 0x00, 0x00, 0x21, 0xFF, 0x2C,
+    0x00, 0x00, 0x72, 0x00, 0x02, 0x2C, 0x00, 0x32, 0x00, 0x0C, 0x0C, 0x88, 0x00, 0xF0, 0x0E, 0x5E,
+    0xFC, 0xB9, 0x00, 0x00, 0xCE, 0xFB, 0x0B, 0x00, 0x7B, 0xFC, 0x90, 0x3B, 0xFF, 0xDB, 0x00, 0x03,
+    0xF8, 0xFF, 0x33, 0x00, 0x9C, 0xFF, 0x6E, 0x17, 0xFF, 0xFA, 0x02, 0x24, 0x39, 0x09, 0xF0, 0x15,
+    0xBC, 0xFF, 0x4A, 0x01, 0xF3, 0xFF, 0x1B, 0x4E, 0xFF, 0xFF, 0x88, 0x00, 0xDC, 0xFF, 0x26, 0x00,
+    0xCF, 0xFF, 0x3B, 0x77, 0xFF, 0xFC, 0xB2, 0x02, 0xFA, 0xFD, 0x06, 0x00, 0xAB, 0xFF, 0x5A, 0xA1,
+    0xFA, 0xC2, 0xDD, 0x1B, 0x4F, 0x0E, 0xF0, 0x07, 0x87, 0xFF, 0x7A, 0xCB, 0xD3, 0x94, 0xFE, 0x45,
+    0xFF, 0xBA, 0x00, 0x00, 0x63, 0xFF, 0x9B, 0xF4, 0xA8, 0x69, 0xFF, 0x8C, 0xFF, 0x96, 0xFD, 0x0B,
+    0x90, 0xD8, 0xFF, 0x7E, 0x3F, 0xFF, 0xD7, 0xFF, 0x72, 0x00, 0x3D, 0x09, 0x50, 0xFF, 0x53, 0x14,
+    0xFF, 0xFF, 0x35, 0x16, 0x20, 0x02, 0xF6, 0xC2, 0x11, 0x41, 0xEA, 0xFF, 0xFF, 0x2A, 0x91, 0x16,
+    0x60, 0xFA, 0x05, 0x00, 0xBF, 0xFF, 0xFE, 0x24, 0x03, 0x60, 0xAF, 0xFF, 0xD4, 0x00, 0x00, 0x95,
+    0x16, 0x01, 0x50, 0x00, 0x00, 0x8B, 0xFF, 0xA9, 0x6D, 0x0F, 0x43, 0xBE, 0x00, 0x00, 0x08, 0x38,
+    0x01, 0xF0, 0x00, 0x8B, 0xFC, 0xC9, 0x00, 0x00, 0x40, 0xFC, 0xE7, 0x06, 0x27, 0xFF, 0xFF, 0x35,
+    0x00, 0x9B, 0x4E, 0x07, 0x60, 0xBD, 0xFF, 0x9F, 0x07, 0xEF, 0xFF, 0xA8, 0x27, 0x50, 0xFF, 0xF7,
+    0x61, 0xFF, 0xCF, 0x70, 0x0D, 0x32, 0xE7, 0xFF, 0xF4, 0xCB, 0x12, 0x41, 0x83, 0xFF, 0xFF, 0xFA,
+    0x25, 0x19, 0x21, 0x2B, 0xFF, 0x7D, 0x0C, 0x41, 0x00, 0x00, 0x67, 0xFF, 0x0C, 0x17, 0x00, 0x89,
+    0x06, 0x20, 0xFF, 0xFA, 0x2F, 0x10, 0x40, 0x27, 0xFF, 0xF3, 0xE1, 0xA9, 0x0B, 0xF0, 0x0F, 0x00,
+    0x86, 0xFF, 0x9F, 0x78, 0xFF, 0xDF, 0x03, 0x00, 0x03, 0xE4, 0xFF, 0x43, 0x16, 0xF9, 0xFF, 0x4A,
+    0x00, 0x45, 0xFF, 0xE4, 0x03, 0x00, 0xA4, 0xFF, 0xB3, 0x00, 0xA5, 0xFF, 0x8A, 0xA9, 0x0B, 0x26,
+    0xFE, 0x1F, 0x88, 0x00, 0xF0, 0x09, 0xAD, 0xFC, 0xA4, 0x00, 0x00, 0x50, 0xFC, 0xF0, 0x08, 0x5E,
+    0xFF, 0xEF, 0x05, 0x00, 0x9B, 0xFF, 0xAA, 0x00, 0x11, 0xFB, 0xFF, 0x41, 0x01, 0xE5, 0x7D, 0x08,
+    0x70, 0xB8, 0xFF, 0x8F, 0x30, 0xFF, 0xF9, 0x0E, 0x90, 0x15, 0x40, 0xDE, 0x7B, 0xFF, 0xB4, 0x23,
+    0x03, 0x51, 0xFD, 0xFF, 0xE4, 0xFF, 0x62, 0x55, 0x13, 0x31, 0xFF, 0xFF, 0xFD, 0x91, 0x00, 0x42,
+    0x6D, 0xFF, 0xFF, 0xBE, 0x53, 0x11, 0x32, 0xFF, 0xFF, 0x71, 0x5B, 0x0D, 0x01, 0x4A, 0x02, 0x0F,
+    0x09, 0x00, 0x14, 0x04, 0xC4, 0x13, 0x11, 0x38, 0x47, 0x03, 0xD1, 0xCD, 0x24, 0xA4, 0xA4, 0xA4,
+    0xEF, 0xFF, 0xB2, 0x00, 0x00, 0x00, 0x11, 0xFA, 0x22, 0x00, 0x30, 0x61, 0xFF, 0xF7, 0x21, 0x00,
+    0x11, 0xB7, 0xF6, 0x00, 0x40, 0x13, 0xFB, 0xFF, 0x56, 0x0A, 0x16, 0x31, 0xFF, 0xF4, 0x0B, 0x28,
+    0x02, 0x00, 0xF7, 0x0F, 0x21, 0x15, 0xFC, 0xD2, 0x13, 0x30, 0x66, 0xFF, 0xF1, 0x75, 0x01, 0x32,
+    0xBC, 0xFF, 0xA1, 0xA7, 0x00, 0x11, 0x4A, 0x13, 0x11, 0x61, 0xFF, 0xA2, 0x9C, 0x9C, 0x82, 0x68,
+    0x63, 0x04, 0x10, 0xD4, 0x60, 0x14, 0x02, 0x48, 0x05, 0x10, 0x05, 0x6B, 0x00, 0x90, 0x14, 0x05,
+    0xFF, 0xFF, 0xA7, 0xA4, 0x0D, 0x05, 0xFF, 0x32, 0x0E, 0x02, 0x06, 0x00, 0x1F, 0x06, 0x06, 0x00,
+    0x04, 0x1F, 0x07, 0x06, 0x00, 0x04, 0x1F, 0x08, 0x06, 0x00, 0x01, 0x41, 0xA3, 0xA0, 0x0A, 0x08,
+    0xBA, 0x14, 0x06, 0xDC, 0x00, 0x31, 0x40, 0xFC, 0x5A, 0xEB, 0x00, 0x21, 0xF5, 0xA2, 0x0F, 0x00,
+    0x32, 0xB4, 0xE8, 0x02, 0x39, 0x01, 0x00, 0x54, 0x06, 0x41, 0x00, 0x26, 0xFF, 0x78, 0xD1, 0x02,
+    0x12, 0xDE, 0x46, 0x2F, 0x21, 0x97, 0xFB, 0x8E, 0x0F, 0x12, 0x50, 0xF9, 0x02, 0x31, 0x0E, 0xFB,
+    0x96, 0x16, 0x00, 0x21, 0xC1, 0xDE, 0xF6, 0x02, 0x20, 0x7A, 0xFF, 0xA3, 0x0B, 0x22, 0x00, 0x33,
+    0x05, 0x0D, 0x31, 0x02, 0xEA, 0xB4, 0x1D, 0x00, 0x20, 0xA4, 0xF5, 0xC2, 0x00, 0x03, 0x2C, 0x16,
+    0x80, 0x9E, 0xFC, 0xFC, 0xFC, 0x77, 0x67, 0xA4, 0xDB, 0x56, 0x00, 0x1F, 0x98, 0x05, 0x00, 0x2B,
+    0x81, 0x64, 0xA0, 0xD9, 0xFF, 0x78, 0xA0, 0xFF, 0xFF, 0xA1, 0x00, 0x24, 0x08, 0x08, 0x2C, 0x16,
+    0x31, 0x4D, 0xFC, 0xFC, 0x28, 0x15, 0x21, 0xBB, 0xFF, 0x83, 0x0D, 0x60, 0x29, 0xFF, 0xB9, 0xD2,
+    0xF9, 0x16, 0xEA, 0x02, 0xF1, 0x09, 0x5D, 0x76, 0xFF, 0x7D, 0x00, 0x0F, 0xF4, 0xF5, 0x0C, 0x1D,
+    0xFE, 0xE7, 0x06, 0x2C, 0x84, 0x61, 0x00, 0x00, 0x6E, 0x84, 0x21, 0x06, 0x07, 0x02, 0x98, 0x00,
+    0x11, 0xA0, 0x01, 0x00, 0x33, 0x0A, 0xFF, 0xFF, 0x1C, 0x01, 0x31, 0x05, 0x05, 0x04, 0x54, 0x28,
+    0xF0, 0x00, 0x04, 0xC8, 0xFC, 0x61, 0x00, 0x00, 0x2A, 0xF8, 0xB7, 0x00, 0x00, 0x00, 0x73, 0xFB,
+    0x12, 0x26, 0x16, 0x42, 0x01, 0x08, 0x08, 0x0A, 0xD4, 0x05, 0xE0, 0x24, 0xAF, 0xF1, 0xF1, 0xA7,
+    0x10, 0x00, 0x01, 0xCF, 0xFF, 0xC9, 0xE5, 0xFF, 0x8D, 0xFE, 0x03, 0xA1, 0x17, 0x70, 0xFF, 0xD3,
+    0x00, 0x14, 0x5C, 0x5C, 0x03, 0x70, 0x0E, 0x05, 0x21, 0x40, 0xBF, 0xB6, 0x13, 0xF4, 0x18, 0x7C,
+    0xFF, 0xD2, 0x87, 0xFF, 0xE0, 0x00, 0x22, 0xFF, 0xFD, 0x1E, 0x64, 0xFF, 0xE0, 0x00, 0x4F, 0xFF,
+    0xEF, 0x02, 0x6B, 0xFF, 0xE1, 0x00, 0x2A, 0xFF, 0xFF, 0xB7, 0xE4, 0xFF, 0xEB, 0x00, 0x00, 0x7D,
+    0xF3, 0xDB, 0x51, 0xFF, 0xFE, 0x05, 0x2C, 0x06, 0x41, 0x18, 0xFC, 0xFC, 0x3C, 0x08, 0x00, 0x2F,
+    0xFF, 0xFF, 0x08, 0x00, 0x05, 0x40, 0x88, 0xD4, 0xF0, 0x70, 0x08, 0x00, 0xD1, 0xDB, 0xC4, 0xFF,
+    0xFD, 0x1A, 0x18, 0xFF, 0xFF, 0x3D, 0x09, 0xFB, 0xFF, 0x56, 0x20, 0x00, 0x31, 0xED, 0xFF, 0x64,
+    0x08, 0x00, 0x1B, 0xEC, 0x08, 0x00, 0x30, 0xED, 0xFF, 0x63, 0x08, 0x00, 0xF3, 0x07, 0x07, 0xFB,
+    0xFF, 0x50, 0x18, 0xFF, 0xFF, 0xCF, 0xBB, 0xFF, 0xFA, 0x15, 0x18, 0xFF, 0xFF, 0x95, 0xE0, 0xF1,
+    0x68, 0x00, 0x07, 0x07, 0xD0, 0x00, 0xF1, 0x0D, 0x30, 0xC3, 0xF6, 0xED, 0xA4, 0x10, 0x03, 0xE0,
+    0xFF, 0xC8, 0xE3, 0xFF, 0x8C, 0x2F, 0xFF, 0xFF, 0x19, 0x64, 0xFF, 0xCB, 0x4A, 0xFF, 0xFF, 0x09,
+    0x44, 0xC4, 0xA3, 0x4C, 0x40, 0x02, 0x13, 0x00, 0x07, 0x00, 0x00, 0x15, 0x00, 0xF7, 0x09, 0x54,
+    0xF4, 0xCB, 0x30, 0xFF, 0xFF, 0x18, 0x65, 0xFF, 0xC9, 0x04, 0xE2, 0xFF, 0xC8, 0xE2, 0xFF, 0x89,
+    0x00, 0x34, 0xC8, 0xFA, 0xF0, 0xA3, 0x0E, 0xBC, 0x10, 0x61, 0x00, 0x00, 0x00, 0x2C, 0xFC, 0xFC,
+    0x14, 0x1F, 0x3E, 0x2C, 0xFF, 0xFF, 0x08, 0x00, 0xF0, 0x04, 0x4C, 0xE3, 0xE9, 0x9A, 0xFF, 0xFF,
+    0x28, 0x04, 0xE9, 0xFF, 0xD2, 0xCE, 0xFF, 0xFF, 0x28, 0x2F, 0xFF, 0xFF, 0x27, 0x18, 0x00, 0x40,
+    0x46, 0xFF, 0xFF, 0x11, 0x08, 0x00, 0x48, 0x48, 0xFF, 0xFF, 0x10, 0x08, 0x00, 0x13, 0x47, 0x18,
+    0x00, 0x40, 0x34, 0xFF, 0xFF, 0x22, 0x08, 0x00, 0x50, 0x06, 0xF4, 0xFF, 0xCC, 0xC5, 0x48, 0x00,
+    0x84, 0x5B, 0xE6, 0xED, 0x9C, 0xFF, 0xFF, 0x28, 0x08, 0xC8, 0x00, 0xF1, 0x03, 0x2D, 0xC1, 0xF6,
+    0xEE, 0x9F, 0x0B, 0x03, 0xDD, 0xFF, 0xC3, 0xDE, 0xFF, 0x83, 0x2E, 0xFF, 0xFF, 0x0F, 0x58, 0xC8,
+    0x00, 0x51, 0x9E, 0xBC, 0xFF, 0xE1, 0x4C, 0xE1, 0x01, 0x10, 0xE4, 0xC8, 0x00, 0xF4, 0x14, 0x04,
+    0x04, 0x04, 0x4A, 0xFF, 0xFF, 0x04, 0x2B, 0x88, 0x79, 0x30, 0xFF, 0xFF, 0x14, 0x60, 0xFF, 0xD5,
+    0x04, 0xE3, 0xFF, 0xCD, 0xE6, 0xFF, 0x8D, 0x00, 0x35, 0xC7, 0xF9, 0xEF, 0xA0, 0x0D, 0x00, 0x00,
+    0x05, 0x06, 0x9C, 0x13, 0xC1, 0xAE, 0xF5, 0xF0, 0x0F, 0x00, 0x6D, 0xFF, 0xFC, 0xB3, 0x0D, 0x00,
+    0x98, 0x4F, 0x04, 0x10, 0xA0, 0x2D, 0x11, 0xC2, 0xAE, 0xFF, 0xFF, 0xFF, 0xFC, 0x10, 0x71, 0xDE,
+    0xFF, 0xE4, 0xA4, 0x0B, 0x12, 0x00, 0x0F, 0x06, 0x00, 0x17, 0x00, 0xE0, 0x04, 0x16, 0xFD, 0xBA,
+    0x12, 0xF0, 0x0A, 0x0F, 0x00, 0x00, 0x2A, 0xBB, 0xF6, 0xE5, 0x64, 0x86, 0xD4, 0x01, 0x01, 0xD9,
+    0xFF, 0xC2, 0xE1, 0xFF, 0xDB, 0x68, 0x04, 0x28, 0xFF, 0xF7, 0x04, 0x57, 0x44, 0x04, 0x50, 0x42,
+    0xFF, 0xE6, 0x00, 0x44, 0x71, 0x05, 0x50, 0x2F, 0xFF, 0xF4, 0x04, 0x54, 0x58, 0x15, 0x50, 0x03,
+    0xD3, 0xFF, 0xBA, 0xDD, 0x79, 0x0C, 0xD1, 0x00, 0x7D, 0xF2, 0xF8, 0xF3, 0x9D, 0x08, 0x00, 0x00,
+    0x2C, 0xFE, 0x9B, 0x1B, 0x83, 0x12, 0xF0, 0x06, 0x2C, 0xFA, 0xFF, 0xFF, 0xFD, 0xDA, 0x73, 0x01,
+    0x00, 0x02, 0xA8, 0xE9, 0x9E, 0xB9, 0xF2, 0xFF, 0x43, 0x00, 0x66, 0xFF, 0x84, 0xE7, 0x14, 0xF7,
+    0x04, 0x6F, 0x00, 0x96, 0xFF, 0xEE, 0xAD, 0xA6, 0xE7, 0xFF, 0x44, 0x00, 0x20, 0xB0, 0xEC, 0xFF,
+    0xFD, 0xDA, 0x7C, 0x01, 0x68, 0x12, 0x52, 0x10, 0xFC, 0xFC, 0x3F, 0x00, 0x9F, 0x14, 0x1F, 0x40,
+    0x08, 0x00, 0x04, 0x70, 0x6F, 0xB8, 0xF6, 0xB3, 0x03, 0x10, 0xFF, 0xA0, 0x14, 0xA0, 0xFF, 0x3B,
+    0x10, 0xFF, 0xFF, 0x43, 0x09, 0xFF, 0xFF, 0x4C, 0x20, 0x00, 0x1F, 0x04, 0x08, 0x00, 0x20, 0x04,
+    0xA8, 0x1D, 0x85, 0x08, 0xFC, 0xFC, 0x4B, 0x06, 0xA4, 0xA4, 0x31, 0xF8, 0x12, 0x7F, 0xFC, 0xFC,
+    0x47, 0x08, 0xFF, 0xFF, 0x48, 0x04, 0x00, 0x0D, 0x42, 0x04, 0x05, 0x11, 0xFF, 0x40, 0x01, 0x97,
+    0xE1, 0xFC, 0x73, 0x00, 0x00, 0x93, 0xA4, 0x4B, 0x00, 0x01, 0x00, 0x30, 0xDD, 0xFC, 0x6F, 0xFA,
+    0x0B, 0x1F, 0x70, 0x05, 0x00, 0x16, 0xF6, 0x00, 0x04, 0xEE, 0xFF, 0x6D, 0x31, 0xD9, 0xFF, 0xFF,
+    0x37, 0x34, 0xF7, 0xEC, 0x7D, 0x01, 0x00, 0x80, 0x06, 0x53, 0x18, 0xFC, 0xFC, 0x38, 0x00, 0x75,
+    0x03, 0x0F, 0x09, 0x00, 0x0A, 0x40, 0x9F, 0xFC, 0xD9, 0x08, 0x09, 0x00, 0x10, 0x3F, 0xA2, 0x16,
+    0x71, 0x18, 0xFF, 0xFF, 0x3E, 0xD6, 0xFF, 0xB3, 0x1B, 0x00, 0x41, 0xB0, 0xFF, 0xF8, 0x22, 0x09,
+    0x00, 0x41, 0xFF, 0xFF, 0xEF, 0x09, 0x09, 0x00, 0x42, 0xB3, 0xE3, 0xFF, 0x5D, 0xCE, 0x03, 0x32,
+    0x89, 0xFF, 0xC3, 0x3F, 0x00, 0x10, 0x2E, 0xA0, 0x07, 0x01, 0x48, 0x00, 0x32, 0xD2, 0xFF, 0x8F,
+    0x09, 0x00, 0x40, 0x76, 0xFF, 0xEE, 0x08, 0x90, 0x1A, 0x04, 0xB8, 0x0A, 0x4F, 0x5B, 0xF8, 0xFF,
+    0x5C, 0x03, 0x00, 0x11, 0x00, 0x74, 0x08, 0x02, 0x08, 0x03, 0xF0, 0x09, 0x1C, 0xFC, 0xFC, 0x67,
+    0xD3, 0xF6, 0x90, 0x39, 0xC7, 0xF7, 0xA6, 0x03, 0x1C, 0xFF, 0xFF, 0xE9, 0xBB, 0xFF, 0xFF, 0xE9,
+    0xB4, 0xFF, 0xFF, 0x3C, 0x54, 0x16, 0xFF, 0x05, 0x03, 0xFC, 0xFF, 0x46, 0x00, 0xDE, 0xFF, 0x5B,
+    0x1C, 0xFF, 0xFF, 0x18, 0x00, 0xF8, 0xFF, 0x3C, 0x00, 0xD8, 0xFF, 0x5C, 0x0C, 0x00, 0x35, 0x25,
+    0x08, 0x08, 0x80, 0x00, 0xFF, 0x07, 0x6F, 0xB7, 0xF6, 0xA1, 0x01, 0x1C, 0xFF, 0xFF, 0xE3, 0xC4,
+    0xFF, 0xFF, 0x22, 0x1C, 0xFF, 0xFF, 0x3A, 0x21, 0xFF, 0xFF, 0x38, 0x1C, 0x04, 0x00, 0x24, 0x05,
+    0xE0, 0x03, 0x80, 0x2C, 0xBF, 0xF6, 0xED, 0x9D, 0x0D, 0x04, 0xDF, 0xA8, 0x04, 0xF5, 0x05, 0x96,
+    0x33, 0xFF, 0xFF, 0x13, 0x5D, 0xFF, 0xE7, 0x4B, 0xFF, 0xFF, 0x01, 0x4D, 0xFF, 0xFF, 0x4C, 0xFF,
+    0xFF, 0x00, 0x4C, 0x07, 0x00, 0xF0, 0x0D, 0x4B, 0xFF, 0xFF, 0x00, 0x4D, 0xFF, 0xFF, 0x34, 0xFF,
+    0xFF, 0x0F, 0x5D, 0xFF, 0xE8, 0x04, 0xE3, 0xFF, 0xC1, 0xDE, 0xFF, 0x9B, 0x00, 0x32, 0xC1, 0xF9,
+    0xEF, 0xA1, 0x10, 0xFC, 0x02, 0x32, 0x0D, 0x00, 0xFD, 0xA8, 0x00, 0xD0, 0x8D, 0xD8, 0xEF, 0x6D,
+    0x00, 0x1C, 0xFF, 0xFF, 0xDA, 0xC7, 0xFF, 0xFC, 0x17, 0x58, 0x1A, 0x40, 0x0B, 0xFD, 0xFF, 0x4F,
+    0x74, 0x00, 0x41, 0x00, 0xF1, 0xFF, 0x60, 0x08, 0x00, 0x1B, 0xF0, 0x08, 0x00, 0x31, 0xF1, 0xFF,
+    0x5F, 0x94, 0x00, 0xF3, 0x05, 0xFD, 0xFF, 0x4C, 0x1C, 0xFF, 0xFF, 0xCD, 0xBE, 0xFF, 0xF9, 0x12,
+    0x1C, 0xFF, 0xFF, 0x91, 0xE0, 0xEF, 0x65, 0x00, 0x1C, 0x19, 0x02, 0x0C, 0x08, 0x00, 0x04, 0x70,
+    0x00, 0xF0, 0x0D, 0x00, 0x48, 0xE1, 0xE9, 0x95, 0xFC, 0xFC, 0x30, 0x04, 0xE8, 0xFF, 0xD3, 0xCD,
+    0xFF, 0xFF, 0x30, 0x30, 0xFF, 0xFF, 0x27, 0x24, 0xFF, 0xFF, 0x30, 0x43, 0xFF, 0xFF, 0x11, 0x08,
+    0x00, 0x48, 0x44, 0xFF, 0xFF, 0x10, 0x08, 0x00, 0x04, 0x18, 0x00, 0x40, 0x30, 0xFF, 0xFF, 0x22,
+    0x08, 0x00, 0x50, 0x05, 0xF1, 0xFF, 0xCC, 0xC4, 0xF2, 0x1D, 0x40, 0x59, 0xE6, 0xED, 0x97, 0x08,
+    0x00, 0x02, 0x07, 0x19, 0x0D, 0x08, 0x00, 0x18, 0x06, 0x1C, 0x17, 0x60, 0x02, 0x14, 0xFC, 0xFC,
+    0x6B, 0xCE, 0x8F, 0x0B, 0xA1, 0xFB, 0xB8, 0x79, 0x14, 0xFF, 0xFF, 0x77, 0x00, 0x00, 0x14, 0xDC,
+    0x03, 0x0F, 0x06, 0x00, 0x11, 0x16, 0x00, 0x24, 0x06, 0xF1, 0x16, 0x54, 0xD4, 0xF7, 0xBB, 0x24,
+    0x00, 0x21, 0xFD, 0xFB, 0xB4, 0xFC, 0xCD, 0x01, 0x5F, 0xFF, 0xC6, 0x00, 0x8E, 0xD7, 0x15, 0x31,
+    0xFF, 0xFF, 0x73, 0x0A, 0x01, 0x00, 0x00, 0x93, 0xFF, 0xFF, 0x8B, 0x02, 0x00, 0x00, 0x02, 0x83,
+    0x9A, 0x18, 0xF1, 0x0B, 0x0C, 0x08, 0x63, 0xFF, 0xFF, 0x31, 0x67, 0xF5, 0x63, 0x00, 0xC7, 0xFF,
+    0x5B, 0x31, 0xFE, 0xF4, 0xAB, 0xFC, 0xFD, 0x20, 0x00, 0x5B, 0xD7, 0xFB, 0xD1, 0x57, 0x4C, 0x1D,
+    0x03, 0xD6, 0x17, 0x40, 0xB6, 0xFC, 0x9E, 0x00, 0xCB, 0x09, 0x14, 0xA0, 0x06, 0x00, 0x01, 0x56,
+    0x05, 0x78, 0x1C, 0x71, 0xE7, 0xFF, 0xDE, 0xA4, 0x12, 0x18, 0x00, 0x0F, 0x06, 0x00, 0x00, 0x11,
+    0xB4, 0x76, 0x09, 0xD4, 0x88, 0xFF, 0xFF, 0xDB, 0x32, 0x00, 0x17, 0xC6, 0xFC, 0xF5, 0x33, 0x00,
+    0x00, 0x7C, 0x02, 0xFF, 0x00, 0x2C, 0xFC, 0xFC, 0x24, 0x34, 0xFC, 0xFC, 0x1C, 0x2C, 0xFF, 0xFF,
+    0x24, 0x34, 0xFF, 0xFF, 0x08, 0x00, 0x19, 0xA0, 0x2A, 0x37, 0xFF, 0xFF, 0x1C, 0x19, 0xFF, 0xFF,
+    0xD0, 0xE7, 0xD6, 0x0B, 0x74, 0x9F, 0xFA, 0xC0, 0x67, 0xFF, 0xFF, 0x1C, 0x00, 0x01, 0xF0, 0x13,
+    0xAE, 0xFC, 0x8B, 0x00, 0xA3, 0xFC, 0x92, 0x80, 0xFF, 0xAF, 0x00, 0xC7, 0xFF, 0x63, 0x4E, 0xFF,
+    0xD2, 0x00, 0xE8, 0xFF, 0x33, 0x1D, 0xFF, 0xF4, 0x0C, 0xFF, 0xFB, 0x07, 0x01, 0xEC, 0xFF, 0x43,
+    0xFF, 0xD1, 0x7A, 0x08, 0x10, 0x88, 0x9F, 0x00, 0x50, 0x89, 0xFF, 0xCC, 0xFF, 0x6F, 0x55, 0x1B,
+    0x30, 0xFE, 0xFF, 0x3E, 0xFF, 0x0A, 0x10, 0xFF, 0x2E, 0x1B, 0x43, 0x02, 0xF3, 0xFF, 0xDC, 0xD0,
+    0x22, 0x01, 0x50, 0x00, 0xF0, 0x2C, 0x7F, 0xFC, 0x67, 0x00, 0xD6, 0xF9, 0x06, 0x3A, 0xFC, 0x96,
+    0x5B, 0xFF, 0x89, 0x07, 0xFC, 0xFF, 0x29, 0x5E, 0xFF, 0x71, 0x34, 0xFF, 0xAB, 0x2C, 0xFF, 0xFF,
+    0x50, 0x82, 0xFF, 0x49, 0x0E, 0xFF, 0xCC, 0x55, 0xFF, 0xFE, 0x76, 0xA6, 0xFF, 0x21, 0x00, 0xE7,
+    0xED, 0x7E, 0xF1, 0xCD, 0x9D, 0xCB, 0xF8, 0x03, 0x00, 0xC0, 0xFF, 0xB7, 0xC3, 0xA0, 0xC4, 0xF0,
+    0xD2, 0xB0, 0x15, 0x40, 0xF7, 0x94, 0x74, 0xF5, 0xF1, 0x1C, 0x80, 0x72, 0xFF, 0xFF, 0x65, 0x47,
+    0xFF, 0xFF, 0x83, 0x20, 0x1C, 0x60, 0xFF, 0x36, 0x1B, 0xFF, 0xFF, 0x5B, 0x03, 0x02, 0x65, 0xFE,
+    0x0A, 0x01, 0xEF, 0xFF, 0x34, 0xBC, 0x01, 0xF1, 0x05, 0x92, 0xFC, 0xB1, 0x00, 0x64, 0xFC, 0x99,
+    0x26, 0xFE, 0xFF, 0x26, 0xC8, 0xFF, 0x2F, 0x00, 0xB1, 0xFF, 0xBD, 0xFF, 0xC2, 0x36, 0x18, 0xF0,
+    0x1E, 0xFF, 0x55, 0x00, 0x00, 0x01, 0xD8, 0xFF, 0xE4, 0x05, 0x00, 0x00, 0x15, 0xF9, 0xFF, 0xE8,
+    0x08, 0x00, 0x00, 0x73, 0xFF, 0xFF, 0xFF, 0x62, 0x00, 0x01, 0xD9, 0xFF, 0x98, 0xFF, 0xD4, 0x01,
+    0x3F, 0xFF, 0xC2, 0x10, 0xF3, 0xFF, 0x48, 0xA5, 0xFF, 0x63, 0x00, 0x8E, 0xFF, 0xBB, 0x0C, 0x02,
+    0x02, 0xC8, 0x02, 0xF0, 0x18, 0xC3, 0xFC, 0x75, 0x00, 0x67, 0xFC, 0xD2, 0x89, 0xFF, 0xA5, 0x00,
+    0x90, 0xFF, 0x9E, 0x4B, 0xFF, 0xD3, 0x00, 0xB8, 0xFF, 0x66, 0x10, 0xFE, 0xFB, 0x07, 0xE0, 0xFF,
+    0x2F, 0x00, 0xCE, 0xFF, 0x3A, 0xFF, 0xF5, 0x04, 0x00, 0x8F, 0xFF, 0x8F, 0xD3, 0x12, 0x51, 0x51,
+    0xFF, 0xE4, 0xFF, 0x89, 0x4E, 0x02, 0x61, 0xFF, 0x51, 0x00, 0x00, 0x00, 0xD5, 0x2C, 0x12, 0x40,
+    0x00, 0x98, 0xFF, 0xE3, 0x98, 0x00, 0xF1, 0x02, 0x75, 0xFF, 0xAB, 0x00, 0x00, 0x0B, 0xB6, 0xF0,
+    0xFF, 0x52, 0x00, 0x00, 0x10, 0xFD, 0xD5, 0x74, 0x01, 0x20, 0x02, 0x05, 0xC8, 0x01, 0x91, 0xFC,
+    0xFC, 0xD5, 0x1D, 0xA4, 0xA4, 0xE3, 0xFF, 0xBE, 0x3E, 0x22, 0x10, 0x5B, 0x38, 0x0B, 0x00, 0x1A,
+    0x05, 0x10, 0xC6, 0x94, 0x0C, 0x40, 0x2E, 0xFF, 0xFF, 0x2B, 0xDC, 0x09, 0x50, 0xC4, 0x00, 0x00,
+    0x0C, 0xF2, 0x24, 0x10, 0x70, 0x5D, 0xFF, 0xFF, 0xA6, 0x9C, 0x7F, 0x70, 0x6E, 0x05, 0x14, 0xD0,
+    0x50, 0x0B, 0xF4, 0x08, 0x00, 0x00, 0x7D, 0xE8, 0xFC, 0x4B, 0x00, 0x17, 0xFF, 0xFF, 0xCC, 0x31,
+    0x00, 0x35, 0xFF, 0xFF, 0x1F, 0x00, 0x00, 0x38, 0xFF, 0xFF, 0x14, 0x06, 0x00, 0x11, 0x3A, 0x06,
+    0x00, 0x10, 0x4A, 0x1B, 0x0D, 0x20, 0x2A, 0xD4, 0xB5, 0x0C, 0xF0, 0x02, 0x44, 0xFF, 0xFC, 0x52,
+    0x00, 0x00, 0x02, 0x70, 0xFF, 0xE1, 0x00, 0x00, 0x00, 0x3E, 0xFF, 0xFF, 0x0B, 0xD4, 0x21, 0x2A,
+    0xFF, 0x14, 0x36, 0x00, 0xF0, 0x02, 0x32, 0xFF, 0xFF, 0x21, 0x00, 0x00, 0x13, 0xFE, 0xFF, 0xCA,
+    0x30, 0x00, 0x00, 0x76, 0xEB, 0xFF, 0x4C, 0xAC, 0x05, 0x02, 0x5C, 0x21, 0x53, 0xDA, 0xFC, 0x28,
+    0xDD, 0xFF, 0x03, 0x00, 0x17, 0xDE, 0x03, 0x00, 0x17, 0xDF, 0x03, 0x00, 0x1A, 0xE0, 0x03, 0x00,
+    0x05, 0xFC, 0x0B, 0x81, 0x43, 0xFC, 0xE9, 0x84, 0x00, 0x00, 0x2C, 0xC9, 0xF9, 0x13, 0x00, 0x47,
+    0x06, 0x10, 0x00, 0x4A, 0x21, 0x10, 0x44, 0x53, 0x1A, 0x06, 0x06, 0x00, 0x21, 0x02, 0xF6, 0x54,
+    0x0C, 0x80, 0xA3, 0xFF, 0xD7, 0x2F, 0x00, 0x00, 0x4D, 0xFA, 0x7C, 0x00, 0x40, 0xDC, 0xFF, 0x76,
+    0x02, 0x0F, 0x0C, 0x1A, 0x46, 0x2A, 0x00, 0x02, 0x3C, 0x00, 0x10, 0x1A, 0xF9, 0x12, 0x20, 0x2B,
+    0xC7, 0x75, 0x01, 0x42, 0x44, 0xFF, 0xED, 0x7D, 0x8C, 0x04, 0x12, 0x04, 0x52, 0x37, 0xF4, 0x08,
+    0x21, 0x8C, 0x63, 0x07, 0x00, 0x22, 0x00, 0x26, 0xEF, 0xFF, 0xFF, 0xE4, 0xB4, 0xFD, 0x2E, 0x06,
+    0x7A, 0x17, 0x53, 0xCB, 0xF5, 0x7A, 0x01, 0x14, 0x1B, 0x22, 0x06, 0x06, 0x1F, 0x19, 0xFF, 0x02,
+    0x25, 0x54, 0x54, 0x54, 0x54, 0x07, 0x70, 0x55, 0x3C, 0x3C, 0x9B, 0x14, 0x70, 0x20, 0x00, 0x00,
+    0x7C, 0x06, 0x00, 0x1F, 0x67, 0x9B, 0x8C, 0x8C, 0xC5, 0x14, 0x20, 0xB4, 0x25, 0x0F, 0x01, 0x00,
+    0x45, 0x3F, 0x23, 0x23, 0x23, 0x18, 0x00, 0x02, 0x3E, 0xFF, 0xFF, 0xFF, 0x3B, 0x00, 0x0F, 0x23,
+    0x00, 0xFF, 0xE6, 0x0F, 0x36, 0x00, 0x03, 0x08, 0x01, 0x00, 0x0F, 0x14, 0x00, 0x01, 0x0F, 0x23,
+    0x00, 0x33, 0x0F, 0x8E, 0x00, 0x12, 0x16, 0x04, 0x01, 0x00, 0x04, 0xD2, 0x00, 0x06, 0x13, 0x00,
+    0x1F, 0x01, 0xBC, 0x02, 0xFF, 0xCC, 0x0F, 0x01, 0x00, 0xFF, 0xFF, 0xA1, 0xF0, 0x29, 0x64, 0x65,
+    0x66, 0x61, 0x75, 0x6C, 0x74, 0x00, 0x28, 0x42, 0xFF, 0xFF, 0x18, 0xC6, 0x04, 0x21, 0xC7, 0x39,
+    0x10, 0x84, 0x9D, 0xC4, 0xFF, 0xFF, 0x04, 0x21, 0xEB, 0x5A, 0x10, 0x84, 0x08, 0x42, 0x04, 0x21,
+    0x10, 0x84, 0x14, 0xFD, 0x28, 0xFF, 0xFF, 0xFF, 0x1F, 0x04, 0x10, 0x84, 0x18, 0xC6, 0x1F, 0x04,
+    0xFF, 0xFF, 0x08, 0x42, 0x10, 0x84, 0x06, 0x00, 0x22, 0x18, 0xC6, 0x0A, 0x00, 0x00, 0x08, 0x00,
+    0xF8, 0x61, 0x54, 0x44, 0x00, 0x00, 0x74, 0x44, 0x00, 0x00, 0x78, 0x44, 0x00, 0x00, 0x98, 0x44,
+    0x00, 0x00, 0xB8, 0x44, 0x00, 0x00, 0xD8, 0x44, 0x00, 0x00, 0xF8, 0x44, 0x00, 0x00, 0x18, 0x45,
+    0x00, 0x00, 0x38, 0x45, 0x00, 0x00, 0x58, 0x45, 0x00, 0x00, 0x78, 0x45, 0x00, 0x00, 0x98, 0x45,
+    0x00, 0x00, 0xB8, 0x45, 0x00, 0x00, 0xBC, 0x45, 0x00, 0x00, 0xC0, 0x45, 0x00, 0x00, 0xC4, 0x45,
+    0x00, 0x00, 0xC8, 0x45, 0x00, 0x00, 0xCC, 0x45, 0x00, 0x00, 0xD0, 0x45, 0x00, 0x00, 0xD4, 0x45,
+    0x00, 0x00, 0xF4, 0x45, 0x00, 0x00, 0x14, 0x46, 0x00, 0x00, 0x34, 0x46, 0x00, 0x00, 0x38, 0x46,
+    0x00, 0x00, 0x3C, 0x46, 0x00, 0x00, 0x40, 0x46, 0x00, 0x00, 0x6C, 0x46, 0x00, 0x00, 0x98, 0x46,
+    0x00, 0x00, 0x21, 0x2F, 0x00, 0xF7, 0x14, 0x22, 0xC4, 0x46, 0x86, 0x23, 0x20, 0xCC, 0x46, 0x8A,
+    0x03, 0x0E, 0x1C, 0x43, 0x00, 0x64, 0x11, 0x13, 0xD0, 0x24, 0x00, 0x13, 0xDC, 0x24, 0x00, 0x1B,
+    0x04, 0x44, 0x00, 0x13, 0xE0, 0x20, 0x00, 0x13, 0xE8, 0x20, 0x00, 0x1B, 0x07, 0x20, 0x00, 0x13,
+    0xEC, 0x20, 0x00, 0x13, 0xF4, 0x20, 0x00, 0x0C, 0x84, 0x00, 0x13, 0xF8, 0x20, 0x00, 0x22, 0x00,
+    0x47, 0x20, 0x00, 0x0C, 0x80, 0x00, 0x22, 0x04, 0x47, 0x14, 0x00, 0x2F, 0x10, 0x47, 0x60, 0x00,
+    0x03, 0x13, 0x14, 0x20, 0x00, 0x2F, 0x1C, 0x47, 0x60, 0x00, 0x03, 0x13, 0x20, 0x20, 0x00, 0x1F,
+    0x28, 0x60, 0x00, 0x04, 0x13, 0x2C, 0x20, 0x00, 0x1F, 0x38, 0x60, 0x00, 0x04, 0x13, 0x3C, 0x20,
+    0x00, 0x1F, 0x44, 0x60, 0x00, 0x04, 0x13, 0x48, 0x20, 0x00, 0x17, 0x50, 0x60, 0x00, 0x13, 0x02,
+    0x5C, 0x00, 0x00, 0x74, 0x0A, 0x13, 0x06, 0x80, 0x3C, 0x2E, 0x09, 0x00, 0x3C, 0x00, 0x13, 0x54,
+    0x3C, 0x00, 0x13, 0x5C, 0x3C, 0x00, 0x1B, 0x05, 0x20, 0x00, 0x13, 0x60, 0x20, 0x00, 0x1F, 0x68,
+    0x7C, 0x00, 0x04, 0x13, 0x6C, 0x20, 0x00, 0x1B, 0x74, 0xDC, 0x00, 0x1F, 0x02, 0x10, 0x45, 0x00,
+    0x1B, 0x10, 0x3C, 0x00, 0x26, 0x78, 0x47, 0x10, 0x00, 0x0F, 0x2C, 0x00, 0x0D, 0x1F, 0x80, 0x2C,
+    0x00, 0x18, 0x17, 0x88, 0x2C, 0x00, 0xF2, 0x37, 0x90, 0x47, 0x00, 0x00, 0x94, 0x47, 0x00, 0x00,
+    0x98, 0x47, 0x00, 0x00, 0xA4, 0x47, 0x00, 0x00, 0xA8, 0x47, 0x00, 0x00, 0xAC, 0x47, 0x00, 0x00,
+    0xB0, 0x47, 0x00, 0x00, 0xBC, 0x47, 0x00, 0x00, 0xC0, 0x47, 0x00, 0x00, 0xC4, 0x47, 0x00, 0x00,
+    0xD0, 0x47, 0x00, 0x00, 0xD4, 0x47, 0x00, 0x00, 0xD8, 0x47, 0x00, 0x00, 0xE4, 0x47, 0x00, 0x00,
+    0xE8, 0x47, 0x00, 0x00, 0xEC, 0x47, 0x00, 0x00, 0xF8, 0x47, 0x00, 0x00, 0xFC, 0x47, 0x05, 0x47,
+    0xF1, 0x6F, 0x04, 0x48, 0x00, 0x00, 0x10, 0x48, 0x00, 0x00, 0x14, 0x48, 0x00, 0x00, 0x18, 0x48,
+    0x00, 0x00, 0x24, 0x48, 0x00, 0x00, 0x28, 0x48, 0x00, 0x00, 0x2C, 0x48, 0x00, 0x00, 0x38, 0x48,
+    0x00, 0x00, 0x3C, 0x48, 0x00, 0x00, 0x40, 0x48, 0x00, 0x00, 0x44, 0x48, 0x00, 0x00, 0x50, 0x48,
+    0x00, 0x00, 0x54, 0x48, 0x00, 0x00, 0x58, 0x48, 0x00, 0x00, 0x64, 0x48, 0x00, 0x00, 0x68, 0x48,
+    0x00, 0x00, 0x6C, 0x48, 0x00, 0x00, 0x78, 0x48, 0x00, 0x00, 0x7C, 0x48, 0x00, 0x00, 0x80, 0x48,
+    0x00, 0x00, 0x8C, 0x48, 0x00, 0x00, 0x90, 0x48, 0x00, 0x00, 0x94, 0x48, 0x00, 0x00, 0xA0, 0x48,
+    0x00, 0x00, 0xA4, 0x48, 0x00, 0x00, 0xA8, 0x48, 0x00, 0x00, 0xB4, 0x48, 0x00, 0x00, 0xD8, 0x48,
+    0x00, 0x00, 0xFC, 0x48, 0x00, 0x00, 0x20, 0x49, 0x00, 0x00, 0x44, 0x49, 0x00, 0x00, 0x68, 0x49,
+    0xDC, 0x00, 0x00, 0xE5, 0x16, 0x1B, 0xE0, 0x0B, 0x04, 0x2F, 0xE0, 0x00, 0x18, 0x00, 0x00, 0x2E,
+    0x01, 0x60, 0x14, 0x00, 0x1F, 0x03, 0x28, 0x00, 0x00, 0x1F, 0x04, 0x54, 0x00, 0x18, 0x1F, 0x05,
+    0x40, 0x00, 0x2C, 0x1F, 0x06, 0x40, 0x00, 0x14, 0x1F, 0x07, 0x54, 0x00, 0x01, 0x0F, 0xD0, 0x00,
+    0x00, 0x1F, 0x08, 0x3C, 0x00, 0x02, 0x11, 0xFE, 0x46, 0x04, 0x9F, 0x5F, 0x00, 0x62, 0x00, 0x22,
+    0x01, 0x4C, 0x00, 0x11, 0xB8, 0x3F, 0x06, 0x03, 0xBC, 0x0C, 0x21, 0x00, 0x23, 0x68, 0x45, 0x0E,
+    0xC8, 0x40, 0x1F, 0xFC, 0x48, 0x00, 0x10, 0x11, 0xFB, 0x24, 0x00, 0x3F, 0xBD, 0x01, 0xED, 0x48,
+    0x00, 0x08, 0x1F, 0xFA, 0x48, 0x00, 0x10, 0x13, 0xF9, 0x48, 0x00, 0x0F, 0x90, 0x00, 0x07, 0xF0,
+    0x02, 0xB0, 0x49, 0x00, 0x00, 0xC0, 0x49, 0x00, 0x00, 0xD0, 0x49, 0x00, 0x00, 0xE0, 0x49, 0x00,
+    0x00, 0xF0, 0xD0, 0x48, 0xDE, 0x4A, 0x00, 0x00, 0x10, 0x4A, 0x00, 0x00, 0x20, 0x4A, 0x00, 0x00,
+    0x30, 0x4A, 0x34, 0x00, 0x1B, 0x01, 0x10, 0x00, 0x04, 0xD8, 0x29, 0x2A, 0x40, 0x4A, 0x10, 0x00,
+    0x1B, 0x50, 0x10, 0x00, 0x1B, 0x88, 0x10, 0x00, 0x1B, 0x8C, 0x10, 0x00, 0x1B, 0xC8, 0x10, 0x00,
+    0x2A, 0x00, 0x4B, 0x10, 0x00, 0x13, 0x04, 0x10, 0x00, 0xB0, 0x48, 0x65, 0x6C, 0x6C, 0x6F, 0x2C,
+    0x20, 0x77, 0x6F, 0x72, 0x6C, 0xE7, 0x44, 0xF0, 0x27, 0x00, 0x54, 0x6F, 0x75, 0x63, 0x68, 0x20,
+    0x74, 0x6F, 0x70, 0x2D, 0x6C, 0x65, 0x66, 0x74, 0x20, 0x63, 0x72, 0x6F, 0x73, 0x73, 0x20, 0x69,
+    0x6E, 0x20, 0x74, 0x68, 0x65, 0x20, 0x63, 0x65, 0x6E, 0x74, 0x65, 0x72, 0x20, 0x75, 0x6E, 0x74,
+    0x69, 0x6C, 0x20, 0x63, 0x68, 0x61, 0x6E, 0x67, 0x65, 0x20, 0x63, 0x6F, 0x6C, 0x6F, 0x72, 0xE4,
+    0x1C, 0x05, 0x3C, 0x00, 0xBF, 0x62, 0x6F, 0x74, 0x74, 0x6F, 0x6D, 0x2D, 0x72, 0x69, 0x67, 0x68,
+    0x40, 0x00, 0x18, 0x06, 0x78, 0x00, 0x0F, 0x39, 0x00, 0x1B, 0xF0, 0x01, 0x59, 0x65, 0x73, 0x00,
+    0x53, 0x74, 0x61, 0x72, 0x74, 0x20, 0x61, 0x67, 0x61, 0x69, 0x6E, 0x00
+};
+
+} // namespace gui
+} // namespace eez
diff --git a/Src/gui/document.h b/Src/gui/document.h
new file mode 100644
index 0000000..2313162
--- /dev/null
+++ b/Src/gui/document.h
@@ -0,0 +1,180 @@
+#pragma once
+
+#include <eez/gui/data.h>
+#include <eez/gui/widget.h>
+
+namespace eez {
+namespace gui {
+
+enum DataEnum {
+    DATA_ID_NONE = 0,
+    DATA_ID_ALERT_MESSAGE = 1,
+    DATA_ID_TOUCH_CALIBRATION_POINT = 2,
+    DATA_ID_KEYPAD_TEXT = 3,
+    DATA_ID_KEYPAD_EDIT_UNIT = 4,
+    DATA_ID_KEYPAD_SIGN_ENABLED = 5,
+    DATA_ID_KEYPAD_UNIT_ENABLED = 6,
+    DATA_ID_KEYPAD_DOT_ENABLED = 7,
+    DATA_ID_KEYPAD_OPTION1_ENABLED = 8,
+    DATA_ID_KEYPAD_OPTION1_TEXT = 9,
+    DATA_ID_KEYPAD_OPTION2_ENABLED = 10,
+    DATA_ID_KEYPAD_OPTION2_TEXT = 11,
+    DATA_ID_KEYPAD_OPTION3_ENABLED = 12,
+    DATA_ID_KEYPAD_OPTION3_TEXT = 13,
+    DATA_ID_KEYPAD_MODE = 14,
+    DATA_ID_KEYPAD_OK_ENABLED = 15
+};
+
+void data_none(DataOperationEnum operation, const WidgetCursor &cursor, Value &value);
+void data_alert_message(DataOperationEnum operation, const WidgetCursor &cursor, Value &value);
+void data_touch_calibration_point(DataOperationEnum operation, const WidgetCursor &cursor, Value &value);
+void data_keypad_text(DataOperationEnum operation, const WidgetCursor &cursor, Value &value);
+void data_keypad_edit_unit(DataOperationEnum operation, const WidgetCursor &cursor, Value &value);
+void data_keypad_sign_enabled(DataOperationEnum operation, const WidgetCursor &cursor, Value &value);
+void data_keypad_unit_enabled(DataOperationEnum operation, const WidgetCursor &cursor, Value &value);
+void data_keypad_dot_enabled(DataOperationEnum operation, const WidgetCursor &cursor, Value &value);
+void data_keypad_option1_enabled(DataOperationEnum operation, const WidgetCursor &cursor, Value &value);
+void data_keypad_option1_text(DataOperationEnum operation, const WidgetCursor &cursor, Value &value);
+void data_keypad_option2_enabled(DataOperationEnum operation, const WidgetCursor &cursor, Value &value);
+void data_keypad_option2_text(DataOperationEnum operation, const WidgetCursor &cursor, Value &value);
+void data_keypad_option3_enabled(DataOperationEnum operation, const WidgetCursor &cursor, Value &value);
+void data_keypad_option3_text(DataOperationEnum operation, const WidgetCursor &cursor, Value &value);
+void data_keypad_mode(DataOperationEnum operation, const WidgetCursor &cursor, Value &value);
+void data_keypad_ok_enabled(DataOperationEnum operation, const WidgetCursor &cursor, Value &value);
+
+typedef void (*DataOperationsFunction)(DataOperationEnum operation, const WidgetCursor &widgetCursor, Value &value);
+
+extern DataOperationsFunction g_dataOperationsFunctions[];
+
+enum ActionsEnum {
+    ACTION_ID_NONE = 0,
+    ACTION_ID_YES = 1,
+    ACTION_ID_NO = 2,
+    ACTION_ID_CANCEL = 3,
+    ACTION_ID_EDIT = 4,
+    ACTION_ID_DRAG_OVERLAY = 5,
+    ACTION_ID_SCROLL = 6,
+    ACTION_ID_KEYPAD_KEY = 7,
+    ACTION_ID_KEYPAD_BACK = 8,
+    ACTION_ID_KEYPAD_UNIT = 9,
+    ACTION_ID_KEYPAD_OPTION1 = 10,
+    ACTION_ID_KEYPAD_OPTION2 = 11,
+    ACTION_ID_KEYPAD_OPTION3 = 12,
+    ACTION_ID_KEYPAD_SIGN = 13,
+    ACTION_ID_KEYPAD_OK = 14,
+    ACTION_ID_KEYPAD_CANCEL = 15,
+    ACTION_ID_TOGGLE_KEYPAD_MODE = 16,
+    ACTION_ID_KEYPAD_SPACE = 17
+};
+
+void action_yes();
+void action_no();
+void action_cancel();
+void action_edit();
+void action_drag_overlay();
+void action_scroll();
+void action_keypad_key();
+void action_keypad_back();
+void action_keypad_unit();
+void action_keypad_option1();
+void action_keypad_option2();
+void action_keypad_option3();
+void action_keypad_sign();
+void action_keypad_ok();
+void action_keypad_cancel();
+void action_toggle_keypad_mode();
+void action_keypad_space();
+
+extern ActionExecFunc g_actionExecFunctions[];
+
+enum FontsEnum {
+    FONT_ID_NONE = 0,
+    FONT_ID_SHADOW = 1,
+    FONT_ID_MEDIUM = 2,
+    FONT_ID_GUI_ICONS = 3
+};
+
+enum BitmapsEnum {
+    BITMAP_ID_NONE = 0
+};
+
+enum StylesEnum {
+    STYLE_ID_NONE = 0,
+    STYLE_ID_DEFAULT = 1,
+    STYLE_ID_INFO_ALERT = 2,
+    STYLE_ID_ERROR_ALERT = 3,
+    STYLE_ID_ERROR_ALERT_BUTTON = 4,
+    STYLE_ID_SELECT_ENUM_ITEM_POPUP_CONTAINER = 5,
+    STYLE_ID_SELECT_ENUM_ITEM_POPUP_CONTAINER_S = 6,
+    STYLE_ID_SELECT_ENUM_ITEM_POPUP_ITEM = 7,
+    STYLE_ID_SELECT_ENUM_ITEM_POPUP_ITEM_S = 8,
+    STYLE_ID_SELECT_ENUM_ITEM_POPUP_DISABLED_ITEM = 9,
+    STYLE_ID_SELECT_ENUM_ITEM_POPUP_DISABLED_ITEM_S = 10,
+    STYLE_ID_MENU_WITH_BUTTONS_MESSAGE = 11,
+    STYLE_ID_MENU_WITH_BUTTONS_CONTAINER = 12,
+    STYLE_ID_MENU_WITH_BUTTONS_BUTTON = 13,
+    STYLE_ID_FPS_GRAPH = 14,
+    STYLE_ID_BACKGROUND = 15,
+    STYLE_ID_TOUCH_CALIBRATION = 16,
+    STYLE_ID_NOTE_M = 17,
+    STYLE_ID_TOUCH_CALIBRATION_POINT = 18,
+    STYLE_ID_BUTTON = 19
+};
+
+enum ThemesEnum {
+    THEME_ID_DEFAULT = 0
+};
+
+enum ColorsEnum {
+    COLOR_ID_TRANSPARENT = 65535,
+    COLOR_ID_BACKGROUND = 0,
+    COLOR_ID_BACKDROP = 1,
+    COLOR_ID_TEXT = 2,
+    COLOR_ID_TEXT_INACTIVE = 3,
+    COLOR_ID_DARK_TEXT = 4,
+    COLOR_ID_BORDER = 5,
+    COLOR_ID_ACTIVE_BACKGROUND = 6,
+    COLOR_ID_BUTTON_TEXT = 7,
+    COLOR_ID_BUTTON_BACKGROUND = 8,
+    COLOR_ID_BUTTON_ACTIVE_BACKGROUND = 9,
+    COLOR_ID_BUTTON_BORDER = 10,
+    COLOR_ID_BUTTON_DISABLED_TEXT = 11,
+    COLOR_ID_BUTTON_DISABLED_BACKGROUND = 12,
+    COLOR_ID_BUTTON_DISABLED_BORDER = 13,
+    COLOR_ID_ERROR = 14,
+    COLOR_ID_NOTE = 15,
+    COLOR_ID_SWITCH_WIDGET_COLOR = 16,
+    COLOR_ID_SWITCH_WIDGET_BACKGROUND_ON = 17,
+    COLOR_ID_SWITCH_WIDGET_BACKGROUND_OFF = 18,
+    COLOR_ID_SWITCH_WIDGET_BORDER = 19,
+    COLOR_ID_SLIDER_WIDGET_COLOR = 20,
+    COLOR_ID_SLIDER_WIDGET_BACKGROUND = 21,
+    COLOR_ID_DROP_DOWN_LIST_COLOR = 22,
+    COLOR_ID_DROP_DOWN_LIST_COLOR_DISABLED = 23,
+    COLOR_ID_DROP_DOWN_LIST_BACKGROUND = 24,
+    COLOR_ID_DROP_DOWN_LIST_BORDER = 25,
+    COLOR_ID_DROP_DOWN_LIST_ACTIVE_BACKGROUND = 26,
+    COLOR_ID_TEXT_INPUT_COLOR = 27,
+    COLOR_ID_TEXT_INPUT_COLOR_DISABLED = 28,
+    COLOR_ID_TEXT_INPUT_BACKGROUND = 29,
+    COLOR_ID_TEXT_INPUT_ACTIVE_BACKGROUND = 30,
+    COLOR_ID_TEXT_INPUT_BORDER = 31,
+	COLOR_ID_CUSTOM_UNDEFINED = 32,
+	COLOR_ID_CUSTOM_000000 = 33,
+	COLOR_ID_CUSTOM_00FF1E = 34,
+	COLOR_ID_CUSTOM_FFFFFF = 35,
+	COLOR_ID_CUSTOM_00FF00 = 36
+};
+
+enum PagesEnum {
+    PAGE_ID_NONE = 0,
+    PAGE_ID_MAIN = 1,
+    PAGE_ID_TOUCH_CALIBRATION = 2,
+    PAGE_ID_TOUCH_CALIBRATION_YES_NO = 3,
+    PAGE_ID_NUMERIC_KEYPAD = 4
+};
+
+extern const uint8_t assets[9804];
+
+} // namespace gui
+} // namespace eez
diff --git a/USB_HOST/App/usb_host.c b/USB_HOST/App/usb_host.c
new file mode 100644
index 0000000..7fec99c
--- /dev/null
+++ b/USB_HOST/App/usb_host.c
@@ -0,0 +1,128 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file            : usb_host.c
+  * @version         : v1.0_Cube
+  * @brief           : This file implements the USB Host
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2022 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+
+#include "usb_host.h"
+#include "usbh_core.h"
+#include "usbh_cdc.h"
+
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* USER CODE BEGIN PV */
+/* Private variables ---------------------------------------------------------*/
+
+/* USER CODE END PV */
+
+/* USER CODE BEGIN PFP */
+/* Private function prototypes -----------------------------------------------*/
+
+/* USER CODE END PFP */
+
+/* USB Host core handle declaration */
+USBH_HandleTypeDef hUsbHostFS;
+ApplicationTypeDef Appli_state = APPLICATION_IDLE;
+
+/*
+ * -- Insert your variables declaration here --
+ */
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/*
+ * user callback declaration
+ */
+static void USBH_UserProcess(USBH_HandleTypeDef *phost, uint8_t id);
+
+/*
+ * -- Insert your external function declaration here --
+ */
+/* USER CODE BEGIN 1 */
+
+/* USER CODE END 1 */
+
+/**
+  * Init USB host library, add supported class and start the library
+  * @retval None
+  */
+void MX_USB_HOST_Init(void)
+{
+  /* USER CODE BEGIN USB_HOST_Init_PreTreatment */
+
+  /* USER CODE END USB_HOST_Init_PreTreatment */
+
+  /* Init host Library, add supported class and start the library. */
+  if (USBH_Init(&hUsbHostFS, USBH_UserProcess, HOST_FS) != USBH_OK)
+  {
+    Error_Handler();
+  }
+  if (USBH_RegisterClass(&hUsbHostFS, USBH_CDC_CLASS) != USBH_OK)
+  {
+    Error_Handler();
+  }
+  if (USBH_Start(&hUsbHostFS) != USBH_OK)
+  {
+    Error_Handler();
+  }
+  /* USER CODE BEGIN USB_HOST_Init_PostTreatment */
+
+  /* USER CODE END USB_HOST_Init_PostTreatment */
+}
+
+/*
+ * user callback definition
+ */
+static void USBH_UserProcess  (USBH_HandleTypeDef *phost, uint8_t id)
+{
+  /* USER CODE BEGIN CALL_BACK_1 */
+  switch(id)
+  {
+  case HOST_USER_SELECT_CONFIGURATION:
+  break;
+
+  case HOST_USER_DISCONNECTION:
+  Appli_state = APPLICATION_DISCONNECT;
+  break;
+
+  case HOST_USER_CLASS_ACTIVE:
+  Appli_state = APPLICATION_READY;
+  break;
+
+  case HOST_USER_CONNECTION:
+  Appli_state = APPLICATION_START;
+  break;
+
+  default:
+  break;
+  }
+  /* USER CODE END CALL_BACK_1 */
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
diff --git a/USB_HOST/App/usb_host.h b/USB_HOST/App/usb_host.h
new file mode 100644
index 0000000..3fb9623
--- /dev/null
+++ b/USB_HOST/App/usb_host.h
@@ -0,0 +1,90 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file           : usb_host.h
+  * @version        : v1.0_Cube
+  * @brief          : Header for usb_host.c file.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2022 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __USB_HOST__H__
+#define __USB_HOST__H__
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx.h"
+#include "stm32f4xx_hal.h"
+
+/* USER CODE BEGIN INCLUDE */
+
+/* USER CODE END INCLUDE */
+
+/** @addtogroup USBH_OTG_DRIVER
+  * @{
+  */
+
+/** @defgroup USBH_HOST USBH_HOST
+  * @brief Host file for Usb otg low level driver.
+  * @{
+  */
+
+/** @defgroup USBH_HOST_Exported_Variables USBH_HOST_Exported_Variables
+  * @brief Public variables.
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** Status of the application. */
+typedef enum {
+  APPLICATION_IDLE = 0,
+  APPLICATION_START,
+  APPLICATION_READY,
+  APPLICATION_DISCONNECT
+}ApplicationTypeDef;
+
+/** @defgroup USBH_HOST_Exported_FunctionsPrototype USBH_HOST_Exported_FunctionsPrototype
+  * @brief Declaration of public functions for Usb host.
+  * @{
+  */
+
+/* Exported functions -------------------------------------------------------*/
+
+/** @brief USB Host initialization function. */
+void MX_USB_HOST_Init(void);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __USB_HOST__H__ */
+
diff --git a/USB_HOST/Target/usbh_conf.c b/USB_HOST/Target/usbh_conf.c
new file mode 100644
index 0000000..bab92b5
--- /dev/null
+++ b/USB_HOST/Target/usbh_conf.c
@@ -0,0 +1,548 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file           : Target/usbh_conf.c
+  * @version        : v1.0_Cube
+  * @brief          : This file implements the board support package for the USB host library
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2022 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "usbh_core.h"
+#include "usbh_platform.h"
+
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+
+/* USER CODE BEGIN PV */
+/* Private variables ---------------------------------------------------------*/
+
+/* USER CODE END PV */
+
+HCD_HandleTypeDef hhcd_USB_OTG_FS;
+void Error_Handler(void);
+
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/* USER CODE BEGIN PFP */
+/* Private function prototypes -----------------------------------------------*/
+USBH_StatusTypeDef USBH_Get_USB_Status(HAL_StatusTypeDef hal_status);
+
+/* USER CODE END PFP */
+
+/* Private functions ---------------------------------------------------------*/
+
+/* USER CODE BEGIN 1 */
+
+/* USER CODE END 1 */
+
+/*******************************************************************************
+                       LL Driver Callbacks (HCD -> USB Host Library)
+*******************************************************************************/
+/* MSP Init */
+
+void HAL_HCD_MspInit(HCD_HandleTypeDef* hcdHandle)
+{
+  GPIO_InitTypeDef GPIO_InitStruct = {0};
+  if(hcdHandle->Instance==USB_OTG_FS)
+  {
+  /* USER CODE BEGIN USB_OTG_FS_MspInit 0 */
+
+  /* USER CODE END USB_OTG_FS_MspInit 0 */
+
+    __HAL_RCC_GPIOA_CLK_ENABLE();
+    /**USB_OTG_FS GPIO Configuration
+    PA12     ------> USB_OTG_FS_DP
+    PA11     ------> USB_OTG_FS_DM
+    PA10     ------> USB_OTG_FS_ID
+    PA9     ------> USB_OTG_FS_VBUS
+    */
+    GPIO_InitStruct.Pin = USB_FS1_P_Pin|USB_FS1_N_Pin|USB_FS1_ID_Pin;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+    GPIO_InitStruct.Alternate = GPIO_AF10_OTG_FS;
+    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+
+    GPIO_InitStruct.Pin = VBUS_FS1_Pin;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+    HAL_GPIO_Init(VBUS_FS1_GPIO_Port, &GPIO_InitStruct);
+
+    /* Peripheral clock enable */
+    __HAL_RCC_USB_OTG_FS_CLK_ENABLE();
+
+    /* Peripheral interrupt init */
+    HAL_NVIC_SetPriority(OTG_FS_IRQn, 5, 0);
+    HAL_NVIC_EnableIRQ(OTG_FS_IRQn);
+  /* USER CODE BEGIN USB_OTG_FS_MspInit 1 */
+
+  /* USER CODE END USB_OTG_FS_MspInit 1 */
+  }
+}
+
+void HAL_HCD_MspDeInit(HCD_HandleTypeDef* hcdHandle)
+{
+  if(hcdHandle->Instance==USB_OTG_FS)
+  {
+  /* USER CODE BEGIN USB_OTG_FS_MspDeInit 0 */
+
+  /* USER CODE END USB_OTG_FS_MspDeInit 0 */
+    /* Peripheral clock disable */
+    __HAL_RCC_USB_OTG_FS_CLK_DISABLE();
+
+    /**USB_OTG_FS GPIO Configuration
+    PA12     ------> USB_OTG_FS_DP
+    PA11     ------> USB_OTG_FS_DM
+    PA10     ------> USB_OTG_FS_ID
+    PA9     ------> USB_OTG_FS_VBUS
+    */
+    HAL_GPIO_DeInit(GPIOA, USB_FS1_P_Pin|USB_FS1_N_Pin|USB_FS1_ID_Pin|VBUS_FS1_Pin);
+
+    /* Peripheral interrupt Deinit*/
+    HAL_NVIC_DisableIRQ(OTG_FS_IRQn);
+
+  /* USER CODE BEGIN USB_OTG_FS_MspDeInit 1 */
+
+  /* USER CODE END USB_OTG_FS_MspDeInit 1 */
+  }
+}
+
+/**
+  * @brief  SOF callback.
+  * @param  hhcd: HCD handle
+  * @retval None
+  */
+void HAL_HCD_SOF_Callback(HCD_HandleTypeDef *hhcd)
+{
+  USBH_LL_IncTimer(hhcd->pData);
+}
+
+/**
+  * @brief  SOF callback.
+  * @param  hhcd: HCD handle
+  * @retval None
+  */
+void HAL_HCD_Connect_Callback(HCD_HandleTypeDef *hhcd)
+{
+  USBH_LL_Connect(hhcd->pData);
+}
+
+/**
+  * @brief  SOF callback.
+  * @param  hhcd: HCD handle
+  * @retval None
+  */
+void HAL_HCD_Disconnect_Callback(HCD_HandleTypeDef *hhcd)
+{
+  USBH_LL_Disconnect(hhcd->pData);
+}
+
+/**
+  * @brief  Notify URB state change callback.
+  * @param  hhcd: HCD handle
+  * @param  chnum: channel number
+  * @param  urb_state: state
+  * @retval None
+  */
+void HAL_HCD_HC_NotifyURBChange_Callback(HCD_HandleTypeDef *hhcd, uint8_t chnum, HCD_URBStateTypeDef urb_state)
+{
+  /* To be used with OS to sync URB state with the global state machine */
+#if (USBH_USE_OS == 1)
+  USBH_LL_NotifyURBChange(hhcd->pData);
+#endif
+}
+/**
+* @brief  Port Port Enabled callback.
+  * @param  hhcd: HCD handle
+  * @retval None
+  */
+void HAL_HCD_PortEnabled_Callback(HCD_HandleTypeDef *hhcd)
+{
+  USBH_LL_PortEnabled(hhcd->pData);
+}
+
+/**
+  * @brief  Port Port Disabled callback.
+  * @param  hhcd: HCD handle
+  * @retval None
+  */
+void HAL_HCD_PortDisabled_Callback(HCD_HandleTypeDef *hhcd)
+{
+  USBH_LL_PortDisabled(hhcd->pData);
+}
+
+/*******************************************************************************
+                       LL Driver Interface (USB Host Library --> HCD)
+*******************************************************************************/
+
+/**
+  * @brief  Initialize the low level portion of the host driver.
+  * @param  phost: Host handle
+  * @retval USBH status
+  */
+USBH_StatusTypeDef USBH_LL_Init(USBH_HandleTypeDef *phost)
+{
+  /* Init USB_IP */
+  if (phost->id == HOST_FS) {
+  /* Link the driver to the stack. */
+  hhcd_USB_OTG_FS.pData = phost;
+  phost->pData = &hhcd_USB_OTG_FS;
+
+  hhcd_USB_OTG_FS.Instance = USB_OTG_FS;
+  hhcd_USB_OTG_FS.Init.Host_channels = 8;
+  hhcd_USB_OTG_FS.Init.speed = HCD_SPEED_FULL;
+  hhcd_USB_OTG_FS.Init.dma_enable = DISABLE;
+  hhcd_USB_OTG_FS.Init.phy_itface = HCD_PHY_EMBEDDED;
+  hhcd_USB_OTG_FS.Init.Sof_enable = DISABLE;
+  if (HAL_HCD_Init(&hhcd_USB_OTG_FS) != HAL_OK)
+  {
+    Error_Handler( );
+  }
+
+  USBH_LL_SetTimer(phost, HAL_HCD_GetCurrentFrame(&hhcd_USB_OTG_FS));
+  }
+  return USBH_OK;
+}
+
+/**
+  * @brief  De-Initialize the low level portion of the host driver.
+  * @param  phost: Host handle
+  * @retval USBH status
+  */
+USBH_StatusTypeDef USBH_LL_DeInit(USBH_HandleTypeDef *phost)
+{
+  HAL_StatusTypeDef hal_status = HAL_OK;
+  USBH_StatusTypeDef usb_status = USBH_OK;
+
+  hal_status = HAL_HCD_DeInit(phost->pData);
+
+  usb_status = USBH_Get_USB_Status(hal_status);
+
+  return usb_status;
+}
+
+/**
+  * @brief  Start the low level portion of the host driver.
+  * @param  phost: Host handle
+  * @retval USBH status
+  */
+USBH_StatusTypeDef USBH_LL_Start(USBH_HandleTypeDef *phost)
+{
+  HAL_StatusTypeDef hal_status = HAL_OK;
+  USBH_StatusTypeDef usb_status = USBH_OK;
+
+  hal_status = HAL_HCD_Start(phost->pData);
+
+  usb_status = USBH_Get_USB_Status(hal_status);
+
+  return usb_status;
+}
+
+/**
+  * @brief  Stop the low level portion of the host driver.
+  * @param  phost: Host handle
+  * @retval USBH status
+  */
+USBH_StatusTypeDef USBH_LL_Stop(USBH_HandleTypeDef *phost)
+{
+  HAL_StatusTypeDef hal_status = HAL_OK;
+  USBH_StatusTypeDef usb_status = USBH_OK;
+
+  hal_status = HAL_HCD_Stop(phost->pData);
+
+  usb_status = USBH_Get_USB_Status(hal_status);
+
+  return usb_status;
+}
+
+/**
+  * @brief  Return the USB host speed from the low level driver.
+  * @param  phost: Host handle
+  * @retval USBH speeds
+  */
+USBH_SpeedTypeDef USBH_LL_GetSpeed(USBH_HandleTypeDef *phost)
+{
+  USBH_SpeedTypeDef speed = USBH_SPEED_FULL;
+
+  switch (HAL_HCD_GetCurrentSpeed(phost->pData))
+  {
+  case 0 :
+    speed = USBH_SPEED_HIGH;
+    break;
+
+  case 1 :
+    speed = USBH_SPEED_FULL;
+    break;
+
+  case 2 :
+    speed = USBH_SPEED_LOW;
+    break;
+
+  default:
+   speed = USBH_SPEED_FULL;
+    break;
+  }
+  return  speed;
+}
+
+/**
+  * @brief  Reset the Host port of the low level driver.
+  * @param  phost: Host handle
+  * @retval USBH status
+  */
+USBH_StatusTypeDef USBH_LL_ResetPort(USBH_HandleTypeDef *phost)
+{
+  HAL_StatusTypeDef hal_status = HAL_OK;
+  USBH_StatusTypeDef usb_status = USBH_OK;
+
+  hal_status = HAL_HCD_ResetPort(phost->pData);
+
+  usb_status = USBH_Get_USB_Status(hal_status);
+
+  return usb_status;
+}
+
+/**
+  * @brief  Return the last transferred packet size.
+  * @param  phost: Host handle
+  * @param  pipe: Pipe index
+  * @retval Packet size
+  */
+uint32_t USBH_LL_GetLastXferSize(USBH_HandleTypeDef *phost, uint8_t pipe)
+{
+  return HAL_HCD_HC_GetXferCount(phost->pData, pipe);
+}
+
+/**
+  * @brief  Open a pipe of the low level driver.
+  * @param  phost: Host handle
+  * @param  pipe_num: Pipe index
+  * @param  epnum: Endpoint number
+  * @param  dev_address: Device USB address
+  * @param  speed: Device Speed
+  * @param  ep_type: Endpoint type
+  * @param  mps: Endpoint max packet size
+  * @retval USBH status
+  */
+USBH_StatusTypeDef USBH_LL_OpenPipe(USBH_HandleTypeDef *phost, uint8_t pipe_num, uint8_t epnum,
+                                    uint8_t dev_address, uint8_t speed, uint8_t ep_type, uint16_t mps)
+{
+  HAL_StatusTypeDef hal_status = HAL_OK;
+  USBH_StatusTypeDef usb_status = USBH_OK;
+
+  hal_status = HAL_HCD_HC_Init(phost->pData, pipe_num, epnum,
+                               dev_address, speed, ep_type, mps);
+
+  usb_status = USBH_Get_USB_Status(hal_status);
+
+  return usb_status;
+}
+
+/**
+  * @brief  Close a pipe of the low level driver.
+  * @param  phost: Host handle
+  * @param  pipe: Pipe index
+  * @retval USBH status
+  */
+USBH_StatusTypeDef USBH_LL_ClosePipe(USBH_HandleTypeDef *phost, uint8_t pipe)
+{
+  HAL_StatusTypeDef hal_status = HAL_OK;
+  USBH_StatusTypeDef usb_status = USBH_OK;
+
+  hal_status = HAL_HCD_HC_Halt(phost->pData, pipe);
+
+  usb_status = USBH_Get_USB_Status(hal_status);
+
+  return usb_status;
+}
+
+/**
+  * @brief  Submit a new URB to the low level driver.
+  * @param  phost: Host handle
+  * @param  pipe: Pipe index
+  *         This parameter can be a value from 1 to 15
+  * @param  direction : Channel number
+  *          This parameter can be one of the these values:
+  *           0 : Output
+  *           1 : Input
+  * @param  ep_type : Endpoint Type
+  *          This parameter can be one of the these values:
+  *            @arg EP_TYPE_CTRL: Control type
+  *            @arg EP_TYPE_ISOC: Isochrounous type
+  *            @arg EP_TYPE_BULK: Bulk type
+  *            @arg EP_TYPE_INTR: Interrupt type
+  * @param  token : Endpoint Type
+  *          This parameter can be one of the these values:
+  *            @arg 0: PID_SETUP
+  *            @arg 1: PID_DATA
+  * @param  pbuff : pointer to URB data
+  * @param  length : Length of URB data
+  * @param  do_ping : activate do ping protocol (for high speed only)
+  *          This parameter can be one of the these values:
+  *           0 : do ping inactive
+  *           1 : do ping active
+  * @retval Status
+  */
+USBH_StatusTypeDef USBH_LL_SubmitURB(USBH_HandleTypeDef *phost, uint8_t pipe, uint8_t direction,
+                                     uint8_t ep_type, uint8_t token, uint8_t *pbuff, uint16_t length,
+                                     uint8_t do_ping)
+{
+  HAL_StatusTypeDef hal_status = HAL_OK;
+  USBH_StatusTypeDef usb_status = USBH_OK;
+
+  hal_status = HAL_HCD_HC_SubmitRequest(phost->pData, pipe, direction ,
+                                        ep_type, token, pbuff, length,
+                                        do_ping);
+  usb_status =  USBH_Get_USB_Status(hal_status);
+
+  return usb_status;
+}
+
+/**
+  * @brief  Get a URB state from the low level driver.
+  * @param  phost: Host handle
+  * @param  pipe: Pipe index
+  *         This parameter can be a value from 1 to 15
+  * @retval URB state
+  *          This parameter can be one of the these values:
+  *            @arg URB_IDLE
+  *            @arg URB_DONE
+  *            @arg URB_NOTREADY
+  *            @arg URB_NYET
+  *            @arg URB_ERROR
+  *            @arg URB_STALL
+  */
+USBH_URBStateTypeDef USBH_LL_GetURBState(USBH_HandleTypeDef *phost, uint8_t pipe)
+{
+  return (USBH_URBStateTypeDef)HAL_HCD_HC_GetURBState (phost->pData, pipe);
+}
+
+/**
+  * @brief  Drive VBUS.
+  * @param  phost: Host handle
+  * @param  state : VBUS state
+  *          This parameter can be one of the these values:
+  *           0 : VBUS Inactive
+  *           1 : VBUS Active
+  * @retval Status
+  */
+USBH_StatusTypeDef USBH_LL_DriverVBUS(USBH_HandleTypeDef *phost, uint8_t state)
+{
+  if (phost->id == HOST_FS) {
+    MX_DriverVbusFS(state);
+  }
+
+  /* USER CODE BEGIN 0 */
+
+  /* USER CODE END 0*/
+
+  HAL_Delay(200);
+  return USBH_OK;
+}
+
+/**
+  * @brief  Set toggle for a pipe.
+  * @param  phost: Host handle
+  * @param  pipe: Pipe index
+  * @param  toggle: toggle (0/1)
+  * @retval Status
+  */
+USBH_StatusTypeDef USBH_LL_SetToggle(USBH_HandleTypeDef *phost, uint8_t pipe, uint8_t toggle)
+{
+  HCD_HandleTypeDef *pHandle;
+  pHandle = phost->pData;
+
+  if(pHandle->hc[pipe].ep_is_in)
+  {
+    pHandle->hc[pipe].toggle_in = toggle;
+  }
+  else
+  {
+    pHandle->hc[pipe].toggle_out = toggle;
+  }
+
+  return USBH_OK;
+}
+
+/**
+  * @brief  Return the current toggle of a pipe.
+  * @param  phost: Host handle
+  * @param  pipe: Pipe index
+  * @retval toggle (0/1)
+  */
+uint8_t USBH_LL_GetToggle(USBH_HandleTypeDef *phost, uint8_t pipe)
+{
+  uint8_t toggle = 0;
+  HCD_HandleTypeDef *pHandle;
+  pHandle = phost->pData;
+
+  if(pHandle->hc[pipe].ep_is_in)
+  {
+    toggle = pHandle->hc[pipe].toggle_in;
+  }
+  else
+  {
+    toggle = pHandle->hc[pipe].toggle_out;
+  }
+  return toggle;
+}
+
+/**
+  * @brief  Delay routine for the USB Host Library
+  * @param  Delay: Delay in ms
+  * @retval None
+  */
+void USBH_Delay(uint32_t Delay)
+{
+  HAL_Delay(Delay);
+}
+
+/**
+  * @brief  Returns the USB status depending on the HAL status:
+  * @param  hal_status: HAL status
+  * @retval USB status
+  */
+USBH_StatusTypeDef USBH_Get_USB_Status(HAL_StatusTypeDef hal_status)
+{
+  USBH_StatusTypeDef usb_status = USBH_OK;
+
+  switch (hal_status)
+  {
+    case HAL_OK :
+      usb_status = USBH_OK;
+    break;
+    case HAL_ERROR :
+      usb_status = USBH_FAIL;
+    break;
+    case HAL_BUSY :
+      usb_status = USBH_BUSY;
+    break;
+    case HAL_TIMEOUT :
+      usb_status = USBH_FAIL;
+    break;
+    default :
+      usb_status = USBH_FAIL;
+    break;
+  }
+  return usb_status;
+}
+
diff --git a/USB_HOST/Target/usbh_conf.h b/USB_HOST/Target/usbh_conf.h
new file mode 100644
index 0000000..fd73fe5
--- /dev/null
+++ b/USB_HOST/Target/usbh_conf.h
@@ -0,0 +1,194 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file           : Target/usbh_conf.h
+  * @version        : v1.0_Cube
+  * @brief          : Header for usbh_conf.c file.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2022 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __USBH_CONF__H__
+#define __USBH_CONF__H__
+#ifdef __cplusplus
+ extern "C" {
+#endif
+/* Includes ------------------------------------------------------------------*/
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include "main.h"
+
+#include "stm32f4xx.h"
+#include "stm32f4xx_hal.h"
+
+/* USER CODE BEGIN INCLUDE */
+
+/* USER CODE END INCLUDE */
+
+/** @addtogroup STM32_USB_HOST_LIBRARY
+  * @{
+  */
+
+/** @defgroup USBH_CONF
+  * @brief usb host low level driver configuration file
+  * @{
+  */
+
+/** @defgroup USBH_CONF_Exported_Variables USBH_CONF_Exported_Variables
+  * @brief Public variables.
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup USBH_CONF_Exported_Defines USBH_CONF_Exported_Defines
+  * @brief Defines for configuration of the Usb host.
+  * @{
+  */
+
+/*----------   -----------*/
+#define USBH_MAX_NUM_ENDPOINTS      2U
+
+/*----------   -----------*/
+#define USBH_MAX_NUM_INTERFACES      2U
+
+/*----------   -----------*/
+#define USBH_MAX_NUM_CONFIGURATION      1U
+
+/*----------   -----------*/
+#define USBH_KEEP_CFG_DESCRIPTOR      1U
+
+/*----------   -----------*/
+#define USBH_MAX_NUM_SUPPORTED_CLASS      1U
+
+/*----------   -----------*/
+#define USBH_MAX_SIZE_CONFIGURATION      256U
+
+/*----------   -----------*/
+#define USBH_MAX_DATA_BUFFER      512U
+
+/*----------   -----------*/
+#define USBH_DEBUG_LEVEL      0U
+
+/*----------   -----------*/
+#define USBH_USE_OS      1U
+
+/****************************************/
+/* #define for FS and HS identification */
+#define HOST_HS 		0
+#define HOST_FS 		1
+
+#if (USBH_USE_OS == 1)
+  #include "cmsis_os.h"
+  #define USBH_PROCESS_PRIO          osPriorityNormal
+  #define USBH_PROCESS_STACK_SIZE    ((uint16_t)128)
+#endif /* (USBH_USE_OS == 1) */
+
+/**
+  * @}
+  */
+
+/** @defgroup USBH_CONF_Exported_Macros USBH_CONF_Exported_Macros
+  * @brief Aliases.
+  * @{
+  */
+
+/* Memory management macros */
+
+/** Alias for memory allocation. */
+#define USBH_malloc         malloc
+
+/** Alias for memory release. */
+#define USBH_free           free
+
+/** Alias for memory set. */
+#define USBH_memset         memset
+
+/** Alias for memory copy. */
+#define USBH_memcpy         memcpy
+
+/* DEBUG macros */
+
+#if (USBH_DEBUG_LEVEL > 0U)
+#define  USBH_UsrLog(...)   do { \
+                            printf(__VA_ARGS__); \
+                            printf("\n"); \
+} while (0)
+#else
+#define USBH_UsrLog(...) do {} while (0)
+#endif
+
+#if (USBH_DEBUG_LEVEL > 1U)
+
+#define  USBH_ErrLog(...) do { \
+                            printf("ERROR: ") ; \
+                            printf(__VA_ARGS__); \
+                            printf("\n"); \
+} while (0)
+#else
+#define USBH_ErrLog(...) do {} while (0)
+#endif
+
+#if (USBH_DEBUG_LEVEL > 2U)
+#define  USBH_DbgLog(...)   do { \
+                            printf("DEBUG : ") ; \
+                            printf(__VA_ARGS__); \
+                            printf("\n"); \
+} while (0)
+#else
+#define USBH_DbgLog(...) do {} while (0)
+#endif
+
+/**
+  * @}
+  */
+
+/** @defgroup USBH_CONF_Exported_Types USBH_CONF_Exported_Types
+  * @brief Types.
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup USBH_CONF_Exported_FunctionsPrototype USBH_CONF_Exported_FunctionsPrototype
+  * @brief Declaration of public functions for Usb host.
+  * @{
+  */
+
+/* Exported functions -------------------------------------------------------*/
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __USBH_CONF__H__ */
+
diff --git a/USB_HOST/Target/usbh_platform.c b/USB_HOST/Target/usbh_platform.c
new file mode 100644
index 0000000..e76be14
--- /dev/null
+++ b/USB_HOST/Target/usbh_platform.c
@@ -0,0 +1,52 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file           : usbh_platform.c
+
+  * @brief          : This file implements the USB platform
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2022 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "usbh_platform.h"
+
+/* USER CODE BEGIN INCLUDE */
+
+/* USER CODE END INCLUDE */
+
+/**
+  * @brief  Drive VBUS.
+  * @param  state : VBUS state
+  *          This parameter can be one of the these values:
+  *           - 1 : VBUS Active
+  *           - 0 : VBUS Inactive
+  */
+void MX_DriverVbusFS(uint8_t state)
+{
+  uint8_t data = state;
+  /* USER CODE BEGIN PREPARE_GPIO_DATA_VBUS_FS */
+  if(state == 0)
+  {
+    /* Drive high Charge pump */
+    data = GPIO_PIN_RESET;
+  }
+  else
+  {
+    /* Drive low Charge pump */
+    data = GPIO_PIN_SET;
+  }
+  /* USER CODE END PREPARE_GPIO_DATA_VBUS_FS */
+  HAL_GPIO_WritePin(GPIOB,GPIO_PIN_2,(GPIO_PinState)data);
+}
+
diff --git a/USB_HOST/Target/usbh_platform.h b/USB_HOST/Target/usbh_platform.h
new file mode 100644
index 0000000..2f2be07
--- /dev/null
+++ b/USB_HOST/Target/usbh_platform.h
@@ -0,0 +1,42 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file           : usbh_platform.h
+  * @brief          : Header for usbh_platform.c file.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2022 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __USBH_PLATFORM_H__
+#define __USBH_PLATFORM_H__
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "usb_host.h"
+
+/* USER CODE BEGIN INCLUDE */
+
+/* USER CODE END INCLUDE */
+
+void MX_DriverVbusFS(uint8_t state);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __USBH_PLATFORM_H__ */
+
diff --git a/Utilities/CPU/Release_Notes.html b/Utilities/CPU/Release_Notes.html
new file mode 100644
index 0000000..a4b24b9
--- /dev/null
+++ b/Utilities/CPU/Release_Notes.html
@@ -0,0 +1,197 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html xmlns:v="urn:schemas-microsoft-com:vml" xmlns:o="urn:schemas-microsoft-com:office:office" xmlns:w="urn:schemas-microsoft-com:office:word" xmlns="http://www.w3.org/TR/REC-html40"><head>
+
+
+
+
+
+
+
+
+
+
+
+  
+  <meta http-equiv="Content-Type" content="text/html; charset=ISO-8859-1">
+
+  
+  <link rel="File-List" href="Library_files/filelist.xml">
+
+  
+  <link rel="Edit-Time-Data" href="Library_files/editdata.mso"><!--[if !mso]> <style> v\:* {behavior:url(#default#VML);} o\:* {behavior:url(#default#VML);} w\:* {behavior:url(#default#VML);} .shape {behavior:url(#default#VML);} </style> <![endif]--><title>Release Notes for STM32Cube CPU Utilities Driver</title><!--[if gte mso 9]><xml> <o:DocumentProperties> <o:Author>STMicroelectronics</o:Author> <o:LastAuthor>STMicroelectronics</o:LastAuthor> <o:Revision>37</o:Revision> <o:TotalTime>136</o:TotalTime> <o:Created>2009-02-27T19:26:00Z</o:Created> <o:LastSaved>2009-03-01T17:56:00Z</o:LastSaved> <o:Pages>1</o:Pages> <o:Words>522</o:Words> <o:Characters>2977</o:Characters> <o:Company>STMicroelectronics</o:Company> <o:Lines>24</o:Lines> <o:Paragraphs>6</o:Paragraphs> <o:CharactersWithSpaces>3493</o:CharactersWithSpaces> <o:Version>11.6568</o:Version> </o:DocumentProperties> </xml><![endif]--><!--[if gte mso 9]><xml> <w:WordDocument> <w:Zoom>110</w:Zoom> <w:ValidateAgainstSchemas/> <w:SaveIfXMLInvalid>false</w:SaveIfXMLInvalid> <w:IgnoreMixedContent>false</w:IgnoreMixedContent> <w:AlwaysShowPlaceholderText>false</w:AlwaysShowPlaceholderText> <w:BrowserLevel>MicrosoftInternetExplorer4</w:BrowserLevel> </w:WordDocument> </xml><![endif]--><!--[if gte mso 9]><xml> <w:LatentStyles DefLockedState="false" LatentStyleCount="156"> </w:LatentStyles> </xml><![endif]-->
+
+
+  
+
+  
+
+  
+  <style>
+<!--
+/* Style Definitions */
+p.MsoNormal, li.MsoNormal, div.MsoNormal
+{mso-style-parent:"";
+margin:0in;
+margin-bottom:.0001pt;
+mso-pagination:widow-orphan;
+font-size:12.0pt;
+font-family:"Times New Roman";
+mso-fareast-font-family:"Times New Roman";}
+h2
+{mso-style-next:Normal;
+margin-top:12.0pt;
+margin-right:0in;
+margin-bottom:3.0pt;
+margin-left:0in;
+mso-pagination:widow-orphan;
+page-break-after:avoid;
+mso-outline-level:2;
+font-size:14.0pt;
+font-family:Arial;
+font-weight:bold;
+font-style:italic;}
+a:link, span.MsoHyperlink
+{color:blue;
+text-decoration:underline;
+text-underline:single;}
+a:visited, span.MsoHyperlinkFollowed
+{color:blue;
+text-decoration:underline;
+text-underline:single;}
+p
+{mso-margin-top-alt:auto;
+margin-right:0in;
+mso-margin-bottom-alt:auto;
+margin-left:0in;
+mso-pagination:widow-orphan;
+font-size:12.0pt;
+font-family:"Times New Roman";
+mso-fareast-font-family:"Times New Roman";}
+@page Section1
+{size:8.5in 11.0in;
+margin:1.0in 1.25in 1.0in 1.25in;
+mso-header-margin:.5in;
+mso-footer-margin:.5in;
+mso-paper-source:0;}
+div.Section1
+{page:Section1;}
+-->
+  </style><!--[if gte mso 10]> <style> /* Style Definitions */ table.MsoNormalTable {mso-style-name:"Table Normal"; mso-tstyle-rowband-size:0; mso-tstyle-colband-size:0; mso-style-noshow:yes; mso-style-parent:""; mso-padding-alt:0in 5.4pt 0in 5.4pt; mso-para-margin:0in; mso-para-margin-bottom:.0001pt; mso-pagination:widow-orphan; font-size:10.0pt; font-family:"Times New Roman"; mso-ansi-language:#0400; mso-fareast-language:#0400; mso-bidi-language:#0400;} </style> <![endif]--><!--[if gte mso 9]><xml> <o:shapedefaults v:ext="edit" spidmax="5122"/> </xml><![endif]--><!--[if gte mso 9]><xml> <o:shapelayout v:ext="edit"> <o:idmap v:ext="edit" data="1"/> </o:shapelayout></xml><![endif]-->
+  <meta content="MCD Application Team" name="author"></head><body link="blue" vlink="blue">
+<div class="Section1">
+<p class="MsoNormal"><span style="font-family: Arial;"><o:p><br>
+</o:p></span></p>
+<div align="center">
+<table class="MsoNormalTable" style="width: 675pt;" border="0" cellpadding="0" cellspacing="0" width="900">
+  <tbody>
+    <tr>
+      <td style="padding: 0cm;" valign="top">
+      <table class="MsoNormalTable" style="width: 675pt;" border="0" cellpadding="0" cellspacing="0" width="900">
+        <tbody>
+          <tr>
+            <td style="vertical-align: top;">
+            <p class="MsoNormal"><span style="font-size: 8pt; font-family: Arial; color: blue;"><a href="../../Release_Notes.html">Back to Release page</a><o:p></o:p></span></p>
+            </td>
+          </tr>
+          <tr style="">
+            <td style="padding: 1.5pt;">
+            <h1 style="margin-bottom: 18pt; text-align: center;" align="center"><span style="font-size: 20pt; font-family: Verdana; color: rgb(51, 102, 255);">Release
+Notes for STM32Cube CPU Utilities Driver</span><span style="font-size: 20pt; font-family: Verdana;"><o:p></o:p></span></h1>
+            <p class="MsoNormal" style="text-align: center;" align="center"><span style="font-size: 10pt; font-family: Arial; color: black;">Copyright
+2014 STMicroelectronics</span><span style="color: black;"><u1:p></u1:p><o:p></o:p></span></p>
+            <p class="MsoNormal" style="text-align: center;" align="center"><span style="font-size: 10pt; font-family: Arial; color: black;"><img alt="" id="_x0000_i1025" src="../../_htmresc/st_logo.png" style="border: 0px solid ; width: 86px; height: 65px;"></span><span style="font-size: 10pt;"><o:p></o:p></span></p>
+            </td>
+          </tr>
+        </tbody>
+      </table>
+      <p class="MsoNormal"><span style="font-family: Arial; display: none;"><o:p>&nbsp;</o:p></span></p>
+      <table class="MsoNormalTable" style="width: 675pt;" border="0" cellpadding="0" width="900">
+        <tbody>
+          <tr style="">
+            <td style="padding: 0cm;" valign="top">
+            <span style="font-family: &quot;Times New Roman&quot;;"></span><h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial;"><a name="History"></a><span style="font-size: 12pt; color: white;">Update History</span></h2>
+            <h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; margin-right: 500pt; width: 180px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.1.0 / 20-November-2014 <o:p></o:p></span></h3>
+
+
+
+
+            
+            
+            
+            <p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
+Changes<o:p></o:p></span></u></b></p>
+
+
+            <span style="font-size: 10pt; font-family: Verdana;"></span>
+
+
+            
+            <span style="font-size: 10pt; font-family: Verdana;"></span>
+            <p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;"><o:p></o:p></span></u></b></p>
+
+
+
+            
+            
+            <ul style="list-style-type: square;">
+              <li><span style="font-size: 10pt; font-family: Verdana;">Update some APIs to be in line with FreeRTOS V8.1.2</span></li>
+            </ul>
+
+            <h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; margin-right: 500pt; width: 180px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.0.0 / 18-February-2014 <o:p></o:p></span></h3>
+
+
+
+            
+            
+            <p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
+Changes<o:p></o:p></span></u></b></p>
+
+            <span style="font-size: 10pt; font-family: Verdana;"></span>
+
+
+            
+            <span style="font-size: 10pt; font-family: Verdana;"></span><p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;"><o:p></o:p></span></u></b></p>
+
+
+            
+            <ul style="list-style-type: square;">
+              <li><span style="font-size: 10pt; font-family: Verdana;">First official release</span><span style="font-size: 10pt; font-family: Verdana;"><br>
+                </span></li>
+            </ul><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic; font-weight: bold;"></span></span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic; font-weight: bold;"></span></span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic; font-weight: bold;"></span></span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic; font-weight: bold;"></span></span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic; font-weight: bold;"></span></span><span style="font-size: 10pt; font-family: Verdana;"></span><h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial;"><a name="License"></a><span style="font-size: 12pt; color: white;">License<o:p></o:p></span><br></h2>
+            <div style="text-align: justify;"><font size="-1"><span style="font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are
+met:</span><br>
+            </font>
+            <ol><li><font size="-1"><span style="font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.</span><span style="font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"></span></font></li><li><font size="-1"><span style="font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Redistributions
+in binary form must reproduce the above copyright notice, this list of
+conditions and the following disclaimer in </span><span style="font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">the documentation and/or other materials provided with the distribution.</span><span style="font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"></span></font></li><li><font size="-1"><span style="font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived </span><br>
+                </font>
+              </li></ol>
+            <font size="-1"><span style="font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; from this software without specific prior written permission.</span><br>
+            <span style="font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"></span><br>
+            <span style="font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED</span><span style="font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"> WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A </span><span style="font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY </span><span style="font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, </span><span style="font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER</span><span style="font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"> CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR </span><span style="font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.</span></font>
+            
+            </div>
+<p class="MsoNormal"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;; color: black;"><o:p></o:p></span></p>
+<b><span style="font-size: 10pt; font-family: Verdana; color: black;"></span></b>
+            
+            <div class="MsoNormal" style="text-align: center;" align="center"><span style="color: black;">
+            <hr align="center" size="2" width="100%"></span></div>
+            <p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt; text-align: center;" align="center"><span style="font-size: 10pt; font-family: Verdana; color: black;">For
+complete documentation on </span><span style="font-size: 10pt; font-family: Verdana;">STM32<span style="color: black;">&nbsp;Microcontrollers
+visit </span><u><span style="color: blue;"><a href="http://www.st.com/internet/mcu/class/1734.jsp" target="_blank">www.st.com/STM32</a></span></u></span><span style="font-size: 10pt; font-family: Verdana;"><a target="_blank" href="http://www.st.com/internet/mcu/family/141.jsp"><u><span style="color: blue;"></span></u></a></span><span style="font-size: 10pt; font-family: Verdana;"><u><span style="color: blue;"></span></u></span><span style="color: black;"><o:p></o:p></span></p>
+            </td>
+          </tr>
+        </tbody>
+      </table>
+      <p class="MsoNormal"><span style="font-size: 10pt;"><o:p></o:p></span></p>
+      </td>
+    </tr>
+  </tbody>
+</table>
+</div>
+<p class="MsoNormal"><o:p>&nbsp;</o:p></p>
+</div>
+
+</body></html>
\ No newline at end of file
diff --git a/Utilities/CPU/cpu_utils.c b/Utilities/CPU/cpu_utils.c
new file mode 100644
index 0000000..a2e109e
--- /dev/null
+++ b/Utilities/CPU/cpu_utils.c
@@ -0,0 +1,144 @@
+/**
+  ******************************************************************************
+  * @file    cpu_utils.c
+  * @author  MCD Application Team
+  * @version V1.1.0
+  * @date    20-November-2014
+  * @brief   Utilities for CPU Load calculation
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */ 
+
+/********************** NOTES **********************************************
+To use this module, the following steps should be followed :
+
+1- in the _OS_Config.h file (ex. FreeRTOSConfig.h) enable the following macros : 
+      - #define configUSE_IDLE_HOOK        1
+      - #define configUSE_TICK_HOOK        1
+
+2- in the _OS_Config.h define the following macros : 
+      - #define traceTASK_SWITCHED_IN()  extern void StartIdleMonitor(void); \
+                                         StartIdleMonitor()
+      - #define traceTASK_SWITCHED_OUT() extern void EndIdleMonitor(void); \
+                                         EndIdleMonitor()
+*******************************************************************************/
+
+
+/* Includes ------------------------------------------------------------------*/
+#include "cpu_utils.h"
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+
+xTaskHandle    xIdleHandle = NULL;
+__IO uint32_t  osCPU_Usage = 0; 
+uint32_t       osCPU_IdleStartTime = 0; 
+uint32_t       osCPU_IdleSpentTime = 0; 
+uint32_t       osCPU_TotalIdleTime = 0; 
+
+/* Private functions ---------------------------------------------------------*/
+/**
+  * @brief  Application Idle Hook
+  * @param  None 
+  * @retval None
+  */
+void vApplicationIdleHook(void) 
+{
+  if( xIdleHandle == NULL )
+  {
+    /* Store the handle to the idle task. */
+    xIdleHandle = xTaskGetCurrentTaskHandle();
+  }
+}
+
+/**
+  * @brief  Application Idle Hook
+  * @param  None 
+  * @retval None
+  */
+void vApplicationTickHook (void)
+{
+  static int tick = 0;
+  
+  if(tick ++ > CALCULATION_PERIOD)
+  {
+    tick = 0;
+    
+    if(osCPU_TotalIdleTime > 1000)
+    {
+      osCPU_TotalIdleTime = 1000;
+    }
+    osCPU_Usage = (100 - (osCPU_TotalIdleTime * 100) / CALCULATION_PERIOD);
+    osCPU_TotalIdleTime = 0;
+  }
+}
+
+/**
+  * @brief  Start Idle monitor
+  * @param  None 
+  * @retval None
+  */
+void StartIdleMonitor (void)
+{
+  if( xTaskGetCurrentTaskHandle() == xIdleHandle ) 
+  {
+    osCPU_IdleStartTime = xTaskGetTickCountFromISR();
+  }
+}
+
+/**
+  * @brief  Stop Idle monitor
+  * @param  None 
+  * @retval None
+  */
+void EndIdleMonitor (void)
+{
+  if( xTaskGetCurrentTaskHandle() == xIdleHandle )
+  {
+    /* Store the handle to the idle task. */
+    osCPU_IdleSpentTime = xTaskGetTickCountFromISR() - osCPU_IdleStartTime;
+    osCPU_TotalIdleTime += osCPU_IdleSpentTime; 
+  }
+}
+
+/**
+  * @brief  Stop Idle monitor
+  * @param  None 
+  * @retval None
+  */
+uint16_t osGetCPUUsage (void)
+{
+  return (uint16_t)osCPU_Usage;
+}
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Utilities/CPU/cpu_utils.h b/Utilities/CPU/cpu_utils.h
new file mode 100644
index 0000000..db4ee9c
--- /dev/null
+++ b/Utilities/CPU/cpu_utils.h
@@ -0,0 +1,64 @@
+/**
+  ******************************************************************************
+  * @file    cpu_utils.h
+  * @author  MCD Application Team
+  * @version V1.1.0
+  * @date    20-November-2014
+  * @brief   Header for cpu_utils module
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */ 
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef _CPU_UTILS_H__
+#define _CPU_UTILS_H__
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Exported variables --------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+#define CALCULATION_PERIOD    1000
+
+/* Exported functions ------------------------------------------------------- */
+uint16_t osGetCPUUsage (void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _CPU_UTILS_H__ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Utilities/Fonts/Release_Notes.html b/Utilities/Fonts/Release_Notes.html
new file mode 100644
index 0000000..8c60ce7
--- /dev/null
+++ b/Utilities/Fonts/Release_Notes.html
@@ -0,0 +1,163 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html xmlns:v="urn:schemas-microsoft-com:vml" xmlns:o="urn:schemas-microsoft-com:office:office" xmlns:w="urn:schemas-microsoft-com:office:word" xmlns="http://www.w3.org/TR/REC-html40"><head>
+
+
+
+
+
+
+
+
+
+
+  
+  <meta http-equiv="Content-Type" content="text/html; charset=ISO-8859-1">
+
+  
+  <link rel="File-List" href="Library_files/filelist.xml">
+
+  
+  <link rel="Edit-Time-Data" href="Library_files/editdata.mso"><!--[if !mso]> <style> v\:* {behavior:url(#default#VML);} o\:* {behavior:url(#default#VML);} w\:* {behavior:url(#default#VML);} .shape {behavior:url(#default#VML);} </style> <![endif]--><title>Release Notes for STM32Cube Fonts Utilities Driver</title><!--[if gte mso 9]><xml> <o:DocumentProperties> <o:Author>STMicroelectronics</o:Author> <o:LastAuthor>STMicroelectronics</o:LastAuthor> <o:Revision>37</o:Revision> <o:TotalTime>136</o:TotalTime> <o:Created>2009-02-27T19:26:00Z</o:Created> <o:LastSaved>2009-03-01T17:56:00Z</o:LastSaved> <o:Pages>1</o:Pages> <o:Words>522</o:Words> <o:Characters>2977</o:Characters> <o:Company>STMicroelectronics</o:Company> <o:Lines>24</o:Lines> <o:Paragraphs>6</o:Paragraphs> <o:CharactersWithSpaces>3493</o:CharactersWithSpaces> <o:Version>11.6568</o:Version> </o:DocumentProperties> </xml><![endif]--><!--[if gte mso 9]><xml> <w:WordDocument> <w:Zoom>110</w:Zoom> <w:ValidateAgainstSchemas/> <w:SaveIfXMLInvalid>false</w:SaveIfXMLInvalid> <w:IgnoreMixedContent>false</w:IgnoreMixedContent> <w:AlwaysShowPlaceholderText>false</w:AlwaysShowPlaceholderText> <w:BrowserLevel>MicrosoftInternetExplorer4</w:BrowserLevel> </w:WordDocument> </xml><![endif]--><!--[if gte mso 9]><xml> <w:LatentStyles DefLockedState="false" LatentStyleCount="156"> </w:LatentStyles> </xml><![endif]-->
+
+
+  
+
+  
+
+  
+  <style>
+<!--
+/* Style Definitions */
+p.MsoNormal, li.MsoNormal, div.MsoNormal
+{mso-style-parent:"";
+margin:0in;
+margin-bottom:.0001pt;
+mso-pagination:widow-orphan;
+font-size:12.0pt;
+font-family:"Times New Roman";
+mso-fareast-font-family:"Times New Roman";}
+h2
+{mso-style-next:Normal;
+margin-top:12.0pt;
+margin-right:0in;
+margin-bottom:3.0pt;
+margin-left:0in;
+mso-pagination:widow-orphan;
+page-break-after:avoid;
+mso-outline-level:2;
+font-size:14.0pt;
+font-family:Arial;
+font-weight:bold;
+font-style:italic;}
+a:link, span.MsoHyperlink
+{color:blue;
+text-decoration:underline;
+text-underline:single;}
+a:visited, span.MsoHyperlinkFollowed
+{color:blue;
+text-decoration:underline;
+text-underline:single;}
+p
+{mso-margin-top-alt:auto;
+margin-right:0in;
+mso-margin-bottom-alt:auto;
+margin-left:0in;
+mso-pagination:widow-orphan;
+font-size:12.0pt;
+font-family:"Times New Roman";
+mso-fareast-font-family:"Times New Roman";}
+@page Section1
+{size:8.5in 11.0in;
+margin:1.0in 1.25in 1.0in 1.25in;
+mso-header-margin:.5in;
+mso-footer-margin:.5in;
+mso-paper-source:0;}
+div.Section1
+{page:Section1;}
+-->
+  </style><!--[if gte mso 10]> <style> /* Style Definitions */ table.MsoNormalTable {mso-style-name:"Table Normal"; mso-tstyle-rowband-size:0; mso-tstyle-colband-size:0; mso-style-noshow:yes; mso-style-parent:""; mso-padding-alt:0in 5.4pt 0in 5.4pt; mso-para-margin:0in; mso-para-margin-bottom:.0001pt; mso-pagination:widow-orphan; font-size:10.0pt; font-family:"Times New Roman"; mso-ansi-language:#0400; mso-fareast-language:#0400; mso-bidi-language:#0400;} </style> <![endif]--><!--[if gte mso 9]><xml> <o:shapedefaults v:ext="edit" spidmax="5122"/> </xml><![endif]--><!--[if gte mso 9]><xml> <o:shapelayout v:ext="edit"> <o:idmap v:ext="edit" data="1"/> </o:shapelayout></xml><![endif]-->
+  <meta content="MCD Application Team" name="author"></head><body link="blue" vlink="blue">
+<div class="Section1">
+<p class="MsoNormal"><span style="font-family: Arial;"><o:p><br>
+</o:p></span></p>
+<div align="center">
+<table class="MsoNormalTable" style="width: 675pt;" border="0" cellpadding="0" cellspacing="0" width="900">
+  <tbody>
+    <tr>
+      <td style="padding: 0cm;" valign="top">
+      <table class="MsoNormalTable" style="width: 675pt;" border="0" cellpadding="0" cellspacing="0" width="900">
+        <tbody>
+          <tr>
+            <td style="vertical-align: top;">
+            <p class="MsoNormal"><span style="font-size: 8pt; font-family: Arial; color: blue;"><a href="../../Release_Notes.html">Back to Release page</a><o:p></o:p></span></p>
+            </td>
+          </tr>
+          <tr style="">
+            <td style="padding: 1.5pt;">
+            <h1 style="margin-bottom: 18pt; text-align: center;" align="center"><span style="font-size: 20pt; font-family: Verdana; color: rgb(51, 102, 255);">Release
+Notes for STM32Cube Fonts Utilities Driver</span><span style="font-size: 20pt; font-family: Verdana;"><o:p></o:p></span></h1>
+            <p class="MsoNormal" style="text-align: center;" align="center"><span style="font-size: 10pt; font-family: Arial; color: black;">Copyright
+2014 STMicroelectronics</span><span style="color: black;"><u1:p></u1:p><o:p></o:p></span></p>
+            <p class="MsoNormal" style="text-align: center;" align="center"><span style="font-size: 10pt; font-family: Arial; color: black;"><img alt="" id="_x0000_i1025" src="../../_htmresc/st_logo.png" style="border: 0px solid ; width: 86px; height: 65px;"></span><span style="font-size: 10pt;"><o:p></o:p></span></p>
+            </td>
+          </tr>
+        </tbody>
+      </table>
+      <p class="MsoNormal"><span style="font-family: Arial; display: none;"><o:p>&nbsp;</o:p></span></p>
+      <table class="MsoNormalTable" style="width: 675pt;" border="0" cellpadding="0" width="900">
+        <tbody>
+          <tr style="">
+            <td style="padding: 0cm;" valign="top">
+            <span style="font-family: &quot;Times New Roman&quot;;"></span><h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial;"><a name="History"></a><span style="font-size: 12pt; color: white;">Update History</span></h2><br>
+            <h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; margin-right: 500pt; width: 180px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.0.0 / 18-February-2014 <o:p></o:p></span></h3>
+
+
+            
+            
+            <p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
+Changes<o:p></o:p></span></u></b></p>
+            <span style="font-size: 10pt; font-family: Verdana;"></span><p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;"><o:p></o:p></span></u></b></p>
+
+
+            
+            <ul style="list-style-type: square;">
+              <li><span style="font-size: 10pt; font-family: Verdana;">First official release</span><span style="font-size: 10pt; font-family: Verdana;"><br>
+                </span></li>
+            </ul><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic; font-weight: bold;"></span></span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic; font-weight: bold;"></span></span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic; font-weight: bold;"></span></span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic; font-weight: bold;"></span></span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic; font-weight: bold;"></span></span><span style="font-size: 10pt; font-family: Verdana;"></span><h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial;"><a name="License"></a><span style="font-size: 12pt; color: white;">License<o:p></o:p></span><br></h2>
+            <div style="text-align: justify;"><font size="-1"><span style="font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are
+met:</span><br>
+            </font>
+            <ol><li><font size="-1"><span style="font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.</span><span style="font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"></span></font></li><li><font size="-1"><span style="font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Redistributions
+in binary form must reproduce the above copyright notice, this list of
+conditions and the following disclaimer in </span><span style="font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">the documentation and/or other materials provided with the distribution.</span><span style="font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"></span></font></li><li><font size="-1"><span style="font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived </span><br>
+                </font>
+              </li></ol>
+            <font size="-1"><span style="font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; from this software without specific prior written permission.</span><br>
+            <span style="font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"></span><br>
+            <span style="font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED</span><span style="font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"> WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A </span><span style="font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY </span><span style="font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, </span><span style="font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER</span><span style="font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"> CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR </span><span style="font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.</span></font>
+            
+            </div>
+<p class="MsoNormal"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;; color: black;"><o:p></o:p></span></p>
+<b><span style="font-size: 10pt; font-family: Verdana; color: black;"></span></b>
+            
+            <div class="MsoNormal" style="text-align: center;" align="center"><span style="color: black;">
+            <hr align="center" size="2" width="100%"></span></div>
+            <p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt; text-align: center;" align="center"><span style="font-size: 10pt; font-family: Verdana; color: black;">For
+complete documentation on </span><span style="font-size: 10pt; font-family: Verdana;">STM32<span style="color: black;">&nbsp;Microcontrollers
+visit </span><u><span style="color: blue;"><a href="http://www.st.com/internet/mcu/class/1734.jsp" target="_blank">www.st.com/STM32</a></span></u></span><span style="font-size: 10pt; font-family: Verdana;"><a target="_blank" href="http://www.st.com/internet/mcu/family/141.jsp"><u><span style="color: blue;"></span></u></a></span><span style="font-size: 10pt; font-family: Verdana;"><u><span style="color: blue;"></span></u></span><span style="color: black;"><o:p></o:p></span></p>
+            </td>
+          </tr>
+        </tbody>
+      </table>
+      <p class="MsoNormal"><span style="font-size: 10pt;"><o:p></o:p></span></p>
+      </td>
+    </tr>
+  </tbody>
+</table>
+</div>
+<p class="MsoNormal"><o:p>&nbsp;</o:p></p>
+</div>
+
+</body></html>
\ No newline at end of file
diff --git a/Utilities/Fonts/font12.c b/Utilities/Fonts/font12.c
new file mode 100644
index 0000000..7d428cd
--- /dev/null
+++ b/Utilities/Fonts/font12.c
@@ -0,0 +1,1464 @@
+/**
+  ******************************************************************************
+  * @file    Font12.c
+  * @author  MCD Application Team
+  * @version V1.0.0
+  * @date    18-February-2014
+  * @brief   This file provides text Font12 for STM32xx-EVAL's LCD driver. 
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "fonts.h"
+
+/** @addtogroup Utilities
+  * @{
+  */
+  
+/** @addtogroup STM32_EVAL
+  * @{
+  */ 
+
+/** @addtogroup Common
+  * @{
+  */
+
+/** @addtogroup FONTS
+  * @brief      This file provides text Font12 for STM32xx-EVAL's LCD driver.
+  * @{
+  */  
+
+/** @defgroup FONTS_Private_Types
+  * @{
+  */ 
+/**
+  * @}
+  */ 
+
+
+/** @defgroup FONTS_Private_Defines
+  * @{
+  */
+/**
+  * @}
+  */ 
+
+
+/** @defgroup FONTS_Private_Macros
+  * @{
+  */
+/**
+  * @}
+  */ 
+  
+
+/** @defgroup FONTS_Private_Variables
+  * @{
+  */
+// 
+//  Font data for Courier New 12pt
+// 
+
+const uint8_t Font12_Table[] = 
+{
+	// @0 ' ' (7 pixels wide)
+	0x00, //        
+	0x00, //        
+	0x00, //        
+	0x00, //        
+	0x00, //        
+	0x00, //        
+	0x00, //        
+	0x00, //        
+	0x00, //        
+	0x00, //        
+	0x00, //        
+	0x00, //        
+
+	// @12 '!' (7 pixels wide)
+	0x00, //        
+	0x10, //    #   
+	0x10, //    #   
+	0x10, //    #   
+	0x10, //    #   
+	0x10, //    #   
+	0x00, //        
+	0x00, //        
+	0x10, //    #   
+	0x00, //        
+	0x00, //        
+	0x00, //        
+
+	// @24 '"' (7 pixels wide)
+	0x00, //        
+	0x6C, //  ## ## 
+	0x48, //  #  #  
+	0x48, //  #  #  
+	0x00, //        
+	0x00, //        
+	0x00, //        
+	0x00, //        
+	0x00, //        
+	0x00, //        
+	0x00, //        
+	0x00, //        
+
+	// @36 '#' (7 pixels wide)
+	0x00, //        
+	0x14, //    # # 
+	0x14, //    # # 
+	0x28, //   # #  
+	0x7C, //  ##### 
+	0x28, //   # #  
+	0x7C, //  ##### 
+	0x28, //   # #  
+	0x50, //  # #   
+	0x50, //  # #   
+	0x00, //        
+	0x00, //        
+
+	// @48 '$' (7 pixels wide)
+	0x00, //        
+	0x10, //    #   
+	0x38, //   ###  
+	0x40, //  #     
+	0x40, //  #     
+	0x38, //   ###  
+	0x48, //  #  #  
+	0x70, //  ###   
+	0x10, //    #   
+	0x10, //    #   
+	0x00, //        
+	0x00, //        
+
+	// @60 '%' (7 pixels wide)
+	0x00, //        
+	0x20, //   #    
+	0x50, //  # #   
+	0x20, //   #    
+	0x0C, //     ## 
+	0x70, //  ###   
+	0x08, //     #  
+	0x14, //    # # 
+	0x08, //     #  
+	0x00, //        
+	0x00, //        
+	0x00, //        
+
+	// @72 '&' (7 pixels wide)
+	0x00, //        
+	0x00, //        
+	0x00, //        
+	0x18, //    ##  
+	0x20, //   #    
+	0x20, //   #    
+	0x54, //  # # # 
+	0x48, //  #  #  
+	0x34, //   ## # 
+	0x00, //        
+	0x00, //        
+	0x00, //        
+
+	// @84 ''' (7 pixels wide)
+	0x00, //        
+	0x10, //    #   
+	0x10, //    #   
+	0x10, //    #   
+	0x10, //    #   
+	0x00, //        
+	0x00, //        
+	0x00, //        
+	0x00, //        
+	0x00, //        
+	0x00, //        
+	0x00, //        
+
+	// @96 '(' (7 pixels wide)
+	0x00, //        
+	0x08, //     #  
+	0x08, //     #  
+	0x10, //    #   
+	0x10, //    #   
+	0x10, //    #   
+	0x10, //    #   
+	0x10, //    #   
+	0x10, //    #   
+	0x08, //     #  
+	0x08, //     #  
+	0x00, //        
+
+	// @108 ')' (7 pixels wide)
+	0x00, //        
+	0x20, //   #    
+	0x20, //   #    
+	0x10, //    #   
+	0x10, //    #   
+	0x10, //    #   
+	0x10, //    #   
+	0x10, //    #   
+	0x10, //    #   
+	0x20, //   #    
+	0x20, //   #    
+	0x00, //        
+
+	// @120 '*' (7 pixels wide)
+	0x00, //        
+	0x10, //    #   
+	0x7C, //  ##### 
+	0x10, //    #   
+	0x28, //   # #  
+	0x28, //   # #  
+	0x00, //        
+	0x00, //        
+	0x00, //        
+	0x00, //        
+	0x00, //        
+	0x00, //        
+
+	// @132 '+' (7 pixels wide)
+	0x00, //        
+	0x00, //        
+	0x10, //    #   
+	0x10, //    #   
+	0x10, //    #   
+	0xFE, // #######
+	0x10, //    #   
+	0x10, //    #   
+	0x10, //    #   
+	0x00, //        
+	0x00, //        
+	0x00, //        
+
+	// @144 ',' (7 pixels wide)
+	0x00, //        
+	0x00, //        
+	0x00, //        
+	0x00, //        
+	0x00, //        
+	0x00, //        
+	0x00, //        
+	0x18, //    ##  
+	0x10, //    #   
+	0x30, //   ##   
+	0x20, //   #    
+	0x00, //        
+
+	// @156 '-' (7 pixels wide)
+	0x00, //        
+	0x00, //        
+	0x00, //        
+	0x00, //        
+	0x00, //        
+	0x7C, //  ##### 
+	0x00, //        
+	0x00, //        
+	0x00, //        
+	0x00, //        
+	0x00, //        
+	0x00, //        
+
+	// @168 '.' (7 pixels wide)
+	0x00, //        
+	0x00, //        
+	0x00, //        
+	0x00, //        
+	0x00, //        
+	0x00, //        
+	0x00, //        
+	0x30, //   ##   
+	0x30, //   ##   
+	0x00, //        
+	0x00, //        
+	0x00, //        
+
+	// @180 '/' (7 pixels wide)
+	0x00, //        
+	0x04, //      # 
+	0x04, //      # 
+	0x08, //     #  
+	0x08, //     #  
+	0x10, //    #   
+	0x10, //    #   
+	0x20, //   #    
+	0x20, //   #    
+	0x40, //  #     
+	0x00, //        
+	0x00, //        
+
+	// @192 '0' (7 pixels wide)
+	0x00, //        
+	0x38, //   ###  
+	0x44, //  #   # 
+	0x44, //  #   # 
+	0x44, //  #   # 
+	0x44, //  #   # 
+	0x44, //  #   # 
+	0x44, //  #   # 
+	0x38, //   ###  
+	0x00, //        
+	0x00, //        
+	0x00, //        
+
+	// @204 '1' (7 pixels wide)
+	0x00, //        
+	0x30, //   ##   
+	0x10, //    #   
+	0x10, //    #   
+	0x10, //    #   
+	0x10, //    #   
+	0x10, //    #   
+	0x10, //    #   
+	0x7C, //  ##### 
+	0x00, //        
+	0x00, //        
+	0x00, //        
+
+	// @216 '2' (7 pixels wide)
+	0x00, //        
+	0x38, //   ###  
+	0x44, //  #   # 
+	0x04, //      # 
+	0x08, //     #  
+	0x10, //    #   
+	0x20, //   #    
+	0x44, //  #   # 
+	0x7C, //  ##### 
+	0x00, //        
+	0x00, //        
+	0x00, //        
+
+	// @228 '3' (7 pixels wide)
+	0x00, //        
+	0x38, //   ###  
+	0x44, //  #   # 
+	0x04, //      # 
+	0x18, //    ##  
+	0x04, //      # 
+	0x04, //      # 
+	0x44, //  #   # 
+	0x38, //   ###  
+	0x00, //        
+	0x00, //        
+	0x00, //        
+
+	// @240 '4' (7 pixels wide)
+	0x00, //        
+	0x0C, //     ## 
+	0x14, //    # # 
+	0x14, //    # # 
+	0x24, //   #  # 
+	0x44, //  #   # 
+	0x7E, //  ######
+	0x04, //      # 
+	0x0E, //     ###
+	0x00, //        
+	0x00, //        
+	0x00, //        
+
+	// @252 '5' (7 pixels wide)
+	0x00, //        
+	0x3C, //   #### 
+	0x20, //   #    
+	0x20, //   #    
+	0x38, //   ###  
+	0x04, //      # 
+	0x04, //      # 
+	0x44, //  #   # 
+	0x38, //   ###  
+	0x00, //        
+	0x00, //        
+	0x00, //        
+
+	// @264 '6' (7 pixels wide)
+	0x00, //        
+	0x1C, //    ### 
+	0x20, //   #    
+	0x40, //  #     
+	0x78, //  ####  
+	0x44, //  #   # 
+	0x44, //  #   # 
+	0x44, //  #   # 
+	0x38, //   ###  
+	0x00, //        
+	0x00, //        
+	0x00, //        
+
+	// @276 '7' (7 pixels wide)
+	0x00, //        
+	0x7C, //  ##### 
+	0x44, //  #   # 
+	0x04, //      # 
+	0x08, //     #  
+	0x08, //     #  
+	0x08, //     #  
+	0x10, //    #   
+	0x10, //    #   
+	0x00, //        
+	0x00, //        
+	0x00, //        
+
+	// @288 '8' (7 pixels wide)
+	0x00, //        
+	0x38, //   ###  
+	0x44, //  #   # 
+	0x44, //  #   # 
+	0x38, //   ###  
+	0x44, //  #   # 
+	0x44, //  #   # 
+	0x44, //  #   # 
+	0x38, //   ###  
+	0x00, //        
+	0x00, //        
+	0x00, //        
+
+	// @300 '9' (7 pixels wide)
+	0x00, //        
+	0x38, //   ###  
+	0x44, //  #   # 
+	0x44, //  #   # 
+	0x44, //  #   # 
+	0x3C, //   #### 
+	0x04, //      # 
+	0x08, //     #  
+	0x70, //  ###   
+	0x00, //        
+	0x00, //        
+	0x00, //        
+
+	// @312 ':' (7 pixels wide)
+	0x00, //        
+	0x00, //        
+	0x00, //        
+	0x30, //   ##   
+	0x30, //   ##   
+	0x00, //        
+	0x00, //        
+	0x30, //   ##   
+	0x30, //   ##   
+	0x00, //        
+	0x00, //        
+	0x00, //        
+
+	// @324 ';' (7 pixels wide)
+	0x00, //        
+	0x00, //        
+	0x00, //        
+	0x18, //    ##  
+	0x18, //    ##  
+	0x00, //        
+	0x00, //        
+	0x18, //    ##  
+	0x30, //   ##   
+	0x20, //   #    
+	0x00, //        
+	0x00, //        
+
+	// @336 '<' (7 pixels wide)
+	0x00, //        
+	0x00, //        
+	0x0C, //     ## 
+	0x10, //    #   
+	0x60, //  ##    
+	0x80, // #      
+	0x60, //  ##    
+	0x10, //    #   
+	0x0C, //     ## 
+	0x00, //        
+	0x00, //        
+	0x00, //        
+
+	// @348 '=' (7 pixels wide)
+	0x00, //        
+	0x00, //        
+	0x00, //        
+	0x00, //        
+	0x7C, //  ##### 
+	0x00, //        
+	0x7C, //  ##### 
+	0x00, //        
+	0x00, //        
+	0x00, //        
+	0x00, //        
+	0x00, //        
+
+	// @360 '>' (7 pixels wide)
+	0x00, //        
+	0x00, //        
+	0xC0, // ##     
+	0x20, //   #    
+	0x18, //    ##  
+	0x04, //      # 
+	0x18, //    ##  
+	0x20, //   #    
+	0xC0, // ##     
+	0x00, //        
+	0x00, //        
+	0x00, //        
+
+	// @372 '?' (7 pixels wide)
+	0x00, //        
+	0x00, //        
+	0x18, //    ##  
+	0x24, //   #  # 
+	0x04, //      # 
+	0x08, //     #  
+	0x10, //    #   
+	0x00, //        
+	0x30, //   ##   
+	0x00, //        
+	0x00, //        
+	0x00, //        
+
+	// @384 '@' (7 pixels wide)
+	0x38, //   ###  
+	0x44, //  #   # 
+	0x44, //  #   # 
+	0x4C, //  #  ## 
+	0x54, //  # # # 
+	0x54, //  # # # 
+	0x4C, //  #  ## 
+	0x40, //  #     
+	0x44, //  #   # 
+	0x38, //   ###  
+	0x00, //        
+	0x00, //        
+
+	// @396 'A' (7 pixels wide)
+	0x00, //        
+	0x30, //   ##   
+	0x10, //    #   
+	0x28, //   # #  
+	0x28, //   # #  
+	0x28, //   # #  
+	0x7C, //  ##### 
+	0x44, //  #   # 
+	0xEE, // ### ###
+	0x00, //        
+	0x00, //        
+	0x00, //        
+
+	// @408 'B' (7 pixels wide)
+	0x00, //        
+	0xF8, // #####  
+	0x44, //  #   # 
+	0x44, //  #   # 
+	0x78, //  ####  
+	0x44, //  #   # 
+	0x44, //  #   # 
+	0x44, //  #   # 
+	0xF8, // #####  
+	0x00, //        
+	0x00, //        
+	0x00, //        
+
+	// @420 'C' (7 pixels wide)
+	0x00, //        
+	0x3C, //   #### 
+	0x44, //  #   # 
+	0x40, //  #     
+	0x40, //  #     
+	0x40, //  #     
+	0x40, //  #     
+	0x44, //  #   # 
+	0x38, //   ###  
+	0x00, //        
+	0x00, //        
+	0x00, //        
+
+	// @432 'D' (7 pixels wide)
+	0x00, //        
+	0xF0, // ####   
+	0x48, //  #  #  
+	0x44, //  #   # 
+	0x44, //  #   # 
+	0x44, //  #   # 
+	0x44, //  #   # 
+	0x48, //  #  #  
+	0xF0, // ####   
+	0x00, //        
+	0x00, //        
+	0x00, //        
+
+	// @444 'E' (7 pixels wide)
+	0x00, //        
+	0xFC, // ###### 
+	0x44, //  #   # 
+	0x50, //  # #   
+	0x70, //  ###   
+	0x50, //  # #   
+	0x40, //  #     
+	0x44, //  #   # 
+	0xFC, // ###### 
+	0x00, //        
+	0x00, //        
+	0x00, //        
+
+	// @456 'F' (7 pixels wide)
+	0x00, //        
+	0x7E, //  ######
+	0x22, //   #   #
+	0x28, //   # #  
+	0x38, //   ###  
+	0x28, //   # #  
+	0x20, //   #    
+	0x20, //   #    
+	0x70, //  ###   
+	0x00, //        
+	0x00, //        
+	0x00, //        
+
+	// @468 'G' (7 pixels wide)
+	0x00, //        
+	0x3C, //   #### 
+	0x44, //  #   # 
+	0x40, //  #     
+	0x40, //  #     
+	0x4E, //  #  ###
+	0x44, //  #   # 
+	0x44, //  #   # 
+	0x38, //   ###  
+	0x00, //        
+	0x00, //        
+	0x00, //        
+
+	// @480 'H' (7 pixels wide)
+	0x00, //        
+	0xEE, // ### ###
+	0x44, //  #   # 
+	0x44, //  #   # 
+	0x7C, //  ##### 
+	0x44, //  #   # 
+	0x44, //  #   # 
+	0x44, //  #   # 
+	0xEE, // ### ###
+	0x00, //        
+	0x00, //        
+	0x00, //        
+
+	// @492 'I' (7 pixels wide)
+	0x00, //        
+	0x7C, //  ##### 
+	0x10, //    #   
+	0x10, //    #   
+	0x10, //    #   
+	0x10, //    #   
+	0x10, //    #   
+	0x10, //    #   
+	0x7C, //  ##### 
+	0x00, //        
+	0x00, //        
+	0x00, //        
+
+	// @504 'J' (7 pixels wide)
+	0x00, //        
+	0x3C, //   #### 
+	0x08, //     #  
+	0x08, //     #  
+	0x08, //     #  
+	0x48, //  #  #  
+	0x48, //  #  #  
+	0x48, //  #  #  
+	0x30, //   ##   
+	0x00, //        
+	0x00, //        
+	0x00, //        
+
+	// @516 'K' (7 pixels wide)
+	0x00, //        
+	0xEE, // ### ###
+	0x44, //  #   # 
+	0x48, //  #  #  
+	0x50, //  # #   
+	0x70, //  ###   
+	0x48, //  #  #  
+	0x44, //  #   # 
+	0xE6, // ###  ##
+	0x00, //        
+	0x00, //        
+	0x00, //        
+
+	// @528 'L' (7 pixels wide)
+	0x00, //        
+	0x70, //  ###   
+	0x20, //   #    
+	0x20, //   #    
+	0x20, //   #    
+	0x20, //   #    
+	0x24, //   #  # 
+	0x24, //   #  # 
+	0x7C, //  ##### 
+	0x00, //        
+	0x00, //        
+	0x00, //        
+
+	// @540 'M' (7 pixels wide)
+	0x00, //        
+	0xEE, // ### ###
+	0x6C, //  ## ## 
+	0x6C, //  ## ## 
+	0x54, //  # # # 
+	0x54, //  # # # 
+	0x44, //  #   # 
+	0x44, //  #   # 
+	0xEE, // ### ###
+	0x00, //        
+	0x00, //        
+	0x00, //        
+
+	// @552 'N' (7 pixels wide)
+	0x00, //        
+	0xEE, // ### ###
+	0x64, //  ##  # 
+	0x64, //  ##  # 
+	0x54, //  # # # 
+	0x54, //  # # # 
+	0x54, //  # # # 
+	0x4C, //  #  ## 
+	0xEC, // ### ## 
+	0x00, //        
+	0x00, //        
+	0x00, //        
+
+	// @564 'O' (7 pixels wide)
+	0x00, //        
+	0x38, //   ###  
+	0x44, //  #   # 
+	0x44, //  #   # 
+	0x44, //  #   # 
+	0x44, //  #   # 
+	0x44, //  #   # 
+	0x44, //  #   # 
+	0x38, //   ###  
+	0x00, //        
+	0x00, //        
+	0x00, //        
+
+	// @576 'P' (7 pixels wide)
+	0x00, //        
+	0x78, //  ####  
+	0x24, //   #  # 
+	0x24, //   #  # 
+	0x24, //   #  # 
+	0x38, //   ###  
+	0x20, //   #    
+	0x20, //   #    
+	0x70, //  ###   
+	0x00, //        
+	0x00, //        
+	0x00, //        
+
+	// @588 'Q' (7 pixels wide)
+	0x00, //        
+	0x38, //   ###  
+	0x44, //  #   # 
+	0x44, //  #   # 
+	0x44, //  #   # 
+	0x44, //  #   # 
+	0x44, //  #   # 
+	0x44, //  #   # 
+	0x38, //   ###  
+	0x1C, //    ### 
+	0x00, //        
+	0x00, //        
+
+	// @600 'R' (7 pixels wide)
+	0x00, //        
+	0xF8, // #####  
+	0x44, //  #   # 
+	0x44, //  #   # 
+	0x44, //  #   # 
+	0x78, //  ####  
+	0x48, //  #  #  
+	0x44, //  #   # 
+	0xE2, // ###   #
+	0x00, //        
+	0x00, //        
+	0x00, //        
+
+	// @612 'S' (7 pixels wide)
+	0x00, //        
+	0x34, //   ## # 
+	0x4C, //  #  ## 
+	0x40, //  #     
+	0x38, //   ###  
+	0x04, //      # 
+	0x04, //      # 
+	0x64, //  ##  # 
+	0x58, //  # ##  
+	0x00, //        
+	0x00, //        
+	0x00, //        
+
+	// @624 'T' (7 pixels wide)
+	0x00, //        
+	0xFE, // #######
+	0x92, // #  #  #
+	0x10, //    #   
+	0x10, //    #   
+	0x10, //    #   
+	0x10, //    #   
+	0x10, //    #   
+	0x38, //   ###  
+	0x00, //        
+	0x00, //        
+	0x00, //        
+
+	// @636 'U' (7 pixels wide)
+	0x00, //        
+	0xEE, // ### ###
+	0x44, //  #   # 
+	0x44, //  #   # 
+	0x44, //  #   # 
+	0x44, //  #   # 
+	0x44, //  #   # 
+	0x44, //  #   # 
+	0x38, //   ###  
+	0x00, //        
+	0x00, //        
+	0x00, //        
+
+	// @648 'V' (7 pixels wide)
+	0x00, //        
+	0xEE, // ### ###
+	0x44, //  #   # 
+	0x44, //  #   # 
+	0x28, //   # #  
+	0x28, //   # #  
+	0x28, //   # #  
+	0x10, //    #   
+	0x10, //    #   
+	0x00, //        
+	0x00, //        
+	0x00, //        
+
+	// @660 'W' (7 pixels wide)
+	0x00, //        
+	0xEE, // ### ###
+	0x44, //  #   # 
+	0x44, //  #   # 
+	0x54, //  # # # 
+	0x54, //  # # # 
+	0x54, //  # # # 
+	0x54, //  # # # 
+	0x28, //   # #  
+	0x00, //        
+	0x00, //        
+	0x00, //        
+
+	// @672 'X' (7 pixels wide)
+	0x00, //        
+	0xC6, // ##   ##
+	0x44, //  #   # 
+	0x28, //   # #  
+	0x10, //    #   
+	0x10, //    #   
+	0x28, //   # #  
+	0x44, //  #   # 
+	0xC6, // ##   ##
+	0x00, //        
+	0x00, //        
+	0x00, //        
+
+	// @684 'Y' (7 pixels wide)
+	0x00, //        
+	0xEE, // ### ###
+	0x44, //  #   # 
+	0x28, //   # #  
+	0x28, //   # #  
+	0x10, //    #   
+	0x10, //    #   
+	0x10, //    #   
+	0x38, //   ###  
+	0x00, //        
+	0x00, //        
+	0x00, //        
+
+	// @696 'Z' (7 pixels wide)
+	0x00, //        
+	0x7C, //  ##### 
+	0x44, //  #   # 
+	0x08, //     #  
+	0x10, //    #   
+	0x10, //    #   
+	0x20, //   #    
+	0x44, //  #   # 
+	0x7C, //  ##### 
+	0x00, //        
+	0x00, //        
+	0x00, //        
+
+	// @708 '[' (7 pixels wide)
+	0x00, //        
+	0x38, //   ###  
+	0x20, //   #    
+	0x20, //   #    
+	0x20, //   #    
+	0x20, //   #    
+	0x20, //   #    
+	0x20, //   #    
+	0x20, //   #    
+	0x20, //   #    
+	0x38, //   ###  
+	0x00, //        
+
+	// @720 '\' (7 pixels wide)
+	0x00, //        
+	0x40, //  #     
+	0x20, //   #    
+	0x20, //   #    
+	0x20, //   #    
+	0x10, //    #   
+	0x10, //    #   
+	0x08, //     #  
+	0x08, //     #  
+	0x08, //     #  
+	0x00, //        
+	0x00, //        
+
+	// @732 ']' (7 pixels wide)
+	0x00, //        
+	0x38, //   ###  
+	0x08, //     #  
+	0x08, //     #  
+	0x08, //     #  
+	0x08, //     #  
+	0x08, //     #  
+	0x08, //     #  
+	0x08, //     #  
+	0x08, //     #  
+	0x38, //   ###  
+	0x00, //        
+
+	// @744 '^' (7 pixels wide)
+	0x00, //        
+	0x10, //    #   
+	0x10, //    #   
+	0x28, //   # #  
+	0x44, //  #   # 
+	0x00, //        
+	0x00, //        
+	0x00, //        
+	0x00, //        
+	0x00, //        
+	0x00, //        
+	0x00, //        
+
+	// @756 '_' (7 pixels wide)
+	0x00, //        
+	0x00, //        
+	0x00, //        
+	0x00, //        
+	0x00, //        
+	0x00, //        
+	0x00, //        
+	0x00, //        
+	0x00, //        
+	0x00, //        
+	0x00, //        
+	0xFE, // #######
+
+	// @768 '`' (7 pixels wide)
+	0x00, //        
+	0x10, //    #   
+	0x08, //     #  
+	0x00, //        
+	0x00, //        
+	0x00, //        
+	0x00, //        
+	0x00, //        
+	0x00, //        
+	0x00, //        
+	0x00, //        
+	0x00, //        
+
+	// @780 'a' (7 pixels wide)
+	0x00, //        
+	0x00, //        
+	0x00, //        
+	0x38, //   ###  
+	0x44, //  #   # 
+	0x3C, //   #### 
+	0x44, //  #   # 
+	0x44, //  #   # 
+	0x3E, //   #####
+	0x00, //        
+	0x00, //        
+	0x00, //        
+
+	// @792 'b' (7 pixels wide)
+	0x00, //        
+	0xC0, // ##     
+	0x40, //  #     
+	0x58, //  # ##  
+	0x64, //  ##  # 
+	0x44, //  #   # 
+	0x44, //  #   # 
+	0x44, //  #   # 
+	0xF8, // #####  
+	0x00, //        
+	0x00, //        
+	0x00, //        
+
+	// @804 'c' (7 pixels wide)
+	0x00, //        
+	0x00, //        
+	0x00, //        
+	0x3C, //   #### 
+	0x44, //  #   # 
+	0x40, //  #     
+	0x40, //  #     
+	0x44, //  #   # 
+	0x38, //   ###  
+	0x00, //        
+	0x00, //        
+	0x00, //        
+
+	// @816 'd' (7 pixels wide)
+	0x00, //        
+	0x0C, //     ## 
+	0x04, //      # 
+	0x34, //   ## # 
+	0x4C, //  #  ## 
+	0x44, //  #   # 
+	0x44, //  #   # 
+	0x44, //  #   # 
+	0x3E, //   #####
+	0x00, //        
+	0x00, //        
+	0x00, //        
+
+	// @828 'e' (7 pixels wide)
+	0x00, //        
+	0x00, //        
+	0x00, //        
+	0x38, //   ###  
+	0x44, //  #   # 
+	0x7C, //  ##### 
+	0x40, //  #     
+	0x40, //  #     
+	0x3C, //   #### 
+	0x00, //        
+	0x00, //        
+	0x00, //        
+
+	// @840 'f' (7 pixels wide)
+	0x00, //        
+	0x1C, //    ### 
+	0x20, //   #    
+	0x7C, //  ##### 
+	0x20, //   #    
+	0x20, //   #    
+	0x20, //   #    
+	0x20, //   #    
+	0x7C, //  ##### 
+	0x00, //        
+	0x00, //        
+	0x00, //        
+
+	// @852 'g' (7 pixels wide)
+	0x00, //        
+	0x00, //        
+	0x00, //        
+	0x36, //   ## ##
+	0x4C, //  #  ## 
+	0x44, //  #   # 
+	0x44, //  #   # 
+	0x44, //  #   # 
+	0x3C, //   #### 
+	0x04, //      # 
+	0x38, //   ###  
+	0x00, //        
+
+	// @864 'h' (7 pixels wide)
+	0x00, //        
+	0xC0, // ##     
+	0x40, //  #     
+	0x58, //  # ##  
+	0x64, //  ##  # 
+	0x44, //  #   # 
+	0x44, //  #   # 
+	0x44, //  #   # 
+	0xEE, // ### ###
+	0x00, //        
+	0x00, //        
+	0x00, //        
+
+	// @876 'i' (7 pixels wide)
+	0x00, //        
+	0x10, //    #   
+	0x00, //        
+	0x70, //  ###   
+	0x10, //    #   
+	0x10, //    #   
+	0x10, //    #   
+	0x10, //    #   
+	0x7C, //  ##### 
+	0x00, //        
+	0x00, //        
+	0x00, //        
+
+	// @888 'j' (7 pixels wide)
+	0x00, //        
+	0x10, //    #   
+	0x00, //        
+	0x78, //  ####  
+	0x08, //     #  
+	0x08, //     #  
+	0x08, //     #  
+	0x08, //     #  
+	0x08, //     #  
+	0x08, //     #  
+	0x70, //  ###   
+	0x00, //        
+
+	// @900 'k' (7 pixels wide)
+	0x00, //        
+	0xC0, // ##     
+	0x40, //  #     
+	0x5C, //  # ### 
+	0x48, //  #  #  
+	0x70, //  ###   
+	0x50, //  # #   
+	0x48, //  #  #  
+	0xDC, // ## ### 
+	0x00, //        
+	0x00, //        
+	0x00, //        
+
+	// @912 'l' (7 pixels wide)
+	0x00, //        
+	0x30, //   ##   
+	0x10, //    #   
+	0x10, //    #   
+	0x10, //    #   
+	0x10, //    #   
+	0x10, //    #   
+	0x10, //    #   
+	0x7C, //  ##### 
+	0x00, //        
+	0x00, //        
+	0x00, //        
+
+	// @924 'm' (7 pixels wide)
+	0x00, //        
+	0x00, //        
+	0x00, //        
+	0xE8, // ### #  
+	0x54, //  # # # 
+	0x54, //  # # # 
+	0x54, //  # # # 
+	0x54, //  # # # 
+	0xFE, // #######
+	0x00, //        
+	0x00, //        
+	0x00, //        
+
+	// @936 'n' (7 pixels wide)
+	0x00, //        
+	0x00, //        
+	0x00, //        
+	0xD8, // ## ##  
+	0x64, //  ##  # 
+	0x44, //  #   # 
+	0x44, //  #   # 
+	0x44, //  #   # 
+	0xEE, // ### ###
+	0x00, //        
+	0x00, //        
+	0x00, //        
+
+	// @948 'o' (7 pixels wide)
+	0x00, //        
+	0x00, //        
+	0x00, //        
+	0x38, //   ###  
+	0x44, //  #   # 
+	0x44, //  #   # 
+	0x44, //  #   # 
+	0x44, //  #   # 
+	0x38, //   ###  
+	0x00, //        
+	0x00, //        
+	0x00, //        
+
+	// @960 'p' (7 pixels wide)
+	0x00, //        
+	0x00, //        
+	0x00, //        
+	0xD8, // ## ##  
+	0x64, //  ##  # 
+	0x44, //  #   # 
+	0x44, //  #   # 
+	0x44, //  #   # 
+	0x78, //  ####  
+	0x40, //  #     
+	0xE0, // ###    
+	0x00, //        
+
+	// @972 'q' (7 pixels wide)
+	0x00, //        
+	0x00, //        
+	0x00, //        
+	0x36, //   ## ##
+	0x4C, //  #  ## 
+	0x44, //  #   # 
+	0x44, //  #   # 
+	0x44, //  #   # 
+	0x3C, //   #### 
+	0x04, //      # 
+	0x0E, //     ###
+	0x00, //        
+
+	// @984 'r' (7 pixels wide)
+	0x00, //        
+	0x00, //        
+	0x00, //        
+	0x6C, //  ## ## 
+	0x30, //   ##   
+	0x20, //   #    
+	0x20, //   #    
+	0x20, //   #    
+	0x7C, //  ##### 
+	0x00, //        
+	0x00, //        
+	0x00, //        
+
+	// @996 's' (7 pixels wide)
+	0x00, //        
+	0x00, //        
+	0x00, //        
+	0x3C, //   #### 
+	0x44, //  #   # 
+	0x38, //   ###  
+	0x04, //      # 
+	0x44, //  #   # 
+	0x78, //  ####  
+	0x00, //        
+	0x00, //        
+	0x00, //        
+
+	// @1008 't' (7 pixels wide)
+	0x00, //        
+	0x00, //        
+	0x20, //   #    
+	0x7C, //  ##### 
+	0x20, //   #    
+	0x20, //   #    
+	0x20, //   #    
+	0x22, //   #   #
+	0x1C, //    ### 
+	0x00, //        
+	0x00, //        
+	0x00, //        
+
+	// @1020 'u' (7 pixels wide)
+	0x00, //        
+	0x00, //        
+	0x00, //        
+	0xCC, // ##  ## 
+	0x44, //  #   # 
+	0x44, //  #   # 
+	0x44, //  #   # 
+	0x4C, //  #  ## 
+	0x36, //   ## ##
+	0x00, //        
+	0x00, //        
+	0x00, //        
+
+	// @1032 'v' (7 pixels wide)
+	0x00, //        
+	0x00, //        
+	0x00, //        
+	0xEE, // ### ###
+	0x44, //  #   # 
+	0x44, //  #   # 
+	0x28, //   # #  
+	0x28, //   # #  
+	0x10, //    #   
+	0x00, //        
+	0x00, //        
+	0x00, //        
+
+	// @1044 'w' (7 pixels wide)
+	0x00, //        
+	0x00, //        
+	0x00, //        
+	0xEE, // ### ###
+	0x44, //  #   # 
+	0x54, //  # # # 
+	0x54, //  # # # 
+	0x54, //  # # # 
+	0x28, //   # #  
+	0x00, //        
+	0x00, //        
+	0x00, //        
+
+	// @1056 'x' (7 pixels wide)
+	0x00, //        
+	0x00, //        
+	0x00, //        
+	0xCC, // ##  ## 
+	0x48, //  #  #  
+	0x30, //   ##   
+	0x30, //   ##   
+	0x48, //  #  #  
+	0xCC, // ##  ## 
+	0x00, //        
+	0x00, //        
+	0x00, //        
+
+	// @1068 'y' (7 pixels wide)
+	0x00, //        
+	0x00, //        
+	0x00, //        
+	0xEE, // ### ###
+	0x44, //  #   # 
+	0x24, //   #  # 
+	0x28, //   # #  
+	0x18, //    ##  
+	0x10, //    #   
+	0x10, //    #   
+	0x78, //  ####  
+	0x00, //        
+
+	// @1080 'z' (7 pixels wide)
+	0x00, //        
+	0x00, //        
+	0x00, //        
+	0x7C, //  ##### 
+	0x48, //  #  #  
+	0x10, //    #   
+	0x20, //   #    
+	0x44, //  #   # 
+	0x7C, //  ##### 
+	0x00, //        
+	0x00, //        
+	0x00, //        
+
+	// @1092 '{' (7 pixels wide)
+	0x00, //        
+	0x08, //     #  
+	0x10, //    #   
+	0x10, //    #   
+	0x10, //    #   
+	0x10, //    #   
+	0x20, //   #    
+	0x10, //    #   
+	0x10, //    #   
+	0x10, //    #   
+	0x08, //     #  
+	0x00, //        
+
+	// @1104 '|' (7 pixels wide)
+	0x00, //        
+	0x10, //    #   
+	0x10, //    #   
+	0x10, //    #   
+	0x10, //    #   
+	0x10, //    #   
+	0x10, //    #   
+	0x10, //    #   
+	0x10, //    #   
+	0x10, //    #   
+	0x00, //        
+	0x00, //        
+
+	// @1116 '}' (7 pixels wide)
+	0x00, //        
+	0x20, //   #    
+	0x10, //    #   
+	0x10, //    #   
+	0x10, //    #   
+	0x10, //    #   
+	0x08, //     #  
+	0x10, //    #   
+	0x10, //    #   
+	0x10, //    #   
+	0x20, //   #    
+	0x00, //        
+
+	// @1128 '~' (7 pixels wide)
+	0x00, //        
+	0x00, //        
+	0x00, //        
+	0x00, //        
+	0x00, //        
+	0x24, //   #  # 
+	0x58, //  # ##  
+	0x00, //        
+	0x00, //        
+	0x00, //        
+	0x00, //        
+	0x00, //        
+};
+
+sFONT Font12 = {
+  Font12_Table,
+  7, /* Width */
+  12, /* Height */
+};
+
+/**
+  * @}
+  */ 
+
+
+/** @defgroup FONTS_Private_Function_Prototypes
+  * @{
+  */ 
+/**
+  * @}
+  */ 
+
+
+/** @defgroup FONTS_Private_Functions
+  * @{
+  */
+    
+/**
+  * @}
+  */
+  
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */  
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Utilities/Fonts/font16.c b/Utilities/Fonts/font16.c
new file mode 100644
index 0000000..3c0e189
--- /dev/null
+++ b/Utilities/Fonts/font16.c
@@ -0,0 +1,1844 @@
+/**
+  ******************************************************************************
+  * @file    font16.c
+  * @author  MCD Application Team
+  * @version V1.0.0
+  * @date    18-February-2014
+  * @brief   This file provides text font16 for STM32xx-EVAL's LCD driver. 
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "fonts.h"
+
+/** @addtogroup Utilities
+  * @{
+  */
+  
+/** @addtogroup STM32_EVAL
+  * @{
+  */ 
+
+/** @addtogroup Common
+  * @{
+  */
+
+/** @addtogroup FONTS
+  * @brief      This file provides text font16 for STM32xx-EVAL's LCD driver.
+  * @{
+  */  
+
+/** @defgroup FONTS_Private_Types
+  * @{
+  */ 
+/**
+  * @}
+  */ 
+
+
+/** @defgroup FONTS_Private_Defines
+  * @{
+  */
+/**
+  * @}
+  */ 
+
+
+/** @defgroup FONTS_Private_Macros
+  * @{
+  */
+/**
+  * @}
+  */ 
+  
+
+/** @defgroup FONTS_Private_Variables
+  * @{
+  */
+// 
+//  Font data for Courier New 12pt
+// 
+
+const uint8_t Font16_Table[] = 
+{
+	// @0 ' ' (11 pixels wide)
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+
+	// @32 '!' (11 pixels wide)
+	0x00, 0x00, //            
+	0x0C, 0x00, //     ##     
+	0x0C, 0x00, //     ##     
+	0x0C, 0x00, //     ##     
+	0x0C, 0x00, //     ##     
+	0x0C, 0x00, //     ##     
+	0x0C, 0x00, //     ##     
+	0x0C, 0x00, //     ##     
+	0x0C, 0x00, //     ##     
+	0x00, 0x00, //            
+	0x0C, 0x00, //     ##     
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+
+	// @64 '"' (11 pixels wide)
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x1D, 0xC0, //    ### ### 
+	0x1D, 0xC0, //    ### ### 
+	0x08, 0x80, //     #   #  
+	0x08, 0x80, //     #   #  
+	0x08, 0x80, //     #   #  
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+
+	// @96 '#' (11 pixels wide)
+	0x00, 0x00, //            
+	0x0D, 0x80, //     ## ##  
+	0x0D, 0x80, //     ## ##  
+	0x0D, 0x80, //     ## ##  
+	0x0D, 0x80, //     ## ##  
+	0x3F, 0xC0, //   ######## 
+	0x1B, 0x00, //    ## ##   
+	0x3F, 0xC0, //   ######## 
+	0x1B, 0x00, //    ## ##   
+	0x1B, 0x00, //    ## ##   
+	0x1B, 0x00, //    ## ##   
+	0x1B, 0x00, //    ## ##   
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+
+	// @128 '$' (11 pixels wide)
+	0x04, 0x00, //      #     
+	0x1F, 0x80, //    ######  
+	0x31, 0x80, //   ##   ##  
+	0x31, 0x80, //   ##   ##  
+	0x38, 0x00, //   ###      
+	0x1E, 0x00, //    ####    
+	0x0F, 0x00, //     ####   
+	0x03, 0x80, //       ###  
+	0x31, 0x80, //   ##   ##  
+	0x31, 0x80, //   ##   ##  
+	0x3F, 0x00, //   ######   
+	0x04, 0x00, //      #     
+	0x04, 0x00, //      #     
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+
+	// @160 '%' (11 pixels wide)
+	0x00, 0x00, //            
+	0x18, 0x00, //    ##      
+	0x24, 0x00, //   #  #     
+	0x24, 0x00, //   #  #     
+	0x18, 0xC0, //    ##   ## 
+	0x07, 0x80, //      ####  
+	0x1E, 0x00, //    ####    
+	0x31, 0x80, //   ##   ##  
+	0x02, 0x40, //       #  # 
+	0x02, 0x40, //       #  # 
+	0x01, 0x80, //        ##  
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+
+	// @192 '&' (11 pixels wide)
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x0F, 0x00, //     ####   
+	0x18, 0x00, //    ##      
+	0x18, 0x00, //    ##      
+	0x18, 0x00, //    ##      
+	0x0C, 0x00, //     ##     
+	0x1D, 0x80, //    ### ##  
+	0x37, 0x00, //   ## ###   
+	0x33, 0x00, //   ##  ##   
+	0x1D, 0x80, //    ### ##  
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+
+	// @224 ''' (11 pixels wide)
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x07, 0x00, //      ###   
+	0x07, 0x00, //      ###   
+	0x02, 0x00, //       #    
+	0x02, 0x00, //       #    
+	0x02, 0x00, //       #    
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+
+	// @256 '(' (11 pixels wide)
+	0x00, 0x00, //            
+	0x03, 0x00, //       ##   
+	0x03, 0x00, //       ##   
+	0x06, 0x00, //      ##    
+	0x0E, 0x00, //     ###    
+	0x0C, 0x00, //     ##     
+	0x0C, 0x00, //     ##     
+	0x0C, 0x00, //     ##     
+	0x0C, 0x00, //     ##     
+	0x0E, 0x00, //     ###    
+	0x06, 0x00, //      ##    
+	0x03, 0x00, //       ##   
+	0x03, 0x00, //       ##   
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+
+	// @288 ')' (11 pixels wide)
+	0x00, 0x00, //            
+	0x18, 0x00, //    ##      
+	0x18, 0x00, //    ##      
+	0x0C, 0x00, //     ##     
+	0x06, 0x00, //      ##    
+	0x06, 0x00, //      ##    
+	0x06, 0x00, //      ##    
+	0x06, 0x00, //      ##    
+	0x06, 0x00, //      ##    
+	0x06, 0x00, //      ##    
+	0x0C, 0x00, //     ##     
+	0x1C, 0x00, //    ###     
+	0x18, 0x00, //    ##      
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+
+	// @320 '*' (11 pixels wide)
+	0x00, 0x00, //            
+	0x06, 0x00, //      ##    
+	0x06, 0x00, //      ##    
+	0x3F, 0xC0, //   ######## 
+	0x3F, 0xC0, //   ######## 
+	0x0F, 0x00, //     ####   
+	0x1F, 0x80, //    ######  
+	0x19, 0x80, //    ##  ##  
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+
+	// @352 '+' (11 pixels wide)
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x04, 0x00, //      #     
+	0x04, 0x00, //      #     
+	0x04, 0x00, //      #     
+	0x3F, 0x80, //   #######  
+	0x04, 0x00, //      #     
+	0x04, 0x00, //      #     
+	0x04, 0x00, //      #     
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+
+	// @384 ',' (11 pixels wide)
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x06, 0x00, //      ##    
+	0x04, 0x00, //      #     
+	0x0C, 0x00, //     ##     
+	0x08, 0x00, //     #      
+	0x08, 0x00, //     #      
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+
+	// @416 '-' (11 pixels wide)
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x3F, 0x80, //   #######  
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+
+	// @448 '.' (11 pixels wide)
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x0C, 0x00, //     ##     
+	0x0C, 0x00, //     ##     
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+
+	// @480 '/' (11 pixels wide)
+	0x00, 0xC0, //         ## 
+	0x00, 0xC0, //         ## 
+	0x01, 0x80, //        ##  
+	0x01, 0x80, //        ##  
+	0x03, 0x00, //       ##   
+	0x03, 0x00, //       ##   
+	0x06, 0x00, //      ##    
+	0x0C, 0x00, //     ##     
+	0x0C, 0x00, //     ##     
+	0x18, 0x00, //    ##      
+	0x18, 0x00, //    ##      
+	0x30, 0x00, //   ##       
+	0x30, 0x00, //   ##       
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+
+	// @512 '0' (11 pixels wide)
+	0x00, 0x00, //            
+	0x0E, 0x00, //     ###    
+	0x1B, 0x00, //    ## ##   
+	0x31, 0x80, //   ##   ##  
+	0x31, 0x80, //   ##   ##  
+	0x31, 0x80, //   ##   ##  
+	0x31, 0x80, //   ##   ##  
+	0x31, 0x80, //   ##   ##  
+	0x31, 0x80, //   ##   ##  
+	0x1B, 0x00, //    ## ##   
+	0x0E, 0x00, //     ###    
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+
+	// @544 '1' (11 pixels wide)
+	0x00, 0x00, //            
+	0x06, 0x00, //      ##    
+	0x3E, 0x00, //   #####    
+	0x06, 0x00, //      ##    
+	0x06, 0x00, //      ##    
+	0x06, 0x00, //      ##    
+	0x06, 0x00, //      ##    
+	0x06, 0x00, //      ##    
+	0x06, 0x00, //      ##    
+	0x06, 0x00, //      ##    
+	0x3F, 0xC0, //   ######## 
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+
+	// @576 '2' (11 pixels wide)
+	0x00, 0x00, //            
+	0x0F, 0x00, //     ####   
+	0x19, 0x80, //    ##  ##  
+	0x31, 0x80, //   ##   ##  
+	0x31, 0x80, //   ##   ##  
+	0x03, 0x00, //       ##   
+	0x06, 0x00, //      ##    
+	0x0C, 0x00, //     ##     
+	0x18, 0x00, //    ##      
+	0x30, 0x00, //   ##       
+	0x3F, 0x80, //   #######  
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+
+	// @608 '3' (11 pixels wide)
+	0x00, 0x00, //            
+	0x3F, 0x00, //   ######   
+	0x61, 0x80, //  ##    ##  
+	0x01, 0x80, //        ##  
+	0x03, 0x00, //       ##   
+	0x1F, 0x00, //    #####   
+	0x03, 0x80, //       ###  
+	0x01, 0x80, //        ##  
+	0x01, 0x80, //        ##  
+	0x61, 0x80, //  ##    ##  
+	0x3F, 0x00, //   ######   
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+
+	// @640 '4' (11 pixels wide)
+	0x00, 0x00, //            
+	0x07, 0x00, //      ###   
+	0x07, 0x00, //      ###   
+	0x0F, 0x00, //     ####   
+	0x0B, 0x00, //     # ##   
+	0x1B, 0x00, //    ## ##   
+	0x13, 0x00, //    #  ##   
+	0x33, 0x00, //   ##  ##   
+	0x3F, 0x80, //   #######  
+	0x03, 0x00, //       ##   
+	0x0F, 0x80, //     #####  
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+
+	// @672 '5' (11 pixels wide)
+	0x00, 0x00, //            
+	0x1F, 0x80, //    ######  
+	0x18, 0x00, //    ##      
+	0x18, 0x00, //    ##      
+	0x18, 0x00, //    ##      
+	0x1F, 0x00, //    #####   
+	0x11, 0x80, //    #   ##  
+	0x01, 0x80, //        ##  
+	0x01, 0x80, //        ##  
+	0x21, 0x80, //   #    ##  
+	0x1F, 0x00, //    #####   
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+
+	// @704 '6' (11 pixels wide)
+	0x00, 0x00, //            
+	0x07, 0x80, //      ####  
+	0x1C, 0x00, //    ###     
+	0x18, 0x00, //    ##      
+	0x30, 0x00, //   ##       
+	0x37, 0x00, //   ## ###   
+	0x39, 0x80, //   ###  ##  
+	0x31, 0x80, //   ##   ##  
+	0x31, 0x80, //   ##   ##  
+	0x19, 0x80, //    ##  ##  
+	0x0F, 0x00, //     ####   
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+
+	// @736 '7' (11 pixels wide)
+	0x00, 0x00, //            
+	0x7F, 0x00, //  #######   
+	0x43, 0x00, //  #    ##   
+	0x03, 0x00, //       ##   
+	0x06, 0x00, //      ##    
+	0x06, 0x00, //      ##    
+	0x06, 0x00, //      ##    
+	0x06, 0x00, //      ##    
+	0x0C, 0x00, //     ##     
+	0x0C, 0x00, //     ##     
+	0x0C, 0x00, //     ##     
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+
+	// @768 '8' (11 pixels wide)
+	0x00, 0x00, //            
+	0x1F, 0x00, //    #####   
+	0x31, 0x80, //   ##   ##  
+	0x31, 0x80, //   ##   ##  
+	0x31, 0x80, //   ##   ##  
+	0x1F, 0x00, //    #####   
+	0x31, 0x80, //   ##   ##  
+	0x31, 0x80, //   ##   ##  
+	0x31, 0x80, //   ##   ##  
+	0x31, 0x80, //   ##   ##  
+	0x1F, 0x00, //    #####   
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+
+	// @800 '9' (11 pixels wide)
+	0x00, 0x00, //            
+	0x1E, 0x00, //    ####    
+	0x33, 0x00, //   ##  ##   
+	0x31, 0x80, //   ##   ##  
+	0x31, 0x80, //   ##   ##  
+	0x33, 0x80, //   ##  ###  
+	0x1D, 0x80, //    ### ##  
+	0x01, 0x80, //        ##  
+	0x03, 0x00, //       ##   
+	0x07, 0x00, //      ###   
+	0x3C, 0x00, //   ####     
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+
+	// @832 ':' (11 pixels wide)
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x0C, 0x00, //     ##     
+	0x0C, 0x00, //     ##     
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x0C, 0x00, //     ##     
+	0x0C, 0x00, //     ##     
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+
+	// @864 ';' (11 pixels wide)
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x03, 0x00, //       ##   
+	0x03, 0x00, //       ##   
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x06, 0x00, //      ##    
+	0x04, 0x00, //      #     
+	0x08, 0x00, //     #      
+	0x08, 0x00, //     #      
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+
+	// @896 '<' (11 pixels wide)
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0xC0, //         ## 
+	0x03, 0x00, //       ##   
+	0x04, 0x00, //      #     
+	0x18, 0x00, //    ##      
+	0x60, 0x00, //  ##        
+	0x18, 0x00, //    ##      
+	0x04, 0x00, //      #     
+	0x03, 0x00, //       ##   
+	0x00, 0xC0, //         ## 
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+
+	// @928 '=' (11 pixels wide)
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x7F, 0xC0, //  ######### 
+	0x00, 0x00, //            
+	0x7F, 0xC0, //  ######### 
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+
+	// @960 '>' (11 pixels wide)
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x60, 0x00, //  ##        
+	0x18, 0x00, //    ##      
+	0x04, 0x00, //      #     
+	0x03, 0x00, //       ##   
+	0x00, 0xC0, //         ## 
+	0x03, 0x00, //       ##   
+	0x04, 0x00, //      #     
+	0x18, 0x00, //    ##      
+	0x60, 0x00, //  ##        
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+
+	// @992 '?' (11 pixels wide)
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x1F, 0x00, //    #####   
+	0x31, 0x80, //   ##   ##  
+	0x31, 0x80, //   ##   ##  
+	0x01, 0x80, //        ##  
+	0x07, 0x00, //      ###   
+	0x0C, 0x00, //     ##     
+	0x0C, 0x00, //     ##     
+	0x00, 0x00, //            
+	0x0C, 0x00, //     ##     
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+
+	// @1024 '@' (11 pixels wide)
+	0x00, 0x00, //            
+	0x0E, 0x00, //     ###    
+	0x11, 0x00, //    #   #   
+	0x21, 0x00, //   #    #   
+	0x21, 0x00, //   #    #   
+	0x27, 0x00, //   #  ###   
+	0x29, 0x00, //   # #  #   
+	0x29, 0x00, //   # #  #   
+	0x27, 0x00, //   #  ###   
+	0x20, 0x00, //   #        
+	0x11, 0x00, //    #   #   
+	0x0E, 0x00, //     ###    
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+
+	// @1056 'A' (11 pixels wide)
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x3F, 0x00, //   ######   
+	0x0F, 0x00, //     ####   
+	0x09, 0x00, //     #  #   
+	0x19, 0x80, //    ##  ##  
+	0x19, 0x80, //    ##  ##  
+	0x1F, 0x80, //    ######  
+	0x30, 0xC0, //   ##    ## 
+	0x30, 0xC0, //   ##    ## 
+	0x79, 0xE0, //  ####  ####
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+
+	// @1088 'B' (11 pixels wide)
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x7F, 0x00, //  #######   
+	0x31, 0x80, //   ##   ##  
+	0x31, 0x80, //   ##   ##  
+	0x31, 0x80, //   ##   ##  
+	0x3F, 0x00, //   ######   
+	0x31, 0x80, //   ##   ##  
+	0x31, 0x80, //   ##   ##  
+	0x31, 0x80, //   ##   ##  
+	0x7F, 0x00, //  #######   
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+
+	// @1120 'C' (11 pixels wide)
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x1F, 0x40, //    ##### # 
+	0x30, 0xC0, //   ##    ## 
+	0x60, 0x40, //  ##      # 
+	0x60, 0x00, //  ##        
+	0x60, 0x00, //  ##        
+	0x60, 0x00, //  ##        
+	0x60, 0x40, //  ##      # 
+	0x30, 0x80, //   ##    #  
+	0x1F, 0x00, //    #####   
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+
+	// @1152 'D' (11 pixels wide)
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x7F, 0x00, //  #######   
+	0x31, 0x80, //   ##   ##  
+	0x30, 0xC0, //   ##    ## 
+	0x30, 0xC0, //   ##    ## 
+	0x30, 0xC0, //   ##    ## 
+	0x30, 0xC0, //   ##    ## 
+	0x30, 0xC0, //   ##    ## 
+	0x31, 0x80, //   ##   ##  
+	0x7F, 0x00, //  #######   
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+
+	// @1184 'E' (11 pixels wide)
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x7F, 0x80, //  ########  
+	0x30, 0x80, //   ##    #  
+	0x30, 0x80, //   ##    #  
+	0x32, 0x00, //   ##  #    
+	0x3E, 0x00, //   #####    
+	0x32, 0x00, //   ##  #    
+	0x30, 0x80, //   ##    #  
+	0x30, 0x80, //   ##    #  
+	0x7F, 0x80, //  ########  
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+
+	// @1216 'F' (11 pixels wide)
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x7F, 0xC0, //  ######### 
+	0x30, 0x40, //   ##     # 
+	0x30, 0x40, //   ##     # 
+	0x32, 0x00, //   ##  #    
+	0x3E, 0x00, //   #####    
+	0x32, 0x00, //   ##  #    
+	0x30, 0x00, //   ##       
+	0x30, 0x00, //   ##       
+	0x7C, 0x00, //  #####     
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+
+	// @1248 'G' (11 pixels wide)
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x1E, 0x80, //    #### #  
+	0x31, 0x80, //   ##   ##  
+	0x60, 0x80, //  ##     #  
+	0x60, 0x00, //  ##        
+	0x60, 0x00, //  ##        
+	0x67, 0xC0, //  ##  ##### 
+	0x61, 0x80, //  ##    ##  
+	0x31, 0x80, //   ##   ##  
+	0x1F, 0x00, //    #####   
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+
+	// @1280 'H' (11 pixels wide)
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x7B, 0xC0, //  #### #### 
+	0x31, 0x80, //   ##   ##  
+	0x31, 0x80, //   ##   ##  
+	0x31, 0x80, //   ##   ##  
+	0x3F, 0x80, //   #######  
+	0x31, 0x80, //   ##   ##  
+	0x31, 0x80, //   ##   ##  
+	0x31, 0x80, //   ##   ##  
+	0x7B, 0xC0, //  #### #### 
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+
+	// @1312 'I' (11 pixels wide)
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x3F, 0xC0, //   ######## 
+	0x06, 0x00, //      ##    
+	0x06, 0x00, //      ##    
+	0x06, 0x00, //      ##    
+	0x06, 0x00, //      ##    
+	0x06, 0x00, //      ##    
+	0x06, 0x00, //      ##    
+	0x06, 0x00, //      ##    
+	0x3F, 0xC0, //   ######## 
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+
+	// @1344 'J' (11 pixels wide)
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x1F, 0xC0, //    ####### 
+	0x03, 0x00, //       ##   
+	0x03, 0x00, //       ##   
+	0x03, 0x00, //       ##   
+	0x03, 0x00, //       ##   
+	0x63, 0x00, //  ##   ##   
+	0x63, 0x00, //  ##   ##   
+	0x63, 0x00, //  ##   ##   
+	0x3E, 0x00, //   #####    
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+
+	// @1376 'K' (11 pixels wide)
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x7B, 0xC0, //  #### #### 
+	0x31, 0x80, //   ##   ##  
+	0x33, 0x00, //   ##  ##   
+	0x36, 0x00, //   ## ##    
+	0x3C, 0x00, //   ####     
+	0x3E, 0x00, //   #####    
+	0x33, 0x00, //   ##  ##   
+	0x31, 0x80, //   ##   ##  
+	0x79, 0xC0, //  ####  ### 
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+
+	// @1408 'L' (11 pixels wide)
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x7E, 0x00, //  ######    
+	0x18, 0x00, //    ##      
+	0x18, 0x00, //    ##      
+	0x18, 0x00, //    ##      
+	0x18, 0x00, //    ##      
+	0x18, 0x40, //    ##    # 
+	0x18, 0x40, //    ##    # 
+	0x18, 0x40, //    ##    # 
+	0x7F, 0xC0, //  ######### 
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+
+	// @1440 'M' (11 pixels wide)
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0xE0, 0xE0, // ###     ###
+	0x60, 0xC0, //  ##     ## 
+	0x71, 0xC0, //  ###   ### 
+	0x7B, 0xC0, //  #### #### 
+	0x6A, 0xC0, //  ## # # ## 
+	0x6E, 0xC0, //  ## ### ## 
+	0x64, 0xC0, //  ##  #  ## 
+	0x60, 0xC0, //  ##     ## 
+	0xFB, 0xE0, // ##### #####
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+
+	// @1472 'N' (11 pixels wide)
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x73, 0xC0, //  ###  #### 
+	0x31, 0x80, //   ##   ##  
+	0x39, 0x80, //   ###  ##  
+	0x3D, 0x80, //   #### ##  
+	0x35, 0x80, //   ## # ##  
+	0x37, 0x80, //   ## ####  
+	0x33, 0x80, //   ##  ###  
+	0x31, 0x80, //   ##   ##  
+	0x79, 0x80, //  ####  ##  
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+
+	// @1504 'O' (11 pixels wide)
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x1F, 0x00, //    #####   
+	0x31, 0x80, //   ##   ##  
+	0x60, 0xC0, //  ##     ## 
+	0x60, 0xC0, //  ##     ## 
+	0x60, 0xC0, //  ##     ## 
+	0x60, 0xC0, //  ##     ## 
+	0x60, 0xC0, //  ##     ## 
+	0x31, 0x80, //   ##   ##  
+	0x1F, 0x00, //    #####   
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+
+	// @1536 'P' (11 pixels wide)
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x7F, 0x00, //  #######   
+	0x31, 0x80, //   ##   ##  
+	0x31, 0x80, //   ##   ##  
+	0x31, 0x80, //   ##   ##  
+	0x31, 0x80, //   ##   ##  
+	0x3F, 0x00, //   ######   
+	0x30, 0x00, //   ##       
+	0x30, 0x00, //   ##       
+	0x7E, 0x00, //  ######    
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+
+	// @1568 'Q' (11 pixels wide)
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x1F, 0x00, //    #####   
+	0x31, 0x80, //   ##   ##  
+	0x60, 0xC0, //  ##     ## 
+	0x60, 0xC0, //  ##     ## 
+	0x60, 0xC0, //  ##     ## 
+	0x60, 0xC0, //  ##     ## 
+	0x60, 0xC0, //  ##     ## 
+	0x31, 0x80, //   ##   ##  
+	0x1F, 0x00, //    #####   
+	0x0C, 0xC0, //     ##  ## 
+	0x1F, 0x80, //    ######  
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+
+	// @1600 'R' (11 pixels wide)
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x7F, 0x00, //  #######   
+	0x31, 0x80, //   ##   ##  
+	0x31, 0x80, //   ##   ##  
+	0x31, 0x80, //   ##   ##  
+	0x3E, 0x00, //   #####    
+	0x33, 0x00, //   ##  ##   
+	0x31, 0x80, //   ##   ##  
+	0x31, 0x80, //   ##   ##  
+	0x7C, 0xE0, //  #####  ###
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+
+	// @1632 'S' (11 pixels wide)
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x1F, 0x80, //    ######  
+	0x31, 0x80, //   ##   ##  
+	0x31, 0x80, //   ##   ##  
+	0x38, 0x00, //   ###      
+	0x1F, 0x00, //    #####   
+	0x03, 0x80, //       ###  
+	0x31, 0x80, //   ##   ##  
+	0x31, 0x80, //   ##   ##  
+	0x3F, 0x00, //   ######   
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+
+	// @1664 'T' (11 pixels wide)
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x7F, 0x80, //  ########  
+	0x4C, 0x80, //  #  ##  #  
+	0x4C, 0x80, //  #  ##  #  
+	0x4C, 0x80, //  #  ##  #  
+	0x0C, 0x00, //     ##     
+	0x0C, 0x00, //     ##     
+	0x0C, 0x00, //     ##     
+	0x0C, 0x00, //     ##     
+	0x3F, 0x00, //   ######   
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+
+	// @1696 'U' (11 pixels wide)
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x7B, 0xC0, //  #### #### 
+	0x31, 0x80, //   ##   ##  
+	0x31, 0x80, //   ##   ##  
+	0x31, 0x80, //   ##   ##  
+	0x31, 0x80, //   ##   ##  
+	0x31, 0x80, //   ##   ##  
+	0x31, 0x80, //   ##   ##  
+	0x31, 0x80, //   ##   ##  
+	0x1F, 0x00, //    #####   
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+
+	// @1728 'V' (11 pixels wide)
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x7B, 0xC0, //  #### #### 
+	0x31, 0x80, //   ##   ##  
+	0x31, 0x80, //   ##   ##  
+	0x1B, 0x00, //    ## ##   
+	0x1B, 0x00, //    ## ##   
+	0x1B, 0x00, //    ## ##   
+	0x0A, 0x00, //     # #    
+	0x0E, 0x00, //     ###    
+	0x0E, 0x00, //     ###    
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+
+	// @1760 'W' (11 pixels wide)
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0xFB, 0xE0, // ##### #####
+	0x60, 0xC0, //  ##     ## 
+	0x64, 0xC0, //  ##  #  ## 
+	0x6E, 0xC0, //  ## ### ## 
+	0x6E, 0xC0, //  ## ### ## 
+	0x2A, 0x80, //   # # # #  
+	0x3B, 0x80, //   ### ###  
+	0x3B, 0x80, //   ### ###  
+	0x31, 0x80, //   ##   ##  
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+
+	// @1792 'X' (11 pixels wide)
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x7B, 0xC0, //  #### #### 
+	0x31, 0x80, //   ##   ##  
+	0x1B, 0x00, //    ## ##   
+	0x0E, 0x00, //     ###    
+	0x0E, 0x00, //     ###    
+	0x0E, 0x00, //     ###    
+	0x1B, 0x00, //    ## ##   
+	0x31, 0x80, //   ##   ##  
+	0x7B, 0xC0, //  #### #### 
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+
+	// @1824 'Y' (11 pixels wide)
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x79, 0xE0, //  ####  ####
+	0x30, 0xC0, //   ##    ## 
+	0x19, 0x80, //    ##  ##  
+	0x0F, 0x00, //     ####   
+	0x06, 0x00, //      ##    
+	0x06, 0x00, //      ##    
+	0x06, 0x00, //      ##    
+	0x06, 0x00, //      ##    
+	0x1F, 0x80, //    ######  
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+
+	// @1856 'Z' (11 pixels wide)
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x3F, 0x80, //   #######  
+	0x21, 0x80, //   #    ##  
+	0x23, 0x00, //   #   ##   
+	0x06, 0x00, //      ##    
+	0x04, 0x00, //      #     
+	0x0C, 0x00, //     ##     
+	0x18, 0x80, //    ##   #  
+	0x30, 0x80, //   ##    #  
+	0x3F, 0x80, //   #######  
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+
+	// @1888 '[' (11 pixels wide)
+	0x00, 0x00, //            
+	0x07, 0x80, //      ####  
+	0x06, 0x00, //      ##    
+	0x06, 0x00, //      ##    
+	0x06, 0x00, //      ##    
+	0x06, 0x00, //      ##    
+	0x06, 0x00, //      ##    
+	0x06, 0x00, //      ##    
+	0x06, 0x00, //      ##    
+	0x06, 0x00, //      ##    
+	0x06, 0x00, //      ##    
+	0x06, 0x00, //      ##    
+	0x07, 0x80, //      ####  
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+
+	// @1920 '\' (11 pixels wide)
+	0x30, 0x00, //   ##       
+	0x30, 0x00, //   ##       
+	0x18, 0x00, //    ##      
+	0x18, 0x00, //    ##      
+	0x0C, 0x00, //     ##     
+	0x0C, 0x00, //     ##     
+	0x06, 0x00, //      ##    
+	0x03, 0x00, //       ##   
+	0x03, 0x00, //       ##   
+	0x01, 0x80, //        ##  
+	0x01, 0x80, //        ##  
+	0x00, 0xC0, //         ## 
+	0x00, 0xC0, //         ## 
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+
+	// @1952 ']' (11 pixels wide)
+	0x00, 0x00, //            
+	0x1E, 0x00, //    ####    
+	0x06, 0x00, //      ##    
+	0x06, 0x00, //      ##    
+	0x06, 0x00, //      ##    
+	0x06, 0x00, //      ##    
+	0x06, 0x00, //      ##    
+	0x06, 0x00, //      ##    
+	0x06, 0x00, //      ##    
+	0x06, 0x00, //      ##    
+	0x06, 0x00, //      ##    
+	0x06, 0x00, //      ##    
+	0x1E, 0x00, //    ####    
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+
+	// @1984 '^' (11 pixels wide)
+	0x04, 0x00, //      #     
+	0x0A, 0x00, //     # #    
+	0x0A, 0x00, //     # #    
+	0x11, 0x00, //    #   #   
+	0x20, 0x80, //   #     #  
+	0x20, 0x80, //   #     #  
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+
+	// @2016 '_' (11 pixels wide)
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0xFF, 0xE0, // ###########
+
+	// @2048 '`' (11 pixels wide)
+	0x08, 0x00, //     #      
+	0x04, 0x00, //      #     
+	0x02, 0x00, //       #    
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+
+	// @2080 'a' (11 pixels wide)
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x1F, 0x00, //    #####   
+	0x01, 0x80, //        ##  
+	0x01, 0x80, //        ##  
+	0x1F, 0x80, //    ######  
+	0x31, 0x80, //   ##   ##  
+	0x33, 0x80, //   ##  ###  
+	0x1D, 0xC0, //    ### ### 
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+
+	// @2112 'b' (11 pixels wide)
+	0x00, 0x00, //            
+	0x70, 0x00, //  ###       
+	0x30, 0x00, //   ##       
+	0x30, 0x00, //   ##       
+	0x37, 0x00, //   ## ###   
+	0x39, 0x80, //   ###  ##  
+	0x30, 0xC0, //   ##    ## 
+	0x30, 0xC0, //   ##    ## 
+	0x30, 0xC0, //   ##    ## 
+	0x39, 0x80, //   ###  ##  
+	0x77, 0x00, //  ### ###   
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+
+	// @2144 'c' (11 pixels wide)
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x1E, 0x80, //    #### #  
+	0x31, 0x80, //   ##   ##  
+	0x60, 0x80, //  ##     #  
+	0x60, 0x00, //  ##        
+	0x60, 0x80, //  ##     #  
+	0x31, 0x80, //   ##   ##  
+	0x1F, 0x00, //    #####   
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+
+	// @2176 'd' (11 pixels wide)
+	0x00, 0x00, //            
+	0x03, 0x80, //       ###  
+	0x01, 0x80, //        ##  
+	0x01, 0x80, //        ##  
+	0x1D, 0x80, //    ### ##  
+	0x33, 0x80, //   ##  ###  
+	0x61, 0x80, //  ##    ##  
+	0x61, 0x80, //  ##    ##  
+	0x61, 0x80, //  ##    ##  
+	0x33, 0x80, //   ##  ###  
+	0x1D, 0xC0, //    ### ### 
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+
+	// @2208 'e' (11 pixels wide)
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x1F, 0x00, //    #####   
+	0x31, 0x80, //   ##   ##  
+	0x60, 0xC0, //  ##     ## 
+	0x7F, 0xC0, //  ######### 
+	0x60, 0x00, //  ##        
+	0x30, 0xC0, //   ##    ## 
+	0x1F, 0x80, //    ######  
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+
+	// @2240 'f' (11 pixels wide)
+	0x00, 0x00, //            
+	0x07, 0xE0, //      ######
+	0x0C, 0x00, //     ##     
+	0x0C, 0x00, //     ##     
+	0x3F, 0x80, //   #######  
+	0x0C, 0x00, //     ##     
+	0x0C, 0x00, //     ##     
+	0x0C, 0x00, //     ##     
+	0x0C, 0x00, //     ##     
+	0x0C, 0x00, //     ##     
+	0x3F, 0x80, //   #######  
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+
+	// @2272 'g' (11 pixels wide)
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x1D, 0xC0, //    ### ### 
+	0x33, 0x80, //   ##  ###  
+	0x61, 0x80, //  ##    ##  
+	0x61, 0x80, //  ##    ##  
+	0x61, 0x80, //  ##    ##  
+	0x33, 0x80, //   ##  ###  
+	0x1D, 0x80, //    ### ##  
+	0x01, 0x80, //        ##  
+	0x01, 0x80, //        ##  
+	0x1F, 0x00, //    #####   
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+
+	// @2304 'h' (11 pixels wide)
+	0x00, 0x00, //            
+	0x70, 0x00, //  ###       
+	0x30, 0x00, //   ##       
+	0x30, 0x00, //   ##       
+	0x37, 0x00, //   ## ###   
+	0x39, 0x80, //   ###  ##  
+	0x31, 0x80, //   ##   ##  
+	0x31, 0x80, //   ##   ##  
+	0x31, 0x80, //   ##   ##  
+	0x31, 0x80, //   ##   ##  
+	0x7B, 0xC0, //  #### #### 
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+
+	// @2336 'i' (11 pixels wide)
+	0x00, 0x00, //            
+	0x06, 0x00, //      ##    
+	0x06, 0x00, //      ##    
+	0x00, 0x00, //            
+	0x1E, 0x00, //    ####    
+	0x06, 0x00, //      ##    
+	0x06, 0x00, //      ##    
+	0x06, 0x00, //      ##    
+	0x06, 0x00, //      ##    
+	0x06, 0x00, //      ##    
+	0x3F, 0xC0, //   ######## 
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+
+	// @2368 'j' (11 pixels wide)
+	0x00, 0x00, //            
+	0x06, 0x00, //      ##    
+	0x06, 0x00, //      ##    
+	0x00, 0x00, //            
+	0x3F, 0x00, //   ######   
+	0x03, 0x00, //       ##   
+	0x03, 0x00, //       ##   
+	0x03, 0x00, //       ##   
+	0x03, 0x00, //       ##   
+	0x03, 0x00, //       ##   
+	0x03, 0x00, //       ##   
+	0x03, 0x00, //       ##   
+	0x03, 0x00, //       ##   
+	0x3E, 0x00, //   #####    
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+
+	// @2400 'k' (11 pixels wide)
+	0x00, 0x00, //            
+	0x70, 0x00, //  ###       
+	0x30, 0x00, //   ##       
+	0x30, 0x00, //   ##       
+	0x37, 0x80, //   ## ####  
+	0x36, 0x00, //   ## ##    
+	0x3C, 0x00, //   ####     
+	0x3C, 0x00, //   ####     
+	0x36, 0x00, //   ## ##    
+	0x33, 0x00, //   ##  ##   
+	0x77, 0xC0, //  ### ##### 
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+
+	// @2432 'l' (11 pixels wide)
+	0x00, 0x00, //            
+	0x1E, 0x00, //    ####    
+	0x06, 0x00, //      ##    
+	0x06, 0x00, //      ##    
+	0x06, 0x00, //      ##    
+	0x06, 0x00, //      ##    
+	0x06, 0x00, //      ##    
+	0x06, 0x00, //      ##    
+	0x06, 0x00, //      ##    
+	0x06, 0x00, //      ##    
+	0x3F, 0xC0, //   ######## 
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+
+	// @2464 'm' (11 pixels wide)
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x7F, 0x80, //  ########  
+	0x36, 0xC0, //   ## ## ## 
+	0x36, 0xC0, //   ## ## ## 
+	0x36, 0xC0, //   ## ## ## 
+	0x36, 0xC0, //   ## ## ## 
+	0x36, 0xC0, //   ## ## ## 
+	0x76, 0xE0, //  ### ## ###
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+
+	// @2496 'n' (11 pixels wide)
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x77, 0x00, //  ### ###   
+	0x39, 0x80, //   ###  ##  
+	0x31, 0x80, //   ##   ##  
+	0x31, 0x80, //   ##   ##  
+	0x31, 0x80, //   ##   ##  
+	0x31, 0x80, //   ##   ##  
+	0x7B, 0xC0, //  #### #### 
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+
+	// @2528 'o' (11 pixels wide)
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x1F, 0x00, //    #####   
+	0x31, 0x80, //   ##   ##  
+	0x60, 0xC0, //  ##     ## 
+	0x60, 0xC0, //  ##     ## 
+	0x60, 0xC0, //  ##     ## 
+	0x31, 0x80, //   ##   ##  
+	0x1F, 0x00, //    #####   
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+
+	// @2560 'p' (11 pixels wide)
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x77, 0x00, //  ### ###   
+	0x39, 0x80, //   ###  ##  
+	0x30, 0xC0, //   ##    ## 
+	0x30, 0xC0, //   ##    ## 
+	0x30, 0xC0, //   ##    ## 
+	0x39, 0x80, //   ###  ##  
+	0x37, 0x00, //   ## ###   
+	0x30, 0x00, //   ##       
+	0x30, 0x00, //   ##       
+	0x7C, 0x00, //  #####     
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+
+	// @2592 'q' (11 pixels wide)
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x1D, 0xC0, //    ### ### 
+	0x33, 0x80, //   ##  ###  
+	0x61, 0x80, //  ##    ##  
+	0x61, 0x80, //  ##    ##  
+	0x61, 0x80, //  ##    ##  
+	0x33, 0x80, //   ##  ###  
+	0x1D, 0x80, //    ### ##  
+	0x01, 0x80, //        ##  
+	0x01, 0x80, //        ##  
+	0x07, 0xC0, //      ##### 
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+
+	// @2624 'r' (11 pixels wide)
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x7B, 0x80, //  #### ###  
+	0x1C, 0xC0, //    ###  ## 
+	0x18, 0x00, //    ##      
+	0x18, 0x00, //    ##      
+	0x18, 0x00, //    ##      
+	0x18, 0x00, //    ##      
+	0x7F, 0x00, //  #######   
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+
+	// @2656 's' (11 pixels wide)
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x1F, 0x80, //    ######  
+	0x31, 0x80, //   ##   ##  
+	0x3C, 0x00, //   ####     
+	0x1F, 0x00, //    #####   
+	0x03, 0x80, //       ###  
+	0x31, 0x80, //   ##   ##  
+	0x3F, 0x00, //   ######   
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+
+	// @2688 't' (11 pixels wide)
+	0x00, 0x00, //            
+	0x18, 0x00, //    ##      
+	0x18, 0x00, //    ##      
+	0x18, 0x00, //    ##      
+	0x7F, 0x00, //  #######   
+	0x18, 0x00, //    ##      
+	0x18, 0x00, //    ##      
+	0x18, 0x00, //    ##      
+	0x18, 0x00, //    ##      
+	0x18, 0x80, //    ##   #  
+	0x0F, 0x00, //     ####   
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+
+	// @2720 'u' (11 pixels wide)
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x73, 0x80, //  ###  ###  
+	0x31, 0x80, //   ##   ##  
+	0x31, 0x80, //   ##   ##  
+	0x31, 0x80, //   ##   ##  
+	0x31, 0x80, //   ##   ##  
+	0x33, 0x80, //   ##  ###  
+	0x1D, 0xC0, //    ### ### 
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+
+	// @2752 'v' (11 pixels wide)
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x7B, 0xC0, //  #### #### 
+	0x31, 0x80, //   ##   ##  
+	0x31, 0x80, //   ##   ##  
+	0x1B, 0x00, //    ## ##   
+	0x1B, 0x00, //    ## ##   
+	0x0E, 0x00, //     ###    
+	0x0E, 0x00, //     ###    
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+
+	// @2784 'w' (11 pixels wide)
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0xF1, 0xE0, // ####   ####
+	0x60, 0xC0, //  ##     ## 
+	0x64, 0xC0, //  ##  #  ## 
+	0x6E, 0xC0, //  ## ### ## 
+	0x3B, 0x80, //   ### ###  
+	0x3B, 0x80, //   ### ###  
+	0x31, 0x80, //   ##   ##  
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+
+	// @2816 'x' (11 pixels wide)
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x7B, 0xC0, //  #### #### 
+	0x1B, 0x00, //    ## ##   
+	0x0E, 0x00, //     ###    
+	0x0E, 0x00, //     ###    
+	0x0E, 0x00, //     ###    
+	0x1B, 0x00, //    ## ##   
+	0x7B, 0xC0, //  #### #### 
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+
+	// @2848 'y' (11 pixels wide)
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x79, 0xE0, //  ####  ####
+	0x30, 0xC0, //   ##    ## 
+	0x19, 0x80, //    ##  ##  
+	0x19, 0x80, //    ##  ##  
+	0x0B, 0x00, //     # ##   
+	0x0F, 0x00, //     ####   
+	0x06, 0x00, //      ##    
+	0x06, 0x00, //      ##    
+	0x0C, 0x00, //     ##     
+	0x3E, 0x00, //   #####    
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+
+	// @2880 'z' (11 pixels wide)
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x3F, 0x80, //   #######  
+	0x21, 0x80, //   #    ##  
+	0x03, 0x00, //       ##   
+	0x0E, 0x00, //     ###    
+	0x18, 0x00, //    ##      
+	0x30, 0x80, //   ##    #  
+	0x3F, 0x80, //   #######  
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+
+	// @2912 '{' (11 pixels wide)
+	0x00, 0x00, //            
+	0x06, 0x00, //      ##    
+	0x0C, 0x00, //     ##     
+	0x0C, 0x00, //     ##     
+	0x0C, 0x00, //     ##     
+	0x0C, 0x00, //     ##     
+	0x0C, 0x00, //     ##     
+	0x18, 0x00, //    ##      
+	0x0C, 0x00, //     ##     
+	0x0C, 0x00, //     ##     
+	0x0C, 0x00, //     ##     
+	0x0C, 0x00, //     ##     
+	0x06, 0x00, //      ##    
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+
+	// @2944 '|' (11 pixels wide)
+	0x00, 0x00, //            
+	0x06, 0x00, //      ##    
+	0x06, 0x00, //      ##    
+	0x06, 0x00, //      ##    
+	0x06, 0x00, //      ##    
+	0x06, 0x00, //      ##    
+	0x06, 0x00, //      ##    
+	0x06, 0x00, //      ##    
+	0x06, 0x00, //      ##    
+	0x06, 0x00, //      ##    
+	0x06, 0x00, //      ##    
+	0x06, 0x00, //      ##    
+	0x06, 0x00, //      ##    
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+
+	// @2976 '}' (11 pixels wide)
+	0x00, 0x00, //            
+	0x0C, 0x00, //     ##     
+	0x06, 0x00, //      ##    
+	0x06, 0x00, //      ##    
+	0x06, 0x00, //      ##    
+	0x06, 0x00, //      ##    
+	0x06, 0x00, //      ##    
+	0x03, 0x00, //       ##   
+	0x06, 0x00, //      ##    
+	0x06, 0x00, //      ##    
+	0x06, 0x00, //      ##    
+	0x06, 0x00, //      ##    
+	0x0C, 0x00, //     ##     
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+
+	// @3008 '~' (11 pixels wide)
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x18, 0x00, //    ##      
+	0x24, 0x80, //   #  #  #  
+	0x03, 0x00, //       ##   
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+	0x00, 0x00, //            
+};
+
+sFONT Font16 = {
+  Font16_Table,
+  11, /* Width */
+  16, /* Height */
+};
+
+/**
+  * @}
+  */ 
+
+
+/** @defgroup FONTS_Private_Function_Prototypes
+  * @{
+  */ 
+/**
+  * @}
+  */ 
+
+
+/** @defgroup FONTS_Private_Functions
+  * @{
+  */
+    
+/**
+  * @}
+  */
+  
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */  
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Utilities/Fonts/font20.c b/Utilities/Fonts/font20.c
new file mode 100644
index 0000000..e9e6afa
--- /dev/null
+++ b/Utilities/Fonts/font20.c
@@ -0,0 +1,2223 @@
+/**
+  ******************************************************************************
+  * @file    font20.c
+  * @author  MCD Application Team
+  * @version V1.0.0
+  * @date    18-February-2014
+  * @brief   This file provides text font20 for STM32xx-EVAL's LCD driver. 
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "fonts.h"
+
+/** @addtogroup Utilities
+  * @{
+  */
+  
+/** @addtogroup STM32_EVAL
+  * @{
+  */ 
+
+/** @addtogroup Common
+  * @{
+  */
+
+/** @addtogroup FONTS
+  * @brief      This file provides text font20 for STM32xx-EVAL's LCD driver.
+  * @{
+  */  
+
+/** @defgroup FONTS_Private_Types
+  * @{
+  */ 
+/**
+  * @}
+  */ 
+
+
+/** @defgroup FONTS_Private_Defines
+  * @{
+  */
+/**
+  * @}
+  */ 
+
+
+/** @defgroup FONTS_Private_Macros
+  * @{
+  */
+/**
+  * @}
+  */ 
+  
+
+/** @defgroup FONTS_Private_Variables
+  * @{
+  */
+
+// Character bitmaps for Courier New 15pt
+const uint8_t Font20_Table[] = 
+{
+	// @0 ' ' (14 pixels wide)
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+
+	// @40 '!' (14 pixels wide)
+	0x00, 0x00, //               
+	0x07, 0x00, //      ###      
+	0x07, 0x00, //      ###      
+	0x07, 0x00, //      ###      
+	0x07, 0x00, //      ###      
+	0x07, 0x00, //      ###      
+	0x07, 0x00, //      ###      
+	0x07, 0x00, //      ###      
+	0x02, 0x00, //       #       
+	0x02, 0x00, //       #       
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x07, 0x00, //      ###      
+	0x07, 0x00, //      ###      
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+
+	// @80 '"' (14 pixels wide)
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x1C, 0xE0, //    ###  ###   
+	0x1C, 0xE0, //    ###  ###   
+	0x1C, 0xE0, //    ###  ###   
+	0x08, 0x40, //     #    #    
+	0x08, 0x40, //     #    #    
+	0x08, 0x40, //     #    #    
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+
+	// @120 '#' (14 pixels wide)
+	0x0C, 0xC0, //     ##  ##    
+	0x0C, 0xC0, //     ##  ##    
+	0x0C, 0xC0, //     ##  ##    
+	0x0C, 0xC0, //     ##  ##    
+	0x0C, 0xC0, //     ##  ##    
+	0x3F, 0xF0, //   ##########  
+	0x3F, 0xF0, //   ##########  
+	0x0C, 0xC0, //     ##  ##    
+	0x0C, 0xC0, //     ##  ##    
+	0x3F, 0xF0, //   ##########  
+	0x3F, 0xF0, //   ##########  
+	0x0C, 0xC0, //     ##  ##    
+	0x0C, 0xC0, //     ##  ##    
+	0x0C, 0xC0, //     ##  ##    
+	0x0C, 0xC0, //     ##  ##    
+	0x0C, 0xC0, //     ##  ##    
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+
+	// @160 '$' (14 pixels wide)
+	0x03, 0x00, //       ##      
+	0x03, 0x00, //       ##      
+	0x07, 0xE0, //      ######   
+	0x0F, 0xE0, //     #######   
+	0x18, 0x60, //    ##    ##   
+	0x18, 0x00, //    ##         
+	0x1F, 0x00, //    #####      
+	0x0F, 0xC0, //     ######    
+	0x00, 0xE0, //         ###   
+	0x18, 0x60, //    ##    ##   
+	0x18, 0x60, //    ##    ##   
+	0x1F, 0xC0, //    #######    
+	0x1F, 0x80, //    ######     
+	0x03, 0x00, //       ##      
+	0x03, 0x00, //       ##      
+	0x03, 0x00, //       ##      
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+
+	// @200 '%' (14 pixels wide)
+	0x00, 0x00, //               
+	0x1C, 0x00, //    ###        
+	0x22, 0x00, //   #   #       
+	0x22, 0x00, //   #   #       
+	0x22, 0x00, //   #   #       
+	0x1C, 0x60, //    ###   ##   
+	0x01, 0xE0, //        ####   
+	0x0F, 0x80, //     #####     
+	0x3C, 0x00, //   ####        
+	0x31, 0xC0, //   ##   ###    
+	0x02, 0x20, //       #   #   
+	0x02, 0x20, //       #   #   
+	0x02, 0x20, //       #   #   
+	0x01, 0xC0, //        ###    
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+
+	// @240 '&' (14 pixels wide)
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x03, 0xE0, //       #####   
+	0x0F, 0xE0, //     #######   
+	0x0C, 0x00, //     ##        
+	0x0C, 0x00, //     ##        
+	0x06, 0x00, //      ##       
+	0x0F, 0x30, //     ####  ##  
+	0x1F, 0xF0, //    #########  
+	0x19, 0xE0, //    ##  ####   
+	0x18, 0xC0, //    ##   ##    
+	0x1F, 0xF0, //    #########  
+	0x07, 0xB0, //      #### ##  
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+
+	// @280 ''' (14 pixels wide)
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x03, 0x80, //       ###     
+	0x03, 0x80, //       ###     
+	0x03, 0x80, //       ###     
+	0x01, 0x00, //        #      
+	0x01, 0x00, //        #      
+	0x01, 0x00, //        #      
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+
+	// @320 '(' (14 pixels wide)
+	0x00, 0x00, //               
+	0x00, 0xC0, //         ##    
+	0x00, 0xC0, //         ##    
+	0x01, 0x80, //        ##     
+	0x01, 0x80, //        ##     
+	0x01, 0x80, //        ##     
+	0x03, 0x00, //       ##      
+	0x03, 0x00, //       ##      
+	0x03, 0x00, //       ##      
+	0x03, 0x00, //       ##      
+	0x03, 0x00, //       ##      
+	0x03, 0x00, //       ##      
+	0x01, 0x80, //        ##     
+	0x01, 0x80, //        ##     
+	0x01, 0x80, //        ##     
+	0x00, 0xC0, //         ##    
+	0x00, 0xC0, //         ##    
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+
+	// @360 ')' (14 pixels wide)
+	0x00, 0x00, //               
+	0x0C, 0x00, //     ##        
+	0x0C, 0x00, //     ##        
+	0x06, 0x00, //      ##       
+	0x06, 0x00, //      ##       
+	0x06, 0x00, //      ##       
+	0x03, 0x00, //       ##      
+	0x03, 0x00, //       ##      
+	0x03, 0x00, //       ##      
+	0x03, 0x00, //       ##      
+	0x03, 0x00, //       ##      
+	0x03, 0x00, //       ##      
+	0x06, 0x00, //      ##       
+	0x06, 0x00, //      ##       
+	0x06, 0x00, //      ##       
+	0x0C, 0x00, //     ##        
+	0x0C, 0x00, //     ##        
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+
+	// @400 '*' (14 pixels wide)
+	0x00, 0x00, //               
+	0x03, 0x00, //       ##      
+	0x03, 0x00, //       ##      
+	0x03, 0x00, //       ##      
+	0x1B, 0x60, //    ## ## ##   
+	0x1F, 0xE0, //    ########   
+	0x07, 0x80, //      ####     
+	0x07, 0x80, //      ####     
+	0x0F, 0xC0, //     ######    
+	0x0C, 0xC0, //     ##  ##    
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+
+	// @440 '+' (14 pixels wide)
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x03, 0x00, //       ##      
+	0x03, 0x00, //       ##      
+	0x03, 0x00, //       ##      
+	0x03, 0x00, //       ##      
+	0x3F, 0xF0, //   ##########  
+	0x3F, 0xF0, //   ##########  
+	0x03, 0x00, //       ##      
+	0x03, 0x00, //       ##      
+	0x03, 0x00, //       ##      
+	0x03, 0x00, //       ##      
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+
+	// @480 ',' (14 pixels wide)
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x03, 0x80, //       ###     
+	0x03, 0x00, //       ##      
+	0x03, 0x00, //       ##      
+	0x06, 0x00, //      ##       
+	0x06, 0x00, //      ##       
+	0x04, 0x00, //      #        
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+
+	// @520 '-' (14 pixels wide)
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x3F, 0xE0, //   #########   
+	0x3F, 0xE0, //   #########   
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+
+	// @560 '.' (14 pixels wide)
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x03, 0x80, //       ###     
+	0x03, 0x80, //       ###     
+	0x03, 0x80, //       ###     
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+
+	// @600 '/' (14 pixels wide)
+	0x00, 0x60, //          ##   
+	0x00, 0x60, //          ##   
+	0x00, 0xC0, //         ##    
+	0x00, 0xC0, //         ##    
+	0x00, 0xC0, //         ##    
+	0x01, 0x80, //        ##     
+	0x01, 0x80, //        ##     
+	0x03, 0x00, //       ##      
+	0x03, 0x00, //       ##      
+	0x06, 0x00, //      ##       
+	0x06, 0x00, //      ##       
+	0x0C, 0x00, //     ##        
+	0x0C, 0x00, //     ##        
+	0x0C, 0x00, //     ##        
+	0x18, 0x00, //    ##         
+	0x18, 0x00, //    ##         
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+
+	// @640 '0' (14 pixels wide)
+	0x00, 0x00, //               
+	0x0F, 0x80, //     #####     
+	0x1F, 0xC0, //    #######    
+	0x18, 0xC0, //    ##   ##    
+	0x30, 0x60, //   ##     ##   
+	0x30, 0x60, //   ##     ##   
+	0x30, 0x60, //   ##     ##   
+	0x30, 0x60, //   ##     ##   
+	0x30, 0x60, //   ##     ##   
+	0x30, 0x60, //   ##     ##   
+	0x30, 0x60, //   ##     ##   
+	0x18, 0xC0, //    ##   ##    
+	0x1F, 0xC0, //    #######    
+	0x0F, 0x80, //     #####     
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+
+	// @680 '1' (14 pixels wide)
+	0x00, 0x00, //               
+	0x03, 0x00, //       ##      
+	0x1F, 0x00, //    #####      
+	0x1F, 0x00, //    #####      
+	0x03, 0x00, //       ##      
+	0x03, 0x00, //       ##      
+	0x03, 0x00, //       ##      
+	0x03, 0x00, //       ##      
+	0x03, 0x00, //       ##      
+	0x03, 0x00, //       ##      
+	0x03, 0x00, //       ##      
+	0x03, 0x00, //       ##      
+	0x1F, 0xE0, //    ########   
+	0x1F, 0xE0, //    ########   
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+
+	// @720 '2' (14 pixels wide)
+	0x00, 0x00, //               
+	0x0F, 0x80, //     #####     
+	0x1F, 0xC0, //    #######    
+	0x38, 0xE0, //   ###   ###   
+	0x30, 0x60, //   ##     ##   
+	0x00, 0x60, //          ##   
+	0x00, 0xC0, //         ##    
+	0x01, 0x80, //        ##     
+	0x03, 0x00, //       ##      
+	0x06, 0x00, //      ##       
+	0x0C, 0x00, //     ##        
+	0x18, 0x00, //    ##         
+	0x3F, 0xE0, //   #########   
+	0x3F, 0xE0, //   #########   
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+
+	// @760 '3' (14 pixels wide)
+	0x00, 0x00, //               
+	0x0F, 0x80, //     #####     
+	0x3F, 0xC0, //   ########    
+	0x30, 0xE0, //   ##    ###   
+	0x00, 0x60, //          ##   
+	0x00, 0xE0, //         ###   
+	0x07, 0xC0, //      #####    
+	0x07, 0xC0, //      #####    
+	0x00, 0xE0, //         ###   
+	0x00, 0x60, //          ##   
+	0x00, 0x60, //          ##   
+	0x60, 0xE0, //  ##     ###   
+	0x7F, 0xC0, //  #########    
+	0x3F, 0x80, //   #######     
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+
+	// @800 '4' (14 pixels wide)
+	0x00, 0x00, //               
+	0x01, 0xC0, //        ###    
+	0x03, 0xC0, //       ####    
+	0x03, 0xC0, //       ####    
+	0x06, 0xC0, //      ## ##    
+	0x0C, 0xC0, //     ##  ##    
+	0x0C, 0xC0, //     ##  ##    
+	0x18, 0xC0, //    ##   ##    
+	0x30, 0xC0, //   ##    ##    
+	0x3F, 0xE0, //   #########   
+	0x3F, 0xE0, //   #########   
+	0x00, 0xC0, //         ##    
+	0x03, 0xE0, //       #####   
+	0x03, 0xE0, //       #####   
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+
+	// @840 '5' (14 pixels wide)
+	0x00, 0x00, //               
+	0x1F, 0xC0, //    #######    
+	0x1F, 0xC0, //    #######    
+	0x18, 0x00, //    ##         
+	0x18, 0x00, //    ##         
+	0x1F, 0x80, //    ######     
+	0x1F, 0xC0, //    #######    
+	0x18, 0xE0, //    ##   ###   
+	0x00, 0x60, //          ##   
+	0x00, 0x60, //          ##   
+	0x00, 0x60, //          ##   
+	0x30, 0xE0, //   ##    ###   
+	0x3F, 0xC0, //   ########    
+	0x1F, 0x80, //    ######     
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+
+	// @880 '6' (14 pixels wide)
+	0x00, 0x00, //               
+	0x03, 0xE0, //       #####   
+	0x0F, 0xE0, //     #######   
+	0x1E, 0x00, //    ####       
+	0x18, 0x00, //    ##         
+	0x38, 0x00, //   ###         
+	0x37, 0x80, //   ## ####     
+	0x3F, 0xC0, //   ########    
+	0x38, 0xE0, //   ###   ###   
+	0x30, 0x60, //   ##     ##   
+	0x30, 0x60, //   ##     ##   
+	0x18, 0xE0, //    ##   ###   
+	0x1F, 0xC0, //    #######    
+	0x07, 0x80, //      ####     
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+
+	// @920 '7' (14 pixels wide)
+	0x00, 0x00, //               
+	0x3F, 0xE0, //   #########   
+	0x3F, 0xE0, //   #########   
+	0x30, 0x60, //   ##     ##   
+	0x00, 0x60, //          ##   
+	0x00, 0xC0, //         ##    
+	0x00, 0xC0, //         ##    
+	0x00, 0xC0, //         ##    
+	0x01, 0x80, //        ##     
+	0x01, 0x80, //        ##     
+	0x01, 0x80, //        ##     
+	0x03, 0x00, //       ##      
+	0x03, 0x00, //       ##      
+	0x03, 0x00, //       ##      
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+
+	// @960 '8' (14 pixels wide)
+	0x00, 0x00, //               
+	0x0F, 0x80, //     #####     
+	0x1F, 0xC0, //    #######    
+	0x38, 0xE0, //   ###   ###   
+	0x30, 0x60, //   ##     ##   
+	0x38, 0xE0, //   ###   ###   
+	0x1F, 0xC0, //    #######    
+	0x1F, 0xC0, //    #######    
+	0x38, 0xE0, //   ###   ###   
+	0x30, 0x60, //   ##     ##   
+	0x30, 0x60, //   ##     ##   
+	0x38, 0xE0, //   ###   ###   
+	0x1F, 0xC0, //    #######    
+	0x0F, 0x80, //     #####     
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+
+	// @1000 '9' (14 pixels wide)
+	0x00, 0x00, //               
+	0x0F, 0x00, //     ####      
+	0x1F, 0xC0, //    #######    
+	0x38, 0xC0, //   ###   ##    
+	0x30, 0x60, //   ##     ##   
+	0x30, 0x60, //   ##     ##   
+	0x38, 0xE0, //   ###   ###   
+	0x1F, 0xE0, //    ########   
+	0x0F, 0x60, //     #### ##   
+	0x00, 0xE0, //         ###   
+	0x00, 0xC0, //         ##    
+	0x03, 0xC0, //       ####    
+	0x3F, 0x80, //   #######     
+	0x3E, 0x00, //   #####       
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+
+	// @1040 ':' (14 pixels wide)
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x03, 0x80, //       ###     
+	0x03, 0x80, //       ###     
+	0x03, 0x80, //       ###     
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x03, 0x80, //       ###     
+	0x03, 0x80, //       ###     
+	0x03, 0x80, //       ###     
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+
+	// @1080 ';' (14 pixels wide)
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x01, 0xC0, //        ###    
+	0x01, 0xC0, //        ###    
+	0x01, 0xC0, //        ###    
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x03, 0x80, //       ###     
+	0x03, 0x00, //       ##      
+	0x06, 0x00, //      ##       
+	0x06, 0x00, //      ##       
+	0x04, 0x00, //      #        
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+
+	// @1120 '<' (14 pixels wide)
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x30, //           ##  
+	0x00, 0xF0, //         ####  
+	0x03, 0xC0, //       ####    
+	0x07, 0x00, //      ###      
+	0x1C, 0x00, //    ###        
+	0x78, 0x00, //  ####         
+	0x1C, 0x00, //    ###        
+	0x07, 0x00, //      ###      
+	0x03, 0xC0, //       ####    
+	0x00, 0xF0, //         ####  
+	0x00, 0x30, //           ##  
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+
+	// @1160 '=' (14 pixels wide)
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x7F, 0xF0, //  ###########  
+	0x7F, 0xF0, //  ###########  
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x7F, 0xF0, //  ###########  
+	0x7F, 0xF0, //  ###########  
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+
+	// @1200 '>' (14 pixels wide)
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x30, 0x00, //   ##          
+	0x3C, 0x00, //   ####        
+	0x0F, 0x00, //     ####      
+	0x03, 0x80, //       ###     
+	0x00, 0xE0, //         ###   
+	0x00, 0x78, //          #### 
+	0x00, 0xE0, //         ###   
+	0x03, 0x80, //       ###     
+	0x0F, 0x00, //     ####      
+	0x3C, 0x00, //   ####        
+	0x30, 0x00, //   ##          
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+
+	// @1240 '?' (14 pixels wide)
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x0F, 0x80, //     #####     
+	0x1F, 0xC0, //    #######    
+	0x18, 0x60, //    ##    ##   
+	0x18, 0x60, //    ##    ##   
+	0x00, 0x60, //          ##   
+	0x01, 0xC0, //        ###    
+	0x03, 0x80, //       ###     
+	0x03, 0x00, //       ##      
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x07, 0x00, //      ###      
+	0x07, 0x00, //      ###      
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+
+	// @1280 '@' (14 pixels wide)
+	0x00, 0x00, //               
+	0x03, 0x80, //       ###     
+	0x0C, 0x80, //     ##  #     
+	0x08, 0x40, //     #    #    
+	0x10, 0x40, //    #     #    
+	0x10, 0x40, //    #     #    
+	0x11, 0xC0, //    #   ###    
+	0x12, 0x40, //    #  #  #    
+	0x12, 0x40, //    #  #  #    
+	0x12, 0x40, //    #  #  #    
+	0x11, 0xC0, //    #   ###    
+	0x10, 0x00, //    #          
+	0x08, 0x00, //     #         
+	0x08, 0x40, //     #    #    
+	0x07, 0x80, //      ####     
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+
+	// @1320 'A' (14 pixels wide)
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x1F, 0x80, //    ######     
+	0x1F, 0x80, //    ######     
+	0x03, 0x80, //       ###     
+	0x06, 0xC0, //      ## ##    
+	0x06, 0xC0, //      ## ##    
+	0x0C, 0xC0, //     ##  ##    
+	0x0C, 0x60, //     ##   ##   
+	0x1F, 0xE0, //    ########   
+	0x1F, 0xE0, //    ########   
+	0x30, 0x30, //   ##      ##  
+	0x78, 0x78, //  ####    #### 
+	0x78, 0x78, //  ####    #### 
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+
+	// @1360 'B' (14 pixels wide)
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x3F, 0x80, //   #######     
+	0x3F, 0xC0, //   ########    
+	0x18, 0x60, //    ##    ##   
+	0x18, 0x60, //    ##    ##   
+	0x18, 0xE0, //    ##   ###   
+	0x1F, 0xC0, //    #######    
+	0x1F, 0xE0, //    ########   
+	0x18, 0x70, //    ##    ###  
+	0x18, 0x30, //    ##     ##  
+	0x18, 0x30, //    ##     ##  
+	0x3F, 0xF0, //   ##########  
+	0x3F, 0xE0, //   #########   
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+
+	// @1400 'C' (14 pixels wide)
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x07, 0xB0, //      #### ##  
+	0x0F, 0xF0, //     ########  
+	0x1C, 0x70, //    ###   ###  
+	0x38, 0x30, //   ###     ##  
+	0x30, 0x00, //   ##          
+	0x30, 0x00, //   ##          
+	0x30, 0x00, //   ##          
+	0x30, 0x00, //   ##          
+	0x38, 0x30, //   ###     ##  
+	0x1C, 0x70, //    ###   ###  
+	0x0F, 0xE0, //     #######   
+	0x07, 0xC0, //      #####    
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+
+	// @1440 'D' (14 pixels wide)
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x7F, 0x80, //  ########     
+	0x7F, 0xC0, //  #########    
+	0x30, 0xE0, //   ##    ###   
+	0x30, 0x70, //   ##     ###  
+	0x30, 0x30, //   ##      ##  
+	0x30, 0x30, //   ##      ##  
+	0x30, 0x30, //   ##      ##  
+	0x30, 0x30, //   ##      ##  
+	0x30, 0x70, //   ##     ###  
+	0x30, 0xE0, //   ##    ###   
+	0x7F, 0xC0, //  #########    
+	0x7F, 0x80, //  ########     
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+
+	// @1480 'E' (14 pixels wide)
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x3F, 0xF0, //   ##########  
+	0x3F, 0xF0, //   ##########  
+	0x18, 0x30, //    ##     ##  
+	0x18, 0x30, //    ##     ##  
+	0x19, 0x80, //    ##  ##     
+	0x1F, 0x80, //    ######     
+	0x1F, 0x80, //    ######     
+	0x19, 0x80, //    ##  ##     
+	0x18, 0x30, //    ##     ##  
+	0x18, 0x30, //    ##     ##  
+	0x3F, 0xF0, //   ##########  
+	0x3F, 0xF0, //   ##########  
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+
+	// @1520 'F' (14 pixels wide)
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x3F, 0xF0, //   ##########  
+	0x3F, 0xF0, //   ##########  
+	0x18, 0x30, //    ##     ##  
+	0x18, 0x30, //    ##     ##  
+	0x19, 0x80, //    ##  ##     
+	0x1F, 0x80, //    ######     
+	0x1F, 0x80, //    ######     
+	0x19, 0x80, //    ##  ##     
+	0x18, 0x00, //    ##         
+	0x18, 0x00, //    ##         
+	0x3F, 0x00, //   ######      
+	0x3F, 0x00, //   ######      
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+
+	// @1560 'G' (14 pixels wide)
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x07, 0xB0, //      #### ##  
+	0x1F, 0xF0, //    #########  
+	0x18, 0x70, //    ##    ###  
+	0x30, 0x30, //   ##      ##  
+	0x30, 0x00, //   ##          
+	0x30, 0x00, //   ##          
+	0x31, 0xF8, //   ##   ###### 
+	0x31, 0xF8, //   ##   ###### 
+	0x30, 0x30, //   ##      ##  
+	0x18, 0x30, //    ##     ##  
+	0x1F, 0xF0, //    #########  
+	0x07, 0xC0, //      #####    
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+
+	// @1600 'H' (14 pixels wide)
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x3C, 0xF0, //   ####  ####  
+	0x3C, 0xF0, //   ####  ####  
+	0x18, 0x60, //    ##    ##   
+	0x18, 0x60, //    ##    ##   
+	0x18, 0x60, //    ##    ##   
+	0x1F, 0xE0, //    ########   
+	0x1F, 0xE0, //    ########   
+	0x18, 0x60, //    ##    ##   
+	0x18, 0x60, //    ##    ##   
+	0x18, 0x60, //    ##    ##   
+	0x3C, 0xF0, //   ####  ####  
+	0x3C, 0xF0, //   ####  ####  
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+
+	// @1640 'I' (14 pixels wide)
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x1F, 0xE0, //    ########   
+	0x1F, 0xE0, //    ########   
+	0x03, 0x00, //       ##      
+	0x03, 0x00, //       ##      
+	0x03, 0x00, //       ##      
+	0x03, 0x00, //       ##      
+	0x03, 0x00, //       ##      
+	0x03, 0x00, //       ##      
+	0x03, 0x00, //       ##      
+	0x03, 0x00, //       ##      
+	0x1F, 0xE0, //    ########   
+	0x1F, 0xE0, //    ########   
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+
+	// @1680 'J' (14 pixels wide)
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x03, 0xF8, //       ####### 
+	0x03, 0xF8, //       ####### 
+	0x00, 0x60, //          ##   
+	0x00, 0x60, //          ##   
+	0x00, 0x60, //          ##   
+	0x00, 0x60, //          ##   
+	0x30, 0x60, //   ##     ##   
+	0x30, 0x60, //   ##     ##   
+	0x30, 0x60, //   ##     ##   
+	0x30, 0xE0, //   ##    ###   
+	0x3F, 0xC0, //   ########    
+	0x0F, 0x80, //     #####     
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+
+	// @1720 'K' (14 pixels wide)
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x3E, 0xF8, //   ##### ##### 
+	0x3E, 0xF8, //   ##### ##### 
+	0x18, 0xE0, //    ##   ###   
+	0x19, 0x80, //    ##  ##     
+	0x1B, 0x00, //    ## ##      
+	0x1F, 0x00, //    #####      
+	0x1D, 0x80, //    ### ##     
+	0x18, 0xC0, //    ##   ##    
+	0x18, 0xC0, //    ##   ##    
+	0x18, 0x60, //    ##    ##   
+	0x3E, 0x78, //   #####  #### 
+	0x3E, 0x38, //   #####   ### 
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+
+	// @1760 'L' (14 pixels wide)
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x3F, 0x00, //   ######      
+	0x3F, 0x00, //   ######      
+	0x0C, 0x00, //     ##        
+	0x0C, 0x00, //     ##        
+	0x0C, 0x00, //     ##        
+	0x0C, 0x00, //     ##        
+	0x0C, 0x00, //     ##        
+	0x0C, 0x30, //     ##    ##  
+	0x0C, 0x30, //     ##    ##  
+	0x0C, 0x30, //     ##    ##  
+	0x3F, 0xF0, //   ##########  
+	0x3F, 0xF0, //   ##########  
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+
+	// @1800 'M' (14 pixels wide)
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x78, 0x78, //  ####    #### 
+	0x78, 0x78, //  ####    #### 
+	0x38, 0x70, //   ###    ###  
+	0x3C, 0xF0, //   ####  ####  
+	0x34, 0xB0, //   ## #  # ##  
+	0x37, 0xB0, //   ## #### ##  
+	0x37, 0xB0, //   ## #### ##  
+	0x33, 0x30, //   ##  ##  ##  
+	0x33, 0x30, //   ##  ##  ##  
+	0x30, 0x30, //   ##      ##  
+	0x7C, 0xF8, //  #####  ##### 
+	0x7C, 0xF8, //  #####  ##### 
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+
+	// @1840 'N' (14 pixels wide)
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x39, 0xF0, //   ###  #####  
+	0x3D, 0xF0, //   #### #####  
+	0x1C, 0x60, //    ###   ##   
+	0x1E, 0x60, //    ####  ##   
+	0x1E, 0x60, //    ####  ##   
+	0x1B, 0x60, //    ## ## ##   
+	0x1B, 0x60, //    ## ## ##   
+	0x19, 0xE0, //    ##  ####   
+	0x19, 0xE0, //    ##  ####   
+	0x18, 0xE0, //    ##   ###   
+	0x3E, 0xE0, //   ##### ###   
+	0x3E, 0x60, //   #####  ##   
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+
+	// @1880 'O' (14 pixels wide)
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x07, 0x80, //      ####     
+	0x0F, 0xC0, //     ######    
+	0x1C, 0xE0, //    ###  ###   
+	0x38, 0x70, //   ###    ###  
+	0x30, 0x30, //   ##      ##  
+	0x30, 0x30, //   ##      ##  
+	0x30, 0x30, //   ##      ##  
+	0x30, 0x30, //   ##      ##  
+	0x38, 0x70, //   ###    ###  
+	0x1C, 0xE0, //    ###  ###   
+	0x0F, 0xC0, //     ######    
+	0x07, 0x80, //      ####     
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+
+	// @1920 'P' (14 pixels wide)
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x3F, 0xC0, //   ########    
+	0x3F, 0xE0, //   #########   
+	0x18, 0x70, //    ##    ###  
+	0x18, 0x30, //    ##     ##  
+	0x18, 0x30, //    ##     ##  
+	0x18, 0x70, //    ##    ###  
+	0x1F, 0xE0, //    ########   
+	0x1F, 0xC0, //    #######    
+	0x18, 0x00, //    ##         
+	0x18, 0x00, //    ##         
+	0x3F, 0x00, //   ######      
+	0x3F, 0x00, //   ######      
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+
+	// @1960 'Q' (14 pixels wide)
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x07, 0x80, //      ####     
+	0x0F, 0xC0, //     ######    
+	0x1C, 0xE0, //    ###  ###   
+	0x38, 0x70, //   ###    ###  
+	0x30, 0x30, //   ##      ##  
+	0x30, 0x30, //   ##      ##  
+	0x30, 0x30, //   ##      ##  
+	0x30, 0x30, //   ##      ##  
+	0x38, 0x70, //   ###    ###  
+	0x1C, 0xE0, //    ###  ###   
+	0x0F, 0xC0, //     ######    
+	0x07, 0x80, //      ####     
+	0x07, 0xB0, //      #### ##  
+	0x0F, 0xF0, //     ########  
+	0x0C, 0xE0, //     ##  ###   
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+
+	// @2000 'R' (14 pixels wide)
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x3F, 0xC0, //   ########    
+	0x3F, 0xE0, //   #########   
+	0x18, 0x70, //    ##    ###  
+	0x18, 0x30, //    ##     ##  
+	0x18, 0x70, //    ##    ###  
+	0x1F, 0xE0, //    ########   
+	0x1F, 0xC0, //    #######    
+	0x18, 0xE0, //    ##   ###   
+	0x18, 0x60, //    ##    ##   
+	0x18, 0x70, //    ##    ###  
+	0x3E, 0x38, //   #####   ### 
+	0x3E, 0x18, //   #####    ## 
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+
+	// @2040 'S' (14 pixels wide)
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x0F, 0xB0, //     ##### ##  
+	0x1F, 0xF0, //    #########  
+	0x38, 0x70, //   ###    ###  
+	0x30, 0x30, //   ##      ##  
+	0x38, 0x00, //   ###         
+	0x1F, 0x80, //    ######     
+	0x07, 0xE0, //      ######   
+	0x00, 0x70, //          ###  
+	0x30, 0x30, //   ##      ##  
+	0x38, 0x70, //   ###    ###  
+	0x3F, 0xE0, //   #########   
+	0x37, 0xC0, //   ## #####    
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+
+	// @2080 'T' (14 pixels wide)
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x3F, 0xF0, //   ##########  
+	0x3F, 0xF0, //   ##########  
+	0x33, 0x30, //   ##  ##  ##  
+	0x33, 0x30, //   ##  ##  ##  
+	0x33, 0x30, //   ##  ##  ##  
+	0x03, 0x00, //       ##      
+	0x03, 0x00, //       ##      
+	0x03, 0x00, //       ##      
+	0x03, 0x00, //       ##      
+	0x03, 0x00, //       ##      
+	0x0F, 0xC0, //     ######    
+	0x0F, 0xC0, //     ######    
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+
+	// @2120 'U' (14 pixels wide)
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x3C, 0xF0, //   ####  ####  
+	0x3C, 0xF0, //   ####  ####  
+	0x18, 0x60, //    ##    ##   
+	0x18, 0x60, //    ##    ##   
+	0x18, 0x60, //    ##    ##   
+	0x18, 0x60, //    ##    ##   
+	0x18, 0x60, //    ##    ##   
+	0x18, 0x60, //    ##    ##   
+	0x18, 0x60, //    ##    ##   
+	0x1C, 0xE0, //    ###  ###   
+	0x0F, 0xC0, //     ######    
+	0x07, 0x80, //      ####     
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+
+	// @2160 'V' (14 pixels wide)
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x78, 0xF0, //  ####   ####  
+	0x78, 0xF0, //  ####   ####  
+	0x30, 0x60, //   ##     ##   
+	0x30, 0x60, //   ##     ##   
+	0x18, 0xC0, //    ##   ##    
+	0x18, 0xC0, //    ##   ##    
+	0x0D, 0x80, //     ## ##     
+	0x0D, 0x80, //     ## ##     
+	0x0D, 0x80, //     ## ##     
+	0x07, 0x00, //      ###      
+	0x07, 0x00, //      ###      
+	0x07, 0x00, //      ###      
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+
+	// @2200 'W' (14 pixels wide)
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x7C, 0x7C, //  #####   #####
+	0x7C, 0x7C, //  #####   #####
+	0x30, 0x18, //   ##       ## 
+	0x33, 0x98, //   ##  ###  ## 
+	0x33, 0x98, //   ##  ###  ## 
+	0x33, 0x98, //   ##  ###  ## 
+	0x36, 0xD8, //   ## ## ## ## 
+	0x16, 0xD0, //    # ## ## #  
+	0x1C, 0x70, //    ###   ###  
+	0x1C, 0x70, //    ###   ###  
+	0x1C, 0x70, //    ###   ###  
+	0x18, 0x30, //    ##     ##  
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+
+	// @2240 'X' (14 pixels wide)
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x78, 0xF0, //  ####   ####  
+	0x78, 0xF0, //  ####   ####  
+	0x30, 0x60, //   ##     ##   
+	0x18, 0xC0, //    ##   ##    
+	0x0D, 0x80, //     ## ##     
+	0x07, 0x00, //      ###      
+	0x07, 0x00, //      ###      
+	0x0D, 0x80, //     ## ##     
+	0x18, 0xC0, //    ##   ##    
+	0x30, 0x60, //   ##     ##   
+	0x78, 0xF0, //  ####   ####  
+	0x78, 0xF0, //  ####   ####  
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+
+	// @2280 'Y' (14 pixels wide)
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x3C, 0xF0, //   ####  ####  
+	0x3C, 0xF0, //   ####  ####  
+	0x18, 0x60, //    ##    ##   
+	0x0C, 0xC0, //     ##  ##    
+	0x07, 0x80, //      ####     
+	0x07, 0x80, //      ####     
+	0x03, 0x00, //       ##      
+	0x03, 0x00, //       ##      
+	0x03, 0x00, //       ##      
+	0x03, 0x00, //       ##      
+	0x0F, 0xC0, //     ######    
+	0x0F, 0xC0, //     ######    
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+
+	// @2320 'Z' (14 pixels wide)
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x1F, 0xE0, //    ########   
+	0x1F, 0xE0, //    ########   
+	0x18, 0x60, //    ##    ##   
+	0x18, 0xC0, //    ##   ##    
+	0x01, 0x80, //        ##     
+	0x03, 0x00, //       ##      
+	0x03, 0x00, //       ##      
+	0x06, 0x00, //      ##       
+	0x0C, 0x60, //     ##   ##   
+	0x18, 0x60, //    ##    ##   
+	0x1F, 0xE0, //    ########   
+	0x1F, 0xE0, //    ########   
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+
+	// @2360 '[' (14 pixels wide)
+	0x00, 0x00, //               
+	0x03, 0xC0, //       ####    
+	0x03, 0xC0, //       ####    
+	0x03, 0x00, //       ##      
+	0x03, 0x00, //       ##      
+	0x03, 0x00, //       ##      
+	0x03, 0x00, //       ##      
+	0x03, 0x00, //       ##      
+	0x03, 0x00, //       ##      
+	0x03, 0x00, //       ##      
+	0x03, 0x00, //       ##      
+	0x03, 0x00, //       ##      
+	0x03, 0x00, //       ##      
+	0x03, 0x00, //       ##      
+	0x03, 0x00, //       ##      
+	0x03, 0xC0, //       ####    
+	0x03, 0xC0, //       ####    
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+
+	// @2400 '\' (14 pixels wide)
+	0x18, 0x00, //    ##         
+	0x18, 0x00, //    ##         
+	0x0C, 0x00, //     ##        
+	0x0C, 0x00, //     ##        
+	0x0C, 0x00, //     ##        
+	0x06, 0x00, //      ##       
+	0x06, 0x00, //      ##       
+	0x03, 0x00, //       ##      
+	0x03, 0x00, //       ##      
+	0x01, 0x80, //        ##     
+	0x01, 0x80, //        ##     
+	0x00, 0xC0, //         ##    
+	0x00, 0xC0, //         ##    
+	0x00, 0xC0, //         ##    
+	0x00, 0x60, //          ##   
+	0x00, 0x60, //          ##   
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+
+	// @2440 ']' (14 pixels wide)
+	0x00, 0x00, //               
+	0x0F, 0x00, //     ####      
+	0x0F, 0x00, //     ####      
+	0x03, 0x00, //       ##      
+	0x03, 0x00, //       ##      
+	0x03, 0x00, //       ##      
+	0x03, 0x00, //       ##      
+	0x03, 0x00, //       ##      
+	0x03, 0x00, //       ##      
+	0x03, 0x00, //       ##      
+	0x03, 0x00, //       ##      
+	0x03, 0x00, //       ##      
+	0x03, 0x00, //       ##      
+	0x03, 0x00, //       ##      
+	0x03, 0x00, //       ##      
+	0x0F, 0x00, //     ####      
+	0x0F, 0x00, //     ####      
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+
+	// @2480 '^' (14 pixels wide)
+	0x00, 0x00, //               
+	0x02, 0x00, //       #       
+	0x07, 0x00, //      ###      
+	0x0D, 0x80, //     ## ##     
+	0x18, 0xC0, //    ##   ##    
+	0x30, 0x60, //   ##     ##   
+	0x20, 0x20, //   #       #   
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+
+	// @2520 '_' (14 pixels wide)
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0xFF, 0xFC, // ##############
+	0xFF, 0xFC, // ##############
+
+	// @2560 '`' (14 pixels wide)
+	0x00, 0x00, //               
+	0x04, 0x00, //      #        
+	0x03, 0x00, //       ##      
+	0x00, 0x80, //         #     
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+
+	// @2600 'a' (14 pixels wide)
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x0F, 0xC0, //     ######    
+	0x1F, 0xE0, //    ########   
+	0x00, 0x60, //          ##   
+	0x0F, 0xE0, //     #######   
+	0x1F, 0xE0, //    ########   
+	0x38, 0x60, //   ###    ##   
+	0x30, 0xE0, //   ##    ###   
+	0x3F, 0xF0, //   ##########  
+	0x1F, 0x70, //    ##### ###  
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+
+	// @2640 'b' (14 pixels wide)
+	0x00, 0x00, //               
+	0x70, 0x00, //  ###          
+	0x70, 0x00, //  ###          
+	0x30, 0x00, //   ##          
+	0x30, 0x00, //   ##          
+	0x37, 0x80, //   ## ####     
+	0x3F, 0xE0, //   #########   
+	0x38, 0x60, //   ###    ##   
+	0x30, 0x30, //   ##      ##  
+	0x30, 0x30, //   ##      ##  
+	0x30, 0x30, //   ##      ##  
+	0x38, 0x60, //   ###    ##   
+	0x7F, 0xE0, //  ##########   
+	0x77, 0x80, //  ### ####     
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+
+	// @2680 'c' (14 pixels wide)
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x07, 0xB0, //      #### ##  
+	0x1F, 0xF0, //    #########  
+	0x18, 0x30, //    ##     ##  
+	0x30, 0x30, //   ##      ##  
+	0x30, 0x00, //   ##          
+	0x30, 0x00, //   ##          
+	0x38, 0x30, //   ###     ##  
+	0x1F, 0xF0, //    #########  
+	0x0F, 0xC0, //     ######    
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+
+	// @2720 'd' (14 pixels wide)
+	0x00, 0x00, //               
+	0x00, 0x70, //          ###  
+	0x00, 0x70, //          ###  
+	0x00, 0x30, //           ##  
+	0x00, 0x30, //           ##  
+	0x07, 0xB0, //      #### ##  
+	0x1F, 0xF0, //    #########  
+	0x18, 0x70, //    ##    ###  
+	0x30, 0x30, //   ##      ##  
+	0x30, 0x30, //   ##      ##  
+	0x30, 0x30, //   ##      ##  
+	0x38, 0x70, //   ###    ###  
+	0x1F, 0xF8, //    ########## 
+	0x07, 0xB8, //      #### ### 
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+
+	// @2760 'e' (14 pixels wide)
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x07, 0x80, //      ####     
+	0x1F, 0xE0, //    ########   
+	0x18, 0x60, //    ##    ##   
+	0x3F, 0xF0, //   ##########  
+	0x3F, 0xF0, //   ##########  
+	0x30, 0x00, //   ##          
+	0x18, 0x30, //    ##     ##  
+	0x1F, 0xF0, //    #########  
+	0x07, 0xC0, //      #####    
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+
+	// @2800 'f' (14 pixels wide)
+	0x00, 0x00, //               
+	0x03, 0xF0, //       ######  
+	0x07, 0xF0, //      #######  
+	0x06, 0x00, //      ##       
+	0x06, 0x00, //      ##       
+	0x1F, 0xE0, //    ########   
+	0x1F, 0xE0, //    ########   
+	0x06, 0x00, //      ##       
+	0x06, 0x00, //      ##       
+	0x06, 0x00, //      ##       
+	0x06, 0x00, //      ##       
+	0x06, 0x00, //      ##       
+	0x1F, 0xE0, //    ########   
+	0x1F, 0xE0, //    ########   
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+
+	// @2840 'g' (14 pixels wide)
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x07, 0xB8, //      #### ### 
+	0x1F, 0xF8, //    ########## 
+	0x18, 0x70, //    ##    ###  
+	0x30, 0x30, //   ##      ##  
+	0x30, 0x30, //   ##      ##  
+	0x30, 0x30, //   ##      ##  
+	0x18, 0x70, //    ##    ###  
+	0x1F, 0xF0, //    #########  
+	0x07, 0xB0, //      #### ##  
+	0x00, 0x30, //           ##  
+	0x00, 0x70, //          ###  
+	0x0F, 0xE0, //     #######   
+	0x0F, 0xC0, //     ######    
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+
+	// @2880 'h' (14 pixels wide)
+	0x00, 0x00, //               
+	0x38, 0x00, //   ###         
+	0x38, 0x00, //   ###         
+	0x18, 0x00, //    ##         
+	0x18, 0x00, //    ##         
+	0x1B, 0xC0, //    ## ####    
+	0x1F, 0xE0, //    ########   
+	0x1C, 0x60, //    ###   ##   
+	0x18, 0x60, //    ##    ##   
+	0x18, 0x60, //    ##    ##   
+	0x18, 0x60, //    ##    ##   
+	0x18, 0x60, //    ##    ##   
+	0x3C, 0xF0, //   ####  ####  
+	0x3C, 0xF0, //   ####  ####  
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+
+	// @2920 'i' (14 pixels wide)
+	0x00, 0x00, //               
+	0x03, 0x00, //       ##      
+	0x03, 0x00, //       ##      
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x1F, 0x00, //    #####      
+	0x1F, 0x00, //    #####      
+	0x03, 0x00, //       ##      
+	0x03, 0x00, //       ##      
+	0x03, 0x00, //       ##      
+	0x03, 0x00, //       ##      
+	0x03, 0x00, //       ##      
+	0x1F, 0xE0, //    ########   
+	0x1F, 0xE0, //    ########   
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+
+	// @2960 'j' (14 pixels wide)
+	0x00, 0x00, //               
+	0x03, 0x00, //       ##      
+	0x03, 0x00, //       ##      
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x1F, 0xC0, //    #######    
+	0x1F, 0xC0, //    #######    
+	0x00, 0xC0, //         ##    
+	0x00, 0xC0, //         ##    
+	0x00, 0xC0, //         ##    
+	0x00, 0xC0, //         ##    
+	0x00, 0xC0, //         ##    
+	0x00, 0xC0, //         ##    
+	0x00, 0xC0, //         ##    
+	0x00, 0xC0, //         ##    
+	0x01, 0xC0, //        ###    
+	0x3F, 0x80, //   #######     
+	0x3F, 0x00, //   ######      
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+
+	// @3000 'k' (14 pixels wide)
+	0x00, 0x00, //               
+	0x38, 0x00, //   ###         
+	0x38, 0x00, //   ###         
+	0x18, 0x00, //    ##         
+	0x18, 0x00, //    ##         
+	0x1B, 0xE0, //    ## #####   
+	0x1B, 0xE0, //    ## #####   
+	0x1B, 0x00, //    ## ##      
+	0x1E, 0x00, //    ####       
+	0x1E, 0x00, //    ####       
+	0x1B, 0x00, //    ## ##      
+	0x19, 0x80, //    ##  ##     
+	0x39, 0xF0, //   ###  #####  
+	0x39, 0xF0, //   ###  #####  
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+
+	// @3040 'l' (14 pixels wide)
+	0x00, 0x00, //               
+	0x1F, 0x00, //    #####      
+	0x1F, 0x00, //    #####      
+	0x03, 0x00, //       ##      
+	0x03, 0x00, //       ##      
+	0x03, 0x00, //       ##      
+	0x03, 0x00, //       ##      
+	0x03, 0x00, //       ##      
+	0x03, 0x00, //       ##      
+	0x03, 0x00, //       ##      
+	0x03, 0x00, //       ##      
+	0x03, 0x00, //       ##      
+	0x1F, 0xE0, //    ########   
+	0x1F, 0xE0, //    ########   
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+
+	// @3080 'm' (14 pixels wide)
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x7E, 0xE0, //  ###### ###   
+	0x7F, 0xF0, //  ###########  
+	0x33, 0x30, //   ##  ##  ##  
+	0x33, 0x30, //   ##  ##  ##  
+	0x33, 0x30, //   ##  ##  ##  
+	0x33, 0x30, //   ##  ##  ##  
+	0x33, 0x30, //   ##  ##  ##  
+	0x7B, 0xB8, //  #### ### ### 
+	0x7B, 0xB8, //  #### ### ### 
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+
+	// @3120 'n' (14 pixels wide)
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x3B, 0xC0, //   ### ####    
+	0x3F, 0xE0, //   #########   
+	0x1C, 0x60, //    ###   ##   
+	0x18, 0x60, //    ##    ##   
+	0x18, 0x60, //    ##    ##   
+	0x18, 0x60, //    ##    ##   
+	0x18, 0x60, //    ##    ##   
+	0x3C, 0xF0, //   ####  ####  
+	0x3C, 0xF0, //   ####  ####  
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+
+	// @3160 'o' (14 pixels wide)
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x07, 0x80, //      ####     
+	0x1F, 0xE0, //    ########   
+	0x18, 0x60, //    ##    ##   
+	0x30, 0x30, //   ##      ##  
+	0x30, 0x30, //   ##      ##  
+	0x30, 0x30, //   ##      ##  
+	0x18, 0x60, //    ##    ##   
+	0x1F, 0xE0, //    ########   
+	0x07, 0x80, //      ####     
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+
+	// @3200 'p' (14 pixels wide)
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x77, 0x80, //  ### ####     
+	0x7F, 0xE0, //  ##########   
+	0x38, 0x60, //   ###    ##   
+	0x30, 0x30, //   ##      ##  
+	0x30, 0x30, //   ##      ##  
+	0x30, 0x30, //   ##      ##  
+	0x38, 0x60, //   ###    ##   
+	0x3F, 0xE0, //   #########   
+	0x37, 0x80, //   ## ####     
+	0x30, 0x00, //   ##          
+	0x30, 0x00, //   ##          
+	0x7C, 0x00, //  #####        
+	0x7C, 0x00, //  #####        
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+
+	// @3240 'q' (14 pixels wide)
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x07, 0xB8, //      #### ### 
+	0x1F, 0xF8, //    ########## 
+	0x18, 0x70, //    ##    ###  
+	0x30, 0x30, //   ##      ##  
+	0x30, 0x30, //   ##      ##  
+	0x30, 0x30, //   ##      ##  
+	0x18, 0x70, //    ##    ###  
+	0x1F, 0xF0, //    #########  
+	0x07, 0xB0, //      #### ##  
+	0x00, 0x30, //           ##  
+	0x00, 0x30, //           ##  
+	0x00, 0xF8, //         ##### 
+	0x00, 0xF8, //         ##### 
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+
+	// @3280 'r' (14 pixels wide)
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x3C, 0xE0, //   ####  ###   
+	0x3D, 0xF0, //   #### #####  
+	0x0F, 0x30, //     ####  ##  
+	0x0E, 0x00, //     ###       
+	0x0C, 0x00, //     ##        
+	0x0C, 0x00, //     ##        
+	0x0C, 0x00, //     ##        
+	0x3F, 0xC0, //   ########    
+	0x3F, 0xC0, //   ########    
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+
+	// @3320 's' (14 pixels wide)
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x07, 0xE0, //      ######   
+	0x1F, 0xE0, //    ########   
+	0x18, 0x60, //    ##    ##   
+	0x1E, 0x00, //    ####       
+	0x0F, 0xC0, //     ######    
+	0x01, 0xE0, //        ####   
+	0x18, 0x60, //    ##    ##   
+	0x1F, 0xE0, //    ########   
+	0x1F, 0x80, //    ######     
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+
+	// @3360 't' (14 pixels wide)
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x0C, 0x00, //     ##        
+	0x0C, 0x00, //     ##        
+	0x0C, 0x00, //     ##        
+	0x3F, 0xE0, //   #########   
+	0x3F, 0xE0, //   #########   
+	0x0C, 0x00, //     ##        
+	0x0C, 0x00, //     ##        
+	0x0C, 0x00, //     ##        
+	0x0C, 0x00, //     ##        
+	0x0C, 0x30, //     ##    ##  
+	0x0F, 0xF0, //     ########  
+	0x07, 0xC0, //      #####    
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+
+	// @3400 'u' (14 pixels wide)
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x38, 0xE0, //   ###   ###   
+	0x38, 0xE0, //   ###   ###   
+	0x18, 0x60, //    ##    ##   
+	0x18, 0x60, //    ##    ##   
+	0x18, 0x60, //    ##    ##   
+	0x18, 0x60, //    ##    ##   
+	0x18, 0xE0, //    ##   ###   
+	0x1F, 0xF0, //    #########  
+	0x0F, 0x70, //     #### ###  
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+
+	// @3440 'v' (14 pixels wide)
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x78, 0xF0, //  ####   ####  
+	0x78, 0xF0, //  ####   ####  
+	0x30, 0x60, //   ##     ##   
+	0x18, 0xC0, //    ##   ##    
+	0x18, 0xC0, //    ##   ##    
+	0x0D, 0x80, //     ## ##     
+	0x0D, 0x80, //     ## ##     
+	0x07, 0x00, //      ###      
+	0x07, 0x00, //      ###      
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+
+	// @3480 'w' (14 pixels wide)
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x78, 0xF0, //  ####   ####  
+	0x78, 0xF0, //  ####   ####  
+	0x32, 0x60, //   ##  #  ##   
+	0x32, 0x60, //   ##  #  ##   
+	0x37, 0xE0, //   ## ######   
+	0x1D, 0xC0, //    ### ###    
+	0x1D, 0xC0, //    ### ###    
+	0x18, 0xC0, //    ##   ##    
+	0x18, 0xC0, //    ##   ##    
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+
+	// @3520 'x' (14 pixels wide)
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x3C, 0xF0, //   ####  ####  
+	0x3C, 0xF0, //   ####  ####  
+	0x0C, 0xC0, //     ##  ##    
+	0x07, 0x80, //      ####     
+	0x03, 0x00, //       ##      
+	0x07, 0x80, //      ####     
+	0x0C, 0xC0, //     ##  ##    
+	0x3C, 0xF0, //   ####  ####  
+	0x3C, 0xF0, //   ####  ####  
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+
+	// @3560 'y' (14 pixels wide)
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x78, 0xF0, //  ####   ####  
+	0x78, 0xF0, //  ####   ####  
+	0x30, 0x60, //   ##     ##   
+	0x18, 0xC0, //    ##   ##    
+	0x18, 0xC0, //    ##   ##    
+	0x0D, 0x80, //     ## ##     
+	0x0F, 0x80, //     #####     
+	0x07, 0x00, //      ###      
+	0x06, 0x00, //      ##       
+	0x06, 0x00, //      ##       
+	0x0C, 0x00, //     ##        
+	0x7F, 0x00, //  #######      
+	0x7F, 0x00, //  #######      
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+
+	// @3600 'z' (14 pixels wide)
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x1F, 0xE0, //    ########   
+	0x1F, 0xE0, //    ########   
+	0x18, 0xC0, //    ##   ##    
+	0x01, 0x80, //        ##     
+	0x03, 0x00, //       ##      
+	0x06, 0x00, //      ##       
+	0x0C, 0x60, //     ##   ##   
+	0x1F, 0xE0, //    ########   
+	0x1F, 0xE0, //    ########   
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+
+	// @3640 '{' (14 pixels wide)
+	0x00, 0x00, //               
+	0x01, 0xC0, //        ###    
+	0x03, 0xC0, //       ####    
+	0x03, 0x00, //       ##      
+	0x03, 0x00, //       ##      
+	0x03, 0x00, //       ##      
+	0x03, 0x00, //       ##      
+	0x03, 0x00, //       ##      
+	0x07, 0x00, //      ###      
+	0x0E, 0x00, //     ###       
+	0x07, 0x00, //      ###      
+	0x03, 0x00, //       ##      
+	0x03, 0x00, //       ##      
+	0x03, 0x00, //       ##      
+	0x03, 0x00, //       ##      
+	0x03, 0xC0, //       ####    
+	0x01, 0xC0, //        ###    
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+
+	// @3680 '|' (14 pixels wide)
+	0x00, 0x00, //               
+	0x03, 0x00, //       ##      
+	0x03, 0x00, //       ##      
+	0x03, 0x00, //       ##      
+	0x03, 0x00, //       ##      
+	0x03, 0x00, //       ##      
+	0x03, 0x00, //       ##      
+	0x03, 0x00, //       ##      
+	0x03, 0x00, //       ##      
+	0x03, 0x00, //       ##      
+	0x03, 0x00, //       ##      
+	0x03, 0x00, //       ##      
+	0x03, 0x00, //       ##      
+	0x03, 0x00, //       ##      
+	0x03, 0x00, //       ##      
+	0x03, 0x00, //       ##      
+	0x03, 0x00, //       ##      
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+
+	// @3720 '}' (14 pixels wide)
+	0x00, 0x00, //               
+	0x1C, 0x00, //    ###        
+	0x1E, 0x00, //    ####       
+	0x06, 0x00, //      ##       
+	0x06, 0x00, //      ##       
+	0x06, 0x00, //      ##       
+	0x06, 0x00, //      ##       
+	0x06, 0x00, //      ##       
+	0x07, 0x00, //      ###      
+	0x03, 0x80, //       ###     
+	0x07, 0x00, //      ###      
+	0x06, 0x00, //      ##       
+	0x06, 0x00, //      ##       
+	0x06, 0x00, //      ##       
+	0x06, 0x00, //      ##       
+	0x1E, 0x00, //    ####       
+	0x1C, 0x00, //    ###        
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+
+	// @3760 '~' (14 pixels wide)
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x0E, 0x00, //     ###       
+	0x3F, 0x30, //   ######  ##  
+	0x33, 0xF0, //   ##  ######  
+	0x01, 0xE0, //        ####   
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+	0x00, 0x00, //               
+};
+
+
+sFONT Font20 = {
+  Font20_Table,
+  14, /* Width */
+  20, /* Height */
+};
+
+/**
+  * @}
+  */ 
+
+
+/** @defgroup FONTS_Private_Function_Prototypes
+  * @{
+  */ 
+/**
+  * @}
+  */ 
+
+
+/** @defgroup FONTS_Private_Functions
+  * @{
+  */
+    
+/**
+  * @}
+  */
+  
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */  
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Utilities/Fonts/font24.c b/Utilities/Fonts/font24.c
new file mode 100644
index 0000000..bdee2f1
--- /dev/null
+++ b/Utilities/Fonts/font24.c
@@ -0,0 +1,2600 @@
+/**
+  ******************************************************************************
+  * @file    font24.c
+  * @author  MCD Application Team
+  * @version V1.0.0
+  * @date    18-February-2014
+  * @brief   This file provides text font24 for STM32xx-EVAL's LCD driver. 
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "fonts.h"
+
+/** @addtogroup Utilities
+  * @{
+  */
+  
+/** @addtogroup STM32_EVAL
+  * @{
+  */ 
+
+/** @addtogroup Common
+  * @{
+  */
+
+/** @addtogroup FONTS
+  * @brief      This file provides text font24 for STM32xx-EVAL's LCD driver.
+  * @{
+  */  
+
+/** @defgroup FONTS_Private_Types
+  * @{
+  */ 
+/**
+  * @}
+  */ 
+
+
+/** @defgroup FONTS_Private_Defines
+  * @{
+  */
+/**
+  * @}
+  */ 
+
+
+/** @defgroup FONTS_Private_Macros
+  * @{
+  */
+/**
+  * @}
+  */ 
+  
+
+/** @defgroup FONTS_Private_Variables
+  * @{
+  */
+const uint8_t Font24_Table [] = 
+{
+	// @0 ' ' (17 pixels wide)
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+
+	// @72 '!' (17 pixels wide)
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x03, 0x80, 0x00, //       ###        
+	0x03, 0x80, 0x00, //       ###        
+	0x03, 0x80, 0x00, //       ###        
+	0x03, 0x80, 0x00, //       ###        
+	0x03, 0x80, 0x00, //       ###        
+	0x03, 0x80, 0x00, //       ###        
+	0x03, 0x80, 0x00, //       ###        
+	0x03, 0x80, 0x00, //       ###        
+	0x03, 0x80, 0x00, //       ###        
+	0x01, 0x00, 0x00, //        #         
+	0x01, 0x00, 0x00, //        #         
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x03, 0x80, 0x00, //       ###        
+	0x03, 0x80, 0x00, //       ###        
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+
+	// @144 '"' (17 pixels wide)
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x0E, 0x70, 0x00, //     ###  ###     
+	0x0E, 0x70, 0x00, //     ###  ###     
+	0x0E, 0x70, 0x00, //     ###  ###     
+	0x04, 0x20, 0x00, //      #    #      
+	0x04, 0x20, 0x00, //      #    #      
+	0x04, 0x20, 0x00, //      #    #      
+	0x04, 0x20, 0x00, //      #    #      
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+
+	// @216 '#' (17 pixels wide)
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x06, 0x60, 0x00, //      ##  ##      
+	0x06, 0x60, 0x00, //      ##  ##      
+	0x06, 0x60, 0x00, //      ##  ##      
+	0x06, 0x60, 0x00, //      ##  ##      
+	0x06, 0x60, 0x00, //      ##  ##      
+	0x3F, 0xF8, 0x00, //   ###########    
+	0x3F, 0xF8, 0x00, //   ###########    
+	0x06, 0x60, 0x00, //      ##  ##      
+	0x0C, 0xC0, 0x00, //     ##  ##       
+	0x3F, 0xF8, 0x00, //   ###########    
+	0x3F, 0xF8, 0x00, //   ###########    
+	0x0C, 0xC0, 0x00, //     ##  ##       
+	0x0C, 0xC0, 0x00, //     ##  ##       
+	0x0C, 0xC0, 0x00, //     ##  ##       
+	0x0C, 0xC0, 0x00, //     ##  ##       
+	0x0C, 0xC0, 0x00, //     ##  ##       
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+
+	// @288 '$' (17 pixels wide)
+	0x00, 0x00, 0x00, //                  
+	0x01, 0x80, 0x00, //        ##        
+	0x01, 0x80, 0x00, //        ##        
+	0x07, 0xB0, 0x00, //      #### ##     
+	0x0F, 0xF0, 0x00, //     ########     
+	0x18, 0x70, 0x00, //    ##    ###     
+	0x18, 0x70, 0x00, //    ##    ###     
+	0x1C, 0x00, 0x00, //    ###           
+	0x0F, 0x80, 0x00, //     #####        
+	0x07, 0xE0, 0x00, //      ######      
+	0x00, 0xF0, 0x00, //         ####     
+	0x18, 0x30, 0x00, //    ##     ##     
+	0x1C, 0x30, 0x00, //    ###    ##     
+	0x1C, 0x70, 0x00, //    ###   ###     
+	0x1F, 0xE0, 0x00, //    ########      
+	0x1B, 0xC0, 0x00, //    ## ####       
+	0x01, 0x80, 0x00, //        ##        
+	0x01, 0x80, 0x00, //        ##        
+	0x01, 0x80, 0x00, //        ##        
+	0x01, 0x80, 0x00, //        ##        
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+
+	// @360 '%' (17 pixels wide)
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x07, 0x80, 0x00, //      ####        
+	0x0F, 0xC0, 0x00, //     ######       
+	0x1C, 0xE0, 0x00, //    ###  ###      
+	0x18, 0x60, 0x00, //    ##    ##      
+	0x18, 0x60, 0x00, //    ##    ##      
+	0x1C, 0xE0, 0x00, //    ###  ###      
+	0x0F, 0xF8, 0x00, //     #########    
+	0x07, 0xE0, 0x00, //      ######      
+	0x1F, 0xF0, 0x00, //    #########     
+	0x07, 0x38, 0x00, //      ###  ###    
+	0x06, 0x18, 0x00, //      ##    ##    
+	0x06, 0x18, 0x00, //      ##    ##    
+	0x07, 0x38, 0x00, //      ###  ###    
+	0x03, 0xF0, 0x00, //       ######     
+	0x01, 0xE0, 0x00, //        ####      
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+
+	// @432 '&' (17 pixels wide)
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x03, 0xF0, 0x00, //       ######     
+	0x07, 0xF0, 0x00, //      #######     
+	0x0C, 0x60, 0x00, //     ##   ##      
+	0x0C, 0x00, 0x00, //     ##           
+	0x0C, 0x00, 0x00, //     ##           
+	0x06, 0x00, 0x00, //      ##          
+	0x07, 0x00, 0x00, //      ###         
+	0x0F, 0x9C, 0x00, //     #####  ###   
+	0x1D, 0xFC, 0x00, //    ### #######   
+	0x18, 0xF0, 0x00, //    ##   ####     
+	0x18, 0x70, 0x00, //    ##    ###     
+	0x0F, 0xFC, 0x00, //     ##########   
+	0x07, 0xDC, 0x00, //      ##### ###   
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+
+	// @504 ''' (17 pixels wide)
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x03, 0x80, 0x00, //       ###        
+	0x03, 0x80, 0x00, //       ###        
+	0x03, 0x80, 0x00, //       ###        
+	0x01, 0x00, 0x00, //        #         
+	0x01, 0x00, 0x00, //        #         
+	0x01, 0x00, 0x00, //        #         
+	0x01, 0x00, 0x00, //        #         
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+
+	// @576 '(' (17 pixels wide)
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x18, 0x00, //            ##    
+	0x00, 0x38, 0x00, //           ###    
+	0x00, 0x70, 0x00, //          ###     
+	0x00, 0xF0, 0x00, //         ####     
+	0x00, 0xE0, 0x00, //         ###      
+	0x00, 0xE0, 0x00, //         ###      
+	0x01, 0xC0, 0x00, //        ###       
+	0x01, 0xC0, 0x00, //        ###       
+	0x01, 0xC0, 0x00, //        ###       
+	0x01, 0xC0, 0x00, //        ###       
+	0x01, 0xC0, 0x00, //        ###       
+	0x01, 0xC0, 0x00, //        ###       
+	0x00, 0xE0, 0x00, //         ###      
+	0x00, 0xE0, 0x00, //         ###      
+	0x00, 0x70, 0x00, //          ###     
+	0x00, 0x70, 0x00, //          ###     
+	0x00, 0x38, 0x00, //           ###    
+	0x00, 0x18, 0x00, //            ##    
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+
+	// @648 ')' (17 pixels wide)
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x18, 0x00, 0x00, //    ##            
+	0x1C, 0x00, 0x00, //    ###           
+	0x0E, 0x00, 0x00, //     ###          
+	0x0E, 0x00, 0x00, //     ###          
+	0x07, 0x00, 0x00, //      ###         
+	0x07, 0x00, 0x00, //      ###         
+	0x03, 0x80, 0x00, //       ###        
+	0x03, 0x80, 0x00, //       ###        
+	0x03, 0x80, 0x00, //       ###        
+	0x03, 0x80, 0x00, //       ###        
+	0x03, 0x80, 0x00, //       ###        
+	0x03, 0x80, 0x00, //       ###        
+	0x07, 0x00, 0x00, //      ###         
+	0x07, 0x00, 0x00, //      ###         
+	0x0F, 0x00, 0x00, //     ####         
+	0x0E, 0x00, 0x00, //     ###          
+	0x1C, 0x00, 0x00, //    ###           
+	0x18, 0x00, 0x00, //    ##            
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+
+	// @720 '*' (17 pixels wide)
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x01, 0x80, 0x00, //        ##        
+	0x01, 0x80, 0x00, //        ##        
+	0x01, 0x80, 0x00, //        ##        
+	0x1D, 0xB8, 0x00, //    ### ## ###    
+	0x1F, 0xF8, 0x00, //    ##########    
+	0x07, 0xE0, 0x00, //      ######      
+	0x03, 0xC0, 0x00, //       ####       
+	0x03, 0xC0, 0x00, //       ####       
+	0x06, 0x60, 0x00, //      ##  ##      
+	0x06, 0x60, 0x00, //      ##  ##      
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+
+	// @792 '+' (17 pixels wide)
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x01, 0x80, 0x00, //        ##        
+	0x01, 0x80, 0x00, //        ##        
+	0x01, 0x80, 0x00, //        ##        
+	0x01, 0x80, 0x00, //        ##        
+	0x01, 0x80, 0x00, //        ##        
+	0x3F, 0xFC, 0x00, //   ############   
+	0x3F, 0xFC, 0x00, //   ############   
+	0x01, 0x80, 0x00, //        ##        
+	0x01, 0x80, 0x00, //        ##        
+	0x01, 0x80, 0x00, //        ##        
+	0x01, 0x80, 0x00, //        ##        
+	0x01, 0x80, 0x00, //        ##        
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+
+	// @864 ',' (17 pixels wide)
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0xE0, 0x00, //         ###      
+	0x00, 0xC0, 0x00, //         ##       
+	0x01, 0xC0, 0x00, //        ###       
+	0x01, 0x80, 0x00, //        ##        
+	0x01, 0x80, 0x00, //        ##        
+	0x03, 0x00, 0x00, //       ##         
+	0x03, 0x00, 0x00, //       ##         
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+
+	// @936 '-' (17 pixels wide)
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x1F, 0xF8, 0x00, //    ##########    
+	0x1F, 0xF8, 0x00, //    ##########    
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+
+	// @1008 '.' (17 pixels wide)
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x03, 0xC0, 0x00, //       ####       
+	0x03, 0xC0, 0x00, //       ####       
+	0x03, 0xC0, 0x00, //       ####       
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+
+	// @1080 '/' (17 pixels wide)
+	0x00, 0x18, 0x00, //            ##    
+	0x00, 0x18, 0x00, //            ##    
+	0x00, 0x38, 0x00, //           ###    
+	0x00, 0x30, 0x00, //           ##     
+	0x00, 0x70, 0x00, //          ###     
+	0x00, 0x60, 0x00, //          ##      
+	0x00, 0x60, 0x00, //          ##      
+	0x00, 0xC0, 0x00, //         ##       
+	0x00, 0xC0, 0x00, //         ##       
+	0x01, 0x80, 0x00, //        ##        
+	0x01, 0x80, 0x00, //        ##        
+	0x03, 0x00, 0x00, //       ##         
+	0x03, 0x00, 0x00, //       ##         
+	0x06, 0x00, 0x00, //      ##          
+	0x06, 0x00, 0x00, //      ##          
+	0x0E, 0x00, 0x00, //     ###          
+	0x0C, 0x00, 0x00, //     ##           
+	0x1C, 0x00, 0x00, //    ###           
+	0x18, 0x00, 0x00, //    ##            
+	0x18, 0x00, 0x00, //    ##            
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+
+	// @1152 '0' (17 pixels wide)
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x03, 0xC0, 0x00, //       ####       
+	0x07, 0xE0, 0x00, //      ######      
+	0x0C, 0x30, 0x00, //     ##    ##     
+	0x0C, 0x30, 0x00, //     ##    ##     
+	0x18, 0x18, 0x00, //    ##      ##    
+	0x18, 0x18, 0x00, //    ##      ##    
+	0x18, 0x18, 0x00, //    ##      ##    
+	0x18, 0x18, 0x00, //    ##      ##    
+	0x18, 0x18, 0x00, //    ##      ##    
+	0x18, 0x18, 0x00, //    ##      ##    
+	0x18, 0x18, 0x00, //    ##      ##    
+	0x0C, 0x30, 0x00, //     ##    ##     
+	0x0C, 0x30, 0x00, //     ##    ##     
+	0x07, 0xE0, 0x00, //      ######      
+	0x03, 0xC0, 0x00, //       ####       
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+
+	// @1224 '1' (17 pixels wide)
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x80, 0x00, //         #        
+	0x07, 0x80, 0x00, //      ####        
+	0x1F, 0x80, 0x00, //    ######        
+	0x1D, 0x80, 0x00, //    ### ##        
+	0x01, 0x80, 0x00, //        ##        
+	0x01, 0x80, 0x00, //        ##        
+	0x01, 0x80, 0x00, //        ##        
+	0x01, 0x80, 0x00, //        ##        
+	0x01, 0x80, 0x00, //        ##        
+	0x01, 0x80, 0x00, //        ##        
+	0x01, 0x80, 0x00, //        ##        
+	0x01, 0x80, 0x00, //        ##        
+	0x01, 0x80, 0x00, //        ##        
+	0x1F, 0xF8, 0x00, //    ##########    
+	0x1F, 0xF8, 0x00, //    ##########    
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+
+	// @1296 '2' (17 pixels wide)
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x07, 0xC0, 0x00, //      #####       
+	0x1F, 0xF0, 0x00, //    #########     
+	0x38, 0x30, 0x00, //   ###     ##     
+	0x30, 0x18, 0x00, //   ##       ##    
+	0x30, 0x18, 0x00, //   ##       ##    
+	0x00, 0x18, 0x00, //            ##    
+	0x00, 0x30, 0x00, //           ##     
+	0x00, 0x60, 0x00, //          ##      
+	0x01, 0xC0, 0x00, //        ###       
+	0x03, 0x80, 0x00, //       ###        
+	0x06, 0x00, 0x00, //      ##          
+	0x0C, 0x00, 0x00, //     ##           
+	0x18, 0x00, 0x00, //    ##            
+	0x3F, 0xF8, 0x00, //   ###########    
+	0x3F, 0xF8, 0x00, //   ###########    
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+
+	// @1368 '3' (17 pixels wide)
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x03, 0xC0, 0x00, //       ####       
+	0x0F, 0xE0, 0x00, //     #######      
+	0x0C, 0x70, 0x00, //     ##   ###     
+	0x00, 0x30, 0x00, //           ##     
+	0x00, 0x30, 0x00, //           ##     
+	0x00, 0x60, 0x00, //          ##      
+	0x03, 0xC0, 0x00, //       ####       
+	0x03, 0xE0, 0x00, //       #####      
+	0x00, 0x70, 0x00, //          ###     
+	0x00, 0x18, 0x00, //            ##    
+	0x00, 0x18, 0x00, //            ##    
+	0x00, 0x18, 0x00, //            ##    
+	0x18, 0x38, 0x00, //    ##     ###    
+	0x1F, 0xF0, 0x00, //    #########     
+	0x0F, 0xC0, 0x00, //     ######       
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+
+	// @1440 '4' (17 pixels wide)
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0xE0, 0x00, //         ###      
+	0x01, 0xE0, 0x00, //        ####      
+	0x01, 0xE0, 0x00, //        ####      
+	0x03, 0x60, 0x00, //       ## ##      
+	0x06, 0x60, 0x00, //      ##  ##      
+	0x06, 0x60, 0x00, //      ##  ##      
+	0x0C, 0x60, 0x00, //     ##   ##      
+	0x0C, 0x60, 0x00, //     ##   ##      
+	0x18, 0x60, 0x00, //    ##    ##      
+	0x30, 0x60, 0x00, //   ##     ##      
+	0x3F, 0xF8, 0x00, //   ###########    
+	0x3F, 0xF8, 0x00, //   ###########    
+	0x00, 0x60, 0x00, //          ##      
+	0x03, 0xF8, 0x00, //       #######    
+	0x03, 0xF8, 0x00, //       #######    
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+
+	// @1512 '5' (17 pixels wide)
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x1F, 0xF0, 0x00, //    #########     
+	0x1F, 0xF0, 0x00, //    #########     
+	0x18, 0x00, 0x00, //    ##            
+	0x18, 0x00, 0x00, //    ##            
+	0x18, 0x00, 0x00, //    ##            
+	0x1B, 0xC0, 0x00, //    ## ####       
+	0x1F, 0xF0, 0x00, //    #########     
+	0x1C, 0x30, 0x00, //    ###    ##     
+	0x00, 0x18, 0x00, //            ##    
+	0x00, 0x18, 0x00, //            ##    
+	0x00, 0x18, 0x00, //            ##    
+	0x00, 0x18, 0x00, //            ##    
+	0x30, 0x30, 0x00, //   ##      ##     
+	0x3F, 0xF0, 0x00, //   ##########     
+	0x0F, 0xC0, 0x00, //     ######       
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+
+	// @1584 '6' (17 pixels wide)
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0xF8, 0x00, //         #####    
+	0x03, 0xF8, 0x00, //       #######    
+	0x07, 0x00, 0x00, //      ###         
+	0x0E, 0x00, 0x00, //     ###          
+	0x0C, 0x00, 0x00, //     ##           
+	0x18, 0x00, 0x00, //    ##            
+	0x1B, 0xC0, 0x00, //    ## ####       
+	0x1F, 0xF0, 0x00, //    #########     
+	0x1C, 0x30, 0x00, //    ###    ##     
+	0x18, 0x18, 0x00, //    ##      ##    
+	0x18, 0x18, 0x00, //    ##      ##    
+	0x18, 0x18, 0x00, //    ##      ##    
+	0x0C, 0x38, 0x00, //     ##    ###    
+	0x0F, 0xF0, 0x00, //     ########     
+	0x03, 0xE0, 0x00, //       #####      
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+
+	// @1656 '7' (17 pixels wide)
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x1F, 0xF8, 0x00, //    ##########    
+	0x1F, 0xF8, 0x00, //    ##########    
+	0x18, 0x18, 0x00, //    ##      ##    
+	0x18, 0x38, 0x00, //    ##     ###    
+	0x00, 0x30, 0x00, //           ##     
+	0x00, 0x30, 0x00, //           ##     
+	0x00, 0x70, 0x00, //          ###     
+	0x00, 0x60, 0x00, //          ##      
+	0x00, 0x60, 0x00, //          ##      
+	0x00, 0xE0, 0x00, //         ###      
+	0x00, 0xC0, 0x00, //         ##       
+	0x00, 0xC0, 0x00, //         ##       
+	0x01, 0xC0, 0x00, //        ###       
+	0x01, 0x80, 0x00, //        ##        
+	0x01, 0x80, 0x00, //        ##        
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+
+	// @1728 '8' (17 pixels wide)
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x07, 0xE0, 0x00, //      ######      
+	0x0F, 0xF0, 0x00, //     ########     
+	0x1C, 0x38, 0x00, //    ###    ###    
+	0x18, 0x18, 0x00, //    ##      ##    
+	0x18, 0x18, 0x00, //    ##      ##    
+	0x0C, 0x30, 0x00, //     ##    ##     
+	0x07, 0xE0, 0x00, //      ######      
+	0x07, 0xE0, 0x00, //      ######      
+	0x0C, 0x30, 0x00, //     ##    ##     
+	0x18, 0x18, 0x00, //    ##      ##    
+	0x18, 0x18, 0x00, //    ##      ##    
+	0x18, 0x18, 0x00, //    ##      ##    
+	0x1C, 0x38, 0x00, //    ###    ###    
+	0x0F, 0xF0, 0x00, //     ########     
+	0x07, 0xE0, 0x00, //      ######      
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+
+	// @1800 '9' (17 pixels wide)
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x07, 0xC0, 0x00, //      #####       
+	0x0F, 0xF0, 0x00, //     ########     
+	0x1C, 0x30, 0x00, //    ###    ##     
+	0x18, 0x18, 0x00, //    ##      ##    
+	0x18, 0x18, 0x00, //    ##      ##    
+	0x18, 0x18, 0x00, //    ##      ##    
+	0x0C, 0x38, 0x00, //     ##    ###    
+	0x0F, 0xF8, 0x00, //     #########    
+	0x03, 0xD8, 0x00, //       #### ##    
+	0x00, 0x18, 0x00, //            ##    
+	0x00, 0x30, 0x00, //           ##     
+	0x00, 0x70, 0x00, //          ###     
+	0x00, 0xE0, 0x00, //         ###      
+	0x1F, 0xC0, 0x00, //    #######       
+	0x1F, 0x00, 0x00, //    #####         
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+
+	// @1872 ':' (17 pixels wide)
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x03, 0xC0, 0x00, //       ####       
+	0x03, 0xC0, 0x00, //       ####       
+	0x03, 0xC0, 0x00, //       ####       
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x03, 0xC0, 0x00, //       ####       
+	0x03, 0xC0, 0x00, //       ####       
+	0x03, 0xC0, 0x00, //       ####       
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+
+	// @1944 ';' (17 pixels wide)
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0xF0, 0x00, //         ####     
+	0x00, 0xF0, 0x00, //         ####     
+	0x00, 0xF0, 0x00, //         ####     
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0xE0, 0x00, //         ###      
+	0x01, 0xC0, 0x00, //        ###       
+	0x01, 0x80, 0x00, //        ##        
+	0x01, 0x80, 0x00, //        ##        
+	0x03, 0x00, 0x00, //       ##         
+	0x02, 0x00, 0x00, //       #          
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+
+	// @2016 '<' (17 pixels wide)
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x1C, 0x00, //            ###   
+	0x00, 0x3C, 0x00, //           ####   
+	0x00, 0xF0, 0x00, //         ####     
+	0x03, 0xC0, 0x00, //       ####       
+	0x0F, 0x00, 0x00, //     ####         
+	0x3C, 0x00, 0x00, //   ####           
+	0xF0, 0x00, 0x00, // ####             
+	0x3C, 0x00, 0x00, //   ####           
+	0x0F, 0x00, 0x00, //     ####         
+	0x03, 0xC0, 0x00, //       ####       
+	0x00, 0xF0, 0x00, //         ####     
+	0x00, 0x3C, 0x00, //           ####   
+	0x00, 0x1C, 0x00, //            ###   
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+
+	// @2088 '=' (17 pixels wide)
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x7F, 0xFC, 0x00, //  #############   
+	0x7F, 0xFC, 0x00, //  #############   
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x7F, 0xFC, 0x00, //  #############   
+	0x7F, 0xFC, 0x00, //  #############   
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+
+	// @2160 '>' (17 pixels wide)
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x70, 0x00, 0x00, //  ###             
+	0x78, 0x00, 0x00, //  ####            
+	0x1E, 0x00, 0x00, //    ####          
+	0x07, 0x80, 0x00, //      ####        
+	0x01, 0xE0, 0x00, //        ####      
+	0x00, 0x78, 0x00, //          ####    
+	0x00, 0x1E, 0x00, //            ####  
+	0x00, 0x78, 0x00, //          ####    
+	0x01, 0xE0, 0x00, //        ####      
+	0x07, 0x80, 0x00, //      ####        
+	0x1E, 0x00, 0x00, //    ####          
+	0x78, 0x00, 0x00, //  ####            
+	0x70, 0x00, 0x00, //  ###             
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+
+	// @2232 '?' (17 pixels wide)
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x07, 0xC0, 0x00, //      #####       
+	0x0F, 0xE0, 0x00, //     #######      
+	0x18, 0x70, 0x00, //    ##    ###     
+	0x18, 0x30, 0x00, //    ##     ##     
+	0x18, 0x30, 0x00, //    ##     ##     
+	0x00, 0x70, 0x00, //          ###     
+	0x00, 0xE0, 0x00, //         ###      
+	0x03, 0xC0, 0x00, //       ####       
+	0x03, 0x80, 0x00, //       ###        
+	0x03, 0x00, 0x00, //       ##         
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x07, 0x00, 0x00, //      ###         
+	0x07, 0x00, 0x00, //      ###         
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+
+	// @2304 '@' (17 pixels wide)
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x03, 0xE0, 0x00, //       #####      
+	0x07, 0xF0, 0x00, //      #######     
+	0x0E, 0x38, 0x00, //     ###   ###    
+	0x0C, 0x18, 0x00, //     ##     ##    
+	0x18, 0x78, 0x00, //    ##    ####    
+	0x18, 0xF8, 0x00, //    ##   #####    
+	0x19, 0xD8, 0x00, //    ##  ### ##    
+	0x19, 0x98, 0x00, //    ##  ##  ##    
+	0x19, 0x98, 0x00, //    ##  ##  ##    
+	0x19, 0x98, 0x00, //    ##  ##  ##    
+	0x18, 0xF8, 0x00, //    ##   #####    
+	0x18, 0x78, 0x00, //    ##    ####    
+	0x18, 0x00, 0x00, //    ##            
+	0x0C, 0x00, 0x00, //     ##           
+	0x0E, 0x18, 0x00, //     ###    ##    
+	0x07, 0xF8, 0x00, //      ########    
+	0x03, 0xE0, 0x00, //       #####      
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+
+	// @2376 'A' (17 pixels wide)
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x1F, 0x80, 0x00, //    ######        
+	0x1F, 0xC0, 0x00, //    #######       
+	0x01, 0xC0, 0x00, //        ###       
+	0x03, 0x60, 0x00, //       ## ##      
+	0x03, 0x60, 0x00, //       ## ##      
+	0x06, 0x30, 0x00, //      ##   ##     
+	0x06, 0x30, 0x00, //      ##   ##     
+	0x0C, 0x30, 0x00, //     ##    ##     
+	0x0F, 0xF8, 0x00, //     #########    
+	0x1F, 0xF8, 0x00, //    ##########    
+	0x18, 0x0C, 0x00, //    ##       ##   
+	0x30, 0x0C, 0x00, //   ##        ##   
+	0xFC, 0x7F, 0x00, // ######   ####### 
+	0xFC, 0x7F, 0x00, // ######   ####### 
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+
+	// @2448 'B' (17 pixels wide)
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x7F, 0xE0, 0x00, //  ##########      
+	0x7F, 0xF0, 0x00, //  ###########     
+	0x18, 0x38, 0x00, //    ##     ###    
+	0x18, 0x18, 0x00, //    ##      ##    
+	0x18, 0x18, 0x00, //    ##      ##    
+	0x18, 0x38, 0x00, //    ##     ###    
+	0x1F, 0xF0, 0x00, //    #########     
+	0x1F, 0xF8, 0x00, //    ##########    
+	0x18, 0x1C, 0x00, //    ##      ###   
+	0x18, 0x0C, 0x00, //    ##       ##   
+	0x18, 0x0C, 0x00, //    ##       ##   
+	0x18, 0x0C, 0x00, //    ##       ##   
+	0x7F, 0xF8, 0x00, //  ############    
+	0x7F, 0xF0, 0x00, //  ###########     
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+
+	// @2520 'C' (17 pixels wide)
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x03, 0xEC, 0x00, //       ##### ##   
+	0x0F, 0xFC, 0x00, //     ##########   
+	0x1C, 0x1C, 0x00, //    ###     ###   
+	0x18, 0x0C, 0x00, //    ##       ##   
+	0x30, 0x0C, 0x00, //   ##        ##   
+	0x30, 0x00, 0x00, //   ##             
+	0x30, 0x00, 0x00, //   ##             
+	0x30, 0x00, 0x00, //   ##             
+	0x30, 0x00, 0x00, //   ##             
+	0x30, 0x00, 0x00, //   ##             
+	0x18, 0x0C, 0x00, //    ##       ##   
+	0x1C, 0x1C, 0x00, //    ###     ###   
+	0x0F, 0xF8, 0x00, //     #########    
+	0x03, 0xF0, 0x00, //       ######     
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+
+	// @2592 'D' (17 pixels wide)
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x7F, 0xC0, 0x00, //  #########       
+	0x7F, 0xF0, 0x00, //  ###########     
+	0x18, 0x38, 0x00, //    ##     ###    
+	0x18, 0x18, 0x00, //    ##      ##    
+	0x18, 0x0C, 0x00, //    ##       ##   
+	0x18, 0x0C, 0x00, //    ##       ##   
+	0x18, 0x0C, 0x00, //    ##       ##   
+	0x18, 0x0C, 0x00, //    ##       ##   
+	0x18, 0x0C, 0x00, //    ##       ##   
+	0x18, 0x0C, 0x00, //    ##       ##   
+	0x18, 0x18, 0x00, //    ##      ##    
+	0x18, 0x38, 0x00, //    ##     ###    
+	0x7F, 0xF0, 0x00, //  ###########     
+	0x7F, 0xE0, 0x00, //  ##########      
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+
+	// @2664 'E' (17 pixels wide)
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x7F, 0xF8, 0x00, //  ############    
+	0x7F, 0xF8, 0x00, //  ############    
+	0x18, 0x18, 0x00, //    ##      ##    
+	0x18, 0x18, 0x00, //    ##      ##    
+	0x19, 0x98, 0x00, //    ##  ##  ##    
+	0x19, 0x80, 0x00, //    ##  ##        
+	0x1F, 0x80, 0x00, //    ######        
+	0x1F, 0x80, 0x00, //    ######        
+	0x19, 0x80, 0x00, //    ##  ##        
+	0x19, 0x98, 0x00, //    ##  ##  ##    
+	0x18, 0x18, 0x00, //    ##      ##    
+	0x18, 0x18, 0x00, //    ##      ##    
+	0x7F, 0xF8, 0x00, //  ############    
+	0x7F, 0xF8, 0x00, //  ############    
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+
+	// @2736 'F' (17 pixels wide)
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x3F, 0xFC, 0x00, //   ############   
+	0x3F, 0xFC, 0x00, //   ############   
+	0x0C, 0x0C, 0x00, //     ##      ##   
+	0x0C, 0x0C, 0x00, //     ##      ##   
+	0x0C, 0xCC, 0x00, //     ##  ##  ##   
+	0x0C, 0xC0, 0x00, //     ##  ##       
+	0x0F, 0xC0, 0x00, //     ######       
+	0x0F, 0xC0, 0x00, //     ######       
+	0x0C, 0xC0, 0x00, //     ##  ##       
+	0x0C, 0xC0, 0x00, //     ##  ##       
+	0x0C, 0x00, 0x00, //     ##           
+	0x0C, 0x00, 0x00, //     ##           
+	0x3F, 0xC0, 0x00, //   ########       
+	0x3F, 0xC0, 0x00, //   ########       
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+
+	// @2808 'G' (17 pixels wide)
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x03, 0xEC, 0x00, //       ##### ##   
+	0x0F, 0xFC, 0x00, //     ##########   
+	0x1C, 0x1C, 0x00, //    ###     ###   
+	0x18, 0x0C, 0x00, //    ##       ##   
+	0x30, 0x0C, 0x00, //   ##        ##   
+	0x30, 0x00, 0x00, //   ##             
+	0x30, 0x00, 0x00, //   ##             
+	0x30, 0xFE, 0x00, //   ##    #######  
+	0x30, 0xFE, 0x00, //   ##    #######  
+	0x30, 0x0C, 0x00, //   ##        ##   
+	0x38, 0x0C, 0x00, //   ###       ##   
+	0x1C, 0x1C, 0x00, //    ###     ###   
+	0x0F, 0xFC, 0x00, //     ##########   
+	0x03, 0xF0, 0x00, //       ######     
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+
+	// @2880 'H' (17 pixels wide)
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x7E, 0x7E, 0x00, //  ######  ######  
+	0x7E, 0x7E, 0x00, //  ######  ######  
+	0x18, 0x18, 0x00, //    ##      ##    
+	0x18, 0x18, 0x00, //    ##      ##    
+	0x18, 0x18, 0x00, //    ##      ##    
+	0x18, 0x18, 0x00, //    ##      ##    
+	0x1F, 0xF8, 0x00, //    ##########    
+	0x1F, 0xF8, 0x00, //    ##########    
+	0x18, 0x18, 0x00, //    ##      ##    
+	0x18, 0x18, 0x00, //    ##      ##    
+	0x18, 0x18, 0x00, //    ##      ##    
+	0x18, 0x18, 0x00, //    ##      ##    
+	0x7E, 0x7E, 0x00, //  ######  ######  
+	0x7E, 0x7E, 0x00, //  ######  ######  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+
+	// @2952 'I' (17 pixels wide)
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x1F, 0xF8, 0x00, //    ##########    
+	0x1F, 0xF8, 0x00, //    ##########    
+	0x01, 0x80, 0x00, //        ##        
+	0x01, 0x80, 0x00, //        ##        
+	0x01, 0x80, 0x00, //        ##        
+	0x01, 0x80, 0x00, //        ##        
+	0x01, 0x80, 0x00, //        ##        
+	0x01, 0x80, 0x00, //        ##        
+	0x01, 0x80, 0x00, //        ##        
+	0x01, 0x80, 0x00, //        ##        
+	0x01, 0x80, 0x00, //        ##        
+	0x01, 0x80, 0x00, //        ##        
+	0x1F, 0xF8, 0x00, //    ##########    
+	0x1F, 0xF8, 0x00, //    ##########    
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+
+	// @3024 'J' (17 pixels wide)
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x07, 0xFE, 0x00, //      ##########  
+	0x07, 0xFE, 0x00, //      ##########  
+	0x00, 0x30, 0x00, //           ##     
+	0x00, 0x30, 0x00, //           ##     
+	0x00, 0x30, 0x00, //           ##     
+	0x00, 0x30, 0x00, //           ##     
+	0x00, 0x30, 0x00, //           ##     
+	0x30, 0x30, 0x00, //   ##      ##     
+	0x30, 0x30, 0x00, //   ##      ##     
+	0x30, 0x30, 0x00, //   ##      ##     
+	0x30, 0x30, 0x00, //   ##      ##     
+	0x30, 0x60, 0x00, //   ##     ##      
+	0x3F, 0xE0, 0x00, //   #########      
+	0x0F, 0x80, 0x00, //     #####        
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+
+	// @3096 'K' (17 pixels wide)
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x7F, 0x3E, 0x00, //  #######  #####  
+	0x7F, 0x3E, 0x00, //  #######  #####  
+	0x18, 0x30, 0x00, //    ##     ##     
+	0x18, 0x60, 0x00, //    ##    ##      
+	0x18, 0xC0, 0x00, //    ##   ##       
+	0x19, 0x80, 0x00, //    ##  ##        
+	0x1B, 0x80, 0x00, //    ## ###        
+	0x1F, 0xC0, 0x00, //    #######       
+	0x1C, 0xE0, 0x00, //    ###  ###      
+	0x18, 0x70, 0x00, //    ##    ###     
+	0x18, 0x30, 0x00, //    ##     ##     
+	0x18, 0x38, 0x00, //    ##     ###    
+	0x7F, 0x1F, 0x00, //  #######   ##### 
+	0x7F, 0x1F, 0x00, //  #######   ##### 
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+
+	// @3168 'L' (17 pixels wide)
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x7F, 0x80, 0x00, //  ########        
+	0x7F, 0x80, 0x00, //  ########        
+	0x0C, 0x00, 0x00, //     ##           
+	0x0C, 0x00, 0x00, //     ##           
+	0x0C, 0x00, 0x00, //     ##           
+	0x0C, 0x00, 0x00, //     ##           
+	0x0C, 0x00, 0x00, //     ##           
+	0x0C, 0x00, 0x00, //     ##           
+	0x0C, 0x0C, 0x00, //     ##      ##   
+	0x0C, 0x0C, 0x00, //     ##      ##   
+	0x0C, 0x0C, 0x00, //     ##      ##   
+	0x0C, 0x0C, 0x00, //     ##      ##   
+	0x7F, 0xFC, 0x00, //  #############   
+	0x7F, 0xFC, 0x00, //  #############   
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+
+	// @3240 'M' (17 pixels wide)
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0xF0, 0x0F, 0x00, // ####        #### 
+	0xF8, 0x1F, 0x00, // #####      ##### 
+	0x38, 0x1C, 0x00, //   ###      ###   
+	0x3C, 0x3C, 0x00, //   ####    ####   
+	0x3C, 0x3C, 0x00, //   ####    ####   
+	0x36, 0x6C, 0x00, //   ## ##  ## ##   
+	0x36, 0x6C, 0x00, //   ## ##  ## ##   
+	0x33, 0xCC, 0x00, //   ##  ####  ##   
+	0x33, 0xCC, 0x00, //   ##  ####  ##   
+	0x31, 0x8C, 0x00, //   ##   ##   ##   
+	0x30, 0x0C, 0x00, //   ##        ##   
+	0x30, 0x0C, 0x00, //   ##        ##   
+	0xFE, 0x7F, 0x00, // #######  ####### 
+	0xFE, 0x7F, 0x00, // #######  ####### 
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+
+	// @3312 'N' (17 pixels wide)
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x78, 0xFE, 0x00, //  ####   #######  
+	0x78, 0xFE, 0x00, //  ####   #######  
+	0x1C, 0x18, 0x00, //    ###     ##    
+	0x1E, 0x18, 0x00, //    ####    ##    
+	0x1F, 0x18, 0x00, //    #####   ##    
+	0x1B, 0x18, 0x00, //    ## ##   ##    
+	0x1B, 0x98, 0x00, //    ## ###  ##    
+	0x19, 0xD8, 0x00, //    ##  ### ##    
+	0x18, 0xD8, 0x00, //    ##   ## ##    
+	0x18, 0xF8, 0x00, //    ##   #####    
+	0x18, 0x78, 0x00, //    ##    ####    
+	0x18, 0x38, 0x00, //    ##     ###    
+	0x7F, 0x18, 0x00, //  #######   ##    
+	0x7F, 0x18, 0x00, //  #######   ##    
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+
+	// @3384 'O' (17 pixels wide)
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x03, 0xC0, 0x00, //       ####       
+	0x0F, 0xF0, 0x00, //     ########     
+	0x1C, 0x38, 0x00, //    ###    ###    
+	0x18, 0x18, 0x00, //    ##      ##    
+	0x38, 0x1C, 0x00, //   ###      ###   
+	0x30, 0x0C, 0x00, //   ##        ##   
+	0x30, 0x0C, 0x00, //   ##        ##   
+	0x30, 0x0C, 0x00, //   ##        ##   
+	0x30, 0x0C, 0x00, //   ##        ##   
+	0x38, 0x1C, 0x00, //   ###      ###   
+	0x18, 0x18, 0x00, //    ##      ##    
+	0x1C, 0x38, 0x00, //    ###    ###    
+	0x0F, 0xF0, 0x00, //     ########     
+	0x03, 0xC0, 0x00, //       ####       
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+
+	// @3456 'P' (17 pixels wide)
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x3F, 0xF0, 0x00, //   ##########     
+	0x3F, 0xF8, 0x00, //   ###########    
+	0x0C, 0x1C, 0x00, //     ##     ###   
+	0x0C, 0x0C, 0x00, //     ##      ##   
+	0x0C, 0x0C, 0x00, //     ##      ##   
+	0x0C, 0x0C, 0x00, //     ##      ##   
+	0x0C, 0x18, 0x00, //     ##     ##    
+	0x0F, 0xF8, 0x00, //     #########    
+	0x0F, 0xE0, 0x00, //     #######      
+	0x0C, 0x00, 0x00, //     ##           
+	0x0C, 0x00, 0x00, //     ##           
+	0x0C, 0x00, 0x00, //     ##           
+	0x3F, 0xC0, 0x00, //   ########       
+	0x3F, 0xC0, 0x00, //   ########       
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+
+	// @3528 'Q' (17 pixels wide)
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x03, 0xC0, 0x00, //       ####       
+	0x0F, 0xF0, 0x00, //     ########     
+	0x1C, 0x38, 0x00, //    ###    ###    
+	0x18, 0x18, 0x00, //    ##      ##    
+	0x38, 0x1C, 0x00, //   ###      ###   
+	0x30, 0x0C, 0x00, //   ##        ##   
+	0x30, 0x0C, 0x00, //   ##        ##   
+	0x30, 0x0C, 0x00, //   ##        ##   
+	0x30, 0x0C, 0x00, //   ##        ##   
+	0x38, 0x1C, 0x00, //   ###      ###   
+	0x18, 0x18, 0x00, //    ##      ##    
+	0x1C, 0x38, 0x00, //    ###    ###    
+	0x0F, 0xF0, 0x00, //     ########     
+	0x07, 0xC0, 0x00, //      #####       
+	0x07, 0xCC, 0x00, //      #####  ##   
+	0x0F, 0xFC, 0x00, //     ##########   
+	0x0C, 0x38, 0x00, //     ##    ###    
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+
+	// @3600 'R' (17 pixels wide)
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x7F, 0xE0, 0x00, //  ##########      
+	0x7F, 0xF0, 0x00, //  ###########     
+	0x18, 0x38, 0x00, //    ##     ###    
+	0x18, 0x18, 0x00, //    ##      ##    
+	0x18, 0x18, 0x00, //    ##      ##    
+	0x18, 0x38, 0x00, //    ##     ###    
+	0x1F, 0xF0, 0x00, //    #########     
+	0x1F, 0xC0, 0x00, //    #######       
+	0x18, 0xE0, 0x00, //    ##   ###      
+	0x18, 0x70, 0x00, //    ##    ###     
+	0x18, 0x30, 0x00, //    ##     ##     
+	0x18, 0x38, 0x00, //    ##     ###    
+	0x7F, 0x1E, 0x00, //  #######   ####  
+	0x7F, 0x0E, 0x00, //  #######    ###  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+
+	// @3672 'S' (17 pixels wide)
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x07, 0xD8, 0x00, //      ##### ##    
+	0x0F, 0xF8, 0x00, //     #########    
+	0x1C, 0x38, 0x00, //    ###    ###    
+	0x18, 0x18, 0x00, //    ##      ##    
+	0x18, 0x18, 0x00, //    ##      ##    
+	0x1E, 0x00, 0x00, //    ####          
+	0x0F, 0xC0, 0x00, //     ######       
+	0x03, 0xF0, 0x00, //       ######     
+	0x00, 0x78, 0x00, //          ####    
+	0x18, 0x18, 0x00, //    ##      ##    
+	0x18, 0x18, 0x00, //    ##      ##    
+	0x1C, 0x38, 0x00, //    ###    ###    
+	0x1F, 0xF0, 0x00, //    #########     
+	0x1B, 0xE0, 0x00, //    ## #####      
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+
+	// @3744 'T' (17 pixels wide)
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x3F, 0xFC, 0x00, //   ############   
+	0x3F, 0xFC, 0x00, //   ############   
+	0x31, 0x8C, 0x00, //   ##   ##   ##   
+	0x31, 0x8C, 0x00, //   ##   ##   ##   
+	0x31, 0x8C, 0x00, //   ##   ##   ##   
+	0x31, 0x8C, 0x00, //   ##   ##   ##   
+	0x01, 0x80, 0x00, //        ##        
+	0x01, 0x80, 0x00, //        ##        
+	0x01, 0x80, 0x00, //        ##        
+	0x01, 0x80, 0x00, //        ##        
+	0x01, 0x80, 0x00, //        ##        
+	0x01, 0x80, 0x00, //        ##        
+	0x0F, 0xF0, 0x00, //     ########     
+	0x0F, 0xF0, 0x00, //     ########     
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+
+	// @3816 'U' (17 pixels wide)
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x7E, 0x7E, 0x00, //  ######  ######  
+	0x7E, 0x7E, 0x00, //  ######  ######  
+	0x18, 0x18, 0x00, //    ##      ##    
+	0x18, 0x18, 0x00, //    ##      ##    
+	0x18, 0x18, 0x00, //    ##      ##    
+	0x18, 0x18, 0x00, //    ##      ##    
+	0x18, 0x18, 0x00, //    ##      ##    
+	0x18, 0x18, 0x00, //    ##      ##    
+	0x18, 0x18, 0x00, //    ##      ##    
+	0x18, 0x18, 0x00, //    ##      ##    
+	0x18, 0x18, 0x00, //    ##      ##    
+	0x0C, 0x30, 0x00, //     ##    ##     
+	0x0F, 0xF0, 0x00, //     ########     
+	0x03, 0xC0, 0x00, //       ####       
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+
+	// @3888 'V' (17 pixels wide)
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x7F, 0x7F, 0x00, //  ####### ####### 
+	0x7F, 0x7F, 0x00, //  ####### ####### 
+	0x18, 0x0C, 0x00, //    ##       ##   
+	0x0C, 0x18, 0x00, //     ##     ##    
+	0x0C, 0x18, 0x00, //     ##     ##    
+	0x0C, 0x18, 0x00, //     ##     ##    
+	0x06, 0x30, 0x00, //      ##   ##     
+	0x06, 0x30, 0x00, //      ##   ##     
+	0x03, 0x60, 0x00, //       ## ##      
+	0x03, 0x60, 0x00, //       ## ##      
+	0x03, 0x60, 0x00, //       ## ##      
+	0x01, 0xC0, 0x00, //        ###       
+	0x01, 0xC0, 0x00, //        ###       
+	0x00, 0x80, 0x00, //         #        
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+
+	// @3960 'W' (17 pixels wide)
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0xFE, 0x3F, 0x80, // #######   #######
+	0xFE, 0x3F, 0x80, // #######   #######
+	0x30, 0x06, 0x00, //   ##         ##  
+	0x30, 0x06, 0x00, //   ##         ##  
+	0x30, 0x86, 0x00, //   ##    #    ##  
+	0x19, 0xCC, 0x00, //    ##  ###  ##   
+	0x19, 0xCC, 0x00, //    ##  ###  ##   
+	0x1B, 0x6C, 0x00, //    ## ## ## ##   
+	0x1B, 0x6C, 0x00, //    ## ## ## ##   
+	0x1E, 0x7C, 0x00, //    ####  #####   
+	0x0E, 0x38, 0x00, //     ###   ###    
+	0x0E, 0x38, 0x00, //     ###   ###    
+	0x0C, 0x18, 0x00, //     ##     ##    
+	0x0C, 0x18, 0x00, //     ##     ##    
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+
+	// @4032 'X' (17 pixels wide)
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x7E, 0x7E, 0x00, //  ######  ######  
+	0x7E, 0x7E, 0x00, //  ######  ######  
+	0x18, 0x18, 0x00, //    ##      ##    
+	0x0C, 0x30, 0x00, //     ##    ##     
+	0x06, 0x60, 0x00, //      ##  ##      
+	0x03, 0xC0, 0x00, //       ####       
+	0x01, 0x80, 0x00, //        ##        
+	0x01, 0x80, 0x00, //        ##        
+	0x03, 0xC0, 0x00, //       ####       
+	0x06, 0x60, 0x00, //      ##  ##      
+	0x0C, 0x30, 0x00, //     ##    ##     
+	0x18, 0x18, 0x00, //    ##      ##    
+	0x7E, 0x7E, 0x00, //  ######  ######  
+	0x7E, 0x7E, 0x00, //  ######  ######  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+
+	// @4104 'Y' (17 pixels wide)
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x7C, 0x7E, 0x00, //  #####   ######  
+	0x7C, 0x7E, 0x00, //  #####   ######  
+	0x18, 0x18, 0x00, //    ##      ##    
+	0x0C, 0x30, 0x00, //     ##    ##     
+	0x06, 0x60, 0x00, //      ##  ##      
+	0x06, 0x60, 0x00, //      ##  ##      
+	0x03, 0xC0, 0x00, //       ####       
+	0x01, 0x80, 0x00, //        ##        
+	0x01, 0x80, 0x00, //        ##        
+	0x01, 0x80, 0x00, //        ##        
+	0x01, 0x80, 0x00, //        ##        
+	0x01, 0x80, 0x00, //        ##        
+	0x0F, 0xF0, 0x00, //     ########     
+	0x0F, 0xF0, 0x00, //     ########     
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+
+	// @4176 'Z' (17 pixels wide)
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x1F, 0xF8, 0x00, //    ##########    
+	0x1F, 0xF8, 0x00, //    ##########    
+	0x18, 0x18, 0x00, //    ##      ##    
+	0x18, 0x30, 0x00, //    ##     ##     
+	0x18, 0x60, 0x00, //    ##    ##      
+	0x18, 0xC0, 0x00, //    ##   ##       
+	0x01, 0x80, 0x00, //        ##        
+	0x03, 0x00, 0x00, //       ##         
+	0x06, 0x18, 0x00, //      ##    ##    
+	0x0C, 0x18, 0x00, //     ##     ##    
+	0x18, 0x18, 0x00, //    ##      ##    
+	0x30, 0x18, 0x00, //   ##       ##    
+	0x3F, 0xF8, 0x00, //   ###########    
+	0x3F, 0xF8, 0x00, //   ###########    
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+
+	// @4248 '[' (17 pixels wide)
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x01, 0xF0, 0x00, //        #####     
+	0x01, 0xF0, 0x00, //        #####     
+	0x01, 0x80, 0x00, //        ##        
+	0x01, 0x80, 0x00, //        ##        
+	0x01, 0x80, 0x00, //        ##        
+	0x01, 0x80, 0x00, //        ##        
+	0x01, 0x80, 0x00, //        ##        
+	0x01, 0x80, 0x00, //        ##        
+	0x01, 0x80, 0x00, //        ##        
+	0x01, 0x80, 0x00, //        ##        
+	0x01, 0x80, 0x00, //        ##        
+	0x01, 0x80, 0x00, //        ##        
+	0x01, 0x80, 0x00, //        ##        
+	0x01, 0x80, 0x00, //        ##        
+	0x01, 0x80, 0x00, //        ##        
+	0x01, 0x80, 0x00, //        ##        
+	0x01, 0xF0, 0x00, //        #####     
+	0x01, 0xF0, 0x00, //        #####     
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+
+	// @4320 '\' (17 pixels wide)
+	0x18, 0x00, 0x00, //    ##            
+	0x18, 0x00, 0x00, //    ##            
+	0x1C, 0x00, 0x00, //    ###           
+	0x0C, 0x00, 0x00, //     ##           
+	0x0E, 0x00, 0x00, //     ###          
+	0x06, 0x00, 0x00, //      ##          
+	0x06, 0x00, 0x00, //      ##          
+	0x03, 0x00, 0x00, //       ##         
+	0x03, 0x00, 0x00, //       ##         
+	0x01, 0x80, 0x00, //        ##        
+	0x01, 0x80, 0x00, //        ##        
+	0x00, 0xC0, 0x00, //         ##       
+	0x00, 0xC0, 0x00, //         ##       
+	0x00, 0x60, 0x00, //          ##      
+	0x00, 0x60, 0x00, //          ##      
+	0x00, 0x70, 0x00, //          ###     
+	0x00, 0x30, 0x00, //           ##     
+	0x00, 0x38, 0x00, //           ###    
+	0x00, 0x18, 0x00, //            ##    
+	0x00, 0x18, 0x00, //            ##    
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+
+	// @4392 ']' (17 pixels wide)
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x0F, 0x80, 0x00, //     #####        
+	0x0F, 0x80, 0x00, //     #####        
+	0x01, 0x80, 0x00, //        ##        
+	0x01, 0x80, 0x00, //        ##        
+	0x01, 0x80, 0x00, //        ##        
+	0x01, 0x80, 0x00, //        ##        
+	0x01, 0x80, 0x00, //        ##        
+	0x01, 0x80, 0x00, //        ##        
+	0x01, 0x80, 0x00, //        ##        
+	0x01, 0x80, 0x00, //        ##        
+	0x01, 0x80, 0x00, //        ##        
+	0x01, 0x80, 0x00, //        ##        
+	0x01, 0x80, 0x00, //        ##        
+	0x01, 0x80, 0x00, //        ##        
+	0x01, 0x80, 0x00, //        ##        
+	0x01, 0x80, 0x00, //        ##        
+	0x0F, 0x80, 0x00, //     #####        
+	0x0F, 0x80, 0x00, //     #####        
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+
+	// @4464 '^' (17 pixels wide)
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x80, 0x00, //         #        
+	0x01, 0xC0, 0x00, //        ###       
+	0x03, 0xE0, 0x00, //       #####      
+	0x07, 0x70, 0x00, //      ### ###     
+	0x06, 0x30, 0x00, //      ##   ##     
+	0x0C, 0x18, 0x00, //     ##     ##    
+	0x18, 0x0C, 0x00, //    ##       ##   
+	0x10, 0x04, 0x00, //    #         #   
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+
+	// @4536 '_' (17 pixels wide)
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0xFF, 0xFF, 0x00, // ################ 
+	0xFF, 0xFF, 0x00, // ################ 
+
+	// @4608 '`' (17 pixels wide)
+	0x00, 0x00, 0x00, //                  
+	0x03, 0x00, 0x00, //       ##         
+	0x03, 0x80, 0x00, //       ###        
+	0x00, 0xE0, 0x00, //         ###      
+	0x00, 0x60, 0x00, //          ##      
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+
+	// @4680 'a' (17 pixels wide)
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x0F, 0xC0, 0x00, //     ######       
+	0x1F, 0xE0, 0x00, //    ########      
+	0x00, 0x30, 0x00, //           ##     
+	0x00, 0x30, 0x00, //           ##     
+	0x07, 0xF0, 0x00, //      #######     
+	0x1F, 0xF0, 0x00, //    #########     
+	0x38, 0x30, 0x00, //   ###     ##     
+	0x30, 0x30, 0x00, //   ##      ##     
+	0x30, 0x70, 0x00, //   ##     ###     
+	0x1F, 0xFC, 0x00, //    ###########   
+	0x0F, 0xBC, 0x00, //     ##### ####   
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+
+	// @4752 'b' (17 pixels wide)
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x78, 0x00, 0x00, //  ####            
+	0x78, 0x00, 0x00, //  ####            
+	0x18, 0x00, 0x00, //    ##            
+	0x18, 0x00, 0x00, //    ##            
+	0x1B, 0xE0, 0x00, //    ## #####      
+	0x1F, 0xF8, 0x00, //    ##########    
+	0x1C, 0x18, 0x00, //    ###     ##    
+	0x18, 0x0C, 0x00, //    ##       ##   
+	0x18, 0x0C, 0x00, //    ##       ##   
+	0x18, 0x0C, 0x00, //    ##       ##   
+	0x18, 0x0C, 0x00, //    ##       ##   
+	0x18, 0x0C, 0x00, //    ##       ##   
+	0x1C, 0x18, 0x00, //    ###     ##    
+	0x7F, 0xF8, 0x00, //  ############    
+	0x7B, 0xE0, 0x00, //  #### #####      
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+
+	// @4824 'c' (17 pixels wide)
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x03, 0xEC, 0x00, //       ##### ##   
+	0x0F, 0xFC, 0x00, //     ##########   
+	0x1C, 0x1C, 0x00, //    ###     ###   
+	0x38, 0x0C, 0x00, //   ###       ##   
+	0x30, 0x0C, 0x00, //   ##        ##   
+	0x30, 0x00, 0x00, //   ##             
+	0x30, 0x00, 0x00, //   ##             
+	0x38, 0x0C, 0x00, //   ###       ##   
+	0x1C, 0x1C, 0x00, //    ###     ###   
+	0x0F, 0xF8, 0x00, //     #########    
+	0x03, 0xF0, 0x00, //       ######     
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+
+	// @4896 'd' (17 pixels wide)
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x78, 0x00, //          ####    
+	0x00, 0x78, 0x00, //          ####    
+	0x00, 0x18, 0x00, //            ##    
+	0x00, 0x18, 0x00, //            ##    
+	0x07, 0xD8, 0x00, //      ##### ##    
+	0x1F, 0xF8, 0x00, //    ##########    
+	0x18, 0x38, 0x00, //    ##     ###    
+	0x30, 0x18, 0x00, //   ##       ##    
+	0x30, 0x18, 0x00, //   ##       ##    
+	0x30, 0x18, 0x00, //   ##       ##    
+	0x30, 0x18, 0x00, //   ##       ##    
+	0x30, 0x18, 0x00, //   ##       ##    
+	0x18, 0x38, 0x00, //    ##     ###    
+	0x1F, 0xFE, 0x00, //    ############  
+	0x07, 0xDE, 0x00, //      ##### ####  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+
+	// @4968 'e' (17 pixels wide)
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x07, 0xE0, 0x00, //      ######      
+	0x1F, 0xF8, 0x00, //    ##########    
+	0x18, 0x18, 0x00, //    ##      ##    
+	0x30, 0x0C, 0x00, //   ##        ##   
+	0x3F, 0xFC, 0x00, //   ############   
+	0x3F, 0xFC, 0x00, //   ############   
+	0x30, 0x00, 0x00, //   ##             
+	0x30, 0x00, 0x00, //   ##             
+	0x18, 0x0C, 0x00, //    ##       ##   
+	0x1F, 0xFC, 0x00, //    ###########   
+	0x07, 0xF0, 0x00, //      #######     
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+
+	// @5040 'f' (17 pixels wide)
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x01, 0xFC, 0x00, //        #######   
+	0x03, 0xFC, 0x00, //       ########   
+	0x06, 0x00, 0x00, //      ##          
+	0x06, 0x00, 0x00, //      ##          
+	0x3F, 0xF8, 0x00, //   ###########    
+	0x3F, 0xF8, 0x00, //   ###########    
+	0x06, 0x00, 0x00, //      ##          
+	0x06, 0x00, 0x00, //      ##          
+	0x06, 0x00, 0x00, //      ##          
+	0x06, 0x00, 0x00, //      ##          
+	0x06, 0x00, 0x00, //      ##          
+	0x06, 0x00, 0x00, //      ##          
+	0x06, 0x00, 0x00, //      ##          
+	0x3F, 0xF0, 0x00, //   ##########     
+	0x3F, 0xF0, 0x00, //   ##########     
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+
+	// @5112 'g' (17 pixels wide)
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x07, 0xDE, 0x00, //      ##### ####  
+	0x1F, 0xFE, 0x00, //    ############  
+	0x18, 0x38, 0x00, //    ##     ###    
+	0x30, 0x18, 0x00, //   ##       ##    
+	0x30, 0x18, 0x00, //   ##       ##    
+	0x30, 0x18, 0x00, //   ##       ##    
+	0x30, 0x18, 0x00, //   ##       ##    
+	0x30, 0x18, 0x00, //   ##       ##    
+	0x18, 0x38, 0x00, //    ##     ###    
+	0x1F, 0xF8, 0x00, //    ##########    
+	0x07, 0xD8, 0x00, //      ##### ##    
+	0x00, 0x18, 0x00, //            ##    
+	0x00, 0x18, 0x00, //            ##    
+	0x00, 0x38, 0x00, //           ###    
+	0x0F, 0xF0, 0x00, //     ########     
+	0x0F, 0xC0, 0x00, //     ######       
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+
+	// @5184 'h' (17 pixels wide)
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x78, 0x00, 0x00, //  ####            
+	0x78, 0x00, 0x00, //  ####            
+	0x18, 0x00, 0x00, //    ##            
+	0x18, 0x00, 0x00, //    ##            
+	0x1B, 0xE0, 0x00, //    ## #####      
+	0x1F, 0xF0, 0x00, //    #########     
+	0x1C, 0x38, 0x00, //    ###    ###    
+	0x18, 0x18, 0x00, //    ##      ##    
+	0x18, 0x18, 0x00, //    ##      ##    
+	0x18, 0x18, 0x00, //    ##      ##    
+	0x18, 0x18, 0x00, //    ##      ##    
+	0x18, 0x18, 0x00, //    ##      ##    
+	0x18, 0x18, 0x00, //    ##      ##    
+	0x7E, 0x7E, 0x00, //  ######  ######  
+	0x7E, 0x7E, 0x00, //  ######  ######  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+
+	// @5256 'i' (17 pixels wide)
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x01, 0x80, 0x00, //        ##        
+	0x01, 0x80, 0x00, //        ##        
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x1F, 0x80, 0x00, //    ######        
+	0x1F, 0x80, 0x00, //    ######        
+	0x01, 0x80, 0x00, //        ##        
+	0x01, 0x80, 0x00, //        ##        
+	0x01, 0x80, 0x00, //        ##        
+	0x01, 0x80, 0x00, //        ##        
+	0x01, 0x80, 0x00, //        ##        
+	0x01, 0x80, 0x00, //        ##        
+	0x01, 0x80, 0x00, //        ##        
+	0x3F, 0xFC, 0x00, //   ############   
+	0x3F, 0xFC, 0x00, //   ############   
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+
+	// @5328 'j' (17 pixels wide)
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0xC0, 0x00, //         ##       
+	0x00, 0xC0, 0x00, //         ##       
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x1F, 0xF0, 0x00, //    #########     
+	0x1F, 0xF0, 0x00, //    #########     
+	0x00, 0x30, 0x00, //           ##     
+	0x00, 0x30, 0x00, //           ##     
+	0x00, 0x30, 0x00, //           ##     
+	0x00, 0x30, 0x00, //           ##     
+	0x00, 0x30, 0x00, //           ##     
+	0x00, 0x30, 0x00, //           ##     
+	0x00, 0x30, 0x00, //           ##     
+	0x00, 0x30, 0x00, //           ##     
+	0x00, 0x30, 0x00, //           ##     
+	0x00, 0x30, 0x00, //           ##     
+	0x00, 0x30, 0x00, //           ##     
+	0x00, 0x70, 0x00, //          ###     
+	0x1F, 0xE0, 0x00, //    ########      
+	0x1F, 0x80, 0x00, //    ######        
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+
+	// @5400 'k' (17 pixels wide)
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x3C, 0x00, 0x00, //   ####           
+	0x3C, 0x00, 0x00, //   ####           
+	0x0C, 0x00, 0x00, //     ##           
+	0x0C, 0x00, 0x00, //     ##           
+	0x0C, 0xF8, 0x00, //     ##  #####    
+	0x0C, 0xF8, 0x00, //     ##  #####    
+	0x0C, 0xC0, 0x00, //     ##  ##       
+	0x0D, 0x80, 0x00, //     ## ##        
+	0x0F, 0x80, 0x00, //     #####        
+	0x0F, 0x00, 0x00, //     ####         
+	0x0F, 0x80, 0x00, //     #####        
+	0x0D, 0xC0, 0x00, //     ## ###       
+	0x0C, 0xE0, 0x00, //     ##  ###      
+	0x3C, 0x7C, 0x00, //   ####   #####   
+	0x3C, 0x7C, 0x00, //   ####   #####   
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+
+	// @5472 'l' (17 pixels wide)
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x1F, 0x80, 0x00, //    ######        
+	0x1F, 0x80, 0x00, //    ######        
+	0x01, 0x80, 0x00, //        ##        
+	0x01, 0x80, 0x00, //        ##        
+	0x01, 0x80, 0x00, //        ##        
+	0x01, 0x80, 0x00, //        ##        
+	0x01, 0x80, 0x00, //        ##        
+	0x01, 0x80, 0x00, //        ##        
+	0x01, 0x80, 0x00, //        ##        
+	0x01, 0x80, 0x00, //        ##        
+	0x01, 0x80, 0x00, //        ##        
+	0x01, 0x80, 0x00, //        ##        
+	0x01, 0x80, 0x00, //        ##        
+	0x3F, 0xFC, 0x00, //   ############   
+	0x3F, 0xFC, 0x00, //   ############   
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+
+	// @5544 'm' (17 pixels wide)
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0xF7, 0x78, 0x00, // #### ### ####    
+	0xFF, 0xFC, 0x00, // ##############   
+	0x39, 0xCC, 0x00, //   ###  ###  ##   
+	0x31, 0x8C, 0x00, //   ##   ##   ##   
+	0x31, 0x8C, 0x00, //   ##   ##   ##   
+	0x31, 0x8C, 0x00, //   ##   ##   ##   
+	0x31, 0x8C, 0x00, //   ##   ##   ##   
+	0x31, 0x8C, 0x00, //   ##   ##   ##   
+	0x31, 0x8C, 0x00, //   ##   ##   ##   
+	0xFD, 0xEF, 0x00, // ###### #### #### 
+	0xFD, 0xEF, 0x00, // ###### #### #### 
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+
+	// @5616 'n' (17 pixels wide)
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x7B, 0xE0, 0x00, //  #### #####      
+	0x7F, 0xF0, 0x00, //  ###########     
+	0x1C, 0x38, 0x00, //    ###    ###    
+	0x18, 0x18, 0x00, //    ##      ##    
+	0x18, 0x18, 0x00, //    ##      ##    
+	0x18, 0x18, 0x00, //    ##      ##    
+	0x18, 0x18, 0x00, //    ##      ##    
+	0x18, 0x18, 0x00, //    ##      ##    
+	0x18, 0x18, 0x00, //    ##      ##    
+	0x7E, 0x7E, 0x00, //  ######  ######  
+	0x7E, 0x7E, 0x00, //  ######  ######  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+
+	// @5688 'o' (17 pixels wide)
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x03, 0xC0, 0x00, //       ####       
+	0x0F, 0xF0, 0x00, //     ########     
+	0x1C, 0x38, 0x00, //    ###    ###    
+	0x38, 0x1C, 0x00, //   ###      ###   
+	0x30, 0x0C, 0x00, //   ##        ##   
+	0x30, 0x0C, 0x00, //   ##        ##   
+	0x30, 0x0C, 0x00, //   ##        ##   
+	0x38, 0x1C, 0x00, //   ###      ###   
+	0x1C, 0x38, 0x00, //    ###    ###    
+	0x0F, 0xF0, 0x00, //     ########     
+	0x03, 0xC0, 0x00, //       ####       
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+
+	// @5760 'p' (17 pixels wide)
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x7B, 0xE0, 0x00, //  #### #####      
+	0x7F, 0xF8, 0x00, //  ############    
+	0x1C, 0x18, 0x00, //    ###     ##    
+	0x18, 0x0C, 0x00, //    ##       ##   
+	0x18, 0x0C, 0x00, //    ##       ##   
+	0x18, 0x0C, 0x00, //    ##       ##   
+	0x18, 0x0C, 0x00, //    ##       ##   
+	0x18, 0x0C, 0x00, //    ##       ##   
+	0x1C, 0x18, 0x00, //    ###     ##    
+	0x1F, 0xF8, 0x00, //    ##########    
+	0x1B, 0xE0, 0x00, //    ## #####      
+	0x18, 0x00, 0x00, //    ##            
+	0x18, 0x00, 0x00, //    ##            
+	0x18, 0x00, 0x00, //    ##            
+	0x7F, 0x00, 0x00, //  #######         
+	0x7F, 0x00, 0x00, //  #######         
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+
+	// @5832 'q' (17 pixels wide)
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x07, 0xDE, 0x00, //      ##### ####  
+	0x1F, 0xFE, 0x00, //    ############  
+	0x18, 0x38, 0x00, //    ##     ###    
+	0x30, 0x18, 0x00, //   ##       ##    
+	0x30, 0x18, 0x00, //   ##       ##    
+	0x30, 0x18, 0x00, //   ##       ##    
+	0x30, 0x18, 0x00, //   ##       ##    
+	0x30, 0x18, 0x00, //   ##       ##    
+	0x18, 0x38, 0x00, //    ##     ###    
+	0x1F, 0xF8, 0x00, //    ##########    
+	0x07, 0xD8, 0x00, //      ##### ##    
+	0x00, 0x18, 0x00, //            ##    
+	0x00, 0x18, 0x00, //            ##    
+	0x00, 0x18, 0x00, //            ##    
+	0x00, 0xFE, 0x00, //         #######  
+	0x00, 0xFE, 0x00, //         #######  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+
+	// @5904 'r' (17 pixels wide)
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x3E, 0x78, 0x00, //   #####  ####    
+	0x3E, 0xFC, 0x00, //   ##### ######   
+	0x07, 0xCC, 0x00, //      #####  ##   
+	0x07, 0x00, 0x00, //      ###         
+	0x06, 0x00, 0x00, //      ##          
+	0x06, 0x00, 0x00, //      ##          
+	0x06, 0x00, 0x00, //      ##          
+	0x06, 0x00, 0x00, //      ##          
+	0x06, 0x00, 0x00, //      ##          
+	0x3F, 0xF0, 0x00, //   ##########     
+	0x3F, 0xF0, 0x00, //   ##########     
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+
+	// @5976 's' (17 pixels wide)
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x07, 0xF8, 0x00, //      ########    
+	0x0F, 0xF8, 0x00, //     #########    
+	0x18, 0x18, 0x00, //    ##      ##    
+	0x18, 0x18, 0x00, //    ##      ##    
+	0x1F, 0x80, 0x00, //    ######        
+	0x0F, 0xF0, 0x00, //     ########     
+	0x00, 0xF8, 0x00, //         #####    
+	0x18, 0x18, 0x00, //    ##      ##    
+	0x18, 0x38, 0x00, //    ##     ###    
+	0x1F, 0xF0, 0x00, //    #########     
+	0x1F, 0xE0, 0x00, //    ########      
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+
+	// @6048 't' (17 pixels wide)
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x0C, 0x00, 0x00, //     ##           
+	0x0C, 0x00, 0x00, //     ##           
+	0x0C, 0x00, 0x00, //     ##           
+	0x0C, 0x00, 0x00, //     ##           
+	0x3F, 0xF0, 0x00, //   ##########     
+	0x3F, 0xF0, 0x00, //   ##########     
+	0x0C, 0x00, 0x00, //     ##           
+	0x0C, 0x00, 0x00, //     ##           
+	0x0C, 0x00, 0x00, //     ##           
+	0x0C, 0x00, 0x00, //     ##           
+	0x0C, 0x00, 0x00, //     ##           
+	0x0C, 0x00, 0x00, //     ##           
+	0x0C, 0x1C, 0x00, //     ##     ###   
+	0x07, 0xFC, 0x00, //      #########   
+	0x03, 0xF0, 0x00, //       ######     
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+
+	// @6120 'u' (17 pixels wide)
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x78, 0x78, 0x00, //  ####    ####    
+	0x78, 0x78, 0x00, //  ####    ####    
+	0x18, 0x18, 0x00, //    ##      ##    
+	0x18, 0x18, 0x00, //    ##      ##    
+	0x18, 0x18, 0x00, //    ##      ##    
+	0x18, 0x18, 0x00, //    ##      ##    
+	0x18, 0x18, 0x00, //    ##      ##    
+	0x18, 0x18, 0x00, //    ##      ##    
+	0x18, 0x38, 0x00, //    ##     ###    
+	0x0F, 0xFE, 0x00, //     ###########  
+	0x07, 0xDE, 0x00, //      ##### ####  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+
+	// @6192 'v' (17 pixels wide)
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x7C, 0x3E, 0x00, //  #####    #####  
+	0x7C, 0x3E, 0x00, //  #####    #####  
+	0x18, 0x18, 0x00, //    ##      ##    
+	0x18, 0x18, 0x00, //    ##      ##    
+	0x0C, 0x30, 0x00, //     ##    ##     
+	0x0C, 0x30, 0x00, //     ##    ##     
+	0x06, 0x60, 0x00, //      ##  ##      
+	0x06, 0x60, 0x00, //      ##  ##      
+	0x07, 0xE0, 0x00, //      ######      
+	0x03, 0xC0, 0x00, //       ####       
+	0x03, 0xC0, 0x00, //       ####       
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+
+	// @6264 'w' (17 pixels wide)
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x78, 0x3C, 0x00, //  ####     ####   
+	0x78, 0x3C, 0x00, //  ####     ####   
+	0x31, 0x18, 0x00, //   ##   #   ##    
+	0x33, 0x98, 0x00, //   ##  ###  ##    
+	0x33, 0x98, 0x00, //   ##  ###  ##    
+	0x1A, 0xB0, 0x00, //    ## # # ##     
+	0x1E, 0xF0, 0x00, //    #### ####     
+	0x1E, 0xF0, 0x00, //    #### ####     
+	0x1C, 0x60, 0x00, //    ###   ##      
+	0x0C, 0x60, 0x00, //     ##   ##      
+	0x0C, 0x60, 0x00, //     ##   ##      
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+
+	// @6336 'x' (17 pixels wide)
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x3E, 0x7C, 0x00, //   #####  #####   
+	0x3E, 0x7C, 0x00, //   #####  #####   
+	0x0C, 0x30, 0x00, //     ##    ##     
+	0x06, 0x60, 0x00, //      ##  ##      
+	0x03, 0xC0, 0x00, //       ####       
+	0x01, 0x80, 0x00, //        ##        
+	0x03, 0xC0, 0x00, //       ####       
+	0x06, 0x60, 0x00, //      ##  ##      
+	0x0C, 0x30, 0x00, //     ##    ##     
+	0x3E, 0x7C, 0x00, //   #####  #####   
+	0x3E, 0x7C, 0x00, //   #####  #####   
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+
+	// @6408 'y' (17 pixels wide)
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x7E, 0x1F, 0x00, //  ######    ##### 
+	0x7E, 0x1F, 0x00, //  ######    ##### 
+	0x18, 0x0C, 0x00, //    ##       ##   
+	0x0C, 0x18, 0x00, //     ##     ##    
+	0x0C, 0x18, 0x00, //     ##     ##    
+	0x06, 0x30, 0x00, //      ##   ##     
+	0x06, 0x30, 0x00, //      ##   ##     
+	0x03, 0x60, 0x00, //       ## ##      
+	0x03, 0xE0, 0x00, //       #####      
+	0x01, 0xC0, 0x00, //        ###       
+	0x00, 0xC0, 0x00, //         ##       
+	0x01, 0x80, 0x00, //        ##        
+	0x01, 0x80, 0x00, //        ##        
+	0x03, 0x00, 0x00, //       ##         
+	0x3F, 0xC0, 0x00, //   ########       
+	0x3F, 0xC0, 0x00, //   ########       
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+
+	// @6480 'z' (17 pixels wide)
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x1F, 0xF8, 0x00, //    ##########    
+	0x1F, 0xF8, 0x00, //    ##########    
+	0x18, 0x30, 0x00, //    ##     ##     
+	0x18, 0x60, 0x00, //    ##    ##      
+	0x00, 0xC0, 0x00, //         ##       
+	0x01, 0x80, 0x00, //        ##        
+	0x03, 0x00, 0x00, //       ##         
+	0x06, 0x18, 0x00, //      ##    ##    
+	0x0C, 0x18, 0x00, //     ##     ##    
+	0x1F, 0xF8, 0x00, //    ##########    
+	0x1F, 0xF8, 0x00, //    ##########    
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+
+	// @6552 '{' (17 pixels wide)
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0xE0, 0x00, //         ###      
+	0x01, 0xE0, 0x00, //        ####      
+	0x01, 0x80, 0x00, //        ##        
+	0x01, 0x80, 0x00, //        ##        
+	0x01, 0x80, 0x00, //        ##        
+	0x01, 0x80, 0x00, //        ##        
+	0x01, 0x80, 0x00, //        ##        
+	0x01, 0x80, 0x00, //        ##        
+	0x03, 0x80, 0x00, //       ###        
+	0x07, 0x00, 0x00, //      ###         
+	0x03, 0x80, 0x00, //       ###        
+	0x01, 0x80, 0x00, //        ##        
+	0x01, 0x80, 0x00, //        ##        
+	0x01, 0x80, 0x00, //        ##        
+	0x01, 0x80, 0x00, //        ##        
+	0x01, 0x80, 0x00, //        ##        
+	0x01, 0xE0, 0x00, //        ####      
+	0x00, 0xE0, 0x00, //         ###      
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+
+	// @6624 '|' (17 pixels wide)
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x01, 0x80, 0x00, //        ##        
+	0x01, 0x80, 0x00, //        ##        
+	0x01, 0x80, 0x00, //        ##        
+	0x01, 0x80, 0x00, //        ##        
+	0x01, 0x80, 0x00, //        ##        
+	0x01, 0x80, 0x00, //        ##        
+	0x01, 0x80, 0x00, //        ##        
+	0x01, 0x80, 0x00, //        ##        
+	0x01, 0x80, 0x00, //        ##        
+	0x01, 0x80, 0x00, //        ##        
+	0x01, 0x80, 0x00, //        ##        
+	0x01, 0x80, 0x00, //        ##        
+	0x01, 0x80, 0x00, //        ##        
+	0x01, 0x80, 0x00, //        ##        
+	0x01, 0x80, 0x00, //        ##        
+	0x01, 0x80, 0x00, //        ##        
+	0x01, 0x80, 0x00, //        ##        
+	0x01, 0x80, 0x00, //        ##        
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+
+	// @6696 '}' (17 pixels wide)
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x07, 0x00, 0x00, //      ###         
+	0x07, 0x80, 0x00, //      ####        
+	0x01, 0x80, 0x00, //        ##        
+	0x01, 0x80, 0x00, //        ##        
+	0x01, 0x80, 0x00, //        ##        
+	0x01, 0x80, 0x00, //        ##        
+	0x01, 0x80, 0x00, //        ##        
+	0x01, 0x80, 0x00, //        ##        
+	0x01, 0xC0, 0x00, //        ###       
+	0x00, 0xE0, 0x00, //         ###      
+	0x01, 0xC0, 0x00, //        ###       
+	0x01, 0x80, 0x00, //        ##        
+	0x01, 0x80, 0x00, //        ##        
+	0x01, 0x80, 0x00, //        ##        
+	0x01, 0x80, 0x00, //        ##        
+	0x01, 0x80, 0x00, //        ##        
+	0x07, 0x80, 0x00, //      ####        
+	0x07, 0x00, 0x00, //      ###         
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+
+	// @6768 '~' (17 pixels wide)
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x0E, 0x00, 0x00, //     ###          
+	0x1F, 0x18, 0x00, //    #####   ##    
+	0x3B, 0xB8, 0x00, //   ### ### ###    
+	0x31, 0xF0, 0x00, //   ##   #####     
+	0x00, 0xE0, 0x00, //         ###      
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+	0x00, 0x00, 0x00, //                  
+};
+
+sFONT Font24 = {
+  Font24_Table,
+  17, /* Width */
+  24, /* Height */
+};
+
+/**
+  * @}
+  */ 
+
+
+/** @defgroup FONTS_Private_Function_Prototypes
+  * @{
+  */ 
+/**
+  * @}
+  */ 
+
+
+/** @defgroup FONTS_Private_Functions
+  * @{
+  */
+    
+/**
+  * @}
+  */
+  
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */  
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Utilities/Fonts/font8.c b/Utilities/Fonts/font8.c
new file mode 100644
index 0000000..1a3cbf9
--- /dev/null
+++ b/Utilities/Fonts/font8.c
@@ -0,0 +1,1084 @@
+/**
+  ******************************************************************************
+  * @file    Font8.c
+  * @author  MCD Application Team
+  * @version V1.0.0
+  * @date    18-February-2014
+  * @brief   This file provides text Font8 for STM32xx-EVAL's LCD driver. 
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "fonts.h"
+
+/** @addtogroup Utilities
+  * @{
+  */
+  
+/** @addtogroup STM32_EVAL
+  * @{
+  */ 
+
+/** @addtogroup Common
+  * @{
+  */
+
+/** @addtogroup FONTS
+  * @brief      This file provides text Font8 for STM32xx-EVAL's LCD driver. 
+  * @{
+  */  
+
+/** @defgroup FONTS_Private_Types
+  * @{
+  */ 
+/**
+  * @}
+  */ 
+
+
+/** @defgroup FONTS_Private_Defines
+  * @{
+  */
+/**
+  * @}
+  */ 
+
+
+/** @defgroup FONTS_Private_Macros
+  * @{
+  */
+/**
+  * @}
+  */ 
+  
+
+/** @defgroup FONTS_Private_Variables
+  * @{
+  */
+// 
+//  Font data for Courier New 12pt
+// 
+
+const uint8_t Font8_Table[] = 
+{
+	// @0 ' ' (5 pixels wide)
+	0x00, //      
+	0x00, //      
+	0x00, //      
+	0x00, //      
+	0x00, //      
+	0x00, //      
+	0x00, //      
+	0x00, //      
+
+	// @8 '!' (5 pixels wide)
+	0x20, //   #  
+	0x20, //   #  
+	0x20, //   #  
+	0x20, //   #  
+	0x00, //      
+	0x20, //   #  
+	0x00, //      
+	0x00, //      
+
+	// @16 '"' (5 pixels wide)
+	0x50, //  # # 
+	0x50, //  # # 
+	0x00, //      
+	0x00, //      
+	0x00, //      
+	0x00, //      
+	0x00, //      
+	0x00, //      
+
+	// @24 '#' (5 pixels wide)
+	0x28, //   # #
+	0x50, //  # # 
+	0xF8, // #####
+	0x50, //  # # 
+	0xF8, // #####
+	0x50, //  # # 
+	0xA0, // # #  
+	0x00, //      
+
+	// @32 '$' (5 pixels wide)
+	0x20, //   #  
+	0x30, //   ## 
+	0x60, //  ##  
+	0x30, //   ## 
+	0x10, //    # 
+	0x60, //  ##  
+	0x20, //   #  
+	0x00, //      
+
+	// @40 '%' (5 pixels wide)
+	0x20, //   #  
+	0x20, //   #  
+	0x18, //    ##
+	0x60, //  ##  
+	0x10, //    # 
+	0x10, //    # 
+	0x00, //      
+	0x00, //      
+
+	// @48 '&' (5 pixels wide)
+	0x00, //      
+	0x38, //   ###
+	0x20, //   #  
+	0x60, //  ##  
+	0x50, //  # # 
+	0x78, //  ####
+	0x00, //      
+	0x00, //      
+
+	// @56 ''' (5 pixels wide)
+	0x20, //   #  
+	0x20, //   #  
+	0x20, //   #  
+	0x00, //      
+	0x00, //      
+	0x00, //      
+	0x00, //      
+	0x00, //      
+
+	// @64 '(' (5 pixels wide)
+	0x10, //    # 
+	0x20, //   #  
+	0x20, //   #  
+	0x20, //   #  
+	0x20, //   #  
+	0x20, //   #  
+	0x10, //    # 
+	0x00, //      
+
+	// @72 ')' (5 pixels wide)
+	0x40, //  #   
+	0x20, //   #  
+	0x20, //   #  
+	0x20, //   #  
+	0x20, //   #  
+	0x20, //   #  
+	0x40, //  #   
+	0x00, //      
+
+	// @80 '*' (5 pixels wide)
+	0x20, //   #  
+	0x70, //  ### 
+	0x20, //   #  
+	0x50, //  # # 
+	0x00, //      
+	0x00, //      
+	0x00, //      
+	0x00, //      
+
+	// @88 '+' (5 pixels wide)
+	0x00, //      
+	0x20, //   #  
+	0x20, //   #  
+	0xF8, // #####
+	0x20, //   #  
+	0x20, //   #  
+	0x00, //      
+	0x00, //      
+
+	// @96 ',' (5 pixels wide)
+	0x00, //      
+	0x00, //      
+	0x00, //      
+	0x00, //      
+	0x10, //    # 
+	0x20, //   #  
+	0x20, //   #  
+	0x00, //      
+
+	// @104 '-' (5 pixels wide)
+	0x00, //      
+	0x00, //      
+	0x00, //      
+	0x70, //  ### 
+	0x00, //      
+	0x00, //      
+	0x00, //      
+	0x00, //      
+
+	// @112 '.' (5 pixels wide)
+	0x00, //      
+	0x00, //      
+	0x00, //      
+	0x00, //      
+	0x00, //      
+	0x20, //   #  
+	0x00, //      
+	0x00, //      
+
+	// @120 '/' (5 pixels wide)
+	0x10, //    # 
+	0x20, //   #  
+	0x20, //   #  
+	0x20, //   #  
+	0x40, //  #   
+	0x40, //  #   
+	0x80, // #    
+	0x00, //      
+
+	// @128 '0' (5 pixels wide)
+	0x20, //   #  
+	0x50, //  # # 
+	0x50, //  # # 
+	0x50, //  # # 
+	0x50, //  # # 
+	0x20, //   #  
+	0x00, //      
+	0x00, //      
+
+	// @136 '1' (5 pixels wide)
+	0x60, //  ##  
+	0x20, //   #  
+	0x20, //   #  
+	0x20, //   #  
+	0x20, //   #  
+	0xF8, // #####
+	0x00, //      
+	0x00, //      
+
+	// @144 '2' (5 pixels wide)
+	0x20, //   #  
+	0x50, //  # # 
+	0x20, //   #  
+	0x20, //   #  
+	0x40, //  #   
+	0x70, //  ### 
+	0x00, //      
+	0x00, //      
+
+	// @152 '3' (5 pixels wide)
+	0x20, //   #  
+	0x50, //  # # 
+	0x10, //    # 
+	0x20, //   #  
+	0x10, //    # 
+	0x60, //  ##  
+	0x00, //      
+	0x00, //      
+
+	// @160 '4' (5 pixels wide)
+	0x10, //    # 
+	0x30, //   ## 
+	0x50, //  # # 
+	0x78, //  ####
+	0x10, //    # 
+	0x38, //   ###
+	0x00, //      
+	0x00, //      
+
+	// @168 '5' (5 pixels wide)
+	0x70, //  ### 
+	0x40, //  #   
+	0x60, //  ##  
+	0x10, //    # 
+	0x50, //  # # 
+	0x20, //   #  
+	0x00, //      
+	0x00, //      
+
+	// @176 '6' (5 pixels wide)
+	0x30, //   ## 
+	0x40, //  #   
+	0x60, //  ##  
+	0x50, //  # # 
+	0x50, //  # # 
+	0x60, //  ##  
+	0x00, //      
+	0x00, //      
+
+	// @184 '7' (5 pixels wide)
+	0x70, //  ### 
+	0x50, //  # # 
+	0x10, //    # 
+	0x20, //   #  
+	0x20, //   #  
+	0x20, //   #  
+	0x00, //      
+	0x00, //      
+
+	// @192 '8' (5 pixels wide)
+	0x20, //   #  
+	0x50, //  # # 
+	0x20, //   #  
+	0x50, //  # # 
+	0x50, //  # # 
+	0x20, //   #  
+	0x00, //      
+	0x00, //      
+
+	// @200 '9' (5 pixels wide)
+	0x30, //   ## 
+	0x50, //  # # 
+	0x50, //  # # 
+	0x30, //   ## 
+	0x10, //    # 
+	0x60, //  ##  
+	0x00, //      
+	0x00, //      
+
+	// @208 ':' (5 pixels wide)
+	0x00, //      
+	0x00, //      
+	0x20, //   #  
+	0x00, //      
+	0x00, //      
+	0x20, //   #  
+	0x00, //      
+	0x00, //      
+
+	// @216 ';' (5 pixels wide)
+	0x00, //      
+	0x00, //      
+	0x10, //    # 
+	0x00, //      
+	0x10, //    # 
+	0x20, //   #  
+	0x00, //      
+	0x00, //      
+
+	// @224 '<' (5 pixels wide)
+	0x00, //      
+	0x10, //    # 
+	0x20, //   #  
+	0xC0, // ##   
+	0x20, //   #  
+	0x10, //    # 
+	0x00, //      
+	0x00, //      
+
+	// @232 '=' (5 pixels wide)
+	0x00, //      
+	0x70, //  ### 
+	0x00, //      
+	0x70, //  ### 
+	0x00, //      
+	0x00, //      
+	0x00, //      
+	0x00, //      
+
+	// @240 '>' (5 pixels wide)
+	0x00, //      
+	0x40, //  #   
+	0x20, //   #  
+	0x18, //    ##
+	0x20, //   #  
+	0x40, //  #   
+	0x00, //      
+	0x00, //      
+
+	// @248 '?' (5 pixels wide)
+	0x20, //   #  
+	0x50, //  # # 
+	0x10, //    # 
+	0x20, //   #  
+	0x00, //      
+	0x20, //   #  
+	0x00, //      
+	0x00, //      
+
+	// @256 '@' (5 pixels wide)
+	0x30, //   ## 
+	0x48, //  #  #
+	0x48, //  #  #
+	0x58, //  # ##
+	0x48, //  #  #
+	0x40, //  #   
+	0x38, //   ###
+	0x00, //      
+
+	// @264 'A' (5 pixels wide)
+	0x60, //  ##  
+	0x20, //   #  
+	0x50, //  # # 
+	0x70, //  ### 
+	0x88, // #   #
+	0xD8, // ## ##
+	0x00, //      
+	0x00, //      
+
+	// @272 'B' (5 pixels wide)
+	0xF0, // #### 
+	0x48, //  #  #
+	0x70, //  ### 
+	0x48, //  #  #
+	0x48, //  #  #
+	0xF0, // #### 
+	0x00, //      
+	0x00, //      
+
+	// @280 'C' (5 pixels wide)
+	0x70, //  ### 
+	0x50, //  # # 
+	0x40, //  #   
+	0x40, //  #   
+	0x40, //  #   
+	0x30, //   ## 
+	0x00, //      
+	0x00, //      
+
+	// @288 'D' (5 pixels wide)
+	0xF0, // #### 
+	0x48, //  #  #
+	0x48, //  #  #
+	0x48, //  #  #
+	0x48, //  #  #
+	0xF0, // #### 
+	0x00, //      
+	0x00, //      
+
+	// @296 'E' (5 pixels wide)
+	0xF8, // #####
+	0x48, //  #  #
+	0x60, //  ##  
+	0x40, //  #   
+	0x48, //  #  #
+	0xF8, // #####
+	0x00, //      
+	0x00, //      
+
+	// @304 'F' (5 pixels wide)
+	0xF8, // #####
+	0x48, //  #  #
+	0x60, //  ##  
+	0x40, //  #   
+	0x40, //  #   
+	0xE0, // ###  
+	0x00, //      
+	0x00, //      
+
+	// @312 'G' (5 pixels wide)
+	0x70, //  ### 
+	0x40, //  #   
+	0x40, //  #   
+	0x58, //  # ##
+	0x50, //  # # 
+	0x30, //   ## 
+	0x00, //      
+	0x00, //      
+
+	// @320 'H' (5 pixels wide)
+	0xE8, // ### #
+	0x48, //  #  #
+	0x78, //  ####
+	0x48, //  #  #
+	0x48, //  #  #
+	0xE8, // ### #
+	0x00, //      
+	0x00, //      
+
+	// @328 'I' (5 pixels wide)
+	0x70, //  ### 
+	0x20, //   #  
+	0x20, //   #  
+	0x20, //   #  
+	0x20, //   #  
+	0x70, //  ### 
+	0x00, //      
+	0x00, //      
+
+	// @336 'J' (5 pixels wide)
+	0x38, //   ###
+	0x10, //    # 
+	0x10, //    # 
+	0x50, //  # # 
+	0x50, //  # # 
+	0x20, //   #  
+	0x00, //      
+	0x00, //      
+
+	// @344 'K' (5 pixels wide)
+	0xD8, // ## ##
+	0x50, //  # # 
+	0x60, //  ##  
+	0x70, //  ### 
+	0x50, //  # # 
+	0xD8, // ## ##
+	0x00, //      
+	0x00, //      
+
+	// @352 'L' (5 pixels wide)
+	0xE0, // ###  
+	0x40, //  #   
+	0x40, //  #   
+	0x40, //  #   
+	0x48, //  #  #
+	0xF8, // #####
+	0x00, //      
+	0x00, //      
+
+	// @360 'M' (5 pixels wide)
+	0xD8, // ## ##
+	0xD8, // ## ##
+	0xD8, // ## ##
+	0xA8, // # # #
+	0x88, // #   #
+	0xD8, // ## ##
+	0x00, //      
+	0x00, //      
+
+	// @368 'N' (5 pixels wide)
+	0xD8, // ## ##
+	0x68, //  ## #
+	0x68, //  ## #
+	0x58, //  # ##
+	0x58, //  # ##
+	0xE8, // ### #
+	0x00, //      
+	0x00, //      
+
+	// @376 'O' (5 pixels wide)
+	0x30, //   ## 
+	0x48, //  #  #
+	0x48, //  #  #
+	0x48, //  #  #
+	0x48, //  #  #
+	0x30, //   ## 
+	0x00, //      
+	0x00, //      
+
+	// @384 'P' (5 pixels wide)
+	0xF0, // #### 
+	0x48, //  #  #
+	0x48, //  #  #
+	0x70, //  ### 
+	0x40, //  #   
+	0xE0, // ###  
+	0x00, //      
+	0x00, //      
+
+	// @392 'Q' (5 pixels wide)
+	0x30, //   ## 
+	0x48, //  #  #
+	0x48, //  #  #
+	0x48, //  #  #
+	0x48, //  #  #
+	0x30, //   ## 
+	0x18, //    ##
+	0x00, //      
+
+	// @400 'R' (5 pixels wide)
+	0xF0, // #### 
+	0x48, //  #  #
+	0x48, //  #  #
+	0x70, //  ### 
+	0x48, //  #  #
+	0xE8, // ### #
+	0x00, //      
+	0x00, //      
+
+	// @408 'S' (5 pixels wide)
+	0x70, //  ### 
+	0x50, //  # # 
+	0x20, //   #  
+	0x10, //    # 
+	0x50, //  # # 
+	0x70, //  ### 
+	0x00, //      
+	0x00, //      
+
+	// @416 'T' (5 pixels wide)
+	0xF8, // #####
+	0xA8, // # # #
+	0x20, //   #  
+	0x20, //   #  
+	0x20, //   #  
+	0x70, //  ### 
+	0x00, //      
+	0x00, //      
+
+	// @424 'U' (5 pixels wide)
+	0xD8, // ## ##
+	0x48, //  #  #
+	0x48, //  #  #
+	0x48, //  #  #
+	0x48, //  #  #
+	0x30, //   ## 
+	0x00, //      
+	0x00, //      
+
+	// @432 'V' (5 pixels wide)
+	0xD8, // ## ##
+	0x88, // #   #
+	0x48, //  #  #
+	0x50, //  # # 
+	0x50, //  # # 
+	0x30, //   ## 
+	0x00, //      
+	0x00, //      
+
+	// @440 'W' (5 pixels wide)
+	0xD8, // ## ##
+	0x88, // #   #
+	0xA8, // # # #
+	0xA8, // # # #
+	0xA8, // # # #
+	0x50, //  # # 
+	0x00, //      
+	0x00, //      
+
+	// @448 'X' (5 pixels wide)
+	0xD8, // ## ##
+	0x50, //  # # 
+	0x20, //   #  
+	0x20, //   #  
+	0x50, //  # # 
+	0xD8, // ## ##
+	0x00, //      
+	0x00, //      
+
+	// @456 'Y' (5 pixels wide)
+	0xD8, // ## ##
+	0x88, // #   #
+	0x50, //  # # 
+	0x20, //   #  
+	0x20, //   #  
+	0x70, //  ### 
+	0x00, //      
+	0x00, //      
+
+	// @464 'Z' (5 pixels wide)
+	0x78, //  ####
+	0x48, //  #  #
+	0x10, //    # 
+	0x20, //   #  
+	0x48, //  #  #
+	0x78, //  ####
+	0x00, //      
+	0x00, //      
+
+	// @472 '[' (5 pixels wide)
+	0x30, //   ## 
+	0x20, //   #  
+	0x20, //   #  
+	0x20, //   #  
+	0x20, //   #  
+	0x20, //   #  
+	0x30, //   ## 
+	0x00, //      
+
+	// @480 '\' (5 pixels wide)
+	0x80, // #    
+	0x40, //  #   
+	0x40, //  #   
+	0x20, //   #  
+	0x20, //   #  
+	0x20, //   #  
+	0x10, //    # 
+	0x00, //      
+
+	// @488 ']' (5 pixels wide)
+	0x60, //  ##  
+	0x20, //   #  
+	0x20, //   #  
+	0x20, //   #  
+	0x20, //   #  
+	0x20, //   #  
+	0x60, //  ##  
+	0x00, //      
+
+	// @496 '^' (5 pixels wide)
+	0x20, //   #  
+	0x20, //   #  
+	0x50, //  # # 
+	0x00, //      
+	0x00, //      
+	0x00, //      
+	0x00, //      
+	0x00, //      
+
+	// @504 '_' (5 pixels wide)
+	0x00, //      
+	0x00, //      
+	0x00, //      
+	0x00, //      
+	0x00, //      
+	0x00, //      
+	0x00, //      
+	0xF8, // #####
+
+	// @512 '`' (5 pixels wide)
+	0x20, //   #  
+	0x10, //    # 
+	0x00, //      
+	0x00, //      
+	0x00, //      
+	0x00, //      
+	0x00, //      
+	0x00, //      
+
+	// @520 'a' (5 pixels wide)
+	0x00, //      
+	0x00, //      
+	0x30, //   ## 
+	0x10, //    # 
+	0x70, //  ### 
+	0x78, //  ####
+	0x00, //      
+	0x00, //      
+
+	// @528 'b' (5 pixels wide)
+	0xC0, // ##   
+	0x40, //  #   
+	0x70, //  ### 
+	0x48, //  #  #
+	0x48, //  #  #
+	0xF0, // #### 
+	0x00, //      
+	0x00, //      
+
+	// @536 'c' (5 pixels wide)
+	0x00, //      
+	0x00, //      
+	0x70, //  ### 
+	0x40, //  #   
+	0x40, //  #   
+	0x70, //  ### 
+	0x00, //      
+	0x00, //      
+
+	// @544 'd' (5 pixels wide)
+	0x18, //    ##
+	0x08, //     #
+	0x38, //   ###
+	0x48, //  #  #
+	0x48, //  #  #
+	0x38, //   ###
+	0x00, //      
+	0x00, //      
+
+	// @552 'e' (5 pixels wide)
+	0x00, //      
+	0x00, //      
+	0x70, //  ### 
+	0x70, //  ### 
+	0x40, //  #   
+	0x30, //   ## 
+	0x00, //      
+	0x00, //      
+
+	// @560 'f' (5 pixels wide)
+	0x10, //    # 
+	0x20, //   #  
+	0x70, //  ### 
+	0x20, //   #  
+	0x20, //   #  
+	0x70, //  ### 
+	0x00, //      
+	0x00, //      
+
+	// @568 'g' (5 pixels wide)
+	0x00, //      
+	0x00, //      
+	0x38, //   ###
+	0x48, //  #  #
+	0x48, //  #  #
+	0x38, //   ###
+	0x08, //     #
+	0x30, //   ## 
+
+	// @576 'h' (5 pixels wide)
+	0xC0, // ##   
+	0x40, //  #   
+	0x70, //  ### 
+	0x48, //  #  #
+	0x48, //  #  #
+	0xE8, // ### #
+	0x00, //      
+	0x00, //      
+
+	// @584 'i' (5 pixels wide)
+	0x20, //   #  
+	0x00, //      
+	0x60, //  ##  
+	0x20, //   #  
+	0x20, //   #  
+	0x70, //  ### 
+	0x00, //      
+	0x00, //      
+
+	// @592 'j' (5 pixels wide)
+	0x20, //   #  
+	0x00, //      
+	0x70, //  ### 
+	0x10, //    # 
+	0x10, //    # 
+	0x10, //    # 
+	0x10, //    # 
+	0x70, //  ### 
+
+	// @600 'k' (5 pixels wide)
+	0xC0, // ##   
+	0x40, //  #   
+	0x58, //  # ##
+	0x70, //  ### 
+	0x50, //  # # 
+	0xD8, // ## ##
+	0x00, //      
+	0x00, //      
+
+	// @608 'l' (5 pixels wide)
+	0x60, //  ##  
+	0x20, //   #  
+	0x20, //   #  
+	0x20, //   #  
+	0x20, //   #  
+	0x70, //  ### 
+	0x00, //      
+	0x00, //      
+
+	// @616 'm' (5 pixels wide)
+	0x00, //      
+	0x00, //      
+	0xD0, // ## # 
+	0xA8, // # # #
+	0xA8, // # # #
+	0xA8, // # # #
+	0x00, //      
+	0x00, //      
+
+	// @624 'n' (5 pixels wide)
+	0x00, //      
+	0x00, //      
+	0xF0, // #### 
+	0x48, //  #  #
+	0x48, //  #  #
+	0xC8, // ##  #
+	0x00, //      
+	0x00, //      
+
+	// @632 'o' (5 pixels wide)
+	0x00, //      
+	0x00, //      
+	0x30, //   ## 
+	0x48, //  #  #
+	0x48, //  #  #
+	0x30, //   ## 
+	0x00, //      
+	0x00, //      
+
+	// @640 'p' (5 pixels wide)
+	0x00, //      
+	0x00, //      
+	0xF0, // #### 
+	0x48, //  #  #
+	0x48, //  #  #
+	0x70, //  ### 
+	0x40, //  #   
+	0xE0, // ###  
+
+	// @648 'q' (5 pixels wide)
+	0x00, //      
+	0x00, //      
+	0x38, //   ###
+	0x48, //  #  #
+	0x48, //  #  #
+	0x38, //   ###
+	0x08, //     #
+	0x18, //    ##
+
+	// @656 'r' (5 pixels wide)
+	0x00, //      
+	0x00, //      
+	0x78, //  ####
+	0x20, //   #  
+	0x20, //   #  
+	0x70, //  ### 
+	0x00, //      
+	0x00, //      
+
+	// @664 's' (5 pixels wide)
+	0x00, //      
+	0x00, //      
+	0x30, //   ## 
+	0x20, //   #  
+	0x10, //    # 
+	0x60, //  ##  
+	0x00, //      
+	0x00, //      
+
+	// @672 't' (5 pixels wide)
+	0x00, //      
+	0x40, //  #   
+	0xF0, // #### 
+	0x40, //  #   
+	0x48, //  #  #
+	0x30, //   ## 
+	0x00, //      
+	0x00, //      
+
+	// @680 'u' (5 pixels wide)
+	0x00, //      
+	0x00, //      
+	0xD8, // ## ##
+	0x48, //  #  #
+	0x48, //  #  #
+	0x38, //   ###
+	0x00, //      
+	0x00, //      
+
+	// @688 'v' (5 pixels wide)
+	0x00, //      
+	0x00, //      
+	0xC8, // ##  #
+	0x48, //  #  #
+	0x30, //   ## 
+	0x30, //   ## 
+	0x00, //      
+	0x00, //      
+
+	// @696 'w' (5 pixels wide)
+	0x00, //      
+	0x00, //      
+	0xD8, // ## ##
+	0xA8, // # # #
+	0xA8, // # # #
+	0x50, //  # # 
+	0x00, //      
+	0x00, //      
+
+	// @704 'x' (5 pixels wide)
+	0x00, //      
+	0x00, //      
+	0x48, //  #  #
+	0x30, //   ## 
+	0x30, //   ## 
+	0x48, //  #  #
+	0x00, //      
+	0x00, //      
+
+	// @712 'y' (5 pixels wide)
+	0x00, //      
+	0x00, //      
+	0xD8, // ## ##
+	0x50, //  # # 
+	0x50, //  # # 
+	0x20, //   #  
+	0x20, //   #  
+	0x60, //  ##  
+
+	// @720 'z' (5 pixels wide)
+	0x00, //      
+	0x00, //      
+	0x78, //  ####
+	0x50, //  # # 
+	0x28, //   # #
+	0x78, //  ####
+	0x00, //      
+	0x00, //      
+
+	// @728 '{' (5 pixels wide)
+	0x10, //    # 
+	0x20, //   #  
+	0x20, //   #  
+	0x60, //  ##  
+	0x20, //   #  
+	0x20, //   #  
+	0x10, //    # 
+	0x00, //      
+
+	// @736 '|' (5 pixels wide)
+	0x20, //   #  
+	0x20, //   #  
+	0x20, //   #  
+	0x20, //   #  
+	0x20, //   #  
+	0x20, //   #  
+	0x20, //   #  
+	0x00, //      
+
+	// @744 '}' (5 pixels wide)
+	0x40, //  #   
+	0x20, //   #  
+	0x20, //   #  
+	0x30, //   ## 
+	0x20, //   #  
+	0x20, //   #  
+	0x40, //  #   
+	0x00, //      
+
+	// @752 '~' (5 pixels wide)
+	0x00, //      
+	0x00, //      
+	0x00, //      
+	0x28, //   # #
+	0x50, //  # # 
+	0x00, //      
+	0x00, //      
+	0x00, //      
+};
+
+sFONT Font8 = {
+  Font8_Table,
+  5, /* Width */
+  8, /* Height */
+};
+
+/**
+  * @}
+  */ 
+
+
+/** @defgroup FONTS_Private_Function_Prototypes
+  * @{
+  */ 
+/**
+  * @}
+  */ 
+
+
+/** @defgroup FONTS_Private_Functions
+  * @{
+  */
+    
+/**
+  * @}
+  */
+  
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */  
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Utilities/Fonts/fonts.h b/Utilities/Fonts/fonts.h
new file mode 100644
index 0000000..e9a794b
--- /dev/null
+++ b/Utilities/Fonts/fonts.h
@@ -0,0 +1,134 @@
+/**
+  ******************************************************************************
+  * @file    fonts.h
+  * @author  MCD Application Team
+  * @version V1.0.0
+  * @date    18-February-2014
+  * @brief   Header for fonts.c file
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __FONTS_H
+#define __FONTS_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include <stdint.h>
+
+/** @addtogroup Utilities
+  * @{
+  */
+  
+/** @addtogroup STM32_EVAL
+  * @{
+  */ 
+
+/** @addtogroup Common
+  * @{
+  */
+
+/** @addtogroup FONTS
+  * @{
+  */ 
+
+/** @defgroup FONTS_Exported_Types
+  * @{
+  */ 
+typedef struct _tFont
+{    
+  const uint8_t *table;
+  uint16_t Width;
+  uint16_t Height;
+  
+} sFONT;
+
+extern sFONT Font24;
+extern sFONT Font20;
+extern sFONT Font16;
+extern sFONT Font12;
+extern sFONT Font8;
+/**
+  * @}
+  */ 
+
+/** @defgroup FONTS_Exported_Constants
+  * @{
+  */ 
+#define LINE(x) ((x) * (((sFONT *)BSP_LCD_GetFont())->Height))
+
+/**
+  * @}
+  */ 
+
+/** @defgroup FONTS_Exported_Macros
+  * @{
+  */ 
+/**
+  * @}
+  */ 
+
+/** @defgroup FONTS_Exported_Functions
+  * @{
+  */ 
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+  
+#endif /* __FONTS_H */
+ 
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */      
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Utilities/Log/Release_Notes.html b/Utilities/Log/Release_Notes.html
new file mode 100644
index 0000000..819cf06
--- /dev/null
+++ b/Utilities/Log/Release_Notes.html
@@ -0,0 +1,170 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html xmlns:v="urn:schemas-microsoft-com:vml" xmlns:o="urn:schemas-microsoft-com:office:office" xmlns:w="urn:schemas-microsoft-com:office:word" xmlns="http://www.w3.org/TR/REC-html40"><head>
+
+
+
+
+
+
+
+
+
+  
+  <meta http-equiv="Content-Type" content="text/html; charset=ISO-8859-1">
+
+  
+  <link rel="File-List" href="Library_files/filelist.xml">
+
+  
+  <link rel="Edit-Time-Data" href="Library_files/editdata.mso"><!--[if !mso]> <style> v\:* {behavior:url(#default#VML);} o\:* {behavior:url(#default#VML);} w\:* {behavior:url(#default#VML);} .shape {behavior:url(#default#VML);} </style> <![endif]--><title>Release Notes for STM32Cube Log Utilities Driver</title><!--[if gte mso 9]><xml> <o:DocumentProperties> <o:Author>STMicroelectronics</o:Author> <o:LastAuthor>STMicroelectronics</o:LastAuthor> <o:Revision>37</o:Revision> <o:TotalTime>136</o:TotalTime> <o:Created>2009-02-27T19:26:00Z</o:Created> <o:LastSaved>2009-03-01T17:56:00Z</o:LastSaved> <o:Pages>1</o:Pages> <o:Words>522</o:Words> <o:Characters>2977</o:Characters> <o:Company>STMicroelectronics</o:Company> <o:Lines>24</o:Lines> <o:Paragraphs>6</o:Paragraphs> <o:CharactersWithSpaces>3493</o:CharactersWithSpaces> <o:Version>11.6568</o:Version> </o:DocumentProperties> </xml><![endif]--><!--[if gte mso 9]><xml> <w:WordDocument> <w:Zoom>110</w:Zoom> <w:ValidateAgainstSchemas/> <w:SaveIfXMLInvalid>false</w:SaveIfXMLInvalid> <w:IgnoreMixedContent>false</w:IgnoreMixedContent> <w:AlwaysShowPlaceholderText>false</w:AlwaysShowPlaceholderText> <w:BrowserLevel>MicrosoftInternetExplorer4</w:BrowserLevel> </w:WordDocument> </xml><![endif]--><!--[if gte mso 9]><xml> <w:LatentStyles DefLockedState="false" LatentStyleCount="156"> </w:LatentStyles> </xml><![endif]-->
+
+
+  
+
+  
+
+  
+  <style>
+<!--
+/* Style Definitions */
+p.MsoNormal, li.MsoNormal, div.MsoNormal
+{mso-style-parent:"";
+margin:0in;
+margin-bottom:.0001pt;
+mso-pagination:widow-orphan;
+font-size:12.0pt;
+font-family:"Times New Roman";
+mso-fareast-font-family:"Times New Roman";}
+h2
+{mso-style-next:Normal;
+margin-top:12.0pt;
+margin-right:0in;
+margin-bottom:3.0pt;
+margin-left:0in;
+mso-pagination:widow-orphan;
+page-break-after:avoid;
+mso-outline-level:2;
+font-size:14.0pt;
+font-family:Arial;
+font-weight:bold;
+font-style:italic;}
+a:link, span.MsoHyperlink
+{color:blue;
+text-decoration:underline;
+text-underline:single;}
+a:visited, span.MsoHyperlinkFollowed
+{color:blue;
+text-decoration:underline;
+text-underline:single;}
+p
+{mso-margin-top-alt:auto;
+margin-right:0in;
+mso-margin-bottom-alt:auto;
+margin-left:0in;
+mso-pagination:widow-orphan;
+font-size:12.0pt;
+font-family:"Times New Roman";
+mso-fareast-font-family:"Times New Roman";}
+@page Section1
+{size:8.5in 11.0in;
+margin:1.0in 1.25in 1.0in 1.25in;
+mso-header-margin:.5in;
+mso-footer-margin:.5in;
+mso-paper-source:0;}
+div.Section1
+{page:Section1;}
+-->
+  </style><!--[if gte mso 10]> <style> /* Style Definitions */ table.MsoNormalTable {mso-style-name:"Table Normal"; mso-tstyle-rowband-size:0; mso-tstyle-colband-size:0; mso-style-noshow:yes; mso-style-parent:""; mso-padding-alt:0in 5.4pt 0in 5.4pt; mso-para-margin:0in; mso-para-margin-bottom:.0001pt; mso-pagination:widow-orphan; font-size:10.0pt; font-family:"Times New Roman"; mso-ansi-language:#0400; mso-fareast-language:#0400; mso-bidi-language:#0400;} </style> <![endif]--><!--[if gte mso 9]><xml> <o:shapedefaults v:ext="edit" spidmax="5122"/> </xml><![endif]--><!--[if gte mso 9]><xml> <o:shapelayout v:ext="edit"> <o:idmap v:ext="edit" data="1"/> </o:shapelayout></xml><![endif]-->
+  <meta content="MCD Application Team" name="author"></head>
+<body link="blue" vlink="blue">
+<div class="Section1">
+<p class="MsoNormal"><span style="font-family: Arial;"><o:p><br>
+</o:p></span></p>
+<div align="center">
+<table class="MsoNormalTable" style="width: 675pt;" border="0" cellpadding="0" cellspacing="0" width="900">
+  <tbody>
+    <tr>
+      <td style="padding: 0cm;" valign="top">
+      <table class="MsoNormalTable" style="width: 675pt;" border="0" cellpadding="0" cellspacing="0" width="900">
+        <tbody>
+          <tr>
+            <td style="vertical-align: top;">
+            <p class="MsoNormal"><span style="font-size: 8pt; font-family: Arial; color: blue;"><a href="../../Release_Notes.html">Back to Release page</a><o:p></o:p></span></p>
+            </td>
+          </tr>
+          <tr style="">
+            <td style="padding: 1.5pt;">
+            <h1 style="margin-bottom: 18pt; text-align: center;" align="center"><span style="font-size: 20pt; font-family: Verdana; color: rgb(51, 102, 255);">Release
+Notes for STM32Cube Log Utilities Driver</span><span style="font-size: 20pt; font-family: Verdana;"><o:p></o:p></span></h1>
+            <p class="MsoNormal" style="text-align: center;" align="center"><span style="font-size: 10pt; font-family: Arial; color: black;">Copyright
+2016 STMicroelectronics</span><span style="color: black;"><u1:p></u1:p><o:p></o:p></span></p>
+            <p class="MsoNormal" style="text-align: center;" align="center"><span style="font-size: 10pt; font-family: Arial; color: black;"><img alt="" id="_x0000_i1025" src="../../_htmresc/st_logo.png" style="border: 0px solid ; width: 86px; height: 65px;"></span><span style="font-size: 10pt;"><o:p></o:p></span></p>
+            </td>
+          </tr>
+        </tbody>
+      </table>
+      <p class="MsoNormal"><span style="font-family: Arial; display: none;"><o:p>&nbsp;</o:p></span></p>
+      <table class="MsoNormalTable" style="width: 675pt;" border="0" cellpadding="0" width="900">
+        <tbody>
+          <tr style="">
+            <td style="padding: 0cm;" valign="top">
+            <span style="font-family: &quot;Times New Roman&quot;;"></span><h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial;"><a name="History"></a><span style="font-size: 12pt; color: white;">Update History</span></h2>
+            <h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 180px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.0.1 / 18-November-2016 <o:p></o:p></span></h3>
+
+            
+            <p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
+Changes<o:p></o:p></span></u></b></p>
+
+
+            
+            <ul style="list-style-type: square;"><li><span style="font-size: 10pt; font-family: Verdana;">Update the following macros implementation:</span></li><ul><li><span style="font-size: 10pt; font-family: Verdana;">LCD_ErrLog(...)</span></li><li><span style="font-size: 10pt; font-family: Verdana;">LCD_UsrLog(...)</span></li><li><span style="font-size: 10pt; font-family: Verdana;">LCD_DbgLog(...)<br></span></li></ul></ul>
+<span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic; font-weight: bold;"></span></span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic; font-weight: bold;"></span></span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic; font-weight: bold;"></span></span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic; font-weight: bold;"></span></span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic; font-weight: bold;"></span></span><span style="font-size: 10pt; font-family: Verdana;"></span><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 180px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.0.0 / 18-February-2014 <o:p></o:p></span></h3>
+
+            
+            <p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
+Changes<o:p></o:p></span></u></b></p>
+
+
+            
+            <ul style="list-style-type: square;">
+              <li><span style="font-size: 10pt; font-family: Verdana;">First official release<br>
+                </span></li>
+            </ul>
+<span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic; font-weight: bold;"></span></span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic; font-weight: bold;"></span></span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic; font-weight: bold;"></span></span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic; font-weight: bold;"></span></span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic; font-weight: bold;"></span></span><span style="font-size: 10pt; font-family: Verdana;"></span><h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial;"><a name="License"></a><span style="font-size: 12pt; color: white;">License<o:p></o:p></span><br></h2>
+            <div style="text-align: justify;"><font size="-1"><span style="font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are
+met:</span><br>
+            </font>
+            <ol><li><font size="-1"><span style="font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.</span><span style="font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"></span></font></li><li><font size="-1"><span style="font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Redistributions
+in binary form must reproduce the above copyright notice, this list of
+conditions and the following disclaimer in </span><span style="font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">the documentation and/or other materials provided with the distribution.</span><span style="font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"></span></font></li><li><font size="-1"><span style="font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived </span><br>
+                </font>
+              </li></ol>
+            <font size="-1"><span style="font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; from this software without specific prior written permission.</span><br>
+            <span style="font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"></span><br>
+            <span style="font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED</span><span style="font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"> WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A </span><span style="font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY </span><span style="font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, </span><span style="font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER</span><span style="font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"> CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR </span><span style="font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.</span></font>
+            
+            </div>
+<p class="MsoNormal"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;; color: black;"><o:p></o:p></span></p>
+<b><span style="font-size: 10pt; font-family: Verdana; color: black;"></span></b>
+            
+            <div class="MsoNormal" style="text-align: center;" align="center"><span style="color: black;">
+            <hr align="center" size="2" width="100%"></span></div>
+            <p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt; text-align: center;" align="center"><span style="font-size: 10pt; font-family: Verdana; color: black;">For
+complete documentation on </span><span style="font-size: 10pt; font-family: Verdana;">STM32<span style="color: black;">&nbsp;Microcontrollers
+visit </span><u><span style="color: blue;"><a href="http://www.st.com/internet/mcu/class/1734.jsp" target="_blank">www.st.com/STM32</a></span></u></span><span style="font-size: 10pt; font-family: Verdana;"><a target="_blank" href="http://www.st.com/internet/mcu/family/141.jsp"><u><span style="color: blue;"></span></u></a></span><span style="font-size: 10pt; font-family: Verdana;"><u><span style="color: blue;"></span></u></span><span style="color: black;"><o:p></o:p></span></p>
+            </td>
+          </tr>
+        </tbody>
+      </table>
+      <p class="MsoNormal"><span style="font-size: 10pt;"><o:p></o:p></span></p>
+      </td>
+    </tr>
+  </tbody>
+</table>
+</div>
+<p class="MsoNormal"><o:p>&nbsp;</o:p></p>
+</div>
+
+</body></html>
\ No newline at end of file
diff --git a/Utilities/Log/lcd_log.c b/Utilities/Log/lcd_log.c
new file mode 100644
index 0000000..034cce0
--- /dev/null
+++ b/Utilities/Log/lcd_log.c
@@ -0,0 +1,515 @@
+/**
+  ******************************************************************************
+  * @file    lcd_log.c
+  * @author  MCD Application Team
+  * @version V1.0.1
+  * @date    18-November-2016
+  * @brief   This file provides all the LCD Log firmware functions.
+  *          
+  *          The LCD Log module allows to automatically set a header and footer
+  *          on any application using the LCD display and allows to dump user,
+  *          debug and error messages by using the following macros: LCD_ErrLog(),
+  *          LCD_UsrLog() and LCD_DbgLog().
+  *         
+  *          It supports also the scroll feature by embedding an internal software
+  *          cache for display. This feature allows to dump message sequentially
+  *          on the display even if the number of displayed lines is bigger than
+  *          the total number of line allowed by the display.
+  *      
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include  <stdio.h>
+#include  "lcd_log.h"
+
+/** @addtogroup Utilities
+  * @{
+  */
+
+/** @addtogroup STM32_EVAL
+* @{
+*/
+
+/** @addtogroup Common
+  * @{
+  */
+
+/** @defgroup LCD_LOG 
+* @brief LCD Log LCD_Application module
+* @{
+*/ 
+
+/** @defgroup LCD_LOG_Private_Types
+* @{
+*/ 
+/**
+* @}
+*/ 
+
+
+/** @defgroup LCD_LOG_Private_Defines
+* @{
+*/ 
+
+/**
+* @}
+*/ 
+
+/* Define the display window settings */
+#define     YWINDOW_MIN         4
+
+/** @defgroup LCD_LOG_Private_Macros
+* @{
+*/ 
+/**
+* @}
+*/ 
+
+
+/** @defgroup LCD_LOG_Private_Variables
+* @{
+*/ 
+
+LCD_LOG_line LCD_CacheBuffer [LCD_CACHE_DEPTH]; 
+uint32_t LCD_LineColor;
+uint16_t LCD_CacheBuffer_xptr;
+uint16_t LCD_CacheBuffer_yptr_top;
+uint16_t LCD_CacheBuffer_yptr_bottom;
+
+uint16_t LCD_CacheBuffer_yptr_top_bak;
+uint16_t LCD_CacheBuffer_yptr_bottom_bak;
+
+FunctionalState LCD_CacheBuffer_yptr_invert;
+FunctionalState LCD_ScrollActive;
+FunctionalState LCD_Lock;
+FunctionalState LCD_Scrolled;
+uint16_t LCD_ScrollBackStep;
+
+/**
+* @}
+*/ 
+
+
+/** @defgroup LCD_LOG_Private_FunctionPrototypes
+* @{
+*/ 
+
+/**
+* @}
+*/ 
+
+
+/** @defgroup LCD_LOG_Private_Functions
+* @{
+*/ 
+
+
+/**
+  * @brief  Initializes the LCD Log module 
+  * @param  None
+  * @retval None
+  */
+
+void LCD_LOG_Init ( void)
+{
+  /* Deinit LCD cache */
+  LCD_LOG_DeInit();
+  
+  /* Clear the LCD */
+  BSP_LCD_Clear(LCD_LOG_BACKGROUND_COLOR);  
+}
+
+/**
+  * @brief DeInitializes the LCD Log module. 
+  * @param  None
+  * @retval None
+  */
+void LCD_LOG_DeInit(void)
+{
+  LCD_LineColor = LCD_LOG_TEXT_COLOR;
+  LCD_CacheBuffer_xptr = 0;
+  LCD_CacheBuffer_yptr_top = 0;
+  LCD_CacheBuffer_yptr_bottom = 0;
+  
+  LCD_CacheBuffer_yptr_top_bak = 0;
+  LCD_CacheBuffer_yptr_bottom_bak = 0;
+  
+  LCD_CacheBuffer_yptr_invert= ENABLE;
+  LCD_ScrollActive = DISABLE;
+  LCD_Lock = DISABLE;
+  LCD_Scrolled = DISABLE;
+  LCD_ScrollBackStep = 0;
+}
+
+/**
+  * @brief  Display the application header on the LCD screen 
+  * @param  header: pointer to the string to be displayed
+  * @retval None
+  */
+void LCD_LOG_SetHeader (uint8_t *header)
+{
+  /* Set the LCD Font */
+  BSP_LCD_SetFont (&LCD_LOG_HEADER_FONT);
+
+  BSP_LCD_SetTextColor(LCD_LOG_SOLID_BACKGROUND_COLOR);
+  BSP_LCD_FillRect(0, 0, BSP_LCD_GetXSize(), LCD_LOG_HEADER_FONT.Height * 3);
+  
+  /* Set the LCD Text Color */
+  BSP_LCD_SetTextColor(LCD_LOG_SOLID_TEXT_COLOR);
+  BSP_LCD_SetBackColor(LCD_LOG_SOLID_BACKGROUND_COLOR);
+
+  BSP_LCD_DisplayStringAt(0, LCD_LOG_HEADER_FONT.Height, header, CENTER_MODE);
+
+  BSP_LCD_SetBackColor(LCD_LOG_BACKGROUND_COLOR);
+  BSP_LCD_SetTextColor(LCD_LOG_TEXT_COLOR);
+  BSP_LCD_SetFont (&LCD_LOG_TEXT_FONT);
+}
+
+/**
+  * @brief  Display the application footer on the LCD screen 
+  * @param  footer: pointer to the string to be displayed
+  * @retval None
+  */
+void LCD_LOG_SetFooter(uint8_t *footer)
+{
+  /* Set the LCD Font */
+  BSP_LCD_SetFont (&LCD_LOG_FOOTER_FONT);
+
+  BSP_LCD_SetTextColor(LCD_LOG_SOLID_BACKGROUND_COLOR);
+  BSP_LCD_FillRect(0, BSP_LCD_GetYSize() - LCD_LOG_FOOTER_FONT.Height - 4, BSP_LCD_GetXSize(), LCD_LOG_FOOTER_FONT.Height + 4);
+  
+  /* Set the LCD Text Color */
+  BSP_LCD_SetTextColor(LCD_LOG_SOLID_TEXT_COLOR);
+  BSP_LCD_SetBackColor(LCD_LOG_SOLID_BACKGROUND_COLOR);
+
+  BSP_LCD_DisplayStringAt(0, BSP_LCD_GetYSize() - LCD_LOG_FOOTER_FONT.Height, footer, CENTER_MODE);
+
+  BSP_LCD_SetBackColor(LCD_LOG_BACKGROUND_COLOR);
+  BSP_LCD_SetTextColor(LCD_LOG_TEXT_COLOR);
+  BSP_LCD_SetFont (&LCD_LOG_TEXT_FONT);
+}
+
+/**
+  * @brief  Clear the Text Zone 
+  * @param  None 
+  * @retval None
+  */
+void LCD_LOG_ClearTextZone(void)
+{
+  uint8_t i=0;
+  
+  for (i= 0 ; i < YWINDOW_SIZE; i++)
+  {
+    BSP_LCD_ClearStringLine(i + YWINDOW_MIN);
+  }
+  
+  LCD_LOG_DeInit();
+}
+
+/**
+  * @brief  Redirect the printf to the LCD
+  * @param  c: character to be displayed
+  * @param  f: output file pointer
+  * @retval None
+ */
+LCD_LOG_PUTCHAR
+{
+  
+  sFONT *cFont = BSP_LCD_GetFont();
+  uint32_t idx;
+  
+  if(LCD_Lock == DISABLE)
+  {
+    if(LCD_ScrollActive == ENABLE)
+    {
+      LCD_CacheBuffer_yptr_bottom = LCD_CacheBuffer_yptr_bottom_bak;
+      LCD_CacheBuffer_yptr_top    = LCD_CacheBuffer_yptr_top_bak;
+      LCD_ScrollActive = DISABLE;
+      LCD_Scrolled = DISABLE;
+      LCD_ScrollBackStep = 0;
+      
+    }
+    
+    if(( LCD_CacheBuffer_xptr < (BSP_LCD_GetXSize()) /cFont->Width ) &&  ( ch != '\n'))
+    {
+      LCD_CacheBuffer[LCD_CacheBuffer_yptr_bottom].line[LCD_CacheBuffer_xptr++] = (uint16_t)ch;
+    }   
+    else 
+    {
+      if(LCD_CacheBuffer_yptr_top >= LCD_CacheBuffer_yptr_bottom)
+      {
+        
+        if(LCD_CacheBuffer_yptr_invert == DISABLE)
+        {
+          LCD_CacheBuffer_yptr_top++;
+          
+          if(LCD_CacheBuffer_yptr_top == LCD_CACHE_DEPTH)
+          {
+            LCD_CacheBuffer_yptr_top = 0;  
+          }
+        }
+        else
+        {
+          LCD_CacheBuffer_yptr_invert= DISABLE;
+        }
+      }
+      
+      for(idx = LCD_CacheBuffer_xptr ; idx < (BSP_LCD_GetXSize()) /cFont->Width; idx++)
+      {
+        LCD_CacheBuffer[LCD_CacheBuffer_yptr_bottom].line[LCD_CacheBuffer_xptr++] = ' ';
+      }   
+      LCD_CacheBuffer[LCD_CacheBuffer_yptr_bottom].color = LCD_LineColor;  
+      
+      LCD_CacheBuffer_xptr = 0;
+      
+      LCD_LOG_UpdateDisplay (); 
+      
+      LCD_CacheBuffer_yptr_bottom ++; 
+      
+      if (LCD_CacheBuffer_yptr_bottom == LCD_CACHE_DEPTH) 
+      {
+        LCD_CacheBuffer_yptr_bottom = 0;
+        LCD_CacheBuffer_yptr_top = 1;    
+        LCD_CacheBuffer_yptr_invert = ENABLE;
+      }
+      
+      if( ch != '\n')
+      {
+        LCD_CacheBuffer[LCD_CacheBuffer_yptr_bottom].line[LCD_CacheBuffer_xptr++] = (uint16_t)ch;
+      }
+      
+    }
+  }
+  return ch;
+}
+  
+/**
+  * @brief  Update the text area display
+  * @param  None
+  * @retval None
+  */
+void LCD_LOG_UpdateDisplay (void)
+{
+  uint8_t cnt = 0 ;
+  uint16_t length = 0 ;
+  uint16_t ptr = 0, index = 0;
+  
+  if((LCD_CacheBuffer_yptr_bottom  < (YWINDOW_SIZE -1)) && 
+     (LCD_CacheBuffer_yptr_bottom  >= LCD_CacheBuffer_yptr_top))
+  {
+    BSP_LCD_SetTextColor(LCD_CacheBuffer[cnt + LCD_CacheBuffer_yptr_bottom].color);
+    BSP_LCD_DisplayStringAtLine ((YWINDOW_MIN + LCD_CacheBuffer_yptr_bottom),
+                           (uint8_t *)(LCD_CacheBuffer[cnt + LCD_CacheBuffer_yptr_bottom].line));
+  }
+  else
+  {
+    
+    if(LCD_CacheBuffer_yptr_bottom < LCD_CacheBuffer_yptr_top)
+    {
+      /* Virtual length for rolling */
+      length = LCD_CACHE_DEPTH + LCD_CacheBuffer_yptr_bottom ;
+    }
+    else
+    {
+      length = LCD_CacheBuffer_yptr_bottom;
+    }
+    
+    ptr = length - YWINDOW_SIZE + 1;
+    
+    for  (cnt = 0 ; cnt < YWINDOW_SIZE ; cnt ++)
+    {
+      
+      index = (cnt + ptr )% LCD_CACHE_DEPTH ;
+      
+      BSP_LCD_SetTextColor(LCD_CacheBuffer[index].color);
+      BSP_LCD_DisplayStringAtLine ((cnt + YWINDOW_MIN), 
+                             (uint8_t *)(LCD_CacheBuffer[index].line));
+      
+    }
+  }
+  
+}
+
+#if( LCD_SCROLL_ENABLED == 1)
+/**
+  * @brief  Display previous text frame
+  * @param  None
+  * @retval Status
+  */
+ErrorStatus LCD_LOG_ScrollBack(void)
+{
+    
+  if(LCD_ScrollActive == DISABLE)
+  {
+    
+    LCD_CacheBuffer_yptr_bottom_bak = LCD_CacheBuffer_yptr_bottom;
+    LCD_CacheBuffer_yptr_top_bak    = LCD_CacheBuffer_yptr_top;
+    
+    
+    if(LCD_CacheBuffer_yptr_bottom > LCD_CacheBuffer_yptr_top) 
+    {
+      
+      if ((LCD_CacheBuffer_yptr_bottom - LCD_CacheBuffer_yptr_top) <=  YWINDOW_SIZE)
+      {
+        LCD_Lock = DISABLE;
+        return ERROR;
+      }
+    }
+    LCD_ScrollActive = ENABLE;
+    
+    if((LCD_CacheBuffer_yptr_bottom  > LCD_CacheBuffer_yptr_top)&&
+       (LCD_Scrolled == DISABLE ))
+    {
+      LCD_CacheBuffer_yptr_bottom--;
+      LCD_Scrolled = ENABLE;
+    }
+    
+  }
+  
+  if(LCD_ScrollActive == ENABLE)
+  {
+    LCD_Lock = ENABLE;
+    
+    if(LCD_CacheBuffer_yptr_bottom > LCD_CacheBuffer_yptr_top) 
+    {
+      
+      if((LCD_CacheBuffer_yptr_bottom  - LCD_CacheBuffer_yptr_top) <  YWINDOW_SIZE )
+      {
+        LCD_Lock = DISABLE;
+        return ERROR;
+      }
+      
+      LCD_CacheBuffer_yptr_bottom --;
+    }
+    else if(LCD_CacheBuffer_yptr_bottom <= LCD_CacheBuffer_yptr_top)
+    {
+      
+      if((LCD_CACHE_DEPTH  - LCD_CacheBuffer_yptr_top + LCD_CacheBuffer_yptr_bottom) < YWINDOW_SIZE)
+      {
+        LCD_Lock = DISABLE;
+        return ERROR;
+      }
+      LCD_CacheBuffer_yptr_bottom --;
+      
+      if(LCD_CacheBuffer_yptr_bottom == 0xFFFF)
+      {
+        LCD_CacheBuffer_yptr_bottom = LCD_CACHE_DEPTH - 2;
+      }
+    }
+    LCD_ScrollBackStep++;
+    LCD_LOG_UpdateDisplay();
+    LCD_Lock = DISABLE;
+  }
+  return SUCCESS;
+}
+
+/**
+  * @brief  Display next text frame
+  * @param  None
+  * @retval Status
+  */
+ErrorStatus LCD_LOG_ScrollForward(void)
+{
+  
+  if(LCD_ScrollBackStep != 0)
+  {
+    if(LCD_ScrollActive == DISABLE)
+    {
+      
+      LCD_CacheBuffer_yptr_bottom_bak = LCD_CacheBuffer_yptr_bottom;
+      LCD_CacheBuffer_yptr_top_bak    = LCD_CacheBuffer_yptr_top;
+      
+      if(LCD_CacheBuffer_yptr_bottom > LCD_CacheBuffer_yptr_top) 
+      {
+        
+        if ((LCD_CacheBuffer_yptr_bottom - LCD_CacheBuffer_yptr_top) <=  YWINDOW_SIZE)
+        {
+          LCD_Lock = DISABLE;
+          return ERROR;
+        }
+      }
+      LCD_ScrollActive = ENABLE;
+      
+      if((LCD_CacheBuffer_yptr_bottom  > LCD_CacheBuffer_yptr_top)&&
+         (LCD_Scrolled == DISABLE ))
+      {
+        LCD_CacheBuffer_yptr_bottom--;
+        LCD_Scrolled = ENABLE;
+      }
+      
+    }
+    
+    if(LCD_ScrollActive == ENABLE)
+    {
+      LCD_Lock = ENABLE;
+      LCD_ScrollBackStep--;
+      
+      if(++LCD_CacheBuffer_yptr_bottom == LCD_CACHE_DEPTH)
+      {
+        LCD_CacheBuffer_yptr_bottom = 0;
+      }
+      
+      LCD_LOG_UpdateDisplay();
+      LCD_Lock = DISABLE;
+      
+    } 
+    return SUCCESS;
+  }
+  else // LCD_ScrollBackStep == 0 
+  {
+    LCD_Lock = DISABLE;
+    return ERROR;
+  }  
+}
+#endif /* LCD_SCROLL_ENABLED */
+
+/**
+  * @}
+  */
+  
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Utilities/Log/lcd_log.h b/Utilities/Log/lcd_log.h
new file mode 100644
index 0000000..2c81ef8
--- /dev/null
+++ b/Utilities/Log/lcd_log.h
@@ -0,0 +1,170 @@
+/**
+  ******************************************************************************
+  * @file    lcd_log.h
+  * @author  MCD Application Team
+  * @version V1.0.1
+  * @date    18-November-2016
+  * @brief   header for the lcd_log.c file
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */ 
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef  __LCD_LOG_H__
+#define  __LCD_LOG_H__
+
+/* Includes ------------------------------------------------------------------*/
+
+#include "lcd_log_conf.h"
+
+/** @addtogroup Utilities
+  * @{
+  */
+  
+/** @addtogroup STM32_EVAL
+  * @{
+  */ 
+
+/** @addtogroup Common
+  * @{
+  */
+
+/** @addtogroup LCD_LOG
+  * @{
+  */
+  
+/** @defgroup LCD_LOG
+  * @brief 
+  * @{
+  */ 
+
+
+/** @defgroup LCD_LOG_Exported_Defines
+  * @{
+  */ 
+
+#if (LCD_SCROLL_ENABLED == 1)
+ #define     LCD_CACHE_DEPTH     (YWINDOW_SIZE + CACHE_SIZE)
+#else
+ #define     LCD_CACHE_DEPTH     YWINDOW_SIZE
+#endif
+/**
+  * @}
+  */ 
+
+/** @defgroup LCD_LOG_Exported_Types
+  * @{
+  */ 
+typedef struct _LCD_LOG_line
+{
+  uint8_t  line[128];
+  uint32_t color;
+
+}LCD_LOG_line;
+
+/**
+  * @}
+  */ 
+
+/** @defgroup LCD_LOG_Exported_Macros
+  * @{
+  */ 
+#define  LCD_ErrLog(...)    do { \
+                                 LCD_LineColor = LCD_COLOR_RED;\
+                                 printf("ERROR: ") ;\
+                                 printf(__VA_ARGS__);\
+                                 LCD_LineColor = LCD_LOG_DEFAULT_COLOR;\
+                               }while (0)
+
+#define  LCD_UsrLog(...)    do { \
+	                             LCD_LineColor = LCD_LOG_TEXT_COLOR;\
+                                 printf(__VA_ARGS__);\
+                               } while (0)
+
+
+#define  LCD_DbgLog(...)    do { \
+                                 LCD_LineColor = LCD_COLOR_CYAN;\
+                                 printf(__VA_ARGS__);\
+                                 LCD_LineColor = LCD_LOG_DEFAULT_COLOR;\
+                               }while (0)
+/**
+  * @}
+  */ 
+
+/** @defgroup LCD_LOG_Exported_Variables
+  * @{
+  */ 
+extern uint32_t LCD_LineColor;
+
+/**
+  * @}
+  */ 
+
+/** @defgroup LCD_LOG_Exported_FunctionsPrototype
+  * @{
+  */ 
+void LCD_LOG_Init(void);
+void LCD_LOG_DeInit(void);
+void LCD_LOG_SetHeader(uint8_t *Title);
+void LCD_LOG_SetFooter(uint8_t *Status);
+void LCD_LOG_ClearTextZone(void);
+void LCD_LOG_UpdateDisplay (void);
+
+#if (LCD_SCROLL_ENABLED == 1)
+ ErrorStatus LCD_LOG_ScrollBack(void);
+ ErrorStatus LCD_LOG_ScrollForward(void);
+#endif
+/**
+  * @}
+  */ 
+
+
+#endif /* __LCD_LOG_H__ */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */  
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Utilities/Log/lcd_log_conf_template.h b/Utilities/Log/lcd_log_conf_template.h
new file mode 100644
index 0000000..b315fc9
--- /dev/null
+++ b/Utilities/Log/lcd_log_conf_template.h
@@ -0,0 +1,146 @@
+/**
+  ******************************************************************************
+  * @file    lcd_log_conf_template.h
+  * @author  MCD Application Team
+  * @version V1.0.1
+  * @date    18-November-2016
+  * @brief   lcd_log configuration template file.
+  *          This file should be copied to the application folder and modified 
+  *          as follows:
+  *            - Rename it to 'lcd_log_conf.h'.
+  *            - Update the name of the LCD driver's header file, depending on
+  *               the EVAL board you are using, see line40 below (be default this  
+  *               file will generate compile error unless you do this modification).
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+
+#ifndef  __LCD_LOG_CONF_H__
+#define  __LCD_LOG_CONF_H__
+
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32xxx_eval_lcd.h" /* replace 'stm32xxx' with your EVAL board name, ex: stm324x9i_eval_lcd.h */
+#include <stdio.h>
+
+
+/** @addtogroup LCD_LOG
+  * @{
+  */
+  
+/** @defgroup LCD_LOG
+  * @brief This file is the 
+  * @{
+  */ 
+
+
+/** @defgroup LCD_LOG_CONF_Exported_Defines
+  * @{
+  */ 
+
+/* Comment the line below to disable the scroll back and forward features */
+#define     LCD_SCROLL_ENABLED      1 
+
+/* Define the Fonts  */
+#define     LCD_LOG_HEADER_FONT                   Font16
+#define     LCD_LOG_FOOTER_FONT                   Font12
+#define     LCD_LOG_TEXT_FONT                     Font12
+            
+/* Define the LCD LOG Color  */
+#define     LCD_LOG_BACKGROUND_COLOR              LCD_COLOR_WHITE
+#define     LCD_LOG_TEXT_COLOR                    LCD_COLOR_DARKBLUE
+
+#define     LCD_LOG_SOLID_BACKGROUND_COLOR        LCD_COLOR_BLUE
+#define     LCD_LOG_SOLID_TEXT_COLOR              LCD_COLOR_WHITE
+
+/* Define the cache depth */
+#define     CACHE_SIZE              100
+#define     YWINDOW_SIZE            17
+
+#if (YWINDOW_SIZE > 17)
+  #error "Wrong YWINDOW SIZE"
+#endif
+
+/* Redirect the printf to the LCD */
+#ifdef __GNUC__
+/* With GCC/RAISONANCE, small printf (option LD Linker->Libraries->Small printf
+   set to 'Yes') calls __io_putchar() */
+#define LCD_LOG_PUTCHAR int __io_putchar(int ch)
+#else
+#define LCD_LOG_PUTCHAR int fputc(int ch, FILE *f)
+#endif /* __GNUC__ */
+
+/** @defgroup LCD_LOG_CONF_Exported_TypesDefinitions
+  * @{
+  */ 
+
+/**
+  * @}
+  */ 
+
+
+/** @defgroup LCD_LOG_Exported_Macros
+  * @{
+  */ 
+
+
+/**
+  * @}
+  */ 
+
+/** @defgroup LCD_LOG_CONF_Exported_Variables
+  * @{
+  */ 
+
+/**
+  * @}
+  */ 
+
+/** @defgroup LCD_LOG_CONF_Exported_FunctionsPrototype
+  * @{
+  */ 
+
+/**
+  * @}
+  */ 
+
+
+#endif //__LCD_LOG_CONF_H__
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/eez-flow-template-stm32f469i-disco Debug.launch b/eez-flow-template-stm32f469i-disco Debug.launch
new file mode 100644
index 0000000..1b5d2aa
--- /dev/null
+++ b/eez-flow-template-stm32f469i-disco Debug.launch	
@@ -0,0 +1,80 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<launchConfiguration type="com.st.stm32cube.ide.mcu.debug.launch.launchConfigurationType">
+    <stringAttribute key="com.st.stm32cube.ide.mcu.debug.launch.access_port_id" value="0"/>
+    <booleanAttribute key="com.st.stm32cube.ide.mcu.debug.launch.enable_live_expr" value="true"/>
+    <booleanAttribute key="com.st.stm32cube.ide.mcu.debug.launch.enable_swv" value="false"/>
+    <intAttribute key="com.st.stm32cube.ide.mcu.debug.launch.formatVersion" value="2"/>
+    <stringAttribute key="com.st.stm32cube.ide.mcu.debug.launch.ip_address_local" value="localhost"/>
+    <booleanAttribute key="com.st.stm32cube.ide.mcu.debug.launch.limit_swo_clock.enabled" value="false"/>
+    <stringAttribute key="com.st.stm32cube.ide.mcu.debug.launch.limit_swo_clock.value" value=""/>
+    <stringAttribute key="com.st.stm32cube.ide.mcu.debug.launch.loadList" value="{&quot;fItems&quot;:[{&quot;fIsFromMainTab&quot;:true,&quot;fPath&quot;:&quot;Debug/eez-flow-template-stm32f469i-disco.elf&quot;,&quot;fProjectName&quot;:&quot;eez-flow-template-stm32f469i-disco&quot;,&quot;fPerformBuild&quot;:true,&quot;fDownload&quot;:true,&quot;fLoadSymbols&quot;:true}]}"/>
+    <stringAttribute key="com.st.stm32cube.ide.mcu.debug.launch.override_start_address_mode" value="default"/>
+    <stringAttribute key="com.st.stm32cube.ide.mcu.debug.launch.remoteCommand" value="target remote"/>
+    <booleanAttribute key="com.st.stm32cube.ide.mcu.debug.launch.startServer" value="true"/>
+    <booleanAttribute key="com.st.stm32cube.ide.mcu.debug.launch.startuptab.exception.divby0" value="true"/>
+    <booleanAttribute key="com.st.stm32cube.ide.mcu.debug.launch.startuptab.exception.unaligned" value="false"/>
+    <booleanAttribute key="com.st.stm32cube.ide.mcu.debug.launch.startuptab.haltonexception" value="true"/>
+    <booleanAttribute key="com.st.stm32cube.ide.mcu.debug.launch.swd_mode" value="true"/>
+    <stringAttribute key="com.st.stm32cube.ide.mcu.debug.launch.swv_port" value="61235"/>
+    <stringAttribute key="com.st.stm32cube.ide.mcu.debug.launch.swv_trace_hclk" value="16000000"/>
+    <booleanAttribute key="com.st.stm32cube.ide.mcu.debug.launch.useRemoteTarget" value="true"/>
+    <stringAttribute key="com.st.stm32cube.ide.mcu.debug.launch.vector_table" value=""/>
+    <booleanAttribute key="com.st.stm32cube.ide.mcu.debug.launch.verify_flash_download" value="true"/>
+    <booleanAttribute key="com.st.stm32cube.ide.mcu.debug.stlink.cti_allow_halt" value="false"/>
+    <booleanAttribute key="com.st.stm32cube.ide.mcu.debug.stlink.cti_signal_halt" value="false"/>
+    <booleanAttribute key="com.st.stm32cube.ide.mcu.debug.stlink.enable_external_loader" value="false"/>
+    <booleanAttribute key="com.st.stm32cube.ide.mcu.debug.stlink.enable_logging" value="false"/>
+    <booleanAttribute key="com.st.stm32cube.ide.mcu.debug.stlink.enable_max_halt_delay" value="false"/>
+    <booleanAttribute key="com.st.stm32cube.ide.mcu.debug.stlink.enable_shared_stlink" value="false"/>
+    <stringAttribute key="com.st.stm32cube.ide.mcu.debug.stlink.external_loader" value=""/>
+    <booleanAttribute key="com.st.stm32cube.ide.mcu.debug.stlink.external_loader_init" value="false"/>
+    <stringAttribute key="com.st.stm32cube.ide.mcu.debug.stlink.frequency" value="0"/>
+    <booleanAttribute key="com.st.stm32cube.ide.mcu.debug.stlink.halt_all_on_reset" value="false"/>
+    <stringAttribute key="com.st.stm32cube.ide.mcu.debug.stlink.log_file" value="C:\work\eez\eez-flow-template-stm32f469i-disco\Debug\st-link_gdbserver_log.txt"/>
+    <stringAttribute key="com.st.stm32cube.ide.mcu.debug.stlink.low_power_debug" value="enable"/>
+    <stringAttribute key="com.st.stm32cube.ide.mcu.debug.stlink.max_halt_delay" value="2"/>
+    <stringAttribute key="com.st.stm32cube.ide.mcu.debug.stlink.reset_strategy" value="connect_under_reset"/>
+    <booleanAttribute key="com.st.stm32cube.ide.mcu.debug.stlink.stlink_check_serial_number" value="false"/>
+    <stringAttribute key="com.st.stm32cube.ide.mcu.debug.stlink.stlink_txt_serial_number" value=""/>
+    <stringAttribute key="com.st.stm32cube.ide.mcu.debug.stlink.watchdog_config" value="none"/>
+    <booleanAttribute key="com.st.stm32cube.ide.mcu.debug.stlinkenable_rtos" value="false"/>
+    <stringAttribute key="com.st.stm32cube.ide.mcu.debug.stlinkrestart_configurations" value="{&quot;fVersion&quot;:1,&quot;fItems&quot;:[{&quot;fDisplayName&quot;:&quot;Reset&quot;,&quot;fIsSuppressible&quot;:false,&quot;fResetAttribute&quot;:&quot;Software system reset&quot;,&quot;fResetStrategies&quot;:[{&quot;fDisplayName&quot;:&quot;Software system reset&quot;,&quot;fLaunchAttribute&quot;:&quot;system_reset&quot;,&quot;fGdbCommands&quot;:[&quot;monitor reset\r\n&quot;],&quot;fCmdOptions&quot;:[&quot;-g&quot;]},{&quot;fDisplayName&quot;:&quot;Hardware reset&quot;,&quot;fLaunchAttribute&quot;:&quot;hardware_reset&quot;,&quot;fGdbCommands&quot;:[&quot;monitor reset hardware\r\n&quot;],&quot;fCmdOptions&quot;:[&quot;-g&quot;]},{&quot;fDisplayName&quot;:&quot;Core reset&quot;,&quot;fLaunchAttribute&quot;:&quot;core_reset&quot;,&quot;fGdbCommands&quot;:[&quot;monitor reset core\r\n&quot;],&quot;fCmdOptions&quot;:[&quot;-g&quot;]},{&quot;fDisplayName&quot;:&quot;None&quot;,&quot;fLaunchAttribute&quot;:&quot;no_reset&quot;,&quot;fGdbCommands&quot;:[],&quot;fCmdOptions&quot;:[&quot;-g&quot;]}],&quot;fGdbCommandGroup&quot;:{&quot;name&quot;:&quot;Additional commands&quot;,&quot;commands&quot;:[]},&quot;fStartApplication&quot;:true}]}"/>
+    <booleanAttribute key="com.st.stm32cube.ide.mcu.rtosproxy.enableRtosProxy" value="false"/>
+    <stringAttribute key="com.st.stm32cube.ide.mcu.rtosproxy.rtosProxyCustomProperties" value=""/>
+    <stringAttribute key="com.st.stm32cube.ide.mcu.rtosproxy.rtosProxyDriver" value="threadx"/>
+    <booleanAttribute key="com.st.stm32cube.ide.mcu.rtosproxy.rtosProxyDriverAuto" value="false"/>
+    <stringAttribute key="com.st.stm32cube.ide.mcu.rtosproxy.rtosProxyDriverPort" value="cortex_m0"/>
+    <intAttribute key="com.st.stm32cube.ide.mcu.rtosproxy.rtosProxyPort" value="60000"/>
+    <booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.doHalt" value="false"/>
+    <booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.doReset" value="false"/>
+    <stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.initCommands" value=""/>
+    <stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.ipAddress" value="localhost"/>
+    <stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.jtagDeviceId" value="com.st.stm32cube.ide.mcu.debug.stlink"/>
+    <stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.pcRegister" value=""/>
+    <intAttribute key="org.eclipse.cdt.debug.gdbjtag.core.portNumber" value="61234"/>
+    <stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.runCommands" value=""/>
+    <booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setPcRegister" value="false"/>
+    <booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setResume" value="true"/>
+    <booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setStopAt" value="true"/>
+    <stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.stopAt" value="main"/>
+    <stringAttribute key="org.eclipse.cdt.dsf.gdb.DEBUG_NAME" value="arm-none-eabi-gdb"/>
+    <booleanAttribute key="org.eclipse.cdt.dsf.gdb.NON_STOP" value="false"/>
+    <booleanAttribute key="org.eclipse.cdt.dsf.gdb.UPDATE_THREADLIST_ON_SUSPEND" value="false"/>
+    <intAttribute key="org.eclipse.cdt.launch.ATTR_BUILD_BEFORE_LAUNCH_ATTR" value="2"/>
+    <stringAttribute key="org.eclipse.cdt.launch.COREFILE_PATH" value=""/>
+    <stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_START_MODE" value="remote"/>
+    <booleanAttribute key="org.eclipse.cdt.launch.DEBUGGER_STOP_AT_MAIN" value="true"/>
+    <stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_STOP_AT_MAIN_SYMBOL" value="main"/>
+    <stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="Debug/eez-flow-template-stm32f469i-disco.elf"/>
+    <stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="eez-flow-template-stm32f469i-disco"/>
+    <booleanAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_AUTO_ATTR" value="true"/>
+    <stringAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_ID_ATTR" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.debug.460065682"/>
+    <listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
+        <listEntry value="/eez-flow-template-stm32f469i-disco"/>
+    </listAttribute>
+    <listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
+        <listEntry value="4"/>
+    </listAttribute>
+    <stringAttribute key="org.eclipse.dsf.launch.MEMORY_BLOCKS" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&lt;memoryBlockExpressionList context=&quot;reserved-for-future-use&quot;/&gt;"/>
+    <stringAttribute key="process_factory_id" value="com.st.stm32cube.ide.mcu.debug.launch.HardwareDebugProcessFactory"/>
+</launchConfiguration>
diff --git a/eez-flow-template-stm32f469i-disco.ioc b/eez-flow-template-stm32f469i-disco.ioc
new file mode 100644
index 0000000..44b4c84
--- /dev/null
+++ b/eez-flow-template-stm32f469i-disco.ioc
@@ -0,0 +1,1263 @@
+#MicroXplorer Configuration settings - do not modify
+DSIHOST.IPParameters=NumberOfLanes,StopWaitTime,TEAcknowledgeRequest,LPGenShortWriteNoP,LPGenShortWriteOneP,LPGenShortWriteTwoP,LPGenShortReadNoP,LPGenShortReadOneP,LPGenShortReadTwoP,LPGenLongWrite,LPDcsShortWriteNoP,LPDcsShortWriteOneP,LPDcsShortReadNoP,LPDcsLongWrite,LPMaxReadPacket
+DSIHOST.LPDcsLongWrite=DSI_LP_DLW_ENABLE
+DSIHOST.LPDcsShortReadNoP=DSI_LP_DSR0P_ENABLE
+DSIHOST.LPDcsShortWriteNoP=DSI_LP_DSW0P_ENABLE
+DSIHOST.LPDcsShortWriteOneP=DSI_LP_DSW1P_ENABLE
+DSIHOST.LPGenLongWrite=DSI_LP_GLW_ENABLE
+DSIHOST.LPGenShortReadNoP=DSI_LP_GSR0P_ENABLE
+DSIHOST.LPGenShortReadOneP=DSI_LP_GSR1P_ENABLE
+DSIHOST.LPGenShortReadTwoP=DSI_LP_GSR2P_ENABLE
+DSIHOST.LPGenShortWriteNoP=DSI_LP_GSW0P_ENABLE
+DSIHOST.LPGenShortWriteOneP=DSI_LP_GSW1P_ENABLE
+DSIHOST.LPGenShortWriteTwoP=DSI_LP_GSW2P_ENABLE
+DSIHOST.LPMaxReadPacket=DSI_LP_MRDP_ENABLE
+DSIHOST.NumberOfLanes=DSI_TWO_DATA_LANES
+DSIHOST.StopWaitTime=10
+DSIHOST.TEAcknowledgeRequest=DSI_TE_ACKNOWLEDGE_ENABLE
+DSIHOST_CKN.GPIOParameters=GPIO_Label
+DSIHOST_CKN.GPIO_Label=DSI_CK_N
+DSIHOST_CKN.Locked=true
+DSIHOST_CKN.Mode=DSIHost_Adapted_TE
+DSIHOST_CKN.Signal=DSIHOST_CKN
+DSIHOST_CKP.GPIOParameters=GPIO_Label
+DSIHOST_CKP.GPIO_Label=DSI_CK_P
+DSIHOST_CKP.Locked=true
+DSIHOST_CKP.Mode=DSIHost_Adapted_TE
+DSIHOST_CKP.Signal=DSIHOST_CKP
+DSIHOST_D0N.GPIOParameters=GPIO_Label
+DSIHOST_D0N.GPIO_Label=DSI_D0_N
+DSIHOST_D0N.Locked=true
+DSIHOST_D0N.Mode=DSIHost_Adapted_TE
+DSIHOST_D0N.Signal=DSIHOST_D0N
+DSIHOST_D0P.GPIOParameters=GPIO_Label
+DSIHOST_D0P.GPIO_Label=DSI_D0_P
+DSIHOST_D0P.Locked=true
+DSIHOST_D0P.Mode=DSIHost_Adapted_TE
+DSIHOST_D0P.Signal=DSIHOST_D0P
+DSIHOST_D1N.GPIOParameters=GPIO_Label
+DSIHOST_D1N.GPIO_Label=DSI_D1_N
+DSIHOST_D1N.Locked=true
+DSIHOST_D1N.Mode=DSIHost_Adapted_TE
+DSIHOST_D1N.Signal=DSIHOST_D1N
+DSIHOST_D1P.GPIOParameters=GPIO_Label
+DSIHOST_D1P.GPIO_Label=DSI_D1_P
+DSIHOST_D1P.Locked=true
+DSIHOST_D1P.Mode=DSIHost_Adapted_TE
+DSIHOST_D1P.Signal=DSIHOST_D1P
+FATFS.BSP.number=1
+FATFS0.BSP.STBoard=false
+FATFS0.BSP.api=UnknownBspDriver
+FATFS0.BSP.component=
+FATFS0.BSP.condition=
+FATFS0.BSP.instance=PG2
+FATFS0.BSP.ip=GPIO
+FATFS0.BSP.mode=Input
+FATFS0.BSP.name=Detect_SDIO
+FATFS0.BSP.semaphore=
+FATFS0.BSP.solution=PG2
+FMC.CASLatency1=FMC_SDRAM_CAS_LATENCY_3
+FMC.ExitSelfRefreshDelay1=7
+FMC.IPParameters=CASLatency1,SDClockPeriod1,SDClockPeriod2,ReadBurst1,ReadBurst2,LoadToActiveDelay1,ExitSelfRefreshDelay1,SelfRefreshTime1,RowCycleDelay1,RowCycleDelay2,WriteRecoveryTime1,RPDelay1,RPDelay2,RCDDelay1
+FMC.LoadToActiveDelay1=2
+FMC.RCDDelay1=2
+FMC.RPDelay1=2
+FMC.RPDelay2=2
+FMC.ReadBurst1=FMC_SDRAM_RBURST_ENABLE
+FMC.ReadBurst2=FMC_SDRAM_RBURST_ENABLE
+FMC.RowCycleDelay1=7
+FMC.RowCycleDelay2=7
+FMC.SDClockPeriod1=FMC_SDRAM_CLOCK_PERIOD_2
+FMC.SDClockPeriod2=FMC_SDRAM_CLOCK_PERIOD_2
+FMC.SelfRefreshTime1=4
+FMC.WriteRecoveryTime1=3
+FREERTOS.IPParameters=Tasks01,configUSE_RECURSIVE_MUTEXES,configUSE_COUNTING_SEMAPHORES,configUSE_APPLICATION_TASK_TAG,configTOTAL_HEAP_SIZE,configUSE_IDLE_HOOK,configUSE_MALLOC_FAILED_HOOK,configCHECK_FOR_STACK_OVERFLOW,configUSE_NEWLIB_REENTRANT
+FREERTOS.Tasks01=defaultTask,24,4096,StartDefaultTask,Default,NULL,Dynamic,NULL,NULL
+FREERTOS.configCHECK_FOR_STACK_OVERFLOW=2
+FREERTOS.configTOTAL_HEAP_SIZE=32768
+FREERTOS.configUSE_APPLICATION_TASK_TAG=1
+FREERTOS.configUSE_COUNTING_SEMAPHORES=1
+FREERTOS.configUSE_IDLE_HOOK=1
+FREERTOS.configUSE_MALLOC_FAILED_HOOK=1
+FREERTOS.configUSE_NEWLIB_REENTRANT=1
+FREERTOS.configUSE_RECURSIVE_MUTEXES=1
+File.Version=6
+KeepUserPlacement=false
+LTDC.ActiveW=200
+LTDC.Alpha_L0=255
+LTDC.BlendingFactor1_L0=LTDC_BLENDING_FACTOR1_PAxCA
+LTDC.BlendingFactor2_L0=LTDC_BLENDING_FACTOR2_PAxCA
+LTDC.FBStartAdress_L0=0xC0000000
+LTDC.HBP=1
+LTDC.HFP=1
+LTDC.HSync=1
+LTDC.IPParameters=Layers,WindowX1_L0,WindowY1_L0,PixelFormat_L0,Alpha_L0,BlendingFactor1_L0,BlendingFactor2_L0,FBStartAdress_L0,ImageWidth_L0,ImageHeight_L0,HSync,HBP,ActiveW,HFP,VSync,VBP,VFP
+LTDC.ImageHeight_L0=480
+LTDC.ImageWidth_L0=200
+LTDC.Layers=0
+LTDC.PixelFormat_L0=LTDC_PIXEL_FORMAT_RGB565
+LTDC.VBP=1
+LTDC.VFP=1
+LTDC.VSync=1
+LTDC.WindowX1_L0=200
+LTDC.WindowY1_L0=480
+Mcu.CPN=STM32F469NIH6
+Mcu.Family=STM32F4
+Mcu.IP0=CRC
+Mcu.IP1=DMA2D
+Mcu.IP10=QUADSPI
+Mcu.IP11=RCC
+Mcu.IP12=SAI1
+Mcu.IP13=SDIO
+Mcu.IP14=SYS
+Mcu.IP15=TIM1
+Mcu.IP16=USART3
+Mcu.IP17=USART6
+Mcu.IP18=USB_HOST
+Mcu.IP19=USB_OTG_FS
+Mcu.IP2=DSIHOST
+Mcu.IP3=FATFS
+Mcu.IP4=FMC
+Mcu.IP5=FREERTOS
+Mcu.IP6=I2C1
+Mcu.IP7=I2C2
+Mcu.IP8=LTDC
+Mcu.IP9=NVIC
+Mcu.IPNb=20
+Mcu.Name=STM32F469NIHx
+Mcu.Package=TFBGA216
+Mcu.Pin0=PE4
+Mcu.Pin1=PE3
+Mcu.Pin10=PA13
+Mcu.Pin100=PE11
+Mcu.Pin101=PE14
+Mcu.Pin102=PB10
+Mcu.Pin103=PH8
+Mcu.Pin104=PH10
+Mcu.Pin105=PA3
+Mcu.Pin106=PB0
+Mcu.Pin107=PE7
+Mcu.Pin108=PE10
+Mcu.Pin109=PE12
+Mcu.Pin11=PE5
+Mcu.Pin110=PE15
+Mcu.Pin111=PE13
+Mcu.Pin112=PB11
+Mcu.Pin113=VP_CRC_VS_CRC
+Mcu.Pin114=VP_DMA2D_VS_DMA2D
+Mcu.Pin115=VP_FATFS_VS_SDIO
+Mcu.Pin116=VP_FREERTOS_VS_CMSIS_V2
+Mcu.Pin117=VP_LTDC_DSIMode
+Mcu.Pin118=VP_SYS_VS_tim6
+Mcu.Pin119=VP_TIM1_VS_ClockSourceINT
+Mcu.Pin12=PB9
+Mcu.Pin120=VP_USB_HOST_VS_USB_HOST_CDC_FS
+Mcu.Pin13=PB7
+Mcu.Pin14=PB6
+Mcu.Pin15=PG15
+Mcu.Pin16=PD6
+Mcu.Pin17=PD0
+Mcu.Pin18=PC11
+Mcu.Pin19=PC10
+Mcu.Pin2=PE2
+Mcu.Pin20=PA12
+Mcu.Pin21=PI4
+Mcu.Pin22=PD5
+Mcu.Pin23=PD1
+Mcu.Pin24=PI3
+Mcu.Pin25=PI2
+Mcu.Pin26=PA11
+Mcu.Pin27=PF0
+Mcu.Pin28=PI5
+Mcu.Pin29=PI7
+Mcu.Pin3=PG14
+Mcu.Pin30=PI10
+Mcu.Pin31=PI6
+Mcu.Pin32=PK3
+Mcu.Pin33=PG9
+Mcu.Pin34=PD4
+Mcu.Pin35=PD2
+Mcu.Pin36=PH15
+Mcu.Pin37=PI1
+Mcu.Pin38=PA10
+Mcu.Pin39=PC14/OSC32_IN
+Mcu.Pin4=PE1
+Mcu.Pin40=PF1
+Mcu.Pin41=PI9
+Mcu.Pin42=PH13
+Mcu.Pin43=PH14
+Mcu.Pin44=PI0
+Mcu.Pin45=PA9
+Mcu.Pin46=PC15/OSC32_OUT
+Mcu.Pin47=DSIHOST_D1P
+Mcu.Pin48=DSIHOST_D1N
+Mcu.Pin49=PC9
+Mcu.Pin5=PE0
+Mcu.Pin50=PH0/OSC_IN
+Mcu.Pin51=PF2
+Mcu.Pin52=PC8
+Mcu.Pin53=PH1/OSC_OUT
+Mcu.Pin54=PF3
+Mcu.Pin55=PH4
+Mcu.Pin56=DSIHOST_CKP
+Mcu.Pin57=DSIHOST_CKN
+Mcu.Pin58=PG8
+Mcu.Pin59=PF4
+Mcu.Pin6=PB8
+Mcu.Pin60=PH5
+Mcu.Pin61=PH3
+Mcu.Pin62=DSIHOST_D0P
+Mcu.Pin63=DSIHOST_D0N
+Mcu.Pin64=PG7
+Mcu.Pin65=PG6
+Mcu.Pin66=PF7
+Mcu.Pin67=PF6
+Mcu.Pin68=PF5
+Mcu.Pin69=PH2
+Mcu.Pin7=PB3
+Mcu.Pin70=PD15
+Mcu.Pin71=PD10
+Mcu.Pin72=PF10
+Mcu.Pin73=PF9
+Mcu.Pin74=PF8
+Mcu.Pin75=PD14
+Mcu.Pin76=PD9
+Mcu.Pin77=PD8
+Mcu.Pin78=PC0
+Mcu.Pin79=PB2/BOOT1
+Mcu.Pin8=PC12
+Mcu.Pin80=PF12
+Mcu.Pin81=PG1
+Mcu.Pin82=PF15
+Mcu.Pin83=PD13
+Mcu.Pin84=PG2
+Mcu.Pin85=PJ5
+Mcu.Pin86=PH12
+Mcu.Pin87=PA0/WKUP
+Mcu.Pin88=PF13
+Mcu.Pin89=PG0
+Mcu.Pin9=PA14
+Mcu.Pin90=PE8
+Mcu.Pin91=PG5
+Mcu.Pin92=PG4
+Mcu.Pin93=PH7
+Mcu.Pin94=PH9
+Mcu.Pin95=PH11
+Mcu.Pin96=PF14
+Mcu.Pin97=PJ2
+Mcu.Pin98=PF11
+Mcu.Pin99=PE9
+Mcu.PinsNb=121
+Mcu.ThirdPartyNb=0
+Mcu.UserConstants=
+Mcu.UserName=STM32F469NIHx
+MxCube.Version=6.6.0
+MxDb.Version=DB.6.0.60
+NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
+NVIC.DMA2D_IRQn=true\:5\:0\:false\:false\:true\:true\:true\:true
+NVIC.DSI_IRQn=true\:5\:0\:false\:false\:true\:true\:true\:true
+NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
+NVIC.ForceEnableDMAVector=true
+NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
+NVIC.LTDC_IRQn=true\:5\:0\:false\:false\:true\:true\:true\:true
+NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
+NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
+NVIC.OTG_FS_IRQn=true\:5\:0\:false\:false\:true\:true\:true\:true
+NVIC.PendSV_IRQn=true\:15\:0\:false\:false\:false\:false\:false\:false
+NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4
+NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:false\:false\:false\:false
+NVIC.SysTick_IRQn=true\:15\:0\:false\:false\:false\:true\:false\:false
+NVIC.TIM6_DAC_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:true
+NVIC.TimeBase=TIM6_DAC_IRQn
+NVIC.TimeBaseIP=TIM6
+NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
+PA0/WKUP.GPIOParameters=GPIO_Label
+PA0/WKUP.GPIO_Label=WAKEUP [B2]
+PA0/WKUP.Locked=true
+PA0/WKUP.Mode=SYS_WakeUp0
+PA0/WKUP.Signal=SYS_WKUP
+PA10.GPIOParameters=GPIO_Speed,GPIO_PuPd,GPIO_Label,GPIO_Mode
+PA10.GPIO_Label=USB_FS1_ID
+PA10.GPIO_Mode=GPIO_MODE_AF_PP
+PA10.GPIO_PuPd=GPIO_NOPULL
+PA10.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH
+PA10.Locked=true
+PA10.Signal=USB_OTG_FS_ID
+PA11.GPIOParameters=GPIO_Speed,GPIO_PuPd,GPIO_Label,GPIO_Mode
+PA11.GPIO_Label=USB_FS1_N
+PA11.GPIO_Mode=GPIO_MODE_AF_PP
+PA11.GPIO_PuPd=GPIO_NOPULL
+PA11.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH
+PA11.Locked=true
+PA11.Mode=Host_Only
+PA11.Signal=USB_OTG_FS_DM
+PA12.GPIOParameters=GPIO_Speed,GPIO_PuPd,GPIO_Label,GPIO_Mode
+PA12.GPIO_Label=USB_FS1_P
+PA12.GPIO_Mode=GPIO_MODE_AF_PP
+PA12.GPIO_PuPd=GPIO_NOPULL
+PA12.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH
+PA12.Locked=true
+PA12.Mode=Host_Only
+PA12.Signal=USB_OTG_FS_DP
+PA13.GPIOParameters=GPIO_Label
+PA13.GPIO_Label=SWDIO
+PA13.Locked=true
+PA13.Mode=Serial_Wire
+PA13.Signal=SYS_JTMS-SWDIO
+PA14.GPIOParameters=GPIO_Label
+PA14.GPIO_Label=SWCLK
+PA14.Locked=true
+PA14.Mode=Serial_Wire
+PA14.Signal=SYS_JTCK-SWCLK
+PA3.GPIOParameters=GPIO_Speed,GPIO_PuPd,GPIO_Label,GPIO_ModeDefaultOutputPP
+PA3.GPIO_Label=LCD_BL_CTRL [STLD40DPUR_EN]
+PA3.GPIO_ModeDefaultOutputPP=GPIO_MODE_OUTPUT_PP
+PA3.GPIO_PuPd=GPIO_NOPULL
+PA3.GPIO_Speed=GPIO_SPEED_FREQ_LOW
+PA3.Locked=true
+PA3.Signal=GPIO_Output
+PA9.GPIOParameters=GPIO_Speed,GPIO_PuPd,GPIO_Label,GPIO_Mode
+PA9.GPIO_Label=VBUS_FS1
+PA9.GPIO_Mode=GPIO_MODE_AF_PP
+PA9.GPIO_PuPd=GPIO_NOPULL
+PA9.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH
+PA9.Locked=true
+PA9.Mode=Activate_VBUS
+PA9.Signal=USB_OTG_FS_VBUS
+PB0.GPIOParameters=GPIO_Speed,GPIO_PuPd,GPIO_Label,GPIO_ModeDefaultOutputPP
+PB0.GPIO_Label=EXT_RESET
+PB0.GPIO_ModeDefaultOutputPP=GPIO_MODE_OUTPUT_PP
+PB0.GPIO_PuPd=GPIO_NOPULL
+PB0.GPIO_Speed=GPIO_SPEED_FREQ_LOW
+PB0.Locked=true
+PB0.Signal=GPIO_Output
+PB10.GPIOParameters=GPIO_Speed,GPIO_PuPd,GPIO_Label,GPIO_Mode
+PB10.GPIO_Label=STLK_RX [STLINK V2-1_U2_RX]
+PB10.GPIO_Mode=GPIO_MODE_AF_PP
+PB10.GPIO_PuPd=GPIO_PULLUP
+PB10.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH
+PB10.Locked=true
+PB10.Mode=Asynchronous
+PB10.Signal=USART3_TX
+PB11.GPIOParameters=GPIO_Speed,GPIO_PuPd,GPIO_Label,GPIO_Mode
+PB11.GPIO_Label=STLK_TX [STLINK V2-1_U2_TX]
+PB11.GPIO_Mode=GPIO_MODE_AF_PP
+PB11.GPIO_PuPd=GPIO_PULLUP
+PB11.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH
+PB11.Locked=true
+PB11.Mode=Asynchronous
+PB11.Signal=USART3_RX
+PB2/BOOT1.GPIOParameters=GPIO_Speed,GPIO_PuPd,GPIO_Label,GPIO_ModeDefaultOutputPP
+PB2/BOOT1.GPIO_Label=OTG_FS1_PowerSwitchOn [STMPS2151STR_En]
+PB2/BOOT1.GPIO_ModeDefaultOutputPP=GPIO_MODE_OUTPUT_PP
+PB2/BOOT1.GPIO_PuPd=GPIO_NOPULL
+PB2/BOOT1.GPIO_Speed=GPIO_SPEED_FREQ_LOW
+PB2/BOOT1.Locked=true
+PB2/BOOT1.Signal=GPIO_Output
+PB3.GPIOParameters=GPIO_Speed,GPIO_PuPd,GPIO_Label,GPIO_Mode
+PB3.GPIO_Label=I2S3_CK
+PB3.GPIO_Mode=GPIO_MODE_AF_PP
+PB3.GPIO_PuPd=GPIO_NOPULL
+PB3.GPIO_Speed=GPIO_SPEED_FREQ_LOW
+PB3.Locked=true
+PB3.Signal=I2S3_CK
+PB6.GPIOParameters=GPIO_Speed,GPIO_PuPd,GPIO_Label,GPIO_Mode
+PB6.GPIO_Label=QSPI_BK1_NCS [N25Q128A13EF840F_S]
+PB6.GPIO_Mode=GPIO_MODE_AF_PP
+PB6.GPIO_PuPd=GPIO_NOPULL
+PB6.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH
+PB6.Locked=true
+PB6.Mode=Single Bank 1
+PB6.Signal=QUADSPI_BK1_NCS
+PB7.GPIOParameters=GPIO_PuPd,GPIO_Label,GPIO_ModeDefaultEXTI
+PB7.GPIO_Label=OTG_FS1_OverCurrent [STMPS2151STR_FAULT]
+PB7.GPIO_ModeDefaultEXTI=GPIO_MODE_IT_RISING
+PB7.GPIO_PuPd=GPIO_NOPULL
+PB7.Locked=true
+PB7.Signal=GPXTI7
+PB8.GPIOParameters=GPIO_Speed,GPIO_Label,GPIO_Pu,GPIO_Mode
+PB8.GPIO_Label=I2C1_SCL
+PB8.GPIO_Mode=GPIO_MODE_AF_OD
+PB8.GPIO_Pu=GPIO_PULLUP
+PB8.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH
+PB8.Locked=true
+PB8.Mode=I2C
+PB8.Signal=I2C1_SCL
+PB9.GPIOParameters=GPIO_Speed,GPIO_Label,GPIO_Pu,GPIO_Mode
+PB9.GPIO_Label=I2C1_SDA
+PB9.GPIO_Mode=GPIO_MODE_AF_OD
+PB9.GPIO_Pu=GPIO_PULLUP
+PB9.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH
+PB9.Locked=true
+PB9.Mode=I2C
+PB9.Signal=I2C1_SDA
+PC0.GPIOParameters=GPIO_PuPd,GPIO_Speed_High_Default,GPIO_Label,GPIO_Mode
+PC0.GPIO_Label=SDNWE [MT48LC4M32B2B5-6A_WE]
+PC0.GPIO_Mode=GPIO_MODE_AF_PP
+PC0.GPIO_PuPd=GPIO_NOPULL
+PC0.GPIO_Speed_High_Default=GPIO_SPEED_FREQ_VERY_HIGH
+PC0.Locked=true
+PC0.Signal=FMC_SDNWE
+PC10.GPIOParameters=GPIO_PuPd,GPIO_Speed_High_Default,GPIO_Label,GPIO_Mode
+PC10.GPIO_Label=uSD_D2
+PC10.GPIO_Mode=GPIO_MODE_AF_PP
+PC10.GPIO_PuPd=GPIO_NOPULL
+PC10.GPIO_Speed_High_Default=GPIO_SPEED_FREQ_VERY_HIGH
+PC10.Locked=true
+PC10.Mode=SD_4_bits_Wide_bus
+PC10.Signal=SDIO_D2
+PC11.GPIOParameters=GPIO_PuPd,GPIO_Speed_High_Default,GPIO_Label,GPIO_Mode
+PC11.GPIO_Label=uSD_D3
+PC11.GPIO_Mode=GPIO_MODE_AF_PP
+PC11.GPIO_PuPd=GPIO_NOPULL
+PC11.GPIO_Speed_High_Default=GPIO_SPEED_FREQ_VERY_HIGH
+PC11.Locked=true
+PC11.Mode=SD_4_bits_Wide_bus
+PC11.Signal=SDIO_D3
+PC12.GPIOParameters=GPIO_PuPd,GPIO_Speed_High_Default,GPIO_Label,GPIO_Mode
+PC12.GPIO_Label=uSD_CLK
+PC12.GPIO_Mode=GPIO_MODE_AF_PP
+PC12.GPIO_PuPd=GPIO_NOPULL
+PC12.GPIO_Speed_High_Default=GPIO_SPEED_FREQ_VERY_HIGH
+PC12.Locked=true
+PC12.Mode=SD_4_bits_Wide_bus
+PC12.Signal=SDIO_CK
+PC14/OSC32_IN.Locked=true
+PC14/OSC32_IN.Mode=LSE-External-Oscillator
+PC14/OSC32_IN.Signal=RCC_OSC32_IN
+PC15/OSC32_OUT.Locked=true
+PC15/OSC32_OUT.Mode=LSE-External-Oscillator
+PC15/OSC32_OUT.Signal=RCC_OSC32_OUT
+PC8.GPIOParameters=GPIO_PuPd,GPIO_Speed_High_Default,GPIO_Label,GPIO_Mode
+PC8.GPIO_Label=uSD_D0
+PC8.GPIO_Mode=GPIO_MODE_AF_PP
+PC8.GPIO_PuPd=GPIO_NOPULL
+PC8.GPIO_Speed_High_Default=GPIO_SPEED_FREQ_VERY_HIGH
+PC8.Locked=true
+PC8.Mode=SD_4_bits_Wide_bus
+PC8.Signal=SDIO_D0
+PC9.GPIOParameters=GPIO_PuPd,GPIO_Speed_High_Default,GPIO_Label,GPIO_Mode
+PC9.GPIO_Label=uSD_D1
+PC9.GPIO_Mode=GPIO_MODE_AF_PP
+PC9.GPIO_PuPd=GPIO_NOPULL
+PC9.GPIO_Speed_High_Default=GPIO_SPEED_FREQ_VERY_HIGH
+PC9.Locked=true
+PC9.Mode=SD_4_bits_Wide_bus
+PC9.Signal=SDIO_D1
+PD0.GPIOParameters=GPIO_PuPd,GPIO_Speed_High_Default,GPIO_Label,GPIO_Mode
+PD0.GPIO_Label=D2
+PD0.GPIO_Mode=GPIO_MODE_AF_PP
+PD0.GPIO_PuPd=GPIO_NOPULL
+PD0.GPIO_Speed_High_Default=GPIO_SPEED_FREQ_VERY_HIGH
+PD0.Locked=true
+PD0.Signal=FMC_D2_DA2
+PD1.GPIOParameters=GPIO_PuPd,GPIO_Speed_High_Default,GPIO_Label,GPIO_Mode
+PD1.GPIO_Label=D3
+PD1.GPIO_Mode=GPIO_MODE_AF_PP
+PD1.GPIO_PuPd=GPIO_NOPULL
+PD1.GPIO_Speed_High_Default=GPIO_SPEED_FREQ_VERY_HIGH
+PD1.Locked=true
+PD1.Signal=FMC_D3_DA3
+PD10.GPIOParameters=GPIO_PuPd,GPIO_Speed_High_Default,GPIO_Label,GPIO_Mode
+PD10.GPIO_Label=D15
+PD10.GPIO_Mode=GPIO_MODE_AF_PP
+PD10.GPIO_PuPd=GPIO_NOPULL
+PD10.GPIO_Speed_High_Default=GPIO_SPEED_FREQ_VERY_HIGH
+PD10.Locked=true
+PD10.Signal=FMC_D15_DA15
+PD13.GPIOParameters=GPIO_ModeDefaultPP,GPIO_Speed,GPIO_PuPd,GPIO_Label
+PD13.GPIO_Label=MIC_CK [MP34DT01TR_CLK]
+PD13.GPIO_ModeDefaultPP=GPIO_MODE_AF_PP
+PD13.GPIO_PuPd=GPIO_NOPULL
+PD13.GPIO_Speed=GPIO_SPEED_FREQ_LOW
+PD13.Locked=true
+PD13.Signal=S_TIM4_CH2
+PD14.GPIOParameters=GPIO_PuPd,GPIO_Speed_High_Default,GPIO_Label,GPIO_Mode
+PD14.GPIO_Label=D0
+PD14.GPIO_Mode=GPIO_MODE_AF_PP
+PD14.GPIO_PuPd=GPIO_NOPULL
+PD14.GPIO_Speed_High_Default=GPIO_SPEED_FREQ_VERY_HIGH
+PD14.Locked=true
+PD14.Signal=FMC_D0_DA0
+PD15.GPIOParameters=GPIO_PuPd,GPIO_Speed_High_Default,GPIO_Label,GPIO_Mode
+PD15.GPIO_Label=D1
+PD15.GPIO_Mode=GPIO_MODE_AF_PP
+PD15.GPIO_PuPd=GPIO_NOPULL
+PD15.GPIO_Speed_High_Default=GPIO_SPEED_FREQ_VERY_HIGH
+PD15.Locked=true
+PD15.Signal=FMC_D1_DA1
+PD2.GPIOParameters=GPIO_PuPd,GPIO_Speed_High_Default,GPIO_Label,GPIO_Mode
+PD2.GPIO_Label=uSD_CMD
+PD2.GPIO_Mode=GPIO_MODE_AF_PP
+PD2.GPIO_PuPd=GPIO_NOPULL
+PD2.GPIO_Speed_High_Default=GPIO_SPEED_FREQ_VERY_HIGH
+PD2.Locked=true
+PD2.Mode=SD_4_bits_Wide_bus
+PD2.Signal=SDIO_CMD
+PD4.GPIOParameters=GPIO_Speed,GPIO_PuPd,GPIO_Label,GPIO_ModeDefaultOutputPP
+PD4.GPIO_Label=LED2 [Orange]
+PD4.GPIO_ModeDefaultOutputPP=GPIO_MODE_OUTPUT_OD
+PD4.GPIO_PuPd=GPIO_NOPULL
+PD4.GPIO_Speed=GPIO_SPEED_FREQ_LOW
+PD4.Locked=true
+PD4.Signal=GPIO_Output
+PD5.GPIOParameters=GPIO_Speed,GPIO_PuPd,GPIO_Label,GPIO_ModeDefaultOutputPP
+PD5.GPIO_Label=LED3 [Red]
+PD5.GPIO_ModeDefaultOutputPP=GPIO_MODE_OUTPUT_OD
+PD5.GPIO_PuPd=GPIO_NOPULL
+PD5.GPIO_Speed=GPIO_SPEED_FREQ_LOW
+PD5.Locked=true
+PD5.Signal=GPIO_Output
+PD6.GPIOParameters=GPIO_Speed,GPIO_PuPd,GPIO_Label,GPIO_Mode
+PD6.GPIO_Label=MIC_DATA [MP34DT01TR_DOUT]
+PD6.GPIO_Mode=GPIO_MODE_AF_PP
+PD6.GPIO_PuPd=GPIO_NOPULL
+PD6.GPIO_Speed=GPIO_SPEED_FREQ_LOW
+PD6.Locked=true
+PD6.Mode=SAI_A_MasterWithClock
+PD6.Signal=SAI1_SD_A
+PD8.GPIOParameters=GPIO_PuPd,GPIO_Speed_High_Default,GPIO_Label,GPIO_Mode
+PD8.GPIO_Label=D13
+PD8.GPIO_Mode=GPIO_MODE_AF_PP
+PD8.GPIO_PuPd=GPIO_NOPULL
+PD8.GPIO_Speed_High_Default=GPIO_SPEED_FREQ_VERY_HIGH
+PD8.Locked=true
+PD8.Signal=FMC_D13_DA13
+PD9.GPIOParameters=GPIO_PuPd,GPIO_Speed_High_Default,GPIO_Label,GPIO_Mode
+PD9.GPIO_Label=D14
+PD9.GPIO_Mode=GPIO_MODE_AF_PP
+PD9.GPIO_PuPd=GPIO_NOPULL
+PD9.GPIO_Speed_High_Default=GPIO_SPEED_FREQ_VERY_HIGH
+PD9.Locked=true
+PD9.Signal=FMC_D14_DA14
+PE0.GPIOParameters=GPIO_PuPd,GPIO_Speed_High_Default,GPIO_Label,GPIO_Mode
+PE0.GPIO_Label=FMC_NBL0 [ MT48LC4M32B2B5-6A_DQM0]
+PE0.GPIO_Mode=GPIO_MODE_AF_PP
+PE0.GPIO_PuPd=GPIO_NOPULL
+PE0.GPIO_Speed_High_Default=GPIO_SPEED_FREQ_VERY_HIGH
+PE0.Locked=true
+PE0.Signal=FMC_NBL0
+PE1.GPIOParameters=GPIO_PuPd,GPIO_Speed_High_Default,GPIO_Label,GPIO_Mode
+PE1.GPIO_Label=FMC_NBL1 [ MT48LC4M32B2B5-6A_DQM1]
+PE1.GPIO_Mode=GPIO_MODE_AF_PP
+PE1.GPIO_PuPd=GPIO_NOPULL
+PE1.GPIO_Speed_High_Default=GPIO_SPEED_FREQ_VERY_HIGH
+PE1.Locked=true
+PE1.Signal=FMC_NBL1
+PE10.GPIOParameters=GPIO_PuPd,GPIO_Speed_High_Default,GPIO_Label,GPIO_Mode
+PE10.GPIO_Label=D7
+PE10.GPIO_Mode=GPIO_MODE_AF_PP
+PE10.GPIO_PuPd=GPIO_NOPULL
+PE10.GPIO_Speed_High_Default=GPIO_SPEED_FREQ_VERY_HIGH
+PE10.Locked=true
+PE10.Signal=FMC_D7_DA7
+PE11.GPIOParameters=GPIO_PuPd,GPIO_Speed_High_Default,GPIO_Label,GPIO_Mode
+PE11.GPIO_Label=D8
+PE11.GPIO_Mode=GPIO_MODE_AF_PP
+PE11.GPIO_PuPd=GPIO_NOPULL
+PE11.GPIO_Speed_High_Default=GPIO_SPEED_FREQ_VERY_HIGH
+PE11.Locked=true
+PE11.Signal=FMC_D8_DA8
+PE12.GPIOParameters=GPIO_PuPd,GPIO_Speed_High_Default,GPIO_Label,GPIO_Mode
+PE12.GPIO_Label=D9
+PE12.GPIO_Mode=GPIO_MODE_AF_PP
+PE12.GPIO_PuPd=GPIO_NOPULL
+PE12.GPIO_Speed_High_Default=GPIO_SPEED_FREQ_VERY_HIGH
+PE12.Locked=true
+PE12.Signal=FMC_D9_DA9
+PE13.GPIOParameters=GPIO_PuPd,GPIO_Speed_High_Default,GPIO_Label,GPIO_Mode
+PE13.GPIO_Label=D10
+PE13.GPIO_Mode=GPIO_MODE_AF_PP
+PE13.GPIO_PuPd=GPIO_NOPULL
+PE13.GPIO_Speed_High_Default=GPIO_SPEED_FREQ_VERY_HIGH
+PE13.Locked=true
+PE13.Signal=FMC_D10_DA10
+PE14.GPIOParameters=GPIO_PuPd,GPIO_Speed_High_Default,GPIO_Label,GPIO_Mode
+PE14.GPIO_Label=D11
+PE14.GPIO_Mode=GPIO_MODE_AF_PP
+PE14.GPIO_PuPd=GPIO_NOPULL
+PE14.GPIO_Speed_High_Default=GPIO_SPEED_FREQ_VERY_HIGH
+PE14.Locked=true
+PE14.Signal=FMC_D11_DA11
+PE15.GPIOParameters=GPIO_PuPd,GPIO_Speed_High_Default,GPIO_Label,GPIO_Mode
+PE15.GPIO_Label=D12
+PE15.GPIO_Mode=GPIO_MODE_AF_PP
+PE15.GPIO_PuPd=GPIO_NOPULL
+PE15.GPIO_Speed_High_Default=GPIO_SPEED_FREQ_VERY_HIGH
+PE15.Locked=true
+PE15.Signal=FMC_D12_DA12
+PE2.GPIOParameters=GPIO_Speed,GPIO_PuPd,GPIO_Label,GPIO_ModeDefaultOutputPP
+PE2.GPIO_Label=AUDIO_RST [CS43L22_RESET]
+PE2.GPIO_ModeDefaultOutputPP=GPIO_MODE_OUTPUT_PP
+PE2.GPIO_PuPd=GPIO_NOPULL
+PE2.GPIO_Speed=GPIO_SPEED_FREQ_LOW
+PE2.Locked=true
+PE2.Signal=GPIO_Output
+PE3.GPIOParameters=GPIO_Speed,GPIO_PuPd,GPIO_Label,GPIO_ModeDefaultOutputPP
+PE3.GPIO_Label=SPKR/HP [CS43L22_SPKR/HP]
+PE3.GPIO_ModeDefaultOutputPP=GPIO_MODE_OUTPUT_PP
+PE3.GPIO_PuPd=GPIO_NOPULL
+PE3.GPIO_Speed=GPIO_SPEED_FREQ_LOW
+PE3.Locked=true
+PE3.Signal=GPIO_Output
+PE4.GPIOParameters=GPIO_Speed,GPIO_PuPd,GPIO_Label,GPIO_Mode
+PE4.GPIO_Label=SAI1_FSA [CS43L22_LRCK]
+PE4.GPIO_Mode=GPIO_MODE_AF_PP
+PE4.GPIO_PuPd=GPIO_NOPULL
+PE4.GPIO_Speed=GPIO_SPEED_FREQ_LOW
+PE4.Locked=true
+PE4.Mode=SAI_A_MasterWithClock
+PE4.Signal=SAI1_FS_A
+PE5.GPIOParameters=GPIO_Speed,GPIO_PuPd,GPIO_Label,GPIO_Mode
+PE5.GPIO_Label=SAI1_SCKA [CS43L22_CLK]
+PE5.GPIO_Mode=GPIO_MODE_AF_PP
+PE5.GPIO_PuPd=GPIO_NOPULL
+PE5.GPIO_Speed=GPIO_SPEED_FREQ_LOW
+PE5.Locked=true
+PE5.Mode=SAI_A_MasterWithClock
+PE5.Signal=SAI1_SCK_A
+PE7.GPIOParameters=GPIO_PuPd,GPIO_Speed_High_Default,GPIO_Label,GPIO_Mode
+PE7.GPIO_Label=D4
+PE7.GPIO_Mode=GPIO_MODE_AF_PP
+PE7.GPIO_PuPd=GPIO_NOPULL
+PE7.GPIO_Speed_High_Default=GPIO_SPEED_FREQ_VERY_HIGH
+PE7.Locked=true
+PE7.Signal=FMC_D4_DA4
+PE8.GPIOParameters=GPIO_PuPd,GPIO_Speed_High_Default,GPIO_Label,GPIO_Mode
+PE8.GPIO_Label=D5
+PE8.GPIO_Mode=GPIO_MODE_AF_PP
+PE8.GPIO_PuPd=GPIO_NOPULL
+PE8.GPIO_Speed_High_Default=GPIO_SPEED_FREQ_VERY_HIGH
+PE8.Locked=true
+PE8.Signal=FMC_D5_DA5
+PE9.GPIOParameters=GPIO_PuPd,GPIO_Speed_High_Default,GPIO_Label,GPIO_Mode
+PE9.GPIO_Label=D6
+PE9.GPIO_Mode=GPIO_MODE_AF_PP
+PE9.GPIO_PuPd=GPIO_NOPULL
+PE9.GPIO_Speed_High_Default=GPIO_SPEED_FREQ_VERY_HIGH
+PE9.Locked=true
+PE9.Signal=FMC_D6_DA6
+PF0.GPIOParameters=GPIO_PuPd,GPIO_Speed_High_Default,GPIO_Label,GPIO_Mode
+PF0.GPIO_Label=A0
+PF0.GPIO_Mode=GPIO_MODE_AF_PP
+PF0.GPIO_PuPd=GPIO_NOPULL
+PF0.GPIO_Speed_High_Default=GPIO_SPEED_FREQ_VERY_HIGH
+PF0.Locked=true
+PF0.Signal=FMC_A0
+PF1.GPIOParameters=GPIO_PuPd,GPIO_Speed_High_Default,GPIO_Label,GPIO_Mode
+PF1.GPIO_Label=A1
+PF1.GPIO_Mode=GPIO_MODE_AF_PP
+PF1.GPIO_PuPd=GPIO_NOPULL
+PF1.GPIO_Speed_High_Default=GPIO_SPEED_FREQ_VERY_HIGH
+PF1.Locked=true
+PF1.Signal=FMC_A1
+PF10.GPIOParameters=GPIO_Speed,GPIO_PuPd,GPIO_Label,GPIO_Mode
+PF10.GPIO_Label=QSPI_CLK [N25Q128A13EF840F_C]
+PF10.GPIO_Mode=GPIO_MODE_AF_PP
+PF10.GPIO_PuPd=GPIO_NOPULL
+PF10.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH
+PF10.Locked=true
+PF10.Mode=Single Bank 1
+PF10.Signal=QUADSPI_CLK
+PF11.GPIOParameters=GPIO_PuPd,GPIO_Speed_High_Default,GPIO_Label,GPIO_Mode
+PF11.GPIO_Label=SDNMT48LC4M32B2B5-6A_RAS]RAS [
+PF11.GPIO_Mode=GPIO_MODE_AF_PP
+PF11.GPIO_PuPd=GPIO_NOPULL
+PF11.GPIO_Speed_High_Default=GPIO_SPEED_FREQ_VERY_HIGH
+PF11.Locked=true
+PF11.Signal=FMC_SDNRAS
+PF12.GPIOParameters=GPIO_PuPd,GPIO_Speed_High_Default,GPIO_Label,GPIO_Mode
+PF12.GPIO_Label=A6
+PF12.GPIO_Mode=GPIO_MODE_AF_PP
+PF12.GPIO_PuPd=GPIO_NOPULL
+PF12.GPIO_Speed_High_Default=GPIO_SPEED_FREQ_VERY_HIGH
+PF12.Locked=true
+PF12.Signal=FMC_A6
+PF13.GPIOParameters=GPIO_PuPd,GPIO_Speed_High_Default,GPIO_Label,GPIO_Mode
+PF13.GPIO_Label=A7
+PF13.GPIO_Mode=GPIO_MODE_AF_PP
+PF13.GPIO_PuPd=GPIO_NOPULL
+PF13.GPIO_Speed_High_Default=GPIO_SPEED_FREQ_VERY_HIGH
+PF13.Locked=true
+PF13.Signal=FMC_A7
+PF14.GPIOParameters=GPIO_PuPd,GPIO_Speed_High_Default,GPIO_Label,GPIO_Mode
+PF14.GPIO_Label=A8
+PF14.GPIO_Mode=GPIO_MODE_AF_PP
+PF14.GPIO_PuPd=GPIO_NOPULL
+PF14.GPIO_Speed_High_Default=GPIO_SPEED_FREQ_VERY_HIGH
+PF14.Locked=true
+PF14.Signal=FMC_A8
+PF15.GPIOParameters=GPIO_PuPd,GPIO_Speed_High_Default,GPIO_Label,GPIO_Mode
+PF15.GPIO_Label=A9
+PF15.GPIO_Mode=GPIO_MODE_AF_PP
+PF15.GPIO_PuPd=GPIO_NOPULL
+PF15.GPIO_Speed_High_Default=GPIO_SPEED_FREQ_VERY_HIGH
+PF15.Locked=true
+PF15.Signal=FMC_A9
+PF2.GPIOParameters=GPIO_PuPd,GPIO_Speed_High_Default,GPIO_Label,GPIO_Mode
+PF2.GPIO_Label=A2
+PF2.GPIO_Mode=GPIO_MODE_AF_PP
+PF2.GPIO_PuPd=GPIO_NOPULL
+PF2.GPIO_Speed_High_Default=GPIO_SPEED_FREQ_VERY_HIGH
+PF2.Locked=true
+PF2.Signal=FMC_A2
+PF3.GPIOParameters=GPIO_PuPd,GPIO_Speed_High_Default,GPIO_Label,GPIO_Mode
+PF3.GPIO_Label=A3
+PF3.GPIO_Mode=GPIO_MODE_AF_PP
+PF3.GPIO_PuPd=GPIO_NOPULL
+PF3.GPIO_Speed_High_Default=GPIO_SPEED_FREQ_VERY_HIGH
+PF3.Locked=true
+PF3.Signal=FMC_A3
+PF4.GPIOParameters=GPIO_PuPd,GPIO_Speed_High_Default,GPIO_Label,GPIO_Mode
+PF4.GPIO_Label=A4
+PF4.GPIO_Mode=GPIO_MODE_AF_PP
+PF4.GPIO_PuPd=GPIO_NOPULL
+PF4.GPIO_Speed_High_Default=GPIO_SPEED_FREQ_VERY_HIGH
+PF4.Locked=true
+PF4.Signal=FMC_A4
+PF5.GPIOParameters=GPIO_PuPd,GPIO_Speed_High_Default,GPIO_Label,GPIO_Mode
+PF5.GPIO_Label=A5
+PF5.GPIO_Mode=GPIO_MODE_AF_PP
+PF5.GPIO_PuPd=GPIO_NOPULL
+PF5.GPIO_Speed_High_Default=GPIO_SPEED_FREQ_VERY_HIGH
+PF5.Locked=true
+PF5.Signal=FMC_A5
+PF6.GPIOParameters=GPIO_Speed,GPIO_PuPd,GPIO_Label,GPIO_Mode
+PF6.GPIO_Label=QSPI_BK1_IO3 [N25Q128A13EF840F_DQ3]
+PF6.GPIO_Mode=GPIO_MODE_AF_PP
+PF6.GPIO_PuPd=GPIO_NOPULL
+PF6.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH
+PF6.Locked=true
+PF6.Mode=Single Bank 1
+PF6.Signal=QUADSPI_BK1_IO3
+PF7.GPIOParameters=GPIO_Speed,GPIO_PuPd,GPIO_Label,GPIO_Mode
+PF7.GPIO_Label=QSPI_BK1_IO2 [N25Q128A13EF840F_DQ2]
+PF7.GPIO_Mode=GPIO_MODE_AF_PP
+PF7.GPIO_PuPd=GPIO_NOPULL
+PF7.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH
+PF7.Locked=true
+PF7.Mode=Single Bank 1
+PF7.Signal=QUADSPI_BK1_IO2
+PF8.GPIOParameters=GPIO_Speed,GPIO_PuPd,GPIO_Label,GPIO_Mode
+PF8.GPIO_Label=QSPI_BK1_IO0 [N25Q128A13EF840F_DQ0]
+PF8.GPIO_Mode=GPIO_MODE_AF_PP
+PF8.GPIO_PuPd=GPIO_NOPULL
+PF8.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH
+PF8.Locked=true
+PF8.Mode=Single Bank 1
+PF8.Signal=QUADSPI_BK1_IO0
+PF9.GPIOParameters=GPIO_Speed,GPIO_PuPd,GPIO_Label,GPIO_Mode
+PF9.GPIO_Label=QSPI_BK1_IO1 [N25Q128A13EF840F_DQ1]
+PF9.GPIO_Mode=GPIO_MODE_AF_PP
+PF9.GPIO_PuPd=GPIO_NOPULL
+PF9.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH
+PF9.Locked=true
+PF9.Mode=Single Bank 1
+PF9.Signal=QUADSPI_BK1_IO1
+PG0.GPIOParameters=GPIO_PuPd,GPIO_Speed_High_Default,GPIO_Label,GPIO_Mode
+PG0.GPIO_Label=A10
+PG0.GPIO_Mode=GPIO_MODE_AF_PP
+PG0.GPIO_PuPd=GPIO_NOPULL
+PG0.GPIO_Speed_High_Default=GPIO_SPEED_FREQ_VERY_HIGH
+PG0.Locked=true
+PG0.Signal=FMC_A10
+PG1.GPIOParameters=GPIO_PuPd,GPIO_Speed_High_Default,GPIO_Label,GPIO_Mode
+PG1.GPIO_Label=A11
+PG1.GPIO_Mode=GPIO_MODE_AF_PP
+PG1.GPIO_PuPd=GPIO_NOPULL
+PG1.GPIO_Speed_High_Default=GPIO_SPEED_FREQ_VERY_HIGH
+PG1.Locked=true
+PG1.Signal=FMC_A11
+PG14.GPIOParameters=GPIO_Speed,GPIO_PuPd,GPIO_Label,GPIO_Mode
+PG14.GPIO_Label=ARDUINO USART6_TX
+PG14.GPIO_Mode=GPIO_MODE_AF_PP
+PG14.GPIO_PuPd=GPIO_NOPULL
+PG14.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH
+PG14.Locked=true
+PG14.Mode=Asynchronous
+PG14.Signal=USART6_TX
+PG15.GPIOParameters=GPIO_PuPd,GPIO_Speed_High_Default,GPIO_Label,GPIO_Mode
+PG15.GPIO_Label=SDNCAS [MT48LC4M32B2B5-6A_CAS]
+PG15.GPIO_Mode=GPIO_MODE_AF_PP
+PG15.GPIO_PuPd=GPIO_NOPULL
+PG15.GPIO_Speed_High_Default=GPIO_SPEED_FREQ_VERY_HIGH
+PG15.Locked=true
+PG15.Signal=FMC_SDNCAS
+PG2.GPIOParameters=GPIO_PuPd,GPIO_Label,GPIO_Mode
+PG2.GPIO_Label=uSD_Detect
+PG2.GPIO_Mode=GPIO_MODE_INPUT
+PG2.GPIO_PuPd=GPIO_NOPULL
+PG2.Locked=true
+PG2.Signal=GPIO_Input
+PG4.Locked=true
+PG4.Signal=FMC_A14_BA0
+PG5.Locked=true
+PG5.Signal=FMC_A15_BA1
+PG6.GPIOParameters=GPIO_Speed,GPIO_PuPd,GPIO_Label,GPIO_ModeDefaultOutputPP
+PG6.GPIO_Label=LED1 [Green]
+PG6.GPIO_ModeDefaultOutputPP=GPIO_MODE_OUTPUT_OD
+PG6.GPIO_PuPd=GPIO_NOPULL
+PG6.GPIO_Speed=GPIO_SPEED_FREQ_LOW
+PG6.Locked=true
+PG6.Signal=GPIO_Output
+PG7.GPIOParameters=GPIO_Speed,GPIO_PuPd,GPIO_Label,GPIO_Mode
+PG7.GPIO_Label=SAI1_MCLKA [CS43L22_MCLK]
+PG7.GPIO_Mode=GPIO_MODE_AF_PP
+PG7.GPIO_PuPd=GPIO_NOPULL
+PG7.GPIO_Speed=GPIO_SPEED_FREQ_LOW
+PG7.Locked=true
+PG7.Mode=SAI_A_MasterWithClock
+PG7.Signal=SAI1_MCLK_A
+PG8.GPIOParameters=GPIO_PuPd,GPIO_Speed_High_Default,GPIO_Label,GPIO_Mode
+PG8.GPIO_Label=SDCLK [MT48LC4M32B2B5-6A_CLK]
+PG8.GPIO_Mode=GPIO_MODE_AF_PP
+PG8.GPIO_PuPd=GPIO_NOPULL
+PG8.GPIO_Speed_High_Default=GPIO_SPEED_FREQ_VERY_HIGH
+PG8.Locked=true
+PG8.Signal=FMC_SDCLK
+PG9.GPIOParameters=GPIO_Speed,GPIO_PuPd,GPIO_Label,GPIO_Mode
+PG9.GPIO_Label=USART6_RX
+PG9.GPIO_Mode=GPIO_MODE_AF_PP
+PG9.GPIO_PuPd=GPIO_NOPULL
+PG9.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH
+PG9.Locked=true
+PG9.Mode=Asynchronous
+PG9.Signal=USART6_RX
+PH0/OSC_IN.Locked=true
+PH0/OSC_IN.Mode=HSE-External-Oscillator
+PH0/OSC_IN.Signal=RCC_OSC_IN
+PH1/OSC_OUT.Locked=true
+PH1/OSC_OUT.Mode=HSE-External-Oscillator
+PH1/OSC_OUT.Signal=RCC_OSC_OUT
+PH10.GPIOParameters=GPIO_PuPd,GPIO_Speed_High_Default,GPIO_Label,GPIO_Mode
+PH10.GPIO_Label=D18
+PH10.GPIO_Mode=GPIO_MODE_AF_PP
+PH10.GPIO_PuPd=GPIO_NOPULL
+PH10.GPIO_Speed_High_Default=GPIO_SPEED_FREQ_VERY_HIGH
+PH10.Locked=true
+PH10.Signal=FMC_D18
+PH11.GPIOParameters=GPIO_PuPd,GPIO_Speed_High_Default,GPIO_Label,GPIO_Mode
+PH11.GPIO_Label=D19
+PH11.GPIO_Mode=GPIO_MODE_AF_PP
+PH11.GPIO_PuPd=GPIO_NOPULL
+PH11.GPIO_Speed_High_Default=GPIO_SPEED_FREQ_VERY_HIGH
+PH11.Locked=true
+PH11.Signal=FMC_D19
+PH12.GPIOParameters=GPIO_PuPd,GPIO_Speed_High_Default,GPIO_Label,GPIO_Mode
+PH12.GPIO_Label=D20
+PH12.GPIO_Mode=GPIO_MODE_AF_PP
+PH12.GPIO_PuPd=GPIO_NOPULL
+PH12.GPIO_Speed_High_Default=GPIO_SPEED_FREQ_VERY_HIGH
+PH12.Locked=true
+PH12.Signal=FMC_D20
+PH13.GPIOParameters=GPIO_PuPd,GPIO_Speed_High_Default,GPIO_Label,GPIO_Mode
+PH13.GPIO_Label=D21
+PH13.GPIO_Mode=GPIO_MODE_AF_PP
+PH13.GPIO_PuPd=GPIO_NOPULL
+PH13.GPIO_Speed_High_Default=GPIO_SPEED_FREQ_VERY_HIGH
+PH13.Locked=true
+PH13.Signal=FMC_D21
+PH14.GPIOParameters=GPIO_PuPd,GPIO_Speed_High_Default,GPIO_Label,GPIO_Mode
+PH14.GPIO_Label=D22
+PH14.GPIO_Mode=GPIO_MODE_AF_PP
+PH14.GPIO_PuPd=GPIO_NOPULL
+PH14.GPIO_Speed_High_Default=GPIO_SPEED_FREQ_VERY_HIGH
+PH14.Locked=true
+PH14.Signal=FMC_D22
+PH15.GPIOParameters=GPIO_PuPd,GPIO_Speed_High_Default,GPIO_Label,GPIO_Mode
+PH15.GPIO_Label=D23
+PH15.GPIO_Mode=GPIO_MODE_AF_PP
+PH15.GPIO_PuPd=GPIO_NOPULL
+PH15.GPIO_Speed_High_Default=GPIO_SPEED_FREQ_VERY_HIGH
+PH15.Locked=true
+PH15.Signal=FMC_D23
+PH2.GPIOParameters=GPIO_PuPd,GPIO_Speed_High_Default,GPIO_Label,GPIO_Mode
+PH2.GPIO_Label=SDCKE0 [MT48LC4M32B2B5-6A_CKE]
+PH2.GPIO_Mode=GPIO_MODE_AF_PP
+PH2.GPIO_PuPd=GPIO_NOPULL
+PH2.GPIO_Speed_High_Default=GPIO_SPEED_FREQ_VERY_HIGH
+PH2.Locked=true
+PH2.Mode=SdramChipSelect1_1
+PH2.Signal=FMC_SDCKE0
+PH3.GPIOParameters=GPIO_PuPd,GPIO_Speed_High_Default,GPIO_Label,GPIO_Mode
+PH3.GPIO_Label=SDNE0 [MT48LC4M32B2B5-6A_CS]
+PH3.GPIO_Mode=GPIO_MODE_AF_PP
+PH3.GPIO_PuPd=GPIO_NOPULL
+PH3.GPIO_Speed_High_Default=GPIO_SPEED_FREQ_VERY_HIGH
+PH3.Locked=true
+PH3.Mode=SdramChipSelect1_1
+PH3.Signal=FMC_SDNE0
+PH4.GPIOParameters=GPIO_Speed,GPIO_Label,GPIO_Pu,GPIO_Mode
+PH4.GPIO_Label=I2C2_SCL [CS43L22_SCL]
+PH4.GPIO_Mode=GPIO_MODE_AF_OD
+PH4.GPIO_Pu=GPIO_PULLUP
+PH4.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH
+PH4.Locked=true
+PH4.Mode=I2C
+PH4.Signal=I2C2_SCL
+PH5.GPIOParameters=GPIO_Speed,GPIO_Label,GPIO_Pu,GPIO_Mode
+PH5.GPIO_Label=I2C2_SDA [CS43L22_SDA]
+PH5.GPIO_Mode=GPIO_MODE_AF_OD
+PH5.GPIO_Pu=GPIO_PULLUP
+PH5.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH
+PH5.Locked=true
+PH5.Mode=I2C
+PH5.Signal=I2C2_SDA
+PH7.Locked=true
+PH7.Signal=GPIO_Output
+PH8.GPIOParameters=GPIO_PuPd,GPIO_Speed_High_Default,GPIO_Label,GPIO_Mode
+PH8.GPIO_Label=D16
+PH8.GPIO_Mode=GPIO_MODE_AF_PP
+PH8.GPIO_PuPd=GPIO_NOPULL
+PH8.GPIO_Speed_High_Default=GPIO_SPEED_FREQ_VERY_HIGH
+PH8.Locked=true
+PH8.Signal=FMC_D16
+PH9.GPIOParameters=GPIO_PuPd,GPIO_Speed_High_Default,GPIO_Label,GPIO_Mode
+PH9.GPIO_Label=D17
+PH9.GPIO_Mode=GPIO_MODE_AF_PP
+PH9.GPIO_PuPd=GPIO_NOPULL
+PH9.GPIO_Speed_High_Default=GPIO_SPEED_FREQ_VERY_HIGH
+PH9.Locked=true
+PH9.Signal=FMC_D17
+PI0.GPIOParameters=GPIO_PuPd,GPIO_Speed_High_Default,GPIO_Label,GPIO_Mode
+PI0.GPIO_Label=D24
+PI0.GPIO_Mode=GPIO_MODE_AF_PP
+PI0.GPIO_PuPd=GPIO_NOPULL
+PI0.GPIO_Speed_High_Default=GPIO_SPEED_FREQ_VERY_HIGH
+PI0.Locked=true
+PI0.Signal=FMC_D24
+PI1.GPIOParameters=GPIO_PuPd,GPIO_Speed_High_Default,GPIO_Label,GPIO_Mode
+PI1.GPIO_Label=D25
+PI1.GPIO_Mode=GPIO_MODE_AF_PP
+PI1.GPIO_PuPd=GPIO_NOPULL
+PI1.GPIO_Speed_High_Default=GPIO_SPEED_FREQ_VERY_HIGH
+PI1.Locked=true
+PI1.Signal=FMC_D25
+PI10.GPIOParameters=GPIO_PuPd,GPIO_Speed_High_Default,GPIO_Label,GPIO_Mode
+PI10.GPIO_Label=D31
+PI10.GPIO_Mode=GPIO_MODE_AF_PP
+PI10.GPIO_PuPd=GPIO_NOPULL
+PI10.GPIO_Speed_High_Default=GPIO_SPEED_FREQ_VERY_HIGH
+PI10.Locked=true
+PI10.Signal=FMC_D31
+PI2.GPIOParameters=GPIO_PuPd,GPIO_Speed_High_Default,GPIO_Label,GPIO_Mode
+PI2.GPIO_Label=D26
+PI2.GPIO_Mode=GPIO_MODE_AF_PP
+PI2.GPIO_PuPd=GPIO_NOPULL
+PI2.GPIO_Speed_High_Default=GPIO_SPEED_FREQ_VERY_HIGH
+PI2.Locked=true
+PI2.Signal=FMC_D26
+PI3.GPIOParameters=GPIO_PuPd,GPIO_Speed_High_Default,GPIO_Label,GPIO_Mode
+PI3.GPIO_Label=D27
+PI3.GPIO_Mode=GPIO_MODE_AF_PP
+PI3.GPIO_PuPd=GPIO_NOPULL
+PI3.GPIO_Speed_High_Default=GPIO_SPEED_FREQ_VERY_HIGH
+PI3.Locked=true
+PI3.Signal=FMC_D27
+PI4.GPIOParameters=GPIO_PuPd,GPIO_Speed_High_Default,GPIO_Label,GPIO_Mode
+PI4.GPIO_Label=FMC_NBL2 [MT48LC4M32B2B5-6A_DQM2]
+PI4.GPIO_Mode=GPIO_MODE_AF_PP
+PI4.GPIO_PuPd=GPIO_NOPULL
+PI4.GPIO_Speed_High_Default=GPIO_SPEED_FREQ_VERY_HIGH
+PI4.Locked=true
+PI4.Signal=FMC_NBL2
+PI5.GPIOParameters=GPIO_PuPd,GPIO_Speed_High_Default,GPIO_Label,GPIO_Mode
+PI5.GPIO_Label=FMC_NBL3 [MT48LC4M32B2B5-6A_DQM3]
+PI5.GPIO_Mode=GPIO_MODE_AF_PP
+PI5.GPIO_PuPd=GPIO_NOPULL
+PI5.GPIO_Speed_High_Default=GPIO_SPEED_FREQ_VERY_HIGH
+PI5.Locked=true
+PI5.Signal=FMC_NBL3
+PI6.GPIOParameters=GPIO_PuPd,GPIO_Speed_High_Default,GPIO_Label,GPIO_Mode
+PI6.GPIO_Label=D28
+PI6.GPIO_Mode=GPIO_MODE_AF_PP
+PI6.GPIO_PuPd=GPIO_NOPULL
+PI6.GPIO_Speed_High_Default=GPIO_SPEED_FREQ_VERY_HIGH
+PI6.Locked=true
+PI6.Signal=FMC_D28
+PI7.GPIOParameters=GPIO_PuPd,GPIO_Speed_High_Default,GPIO_Label,GPIO_Mode
+PI7.GPIO_Label=D29
+PI7.GPIO_Mode=GPIO_MODE_AF_PP
+PI7.GPIO_PuPd=GPIO_NOPULL
+PI7.GPIO_Speed_High_Default=GPIO_SPEED_FREQ_VERY_HIGH
+PI7.Locked=true
+PI7.Signal=FMC_D29
+PI9.GPIOParameters=GPIO_PuPd,GPIO_Speed_High_Default,GPIO_Label,GPIO_Mode
+PI9.GPIO_Label=D30
+PI9.GPIO_Mode=GPIO_MODE_AF_PP
+PI9.GPIO_PuPd=GPIO_NOPULL
+PI9.GPIO_Speed_High_Default=GPIO_SPEED_FREQ_VERY_HIGH
+PI9.Locked=true
+PI9.Signal=FMC_D30
+PJ2.GPIOParameters=GPIO_Speed,GPIO_PuPd,GPIO_Label,GPIO_Mode
+PJ2.GPIO_Label=DSI_TE
+PJ2.GPIO_Mode=GPIO_MODE_AF_PP
+PJ2.GPIO_PuPd=GPIO_NOPULL
+PJ2.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH
+PJ2.Locked=true
+PJ2.Mode=DSIHost_Adapted_TE
+PJ2.Signal=DSIHOST_TE
+PJ5.GPIOParameters=GPIO_PuPd,GPIO_Label,GPIO_ModeDefaultEXTI
+PJ5.GPIO_Label=LCD_INT
+PJ5.GPIO_ModeDefaultEXTI=GPIO_MODE_IT_RISING
+PJ5.GPIO_PuPd=GPIO_NOPULL
+PJ5.Locked=true
+PJ5.Signal=GPXTI5
+PK3.GPIOParameters=GPIO_Speed,GPIO_PuPd,GPIO_Label,GPIO_ModeDefaultOutputPP
+PK3.GPIO_Label=LED4 [Blue]
+PK3.GPIO_ModeDefaultOutputPP=GPIO_MODE_OUTPUT_OD
+PK3.GPIO_PuPd=GPIO_NOPULL
+PK3.GPIO_Speed=GPIO_SPEED_FREQ_LOW
+PK3.Locked=true
+PK3.Signal=GPIO_Output
+PinOutPanel.CurrentBGAView=Top
+PinOutPanel.RotationAngle=0
+ProjectManager.AskForMigrate=true
+ProjectManager.BackupPrevious=false
+ProjectManager.CompilerOptimize=6
+ProjectManager.ComputerToolchain=false
+ProjectManager.CoupleFile=true
+ProjectManager.CustomerFirmwarePackage=
+ProjectManager.DefaultFWLocation=true
+ProjectManager.DeletePrevious=true
+ProjectManager.DeviceId=STM32F469NIHx
+ProjectManager.FirmwarePackage=STM32Cube FW_F4 V1.27.0
+ProjectManager.FreePins=false
+ProjectManager.HalAssertFull=false
+ProjectManager.HeapSize=0x200
+ProjectManager.KeepUserCode=true
+ProjectManager.LastFirmware=true
+ProjectManager.LibraryCopy=1
+ProjectManager.MainLocation=Core/Src
+ProjectManager.NoMain=false
+ProjectManager.PreviousToolchain=
+ProjectManager.ProjectBuild=false
+ProjectManager.ProjectFileName=eez-flow-template-stm32f469i-disco.ioc
+ProjectManager.ProjectName=eez-flow-template-stm32f469i-disco
+ProjectManager.RegisterCallBack=
+ProjectManager.StackSize=0x400
+ProjectManager.TargetToolchain=STM32CubeIDE
+ProjectManager.ToolChainLocation=
+ProjectManager.UnderRoot=true
+ProjectManager.functionlistsort=1-SystemClock_Config-RCC-false-HAL-false,2-MX_GPIO_Init-GPIO-false-HAL-true,3-MX_CRC_Init-CRC-false-HAL-true,4-MX_DMA2D_Init-DMA2D-false-HAL-true,5-MX_DSIHOST_DSI_Init-DSIHOST-false-HAL-true,6-MX_FMC_Init-FMC-false-HAL-true,7-MX_I2C1_Init-I2C1-false-HAL-true,8-MX_I2C2_Init-I2C2-false-HAL-true,9-MX_LTDC_Init-LTDC-false-HAL-true,10-MX_QUADSPI_Init-QUADSPI-false-HAL-true,11-MX_SAI1_Init-SAI1-false-HAL-true,12-MX_SDIO_SD_Init-SDIO-false-HAL-true,13-MX_TIM1_Init-TIM1-false-HAL-true,14-MX_USART3_UART_Init-USART3-false-HAL-true,15-MX_USART6_UART_Init-USART6-false-HAL-true,16-MX_FATFS_Init-FATFS-false-HAL-false,17-MX_USB_HOST_Init-USB_HOST-false-HAL-false
+QUADSPI.ChipSelectHighTime=QSPI_CS_HIGH_TIME_5_CYCLE
+QUADSPI.ClockPrescaler=1
+QUADSPI.FifoThreshold=1
+QUADSPI.FlashSize=24
+QUADSPI.IPParameters=FifoThreshold,FlashSize,ClockPrescaler,SampleShifting,ChipSelectHighTime
+QUADSPI.SampleShifting=QSPI_SAMPLE_SHIFTING_HALFCYCLE
+RCC.AHBFreq_Value=180000000
+RCC.APB1CLKDivider=RCC_HCLK_DIV4
+RCC.APB1Freq_Value=45000000
+RCC.APB1TimFreq_Value=90000000
+RCC.APB2CLKDivider=RCC_HCLK_DIV2
+RCC.APB2Freq_Value=90000000
+RCC.APB2TimFreq_Value=180000000
+RCC.CortexFreq_Value=180000000
+RCC.DSIFreq_Value=62500000
+RCC.DSITXEscFreq_Value=15625000
+RCC.EthernetFreq_Value=180000000
+RCC.FCLKCortexFreq_Value=180000000
+RCC.FamilyName=M
+RCC.HCLKFreq_Value=180000000
+RCC.HSE_VALUE=8000000
+RCC.I2SFreq_Value=96000000
+RCC.IPParameters=AHBFreq_Value,APB1CLKDivider,APB1Freq_Value,APB1TimFreq_Value,APB2CLKDivider,APB2Freq_Value,APB2TimFreq_Value,CortexFreq_Value,DSIFreq_Value,DSITXEscFreq_Value,EthernetFreq_Value,FCLKCortexFreq_Value,FamilyName,HCLKFreq_Value,HSE_VALUE,I2SFreq_Value,LCDTFTFreq_Value,MCO2PinFreq_Value,PLLCLKFreq_Value,PLLDSIFreq_Value,PLLDSIIDF,PLLDSINDIV,PLLDSIVCOFreq_Value,PLLI2SQCLKFreq_Value,PLLI2SRCLKFreq_Value,PLLM,PLLN,PLLQ,PLLQCLKFreq_Value,PLLR,PLLRCLKFreq_Value,PLLRFreq_Value,PLLSAIP,PLLSAIPCLKFreq_Value,PLLSAIQ,PLLSAIQCLKFreq_Value,PLLSAIRCLKFreq_Value,PLLSAIRDiv,RTCFreq_Value,RTCHSEDivFreq_Value,SAIAFreq_Value,SAIBFreq_Value,SDIOFreq_Value,SYSCLKFreq_VALUE,SYSCLKSource,USBCLockSelection,USBFreq_Value,VCOI2SOutputFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value,VCOSAIOutputFreq_Value
+RCC.LCDTFTFreq_Value=24000000
+RCC.MCO2PinFreq_Value=180000000
+RCC.PLLCLKFreq_Value=180000000
+RCC.PLLDSIFreq_Value=500000000
+RCC.PLLDSIIDF=DSI_PLL_IN_DIV2
+RCC.PLLDSINDIV=125
+RCC.PLLDSIVCOFreq_Value=1000000000
+RCC.PLLI2SQCLKFreq_Value=48000000
+RCC.PLLI2SRCLKFreq_Value=96000000
+RCC.PLLM=8
+RCC.PLLN=360
+RCC.PLLQ=7
+RCC.PLLQCLKFreq_Value=51428571.428571425
+RCC.PLLR=6
+RCC.PLLRCLKFreq_Value=60000000
+RCC.PLLRFreq_Value=60000000
+RCC.PLLSAIP=RCC_PLLSAIP_DIV4
+RCC.PLLSAIPCLKFreq_Value=48000000
+RCC.PLLSAIQ=2
+RCC.PLLSAIQCLKFreq_Value=96000000
+RCC.PLLSAIRCLKFreq_Value=96000000
+RCC.PLLSAIRDiv=RCC_PLLSAIDIVR_4
+RCC.RTCFreq_Value=32000
+RCC.RTCHSEDivFreq_Value=4000000
+RCC.SAIAFreq_Value=96000000
+RCC.SAIBFreq_Value=96000000
+RCC.SDIOFreq_Value=48000000
+RCC.SYSCLKFreq_VALUE=180000000
+RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK
+RCC.USBCLockSelection=RCC_CLK48CLKSOURCE_PLLSAIP
+RCC.USBFreq_Value=48000000
+RCC.VCOI2SOutputFreq_Value=192000000
+RCC.VCOInputFreq_Value=1000000
+RCC.VCOOutputFreq_Value=360000000
+RCC.VCOSAIOutputFreq_Value=192000000
+SAI1.ErrorAudioFreq-SAI_A_MasterWithClock=-2.34 %
+SAI1.IPParameters=Instance-SAI_A_MasterWithClock,MClockEnable-SAI_A_MasterWithClock,RealAudioFreq-SAI_A_MasterWithClock,ErrorAudioFreq-SAI_A_MasterWithClock,VirtualMode-SAI_A_MasterWithClock,Synchro-SAI_A_MasterWithClock
+SAI1.Instance-SAI_A_MasterWithClock=SAI$Index_Block_A
+SAI1.MClockEnable-SAI_A_MasterWithClock=SAI_MASTERCLOCK_ENABLE
+SAI1.RealAudioFreq-SAI_A_MasterWithClock=187.5 KHz
+SAI1.Synchro-SAI_A_MasterWithClock=SAI_ASYNCHRONOUS
+SAI1.VirtualMode-SAI_A_MasterWithClock=VM_MASTER
+SDIO.IPParameters=WideMode
+SDIO.WideMode=SDIO_BUS_WIDE_4B
+SH.FMC_A0.0=FMC_A0,12b-sda1
+SH.FMC_A0.ConfNb=1
+SH.FMC_A1.0=FMC_A1,12b-sda1
+SH.FMC_A1.ConfNb=1
+SH.FMC_A10.0=FMC_A10,12b-sda1
+SH.FMC_A10.ConfNb=1
+SH.FMC_A11.0=FMC_A11,12b-sda1
+SH.FMC_A11.ConfNb=1
+SH.FMC_A14_BA0.0=FMC_BA0,FourSdramBanks1
+SH.FMC_A14_BA0.ConfNb=1
+SH.FMC_A15_BA1.0=FMC_BA1,FourSdramBanks1
+SH.FMC_A15_BA1.ConfNb=1
+SH.FMC_A2.0=FMC_A2,12b-sda1
+SH.FMC_A2.ConfNb=1
+SH.FMC_A3.0=FMC_A3,12b-sda1
+SH.FMC_A3.ConfNb=1
+SH.FMC_A4.0=FMC_A4,12b-sda1
+SH.FMC_A4.ConfNb=1
+SH.FMC_A5.0=FMC_A5,12b-sda1
+SH.FMC_A5.ConfNb=1
+SH.FMC_A6.0=FMC_A6,12b-sda1
+SH.FMC_A6.ConfNb=1
+SH.FMC_A7.0=FMC_A7,12b-sda1
+SH.FMC_A7.ConfNb=1
+SH.FMC_A8.0=FMC_A8,12b-sda1
+SH.FMC_A8.ConfNb=1
+SH.FMC_A9.0=FMC_A9,12b-sda1
+SH.FMC_A9.ConfNb=1
+SH.FMC_D0_DA0.0=FMC_D0,sd-32b-d1
+SH.FMC_D0_DA0.ConfNb=1
+SH.FMC_D10_DA10.0=FMC_D10,sd-32b-d1
+SH.FMC_D10_DA10.ConfNb=1
+SH.FMC_D11_DA11.0=FMC_D11,sd-32b-d1
+SH.FMC_D11_DA11.ConfNb=1
+SH.FMC_D12_DA12.0=FMC_D12,sd-32b-d1
+SH.FMC_D12_DA12.ConfNb=1
+SH.FMC_D13_DA13.0=FMC_D13,sd-32b-d1
+SH.FMC_D13_DA13.ConfNb=1
+SH.FMC_D14_DA14.0=FMC_D14,sd-32b-d1
+SH.FMC_D14_DA14.ConfNb=1
+SH.FMC_D15_DA15.0=FMC_D15,sd-32b-d1
+SH.FMC_D15_DA15.ConfNb=1
+SH.FMC_D16.0=FMC_D16,sd-32b-d1
+SH.FMC_D16.ConfNb=1
+SH.FMC_D17.0=FMC_D17,sd-32b-d1
+SH.FMC_D17.ConfNb=1
+SH.FMC_D18.0=FMC_D18,sd-32b-d1
+SH.FMC_D18.ConfNb=1
+SH.FMC_D19.0=FMC_D19,sd-32b-d1
+SH.FMC_D19.ConfNb=1
+SH.FMC_D1_DA1.0=FMC_D1,sd-32b-d1
+SH.FMC_D1_DA1.ConfNb=1
+SH.FMC_D20.0=FMC_D20,sd-32b-d1
+SH.FMC_D20.ConfNb=1
+SH.FMC_D21.0=FMC_D21,sd-32b-d1
+SH.FMC_D21.ConfNb=1
+SH.FMC_D22.0=FMC_D22,sd-32b-d1
+SH.FMC_D22.ConfNb=1
+SH.FMC_D23.0=FMC_D23,sd-32b-d1
+SH.FMC_D23.ConfNb=1
+SH.FMC_D24.0=FMC_D24,sd-32b-d1
+SH.FMC_D24.ConfNb=1
+SH.FMC_D25.0=FMC_D25,sd-32b-d1
+SH.FMC_D25.ConfNb=1
+SH.FMC_D26.0=FMC_D26,sd-32b-d1
+SH.FMC_D26.ConfNb=1
+SH.FMC_D27.0=FMC_D27,sd-32b-d1
+SH.FMC_D27.ConfNb=1
+SH.FMC_D28.0=FMC_D28,sd-32b-d1
+SH.FMC_D28.ConfNb=1
+SH.FMC_D29.0=FMC_D29,sd-32b-d1
+SH.FMC_D29.ConfNb=1
+SH.FMC_D2_DA2.0=FMC_D2,sd-32b-d1
+SH.FMC_D2_DA2.ConfNb=1
+SH.FMC_D30.0=FMC_D30,sd-32b-d1
+SH.FMC_D30.ConfNb=1
+SH.FMC_D31.0=FMC_D31,sd-32b-d1
+SH.FMC_D31.ConfNb=1
+SH.FMC_D3_DA3.0=FMC_D3,sd-32b-d1
+SH.FMC_D3_DA3.ConfNb=1
+SH.FMC_D4_DA4.0=FMC_D4,sd-32b-d1
+SH.FMC_D4_DA4.ConfNb=1
+SH.FMC_D5_DA5.0=FMC_D5,sd-32b-d1
+SH.FMC_D5_DA5.ConfNb=1
+SH.FMC_D6_DA6.0=FMC_D6,sd-32b-d1
+SH.FMC_D6_DA6.ConfNb=1
+SH.FMC_D7_DA7.0=FMC_D7,sd-32b-d1
+SH.FMC_D7_DA7.ConfNb=1
+SH.FMC_D8_DA8.0=FMC_D8,sd-32b-d1
+SH.FMC_D8_DA8.ConfNb=1
+SH.FMC_D9_DA9.0=FMC_D9,sd-32b-d1
+SH.FMC_D9_DA9.ConfNb=1
+SH.FMC_NBL0.0=FMC_NBL0,Sd4ByteEnable1
+SH.FMC_NBL0.ConfNb=1
+SH.FMC_NBL1.0=FMC_NBL1,Sd4ByteEnable1
+SH.FMC_NBL1.ConfNb=1
+SH.FMC_NBL2.0=FMC_NBL2,Sd4ByteEnable1
+SH.FMC_NBL2.ConfNb=1
+SH.FMC_NBL3.0=FMC_NBL3,Sd4ByteEnable1
+SH.FMC_NBL3.ConfNb=1
+SH.FMC_SDCLK.0=FMC_SDCLK,12b-sda1
+SH.FMC_SDCLK.ConfNb=1
+SH.FMC_SDNCAS.0=FMC_SDNCAS,12b-sda1
+SH.FMC_SDNCAS.ConfNb=1
+SH.FMC_SDNRAS.0=FMC_SDNRAS,12b-sda1
+SH.FMC_SDNRAS.ConfNb=1
+SH.FMC_SDNWE.0=FMC_SDNWE,12b-sda1
+SH.FMC_SDNWE.ConfNb=1
+SH.GPXTI5.0=GPIO_EXTI5
+SH.GPXTI5.ConfNb=1
+SH.GPXTI7.0=GPIO_EXTI7
+SH.GPXTI7.ConfNb=1
+SH.S_TIM4_CH2.0=TIM4_CH2
+SH.S_TIM4_CH2.ConfNb=1
+USART3.IPParameters=VirtualMode
+USART3.VirtualMode=VM_ASYNC
+USART6.IPParameters=VirtualMode
+USART6.VirtualMode=VM_ASYNC
+USB_HOST.BSP.number=1
+USB_HOST.IPParameters=VirtualModeFS,USBH_HandleTypeDef-CDC_FS
+USB_HOST.USBH_HandleTypeDef-CDC_FS=hUsbHostFS
+USB_HOST.VirtualModeFS=Cdc
+USB_HOST0.BSP.STBoard=false
+USB_HOST0.BSP.api=UnknownBspDriver
+USB_HOST0.BSP.component=
+USB_HOST0.BSP.condition=
+USB_HOST0.BSP.instance=PB2/BOOT1
+USB_HOST0.BSP.ip=GPIO
+USB_HOST0.BSP.mode=Output
+USB_HOST0.BSP.name=Drive_VBUS_FS
+USB_HOST0.BSP.semaphore=
+USB_HOST0.BSP.solution=PB2/BOOT1
+USB_OTG_FS.IPParameters=phy_itface,VirtualMode
+USB_OTG_FS.VirtualMode=Host_Only
+USB_OTG_FS.phy_itface=HCD_PHY_EMBEDDED
+VP_CRC_VS_CRC.Mode=CRC_Activate
+VP_CRC_VS_CRC.Signal=CRC_VS_CRC
+VP_DMA2D_VS_DMA2D.Mode=DMA2D_Activate
+VP_DMA2D_VS_DMA2D.Signal=DMA2D_VS_DMA2D
+VP_FATFS_VS_SDIO.Mode=SDIO
+VP_FATFS_VS_SDIO.Signal=FATFS_VS_SDIO
+VP_FREERTOS_VS_CMSIS_V2.Mode=CMSIS_V2
+VP_FREERTOS_VS_CMSIS_V2.Signal=FREERTOS_VS_CMSIS_V2
+VP_LTDC_DSIMode.Mode=RGB888
+VP_LTDC_DSIMode.Signal=LTDC_DSIMode
+VP_SYS_VS_tim6.Mode=TIM6
+VP_SYS_VS_tim6.Signal=SYS_VS_tim6
+VP_TIM1_VS_ClockSourceINT.Mode=Internal
+VP_TIM1_VS_ClockSourceINT.Signal=TIM1_VS_ClockSourceINT
+VP_USB_HOST_VS_USB_HOST_CDC_FS.Mode=CDC_FS
+VP_USB_HOST_VS_USB_HOST_CDC_FS.Signal=USB_HOST_VS_USB_HOST_CDC_FS
+board=STM32F469I-DISCO
+boardIOC=true
+isbadioc=false